From 2cf60427e9a5fcc79aa29619afa9c2af6def2a70 Mon Sep 17 00:00:00 2001 From: AndrasZiegler Date: Thu, 21 Nov 2024 10:35:47 +0100 Subject: [PATCH 1/7] 7 extend documentation (#8) * updated current workflow naming convention, added truffhog scan workflow * added Code of conduct and Contribbution guideline documents * changed SQ workflow to manual only --- .github/CONTRIBUTING.md | 116 ++++++++++++++ ...mmit.yml => 00-Check.-Code-Convention.yml} | 3 +- ...cla_signature.yml => 01-CLA-Assistant.yml} | 2 +- ...e_build_test.yml => 02-Build-Firmware.yml} | 3 +- ...onarqube.yml => 03-SonarQube-Analysis.yml} | 6 +- .../workflows/04-TruffleHog-Security-Scan.yml | 19 +++ CODE_OF_CONDUCT.md | 143 ++++++++++++++++++ 7 files changed, 285 insertions(+), 7 deletions(-) create mode 100644 .github/CONTRIBUTING.md rename .github/workflows/{precommit.yml => 00-Check.-Code-Convention.yml} (98%) rename .github/workflows/{cla_signature.yml => 01-CLA-Assistant.yml} (99%) rename .github/workflows/{software_build_test.yml => 02-Build-Firmware.yml} (98%) rename .github/workflows/{sonarqube.yml => 03-SonarQube-Analysis.yml} (92%) create mode 100644 .github/workflows/04-TruffleHog-Security-Scan.yml create mode 100644 CODE_OF_CONDUCT.md diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md new file mode 100644 index 0000000..adbfb70 --- /dev/null +++ b/.github/CONTRIBUTING.md @@ -0,0 +1,116 @@ +# Contributing to a SiliconLabs open source project + +You want to contribute to a Silicon Labs Open Source project? Welcome! Please read this document to understand what you can do: + * [Help Others](#help-others) + * [Analyze Issues](#analyze-issues) + * [Report an Issue](#report-an-issue) + * [Contribute Code](#contribute-code) + +## Help Others + +You can help the Silicon Labs open source projects by helping others who use them and need support. + +## Analyze Issues + +Analyzing issue reports can be a lot of effort. Any help is welcome! +Go to [Issue tracker](https://github.com/SiliconLabsSoftware/bluetooth-AoA-example/issues?q=is%3Aopen+is%3Aissue) and find an open issue which needs additional work or a bugfix (e.g. issues labeled with "help wanted" or "bug"). + +Additional work could include any further information, or a gist, or it might be a hint that helps understanding the issue. Maybe you can even find and [contribute](#contribute-code) a bugfix? + +## Report an Issue + +If you find a bug - behavior of Silicon Labs Open Source projects code contradicting your expectation - you are welcome to report it. +We can only handle well-reported, actual bugs, so please follow the guidelines below. + +Once you have familiarized with the guidelines, you can go to the [Create an issue](https://github.com/SiliconLabsSoftware/bluetooth-AoA-example/issues/new) to report the issue. + +### Quick Checklist for Bug Reports + +Issue report checklist: + * Real, current bug + * No duplicate + * Reproducible + * Good summary + * Well-documented + * Minimal example + + +### Issue handling process + +When an issue is reported, a committer will look at it and either confirm it as a real issue, close it if it is not an issue, or ask for more details. + +An issue that is about a real bug is closed as soon as the fix is committed. + + +### Reporting Security Issues + +If you find a security issue, please act responsibly and report it not in the public issue tracker, but directly to the CODE_OWNERS, so we can fix it before it can be exploited. + + +### Usage of Labels + +GitHub offers labels to categorize issues. We defined the following labels so far: + +Labels for issue categories: + * bug: this issue is a bug in the code + * feature: this issue is a request for a new functionality or an enhancement request + +Status of open issues: + * help wanted: the feature request is approved and you are invited to contribute + +Status/resolution of closed issues: + * wontfix: while acknowledged to be an issue, a fix cannot or will not be provided + +The labels can only be set and modified by committers. + + +### Issue Reporting Disclaimer + +We want to improve the quality of Silicon Labs Open Source projects and good bug reports are welcome! But our capacity is limited, thus we reserve the right to close or to not process insufficient bug reports in favor of those which are very cleanly documented and easy to reproduce. Even though we would like to solve each well-documented issue, there is always the chance that it will not happen - remember: these projects are open source and comes without warranty. + +Bug report analysis support is very welcome! (e.g. pre-analysis or proposing solutions) + + +## Contribute Code + +You are welcome to contribute code to Silicon Labs Open Source projects in order to fix bugs or to implement new features. + +There are three important things to know: + +1. You must be aware that you need to sign a [CLA](https://en.wikipedia.org/wiki/Contributor_License_Agreement) in order for your contribution to be accepted. This is common practice in all major Open Source projects. +2. There are **several requirements regarding code style, quality, and product standards** which need to be met (we also have to follow them). The respective section below gives more details on the coding guidelines. + + +### Contribution Content Guidelines + +These are some of the rules we try to follow: + +- Apply a clean coding style adapted to the surrounding code, even though we are aware the existing code is not fully clean +- Use (4)spaces for indentation (except if the modified file consistently uses tabs) +- Use variable naming conventions like in the other files you are seeing (camelcase) +- No console.log() - use logging service +- Run the ESLint code check and make it succeed +- Comment your code where it gets non-trivial +- Keep an eye on performance and memory consumption, properly destroy objects when not used anymore +- Write a unit test +- Do not do any incompatible changes, especially do not modify the name or behavior of public API methods or properties + +### How to contribute - the Process + +1. Make sure the change would be welcome (e.g. a bugfix or a useful feature); best do so by proposing it in a GitHub issue +2. Create a branch forking the cla-assistant repository and do your change +3. Commit and push your changes on that branch +4. In the commit message + - Describe the problem you fix with this change. + - Describe the effect that this change has from a user's point of view. App crashes and lockups are pretty convincing for example, but not all bugs are that obvious and should be mentioned in the text. + - Describe the technical details of what you changed. It is important to describe the change in a most understandable way so the reviewer is able to verify that the code is behaving as you intend it to. +5. If your change fixes an issue reported at GitHub, add the following line to the commit message: + - ```Fixes #(issueNumber)``` + - Do NOT add a colon after "Fixes" - this prevents automatic closing. +6. Create a Pull Request +7. Follow the link posted by the Silicon Labs Open Source projects to your pull request and accept it, as described in detail above. +8. Wait for our code review and approval, possibly enhancing your change on request + - Note that the Silicon Labs Open Source projects developers also have their regular duties, so depending on the required effort for reviewing, testing and clarification this may take a while + +9. Once the change has been approved we will inform you in a comment +10. We will close the pull request, feel free to delete the now obsolete branch \ No newline at end of file diff --git a/.github/workflows/precommit.yml b/.github/workflows/00-Check.-Code-Convention.yml similarity index 98% rename from .github/workflows/precommit.yml rename to .github/workflows/00-Check.-Code-Convention.yml index 29b01cf..7b6d95f 100644 --- a/.github/workflows/precommit.yml +++ b/.github/workflows/00-Check.-Code-Convention.yml @@ -1,4 +1,4 @@ -name: Pre Commit check +name: 00-Check.-Code-Convention on: push: branches-ignore: @@ -7,6 +7,7 @@ on: pull_request: branches: - main + - develop - "release/**" workflow_dispatch: inputs: diff --git a/.github/workflows/cla_signature.yml b/.github/workflows/01-CLA-Assistant.yml similarity index 99% rename from .github/workflows/cla_signature.yml rename to .github/workflows/01-CLA-Assistant.yml index b7b5ebe..1df289b 100644 --- a/.github/workflows/cla_signature.yml +++ b/.github/workflows/01-CLA-Assistant.yml @@ -1,4 +1,4 @@ -name: "CLA Assistant" +name: 01-CLA-Assistant on: issue_comment: types: [created] diff --git a/.github/workflows/software_build_test.yml b/.github/workflows/02-Build-Firmware.yml similarity index 98% rename from .github/workflows/software_build_test.yml rename to .github/workflows/02-Build-Firmware.yml index 9da6c79..35d1331 100644 --- a/.github/workflows/software_build_test.yml +++ b/.github/workflows/02-Build-Firmware.yml @@ -1,8 +1,9 @@ -name: Build the software +name: 02-Build-Firmware on: pull_request: branches: - main + - develop workflow_dispatch: env: ARCH: x86_64 diff --git a/.github/workflows/sonarqube.yml b/.github/workflows/03-SonarQube-Analysis.yml similarity index 92% rename from .github/workflows/sonarqube.yml rename to .github/workflows/03-SonarQube-Analysis.yml index 5784b5d..f9e1f08 100644 --- a/.github/workflows/sonarqube.yml +++ b/.github/workflows/03-SonarQube-Analysis.yml @@ -1,9 +1,7 @@ -name: SonarQube Analysis +name: 03-SonarQube-Analysis on: - pull_request: - branches: - - main + #It is an internal tool, it can only ran a self hosted runner. Currently it can be triggered only manually. workflow_dispatch: diff --git a/.github/workflows/04-TruffleHog-Security-Scan.yml b/.github/workflows/04-TruffleHog-Security-Scan.yml new file mode 100644 index 0000000..478e0dd --- /dev/null +++ b/.github/workflows/04-TruffleHog-Security-Scan.yml @@ -0,0 +1,19 @@ +name: 04-TruffleHog-Security-Scan +on: + pull_request: + branches: + - main + - develop + workflow_dispatch: +jobs: + trufflehog_scan: + runs-on: ubuntu-latest + steps: + - name: Checkout code + uses: actions/checkout@v4 + with: + fetch-depth: 0 + - name: Secret Scanning + uses: trufflesecurity/trufflehog@v3.84.0 + with: + extra_args: --only-verified \ No newline at end of file diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..9b4c6b5 --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1,143 @@ +# Silicon Labs open source projects Code of Conduct + +Silicon Labs open source projects Code of Conduct applies to all those contributing +to, participating in, or maintaining the Silicon Labs open source projects, +including Connectivity Standards Alliance members and non-members. + +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, caste, color, religion, or sexual +identity and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +- Demonstrating empathy and kindness toward other people +- Being respectful of differing opinions, viewpoints, and experiences +- Giving and gracefully accepting constructive feedback +- Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +- Focusing on what is best not just for us as individuals, but for the overall + community +- Respecting people's privacy and private product plans + +Examples of unacceptable behavior include: + +- The use of sexualized language or imagery, and sexual attention or advances + of any kind +- Trolling, insulting or derogatory comments, and personal or political + attacks +- Public or private harassment +- Publishing others' private information, such as a physical or email address, + without their explicit permission +- Other conduct which could reasonably be considered inappropriate in a + professional setting +- Disclosure of private information, unreleased products +- Disclosure of unreleased specification information outside of Connectivity + Standards Alliance approved forums + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported to the community leaders responsible for enforcement at +help@csa-iot.org. All submissions will be reviewed and investigated promptly and +fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series of +actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or permanent +ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within the +community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.1, available at +[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1]. + +Community Impact Guidelines were inspired by [Mozilla's code of conduct +enforcement ladder][mozilla coc]. + +For answers to common questions about this code of conduct, see the FAQ at +[https://www.contributor-covenant.org/faq][faq]. Translations are available at +[https://www.contributor-covenant.org/translations][translations]. + +[homepage]: https://www.contributor-covenant.org +[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html +[mozilla coc]: https://github.com/mozilla/diversity +[faq]: https://www.contributor-covenant.org/faq +[translations]: https://www.contributor-covenant.org/translations \ No newline at end of file From 347324cb896a8439538c33e143626d9c983758e8 Mon Sep 17 00:00:00 2001 From: AndrasZiegler Date: Thu, 21 Nov 2024 15:34:01 +0100 Subject: [PATCH 2/7] Updated CLA assistant workflow (#9) * modified cla db repo branch * fixed cla.dm path * updated cla assistant custom messages --- .github/workflows/01-CLA-Assistant.yml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/01-CLA-Assistant.yml b/.github/workflows/01-CLA-Assistant.yml index 1df289b..d2ac892 100644 --- a/.github/workflows/01-CLA-Assistant.yml +++ b/.github/workflows/01-CLA-Assistant.yml @@ -28,15 +28,15 @@ jobs: PERSONAL_ACCESS_TOKEN: ${{ secrets.PERSONAL_ACCESS_TOKEN }} with: path-to-signatures: 'cla_signatures_db.json' - path-to-document: 'cla.md' + path-to-document: 'https://github.com/SiliconLabsSoftware/bluetooth-AoA-example/blob/main/cla.md' # branch should not be protected - branch: 'main' + branch: 'test' allowlist: user1,bot* # the followings are the optional inputs - If the optional inputs are not given, then default values will be taken remote-organization-name: 'SiliconLabsWorkflows' remote-repository-name: 'private-central-cla' - create-file-commit-message: 'For example: Creating file for storing CLA Signatures' - signed-commit-message: 'For example: $contributorName has signed the CLA in $owner/$repo#$pullRequestNo' + create-file-commit-message: 'Created the CLA database file. CLA Assistant Lite bot created this file.' + signed-commit-message: '$contributorName has signed the CLA in $owner/$repo#$pullRequestNo' #custom-notsigned-prcomment: 'pull request comment with Introductory message to ask new contributors to sign' #custom-pr-sign-comment: 'The signature to be committed in order to sign the CLA' #custom-allsigned-prcomment: 'pull request comment when all contributors has signed, defaults to **CLA Assistant Lite bot** All Contributors have signed the CLA.' From 31305fcde30217fb25f0cce91eaf9e8b33d3c333 Mon Sep 17 00:00:00 2001 From: silabs-akosj <146345861+silabs-akosj@users.noreply.github.com> Date: Thu, 21 Nov 2024 15:50:15 +0100 Subject: [PATCH 3/7] Update readme, link to other BT examples (#11) --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 496d014..7277226 100644 --- a/README.md +++ b/README.md @@ -20,6 +20,9 @@ The host receives it, processes it and logs it to the standard output. Data is provided in JSON format and depending on the actual configuration it will be raw I/Q sample or angle information. The angle information is calculated by the host with MVP (Matrix Vector Processor) from the I/Q samples. +If you are interested in other Bluethooth examples you can find more here: +[Bluetooth application examples](https://github.com/SiliconLabs/bluetooth_applications) + ### NCP firmware This is a simple locator NCP project, only change is that the VCOM is disabled (so the UART line can be used directly). From a02ca9b51440fee3888f71665ce1f55905b5feb1 Mon Sep 17 00:00:00 2001 From: silabs-akosj <146345861+silabs-akosj@users.noreply.github.com> Date: Fri, 22 Nov 2024 13:39:54 +0100 Subject: [PATCH 4/7] [12] there is a typo in the text (#13) The typos have been fixed! --- ...-Check.-Code-Convention.yml => 00-Check-Code-Convention.yml} | 2 +- .github/workflows/02-Build-Firmware.yml | 2 +- README.md | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) rename .github/workflows/{00-Check.-Code-Convention.yml => 00-Check-Code-Convention.yml} (98%) diff --git a/.github/workflows/00-Check.-Code-Convention.yml b/.github/workflows/00-Check-Code-Convention.yml similarity index 98% rename from .github/workflows/00-Check.-Code-Convention.yml rename to .github/workflows/00-Check-Code-Convention.yml index 7b6d95f..de3fa66 100644 --- a/.github/workflows/00-Check.-Code-Convention.yml +++ b/.github/workflows/00-Check-Code-Convention.yml @@ -1,4 +1,4 @@ -name: 00-Check.-Code-Convention +name: 00-Check-Code-Convention on: push: branches-ignore: diff --git a/.github/workflows/02-Build-Firmware.yml b/.github/workflows/02-Build-Firmware.yml index 35d1331..99f9115 100644 --- a/.github/workflows/02-Build-Firmware.yml +++ b/.github/workflows/02-Build-Firmware.yml @@ -11,7 +11,7 @@ env: ARM_GCC_DIR: "/opt/gcc-arm-none-eabi/" ARM_GCC_URL: "https://developer.arm.com/-/media/Files/downloads/gnu/12.2.rel1/binrel/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi.tar.xz" jobs: - SW_build: + FW_build: runs-on: ubuntu-22.04 steps: - name: Trigger diff --git a/README.md b/README.md index 7277226..9682c98 100644 --- a/README.md +++ b/README.md @@ -20,7 +20,7 @@ The host receives it, processes it and logs it to the standard output. Data is provided in JSON format and depending on the actual configuration it will be raw I/Q sample or angle information. The angle information is calculated by the host with MVP (Matrix Vector Processor) from the I/Q samples. -If you are interested in other Bluethooth examples you can find more here: +If you are interested in other Bluetooth examples you can find more here: [Bluetooth application examples](https://github.com/SiliconLabs/bluetooth_applications) ### NCP firmware From bc1fa826870344ee523718b3250366312c6a8f74 Mon Sep 17 00:00:00 2001 From: AndrasZiegler Date: Mon, 25 Nov 2024 16:32:59 +0100 Subject: [PATCH 5/7] 4 cla assistant doesnt store signatures (#14) Moved the CLA assistant signature database into an internal repository. Also now the CLA assistant uses a fork of the source code not the public repo. --- .github/workflows/01-CLA-Assistant.yml | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/.github/workflows/01-CLA-Assistant.yml b/.github/workflows/01-CLA-Assistant.yml index d2ac892..1184aa9 100644 --- a/.github/workflows/01-CLA-Assistant.yml +++ b/.github/workflows/01-CLA-Assistant.yml @@ -20,23 +20,23 @@ jobs: steps: - name: "CLA Assistant" if: (github.event.comment.body == 'recheck' || github.event.comment.body == 'I have read the CLA Document and I hereby sign the CLA') || github.event_name == 'pull_request_target' - uses: contributor-assistant/github-action@v2.6.1 + uses: SiliconLabsWorkflows/cla-assistant@master env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # the below token should have repo scope and must be manually added by you in the repository's secret # This token is required only if you have configured to store the signatures in a remote repository/organization PERSONAL_ACCESS_TOKEN: ${{ secrets.PERSONAL_ACCESS_TOKEN }} with: - path-to-signatures: 'cla_signatures_db.json' - path-to-document: 'https://github.com/SiliconLabsSoftware/bluetooth-AoA-example/blob/main/cla.md' + path-to-signatures: "cla_signatures_db.json" + path-to-document: "https://github.com/SiliconLabsSoftware/bluetooth-AoA-example/blob/main/cla.md" # branch should not be protected - branch: 'test' - allowlist: user1,bot* + branch: 'debug' + allowlist: silabs-*,bot* # the followings are the optional inputs - If the optional inputs are not given, then default values will be taken - remote-organization-name: 'SiliconLabsWorkflows' - remote-repository-name: 'private-central-cla' - create-file-commit-message: 'Created the CLA database file. CLA Assistant Lite bot created this file.' - signed-commit-message: '$contributorName has signed the CLA in $owner/$repo#$pullRequestNo' + remote-organization-name: "SiliconLabsInternal" + remote-repository-name: "contributor-license-agreements" + create-file-commit-message: "Created the CLA database file. CLA Assistant Lite bot created this file." + signed-commit-message: "$contributorName has signed the CLA in $owner/$repo#$pullRequestNo" #custom-notsigned-prcomment: 'pull request comment with Introductory message to ask new contributors to sign' #custom-pr-sign-comment: 'The signature to be committed in order to sign the CLA' #custom-allsigned-prcomment: 'pull request comment when all contributors has signed, defaults to **CLA Assistant Lite bot** All Contributors have signed the CLA.' From cf42fdf34e24680ea3c314046f9afd64da87cf79 Mon Sep 17 00:00:00 2001 From: AndrasZiegler Date: Tue, 26 Nov 2024 13:23:21 +0100 Subject: [PATCH 6/7] Create CODEOWNERS (#16) --- .github/CODEOWNERS | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .github/CODEOWNERS diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS new file mode 100644 index 0000000..22e9729 --- /dev/null +++ b/.github/CODEOWNERS @@ -0,0 +1,2 @@ +# This is a # Default codeowners for the repository +* @AndrasZiegler @silabs-TiborL From e24564c7934a2deedd41b71353c2f431856b2112 Mon Sep 17 00:00:00 2001 From: AndrasZiegler Date: Wed, 27 Nov 2024 13:25:19 +0100 Subject: [PATCH 7/7] Now the code passes the code convention tool check (#18) - updated the code convention test with real output checking. Now the workflow fails when any part of the testsetup fails - Updated the project source code so now all the stages are passing during the code convention test workflow. --- .github/CONTRIBUTING.md | 2 +- .github/Docker_readme.md | 14 +- .github/build-docker-image.sh | 106 +- .github/build-with-docker.sh | 122 +- .github/uncrustify.cfg | 368 +- .../workflows/00-Check-Code-Convention.yml | 11 + .github/workflows/01-CLA-Assistant.yml | 2 +- .../workflows/04-TruffleHog-Security-Scan.yml | 2 +- .gitignore | 36 +- .pre-commit-config.yaml | 52 +- CODE_OF_CONDUCT.md | 2 +- Dockerfile | 186 +- LICENSE | 20 +- Makefile | 22 +- cla.md | 62 +- data_format_sample.c | 160 +- locator_host/Makefile | 34 +- locator_host/app.c | 272 +- locator_host/app.h | 162 +- locator_host/app_log.h | 204 +- locator_host/autogen/RTE_Components.h | 44 +- locator_host/autogen/gatt_db.c | 220 +- locator_host/autogen/gatt_db.h | 44 +- locator_host/autogen/linkerfile.ld | 504 +- locator_host/autogen/sl_bluetooth.c | 86 +- locator_host/autogen/sl_bluetooth.h | 72 +- locator_host/autogen/sl_board_default_init.c | 72 +- locator_host/autogen/sl_component_catalog.h | 54 +- locator_host/autogen/sl_device_init_clocks.c | 120 +- locator_host/autogen/sl_event_handler.c | 184 +- locator_host/autogen/sl_event_handler.h | 30 +- locator_host/autogen/sl_iostream_handles.c | 52 +- locator_host/autogen/sl_iostream_handles.h | 40 +- .../autogen/sl_iostream_init_instances.h | 30 +- locator_host/autogen/sl_simple_com_isr.c | 152 +- locator_host/autogen/sl_uartdrv_init.c | 182 +- locator_host/autogen/sl_uartdrv_instances.h | 70 +- locator_host/bt/CMakeLists.txt | 10 +- locator_host/bt/aoa/CMakeLists.txt | 66 +- locator_host/bt/aoa/README.txt | 6 +- .../bt/aoa/antenna_array/antenna_array.c | 766 +- .../bt/aoa/antenna_array/antenna_array.h | 354 +- .../antenna_array/antenna_array_brd4191a.h | 250 +- locator_host/bt/aoa/aoa_angle/aoa_angle.c | 1422 +- locator_host/bt/aoa/aoa_angle/aoa_angle.h | 440 +- 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23622 ++++++------ .../platform/emlib/src/em_core.c | 2056 +- .../platform/emlib/src/em_dbg.c | 428 +- .../platform/emlib/src/em_emu.c | 8376 ++--- .../platform/emlib/src/em_eusart.c | 2790 +- .../platform/emlib/src/em_gpcrc.c | 276 +- .../platform/emlib/src/em_gpio.c | 904 +- .../platform/emlib/src/em_i2c.c | 1880 +- .../platform/emlib/src/em_iadc.c | 2356 +- .../platform/emlib/src/em_ldma.c | 996 +- .../platform/emlib/src/em_letimer.c | 1370 +- .../platform/emlib/src/em_msc.c | 4150 +- .../platform/emlib/src/em_opamp.c | 1400 +- .../platform/emlib/src/em_pcnt.c | 2134 +- .../platform/emlib/src/em_prs.c | 1322 +- .../platform/emlib/src/em_rmu.c | 764 +- .../platform/emlib/src/em_se.c | 2744 +- .../platform/emlib/src/em_system.c | 872 +- .../platform/emlib/src/em_timer.c | 1040 +- .../platform/emlib/src/em_usart.c | 2888 +- .../platform/emlib/src/em_vdac.c | 1272 +- .../platform/emlib/src/em_wdog.c | 710 +- .../peripheral/inc/peripheral_sysrtc.h | 868 +- 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32 +- .../locator_host_cmake/CMakeLists.txt | 110 +- .../locator_host_cmake/CMakePresets.json | 70 +- .../locator_host_cmake/locator_host.cmake | 466 +- .../locator_host_cmake/toolchain.cmake | 172 +- locator_host/main.c | 142 +- locator_host/readme.md | 248 +- locator_host/sl_system_config.h | 134 +- locator_host/tools/mqtt_forwarder/README.md | 14 +- locator_host/tools/mqtt_forwarder/main.py | 68 +- locator_host/tools/mqtt_forwarder/mqtt.py | 26 +- .../tools/mqtt_forwarder/requirements.txt | 2 +- .../tools/mqtt_forwarder/rtt_viewer.py | 54 +- locator_ncp/Makefile | 32 +- locator_ncp/app.c | 242 +- locator_ncp/app.h | 138 +- locator_ncp/autogen/RTE_Components.h | 44 +- locator_ncp/autogen/linkerfile.ld | 500 +- locator_ncp/autogen/sl_application_type.h | 82 +- locator_ncp/autogen/sl_bluetooth.c | 178 +- locator_ncp/autogen/sl_bluetooth.h | 84 +- locator_ncp/autogen/sl_board_default_init.c | 72 +- locator_ncp/autogen/sl_component_catalog.h | 102 +- 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| 330 +- .../common/util/app_assert/sl_app_assert.h | 80 +- .../app/common/util/app_timer/app_timer.c | 708 +- .../app/common/util/app_timer/app_timer.h | 234 +- .../common/util/app_timer/sl_simple_timer.h | 86 +- .../hardware/board/inc/sl_board_control.h | 438 +- .../hardware/board/inc/sl_board_init.h | 130 +- .../board/src/sl_board_control_gpio.c | 910 +- .../hardware/board/src/sl_board_init.c | 196 +- .../configuration_over_swo/inc/sl_cos.h | 294 +- .../configuration_over_swo/src/sl_cos.c | 740 +- .../sl_mx25_flash_shutdown.h | 130 +- .../sl_mx25_flash_shutdown.c | 282 +- .../CMSIS/Core/Include/cmsis_compiler.h | 566 +- .../platform/CMSIS/Core/Include/cmsis_gcc.h | 4422 +-- .../CMSIS/Core/Include/cmsis_version.h | 78 +- .../platform/CMSIS/Core/Include/core_cm33.h | 6530 ++-- .../platform/CMSIS/Core/Include/mpu_armv8.h | 704 +- .../platform/CMSIS/Core/Include/tz_context.h | 140 +- .../EFR32BG22/Include/efr32bg22_aes.h | 906 +- .../EFR32BG22/Include/efr32bg22_buram.h | 160 +- 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+- .../bootloader/api/application_properties.h | 336 +- .../platform/bootloader/api/btl_errorcode.h | 758 +- .../platform/bootloader/api/btl_interface.c | 1702 +- .../platform/bootloader/api/btl_interface.h | 1458 +- .../bootloader/api/btl_interface_parser.h | 276 +- .../bootloader/api/btl_interface_storage.c | 1152 +- .../bootloader/api/btl_interface_storage.h | 1306 +- .../platform/bootloader/api/btl_reset_info.h | 194 +- .../app_properties/app_properties.c | 98 +- .../platform/common/inc/sl_assert.h | 198 +- .../platform/common/inc/sl_atomic.h | 160 +- .../platform/common/inc/sl_common.h | 770 +- .../platform/common/inc/sl_enum.h | 132 +- .../platform/common/inc/sl_slist.h | 306 +- .../platform/common/inc/sl_status.h | 904 +- .../platform/common/src/sl_assert.c | 152 +- .../platform/common/src/sl_slist.c | 344 +- .../platform/common/src/sl_syscalls.c | 230 +- .../common/toolchain/inc/sl_gcc_preinclude.h | 80 +- .../platform/common/toolchain/inc/sl_memory.h | 136 +- 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+- .../se_manager/inc/sl_se_manager_hash.h | 616 +- .../inc/sl_se_manager_internal_keys.h | 286 +- .../inc/sl_se_manager_key_derivation.h | 872 +- .../inc/sl_se_manager_key_handling.h | 516 +- .../se_manager/inc/sl_se_manager_signature.h | 370 +- .../se_manager/inc/sl_se_manager_types.h | 990 +- .../se_manager/inc/sl_se_manager_util.h | 1650 +- .../se_manager/inc/sli_se_manager_features.h | 266 +- .../se_manager/inc/sli_se_manager_internal.h | 858 +- .../se_manager/src/sl_se_manager.c | 1032 +- .../src/sl_se_manager_attestation.c | 592 +- .../se_manager/src/sl_se_manager_cipher.c | 5766 +-- .../se_manager/src/sl_se_manager_entropy.c | 206 +- .../se_manager/src/sl_se_manager_hash.c | 1346 +- .../src/sl_se_manager_key_derivation.c | 2168 +- .../src/sl_se_manager_key_handling.c | 2384 +- .../se_manager/src/sl_se_manager_signature.c | 424 +- .../se_manager/src/sl_se_manager_util.c | 2662 +- .../se_manager/src/sli_se_manager_osal.h | 332 +- .../src/sli_se_manager_osal_baremetal.h | 272 +- .../include/compiler_extentions.h | 28 +- .../include/cryptolib_def.h | 316 +- .../include/cryptolib_types.h | 234 +- .../sl_cryptoacc_library/include/sx_aes.h | 2694 +- .../include/sx_blk_cipher_common.h | 50 +- .../sl_cryptoacc_library/include/sx_dh_alg.h | 166 +- .../sl_cryptoacc_library/include/sx_dma.h | 378 +- .../include/sx_ecc_curves.h | 200 +- .../include/sx_ecc_keygen_alg.h | 294 +- .../include/sx_ecdsa_alg.h | 350 +- .../sl_cryptoacc_library/include/sx_errors.h | 142 +- .../sl_cryptoacc_library/include/sx_hash.h | 450 +- .../sl_cryptoacc_library/include/sx_hw_cfg.h | 82 +- .../sl_cryptoacc_library/include/sx_math.h | 178 +- .../sl_cryptoacc_library/include/sx_memcmp.h | 64 +- .../sl_cryptoacc_library/include/sx_memcpy.h | 140 +- .../include/sx_primitives.h | 576 +- .../sl_cryptoacc_library/include/sx_rng.h | 174 +- .../sl_cryptoacc_library/include/sx_trng.h | 386 +- .../sl_cryptoacc_library/src/ba411e_config.h | 248 +- .../sl_cryptoacc_library/src/ba413_config.h | 248 +- .../sl_cryptoacc_library/src/ba414ep_config.c | 1028 +- .../sl_cryptoacc_library/src/ba414ep_config.h | 1080 +- .../sl_cryptoacc_library/src/ba431_config.c | 428 +- .../sl_cryptoacc_library/src/ba431_config.h | 690 +- .../src/cryptodma_internal.c | 440 +- .../src/cryptodma_internal.h | 548 +- .../src/cryptolib_types.c | 30 +- .../sl_cryptoacc_library/src/padding.h | 62 +- .../sl_cryptoacc_library/src/sx_aes.c | 2052 +- .../sl_cryptoacc_library/src/sx_blk_cipher.c | 2774 +- .../sl_cryptoacc_library/src/sx_blk_cipher.h | 1742 +- .../sl_cryptoacc_library/src/sx_dh_alg.c | 192 +- .../sl_cryptoacc_library/src/sx_ecc_curves.c | 886 +- .../src/sx_ecc_keygen_alg.c | 240 +- .../sl_cryptoacc_library/src/sx_ecdsa_alg.c | 548 +- .../sl_cryptoacc_library/src/sx_hash.c | 842 +- .../sl_cryptoacc_library/src/sx_math.c | 268 +- .../sl_cryptoacc_library/src/sx_memcmp.c | 76 +- .../sl_cryptoacc_library/src/sx_memcpy.c | 204 +- .../sl_cryptoacc_library/src/sx_primitives.c | 1074 +- .../sl_cryptoacc_library/src/sx_rng.c | 242 +- .../sl_cryptoacc_library/src/sx_trng.c | 748 +- .../sl_cryptoacc_library/src/sxregs.h | 34 +- .../config/sli_mbedtls_acceleration.h | 1048 +- .../config/sli_mbedtls_omnipresent.h | 282 +- .../config/sli_psa_acceleration.h | 270 +- .../sl_mbedtls_support/inc/aes_alt.h | 162 +- .../sl_mbedtls_support/inc/ccm_alt.h | 140 +- .../sl_mbedtls_support/inc/cmac_alt.h | 156 +- .../sl_mbedtls_support/inc/gcm_alt.h | 242 +- .../sl_mbedtls_support/inc/sha1_alt.h | 164 +- .../sl_mbedtls_support/inc/sha256_alt.h | 168 +- .../sl_mbedtls_support/inc/sha512_alt.h | 156 +- .../sl_mbedtls_support/inc/sl_mbedtls.h | 84 +- .../sl_mbedtls_support/inc/sl_psa_crypto.h | 240 +- .../sl_mbedtls_support/inc/sl_psa_values.h | 392 +- .../sl_mbedtls_support/inc/sli_psa_crypto.h | 310 +- .../sl_mbedtls_support/src/cryptoacc_aes.c | 1668 +- .../sl_mbedtls_support/src/cryptoacc_gcm.c | 1020 +- .../sl_mbedtls_support/src/mbedtls_ccm.c | 698 +- .../sl_mbedtls_support/src/mbedtls_cmac.c | 828 +- .../src/mbedtls_ecdsa_ecdh.c | 844 +- .../sl_mbedtls_support/src/sl_mbedtls.c | 234 +- .../sl_mbedtls_support/src/sl_psa_crypto.c | 154 +- .../sl_mbedtls_support/src/sli_psa_crypto.c | 234 +- .../src/sli_protocol_crypto.h | 410 +- .../src/sli_protocol_crypto_radioaes.c | 1728 +- .../src/sli_radioaes_management.c | 406 +- .../src/sli_radioaes_management.h | 202 +- .../sl_psa_driver/inc/cryptoacc_management.h | 198 +- .../sl_psa_driver/inc/psa/error.h | 52 +- .../inc/psa/internal_trusted_storage.h | 58 +- .../inc/psa/sli_internal_trusted_storage.h | 262 +- .../inc/sli_cryptoacc_driver_trng.h | 174 +- .../inc/sli_cryptoacc_transparent_functions.h | 700 +- .../inc/sli_cryptoacc_transparent_types.h | 272 +- .../sl_psa_driver/inc/sli_psa_driver_common.h | 460 +- .../inc/sli_psa_driver_features.h | 786 +- .../inc/sli_se_version_dependencies.h | 282 +- .../sl_psa_driver/src/cryptoacc_management.c | 272 +- .../sl_psa_driver/src/sl_psa_its_nvm3.c | 6604 ++-- .../src/sli_cryptoacc_driver_trng.c | 562 +- .../sli_cryptoacc_transparent_driver_aead.c | 3650 +- .../sli_cryptoacc_transparent_driver_cipher.c | 4336 +-- .../sli_cryptoacc_transparent_driver_hash.c | 980 +- ...ptoacc_transparent_driver_key_derivation.c | 392 +- ...ptoacc_transparent_driver_key_management.c | 968 +- .../sli_cryptoacc_transparent_driver_mac.c | 1480 +- ...i_cryptoacc_transparent_driver_signature.c | 672 +- .../sl_psa_driver/src/sli_psa_driver_common.c | 130 +- .../sl_psa_driver/src/sli_psa_driver_init.c | 264 +- .../sl_psa_driver/src/sli_psa_trng.c | 332 +- .../src/sli_se_version_dependencies.c | 144 +- .../device_init/inc/sl_device_init_clocks.h | 242 +- .../device_init/inc/sl_device_init_dcdc.h | 176 +- .../device_init/inc/sl_device_init_emu.h | 178 +- .../device_init/inc/sl_device_init_hfxo.h | 176 +- .../device_init/inc/sl_device_init_lfrco.h | 156 +- .../device_init/inc/sl_device_init_lfxo.h | 170 +- .../device_init/inc/sl_device_init_nvic.h | 140 +- .../device_init/src/sl_device_init_dcdc_s2.c | 114 +- .../device_init/src/sl_device_init_emu_s2.c | 98 +- .../device_init/src/sl_device_init_hfxo_s2.c | 174 +- .../device_init/src/sl_device_init_lfrco.c | 132 +- .../device_init/src/sl_device_init_lfxo_s2.c | 94 +- .../device_init/src/sl_device_init_nvic.c | 92 +- .../platform/service/mpu/inc/sl_mpu.h | 174 +- .../platform/service/mpu/src/sl_mpu.c | 806 +- .../power_manager/inc/sl_power_manager.h | 1070 +- .../inc/sl_power_manager_debug.h | 120 +- .../power_manager/inc/sli_power_manager.h | 194 +- .../power_manager/src/sl_power_manager.c | 2360 +- .../src/sl_power_manager_debug.c | 338 +- .../src/sl_power_manager_hal_s2.c | 1328 +- .../src/sli_power_manager_private.h | 284 +- .../service/sleeptimer/inc/sl_sleeptimer.h | 2262 +- .../service/sleeptimer/inc/sli_sleeptimer.h | 272 +- .../service/sleeptimer/src/sl_sleeptimer.c | 3884 +- .../sleeptimer/src/sl_sleeptimer_hal_burtc.c | 650 +- .../sleeptimer/src/sl_sleeptimer_hal_prortc.c | 1068 +- .../sleeptimer/src/sl_sleeptimer_hal_rtcc.c | 682 +- .../sleeptimer/src/sl_sleeptimer_hal_timer.c | 726 +- .../sleeptimer/src/sli_sleeptimer_hal.h | 292 +- .../service/system/inc/sl_system_init.h | 306 +- .../system/inc/sl_system_process_action.h | 106 +- .../service/system/src/sl_system_init.c | 78 +- .../system/src/sl_system_process_action.c | 76 +- .../platform/service/udelay/inc/sl_udelay.h | 156 +- .../platform/service/udelay/src/sl_udelay.c | 138 +- .../service/udelay/src/sl_udelay_armv6m_gcc.S | 120 +- .../protocol/bluetooth/api/sl_bt.xapi | 7422 ++-- .../bgstack/ll/inc/sl_btctrl_linklayer.h | 614 +- .../protocol/bluetooth/inc/sl_bgapi.h | 620 +- .../protocol/bluetooth/inc/sl_bt_api.h | 31264 ++++++++-------- .../bluetooth/inc/sl_bt_api_compatibility.h | 100 +- .../protocol/bluetooth/inc/sl_bt_ll_config.h | 160 +- .../bluetooth/inc/sl_bt_stack_config.h | 138 +- .../protocol/bluetooth/inc/sl_bt_stack_init.h | 76 +- .../protocol/bluetooth/inc/sl_bt_types.h | 44 +- .../protocol/bluetooth/inc/sl_bt_version.h | 168 +- .../bluetooth/inc/sli_bt_accept_list_config.h | 66 +- .../bluetooth/inc/sli_bt_advertiser_config.h | 60 +- .../bluetooth/inc/sli_bt_config_defs.h | 432 +- .../bluetooth/inc/sli_bt_connection_config.h | 62 +- .../inc/sli_bt_dynamic_gattdb_config.h | 60 +- .../bluetooth/inc/sli_bt_gattdb_def.h | 216 +- .../bluetooth/inc/sli_bt_l2cap_config.h | 66 +- .../inc/sli_bt_pawr_advertiser_config.h | 66 +- .../inc/sli_bt_periodic_adv_config.h | 76 +- .../inc/sli_bt_periodic_advertiser_config.h | 66 +- .../bluetooth/inc/sli_bt_sync_config.h | 66 +- .../protocol/bluetooth/src/sl_bt_stack_init.c | 1810 +- .../bluetooth/src/sli_bt_accept_list_config.c | 56 +- .../bluetooth/src/sli_bt_advertiser_config.c | 66 +- .../bluetooth/src/sli_bt_connection_config.c | 70 +- .../src/sli_bt_dynamic_gattdb_config.c | 82 +- .../bluetooth/src/sli_bt_l2cap_config.c | 70 +- .../src/sli_bt_pawr_advertiser_config.c | 56 +- .../src/sli_bt_periodic_adv_config.c | 88 +- .../src/sli_bt_periodic_advertiser_config.c | 56 +- .../bluetooth/src/sli_bt_sync_config.c | 56 +- .../silabs_core/memory_manager/sl_malloc.c | 202 +- .../silabs_core/memory_manager/sl_malloc.h | 76 +- .../third_party/mbedtls/include/mbedtls/aes.h | 1278 +- .../mbedtls/include/mbedtls/aria.h | 706 +- .../mbedtls/include/mbedtls/asn1.h | 1306 +- .../mbedtls/include/mbedtls/asn1write.h | 802 +- .../mbedtls/include/mbedtls/base64.h | 188 +- .../mbedtls/include/mbedtls/bignum.h | 2192 +- .../mbedtls/include/mbedtls/build_info.h | 316 +- .../mbedtls/include/mbedtls/camellia.h | 630 +- .../third_party/mbedtls/include/mbedtls/ccm.h | 1060 +- .../mbedtls/include/mbedtls/chacha20.h | 428 +- .../mbedtls/include/mbedtls/chachapoly.h | 708 +- .../mbedtls/include/mbedtls/check_config.h | 2436 +- .../mbedtls/include/mbedtls/cipher.h | 2378 +- .../mbedtls/include/mbedtls/cmac.h | 516 +- .../mbedtls/include/mbedtls/compat-2.x.h | 116 +- .../mbedtls/config_adjust_legacy_crypto.h | 390 +- .../mbedtls/config_adjust_legacy_from_psa.h | 1522 +- .../mbedtls/config_adjust_psa_from_legacy.h | 692 +- .../config_adjust_psa_superset_legacy.h | 308 +- .../include/mbedtls/config_adjust_ssl.h | 176 +- .../include/mbedtls/config_adjust_x509.h | 74 +- .../mbedtls/include/mbedtls/config_psa.h | 134 +- .../mbedtls/include/mbedtls/constant_time.h | 96 +- .../mbedtls/include/mbedtls/ctr_drbg.h | 1152 +- .../mbedtls/include/mbedtls/debug.h | 640 +- .../third_party/mbedtls/include/mbedtls/des.h | 794 +- .../third_party/mbedtls/include/mbedtls/dhm.h | 1968 +- .../mbedtls/include/mbedtls/ecdh.h | 906 +- .../mbedtls/include/mbedtls/ecdsa.h | 1366 +- .../mbedtls/include/mbedtls/ecjpake.h | 620 +- .../third_party/mbedtls/include/mbedtls/ecp.h | 2748 +- .../mbedtls/include/mbedtls/entropy.h | 570 +- .../mbedtls/include/mbedtls/error.h | 426 +- .../third_party/mbedtls/include/mbedtls/gcm.h | 764 +- .../mbedtls/include/mbedtls/hkdf.h | 272 +- .../mbedtls/include/mbedtls/hmac_drbg.h | 892 +- .../third_party/mbedtls/include/mbedtls/lms.h | 904 +- .../mbedtls/include/mbedtls/mbedtls_config.h | 8250 ++-- .../third_party/mbedtls/include/mbedtls/md.h | 1296 +- .../third_party/mbedtls/include/mbedtls/md5.h | 404 +- .../include/mbedtls/memory_buffer_alloc.h | 308 +- .../mbedtls/include/mbedtls/net_sockets.h | 622 +- .../mbedtls/include/mbedtls/nist_kw.h | 356 +- .../third_party/mbedtls/include/mbedtls/oid.h | 1468 +- .../third_party/mbedtls/include/mbedtls/pem.h | 344 +- .../third_party/mbedtls/include/mbedtls/pk.h | 2214 +- .../mbedtls/include/mbedtls/pkcs12.h | 396 +- .../mbedtls/include/mbedtls/pkcs5.h | 418 +- .../mbedtls/include/mbedtls/pkcs7.h | 506 +- .../mbedtls/include/mbedtls/platform.h | 994 +- .../mbedtls/include/mbedtls/platform_time.h | 182 +- .../mbedtls/include/mbedtls/platform_util.h | 426 +- .../mbedtls/include/mbedtls/poly1305.h | 360 +- .../mbedtls/include/mbedtls/private_access.h | 64 +- .../mbedtls/include/mbedtls/psa_util.h | 232 +- .../mbedtls/include/mbedtls/ripemd160.h | 296 +- .../third_party/mbedtls/include/mbedtls/rsa.h | 2310 +- .../mbedtls/include/mbedtls/sha1.h | 462 +- .../mbedtls/include/mbedtls/sha256.h | 420 +- .../mbedtls/include/mbedtls/sha3.h | 368 +- .../mbedtls/include/mbedtls/sha512.h | 440 +- .../third_party/mbedtls/include/mbedtls/ssl.h | 10760 +++--- .../mbedtls/include/mbedtls/ssl_cache.h | 398 +- .../include/mbedtls/ssl_ciphersuites.h | 1256 +- .../mbedtls/include/mbedtls/ssl_cookie.h | 236 +- .../mbedtls/include/mbedtls/ssl_ticket.h | 386 +- .../mbedtls/include/mbedtls/threading.h | 276 +- .../mbedtls/include/mbedtls/timing.h | 212 +- .../mbedtls/include/mbedtls/version.h | 180 +- .../mbedtls/include/mbedtls/x509.h | 1124 +- .../mbedtls/include/mbedtls/x509_crl.h | 392 +- .../mbedtls/include/mbedtls/x509_crt.h | 2416 +- .../mbedtls/include/mbedtls/x509_csr.h | 662 +- .../mbedtls/include/psa/build_info.h | 64 +- .../third_party/mbedtls/include/psa/crypto.h | 9544 ++--- .../include/psa/crypto_adjust_auto_enabled.h | 66 +- .../psa/crypto_adjust_config_key_pair_types.h | 206 +- .../psa/crypto_adjust_config_synonyms.h | 114 +- .../include/psa/crypto_builtin_composites.h | 444 +- .../psa/crypto_builtin_key_derivation.h | 260 +- .../include/psa/crypto_builtin_primitives.h | 252 +- .../mbedtls/include/psa/crypto_compat.h | 348 +- .../mbedtls/include/psa/crypto_config.h | 330 +- .../include/psa/crypto_driver_common.h | 112 +- .../psa/crypto_driver_contexts_composites.h | 382 +- .../crypto_driver_contexts_key_derivation.h | 128 +- .../psa/crypto_driver_contexts_primitives.h | 330 +- .../mbedtls/include/psa/crypto_extra.h | 4178 +-- .../mbedtls/include/psa/crypto_legacy.h | 200 +- .../mbedtls/include/psa/crypto_platform.h | 208 +- .../mbedtls/include/psa/crypto_se_driver.h | 2790 +- .../mbedtls/include/psa/crypto_sizes.h | 2606 +- .../mbedtls/include/psa/crypto_struct.h | 966 +- .../mbedtls/include/psa/crypto_types.h | 958 +- .../mbedtls/include/psa/crypto_values.h | 5570 +-- .../third_party/mbedtls/library/alignment.h | 1042 +- .../mbedtls/library/base64_internal.h | 114 +- .../third_party/mbedtls/library/bignum_core.h | 1550 +- .../third_party/mbedtls/library/bignum_mod.h | 928 +- .../mbedtls/library/bignum_mod_raw.h | 856 +- .../mbedtls/library/bignum_mod_raw_invasive.h | 92 +- .../util/third_party/mbedtls/library/bn_mul.h | 2212 +- .../mbedtls/library/check_crypto_config.h | 306 +- .../util/third_party/mbedtls/library/cipher.c | 3364 +- .../third_party/mbedtls/library/cipher_wrap.c | 4870 +-- .../third_party/mbedtls/library/cipher_wrap.h | 288 +- .../util/third_party/mbedtls/library/common.h | 674 +- .../mbedtls/library/constant_time.c | 546 +- .../mbedtls/library/constant_time_impl.h | 1132 +- .../mbedtls/library/constant_time_internal.h | 1182 +- .../mbedtls/library/ecp_internal_alt.h | 598 +- .../mbedtls/library/ecp_invasive.h | 674 +- .../mbedtls/library/entropy_poll.h | 152 +- .../util/third_party/mbedtls/library/lmots.h | 646 +- .../util/third_party/mbedtls/library/md_psa.h | 150 +- .../third_party/mbedtls/library/md_wrap.h | 116 +- .../third_party/mbedtls/library/mps_common.h | 390 +- .../third_party/mbedtls/library/mps_error.h | 206 +- .../third_party/mbedtls/library/mps_reader.h | 760 +- .../third_party/mbedtls/library/mps_trace.h | 336 +- .../third_party/mbedtls/library/padlock.h | 246 +- .../third_party/mbedtls/library/pk_internal.h | 260 +- .../third_party/mbedtls/library/pk_wrap.h | 336 +- .../third_party/mbedtls/library/pkwrite.h | 248 +- .../third_party/mbedtls/library/platform.c | 828 +- .../mbedtls/library/platform_util.c | 594 +- .../third_party/mbedtls/library/psa_crypto.c | 17504 ++++----- .../mbedtls/library/psa_crypto_aead.c | 1334 +- .../mbedtls/library/psa_crypto_aead.h | 1022 +- .../mbedtls/library/psa_crypto_cipher.c | 1232 +- .../mbedtls/library/psa_crypto_cipher.h | 610 +- .../mbedtls/library/psa_crypto_client.c | 158 +- .../mbedtls/library/psa_crypto_core.h | 1786 +- .../mbedtls/library/psa_crypto_core_common.h | 128 +- .../library/psa_crypto_driver_wrappers.h | 8888 ++--- .../psa_crypto_driver_wrappers_no_static.c | 898 +- .../psa_crypto_driver_wrappers_no_static.h | 86 +- .../mbedtls/library/psa_crypto_ecp.c | 1146 +- .../mbedtls/library/psa_crypto_ecp.h | 558 +- .../mbedtls/library/psa_crypto_ffdh.c | 614 +- .../mbedtls/library/psa_crypto_ffdh.h | 288 +- .../mbedtls/library/psa_crypto_hash.c | 964 +- .../mbedtls/library/psa_crypto_hash.h | 446 +- .../mbedtls/library/psa_crypto_invasive.h | 164 +- .../mbedtls/library/psa_crypto_its.h | 286 +- .../mbedtls/library/psa_crypto_mac.c | 1016 +- .../mbedtls/library/psa_crypto_mac.h | 552 +- .../mbedtls/library/psa_crypto_pake.c | 1166 +- .../mbedtls/library/psa_crypto_pake.h | 342 +- .../mbedtls/library/psa_crypto_random_impl.h | 408 +- .../mbedtls/library/psa_crypto_rsa.c | 1478 +- .../mbedtls/library/psa_crypto_rsa.h | 658 +- .../mbedtls/library/psa_crypto_se.c | 770 +- .../mbedtls/library/psa_crypto_se.h | 394 +- .../library/psa_crypto_slot_management.c | 1486 +- .../library/psa_crypto_slot_management.h | 422 +- .../mbedtls/library/psa_crypto_storage.c | 986 +- .../mbedtls/library/psa_crypto_storage.h | 792 +- .../third_party/mbedtls/library/psa_util.c | 342 +- .../mbedtls/library/psa_util_internal.h | 216 +- .../mbedtls/library/rsa_alt_helpers.h | 440 +- .../third_party/mbedtls/library/ssl_client.h | 68 +- .../mbedtls/library/ssl_debug_helpers.h | 180 +- .../third_party/mbedtls/library/ssl_misc.h | 5718 +-- .../mbedtls/library/ssl_tls13_invasive.h | 70 +- .../mbedtls/library/ssl_tls13_keys.h | 1326 +- .../third_party/mbedtls/library/threading.c | 400 +- locator_ncp/locator_ncp.pintool | 62 +- locator_ncp/locator_ncp.slcp | 142 +- locator_ncp/locator_ncp.slps | 32 +- locator_ncp/locator_ncp_cmake/CMakeLists.txt | 94 +- .../locator_ncp_cmake/CMakePresets.json | 76 +- .../locator_ncp_cmake/locator_ncp.cmake | 626 +- locator_ncp/locator_ncp_cmake/toolchain.cmake | 144 +- locator_ncp/main.c | 142 +- locator_ncp/readme.md | 210 +- sonar-project.properties | 52 +- tools/.clang-tidy | 100 +- tools/.codespell/.codespellrc | 20 +- tools/.codespell/ignore-words.txt | 4 +- tools/README.md | 338 +- tools/uncrustify.cfg | 368 +- 999 files changed, 481083 insertions(+), 481072 deletions(-) diff --git a/.github/CONTRIBUTING.md b/.github/CONTRIBUTING.md index adbfb70..4dc7d03 100644 --- a/.github/CONTRIBUTING.md +++ b/.github/CONTRIBUTING.md @@ -113,4 +113,4 @@ These are some of the rules we try to follow: - Note that the Silicon Labs Open Source projects developers also have their regular duties, so depending on the required effort for reviewing, testing and clarification this may take a while 9. Once the change has been approved we will inform you in a comment -10. We will close the pull request, feel free to delete the now obsolete branch \ No newline at end of file +10. We will close the pull request, feel free to delete the now obsolete branch diff --git a/.github/Docker_readme.md b/.github/Docker_readme.md index 8a60934..66ff51e 100644 --- a/.github/Docker_readme.md +++ b/.github/Docker_readme.md @@ -1,7 +1,7 @@ -# Build docker image - -Having a docker image for CICD is always a good way to secure the product development. Let's build a docker image. - -## Readme - -Please check the documentation in the main [README](../README.md) file. +# Build docker image + +Having a docker image for CICD is always a good way to secure the product development. Let's build a docker image. + +## Readme + +Please check the documentation in the main [README](../README.md) file. diff --git a/.github/build-docker-image.sh b/.github/build-docker-image.sh index 3143db4..1de4fdd 100644 --- a/.github/build-docker-image.sh +++ b/.github/build-docker-image.sh @@ -1,53 +1,53 @@ -#!/bin/sh - -display_help() { - echo "Usage: $0 -i image_name -v version -r registry -a architecture " >&2 - echo - echo " -i image_name Specify the image name, for example: devs_xg24_aoa_poc" - echo " -v version Specify the version of docker image, for example: 1.0.0" - echo " -r registry Specify the Docker registry to push the image to (optional) example: lx0017637.silabs.com:5000" - echo " If internal registry is used, SonarQube will be included." - echo " -a architecture Specify the architecture, for example: x86_64 or aarch64" - echo - exit 1 -} - -image_name="" -version="1.0.0" -registry="none" -architecture="x86_64" -run_sonarqube_scanner="false" - -# Process the options -while getopts ":h:i:v:r:a:" opt; do - case $opt in - h) display_help - exit;; - i) image_name="$OPTARG";; - v) version="$OPTARG";; - r) registry="$OPTARG";; - a) architecture="$OPTARG";; - \?) echo "Invalid option -$OPTARG" >&2 - display_help - exit 1;; - :) echo "Option -$OPTARG requires an argument." >&2 - display_help - exit 1;; - esac -done - -if [ "$registry" = "lx0017637.silabs.com:5000" ] ; then - echo "Internal silabs build with: $registry" - run_sonarqube_scanner="true" -fi - -# Build the Docker image -echo "Building Docker image: $image_name:$version for architecture: $architecture " -docker build --build-arg ARCH="$architecture" --build-arg SONARQUBE="$run_sonarqube_scanner" -t "$image_name:$version" -f Dockerfile . - -if [ -n "$registry" ] && [ "$registry" != "none" ] ; then - docker tag "$image_name:$version" "$registry/$image_name:$version" - docker push "$registry/$image_name:$version" -else - echo "Docker registry not specified, skipping tagging and pushing." -fi +#!/bin/sh + +display_help() { + echo "Usage: $0 -i image_name -v version -r registry -a architecture " >&2 + echo + echo " -i image_name Specify the image name, for example: devs_xg24_aoa_poc" + echo " -v version Specify the version of docker image, for example: 1.0.0" + echo " -r registry Specify the Docker registry to push the image to (optional) example: lx0017637.silabs.com:5000" + echo " If internal registry is used, SonarQube will be included." + echo " -a architecture Specify the architecture, for example: x86_64 or aarch64" + echo + exit 1 +} + +image_name="" +version="1.0.0" +registry="none" +architecture="x86_64" +run_sonarqube_scanner="false" + +# Process the options +while getopts ":h:i:v:r:a:" opt; do + case $opt in + h) display_help + exit;; + i) image_name="$OPTARG";; + v) version="$OPTARG";; + r) registry="$OPTARG";; + a) architecture="$OPTARG";; + \?) echo "Invalid option -$OPTARG" >&2 + display_help + exit 1;; + :) echo "Option -$OPTARG requires an argument." >&2 + display_help + exit 1;; + esac +done + +if [ "$registry" = "lx0017637.silabs.com:5000" ] ; then + echo "Internal silabs build with: $registry" + run_sonarqube_scanner="true" +fi + +# Build the Docker image +echo "Building Docker image: $image_name:$version for architecture: $architecture " +docker build --build-arg ARCH="$architecture" --build-arg SONARQUBE="$run_sonarqube_scanner" -t "$image_name:$version" -f Dockerfile . + +if [ -n "$registry" ] && [ "$registry" != "none" ] ; then + docker tag "$image_name:$version" "$registry/$image_name:$version" + docker push "$registry/$image_name:$version" +else + echo "Docker registry not specified, skipping tagging and pushing." +fi diff --git a/.github/build-with-docker.sh b/.github/build-with-docker.sh index 0cff8a8..0e1c3f1 100644 --- a/.github/build-with-docker.sh +++ b/.github/build-with-docker.sh @@ -1,61 +1,61 @@ -#!/bin/sh - -display_help() { - echo "Usage: $0 -i image_name -v version -r registry -a architecture -c clean" >&2 - echo - echo " -i image_name Specify the image name, for example: devs_xg24_aoa_poc" - echo " -v version Specify the version of docker image, for example: 1.0.0" - echo " -r registry Specify the Docker registry to push the image to" - echo " -a architecture Specify the architecture, for example: x86_64 or aarch64 (optional)" - echo " -c clean Specify 'clean' to remove the built Docker image" - echo - exit 1 -} - -image_name="devs_xg24_aoa_poc" -version="1.0.0" -registry="none" -architecture="x86_64" -clean="false" - -while getopts ":hi:v:r:a:c" opt; do - case ${opt} in - h ) - display_help - exit 1;; - i ) - image_name=$OPTARG;; - v ) - version=$OPTARG;; - r ) - registry=$OPTARG;; - a ) - architecture=$OPTARG;; - c ) - clean="true";; - \? ) - display_help - exit 1 ;; - : ) - echo "Invalid option: $OPTARG requires an argument" 1>&2 - display_help - exit 1 ;; - esac -done -shift $((OPTIND -1)) - -echo "<----- Docker based Weber Wasp project building script ----->" - -echo "Calling the docker image builder script..." - -# Call build-docker-image.sh with arguments -sh ./.github/build-docker-image.sh -i $image_name -v $version -r $registry -a $architecture || { echo "Failed to build the Docker image"; exit 1; } - -echo "<----- Running the docker based build environment ----->" -# Run the docker image -docker run -u root --rm -v $(pwd):/home/jenkins/devs_xg24_aoa_poc $image_name:$version /bin/sh -c "cd devs_xg24_aoa_poc && make all" - -if [ "$clean" = "true" ]; then - docker rmi $image_name:$version - echo "Clean mode activated. Docker image $image_name:$version is removed." -fi +#!/bin/sh + +display_help() { + echo "Usage: $0 -i image_name -v version -r registry -a architecture -c clean" >&2 + echo + echo " -i image_name Specify the image name, for example: devs_xg24_aoa_poc" + echo " -v version Specify the version of docker image, for example: 1.0.0" + echo " -r registry Specify the Docker registry to push the image to" + echo " -a architecture Specify the architecture, for example: x86_64 or aarch64 (optional)" + echo " -c clean Specify 'clean' to remove the built Docker image" + echo + exit 1 +} + +image_name="devs_xg24_aoa_poc" +version="1.0.0" +registry="none" +architecture="x86_64" +clean="false" + +while getopts ":hi:v:r:a:c" opt; do + case ${opt} in + h ) + display_help + exit 1;; + i ) + image_name=$OPTARG;; + v ) + version=$OPTARG;; + r ) + registry=$OPTARG;; + a ) + architecture=$OPTARG;; + c ) + clean="true";; + \? ) + display_help + exit 1 ;; + : ) + echo "Invalid option: $OPTARG requires an argument" 1>&2 + display_help + exit 1 ;; + esac +done +shift $((OPTIND -1)) + +echo "<----- Docker based Weber Wasp project building script ----->" + +echo "Calling the docker image builder script..." + +# Call build-docker-image.sh with arguments +sh ./.github/build-docker-image.sh -i $image_name -v $version -r $registry -a $architecture || { echo "Failed to build the Docker image"; exit 1; } + +echo "<----- Running the docker based build environment ----->" +# Run the docker image +docker run -u root --rm -v $(pwd):/home/jenkins/devs_xg24_aoa_poc $image_name:$version /bin/sh -c "cd devs_xg24_aoa_poc && make all" + +if [ "$clean" = "true" ]; then + docker rmi $image_name:$version + echo "Clean mode activated. Docker image $image_name:$version is removed." +fi diff --git a/.github/uncrustify.cfg b/.github/uncrustify.cfg index 87bb119..b49726d 100644 --- a/.github/uncrustify.cfg +++ b/.github/uncrustify.cfg @@ -1,184 +1,184 @@ -# uncrustify.cfg version 1.0.0 -# SPDX-FileCopyrightText: Silicon Laboratories Inc. https://www.silabs.com -# SPDX-License-Identifier: Zlib - -tok_split_gte=false -utf8_byte=false -utf8_force=true -indent_cmt_with_tabs=false -indent_align_string=true -indent_braces=false -indent_braces_no_func=false -indent_braces_no_class=false -indent_braces_no_struct=false -indent_brace_parent=false -indent_namespace=false -indent_extern=false -indent_class=true -indent_class_colon=false -indent_else_if=false -indent_var_def_cont=false -indent_func_call_param=false -indent_func_def_param=false -indent_func_proto_param=false -indent_func_class_param=false -indent_func_ctor_var_param=false -indent_template_param=false -indent_func_param_double=false -indent_relative_single_line_comments=false -indent_col1_comment=false -indent_access_spec_body=false -indent_paren_nl=false -indent_comma_paren=false -indent_bool_paren=false -indent_first_bool_expr=false -indent_square_nl=false -indent_preserve_sql=false -indent_align_assign=true -sp_balance_nested_parens=false -align_keep_tabs=false -align_with_tabs=false -align_on_tabstop=false -align_number_left=false -align_func_params=false -align_same_func_call_params=false -align_var_def_colon=false -align_var_def_attribute=false -align_var_def_inline=false -align_right_cmt_mix=false -align_on_operator=false -align_mix_var_proto=false -align_single_line_func=false -align_single_line_brace=false -align_nl_cont=true -align_left_shift=true -align_oc_decl_colon=false -nl_collapse_empty_body=false -nl_assign_leave_one_liners=false -nl_class_leave_one_liners=false -nl_enum_leave_one_liners=false -nl_getset_leave_one_liners=false -nl_func_leave_one_liners=false -nl_if_leave_one_liners=false -nl_multi_line_cond=false -nl_multi_line_define=false -nl_before_case=false -nl_after_case=false -nl_after_return=false -nl_after_semicolon=false -nl_after_brace_open=false -nl_after_brace_open_cmt=false -nl_after_vbrace_open=false -nl_after_vbrace_open_empty=false -nl_after_brace_close=false -nl_after_vbrace_close=false -nl_define_macro=false -nl_squeeze_ifdef=false -nl_ds_struct_enum_cmt=false -nl_ds_struct_enum_close_brace=false -nl_create_if_one_liner=false -nl_create_for_one_liner=false -nl_create_while_one_liner=false -ls_for_split_full=false -ls_func_split_full=true -nl_after_multiline_comment=false -eat_blanks_after_open_brace=true -eat_blanks_before_close_brace=true -mod_full_brace_if_chain=false -mod_pawn_semicolon=false -mod_full_paren_if_bool=false -mod_remove_extra_semicolon=false -mod_sort_import=false -mod_sort_using=false -mod_sort_include=false -mod_move_case_break=false -mod_remove_empty_return=false -cmt_indent_multi=true -cmt_c_group=false -cmt_c_nl_start=false -cmt_c_nl_end=false -cmt_cpp_group=false -cmt_cpp_nl_start=false -cmt_cpp_nl_end=false -cmt_cpp_to_c=false -cmt_star_cont=false -cmt_multi_check_last=true -cmt_insert_before_preproc=false -pp_indent=ignore -pp_if_indent_code=false -input_tab_size=2 -indent_columns=2 -indent_label=0 -align_pp_define_span=0 -nl_start_of_file=remove -nl_end_of_file_min=1 -code_width=0 -nl_max=2 -nl_comment_func_def=1 -cmt_width=0 -utf8_bom=remove -indent_with_tabs=0 -sp_before_assign=add -sp_after_assign=add -sp_bool=add -sp_compare=add -sp_inside_paren=remove -sp_before_sparen=force -sp_paren_paren=ignore -sp_inside_sparen=ignore -sp_after_sparen=force -sp_before_square=remove -sp_before_squares=remove -sp_inside_square=remove -sp_after_comma=force -sp_before_comma=remove -sp_paren_comma=remove -sp_inside_braces=add -sp_inside_braces_empty=remove -sp_func_def_paren=remove -sp_inside_fparen=remove -sp_func_call_paren=remove -sp_func_call_paren_empty=remove -sp_else_brace=force -sp_brace_else=force -sp_sign=remove -sp_incdec=remove -sp_cmt_cpp_start=ignore -sp_endif_cmt=force -nl_end_of_file=add -nl_enum_brace=remove -nl_struct_brace=remove -nl_union_brace=remove -nl_for_brace=remove -nl_brace_finally=remove -nl_while_brace=remove -nl_do_brace=remove -nl_brace_while=remove -nl_switch_brace=remove -nl_if_brace=remove -nl_brace_else=remove -nl_elseif_brace=remove -nl_else_brace=remove -nl_fdef_brace=add -mod_full_brace_do=force -mod_full_brace_if=force -mod_full_brace_while=ignore -mod_full_brace_for=force -mod_full_brace_function=force -sp_cmt_cpp_doxygen=true -cmt_sp_after_star_cont=3 -align_keep_extra_space=True -align_var_def_star_style=1 -align_var_def_amp_style=1 -sp_after_type=ignore -pos_arith=lead -pos_bool=lead -pos_compare=lead -pos_conditional=lead -pos_comma=trail -sp_arith=add -sp_assign=add -sp_pp_concat=ignore -# Indent the 'case' label from the 'switch' header (coding standard §4.4.3) -# Note: Must come *after* the declaration of 'indent_columns'! -indent_switch_case=indent_columns +# uncrustify.cfg version 1.0.0 +# SPDX-FileCopyrightText: Silicon Laboratories Inc. https://www.silabs.com +# SPDX-License-Identifier: Zlib + +tok_split_gte=false +utf8_byte=false +utf8_force=true +indent_cmt_with_tabs=false +indent_align_string=true +indent_braces=false +indent_braces_no_func=false +indent_braces_no_class=false +indent_braces_no_struct=false +indent_brace_parent=false +indent_namespace=false +indent_extern=false +indent_class=true +indent_class_colon=false +indent_else_if=false +indent_var_def_cont=false +indent_func_call_param=false +indent_func_def_param=false +indent_func_proto_param=false +indent_func_class_param=false +indent_func_ctor_var_param=false +indent_template_param=false +indent_func_param_double=false +indent_relative_single_line_comments=false +indent_col1_comment=false +indent_access_spec_body=false +indent_paren_nl=false +indent_comma_paren=false +indent_bool_paren=false +indent_first_bool_expr=false +indent_square_nl=false +indent_preserve_sql=false +indent_align_assign=true +sp_balance_nested_parens=false +align_keep_tabs=false +align_with_tabs=false +align_on_tabstop=false +align_number_left=false +align_func_params=false +align_same_func_call_params=false +align_var_def_colon=false +align_var_def_attribute=false +align_var_def_inline=false +align_right_cmt_mix=false +align_on_operator=false +align_mix_var_proto=false +align_single_line_func=false +align_single_line_brace=false +align_nl_cont=true +align_left_shift=true +align_oc_decl_colon=false +nl_collapse_empty_body=false +nl_assign_leave_one_liners=false +nl_class_leave_one_liners=false +nl_enum_leave_one_liners=false +nl_getset_leave_one_liners=false +nl_func_leave_one_liners=false +nl_if_leave_one_liners=false +nl_multi_line_cond=false +nl_multi_line_define=false +nl_before_case=false +nl_after_case=false +nl_after_return=false +nl_after_semicolon=false +nl_after_brace_open=false +nl_after_brace_open_cmt=false +nl_after_vbrace_open=false +nl_after_vbrace_open_empty=false +nl_after_brace_close=false +nl_after_vbrace_close=false +nl_define_macro=false +nl_squeeze_ifdef=false +nl_ds_struct_enum_cmt=false +nl_ds_struct_enum_close_brace=false +nl_create_if_one_liner=false +nl_create_for_one_liner=false +nl_create_while_one_liner=false +ls_for_split_full=false +ls_func_split_full=true +nl_after_multiline_comment=false +eat_blanks_after_open_brace=true +eat_blanks_before_close_brace=true +mod_full_brace_if_chain=false +mod_pawn_semicolon=false +mod_full_paren_if_bool=false +mod_remove_extra_semicolon=false +mod_sort_import=false +mod_sort_using=false +mod_sort_include=false +mod_move_case_break=false +mod_remove_empty_return=false +cmt_indent_multi=true +cmt_c_group=false +cmt_c_nl_start=false +cmt_c_nl_end=false +cmt_cpp_group=false +cmt_cpp_nl_start=false +cmt_cpp_nl_end=false +cmt_cpp_to_c=false +cmt_star_cont=false +cmt_multi_check_last=true +cmt_insert_before_preproc=false +pp_indent=ignore +pp_if_indent_code=false +input_tab_size=2 +indent_columns=2 +indent_label=0 +align_pp_define_span=0 +nl_start_of_file=remove +nl_end_of_file_min=1 +code_width=0 +nl_max=2 +nl_comment_func_def=1 +cmt_width=0 +utf8_bom=remove +indent_with_tabs=0 +sp_before_assign=add +sp_after_assign=add +sp_bool=add +sp_compare=add +sp_inside_paren=remove +sp_before_sparen=force +sp_paren_paren=ignore +sp_inside_sparen=ignore +sp_after_sparen=force +sp_before_square=remove +sp_before_squares=remove +sp_inside_square=remove +sp_after_comma=force +sp_before_comma=remove +sp_paren_comma=remove +sp_inside_braces=add +sp_inside_braces_empty=remove +sp_func_def_paren=remove +sp_inside_fparen=remove +sp_func_call_paren=remove +sp_func_call_paren_empty=remove +sp_else_brace=force +sp_brace_else=force +sp_sign=remove +sp_incdec=remove +sp_cmt_cpp_start=ignore +sp_endif_cmt=force +nl_end_of_file=add +nl_enum_brace=remove +nl_struct_brace=remove +nl_union_brace=remove +nl_for_brace=remove +nl_brace_finally=remove +nl_while_brace=remove +nl_do_brace=remove +nl_brace_while=remove +nl_switch_brace=remove +nl_if_brace=remove +nl_brace_else=remove +nl_elseif_brace=remove +nl_else_brace=remove +nl_fdef_brace=add +mod_full_brace_do=force +mod_full_brace_if=force +mod_full_brace_while=ignore +mod_full_brace_for=force +mod_full_brace_function=force +sp_cmt_cpp_doxygen=true +cmt_sp_after_star_cont=3 +align_keep_extra_space=True +align_var_def_star_style=1 +align_var_def_amp_style=1 +sp_after_type=ignore +pos_arith=lead +pos_bool=lead +pos_compare=lead +pos_conditional=lead +pos_comma=trail +sp_arith=add +sp_assign=add +sp_pp_concat=ignore +# Indent the 'case' label from the 'switch' header (coding standard §4.4.3) +# Note: Must come *after* the declaration of 'indent_columns'! +indent_switch_case=indent_columns diff --git a/.github/workflows/00-Check-Code-Convention.yml b/.github/workflows/00-Check-Code-Convention.yml index de3fa66..6c9acf6 100644 --- a/.github/workflows/00-Check-Code-Convention.yml +++ b/.github/workflows/00-Check-Code-Convention.yml @@ -88,3 +88,14 @@ jobs: name: CodingConventionResult path: CodingConventionTool.txt retention-days: 90 + - name: Check log file to set status of the job + run: | + keywords=("Failed") + for keyword in "${keywords[@]}"; do + if grep -q "$keyword" CodingConventionTool.txt; then + echo "Keyword '$keyword' found in the file." + exit 1 + else + echo "Keyword '$keyword' not found in the file." + fi + done diff --git a/.github/workflows/01-CLA-Assistant.yml b/.github/workflows/01-CLA-Assistant.yml index 1184aa9..4d2c85a 100644 --- a/.github/workflows/01-CLA-Assistant.yml +++ b/.github/workflows/01-CLA-Assistant.yml @@ -32,7 +32,7 @@ jobs: # branch should not be protected branch: 'debug' allowlist: silabs-*,bot* - # the followings are the optional inputs - If the optional inputs are not given, then default values will be taken + # the following are the optional inputs - If the optional inputs are not given, then default values will be taken remote-organization-name: "SiliconLabsInternal" remote-repository-name: "contributor-license-agreements" create-file-commit-message: "Created the CLA database file. CLA Assistant Lite bot created this file." diff --git a/.github/workflows/04-TruffleHog-Security-Scan.yml b/.github/workflows/04-TruffleHog-Security-Scan.yml index 478e0dd..6e22d0e 100644 --- a/.github/workflows/04-TruffleHog-Security-Scan.yml +++ b/.github/workflows/04-TruffleHog-Security-Scan.yml @@ -16,4 +16,4 @@ jobs: - name: Secret Scanning uses: trufflesecurity/trufflehog@v3.84.0 with: - extra_args: --only-verified \ No newline at end of file + extra_args: --only-verified diff --git a/.gitignore b/.gitignore index 5f7fa89..9efea4a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,18 +1,18 @@ -*.launch -*.orig -*.bak -*.html -*.png -.vscode/ -**/build/ -**/GNU ARM v* -**/.cproject -**/.project -**/.projectlinkstore -**/.settings -**/.makefile -**/.trash -**/.pdm -**/.uceditor -**/autogen/*.crc -**/__pycache__ +*.launch +*.orig +*.bak +*.html +*.png +.vscode/ +**/build/ +**/GNU ARM v* +**/.cproject +**/.project +**/.projectlinkstore +**/.settings +**/.makefile +**/.trash +**/.pdm +**/.uceditor +**/autogen/*.crc +**/__pycache__ diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index c36d7d4..24edeb5 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,26 +1,26 @@ -exclude: .*/build/.*|.*/gecko_sdk.*/.*|.*/autogen/.* -repos: -- repo: https://github.com/pre-commit/pre-commit-hooks - rev: v4.0.1 - hooks: - - id: end-of-file-fixer - - id: trailing-whitespace -- repo: https://github.com/codespell-project/codespell - rev: v2.2.4 - hooks: - - id: codespell - args: [-w,--config,./tools/.codespell/.codespellrc] -- repo: https://github.com/pocc/pre-commit-hooks - rev: v1.3.5 - hooks: - - id: uncrustify - args: [-c,./tools/uncrustify.cfg,-lC,--no-backup,--replace] - - id: clang-tidy - args: - - --config-file=./tools/.clang-tidy - - --use-color - - --extra-arg=-I/inc - - --header-filter:'^((?!test).)*$' - - -p=./build - - id: cppcheck - args: [--language=c,--std=c99,--check-config,--suppress=missingInclude,--suppress=unmatchedSuppression] +exclude: .*/build/.*|.*/gecko_sdk.*/.*|.*/autogen/.* +repos: +- repo: https://github.com/pre-commit/pre-commit-hooks + rev: v4.0.1 + hooks: + - id: end-of-file-fixer + - id: trailing-whitespace +- repo: https://github.com/codespell-project/codespell + rev: v2.2.4 + hooks: + - id: codespell + args: [-w,--config,./tools/.codespell/.codespellrc] +- repo: https://github.com/pocc/pre-commit-hooks + rev: v1.3.5 + hooks: + - id: uncrustify + args: [-c,./tools/uncrustify.cfg,-lC,--no-backup,--replace] + - id: clang-tidy + args: + - --config-file=./tools/.clang-tidy + - --use-color + - --extra-arg=-I/inc + - --header-filter:'^((?!test).)*$' + - -p=./build + - id: cppcheck + args: [--language=c,--std=c99,--check-config,--suppress=missingInclude,--suppress=unmatchedSuppression] diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md index 9b4c6b5..410b69c 100644 --- a/CODE_OF_CONDUCT.md +++ b/CODE_OF_CONDUCT.md @@ -140,4 +140,4 @@ For answers to common questions about this code of conduct, see the FAQ at [v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html [mozilla coc]: https://github.com/mozilla/diversity [faq]: https://www.contributor-covenant.org/faq -[translations]: https://www.contributor-covenant.org/translations \ No newline at end of file +[translations]: https://www.contributor-covenant.org/translations diff --git a/Dockerfile b/Dockerfile index 4e4728c..60923a1 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,93 +1,93 @@ -FROM ubuntu:jammy - -ARG UID=1000 -ARG GID=1000 - -ENV TZ=Europe/Budapest - -#Tested for x86_64 and aarch64 -ARG ARCH=x86_64 -ARG SONARQUBE=false - -RUN groupadd --gid $GID jenkins -RUN useradd --home /home/jenkins --create-home --shell /bin/sh --uid $UID --gid $GID jenkins - -RUN apt-get update && \ - apt-get install --no-install-recommends -y \ - software-properties-common \ - gpg-agent && \ - add-apt-repository ppa:openjdk-r/ppa && \ - apt-get install --no-install-recommends -y \ - clang \ - clang-tidy \ - cppcheck \ - git \ - build-essential \ - curl \ - jq \ - python3-dev \ - python3-pip \ - ninja-build \ - make \ - wget \ - zip \ - unzip \ - libgl1 \ - libglib2.0-0 \ - libpcre2-dev \ - openjdk-17-jdk \ - && rm -rf /var/lib/apt/lists/* - -#Install newer version of CMake 3.25.4 because Ubuntu 22.04 has 3.16.3 - -RUN wget https://github.com/Kitware/CMake/releases/download/v3.25.3/cmake-3.25.3-linux-${ARCH}.sh \ - -q -O /tmp/cmake-install.sh \ - && chmod u+x /tmp/cmake-install.sh \ - && mkdir /opt/cmake-3.25.3 \ - && /tmp/cmake-install.sh --skip-license --prefix=/opt/cmake-3.25.3 \ - && rm /tmp/cmake-install.sh \ - && ln -s /opt/cmake-3.25.3/bin/* /usr/local/bin - -# install GNU Arm Embedded Toolchain -ARG ARM_GCC_URL="https://developer.arm.com/-/media/Files/downloads/gnu/12.2.rel1/binrel/arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi.tar.xz" -RUN cd /tmp/ \ - && wget "$ARM_GCC_URL" \ - && tar -xf arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi.tar.xz \ - && mv arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi /opt/gcc-arm-none-eabi \ - && rm arm-gnu-toolchain-12.2.rel-${ARCH}-arm-none-eabi -rf - -#install Simplicity Commander -WORKDIR /home/jenkins -RUN wget https://www.silabs.com/documents/login/software/SimplicityCommander-Linux.zip \ - && unzip SimplicityCommander-Linux.zip \ - && tar -xf SimplicityCommander-Linux/Commander-cli_linux_${ARCH}_*.tar.bz \ - && mv commander-cli /opt/commander-cli \ - && rm -rf SimplicityCommander-Linux.zip SimplicityCommander-Linux - -# Download and install SONARQUBE scanner -RUN if [ "$SONARQUBE" = "true" ]; then \ - curl -L -o /tmp/sonar-scanner-cli.zip -k https://binaries.sonarsource.com/Distribution/sonar-scanner-cli/sonar-scanner-cli-6.1.0.4477-linux-x64.zip \ - && unzip /tmp/sonar-scanner-cli.zip -d /opt \ - && ln -s /opt/sonar-scanner-6.1.0.4477-linux-x64/bin/sonar-scanner /usr/local/bin/sonar-scanner \ - && rm /tmp/sonar-scanner-cli.zip; \ - fi - -# Download and install build-wrapper -RUN if [ "$SONARQUBE" = "true" ]; then \ - curl -L -o /tmp/build-wrapper-linux-${ARCH}.zip -k https://sonarqube.silabs.net/static/cpp/build-wrapper-linux-x86.zip \ - && unzip /tmp/build-wrapper-linux-${ARCH}.zip -d /opt \ - && ln -s /opt/build-wrapper-linux-x86/build-wrapper-linux-x86-64 /usr/local/bin/build-wrapper \ - && rm /tmp/build-wrapper-linux-${ARCH}.zip; \ - fi - -USER jenkins - -ENV JAVA_HOME=/usr/lib/jvm/java-17-openjdk-amd64 -ENV PATH="${JAVA_HOME}/bin:${PATH}" -ENV POST_BUILD_EXE="/opt/commander-cli/commander-cli" -ENV ARM_GCC_DIR="/opt/gcc-arm-none-eabi/" -ENV PATH="${PATH}:/opt/gcc-arm-none-eabi/bin" -ENV PATH="${PATH}:/usr/local/bin" - -ENV PATH="${PATH}:/opt/build-wrapper-linux-x86/" -WORKDIR /home/jenkins +FROM ubuntu:jammy + +ARG UID=1000 +ARG GID=1000 + +ENV TZ=Europe/Budapest + +#Tested for x86_64 and aarch64 +ARG ARCH=x86_64 +ARG SONARQUBE=false + +RUN groupadd --gid $GID jenkins +RUN useradd --home /home/jenkins --create-home --shell /bin/sh --uid $UID --gid $GID jenkins + +RUN apt-get update && \ + apt-get install --no-install-recommends -y \ + software-properties-common \ + gpg-agent && \ + add-apt-repository ppa:openjdk-r/ppa && \ + apt-get install --no-install-recommends -y \ + clang \ + clang-tidy \ + cppcheck \ + git \ + build-essential \ + curl \ + jq \ + python3-dev \ + python3-pip \ + ninja-build \ + make \ + wget \ + zip \ + unzip \ + libgl1 \ + libglib2.0-0 \ + libpcre2-dev \ + openjdk-17-jdk \ + && rm -rf /var/lib/apt/lists/* + +#Install newer version of CMake 3.25.4 because Ubuntu 22.04 has 3.16.3 + +RUN wget https://github.com/Kitware/CMake/releases/download/v3.25.3/cmake-3.25.3-linux-${ARCH}.sh \ + -q -O /tmp/cmake-install.sh \ + && chmod u+x /tmp/cmake-install.sh \ + && mkdir /opt/cmake-3.25.3 \ + && /tmp/cmake-install.sh --skip-license --prefix=/opt/cmake-3.25.3 \ + && rm /tmp/cmake-install.sh \ + && ln -s /opt/cmake-3.25.3/bin/* /usr/local/bin + +# install GNU Arm Embedded Toolchain +ARG ARM_GCC_URL="https://developer.arm.com/-/media/Files/downloads/gnu/12.2.rel1/binrel/arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi.tar.xz" +RUN cd /tmp/ \ + && wget "$ARM_GCC_URL" \ + && tar -xf arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi.tar.xz \ + && mv arm-gnu-toolchain-12.2.rel1-${ARCH}-arm-none-eabi /opt/gcc-arm-none-eabi \ + && rm arm-gnu-toolchain-12.2.rel-${ARCH}-arm-none-eabi -rf + +#install Simplicity Commander +WORKDIR /home/jenkins +RUN wget https://www.silabs.com/documents/login/software/SimplicityCommander-Linux.zip \ + && unzip SimplicityCommander-Linux.zip \ + && tar -xf SimplicityCommander-Linux/Commander-cli_linux_${ARCH}_*.tar.bz \ + && mv commander-cli /opt/commander-cli \ + && rm -rf SimplicityCommander-Linux.zip SimplicityCommander-Linux + +# Download and install SONARQUBE scanner +RUN if [ "$SONARQUBE" = "true" ]; then \ + curl -L -o /tmp/sonar-scanner-cli.zip -k https://binaries.sonarsource.com/Distribution/sonar-scanner-cli/sonar-scanner-cli-6.1.0.4477-linux-x64.zip \ + && unzip /tmp/sonar-scanner-cli.zip -d /opt \ + && ln -s /opt/sonar-scanner-6.1.0.4477-linux-x64/bin/sonar-scanner /usr/local/bin/sonar-scanner \ + && rm /tmp/sonar-scanner-cli.zip; \ + fi + +# Download and install build-wrapper +RUN if [ "$SONARQUBE" = "true" ]; then \ + curl -L -o /tmp/build-wrapper-linux-${ARCH}.zip -k https://sonarqube.silabs.net/static/cpp/build-wrapper-linux-x86.zip \ + && unzip /tmp/build-wrapper-linux-${ARCH}.zip -d /opt \ + && ln -s /opt/build-wrapper-linux-x86/build-wrapper-linux-x86-64 /usr/local/bin/build-wrapper \ + && rm /tmp/build-wrapper-linux-${ARCH}.zip; \ + fi + +USER jenkins + +ENV JAVA_HOME=/usr/lib/jvm/java-17-openjdk-amd64 +ENV PATH="${JAVA_HOME}/bin:${PATH}" +ENV POST_BUILD_EXE="/opt/commander-cli/commander-cli" +ENV ARM_GCC_DIR="/opt/gcc-arm-none-eabi/" +ENV PATH="${PATH}:/opt/gcc-arm-none-eabi/bin" +ENV PATH="${PATH}:/usr/local/bin" + +ENV PATH="${PATH}:/opt/build-wrapper-linux-x86/" +WORKDIR /home/jenkins diff --git a/LICENSE b/LICENSE index 8efae93..6c828cd 100644 --- a/LICENSE +++ b/LICENSE @@ -1,10 +1,10 @@ -**Copyright 2024 Silicon Laboratories Inc. [www.silabs.com](https://www.silabs.com/)** - -Source code in this repo is covered by one of several different licenses. -The default license is the Master Software License Agreement (MSLA) -[www.silabs.com/about-us/legal/master-software-license-agreement](), -which applies unless otherwise noted. - -During the unit test build process, some third-party code will be added to this -repository and separated into another license. An example can be found in the -build/_deps directory, where the Unity library uses the MIT license. +**Copyright 2024 Silicon Laboratories Inc. [www.silabs.com](https://www.silabs.com/)** + +Source code in this repo is covered by one of several different licenses. +The default license is the Master Software License Agreement (MSLA) +[www.silabs.com/about-us/legal/master-software-license-agreement](), +which applies unless otherwise noted. + +During the unit test build process, some third-party code will be added to this +repository and separated into another license. An example can be found in the +build/_deps directory, where the Unity library uses the MIT license. diff --git a/Makefile b/Makefile index 693b251..27412db 100644 --- a/Makefile +++ b/Makefile @@ -1,11 +1,11 @@ -.SUFFIXES: # ignore builtin rules -.PHONY: all locator_host locator_ncp - -TARGET ?= clean_build -TYPE ?= Debug #Release - -all: locator_host locator_ncp - -locator_host locator_ncp: - @echo 'Building $@...!' - ${MAKE} -C $@ ${TARGET} TYPE=${TYPE} +.SUFFIXES: # ignore builtin rules +.PHONY: all locator_host locator_ncp + +TARGET ?= clean_build +TYPE ?= Debug #Release + +all: locator_host locator_ncp + +locator_host locator_ncp: + @echo 'Building $@...!' + ${MAKE} -C $@ ${TARGET} TYPE=${TYPE} diff --git a/cla.md b/cla.md index ce48663..af3aaef 100644 --- a/cla.md +++ b/cla.md @@ -1,31 +1,31 @@ -# Silicon Labs Contributor License Agreement - -By accepting this Contributor License Agreement, You understand and agree that project(s) and Contribution(s) are public and that a record of any contribution (including any personal information submitted such as full name and email address) will be maintained indefinitely and may be redistributed consistent with this project. -To clarify the intellectual property license granted with a Contribution from any person or entity, Silicon Laboratories Inc. ("Silicon Labs") requires acceptance of this Contributor License Agreement ("CLA") thereby indicating agreement to the license terms below. This license is for Your protection as a Contributor as well as the protection of Silicon Labs and users. This CLA can be executed by an individual or a corporate entity to authorize Contribution(s) to Silicon Labs Unify Software Development Kit (SDK) (the “Project”). -You accept and agree to the following terms and conditions for any Contribution submitted to Silicon Labs. Except for the license granted herein to Silicon Labs and recipients of software distributed by Silicon Labs, You reserve all right, title, and interest in and to Your Contribution(s). - -1. **Definitions**. "You" (or "Your") shall mean the copyright owner or legal entity authorized by the copyright owner that is entering into this CLA with Silicon Labs. For legal entities, the entity making a Contribution and all other entities that control, are controlled by, or are under common control with that entity are considered to be a single Contributor. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. "Contribution" shall mean any original work of authorship, including any modifications or additions to an existing work, that is intentionally submitted by You to Silicon Labs for inclusion in, or documentation of, any part of the Project. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to Silicon Labs or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, Silicon Labs for the purpose of discussing and improving the Project, but excluding a communication that is conspicuously marked or otherwise designated in writing by You as "Not a Contribution." Notwithstanding anything else in this definition, any pull request (PR) submitted by You will be a “Contribution.” - -2. **Grant of Copyright License**. Subject to the terms and conditions of this CLA, You hereby grant to Silicon Labs and to recipients of software distributed by Silicon Labs a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare derivative works of, publicly display, publicly perform, sublicense, and distribute Your Contribution(s) and such derivative works. - -3. **Grant of Patent License**. Subject to the terms and conditions of this CLA, You hereby grant to Silicon Labs and to recipients of software distributed by Silicon Labs a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Project or the Contribution, where such license applies only to those patent claims licensable by You that are necessarily infringed by Your Contribution(s) alone or by combination of Your Contribution(s) with the Project to which such Contribution(s) was submitted. If any entity institutes patent litigation against You or any other entity (including a cross-claim or counterclaim in a lawsuit) alleging that Your Contribution, or the Project to which You have contributed, constitutes direct or contributory patent infringement, then any patent licenses granted to that entity under this CLA for that Contribution or Project shall terminate as of the date such litigation is filed. - -4. **Individual Contributors**. You represent that You are legally entitled to grant the above license. If Your employer has rights to intellectual property that You create that includes Your Contribution(s), You represent that You have received permission to make such Contribution(s) on behalf of that employer, that Your employer has waived such rights for such Contribution(s) to Silicon Labs, or that Your employer has executed this or a separate CLA with Silicon Labs. - -5. **Corporate Contributors**. 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Unless required by applicable law or agreed to in writing, You provide Your Contribution(s) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. - -8. **Third Party Submissions**. Should You wish to submit work that is not Your original creation, You must submit it to Silicon Labs separately from any Contribution, identifying the complete details of its source and of any license or other restriction (including, but not limited to, related patents, trademarks, and license agreements) of which You are personally aware, and conspicuously marking the work as "Submitted on behalf of a third-party: [named here]". - -9. **No Obligation to Accept**. Silicon Labs is not obligated to accept Your Contribution to the Project. Although Silicon Labs will review Your Contribution, neither accepting nor rejecting Your Contribution implies any form of endorsement, approval or comment on Your Contribution. - -10. **Term**. This CLA shall come into effect upon Your acceptance below and shall apply to all Contribution(s) to Silicon Labs. - -11. **Updates**. You agree to notify Silicon Labs of any facts or circumstances of which You become aware that would make these representations inaccurate in any respect. - -12. **Governing Law**. The CLA is governed by the laws and construed in accordance with the laws of the State of Texas, excluding its conflicts of laws provisions. Any legal action or proceeding arising out of or relating to this CLA shall be exclusively subject to the laws venue of the courts located in Travis County, Texas. - -13. **Entire Agreement**. This CLA constitutes the entire agreement between You and Silicon Labs regarding Your Contributions to the Project and supersedes any prior agreements, understandings or representations, whether oral or written. +# Silicon Labs Contributor License Agreement + +By accepting this Contributor License Agreement, You understand and agree that project(s) and Contribution(s) are public and that a record of any contribution (including any personal information submitted such as full name and email address) will be maintained indefinitely and may be redistributed consistent with this project. +To clarify the intellectual property license granted with a Contribution from any person or entity, Silicon Laboratories Inc. ("Silicon Labs") requires acceptance of this Contributor License Agreement ("CLA") thereby indicating agreement to the license terms below. This license is for Your protection as a Contributor as well as the protection of Silicon Labs and users. This CLA can be executed by an individual or a corporate entity to authorize Contribution(s) to Silicon Labs Unify Software Development Kit (SDK) (the “Project”). +You accept and agree to the following terms and conditions for any Contribution submitted to Silicon Labs. Except for the license granted herein to Silicon Labs and recipients of software distributed by Silicon Labs, You reserve all right, title, and interest in and to Your Contribution(s). + +1. **Definitions**. "You" (or "Your") shall mean the copyright owner or legal entity authorized by the copyright owner that is entering into this CLA with Silicon Labs. For legal entities, the entity making a Contribution and all other entities that control, are controlled by, or are under common control with that entity are considered to be a single Contributor. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity. "Contribution" shall mean any original work of authorship, including any modifications or additions to an existing work, that is intentionally submitted by You to Silicon Labs for inclusion in, or documentation of, any part of the Project. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to Silicon Labs or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, Silicon Labs for the purpose of discussing and improving the Project, but excluding a communication that is conspicuously marked or otherwise designated in writing by You as "Not a Contribution." Notwithstanding anything else in this definition, any pull request (PR) submitted by You will be a “Contribution.” + +2. **Grant of Copyright License**. Subject to the terms and conditions of this CLA, You hereby grant to Silicon Labs and to recipients of software distributed by Silicon Labs a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare derivative works of, publicly display, publicly perform, sublicense, and distribute Your Contribution(s) and such derivative works. + +3. **Grant of Patent License**. Subject to the terms and conditions of this CLA, You hereby grant to Silicon Labs and to recipients of software distributed by Silicon Labs a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Project or the Contribution, where such license applies only to those patent claims licensable by You that are necessarily infringed by Your Contribution(s) alone or by combination of Your Contribution(s) with the Project to which such Contribution(s) was submitted. If any entity institutes patent litigation against You or any other entity (including a cross-claim or counterclaim in a lawsuit) alleging that Your Contribution, or the Project to which You have contributed, constitutes direct or contributory patent infringement, then any patent licenses granted to that entity under this CLA for that Contribution or Project shall terminate as of the date such litigation is filed. + +4. **Individual Contributors**. You represent that You are legally entitled to grant the above license. If Your employer has rights to intellectual property that You create that includes Your Contribution(s), You represent that You have received permission to make such Contribution(s) on behalf of that employer, that Your employer has waived such rights for such Contribution(s) to Silicon Labs, or that Your employer has executed this or a separate CLA with Silicon Labs. + +5. **Corporate Contributors**. If a corporation or other business entity executes this CLA, employee(s) or contractor(s) authorized to make Contribution(s) should be identified by You as part of Your Contribution. Employee(s) or contractor(s) submitting one or more PR(s) will be treated as authorized to make Contribution(s). + +6. **Original Works**. You represent that each of Your Contribution(s) is Your original creation (see section 8 for submissions on behalf of others). You also represent that Your Contribution submissions include complete details of any third-party license or other restriction (including, but not limited to, related patents and trademarks) of which You are personally aware and which are associated with any part of Your Contribution(s). + +7. **Support**. You are not expected to provide support to others for Your Contribution(s), except to the extent You desire to provide support. You may provide support to others for free, for a fee, or not at all. Unless required by applicable law or agreed to in writing, You provide Your Contribution(s) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. + +8. **Third Party Submissions**. Should You wish to submit work that is not Your original creation, You must submit it to Silicon Labs separately from any Contribution, identifying the complete details of its source and of any license or other restriction (including, but not limited to, related patents, trademarks, and license agreements) of which You are personally aware, and conspicuously marking the work as "Submitted on behalf of a third-party: [named here]". + +9. **No Obligation to Accept**. Silicon Labs is not obligated to accept Your Contribution to the Project. Although Silicon Labs will review Your Contribution, neither accepting nor rejecting Your Contribution implies any form of endorsement, approval or comment on Your Contribution. + +10. **Term**. This CLA shall come into effect upon Your acceptance below and shall apply to all Contribution(s) to Silicon Labs. + +11. **Updates**. You agree to notify Silicon Labs of any facts or circumstances of which You become aware that would make these representations inaccurate in any respect. + +12. **Governing Law**. The CLA is governed by the laws and construed in accordance with the laws of the State of Texas, excluding its conflicts of laws provisions. Any legal action or proceeding arising out of or relating to this CLA shall be exclusively subject to the laws venue of the courts located in Travis County, Texas. + +13. **Entire Agreement**. This CLA constitutes the entire agreement between You and Silicon Labs regarding Your Contributions to the Project and supersedes any prior agreements, understandings or representations, whether oral or written. diff --git a/data_format_sample.c b/data_format_sample.c index 102d109..eef27ba 100644 --- a/data_format_sample.c +++ b/data_format_sample.c @@ -1,80 +1,80 @@ -#include -#include - -#define SL_UNUSED_PARAMETER(param) (void) (param) -const unsigned int SL_MAX_UART_CONNECTIONS = 3; -uint8_t sl_uart_char; - -typedef enum { - SL_CARD_SPADE, - SL_CARD_HEART, - SL_CARD_CLUB, - SL_CARD_DIAMOND -} sl_card_suit_t; - -typedef struct { - uint32_t hour; - uint32_t minute; - uint32_t second; -} sl_time_t; - -sl_time_t sl_time; - -void sl_do_something(uint8_t bar) -{ - // uint8_t arr[100]; //magic number - uint8_t foo = 1; - if (foo > bar) { // The preceding brace is *required* - do_this(); - } else if (foo < bar) { - do_that(); - } else { - do_another_thing(); - } - - if (foo > bar) { - do_this(); - } - - while (1) { - } - - do { - sli_do_work(); - } while (foo); - - switch (bar) { - case 1: - sli_do_this(); - break; - - case 2: - sli_do_that(); - break; - - case 3: - { - sli_do_the_other_thing(); - break; - } - - case 0: - default: - sli_do_what(); - break; - } -} - -void sl_do_something2(int a, - int b, - int c, - const char *string1, - const char *string2) -{ - // ... -} - -void sli_do_something(int a, int b, int c) -{ - // ... -} +#include +#include + +#define SL_UNUSED_PARAMETER(param) (void) (param) +const unsigned int SL_MAX_UART_CONNECTIONS = 3; +uint8_t sl_uart_char; + +typedef enum { + SL_CARD_SPADE, + SL_CARD_HEART, + SL_CARD_CLUB, + SL_CARD_DIAMOND +} sl_card_suit_t; + +typedef struct { + uint32_t hour; + uint32_t minute; + uint32_t second; +} sl_time_t; + +sl_time_t sl_time; + +void sl_do_something(uint8_t bar) +{ + // uint8_t arr[100]; //magic number + uint8_t foo = 1; + if (foo > bar) { // The preceding brace is *required* + do_this(); + } else if (foo < bar) { + do_that(); + } else { + do_another_thing(); + } + + if (foo > bar) { + do_this(); + } + + while (1) { + } + + do { + sli_do_work(); + } while (foo); + + switch (bar) { + case 1: + sli_do_this(); + break; + + case 2: + sli_do_that(); + break; + + case 3: + { + sli_do_the_other_thing(); + break; + } + + case 0: + default: + sli_do_what(); + break; + } +} + +void sl_do_something2(int a, + int b, + int c, + const char *string1, + const char *string2) +{ + // ... +} + +void sli_do_something(int a, int b, int c) +{ + // ... +} diff --git a/locator_host/Makefile b/locator_host/Makefile index 87983e6..1e59d8d 100644 --- a/locator_host/Makefile +++ b/locator_host/Makefile @@ -1,17 +1,17 @@ -.SUFFIXES: # ignore builtin rules -.PHONY: clean configure build clean_build - -TYPE ?= Debug #Release -BUILD_DIR ?= build - -clean_build: clean configure build - -clean: - @echo 'Cleaning every build directory!' - rm -rf ${BUILD_DIR} -configure: - @echo 'CMAKE configure...!' - cmake locator_host_cmake -B ${BUILD_DIR} -G "Ninja" -DCMAKE_BUILD_TYPE:STRING=${TYPE} -DCMAKE_TOOLCHAIN_FILE:STRING=toolchain.cmake -build: - @echo 'CMAKE build...!' - cmake --build ${BUILD_DIR} --parallel --config ${TYPE} +.SUFFIXES: # ignore builtin rules +.PHONY: clean configure build clean_build + +TYPE ?= Debug #Release +BUILD_DIR ?= build + +clean_build: clean configure build + +clean: + @echo 'Cleaning every build directory!' + rm -rf ${BUILD_DIR} +configure: + @echo 'CMAKE configure...!' + cmake locator_host_cmake -B ${BUILD_DIR} -G "Ninja" -DCMAKE_BUILD_TYPE:STRING=${TYPE} -DCMAKE_TOOLCHAIN_FILE:STRING=toolchain.cmake +build: + @echo 'CMAKE build...!' + cmake --build ${BUILD_DIR} --parallel --config ${TYPE} diff --git a/locator_host/app.c b/locator_host/app.c index 0693cf3..03b3dd1 100644 --- a/locator_host/app.c +++ b/locator_host/app.c @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief Core application logic. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include "app.h" -#include "app_log.h" -#include "em_rmu.h" -#include "sl_watchdog.h" -#include "sl_timer.h" -#include "sl_bt_aoa.h" - -//macros ----------------------------------------------------------------------- -#define SLI_APP_SATURATE(number, min, max) ((number) > (max)) ? (max) : ((number) < (min)) ? (min) : (number) -#define sli_app_mqtt_create_topic(topic_buff, sub_topic, locator_id, tag_id) \ - snprintf((char *)(topic_buff), \ - sizeof(topic_buff), \ - "silabs/aoa/" sub_topic "/%06llX/%06llX", \ - locator_id, tag_id) - -//private type definitions ----------------------------------------------------- -//private function prototypes -------------------------------------------------- -//private variables ------------------------------------------------------------ -static app_mqtt_data_t sli_app_mqtt_message; - -//function definitions---------------------------------------------------------- - -/**************************************************************************//** - * Application Init. - *****************************************************************************/ -void app_init(void) -{ - sl_watchdog_init(); //MUST be the first! - app_log_warning("\r\n\r\nApplication reset! Reason: 0x%lX\r\n", RMU_ResetCauseGet()); - - sl_timer_init(); - sl_bt_aoa_init(); -} - -/**************************************************************************//** - * Application Process Action. - *****************************************************************************/ -void app_process_action(void) -{ - sl_watchdog_feed(); -} - -void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_iq_report_t *iq) -{ - int len = sli_app_mqtt_create_topic(sli_app_mqtt_message.topic, "iq", locator_id->system_id, tag_id->system_id); - sli_app_mqtt_message.topic_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.topic)); - -#if SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD == SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_RAW_BYTES - sli_app_mqtt_message.content_length = SLI_APP_SATURATE(iq->length, 0, sizeof(sli_app_mqtt_message.content)); - memcpy(sli_app_mqtt_message.content, iq->samples, sli_app_mqtt_message.content_length); -#elif SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD == SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON - #define JSON_END "\"\n}\n" - const int max_content_size = sizeof(sli_app_mqtt_message.content) - sizeof(JSON_END); //terminating characters shall fit - const char *hex = "0123456789ABCDEF"; - - len = snprintf((char *)sli_app_mqtt_message.content, - sizeof(sli_app_mqtt_message.content), - "{\n\"channel\": %u,\n" - "\"rssi\": %d,\n" - "\"sequence\": %u,\n" - "\"samples\": \"",//extra spaces, so that ending will surely fit even when sample buffer is small - iq->channel, iq->rssi, iq->event_counter); - sli_app_mqtt_message.content_length = SLI_APP_SATURATE(len, 0, max_content_size); - - for (size_t i = 0; (i < iq->length) && (sli_app_mqtt_message.content_length < max_content_size); i++) { - sli_app_mqtt_message.content[sli_app_mqtt_message.content_length++] = hex[(iq->samples[i] >> 4) & 0xF]; - sli_app_mqtt_message.content[sli_app_mqtt_message.content_length++] = hex[(iq->samples[i]) & 0xF]; - } - memcpy(&sli_app_mqtt_message.content[sli_app_mqtt_message.content_length], JSON_END, sizeof(JSON_END)); - sli_app_mqtt_message.content_length += (sizeof(JSON_END) - 1); -#else - #error Unsupported SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD! -#endif - - app_mqtt_client_publish(&sli_app_mqtt_message); -} - -void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_angle_t *angle) -{ - int len = sli_app_mqtt_create_topic(sli_app_mqtt_message.topic, "angle", locator_id->system_id, tag_id->system_id); - sli_app_mqtt_message.topic_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.topic)); - - len = snprintf((char *)sli_app_mqtt_message.content, - sizeof(sli_app_mqtt_message.content), - "{\n\"azimuth\": %.2f,\n\"azimuth_stdev\": %.2f,\n" - "\"elevation\": %.2f,\n\"elevation_stdev\": %.2f,\n" - "\"distance\": %.2f,\n\"distance_stdev\": %.2f,\n" - "\"sequence\": %lu\n}\n", - angle->azimuth, angle->azimuth_stdev, - angle->elevation, angle->elevation_stdev, - angle->distance, angle->distance_stdev, - angle->sequence); - sli_app_mqtt_message.content_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.content)); - - app_mqtt_client_publish(&sli_app_mqtt_message); -} - -int app_mqtt_client_publish(const app_mqtt_data_t *message) -{ - app_log_info("Topic: %s" APP_LOG_NL "%s" APP_LOG_NL, message->topic, message->content); - return 0; -} +/***************************************************************************//** + * @file + * @brief Core application logic. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include "app.h" +#include "app_log.h" +#include "em_rmu.h" +#include "sl_watchdog.h" +#include "sl_timer.h" +#include "sl_bt_aoa.h" + +//macros ----------------------------------------------------------------------- +#define SLI_APP_SATURATE(number, min, max) ((number) > (max)) ? (max) : ((number) < (min)) ? (min) : (number) +#define sli_app_mqtt_create_topic(topic_buff, sub_topic, locator_id, tag_id) \ + snprintf((char *)(topic_buff), \ + sizeof(topic_buff), \ + "silabs/aoa/" sub_topic "/%06llX/%06llX", \ + locator_id, tag_id) + +//private type definitions ----------------------------------------------------- +//private function prototypes -------------------------------------------------- +//private variables ------------------------------------------------------------ +static app_mqtt_data_t sli_app_mqtt_message; + +//function definitions---------------------------------------------------------- + +/**************************************************************************//** + * Application Init. + *****************************************************************************/ +void app_init(void) +{ + sl_watchdog_init(); //MUST be the first! + app_log_warning("\r\n\r\nApplication reset! Reason: 0x%lX\r\n", RMU_ResetCauseGet()); + + sl_timer_init(); + sl_bt_aoa_init(); +} + +/**************************************************************************//** + * Application Process Action. + *****************************************************************************/ +void app_process_action(void) +{ + sl_watchdog_feed(); +} + +void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_iq_report_t *iq) +{ + int len = sli_app_mqtt_create_topic(sli_app_mqtt_message.topic, "iq", locator_id->system_id, tag_id->system_id); + sli_app_mqtt_message.topic_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.topic)); + +#if SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD == SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_RAW_BYTES + sli_app_mqtt_message.content_length = SLI_APP_SATURATE(iq->length, 0, sizeof(sli_app_mqtt_message.content)); + memcpy(sli_app_mqtt_message.content, iq->samples, sli_app_mqtt_message.content_length); +#elif SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD == SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON + #define JSON_END "\"\n}\n" + const int max_content_size = sizeof(sli_app_mqtt_message.content) - sizeof(JSON_END); //terminating characters shall fit + const char *hex = "0123456789ABCDEF"; + + len = snprintf((char *)sli_app_mqtt_message.content, + sizeof(sli_app_mqtt_message.content), + "{\n\"channel\": %u,\n" + "\"rssi\": %d,\n" + "\"sequence\": %u,\n" + "\"samples\": \"",//extra spaces, so that ending will surely fit even when sample buffer is small + iq->channel, iq->rssi, iq->event_counter); + sli_app_mqtt_message.content_length = SLI_APP_SATURATE(len, 0, max_content_size); + + for (size_t i = 0; (i < iq->length) && (sli_app_mqtt_message.content_length < max_content_size); i++) { + sli_app_mqtt_message.content[sli_app_mqtt_message.content_length++] = hex[(iq->samples[i] >> 4) & 0xF]; + sli_app_mqtt_message.content[sli_app_mqtt_message.content_length++] = hex[(iq->samples[i]) & 0xF]; + } + memcpy(&sli_app_mqtt_message.content[sli_app_mqtt_message.content_length], JSON_END, sizeof(JSON_END)); + sli_app_mqtt_message.content_length += (sizeof(JSON_END) - 1); +#else + #error Unsupported SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD! +#endif + + app_mqtt_client_publish(&sli_app_mqtt_message); +} + +void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_angle_t *angle) +{ + int len = sli_app_mqtt_create_topic(sli_app_mqtt_message.topic, "angle", locator_id->system_id, tag_id->system_id); + sli_app_mqtt_message.topic_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.topic)); + + len = snprintf((char *)sli_app_mqtt_message.content, + sizeof(sli_app_mqtt_message.content), + "{\n\"azimuth\": %.2f,\n\"azimuth_stdev\": %.2f,\n" + "\"elevation\": %.2f,\n\"elevation_stdev\": %.2f,\n" + "\"distance\": %.2f,\n\"distance_stdev\": %.2f,\n" + "\"sequence\": %lu\n}\n", + angle->azimuth, angle->azimuth_stdev, + angle->elevation, angle->elevation_stdev, + angle->distance, angle->distance_stdev, + angle->sequence); + sli_app_mqtt_message.content_length = SLI_APP_SATURATE(len, 0, (int)sizeof(sli_app_mqtt_message.content)); + + app_mqtt_client_publish(&sli_app_mqtt_message); +} + +int app_mqtt_client_publish(const app_mqtt_data_t *message) +{ + app_log_info("Topic: %s" APP_LOG_NL "%s" APP_LOG_NL, message->topic, message->content); + return 0; +} diff --git a/locator_host/app.h b/locator_host/app.h index de0b095..8568481 100644 --- a/locator_host/app.h +++ b/locator_host/app.h @@ -1,81 +1,81 @@ -/***************************************************************************//** - * @file - * @brief Application interface provided to main(). - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef APP_H -#define APP_H -#ifdef __cplusplus -extern "C" { -#endif -#include "sl_system_config.h" - -//macros ----------------------------------------------------------------------- -#define APP_MQTT_CLIENT_MESSAGE_TOPIC_SIZE 64 -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED /*Space is needed for the Tags*/ - #define APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE 256 -#else - #define APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE 568 -#endif - -//type definitions ------------------------------------------------------------- -///Message buffer for the AOA data. -//safe to use this even in a multi-threaded environment because sl_bt_aoa_on_*_report() is called from 1 thread. -typedef struct { - uint8_t topic[APP_MQTT_CLIENT_MESSAGE_TOPIC_SIZE]; ///< Topic buffer. - uint32_t topic_length; ///< Length of the topic. - uint8_t content[APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE];///< Content buffer. - uint32_t content_length; ///< Length of the content. -} app_mqtt_data_t; - -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- -/**************************************************************************//** - * Application Init. - *****************************************************************************/ -void app_init(void); - -/**************************************************************************//** - * Application Process Action. - *****************************************************************************/ -void app_process_action(void); - -/***************************************************************************//** - * User shall implement this! - * Publishes the requested message to the MQTT broker. - * Weak implementation will log the MQTT message - * - * @param[in] app_mqtt_data_t MQTT message to send. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -int app_mqtt_client_publish(const app_mqtt_data_t *message); - -#ifdef __cplusplus -} -#endif -#endif // APP_H +/***************************************************************************//** + * @file + * @brief Application interface provided to main(). + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef APP_H +#define APP_H +#ifdef __cplusplus +extern "C" { +#endif +#include "sl_system_config.h" + +//macros ----------------------------------------------------------------------- +#define APP_MQTT_CLIENT_MESSAGE_TOPIC_SIZE 64 +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED /*Space is needed for the Tags*/ + #define APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE 256 +#else + #define APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE 568 +#endif + +//type definitions ------------------------------------------------------------- +///Message buffer for the AOA data. +//safe to use this even in a multi-threaded environment because sl_bt_aoa_on_*_report() is called from 1 thread. +typedef struct { + uint8_t topic[APP_MQTT_CLIENT_MESSAGE_TOPIC_SIZE]; ///< Topic buffer. + uint32_t topic_length; ///< Length of the topic. + uint8_t content[APP_MQTT_CLIENT_MESSAGE_PAYLOAD_SIZE];///< Content buffer. + uint32_t content_length; ///< Length of the content. +} app_mqtt_data_t; + +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- +/**************************************************************************//** + * Application Init. + *****************************************************************************/ +void app_init(void); + +/**************************************************************************//** + * Application Process Action. + *****************************************************************************/ +void app_process_action(void); + +/***************************************************************************//** + * User shall implement this! + * Publishes the requested message to the MQTT broker. + * Weak implementation will log the MQTT message + * + * @param[in] app_mqtt_data_t MQTT message to send. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +int app_mqtt_client_publish(const app_mqtt_data_t *message); + +#ifdef __cplusplus +} +#endif +#endif // APP_H diff --git a/locator_host/app_log.h b/locator_host/app_log.h index 84403a0..e71b0f2 100644 --- a/locator_host/app_log.h +++ b/locator_host/app_log.h @@ -1,102 +1,102 @@ -/***************************************************************************//** - * @file sl_app_log.h - * @brief Debug printing with assert functionality - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef COMMON_SL_APP_LOG_H_ -#define COMMON_SL_APP_LOG_H_ -#ifdef __cplusplus -extern "C" { -#endif -#include "printf.h" //SHALL NOT BE USED DIRECTLY! - -//macros ----------------------------------------------------------------------- -#define APP_LOG_LEVEL_CRITICAL 1 -#define APP_LOG_LEVEL_ERROR 2 -#define APP_LOG_LEVEL_WARNING 3 -#define APP_LOG_LEVEL_INFO 4 -#define APP_LOG_LEVEL_DEBUG 5 -#if DEBUG - #define APP_LOG_LEVEL APP_LOG_LEVEL_DEBUG -#else //PRODUCTION - #define APP_LOG_LEVEL APP_LOG_LEVEL_INFO -#endif -#define APP_LOG_NL "\r\n" - -#define APP_LOG_OS_MAX_QUEUE_SIZE (512) - -#define __APP_LOG_NUM_TO_STR(x) #x -#define APP_LOG_NUM_TO_STR(x) __APP_LOG_NUM_TO_STR(x) - -#define app_log(...) printf(__VA_ARGS__) -#define app_log_status(sc, ...) if (sc) app_log(__VA_ARGS__) - -#if APP_LOG_LEVEL >= APP_LOG_LEVEL_CRITICAL - #define app_log_critical(...) app_log(__VA_ARGS__) - #define app_log_status_critical(sc, ...) app_log_status(sc, __VA_ARGS__) -#else - #define app_log_critical(...) app_log_none(__VA_ARGS__) - #define app_log_status_critical(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) -#endif - - #if APP_LOG_LEVEL >= APP_LOG_LEVEL_ERROR - #define app_log_error(...) app_log(__VA_ARGS__) - #define app_log_status_error(sc, ...) app_log_status(sc, __VA_ARGS__) -#else - #define app_log_error(...) app_log_none(__VA_ARGS__) - #define app_log_status_error(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) -#endif - -#if APP_LOG_LEVEL >= APP_LOG_LEVEL_WARNING - #define app_log_warning(...) app_log(__VA_ARGS__) - #define app_log_status_warning(sc, ...) app_log_status(sc, __VA_ARGS__) -#else - #define app_log_warning(...) app_log_none(__VA_ARGS__) - #define app_log_status_warning(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) -#endif - -#if APP_LOG_LEVEL >= APP_LOG_LEVEL_INFO - #define app_log_info(...) app_log(__VA_ARGS__) - #define app_log_status_info(sc, ...) app_log_status(sc, __VA_ARGS__) -#else - #define app_log_info(...) app_log_none(__VA_ARGS__) - #define app_log_status_info(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) -#endif - -#if APP_LOG_LEVEL >= APP_LOG_LEVEL_DEBUG - #define app_log_debug(...) app_log(__VA_ARGS__) - #define app_log_status_debug(sc, ...) app_log_status(sc, __VA_ARGS__) -#else - #define app_log_debug(...) app_log_none(__VA_ARGS__) - #define app_log_status_debug(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) -#endif - -//type definitions ------------------------------------------------------------- -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- - -/***************************************************************************//** - * Function to avoid unused variable warnings due to different log levels. - * @warning This function does nothing and shall not be used directly! - ******************************************************************************/ -static inline void app_log_none(const char* format, ...) -{ - (void)format; -} - -#ifdef __cplusplus -} -#endif -#endif /* COMMON_SL_APP_LOG_H_ */ +/***************************************************************************//** + * @file sl_app_log.h + * @brief Debug printing with assert functionality + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef COMMON_SL_APP_LOG_H_ +#define COMMON_SL_APP_LOG_H_ +#ifdef __cplusplus +extern "C" { +#endif +#include "printf.h" //SHALL NOT BE USED DIRECTLY! + +//macros ----------------------------------------------------------------------- +#define APP_LOG_LEVEL_CRITICAL 1 +#define APP_LOG_LEVEL_ERROR 2 +#define APP_LOG_LEVEL_WARNING 3 +#define APP_LOG_LEVEL_INFO 4 +#define APP_LOG_LEVEL_DEBUG 5 +#if DEBUG + #define APP_LOG_LEVEL APP_LOG_LEVEL_DEBUG +#else //PRODUCTION + #define APP_LOG_LEVEL APP_LOG_LEVEL_INFO +#endif +#define APP_LOG_NL "\r\n" + +#define APP_LOG_OS_MAX_QUEUE_SIZE (512) + +#define __APP_LOG_NUM_TO_STR(x) #x +#define APP_LOG_NUM_TO_STR(x) __APP_LOG_NUM_TO_STR(x) + +#define app_log(...) printf(__VA_ARGS__) +#define app_log_status(sc, ...) if (sc) app_log(__VA_ARGS__) + +#if APP_LOG_LEVEL >= APP_LOG_LEVEL_CRITICAL + #define app_log_critical(...) app_log(__VA_ARGS__) + #define app_log_status_critical(sc, ...) app_log_status(sc, __VA_ARGS__) +#else + #define app_log_critical(...) app_log_none(__VA_ARGS__) + #define app_log_status_critical(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) +#endif + + #if APP_LOG_LEVEL >= APP_LOG_LEVEL_ERROR + #define app_log_error(...) app_log(__VA_ARGS__) + #define app_log_status_error(sc, ...) app_log_status(sc, __VA_ARGS__) +#else + #define app_log_error(...) app_log_none(__VA_ARGS__) + #define app_log_status_error(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) +#endif + +#if APP_LOG_LEVEL >= APP_LOG_LEVEL_WARNING + #define app_log_warning(...) app_log(__VA_ARGS__) + #define app_log_status_warning(sc, ...) app_log_status(sc, __VA_ARGS__) +#else + #define app_log_warning(...) app_log_none(__VA_ARGS__) + #define app_log_status_warning(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) +#endif + +#if APP_LOG_LEVEL >= APP_LOG_LEVEL_INFO + #define app_log_info(...) app_log(__VA_ARGS__) + #define app_log_status_info(sc, ...) app_log_status(sc, __VA_ARGS__) +#else + #define app_log_info(...) app_log_none(__VA_ARGS__) + #define app_log_status_info(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) +#endif + +#if APP_LOG_LEVEL >= APP_LOG_LEVEL_DEBUG + #define app_log_debug(...) app_log(__VA_ARGS__) + #define app_log_status_debug(sc, ...) app_log_status(sc, __VA_ARGS__) +#else + #define app_log_debug(...) app_log_none(__VA_ARGS__) + #define app_log_status_debug(sc, ...) (void)(sc); app_log_none(__VA_ARGS__) +#endif + +//type definitions ------------------------------------------------------------- +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- + +/***************************************************************************//** + * Function to avoid unused variable warnings due to different log levels. + * @warning This function does nothing and shall not be used directly! + ******************************************************************************/ +static inline void app_log_none(const char* format, ...) +{ + (void)format; +} + +#ifdef __cplusplus +} +#endif +#endif /* COMMON_SL_APP_LOG_H_ */ diff --git a/locator_host/autogen/RTE_Components.h b/locator_host/autogen/RTE_Components.h index aa62dc4..9dc9cd4 100644 --- a/locator_host/autogen/RTE_Components.h +++ b/locator_host/autogen/RTE_Components.h @@ -1,22 +1,22 @@ -// This file is autogenerated by Simplicity Configuration Tools. -// The contents of this file will be replaced in their entirety upon regeneration. -// -// Source template file: RTE_Components.h.jinja - - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -/* standard device header from emlib */ -#define CMSIS_device_header "em_device.h" - -/* components are auto-generated here */ - - -#endif /* RTE_COMPONENTS_H */ - -/* This file is autogenerated by Simplicity Configuration Tools. */ -/* The contents of this file will be replaced in their entirety upon regeneration. */ -/* */ -/* Source template file: RTE_Components.h.jinja */ - +// This file is autogenerated by Simplicity Configuration Tools. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Simplicity Configuration Tools. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/locator_host/autogen/gatt_db.c b/locator_host/autogen/gatt_db.c index 574dc0e..b371baa 100644 --- a/locator_host/autogen/gatt_db.c +++ b/locator_host/autogen/gatt_db.c @@ -1,110 +1,110 @@ -/******************************************************************** - * Autogenerated file, do not edit. - *******************************************************************/ - -#include -#include "sli_bt_gattdb_def.h" - -#define GATT_HEADER(F) F -#define GATT_DATA(F) F -GATT_DATA(const uint16_t gattdb_uuidtable_16_map[]) = -{ - 0x2800, - 0x2801, - 0x2803, - 0x2a00, - 0x2a01, - 0x2a29, - 0x2a23, - 0x2a05, - 0x2b2a, - 0x2b29, - 0x2902, -}; - -GATT_DATA(const uint8_t gattdb_uuidtable_128_map[]) = -{ - 0x0 //IAR workaround for empty array -}; -GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_17) = { - .properties = 0x02, - .max_len = 8, - .data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, -}; -GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_15) = { - .len = 12, - .data = { 0x53, 0x69, 0x6c, 0x69, 0x63, 0x6f, 0x6e, 0x20, 0x4c, 0x61, 0x62, 0x73, } -}; -GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_13) = { - .len = 2, - .data = { 0x0a, 0x18, } -}; -GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_12) = { - .len = 2, - .data = { 0x00, 0x00, } -}; -GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_10) = { - .properties = 0x0a, - .max_len = 13, - .data = { 0x45, 0x6d, 0x70, 0x74, 0x79, 0x20, 0x45, 0x78, 0x61, 0x6d, 0x70, 0x6c, 0x65, }, -}; -GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_8) = { - .len = 2, - .data = { 0x00, 0x18, } -}; -GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_7) = { - .properties = 0x0a, - .max_len = 1, - .data = { 0x00, }, -}; -GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_5) = { - .properties = 0x02, - .max_len = 16, - .data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, -}; -GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_2) = { - .properties = 0x20, - .max_len = 4, - .data = { 0x00, 0x00, 0x00, 0x00, }, -}; -GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_0) = { - .len = 2, - .data = { 0x01, 0x18, } -}; - -GATT_DATA(const sli_bt_gattdb_attribute_t gattdb_attributes_map[]) = { - { .handle = 0x01, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_0 }, - { .handle = 0x02, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x20, .char_uuid = 0x0007 } }, - { .handle = 0x03, .uuid = 0x0007, .permissions = 0x800, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_2 }, - { .handle = 0x04, .uuid = 0x000a, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x03, .configdata = { .flags = 0x02, .clientconfig_index = 0x00 } }, - { .handle = 0x05, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0008 } }, - { .handle = 0x06, .uuid = 0x0008, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_5 }, - { .handle = 0x07, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x0a, .char_uuid = 0x0009 } }, - { .handle = 0x08, .uuid = 0x0009, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_7 }, - { .handle = 0x09, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_8 }, - { .handle = 0x0a, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x0a, .char_uuid = 0x0003 } }, - { .handle = 0x0b, .uuid = 0x0003, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_10 }, - { .handle = 0x0c, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0004 } }, - { .handle = 0x0d, .uuid = 0x0004, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_12 }, - { .handle = 0x0e, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_13 }, - { .handle = 0x0f, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0005 } }, - { .handle = 0x10, .uuid = 0x0005, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_15 }, - { .handle = 0x11, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0006 } }, - { .handle = 0x12, .uuid = 0x0006, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_17 }, -}; - -GATT_HEADER(const sli_bt_gattdb_t gattdb) = { - .attributes = gattdb_attributes_map, - .attribute_table_size = 18, - .attribute_num = 18, - .uuid16 = gattdb_uuidtable_16_map, - .uuid16_table_size = 11, - .uuid16_num = 11, - .uuid128 = gattdb_uuidtable_128_map, - .uuid128_table_size = 0, - .uuid128_num = 0, - .num_ccfg = 1, - .caps_mask = 0xffff, - .enabled_caps = 0xffff, -}; -const sli_bt_gattdb_t *static_gattdb = &gattdb; +/******************************************************************** + * Autogenerated file, do not edit. + *******************************************************************/ + +#include +#include "sli_bt_gattdb_def.h" + +#define GATT_HEADER(F) F +#define GATT_DATA(F) F +GATT_DATA(const uint16_t gattdb_uuidtable_16_map[]) = +{ + 0x2800, + 0x2801, + 0x2803, + 0x2a00, + 0x2a01, + 0x2a29, + 0x2a23, + 0x2a05, + 0x2b2a, + 0x2b29, + 0x2902, +}; + +GATT_DATA(const uint8_t gattdb_uuidtable_128_map[]) = +{ + 0x0 //IAR workaround for empty array +}; +GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_17) = { + .properties = 0x02, + .max_len = 8, + .data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, +}; +GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_15) = { + .len = 12, + .data = { 0x53, 0x69, 0x6c, 0x69, 0x63, 0x6f, 0x6e, 0x20, 0x4c, 0x61, 0x62, 0x73, } +}; +GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_13) = { + .len = 2, + .data = { 0x0a, 0x18, } +}; +GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_12) = { + .len = 2, + .data = { 0x00, 0x00, } +}; +GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_10) = { + .properties = 0x0a, + .max_len = 13, + .data = { 0x45, 0x6d, 0x70, 0x74, 0x79, 0x20, 0x45, 0x78, 0x61, 0x6d, 0x70, 0x6c, 0x65, }, +}; +GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_8) = { + .len = 2, + .data = { 0x00, 0x18, } +}; +GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_7) = { + .properties = 0x0a, + .max_len = 1, + .data = { 0x00, }, +}; +GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_5) = { + .properties = 0x02, + .max_len = 16, + .data = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }, +}; +GATT_DATA(sli_bt_gattdb_attribute_chrvalue_t gattdb_attribute_field_2) = { + .properties = 0x20, + .max_len = 4, + .data = { 0x00, 0x00, 0x00, 0x00, }, +}; +GATT_DATA(const sli_bt_gattdb_value_t gattdb_attribute_field_0) = { + .len = 2, + .data = { 0x01, 0x18, } +}; + +GATT_DATA(const sli_bt_gattdb_attribute_t gattdb_attributes_map[]) = { + { .handle = 0x01, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_0 }, + { .handle = 0x02, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x20, .char_uuid = 0x0007 } }, + { .handle = 0x03, .uuid = 0x0007, .permissions = 0x800, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_2 }, + { .handle = 0x04, .uuid = 0x000a, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x03, .configdata = { .flags = 0x02, .clientconfig_index = 0x00 } }, + { .handle = 0x05, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0008 } }, + { .handle = 0x06, .uuid = 0x0008, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_5 }, + { .handle = 0x07, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x0a, .char_uuid = 0x0009 } }, + { .handle = 0x08, .uuid = 0x0009, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_7 }, + { .handle = 0x09, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_8 }, + { .handle = 0x0a, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x0a, .char_uuid = 0x0003 } }, + { .handle = 0x0b, .uuid = 0x0003, .permissions = 0x803, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_10 }, + { .handle = 0x0c, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0004 } }, + { .handle = 0x0d, .uuid = 0x0004, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_12 }, + { .handle = 0x0e, .uuid = 0x0000, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_13 }, + { .handle = 0x0f, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0005 } }, + { .handle = 0x10, .uuid = 0x0005, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x00, .constdata = &gattdb_attribute_field_15 }, + { .handle = 0x11, .uuid = 0x0002, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x05, .characteristic = { .properties = 0x02, .char_uuid = 0x0006 } }, + { .handle = 0x12, .uuid = 0x0006, .permissions = 0x801, .caps = 0xffff, .state = 0x00, .datatype = 0x01, .dynamicdata = &gattdb_attribute_field_17 }, +}; + +GATT_HEADER(const sli_bt_gattdb_t gattdb) = { + .attributes = gattdb_attributes_map, + .attribute_table_size = 18, + .attribute_num = 18, + .uuid16 = gattdb_uuidtable_16_map, + .uuid16_table_size = 11, + .uuid16_num = 11, + .uuid128 = gattdb_uuidtable_128_map, + .uuid128_table_size = 0, + .uuid128_num = 0, + .num_ccfg = 1, + .caps_mask = 0xffff, + .enabled_caps = 0xffff, +}; +const sli_bt_gattdb_t *static_gattdb = &gattdb; diff --git a/locator_host/autogen/gatt_db.h b/locator_host/autogen/gatt_db.h index f017744..e6e8f04 100644 --- a/locator_host/autogen/gatt_db.h +++ b/locator_host/autogen/gatt_db.h @@ -1,22 +1,22 @@ -/******************************************************************** - * Autogenerated file, do not edit. - *******************************************************************/ - -#ifndef __GATT_DB_H -#define __GATT_DB_H - -#include "sli_bt_gattdb_def.h" - -extern const sli_bt_gattdb_t gattdb; - -#define gattdb_generic_attribute 1 -#define gattdb_service_changed_char 3 -#define gattdb_database_hash 6 -#define gattdb_client_support_features 8 -#define gattdb_device_name 11 -#define gattdb_device_information 14 -#define gattdb_manufacturer_name_string 16 -#define gattdb_system_id 18 - - -#endif // __GATT_DB_H +/******************************************************************** + * Autogenerated file, do not edit. + *******************************************************************/ + +#ifndef __GATT_DB_H +#define __GATT_DB_H + +#include "sli_bt_gattdb_def.h" + +extern const sli_bt_gattdb_t gattdb; + +#define gattdb_generic_attribute 1 +#define gattdb_service_changed_char 3 +#define gattdb_database_hash 6 +#define gattdb_client_support_features 8 +#define gattdb_device_name 11 +#define gattdb_device_information 14 +#define gattdb_manufacturer_name_string 16 +#define gattdb_system_id 18 + + +#endif // __GATT_DB_H diff --git a/locator_host/autogen/linkerfile.ld b/locator_host/autogen/linkerfile.ld index 1512596..d2500a0 100644 --- a/locator_host/autogen/linkerfile.ld +++ b/locator_host/autogen/linkerfile.ld @@ -1,252 +1,252 @@ -/***************************************************************************//** - * GCC Linker script for Silicon Labs devices - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - MEMORY - { - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 0x17e000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 - } - -ENTRY(Reset_Handler) - -SECTIONS -{ - - .text : - { - linker_vectors_begin = .; - KEEP(*(.vectors)) - linker_vectors_end = .; - - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - - linker_code_begin = .; - *(SORT_BY_ALIGNMENT(.text*)) - . = ALIGN(32); - linker_code_end = .; - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - __code_classification_validator_start__ = .; - . = . + 0x20; - *(code_classification_validator) - . = ALIGN(32); - __code_classification_validator_end__ = .; - - *(.rodata*) - *(.eh_frame*) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - __etext = .; - - /* Start placing output sections which are loaded into RAM */ - . = ORIGIN(RAM); - - .stack ALIGN(8) (NOLOAD): - { - __StackLimit = .; - KEEP(*(.stack*)) - . = ALIGN(4); - __StackTop = .; - PROVIDE(__stack = __StackTop); - } > RAM - - - .noinit . (NOLOAD): - { - *(.noinit*); - } > RAM - - .data . : AT (__etext) - { - . = ALIGN(4); - __data_start__ = .; - *(vtable) - *(SORT_BY_ALIGNMENT(.data*)) - . = ALIGN(4); - - PROVIDE(__ram_func_section_start = .); - *(.ram) - PROVIDE(__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - *(SEGGER_RTT) - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss . : - { - . = ALIGN(4); - __bss_start__ = .; - *(SORT_BY_ALIGNMENT(.bss*)) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - __ramfuncs_start__ = .; - - __vma_ramfuncs_start__ = .; - __lma_ramfuncs_start__ = __etext + SIZEOF(.data); - - __text_application_ram_offset__ = . - __vma_ramfuncs_start__; - text_application_ram . : AT(__lma_ramfuncs_start__ + __text_application_ram_offset__) - { - . = ALIGN(4); - __text_application_ram_start__ = .; - *(text_application_ram) - . = ALIGN(4); - __text_application_ram_end__ = .; - } > RAM - - . = ALIGN(4); - __vma_ramfuncs_end__ = .; - __lma_ramfuncs_end__ = __lma_ramfuncs_start__ + __text_application_ram_offset__ + SIZEOF(text_application_ram); - - __ramfuncs_end__ = .; - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - } > RAM - - __heap_size = __HeapLimit - __HeapBase; - __ram_end__ = 0x20000000 + 0x40000; - __main_flash_end__ = 0x8000000 + 0x17e000; - - /* This is where we handle flash storage blocks. We use dummy sections for finding the configured - * block sizes and then "place" them at the end of flash when the size is known. */ - .internal_storage (DSECT) : { - KEEP(*(.internal_storage*)) - } > FLASH - - - .nvm (DSECT) : { - KEEP(*(.simee*)) - } > FLASH - - linker_nvm_end = __main_flash_end__; - linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); - linker_nvm_size = SIZEOF(.nvm); - linker_storage_end = linker_nvm_begin; - __nvm3Base = linker_nvm_begin; - - linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); - linker_storage_size = SIZEOF(.internal_storage); - ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") - - - app_flash_end = 0x8000000 + 0x17e000; - ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= app_flash_end, "NVM3 is excessing the flash size !") -} +/***************************************************************************//** + * GCC Linker script for Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + MEMORY + { + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 0x17e000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 + } + +ENTRY(Reset_Handler) + +SECTIONS +{ + + .text : + { + linker_vectors_begin = .; + KEEP(*(.vectors)) + linker_vectors_end = .; + + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + + linker_code_begin = .; + *(SORT_BY_ALIGNMENT(.text*)) + . = ALIGN(32); + linker_code_end = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + __code_classification_validator_start__ = .; + . = . + 0x20; + *(code_classification_validator) + . = ALIGN(32); + __code_classification_validator_end__ = .; + + *(.rodata*) + *(.eh_frame*) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + __etext = .; + + /* Start placing output sections which are loaded into RAM */ + . = ORIGIN(RAM); + + .stack ALIGN(8) (NOLOAD): + { + __StackLimit = .; + KEEP(*(.stack*)) + . = ALIGN(4); + __StackTop = .; + PROVIDE(__stack = __StackTop); + } > RAM + + + .noinit . (NOLOAD): + { + *(.noinit*); + } > RAM + + .data . : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(SORT_BY_ALIGNMENT(.data*)) + . = ALIGN(4); + + PROVIDE(__ram_func_section_start = .); + *(.ram) + PROVIDE(__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + *(SEGGER_RTT) + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss . : + { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + __ramfuncs_start__ = .; + + __vma_ramfuncs_start__ = .; + __lma_ramfuncs_start__ = __etext + SIZEOF(.data); + + __text_application_ram_offset__ = . - __vma_ramfuncs_start__; + text_application_ram . : AT(__lma_ramfuncs_start__ + __text_application_ram_offset__) + { + . = ALIGN(4); + __text_application_ram_start__ = .; + *(text_application_ram) + . = ALIGN(4); + __text_application_ram_end__ = .; + } > RAM + + . = ALIGN(4); + __vma_ramfuncs_end__ = .; + __lma_ramfuncs_end__ = __lma_ramfuncs_start__ + __text_application_ram_offset__ + SIZEOF(text_application_ram); + + __ramfuncs_end__ = .; + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + } > RAM + + __heap_size = __HeapLimit - __HeapBase; + __ram_end__ = 0x20000000 + 0x40000; + __main_flash_end__ = 0x8000000 + 0x17e000; + + /* This is where we handle flash storage blocks. We use dummy sections for finding the configured + * block sizes and then "place" them at the end of flash when the size is known. */ + .internal_storage (DSECT) : { + KEEP(*(.internal_storage*)) + } > FLASH + + + .nvm (DSECT) : { + KEEP(*(.simee*)) + } > FLASH + + linker_nvm_end = __main_flash_end__; + linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); + linker_nvm_size = SIZEOF(.nvm); + linker_storage_end = linker_nvm_begin; + __nvm3Base = linker_nvm_begin; + + linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); + linker_storage_size = SIZEOF(.internal_storage); + ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") + + + app_flash_end = 0x8000000 + 0x17e000; + ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= app_flash_end, "NVM3 is excessing the flash size !") +} diff --git a/locator_host/autogen/sl_bluetooth.c b/locator_host/autogen/sl_bluetooth.c index 1eae81e..abfa85f 100644 --- a/locator_host/autogen/sl_bluetooth.c +++ b/locator_host/autogen/sl_bluetooth.c @@ -1,43 +1,43 @@ - - -#include -#include "sl_bluetooth.h" -#include "sl_ncp_gatt.h" - -void sl_bt_init(void) -{ -} - -SL_WEAK void sl_bt_on_event(sl_bt_msg_t* evt) -{ - (void)(evt); -} - -void sl_bt_process_event(sl_bt_msg_t *evt) -{ - sl_ncp_gatt_on_event(evt); - sl_bt_on_event(evt); -} - -#if !defined(SL_CATALOG_KERNEL_PRESENT) -// When running in an RTOS, the stack events are processed in a dedicated -// event processing task, and these functions are not used at all. - -SL_WEAK bool sl_bt_can_process_event(uint32_t len) -{ - (void)(len); - return true; -} - -void sl_bt_step(void) -{ - sl_bt_msg_t evt; - - // Pop (non-blocking) a Bluetooth stack event from event queue. - sl_status_t status = sl_bt_pop_event(&evt); - if(status != SL_STATUS_OK){ - return; - } - sl_bt_process_event(&evt); -} -#endif // !defined(SL_CATALOG_KERNEL_PRESENT) + + +#include +#include "sl_bluetooth.h" +#include "sl_ncp_gatt.h" + +void sl_bt_init(void) +{ +} + +SL_WEAK void sl_bt_on_event(sl_bt_msg_t* evt) +{ + (void)(evt); +} + +void sl_bt_process_event(sl_bt_msg_t *evt) +{ + sl_ncp_gatt_on_event(evt); + sl_bt_on_event(evt); +} + +#if !defined(SL_CATALOG_KERNEL_PRESENT) +// When running in an RTOS, the stack events are processed in a dedicated +// event processing task, and these functions are not used at all. + +SL_WEAK bool sl_bt_can_process_event(uint32_t len) +{ + (void)(len); + return true; +} + +void sl_bt_step(void) +{ + sl_bt_msg_t evt; + + // Pop (non-blocking) a Bluetooth stack event from event queue. + sl_status_t status = sl_bt_pop_event(&evt); + if(status != SL_STATUS_OK){ + return; + } + sl_bt_process_event(&evt); +} +#endif // !defined(SL_CATALOG_KERNEL_PRESENT) diff --git a/locator_host/autogen/sl_bluetooth.h b/locator_host/autogen/sl_bluetooth.h index 908429c..ae5aa65 100644 --- a/locator_host/autogen/sl_bluetooth.h +++ b/locator_host/autogen/sl_bluetooth.h @@ -1,36 +1,36 @@ -#ifndef BLUETOOTH_H -#define BLUETOOTH_H - -#include -#include "sl_bt_api.h" - -#define SL_BT_COMPONENT_CONNECTIONS 0 - -// Initialize Bluetooth core functionality -void sl_bt_init(void); - -// Polls bluetooth stack for an event and processes it -void sl_bt_step(void); - -/** - * Tell if the application can process a new Bluetooth event in its current - * state, for example, based on resource availability status. - * If true is returned by this function, sl_bt_process_event will be called - * for event processing. Otherwise, the event will be kept in stack's event - * queue until the application can process it. - * - * @note Default implementation of this function returns true. - * Application can override it for own business logic. - * - * @param len Data length of the event - * @return ture if event can be processed; false otherwise - */ -bool sl_bt_can_process_event(uint32_t len); - -// Processes a single bluetooth event -void sl_bt_process_event(sl_bt_msg_t *evt); - -void sl_bt_on_event(sl_bt_msg_t* evt); - - -#endif // BLUETOOTH_H +#ifndef BLUETOOTH_H +#define BLUETOOTH_H + +#include +#include "sl_bt_api.h" + +#define SL_BT_COMPONENT_CONNECTIONS 0 + +// Initialize Bluetooth core functionality +void sl_bt_init(void); + +// Polls bluetooth stack for an event and processes it +void sl_bt_step(void); + +/** + * Tell if the application can process a new Bluetooth event in its current + * state, for example, based on resource availability status. + * If true is returned by this function, sl_bt_process_event will be called + * for event processing. Otherwise, the event will be kept in stack's event + * queue until the application can process it. + * + * @note Default implementation of this function returns true. + * Application can override it for own business logic. + * + * @param len Data length of the event + * @return ture if event can be processed; false otherwise + */ +bool sl_bt_can_process_event(uint32_t len); + +// Processes a single bluetooth event +void sl_bt_process_event(sl_bt_msg_t *evt); + +void sl_bt_on_event(sl_bt_msg_t* evt); + + +#endif // BLUETOOTH_H diff --git a/locator_host/autogen/sl_board_default_init.c b/locator_host/autogen/sl_board_default_init.c index bd43db3..ca5086b 100644 --- a/locator_host/autogen/sl_board_default_init.c +++ b/locator_host/autogen/sl_board_default_init.c @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief Board Default Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" - -void sl_board_default_init(void) -{ - sl_board_disable_vcom(); - -} +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/locator_host/autogen/sl_component_catalog.h b/locator_host/autogen/sl_component_catalog.h index 57527eb..73e7f71 100644 --- a/locator_host/autogen/sl_component_catalog.h +++ b/locator_host/autogen/sl_component_catalog.h @@ -1,27 +1,27 @@ -#ifndef SL_COMPONENT_CATALOG_H -#define SL_COMPONENT_CATALOG_H - -// APIs present in project -#define SL_CATALOG_APP_ASSERT_PRESENT -#define SL_CATALOG_DEVICE_INIT_PRESENT -#define SL_CATALOG_DEVICE_INIT_CLOCKS_PRESENT -#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT -#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT -#define SL_CATALOG_DEVICE_INIT_EMU_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT -#define SL_CATALOG_DEVICE_INIT_LFXO_PRESENT -#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT -#define SL_CATALOG_MVP_PRESENT -#define SL_CATALOG_EMLIB_CORE_PRESENT -#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT -#define SL_CATALOG_GATT_CONFIGURATION_PRESENT -#define SL_CATALOG_IOSTREAM_PRESENT -#define SL_CATALOG_MPU_PRESENT -#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT -#define SL_CATALOG_PRINTF_PRESENT -#define SL_CATALOG_SIMPLE_COM_PRESENT -#define SL_CATALOG_SLEEPTIMER_PRESENT -#define SL_CATALOG_UARTDRV_USART_PRESENT - -#endif // SL_COMPONENT_CATALOG_H +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_APP_ASSERT_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT +#define SL_CATALOG_DEVICE_INIT_CLOCKS_PRESENT +#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT +#define SL_CATALOG_DEVICE_INIT_DPLL_PRESENT +#define SL_CATALOG_DEVICE_INIT_EMU_PRESENT +#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_LFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_MVP_PRESENT +#define SL_CATALOG_EMLIB_CORE_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_GATT_CONFIGURATION_PRESENT +#define SL_CATALOG_IOSTREAM_PRESENT +#define SL_CATALOG_MPU_PRESENT +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT +#define SL_CATALOG_PRINTF_PRESENT +#define SL_CATALOG_SIMPLE_COM_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_UARTDRV_USART_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/locator_host/autogen/sl_device_init_clocks.c b/locator_host/autogen/sl_device_init_clocks.c index 09fb636..0ca58ad 100644 --- a/locator_host/autogen/sl_device_init_clocks.c +++ b/locator_host/autogen/sl_device_init_clocks.c @@ -1,60 +1,60 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for clocks. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_CLOCK_SELECT_SET(SYSCLK, HFRCODPLL); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPACLK, HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPBCLK, HFRCODPLL); -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPCCLK, HFRCODPLL); -#endif - CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFXO); - CMU_CLOCK_SELECT_SET(EM4GRPACLK, LFXO); -#if defined(RTCC_PRESENT) - CMU_CLOCK_SELECT_SET(RTCC, LFXO); -#endif -#if defined(SYSRTC_PRESENT) - CMU_CLOCK_SELECT_SET(SYSRTC, LFXO); -#endif - CMU_CLOCK_SELECT_SET(WDOG0, LFXO); -#if WDOG_COUNT > 1 - CMU_CLOCK_SELECT_SET(WDOG1, LFXO); -#endif - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(SYSCLK, HFRCODPLL); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPACLK, HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPBCLK, HFRCODPLL); +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPCCLK, HFRCODPLL); +#endif + CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFXO); + CMU_CLOCK_SELECT_SET(EM4GRPACLK, LFXO); +#if defined(RTCC_PRESENT) + CMU_CLOCK_SELECT_SET(RTCC, LFXO); +#endif +#if defined(SYSRTC_PRESENT) + CMU_CLOCK_SELECT_SET(SYSRTC, LFXO); +#endif + CMU_CLOCK_SELECT_SET(WDOG0, LFXO); +#if WDOG_COUNT > 1 + CMU_CLOCK_SELECT_SET(WDOG1, LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/locator_host/autogen/sl_event_handler.c b/locator_host/autogen/sl_event_handler.c index 443ce7b..16c78ed 100644 --- a/locator_host/autogen/sl_event_handler.c +++ b/locator_host/autogen/sl_event_handler.c @@ -1,92 +1,92 @@ -#include "sl_event_handler.h" - -#include "em_chip.h" -#include "sl_device_init_nvic.h" -#include "sl_board_init.h" -#include "sl_device_init_dcdc.h" -#include "sl_device_init_lfxo.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_dpll.h" -#include "sl_device_init_clocks.h" -#include "sl_device_init_emu.h" -#include "sl_board_control.h" -#include "sl_sleeptimer.h" -#include "sl_bluetooth.h" -#include "sl_debug_swo.h" -#include "sl_mvp.h" -#include "gpiointerrupt.h" -#include "sl_iostream_rtt.h" -#include "sl_mpu.h" -#include "sl_ram_interrupt_vector_init.h" -#include "sl_simple_com.h" -#include "sl_uartdrv_instances.h" -#include "sl_ncp_host_com.h" -#include "sl_iostream_init_instances.h" -#include "sl_cos.h" - -void sl_platform_init(void) -{ - CHIP_Init(); - sl_device_init_nvic(); - sl_board_preinit(); - sl_device_init_dcdc(); - sl_device_init_lfxo(); - sl_device_init_hfxo(); - sl_device_init_dpll(); - sl_device_init_clocks(); - sl_device_init_emu(); - sl_board_init(); - sl_ram_interrupt_vector_init(); -} - -void sl_driver_init(void) -{ - sl_debug_swo_init(); - sli_mvp_init(); - GPIOINT_Init(); - sl_uartdrv_init_instances(); - sl_cos_send_config(); -} - -void sl_service_init(void) -{ - sl_board_configure_vcom(); - sl_sleeptimer_init(); - sl_mpu_disable_execute_from_ram(); - sl_iostream_init_instances(); -} - -void sl_stack_init(void) -{ - sl_bt_init(); -} - -void sl_internal_app_init(void) -{ - sl_simple_com_init(); - sl_ncp_host_com_init(); -} - -void sl_platform_process_action(void) -{ -} - -void sl_service_process_action(void) -{ - sl_simple_com_step(); -} - -void sl_stack_process_action(void) -{ - sl_bt_step(); -} - -void sl_internal_app_process_action(void) -{ -} - -void sl_iostream_init_instances(void) -{ - sl_iostream_rtt_init(); -} - +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_dpll.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "sl_bluetooth.h" +#include "sl_debug_swo.h" +#include "sl_mvp.h" +#include "gpiointerrupt.h" +#include "sl_iostream_rtt.h" +#include "sl_mpu.h" +#include "sl_ram_interrupt_vector_init.h" +#include "sl_simple_com.h" +#include "sl_uartdrv_instances.h" +#include "sl_ncp_host_com.h" +#include "sl_iostream_init_instances.h" +#include "sl_cos.h" + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_lfxo(); + sl_device_init_hfxo(); + sl_device_init_dpll(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + sl_ram_interrupt_vector_init(); +} + +void sl_driver_init(void) +{ + sl_debug_swo_init(); + sli_mvp_init(); + GPIOINT_Init(); + sl_uartdrv_init_instances(); + sl_cos_send_config(); +} + +void sl_service_init(void) +{ + sl_board_configure_vcom(); + sl_sleeptimer_init(); + sl_mpu_disable_execute_from_ram(); + sl_iostream_init_instances(); +} + +void sl_stack_init(void) +{ + sl_bt_init(); +} + +void sl_internal_app_init(void) +{ + sl_simple_com_init(); + sl_ncp_host_com_init(); +} + +void sl_platform_process_action(void) +{ +} + +void sl_service_process_action(void) +{ + sl_simple_com_step(); +} + +void sl_stack_process_action(void) +{ + sl_bt_step(); +} + +void sl_internal_app_process_action(void) +{ +} + +void sl_iostream_init_instances(void) +{ + sl_iostream_rtt_init(); +} + diff --git a/locator_host/autogen/sl_event_handler.h b/locator_host/autogen/sl_event_handler.h index 9ac6fcd..93f4386 100644 --- a/locator_host/autogen/sl_event_handler.h +++ b/locator_host/autogen/sl_event_handler.h @@ -1,15 +1,15 @@ -#ifndef SL_EVENT_HANDLER_H -#define SL_EVENT_HANDLER_H - -void sl_platform_init(void); -void sl_driver_init(void); -void sl_service_init(void); -void sl_stack_init(void); -void sl_internal_app_init(void); -void sl_platform_process_action(void); -void sl_service_process_action(void); -void sl_stack_process_action(void); -void sl_internal_app_process_action(void); -void sl_iostream_init_instances(void); - -#endif // SL_EVENT_HANDLER_H +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_platform_process_action(void); +void sl_service_process_action(void); +void sl_stack_process_action(void); +void sl_internal_app_process_action(void); +void sl_iostream_init_instances(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/locator_host/autogen/sl_iostream_handles.c b/locator_host/autogen/sl_iostream_handles.c index 064e882..fe071ee 100644 --- a/locator_host/autogen/sl_iostream_handles.c +++ b/locator_host/autogen/sl_iostream_handles.c @@ -1,27 +1,27 @@ -#include "sl_iostream.h" -#include "sl_iostream_handles.h" -#include "string.h" - -const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { - - &sl_iostream_instance_rtt_info, - -}; - -const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); - -/***************************************************************************//** - * Get iostream instance handle for a given name - * - * @return Instance handle if it exist, NULL otherwise. - ******************************************************************************/ -sl_iostream_t *sl_iostream_get_handle(char *name) -{ - for (uint32_t i = 0; i < sl_iostream_instances_count; i++) { - if (strcmp(sl_iostream_instances_info[i]->name, name) == 0) { - return sl_iostream_instances_info[i]->handle; - } - } - - return NULL; +#include "sl_iostream.h" +#include "sl_iostream_handles.h" +#include "string.h" + +const sl_iostream_instance_info_t *sl_iostream_instances_info[] = { + + &sl_iostream_instance_rtt_info, + +}; + +const uint32_t sl_iostream_instances_count = sizeof(sl_iostream_instances_info) / sizeof(sl_iostream_instances_info[0]); + +/***************************************************************************//** + * Get iostream instance handle for a given name + * + * @return Instance handle if it exist, NULL otherwise. + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_handle(char *name) +{ + for (uint32_t i = 0; i < sl_iostream_instances_count; i++) { + if (strcmp(sl_iostream_instances_info[i]->name, name) == 0) { + return sl_iostream_instances_info[i]->handle; + } + } + + return NULL; } \ No newline at end of file diff --git a/locator_host/autogen/sl_iostream_handles.h b/locator_host/autogen/sl_iostream_handles.h index e7aab8e..770dc48 100644 --- a/locator_host/autogen/sl_iostream_handles.h +++ b/locator_host/autogen/sl_iostream_handles.h @@ -1,20 +1,20 @@ -#ifndef SL_IOSTREAM_HANDLES_H -#define SL_IOSTREAM_HANDLES_H -#include "sl_iostream.h" -#include "sl_iostream_rtt.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -extern const sl_iostream_instance_info_t *sl_iostream_instances_info[]; -extern const uint32_t sl_iostream_instances_count; - -sl_iostream_t *sl_iostream_get_handle(char *name); - -#ifdef __cplusplus -} -#endif - -#endif // SL_IOSTREAM_HANDLES_H +#ifndef SL_IOSTREAM_HANDLES_H +#define SL_IOSTREAM_HANDLES_H +#include "sl_iostream.h" +#include "sl_iostream_rtt.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +extern const sl_iostream_instance_info_t *sl_iostream_instances_info[]; +extern const uint32_t sl_iostream_instances_count; + +sl_iostream_t *sl_iostream_get_handle(char *name); + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_HANDLES_H diff --git a/locator_host/autogen/sl_iostream_init_instances.h b/locator_host/autogen/sl_iostream_init_instances.h index c092c37..0dc7af5 100644 --- a/locator_host/autogen/sl_iostream_init_instances.h +++ b/locator_host/autogen/sl_iostream_init_instances.h @@ -1,16 +1,16 @@ -#ifndef SL_IOSTREAM_INIT_INSTANCES_H -#define SL_IOSTREAM_INIT_INSTANCES_H - -#include "sl_iostream.h" -#ifdef __cplusplus -extern "C" { -#endif - -// Initialize iostream component(s) / instance(s) -void sl_iostream_init_instances(void); - -#ifdef __cplusplus -} -#endif - +#ifndef SL_IOSTREAM_INIT_INSTANCES_H +#define SL_IOSTREAM_INIT_INSTANCES_H + +#include "sl_iostream.h" +#ifdef __cplusplus +extern "C" { +#endif + +// Initialize iostream component(s) / instance(s) +void sl_iostream_init_instances(void); + +#ifdef __cplusplus +} +#endif + #endif // SL_IOSTREAM_INIT_INSTANCES_H \ No newline at end of file diff --git a/locator_host/autogen/sl_simple_com_isr.c b/locator_host/autogen/sl_simple_com_isr.c index bbdaf1e..1712903 100644 --- a/locator_host/autogen/sl_simple_com_isr.c +++ b/locator_host/autogen/sl_simple_com_isr.c @@ -1,76 +1,76 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) interrupt service routine - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_uartdrv_usart_exp_config.h" - -// ISR function, declared in sl_simple_com.c -extern void sli_simple_com_isr(void); - -/******************************************************************************* - * Concatenate preprocessor tokens A and B without expanding macro unless it is - * invoked from a macro, already. - ******************************************************************************/ -#define PPCAT_NX(A, B) A ## B - -/******************************************************************************* - * Concatenate preprocessor tokens A and B after macro-expanding them. - ******************************************************************************/ -#define PPCAT(A, B) PPCAT_NX(A, B) - -/******************************************************************************* - * Actual USART instance number, generated upon project creation / modification. - ******************************************************************************/ -#define SL_UART_INST_NO SL_UARTDRV_USART_EXP_PERIPHERAL_NO - -/******************************************************************************* - * Concatenate the actual value of SL_UARTDRV_USART_*_PERIPHERAL_NO and the - * parameter to (partially) create the interrupt service routine name. This - * will be the second part. Please note it can be created only this way: second - * part of the name, first - otherwise recursive macro expansion would mess up - * the whole effort. - ******************************************************************************/ -#define SL_SIMPLE_COM_VNAME(A) PPCAT(SL_UART_INST_NO, A) - -/******************************************************************************* - * Finally, construct the actual ISR vector name for USARTn - * Currently, this macro has limited supports only for USARTn vectors. - ******************************************************************************/ -#define SL_SIMPLE_COM_IRQ PPCAT(USART, \ - SL_SIMPLE_COM_VNAME(_RX_IRQHandler)) - -/**************************************************************************//** - * Override the default interrupt handler using the special macro in order to - * place the vector in the appropriate place no matter which USART peripheral is - * actually used. - *****************************************************************************/ -void SL_SIMPLE_COM_IRQ() -{ - sli_simple_com_isr(); -} - +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) interrupt service routine + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_uartdrv_usart_exp_config.h" + +// ISR function, declared in sl_simple_com.c +extern void sli_simple_com_isr(void); + +/******************************************************************************* + * Concatenate preprocessor tokens A and B without expanding macro unless it is + * invoked from a macro, already. + ******************************************************************************/ +#define PPCAT_NX(A, B) A ## B + +/******************************************************************************* + * Concatenate preprocessor tokens A and B after macro-expanding them. + ******************************************************************************/ +#define PPCAT(A, B) PPCAT_NX(A, B) + +/******************************************************************************* + * Actual USART instance number, generated upon project creation / modification. + ******************************************************************************/ +#define SL_UART_INST_NO SL_UARTDRV_USART_EXP_PERIPHERAL_NO + +/******************************************************************************* + * Concatenate the actual value of SL_UARTDRV_USART_*_PERIPHERAL_NO and the + * parameter to (partially) create the interrupt service routine name. This + * will be the second part. Please note it can be created only this way: second + * part of the name, first - otherwise recursive macro expansion would mess up + * the whole effort. + ******************************************************************************/ +#define SL_SIMPLE_COM_VNAME(A) PPCAT(SL_UART_INST_NO, A) + +/******************************************************************************* + * Finally, construct the actual ISR vector name for USARTn + * Currently, this macro has limited supports only for USARTn vectors. + ******************************************************************************/ +#define SL_SIMPLE_COM_IRQ PPCAT(USART, \ + SL_SIMPLE_COM_VNAME(_RX_IRQHandler)) + +/**************************************************************************//** + * Override the default interrupt handler using the special macro in order to + * place the vector in the appropriate place no matter which USART peripheral is + * actually used. + *****************************************************************************/ +void SL_SIMPLE_COM_IRQ() +{ + sli_simple_com_isr(); +} + diff --git a/locator_host/autogen/sl_uartdrv_init.c b/locator_host/autogen/sl_uartdrv_init.c index e85bfd4..06a42cb 100644 --- a/locator_host/autogen/sl_uartdrv_init.c +++ b/locator_host/autogen/sl_uartdrv_init.c @@ -1,91 +1,91 @@ -#include "uartdrv.h" -#include "sl_uartdrv_instances.h" -#include - -#include "sl_uartdrv_usart_exp_config.h" - -UARTDRV_HandleData_t sl_uartdrv_usart_exp_handle_data; -UARTDRV_Handle_t sl_uartdrv_usart_exp_handle = &sl_uartdrv_usart_exp_handle_data; - -static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; - -/* If CTS and RTS not defined, define a default value to avoid errors */ -#ifndef SL_UARTDRV_USART_EXP_CTS_PORT -#define SL_UARTDRV_USART_EXP_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_CTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_EXP_CTS_LOC 0 -#endif -#endif - -#ifndef SL_UARTDRV_USART_EXP_RTS_PORT -#define SL_UARTDRV_USART_EXP_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_EXP_RTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_EXP_RTS_LOC 0 -#endif -#endif - - -/* Define RX and TX buffer queues */ -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE, sl_uartdrv_usart_exp_rx_buffer); -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE, sl_uartdrv_usart_exp_tx_buffer); - - -/* Create uartdrv initialization structs */ -UARTDRV_InitUart_t sl_uartdrv_usart_init_exp = { - .port = SL_UARTDRV_USART_EXP_PERIPHERAL, - .baudRate = SL_UARTDRV_USART_EXP_BAUDRATE, -#if defined(_USART_ROUTELOC0_MASK) - .portLocationTx = SL_UARTDRV_USART_EXP_TX_LOC, - .portLocationRx = SL_UARTDRV_USART_EXP_RX_LOC, -#elif defined(_USART_ROUTE_MASK) - .portLocation = SL_UARTDRV_USART_EXP_ROUTE_LOC, -#elif defined(_GPIO_USART_ROUTEEN_MASK) - .txPort = SL_UARTDRV_USART_EXP_TX_PORT, - .rxPort = SL_UARTDRV_USART_EXP_RX_PORT, - .txPin = SL_UARTDRV_USART_EXP_TX_PIN, - .rxPin = SL_UARTDRV_USART_EXP_RX_PIN, - .uartNum = SL_UARTDRV_USART_EXP_PERIPHERAL_NO, -#endif - .stopBits = SL_UARTDRV_USART_EXP_STOP_BITS, - .parity = SL_UARTDRV_USART_EXP_PARITY, - .oversampling = SL_UARTDRV_USART_EXP_OVERSAMPLING, -#if defined(USART_CTRL_MVDIS) - .mvdis = SL_UARTDRV_USART_EXP_MVDIS, -#endif - .fcType = SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE, - .ctsPort = SL_UARTDRV_USART_EXP_CTS_PORT, - .rtsPort = SL_UARTDRV_USART_EXP_RTS_PORT, - .ctsPin = SL_UARTDRV_USART_EXP_CTS_PIN, - .rtsPin = SL_UARTDRV_USART_EXP_RTS_PIN, - .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_exp_rx_buffer, - .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_exp_tx_buffer, -#if defined(_USART_ROUTELOC1_MASK) - .portLocationCts = SL_UARTDRV_USART_EXP_CTS_LOC, - .portLocationRts = SL_UARTDRV_USART_EXP_RTS_LOC, -#endif -}; - - -void sl_uartdrv_init_instances(void){ - UARTDRV_InitUart(sl_uartdrv_usart_exp_handle, &sl_uartdrv_usart_init_exp); - sl_uartdrv_set_default(sl_uartdrv_usart_exp_handle); -} - -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) -{ - sl_status_t status = SL_STATUS_INVALID_HANDLE; - - if (handle != NULL) { - sli_uartdrv_default_handle = handle; - status = SL_STATUS_OK; - } - - return status; -} - -UARTDRV_Handle_t sl_uartdrv_get_default(void) -{ - return sli_uartdrv_default_handle; -} +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_exp_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_exp_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_exp_handle = &sl_uartdrv_usart_exp_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_EXP_CTS_PORT +#define SL_UARTDRV_USART_EXP_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_EXP_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_EXP_RTS_PORT +#define SL_UARTDRV_USART_EXP_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_EXP_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_EXP_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE, sl_uartdrv_usart_exp_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE, sl_uartdrv_usart_exp_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_exp = { + .port = SL_UARTDRV_USART_EXP_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_EXP_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_EXP_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_EXP_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_EXP_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_EXP_TX_PORT, + .rxPort = SL_UARTDRV_USART_EXP_RX_PORT, + .txPin = SL_UARTDRV_USART_EXP_TX_PIN, + .rxPin = SL_UARTDRV_USART_EXP_RX_PIN, + .uartNum = SL_UARTDRV_USART_EXP_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_EXP_STOP_BITS, + .parity = SL_UARTDRV_USART_EXP_PARITY, + .oversampling = SL_UARTDRV_USART_EXP_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_EXP_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_EXP_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_EXP_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_EXP_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_EXP_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_exp_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_exp_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_EXP_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_EXP_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_exp_handle, &sl_uartdrv_usart_init_exp); + sl_uartdrv_set_default(sl_uartdrv_usart_exp_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/locator_host/autogen/sl_uartdrv_instances.h b/locator_host/autogen/sl_uartdrv_instances.h index 041e9e8..f530841 100644 --- a/locator_host/autogen/sl_uartdrv_instances.h +++ b/locator_host/autogen/sl_uartdrv_instances.h @@ -1,35 +1,35 @@ -#ifndef SL_UARTDRV_INSTANCES_H -#define SL_UARTDRV_INSTANCES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_status.h" -#include "uartdrv.h" - -extern UARTDRV_Handle_t sl_uartdrv_usart_exp_handle; - -void sl_uartdrv_init_instances(void); - -/***************************************************************************//** - * Set the handle as the default UARTDRV handle. - * - * @param[in] handle UARTDRV handle to set as default. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); - -/***************************************************************************//** - * Get the default UARTDRV handle configured. - * - * @return UARTDRV handle - ******************************************************************************/ -UARTDRV_Handle_t sl_uartdrv_get_default(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_UARTDRV_INSTANCES_H +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_exp_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/locator_host/bt/CMakeLists.txt b/locator_host/bt/CMakeLists.txt index 9c89101..4c4065d 100644 --- a/locator_host/bt/CMakeLists.txt +++ b/locator_host/bt/CMakeLists.txt @@ -1,5 +1,5 @@ -add_subdirectory(aoa) - -add_library(bt) -target_link_libraries(bt PRIVATE bt_aoa) -target_include_directories(bt PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/aoa) +add_subdirectory(aoa) + +add_library(bt) +target_link_libraries(bt PRIVATE bt_aoa) +target_include_directories(bt PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/aoa) diff --git a/locator_host/bt/aoa/CMakeLists.txt b/locator_host/bt/aoa/CMakeLists.txt index 77a87e7..ae0cc57 100644 --- a/locator_host/bt/aoa/CMakeLists.txt +++ b/locator_host/bt/aoa/CMakeLists.txt @@ -1,33 +1,33 @@ -add_library(bt_aoa OBJECT - sl_bt_aoa.c - #Add the GSDK sources here directly because directories copied from GSDK directly (no place for the CMakeLists.txt file there might be overwritten) - antenna_array/antenna_array.c - aoa_angle/aoa_angle.c - aoa_cte/aoa_cte.c - aoa_cte/cte_conn_less.c - aoa_cte/cte_conn.c - aoa_cte/cte_silabs.c - aoa_db/aoa_db.c - aoa_util/aoa_util.c - ncp_evt_filter/sl_ncp_evt_filter.c -) -target_link_libraries(bt_aoa PRIVATE drivers slc_locator_host) -target_compile_definitions(bt_aoa PRIVATE - _POSIX_C_SOURCE=200809 #needed to avoid warning for strtok_r usage -) -target_include_directories(bt_aoa PRIVATE - ../../. #System configuration - antenna_array - aoa_angle - aoa_angle/config - aoa_cte - aoa_cte/config - aoa_db - aoa_util - config - ncp_evt_filter - ncp_evt_filter/config -) -target_include_directories(bt_aoa PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR} -) +add_library(bt_aoa OBJECT + sl_bt_aoa.c + #Add the GSDK sources here directly because directories copied from GSDK directly (no place for the CMakeLists.txt file there might be overwritten) + antenna_array/antenna_array.c + aoa_angle/aoa_angle.c + aoa_cte/aoa_cte.c + aoa_cte/cte_conn_less.c + aoa_cte/cte_conn.c + aoa_cte/cte_silabs.c + aoa_db/aoa_db.c + aoa_util/aoa_util.c + ncp_evt_filter/sl_ncp_evt_filter.c +) +target_link_libraries(bt_aoa PRIVATE drivers slc_locator_host) +target_compile_definitions(bt_aoa PRIVATE + _POSIX_C_SOURCE=200809 #needed to avoid warning for strtok_r usage +) +target_include_directories(bt_aoa PRIVATE + ../../. #System configuration + antenna_array + aoa_angle + aoa_angle/config + aoa_cte + aoa_cte/config + aoa_db + aoa_util + config + ncp_evt_filter + ncp_evt_filter/config +) +target_include_directories(bt_aoa PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR} +) diff --git a/locator_host/bt/aoa/README.txt b/locator_host/bt/aoa/README.txt index 871a0f5..074b9e7 100644 --- a/locator_host/bt/aoa/README.txt +++ b/locator_host/bt/aoa/README.txt @@ -1,3 +1,3 @@ -The folders in this directory are required for sl_bt_aoa.c/h. -These directories are part of the GSDK however (unfortunately) cannot be added through Studio so it needs to be copied manually. -Therefore in case of GSDK update, COPY manually the new angle calculation dependencies from the GSDK repository. +The folders in this directory are required for sl_bt_aoa.c/h. +These directories are part of the GSDK however (unfortunately) cannot be added through Studio so it needs to be copied manually. +Therefore in case of GSDK update, COPY manually the new angle calculation dependencies from the GSDK repository. diff --git a/locator_host/bt/aoa/antenna_array/antenna_array.c b/locator_host/bt/aoa/antenna_array/antenna_array.c index e4333a7..d867aca 100644 --- a/locator_host/bt/aoa/antenna_array/antenna_array.c +++ b/locator_host/bt/aoa/antenna_array/antenna_array.c @@ -1,383 +1,383 @@ -/***************************************************************************//** - * @file - * @brief Antenna array handler for Silicon Labs boards. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include "antenna_array.h" -#include "antenna_array_brd4191a.h" - -static uint8_t get_array_variant(uint8_t array_type, uint8_t *pattern); - -static const uint8_t antenna_array_4x4_ura[] = { - 0, 1, 2, 3, - 4, 5, 6, 7, - 8, 9, 10, 11, - 12, 13, 14, 15 -}; - -static const uint8_t antenna_array_3x3_ura[] = { - // Variant 0 - 0, 1, 2, - 4, 5, 6, - 8, 9, 10, - // Variant 1 - 1, 2, 3, - 5, 6, 7, - 9, 10, 11, - // Variant 2 - 4, 5, 6, - 8, 9, 10, - 12, 13, 14, - // Variant 3 - 5, 6, 7, - 9, 10, 11, - 13, 14, 15 -}; - -static const uint8_t antenna_array_1x4_ula[] = { - // Variant 0 - 0, 1, 2, 3, - // Variant 1 - 4, 5, 6, 7, - // Variant 2 - 8, 9, 10, 11, - // Variant 3 - 12, 13, 14, 15, - // Variant 4 - 0, - 4, - 8, - 12, - // Variant 5 - 1, - 5, - 9, - 13, - // Variant 6 - 2, - 6, - 10, - 14, - // Variant 7 - 3, - 7, - 11, - 15 -}; - -static const uint8_t array_size[ANTENNA_ARRAY_TYPE_LAST] = { - 16, // ANTENNA_ARRAY_TYPE_4x4_URA - 9, // ANTENNA_ARRAY_TYPE_3x3_URA - 4, // ANTENNA_ARRAY_TYPE_1x4_ULA - 16 // ANTENNA_ARRAY_TYPE_4x4_DP_URA -}; - -static const uint8_t array_variants[ANTENNA_ARRAY_TYPE_LAST] = { - 1, // ANTENNA_ARRAY_TYPE_4x4_URA - 4, // ANTENNA_ARRAY_TYPE_3x3_URA - 8, // ANTENNA_ARRAY_TYPE_1x4_ULA - 1 // ANTENNA_ARRAY_TYPE_4x4_DP_URA -}; - -static const uint8_t *array_list[ANTENNA_ARRAY_TYPE_LAST] = { - antenna_array_4x4_ura, - antenna_array_3x3_ura, - antenna_array_1x4_ula, - antenna_array_4x4_ura // 4x4 DP is the same as 4x4 CP. -}; - -static const uint8_t antenna_array_dp_vertical[] = ANT_VERTICAL; -static const uint8_t antenna_array_dp_horizontal[] = ANT_HORIZONTAL; -static const uint8_t reference_antenna = ANT_6_CP; - -static char *board_list_str[] = { - "BRD4185A", - "BRD4191A" -}; - -static antenna_array_board_t type_to_board[] = { - BRD4185A, // ANTENNA_ARRAY_TYPE_4x4_URA - BRD4185A, // ANTENNA_ARRAY_TYPE_3x3_URA - BRD4185A, // ANTENNA_ARRAY_TYPE_1x4_ULA - BRD4191A // ANTENNA_ARRAY_TYPE_4x4_DP_URA -}; - -static uint8_t board_to_type[] = { - ANTENNA_ARRAY_TYPE_4x4_URA, // BRD4185A - ANTENNA_ARRAY_TYPE_4x4_DP_URA // BRD4191A -}; - -/***************************************************************************//** - * Initialize antenna switch pattern with default values. - ******************************************************************************/ -sl_status_t antenna_array_init(antenna_array_t *antenna_array, - uint8_t array_type) -{ - if (antenna_array == NULL) { - return SL_STATUS_NULL_POINTER; - } - - if (array_type >= ANTENNA_ARRAY_TYPE_LAST) { - // Array type not supported or invalid. - return SL_STATUS_INVALID_PARAMETER; - } - - antenna_array->array_type = array_type; - antenna_array->size = array_size[array_type]; - - for (uint8_t i = 0; i < antenna_array->size; i++) { - // Use the 1st variant as default. - antenna_array->pattern[i] = array_list[array_type][i]; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Override antenna switch pattern. - ******************************************************************************/ -sl_status_t antenna_array_set_pattern(antenna_array_t *antenna_array, - uint8_t *pattern, - uint8_t size) -{ - if ((antenna_array == NULL) || (pattern == NULL)) { - return SL_STATUS_NULL_POINTER; - } - - if (size != antenna_array->size) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check if pattern is valid. - if (get_array_variant(antenna_array->array_type, pattern) == array_variants[antenna_array->array_type]) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Copy pattern. - for (uint8_t i = 0; i < antenna_array->size; i++) { - antenna_array->pattern[i] = pattern[i]; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Get antenna switch pin sequence. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[out] pattern Pin sequence that implements the antenna switch pattern. - * The first element in the sequence represents the - * reference antenna. - * @param[in,out] size Buffer length as input, actual pattern length as output. - ******************************************************************************/ -sl_status_t antenna_array_get_pin_pattern(antenna_array_t *antenna_array, - uint8_t *pattern, - uint8_t *size) -{ - if ((antenna_array == NULL) || (size == NULL)) { - return SL_STATUS_NULL_POINTER; - } - if (antenna_array_type_is_dp(antenna_array->array_type)) { - // Output buffer is optional. - if (pattern != NULL) { - // Check if output buffer size is large enough. - if (*size < (1 + (2 * antenna_array->size))) { - return SL_STATUS_INVALID_PARAMETER; - } - // Fill output buffer. - pattern[0] = reference_antenna; - for (uint8_t i = 0; i < antenna_array->size; i++) { - pattern[2 * i + 1] = antenna_array_dp_vertical[antenna_array->pattern[i]]; - pattern[2 * i + 2] = antenna_array_dp_horizontal[antenna_array->pattern[i]]; - } - } - *size = 1 + (2 * antenna_array->size); - } else { - // Output buffer is optional. - if (pattern != NULL) { - // Check if output buffer size is large enough. - if (*size < antenna_array->size) { - return SL_STATUS_INVALID_PARAMETER; - } - // Fill output buffer. - for (uint8_t i = 0; i < antenna_array->size; i++) { - pattern[i] = antenna_array->pattern[i]; - } - } - *size = antenna_array->size; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Convert antenna switch pattern to [0..n-1] interval without gaps. - ******************************************************************************/ -sl_status_t antenna_array_get_continuous_pattern(antenna_array_t *antenna_array, - uint32_t *pattern, - uint32_t *size) -{ - if ((antenna_array == NULL) || (pattern == NULL) || (size == NULL)) { - return SL_STATUS_NULL_POINTER; - } - - if (*size < antenna_array->size) { - return SL_STATUS_INVALID_PARAMETER; - } - - uint8_t variant = get_array_variant(antenna_array->array_type, antenna_array->pattern); - if (variant == array_variants[antenna_array->array_type]) { - // Pattern corrupted. - return SL_STATUS_FAIL; - } - - uint8_t offset = variant * array_size[antenna_array->array_type]; - const uint8_t *reference_array = &array_list[antenna_array->array_type][offset]; - - for (uint8_t i = 0; i < antenna_array->size; i++) { - for (uint8_t j = 0; j < array_size[antenna_array->array_type]; j++) { - if (antenna_array->pattern[i] == reference_array[j]) { - pattern[i] = j; - break; - } - } - } - *size = antenna_array->size; - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Shuffle the current antenna switch pattern. - ******************************************************************************/ -sl_status_t antenna_array_shuffle_pattern(antenna_array_t *antenna_array, - int(random)(void)) -{ - uint8_t i, j, temp; - - if ((antenna_array == NULL) || (random == NULL)) { - return SL_STATUS_NULL_POINTER; - } - // Swap index i with a random index j. - for (i = 0; i < antenna_array->size - 1; i++) { - j = i + 1 + (random() % (antenna_array->size - i - 1)); - temp = antenna_array->pattern[j]; - antenna_array->pattern[j] = antenna_array->pattern[i]; - antenna_array->pattern[i] = temp; - } - return SL_STATUS_OK; -} - -static uint8_t get_array_variant(uint8_t array_type, uint8_t *pattern) -{ - uint8_t variant; - uint8_t antenna_i; - uint8_t antenna_j; - - for (variant = 0; variant < array_variants[array_type]; variant++) { - for (antenna_i = 0; antenna_i < array_size[array_type]; antenna_i++) { - for (antenna_j = 0; (antenna_j < array_size[array_type]); antenna_j++) { - if (pattern[antenna_j] == array_list[array_type][variant * array_size[array_type] + antenna_i]) { - // Antenna found. - break; - } - } - if (antenna_j == array_size[array_type]) { - // Antenna not found, try next variant. - break; - } - } - if (antenna_i == array_size[array_type]) { - // All antennas found for the variant. - break; - } - } - return variant; -} - -// Assign a compatible board to an antenna array type. -sl_status_t antenna_array_type_to_board(uint8_t array_type, - antenna_array_board_t *board) -{ - if (board == NULL) { - return SL_STATUS_NULL_POINTER; - } else if (array_type < 0 || array_type >= ANTENNA_ARRAY_TYPE_LAST) { - return SL_STATUS_INVALID_PARAMETER; - } - *board = type_to_board[array_type]; - return SL_STATUS_OK; -} - -// Assign a default antenna array type to a board. -sl_status_t antenna_array_board_to_type(antenna_array_board_t board, - uint8_t *array_type) -{ - if (array_type == NULL) { - return SL_STATUS_NULL_POINTER; - } else if (board < 0 || board >= ANTENNA_ARRAY_BOARD_COUNT) { - return SL_STATUS_INVALID_PARAMETER; - } else if (board == ANTENNA_ARRAY_BOARD_UNKNOWN) { - return SL_STATUS_NOT_SUPPORTED; - } - *array_type = board_to_type[board]; - return SL_STATUS_OK; -} - -// Convert string to antenna array board. -sl_status_t antenna_array_string_to_board(const char *str, - antenna_array_board_t *board) -{ - if (str == NULL || board == NULL) { - return SL_STATUS_NULL_POINTER; - } - for (int i = 0; i < ANTENNA_ARRAY_BOARD_UNKNOWN; i++) { - if (strcmp(board_list_str[i], str) == 0) { - *board = (antenna_array_board_t)i; - return SL_STATUS_OK; - } - } - return SL_STATUS_NOT_SUPPORTED; -} - -// Convert antenna array board to string. -sl_status_t antenna_array_board_to_string(antenna_array_board_t board, - char *str) -{ - if (str == NULL) { - return SL_STATUS_NULL_POINTER; - } else if (board < 0 || board >= ANTENNA_ARRAY_BOARD_COUNT) { - return SL_STATUS_INVALID_PARAMETER; - } else if (board == ANTENNA_ARRAY_BOARD_UNKNOWN) { - return SL_STATUS_NOT_SUPPORTED; - } - - memcpy(str, board_list_str[board], strlen(board_list_str[board]) + 1); - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Antenna array handler for Silicon Labs boards. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include "antenna_array.h" +#include "antenna_array_brd4191a.h" + +static uint8_t get_array_variant(uint8_t array_type, uint8_t *pattern); + +static const uint8_t antenna_array_4x4_ura[] = { + 0, 1, 2, 3, + 4, 5, 6, 7, + 8, 9, 10, 11, + 12, 13, 14, 15 +}; + +static const uint8_t antenna_array_3x3_ura[] = { + // Variant 0 + 0, 1, 2, + 4, 5, 6, + 8, 9, 10, + // Variant 1 + 1, 2, 3, + 5, 6, 7, + 9, 10, 11, + // Variant 2 + 4, 5, 6, + 8, 9, 10, + 12, 13, 14, + // Variant 3 + 5, 6, 7, + 9, 10, 11, + 13, 14, 15 +}; + +static const uint8_t antenna_array_1x4_ula[] = { + // Variant 0 + 0, 1, 2, 3, + // Variant 1 + 4, 5, 6, 7, + // Variant 2 + 8, 9, 10, 11, + // Variant 3 + 12, 13, 14, 15, + // Variant 4 + 0, + 4, + 8, + 12, + // Variant 5 + 1, + 5, + 9, + 13, + // Variant 6 + 2, + 6, + 10, + 14, + // Variant 7 + 3, + 7, + 11, + 15 +}; + +static const uint8_t array_size[ANTENNA_ARRAY_TYPE_LAST] = { + 16, // ANTENNA_ARRAY_TYPE_4x4_URA + 9, // ANTENNA_ARRAY_TYPE_3x3_URA + 4, // ANTENNA_ARRAY_TYPE_1x4_ULA + 16 // ANTENNA_ARRAY_TYPE_4x4_DP_URA +}; + +static const uint8_t array_variants[ANTENNA_ARRAY_TYPE_LAST] = { + 1, // ANTENNA_ARRAY_TYPE_4x4_URA + 4, // ANTENNA_ARRAY_TYPE_3x3_URA + 8, // ANTENNA_ARRAY_TYPE_1x4_ULA + 1 // ANTENNA_ARRAY_TYPE_4x4_DP_URA +}; + +static const uint8_t *array_list[ANTENNA_ARRAY_TYPE_LAST] = { + antenna_array_4x4_ura, + antenna_array_3x3_ura, + antenna_array_1x4_ula, + antenna_array_4x4_ura // 4x4 DP is the same as 4x4 CP. +}; + +static const uint8_t antenna_array_dp_vertical[] = ANT_VERTICAL; +static const uint8_t antenna_array_dp_horizontal[] = ANT_HORIZONTAL; +static const uint8_t reference_antenna = ANT_6_CP; + +static char *board_list_str[] = { + "BRD4185A", + "BRD4191A" +}; + +static antenna_array_board_t type_to_board[] = { + BRD4185A, // ANTENNA_ARRAY_TYPE_4x4_URA + BRD4185A, // ANTENNA_ARRAY_TYPE_3x3_URA + BRD4185A, // ANTENNA_ARRAY_TYPE_1x4_ULA + BRD4191A // ANTENNA_ARRAY_TYPE_4x4_DP_URA +}; + +static uint8_t board_to_type[] = { + ANTENNA_ARRAY_TYPE_4x4_URA, // BRD4185A + ANTENNA_ARRAY_TYPE_4x4_DP_URA // BRD4191A +}; + +/***************************************************************************//** + * Initialize antenna switch pattern with default values. + ******************************************************************************/ +sl_status_t antenna_array_init(antenna_array_t *antenna_array, + uint8_t array_type) +{ + if (antenna_array == NULL) { + return SL_STATUS_NULL_POINTER; + } + + if (array_type >= ANTENNA_ARRAY_TYPE_LAST) { + // Array type not supported or invalid. + return SL_STATUS_INVALID_PARAMETER; + } + + antenna_array->array_type = array_type; + antenna_array->size = array_size[array_type]; + + for (uint8_t i = 0; i < antenna_array->size; i++) { + // Use the 1st variant as default. + antenna_array->pattern[i] = array_list[array_type][i]; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Override antenna switch pattern. + ******************************************************************************/ +sl_status_t antenna_array_set_pattern(antenna_array_t *antenna_array, + uint8_t *pattern, + uint8_t size) +{ + if ((antenna_array == NULL) || (pattern == NULL)) { + return SL_STATUS_NULL_POINTER; + } + + if (size != antenna_array->size) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if pattern is valid. + if (get_array_variant(antenna_array->array_type, pattern) == array_variants[antenna_array->array_type]) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Copy pattern. + for (uint8_t i = 0; i < antenna_array->size; i++) { + antenna_array->pattern[i] = pattern[i]; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Get antenna switch pin sequence. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[out] pattern Pin sequence that implements the antenna switch pattern. + * The first element in the sequence represents the + * reference antenna. + * @param[in,out] size Buffer length as input, actual pattern length as output. + ******************************************************************************/ +sl_status_t antenna_array_get_pin_pattern(antenna_array_t *antenna_array, + uint8_t *pattern, + uint8_t *size) +{ + if ((antenna_array == NULL) || (size == NULL)) { + return SL_STATUS_NULL_POINTER; + } + if (antenna_array_type_is_dp(antenna_array->array_type)) { + // Output buffer is optional. + if (pattern != NULL) { + // Check if output buffer size is large enough. + if (*size < (1 + (2 * antenna_array->size))) { + return SL_STATUS_INVALID_PARAMETER; + } + // Fill output buffer. + pattern[0] = reference_antenna; + for (uint8_t i = 0; i < antenna_array->size; i++) { + pattern[2 * i + 1] = antenna_array_dp_vertical[antenna_array->pattern[i]]; + pattern[2 * i + 2] = antenna_array_dp_horizontal[antenna_array->pattern[i]]; + } + } + *size = 1 + (2 * antenna_array->size); + } else { + // Output buffer is optional. + if (pattern != NULL) { + // Check if output buffer size is large enough. + if (*size < antenna_array->size) { + return SL_STATUS_INVALID_PARAMETER; + } + // Fill output buffer. + for (uint8_t i = 0; i < antenna_array->size; i++) { + pattern[i] = antenna_array->pattern[i]; + } + } + *size = antenna_array->size; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Convert antenna switch pattern to [0..n-1] interval without gaps. + ******************************************************************************/ +sl_status_t antenna_array_get_continuous_pattern(antenna_array_t *antenna_array, + uint32_t *pattern, + uint32_t *size) +{ + if ((antenna_array == NULL) || (pattern == NULL) || (size == NULL)) { + return SL_STATUS_NULL_POINTER; + } + + if (*size < antenna_array->size) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint8_t variant = get_array_variant(antenna_array->array_type, antenna_array->pattern); + if (variant == array_variants[antenna_array->array_type]) { + // Pattern corrupted. + return SL_STATUS_FAIL; + } + + uint8_t offset = variant * array_size[antenna_array->array_type]; + const uint8_t *reference_array = &array_list[antenna_array->array_type][offset]; + + for (uint8_t i = 0; i < antenna_array->size; i++) { + for (uint8_t j = 0; j < array_size[antenna_array->array_type]; j++) { + if (antenna_array->pattern[i] == reference_array[j]) { + pattern[i] = j; + break; + } + } + } + *size = antenna_array->size; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Shuffle the current antenna switch pattern. + ******************************************************************************/ +sl_status_t antenna_array_shuffle_pattern(antenna_array_t *antenna_array, + int(random)(void)) +{ + uint8_t i, j, temp; + + if ((antenna_array == NULL) || (random == NULL)) { + return SL_STATUS_NULL_POINTER; + } + // Swap index i with a random index j. + for (i = 0; i < antenna_array->size - 1; i++) { + j = i + 1 + (random() % (antenna_array->size - i - 1)); + temp = antenna_array->pattern[j]; + antenna_array->pattern[j] = antenna_array->pattern[i]; + antenna_array->pattern[i] = temp; + } + return SL_STATUS_OK; +} + +static uint8_t get_array_variant(uint8_t array_type, uint8_t *pattern) +{ + uint8_t variant; + uint8_t antenna_i; + uint8_t antenna_j; + + for (variant = 0; variant < array_variants[array_type]; variant++) { + for (antenna_i = 0; antenna_i < array_size[array_type]; antenna_i++) { + for (antenna_j = 0; (antenna_j < array_size[array_type]); antenna_j++) { + if (pattern[antenna_j] == array_list[array_type][variant * array_size[array_type] + antenna_i]) { + // Antenna found. + break; + } + } + if (antenna_j == array_size[array_type]) { + // Antenna not found, try next variant. + break; + } + } + if (antenna_i == array_size[array_type]) { + // All antennas found for the variant. + break; + } + } + return variant; +} + +// Assign a compatible board to an antenna array type. +sl_status_t antenna_array_type_to_board(uint8_t array_type, + antenna_array_board_t *board) +{ + if (board == NULL) { + return SL_STATUS_NULL_POINTER; + } else if (array_type < 0 || array_type >= ANTENNA_ARRAY_TYPE_LAST) { + return SL_STATUS_INVALID_PARAMETER; + } + *board = type_to_board[array_type]; + return SL_STATUS_OK; +} + +// Assign a default antenna array type to a board. +sl_status_t antenna_array_board_to_type(antenna_array_board_t board, + uint8_t *array_type) +{ + if (array_type == NULL) { + return SL_STATUS_NULL_POINTER; + } else if (board < 0 || board >= ANTENNA_ARRAY_BOARD_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } else if (board == ANTENNA_ARRAY_BOARD_UNKNOWN) { + return SL_STATUS_NOT_SUPPORTED; + } + *array_type = board_to_type[board]; + return SL_STATUS_OK; +} + +// Convert string to antenna array board. +sl_status_t antenna_array_string_to_board(const char *str, + antenna_array_board_t *board) +{ + if (str == NULL || board == NULL) { + return SL_STATUS_NULL_POINTER; + } + for (int i = 0; i < ANTENNA_ARRAY_BOARD_UNKNOWN; i++) { + if (strcmp(board_list_str[i], str) == 0) { + *board = (antenna_array_board_t)i; + return SL_STATUS_OK; + } + } + return SL_STATUS_NOT_SUPPORTED; +} + +// Convert antenna array board to string. +sl_status_t antenna_array_board_to_string(antenna_array_board_t board, + char *str) +{ + if (str == NULL) { + return SL_STATUS_NULL_POINTER; + } else if (board < 0 || board >= ANTENNA_ARRAY_BOARD_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } else if (board == ANTENNA_ARRAY_BOARD_UNKNOWN) { + return SL_STATUS_NOT_SUPPORTED; + } + + memcpy(str, board_list_str[board], strlen(board_list_str[board]) + 1); + return SL_STATUS_OK; +} diff --git a/locator_host/bt/aoa/antenna_array/antenna_array.h b/locator_host/bt/aoa/antenna_array/antenna_array.h index ee6f5ef..130784b 100644 --- a/locator_host/bt/aoa/antenna_array/antenna_array.h +++ b/locator_host/bt/aoa/antenna_array/antenna_array.h @@ -1,177 +1,177 @@ -/***************************************************************************//** - * @file - * @brief Antenna array handler for Silicon Labs boards. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef ANTENNA_ARRAY_H -#define ANTENNA_ARRAY_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// List of supported antenna array types. See also sl_rtl_aox_array_type. -#define ANTENNA_ARRAY_TYPE_4x4_URA 0 ///< Silicon Labs Ref. 4x4 Uniform Rectangular Array -#define ANTENNA_ARRAY_TYPE_3x3_URA 1 ///< Silicon Labs Ref. 3x3 Uniform Rectangular Array -#define ANTENNA_ARRAY_TYPE_1x4_ULA 2 ///< Silicon Labs Ref. 1x4 Uniform Linear Array -#define ANTENNA_ARRAY_TYPE_4x4_DP_URA 3 ///< Silicon Labs Ref. 4x4 Uniform Dual Polarized Rectangular Array -#define ANTENNA_ARRAY_TYPE_LAST 4 ///< Placeholder - -/// Check if antenna is of dual polarized type. -#define antenna_array_type_is_dp(x) ((x) == ANTENNA_ARRAY_TYPE_4x4_DP_URA) - -/// Antenna array returned by antenna_array_get_continuous_pattern is guaranteed -/// to fit into this buffer size. -#define ANTENNA_ARRAY_MAX_PATTERN_SIZE 16 - -/// Antenna array returned by antenna_array_get_pin_pattern is guaranteed -/// to fit into this buffer size. -#define ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE 33 - -/// Antenna array storage type. -typedef struct antenna_array_s { - uint8_t pattern[ANTENNA_ARRAY_MAX_PATTERN_SIZE]; - uint8_t size; - uint8_t array_type; -} antenna_array_t; - -/// List of supported boards. -typedef enum { - BRD4185A, - BRD4191A, - ANTENNA_ARRAY_BOARD_UNKNOWN, - ANTENNA_ARRAY_BOARD_COUNT -} antenna_array_board_t; - -/***************************************************************************//** - * Initialize antenna switch pattern with default values. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[in] array_type Antenna array type. - ******************************************************************************/ -sl_status_t antenna_array_init(antenna_array_t *antenna_array, - uint8_t array_type); - -/***************************************************************************//** - * Override antenna switch pattern. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[in] pattern New antenna switch pattern given as the antenna numbers - * printed on the board minus 1. E.g., antenna 1 is given as - * 0. - * @param[in] size Length of the pattern. - ******************************************************************************/ -sl_status_t antenna_array_set_pattern(antenna_array_t *antenna_array, - uint8_t *pattern, - uint8_t size); - -/***************************************************************************//** - * Get antenna switch pin sequence. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[out] pattern Pin sequence that implements the antenna switch pattern. - * The first element in the sequence represents the - * reference antenna. Optional argument, can be omitted - * by passing NULL. - * @param[in,out] size Buffer length as input, actual pattern length as output. - ******************************************************************************/ -sl_status_t antenna_array_get_pin_pattern(antenna_array_t *antenna_array, - uint8_t *pattern, - uint8_t *size); - -/***************************************************************************//** - * Convert antenna switch pattern to [0..n-1] interval without gaps. - * - * This function is relevant for reduced antenna boards like 3x3 URA or 1x4 ULA. - * If all antennas on the boards are in use, then the pattern returned by this - * function and the stored pattern are identical. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[out] pattern Buffer for the converted switch pattern. - * @param[in,out] size Buffer length as input, actual pattern length as output. - ******************************************************************************/ -sl_status_t antenna_array_get_continuous_pattern(antenna_array_t *antenna_array, - uint32_t *pattern, - uint32_t *size); - -/***************************************************************************//** - * Shuffle the current antenna switch pattern. - * - * @param[in] antenna_array Antenna array instance to operate on. - * @param[in] random Function generating random values. - ******************************************************************************/ -sl_status_t antenna_array_shuffle_pattern(antenna_array_t *antenna_array, - int(random)(void)); - -/***************************************************************************//** - * Assign a compatible board to an antenna array type. - * - * @param[in] array_type One of the supported antenna array types. - * @param[out] board Antenna array board that matches the array type. - * @return SL_STATUS_OK if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t antenna_array_type_to_board(uint8_t array_type, - antenna_array_board_t *board); - -/***************************************************************************//** - * Assign a default antenna array type to a board. - * - * @param[in] board One of the supported antenna array boards. - * @param[out] array_type Default antenna array type that matches the board. - * @return SL_STATUS_OK if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t antenna_array_board_to_type(antenna_array_board_t board, - uint8_t *array_type); - -/***************************************************************************//** - * Convert string to antenna array board. - * - * @param[in] str Input string. - * @param[out] board Antenna array board. - * @return SL_STATUS_OK if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t antenna_array_string_to_board(const char *str, - antenna_array_board_t *board); - -/***************************************************************************//** - * Convert antenna array board to string. - * - * @param[in] board Antenna array board. - * @param[out] str Output string. - * @return SL_STATUS_OK if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t antenna_array_board_to_string(antenna_array_board_t board, - char *str); - -#ifdef __cplusplus -}; -#endif - -#endif // ANTENNA_ARRAY_H +/***************************************************************************//** + * @file + * @brief Antenna array handler for Silicon Labs boards. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef ANTENNA_ARRAY_H +#define ANTENNA_ARRAY_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// List of supported antenna array types. See also sl_rtl_aox_array_type. +#define ANTENNA_ARRAY_TYPE_4x4_URA 0 ///< Silicon Labs Ref. 4x4 Uniform Rectangular Array +#define ANTENNA_ARRAY_TYPE_3x3_URA 1 ///< Silicon Labs Ref. 3x3 Uniform Rectangular Array +#define ANTENNA_ARRAY_TYPE_1x4_ULA 2 ///< Silicon Labs Ref. 1x4 Uniform Linear Array +#define ANTENNA_ARRAY_TYPE_4x4_DP_URA 3 ///< Silicon Labs Ref. 4x4 Uniform Dual Polarized Rectangular Array +#define ANTENNA_ARRAY_TYPE_LAST 4 ///< Placeholder + +/// Check if antenna is of dual polarized type. +#define antenna_array_type_is_dp(x) ((x) == ANTENNA_ARRAY_TYPE_4x4_DP_URA) + +/// Antenna array returned by antenna_array_get_continuous_pattern is guaranteed +/// to fit into this buffer size. +#define ANTENNA_ARRAY_MAX_PATTERN_SIZE 16 + +/// Antenna array returned by antenna_array_get_pin_pattern is guaranteed +/// to fit into this buffer size. +#define ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE 33 + +/// Antenna array storage type. +typedef struct antenna_array_s { + uint8_t pattern[ANTENNA_ARRAY_MAX_PATTERN_SIZE]; + uint8_t size; + uint8_t array_type; +} antenna_array_t; + +/// List of supported boards. +typedef enum { + BRD4185A, + BRD4191A, + ANTENNA_ARRAY_BOARD_UNKNOWN, + ANTENNA_ARRAY_BOARD_COUNT +} antenna_array_board_t; + +/***************************************************************************//** + * Initialize antenna switch pattern with default values. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[in] array_type Antenna array type. + ******************************************************************************/ +sl_status_t antenna_array_init(antenna_array_t *antenna_array, + uint8_t array_type); + +/***************************************************************************//** + * Override antenna switch pattern. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[in] pattern New antenna switch pattern given as the antenna numbers + * printed on the board minus 1. E.g., antenna 1 is given as + * 0. + * @param[in] size Length of the pattern. + ******************************************************************************/ +sl_status_t antenna_array_set_pattern(antenna_array_t *antenna_array, + uint8_t *pattern, + uint8_t size); + +/***************************************************************************//** + * Get antenna switch pin sequence. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[out] pattern Pin sequence that implements the antenna switch pattern. + * The first element in the sequence represents the + * reference antenna. Optional argument, can be omitted + * by passing NULL. + * @param[in,out] size Buffer length as input, actual pattern length as output. + ******************************************************************************/ +sl_status_t antenna_array_get_pin_pattern(antenna_array_t *antenna_array, + uint8_t *pattern, + uint8_t *size); + +/***************************************************************************//** + * Convert antenna switch pattern to [0..n-1] interval without gaps. + * + * This function is relevant for reduced antenna boards like 3x3 URA or 1x4 ULA. + * If all antennas on the boards are in use, then the pattern returned by this + * function and the stored pattern are identical. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[out] pattern Buffer for the converted switch pattern. + * @param[in,out] size Buffer length as input, actual pattern length as output. + ******************************************************************************/ +sl_status_t antenna_array_get_continuous_pattern(antenna_array_t *antenna_array, + uint32_t *pattern, + uint32_t *size); + +/***************************************************************************//** + * Shuffle the current antenna switch pattern. + * + * @param[in] antenna_array Antenna array instance to operate on. + * @param[in] random Function generating random values. + ******************************************************************************/ +sl_status_t antenna_array_shuffle_pattern(antenna_array_t *antenna_array, + int(random)(void)); + +/***************************************************************************//** + * Assign a compatible board to an antenna array type. + * + * @param[in] array_type One of the supported antenna array types. + * @param[out] board Antenna array board that matches the array type. + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t antenna_array_type_to_board(uint8_t array_type, + antenna_array_board_t *board); + +/***************************************************************************//** + * Assign a default antenna array type to a board. + * + * @param[in] board One of the supported antenna array boards. + * @param[out] array_type Default antenna array type that matches the board. + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t antenna_array_board_to_type(antenna_array_board_t board, + uint8_t *array_type); + +/***************************************************************************//** + * Convert string to antenna array board. + * + * @param[in] str Input string. + * @param[out] board Antenna array board. + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t antenna_array_string_to_board(const char *str, + antenna_array_board_t *board); + +/***************************************************************************//** + * Convert antenna array board to string. + * + * @param[in] board Antenna array board. + * @param[out] str Output string. + * @return SL_STATUS_OK if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t antenna_array_board_to_string(antenna_array_board_t board, + char *str); + +#ifdef __cplusplus +}; +#endif + +#endif // ANTENNA_ARRAY_H diff --git a/locator_host/bt/aoa/antenna_array/antenna_array_brd4191a.h b/locator_host/bt/aoa/antenna_array/antenna_array_brd4191a.h index 38af82f..4e01f05 100644 --- a/locator_host/bt/aoa/antenna_array/antenna_array_brd4191a.h +++ b/locator_host/bt/aoa/antenna_array/antenna_array_brd4191a.h @@ -1,125 +1,125 @@ -/***************************************************************************//** - * @file - * @brief 4x4 URA Dual Polarized antenna board pin definitions. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef ANTENNA_ARRAY_BRD4191A_H -#define ANTENNA_ARRAY_BRD4191A_H - -// CTRL5 pin (bit 4) selects one of the CHW switches when in DP mode. -#define CHW1 (0 << 4) -#define CHW2 (1 << 4) - -// CTRL6 pin (bit 5) selects DP/CP mode. -#define DP_MODE (0 << 5) -#define CP_MODE (1 << 5) - -// CTRL7 pin (bit 6) selects AoA/AoD mode. -#define AOA_MODE (0 << 6) -#define AOD_MODE (1 << 6) - -// CTRL1..CTRL4 pins (bits 0..3) select one of the 16 outputs -// of both CHW switches simultaneously. -#define ANT_V1 (DP_MODE | CHW1 | 2) -#define ANT_H1 (DP_MODE | CHW1 | 3) -#define ANT_V2 (DP_MODE | CHW1 | 0) -#define ANT_H2 (DP_MODE | CHW1 | 1) -#define ANT_V3 (DP_MODE | CHW1 | 14) -#define ANT_H3 (DP_MODE | CHW1 | 15) -#define ANT_V4 (DP_MODE | CHW1 | 12) -#define ANT_H4 (DP_MODE | CHW1 | 13) -#define ANT_V5 (DP_MODE | CHW1 | 4) -#define ANT_H5 (DP_MODE | CHW1 | 5) -#define ANT_V6 (DP_MODE | CHW1 | 8) -#define ANT_H6 (DP_MODE | CHW2 | 8) -#define ANT_V7 (DP_MODE | CHW2 | 4) -#define ANT_H7 (DP_MODE | CHW2 | 5) -#define ANT_V8 (DP_MODE | CHW1 | 10) -#define ANT_H8 (DP_MODE | CHW1 | 11) -#define ANT_V9 (DP_MODE | CHW1 | 6) -#define ANT_H9 (DP_MODE | CHW1 | 7) -#define ANT_V10 (DP_MODE | CHW2 | 6) -#define ANT_H10 (DP_MODE | CHW2 | 7) -#define ANT_V11 (DP_MODE | CHW2 | 0) -#define ANT_H11 (DP_MODE | CHW2 | 1) -#define ANT_V12 (DP_MODE | CHW2 | 3) -#define ANT_H12 (DP_MODE | CHW2 | 2) -#define ANT_V13 (DP_MODE | CHW1 | 9) -#define ANT_H13 (DP_MODE | CHW2 | 9) -#define ANT_V14 (DP_MODE | CHW2 | 10) -#define ANT_H14 (DP_MODE | CHW2 | 11) -#define ANT_V15 (DP_MODE | CHW2 | 12) -#define ANT_H15 (DP_MODE | CHW2 | 13) -#define ANT_V16 (DP_MODE | CHW2 | 15) -#define ANT_H16 (DP_MODE | CHW2 | 14) - -// The following antennas are available in CP mode. -#define ANT_6_CP (CP_MODE | 8) -#define ANT_13_CP (CP_MODE | 9) - -// Vertically polarized antennas. -#define ANT_VERTICAL { \ - ANT_V1, \ - ANT_V2, \ - ANT_V3, \ - ANT_V4, \ - ANT_V5, \ - ANT_V6, \ - ANT_V7, \ - ANT_V8, \ - ANT_V9, \ - ANT_V10, \ - ANT_V11, \ - ANT_V12, \ - ANT_V13, \ - ANT_V14, \ - ANT_V15, \ - ANT_V16 \ -} - -// Horizontally polarized antennas. -#define ANT_HORIZONTAL { \ - ANT_H1, \ - ANT_H2, \ - ANT_H3, \ - ANT_H4, \ - ANT_H5, \ - ANT_H6, \ - ANT_H7, \ - ANT_H8, \ - ANT_H9, \ - ANT_H10, \ - ANT_H11, \ - ANT_H12, \ - ANT_H13, \ - ANT_H14, \ - ANT_H15, \ - ANT_H16 \ -} - -#endif // ANTENNA_ARRAY_BRD4191A_H +/***************************************************************************//** + * @file + * @brief 4x4 URA Dual Polarized antenna board pin definitions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef ANTENNA_ARRAY_BRD4191A_H +#define ANTENNA_ARRAY_BRD4191A_H + +// CTRL5 pin (bit 4) selects one of the CHW switches when in DP mode. +#define CHW1 (0 << 4) +#define CHW2 (1 << 4) + +// CTRL6 pin (bit 5) selects DP/CP mode. +#define DP_MODE (0 << 5) +#define CP_MODE (1 << 5) + +// CTRL7 pin (bit 6) selects AoA/AoD mode. +#define AOA_MODE (0 << 6) +#define AOD_MODE (1 << 6) + +// CTRL1..CTRL4 pins (bits 0..3) select one of the 16 outputs +// of both CHW switches simultaneously. +#define ANT_V1 (DP_MODE | CHW1 | 2) +#define ANT_H1 (DP_MODE | CHW1 | 3) +#define ANT_V2 (DP_MODE | CHW1 | 0) +#define ANT_H2 (DP_MODE | CHW1 | 1) +#define ANT_V3 (DP_MODE | CHW1 | 14) +#define ANT_H3 (DP_MODE | CHW1 | 15) +#define ANT_V4 (DP_MODE | CHW1 | 12) +#define ANT_H4 (DP_MODE | CHW1 | 13) +#define ANT_V5 (DP_MODE | CHW1 | 4) +#define ANT_H5 (DP_MODE | CHW1 | 5) +#define ANT_V6 (DP_MODE | CHW1 | 8) +#define ANT_H6 (DP_MODE | CHW2 | 8) +#define ANT_V7 (DP_MODE | CHW2 | 4) +#define ANT_H7 (DP_MODE | CHW2 | 5) +#define ANT_V8 (DP_MODE | CHW1 | 10) +#define ANT_H8 (DP_MODE | CHW1 | 11) +#define ANT_V9 (DP_MODE | CHW1 | 6) +#define ANT_H9 (DP_MODE | CHW1 | 7) +#define ANT_V10 (DP_MODE | CHW2 | 6) +#define ANT_H10 (DP_MODE | CHW2 | 7) +#define ANT_V11 (DP_MODE | CHW2 | 0) +#define ANT_H11 (DP_MODE | CHW2 | 1) +#define ANT_V12 (DP_MODE | CHW2 | 3) +#define ANT_H12 (DP_MODE | CHW2 | 2) +#define ANT_V13 (DP_MODE | CHW1 | 9) +#define ANT_H13 (DP_MODE | CHW2 | 9) +#define ANT_V14 (DP_MODE | CHW2 | 10) +#define ANT_H14 (DP_MODE | CHW2 | 11) +#define ANT_V15 (DP_MODE | CHW2 | 12) +#define ANT_H15 (DP_MODE | CHW2 | 13) +#define ANT_V16 (DP_MODE | CHW2 | 15) +#define ANT_H16 (DP_MODE | CHW2 | 14) + +// The following antennas are available in CP mode. +#define ANT_6_CP (CP_MODE | 8) +#define ANT_13_CP (CP_MODE | 9) + +// Vertically polarized antennas. +#define ANT_VERTICAL { \ + ANT_V1, \ + ANT_V2, \ + ANT_V3, \ + ANT_V4, \ + ANT_V5, \ + ANT_V6, \ + ANT_V7, \ + ANT_V8, \ + ANT_V9, \ + ANT_V10, \ + ANT_V11, \ + ANT_V12, \ + ANT_V13, \ + ANT_V14, \ + ANT_V15, \ + ANT_V16 \ +} + +// Horizontally polarized antennas. +#define ANT_HORIZONTAL { \ + ANT_H1, \ + ANT_H2, \ + ANT_H3, \ + ANT_H4, \ + ANT_H5, \ + ANT_H6, \ + ANT_H7, \ + ANT_H8, \ + ANT_H9, \ + ANT_H10, \ + ANT_H11, \ + ANT_H12, \ + ANT_H13, \ + ANT_H14, \ + ANT_H15, \ + ANT_H16 \ +} + +#endif // ANTENNA_ARRAY_BRD4191A_H diff --git a/locator_host/bt/aoa/aoa_angle/aoa_angle.c b/locator_host/bt/aoa/aoa_angle/aoa_angle.c index bedbbcb..2700bda 100644 --- a/locator_host/bt/aoa/aoa_angle/aoa_angle.c +++ b/locator_host/bt/aoa/aoa_angle/aoa_angle.c @@ -1,711 +1,711 @@ -/***************************************************************************//** - * @file - * @brief Estimate angle data from IQ samples. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include -#include - -#include "aoa_angle.h" -#include "aoa_angle_config.h" -#include "app_log.h" - -// ----------------------------------------------------------------------------- -// Defines - -#define CHECK_ERROR(x) if ((x) != SL_RTL_ERROR_SUCCESS) return (x) - -#define GUARD_PERIOD_US 4 -#define REFERENCE_PERIOD_US 8 -#define REFERENCE_PERIOD_SAMPLES 8 - -#define QUALITY_BUFFER_SIZE 100 - -// ----------------------------------------------------------------------------- -// Type definitions - -typedef struct aoa_angle_config_node_s aoa_angle_config_node_t; -struct aoa_angle_config_node_s { - aoa_id_t id; - aoa_angle_config_t aoa_angle_config; - aoa_angle_config_node_t *next; - float ref_i_samples[REFERENCE_PERIOD_SAMPLES]; - float ref_q_samples[REFERENCE_PERIOD_SAMPLES]; - float **i_samples; - float **q_samples; - size_t sample_rows; - size_t sample_cols; -}; - -// ----------------------------------------------------------------------------- -// Private variables - -// Linked list head -static aoa_angle_config_node_t *head_config = NULL; - -// ----------------------------------------------------------------------------- -// Private function declarations - -static sl_status_t allocate_2D_float_buffer(float*** buf, - size_t rows, - size_t cols); -static void free_2D_float_buffer(float** buf, size_t rows); -static sl_status_t allocate_sample_buffers(aoa_angle_config_node_t *node); -static void free_sample_buffers(aoa_angle_config_node_t *node); -static void free_masks(aoa_mask_node_t *mask_head); -static void get_samples(aoa_iq_report_t *iq_report, - aoa_angle_config_node_t *node); -static float channel_to_frequency(uint8_t channel); -static sl_status_t aoa_angle_set_default_config(aoa_angle_config_t *aoa_angle_config); -static sl_status_t aoa_angle_finalize_node(aoa_angle_config_node_t *node); -static sl_status_t aoa_angle_find(aoa_id_t id, aoa_angle_config_node_t **node); - -// ----------------------------------------------------------------------------- -// Public function definitions - -/**************************************************************************//** - * Add a config to the config list. - *****************************************************************************/ -sl_status_t aoa_angle_add_config(aoa_id_t id, - aoa_angle_config_t **config) -{ - aoa_angle_config_node_t *new; - sl_status_t sc; - - if (SL_STATUS_OK == aoa_angle_find(id, NULL)) { - return SL_STATUS_ALREADY_EXISTS; - } - - new = malloc(sizeof(aoa_angle_config_node_t)); - if (NULL == new) { - return SL_STATUS_ALLOCATION_FAILED; - } - - aoa_id_copy(new->id, id); - new->next = head_config; - head_config = new; - if (NULL != config) { - *config = &(new->aoa_angle_config); - } - - // Initialize sample buffers - new->i_samples = NULL; - new->q_samples = NULL; - new->sample_rows = 0; - new->sample_cols = 0; - - sc = aoa_angle_set_default_config(&new->aoa_angle_config); - if (sc == SL_STATUS_OK) { - sc = aoa_angle_finalize_node(new); - } - return sc; -} - -/**************************************************************************//** - * Add an azimuth mask to the list. - *****************************************************************************/ -sl_status_t aoa_angle_add_azimuth_mask(aoa_id_t config_id, - float min, - float max) -{ - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config; - aoa_mask_node_t *new; - - sc = aoa_angle_get_config(config_id, &aoa_angle_config); - if (SL_STATUS_OK == sc) { - new = malloc(sizeof(aoa_mask_node_t)); - if (NULL == new) { - sc = SL_STATUS_ALLOCATION_FAILED; - } else { - new->max = max; - new->min = min; - - new->next = aoa_angle_config->azimuth_mask_head; - aoa_angle_config->azimuth_mask_head = new; - } - } - return sc; -} - -/**************************************************************************//** - * Add an elevation mask to the list. - *****************************************************************************/ -sl_status_t aoa_angle_add_elevation_mask(aoa_id_t config_id, - float min, - float max) -{ - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config; - aoa_mask_node_t *new; - - sc = aoa_angle_get_config(config_id, &aoa_angle_config); - if (SL_STATUS_OK == sc) { - new = malloc(sizeof(aoa_mask_node_t)); - if (NULL == new) { - sc = SL_STATUS_ALLOCATION_FAILED; - } else { - new->max = max; - new->min = min; - - new->next = aoa_angle_config->elevation_mask_head; - aoa_angle_config->elevation_mask_head = new; - } - } - return sc; -} - -/**************************************************************************//** - * Reset the azimuth mask database - *****************************************************************************/ -sl_status_t aoa_angle_reset_azimuth_masks(aoa_id_t id) -{ - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config; - - sc = aoa_angle_get_config(id, &aoa_angle_config); - if (SL_STATUS_OK == sc) { - free_masks(aoa_angle_config->azimuth_mask_head); - aoa_angle_config->azimuth_mask_head = NULL; - } - - return sc; -} - -/**************************************************************************//** - * Reset the elevation mask database - *****************************************************************************/ -sl_status_t aoa_angle_reset_elevation_masks(aoa_id_t id) -{ - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config; - - sc = aoa_angle_get_config(id, &aoa_angle_config); - if (SL_STATUS_OK == sc) { - free_masks(aoa_angle_config->elevation_mask_head); - aoa_angle_config->elevation_mask_head = NULL; - } - - return sc; -} - -/**************************************************************************//** - * Reset the config database. - *****************************************************************************/ -void aoa_angle_reset_configs(void) -{ - aoa_angle_config_node_t *current = head_config; - - while (NULL != current) { - // At the end of the iteration, head will be automatically set to NULL. - head_config = current->next; - free_sample_buffers(current); - free_masks(current->aoa_angle_config.azimuth_mask_head); - free_masks(current->aoa_angle_config.elevation_mask_head); - free(current); - current = head_config; - } -} - -/**************************************************************************//** - * Return a config from the config list by its ID. - *****************************************************************************/ -sl_status_t aoa_angle_get_config(aoa_id_t id, - aoa_angle_config_t **config) -{ - sl_status_t sc; - aoa_angle_config_node_t *node; - - sc = aoa_angle_find(id, &node); - if (sc == SL_STATUS_OK) { - *config = &node->aoa_angle_config; - } - - return sc; -} - -/**************************************************************************//** - * Finalize configuration settings. - *****************************************************************************/ -sl_status_t aoa_angle_finalize_config(aoa_id_t id) -{ - sl_status_t sc; - aoa_angle_config_node_t *node; - - sc = aoa_angle_find(id, &node); - if (sc == SL_STATUS_OK) { - sc = aoa_angle_finalize_node(node); - } - - return sc; -} - -/***************************************************************************//** - * Initialize angle calculation libraries - ******************************************************************************/ -enum sl_rtl_error_code aoa_init_rtl(aoa_state_t *aoa_state, - aoa_id_t config_id, - bool qa_enable) -{ - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config = NULL; - aoa_mask_node_t *current_azimuth; - aoa_mask_node_t *current_elevation; - uint32_t antenna_switch_pattern[ANTENNA_ARRAY_MAX_PATTERN_SIZE]; - uint32_t antenna_switch_pattern_size = sizeof(antenna_switch_pattern) / sizeof(uint32_t); - - sc = aoa_angle_get_config(config_id, &aoa_angle_config); - if (SL_STATUS_OK != sc) { - return SL_RTL_ERROR_ARGUMENT; - } - - sc = antenna_array_get_continuous_pattern(&aoa_angle_config->antenna_array, - antenna_switch_pattern, - &antenna_switch_pattern_size); - if (SL_STATUS_OK != sc) { - return SL_RTL_ERROR_ARGUMENT; - } - - current_azimuth = aoa_angle_config->azimuth_mask_head; - current_elevation = aoa_angle_config->elevation_mask_head; - - enum sl_rtl_error_code ec; - // Initialize AoX library - ec = sl_rtl_aox_init(&aoa_state->libitem); - CHECK_ERROR(ec); - // Set the number of snapshots, i.e. how many times the antennas are scanned - // during one measurement - ec = sl_rtl_aox_set_num_snapshots(&aoa_state->libitem, - aoa_angle_config->num_snapshots); - CHECK_ERROR(ec); - // Set the antenna array type - ec = sl_rtl_aox_set_array_type(&aoa_state->libitem, - aoa_angle_config->antenna_array.array_type); - CHECK_ERROR(ec); - // Select mode (high speed/high accuracy/etc.) - ec = sl_rtl_aox_set_mode(&aoa_state->libitem, - aoa_angle_config->aox_mode); - CHECK_ERROR(ec); - - aoa_state->qa_enable = qa_enable; - if (qa_enable) { - // Enable IQ sample quality analysis processing - ec = sl_rtl_aox_iq_sample_qa_configure(&aoa_state->libitem); - CHECK_ERROR(ec); - } - - // Add azimuth constraints - while (current_azimuth != NULL) { - ec = sl_rtl_aox_add_constraint(&aoa_state->libitem, - SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH, - current_azimuth->min, - current_azimuth->max); - CHECK_ERROR(ec); - current_azimuth = current_azimuth->next; - } - - // Add elevation constraints - while (current_elevation != NULL) { - ec = sl_rtl_aox_add_constraint(&aoa_state->libitem, - SL_RTL_AOX_CONSTRAINT_TYPE_ELEVATION, - current_elevation->min, - current_elevation->max); - CHECK_ERROR(ec); - current_elevation = current_elevation->next; - } - - // Create AoX estimator - ec = sl_rtl_aox_create_estimator(&aoa_state->libitem); - CHECK_ERROR(ec); - // Set the switching pattern mode - ec = sl_rtl_aox_set_switch_pattern_mode(&aoa_state->libitem, SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL); - CHECK_ERROR(ec); - if (antenna_array_type_is_dp(aoa_angle_config->antenna_array.array_type)) { - // Skip samples from the reference antenna. - ec = sl_rtl_aox_set_switch_pattern_mode(&aoa_state->libitem, SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTRA_REFERENCE); - CHECK_ERROR(ec); - } - // Set the switching pattern - ec = sl_rtl_aox_update_switch_pattern(&aoa_state->libitem, antenna_switch_pattern, NULL); - CHECK_ERROR(ec); - if (aoa_angle_config->angle_filtering == true) { - // Initialize an util item - ec = sl_rtl_util_init(&aoa_state->util_libitem); - CHECK_ERROR(ec); - ec = sl_rtl_util_set_parameter(&aoa_state->util_libitem, - SL_RTL_UTIL_PARAMETER_AMOUNT_OF_FILTERING, - aoa_angle_config->angle_filtering_weight); - CHECK_ERROR(ec); - } - // Initialize correction timeout counter - aoa_state->correction_timeout = 0; - - return ec; -} - -/***************************************************************************//** - * Estimate angle data from IQ samples - ******************************************************************************/ -enum sl_rtl_error_code aoa_calculate(aoa_state_t *aoa_state, - aoa_iq_report_t *iq_report, - aoa_angle_t *angle, - aoa_id_t config_id) -{ - enum sl_rtl_error_code ec; - float phase_rotation; - sl_status_t sc; - aoa_angle_config_node_t *node; - aoa_angle_config_t *aoa_angle_config; - uint32_t quality; - char quality_buffer[QUALITY_BUFFER_SIZE]; - char* quality_string; - - sc = aoa_angle_find(config_id, &node); - if (SL_STATUS_OK != sc) { - return SL_RTL_ERROR_ARGUMENT; - } - - aoa_angle_config = &node->aoa_angle_config; - - // Copy IQ samples into preallocated buffers. - get_samples(iq_report, node); - - // Calculate phase rotation from reference IQ samples. - ec = sl_rtl_aox_calculate_iq_sample_phase_rotation(&aoa_state->libitem, - 2.0f, - node->ref_i_samples, - node->ref_q_samples, - REFERENCE_PERIOD_SAMPLES, - &phase_rotation); - CHECK_ERROR(ec); - - // Provide calculated phase rotation to the estimator. - ec = sl_rtl_aox_set_iq_sample_phase_rotation(&aoa_state->libitem, - phase_rotation); - CHECK_ERROR(ec); - - // Estimate Angle of Arrival from IQ samples. - // sl_rtl_aox_process will return SL_RTL_ERROR_ESTIMATION_IN_PROGRESS - // until it has received enough packets for angle estimation. - ec = sl_rtl_aox_process(&aoa_state->libitem, - node->i_samples, - node->q_samples, - channel_to_frequency(iq_report->channel), - &angle->azimuth, - &angle->elevation); - CHECK_ERROR(ec); - - ec = sl_rtl_aox_get_latest_aoa_standard_deviation(&aoa_state->libitem, - &angle->azimuth_stdev, - &angle->elevation_stdev); - CHECK_ERROR(ec); - - // Calculate distance from RSSI. - ec = sl_rtl_util_rssi2distance(AOA_ANGLE_TAG_TX_POWER, - (float)iq_report->rssi, - &angle->distance); - CHECK_ERROR(ec); - - // Distance standard deviation is not supported, use 0. - angle->distance_stdev = 0; - - if (aoa_angle_config->angle_filtering == true) { - ec = sl_rtl_util_filter(&aoa_state->util_libitem, - angle->distance, - &angle->distance); - CHECK_ERROR(ec); - } - - // Copy sequence counter. - angle->sequence = iq_report->event_counter; - - if (aoa_state->qa_enable) { - // Fetch the quality result. - quality = sl_rtl_aox_iq_sample_qa_get_results(&aoa_state->libitem); - if (quality != 0) { - quality_string = sl_rtl_util_iq_sample_qa_code2string(quality_buffer, - sizeof(quality_buffer), - quality); - app_log_debug("%s [%d] quality: %s" APP_LOG_NL, - config_id, - angle->sequence, - quality_string); - } - } - - if (aoa_state->correction_timeout > 0) { - // Decrement timeout counter. - --aoa_state->correction_timeout; - if (aoa_state->correction_timeout == 0) { - // Timer expired, clear correction values. - ec = sl_rtl_aox_clear_expected_direction(&aoa_state->libitem); - } - } - return ec; -} - -/***************************************************************************//** - * Set correction data for the estimator - ******************************************************************************/ -enum sl_rtl_error_code aoa_set_correction(aoa_state_t *aoa_state, - aoa_angle_t *correction, - aoa_id_t config_id) -{ - enum sl_rtl_error_code ec; - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config = NULL; - - sc = aoa_angle_get_config(config_id, &aoa_angle_config); - if (SL_STATUS_OK != sc) { - return SL_RTL_ERROR_ARGUMENT; - } - - ec = sl_rtl_aox_set_expected_direction(&aoa_state->libitem, - correction->azimuth, - correction->elevation); - CHECK_ERROR(ec); - ec = sl_rtl_aox_set_expected_deviation(&aoa_state->libitem, - correction->azimuth_stdev, - correction->elevation_stdev); - CHECK_ERROR(ec); - - aoa_state->correction_timeout = aoa_angle_config->angle_correction_timeout; - return ec; -} - -/***************************************************************************//** - * Deinitialize angle calculation libraries - ******************************************************************************/ -enum sl_rtl_error_code aoa_deinit_rtl(aoa_state_t *aoa_state, - aoa_id_t config_id) -{ - enum sl_rtl_error_code ec; - sl_status_t sc; - aoa_angle_config_t *aoa_angle_config = NULL; - - sc = aoa_angle_get_config(config_id, &aoa_angle_config); - if (SL_STATUS_OK != sc) { - return SL_RTL_ERROR_ARGUMENT; - } - - ec = sl_rtl_aox_deinit(&aoa_state->libitem); - CHECK_ERROR(ec); - if (aoa_angle_config->angle_filtering == true) { - ec = sl_rtl_util_deinit(&aoa_state->util_libitem); - CHECK_ERROR(ec); - } - - return ec; -} - -// ----------------------------------------------------------------------------- -// Private function declarations - -static sl_status_t allocate_2D_float_buffer(float*** buf, size_t rows, size_t cols) -{ - *buf = malloc(sizeof(float*) * rows); - if (*buf == NULL) { - return SL_STATUS_ALLOCATION_FAILED; - } - - for (size_t i = 0; i < rows; i++) { - (*buf)[i] = malloc(sizeof(float) * cols); - if ((*buf)[i] == NULL) { - return SL_STATUS_ALLOCATION_FAILED; - } - } - - return SL_STATUS_OK; -} - -static void free_2D_float_buffer(float** buf, size_t rows) -{ - for (size_t i = 0; i < rows; i++) { - free(buf[i]); - } - free(buf); -} - -static float channel_to_frequency(uint8_t channel) -{ - static const uint8_t logical_to_physical_channel[40] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, - 0, 12, 39 - }; - - // Return the center frequency of the given channel. - return 2402000000 + 2000000 * logical_to_physical_channel[channel]; -} - -static void get_samples(aoa_iq_report_t *iq_report, aoa_angle_config_node_t *node) -{ - size_t index = 0; - // Write reference IQ samples into the IQ sample buffer (sampled on one antenna) - for (size_t sample = 0; sample < REFERENCE_PERIOD_SAMPLES; ++sample) { - node->ref_i_samples[sample] = iq_report->samples[index++] / 127.0; - if (index == iq_report->length) { - break; - } - node->ref_q_samples[sample] = iq_report->samples[index++] / 127.0; - if (index == iq_report->length) { - break; - } - } - // The last reference sample is the first measurement sample too. - index = (REFERENCE_PERIOD_SAMPLES - 1) * 2; - // Write antenna IQ samples into the IQ sample buffer (sampled on all antennas) - for (size_t snapshot = 0; snapshot < node->sample_rows; ++snapshot) { - for (size_t antenna = 0; antenna < node->sample_cols; ++antenna) { - node->i_samples[snapshot][antenna] = iq_report->samples[index++] / 127.0; - if (index == iq_report->length) { - break; - } - node->q_samples[snapshot][antenna] = iq_report->samples[index++] / 127.0; - if (index == iq_report->length) { - break; - } - } - if (index == iq_report->length) { - break; - } - } -} - -/**************************************************************************//** - * Sets the default config. - *****************************************************************************/ -static sl_status_t aoa_angle_set_default_config(aoa_angle_config_t *aoa_angle_config) -{ - aoa_angle_config->aox_mode = AOA_ANGLE_AOX_MODE; - aoa_angle_config->angle_filtering = true; - aoa_angle_config->angle_filtering_weight = AOA_ANGLE_FILTERING_AMOUNT; - aoa_angle_config->angle_correction_timeout = AOA_ANGLE_CORRECTION_TIMEOUT; - aoa_angle_config->angle_correction_delay = AOA_ANGLE_MAX_CORRECTION_DELAY; - aoa_angle_config->cte_min_length = AOA_ANGLE_CTE_MIN_LENGTH; - aoa_angle_config->cte_slot_duration = AOA_ANGLE_CTE_SLOT_DURATION; - aoa_angle_config->azimuth_mask_head = NULL; - aoa_angle_config->elevation_mask_head = NULL; - return antenna_array_init(&aoa_angle_config->antenna_array, - AOA_ANGLE_ANTENNA_ARRAY_TYPE); -} - -static sl_status_t aoa_angle_finalize_node(aoa_angle_config_node_t *node) -{ - aoa_angle_config_t *cfg = &node->aoa_angle_config; - uint8_t antenna_switch_pattern_size; - sl_status_t sc; - - sc = antenna_array_get_pin_pattern(&cfg->antenna_array, - NULL, - &antenna_switch_pattern_size); - if (sc != SL_STATUS_OK) { - return sc; - } - - cfg->num_snapshots = (uint8_t)(((cfg->cte_min_length * 8) - - GUARD_PERIOD_US - REFERENCE_PERIOD_US) - / (cfg->cte_slot_duration * 2) - / antenna_switch_pattern_size); - - return allocate_sample_buffers(node); -} - -static sl_status_t allocate_sample_buffers(aoa_angle_config_node_t *node) -{ - sl_status_t sc; - aoa_angle_config_t *cfg = &node->aoa_angle_config; - uint8_t antenna_switch_pattern_size; - - sc = antenna_array_get_pin_pattern(&cfg->antenna_array, - NULL, - &antenna_switch_pattern_size); - if (sc != SL_STATUS_OK) { - return sc; - } - - // Reallocate sample buffers - if ((node->sample_rows != cfg->num_snapshots) - || (node->sample_cols != antenna_switch_pattern_size)) { - free_2D_float_buffer(node->i_samples, node->sample_rows); - free_2D_float_buffer(node->q_samples, node->sample_rows); - sc = allocate_2D_float_buffer(&node->i_samples, - cfg->num_snapshots, - antenna_switch_pattern_size); - if (SL_STATUS_OK != sc) { - return sc; - } - sc = allocate_2D_float_buffer(&node->q_samples, - cfg->num_snapshots, - antenna_switch_pattern_size); - if (SL_STATUS_OK != sc) { - return sc; - } - // Store new sample buffer dimensions - node->sample_rows = cfg->num_snapshots; - node->sample_cols = antenna_switch_pattern_size; - } - - return SL_STATUS_OK; -} - -static void free_sample_buffers(aoa_angle_config_node_t *node) -{ - free_2D_float_buffer(node->i_samples, node->sample_rows); - free_2D_float_buffer(node->q_samples, node->sample_rows); -} - -static sl_status_t aoa_angle_find(aoa_id_t id, aoa_angle_config_node_t **node) -{ - aoa_angle_config_node_t *current = head_config; - - while (NULL != current) { - if (aoa_id_compare(id, current->id) == 0) { - if (NULL != node) { - *node = current; - } - return SL_STATUS_OK; - } - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -static void free_masks(aoa_mask_node_t *mask_head) -{ - aoa_mask_node_t *current; - aoa_mask_node_t *next; - - for (current = mask_head; current != NULL; current = next) { - next = current->next; - free(current); - } -} +/***************************************************************************//** + * @file + * @brief Estimate angle data from IQ samples. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "aoa_angle.h" +#include "aoa_angle_config.h" +#include "app_log.h" + +// ----------------------------------------------------------------------------- +// Defines + +#define CHECK_ERROR(x) if ((x) != SL_RTL_ERROR_SUCCESS) return (x) + +#define GUARD_PERIOD_US 4 +#define REFERENCE_PERIOD_US 8 +#define REFERENCE_PERIOD_SAMPLES 8 + +#define QUALITY_BUFFER_SIZE 100 + +// ----------------------------------------------------------------------------- +// Type definitions + +typedef struct aoa_angle_config_node_s aoa_angle_config_node_t; +struct aoa_angle_config_node_s { + aoa_id_t id; + aoa_angle_config_t aoa_angle_config; + aoa_angle_config_node_t *next; + float ref_i_samples[REFERENCE_PERIOD_SAMPLES]; + float ref_q_samples[REFERENCE_PERIOD_SAMPLES]; + float **i_samples; + float **q_samples; + size_t sample_rows; + size_t sample_cols; +}; + +// ----------------------------------------------------------------------------- +// Private variables + +// Linked list head +static aoa_angle_config_node_t *head_config = NULL; + +// ----------------------------------------------------------------------------- +// Private function declarations + +static sl_status_t allocate_2D_float_buffer(float*** buf, + size_t rows, + size_t cols); +static void free_2D_float_buffer(float** buf, size_t rows); +static sl_status_t allocate_sample_buffers(aoa_angle_config_node_t *node); +static void free_sample_buffers(aoa_angle_config_node_t *node); +static void free_masks(aoa_mask_node_t *mask_head); +static void get_samples(aoa_iq_report_t *iq_report, + aoa_angle_config_node_t *node); +static float channel_to_frequency(uint8_t channel); +static sl_status_t aoa_angle_set_default_config(aoa_angle_config_t *aoa_angle_config); +static sl_status_t aoa_angle_finalize_node(aoa_angle_config_node_t *node); +static sl_status_t aoa_angle_find(aoa_id_t id, aoa_angle_config_node_t **node); + +// ----------------------------------------------------------------------------- +// Public function definitions + +/**************************************************************************//** + * Add a config to the config list. + *****************************************************************************/ +sl_status_t aoa_angle_add_config(aoa_id_t id, + aoa_angle_config_t **config) +{ + aoa_angle_config_node_t *new; + sl_status_t sc; + + if (SL_STATUS_OK == aoa_angle_find(id, NULL)) { + return SL_STATUS_ALREADY_EXISTS; + } + + new = malloc(sizeof(aoa_angle_config_node_t)); + if (NULL == new) { + return SL_STATUS_ALLOCATION_FAILED; + } + + aoa_id_copy(new->id, id); + new->next = head_config; + head_config = new; + if (NULL != config) { + *config = &(new->aoa_angle_config); + } + + // Initialize sample buffers + new->i_samples = NULL; + new->q_samples = NULL; + new->sample_rows = 0; + new->sample_cols = 0; + + sc = aoa_angle_set_default_config(&new->aoa_angle_config); + if (sc == SL_STATUS_OK) { + sc = aoa_angle_finalize_node(new); + } + return sc; +} + +/**************************************************************************//** + * Add an azimuth mask to the list. + *****************************************************************************/ +sl_status_t aoa_angle_add_azimuth_mask(aoa_id_t config_id, + float min, + float max) +{ + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config; + aoa_mask_node_t *new; + + sc = aoa_angle_get_config(config_id, &aoa_angle_config); + if (SL_STATUS_OK == sc) { + new = malloc(sizeof(aoa_mask_node_t)); + if (NULL == new) { + sc = SL_STATUS_ALLOCATION_FAILED; + } else { + new->max = max; + new->min = min; + + new->next = aoa_angle_config->azimuth_mask_head; + aoa_angle_config->azimuth_mask_head = new; + } + } + return sc; +} + +/**************************************************************************//** + * Add an elevation mask to the list. + *****************************************************************************/ +sl_status_t aoa_angle_add_elevation_mask(aoa_id_t config_id, + float min, + float max) +{ + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config; + aoa_mask_node_t *new; + + sc = aoa_angle_get_config(config_id, &aoa_angle_config); + if (SL_STATUS_OK == sc) { + new = malloc(sizeof(aoa_mask_node_t)); + if (NULL == new) { + sc = SL_STATUS_ALLOCATION_FAILED; + } else { + new->max = max; + new->min = min; + + new->next = aoa_angle_config->elevation_mask_head; + aoa_angle_config->elevation_mask_head = new; + } + } + return sc; +} + +/**************************************************************************//** + * Reset the azimuth mask database + *****************************************************************************/ +sl_status_t aoa_angle_reset_azimuth_masks(aoa_id_t id) +{ + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config; + + sc = aoa_angle_get_config(id, &aoa_angle_config); + if (SL_STATUS_OK == sc) { + free_masks(aoa_angle_config->azimuth_mask_head); + aoa_angle_config->azimuth_mask_head = NULL; + } + + return sc; +} + +/**************************************************************************//** + * Reset the elevation mask database + *****************************************************************************/ +sl_status_t aoa_angle_reset_elevation_masks(aoa_id_t id) +{ + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config; + + sc = aoa_angle_get_config(id, &aoa_angle_config); + if (SL_STATUS_OK == sc) { + free_masks(aoa_angle_config->elevation_mask_head); + aoa_angle_config->elevation_mask_head = NULL; + } + + return sc; +} + +/**************************************************************************//** + * Reset the config database. + *****************************************************************************/ +void aoa_angle_reset_configs(void) +{ + aoa_angle_config_node_t *current = head_config; + + while (NULL != current) { + // At the end of the iteration, head will be automatically set to NULL. + head_config = current->next; + free_sample_buffers(current); + free_masks(current->aoa_angle_config.azimuth_mask_head); + free_masks(current->aoa_angle_config.elevation_mask_head); + free(current); + current = head_config; + } +} + +/**************************************************************************//** + * Return a config from the config list by its ID. + *****************************************************************************/ +sl_status_t aoa_angle_get_config(aoa_id_t id, + aoa_angle_config_t **config) +{ + sl_status_t sc; + aoa_angle_config_node_t *node; + + sc = aoa_angle_find(id, &node); + if (sc == SL_STATUS_OK) { + *config = &node->aoa_angle_config; + } + + return sc; +} + +/**************************************************************************//** + * Finalize configuration settings. + *****************************************************************************/ +sl_status_t aoa_angle_finalize_config(aoa_id_t id) +{ + sl_status_t sc; + aoa_angle_config_node_t *node; + + sc = aoa_angle_find(id, &node); + if (sc == SL_STATUS_OK) { + sc = aoa_angle_finalize_node(node); + } + + return sc; +} + +/***************************************************************************//** + * Initialize angle calculation libraries + ******************************************************************************/ +enum sl_rtl_error_code aoa_init_rtl(aoa_state_t *aoa_state, + aoa_id_t config_id, + bool qa_enable) +{ + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config = NULL; + aoa_mask_node_t *current_azimuth; + aoa_mask_node_t *current_elevation; + uint32_t antenna_switch_pattern[ANTENNA_ARRAY_MAX_PATTERN_SIZE]; + uint32_t antenna_switch_pattern_size = sizeof(antenna_switch_pattern) / sizeof(uint32_t); + + sc = aoa_angle_get_config(config_id, &aoa_angle_config); + if (SL_STATUS_OK != sc) { + return SL_RTL_ERROR_ARGUMENT; + } + + sc = antenna_array_get_continuous_pattern(&aoa_angle_config->antenna_array, + antenna_switch_pattern, + &antenna_switch_pattern_size); + if (SL_STATUS_OK != sc) { + return SL_RTL_ERROR_ARGUMENT; + } + + current_azimuth = aoa_angle_config->azimuth_mask_head; + current_elevation = aoa_angle_config->elevation_mask_head; + + enum sl_rtl_error_code ec; + // Initialize AoX library + ec = sl_rtl_aox_init(&aoa_state->libitem); + CHECK_ERROR(ec); + // Set the number of snapshots, i.e. how many times the antennas are scanned + // during one measurement + ec = sl_rtl_aox_set_num_snapshots(&aoa_state->libitem, + aoa_angle_config->num_snapshots); + CHECK_ERROR(ec); + // Set the antenna array type + ec = sl_rtl_aox_set_array_type(&aoa_state->libitem, + aoa_angle_config->antenna_array.array_type); + CHECK_ERROR(ec); + // Select mode (high speed/high accuracy/etc.) + ec = sl_rtl_aox_set_mode(&aoa_state->libitem, + aoa_angle_config->aox_mode); + CHECK_ERROR(ec); + + aoa_state->qa_enable = qa_enable; + if (qa_enable) { + // Enable IQ sample quality analysis processing + ec = sl_rtl_aox_iq_sample_qa_configure(&aoa_state->libitem); + CHECK_ERROR(ec); + } + + // Add azimuth constraints + while (current_azimuth != NULL) { + ec = sl_rtl_aox_add_constraint(&aoa_state->libitem, + SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH, + current_azimuth->min, + current_azimuth->max); + CHECK_ERROR(ec); + current_azimuth = current_azimuth->next; + } + + // Add elevation constraints + while (current_elevation != NULL) { + ec = sl_rtl_aox_add_constraint(&aoa_state->libitem, + SL_RTL_AOX_CONSTRAINT_TYPE_ELEVATION, + current_elevation->min, + current_elevation->max); + CHECK_ERROR(ec); + current_elevation = current_elevation->next; + } + + // Create AoX estimator + ec = sl_rtl_aox_create_estimator(&aoa_state->libitem); + CHECK_ERROR(ec); + // Set the switching pattern mode + ec = sl_rtl_aox_set_switch_pattern_mode(&aoa_state->libitem, SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL); + CHECK_ERROR(ec); + if (antenna_array_type_is_dp(aoa_angle_config->antenna_array.array_type)) { + // Skip samples from the reference antenna. + ec = sl_rtl_aox_set_switch_pattern_mode(&aoa_state->libitem, SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTRA_REFERENCE); + CHECK_ERROR(ec); + } + // Set the switching pattern + ec = sl_rtl_aox_update_switch_pattern(&aoa_state->libitem, antenna_switch_pattern, NULL); + CHECK_ERROR(ec); + if (aoa_angle_config->angle_filtering == true) { + // Initialize an util item + ec = sl_rtl_util_init(&aoa_state->util_libitem); + CHECK_ERROR(ec); + ec = sl_rtl_util_set_parameter(&aoa_state->util_libitem, + SL_RTL_UTIL_PARAMETER_AMOUNT_OF_FILTERING, + aoa_angle_config->angle_filtering_weight); + CHECK_ERROR(ec); + } + // Initialize correction timeout counter + aoa_state->correction_timeout = 0; + + return ec; +} + +/***************************************************************************//** + * Estimate angle data from IQ samples + ******************************************************************************/ +enum sl_rtl_error_code aoa_calculate(aoa_state_t *aoa_state, + aoa_iq_report_t *iq_report, + aoa_angle_t *angle, + aoa_id_t config_id) +{ + enum sl_rtl_error_code ec; + float phase_rotation; + sl_status_t sc; + aoa_angle_config_node_t *node; + aoa_angle_config_t *aoa_angle_config; + uint32_t quality; + char quality_buffer[QUALITY_BUFFER_SIZE]; + char* quality_string; + + sc = aoa_angle_find(config_id, &node); + if (SL_STATUS_OK != sc) { + return SL_RTL_ERROR_ARGUMENT; + } + + aoa_angle_config = &node->aoa_angle_config; + + // Copy IQ samples into preallocated buffers. + get_samples(iq_report, node); + + // Calculate phase rotation from reference IQ samples. + ec = sl_rtl_aox_calculate_iq_sample_phase_rotation(&aoa_state->libitem, + 2.0f, + node->ref_i_samples, + node->ref_q_samples, + REFERENCE_PERIOD_SAMPLES, + &phase_rotation); + CHECK_ERROR(ec); + + // Provide calculated phase rotation to the estimator. + ec = sl_rtl_aox_set_iq_sample_phase_rotation(&aoa_state->libitem, + phase_rotation); + CHECK_ERROR(ec); + + // Estimate Angle of Arrival from IQ samples. + // sl_rtl_aox_process will return SL_RTL_ERROR_ESTIMATION_IN_PROGRESS + // until it has received enough packets for angle estimation. + ec = sl_rtl_aox_process(&aoa_state->libitem, + node->i_samples, + node->q_samples, + channel_to_frequency(iq_report->channel), + &angle->azimuth, + &angle->elevation); + CHECK_ERROR(ec); + + ec = sl_rtl_aox_get_latest_aoa_standard_deviation(&aoa_state->libitem, + &angle->azimuth_stdev, + &angle->elevation_stdev); + CHECK_ERROR(ec); + + // Calculate distance from RSSI. + ec = sl_rtl_util_rssi2distance(AOA_ANGLE_TAG_TX_POWER, + (float)iq_report->rssi, + &angle->distance); + CHECK_ERROR(ec); + + // Distance standard deviation is not supported, use 0. + angle->distance_stdev = 0; + + if (aoa_angle_config->angle_filtering == true) { + ec = sl_rtl_util_filter(&aoa_state->util_libitem, + angle->distance, + &angle->distance); + CHECK_ERROR(ec); + } + + // Copy sequence counter. + angle->sequence = iq_report->event_counter; + + if (aoa_state->qa_enable) { + // Fetch the quality result. + quality = sl_rtl_aox_iq_sample_qa_get_results(&aoa_state->libitem); + if (quality != 0) { + quality_string = sl_rtl_util_iq_sample_qa_code2string(quality_buffer, + sizeof(quality_buffer), + quality); + app_log_debug("%s [%d] quality: %s" APP_LOG_NL, + config_id, + angle->sequence, + quality_string); + } + } + + if (aoa_state->correction_timeout > 0) { + // Decrement timeout counter. + --aoa_state->correction_timeout; + if (aoa_state->correction_timeout == 0) { + // Timer expired, clear correction values. + ec = sl_rtl_aox_clear_expected_direction(&aoa_state->libitem); + } + } + return ec; +} + +/***************************************************************************//** + * Set correction data for the estimator + ******************************************************************************/ +enum sl_rtl_error_code aoa_set_correction(aoa_state_t *aoa_state, + aoa_angle_t *correction, + aoa_id_t config_id) +{ + enum sl_rtl_error_code ec; + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config = NULL; + + sc = aoa_angle_get_config(config_id, &aoa_angle_config); + if (SL_STATUS_OK != sc) { + return SL_RTL_ERROR_ARGUMENT; + } + + ec = sl_rtl_aox_set_expected_direction(&aoa_state->libitem, + correction->azimuth, + correction->elevation); + CHECK_ERROR(ec); + ec = sl_rtl_aox_set_expected_deviation(&aoa_state->libitem, + correction->azimuth_stdev, + correction->elevation_stdev); + CHECK_ERROR(ec); + + aoa_state->correction_timeout = aoa_angle_config->angle_correction_timeout; + return ec; +} + +/***************************************************************************//** + * Deinitialize angle calculation libraries + ******************************************************************************/ +enum sl_rtl_error_code aoa_deinit_rtl(aoa_state_t *aoa_state, + aoa_id_t config_id) +{ + enum sl_rtl_error_code ec; + sl_status_t sc; + aoa_angle_config_t *aoa_angle_config = NULL; + + sc = aoa_angle_get_config(config_id, &aoa_angle_config); + if (SL_STATUS_OK != sc) { + return SL_RTL_ERROR_ARGUMENT; + } + + ec = sl_rtl_aox_deinit(&aoa_state->libitem); + CHECK_ERROR(ec); + if (aoa_angle_config->angle_filtering == true) { + ec = sl_rtl_util_deinit(&aoa_state->util_libitem); + CHECK_ERROR(ec); + } + + return ec; +} + +// ----------------------------------------------------------------------------- +// Private function declarations + +static sl_status_t allocate_2D_float_buffer(float*** buf, size_t rows, size_t cols) +{ + *buf = malloc(sizeof(float*) * rows); + if (*buf == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + + for (size_t i = 0; i < rows; i++) { + (*buf)[i] = malloc(sizeof(float) * cols); + if ((*buf)[i] == NULL) { + return SL_STATUS_ALLOCATION_FAILED; + } + } + + return SL_STATUS_OK; +} + +static void free_2D_float_buffer(float** buf, size_t rows) +{ + for (size_t i = 0; i < rows; i++) { + free(buf[i]); + } + free(buf); +} + +static float channel_to_frequency(uint8_t channel) +{ + static const uint8_t logical_to_physical_channel[40] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 0, 12, 39 + }; + + // Return the center frequency of the given channel. + return 2402000000 + 2000000 * logical_to_physical_channel[channel]; +} + +static void get_samples(aoa_iq_report_t *iq_report, aoa_angle_config_node_t *node) +{ + size_t index = 0; + // Write reference IQ samples into the IQ sample buffer (sampled on one antenna) + for (size_t sample = 0; sample < REFERENCE_PERIOD_SAMPLES; ++sample) { + node->ref_i_samples[sample] = iq_report->samples[index++] / 127.0; + if (index == iq_report->length) { + break; + } + node->ref_q_samples[sample] = iq_report->samples[index++] / 127.0; + if (index == iq_report->length) { + break; + } + } + // The last reference sample is the first measurement sample too. + index = (REFERENCE_PERIOD_SAMPLES - 1) * 2; + // Write antenna IQ samples into the IQ sample buffer (sampled on all antennas) + for (size_t snapshot = 0; snapshot < node->sample_rows; ++snapshot) { + for (size_t antenna = 0; antenna < node->sample_cols; ++antenna) { + node->i_samples[snapshot][antenna] = iq_report->samples[index++] / 127.0; + if (index == iq_report->length) { + break; + } + node->q_samples[snapshot][antenna] = iq_report->samples[index++] / 127.0; + if (index == iq_report->length) { + break; + } + } + if (index == iq_report->length) { + break; + } + } +} + +/**************************************************************************//** + * Sets the default config. + *****************************************************************************/ +static sl_status_t aoa_angle_set_default_config(aoa_angle_config_t *aoa_angle_config) +{ + aoa_angle_config->aox_mode = AOA_ANGLE_AOX_MODE; + aoa_angle_config->angle_filtering = true; + aoa_angle_config->angle_filtering_weight = AOA_ANGLE_FILTERING_AMOUNT; + aoa_angle_config->angle_correction_timeout = AOA_ANGLE_CORRECTION_TIMEOUT; + aoa_angle_config->angle_correction_delay = AOA_ANGLE_MAX_CORRECTION_DELAY; + aoa_angle_config->cte_min_length = AOA_ANGLE_CTE_MIN_LENGTH; + aoa_angle_config->cte_slot_duration = AOA_ANGLE_CTE_SLOT_DURATION; + aoa_angle_config->azimuth_mask_head = NULL; + aoa_angle_config->elevation_mask_head = NULL; + return antenna_array_init(&aoa_angle_config->antenna_array, + AOA_ANGLE_ANTENNA_ARRAY_TYPE); +} + +static sl_status_t aoa_angle_finalize_node(aoa_angle_config_node_t *node) +{ + aoa_angle_config_t *cfg = &node->aoa_angle_config; + uint8_t antenna_switch_pattern_size; + sl_status_t sc; + + sc = antenna_array_get_pin_pattern(&cfg->antenna_array, + NULL, + &antenna_switch_pattern_size); + if (sc != SL_STATUS_OK) { + return sc; + } + + cfg->num_snapshots = (uint8_t)(((cfg->cte_min_length * 8) + - GUARD_PERIOD_US - REFERENCE_PERIOD_US) + / (cfg->cte_slot_duration * 2) + / antenna_switch_pattern_size); + + return allocate_sample_buffers(node); +} + +static sl_status_t allocate_sample_buffers(aoa_angle_config_node_t *node) +{ + sl_status_t sc; + aoa_angle_config_t *cfg = &node->aoa_angle_config; + uint8_t antenna_switch_pattern_size; + + sc = antenna_array_get_pin_pattern(&cfg->antenna_array, + NULL, + &antenna_switch_pattern_size); + if (sc != SL_STATUS_OK) { + return sc; + } + + // Reallocate sample buffers + if ((node->sample_rows != cfg->num_snapshots) + || (node->sample_cols != antenna_switch_pattern_size)) { + free_2D_float_buffer(node->i_samples, node->sample_rows); + free_2D_float_buffer(node->q_samples, node->sample_rows); + sc = allocate_2D_float_buffer(&node->i_samples, + cfg->num_snapshots, + antenna_switch_pattern_size); + if (SL_STATUS_OK != sc) { + return sc; + } + sc = allocate_2D_float_buffer(&node->q_samples, + cfg->num_snapshots, + antenna_switch_pattern_size); + if (SL_STATUS_OK != sc) { + return sc; + } + // Store new sample buffer dimensions + node->sample_rows = cfg->num_snapshots; + node->sample_cols = antenna_switch_pattern_size; + } + + return SL_STATUS_OK; +} + +static void free_sample_buffers(aoa_angle_config_node_t *node) +{ + free_2D_float_buffer(node->i_samples, node->sample_rows); + free_2D_float_buffer(node->q_samples, node->sample_rows); +} + +static sl_status_t aoa_angle_find(aoa_id_t id, aoa_angle_config_node_t **node) +{ + aoa_angle_config_node_t *current = head_config; + + while (NULL != current) { + if (aoa_id_compare(id, current->id) == 0) { + if (NULL != node) { + *node = current; + } + return SL_STATUS_OK; + } + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +static void free_masks(aoa_mask_node_t *mask_head) +{ + aoa_mask_node_t *current; + aoa_mask_node_t *next; + + for (current = mask_head; current != NULL; current = next) { + next = current->next; + free(current); + } +} diff --git a/locator_host/bt/aoa/aoa_angle/aoa_angle.h b/locator_host/bt/aoa/aoa_angle/aoa_angle.h index 524cac6..d84215e 100644 --- a/locator_host/bt/aoa/aoa_angle/aoa_angle.h +++ b/locator_host/bt/aoa/aoa_angle/aoa_angle.h @@ -1,220 +1,220 @@ -/***************************************************************************//** - * @file - * @brief Estimate angle data from IQ samples. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_ANGLE_H -#define AOA_ANGLE_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "aoa_types.h" -#include "sl_rtl_clib_api.h" -#include "sl_status.h" -#include "aoa_util.h" -#include "antenna_array.h" - -// Forward declaration -typedef struct aoa_mask_node_s aoa_mask_node_t; - -/// AoA angle estimation handler type, one instance for each asset tag. -typedef struct aoa_state_s { - sl_rtl_aox_libitem libitem; - sl_rtl_util_libitem util_libitem; - uint8_t correction_timeout; - bool qa_enable; -} aoa_state_t; - -/// Elevation or azimuth mask min/max values. -struct aoa_mask_node_s { - float min; - float max; - aoa_mask_node_t *next; -}; - -/// Locator specific configuration settings for AoA angle estimation. -typedef struct aoa_angle_config_s { - enum sl_rtl_aox_mode aox_mode; - bool angle_filtering; - float angle_filtering_weight; - uint16_t angle_correction_timeout; - uint16_t angle_correction_delay; - uint8_t num_snapshots; - uint16_t cte_min_length; - uint16_t cte_slot_duration; - aoa_mask_node_t *azimuth_mask_head; - aoa_mask_node_t *elevation_mask_head; - antenna_array_t antenna_array; -} aoa_angle_config_t; - -/**************************************************************************//** - * Add a config to the config list. - * - * @param[in] id id of the config - * @param[out] config created config entry - * - * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. - * @retval SL_STATUS_OK - Entry creation done. - *****************************************************************************/ -sl_status_t aoa_angle_add_config(aoa_id_t id, - aoa_angle_config_t **config); - -/**************************************************************************//** - * Add an azimuth mask to the list. - * - * @param[in] id id of the config - * @param[in] min min value - * @param[in] max max value - * - * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. - * @retval SL_STATUS_OK - Entry creation done. - *****************************************************************************/ -sl_status_t aoa_angle_add_azimuth_mask(aoa_id_t id, - float min, - float max); - -/**************************************************************************//** - * Add an elevation mask to the list. - * - * @param[in] id id of the config - * @param[in] min min value - * @param[in] max max value - * - * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. - * @retval SL_STATUS_OK - Entry creation done. - *****************************************************************************/ -sl_status_t aoa_angle_add_elevation_mask(aoa_id_t id, - float min, - float max); - -/**************************************************************************//** - * Reset the azimuth mask database. - * - * @param[in] id id of the config - * - * @retval SL_STATUS_NOT_FOUND - Config not found. - * @retval SL_STATUS_OK - Mask destroy done. - *****************************************************************************/ -sl_status_t aoa_angle_reset_azimuth_masks(aoa_id_t id); - -/**************************************************************************//** - * Reset the elevation mask database. - * - * @param[in] id id of the config - * - * @retval SL_STATUS_NOT_FOUND - Config not found. - * @retval SL_STATUS_OK - Mask destroy done. - *****************************************************************************/ -sl_status_t aoa_angle_reset_elevation_masks(aoa_id_t id); - -/**************************************************************************//** - * Reset the config database. - *****************************************************************************/ -void aoa_angle_reset_configs(void); - -/**************************************************************************//** - * Return a config from the config list by its ID. - * - * @param[in] id id of the config - * @param[out] config config entry - * - * @retval SL_STATUS_NOT_FOUND - Entry not found. - * @retval SL_STATUS_OK - Entry found. - *****************************************************************************/ -sl_status_t aoa_angle_get_config(aoa_id_t id, - aoa_angle_config_t **config); - -/**************************************************************************//** - * Finalize configuration settings. - * - * This function shall be called on each configuration change. - * - * @param[in] id id of the config - *****************************************************************************/ -sl_status_t aoa_angle_finalize_config(aoa_id_t id); - -/***************************************************************************//** - * Initialize angle calculation libraries. - * - * @param[in] aoa_state Angle calculation handler - * @param[in] config config entry id - * @param[in] qa_enable IQ sample quality analysis - * - * @return Status returned by the RTL library - ******************************************************************************/ -enum sl_rtl_error_code aoa_init_rtl(aoa_state_t *aoa_state, - aoa_id_t config_id, - bool qa_enable); - -/***************************************************************************//** - * Estimate angle data from IQ samples. - * - * @param[in] aoa_state Angle calculation handler - * @param[in] iq_report IQ report to convert - * @param[out] angle Estimated angle data - * - * @return Status returned by the RTL library - ******************************************************************************/ -enum sl_rtl_error_code aoa_calculate(aoa_state_t *aoa_state, - aoa_iq_report_t *iq_report, - aoa_angle_t *angle, - aoa_id_t config_id); - -/***************************************************************************//** - * Set correction data for the estimator - * - * @param[in] aoa_state Angle calculation handler - * @param[in] correction Correction data - * @param[in] config config entry id - * - * @return Status returned by the RTL library - ******************************************************************************/ -enum sl_rtl_error_code aoa_set_correction(aoa_state_t *aoa_state, - aoa_angle_t *correction, - aoa_id_t config_id); - -/***************************************************************************//** - * Deinitialize angle calculation libraries - * - * @param[in] aoa_state Angle calculation handler - * @param[in] config config entry id - * - * @return Status returned by the RTL library - ******************************************************************************/ -enum sl_rtl_error_code aoa_deinit_rtl(aoa_state_t *aoa_state, - aoa_id_t config_id); - -#ifdef __cplusplus -}; -#endif - -#endif // AOA_ANGLE_H +/***************************************************************************//** + * @file + * @brief Estimate angle data from IQ samples. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_ANGLE_H +#define AOA_ANGLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "aoa_types.h" +#include "sl_rtl_clib_api.h" +#include "sl_status.h" +#include "aoa_util.h" +#include "antenna_array.h" + +// Forward declaration +typedef struct aoa_mask_node_s aoa_mask_node_t; + +/// AoA angle estimation handler type, one instance for each asset tag. +typedef struct aoa_state_s { + sl_rtl_aox_libitem libitem; + sl_rtl_util_libitem util_libitem; + uint8_t correction_timeout; + bool qa_enable; +} aoa_state_t; + +/// Elevation or azimuth mask min/max values. +struct aoa_mask_node_s { + float min; + float max; + aoa_mask_node_t *next; +}; + +/// Locator specific configuration settings for AoA angle estimation. +typedef struct aoa_angle_config_s { + enum sl_rtl_aox_mode aox_mode; + bool angle_filtering; + float angle_filtering_weight; + uint16_t angle_correction_timeout; + uint16_t angle_correction_delay; + uint8_t num_snapshots; + uint16_t cte_min_length; + uint16_t cte_slot_duration; + aoa_mask_node_t *azimuth_mask_head; + aoa_mask_node_t *elevation_mask_head; + antenna_array_t antenna_array; +} aoa_angle_config_t; + +/**************************************************************************//** + * Add a config to the config list. + * + * @param[in] id id of the config + * @param[out] config created config entry + * + * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. + * @retval SL_STATUS_OK - Entry creation done. + *****************************************************************************/ +sl_status_t aoa_angle_add_config(aoa_id_t id, + aoa_angle_config_t **config); + +/**************************************************************************//** + * Add an azimuth mask to the list. + * + * @param[in] id id of the config + * @param[in] min min value + * @param[in] max max value + * + * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. + * @retval SL_STATUS_OK - Entry creation done. + *****************************************************************************/ +sl_status_t aoa_angle_add_azimuth_mask(aoa_id_t id, + float min, + float max); + +/**************************************************************************//** + * Add an elevation mask to the list. + * + * @param[in] id id of the config + * @param[in] min min value + * @param[in] max max value + * + * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation error. + * @retval SL_STATUS_OK - Entry creation done. + *****************************************************************************/ +sl_status_t aoa_angle_add_elevation_mask(aoa_id_t id, + float min, + float max); + +/**************************************************************************//** + * Reset the azimuth mask database. + * + * @param[in] id id of the config + * + * @retval SL_STATUS_NOT_FOUND - Config not found. + * @retval SL_STATUS_OK - Mask destroy done. + *****************************************************************************/ +sl_status_t aoa_angle_reset_azimuth_masks(aoa_id_t id); + +/**************************************************************************//** + * Reset the elevation mask database. + * + * @param[in] id id of the config + * + * @retval SL_STATUS_NOT_FOUND - Config not found. + * @retval SL_STATUS_OK - Mask destroy done. + *****************************************************************************/ +sl_status_t aoa_angle_reset_elevation_masks(aoa_id_t id); + +/**************************************************************************//** + * Reset the config database. + *****************************************************************************/ +void aoa_angle_reset_configs(void); + +/**************************************************************************//** + * Return a config from the config list by its ID. + * + * @param[in] id id of the config + * @param[out] config config entry + * + * @retval SL_STATUS_NOT_FOUND - Entry not found. + * @retval SL_STATUS_OK - Entry found. + *****************************************************************************/ +sl_status_t aoa_angle_get_config(aoa_id_t id, + aoa_angle_config_t **config); + +/**************************************************************************//** + * Finalize configuration settings. + * + * This function shall be called on each configuration change. + * + * @param[in] id id of the config + *****************************************************************************/ +sl_status_t aoa_angle_finalize_config(aoa_id_t id); + +/***************************************************************************//** + * Initialize angle calculation libraries. + * + * @param[in] aoa_state Angle calculation handler + * @param[in] config config entry id + * @param[in] qa_enable IQ sample quality analysis + * + * @return Status returned by the RTL library + ******************************************************************************/ +enum sl_rtl_error_code aoa_init_rtl(aoa_state_t *aoa_state, + aoa_id_t config_id, + bool qa_enable); + +/***************************************************************************//** + * Estimate angle data from IQ samples. + * + * @param[in] aoa_state Angle calculation handler + * @param[in] iq_report IQ report to convert + * @param[out] angle Estimated angle data + * + * @return Status returned by the RTL library + ******************************************************************************/ +enum sl_rtl_error_code aoa_calculate(aoa_state_t *aoa_state, + aoa_iq_report_t *iq_report, + aoa_angle_t *angle, + aoa_id_t config_id); + +/***************************************************************************//** + * Set correction data for the estimator + * + * @param[in] aoa_state Angle calculation handler + * @param[in] correction Correction data + * @param[in] config config entry id + * + * @return Status returned by the RTL library + ******************************************************************************/ +enum sl_rtl_error_code aoa_set_correction(aoa_state_t *aoa_state, + aoa_angle_t *correction, + aoa_id_t config_id); + +/***************************************************************************//** + * Deinitialize angle calculation libraries + * + * @param[in] aoa_state Angle calculation handler + * @param[in] config config entry id + * + * @return Status returned by the RTL library + ******************************************************************************/ +enum sl_rtl_error_code aoa_deinit_rtl(aoa_state_t *aoa_state, + aoa_id_t config_id); + +#ifdef __cplusplus +}; +#endif + +#endif // AOA_ANGLE_H diff --git a/locator_host/bt/aoa/aoa_angle/config/aoa_angle_config.h b/locator_host/bt/aoa/aoa_angle/config/aoa_angle_config.h index 761d853..b90ff61 100644 --- a/locator_host/bt/aoa/aoa_angle/config/aoa_angle_config.h +++ b/locator_host/bt/aoa/aoa_angle/config/aoa_angle_config.h @@ -1,63 +1,63 @@ -/***************************************************************************//** - * @file - * @brief Default configuration values for AoA angle estimation. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_ANGLE_CONFIG_H -#define AOA_ANGLE_CONFIG_H - -#include -#include "sl_rtl_clib_api.h" - -// AoA estimator mode -#define AOA_ANGLE_AOX_MODE SL_RTL_AOA_MODE_REAL_TIME_FAST_RESPONSE - -// Antenna array type -#define AOA_ANGLE_ANTENNA_ARRAY_TYPE SL_RTL_AOX_ARRAY_TYPE_4x4_URA - -// Reference RSSI value of the asset tag at 1.0 m distance in dBm. -#define AOA_ANGLE_TAG_TX_POWER (-45.0) - -// Filter weight applied on the estimated distance. Ranges from 0 to 1. -#define AOA_ANGLE_FILTERING_AMOUNT 0.6f - -// Direction correction will be cleared if this amount of IQ reports are received -// without receiving a correction message. -#define AOA_ANGLE_CORRECTION_TIMEOUT 5 - -// Correction values with a sequence number more than MAX_CORRECTION_DELAY apart -// from the last IQ report are considered outdated and will be ignored. -#define AOA_ANGLE_MAX_CORRECTION_DELAY 3 - -// Minimum CTE length requested in 8 us units. Ranges from 16 to 160 us. -#define AOA_ANGLE_CTE_MIN_LENGTH 20 - -// Switching and sampling slots in us (1 or 2). -#define AOA_ANGLE_CTE_SLOT_DURATION 1 - -#endif // AOA_ANGLE_CONFIG_H +/***************************************************************************//** + * @file + * @brief Default configuration values for AoA angle estimation. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_ANGLE_CONFIG_H +#define AOA_ANGLE_CONFIG_H + +#include +#include "sl_rtl_clib_api.h" + +// AoA estimator mode +#define AOA_ANGLE_AOX_MODE SL_RTL_AOA_MODE_REAL_TIME_FAST_RESPONSE + +// Antenna array type +#define AOA_ANGLE_ANTENNA_ARRAY_TYPE SL_RTL_AOX_ARRAY_TYPE_4x4_URA + +// Reference RSSI value of the asset tag at 1.0 m distance in dBm. +#define AOA_ANGLE_TAG_TX_POWER (-45.0) + +// Filter weight applied on the estimated distance. Ranges from 0 to 1. +#define AOA_ANGLE_FILTERING_AMOUNT 0.6f + +// Direction correction will be cleared if this amount of IQ reports are received +// without receiving a correction message. +#define AOA_ANGLE_CORRECTION_TIMEOUT 5 + +// Correction values with a sequence number more than MAX_CORRECTION_DELAY apart +// from the last IQ report are considered outdated and will be ignored. +#define AOA_ANGLE_MAX_CORRECTION_DELAY 3 + +// Minimum CTE length requested in 8 us units. Ranges from 16 to 160 us. +#define AOA_ANGLE_CTE_MIN_LENGTH 20 + +// Switching and sampling slots in us (1 or 2). +#define AOA_ANGLE_CTE_SLOT_DURATION 1 + +#endif // AOA_ANGLE_CONFIG_H diff --git a/locator_host/bt/aoa/aoa_cte/aoa_cte.c b/locator_host/bt/aoa/aoa_cte/aoa_cte.c index 99d5838..56d480a 100644 --- a/locator_host/bt/aoa/aoa_cte/aoa_cte.c +++ b/locator_host/bt/aoa/aoa_cte/aoa_cte.c @@ -1,120 +1,120 @@ -/***************************************************************************//** - * @file - * @brief CTE Handle module for AoA locator - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include "aoa_cte.h" -#include "sl_common.h" -#include "aoa_cte_config.h" - -// ----------------------------------------------------------------------------- -// Module variables. - -// Current CTE mode. -static aoa_cte_type_t cte_mode = AOA_CTE_DEFAULT_MODE; - -// Common switch pattern for all CTE modes. -uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; -uint8_t cte_switch_pattern_size; - -aoa_cte_config_t aoa_cte_config = { - AOA_CTE_SAMPLING_INTERVAL, - AOA_CTE_MIN_LENGTH, - AOA_CTE_COUNT, - AOA_CTE_SLOT_DURATION, - NULL -}; - -// ----------------------------------------------------------------------------- -// Public function definitions. - -/**************************************************************************//** - * Handles the bluetooth event. - *****************************************************************************/ -sl_status_t aoa_cte_bt_on_event(sl_bt_msg_t *evt) -{ - sl_status_t sc = SL_STATUS_OK; - - if (SL_BT_MSG_ID(evt->header) == sl_bt_evt_system_boot_id) { - // Get actual switch pattern at boot. - cte_switch_pattern_size = sizeof(cte_switch_pattern); - sc = antenna_array_get_pin_pattern(aoa_cte_config.antenna_array, - cte_switch_pattern, - &cte_switch_pattern_size); - if (sc != SL_STATUS_OK) { - return sc; - } - } - - switch (cte_mode) { - case AOA_CTE_TYPE_SILABS: - sc = cte_bt_on_event_silabs(evt); - break; - case AOA_CTE_TYPE_CONN_LESS: - sc = cte_bt_on_event_conn_less(evt); - break; - case AOA_CTE_TYPE_CONN: - sc = cte_bt_on_event_conn(evt); - break; - default: - break; - } - - return sc; -} - -/**************************************************************************//** - * Sets the CTE Mode. - *****************************************************************************/ -sl_status_t aoa_cte_set_mode(aoa_cte_type_t mode) -{ - if (mode >= AOA_CTE_TYPE_COUNT) { - return SL_STATUS_INVALID_PARAMETER; - } - cte_mode = mode; - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Returns the CTE Mode. - *****************************************************************************/ -aoa_cte_type_t aoa_cte_get_mode(void) -{ - return cte_mode; -} - -/**************************************************************************//** - * Callback to notify the application on new iq report. - *****************************************************************************/ -SL_WEAK void aoa_cte_on_iq_report(aoa_db_entry_t *tag, - aoa_iq_report_t *iq_report) -{ - // Implement in the application. -} +/***************************************************************************//** + * @file + * @brief CTE Handle module for AoA locator + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include "aoa_cte.h" +#include "sl_common.h" +#include "aoa_cte_config.h" + +// ----------------------------------------------------------------------------- +// Module variables. + +// Current CTE mode. +static aoa_cte_type_t cte_mode = AOA_CTE_DEFAULT_MODE; + +// Common switch pattern for all CTE modes. +uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; +uint8_t cte_switch_pattern_size; + +aoa_cte_config_t aoa_cte_config = { + AOA_CTE_SAMPLING_INTERVAL, + AOA_CTE_MIN_LENGTH, + AOA_CTE_COUNT, + AOA_CTE_SLOT_DURATION, + NULL +}; + +// ----------------------------------------------------------------------------- +// Public function definitions. + +/**************************************************************************//** + * Handles the bluetooth event. + *****************************************************************************/ +sl_status_t aoa_cte_bt_on_event(sl_bt_msg_t *evt) +{ + sl_status_t sc = SL_STATUS_OK; + + if (SL_BT_MSG_ID(evt->header) == sl_bt_evt_system_boot_id) { + // Get actual switch pattern at boot. + cte_switch_pattern_size = sizeof(cte_switch_pattern); + sc = antenna_array_get_pin_pattern(aoa_cte_config.antenna_array, + cte_switch_pattern, + &cte_switch_pattern_size); + if (sc != SL_STATUS_OK) { + return sc; + } + } + + switch (cte_mode) { + case AOA_CTE_TYPE_SILABS: + sc = cte_bt_on_event_silabs(evt); + break; + case AOA_CTE_TYPE_CONN_LESS: + sc = cte_bt_on_event_conn_less(evt); + break; + case AOA_CTE_TYPE_CONN: + sc = cte_bt_on_event_conn(evt); + break; + default: + break; + } + + return sc; +} + +/**************************************************************************//** + * Sets the CTE Mode. + *****************************************************************************/ +sl_status_t aoa_cte_set_mode(aoa_cte_type_t mode) +{ + if (mode >= AOA_CTE_TYPE_COUNT) { + return SL_STATUS_INVALID_PARAMETER; + } + cte_mode = mode; + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Returns the CTE Mode. + *****************************************************************************/ +aoa_cte_type_t aoa_cte_get_mode(void) +{ + return cte_mode; +} + +/**************************************************************************//** + * Callback to notify the application on new iq report. + *****************************************************************************/ +SL_WEAK void aoa_cte_on_iq_report(aoa_db_entry_t *tag, + aoa_iq_report_t *iq_report) +{ + // Implement in the application. +} diff --git a/locator_host/bt/aoa/aoa_cte/aoa_cte.h b/locator_host/bt/aoa/aoa_cte/aoa_cte.h index 8f741a9..dd4063d 100644 --- a/locator_host/bt/aoa/aoa_cte/aoa_cte.h +++ b/locator_host/bt/aoa/aoa_cte/aoa_cte.h @@ -1,137 +1,137 @@ -/***************************************************************************//** - * @file - * @brief CTE Handle module for AoA locator - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef AOA_CTE_H -#define AOA_CTE_H - -#include "aoa_db.h" -#include "aoa_types.h" -#include "antenna_array.h" -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Type definitions. - -/// Config structure. -typedef struct { - uint16_t cte_sampling_interval; - uint16_t cte_min_length; - uint16_t cte_count; - uint16_t cte_slot_duration; - antenna_array_t *antenna_array; -} aoa_cte_config_t; - -/// Enum for CTE type selection. -typedef enum { - AOA_CTE_TYPE_SILABS = 0, - AOA_CTE_TYPE_CONN, - AOA_CTE_TYPE_CONN_LESS, - AOA_CTE_TYPE_COUNT -} aoa_cte_type_t; - -// ----------------------------------------------------------------------------- -// Public variables. - -/// Configuration parameters -extern aoa_cte_config_t aoa_cte_config; - -// ----------------------------------------------------------------------------- -// Public function declarations - -/**************************************************************************//** - * Handles the bluetooth event. - * - * @param[in] evt Bluetooth event. - * - * @return Status of the operation. - *****************************************************************************/ -sl_status_t aoa_cte_bt_on_event(sl_bt_msg_t *evt); - -/**************************************************************************//** - * Sets the CTE Mode. - * - * @param[in] mode CTE mode. - * - * @retval SL_STATUS_OK - CTE mode is set. - * @retval SL_STATUS_INVALID_PARAMETER - Invalid CTE mode. - *****************************************************************************/ -sl_status_t aoa_cte_set_mode(aoa_cte_type_t mode); - -/**************************************************************************//** - * Returns the CTE Mode. - * - * @return The currently used CTE Mode. - *****************************************************************************/ -aoa_cte_type_t aoa_cte_get_mode(void); - -/**************************************************************************//** - * Bluetooth event handle for connectionless CTE. - * - * @param[in] evt Bluetooth event - * - * @return Status of the operation. - *****************************************************************************/ -sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt); - -/**************************************************************************//** - * Bluetooth event handle for connection CTE. - * - * @param[in] evt Bluetooth event - * - * @return Status of the operation. - *****************************************************************************/ -sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt); - -/**************************************************************************//** - * Bluetooth event handle for Silabs CTE. - * - * @param[in] evt Bluetooth event - * - * @return Status of the operation. - *****************************************************************************/ -sl_status_t cte_bt_on_event_silabs(sl_bt_msg_t *evt); - -/**************************************************************************//** - * Callback to notify the application on new iq report. - * - * @param[in] tag Pointer to the tag. - * @param[in] iq_report IQ report from the tag. - *****************************************************************************/ -void aoa_cte_on_iq_report(aoa_db_entry_t *tag, - aoa_iq_report_t *iq_report); - -#ifdef __cplusplus -}; -#endif - -#endif /* AOA_CTE_H */ +/***************************************************************************//** + * @file + * @brief CTE Handle module for AoA locator + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef AOA_CTE_H +#define AOA_CTE_H + +#include "aoa_db.h" +#include "aoa_types.h" +#include "antenna_array.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Type definitions. + +/// Config structure. +typedef struct { + uint16_t cte_sampling_interval; + uint16_t cte_min_length; + uint16_t cte_count; + uint16_t cte_slot_duration; + antenna_array_t *antenna_array; +} aoa_cte_config_t; + +/// Enum for CTE type selection. +typedef enum { + AOA_CTE_TYPE_SILABS = 0, + AOA_CTE_TYPE_CONN, + AOA_CTE_TYPE_CONN_LESS, + AOA_CTE_TYPE_COUNT +} aoa_cte_type_t; + +// ----------------------------------------------------------------------------- +// Public variables. + +/// Configuration parameters +extern aoa_cte_config_t aoa_cte_config; + +// ----------------------------------------------------------------------------- +// Public function declarations + +/**************************************************************************//** + * Handles the bluetooth event. + * + * @param[in] evt Bluetooth event. + * + * @return Status of the operation. + *****************************************************************************/ +sl_status_t aoa_cte_bt_on_event(sl_bt_msg_t *evt); + +/**************************************************************************//** + * Sets the CTE Mode. + * + * @param[in] mode CTE mode. + * + * @retval SL_STATUS_OK - CTE mode is set. + * @retval SL_STATUS_INVALID_PARAMETER - Invalid CTE mode. + *****************************************************************************/ +sl_status_t aoa_cte_set_mode(aoa_cte_type_t mode); + +/**************************************************************************//** + * Returns the CTE Mode. + * + * @return The currently used CTE Mode. + *****************************************************************************/ +aoa_cte_type_t aoa_cte_get_mode(void); + +/**************************************************************************//** + * Bluetooth event handle for connectionless CTE. + * + * @param[in] evt Bluetooth event + * + * @return Status of the operation. + *****************************************************************************/ +sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt); + +/**************************************************************************//** + * Bluetooth event handle for connection CTE. + * + * @param[in] evt Bluetooth event + * + * @return Status of the operation. + *****************************************************************************/ +sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt); + +/**************************************************************************//** + * Bluetooth event handle for Silabs CTE. + * + * @param[in] evt Bluetooth event + * + * @return Status of the operation. + *****************************************************************************/ +sl_status_t cte_bt_on_event_silabs(sl_bt_msg_t *evt); + +/**************************************************************************//** + * Callback to notify the application on new iq report. + * + * @param[in] tag Pointer to the tag. + * @param[in] iq_report IQ report from the tag. + *****************************************************************************/ +void aoa_cte_on_iq_report(aoa_db_entry_t *tag, + aoa_iq_report_t *iq_report); + +#ifdef __cplusplus +}; +#endif + +#endif /* AOA_CTE_H */ diff --git a/locator_host/bt/aoa/aoa_cte/config/aoa_cte_config.h b/locator_host/bt/aoa/aoa_cte/config/aoa_cte_config.h index 1d7aae6..b61684e 100644 --- a/locator_host/bt/aoa/aoa_cte/config/aoa_cte_config.h +++ b/locator_host/bt/aoa/aoa_cte/config/aoa_cte_config.h @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief CTE Handle module config for AoA locator - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_CTE_CONFIG_H -#define AOA_CTE_CONFIG_H - -// Default CTE Mode -#define AOA_CTE_DEFAULT_MODE AOA_CTE_TYPE_SILABS - -// Scanner timing values in units of 0.625 ms -#define AOA_CTE_SCAN_INTERVAL 160 -#define AOA_CTE_SCAN_WINDOW 160 - -// Scan mode -#define AOA_CTE_SCAN_MODE sl_bt_scanner_scan_mode_passive - -// Measurement interval expressed as the number of connection events. -#define AOA_CTE_SAMPLING_INTERVAL 3 - -// Minimum CTE length requested in 8 us units. Ranges from 16 to 160 us. -#define AOA_CTE_MIN_LENGTH 20 - -// Maximum number of sampled CTEs in each advertising interval. -// 0: Sample and report all available CTEs. -#define AOA_CTE_COUNT 0 - -// Switching and sampling slots in us (1 or 2). -#define AOA_CTE_SLOT_DURATION 1 - -#endif /* AOA_CTE_CONFIG_H */ +/***************************************************************************//** + * @file + * @brief CTE Handle module config for AoA locator + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_CTE_CONFIG_H +#define AOA_CTE_CONFIG_H + +// Default CTE Mode +#define AOA_CTE_DEFAULT_MODE AOA_CTE_TYPE_SILABS + +// Scanner timing values in units of 0.625 ms +#define AOA_CTE_SCAN_INTERVAL 160 +#define AOA_CTE_SCAN_WINDOW 160 + +// Scan mode +#define AOA_CTE_SCAN_MODE sl_bt_scanner_scan_mode_passive + +// Measurement interval expressed as the number of connection events. +#define AOA_CTE_SAMPLING_INTERVAL 3 + +// Minimum CTE length requested in 8 us units. Ranges from 16 to 160 us. +#define AOA_CTE_MIN_LENGTH 20 + +// Maximum number of sampled CTEs in each advertising interval. +// 0: Sample and report all available CTEs. +#define AOA_CTE_COUNT 0 + +// Switching and sampling slots in us (1 or 2). +#define AOA_CTE_SLOT_DURATION 1 + +#endif /* AOA_CTE_CONFIG_H */ diff --git a/locator_host/bt/aoa/aoa_cte/cte_conn.c b/locator_host/bt/aoa/aoa_cte/cte_conn.c index a032da5..26eb99c 100644 --- a/locator_host/bt/aoa/aoa_cte/cte_conn.c +++ b/locator_host/bt/aoa/aoa_cte/cte_conn.c @@ -1,347 +1,347 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth event handler for Connection CTE mode. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_bt_api.h" -#include "aoa_cte.h" -#include "aoa_util.h" -#include "aoa_cte_config.h" -#include "app_log.h" - -// Module shared variables. -extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; -extern uint8_t cte_switch_pattern_size; - -// connection parameters -#define CONN_INTERVAL_MIN 80 //100ms -#define CONN_INTERVAL_MAX 80 //100ms -#define CONN_RESPONDER_LATENCY 0 //no latency -#define CONN_TIMEOUT 100 //1000ms -#define CONN_MIN_CE_LENGTH 0 -#define CONN_MAX_CE_LENGTH 0xffff - -#define CTE_TYPE_AOA 0 - -// UUIDs defined by Bluetooth SIG -static const uint8_t cte_service[] = { 0x4A, 0x18 }; -static const uint8_t cte_enable_char[] = { 0xAD, 0x2B }; - -// Flag indicating that SL_BT_CONFIG_MAX_CONNECTIONS is reached. -static bool connections_unavailable = false; - -static sl_status_t cte_conn_process_advertisement_report(bd_addr *address, uint8_t address_type, uint8_t event_flags, const uint8array *adv_data); - -/**************************************************************************//** - * CTE specific Bluetooth event handler. - *****************************************************************************/ -sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) -{ - sl_status_t sc = SL_STATUS_OK; - aoa_db_entry_t *tag; - - switch (SL_BT_MSG_ID(evt->header)) { - // ------------------------------- - // This event indicates the device has started and the radio is ready. - // Do not call any stack command before receiving this boot event! - case sl_bt_evt_system_boot_id: - // Set scan mode, interval and scan window - sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, - AOA_CTE_SCAN_INTERVAL, - AOA_CTE_SCAN_WINDOW); - if (SL_STATUS_OK != sc) { - break; - } - - // Start scanning on 1M PHY - looking for tags - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - if (SL_STATUS_OK != sc) { - break; - } - - // Set the default connection parameters for subsequent connections - sc = sl_bt_connection_set_default_parameters(CONN_INTERVAL_MIN, - CONN_INTERVAL_MAX, - CONN_RESPONDER_LATENCY, - CONN_TIMEOUT, - CONN_MIN_CE_LENGTH, - CONN_MAX_CE_LENGTH); - break; - - // ------------------------------- - case sl_bt_evt_scanner_legacy_advertisement_report_id: - { - sc = cte_conn_process_advertisement_report(&(evt->data.evt_scanner_legacy_advertisement_report.address), - evt->data.evt_scanner_legacy_advertisement_report.address_type, - evt->data.evt_scanner_legacy_advertisement_report.event_flags, - &(evt->data.evt_scanner_legacy_advertisement_report.data)); - break; - } - - // ------------------------------- - case sl_bt_evt_scanner_extended_advertisement_report_id: - sc = cte_conn_process_advertisement_report(&(evt->data.evt_scanner_extended_advertisement_report.address), - evt->data.evt_scanner_extended_advertisement_report.address_type, - evt->data.evt_scanner_extended_advertisement_report.event_flags, - &(evt->data.evt_scanner_extended_advertisement_report.data)); - break; - - // ------------------------------- - case sl_bt_evt_connection_opened_id: - // Add connection to the asset tag database. - sc = aoa_db_add_tag((uint16_t)evt->data.evt_connection_opened.connection, - &evt->data.evt_connection_opened.address, - evt->data.evt_connection_opened.address_type, - &tag); - if (SL_STATUS_OK != sc) { - break; - } - // Discover CTE service on the responder device - sc = sl_bt_gatt_discover_primary_services_by_uuid(evt->data.evt_connection_opened.connection, - sizeof(cte_service), - cte_service); - break; - - // ------------------------------- - // This event is generated when a new service is discovered - case sl_bt_evt_gatt_service_id: - // Find connection - if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_service.connection, &tag) == SL_STATUS_NOT_FOUND) { - break; - } - // Save service handle for future reference - if (memcmp(evt->data.evt_gatt_service.uuid.data, - cte_service, - sizeof(cte_service)) == 0) { - tag->cte_service_handle = evt->data.evt_gatt_service.service; - } - break; - - // ------------------------------- - // This event is generated when a new characteristic is discovered - case sl_bt_evt_gatt_characteristic_id: - // Find connection - if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_characteristic.connection, &tag) == SL_STATUS_NOT_FOUND) { - break; - } - // Save characteristic handle for future reference - if (memcmp(evt->data.evt_gatt_characteristic.uuid.data, - cte_enable_char, - sizeof(cte_enable_char)) == 0) { - tag->cte_enable_char_handle = evt->data.evt_gatt_characteristic.characteristic; - } - tag->connection_state = DISCOVER_CHARACTERISTICS; - break; - - // ------------------------------- - // This event is generated for various procedure completions, e.g. when a - // write procedure is completed, or service discovery is completed - case sl_bt_evt_gatt_procedure_completed_id: - // Find connection - if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_procedure_completed.connection, &tag) == SL_STATUS_NOT_FOUND) { - break; - } - - switch (tag->connection_state) { - // If service discovery finished - case DISCOVER_SERVICES: - // Discover CTE enable characteristic on the responder device - sc = sl_bt_gatt_discover_characteristics_by_uuid(evt->data.evt_gatt_procedure_completed.connection, - tag->cte_service_handle, - sizeof(cte_enable_char), - cte_enable_char); - break; - - // If characteristic discovery finished - case DISCOVER_CHARACTERISTICS: - { - uint8_t data = 0x01; - // Enable CTE on responder device (by writing 0x01 into the CTE enable characteristic) - sc = sl_bt_gatt_write_characteristic_value(evt->data.evt_gatt_procedure_completed.connection, - tag->cte_enable_char_handle, - sizeof(data), - &data); - if (SL_STATUS_OK != sc) { - break; - } - tag->connection_state = ENABLE_CTE; - break; - } - - // If CTE was enabled - case ENABLE_CTE: - { - // Start listening CTE on advertising packets. - sc = sl_bt_cte_receiver_enable_connection_cte(evt->data.evt_gatt_procedure_completed.connection, - aoa_cte_config.cte_sampling_interval, - aoa_cte_config.cte_min_length, - CTE_TYPE_AOA, - aoa_cte_config.cte_slot_duration, - cte_switch_pattern_size, - cte_switch_pattern); - if (SL_STATUS_OK != sc) { - break; - } - tag->connection_state = RUNNING; - - if (connections_unavailable) { - // No connections available, don't restart scanning. - break; - } - - size_t allowed_tags = aoa_db_allowlist_get_size(); - size_t connected_tags = aoa_db_get_number_of_tags(); - if ((allowed_tags > 0) && (connected_tags == allowed_tags)) { - app_log_debug("All allowed asset tags found, stop scanning." APP_LOG_NL); - break; - } - - // Restart the scanner to discover new tags. - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - if (SL_STATUS_INVALID_STATE == sc) { - // Scanning is already running, continue execution. - sc = SL_STATUS_OK; - } - break; - } - - // Default case, nothing to do. - default: - break; - } - break; - - // ------------------------------- - // This event is generated when a connection is dropped - case sl_bt_evt_connection_closed_id: - connections_unavailable = false; - // Remove connection from active connections - aoa_db_remove_tag((uint16_t)evt->data.evt_connection_closed.connection); - - // Restart the scanner to discover new tags - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - - if (SL_STATUS_INVALID_STATE == sc) { - // Scanning is already running, continue execution. - sc = SL_STATUS_OK; - } - break; - - // ------------------------------- - case sl_bt_evt_cte_receiver_connection_iq_report_id: - { - aoa_iq_report_t iq_report; - - if (evt->data.evt_cte_receiver_connection_iq_report.samples.len == 0) { - // Nothing to be processed. - break; - } - - // Check if asset tag is known. - if (aoa_db_get_tag_by_handle(evt->data.evt_cte_receiver_connection_iq_report.connection, &tag) == SL_STATUS_NOT_FOUND) { - // Unknown tag, proceed with execution. - break; - } - - // Convert event to common IQ report format. - iq_report.channel = evt->data.evt_cte_receiver_connection_iq_report.channel; - iq_report.rssi = evt->data.evt_cte_receiver_connection_iq_report.rssi; - iq_report.event_counter = evt->data.evt_cte_receiver_connection_iq_report.event_counter; - iq_report.length = evt->data.evt_cte_receiver_connection_iq_report.samples.len; - iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_connection_iq_report.samples.data; - - aoa_cte_on_iq_report(tag, &iq_report); - } - break; - - // ------------------------------- - // Default event handler. - default: - break; - } - - return sc; -} - -/****************************************************************************** - * Check if the advertiser is a tag and initiate a connection if it is not - * connected. - *****************************************************************************/ -static sl_status_t cte_conn_process_advertisement_report(bd_addr *address, - uint8_t address_type, - uint8_t event_flags, - const uint8array *adv_data) -{ - sl_status_t sc = SL_STATUS_OK; - aoa_db_entry_t *tag; - - // Check if the tag is allowlisted. - if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(address->addr)) { - return sc; - } - - // Check if tag is already known. - // NOTE: - // It is possible that multiple scan report events arrive from the same - // asset tag before the connection opened event arrives and the asset tag - // is added to the database. Therefore, the asset tag is unknown at this - // point, and connection open command is sent multiple times in a row. - // This is normal and shouldn't cause any issues. - if (SL_STATUS_OK == aoa_db_get_tag_by_address(address, &tag)) { - return sc; - } - - // Check for connectable advertising type. - if ((event_flags & SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) != SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) { - return sc; - } - - // Check for CTE service. - if (!find_service_in_advertisement((uint8_t *)adv_data->data, - adv_data->len, - cte_service, - sizeof(cte_service))) { - return sc; - } - - // Establish connection with the advertising device. - uint8_t conn_handle; - sc = sl_bt_connection_open(*address, - address_type, - sl_bt_gap_phy_1m, - &conn_handle); - if (SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED == sc) { - app_log_warning("SL_BT_CONFIG_MAX_CONNECTIONS reached, stop scanning." APP_LOG_NL); - connections_unavailable = true; - sc = sl_bt_scanner_stop(); - } - return sc; -} +/***************************************************************************//** + * @file + * @brief Bluetooth event handler for Connection CTE mode. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_bt_api.h" +#include "aoa_cte.h" +#include "aoa_util.h" +#include "aoa_cte_config.h" +#include "app_log.h" + +// Module shared variables. +extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; +extern uint8_t cte_switch_pattern_size; + +// connection parameters +#define CONN_INTERVAL_MIN 80 //100ms +#define CONN_INTERVAL_MAX 80 //100ms +#define CONN_RESPONDER_LATENCY 0 //no latency +#define CONN_TIMEOUT 100 //1000ms +#define CONN_MIN_CE_LENGTH 0 +#define CONN_MAX_CE_LENGTH 0xffff + +#define CTE_TYPE_AOA 0 + +// UUIDs defined by Bluetooth SIG +static const uint8_t cte_service[] = { 0x4A, 0x18 }; +static const uint8_t cte_enable_char[] = { 0xAD, 0x2B }; + +// Flag indicating that SL_BT_CONFIG_MAX_CONNECTIONS is reached. +static bool connections_unavailable = false; + +static sl_status_t cte_conn_process_advertisement_report(bd_addr *address, uint8_t address_type, uint8_t event_flags, const uint8array *adv_data); + +/**************************************************************************//** + * CTE specific Bluetooth event handler. + *****************************************************************************/ +sl_status_t cte_bt_on_event_conn(sl_bt_msg_t *evt) +{ + sl_status_t sc = SL_STATUS_OK; + aoa_db_entry_t *tag; + + switch (SL_BT_MSG_ID(evt->header)) { + // ------------------------------- + // This event indicates the device has started and the radio is ready. + // Do not call any stack command before receiving this boot event! + case sl_bt_evt_system_boot_id: + // Set scan mode, interval and scan window + sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); + if (SL_STATUS_OK != sc) { + break; + } + + // Start scanning on 1M PHY - looking for tags + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + if (SL_STATUS_OK != sc) { + break; + } + + // Set the default connection parameters for subsequent connections + sc = sl_bt_connection_set_default_parameters(CONN_INTERVAL_MIN, + CONN_INTERVAL_MAX, + CONN_RESPONDER_LATENCY, + CONN_TIMEOUT, + CONN_MIN_CE_LENGTH, + CONN_MAX_CE_LENGTH); + break; + + // ------------------------------- + case sl_bt_evt_scanner_legacy_advertisement_report_id: + { + sc = cte_conn_process_advertisement_report(&(evt->data.evt_scanner_legacy_advertisement_report.address), + evt->data.evt_scanner_legacy_advertisement_report.address_type, + evt->data.evt_scanner_legacy_advertisement_report.event_flags, + &(evt->data.evt_scanner_legacy_advertisement_report.data)); + break; + } + + // ------------------------------- + case sl_bt_evt_scanner_extended_advertisement_report_id: + sc = cte_conn_process_advertisement_report(&(evt->data.evt_scanner_extended_advertisement_report.address), + evt->data.evt_scanner_extended_advertisement_report.address_type, + evt->data.evt_scanner_extended_advertisement_report.event_flags, + &(evt->data.evt_scanner_extended_advertisement_report.data)); + break; + + // ------------------------------- + case sl_bt_evt_connection_opened_id: + // Add connection to the asset tag database. + sc = aoa_db_add_tag((uint16_t)evt->data.evt_connection_opened.connection, + &evt->data.evt_connection_opened.address, + evt->data.evt_connection_opened.address_type, + &tag); + if (SL_STATUS_OK != sc) { + break; + } + // Discover CTE service on the responder device + sc = sl_bt_gatt_discover_primary_services_by_uuid(evt->data.evt_connection_opened.connection, + sizeof(cte_service), + cte_service); + break; + + // ------------------------------- + // This event is generated when a new service is discovered + case sl_bt_evt_gatt_service_id: + // Find connection + if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_service.connection, &tag) == SL_STATUS_NOT_FOUND) { + break; + } + // Save service handle for future reference + if (memcmp(evt->data.evt_gatt_service.uuid.data, + cte_service, + sizeof(cte_service)) == 0) { + tag->cte_service_handle = evt->data.evt_gatt_service.service; + } + break; + + // ------------------------------- + // This event is generated when a new characteristic is discovered + case sl_bt_evt_gatt_characteristic_id: + // Find connection + if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_characteristic.connection, &tag) == SL_STATUS_NOT_FOUND) { + break; + } + // Save characteristic handle for future reference + if (memcmp(evt->data.evt_gatt_characteristic.uuid.data, + cte_enable_char, + sizeof(cte_enable_char)) == 0) { + tag->cte_enable_char_handle = evt->data.evt_gatt_characteristic.characteristic; + } + tag->connection_state = DISCOVER_CHARACTERISTICS; + break; + + // ------------------------------- + // This event is generated for various procedure completions, e.g. when a + // write procedure is completed, or service discovery is completed + case sl_bt_evt_gatt_procedure_completed_id: + // Find connection + if (aoa_db_get_tag_by_handle(evt->data.evt_gatt_procedure_completed.connection, &tag) == SL_STATUS_NOT_FOUND) { + break; + } + + switch (tag->connection_state) { + // If service discovery finished + case DISCOVER_SERVICES: + // Discover CTE enable characteristic on the responder device + sc = sl_bt_gatt_discover_characteristics_by_uuid(evt->data.evt_gatt_procedure_completed.connection, + tag->cte_service_handle, + sizeof(cte_enable_char), + cte_enable_char); + break; + + // If characteristic discovery finished + case DISCOVER_CHARACTERISTICS: + { + uint8_t data = 0x01; + // Enable CTE on responder device (by writing 0x01 into the CTE enable characteristic) + sc = sl_bt_gatt_write_characteristic_value(evt->data.evt_gatt_procedure_completed.connection, + tag->cte_enable_char_handle, + sizeof(data), + &data); + if (SL_STATUS_OK != sc) { + break; + } + tag->connection_state = ENABLE_CTE; + break; + } + + // If CTE was enabled + case ENABLE_CTE: + { + // Start listening CTE on advertising packets. + sc = sl_bt_cte_receiver_enable_connection_cte(evt->data.evt_gatt_procedure_completed.connection, + aoa_cte_config.cte_sampling_interval, + aoa_cte_config.cte_min_length, + CTE_TYPE_AOA, + aoa_cte_config.cte_slot_duration, + cte_switch_pattern_size, + cte_switch_pattern); + if (SL_STATUS_OK != sc) { + break; + } + tag->connection_state = RUNNING; + + if (connections_unavailable) { + // No connections available, don't restart scanning. + break; + } + + size_t allowed_tags = aoa_db_allowlist_get_size(); + size_t connected_tags = aoa_db_get_number_of_tags(); + if ((allowed_tags > 0) && (connected_tags == allowed_tags)) { + app_log_debug("All allowed asset tags found, stop scanning." APP_LOG_NL); + break; + } + + // Restart the scanner to discover new tags. + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + if (SL_STATUS_INVALID_STATE == sc) { + // Scanning is already running, continue execution. + sc = SL_STATUS_OK; + } + break; + } + + // Default case, nothing to do. + default: + break; + } + break; + + // ------------------------------- + // This event is generated when a connection is dropped + case sl_bt_evt_connection_closed_id: + connections_unavailable = false; + // Remove connection from active connections + aoa_db_remove_tag((uint16_t)evt->data.evt_connection_closed.connection); + + // Restart the scanner to discover new tags + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + + if (SL_STATUS_INVALID_STATE == sc) { + // Scanning is already running, continue execution. + sc = SL_STATUS_OK; + } + break; + + // ------------------------------- + case sl_bt_evt_cte_receiver_connection_iq_report_id: + { + aoa_iq_report_t iq_report; + + if (evt->data.evt_cte_receiver_connection_iq_report.samples.len == 0) { + // Nothing to be processed. + break; + } + + // Check if asset tag is known. + if (aoa_db_get_tag_by_handle(evt->data.evt_cte_receiver_connection_iq_report.connection, &tag) == SL_STATUS_NOT_FOUND) { + // Unknown tag, proceed with execution. + break; + } + + // Convert event to common IQ report format. + iq_report.channel = evt->data.evt_cte_receiver_connection_iq_report.channel; + iq_report.rssi = evt->data.evt_cte_receiver_connection_iq_report.rssi; + iq_report.event_counter = evt->data.evt_cte_receiver_connection_iq_report.event_counter; + iq_report.length = evt->data.evt_cte_receiver_connection_iq_report.samples.len; + iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_connection_iq_report.samples.data; + + aoa_cte_on_iq_report(tag, &iq_report); + } + break; + + // ------------------------------- + // Default event handler. + default: + break; + } + + return sc; +} + +/****************************************************************************** + * Check if the advertiser is a tag and initiate a connection if it is not + * connected. + *****************************************************************************/ +static sl_status_t cte_conn_process_advertisement_report(bd_addr *address, + uint8_t address_type, + uint8_t event_flags, + const uint8array *adv_data) +{ + sl_status_t sc = SL_STATUS_OK; + aoa_db_entry_t *tag; + + // Check if the tag is allowlisted. + if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(address->addr)) { + return sc; + } + + // Check if tag is already known. + // NOTE: + // It is possible that multiple scan report events arrive from the same + // asset tag before the connection opened event arrives and the asset tag + // is added to the database. Therefore, the asset tag is unknown at this + // point, and connection open command is sent multiple times in a row. + // This is normal and shouldn't cause any issues. + if (SL_STATUS_OK == aoa_db_get_tag_by_address(address, &tag)) { + return sc; + } + + // Check for connectable advertising type. + if ((event_flags & SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) != SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE) { + return sc; + } + + // Check for CTE service. + if (!find_service_in_advertisement((uint8_t *)adv_data->data, + adv_data->len, + cte_service, + sizeof(cte_service))) { + return sc; + } + + // Establish connection with the advertising device. + uint8_t conn_handle; + sc = sl_bt_connection_open(*address, + address_type, + sl_bt_gap_phy_1m, + &conn_handle); + if (SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED == sc) { + app_log_warning("SL_BT_CONFIG_MAX_CONNECTIONS reached, stop scanning." APP_LOG_NL); + connections_unavailable = true; + sc = sl_bt_scanner_stop(); + } + return sc; +} diff --git a/locator_host/bt/aoa/aoa_cte/cte_conn_less.c b/locator_host/bt/aoa/aoa_cte/cte_conn_less.c index 72b5ebd..ff1bbc6 100644 --- a/locator_host/bt/aoa/aoa_cte/cte_conn_less.c +++ b/locator_host/bt/aoa/aoa_cte/cte_conn_less.c @@ -1,189 +1,189 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth event handler for Connectionless CTE mode. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_bt_api.h" -#include "aoa_cte.h" -#include "aoa_util.h" -#include "aoa_cte_config.h" -#include "app_log.h" - -// Module shared variables. -extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; -extern uint8_t cte_switch_pattern_size; - -// UUID defined by Bluetooth SIG -static const uint8_t cte_service[] = { 0x4A, 0x18 }; - -/**************************************************************************//** - * CTE specific Bluetooth event handler. - *****************************************************************************/ -sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt) -{ - sl_status_t sc = SL_STATUS_OK; - aoa_db_entry_t *tag; - - switch (SL_BT_MSG_ID(evt->header)) { - // ------------------------------- - // This event indicates the device has started and the radio is ready. - // Do not call any stack command before receiving this boot event! - case sl_bt_evt_system_boot_id: - // Set scan mode, interval and scan window - sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, - AOA_CTE_SCAN_INTERVAL, - AOA_CTE_SCAN_WINDOW); - if (SL_STATUS_OK != sc) { - break; - } - - // Start scanning on 1M PHY - looking for tags - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - break; - - // ------------------------------- - case sl_bt_evt_scanner_extended_advertisement_report_id: - { - // Check if the tag is allowlisted. - if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(evt->data.evt_scanner_extended_advertisement_report.address.addr)) { - break; - } - - // Check if tag is already known. - // NOTE: - // It is possible that multiple scan report events arrive from the same - // asset tag before the sync opened event arrives and the asset tag - // is added to the database. Therefore, the asset tag is unknown at this - // point, and sync open command is sent multiple times in a row. - // This is normal and shouldn't cause any issues. - if (SL_STATUS_OK == aoa_db_get_tag_by_address(&evt->data.evt_scanner_extended_advertisement_report.address, &tag)) { - break; - } - - // Check for CTE service. - if (!find_service_in_advertisement(evt->data.evt_scanner_extended_advertisement_report.data.data, - evt->data.evt_scanner_extended_advertisement_report.data.len, - cte_service, - sizeof(cte_service))) { - break; - } - - // Establish synchronization with the advertising device. - uint16_t sync_handle; - sc = sl_bt_sync_scanner_open(evt->data.evt_scanner_extended_advertisement_report.address, - evt->data.evt_scanner_extended_advertisement_report.address_type, - evt->data.evt_scanner_extended_advertisement_report.adv_sid, - &sync_handle); - if (SL_STATUS_NO_MORE_RESOURCE == sc) { - app_log_warning("SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC reached, stop scanning." APP_LOG_NL); - sc = sl_bt_scanner_stop(); - } - break; - } - - // ------------------------------- - case sl_bt_evt_periodic_sync_opened_id: - { - // Add connection to the asset tag database. - sc = aoa_db_add_tag(evt->data.evt_periodic_sync_opened.sync, - &evt->data.evt_periodic_sync_opened.address, - evt->data.evt_periodic_sync_opened.address_type, - &tag); - if (SL_STATUS_OK != sc) { - break; - } - - // Start listening CTE on advertising packets. - sc = sl_bt_cte_receiver_enable_connectionless_cte(evt->data.evt_periodic_sync_opened.sync, - aoa_cte_config.cte_slot_duration, - aoa_cte_config.cte_count, - cte_switch_pattern_size, - cte_switch_pattern); - if (SL_STATUS_OK != sc) { - break; - } - - size_t allowed_tags = aoa_db_allowlist_get_size(); - size_t connected_tags = aoa_db_get_number_of_tags(); - if ((allowed_tags > 0) && (connected_tags == allowed_tags)) { - app_log_debug("All allowed asset tags found, stop scanning." APP_LOG_NL); - sc = sl_bt_scanner_stop(); - } - break; - } - - // ------------------------------- - case sl_bt_evt_sync_closed_id: - aoa_db_remove_tag(evt->data.evt_cte_receiver_connectionless_iq_report.sync); - - // Restart the scanner to discover new tags - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - - if (SL_STATUS_INVALID_STATE == sc) { - // Scanning is already running, continue execution. - sc = SL_STATUS_OK; - } - break; - - // ------------------------------- - case sl_bt_evt_cte_receiver_connectionless_iq_report_id: - { - aoa_iq_report_t iq_report; - - if (evt->data.evt_cte_receiver_connectionless_iq_report.samples.len == 0) { - // Nothing to be processed. - break; - } - - // Check if asset tag is known. - if (aoa_db_get_tag_by_handle(evt->data.evt_cte_receiver_connectionless_iq_report.sync, &tag) == SL_STATUS_NOT_FOUND) { - // Unknown tag, proceed with execution. - break; - } - - // Convert event to common IQ report format. - iq_report.channel = evt->data.evt_cte_receiver_connectionless_iq_report.channel; - iq_report.rssi = evt->data.evt_cte_receiver_connectionless_iq_report.rssi; - iq_report.event_counter = evt->data.evt_cte_receiver_connectionless_iq_report.event_counter; - iq_report.length = evt->data.evt_cte_receiver_connectionless_iq_report.samples.len; - iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_connectionless_iq_report.samples.data; - - aoa_cte_on_iq_report(tag, &iq_report); - } - break; - - // ------------------------------- - // Default event handler. - default: - break; - } - - return sc; -} +/***************************************************************************//** + * @file + * @brief Bluetooth event handler for Connectionless CTE mode. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_bt_api.h" +#include "aoa_cte.h" +#include "aoa_util.h" +#include "aoa_cte_config.h" +#include "app_log.h" + +// Module shared variables. +extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; +extern uint8_t cte_switch_pattern_size; + +// UUID defined by Bluetooth SIG +static const uint8_t cte_service[] = { 0x4A, 0x18 }; + +/**************************************************************************//** + * CTE specific Bluetooth event handler. + *****************************************************************************/ +sl_status_t cte_bt_on_event_conn_less(sl_bt_msg_t *evt) +{ + sl_status_t sc = SL_STATUS_OK; + aoa_db_entry_t *tag; + + switch (SL_BT_MSG_ID(evt->header)) { + // ------------------------------- + // This event indicates the device has started and the radio is ready. + // Do not call any stack command before receiving this boot event! + case sl_bt_evt_system_boot_id: + // Set scan mode, interval and scan window + sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); + if (SL_STATUS_OK != sc) { + break; + } + + // Start scanning on 1M PHY - looking for tags + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + break; + + // ------------------------------- + case sl_bt_evt_scanner_extended_advertisement_report_id: + { + // Check if the tag is allowlisted. + if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(evt->data.evt_scanner_extended_advertisement_report.address.addr)) { + break; + } + + // Check if tag is already known. + // NOTE: + // It is possible that multiple scan report events arrive from the same + // asset tag before the sync opened event arrives and the asset tag + // is added to the database. Therefore, the asset tag is unknown at this + // point, and sync open command is sent multiple times in a row. + // This is normal and shouldn't cause any issues. + if (SL_STATUS_OK == aoa_db_get_tag_by_address(&evt->data.evt_scanner_extended_advertisement_report.address, &tag)) { + break; + } + + // Check for CTE service. + if (!find_service_in_advertisement(evt->data.evt_scanner_extended_advertisement_report.data.data, + evt->data.evt_scanner_extended_advertisement_report.data.len, + cte_service, + sizeof(cte_service))) { + break; + } + + // Establish synchronization with the advertising device. + uint16_t sync_handle; + sc = sl_bt_sync_scanner_open(evt->data.evt_scanner_extended_advertisement_report.address, + evt->data.evt_scanner_extended_advertisement_report.address_type, + evt->data.evt_scanner_extended_advertisement_report.adv_sid, + &sync_handle); + if (SL_STATUS_NO_MORE_RESOURCE == sc) { + app_log_warning("SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC reached, stop scanning." APP_LOG_NL); + sc = sl_bt_scanner_stop(); + } + break; + } + + // ------------------------------- + case sl_bt_evt_periodic_sync_opened_id: + { + // Add connection to the asset tag database. + sc = aoa_db_add_tag(evt->data.evt_periodic_sync_opened.sync, + &evt->data.evt_periodic_sync_opened.address, + evt->data.evt_periodic_sync_opened.address_type, + &tag); + if (SL_STATUS_OK != sc) { + break; + } + + // Start listening CTE on advertising packets. + sc = sl_bt_cte_receiver_enable_connectionless_cte(evt->data.evt_periodic_sync_opened.sync, + aoa_cte_config.cte_slot_duration, + aoa_cte_config.cte_count, + cte_switch_pattern_size, + cte_switch_pattern); + if (SL_STATUS_OK != sc) { + break; + } + + size_t allowed_tags = aoa_db_allowlist_get_size(); + size_t connected_tags = aoa_db_get_number_of_tags(); + if ((allowed_tags > 0) && (connected_tags == allowed_tags)) { + app_log_debug("All allowed asset tags found, stop scanning." APP_LOG_NL); + sc = sl_bt_scanner_stop(); + } + break; + } + + // ------------------------------- + case sl_bt_evt_sync_closed_id: + aoa_db_remove_tag(evt->data.evt_cte_receiver_connectionless_iq_report.sync); + + // Restart the scanner to discover new tags + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + + if (SL_STATUS_INVALID_STATE == sc) { + // Scanning is already running, continue execution. + sc = SL_STATUS_OK; + } + break; + + // ------------------------------- + case sl_bt_evt_cte_receiver_connectionless_iq_report_id: + { + aoa_iq_report_t iq_report; + + if (evt->data.evt_cte_receiver_connectionless_iq_report.samples.len == 0) { + // Nothing to be processed. + break; + } + + // Check if asset tag is known. + if (aoa_db_get_tag_by_handle(evt->data.evt_cte_receiver_connectionless_iq_report.sync, &tag) == SL_STATUS_NOT_FOUND) { + // Unknown tag, proceed with execution. + break; + } + + // Convert event to common IQ report format. + iq_report.channel = evt->data.evt_cte_receiver_connectionless_iq_report.channel; + iq_report.rssi = evt->data.evt_cte_receiver_connectionless_iq_report.rssi; + iq_report.event_counter = evt->data.evt_cte_receiver_connectionless_iq_report.event_counter; + iq_report.length = evt->data.evt_cte_receiver_connectionless_iq_report.samples.len; + iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_connectionless_iq_report.samples.data; + + aoa_cte_on_iq_report(tag, &iq_report); + } + break; + + // ------------------------------- + // Default event handler. + default: + break; + } + + return sc; +} diff --git a/locator_host/bt/aoa/aoa_cte/cte_silabs.c b/locator_host/bt/aoa/aoa_cte/cte_silabs.c index 96a4f00..f8f76db 100644 --- a/locator_host/bt/aoa/aoa_cte/cte_silabs.c +++ b/locator_host/bt/aoa/aoa_cte/cte_silabs.c @@ -1,134 +1,134 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth event handler for Silabs CTE mode. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_bt_api.h" -#include "sl_ncp_evt_filter_common.h" -#include "aoa_cte.h" -#include "aoa_cte_config.h" - -// Module shared variables. -extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; -extern uint8_t cte_switch_pattern_size; - -/**************************************************************************//** - * CTE specific Bluetooth event handler. - *****************************************************************************/ -sl_status_t cte_bt_on_event_silabs(sl_bt_msg_t *evt) -{ - sl_status_t sc = SL_STATUS_OK; - uint8_t user_data[SL_NCP_EVT_FILTER_CMD_ADD_LEN]; - uint32_t event; - aoa_db_entry_t *tag = NULL; - aoa_iq_report_t iq_report; - - switch (SL_BT_MSG_ID(evt->header)) { - // ------------------------------- - // This event indicates the device has started and the radio is ready. - // Do not call any stack command before receiving this boot event! - case sl_bt_evt_system_boot_id: - // Config the NCP on the target. - // Filter out the scan response event - user_data[0] = SL_NCP_EVT_FILTER_CMD_ADD_ID; - event = sl_bt_evt_scanner_extended_advertisement_report_id; - memcpy(&user_data[1], &event, SL_NCP_EVT_FILTER_CMD_ADD_LEN - 1); - - sc = sl_bt_user_manage_event_filter(SL_NCP_EVT_FILTER_CMD_ADD_LEN, - user_data); - if (SL_STATUS_OK != sc) { - break; - } - - // Set scan mode, interval and scan window - sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, - AOA_CTE_SCAN_INTERVAL, - AOA_CTE_SCAN_WINDOW); - if (SL_STATUS_OK != sc) { - break; - } - - // Start scanning on 1M PHY - looking for tags - sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, - sl_bt_scanner_discover_generic); - if (SL_STATUS_OK != sc) { - break; - } - - // Start Silabs CTE - sc = sl_bt_cte_receiver_enable_silabs_cte(aoa_cte_config.cte_slot_duration, - aoa_cte_config.cte_count, - cte_switch_pattern_size, - cte_switch_pattern); - break; - - // ------------------------------- - case sl_bt_evt_cte_receiver_silabs_iq_report_id: - { - if (evt->data.evt_cte_receiver_silabs_iq_report.samples.len == 0) { - // Nothing to be processed. - break; - } - - // Check if the tag is allowlisted. - if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(evt->data.evt_cte_receiver_silabs_iq_report.address.addr)) { - // Tag is not on the allowlist, ignoring. Not an error. - break; - } - - // Look for this tag. - sc = aoa_db_get_tag_by_address(&evt->data.evt_cte_receiver_silabs_iq_report.address, &tag); - // Check if it is a new tag - if (sc == SL_STATUS_NOT_FOUND) { - sc = aoa_db_add_tag(0, - &evt->data.evt_cte_receiver_silabs_iq_report.address, - evt->data.evt_cte_receiver_silabs_iq_report.address_type, - &tag); - if (SL_STATUS_OK != sc) { - break; - } - } - - // Convert event to common IQ report format. - iq_report.channel = evt->data.evt_cte_receiver_silabs_iq_report.channel; - iq_report.rssi = evt->data.evt_cte_receiver_silabs_iq_report.rssi; - iq_report.event_counter = evt->data.evt_cte_receiver_silabs_iq_report.packet_counter; - iq_report.length = evt->data.evt_cte_receiver_silabs_iq_report.samples.len; - iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_silabs_iq_report.samples.data; - - aoa_cte_on_iq_report(tag, &iq_report); - } - break; - - // ------------------------------- - // Default event handler. - default: - break; - } - - return sc; -} +/***************************************************************************//** + * @file + * @brief Bluetooth event handler for Silabs CTE mode. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_bt_api.h" +#include "sl_ncp_evt_filter_common.h" +#include "aoa_cte.h" +#include "aoa_cte_config.h" + +// Module shared variables. +extern uint8_t cte_switch_pattern[ANTENNA_ARRAY_MAX_PIN_PATTERN_SIZE]; +extern uint8_t cte_switch_pattern_size; + +/**************************************************************************//** + * CTE specific Bluetooth event handler. + *****************************************************************************/ +sl_status_t cte_bt_on_event_silabs(sl_bt_msg_t *evt) +{ + sl_status_t sc = SL_STATUS_OK; + uint8_t user_data[SL_NCP_EVT_FILTER_CMD_ADD_LEN]; + uint32_t event; + aoa_db_entry_t *tag = NULL; + aoa_iq_report_t iq_report; + + switch (SL_BT_MSG_ID(evt->header)) { + // ------------------------------- + // This event indicates the device has started and the radio is ready. + // Do not call any stack command before receiving this boot event! + case sl_bt_evt_system_boot_id: + // Config the NCP on the target. + // Filter out the scan response event + user_data[0] = SL_NCP_EVT_FILTER_CMD_ADD_ID; + event = sl_bt_evt_scanner_extended_advertisement_report_id; + memcpy(&user_data[1], &event, SL_NCP_EVT_FILTER_CMD_ADD_LEN - 1); + + sc = sl_bt_user_manage_event_filter(SL_NCP_EVT_FILTER_CMD_ADD_LEN, + user_data); + if (SL_STATUS_OK != sc) { + break; + } + + // Set scan mode, interval and scan window + sc = sl_bt_scanner_set_parameters(AOA_CTE_SCAN_MODE, + AOA_CTE_SCAN_INTERVAL, + AOA_CTE_SCAN_WINDOW); + if (SL_STATUS_OK != sc) { + break; + } + + // Start scanning on 1M PHY - looking for tags + sc = sl_bt_scanner_start(sl_bt_scanner_scan_phy_1m, + sl_bt_scanner_discover_generic); + if (SL_STATUS_OK != sc) { + break; + } + + // Start Silabs CTE + sc = sl_bt_cte_receiver_enable_silabs_cte(aoa_cte_config.cte_slot_duration, + aoa_cte_config.cte_count, + cte_switch_pattern_size, + cte_switch_pattern); + break; + + // ------------------------------- + case sl_bt_evt_cte_receiver_silabs_iq_report_id: + { + if (evt->data.evt_cte_receiver_silabs_iq_report.samples.len == 0) { + // Nothing to be processed. + break; + } + + // Check if the tag is allowlisted. + if (SL_STATUS_NOT_FOUND == aoa_db_allowlist_find(evt->data.evt_cte_receiver_silabs_iq_report.address.addr)) { + // Tag is not on the allowlist, ignoring. Not an error. + break; + } + + // Look for this tag. + sc = aoa_db_get_tag_by_address(&evt->data.evt_cte_receiver_silabs_iq_report.address, &tag); + // Check if it is a new tag + if (sc == SL_STATUS_NOT_FOUND) { + sc = aoa_db_add_tag(0, + &evt->data.evt_cte_receiver_silabs_iq_report.address, + evt->data.evt_cte_receiver_silabs_iq_report.address_type, + &tag); + if (SL_STATUS_OK != sc) { + break; + } + } + + // Convert event to common IQ report format. + iq_report.channel = evt->data.evt_cte_receiver_silabs_iq_report.channel; + iq_report.rssi = evt->data.evt_cte_receiver_silabs_iq_report.rssi; + iq_report.event_counter = evt->data.evt_cte_receiver_silabs_iq_report.packet_counter; + iq_report.length = evt->data.evt_cte_receiver_silabs_iq_report.samples.len; + iq_report.samples = (int8_t *)evt->data.evt_cte_receiver_silabs_iq_report.samples.data; + + aoa_cte_on_iq_report(tag, &iq_report); + } + break; + + // ------------------------------- + // Default event handler. + default: + break; + } + + return sc; +} diff --git a/locator_host/bt/aoa/aoa_db/aoa_db.c b/locator_host/bt/aoa/aoa_db/aoa_db.c index 9005ede..92ddaab 100644 --- a/locator_host/bt/aoa/aoa_db/aoa_db.c +++ b/locator_host/bt/aoa/aoa_db/aoa_db.c @@ -1,349 +1,349 @@ -/***************************************************************************//** - * @file - * @brief Tag database handler module, responsible for storing states of tags. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include -#include "aoa_db.h" -#include "sl_common.h" - -// ----------------------------------------------------------------------------- -// Type definitions. - -// Forward declarations -typedef struct aoa_db_node aoa_db_node_t; -typedef struct aoa_db_allow_node aoa_db_allow_node_t; - -struct aoa_db_node{ - aoa_db_entry_t entry; - aoa_db_node_t *next; -}; - -struct aoa_db_allow_node{ - uint8_t address[ADR_LEN]; - aoa_db_allow_node_t *next; -}; - -// ----------------------------------------------------------------------------- -// Module variables. - -// Linked list heads -static aoa_db_node_t *head_conn = NULL; -static aoa_db_allow_node_t *head_allow = NULL; - -// ----------------------------------------------------------------------------- -// Public function definitions. - -/**************************************************************************//** - * Add a tag to the database list. - *****************************************************************************/ -sl_status_t aoa_db_add_tag(uint16_t handle, - bd_addr *address, - uint8_t address_type, - aoa_db_entry_t **tag) -{ - aoa_db_node_t *new = (aoa_db_node_t *)malloc(sizeof(aoa_db_node_t)); - if (NULL == new) { - return SL_STATUS_ALLOCATION_FAILED; - } - - // Store the connection handle, and the server address - new->entry.handle = handle; - new->entry.address = *address; - new->entry.address_type = address_type; - new->entry.connection_state = DISCOVER_SERVICES; - new->entry.sequence = -1; - new->next = head_conn; - head_conn = new; - *tag = &(new->entry); - - aoa_db_on_tag_added(*tag); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Removes a tag from the database list. - *****************************************************************************/ -sl_status_t aoa_db_remove_tag(uint16_t handle) -{ - aoa_db_node_t *current = head_conn; - aoa_db_node_t *previous = NULL; - - if (head_conn == NULL) { - return SL_STATUS_EMPTY; - } - - while (NULL != current) { - if (current->entry.handle == handle) { - if (previous != NULL) { - previous->next = current->next; - } else { - head_conn = current->next; - } - aoa_db_on_tag_removed(¤t->entry); - free(current); - return SL_STATUS_OK; - } - previous = current; - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Returns a tag from the tag list by its handle. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_handle(uint16_t handle, - aoa_db_entry_t **tag) -{ - aoa_db_node_t *current = head_conn; - - if (NULL == head_conn) { - return SL_STATUS_NOT_FOUND; - } - - while (NULL != current) { - if (current->entry.handle == handle) { - *tag = &(current->entry); - return SL_STATUS_OK; - } - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Returns a tag from the tag list by its index. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_index(uint32_t index, - aoa_db_entry_t **tag) -{ - aoa_db_node_t *current = head_conn; - uint32_t i = 0; - - if (NULL == head_conn) { - return SL_STATUS_NOT_FOUND; - } - - while (NULL != current) { - if (index == i) { - *tag = &(current->entry); - return SL_STATUS_OK; - } - current = current->next; - i++; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Returns a tag from the tag list by its address. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_address(bd_addr *address, - aoa_db_entry_t **entry) -{ - aoa_db_node_t *current = head_conn; - - if (NULL == head_conn) { - return SL_STATUS_NOT_FOUND; - } - - while (NULL != current) { - if (0 == memcmp(address, &(current->entry.address), sizeof(bd_addr))) { - *entry = &(current->entry); - return SL_STATUS_OK; - } - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Returns the number of tags on the list. - *****************************************************************************/ -size_t aoa_db_get_number_of_tags(void) -{ - size_t i = 0; - aoa_db_node_t *current = head_conn; - - while (NULL != current) { - i++; - current = current->next; - } - - return i; -} - -/**************************************************************************//** - * Adds an address to the allowlist. - *****************************************************************************/ -sl_status_t aoa_db_allowlist_add(uint8_t address[ADR_LEN]) -{ - aoa_db_allow_node_t *new = NULL; - - if (SL_STATUS_OK == aoa_db_allowlist_find(address)) { - return SL_STATUS_ALREADY_EXISTS; - } else { - new = (aoa_db_allow_node_t *)malloc(sizeof(aoa_db_allow_node_t)); - if (NULL == new) { - return SL_STATUS_ALLOCATION_FAILED; - } - for (uint32_t i = 0; i < ADR_LEN; i++) { - new->address[i] = address[i]; - } - } - new->next = head_allow; - head_allow = new; - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Removes all tags from the allowlist. - *****************************************************************************/ -void aoa_db_allowlist_reset(void) -{ - aoa_db_allow_node_t *current; - aoa_db_allow_node_t *next; - - for (current = head_allow; current != NULL; current = next) { - next = current->next; - free(current); - } - - head_allow = NULL; -} - -/**************************************************************************//** - * Removes an address from the allowlist. - *****************************************************************************/ -sl_status_t aoa_db_allowlist_remove(uint8_t address[ADR_LEN]) -{ - aoa_db_allow_node_t *current = head_allow; - aoa_db_allow_node_t *previous = NULL; - - if (head_allow == NULL) { - return SL_STATUS_EMPTY; - } - - if (0 == memcmp(head_allow->address, address, ADR_LEN)) { - head_allow = head_allow->next; - free(current); - return SL_STATUS_OK; - } - - while (NULL != current) { - if (memcmp(current->address, address, ADR_LEN) == 0) { - previous->next = current->next; - free(current); - return SL_STATUS_OK; - } - previous = current; - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Finds an address on the allowlist - *****************************************************************************/ -sl_status_t aoa_db_allowlist_find(uint8_t address[ADR_LEN]) -{ - aoa_db_allow_node_t *current = head_allow; - - if (NULL == head_allow) { - // Allowlist is empty, every tag is allowed - return SL_STATUS_EMPTY; - } - - while (NULL != current) { - if (0 == memcmp(address, current->address, ADR_LEN)) { - return SL_STATUS_OK; - } - current = current->next; - } - - return SL_STATUS_NOT_FOUND; -} - -/**************************************************************************//** - * Returns the number of tags on the allow list. - *****************************************************************************/ -size_t aoa_db_allowlist_get_size(void) -{ - size_t i = 0; - aoa_db_allow_node_t *current = head_allow; - - while (NULL != current) { - i++; - current = current->next; - } - - return i; -} - -/**************************************************************************//** - * Deletes every tags. - *****************************************************************************/ -void aoa_db_remove_all(void) -{ - aoa_db_node_t *current; - aoa_db_node_t *next; - - for (current = head_conn; current != NULL; current = next) { - next = current->next; - aoa_db_on_tag_removed(¤t->entry); - free(current); - } - - head_conn = NULL; -} - -/**************************************************************************//** - * Weak implementation of tag added callback. - *****************************************************************************/ -SL_WEAK void aoa_db_on_tag_added(aoa_db_entry_t *tag) -{ - // Implement this in the application. -} - -/**************************************************************************//** - * Weak implementation of tag removed callback. - *****************************************************************************/ -SL_WEAK void aoa_db_on_tag_removed(aoa_db_entry_t *tag) -{ - // Implement this in the application. -} +/***************************************************************************//** + * @file + * @brief Tag database handler module, responsible for storing states of tags. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include "aoa_db.h" +#include "sl_common.h" + +// ----------------------------------------------------------------------------- +// Type definitions. + +// Forward declarations +typedef struct aoa_db_node aoa_db_node_t; +typedef struct aoa_db_allow_node aoa_db_allow_node_t; + +struct aoa_db_node{ + aoa_db_entry_t entry; + aoa_db_node_t *next; +}; + +struct aoa_db_allow_node{ + uint8_t address[ADR_LEN]; + aoa_db_allow_node_t *next; +}; + +// ----------------------------------------------------------------------------- +// Module variables. + +// Linked list heads +static aoa_db_node_t *head_conn = NULL; +static aoa_db_allow_node_t *head_allow = NULL; + +// ----------------------------------------------------------------------------- +// Public function definitions. + +/**************************************************************************//** + * Add a tag to the database list. + *****************************************************************************/ +sl_status_t aoa_db_add_tag(uint16_t handle, + bd_addr *address, + uint8_t address_type, + aoa_db_entry_t **tag) +{ + aoa_db_node_t *new = (aoa_db_node_t *)malloc(sizeof(aoa_db_node_t)); + if (NULL == new) { + return SL_STATUS_ALLOCATION_FAILED; + } + + // Store the connection handle, and the server address + new->entry.handle = handle; + new->entry.address = *address; + new->entry.address_type = address_type; + new->entry.connection_state = DISCOVER_SERVICES; + new->entry.sequence = -1; + new->next = head_conn; + head_conn = new; + *tag = &(new->entry); + + aoa_db_on_tag_added(*tag); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Removes a tag from the database list. + *****************************************************************************/ +sl_status_t aoa_db_remove_tag(uint16_t handle) +{ + aoa_db_node_t *current = head_conn; + aoa_db_node_t *previous = NULL; + + if (head_conn == NULL) { + return SL_STATUS_EMPTY; + } + + while (NULL != current) { + if (current->entry.handle == handle) { + if (previous != NULL) { + previous->next = current->next; + } else { + head_conn = current->next; + } + aoa_db_on_tag_removed(¤t->entry); + free(current); + return SL_STATUS_OK; + } + previous = current; + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Returns a tag from the tag list by its handle. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_handle(uint16_t handle, + aoa_db_entry_t **tag) +{ + aoa_db_node_t *current = head_conn; + + if (NULL == head_conn) { + return SL_STATUS_NOT_FOUND; + } + + while (NULL != current) { + if (current->entry.handle == handle) { + *tag = &(current->entry); + return SL_STATUS_OK; + } + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Returns a tag from the tag list by its index. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_index(uint32_t index, + aoa_db_entry_t **tag) +{ + aoa_db_node_t *current = head_conn; + uint32_t i = 0; + + if (NULL == head_conn) { + return SL_STATUS_NOT_FOUND; + } + + while (NULL != current) { + if (index == i) { + *tag = &(current->entry); + return SL_STATUS_OK; + } + current = current->next; + i++; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Returns a tag from the tag list by its address. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_address(bd_addr *address, + aoa_db_entry_t **entry) +{ + aoa_db_node_t *current = head_conn; + + if (NULL == head_conn) { + return SL_STATUS_NOT_FOUND; + } + + while (NULL != current) { + if (0 == memcmp(address, &(current->entry.address), sizeof(bd_addr))) { + *entry = &(current->entry); + return SL_STATUS_OK; + } + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Returns the number of tags on the list. + *****************************************************************************/ +size_t aoa_db_get_number_of_tags(void) +{ + size_t i = 0; + aoa_db_node_t *current = head_conn; + + while (NULL != current) { + i++; + current = current->next; + } + + return i; +} + +/**************************************************************************//** + * Adds an address to the allowlist. + *****************************************************************************/ +sl_status_t aoa_db_allowlist_add(uint8_t address[ADR_LEN]) +{ + aoa_db_allow_node_t *new = NULL; + + if (SL_STATUS_OK == aoa_db_allowlist_find(address)) { + return SL_STATUS_ALREADY_EXISTS; + } else { + new = (aoa_db_allow_node_t *)malloc(sizeof(aoa_db_allow_node_t)); + if (NULL == new) { + return SL_STATUS_ALLOCATION_FAILED; + } + for (uint32_t i = 0; i < ADR_LEN; i++) { + new->address[i] = address[i]; + } + } + new->next = head_allow; + head_allow = new; + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Removes all tags from the allowlist. + *****************************************************************************/ +void aoa_db_allowlist_reset(void) +{ + aoa_db_allow_node_t *current; + aoa_db_allow_node_t *next; + + for (current = head_allow; current != NULL; current = next) { + next = current->next; + free(current); + } + + head_allow = NULL; +} + +/**************************************************************************//** + * Removes an address from the allowlist. + *****************************************************************************/ +sl_status_t aoa_db_allowlist_remove(uint8_t address[ADR_LEN]) +{ + aoa_db_allow_node_t *current = head_allow; + aoa_db_allow_node_t *previous = NULL; + + if (head_allow == NULL) { + return SL_STATUS_EMPTY; + } + + if (0 == memcmp(head_allow->address, address, ADR_LEN)) { + head_allow = head_allow->next; + free(current); + return SL_STATUS_OK; + } + + while (NULL != current) { + if (memcmp(current->address, address, ADR_LEN) == 0) { + previous->next = current->next; + free(current); + return SL_STATUS_OK; + } + previous = current; + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Finds an address on the allowlist + *****************************************************************************/ +sl_status_t aoa_db_allowlist_find(uint8_t address[ADR_LEN]) +{ + aoa_db_allow_node_t *current = head_allow; + + if (NULL == head_allow) { + // Allowlist is empty, every tag is allowed + return SL_STATUS_EMPTY; + } + + while (NULL != current) { + if (0 == memcmp(address, current->address, ADR_LEN)) { + return SL_STATUS_OK; + } + current = current->next; + } + + return SL_STATUS_NOT_FOUND; +} + +/**************************************************************************//** + * Returns the number of tags on the allow list. + *****************************************************************************/ +size_t aoa_db_allowlist_get_size(void) +{ + size_t i = 0; + aoa_db_allow_node_t *current = head_allow; + + while (NULL != current) { + i++; + current = current->next; + } + + return i; +} + +/**************************************************************************//** + * Deletes every tags. + *****************************************************************************/ +void aoa_db_remove_all(void) +{ + aoa_db_node_t *current; + aoa_db_node_t *next; + + for (current = head_conn; current != NULL; current = next) { + next = current->next; + aoa_db_on_tag_removed(¤t->entry); + free(current); + } + + head_conn = NULL; +} + +/**************************************************************************//** + * Weak implementation of tag added callback. + *****************************************************************************/ +SL_WEAK void aoa_db_on_tag_added(aoa_db_entry_t *tag) +{ + // Implement this in the application. +} + +/**************************************************************************//** + * Weak implementation of tag removed callback. + *****************************************************************************/ +SL_WEAK void aoa_db_on_tag_removed(aoa_db_entry_t *tag) +{ + // Implement this in the application. +} diff --git a/locator_host/bt/aoa/aoa_db/aoa_db.h b/locator_host/bt/aoa/aoa_db/aoa_db.h index f4e1dea..726d75a 100644 --- a/locator_host/bt/aoa/aoa_db/aoa_db.h +++ b/locator_host/bt/aoa/aoa_db/aoa_db.h @@ -1,213 +1,213 @@ -/***************************************************************************//** - * @file - * @brief Tag database handler header file - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_DB_H -#define AOA_DB_H - -#include -#include "sl_bt_api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -// Bluetooth address length -#define ADR_LEN 6 - -// ----------------------------------------------------------------------------- -// Type definitions. - -/// Connection state, used only in connection oriented mode -typedef enum { - DISCOVER_SERVICES, - DISCOVER_CHARACTERISTICS, - ENABLE_CTE, - RUNNING -} aoa_db_state_t; - -typedef struct { - uint16_t handle; // Connection handle or sync handle in connectionless mode - bd_addr address; - uint8_t address_type; - uint32_t cte_service_handle; // Connection only - uint16_t cte_enable_char_handle; // Connection only - aoa_db_state_t connection_state; // Connection only - int32_t sequence; // RTL lib only - void *user_data; -} aoa_db_entry_t; - -// ----------------------------------------------------------------------------- -// Function Declarations - -/**************************************************************************//** - * Add a tag to the database list. - * - * @param[in] handle Connection or sync handle. - * @param[in] address Bluetooth address in reverse byte order. - * @param[in] address_type Address type. - * @param[out] tag Pointer to the created tag properties structure. - * - * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation failure. - * @retval SL_STATUS_OK - Tag added. - *****************************************************************************/ -sl_status_t aoa_db_add_tag(uint16_t handle, - bd_addr *address, - uint8_t address_type, - aoa_db_entry_t** tag); - -/**************************************************************************//** - * Removes a tag from the database list. - * - * @param[in] handle Connection or sync handle. - * - * @retval SL_STATUS_EMPTY - No tag in the list. - * @retval SL_STATUS_OK - Tag removed. - * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. - *****************************************************************************/ -sl_status_t aoa_db_remove_tag(uint16_t handle); - -/**************************************************************************//** - * Returns a tag from the tag list by its handle. - * - * @param[in] handle Connection or sync handle. - * @param[out] tag Pointer to tag structure. - * - * @retval SL_STATUS_OK - Tag found. - * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_handle(uint16_t handle, - aoa_db_entry_t **tag); - -/**************************************************************************//** - * Returns a tag from the tag list by its handle. - * - * @param[in] index index of the tag. - * @param[out] tag Pointer to tag structure. - * - * @retval SL_STATUS_OK - Tag found. - * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_index(uint32_t index, - aoa_db_entry_t **tag); - -/**************************************************************************//** - * Returns a tag from the tag list by its address. - * - * @param[in] address Bluetooth address in reverse byte order. - * @param[out] tag Pointer to tag structure. - * - * @retval SL_STATUS_EMPTY - No tag in the list. - * @retval SL_STATUS_OK - Tag found. - * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. - *****************************************************************************/ -sl_status_t aoa_db_get_tag_by_address(bd_addr* address, - aoa_db_entry_t **tag); - -/**************************************************************************//** - * Returns the number of tags on the list. - * - * @return Number of tags in the list. - *****************************************************************************/ -size_t aoa_db_get_number_of_tags(void); - -/**************************************************************************//** - * Adds an address to the allowlist. - * - * @param[in] address Address to be added to the allowlist. - * - * @retval SL_STATUS_ALREADY_EXISTS - Address already on the list. - * @retval SL_STATUS_ALLOCATION_FAILED - Allocation error. - * @retval SL_STATUS_OK - Address added to the allowlist. - *****************************************************************************/ -sl_status_t aoa_db_allowlist_add(uint8_t address[ADR_LEN]); - -/**************************************************************************//** - * Removes all tags from the allowlist. - *****************************************************************************/ -void aoa_db_allowlist_reset(void); - -/**************************************************************************//** - * Removes an address from the allowlist. - * - * @param[in] address Address to be removed from the allowlist. - * - * @retval SL_STATUS_EMPTY - Allowlist is empty. - * @retval SL_STATUS_NOT_FOUND - Address is not on the allowlist. - * @retval SL_STATUS_OK - Address removed from the allowlist. - *****************************************************************************/ -sl_status_t aoa_db_allowlist_remove(uint8_t address[ADR_LEN]); - -/**************************************************************************//** - * Finds an address on the allowlist. - * - * @param[in] address Address to be found in the allowlist. - * - * @retval SL_STATUS_NOT_FOUND - Address is not on the allowlist. - * @retval SL_STATUS_EMPTY - Allowlist is empty. - * @retval SL_STATUS_OK - Address is on the allowlist. - *****************************************************************************/ -sl_status_t aoa_db_allowlist_find(uint8_t address[ADR_LEN]); - -/**************************************************************************//** - * Returns the number of tags on the allow list. - * - * @retval Number of tags on the allowlist. - *****************************************************************************/ -size_t aoa_db_allowlist_get_size(void); - -/**************************************************************************//** - * Deletes every tags. - *****************************************************************************/ -void aoa_db_remove_all(void); - -/**************************************************************************//** - * Tag added callback. - * @note To be implemented in user code. - * - * @param[in] tag Pointer to tag. - *****************************************************************************/ -void aoa_db_on_tag_added(aoa_db_entry_t *tag); - -/**************************************************************************//** - * Tag removed callback. - * @note To be implemented in user code. - * - * @param[in] tag Pointer to tag. - *****************************************************************************/ -void aoa_db_on_tag_removed(aoa_db_entry_t *tag); - -#ifdef __cplusplus -}; -#endif - -#endif /* AOA_DB_H */ +/***************************************************************************//** + * @file + * @brief Tag database handler header file + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_DB_H +#define AOA_DB_H + +#include +#include "sl_bt_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +// Bluetooth address length +#define ADR_LEN 6 + +// ----------------------------------------------------------------------------- +// Type definitions. + +/// Connection state, used only in connection oriented mode +typedef enum { + DISCOVER_SERVICES, + DISCOVER_CHARACTERISTICS, + ENABLE_CTE, + RUNNING +} aoa_db_state_t; + +typedef struct { + uint16_t handle; // Connection handle or sync handle in connectionless mode + bd_addr address; + uint8_t address_type; + uint32_t cte_service_handle; // Connection only + uint16_t cte_enable_char_handle; // Connection only + aoa_db_state_t connection_state; // Connection only + int32_t sequence; // RTL lib only + void *user_data; +} aoa_db_entry_t; + +// ----------------------------------------------------------------------------- +// Function Declarations + +/**************************************************************************//** + * Add a tag to the database list. + * + * @param[in] handle Connection or sync handle. + * @param[in] address Bluetooth address in reverse byte order. + * @param[in] address_type Address type. + * @param[out] tag Pointer to the created tag properties structure. + * + * @retval SL_STATUS_ALLOCATION_FAILED - Memory allocation failure. + * @retval SL_STATUS_OK - Tag added. + *****************************************************************************/ +sl_status_t aoa_db_add_tag(uint16_t handle, + bd_addr *address, + uint8_t address_type, + aoa_db_entry_t** tag); + +/**************************************************************************//** + * Removes a tag from the database list. + * + * @param[in] handle Connection or sync handle. + * + * @retval SL_STATUS_EMPTY - No tag in the list. + * @retval SL_STATUS_OK - Tag removed. + * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. + *****************************************************************************/ +sl_status_t aoa_db_remove_tag(uint16_t handle); + +/**************************************************************************//** + * Returns a tag from the tag list by its handle. + * + * @param[in] handle Connection or sync handle. + * @param[out] tag Pointer to tag structure. + * + * @retval SL_STATUS_OK - Tag found. + * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_handle(uint16_t handle, + aoa_db_entry_t **tag); + +/**************************************************************************//** + * Returns a tag from the tag list by its handle. + * + * @param[in] index index of the tag. + * @param[out] tag Pointer to tag structure. + * + * @retval SL_STATUS_OK - Tag found. + * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_index(uint32_t index, + aoa_db_entry_t **tag); + +/**************************************************************************//** + * Returns a tag from the tag list by its address. + * + * @param[in] address Bluetooth address in reverse byte order. + * @param[out] tag Pointer to tag structure. + * + * @retval SL_STATUS_EMPTY - No tag in the list. + * @retval SL_STATUS_OK - Tag found. + * @retval SL_STATUS_NOT_FOUND - Tag is not on the list. + *****************************************************************************/ +sl_status_t aoa_db_get_tag_by_address(bd_addr* address, + aoa_db_entry_t **tag); + +/**************************************************************************//** + * Returns the number of tags on the list. + * + * @return Number of tags in the list. + *****************************************************************************/ +size_t aoa_db_get_number_of_tags(void); + +/**************************************************************************//** + * Adds an address to the allowlist. + * + * @param[in] address Address to be added to the allowlist. + * + * @retval SL_STATUS_ALREADY_EXISTS - Address already on the list. + * @retval SL_STATUS_ALLOCATION_FAILED - Allocation error. + * @retval SL_STATUS_OK - Address added to the allowlist. + *****************************************************************************/ +sl_status_t aoa_db_allowlist_add(uint8_t address[ADR_LEN]); + +/**************************************************************************//** + * Removes all tags from the allowlist. + *****************************************************************************/ +void aoa_db_allowlist_reset(void); + +/**************************************************************************//** + * Removes an address from the allowlist. + * + * @param[in] address Address to be removed from the allowlist. + * + * @retval SL_STATUS_EMPTY - Allowlist is empty. + * @retval SL_STATUS_NOT_FOUND - Address is not on the allowlist. + * @retval SL_STATUS_OK - Address removed from the allowlist. + *****************************************************************************/ +sl_status_t aoa_db_allowlist_remove(uint8_t address[ADR_LEN]); + +/**************************************************************************//** + * Finds an address on the allowlist. + * + * @param[in] address Address to be found in the allowlist. + * + * @retval SL_STATUS_NOT_FOUND - Address is not on the allowlist. + * @retval SL_STATUS_EMPTY - Allowlist is empty. + * @retval SL_STATUS_OK - Address is on the allowlist. + *****************************************************************************/ +sl_status_t aoa_db_allowlist_find(uint8_t address[ADR_LEN]); + +/**************************************************************************//** + * Returns the number of tags on the allow list. + * + * @retval Number of tags on the allowlist. + *****************************************************************************/ +size_t aoa_db_allowlist_get_size(void); + +/**************************************************************************//** + * Deletes every tags. + *****************************************************************************/ +void aoa_db_remove_all(void); + +/**************************************************************************//** + * Tag added callback. + * @note To be implemented in user code. + * + * @param[in] tag Pointer to tag. + *****************************************************************************/ +void aoa_db_on_tag_added(aoa_db_entry_t *tag); + +/**************************************************************************//** + * Tag removed callback. + * @note To be implemented in user code. + * + * @param[in] tag Pointer to tag. + *****************************************************************************/ +void aoa_db_on_tag_removed(aoa_db_entry_t *tag); + +#ifdef __cplusplus +}; +#endif + +#endif /* AOA_DB_H */ diff --git a/locator_host/bt/aoa/aoa_util/aoa_serdes.c b/locator_host/bt/aoa/aoa_util/aoa_serdes.c index 6e9f0d1..a761dd1 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_serdes.c +++ b/locator_host/bt/aoa/aoa_util/aoa_serdes.c @@ -1,242 +1,242 @@ -/***************************************************************************//** - * @file - * @brief AoA serializer and deserializer functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "cJSON.h" -#include "aoa_serdes.h" - -// Helper macro. -#define CHECK_TYPE(x, t) if (((x) == NULL) || ((x)->type != (t))) return SL_STATUS_FAIL - -/// Check pointer to NULL, return error code -#define CHECK_NULL_RETURN(p, sc) \ - do { \ - if ((p) == NULL) { \ - return (sc); \ - } \ - } while (0) - -/***************************************************************************//** - * Serialize IQ report data structure into string. - ******************************************************************************/ -sl_status_t aoa_serialize_iq_report(aoa_iq_report_t *iq_report, char **str) -{ - if ((iq_report == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON_bool b; - cJSON *obj = NULL; - cJSON *root = cJSON_CreateObject(); - CHECK_NULL_RETURN(root, SL_STATUS_FAIL); - cJSON *samples = cJSON_CreateArray(); - CHECK_NULL_RETURN(samples, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "channel", (int)iq_report->channel); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "rssi", (int)iq_report->rssi); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "sequence", (int)iq_report->event_counter); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - for (int i = 0; i < iq_report->length; i++) { - b = cJSON_AddItemToArray(samples, cJSON_CreateNumber(iq_report->samples[i])); - if (!b) { - return SL_STATUS_FAIL; - } - } - b = cJSON_AddItemToObject(root, "samples", samples); - if (!b) { - return SL_STATUS_FAIL; - } - *str = cJSON_Print(root); - cJSON_Delete(root); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Deserialize IQ report data structure from string. - ******************************************************************************/ -sl_status_t aoa_deserialize_iq_report(char *str, aoa_iq_report_t *iq_report) -{ - if ((iq_report == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON *root = cJSON_Parse(str); - CHECK_TYPE(root, cJSON_Object); - cJSON *samples = cJSON_GetObjectItem(root, "samples"); - CHECK_TYPE(samples, cJSON_Array); - cJSON *param = NULL; - uint8_t length = 0; - param = cJSON_GetObjectItem(root, "channel"); - CHECK_TYPE(param, cJSON_Number); - iq_report->channel = (uint8_t)param->valueint; - param = cJSON_GetObjectItem(root, "rssi"); - CHECK_TYPE(param, cJSON_Number); - iq_report->rssi = (int8_t)param->valueint; - param = cJSON_GetObjectItem(root, "sequence"); - CHECK_TYPE(param, cJSON_Number); - iq_report->event_counter = (uint16_t)param->valueint; - cJSON_ArrayForEach(param, samples) { - CHECK_TYPE(param, cJSON_Number); - iq_report->samples[length] = (int8_t)param->valueint; - ++length; - } - iq_report->length = length; - cJSON_Delete(root); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Serialize angle data structure into string. - ******************************************************************************/ -sl_status_t aoa_serialize_angle(aoa_angle_t *angle, char **str) -{ - if ((angle == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON *obj = NULL; - cJSON *root = cJSON_CreateObject(); - CHECK_NULL_RETURN(root, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "azimuth", (double)angle->azimuth); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "azimuth_stdev", (double)angle->azimuth_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "elevation", (double)angle->elevation); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "elevation_stdev", (double)angle->elevation_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "distance", (double)angle->distance); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "distance_stdev", (double)angle->distance_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "sequence", (int)angle->sequence); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - *str = cJSON_Print(root); - cJSON_Delete(root); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Deserialize angle data structure from string. - ******************************************************************************/ -sl_status_t aoa_deserialize_angle(char *str, aoa_angle_t *angle) -{ - if ((angle == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON *root = cJSON_Parse(str); - CHECK_TYPE(root, cJSON_Object); - cJSON *param = cJSON_GetObjectItem(root, "azimuth"); - CHECK_TYPE(param, cJSON_Number); - angle->azimuth = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "azimuth_stdev"); - CHECK_TYPE(param, cJSON_Number); - angle->azimuth_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "elevation"); - CHECK_TYPE(param, cJSON_Number); - angle->elevation = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "elevation_stdev"); - CHECK_TYPE(param, cJSON_Number); - angle->elevation_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "distance"); - CHECK_TYPE(param, cJSON_Number); - angle->distance = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "distance_stdev"); - CHECK_TYPE(param, cJSON_Number); - angle->distance_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "sequence"); - CHECK_TYPE(param, cJSON_Number); - angle->sequence = (int32_t)param->valueint; - cJSON_Delete(root); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Serialize position data structure into string. - ******************************************************************************/ -sl_status_t aoa_serialize_position(aoa_position_t *position, char **str) -{ - if ((position == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON *obj = NULL; - cJSON *root = cJSON_CreateObject(); - CHECK_NULL_RETURN(root, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "x", position->x); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "x_stdev", position->x_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "y", position->y); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "y_stdev", position->y_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "z", position->z); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "z_stdev", position->z_stdev); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - obj = cJSON_AddNumberToObject(root, "sequence", (int)position->sequence); - CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); - *str = cJSON_Print(root); - cJSON_Delete(root); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Deserialize position data structure from string. - ******************************************************************************/ -sl_status_t aoa_deserialize_position(char *str, aoa_position_t *position) -{ - if ((position == NULL) || (str == NULL)) { - return SL_STATUS_NULL_POINTER; - } - cJSON *root = cJSON_Parse(str); - CHECK_TYPE(root, cJSON_Object); - cJSON *param = cJSON_GetObjectItem(root, "x"); - CHECK_TYPE(param, cJSON_Number); - position->x = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "x_stdev"); - CHECK_TYPE(param, cJSON_Number); - position->x_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "y"); - CHECK_TYPE(param, cJSON_Number); - position->y = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "y_stdev"); - CHECK_TYPE(param, cJSON_Number); - position->y_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "z"); - CHECK_TYPE(param, cJSON_Number); - position->z = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "z_stdev"); - CHECK_TYPE(param, cJSON_Number); - position->z_stdev = (float)param->valuedouble; - param = cJSON_GetObjectItem(root, "sequence"); - CHECK_TYPE(param, cJSON_Number); - position->sequence = (int32_t)param->valueint; - cJSON_Delete(root); - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief AoA serializer and deserializer functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "cJSON.h" +#include "aoa_serdes.h" + +// Helper macro. +#define CHECK_TYPE(x, t) if (((x) == NULL) || ((x)->type != (t))) return SL_STATUS_FAIL + +/// Check pointer to NULL, return error code +#define CHECK_NULL_RETURN(p, sc) \ + do { \ + if ((p) == NULL) { \ + return (sc); \ + } \ + } while (0) + +/***************************************************************************//** + * Serialize IQ report data structure into string. + ******************************************************************************/ +sl_status_t aoa_serialize_iq_report(aoa_iq_report_t *iq_report, char **str) +{ + if ((iq_report == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON_bool b; + cJSON *obj = NULL; + cJSON *root = cJSON_CreateObject(); + CHECK_NULL_RETURN(root, SL_STATUS_FAIL); + cJSON *samples = cJSON_CreateArray(); + CHECK_NULL_RETURN(samples, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "channel", (int)iq_report->channel); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "rssi", (int)iq_report->rssi); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "sequence", (int)iq_report->event_counter); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + for (int i = 0; i < iq_report->length; i++) { + b = cJSON_AddItemToArray(samples, cJSON_CreateNumber(iq_report->samples[i])); + if (!b) { + return SL_STATUS_FAIL; + } + } + b = cJSON_AddItemToObject(root, "samples", samples); + if (!b) { + return SL_STATUS_FAIL; + } + *str = cJSON_Print(root); + cJSON_Delete(root); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deserialize IQ report data structure from string. + ******************************************************************************/ +sl_status_t aoa_deserialize_iq_report(char *str, aoa_iq_report_t *iq_report) +{ + if ((iq_report == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON *root = cJSON_Parse(str); + CHECK_TYPE(root, cJSON_Object); + cJSON *samples = cJSON_GetObjectItem(root, "samples"); + CHECK_TYPE(samples, cJSON_Array); + cJSON *param = NULL; + uint8_t length = 0; + param = cJSON_GetObjectItem(root, "channel"); + CHECK_TYPE(param, cJSON_Number); + iq_report->channel = (uint8_t)param->valueint; + param = cJSON_GetObjectItem(root, "rssi"); + CHECK_TYPE(param, cJSON_Number); + iq_report->rssi = (int8_t)param->valueint; + param = cJSON_GetObjectItem(root, "sequence"); + CHECK_TYPE(param, cJSON_Number); + iq_report->event_counter = (uint16_t)param->valueint; + cJSON_ArrayForEach(param, samples) { + CHECK_TYPE(param, cJSON_Number); + iq_report->samples[length] = (int8_t)param->valueint; + ++length; + } + iq_report->length = length; + cJSON_Delete(root); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Serialize angle data structure into string. + ******************************************************************************/ +sl_status_t aoa_serialize_angle(aoa_angle_t *angle, char **str) +{ + if ((angle == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON *obj = NULL; + cJSON *root = cJSON_CreateObject(); + CHECK_NULL_RETURN(root, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "azimuth", (double)angle->azimuth); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "azimuth_stdev", (double)angle->azimuth_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "elevation", (double)angle->elevation); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "elevation_stdev", (double)angle->elevation_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "distance", (double)angle->distance); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "distance_stdev", (double)angle->distance_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "sequence", (int)angle->sequence); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + *str = cJSON_Print(root); + cJSON_Delete(root); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deserialize angle data structure from string. + ******************************************************************************/ +sl_status_t aoa_deserialize_angle(char *str, aoa_angle_t *angle) +{ + if ((angle == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON *root = cJSON_Parse(str); + CHECK_TYPE(root, cJSON_Object); + cJSON *param = cJSON_GetObjectItem(root, "azimuth"); + CHECK_TYPE(param, cJSON_Number); + angle->azimuth = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "azimuth_stdev"); + CHECK_TYPE(param, cJSON_Number); + angle->azimuth_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "elevation"); + CHECK_TYPE(param, cJSON_Number); + angle->elevation = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "elevation_stdev"); + CHECK_TYPE(param, cJSON_Number); + angle->elevation_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "distance"); + CHECK_TYPE(param, cJSON_Number); + angle->distance = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "distance_stdev"); + CHECK_TYPE(param, cJSON_Number); + angle->distance_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "sequence"); + CHECK_TYPE(param, cJSON_Number); + angle->sequence = (int32_t)param->valueint; + cJSON_Delete(root); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Serialize position data structure into string. + ******************************************************************************/ +sl_status_t aoa_serialize_position(aoa_position_t *position, char **str) +{ + if ((position == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON *obj = NULL; + cJSON *root = cJSON_CreateObject(); + CHECK_NULL_RETURN(root, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "x", position->x); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "x_stdev", position->x_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "y", position->y); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "y_stdev", position->y_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "z", position->z); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "z_stdev", position->z_stdev); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + obj = cJSON_AddNumberToObject(root, "sequence", (int)position->sequence); + CHECK_NULL_RETURN(obj, SL_STATUS_FAIL); + *str = cJSON_Print(root); + cJSON_Delete(root); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Deserialize position data structure from string. + ******************************************************************************/ +sl_status_t aoa_deserialize_position(char *str, aoa_position_t *position) +{ + if ((position == NULL) || (str == NULL)) { + return SL_STATUS_NULL_POINTER; + } + cJSON *root = cJSON_Parse(str); + CHECK_TYPE(root, cJSON_Object); + cJSON *param = cJSON_GetObjectItem(root, "x"); + CHECK_TYPE(param, cJSON_Number); + position->x = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "x_stdev"); + CHECK_TYPE(param, cJSON_Number); + position->x_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "y"); + CHECK_TYPE(param, cJSON_Number); + position->y = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "y_stdev"); + CHECK_TYPE(param, cJSON_Number); + position->y_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "z"); + CHECK_TYPE(param, cJSON_Number); + position->z = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "z_stdev"); + CHECK_TYPE(param, cJSON_Number); + position->z_stdev = (float)param->valuedouble; + param = cJSON_GetObjectItem(root, "sequence"); + CHECK_TYPE(param, cJSON_Number); + position->sequence = (int32_t)param->valueint; + cJSON_Delete(root); + return SL_STATUS_OK; +} diff --git a/locator_host/bt/aoa/aoa_util/aoa_serdes.h b/locator_host/bt/aoa/aoa_util/aoa_serdes.h index ac2b924..8e9c223 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_serdes.h +++ b/locator_host/bt/aoa/aoa_util/aoa_serdes.h @@ -1,85 +1,85 @@ -/***************************************************************************//** - * @file - * @brief AoA serializer and deserializer functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_SERDES_H -#define AOA_SERDES_H - -#include "sl_status.h" -#include "aoa_types.h" - -/***************************************************************************//** - * Serialize IQ report data structure into string. - * - * @param[in] iq_report IQ report data structure. - * @param[out] str Pointer to the string buffer, should be freed after use. - ******************************************************************************/ -sl_status_t aoa_serialize_iq_report(aoa_iq_report_t *iq_report, char **str); - -/***************************************************************************//** - * Deserialize IQ report data structure from string. - * - * @param[in] str String buffer. - * @param[out] iq_report IQ report data structure. - ******************************************************************************/ -sl_status_t aoa_deserialize_iq_report(char *str, aoa_iq_report_t *iq_report); - -/***************************************************************************//** - * Serialize angle data structure into string. - * - * @param[in] angle Angle data structure. - * @param[out] str Pointer to the string buffer, should be freed after use. - ******************************************************************************/ -sl_status_t aoa_serialize_angle(aoa_angle_t *angle, char **str); - -/***************************************************************************//** - * Deserialize angle data structure from string. - * - * @param[in] str String buffer. - * @param[out] angle Angle data structure. - ******************************************************************************/ -sl_status_t aoa_deserialize_angle(char *str, aoa_angle_t *angle); - -/***************************************************************************//** - * Serialize position data structure into string. - * - * @param[in] position Position data structure. - * @param[out] str Pointer to the string buffer, should be freed after use. - ******************************************************************************/ -sl_status_t aoa_serialize_position(aoa_position_t *position, char **str); - -/***************************************************************************//** - * Deserialize position data structure from string. - * - * @param[in] str String buffer. - * @param[out] position Position data structure. - ******************************************************************************/ -sl_status_t aoa_deserialize_position(char *str, aoa_position_t *position); - -#endif // AOA_SERDES_H +/***************************************************************************//** + * @file + * @brief AoA serializer and deserializer functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_SERDES_H +#define AOA_SERDES_H + +#include "sl_status.h" +#include "aoa_types.h" + +/***************************************************************************//** + * Serialize IQ report data structure into string. + * + * @param[in] iq_report IQ report data structure. + * @param[out] str Pointer to the string buffer, should be freed after use. + ******************************************************************************/ +sl_status_t aoa_serialize_iq_report(aoa_iq_report_t *iq_report, char **str); + +/***************************************************************************//** + * Deserialize IQ report data structure from string. + * + * @param[in] str String buffer. + * @param[out] iq_report IQ report data structure. + ******************************************************************************/ +sl_status_t aoa_deserialize_iq_report(char *str, aoa_iq_report_t *iq_report); + +/***************************************************************************//** + * Serialize angle data structure into string. + * + * @param[in] angle Angle data structure. + * @param[out] str Pointer to the string buffer, should be freed after use. + ******************************************************************************/ +sl_status_t aoa_serialize_angle(aoa_angle_t *angle, char **str); + +/***************************************************************************//** + * Deserialize angle data structure from string. + * + * @param[in] str String buffer. + * @param[out] angle Angle data structure. + ******************************************************************************/ +sl_status_t aoa_deserialize_angle(char *str, aoa_angle_t *angle); + +/***************************************************************************//** + * Serialize position data structure into string. + * + * @param[in] position Position data structure. + * @param[out] str Pointer to the string buffer, should be freed after use. + ******************************************************************************/ +sl_status_t aoa_serialize_position(aoa_position_t *position, char **str); + +/***************************************************************************//** + * Deserialize position data structure from string. + * + * @param[in] str String buffer. + * @param[out] position Position data structure. + ******************************************************************************/ +sl_status_t aoa_deserialize_position(char *str, aoa_position_t *position); + +#endif // AOA_SERDES_H diff --git a/locator_host/bt/aoa/aoa_util/aoa_topics.h b/locator_host/bt/aoa/aoa_util/aoa_topics.h index e13de78..94e21f6 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_topics.h +++ b/locator_host/bt/aoa/aoa_util/aoa_topics.h @@ -1,46 +1,46 @@ -/***************************************************************************//** - * @file - * @brief AoA MQTT topics. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_TOPICS_H -#define AOA_TOPICS_H - -#define AOA_TOPIC_IQ_REPORT_PRINT "silabs/aoa/iq_report/%s/%s" -#define AOA_TOPIC_IQ_REPORT_SCAN "silabs/aoa/iq_report/%64[^/]/%64[^/]" -#define AOA_TOPIC_ANGLE_PRINT "silabs/aoa/angle/%s/%s" -#define AOA_TOPIC_ANGLE_SCAN "silabs/aoa/angle/%64[^/]/%64[^/]" -#define AOA_TOPIC_POSITION_PRINT "silabs/aoa/position/%s/%s" -#define AOA_TOPIC_POSITION_SCAN "silabs/aoa/position/%64[^/]/%64[^/]" -#define AOA_TOPIC_CORRECTION_PRINT "silabs/aoa/correction/%s/%s" -#define AOA_TOPIC_CORRECTION_SCAN "silabs/aoa/correction/%64[^/]/%64[^/]" -#define AOA_TOPIC_CONFIG_PRINT "silabs/aoa/config/%s" -#define AOA_TOPIC_CONFIG_SCAN "silabs/aoa/config/%64[^/]" -#define AOA_TOPIC_CONFIG_BROADCAST "silabs/aoa/config" - -#endif // AOA_TOPICS_H +/***************************************************************************//** + * @file + * @brief AoA MQTT topics. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_TOPICS_H +#define AOA_TOPICS_H + +#define AOA_TOPIC_IQ_REPORT_PRINT "silabs/aoa/iq_report/%s/%s" +#define AOA_TOPIC_IQ_REPORT_SCAN "silabs/aoa/iq_report/%64[^/]/%64[^/]" +#define AOA_TOPIC_ANGLE_PRINT "silabs/aoa/angle/%s/%s" +#define AOA_TOPIC_ANGLE_SCAN "silabs/aoa/angle/%64[^/]/%64[^/]" +#define AOA_TOPIC_POSITION_PRINT "silabs/aoa/position/%s/%s" +#define AOA_TOPIC_POSITION_SCAN "silabs/aoa/position/%64[^/]/%64[^/]" +#define AOA_TOPIC_CORRECTION_PRINT "silabs/aoa/correction/%s/%s" +#define AOA_TOPIC_CORRECTION_SCAN "silabs/aoa/correction/%64[^/]/%64[^/]" +#define AOA_TOPIC_CONFIG_PRINT "silabs/aoa/config/%s" +#define AOA_TOPIC_CONFIG_SCAN "silabs/aoa/config/%64[^/]" +#define AOA_TOPIC_CONFIG_BROADCAST "silabs/aoa/config" + +#endif // AOA_TOPICS_H diff --git a/locator_host/bt/aoa/aoa_util/aoa_types.h b/locator_host/bt/aoa/aoa_util/aoa_types.h index 8f5034b..57aa788 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_types.h +++ b/locator_host/bt/aoa/aoa_util/aoa_types.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief AoA type definitions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_TYPES_H -#define AOA_TYPES_H - -#include - -#define AOA_ID_MAX_SIZE 64 - -typedef char aoa_id_t[AOA_ID_MAX_SIZE]; - -typedef struct aoa_iq_report_s { - uint8_t channel; - int8_t rssi; - uint16_t event_counter; - uint8_t length; - int8_t *samples; -} aoa_iq_report_t; - -typedef struct aoa_angle_s { - float azimuth; - float azimuth_stdev; - float elevation; - float elevation_stdev; - float distance; - float distance_stdev; - int32_t sequence; -} aoa_angle_t; - -typedef struct aoa_position_s { - float x; - float x_stdev; - float y; - float y_stdev; - float z; - float z_stdev; - int32_t sequence; -} aoa_position_t; - -#endif // AOA_TYPES_H +/***************************************************************************//** + * @file + * @brief AoA type definitions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_TYPES_H +#define AOA_TYPES_H + +#include + +#define AOA_ID_MAX_SIZE 64 + +typedef char aoa_id_t[AOA_ID_MAX_SIZE]; + +typedef struct aoa_iq_report_s { + uint8_t channel; + int8_t rssi; + uint16_t event_counter; + uint8_t length; + int8_t *samples; +} aoa_iq_report_t; + +typedef struct aoa_angle_s { + float azimuth; + float azimuth_stdev; + float elevation; + float elevation_stdev; + float distance; + float distance_stdev; + int32_t sequence; +} aoa_angle_t; + +typedef struct aoa_position_s { + float x; + float x_stdev; + float y; + float y_stdev; + float z; + float z_stdev; + int32_t sequence; +} aoa_position_t; + +#endif // AOA_TYPES_H diff --git a/locator_host/bt/aoa/aoa_util/aoa_util.c b/locator_host/bt/aoa/aoa_util/aoa_util.c index 53bf933..3ee2a61 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_util.c +++ b/locator_host/bt/aoa/aoa_util/aoa_util.c @@ -1,204 +1,204 @@ -/***************************************************************************//** - * @file - * @brief AoA Utilities. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include -#include -#include "aoa_util.h" - -/**************************************************************************//** - * Copies aoa id from source to destination. - *****************************************************************************/ -void aoa_id_copy(aoa_id_t dst, aoa_id_t src) -{ - strncpy(dst, src, AOA_ID_MAX_SIZE); - dst[AOA_ID_MAX_SIZE - 1] = 0; -} - -/**************************************************************************//** - * Compares two aoa ids. - *****************************************************************************/ -int aoa_id_compare(aoa_id_t id1, aoa_id_t id2) -{ - return strncasecmp(id1, id2, AOA_ID_MAX_SIZE); -} - -/**************************************************************************//** - * Converts address to aoa id. - *****************************************************************************/ -void aoa_address_to_id(uint8_t address[ADR_LEN], - uint8_t address_type, - aoa_id_t id) -{ - snprintf(id, AOA_ID_MAX_SIZE, "ble-%s-%02X%02X%02X%02X%02X%02X", - address_type ? "sr" : "pd", - address[5], - address[4], - address[3], - address[2], - address[1], - address[0]); -} - -/**************************************************************************//** - * Converts aoa id to address. - *****************************************************************************/ -sl_status_t aoa_id_to_address(aoa_id_t id, - uint8_t address[ADR_LEN], - uint8_t *address_type) -{ - sl_status_t ret = SL_STATUS_OK; - int retval, i; - unsigned int address_cache[ADR_LEN]; - char *token; - const char delimiter[2] = "-"; - char id_cache[AOA_ID_MAX_SIZE]; - char *saveptr; - - strncpy(id_cache, id, AOA_ID_MAX_SIZE); - - for (i = 0; i < ADR_LEN; i++) { - address_cache[i] = 0; - } - - do { - token = strtok_r(id_cache, delimiter, &saveptr); - // Look for the "ble" prefix. - // If there is no BLE string found in the beginning, abort. - if (token == NULL || strcasecmp("ble", token) != 0) { - ret = SL_STATUS_NOT_FOUND; - break; - } - // Parse address type. - token = strtok_r(NULL, delimiter, &saveptr); - if (token != NULL) { - if (strcasecmp("sr", token) == 0) { - *address_type = 1; - } else { - *address_type = 0; - } - } else { - ret = SL_STATUS_NOT_FOUND; - break; - } - - // Parse address. - token = strtok_r(NULL, delimiter, &saveptr); - if (token != NULL) { - retval = sscanf(token, "%2X%2X%2X%2X%2X%2X", - &address_cache[5], - &address_cache[4], - &address_cache[3], - &address_cache[2], - &address_cache[1], - &address_cache[0]); - if (retval == ADR_LEN) { - for (i = 0; i < ADR_LEN; i++) { - address[i] = address_cache[i]; - } - } else { - ret = SL_STATUS_NOT_FOUND; - break; - } - } else { - ret = SL_STATUS_NOT_FOUND; - break; - } - } while (0); - - return ret; -} - -/**************************************************************************//** - * Compare two sequence numbers. - *****************************************************************************/ -int32_t aoa_sequence_compare(int32_t seq1, int32_t seq2) -{ - int32_t diff; - - if ((seq1 < 0) || (seq2 < 0)) { - // Negative sequence numbers are considered as invalid. - return INT32_MAX; - } - - diff = abs(seq2 - seq1); - return (diff < ((UINT16_MAX + 1) / 2)) ? diff : UINT16_MAX + 1 - diff; -} - -/***************************************************************************//** - * Find given service UUID in an Advertising or Scan Response packet. - ******************************************************************************/ -bool find_service_in_advertisement(uint8_t *adv_data, - uint8_t adv_len, - const uint8_t *uuid, - size_t uuid_len) -{ - uint8_t ad_field_length; - uint8_t ad_field_type; - uint8_t incomplete_list; - uint8_t complete_list; - uint8_t *ad_uuid_field; - uint32_t i = 0; - uint32_t next_ad_structure; - bool ret = false; - - if ((uuid_len == 2) || (uuid_len == 16)) { - // Incomplete List of 16 or 128-bit Service Class UUIDs. - incomplete_list = (uuid_len == 2) ? 0x02 : 0x06; - // Complete List of 16 or 128-bit Service Class UUIDs. - complete_list = (uuid_len == 2) ? 0x03 : 0x07; - - // Parse advertisement packet. - while (i < adv_len) { - ad_field_length = adv_data[i]; - ad_field_type = adv_data[i + 1]; - next_ad_structure = i + ad_field_length + 1; - // Find AD types of interest. - if (ad_field_type == incomplete_list || ad_field_type == complete_list) { - // Compare each UUID to the service UUID to be found. - for (ad_uuid_field = adv_data + i + 2; - ad_uuid_field < adv_data + next_ad_structure; - ad_uuid_field += uuid_len) { - if (memcmp(ad_uuid_field, uuid, uuid_len) == 0) { - ret = true; - break; - } - } - if (ret == true) { - break; - } - } - // Advance to the next AD structure. - i = next_ad_structure; - } - } - return ret; -} +/***************************************************************************//** + * @file + * @brief AoA Utilities. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include +#include "aoa_util.h" + +/**************************************************************************//** + * Copies aoa id from source to destination. + *****************************************************************************/ +void aoa_id_copy(aoa_id_t dst, aoa_id_t src) +{ + strncpy(dst, src, AOA_ID_MAX_SIZE); + dst[AOA_ID_MAX_SIZE - 1] = 0; +} + +/**************************************************************************//** + * Compares two aoa ids. + *****************************************************************************/ +int aoa_id_compare(aoa_id_t id1, aoa_id_t id2) +{ + return strncasecmp(id1, id2, AOA_ID_MAX_SIZE); +} + +/**************************************************************************//** + * Converts address to aoa id. + *****************************************************************************/ +void aoa_address_to_id(uint8_t address[ADR_LEN], + uint8_t address_type, + aoa_id_t id) +{ + snprintf(id, AOA_ID_MAX_SIZE, "ble-%s-%02X%02X%02X%02X%02X%02X", + address_type ? "sr" : "pd", + address[5], + address[4], + address[3], + address[2], + address[1], + address[0]); +} + +/**************************************************************************//** + * Converts aoa id to address. + *****************************************************************************/ +sl_status_t aoa_id_to_address(aoa_id_t id, + uint8_t address[ADR_LEN], + uint8_t *address_type) +{ + sl_status_t ret = SL_STATUS_OK; + int retval, i; + unsigned int address_cache[ADR_LEN]; + char *token; + const char delimiter[2] = "-"; + char id_cache[AOA_ID_MAX_SIZE]; + char *saveptr; + + strncpy(id_cache, id, AOA_ID_MAX_SIZE); + + for (i = 0; i < ADR_LEN; i++) { + address_cache[i] = 0; + } + + do { + token = strtok_r(id_cache, delimiter, &saveptr); + // Look for the "ble" prefix. + // If there is no BLE string found in the beginning, abort. + if (token == NULL || strcasecmp("ble", token) != 0) { + ret = SL_STATUS_NOT_FOUND; + break; + } + // Parse address type. + token = strtok_r(NULL, delimiter, &saveptr); + if (token != NULL) { + if (strcasecmp("sr", token) == 0) { + *address_type = 1; + } else { + *address_type = 0; + } + } else { + ret = SL_STATUS_NOT_FOUND; + break; + } + + // Parse address. + token = strtok_r(NULL, delimiter, &saveptr); + if (token != NULL) { + retval = sscanf(token, "%2X%2X%2X%2X%2X%2X", + &address_cache[5], + &address_cache[4], + &address_cache[3], + &address_cache[2], + &address_cache[1], + &address_cache[0]); + if (retval == ADR_LEN) { + for (i = 0; i < ADR_LEN; i++) { + address[i] = address_cache[i]; + } + } else { + ret = SL_STATUS_NOT_FOUND; + break; + } + } else { + ret = SL_STATUS_NOT_FOUND; + break; + } + } while (0); + + return ret; +} + +/**************************************************************************//** + * Compare two sequence numbers. + *****************************************************************************/ +int32_t aoa_sequence_compare(int32_t seq1, int32_t seq2) +{ + int32_t diff; + + if ((seq1 < 0) || (seq2 < 0)) { + // Negative sequence numbers are considered as invalid. + return INT32_MAX; + } + + diff = abs(seq2 - seq1); + return (diff < ((UINT16_MAX + 1) / 2)) ? diff : UINT16_MAX + 1 - diff; +} + +/***************************************************************************//** + * Find given service UUID in an Advertising or Scan Response packet. + ******************************************************************************/ +bool find_service_in_advertisement(uint8_t *adv_data, + uint8_t adv_len, + const uint8_t *uuid, + size_t uuid_len) +{ + uint8_t ad_field_length; + uint8_t ad_field_type; + uint8_t incomplete_list; + uint8_t complete_list; + uint8_t *ad_uuid_field; + uint32_t i = 0; + uint32_t next_ad_structure; + bool ret = false; + + if ((uuid_len == 2) || (uuid_len == 16)) { + // Incomplete List of 16 or 128-bit Service Class UUIDs. + incomplete_list = (uuid_len == 2) ? 0x02 : 0x06; + // Complete List of 16 or 128-bit Service Class UUIDs. + complete_list = (uuid_len == 2) ? 0x03 : 0x07; + + // Parse advertisement packet. + while (i < adv_len) { + ad_field_length = adv_data[i]; + ad_field_type = adv_data[i + 1]; + next_ad_structure = i + ad_field_length + 1; + // Find AD types of interest. + if (ad_field_type == incomplete_list || ad_field_type == complete_list) { + // Compare each UUID to the service UUID to be found. + for (ad_uuid_field = adv_data + i + 2; + ad_uuid_field < adv_data + next_ad_structure; + ad_uuid_field += uuid_len) { + if (memcmp(ad_uuid_field, uuid, uuid_len) == 0) { + ret = true; + break; + } + } + if (ret == true) { + break; + } + } + // Advance to the next AD structure. + i = next_ad_structure; + } + } + return ret; +} diff --git a/locator_host/bt/aoa/aoa_util/aoa_util.h b/locator_host/bt/aoa/aoa_util/aoa_util.h index ecdb2e2..67e556c 100644 --- a/locator_host/bt/aoa/aoa_util/aoa_util.h +++ b/locator_host/bt/aoa/aoa_util/aoa_util.h @@ -1,114 +1,114 @@ -/***************************************************************************//** - * @file - * @brief AoA Utilities. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef AOA_UTIL_H -#define AOA_UTIL_H - -#include -#include -#include "aoa_types.h" -#include "sl_status.h" - -#define ADR_LEN 6 - -/**************************************************************************//** - * Copies aoa id from source to destination. - * - * @param[in] dst Destination to copy to. - * @param[in] src Source to copy from. - *****************************************************************************/ -void aoa_id_copy(aoa_id_t dst, aoa_id_t src); - -/**************************************************************************//** - * Compares two aoa ids. Case insensitive. - * - * @param[in] id1 First AoA id. - * @param[in] id2 Second AoA id. - * - * @retval < 0 id1 is less than id2. - * @retval > 0 id1 is greater than id2. - * @retval 0 if the two ids are equal. - *****************************************************************************/ -int aoa_id_compare(aoa_id_t id1, aoa_id_t id2); - -/**************************************************************************//** - * Converts an address to aoa id - * - * @param[in] iaddressd1 address. - * @param[in] address_type address type. - * @param[out] id aoa id. - *****************************************************************************/ -void aoa_address_to_id(uint8_t address[ADR_LEN], - uint8_t address_type, - aoa_id_t id); - -/**************************************************************************//** - * Converts an aoa id to address. - * - * @param[in] id AoA id. - * @param[out] address address. - * @param[out] address_type address type. - * - * @retval SL_STATUS_OK - Conversion completed. - * @retval SL_STATUS_NOT_FOUND - AoA Id is not correct. - *****************************************************************************/ -sl_status_t aoa_id_to_address(aoa_id_t id, - uint8_t address[ADR_LEN], - uint8_t *address_type); - -/**************************************************************************//** - * Compare two sequence numbers. - * - * @param[in] seq1 First sequence number. - * @param[in] seq2 Second sequence number. - * - * @return The absolute distance of the sequence numbers. - * @retval 0 The sequence numbers are equal. - * @retval INT32_MAX Any of the sequence numbers are negative. - *****************************************************************************/ -int32_t aoa_sequence_compare(int32_t seq1, int32_t seq2); - -/***************************************************************************//** - * Find given service UUID in an Advertising or Scan Response packet. - * - * @param[in] adv_data Advertising or Scan Response data - * @param[in] adv_len Length of the Advertising or Scan Response data - * @param[in] uuid 16 or 128-bit Service Class UUID - * @param[in] uuid_len Length of 16 or 128-bit Service Class UUID in bytes - * - * @retval true The service UUID is found - * @retval false The service UUID is not found or invalid input parameters - ******************************************************************************/ -bool find_service_in_advertisement(uint8_t *adv_data, - uint8_t adv_len, - const uint8_t *uuid, - size_t uuid_len); - -#endif // AOA_UTIL_H +/***************************************************************************//** + * @file + * @brief AoA Utilities. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef AOA_UTIL_H +#define AOA_UTIL_H + +#include +#include +#include "aoa_types.h" +#include "sl_status.h" + +#define ADR_LEN 6 + +/**************************************************************************//** + * Copies aoa id from source to destination. + * + * @param[in] dst Destination to copy to. + * @param[in] src Source to copy from. + *****************************************************************************/ +void aoa_id_copy(aoa_id_t dst, aoa_id_t src); + +/**************************************************************************//** + * Compares two aoa ids. Case insensitive. + * + * @param[in] id1 First AoA id. + * @param[in] id2 Second AoA id. + * + * @retval < 0 id1 is less than id2. + * @retval > 0 id1 is greater than id2. + * @retval 0 if the two ids are equal. + *****************************************************************************/ +int aoa_id_compare(aoa_id_t id1, aoa_id_t id2); + +/**************************************************************************//** + * Converts an address to aoa id + * + * @param[in] iaddressd1 address. + * @param[in] address_type address type. + * @param[out] id aoa id. + *****************************************************************************/ +void aoa_address_to_id(uint8_t address[ADR_LEN], + uint8_t address_type, + aoa_id_t id); + +/**************************************************************************//** + * Converts an aoa id to address. + * + * @param[in] id AoA id. + * @param[out] address address. + * @param[out] address_type address type. + * + * @retval SL_STATUS_OK - Conversion completed. + * @retval SL_STATUS_NOT_FOUND - AoA Id is not correct. + *****************************************************************************/ +sl_status_t aoa_id_to_address(aoa_id_t id, + uint8_t address[ADR_LEN], + uint8_t *address_type); + +/**************************************************************************//** + * Compare two sequence numbers. + * + * @param[in] seq1 First sequence number. + * @param[in] seq2 Second sequence number. + * + * @return The absolute distance of the sequence numbers. + * @retval 0 The sequence numbers are equal. + * @retval INT32_MAX Any of the sequence numbers are negative. + *****************************************************************************/ +int32_t aoa_sequence_compare(int32_t seq1, int32_t seq2); + +/***************************************************************************//** + * Find given service UUID in an Advertising or Scan Response packet. + * + * @param[in] adv_data Advertising or Scan Response data + * @param[in] adv_len Length of the Advertising or Scan Response data + * @param[in] uuid 16 or 128-bit Service Class UUID + * @param[in] uuid_len Length of 16 or 128-bit Service Class UUID in bytes + * + * @retval true The service UUID is found + * @retval false The service UUID is not found or invalid input parameters + ******************************************************************************/ +bool find_service_in_advertisement(uint8_t *adv_data, + uint8_t adv_len, + const uint8_t *uuid, + size_t uuid_len); + +#endif // AOA_UTIL_H diff --git a/locator_host/bt/aoa/ncp_evt_filter/config/sl_ncp_evt_filter_config.h b/locator_host/bt/aoa/ncp_evt_filter/config/sl_ncp_evt_filter_config.h index 925e375..769e5c6 100644 --- a/locator_host/bt/aoa/ncp_evt_filter/config/sl_ncp_evt_filter_config.h +++ b/locator_host/bt/aoa/ncp_evt_filter/config/sl_ncp_evt_filter_config.h @@ -1,48 +1,48 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_CONFIG_H -#define SL_NCP_EVT_FILTER_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Array length of the event filter <1-16> -// Default: 8 -// Define the length of Bluetooth NCP event filter buffer. -#define SL_NCP_EVT_FILTER_ARRAY_LENGTH 8 -// <<< end of configuration section >>> - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_CONFIG_H +#define SL_NCP_EVT_FILTER_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Array length of the event filter <1-16> +// Default: 8 +// Define the length of Bluetooth NCP event filter buffer. +#define SL_NCP_EVT_FILTER_ARRAY_LENGTH 8 +// <<< end of configuration section >>> + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_CONFIG_H diff --git a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.c b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.c index d955ba2..a0c3922 100644 --- a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.c +++ b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.c @@ -1,220 +1,220 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "sl_status.h" -#include "sl_ncp_evt_filter.h" -#include "sl_ncp_evt_filter_config.h" -#include "sl_ncp_evt_filter_common.h" - -static evt_filter_t evt_filter_array[SL_NCP_EVT_FILTER_ARRAY_LENGTH]; -static uint8_t evt_pos = 0; - -static sl_status_t evt_filter_add_to_array(evt_filter_t event); -static bool evt_filter_search_in_array(evt_filter_t event); -static sl_status_t evt_filter_remove_from_array(evt_filter_t event); -static sl_status_t evt_filter_reset_array(void); -static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd); - -// ----------------------------------------------------------------------------- -// Public functions (API implementation) - -/**************************************************************************//** - * User command (manage_event_filter) handler. - *****************************************************************************/ -void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd) -{ - sl_status_t status = SL_STATUS_FAIL; - - //check length of commands - if (false == evt_filter_check_is_valid_user_command(cmd)) { - sl_bt_send_rsp_user_manage_event_filter(status); - return; - } - - switch (cmd->hdr.id) { - // ------------------------------- - // Add event filter - case SL_NCP_EVT_FILTER_CMD_ADD_ID: - status = evt_filter_add_to_array(cmd->evt); - break; - - // ------------------------------- - // Remove event filter - case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: - status = evt_filter_remove_from_array(cmd->evt); - break; - - // ------------------------------- - // Reset event filter - case SL_NCP_EVT_FILTER_CMD_RESET_ID: - status = evt_filter_reset_array(); - break; - - // ------------------------------- - default: - // Unknown subcommand, send response with failure. - break; - } - - sl_bt_send_rsp_user_manage_event_filter(status); -} - -/***************************************************************************//** - * Checks if the given event is filtered or not. - ******************************************************************************/ -bool sl_ncp_evt_filter_is_filtered(uint32_t header) -{ - return evt_filter_search_in_array(header); -} - -/***************************************************************************//** - * Checks the payload length and header length. - * - * @param[in] cmd: Contains the len, cmd id and event. - * @return Returns false if lengths are not valid true otherwise. - ******************************************************************************/ -static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd) -{ - bool valid = false; - - switch (cmd->hdr.id) { - case SL_NCP_EVT_FILTER_CMD_ADD_ID: - if (SL_NCP_EVT_FILTER_CMD_ADD_LEN == cmd->hdr.len) { - valid = true; - } - break; - - case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: - if (SL_NCP_EVT_FILTER_CMD_REMOVE_LEN == cmd->hdr.len) { - valid = true; - } - break; - - case SL_NCP_EVT_FILTER_CMD_RESET_ID: - if (SL_NCP_EVT_FILTER_CMD_RESET_LEN == cmd->hdr.len) { - valid = true; - } - break; - - default: - break; - } - - return valid; -} - -/***************************************************************************//** - * Clears the content of the event filter array. - * - * @return Returns ok - ******************************************************************************/ -static sl_status_t evt_filter_reset_array(void) -{ - sl_status_t status = SL_STATUS_OK; - memset(evt_filter_array, 0, sizeof(evt_filter_array)); - evt_pos = 0; - return status; -} - -/***************************************************************************//** - * Deletes the given event in the event filter array. - * - * @param[in] event - * @return Returns ok or not_found or empty - ******************************************************************************/ -static sl_status_t evt_filter_remove_from_array(evt_filter_t event) -{ - uint8_t i, j; - sl_status_t status = SL_STATUS_NOT_FOUND; - uint8_t evt_pos_tmp = evt_pos; - - if (evt_pos > 0) { - for (i = 0; i < evt_pos; i++) { - if (event == evt_filter_array[i]) { - evt_filter_array[i] = 0; - status = SL_STATUS_OK; - evt_pos -= 1; - - //move element one space ahead from the removed element - for (j = i; j < evt_pos_tmp - 1; j++) { - evt_filter_array[j] = evt_filter_array[j + 1]; - evt_filter_array[j + 1] = 0; - } - break; - } - } - } else { - status = SL_STATUS_EMPTY; - } - - return status; -} - -/***************************************************************************//** - * Stores the given event in the event filter array. - * - * @param[in] event - * @return Returns ok or full or already exists - ******************************************************************************/ -static sl_status_t evt_filter_add_to_array(evt_filter_t event) -{ - sl_status_t status = SL_STATUS_OK; - - if (evt_pos == SL_NCP_EVT_FILTER_ARRAY_LENGTH) { - status = SL_STATUS_FULL; - } else if (false == evt_filter_search_in_array(event)) { - evt_filter_array[evt_pos] = event; - evt_pos++; - } else { - status = SL_STATUS_ALREADY_EXISTS; - } - return status; -} - -/***************************************************************************//** - * Searches the given event in the event filter array. - * - * @param[in] event - * @return Returns true if finds, false otherwise. - ******************************************************************************/ -static bool evt_filter_search_in_array(evt_filter_t event) -{ - uint8_t i; - bool catch = false; - - for (i = 0; i < evt_pos; i++) { - if (event == evt_filter_array[i]) { - catch = true; - break; - } - } - return catch; -} +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_status.h" +#include "sl_ncp_evt_filter.h" +#include "sl_ncp_evt_filter_config.h" +#include "sl_ncp_evt_filter_common.h" + +static evt_filter_t evt_filter_array[SL_NCP_EVT_FILTER_ARRAY_LENGTH]; +static uint8_t evt_pos = 0; + +static sl_status_t evt_filter_add_to_array(evt_filter_t event); +static bool evt_filter_search_in_array(evt_filter_t event); +static sl_status_t evt_filter_remove_from_array(evt_filter_t event); +static sl_status_t evt_filter_reset_array(void); +static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd); + +// ----------------------------------------------------------------------------- +// Public functions (API implementation) + +/**************************************************************************//** + * User command (manage_event_filter) handler. + *****************************************************************************/ +void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd) +{ + sl_status_t status = SL_STATUS_FAIL; + + //check length of commands + if (false == evt_filter_check_is_valid_user_command(cmd)) { + sl_bt_send_rsp_user_manage_event_filter(status); + return; + } + + switch (cmd->hdr.id) { + // ------------------------------- + // Add event filter + case SL_NCP_EVT_FILTER_CMD_ADD_ID: + status = evt_filter_add_to_array(cmd->evt); + break; + + // ------------------------------- + // Remove event filter + case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: + status = evt_filter_remove_from_array(cmd->evt); + break; + + // ------------------------------- + // Reset event filter + case SL_NCP_EVT_FILTER_CMD_RESET_ID: + status = evt_filter_reset_array(); + break; + + // ------------------------------- + default: + // Unknown subcommand, send response with failure. + break; + } + + sl_bt_send_rsp_user_manage_event_filter(status); +} + +/***************************************************************************//** + * Checks if the given event is filtered or not. + ******************************************************************************/ +bool sl_ncp_evt_filter_is_filtered(uint32_t header) +{ + return evt_filter_search_in_array(header); +} + +/***************************************************************************//** + * Checks the payload length and header length. + * + * @param[in] cmd: Contains the len, cmd id and event. + * @return Returns false if lengths are not valid true otherwise. + ******************************************************************************/ +static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd) +{ + bool valid = false; + + switch (cmd->hdr.id) { + case SL_NCP_EVT_FILTER_CMD_ADD_ID: + if (SL_NCP_EVT_FILTER_CMD_ADD_LEN == cmd->hdr.len) { + valid = true; + } + break; + + case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: + if (SL_NCP_EVT_FILTER_CMD_REMOVE_LEN == cmd->hdr.len) { + valid = true; + } + break; + + case SL_NCP_EVT_FILTER_CMD_RESET_ID: + if (SL_NCP_EVT_FILTER_CMD_RESET_LEN == cmd->hdr.len) { + valid = true; + } + break; + + default: + break; + } + + return valid; +} + +/***************************************************************************//** + * Clears the content of the event filter array. + * + * @return Returns ok + ******************************************************************************/ +static sl_status_t evt_filter_reset_array(void) +{ + sl_status_t status = SL_STATUS_OK; + memset(evt_filter_array, 0, sizeof(evt_filter_array)); + evt_pos = 0; + return status; +} + +/***************************************************************************//** + * Deletes the given event in the event filter array. + * + * @param[in] event + * @return Returns ok or not_found or empty + ******************************************************************************/ +static sl_status_t evt_filter_remove_from_array(evt_filter_t event) +{ + uint8_t i, j; + sl_status_t status = SL_STATUS_NOT_FOUND; + uint8_t evt_pos_tmp = evt_pos; + + if (evt_pos > 0) { + for (i = 0; i < evt_pos; i++) { + if (event == evt_filter_array[i]) { + evt_filter_array[i] = 0; + status = SL_STATUS_OK; + evt_pos -= 1; + + //move element one space ahead from the removed element + for (j = i; j < evt_pos_tmp - 1; j++) { + evt_filter_array[j] = evt_filter_array[j + 1]; + evt_filter_array[j + 1] = 0; + } + break; + } + } + } else { + status = SL_STATUS_EMPTY; + } + + return status; +} + +/***************************************************************************//** + * Stores the given event in the event filter array. + * + * @param[in] event + * @return Returns ok or full or already exists + ******************************************************************************/ +static sl_status_t evt_filter_add_to_array(evt_filter_t event) +{ + sl_status_t status = SL_STATUS_OK; + + if (evt_pos == SL_NCP_EVT_FILTER_ARRAY_LENGTH) { + status = SL_STATUS_FULL; + } else if (false == evt_filter_search_in_array(event)) { + evt_filter_array[evt_pos] = event; + evt_pos++; + } else { + status = SL_STATUS_ALREADY_EXISTS; + } + return status; +} + +/***************************************************************************//** + * Searches the given event in the event filter array. + * + * @param[in] event + * @return Returns true if finds, false otherwise. + ******************************************************************************/ +static bool evt_filter_search_in_array(evt_filter_t event) +{ + uint8_t i; + bool catch = false; + + for (i = 0; i < evt_pos; i++) { + if (event == evt_filter_array[i]) { + catch = true; + break; + } + } + return catch; +} diff --git a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.h b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.h index c5fa99c..66226bb 100644 --- a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.h +++ b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_H -#define SL_NCP_EVT_FILTER_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -#include -#include -#include "sl_bt_api.h" - -typedef uint32_t evt_filter_t; - -PACKSTRUCT(struct user_cmd_manage_event_filter { - struct { - uint8_t len; - uint8_t id; - } hdr; - evt_filter_t evt; -}); - -typedef struct user_cmd_manage_event_filter user_cmd_manage_event_filter_t; - -/**************************************************************************//** - * User command (manage_event_filter) handler. - * This function processes the event filter command which is in the cmd - * parameter and according to it adds/removes/resets the events in the - * event filter array. - * - * @param[in] cmd payload of manage event filter - *****************************************************************************/ -void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd); - -/***************************************************************************//** - * Checks if the given event is filtered or not. - * - * @param[in] header incoming Bluetooth stack event header - * @return Returns true if filtered, false otherwise. - ******************************************************************************/ -bool sl_ncp_evt_filter_is_filtered(uint32_t header); - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_H +#define SL_NCP_EVT_FILTER_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +#include +#include +#include "sl_bt_api.h" + +typedef uint32_t evt_filter_t; + +PACKSTRUCT(struct user_cmd_manage_event_filter { + struct { + uint8_t len; + uint8_t id; + } hdr; + evt_filter_t evt; +}); + +typedef struct user_cmd_manage_event_filter user_cmd_manage_event_filter_t; + +/**************************************************************************//** + * User command (manage_event_filter) handler. + * This function processes the event filter command which is in the cmd + * parameter and according to it adds/removes/resets the events in the + * event filter array. + * + * @param[in] cmd payload of manage event filter + *****************************************************************************/ +void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd); + +/***************************************************************************//** + * Checks if the given event is filtered or not. + * + * @param[in] header incoming Bluetooth stack event header + * @return Returns true if filtered, false otherwise. + ******************************************************************************/ +bool sl_ncp_evt_filter_is_filtered(uint32_t header); + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_H diff --git a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter_common.h b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter_common.h index 4bb98f5..6376de6 100644 --- a/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter_common.h +++ b/locator_host/bt/aoa/ncp_evt_filter/sl_ncp_evt_filter_common.h @@ -1,50 +1,50 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_COMMON_H -#define SL_NCP_EVT_FILTER_COMMON_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -// Manage event filter user command -#define SL_NCP_EVT_FILTER_CMD_ADD_ID 0 -#define SL_NCP_EVT_FILTER_CMD_REMOVE_ID 1 -#define SL_NCP_EVT_FILTER_CMD_RESET_ID 2 - -// Manage event filter command payload length -#define SL_NCP_EVT_FILTER_CMD_ADD_LEN 5 -#define SL_NCP_EVT_FILTER_CMD_REMOVE_LEN 5 -#define SL_NCP_EVT_FILTER_CMD_RESET_LEN 1 - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_COMMON_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_COMMON_H +#define SL_NCP_EVT_FILTER_COMMON_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +// Manage event filter user command +#define SL_NCP_EVT_FILTER_CMD_ADD_ID 0 +#define SL_NCP_EVT_FILTER_CMD_REMOVE_ID 1 +#define SL_NCP_EVT_FILTER_CMD_RESET_ID 2 + +// Manage event filter command payload length +#define SL_NCP_EVT_FILTER_CMD_ADD_LEN 5 +#define SL_NCP_EVT_FILTER_CMD_REMOVE_LEN 5 +#define SL_NCP_EVT_FILTER_CMD_RESET_LEN 1 + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_COMMON_H diff --git a/locator_host/bt/aoa/sl_bt_aoa.c b/locator_host/bt/aoa/sl_bt_aoa.c index a73b447..157336e 100644 --- a/locator_host/bt/aoa/sl_bt_aoa.c +++ b/locator_host/bt/aoa/sl_bt_aoa.c @@ -1,175 +1,175 @@ -/***************************************************************************//** - * @file - * @brief BT AOA application - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include -#include "sl_common.h" -#include "sl_bt_api.h" -#include "sl_bt_ncp_host.h" -#include "sl_bt_aoa.h" -#include "aoa_cte.h" -#include "aoa_angle.h" -#include "aoa_angle_config.h" -#include "app_log.h" -#include "sl_system_config.h" -#include "sl_timer.h" - -//macros ----------------------------------------------------------------------- -///Set to 1 if you wish to report angles instead of the raw IQ data. -#define SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED SYSTEM_BT_AOA_ANGLE_CALCULATION_EN - -//private type definitions ----------------------------------------------------- -//private function prototypes -------------------------------------------------- -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED -static inline sl_status_t sli_bt_aoa_calculate_angle(aoa_state_t *state, aoa_iq_report_t *iq, aoa_angle_t *angle); -#endif - -//private variables ------------------------------------------------------------ -static antenna_array_t sli_bt_aoa_antenna_array; -static sl_bt_aoa_locator_id_t sli_bt_aoa_locator_id; -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED -static aoa_angle_config_t *sli_bt_aoa_angle_configuration; -static aoa_id_t sli_bt_aoa_angle_id = "0"; -SL_TIMER_RUNTIME_STRUCT_DEFINE(sli_bt_aoa_angle_calc_meas); -#endif -SL_TIMER_RUNTIME_STRUCT_DEFINE(sli_bt_aoa_cycle_meas); - -//function definitions---------------------------------------------------------- -void sl_bt_aoa_init(void) -{ - antenna_array_init(&sli_bt_aoa_antenna_array, AOA_ANGLE_ANTENNA_ARRAY_TYPE); - aoa_cte_config.antenna_array = &sli_bt_aoa_antenna_array; - -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED - sl_status_t status = aoa_angle_add_config(sli_bt_aoa_angle_id, &sli_bt_aoa_angle_configuration); - SYSTEM_ASSERT(SL_STATUS_OK == status); - status = aoa_angle_finalize_config(sli_bt_aoa_angle_id); - SYSTEM_ASSERT(SL_STATUS_OK == status); -#endif - - sl_bt_system_reset(sl_bt_system_boot_mode_normal); -} - -void sl_bt_on_event(sl_bt_msg_t *evt) -{ - sl_timer_runtime_meas_start(&sli_bt_aoa_cycle_meas); - - switch (SL_BT_MSG_ID(evt->header)) { - case sl_bt_evt_system_boot_id: - // This event indicates the device has started and the radio is ready. - // Do not call any stack command before receiving this boot event! - app_log_info("BT NCP boot! Stack version: %d.%d.%d (build %d)" APP_LOG_NL, - evt->data.evt_system_boot.major, - evt->data.evt_system_boot.minor, - evt->data.evt_system_boot.patch, - evt->data.evt_system_boot.build); - sl_bt_system_get_identity_address((void *)&sli_bt_aoa_locator_id.system_id, NULL); - app_log_info("MAC address (reversed endianness): %06llX\r\n", sli_bt_aoa_locator_id.system_id); - break; - - case sl_bt_evt_system_error_id: - SYSTEM_ASSERT(0); - break; - case sl_bt_evt_system_hardware_error_id: - SYSTEM_ASSERT(0); - break; - case sl_bt_evt_system_resource_exhausted_id: - SYSTEM_ASSERT(0, "Sys. exhausted, discarded: %u, buff alloc: %u, heap alloc: %u\r\n", - evt->data.evt_system_resource_exhausted.num_buffers_discarded, - evt->data.evt_system_resource_exhausted.num_buffer_allocation_failures, - evt->data.evt_system_resource_exhausted.num_heap_allocation_failures); - break; - - default: - break; - } - - aoa_cte_bt_on_event(evt); - sl_timer_runtime_meas_stop(&sli_bt_aoa_cycle_meas); -} - -/**************************************************************************//** - * Tag added callback (will be called before IQ report) - * - * @param[in] tag Pointer to tag. - *****************************************************************************/ -void aoa_db_on_tag_added(aoa_db_entry_t *tag) -{ -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED - tag->user_data = malloc(sizeof(aoa_state_t)); - SYSTEM_ASSERT(NULL != tag->user_data, "Failed to allocate memory for aoa state."); - - enum sl_rtl_error_code ec = aoa_init_rtl(tag->user_data, sli_bt_aoa_angle_id, false); - SYSTEM_ASSERT(ec == SL_RTL_ERROR_SUCCESS, "aoa_init_rtl failed (%d)", ec); -#else - (void)tag; -#endif -} - -/**************************************************************************//** - * Callback to notify the application on new iq report. - * - * @param[in] tag Pointer to the tag. - * @param[in] iq_report IQ report from the tag. - *****************************************************************************/ -void aoa_cte_on_iq_report(aoa_db_entry_t *tag, - aoa_iq_report_t *iq_report) -{ - const sl_bt_aoa_tag_id_t tag_id = { - .mac_addr = { - tag->address.addr[0], tag->address.addr[1], tag->address.addr[2], - tag->address.addr[3], tag->address.addr[4], tag->address.addr[5] - } - }; - -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED - aoa_angle_t angle = { 0 }; - sl_status_t sc = sli_bt_aoa_calculate_angle(tag->user_data, iq_report, &angle); - if (SL_STATUS_OK == sc) { - sl_bt_aoa_on_angle_report(&sli_bt_aoa_locator_id, &tag_id, &angle); - } -#else - sl_bt_aoa_on_iq_report(&sli_bt_aoa_locator_id, &tag_id, iq_report); -#endif -} - -#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED -static inline sl_status_t sli_bt_aoa_calculate_angle(aoa_state_t *state, aoa_iq_report_t *iq, aoa_angle_t *angle) -{ - sl_timer_runtime_meas_start(&sli_bt_aoa_angle_calc_meas); - enum sl_rtl_error_code sc = aoa_calculate(state, iq, angle, sli_bt_aoa_angle_id); - sl_timer_runtime_meas_stop(&sli_bt_aoa_angle_calc_meas); - return sc; //TODO convert to sl_status_t (indifferent at the moment because we only check success/0) -} -#endif - -SL_WEAK void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_iq_report_t *iq) -{ - (void)locator_id; - (void)tag_id; - (void)iq; -} - -SL_WEAK void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_angle_t *angle) -{ - (void)locator_id; - (void)tag_id; - (void)angle; -} +/***************************************************************************//** + * @file + * @brief BT AOA application + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#include +#include "sl_common.h" +#include "sl_bt_api.h" +#include "sl_bt_ncp_host.h" +#include "sl_bt_aoa.h" +#include "aoa_cte.h" +#include "aoa_angle.h" +#include "aoa_angle_config.h" +#include "app_log.h" +#include "sl_system_config.h" +#include "sl_timer.h" + +//macros ----------------------------------------------------------------------- +///Set to 1 if you wish to report angles instead of the raw IQ data. +#define SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED SYSTEM_BT_AOA_ANGLE_CALCULATION_EN + +//private type definitions ----------------------------------------------------- +//private function prototypes -------------------------------------------------- +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED +static inline sl_status_t sli_bt_aoa_calculate_angle(aoa_state_t *state, aoa_iq_report_t *iq, aoa_angle_t *angle); +#endif + +//private variables ------------------------------------------------------------ +static antenna_array_t sli_bt_aoa_antenna_array; +static sl_bt_aoa_locator_id_t sli_bt_aoa_locator_id; +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED +static aoa_angle_config_t *sli_bt_aoa_angle_configuration; +static aoa_id_t sli_bt_aoa_angle_id = "0"; +SL_TIMER_RUNTIME_STRUCT_DEFINE(sli_bt_aoa_angle_calc_meas); +#endif +SL_TIMER_RUNTIME_STRUCT_DEFINE(sli_bt_aoa_cycle_meas); + +//function definitions---------------------------------------------------------- +void sl_bt_aoa_init(void) +{ + antenna_array_init(&sli_bt_aoa_antenna_array, AOA_ANGLE_ANTENNA_ARRAY_TYPE); + aoa_cte_config.antenna_array = &sli_bt_aoa_antenna_array; + +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED + sl_status_t status = aoa_angle_add_config(sli_bt_aoa_angle_id, &sli_bt_aoa_angle_configuration); + SYSTEM_ASSERT(SL_STATUS_OK == status); + status = aoa_angle_finalize_config(sli_bt_aoa_angle_id); + SYSTEM_ASSERT(SL_STATUS_OK == status); +#endif + + sl_bt_system_reset(sl_bt_system_boot_mode_normal); +} + +void sl_bt_on_event(sl_bt_msg_t *evt) +{ + sl_timer_runtime_meas_start(&sli_bt_aoa_cycle_meas); + + switch (SL_BT_MSG_ID(evt->header)) { + case sl_bt_evt_system_boot_id: + // This event indicates the device has started and the radio is ready. + // Do not call any stack command before receiving this boot event! + app_log_info("BT NCP boot! Stack version: %d.%d.%d (build %d)" APP_LOG_NL, + evt->data.evt_system_boot.major, + evt->data.evt_system_boot.minor, + evt->data.evt_system_boot.patch, + evt->data.evt_system_boot.build); + sl_bt_system_get_identity_address((void *)&sli_bt_aoa_locator_id.system_id, NULL); + app_log_info("MAC address (reversed endianness): %06llX\r\n", sli_bt_aoa_locator_id.system_id); + break; + + case sl_bt_evt_system_error_id: + SYSTEM_ASSERT(0); + break; + case sl_bt_evt_system_hardware_error_id: + SYSTEM_ASSERT(0); + break; + case sl_bt_evt_system_resource_exhausted_id: + SYSTEM_ASSERT(0, "Sys. exhausted, discarded: %u, buff alloc: %u, heap alloc: %u\r\n", + evt->data.evt_system_resource_exhausted.num_buffers_discarded, + evt->data.evt_system_resource_exhausted.num_buffer_allocation_failures, + evt->data.evt_system_resource_exhausted.num_heap_allocation_failures); + break; + + default: + break; + } + + aoa_cte_bt_on_event(evt); + sl_timer_runtime_meas_stop(&sli_bt_aoa_cycle_meas); +} + +/**************************************************************************//** + * Tag added callback (will be called before IQ report) + * + * @param[in] tag Pointer to tag. + *****************************************************************************/ +void aoa_db_on_tag_added(aoa_db_entry_t *tag) +{ +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED + tag->user_data = malloc(sizeof(aoa_state_t)); + SYSTEM_ASSERT(NULL != tag->user_data, "Failed to allocate memory for aoa state."); + + enum sl_rtl_error_code ec = aoa_init_rtl(tag->user_data, sli_bt_aoa_angle_id, false); + SYSTEM_ASSERT(ec == SL_RTL_ERROR_SUCCESS, "aoa_init_rtl failed (%d)", ec); +#else + (void)tag; +#endif +} + +/**************************************************************************//** + * Callback to notify the application on new iq report. + * + * @param[in] tag Pointer to the tag. + * @param[in] iq_report IQ report from the tag. + *****************************************************************************/ +void aoa_cte_on_iq_report(aoa_db_entry_t *tag, + aoa_iq_report_t *iq_report) +{ + const sl_bt_aoa_tag_id_t tag_id = { + .mac_addr = { + tag->address.addr[0], tag->address.addr[1], tag->address.addr[2], + tag->address.addr[3], tag->address.addr[4], tag->address.addr[5] + } + }; + +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED + aoa_angle_t angle = { 0 }; + sl_status_t sc = sli_bt_aoa_calculate_angle(tag->user_data, iq_report, &angle); + if (SL_STATUS_OK == sc) { + sl_bt_aoa_on_angle_report(&sli_bt_aoa_locator_id, &tag_id, &angle); + } +#else + sl_bt_aoa_on_iq_report(&sli_bt_aoa_locator_id, &tag_id, iq_report); +#endif +} + +#if SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED +static inline sl_status_t sli_bt_aoa_calculate_angle(aoa_state_t *state, aoa_iq_report_t *iq, aoa_angle_t *angle) +{ + sl_timer_runtime_meas_start(&sli_bt_aoa_angle_calc_meas); + enum sl_rtl_error_code sc = aoa_calculate(state, iq, angle, sli_bt_aoa_angle_id); + sl_timer_runtime_meas_stop(&sli_bt_aoa_angle_calc_meas); + return sc; //TODO convert to sl_status_t (indifferent at the moment because we only check success/0) +} +#endif + +SL_WEAK void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_iq_report_t *iq) +{ + (void)locator_id; + (void)tag_id; + (void)iq; +} + +SL_WEAK void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_angle_t *angle) +{ + (void)locator_id; + (void)tag_id; + (void)angle; +} diff --git a/locator_host/bt/aoa/sl_bt_aoa.h b/locator_host/bt/aoa/sl_bt_aoa.h index 97daf0a..207097f 100644 --- a/locator_host/bt/aoa/sl_bt_aoa.h +++ b/locator_host/bt/aoa/sl_bt_aoa.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef SL_BT_AOA_H -#define SL_BT_AOA_H -#ifdef __cplusplus -extern "C" { -#endif -#include "aoa_util/aoa_types.h" - -//macros ----------------------------------------------------------------------- -//type definitions ------------------------------------------------------------- -typedef struct { - union { - uint8_t mac_addr[6]; //< MAC address of the bluetooth tag. - uint64_t system_id; //< Same as MAC address but in reversed byte order and the last 2 byte will be always 0. - }; -} sl_bt_aoa_tag_id_t; - -//< MAC address of the locator board. (The last 2 byte will be always 0.) -typedef sl_bt_aoa_tag_id_t sl_bt_aoa_locator_id_t; - -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- - -/***************************************************************************//** - * Initializes the BT AOA component. - ******************************************************************************/ -void sl_bt_aoa_init(void); - -/***************************************************************************//** - * Weekly defined function which will be called when an IQ report is received - * from an AOA tag. - * - * @param[out] tag_id Identification of the tag with the AOA data. - * @param[out] iq Raw IQ samples with some additional info. - * - * @note Won't be called if @ref SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED is 1 - ******************************************************************************/ -void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_iq_report_t *iq); - -/***************************************************************************//** - * Weekly defined function which will be called when an angle report is calculated - * from an AOA tag. - * - * @param[out] tag_id Identification of the tag with the AOA data. - * @param[out] angle Calculated angle - * - * @note Won't be called if @ref SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED is 0 - ******************************************************************************/ -void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, - const sl_bt_aoa_tag_id_t *tag_id, - const aoa_angle_t *angle); - -#ifdef __cplusplus -} -#endif -#endif /* SL_BT_AOA_H */ +/***************************************************************************//** + * @file + * @brief + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef SL_BT_AOA_H +#define SL_BT_AOA_H +#ifdef __cplusplus +extern "C" { +#endif +#include "aoa_util/aoa_types.h" + +//macros ----------------------------------------------------------------------- +//type definitions ------------------------------------------------------------- +typedef struct { + union { + uint8_t mac_addr[6]; //< MAC address of the bluetooth tag. + uint64_t system_id; //< Same as MAC address but in reversed byte order and the last 2 byte will be always 0. + }; +} sl_bt_aoa_tag_id_t; + +//< MAC address of the locator board. (The last 2 byte will be always 0.) +typedef sl_bt_aoa_tag_id_t sl_bt_aoa_locator_id_t; + +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- + +/***************************************************************************//** + * Initializes the BT AOA component. + ******************************************************************************/ +void sl_bt_aoa_init(void); + +/***************************************************************************//** + * Weekly defined function which will be called when an IQ report is received + * from an AOA tag. + * + * @param[out] tag_id Identification of the tag with the AOA data. + * @param[out] iq Raw IQ samples with some additional info. + * + * @note Won't be called if @ref SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED is 1 + ******************************************************************************/ +void sl_bt_aoa_on_iq_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_iq_report_t *iq); + +/***************************************************************************//** + * Weekly defined function which will be called when an angle report is calculated + * from an AOA tag. + * + * @param[out] tag_id Identification of the tag with the AOA data. + * @param[out] angle Calculated angle + * + * @note Won't be called if @ref SL_BT_AOA_CFG_ANGLE_CALCULATION_ENABLED is 0 + ******************************************************************************/ +void sl_bt_aoa_on_angle_report(const sl_bt_aoa_locator_id_t *locator_id, + const sl_bt_aoa_tag_id_t *tag_id, + const aoa_angle_t *angle); + +#ifdef __cplusplus +} +#endif +#endif /* SL_BT_AOA_H */ diff --git a/locator_host/config/SEGGER_RTT_Conf.h b/locator_host/config/SEGGER_RTT_Conf.h index a7e59f4..fe4d15a 100644 --- a/locator_host/config/SEGGER_RTT_Conf.h +++ b/locator_host/config/SEGGER_RTT_Conf.h @@ -1,428 +1,428 @@ -/********************************************************************* - * SEGGER Microcontroller GmbH * - * The Embedded Experts * - ********************************************************************** - * * - * (c) 1995 - 2023 SEGGER Microcontroller GmbH * - * * - * www.segger.com Support: support@segger.com * - * * - ********************************************************************** - * * - * SEGGER SystemView * Real-time application analysis * - * * - ********************************************************************** - * * - * All rights reserved. * - * * - * SEGGER strongly recommends to not make any changes * - * to or modify the source code of this software in order to stay * - * compatible with the SystemView and RTT protocol, and J-Link. * - * * - * Redistribution and use in source and binary forms, with or * - * without modification, are permitted provided that the following * - * condition is met: * - * * - * o Redistributions of source code must retain the above copyright * - * notice, this condition and the following disclaimer. * - * * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * - * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * - * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * - * DAMAGE. * - * * - ********************************************************************** - * * - * SystemView version: 3.52 * - * * - ********************************************************************** - ---------------------------END-OF-HEADER------------------------------ - File : SEGGER_RTT_Conf.h - Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. - Revision: $Rev: 24316 $ - - */ - -#ifndef SEGGER_RTT_CONF_H -#define SEGGER_RTT_CONF_H - -#ifdef __IAR_SYSTEMS_ICC__ - #include -#endif - -/********************************************************************* - * - * Defines, configurable - * - ********************************************************************** - */ - -// -// Take in and set to correct values for Cortex-A systems with CPU cache -// -//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system -//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached -// -// Most common case: -// Up-channel 0: RTT -// Up-channel 1: SystemView -// -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) -#endif -// -// Most common case: -// Down-channel 0: RTT -// Down-channel 1: SystemView -// -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) -#endif - -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) -#endif - -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) -#endif - -#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE - #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) -#endif - -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) -#endif - -/********************************************************************* - * - * RTT memcpy configuration - * - * memcpy() is good for large amounts of data, - * but the overhead is big for small amounts, which are usually stored via RTT. - * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. - * - * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. - * This is may be required with memory access restrictions, - * such as on Cortex-A devices with MMU. - */ -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop -#endif -// -// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets -// -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) -// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) -//#endif - -// -// Target is not allowed to perform other RTT operations while string still has not been stored completely. -// Otherwise we would probably end up with a mixed string in the buffer. -// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. -// -// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. -// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. -// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. -// (Higher priority = lower priority number) -// Default value for embOS: 128u -// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC -// or define SEGGER_RTT_LOCK() to completely disable interrupts. -// -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) -#endif - -/********************************************************************* - * - * RTT lock configuration for SEGGER Embedded Studio, - * Rowley CrossStudio and GCC - */ -#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) - #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, primask \n\t" \ - "movs r1, #1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : "i" (SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : \ - ); \ - } - - #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #elif defined(__riscv) || defined(__riscv_xlen) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("csrr %0, mstatus \n\t" \ - "csrci mstatus, 8 \n\t" \ - "andi %0, %0, 8 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ - "or %0, %0, a1 \n\t" \ - "csrs mstatus, %0 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "a1" \ - ); \ - } - #else - #define SEGGER_RTT_LOCK() - #define SEGGER_RTT_UNLOCK() - #endif -#endif - -/********************************************************************* - * - * RTT lock configuration for IAR EWARM - */ -#ifdef __ICCARM__ - #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) \ - || (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) \ - || (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) \ - || (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) \ - || (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_BASEPRI(); \ - __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ - } - #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) \ - || (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (_SEGGER_RTT__LockState) \ - : \ - : "r1", "cc" \ - ); - - #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (_SEGGER_RTT__LockState) \ - : "r0", "r1", "cc" \ - ); \ - } - #endif -#endif - -/********************************************************************* - * - * RTT lock configuration for IAR RX - */ -#ifdef __ICCRX__ - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* - * - * RTT lock configuration for IAR RL78 - */ -#ifdef __ICCRL78__ - #define SEGGER_RTT_LOCK() { \ - __istate_t _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_interrupt_state(); \ - __disable_interrupt(); - - #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* - * - * RTT lock configuration for KEIL ARM - */ -#ifdef __CC_ARM - #if (defined __TARGET_ARCH_6S_M) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char _SEGGER_RTT__PRIMASK __asm("primask"); \ - _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ - _SEGGER_RTT__PRIMASK = 1u; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - register unsigned char BASEPRI __asm("basepri"); \ - _SEGGER_RTT__LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ - __schedule_barrier(); - - #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ - __schedule_barrier(); \ - } - #endif -#endif - -/********************************************************************* - * - * RTT lock configuration for TI ARM - */ -#ifdef __TI_ARM__ - #if defined (__TI_ARM_V6M0__) - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = __get_PRIMASK(); \ - __set_PRIMASK(1); - - #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ - } - #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) - #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) - #endif - #define SEGGER_RTT_LOCK() { \ - unsigned int _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); - - #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ - } - #endif -#endif - -/********************************************************************* - * - * RTT lock configuration for CCRX - */ -#ifdef __RX - #include - #define SEGGER_RTT_LOCK() { \ - unsigned long _SEGGER_RTT__LockState; \ - _SEGGER_RTT__LockState = get_psw() & 0x010000; \ - clrpsw_i(); - - #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ - } -#endif - -/********************************************************************* - * - * RTT lock configuration for embOS Simulation on Windows - * (Can also be used for generic RTT locking with embOS) - */ -#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) - -void OS_SIM_EnterCriticalSection(void); -void OS_SIM_LeaveCriticalSection(void); - -#define SEGGER_RTT_LOCK() { \ - OS_SIM_EnterCriticalSection(); - -#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ - } -#endif - -/********************************************************************* - * - * RTT lock configuration fallback - */ -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) -#endif - -#endif -/*************************** End of file ****************************/ +/********************************************************************* + * SEGGER Microcontroller GmbH * + * The Embedded Experts * + ********************************************************************** + * * + * (c) 1995 - 2023 SEGGER Microcontroller GmbH * + * * + * www.segger.com Support: support@segger.com * + * * + ********************************************************************** + * * + * SEGGER SystemView * Real-time application analysis * + * * + ********************************************************************** + * * + * All rights reserved. * + * * + * SEGGER strongly recommends to not make any changes * + * to or modify the source code of this software in order to stay * + * compatible with the SystemView and RTT protocol, and J-Link. * + * * + * Redistribution and use in source and binary forms, with or * + * without modification, are permitted provided that the following * + * condition is met: * + * * + * o Redistributions of source code must retain the above copyright * + * notice, this condition and the following disclaimer. * + * * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * + * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * + * DAMAGE. * + * * + ********************************************************************** + * * + * SystemView version: 3.52 * + * * + ********************************************************************** + ---------------------------END-OF-HEADER------------------------------ + File : SEGGER_RTT_Conf.h + Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. + Revision: $Rev: 24316 $ + + */ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __IAR_SYSTEMS_ICC__ + #include +#endif + +/********************************************************************* + * + * Defines, configurable + * + ********************************************************************** + */ + +// +// Take in and set to correct values for Cortex-A systems with CPU cache +// +//#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system +//#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached +// +// Most common case: +// Up-channel 0: RTT +// Up-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) +#endif +// +// Most common case: +// Down-channel 0: RTT +// Down-channel 1: SystemView +// +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN (1024) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#endif + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#endif + +/********************************************************************* + * + * RTT memcpy configuration + * + * memcpy() is good for large amounts of data, + * but the overhead is big for small amounts, which are usually stored via RTT. + * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. + * + * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. + * This is may be required with memory access restrictions, + * such as on Cortex-A devices with MMU. + */ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop +#endif +// +// Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets +// +//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) +//#endif + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +// SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. +// Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. +// When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. +// (Higher priority = lower priority number) +// Default value for embOS: 128u +// Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +// In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC +// or define SEGGER_RTT_LOCK() to completely disable interrupts. +// +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#endif + +/********************************************************************* + * + * RTT lock configuration for SEGGER Embedded Studio, + * Rowley CrossStudio and GCC + */ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, primask \n\t" \ + "movs r1, #1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : "i" (SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #elif defined(__riscv) || defined(__riscv_xlen) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "a1" \ + ); \ + } + #else + #define SEGGER_RTT_LOCK() + #define SEGGER_RTT_UNLOCK() + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR EWARM + */ +#ifdef __ICCARM__ + #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) \ + || (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) \ + || (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) \ + || (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) \ + || (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_BASEPRI(); \ + __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ + } + #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) \ + || (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + __asm volatile ("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r" (_SEGGER_RTT__LockState) \ + : \ + : "r1", "cc" \ + ); + + #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r" (_SEGGER_RTT__LockState) \ + : "r0", "r1", "cc" \ + ); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RX + */ +#ifdef __ICCRX__ + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for IAR RL78 + */ +#ifdef __ICCRL78__ + #define SEGGER_RTT_LOCK() { \ + __istate_t _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_interrupt_state(); \ + __disable_interrupt(); + + #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for KEIL ARM + */ +#ifdef __CC_ARM + #if (defined __TARGET_ARCH_6S_M) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char _SEGGER_RTT__PRIMASK __asm("primask"); \ + _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ + _SEGGER_RTT__PRIMASK = 1u; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + register unsigned char BASEPRI __asm("basepri"); \ + _SEGGER_RTT__LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ + __schedule_barrier(); + + #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ + __schedule_barrier(); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for TI ARM + */ +#ifdef __TI_ARM__ + #if defined (__TI_ARM_V6M0__) + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = __get_PRIMASK(); \ + __set_PRIMASK(1); + + #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ + } + #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) + #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY + #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) + #endif + #define SEGGER_RTT_LOCK() { \ + unsigned int _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); + + #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ + } + #endif +#endif + +/********************************************************************* + * + * RTT lock configuration for CCRX + */ +#ifdef __RX + #include + #define SEGGER_RTT_LOCK() { \ + unsigned long _SEGGER_RTT__LockState; \ + _SEGGER_RTT__LockState = get_psw() & 0x010000; \ + clrpsw_i(); + + #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration for embOS Simulation on Windows + * (Can also be used for generic RTT locking with embOS) + */ +#if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) + +void OS_SIM_EnterCriticalSection(void); +void OS_SIM_LeaveCriticalSection(void); + +#define SEGGER_RTT_LOCK() { \ + OS_SIM_EnterCriticalSection(); + +#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ + } +#endif + +/********************************************************************* + * + * RTT lock configuration fallback + */ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/locator_host/config/app_assert_config.h b/locator_host/config/app_assert_config.h index 81d60f1..2256435 100644 --- a/locator_host/config/app_assert_config.h +++ b/locator_host/config/app_assert_config.h @@ -1,54 +1,54 @@ -/***************************************************************************//** - * @file - * @brief Application assert configuration - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_ASSERT_CONFIG_H -#define APP_ASSERT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Assert component -// Enables Assert. -#define APP_ASSERT_ENABLE 1 - -// Logging -// Enables logging for assert. -#define APP_ASSERT_LOG_ENABLE 1 - -// Enable trace -// Enables trace for assert. -#define APP_ASSERT_TRACE_ENABLE 1 - -// - -// - -// <<< end of configuration section >>> - -#endif // APP_ASSERT_CONFIG_H +/***************************************************************************//** + * @file + * @brief Application assert configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_ASSERT_CONFIG_H +#define APP_ASSERT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Assert component +// Enables Assert. +#define APP_ASSERT_ENABLE 1 + +// Logging +// Enables logging for assert. +#define APP_ASSERT_LOG_ENABLE 1 + +// Enable trace +// Enables trace for assert. +#define APP_ASSERT_TRACE_ENABLE 1 + +// + +// + +// <<< end of configuration section >>> + +#endif // APP_ASSERT_CONFIG_H diff --git a/locator_host/config/btconf/gatt_configuration.btconf b/locator_host/config/btconf/gatt_configuration.btconf index 5eea779..e94936f 100644 --- a/locator_host/config/btconf/gatt_configuration.btconf +++ b/locator_host/config/btconf/gatt_configuration.btconf @@ -1,33 +1,33 @@ - - - - - Abstract: The generic_access service contains generic information about the device. All available Characteristics are readonly. - - - Empty Example - - - - Abstract: The external appearance of this device. The values are composed of a category (10-bits) and sub-categories (6-bits). - 0000 - - - - - Abstract: The Device Information Service exposes manufacturer and/or vendor information about a device. Summary: This service exposes manufacturer information about a device. The Device Information Service is instantiated as a Primary Service. Only one instance of the Device Information Service is exposed on a device. - - Abstract: The value of this characteristic is a UTF-8 string representing the name of the manufacturer of the device. - Silicon Labs - - - - - - Abstract: The SYSTEM ID characteristic consists of a structure with two fields. The first field are the LSOs and the second field contains the MSOs. This is a 64-bit structure which consists of a 40-bit manufacturer-defined identifier concatenated with a 24 bit unique Organizationally Unique Identifier (OUI). The OUI is issued by the IEEE Registration Authority (http://standards.ieee.org/regauth/index.html) and is required to be used in accordance with IEEE Standard 802-2001.6 while the least significant 40 bits are manufacturer defined. If System ID generated based on a Bluetooth Device Address, it is required to be done as follows. System ID and the Bluetooth Device Address have a very similar structure: a Bluetooth Device Address is 48 bits in length and consists of a 24 bit Company Assigned Identifier (manufacturer defined identifier) concatenated with a 24 bit Company Identifier (OUI). In order to encapsulate a Bluetooth Device Address as System ID, the Company Identifier is concatenated with 0xFFFE followed by the Company Assigned Identifier of the Bluetooth Address. For more guidelines related to EUI-64, refer to http://standards.ieee.org/develop/regauth/tut/eui64.pdf. Examples: If the system ID is based of a Bluetooth Device Address with a Company Identifier (OUI) is 0x123456 and the Company Assigned Identifier is 0x9ABCDE, then the System Identifier is required to be 0x123456FFFE9ABCDE. - - - - - - + + + + + Abstract: The generic_access service contains generic information about the device. All available Characteristics are readonly. + + + Empty Example + + + + Abstract: The external appearance of this device. The values are composed of a category (10-bits) and sub-categories (6-bits). + 0000 + + + + + Abstract: The Device Information Service exposes manufacturer and/or vendor information about a device. Summary: This service exposes manufacturer information about a device. The Device Information Service is instantiated as a Primary Service. Only one instance of the Device Information Service is exposed on a device. + + Abstract: The value of this characteristic is a UTF-8 string representing the name of the manufacturer of the device. + Silicon Labs + + + + + + Abstract: The SYSTEM ID characteristic consists of a structure with two fields. The first field are the LSOs and the second field contains the MSOs. This is a 64-bit structure which consists of a 40-bit manufacturer-defined identifier concatenated with a 24 bit unique Organizationally Unique Identifier (OUI). The OUI is issued by the IEEE Registration Authority (http://standards.ieee.org/regauth/index.html) and is required to be used in accordance with IEEE Standard 802-2001.6 while the least significant 40 bits are manufacturer defined. If System ID generated based on a Bluetooth Device Address, it is required to be done as follows. System ID and the Bluetooth Device Address have a very similar structure: a Bluetooth Device Address is 48 bits in length and consists of a 24 bit Company Assigned Identifier (manufacturer defined identifier) concatenated with a 24 bit Company Identifier (OUI). In order to encapsulate a Bluetooth Device Address as System ID, the Company Identifier is concatenated with 0xFFFE followed by the Company Assigned Identifier of the Bluetooth Address. For more guidelines related to EUI-64, refer to http://standards.ieee.org/develop/regauth/tut/eui64.pdf. Examples: If the system ID is based of a Bluetooth Device Address with a Company Identifier (OUI) is 0x123456 and the Company Assigned Identifier is 0x9ABCDE, then the System Identifier is required to be 0x123456FFFE9ABCDE. + + + + + + diff --git a/locator_host/config/dmadrv_config.h b/locator_host/config/dmadrv_config.h index ed105e4..f113d72 100644 --- a/locator_host/config/dmadrv_config.h +++ b/locator_host/config/dmadrv_config.h @@ -1,26 +1,26 @@ -#ifndef DMADRV_CONFIG_H -#define DMADRV_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMA interrupt priority <0-15> -// Priority of the DMA interrupt. Smaller number equals higher priority. -// Default: 8 -#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 8 - -// Number of available channels <1-8> -// Number of DMA channels supported by the driver. A lower channel count -// will reduce RAM memory footprint. The default is to support all channels -// on the device. -// Default: 8 -#define EMDRV_DMADRV_DMA_CH_COUNT 8 - -// Number of fixed priority channels -// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, -// and channels [CH_PRIORITY, CH_COUNT] as round-robin. -// Default: 0 -#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 - -// <<< end of configuration section >>> - -#endif // DMADRV_CONFIG_H +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-15> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 8 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 8 + +// Number of available channels <1-8> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 8 +#define EMDRV_DMADRV_DMA_CH_COUNT 8 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/locator_host/config/emlib_core_debug_config.h b/locator_host/config/emlib_core_debug_config.h index 07ee9b9..13e4b91 100644 --- a/locator_host/config/emlib_core_debug_config.h +++ b/locator_host/config/emlib_core_debug_config.h @@ -1,45 +1,45 @@ -/***************************************************************************//** - * @file - * @brief emlib_core Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CORE_DEBUG_CONFIG_H -#define EM_CORE_DEBUG_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Core Configuration - -// Enables measuring of interrupt disable time for debugging purposes. -// Default: 0 -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 - -// - -// <<< end of configuration section >>> -#endif // EM_CORE_CONFIG_H +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/locator_host/config/pin_config.h b/locator_host/config/pin_config.h index e0dce7b..7ac68fc 100644 --- a/locator_host/config/pin_config.h +++ b/locator_host/config/pin_config.h @@ -1,186 +1,186 @@ -#ifndef PIN_CONFIG_H -#define PIN_CONFIG_H - -// $[CMU] -// [CMU]$ - -// $[LFXO] -// LFXO LFXTAL_I on PD01 -#ifndef LFXO_LFXTAL_I_PORT -#define LFXO_LFXTAL_I_PORT gpioPortD -#endif -#ifndef LFXO_LFXTAL_I_PIN -#define LFXO_LFXTAL_I_PIN 1 -#endif - -// LFXO LFXTAL_O on PD00 -#ifndef LFXO_LFXTAL_O_PORT -#define LFXO_LFXTAL_O_PORT gpioPortD -#endif -#ifndef LFXO_LFXTAL_O_PIN -#define LFXO_LFXTAL_O_PIN 0 -#endif - -// [LFXO]$ - -// $[PRS.ASYNCH0] -// [PRS.ASYNCH0]$ - -// $[PRS.ASYNCH1] -// [PRS.ASYNCH1]$ - -// $[PRS.ASYNCH2] -// [PRS.ASYNCH2]$ - -// $[PRS.ASYNCH3] -// [PRS.ASYNCH3]$ - -// $[PRS.ASYNCH4] -// [PRS.ASYNCH4]$ - -// $[PRS.ASYNCH5] -// [PRS.ASYNCH5]$ - -// $[PRS.ASYNCH6] -// [PRS.ASYNCH6]$ - -// $[PRS.ASYNCH7] -// [PRS.ASYNCH7]$ - -// $[PRS.ASYNCH8] -// [PRS.ASYNCH8]$ - -// $[PRS.ASYNCH9] -// [PRS.ASYNCH9]$ - -// $[PRS.ASYNCH10] -// [PRS.ASYNCH10]$ - -// $[PRS.ASYNCH11] -// [PRS.ASYNCH11]$ - -// $[PRS.ASYNCH12] -// [PRS.ASYNCH12]$ - -// $[PRS.ASYNCH13] -// [PRS.ASYNCH13]$ - -// $[PRS.ASYNCH14] -// [PRS.ASYNCH14]$ - -// $[PRS.ASYNCH15] -// [PRS.ASYNCH15]$ - -// $[PRS.SYNCH0] -// [PRS.SYNCH0]$ - -// $[PRS.SYNCH1] -// [PRS.SYNCH1]$ - -// $[PRS.SYNCH2] -// [PRS.SYNCH2]$ - -// $[PRS.SYNCH3] -// [PRS.SYNCH3]$ - -// $[GPIO] -// GPIO SWV on PA03 -#ifndef GPIO_SWV_PORT -#define GPIO_SWV_PORT gpioPortA -#endif -#ifndef GPIO_SWV_PIN -#define GPIO_SWV_PIN 3 -#endif - -// [GPIO]$ - -// $[TIMER0] -// [TIMER0]$ - -// $[TIMER1] -// [TIMER1]$ - -// $[TIMER2] -// [TIMER2]$ - -// $[TIMER3] -// [TIMER3]$ - -// $[TIMER4] -// [TIMER4]$ - -// $[USART0] -// USART0 RX on PA09 -#ifndef USART0_RX_PORT -#define USART0_RX_PORT gpioPortA -#endif -#ifndef USART0_RX_PIN -#define USART0_RX_PIN 9 -#endif - -// USART0 TX on PA08 -#ifndef USART0_TX_PORT -#define USART0_TX_PORT gpioPortA -#endif -#ifndef USART0_TX_PIN -#define USART0_TX_PIN 8 -#endif - -// [USART0]$ - -// $[I2C1] -// [I2C1]$ - -// $[EUSART1] -// [EUSART1]$ - -// $[KEYSCAN] -// [KEYSCAN]$ - -// $[LETIMER0] -// [LETIMER0]$ - -// $[IADC0] -// [IADC0]$ - -// $[ACMP0] -// [ACMP0]$ - -// $[ACMP1] -// [ACMP1]$ - -// $[VDAC0] -// [VDAC0]$ - -// $[VDAC1] -// [VDAC1]$ - -// $[PCNT0] -// [PCNT0]$ - -// $[HFXO0] -// [HFXO0]$ - -// $[I2C0] -// [I2C0]$ - -// $[EUSART0] -// [EUSART0]$ - -// $[PTI] -// [PTI]$ - -// $[MODEM] -// [MODEM]$ - -// $[CUSTOM_PIN_NAME] -#ifndef _PORT -#define _PORT gpioPortA -#endif -#ifndef _PIN -#define _PIN 0 -#endif - -// [CUSTOM_PIN_NAME]$ - -#endif // PIN_CONFIG_H +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[CMU] +// [CMU]$ + +// $[LFXO] +// LFXO LFXTAL_I on PD01 +#ifndef LFXO_LFXTAL_I_PORT +#define LFXO_LFXTAL_I_PORT gpioPortD +#endif +#ifndef LFXO_LFXTAL_I_PIN +#define LFXO_LFXTAL_I_PIN 1 +#endif + +// LFXO LFXTAL_O on PD00 +#ifndef LFXO_LFXTAL_O_PORT +#define LFXO_LFXTAL_O_PORT gpioPortD +#endif +#ifndef LFXO_LFXTAL_O_PIN +#define LFXO_LFXTAL_O_PIN 0 +#endif + +// [LFXO]$ + +// $[PRS.ASYNCH0] +// [PRS.ASYNCH0]$ + +// $[PRS.ASYNCH1] +// [PRS.ASYNCH1]$ + +// $[PRS.ASYNCH2] +// [PRS.ASYNCH2]$ + +// $[PRS.ASYNCH3] +// [PRS.ASYNCH3]$ + +// $[PRS.ASYNCH4] +// [PRS.ASYNCH4]$ + +// $[PRS.ASYNCH5] +// [PRS.ASYNCH5]$ + +// $[PRS.ASYNCH6] +// [PRS.ASYNCH6]$ + +// $[PRS.ASYNCH7] +// [PRS.ASYNCH7]$ + +// $[PRS.ASYNCH8] +// [PRS.ASYNCH8]$ + +// $[PRS.ASYNCH9] +// [PRS.ASYNCH9]$ + +// $[PRS.ASYNCH10] +// [PRS.ASYNCH10]$ + +// $[PRS.ASYNCH11] +// [PRS.ASYNCH11]$ + +// $[PRS.ASYNCH12] +// [PRS.ASYNCH12]$ + +// $[PRS.ASYNCH13] +// [PRS.ASYNCH13]$ + +// $[PRS.ASYNCH14] +// [PRS.ASYNCH14]$ + +// $[PRS.ASYNCH15] +// [PRS.ASYNCH15]$ + +// $[PRS.SYNCH0] +// [PRS.SYNCH0]$ + +// $[PRS.SYNCH1] +// [PRS.SYNCH1]$ + +// $[PRS.SYNCH2] +// [PRS.SYNCH2]$ + +// $[PRS.SYNCH3] +// [PRS.SYNCH3]$ + +// $[GPIO] +// GPIO SWV on PA03 +#ifndef GPIO_SWV_PORT +#define GPIO_SWV_PORT gpioPortA +#endif +#ifndef GPIO_SWV_PIN +#define GPIO_SWV_PIN 3 +#endif + +// [GPIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[USART0] +// USART0 RX on PA09 +#ifndef USART0_RX_PORT +#define USART0_RX_PORT gpioPortA +#endif +#ifndef USART0_RX_PIN +#define USART0_RX_PIN 9 +#endif + +// USART0 TX on PA08 +#ifndef USART0_TX_PORT +#define USART0_TX_PORT gpioPortA +#endif +#ifndef USART0_TX_PIN +#define USART0_TX_PIN 8 +#endif + +// [USART0]$ + +// $[I2C1] +// [I2C1]$ + +// $[EUSART1] +// [EUSART1]$ + +// $[KEYSCAN] +// [KEYSCAN]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[IADC0] +// [IADC0]$ + +// $[ACMP0] +// [ACMP0]$ + +// $[ACMP1] +// [ACMP1]$ + +// $[VDAC0] +// [VDAC0]$ + +// $[VDAC1] +// [VDAC1]$ + +// $[PCNT0] +// [PCNT0]$ + +// $[HFXO0] +// [HFXO0]$ + +// $[I2C0] +// [I2C0]$ + +// $[EUSART0] +// [EUSART0]$ + +// $[PTI] +// [PTI]$ + +// $[MODEM] +// [MODEM]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT gpioPortA +#endif +#ifndef _PIN +#define _PIN 0 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/locator_host/config/sl_board_control_config.h b/locator_host/config/sl_board_control_config.h index a3a41d8..33b1f77 100644 --- a/locator_host/config/sl_board_control_config.h +++ b/locator_host/config/sl_board_control_config.h @@ -1,88 +1,88 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 0 - -// Enable Relative Humidity and Temperature sensor -// Default: 0 -#define SL_BOARD_ENABLE_SENSOR_RHT 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#ifndef SL_BOARD_ENABLE_VCOM_PORT -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB -#endif -#ifndef SL_BOARD_ENABLE_VCOM_PIN -#define SL_BOARD_ENABLE_VCOM_PIN 0 -#endif -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#ifndef SL_BOARD_ENABLE_DISPLAY_PORT -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC -#endif -#ifndef SL_BOARD_ENABLE_DISPLAY_PIN -#define SL_BOARD_ENABLE_DISPLAY_PIN 9 -#endif -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// SL_BOARD_ENABLE_SENSOR_RHT -// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] -#ifndef SL_BOARD_ENABLE_SENSOR_RHT_PORT -#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD -#endif -#ifndef SL_BOARD_ENABLE_SENSOR_RHT_PIN -#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 -#endif -// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Enable Relative Humidity and Temperature sensor +// Default: 0 +#define SL_BOARD_ENABLE_SENSOR_RHT 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#ifndef SL_BOARD_ENABLE_VCOM_PORT +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#endif +#ifndef SL_BOARD_ENABLE_VCOM_PIN +#define SL_BOARD_ENABLE_VCOM_PIN 0 +#endif +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#ifndef SL_BOARD_ENABLE_DISPLAY_PORT +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortC +#endif +#ifndef SL_BOARD_ENABLE_DISPLAY_PIN +#define SL_BOARD_ENABLE_DISPLAY_PIN 9 +#endif +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// SL_BOARD_ENABLE_SENSOR_RHT +// $[GPIO_SL_BOARD_ENABLE_SENSOR_RHT] +#ifndef SL_BOARD_ENABLE_SENSOR_RHT_PORT +#define SL_BOARD_ENABLE_SENSOR_RHT_PORT gpioPortD +#endif +#ifndef SL_BOARD_ENABLE_SENSOR_RHT_PIN +#define SL_BOARD_ENABLE_SENSOR_RHT_PIN 3 +#endif +// [GPIO_SL_BOARD_ENABLE_SENSOR_RHT]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/locator_host/config/sl_debug_swo_config.h b/locator_host/config/sl_debug_swo_config.h index 56c90a9..5e4aa49 100644 --- a/locator_host/config/sl_debug_swo_config.h +++ b/locator_host/config/sl_debug_swo_config.h @@ -1,106 +1,106 @@ -/***************************************************************************//** - * @file - * @brief SWO configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEBUG_SWO_CONFIG_H -#define SL_DEBUG_SWO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO Configuration - -// SWO Frequency -// Must be 875 kHz for communication with Silicon Labs debuggers -// Default: 875000 -#define SL_DEBUG_SWO_FREQ 875000 - -// Enable interrupt event trace -// Default: 0 -#define SL_DEBUG_SWO_SAMPLE_IRQ 0 - -// Enable Program Counter samples -// Default: 0 -#define SL_DEBUG_SWO_SAMPLE_PC 0 - -// SWO debug sample intervals -// <64=> 64 -// <128=> 128 -// <192=> 192 -// <256=> 256 -// <320=> 320 -// <384=> 384 -// <448=> 448 -// <512=> 512 -// <576=> 576 -// <640=> 640 -// <704=> 704 -// <768=> 768 -// <832=> 832 -// <896=> 896 -// <960=> 960 -// <1024=> 1024 -// <2048=> 2048 -// <3072=> 3072 -// <4096=> 4096 -// <5102=> 5102 -// <6144=> 6144 -// <7168=> 7168 -// <8192=> 8192 -// <9216=> 9216 -// <10240=> 10240 -// <11264=> 11264 -// <12288=> 12288 -// <13312=> 13312 -// <14336=> 14336 -// <15360=> 15360 -// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 -// Default: 15360 -#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_DEBUG -// $[GPIO_SL_DEBUG] -#ifndef SL_DEBUG_PERIPHERAL -#define SL_DEBUG_PERIPHERAL GPIO -#endif - -// GPIO SWV on PA03 -#ifndef SL_DEBUG_SWV_PORT -#define SL_DEBUG_SWV_PORT gpioPortA -#endif -#ifndef SL_DEBUG_SWV_PIN -#define SL_DEBUG_SWV_PIN 3 -#endif -// [GPIO_SL_DEBUG]$ -// <<< sl:end pin_tool >>> - -#endif // SL_DEBUG_SWO_CONFIG_H +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[GPIO_SL_DEBUG] +#ifndef SL_DEBUG_PERIPHERAL +#define SL_DEBUG_PERIPHERAL GPIO +#endif + +// GPIO SWV on PA03 +#ifndef SL_DEBUG_SWV_PORT +#define SL_DEBUG_SWV_PORT gpioPortA +#endif +#ifndef SL_DEBUG_SWV_PIN +#define SL_DEBUG_SWV_PIN 3 +#endif +// [GPIO_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/locator_host/config/sl_device_init_dcdc_config.h b/locator_host/config/sl_device_init_dcdc_config.h index 695e68e..6e496b2 100644 --- a/locator_host/config/sl_device_init_dcdc_config.h +++ b/locator_host/config/sl_device_init_dcdc_config.h @@ -1,58 +1,58 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DCDC Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H -#define SL_DEVICE_INIT_DCDC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable DC/DC Converter -// -// Default: 1 -#define SL_DEVICE_INIT_DCDC_ENABLE 1 - -// Set DC/DC Converter in Bypass Mode -// -// Default: 0 -#define SL_DEVICE_INIT_DCDC_BYPASS 0 - -// Override for DCDC PFMX Mode Peak Current Setting -// -// Default: 1 -#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 - -// DCDC PFMX Mode Peak Current Setting <0-15> -// -// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT -#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 9 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DCDC_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 1 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL 9 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/locator_host/config/sl_device_init_dpll_config.h b/locator_host/config/sl_device_init_dpll_config.h index eea3705..3aa46da 100644 --- a/locator_host/config/sl_device_init_dpll_config.h +++ b/locator_host/config/sl_device_init_dpll_config.h @@ -1,83 +1,83 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DPLL Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H -#define SL_DEVICE_INIT_DPLL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Target Frequency <1000000-80000000> -// DPLL target frequency -// Default: 78000000 -#define SL_DEVICE_INIT_DPLL_FREQ 78000000 - -// Numerator (N) <300-4095> -// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 3839 -#define SL_DEVICE_INIT_DPLL_N 3839 - -// Denominator (M) <0-4095> -// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) -// Default: 1919 -#define SL_DEVICE_INIT_DPLL_M 1919 - -// Reference Clock -// Reference clock source for DPLL -// HFXO -// LFXO -// CLKIN0 -// Default: cmuSelect_HFXO -#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO - -// Reference Clock Edge Detect -// Edge detection for reference clock -// Falling Edge -// Rising Edge -// Default: cmuDPLLEdgeSel_Fall -#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall - -// DPLL Lock Mode -// Lock mode -// Frequency-Lock Loop -// Phase-Lock Loop -// Default: cmuDPLLLockMode_Freq -#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase - -// Automatic Lock Recovery -// Default: 1 -#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 - -// Enable Dither -// Default: 0 -#define SL_DEVICE_INIT_DPLL_DITHER 0 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DPLL_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DPLL Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DPLL_CONFIG_H +#define SL_DEVICE_INIT_DPLL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Target Frequency <1000000-80000000> +// DPLL target frequency +// Default: 78000000 +#define SL_DEVICE_INIT_DPLL_FREQ 78000000 + +// Numerator (N) <300-4095> +// Value of N for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 3839 +#define SL_DEVICE_INIT_DPLL_N 3839 + +// Denominator (M) <0-4095> +// Value of M for output frequency calculation fout = fref * (N+1) / (M+1) +// Default: 1919 +#define SL_DEVICE_INIT_DPLL_M 1919 + +// Reference Clock +// Reference clock source for DPLL +// HFXO +// LFXO +// CLKIN0 +// Default: cmuSelect_HFXO +#define SL_DEVICE_INIT_DPLL_REFCLK cmuSelect_HFXO + +// Reference Clock Edge Detect +// Edge detection for reference clock +// Falling Edge +// Rising Edge +// Default: cmuDPLLEdgeSel_Fall +#define SL_DEVICE_INIT_DPLL_EDGE cmuDPLLEdgeSel_Fall + +// DPLL Lock Mode +// Lock mode +// Frequency-Lock Loop +// Phase-Lock Loop +// Default: cmuDPLLLockMode_Freq +#define SL_DEVICE_INIT_DPLL_LOCKMODE cmuDPLLLockMode_Phase + +// Automatic Lock Recovery +// Default: 1 +#define SL_DEVICE_INIT_DPLL_AUTORECOVER 1 + +// Enable Dither +// Default: 0 +#define SL_DEVICE_INIT_DPLL_DITHER 0 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DPLL_CONFIG_H diff --git a/locator_host/config/sl_device_init_emu_config.h b/locator_host/config/sl_device_init_emu_config.h index 4ac96ba..dc9cedc 100644 --- a/locator_host/config/sl_device_init_emu_config.h +++ b/locator_host/config/sl_device_init_emu_config.h @@ -1,53 +1,53 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_EMU Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_EMU_CONFIG_H -#define SL_DEVICE_INIT_EMU_CONFIG_H - -#include "em_emu.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Allow debugger to remain connected in EM2 -// Force PD0B to stay on on EM2 entry. This allows the debugger to remain connected in EM2 and EM3. -// Enabling debug connectivity results in an increased power consumption in EM2/EM3. -// Default: 1 -#define SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE 1 - -// EM4 pin retention mode -// No Retention: Pads enter reset state when entering EM4. -// Retention through EM4: Pads enter reset state when exiting EM4. -// Retention through EM4 and wakeup. -// Default: emuPinRetentionDisable -#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_EMU_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_EMU Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_EMU_CONFIG_H +#define SL_DEVICE_INIT_EMU_CONFIG_H + +#include "em_emu.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Allow debugger to remain connected in EM2 +// Force PD0B to stay on on EM2 entry. This allows the debugger to remain connected in EM2 and EM3. +// Enabling debug connectivity results in an increased power consumption in EM2/EM3. +// Default: 1 +#define SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE 1 + +// EM4 pin retention mode +// No Retention: Pads enter reset state when entering EM4. +// Retention through EM4: Pads enter reset state when exiting EM4. +// Retention through EM4 and wakeup. +// Default: emuPinRetentionDisable +#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_EMU_CONFIG_H diff --git a/locator_host/config/sl_device_init_hfxo_config.h b/locator_host/config/sl_device_init_hfxo_config.h index 9f3b31e..8d2abf5 100644 --- a/locator_host/config/sl_device_init_hfxo_config.h +++ b/locator_host/config/sl_device_init_hfxo_config.h @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 39000000 -#define SL_DEVICE_INIT_HFXO_FREQ 39000000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 95 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 39000000 +#define SL_DEVICE_INIT_HFXO_FREQ 39000000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 95 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/locator_host/config/sl_device_init_lfxo_config.h b/locator_host/config/sl_device_init_lfxo_config.h index 26d3227..43db6f9 100644 --- a/locator_host/config/sl_device_init_lfxo_config.h +++ b/locator_host/config/sl_device_init_lfxo_config.h @@ -1,93 +1,93 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 44 - -// LFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_LFXO_PRECISION 50 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_DEVICE_INIT_LFXO -// $[LFXO_SL_DEVICE_INIT_LFXO] -#ifndef SL_DEVICE_INIT_LFXO_PERIPHERAL -#define SL_DEVICE_INIT_LFXO_PERIPHERAL LFXO -#endif - -// LFXO LFXTAL_O on PD00 -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT -#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT gpioPortD -#endif -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN -#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN 0 -#endif - -// LFXO LFXTAL_I on PD01 -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT -#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT gpioPortD -#endif -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN -#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN 1 -#endif - -// [LFXO_SL_DEVICE_INIT_LFXO]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 44 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEVICE_INIT_LFXO +// $[LFXO_SL_DEVICE_INIT_LFXO] +#ifndef SL_DEVICE_INIT_LFXO_PERIPHERAL +#define SL_DEVICE_INIT_LFXO_PERIPHERAL LFXO +#endif + +// LFXO LFXTAL_O on PD00 +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT +#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT gpioPortD +#endif +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN +#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN 0 +#endif + +// LFXO LFXTAL_I on PD01 +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT +#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT gpioPortD +#endif +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN +#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN 1 +#endif + +// [LFXO_SL_DEVICE_INIT_LFXO]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/locator_host/config/sl_driver_mvp_config.h b/locator_host/config/sl_driver_mvp_config.h index 8ca03b7..d94d9f9 100644 --- a/locator_host/config/sl_driver_mvp_config.h +++ b/locator_host/config/sl_driver_mvp_config.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief MVP Driver configuration file. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_DRIVER_MVP_CONFIG_H -#define SL_DRIVER_MVP_CONFIG_H - -// Use DMA to load MVP programs -// Enable or disable DMA for loading MVP programs. -// Default: 0 -#define SL_MVP_ENABLE_DMA 0 - -// DMA channel to use when DMA is enabled <0-7> -// DMA channel to use when DMA is enabled -// Default: 0 -#define SL_MVP_DMA_CHANNEL 0 - -// CPU power mode during MVP execution. -// The power mode configuration controls what software should -// do when waiting for an MVP program to finish execution. -// -// <0=> No sleep -// <1=> Enter EM1 -// <2=> Yield RTOS thread -// -// When "No sleep" option is used the MCU core will busy-wait for the MVP -// to finish, this is the option which provides the fastest MVP execution -// time. The "No sleep" option can be used in a bare-metal application or -// an application using RTOS. -// When "Enter EM1" option is used the MCU will be put into EM1 whenever -// the driver waits for an MVP program to complete. The "Enter EM1" option -// is not safe to use in an application using RTOS. -// When "Yield RTOS thread" option is used the task waiting for the MVP -// program to complete will yield, allowing other tasks in the system to -// run or potentially let the scheduler put the system into a sleep mode. -// The "Yield RTOS thread" requires that the application is using RTOS. -// Default: 0 -#define SL_MVP_POWER_MODE 0 - -#endif /* SL_DRIVER_MVP_CONFIG_H */ - -// <<< end of configuration section >>> +/***************************************************************************//** + * @file + * @brief MVP Driver configuration file. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_DRIVER_MVP_CONFIG_H +#define SL_DRIVER_MVP_CONFIG_H + +// Use DMA to load MVP programs +// Enable or disable DMA for loading MVP programs. +// Default: 0 +#define SL_MVP_ENABLE_DMA 0 + +// DMA channel to use when DMA is enabled <0-7> +// DMA channel to use when DMA is enabled +// Default: 0 +#define SL_MVP_DMA_CHANNEL 0 + +// CPU power mode during MVP execution. +// The power mode configuration controls what software should +// do when waiting for an MVP program to finish execution. +// +// <0=> No sleep +// <1=> Enter EM1 +// <2=> Yield RTOS thread +// +// When "No sleep" option is used the MCU core will busy-wait for the MVP +// to finish, this is the option which provides the fastest MVP execution +// time. The "No sleep" option can be used in a bare-metal application or +// an application using RTOS. +// When "Enter EM1" option is used the MCU will be put into EM1 whenever +// the driver waits for an MVP program to complete. The "Enter EM1" option +// is not safe to use in an application using RTOS. +// When "Yield RTOS thread" option is used the task waiting for the MVP +// program to complete will yield, allowing other tasks in the system to +// run or potentially let the scheduler put the system into a sleep mode. +// The "Yield RTOS thread" requires that the application is using RTOS. +// Default: 0 +#define SL_MVP_POWER_MODE 0 + +#endif /* SL_DRIVER_MVP_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/locator_host/config/sl_memory_config.h b/locator_host/config/sl_memory_config.h index 976c70f..55b023c 100644 --- a/locator_host/config/sl_memory_config.h +++ b/locator_host/config/sl_memory_config.h @@ -1,28 +1,28 @@ -#ifndef SL_MEMORY_CONFIG_H -#define SL_MEMORY_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Memory configuration - -// Stack size for the application. -// Default: 4096 -// The stack size configured here will be used by the stack that the -// application uses when coming out of a reset. -#ifndef SL_STACK_SIZE - #define SL_STACK_SIZE 8192 -#endif - -// Minimum heap size for the application. -// Default: 2048 -// Note that this value will configure the c heap which is normally used by -// malloc() and free() from the c library. The value defines a minimum heap -// size that is guaranteed to be available. The available heap may be larger -// to make use of any memory that would otherwise remain unused. -#ifndef SL_HEAP_SIZE - #define SL_HEAP_SIZE 10240 -#endif - -// -// <<< end of configuration section >>> - -#endif +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 8192 +#endif + +// Minimum heap size for the application. +// Default: 2048 +// Note that this value will configure the c heap which is normally used by +// malloc() and free() from the c library. The value defines a minimum heap +// size that is guaranteed to be available. The available heap may be larger +// to make use of any memory that would otherwise remain unused. +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 10240 +#endif + +// +// <<< end of configuration section >>> + +#endif diff --git a/locator_host/config/sl_mx25_flash_shutdown_usart_config.h b/locator_host/config/sl_mx25_flash_shutdown_usart_config.h index ac46c18..cf33571 100644 --- a/locator_host/config/sl_mx25_flash_shutdown_usart_config.h +++ b/locator_host/config/sl_mx25_flash_shutdown_usart_config.h @@ -1,67 +1,67 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 - -// USART0 RX on PC02 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 - -// USART0 CLK on PC03 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PORT -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC -#endif -#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PIN -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 -#endif -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 1 + +// USART0 RX on PC02 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 2 + +// USART0 CLK on PC03 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 3 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PORT +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortC +#endif +#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PIN +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 +#endif +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/locator_host/config/sl_ncp_host_com_config.h b/locator_host/config/sl_ncp_host_com_config.h index 54cc3c2..89943eb 100644 --- a/locator_host/config/sl_ncp_host_com_config.h +++ b/locator_host/config/sl_ncp_host_com_config.h @@ -1,48 +1,48 @@ -/***************************************************************************//** - * @file - * @brief Network Co-Processor (NCP) Host Communication Interface Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_NCP_HOST_COM_CONFIG_H -#define SL_NCP_HOST_COM_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup ncp_host_com - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Buffer size (bytes) <260-4096> -// Default: 260 -// Define the size of the buffer in bytes. -#define SL_NCP_HOST_COM_BUF_SIZE (4096) - -// <<< end of configuration section >>> - -/** @} (end addtogroup ncp_host_com) */ -#endif // SL_NCP_HOST_COM_CONFIG_H +/***************************************************************************//** + * @file + * @brief Network Co-Processor (NCP) Host Communication Interface Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_NCP_HOST_COM_CONFIG_H +#define SL_NCP_HOST_COM_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup ncp_host_com + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Buffer size (bytes) <260-4096> +// Default: 260 +// Define the size of the buffer in bytes. +#define SL_NCP_HOST_COM_BUF_SIZE (4096) + +// <<< end of configuration section >>> + +/** @} (end addtogroup ncp_host_com) */ +#endif // SL_NCP_HOST_COM_CONFIG_H diff --git a/locator_host/config/sl_simple_com_config.h b/locator_host/config/sl_simple_com_config.h index 65714cb..ade2aaf 100644 --- a/locator_host/config/sl_simple_com_config.h +++ b/locator_host/config/sl_simple_com_config.h @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_CONFIG_H -#define SL_SIMPLE_COM_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Receive buffer size (bytes) <260-1024> -// Default: 260 -// Define the size of the receive buffer in bytes. -#define SL_SIMPLE_COM_RX_BUF_SIZE (1024) - -// Transmit buffer size (bytes) <260-4096> -// Default: 260 -// Define the size of the transmit buffer in bytes. -#define SL_SIMPLE_COM_TX_BUF_SIZE (260) - -// Robust -// Message header -// Robustify the communication by adding a message header and filter out invalid messages. -// Note: This configuration should match on the sender and receiver side. -// Default: Off -#define SL_SIMPLE_COM_ROBUST 0 - -// CRC -// Add payload CRC and perform checking. -// Note: This configuration should match on the sender and receiver side. -// Default: On -#define SL_SIMPLE_COM_ROBUST_CRC 1 -// -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_CONFIG_H +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_CONFIG_H +#define SL_SIMPLE_COM_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Receive buffer size (bytes) <260-1024> +// Default: 260 +// Define the size of the receive buffer in bytes. +#define SL_SIMPLE_COM_RX_BUF_SIZE (1024) + +// Transmit buffer size (bytes) <260-4096> +// Default: 260 +// Define the size of the transmit buffer in bytes. +#define SL_SIMPLE_COM_TX_BUF_SIZE (260) + +// Robust +// Message header +// Robustify the communication by adding a message header and filter out invalid messages. +// Note: This configuration should match on the sender and receiver side. +// Default: Off +#define SL_SIMPLE_COM_ROBUST 0 + +// CRC +// Add payload CRC and perform checking. +// Note: This configuration should match on the sender and receiver side. +// Default: On +#define SL_SIMPLE_COM_ROBUST_CRC 1 +// +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_CONFIG_H diff --git a/locator_host/config/sl_sleeptimer_config.h b/locator_host/config/sl_sleeptimer_config.h index 8344ef5..a315b29 100644 --- a/locator_host/config/sl_sleeptimer_config.h +++ b/locator_host/config/sl_sleeptimer_config.h @@ -1,82 +1,82 @@ -/***************************************************************************//** - * @file - * @brief Sleep Timer configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_SLEEPTIMER_CONFIG_H -#define SL_SLEEPTIMER_CONFIG_H - -#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 -#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 -#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 -#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 -#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 -#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 -#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 -#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 - -// Timer Peripheral Used by Sleeptimer -// Default (auto select) -// RTCC -// Radio internal RTC (PRORTC) -// RTC -// SYSRTC -// Back-Up RTC (BURTC) -// WTIMER -// TIMER -// Selection of the Timer Peripheral Used by the Sleeptimer -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT - -// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) -// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. -// Default: 0 -#define SL_SLEEPTIMER_TIMER_INSTANCE 0 - -// Enable wallclock functionality -// Enable or disable wallclock functionalities (get_time, get_date, etc). -// Default: 0 -#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 - -// Timer frequency divider (not applicable for WTIMER/TIMER) -// WTIMER/TIMER peripherals are always prescaled to 1024. -// Default: 1 -#define SL_SLEEPTIMER_FREQ_DIVIDER 1 - -// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. -// Default: 0 -#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 - -// Enable DEBUGRUN functionality on hardware RTC. -// Default: 0 -#define SL_SLEEPTIMER_DEBUGRUN 0 - -#endif /* SLEEPTIMER_CONFIG_H */ - -// <<< end of configuration section >>> +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 +#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 +#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// WTIMER +// TIMER +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) +// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. +// Default: 0 +#define SL_SLEEPTIMER_TIMER_INSTANCE 0 + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider (not applicable for WTIMER/TIMER) +// WTIMER/TIMER peripherals are always prescaled to 1024. +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/locator_host/config/sl_uartdrv_usart_exp_config.h b/locator_host/config/sl_uartdrv_usart_exp_config.h index b2a6357..4e032af 100644 --- a/locator_host/config/sl_uartdrv_usart_exp_config.h +++ b/locator_host/config/sl_uartdrv_usart_exp_config.h @@ -1,118 +1,118 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_EXP_CONFIG_H -#define SL_UARTDRV_USART_EXP_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_EXP_BAUDRATE 460800 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_EXP_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHwUart -#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_EXP_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_EXP -// $[USART_SL_UARTDRV_USART_EXP] -#ifndef SL_UARTDRV_USART_EXP_PERIPHERAL -#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 -#endif -#ifndef SL_UARTDRV_USART_EXP_PERIPHERAL_NO -#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 -#endif - -// USART0 TX on PA08 -#ifndef SL_UARTDRV_USART_EXP_TX_PORT -#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_EXP_TX_PIN -#define SL_UARTDRV_USART_EXP_TX_PIN 8 -#endif - -// USART0 RX on PA09 -#ifndef SL_UARTDRV_USART_EXP_RX_PORT -#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_EXP_RX_PIN -#define SL_UARTDRV_USART_EXP_RX_PIN 9 -#endif - -// [USART_SL_UARTDRV_USART_EXP]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_EXP_CONFIG_H +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_EXP_CONFIG_H +#define SL_UARTDRV_USART_EXP_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_EXP_BAUDRATE 460800 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_EXP_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_EXP_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_EXP_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_EXP_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_EXP_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_EXP +// $[USART_SL_UARTDRV_USART_EXP] +#ifndef SL_UARTDRV_USART_EXP_PERIPHERAL +#define SL_UARTDRV_USART_EXP_PERIPHERAL USART0 +#endif +#ifndef SL_UARTDRV_USART_EXP_PERIPHERAL_NO +#define SL_UARTDRV_USART_EXP_PERIPHERAL_NO 0 +#endif + +// USART0 TX on PA08 +#ifndef SL_UARTDRV_USART_EXP_TX_PORT +#define SL_UARTDRV_USART_EXP_TX_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_EXP_TX_PIN +#define SL_UARTDRV_USART_EXP_TX_PIN 8 +#endif + +// USART0 RX on PA09 +#ifndef SL_UARTDRV_USART_EXP_RX_PORT +#define SL_UARTDRV_USART_EXP_RX_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_EXP_RX_PIN +#define SL_UARTDRV_USART_EXP_RX_PIN 9 +#endif + +// [USART_SL_UARTDRV_USART_EXP]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_EXP_CONFIG_H diff --git a/locator_host/config/uartdrv_config.h b/locator_host/config/uartdrv_config.h index 76ee736..2cfa94a 100644 --- a/locator_host/config/uartdrv_config.h +++ b/locator_host/config/uartdrv_config.h @@ -1,114 +1,114 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV configuration file. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ -#define __SILICON_LABS_UARTDRV_CONFIG_H__ - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ -/// Size of the receive operation queue. -/// @details -/// The maximum number of receive operations that can be queued up for one -/// driver instance before @ref UARTDRV_Receive() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 -#endif - -/// Size of the transmit operation queue. -/// @details -/// The maximum number of transmit operations that can be queued up for one -/// driver instance before @ref UARTDRV_Transmit() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 -#endif - -// <<< Use Configuration Wizard in Context Menu >>> -// UARTDRV Settings - -/// Set to 1 to include flow control support -#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -// Flow control support -// <1=> Enable -// <0=> Disable -// Default: 1 -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 -#endif - -/// Maximum number of driver instances. -#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) -// Maximum number of driver instances -// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 -// Default: 4 -#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 -#endif - -/// UART software flow control code: request peer to start TX -#if !defined(UARTDRV_FC_SW_XON) -// UART software flow control code: request peer to start TX -// Default: 0x11 -#define UARTDRV_FC_SW_XON 0x11 -#endif - -/// UART software flow control code: request peer to stop TX -#if !defined(UARTDRV_FC_SW_XOFF) -// UART software flow control code: request peer to stop TX -// Default: 0x13 -#define UARTDRV_FC_SW_XOFF 0x13 -#endif - -/// UART enable reception when sleeping. -#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) -// Enable reception when sleeping -// Enable reception when sleeping will use the power manager and add EM1 -// requirement during receive operations that use DMA. -// <1=> Enable -// <0=> Disable -// Default: 1 -#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 -#endif - -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup uartdrv) */ - -#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/locator_host/drivers/CMakeLists.txt b/locator_host/drivers/CMakeLists.txt index 6f7145a..505fe29 100644 --- a/locator_host/drivers/CMakeLists.txt +++ b/locator_host/drivers/CMakeLists.txt @@ -1,7 +1,7 @@ -add_library(drivers OBJECT - sl_timer.c - sl_watchdog.c -) -target_link_libraries(drivers PRIVATE slc_locator_host) -target_include_directories(drivers PRIVATE ../.) -target_include_directories(drivers PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) +add_library(drivers OBJECT + sl_timer.c + sl_watchdog.c +) +target_link_libraries(drivers PRIVATE slc_locator_host) +target_include_directories(drivers PRIVATE ../.) +target_include_directories(drivers PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}) diff --git a/locator_host/drivers/sl_timer.c b/locator_host/drivers/sl_timer.c index e4bdeaf..be19c25 100644 --- a/locator_host/drivers/sl_timer.c +++ b/locator_host/drivers/sl_timer.c @@ -1,42 +1,42 @@ -/***************************************************************************//** - * @file - * @brief General timer driver code for SI917 - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include "sl_timer.h" -#include "sl_system_config.h" -#include "em_cmu.h" - -//macros ----------------------------------------------------------------------- -//private type definitions ----------------------------------------------------- -//private function prototypes -------------------------------------------------- -//private variables ------------------------------------------------------------ -//function definitions---------------------------------------------------------- -void sl_timer_init(void) -{ - ITM->LAR = 0xC5ACCE55; - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; -} - -uint32_t sl_timer_get(void) -{ - return DWT->CYCCNT; -} - -uint32_t sl_timer_get_frequency(void) -{ - return CMU_ClockFreqGet(cmuClock_CORE); -} +/***************************************************************************//** + * @file + * @brief General timer driver code for SI917 + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#include "sl_timer.h" +#include "sl_system_config.h" +#include "em_cmu.h" + +//macros ----------------------------------------------------------------------- +//private type definitions ----------------------------------------------------- +//private function prototypes -------------------------------------------------- +//private variables ------------------------------------------------------------ +//function definitions---------------------------------------------------------- +void sl_timer_init(void) +{ + ITM->LAR = 0xC5ACCE55; + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; +} + +uint32_t sl_timer_get(void) +{ + return DWT->CYCCNT; +} + +uint32_t sl_timer_get_frequency(void) +{ + return CMU_ClockFreqGet(cmuClock_CORE); +} diff --git a/locator_host/drivers/sl_timer.h b/locator_host/drivers/sl_timer.h index 01d8386..49827f1 100644 --- a/locator_host/drivers/sl_timer.h +++ b/locator_host/drivers/sl_timer.h @@ -1,130 +1,130 @@ -/***************************************************************************//** - * @file - * @brief - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef SL_TIMER_H -#define SL_TIMER_H -#ifdef __cplusplus -extern "C" { -#endif -#include -#include - -//macros ----------------------------------------------------------------------- -#if DEBUG - #define SL_TIMER_RUNTIME_MEASUREMENT_API_EN 1 -#endif - -/// Exponential moving average factor (higher value "prefers" fresh data). A commonly used value is factor=2/(N+1), where N is the number of samples for a SMA. -#define SL_TIMER_RUNTIME_MEAS_AVG_EMA_COEFF (0.005F) - -#if SL_TIMER_RUNTIME_MEASUREMENT_API_EN - #define SL_TIMER_RUNTIME_STRUCT_DEFINE(name) static sl_timer_runtime_t name - #define sl_timer_runtime_meas_start(...) sli_timer_runtime_meas_start(__VA_ARGS__) - #define sl_timer_runtime_meas_stop(...) sli_timer_runtime_meas_stop(__VA_ARGS__) - #define sl_timer_runtime_meas_reset(...) sli_timer_runtime_meas_reset(__VA_ARGS__) -#else - #define SL_TIMER_RUNTIME_STRUCT_DEFINE(name) - #define sl_timer_runtime_meas_start(...) - #define sl_timer_runtime_meas_stop(...) - #define sl_timer_runtime_meas_reset(...) -#endif - -//type definitions ------------------------------------------------------------- -///Utility structure for runtime measurement -typedef struct { - uint32_t run_count; ///< flags to indicate how many measurement run was performed - uint32_t curr; ///< Current runtime in ticks - uint32_t min; ///< Minimum runtime in ticks - uint32_t max; ///< Maximum runtime in ticks - float avg; ///< Average runtime in ticks - float avg_us; ///< Average runtime in us -} sl_timer_runtime_t; - -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- - -/***************************************************************************//** - * Initializes and starts a 32 bit timer. - * Timer configuration comes from the "config" folder. - ******************************************************************************/ -void sl_timer_init(void); - -/***************************************************************************//** - * Gets the current time in us. - ******************************************************************************/ -uint32_t sl_timer_get(void); - -/***************************************************************************//** - * Gets the timer frequency in Hz. - ******************************************************************************/ -uint32_t sl_timer_get_frequency(void); - -/***************************************************************************//** - * Starts the runtime measurement. - * @param meas: Structure for the current runtime measurement. - * Data will be valid after the @ref sli_timer_runtime_meas_stop call. - * - * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! - ******************************************************************************/ -static inline void sli_timer_runtime_meas_start(sl_timer_runtime_t *meas) -{ - meas->curr = sl_timer_get(); -} - -/***************************************************************************//** - * Stops the runtime measurement. - * @param meas: Structure for the current runtime measurement. - * Data is valid after the call! - * - * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! - ******************************************************************************/ -static inline void sli_timer_runtime_meas_stop(sl_timer_runtime_t *meas) -{ - //save the time first statistic overhead comes after - meas->curr = sl_timer_get() - meas->curr; - - if (0 == meas->run_count) { - //no valid measurement until now - meas->min = meas->curr; - meas->max = meas->curr; - meas->avg = meas->curr; - } else { - //at least 1 measurement before - meas->min = meas->curr >= meas->min ? meas->min : meas->curr; - meas->max = meas->curr <= meas->max ? meas->max : meas->curr; - meas->avg += SL_TIMER_RUNTIME_MEAS_AVG_EMA_COEFF * (meas->curr - meas->avg); - } - meas->avg_us = meas->avg / (sl_timer_get_frequency() / 1000000); - meas->run_count++; -} - -/***************************************************************************//** - * Resets the runtime measurement statistics - * @param meas: Structure for the current runtime measurement. - * Data is valid after the first start and stop call. - * - * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! - ******************************************************************************/ -static inline void sli_timer_runtime_meas_reset(sl_timer_runtime_t *meas) -{ - memset(meas, 0, sizeof(*meas)); -} - -#ifdef __cplusplus -} -#endif -#endif /* SL_TIMER_H */ +/***************************************************************************//** + * @file + * @brief + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef SL_TIMER_H +#define SL_TIMER_H +#ifdef __cplusplus +extern "C" { +#endif +#include +#include + +//macros ----------------------------------------------------------------------- +#if DEBUG + #define SL_TIMER_RUNTIME_MEASUREMENT_API_EN 1 +#endif + +/// Exponential moving average factor (higher value "prefers" fresh data). A commonly used value is factor=2/(N+1), where N is the number of samples for a SMA. +#define SL_TIMER_RUNTIME_MEAS_AVG_EMA_COEFF (0.005F) + +#if SL_TIMER_RUNTIME_MEASUREMENT_API_EN + #define SL_TIMER_RUNTIME_STRUCT_DEFINE(name) static sl_timer_runtime_t name + #define sl_timer_runtime_meas_start(...) sli_timer_runtime_meas_start(__VA_ARGS__) + #define sl_timer_runtime_meas_stop(...) sli_timer_runtime_meas_stop(__VA_ARGS__) + #define sl_timer_runtime_meas_reset(...) sli_timer_runtime_meas_reset(__VA_ARGS__) +#else + #define SL_TIMER_RUNTIME_STRUCT_DEFINE(name) + #define sl_timer_runtime_meas_start(...) + #define sl_timer_runtime_meas_stop(...) + #define sl_timer_runtime_meas_reset(...) +#endif + +//type definitions ------------------------------------------------------------- +///Utility structure for runtime measurement +typedef struct { + uint32_t run_count; ///< flags to indicate how many measurement run was performed + uint32_t curr; ///< Current runtime in ticks + uint32_t min; ///< Minimum runtime in ticks + uint32_t max; ///< Maximum runtime in ticks + float avg; ///< Average runtime in ticks + float avg_us; ///< Average runtime in us +} sl_timer_runtime_t; + +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- + +/***************************************************************************//** + * Initializes and starts a 32 bit timer. + * Timer configuration comes from the "config" folder. + ******************************************************************************/ +void sl_timer_init(void); + +/***************************************************************************//** + * Gets the current time in us. + ******************************************************************************/ +uint32_t sl_timer_get(void); + +/***************************************************************************//** + * Gets the timer frequency in Hz. + ******************************************************************************/ +uint32_t sl_timer_get_frequency(void); + +/***************************************************************************//** + * Starts the runtime measurement. + * @param meas: Structure for the current runtime measurement. + * Data will be valid after the @ref sli_timer_runtime_meas_stop call. + * + * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! + ******************************************************************************/ +static inline void sli_timer_runtime_meas_start(sl_timer_runtime_t *meas) +{ + meas->curr = sl_timer_get(); +} + +/***************************************************************************//** + * Stops the runtime measurement. + * @param meas: Structure for the current runtime measurement. + * Data is valid after the call! + * + * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! + ******************************************************************************/ +static inline void sli_timer_runtime_meas_stop(sl_timer_runtime_t *meas) +{ + //save the time first statistic overhead comes after + meas->curr = sl_timer_get() - meas->curr; + + if (0 == meas->run_count) { + //no valid measurement until now + meas->min = meas->curr; + meas->max = meas->curr; + meas->avg = meas->curr; + } else { + //at least 1 measurement before + meas->min = meas->curr >= meas->min ? meas->min : meas->curr; + meas->max = meas->curr <= meas->max ? meas->max : meas->curr; + meas->avg += SL_TIMER_RUNTIME_MEAS_AVG_EMA_COEFF * (meas->curr - meas->avg); + } + meas->avg_us = meas->avg / (sl_timer_get_frequency() / 1000000); + meas->run_count++; +} + +/***************************************************************************//** + * Resets the runtime measurement statistics + * @param meas: Structure for the current runtime measurement. + * Data is valid after the first start and stop call. + * + * @warning Internal function DO NOT use directly, use the macro with the "sl" prefix! + ******************************************************************************/ +static inline void sli_timer_runtime_meas_reset(sl_timer_runtime_t *meas) +{ + memset(meas, 0, sizeof(*meas)); +} + +#ifdef __cplusplus +} +#endif +#endif /* SL_TIMER_H */ diff --git a/locator_host/drivers/sl_watchdog.c b/locator_host/drivers/sl_watchdog.c index ba8d404..2779233 100644 --- a/locator_host/drivers/sl_watchdog.c +++ b/locator_host/drivers/sl_watchdog.c @@ -1,39 +1,39 @@ -/***************************************************************************//** - * @file - * @brief General timer driver code for SI917 - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#include "sl_watchdog.h" -#include "sl_system_config.h" -#include "em_cmu.h" -#include "em_wdog.h" - -//macros ----------------------------------------------------------------------- -//private type definitions ----------------------------------------------------- -//private function prototypes -------------------------------------------------- -//private variables ------------------------------------------------------------ -//function definitions---------------------------------------------------------- -void sl_watchdog_init(void) -{ - const WDOG_Init_TypeDef wdog_init = WDOG_INIT_DEFAULT; - - CMU_ClockEnable(cmuClock_WDOG0, true); - WDOGn_Init(WDOG0, &wdog_init); -} - -void sl_watchdog_feed(void) -{ - WDOGn_Feed(WDOG0); -} +/***************************************************************************//** + * @file + * @brief General timer driver code for SI917 + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#include "sl_watchdog.h" +#include "sl_system_config.h" +#include "em_cmu.h" +#include "em_wdog.h" + +//macros ----------------------------------------------------------------------- +//private type definitions ----------------------------------------------------- +//private function prototypes -------------------------------------------------- +//private variables ------------------------------------------------------------ +//function definitions---------------------------------------------------------- +void sl_watchdog_init(void) +{ + const WDOG_Init_TypeDef wdog_init = WDOG_INIT_DEFAULT; + + CMU_ClockEnable(cmuClock_WDOG0, true); + WDOGn_Init(WDOG0, &wdog_init); +} + +void sl_watchdog_feed(void) +{ + WDOGn_Feed(WDOG0); +} diff --git a/locator_host/drivers/sl_watchdog.h b/locator_host/drivers/sl_watchdog.h index da75295..a9f3f91 100644 --- a/locator_host/drivers/sl_watchdog.h +++ b/locator_host/drivers/sl_watchdog.h @@ -1,43 +1,43 @@ -/***************************************************************************//** - * @file - * @brief - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef SL_WATCHDOG_H -#define SL_WATCHDOG_H -#ifdef __cplusplus -extern "C" { -#endif - -//macros ----------------------------------------------------------------------- -//type definitions ------------------------------------------------------------- -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- - -/***************************************************************************//** - * Initializes and starts the Wathchdog timer of the MCU. - * Configuration comes from the "config" folder. - ******************************************************************************/ -void sl_watchdog_init(void); - -/***************************************************************************//** - * Restarts/feeds/kicks the watchdog timer - ******************************************************************************/ -void sl_watchdog_feed(void); - -#ifdef __cplusplus -} -#endif -#endif /* SL_WATCHDOG_H */ +/***************************************************************************//** + * @file + * @brief + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef SL_WATCHDOG_H +#define SL_WATCHDOG_H +#ifdef __cplusplus +extern "C" { +#endif + +//macros ----------------------------------------------------------------------- +//type definitions ------------------------------------------------------------- +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- + +/***************************************************************************//** + * Initializes and starts the Wathchdog timer of the MCU. + * Configuration comes from the "config" folder. + ******************************************************************************/ +void sl_watchdog_init(void); + +/***************************************************************************//** + * Restarts/feeds/kicks the watchdog timer + ******************************************************************************/ +void sl_watchdog_feed(void); + +#ifdef __cplusplus +} +#endif +#endif /* SL_WATCHDOG_H */ diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c index 9a80f57..fdaa24b 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c @@ -1,450 +1,450 @@ -/***************************************************************************//** - * @file - * @brief Composes the GATT database using the Dynamic GATT API. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "app_assert.h" -#include "sl_bt_api.h" -#include "gatt_db.h" -#include "sl_ncp_gatt.h" - -// UUID lengths. -#define UUID_16_LEN 2 -#define UUID_128_LEN 16 - -// Bitmask indicating a 128-bit UUID handle. -#define UUID_128_HANDLE 0x8000 -// Check for 16-bit UUID value. -#define IS_UUID_16(uuid) (((uuid) & UUID_128_HANDLE) == 0) - -// 16-bit UUIDs allocated for GATT Declarations. -#define PRIMARY_SERVICE_UUID 0x2800 -#define SECONDARY_SERVICE_UUID 0x2801 -#define INCLUDE_UUID 0x2802 -#define CHARACTERISTIC_UUID 0x2803 -#define CLIENT_CHARACTERISTIC_CONFIGURATION_UUID 0x2902 - -// GATT database datatypes. -#define GATTDB_DATATYPE_CONSTANT_VALUE 0x00 -#define GATTDB_DATATYPE_FIXED_LENGTH_VALUE 0x01 -#define GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE 0x02 -#define GATTDB_DATATYPE_USER_VALUE 0x07 - -// GATT database permission flags. -#define GATTDB_PERMISSION_READ 0x0001 -#define GATTDB_PERMISSION_WRITE 0x0002 -#define GATTDB_PERMISSION_ENCRYPTED_READ 0x0010 -#define GATTDB_PERMISSION_AUTHENTICATED_READ 0x0020 -#define GATTDB_PERMISSION_BONDED_READ 0x0040 -#define GATTDB_PERMISSION_ENCRYPTED_WRITE 0x0100 -#define GATTDB_PERMISSION_AUTHENTICATED_WRITE 0x0200 -#define GATTDB_PERMISSION_BONDED_WRITE 0x0400 -#define GATTDB_PERMISSION_DISCOVERABLE 0x0800 -#define GATTDB_PERMISSION_ENCRYPTED_NOTIFY 0x1000 -#define GATTDB_PERMISSION_AUTHENTICATED_NOTIFY 0x2000 -#define GATTDB_PERMISSION_BONDED_NOTIFY 0x4000 -#define GATTDB_PERMISSION_ADVERTISE 0x8000 - -// Flag indicating that the Client Characteristic Configuration descriptor -// should be created automatically. -#define GATTDB_AUTO_CCCD 0x00 - -// Flag indicating that a service should not be advertised. -#define GATTDB_NON_ADVERTISED_SERVICE 0x00 - -// Structure for attribute values. -typedef struct { - uint16_t max_len; - uint16_t len; - const uint8_t *data; -} attribute_value_t; - -// Initialize GATT database dynamically. -static void dynamic_gattdb_init(void); - -// Select the security related information from the permission property of an -// attribute and map it according to sl_bt_gattdb_security_requirements macros. -static uint16_t map_security(uint16_t permissions); - -// Convert the datatype property of an attribute according to the -// sl_bt_gattdb_value_type_t type. -static sl_bt_gattdb_value_type_t map_value_type(uint8_t datatype); - -// Convert the permissions property of an attribute according to the -// sl_bt_gattdb_descriptor_properties macros. -static uint16_t map_descriptor_property(uint16_t permissions); - -// Get the value and its related length informations of an attribute. -static attribute_value_t get_attribute_value(const sli_bt_gattdb_attribute_t *attribute); - -// Get the index of the first attrubute to be processed. -static uint16_t get_start_index(void); - -// Bluetooth stack event handler. -void sl_ncp_gatt_on_event(sl_bt_msg_t *evt) -{ - switch (SL_BT_MSG_ID(evt->header)) { - case sl_bt_evt_system_boot_id: - dynamic_gattdb_init(); - break; - - default: - break; - } -} - -/**************************************************************************//** - * Initialize GATT database dynamically. - *****************************************************************************/ -static void dynamic_gattdb_init(void) -{ - sl_status_t sc = SL_STATUS_OK; - - // Create a new dynamic GATT Database session. - uint16_t gattdb_session; // Session handle. - sc = sl_bt_gattdb_new_session(&gattdb_session); - app_assert_status(sc); - - // The handle of the last added service. - uint16_t current_service; - // The handle of the last added characteristic. - uint16_t current_characteristic; - // The handle of the last added descriptor. - uint16_t current_descriptor; - // Start index of the attributes - uint16_t i = get_start_index(); - - for (; i < gattdb.attribute_num; i++) { - if (IS_UUID_16(gattdb.attributes[i].uuid)) { - switch (gattdb.uuid16[gattdb.attributes[i].uuid]) { - case PRIMARY_SERVICE_UUID: - // Add service. - sc = sl_bt_gattdb_add_service(gattdb_session, - sl_bt_gattdb_primary_service, - gattdb.attributes[i].permissions & GATTDB_PERMISSION_ADVERTISE \ - ? SL_BT_GATTDB_ADVERTISED_SERVICE \ - : GATTDB_NON_ADVERTISED_SERVICE, - gattdb.attributes[i].constdata->len, - gattdb.attributes[i].constdata->data, - ¤t_service); - app_assert_status(sc); - - // Check the returned handle. - app_assert(current_service == gattdb.attributes[i].handle, - "Handle mismatch when adding service %d.", i); - - // Start service. - sc = sl_bt_gattdb_start_service(gattdb_session, current_service); - app_assert_status(sc); - break; - - case SECONDARY_SERVICE_UUID: - // Add service. - sc = sl_bt_gattdb_add_service(gattdb_session, - sl_bt_gattdb_secondary_service, - gattdb.attributes[i].permissions & GATTDB_PERMISSION_ADVERTISE \ - ? SL_BT_GATTDB_ADVERTISED_SERVICE \ - : GATTDB_NON_ADVERTISED_SERVICE, - gattdb.attributes[i].constdata->len, - gattdb.attributes[i].constdata->data, - ¤t_service); - app_assert_status(sc); - - // Check the returned handle. - app_assert(current_service == gattdb.attributes[i].handle, - "Handle mismatch when adding service %d.", i); - - // Start service. - sc = sl_bt_gattdb_start_service(gattdb_session, current_service); - app_assert_status(sc); - break; - - case INCLUDE_UUID: { - uint16_t handle; - sc = sl_bt_gattdb_add_included_service(gattdb_session, - current_service, - gattdb.attributes[i].service_include.start, - &handle); - app_assert_status(sc); - - // Check the returned handle. - app_assert(handle == gattdb.attributes[i].handle, - "Handle mismatch when including service. Returned handle: %d, expected handle: %d.", - handle, - gattdb.attributes[i].handle); - break; - } - - case CHARACTERISTIC_UUID: { - // Preparing characteristic value. - attribute_value_t value; - value = get_attribute_value(&gattdb.attributes[i + 1]); - - // Add characteristic. - if (IS_UUID_16(gattdb.attributes[i].characteristic.char_uuid)) { - // 16-bit uuid - sl_bt_uuid_16_t uuid; - memcpy(&uuid.data, &gattdb.uuid16[gattdb.attributes[i].characteristic.char_uuid], UUID_16_LEN); - sc = sl_bt_gattdb_add_uuid16_characteristic(gattdb_session, - current_service, - (uint16_t)gattdb.attributes[i].characteristic.properties, - map_security(gattdb.attributes[i + 1].permissions), - GATTDB_AUTO_CCCD, - uuid, - map_value_type(gattdb.attributes[i + 1].datatype), - value.max_len, - value.len, - value.data, - ¤t_characteristic); - app_assert_status(sc); - } else { - // 128-bit uuid - uuid_128 uuid; - memcpy(&uuid.data, &gattdb.uuid128[UUID_128_LEN * (gattdb.attributes[i].characteristic.char_uuid & ~(UUID_128_HANDLE))], UUID_128_LEN); - sc = sl_bt_gattdb_add_uuid128_characteristic(gattdb_session, - current_service, - (uint16_t)gattdb.attributes[i].characteristic.properties, - map_security(gattdb.attributes[i + 1].permissions), - GATTDB_AUTO_CCCD, - uuid, - map_value_type(gattdb.attributes[i + 1].datatype), - value.max_len, - value.len, - value.data, - ¤t_characteristic); - app_assert_status(sc); - } - - // Check the returned handle. - app_assert(current_characteristic == gattdb.attributes[i + 1].handle, - "Handle mismatch when adding characteristic %d.", i); - - // Start characteristic. - sc = sl_bt_gattdb_start_characteristic(gattdb_session, current_characteristic); - app_assert_status(sc); - - i++; // Skip the next attribute since it is processed already. - break; - } - - case CLIENT_CHARACTERISTIC_CONFIGURATION_UUID: - // Client Characteristic Configuration descriptors are created - // automatically by the stack. - break; - - default: { - // Descriptor with 16-bit uuid. - // Preparing descriptor value. - attribute_value_t value; - value = get_attribute_value(&gattdb.attributes[i]); - - // Add descriptor. - sl_bt_uuid_16_t uuid; - memcpy(&uuid.data, &gattdb.uuid16[gattdb.attributes[i].uuid], UUID_16_LEN); - sc = sl_bt_gattdb_add_uuid16_descriptor(gattdb_session, - current_characteristic, - map_descriptor_property(gattdb.attributes[i].permissions), - map_security(gattdb.attributes[i].permissions), - uuid, - map_value_type(gattdb.attributes[i].datatype), - value.max_len, - value.len, - value.data, - ¤t_descriptor); - app_assert_status(sc); - - // Check the returned handle. - app_assert(current_descriptor == gattdb.attributes[i].handle, - "Handle mismatch when adding descriptor %d.", i); - break; - } - } - } else { - // Descriptor with 128-bit uuid. - // Preparing descriptor value. - attribute_value_t value; - value = get_attribute_value(&gattdb.attributes[i]); - - // Add descriptor. - uuid_128 uuid; - memcpy(&uuid.data, &gattdb.uuid128[UUID_128_LEN * (gattdb.attributes[i].uuid & ~(UUID_128_HANDLE))], UUID_128_LEN); - sc = sl_bt_gattdb_add_uuid128_descriptor(gattdb_session, - current_characteristic, - map_descriptor_property(gattdb.attributes[i].permissions), - map_security(gattdb.attributes[i].permissions), - uuid, - map_value_type(gattdb.attributes[i].datatype), - value.max_len, - value.len, - value.data, - ¤t_descriptor); - app_assert_status(sc); - - // Check the returned handle. - app_assert(current_descriptor == gattdb.attributes[i].handle, - "Handle mismatch when adding descriptor %d.", i); - } - } - - // Commit changes. - sc = sl_bt_gattdb_commit(gattdb_session); - app_assert_status(sc); -} - -/***************************************************************************//** - * Select the security related information from the permission property of an - * attribute and map it according to sl_bt_gattdb_security_requirements macros. - * - * @param[in] permissions. The permissions property of an attribute provided by - * gatt_db.c. - * @return The converted security flags ready to pass to the api. - ******************************************************************************/ -static uint16_t map_security(uint16_t permissions) -{ - uint16_t security = 0x0000; - - security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_READ) ? SL_BT_GATTDB_ENCRYPTED_READ : 0x0000; - security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_READ) ? SL_BT_GATTDB_AUTHENTICATED_READ : 0x0000; - security |= (permissions & GATTDB_PERMISSION_BONDED_READ) ? SL_BT_GATTDB_BONDED_READ : 0x0000; - security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_WRITE) ? SL_BT_GATTDB_ENCRYPTED_WRITE : 0x0000; - security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_WRITE) ? SL_BT_GATTDB_AUTHENTICATED_WRITE : 0x0000; - security |= (permissions & GATTDB_PERMISSION_BONDED_WRITE) ? SL_BT_GATTDB_BONDED_WRITE : 0x0000; - security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_NOTIFY) ? SL_BT_GATTDB_ENCRYPTED_NOTIFY : 0x0000; - security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_NOTIFY) ? SL_BT_GATTDB_AUTHENTICATED_NOTIFY : 0x0000; - security |= (permissions & GATTDB_PERMISSION_BONDED_NOTIFY) ? SL_BT_GATTDB_BONDED_NOTIFY : 0x0000; - - return security; -} - -/***************************************************************************//** - * Convert the datatype property of an attribute according to the - * sl_bt_gattdb_value_type_t type. - * - * @param[in] datatype. The datatype property of an attribute provided by - * gatt_db.c. - * @return The converted datatype ready to pass to the api. - ******************************************************************************/ -static sl_bt_gattdb_value_type_t map_value_type(uint8_t datatype) -{ - switch (datatype) { - case GATTDB_DATATYPE_FIXED_LENGTH_VALUE: - return sl_bt_gattdb_fixed_length_value; - - case GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE: - return sl_bt_gattdb_variable_length_value; - - case GATTDB_DATATYPE_USER_VALUE: - return sl_bt_gattdb_user_managed_value; - - default: - // For value types not being supported by dynamic GATT. - return sl_bt_gattdb_fixed_length_value; - } -} - -/***************************************************************************//** - * Convert the permissions property of an attribute according to the - * sl_bt_gattdb_descriptor_properties macros. - * - * @param[in] permissions. The permissions property of an attribute provided by - * gatt_db.c. - * @return The converted permissions ready to pass to the api. - ******************************************************************************/ -static uint16_t map_descriptor_property(uint16_t permissions) -{ - uint16_t property = 0x0000; - - property |= (permissions & GATTDB_PERMISSION_READ) ? SL_BT_GATTDB_DESCRIPTOR_READ : 0x0000; - property |= (permissions & GATTDB_PERMISSION_WRITE) ? SL_BT_GATTDB_DESCRIPTOR_WRITE : 0x0000; - property |= (permissions & GATTDB_PERMISSION_DISCOVERABLE) ? 0x0000 : SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY; - - return property; -} - -/***************************************************************************//** - * Get the value and its related length informations of an attribute. - * - * @param[in] attribute. An attribute from provided by gatt_db.c. - * @return The maximum length, length and the actual data of the attribute. - * @ref attribute_value_t. - ******************************************************************************/ -static attribute_value_t get_attribute_value(const sli_bt_gattdb_attribute_t *attribute) -{ - attribute_value_t value; - - switch (attribute->datatype) { - case GATTDB_DATATYPE_CONSTANT_VALUE: - value.max_len = attribute->constdata->len; - value.len = attribute->constdata->len; - value.data = attribute->constdata->data; - break; - - case GATTDB_DATATYPE_FIXED_LENGTH_VALUE: - value.max_len = attribute->dynamicdata->max_len; - value.len = attribute->dynamicdata->max_len; - value.data = attribute->dynamicdata->data; - break; - - case GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE: - value.max_len = attribute->dynamicdata->max_len; - value.len = attribute->dynamicdata->len; - value.data = attribute->dynamicdata->data; - break; - - default: - // User managed values and other symbols. - value.max_len = 0; - value.len = 0; - value.data = NULL; - break; - } - - return value; -} - -/***************************************************************************//** - * Get the index of the first attrubute to be processed. - ******************************************************************************/ -static uint16_t get_start_index(void) -{ - uint16_t idx = 0; - // Check for Generic Attribute UUID (0x1801) - if ((gattdb.attributes[idx].constdata->len == 2) - && (gattdb.attributes[idx].constdata->data[0] == 0x01) - && (gattdb.attributes[idx].constdata->data[1] == 0x18)) { - for (idx = 1; idx < gattdb.attribute_num; idx++) { - // Find the next service declaration - if (IS_UUID_16(gattdb.attributes[idx].uuid) - && ((gattdb.uuid16[gattdb.attributes[idx].uuid] == PRIMARY_SERVICE_UUID) - || (gattdb.uuid16[gattdb.attributes[idx].uuid] == SECONDARY_SERVICE_UUID))) { - break; - } - } - } - return idx; -} +/***************************************************************************//** + * @file + * @brief Composes the GATT database using the Dynamic GATT API. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "app_assert.h" +#include "sl_bt_api.h" +#include "gatt_db.h" +#include "sl_ncp_gatt.h" + +// UUID lengths. +#define UUID_16_LEN 2 +#define UUID_128_LEN 16 + +// Bitmask indicating a 128-bit UUID handle. +#define UUID_128_HANDLE 0x8000 +// Check for 16-bit UUID value. +#define IS_UUID_16(uuid) (((uuid) & UUID_128_HANDLE) == 0) + +// 16-bit UUIDs allocated for GATT Declarations. +#define PRIMARY_SERVICE_UUID 0x2800 +#define SECONDARY_SERVICE_UUID 0x2801 +#define INCLUDE_UUID 0x2802 +#define CHARACTERISTIC_UUID 0x2803 +#define CLIENT_CHARACTERISTIC_CONFIGURATION_UUID 0x2902 + +// GATT database datatypes. +#define GATTDB_DATATYPE_CONSTANT_VALUE 0x00 +#define GATTDB_DATATYPE_FIXED_LENGTH_VALUE 0x01 +#define GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE 0x02 +#define GATTDB_DATATYPE_USER_VALUE 0x07 + +// GATT database permission flags. +#define GATTDB_PERMISSION_READ 0x0001 +#define GATTDB_PERMISSION_WRITE 0x0002 +#define GATTDB_PERMISSION_ENCRYPTED_READ 0x0010 +#define GATTDB_PERMISSION_AUTHENTICATED_READ 0x0020 +#define GATTDB_PERMISSION_BONDED_READ 0x0040 +#define GATTDB_PERMISSION_ENCRYPTED_WRITE 0x0100 +#define GATTDB_PERMISSION_AUTHENTICATED_WRITE 0x0200 +#define GATTDB_PERMISSION_BONDED_WRITE 0x0400 +#define GATTDB_PERMISSION_DISCOVERABLE 0x0800 +#define GATTDB_PERMISSION_ENCRYPTED_NOTIFY 0x1000 +#define GATTDB_PERMISSION_AUTHENTICATED_NOTIFY 0x2000 +#define GATTDB_PERMISSION_BONDED_NOTIFY 0x4000 +#define GATTDB_PERMISSION_ADVERTISE 0x8000 + +// Flag indicating that the Client Characteristic Configuration descriptor +// should be created automatically. +#define GATTDB_AUTO_CCCD 0x00 + +// Flag indicating that a service should not be advertised. +#define GATTDB_NON_ADVERTISED_SERVICE 0x00 + +// Structure for attribute values. +typedef struct { + uint16_t max_len; + uint16_t len; + const uint8_t *data; +} attribute_value_t; + +// Initialize GATT database dynamically. +static void dynamic_gattdb_init(void); + +// Select the security related information from the permission property of an +// attribute and map it according to sl_bt_gattdb_security_requirements macros. +static uint16_t map_security(uint16_t permissions); + +// Convert the datatype property of an attribute according to the +// sl_bt_gattdb_value_type_t type. +static sl_bt_gattdb_value_type_t map_value_type(uint8_t datatype); + +// Convert the permissions property of an attribute according to the +// sl_bt_gattdb_descriptor_properties macros. +static uint16_t map_descriptor_property(uint16_t permissions); + +// Get the value and its related length informations of an attribute. +static attribute_value_t get_attribute_value(const sli_bt_gattdb_attribute_t *attribute); + +// Get the index of the first attrubute to be processed. +static uint16_t get_start_index(void); + +// Bluetooth stack event handler. +void sl_ncp_gatt_on_event(sl_bt_msg_t *evt) +{ + switch (SL_BT_MSG_ID(evt->header)) { + case sl_bt_evt_system_boot_id: + dynamic_gattdb_init(); + break; + + default: + break; + } +} + +/**************************************************************************//** + * Initialize GATT database dynamically. + *****************************************************************************/ +static void dynamic_gattdb_init(void) +{ + sl_status_t sc = SL_STATUS_OK; + + // Create a new dynamic GATT Database session. + uint16_t gattdb_session; // Session handle. + sc = sl_bt_gattdb_new_session(&gattdb_session); + app_assert_status(sc); + + // The handle of the last added service. + uint16_t current_service; + // The handle of the last added characteristic. + uint16_t current_characteristic; + // The handle of the last added descriptor. + uint16_t current_descriptor; + // Start index of the attributes + uint16_t i = get_start_index(); + + for (; i < gattdb.attribute_num; i++) { + if (IS_UUID_16(gattdb.attributes[i].uuid)) { + switch (gattdb.uuid16[gattdb.attributes[i].uuid]) { + case PRIMARY_SERVICE_UUID: + // Add service. + sc = sl_bt_gattdb_add_service(gattdb_session, + sl_bt_gattdb_primary_service, + gattdb.attributes[i].permissions & GATTDB_PERMISSION_ADVERTISE \ + ? SL_BT_GATTDB_ADVERTISED_SERVICE \ + : GATTDB_NON_ADVERTISED_SERVICE, + gattdb.attributes[i].constdata->len, + gattdb.attributes[i].constdata->data, + ¤t_service); + app_assert_status(sc); + + // Check the returned handle. + app_assert(current_service == gattdb.attributes[i].handle, + "Handle mismatch when adding service %d.", i); + + // Start service. + sc = sl_bt_gattdb_start_service(gattdb_session, current_service); + app_assert_status(sc); + break; + + case SECONDARY_SERVICE_UUID: + // Add service. + sc = sl_bt_gattdb_add_service(gattdb_session, + sl_bt_gattdb_secondary_service, + gattdb.attributes[i].permissions & GATTDB_PERMISSION_ADVERTISE \ + ? SL_BT_GATTDB_ADVERTISED_SERVICE \ + : GATTDB_NON_ADVERTISED_SERVICE, + gattdb.attributes[i].constdata->len, + gattdb.attributes[i].constdata->data, + ¤t_service); + app_assert_status(sc); + + // Check the returned handle. + app_assert(current_service == gattdb.attributes[i].handle, + "Handle mismatch when adding service %d.", i); + + // Start service. + sc = sl_bt_gattdb_start_service(gattdb_session, current_service); + app_assert_status(sc); + break; + + case INCLUDE_UUID: { + uint16_t handle; + sc = sl_bt_gattdb_add_included_service(gattdb_session, + current_service, + gattdb.attributes[i].service_include.start, + &handle); + app_assert_status(sc); + + // Check the returned handle. + app_assert(handle == gattdb.attributes[i].handle, + "Handle mismatch when including service. Returned handle: %d, expected handle: %d.", + handle, + gattdb.attributes[i].handle); + break; + } + + case CHARACTERISTIC_UUID: { + // Preparing characteristic value. + attribute_value_t value; + value = get_attribute_value(&gattdb.attributes[i + 1]); + + // Add characteristic. + if (IS_UUID_16(gattdb.attributes[i].characteristic.char_uuid)) { + // 16-bit uuid + sl_bt_uuid_16_t uuid; + memcpy(&uuid.data, &gattdb.uuid16[gattdb.attributes[i].characteristic.char_uuid], UUID_16_LEN); + sc = sl_bt_gattdb_add_uuid16_characteristic(gattdb_session, + current_service, + (uint16_t)gattdb.attributes[i].characteristic.properties, + map_security(gattdb.attributes[i + 1].permissions), + GATTDB_AUTO_CCCD, + uuid, + map_value_type(gattdb.attributes[i + 1].datatype), + value.max_len, + value.len, + value.data, + ¤t_characteristic); + app_assert_status(sc); + } else { + // 128-bit uuid + uuid_128 uuid; + memcpy(&uuid.data, &gattdb.uuid128[UUID_128_LEN * (gattdb.attributes[i].characteristic.char_uuid & ~(UUID_128_HANDLE))], UUID_128_LEN); + sc = sl_bt_gattdb_add_uuid128_characteristic(gattdb_session, + current_service, + (uint16_t)gattdb.attributes[i].characteristic.properties, + map_security(gattdb.attributes[i + 1].permissions), + GATTDB_AUTO_CCCD, + uuid, + map_value_type(gattdb.attributes[i + 1].datatype), + value.max_len, + value.len, + value.data, + ¤t_characteristic); + app_assert_status(sc); + } + + // Check the returned handle. + app_assert(current_characteristic == gattdb.attributes[i + 1].handle, + "Handle mismatch when adding characteristic %d.", i); + + // Start characteristic. + sc = sl_bt_gattdb_start_characteristic(gattdb_session, current_characteristic); + app_assert_status(sc); + + i++; // Skip the next attribute since it is processed already. + break; + } + + case CLIENT_CHARACTERISTIC_CONFIGURATION_UUID: + // Client Characteristic Configuration descriptors are created + // automatically by the stack. + break; + + default: { + // Descriptor with 16-bit uuid. + // Preparing descriptor value. + attribute_value_t value; + value = get_attribute_value(&gattdb.attributes[i]); + + // Add descriptor. + sl_bt_uuid_16_t uuid; + memcpy(&uuid.data, &gattdb.uuid16[gattdb.attributes[i].uuid], UUID_16_LEN); + sc = sl_bt_gattdb_add_uuid16_descriptor(gattdb_session, + current_characteristic, + map_descriptor_property(gattdb.attributes[i].permissions), + map_security(gattdb.attributes[i].permissions), + uuid, + map_value_type(gattdb.attributes[i].datatype), + value.max_len, + value.len, + value.data, + ¤t_descriptor); + app_assert_status(sc); + + // Check the returned handle. + app_assert(current_descriptor == gattdb.attributes[i].handle, + "Handle mismatch when adding descriptor %d.", i); + break; + } + } + } else { + // Descriptor with 128-bit uuid. + // Preparing descriptor value. + attribute_value_t value; + value = get_attribute_value(&gattdb.attributes[i]); + + // Add descriptor. + uuid_128 uuid; + memcpy(&uuid.data, &gattdb.uuid128[UUID_128_LEN * (gattdb.attributes[i].uuid & ~(UUID_128_HANDLE))], UUID_128_LEN); + sc = sl_bt_gattdb_add_uuid128_descriptor(gattdb_session, + current_characteristic, + map_descriptor_property(gattdb.attributes[i].permissions), + map_security(gattdb.attributes[i].permissions), + uuid, + map_value_type(gattdb.attributes[i].datatype), + value.max_len, + value.len, + value.data, + ¤t_descriptor); + app_assert_status(sc); + + // Check the returned handle. + app_assert(current_descriptor == gattdb.attributes[i].handle, + "Handle mismatch when adding descriptor %d.", i); + } + } + + // Commit changes. + sc = sl_bt_gattdb_commit(gattdb_session); + app_assert_status(sc); +} + +/***************************************************************************//** + * Select the security related information from the permission property of an + * attribute and map it according to sl_bt_gattdb_security_requirements macros. + * + * @param[in] permissions. The permissions property of an attribute provided by + * gatt_db.c. + * @return The converted security flags ready to pass to the api. + ******************************************************************************/ +static uint16_t map_security(uint16_t permissions) +{ + uint16_t security = 0x0000; + + security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_READ) ? SL_BT_GATTDB_ENCRYPTED_READ : 0x0000; + security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_READ) ? SL_BT_GATTDB_AUTHENTICATED_READ : 0x0000; + security |= (permissions & GATTDB_PERMISSION_BONDED_READ) ? SL_BT_GATTDB_BONDED_READ : 0x0000; + security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_WRITE) ? SL_BT_GATTDB_ENCRYPTED_WRITE : 0x0000; + security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_WRITE) ? SL_BT_GATTDB_AUTHENTICATED_WRITE : 0x0000; + security |= (permissions & GATTDB_PERMISSION_BONDED_WRITE) ? SL_BT_GATTDB_BONDED_WRITE : 0x0000; + security |= (permissions & GATTDB_PERMISSION_ENCRYPTED_NOTIFY) ? SL_BT_GATTDB_ENCRYPTED_NOTIFY : 0x0000; + security |= (permissions & GATTDB_PERMISSION_AUTHENTICATED_NOTIFY) ? SL_BT_GATTDB_AUTHENTICATED_NOTIFY : 0x0000; + security |= (permissions & GATTDB_PERMISSION_BONDED_NOTIFY) ? SL_BT_GATTDB_BONDED_NOTIFY : 0x0000; + + return security; +} + +/***************************************************************************//** + * Convert the datatype property of an attribute according to the + * sl_bt_gattdb_value_type_t type. + * + * @param[in] datatype. The datatype property of an attribute provided by + * gatt_db.c. + * @return The converted datatype ready to pass to the api. + ******************************************************************************/ +static sl_bt_gattdb_value_type_t map_value_type(uint8_t datatype) +{ + switch (datatype) { + case GATTDB_DATATYPE_FIXED_LENGTH_VALUE: + return sl_bt_gattdb_fixed_length_value; + + case GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE: + return sl_bt_gattdb_variable_length_value; + + case GATTDB_DATATYPE_USER_VALUE: + return sl_bt_gattdb_user_managed_value; + + default: + // For value types not being supported by dynamic GATT. + return sl_bt_gattdb_fixed_length_value; + } +} + +/***************************************************************************//** + * Convert the permissions property of an attribute according to the + * sl_bt_gattdb_descriptor_properties macros. + * + * @param[in] permissions. The permissions property of an attribute provided by + * gatt_db.c. + * @return The converted permissions ready to pass to the api. + ******************************************************************************/ +static uint16_t map_descriptor_property(uint16_t permissions) +{ + uint16_t property = 0x0000; + + property |= (permissions & GATTDB_PERMISSION_READ) ? SL_BT_GATTDB_DESCRIPTOR_READ : 0x0000; + property |= (permissions & GATTDB_PERMISSION_WRITE) ? SL_BT_GATTDB_DESCRIPTOR_WRITE : 0x0000; + property |= (permissions & GATTDB_PERMISSION_DISCOVERABLE) ? 0x0000 : SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY; + + return property; +} + +/***************************************************************************//** + * Get the value and its related length informations of an attribute. + * + * @param[in] attribute. An attribute from provided by gatt_db.c. + * @return The maximum length, length and the actual data of the attribute. + * @ref attribute_value_t. + ******************************************************************************/ +static attribute_value_t get_attribute_value(const sli_bt_gattdb_attribute_t *attribute) +{ + attribute_value_t value; + + switch (attribute->datatype) { + case GATTDB_DATATYPE_CONSTANT_VALUE: + value.max_len = attribute->constdata->len; + value.len = attribute->constdata->len; + value.data = attribute->constdata->data; + break; + + case GATTDB_DATATYPE_FIXED_LENGTH_VALUE: + value.max_len = attribute->dynamicdata->max_len; + value.len = attribute->dynamicdata->max_len; + value.data = attribute->dynamicdata->data; + break; + + case GATTDB_DATATYPE_VARIABLE_LENGTH_VALUE: + value.max_len = attribute->dynamicdata->max_len; + value.len = attribute->dynamicdata->len; + value.data = attribute->dynamicdata->data; + break; + + default: + // User managed values and other symbols. + value.max_len = 0; + value.len = 0; + value.data = NULL; + break; + } + + return value; +} + +/***************************************************************************//** + * Get the index of the first attrubute to be processed. + ******************************************************************************/ +static uint16_t get_start_index(void) +{ + uint16_t idx = 0; + // Check for Generic Attribute UUID (0x1801) + if ((gattdb.attributes[idx].constdata->len == 2) + && (gattdb.attributes[idx].constdata->data[0] == 0x01) + && (gattdb.attributes[idx].constdata->data[1] == 0x18)) { + for (idx = 1; idx < gattdb.attribute_num; idx++) { + // Find the next service declaration + if (IS_UUID_16(gattdb.attributes[idx].uuid) + && ((gattdb.uuid16[gattdb.attributes[idx].uuid] == PRIMARY_SERVICE_UUID) + || (gattdb.uuid16[gattdb.attributes[idx].uuid] == SECONDARY_SERVICE_UUID))) { + break; + } + } + } + return idx; +} diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.h b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.h index c524657..2f7ade7 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.h +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.h @@ -1,45 +1,45 @@ -/***************************************************************************//** - * @file - * @brief Composes the GATT database using the Dynamic GATT API. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_NCP_GATT_H -#define SL_NCP_GATT_H - -/***********************************************************************************************//** - * @addtogroup ncp_gatt - * @{ - **************************************************************************************************/ - -/**************************************************************************//** - * Bluetooth stack event handler. - * @param[in] evt Event coming from the Bluetooth stack. - *****************************************************************************/ -void sl_ncp_gatt_on_event(sl_bt_msg_t *evt); - -/** @} (end addtogroup ncp_gatt) */ -#endif // SL_NCP_GATT_H +/***************************************************************************//** + * @file + * @brief Composes the GATT database using the Dynamic GATT API. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_NCP_GATT_H +#define SL_NCP_GATT_H + +/***********************************************************************************************//** + * @addtogroup ncp_gatt + * @{ + **************************************************************************************************/ + +/**************************************************************************//** + * Bluetooth stack event handler. + * @param[in] evt Event coming from the Bluetooth stack. + *****************************************************************************/ +void sl_ncp_gatt_on_event(sl_bt_msg_t *evt); + +/** @} (end addtogroup ncp_gatt) */ +#endif // SL_NCP_GATT_H diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c index 0897675..c4b9015 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c @@ -1,186 +1,186 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Host Communication Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include "em_core.h" -#include "sl_bt_ncp_host.h" -#include "sl_simple_com.h" -#include "sl_ncp_host_com.h" -#include "app_assert.h" -#include "sl_component_catalog.h" -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -#include "sl_wake_lock.h" -#endif // SL_CATALOG_WAKE_LOCK_PRESENT - -// Uart reception buffer -typedef struct { - uint16_t len; - uint8_t buf[SL_NCP_HOST_COM_BUF_SIZE]; - bool available; -} buf_t; - -static volatile bool write_completed = false; -static buf_t buf = { 0 }; - -/**************************************************************************//** - * NCP host communication initialization. - *****************************************************************************/ -void sl_ncp_host_com_init(void) -{ - buf.len = 0; - // Register communication interface functions in adaptation layer - sl_status_t sc = sl_bt_api_initialize_nonblock(sl_ncp_host_com_write, - sl_ncp_host_com_read, - sl_ncp_host_com_peek); - app_assert(sc == SL_STATUS_OK, - "[E: 0x%04x] Failed to init Bluetooth NCP\n", - (int)sc); -} - -/**************************************************************************//** - * Transmit function - * - * Transmits len bytes of data from adaptation layer through Uart interface. - * - * @param[out] len Message lenght - * @param[out] data Message data - * - * @note After transmit the reception is automatically started. - *****************************************************************************/ -void sl_ncp_host_com_write(uint32_t len, uint8_t *data) -{ - write_completed = false; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Wake up other controller - sl_wake_lock_set_remote_req(); - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - sl_simple_com_transmit(len, data); - while (!write_completed) { - sl_simple_com_step(); - } - // Start to receive the response as soon as the transmit is completed - sl_simple_com_receive(); -} - -/**************************************************************************//** - * Receive function - * - * Copies received data from Uart interface to adaptation layer - * - * @param[out] len Message lenght - * @param[out] data Message data - * - * @return Received message length - *****************************************************************************/ -int32_t sl_ncp_host_com_read(uint32_t len, uint8_t *data) -{ - (void)data; - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - // Check if there is data in the buffer from Uart - if (len <= buf.len) { - // Copy data to adaptation layer - memcpy((void *)data, (void *)buf.buf, (size_t)len); - buf.len -= len; - memmove((void *)buf.buf, (void *)&buf.buf[len], buf.len); - } else { - len = -1; - } - CORE_EXIT_ATOMIC(); - return len; -} - -/**************************************************************************//** - * Gives back already received message length. - * - * This function checks if data arrived from Uart interface. This way the calls - * can be non blocking. - * - * @param[out] len Message lenght - * @param[out] data Message data - * - * @return Buffer length - *****************************************************************************/ -int32_t sl_ncp_host_com_peek(void) -{ - return buf.len; -} - -/**************************************************************************//** - * Uart transmit completed callback - * - * Called after Uart transmit is finished. - * - * @param[in] status Status of the transmission - *****************************************************************************/ -void sl_simple_com_transmit_cb(sl_status_t status) -{ - (void)status; - - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Signal other controller that it can go to sleep - sl_wake_lock_clear_remote_req(); - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - - write_completed = true; -} - -/**************************************************************************//** - * Uart receive completed callback - * - * Called after Uart receive is finished. Puts the message to the reception - * buffer. - * - * @param[in] status Status of the reception - * @param[in] len Received message length - * @param[in] data Data received - *****************************************************************************/ -void sl_simple_com_receive_cb(sl_status_t status, - uint32_t len, - uint8_t *data) -{ - (void)status; - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - // command fits into command buffer; otherwise discard it - if (len <= (sizeof(buf.buf) - buf.len)) { - memcpy((void *)&buf.buf[buf.len], (void *)data, (size_t)len); - buf.len += len; - } - CORE_EXIT_ATOMIC(); -} - -bool sl_ncp_host_is_ok_to_sleep(void) -{ - if (buf.len != 0) { - return false; - } else { - return true; - } -} +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Host Communication Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include "em_core.h" +#include "sl_bt_ncp_host.h" +#include "sl_simple_com.h" +#include "sl_ncp_host_com.h" +#include "app_assert.h" +#include "sl_component_catalog.h" +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +#include "sl_wake_lock.h" +#endif // SL_CATALOG_WAKE_LOCK_PRESENT + +// Uart reception buffer +typedef struct { + uint16_t len; + uint8_t buf[SL_NCP_HOST_COM_BUF_SIZE]; + bool available; +} buf_t; + +static volatile bool write_completed = false; +static buf_t buf = { 0 }; + +/**************************************************************************//** + * NCP host communication initialization. + *****************************************************************************/ +void sl_ncp_host_com_init(void) +{ + buf.len = 0; + // Register communication interface functions in adaptation layer + sl_status_t sc = sl_bt_api_initialize_nonblock(sl_ncp_host_com_write, + sl_ncp_host_com_read, + sl_ncp_host_com_peek); + app_assert(sc == SL_STATUS_OK, + "[E: 0x%04x] Failed to init Bluetooth NCP\n", + (int)sc); +} + +/**************************************************************************//** + * Transmit function + * + * Transmits len bytes of data from adaptation layer through Uart interface. + * + * @param[out] len Message lenght + * @param[out] data Message data + * + * @note After transmit the reception is automatically started. + *****************************************************************************/ +void sl_ncp_host_com_write(uint32_t len, uint8_t *data) +{ + write_completed = false; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Wake up other controller + sl_wake_lock_set_remote_req(); + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + sl_simple_com_transmit(len, data); + while (!write_completed) { + sl_simple_com_step(); + } + // Start to receive the response as soon as the transmit is completed + sl_simple_com_receive(); +} + +/**************************************************************************//** + * Receive function + * + * Copies received data from Uart interface to adaptation layer + * + * @param[out] len Message lenght + * @param[out] data Message data + * + * @return Received message length + *****************************************************************************/ +int32_t sl_ncp_host_com_read(uint32_t len, uint8_t *data) +{ + (void)data; + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + // Check if there is data in the buffer from Uart + if (len <= buf.len) { + // Copy data to adaptation layer + memcpy((void *)data, (void *)buf.buf, (size_t)len); + buf.len -= len; + memmove((void *)buf.buf, (void *)&buf.buf[len], buf.len); + } else { + len = -1; + } + CORE_EXIT_ATOMIC(); + return len; +} + +/**************************************************************************//** + * Gives back already received message length. + * + * This function checks if data arrived from Uart interface. This way the calls + * can be non blocking. + * + * @param[out] len Message lenght + * @param[out] data Message data + * + * @return Buffer length + *****************************************************************************/ +int32_t sl_ncp_host_com_peek(void) +{ + return buf.len; +} + +/**************************************************************************//** + * Uart transmit completed callback + * + * Called after Uart transmit is finished. + * + * @param[in] status Status of the transmission + *****************************************************************************/ +void sl_simple_com_transmit_cb(sl_status_t status) +{ + (void)status; + + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Signal other controller that it can go to sleep + sl_wake_lock_clear_remote_req(); + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + + write_completed = true; +} + +/**************************************************************************//** + * Uart receive completed callback + * + * Called after Uart receive is finished. Puts the message to the reception + * buffer. + * + * @param[in] status Status of the reception + * @param[in] len Received message length + * @param[in] data Data received + *****************************************************************************/ +void sl_simple_com_receive_cb(sl_status_t status, + uint32_t len, + uint8_t *data) +{ + (void)status; + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + // command fits into command buffer; otherwise discard it + if (len <= (sizeof(buf.buf) - buf.len)) { + memcpy((void *)&buf.buf[buf.len], (void *)data, (size_t)len); + buf.len += len; + } + CORE_EXIT_ATOMIC(); +} + +bool sl_ncp_host_is_ok_to_sleep(void) +{ + if (buf.len != 0) { + return false; + } else { + return true; + } +} diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.h b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.h index af99b33..100b373 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.h +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.h @@ -1,62 +1,62 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Host Communication Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_NCP_HOST_COM_H -#define SL_NCP_HOST_COM_H - -/***********************************************************************************************//** - * @addtogroup ncp_host_com - * @{ - **************************************************************************************************/ - -#include "sl_ncp_host_com_config.h" - -/**************************************************************************//** - * NCP host communication initialization. - *****************************************************************************/ -void sl_ncp_host_com_init(void); - -/**************************************************************************//** - * Transmit function - *****************************************************************************/ -void sl_ncp_host_com_write(uint32_t len, uint8_t *data); - -/**************************************************************************//** - * Receive function - *****************************************************************************/ -int32_t sl_ncp_host_com_read(uint32_t len, uint8_t *data); - -/**************************************************************************//** - * Gives back already received message length. - *****************************************************************************/ -int32_t sl_ncp_host_com_peek(void); - -bool sl_ncp_host_is_ok_to_sleep(void); -/** @} (end addtogroup ncp_host_com) */ -#endif // SL_NCP_HOST_COM_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Host Communication Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_NCP_HOST_COM_H +#define SL_NCP_HOST_COM_H + +/***********************************************************************************************//** + * @addtogroup ncp_host_com + * @{ + **************************************************************************************************/ + +#include "sl_ncp_host_com_config.h" + +/**************************************************************************//** + * NCP host communication initialization. + *****************************************************************************/ +void sl_ncp_host_com_init(void); + +/**************************************************************************//** + * Transmit function + *****************************************************************************/ +void sl_ncp_host_com_write(uint32_t len, uint8_t *data); + +/**************************************************************************//** + * Receive function + *****************************************************************************/ +int32_t sl_ncp_host_com_read(uint32_t len, uint8_t *data); + +/**************************************************************************//** + * Gives back already received message length. + *****************************************************************************/ +int32_t sl_ncp_host_com_peek(void); + +bool sl_ncp_host_is_ok_to_sleep(void); +/** @} (end addtogroup ncp_host_com) */ +#endif // SL_NCP_HOST_COM_H diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h index 666d39a..9010f65 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h @@ -1,83 +1,83 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_H -#define SL_SIMPLE_COM_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -#include -#include "sl_status.h" - -/**************************************************************************//** - * Simple Comm Init. - *****************************************************************************/ -void sl_simple_com_init(void); - -/**************************************************************************//** - * Step function (used in CPC mode) - *****************************************************************************/ -void sl_simple_com_step(void); - -/**************************************************************************//** - * Transmit function - *****************************************************************************/ -void sl_simple_com_transmit(uint32_t len, const uint8_t *data); - -/**************************************************************************//** - * Transmit completed callback - *****************************************************************************/ -void sl_simple_com_transmit_cb(sl_status_t status); - -/**************************************************************************//** - * Receive function (used in UART mode) - *****************************************************************************/ -void sl_simple_com_receive(void); - -/**************************************************************************//** - * Receive completed callback - *****************************************************************************/ -void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data); - -/**************************************************************************//** - * OS initialization function - if the OS is present - *****************************************************************************/ -void sl_simple_com_os_task_init(void); - -/**************************************************************************//** - * Function to trigger the OS task to proceed - if the OS is present - *****************************************************************************/ -void sl_simple_com_os_task_proceed(void); - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_H +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_H +#define SL_SIMPLE_COM_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +#include +#include "sl_status.h" + +/**************************************************************************//** + * Simple Comm Init. + *****************************************************************************/ +void sl_simple_com_init(void); + +/**************************************************************************//** + * Step function (used in CPC mode) + *****************************************************************************/ +void sl_simple_com_step(void); + +/**************************************************************************//** + * Transmit function + *****************************************************************************/ +void sl_simple_com_transmit(uint32_t len, const uint8_t *data); + +/**************************************************************************//** + * Transmit completed callback + *****************************************************************************/ +void sl_simple_com_transmit_cb(sl_status_t status); + +/**************************************************************************//** + * Receive function (used in UART mode) + *****************************************************************************/ +void sl_simple_com_receive(void); + +/**************************************************************************//** + * Receive completed callback + *****************************************************************************/ +void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data); + +/**************************************************************************//** + * OS initialization function - if the OS is present + *****************************************************************************/ +void sl_simple_com_os_task_init(void); + +/**************************************************************************//** + * Function to trigger the OS task to proceed - if the OS is present + *****************************************************************************/ +void sl_simple_com_os_task_proceed(void); + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_H diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c index ae93a2d..9fd7180 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c @@ -1,211 +1,211 @@ -/***************************************************************************//** - * @file - * @brief Robust Communication - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -// ----------------------------------------------------------------------------- -// Includes -#include -#include -#include "sl_simple_com_robust.h" -#ifndef HOST_TOOLCHAIN -#include "sl_simple_com_config.h" -#else // HOST_TOOLCHAIN -#include "host_comm_config.h" -#endif // HOST_TOOLCHAIN - -#define PREAMBLE_BYTE 0b01011010 // 0x5A -#define MAX_PAYLOAD_LENGTH 2047 -#define PAYLOAD_LENGTH_MASK 0b11100000 -#define CRC_PRESENT_FLAG 0b00010000 - -// ----------------------------------------------------------------------------- -// Private function declarations - -/**************************************************************************//** - * Calculate CRC-4 checksum using the x^4 + x + 1 polynomial - * - * @param[in] data pointer to the input data - * @param[in] len length of the input data in nibbles - * @return CRC-4 checksum - *****************************************************************************/ -static uint8_t crc4(const uint8_t *data, size_t len); - -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -/**************************************************************************//** - * Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial - * - * @param[in] data pointer to the input data - * @param[in] len size of the input data in bytes - * @return CRC-8 checksum - *****************************************************************************/ -static uint8_t crc8(const uint8_t *data, size_t len); -#endif - -// ----------------------------------------------------------------------------- -// Private function definitions - -// Calculate CRC-4 checksum using the x^4 + x + 1 polynomial -uint8_t crc4(const uint8_t *data, size_t len) -{ - static const uint8_t table[] = { - 0x0, 0x7, 0xe, 0x9, 0x5, 0x2, 0xb, 0xc, 0xa, 0xd, 0x4, 0x3, 0xf, 0x8, 0x1, 0x6 - }; - - uint8_t crc = 0xa; // CRC value of the preamble 0x5A - for (size_t i = 0; i < len; i++) { - uint8_t shift = i % 2 == 0 ? 4 : 0; // high nibbles have even index - uint8_t nibble = (data[i / 2] >> shift) & 0x0F; - crc = table[crc ^ nibble]; - } - return crc; -} - -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -// Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial -static uint8_t crc8(const uint8_t *data, size_t len) -{ - uint32_t crc = 0; // initial value - for (size_t i = 0; i < len; i++) { - crc ^= data[i] << 8; - for (size_t j = 8; j > 0; j--) { - if (crc & 0x8000) { - crc ^= (0x1070 << 3); - } - crc <<= 1; - } - } - return (uint8_t)(crc >> 8); -} -#endif - -// ----------------------------------------------------------------------------- -// Public function definitions - -// Pack data between preamble byte and (if turned on) CRC checksum -size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, - const uint8_t *data, - uint16_t len) -{ - if (packed_data_ptr == NULL || data == NULL || len > MAX_PAYLOAD_LENGTH) { - return 0; - } - size_t packed_data_size = sl_simple_com_robust_get_pack_buffer_size(len); - - // Building the 3 header bytes: preamble (1 byte), - // Payload length (11 bits), CRC present flag (1 bit), header CRC-4 (4 bits) - packed_data_ptr[0] = PREAMBLE_BYTE; - // 2nd byte of the header contains the lower 8 bits of payload length - packed_data_ptr[1] = (uint8_t)len; - // Upper 3 bits of the 3rd byte of the header contains the higher 3 bits of payload length - packed_data_ptr[2] = (uint8_t)((len >> 3) & PAYLOAD_LENGTH_MASK); -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - packed_data_ptr[2] |= CRC_PRESENT_FLAG; -#endif - // Calculate CRC value for header, exclude preamble - packed_data_ptr[2] |= crc4(packed_data_ptr + 1, 3); - - // Payload - memcpy(&packed_data_ptr[SL_SIMPLE_COM_ROBUST_HEADER_SIZE], data, len); - - // CRC-8 -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - packed_data_ptr[packed_data_size - 1] = crc8(data, len); -#endif - return packed_data_size; -} - -// Unpack packets from byte stream looking for valid headers -sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, - size_t len) -{ - sl_simple_com_robust_result_t result = { - .status = SL_STATUS_FAIL, - .payload = NULL, - .payload_size = 0, - .processed = 0 - }; - - if (data == NULL) { - result.status = SL_STATUS_NULL_POINTER; - return result; - } - if (len <= SL_SIMPLE_COM_ROBUST_HEADER_SIZE) { - result.status = SL_STATUS_EMPTY; - return result; - } - - // Find and validate the message header - size_t margin = len - SL_SIMPLE_COM_ROBUST_HEADER_SIZE; - while ((data[result.processed] != PREAMBLE_BYTE - || crc4(data + result.processed + 1, 4) != 0) - && result.processed < margin) { - result.processed++; - } - // No valid frame found - if (result.processed >= margin) { - result.status = SL_STATUS_NOT_FOUND; - return result; - } - - // Shift input data to the beginning of the frame - data += result.processed; - len -= result.processed; - - // Check payload CRC flag - bool crc_present = (data[2] & CRC_PRESENT_FLAG) != 0; - - // Get payload length from header (11 bits) - result.payload_size = data[1] | ((data[2] & PAYLOAD_LENGTH_MASK) << 3); - - // Check if the incoming data contains the whole payload - size_t message_size = SL_SIMPLE_COM_ROBUST_HEADER_SIZE + result.payload_size; - if (crc_present) { - message_size++; - } - - if (len < message_size) { - result.status = SL_STATUS_FAIL; - return result; - } - - result.processed += message_size; - result.payload = data + SL_SIMPLE_COM_ROBUST_HEADER_SIZE; - - // If payload CRC is present, validate -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - if (crc_present) { - if (crc8(result.payload, result.payload_size + 1) != 0) { - result.status = SL_STATUS_FAIL; - return result; - } - } -#endif // SL_SIMPLE_COM_ROBUST_CRC - - result.status = SL_STATUS_OK; - return result; -} +/***************************************************************************//** + * @file + * @brief Robust Communication + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +// ----------------------------------------------------------------------------- +// Includes +#include +#include +#include "sl_simple_com_robust.h" +#ifndef HOST_TOOLCHAIN +#include "sl_simple_com_config.h" +#else // HOST_TOOLCHAIN +#include "host_comm_config.h" +#endif // HOST_TOOLCHAIN + +#define PREAMBLE_BYTE 0b01011010 // 0x5A +#define MAX_PAYLOAD_LENGTH 2047 +#define PAYLOAD_LENGTH_MASK 0b11100000 +#define CRC_PRESENT_FLAG 0b00010000 + +// ----------------------------------------------------------------------------- +// Private function declarations + +/**************************************************************************//** + * Calculate CRC-4 checksum using the x^4 + x + 1 polynomial + * + * @param[in] data pointer to the input data + * @param[in] len length of the input data in nibbles + * @return CRC-4 checksum + *****************************************************************************/ +static uint8_t crc4(const uint8_t *data, size_t len); + +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +/**************************************************************************//** + * Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial + * + * @param[in] data pointer to the input data + * @param[in] len size of the input data in bytes + * @return CRC-8 checksum + *****************************************************************************/ +static uint8_t crc8(const uint8_t *data, size_t len); +#endif + +// ----------------------------------------------------------------------------- +// Private function definitions + +// Calculate CRC-4 checksum using the x^4 + x + 1 polynomial +uint8_t crc4(const uint8_t *data, size_t len) +{ + static const uint8_t table[] = { + 0x0, 0x7, 0xe, 0x9, 0x5, 0x2, 0xb, 0xc, 0xa, 0xd, 0x4, 0x3, 0xf, 0x8, 0x1, 0x6 + }; + + uint8_t crc = 0xa; // CRC value of the preamble 0x5A + for (size_t i = 0; i < len; i++) { + uint8_t shift = i % 2 == 0 ? 4 : 0; // high nibbles have even index + uint8_t nibble = (data[i / 2] >> shift) & 0x0F; + crc = table[crc ^ nibble]; + } + return crc; +} + +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +// Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial +static uint8_t crc8(const uint8_t *data, size_t len) +{ + uint32_t crc = 0; // initial value + for (size_t i = 0; i < len; i++) { + crc ^= data[i] << 8; + for (size_t j = 8; j > 0; j--) { + if (crc & 0x8000) { + crc ^= (0x1070 << 3); + } + crc <<= 1; + } + } + return (uint8_t)(crc >> 8); +} +#endif + +// ----------------------------------------------------------------------------- +// Public function definitions + +// Pack data between preamble byte and (if turned on) CRC checksum +size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, + const uint8_t *data, + uint16_t len) +{ + if (packed_data_ptr == NULL || data == NULL || len > MAX_PAYLOAD_LENGTH) { + return 0; + } + size_t packed_data_size = sl_simple_com_robust_get_pack_buffer_size(len); + + // Building the 3 header bytes: preamble (1 byte), + // Payload length (11 bits), CRC present flag (1 bit), header CRC-4 (4 bits) + packed_data_ptr[0] = PREAMBLE_BYTE; + // 2nd byte of the header contains the lower 8 bits of payload length + packed_data_ptr[1] = (uint8_t)len; + // Upper 3 bits of the 3rd byte of the header contains the higher 3 bits of payload length + packed_data_ptr[2] = (uint8_t)((len >> 3) & PAYLOAD_LENGTH_MASK); +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + packed_data_ptr[2] |= CRC_PRESENT_FLAG; +#endif + // Calculate CRC value for header, exclude preamble + packed_data_ptr[2] |= crc4(packed_data_ptr + 1, 3); + + // Payload + memcpy(&packed_data_ptr[SL_SIMPLE_COM_ROBUST_HEADER_SIZE], data, len); + + // CRC-8 +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + packed_data_ptr[packed_data_size - 1] = crc8(data, len); +#endif + return packed_data_size; +} + +// Unpack packets from byte stream looking for valid headers +sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, + size_t len) +{ + sl_simple_com_robust_result_t result = { + .status = SL_STATUS_FAIL, + .payload = NULL, + .payload_size = 0, + .processed = 0 + }; + + if (data == NULL) { + result.status = SL_STATUS_NULL_POINTER; + return result; + } + if (len <= SL_SIMPLE_COM_ROBUST_HEADER_SIZE) { + result.status = SL_STATUS_EMPTY; + return result; + } + + // Find and validate the message header + size_t margin = len - SL_SIMPLE_COM_ROBUST_HEADER_SIZE; + while ((data[result.processed] != PREAMBLE_BYTE + || crc4(data + result.processed + 1, 4) != 0) + && result.processed < margin) { + result.processed++; + } + // No valid frame found + if (result.processed >= margin) { + result.status = SL_STATUS_NOT_FOUND; + return result; + } + + // Shift input data to the beginning of the frame + data += result.processed; + len -= result.processed; + + // Check payload CRC flag + bool crc_present = (data[2] & CRC_PRESENT_FLAG) != 0; + + // Get payload length from header (11 bits) + result.payload_size = data[1] | ((data[2] & PAYLOAD_LENGTH_MASK) << 3); + + // Check if the incoming data contains the whole payload + size_t message_size = SL_SIMPLE_COM_ROBUST_HEADER_SIZE + result.payload_size; + if (crc_present) { + message_size++; + } + + if (len < message_size) { + result.status = SL_STATUS_FAIL; + return result; + } + + result.processed += message_size; + result.payload = data + SL_SIMPLE_COM_ROBUST_HEADER_SIZE; + + // If payload CRC is present, validate +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + if (crc_present) { + if (crc8(result.payload, result.payload_size + 1) != 0) { + result.status = SL_STATUS_FAIL; + return result; + } + } +#endif // SL_SIMPLE_COM_ROBUST_CRC + + result.status = SL_STATUS_OK; + return result; +} diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h index c3e74f7..d41ea47 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h @@ -1,96 +1,96 @@ -/***************************************************************************//** - * @file - * @brief Robust Communication Interface - * Packeting layer providing reliable communication with guaranteeing data - * integrity. This module can be used to pack bytes between a header and a CRC - * value and unpack and validate packets from a data stream. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_ROBUST_H -#define SL_SIMPLE_COM_ROBUST_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -#include -#include -#include "sl_status.h" -#ifndef HOST_TOOLCHAIN -#include "sl_simple_com_config.h" -#else // HOST_TOOLCHAIN -#include "host_comm_config.h" -#endif // HOST_TOOLCHAIN - -#define SL_SIMPLE_COM_ROBUST_HEADER_SIZE 3 - -// Get required buffer size for packed data -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE + 1) -#else // SL_SIMPLE_COM_ROBUST_CRC -#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE) -#endif // SL_SIMPLE_COM_ROBUST_CRC - -typedef struct { - sl_status_t status; // SL_STATUS_OK if a packet was found and validated with success - uint8_t *payload; // Pointer to the beginning of the payload - size_t payload_size; // Payload length in bytes - size_t processed; // Number of bytes processed from the input buffer -} sl_simple_com_robust_result_t; - -/**************************************************************************//** - * Pack data between preamble byte and (if turned on) CRC checksum - * This function adds a 3 byte header containing preamble byte, payload - * length, CRC flag and CRC value to the header. If CRC is required an 8 bit - * CRC value will be calculated for the payload and added to the end of packet. - * - * @param[out] packed_data_ptr pointer where the packed data should be loaded - * @param[in] data pointer to the data to be packed - * @param[in] len size of the data to be packed - * @return the size of packed data - *****************************************************************************/ -size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, - const uint8_t *data, - uint16_t len); - -/**************************************************************************//** - * Unpack packets from byte stream looking for valid headers. - * This function searches valid headers and extracts payload after the header - * into destination buffer. Header is validated by 4 bit header CRC and payload - * can be also validated by optional CRC check. - * - * @param[in] data pointer to the data to be unpacked - * @param[in] len size of the data to be unpacked - * @return the result of the action - *****************************************************************************/ -sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, - size_t len); - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_ROBUST_H +/***************************************************************************//** + * @file + * @brief Robust Communication Interface + * Packeting layer providing reliable communication with guaranteeing data + * integrity. This module can be used to pack bytes between a header and a CRC + * value and unpack and validate packets from a data stream. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_ROBUST_H +#define SL_SIMPLE_COM_ROBUST_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +#include +#include +#include "sl_status.h" +#ifndef HOST_TOOLCHAIN +#include "sl_simple_com_config.h" +#else // HOST_TOOLCHAIN +#include "host_comm_config.h" +#endif // HOST_TOOLCHAIN + +#define SL_SIMPLE_COM_ROBUST_HEADER_SIZE 3 + +// Get required buffer size for packed data +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE + 1) +#else // SL_SIMPLE_COM_ROBUST_CRC +#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE) +#endif // SL_SIMPLE_COM_ROBUST_CRC + +typedef struct { + sl_status_t status; // SL_STATUS_OK if a packet was found and validated with success + uint8_t *payload; // Pointer to the beginning of the payload + size_t payload_size; // Payload length in bytes + size_t processed; // Number of bytes processed from the input buffer +} sl_simple_com_robust_result_t; + +/**************************************************************************//** + * Pack data between preamble byte and (if turned on) CRC checksum + * This function adds a 3 byte header containing preamble byte, payload + * length, CRC flag and CRC value to the header. If CRC is required an 8 bit + * CRC value will be calculated for the payload and added to the end of packet. + * + * @param[out] packed_data_ptr pointer where the packed data should be loaded + * @param[in] data pointer to the data to be packed + * @param[in] len size of the data to be packed + * @return the size of packed data + *****************************************************************************/ +size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, + const uint8_t *data, + uint16_t len); + +/**************************************************************************//** + * Unpack packets from byte stream looking for valid headers. + * This function searches valid headers and extracts payload after the header + * into destination buffer. Header is validated by 4 bit header CRC and payload + * can be also validated by optional CRC check. + * + * @param[in] data pointer to the data to be unpacked + * @param[in] len size of the data to be unpacked + * @return the result of the action + *****************************************************************************/ +sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, + size_t len); + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_ROBUST_H diff --git a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c index 5a0588f..46d3c85 100644 --- a/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c +++ b/locator_host/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c @@ -1,584 +1,584 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include -#include "sl_status.h" -#include "em_common.h" -#include "em_core.h" -#include "sl_uartdrv_instances.h" -#include "app_assert.h" -#include "sl_simple_com.h" -#include "sl_simple_com_config.h" -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 -#include "sl_simple_com_robust.h" -#endif // SL_SIMPLE_COM_ROBUST -#ifdef EFR32BG1_USART_E202_WORKAROUND -#include "sl_sleeptimer.h" -#endif // EFR32BG1_USART_E202_WORKAROUND - -// Store UARTDRV handle to use with Simple COM -static UARTDRV_Handle_t uartdrv_handle = NULL; -static IRQn_Type irq_number; - -// store the maximum waiting time for a callback -static uint32_t time_to_wait_tx_callback = 0; - -// store the returned values of TX callback -typedef struct { - UARTDRV_Handle_t handle; - uint32_t timeout; - sl_status_t status; - bool finished; -} tx_cb_sig; - -static tx_cb_sig tx_cb_signal = { 0 }; - -// UART receive and transmit buffers -static uint8_t rx_buf[SL_SIMPLE_COM_RX_BUF_SIZE] = { 0 }; -static uint8_t tx_buf[SL_SIMPLE_COM_TX_BUF_SIZE] = { 0 }; - -#ifdef EFR32BG1_USART_E202_WORKAROUND -// Internal timer and counter for receive -// EFR32BG1 - USART_E202 workaround -static sl_sleeptimer_timer_handle_t receive_timer; -static uint32_t received_count = 0; -#endif // EFR32BG1_USART_E202_WORKAROUND - -// Internal UART receive and transmit callback -static void transmit_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); -static void receive_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); -// Helper functions to ensure reception -static Ecode_t cancel_receive(UARTDRV_Handle_t handle); -static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer); -static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer); - -static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle); - -static Ecode_t uart_receive_start(UARTDRV_Handle_t handle); - -void sli_simple_com_isr(void); - -// ----------------------------------------------------------------------------- -// Public functions (API implementation) - -/**************************************************************************//** - * Simple COM initialization function - *****************************************************************************/ -void sl_simple_com_init(void) -{ - // clear RX and TX buffers - memset(rx_buf, 0, sizeof(rx_buf)); - memset(tx_buf, 0, sizeof(tx_buf)); - - // Get the default UARTDRV handle to use for Simple COM - uartdrv_handle = sl_uartdrv_get_default(); - irq_number = irq_number_from_handle(uartdrv_handle); - app_assert(irq_number >= (IRQn_Type)(0), "Unknown UARTDRV handle\n"); - - // calculate the maximum amount of time to wait for UART TX buffer to empty - time_to_wait_tx_callback = CMU_ClockFreqGet(cmuClock_CORE) - / USART_BaudrateGet(uartdrv_handle->peripheral.uart) - * 4; -} - -/**************************************************************************//** - * Simple COM step function - *****************************************************************************/ -void sl_simple_com_step(void) -{ - if (tx_cb_signal.finished) { - // Wait until UART finished transfer - if ((!(UARTDRV_GetPeripheralStatus(tx_cb_signal.handle) & UARTDRV_STATUS_TXC)) - && (tx_cb_signal.timeout < time_to_wait_tx_callback)) { - tx_cb_signal.timeout++; - sl_simple_com_os_task_proceed(); - } else { - // Clear TX buffer - tx_cb_signal.timeout = 0; - tx_cb_signal.finished = false; - // Call public callback API - sl_simple_com_transmit_cb(ECODE_EMDRV_UARTDRV_OK == tx_cb_signal.status - ? SL_STATUS_OK : SL_STATUS_FAIL); - } - } -} - -/**************************************************************************//** - * UART transmit function - * - * Transmits len bytes of data through the UART interface using DMA. - * - * @param[out] len Message length - * @param[out] data Message data - *****************************************************************************/ -void sl_simple_com_transmit(uint32_t len, const uint8_t *data) -{ - Ecode_t ec; - // Make a copy of the data to be sent to guarantee its integrity until - // transmission completes -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 - app_assert(sl_simple_com_robust_get_pack_buffer_size(len) <= SL_SIMPLE_COM_TX_BUF_SIZE, - "TX length is bigger than allocated buffer\n"); - len = sl_simple_com_robust_pack_data(tx_buf, data, (size_t)len); -#else // SL_SIMPLE_COM_ROBUST - app_assert(len <= SL_SIMPLE_COM_TX_BUF_SIZE, - "TX length is bigger than allocated buffer\n"); - memcpy((void *)tx_buf, (void *)data, (size_t)len); -#endif // SL_SIMPLE_COM_ROBUST - - // Transmit data using a non-blocking transmit function - ec = UARTDRV_Transmit(uartdrv_handle, - tx_buf, - len, - transmit_cb); - app_assert(ECODE_EMDRV_UARTDRV_OK == ec, - "[E: 0x%04x] Failed to start transmitting\n", - (int)ec); - (void)ec; - sl_simple_com_os_task_proceed(); -} - -/**************************************************************************//** - * UART receive function - * - * Starts reception on UART interface using DMA. - * - * @note The problem with standard UART reception is that it needs the exact - * amount of bytes to read. This implementation starts a timer to measure idle - * time on the bus and based on that puts the received message into the buffer. - *****************************************************************************/ -void sl_simple_com_receive(void) -{ - Ecode_t ec; - // Clear pending RX interrupt flag in NVIC - NVIC_ClearPendingIRQ(irq_number); - NVIC_EnableIRQ(irq_number); - // Setup RX timeout to 255 bit-time - uartdrv_handle->peripheral.uart->TIMECMP1 = \ - (USART_TIMECMP1_TSTOP_RXACT - | USART_TIMECMP1_TSTART_RXEOF - | (0xff << _USART_TIMECMP1_TCMPVAL_SHIFT)); - // Clear any USART interrupt flags - USART_IntClear(uartdrv_handle->peripheral.uart, _USART_IF_MASK); - USART_IntEnable(uartdrv_handle->peripheral.uart, USART_IF_TXIDLE | USART_IF_TCMP1); - ec = uart_receive_start(uartdrv_handle); - app_assert(ECODE_EMDRV_UARTDRV_OK == ec, - "[E: 0x%04x] Failed to start receiving\n", - (int)ec); - (void)ec; -} - -/**************************************************************************//** - * UART transmit completed callback - * - * Called after UART transmit is finished. - * - * @param[in] status Status of the transmission - * - * @note Weak implementation - * Called after DMA is complete, the UART transmission might be still ongoing - *****************************************************************************/ -SL_WEAK void sl_simple_com_transmit_cb(sl_status_t status) -{ - (void)status; -} - -/**************************************************************************//** - * UART receive completed callback - * - * Called after UART receive is finished. - * - * @param[in] status Status of the reception - * @param[in] len Received message length - * @param[in] data Data received - * - * @note Weak implementation - *****************************************************************************/ -SL_WEAK void sl_simple_com_receive_cb(sl_status_t status, - uint32_t len, - uint8_t *data) -{ - (void)status; - (void)data; - (void)len; -} - -// ----------------------------------------------------------------------------- -// Private functions - -#ifdef EFR32BG1_USART_E202_WORKAROUND -// EFR32BG1 - USART_E202 workaround -static void timer_callback(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - (void)handle; - (void)data; - - // Assert nRTS - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); - } - - // Get received bytes - uint8_t* buffer = NULL; - uint32_t received = 0; - uint32_t remaining = 0; - UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); - - // if no change in that time callback is needed - if (received_count == received) { - sl_sleeptimer_stop_timer(&receive_timer); - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - - // cancel previous block receive operation - (void)cancel_receive(uartdrv_handle); - uart_receive_start(uartdrv_handle); - CORE_EXIT_ATOMIC(); - received_count = 0; - } else { - // otherwise register received bytes for the next run - received_count = received; - } -} - -#endif // EFR32BG1_USART_E202_WORKAROUND - -/****************************************************************************** - * UART interrupt handler - * - * Called when the set timer for tx idle states finished. - * - * @note automatically restarts the timer and starts a new reception. - * @note TODO: this should be provided by UARTDRV - *****************************************************************************/ -void sli_simple_com_isr(void) -{ - // RX timeout, stop transfer and handle what we got in buffer - if (uartdrv_handle->peripheral.uart->IF & USART_IF_TCMP1) { - CORE_DECLARE_IRQ_STATE; - - // Assert nRTS - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); - } - - CORE_ENTER_ATOMIC(); - // stop the timer - uartdrv_handle->peripheral.uart->TIMECMP1 &= \ - ~_USART_TIMECMP1_TSTART_MASK; - uartdrv_handle->peripheral.uart->TIMECMP1 |= \ - USART_TIMECMP1_TSTART_RXEOF; - // clear timer interrupt - USART_IntClear(uartdrv_handle->peripheral.uart, - USART_IF_TCMP1); -#ifdef EFR32BG1_USART_E202_WORKAROUND - // EFR32BG1 - USART_E202 workaround - sl_sleeptimer_stop_timer(&receive_timer); - sl_sleeptimer_start_periodic_timer( - &receive_timer, - sl_sleeptimer_ms_to_tick(1), - timer_callback, - NULL, - 0, - 0); - uint8_t* buffer = NULL; - uint32_t received = 0; - uint32_t remaining = 0; - UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); - received_count = received; -#else - // cancel previous block receive operation - (void)cancel_receive(uartdrv_handle); - uart_receive_start(uartdrv_handle); -#endif // EFR32BG1_USART_E202_WORKAROUND - CORE_EXIT_ATOMIC(); - } -} - -/****************************************************************************** - * Internal UART transmit completed callback - * - * Called after UART transmit is finished. - * - * @param[in] handle UART driver handle - * @param[in] transferStatus Status of the transfer - * @param[in] data Transmitted data - * @param[in] transferCount Number of sent bytes - * - * @note Calls public sl_simple_com_transmit_cb - * Called after DMA is complete, the UART transmission might be still ongoing - *****************************************************************************/ -static void transmit_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount) -{ - (void)data; - (void)transferCount; - - CORE_ATOMIC_SECTION( - tx_cb_signal.status = transferStatus; - tx_cb_signal.handle = handle; - tx_cb_signal.timeout = 0; - tx_cb_signal.finished = true; - ) - sl_simple_com_os_task_proceed(); -} - -/****************************************************************************** - * Internal UART receive completed callback - * - * Called after UART receive is finished. - * - * @param[in] handle UART driver handle - * @param[in] transferStatus Status of the transfer - * @param[in] data Received data - * @param[in] transferCount Number of received bytes - * - * @note Calls public sl_simple_com_receive_cb - *****************************************************************************/ -static void receive_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount) -{ - (void)handle; - -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 - if (transferCount > 0) { - sl_simple_com_robust_result_t result = sl_simple_com_robust_unpack_data(data, - transferCount); - - // Call public callback API - sl_simple_com_receive_cb((ECODE_EMDRV_UARTDRV_OK == transferStatus - ? SL_STATUS_OK : SL_STATUS_FAIL | result.status), - result.payload_size, - result.payload); - } else { -#else // SL_SIMPLE_COM_ROBUST - { -#endif // SL_SIMPLE_COM_ROBUST - // Call public callback API - sl_simple_com_receive_cb(ECODE_EMDRV_UARTDRV_OK == transferStatus - ? SL_STATUS_OK : SL_STATUS_FAIL, - transferCount, - data); - } - - sl_simple_com_os_task_proceed(); -} - -/****************************************************************************** - * Cancel previous block receive operation. - * - * @param[in] handle UART driver handle - *****************************************************************************/ -static Ecode_t cancel_receive(UARTDRV_Handle_t handle) -{ - UARTDRV_Buffer_t *rxBuffer; - Ecode_t status; - CORE_DECLARE_IRQ_STATE; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - CORE_ENTER_ATOMIC(); - if (handle->rxQueue->used == 0) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } - - // ------------------------------- - // Stop the current DMA transfer - (void)DMADRV_StopTransfer(handle->rxDmaCh); - handle->rxDmaActive = false; - // Update the transfer status of the active transfer - status = get_tail_buffer(handle->rxQueue, &rxBuffer); - // If aborting was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - EFM_ASSERT(rxBuffer != NULL); - (void)DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int *)&rxBuffer->itemsRemaining); - rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // ------------------------------- - // Dequeue all transfers and call callback - while (handle->rxQueue->used > 0) { - (void)dequeue_buffer(handle->rxQueue, &rxBuffer); - // Call the callback - if (rxBuffer->callback != NULL) { - if (rxBuffer->callback != NULL) { - rxBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_OK, - rxBuffer->data, - rxBuffer->transferCount - rxBuffer->itemsRemaining); - } - } - } - - // ------------------------------- - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Gets the buffer tail. - * - * @param[in] queue Input buffer - * @param[out] buffer Output buffer - *****************************************************************************/ -static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Dequeues buffer - * - * Moves through the buffer. - * - * @param[in] queue Input buffer - * @param[out] buffer Output buffer - *****************************************************************************/ -static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - queue->tail = (queue->tail + 1) % queue->size; - queue->used--; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Get NVIC IRQ number from UARTDRV handle - * - * @param[in] handle UART driver handle - * @return Interrupt number - *****************************************************************************/ -static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle) -{ - IRQn_Type irq_number = (IRQn_Type)(-1); - - switch ((uint32_t)handle->peripheral.uart) { -#if defined(USART0_BASE) - case USART0_BASE: - irq_number = USART0_RX_IRQn; - break; -#endif -#if defined(USART1_BASE) - case USART1_BASE: - irq_number = USART1_RX_IRQn; - break; -#endif -#if defined(USART2_BASE) - case USART2_BASE: - irq_number = USART2_RX_IRQn; - break; -#endif -#if defined(USART3_BASE) - case USART3_BASE: - irq_number = USART3_RX_IRQn; - break; -#endif - default: - app_assert(false, "Unknown UARTDRV handle\n"); - break; - } - - return irq_number; -} - -/****************************************************************************** - * Start / resume UARTDRV receiving - * - * @param[in] handle UART driver handle - * @return UARTDRV reported result of the operation - *****************************************************************************/ -static Ecode_t uart_receive_start(UARTDRV_Handle_t handle) -{ - Ecode_t ec = UARTDRV_Receive(handle, rx_buf, sizeof(rx_buf), receive_cb); - - if (ec == ECODE_EMDRV_UARTDRV_OK) { - // De-assert nRTS or send XON - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlAuto); - } - } - - return ec; -} -/****************************************************************************** - * Function to trigger the OS task to proceed - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK void sl_simple_com_os_task_proceed(void) -{ - // No action on bare metal implementation -} +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include "sl_status.h" +#include "em_common.h" +#include "em_core.h" +#include "sl_uartdrv_instances.h" +#include "app_assert.h" +#include "sl_simple_com.h" +#include "sl_simple_com_config.h" +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 +#include "sl_simple_com_robust.h" +#endif // SL_SIMPLE_COM_ROBUST +#ifdef EFR32BG1_USART_E202_WORKAROUND +#include "sl_sleeptimer.h" +#endif // EFR32BG1_USART_E202_WORKAROUND + +// Store UARTDRV handle to use with Simple COM +static UARTDRV_Handle_t uartdrv_handle = NULL; +static IRQn_Type irq_number; + +// store the maximum waiting time for a callback +static uint32_t time_to_wait_tx_callback = 0; + +// store the returned values of TX callback +typedef struct { + UARTDRV_Handle_t handle; + uint32_t timeout; + sl_status_t status; + bool finished; +} tx_cb_sig; + +static tx_cb_sig tx_cb_signal = { 0 }; + +// UART receive and transmit buffers +static uint8_t rx_buf[SL_SIMPLE_COM_RX_BUF_SIZE] = { 0 }; +static uint8_t tx_buf[SL_SIMPLE_COM_TX_BUF_SIZE] = { 0 }; + +#ifdef EFR32BG1_USART_E202_WORKAROUND +// Internal timer and counter for receive +// EFR32BG1 - USART_E202 workaround +static sl_sleeptimer_timer_handle_t receive_timer; +static uint32_t received_count = 0; +#endif // EFR32BG1_USART_E202_WORKAROUND + +// Internal UART receive and transmit callback +static void transmit_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); +static void receive_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); +// Helper functions to ensure reception +static Ecode_t cancel_receive(UARTDRV_Handle_t handle); +static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer); +static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer); + +static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle); + +static Ecode_t uart_receive_start(UARTDRV_Handle_t handle); + +void sli_simple_com_isr(void); + +// ----------------------------------------------------------------------------- +// Public functions (API implementation) + +/**************************************************************************//** + * Simple COM initialization function + *****************************************************************************/ +void sl_simple_com_init(void) +{ + // clear RX and TX buffers + memset(rx_buf, 0, sizeof(rx_buf)); + memset(tx_buf, 0, sizeof(tx_buf)); + + // Get the default UARTDRV handle to use for Simple COM + uartdrv_handle = sl_uartdrv_get_default(); + irq_number = irq_number_from_handle(uartdrv_handle); + app_assert(irq_number >= (IRQn_Type)(0), "Unknown UARTDRV handle\n"); + + // calculate the maximum amount of time to wait for UART TX buffer to empty + time_to_wait_tx_callback = CMU_ClockFreqGet(cmuClock_CORE) + / USART_BaudrateGet(uartdrv_handle->peripheral.uart) + * 4; +} + +/**************************************************************************//** + * Simple COM step function + *****************************************************************************/ +void sl_simple_com_step(void) +{ + if (tx_cb_signal.finished) { + // Wait until UART finished transfer + if ((!(UARTDRV_GetPeripheralStatus(tx_cb_signal.handle) & UARTDRV_STATUS_TXC)) + && (tx_cb_signal.timeout < time_to_wait_tx_callback)) { + tx_cb_signal.timeout++; + sl_simple_com_os_task_proceed(); + } else { + // Clear TX buffer + tx_cb_signal.timeout = 0; + tx_cb_signal.finished = false; + // Call public callback API + sl_simple_com_transmit_cb(ECODE_EMDRV_UARTDRV_OK == tx_cb_signal.status + ? SL_STATUS_OK : SL_STATUS_FAIL); + } + } +} + +/**************************************************************************//** + * UART transmit function + * + * Transmits len bytes of data through the UART interface using DMA. + * + * @param[out] len Message length + * @param[out] data Message data + *****************************************************************************/ +void sl_simple_com_transmit(uint32_t len, const uint8_t *data) +{ + Ecode_t ec; + // Make a copy of the data to be sent to guarantee its integrity until + // transmission completes +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 + app_assert(sl_simple_com_robust_get_pack_buffer_size(len) <= SL_SIMPLE_COM_TX_BUF_SIZE, + "TX length is bigger than allocated buffer\n"); + len = sl_simple_com_robust_pack_data(tx_buf, data, (size_t)len); +#else // SL_SIMPLE_COM_ROBUST + app_assert(len <= SL_SIMPLE_COM_TX_BUF_SIZE, + "TX length is bigger than allocated buffer\n"); + memcpy((void *)tx_buf, (void *)data, (size_t)len); +#endif // SL_SIMPLE_COM_ROBUST + + // Transmit data using a non-blocking transmit function + ec = UARTDRV_Transmit(uartdrv_handle, + tx_buf, + len, + transmit_cb); + app_assert(ECODE_EMDRV_UARTDRV_OK == ec, + "[E: 0x%04x] Failed to start transmitting\n", + (int)ec); + (void)ec; + sl_simple_com_os_task_proceed(); +} + +/**************************************************************************//** + * UART receive function + * + * Starts reception on UART interface using DMA. + * + * @note The problem with standard UART reception is that it needs the exact + * amount of bytes to read. This implementation starts a timer to measure idle + * time on the bus and based on that puts the received message into the buffer. + *****************************************************************************/ +void sl_simple_com_receive(void) +{ + Ecode_t ec; + // Clear pending RX interrupt flag in NVIC + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); + // Setup RX timeout to 255 bit-time + uartdrv_handle->peripheral.uart->TIMECMP1 = \ + (USART_TIMECMP1_TSTOP_RXACT + | USART_TIMECMP1_TSTART_RXEOF + | (0xff << _USART_TIMECMP1_TCMPVAL_SHIFT)); + // Clear any USART interrupt flags + USART_IntClear(uartdrv_handle->peripheral.uart, _USART_IF_MASK); + USART_IntEnable(uartdrv_handle->peripheral.uart, USART_IF_TXIDLE | USART_IF_TCMP1); + ec = uart_receive_start(uartdrv_handle); + app_assert(ECODE_EMDRV_UARTDRV_OK == ec, + "[E: 0x%04x] Failed to start receiving\n", + (int)ec); + (void)ec; +} + +/**************************************************************************//** + * UART transmit completed callback + * + * Called after UART transmit is finished. + * + * @param[in] status Status of the transmission + * + * @note Weak implementation + * Called after DMA is complete, the UART transmission might be still ongoing + *****************************************************************************/ +SL_WEAK void sl_simple_com_transmit_cb(sl_status_t status) +{ + (void)status; +} + +/**************************************************************************//** + * UART receive completed callback + * + * Called after UART receive is finished. + * + * @param[in] status Status of the reception + * @param[in] len Received message length + * @param[in] data Data received + * + * @note Weak implementation + *****************************************************************************/ +SL_WEAK void sl_simple_com_receive_cb(sl_status_t status, + uint32_t len, + uint8_t *data) +{ + (void)status; + (void)data; + (void)len; +} + +// ----------------------------------------------------------------------------- +// Private functions + +#ifdef EFR32BG1_USART_E202_WORKAROUND +// EFR32BG1 - USART_E202 workaround +static void timer_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + (void)handle; + (void)data; + + // Assert nRTS + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); + } + + // Get received bytes + uint8_t* buffer = NULL; + uint32_t received = 0; + uint32_t remaining = 0; + UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); + + // if no change in that time callback is needed + if (received_count == received) { + sl_sleeptimer_stop_timer(&receive_timer); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // cancel previous block receive operation + (void)cancel_receive(uartdrv_handle); + uart_receive_start(uartdrv_handle); + CORE_EXIT_ATOMIC(); + received_count = 0; + } else { + // otherwise register received bytes for the next run + received_count = received; + } +} + +#endif // EFR32BG1_USART_E202_WORKAROUND + +/****************************************************************************** + * UART interrupt handler + * + * Called when the set timer for tx idle states finished. + * + * @note automatically restarts the timer and starts a new reception. + * @note TODO: this should be provided by UARTDRV + *****************************************************************************/ +void sli_simple_com_isr(void) +{ + // RX timeout, stop transfer and handle what we got in buffer + if (uartdrv_handle->peripheral.uart->IF & USART_IF_TCMP1) { + CORE_DECLARE_IRQ_STATE; + + // Assert nRTS + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); + } + + CORE_ENTER_ATOMIC(); + // stop the timer + uartdrv_handle->peripheral.uart->TIMECMP1 &= \ + ~_USART_TIMECMP1_TSTART_MASK; + uartdrv_handle->peripheral.uart->TIMECMP1 |= \ + USART_TIMECMP1_TSTART_RXEOF; + // clear timer interrupt + USART_IntClear(uartdrv_handle->peripheral.uart, + USART_IF_TCMP1); +#ifdef EFR32BG1_USART_E202_WORKAROUND + // EFR32BG1 - USART_E202 workaround + sl_sleeptimer_stop_timer(&receive_timer); + sl_sleeptimer_start_periodic_timer( + &receive_timer, + sl_sleeptimer_ms_to_tick(1), + timer_callback, + NULL, + 0, + 0); + uint8_t* buffer = NULL; + uint32_t received = 0; + uint32_t remaining = 0; + UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); + received_count = received; +#else + // cancel previous block receive operation + (void)cancel_receive(uartdrv_handle); + uart_receive_start(uartdrv_handle); +#endif // EFR32BG1_USART_E202_WORKAROUND + CORE_EXIT_ATOMIC(); + } +} + +/****************************************************************************** + * Internal UART transmit completed callback + * + * Called after UART transmit is finished. + * + * @param[in] handle UART driver handle + * @param[in] transferStatus Status of the transfer + * @param[in] data Transmitted data + * @param[in] transferCount Number of sent bytes + * + * @note Calls public sl_simple_com_transmit_cb + * Called after DMA is complete, the UART transmission might be still ongoing + *****************************************************************************/ +static void transmit_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount) +{ + (void)data; + (void)transferCount; + + CORE_ATOMIC_SECTION( + tx_cb_signal.status = transferStatus; + tx_cb_signal.handle = handle; + tx_cb_signal.timeout = 0; + tx_cb_signal.finished = true; + ) + sl_simple_com_os_task_proceed(); +} + +/****************************************************************************** + * Internal UART receive completed callback + * + * Called after UART receive is finished. + * + * @param[in] handle UART driver handle + * @param[in] transferStatus Status of the transfer + * @param[in] data Received data + * @param[in] transferCount Number of received bytes + * + * @note Calls public sl_simple_com_receive_cb + *****************************************************************************/ +static void receive_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount) +{ + (void)handle; + +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 + if (transferCount > 0) { + sl_simple_com_robust_result_t result = sl_simple_com_robust_unpack_data(data, + transferCount); + + // Call public callback API + sl_simple_com_receive_cb((ECODE_EMDRV_UARTDRV_OK == transferStatus + ? SL_STATUS_OK : SL_STATUS_FAIL | result.status), + result.payload_size, + result.payload); + } else { +#else // SL_SIMPLE_COM_ROBUST + { +#endif // SL_SIMPLE_COM_ROBUST + // Call public callback API + sl_simple_com_receive_cb(ECODE_EMDRV_UARTDRV_OK == transferStatus + ? SL_STATUS_OK : SL_STATUS_FAIL, + transferCount, + data); + } + + sl_simple_com_os_task_proceed(); +} + +/****************************************************************************** + * Cancel previous block receive operation. + * + * @param[in] handle UART driver handle + *****************************************************************************/ +static Ecode_t cancel_receive(UARTDRV_Handle_t handle) +{ + UARTDRV_Buffer_t *rxBuffer; + Ecode_t status; + CORE_DECLARE_IRQ_STATE; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + CORE_ENTER_ATOMIC(); + if (handle->rxQueue->used == 0) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } + + // ------------------------------- + // Stop the current DMA transfer + (void)DMADRV_StopTransfer(handle->rxDmaCh); + handle->rxDmaActive = false; + // Update the transfer status of the active transfer + status = get_tail_buffer(handle->rxQueue, &rxBuffer); + // If aborting was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + EFM_ASSERT(rxBuffer != NULL); + (void)DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int *)&rxBuffer->itemsRemaining); + rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // ------------------------------- + // Dequeue all transfers and call callback + while (handle->rxQueue->used > 0) { + (void)dequeue_buffer(handle->rxQueue, &rxBuffer); + // Call the callback + if (rxBuffer->callback != NULL) { + if (rxBuffer->callback != NULL) { + rxBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_OK, + rxBuffer->data, + rxBuffer->transferCount - rxBuffer->itemsRemaining); + } + } + } + + // ------------------------------- + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Gets the buffer tail. + * + * @param[in] queue Input buffer + * @param[out] buffer Output buffer + *****************************************************************************/ +static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Dequeues buffer + * + * Moves through the buffer. + * + * @param[in] queue Input buffer + * @param[out] buffer Output buffer + *****************************************************************************/ +static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + queue->tail = (queue->tail + 1) % queue->size; + queue->used--; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Get NVIC IRQ number from UARTDRV handle + * + * @param[in] handle UART driver handle + * @return Interrupt number + *****************************************************************************/ +static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle) +{ + IRQn_Type irq_number = (IRQn_Type)(-1); + + switch ((uint32_t)handle->peripheral.uart) { +#if defined(USART0_BASE) + case USART0_BASE: + irq_number = USART0_RX_IRQn; + break; +#endif +#if defined(USART1_BASE) + case USART1_BASE: + irq_number = USART1_RX_IRQn; + break; +#endif +#if defined(USART2_BASE) + case USART2_BASE: + irq_number = USART2_RX_IRQn; + break; +#endif +#if defined(USART3_BASE) + case USART3_BASE: + irq_number = USART3_RX_IRQn; + break; +#endif + default: + app_assert(false, "Unknown UARTDRV handle\n"); + break; + } + + return irq_number; +} + +/****************************************************************************** + * Start / resume UARTDRV receiving + * + * @param[in] handle UART driver handle + * @return UARTDRV reported result of the operation + *****************************************************************************/ +static Ecode_t uart_receive_start(UARTDRV_Handle_t handle) +{ + Ecode_t ec = UARTDRV_Receive(handle, rx_buf, sizeof(rx_buf), receive_cb); + + if (ec == ECODE_EMDRV_UARTDRV_OK) { + // De-assert nRTS or send XON + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlAuto); + } + } + + return ec; +} +/****************************************************************************** + * Function to trigger the OS task to proceed + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK void sl_simple_com_os_task_proceed(void) +{ + // No action on bare metal implementation +} diff --git a/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h b/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h index 9fee028..64b8e43 100644 --- a/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h +++ b/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h @@ -1,165 +1,165 @@ -/***************************************************************************//** - * @file - * @brief Application assert interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_ASSERT_H -#define APP_ASSERT_H - -#ifdef SL_COMPONENT_CATALOG_PRESENT -#include "sl_component_catalog.h" -#endif // SL_COMPONENT_CATALOG_PRESENT -#include "app_assert_config.h" -#include "sl_status.h" -#ifdef SL_CATALOG_APP_LOG_PRESENT -#include "app_log.h" -#endif - -#define APP_ASSERT_SEPARATOR ": " -#define APP_ASSERT_FORMAT "Assertion '%s' failed" -#define APP_ASSERT_TEXT "Assertion failed" - -#if defined(APP_ASSERT_ENABLE) && APP_ASSERT_ENABLE - -#ifdef HOST_TOOLCHAIN -#include -#define _app_assert_abort() abort() -#else -#define _app_assert_abort() while (1) -#endif // HOST_TOOLCHAIN - -#if defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE -#define _app_assert_trace() app_log_print_trace() -#else // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE -#define _app_assert_trace() -#endif // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE - -#if defined(SL_CATALOG_APP_LOG_PRESENT) \ - && APP_ASSERT_LOG_ENABLE \ - && defined(APP_LOG_ENABLE) \ - && APP_LOG_ENABLE - -#define _app_assert_log_status(sc, ...) \ - do { \ - app_log_nl(); \ - _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ - _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ - _app_log_time(); \ - _app_log_counter(); \ - _app_assert_trace(); \ - _app_log_print_status(sc); \ - app_log_append(__VA_ARGS__); \ - } while (0) - -#define _app_assert_log(...) \ - do { \ - app_log_nl(); \ - _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ - _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ - _app_log_time(); \ - _app_log_counter(); \ - _app_assert_trace(); \ - app_log_append(__VA_ARGS__); \ - } while (0) - -#define app_assert_s(expr) \ - do { \ - if (!(expr)) { \ - _app_assert_log(APP_ASSERT_FORMAT, \ - #expr); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert_status(sc) \ - do { \ - if (!(sc == SL_STATUS_OK)) { \ - _app_assert_log_status(sc, \ - APP_ASSERT_TEXT); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert_status_f(sc, ...) \ - do { \ - if (!(sc == SL_STATUS_OK)) { \ - _app_assert_log_status(sc, \ - APP_ASSERT_TEXT \ - APP_ASSERT_SEPARATOR \ - __VA_ARGS__); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert(expr, ...) \ - do { \ - if (!(expr)) { \ - _app_assert_log(APP_ASSERT_FORMAT \ - APP_ASSERT_SEPARATOR, \ - #expr); \ - app_log_append(__VA_ARGS__); \ - _app_assert_abort(); \ - } \ - } while (0) - -#else // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE - -#define _app_assert_printless(expr) \ - do { \ - if (!(expr)) { \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert(expr, ...) \ - _app_assert_printless(expr) - -#define app_assert_s(expr) \ - _app_assert_printless(expr) - -#define app_assert_status(sc) \ - _app_assert_printless(sc == SL_STATUS_OK) - -#define app_assert_status_f(sc, ...) \ - _app_assert_printless(sc == SL_STATUS_OK) - -#endif // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE - -#else // APP_ASSERT_ENABLE - -#define app_assert(expr, ...) - -#define app_assert_s(expr) - -#define app_assert_status(sc) (void)sc - -#define app_assert_status_f(sc, ...) (void)sc - -#endif // APP_ASSERT_ENABLE - -#endif // APP_ASSERT_H +/***************************************************************************//** + * @file + * @brief Application assert interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_ASSERT_H +#define APP_ASSERT_H + +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#endif // SL_COMPONENT_CATALOG_PRESENT +#include "app_assert_config.h" +#include "sl_status.h" +#ifdef SL_CATALOG_APP_LOG_PRESENT +#include "app_log.h" +#endif + +#define APP_ASSERT_SEPARATOR ": " +#define APP_ASSERT_FORMAT "Assertion '%s' failed" +#define APP_ASSERT_TEXT "Assertion failed" + +#if defined(APP_ASSERT_ENABLE) && APP_ASSERT_ENABLE + +#ifdef HOST_TOOLCHAIN +#include +#define _app_assert_abort() abort() +#else +#define _app_assert_abort() while (1) +#endif // HOST_TOOLCHAIN + +#if defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE +#define _app_assert_trace() app_log_print_trace() +#else // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE +#define _app_assert_trace() +#endif // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE + +#if defined(SL_CATALOG_APP_LOG_PRESENT) \ + && APP_ASSERT_LOG_ENABLE \ + && defined(APP_LOG_ENABLE) \ + && APP_LOG_ENABLE + +#define _app_assert_log_status(sc, ...) \ + do { \ + app_log_nl(); \ + _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ + _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ + _app_log_time(); \ + _app_log_counter(); \ + _app_assert_trace(); \ + _app_log_print_status(sc); \ + app_log_append(__VA_ARGS__); \ + } while (0) + +#define _app_assert_log(...) \ + do { \ + app_log_nl(); \ + _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ + _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ + _app_log_time(); \ + _app_log_counter(); \ + _app_assert_trace(); \ + app_log_append(__VA_ARGS__); \ + } while (0) + +#define app_assert_s(expr) \ + do { \ + if (!(expr)) { \ + _app_assert_log(APP_ASSERT_FORMAT, \ + #expr); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert_status(sc) \ + do { \ + if (!(sc == SL_STATUS_OK)) { \ + _app_assert_log_status(sc, \ + APP_ASSERT_TEXT); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert_status_f(sc, ...) \ + do { \ + if (!(sc == SL_STATUS_OK)) { \ + _app_assert_log_status(sc, \ + APP_ASSERT_TEXT \ + APP_ASSERT_SEPARATOR \ + __VA_ARGS__); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert(expr, ...) \ + do { \ + if (!(expr)) { \ + _app_assert_log(APP_ASSERT_FORMAT \ + APP_ASSERT_SEPARATOR, \ + #expr); \ + app_log_append(__VA_ARGS__); \ + _app_assert_abort(); \ + } \ + } while (0) + +#else // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE + +#define _app_assert_printless(expr) \ + do { \ + if (!(expr)) { \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert(expr, ...) \ + _app_assert_printless(expr) + +#define app_assert_s(expr) \ + _app_assert_printless(expr) + +#define app_assert_status(sc) \ + _app_assert_printless(sc == SL_STATUS_OK) + +#define app_assert_status_f(sc, ...) \ + _app_assert_printless(sc == SL_STATUS_OK) + +#endif // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE + +#else // APP_ASSERT_ENABLE + +#define app_assert(expr, ...) + +#define app_assert_s(expr) + +#define app_assert_status(sc) (void)sc + +#define app_assert_status_f(sc, ...) (void)sc + +#endif // APP_ASSERT_ENABLE + +#endif // APP_ASSERT_H diff --git a/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h b/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h index 01f97c3..c625ead 100644 --- a/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h +++ b/locator_host/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h @@ -1,40 +1,40 @@ -/***************************************************************************//** - * @file - * @brief Application assert interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_APP_ASSERT_H -#define SL_APP_ASSERT_H - -#include "app_assert.h" - -#warning "sl_app_assert is deprecated and marked for removal in a later release. Please use app_assert instead." - -#define sl_app_assert(expr, ...) app_assert(expr, __VA_ARGS__) - -#endif // SL_APP_ASSERT_H +/***************************************************************************//** + * @file + * @brief Application assert interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_APP_ASSERT_H +#define SL_APP_ASSERT_H + +#include "app_assert.h" + +#warning "sl_app_assert is deprecated and marked for removal in a later release. Please use app_assert instead." + +#define sl_app_assert(expr, ...) app_assert(expr, __VA_ARGS__) + +#endif // SL_APP_ASSERT_H diff --git a/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h b/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h index a629332..0000f6a 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h +++ b/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h @@ -1,219 +1,219 @@ -/***************************************************************************//** - * @file - * @brief Board Control API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_BOARD_CONTROL_H -#define SL_BOARD_CONTROL_H - -#include "sl_status.h" -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup board_control Board Control - * @brief Functions to control Silicon Labs board features - * @{ - ******************************************************************************/ - -/// Board Sensor Type -SL_ENUM_GENERIC(sl_board_sensor_t, int) { - SL_BOARD_SENSOR_RHT = (1UL << 0UL), ///< Relative Humidity and Temperature Sensor - SL_BOARD_SENSOR_LIGHT = (1UL << 1UL), ///< UV Index and Ambient Light Sensor - SL_BOARD_SENSOR_PRESSURE = (1UL << 2UL), ///< Barometric Pressure Sensor - SL_BOARD_SENSOR_HALL = (1UL << 3UL), ///< Hall Effect Sensor - SL_BOARD_SENSOR_GAS = (1UL << 4UL), ///< Gas Sensor - SL_BOARD_SENSOR_IMU = (1UL << 5UL), ///< Inertial Measurement Unit (Accelerometer/Gyroscope) - SL_BOARD_SENSOR_MICROPHONE = (1UL << 6UL), ///< Microphone -}; - -/// Board Memory Type -SL_ENUM_GENERIC(sl_board_memory_t, int) { - SL_BOARD_MEMORY_SDCARD = (1UL << 0UL), ///< SD Card - SL_BOARD_MEMORY_QSPI = (1UL << 1UL), ///< Quad SPI Flash -}; - -/// Board Oscillator Type -SL_ENUM_GENERIC(sl_board_oscillator_t, int) { - SL_BOARD_OSCILLATOR_TCXO = (1UL << 0UL), ///< TCXO -}; - -/***************************************************************************//** - * @brief Configure Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully enabled - * @retval SL_STATUS_FAIL Enabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - * @retval SL_STATUS_NOT_SUPPORTED VCOM enabled was not configured - ******************************************************************************/ -sl_status_t sl_board_configure_vcom(void); - -/***************************************************************************//** - * @brief Enable Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully enabled - * @retval SL_STATUS_FAIL Enabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_vcom(void); - -/***************************************************************************//** - * @brief Disable Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully disabled - * @retval SL_STATUS_FAIL Disabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_vcom(void); - -/***************************************************************************//** - * @brief Enable a sensor. - * - * @warning - * On boards 4166A, 4184A, and 4184B sensors - * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; - * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; - * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor - * respectively, are tied to the same enable pin. Calling the enable function - * for only one of these sensors has the side-effect of enabling all three; - * and calling the disable function for only one of them has the - * side-effect of disabling all three. - * The latter scenario seems less than desirable. - * - * @param[in] sensor Sensor to enable - * - * @return Status code - * @retval SL_STATUS_OK Sensor was successfully enabled - * @retval SL_STATUS_FAIL Enabling sensor failed - * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor); - -/***************************************************************************//** - * @brief Disable a sensor. - * - * @warning - * On boards 4166A, 4184A, and 4184B sensors - * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; - * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; - * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor - * respectively, are tied to the same enable pin. Calling the enable function - * for only one of these sensors has the side-effect of enabling all three; - * and calling the disable function for only one of them has the - * side-effect of disabling all three. - * The latter scenario seems less than desirable. - * - * @param[in] sensor Sensors to disable - * - * @return Status code - * @retval SL_STATUS_OK Sensor was successfully disabled - * @retval SL_STATUS_FAIL Disabling sensor failed - * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor); - -/***************************************************************************//** - * @brief Enable display. - * - * @return Status code - * @retval SL_STATUS_OK Display was successfully enabled - * @retval SL_STATUS_FAIL Enabling display failed - * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_display(void); - -/***************************************************************************//** - * @brief Disable display. - * - * @return Status code - * @retval SL_STATUS_OK Display was successfully disabled - * @retval SL_STATUS_FAIL Disabling display failed - * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_display(void); - -/***************************************************************************//** - * @brief Enable memory. - * - * @param[in] memory Memory to enable - * - * @return Status code - * @retval SL_STATUS_OK Memory was successfully enabled - * @retval SL_STATUS_FAIL Enabling memory failed - * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_memory(sl_board_memory_t memory); - -/***************************************************************************//** - * @brief Disable memory. - * - * @param[in] memory Memory to disable - * - * @return Status code - * @retval SL_STATUS_OK Memory was successfully disabled - * @retval SL_STATUS_FAIL Disabling memory failed - * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_memory(sl_board_memory_t memory); - -/***************************************************************************//** - * @brief Enable an oscillator. - * - * @param[in] oscillator Oscillator to enable - * - * @return Status code - * @retval SL_STATUS_OK Oscillator was successfully enabled - * @retval SL_STATUS_FAIL Enabling oscillator failed - * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator); - -/***************************************************************************//** - * @brief Disable a oscillator. - * - * @param[in] oscillator Oscillator to disable - * - * @return Status code - * @retval SL_STATUS_OK Oscillator was successfully disabled - * @retval SL_STATUS_FAIL Disabling oscillator failed - * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator); - -/** @} */ - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // SL_BOARD_CONTROL_H +/***************************************************************************//** + * @file + * @brief Board Control API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_BOARD_CONTROL_H +#define SL_BOARD_CONTROL_H + +#include "sl_status.h" +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup board_control Board Control + * @brief Functions to control Silicon Labs board features + * @{ + ******************************************************************************/ + +/// Board Sensor Type +SL_ENUM_GENERIC(sl_board_sensor_t, int) { + SL_BOARD_SENSOR_RHT = (1UL << 0UL), ///< Relative Humidity and Temperature Sensor + SL_BOARD_SENSOR_LIGHT = (1UL << 1UL), ///< UV Index and Ambient Light Sensor + SL_BOARD_SENSOR_PRESSURE = (1UL << 2UL), ///< Barometric Pressure Sensor + SL_BOARD_SENSOR_HALL = (1UL << 3UL), ///< Hall Effect Sensor + SL_BOARD_SENSOR_GAS = (1UL << 4UL), ///< Gas Sensor + SL_BOARD_SENSOR_IMU = (1UL << 5UL), ///< Inertial Measurement Unit (Accelerometer/Gyroscope) + SL_BOARD_SENSOR_MICROPHONE = (1UL << 6UL), ///< Microphone +}; + +/// Board Memory Type +SL_ENUM_GENERIC(sl_board_memory_t, int) { + SL_BOARD_MEMORY_SDCARD = (1UL << 0UL), ///< SD Card + SL_BOARD_MEMORY_QSPI = (1UL << 1UL), ///< Quad SPI Flash +}; + +/// Board Oscillator Type +SL_ENUM_GENERIC(sl_board_oscillator_t, int) { + SL_BOARD_OSCILLATOR_TCXO = (1UL << 0UL), ///< TCXO +}; + +/***************************************************************************//** + * @brief Configure Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully enabled + * @retval SL_STATUS_FAIL Enabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + * @retval SL_STATUS_NOT_SUPPORTED VCOM enabled was not configured + ******************************************************************************/ +sl_status_t sl_board_configure_vcom(void); + +/***************************************************************************//** + * @brief Enable Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully enabled + * @retval SL_STATUS_FAIL Enabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_vcom(void); + +/***************************************************************************//** + * @brief Disable Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully disabled + * @retval SL_STATUS_FAIL Disabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_vcom(void); + +/***************************************************************************//** + * @brief Enable a sensor. + * + * @warning + * On boards 4166A, 4184A, and 4184B sensors + * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; + * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; + * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor + * respectively, are tied to the same enable pin. Calling the enable function + * for only one of these sensors has the side-effect of enabling all three; + * and calling the disable function for only one of them has the + * side-effect of disabling all three. + * The latter scenario seems less than desirable. + * + * @param[in] sensor Sensor to enable + * + * @return Status code + * @retval SL_STATUS_OK Sensor was successfully enabled + * @retval SL_STATUS_FAIL Enabling sensor failed + * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor); + +/***************************************************************************//** + * @brief Disable a sensor. + * + * @warning + * On boards 4166A, 4184A, and 4184B sensors + * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; + * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; + * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor + * respectively, are tied to the same enable pin. Calling the enable function + * for only one of these sensors has the side-effect of enabling all three; + * and calling the disable function for only one of them has the + * side-effect of disabling all three. + * The latter scenario seems less than desirable. + * + * @param[in] sensor Sensors to disable + * + * @return Status code + * @retval SL_STATUS_OK Sensor was successfully disabled + * @retval SL_STATUS_FAIL Disabling sensor failed + * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor); + +/***************************************************************************//** + * @brief Enable display. + * + * @return Status code + * @retval SL_STATUS_OK Display was successfully enabled + * @retval SL_STATUS_FAIL Enabling display failed + * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_display(void); + +/***************************************************************************//** + * @brief Disable display. + * + * @return Status code + * @retval SL_STATUS_OK Display was successfully disabled + * @retval SL_STATUS_FAIL Disabling display failed + * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_display(void); + +/***************************************************************************//** + * @brief Enable memory. + * + * @param[in] memory Memory to enable + * + * @return Status code + * @retval SL_STATUS_OK Memory was successfully enabled + * @retval SL_STATUS_FAIL Enabling memory failed + * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_memory(sl_board_memory_t memory); + +/***************************************************************************//** + * @brief Disable memory. + * + * @param[in] memory Memory to disable + * + * @return Status code + * @retval SL_STATUS_OK Memory was successfully disabled + * @retval SL_STATUS_FAIL Disabling memory failed + * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_memory(sl_board_memory_t memory); + +/***************************************************************************//** + * @brief Enable an oscillator. + * + * @param[in] oscillator Oscillator to enable + * + * @return Status code + * @retval SL_STATUS_OK Oscillator was successfully enabled + * @retval SL_STATUS_FAIL Enabling oscillator failed + * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator); + +/***************************************************************************//** + * @brief Disable a oscillator. + * + * @param[in] oscillator Oscillator to disable + * + * @return Status code + * @retval SL_STATUS_OK Oscillator was successfully disabled + * @retval SL_STATUS_FAIL Disabling oscillator failed + * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator); + +/** @} */ + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // SL_BOARD_CONTROL_H diff --git a/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h b/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h index 8bd5f4b..036ff64 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h +++ b/locator_host/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief Board Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_BOARD_INIT_H -#define SL_BOARD_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup board_init Board Init - * @brief Initialization of Silicon Labs board features - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Initialize board. - * @details - * Initialize a Silicon Labs board by enabling available and configured board - * features, in addition to performing necessary board errata fixes and setting - * default pin states. - ******************************************************************************/ -void sl_board_init(void); - -/***************************************************************************//** - * @brief Initialize board features that are required at early boot. - * @details - * Certain board features such as external oscillators may need to be powered - * before core device features, such as the clock tree, are configured. - ******************************************************************************/ -void sl_board_preinit(void); -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_BOARD_INIT_H +/***************************************************************************//** + * @file + * @brief Board Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_BOARD_INIT_H +#define SL_BOARD_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup board_init Board Init + * @brief Initialization of Silicon Labs board features + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Initialize board. + * @details + * Initialize a Silicon Labs board by enabling available and configured board + * features, in addition to performing necessary board errata fixes and setting + * default pin states. + ******************************************************************************/ +void sl_board_init(void); + +/***************************************************************************//** + * @brief Initialize board features that are required at early boot. + * @details + * Certain board features such as external oscillators may need to be powered + * before core device features, such as the clock tree, are configured. + ******************************************************************************/ +void sl_board_preinit(void); +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_BOARD_INIT_H diff --git a/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c b/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c index 0d02db2..5e318e5 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c +++ b/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c @@ -1,455 +1,455 @@ -/***************************************************************************//** - * @file - * @brief Board Control API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" -#include "sl_board_control_config.h" -#include "em_device.h" - -#if defined(_SILICON_LABS_32B_SERIES_3) -#include "sl_peripheral_gpio.h" -#else -#include "em_gpio.h" -#endif - -sl_status_t sl_board_configure_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM) && SL_BOARD_ENABLE_VCOM - return sl_board_enable_vcom(); -#else - return SL_STATUS_NOT_SUPPORTED; -#endif -} - -sl_status_t sl_board_enable_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 1); -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_disable_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 0); -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_enable_display(void) -{ -#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 1); -#endif -#if defined(SL_BOARD_SELECT_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 1); -#endif -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_disable_display(void) -{ -#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 0); -#endif -#if defined(SL_BOARD_SELECT_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 0); -#endif -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (sensor) { - case SL_BOARD_SENSOR_RHT: - #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_LIGHT: - #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_PRESSURE: - #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_HALL: - #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_GAS: - #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_IMU: - #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_MICROPHONE: - #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (sensor) { - case SL_BOARD_SENSOR_RHT: - #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_LIGHT: - #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_PRESSURE: - #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_HALL: - #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_GAS: - #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_IMU: - #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_MICROPHONE: - #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_enable_memory(sl_board_memory_t memory) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (memory) { - case SL_BOARD_MEMORY_SDCARD: - #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_MEMORY_QSPI: - #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_memory(sl_board_memory_t memory) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (memory) { - case SL_BOARD_MEMORY_SDCARD: - #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_MEMORY_QSPI: - #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (oscillator) { - case SL_BOARD_OSCILLATOR_TCXO: - #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (oscillator) { - case SL_BOARD_OSCILLATOR_TCXO: - #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} +/***************************************************************************//** + * @file + * @brief Board Control API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" +#include "sl_board_control_config.h" +#include "em_device.h" + +#if defined(_SILICON_LABS_32B_SERIES_3) +#include "sl_peripheral_gpio.h" +#else +#include "em_gpio.h" +#endif + +sl_status_t sl_board_configure_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM) && SL_BOARD_ENABLE_VCOM + return sl_board_enable_vcom(); +#else + return SL_STATUS_NOT_SUPPORTED; +#endif +} + +sl_status_t sl_board_enable_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 1); +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_disable_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 0); +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_enable_display(void) +{ +#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 1); +#endif +#if defined(SL_BOARD_SELECT_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 1); +#endif +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_disable_display(void) +{ +#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 0); +#endif +#if defined(SL_BOARD_SELECT_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 0); +#endif +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (sensor) { + case SL_BOARD_SENSOR_RHT: + #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_LIGHT: + #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_PRESSURE: + #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_HALL: + #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_GAS: + #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_IMU: + #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_MICROPHONE: + #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (sensor) { + case SL_BOARD_SENSOR_RHT: + #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_LIGHT: + #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_PRESSURE: + #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_HALL: + #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_GAS: + #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_IMU: + #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_MICROPHONE: + #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_enable_memory(sl_board_memory_t memory) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (memory) { + case SL_BOARD_MEMORY_SDCARD: + #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_MEMORY_QSPI: + #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_memory(sl_board_memory_t memory) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (memory) { + case SL_BOARD_MEMORY_SDCARD: + #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_MEMORY_QSPI: + #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (oscillator) { + case SL_BOARD_OSCILLATOR_TCXO: + #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (oscillator) { + case SL_BOARD_OSCILLATOR_TCXO: + #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c b/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c index bbe57b0..bdcb8a5 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c +++ b/locator_host/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c @@ -1,98 +1,98 @@ -/***************************************************************************//** - * @file - * @brief Board Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" -#include "sl_board_control_config.h" - -#include "em_cmu.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT) -#include "sl_mx25_flash_shutdown.h" -#endif - -void sl_board_default_init(void); - -void sl_board_init(void) -{ - CMU_ClockEnable(cmuClock_GPIO, true); - - // Errata fixes and default pin states - sl_board_default_init(); - -#if defined(SL_BOARD_ENABLE_SENSOR_RHT) && SL_BOARD_ENABLE_SENSOR_RHT - sl_board_enable_sensor(SL_BOARD_SENSOR_RHT); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT) && SL_BOARD_ENABLE_SENSOR_LIGHT - sl_board_enable_sensor(SL_BOARD_SENSOR_LIGHT); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE) && SL_BOARD_ENABLE_SENSOR_PRESSURE - sl_board_enable_sensor(SL_BOARD_SENSOR_PRESSURE); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_HALL) && SL_BOARD_ENABLE_SENSOR_HALL - sl_board_enable_sensor(SL_BOARD_SENSOR_HALL); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_GAS) && SL_BOARD_ENABLE_SENSOR_GAS - sl_board_enable_sensor(SL_BOARD_SENSOR_GAS); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_IMU) && SL_BOARD_ENABLE_SENSOR_IMU - sl_board_enable_sensor(SL_BOARD_SENSOR_IMU); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE) && SL_BOARD_ENABLE_SENSOR_MICROPHONE - sl_board_enable_sensor(SL_BOARD_SENSOR_MICROPHONE); -#endif - -#if defined(SL_BOARD_ENABLE_DISPLAY) && SL_BOARD_ENABLE_DISPLAY - sl_board_enable_display(); -#endif - -#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD) && SL_BOARD_ENABLE_MEMORY_SDCARD - sl_board_enable_memory(SL_BOARD_MEMORY_SDCARD); -#endif -#if defined(SL_BOARD_ENABLE_MEMORY_QSPI) && SL_BOARD_ENABLE_MEMORY_QSPI - sl_board_enable_memory(SL_BOARD_MEMORY_QSPI); -#endif - -#if (defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)) && \ - defined(SL_BOARD_DISABLE_MEMORY_SPI) && SL_BOARD_DISABLE_MEMORY_SPI - sl_mx25_flash_shutdown(); -#endif -} - -void sl_board_preinit(void) -{ - CMU_ClockEnable(cmuClock_GPIO, true); - -#if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO) && SL_BOARD_ENABLE_OSCILLATOR_TCXO - sl_board_enable_oscillator(SL_BOARD_OSCILLATOR_TCXO); -#endif -} +/***************************************************************************//** + * @file + * @brief Board Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" +#include "sl_board_control_config.h" + +#include "em_cmu.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT) +#include "sl_mx25_flash_shutdown.h" +#endif + +void sl_board_default_init(void); + +void sl_board_init(void) +{ + CMU_ClockEnable(cmuClock_GPIO, true); + + // Errata fixes and default pin states + sl_board_default_init(); + +#if defined(SL_BOARD_ENABLE_SENSOR_RHT) && SL_BOARD_ENABLE_SENSOR_RHT + sl_board_enable_sensor(SL_BOARD_SENSOR_RHT); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT) && SL_BOARD_ENABLE_SENSOR_LIGHT + sl_board_enable_sensor(SL_BOARD_SENSOR_LIGHT); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE) && SL_BOARD_ENABLE_SENSOR_PRESSURE + sl_board_enable_sensor(SL_BOARD_SENSOR_PRESSURE); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_HALL) && SL_BOARD_ENABLE_SENSOR_HALL + sl_board_enable_sensor(SL_BOARD_SENSOR_HALL); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_GAS) && SL_BOARD_ENABLE_SENSOR_GAS + sl_board_enable_sensor(SL_BOARD_SENSOR_GAS); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_IMU) && SL_BOARD_ENABLE_SENSOR_IMU + sl_board_enable_sensor(SL_BOARD_SENSOR_IMU); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE) && SL_BOARD_ENABLE_SENSOR_MICROPHONE + sl_board_enable_sensor(SL_BOARD_SENSOR_MICROPHONE); +#endif + +#if defined(SL_BOARD_ENABLE_DISPLAY) && SL_BOARD_ENABLE_DISPLAY + sl_board_enable_display(); +#endif + +#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD) && SL_BOARD_ENABLE_MEMORY_SDCARD + sl_board_enable_memory(SL_BOARD_MEMORY_SDCARD); +#endif +#if defined(SL_BOARD_ENABLE_MEMORY_QSPI) && SL_BOARD_ENABLE_MEMORY_QSPI + sl_board_enable_memory(SL_BOARD_MEMORY_QSPI); +#endif + +#if (defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)) && \ + defined(SL_BOARD_DISABLE_MEMORY_SPI) && SL_BOARD_DISABLE_MEMORY_SPI + sl_mx25_flash_shutdown(); +#endif +} + +void sl_board_preinit(void) +{ + CMU_ClockEnable(cmuClock_GPIO, true); + +#if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO) && SL_BOARD_ENABLE_OSCILLATOR_TCXO + sl_board_enable_oscillator(SL_BOARD_OSCILLATOR_TCXO); +#endif +} diff --git a/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h b/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h index 0818ff1..06f9d9c 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h +++ b/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h @@ -1,147 +1,147 @@ -/***************************************************************************//** - * @file - * @brief Configuration Over SWO Component. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_COS_H -#define SL_COS_H - -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup cos Configuration Over SWO - * @brief Configuration Over SWO - * @details - * ## Overview - * - * When working with VCOM and/or PTI with a Silicon Labs kit (WSTK or WPK), - * it's important that the configuration of the kit's board controller - * matches that of the target application. - * The Configuration Over SWO component provides a way to automatically - * configure the board controller to use the same settings for VCOM and - * PTI configuration is sent to the board controller over SWO at startup, - * ensuring that the configuration is synchronized. - * @{ - ******************************************************************************/ - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ -#if defined (SL_CATALOG_UARTDRV_USART_PRESENT) || defined (SL_CATALOG_UARTDRV_EUSART_PRESENT) -#define SLI_COS_UARTDRV_VCOM_PRESENT -#endif // SL_CATALOG_UARTDRV_USART_PRESENT || SL_CATALOG_UARTDRV_EUSART_PRESENT - -#define COS_CONFIG_FLOWCONTROL_NONE 0 -#define COS_CONFIG_FLOWCONTROL_CTS 1 -#define COS_CONFIG_FLOWCONTROL_RTS 2 -#define COS_CONFIG_FLOWCONTROL_CTS_RTS 3 -/// @endcond - -// ----------------------------------------------------------------------------- -// Data Types - -/// @brief Enumeration representing the PTI Modes -SL_ENUM(COS_PtiMode_t) { - /** ONEWIRE mode. */ - COS_CONFIG_PTI_MODE_ONEWIRE, - /** TWOWIRE mode. */ - COS_CONFIG_PTI_MODE_TWOWIRE, - /** UART mode. */ - COS_CONFIG_PTI_MODE_EFRUART, - /** SPI mode. */ - COS_CONFIG_PTI_MODE_EFRSPI, - /** Mode count. */ - COS_CONFIG_PTI_MODE_COUNT -}; - -/// @brief Enumeration representing the PTI Interfaces -SL_ENUM(COS_PtiInterface_t) { - /** PTI INTERFACE 0. */ - COS_CONFIG_PTI_INTERFACE_0, - /** PTI INTERFACE 1. */ - COS_CONFIG_PTI_INTERFACE_1, - /** Interface count. */ - COS_CONFIG_PTI_INTERFACE_COUNT -}; - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. - ******************************************************************************/ -void sl_cos_send_config(void); - - /***************************************************************************//** - * Custom API, to be used by other software component to write the - * structured VCOM data on SWO ITM channel 8 - * The following Custom API take Baud rate, Flow Control as an input that should be - * configured at the bit(0 to 23) and bit(30(CTS), 31(RTS)) of the structured VCOM - * data respectively so that WSTK identifies the baud rate and flow_control values - * and configure accordingly - * - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * - * @param[in] flow_control Flow Control value that has to be set over bit_30 and bit_31. - ******************************************************************************/ -void sl_cos_config_vcom(uint32_t baudrate, - uint8_t flow_control); - -/***************************************************************************//** - * Custom API, to be used by other software component to write the - * structured PTI data on SWO ITM channel 8 - * - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] mode COS_PtiMode_t to be used. - * ONEWIRE mode. - * TWOWIRE mode. - * UART mode. - * SPI mode. - * PTI Modes that has to be set over bit_27 to bit_29. - * @param[in] interface COS_PtiInterface_t to be used. - * PTI INTERFACE 0. - * PTI INTERFACE 1. - * Interface value that has to be set over bit_30 and bit_31. - * @return config - ******************************************************************************/ -void sl_cos_config_pti(uint32_t baudrate, - COS_PtiMode_t mode, - COS_PtiInterface_t interface); - -/** @} (end addtogroup cos) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_COS_H */ +/***************************************************************************//** + * @file + * @brief Configuration Over SWO Component. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COS_H +#define SL_COS_H + +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup cos Configuration Over SWO + * @brief Configuration Over SWO + * @details + * ## Overview + * + * When working with VCOM and/or PTI with a Silicon Labs kit (WSTK or WPK), + * it's important that the configuration of the kit's board controller + * matches that of the target application. + * The Configuration Over SWO component provides a way to automatically + * configure the board controller to use the same settings for VCOM and + * PTI configuration is sent to the board controller over SWO at startup, + * ensuring that the configuration is synchronized. + * @{ + ******************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#if defined (SL_CATALOG_UARTDRV_USART_PRESENT) || defined (SL_CATALOG_UARTDRV_EUSART_PRESENT) +#define SLI_COS_UARTDRV_VCOM_PRESENT +#endif // SL_CATALOG_UARTDRV_USART_PRESENT || SL_CATALOG_UARTDRV_EUSART_PRESENT + +#define COS_CONFIG_FLOWCONTROL_NONE 0 +#define COS_CONFIG_FLOWCONTROL_CTS 1 +#define COS_CONFIG_FLOWCONTROL_RTS 2 +#define COS_CONFIG_FLOWCONTROL_CTS_RTS 3 +/// @endcond + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Enumeration representing the PTI Modes +SL_ENUM(COS_PtiMode_t) { + /** ONEWIRE mode. */ + COS_CONFIG_PTI_MODE_ONEWIRE, + /** TWOWIRE mode. */ + COS_CONFIG_PTI_MODE_TWOWIRE, + /** UART mode. */ + COS_CONFIG_PTI_MODE_EFRUART, + /** SPI mode. */ + COS_CONFIG_PTI_MODE_EFRSPI, + /** Mode count. */ + COS_CONFIG_PTI_MODE_COUNT +}; + +/// @brief Enumeration representing the PTI Interfaces +SL_ENUM(COS_PtiInterface_t) { + /** PTI INTERFACE 0. */ + COS_CONFIG_PTI_INTERFACE_0, + /** PTI INTERFACE 1. */ + COS_CONFIG_PTI_INTERFACE_1, + /** Interface count. */ + COS_CONFIG_PTI_INTERFACE_COUNT +}; + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. + ******************************************************************************/ +void sl_cos_send_config(void); + + /***************************************************************************//** + * Custom API, to be used by other software component to write the + * structured VCOM data on SWO ITM channel 8 + * The following Custom API take Baud rate, Flow Control as an input that should be + * configured at the bit(0 to 23) and bit(30(CTS), 31(RTS)) of the structured VCOM + * data respectively so that WSTK identifies the baud rate and flow_control values + * and configure accordingly + * + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * + * @param[in] flow_control Flow Control value that has to be set over bit_30 and bit_31. + ******************************************************************************/ +void sl_cos_config_vcom(uint32_t baudrate, + uint8_t flow_control); + +/***************************************************************************//** + * Custom API, to be used by other software component to write the + * structured PTI data on SWO ITM channel 8 + * + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] mode COS_PtiMode_t to be used. + * ONEWIRE mode. + * TWOWIRE mode. + * UART mode. + * SPI mode. + * PTI Modes that has to be set over bit_27 to bit_29. + * @param[in] interface COS_PtiInterface_t to be used. + * PTI INTERFACE 0. + * PTI INTERFACE 1. + * Interface value that has to be set over bit_30 and bit_31. + * @return config + ******************************************************************************/ +void sl_cos_config_pti(uint32_t baudrate, + COS_PtiMode_t mode, + COS_PtiInterface_t interface); + +/** @} (end addtogroup cos) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_COS_H */ diff --git a/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c b/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c index 049a030..d301cf0 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c +++ b/locator_host/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c @@ -1,370 +1,370 @@ -/***************************************************************************//** - * @file - * @brief Configuration Over SWO Component - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#include -#include -#include -#include "sl_cos.h" -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -#include "sl_uartdrv_instances.h" -#endif // SLI_COS_UARTDRV_VCOM_PRESENT -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -#include "sl_rail_util_pti_config.h" -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -#include "sl_status.h" -#include "sl_debug_swo.h" - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ -#if defined (__ICCARM__) -#define DCH_PACKED_STRUCT __packed struct -#elif defined (__clang__) || defined (__ARM_ARCH) -#define DCH_PACKED_STRUCT struct __attribute__ ((__packed__)) -#elif defined (__GNUC__) -#define DCH_PACKED_STRUCT struct __attribute__ ((gcc_struct, __packed__)) -#endif - -#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) -#define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) - -#define COS_CONFIG_OPTION_TYPE_NULL 0 -#define COS_CONFIG_OPTION_TYPE_UART 1 -#define COS_CONFIG_OPTION_TYPE_PTI 2 - -#define COS_CONFIG_BAUDRATE_POS 0 -#define COS_CONFIG_BAUDRATE_MASK 0x00FFFFFFLU - -#define COS_CONFIG_UART_STOPBITS_1 0 -#define COS_CONFIG_UART_STOPBITS_1_5 1 -#define COS_CONFIG_UART_STOPBITS_2 2 -#define COS_CONFIG_UART_STOPBITS_LAST COS_CONFIG_UART_STOPBITS_2 -#define COS_CONFIG_UART_STOPBITS_POS 24 -#define COS_CONFIG_UART_STOPBITS_MASK 0x03LU - -#define COS_CONFIG_UART_PARITY_NONE 0 -#define COS_CONFIG_UART_PARITY_EVEN 1 -#define COS_CONFIG_UART_PARITY_ODD 2 -#define COS_CONFIG_UART_PARITY_LAST COS_CONFIG_UART_PARITY_ODD -#define COS_CONFIG_UART_PARITY_POS 26 -#define COS_CONFIG_UART_PARITY_MASK 0x03LU - -#define COS_CONFIG_UART_MODE_UART 0 -#define COS_CONFIG_UART_MODE_SPISLAVE 1 -#define COS_CONFIG_UART_MODE_SPIMASTER 2 -#define COS_CONFIG_UART_MODE_LAST COS_CONFIG_UART_MODE_ENABLED -#define COS_CONFIG_UART_MODE_POS 28 -#define COS_CONFIG_UART_MODE_MASK 0x03LU - -#define COS_CONFIG_UART_CTS_DISABLED 0 -#define COS_CONFIG_UART_CTS_ENABLED 1 -#define COS_CONFIG_UART_CTS_LAST COS_CONFIG_UART_CTS_ENABLED -#define COS_CONFIG_UART_CTS_POS 30 -#define COS_CONFIG_UART_CTS_MASK 0x01LU - -#define COS_CONFIG_UART_RTS_DISABLED 0 -#define COS_CONFIG_UART_RTS_ENABLED 1 -#define COS_CONFIG_UART_RTS_LAST COS_CONFIG_UART_RTS_ENABLED -#define COS_CONFIG_UART_RTS_POS 31 -#define COS_CONFIG_UART_RTS_MASK 0x01LU -#define COS_CONFIG_UART_FC_POS 30 -#define COS_CONFIG_UART_FC_MASK 0x03LU - -#define COS_CONFIG_PTI_MODE_POS 27 -#define COS_CONFIG_PTI_MODE_MASK 0x07LU - -#define COS_CONFIG_PTI_INTERFACE_POS 30 -#define COS_CONFIG_PTI_INTERFACE_MASK 0x03LU - -// SWO message type for COS -#define EM_COS_PACKET 0X0080LU - -// MACRO for SWO channel 8 -#define SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL 8U - -/******************************************************************************* - ****************************** VARIABLES ********************************** - ******************************************************************************/ - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static UARTDRV_Handle_t uartdrv_handle = NULL; -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -/***************************************************************************//** - * Structure to store the COS Config Options - ******************************************************************************/ -typedef DCH_PACKED_STRUCT __COS_ConfigOption { - uint8_t optionType; ///< option type - uint8_t reserved1; ///< reserved one - uint16_t reserved2; ///< reserved two - uint32_t optionValue; ///< option value -} COS_ConfigOption_t; - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static uint32_t sli_cos_vcom_config(uint32_t baudrate, uint8_t flow_control); -static void sli_cos_vcom_write(void); -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -static uint32_t sli_cos_pti_config(uint32_t baudrate, RAIL_PtiMode_t mode, uint8_t interface); -static void sli_cos_pti_write(void); -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, - size_t buffer_length); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. - ******************************************************************************/ -void sl_cos_send_config(void) -{ - // Configure SWO stimulus 8 - sl_debug_swo_enable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) - sli_cos_vcom_write(); -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) - // If RAIL PTI MODE is RAIL_PTI_MODE_DISABLED, then don't initiate sli_cos_pti_write(). - if (SL_RAIL_UTIL_PTI_MODE != RAIL_PTI_MODE_DISABLED) { - sli_cos_pti_write(); - } -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - - // Disable SWO stimulus 8 - sl_debug_swo_disable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); - - return; -} - -/***************************************************************************//** - * Pack the BaudRate, flow control value of VCOM into a 32 bit integer - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] flow_control Flow control that has to be set over bit_30 and bit_31. - * return uint32_t result - ******************************************************************************/ -static uint32_t sli_cos_vcom_config(uint32_t baudrate, - uint8_t flow_control) -{ - uint32_t config = 0; - - // Packing baudrate, and flow control info to config. - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((flow_control) & (COS_CONFIG_UART_FC_MASK)) << COS_CONFIG_UART_FC_POS); - - return config; -} - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -/***************************************************************************//** - * Pack the BaudRate and mode value of PTI into a 32 bit integer - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] mode RAIL_PtiMode_t to be used. - * RAIL_PTI_MODE_DISABLED; Turn PTI off entirely. - * RAIL_PTI_MODE_SPI; SPI mode. - * RAIL_PTI_MODE_UART; UART mode. - * RAIL_PTI_MODE_UART_ONEWIRE; 9-bit UART mode. - * PTI Modes that has to be set over bit_27 to bit_29. - * @param[in] interface Interface value that has to be set over bit_30 and bit_31. - * return uint32_t config - ******************************************************************************/ -static uint32_t sli_cos_pti_config(uint32_t baudrate, - RAIL_PtiMode_t mode, uint8_t interface) -{ - uint32_t config = 0; - COS_PtiMode_t mode_Val = COS_CONFIG_PTI_MODE_EFRUART; - - // Mapping received Rail PTI Mode to COS PTI Mode - if (RAIL_PTI_MODE_SPI == mode) { - mode_Val = COS_CONFIG_PTI_MODE_EFRSPI; - } - - // Packing baudrate, mode and interface info to config. - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((mode_Val) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); - config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); - - return config; -} -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -/***************************************************************************//** - * Write the structured VCOM data on SWO ITM channel 8. - ******************************************************************************/ -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static void sli_cos_vcom_write(void) -{ - COS_ConfigOption_t Cos_Uart_Config; - uartdrv_handle = sl_uartdrv_get_default(); - uint32_t baudrate = 0; - - Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; - -#ifdef SL_CATALOG_UARTDRV_EUSART_PRESENT - if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeEuart) { - baudrate = EUSART_BaudrateGet(uartdrv_handle->peripheral.euart); - } -#endif // SL_CATALOG_UARTDRV_EUSART_PRESENT - -#ifdef SL_CATALOG_UARTDRV_USART_PRESENT - if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeUart) { - baudrate = USART_BaudrateGet(uartdrv_handle->peripheral.uart); - } -#endif // SL_CATALOG_UARTDRV_USART_PRESENT - - Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, uartdrv_handle->fcType); - - sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); -} -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -/***************************************************************************//** - * Write the structured PTI data on SWO ITM channel 8. - ******************************************************************************/ -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -static void sli_cos_pti_write(void) -{ - COS_ConfigOption_t Cos_Pti_Config; - - Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; - Cos_Pti_Config.optionValue = sli_cos_pti_config(SL_RAIL_UTIL_PTI_BAUD_RATE_HZ, SL_RAIL_UTIL_PTI_MODE, COS_CONFIG_PTI_INTERFACE_0); - - sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); -} -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -/***************************************************************************//** - * Custom API which can be used by other software component, to write the - * structured PTI data on SWO ITM channel 8. - ******************************************************************************/ -void sl_cos_config_pti(uint32_t baudrate, - COS_PtiMode_t mode, - COS_PtiInterface_t interface) -{ - COS_ConfigOption_t Cos_Pti_Config; - uint32_t config = 0; - - Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; - - // Packing baudrate, mode and interface info to config - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((mode) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); - config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); - - Cos_Pti_Config.optionValue = config; - - sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); -} - -/***************************************************************************//** - * Custom API which can be used by other software component, to write the - * structured VCOM data on SWO ITM channel 8. - ******************************************************************************/ -void sl_cos_config_vcom(uint32_t baudrate, - uint8_t flow_control) -{ - COS_ConfigOption_t Cos_Uart_Config; - - Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; - Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, flow_control); - - sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); -} - -/***************************************************************************//** - * Write data on SWO interface (WSTK-port 4900) - ******************************************************************************/ -static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, - size_t buffer_length) -{ - uint8_t *buf = (uint8_t *)buffer; - uint32_t packet_length; - uint32_t i; - uint8_t output_byte; - uint8_t seq_nbr = 0; - - // Full length is 2 square braces, 1 byte length and 2 byte CRC - packet_length = ( (uint32_t)buffer_length) + 9; - - // The write feature is built upon the existing Ember Debug Message (EDM) protocol, which today is transmitted over SWO UART on ITM Channel 8. - // The Protocol have the Start-byte, Length, Version, Message type, Sequence number, Message, CRC CCITT-16, and End-byte for correct communication. - for ( i = 0; i < packet_length; ++i ) { - if ( i == 0 ) { - // Frame start - output_byte = '['; - } else if ( i == 1 ) { - // Including special byte, type and sequence number - output_byte = buffer_length + 4; - } else if ( i == 2 ) { - // Special EDM byte - output_byte = 0xD1; - } else if ( i == 3 ) { - // COS Type byte 1 - output_byte = LOW_BYTE((uint16_t)(EM_COS_PACKET)); - } else if ( i == 4 ) { - // COS Type byte 2 - output_byte = HIGH_BYTE((uint16_t)(EM_COS_PACKET)); - } else if ( i == 5 ) { - // Sequence number - output_byte = seq_nbr++; - } else if ( i == (packet_length - 3) ) { - // CRC first byte - // Ignored by FW - so we also skip it - output_byte = 0x5A; - } else if ( i == (packet_length - 2) ) { - // CRC second byte - // Ignored by FW - so we also skip it - output_byte = 0x5A; - } else if ( i == (packet_length - 1) ) { - // Frame end - output_byte = ']'; - } else { - // Data - output_byte = buf[i - 6]; - } - - sl_debug_swo_write(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL, output_byte); - } - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Configuration Over SWO Component + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include +#include +#include +#include "sl_cos.h" +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +#include "sl_uartdrv_instances.h" +#endif // SLI_COS_UARTDRV_VCOM_PRESENT +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +#include "sl_rail_util_pti_config.h" +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +#include "sl_status.h" +#include "sl_debug_swo.h" + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#if defined (__ICCARM__) +#define DCH_PACKED_STRUCT __packed struct +#elif defined (__clang__) || defined (__ARM_ARCH) +#define DCH_PACKED_STRUCT struct __attribute__ ((__packed__)) +#elif defined (__GNUC__) +#define DCH_PACKED_STRUCT struct __attribute__ ((gcc_struct, __packed__)) +#endif + +#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) +#define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) + +#define COS_CONFIG_OPTION_TYPE_NULL 0 +#define COS_CONFIG_OPTION_TYPE_UART 1 +#define COS_CONFIG_OPTION_TYPE_PTI 2 + +#define COS_CONFIG_BAUDRATE_POS 0 +#define COS_CONFIG_BAUDRATE_MASK 0x00FFFFFFLU + +#define COS_CONFIG_UART_STOPBITS_1 0 +#define COS_CONFIG_UART_STOPBITS_1_5 1 +#define COS_CONFIG_UART_STOPBITS_2 2 +#define COS_CONFIG_UART_STOPBITS_LAST COS_CONFIG_UART_STOPBITS_2 +#define COS_CONFIG_UART_STOPBITS_POS 24 +#define COS_CONFIG_UART_STOPBITS_MASK 0x03LU + +#define COS_CONFIG_UART_PARITY_NONE 0 +#define COS_CONFIG_UART_PARITY_EVEN 1 +#define COS_CONFIG_UART_PARITY_ODD 2 +#define COS_CONFIG_UART_PARITY_LAST COS_CONFIG_UART_PARITY_ODD +#define COS_CONFIG_UART_PARITY_POS 26 +#define COS_CONFIG_UART_PARITY_MASK 0x03LU + +#define COS_CONFIG_UART_MODE_UART 0 +#define COS_CONFIG_UART_MODE_SPISLAVE 1 +#define COS_CONFIG_UART_MODE_SPIMASTER 2 +#define COS_CONFIG_UART_MODE_LAST COS_CONFIG_UART_MODE_ENABLED +#define COS_CONFIG_UART_MODE_POS 28 +#define COS_CONFIG_UART_MODE_MASK 0x03LU + +#define COS_CONFIG_UART_CTS_DISABLED 0 +#define COS_CONFIG_UART_CTS_ENABLED 1 +#define COS_CONFIG_UART_CTS_LAST COS_CONFIG_UART_CTS_ENABLED +#define COS_CONFIG_UART_CTS_POS 30 +#define COS_CONFIG_UART_CTS_MASK 0x01LU + +#define COS_CONFIG_UART_RTS_DISABLED 0 +#define COS_CONFIG_UART_RTS_ENABLED 1 +#define COS_CONFIG_UART_RTS_LAST COS_CONFIG_UART_RTS_ENABLED +#define COS_CONFIG_UART_RTS_POS 31 +#define COS_CONFIG_UART_RTS_MASK 0x01LU +#define COS_CONFIG_UART_FC_POS 30 +#define COS_CONFIG_UART_FC_MASK 0x03LU + +#define COS_CONFIG_PTI_MODE_POS 27 +#define COS_CONFIG_PTI_MODE_MASK 0x07LU + +#define COS_CONFIG_PTI_INTERFACE_POS 30 +#define COS_CONFIG_PTI_INTERFACE_MASK 0x03LU + +// SWO message type for COS +#define EM_COS_PACKET 0X0080LU + +// MACRO for SWO channel 8 +#define SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL 8U + +/******************************************************************************* + ****************************** VARIABLES ********************************** + ******************************************************************************/ + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static UARTDRV_Handle_t uartdrv_handle = NULL; +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +/***************************************************************************//** + * Structure to store the COS Config Options + ******************************************************************************/ +typedef DCH_PACKED_STRUCT __COS_ConfigOption { + uint8_t optionType; ///< option type + uint8_t reserved1; ///< reserved one + uint16_t reserved2; ///< reserved two + uint32_t optionValue; ///< option value +} COS_ConfigOption_t; + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static uint32_t sli_cos_vcom_config(uint32_t baudrate, uint8_t flow_control); +static void sli_cos_vcom_write(void); +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +static uint32_t sli_cos_pti_config(uint32_t baudrate, RAIL_PtiMode_t mode, uint8_t interface); +static void sli_cos_pti_write(void); +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, + size_t buffer_length); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. + ******************************************************************************/ +void sl_cos_send_config(void) +{ + // Configure SWO stimulus 8 + sl_debug_swo_enable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) + sli_cos_vcom_write(); +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) + // If RAIL PTI MODE is RAIL_PTI_MODE_DISABLED, then don't initiate sli_cos_pti_write(). + if (SL_RAIL_UTIL_PTI_MODE != RAIL_PTI_MODE_DISABLED) { + sli_cos_pti_write(); + } +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + + // Disable SWO stimulus 8 + sl_debug_swo_disable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); + + return; +} + +/***************************************************************************//** + * Pack the BaudRate, flow control value of VCOM into a 32 bit integer + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] flow_control Flow control that has to be set over bit_30 and bit_31. + * return uint32_t result + ******************************************************************************/ +static uint32_t sli_cos_vcom_config(uint32_t baudrate, + uint8_t flow_control) +{ + uint32_t config = 0; + + // Packing baudrate, and flow control info to config. + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((flow_control) & (COS_CONFIG_UART_FC_MASK)) << COS_CONFIG_UART_FC_POS); + + return config; +} + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +/***************************************************************************//** + * Pack the BaudRate and mode value of PTI into a 32 bit integer + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] mode RAIL_PtiMode_t to be used. + * RAIL_PTI_MODE_DISABLED; Turn PTI off entirely. + * RAIL_PTI_MODE_SPI; SPI mode. + * RAIL_PTI_MODE_UART; UART mode. + * RAIL_PTI_MODE_UART_ONEWIRE; 9-bit UART mode. + * PTI Modes that has to be set over bit_27 to bit_29. + * @param[in] interface Interface value that has to be set over bit_30 and bit_31. + * return uint32_t config + ******************************************************************************/ +static uint32_t sli_cos_pti_config(uint32_t baudrate, + RAIL_PtiMode_t mode, uint8_t interface) +{ + uint32_t config = 0; + COS_PtiMode_t mode_Val = COS_CONFIG_PTI_MODE_EFRUART; + + // Mapping received Rail PTI Mode to COS PTI Mode + if (RAIL_PTI_MODE_SPI == mode) { + mode_Val = COS_CONFIG_PTI_MODE_EFRSPI; + } + + // Packing baudrate, mode and interface info to config. + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((mode_Val) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); + config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); + + return config; +} +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +/***************************************************************************//** + * Write the structured VCOM data on SWO ITM channel 8. + ******************************************************************************/ +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static void sli_cos_vcom_write(void) +{ + COS_ConfigOption_t Cos_Uart_Config; + uartdrv_handle = sl_uartdrv_get_default(); + uint32_t baudrate = 0; + + Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; + +#ifdef SL_CATALOG_UARTDRV_EUSART_PRESENT + if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeEuart) { + baudrate = EUSART_BaudrateGet(uartdrv_handle->peripheral.euart); + } +#endif // SL_CATALOG_UARTDRV_EUSART_PRESENT + +#ifdef SL_CATALOG_UARTDRV_USART_PRESENT + if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeUart) { + baudrate = USART_BaudrateGet(uartdrv_handle->peripheral.uart); + } +#endif // SL_CATALOG_UARTDRV_USART_PRESENT + + Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, uartdrv_handle->fcType); + + sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); +} +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +/***************************************************************************//** + * Write the structured PTI data on SWO ITM channel 8. + ******************************************************************************/ +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +static void sli_cos_pti_write(void) +{ + COS_ConfigOption_t Cos_Pti_Config; + + Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; + Cos_Pti_Config.optionValue = sli_cos_pti_config(SL_RAIL_UTIL_PTI_BAUD_RATE_HZ, SL_RAIL_UTIL_PTI_MODE, COS_CONFIG_PTI_INTERFACE_0); + + sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); +} +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +/***************************************************************************//** + * Custom API which can be used by other software component, to write the + * structured PTI data on SWO ITM channel 8. + ******************************************************************************/ +void sl_cos_config_pti(uint32_t baudrate, + COS_PtiMode_t mode, + COS_PtiInterface_t interface) +{ + COS_ConfigOption_t Cos_Pti_Config; + uint32_t config = 0; + + Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; + + // Packing baudrate, mode and interface info to config + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((mode) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); + config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); + + Cos_Pti_Config.optionValue = config; + + sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); +} + +/***************************************************************************//** + * Custom API which can be used by other software component, to write the + * structured VCOM data on SWO ITM channel 8. + ******************************************************************************/ +void sl_cos_config_vcom(uint32_t baudrate, + uint8_t flow_control) +{ + COS_ConfigOption_t Cos_Uart_Config; + + Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; + Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, flow_control); + + sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); +} + +/***************************************************************************//** + * Write data on SWO interface (WSTK-port 4900) + ******************************************************************************/ +static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, + size_t buffer_length) +{ + uint8_t *buf = (uint8_t *)buffer; + uint32_t packet_length; + uint32_t i; + uint8_t output_byte; + uint8_t seq_nbr = 0; + + // Full length is 2 square braces, 1 byte length and 2 byte CRC + packet_length = ( (uint32_t)buffer_length) + 9; + + // The write feature is built upon the existing Ember Debug Message (EDM) protocol, which today is transmitted over SWO UART on ITM Channel 8. + // The Protocol have the Start-byte, Length, Version, Message type, Sequence number, Message, CRC CCITT-16, and End-byte for correct communication. + for ( i = 0; i < packet_length; ++i ) { + if ( i == 0 ) { + // Frame start + output_byte = '['; + } else if ( i == 1 ) { + // Including special byte, type and sequence number + output_byte = buffer_length + 4; + } else if ( i == 2 ) { + // Special EDM byte + output_byte = 0xD1; + } else if ( i == 3 ) { + // COS Type byte 1 + output_byte = LOW_BYTE((uint16_t)(EM_COS_PACKET)); + } else if ( i == 4 ) { + // COS Type byte 2 + output_byte = HIGH_BYTE((uint16_t)(EM_COS_PACKET)); + } else if ( i == 5 ) { + // Sequence number + output_byte = seq_nbr++; + } else if ( i == (packet_length - 3) ) { + // CRC first byte + // Ignored by FW - so we also skip it + output_byte = 0x5A; + } else if ( i == (packet_length - 2) ) { + // CRC second byte + // Ignored by FW - so we also skip it + output_byte = 0x5A; + } else if ( i == (packet_length - 1) ) { + // Frame end + output_byte = ']'; + } else { + // Data + output_byte = buf[i - 6]; + } + + sl_debug_swo_write(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL, output_byte); + } + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h b/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h index 7dd0da5..c471eff 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h +++ b/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief MX25 flash shutdown - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_H -#define SL_MX25_FLASH_SHUTDOWN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "em_device.h" -#include "sl_mx25_flash_shutdown_usart_config.h" - -/***************************************************************************//** - * @addtogroup mx25_flash_shutdown MX25 SPI Flash Shutdown - * @brief Provide a function to put the MX25 SPI flash into deep power down - * mode to reduce power consumption. - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Put the MX25 SPI flash into deep power down mode. - * - * This function initializes SPI communication with the MX25 flash and sends - * the deep power-down instruction, which sets the device to minimal - * power consumption. The SPI communication is disabled to free the USART. - ******************************************************************************/ -void sl_mx25_flash_shutdown(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif // SL_MX25_FLASH_SHUTDOWN_H +/***************************************************************************//** + * @file + * @brief MX25 flash shutdown + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_H +#define SL_MX25_FLASH_SHUTDOWN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "em_device.h" +#include "sl_mx25_flash_shutdown_usart_config.h" + +/***************************************************************************//** + * @addtogroup mx25_flash_shutdown MX25 SPI Flash Shutdown + * @brief Provide a function to put the MX25 SPI flash into deep power down + * mode to reduce power consumption. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Put the MX25 SPI flash into deep power down mode. + * + * This function initializes SPI communication with the MX25 flash and sends + * the deep power-down instruction, which sets the device to minimal + * power consumption. The SPI communication is disabled to free the USART. + ******************************************************************************/ +void sl_mx25_flash_shutdown(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif // SL_MX25_FLASH_SHUTDOWN_H diff --git a/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c b/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c index 6eec5a9..42ad519 100644 --- a/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c +++ b/locator_host/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c @@ -1,141 +1,141 @@ -/***************************************************************************//** - * @file - * @brief MX25 flash shutdown - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_cmu.h" -#include "em_usart.h" -#include "em_gpio.h" -#include "sl_udelay.h" -#include "sl_mx25_flash_shutdown.h" - -// Fallback to baudrate of 8 MHz if not defined for backwards compatibility -#ifndef SL_MX25_FLASH_SHUTDOWN_BAUDRATE -#define SL_MX25_FLASH_SHUTDOWN_BAUDRATE 8000000 -#endif - -// Define usart clock -#ifndef SL_MX25_FLASH_SHUTDOWN_CLK -#define MERGE(x, y) x##y -#define USART_CLOCK(n) MERGE(cmuClock_USART, n) -#define SL_MX25_FLASH_SHUTDOWN_CLK USART_CLOCK(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO) -#endif - -#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL -static void cs_low(void) -{ - GPIO_PinOutClear(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); -} - -static void cs_high(void) -{ - GPIO_PinOutSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); -} -#endif - -/***************************************************************************//** - * Puts the MX25 into deep power down mode. - ******************************************************************************/ -void sl_mx25_flash_shutdown(void) -{ -#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL - // Init flash - USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; - - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, true); - - init.msbf = true; - init.baudrate = SL_MX25_FLASH_SHUTDOWN_BAUDRATE; - - USART_InitSync(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init); - - // IO config - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeInput, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModePushPull, 1); - -#ifdef _GPIO_USART_ROUTEEN_MASK - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = ((SL_MX25_FLASH_SHUTDOWN_CLK_PORT << _GPIO_USART_CLKROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_CLK_PIN << _GPIO_USART_CLKROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = ((SL_MX25_FLASH_SHUTDOWN_RX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = ((SL_MX25_FLASH_SHUTDOWN_TX_PORT << _GPIO_USART_TXROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_TX_PIN << _GPIO_USART_TXROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = (GPIO_USART_ROUTEEN_RXPEN - | GPIO_USART_ROUTEEN_TXPEN - | GPIO_USART_ROUTEEN_CLKPEN); -#else - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = ((SL_MX25_FLASH_SHUTDOWN_RX_LOC << _USART_ROUTELOC0_RXLOC_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_TX_LOC << _USART_ROUTELOC0_TXLOC_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_CLK_LOC << _USART_ROUTELOC0_CLKLOC_SHIFT)); - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = (USART_ROUTEPEN_RXPEN - | USART_ROUTEPEN_TXPEN - | USART_ROUTEPEN_CLKPEN); -#endif - - // Wait for flash warm-up - sl_udelay_wait(800); // wait for tVSL=800us - - // Wake up flash in case the device is in deep power down mode already. - cs_low(); - sl_udelay_wait(20); // wait for tCRDP=20us - cs_high(); - sl_udelay_wait(35); // wait for tRDP=35us - - // Chip select go low to start a flash command - cs_low(); - - // Deep Power Down Mode command (0xB9) - USART_SpiTransfer(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9); - - // Chip select go high to end a flash command - cs_high(); - - // Deinit flash - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModeDisabled, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeDisabled, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModeDisabled, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModeDisabled, 1); - - USART_Reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL); - -#ifdef _GPIO_USART_ROUTEEN_MASK - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; -#else - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; -#endif - - CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, false); -#endif -} +/***************************************************************************//** + * @file + * @brief MX25 flash shutdown + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_cmu.h" +#include "em_usart.h" +#include "em_gpio.h" +#include "sl_udelay.h" +#include "sl_mx25_flash_shutdown.h" + +// Fallback to baudrate of 8 MHz if not defined for backwards compatibility +#ifndef SL_MX25_FLASH_SHUTDOWN_BAUDRATE +#define SL_MX25_FLASH_SHUTDOWN_BAUDRATE 8000000 +#endif + +// Define usart clock +#ifndef SL_MX25_FLASH_SHUTDOWN_CLK +#define MERGE(x, y) x##y +#define USART_CLOCK(n) MERGE(cmuClock_USART, n) +#define SL_MX25_FLASH_SHUTDOWN_CLK USART_CLOCK(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO) +#endif + +#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL +static void cs_low(void) +{ + GPIO_PinOutClear(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); +} + +static void cs_high(void) +{ + GPIO_PinOutSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); +} +#endif + +/***************************************************************************//** + * Puts the MX25 into deep power down mode. + ******************************************************************************/ +void sl_mx25_flash_shutdown(void) +{ +#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL + // Init flash + USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; + + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, true); + + init.msbf = true; + init.baudrate = SL_MX25_FLASH_SHUTDOWN_BAUDRATE; + + USART_InitSync(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init); + + // IO config + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModePushPull, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeInput, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModePushPull, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModePushPull, 1); + +#ifdef _GPIO_USART_ROUTEEN_MASK + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = ((SL_MX25_FLASH_SHUTDOWN_CLK_PORT << _GPIO_USART_CLKROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_CLK_PIN << _GPIO_USART_CLKROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = ((SL_MX25_FLASH_SHUTDOWN_RX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = ((SL_MX25_FLASH_SHUTDOWN_TX_PORT << _GPIO_USART_TXROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_TX_PIN << _GPIO_USART_TXROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = (GPIO_USART_ROUTEEN_RXPEN + | GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_CLKPEN); +#else + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = ((SL_MX25_FLASH_SHUTDOWN_RX_LOC << _USART_ROUTELOC0_RXLOC_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_TX_LOC << _USART_ROUTELOC0_TXLOC_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_CLK_LOC << _USART_ROUTELOC0_CLKLOC_SHIFT)); + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = (USART_ROUTEPEN_RXPEN + | USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_CLKPEN); +#endif + + // Wait for flash warm-up + sl_udelay_wait(800); // wait for tVSL=800us + + // Wake up flash in case the device is in deep power down mode already. + cs_low(); + sl_udelay_wait(20); // wait for tCRDP=20us + cs_high(); + sl_udelay_wait(35); // wait for tRDP=35us + + // Chip select go low to start a flash command + cs_low(); + + // Deep Power Down Mode command (0xB9) + USART_SpiTransfer(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9); + + // Chip select go high to end a flash command + cs_high(); + + // Deinit flash + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModeDisabled, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeDisabled, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModeDisabled, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModeDisabled, 1); + + USART_Reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL); + +#ifdef _GPIO_USART_ROUTEEN_MASK + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; +#else + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; +#endif + + CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, false); +#endif +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h index adbf296..21a2c71 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h @@ -1,283 +1,283 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h index 67bda4e..045aaf1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h @@ -1,2211 +1,2211 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h index 2f048e4..a196dfd 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h @@ -1,39 +1,39 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.4 - * @date 23. July 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h index f9cf6ab..4dbde81 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h @@ -1,3265 +1,3265 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h index 3de16ef..b6ff9a9 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h @@ -1,352 +1,352 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h index 0d09749..d4c1474 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h +++ b/locator_host/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h @@ -1,70 +1,70 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h index 9b04234..1306c3f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_acmp.h @@ -1,654 +1,654 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 ACMP register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_ACMP_H -#define EFR32MG24_ACMP_H -#define ACMP_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_ACMP ACMP - * @{ - * @brief EFR32MG24 ACMP Register Declaration. - *****************************************************************************/ - -/** ACMP Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< ACMP enable */ - __IOM uint32_t SWRST; /**< Software reset */ - __IOM uint32_t CFG; /**< Configuration register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t INPUTCTRL; /**< Input Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Syncbusy */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< ACMP enable */ - __IOM uint32_t SWRST_SET; /**< Software reset */ - __IOM uint32_t CFG_SET; /**< Configuration register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< ACMP enable */ - __IOM uint32_t SWRST_CLR; /**< Software reset */ - __IOM uint32_t CFG_CLR; /**< Configuration register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< ACMP enable */ - __IOM uint32_t SWRST_TGL; /**< Software reset */ - __IOM uint32_t CFG_TGL; /**< Configuration register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ -} ACMP_TypeDef; -/** @} End of group EFR32MG24_ACMP */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_ACMP - * @{ - * @defgroup EFR32MG24_ACMP_BitFields ACMP Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for ACMP IPVERSION */ -#define _ACMP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ -#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ACMP_IPVERSION */ -#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ - -/* Bit fields for ACMP EN */ -#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ -#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ -#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ -#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ -#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ -#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ -#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ -#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ - -/* Bit fields for ACMP SWRST */ -#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ -#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ -#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ -#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ -#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ -#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ -#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ - -/* Bit fields for ACMP CFG */ -#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ -#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ -#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ -#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ -#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ -#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ -#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ -#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ -#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ -#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ -#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ -#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ -#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ -#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ -#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ -#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ -#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ - -/* Bit fields for ACMP CTRL */ -#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ -#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ -#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ -#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ -#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ -#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ -#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ -#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ -#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ -#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ - -/* Bit fields for ACMP INPUTCTRL */ -#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ -#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 0x00000041UL /**< Mode VDAC0OUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 0x00000043UL /**< Mode VDAC1OUT1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 << 0) /**< Shifted mode VDAC0OUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 << 0) /**< Shifted mode VDAC1OUT1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ -#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ -#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ -#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ -#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ -#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ -#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ - -/* Bit fields for ACMP STATUS */ -#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ -#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ -#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ -#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ -#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ -#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ -#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ - -/* Bit fields for ACMP IF */ -#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ -#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ -#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ -#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ -#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ -#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ -#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ -#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ -#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ - -/* Bit fields for ACMP IEN */ -#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ -#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ -#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ -#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ -#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ -#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ -#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ -#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ -#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ -#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ -#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ -#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ -#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ -#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ -#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ -#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ - -/* Bit fields for ACMP SYNCBUSY */ -#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ -#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ -#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ -#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ - -/** @} End of group EFR32MG24_ACMP_BitFields */ -/** @} End of group EFR32MG24_ACMP */ -/** @} End of group Parts */ - -#endif // EFR32MG24_ACMP_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 ACMP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ACMP_H +#define EFR32MG24_ACMP_H +#define ACMP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ACMP ACMP + * @{ + * @brief EFR32MG24 ACMP Register Declaration. + *****************************************************************************/ + +/** ACMP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< ACMP enable */ + __IOM uint32_t SWRST; /**< Software reset */ + __IOM uint32_t CFG; /**< Configuration register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t INPUTCTRL; /**< Input Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< ACMP enable */ + __IOM uint32_t SWRST_SET; /**< Software reset */ + __IOM uint32_t CFG_SET; /**< Configuration register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t INPUTCTRL_SET; /**< Input Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< ACMP enable */ + __IOM uint32_t SWRST_CLR; /**< Software reset */ + __IOM uint32_t CFG_CLR; /**< Configuration register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t INPUTCTRL_CLR; /**< Input Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< ACMP enable */ + __IOM uint32_t SWRST_TGL; /**< Software reset */ + __IOM uint32_t CFG_TGL; /**< Configuration register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t INPUTCTRL_TGL; /**< Input Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy */ +} ACMP_TypeDef; +/** @} End of group EFR32MG24_ACMP */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ACMP + * @{ + * @defgroup EFR32MG24_ACMP_BitFields ACMP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ACMP IPVERSION */ +#define _ACMP_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ACMP_IPVERSION */ +#define _ACMP_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for ACMP_IPVERSION */ +#define ACMP_IPVERSION_IPVERSION_DEFAULT (_ACMP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IPVERSION */ + +/* Bit fields for ACMP EN */ +#define _ACMP_EN_RESETVALUE 0x00000000UL /**< Default value for ACMP_EN */ +#define _ACMP_EN_MASK 0x00000003UL /**< Mask for ACMP_EN */ +#define ACMP_EN_EN (0x1UL << 0) /**< Module enable */ +#define _ACMP_EN_EN_SHIFT 0 /**< Shift value for ACMP_EN */ +#define _ACMP_EN_EN_MASK 0x1UL /**< Bit mask for ACMP_EN */ +#define _ACMP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_EN_DEFAULT (_ACMP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _ACMP_EN_DISABLING_SHIFT 1 /**< Shift value for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_MASK 0x2UL /**< Bit mask for ACMP_DISABLING */ +#define _ACMP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_EN */ +#define ACMP_EN_DISABLING_DEFAULT (_ACMP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_EN */ + +/* Bit fields for ACMP SWRST */ +#define _ACMP_SWRST_RESETVALUE 0x00000000UL /**< Default value for ACMP_SWRST */ +#define _ACMP_SWRST_MASK 0x00000003UL /**< Mask for ACMP_SWRST */ +#define ACMP_SWRST_SWRST (0x1UL << 0) /**< Software reset */ +#define _ACMP_SWRST_SWRST_SHIFT 0 /**< Shift value for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for ACMP_SWRST */ +#define _ACMP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_SWRST_DEFAULT (_ACMP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _ACMP_SWRST_RESETTING_SHIFT 1 /**< Shift value for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for ACMP_RESETTING */ +#define _ACMP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SWRST */ +#define ACMP_SWRST_RESETTING_DEFAULT (_ACMP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_SWRST */ + +/* Bit fields for ACMP CFG */ +#define _ACMP_CFG_RESETVALUE 0x00000004UL /**< Default value for ACMP_CFG */ +#define _ACMP_CFG_MASK 0x00030F07UL /**< Mask for ACMP_CFG */ +#define _ACMP_CFG_BIAS_SHIFT 0 /**< Shift value for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_MASK 0x7UL /**< Bit mask for ACMP_BIAS */ +#define _ACMP_CFG_BIAS_DEFAULT 0x00000004UL /**< Mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_BIAS_DEFAULT (_ACMP_CFG_BIAS_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_SHIFT 8 /**< Shift value for ACMP_HYST */ +#define _ACMP_CFG_HYST_MASK 0xF00UL /**< Bit mask for ACMP_HYST */ +#define _ACMP_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_HYST_DISABLED 0x00000000UL /**< Mode DISABLED for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM10MV 0x00000001UL /**< Mode SYM10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM20MV 0x00000002UL /**< Mode SYM20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_SYM30MV 0x00000003UL /**< Mode SYM30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS10MV 0x00000004UL /**< Mode POS10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS20MV 0x00000005UL /**< Mode POS20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_POS30MV 0x00000006UL /**< Mode POS30MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG10MV 0x00000008UL /**< Mode NEG10MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG20MV 0x00000009UL /**< Mode NEG20MV for ACMP_CFG */ +#define _ACMP_CFG_HYST_NEG30MV 0x0000000AUL /**< Mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_DEFAULT (_ACMP_CFG_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_HYST_DISABLED (_ACMP_CFG_HYST_DISABLED << 8) /**< Shifted mode DISABLED for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM10MV (_ACMP_CFG_HYST_SYM10MV << 8) /**< Shifted mode SYM10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM20MV (_ACMP_CFG_HYST_SYM20MV << 8) /**< Shifted mode SYM20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_SYM30MV (_ACMP_CFG_HYST_SYM30MV << 8) /**< Shifted mode SYM30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS10MV (_ACMP_CFG_HYST_POS10MV << 8) /**< Shifted mode POS10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS20MV (_ACMP_CFG_HYST_POS20MV << 8) /**< Shifted mode POS20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_POS30MV (_ACMP_CFG_HYST_POS30MV << 8) /**< Shifted mode POS30MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG10MV (_ACMP_CFG_HYST_NEG10MV << 8) /**< Shifted mode NEG10MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG20MV (_ACMP_CFG_HYST_NEG20MV << 8) /**< Shifted mode NEG20MV for ACMP_CFG */ +#define ACMP_CFG_HYST_NEG30MV (_ACMP_CFG_HYST_NEG30MV << 8) /**< Shifted mode NEG30MV for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE (0x1UL << 16) /**< Input Range */ +#define _ACMP_CFG_INPUTRANGE_SHIFT 16 /**< Shift value for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_MASK 0x10000UL /**< Bit mask for ACMP_INPUTRANGE */ +#define _ACMP_CFG_INPUTRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_FULL 0x00000000UL /**< Mode FULL for ACMP_CFG */ +#define _ACMP_CFG_INPUTRANGE_REDUCED 0x00000001UL /**< Mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_DEFAULT (_ACMP_CFG_INPUTRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_FULL (_ACMP_CFG_INPUTRANGE_FULL << 16) /**< Shifted mode FULL for ACMP_CFG */ +#define ACMP_CFG_INPUTRANGE_REDUCED (_ACMP_CFG_INPUTRANGE_REDUCED << 16) /**< Shifted mode REDUCED for ACMP_CFG */ +#define ACMP_CFG_ACCURACY (0x1UL << 17) /**< ACMP accuracy mode */ +#define _ACMP_CFG_ACCURACY_SHIFT 17 /**< Shift value for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_MASK 0x20000UL /**< Bit mask for ACMP_ACCURACY */ +#define _ACMP_CFG_ACCURACY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_LOW 0x00000000UL /**< Mode LOW for ACMP_CFG */ +#define _ACMP_CFG_ACCURACY_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_DEFAULT (_ACMP_CFG_ACCURACY_DEFAULT << 17) /**< Shifted mode DEFAULT for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_LOW (_ACMP_CFG_ACCURACY_LOW << 17) /**< Shifted mode LOW for ACMP_CFG */ +#define ACMP_CFG_ACCURACY_HIGH (_ACMP_CFG_ACCURACY_HIGH << 17) /**< Shifted mode HIGH for ACMP_CFG */ + +/* Bit fields for ACMP CTRL */ +#define _ACMP_CTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_CTRL */ +#define _ACMP_CTRL_MASK 0x00000003UL /**< Mask for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL (0x1UL << 0) /**< Not Ready Value */ +#define _ACMP_CTRL_NOTRDYVAL_SHIFT 0 /**< Shift value for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_MASK 0x1UL /**< Bit mask for ACMP_NOTRDYVAL */ +#define _ACMP_CTRL_NOTRDYVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_LOW 0x00000000UL /**< Mode LOW for ACMP_CTRL */ +#define _ACMP_CTRL_NOTRDYVAL_HIGH 0x00000001UL /**< Mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_DEFAULT (_ACMP_CTRL_NOTRDYVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_LOW (_ACMP_CTRL_NOTRDYVAL_LOW << 0) /**< Shifted mode LOW for ACMP_CTRL */ +#define ACMP_CTRL_NOTRDYVAL_HIGH (_ACMP_CTRL_NOTRDYVAL_HIGH << 0) /**< Shifted mode HIGH for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV (0x1UL << 1) /**< Comparator GPIO Output Invert */ +#define _ACMP_CTRL_GPIOINV_SHIFT 1 /**< Shift value for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_MASK 0x2UL /**< Bit mask for ACMP_GPIOINV */ +#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /**< Mode NOTINV for ACMP_CTRL */ +#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /**< Mode INV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 1) /**< Shifted mode NOTINV for ACMP_CTRL */ +#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 1) /**< Shifted mode INV for ACMP_CTRL */ + +/* Bit fields for ACMP INPUTCTRL */ +#define _ACMP_INPUTCTRL_RESETVALUE 0x00000000UL /**< Default value for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_MASK 0x703FFFFFUL /**< Mask for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_SHIFT 0 /**< Shift value for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_MASK 0xFFUL /**< Bit mask for ACMP_POSSEL */ +#define _ACMP_INPUTCTRL_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 0x00000041UL /**< Mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 0x00000043UL /**< Mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPA 0x00000050UL /**< Mode EXTPA for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPB 0x00000051UL /**< Mode EXTPB for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPC 0x00000052UL /**< Mode EXTPC for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_EXTPD 0x00000053UL /**< Mode EXTPD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_POSSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_DEFAULT (_ACMP_INPUTCTRL_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VSS (_ACMP_INPUTCTRL_POSSEL_VSS << 0) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD << 0) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP << 0) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25 << 0) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP << 0) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5 << 0) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP << 0) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4 << 0) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP << 0) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4 << 0) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP << 0) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1 << 0) /**< Shifted mode VDAC0OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 (_ACMP_INPUTCTRL_POSSEL_VDAC1OUT1 << 0) /**< Shifted mode VDAC1OUT1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPA (_ACMP_INPUTCTRL_POSSEL_EXTPA << 0) /**< Shifted mode EXTPA for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPB (_ACMP_INPUTCTRL_POSSEL_EXTPB << 0) /**< Shifted mode EXTPB for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPC (_ACMP_INPUTCTRL_POSSEL_EXTPC << 0) /**< Shifted mode EXTPC for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_EXTPD (_ACMP_INPUTCTRL_POSSEL_EXTPD << 0) /**< Shifted mode EXTPD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA0 (_ACMP_INPUTCTRL_POSSEL_PA0 << 0) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA1 (_ACMP_INPUTCTRL_POSSEL_PA1 << 0) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA2 (_ACMP_INPUTCTRL_POSSEL_PA2 << 0) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA3 (_ACMP_INPUTCTRL_POSSEL_PA3 << 0) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA4 (_ACMP_INPUTCTRL_POSSEL_PA4 << 0) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA5 (_ACMP_INPUTCTRL_POSSEL_PA5 << 0) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA6 (_ACMP_INPUTCTRL_POSSEL_PA6 << 0) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA7 (_ACMP_INPUTCTRL_POSSEL_PA7 << 0) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA8 (_ACMP_INPUTCTRL_POSSEL_PA8 << 0) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA9 (_ACMP_INPUTCTRL_POSSEL_PA9 << 0) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA10 (_ACMP_INPUTCTRL_POSSEL_PA10 << 0) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA11 (_ACMP_INPUTCTRL_POSSEL_PA11 << 0) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA12 (_ACMP_INPUTCTRL_POSSEL_PA12 << 0) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA13 (_ACMP_INPUTCTRL_POSSEL_PA13 << 0) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA14 (_ACMP_INPUTCTRL_POSSEL_PA14 << 0) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PA15 (_ACMP_INPUTCTRL_POSSEL_PA15 << 0) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB0 (_ACMP_INPUTCTRL_POSSEL_PB0 << 0) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB1 (_ACMP_INPUTCTRL_POSSEL_PB1 << 0) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB2 (_ACMP_INPUTCTRL_POSSEL_PB2 << 0) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB3 (_ACMP_INPUTCTRL_POSSEL_PB3 << 0) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB4 (_ACMP_INPUTCTRL_POSSEL_PB4 << 0) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB5 (_ACMP_INPUTCTRL_POSSEL_PB5 << 0) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB6 (_ACMP_INPUTCTRL_POSSEL_PB6 << 0) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB7 (_ACMP_INPUTCTRL_POSSEL_PB7 << 0) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB8 (_ACMP_INPUTCTRL_POSSEL_PB8 << 0) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB9 (_ACMP_INPUTCTRL_POSSEL_PB9 << 0) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB10 (_ACMP_INPUTCTRL_POSSEL_PB10 << 0) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB11 (_ACMP_INPUTCTRL_POSSEL_PB11 << 0) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB12 (_ACMP_INPUTCTRL_POSSEL_PB12 << 0) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB13 (_ACMP_INPUTCTRL_POSSEL_PB13 << 0) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB14 (_ACMP_INPUTCTRL_POSSEL_PB14 << 0) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PB15 (_ACMP_INPUTCTRL_POSSEL_PB15 << 0) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC0 (_ACMP_INPUTCTRL_POSSEL_PC0 << 0) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC1 (_ACMP_INPUTCTRL_POSSEL_PC1 << 0) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC2 (_ACMP_INPUTCTRL_POSSEL_PC2 << 0) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC3 (_ACMP_INPUTCTRL_POSSEL_PC3 << 0) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC4 (_ACMP_INPUTCTRL_POSSEL_PC4 << 0) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC5 (_ACMP_INPUTCTRL_POSSEL_PC5 << 0) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC6 (_ACMP_INPUTCTRL_POSSEL_PC6 << 0) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC7 (_ACMP_INPUTCTRL_POSSEL_PC7 << 0) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC8 (_ACMP_INPUTCTRL_POSSEL_PC8 << 0) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC9 (_ACMP_INPUTCTRL_POSSEL_PC9 << 0) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC10 (_ACMP_INPUTCTRL_POSSEL_PC10 << 0) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC11 (_ACMP_INPUTCTRL_POSSEL_PC11 << 0) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC12 (_ACMP_INPUTCTRL_POSSEL_PC12 << 0) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC13 (_ACMP_INPUTCTRL_POSSEL_PC13 << 0) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC14 (_ACMP_INPUTCTRL_POSSEL_PC14 << 0) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PC15 (_ACMP_INPUTCTRL_POSSEL_PC15 << 0) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD0 (_ACMP_INPUTCTRL_POSSEL_PD0 << 0) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD1 (_ACMP_INPUTCTRL_POSSEL_PD1 << 0) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD2 (_ACMP_INPUTCTRL_POSSEL_PD2 << 0) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD3 (_ACMP_INPUTCTRL_POSSEL_PD3 << 0) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD4 (_ACMP_INPUTCTRL_POSSEL_PD4 << 0) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD5 (_ACMP_INPUTCTRL_POSSEL_PD5 << 0) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD6 (_ACMP_INPUTCTRL_POSSEL_PD6 << 0) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD7 (_ACMP_INPUTCTRL_POSSEL_PD7 << 0) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD8 (_ACMP_INPUTCTRL_POSSEL_PD8 << 0) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD9 (_ACMP_INPUTCTRL_POSSEL_PD9 << 0) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD10 (_ACMP_INPUTCTRL_POSSEL_PD10 << 0) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD11 (_ACMP_INPUTCTRL_POSSEL_PD11 << 0) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD12 (_ACMP_INPUTCTRL_POSSEL_PD12 << 0) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD13 (_ACMP_INPUTCTRL_POSSEL_PD13 << 0) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD14 (_ACMP_INPUTCTRL_POSSEL_PD14 << 0) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_POSSEL_PD15 (_ACMP_INPUTCTRL_POSSEL_PD15 << 0) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_SHIFT 8 /**< Shift value for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_MASK 0xFF00UL /**< Bit mask for ACMP_NEGSEL */ +#define _ACMP_INPUTCTRL_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSS 0x00000000UL /**< Mode VSS for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD 0x00000010UL /**< Mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP 0x00000011UL /**< Mode VREFDIVAVDDLP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 0x00000012UL /**< Mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP 0x00000013UL /**< Mode VREFDIV1V25LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 0x00000014UL /**< Mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP 0x00000015UL /**< Mode VREFDIV2V5LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 0x00000020UL /**< Mode VSENSE01DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP 0x00000021UL /**< Mode VSENSE01DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 0x00000022UL /**< Mode VSENSE11DIV4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP 0x00000023UL /**< Mode VSENSE11DIV4LP for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_CAPSENSE 0x00000030UL /**< Mode CAPSENSE for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 0x00000040UL /**< Mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 0x00000042UL /**< Mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA0 0x00000080UL /**< Mode PA0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA1 0x00000081UL /**< Mode PA1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA2 0x00000082UL /**< Mode PA2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA3 0x00000083UL /**< Mode PA3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA4 0x00000084UL /**< Mode PA4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA5 0x00000085UL /**< Mode PA5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA6 0x00000086UL /**< Mode PA6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA7 0x00000087UL /**< Mode PA7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA8 0x00000088UL /**< Mode PA8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA9 0x00000089UL /**< Mode PA9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA10 0x0000008AUL /**< Mode PA10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA11 0x0000008BUL /**< Mode PA11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA12 0x0000008CUL /**< Mode PA12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA13 0x0000008DUL /**< Mode PA13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA14 0x0000008EUL /**< Mode PA14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PA15 0x0000008FUL /**< Mode PA15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB0 0x00000090UL /**< Mode PB0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB1 0x00000091UL /**< Mode PB1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB2 0x00000092UL /**< Mode PB2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB3 0x00000093UL /**< Mode PB3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB4 0x00000094UL /**< Mode PB4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB5 0x00000095UL /**< Mode PB5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB6 0x00000096UL /**< Mode PB6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB7 0x00000097UL /**< Mode PB7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB8 0x00000098UL /**< Mode PB8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB9 0x00000099UL /**< Mode PB9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB10 0x0000009AUL /**< Mode PB10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB11 0x0000009BUL /**< Mode PB11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB12 0x0000009CUL /**< Mode PB12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB13 0x0000009DUL /**< Mode PB13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB14 0x0000009EUL /**< Mode PB14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PB15 0x0000009FUL /**< Mode PB15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC0 0x000000A0UL /**< Mode PC0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC1 0x000000A1UL /**< Mode PC1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC2 0x000000A2UL /**< Mode PC2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC3 0x000000A3UL /**< Mode PC3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC4 0x000000A4UL /**< Mode PC4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC5 0x000000A5UL /**< Mode PC5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC6 0x000000A6UL /**< Mode PC6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC7 0x000000A7UL /**< Mode PC7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC8 0x000000A8UL /**< Mode PC8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC9 0x000000A9UL /**< Mode PC9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC10 0x000000AAUL /**< Mode PC10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC11 0x000000ABUL /**< Mode PC11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC12 0x000000ACUL /**< Mode PC12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC13 0x000000ADUL /**< Mode PC13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC14 0x000000AEUL /**< Mode PC14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PC15 0x000000AFUL /**< Mode PC15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD0 0x000000B0UL /**< Mode PD0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD1 0x000000B1UL /**< Mode PD1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD2 0x000000B2UL /**< Mode PD2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD3 0x000000B3UL /**< Mode PD3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD4 0x000000B4UL /**< Mode PD4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD5 0x000000B5UL /**< Mode PD5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD6 0x000000B6UL /**< Mode PD6 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD7 0x000000B7UL /**< Mode PD7 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD8 0x000000B8UL /**< Mode PD8 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD9 0x000000B9UL /**< Mode PD9 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD10 0x000000BAUL /**< Mode PD10 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD11 0x000000BBUL /**< Mode PD11 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD12 0x000000BCUL /**< Mode PD12 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD13 0x000000BDUL /**< Mode PD13 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD14 0x000000BEUL /**< Mode PD14 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_NEGSEL_PD15 0x000000BFUL /**< Mode PD15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_DEFAULT (_ACMP_INPUTCTRL_NEGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VSS (_ACMP_INPUTCTRL_NEGSEL_VSS << 8) /**< Shifted mode VSS for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDD << 8) /**< Shifted mode VREFDIVAVDD for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP (_ACMP_INPUTCTRL_NEGSEL_VREFDIVAVDDLP << 8) /**< Shifted mode VREFDIVAVDDLP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25 << 8) /**< Shifted mode VREFDIV1V25 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV1V25LP << 8) /**< Shifted mode VREFDIV1V25LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5 << 8) /**< Shifted mode VREFDIV2V5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP (_ACMP_INPUTCTRL_NEGSEL_VREFDIV2V5LP << 8) /**< Shifted mode VREFDIV2V5LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4 << 8) /**< Shifted mode VSENSE01DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE01DIV4LP << 8) /**< Shifted mode VSENSE01DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4 << 8) /**< Shifted mode VSENSE11DIV4 for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP (_ACMP_INPUTCTRL_NEGSEL_VSENSE11DIV4LP << 8) /**< Shifted mode VSENSE11DIV4LP for ACMP_INPUTCTRL*/ +#define ACMP_INPUTCTRL_NEGSEL_CAPSENSE (_ACMP_INPUTCTRL_NEGSEL_CAPSENSE << 8) /**< Shifted mode CAPSENSE for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC0OUT0 << 8) /**< Shifted mode VDAC0OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 (_ACMP_INPUTCTRL_NEGSEL_VDAC1OUT0 << 8) /**< Shifted mode VDAC1OUT0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA0 (_ACMP_INPUTCTRL_NEGSEL_PA0 << 8) /**< Shifted mode PA0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA1 (_ACMP_INPUTCTRL_NEGSEL_PA1 << 8) /**< Shifted mode PA1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA2 (_ACMP_INPUTCTRL_NEGSEL_PA2 << 8) /**< Shifted mode PA2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA3 (_ACMP_INPUTCTRL_NEGSEL_PA3 << 8) /**< Shifted mode PA3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA4 (_ACMP_INPUTCTRL_NEGSEL_PA4 << 8) /**< Shifted mode PA4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA5 (_ACMP_INPUTCTRL_NEGSEL_PA5 << 8) /**< Shifted mode PA5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA6 (_ACMP_INPUTCTRL_NEGSEL_PA6 << 8) /**< Shifted mode PA6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA7 (_ACMP_INPUTCTRL_NEGSEL_PA7 << 8) /**< Shifted mode PA7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA8 (_ACMP_INPUTCTRL_NEGSEL_PA8 << 8) /**< Shifted mode PA8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA9 (_ACMP_INPUTCTRL_NEGSEL_PA9 << 8) /**< Shifted mode PA9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA10 (_ACMP_INPUTCTRL_NEGSEL_PA10 << 8) /**< Shifted mode PA10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA11 (_ACMP_INPUTCTRL_NEGSEL_PA11 << 8) /**< Shifted mode PA11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA12 (_ACMP_INPUTCTRL_NEGSEL_PA12 << 8) /**< Shifted mode PA12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA13 (_ACMP_INPUTCTRL_NEGSEL_PA13 << 8) /**< Shifted mode PA13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA14 (_ACMP_INPUTCTRL_NEGSEL_PA14 << 8) /**< Shifted mode PA14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PA15 (_ACMP_INPUTCTRL_NEGSEL_PA15 << 8) /**< Shifted mode PA15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB0 (_ACMP_INPUTCTRL_NEGSEL_PB0 << 8) /**< Shifted mode PB0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB1 (_ACMP_INPUTCTRL_NEGSEL_PB1 << 8) /**< Shifted mode PB1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB2 (_ACMP_INPUTCTRL_NEGSEL_PB2 << 8) /**< Shifted mode PB2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB3 (_ACMP_INPUTCTRL_NEGSEL_PB3 << 8) /**< Shifted mode PB3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB4 (_ACMP_INPUTCTRL_NEGSEL_PB4 << 8) /**< Shifted mode PB4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB5 (_ACMP_INPUTCTRL_NEGSEL_PB5 << 8) /**< Shifted mode PB5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB6 (_ACMP_INPUTCTRL_NEGSEL_PB6 << 8) /**< Shifted mode PB6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB7 (_ACMP_INPUTCTRL_NEGSEL_PB7 << 8) /**< Shifted mode PB7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB8 (_ACMP_INPUTCTRL_NEGSEL_PB8 << 8) /**< Shifted mode PB8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB9 (_ACMP_INPUTCTRL_NEGSEL_PB9 << 8) /**< Shifted mode PB9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB10 (_ACMP_INPUTCTRL_NEGSEL_PB10 << 8) /**< Shifted mode PB10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB11 (_ACMP_INPUTCTRL_NEGSEL_PB11 << 8) /**< Shifted mode PB11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB12 (_ACMP_INPUTCTRL_NEGSEL_PB12 << 8) /**< Shifted mode PB12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB13 (_ACMP_INPUTCTRL_NEGSEL_PB13 << 8) /**< Shifted mode PB13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB14 (_ACMP_INPUTCTRL_NEGSEL_PB14 << 8) /**< Shifted mode PB14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PB15 (_ACMP_INPUTCTRL_NEGSEL_PB15 << 8) /**< Shifted mode PB15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC0 (_ACMP_INPUTCTRL_NEGSEL_PC0 << 8) /**< Shifted mode PC0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC1 (_ACMP_INPUTCTRL_NEGSEL_PC1 << 8) /**< Shifted mode PC1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC2 (_ACMP_INPUTCTRL_NEGSEL_PC2 << 8) /**< Shifted mode PC2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC3 (_ACMP_INPUTCTRL_NEGSEL_PC3 << 8) /**< Shifted mode PC3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC4 (_ACMP_INPUTCTRL_NEGSEL_PC4 << 8) /**< Shifted mode PC4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC5 (_ACMP_INPUTCTRL_NEGSEL_PC5 << 8) /**< Shifted mode PC5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC6 (_ACMP_INPUTCTRL_NEGSEL_PC6 << 8) /**< Shifted mode PC6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC7 (_ACMP_INPUTCTRL_NEGSEL_PC7 << 8) /**< Shifted mode PC7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC8 (_ACMP_INPUTCTRL_NEGSEL_PC8 << 8) /**< Shifted mode PC8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC9 (_ACMP_INPUTCTRL_NEGSEL_PC9 << 8) /**< Shifted mode PC9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC10 (_ACMP_INPUTCTRL_NEGSEL_PC10 << 8) /**< Shifted mode PC10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC11 (_ACMP_INPUTCTRL_NEGSEL_PC11 << 8) /**< Shifted mode PC11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC12 (_ACMP_INPUTCTRL_NEGSEL_PC12 << 8) /**< Shifted mode PC12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC13 (_ACMP_INPUTCTRL_NEGSEL_PC13 << 8) /**< Shifted mode PC13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC14 (_ACMP_INPUTCTRL_NEGSEL_PC14 << 8) /**< Shifted mode PC14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PC15 (_ACMP_INPUTCTRL_NEGSEL_PC15 << 8) /**< Shifted mode PC15 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD0 (_ACMP_INPUTCTRL_NEGSEL_PD0 << 8) /**< Shifted mode PD0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD1 (_ACMP_INPUTCTRL_NEGSEL_PD1 << 8) /**< Shifted mode PD1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD2 (_ACMP_INPUTCTRL_NEGSEL_PD2 << 8) /**< Shifted mode PD2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD3 (_ACMP_INPUTCTRL_NEGSEL_PD3 << 8) /**< Shifted mode PD3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD4 (_ACMP_INPUTCTRL_NEGSEL_PD4 << 8) /**< Shifted mode PD4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD5 (_ACMP_INPUTCTRL_NEGSEL_PD5 << 8) /**< Shifted mode PD5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD6 (_ACMP_INPUTCTRL_NEGSEL_PD6 << 8) /**< Shifted mode PD6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD7 (_ACMP_INPUTCTRL_NEGSEL_PD7 << 8) /**< Shifted mode PD7 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD8 (_ACMP_INPUTCTRL_NEGSEL_PD8 << 8) /**< Shifted mode PD8 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD9 (_ACMP_INPUTCTRL_NEGSEL_PD9 << 8) /**< Shifted mode PD9 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD10 (_ACMP_INPUTCTRL_NEGSEL_PD10 << 8) /**< Shifted mode PD10 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD11 (_ACMP_INPUTCTRL_NEGSEL_PD11 << 8) /**< Shifted mode PD11 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD12 (_ACMP_INPUTCTRL_NEGSEL_PD12 << 8) /**< Shifted mode PD12 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD13 (_ACMP_INPUTCTRL_NEGSEL_PD13 << 8) /**< Shifted mode PD13 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD14 (_ACMP_INPUTCTRL_NEGSEL_PD14 << 8) /**< Shifted mode PD14 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_NEGSEL_PD15 (_ACMP_INPUTCTRL_NEGSEL_PD15 << 8) /**< Shifted mode PD15 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_VREFDIV_SHIFT 16 /**< Shift value for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_MASK 0x3F0000UL /**< Bit mask for ACMP_VREFDIV */ +#define _ACMP_INPUTCTRL_VREFDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_VREFDIV_DEFAULT (_ACMP_INPUTCTRL_VREFDIV_DEFAULT << 16) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_SHIFT 28 /**< Shift value for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_MASK 0x70000000UL /**< Bit mask for ACMP_CSRESSEL */ +#define _ACMP_INPUTCTRL_CSRESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES0 0x00000000UL /**< Mode RES0 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES1 0x00000001UL /**< Mode RES1 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES2 0x00000002UL /**< Mode RES2 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES3 0x00000003UL /**< Mode RES3 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES4 0x00000004UL /**< Mode RES4 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES5 0x00000005UL /**< Mode RES5 for ACMP_INPUTCTRL */ +#define _ACMP_INPUTCTRL_CSRESSEL_RES6 0x00000006UL /**< Mode RES6 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_DEFAULT (_ACMP_INPUTCTRL_CSRESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES0 (_ACMP_INPUTCTRL_CSRESSEL_RES0 << 28) /**< Shifted mode RES0 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES1 (_ACMP_INPUTCTRL_CSRESSEL_RES1 << 28) /**< Shifted mode RES1 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES2 (_ACMP_INPUTCTRL_CSRESSEL_RES2 << 28) /**< Shifted mode RES2 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES3 (_ACMP_INPUTCTRL_CSRESSEL_RES3 << 28) /**< Shifted mode RES3 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES4 (_ACMP_INPUTCTRL_CSRESSEL_RES4 << 28) /**< Shifted mode RES4 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES5 (_ACMP_INPUTCTRL_CSRESSEL_RES5 << 28) /**< Shifted mode RES5 for ACMP_INPUTCTRL */ +#define ACMP_INPUTCTRL_CSRESSEL_RES6 (_ACMP_INPUTCTRL_CSRESSEL_RES6 << 28) /**< Shifted mode RES6 for ACMP_INPUTCTRL */ + +/* Bit fields for ACMP STATUS */ +#define _ACMP_STATUS_RESETVALUE 0x00000000UL /**< Default value for ACMP_STATUS */ +#define _ACMP_STATUS_MASK 0x0000001DUL /**< Mask for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (0x1UL << 0) /**< Analog Comparator Output */ +#define _ACMP_STATUS_ACMPOUT_SHIFT 0 /**< Shift value for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_MASK 0x1UL /**< Bit mask for ACMP_ACMPOUT */ +#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY (0x1UL << 2) /**< Analog Comparator Ready */ +#define _ACMP_STATUS_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_STATUS_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_ACMPRDY_DEFAULT (_ACMP_STATUS_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT (0x1UL << 3) /**< INPUT conflict */ +#define _ACMP_STATUS_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_STATUS_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_INPUTCONFLICT_DEFAULT (_ACMP_STATUS_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_STATUS_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_STATUS_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_STATUS */ +#define ACMP_STATUS_PORTALLOCERR_DEFAULT (_ACMP_STATUS_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_STATUS */ + +/* Bit fields for ACMP IF */ +#define _ACMP_IF_RESETVALUE 0x00000000UL /**< Default value for ACMP_IF */ +#define _ACMP_IF_MASK 0x0000001FUL /**< Mask for ACMP_IF */ +#define ACMP_IF_RISE (0x1UL << 0) /**< Rising Edge Triggered Interrupt Flag */ +#define _ACMP_IF_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IF_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IF_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_RISE_DEFAULT (_ACMP_IF_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL (0x1UL << 1) /**< Falling Edge Triggered Interrupt Flag */ +#define _ACMP_IF_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IF_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IF_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_FALL_DEFAULT (_ACMP_IF_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY (0x1UL << 2) /**< ACMP ready Interrupt flag */ +#define _ACMP_IF_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IF_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_ACMPRDY_DEFAULT (_ACMP_IF_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT (0x1UL << 3) /**< Input conflict */ +#define _ACMP_IF_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IF_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_INPUTCONFLICT_DEFAULT (_ACMP_IF_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR (0x1UL << 4) /**< Port allocation error */ +#define _ACMP_IF_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IF */ +#define ACMP_IF_PORTALLOCERR_DEFAULT (_ACMP_IF_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IF */ + +/* Bit fields for ACMP IEN */ +#define _ACMP_IEN_RESETVALUE 0x00000000UL /**< Default value for ACMP_IEN */ +#define _ACMP_IEN_MASK 0x0000001FUL /**< Mask for ACMP_IEN */ +#define ACMP_IEN_RISE (0x1UL << 0) /**< Rising edge interrupt enable */ +#define _ACMP_IEN_RISE_SHIFT 0 /**< Shift value for ACMP_RISE */ +#define _ACMP_IEN_RISE_MASK 0x1UL /**< Bit mask for ACMP_RISE */ +#define _ACMP_IEN_RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_RISE_DEFAULT (_ACMP_IEN_RISE_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL (0x1UL << 1) /**< Falling edge interrupt enable */ +#define _ACMP_IEN_FALL_SHIFT 1 /**< Shift value for ACMP_FALL */ +#define _ACMP_IEN_FALL_MASK 0x2UL /**< Bit mask for ACMP_FALL */ +#define _ACMP_IEN_FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_FALL_DEFAULT (_ACMP_IEN_FALL_DEFAULT << 1) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY (0x1UL << 2) /**< ACMP ready interrupt enable */ +#define _ACMP_IEN_ACMPRDY_SHIFT 2 /**< Shift value for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_MASK 0x4UL /**< Bit mask for ACMP_ACMPRDY */ +#define _ACMP_IEN_ACMPRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_ACMPRDY_DEFAULT (_ACMP_IEN_ACMPRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT (0x1UL << 3) /**< Input conflict interrupt enable */ +#define _ACMP_IEN_INPUTCONFLICT_SHIFT 3 /**< Shift value for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_MASK 0x8UL /**< Bit mask for ACMP_INPUTCONFLICT */ +#define _ACMP_IEN_INPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_INPUTCONFLICT_DEFAULT (_ACMP_IEN_INPUTCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR (0x1UL << 4) /**< Port allocation error interrupt enable */ +#define _ACMP_IEN_PORTALLOCERR_SHIFT 4 /**< Shift value for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_MASK 0x10UL /**< Bit mask for ACMP_PORTALLOCERR */ +#define _ACMP_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_IEN */ +#define ACMP_IEN_PORTALLOCERR_DEFAULT (_ACMP_IEN_PORTALLOCERR_DEFAULT << 4) /**< Shifted mode DEFAULT for ACMP_IEN */ + +/* Bit fields for ACMP SYNCBUSY */ +#define _ACMP_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for ACMP_SYNCBUSY */ +#define _ACMP_SYNCBUSY_MASK 0x00000001UL /**< Mask for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL (0x1UL << 0) /**< Syncbusy for INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_SHIFT 0 /**< Shift value for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_MASK 0x1UL /**< Bit mask for ACMP_INPUTCTRL */ +#define _ACMP_SYNCBUSY_INPUTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ACMP_SYNCBUSY */ +#define ACMP_SYNCBUSY_INPUTCTRL_DEFAULT (_ACMP_SYNCBUSY_INPUTCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for ACMP_SYNCBUSY */ + +/** @} End of group EFR32MG24_ACMP_BitFields */ +/** @} End of group EFR32MG24_ACMP */ +/** @} End of group Parts */ + +#endif // EFR32MG24_ACMP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h index fc5928f..16c8c86 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_aes.h @@ -1,453 +1,453 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 AES register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_AES_H -#define EFR32MG24_AES_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_AES AES - * @{ - * @brief EFR32MG24 AES Register Declaration. - *****************************************************************************/ - -/** AES Register Declaration. */ -typedef struct { - __IOM uint32_t FETCHADDR; /**< Fetcher Address */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t FETCHLEN; /**< Fetcher Length */ - __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ - __IOM uint32_t PUSHADDR; /**< Pusher Address */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t PUSHLEN; /**< Pusher Length */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IM uint32_t IF; /**< Interrupt Flags */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt status clear */ - __IOM uint32_t CTRL; /**< Control register */ - __IOM uint32_t CMD; /**< Command register */ - __IM uint32_t STATUS; /**< Status register */ - uint32_t RESERVED4[240U]; /**< Reserved for future use */ - __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ - __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ - __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ - __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ - __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ - __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ -} AES_TypeDef; -/** @} End of group EFR32MG24_AES */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_AES - * @{ - * @defgroup EFR32MG24_AES_BitFields AES Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for AES FETCHADDR */ -#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ -#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ -#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ -#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ - -/* Bit fields for AES FETCHLEN */ -#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ -#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ -#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ -#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ - -/* Bit fields for AES FETCHTAG */ -#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ -#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ -#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ -#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ -#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ -#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ - -/* Bit fields for AES PUSHADDR */ -#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ -#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ -#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ -#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ - -/* Bit fields for AES PUSHLEN */ -#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ -#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ -#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ -#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ - -/* Bit fields for AES IEN */ -#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ -#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ -#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ -#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ -#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ -#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ -#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ -#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ - -/* Bit fields for AES IF */ -#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ -#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ -#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ -#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ -#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ -#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ -#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ -#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ - -/* Bit fields for AES IF_CLR */ -#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ -#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ -#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ -#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ -#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ -#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ - -/* Bit fields for AES CTRL */ -#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ -#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ -#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ -#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ -#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ -#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ -#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ -#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ -#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ - -/* Bit fields for AES CMD */ -#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ -#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ -#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ -#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ -#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ - -/* Bit fields for AES STATUS */ -#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ -#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ -#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ -#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ -#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ -#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ -#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ -#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ -#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ -#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ -#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ - -/* Bit fields for AES INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ - -/* Bit fields for AES BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ -#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ - -/* Bit fields for AES BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ -#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ - -/* Bit fields for AES BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ -#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ - -/* Bit fields for AES BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ - -/* Bit fields for AES BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ -#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ - -/** @} End of group EFR32MG24_AES_BitFields */ -/** @} End of group EFR32MG24_AES */ -/** @} End of group Parts */ - -#endif // EFR32MG24_AES_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_AES_H +#define EFR32MG24_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_AES AES + * @{ + * @brief EFR32MG24 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32MG24_AES */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_AES + * @{ + * @defgroup EFR32MG24_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32MG24_AES_BitFields */ +/** @} End of group EFR32MG24_AES */ +/** @} End of group Parts */ + +#endif // EFR32MG24_AES_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h index a1259b6..88bba93 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_buram.h @@ -1,80 +1,80 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 BURAM register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_BURAM_H -#define EFR32MG24_BURAM_H -#define BURAM_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_BURAM BURAM - * @{ - * @brief EFR32MG24 BURAM Register Declaration. - *****************************************************************************/ - -/** BURAM RET Register Group Declaration. */ -typedef struct { - __IOM uint32_t REG; /**< Retention Register */ -} BURAM_RET_TypeDef; - -/** BURAM Register Declaration. */ -typedef struct { - BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ - uint32_t RESERVED0[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ - uint32_t RESERVED1[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ - uint32_t RESERVED2[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ -} BURAM_TypeDef; -/** @} End of group EFR32MG24_BURAM */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_BURAM - * @{ - * @defgroup EFR32MG24_BURAM_BitFields BURAM Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for BURAM RET_REG */ -#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ -#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ -#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ -#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ - -/** @} End of group EFR32MG24_BURAM_BitFields */ -/** @} End of group EFR32MG24_BURAM */ -/** @} End of group Parts */ - -#endif // EFR32MG24_BURAM_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_BURAM_H +#define EFR32MG24_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_BURAM BURAM + * @{ + * @brief EFR32MG24 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct { + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32MG24_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_BURAM + * @{ + * @defgroup EFR32MG24_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32MG24_BURAM_BitFields */ +/** @} End of group EFR32MG24_BURAM */ +/** @} End of group Parts */ + +#endif // EFR32MG24_BURAM_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h index 90968d4..7423bad 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_burtc.h @@ -1,332 +1,332 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 BURTC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_BURTC_H -#define EFR32MG24_BURTC_H -#define BURTC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_BURTC BURTC - * @{ - * @brief EFR32MG24 BURTC Register Declaration. - *****************************************************************************/ - -/** BURTC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t COMP; /**< Compare Value Register */ - uint32_t RESERVED0[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t COMP_SET; /**< Compare Value Register */ - uint32_t RESERVED1[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t COMP_CLR; /**< Compare Value Register */ - uint32_t RESERVED2[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t COMP_TGL; /**< Compare Value Register */ -} BURTC_TypeDef; -/** @} End of group EFR32MG24_BURTC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_BURTC - * @{ - * @defgroup EFR32MG24_BURTC_BitFields BURTC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for BURTC IPVERSION */ -#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ -#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ - -/* Bit fields for BURTC EN */ -#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ -#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ -#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ -#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ -#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ -#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ -#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ - -/* Bit fields for BURTC CFG */ -#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ -#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ -#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ -#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ - -/* Bit fields for BURTC CMD */ -#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ -#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ -#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ -#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ -#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ - -/* Bit fields for BURTC STATUS */ -#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ -#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ -#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ -#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ - -/* Bit fields for BURTC IF */ -#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ -#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ -#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ - -/* Bit fields for BURTC IEN */ -#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ -#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ -#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ - -/* Bit fields for BURTC PRECNT */ -#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ -#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ -#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ - -/* Bit fields for BURTC CNT */ -#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ -#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ -#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ -#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ - -/* Bit fields for BURTC EM4WUEN */ -#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ -#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ - -/* Bit fields for BURTC SYNCBUSY */ -#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ -#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ -#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ -#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ -#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ -#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ - -/* Bit fields for BURTC LOCK */ -#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ -#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ - -/* Bit fields for BURTC COMP */ -#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ -#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ -#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ -#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ - -/** @} End of group EFR32MG24_BURTC_BitFields */ -/** @} End of group EFR32MG24_BURTC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_BURTC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_BURTC_H +#define EFR32MG24_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_BURTC BURTC + * @{ + * @brief EFR32MG24 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32MG24_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_BURTC + * @{ + * @defgroup EFR32MG24_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ +#define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32MG24_BURTC_BitFields */ +/** @} End of group EFR32MG24_BURTC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_BURTC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h index 7c3971e..6a66949 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_cmu.h @@ -1,1121 +1,1121 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 CMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_CMU_H -#define EFR32MG24_CMU_H -#define CMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_CMU CMU - * @{ - * @brief EFR32MG24 CMU Register Declaration. - *****************************************************************************/ - -/** CMU Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED3[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL; /**< Calibration Control Register */ - __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ - uint32_t RESERVED8[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED11[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ - uint32_t RESERVED14[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED16[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ - uint32_t RESERVED17[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ - uint32_t RESERVED18[7U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ - uint32_t RESERVED19[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED20[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ - uint32_t RESERVED21[4U]; /**< Reserved for future use */ - __IOM uint32_t VDAC1CLKCTRL; /**< VDAC1 Clock Control */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED26[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED27[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ - __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ - uint32_t RESERVED28[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ - uint32_t RESERVED30[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ - uint32_t RESERVED32[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED33[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED35[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED36[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED37[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ - uint32_t RESERVED38[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ - uint32_t RESERVED39[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ - uint32_t RESERVED40[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ - uint32_t RESERVED41[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ - uint32_t RESERVED42[7U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ - uint32_t RESERVED43[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED44[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ - uint32_t RESERVED45[4U]; /**< Reserved for future use */ - __IOM uint32_t VDAC1CLKCTRL_SET; /**< VDAC1 Clock Control */ - uint32_t RESERVED46[1U]; /**< Reserved for future use */ - uint32_t RESERVED47[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED48[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED49[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED50[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED51[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ - __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ - uint32_t RESERVED52[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ - uint32_t RESERVED53[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ - uint32_t RESERVED54[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ - uint32_t RESERVED55[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ - uint32_t RESERVED56[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED57[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED58[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED59[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED60[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED61[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ - uint32_t RESERVED62[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ - uint32_t RESERVED63[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ - uint32_t RESERVED64[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ - uint32_t RESERVED65[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ - uint32_t RESERVED66[7U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ - uint32_t RESERVED67[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED68[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ - uint32_t RESERVED69[4U]; /**< Reserved for future use */ - __IOM uint32_t VDAC1CLKCTRL_CLR; /**< VDAC1 Clock Control */ - uint32_t RESERVED70[1U]; /**< Reserved for future use */ - uint32_t RESERVED71[857U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED72[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED73[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED74[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED75[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ - __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ - uint32_t RESERVED76[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ - uint32_t RESERVED77[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ - uint32_t RESERVED78[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ - uint32_t RESERVED79[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ - uint32_t RESERVED80[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED81[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ - uint32_t RESERVED82[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ - uint32_t RESERVED83[5U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED84[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED85[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ - uint32_t RESERVED86[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED87[1U]; /**< Reserved for future use */ - __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ - uint32_t RESERVED88[5U]; /**< Reserved for future use */ - __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ - uint32_t RESERVED89[7U]; /**< Reserved for future use */ - __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ - uint32_t RESERVED90[7U]; /**< Reserved for future use */ - __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ - uint32_t RESERVED91[3U]; /**< Reserved for future use */ - __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ - uint32_t RESERVED92[3U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ - uint32_t RESERVED93[4U]; /**< Reserved for future use */ - __IOM uint32_t VDAC1CLKCTRL_TGL; /**< VDAC1 Clock Control */ - uint32_t RESERVED94[1U]; /**< Reserved for future use */ -} CMU_TypeDef; -/** @} End of group EFR32MG24_CMU */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_CMU - * @{ - * @defgroup EFR32MG24_CMU_BitFields CMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for CMU IPVERSION */ -#define _CMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for CMU_IPVERSION */ -#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_IPVERSION */ -#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ - -/* Bit fields for CMU STATUS */ -#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ -#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ -#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ -#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ -#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ -#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ - -/* Bit fields for CMU LOCK */ -#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ -#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ - -/* Bit fields for CMU WDOGLOCK */ -#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ - -/* Bit fields for CMU IF */ -#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ -#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ -#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ -#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ -#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ - -/* Bit fields for CMU IEN */ -#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ -#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ -#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ -#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ -#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ - -/* Bit fields for CMU CALCMD */ -#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ -#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ -#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ -#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ - -/* Bit fields for CMU CALCTRL */ -#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ -#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ -#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ -#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ -#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ -#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ - -/* Bit fields for CMU CALCNT */ -#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ -#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ - -/* Bit fields for CMU CLKEN0 */ -#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ -#define _CMU_CLKEN0_MASK 0xFDFFFFFFUL /**< Mask for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ -#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ -#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ -#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ -#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ -#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ - -/* Bit fields for CMU CLKEN1 */ -#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ -#define _CMU_CLKEN1_MASK 0x7EFFEFFFUL /**< Mask for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ -#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ -#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ -#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ -#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ -#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ -#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ -#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ -#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ -#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ -#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ -#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ -#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ -#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ -#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ -#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ -#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ -#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ -#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ -#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ -#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ -#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ -#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ -#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ -#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ -#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ -#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC1 (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_VDAC1_SHIFT 29 /**< Shift value for CMU_VDAC1 */ -#define _CMU_CLKEN1_VDAC1_MASK 0x20000000UL /**< Bit mask for CMU_VDAC1 */ -#define _CMU_CLKEN1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_VDAC1_DEFAULT (_CMU_CLKEN1_VDAC1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MVP (0x1UL << 30) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MVP_SHIFT 30 /**< Shift value for CMU_MVP */ -#define _CMU_CLKEN1_MVP_MASK 0x40000000UL /**< Bit mask for CMU_MVP */ -#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ - -/* Bit fields for CMU SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ - -/* Bit fields for CMU TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ -#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ - -/* Bit fields for CMU EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ -#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ - -/* Bit fields for CMU DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ -#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ - -/* Bit fields for CMU EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ - -/* Bit fields for CMU EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ -#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ -#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ - -/* Bit fields for CMU EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ - -/* Bit fields for CMU EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ - -/* Bit fields for CMU IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ -#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ - -/* Bit fields for CMU WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ - -/* Bit fields for CMU WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ - -/* Bit fields for CMU EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ - -/* Bit fields for CMU SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ - -/* Bit fields for CMU VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ -#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ -#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ -#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ - -/* Bit fields for CMU PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ -#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ -#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ -#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ - -/* Bit fields for CMU RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ -#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ -#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ - -/* Bit fields for CMU VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC1CLKCTRL */ -#define _CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ -#define CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC1CLKCTRL */ -#define CMU_VDAC1CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC1CLKCTRL */ -#define CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC1CLKCTRL*/ -#define CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC1CLKCTRL*/ -#define CMU_VDAC1CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC1CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC1CLKCTRL */ -#define CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ - -/** @} End of group EFR32MG24_CMU_BitFields */ -/** @} End of group EFR32MG24_CMU */ -/** @} End of group Parts */ - -#endif // EFR32MG24_CMU_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_CMU_H +#define EFR32MG24_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_CMU CMU + * @{ + * @brief EFR32MG24 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED11[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED14[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED16[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL; /**< EUSART0 Clock Control */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL; /**< System RTC0 Clock Control */ + uint32_t RESERVED18[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL; /**< VDAC0 Clock Control */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL; /**< VDAC1 Clock Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED27[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED28[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED30[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED32[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED33[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_SET; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED35[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED37[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED38[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_SET; /**< Watchdog1 Clock Control */ + uint32_t RESERVED40[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_SET; /**< EUSART0 Clock Control */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_SET; /**< System RTC0 Clock Control */ + uint32_t RESERVED42[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_SET; /**< VDAC0 Clock Control */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_SET; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_SET; /**< VDAC1 Clock Control */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED49[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED50[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED51[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED52[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED54[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED55[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED56[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED57[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_CLR; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED59[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED60[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED61[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED62[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED63[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_CLR; /**< Watchdog1 Clock Control */ + uint32_t RESERVED64[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_CLR; /**< EUSART0 Clock Control */ + uint32_t RESERVED65[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_CLR; /**< System RTC0 Clock Control */ + uint32_t RESERVED66[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_CLR; /**< VDAC0 Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_CLR; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED68[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED69[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_CLR; /**< VDAC1 Clock Control */ + uint32_t RESERVED70[1U]; /**< Reserved for future use */ + uint32_t RESERVED71[857U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED72[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED73[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED74[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED75[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED76[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED77[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED78[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED79[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED80[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED81[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + uint32_t RESERVED82[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPCCLKCTRL_TGL; /**< EM01 Peripheral Group C Clock Control */ + uint32_t RESERVED83[5U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED84[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED85[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED86[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED87[1U]; /**< Reserved for future use */ + __IOM uint32_t WDOG1CLKCTRL_TGL; /**< Watchdog1 Clock Control */ + uint32_t RESERVED88[5U]; /**< Reserved for future use */ + __IOM uint32_t EUSART0CLKCTRL_TGL; /**< EUSART0 Clock Control */ + uint32_t RESERVED89[7U]; /**< Reserved for future use */ + __IOM uint32_t SYSRTC0CLKCTRL_TGL; /**< System RTC0 Clock Control */ + uint32_t RESERVED90[7U]; /**< Reserved for future use */ + __IOM uint32_t VDAC0CLKCTRL_TGL; /**< VDAC0 Clock Control */ + uint32_t RESERVED91[3U]; /**< Reserved for future use */ + __IOM uint32_t PCNT0CLKCTRL_TGL; /**< Pulse counter 0 Clock Control */ + uint32_t RESERVED92[3U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ + uint32_t RESERVED93[4U]; /**< Reserved for future use */ + __IOM uint32_t VDAC1CLKCTRL_TGL; /**< VDAC1 Clock Control */ + uint32_t RESERVED94[1U]; /**< Reserved for future use */ +} CMU_TypeDef; +/** @} End of group EFR32MG24_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_CMU + * @{ + * @defgroup EFR32MG24_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0038001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCOEM23 0x00000005UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCOEM23 (_CMU_CALCTRL_UPSEL_HFRCOEM23 << 24) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCOEM23 0x00000006UL /**< Mode HFRCOEM23 for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCOEM23 (_CMU_CALCTRL_DOWNSEL_HFRCOEM23 << 28) /**< Shifted mode HFRCOEM23 for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFDFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER4_SHIFT 8 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_MASK 0x100UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER4_DEFAULT (_CMU_CLKEN0_TIMER4_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 9 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x200UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCOEM23_SHIFT 19 /**< Shift value for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_MASK 0x80000UL /**< Bit mask for CMU_HFRCOEM23 */ +#define _CMU_CLKEN0_HFRCOEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCOEM23_DEFAULT (_CMU_CLKEN0_HFRCOEM23_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 20 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x100000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 21 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x200000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 22 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x400000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 23 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x800000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 24 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x1000000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0 (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSRTC0_SHIFT 30 /**< Shift value for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_MASK 0x40000000UL /**< Bit mask for CMU_SYSRTC0 */ +#define _CMU_CLKEN0_SYSRTC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSRTC0_DEFAULT (_CMU_CLKEN0_SYSRTC0_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x7EFFEFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RFSCRATCHPAD */ +#define _CMU_CLKEN1_RFSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RFSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_HOSTMAILBOX_SHIFT 8 /**< Shift value for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_MASK 0x100UL /**< Bit mask for CMU_HOSTMAILBOX */ +#define _CMU_CLKEN1_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_HOSTMAILBOX_DEFAULT (_CMU_CLKEN1_HOSTMAILBOX_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFMAILBOX_SHIFT 9 /**< Shift value for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_MASK 0x200UL /**< Bit mask for CMU_RFMAILBOX */ +#define _CMU_CLKEN1_RFMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFMAILBOX_DEFAULT (_CMU_CLKEN1_RFMAILBOX_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SEMAILBOXHOST_SHIFT 10 /**< Shift value for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_MASK 0x400UL /**< Bit mask for CMU_SEMAILBOXHOST */ +#define _CMU_CLKEN1_SEMAILBOXHOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SEMAILBOXHOST_DEFAULT (_CMU_CLKEN1_SEMAILBOXHOST_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_KEYSCAN_SHIFT 13 /**< Shift value for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_MASK 0x2000UL /**< Bit mask for CMU_KEYSCAN */ +#define _CMU_CLKEN1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_KEYSCAN_DEFAULT (_CMU_CLKEN1_KEYSCAN_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 14 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x4000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 15 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x8000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 16 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x10000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_WDOG1_SHIFT 17 /**< Shift value for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_MASK 0x20000UL /**< Bit mask for CMU_WDOG1 */ +#define _CMU_CLKEN1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_WDOG1_DEFAULT (_CMU_CLKEN1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP0_SHIFT 18 /**< Shift value for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_MASK 0x40000UL /**< Bit mask for CMU_ACMP0 */ +#define _CMU_CLKEN1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP0_DEFAULT (_CMU_CLKEN1_ACMP0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ACMP1_SHIFT 19 /**< Shift value for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_MASK 0x80000UL /**< Bit mask for CMU_ACMP1 */ +#define _CMU_CLKEN1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ACMP1_DEFAULT (_CMU_CLKEN1_ACMP1_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0 (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC0_SHIFT 20 /**< Shift value for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_MASK 0x100000UL /**< Bit mask for CMU_VDAC0 */ +#define _CMU_CLKEN1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC0_DEFAULT (_CMU_CLKEN1_VDAC0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0 (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PCNT0_SHIFT 21 /**< Shift value for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_MASK 0x200000UL /**< Bit mask for CMU_PCNT0 */ +#define _CMU_CLKEN1_PCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PCNT0_DEFAULT (_CMU_CLKEN1_PCNT0_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0 (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART0_SHIFT 22 /**< Shift value for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_MASK 0x400000UL /**< Bit mask for CMU_EUSART0 */ +#define _CMU_CLKEN1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART0_DEFAULT (_CMU_CLKEN1_EUSART0_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1 (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_EUSART1_SHIFT 23 /**< Shift value for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_MASK 0x800000UL /**< Bit mask for CMU_EUSART1 */ +#define _CMU_CLKEN1_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_EUSART1_DEFAULT (_CMU_CLKEN1_EUSART1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0 (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA0_SHIFT 25 /**< Shift value for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_MASK 0x2000000UL /**< Bit mask for CMU_RFECA0 */ +#define _CMU_CLKEN1_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA0_DEFAULT (_CMU_CLKEN1_RFECA0_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1 (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFECA1_SHIFT 26 /**< Shift value for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_MASK 0x4000000UL /**< Bit mask for CMU_RFECA1 */ +#define _CMU_CLKEN1_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFECA1_DEFAULT (_CMU_CLKEN1_RFECA1_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_DMEM_SHIFT 27 /**< Shift value for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_MASK 0x8000000UL /**< Bit mask for CMU_DMEM */ +#define _CMU_CLKEN1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_DMEM_DEFAULT (_CMU_CLKEN1_DMEM_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ECAIFADC_SHIFT 28 /**< Shift value for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_MASK 0x10000000UL /**< Bit mask for CMU_ECAIFADC */ +#define _CMU_CLKEN1_ECAIFADC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ECAIFADC_DEFAULT (_CMU_CLKEN1_ECAIFADC_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1 (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_VDAC1_SHIFT 29 /**< Shift value for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_MASK 0x20000000UL /**< Bit mask for CMU_VDAC1 */ +#define _CMU_CLKEN1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_VDAC1_DEFAULT (_CMU_CLKEN1_VDAC1_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MVP_SHIFT 30 /**< Shift value for CMU_MVP */ +#define _CMU_CLKEN1_MVP_MASK 0x40000000UL /**< Bit mask for CMU_MVP */ +#define _CMU_CLKEN1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MVP_DEFAULT (_CMU_CLKEN1_MVP_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000033UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_DISABLE 0x00000000UL /**< Mode DISABLE for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_SYSCLK 0x00000001UL /**< Mode SYSCLK for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT 0x00000003UL /**< Mode HFRCODPLLRT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DEFAULT (_CMU_TRACECLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_DISABLE (_CMU_TRACECLKCTRL_CLKSEL_DISABLE << 0) /**< Shifted mode DISABLE for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_SYSCLK (_CMU_TRACECLKCTRL_CLKSEL_SYSCLK << 0) /**< Shifted mode SYSCLK for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 (_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_TRACECLKCTRL*/ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV3 0x00000002UL /**< Mode DIV3 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV3 (_CMU_TRACECLKCTRL_PRESC_DIV3 << 4) /**< Shifted mode DIV3 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCOEM23 << 8) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 0x00000009UL /**< Mode HFRCOEM23 for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCOEM23 << 16) /**< Shifted mode HFRCOEM23 for CMU_EXPORTCLKCTRL*/ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL */ +#define _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPCCLKCTRL */ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPCCLKCTRL*/ +#define CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPCCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 0x00000003UL /**< Mode HFRCOEM23 for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 (_CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_LFXO (_CMU_WDOG1CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG1CLKCTRL*/ + +/* Bit fields for CMU EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK 0x00000001UL /**< Mode EM01GRPCCLK for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 0x00000002UL /**< Mode HFRCOEM23 for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_EUSART0CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUSART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK (_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK << 0) /**< Shifted mode EM01GRPCCLK for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_EUSART0CLKCTRL*/ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFRCO (_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_LFXO (_CMU_EUSART0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EUSART0CLKCTRL */ + +/* Bit fields for CMU SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT (_CMU_SYSRTC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO (_CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO (_CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_SYSRTC0CLKCTRL */ + +/* Bit fields for CMU VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC0CLKCTRL */ +#define _CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC0CLKCTRL*/ +#define CMU_VDAC0CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC0CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC0CLKCTRL */ +#define CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC0CLKCTRL */ + +/* Bit fields for CMU PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000001UL /**< Mode EM23GRPACLK for CMU_PCNT0CLKCTRL */ +#define _CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 0x00000002UL /**< Mode PCNTS0 for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT (_CMU_PCNT0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_DISABLED (_CMU_PCNT0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_PCNT0CLKCTRL */ +#define CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_PCNT0CLKCTRL*/ +#define CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 (_CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0 << 0) /**< Shifted mode PCNTS0 for CMU_PCNT0CLKCTRL */ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000003UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/* Bit fields for CMU VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_VDAC1CLKCTRL */ +#define _CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 0x00000004UL /**< Mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT (_CMU_VDAC1CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_DISABLED (_CMU_VDAC1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_VDAC1CLKCTRL*/ +#define CMU_VDAC1CLKCTRL_CLKSEL_FSRCO (_CMU_VDAC1CLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_VDAC1CLKCTRL */ +#define CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 (_CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23 << 0) /**< Shifted mode HFRCOEM23 for CMU_VDAC1CLKCTRL */ + +/** @} End of group EFR32MG24_CMU_BitFields */ +/** @} End of group EFR32MG24_CMU */ +/** @} End of group Parts */ + +#endif // EFR32MG24_CMU_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h index 6ffc79b..e0a4bfc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dcdc.h @@ -1,446 +1,446 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 DCDC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_DCDC_H -#define EFR32MG24_DCDC_H -#define DCDC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_DCDC DCDC - * @{ - * @brief EFR32MG24 DCDC Register Declaration. - *****************************************************************************/ - -/** DCDC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t CTRL; /**< Control */ - __IOM uint32_t EM01CTRL0; /**< EM01 Control */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t EM23CTRL0; /**< EM23 Control */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status Register */ - __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ - uint32_t RESERVED3[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - uint32_t RESERVED6[7U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[7U]; /**< Reserved for future use */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[987U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t CTRL_SET; /**< Control */ - __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ - uint32_t RESERVED12[3U]; /**< Reserved for future use */ - __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ - uint32_t RESERVED14[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ - uint32_t RESERVED15[2U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[7U]; /**< Reserved for future use */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[7U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[987U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t CTRL_CLR; /**< Control */ - __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ - uint32_t RESERVED23[3U]; /**< Reserved for future use */ - __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ - uint32_t RESERVED26[2U]; /**< Reserved for future use */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[7U]; /**< Reserved for future use */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - uint32_t RESERVED30[7U]; /**< Reserved for future use */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - uint32_t RESERVED32[987U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t CTRL_TGL; /**< Control */ - __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ - uint32_t RESERVED33[1U]; /**< Reserved for future use */ - __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ - uint32_t RESERVED34[3U]; /**< Reserved for future use */ - __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ - uint32_t RESERVED36[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ - uint32_t RESERVED37[2U]; /**< Reserved for future use */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - uint32_t RESERVED39[7U]; /**< Reserved for future use */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - uint32_t RESERVED41[7U]; /**< Reserved for future use */ - uint32_t RESERVED42[1U]; /**< Reserved for future use */ -} DCDC_TypeDef; -/** @} End of group EFR32MG24_DCDC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_DCDC - * @{ - * @defgroup EFR32MG24_DCDC_BitFields DCDC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DCDC IPVERSION */ -#define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */ -#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ - -/* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ - -/* Bit fields for DCDC EM01CTRL0 */ -#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ -#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ -#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ -#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ -#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ -#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ -#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ - -/* Bit fields for DCDC EM23CTRL0 */ -#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ -#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ -#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ -#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ -#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ -#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ -#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ - -/* Bit fields for DCDC PFMXCTRL */ -#define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ -#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ -#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ -#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ -#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ - -/* Bit fields for DCDC IF */ -#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ -#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ -#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ -#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ -#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ -#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ -#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ -#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ -#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ -#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ -#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ -#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ -#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ -#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ -#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ -#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ -#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ -#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ -#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ -#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ -#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ -#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ -#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ -#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ - -/* Bit fields for DCDC IEN */ -#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ -#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ -#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ -#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ -#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ -#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ -#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ -#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ -#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ -#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ -#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ -#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ -#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ -#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ -#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ -#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ -#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ -#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ -#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ -#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ -#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ -#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ -#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ -#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ - -/* Bit fields for DCDC STATUS */ -#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ -#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ -#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ -#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ -#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ -#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ -#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ -#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ -#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ -#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ -#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ -#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ -#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ -#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ -#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ - -/* Bit fields for DCDC SYNCBUSY */ -#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ -#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ -#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ -#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ -#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ -#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ -#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ -#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ -#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ -#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ -#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ -#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ -#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ -#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ -#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ -#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ -#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ -#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ - -/* Bit fields for DCDC LOCK */ -#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ -#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ -#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ -#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ -#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ -#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ -#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ -#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ - -/* Bit fields for DCDC LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ -#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ -#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ -#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ - -/** @} End of group EFR32MG24_DCDC_BitFields */ -/** @} End of group EFR32MG24_DCDC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_DCDC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DCDC_H +#define EFR32MG24_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DCDC DCDC + * @{ + * @brief EFR32MG24 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL; /**< PFMX Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_SET; /**< PFMX Control Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[7U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[7U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED23[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_CLR; /**< PFMX Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[7U]; /**< Reserved for future use */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + uint32_t RESERVED30[7U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + uint32_t RESERVED32[987U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED34[3U]; /**< Reserved for future use */ + __IOM uint32_t PFMXCTRL_TGL; /**< PFMX Control Register */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[7U]; /**< Reserved for future use */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[7U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32MG24_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DCDC + * @{ + * @defgroup EFR32MG24_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000100UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x800001F1UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x1F0UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000010UL /**< Mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC PFMXCTRL */ +#define _DCDC_PFMXCTRL_RESETVALUE 0x00000C0CUL /**< Default value for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_MASK 0x00001F0FUL /**< Mask for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_PFMXCTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD50MA 0x00000003UL /**< Mode LOAD50MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD65MA 0x00000004UL /**< Mode LOAD65MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD73MA 0x00000005UL /**< Mode LOAD73MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD80MA 0x00000006UL /**< Mode LOAD80MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD86MA 0x00000007UL /**< Mode LOAD86MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD93MA 0x00000008UL /**< Mode LOAD93MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD100MA 0x00000009UL /**< Mode LOAD100MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD106MA 0x0000000AUL /**< Mode LOAD106MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD113MA 0x0000000BUL /**< Mode LOAD113MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKVAL_LOAD120MA 0x0000000CUL /**< Mode LOAD120MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_DEFAULT (_DCDC_PFMXCTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD50MA (_DCDC_PFMXCTRL_IPKVAL_LOAD50MA << 0) /**< Shifted mode LOAD50MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD65MA (_DCDC_PFMXCTRL_IPKVAL_LOAD65MA << 0) /**< Shifted mode LOAD65MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD73MA (_DCDC_PFMXCTRL_IPKVAL_LOAD73MA << 0) /**< Shifted mode LOAD73MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD80MA (_DCDC_PFMXCTRL_IPKVAL_LOAD80MA << 0) /**< Shifted mode LOAD80MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD86MA (_DCDC_PFMXCTRL_IPKVAL_LOAD86MA << 0) /**< Shifted mode LOAD86MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD93MA (_DCDC_PFMXCTRL_IPKVAL_LOAD93MA << 0) /**< Shifted mode LOAD93MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD100MA (_DCDC_PFMXCTRL_IPKVAL_LOAD100MA << 0) /**< Shifted mode LOAD100MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD106MA (_DCDC_PFMXCTRL_IPKVAL_LOAD106MA << 0) /**< Shifted mode LOAD106MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD113MA (_DCDC_PFMXCTRL_IPKVAL_LOAD113MA << 0) /**< Shifted mode LOAD113MA for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKVAL_LOAD120MA (_DCDC_PFMXCTRL_IPKVAL_LOAD120MA << 0) /**< Shifted mode LOAD120MA for DCDC_PFMXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT 8 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK 0x1F00UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_PFMXCTRL */ +#define DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_PFMXCTRL_IPKTMAXCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_PFMXCTRL */ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000003FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE (0x1UL << 9) /**< Entered PFMX mode */ +#define _DCDC_IF_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IF_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_PFMXMODE_DEFAULT (_DCDC_IF_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000003FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGIN below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGIN above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE (0x1UL << 9) /**< PFMX Mode Interrupt Enable */ +#define _DCDC_IEN_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_IEN_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_PFMXMODE_DEFAULT (_DCDC_IEN_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000071FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE (0x1UL << 9) /**< DCDC in PFMX mode */ +#define _DCDC_STATUS_PFMXMODE_SHIFT 9 /**< Shift value for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_MASK 0x200UL /**< Bit mask for DCDC_PFMXMODE */ +#define _DCDC_STATUS_PFMXMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_PFMXMODE_DEFAULT (_DCDC_STATUS_PFMXMODE_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC SYNCBUSY */ +#define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ +#define _DCDC_SYNCBUSY_MASK 0x000000FFUL /**< Mask for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for DCDC_CTRL */ +#define _DCDC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_CTRL_DEFAULT (_DCDC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0 (0x1UL << 1) /**< EM01CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM01CTRL0_SHIFT 1 /**< Shift value for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_MASK 0x2UL /**< Bit mask for DCDC_EM01CTRL0 */ +#define _DCDC_SYNCBUSY_EM01CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL0_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1 (0x1UL << 2) /**< EM01CTRL1 Sync Bust Status */ +#define _DCDC_SYNCBUSY_EM01CTRL1_SHIFT 2 /**< Shift value for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_MASK 0x4UL /**< Bit mask for DCDC_EM01CTRL1 */ +#define _DCDC_SYNCBUSY_EM01CTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM01CTRL1_DEFAULT (_DCDC_SYNCBUSY_EM01CTRL1_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0 (0x1UL << 3) /**< EM23CTRL0 Sync Busy Status */ +#define _DCDC_SYNCBUSY_EM23CTRL0_SHIFT 3 /**< Shift value for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_MASK 0x8UL /**< Bit mask for DCDC_EM23CTRL0 */ +#define _DCDC_SYNCBUSY_EM23CTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_EM23CTRL0_DEFAULT (_DCDC_SYNCBUSY_EM23CTRL0_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL (0x1UL << 7) /**< PFMXCTRL Sync Busy Status */ +#define _DCDC_SYNCBUSY_PFMXCTRL_SHIFT 7 /**< Shift value for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_MASK 0x80UL /**< Bit mask for DCDC_PFMXCTRL */ +#define _DCDC_SYNCBUSY_PFMXCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ +#define DCDC_SYNCBUSY_PFMXCTRL_DEFAULT (_DCDC_SYNCBUSY_PFMXCTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32MG24_DCDC_BitFields */ +/** @} End of group EFR32MG24_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_DCDC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h index 21aa898..1e0bb94 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_devinfo.h @@ -1,976 +1,976 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 DEVINFO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_DEVINFO_H -#define EFR32MG24_DEVINFO_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_DEVINFO DEVINFO - * @{ - * @brief EFR32MG24 DEVINFO Register Declaration. - *****************************************************************************/ - -/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ -typedef struct { - __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ -} DEVINFO_HFRCODPLLCAL_TypeDef; - -/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ -typedef struct { - __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */ -} DEVINFO_HFRCOEM23CAL_TypeDef; - -/** DEVINFO HFRCOSECAL Register Group Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} DEVINFO_HFRCOSECAL_TypeDef; - -/** DEVINFO Register Declaration. */ -typedef struct { - __IM uint32_t INFO; /**< DI Information */ - __IM uint32_t PART; /**< Part Info */ - __IM uint32_t MEMINFO; /**< Memory Info */ - __IM uint32_t MSIZE; /**< Memory Size */ - __IM uint32_t PKGINFO; /**< Misc Device Info */ - __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ - __IM uint32_t SWFIX; /**< SW Fix Register */ - __IM uint32_t SWCAPA0; /**< Software Restriction */ - __IM uint32_t SWCAPA1; /**< Software Restriction */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t EXTINFO; /**< External Component Info */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IM uint32_t EUI48L; /**< EUI 48 Low */ - __IM uint32_t EUI48H; /**< EUI 48 High */ - __IM uint32_t EUI64L; /**< EUI64 Low */ - __IM uint32_t EUI64H; /**< EUI64 High */ - __IM uint32_t CALTEMP; /**< Calibration temperature */ - __IM uint32_t EMUTEMP; /**< EMU Temp */ - DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ - DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ - DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ - __IM uint32_t MODULENAME0; /**< Module Name Information */ - __IM uint32_t MODULENAME1; /**< Module Name Information */ - __IM uint32_t MODULENAME2; /**< Module Name Information */ - __IM uint32_t MODULENAME3; /**< Module Name Information */ - __IM uint32_t MODULENAME4; /**< Module Name Information */ - __IM uint32_t MODULENAME5; /**< Module Name Information */ - __IM uint32_t MODULENAME6; /**< Module Name Information */ - __IM uint32_t MODULEINFO; /**< Module Information */ - __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ - uint32_t RESERVED3[11U]; /**< Reserved for future use */ - __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ - __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ - __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ - __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ - uint32_t RESERVED4[24U]; /**< Reserved for future use */ - __IM uint32_t LEGACY; /**< Legacy Device Info */ - uint32_t RESERVED5[23U]; /**< Reserved for future use */ - __IM uint32_t RTHERM; /**< Thermistor Calibration */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t FENOTCHCAL; /**< FENOTCH Calibration */ - uint32_t RESERVED7[78U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ -} DEVINFO_TypeDef; -/** @} End of group EFR32MG24_DEVINFO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_DEVINFO - * @{ - * @defgroup EFR32MG24_DEVINFO_BitFields DEVINFO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DEVINFO INFO */ -#define _DEVINFO_INFO_RESETVALUE 0x0B000000UL /**< Default value for DEVINFO_INFO */ -#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ -#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ -#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ -#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ -#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ -#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ -#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ -#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ -#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ -#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ - -/* Bit fields for DEVINFO PART */ -#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ -#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ -#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ -#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ -#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ -#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ -#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ -#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ -#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ - -/* Bit fields for DEVINFO MEMINFO */ -#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ -#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ -#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ - -/* Bit fields for DEVINFO MSIZE */ -#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ -#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ -#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ -#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ -#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ -#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ -#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ - -/* Bit fields for DEVINFO PKGINFO */ -#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ -#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ -#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ -#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ -#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ -#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ -#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ - -/* Bit fields for DEVINFO CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ -#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ - -/* Bit fields for DEVINFO SWFIX */ -#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ -#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ -#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ -#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ -#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ -#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ - -/* Bit fields for DEVINFO SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ -#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ -#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ -#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ -#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ -#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ -#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ -#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ -#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ -#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ -#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ -#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ -#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */ -#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */ -#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */ - -/* Bit fields for DEVINFO SWCAPA1 */ -#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ -#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ -#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ -#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ -#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ -#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ -#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ -#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ -#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ -#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ -#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */ -#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */ -#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */ -#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_FENOTCH (0x1UL << 4) /**< FENOTCH */ -#define _DEVINFO_SWCAPA1_FENOTCH_SHIFT 4 /**< Shift value for DEVINFO_FENOTCH */ -#define _DEVINFO_SWCAPA1_FENOTCH_MASK 0x10UL /**< Bit mask for DEVINFO_FENOTCH */ -#define _DEVINFO_SWCAPA1_FENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_FENOTCH_DEFAULT (_DEVINFO_SWCAPA1_FENOTCH_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ - -/* Bit fields for DEVINFO EXTINFO */ -#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ -#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ -#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ -#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ -#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ -#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ -#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ - -/* Bit fields for DEVINFO EUI48L */ -#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ -#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ -#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ -#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ -#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ -#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ -#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ - -/* Bit fields for DEVINFO EUI48H */ -#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ -#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ -#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ -#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ -#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ -#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ -#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ - -/* Bit fields for DEVINFO EUI64L */ -#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ -#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ -#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ -#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ -#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ -#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ - -/* Bit fields for DEVINFO EUI64H */ -#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ -#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ -#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ -#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ -#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ -#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ -#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ - -/* Bit fields for DEVINFO CALTEMP */ -#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ -#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ -#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ -#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ -#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ -#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ - -/* Bit fields for DEVINFO EMUTEMP */ -#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ -#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ -#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ - -/* Bit fields for DEVINFO HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ - -/* Bit fields for DEVINFO HFRCOEM23CAL */ -#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */ -#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */ -#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ -#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ -#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */ -#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ -#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ -#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ - -/* Bit fields for DEVINFO MODULENAME0 */ -#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ -#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ -#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ -#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ -#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ -#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ -#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ -#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ - -/* Bit fields for DEVINFO MODULENAME1 */ -#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ -#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ -#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ -#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ -#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ -#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ -#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ -#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ - -/* Bit fields for DEVINFO MODULENAME2 */ -#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ -#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ -#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ -#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ -#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ -#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ -#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ -#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ - -/* Bit fields for DEVINFO MODULENAME3 */ -#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ -#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ -#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ -#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ -#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ -#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ -#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ -#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ - -/* Bit fields for DEVINFO MODULENAME4 */ -#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ -#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ -#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ -#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ -#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ -#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ -#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ -#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ - -/* Bit fields for DEVINFO MODULENAME5 */ -#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ -#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ -#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ -#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ -#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ -#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ -#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ -#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ - -/* Bit fields for DEVINFO MODULENAME6 */ -#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ -#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ -#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ -#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ -#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ -#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ -#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ -#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ - -/* Bit fields for DEVINFO MODULEINFO */ -#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ -#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ -#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ -#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ -#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ -#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ -#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ -#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ -#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ -#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ -#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ -#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ -#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ -#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ -#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ -#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ -#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ -#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ -#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ -#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ -#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ -#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ -#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ - -/* Bit fields for DEVINFO MODXOCAL */ -#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ - -/* Bit fields for DEVINFO IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ - -/* Bit fields for DEVINFO IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ - -/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ -#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ -#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ -#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ - -/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ -#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ - -/* Bit fields for DEVINFO LEGACY */ -#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ - -/* Bit fields for DEVINFO RTHERM */ -#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ -#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ - -/* Bit fields for DEVINFO FENOTCHCAL */ -#define _DEVINFO_FENOTCHCAL_RESETVALUE 0x000000FFUL /**< Default value for DEVINFO_FENOTCHCAL */ -#define _DEVINFO_FENOTCHCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_FENOTCHCAL */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_SHIFT 0 /**< Shift value for DEVINFO_FENOTCHCAPCRSE */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_MASK 0xFUL /**< Bit mask for DEVINFO_FENOTCHCAPCRSE */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ -#define DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_SHIFT 4 /**< Shift value for DEVINFO_FENOTCHCAPFINE */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_MASK 0xF0UL /**< Bit mask for DEVINFO_FENOTCHCAPFINE */ -#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ -#define DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ - -/** @} End of group EFR32MG24_DEVINFO_BitFields */ -/** @} End of group EFR32MG24_DEVINFO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_DEVINFO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DEVINFO_H +#define EFR32MG24_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DEVINFO DEVINFO + * @{ + * @brief EFR32MG24 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct { + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct { + __IM uint32_t HFRCOEM23CAL; /**< HFRCOEM23 Calibration */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct { + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature */ + __IM uint32_t EMUTEMP; /**< EMU Temp */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t FENOTCHCAL; /**< FENOTCH Calibration */ + uint32_t RESERVED7[78U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32MG24_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DEVINFO + * @{ + * @defgroup EFR32MG24_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x0B000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x07333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_SHIFT 24 /**< Shift value for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_MASK 0x7000000UL /**< Bit mask for DEVINFO_ZWAVE */ +#define _DEVINFO_SWCAPA0_ZWAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZWAVE_LEVEL4 0x00000004UL /**< Mode LEVEL4 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_DEFAULT (_DEVINFO_SWCAPA0_ZWAVE_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL0 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL0 << 24) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL1 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL1 << 24) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL2 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL2 << 24) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL3 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL3 << 24) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZWAVE_LEVEL4 (_DEVINFO_SWCAPA0_ZWAVE_LEVEL4 << 24) /**< Shifted mode LEVEL4 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x0000001FUL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT (0x1UL << 3) /**< XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_SHIFT 3 /**< Shift value for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_MASK 0x8UL /**< Bit mask for DEVINFO_XOUT */ +#define _DEVINFO_SWCAPA1_XOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_XOUT_DEFAULT (_DEVINFO_SWCAPA1_XOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH (0x1UL << 4) /**< FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_SHIFT 4 /**< Shift value for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_MASK 0x10UL /**< Bit mask for DEVINFO_FENOTCH */ +#define _DEVINFO_SWCAPA1_FENOTCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_FENOTCH_DEFAULT (_DEVINFO_SWCAPA1_FENOTCH_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCOEM23CAL */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT (_DEVINFO_HFRCOEM23CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define DEVINFO_HFRCOEM23CAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT (_DEVINFO_HFRCOEM23CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCOEM23CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT (_DEVINFO_HFRCOEM23CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT (_DEVINFO_HFRCOEM23CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCOEM23CAL */ +#define DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT (_DEVINFO_HFRCOEM23CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCOEM23CAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/* Bit fields for DEVINFO FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_RESETVALUE 0x000000FFUL /**< Default value for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_SHIFT 0 /**< Shift value for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_MASK 0xFUL /**< Bit mask for DEVINFO_FENOTCHCAPCRSE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPCRSE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_SHIFT 4 /**< Shift value for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_MASK 0xF0UL /**< Bit mask for DEVINFO_FENOTCHCAPFINE */ +#define _DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT 0x0000000FUL /**< Mode DEFAULT for DEVINFO_FENOTCHCAL */ +#define DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT (_DEVINFO_FENOTCHCAL_FENOTCHCAPFINE_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_FENOTCHCAL */ + +/** @} End of group EFR32MG24_DEVINFO_BitFields */ +/** @} End of group EFR32MG24_DEVINFO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_DEVINFO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h index c7f5d15..1c3faf1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dma_descriptor.h @@ -1,59 +1,59 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 DMA descriptor bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_DMA_DESCRIPTOR_H -#define EFR32MG24_DMA_DESCRIPTOR_H - -#if defined(__ICCARM__) -#pragma system_include /* Treat file as system include file. */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* Treat file as system include file. */ -#endif - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup DMA_DESCRIPTOR DMA Descriptor - * @{ - *****************************************************************************/ -/** DMA_DESCRIPTOR Register Declaration */ -typedef struct { - /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ - /* pointer and referenced memory are declared volatile. */ - __IOM uint32_t CTRL; /**< DMA control register */ - __IOM void * __IOM SRC; /**< DMA source address */ - __IOM void * __IOM DST; /**< DMA destination address */ - __IOM void * __IOM LINK; /**< DMA link address */ -} DMA_DESCRIPTOR_TypeDef; /**< @} */ - -/** @} End of group Parts */ - -#endif // EFR32MG24_DMA_DESCRIPTOR_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DMA_DESCRIPTOR_H +#define EFR32MG24_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // EFR32MG24_DMA_DESCRIPTOR_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h index f1f1e3e..a716fbc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_dpll.h @@ -1,232 +1,232 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 DPLL register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_DPLL_H -#define EFR32MG24_DPLL_H -#define DPLL_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_DPLL DPLL - * @{ - * @brief EFR32MG24 DPLL Register Declaration. - *****************************************************************************/ - -/** DPLL Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CFG1; /**< Config1 */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CFG1_SET; /**< Config1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CFG1_CLR; /**< Config1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CFG1_TGL; /**< Config1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status */ - uint32_t RESERVED6[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock */ -} DPLL_TypeDef; -/** @} End of group EFR32MG24_DPLL */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_DPLL - * @{ - * @defgroup EFR32MG24_DPLL_BitFields DPLL Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DPLL IPVERSION */ -#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ -#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ - -/* Bit fields for DPLL EN */ -#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ -#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ -#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ -#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ -#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ -#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ -#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ - -/* Bit fields for DPLL CFG */ -#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ -#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ -#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ -#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ -#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ -#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ -#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ -#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ -#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ -#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ -#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ -#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ -#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ - -/* Bit fields for DPLL CFG1 */ -#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ -#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ -#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ -#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ -#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ -#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ -#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ -#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ - -/* Bit fields for DPLL IF */ -#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ -#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ -#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ -#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ -#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ -#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ - -/* Bit fields for DPLL IEN */ -#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ -#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ -#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ -#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ -#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ -#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ - -/* Bit fields for DPLL STATUS */ -#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ -#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ -#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ -#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ -#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ -#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ -#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ -#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ - -/* Bit fields for DPLL LOCK */ -#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ -#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ - -/** @} End of group EFR32MG24_DPLL_BitFields */ -/** @} End of group EFR32MG24_DPLL */ -/** @} End of group Parts */ - -#endif // EFR32MG24_DPLL_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_DPLL_H +#define EFR32MG24_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_DPLL DPLL + * @{ + * @brief EFR32MG24 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32MG24_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_DPLL + * @{ + * @defgroup EFR32MG24_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000003UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _DPLL_EN_DISABLING_SHIFT 1 /**< Shift value for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_MASK 0x2UL /**< Bit mask for DPLL_DISABLING */ +#define _DPLL_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_DISABLING_DEFAULT (_DPLL_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32MG24_DPLL_BitFields */ +/** @} End of group EFR32MG24_DPLL */ +/** @} End of group Parts */ + +#endif // EFR32MG24_DPLL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h index c3c1593..4119e1a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_emu.h @@ -1,779 +1,779 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 EMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_EMU_H -#define EFR32MG24_EMU_H -#define EMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_EMU EMU - * @{ - * @brief EFR32MG24 EMU Register Declaration. - *****************************************************************************/ - -/** EMU Register Declaration. */ -typedef struct { - uint32_t RESERVED0[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED3[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t LOCK; /**< EMU Configuration lock register */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL; /**< EM4 Control */ - __IOM uint32_t CMD; /**< EMU Command register */ - __IOM uint32_t CTRL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< EMU Status register */ - __IM uint32_t TEMP; /**< Temperature */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ - uint32_t RESERVED7[6U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED10[14U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[18U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[924U]; /**< Reserved for future use */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ - uint32_t RESERVED17[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ - uint32_t RESERVED18[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ - __IOM uint32_t CMD_SET; /**< EMU Command register */ - __IOM uint32_t CTRL_SET; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< EMU Status register */ - __IM uint32_t TEMP_SET; /**< Temperature */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ - uint32_t RESERVED22[6U]; /**< Reserved for future use */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - uint32_t RESERVED24[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED25[14U]; /**< Reserved for future use */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - uint32_t RESERVED27[18U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[924U]; /**< Reserved for future use */ - uint32_t RESERVED30[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ - uint32_t RESERVED32[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ - uint32_t RESERVED33[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ - __IOM uint32_t CMD_CLR; /**< EMU Command register */ - __IOM uint32_t CTRL_CLR; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< EMU Status register */ - __IM uint32_t TEMP_CLR; /**< Temperature */ - uint32_t RESERVED35[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ - uint32_t RESERVED37[6U]; /**< Reserved for future use */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - uint32_t RESERVED39[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED40[14U]; /**< Reserved for future use */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - uint32_t RESERVED42[18U]; /**< Reserved for future use */ - uint32_t RESERVED43[1U]; /**< Reserved for future use */ - uint32_t RESERVED44[924U]; /**< Reserved for future use */ - uint32_t RESERVED45[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ - uint32_t RESERVED47[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED48[6U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ - __IOM uint32_t CMD_TGL; /**< EMU Command register */ - __IOM uint32_t CTRL_TGL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ - uint32_t RESERVED49[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< EMU Status register */ - __IM uint32_t TEMP_TGL; /**< Temperature */ - uint32_t RESERVED50[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ - __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ - uint32_t RESERVED52[6U]; /**< Reserved for future use */ - uint32_t RESERVED53[1U]; /**< Reserved for future use */ - uint32_t RESERVED54[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED55[14U]; /**< Reserved for future use */ - uint32_t RESERVED56[1U]; /**< Reserved for future use */ - uint32_t RESERVED57[18U]; /**< Reserved for future use */ - uint32_t RESERVED58[1U]; /**< Reserved for future use */ -} EMU_TypeDef; -/** @} End of group EFR32MG24_EMU */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_EMU - * @{ - * @defgroup EFR32MG24_EMU_BitFields EMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for EMU DECBOD */ -#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ -#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ -#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ -#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ -#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ -#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ - -/* Bit fields for EMU BOD3SENSE */ -#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ -#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ -#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ - -/* Bit fields for EMU VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ - -/* Bit fields for EMU PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ -#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ - -/* Bit fields for EMU IPVERSION */ -#define _EMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for EMU_IPVERSION */ -#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ -#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_IPVERSION */ -#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ - -/* Bit fields for EMU LOCK */ -#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ -#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ - -/* Bit fields for EMU IF */ -#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ -#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ -#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ -#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ -#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ -#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ -#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ - -/* Bit fields for EMU IEN */ -#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ -#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ -#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ -#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ -#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ - -/* Bit fields for EMU EM4CTRL */ -#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ - -/* Bit fields for EMU CMD */ -#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ -#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ -#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ -#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ -#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ -#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ -#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ -#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ -#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ - -/* Bit fields for EMU CTRL */ -#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ -#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ -#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ -#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ -#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ -#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ - -/* Bit fields for EMU TEMPLIMITS */ -#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ - -/* Bit fields for EMU STATUS */ -#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ -#define _EMU_STATUS_MASK 0xFFFFEFFFUL /**< Mask for EMU_STATUS */ -#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ -#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ -#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ -#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ -#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ -#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ -#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ -#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ -#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ -#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE (0x1UL << 8) /**< RAC active */ -#define _EMU_STATUS_RACACTIVE_SHIFT 8 /**< Shift value for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_MASK 0x100UL /**< Bit mask for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET (0x1UL << 9) /**< EM4 IO retention status */ -#define _EMU_STATUS_EM4IORET_SHIFT 9 /**< Shift value for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_MASK 0x200UL /**< Bit mask for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED (0x1UL << 10) /**< EM2 entered */ -#define _EMU_STATUS_EM2ENTERED_SHIFT 10 /**< Shift value for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_MASK 0x400UL /**< Bit mask for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ - -/* Bit fields for EMU TEMP */ -#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ -#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ -#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ -#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ -#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ - -/* Bit fields for EMU RSTCTRL */ -#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ -#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ -#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ -#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ -#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ -#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ - -/* Bit fields for EMU RSTCAUSE */ -#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ -#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ -#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ -#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ -#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ -#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ -#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ -#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ -#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ -#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ -#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ -#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ -#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ -#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ -#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ -#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ -#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ -#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ -#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ -#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ - -/* Bit fields for EMU TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ -#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ -#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ - -/* Bit fields for EMU DGIF */ -#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ -#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ - -/* Bit fields for EMU DGIEN */ -#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ -#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ - -/* Bit fields for EMU EFPIF */ -#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ -#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ -#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ - -/* Bit fields for EMU EFPIEN */ -#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ -#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ -#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ - -/** @} End of group EFR32MG24_EMU_BitFields */ -/** @} End of group EFR32MG24_EMU */ -/** @} End of group Parts */ - -#endif // EFR32MG24_EMU_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_EMU_H +#define EFR32MG24_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_EMU EMU + * @{ + * @brief EFR32MG24 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct { + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE; /**< Tamper Reset cause */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[14U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[18U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[924U]; /**< Reserved for future use */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED17[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_SET; /**< Tamper Reset cause */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED22[6U]; /**< Reserved for future use */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + uint32_t RESERVED24[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED25[14U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[18U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[924U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED32[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED33[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED35[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_CLR; /**< Tamper Reset cause */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED37[6U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED40[14U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[18U]; /**< Reserved for future use */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + uint32_t RESERVED44[924U]; /**< Reserved for future use */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED47[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED48[6U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED49[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED50[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + __IM uint32_t TAMPERRSTCAUSE_TGL; /**< Tamper Reset cause */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED52[6U]; /**< Reserved for future use */ + uint32_t RESERVED53[1U]; /**< Reserved for future use */ + uint32_t RESERVED54[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED55[14U]; /**< Reserved for future use */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + uint32_t RESERVED57[18U]; /**< Reserved for future use */ + uint32_t RESERVED58[1U]; /**< Reserved for future use */ +} EMU_TypeDef; +/** @} End of group EFR32MG24_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_EMU + * @{ + * @defgroup EFR32MG24_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN 0x00000001UL /**< Mode PERIPHNORETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN 0x00000002UL /**< Mode RADIONORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_PERIPHNORETAIN << 0) /**< Shifted mode PERIPHNORETAIN for EMU_PD1PARETCTRL*/ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RADIONORETAIN << 0) /**< Shifted mode RADIONORETAIN for EMU_PD1PARETCTRL*/ + +/* Bit fields for EMU IPVERSION */ +#define _EMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for EMU_IPVERSION */ +#define _EMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_IPVERSION */ +#define _EMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_IPVERSION */ +#define EMU_IPVERSION_IPVERSION_DEFAULT (_EMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IPVERSION */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00060E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR (0x1UL << 18) /**< Tamper Reset Cause Clear */ +#define _EMU_CMD_TAMPERRCCLR_SHIFT 18 /**< Shift value for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_MASK 0x40000UL /**< Bit mask for EMU_TAMPERRCCLR */ +#define _EMU_CMD_TAMPERRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TAMPERRCCLR_DEFAULT (_EMU_CMD_TAMPERRCCLR_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFFFFEFFFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 8) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 8 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x100UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 9) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 9 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x200UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 10) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 10 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x400UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x00060407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC006C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8006FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1 (0x1UL << 4) /**< Watchdog 1 Reset */ +#define _EMU_RSTCAUSE_WDOG1_SHIFT 4 /**< Shift value for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_MASK 0x10UL /**< Bit mask for EMU_WDOG1 */ +#define _EMU_RSTCAUSE_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG1_DEFAULT (_EMU_RSTCAUSE_WDOG1_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER (0x1UL << 13) /**< SE Tamper event Reset */ +#define _EMU_RSTCAUSE_SETAMPER_SHIFT 13 /**< Shift value for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_MASK 0x2000UL /**< Bit mask for EMU_SETAMPER */ +#define _EMU_RSTCAUSE_SETAMPER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SETAMPER_DEFAULT (_EMU_RSTCAUSE_SETAMPER_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_MASK 0xFFFFFFFFUL /**< Mask for EMU_TAMPERRSTCAUSE */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_SHIFT 0 /**< Shift value for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_MASK 0xFFFFFFFFUL /**< Bit mask for EMU_TAMPERRST */ +#define _EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TAMPERRSTCAUSE */ +#define EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT (_EMU_TAMPERRSTCAUSE_TAMPERRST_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TAMPERRSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32MG24_EMU_BitFields */ +/** @} End of group EFR32MG24_EMU */ +/** @} End of group Parts */ + +#endif // EFR32MG24_EMU_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h index c8e54c9..0c96d0f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_eusart.h @@ -1,1319 +1,1319 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 EUSART register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_EUSART_H -#define EFR32MG24_EUSART_H -#define EUSART_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_EUSART EUSART - * @{ - * @brief EFR32MG24 EUSART Register Declaration. - *****************************************************************************/ - -/** EUSART Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG0; /**< Configuration 0 Register */ - __IOM uint32_t CFG1; /**< Configuration 1 Register */ - __IOM uint32_t CFG2; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t RXDATA; /**< RX Data Register */ - __IM uint32_t RXDATAP; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA; /**< TX Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t DALICFG; /**< DALI Config Register */ - uint32_t RESERVED0[41U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t RXDATA_SET; /**< RX Data Register */ - __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< TX Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t DALICFG_SET; /**< DALI Config Register */ - uint32_t RESERVED3[41U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t RXDATA_CLR; /**< RX Data Register */ - __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t DALICFG_CLR; /**< DALI Config Register */ - uint32_t RESERVED6[41U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[959U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ - __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ - __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ - __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ - __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t RXDATA_TGL; /**< RX Data Register */ - __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t DALICFG_TGL; /**< DALI Config Register */ - uint32_t RESERVED9[41U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ -} EUSART_TypeDef; -/** @} End of group EFR32MG24_EUSART */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_EUSART - * @{ - * @defgroup EFR32MG24_EUSART_BitFields EUSART Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for EUSART IPVERSION */ -#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ -#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ - -/* Bit fields for EUSART EN */ -#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ -#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ -#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ -#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ -#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ -#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ -#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ - -/* Bit fields for EUSART CFG0 */ -#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ -#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ -#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ -#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ -#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ -#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ -#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ -#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ -#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ -#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ -#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ - -/* Bit fields for EUSART CFG1 */ -#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ -#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ -#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ -#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ -#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ -#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ -#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ -#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ -#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ -#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ - -/* Bit fields for EUSART CFG2 */ -#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ -#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ -#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ -#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ -#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ -#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ -#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ -#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ -#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ -#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ -#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ -#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ -#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ -#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ -#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ -#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ -#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ -#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ -#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ -#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ -#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ -#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ -#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ -#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ -#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ -#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ - -/* Bit fields for EUSART FRAMECFG */ -#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ -#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ - -/* Bit fields for EUSART DTXDATCFG */ -#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ -#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ -#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ -#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ - -/* Bit fields for EUSART IRHFCFG */ -#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ -#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ - -/* Bit fields for EUSART IRLFCFG */ -#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ -#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ -#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ - -/* Bit fields for EUSART TIMINGCFG */ -#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ -#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ -#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ -#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ -#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ - -/* Bit fields for EUSART STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ -#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ - -/* Bit fields for EUSART SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ -#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ - -/* Bit fields for EUSART CLKDIV */ -#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ -#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ - -/* Bit fields for EUSART TRIGCTRL */ -#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ -#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ -#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ -#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ - -/* Bit fields for EUSART CMD */ -#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ -#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ -#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ -#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ -#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ -#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ -#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ -#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ - -/* Bit fields for EUSART RXDATA */ -#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ -#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ - -/* Bit fields for EUSART RXDATAP */ -#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ - -/* Bit fields for EUSART TXDATA */ -#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ -#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ - -/* Bit fields for EUSART STATUS */ -#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ -#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ -#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ -#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ -#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ -#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ -#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ -#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ -#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ - -/* Bit fields for EUSART IF */ -#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ -#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ -#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ -#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ -#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ -#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ -#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ -#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ -#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ -#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ -#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ -#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ - -/* Bit fields for EUSART IEN */ -#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ -#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ -#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ -#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ -#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ -#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ -#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ -#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ -#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ -#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ -#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ -#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ -#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ -#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ -#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ -#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ -#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ -#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ -#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ -#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ -#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ -#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ -#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ -#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ -#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ -#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ - -/* Bit fields for EUSART SYNCBUSY */ -#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ -#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ -#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ -#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ -#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ -#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ -#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ -#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ -#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ -#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ - -/* Bit fields for EUSART DALICFG */ -#define _EUSART_DALICFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DALICFG */ -#define _EUSART_DALICFG_MASK 0x00009F3FUL /**< Mask for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIEN (0x1UL << 0) /**< DALI Enable Bit */ -#define _EUSART_DALICFG_DALIEN_SHIFT 0 /**< Shift value for EUSART_DALIEN */ -#define _EUSART_DALICFG_DALIEN_MASK 0x1UL /**< Bit mask for EUSART_DALIEN */ -#define _EUSART_DALICFG_DALIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIEN_DEFAULT (_EUSART_DALICFG_DALIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_SHIFT 1 /**< Shift value for EUSART_DALITXDATABITS */ -#define _EUSART_DALICFG_DALITXDATABITS_MASK 0x3EUL /**< Bit mask for EUSART_DALITXDATABITS */ -#define _EUSART_DALICFG_DALITXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_DEFAULT (_EUSART_DALICFG_DALITXDATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_EIGHT (_EUSART_DALICFG_DALITXDATABITS_EIGHT << 1) /**< Shifted mode EIGHT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_NINE (_EUSART_DALICFG_DALITXDATABITS_NINE << 1) /**< Shifted mode NINE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TEN (_EUSART_DALICFG_DALITXDATABITS_TEN << 1) /**< Shifted mode TEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_ELEVEN (_EUSART_DALICFG_DALITXDATABITS_ELEVEN << 1) /**< Shifted mode ELEVEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWELVE (_EUSART_DALICFG_DALITXDATABITS_TWELVE << 1) /**< Shifted mode TWELVE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_THIRTEEN (_EUSART_DALICFG_DALITXDATABITS_THIRTEEN << 1) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_FOURTEEN (_EUSART_DALICFG_DALITXDATABITS_FOURTEEN << 1) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_FIFTEEN (_EUSART_DALICFG_DALITXDATABITS_FIFTEEN << 1) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_SIXTEEN (_EUSART_DALICFG_DALITXDATABITS_SIXTEEN << 1) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALITXDATABITS_SEVENTEEN << 1) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALITXDATABITS_EIGHTEEN << 1) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_NINETEEN (_EUSART_DALICFG_DALITXDATABITS_NINETEEN << 1) /**< Shifted mode NINETEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTY (_EUSART_DALICFG_DALITXDATABITS_TWENTY << 1) /**< Shifted mode TWENTY for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYONE (_EUSART_DALICFG_DALITXDATABITS_TWENTYONE << 1) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALITXDATABITS_TWENTYTWO << 1) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE << 1) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR << 1) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE << 1) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALITXDATABITS_TWENTYSIX << 1) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN << 1) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT << 1) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALITXDATABITS_TWENTYNINE << 1) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_THIRTY (_EUSART_DALICFG_DALITXDATABITS_THIRTY << 1) /**< Shifted mode THIRTY for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_THIRTYONE (_EUSART_DALICFG_DALITXDATABITS_THIRTYONE << 1) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALITXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALITXDATABITS_THIRTYTWO << 1) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_SHIFT 8 /**< Shift value for EUSART_DALIRXDATABITS */ -#define _EUSART_DALICFG_DALIRXDATABITS_MASK 0x1F00UL /**< Bit mask for EUSART_DALIRXDATABITS */ -#define _EUSART_DALICFG_DALIRXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ -#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_DEFAULT (_EUSART_DALICFG_DALIRXDATABITS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_EIGHT (_EUSART_DALICFG_DALIRXDATABITS_EIGHT << 8) /**< Shifted mode EIGHT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_NINE (_EUSART_DALICFG_DALIRXDATABITS_NINE << 8) /**< Shifted mode NINE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TEN (_EUSART_DALICFG_DALIRXDATABITS_TEN << 8) /**< Shifted mode TEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_ELEVEN (_EUSART_DALICFG_DALIRXDATABITS_ELEVEN << 8) /**< Shifted mode ELEVEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWELVE (_EUSART_DALICFG_DALIRXDATABITS_TWELVE << 8) /**< Shifted mode TWELVE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_THIRTEEN (_EUSART_DALICFG_DALIRXDATABITS_THIRTEEN << 8) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_FOURTEEN (_EUSART_DALICFG_DALIRXDATABITS_FOURTEEN << 8) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_FIFTEEN (_EUSART_DALICFG_DALIRXDATABITS_FIFTEEN << 8) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_SIXTEEN (_EUSART_DALICFG_DALIRXDATABITS_SIXTEEN << 8) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN << 8) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN << 8) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_NINETEEN (_EUSART_DALICFG_DALIRXDATABITS_NINETEEN << 8) /**< Shifted mode NINETEEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTY (_EUSART_DALICFG_DALIRXDATABITS_TWENTY << 8) /**< Shifted mode TWENTY for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYONE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYONE << 8) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO << 8) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE << 8) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR << 8) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE << 8) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX << 8) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN << 8) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT << 8) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE << 8) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_THIRTY (_EUSART_DALICFG_DALIRXDATABITS_THIRTY << 8) /**< Shifted mode THIRTY for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_THIRTYONE (_EUSART_DALICFG_DALIRXDATABITS_THIRTYONE << 8) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO << 8) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXENDT (0x1UL << 15) /**< DALI RX Enabled During Transmission */ -#define _EUSART_DALICFG_DALIRXENDT_SHIFT 15 /**< Shift value for EUSART_DALIRXENDT */ -#define _EUSART_DALICFG_DALIRXENDT_MASK 0x8000UL /**< Bit mask for EUSART_DALIRXENDT */ -#define _EUSART_DALICFG_DALIRXENDT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ -#define EUSART_DALICFG_DALIRXENDT_DEFAULT (_EUSART_DALICFG_DALIRXENDT_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_DALICFG */ - -/** @} End of group EFR32MG24_EUSART_BitFields */ -/** @} End of group EFR32MG24_EUSART */ -/** @} End of group Parts */ - -#endif // EFR32MG24_EUSART_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_EUSART_H +#define EFR32MG24_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_EUSART EUSART + * @{ + * @brief EFR32MG24 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t CFG2; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG; /**< DALI Config Register */ + uint32_t RESERVED0[41U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_SET; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_SET; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_SET; /**< DALI Config Register */ + uint32_t RESERVED3[41U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_CLR; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_CLR; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_CLR; /**< DALI Config Register */ + uint32_t RESERVED6[41U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[959U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t CFG2_TGL; /**< Configuration 2 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t DTXDATCFG_TGL; /**< Default TX DATA Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t DALICFG_TGL; /**< DALI Config Register */ + uint32_t RESERVED9[41U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} EUSART_TypeDef; +/** @} End of group EFR32MG24_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_EUSART + * @{ + * @defgroup EFR32MG24_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000003UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _EUSART_EN_DISABLING_SHIFT 1 /**< Shift value for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_MASK 0x2UL /**< Bit mask for EUSART_DISABLING */ +#define _EUSART_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_DISABLING_DEFAULT (_EUSART_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FFUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC (0x1UL << 0) /**< Synchronous Mode */ +#define _EUSART_CFG0_SYNC_SHIFT 0 /**< Shift value for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_MASK 0x1UL /**< Bit mask for EUSART_SYNC */ +#define _EUSART_CFG0_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_ASYNC 0x00000000UL /**< Mode ASYNC for EUSART_CFG0 */ +#define _EUSART_CFG0_SYNC_SYNC 0x00000001UL /**< Mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_DEFAULT (_EUSART_CFG0_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_ASYNC (_EUSART_CFG0_SYNC_ASYNC << 0) /**< Shifted mode ASYNC for EUSART_CFG0 */ +#define EUSART_CFG0_SYNC_SYNC (_EUSART_CFG0_SYNC_SYNC << 0) /**< Shifted mode SYNC for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x7BCF8E7FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SHIFT 4 /**< Shift value for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_MASK 0x70UL /**< Bit mask for EUSART_RXTIMEOUT */ +#define _EUSART_CFG1_RXTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_DISABLED 0x00000000UL /**< Mode DISABLED for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_ONEFRAME 0x00000001UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_TWOFRAMES 0x00000002UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_THREEFRAMES 0x00000003UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FOURFRAMES 0x00000004UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_FIVEFRAMES 0x00000005UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SIXFRAMES 0x00000006UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXTIMEOUT_SEVENFRAMES 0x00000007UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DEFAULT (_EUSART_CFG1_RXTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_DISABLED (_EUSART_CFG1_RXTIMEOUT_DISABLED << 4) /**< Shifted mode DISABLED for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_ONEFRAME (_EUSART_CFG1_RXTIMEOUT_ONEFRAME << 4) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_TWOFRAMES (_EUSART_CFG1_RXTIMEOUT_TWOFRAMES << 4) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_THREEFRAMES (_EUSART_CFG1_RXTIMEOUT_THREEFRAMES << 4) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FOURFRAMES (_EUSART_CFG1_RXTIMEOUT_FOURFRAMES << 4) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_FIVEFRAMES (_EUSART_CFG1_RXTIMEOUT_FIVEFRAMES << 4) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SIXFRAMES (_EUSART_CFG1_RXTIMEOUT_SIXFRAMES << 4) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXTIMEOUT_SEVENFRAMES (_EUSART_CFG1_RXTIMEOUT_SEVENFRAMES << 4) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0xF0000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIVEFRAMES (_EUSART_CFG1_TXFIW_FIVEFRAMES << 16) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXFRAMES (_EUSART_CFG1_TXFIW_SIXFRAMES << 16) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SEVENFRAMES (_EUSART_CFG1_TXFIW_SEVENFRAMES << 16) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_EIGHTFRAMES (_EUSART_CFG1_TXFIW_EIGHTFRAMES << 16) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_NINEFRAMES (_EUSART_CFG1_TXFIW_NINEFRAMES << 16) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TENFRAMES (_EUSART_CFG1_TXFIW_TENFRAMES << 16) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ELEVENFRAMES (_EUSART_CFG1_TXFIW_ELEVENFRAMES << 16) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWELVEFRAMES (_EUSART_CFG1_TXFIW_TWELVEFRAMES << 16) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THIRTEENFRAMES (_EUSART_CFG1_TXFIW_THIRTEENFRAMES << 16) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURTEENFRAMES (_EUSART_CFG1_TXFIW_FOURTEENFRAMES << 16) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FIFTEENFRAMES (_EUSART_CFG1_TXFIW_FIFTEENFRAMES << 16) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_SIXTEENFRAMES (_EUSART_CFG1_TXFIW_SIXTEENFRAMES << 16) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0x3C00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIVEFRAMES (_EUSART_CFG1_RTSRXFW_FIVEFRAMES << 22) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXFRAMES (_EUSART_CFG1_RTSRXFW_SIXFRAMES << 22) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SEVENFRAMES (_EUSART_CFG1_RTSRXFW_SEVENFRAMES << 22) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_EIGHTFRAMES (_EUSART_CFG1_RTSRXFW_EIGHTFRAMES << 22) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_NINEFRAMES (_EUSART_CFG1_RTSRXFW_NINEFRAMES << 22) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TENFRAMES (_EUSART_CFG1_RTSRXFW_TENFRAMES << 22) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ELEVENFRAMES (_EUSART_CFG1_RTSRXFW_ELEVENFRAMES << 22) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWELVEFRAMES (_EUSART_CFG1_RTSRXFW_TWELVEFRAMES << 22) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THIRTEENFRAMES (_EUSART_CFG1_RTSRXFW_THIRTEENFRAMES << 22) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURTEENFRAMES (_EUSART_CFG1_RTSRXFW_FOURTEENFRAMES << 22) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FIFTEENFRAMES (_EUSART_CFG1_RTSRXFW_FIFTEENFRAMES << 22) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_SIXTEENFRAMES (_EUSART_CFG1_RTSRXFW_SIXTEENFRAMES << 22) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 27 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x78000000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIVEFRAMES 0x00000004UL /**< Mode FIVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXFRAMES 0x00000005UL /**< Mode SIXFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SEVENFRAMES 0x00000006UL /**< Mode SEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_EIGHTFRAMES 0x00000007UL /**< Mode EIGHTFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_NINEFRAMES 0x00000008UL /**< Mode NINEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TENFRAMES 0x00000009UL /**< Mode TENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ELEVENFRAMES 0x0000000AUL /**< Mode ELEVENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWELVEFRAMES 0x0000000BUL /**< Mode TWELVEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THIRTEENFRAMES 0x0000000CUL /**< Mode THIRTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURTEENFRAMES 0x0000000DUL /**< Mode FOURTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FIFTEENFRAMES 0x0000000EUL /**< Mode FIFTEENFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SIXTEENFRAMES 0x0000000FUL /**< Mode SIXTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 27) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 27) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 27) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 27) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 27) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIVEFRAMES (_EUSART_CFG1_RXFIW_FIVEFRAMES << 27) /**< Shifted mode FIVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXFRAMES (_EUSART_CFG1_RXFIW_SIXFRAMES << 27) /**< Shifted mode SIXFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SEVENFRAMES (_EUSART_CFG1_RXFIW_SEVENFRAMES << 27) /**< Shifted mode SEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_EIGHTFRAMES (_EUSART_CFG1_RXFIW_EIGHTFRAMES << 27) /**< Shifted mode EIGHTFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_NINEFRAMES (_EUSART_CFG1_RXFIW_NINEFRAMES << 27) /**< Shifted mode NINEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TENFRAMES (_EUSART_CFG1_RXFIW_TENFRAMES << 27) /**< Shifted mode TENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ELEVENFRAMES (_EUSART_CFG1_RXFIW_ELEVENFRAMES << 27) /**< Shifted mode ELEVENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWELVEFRAMES (_EUSART_CFG1_RXFIW_TWELVEFRAMES << 27) /**< Shifted mode TWELVEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THIRTEENFRAMES (_EUSART_CFG1_RXFIW_THIRTEENFRAMES << 27) /**< Shifted mode THIRTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURTEENFRAMES (_EUSART_CFG1_RXFIW_FOURTEENFRAMES << 27) /**< Shifted mode FOURTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FIFTEENFRAMES (_EUSART_CFG1_RXFIW_FIFTEENFRAMES << 27) /**< Shifted mode FIFTEENFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_SIXTEENFRAMES (_EUSART_CFG1_RXFIW_SIXTEENFRAMES << 27) /**< Shifted mode SIXTEENFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART CFG2 */ +#define _EUSART_CFG2_RESETVALUE 0x00000020UL /**< Default value for EUSART_CFG2 */ +#define _EUSART_CFG2_MASK 0xFF0000FFUL /**< Mask for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER (0x1UL << 0) /**< Main mode */ +#define _EUSART_CFG2_MASTER_SHIFT 0 /**< Shift value for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_MASK 0x1UL /**< Bit mask for EUSART_MASTER */ +#define _EUSART_CFG2_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_SLAVE 0x00000000UL /**< Mode SLAVE for EUSART_CFG2 */ +#define _EUSART_CFG2_MASTER_MASTER 0x00000001UL /**< Mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_DEFAULT (_EUSART_CFG2_MASTER_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_SLAVE (_EUSART_CFG2_MASTER_SLAVE << 0) /**< Shifted mode SLAVE for EUSART_CFG2 */ +#define EUSART_CFG2_MASTER_MASTER (_EUSART_CFG2_MASTER_MASTER << 0) /**< Shifted mode MASTER for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL (0x1UL << 1) /**< Clock Polarity */ +#define _EUSART_CFG2_CLKPOL_SHIFT 1 /**< Shift value for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_MASK 0x2UL /**< Bit mask for EUSART_CLKPOL */ +#define _EUSART_CFG2_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_DEFAULT (_EUSART_CFG2_CLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLELOW (_EUSART_CFG2_CLKPOL_IDLELOW << 1) /**< Shifted mode IDLELOW for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPOL_IDLEHIGH (_EUSART_CFG2_CLKPOL_IDLEHIGH << 1) /**< Shifted mode IDLEHIGH for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA (0x1UL << 2) /**< Clock Edge for Setup/Sample */ +#define _EUSART_CFG2_CLKPHA_SHIFT 2 /**< Shift value for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_MASK 0x4UL /**< Bit mask for EUSART_CLKPHA */ +#define _EUSART_CFG2_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for EUSART_CFG2 */ +#define _EUSART_CFG2_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_DEFAULT (_EUSART_CFG2_CLKPHA_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLELEADING (_EUSART_CFG2_CLKPHA_SAMPLELEADING << 2) /**< Shifted mode SAMPLELEADING for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPHA_SAMPLETRAILING (_EUSART_CFG2_CLKPHA_SAMPLETRAILING << 2) /**< Shifted mode SAMPLETRAILING for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV (0x1UL << 3) /**< Chip Select Invert */ +#define _EUSART_CFG2_CSINV_SHIFT 3 /**< Shift value for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_MASK 0x8UL /**< Bit mask for EUSART_CSINV */ +#define _EUSART_CFG2_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AL 0x00000000UL /**< Mode AL for EUSART_CFG2 */ +#define _EUSART_CFG2_CSINV_AH 0x00000001UL /**< Mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_DEFAULT (_EUSART_CFG2_CSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AL (_EUSART_CFG2_CSINV_AL << 3) /**< Shifted mode AL for EUSART_CFG2 */ +#define EUSART_CFG2_CSINV_AH (_EUSART_CFG2_CSINV_AH << 3) /**< Shifted mode AH for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX (0x1UL << 4) /**< Always Transmit When RXFIFO Not Full */ +#define _EUSART_CFG2_AUTOTX_SHIFT 4 /**< Shift value for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_MASK 0x10UL /**< Bit mask for EUSART_AUTOTX */ +#define _EUSART_CFG2_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOTX_DEFAULT (_EUSART_CFG2_AUTOTX_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS (0x1UL << 5) /**< Automatic Chip Select */ +#define _EUSART_CFG2_AUTOCS_SHIFT 5 /**< Shift value for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_MASK 0x20UL /**< Bit mask for EUSART_AUTOCS */ +#define _EUSART_CFG2_AUTOCS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_AUTOCS_DEFAULT (_EUSART_CFG2_AUTOCS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN (0x1UL << 6) /**< PRS CLK Enable */ +#define _EUSART_CFG2_CLKPRSEN_SHIFT 6 /**< Shift value for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_MASK 0x40UL /**< Bit mask for EUSART_CLKPRSEN */ +#define _EUSART_CFG2_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_CLKPRSEN_DEFAULT (_EUSART_CFG2_CLKPRSEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD (0x1UL << 7) /**< Force Load to Shift Register */ +#define _EUSART_CFG2_FORCELOAD_SHIFT 7 /**< Shift value for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_MASK 0x80UL /**< Bit mask for EUSART_FORCELOAD */ +#define _EUSART_CFG2_FORCELOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_FORCELOAD_DEFAULT (_EUSART_CFG2_FORCELOAD_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CFG2 */ +#define _EUSART_CFG2_SDIV_SHIFT 24 /**< Shift value for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_MASK 0xFF000000UL /**< Bit mask for EUSART_SDIV */ +#define _EUSART_CFG2_SDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG2 */ +#define EUSART_CFG2_SDIV_DEFAULT (_EUSART_CFG2_SDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG2 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x0000330FUL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0xFUL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TEN 0x00000004UL /**< Mode TEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_ELEVEN 0x00000005UL /**< Mode ELEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_TWELVE 0x00000006UL /**< Mode TWELVE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_THIRTEEN 0x00000007UL /**< Mode THIRTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FOURTEEN 0x00000008UL /**< Mode FOURTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_FIFTEEN 0x00000009UL /**< Mode FIFTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SIXTEEN 0x0000000AUL /**< Mode SIXTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TEN (_EUSART_FRAMECFG_DATABITS_TEN << 0) /**< Shifted mode TEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_ELEVEN (_EUSART_FRAMECFG_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_TWELVE (_EUSART_FRAMECFG_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_THIRTEEN (_EUSART_FRAMECFG_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FOURTEEN (_EUSART_FRAMECFG_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_FIFTEEN (_EUSART_FRAMECFG_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SIXTEEN (_EUSART_FRAMECFG_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART DTXDATCFG */ +#define _EUSART_DTXDATCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_MASK 0x0000FFFFUL /**< Mask for EUSART_DTXDATCFG */ +#define _EUSART_DTXDATCFG_DTXDAT_SHIFT 0 /**< Shift value for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_MASK 0xFFFFUL /**< Bit mask for EUSART_DTXDAT */ +#define _EUSART_DTXDATCFG_DTXDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DTXDATCFG */ +#define EUSART_DTXDATCFG_DTXDAT_DEFAULT (_EUSART_DTXDATCFG_DTXDAT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DTXDATCFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00050000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x000F7773UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SHIFT 4 /**< Shift value for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_MASK 0x70UL /**< Bit mask for EUSART_CSSETUP */ +#define _EUSART_TIMINGCFG_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSSETUP_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_DEFAULT (_EUSART_TIMINGCFG_CSSETUP_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ZERO (_EUSART_TIMINGCFG_CSSETUP_ZERO << 4) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_ONE (_EUSART_TIMINGCFG_CSSETUP_ONE << 4) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_TWO (_EUSART_TIMINGCFG_CSSETUP_TWO << 4) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_THREE (_EUSART_TIMINGCFG_CSSETUP_THREE << 4) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FOUR (_EUSART_TIMINGCFG_CSSETUP_FOUR << 4) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_FIVE (_EUSART_TIMINGCFG_CSSETUP_FIVE << 4) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SIX (_EUSART_TIMINGCFG_CSSETUP_SIX << 4) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSSETUP_SEVEN (_EUSART_TIMINGCFG_CSSETUP_SEVEN << 4) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SHIFT 8 /**< Shift value for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_MASK 0x700UL /**< Bit mask for EUSART_CSHOLD */ +#define _EUSART_TIMINGCFG_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_CSHOLD_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_DEFAULT (_EUSART_TIMINGCFG_CSHOLD_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ZERO (_EUSART_TIMINGCFG_CSHOLD_ZERO << 8) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_ONE (_EUSART_TIMINGCFG_CSHOLD_ONE << 8) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_TWO (_EUSART_TIMINGCFG_CSHOLD_TWO << 8) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_THREE (_EUSART_TIMINGCFG_CSHOLD_THREE << 8) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FOUR (_EUSART_TIMINGCFG_CSHOLD_FOUR << 8) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_FIVE (_EUSART_TIMINGCFG_CSHOLD_FIVE << 8) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SIX (_EUSART_TIMINGCFG_CSHOLD_SIX << 8) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_CSHOLD_SEVEN (_EUSART_TIMINGCFG_CSHOLD_SEVEN << 8) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SHIFT 12 /**< Shift value for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_MASK 0x7000UL /**< Bit mask for EUSART_ICS */ +#define _EUSART_TIMINGCFG_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ZERO 0x00000000UL /**< Mode ZERO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_ONE 0x00000001UL /**< Mode ONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_TWO 0x00000002UL /**< Mode TWO for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_THREE 0x00000003UL /**< Mode THREE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FOUR 0x00000004UL /**< Mode FOUR for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_FIVE 0x00000005UL /**< Mode FIVE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SIX 0x00000006UL /**< Mode SIX for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_ICS_SEVEN 0x00000007UL /**< Mode SEVEN for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_DEFAULT (_EUSART_TIMINGCFG_ICS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ZERO (_EUSART_TIMINGCFG_ICS_ZERO << 12) /**< Shifted mode ZERO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_ONE (_EUSART_TIMINGCFG_ICS_ONE << 12) /**< Shifted mode ONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_TWO (_EUSART_TIMINGCFG_ICS_TWO << 12) /**< Shifted mode TWO for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_THREE (_EUSART_TIMINGCFG_ICS_THREE << 12) /**< Shifted mode THREE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FOUR (_EUSART_TIMINGCFG_ICS_FOUR << 12) /**< Shifted mode FOUR for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_FIVE (_EUSART_TIMINGCFG_ICS_FIVE << 12) /**< Shifted mode FIVE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SIX (_EUSART_TIMINGCFG_ICS_SIX << 12) /**< Shifted mode SIX for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_ICS_SEVEN (_EUSART_TIMINGCFG_ICS_SEVEN << 12) /**< Shifted mode SEVEN for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT 16 /**< Shift value for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_MASK 0xF0000UL /**< Bit mask for EUSART_SETUPWINDOW */ +#define _EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT 0x00000005UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT (_EUSART_TIMINGCFG_SETUPWINDOW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0xFFFFFFFFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000007UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN (0x1UL << 2) /**< AUTOTX Trigger Enable */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_SHIFT 2 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_MASK 0x4UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT (_EUSART_TRIGCTRL_AUTOTXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x0000FFFFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0xFFFFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x0000FFFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0xFFFFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x031F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x1F0000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 25) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 25 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x2000000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x030D3FFFUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF (0x1UL << 7) /**< TX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IF_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXUF_DEFAULT (_EUSART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR (0x1UL << 11) /**< Load Error Interrupt Flag */ +#define _EUSART_IF_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IF_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_LOADERR_DEFAULT (_EUSART_IF_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU (0x1UL << 16) /**< CS Wake-up Interrupt Flag */ +#define _EUSART_IF_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IF_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IF_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CSWU_DEFAULT (_EUSART_IF_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO (0x1UL << 25) /**< RX Timeout Interrupt Flag */ +#define _EUSART_IF_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IF_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IF_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXTO_DEFAULT (_EUSART_IF_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x030D3FFFUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete Enable */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level Enable */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level Enable */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full Enable */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow Enable */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow Enable */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow Enable */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF (0x1UL << 7) /**< TX FIFO Underflow Enable */ +#define _EUSART_IEN_TXUF_SHIFT 7 /**< Shift value for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_MASK 0x80UL /**< Bit mask for EUSART_TXUF */ +#define _EUSART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXUF_DEFAULT (_EUSART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error Enable */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error Enable */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame Enable */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR (0x1UL << 11) /**< Load Error Enable */ +#define _EUSART_IEN_LOADERR_SHIFT 11 /**< Shift value for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_MASK 0x800UL /**< Bit mask for EUSART_LOADERR */ +#define _EUSART_IEN_LOADERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_LOADERR_DEFAULT (_EUSART_IEN_LOADERR_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Enable */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE Enable */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU (0x1UL << 16) /**< CS Wake-up Enable */ +#define _EUSART_IEN_CSWU_SHIFT 16 /**< Shift value for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_MASK 0x10000UL /**< Bit mask for EUSART_CSWU */ +#define _EUSART_IEN_CSWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CSWU_DEFAULT (_EUSART_IEN_CSWU_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame Enable */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame Enable */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Enable */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO (0x1UL << 25) /**< RX Timeout Enable */ +#define _EUSART_IEN_RXTO_SHIFT 25 /**< Shift value for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_MASK 0x2000000UL /**< Bit mask for EUSART_RXTO */ +#define _EUSART_IEN_RXTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXTO_DEFAULT (_EUSART_IEN_RXTO_DEFAULT << 25) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x00000FFFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN (0x1UL << 11) /**< SYNCBUSY for AUTOTXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_SHIFT 11 /**< Shift value for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_MASK 0x800UL /**< Bit mask for EUSART_AUTOTXTEN */ +#define _EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT (_EUSART_SYNCBUSY_AUTOTXTEN_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/* Bit fields for EUSART DALICFG */ +#define _EUSART_DALICFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_DALICFG */ +#define _EUSART_DALICFG_MASK 0x00009F3FUL /**< Mask for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN (0x1UL << 0) /**< DALI Enable Bit */ +#define _EUSART_DALICFG_DALIEN_SHIFT 0 /**< Shift value for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_MASK 0x1UL /**< Bit mask for EUSART_DALIEN */ +#define _EUSART_DALICFG_DALIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIEN_DEFAULT (_EUSART_DALICFG_DALIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SHIFT 1 /**< Shift value for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_MASK 0x3EUL /**< Bit mask for EUSART_DALITXDATABITS */ +#define _EUSART_DALICFG_DALITXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_DEFAULT (_EUSART_DALICFG_DALITXDATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHT (_EUSART_DALICFG_DALITXDATABITS_EIGHT << 1) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINE (_EUSART_DALICFG_DALITXDATABITS_NINE << 1) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TEN (_EUSART_DALICFG_DALITXDATABITS_TEN << 1) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_ELEVEN (_EUSART_DALICFG_DALITXDATABITS_ELEVEN << 1) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWELVE (_EUSART_DALICFG_DALITXDATABITS_TWELVE << 1) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTEEN (_EUSART_DALICFG_DALITXDATABITS_THIRTEEN << 1) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FOURTEEN (_EUSART_DALICFG_DALITXDATABITS_FOURTEEN << 1) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_FIFTEEN (_EUSART_DALICFG_DALITXDATABITS_FIFTEEN << 1) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SIXTEEN (_EUSART_DALICFG_DALITXDATABITS_SIXTEEN << 1) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALITXDATABITS_SEVENTEEN << 1) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALITXDATABITS_EIGHTEEN << 1) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_NINETEEN (_EUSART_DALICFG_DALITXDATABITS_NINETEEN << 1) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTY (_EUSART_DALICFG_DALITXDATABITS_TWENTY << 1) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYONE (_EUSART_DALICFG_DALITXDATABITS_TWENTYONE << 1) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALITXDATABITS_TWENTYTWO << 1) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE << 1) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR << 1) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE << 1) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALITXDATABITS_TWENTYSIX << 1) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN << 1) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT << 1) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALITXDATABITS_TWENTYNINE << 1) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTY (_EUSART_DALICFG_DALITXDATABITS_THIRTY << 1) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYONE (_EUSART_DALICFG_DALITXDATABITS_THIRTYONE << 1) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALITXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALITXDATABITS_THIRTYTWO << 1) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SHIFT 8 /**< Shift value for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_MASK 0x1F00UL /**< Bit mask for EUSART_DALIRXDATABITS */ +#define _EUSART_DALICFG_DALIRXDATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINE 0x00000001UL /**< Mode NINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TEN 0x00000002UL /**< Mode TEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_ELEVEN 0x00000003UL /**< Mode ELEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWELVE 0x00000004UL /**< Mode TWELVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTEEN 0x00000005UL /**< Mode THIRTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FOURTEEN 0x00000006UL /**< Mode FOURTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_FIFTEEN 0x00000007UL /**< Mode FIFTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SIXTEEN 0x00000008UL /**< Mode SIXTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN 0x00000009UL /**< Mode SEVENTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN 0x0000000AUL /**< Mode EIGHTEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_NINETEEN 0x0000000BUL /**< Mode NINETEEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTY 0x0000000CUL /**< Mode TWENTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYONE 0x0000000DUL /**< Mode TWENTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO 0x0000000EUL /**< Mode TWENTYTWO for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE 0x0000000FUL /**< Mode TWENTYTHREE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR 0x00000010UL /**< Mode TWENTYFOUR for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE 0x00000011UL /**< Mode TWENTYFIVE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX 0x00000012UL /**< Mode TWENTYSIX for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN 0x00000013UL /**< Mode TWENTYSEVEN for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT 0x00000014UL /**< Mode TWENTYEIGHT for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE 0x00000015UL /**< Mode TWENTYNINE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTY 0x00000016UL /**< Mode THIRTY for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYONE 0x00000017UL /**< Mode THIRTYONE for EUSART_DALICFG */ +#define _EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO 0x00000018UL /**< Mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_DEFAULT (_EUSART_DALICFG_DALIRXDATABITS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHT (_EUSART_DALICFG_DALIRXDATABITS_EIGHT << 8) /**< Shifted mode EIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINE (_EUSART_DALICFG_DALIRXDATABITS_NINE << 8) /**< Shifted mode NINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TEN (_EUSART_DALICFG_DALIRXDATABITS_TEN << 8) /**< Shifted mode TEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_ELEVEN (_EUSART_DALICFG_DALIRXDATABITS_ELEVEN << 8) /**< Shifted mode ELEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWELVE (_EUSART_DALICFG_DALIRXDATABITS_TWELVE << 8) /**< Shifted mode TWELVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTEEN (_EUSART_DALICFG_DALIRXDATABITS_THIRTEEN << 8) /**< Shifted mode THIRTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FOURTEEN (_EUSART_DALICFG_DALIRXDATABITS_FOURTEEN << 8) /**< Shifted mode FOURTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_FIFTEEN (_EUSART_DALICFG_DALIRXDATABITS_FIFTEEN << 8) /**< Shifted mode FIFTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SIXTEEN (_EUSART_DALICFG_DALIRXDATABITS_SIXTEEN << 8) /**< Shifted mode SIXTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN (_EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN << 8) /**< Shifted mode SEVENTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN (_EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN << 8) /**< Shifted mode EIGHTEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_NINETEEN (_EUSART_DALICFG_DALIRXDATABITS_NINETEEN << 8) /**< Shifted mode NINETEEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTY (_EUSART_DALICFG_DALIRXDATABITS_TWENTY << 8) /**< Shifted mode TWENTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYONE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYONE << 8) /**< Shifted mode TWENTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO << 8) /**< Shifted mode TWENTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYTHREE << 8) /**< Shifted mode TWENTYTHREE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR << 8) /**< Shifted mode TWENTYFOUR for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE << 8) /**< Shifted mode TWENTYFIVE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX << 8) /**< Shifted mode TWENTYSIX for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN (_EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN << 8) /**< Shifted mode TWENTYSEVEN for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT (_EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT << 8) /**< Shifted mode TWENTYEIGHT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE (_EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE << 8) /**< Shifted mode TWENTYNINE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTY (_EUSART_DALICFG_DALIRXDATABITS_THIRTY << 8) /**< Shifted mode THIRTY for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYONE (_EUSART_DALICFG_DALIRXDATABITS_THIRTYONE << 8) /**< Shifted mode THIRTYONE for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO (_EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO << 8) /**< Shifted mode THIRTYTWO for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT (0x1UL << 15) /**< DALI RX Enabled During Transmission */ +#define _EUSART_DALICFG_DALIRXENDT_SHIFT 15 /**< Shift value for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_MASK 0x8000UL /**< Bit mask for EUSART_DALIRXENDT */ +#define _EUSART_DALICFG_DALIRXENDT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_DALICFG */ +#define EUSART_DALICFG_DALIRXENDT_DEFAULT (_EUSART_DALICFG_DALIRXENDT_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_DALICFG */ + +/** @} End of group EFR32MG24_EUSART_BitFields */ +/** @} End of group EFR32MG24_EUSART */ +/** @} End of group Parts */ + +#endif // EFR32MG24_EUSART_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h index 39ccc52..de9c06c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_fsrco.h @@ -1,75 +1,75 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 FSRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_FSRCO_H -#define EFR32MG24_FSRCO_H -#define FSRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_FSRCO FSRCO - * @{ - * @brief EFR32MG24 FSRCO Register Declaration. - *****************************************************************************/ - -/** FSRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - uint32_t RESERVED0[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - uint32_t RESERVED1[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - uint32_t RESERVED2[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ -} FSRCO_TypeDef; -/** @} End of group EFR32MG24_FSRCO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_FSRCO - * @{ - * @defgroup EFR32MG24_FSRCO_BitFields FSRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for FSRCO IPVERSION */ -#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ -#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ - -/** @} End of group EFR32MG24_FSRCO_BitFields */ -/** @} End of group EFR32MG24_FSRCO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_FSRCO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_FSRCO_H +#define EFR32MG24_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_FSRCO FSRCO + * @{ + * @brief EFR32MG24 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32MG24_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_FSRCO + * @{ + * @defgroup EFR32MG24_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32MG24_FSRCO_BitFields */ +/** @} End of group EFR32MG24_FSRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_FSRCO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h index c3fbd52..e5c826e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpcrc.h @@ -1,246 +1,246 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 GPCRC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_GPCRC_H -#define EFR32MG24_GPCRC_H -#define GPCRC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_GPCRC GPCRC - * @{ - * @brief EFR32MG24 GPCRC Register Declaration. - *****************************************************************************/ - -/** GPCRC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t EN; /**< CRC Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t INIT; /**< CRC Init Value */ - __IOM uint32_t POLY; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ - __IM uint32_t DATA; /**< CRC Data Register */ - __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED0[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t EN_SET; /**< CRC Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t INIT_SET; /**< CRC Init Value */ - __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_SET; /**< CRC Data Register */ - __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED1[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t EN_CLR; /**< CRC Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t INIT_CLR; /**< CRC Init Value */ - __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_CLR; /**< CRC Data Register */ - __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED2[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t EN_TGL; /**< CRC Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t INIT_TGL; /**< CRC Init Value */ - __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_TGL; /**< CRC Data Register */ - __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ -} GPCRC_TypeDef; -/** @} End of group EFR32MG24_GPCRC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_GPCRC - * @{ - * @defgroup EFR32MG24_GPCRC_BitFields GPCRC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for GPCRC IPVERSION */ -#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ -#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ - -/* Bit fields for GPCRC EN */ -#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ -#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ -#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ -#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ -#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ -#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ -#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ -#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ -#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ -#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ -#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ - -/* Bit fields for GPCRC CTRL */ -#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ -#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ -#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ -#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ -#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ -#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ -#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ - -/* Bit fields for GPCRC CMD */ -#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ -#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ -#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ -#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ -#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ - -/* Bit fields for GPCRC INIT */ -#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ -#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ -#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ - -/* Bit fields for GPCRC POLY */ -#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ -#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ -#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ - -/* Bit fields for GPCRC INPUTDATA */ -#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ -#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ - -/* Bit fields for GPCRC INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ -#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ - -/* Bit fields for GPCRC INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ -#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ - -/* Bit fields for GPCRC DATA */ -#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ -#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ -#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ - -/* Bit fields for GPCRC DATAREV */ -#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ -#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ - -/* Bit fields for GPCRC DATABYTEREV */ -#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ -#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ - -/** @} End of group EFR32MG24_GPCRC_BitFields */ -/** @} End of group EFR32MG24_GPCRC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_GPCRC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_GPCRC_H +#define EFR32MG24_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_GPCRC GPCRC + * @{ + * @brief EFR32MG24 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32MG24_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_GPCRC + * @{ + * @defgroup EFR32MG24_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32MG24_GPCRC_BitFields */ +/** @} End of group EFR32MG24_GPCRC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_GPCRC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h index df8d784..c97f329 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio.h @@ -1,2632 +1,2632 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 GPIO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_GPIO_H -#define EFR32MG24_GPIO_H -#define GPIO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ - -#include "efr32mg24_gpio_port.h" - -typedef struct { - __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ - __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_ACMPROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< CMU pin enable */ - __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ - __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ - __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ - __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ -} GPIO_CMUROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_EUSARTROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< FRC pin enable */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_FRCROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ - __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ - __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_I2CROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ - __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ - __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ - __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ - __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ - __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ - __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ - __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ - __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ - __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ - __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ - __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ - __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ - __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ - __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_KEYSCANROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ - __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ - __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_LETIMERROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ - __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ - __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ - __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ - __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ - __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ - __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ - __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ - __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ - __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ - __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ - __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ - __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ - __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DINROUTE; /**< DIN port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_MODEMROUTE_TypeDef; - -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ - __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ -} GPIO_PCNTROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ - __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ - __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ - __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ - __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ - __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ - __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ - __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ - __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ - __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ - __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ - __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ - __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ - __IOM uint32_t ASYNCH12ROUTE; /**< ASYNCH12 port/pin select */ - __IOM uint32_t ASYNCH13ROUTE; /**< ASYNCH13 port/pin select */ - __IOM uint32_t ASYNCH14ROUTE; /**< ASYNCH14 port/pin select */ - __IOM uint32_t ASYNCH15ROUTE; /**< ASYNCH15 port/pin select */ - __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ - __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ - __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ - __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_PRSROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< RAC pin enable */ - __IOM uint32_t LNAENROUTE; /**< LNAEN port/pin select */ - __IOM uint32_t PAENROUTE; /**< PAEN port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_RACROUTE_TypeDef; - -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ -} GPIO_SYXOROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ - __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ - __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ - __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ - __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ - __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ - __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_TIMERROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_USARTROUTE_TypeDef; - -typedef struct { - __IM uint32_t IPVERSION; /**< main */ - uint32_t RESERVED0[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P[4U]; /**< */ - uint32_t RESERVED1[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ - uint32_t RESERVED3[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ - uint32_t RESERVED4[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED5[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ - uint32_t RESERVED9[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keypad DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ - GPIO_RACROUTE_TypeDef RACROUTE; /**< rac DBUS config registers */ - uint32_t RESERVED10[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED11[560U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< main */ - uint32_t RESERVED12[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_SET[4U]; /**< */ - uint32_t RESERVED13[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED14[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ - uint32_t RESERVED16[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED17[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ - uint32_t RESERVED19[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ - uint32_t RESERVED21[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keypad DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ - GPIO_RACROUTE_TypeDef RACROUTE_SET; /**< rac DBUS config registers */ - uint32_t RESERVED22[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED23[560U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< main */ - uint32_t RESERVED24[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_CLR[4U]; /**< */ - uint32_t RESERVED25[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ - uint32_t RESERVED28[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ - uint32_t RESERVED31[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ - uint32_t RESERVED32[2U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keypad DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ - GPIO_RACROUTE_TypeDef RACROUTE_CLR; /**< rac DBUS config registers */ - uint32_t RESERVED34[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED35[560U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< main */ - uint32_t RESERVED36[11U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_TGL[4U]; /**< */ - uint32_t RESERVED37[132U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - uint32_t RESERVED38[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ - uint32_t RESERVED39[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ - uint32_t RESERVED40[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED41[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED42[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ - uint32_t RESERVED43[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ - uint32_t RESERVED44[2U]; /**< Reserved for future use */ - GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ - GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ - uint32_t RESERVED45[4U]; /**< Reserved for future use */ - GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ - GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keypad DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ - GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ - GPIO_RACROUTE_TypeDef RACROUTE_TGL; /**< rac DBUS config registers */ - uint32_t RESERVED46[23U]; /**< Reserved for future use */ - GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ -} GPIO_TypeDef; - -/* Bit fields for GPIO IPVERSION */ -#define _GPIO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ -#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ -#define GPIO_PORTA 0x00000000UL /**< PORTA index */ -#define GPIO_PORTB 0x00000001UL /**< PORTB index */ -#define GPIO_PORTC 0x00000002UL /**< PORTC index */ -#define GPIO_PORTD 0x00000003UL /**< PORTD index */ - -/* Bit fields for GPIO LOCK */ -#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ -#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ - -/* Bit fields for GPIO GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ - -/* Bit fields for GPIO ABUSALLOC */ -#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_VDAC1CH0 (_GPIO_ABUSALLOC_AODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_VDAC1CH1 (_GPIO_ABUSALLOC_AODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ - -/* Bit fields for GPIO BBUSALLOC */ -#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_VDAC1CH0 (_GPIO_BBUSALLOC_BODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_VDAC1CH1 (_GPIO_BBUSALLOC_BODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ - -/* Bit fields for GPIO CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ - -/* Bit fields for GPIO EXTIPSELL */ -#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ - -/* Bit fields for GPIO EXTIPSELH */ -#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ - -/* Bit fields for GPIO EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ - -/* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ - -/* Bit fields for GPIO EXTIRISE */ -#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ -#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ - -/* Bit fields for GPIO EXTIFALL */ -#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ -#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ - -/* Bit fields for GPIO IF */ -#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ -#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ -#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ -#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ - -/* Bit fields for GPIO IEN */ -#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ -#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ - -/* Bit fields for GPIO EM4WUEN */ -#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ -#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ - -/* Bit fields for GPIO EM4WUPOL */ -#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ -#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ - -/* Bit fields for GPIO DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ - -/* Bit fields for GPIO TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ - -/* Bit fields for GPIO_ACMP ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ -#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ -#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ -#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ - -/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ -#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ - -/* Bit fields for GPIO_CMU ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ - -/* Bit fields for GPIO_CMU CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ - -/* Bit fields for GPIO_EUSART ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ -#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ -#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ -#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ -#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ - -/* Bit fields for GPIO_EUSART CSROUTE */ -#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ -#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ -#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ -#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ - -/* Bit fields for GPIO_EUSART CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ -#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ -#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ -#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ - -/* Bit fields for GPIO_EUSART RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ -#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ -#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ -#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ - -/* Bit fields for GPIO_EUSART RXROUTE */ -#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ -#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ -#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ -#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ - -/* Bit fields for GPIO_EUSART SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ -#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ -#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ -#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ - -/* Bit fields for GPIO_EUSART TXROUTE */ -#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ -#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ -#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ -#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ - -/* Bit fields for GPIO_FRC ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ - -/* Bit fields for GPIO_FRC DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ - -/* Bit fields for GPIO_FRC DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ -#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ - -/* Bit fields for GPIO_FRC DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ - -/* Bit fields for GPIO_I2C ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ - -/* Bit fields for GPIO_I2C SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ - -/* Bit fields for GPIO_I2C SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ - -/* Bit fields for GPIO_KEYSCAN ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ -#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ -#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ -#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ -#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ -#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ -#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ -#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ -#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ -#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ -#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ -#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ - -/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ -#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ - -/* Bit fields for GPIO_LETIMER ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ - -/* Bit fields for GPIO_LETIMER OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ - -/* Bit fields for GPIO_LETIMER OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ - -/* Bit fields for GPIO_MODEM ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ - -/* Bit fields for GPIO_MODEM ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ -#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ - -/* Bit fields for GPIO_MODEM ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ -#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ - -/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ - -/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ - -/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ - -/* Bit fields for GPIO_MODEM DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ -#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ - -/* Bit fields for GPIO_MODEM DINROUTE */ -#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ -#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ - -/* Bit fields for GPIO_MODEM DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ -#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ - -/* Bit fields for GPIO_PCNT S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ -#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ -#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ -#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ - -/* Bit fields for GPIO_PCNT S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ -#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ -#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ -#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ - -/* Bit fields for GPIO_PRS ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_MASK 0x000FFFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH12PEN (0x1UL << 12) /**< ASYNCH12 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_SHIFT 12 /**< Shift value for GPIO_ASYNCH12PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_MASK 0x1000UL /**< Bit mask for GPIO_ASYNCH12PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH13PEN (0x1UL << 13) /**< ASYNCH13 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_SHIFT 13 /**< Shift value for GPIO_ASYNCH13PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_MASK 0x2000UL /**< Bit mask for GPIO_ASYNCH13PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH14PEN (0x1UL << 14) /**< ASYNCH14 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_SHIFT 14 /**< Shift value for GPIO_ASYNCH14PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_MASK 0x4000UL /**< Bit mask for GPIO_ASYNCH14PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH15PEN (0x1UL << 15) /**< ASYNCH15 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_SHIFT 15 /**< Shift value for GPIO_ASYNCH15PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_MASK 0x8000UL /**< Bit mask for GPIO_ASYNCH15PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 16) /**< SYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 16 /**< Shift value for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x10000UL /**< Bit mask for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 17) /**< SYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 17 /**< Shift value for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x20000UL /**< Bit mask for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 18) /**< SYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 18 /**< Shift value for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x40000UL /**< Bit mask for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 19) /**< SYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 19 /**< Shift value for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x80000UL /**< Bit mask for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ - -/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH12ROUTE */ -#define _GPIO_PRS_ASYNCH12ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH12ROUTE */ -#define _GPIO_PRS_ASYNCH12ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH12ROUTE */ -#define _GPIO_PRS_ASYNCH12ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH12ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ -#define GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ -#define _GPIO_PRS_ASYNCH12ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH12ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ -#define GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH13ROUTE */ -#define _GPIO_PRS_ASYNCH13ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH13ROUTE */ -#define _GPIO_PRS_ASYNCH13ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH13ROUTE */ -#define _GPIO_PRS_ASYNCH13ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH13ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ -#define GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ -#define _GPIO_PRS_ASYNCH13ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH13ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ -#define GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH14ROUTE */ -#define _GPIO_PRS_ASYNCH14ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH14ROUTE */ -#define _GPIO_PRS_ASYNCH14ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH14ROUTE */ -#define _GPIO_PRS_ASYNCH14ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH14ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ -#define GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ -#define _GPIO_PRS_ASYNCH14ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH14ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ -#define GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH15ROUTE */ -#define _GPIO_PRS_ASYNCH15ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH15ROUTE */ -#define _GPIO_PRS_ASYNCH15ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH15ROUTE */ -#define _GPIO_PRS_ASYNCH15ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH15ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ -#define GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ -#define _GPIO_PRS_ASYNCH15ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH15ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ -#define GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ - -/* Bit fields for GPIO_RAC ROUTEEN */ -#define _GPIO_RAC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_ROUTEEN */ -#define _GPIO_RAC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_RAC_ROUTEEN */ -#define GPIO_RAC_ROUTEEN_LNAENPEN (0x1UL << 0) /**< LNAEN pin enable control bit */ -#define _GPIO_RAC_ROUTEEN_LNAENPEN_SHIFT 0 /**< Shift value for GPIO_LNAENPEN */ -#define _GPIO_RAC_ROUTEEN_LNAENPEN_MASK 0x1UL /**< Bit mask for GPIO_LNAENPEN */ -#define _GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ -#define GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ -#define GPIO_RAC_ROUTEEN_PAENPEN (0x1UL << 1) /**< PAEN pin enable control bit */ -#define _GPIO_RAC_ROUTEEN_PAENPEN_SHIFT 1 /**< Shift value for GPIO_PAENPEN */ -#define _GPIO_RAC_ROUTEEN_PAENPEN_MASK 0x2UL /**< Bit mask for GPIO_PAENPEN */ -#define _GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ -#define GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ - -/* Bit fields for GPIO_RAC LNAENROUTE */ -#define _GPIO_RAC_LNAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_LNAENROUTE */ -#define _GPIO_RAC_LNAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_LNAENROUTE */ -#define _GPIO_RAC_LNAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_RAC_LNAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_RAC_LNAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ -#define GPIO_RAC_LNAENROUTE_PORT_DEFAULT (_GPIO_RAC_LNAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ -#define _GPIO_RAC_LNAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_RAC_LNAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_RAC_LNAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ -#define GPIO_RAC_LNAENROUTE_PIN_DEFAULT (_GPIO_RAC_LNAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ - -/* Bit fields for GPIO_RAC PAENROUTE */ -#define _GPIO_RAC_PAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_PAENROUTE */ -#define _GPIO_RAC_PAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_PAENROUTE */ -#define _GPIO_RAC_PAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_RAC_PAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_RAC_PAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ -#define GPIO_RAC_PAENROUTE_PORT_DEFAULT (_GPIO_RAC_PAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ -#define _GPIO_RAC_PAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_RAC_PAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_RAC_PAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ -#define GPIO_RAC_PAENROUTE_PIN_DEFAULT (_GPIO_RAC_PAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ - -/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ -#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ - -/* Bit fields for GPIO_TIMER ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ - -/* Bit fields for GPIO_TIMER CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ -#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ - -/* Bit fields for GPIO_TIMER CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ -#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ - -/* Bit fields for GPIO_TIMER CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ -#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ - -/* Bit fields for GPIO_USART ROUTEEN */ -#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ -#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ - -/* Bit fields for GPIO_USART CSROUTE */ -#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ - -/* Bit fields for GPIO_USART CTSROUTE */ -#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ -#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ - -/* Bit fields for GPIO_USART RTSROUTE */ -#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ -#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ - -/* Bit fields for GPIO_USART RXROUTE */ -#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ - -/* Bit fields for GPIO_USART CLKROUTE */ -#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ -#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ - -/* Bit fields for GPIO_USART TXROUTE */ -#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -/** @} End of group Parts */ - -#endif // EFR32MG24_GPIO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_GPIO_H +#define EFR32MG24_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32mg24_gpio_port.h" + +typedef struct { + __IOM uint32_t ROUTEEN; /**< ACMP0 pin enable */ + __IOM uint32_t ACMPOUTROUTE; /**< ACMPOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_ACMPROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< EUSART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t SCLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUSARTROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< KEYSCAN pin enable */ + __IOM uint32_t COLOUT0ROUTE; /**< COLOUT0 port/pin select */ + __IOM uint32_t COLOUT1ROUTE; /**< COLOUT1 port/pin select */ + __IOM uint32_t COLOUT2ROUTE; /**< COLOUT2 port/pin select */ + __IOM uint32_t COLOUT3ROUTE; /**< COLOUT3 port/pin select */ + __IOM uint32_t COLOUT4ROUTE; /**< COLOUT4 port/pin select */ + __IOM uint32_t COLOUT5ROUTE; /**< COLOUT5 port/pin select */ + __IOM uint32_t COLOUT6ROUTE; /**< COLOUT6 port/pin select */ + __IOM uint32_t COLOUT7ROUTE; /**< COLOUT7 port/pin select */ + __IOM uint32_t ROWSENSE0ROUTE; /**< ROWSENSE0 port/pin select */ + __IOM uint32_t ROWSENSE1ROUTE; /**< ROWSENSE1 port/pin select */ + __IOM uint32_t ROWSENSE2ROUTE; /**< ROWSENSE2 port/pin select */ + __IOM uint32_t ROWSENSE3ROUTE; /**< ROWSENSE3 port/pin select */ + __IOM uint32_t ROWSENSE4ROUTE; /**< ROWSENSE4 port/pin select */ + __IOM uint32_t ROWSENSE5ROUTE; /**< ROWSENSE5 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_KEYSCANROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t S0INROUTE; /**< S0IN port/pin select */ + __IOM uint32_t S1INROUTE; /**< S1IN port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_PCNTROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t ASYNCH12ROUTE; /**< ASYNCH12 port/pin select */ + __IOM uint32_t ASYNCH13ROUTE; /**< ASYNCH13 port/pin select */ + __IOM uint32_t ASYNCH14ROUTE; /**< ASYNCH14 port/pin select */ + __IOM uint32_t ASYNCH15ROUTE; /**< ASYNCH15 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< RAC pin enable */ + __IOM uint32_t LNAENROUTE; /**< LNAEN port/pin select */ + __IOM uint32_t PAENROUTE; /**< PAEN port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_RACROUTE_TypeDef; + +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTREQINASYNCROUTE; /**< BUFOUTREQINASYNC port/pin select */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} GPIO_SYXOROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct { + __IM uint32_t IPVERSION; /**< main */ + uint32_t RESERVED0[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED1[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED4[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED5[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + uint32_t RESERVED9[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE; /**< rac DBUS config registers */ + uint32_t RESERVED10[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED11[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< main */ + uint32_t RESERVED12[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED13[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED16[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED17[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_SET[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_SET[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_SET; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_SET[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_SET; /**< rac DBUS config registers */ + uint32_t RESERVED22[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_SET[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED23[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< main */ + uint32_t RESERVED24[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED25[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED28[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED31[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_CLR[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_CLR[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_CLR; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_CLR[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_CLR; /**< rac DBUS config registers */ + uint32_t RESERVED34[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_CLR[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[1U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED35[560U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< main */ + uint32_t RESERVED36[11U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED37[132U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED38[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED39[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED40[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + GPIO_ACMPROUTE_TypeDef ACMPROUTE_TGL[2U]; /**< acmp0 DBUS config registers */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + uint32_t RESERVED45[4U]; /**< Reserved for future use */ + GPIO_EUSARTROUTE_TypeDef EUSARTROUTE_TGL[2U]; /**< eusart0 DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_KEYSCANROUTE_TypeDef KEYSCANROUTE_TGL; /**< keypad DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL; /**< letimer DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PCNTROUTE_TypeDef PCNTROUTE_TGL[1U]; /**< pcnt0 DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_RACROUTE_TypeDef RACROUTE_TGL; /**< rac DBUS config registers */ + uint32_t RESERVED46[23U]; /**< Reserved for future use */ + GPIO_SYXOROUTE_TypeDef SYXOROUTE_TGL[1U]; /**< syxo0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[1U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +/* Bit fields for GPIO IPVERSION */ +#define _GPIO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPIO_IPVERSION */ +#define _GPIO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_IPVERSION_IPVERSION_DEFAULT (_GPIO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IPVERSION */ +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP0 (_GPIO_ABUSALLOC_AEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ACMP1 (_GPIO_ABUSALLOC_AEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 (_GPIO_ABUSALLOC_AEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP0 (_GPIO_ABUSALLOC_AEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ACMP1 (_GPIO_ABUSALLOC_AEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 (_GPIO_ABUSALLOC_AEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP0 (_GPIO_ABUSALLOC_AODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ACMP1 (_GPIO_ABUSALLOC_AODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC0CH0 (_GPIO_ABUSALLOC_AODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_VDAC1CH0 (_GPIO_ABUSALLOC_AODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP0 (_GPIO_ABUSALLOC_AODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ACMP1 (_GPIO_ABUSALLOC_AODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC0CH1 (_GPIO_ABUSALLOC_AODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_VDAC1CH1 (_GPIO_ABUSALLOC_AODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP0 (_GPIO_BBUSALLOC_BEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ACMP1 (_GPIO_BBUSALLOC_BEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 (_GPIO_BBUSALLOC_BEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP0 (_GPIO_BBUSALLOC_BEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ACMP1 (_GPIO_BBUSALLOC_BEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 (_GPIO_BBUSALLOC_BEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP0 (_GPIO_BBUSALLOC_BODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ACMP1 (_GPIO_BBUSALLOC_BODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC0CH0 (_GPIO_BBUSALLOC_BODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_VDAC1CH0 (_GPIO_BBUSALLOC_BODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP0 (_GPIO_BBUSALLOC_BODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ACMP1 (_GPIO_BBUSALLOC_BODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC0CH1 (_GPIO_BBUSALLOC_BODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_VDAC1CH1 (_GPIO_BBUSALLOC_BODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP0 << 0) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN0_ACMP1 << 0) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDEVEN0_VDAC1CH0 << 0) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP0 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP0 << 8) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ACMP1 (_GPIO_CDBUSALLOC_CDEVEN1_ACMP1 << 8) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC0CH1 << 8) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDEVEN1_VDAC1CH1 << 8) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 0x00000004UL /**< Mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 0x00000005UL /**< Mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP0 (_GPIO_CDBUSALLOC_CDODD0_ACMP0 << 16) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ACMP1 (_GPIO_CDBUSALLOC_CDODD0_ACMP1 << 16) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC0CH0 << 16) /**< Shifted mode VDAC0CH0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 (_GPIO_CDBUSALLOC_CDODD0_VDAC1CH0 << 16) /**< Shifted mode VDAC1CH0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP0 0x00000002UL /**< Mode ACMP0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ACMP1 0x00000003UL /**< Mode ACMP1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 0x00000004UL /**< Mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 0x00000005UL /**< Mode VDAC1CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP0 (_GPIO_CDBUSALLOC_CDODD1_ACMP0 << 24) /**< Shifted mode ACMP0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ACMP1 (_GPIO_CDBUSALLOC_CDODD1_ACMP1 << 24) /**< Shifted mode ACMP1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC0CH1 << 24) /**< Shifted mode VDAC0CH1 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 (_GPIO_CDBUSALLOC_CDODD1_VDAC1CH1 << 24) /**< Shifted mode VDAC1CH1 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN0 << 0) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN1 << 0) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN2 << 0) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_PIN3 << 0) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN0 << 4) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN1 << 4) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN2 << 4) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_PIN3 << 4) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN0 << 8) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN1 << 8) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN2 << 8) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_PIN3 << 8) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN0 << 12) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN1 << 12) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN2 << 12) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_PIN3 << 12) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN0 << 16) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN1 << 16) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN2 << 16) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_PIN3 << 16) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN0 << 20) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN1 << 20) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN2 << 20) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_PIN3 << 20) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN0 << 24) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN1 << 24) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN2 << 24) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_PIN3 << 24) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 0x00000000UL /**< Mode PIN0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 0x00000001UL /**< Mode PIN1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 0x00000002UL /**< Mode PIN2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 0x00000003UL /**< Mode PIN3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN0 << 28) /**< Shifted mode PIN0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN1 << 28) /**< Shifted mode PIN1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN2 << 28) /**< Shifted mode PIN2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_PIN3 << 28) /**< Shifted mode PIN3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN8 << 0) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN9 << 0) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN10 << 0) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_PIN11 << 0) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN8 << 4) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN9 << 4) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN10 << 4) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_PIN11 << 4) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN8 << 8) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN9 << 8) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN10 << 8) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_PIN11 << 8) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 0x00000000UL /**< Mode PIN8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 0x00000001UL /**< Mode PIN9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 0x00000002UL /**< Mode PIN10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 0x00000003UL /**< Mode PIN11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN8 << 12) /**< Shifted mode PIN8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN9 << 12) /**< Shifted mode PIN9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN10 << 12) /**< Shifted mode PIN10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_PIN11 << 12) /**< Shifted mode PIN11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x0000003FUL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN (0x1UL << 3) /**< Trace Data1 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_SHIFT 3 /**< Shift value for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_MASK 0x8UL /**< Bit mask for GPIO_TRACEDATA1PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA1PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN (0x1UL << 4) /**< Trace Data2 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_SHIFT 4 /**< Shift value for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_MASK 0x10UL /**< Bit mask for GPIO_TRACEDATA2PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA2PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN (0x1UL << 5) /**< Trace Data3 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_SHIFT 5 /**< Shift value for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_MASK 0x20UL /**< Bit mask for GPIO_TRACEDATA3PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA3PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_ACMP ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ROUTEEN */ +#define _GPIO_ACMP_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN (0x1UL << 0) /**< ACMPOUT pin enable control bit */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_SHIFT 0 /**< Shift value for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_MASK 0x1UL /**< Bit mask for GPIO_ACMPOUTPEN */ +#define _GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ROUTEEN */ +#define GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT (_GPIO_ACMP_ROUTEEN_ACMPOUTPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ROUTEEN */ + +/* Bit fields for GPIO_ACMP ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_ACMP_ACMPOUTROUTE */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE */ +#define GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT (_GPIO_ACMP_ACMPOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ACMP_ACMPOUTROUTE*/ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_EUSART ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_ROUTEEN */ +#define _GPIO_EUSART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_SCLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_SHIFT 3 /**< Shift value for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK 0x8UL /**< Bit mask for GPIO_SCLKPEN */ +#define _GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_SCLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ +#define GPIO_EUSART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_ROUTEEN */ +#define GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUSART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EUSART_ROUTEEN*/ + +/* Bit fields for GPIO_EUSART CSROUTE */ +#define _GPIO_EUSART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CSROUTE */ +#define _GPIO_EUSART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PORT_DEFAULT (_GPIO_EUSART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ +#define _GPIO_EUSART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CSROUTE */ +#define GPIO_EUSART_CSROUTE_PIN_DEFAULT (_GPIO_EUSART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CSROUTE*/ + +/* Bit fields for GPIO_EUSART CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_CTSROUTE */ +#define _GPIO_EUSART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PORT_DEFAULT (_GPIO_EUSART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ +#define _GPIO_EUSART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_CTSROUTE */ +#define GPIO_EUSART_CTSROUTE_PIN_DEFAULT (_GPIO_EUSART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_CTSROUTE*/ + +/* Bit fields for GPIO_EUSART RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RTSROUTE */ +#define _GPIO_EUSART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PORT_DEFAULT (_GPIO_EUSART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ +#define _GPIO_EUSART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RTSROUTE */ +#define GPIO_EUSART_RTSROUTE_PIN_DEFAULT (_GPIO_EUSART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RTSROUTE*/ + +/* Bit fields for GPIO_EUSART RXROUTE */ +#define _GPIO_EUSART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_RXROUTE */ +#define _GPIO_EUSART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PORT_DEFAULT (_GPIO_EUSART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ +#define _GPIO_EUSART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_RXROUTE */ +#define GPIO_EUSART_RXROUTE_PIN_DEFAULT (_GPIO_EUSART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_RXROUTE*/ + +/* Bit fields for GPIO_EUSART SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_SCLKROUTE */ +#define _GPIO_EUSART_SCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_SCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PORT_DEFAULT (_GPIO_EUSART_SCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ +#define _GPIO_EUSART_SCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_SCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_SCLKROUTE */ +#define GPIO_EUSART_SCLKROUTE_PIN_DEFAULT (_GPIO_EUSART_SCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_SCLKROUTE*/ + +/* Bit fields for GPIO_EUSART TXROUTE */ +#define _GPIO_EUSART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUSART_TXROUTE */ +#define _GPIO_EUSART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUSART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PORT_DEFAULT (_GPIO_EUSART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ +#define _GPIO_EUSART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUSART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUSART_TXROUTE */ +#define GPIO_EUSART_TXROUTE_PIN_DEFAULT (_GPIO_EUSART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUSART_TXROUTE*/ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_KEYSCAN ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROUTEEN */ +#define _GPIO_KEYSCAN_ROUTEEN_MASK 0x000000FFUL /**< Mask for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN (0x1UL << 0) /**< COLOUT0 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_SHIFT 0 /**< Shift value for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_COLOUT0PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN (0x1UL << 1) /**< COLOUT1 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_SHIFT 1 /**< Shift value for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_COLOUT1PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN (0x1UL << 2) /**< COLOUT2 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_SHIFT 2 /**< Shift value for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_COLOUT2PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN (0x1UL << 3) /**< COLOUT3 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_SHIFT 3 /**< Shift value for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_MASK 0x8UL /**< Bit mask for GPIO_COLOUT3PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN (0x1UL << 4) /**< COLOUT4 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_SHIFT 4 /**< Shift value for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_MASK 0x10UL /**< Bit mask for GPIO_COLOUT4PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN (0x1UL << 5) /**< COLOUT5 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_SHIFT 5 /**< Shift value for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_MASK 0x20UL /**< Bit mask for GPIO_COLOUT5PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN (0x1UL << 6) /**< COLOUT6 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_SHIFT 6 /**< Shift value for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_MASK 0x40UL /**< Bit mask for GPIO_COLOUT6PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN (0x1UL << 7) /**< COLOUT7 pin enable control bit */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_SHIFT 7 /**< Shift value for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_MASK 0x80UL /**< Bit mask for GPIO_COLOUT7PEN */ +#define _GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROUTEEN */ +#define GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT (_GPIO_KEYSCAN_ROUTEEN_COLOUT7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROUTEEN*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE */ +#define GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE */ +#define GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE */ +#define GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE */ +#define GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE */ +#define GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE */ +#define GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT5ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE */ +#define GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT6ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE */ +#define GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_COLOUT7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_COLOUT7ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE0ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE0ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE1ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE1ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE2ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE2ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE3ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE3ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE4ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE4ROUTE*/ + +/* Bit fields for GPIO_KEYSCAN ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_KEYSCAN_ROWSENSE5ROUTE */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ +#define GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT (_GPIO_KEYSCAN_ROWSENSE5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_KEYSCAN_ROWSENSE5ROUTE*/ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PCNT S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S0INROUTE */ +#define _GPIO_PCNT_S0INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S0INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PORT_DEFAULT (_GPIO_PCNT_S0INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ +#define _GPIO_PCNT_S0INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S0INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S0INROUTE */ +#define GPIO_PCNT_S0INROUTE_PIN_DEFAULT (_GPIO_PCNT_S0INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S0INROUTE*/ + +/* Bit fields for GPIO_PCNT S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PCNT_S1INROUTE */ +#define _GPIO_PCNT_S1INROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PCNT_S1INROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PORT_DEFAULT (_GPIO_PCNT_S1INROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ +#define _GPIO_PCNT_S1INROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PCNT_S1INROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PCNT_S1INROUTE */ +#define GPIO_PCNT_S1INROUTE_PIN_DEFAULT (_GPIO_PCNT_S1INROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PCNT_S1INROUTE*/ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x000FFFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN (0x1UL << 12) /**< ASYNCH12 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_SHIFT 12 /**< Shift value for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_MASK 0x1000UL /**< Bit mask for GPIO_ASYNCH12PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH12PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN (0x1UL << 13) /**< ASYNCH13 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_SHIFT 13 /**< Shift value for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_MASK 0x2000UL /**< Bit mask for GPIO_ASYNCH13PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH13PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN (0x1UL << 14) /**< ASYNCH14 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_SHIFT 14 /**< Shift value for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_MASK 0x4000UL /**< Bit mask for GPIO_ASYNCH14PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH14PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN (0x1UL << 15) /**< ASYNCH15 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_SHIFT 15 /**< Shift value for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_MASK 0x8000UL /**< Bit mask for GPIO_ASYNCH15PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH15PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 16) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 16 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x10000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 17) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 17 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x20000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 18) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 18 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x40000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 19) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 19 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x80000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH12ROUTE */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE */ +#define GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH12ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH12ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH13ROUTE */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE */ +#define GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH13ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH13ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH14ROUTE */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE */ +#define GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH14ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH14ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH15ROUTE */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE */ +#define GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH15ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH15ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_RAC ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_ROUTEEN */ +#define _GPIO_RAC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN (0x1UL << 0) /**< LNAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_SHIFT 0 /**< Shift value for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_MASK 0x1UL /**< Bit mask for GPIO_LNAENPEN */ +#define _GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_LNAENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN (0x1UL << 1) /**< PAEN pin enable control bit */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_SHIFT 1 /**< Shift value for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_MASK 0x2UL /**< Bit mask for GPIO_PAENPEN */ +#define _GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_ROUTEEN */ +#define GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT (_GPIO_RAC_ROUTEEN_PAENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_RAC_ROUTEEN */ + +/* Bit fields for GPIO_RAC LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_LNAENROUTE */ +#define _GPIO_RAC_LNAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_LNAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PORT_DEFAULT (_GPIO_RAC_LNAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ +#define _GPIO_RAC_LNAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_LNAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_LNAENROUTE */ +#define GPIO_RAC_LNAENROUTE_PIN_DEFAULT (_GPIO_RAC_LNAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_LNAENROUTE*/ + +/* Bit fields for GPIO_RAC PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_RAC_PAENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PORT_DEFAULT (_GPIO_RAC_PAENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define _GPIO_RAC_PAENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_RAC_PAENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_RAC_PAENROUTE */ +#define GPIO_RAC_PAENROUTE_PIN_DEFAULT (_GPIO_RAC_PAENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_RAC_PAENROUTE */ + +/* Bit fields for GPIO_SYXO BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_MASK 0x000F0003UL /**< Mask for GPIO_SYXO_BUFOUTREQINASYNCROUTE */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ +#define GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT (_GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_SYXO_BUFOUTREQINASYNCROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // EFR32MG24_GPIO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h index 3177d5b..4db9069 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_gpio_port.h @@ -1,457 +1,457 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 GPIO Port register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef GPIO_PORT_H -#define GPIO_PORT_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @brief EFR32MG24 GPIO PORT - *****************************************************************************/ -typedef struct { - __IOM uint32_t CTRL; /**< Port control */ - __IOM uint32_t MODEL; /**< mode low */ - uint32_t RESERVED0[1]; /**< Reserved for future use */ - __IOM uint32_t MODEH; /**< mode high */ - __IOM uint32_t DOUT; /**< data out */ - __IM uint32_t DIN; /**< data in */ - uint32_t RESERVED1[6]; /**< Reserved for future use */ -} GPIO_PORT_TypeDef; - -/* Bit fields for GPIO_P CTRL */ -#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ -#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ -#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ - -/* Bit fields for GPIO_P MODEL */ -#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ - -/* Bit fields for GPIO_P MODEH */ -#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MASK 0x000000FFUL /**< Mask for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ - -/* Bit fields for GPIO_P DOUT */ -#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_MASK 0x000003FFUL /**< Mask for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_MASK 0x3FFUL /**< Bit mask for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ -#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ - -/* Bit fields for GPIO_P DIN */ -#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ -#define _GPIO_P_DIN_MASK 0x000003FFUL /**< Mask for GPIO_P_DIN */ -#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_MASK 0x3FFUL /**< Bit mask for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ -#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ -/** @} End of group Parts */ - -#endif // GPIO_PORT_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32MG24 GPIO PORT + *****************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x000000FFUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define _GPIO_P_MODEH_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEH_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_DEFAULT (_GPIO_P_MODEH_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_DISABLED (_GPIO_P_MODEH_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUT (_GPIO_P_MODEH_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULL (_GPIO_P_MODEH_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_INPUTPULLFILTER (_GPIO_P_MODEH_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_PUSHPULL (_GPIO_P_MODEH_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_PUSHPULLALT (_GPIO_P_MODEH_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDOR (_GPIO_P_MODEH_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDAND (_GPIO_P_MODEH_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDFILTER (_GPIO_P_MODEH_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALT (_GPIO_P_MODEH_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000003FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x3FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000003FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x3FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h index 8e54f9f..297d2fb 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfrco.h @@ -1,226 +1,226 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 HFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_HFRCO_H -#define EFR32MG24_HFRCO_H -#define HFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_HFRCO HFRCO - * @{ - * @brief EFR32MG24 HFRCO Register Declaration. - *****************************************************************************/ - -/** HFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t CTRL; /**< Ctrl Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED1[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t CTRL_SET; /**< Ctrl Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED3[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED5[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ -} HFRCO_TypeDef; -/** @} End of group EFR32MG24_HFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_HFRCO - * @{ - * @defgroup EFR32MG24_HFRCO_BitFields HFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for HFRCO IPVERSION */ -#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ -#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ - -/* Bit fields for HFRCO CTRL */ -#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ -#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ -#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ -#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ -#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ - -/* Bit fields for HFRCO CAL */ -#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ -#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ -#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ -#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ -#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ - -/* Bit fields for HFRCO STATUS */ -#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ -#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ -#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ -#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ -#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ - -/* Bit fields for HFRCO IF */ -#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ -#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ -#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ -#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ - -/* Bit fields for HFRCO IEN */ -#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ -#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ -#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ -#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ -#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ - -/* Bit fields for HFRCO LOCK */ -#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ -#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ - -/** @} End of group EFR32MG24_HFRCO_BitFields */ -/** @} End of group EFR32MG24_HFRCO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_HFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_HFRCO_H +#define EFR32MG24_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_HFRCO HFRCO + * @{ + * @brief EFR32MG24 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32MG24_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_HFRCO + * @{ + * @defgroup EFR32MG24_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000007UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND (0x1UL << 2) /**< EM23 On-demand */ +#define _HFRCO_CTRL_EM23ONDEMAND_SHIFT 2 /**< Shift value for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_MASK 0x4UL /**< Bit mask for HFRCO_EM23ONDEMAND */ +#define _HFRCO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_EM23ONDEMAND_DEFAULT (_HFRCO_CTRL_EM23ONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32MG24_HFRCO_BitFields */ +/** @} End of group EFR32MG24_HFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_HFRCO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h index 10f2971..7aeff5b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_hfxo.h @@ -1,801 +1,801 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 HFXO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_HFXO_H -#define EFR32MG24_HFXO_H -#define HFXO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_HFXO HFXO - * @{ - * @brief EFR32MG24 HFXO Register Declaration. - *****************************************************************************/ - -/** HFXO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Control Register */ - uint32_t RESERVED3[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED6[5U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED8[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - uint32_t RESERVED12[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED15[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED17[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - uint32_t RESERVED21[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ - uint32_t RESERVED22[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED24[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED26[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ - __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - uint32_t RESERVED30[5U]; /**< Reserved for future use */ - __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ - __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ -} HFXO_TypeDef; -/** @} End of group EFR32MG24_HFXO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_HFXO - * @{ - * @defgroup EFR32MG24_HFXO_BitFields HFXO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for HFXO IPVERSION */ -#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ -#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ - -/* Bit fields for HFXO XTALCFG */ -#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ - -/* Bit fields for HFXO XTALCTRL */ -#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ - -/* Bit fields for HFXO XTALCTRL1 */ -#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ -#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ -#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ - -/* Bit fields for HFXO CFG */ -#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ -#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ -#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ -#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ -#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ -#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ -#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ -#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ -#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ - -/* Bit fields for HFXO CTRL */ -#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ -#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ -#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ -#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ -#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ -#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ -#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ -#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ -#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ -#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ -#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ -#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ -#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ -#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ -#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ -#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ -#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ -#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ -#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ -#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ - -/* Bit fields for HFXO BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ -#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ -#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ - -/* Bit fields for HFXO BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ -#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ -#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ -#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ -#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ -#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ -#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ - -/* Bit fields for HFXO CMD */ -#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ -#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ -#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ - -/* Bit fields for HFXO STATUS */ -#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ -#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ -#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ -#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ -#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ -#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ -#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ -#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ -#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ -#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ -#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ -#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ -#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ -#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ -#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ -#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ -#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ - -/* Bit fields for HFXO IF */ -#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ -#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ -#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ - -/* Bit fields for HFXO IEN */ -#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ -#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ -#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ -#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ -#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ -#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ -#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ -#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ -#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ -#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ -#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ -#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ -#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ -#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ -#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ -#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ -#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ -#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ -#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ -#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ - -/* Bit fields for HFXO LOCK */ -#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ -#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ - -/** @} End of group EFR32MG24_HFXO_BitFields */ -/** @} End of group EFR32MG24_HFXO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_HFXO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_HFXO_H +#define EFR32MG24_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_HFXO HFXO + * @{ + * @brief EFR32MG24 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED3[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL; /**< BUFOUT Control Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_SET; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED12[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_SET; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_SET; /**< BUFOUT Control Register */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_CLR; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED21[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_CLR; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_CLR; /**< BUFOUT Control Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + __IOM uint32_t XTALCTRL1_TGL; /**< BUFOUT Crystal Control Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED30[5U]; /**< Reserved for future use */ + __IOM uint32_t BUFOUTTRIM_TGL; /**< BUFOUT Trim Configuration Register */ + __IOM uint32_t BUFOUTCTRL_TGL; /**< BUFOUT Control Register */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32MG24_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_HFXO + * @{ + * @defgroup EFR32MG24_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x0BB00820UL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000020UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4US 0x00000000UL /**< Mode T4US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000001UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000003UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000004UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000005UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000006UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000007UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000008UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000009UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x0000000AUL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000BUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000DUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000EUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000FUL /**< Mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4US << 20) /**< Shifted mode T4US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x033C3C3CUL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO XTALCTRL1 */ +#define _HFXO_XTALCTRL1_RESETVALUE 0x0000003CUL /**< Default value for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_MASK 0x000000FFUL /**< Mask for HFXO_XTALCTRL1 */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_SHIFT 0 /**< Shift value for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_MASK 0xFFUL /**< Bit mask for HFXO_CTUNEXIBUFOUTANA */ +#define _HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT 0x0000003CUL /**< Mode DEFAULT for HFXO_XTALCTRL1 */ +#define HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT (_HFXO_XTALCTRL1_CTUNEXIBUFOUTANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL1 */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xB000000FUL /**< Mask for HFXO_CFG */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x3UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLKPKDET 0x00000002UL /**< Mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLKPKDET (_HFXO_CFG_MODE_EXTCLKPKDET << 0) /**< Shifted mode EXTCLKPKDET for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT (0x1UL << 28) /**< Force Low Frequency Timeout */ +#define _HFXO_CFG_FORCELFTIMEOUT_SHIFT 28 /**< Shift value for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_MASK 0x10000000UL /**< Bit mask for HFXO_FORCELFTIMEOUT */ +#define _HFXO_CFG_FORCELFTIMEOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_FORCELFTIMEOUT_DEFAULT (_HFXO_CFG_FORCELFTIMEOUT_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x07000040UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x8707FF7DUL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE (0x1UL << 0) /**< Freeze BUFOUT Controls */ +#define _HFXO_CTRL_BUFOUTFREEZE_SHIFT 0 /**< Shift value for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_MASK 0x1UL /**< Bit mask for HFXO_BUFOUTFREEZE */ +#define _HFXO_CTRL_BUFOUTFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_BUFOUTFREEZE_DEFAULT (_HFXO_CTRL_BUFOUTFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND (0x1UL << 3) /**< On-demand During EM23 */ +#define _HFXO_CTRL_EM23ONDEMAND_SHIFT 3 /**< Shift value for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_MASK 0x8UL /**< Bit mask for HFXO_EM23ONDEMAND */ +#define _HFXO_CTRL_EM23ONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_EM23ONDEMAND_DEFAULT (_HFXO_CTRL_EM23ONDEMAND_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX (0x1UL << 6) /**< Force Tuning Cap to Max Value */ +#define _HFXO_CTRL_FORCECTUNEMAX_SHIFT 6 /**< Shift value for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_MASK 0x40UL /**< Bit mask for HFXO_FORCECTUNEMAX */ +#define _HFXO_CTRL_FORCECTUNEMAX_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCECTUNEMAX_DEFAULT (_HFXO_CTRL_FORCECTUNEMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_SHIFT 8 /**< Shift value for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_MASK 0xF00UL /**< Bit mask for HFXO_PRSSTATUSSEL0 */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL0_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_DISABLED (_HFXO_CTRL_PRSSTATUSSEL0_DISABLED << 8) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_ENS (_HFXO_CTRL_PRSSTATUSSEL0_ENS << 8) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL0_COREBIASOPTRDY << 8) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_RDY (_HFXO_CTRL_PRSSTATUSSEL0_RDY << 8) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL0_PRSRDY << 8) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTRDY << 8) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_HWREQ (_HFXO_CTRL_PRSSTATUSSEL0_HWREQ << 8) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_PRSHWREQ << 8) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL0_BUFOUTHWREQ << 8) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_SHIFT 12 /**< Shift value for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_MASK 0xF000UL /**< Bit mask for HFXO_PRSSTATUSSEL1 */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_ENS 0x00000001UL /**< Mode ENS for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY 0x00000002UL /**< Mode COREBIASOPTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_RDY 0x00000003UL /**< Mode RDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSRDY 0x00000004UL /**< Mode PRSRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY 0x00000005UL /**< Mode BUFOUTRDY for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_HWREQ 0x00000008UL /**< Mode HWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ 0x00000009UL /**< Mode PRSHWREQ for HFXO_CTRL */ +#define _HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ 0x0000000AUL /**< Mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DEFAULT (_HFXO_CTRL_PRSSTATUSSEL1_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_DISABLED (_HFXO_CTRL_PRSSTATUSSEL1_DISABLED << 12) /**< Shifted mode DISABLED for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_ENS (_HFXO_CTRL_PRSSTATUSSEL1_ENS << 12) /**< Shifted mode ENS for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY (_HFXO_CTRL_PRSSTATUSSEL1_COREBIASOPTRDY << 12) /**< Shifted mode COREBIASOPTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_RDY (_HFXO_CTRL_PRSSTATUSSEL1_RDY << 12) /**< Shifted mode RDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSRDY (_HFXO_CTRL_PRSSTATUSSEL1_PRSRDY << 12) /**< Shifted mode PRSRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTRDY << 12) /**< Shifted mode BUFOUTRDY for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_HWREQ (_HFXO_CTRL_PRSSTATUSSEL1_HWREQ << 12) /**< Shifted mode HWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_PRSHWREQ << 12) /**< Shifted mode PRSHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ (_HFXO_CTRL_PRSSTATUSSEL1_BUFOUTHWREQ << 12) /**< Shifted mode BUFOUTHWREQ for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 16) /**< Force Digital Clock Request */ +#define _HFXO_CTRL_FORCEEN_SHIFT 16 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x10000UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS (0x1UL << 17) /**< Force PRS Oscillator Request */ +#define _HFXO_CTRL_FORCEENPRS_SHIFT 17 /**< Shift value for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_MASK 0x20000UL /**< Bit mask for HFXO_FORCEENPRS */ +#define _HFXO_CTRL_FORCEENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENPRS_DEFAULT (_HFXO_CTRL_FORCEENPRS_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT (0x1UL << 18) /**< Force BUFOUT Request */ +#define _HFXO_CTRL_FORCEENBUFOUT_SHIFT 18 /**< Shift value for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_MASK 0x40000UL /**< Bit mask for HFXO_FORCEENBUFOUT */ +#define _HFXO_CTRL_FORCEENBUFOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEENBUFOUT_DEFAULT (_HFXO_CTRL_FORCEENBUFOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 24) /**< Disable On-demand For Digital Clock */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 24 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x1000000UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS (0x1UL << 25) /**< Disable On-demand For PRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_SHIFT 25 /**< Shift value for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_MASK 0x2000000UL /**< Bit mask for HFXO_DISONDEMANDPRS */ +#define _HFXO_CTRL_DISONDEMANDPRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDPRS_DEFAULT (_HFXO_CTRL_DISONDEMANDPRS_DEFAULT << 25) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT (0x1UL << 26) /**< Disable On-demand For BUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_SHIFT 26 /**< Shift value for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_MASK 0x4000000UL /**< Bit mask for HFXO_DISONDEMANDBUFOUT */ +#define _HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT (_HFXO_CTRL_DISONDEMANDBUFOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_CTRL */ + +/* Bit fields for HFXO BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_RESETVALUE 0x00000008UL /**< Default value for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_MASK 0x0000000FUL /**< Mask for HFXO_BUFOUTTRIM */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT 0 /**< Shift value for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK 0xFUL /**< Bit mask for HFXO_VTRTRIMANA */ +#define _HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFXO_BUFOUTTRIM */ +#define HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT (_HFXO_BUFOUTTRIM_VTRTRIMANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTTRIM */ + +/* Bit fields for HFXO BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_RESETVALUE 0x00643C15UL /**< Default value for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_MASK 0xC0FFFFFFUL /**< Mask for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_SHIFT 0 /**< Shift value for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_MASK 0xFUL /**< Bit mask for HFXO_XOUTBIASANA */ +#define _HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT 0x00000005UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_SHIFT 4 /**< Shift value for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_MASK 0xF0UL /**< Bit mask for HFXO_XOUTCFANA */ +#define _HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTCFANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_SHIFT 8 /**< Shift value for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_MASK 0xF00UL /**< Bit mask for HFXO_XOUTGMANA */ +#define _HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT 0x0000000CUL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT (_HFXO_BUFOUTCTRL_XOUTGMANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_SHIFT 12 /**< Shift value for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_MASK 0xF000UL /**< Bit mask for HFXO_PEAKDETTHRESANA */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV 0x00000000UL /**< Mode V105MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV 0x00000001UL /**< Mode V132MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV 0x00000002UL /**< Mode V157MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV 0x00000003UL /**< Mode V184MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV 0x00000004UL /**< Mode V210MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV 0x00000005UL /**< Mode V236MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV 0x00000006UL /**< Mode V262MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV 0x00000007UL /**< Mode V289MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV 0x00000008UL /**< Mode V315MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV 0x00000009UL /**< Mode V341MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV 0x0000000AUL /**< Mode V367MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV 0x0000000BUL /**< Mode V394MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV 0x0000000CUL /**< Mode V420MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV 0x0000000DUL /**< Mode V446MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV 0x0000000EUL /**< Mode V472MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV 0x0000000FUL /**< Mode V499MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V105MV << 12) /**< Shifted mode V105MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V132MV << 12) /**< Shifted mode V132MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V157MV << 12) /**< Shifted mode V157MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V184MV << 12) /**< Shifted mode V184MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V210MV << 12) /**< Shifted mode V210MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V236MV << 12) /**< Shifted mode V236MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V262MV << 12) /**< Shifted mode V262MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V289MV << 12) /**< Shifted mode V289MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V315MV << 12) /**< Shifted mode V315MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V341MV << 12) /**< Shifted mode V341MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V367MV << 12) /**< Shifted mode V367MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V394MV << 12) /**< Shifted mode V394MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V420MV << 12) /**< Shifted mode V420MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V446MV << 12) /**< Shifted mode V446MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V472MV << 12) /**< Shifted mode V472MV for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV (_HFXO_BUFOUTCTRL_PEAKDETTHRESANA_V499MV << 12) /**< Shifted mode V499MV for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_SHIFT 16 /**< Shift value for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_MASK 0xF0000UL /**< Bit mask for HFXO_TIMEOUTCTUNE */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US 0x00000000UL /**< Mode T2US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US 0x00000001UL /**< Mode T5US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US 0x00000002UL /**< Mode T10US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US 0x00000003UL /**< Mode T16US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US 0x00000004UL /**< Mode T21US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US 0x00000005UL /**< Mode T26US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US 0x00000006UL /**< Mode T31US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US 0x00000007UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US 0x00000008UL /**< Mode T52US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US 0x00000009UL /**< Mode T63US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US 0x0000000AUL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US 0x0000000BUL /**< Mode T104US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US 0x0000000CUL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US 0x0000000DUL /**< Mode T313US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US 0x0000000EUL /**< Mode T521US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US 0x0000000FUL /**< Mode T938US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T2US << 16) /**< Shifted mode T2US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T5US << 16) /**< Shifted mode T5US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T10US << 16) /**< Shifted mode T10US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T16US << 16) /**< Shifted mode T16US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T21US << 16) /**< Shifted mode T21US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T26US << 16) /**< Shifted mode T26US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T31US << 16) /**< Shifted mode T31US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T42US << 16) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T52US << 16) /**< Shifted mode T52US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T63US << 16) /**< Shifted mode T63US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T83US << 16) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T104US << 16) /**< Shifted mode T104US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T208US << 16) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T313US << 16) /**< Shifted mode T313US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T521US << 16) /**< Shifted mode T521US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US (_HFXO_BUFOUTCTRL_TIMEOUTCTUNE_T938US << 16) /**< Shifted mode T938US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTARTUP */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT 0x00000006UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US 0x00000000UL /**< Mode T42US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US 0x00000001UL /**< Mode T83US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US 0x00000002UL /**< Mode T108US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US 0x00000003UL /**< Mode T133US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US 0x00000004UL /**< Mode T158US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US 0x00000005UL /**< Mode T183US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US 0x00000006UL /**< Mode T208US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US 0x00000007UL /**< Mode T233US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US 0x00000008UL /**< Mode T258US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US 0x00000009UL /**< Mode T283US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US 0x0000000AUL /**< Mode T333US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US 0x0000000BUL /**< Mode T375US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US 0x0000000CUL /**< Mode T417US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US 0x0000000DUL /**< Mode T458US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US 0x0000000EUL /**< Mode T500US for HFXO_BUFOUTCTRL */ +#define _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US 0x0000000FUL /**< Mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US << 20) /**< Shifted mode T42US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US << 20) /**< Shifted mode T83US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US << 20) /**< Shifted mode T108US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US << 20) /**< Shifted mode T133US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US << 20) /**< Shifted mode T158US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US << 20) /**< Shifted mode T183US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US << 20) /**< Shifted mode T208US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US << 20) /**< Shifted mode T233US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US << 20) /**< Shifted mode T258US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US << 20) /**< Shifted mode T283US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US << 20) /**< Shifted mode T333US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US << 20) /**< Shifted mode T375US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US << 20) /**< Shifted mode T417US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US << 20) /**< Shifted mode T458US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US << 20) /**< Shifted mode T500US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US (_HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US << 20) /**< Shifted mode T667US for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY (0x1UL << 31) /**< Minimum Startup Delay */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT 31 /**< Shift value for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK 0x80000000UL /**< Bit mask for HFXO_MINIMUMSTARTUPDELAY */ +#define _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_BUFOUTCTRL */ +#define HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT (_HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_BUFOUTCTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000001UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC03F800FUL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY (0x1UL << 2) /**< PRS Ready Status */ +#define _HFXO_STATUS_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_STATUS_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSRDY_DEFAULT (_HFXO_STATUS_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Status */ +#define _HFXO_STATUS_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_STATUS_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTRDY_DEFAULT (_HFXO_STATUS_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT Frozen */ +#define _HFXO_STATUS_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_STATUS_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTFROZEN_DEFAULT (_HFXO_STATUS_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Digital Clock */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ (0x1UL << 20) /**< Oscillator Requested by PRS Request */ +#define _HFXO_STATUS_PRSHWREQ_SHIFT 20 /**< Shift value for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_MASK 0x100000UL /**< Bit mask for HFXO_PRSHWREQ */ +#define _HFXO_STATUS_PRSHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_PRSHWREQ_DEFAULT (_HFXO_STATUS_PRSHWREQ_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ (0x1UL << 21) /**< Oscillator Requested by BUFOUT Request */ +#define _HFXO_STATUS_BUFOUTHWREQ_SHIFT 21 /**< Shift value for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTHWREQ */ +#define _HFXO_STATUS_BUFOUTHWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_BUFOUTHWREQ_DEFAULT (_HFXO_STATUS_BUFOUTHWREQ_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY (0x1UL << 30) /**< Sync Busy */ +#define _HFXO_STATUS_SYNCBUSY_SHIFT 30 /**< Shift value for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_MASK 0x40000000UL /**< Bit mask for HFXO_SYNCBUSY */ +#define _HFXO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_SYNCBUSY_DEFAULT (_HFXO_STATUS_SYNCBUSY_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xF830800FUL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IF_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IF_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSRDY_DEFAULT (_HFXO_IF_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IF_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IF_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTRDY_DEFAULT (_HFXO_IF_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IF_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IF_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFROZEN_DEFAULT (_HFXO_IF_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IF_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IF_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_PRSERR_DEFAULT (_HFXO_IF_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IF_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IF_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTERR_DEFAULT (_HFXO_IF_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IF_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IF_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTFREEZEERR_DEFAULT (_HFXO_IF_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IF_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IF_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_BUFOUTDNSERR_DEFAULT (_HFXO_IF_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IF_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IF_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_LFTIMEOUTERR_DEFAULT (_HFXO_IF_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xF830800FUL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Digital Clock Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY (0x1UL << 2) /**< PRS Ready Interrupt */ +#define _HFXO_IEN_PRSRDY_SHIFT 2 /**< Shift value for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_MASK 0x4UL /**< Bit mask for HFXO_PRSRDY */ +#define _HFXO_IEN_PRSRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSRDY_DEFAULT (_HFXO_IEN_PRSRDY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY (0x1UL << 3) /**< BUFOUT Ready Interrupt */ +#define _HFXO_IEN_BUFOUTRDY_SHIFT 3 /**< Shift value for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_MASK 0x8UL /**< Bit mask for HFXO_BUFOUTRDY */ +#define _HFXO_IEN_BUFOUTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTRDY_DEFAULT (_HFXO_IEN_BUFOUTRDY_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN (0x1UL << 15) /**< BUFOUT FROZEN Interrupt */ +#define _HFXO_IEN_BUFOUTFROZEN_SHIFT 15 /**< Shift value for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_MASK 0x8000UL /**< Bit mask for HFXO_BUFOUTFROZEN */ +#define _HFXO_IEN_BUFOUTFROZEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFROZEN_DEFAULT (_HFXO_IEN_BUFOUTFROZEN_DEFAULT << 15) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR (0x1UL << 20) /**< PRS Requset Error Interrupt */ +#define _HFXO_IEN_PRSERR_SHIFT 20 /**< Shift value for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_MASK 0x100000UL /**< Bit mask for HFXO_PRSERR */ +#define _HFXO_IEN_PRSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_PRSERR_DEFAULT (_HFXO_IEN_PRSERR_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR (0x1UL << 21) /**< BUFOUT Request Error Interrupt */ +#define _HFXO_IEN_BUFOUTERR_SHIFT 21 /**< Shift value for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_MASK 0x200000UL /**< Bit mask for HFXO_BUFOUTERR */ +#define _HFXO_IEN_BUFOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTERR_DEFAULT (_HFXO_IEN_BUFOUTERR_DEFAULT << 21) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR (0x1UL << 27) /**< BUFOUT Freeze Error Interrupt */ +#define _HFXO_IEN_BUFOUTFREEZEERR_SHIFT 27 /**< Shift value for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_MASK 0x8000000UL /**< Bit mask for HFXO_BUFOUTFREEZEERR */ +#define _HFXO_IEN_BUFOUTFREEZEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTFREEZEERR_DEFAULT (_HFXO_IEN_BUFOUTFREEZEERR_DEFAULT << 27) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR (0x1UL << 28) /**< BUFOUT Did Not Start Error Interrupt */ +#define _HFXO_IEN_BUFOUTDNSERR_SHIFT 28 /**< Shift value for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_MASK 0x10000000UL /**< Bit mask for HFXO_BUFOUTDNSERR */ +#define _HFXO_IEN_BUFOUTDNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_BUFOUTDNSERR_DEFAULT (_HFXO_IEN_BUFOUTDNSERR_DEFAULT << 28) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR (0x1UL << 30) /**< Low Frequency Timeout Error Interrupt */ +#define _HFXO_IEN_LFTIMEOUTERR_SHIFT 30 /**< Shift value for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_MASK 0x40000000UL /**< Bit mask for HFXO_LFTIMEOUTERR */ +#define _HFXO_IEN_LFTIMEOUTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_LFTIMEOUTERR_DEFAULT (_HFXO_IEN_LFTIMEOUTERR_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32MG24_HFXO_BitFields */ +/** @} End of group EFR32MG24_HFXO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_HFXO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h index 5ca0065..06f6934 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_i2c.h @@ -1,744 +1,744 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 I2C register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_I2C_H -#define EFR32MG24_I2C_H -#define I2C_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_I2C I2C - * @{ - * @brief EFR32MG24 I2C Register Declaration. - *****************************************************************************/ - -/** I2C Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP VERSION Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATE; /**< State Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Division Register */ - __IOM uint32_t SADDR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATE_SET; /**< State Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ - __IOM uint32_t SADDR_SET; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATE_CLR; /**< State Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ - __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATE_TGL; /**< State Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ - __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ -} I2C_TypeDef; -/** @} End of group EFR32MG24_I2C */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_I2C - * @{ - * @defgroup EFR32MG24_I2C_BitFields I2C Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for I2C IPVERSION */ -#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ -#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ -#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ - -/* Bit fields for I2C EN */ -#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ -#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ -#define I2C_EN_EN (0x1UL << 0) /**< module enable */ -#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ -#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ -#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ -#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ -#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ -#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ -#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ -#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ - -/* Bit fields for I2C CTRL */ -#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ -#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ -#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ -#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ -#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ -#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ -#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ -#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ -#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ -#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ -#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ -#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ -#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ -#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ -#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ -#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ -#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ -#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ -#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ -#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ -#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ -#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ -#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ -#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ -#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ -#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ -#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ -#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ -#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ -#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ -#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ - -/* Bit fields for I2C CMD */ -#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ -#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ -#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ -#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ -#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ -#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ -#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ -#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ -#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ -#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ -#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ -#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ -#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ -#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ -#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ -#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ -#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ -#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ -#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ -#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ -#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ - -/* Bit fields for I2C STATE */ -#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ -#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ -#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ -#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ -#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ -#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ -#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ -#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ -#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ -#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ -#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ -#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ -#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ -#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ -#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ -#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ -#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ -#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ -#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ -#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ -#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ -#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ -#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ -#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ -#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ -#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ -#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ -#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ -#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ - -/* Bit fields for I2C STATUS */ -#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ -#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ -#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ -#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ -#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ -#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ -#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ -#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ -#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ -#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ -#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ -#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ -#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ -#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ -#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ -#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ -#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ -#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ -#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ -#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ -#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ -#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ -#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ -#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ -#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ -#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ -#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ - -/* Bit fields for I2C CLKDIV */ -#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ -#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ -#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ -#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ -#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ - -/* Bit fields for I2C SADDR */ -#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ -#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ -#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ -#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ -#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ -#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ - -/* Bit fields for I2C SADDRMASK */ -#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ -#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ - -/* Bit fields for I2C RXDATA */ -#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ -#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ -#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ - -/* Bit fields for I2C RXDOUBLE */ -#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ - -/* Bit fields for I2C RXDATAP */ -#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ -#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ -#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ - -/* Bit fields for I2C RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ - -/* Bit fields for I2C TXDATA */ -#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ -#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ -#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ - -/* Bit fields for I2C TXDOUBLE */ -#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ - -/* Bit fields for I2C IF */ -#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ -#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ -#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ - -/* Bit fields for I2C IEN */ -#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ -#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ -#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ - -/** @} End of group EFR32MG24_I2C_BitFields */ -/** @} End of group EFR32MG24_I2C */ -/** @} End of group Parts */ - -#endif // EFR32MG24_I2C_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_I2C_H +#define EFR32MG24_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_I2C I2C + * @{ + * @brief EFR32MG24 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32MG24_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_I2C + * @{ + * @defgroup EFR32MG24_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32MG24_I2C_BitFields */ +/** @} End of group EFR32MG24_I2C */ +/** @} End of group Parts */ + +#endif // EFR32MG24_I2C_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h index 0adf097..9cbbe29 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_iadc.h @@ -1,1072 +1,1072 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 IADC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_IADC_H -#define EFR32MG24_IADC_H -#define IADC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_IADC IADC - * @{ - * @brief EFR32MG24 IADC Register Declaration. - *****************************************************************************/ - -/** IADC CFG Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG; /**< Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t SCALE; /**< Scaling */ - __IOM uint32_t SCHED; /**< Scheduling */ -} IADC_CFG_TypeDef; - -/** IADC SCANTABLE Register Group Declaration. */ -typedef struct { - __IOM uint32_t SCAN; /**< SCAN Entry */ -} IADC_SCANTABLE_TypeDef; - -/** IADC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CTRL; /**< Control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t TIMER; /**< Timer */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t MASKREQ; /**< Mask Request */ - __IM uint32_t STMASK; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER; /**< Trigger */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG[2U]; /**< CFG */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA; /**< Scan Data */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CTRL_SET; /**< Control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t TIMER_SET; /**< Timer */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t MASKREQ_SET; /**< Mask Request */ - __IM uint32_t STMASK_SET; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_SET; /**< Trigger */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ - uint32_t RESERVED11[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_SET; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_SET; /**< Scan Data */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CTRL_CLR; /**< Control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t TIMER_CLR; /**< Timer */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ - __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_CLR; /**< Trigger */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_CLR; /**< Scan Data */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CTRL_TGL; /**< Control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t TIMER_TGL; /**< Timer */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ - __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_TGL; /**< Trigger */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ - __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_TGL; /**< Scan Data */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ -} IADC_TypeDef; -/** @} End of group EFR32MG24_IADC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_IADC - * @{ - * @defgroup EFR32MG24_IADC_BitFields IADC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for IADC IPVERSION */ -#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ -#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ -#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ - -/* Bit fields for IADC EN */ -#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ -#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ -#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ -#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ -#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ -#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ -#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ -#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ -#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ -#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ -#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ -#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ -#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ - -/* Bit fields for IADC CTRL */ -#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ -#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ -#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ -#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ -#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ - -/* Bit fields for IADC CMD */ -#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ -#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ -#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ -#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ -#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ -#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ -#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ -#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ -#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ -#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ -#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ - -/* Bit fields for IADC TIMER */ -#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ -#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ -#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ -#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ - -/* Bit fields for IADC STATUS */ -#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ -#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ -#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ -#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ -#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ -#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ -#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ -#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ -#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ -#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ -#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ -#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ -#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ - -/* Bit fields for IADC MASKREQ */ -#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ -#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ - -/* Bit fields for IADC STMASK */ -#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ -#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ -#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ -#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ - -/* Bit fields for IADC CMPTHR */ -#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ -#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ - -/* Bit fields for IADC IF */ -#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ -#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ -#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ -#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ -#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ -#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ -#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ -#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ -#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ -#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ -#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ -#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ -#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ -#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ -#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ -#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ - -/* Bit fields for IADC IEN */ -#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ -#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ -#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ -#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ -#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ -#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ -#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ -#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ -#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ -#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ -#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ -#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ -#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ -#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ -#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ -#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ - -/* Bit fields for IADC TRIGGER */ -#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ -#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ -#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ -#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ -#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ - -/* Bit fields for IADC CFG */ -#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ -#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ -#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ -#define _IADC_CFG_ADCMODE_HIGHSPEED 0x00000001UL /**< Mode HIGHSPEED for IADC_CFG */ -#define _IADC_CFG_ADCMODE_HIGHACCURACY 0x00000002UL /**< Mode HIGHACCURACY for IADC_CFG */ -#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ -#define IADC_CFG_ADCMODE_HIGHSPEED (_IADC_CFG_ADCMODE_HIGHSPEED << 0) /**< Shifted mode HIGHSPEED for IADC_CFG */ -#define IADC_CFG_ADCMODE_HIGHACCURACY (_IADC_CFG_ADCMODE_HIGHACCURACY << 0) /**< Shifted mode HIGHACCURACY for IADC_CFG */ -#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ -#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ -#define _IADC_CFG_OSRHA_SHIFT 5 /**< Shift value for IADC_OSRHA */ -#define _IADC_CFG_OSRHA_MASK 0xE0UL /**< Bit mask for IADC_OSRHA */ -#define _IADC_CFG_OSRHA_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC16 0x00000000UL /**< Mode HIACC16 for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC32 0x00000001UL /**< Mode HIACC32 for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC64 0x00000002UL /**< Mode HIACC64 for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC92 0x00000003UL /**< Mode HIACC92 for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC128 0x00000004UL /**< Mode HIACC128 for IADC_CFG */ -#define _IADC_CFG_OSRHA_HIACC256 0x00000005UL /**< Mode HIACC256 for IADC_CFG */ -#define IADC_CFG_OSRHA_DEFAULT (_IADC_CFG_OSRHA_DEFAULT << 5) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC16 (_IADC_CFG_OSRHA_HIACC16 << 5) /**< Shifted mode HIACC16 for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC32 (_IADC_CFG_OSRHA_HIACC32 << 5) /**< Shifted mode HIACC32 for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC64 (_IADC_CFG_OSRHA_HIACC64 << 5) /**< Shifted mode HIACC64 for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC92 (_IADC_CFG_OSRHA_HIACC92 << 5) /**< Shifted mode HIACC92 for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC128 (_IADC_CFG_OSRHA_HIACC128 << 5) /**< Shifted mode HIACC128 for IADC_CFG */ -#define IADC_CFG_OSRHA_HIACC256 (_IADC_CFG_OSRHA_HIACC256 << 5) /**< Shifted mode HIACC256 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ -#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ -#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ -#define _IADC_CFG_REFSEL_VREF2P5 0x00000002UL /**< Mode VREF2P5 for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ -#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ -#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ -#define IADC_CFG_REFSEL_VREF2P5 (_IADC_CFG_REFSEL_VREF2P5 << 16) /**< Shifted mode VREF2P5 for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ -#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ -#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ - -/* Bit fields for IADC SCALE */ -#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ -#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ -#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ -#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ - -/* Bit fields for IADC SCHED */ -#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ -#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ -#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ -#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ - -/* Bit fields for IADC SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ - -/* Bit fields for IADC SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ -#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ - -/* Bit fields for IADC SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ -#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ - -/* Bit fields for IADC SINGLEDATA */ -#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ -#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ - -/* Bit fields for IADC SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ - -/* Bit fields for IADC SCANFIFODATA */ -#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ -#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ - -/* Bit fields for IADC SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ -#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ - -/* Bit fields for IADC SCANDATA */ -#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ -#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ -#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ -#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ - -/* Bit fields for IADC SINGLE */ -#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ -#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ -#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ -#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ - -/* Bit fields for IADC SCAN */ -#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ -#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ -#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ -#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ -#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ - -/** @} End of group EFR32MG24_IADC_BitFields */ -/** @} End of group EFR32MG24_IADC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_IADC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_IADC_H +#define EFR32MG24_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_IADC IADC + * @{ + * @brief EFR32MG24 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct { + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO DATA */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32MG24_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_IADC + * @{ + * @defgroup EFR32MG24_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000003UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ +#define IADC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _IADC_EN_DISABLING_SHIFT 1 /**< Shift value for IADC_DISABLING */ +#define _IADC_EN_DISABLING_MASK 0x2UL /**< Bit mask for IADC_DISABLING */ +#define _IADC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define IADC_EN_DISABLING_DEFAULT (_IADC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define _IADC_CFG_ADCMODE_HIGHSPEED 0x00000001UL /**< Mode HIGHSPEED for IADC_CFG */ +#define _IADC_CFG_ADCMODE_HIGHACCURACY 0x00000002UL /**< Mode HIGHACCURACY for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_HIGHSPEED (_IADC_CFG_ADCMODE_HIGHSPEED << 0) /**< Shifted mode HIGHSPEED for IADC_CFG */ +#define IADC_CFG_ADCMODE_HIGHACCURACY (_IADC_CFG_ADCMODE_HIGHACCURACY << 0) /**< Shifted mode HIGHACCURACY for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_OSRHA_SHIFT 5 /**< Shift value for IADC_OSRHA */ +#define _IADC_CFG_OSRHA_MASK 0xE0UL /**< Bit mask for IADC_OSRHA */ +#define _IADC_CFG_OSRHA_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC16 0x00000000UL /**< Mode HIACC16 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC32 0x00000001UL /**< Mode HIACC32 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC64 0x00000002UL /**< Mode HIACC64 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC92 0x00000003UL /**< Mode HIACC92 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC128 0x00000004UL /**< Mode HIACC128 for IADC_CFG */ +#define _IADC_CFG_OSRHA_HIACC256 0x00000005UL /**< Mode HIACC256 for IADC_CFG */ +#define IADC_CFG_OSRHA_DEFAULT (_IADC_CFG_OSRHA_DEFAULT << 5) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC16 (_IADC_CFG_OSRHA_HIACC16 << 5) /**< Shifted mode HIACC16 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC32 (_IADC_CFG_OSRHA_HIACC32 << 5) /**< Shifted mode HIACC32 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC64 (_IADC_CFG_OSRHA_HIACC64 << 5) /**< Shifted mode HIACC64 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC92 (_IADC_CFG_OSRHA_HIACC92 << 5) /**< Shifted mode HIACC92 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC128 (_IADC_CFG_OSRHA_HIACC128 << 5) /**< Shifted mode HIACC128 for IADC_CFG */ +#define IADC_CFG_OSRHA_HIACC256 (_IADC_CFG_OSRHA_HIACC256 << 5) /**< Shifted mode HIACC256 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF2P5 0x00000002UL /**< Mode VREF2P5 for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF2P5 (_IADC_CFG_REFSEL_VREF2P5 << 16) /**< Shifted mode VREF2P5 for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID5 (_IADC_SINGLEFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID6 (_IADC_SINGLEFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID7 (_IADC_SINGLEFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID8 (_IADC_SINGLEFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000017FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x70UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID5 0x00000004UL /**< Mode VALID5 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID6 0x00000005UL /**< Mode VALID6 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID7 0x00000006UL /**< Mode VALID7 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID8 0x00000007UL /**< Mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID5 (_IADC_SCANFIFOCFG_DVL_VALID5 << 4) /**< Shifted mode VALID5 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID6 (_IADC_SCANFIFOCFG_DVL_VALID6 << 4) /**< Shifted mode VALID6 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID7 (_IADC_SCANFIFOCFG_DVL_VALID7 << 4) /**< Shifted mode VALID7 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID8 (_IADC_SCANFIFOCFG_DVL_VALID8 << 4) /**< Shifted mode VALID8 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x0000000FUL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0xFUL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DAC1 (_IADC_SINGLE_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA1 (_IADC_SINGLE_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PADANA3 (_IADC_SINGLE_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DAC0 (_IADC_SINGLE_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA0 (_IADC_SINGLE_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PADANA2 (_IADC_SINGLE_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_DAC1 0x00000002UL /**< Mode DAC1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA1 0x00000004UL /**< Mode PADANA1 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PADANA3 0x00000005UL /**< Mode PADANA3 for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DAC1 (_IADC_SCAN_PORTNEG_DAC1 << 4) /**< Shifted mode DAC1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA1 (_IADC_SCAN_PORTNEG_PADANA1 << 4) /**< Shifted mode PADANA1 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PADANA3 (_IADC_SCAN_PORTNEG_PADANA3 << 4) /**< Shifted mode PADANA3 for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_DAC0 0x00000002UL /**< Mode DAC0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA0 0x00000004UL /**< Mode PADANA0 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PADANA2 0x00000005UL /**< Mode PADANA2 for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DAC0 (_IADC_SCAN_PORTPOS_DAC0 << 12) /**< Shifted mode DAC0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA0 (_IADC_SCAN_PORTPOS_PADANA0 << 12) /**< Shifted mode PADANA0 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PADANA2 (_IADC_SCAN_PORTPOS_PADANA2 << 12) /**< Shifted mode PADANA2 for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32MG24_IADC_BitFields */ +/** @} End of group EFR32MG24_IADC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_IADC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h index 4d41609..885764d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_icache.h @@ -1,248 +1,248 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 ICACHE register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_ICACHE_H -#define EFR32MG24_ICACHE_H -#define ICACHE_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_ICACHE ICACHE - * @{ - * @brief EFR32MG24 ICACHE Register Declaration. - *****************************************************************************/ - -/** ICACHE Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t PCHITS; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LPMODE; /**< Low Power Mode */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ -} ICACHE_TypeDef; -/** @} End of group EFR32MG24_ICACHE */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_ICACHE - * @{ - * @defgroup EFR32MG24_ICACHE_BitFields ICACHE Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for ICACHE IPVERSION */ -#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ -#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ - -/* Bit fields for ICACHE CTRL */ -#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ -#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ -#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ -#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ - -/* Bit fields for ICACHE PCHITS */ -#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ -#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ - -/* Bit fields for ICACHE PCMISSES */ -#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ -#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ - -/* Bit fields for ICACHE PCAHITS */ -#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ -#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ - -/* Bit fields for ICACHE STATUS */ -#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ -#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ -#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ - -/* Bit fields for ICACHE CMD */ -#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ -#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ -#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ -#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ -#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ - -/* Bit fields for ICACHE LPMODE */ -#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ - -/* Bit fields for ICACHE IF */ -#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ -#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ -#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ -#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ -#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ - -/* Bit fields for ICACHE IEN */ -#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ -#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ -#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ -#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ -#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ - -/** @} End of group EFR32MG24_ICACHE_BitFields */ -/** @} End of group EFR32MG24_ICACHE */ -/** @} End of group Parts */ - -#endif // EFR32MG24_ICACHE_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ICACHE_H +#define EFR32MG24_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ICACHE ICACHE + * @{ + * @brief EFR32MG24 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32MG24_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ICACHE + * @{ + * @defgroup EFR32MG24_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32MG24_ICACHE_BitFields */ +/** @} End of group EFR32MG24_ICACHE */ +/** @} End of group Parts */ + +#endif // EFR32MG24_ICACHE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h index b1ed299..1a19e40 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_keyscan.h @@ -1,386 +1,386 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 KEYSCAN register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_KEYSCAN_H -#define EFR32MG24_KEYSCAN_H -#define KEYSCAN_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_KEYSCAN KEYSCAN - * @{ - * @brief EFR32MG24 KEYSCAN Register Declaration. - *****************************************************************************/ - -/** KEYSCAN Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t DELAY; /**< Delay */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t DELAY_SET; /**< Delay */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t DELAY_CLR; /**< Delay */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t DELAY_TGL; /**< Delay */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ -} KEYSCAN_TypeDef; -/** @} End of group EFR32MG24_KEYSCAN */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_KEYSCAN - * @{ - * @defgroup EFR32MG24_KEYSCAN_BitFields KEYSCAN Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for KEYSCAN IPVERSION */ -#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ -#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ -#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ - -/* Bit fields for KEYSCAN EN */ -#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */ -#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */ -#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */ -#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */ -#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */ -#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ -#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */ -#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */ -#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */ -#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */ -#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */ -#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */ -#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */ -#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ -#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */ - -/* Bit fields for KEYSCAN SWRST */ -#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */ -#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */ -#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */ -#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */ -#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ -#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ -#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */ -#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */ -#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ -#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ - -/* Bit fields for KEYSCAN CFG */ -#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ -#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ -#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ -#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ -#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ -#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ -#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ -#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ -#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ -#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ -#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ - -/* Bit fields for KEYSCAN CMD */ -#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ -#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ -#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ -#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ -#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ -#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ -#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ - -/* Bit fields for KEYSCAN DELAY */ -#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ -#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ -#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ -#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ -#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */ -#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ - -/* Bit fields for KEYSCAN STATUS */ -#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ -#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ -#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ -#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ -#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ -#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ -#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ -#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ -#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ -#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ - -/* Bit fields for KEYSCAN IF */ -#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */ -#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */ -#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */ -#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ -#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ -#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */ -#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ -#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ -#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */ -#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ -#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ -#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */ -#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ -#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ -#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ -#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */ - -/* Bit fields for KEYSCAN IEN */ -#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */ -#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */ -#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */ -#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ -#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ -#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */ -#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ -#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ -#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */ -#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ -#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ -#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */ -#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ -#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ -#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ -#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ - -/** @} End of group EFR32MG24_KEYSCAN_BitFields */ -/** @} End of group EFR32MG24_KEYSCAN */ -/** @} End of group Parts */ - -#endif // EFR32MG24_KEYSCAN_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 KEYSCAN register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_KEYSCAN_H +#define EFR32MG24_KEYSCAN_H +#define KEYSCAN_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_KEYSCAN KEYSCAN + * @{ + * @brief EFR32MG24 KEYSCAN Register Declaration. + *****************************************************************************/ + +/** KEYSCAN Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t DELAY; /**< Delay */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t DELAY_SET; /**< Delay */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t DELAY_CLR; /**< Delay */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t DELAY_TGL; /**< Delay */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ +} KEYSCAN_TypeDef; +/** @} End of group EFR32MG24_KEYSCAN */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_KEYSCAN + * @{ + * @defgroup EFR32MG24_KEYSCAN_BitFields KEYSCAN Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for KEYSCAN IPVERSION */ +#define _KEYSCAN_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for KEYSCAN_IPVERSION */ +#define _KEYSCAN_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_IPVERSION */ +#define KEYSCAN_IPVERSION_IPVERSION_DEFAULT (_KEYSCAN_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IPVERSION */ + +/* Bit fields for KEYSCAN EN */ +#define _KEYSCAN_EN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_EN */ +#define _KEYSCAN_EN_MASK 0x00000003UL /**< Mask for KEYSCAN_EN */ +#define KEYSCAN_EN_EN (0x1UL << 0) /**< Enable */ +#define _KEYSCAN_EN_EN_SHIFT 0 /**< Shift value for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_MASK 0x1UL /**< Bit mask for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for KEYSCAN_EN */ +#define _KEYSCAN_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DEFAULT (_KEYSCAN_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_DISABLE (_KEYSCAN_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_EN_ENABLE (_KEYSCAN_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _KEYSCAN_EN_DISABLING_SHIFT 1 /**< Shift value for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_MASK 0x2UL /**< Bit mask for KEYSCAN_DISABLING */ +#define _KEYSCAN_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_EN */ +#define KEYSCAN_EN_DISABLING_DEFAULT (_KEYSCAN_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_EN */ + +/* Bit fields for KEYSCAN SWRST */ +#define _KEYSCAN_SWRST_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_MASK 0x00000003UL /**< Mask for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _KEYSCAN_SWRST_SWRST_SHIFT 0 /**< Shift value for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_MASK 0x1UL /**< Bit mask for KEYSCAN_SWRST */ +#define _KEYSCAN_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_SWRST_DEFAULT (_KEYSCAN_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _KEYSCAN_SWRST_RESETTING_SHIFT 1 /**< Shift value for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for KEYSCAN_RESETTING */ +#define _KEYSCAN_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_SWRST */ +#define KEYSCAN_SWRST_RESETTING_DEFAULT (_KEYSCAN_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_SWRST */ + +/* Bit fields for KEYSCAN CFG */ +#define _KEYSCAN_CFG_RESETVALUE 0x2501387FUL /**< Default value for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_MASK 0x7753FFFFUL /**< Mask for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_CLKDIV_SHIFT 0 /**< Shift value for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_MASK 0x3FFFFUL /**< Bit mask for KEYSCAN_CLKDIV */ +#define _KEYSCAN_CFG_CLKDIV_DEFAULT 0x0001387FUL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_CLKDIV_DEFAULT (_KEYSCAN_CFG_CLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS (0x1UL << 20) /**< Single Press */ +#define _KEYSCAN_CFG_SINGLEPRESS_SHIFT 20 /**< Shift value for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_MASK 0x100000UL /**< Bit mask for KEYSCAN_SINGLEPRESS */ +#define _KEYSCAN_CFG_SINGLEPRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS 0x00000000UL /**< Mode MULTIPRESS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS 0x00000001UL /**< Mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_DEFAULT (_KEYSCAN_CFG_SINGLEPRESS_DEFAULT << 20) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS (_KEYSCAN_CFG_SINGLEPRESS_MULTIPRESS << 20) /**< Shifted mode MULTIPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS (_KEYSCAN_CFG_SINGLEPRESS_SINGLEPRESS << 20) /**< Shifted mode SINGLEPRESS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART (0x1UL << 22) /**< Automatically Start */ +#define _KEYSCAN_CFG_AUTOSTART_SHIFT 22 /**< Shift value for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_MASK 0x400000UL /**< Bit mask for KEYSCAN_AUTOSTART */ +#define _KEYSCAN_CFG_AUTOSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS 0x00000000UL /**< Mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN 0x00000001UL /**< Mode AUTOSTARTEN for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_DEFAULT (_KEYSCAN_CFG_AUTOSTART_DEFAULT << 22) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTDIS << 22) /**< Shifted mode AUTOSTARTDIS for KEYSCAN_CFG */ +#define KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN (_KEYSCAN_CFG_AUTOSTART_AUTOSTARTEN << 22) /**< Shifted mode AUTOSTARTEN for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_SHIFT 24 /**< Shift value for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_MASK 0x7000000UL /**< Bit mask for KEYSCAN_NUMROWS */ +#define _KEYSCAN_CFG_NUMROWS_DEFAULT 0x00000005UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV1 0x00000000UL /**< Mode RSV1 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_RSV2 0x00000001UL /**< Mode RSV2 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW3 0x00000002UL /**< Mode ROW3 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW4 0x00000003UL /**< Mode ROW4 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW5 0x00000004UL /**< Mode ROW5 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMROWS_ROW6 0x00000005UL /**< Mode ROW6 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_DEFAULT (_KEYSCAN_CFG_NUMROWS_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV1 (_KEYSCAN_CFG_NUMROWS_RSV1 << 24) /**< Shifted mode RSV1 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_RSV2 (_KEYSCAN_CFG_NUMROWS_RSV2 << 24) /**< Shifted mode RSV2 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW3 (_KEYSCAN_CFG_NUMROWS_ROW3 << 24) /**< Shifted mode ROW3 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW4 (_KEYSCAN_CFG_NUMROWS_ROW4 << 24) /**< Shifted mode ROW4 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW5 (_KEYSCAN_CFG_NUMROWS_ROW5 << 24) /**< Shifted mode ROW5 for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMROWS_ROW6 (_KEYSCAN_CFG_NUMROWS_ROW6 << 24) /**< Shifted mode ROW6 for KEYSCAN_CFG */ +#define _KEYSCAN_CFG_NUMCOLS_SHIFT 28 /**< Shift value for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_MASK 0x70000000UL /**< Bit mask for KEYSCAN_NUMCOLS */ +#define _KEYSCAN_CFG_NUMCOLS_DEFAULT 0x00000002UL /**< Mode DEFAULT for KEYSCAN_CFG */ +#define KEYSCAN_CFG_NUMCOLS_DEFAULT (_KEYSCAN_CFG_NUMCOLS_DEFAULT << 28) /**< Shifted mode DEFAULT for KEYSCAN_CFG */ + +/* Bit fields for KEYSCAN CMD */ +#define _KEYSCAN_CMD_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_CMD */ +#define _KEYSCAN_CMD_MASK 0x00000003UL /**< Mask for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART (0x1UL << 0) /**< Keyscan Start */ +#define _KEYSCAN_CMD_KEYSCANSTART_SHIFT 0 /**< Shift value for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_MASK 0x1UL /**< Bit mask for KEYSCAN_KEYSCANSTART */ +#define _KEYSCAN_CMD_KEYSCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTART_DEFAULT (_KEYSCAN_CMD_KEYSCANSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP (0x1UL << 1) /**< Keyscan Stop */ +#define _KEYSCAN_CMD_KEYSCANSTOP_SHIFT 1 /**< Shift value for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_MASK 0x2UL /**< Bit mask for KEYSCAN_KEYSCANSTOP */ +#define _KEYSCAN_CMD_KEYSCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_CMD */ +#define KEYSCAN_CMD_KEYSCANSTOP_DEFAULT (_KEYSCAN_CMD_KEYSCANSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_CMD */ + +/* Bit fields for KEYSCAN DELAY */ +#define _KEYSCAN_DELAY_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_MASK 0x0F0F0F00UL /**< Mask for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SHIFT 8 /**< Shift value for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_MASK 0xF00UL /**< Bit mask for KEYSCAN_SCANDLY */ +#define _KEYSCAN_DELAY_SCANDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY2 0x00000000UL /**< Mode SCANDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY4 0x00000001UL /**< Mode SCANDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY6 0x00000002UL /**< Mode SCANDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY8 0x00000003UL /**< Mode SCANDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY10 0x00000004UL /**< Mode SCANDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY12 0x00000005UL /**< Mode SCANDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY14 0x00000006UL /**< Mode SCANDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY16 0x00000007UL /**< Mode SCANDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY18 0x00000008UL /**< Mode SCANDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY20 0x00000009UL /**< Mode SCANDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY22 0x0000000AUL /**< Mode SCANDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY24 0x0000000BUL /**< Mode SCANDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY26 0x0000000CUL /**< Mode SCANDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY28 0x0000000DUL /**< Mode SCANDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY30 0x0000000EUL /**< Mode SCANDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_SCANDLY_SCANDLY32 0x0000000FUL /**< Mode SCANDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_DEFAULT (_KEYSCAN_DELAY_SCANDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY2 (_KEYSCAN_DELAY_SCANDLY_SCANDLY2 << 8) /**< Shifted mode SCANDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY4 (_KEYSCAN_DELAY_SCANDLY_SCANDLY4 << 8) /**< Shifted mode SCANDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY6 (_KEYSCAN_DELAY_SCANDLY_SCANDLY6 << 8) /**< Shifted mode SCANDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY8 (_KEYSCAN_DELAY_SCANDLY_SCANDLY8 << 8) /**< Shifted mode SCANDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY10 (_KEYSCAN_DELAY_SCANDLY_SCANDLY10 << 8) /**< Shifted mode SCANDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY12 (_KEYSCAN_DELAY_SCANDLY_SCANDLY12 << 8) /**< Shifted mode SCANDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY14 (_KEYSCAN_DELAY_SCANDLY_SCANDLY14 << 8) /**< Shifted mode SCANDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY16 (_KEYSCAN_DELAY_SCANDLY_SCANDLY16 << 8) /**< Shifted mode SCANDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY18 (_KEYSCAN_DELAY_SCANDLY_SCANDLY18 << 8) /**< Shifted mode SCANDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY20 (_KEYSCAN_DELAY_SCANDLY_SCANDLY20 << 8) /**< Shifted mode SCANDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY22 (_KEYSCAN_DELAY_SCANDLY_SCANDLY22 << 8) /**< Shifted mode SCANDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY24 (_KEYSCAN_DELAY_SCANDLY_SCANDLY24 << 8) /**< Shifted mode SCANDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY26 (_KEYSCAN_DELAY_SCANDLY_SCANDLY26 << 8) /**< Shifted mode SCANDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY28 (_KEYSCAN_DELAY_SCANDLY_SCANDLY28 << 8) /**< Shifted mode SCANDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY30 (_KEYSCAN_DELAY_SCANDLY_SCANDLY30 << 8) /**< Shifted mode SCANDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_SCANDLY_SCANDLY32 (_KEYSCAN_DELAY_SCANDLY_SCANDLY32 << 8) /**< Shifted mode SCANDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_SHIFT 16 /**< Shift value for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_MASK 0xF0000UL /**< Bit mask for KEYSCAN_DEBDLY */ +#define _KEYSCAN_DELAY_DEBDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY2 0x00000000UL /**< Mode DEBDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY4 0x00000001UL /**< Mode DEBDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY6 0x00000002UL /**< Mode DEBDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY8 0x00000003UL /**< Mode DEBDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY10 0x00000004UL /**< Mode DEBDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY12 0x00000005UL /**< Mode DEBDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY14 0x00000006UL /**< Mode DEBDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY16 0x00000007UL /**< Mode DEBDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY18 0x00000008UL /**< Mode DEBDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY20 0x00000009UL /**< Mode DEBDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY22 0x0000000AUL /**< Mode DEBDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY24 0x0000000BUL /**< Mode DEBDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY26 0x0000000CUL /**< Mode DEBDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY28 0x0000000DUL /**< Mode DEBDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY30 0x0000000EUL /**< Mode DEBDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_DEBDLY_DEBDLY32 0x0000000FUL /**< Mode DEBDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEFAULT (_KEYSCAN_DELAY_DEBDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY2 (_KEYSCAN_DELAY_DEBDLY_DEBDLY2 << 16) /**< Shifted mode DEBDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY4 (_KEYSCAN_DELAY_DEBDLY_DEBDLY4 << 16) /**< Shifted mode DEBDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY6 (_KEYSCAN_DELAY_DEBDLY_DEBDLY6 << 16) /**< Shifted mode DEBDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY8 (_KEYSCAN_DELAY_DEBDLY_DEBDLY8 << 16) /**< Shifted mode DEBDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY10 (_KEYSCAN_DELAY_DEBDLY_DEBDLY10 << 16) /**< Shifted mode DEBDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY12 (_KEYSCAN_DELAY_DEBDLY_DEBDLY12 << 16) /**< Shifted mode DEBDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY14 (_KEYSCAN_DELAY_DEBDLY_DEBDLY14 << 16) /**< Shifted mode DEBDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY16 (_KEYSCAN_DELAY_DEBDLY_DEBDLY16 << 16) /**< Shifted mode DEBDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY18 (_KEYSCAN_DELAY_DEBDLY_DEBDLY18 << 16) /**< Shifted mode DEBDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY20 (_KEYSCAN_DELAY_DEBDLY_DEBDLY20 << 16) /**< Shifted mode DEBDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY22 (_KEYSCAN_DELAY_DEBDLY_DEBDLY22 << 16) /**< Shifted mode DEBDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY24 (_KEYSCAN_DELAY_DEBDLY_DEBDLY24 << 16) /**< Shifted mode DEBDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY26 (_KEYSCAN_DELAY_DEBDLY_DEBDLY26 << 16) /**< Shifted mode DEBDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY28 (_KEYSCAN_DELAY_DEBDLY_DEBDLY28 << 16) /**< Shifted mode DEBDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY30 (_KEYSCAN_DELAY_DEBDLY_DEBDLY30 << 16) /**< Shifted mode DEBDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_DEBDLY_DEBDLY32 (_KEYSCAN_DELAY_DEBDLY_DEBDLY32 << 16) /**< Shifted mode DEBDLY32 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_SHIFT 24 /**< Shift value for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_MASK 0xF000000UL /**< Bit mask for KEYSCAN_STABDLY */ +#define _KEYSCAN_DELAY_STABDLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY2 0x00000000UL /**< Mode STABDLY2 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY4 0x00000001UL /**< Mode STABDLY4 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY6 0x00000002UL /**< Mode STABDLY6 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY8 0x00000003UL /**< Mode STABDLY8 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY10 0x00000004UL /**< Mode STABDLY10 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY12 0x00000005UL /**< Mode STABDLY12 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY14 0x00000006UL /**< Mode STABDLY14 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY16 0x00000007UL /**< Mode STABDLY16 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY18 0x00000008UL /**< Mode STABDLY18 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY20 0x00000009UL /**< Mode STABDLY20 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY22 0x0000000AUL /**< Mode STABDLY22 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY24 0x0000000BUL /**< Mode STABDLY24 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY26 0x0000000CUL /**< Mode STABDLY26 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY28 0x0000000DUL /**< Mode STABDLY28 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY30 0x0000000EUL /**< Mode STABDLY30 for KEYSCAN_DELAY */ +#define _KEYSCAN_DELAY_STABDLY_STABDLY32 0x0000000FUL /**< Mode STABDLY32 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_DEFAULT (_KEYSCAN_DELAY_STABDLY_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY2 (_KEYSCAN_DELAY_STABDLY_STABDLY2 << 24) /**< Shifted mode STABDLY2 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY4 (_KEYSCAN_DELAY_STABDLY_STABDLY4 << 24) /**< Shifted mode STABDLY4 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY6 (_KEYSCAN_DELAY_STABDLY_STABDLY6 << 24) /**< Shifted mode STABDLY6 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY8 (_KEYSCAN_DELAY_STABDLY_STABDLY8 << 24) /**< Shifted mode STABDLY8 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY10 (_KEYSCAN_DELAY_STABDLY_STABDLY10 << 24) /**< Shifted mode STABDLY10 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY12 (_KEYSCAN_DELAY_STABDLY_STABDLY12 << 24) /**< Shifted mode STABDLY12 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY14 (_KEYSCAN_DELAY_STABDLY_STABDLY14 << 24) /**< Shifted mode STABDLY14 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY16 (_KEYSCAN_DELAY_STABDLY_STABDLY16 << 24) /**< Shifted mode STABDLY16 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY18 (_KEYSCAN_DELAY_STABDLY_STABDLY18 << 24) /**< Shifted mode STABDLY18 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY20 (_KEYSCAN_DELAY_STABDLY_STABDLY20 << 24) /**< Shifted mode STABDLY20 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY22 (_KEYSCAN_DELAY_STABDLY_STABDLY22 << 24) /**< Shifted mode STABDLY22 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY24 (_KEYSCAN_DELAY_STABDLY_STABDLY24 << 24) /**< Shifted mode STABDLY24 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY26 (_KEYSCAN_DELAY_STABDLY_STABDLY26 << 24) /**< Shifted mode STABDLY26 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY28 (_KEYSCAN_DELAY_STABDLY_STABDLY28 << 24) /**< Shifted mode STABDLY28 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY30 (_KEYSCAN_DELAY_STABDLY_STABDLY30 << 24) /**< Shifted mode STABDLY30 for KEYSCAN_DELAY */ +#define KEYSCAN_DELAY_STABDLY_STABDLY32 (_KEYSCAN_DELAY_STABDLY_STABDLY32 << 24) /**< Shifted mode STABDLY32 for KEYSCAN_DELAY */ + +/* Bit fields for KEYSCAN STATUS */ +#define _KEYSCAN_STATUS_RESETVALUE 0x40000000UL /**< Default value for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_MASK 0xC701003FUL /**< Mask for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_ROW_SHIFT 0 /**< Shift value for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_MASK 0x3FUL /**< Bit mask for KEYSCAN_ROW */ +#define _KEYSCAN_STATUS_ROW_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_ROW_DEFAULT (_KEYSCAN_STATUS_ROW_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING (0x1UL << 16) /**< Running */ +#define _KEYSCAN_STATUS_RUNNING_SHIFT 16 /**< Shift value for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_MASK 0x10000UL /**< Bit mask for KEYSCAN_RUNNING */ +#define _KEYSCAN_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_RUNNING_DEFAULT (_KEYSCAN_STATUS_RUNNING_DEFAULT << 16) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define _KEYSCAN_STATUS_COL_SHIFT 24 /**< Shift value for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_MASK 0x7000000UL /**< Bit mask for KEYSCAN_COL */ +#define _KEYSCAN_STATUS_COL_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_COL_DEFAULT (_KEYSCAN_STATUS_COL_DEFAULT << 24) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY (0x1UL << 30) /**< No Key pressed status */ +#define _KEYSCAN_STATUS_NOKEY_SHIFT 30 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_MASK 0x40000000UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_STATUS_NOKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_NOKEY_DEFAULT (_KEYSCAN_STATUS_NOKEY_DEFAULT << 30) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy */ +#define _KEYSCAN_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for KEYSCAN_SYNCBUSY */ +#define _KEYSCAN_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_STATUS */ +#define KEYSCAN_STATUS_SYNCBUSY_DEFAULT (_KEYSCAN_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for KEYSCAN_STATUS */ + +/* Bit fields for KEYSCAN IF */ +#define _KEYSCAN_IF_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IF */ +#define _KEYSCAN_IF_MASK 0x0000000FUL /**< Mask for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY (0x1UL << 0) /**< No key was pressed */ +#define _KEYSCAN_IF_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IF_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_NOKEY_DEFAULT (_KEYSCAN_IF_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY (0x1UL << 1) /**< A key was pressed */ +#define _KEYSCAN_IF_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IF_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_KEY_DEFAULT (_KEYSCAN_IF_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED (0x1UL << 2) /**< Completed scan */ +#define _KEYSCAN_IF_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IF_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_SCANNED_DEFAULT (_KEYSCAN_IF_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IF_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IF_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IF */ +#define KEYSCAN_IF_WAKEUP_DEFAULT (_KEYSCAN_IF_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IF */ + +/* Bit fields for KEYSCAN IEN */ +#define _KEYSCAN_IEN_RESETVALUE 0x00000000UL /**< Default value for KEYSCAN_IEN */ +#define _KEYSCAN_IEN_MASK 0x0000000FUL /**< Mask for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY (0x1UL << 0) /**< No Key was pressed */ +#define _KEYSCAN_IEN_NOKEY_SHIFT 0 /**< Shift value for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_MASK 0x1UL /**< Bit mask for KEYSCAN_NOKEY */ +#define _KEYSCAN_IEN_NOKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_NOKEY_DEFAULT (_KEYSCAN_IEN_NOKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY (0x1UL << 1) /**< A Key was pressed */ +#define _KEYSCAN_IEN_KEY_SHIFT 1 /**< Shift value for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_MASK 0x2UL /**< Bit mask for KEYSCAN_KEY */ +#define _KEYSCAN_IEN_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_KEY_DEFAULT (_KEYSCAN_IEN_KEY_DEFAULT << 1) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED (0x1UL << 2) /**< Completed Scanning */ +#define _KEYSCAN_IEN_SCANNED_SHIFT 2 /**< Shift value for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_MASK 0x4UL /**< Bit mask for KEYSCAN_SCANNED */ +#define _KEYSCAN_IEN_SCANNED_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_SCANNED_DEFAULT (_KEYSCAN_IEN_SCANNED_DEFAULT << 2) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP (0x1UL << 3) /**< Wake up */ +#define _KEYSCAN_IEN_WAKEUP_SHIFT 3 /**< Shift value for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_MASK 0x8UL /**< Bit mask for KEYSCAN_WAKEUP */ +#define _KEYSCAN_IEN_WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for KEYSCAN_IEN */ +#define KEYSCAN_IEN_WAKEUP_DEFAULT (_KEYSCAN_IEN_WAKEUP_DEFAULT << 3) /**< Shifted mode DEFAULT for KEYSCAN_IEN */ + +/** @} End of group EFR32MG24_KEYSCAN_BitFields */ +/** @} End of group EFR32MG24_KEYSCAN */ +/** @} End of group Parts */ + +#endif // EFR32MG24_KEYSCAN_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h index 890cb37..abf4346 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldma.h @@ -1,685 +1,685 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LDMA register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LDMA_H -#define EFR32MG24_LDMA_H -#define LDMA_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_LDMA LDMA - * @{ - * @brief EFR32MG24 LDMA Register Declaration. - *****************************************************************************/ - -/** LDMA CH Register Group Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG; /**< Channel Configuration Register */ - __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ - __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ - __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ - __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ - __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ -} LDMA_CH_TypeDef; - -/** LDMA Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL; /**< DMA Control Register */ - __IM uint32_t STATUS; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_SET; /**< DMA Control Register */ - __IM uint32_t STATUS_SET; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ - __IM uint32_t STATUS_CLR; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ - __IM uint32_t STATUS_TGL; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ -} LDMA_TypeDef; -/** @} End of group EFR32MG24_LDMA */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_LDMA - * @{ - * @defgroup EFR32MG24_LDMA_BitFields LDMA Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LDMA IPVERSION */ -#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ -#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ - -/* Bit fields for LDMA EN */ -#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ -#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ -#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ -#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ -#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ -#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ -#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ - -/* Bit fields for LDMA CTRL */ -#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ -#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ -#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ -#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ -#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ -#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ -#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ -#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ - -/* Bit fields for LDMA STATUS */ -#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ -#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ -#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ -#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ -#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ -#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ -#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ -#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ -#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ -#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ -#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ -#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ -#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ -#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ -#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ -#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ -#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ - -/* Bit fields for LDMA SYNCSWSET */ -#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ -#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ - -/* Bit fields for LDMA SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ -#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ - -/* Bit fields for LDMA SYNCHWEN */ -#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ - -/* Bit fields for LDMA SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ - -/* Bit fields for LDMA SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ -#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ - -/* Bit fields for LDMA CHEN */ -#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ -#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ -#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ - -/* Bit fields for LDMA CHDIS */ -#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ -#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ -#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ - -/* Bit fields for LDMA CHSTATUS */ -#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ -#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ - -/* Bit fields for LDMA CHBUSY */ -#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ -#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ -#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ -#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ -#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ -#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ - -/* Bit fields for LDMA CHDONE */ -#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ -#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ -#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ -#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ -#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ -#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ -#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ -#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ -#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ -#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ -#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ -#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ -#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ -#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ -#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ -#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ -#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ -#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ - -/* Bit fields for LDMA DBGHALT */ -#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ -#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ - -/* Bit fields for LDMA SWREQ */ -#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ -#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ -#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ - -/* Bit fields for LDMA REQDIS */ -#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ -#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ -#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ - -/* Bit fields for LDMA REQPEND */ -#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ -#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ -#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ - -/* Bit fields for LDMA LINKLOAD */ -#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ -#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ - -/* Bit fields for LDMA REQCLEAR */ -#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ -#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ - -/* Bit fields for LDMA IF */ -#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ -#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ -#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ -#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ -#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ -#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ -#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ -#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ -#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ -#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ -#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ -#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ -#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ -#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ -#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ -#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ -#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ -#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ -#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ -#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ -#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ -#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ - -/* Bit fields for LDMA IEN */ -#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ -#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ -#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ -#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ -#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ -#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ -#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ -#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ - -/* Bit fields for LDMA CH_CFG */ -#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ -#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ -#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ - -/* Bit fields for LDMA CH_LOOP */ -#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ -#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ -#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ -#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ -#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ -#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ - -/* Bit fields for LDMA CH_CTRL */ -#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ -#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ -#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ -#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ -#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ -#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ -#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ -#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ -#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ - -/* Bit fields for LDMA CH_SRC */ -#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ -#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ -#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ -#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ -#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ -#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ - -/* Bit fields for LDMA CH_DST */ -#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ -#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ -#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ -#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ -#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ -#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ - -/* Bit fields for LDMA CH_LINK */ -#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ -#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ -#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ -#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ -#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ -#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ -#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ -#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ -#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ - -/** @} End of group EFR32MG24_LDMA_BitFields */ -/** @} End of group EFR32MG24_LDMA */ -/** @} End of group Parts */ - -#endif // EFR32MG24_LDMA_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LDMA_H +#define EFR32MG24_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LDMA LDMA + * @{ + * @brief EFR32MG24 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32MG24_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LDMA + * @{ + * @defgroup EFR32MG24_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32MG24_LDMA_BitFields */ +/** @} End of group EFR32MG24_LDMA */ +/** @} End of group Parts */ + +#endif // EFR32MG24_LDMA_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h index 98874c7..e3dfef9 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar.h @@ -1,96 +1,96 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LDMAXBAR register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LDMAXBAR_H -#define EFR32MG24_LDMAXBAR_H -#define LDMAXBAR_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_LDMAXBAR LDMAXBAR - * @{ - * @brief EFR32MG24 LDMAXBAR Register Declaration. - *****************************************************************************/ - -/** LDMAXBAR CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ -} LDMAXBAR_CH_TypeDef; - -/** LDMAXBAR Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[1015U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ - LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ -} LDMAXBAR_TypeDef; -/** @} End of group EFR32MG24_LDMAXBAR */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_LDMAXBAR - * @{ - * @defgroup EFR32MG24_LDMAXBAR_BitFields LDMAXBAR Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LDMAXBAR IPVERSION */ -#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ -#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ -#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ - -/* Bit fields for LDMAXBAR CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ - -/** @} End of group EFR32MG24_LDMAXBAR_BitFields */ -/** @} End of group EFR32MG24_LDMAXBAR */ -/** @} End of group Parts */ - -#endif // EFR32MG24_LDMAXBAR_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LDMAXBAR_H +#define EFR32MG24_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32MG24 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1015U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP veersion ID */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32MG24_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LDMAXBAR + * @{ + * @defgroup EFR32MG24_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR IPVERSION */ +#define _LDMAXBAR_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LDMAXBAR_IPVERSION */ +#define _LDMAXBAR_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LDMAXBAR_IPVERSION */ +#define LDMAXBAR_IPVERSION_IPVERSION_DEFAULT (_LDMAXBAR_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_IPVERSION */ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32MG24_LDMAXBAR_BitFields */ +/** @} End of group EFR32MG24_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // EFR32MG24_LDMAXBAR_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h index 2164843..3884753 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ldmaxbar_defines.h @@ -1,157 +1,157 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LDMA XBAR channel request soruce definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LDMAXBAR_DEFINES_H -#define EFR32MG24_LDMAXBAR_DEFINES_H - -// Module source selection indices -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x0000000fUL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000010UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x00000011UL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 0x00000012UL /**< Mode VDAC1 for LDMAXBAR_CH_REQSEL */ - -// Shifted source selection indices -#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) -#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 << 16) /**< Shifted Mode VDAC1 for LDMAXBAR_CH_REQSEL */ - -// Module signal selection indices -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ 0x00000000UL /** Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ 0x00000001UL /** Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ - -// Shifted Module signal selection indices -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ - -#endif // EFR32MG24_LDMAXBAR_DEFINES_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LDMAXBAR_DEFINES_H +#define EFR32MG24_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000005UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000006UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000aUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000bUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000cUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000dUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x0000000eUL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 0x0000000fUL /**< Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 0x00000010UL /**< Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 0x00000011UL /**< Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 0x00000012UL /**< Mode VDAC1 for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0 << 16) /**< Shifted Mode EUSART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1 << 16) /**< Shifted Mode EUSART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted Mode VDAC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1 << 16) /**< Shifted Mode VDAC1 for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL 0x00000000UL /** Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL 0x00000001UL /** Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL 0x00000000UL /** Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL 0x00000001UL /** Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ 0x00000000UL /** Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ 0x00000001UL /** Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ 0x00000000UL /** Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ 0x00000001UL /** Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL << 0) /** Shifted Mode EUSART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL << 0) /** Shifted Mode EUSART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL << 0) /** Shifted Mode EUSART1RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL << 0) /** Shifted Mode EUSART1TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ << 0) /** Shifted Mode VDAC0CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ << 0) /** Shifted Mode VDAC0CH1_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ << 0) /** Shifted Mode VDAC1CH0_REQ for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ (_LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ << 0) /** Shifted Mode VDAC1CH1_REQ for LDMAXBAR_CH_REQSEL**/ + +#endif // EFR32MG24_LDMAXBAR_DEFINES_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h index 1fa36ec..52915fc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_letimer.h @@ -1,534 +1,534 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LETIMER register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LETIMER_H -#define EFR32MG24_LETIMER_H -#define LETIMER_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_LETIMER LETIMER - * @{ - * @brief EFR32MG24 LETIMER Register Declaration. - *****************************************************************************/ - -/** LETIMER Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t EN; /**< module en */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t COMP0; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1; /**< Compare Value Register 1 */ - __IOM uint32_t TOP; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ - uint32_t RESERVED1[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t EN_SET; /**< module en */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ - uint32_t RESERVED3[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t EN_CLR; /**< module en */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ - uint32_t RESERVED5[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t EN_TGL; /**< module en */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ -} LETIMER_TypeDef; -/** @} End of group EFR32MG24_LETIMER */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_LETIMER - * @{ - * @defgroup EFR32MG24_LETIMER_BitFields LETIMER Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LETIMER IPVERSION */ -#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ -#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ - -/* Bit fields for LETIMER EN */ -#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ -#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ -#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ -#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ -#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ -#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ -#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ - -/* Bit fields for LETIMER SWRST */ -#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ -#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ -#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ -#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ -#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ - -/* Bit fields for LETIMER CTRL */ -#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ -#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ -#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ -#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ -#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ -#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ -#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ - -/* Bit fields for LETIMER CMD */ -#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ -#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ -#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ -#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ -#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ -#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ -#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ -#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ -#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ - -/* Bit fields for LETIMER STATUS */ -#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ -#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ -#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ -#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ -#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ - -/* Bit fields for LETIMER CNT */ -#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ -#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ -#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ - -/* Bit fields for LETIMER COMP0 */ -#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ -#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ - -/* Bit fields for LETIMER COMP1 */ -#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ -#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ - -/* Bit fields for LETIMER TOP */ -#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ -#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ -#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ - -/* Bit fields for LETIMER TOPBUFF */ -#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ -#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ - -/* Bit fields for LETIMER REP0 */ -#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ -#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ -#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ - -/* Bit fields for LETIMER REP1 */ -#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ -#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ -#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ - -/* Bit fields for LETIMER IF */ -#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ -#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ -#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ -#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ -#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ -#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ -#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ -#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ - -/* Bit fields for LETIMER IEN */ -#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ -#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ -#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ -#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ -#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ -#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ -#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ -#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ - -/* Bit fields for LETIMER LOCK */ -#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ -#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ -#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ -#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ - -/* Bit fields for LETIMER SYNCBUSY */ -#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ -#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ -#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ -#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ -#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ -#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ -#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ -#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ - -/* Bit fields for LETIMER PRSMODE */ -#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ - -/** @} End of group EFR32MG24_LETIMER_BitFields */ -/** @} End of group EFR32MG24_LETIMER */ -/** @} End of group Parts */ - -#endif // EFR32MG24_LETIMER_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LETIMER_H +#define EFR32MG24_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LETIMER LETIMER + * @{ + * @brief EFR32MG24 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED5[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32MG24_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LETIMER + * @{ + * @defgroup EFR32MG24_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000003UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _LETIMER_EN_DISABLING_SHIFT 1 /**< Shift value for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for LETIMER_DISABLING */ +#define _LETIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_DISABLING_DEFAULT (_LETIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER SWRST */ +#define _LETIMER_SWRST_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SWRST */ +#define _LETIMER_SWRST_MASK 0x00000003UL /**< Mask for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _LETIMER_SWRST_SWRST_SHIFT 0 /**< Shift value for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_MASK 0x1UL /**< Bit mask for LETIMER_SWRST */ +#define _LETIMER_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_SWRST_DEFAULT (_LETIMER_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _LETIMER_SWRST_RESETTING_SHIFT 1 /**< Shift value for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for LETIMER_RESETTING */ +#define _LETIMER_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SWRST */ +#define LETIMER_SWRST_RESETTING_DEFAULT (_LETIMER_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SWRST */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000003UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS (0x1UL << 1) /**< LETIMER Lock Status */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_SHIFT 1 /**< Shift value for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_MASK 0x2UL /**< Bit mask for LETIMER_LETIMERLOCKSTATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LETIMER_STATUS */ +#define _LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT (_LETIMER_STATUS_LETIMERLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for LETIMER_STATUS */ +#define LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED (_LETIMER_STATUS_LETIMERLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER LOCK */ +#define _LETIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for LETIMER_LOCK */ +#define _LETIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_SHIFT 0 /**< Shift value for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_MASK 0xFFFFUL /**< Bit mask for LETIMER_LETIMERLOCKKEY */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_LOCK */ +#define _LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK 0x0000CCFCUL /**< Mode UNLOCK for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT (_LETIMER_LOCK_LETIMERLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_LOCK */ +#define LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK (_LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LETIMER_LOCK */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32MG24_LETIMER_BitFields */ +/** @} End of group EFR32MG24_LETIMER */ +/** @} End of group Parts */ + +#endif // EFR32MG24_LETIMER_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h index d89c987..393cfc7 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfrco.h @@ -1,304 +1,304 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LFRCO_H -#define EFR32MG24_LFRCO_H -#define LFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_LFRCO LFRCO - * @{ - * @brief EFR32MG24 LFRCO Register Declaration. - *****************************************************************************/ - -/** LFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED3[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED7[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED11[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED12[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ -} LFRCO_TypeDef; -/** @} End of group EFR32MG24_LFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_LFRCO - * @{ - * @defgroup EFR32MG24_LFRCO_BitFields LFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LFRCO IPVERSION */ -#define _LFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFRCO_IPVERSION */ -#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ - -/* Bit fields for LFRCO CTRL */ -#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ -#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ -#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ -#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ -#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ -#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ -#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ -#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ - -/* Bit fields for LFRCO STATUS */ -#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ -#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ - -/* Bit fields for LFRCO IF */ -#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ -#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ -#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ -#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ -#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ -#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ -#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ -#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ -#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ -#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ -#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ -#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ -#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ -#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ -#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ -#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ -#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ -#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ -#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ -#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ -#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ -#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ -#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ -#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ - -/* Bit fields for LFRCO IEN */ -#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ -#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ -#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ -#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ -#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ -#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ -#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ -#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ -#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ -#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ -#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ -#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ -#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ -#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ -#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ -#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ -#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ -#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ -#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ -#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ -#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ -#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ -#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ -#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ - -/* Bit fields for LFRCO LOCK */ -#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ -#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ - -/* Bit fields for LFRCO CFG */ -#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ -#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ -#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ -#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ -#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ -#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ -#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ - -/* Bit fields for LFRCO NOMCAL */ -#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ -#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ -#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ -#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ -#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ -#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ - -/* Bit fields for LFRCO NOMCALINV */ -#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ -#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ -#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ - -/* Bit fields for LFRCO CMD */ -#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ -#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ -#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ -#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ -#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ -#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ -#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ - -/** @} End of group EFR32MG24_LFRCO_BitFields */ -/** @} End of group EFR32MG24_LFRCO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_LFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LFRCO_H +#define EFR32MG24_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LFRCO LFRCO + * @{ + * @brief EFR32MG24 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32MG24_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LFRCO + * @{ + * @defgroup EFR32MG24_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group EFR32MG24_LFRCO_BitFields */ +/** @} End of group EFR32MG24_LFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_LFRCO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h index d916139..0541ebf 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_lfxo.h @@ -1,281 +1,281 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 LFXO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_LFXO_H -#define EFR32MG24_LFXO_H -#define LFXO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_LFXO LFXO - * @{ - * @brief EFR32MG24 LFXO Register Declaration. - *****************************************************************************/ - -/** LFXO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< LFXO IP version */ - __IOM uint32_t CTRL; /**< LFXO Control Register */ - __IOM uint32_t CFG; /**< LFXO Configuration Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< LFXO Status Register */ - __IOM uint32_t CAL; /**< LFXO Calibration Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ - __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ - __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< LFXO Status Register */ - __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ - __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ - __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ - __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ - __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ - __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ - __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ -} LFXO_TypeDef; -/** @} End of group EFR32MG24_LFXO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_LFXO - * @{ - * @defgroup EFR32MG24_LFXO_BitFields LFXO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LFXO IPVERSION */ -#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ -#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ - -/* Bit fields for LFXO CTRL */ -#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ -#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ -#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ -#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ -#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ -#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ - -/* Bit fields for LFXO CFG */ -#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ -#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ -#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ -#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ -#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ -#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ -#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ -#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ -#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ -#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ -#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ - -/* Bit fields for LFXO STATUS */ -#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ -#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ -#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ -#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ -#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ -#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ -#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ -#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ - -/* Bit fields for LFXO CAL */ -#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ -#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ -#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ -#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ - -/* Bit fields for LFXO IF */ -#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ -#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ -#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ -#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ -#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ - -/* Bit fields for LFXO IEN */ -#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ -#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ -#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ -#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ -#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ - -/* Bit fields for LFXO SYNCBUSY */ -#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ -#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ -#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ - -/* Bit fields for LFXO LOCK */ -#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ -#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ - -/** @} End of group EFR32MG24_LFXO_BitFields */ -/** @} End of group EFR32MG24_LFXO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_LFXO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_LFXO_H +#define EFR32MG24_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_LFXO LFXO + * @{ + * @brief EFR32MG24 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32MG24_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_LFXO + * @{ + * @defgroup EFR32MG24_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32MG24_LFXO_BitFields */ +/** @} End of group EFR32MG24_LFXO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_LFXO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h index 2697da0..afccf45 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mailbox.h @@ -1,140 +1,140 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 MAILBOX register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_MAILBOX_H -#define EFR32MG24_MAILBOX_H -#define MAILBOX_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_MAILBOX MAILBOX - * @{ - * @brief EFR32MG24 MAILBOX Register Declaration. - *****************************************************************************/ - -/** MAILBOX MSGPTRS Register Group Declaration. */ -typedef struct { - __IOM uint32_t MSGPTR; /**< Message Pointer */ -} MAILBOX_MSGPTRS_TypeDef; - -/** MAILBOX Register Declaration. */ -typedef struct { - MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ - uint32_t RESERVED0[12U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag register */ - __IOM uint32_t IEN; /**< Interrupt Enable register */ - uint32_t RESERVED1[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ - uint32_t RESERVED2[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ - uint32_t RESERVED3[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ - uint32_t RESERVED4[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ - uint32_t RESERVED5[1006U]; /**< Reserved for future use */ - MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ - uint32_t RESERVED6[12U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ -} MAILBOX_TypeDef; -/** @} End of group EFR32MG24_MAILBOX */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_MAILBOX - * @{ - * @defgroup EFR32MG24_MAILBOX_BitFields MAILBOX Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for MAILBOX MSGPTR */ -#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ -#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ -#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ -#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ - -/* Bit fields for MAILBOX IF */ -#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ -#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ -#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ -#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ -#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ -#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ -#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ -#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ - -/* Bit fields for MAILBOX IEN */ -#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ -#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ -#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ -#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ -#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ -#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ -#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ -#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ - -/** @} End of group EFR32MG24_MAILBOX_BitFields */ -/** @} End of group EFR32MG24_MAILBOX */ -/** @} End of group Parts */ - -#endif // EFR32MG24_MAILBOX_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 MAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MAILBOX_H +#define EFR32MG24_MAILBOX_H +#define MAILBOX_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MAILBOX MAILBOX + * @{ + * @brief EFR32MG24 MAILBOX Register Declaration. + *****************************************************************************/ + +/** MAILBOX MSGPTRS Register Group Declaration. */ +typedef struct { + __IOM uint32_t MSGPTR; /**< Message Pointer */ +} MAILBOX_MSGPTRS_TypeDef; + +/** MAILBOX Register Declaration. */ +typedef struct { + MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ + uint32_t RESERVED0[12U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag register */ + __IOM uint32_t IEN; /**< Interrupt Enable register */ + uint32_t RESERVED1[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ + uint32_t RESERVED2[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ + uint32_t RESERVED3[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ + uint32_t RESERVED4[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ + uint32_t RESERVED6[12U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ +} MAILBOX_TypeDef; +/** @} End of group EFR32MG24_MAILBOX */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MAILBOX + * @{ + * @defgroup EFR32MG24_MAILBOX_BitFields MAILBOX Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MAILBOX MSGPTR */ +#define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ +#define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ +#define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ +#define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ + +/* Bit fields for MAILBOX IF */ +#define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ +#define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ +#define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ +#define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ +#define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ +#define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ +#define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ +#define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ + +/* Bit fields for MAILBOX IEN */ +#define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ +#define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ +#define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ +#define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ +#define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ +#define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ +#define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ +#define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ + +/** @} End of group EFR32MG24_MAILBOX_BitFields */ +/** @} End of group EFR32MG24_MAILBOX */ +/** @} End of group Parts */ + +#endif // EFR32MG24_MAILBOX_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h index 9eca4c1..813b224 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mpahbram.h @@ -1,330 +1,330 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 MPAHBRAM register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_MPAHBRAM_H -#define EFR32MG24_MPAHBRAM_H -#define MPAHBRAM_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM - * @{ - * @brief EFR32MG24 MPAHBRAM Register Declaration. - *****************************************************************************/ - -/** MPAHBRAM Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CMD; /**< Command register */ - __IOM uint32_t CTRL; /**< Control register */ - __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ - __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ - __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ - __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[7U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CMD_SET; /**< Command register */ - __IOM uint32_t CTRL_SET; /**< Control register */ - __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ - __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ - __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ - __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED3[7U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CMD_CLR; /**< Command register */ - __IOM uint32_t CTRL_CLR; /**< Control register */ - __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ - __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ - __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ - __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED6[7U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[1006U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CMD_TGL; /**< Command register */ - __IOM uint32_t CTRL_TGL; /**< Control register */ - __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ - __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ - __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ - __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ - __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ -} MPAHBRAM_TypeDef; -/** @} End of group EFR32MG24_MPAHBRAM */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_MPAHBRAM - * @{ - * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for MPAHBRAM IPVERSION */ -#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ -#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ -#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ - -/* Bit fields for MPAHBRAM CMD */ -#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ -#define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ -#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ -#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ -#define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ -#define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ -#define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ -#define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ -#define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ -#define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ -#define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ - -/* Bit fields for MPAHBRAM CTRL */ -#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ -#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ -#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ -#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ -#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ -#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ -#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ -#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ -#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ -#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ -#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ -#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ -#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ -#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ - -/* Bit fields for MPAHBRAM ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ -#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ - -/* Bit fields for MPAHBRAM ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ -#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ - -/* Bit fields for MPAHBRAM ECCERRADDR2 */ -#define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ -#define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ -#define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ -#define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ - -/* Bit fields for MPAHBRAM ECCERRADDR3 */ -#define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ -#define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ -#define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ -#define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ -#define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ - -/* Bit fields for MPAHBRAM ECCMERRIND */ -#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ -#define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ -#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ -#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ -#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ -#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ -#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ -#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ -#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ -#define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ -#define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ -#define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ -#define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ -#define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ -#define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ -#define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ -#define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ -#define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ - -/* Bit fields for MPAHBRAM IF */ -#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ -#define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ -#define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ -#define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ -#define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ -#define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ -#define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ -#define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ -#define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ -#define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ -#define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ -#define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ - -/* Bit fields for MPAHBRAM IEN */ -#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ -#define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ -#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ -#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ -#define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ -#define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ -#define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ -#define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ -#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ -#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ -#define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ -#define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ -#define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ -#define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ -#define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ -#define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ - -/** @} End of group EFR32MG24_MPAHBRAM_BitFields */ -/** @} End of group EFR32MG24_MPAHBRAM */ -/** @} End of group Parts */ - -#endif // EFR32MG24_MPAHBRAM_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 MPAHBRAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MPAHBRAM_H +#define EFR32MG24_MPAHBRAM_H +#define MPAHBRAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM + * @{ + * @brief EFR32MG24 MPAHBRAM Register Declaration. + *****************************************************************************/ + +/** MPAHBRAM Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CMD; /**< Command register */ + __IOM uint32_t CTRL; /**< Control register */ + __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CMD_SET; /**< Command register */ + __IOM uint32_t CTRL_SET; /**< Control register */ + __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED3[7U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CMD_CLR; /**< Command register */ + __IOM uint32_t CTRL_CLR; /**< Control register */ + __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[1006U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CMD_TGL; /**< Command register */ + __IOM uint32_t CTRL_TGL; /**< Control register */ + __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ + __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ + __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ + __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ + __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ +} MPAHBRAM_TypeDef; +/** @} End of group EFR32MG24_MPAHBRAM */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MPAHBRAM + * @{ + * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MPAHBRAM IPVERSION */ +#define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ +#define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ +#define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ + +/* Bit fields for MPAHBRAM CMD */ +#define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ +#define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ +#define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ +#define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ +#define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ +#define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ +#define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ + +/* Bit fields for MPAHBRAM CTRL */ +#define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ +#define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ +#define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ +#define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ +#define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ +#define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ +#define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ +#define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ +#define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ +#define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ +#define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ + +/* Bit fields for MPAHBRAM ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ +#define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ + +/* Bit fields for MPAHBRAM ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ +#define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ + +/* Bit fields for MPAHBRAM ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ +#define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ + +/* Bit fields for MPAHBRAM ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ +#define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ +#define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ + +/* Bit fields for MPAHBRAM ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ +#define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ +#define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ +#define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ +#define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ +#define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ +#define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ +#define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ +#define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ +#define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ +#define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ + +/* Bit fields for MPAHBRAM IF */ +#define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ +#define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ +#define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ +#define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ + +/* Bit fields for MPAHBRAM IEN */ +#define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ +#define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ +#define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ +#define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ +#define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ +#define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ +#define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ +#define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ +#define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ +#define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ +#define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ +#define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ + +/** @} End of group EFR32MG24_MPAHBRAM_BitFields */ +/** @} End of group EFR32MG24_MPAHBRAM */ +/** @} End of group Parts */ + +#endif // EFR32MG24_MPAHBRAM_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h index 6b2ab4f..311a58a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_msc.h @@ -1,546 +1,546 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 MSC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_MSC_H -#define EFR32MG24_MSC_H -#define MSC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_MSC MSC - * @{ - * @brief EFR32MG24 MSC Register Declaration. - *****************************************************************************/ - -/** MSC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t READCTRL; /**< Read Control Register */ - __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL; /**< Write Control Register */ - __IOM uint32_t WRITECMD; /**< Write Command Register */ - __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA; /**< Write Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL; /**< Power control register */ - uint32_t RESERVED2[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ - __IOM uint32_t PAGELOCK4; /**< Main space page 128-159 lock word */ - __IOM uint32_t PAGELOCK5; /**< Main space page 160-191 lock word */ - uint32_t RESERVED3[2U]; /**< Reserved for future use */ - uint32_t RESERVED4[4U]; /**< Reserved for future use */ - uint32_t RESERVED5[4U]; /**< Reserved for future use */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[12U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t READCTRL_SET; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ - __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ - __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_SET; /**< Write Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED12[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ - uint32_t RESERVED13[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_SET; /**< Power control register */ - uint32_t RESERVED14[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ - __IOM uint32_t PAGELOCK4_SET; /**< Main space page 128-159 lock word */ - __IOM uint32_t PAGELOCK5_SET; /**< Main space page 160-191 lock word */ - uint32_t RESERVED15[2U]; /**< Reserved for future use */ - uint32_t RESERVED16[4U]; /**< Reserved for future use */ - uint32_t RESERVED17[4U]; /**< Reserved for future use */ - uint32_t RESERVED18[4U]; /**< Reserved for future use */ - uint32_t RESERVED19[12U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[8U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ - __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ - __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_CLR; /**< Write Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ - uint32_t RESERVED26[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ - __IOM uint32_t PAGELOCK4_CLR; /**< Main space page 128-159 lock word */ - __IOM uint32_t PAGELOCK5_CLR; /**< Main space page 160-191 lock word */ - uint32_t RESERVED27[2U]; /**< Reserved for future use */ - uint32_t RESERVED28[4U]; /**< Reserved for future use */ - uint32_t RESERVED29[4U]; /**< Reserved for future use */ - uint32_t RESERVED30[4U]; /**< Reserved for future use */ - uint32_t RESERVED31[12U]; /**< Reserved for future use */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - uint32_t RESERVED33[8U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ - uint32_t RESERVED35[910U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ - __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ - __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ - __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ - __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_TGL; /**< Write Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED36[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ - uint32_t RESERVED38[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ - __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ - __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ - __IOM uint32_t PAGELOCK4_TGL; /**< Main space page 128-159 lock word */ - __IOM uint32_t PAGELOCK5_TGL; /**< Main space page 160-191 lock word */ - uint32_t RESERVED39[2U]; /**< Reserved for future use */ - uint32_t RESERVED40[4U]; /**< Reserved for future use */ - uint32_t RESERVED41[4U]; /**< Reserved for future use */ - uint32_t RESERVED42[4U]; /**< Reserved for future use */ - uint32_t RESERVED43[12U]; /**< Reserved for future use */ - uint32_t RESERVED44[1U]; /**< Reserved for future use */ - uint32_t RESERVED45[8U]; /**< Reserved for future use */ - uint32_t RESERVED46[1U]; /**< Reserved for future use */ -} MSC_TypeDef; -/** @} End of group EFR32MG24_MSC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_MSC - * @{ - * @defgroup EFR32MG24_MSC_BitFields MSC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for MSC IPVERSION */ -#define _MSC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MSC_IPVERSION */ -#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_IPVERSION */ -#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ - -/* Bit fields for MSC READCTRL */ -#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ -#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ -#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ -#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ - -/* Bit fields for MSC RDATACTRL */ -#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ -#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ -#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ -#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ -#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ -#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ -#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ -#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ -#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ -#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ - -/* Bit fields for MSC WRITECTRL */ -#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ -#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ -#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ -#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ -#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ -#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ -#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ - -/* Bit fields for MSC WRITECMD */ -#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ -#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ -#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ -#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ -#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ -#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ -#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ -#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ -#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ -#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ - -/* Bit fields for MSC ADDRB */ -#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ -#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ -#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ - -/* Bit fields for MSC WDATA */ -#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ -#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ -#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ -#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ -#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ -#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ - -/* Bit fields for MSC STATUS */ -#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ -#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ -#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ -#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ -#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ -#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ -#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ -#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ -#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ -#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ -#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ -#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ -#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ -#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ -#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ -#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ -#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ -#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */ -#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ -#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ -#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ -#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ -#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ -#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ - -/* Bit fields for MSC IF */ -#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ -#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ -#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ -#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ -#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ -#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ -#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ -#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ - -/* Bit fields for MSC IEN */ -#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ -#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ -#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ -#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ -#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ -#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ -#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ -#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ - -/* Bit fields for MSC USERDATASIZE */ -#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ -#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ - -/* Bit fields for MSC CMD */ -#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ -#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ -#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ -#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ -#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ - -/* Bit fields for MSC LOCK */ -#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ -#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ - -/* Bit fields for MSC MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ - -/* Bit fields for MSC PWRCTRL */ -#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ - -/* Bit fields for MSC PAGELOCK0 */ -#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ -#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ - -/* Bit fields for MSC PAGELOCK1 */ -#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ -#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ - -/* Bit fields for MSC PAGELOCK2 */ -#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ -#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ -#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ -#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ - -/* Bit fields for MSC PAGELOCK3 */ -#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ -#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ -#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ -#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ - -/* Bit fields for MSC PAGELOCK4 */ -#define _MSC_PAGELOCK4_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK4 */ -#define _MSC_PAGELOCK4_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK4 */ -#define _MSC_PAGELOCK4_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK4_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK4_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK4 */ -#define MSC_PAGELOCK4_LOCKBIT_DEFAULT (_MSC_PAGELOCK4_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK4 */ - -/* Bit fields for MSC PAGELOCK5 */ -#define _MSC_PAGELOCK5_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK5 */ -#define _MSC_PAGELOCK5_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK5 */ -#define _MSC_PAGELOCK5_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK5_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK5_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK5 */ -#define MSC_PAGELOCK5_LOCKBIT_DEFAULT (_MSC_PAGELOCK5_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK5 */ - -/** @} End of group EFR32MG24_MSC_BitFields */ -/** @} End of group EFR32MG24_MSC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_MSC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MSC_H +#define EFR32MG24_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MSC MSC + * @{ + * @brief EFR32MG24 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED2[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5; /**< Main space page 160-191 lock word */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + uint32_t RESERVED4[4U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[12U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_SET; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED13[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED14[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_SET; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_SET; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_SET; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_SET; /**< Main space page 160-191 lock word */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + uint32_t RESERVED16[4U]; /**< Reserved for future use */ + uint32_t RESERVED17[4U]; /**< Reserved for future use */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + uint32_t RESERVED19[12U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[8U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_CLR; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED26[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_CLR; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_CLR; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_CLR; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_CLR; /**< Main space page 160-191 lock word */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + uint32_t RESERVED28[4U]; /**< Reserved for future use */ + uint32_t RESERVED29[4U]; /**< Reserved for future use */ + uint32_t RESERVED30[4U]; /**< Reserved for future use */ + uint32_t RESERVED31[12U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[8U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + uint32_t RESERVED35[910U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t RDATACTRL_TGL; /**< Read Data Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED36[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED38[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + __IOM uint32_t PAGELOCK2_TGL; /**< Main space page 64-95 lock word */ + __IOM uint32_t PAGELOCK3_TGL; /**< Main space page 96-127 lock word */ + __IOM uint32_t PAGELOCK4_TGL; /**< Main space page 128-159 lock word */ + __IOM uint32_t PAGELOCK5_TGL; /**< Main space page 160-191 lock word */ + uint32_t RESERVED39[2U]; /**< Reserved for future use */ + uint32_t RESERVED40[4U]; /**< Reserved for future use */ + uint32_t RESERVED41[4U]; /**< Reserved for future use */ + uint32_t RESERVED42[4U]; /**< Reserved for future use */ + uint32_t RESERVED43[12U]; /**< Reserved for future use */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + uint32_t RESERVED45[8U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32MG24_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MSC + * @{ + * @defgroup EFR32MG24_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00300000UL /**< Mask for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC RDATACTRL */ +#define _MSC_RDATACTRL_RESETVALUE 0x00001000UL /**< Default value for MSC_RDATACTRL */ +#define _MSC_RDATACTRL_MASK 0x00001002UL /**< Mask for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS (0x1UL << 1) /**< Automatic Invalidate Disable */ +#define _MSC_RDATACTRL_AFDIS_SHIFT 1 /**< Shift value for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_MASK 0x2UL /**< Bit mask for MSC_AFDIS */ +#define _MSC_RDATACTRL_AFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_AFDIS_DEFAULT (_MSC_RDATACTRL_AFDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_RDATACTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_RDATACTRL_DOUTBUFEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_RDATACTRL */ +#define MSC_RDATACTRL_DOUTBUFEN_DEFAULT (_MSC_RDATACTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_RDATACTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x03FF000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_RANGECOUNT_SHIFT 16 /**< Shift value for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_MASK 0x3FF0000UL /**< Bit mask for MSC_RANGECOUNT */ +#define _MSC_WRITECTRL_RANGECOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_RANGECOUNT_DEFAULT (_MSC_WRITECTRL_RANGECOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001136UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE (0x1UL << 4) /**< Erase range of pages */ +#define _MSC_WRITECMD_ERASERANGE_SHIFT 4 /**< Shift value for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_MASK 0x10UL /**< Bit mask for MSC_ERASERANGE */ +#define _MSC_WRITECMD_ERASERANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASERANGE_DEFAULT (_MSC_WRITECMD_ERASERANGE_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF90100FFUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL (0x1UL << 7) /**< EraseRange with skipped locked pages */ +#define _MSC_STATUS_RANGEPARTIAL_SHIFT 7 /**< Shift value for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_MASK 0x80UL /**< Bit mask for MSC_RANGEPARTIAL */ +#define _MSC_STATUS_RANGEPARTIAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_RANGEPARTIAL_DEFAULT (_MSC_STATUS_RANGEPARTIAL_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash power on status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/* Bit fields for MSC PAGELOCK2 */ +#define _MSC_PAGELOCK2_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK2 */ +#define _MSC_PAGELOCK2_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK2_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK2 */ +#define MSC_PAGELOCK2_LOCKBIT_DEFAULT (_MSC_PAGELOCK2_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK2 */ + +/* Bit fields for MSC PAGELOCK3 */ +#define _MSC_PAGELOCK3_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK3 */ +#define _MSC_PAGELOCK3_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK3_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK3 */ +#define MSC_PAGELOCK3_LOCKBIT_DEFAULT (_MSC_PAGELOCK3_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK3 */ + +/* Bit fields for MSC PAGELOCK4 */ +#define _MSC_PAGELOCK4_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK4 */ +#define _MSC_PAGELOCK4_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK4 */ +#define _MSC_PAGELOCK4_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK4_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK4_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK4 */ +#define MSC_PAGELOCK4_LOCKBIT_DEFAULT (_MSC_PAGELOCK4_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK4 */ + +/* Bit fields for MSC PAGELOCK5 */ +#define _MSC_PAGELOCK5_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK5 */ +#define _MSC_PAGELOCK5_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK5 */ +#define _MSC_PAGELOCK5_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK5_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK5_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK5 */ +#define MSC_PAGELOCK5_LOCKBIT_DEFAULT (_MSC_PAGELOCK5_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK5 */ + +/** @} End of group EFR32MG24_MSC_BitFields */ +/** @} End of group EFR32MG24_MSC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_MSC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h index 111b803..75df5fa 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_mvp.h @@ -1,1386 +1,1386 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 MVP register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_MVP_H -#define EFR32MG24_MVP_H -#define MVP_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_MVP MVP - * @{ - * @brief EFR32MG24 MVP Register Declaration. - *****************************************************************************/ - -/** MVP PERF Register Group Declaration. */ -typedef struct { - __IM uint32_t CNT; /**< Run Counter */ -} MVP_PERF_TypeDef; - -/** MVP ARRAYST Register Group Declaration. */ -typedef struct { - __IOM uint32_t INDEXSTATE; /**< Index State */ -} MVP_ARRAYST_TypeDef; - -/** MVP LOOPST Register Group Declaration. */ -typedef struct { - __IOM uint32_t STATE; /**< Loop State */ -} MVP_LOOPST_TypeDef; - -/** MVP ALU Register Group Declaration. */ -typedef struct { - __IOM uint32_t REGSTATE; /**< ALU Rn Register */ -} MVP_ALU_TypeDef; - -/** MVP ARRAY Register Group Declaration. */ -typedef struct { - __IOM uint32_t ADDRCFG; /**< Array Base Address */ - __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ - __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ - __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ -} MVP_ARRAY_TypeDef; - -/** MVP LOOP Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG; /**< Loop Configuration */ - __IOM uint32_t RST; /**< Loop Reset */ -} MVP_LOOP_TypeDef; - -/** MVP INSTR Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ - __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ - __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ -} MVP_INSTR_TypeDef; - -/** MVP Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t SWRST; /**< Software Reset */ - __IOM uint32_t CFG; /**< Configuration */ - __IM uint32_t STATUS; /**< Status */ - MVP_PERF_TypeDef PERF[2U]; /**< */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - __IM uint32_t FAULTSTATUS; /**< Fault Status */ - __IM uint32_t FAULTADDR; /**< Fault Address */ - __IOM uint32_t PROGRAMSTATE; /**< Program State */ - MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ - MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ - MVP_ALU_TypeDef ALU[8U]; /**< */ - MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ - MVP_LOOP_TypeDef LOOP[8U]; /**< */ - MVP_INSTR_TypeDef INSTR[8U]; /**< */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED0[34U]; /**< Reserved for future use */ - __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ - __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ - uint32_t RESERVED1[894U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset */ - __IOM uint32_t CFG_SET; /**< Configuration */ - __IM uint32_t STATUS_SET; /**< Status */ - MVP_PERF_TypeDef PERF_SET[2U]; /**< */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ - __IM uint32_t FAULTADDR_SET; /**< Fault Address */ - __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ - MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ - MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ - MVP_ALU_TypeDef ALU_SET[8U]; /**< */ - MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ - MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ - MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED2[34U]; /**< Reserved for future use */ - __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ - __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ - uint32_t RESERVED3[894U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset */ - __IOM uint32_t CFG_CLR; /**< Configuration */ - __IM uint32_t STATUS_CLR; /**< Status */ - MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ - __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ - __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ - MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ - MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ - MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ - MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ - MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ - MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED4[34U]; /**< Reserved for future use */ - __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ - __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ - uint32_t RESERVED5[894U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset */ - __IOM uint32_t CFG_TGL; /**< Configuration */ - __IM uint32_t STATUS_TGL; /**< Status */ - MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ - __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ - __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ - MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ - MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ - MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ - MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ - MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ - MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED6[34U]; /**< Reserved for future use */ - __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ - __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ -} MVP_TypeDef; -/** @} End of group EFR32MG24_MVP */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_MVP - * @{ - * @defgroup EFR32MG24_MVP_BitFields MVP Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for MVP IPVERSION */ -#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ -#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ -#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ -#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ -#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ -#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ - -/* Bit fields for MVP EN */ -#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ -#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ -#define MVP_EN_EN (0x1UL << 0) /**< Enable */ -#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ -#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ -#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ -#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ -#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ -#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ -#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ -#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ -#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ - -/* Bit fields for MVP SWRST */ -#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ -#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ -#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ -#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ -#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ -#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ -#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ -#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ -#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ -#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ -#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ -#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ - -/* Bit fields for MVP CFG */ -#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ -#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ -#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ -#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ -#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ -#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ -#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ -#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ -#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ -#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ -#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ -#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ -#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ -#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ -#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ -#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ -#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ -#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ -#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ -#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ -#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ -#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ -#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ -#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ -#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ - -/* Bit fields for MVP STATUS */ -#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ -#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ -#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ -#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ -#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ -#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ -#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ -#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ -#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ -#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ -#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ -#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ -#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ -#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ -#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ -#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ -#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ - -/* Bit fields for MVP PERFCNT */ -#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ -#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ -#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ -#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ -#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ -#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ - -/* Bit fields for MVP IF */ -#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ -#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ -#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ -#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ -#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ -#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ -#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ -#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ -#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ -#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ -#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ -#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ -#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ -#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ -#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ -#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ -#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ -#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ -#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ -#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ -#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ -#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ -#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ -#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ -#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ -#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ -#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ -#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ -#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ -#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ -#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ -#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ -#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ -#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ -#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ -#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ -#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ -#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ -#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ -#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ -#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ -#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ -#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ -#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ -#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ -#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ -#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ -#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ -#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ -#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ -#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ -#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ -#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ -#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ -#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ -#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ -#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ -#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ -#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ -#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ -#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ -#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ -#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ -#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ -#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ -#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ -#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ -#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ -#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ -#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ - -/* Bit fields for MVP IEN */ -#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ -#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ -#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ -#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ -#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ -#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ -#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ -#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ -#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ -#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ -#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ -#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ -#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ -#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ -#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ -#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ -#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ -#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ -#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ -#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ -#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ -#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ -#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ -#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ -#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ -#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ -#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ -#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ -#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ -#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ -#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ -#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ -#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ -#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ -#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ -#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ -#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ -#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ -#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ -#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ -#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ -#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ -#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ -#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ -#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ -#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ -#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ -#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ -#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ -#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ -#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ -#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ -#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ -#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ -#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ -#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ -#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ -#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ -#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ -#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ -#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ -#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ -#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ -#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ -#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ -#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ -#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ -#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ -#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ - -/* Bit fields for MVP FAULTSTATUS */ -#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ -#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ -#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ -#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ -#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ -#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ -#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ -#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ -#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ -#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ -#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ -#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ - -/* Bit fields for MVP FAULTADDR */ -#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ -#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ -#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ -#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ -#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ -#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ - -/* Bit fields for MVP PROGRAMSTATE */ -#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ -#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ -#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ -#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ -#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ -#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ - -/* Bit fields for MVP ARRAYINDEXSTATE */ -#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ -#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ -#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ -#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ -#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ -#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ -#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ -#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ -#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ - -/* Bit fields for MVP LOOPSTATE */ -#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ -#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ -#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ -#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ -#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ -#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ -#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ -#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ -#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ -#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ -#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ -#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ -#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ -#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ -#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ - -/* Bit fields for MVP ALUREGSTATE */ -#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ -#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ -#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ -#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ -#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ -#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ -#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ -#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ -#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ -#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ - -/* Bit fields for MVP ARRAYADDRCFG */ -#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ -#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ -#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ -#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ -#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ -#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ - -/* Bit fields for MVP ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ -#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ -#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ -#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ -#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ -#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ -#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ -#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ -#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ -#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ - -/* Bit fields for MVP ARRAYDIM1CFG */ -#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ -#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ -#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ -#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ -#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ -#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ -#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ -#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ -#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ -#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ - -/* Bit fields for MVP ARRAYDIM2CFG */ -#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ -#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ -#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ -#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ -#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ -#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ -#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ -#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ -#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ -#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ - -/* Bit fields for MVP LOOPCFG */ -#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ -#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ -#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ -#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ -#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ -#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ -#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ - -/* Bit fields for MVP LOOPRST */ -#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ -#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ -#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ -#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ - -/* Bit fields for MVP INSTRCFG0 */ -#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ -#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ -#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ -#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ -#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ -#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ -#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ -#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ -#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ -#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ -#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ -#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ -#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ -#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ -#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ -#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ -#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ -#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ -#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ -#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ -#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ -#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ -#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ -#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ -#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ -#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ -#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ -#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ -#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ -#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ -#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ -#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ -#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ -#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ - -/* Bit fields for MVP INSTRCFG1 */ -#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ -#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ -#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ -#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ -#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ -#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ -#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ -#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ -#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ -#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ -#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ -#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ -#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ -#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ -#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ -#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ -#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ -#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ -#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ -#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ - -/* Bit fields for MVP INSTRCFG2 */ -#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ -#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ -#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ -#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ -#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ -#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ -#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ -#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ -#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ -#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ -#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ -#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ -#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ -#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ -#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ -#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ -#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ -#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ -#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ -#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ -#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ -#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ -#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ -#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ -#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ -#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ -#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ -#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ -#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ -#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ -#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ -#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ -#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ -#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ -#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ -#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ -#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ -#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ -#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ -#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ -#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ -#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ - -/* Bit fields for MVP CMD */ -#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ -#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ -#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ -#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ -#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ -#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ -#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ -#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ -#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ -#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ -#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ -#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ -#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ -#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ -#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ -#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ -#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ -#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ -#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ -#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ -#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ -#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ - -/* Bit fields for MVP DEBUGEN */ -#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ -#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ -#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ -#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ -#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ -#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ -#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ -#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ -#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ -#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ -#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ -#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ -#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ -#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ -#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ -#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ -#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ -#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ -#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ -#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ -#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ -#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ -#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ -#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ -#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ -#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ -#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ -#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ -#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ -#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ -#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ -#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ -#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ -#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ -#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ -#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ -#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ -#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ -#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ -#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ -#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ -#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ - -/* Bit fields for MVP DEBUGSTEPCNT */ -#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ -#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ -#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ -#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ -#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ -#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ - -/** @} End of group EFR32MG24_MVP_BitFields */ -/** @} End of group EFR32MG24_MVP */ -/** @} End of group Parts */ - -#endif // EFR32MG24_MVP_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 MVP register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_MVP_H +#define EFR32MG24_MVP_H +#define MVP_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_MVP MVP + * @{ + * @brief EFR32MG24 MVP Register Declaration. + *****************************************************************************/ + +/** MVP PERF Register Group Declaration. */ +typedef struct { + __IM uint32_t CNT; /**< Run Counter */ +} MVP_PERF_TypeDef; + +/** MVP ARRAYST Register Group Declaration. */ +typedef struct { + __IOM uint32_t INDEXSTATE; /**< Index State */ +} MVP_ARRAYST_TypeDef; + +/** MVP LOOPST Register Group Declaration. */ +typedef struct { + __IOM uint32_t STATE; /**< Loop State */ +} MVP_LOOPST_TypeDef; + +/** MVP ALU Register Group Declaration. */ +typedef struct { + __IOM uint32_t REGSTATE; /**< ALU Rn Register */ +} MVP_ALU_TypeDef; + +/** MVP ARRAY Register Group Declaration. */ +typedef struct { + __IOM uint32_t ADDRCFG; /**< Array Base Address */ + __IOM uint32_t DIM0CFG; /**< Dimension 0 Configuration */ + __IOM uint32_t DIM1CFG; /**< Dimension 1 Configuration */ + __IOM uint32_t DIM2CFG; /**< Dimension 2 Configuration */ +} MVP_ARRAY_TypeDef; + +/** MVP LOOP Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Loop Configuration */ + __IOM uint32_t RST; /**< Loop Reset */ +} MVP_LOOP_TypeDef; + +/** MVP INSTR Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG0; /**< Instruction Configuration Word 0 */ + __IOM uint32_t CFG1; /**< Instruction Configuration Word 1 */ + __IOM uint32_t CFG2; /**< Instruction Configuration Word 2 */ +} MVP_INSTR_TypeDef; + +/** MVP Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t SWRST; /**< Software Reset */ + __IOM uint32_t CFG; /**< Configuration */ + __IM uint32_t STATUS; /**< Status */ + MVP_PERF_TypeDef PERF[2U]; /**< */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS; /**< Fault Status */ + __IM uint32_t FAULTADDR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST[8U]; /**< */ + MVP_ALU_TypeDef ALU[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY[5U]; /**< */ + MVP_LOOP_TypeDef LOOP[8U]; /**< */ + MVP_INSTR_TypeDef INSTR[8U]; /**< */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT; /**< Debug Step Register */ + uint32_t RESERVED1[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset */ + __IOM uint32_t CFG_SET; /**< Configuration */ + __IM uint32_t STATUS_SET; /**< Status */ + MVP_PERF_TypeDef PERF_SET[2U]; /**< */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_SET; /**< Fault Status */ + __IM uint32_t FAULTADDR_SET; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_SET; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_SET[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_SET[8U]; /**< */ + MVP_ALU_TypeDef ALU_SET[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_SET[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_SET[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_SET[8U]; /**< */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_SET; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_SET; /**< Debug Step Register */ + uint32_t RESERVED3[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset */ + __IOM uint32_t CFG_CLR; /**< Configuration */ + __IM uint32_t STATUS_CLR; /**< Status */ + MVP_PERF_TypeDef PERF_CLR[2U]; /**< */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_CLR; /**< Fault Status */ + __IM uint32_t FAULTADDR_CLR; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_CLR; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_CLR[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_CLR[8U]; /**< */ + MVP_ALU_TypeDef ALU_CLR[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_CLR[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_CLR[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_CLR[8U]; /**< */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_CLR; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_CLR; /**< Debug Step Register */ + uint32_t RESERVED5[894U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset */ + __IOM uint32_t CFG_TGL; /**< Configuration */ + __IM uint32_t STATUS_TGL; /**< Status */ + MVP_PERF_TypeDef PERF_TGL[2U]; /**< */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IM uint32_t FAULTSTATUS_TGL; /**< Fault Status */ + __IM uint32_t FAULTADDR_TGL; /**< Fault Address */ + __IOM uint32_t PROGRAMSTATE_TGL; /**< Program State */ + MVP_ARRAYST_TypeDef ARRAYST_TGL[5U]; /**< */ + MVP_LOOPST_TypeDef LOOPST_TGL[8U]; /**< */ + MVP_ALU_TypeDef ALU_TGL[8U]; /**< */ + MVP_ARRAY_TypeDef ARRAY_TGL[5U]; /**< */ + MVP_LOOP_TypeDef LOOP_TGL[8U]; /**< */ + MVP_INSTR_TypeDef INSTR_TGL[8U]; /**< */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[34U]; /**< Reserved for future use */ + __IOM uint32_t DEBUGEN_TGL; /**< Debug Enable Register */ + __IOM uint32_t DEBUGSTEPCNT_TGL; /**< Debug Step Register */ +} MVP_TypeDef; +/** @} End of group EFR32MG24_MVP */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_MVP + * @{ + * @defgroup EFR32MG24_MVP_BitFields MVP Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MVP IPVERSION */ +#define _MVP_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for MVP_IPVERSION */ +#define _MVP_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_IPVERSION */ +#define _MVP_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_IPVERSION */ +#define MVP_IPVERSION_IPVERSION_DEFAULT (_MVP_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IPVERSION */ + +/* Bit fields for MVP EN */ +#define _MVP_EN_RESETVALUE 0x00000000UL /**< Default value for MVP_EN */ +#define _MVP_EN_MASK 0x00000003UL /**< Mask for MVP_EN */ +#define MVP_EN_EN (0x1UL << 0) /**< Enable */ +#define _MVP_EN_EN_SHIFT 0 /**< Shift value for MVP_EN */ +#define _MVP_EN_EN_MASK 0x1UL /**< Bit mask for MVP_EN */ +#define _MVP_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_EN_DEFAULT (_MVP_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING (0x1UL << 1) /**< Disablement Busy Status */ +#define _MVP_EN_DISABLING_SHIFT 1 /**< Shift value for MVP_DISABLING */ +#define _MVP_EN_DISABLING_MASK 0x2UL /**< Bit mask for MVP_DISABLING */ +#define _MVP_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_EN */ +#define MVP_EN_DISABLING_DEFAULT (_MVP_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_EN */ + +/* Bit fields for MVP SWRST */ +#define _MVP_SWRST_RESETVALUE 0x00000000UL /**< Default value for MVP_SWRST */ +#define _MVP_SWRST_MASK 0x00000003UL /**< Mask for MVP_SWRST */ +#define MVP_SWRST_SWRST (0x1UL << 0) /**< Software Reset Command */ +#define _MVP_SWRST_SWRST_SHIFT 0 /**< Shift value for MVP_SWRST */ +#define _MVP_SWRST_SWRST_MASK 0x1UL /**< Bit mask for MVP_SWRST */ +#define _MVP_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_SWRST_DEFAULT (_MVP_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING (0x1UL << 1) /**< Software Reset Busy Status */ +#define _MVP_SWRST_RESETTING_SHIFT 1 /**< Shift value for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for MVP_RESETTING */ +#define _MVP_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_SWRST */ +#define MVP_SWRST_RESETTING_DEFAULT (_MVP_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_SWRST */ + +/* Bit fields for MVP CFG */ +#define _MVP_CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_CFG */ +#define _MVP_CFG_MASK 0x00FF000FUL /**< Mask for MVP_CFG */ +#define MVP_CFG_PERFCNTEN (0x1UL << 0) /**< Performance Counter Enable */ +#define _MVP_CFG_PERFCNTEN_SHIFT 0 /**< Shift value for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_MASK 0x1UL /**< Bit mask for MVP_PERFCNTEN */ +#define _MVP_CFG_PERFCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERFCNTEN_DEFAULT (_MVP_CFG_PERFCNTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS (0x1UL << 1) /**< ALU Output Stream Compression Disable */ +#define _MVP_CFG_OUTCOMPRESSDIS_SHIFT 1 /**< Shift value for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_MASK 0x2UL /**< Bit mask for MVP_OUTCOMPRESSDIS */ +#define _MVP_CFG_OUTCOMPRESSDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_OUTCOMPRESSDIS_DEFAULT (_MVP_CFG_OUTCOMPRESSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS (0x1UL << 2) /**< ALU Input Word Cache Disable */ +#define _MVP_CFG_INCACHEDIS_SHIFT 2 /**< Shift value for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_MASK 0x4UL /**< Bit mask for MVP_INCACHEDIS */ +#define _MVP_CFG_INCACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_INCACHEDIS_DEFAULT (_MVP_CFG_INCACHEDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS (0x1UL << 3) /**< Loop Error Halt Disable */ +#define _MVP_CFG_LOOPERRHALTDIS_SHIFT 3 /**< Shift value for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_MASK 0x8UL /**< Bit mask for MVP_LOOPERRHALTDIS */ +#define _MVP_CFG_LOOPERRHALTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define MVP_CFG_LOOPERRHALTDIS_DEFAULT (_MVP_CFG_LOOPERRHALTDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_SHIFT 16 /**< Shift value for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_MASK 0xF0000UL /**< Bit mask for MVP_PERF0CNTSEL */ +#define _MVP_CFG_PERF0CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_DEFAULT (_MVP_CFG_PERF0CNTSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_RUN (_MVP_CFG_PERF0CNTSEL_RUN << 16) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_CMD (_MVP_CFG_PERF0CNTSEL_CMD << 16) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STALL (_MVP_CFG_PERF0CNTSEL_STALL << 16) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_NOOP (_MVP_CFG_PERF0CNTSEL_NOOP << 16) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_ALUACTIVE (_MVP_CFG_PERF0CNTSEL_ALUACTIVE << 16) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_PIPESTALL (_MVP_CFG_PERF0CNTSEL_PIPESTALL << 16) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_IOFENCESTALL (_MVP_CFG_PERF0CNTSEL_IOFENCESTALL << 16) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0STALL (_MVP_CFG_PERF0CNTSEL_LOAD0STALL << 16) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1STALL (_MVP_CFG_PERF0CNTSEL_LOAD1STALL << 16) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_STORESTALL (_MVP_CFG_PERF0CNTSEL_STORESTALL << 16) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_BUSSTALL (_MVP_CFG_PERF0CNTSEL_BUSSTALL << 16) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD0AHBSTALL << 16) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF0CNTSEL_LOAD1AHBSTALL << 16) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD0FENCESTALL << 16) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF0CNTSEL_LOAD1FENCESTALL << 16) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_SHIFT 20 /**< Shift value for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_MASK 0xF00000UL /**< Bit mask for MVP_PERF1CNTSEL */ +#define _MVP_CFG_PERF1CNTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_RUN 0x00000000UL /**< Mode RUN for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_CMD 0x00000001UL /**< Mode CMD for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STALL 0x00000002UL /**< Mode STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_NOOP 0x00000003UL /**< Mode NOOP for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_ALUACTIVE 0x00000004UL /**< Mode ALUACTIVE for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_PIPESTALL 0x00000005UL /**< Mode PIPESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_IOFENCESTALL 0x00000006UL /**< Mode IOFENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0STALL 0x00000007UL /**< Mode LOAD0STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1STALL 0x00000008UL /**< Mode LOAD1STALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_STORESTALL 0x00000009UL /**< Mode STORESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_BUSSTALL 0x0000000AUL /**< Mode BUSSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL 0x0000000BUL /**< Mode LOAD0AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL 0x0000000CUL /**< Mode LOAD1AHBSTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL 0x0000000DUL /**< Mode LOAD0FENCESTALL for MVP_CFG */ +#define _MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL 0x0000000EUL /**< Mode LOAD1FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_DEFAULT (_MVP_CFG_PERF1CNTSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_RUN (_MVP_CFG_PERF1CNTSEL_RUN << 20) /**< Shifted mode RUN for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_CMD (_MVP_CFG_PERF1CNTSEL_CMD << 20) /**< Shifted mode CMD for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STALL (_MVP_CFG_PERF1CNTSEL_STALL << 20) /**< Shifted mode STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_NOOP (_MVP_CFG_PERF1CNTSEL_NOOP << 20) /**< Shifted mode NOOP for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_ALUACTIVE (_MVP_CFG_PERF1CNTSEL_ALUACTIVE << 20) /**< Shifted mode ALUACTIVE for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_PIPESTALL (_MVP_CFG_PERF1CNTSEL_PIPESTALL << 20) /**< Shifted mode PIPESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_IOFENCESTALL (_MVP_CFG_PERF1CNTSEL_IOFENCESTALL << 20) /**< Shifted mode IOFENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0STALL (_MVP_CFG_PERF1CNTSEL_LOAD0STALL << 20) /**< Shifted mode LOAD0STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1STALL (_MVP_CFG_PERF1CNTSEL_LOAD1STALL << 20) /**< Shifted mode LOAD1STALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_STORESTALL (_MVP_CFG_PERF1CNTSEL_STORESTALL << 20) /**< Shifted mode STORESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_BUSSTALL (_MVP_CFG_PERF1CNTSEL_BUSSTALL << 20) /**< Shifted mode BUSSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD0AHBSTALL << 20) /**< Shifted mode LOAD0AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL (_MVP_CFG_PERF1CNTSEL_LOAD1AHBSTALL << 20) /**< Shifted mode LOAD1AHBSTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD0FENCESTALL << 20) /**< Shifted mode LOAD0FENCESTALL for MVP_CFG */ +#define MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL (_MVP_CFG_PERF1CNTSEL_LOAD1FENCESTALL << 20) /**< Shifted mode LOAD1FENCESTALL for MVP_CFG */ + +/* Bit fields for MVP STATUS */ +#define _MVP_STATUS_RESETVALUE 0x00000004UL /**< Default value for MVP_STATUS */ +#define _MVP_STATUS_MASK 0x00000007UL /**< Mask for MVP_STATUS */ +#define MVP_STATUS_RUNNING (0x1UL << 0) /**< Running Status */ +#define _MVP_STATUS_RUNNING_SHIFT 0 /**< Shift value for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for MVP_RUNNING */ +#define _MVP_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_RUNNING_DEFAULT (_MVP_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED (0x1UL << 1) /**< Paused Status */ +#define _MVP_STATUS_PAUSED_SHIFT 1 /**< Shift value for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_MASK 0x2UL /**< Bit mask for MVP_PAUSED */ +#define _MVP_STATUS_PAUSED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_PAUSED_DEFAULT (_MVP_STATUS_PAUSED_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE (0x1UL << 2) /**< Idle Status */ +#define _MVP_STATUS_IDLE_SHIFT 2 /**< Shift value for MVP_IDLE */ +#define _MVP_STATUS_IDLE_MASK 0x4UL /**< Bit mask for MVP_IDLE */ +#define _MVP_STATUS_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MVP_STATUS */ +#define MVP_STATUS_IDLE_DEFAULT (_MVP_STATUS_IDLE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_STATUS */ + +/* Bit fields for MVP PERFCNT */ +#define _MVP_PERFCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_PERFCNT */ +#define _MVP_PERFCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_PERFCNT */ +#define _MVP_PERFCNT_COUNT_SHIFT 0 /**< Shift value for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_COUNT */ +#define _MVP_PERFCNT_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PERFCNT */ +#define MVP_PERFCNT_COUNT_DEFAULT (_MVP_PERFCNT_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PERFCNT */ + +/* Bit fields for MVP IF */ +#define _MVP_IF_RESETVALUE 0x00000000UL /**< Default value for MVP_IF */ +#define _MVP_IF_MASK 0x1F0FFDFFUL /**< Mask for MVP_IF */ +#define MVP_IF_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Flags */ +#define _MVP_IF_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IF_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PROGDONE_DEFAULT (_MVP_IF_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IF_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP0DONE_DEFAULT (_MVP_IF_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IF_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP1DONE_DEFAULT (_MVP_IF_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IF_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP2DONE_DEFAULT (_MVP_IF_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IF_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP3DONE_DEFAULT (_MVP_IF_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IF_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP4DONE_DEFAULT (_MVP_IF_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IF_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP5DONE_DEFAULT (_MVP_IF_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IF_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP6DONE_DEFAULT (_MVP_IF_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Flag */ +#define _MVP_IF_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IF_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOP7DONE_DEFAULT (_MVP_IF_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Flag */ +#define _MVP_IF_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IF_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUNAN_DEFAULT (_MVP_IF_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL (0x1UL << 11) /**< R0 non-zero Interrupt Flag */ +#define _MVP_IF_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IF_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_R0POSREAL_DEFAULT (_MVP_IF_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF (0x1UL << 12) /**< ALU Overflow on result */ +#define _MVP_IF_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IF_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IF_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUOF_DEFAULT (_MVP_IF_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF (0x1UL << 13) /**< ALU Underflow on result */ +#define _MVP_IF_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IF_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IF_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUUF_DEFAULT (_MVP_IF_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF (0x1UL << 14) /**< Overflow during array store */ +#define _MVP_IF_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IF_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTOF_DEFAULT (_MVP_IF_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF (0x1UL << 15) /**< Underflow during array store conversion */ +#define _MVP_IF_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IF_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTUF_DEFAULT (_MVP_IF_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF (0x1UL << 16) /**< Infinity encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IF_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTINF_DEFAULT (_MVP_IF_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN (0x1UL << 17) /**< NaN encountered during array store conversion*/ +#define _MVP_IF_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IF_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_STORECONVERTNAN_DEFAULT (_MVP_IF_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0 (0x1UL << 18) /**< Run Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IF_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT0_DEFAULT (_MVP_IF_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1 (0x1UL << 19) /**< Stall Count Overflow Interrupt Flag */ +#define _MVP_IF_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IF_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_PERFCNT1_DEFAULT (_MVP_IF_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Flag */ +#define _MVP_IF_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IF_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_LOOPFAULT_DEFAULT (_MVP_IF_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Flag */ +#define _MVP_IF_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IF_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSERRFAULT_DEFAULT (_MVP_IF_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Flag */ +#define _MVP_IF_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IF_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_BUSALIGNFAULT_DEFAULT (_MVP_IF_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT (0x1UL << 27) /**< ALU Fault Interrupt Flag */ +#define _MVP_IF_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IF_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ALUFAULT_DEFAULT (_MVP_IF_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Flag */ +#define _MVP_IF_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IF_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IF */ +#define MVP_IF_ARRAYFAULT_DEFAULT (_MVP_IF_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IF */ + +/* Bit fields for MVP IEN */ +#define _MVP_IEN_RESETVALUE 0x00000000UL /**< Default value for MVP_IEN */ +#define _MVP_IEN_MASK 0x1F0FFDFFUL /**< Mask for MVP_IEN */ +#define MVP_IEN_PROGDONE (0x1UL << 0) /**< Program Done Interrupt Enable */ +#define _MVP_IEN_PROGDONE_SHIFT 0 /**< Shift value for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_MASK 0x1UL /**< Bit mask for MVP_PROGDONE */ +#define _MVP_IEN_PROGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PROGDONE_DEFAULT (_MVP_IEN_PROGDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE (0x1UL << 1) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP0DONE_SHIFT 1 /**< Shift value for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_LOOP0DONE */ +#define _MVP_IEN_LOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP0DONE_DEFAULT (_MVP_IEN_LOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE (0x1UL << 2) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP1DONE_SHIFT 2 /**< Shift value for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_LOOP1DONE */ +#define _MVP_IEN_LOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP1DONE_DEFAULT (_MVP_IEN_LOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE (0x1UL << 3) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP2DONE_SHIFT 3 /**< Shift value for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_LOOP2DONE */ +#define _MVP_IEN_LOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP2DONE_DEFAULT (_MVP_IEN_LOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE (0x1UL << 4) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP3DONE_SHIFT 4 /**< Shift value for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_LOOP3DONE */ +#define _MVP_IEN_LOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP3DONE_DEFAULT (_MVP_IEN_LOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE (0x1UL << 5) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP4DONE_SHIFT 5 /**< Shift value for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_LOOP4DONE */ +#define _MVP_IEN_LOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP4DONE_DEFAULT (_MVP_IEN_LOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE (0x1UL << 6) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP5DONE_SHIFT 6 /**< Shift value for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_LOOP5DONE */ +#define _MVP_IEN_LOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP5DONE_DEFAULT (_MVP_IEN_LOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE (0x1UL << 7) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP6DONE_SHIFT 7 /**< Shift value for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_LOOP6DONE */ +#define _MVP_IEN_LOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP6DONE_DEFAULT (_MVP_IEN_LOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE (0x1UL << 8) /**< Loop Done Interrupt Enable */ +#define _MVP_IEN_LOOP7DONE_SHIFT 8 /**< Shift value for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_LOOP7DONE */ +#define _MVP_IEN_LOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOP7DONE_DEFAULT (_MVP_IEN_LOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN (0x1UL << 10) /**< Not-a-Number Interrupt Enable */ +#define _MVP_IEN_ALUNAN_SHIFT 10 /**< Shift value for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_MASK 0x400UL /**< Bit mask for MVP_ALUNAN */ +#define _MVP_IEN_ALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUNAN_DEFAULT (_MVP_IEN_ALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL (0x1UL << 11) /**< R0 Non-Zero Interrupt Enable */ +#define _MVP_IEN_R0POSREAL_SHIFT 11 /**< Shift value for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_MASK 0x800UL /**< Bit mask for MVP_R0POSREAL */ +#define _MVP_IEN_R0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_R0POSREAL_DEFAULT (_MVP_IEN_R0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF (0x1UL << 12) /**< ALU Overflow Interrupt Enable */ +#define _MVP_IEN_ALUOF_SHIFT 12 /**< Shift value for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_MASK 0x1000UL /**< Bit mask for MVP_ALUOF */ +#define _MVP_IEN_ALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUOF_DEFAULT (_MVP_IEN_ALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF (0x1UL << 13) /**< ALU Underflow Interrupt Enable */ +#define _MVP_IEN_ALUUF_SHIFT 13 /**< Shift value for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_MASK 0x2000UL /**< Bit mask for MVP_ALUUF */ +#define _MVP_IEN_ALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUUF_DEFAULT (_MVP_IEN_ALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF (0x1UL << 14) /**< Store conversion Overflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTOF_SHIFT 14 /**< Shift value for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_STORECONVERTOF */ +#define _MVP_IEN_STORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTOF_DEFAULT (_MVP_IEN_STORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF (0x1UL << 15) /**< Store Conversion Underflow Interrupt Enable */ +#define _MVP_IEN_STORECONVERTUF_SHIFT 15 /**< Shift value for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_STORECONVERTUF */ +#define _MVP_IEN_STORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTUF_DEFAULT (_MVP_IEN_STORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF (0x1UL << 16) /**< Store Conversion Infinity Interrupt Enable */ +#define _MVP_IEN_STORECONVERTINF_SHIFT 16 /**< Shift value for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_STORECONVERTINF */ +#define _MVP_IEN_STORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTINF_DEFAULT (_MVP_IEN_STORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN (0x1UL << 17) /**< Store Conversion NaN Interrupt Enable */ +#define _MVP_IEN_STORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_STORECONVERTNAN */ +#define _MVP_IEN_STORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_STORECONVERTNAN_DEFAULT (_MVP_IEN_STORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0 (0x1UL << 18) /**< Perf Counter 0 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT0_SHIFT 18 /**< Shift value for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_MASK 0x40000UL /**< Bit mask for MVP_PERFCNT0 */ +#define _MVP_IEN_PERFCNT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT0_DEFAULT (_MVP_IEN_PERFCNT0_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1 (0x1UL << 19) /**< Perf Counter 1 Overflow Interrupt Enable */ +#define _MVP_IEN_PERFCNT1_SHIFT 19 /**< Shift value for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_MASK 0x80000UL /**< Bit mask for MVP_PERFCNT1 */ +#define _MVP_IEN_PERFCNT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_PERFCNT1_DEFAULT (_MVP_IEN_PERFCNT1_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT (0x1UL << 24) /**< Loop Fault Interrupt Enable */ +#define _MVP_IEN_LOOPFAULT_SHIFT 24 /**< Shift value for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_MASK 0x1000000UL /**< Bit mask for MVP_LOOPFAULT */ +#define _MVP_IEN_LOOPFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_LOOPFAULT_DEFAULT (_MVP_IEN_LOOPFAULT_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT (0x1UL << 25) /**< Bus Error Fault Interrupt Enable */ +#define _MVP_IEN_BUSERRFAULT_SHIFT 25 /**< Shift value for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_MASK 0x2000000UL /**< Bit mask for MVP_BUSERRFAULT */ +#define _MVP_IEN_BUSERRFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSERRFAULT_DEFAULT (_MVP_IEN_BUSERRFAULT_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT (0x1UL << 26) /**< Bus Alignment Fault Interrupt Enable */ +#define _MVP_IEN_BUSALIGNFAULT_SHIFT 26 /**< Shift value for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_MASK 0x4000000UL /**< Bit mask for MVP_BUSALIGNFAULT */ +#define _MVP_IEN_BUSALIGNFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_BUSALIGNFAULT_DEFAULT (_MVP_IEN_BUSALIGNFAULT_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT (0x1UL << 27) /**< ALU Input Fault Interrupt Enable */ +#define _MVP_IEN_ALUFAULT_SHIFT 27 /**< Shift value for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_MASK 0x8000000UL /**< Bit mask for MVP_ALUFAULT */ +#define _MVP_IEN_ALUFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ALUFAULT_DEFAULT (_MVP_IEN_ALUFAULT_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT (0x1UL << 28) /**< Array Fault Interrupt Enable */ +#define _MVP_IEN_ARRAYFAULT_SHIFT 28 /**< Shift value for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_MASK 0x10000000UL /**< Bit mask for MVP_ARRAYFAULT */ +#define _MVP_IEN_ARRAYFAULT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_IEN */ +#define MVP_IEN_ARRAYFAULT_DEFAULT (_MVP_IEN_ARRAYFAULT_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_IEN */ + +/* Bit fields for MVP FAULTSTATUS */ +#define _MVP_FAULTSTATUS_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_MASK 0x000F3707UL /**< Mask for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTPC_SHIFT 0 /**< Shift value for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_MASK 0x7UL /**< Bit mask for MVP_FAULTPC */ +#define _MVP_FAULTSTATUS_FAULTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTPC_DEFAULT (_MVP_FAULTSTATUS_FAULTPC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTARRAY_SHIFT 8 /**< Shift value for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_MASK 0x700UL /**< Bit mask for MVP_FAULTARRAY */ +#define _MVP_FAULTSTATUS_FAULTARRAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTARRAY_DEFAULT (_MVP_FAULTSTATUS_FAULTARRAY_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_SHIFT 12 /**< Shift value for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_MASK 0x3000UL /**< Bit mask for MVP_FAULTBUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_NONE 0x00000000UL /**< Mode NONE for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM 0x00000001UL /**< Mode LOAD0STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM 0x00000002UL /**< Mode LOAD1STREAM for MVP_FAULTSTATUS */ +#define _MVP_FAULTSTATUS_FAULTBUS_STORESTREAM 0x00000003UL /**< Mode STORESTREAM for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_DEFAULT (_MVP_FAULTSTATUS_FAULTBUS_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_NONE (_MVP_FAULTSTATUS_FAULTBUS_NONE << 12) /**< Shifted mode NONE for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD0STREAM << 12) /**< Shifted mode LOAD0STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM (_MVP_FAULTSTATUS_FAULTBUS_LOAD1STREAM << 12) /**< Shifted mode LOAD1STREAM for MVP_FAULTSTATUS*/ +#define MVP_FAULTSTATUS_FAULTBUS_STORESTREAM (_MVP_FAULTSTATUS_FAULTBUS_STORESTREAM << 12) /**< Shifted mode STORESTREAM for MVP_FAULTSTATUS*/ +#define _MVP_FAULTSTATUS_FAULTLOOP_SHIFT 16 /**< Shift value for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_MASK 0xF0000UL /**< Bit mask for MVP_FAULTLOOP */ +#define _MVP_FAULTSTATUS_FAULTLOOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTSTATUS */ +#define MVP_FAULTSTATUS_FAULTLOOP_DEFAULT (_MVP_FAULTSTATUS_FAULTLOOP_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_FAULTSTATUS */ + +/* Bit fields for MVP FAULTADDR */ +#define _MVP_FAULTADDR_RESETVALUE 0x00000000UL /**< Default value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_MASK 0xFFFFFFFFUL /**< Mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_SHIFT 0 /**< Shift value for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_FAULTADDR */ +#define _MVP_FAULTADDR_FAULTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_FAULTADDR */ +#define MVP_FAULTADDR_FAULTADDR_DEFAULT (_MVP_FAULTADDR_FAULTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_FAULTADDR */ + +/* Bit fields for MVP PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_MASK 0x00000007UL /**< Mask for MVP_PROGRAMSTATE */ +#define _MVP_PROGRAMSTATE_PC_SHIFT 0 /**< Shift value for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_MASK 0x7UL /**< Bit mask for MVP_PC */ +#define _MVP_PROGRAMSTATE_PC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_PROGRAMSTATE */ +#define MVP_PROGRAMSTATE_PC_DEFAULT (_MVP_PROGRAMSTATE_PC_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_PROGRAMSTATE */ + +/* Bit fields for MVP ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_MASK 0x3FFFFFFFUL /**< Mask for MVP_ARRAYINDEXSTATE */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_SHIFT 0 /**< Shift value for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_MASK 0x3FFUL /**< Bit mask for MVP_DIM0INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM0INDEX_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_SHIFT 10 /**< Shift value for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_MASK 0xFFC00UL /**< Bit mask for MVP_DIM1INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM1INDEX_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_SHIFT 20 /**< Shift value for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_MASK 0x3FF00000UL /**< Bit mask for MVP_DIM2INDEX */ +#define _MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYINDEXSTATE */ +#define MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT (_MVP_ARRAYINDEXSTATE_DIM2INDEX_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_ARRAYINDEXSTATE*/ + +/* Bit fields for MVP LOOPSTATE */ +#define _MVP_LOOPSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_MASK 0x000713FFUL /**< Mask for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_CNT_SHIFT 0 /**< Shift value for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_MASK 0x3FFUL /**< Bit mask for MVP_CNT */ +#define _MVP_LOOPSTATE_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_CNT_DEFAULT (_MVP_LOOPSTATE_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE (0x1UL << 12) /**< Loop Active */ +#define _MVP_LOOPSTATE_ACTIVE_SHIFT 12 /**< Shift value for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_MASK 0x1000UL /**< Bit mask for MVP_ACTIVE */ +#define _MVP_LOOPSTATE_ACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_ACTIVE_DEFAULT (_MVP_LOOPSTATE_ACTIVE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ +#define _MVP_LOOPSTATE_PCBEGIN_SHIFT 16 /**< Shift value for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_MASK 0x70000UL /**< Bit mask for MVP_PCBEGIN */ +#define _MVP_LOOPSTATE_PCBEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPSTATE */ +#define MVP_LOOPSTATE_PCBEGIN_DEFAULT (_MVP_LOOPSTATE_PCBEGIN_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPSTATE */ + +/* Bit fields for MVP ALUREGSTATE */ +#define _MVP_ALUREGSTATE_RESETVALUE 0x00000000UL /**< Default value for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_MASK 0xFFFFFFFFUL /**< Mask for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FREAL_SHIFT 0 /**< Shift value for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_MASK 0xFFFFUL /**< Bit mask for MVP_FREAL */ +#define _MVP_ALUREGSTATE_FREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FREAL_DEFAULT (_MVP_ALUREGSTATE_FREAL_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ +#define _MVP_ALUREGSTATE_FIMAG_SHIFT 16 /**< Shift value for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_MASK 0xFFFF0000UL /**< Bit mask for MVP_FIMAG */ +#define _MVP_ALUREGSTATE_FIMAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ALUREGSTATE */ +#define MVP_ALUREGSTATE_FIMAG_DEFAULT (_MVP_ALUREGSTATE_FIMAG_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ALUREGSTATE */ + +/* Bit fields for MVP ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_MASK 0xFFFFFFFFUL /**< Mask for MVP_ARRAYADDRCFG */ +#define _MVP_ARRAYADDRCFG_BASE_SHIFT 0 /**< Shift value for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_MASK 0xFFFFFFFFUL /**< Bit mask for MVP_BASE */ +#define _MVP_ARRAYADDRCFG_BASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYADDRCFG */ +#define MVP_ARRAYADDRCFG_BASE_DEFAULT (_MVP_ARRAYADDRCFG_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYADDRCFG */ + +/* Bit fields for MVP ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_RESETVALUE 0x00002000UL /**< Default value for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_MASK 0x0FFF73FFUL /**< Mask for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM0CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_SIZE_DEFAULT (_MVP_ARRAYDIM0CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT 12 /**< Shift value for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_MASK 0x3000UL /**< Bit mask for MVP_BASETYPE */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_UINT8 0x00000000UL /**< Mode UINT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_INT8 0x00000001UL /**< Mode INT8 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 0x00000002UL /**< Mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_BASETYPE_RESERVED 0x00000003UL /**< Mode RESERVED for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT (_MVP_ARRAYDIM0CFG_BASETYPE_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_UINT8 (_MVP_ARRAYDIM0CFG_BASETYPE_UINT8 << 12) /**< Shifted mode UINT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_INT8 (_MVP_ARRAYDIM0CFG_BASETYPE_INT8 << 12) /**< Shifted mode INT8 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 (_MVP_ARRAYDIM0CFG_BASETYPE_BINARY16 << 12) /**< Shifted mode BINARY16 for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX (0x1UL << 14) /**< Complex Data Type */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT 14 /**< Shift value for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_MASK 0x4000UL /**< Bit mask for MVP_COMPLEX */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_SCALAR 0x00000000UL /**< Mode SCALAR for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX 0x00000001UL /**< Mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT (_MVP_ARRAYDIM0CFG_COMPLEX_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_SCALAR (_MVP_ARRAYDIM0CFG_COMPLEX_SCALAR << 14) /**< Shifted mode SCALAR for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << 14) /**< Shifted mode COMPLEX for MVP_ARRAYDIM0CFG */ +#define _MVP_ARRAYDIM0CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM0CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM0CFG */ +#define MVP_ARRAYDIM0CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM0CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM0CFG */ + +/* Bit fields for MVP ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM1CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_SIZE_DEFAULT (_MVP_ARRAYDIM1CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define _MVP_ARRAYDIM1CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM1CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM1CFG */ +#define MVP_ARRAYDIM1CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM1CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM1CFG */ + +/* Bit fields for MVP ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_RESETVALUE 0x00000000UL /**< Default value for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_MASK 0x0FFF03FFUL /**< Mask for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_SIZE_SHIFT 0 /**< Shift value for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_MASK 0x3FFUL /**< Bit mask for MVP_SIZE */ +#define _MVP_ARRAYDIM2CFG_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_SIZE_DEFAULT (_MVP_ARRAYDIM2CFG_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define _MVP_ARRAYDIM2CFG_STRIDE_SHIFT 16 /**< Shift value for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_MASK 0xFFF0000UL /**< Bit mask for MVP_STRIDE */ +#define _MVP_ARRAYDIM2CFG_STRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_ARRAYDIM2CFG */ +#define MVP_ARRAYDIM2CFG_STRIDE_DEFAULT (_MVP_ARRAYDIM2CFG_STRIDE_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_ARRAYDIM2CFG */ + +/* Bit fields for MVP LOOPCFG */ +#define _MVP_LOOPCFG_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_MASK 0x777773FFUL /**< Mask for MVP_LOOPCFG */ +#define _MVP_LOOPCFG_NUMITERS_SHIFT 0 /**< Shift value for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_MASK 0x3FFUL /**< Bit mask for MVP_NUMITERS */ +#define _MVP_LOOPCFG_NUMITERS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_NUMITERS_DEFAULT (_MVP_LOOPCFG_NUMITERS_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0 (0x1UL << 12) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1 (0x1UL << 13) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2 (0x1UL << 14) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY0INCRDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0 (0x1UL << 16) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1 (0x1UL << 17) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2 (0x1UL << 18) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY1INCRDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0 (0x1UL << 20) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1 (0x1UL << 21) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2 (0x1UL << 22) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY2INCRDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0 (0x1UL << 24) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1 (0x1UL << 25) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2 (0x1UL << 26) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY3INCRDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0 (0x1UL << 28) /**< Increment Dimension 0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4INCRDIM0 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1 (0x1UL << 29) /**< Increment Dimension 1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4INCRDIM1 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2 (0x1UL << 30) /**< Increment Dimension 2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4INCRDIM2 */ +#define _MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPCFG */ +#define MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT (_MVP_LOOPCFG_ARRAY4INCRDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPCFG */ + +/* Bit fields for MVP LOOPRST */ +#define _MVP_LOOPRST_RESETVALUE 0x00000000UL /**< Default value for MVP_LOOPRST */ +#define _MVP_LOOPRST_MASK 0x77777000UL /**< Mask for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0 (0x1UL << 12) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT 12 /**< Shift value for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_MASK 0x1000UL /**< Bit mask for MVP_ARRAY0RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM0_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1 (0x1UL << 13) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_SHIFT 13 /**< Shift value for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_MASK 0x2000UL /**< Bit mask for MVP_ARRAY0RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM1_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2 (0x1UL << 14) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_SHIFT 14 /**< Shift value for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_MASK 0x4000UL /**< Bit mask for MVP_ARRAY0RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY0RESETDIM2_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0 (0x1UL << 16) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_SHIFT 16 /**< Shift value for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_MASK 0x10000UL /**< Bit mask for MVP_ARRAY1RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM0_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1 (0x1UL << 17) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_SHIFT 17 /**< Shift value for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_MASK 0x20000UL /**< Bit mask for MVP_ARRAY1RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM1_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2 (0x1UL << 18) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_SHIFT 18 /**< Shift value for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_MASK 0x40000UL /**< Bit mask for MVP_ARRAY1RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY1RESETDIM2_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0 (0x1UL << 20) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_SHIFT 20 /**< Shift value for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_MASK 0x100000UL /**< Bit mask for MVP_ARRAY2RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM0_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1 (0x1UL << 21) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_SHIFT 21 /**< Shift value for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_MASK 0x200000UL /**< Bit mask for MVP_ARRAY2RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM1_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2 (0x1UL << 22) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_SHIFT 22 /**< Shift value for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_MASK 0x400000UL /**< Bit mask for MVP_ARRAY2RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY2RESETDIM2_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0 (0x1UL << 24) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_SHIFT 24 /**< Shift value for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_MASK 0x1000000UL /**< Bit mask for MVP_ARRAY3RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM0_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1 (0x1UL << 25) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_SHIFT 25 /**< Shift value for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_MASK 0x2000000UL /**< Bit mask for MVP_ARRAY3RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM1_DEFAULT << 25) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2 (0x1UL << 26) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_SHIFT 26 /**< Shift value for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_MASK 0x4000000UL /**< Bit mask for MVP_ARRAY3RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY3RESETDIM2_DEFAULT << 26) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0 (0x1UL << 28) /**< Reset Dimension 0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_SHIFT 28 /**< Shift value for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_MASK 0x10000000UL /**< Bit mask for MVP_ARRAY4RESETDIM0 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM0_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1 (0x1UL << 29) /**< Reset Dimension 1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_SHIFT 29 /**< Shift value for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_MASK 0x20000000UL /**< Bit mask for MVP_ARRAY4RESETDIM1 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM1_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2 (0x1UL << 30) /**< Reset Dimension 2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_SHIFT 30 /**< Shift value for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_MASK 0x40000000UL /**< Bit mask for MVP_ARRAY4RESETDIM2 */ +#define _MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_LOOPRST */ +#define MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT (_MVP_LOOPRST_ARRAY4RESETDIM2_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_LOOPRST */ + +/* Bit fields for MVP INSTRCFG0 */ +#define _MVP_INSTRCFG0_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_MASK 0x70F7F7F7UL /**< Mask for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN0REGID_SHIFT 0 /**< Shift value for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_MASK 0x7UL /**< Bit mask for MVP_ALUIN0REGID */ +#define _MVP_INSTRCFG0_ALUIN0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO (0x1UL << 4) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_SHIFT 4 /**< Shift value for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_MASK 0x10UL /**< Bit mask for MVP_ALUIN0REALZERO */ +#define _MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALZERO_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE (0x1UL << 5) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_SHIFT 5 /**< Shift value for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_MASK 0x20UL /**< Bit mask for MVP_ALUIN0REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0REALNEGATE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO (0x1UL << 6) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_SHIFT 6 /**< Shift value for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_MASK 0x40UL /**< Bit mask for MVP_ALUIN0IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGZERO_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE (0x1UL << 7) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_SHIFT 7 /**< Shift value for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_MASK 0x80UL /**< Bit mask for MVP_ALUIN0IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN0IMAGNEGATE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN1REGID_SHIFT 8 /**< Shift value for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_MASK 0x700UL /**< Bit mask for MVP_ALUIN1REGID */ +#define _MVP_INSTRCFG0_ALUIN1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN1REGID_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO (0x1UL << 12) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_SHIFT 12 /**< Shift value for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_MASK 0x1000UL /**< Bit mask for MVP_ALUIN1REALZERO */ +#define _MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALZERO_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE (0x1UL << 13) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_SHIFT 13 /**< Shift value for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_MASK 0x2000UL /**< Bit mask for MVP_ALUIN1REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1REALNEGATE_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO (0x1UL << 14) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_SHIFT 14 /**< Shift value for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_MASK 0x4000UL /**< Bit mask for MVP_ALUIN1IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGZERO_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE (0x1UL << 15) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_SHIFT 15 /**< Shift value for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_MASK 0x8000UL /**< Bit mask for MVP_ALUIN1IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN1IMAGNEGATE_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUIN2REGID_SHIFT 16 /**< Shift value for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_MASK 0x70000UL /**< Bit mask for MVP_ALUIN2REGID */ +#define _MVP_INSTRCFG0_ALUIN2REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REGID_DEFAULT (_MVP_INSTRCFG0_ALUIN2REGID_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO (0x1UL << 20) /**< Real Zero */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_SHIFT 20 /**< Shift value for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_MASK 0x100000UL /**< Bit mask for MVP_ALUIN2REALZERO */ +#define _MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALZERO_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE (0x1UL << 21) /**< Real Negate */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_SHIFT 21 /**< Shift value for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_MASK 0x200000UL /**< Bit mask for MVP_ALUIN2REALNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2REALNEGATE_DEFAULT << 21) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO (0x1UL << 22) /**< Imaginary Not Zero */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_SHIFT 22 /**< Shift value for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_MASK 0x400000UL /**< Bit mask for MVP_ALUIN2IMAGZERO */ +#define _MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGZERO_DEFAULT << 22) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE (0x1UL << 23) /**< Imaginary Negate */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_SHIFT 23 /**< Shift value for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_MASK 0x800000UL /**< Bit mask for MVP_ALUIN2IMAGNEGATE */ +#define _MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT (_MVP_INSTRCFG0_ALUIN2IMAGNEGATE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ +#define _MVP_INSTRCFG0_ALUOUTREGID_SHIFT 28 /**< Shift value for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_MASK 0x70000000UL /**< Bit mask for MVP_ALUOUTREGID */ +#define _MVP_INSTRCFG0_ALUOUTREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG0 */ +#define MVP_INSTRCFG0_ALUOUTREGID_DEFAULT (_MVP_INSTRCFG0_ALUOUTREGID_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG0 */ + +/* Bit fields for MVP INSTRCFG1 */ +#define _MVP_INSTRCFG1_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_MASK 0x3FFFFFFFUL /**< Mask for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_SHIFT 0 /**< Shift value for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_MASK 0x7UL /**< Bit mask for MVP_ISTREAM0REGID */ +#define _MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0REGID_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD (0x1UL << 3) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_SHIFT 3 /**< Shift value for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_MASK 0x8UL /**< Bit mask for MVP_ISTREAM0LOAD */ +#define _MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM0LOAD_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_SHIFT 4 /**< Shift value for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_MASK 0x70UL /**< Bit mask for MVP_ISTREAM0ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYID_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0 (0x1UL << 7) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_SHIFT 7 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_MASK 0x80UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM0_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1 (0x1UL << 8) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_SHIFT 8 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_MASK 0x100UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM1_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2 (0x1UL << 9) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_SHIFT 9 /**< Shift value for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_MASK 0x200UL /**< Bit mask for MVP_ISTREAM0ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM0ARRAYINCRDIM2_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_SHIFT 10 /**< Shift value for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_MASK 0x1C00UL /**< Bit mask for MVP_ISTREAM1REGID */ +#define _MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1REGID_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD (0x1UL << 13) /**< Load register */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_SHIFT 13 /**< Shift value for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_MASK 0x2000UL /**< Bit mask for MVP_ISTREAM1LOAD */ +#define _MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT (_MVP_INSTRCFG1_ISTREAM1LOAD_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_SHIFT 14 /**< Shift value for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_MASK 0x1C000UL /**< Bit mask for MVP_ISTREAM1ARRAYID */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYID_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0 (0x1UL << 17) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_SHIFT 17 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_MASK 0x20000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM0_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1 (0x1UL << 18) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_SHIFT 18 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_MASK 0x40000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM1_DEFAULT << 18) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2 (0x1UL << 19) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_SHIFT 19 /**< Shift value for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_MASK 0x80000UL /**< Bit mask for MVP_ISTREAM1ARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_ISTREAM1ARRAYINCRDIM2_DEFAULT << 19) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMREGID_SHIFT 20 /**< Shift value for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_MASK 0x700000UL /**< Bit mask for MVP_OSTREAMREGID */ +#define _MVP_INSTRCFG1_OSTREAMREGID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMREGID_DEFAULT (_MVP_INSTRCFG1_OSTREAMREGID_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE (0x1UL << 23) /**< Store to Register */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_SHIFT 23 /**< Shift value for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_MASK 0x800000UL /**< Bit mask for MVP_OSTREAMSTORE */ +#define _MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT (_MVP_INSTRCFG1_OSTREAMSTORE_DEFAULT << 23) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_SHIFT 24 /**< Shift value for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_MASK 0x7000000UL /**< Bit mask for MVP_OSTREAMARRAYID */ +#define _MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYID_DEFAULT << 24) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0 (0x1UL << 27) /**< Increment Array Dimension 0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_SHIFT 27 /**< Shift value for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_MASK 0x8000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM0 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM0_DEFAULT << 27) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1 (0x1UL << 28) /**< Increment Array Dimension 1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_SHIFT 28 /**< Shift value for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_MASK 0x10000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM1 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM1_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2 (0x1UL << 29) /**< Increment Array Dimension 2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_SHIFT 29 /**< Shift value for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_MASK 0x20000000UL /**< Bit mask for MVP_OSTREAMARRAYINCRDIM2 */ +#define _MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG1 */ +#define MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT (_MVP_INSTRCFG1_OSTREAMARRAYINCRDIM2_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_INSTRCFG1 */ + +/* Bit fields for MVP INSTRCFG2 */ +#define _MVP_INSTRCFG2_RESETVALUE 0x00000000UL /**< Default value for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_MASK 0x9FF0FFFFUL /**< Mask for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN (0x1UL << 0) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_SHIFT 0 /**< Shift value for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_MASK 0x1UL /**< Bit mask for MVP_LOOP0BEGIN */ +#define _MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP0BEGIN_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END (0x1UL << 1) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP0END_SHIFT 1 /**< Shift value for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_MASK 0x2UL /**< Bit mask for MVP_LOOP0END */ +#define _MVP_INSTRCFG2_LOOP0END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP0END_DEFAULT (_MVP_INSTRCFG2_LOOP0END_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN (0x1UL << 2) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_SHIFT 2 /**< Shift value for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_MASK 0x4UL /**< Bit mask for MVP_LOOP1BEGIN */ +#define _MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP1BEGIN_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END (0x1UL << 3) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP1END_SHIFT 3 /**< Shift value for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_MASK 0x8UL /**< Bit mask for MVP_LOOP1END */ +#define _MVP_INSTRCFG2_LOOP1END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP1END_DEFAULT (_MVP_INSTRCFG2_LOOP1END_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN (0x1UL << 4) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_SHIFT 4 /**< Shift value for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_MASK 0x10UL /**< Bit mask for MVP_LOOP2BEGIN */ +#define _MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP2BEGIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END (0x1UL << 5) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP2END_SHIFT 5 /**< Shift value for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_MASK 0x20UL /**< Bit mask for MVP_LOOP2END */ +#define _MVP_INSTRCFG2_LOOP2END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP2END_DEFAULT (_MVP_INSTRCFG2_LOOP2END_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN (0x1UL << 6) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_SHIFT 6 /**< Shift value for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_MASK 0x40UL /**< Bit mask for MVP_LOOP3BEGIN */ +#define _MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP3BEGIN_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END (0x1UL << 7) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP3END_SHIFT 7 /**< Shift value for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_MASK 0x80UL /**< Bit mask for MVP_LOOP3END */ +#define _MVP_INSTRCFG2_LOOP3END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP3END_DEFAULT (_MVP_INSTRCFG2_LOOP3END_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN (0x1UL << 8) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_SHIFT 8 /**< Shift value for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_MASK 0x100UL /**< Bit mask for MVP_LOOP4BEGIN */ +#define _MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP4BEGIN_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END (0x1UL << 9) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP4END_SHIFT 9 /**< Shift value for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_MASK 0x200UL /**< Bit mask for MVP_LOOP4END */ +#define _MVP_INSTRCFG2_LOOP4END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP4END_DEFAULT (_MVP_INSTRCFG2_LOOP4END_DEFAULT << 9) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN (0x1UL << 10) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_SHIFT 10 /**< Shift value for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_MASK 0x400UL /**< Bit mask for MVP_LOOP5BEGIN */ +#define _MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP5BEGIN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END (0x1UL << 11) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP5END_SHIFT 11 /**< Shift value for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_MASK 0x800UL /**< Bit mask for MVP_LOOP5END */ +#define _MVP_INSTRCFG2_LOOP5END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP5END_DEFAULT (_MVP_INSTRCFG2_LOOP5END_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN (0x1UL << 12) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_SHIFT 12 /**< Shift value for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_MASK 0x1000UL /**< Bit mask for MVP_LOOP6BEGIN */ +#define _MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP6BEGIN_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END (0x1UL << 13) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP6END_SHIFT 13 /**< Shift value for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_MASK 0x2000UL /**< Bit mask for MVP_LOOP6END */ +#define _MVP_INSTRCFG2_LOOP6END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP6END_DEFAULT (_MVP_INSTRCFG2_LOOP6END_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN (0x1UL << 14) /**< Loop Begin */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_SHIFT 14 /**< Shift value for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_MASK 0x4000UL /**< Bit mask for MVP_LOOP7BEGIN */ +#define _MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT (_MVP_INSTRCFG2_LOOP7BEGIN_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END (0x1UL << 15) /**< Loop End */ +#define _MVP_INSTRCFG2_LOOP7END_SHIFT 15 /**< Shift value for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_MASK 0x8000UL /**< Bit mask for MVP_LOOP7END */ +#define _MVP_INSTRCFG2_LOOP7END_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_LOOP7END_DEFAULT (_MVP_INSTRCFG2_LOOP7END_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SHIFT 20 /**< Shift value for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_MASK 0x1FF00000UL /**< Bit mask for MVP_ALUOP */ +#define _MVP_INSTRCFG2_ALUOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NOOP 0x00000000UL /**< Mode NOOP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLEAR 0x00000001UL /**< Mode CLEAR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_COPY 0x00000041UL /**< Mode COPY for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SWAP 0x00000042UL /**< Mode SWAP for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DBL 0x00000043UL /**< Mode DBL for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANA 0x00000044UL /**< Mode FANA for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_FANB 0x00000045UL /**< Mode FANB for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RELU2 0x00000046UL /**< Mode RELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_NRELU2 0x00000047UL /**< Mode NRELU2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_INC2 0x00000048UL /**< Mode INC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_DEC2 0x00000049UL /**< Mode DEC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR 0x0000004AUL /**< Mode ADDR for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX 0x0000004BUL /**< Mode MAX for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN 0x0000004CUL /**< Mode MIN for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_RSQR2B 0x00000124UL /**< Mode RSQR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDC 0x0000014EUL /**< Mode ADDC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2A 0x00000153UL /**< Mode MAX2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2A 0x00000154UL /**< Mode MIN2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XREALC2 0x0000015EUL /**< Mode XREALC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_XIMAGC2 0x0000015FUL /**< Mode XIMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR2B 0x00000161UL /**< Mode ADDR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX2B 0x00000162UL /**< Mode MAX2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN2B 0x00000163UL /**< Mode MIN2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULC 0x0000018DUL /**< Mode MULC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2A 0x00000197UL /**< Mode MULR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MULR2B 0x00000198UL /**< Mode MULR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ADDR4 0x0000019AUL /**< Mode ADDR4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAX4 0x0000019BUL /**< Mode MAX4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MIN4 0x0000019CUL /**< Mode MIN4 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_SQRMAGC2 0x0000019DUL /**< Mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_PRELU2B 0x000001A0UL /**< Mode PRELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACC 0x000001CDUL /**< Mode MACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_AACC 0x000001CEUL /**< Mode AACC for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2A 0x000001CFUL /**< Mode ELU2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_ELU2B 0x000001D0UL /**< Mode ELU2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2A 0x000001D1UL /**< Mode IFR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFR2B 0x000001D2UL /**< Mode IFR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MAXAC2 0x000001D3UL /**< Mode MAXAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MINAC2 0x000001D4UL /**< Mode MINAC2 for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2A 0x000001D5UL /**< Mode CLIP2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_CLIP2B 0x000001D6UL /**< Mode CLIP2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2A 0x000001D7UL /**< Mode MACR2A for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_MACR2B 0x000001D8UL /**< Mode MACR2B for MVP_INSTRCFG2 */ +#define _MVP_INSTRCFG2_ALUOP_IFC 0x000001D9UL /**< Mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEFAULT (_MVP_INSTRCFG2_ALUOP_DEFAULT << 20) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NOOP (_MVP_INSTRCFG2_ALUOP_NOOP << 20) /**< Shifted mode NOOP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLEAR (_MVP_INSTRCFG2_ALUOP_CLEAR << 20) /**< Shifted mode CLEAR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_COPY (_MVP_INSTRCFG2_ALUOP_COPY << 20) /**< Shifted mode COPY for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SWAP (_MVP_INSTRCFG2_ALUOP_SWAP << 20) /**< Shifted mode SWAP for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DBL (_MVP_INSTRCFG2_ALUOP_DBL << 20) /**< Shifted mode DBL for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANA (_MVP_INSTRCFG2_ALUOP_FANA << 20) /**< Shifted mode FANA for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_FANB (_MVP_INSTRCFG2_ALUOP_FANB << 20) /**< Shifted mode FANB for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RELU2 (_MVP_INSTRCFG2_ALUOP_RELU2 << 20) /**< Shifted mode RELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_NRELU2 (_MVP_INSTRCFG2_ALUOP_NRELU2 << 20) /**< Shifted mode NRELU2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_INC2 (_MVP_INSTRCFG2_ALUOP_INC2 << 20) /**< Shifted mode INC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_DEC2 (_MVP_INSTRCFG2_ALUOP_DEC2 << 20) /**< Shifted mode DEC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR (_MVP_INSTRCFG2_ALUOP_ADDR << 20) /**< Shifted mode ADDR for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX (_MVP_INSTRCFG2_ALUOP_MAX << 20) /**< Shifted mode MAX for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN (_MVP_INSTRCFG2_ALUOP_MIN << 20) /**< Shifted mode MIN for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_RSQR2B (_MVP_INSTRCFG2_ALUOP_RSQR2B << 20) /**< Shifted mode RSQR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDC (_MVP_INSTRCFG2_ALUOP_ADDC << 20) /**< Shifted mode ADDC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2A (_MVP_INSTRCFG2_ALUOP_MAX2A << 20) /**< Shifted mode MAX2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2A (_MVP_INSTRCFG2_ALUOP_MIN2A << 20) /**< Shifted mode MIN2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XREALC2 (_MVP_INSTRCFG2_ALUOP_XREALC2 << 20) /**< Shifted mode XREALC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_XIMAGC2 (_MVP_INSTRCFG2_ALUOP_XIMAGC2 << 20) /**< Shifted mode XIMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR2B (_MVP_INSTRCFG2_ALUOP_ADDR2B << 20) /**< Shifted mode ADDR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX2B (_MVP_INSTRCFG2_ALUOP_MAX2B << 20) /**< Shifted mode MAX2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN2B (_MVP_INSTRCFG2_ALUOP_MIN2B << 20) /**< Shifted mode MIN2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULC (_MVP_INSTRCFG2_ALUOP_MULC << 20) /**< Shifted mode MULC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2A (_MVP_INSTRCFG2_ALUOP_MULR2A << 20) /**< Shifted mode MULR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MULR2B (_MVP_INSTRCFG2_ALUOP_MULR2B << 20) /**< Shifted mode MULR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ADDR4 (_MVP_INSTRCFG2_ALUOP_ADDR4 << 20) /**< Shifted mode ADDR4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAX4 (_MVP_INSTRCFG2_ALUOP_MAX4 << 20) /**< Shifted mode MAX4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MIN4 (_MVP_INSTRCFG2_ALUOP_MIN4 << 20) /**< Shifted mode MIN4 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_SQRMAGC2 (_MVP_INSTRCFG2_ALUOP_SQRMAGC2 << 20) /**< Shifted mode SQRMAGC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_PRELU2B (_MVP_INSTRCFG2_ALUOP_PRELU2B << 20) /**< Shifted mode PRELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACC (_MVP_INSTRCFG2_ALUOP_MACC << 20) /**< Shifted mode MACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_AACC (_MVP_INSTRCFG2_ALUOP_AACC << 20) /**< Shifted mode AACC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2A (_MVP_INSTRCFG2_ALUOP_ELU2A << 20) /**< Shifted mode ELU2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_ELU2B (_MVP_INSTRCFG2_ALUOP_ELU2B << 20) /**< Shifted mode ELU2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2A (_MVP_INSTRCFG2_ALUOP_IFR2A << 20) /**< Shifted mode IFR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFR2B (_MVP_INSTRCFG2_ALUOP_IFR2B << 20) /**< Shifted mode IFR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MAXAC2 (_MVP_INSTRCFG2_ALUOP_MAXAC2 << 20) /**< Shifted mode MAXAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MINAC2 (_MVP_INSTRCFG2_ALUOP_MINAC2 << 20) /**< Shifted mode MINAC2 for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2A (_MVP_INSTRCFG2_ALUOP_CLIP2A << 20) /**< Shifted mode CLIP2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_CLIP2B (_MVP_INSTRCFG2_ALUOP_CLIP2B << 20) /**< Shifted mode CLIP2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2A (_MVP_INSTRCFG2_ALUOP_MACR2A << 20) /**< Shifted mode MACR2A for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_MACR2B (_MVP_INSTRCFG2_ALUOP_MACR2B << 20) /**< Shifted mode MACR2B for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ALUOP_IFC (_MVP_INSTRCFG2_ALUOP_IFC << 20) /**< Shifted mode IFC for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG (0x1UL << 31) /**< End of Program */ +#define _MVP_INSTRCFG2_ENDPROG_SHIFT 31 /**< Shift value for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_MASK 0x80000000UL /**< Bit mask for MVP_ENDPROG */ +#define _MVP_INSTRCFG2_ENDPROG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_INSTRCFG2 */ +#define MVP_INSTRCFG2_ENDPROG_DEFAULT (_MVP_INSTRCFG2_ENDPROG_DEFAULT << 31) /**< Shifted mode DEFAULT for MVP_INSTRCFG2 */ + +/* Bit fields for MVP CMD */ +#define _MVP_CMD_RESETVALUE 0x00000000UL /**< Default value for MVP_CMD */ +#define _MVP_CMD_MASK 0x0000000FUL /**< Mask for MVP_CMD */ +#define MVP_CMD_START (0x1UL << 0) /**< Start Command */ +#define _MVP_CMD_START_SHIFT 0 /**< Shift value for MVP_START */ +#define _MVP_CMD_START_MASK 0x1UL /**< Bit mask for MVP_START */ +#define _MVP_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_START_DEFAULT (_MVP_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT (0x1UL << 1) /**< Halt Command */ +#define _MVP_CMD_HALT_SHIFT 1 /**< Shift value for MVP_HALT */ +#define _MVP_CMD_HALT_MASK 0x2UL /**< Bit mask for MVP_HALT */ +#define _MVP_CMD_HALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_HALT_DEFAULT (_MVP_CMD_HALT_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP (0x1UL << 2) /**< Step Command */ +#define _MVP_CMD_STEP_SHIFT 2 /**< Shift value for MVP_STEP */ +#define _MVP_CMD_STEP_MASK 0x4UL /**< Bit mask for MVP_STEP */ +#define _MVP_CMD_STEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_STEP_DEFAULT (_MVP_CMD_STEP_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT (0x1UL << 3) /**< Initialization Command/Qualifier */ +#define _MVP_CMD_INIT_SHIFT 3 /**< Shift value for MVP_INIT */ +#define _MVP_CMD_INIT_MASK 0x8UL /**< Bit mask for MVP_INIT */ +#define _MVP_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_CMD */ +#define MVP_CMD_INIT_DEFAULT (_MVP_CMD_INIT_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_CMD */ + +/* Bit fields for MVP DEBUGEN */ +#define _MVP_DEBUGEN_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGEN */ +#define _MVP_DEBUGEN_MASK 0x7003FDFEUL /**< Mask for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE (0x1UL << 1) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_SHIFT 1 /**< Shift value for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_MASK 0x2UL /**< Bit mask for MVP_BKPTLOOP0DONE */ +#define _MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP0DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE (0x1UL << 2) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_SHIFT 2 /**< Shift value for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_MASK 0x4UL /**< Bit mask for MVP_BKPTLOOP1DONE */ +#define _MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP1DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE (0x1UL << 3) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_SHIFT 3 /**< Shift value for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_MASK 0x8UL /**< Bit mask for MVP_BKPTLOOP2DONE */ +#define _MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP2DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE (0x1UL << 4) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_SHIFT 4 /**< Shift value for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_MASK 0x10UL /**< Bit mask for MVP_BKPTLOOP3DONE */ +#define _MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP3DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE (0x1UL << 5) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_SHIFT 5 /**< Shift value for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_MASK 0x20UL /**< Bit mask for MVP_BKPTLOOP4DONE */ +#define _MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP4DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE (0x1UL << 6) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_SHIFT 6 /**< Shift value for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_MASK 0x40UL /**< Bit mask for MVP_BKPTLOOP5DONE */ +#define _MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP5DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE (0x1UL << 7) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_SHIFT 7 /**< Shift value for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_MASK 0x80UL /**< Bit mask for MVP_BKPTLOOP6DONE */ +#define _MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP6DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE (0x1UL << 8) /**< Enable Breakpoint on Loop Done */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_SHIFT 8 /**< Shift value for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_MASK 0x100UL /**< Bit mask for MVP_BKPTLOOP7DONE */ +#define _MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT (_MVP_DEBUGEN_BKPTLOOP7DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN (0x1UL << 10) /**< Enable Breakpoint on ALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_SHIFT 10 /**< Shift value for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_MASK 0x400UL /**< Bit mask for MVP_BKPTALUNAN */ +#define _MVP_DEBUGEN_BKPTALUNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUNAN_DEFAULT (_MVP_DEBUGEN_BKPTALUNAN_DEFAULT << 10) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL (0x1UL << 11) /**< Enable Breakpoint on R0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_SHIFT 11 /**< Shift value for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_MASK 0x800UL /**< Bit mask for MVP_BKPTR0POSREAL */ +#define _MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT (_MVP_DEBUGEN_BKPTR0POSREAL_DEFAULT << 11) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF (0x1UL << 12) /**< Enable Breakpoint on ALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_SHIFT 12 /**< Shift value for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_MASK 0x1000UL /**< Bit mask for MVP_BKPTALUOF */ +#define _MVP_DEBUGEN_BKPTALUOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUOF_DEFAULT (_MVP_DEBUGEN_BKPTALUOF_DEFAULT << 12) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF (0x1UL << 13) /**< Enable Breakpoint on ALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_SHIFT 13 /**< Shift value for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_MASK 0x2000UL /**< Bit mask for MVP_BKPTALUUF */ +#define _MVP_DEBUGEN_BKPTALUUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTALUUF_DEFAULT (_MVP_DEBUGEN_BKPTALUUF_DEFAULT << 13) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF (0x1UL << 14) /**< Enable Breakpoint on STORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_SHIFT 14 /**< Shift value for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_MASK 0x4000UL /**< Bit mask for MVP_BKPTSTORECONVERTOF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTOF_DEFAULT << 14) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF (0x1UL << 15) /**< Enable Breakpoint on STORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_SHIFT 15 /**< Shift value for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_MASK 0x8000UL /**< Bit mask for MVP_BKPTSTORECONVERTUF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTUF_DEFAULT << 15) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF (0x1UL << 16) /**< Enable Breakpoint on STORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_SHIFT 16 /**< Shift value for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_MASK 0x10000UL /**< Bit mask for MVP_BKPTSTORECONVERTINF */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTINF_DEFAULT << 16) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN (0x1UL << 17) /**< Enable Breakpoint on STORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_SHIFT 17 /**< Shift value for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_MASK 0x20000UL /**< Bit mask for MVP_BKPTSTORECONVERTNAN */ +#define _MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT (_MVP_DEBUGEN_BKPTSTORECONVERTNAN_DEFAULT << 17) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN (0x1UL << 28) /**< Debug Step Count Enable */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_SHIFT 28 /**< Shift value for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_MASK 0x10000000UL /**< Bit mask for MVP_DEBUGSTEPCNTEN */ +#define _MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT (_MVP_DEBUGEN_DEBUGSTEPCNTEN_DEFAULT << 28) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN (0x1UL << 29) /**< Trigger Breakpoint when ALL conditions match*/ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_SHIFT 29 /**< Shift value for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_MASK 0x20000000UL /**< Bit mask for MVP_DEBUGBKPTALLEN */ +#define _MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTALLEN_DEFAULT << 29) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN (0x1UL << 30) /**< Enable Breakpoint when ANY conditions match */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_SHIFT 30 /**< Shift value for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_MASK 0x40000000UL /**< Bit mask for MVP_DEBUGBKPTANYEN */ +#define _MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGEN */ +#define MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT (_MVP_DEBUGEN_DEBUGBKPTANYEN_DEFAULT << 30) /**< Shifted mode DEFAULT for MVP_DEBUGEN */ + +/* Bit fields for MVP DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_RESETVALUE 0x00000000UL /**< Default value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_MASK 0x00FFFFFFUL /**< Mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_SHIFT 0 /**< Shift value for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_MASK 0xFFFFFFUL /**< Bit mask for MVP_DEBUGSTEPCNT */ +#define _MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MVP_DEBUGSTEPCNT */ +#define MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT (_MVP_DEBUGSTEPCNT_DEBUGSTEPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for MVP_DEBUGSTEPCNT */ + +/** @} End of group EFR32MG24_MVP_BitFields */ +/** @} End of group EFR32MG24_MVP */ +/** @} End of group Parts */ + +#endif // EFR32MG24_MVP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h index c2ba4e8..f158b0e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_pcnt.h @@ -1,482 +1,482 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 PCNT register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_PCNT_H -#define EFR32MG24_PCNT_H -#define PCNT_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_PCNT PCNT - * @{ - * @brief EFR32MG24 PCNT Register Declaration. - *****************************************************************************/ - -/** PCNT Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP; /**< Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_SET; /**< Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED1[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_CLR; /**< Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED2[1008U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ - __IOM uint32_t TOP_TGL; /**< Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ -} PCNT_TypeDef; -/** @} End of group EFR32MG24_PCNT */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_PCNT - * @{ - * @defgroup EFR32MG24_PCNT_BitFields PCNT Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for PCNT IPVERSION */ -#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ -#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ -#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ - -/* Bit fields for PCNT EN */ -#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ -#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ -#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ -#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ -#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ -#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ -#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ -#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ -#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ -#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ -#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ - -/* Bit fields for PCNT SWRST */ -#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ -#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ -#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ -#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ -#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ -#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ -#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ -#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ -#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ -#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ - -/* Bit fields for PCNT CFG */ -#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ -#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ -#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ -#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ -#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ -#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ -#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ -#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ -#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ -#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ -#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ -#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ -#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ -#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ -#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ -#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ -#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ -#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ -#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ -#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ -#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ -#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ -#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ -#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ -#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ -#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ -#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ -#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ -#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ -#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ -#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ -#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ -#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ -#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ -#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ -#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ -#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ - -/* Bit fields for PCNT CTRL */ -#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ -#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ -#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ -#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ -#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ -#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ -#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ -#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ -#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ -#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ -#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ -#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ -#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ -#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ -#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ -#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ -#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ -#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ -#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ -#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ -#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ -#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ -#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ -#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ -#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ -#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ -#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ -#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ -#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ -#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ -#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ -#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ -#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ -#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ -#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ -#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ -#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ -#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ -#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ -#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ - -/* Bit fields for PCNT CMD */ -#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ -#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ -#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ -#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ -#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ -#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ -#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ -#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ -#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ -#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ -#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ -#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ -#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ -#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ -#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ -#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ -#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ -#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ -#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ -#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ -#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ -#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ -#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ -#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ -#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ -#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ -#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ -#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ - -/* Bit fields for PCNT STATUS */ -#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ -#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ -#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ -#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ -#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ -#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ -#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ -#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ -#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ -#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ -#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ -#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ -#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ -#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ -#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ -#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ -#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ - -/* Bit fields for PCNT IF */ -#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ -#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ -#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ -#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ -#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ -#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ -#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ -#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ -#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ -#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ -#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ -#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ -#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ -#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ -#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ -#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ -#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ -#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ -#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ -#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ -#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ -#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ -#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ -#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ -#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ -#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ - -/* Bit fields for PCNT IEN */ -#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ -#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ -#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ -#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ -#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ -#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ -#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ -#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ -#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ -#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ -#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ -#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ -#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ -#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ -#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ -#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ -#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ -#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ - -/* Bit fields for PCNT CNT */ -#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ -#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ -#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ -#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ -#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ -#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ - -/* Bit fields for PCNT AUXCNT */ -#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ -#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ -#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ -#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ -#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ -#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ - -/* Bit fields for PCNT TOP */ -#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ -#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ -#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ -#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ -#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ -#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ - -/* Bit fields for PCNT TOPB */ -#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ -#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ -#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ -#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ -#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ -#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ - -/* Bit fields for PCNT OVSCTRL */ -#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ -#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ -#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ -#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ -#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ -#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ -#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ -#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ -#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ -#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ -#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ - -/* Bit fields for PCNT SYNCBUSY */ -#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ -#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ -#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ -#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ -#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ -#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ -#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ -#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ -#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ -#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ -#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ -#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ -#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ -#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ -#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ -#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ -#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ -#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ - -/* Bit fields for PCNT LOCK */ -#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ -#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ -#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ -#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ -#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ -#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ -#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ -#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ - -/** @} End of group EFR32MG24_PCNT_BitFields */ -/** @} End of group EFR32MG24_PCNT */ -/** @} End of group Parts */ - -#endif // EFR32MG24_PCNT_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 PCNT register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PCNT_H +#define EFR32MG24_PCNT_H +#define PCNT_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_PCNT PCNT + * @{ + * @brief EFR32MG24 PCNT Register Declaration. + *****************************************************************************/ + +/** PCNT Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP; /**< Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_SET; /**< Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED1[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_CLR; /**< Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED2[1008U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ + __IOM uint32_t TOP_TGL; /**< Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} PCNT_TypeDef; +/** @} End of group EFR32MG24_PCNT */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_PCNT + * @{ + * @defgroup EFR32MG24_PCNT_BitFields PCNT Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PCNT IPVERSION */ +#define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ +#define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ +#define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ + +/* Bit fields for PCNT EN */ +#define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ +#define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ +#define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ +#define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ +#define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ +#define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ +#define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ +#define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ + +/* Bit fields for PCNT SWRST */ +#define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ +#define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ +#define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ +#define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ +#define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ +#define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ + +/* Bit fields for PCNT CFG */ +#define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ +#define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ +#define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ +#define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ +#define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ +#define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ +#define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ +#define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ +#define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ +#define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ +#define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ +#define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ +#define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ +#define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ +#define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ +#define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ +#define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ +#define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ +#define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ +#define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ +#define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ +#define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ +#define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ +#define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ + +/* Bit fields for PCNT CTRL */ +#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ +#define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ +#define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ +#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ +#define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ +#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ +#define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ +#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ +#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ +#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ +#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ +#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ +#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ +#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ + +/* Bit fields for PCNT CMD */ +#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ +#define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ +#define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ +#define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ +#define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ +#define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ +#define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ +#define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ +#define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ +#define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ +#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ +#define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ +#define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ +#define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ +#define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ +#define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ +#define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ +#define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ +#define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ +#define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ + +/* Bit fields for PCNT STATUS */ +#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ +#define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ +#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ +#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ +#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ +#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ +#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ +#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ +#define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ +#define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ +#define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ +#define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ +#define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ +#define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ +#define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ +#define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ +#define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ + +/* Bit fields for PCNT IF */ +#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ +#define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ +#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ +#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ + +/* Bit fields for PCNT IEN */ +#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ +#define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ +#define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ +#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ +#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ +#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ +#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ +#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ +#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ +#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ +#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ +#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ +#define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ +#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ +#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ + +/* Bit fields for PCNT CNT */ +#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ +#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ +#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ +#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ +#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ + +/* Bit fields for PCNT AUXCNT */ +#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ +#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ +#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ + +/* Bit fields for PCNT TOP */ +#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ +#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ +#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ +#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ +#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ + +/* Bit fields for PCNT TOPB */ +#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ +#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ +#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ + +/* Bit fields for PCNT OVSCTRL */ +#define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ +#define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ +#define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ +#define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ +#define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ +#define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ + +/* Bit fields for PCNT SYNCBUSY */ +#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ +#define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ +#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ +#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ +#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ +#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ +#define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ +#define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ +#define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ +#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ +#define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ +#define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ +#define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ + +/* Bit fields for PCNT LOCK */ +#define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ +#define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ +#define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ +#define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ +#define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ + +/** @} End of group EFR32MG24_PCNT_BitFields */ +/** @} End of group EFR32MG24_PCNT */ +/** @} End of group Parts */ + +#endif // EFR32MG24_PCNT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h index 0692d2d..7838462 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs.h @@ -1,1621 +1,1621 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 PRS register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_PRS_H -#define EFR32MG24_PRS_H -#define PRS_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_PRS PRS - * @{ - * @brief EFR32MG24 PRS Register Declaration. - *****************************************************************************/ - -/** PRS ASYNC_CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t CTRL; /**< Async Channel Control Register */ -} PRS_ASYNC_CH_TypeDef; - -/** PRS SYNC_CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t CTRL; /**< Sync Channel Control Register */ -} PRS_SYNC_CH_TypeDef; - -/** PRS Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< PRS IPVERSION */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH[16U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ - __IOM uint32_t CONSUMER_MODEM_PAEN; /**< PAEN Consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ - uint32_t RESERVED2[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ - uint32_t RESERVED3[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[892U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[16U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ - __IOM uint32_t CONSUMER_MODEM_PAEN_SET; /**< PAEN Consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ - uint32_t RESERVED8[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[892U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[16U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ - __IOM uint32_t CONSUMER_MODEM_PAEN_CLR; /**< PAEN Consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ - uint32_t RESERVED14[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[892U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[16U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ - __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ - __IOM uint32_t CONSUMER_MODEM_PAEN_TGL; /**< PAEN Consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ - __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ - uint32_t RESERVED20[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ - __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ - __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ - __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ - __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ - __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ - __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ - __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ - __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ - __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ - __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ - uint32_t RESERVED21[3U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ - __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ - __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ -} PRS_TypeDef; -/** @} End of group EFR32MG24_PRS */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_PRS - * @{ - * @defgroup EFR32MG24_PRS_BitFields PRS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for PRS IPVERSION */ -#define _PRS_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for PRS_IPVERSION */ -#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for PRS_IPVERSION */ -#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ - -/* Bit fields for PRS ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ -#define _PRS_ASYNC_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ -#define _PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ -#define _PRS_ASYNC_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ -#define _PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ -#define _PRS_ASYNC_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ -#define _PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ -#define _PRS_ASYNC_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ -#define _PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ - -/* Bit fields for PRS ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ - -/* Bit fields for PRS ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ -#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ -#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ -#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ -#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ -#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ -#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ -#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ -#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ -#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ -#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ -#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ -#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ -#define _PRS_ASYNC_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ -#define _PRS_ASYNC_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ -#define _PRS_ASYNC_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH12VAL_DEFAULT (_PRS_ASYNC_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 current value */ -#define _PRS_ASYNC_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ -#define _PRS_ASYNC_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ -#define _PRS_ASYNC_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH13VAL_DEFAULT (_PRS_ASYNC_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 current value */ -#define _PRS_ASYNC_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ -#define _PRS_ASYNC_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ -#define _PRS_ASYNC_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH14VAL_DEFAULT (_PRS_ASYNC_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 current value */ -#define _PRS_ASYNC_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ -#define _PRS_ASYNC_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ -#define _PRS_ASYNC_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH15VAL_DEFAULT (_PRS_ASYNC_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ - -/* Bit fields for PRS SYNC_PEEK */ -#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ -#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ - -/* Bit fields for PRS ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ - -/* Bit fields for PRS SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ - -/* Bit fields for PRS CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ -#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ - -/* Bit fields for PRS CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ -#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ - -/* Bit fields for PRS CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ -#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ - -/* Bit fields for PRS CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ -#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ - -/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ -#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ -#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ - -/* Bit fields for PRS CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ -#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ - -/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ -#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ - -/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ - -/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ - -/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ -#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ -#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ -#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ -#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ - -/* Bit fields for PRS CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ -#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ - -/* Bit fields for PRS CONSUMER_MODEM_PAEN */ -#define _PRS_CONSUMER_MODEM_PAEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_PAEN */ -#define _PRS_CONSUMER_MODEM_PAEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_PAEN */ -#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_PAEN */ -#define PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_PAEN*/ - -/* Bit fields for PRS CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ -#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ - -/* Bit fields for PRS CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ -#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ - -/* Bit fields for PRS CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ -#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ -#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ -#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ -#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ -#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ - -/* Bit fields for PRS CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ -#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ - -/* Bit fields for PRS CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ -#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ - -/* Bit fields for PRS CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ -#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ - -/* Bit fields for PRS CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ -#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ - -/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ -#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ - -/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ -#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ - -/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ -#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ - -/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ -#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ - -/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ -#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ -#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ -#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ -#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ -#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ - -/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ -#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ -#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ -#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ -#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ -#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ -#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ -#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ -#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ -#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ -#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ -#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ -#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ -#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ -#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ -#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ -#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ -#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ - -/* Bit fields for PRS CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ -#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ - -/* Bit fields for PRS CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ -#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ - -/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ -#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ -#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ - -/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ - -/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ - -/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ - -/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ - -/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ - -/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH0 */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ -#define PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ - -/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH1 */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ -#define PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ - -/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ -#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ - -/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ -#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ - -/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ -#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ - -/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ -#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ - -/** @} End of group EFR32MG24_PRS_BitFields */ -/** @} End of group EFR32MG24_PRS */ -/** @} End of group Parts */ - -#endif // EFR32MG24_PRS_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PRS_H +#define EFR32MG24_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_PRS PRS + * @{ + * @brief EFR32MG24 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< PRS IPVERSION */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN; /**< S1IN Consumer register */ + uint32_t RESERVED2[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< TRIGGER Consumer register */ + uint32_t RESERVED3[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1; /**< SRC1 Consumer register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< PRS IPVERSION */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_SET; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_SET; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_SET; /**< S1IN Consumer register */ + uint32_t RESERVED8[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_SET; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_SET; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_SET; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_SET; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_SET; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_SET; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_SET; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_SET; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_SET; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_SET; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_SET; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< TRIGGER Consumer register */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_SET; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_SET; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_SET; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_SET; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_SET; /**< SRC1 Consumer register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< PRS IPVERSION */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_CLR; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_CLR; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_CLR; /**< S1IN Consumer register */ + uint32_t RESERVED14[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_CLR; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_CLR; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_CLR; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_CLR; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_CLR; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_CLR; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_CLR; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_CLR; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_CLR; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_CLR; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_CLR; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< TRIGGER Consumer register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_CLR; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_CLR; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_CLR; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_CLR; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_CLR; /**< SRC1 Consumer register */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[892U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< PRS IPVERSION */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[16U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CALDN consumer register */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CALUP Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_EUSART1_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_EUSART1_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< SCAN consumer register */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< SINGLE Consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 consumer register */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< CLEAR consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< START Consumer register */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< STOP Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< DIN consumer register */ + __IOM uint32_t CONSUMER_MODEM_PAEN_TGL; /**< PAEN Consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S0IN_TGL; /**< S0IN consumer register */ + __IOM uint32_t CONSUMER_PCNT0_S1IN_TGL; /**< S1IN Consumer register */ + uint32_t RESERVED20[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< CLR consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< CTI Consumer register */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< FORCETX Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RXDIS Consumer register */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RXEN Consumer register */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< TXEN Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC25_TGL; /**< TAMPERSRC25 consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC26_TGL; /**< TAMPERSRC26 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC27_TGL; /**< TAMPERSRC27 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC28_TGL; /**< TAMPERSRC28 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC29_TGL; /**< TAMPERSRC29 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC30_TGL; /**< TAMPERSRC30 Consumer register */ + __IOM uint32_t CONSUMER_SETAMPER_TAMPERSRC31_TGL; /**< TAMPERSRC31 Consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN0_TGL; /**< IN0 consumer register */ + __IOM uint32_t CONSUMER_SYSRTC0_IN1_TGL; /**< IN1 Consumer register */ + __IOM uint32_t CONSUMER_HFXO0_OSCREQ_TGL; /**< OSCREQ consumer register */ + __IOM uint32_t CONSUMER_HFXO0_TIMEOUT_TGL; /**< TIMEOUT Consumer register */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< CC0 consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< CC1 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< CC2 Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< DTI Consumer register */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< CLK consumer register */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< IR Consumer register */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< RX Consumer register */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< TRIGGER Consumer register */ + uint32_t RESERVED21[3U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC0_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC0_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH0_TGL; /**< ASYNCTRIG consumer register */ + __IOM uint32_t CONSUMER_VDAC1_ASYNCTRIGCH1_TGL; /**< ASYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH0_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_VDAC1_SYNCTRIGCH1_TGL; /**< SYNCTRIG Consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< SRC1 Consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC0_TGL; /**< SRC0 consumer register */ + __IOM uint32_t CONSUMER_WDOG1_SRC1_TGL; /**< SRC1 Consumer register */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ +} PRS_TypeDef; +/** @} End of group EFR32MG24_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_PRS + * @{ + * @defgroup EFR32MG24_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE (0x1UL << 12) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_SHIFT 12 /**< Shift value for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_MASK 0x1000UL /**< Bit mask for PRS_CH12PULSE */ +#define _PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH12PULSE_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE (0x1UL << 13) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_SHIFT 13 /**< Shift value for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_MASK 0x2000UL /**< Bit mask for PRS_CH13PULSE */ +#define _PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH13PULSE_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE (0x1UL << 14) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_SHIFT 14 /**< Shift value for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_MASK 0x4000UL /**< Bit mask for PRS_CH14PULSE */ +#define _PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH14PULSE_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE (0x1UL << 15) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_SHIFT 15 /**< Shift value for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_MASK 0x8000UL /**< Bit mask for PRS_CH15PULSE */ +#define _PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH15PULSE_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL (0x1UL << 12) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_SHIFT 12 /**< Shift value for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_MASK 0x1000UL /**< Bit mask for PRS_CH12LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH12LEVEL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL (0x1UL << 13) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_SHIFT 13 /**< Shift value for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_MASK 0x2000UL /**< Bit mask for PRS_CH13LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH13LEVEL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL (0x1UL << 14) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_SHIFT 14 /**< Shift value for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_MASK 0x4000UL /**< Bit mask for PRS_CH14LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH14LEVEL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL (0x1UL << 15) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_SHIFT 15 /**< Shift value for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_MASK 0x8000UL /**< Bit mask for PRS_CH15LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH15LEVEL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x0000FFFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL (0x1UL << 12) /**< Channel 12 Current Value */ +#define _PRS_ASYNC_PEEK_CH12VAL_SHIFT 12 /**< Shift value for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_MASK 0x1000UL /**< Bit mask for PRS_CH12VAL */ +#define _PRS_ASYNC_PEEK_CH12VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH12VAL_DEFAULT (_PRS_ASYNC_PEEK_CH12VAL_DEFAULT << 12) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL (0x1UL << 13) /**< Channel 13 current value */ +#define _PRS_ASYNC_PEEK_CH13VAL_SHIFT 13 /**< Shift value for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_MASK 0x2000UL /**< Bit mask for PRS_CH13VAL */ +#define _PRS_ASYNC_PEEK_CH13VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH13VAL_DEFAULT (_PRS_ASYNC_PEEK_CH13VAL_DEFAULT << 13) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL (0x1UL << 14) /**< Channel 14 current value */ +#define _PRS_ASYNC_PEEK_CH14VAL_SHIFT 14 /**< Shift value for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_MASK 0x4000UL /**< Bit mask for PRS_CH14VAL */ +#define _PRS_ASYNC_PEEK_CH14VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH14VAL_DEFAULT (_PRS_ASYNC_PEEK_CH14VAL_DEFAULT << 14) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL (0x1UL << 15) /**< Channel 15 current value */ +#define _PRS_ASYNC_PEEK_CH15VAL_SHIFT 15 /**< Shift value for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_MASK 0x8000UL /**< Bit mask for PRS_CH15VAL */ +#define _PRS_ASYNC_PEEK_CH15VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH15VAL_DEFAULT (_PRS_ASYNC_PEEK_CH15VAL_DEFAULT << 15) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_NONE (_PRS_SYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_CLK */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_CLK */ +#define PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_RX */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_RX */ +#define PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define _PRS_CONSUMER_EUSART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART0_TRIGGER */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ +#define PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_CLK */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_CLK */ +#define PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_CLK*/ + +/* Bit fields for PRS CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_RX */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_RX */ +#define PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_RX*/ + +/* Bit fields for PRS CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define _PRS_CONSUMER_EUSART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUSART1_TRIGGER */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ +#define PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUSART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUSART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_PAEN */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_PAEN */ +#define PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_PAEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_PAEN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S0IN */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN */ +#define PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S0IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S0IN*/ + +/* Bit fields for PRS CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_PCNT0_S1IN */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN */ +#define PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT (_PRS_CONSUMER_PCNT0_S1IN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_PCNT0_S1IN*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC25 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC25_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC25*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC26 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC26_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC26*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC27 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC27_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC27*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC28 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC28_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC28*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC29 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC29_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC29*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC30 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC30_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC30*/ + +/* Bit fields for PRS CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SETAMPER_TAMPERSRC31 */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ +#define PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT (_PRS_CONSUMER_SETAMPER_TAMPERSRC31_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SETAMPER_TAMPERSRC31*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN0 */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0 */ +#define PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN0*/ + +/* Bit fields for PRS CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_SYSRTC0_IN1 */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1 */ +#define PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT (_PRS_CONSUMER_SYSRTC0_IN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_SYSRTC0_IN1*/ + +/* Bit fields for PRS CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_OSCREQ */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ */ +#define PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_OSCREQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_OSCREQ*/ + +/* Bit fields for PRS CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_HFXO0_TIMEOUT*/ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT */ +#define PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT (_PRS_CONSUMER_HFXO0_TIMEOUT_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_HFXO0_TIMEOUT*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC0_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC0_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC0_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_ASYNCTRIGCH1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_ASYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH0 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH0*/ + +/* Bit fields for PRS CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_MASK 0x00000300UL /**< Mask for PRS_CONSUMER_VDAC1_SYNCTRIGCH1 */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ +#define PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT (_PRS_CONSUMER_VDAC1_SYNCTRIGCH1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_VDAC1_SYNCTRIGCH1*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC0 */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0 */ +#define PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG1_SRC1 */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1 */ +#define PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG1_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG1_SRC1*/ + +/** @} End of group EFR32MG24_PRS_BitFields */ +/** @} End of group EFR32MG24_PRS */ +/** @} End of group Parts */ + +#endif // EFR32MG24_PRS_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h index 6dbf41a..63ce4f3 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_prs_signals.h @@ -1,976 +1,976 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 PRS register signal bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_PRS_SIGNALS_H -#define EFR32MG24_PRS_SIGNALS_H - -/** Synchronous signal sources enumeration: */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000008UL) - -/** Synchronous signal sources enumeration aligned with register bit field: */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) - -/** Synchronous signals enumeration: */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (0x00000001UL) - -/** Synchronous signals enumeration aligned with register bit field: */ -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC << 0) - -/** Synchronous signals and sources combined and aligned with register bit fields: */ -#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) -#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) -#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) -#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) -#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) -#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) -#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) -#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) -#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) -#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) -#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) -#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) -#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) -#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) -#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) -#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) -#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) -#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) -#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) -#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) -#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) -#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) -#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) -#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) -#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) -#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) -#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) -#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) -#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC) -#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC) -#define PRS_SYNC_VDAC1_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC) -#define PRS_SYNC_VDAC1_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC) - -/** Asynchronous signal sources enumeration: */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000cUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000dUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x0000000eUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000000fUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000010UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000011UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x00000012UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000013UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (0x00000014UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000015UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000016UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000017UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x00000018UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000019UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000035UL) - -/** Asynchronous signal sources enumeration aligned with register bit field: */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8) - -/** Asynchronous signals enumeration: */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) - -/** Asynchronous signals enumeration aligned with register bit field: */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) - -/** Asynchronous signals and sources combined and aligned with register bit fields: */ -#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) -#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) -#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) -#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) -#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) -#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) -#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) -#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) -#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) -#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) -#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) -#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) -#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) -#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) -#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) -#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) -#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) -#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) -#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) -#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) -#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) -#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) -#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) -#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) -#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) -#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) -#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) -#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) -#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) -#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) -#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) -#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) -#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) -#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) -#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) -#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) -#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) -#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) -#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) -#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) -#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) -#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) -#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) -#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) -#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) -#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) -#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) -#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) -#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) -#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) -#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) -#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) -#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) -#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) -#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) -#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) -#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) -#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) -#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) -#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) -#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) -#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) -#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) -#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) -#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) -#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) -#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) -#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) -#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) -#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) -#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) -#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) -#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) -#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) -#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) -#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) -#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) -#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) -#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) -#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) -#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) -#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) -#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) -#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) -#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) -#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) -#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) -#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) -#define PRS_ASYNC_MODEMH_SI (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI) -#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) -#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) -#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) -#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) -#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) -#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) -#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) -#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) -#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) -#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) -#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) -#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) -#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) -#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) -#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) -#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) -#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) -#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) -#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) -#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) -#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) -#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) -#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) -#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) -#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) -#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) -#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) -#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) -#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) -#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) -#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) -#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) -#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) -#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) -#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) -#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) -#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) -#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) -#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) -#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) -#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) -#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) -#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) -#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) -#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) -#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) -#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) -#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) -#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT) -#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR) -#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF) -#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0) -#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1) -#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0) -#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1) -#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS) -#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1) -#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) -#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) -#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) -#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) -#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) -#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) -#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) -#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) -#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) -#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) -#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) -#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) -#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) -#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) -#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) -#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) -#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM) -#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM) -#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC) -#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC) -#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF) -#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF) -#define PRS_ASYNC_VDAC1L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM) -#define PRS_ASYNC_VDAC1L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM) -#define PRS_ASYNC_VDAC1L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC) -#define PRS_ASYNC_VDAC1L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC) -#define PRS_ASYNC_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF) -#define PRS_ASYNC_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF) -#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) -#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) -#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) - -/** - * Asynchronous signals and sources combined and aligned with register bit fields - * without the '_ASYNCH_' infix in order for backward compatibility: - */ -#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) -#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) -#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) -#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) -#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) -#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) -#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) -#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) -#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) -#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) -#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) -#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) -#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) -#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) -#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) -#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) -#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) -#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) -#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) -#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) -#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) -#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) -#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) -#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) -#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) -#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) -#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) -#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) -#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) -#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) -#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) -#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) -#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) -#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) -#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) -#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) -#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) -#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) -#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) -#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) -#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) -#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) -#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) -#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) -#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) -#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) -#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) -#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) -#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) -#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) -#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) -#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) -#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) -#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) -#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) -#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) -#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) -#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) -#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) -#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) -#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) -#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) -#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) -#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) -#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) -#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) -#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) -#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) -#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) -#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) -#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) -#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) -#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) -#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) -#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) -#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) -#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) -#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) -#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) -#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) -#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) -#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) -#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) -#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) -#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) -#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) -#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) -#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) -#define PRS_MODEMH_SI (PRS_ASYNC_MODEMH_SI) -#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) -#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) -#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) -#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) -#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) -#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) -#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) -#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) -#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) -#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) -#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) -#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) -#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) -#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) -#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) -#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) -#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) -#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) -#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) -#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) -#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) -#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) -#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) -#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) -#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) -#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) -#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) -#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) -#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) -#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) -#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) -#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) -#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) -#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) -#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) -#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) -#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) -#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) -#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) -#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) -#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) -#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) -#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) -#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) -#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) -#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) -#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) -#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) -#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT) -#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR) -#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF) -#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0) -#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1) -#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0) -#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1) -#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS) -#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1) -#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) -#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) -#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) -#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) -#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) -#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) -#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) -#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) -#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) -#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) -#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) -#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) -#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) -#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) -#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) -#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) -#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM) -#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM) -#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC) -#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC) -#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF) -#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF) -#define PRS_VDAC1L_CH0WARM (PRS_ASYNC_VDAC1L_CH0WARM) -#define PRS_VDAC1L_CH1WARM (PRS_ASYNC_VDAC1L_CH1WARM) -#define PRS_VDAC1L_CH0DONEASYNC (PRS_ASYNC_VDAC1L_CH0DONEASYNC) -#define PRS_VDAC1L_CH1DONEASYNC (PRS_ASYNC_VDAC1L_CH1DONEASYNC) -#define PRS_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_VDAC1L_INTERNALTIMEROF) -#define PRS_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_VDAC1L_REFRESHTIMEROF) -#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) -#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) -#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) - -#endif // EFR32MG24_PRS_SIGNALS_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_PRS_SIGNALS_H +#define EFR32MG24_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000007UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000008UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (0x00000001UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC (_PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_SYNC_VDAC0_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC) +#define PRS_SYNC_VDAC0_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC) +#define PRS_SYNC_VDAC1_CH0_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC) +#define PRS_SYNC_VDAC1_CH1_DONE_SYNC (PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1 | PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (0x00000011UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (0x00000012UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (0x00000013UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (0x00000014UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (0x00000015UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x00000016UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x00000017UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x00000018UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (0x00000019UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000035UL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCOEM23 << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID (_PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 (_PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF (_PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_MODEMH_SI (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSI) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_RAC_AUXADCDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATA) +#define PRS_ASYNC_RAC_AUXADCDATAVALID (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACAUXADCDATAVALID) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_ACMP0_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP0 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP0OUT) +#define PRS_ASYNC_ACMP1_OUT (PRS_ASYNC_CH_CTRL_SOURCESEL_ACMP1 | PRS_ASYNC_CH_CTRL_SIGSEL_ACMP1OUT) +#define PRS_ASYNC_PCNT0_DIR (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0DIR) +#define PRS_ASYNC_PCNT0_UFOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PCNT0 | PRS_ASYNC_CH_CTRL_SIGSEL_PCNT0UFOF) +#define PRS_ASYNC_SYSRTC0_GRP0OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT0) +#define PRS_ASYNC_SYSRTC0_GRP0OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP0OUT1) +#define PRS_ASYNC_SYSRTC0_GRP1OUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT0) +#define PRS_ASYNC_SYSRTC0_GRP1OUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYSRTC0 | PRS_ASYNC_CH_CTRL_SIGSEL_SYSRTC0GRP1OUT1) +#define PRS_ASYNC_HFXO0L_STATUS (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS) +#define PRS_ASYNC_HFXO0L_STATUS1 (PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L | PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1) +#define PRS_ASYNC_EUSART0L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LCS) +#define PRS_ASYNC_EUSART0L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LIRDATX) +#define PRS_ASYNC_EUSART0L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRTS) +#define PRS_ASYNC_EUSART0L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXDATAV) +#define PRS_ASYNC_EUSART0L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTX) +#define PRS_ASYNC_EUSART0L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXC) +#define PRS_ASYNC_EUSART0L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LRXFL) +#define PRS_ASYNC_EUSART0L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART0L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART0LTXFL) +#define PRS_ASYNC_EUSART1L_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LCS) +#define PRS_ASYNC_EUSART1L_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LIRDATX) +#define PRS_ASYNC_EUSART1L_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRTS) +#define PRS_ASYNC_EUSART1L_RXDATAV (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXDATAV) +#define PRS_ASYNC_EUSART1L_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTX) +#define PRS_ASYNC_EUSART1L_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXC) +#define PRS_ASYNC_EUSART1L_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LRXFL) +#define PRS_ASYNC_EUSART1L_TXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUSART1L | PRS_ASYNC_CH_CTRL_SIGSEL_EUSART1LTXFL) +#define PRS_ASYNC_VDAC0L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0WARM) +#define PRS_ASYNC_VDAC0L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1WARM) +#define PRS_ASYNC_VDAC0L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC) +#define PRS_ASYNC_VDAC0L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC) +#define PRS_ASYNC_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LREFRESHTIMEROF) +#define PRS_ASYNC_VDAC1L_CH0WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0WARM) +#define PRS_ASYNC_VDAC1L_CH1WARM (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1WARM) +#define PRS_ASYNC_VDAC1L_CH0DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC) +#define PRS_ASYNC_VDAC1L_CH1DONEASYNC (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC) +#define PRS_ASYNC_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LINTERNALTIMEROF) +#define PRS_ASYNC_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L | PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LREFRESHTIMEROF) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_MODEMH_SI (PRS_ASYNC_MODEMH_SI) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_RAC_AUXADCDATA (PRS_ASYNC_RAC_AUXADCDATA) +#define PRS_RAC_AUXADCDATAVALID (PRS_ASYNC_RAC_AUXADCDATAVALID) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_ACMP0_OUT (PRS_ASYNC_ACMP0_OUT) +#define PRS_ACMP1_OUT (PRS_ASYNC_ACMP1_OUT) +#define PRS_PCNT0_DIR (PRS_ASYNC_PCNT0_DIR) +#define PRS_PCNT0_UFOF (PRS_ASYNC_PCNT0_UFOF) +#define PRS_SYSRTC0_GRP0OUT0 (PRS_ASYNC_SYSRTC0_GRP0OUT0) +#define PRS_SYSRTC0_GRP0OUT1 (PRS_ASYNC_SYSRTC0_GRP0OUT1) +#define PRS_SYSRTC0_GRP1OUT0 (PRS_ASYNC_SYSRTC0_GRP1OUT0) +#define PRS_SYSRTC0_GRP1OUT1 (PRS_ASYNC_SYSRTC0_GRP1OUT1) +#define PRS_HFXO0L_STATUS (PRS_ASYNC_HFXO0L_STATUS) +#define PRS_HFXO0L_STATUS1 (PRS_ASYNC_HFXO0L_STATUS1) +#define PRS_EUSART0L_CS (PRS_ASYNC_EUSART0L_CS) +#define PRS_EUSART0L_IRDATX (PRS_ASYNC_EUSART0L_IRDATX) +#define PRS_EUSART0L_RTS (PRS_ASYNC_EUSART0L_RTS) +#define PRS_EUSART0L_RXDATAV (PRS_ASYNC_EUSART0L_RXDATAV) +#define PRS_EUSART0L_TX (PRS_ASYNC_EUSART0L_TX) +#define PRS_EUSART0L_TXC (PRS_ASYNC_EUSART0L_TXC) +#define PRS_EUSART0L_RXFL (PRS_ASYNC_EUSART0L_RXFL) +#define PRS_EUSART0L_TXFL (PRS_ASYNC_EUSART0L_TXFL) +#define PRS_EUSART1L_CS (PRS_ASYNC_EUSART1L_CS) +#define PRS_EUSART1L_IRDATX (PRS_ASYNC_EUSART1L_IRDATX) +#define PRS_EUSART1L_RTS (PRS_ASYNC_EUSART1L_RTS) +#define PRS_EUSART1L_RXDATAV (PRS_ASYNC_EUSART1L_RXDATAV) +#define PRS_EUSART1L_TX (PRS_ASYNC_EUSART1L_TX) +#define PRS_EUSART1L_TXC (PRS_ASYNC_EUSART1L_TXC) +#define PRS_EUSART1L_RXFL (PRS_ASYNC_EUSART1L_RXFL) +#define PRS_EUSART1L_TXFL (PRS_ASYNC_EUSART1L_TXFL) +#define PRS_VDAC0L_CH0WARM (PRS_ASYNC_VDAC0L_CH0WARM) +#define PRS_VDAC0L_CH1WARM (PRS_ASYNC_VDAC0L_CH1WARM) +#define PRS_VDAC0L_CH0DONEASYNC (PRS_ASYNC_VDAC0L_CH0DONEASYNC) +#define PRS_VDAC0L_CH1DONEASYNC (PRS_ASYNC_VDAC0L_CH1DONEASYNC) +#define PRS_VDAC0L_INTERNALTIMEROF (PRS_ASYNC_VDAC0L_INTERNALTIMEROF) +#define PRS_VDAC0L_REFRESHTIMEROF (PRS_ASYNC_VDAC0L_REFRESHTIMEROF) +#define PRS_VDAC1L_CH0WARM (PRS_ASYNC_VDAC1L_CH0WARM) +#define PRS_VDAC1L_CH1WARM (PRS_ASYNC_VDAC1L_CH1WARM) +#define PRS_VDAC1L_CH0DONEASYNC (PRS_ASYNC_VDAC1L_CH0DONEASYNC) +#define PRS_VDAC1L_CH1DONEASYNC (PRS_ASYNC_VDAC1L_CH1DONEASYNC) +#define PRS_VDAC1L_INTERNALTIMEROF (PRS_ASYNC_VDAC1L_INTERNALTIMEROF) +#define PRS_VDAC1L_REFRESHTIMEROF (PRS_ASYNC_VDAC1L_REFRESHTIMEROF) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif // EFR32MG24_PRS_SIGNALS_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h index abbe22e..de4e2d4 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_scratchpad.h @@ -1,87 +1,87 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 SCRATCHPAD register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_SCRATCHPAD_H -#define EFR32MG24_SCRATCHPAD_H -#define SCRATCHPAD_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_SCRATCHPAD SCRATCHPAD - * @{ - * @brief EFR32MG24 SCRATCHPAD Register Declaration. - *****************************************************************************/ - -/** SCRATCHPAD Register Declaration. */ -typedef struct { - __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ - uint32_t RESERVED0[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ - uint32_t RESERVED1[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ - uint32_t RESERVED2[1022U]; /**< Reserved for future use */ - __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ - __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ -} SCRATCHPAD_TypeDef; -/** @} End of group EFR32MG24_SCRATCHPAD */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SCRATCHPAD - * @{ - * @defgroup EFR32MG24_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SCRATCHPAD SREG0 */ -#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ -#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ -#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ - -/* Bit fields for SCRATCHPAD SREG1 */ -#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ -#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ -#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ -#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ - -/** @} End of group EFR32MG24_SCRATCHPAD_BitFields */ -/** @} End of group EFR32MG24_SCRATCHPAD */ -/** @} End of group Parts */ - -#endif // EFR32MG24_SCRATCHPAD_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 SCRATCHPAD register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SCRATCHPAD_H +#define EFR32MG24_SCRATCHPAD_H +#define SCRATCHPAD_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SCRATCHPAD SCRATCHPAD + * @{ + * @brief EFR32MG24 SCRATCHPAD Register Declaration. + *****************************************************************************/ + +/** SCRATCHPAD Register Declaration. */ +typedef struct { + __IOM uint32_t SREG0; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1; /**< Scratchpad Register 1 */ + uint32_t RESERVED0[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_SET; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_SET; /**< Scratchpad Register 1 */ + uint32_t RESERVED1[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_CLR; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_CLR; /**< Scratchpad Register 1 */ + uint32_t RESERVED2[1022U]; /**< Reserved for future use */ + __IOM uint32_t SREG0_TGL; /**< Scratchpad Register 0 */ + __IOM uint32_t SREG1_TGL; /**< Scratchpad Register 1 */ +} SCRATCHPAD_TypeDef; +/** @} End of group EFR32MG24_SCRATCHPAD */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SCRATCHPAD + * @{ + * @defgroup EFR32MG24_SCRATCHPAD_BitFields SCRATCHPAD Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SCRATCHPAD SREG0 */ +#define _SCRATCHPAD_SREG0_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG0 */ +#define _SCRATCHPAD_SREG0_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG0_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG0 */ +#define SCRATCHPAD_SREG0_SCRATCH_DEFAULT (_SCRATCHPAD_SREG0_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG0 */ + +/* Bit fields for SCRATCHPAD SREG1 */ +#define _SCRATCHPAD_SREG1_RESETVALUE 0x00000000UL /**< Default value for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_MASK 0xFFFFFFFFUL /**< Mask for SCRATCHPAD_SREG1 */ +#define _SCRATCHPAD_SREG1_SCRATCH_SHIFT 0 /**< Shift value for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_MASK 0xFFFFFFFFUL /**< Bit mask for SCRATCHPAD_SCRATCH */ +#define _SCRATCHPAD_SREG1_SCRATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for SCRATCHPAD_SREG1 */ +#define SCRATCHPAD_SREG1_SCRATCH_DEFAULT (_SCRATCHPAD_SREG1_SCRATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for SCRATCHPAD_SREG1 */ + +/** @} End of group EFR32MG24_SCRATCHPAD_BitFields */ +/** @} End of group EFR32MG24_SCRATCHPAD */ +/** @} End of group Parts */ + +#endif // EFR32MG24_SCRATCHPAD_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h index eca814b..a1ff5d5 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_semailbox.h @@ -1,383 +1,383 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 SEMAILBOX register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_SEMAILBOX_H -#define EFR32MG24_SEMAILBOX_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_SEMAILBOX_HOST SEMAILBOX_HOST - * @{ - * @brief EFR32MG24 SEMAILBOX_HOST Register Declaration. - *****************************************************************************/ - -/** SEMAILBOX_HOST Register Declaration. */ -typedef struct { - __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ -} SEMAILBOX_HOST_TypeDef; -/** @} End of group EFR32MG24_SEMAILBOX_HOST */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SEMAILBOX_HOST - * @{ - * @defgroup EFR32MG24_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SEMAILBOX FIFO */ -#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ -#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ - -/* Bit fields for SEMAILBOX TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ -#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ -#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ - -/* Bit fields for SEMAILBOX RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ -#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ -#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ - -/* Bit fields for SEMAILBOX TX_PROT */ -#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ -#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ -#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ - -/* Bit fields for SEMAILBOX RX_PROT */ -#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ -#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ -#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ - -/* Bit fields for SEMAILBOX TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ -#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ - -/* Bit fields for SEMAILBOX RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ -#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ - -/* Bit fields for SEMAILBOX CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ -#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ -#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ -#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ - -/** @} End of group EFR32MG24_SEMAILBOX_HOST_BitFields */ -/** @} End of group EFR32MG24_SEMAILBOX_HOST */ -/**************************************************************************//** - * @defgroup EFR32MG24_SEMAILBOX_APBSE SEMAILBOX_APBSE - * @{ - * @brief EFR32MG24 SEMAILBOX_APBSE Register Declaration. - *****************************************************************************/ - -/** SEMAILBOX_APBSE Register Declaration. */ -typedef struct { - __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ - uint32_t RESERVED0[15U]; /**< Reserved for future use */ - __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ - __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ - __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ - __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ - __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ - __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ -} SEMAILBOX_APBSE_TypeDef; -/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SEMAILBOX_APBSE - * @{ - * @defgroup EFR32MG24_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ - -/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ -#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ -#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ - -/** @} End of group EFR32MG24_SEMAILBOX_APBSE_BitFields */ -/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ -/** @} End of group Parts */ - -#endif // EFR32MG24_SEMAILBOX_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 SEMAILBOX register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SEMAILBOX_H +#define EFR32MG24_SEMAILBOX_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SEMAILBOX_HOST SEMAILBOX_HOST + * @{ + * @brief EFR32MG24 SEMAILBOX_HOST Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_HOST Register Declaration. */ +typedef struct { + __IOM uint32_t FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t TX_STATUS; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t RX_STATUS; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t TX_PROT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t RX_PROT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t TX_HEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t RX_HEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t CONFIGURATION; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_HOST_TypeDef; +/** @} End of group EFR32MG24_SEMAILBOX_HOST */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SEMAILBOX_HOST + * @{ + * @defgroup EFR32MG24_SEMAILBOX_HOST_BitFields SEMAILBOX_HOST Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX FIFO */ +#define _SEMAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_FIFO */ +#define SEMAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_FIFO */ + +/* Bit fields for SEMAILBOX TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_TX_STATUS */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_TX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define _SEMAILBOX_TX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_TX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_TX_STATUS_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXINT_DEFAULT (_SEMAILBOX_TX_STATUS_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_TX_STATUS_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXFULL_DEFAULT (_SEMAILBOX_TX_STATUS_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ +#define SEMAILBOX_TX_STATUS_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_TX_STATUS_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_STATUS */ +#define SEMAILBOX_TX_STATUS_TXERROR_DEFAULT (_SEMAILBOX_TX_STATUS_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_STATUS*/ + +/* Bit fields for SEMAILBOX RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_RX_STATUS */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT (_SEMAILBOX_RX_STATUS_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define _SEMAILBOX_RX_STATUS_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT (_SEMAILBOX_RX_STATUS_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_RX_STATUS_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXINT_DEFAULT (_SEMAILBOX_RX_STATUS_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT (_SEMAILBOX_RX_STATUS_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_RX_STATUS_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXHDR_DEFAULT (_SEMAILBOX_RX_STATUS_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ +#define SEMAILBOX_RX_STATUS_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_RX_STATUS_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_STATUS */ +#define SEMAILBOX_RX_STATUS_RXERROR_DEFAULT (_SEMAILBOX_RX_STATUS_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_STATUS*/ + +/* Bit fields for SEMAILBOX TX_PROT */ +#define _SEMAILBOX_TX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_TX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_TX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_TX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_TX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ +#define _SEMAILBOX_TX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_TX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_PROT */ +#define SEMAILBOX_TX_PROT_USER_DEFAULT (_SEMAILBOX_TX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_TX_PROT */ + +/* Bit fields for SEMAILBOX RX_PROT */ +#define _SEMAILBOX_RX_PROT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT (_SEMAILBOX_RX_PROT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT (_SEMAILBOX_RX_PROT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_RX_PROT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_NONSECURE_DEFAULT (_SEMAILBOX_RX_PROT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ +#define _SEMAILBOX_RX_PROT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_RX_PROT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_PROT */ +#define SEMAILBOX_RX_PROT_USER_DEFAULT (_SEMAILBOX_RX_PROT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_RX_PROT */ + +/* Bit fields for SEMAILBOX TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_TX_HEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_TX_HEADER */ +#define SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT (_SEMAILBOX_TX_HEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_TX_HEADER*/ + +/* Bit fields for SEMAILBOX RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_RX_HEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_RX_HEADER */ +#define SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT (_SEMAILBOX_RX_HEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_RX_HEADER*/ + +/* Bit fields for SEMAILBOX CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_CONFIGURATION */ +#define _SEMAILBOX_CONFIGURATION_MASK 0x00000003UL /**< Mask for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ +#define SEMAILBOX_CONFIGURATION_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_CONFIGURATION */ +#define SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT (_SEMAILBOX_CONFIGURATION_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_CONFIGURATION*/ + +/** @} End of group EFR32MG24_SEMAILBOX_HOST_BitFields */ +/** @} End of group EFR32MG24_SEMAILBOX_HOST */ +/**************************************************************************//** + * @defgroup EFR32MG24_SEMAILBOX_APBSE SEMAILBOX_APBSE + * @{ + * @brief EFR32MG24 SEMAILBOX_APBSE Register Declaration. + *****************************************************************************/ + +/** SEMAILBOX_APBSE Register Declaration. */ +typedef struct { + __IOM uint32_t SE_ESECURE_MAILBOX_FIFO; /**< ESECURE_MAILBOX_FIFO */ + uint32_t RESERVED0[15U]; /**< Reserved for future use */ + __IM uint32_t SE_ESECURE_MAILBOX_TXSTAT; /**< ESECURE_MAILBOX_TXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXSTAT; /**< ESECURE_MAILBOX_RXSTAT */ + __IM uint32_t SE_ESECURE_MAILBOX_TXPROTECT; /**< ESECURE_MAILBOX_TXPROTECT */ + __IM uint32_t SE_ESECURE_MAILBOX_RXPROTECT; /**< ESECURE_MAILBOX_RXPROTECT */ + __IOM uint32_t SE_ESECURE_MAILBOX_TXHEADER; /**< ESECURE_MAILBOX_TXHEADER */ + __IM uint32_t SE_ESECURE_MAILBOX_RXHEADER; /**< ESECURE_MAILBOX_RXHEADER */ + __IOM uint32_t SE_ESECURE_MAILBOX_CONFIG; /**< ESECURE_MAILBOX_CONFIG */ +} SEMAILBOX_APBSE_TypeDef; +/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SEMAILBOX_APBSE + * @{ + * @defgroup EFR32MG24_SEMAILBOX_APBSE_BitFields SEMAILBOX_APBSE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_SHIFT 0 /**< Shift value for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_FIFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_FIFO_FIFO_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_FIFO*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MASK 0x00BFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT (0x1UL << 20) /**< TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_SHIFT 20 /**< Shift value for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_TXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL (0x1UL << 21) /**< TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_SHIFT 21 /**< Shift value for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_MASK 0x200000UL /**< Bit mask for SEMAILBOX_TXFULL */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXFULL_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR (0x1UL << 23) /**< TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_TXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT_TXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXSTAT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MASK 0x00FFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_SHIFT 0 /**< Shift value for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_MASK 0xFFFFUL /**< Bit mask for SEMAILBOX_REMBYTES */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_REMBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_SHIFT 16 /**< Shift value for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_MASK 0xF0000UL /**< Bit mask for SEMAILBOX_MSGINFO */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_MSGINFO_DEFAULT << 16) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT (0x1UL << 20) /**< RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_SHIFT 20 /**< Shift value for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_MASK 0x100000UL /**< Bit mask for SEMAILBOX_RXINT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXINT_DEFAULT << 20) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY (0x1UL << 21) /**< RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_SHIFT 21 /**< Shift value for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_MASK 0x200000UL /**< Bit mask for SEMAILBOX_RXEMPTY */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXEMPTY_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR (0x1UL << 22) /**< RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_SHIFT 22 /**< Shift value for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_MASK 0x400000UL /**< Bit mask for SEMAILBOX_RXHDR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXHDR_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR (0x1UL << 23) /**< RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_SHIFT 23 /**< Shift value for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_MASK 0x800000UL /**< Bit mask for SEMAILBOX_RXERROR */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT_RXERROR_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXSTAT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXPROTECT */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_MASK 0xFFE00000UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED (0x1UL << 21) /**< UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_SHIFT 21 /**< Shift value for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_MASK 0x200000UL /**< Bit mask for SEMAILBOX_UNPROTECTED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_UNPROTECTED_DEFAULT << 21) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED (0x1UL << 22) /**< PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_SHIFT 22 /**< Shift value for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_MASK 0x400000UL /**< Bit mask for SEMAILBOX_PRIVILEGED */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_PRIVILEGED_DEFAULT << 22) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE (0x1UL << 23) /**< NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_SHIFT 23 /**< Shift value for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_MASK 0x800000UL /**< Bit mask for SEMAILBOX_NONSECURE */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_NONSECURE_DEFAULT << 23) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_SHIFT 24 /**< Shift value for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_MASK 0xFF000000UL /**< Bit mask for SEMAILBOX_USER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT_USER_DEFAULT << 24) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXPROTECT*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_TXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER_TXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_TXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_MASK 0xFFFFFFFFUL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_SHIFT 0 /**< Shift value for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_MASK 0xFFFFFFFFUL /**< Bit mask for SEMAILBOX_RXHEADER */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER_RXHEADER_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_RXHEADER*/ + +/* Bit fields for SEMAILBOX SE_ESECURE_MAILBOX_CONFIG */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RESETVALUE 0x00000000UL /**< Default value for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_MASK 0x00000003UL /**< Mask for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN (0x1UL << 0) /**< TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_SHIFT 0 /**< Shift value for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_MASK 0x1UL /**< Bit mask for SEMAILBOX_TXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_TXINTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN (0x1UL << 1) /**< RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_SHIFT 1 /**< Shift value for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_MASK 0x2UL /**< Bit mask for SEMAILBOX_RXINTEN */ +#define _SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ +#define SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT (_SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG_RXINTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SEMAILBOX_SE_ESECURE_MAILBOX_CONFIG*/ + +/** @} End of group EFR32MG24_SEMAILBOX_APBSE_BitFields */ +/** @} End of group EFR32MG24_SEMAILBOX_APBSE */ +/** @} End of group Parts */ + +#endif // EFR32MG24_SEMAILBOX_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h index 09c83b6..78e5cf0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_smu.h @@ -1,1483 +1,1483 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 SMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_SMU_H -#define EFR32MG24_SMU_H -#define SMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_SMU SMU - * @{ - * @brief EFR32MG24 SMU Register Declaration. - *****************************************************************************/ - -/** SMU Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL; /**< M33 Control Settings */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0; /**< Privileged Access */ - __IOM uint32_t PPUPATD1; /**< Privileged Access */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0; /**< Secure Access */ - __IOM uint32_t PPUSATD1; /**< Secure Access */ - uint32_t RESERVED3[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ - uint32_t RESERVED6[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS; /**< Fault Status */ - __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ - uint32_t RESERVED9[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ - uint32_t RESERVED10[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED13[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ - __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ - uint32_t RESERVED14[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_SET; /**< Fault Status */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED16[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ - uint32_t RESERVED17[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_SET; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ - uint32_t RESERVED18[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ - uint32_t RESERVED21[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ - uint32_t RESERVED23[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED24[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ - __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ - uint32_t RESERVED25[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_CLR; /**< Fault Status */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED27[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ - uint32_t RESERVED28[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_CLR; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ - uint32_t RESERVED32[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED35[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ - __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ - uint32_t RESERVED36[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_TGL; /**< Fault Status */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ - uint32_t RESERVED39[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_TGL; /**< Fault Status */ - __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ - uint32_t RESERVED40[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ - __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ - uint32_t RESERVED41[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ - uint32_t RESERVED42[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ - __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ -} SMU_TypeDef; -/** @} End of group EFR32MG24_SMU */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SMU - * @{ - * @defgroup EFR32MG24_SMU_BitFields SMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SMU IPVERSION */ -#define _SMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SMU_IPVERSION */ -#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SMU_IPVERSION */ -#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ - -/* Bit fields for SMU STATUS */ -#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ -#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ -#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ -#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ -#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ - -/* Bit fields for SMU LOCK */ -#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ -#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ - -/* Bit fields for SMU IF */ -#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ -#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ -#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ -#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ -#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ -#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ -#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ - -/* Bit fields for SMU IEN */ -#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ -#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ -#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ -#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ -#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ -#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ -#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ - -/* Bit fields for SMU M33CTRL */ -#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ -#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ -#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ -#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ - -/* Bit fields for SMU PPUPATD0 */ -#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ -#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ -#define _SMU_PPUPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUPATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSRTC_DEFAULT (_SMU_PPUPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ - -/* Bit fields for SMU PPUPATD1 */ -#define _SMU_PPUPATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUPATD1 */ -#define _SMU_PPUPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ -#define _SMU_PPUPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ -#define _SMU_PPUPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ -#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ -#define _SMU_PPUPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ -#define _SMU_PPUPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ -#define _SMU_PPUPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ -#define _SMU_PPUPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ -#define _SMU_PPUPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ -#define _SMU_PPUPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ -#define _SMU_PPUPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_VDAC1_DEFAULT (_SMU_PPUPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ -#define _SMU_PPUPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ -#define _SMU_PPUPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ -#define _SMU_PPUPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ -#define _SMU_PPUPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ -#define _SMU_PPUPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ -#define _SMU_PPUPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ -#define _SMU_PPUPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ -#define _SMU_PPUPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ -#define _SMU_PPUPATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_MVP_DEFAULT (_SMU_PPUPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ - -/* Bit fields for SMU PPUSATD0 */ -#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ -#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ -#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ -#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ -#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ -#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ -#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ -#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ -#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ -#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ -#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ -#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ -#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ -#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ -#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ -#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ -#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ -#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ -#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ -#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ -#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ -#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ -#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ -#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ -#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ -#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ -#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ -#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ -#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ -#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Secure Access */ -#define _SMU_PPUSATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUSATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUSATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSRTC_DEFAULT (_SMU_PPUSATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ - -/* Bit fields for SMU PPUSATD1 */ -#define _SMU_PPUSATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUSATD1 */ -#define _SMU_PPUSATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Secure Access */ -#define _SMU_PPUSATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM (0x1UL << 1) /**< DMEM Secure Access */ -#define _SMU_PPUSATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Secure Access */ -#define _SMU_PPUSATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU (0x1UL << 3) /**< SMU Secure Access */ -#define _SMU_PPUSATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Secure Access */ -#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Secure Access */ -#define _SMU_PPUSATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0 (0x1UL << 6) /**< IADC0 Secure Access */ -#define _SMU_PPUSATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Secure Access */ -#define _SMU_PPUSATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Secure Access */ -#define _SMU_PPUSATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Secure Access */ -#define _SMU_PPUSATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Secure Access */ -#define _SMU_PPUSATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Secure Access */ -#define _SMU_PPUSATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ -#define _SMU_PPUSATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ -#define _SMU_PPUSATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_VDAC1_DEFAULT (_SMU_PPUSATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT (0x1UL << 12) /**< PCNT Secure Access */ -#define _SMU_PPUSATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Secure Access */ -#define _SMU_PPUSATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Secure Access */ -#define _SMU_PPUSATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0 (0x1UL << 15) /**< I2C0 Secure Access */ -#define _SMU_PPUSATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Secure Access */ -#define _SMU_PPUSATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Secure Access */ -#define _SMU_PPUSATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Secure Access */ -#define _SMU_PPUSATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Secure Access */ -#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_MVP (0x1UL << 20) /**< MVP Secure Access */ -#define _SMU_PPUSATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ -#define _SMU_PPUSATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ -#define _SMU_PPUSATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_MVP_DEFAULT (_SMU_PPUSATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Secure Access */ -#define _SMU_PPUSATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ - -/* Bit fields for SMU PPUFS */ -#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ -#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ -#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ -#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ - -/* Bit fields for SMU BMPUPATD0 */ -#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ -#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ -#define _SMU_BMPUPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ -#define _SMU_BMPUPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ -#define _SMU_BMPUPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ -#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ -#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ - -/* Bit fields for SMU BMPUSATD0 */ -#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ -#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ -#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ -#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 secure mode */ -#define _SMU_BMPUSATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUSATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 secure mode */ -#define _SMU_BMPUSATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUSATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 secure mode */ -#define _SMU_BMPUSATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUSATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ -#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */ -#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */ -#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ - -/* Bit fields for SMU BMPUFS */ -#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ -#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ -#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ -#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ - -/* Bit fields for SMU BMPUFSADDR */ -#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ -#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ - -/* Bit fields for SMU ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ -#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ - -/* Bit fields for SMU ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ -#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ - -/* Bit fields for SMU ESAUMRB01 */ -#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ -#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ - -/* Bit fields for SMU ESAUMRB12 */ -#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ -#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ - -/* Bit fields for SMU ESAUMRB45 */ -#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ -#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ - -/* Bit fields for SMU ESAUMRB56 */ -#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ -#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ - -/** @} End of group EFR32MG24_SMU_BitFields */ -/** @} End of group EFR32MG24_SMU */ -/**************************************************************************//** - * @defgroup EFR32MG24_SMU_CFGNS SMU_CFGNS - * @{ - * @brief EFR32MG24 SMU_CFGNS Register Declaration. - *****************************************************************************/ - -/** SMU_CFGNS Register Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS; /**< Status Register */ - __IOM uint32_t NSLOCK; /**< Lock Register */ - __IOM uint32_t NSIF; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ - uint32_t RESERVED3[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS; /**< Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ - uint32_t RESERVED5[63U]; /**< Reserved for future use */ - uint32_t RESERVED6[876U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_SET; /**< Status Register */ - __IOM uint32_t NSLOCK_SET; /**< Lock Register */ - __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ - uint32_t RESERVED10[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_SET; /**< Fault Status */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[876U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_CLR; /**< Status Register */ - __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ - __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - uint32_t RESERVED16[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ - uint32_t RESERVED17[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ - uint32_t RESERVED19[63U]; /**< Reserved for future use */ - uint32_t RESERVED20[876U]; /**< Reserved for future use */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_TGL; /**< Status Register */ - __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ - __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - uint32_t RESERVED23[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ - __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ - uint32_t RESERVED24[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ - uint32_t RESERVED26[63U]; /**< Reserved for future use */ -} SMU_CFGNS_TypeDef; -/** @} End of group EFR32MG24_SMU_CFGNS */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SMU_CFGNS - * @{ - * @defgroup EFR32MG24_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SMU NSSTATUS */ -#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ -#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ - -/* Bit fields for SMU NSLOCK */ -#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ -#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ - -/* Bit fields for SMU NSIF */ -#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ -#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ -#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ -#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ - -/* Bit fields for SMU NSIEN */ -#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ -#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ -#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ -#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ - -/* Bit fields for SMU PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ -#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ -#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ -#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ -#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ -#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ -#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ -#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ -#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ -#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ -#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ -#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ -#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ -#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ -#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ -#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ -#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ -#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ -#define _SMU_PPUNSPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ -#define _SMU_PPUNSPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ -#define _SMU_PPUNSPATD0_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSRTC_DEFAULT (_SMU_PPUNSPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ - -/* Bit fields for SMU PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ -#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ -#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ -#define _SMU_PPUNSPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ -#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ -#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ -#define _SMU_PPUNSPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ -#define _SMU_PPUNSPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ -#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ -#define _SMU_PPUNSPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ -#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ -#define _SMU_PPUNSPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ -#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ -#define _SMU_PPUNSPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ -#define _SMU_PPUNSPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ -#define _SMU_PPUNSPATD1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_VDAC1_DEFAULT (_SMU_PPUNSPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ -#define _SMU_PPUNSPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ -#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ -#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ -#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ -#define _SMU_PPUNSPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ -#define _SMU_PPUNSPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ -#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ -#define _SMU_PPUNSPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ -#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ -#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ -#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ -#define _SMU_PPUNSPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ -#define _SMU_PPUNSPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ -#define _SMU_PPUNSPATD1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_MVP_DEFAULT (_SMU_PPUNSPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ - -/* Bit fields for SMU PPUNSFS */ -#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ -#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ - -/* Bit fields for SMU BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ -#define _SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ -#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ -#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ -#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ -#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ - -/** @} End of group EFR32MG24_SMU_CFGNS_BitFields */ -/** @} End of group EFR32MG24_SMU_CFGNS */ -/** @} End of group Parts */ - -#endif // EFR32MG24_SMU_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SMU_H +#define EFR32MG24_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SMU SMU + * @{ + * @brief EFR32MG24 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control Settings */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< Privileged Access */ + __IOM uint32_t PPUPATD1; /**< Privileged Access */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< Secure Access */ + __IOM uint32_t PPUSATD1; /**< Secure Access */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< Secure Attribute */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< Fault Status */ + __IM uint32_t BMPUFSADDR; /**< Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1; /**< Region Types 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12; /**< Movable Region Boundary */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56; /**< Movable Region Boundary */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control Settings */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< Secure Access */ + __IOM uint32_t PPUSATD1_SET; /**< Secure Access */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< Secure Attribute */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< Region Types 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_SET; /**< Movable Region Boundary */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_SET; /**< Movable Region Boundary */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control Settings */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< Secure Access */ + __IOM uint32_t PPUSATD1_CLR; /**< Secure Access */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< Secure Attribute */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< Region Types 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_CLR; /**< Movable Region Boundary */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control Settings */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< Secure Access */ + __IOM uint32_t PPUSATD1_TGL; /**< Secure Access */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< Secure Attribute */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< Region Types 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< Region Types 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB12_TGL; /**< Movable Region Boundary */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< Movable Region Boundary */ + __IOM uint32_t ESAUMRB56_TGL; /**< Movable Region Boundary */ +} SMU_TypeDef; +/** @} End of group EFR32MG24_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SMU + * @{ + * @defgroup EFR32MG24_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< New BitField */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< New BitField */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCDC_DEFAULT (_SMU_PPUPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUPATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUPATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EUSART1_DEFAULT (_SMU_PPUPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ +#define _SMU_PPUPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUPATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSRTC_DEFAULT (_SMU_PPUPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUPATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_KEYSCAN_DEFAULT (_SMU_PPUPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ +#define _SMU_PPUPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUPATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DMEM_DEFAULT (_SMU_PPUPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ +#define _SMU_PPUPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUPATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP0_DEFAULT (_SMU_PPUPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ +#define _SMU_PPUPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUPATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_ACMP1_DEFAULT (_SMU_PPUPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ +#define _SMU_PPUPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUPATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC0_DEFAULT (_SMU_PPUPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ +#define _SMU_PPUPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUPATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_VDAC1_DEFAULT (_SMU_PPUPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ +#define _SMU_PPUPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUPATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PCNT_DEFAULT (_SMU_PPUPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUPATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFRCO1_DEFAULT (_SMU_PPUPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_HFXO0_DEFAULT (_SMU_PPUPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ +#define _SMU_PPUPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUPATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG1_DEFAULT (_SMU_PPUPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ +#define _SMU_PPUPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUPATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUSART0_DEFAULT (_SMU_PPUPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUPATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SEMAILBOX_DEFAULT (_SMU_PPUPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ +#define _SMU_PPUPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUPATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_MVP_DEFAULT (_SMU_PPUPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 4) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 6) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 7) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 9) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 11) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 12) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 13) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 20) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 21) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 22) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 26) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 27) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC (0x1UL << 28) /**< DCDC Secure Access */ +#define _SMU_PPUSATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD0_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCDC_DEFAULT (_SMU_PPUSATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Secure Access */ +#define _SMU_PPUSATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUSATD0_HOSTMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUSATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Secure Access */ +#define _SMU_PPUSATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUSATD0_EUSART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EUSART1_DEFAULT (_SMU_PPUSATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Secure Access */ +#define _SMU_PPUSATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUSATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUSATD0_SYSRTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSRTC_DEFAULT (_SMU_PPUSATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x003FFFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Secure Access */ +#define _SMU_PPUSATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUSATD1_KEYSCAN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_KEYSCAN_DEFAULT (_SMU_PPUSATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM (0x1UL << 1) /**< DMEM Secure Access */ +#define _SMU_PPUSATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUSATD1_DMEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DMEM_DEFAULT (_SMU_PPUSATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 3) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 6) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Secure Access */ +#define _SMU_PPUSATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUSATD1_ACMP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP0_DEFAULT (_SMU_PPUSATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Secure Access */ +#define _SMU_PPUSATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUSATD1_ACMP1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_ACMP1_DEFAULT (_SMU_PPUSATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Secure Access */ +#define _SMU_PPUSATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUSATD1_VDAC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC0_DEFAULT (_SMU_PPUSATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Secure Access */ +#define _SMU_PPUSATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUSATD1_VDAC1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_VDAC1_DEFAULT (_SMU_PPUSATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT (0x1UL << 12) /**< PCNT Secure Access */ +#define _SMU_PPUSATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUSATD1_PCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PCNT_DEFAULT (_SMU_PPUSATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Secure Access */ +#define _SMU_PPUSATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUSATD1_HFRCO1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFRCO1_DEFAULT (_SMU_PPUSATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD1_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_HFXO0_DEFAULT (_SMU_PPUSATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 15) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Secure Access */ +#define _SMU_PPUSATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUSATD1_WDOG1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG1_DEFAULT (_SMU_PPUSATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Secure Access */ +#define _SMU_PPUSATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUSATD1_EUSART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUSART0_DEFAULT (_SMU_PPUSATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Secure Access */ +#define _SMU_PPUSATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUSATD1_SEMAILBOX_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SEMAILBOX_DEFAULT (_SMU_PPUSATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP (0x1UL << 20) /**< MVP Secure Access */ +#define _SMU_PPUSATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUSATD1_MVP_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_MVP_DEFAULT (_SMU_PPUSATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA0_DEFAULT (_SMU_BMPUPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RFECA1_DEFAULT (_SMU_BMPUPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000003FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 2) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 secure mode */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUSATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0 (0x1UL << 6) /**< RFECA0 secure mode */ +#define _SMU_BMPUSATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUSATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA0_DEFAULT (_SMU_BMPUSATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1 (0x1UL << 7) /**< RFECA1 secure mode */ +#define _SMU_BMPUSATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUSATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RFECA1_DEFAULT (_SMU_BMPUSATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA secure mode */ +#define _SMU_BMPUSATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUSATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_SEEXTDMA_DEFAULT (_SMU_BMPUSATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x0A000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x0000A000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x0C000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x0000C000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32MG24_SMU_BitFields */ +/** @} End of group EFR32MG24_SMU */ +/**************************************************************************//** + * @defgroup EFR32MG24_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32MG24 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Status Register */ + __IOM uint32_t NSLOCK; /**< Lock Register */ + __IOM uint32_t NSIF; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1; /**< Privileged Access */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< Privileged Attribute */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Status Register */ + __IOM uint32_t NSLOCK_SET; /**< Lock Register */ + __IOM uint32_t NSIF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_SET; /**< Privileged Access */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< Privileged Attribute */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Status Register */ + __IOM uint32_t NSLOCK_CLR; /**< Lock Register */ + __IOM uint32_t NSIF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_CLR; /**< Privileged Access */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< Privileged Attribute */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Status Register */ + __IOM uint32_t NSLOCK_TGL; /**< Lock Register */ + __IOM uint32_t NSIF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t NSIEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< Privileged Access */ + __IOM uint32_t PPUNSPATD1_TGL; /**< Privileged Access */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< Privileged Attribute */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32MG24_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SMU_CFGNS + * @{ + * @defgroup EFR32MG24_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD (0x1UL << 0) /**< SCRATCHPAD Privileged Access */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_SHIFT 0 /**< Shift value for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_MASK 0x1UL /**< Bit mask for SMU_SCRATCHPAD */ +#define _SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT (_SMU_PPUNSPATD0_SCRATCHPAD_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 3) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 3 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x8UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 4) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 4 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x10UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 5) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 5 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x20UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 6) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 6 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x40UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 7) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 7 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x80UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 8) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 8 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x100UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 9) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 9 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x200UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 10) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 10 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x400UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 11) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 11 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x800UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 12) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 12 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x1000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 13) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 13 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x2000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 14) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 14 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x4000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 15) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 15 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x8000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 16) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 16 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x10000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 17) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 17 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x20000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 18) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 18 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x40000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 19) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 19 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x80000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 20) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 20 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x100000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 21) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 21 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x200000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 22) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 22 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x400000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 23) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 23 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x800000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 24) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 24 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x1000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 25) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 25 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x2000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 26) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 26 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x4000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 27) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 27 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x8000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC (0x1UL << 28) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD0_DCDC_SHIFT 28 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_MASK 0x10000000UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCDC_DEFAULT (_SMU_PPUNSPATD0_DCDC_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX (0x1UL << 29) /**< HOSTMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_SHIFT 29 /**< Shift value for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_MASK 0x20000000UL /**< Bit mask for SMU_HOSTMAILBOX */ +#define _SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT (_SMU_PPUNSPATD0_HOSTMAILBOX_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1 (0x1UL << 30) /**< EUSART1 Privileged Access */ +#define _SMU_PPUNSPATD0_EUSART1_SHIFT 30 /**< Shift value for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_MASK 0x40000000UL /**< Bit mask for SMU_EUSART1 */ +#define _SMU_PPUNSPATD0_EUSART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EUSART1_DEFAULT (_SMU_PPUNSPATD0_EUSART1_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSRTC (0x1UL << 31) /**< SYSRTC Privileged Access */ +#define _SMU_PPUNSPATD0_SYSRTC_SHIFT 31 /**< Shift value for SMU_SYSRTC */ +#define _SMU_PPUNSPATD0_SYSRTC_MASK 0x80000000UL /**< Bit mask for SMU_SYSRTC */ +#define _SMU_PPUNSPATD0_SYSRTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSRTC_DEFAULT (_SMU_PPUNSPATD0_SYSRTC_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x003FFFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN (0x1UL << 0) /**< KEYSCAN Privileged Access */ +#define _SMU_PPUNSPATD1_KEYSCAN_SHIFT 0 /**< Shift value for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_MASK 0x1UL /**< Bit mask for SMU_KEYSCAN */ +#define _SMU_PPUNSPATD1_KEYSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_KEYSCAN_DEFAULT (_SMU_PPUNSPATD1_KEYSCAN_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM (0x1UL << 1) /**< DMEM Privileged Access */ +#define _SMU_PPUNSPATD1_DMEM_SHIFT 1 /**< Shift value for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_MASK 0x2UL /**< Bit mask for SMU_DMEM */ +#define _SMU_PPUNSPATD1_DMEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DMEM_DEFAULT (_SMU_PPUNSPATD1_DMEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 2) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 2 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x4UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 3) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 3 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x8UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 4) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 4 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x10UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 5) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 5 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x20UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 6) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 6 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x40UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0 (0x1UL << 7) /**< ACMP0 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP0_SHIFT 7 /**< Shift value for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_MASK 0x80UL /**< Bit mask for SMU_ACMP0 */ +#define _SMU_PPUNSPATD1_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP0_DEFAULT (_SMU_PPUNSPATD1_ACMP0_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1 (0x1UL << 8) /**< ACMP1 Privileged Access */ +#define _SMU_PPUNSPATD1_ACMP1_SHIFT 8 /**< Shift value for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_MASK 0x100UL /**< Bit mask for SMU_ACMP1 */ +#define _SMU_PPUNSPATD1_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_ACMP1_DEFAULT (_SMU_PPUNSPATD1_ACMP1_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 9) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 9 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x200UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0 (0x1UL << 10) /**< VDAC0 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC0_SHIFT 10 /**< Shift value for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_MASK 0x400UL /**< Bit mask for SMU_VDAC0 */ +#define _SMU_PPUNSPATD1_VDAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC0_DEFAULT (_SMU_PPUNSPATD1_VDAC0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1 (0x1UL << 11) /**< VDAC1 Privileged Access */ +#define _SMU_PPUNSPATD1_VDAC1_SHIFT 11 /**< Shift value for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_MASK 0x800UL /**< Bit mask for SMU_VDAC1 */ +#define _SMU_PPUNSPATD1_VDAC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_VDAC1_DEFAULT (_SMU_PPUNSPATD1_VDAC1_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT (0x1UL << 12) /**< PCNT Privileged Access */ +#define _SMU_PPUNSPATD1_PCNT_SHIFT 12 /**< Shift value for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_MASK 0x1000UL /**< Bit mask for SMU_PCNT */ +#define _SMU_PPUNSPATD1_PCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PCNT_DEFAULT (_SMU_PPUNSPATD1_PCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1 (0x1UL << 13) /**< HFRCO1 Privileged Access */ +#define _SMU_PPUNSPATD1_HFRCO1_SHIFT 13 /**< Shift value for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_MASK 0x2000UL /**< Bit mask for SMU_HFRCO1 */ +#define _SMU_PPUNSPATD1_HFRCO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFRCO1_DEFAULT (_SMU_PPUNSPATD1_HFRCO1_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0 (0x1UL << 14) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD1_HFXO0_SHIFT 14 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_MASK 0x4000UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD1_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_HFXO0_DEFAULT (_SMU_PPUNSPATD1_HFXO0_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 15) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 15 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x8000UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 16) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 16 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x10000UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1 (0x1UL << 17) /**< WDOG1 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG1_SHIFT 17 /**< Shift value for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_MASK 0x20000UL /**< Bit mask for SMU_WDOG1 */ +#define _SMU_PPUNSPATD1_WDOG1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG1_DEFAULT (_SMU_PPUNSPATD1_WDOG1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0 (0x1UL << 18) /**< EUSART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUSART0_SHIFT 18 /**< Shift value for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_MASK 0x40000UL /**< Bit mask for SMU_EUSART0 */ +#define _SMU_PPUNSPATD1_EUSART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUSART0_DEFAULT (_SMU_PPUNSPATD1_EUSART0_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX (0x1UL << 19) /**< SEMAILBOX Privileged Access */ +#define _SMU_PPUNSPATD1_SEMAILBOX_SHIFT 19 /**< Shift value for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_MASK 0x80000UL /**< Bit mask for SMU_SEMAILBOX */ +#define _SMU_PPUNSPATD1_SEMAILBOX_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SEMAILBOX_DEFAULT (_SMU_PPUNSPATD1_SEMAILBOX_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_MVP (0x1UL << 20) /**< MVP Privileged Access */ +#define _SMU_PPUNSPATD1_MVP_SHIFT 20 /**< Shift value for SMU_MVP */ +#define _SMU_PPUNSPATD1_MVP_MASK 0x100000UL /**< Bit mask for SMU_MVP */ +#define _SMU_PPUNSPATD1_MVP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_MVP_DEFAULT (_SMU_PPUNSPATD1_MVP_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 21) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 21 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x200000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x000001FFUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 1) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 1 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x2UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 2) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 2 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x4UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA0 (0x1UL << 3) /**< MVPAHBDATA0 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_SHIFT 3 /**< Shift value for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_MASK 0x8UL /**< Bit mask for SMU_MVPAHBDATA0 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA1 (0x1UL << 4) /**< MVPAHBDATA1 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_SHIFT 4 /**< Shift value for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_MASK 0x10UL /**< Bit mask for SMU_MVPAHBDATA1 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA1_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA2 (0x1UL << 5) /**< MVPAHBDATA2 privileged mode */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_SHIFT 5 /**< Shift value for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_MASK 0x20UL /**< Bit mask for SMU_MVPAHBDATA2 */ +#define _SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT (_SMU_BMPUNSPATD0_MVPAHBDATA2_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0 (0x1UL << 6) /**< RFECA0 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA0_SHIFT 6 /**< Shift value for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_MASK 0x40UL /**< Bit mask for SMU_RFECA0 */ +#define _SMU_BMPUNSPATD0_RFECA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA0_DEFAULT (_SMU_BMPUNSPATD0_RFECA0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1 (0x1UL << 7) /**< RFECA1 privileged mode */ +#define _SMU_BMPUNSPATD0_RFECA1_SHIFT 7 /**< Shift value for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_MASK 0x80UL /**< Bit mask for SMU_RFECA1 */ +#define _SMU_BMPUNSPATD0_RFECA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RFECA1_DEFAULT (_SMU_BMPUNSPATD0_RFECA1_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA (0x1UL << 8) /**< SEEXTDMA privileged mode */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_SHIFT 8 /**< Shift value for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_MASK 0x100UL /**< Bit mask for SMU_SEEXTDMA */ +#define _SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT (_SMU_BMPUNSPATD0_SEEXTDMA_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32MG24_SMU_CFGNS_BitFields */ +/** @} End of group EFR32MG24_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32MG24_SMU_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h index 9cdc793..346f84c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_syscfg.h @@ -1,776 +1,776 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 SYSCFG register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_SYSCFG_H -#define EFR32MG24_SYSCFG_H -#define SYSCFG_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_SYSCFG SYSCFG - * @{ - * @brief EFR32MG24 SYSCFG Register Declaration. - *****************************************************************************/ - -/** SYSCFG Register Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ - uint32_t RESERVED3[54U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Control */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ - uint32_t RESERVED7[64U]; /**< Reserved for future use */ - __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ - uint32_t RESERVED8[60U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ - __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ - __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ - uint32_t RESERVED11[120U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ - __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ - __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[635U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ - uint32_t RESERVED17[54U]; /**< Reserved for future use */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Control */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ - uint32_t RESERVED21[64U]; /**< Reserved for future use */ - __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ - uint32_t RESERVED22[60U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ - __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ - __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ - uint32_t RESERVED25[120U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ - __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ - __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - uint32_t RESERVED27[635U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ - uint32_t RESERVED31[54U]; /**< Reserved for future use */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - uint32_t RESERVED33[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Control */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ - uint32_t RESERVED35[64U]; /**< Reserved for future use */ - __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ - uint32_t RESERVED36[60U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control */ - uint32_t RESERVED37[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ - __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ - __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ - uint32_t RESERVED39[120U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ - __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ - __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - uint32_t RESERVED41[635U]; /**< Reserved for future use */ - uint32_t RESERVED42[1U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED43[1U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ - uint32_t RESERVED44[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ - uint32_t RESERVED45[54U]; /**< Reserved for future use */ - uint32_t RESERVED46[1U]; /**< Reserved for future use */ - uint32_t RESERVED47[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Control */ - uint32_t RESERVED48[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ - uint32_t RESERVED49[64U]; /**< Reserved for future use */ - __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ - uint32_t RESERVED50[60U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control */ - uint32_t RESERVED51[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED52[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ - __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ - __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ - uint32_t RESERVED53[120U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ - __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ - __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ - uint32_t RESERVED54[1U]; /**< Reserved for future use */ -} SYSCFG_TypeDef; -/** @} End of group EFR32MG24_SYSCFG */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SYSCFG - * @{ - * @defgroup EFR32MG24_SYSCFG_BitFields SYSCFG Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SYSCFG IPVERSION */ -#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ -#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ -#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ - -/* Bit fields for SYSCFG IF */ -#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ -#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ -#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ -#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ -#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ -#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ -#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ -#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ -#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ -#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ -#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ -#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ -#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ -#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ -#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ -#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ -#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ -#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ -#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ -#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ -#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ -#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ -#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ - -/* Bit fields for SYSCFG IEN */ -#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ -#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ -#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ -#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ -#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ -#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ -#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ -#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ -#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ -#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ -#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ -#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ -#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ -#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ -#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ -#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ -#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ -#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ -#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ -#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ -#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ -#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ -#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ - -/* Bit fields for SYSCFG CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000F01UL /**< Default value for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x0000003CUL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ - -/* Bit fields for SYSCFG CHIPREV */ -#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_MG24 0x0000003CUL /**< Mode MG24 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_BG24 0x0000003DUL /**< Mode BG24 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_MG24 (_SYSCFG_CHIPREV_FAMILY_MG24 << 6) /**< Shifted mode MG24 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_BG24 (_SYSCFG_CHIPREV_FAMILY_BG24 << 6) /**< Shifted mode BG24 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ - -/* Bit fields for SYSCFG CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ - -/* Bit fields for SYSCFG CTRL */ -#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ -#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ -#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ -#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ - -/* Bit fields for SYSCFG DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ - -/* Bit fields for SYSCFG RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ -#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ -#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ - -/* Bit fields for SYSCFG RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ - -/* Bit fields for SYSCFG RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ - -/* Bit fields for SYSCFG SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ -#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ - -/* Bit fields for SYSCFG FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ -#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ - -/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ -#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ -#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ - -/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */ -#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ -#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ - -/* Bit fields for SYSCFG ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ -#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ - -/* Bit fields for SYSCFG ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ -#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ - -/* Bit fields for SYSCFG ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ -#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ - -/* Bit fields for SYSCFG ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ -#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ -#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ - -/** @} End of group EFR32MG24_SYSCFG_BitFields */ -/** @} End of group EFR32MG24_SYSCFG */ -/**************************************************************************//** - * @defgroup EFR32MG24_SYSCFG_CFGNS SYSCFG_CFGNS - * @{ - * @brief EFR32MG24 SYSCFG_CFGNS Register Declaration. - *****************************************************************************/ - -/** SYSCFG_CFGNS Register Declaration. */ -typedef struct { - uint32_t RESERVED0[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */ - uint32_t RESERVED1[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - uint32_t RESERVED3[637U]; /**< Reserved for future use */ - uint32_t RESERVED4[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */ - uint32_t RESERVED5[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[637U]; /**< Reserved for future use */ - uint32_t RESERVED8[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */ - uint32_t RESERVED9[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[637U]; /**< Reserved for future use */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */ - uint32_t RESERVED13[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ -} SYSCFG_CFGNS_TypeDef; -/** @} End of group EFR32MG24_SYSCFG_CFGNS */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SYSCFG_CFGNS - * @{ - * @defgroup EFR32MG24_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SYSCFG CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ -#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ -#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ -#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ -#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ -#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ -#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ -#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ -#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ - -/* Bit fields for SYSCFG ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ -#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ - -/* Bit fields for SYSCFG ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ -#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ - -/** @} End of group EFR32MG24_SYSCFG_CFGNS_BitFields */ -/** @} End of group EFR32MG24_SYSCFG_CFGNS */ -/** @} End of group Parts */ - -#endif // EFR32MG24_SYSCFG_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SYSCFG_H +#define EFR32MG24_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSCFG SYSCFG + * @{ + * @brief EFR32MG24 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED7[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF; /**< RAM Bias Configuration */ + uint32_t RESERVED8[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL; /**< DMEM0 port remap selection */ + uint32_t RESERVED11[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION; /**< SE SW Version */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[635U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED17[54U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED21[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_SET; /**< RAM Bias Configuration */ + uint32_t RESERVED22[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_SET; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_SET; /**< DMEM0 port remap selection */ + uint32_t RESERVED25[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_SET; /**< SE SW Version */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[635U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED31[54U]; /**< Reserved for future use */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + uint32_t RESERVED33[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED35[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_CLR; /**< RAM Bias Configuration */ + uint32_t RESERVED36[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control */ + uint32_t RESERVED37[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_CLR; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_CLR; /**< DMEM0 port remap selection */ + uint32_t RESERVED39[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_CLR; /**< SE SW Version */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[635U]; /**< Reserved for future use */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED43[1U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED45[54U]; /**< Reserved for future use */ + uint32_t RESERVED46[1U]; /**< Reserved for future use */ + uint32_t RESERVED47[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED48[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED49[64U]; /**< Reserved for future use */ + __IOM uint32_t RAMBIASCONF_TGL; /**< RAM Bias Configuration */ + uint32_t RESERVED50[60U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control */ + uint32_t RESERVED51[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + __IOM uint32_t ICACHERAMRETNCTRL_TGL; /**< HOST ICACHERAM Retention Control */ + __IOM uint32_t DMEM0PORTMAPSEL_TGL; /**< DMEM0 port remap selection */ + uint32_t RESERVED53[120U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ + __IOM uint32_t ROOTSESWVERSION_TGL; /**< SE SW Version */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ +} SYSCFG_TypeDef; +/** @} End of group EFR32MG24_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSCFG + * @{ + * @defgroup EFR32MG24_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IPVERSION */ +#define _SYSCFG_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_IPVERSION */ +#define _SYSCFG_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_IPVERSION */ +#define SYSCFG_IPVERSION_IPVERSION_DEFAULT (_SYSCFG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IPVERSION */ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x33033F0FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt Flag */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC (0x1UL << 8) /**< FPU Invalid Operation interrupt flag */ +#define _SYSCFG_IF_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIOC_DEFAULT (_SYSCFG_IF_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC (0x1UL << 9) /**< FPU Divide by zero interrupt flag */ +#define _SYSCFG_IF_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPDZC_DEFAULT (_SYSCFG_IF_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC (0x1UL << 10) /**< FPU Underflow interrupt flag */ +#define _SYSCFG_IF_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPUFC_DEFAULT (_SYSCFG_IF_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC (0x1UL << 11) /**< FPU Overflow interrupt flag */ +#define _SYSCFG_IF_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPOFC_DEFAULT (_SYSCFG_IF_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC (0x1UL << 12) /**< FPU Input denormal interrupt flag */ +#define _SYSCFG_IF_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIDC_DEFAULT (_SYSCFG_IF_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC (0x1UL << 13) /**< FPU Inexact interrupt flag */ +#define _SYSCFG_IF_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FPIXC_DEFAULT (_SYSCFG_IF_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IF_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IF_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIF Interrupt Flag */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IF_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x33033F0FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt Enable */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC (0x1UL << 8) /**< FPU Invalid Operation Interrupt Enable */ +#define _SYSCFG_IEN_FPIOC_SHIFT 8 /**< Shift value for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_MASK 0x100UL /**< Bit mask for SYSCFG_FPIOC */ +#define _SYSCFG_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIOC_DEFAULT (_SYSCFG_IEN_FPIOC_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC (0x1UL << 9) /**< FPU Divide by zero Interrupt Enable */ +#define _SYSCFG_IEN_FPDZC_SHIFT 9 /**< Shift value for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_MASK 0x200UL /**< Bit mask for SYSCFG_FPDZC */ +#define _SYSCFG_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPDZC_DEFAULT (_SYSCFG_IEN_FPDZC_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC (0x1UL << 10) /**< FPU Underflow Interrupt Enable */ +#define _SYSCFG_IEN_FPUFC_SHIFT 10 /**< Shift value for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_MASK 0x400UL /**< Bit mask for SYSCFG_FPUFC */ +#define _SYSCFG_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPUFC_DEFAULT (_SYSCFG_IEN_FPUFC_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC (0x1UL << 11) /**< FPU Overflow Interrupt Enable */ +#define _SYSCFG_IEN_FPOFC_SHIFT 11 /**< Shift value for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_MASK 0x800UL /**< Bit mask for SYSCFG_FPOFC */ +#define _SYSCFG_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPOFC_DEFAULT (_SYSCFG_IEN_FPOFC_DEFAULT << 11) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC (0x1UL << 12) /**< FPU Input denormal Interrupt Enable */ +#define _SYSCFG_IEN_FPIDC_SHIFT 12 /**< Shift value for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_MASK 0x1000UL /**< Bit mask for SYSCFG_FPIDC */ +#define _SYSCFG_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIDC_DEFAULT (_SYSCFG_IEN_FPIDC_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC (0x1UL << 13) /**< FPU Inexact Interrupt Enable */ +#define _SYSCFG_IEN_FPIXC_SHIFT 13 /**< Shift value for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_MASK 0x2000UL /**< Bit mask for SYSCFG_FPIXC */ +#define _SYSCFG_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FPIXC_DEFAULT (_SYSCFG_IEN_FPIXC_DEFAULT << 13) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR (0x1UL << 16) /**< HOST2SRWBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_SHIFT 16 /**< Shift value for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_MASK 0x10000UL /**< Bit mask for SYSCFG_HOST2SRWBUSERR */ +#define _SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT (_SYSCFG_IEN_HOST2SRWBUSERR_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR (0x1UL << 17) /**< SRW2HOSTBUSERRIEN Interrupt Enable */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_SHIFT 17 /**< Shift value for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_MASK 0x20000UL /**< Bit mask for SYSCFG_SRW2HOSTBUSERR */ +#define _SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT (_SYSCFG_IEN_SRW2HOSTBUSERR_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM Error 1-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM Error 2-bit Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000F01UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x0000003CUL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_MG24 0x0000003CUL /**< Mode MG24 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_BG24 0x0000003DUL /**< Mode BG24 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_MG24 (_SYSCFG_CHIPREV_FAMILY_MG24 << 6) /**< Shifted mode MG24 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_BG24 (_SYSCFG_CHIPREV_FAMILY_BG24 << 6) /**< Shifted mode BG24 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000023UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000023UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enabl */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Disabled Clkbus Bus Fault Enable */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for SYSCFG_CLKDISFAULTEN */ +#define _SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT (_SYSCFG_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC error bus fault response ena */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00007FFFUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x7FFFUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 0x00004000UL /**< Mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 0x00006000UL /**< Mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 0x00007000UL /**< Mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 0x00007800UL /**< Mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 0x00007C00UL /**< Mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 0x00007E00UL /**< Mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 0x00007F00UL /**< Mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 0x00007F80UL /**< Mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 0x00007FC0UL /**< Mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 0x00007FE0UL /**< Mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 0x00007FF0UL /**< Mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 0x00007FF8UL /**< Mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 0x00007FFCUL /**< Mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 0x00007FFEUL /**< Mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 0x00007FFFUL /**< Mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK15 << 0) /**< Shifted mode BLK15 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK14TO15 << 0) /**< Shifted mode BLK14TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK13TO15 << 0) /**< Shifted mode BLK13TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK12TO15 << 0) /**< Shifted mode BLK12TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK11TO15 << 0) /**< Shifted mode BLK11TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK10TO15 << 0) /**< Shifted mode BLK10TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK9TO15 << 0) /**< Shifted mode BLK9TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK8TO15 << 0) /**< Shifted mode BLK8TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK7TO15 << 0) /**< Shifted mode BLK7TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK6TO15 << 0) /**< Shifted mode BLK6TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5TO15 << 0) /**< Shifted mode BLK5TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO15 << 0) /**< Shifted mode BLK4TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO15 << 0) /**< Shifted mode BLK3TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO15 << 0) /**< Shifted mode BLK2TO15 for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO15 << 0) /**< Shifted mode BLK1TO15 for SYSCFG_DMEM0RETNCTRL*/ + +/* Bit fields for SYSCFG RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RESETVALUE 0x00000002UL /**< Default value for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_MASK 0x0000000FUL /**< Mask for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_MASK 0xFUL /**< Bit mask for SYSCFG_RAMBIASCTRL */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_No 0x00000000UL /**< Mode No for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 0x00000001UL /**< Mode VSB100 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 0x00000002UL /**< Mode VSB200 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 0x00000004UL /**< Mode VSB300 for SYSCFG_RAMBIASCONF */ +#define _SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 0x00000008UL /**< Mode VSB400 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_No (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_No << 0) /**< Shifted mode No for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB100 << 0) /**< Shifted mode VSB100 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB200 << 0) /**< Shifted mode VSB200 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB300 << 0) /**< Shifted mode VSB300 for SYSCFG_RAMBIASCONF */ +#define SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 (_SYSCFG_RAMBIASCONF_RAMBIASCTRL_VSB400 << 0) /**< Shifted mode VSB400 for SYSCFG_RAMBIASCONF */ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_MASK 0x00000001UL /**< Mask for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL (0x1UL << 0) /**< ICACHERAM Retention control */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_ICACHERAMRETNCTRL */ +#define _SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL */ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_ICACHERAMRETNCTRL*/ +#define SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF (_SYSCFG_ICACHERAMRETNCTRL_RAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_ICACHERAMRETNCTRL*/ + +/* Bit fields for SYSCFG DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_RESETVALUE 0x00007905UL /**< Default value for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MASK 0x0000FFFFUL /**< Mask for SYSCFG_DMEM0PORTMAPSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT 0 /**< Shift value for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_MASK 0x3UL /**< Bit mask for SYSCFG_LDMAPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT 2 /**< Shift value for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_MASK 0xCUL /**< Bit mask for SYSCFG_SRWAESPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT 4 /**< Shift value for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_MASK 0x30UL /**< Bit mask for SYSCFG_AHBSRWPORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT 6 /**< Shift value for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_MASK 0xC0UL /**< Bit mask for SYSCFG_SRWECA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT 8 /**< Shift value for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_MASK 0x300UL /**< Bit mask for SYSCFG_SRWECA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT 10 /**< Shift value for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK 0xC00UL /**< Bit mask for SYSCFG_MVPAHBDATA0PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT 12 /**< Shift value for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK 0x3000UL /**< Bit mask for SYSCFG_MVPAHBDATA1PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT 14 /**< Shift value for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK 0xC000UL /**< Bit mask for SYSCFG_MVPAHBDATA2PORTSEL */ +#define _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL */ +#define SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT (_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for SYSCFG_DMEM0PORTMAPSEL*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x007F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x807F0107UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 16) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 17) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 18) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 19) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 20) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK (0x1UL << 21) /**< Radio Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_SHIFT 21 /**< Shift value for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_MASK 0x200000UL /**< Bit mask for SYSCFG_RADIOIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIOIDBGLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK (0x1UL << 22) /**< Radio Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_SHIFT 22 /**< Shift value for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_MASK 0x400000UL /**< Bit mask for SYSCFG_RADIONIDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIONIDBGLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED (0x1UL << 31) /**< E-Fuse Unlocked */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_SHIFT 31 /**< Shift value for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_MASK 0x80000000UL /**< Bit mask for SYSCFG_EFUSEUNLOCKED */ +#define _SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_EFUSEUNLOCKED_DEFAULT << 31) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/* Bit fields for SYSCFG ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTSESWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_SHIFT 0 /**< Shift value for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SWVERSION */ +#define _SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTSESWVERSION */ +#define SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT (_SYSCFG_ROOTSESWVERSION_SWVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTSESWVERSION*/ + +/** @} End of group EFR32MG24_SYSCFG_BitFields */ +/** @} End of group EFR32MG24_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32MG24 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + uint32_t RESERVED3[637U]; /**< Reserved for future use */ + uint32_t RESERVED4[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED5[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[637U]; /**< Reserved for future use */ + uint32_t RESERVED8[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED9[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-Secure Sys-Tick cal. */ + uint32_t RESERVED13[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32MG24_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSCFG_CFGNS + * @{ + * @defgroup EFR32MG24_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32MG24_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32MG24_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32MG24_SYSCFG_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h index 16b2c31..685c0d2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_sysrtc.h @@ -1,421 +1,421 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 SYSRTC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_SYSRTC_H -#define EFR32MG24_SYSRTC_H -#define SYSRTC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_SYSRTC SYSRTC - * @{ - * @brief EFR32MG24 SYSRTC Register Declaration. - *****************************************************************************/ - -/** SYSRTC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP VERSION */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - uint32_t RESERVED15[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - uint32_t RESERVED17[1U]; /**< Reserved for future use */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[7U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ - __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ - __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ - __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ - __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ - __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ - __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[7U]; /**< Reserved for future use */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ -} SYSRTC_TypeDef; -/** @} End of group EFR32MG24_SYSRTC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_SYSRTC - * @{ - * @defgroup EFR32MG24_SYSRTC_BitFields SYSRTC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SYSRTC IPVERSION */ -#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ -#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ -#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ - -/* Bit fields for SYSRTC EN */ -#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ -#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ -#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ -#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ -#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ -#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ -#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ -#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ - -/* Bit fields for SYSRTC SWRST */ -#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ -#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ -#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ -#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ - -/* Bit fields for SYSRTC CFG */ -#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ -#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ -#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ -#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ -#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ - -/* Bit fields for SYSRTC CMD */ -#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ -#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ -#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ -#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ -#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ -#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ - -/* Bit fields for SYSRTC STATUS */ -#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ -#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ -#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ -#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ -#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ -#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ - -/* Bit fields for SYSRTC CNT */ -#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ -#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ -#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ - -/* Bit fields for SYSRTC SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ -#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ -#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ -#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ -#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ -#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ -#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ -#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ -#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ - -/* Bit fields for SYSRTC LOCK */ -#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ -#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ -#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ -#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ - -/* Bit fields for SYSRTC GRP0_IF */ -#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ -#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ -#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ -#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ - -/* Bit fields for SYSRTC GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ -#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ -#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ -#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ -#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ -#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ -#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ -#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ - -/* Bit fields for SYSRTC GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ -#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ -#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ -#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ -#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ -#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ - -/* Bit fields for SYSRTC GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ -#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ - -/* Bit fields for SYSRTC GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ -#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ - -/* Bit fields for SYSRTC GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ -#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ -#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ - -/* Bit fields for SYSRTC GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ -#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ -#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ -#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ -#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ - -/** @} End of group EFR32MG24_SYSRTC_BitFields */ -/** @} End of group EFR32MG24_SYSRTC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_SYSRTC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 SYSRTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_SYSRTC_H +#define EFR32MG24_SYSRTC_H +#define SYSRTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_SYSRTC SYSRTC + * @{ + * @brief EFR32MG24 SYSRTC Register Declaration. + *****************************************************************************/ + +/** SYSRTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ + __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ + __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ + __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ + __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ + __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ + __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} SYSRTC_TypeDef; +/** @} End of group EFR32MG24_SYSRTC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_SYSRTC + * @{ + * @defgroup EFR32MG24_SYSRTC_BitFields SYSRTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSRTC IPVERSION */ +#define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ +#define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ +#define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ + +/* Bit fields for SYSRTC EN */ +#define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ +#define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ +#define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ +#define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ +#define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ +#define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ +#define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ +#define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ + +/* Bit fields for SYSRTC SWRST */ +#define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ +#define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ +#define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ +#define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ + +/* Bit fields for SYSRTC CFG */ +#define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ +#define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ +#define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ +#define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ +#define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ + +/* Bit fields for SYSRTC CMD */ +#define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ +#define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ +#define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ +#define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ +#define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ +#define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ + +/* Bit fields for SYSRTC STATUS */ +#define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ +#define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ +#define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ +#define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ +#define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ + +/* Bit fields for SYSRTC CNT */ +#define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ +#define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ +#define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ + +/* Bit fields for SYSRTC SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ +#define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ +#define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ +#define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ +#define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ +#define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ +#define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ +#define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ +#define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ + +/* Bit fields for SYSRTC LOCK */ +#define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ +#define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ +#define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ +#define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ + +/* Bit fields for SYSRTC GRP0_IF */ +#define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ +#define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ +#define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ +#define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ + +/* Bit fields for SYSRTC GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ +#define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ +#define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ +#define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ +#define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ +#define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ +#define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ +#define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ + +/* Bit fields for SYSRTC GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ +#define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ +#define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ +#define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ +#define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ +#define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ + +/* Bit fields for SYSRTC GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ +#define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ +#define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ + +/* Bit fields for SYSRTC GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ +#define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ +#define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ + +/* Bit fields for SYSRTC GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ +#define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ +#define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ +#define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ +#define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ + +/** @} End of group EFR32MG24_SYSRTC_BitFields */ +/** @} End of group EFR32MG24_SYSRTC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_SYSRTC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h index 7848198..cd1ea0c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_timer.h @@ -1,1020 +1,1020 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 TIMER register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_TIMER_H -#define EFR32MG24_TIMER_H -#define TIMER_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_TIMER TIMER - * @{ - * @brief EFR32MG24 TIMER Register Declaration. - *****************************************************************************/ - -/** TIMER CC Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG; /**< CC Channel Configuration Register */ - __IOM uint32_t CTRL; /**< CC Channel Control Register */ - __IOM uint32_t OC; /**< OC Channel Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ - __IM uint32_t ICF; /**< IC Channel Value Register */ - __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ -} TIMER_CC_TypeDef; - -/** TIMER Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t TOP; /**< Counter Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN; /**< module en */ - uint32_t RESERVED1[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ - uint32_t RESERVED3[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_SET; /**< module en */ - uint32_t RESERVED5[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED6[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ - uint32_t RESERVED7[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_CLR; /**< module en */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED10[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ - uint32_t RESERVED11[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_TGL; /**< module en */ - uint32_t RESERVED13[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED14[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ -} TIMER_TypeDef; -/** @} End of group EFR32MG24_TIMER */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_TIMER - * @{ - * @defgroup EFR32MG24_TIMER_BitFields TIMER Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for TIMER IPVERSION */ -#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ -#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ - -/* Bit fields for TIMER CFG */ -#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ -#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ -#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ -#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ -#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ -#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ -#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ -#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ -#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ -#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ -#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ -#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ -#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ -#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ -#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ -#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ -#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ -#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ -#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ -#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ -#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ -#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ -#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ -#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ - -/* Bit fields for TIMER CTRL */ -#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ -#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ -#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ - -/* Bit fields for TIMER CMD */ -#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ -#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ -#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ -#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ -#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ -#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ -#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ -#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ -#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ - -/* Bit fields for TIMER STATUS */ -#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ -#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ -#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ -#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ -#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ -#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ -#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ -#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ -#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ - -/* Bit fields for TIMER IF */ -#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ -#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ -#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ -#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ -#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ -#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ -#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ - -/* Bit fields for TIMER IEN */ -#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ -#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ -#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ -#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ -#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ -#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ -#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ -#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ -#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ -#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ -#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ -#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ -#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ -#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ - -/* Bit fields for TIMER TOP */ -#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ -#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ -#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ -#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ - -/* Bit fields for TIMER TOPB */ -#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ -#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ -#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ - -/* Bit fields for TIMER CNT */ -#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ -#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ -#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ -#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ - -/* Bit fields for TIMER LOCK */ -#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ -#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ - -/* Bit fields for TIMER EN */ -#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ -#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ -#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ -#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ -#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ -#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ -#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ - -/* Bit fields for TIMER CC_CFG */ -#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ -#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ -#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ -#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ -#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ - -/* Bit fields for TIMER CC_CTRL */ -#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ -#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ -#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ - -/* Bit fields for TIMER CC_OC */ -#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ -#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ -#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ -#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ -#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ -#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ - -/* Bit fields for TIMER CC_OCB */ -#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ -#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ - -/* Bit fields for TIMER CC_ICF */ -#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ -#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ - -/* Bit fields for TIMER CC_ICOF */ -#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ -#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ - -/* Bit fields for TIMER DTCFG */ -#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ -#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ -#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ -#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ -#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ -#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ -#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ - -/* Bit fields for TIMER DTTIMECFG */ -#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ - -/* Bit fields for TIMER DTFCFG */ -#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ -#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ -#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ - -/* Bit fields for TIMER DTCTRL */ -#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ -#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ -#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ -#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ - -/* Bit fields for TIMER DTOGEN */ -#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ -#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ - -/* Bit fields for TIMER DTFAULT */ -#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ -#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ -#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ -#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ -#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ -#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ -#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ - -/* Bit fields for TIMER DTFAULTC */ -#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ -#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ -#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ -#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ - -/* Bit fields for TIMER DTLOCK */ -#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ - -/** @} End of group EFR32MG24_TIMER_BitFields */ -/** @} End of group EFR32MG24_TIMER */ -/** @} End of group Parts */ - -#endif // EFR32MG24_TIMER_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_TIMER_H +#define EFR32MG24_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_TIMER TIMER + * @{ + * @brief EFR32MG24 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32MG24_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_TIMER + * @{ + * @defgroup EFR32MG24_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000003UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _TIMER_EN_DISABLING_SHIFT 1 /**< Shift value for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_MASK 0x2UL /**< Bit mask for TIMER_DISABLING */ +#define _TIMER_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_DISABLING_DEFAULT (_TIMER_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32MG24_TIMER_BitFields */ +/** @} End of group EFR32MG24_TIMER */ +/** @} End of group Parts */ + +#endif // EFR32MG24_TIMER_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h index bc1f4fd..3a1b5b1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_ulfrco.h @@ -1,147 +1,147 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 ULFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_ULFRCO_H -#define EFR32MG24_ULFRCO_H -#define ULFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_ULFRCO ULFRCO - * @{ - * @brief EFR32MG24 ULFRCO Register Declaration. - *****************************************************************************/ - -/** ULFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED8[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED10[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ -} ULFRCO_TypeDef; -/** @} End of group EFR32MG24_ULFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_ULFRCO - * @{ - * @defgroup EFR32MG24_ULFRCO_BitFields ULFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for ULFRCO IPVERSION */ -#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ -#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ - -/* Bit fields for ULFRCO STATUS */ -#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ -#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ - -/* Bit fields for ULFRCO IF */ -#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ -#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ -#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ -#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ -#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ - -/* Bit fields for ULFRCO IEN */ -#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ -#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ -#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ -#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ -#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ - -/** @} End of group EFR32MG24_ULFRCO_BitFields */ -/** @} End of group EFR32MG24_ULFRCO */ -/** @} End of group Parts */ - -#endif // EFR32MG24_ULFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_ULFRCO_H +#define EFR32MG24_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_ULFRCO ULFRCO + * @{ + * @brief EFR32MG24 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32MG24_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_ULFRCO + * @{ + * @defgroup EFR32MG24_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32MG24_ULFRCO_BitFields */ +/** @} End of group EFR32MG24_ULFRCO */ +/** @} End of group Parts */ + +#endif // EFR32MG24_ULFRCO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h index d80e44a..25b8711 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_usart.h @@ -1,1431 +1,1431 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 USART register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_USART_H -#define EFR32MG24_USART_H -#define USART_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_USART USART - * @{ - * @brief EFR32MG24 USART Register Declaration. - *****************************************************************************/ - -/** USART Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< USART Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t FRAME; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< USART Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Control Register */ - __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL; /**< I2S Control Register */ - __IOM uint32_t TIMING; /**< Timing Register */ - __IOM uint32_t CTRLX; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ - uint32_t RESERVED0[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< USART Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< USART Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ - __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ - __IOM uint32_t TIMING_SET; /**< Timing Register */ - __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ - uint32_t RESERVED1[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< USART Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< USART Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ - __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ - __IOM uint32_t TIMING_CLR; /**< Timing Register */ - __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ - uint32_t RESERVED2[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< USART Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< USART Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ - __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ - __IOM uint32_t TIMING_TGL; /**< Timing Register */ - __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ -} USART_TypeDef; -/** @} End of group EFR32MG24_USART */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_USART - * @{ - * @defgroup EFR32MG24_USART_BitFields USART Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for USART IPVERSION */ -#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ -#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ -#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ - -/* Bit fields for USART EN */ -#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ -#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ -#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ -#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ -#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ -#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ -#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ - -/* Bit fields for USART CTRL */ -#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ -#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ -#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ -#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ -#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ -#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ -#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ -#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ -#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ -#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ -#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ -#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ -#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ -#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ -#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ -#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ -#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ -#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ -#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ -#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ -#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ -#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ -#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ -#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ -#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ -#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ -#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ -#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ -#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ -#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ -#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ -#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ -#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ -#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ -#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ -#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ -#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ -#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ -#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ -#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ -#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ -#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ -#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ -#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ -#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ -#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ -#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ -#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ -#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ -#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ -#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ -#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ -#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ -#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ -#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ -#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ -#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ -#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ - -/* Bit fields for USART FRAME */ -#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ -#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ -#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ -#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ -#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ -#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ -#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ -#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ -#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ -#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ -#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ -#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ -#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ -#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ -#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ -#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ -#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ -#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ -#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ -#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ -#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ -#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ -#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ -#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ -#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ - -/* Bit fields for USART TRIGCTRL */ -#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ -#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ -#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ -#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ -#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ - -/* Bit fields for USART CMD */ -#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ -#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ -#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ -#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ -#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ -#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ -#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ -#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ -#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ -#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ -#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ -#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ -#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ -#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ -#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ -#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ -#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ -#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ -#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ -#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ -#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ -#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ -#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ -#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ -#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ -#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ -#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ -#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ -#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ -#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ -#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ -#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ -#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ -#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ -#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ - -/* Bit fields for USART STATUS */ -#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ -#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ -#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ -#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ -#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ -#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ -#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ -#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ -#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ -#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ -#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ -#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ -#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ -#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ -#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ -#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ -#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ -#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ -#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ -#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ -#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ -#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ -#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ -#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ -#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ -#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ - -/* Bit fields for USART CLKDIV */ -#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ -#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ -#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ -#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ -#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ - -/* Bit fields for USART RXDATAX */ -#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ -#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ -#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ -#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ -#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ -#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ -#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ -#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ -#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ -#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ -#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ - -/* Bit fields for USART RXDATA */ -#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ -#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ -#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ - -/* Bit fields for USART RXDOUBLEX */ -#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ -#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ -#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ -#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ -#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ - -/* Bit fields for USART RXDOUBLE */ -#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ - -/* Bit fields for USART RXDATAXP */ -#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ -#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ -#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ -#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ -#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ -#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ -#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ -#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ -#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ -#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ -#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ - -/* Bit fields for USART RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ -#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ -#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ -#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ -#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ - -/* Bit fields for USART TXDATAX */ -#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ -#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ -#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ -#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ -#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ -#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ -#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ -#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ -#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ -#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ -#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ -#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ - -/* Bit fields for USART TXDATA */ -#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ -#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ -#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ - -/* Bit fields for USART TXDOUBLEX */ -#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ - -/* Bit fields for USART TXDOUBLE */ -#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ - -/* Bit fields for USART IF */ -#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ -#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ -#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ -#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ -#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ -#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ -#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ -#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ -#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ -#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ -#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ -#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ -#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ -#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ -#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ -#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ -#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ -#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ -#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ -#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ -#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ -#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ -#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ -#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ -#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ -#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ -#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ -#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ -#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ -#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ -#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ -#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ -#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ -#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ -#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ -#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ -#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ -#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ -#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ -#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ -#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ -#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ -#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ -#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ -#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ -#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ - -/* Bit fields for USART IEN */ -#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ -#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ -#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ -#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ -#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ -#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ -#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ -#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ -#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ -#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ -#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ -#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ -#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ -#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ -#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ -#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ -#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ -#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ -#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ -#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ -#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ -#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ -#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ -#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ -#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ -#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ -#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ -#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ -#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ -#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ -#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ -#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ -#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ -#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ -#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ -#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ -#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ -#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ -#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ -#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ -#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ -#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ -#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ -#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ -#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ -#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ -#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ -#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ -#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ -#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ -#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ - -/* Bit fields for USART IRCTRL */ -#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ -#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ -#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ -#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ -#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ -#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ -#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ -#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ -#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ -#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ -#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ - -/* Bit fields for USART I2SCTRL */ -#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ -#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ -#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ -#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ -#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ -#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ -#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ -#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ -#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ -#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ -#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ -#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ -#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ -#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ -#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ -#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ -#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ -#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ -#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ -#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ -#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ -#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ - -/* Bit fields for USART TIMING */ -#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ -#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ -#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ -#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ -#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ -#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ -#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ -#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ -#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ -#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ -#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ -#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ - -/* Bit fields for USART CTRLX */ -#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ -#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ -#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ -#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ -#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ -#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ -#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ -#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ -#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ -#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ -#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ -#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ -#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ -#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ -#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ -#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ -#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ -#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ -#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ -#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ - -/* Bit fields for USART TIMECMP0 */ -#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ -#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ -#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ - -/* Bit fields for USART TIMECMP1 */ -#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ -#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ -#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ - -/* Bit fields for USART TIMECMP2 */ -#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ -#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ -#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ - -/** @} End of group EFR32MG24_USART_BitFields */ -/** @} End of group EFR32MG24_USART */ -/** @} End of group Parts */ - -#endif // EFR32MG24_USART_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_USART_H +#define EFR32MG24_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_USART USART + * @{ + * @brief EFR32MG24 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32MG24_USART */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_USART + * @{ + * @defgroup EFR32MG24_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32MG24_USART_BitFields */ +/** @} End of group EFR32MG24_USART */ +/** @} End of group Parts */ + +#endif // EFR32MG24_USART_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h index 29863a2..db8e862 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_vdac.h @@ -1,757 +1,757 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 VDAC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_VDAC_H -#define EFR32MG24_VDAC_H -#define VDAC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_VDAC VDAC - * @{ - * @brief EFR32MG24 VDAC Register Declaration. - *****************************************************************************/ - -/** VDAC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Module Enable */ - __IOM uint32_t SWRST; /**< Software Reset Register */ - __IOM uint32_t CFG; /**< Config Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ - uint32_t RESERVED0[50U]; /**< Reserved for future use */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - uint32_t RESERVED2[63U]; /**< Reserved for future use */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Module Enable */ - __IOM uint32_t SWRST_SET; /**< Software Reset Register */ - __IOM uint32_t CFG_SET; /**< Config Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ - uint32_t RESERVED5[50U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[63U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable */ - __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ - __IOM uint32_t CFG_CLR; /**< Config Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ - uint32_t RESERVED10[50U]; /**< Reserved for future use */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - uint32_t RESERVED14[895U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable */ - __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ - __IOM uint32_t CFG_TGL; /**< Config Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ - __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ - __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ - __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ - __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ - uint32_t RESERVED15[50U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[63U]; /**< Reserved for future use */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ -} VDAC_TypeDef; -/** @} End of group EFR32MG24_VDAC */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_VDAC - * @{ - * @defgroup EFR32MG24_VDAC_BitFields VDAC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for VDAC IPVERSION */ -#define _VDAC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ -#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_IPVERSION */ -#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ - -/* Bit fields for VDAC EN */ -#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ -#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ -#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ -#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ -#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ -#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ -#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ -#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ -#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ -#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ -#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ -#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ -#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ -#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ - -/* Bit fields for VDAC SWRST */ -#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ -#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ -#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ -#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ -#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ -#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ -#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ -#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ - -/* Bit fields for VDAC CFG */ -#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ -#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ -#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ -#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ -#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ -#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ -#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ -#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ -#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ -#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ -#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ -#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ -#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ -#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ -#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ -#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ -#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ -#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ -#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ -#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ -#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ -#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ -#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ -#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ -#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ -#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ -#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ -#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ -#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ -#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ -#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ -#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ -#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ -#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ -#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ -#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ -#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ -#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ - -/* Bit fields for VDAC STATUS */ -#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ -#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ -#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ -#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ -#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ -#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ -#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ -#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ -#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ -#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ -#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ -#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ -#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ -#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ -#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ -#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ -#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ -#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ -#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ -#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ -#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ -#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ -#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ -#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ -#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ -#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ -#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ -#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ -#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ -#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ -#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ -#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ - -/* Bit fields for VDAC CH0CFG */ -#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ -#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ -#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ -#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ -#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ -#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ -#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ - -/* Bit fields for VDAC CH1CFG */ -#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ -#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ -#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ -#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ -#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ -#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ -#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ -#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ -#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ -#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ -#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ -#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ -#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ -#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ - -/* Bit fields for VDAC CMD */ -#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ -#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ -#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ -#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ -#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ -#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ -#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ -#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ -#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ -#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ -#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ -#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ -#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ -#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ -#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ -#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ -#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ -#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ -#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ - -/* Bit fields for VDAC IF */ -#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ -#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ -#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ -#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ -#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ -#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ - -/* Bit fields for VDAC IEN */ -#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ -#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ -#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ -#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ -#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ -#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ -#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ -#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ -#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ -#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ -#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ -#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ -#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ -#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ -#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ -#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ -#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ -#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ -#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ - -/* Bit fields for VDAC CH0F */ -#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ -#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ -#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ -#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ - -/* Bit fields for VDAC CH1F */ -#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ -#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ -#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ -#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ -#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ -#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ - -/* Bit fields for VDAC OUTCTRL */ -#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ -#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ -#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ -#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ -#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ -#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ -#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ -#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ -#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ -#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ - -/* Bit fields for VDAC OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ -#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ -#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ - -/** @} End of group EFR32MG24_VDAC_BitFields */ -/** @} End of group EFR32MG24_VDAC */ -/** @} End of group Parts */ - -#endif // EFR32MG24_VDAC_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 VDAC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_VDAC_H +#define EFR32MG24_VDAC_H +#define VDAC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_VDAC VDAC + * @{ + * @brief EFR32MG24 VDAC Register Declaration. + *****************************************************************************/ + +/** VDAC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Module Enable */ + __IOM uint32_t SWRST; /**< Software Reset Register */ + __IOM uint32_t CFG; /**< Config Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CH0CFG; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG; /**< Channel 1 Config Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG; /**< DAC Out Timer Config Register */ + uint32_t RESERVED0[50U]; /**< Reserved for future use */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + uint32_t RESERVED2[63U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Module Enable */ + __IOM uint32_t SWRST_SET; /**< Software Reset Register */ + __IOM uint32_t CFG_SET; /**< Config Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CH0CFG_SET; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_SET; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_SET; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_SET; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_SET; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_SET; /**< DAC Out Timer Config Register */ + uint32_t RESERVED5[50U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[63U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable */ + __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ + __IOM uint32_t CFG_CLR; /**< Config Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CH0CFG_CLR; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_CLR; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_CLR; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_CLR; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_CLR; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_CLR; /**< DAC Out Timer Config Register */ + uint32_t RESERVED10[50U]; /**< Reserved for future use */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + uint32_t RESERVED14[895U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable */ + __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ + __IOM uint32_t CFG_TGL; /**< Config Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CH0CFG_TGL; /**< Channel 0 Config Register */ + __IOM uint32_t CH1CFG_TGL; /**< Channel 1 Config Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t CH0F_TGL; /**< Channel 0 Data Write Fifo */ + __IOM uint32_t CH1F_TGL; /**< Channel 1 Data Write Fifo */ + __IOM uint32_t OUTCTRL_TGL; /**< DAC Output Control */ + __IOM uint32_t OUTTIMERCFG_TGL; /**< DAC Out Timer Config Register */ + uint32_t RESERVED15[50U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[63U]; /**< Reserved for future use */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ +} VDAC_TypeDef; +/** @} End of group EFR32MG24_VDAC */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_VDAC + * @{ + * @defgroup EFR32MG24_VDAC_BitFields VDAC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for VDAC IPVERSION */ +#define _VDAC_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for VDAC_IPVERSION */ +#define _VDAC_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_IPVERSION */ +#define VDAC_IPVERSION_IPVERSION_DEFAULT (_VDAC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IPVERSION */ + +/* Bit fields for VDAC EN */ +#define _VDAC_EN_RESETVALUE 0x00000000UL /**< Default value for VDAC_EN */ +#define _VDAC_EN_MASK 0x00000003UL /**< Mask for VDAC_EN */ +#define VDAC_EN_EN (0x1UL << 0) /**< VDAC Module Enable */ +#define _VDAC_EN_EN_SHIFT 0 /**< Shift value for VDAC_EN */ +#define _VDAC_EN_EN_MASK 0x1UL /**< Bit mask for VDAC_EN */ +#define _VDAC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define _VDAC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for VDAC_EN */ +#define _VDAC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for VDAC_EN */ +#define VDAC_EN_EN_DEFAULT (_VDAC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_EN */ +#define VDAC_EN_EN_DISABLE (_VDAC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for VDAC_EN */ +#define VDAC_EN_EN_ENABLE (_VDAC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for VDAC_EN */ +#define VDAC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ +#define _VDAC_EN_DISABLING_SHIFT 1 /**< Shift value for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_MASK 0x2UL /**< Bit mask for VDAC_DISABLING */ +#define _VDAC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_EN */ +#define VDAC_EN_DISABLING_DEFAULT (_VDAC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_EN */ + +/* Bit fields for VDAC SWRST */ +#define _VDAC_SWRST_RESETVALUE 0x00000000UL /**< Default value for VDAC_SWRST */ +#define _VDAC_SWRST_MASK 0x00000003UL /**< Mask for VDAC_SWRST */ +#define VDAC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ +#define _VDAC_SWRST_SWRST_SHIFT 0 /**< Shift value for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for VDAC_SWRST */ +#define _VDAC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_SWRST_DEFAULT (_VDAC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ +#define _VDAC_SWRST_RESETTING_SHIFT 1 /**< Shift value for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for VDAC_RESETTING */ +#define _VDAC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_SWRST */ +#define VDAC_SWRST_RESETTING_DEFAULT (_VDAC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_SWRST */ + +/* Bit fields for VDAC CFG */ +#define _VDAC_CFG_RESETVALUE 0x20000000UL /**< Default value for VDAC_CFG */ +#define _VDAC_CFG_MASK 0x7F773FBFUL /**< Mask for VDAC_CFG */ +#define VDAC_CFG_DIFF (0x1UL << 0) /**< Differential Mode */ +#define _VDAC_CFG_DIFF_SHIFT 0 /**< Shift value for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_MASK 0x1UL /**< Bit mask for VDAC_DIFF */ +#define _VDAC_CFG_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DIFF_SINGLEENDED 0x00000000UL /**< Mode SINGLEENDED for VDAC_CFG */ +#define _VDAC_CFG_DIFF_DIFFERENTIAL 0x00000001UL /**< Mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_DIFF_DEFAULT (_VDAC_CFG_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DIFF_SINGLEENDED (_VDAC_CFG_DIFF_SINGLEENDED << 0) /**< Shifted mode SINGLEENDED for VDAC_CFG */ +#define VDAC_CFG_DIFF_DIFFERENTIAL (_VDAC_CFG_DIFF_DIFFERENTIAL << 0) /**< Shifted mode DIFFERENTIAL for VDAC_CFG */ +#define VDAC_CFG_SINEMODE (0x1UL << 1) /**< Sine Mode */ +#define _VDAC_CFG_SINEMODE_SHIFT 1 /**< Shift value for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_MASK 0x2UL /**< Bit mask for VDAC_SINEMODE */ +#define _VDAC_CFG_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_DISSINEMODE 0x00000000UL /**< Mode DISSINEMODE for VDAC_CFG */ +#define _VDAC_CFG_SINEMODE_ENSINEMODE 0x00000001UL /**< Mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DEFAULT (_VDAC_CFG_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_DISSINEMODE (_VDAC_CFG_SINEMODE_DISSINEMODE << 1) /**< Shifted mode DISSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINEMODE_ENSINEMODE (_VDAC_CFG_SINEMODE_ENSINEMODE << 1) /**< Shifted mode ENSINEMODE for VDAC_CFG */ +#define VDAC_CFG_SINERESET (0x1UL << 2) /**< Sine Wave Reset When inactive */ +#define _VDAC_CFG_SINERESET_SHIFT 2 /**< Shift value for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_MASK 0x4UL /**< Bit mask for VDAC_SINERESET */ +#define _VDAC_CFG_SINERESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_SINERESET_DEFAULT (_VDAC_CFG_SINERESET_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST (0x1UL << 3) /**< Channel 0 Start Reset Prescaler */ +#define _VDAC_CFG_CH0PRESCRST_SHIFT 3 /**< Shift value for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_MASK 0x8UL /**< Bit mask for VDAC_CH0PRESCRST */ +#define _VDAC_CFG_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_NORESETPRESC 0x00000000UL /**< Mode NORESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_CH0PRESCRST_RESETPRESC 0x00000001UL /**< Mode RESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_DEFAULT (_VDAC_CFG_CH0PRESCRST_DEFAULT << 3) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_NORESETPRESC (_VDAC_CFG_CH0PRESCRST_NORESETPRESC << 3) /**< Shifted mode NORESETPRESC for VDAC_CFG */ +#define VDAC_CFG_CH0PRESCRST_RESETPRESC (_VDAC_CFG_CH0PRESCRST_RESETPRESC << 3) /**< Shifted mode RESETPRESC for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_SHIFT 4 /**< Shift value for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_MASK 0x30UL /**< Bit mask for VDAC_REFRSEL */ +#define _VDAC_CFG_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V125 0x00000000UL /**< Mode V125 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_V25 0x00000001UL /**< Mode V25 for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_VDD 0x00000002UL /**< Mode VDD for VDAC_CFG */ +#define _VDAC_CFG_REFRSEL_EXT 0x00000003UL /**< Mode EXT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_DEFAULT (_VDAC_CFG_REFRSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V125 (_VDAC_CFG_REFRSEL_V125 << 4) /**< Shifted mode V125 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_V25 (_VDAC_CFG_REFRSEL_V25 << 4) /**< Shifted mode V25 for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_VDD (_VDAC_CFG_REFRSEL_VDD << 4) /**< Shifted mode VDD for VDAC_CFG */ +#define VDAC_CFG_REFRSEL_EXT (_VDAC_CFG_REFRSEL_EXT << 4) /**< Shifted mode EXT for VDAC_CFG */ +#define _VDAC_CFG_PRESC_SHIFT 7 /**< Shift value for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_MASK 0x3F80UL /**< Bit mask for VDAC_PRESC */ +#define _VDAC_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_PRESC_DEFAULT (_VDAC_CFG_PRESC_DEFAULT << 7) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT 16 /**< Shift value for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_MASK 0x70000UL /**< Bit mask for VDAC_TIMEROVRFLOWPERIOD */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT (_VDAC_CFG_TIMEROVRFLOWPERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2 << 16) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4 << 16) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8 << 16) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16 << 16) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32 << 16) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 (_VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 << 16) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_SHIFT 20 /**< Shift value for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_MASK 0x700000UL /**< Bit mask for VDAC_REFRESHPERIOD */ +#define _VDAC_CFG_REFRESHPERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES2 0x00000000UL /**< Mode CYCLES2 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES4 0x00000001UL /**< Mode CYCLES4 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES8 0x00000002UL /**< Mode CYCLES8 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES16 0x00000003UL /**< Mode CYCLES16 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES32 0x00000004UL /**< Mode CYCLES32 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES64 0x00000005UL /**< Mode CYCLES64 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES128 0x00000006UL /**< Mode CYCLES128 for VDAC_CFG */ +#define _VDAC_CFG_REFRESHPERIOD_CYCLES256 0x00000007UL /**< Mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_DEFAULT (_VDAC_CFG_REFRESHPERIOD_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES2 (_VDAC_CFG_REFRESHPERIOD_CYCLES2 << 20) /**< Shifted mode CYCLES2 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES4 (_VDAC_CFG_REFRESHPERIOD_CYCLES4 << 20) /**< Shifted mode CYCLES4 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES8 (_VDAC_CFG_REFRESHPERIOD_CYCLES8 << 20) /**< Shifted mode CYCLES8 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES16 (_VDAC_CFG_REFRESHPERIOD_CYCLES16 << 20) /**< Shifted mode CYCLES16 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES32 (_VDAC_CFG_REFRESHPERIOD_CYCLES32 << 20) /**< Shifted mode CYCLES32 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES64 (_VDAC_CFG_REFRESHPERIOD_CYCLES64 << 20) /**< Shifted mode CYCLES64 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES128 (_VDAC_CFG_REFRESHPERIOD_CYCLES128 << 20) /**< Shifted mode CYCLES128 for VDAC_CFG */ +#define VDAC_CFG_REFRESHPERIOD_CYCLES256 (_VDAC_CFG_REFRESHPERIOD_CYCLES256 << 20) /**< Shifted mode CYCLES256 for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM (0x1UL << 24) /**< Bias Keepwarm Mode Enable */ +#define _VDAC_CFG_BIASKEEPWARM_SHIFT 24 /**< Shift value for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_MASK 0x1000000UL /**< Bit mask for VDAC_BIASKEEPWARM */ +#define _VDAC_CFG_BIASKEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_BIASKEEPWARM_DEFAULT (_VDAC_CFG_BIASKEEPWARM_DEFAULT << 24) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU (0x1UL << 25) /**< VDAC DMA Wakeup */ +#define _VDAC_CFG_DMAWU_SHIFT 25 /**< Shift value for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_MASK 0x2000000UL /**< Bit mask for VDAC_DMAWU */ +#define _VDAC_CFG_DMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DMAWU_DEFAULT (_VDAC_CFG_DMAWU_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK (0x1UL << 26) /**< Always allow clk_dac */ +#define _VDAC_CFG_ONDEMANDCLK_SHIFT 26 /**< Shift value for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_MASK 0x4000000UL /**< Bit mask for VDAC_ONDEMANDCLK */ +#define _VDAC_CFG_ONDEMANDCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_ONDEMANDCLK_DEFAULT (_VDAC_CFG_ONDEMANDCLK_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT (0x1UL << 27) /**< Debug Halt */ +#define _VDAC_CFG_DBGHALT_SHIFT 27 /**< Shift value for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_MASK 0x8000000UL /**< Bit mask for VDAC_DBGHALT */ +#define _VDAC_CFG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for VDAC_CFG */ +#define _VDAC_CFG_DBGHALT_HALT 0x00000001UL /**< Mode HALT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_DEFAULT (_VDAC_CFG_DBGHALT_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_NORMAL (_VDAC_CFG_DBGHALT_NORMAL << 27) /**< Shifted mode NORMAL for VDAC_CFG */ +#define VDAC_CFG_DBGHALT_HALT (_VDAC_CFG_DBGHALT_HALT << 27) /**< Shifted mode HALT for VDAC_CFG */ +#define _VDAC_CFG_WARMUPTIME_SHIFT 28 /**< Shift value for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_MASK 0x70000000UL /**< Bit mask for VDAC_WARMUPTIME */ +#define _VDAC_CFG_WARMUPTIME_DEFAULT 0x00000002UL /**< Mode DEFAULT for VDAC_CFG */ +#define VDAC_CFG_WARMUPTIME_DEFAULT (_VDAC_CFG_WARMUPTIME_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_CFG */ + +/* Bit fields for VDAC STATUS */ +#define _VDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for VDAC_STATUS */ +#define _VDAC_STATUS_MASK 0xFCDBF333UL /**< Mask for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS (0x1UL << 0) /**< Channel 0 Enabled Status */ +#define _VDAC_STATUS_CH0ENS_SHIFT 0 /**< Shift value for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_MASK 0x1UL /**< Bit mask for VDAC_CH0ENS */ +#define _VDAC_STATUS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0ENS_DEFAULT (_VDAC_STATUS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS (0x1UL << 1) /**< Channel 1 Enabled Status */ +#define _VDAC_STATUS_CH1ENS_SHIFT 1 /**< Shift value for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_MASK 0x2UL /**< Bit mask for VDAC_CH1ENS */ +#define _VDAC_STATUS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1ENS_DEFAULT (_VDAC_STATUS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM (0x1UL << 4) /**< Channel 0 Warmed Status */ +#define _VDAC_STATUS_CH0WARM_SHIFT 4 /**< Shift value for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_MASK 0x10UL /**< Bit mask for VDAC_CH0WARM */ +#define _VDAC_STATUS_CH0WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0WARM_DEFAULT (_VDAC_STATUS_CH0WARM_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM (0x1UL << 5) /**< Channel 1 Warmed Status */ +#define _VDAC_STATUS_CH1WARM_SHIFT 5 /**< Shift value for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_MASK 0x20UL /**< Bit mask for VDAC_CH1WARM */ +#define _VDAC_STATUS_CH1WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1WARM_DEFAULT (_VDAC_STATUS_CH1WARM_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL (0x1UL << 8) /**< Channel 0 FIFO Full Status */ +#define _VDAC_STATUS_CH0FIFOFULL_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFULL */ +#define _VDAC_STATUS_CH0FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFULL_DEFAULT (_VDAC_STATUS_CH0FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL (0x1UL << 9) /**< Channel 1 FIFO Full Status */ +#define _VDAC_STATUS_CH1FIFOFULL_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFULL */ +#define _VDAC_STATUS_CH1FIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFULL_DEFAULT (_VDAC_STATUS_CH1FIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH0FIFOCNT_SHIFT 12 /**< Shift value for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_MASK 0x7000UL /**< Bit mask for VDAC_CH0FIFOCNT */ +#define _VDAC_STATUS_CH0FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOCNT_DEFAULT (_VDAC_STATUS_CH0FIFOCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define _VDAC_STATUS_CH1FIFOCNT_SHIFT 15 /**< Shift value for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_MASK 0x38000UL /**< Bit mask for VDAC_CH1FIFOCNT */ +#define _VDAC_STATUS_CH1FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOCNT_DEFAULT (_VDAC_STATUS_CH1FIFOCNT_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE (0x1UL << 19) /**< Channel 0 Current Status */ +#define _VDAC_STATUS_CH0CURRENTSTATE_SHIFT 19 /**< Shift value for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_MASK 0x80000UL /**< Bit mask for VDAC_CH0CURRENTSTATE */ +#define _VDAC_STATUS_CH0CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH0CURRENTSTATE_DEFAULT << 19) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE (0x1UL << 20) /**< Channel 1 Current Status */ +#define _VDAC_STATUS_CH1CURRENTSTATE_SHIFT 20 /**< Shift value for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_MASK 0x100000UL /**< Bit mask for VDAC_CH1CURRENTSTATE */ +#define _VDAC_STATUS_CH1CURRENTSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1CURRENTSTATE_DEFAULT (_VDAC_STATUS_CH1CURRENTSTATE_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY (0x1UL << 22) /**< Channel 0 FIFO Empty Status */ +#define _VDAC_STATUS_CH0FIFOEMPTY_SHIFT 22 /**< Shift value for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_MASK 0x400000UL /**< Bit mask for VDAC_CH0FIFOEMPTY */ +#define _VDAC_STATUS_CH0FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH0FIFOEMPTY_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY (0x1UL << 23) /**< Channel 1 FIFO Empty Status */ +#define _VDAC_STATUS_CH1FIFOEMPTY_SHIFT 23 /**< Shift value for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_MASK 0x800000UL /**< Bit mask for VDAC_CH1FIFOEMPTY */ +#define _VDAC_STATUS_CH1FIFOEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOEMPTY_DEFAULT (_VDAC_STATUS_CH1FIFOEMPTY_DEFAULT << 23) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY (0x1UL << 26) /**< CH0 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_SHIFT 26 /**< Shift value for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_MASK 0x4000000UL /**< Bit mask for VDAC_CH0FIFOFLBUSY */ +#define _VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH0FIFOFLBUSY_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY (0x1UL << 27) /**< CH1 FIFO Flush Sync Busy */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_SHIFT 27 /**< Shift value for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_MASK 0x8000000UL /**< Bit mask for VDAC_CH1FIFOFLBUSY */ +#define _VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT (_VDAC_STATUS_CH1FIFOFLBUSY_DEFAULT << 27) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT (0x1UL << 28) /**< ABUS Input Conflict Status */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_SHIFT 28 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_MASK 0x10000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT (_VDAC_STATUS_ABUSINPUTCONFLICT_DEFAULT << 28) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE (0x1UL << 29) /**< Sine Wave Output Status on Channel */ +#define _VDAC_STATUS_SINEACTIVE_SHIFT 29 /**< Shift value for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_MASK 0x20000000UL /**< Bit mask for VDAC_SINEACTIVE */ +#define _VDAC_STATUS_SINEACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SINEACTIVE_DEFAULT (_VDAC_STATUS_SINEACTIVE_DEFAULT << 29) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR (0x1UL << 30) /**< ABUS Allocation Error Status */ +#define _VDAC_STATUS_ABUSALLOCERR_SHIFT 30 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_MASK 0x40000000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_STATUS_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_ABUSALLOCERR_DEFAULT (_VDAC_STATUS_ABUSALLOCERR_DEFAULT << 30) /**< Shifted mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY (0x1UL << 31) /**< Sync Busy Combined */ +#define _VDAC_STATUS_SYNCBUSY_SHIFT 31 /**< Shift value for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_MASK 0x80000000UL /**< Bit mask for VDAC_SYNCBUSY */ +#define _VDAC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_STATUS */ +#define VDAC_STATUS_SYNCBUSY_DEFAULT (_VDAC_STATUS_SYNCBUSY_DEFAULT << 31) /**< Shifted mode DEFAULT for VDAC_STATUS */ + +/* Bit fields for VDAC CH0CFG */ +#define _VDAC_CH0CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE (0x1UL << 0) /**< Channel 0 Conversion Mode */ +#define _VDAC_CH0CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH0CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_DEFAULT (_VDAC_CH0CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_CONTINUOUS (_VDAC_CH0CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_CONVMODE_SAMPLEOFF (_VDAC_CH0CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE (0x1UL << 2) /**< Channel 0 Power Mode */ +#define _VDAC_CH0CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH0CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_DEFAULT (_VDAC_CH0CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_HIGHPOWER (_VDAC_CH0CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_POWERMODE_LOWPOWER (_VDAC_CH0CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH0CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_DEFAULT (_VDAC_CH0CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_NONE (_VDAC_CH0CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SW (_VDAC_CH0CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_SYNCPRS (_VDAC_CH0CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH0CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_TRIGMODE_ASYNCPRS (_VDAC_CH0CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH0CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH0CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_NONE (_VDAC_CH0CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH0CFG */ +#define VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH0CFG */ +#define _VDAC_CH0CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH0CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_FIFODVL_DEFAULT (_VDAC_CH0CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 0 High Cap Load Mode Enable */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH0CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM (0x1UL << 16) /**< Channel 0 Keepwarm Mode Enable */ +#define _VDAC_CH0CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH0CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0CFG */ +#define VDAC_CH0CFG_KEEPWARM_DEFAULT (_VDAC_CH0CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH0CFG */ + +/* Bit fields for VDAC CH1CFG */ +#define _VDAC_CH1CFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_MASK 0x00015B75UL /**< Mask for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE (0x1UL << 0) /**< Channel 1 Conversion Mode */ +#define _VDAC_CH1CFG_CONVMODE_SHIFT 0 /**< Shift value for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_MASK 0x1UL /**< Bit mask for VDAC_CONVMODE */ +#define _VDAC_CH1CFG_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_CONVMODE_SAMPLEOFF 0x00000001UL /**< Mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_DEFAULT (_VDAC_CH1CFG_CONVMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_CONTINUOUS (_VDAC_CH1CFG_CONVMODE_CONTINUOUS << 0) /**< Shifted mode CONTINUOUS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_CONVMODE_SAMPLEOFF (_VDAC_CH1CFG_CONVMODE_SAMPLEOFF << 0) /**< Shifted mode SAMPLEOFF for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE (0x1UL << 2) /**< Channel 1 Power Mode */ +#define _VDAC_CH1CFG_POWERMODE_SHIFT 2 /**< Shift value for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_MASK 0x4UL /**< Bit mask for VDAC_POWERMODE */ +#define _VDAC_CH1CFG_POWERMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_HIGHPOWER 0x00000000UL /**< Mode HIGHPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_POWERMODE_LOWPOWER 0x00000001UL /**< Mode LOWPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_DEFAULT (_VDAC_CH1CFG_POWERMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_HIGHPOWER (_VDAC_CH1CFG_POWERMODE_HIGHPOWER << 2) /**< Shifted mode HIGHPOWER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_POWERMODE_LOWPOWER (_VDAC_CH1CFG_POWERMODE_LOWPOWER << 2) /**< Shifted mode LOWPOWER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SHIFT 4 /**< Shift value for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_MASK 0x70UL /**< Bit mask for VDAC_TRIGMODE */ +#define _VDAC_CH1CFG_TRIGMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SW 0x00000001UL /**< Mode SW for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_INTERNALTIMER 0x00000004UL /**< Mode INTERNALTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_TRIGMODE_ASYNCPRS 0x00000005UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_DEFAULT (_VDAC_CH1CFG_TRIGMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_NONE (_VDAC_CH1CFG_TRIGMODE_NONE << 4) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SW (_VDAC_CH1CFG_TRIGMODE_SW << 4) /**< Shifted mode SW for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_SYNCPRS (_VDAC_CH1CFG_TRIGMODE_SYNCPRS << 4) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_INTERNALTIMER (_VDAC_CH1CFG_TRIGMODE_INTERNALTIMER << 4) /**< Shifted mode INTERNALTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_TRIGMODE_ASYNCPRS (_VDAC_CH1CFG_TRIGMODE_ASYNCPRS << 4) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SHIFT 8 /**< Shift value for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_MASK 0x300UL /**< Bit mask for VDAC_REFRESHSOURCE */ +#define _VDAC_CH1CFG_REFRESHSOURCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_NONE 0x00000000UL /**< Mode NONE for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER 0x00000001UL /**< Mode REFRESHTIMER for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS 0x00000002UL /**< Mode SYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS 0x00000003UL /**< Mode ASYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_DEFAULT (_VDAC_CH1CFG_REFRESHSOURCE_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_NONE (_VDAC_CH1CFG_REFRESHSOURCE_NONE << 8) /**< Shifted mode NONE for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER (_VDAC_CH1CFG_REFRESHSOURCE_REFRESHTIMER << 8) /**< Shifted mode REFRESHTIMER for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_SYNCPRS << 8) /**< Shifted mode SYNCPRS for VDAC_CH1CFG */ +#define VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS (_VDAC_CH1CFG_REFRESHSOURCE_ASYNCPRS << 8) /**< Shifted mode ASYNCPRS for VDAC_CH1CFG */ +#define _VDAC_CH1CFG_FIFODVL_SHIFT 11 /**< Shift value for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_MASK 0x1800UL /**< Bit mask for VDAC_FIFODVL */ +#define _VDAC_CH1CFG_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_FIFODVL_DEFAULT (_VDAC_CH1CFG_FIFODVL_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN (0x1UL << 14) /**< Channel 1 High Cap Load Mode Enable */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_SHIFT 14 /**< Shift value for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_MASK 0x4000UL /**< Bit mask for VDAC_HIGHCAPLOADEN */ +#define _VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT (_VDAC_CH1CFG_HIGHCAPLOADEN_DEFAULT << 14) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM (0x1UL << 16) /**< Channel 1 Keepwarm Mode Enable */ +#define _VDAC_CH1CFG_KEEPWARM_SHIFT 16 /**< Shift value for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_MASK 0x10000UL /**< Bit mask for VDAC_KEEPWARM */ +#define _VDAC_CH1CFG_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1CFG */ +#define VDAC_CH1CFG_KEEPWARM_DEFAULT (_VDAC_CH1CFG_KEEPWARM_DEFAULT << 16) /**< Shifted mode DEFAULT for VDAC_CH1CFG */ + +/* Bit fields for VDAC CMD */ +#define _VDAC_CMD_RESETVALUE 0x00000000UL /**< Default value for VDAC_CMD */ +#define _VDAC_CMD_MASK 0x00000F33UL /**< Mask for VDAC_CMD */ +#define VDAC_CMD_CH0EN (0x1UL << 0) /**< DAC Channel 0 Enable */ +#define _VDAC_CMD_CH0EN_SHIFT 0 /**< Shift value for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_MASK 0x1UL /**< Bit mask for VDAC_CH0EN */ +#define _VDAC_CMD_CH0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0EN_DEFAULT (_VDAC_CMD_CH0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS (0x1UL << 1) /**< DAC Channel 0 Disable */ +#define _VDAC_CMD_CH0DIS_SHIFT 1 /**< Shift value for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_MASK 0x2UL /**< Bit mask for VDAC_CH0DIS */ +#define _VDAC_CMD_CH0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0DIS_DEFAULT (_VDAC_CMD_CH0DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN (0x1UL << 4) /**< DAC Channel 1 Enable */ +#define _VDAC_CMD_CH1EN_SHIFT 4 /**< Shift value for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_MASK 0x10UL /**< Bit mask for VDAC_CH1EN */ +#define _VDAC_CMD_CH1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1EN_DEFAULT (_VDAC_CMD_CH1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS (0x1UL << 5) /**< DAC Channel 1 Disable */ +#define _VDAC_CMD_CH1DIS_SHIFT 5 /**< Shift value for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_MASK 0x20UL /**< Bit mask for VDAC_CH1DIS */ +#define _VDAC_CMD_CH1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1DIS_DEFAULT (_VDAC_CMD_CH1DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH (0x1UL << 8) /**< CH0 WFIFO Flush */ +#define _VDAC_CMD_CH0FIFOFLUSH_SHIFT 8 /**< Shift value for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_MASK 0x100UL /**< Bit mask for VDAC_CH0FIFOFLUSH */ +#define _VDAC_CMD_CH0FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH0FIFOFLUSH_DEFAULT (_VDAC_CMD_CH0FIFOFLUSH_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH (0x1UL << 9) /**< CH1 WFIFO Flush */ +#define _VDAC_CMD_CH1FIFOFLUSH_SHIFT 9 /**< Shift value for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_MASK 0x200UL /**< Bit mask for VDAC_CH1FIFOFLUSH */ +#define _VDAC_CMD_CH1FIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_CH1FIFOFLUSH_DEFAULT (_VDAC_CMD_CH1FIFOFLUSH_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART (0x1UL << 10) /**< Start Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTART_SHIFT 10 /**< Shift value for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_MASK 0x400UL /**< Bit mask for VDAC_SINEMODESTART */ +#define _VDAC_CMD_SINEMODESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTART_DEFAULT (_VDAC_CMD_SINEMODESTART_DEFAULT << 10) /**< Shifted mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP (0x1UL << 11) /**< Stop Sine Wave Generation */ +#define _VDAC_CMD_SINEMODESTOP_SHIFT 11 /**< Shift value for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_MASK 0x800UL /**< Bit mask for VDAC_SINEMODESTOP */ +#define _VDAC_CMD_SINEMODESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CMD */ +#define VDAC_CMD_SINEMODESTOP_DEFAULT (_VDAC_CMD_SINEMODESTOP_DEFAULT << 11) /**< Shifted mode DEFAULT for VDAC_CMD */ + +/* Bit fields for VDAC IF */ +#define _VDAC_IF_RESETVALUE 0x00000000UL /**< Default value for VDAC_IF */ +#define _VDAC_IF_MASK 0x04340333UL /**< Mask for VDAC_IF */ +#define VDAC_IF_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IF_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0CD_DEFAULT (_VDAC_IF_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IF_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IF_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1CD_DEFAULT (_VDAC_IF_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IF_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0OF_DEFAULT (_VDAC_IF_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IF_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IF_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1OF_DEFAULT (_VDAC_IF_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0UF_DEFAULT (_VDAC_IF_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IF_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1UF_DEFAULT (_VDAC_IF_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR (0x1UL << 18) /**< ABUS Port Allocation Error Flag */ +#define _VDAC_IF_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IF_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSALLOCERR_DEFAULT (_VDAC_IF_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IF_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH0DVL_DEFAULT (_VDAC_IF_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IF_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IF_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_CH1DVL_DEFAULT (_VDAC_IF_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Error Flag */ +#define _VDAC_IF_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IF_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IF */ +#define VDAC_IF_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IF_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IF */ + +/* Bit fields for VDAC IEN */ +#define _VDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for VDAC_IEN */ +#define _VDAC_IEN_MASK 0x04340333UL /**< Mask for VDAC_IEN */ +#define VDAC_IEN_CH0CD (0x1UL << 0) /**< CH0 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH0CD_SHIFT 0 /**< Shift value for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_MASK 0x1UL /**< Bit mask for VDAC_CH0CD */ +#define _VDAC_IEN_CH0CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0CD_DEFAULT (_VDAC_IEN_CH0CD_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD (0x1UL << 1) /**< CH1 Conversion Done Interrupt Flag */ +#define _VDAC_IEN_CH1CD_SHIFT 1 /**< Shift value for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_MASK 0x2UL /**< Bit mask for VDAC_CH1CD */ +#define _VDAC_IEN_CH1CD_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1CD_DEFAULT (_VDAC_IEN_CH1CD_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF (0x1UL << 4) /**< CH0 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH0OF_SHIFT 4 /**< Shift value for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_MASK 0x10UL /**< Bit mask for VDAC_CH0OF */ +#define _VDAC_IEN_CH0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0OF_DEFAULT (_VDAC_IEN_CH0OF_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF (0x1UL << 5) /**< CH1 Data Overflow Interrupt Flag */ +#define _VDAC_IEN_CH1OF_SHIFT 5 /**< Shift value for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_MASK 0x20UL /**< Bit mask for VDAC_CH1OF */ +#define _VDAC_IEN_CH1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1OF_DEFAULT (_VDAC_IEN_CH1OF_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF (0x1UL << 8) /**< CH0 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH0UF_SHIFT 8 /**< Shift value for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_MASK 0x100UL /**< Bit mask for VDAC_CH0UF */ +#define _VDAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0UF_DEFAULT (_VDAC_IEN_CH0UF_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF (0x1UL << 9) /**< CH1 Data Underflow Interrupt Flag */ +#define _VDAC_IEN_CH1UF_SHIFT 9 /**< Shift value for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_MASK 0x200UL /**< Bit mask for VDAC_CH1UF */ +#define _VDAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1UF_DEFAULT (_VDAC_IEN_CH1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR (0x1UL << 18) /**< ABUS Allocation Error Interrupt Flag */ +#define _VDAC_IEN_ABUSALLOCERR_SHIFT 18 /**< Shift value for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_MASK 0x40000UL /**< Bit mask for VDAC_ABUSALLOCERR */ +#define _VDAC_IEN_ABUSALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSALLOCERR_DEFAULT (_VDAC_IEN_ABUSALLOCERR_DEFAULT << 18) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL (0x1UL << 20) /**< CH0 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH0DVL_SHIFT 20 /**< Shift value for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_MASK 0x100000UL /**< Bit mask for VDAC_CH0DVL */ +#define _VDAC_IEN_CH0DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH0DVL_DEFAULT (_VDAC_IEN_CH0DVL_DEFAULT << 20) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL (0x1UL << 21) /**< CH1 Data Valid Level Interrupt Flag */ +#define _VDAC_IEN_CH1DVL_SHIFT 21 /**< Shift value for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_MASK 0x200000UL /**< Bit mask for VDAC_CH1DVL */ +#define _VDAC_IEN_CH1DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_CH1DVL_DEFAULT (_VDAC_IEN_CH1DVL_DEFAULT << 21) /**< Shifted mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT (0x1UL << 26) /**< ABUS Input Conflict Interrupt Flag */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_SHIFT 26 /**< Shift value for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_MASK 0x4000000UL /**< Bit mask for VDAC_ABUSINPUTCONFLICT */ +#define _VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_IEN */ +#define VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT (_VDAC_IEN_ABUSINPUTCONFLICT_DEFAULT << 26) /**< Shifted mode DEFAULT for VDAC_IEN */ + +/* Bit fields for VDAC CH0F */ +#define _VDAC_CH0F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH0F */ +#define _VDAC_CH0F_MASK 0x00000FFFUL /**< Mask for VDAC_CH0F */ +#define _VDAC_CH0F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH0F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH0F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH0F */ +#define VDAC_CH0F_DATA_DEFAULT (_VDAC_CH0F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH0F */ + +/* Bit fields for VDAC CH1F */ +#define _VDAC_CH1F_RESETVALUE 0x00000000UL /**< Default value for VDAC_CH1F */ +#define _VDAC_CH1F_MASK 0x00000FFFUL /**< Mask for VDAC_CH1F */ +#define _VDAC_CH1F_DATA_SHIFT 0 /**< Shift value for VDAC_DATA */ +#define _VDAC_CH1F_DATA_MASK 0xFFFUL /**< Bit mask for VDAC_DATA */ +#define _VDAC_CH1F_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_CH1F */ +#define VDAC_CH1F_DATA_DEFAULT (_VDAC_CH1F_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_CH1F */ + +/* Bit fields for VDAC OUTCTRL */ +#define _VDAC_OUTCTRL_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_MASK 0x7FDFF333UL /**< Mask for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0 (0x1UL << 0) /**< CH0 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT 0 /**< Shift value for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_MASK 0x1UL /**< Bit mask for VDAC_MAINOUTENCH0 */ +#define _VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1 (0x1UL << 1) /**< CH1 Main Output Enable */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT 1 /**< Shift value for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_MASK 0x2UL /**< Bit mask for VDAC_MAINOUTENCH1 */ +#define _VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT (_VDAC_OUTCTRL_MAINOUTENCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0 (0x1UL << 4) /**< CH0 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT 4 /**< Shift value for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_MASK 0x10UL /**< Bit mask for VDAC_AUXOUTENCH0 */ +#define _VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH0_DEFAULT << 4) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1 (0x1UL << 5) /**< CH1 Alternative Output Enable */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT 5 /**< Shift value for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_MASK 0x20UL /**< Bit mask for VDAC_AUXOUTENCH1 */ +#define _VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT (_VDAC_OUTCTRL_AUXOUTENCH1_DEFAULT << 5) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0 (0x1UL << 8) /**< CH1 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH0_SHIFT 8 /**< Shift value for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_MASK 0x100UL /**< Bit mask for VDAC_SHORTCH0 */ +#define _VDAC_OUTCTRL_SHORTCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH0_DEFAULT (_VDAC_OUTCTRL_SHORTCH0_DEFAULT << 8) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1 (0x1UL << 9) /**< CH0 Main and Alternative Output Short */ +#define _VDAC_OUTCTRL_SHORTCH1_SHIFT 9 /**< Shift value for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_MASK 0x200UL /**< Bit mask for VDAC_SHORTCH1 */ +#define _VDAC_OUTCTRL_SHORTCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_SHORTCH1_DEFAULT (_VDAC_OUTCTRL_SHORTCH1_DEFAULT << 9) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT 12 /**< Shift value for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK 0x7000UL /**< Bit mask for VDAC_ABUSPORTSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH0_DEFAULT << 12) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH0_NONE << 12) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA << 12) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB << 12) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC << 12) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD << 12) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT 15 /**< Shift value for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_MASK 0x1F8000UL /**< Bit mask for VDAC_ABUSPINSELCH0 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH0_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT 22 /**< Shift value for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK 0x1C00000UL /**< Bit mask for VDAC_ABUSPORTSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_NONE 0x00000000UL /**< Mode NONE for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA 0x00000001UL /**< Mode PORTA for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB 0x00000002UL /**< Mode PORTB for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC 0x00000003UL /**< Mode PORTC for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD 0x00000004UL /**< Mode PORTD for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPORTSELCH1_DEFAULT << 22) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_NONE (_VDAC_OUTCTRL_ABUSPORTSELCH1_NONE << 22) /**< Shifted mode NONE for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTA << 22) /**< Shifted mode PORTA for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTB << 22) /**< Shifted mode PORTB for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTC << 22) /**< Shifted mode PORTC for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD (_VDAC_OUTCTRL_ABUSPORTSELCH1_PORTD << 22) /**< Shifted mode PORTD for VDAC_OUTCTRL */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT 25 /**< Shift value for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_MASK 0x7E000000UL /**< Bit mask for VDAC_ABUSPINSELCH1 */ +#define _VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTCTRL */ +#define VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT (_VDAC_OUTCTRL_ABUSPINSELCH1_DEFAULT << 25) /**< Shifted mode DEFAULT for VDAC_OUTCTRL */ + +/* Bit fields for VDAC OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_RESETVALUE 0x00000000UL /**< Default value for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_MASK 0x01FF83FFUL /**< Mask for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT 0 /**< Shift value for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK 0x3FFUL /**< Bit mask for VDAC_CH0OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_DEFAULT << 0) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT 15 /**< Shift value for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK 0x1FF8000UL /**< Bit mask for VDAC_CH1OUTHOLDTIME */ +#define _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for VDAC_OUTTIMERCFG */ +#define VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT (_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_DEFAULT << 15) /**< Shifted mode DEFAULT for VDAC_OUTTIMERCFG */ + +/** @} End of group EFR32MG24_VDAC_BitFields */ +/** @} End of group EFR32MG24_VDAC */ +/** @} End of group Parts */ + +#endif // EFR32MG24_VDAC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h index 4955724..1b00950 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24_wdog.h @@ -1,375 +1,375 @@ -/**************************************************************************//** - * @file - * @brief EFR32MG24 WDOG register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24_WDOG_H -#define EFR32MG24_WDOG_H -#define WDOG_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32MG24_WDOG WDOG - * @{ - * @brief EFR32MG24 WDOG Register Declaration. - *****************************************************************************/ - -/** WDOG Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ -} WDOG_TypeDef; -/** @} End of group EFR32MG24_WDOG */ - -/**************************************************************************//** - * @addtogroup EFR32MG24_WDOG - * @{ - * @defgroup EFR32MG24_WDOG_BitFields WDOG Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for WDOG IPVERSION */ -#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ -#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ - -/* Bit fields for WDOG EN */ -#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ -#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ -#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ -#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ -#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ -#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ -#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ - -/* Bit fields for WDOG CFG */ -#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ -#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ -#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ -#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ -#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ -#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ -#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ -#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ -#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ -#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ -#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ - -/* Bit fields for WDOG CMD */ -#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ -#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ -#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ -#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ -#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ - -/* Bit fields for WDOG STATUS */ -#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ -#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ -#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ -#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ - -/* Bit fields for WDOG IF */ -#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ -#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ -#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ -#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ -#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ - -/* Bit fields for WDOG IEN */ -#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ -#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ -#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ -#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ -#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ -#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ - -/* Bit fields for WDOG LOCK */ -#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ -#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ - -/* Bit fields for WDOG SYNCBUSY */ -#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ -#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ -#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ - -/** @} End of group EFR32MG24_WDOG_BitFields */ -/** @} End of group EFR32MG24_WDOG */ -/** @} End of group Parts */ - -#endif // EFR32MG24_WDOG_H +/**************************************************************************//** + * @file + * @brief EFR32MG24 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24_WDOG_H +#define EFR32MG24_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32MG24_WDOG WDOG + * @{ + * @brief EFR32MG24 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32MG24_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32MG24_WDOG + * @{ + * @defgroup EFR32MG24_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000003UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING (0x1UL << 1) /**< Disabling busy status */ +#define _WDOG_EN_DISABLING_SHIFT 1 /**< Shift value for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_MASK 0x2UL /**< Bit mask for WDOG_DISABLING */ +#define _WDOG_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_DISABLING_DEFAULT (_WDOG_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F073FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM1RUN (0x1UL << 1) /**< EM1 Run */ +#define _WDOG_CFG_EM1RUN_SHIFT 1 /**< Shift value for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_MASK 0x2UL /**< Bit mask for WDOG_EM1RUN */ +#define _WDOG_CFG_EM1RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM1RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DEFAULT (_WDOG_CFG_EM1RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_DISABLE (_WDOG_CFG_EM1RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM1RUN_ENABLE (_WDOG_CFG_EM1RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 2) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 2 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x4UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 3) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 3 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x8UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 4) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 4 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x10UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 5) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 5 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x20UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 5) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 5) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 5) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32MG24_WDOG_BitFields */ +/** @} End of group EFR32MG24_WDOG */ +/** @} End of group Parts */ + +#endif // EFR32MG24_WDOG_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h index 25a82af..be49139 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/efr32mg24b220f1536im48.h @@ -1,1520 +1,1520 @@ -/**************************************************************************//** - * @file - * @brief CMSIS Cortex-M Peripheral Access Layer Header File - * for EFR32MG24B220F1536IM48 - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32MG24B220F1536IM48_H -#define EFR32MG24B220F1536IM48_H - -#ifdef __cplusplus -extern "C" { -#endif - -/**************************************************************************//** - * @addtogroup Parts - * @{ - *****************************************************************************/ - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48 EFR32MG24B220F1536IM48 - * @{ - *****************************************************************************/ - -/** Interrupt Number Definition */ -typedef enum IRQn{ - /****** Cortex-M Processor Exceptions Numbers ******************************************/ - NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ - - /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ - - SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ - SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ - SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ - EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ - TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ - TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ - TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ - TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ - TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ - USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ - USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ - EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ - EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ - EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ - EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ - MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ - ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ - BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ - LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ - SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ - MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ - LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ - LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ - LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ - ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ - GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ - GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ - I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ - I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ - EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ - AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ - BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ - FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ - FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ - MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ - PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ - RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ - RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ - HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ - SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ - ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ - ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ - WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ - WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ - HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ - HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ - HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ - CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ - AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ - IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ - MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ - DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ - EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ - DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ - PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ - SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ - SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ - SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ - SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ - KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ - KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ - M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ - M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ - FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ - SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ - SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ - SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ - SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ - SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ - KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ - RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ - RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ - VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ - VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ - AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ - AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ -} IRQn_Type; - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48_Core EFR32MG24B220F1536IM48 Core - * @{ - * @brief Processor and Core Peripheral Section - *****************************************************************************/ - -#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ -#define __DSP_PRESENT 1U /**< Presence of DSP */ -#define __FPU_PRESENT 1U /**< Presence of FPU */ -#define __MPU_PRESENT 1U /**< Presence of MPU */ -#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ -#define __TZ_PRESENT 1U /**< Presence of TrustZone */ -#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ -#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ -#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ - -/** @} End of group EFR32MG24B220F1536IM48_Core */ - -/**************************************************************************//** -* @defgroup EFR32MG24B220F1536IM48_Part EFR32MG24B220F1536IM48 Part -* @{ -******************************************************************************/ - -/** Part number */ - -/* If part number is not defined as compiler option, define it */ -#if !defined(EFR32MG24B220F1536IM48) -#define EFR32MG24B220F1536IM48 1 /**< FULL Part */ -#endif - -/** Configure part number */ -#define PART_NUMBER "EFR32MG24B220F1536IM48" /**< Part Number */ - -/** Family / Line / Series / Config */ -#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ -#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ -#define _EFR_DEVICE 1 /** Product Line Identifier */ -#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ -#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ -#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ -#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ -#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ -#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ -#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ -#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ -#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ -#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ -#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ -#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ -#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ -#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ -#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ -#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ -#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ -#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ -#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ -#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ - -/** Memory Base addresses and limits */ -#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ -#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ -#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ -#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ -#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ -#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ -#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ -#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ -#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ -#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ -#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ -#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ -#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ -#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ -#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ -#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ -#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ -#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ -#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ -#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ -#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ -#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ -#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ -#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ -#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ -#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ -#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ -#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ -#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ -#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ -#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ -#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ -#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ -#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ -#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ -#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ -#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ -#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ -#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ -#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ -#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ -#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ -#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ -#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ -#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ -#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ -#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ -#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ -#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ - -/** Flash and SRAM limits for EFR32MG24B220F1536IM48 */ -#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ -#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ -#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ -#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ -#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ -#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ -#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ - -/* GPIO Avalibility Info */ -#define GPIO_PA_INDEX 0U /**< Index of port PA */ -#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ -#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ -#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ -#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ -#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ -#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ -#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ -#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ -#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ -#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ -#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ -#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ -#define GPIO_PB_INDEX 1U /**< Index of port PB */ -#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ -#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ -#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ -#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ -#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ -#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ -#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ -#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ -#define GPIO_PC_INDEX 2U /**< Index of port PC */ -#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ -#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ -#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ -#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ -#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ -#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ -#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ -#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ -#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ -#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ -#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ -#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ -#define GPIO_PD_INDEX 3U /**< Index of port PD */ -#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ -#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ -#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ -#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ -#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ -#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ -#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ -#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ - -/* Fixed Resource Locations */ -#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ -#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ -#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ -#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ -#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ -#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ -#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ -#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ -#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ -#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ -#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ -#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ -#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ -#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ -#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ -#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ -#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ -#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ -#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ -#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ -#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ -#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ -#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ -#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ -#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ -#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ -#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ -#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ -#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ -#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ -#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ -#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ -#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ -#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ -#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ -#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ -#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ -#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ -#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ -#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ -#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ -#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ -#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ -#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ -#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ -#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ -#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ -#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ -#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ -#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ -#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ -#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ -#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ -#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ -#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ -#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ -#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ -#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ -#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ -#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ - -/* Part number capabilities */ -#define ACMP_PRESENT /** ACMP is available in this part */ -#define ACMP_COUNT 2 /** 2 ACMPs available */ -#define BURAM_PRESENT /** BURAM is available in this part */ -#define BURAM_COUNT 1 /** 1 BURAMs available */ -#define BURTC_PRESENT /** BURTC is available in this part */ -#define BURTC_COUNT 1 /** 1 BURTCs available */ -#define CMU_PRESENT /** CMU is available in this part */ -#define CMU_COUNT 1 /** 1 CMUs available */ -#define DCDC_PRESENT /** DCDC is available in this part */ -#define DCDC_COUNT 1 /** 1 DCDCs available */ -#define DMEM_PRESENT /** DMEM is available in this part */ -#define DMEM_COUNT 1 /** 1 DMEMs available */ -#define DPLL_PRESENT /** DPLL is available in this part */ -#define DPLL_COUNT 1 /** 1 DPLLs available */ -#define EMU_PRESENT /** EMU is available in this part */ -#define EMU_COUNT 1 /** 1 EMUs available */ -#define EUSART_PRESENT /** EUSART is available in this part */ -#define EUSART_COUNT 2 /** 2 EUSARTs available */ -#define FSRCO_PRESENT /** FSRCO is available in this part */ -#define FSRCO_COUNT 1 /** 1 FSRCOs available */ -#define GPCRC_PRESENT /** GPCRC is available in this part */ -#define GPCRC_COUNT 1 /** 1 GPCRCs available */ -#define GPIO_PRESENT /** GPIO is available in this part */ -#define GPIO_COUNT 1 /** 1 GPIOs available */ -#define HFRCO_PRESENT /** HFRCO is available in this part */ -#define HFRCO_COUNT 1 /** 1 HFRCOs available */ -#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ -#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ -#define HFXO_PRESENT /** HFXO is available in this part */ -#define HFXO_COUNT 1 /** 1 HFXOs available */ -#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ -#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ -#define I2C_PRESENT /** I2C is available in this part */ -#define I2C_COUNT 2 /** 2 I2Cs available */ -#define IADC_PRESENT /** IADC is available in this part */ -#define IADC_COUNT 1 /** 1 IADCs available */ -#define ICACHE_PRESENT /** ICACHE is available in this part */ -#define ICACHE_COUNT 1 /** 1 ICACHEs available */ -#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ -#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ -#define LDMA_PRESENT /** LDMA is available in this part */ -#define LDMA_COUNT 1 /** 1 LDMAs available */ -#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ -#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ -#define LETIMER_PRESENT /** LETIMER is available in this part */ -#define LETIMER_COUNT 1 /** 1 LETIMERs available */ -#define LFRCO_PRESENT /** LFRCO is available in this part */ -#define LFRCO_COUNT 1 /** 1 LFRCOs available */ -#define LFXO_PRESENT /** LFXO is available in this part */ -#define LFXO_COUNT 1 /** 1 LFXOs available */ -#define MSC_PRESENT /** MSC is available in this part */ -#define MSC_COUNT 1 /** 1 MSCs available */ -#define MVP_PRESENT /** MVP is available in this part */ -#define MVP_COUNT 1 /** 1 MVPs available */ -#define PCNT_PRESENT /** PCNT is available in this part */ -#define PCNT_COUNT 1 /** 1 PCNTs available */ -#define PRS_PRESENT /** PRS is available in this part */ -#define PRS_COUNT 1 /** 1 PRSs available */ -#define RADIOAES_PRESENT /** RADIOAES is available in this part */ -#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ -#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ -#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ -#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ -#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ -#define SMU_PRESENT /** SMU is available in this part */ -#define SMU_COUNT 1 /** 1 SMUs available */ -#define SYSCFG_PRESENT /** SYSCFG is available in this part */ -#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ -#define SYSRTC_PRESENT /** SYSRTC is available in this part */ -#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ -#define TIMER_PRESENT /** TIMER is available in this part */ -#define TIMER_COUNT 5 /** 5 TIMERs available */ -#define ULFRCO_PRESENT /** ULFRCO is available in this part */ -#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ -#define USART_PRESENT /** USART is available in this part */ -#define USART_COUNT 1 /** 1 USARTs available */ -#define VDAC_PRESENT /** VDAC is available in this part */ -#define VDAC_COUNT 2 /** 2 VDACs available */ -#define WDOG_PRESENT /** WDOG is available in this part */ -#define WDOG_COUNT 2 /** 2 WDOGs available */ -#define DEVINFO_PRESENT /** DEVINFO is available in this part */ -#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ - -/* Include standard ARM headers for the core */ -#include "core_cm33.h" /* Core Header File */ -#include "system_efr32mg24.h" /* System Header File */ - -/** @} End of group EFR32MG24B220F1536IM48_Part */ - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48_Peripheral_TypeDefs EFR32MG24B220F1536IM48 Peripheral TypeDefs - * @{ - * @brief Device Specific Peripheral Register Structures - *****************************************************************************/ -#include "efr32mg24_scratchpad.h" -#include "efr32mg24_emu.h" -#include "efr32mg24_cmu.h" -#include "efr32mg24_hfrco.h" -#include "efr32mg24_fsrco.h" -#include "efr32mg24_dpll.h" -#include "efr32mg24_lfxo.h" -#include "efr32mg24_lfrco.h" -#include "efr32mg24_ulfrco.h" -#include "efr32mg24_msc.h" -#include "efr32mg24_icache.h" -#include "efr32mg24_prs.h" -#include "efr32mg24_gpio.h" -#include "efr32mg24_ldma.h" -#include "efr32mg24_ldmaxbar.h" -#include "efr32mg24_timer.h" -#include "efr32mg24_usart.h" -#include "efr32mg24_burtc.h" -#include "efr32mg24_i2c.h" -#include "efr32mg24_syscfg.h" -#include "efr32mg24_buram.h" -#include "efr32mg24_gpcrc.h" -#include "efr32mg24_dcdc.h" -#include "efr32mg24_mailbox.h" -#include "efr32mg24_eusart.h" -#include "efr32mg24_sysrtc.h" -#include "efr32mg24_keyscan.h" -#include "efr32mg24_mpahbram.h" -#include "efr32mg24_aes.h" -#include "efr32mg24_smu.h" -#include "efr32mg24_letimer.h" -#include "efr32mg24_iadc.h" -#include "efr32mg24_acmp.h" -#include "efr32mg24_vdac.h" -#include "efr32mg24_pcnt.h" -#include "efr32mg24_hfxo.h" -#include "efr32mg24_wdog.h" -#include "efr32mg24_semailbox.h" -#include "efr32mg24_mvp.h" -#include "efr32mg24_devinfo.h" - -/* Custom headers for LDMAXBAR and PRS mappings */ -#include "efr32mg24_prs_signals.h" -#include "efr32mg24_dma_descriptor.h" -#include "efr32mg24_ldmaxbar_defines.h" - -/** @} End of group EFR32MG24B220F1536IM48_Peripheral_TypeDefs */ - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48_Peripheral_Base EFR32MG24B220F1536IM48 Peripheral Memory Map - * @{ - *****************************************************************************/ - -#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ -#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ -#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ -#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ -#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ -#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ -#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ -#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ -#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ -#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ -#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ -#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ -#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ -#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ -#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ -#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ -#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ -#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ -#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ -#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ -#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ -#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ -#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ -#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ -#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ -#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ -#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ -#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ -#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ -#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ -#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ -#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ -#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ -#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ -#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ -#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ -#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ -#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ -#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ -#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ -#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ -#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ -#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ -#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ -#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ -#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ -#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ -#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ -#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ -#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ -#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ -#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ -#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ -#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ -#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ -#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ -#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ -#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ -#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ -#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ -#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ -#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ -#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ -#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ -#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ -#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ -#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ -#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ -#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ -#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ -#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ -#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ -#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ -#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ -#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ -#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ -#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ -#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ -#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ -#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ -#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ -#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ -#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ -#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ -#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ -#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ -#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ -#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ -#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ -#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ -#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ -#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ -#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ -#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ -#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ -#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ -#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ -#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ -#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ -#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ -#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ -#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" - -#endif -#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) -#include "sl_trustzone_secure_config.h" - -#endif - -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) -#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ -#else -#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) -#define EMU_BASE (EMU_S_BASE) /* EMU base address */ -#else -#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) -#define CMU_BASE (CMU_S_BASE) /* CMU base address */ -#else -#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) -#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ -#else -#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) -#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ -#else -#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) -#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ -#else -#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) -#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ -#else -#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) -#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ -#else -#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) -#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ -#else -#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) -#define MSC_BASE (MSC_S_BASE) /* MSC base address */ -#else -#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) -#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ -#else -#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) -#define PRS_BASE (PRS_S_BASE) /* PRS base address */ -#else -#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) -#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ -#else -#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) -#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ -#else -#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) -#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ -#else -#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) -#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ -#else -#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) -#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ -#else -#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) -#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ -#else -#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) -#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ -#else -#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) -#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ -#else -#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) -#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ -#else -#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) -#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ -#else -#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) -#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ -#else -#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) -#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ -#else -#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) -#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ -#else -#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) -#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ -#else -#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) -#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ -#else -#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) -#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ -#else -#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) -#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ -#else -#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) -#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ -#else -#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) -#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ -#else -#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) -#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ -#else -#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) -#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ -#else -#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) -#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ -#else -#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) -#define SMU_BASE (SMU_S_BASE) /* SMU base address */ -#else -#define SMU_BASE (SMU_S_BASE) /* SMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) -#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ -#else -#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) -#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ -#else -#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) -#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ -#else -#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) -#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ -#else -#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) -#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ -#else -#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) -#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ -#else -#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) -#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ -#else -#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) -#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ -#else -#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) -#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ -#else -#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) -#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ -#else -#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) -#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ -#else -#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) -#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ -#else -#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) -#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ -#else -#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) -#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ -#else -#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) -#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ -#else -#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) -#define MVP_BASE (MVP_S_BASE) /* MVP base address */ -#else -#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S - -#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ -/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Base */ - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48_Peripheral_Declaration EFR32MG24B220F1536IM48 Peripheral Declarations Map - * @{ - *****************************************************************************/ - -#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ -#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ -#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ -#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ -#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ -#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ -#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ -#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ -#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ -#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ -#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ -#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ -#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ -#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ -#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ -#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ -#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ -#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ -#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ -#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ -#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ -#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ -#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ -#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ -#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ -#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ -#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ -#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ -#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ -#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ -#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ -#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ -#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ -#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ -#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ -#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ -#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ -#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ -#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ -#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ -#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ -#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ -#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ -#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ -#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ -#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ -#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ -#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ -#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ -#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ -#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ -#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ -#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ -#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ -#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ -#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ -#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ -#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ -#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ -#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ -#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ -#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ -#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ -#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ -#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ -#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ -#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ -#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ -#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ -#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ -#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ -#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ -#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ -#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ -#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ -#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ -#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ -#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ -#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ -#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ -#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ -#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ -#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ -#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ -#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ -#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ -#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ -#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ -#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ -#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ -#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ -#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ -#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ -#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ -#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ -#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ -#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ -#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ -#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ -#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ -#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ -#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ -#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ -#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ -#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ -#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ -#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ -#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ -#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ -#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ -#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ -#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ -#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ -#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ -#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ -#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ -#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ -#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ -#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ -#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ -#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ -#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ -#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ -#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ -#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ -#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ -#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ -#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ -#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ -#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ -#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ -#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ -#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ -#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ -#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ -#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ -#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ -#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ -#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ -#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ -#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ -#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ -#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ -#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ -#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ -#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ -#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ -#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ -#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ -#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ -#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ -/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Declaration */ - -/**************************************************************************//** - * @defgroup EFR32MG24B220F1536IM48_Peripheral_Parameters EFR32MG24B220F1536IM48 Peripheral Parameters - * @{ - * @brief Device peripheral parameter values - *****************************************************************************/ - -/* Common peripheral register block offsets. */ -#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ -#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ -#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ -#define MSC_CDA_PRESENT 0x0UL /**> */ -#define MSC_FDIO_WIDTH 0x40UL /**> None */ -#define MSC_FLASHADDRBITS 0x15UL /**> None */ -#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ -#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ -#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ -#define MSC_INFOADDRBITS 0xEUL /**> None */ -#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ -#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ -#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ -#define MSC_REDUNDANCY 0x2UL /**> None */ -#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ -#define MSC_UD_PRESENT 0x1UL /**> */ -#define MSC_YADDRBITS 0x6UL /**> */ -#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ -#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ -#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ -#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ -#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ -#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ -#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ -#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ -#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ -#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ -#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ -#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ -#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ -#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ -#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ -#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ -#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ -#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ -#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ -#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ -#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ -#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ -#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ -#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ -#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ -#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ -#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ -#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ -#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ -#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ -#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ -#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ -#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ -#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ -#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ -#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ -#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ -#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ -#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ -#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ -#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ -#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ -#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ -#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ -#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ -#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ -#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ -#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ -#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ -#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ -#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ -#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ -#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ -#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ -#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ -#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ -#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ -#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ -#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ -#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ -#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ -#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ -#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ -#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ -#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ -#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ -#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ -#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ -#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ -#define PRS_SYNC_CH_NUM 0x4UL /**> None */ -#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ -#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ -#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ -#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ -#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ -#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ -#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ -#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ -#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ -#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ -#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ -#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ -#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ -#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ -#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ -#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ -#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ -#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ -#define GPIO_PORT_A_WL 0x8UL /**> New Param */ -#define GPIO_PORT_A_WU 0x2UL /**> New Param */ -#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ -#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ -#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ -#define GPIO_PORT_B_WL 0x6UL /**> New Param */ -#define GPIO_PORT_B_WU 0x0UL /**> New Param */ -#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ -#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ -#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ -#define GPIO_PORT_C_WL 0x8UL /**> New Param */ -#define GPIO_PORT_C_WU 0x2UL /**> New Param */ -#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ -#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ -#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ -#define GPIO_PORT_D_WL 0x6UL /**> New Param */ -#define GPIO_PORT_D_WU 0x0UL /**> New Param */ -#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ -#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ -#define LDMA_CH_BITS 0x5UL /**> New Param */ -#define LDMA_CH_NUM 0x8UL /**> New Param */ -#define LDMA_FIFO_BITS 0x5UL /**> New Param */ -#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ -#define LDMAXBAR_CH_BITS 0x5UL /**> None */ -#define LDMAXBAR_CH_NUM 0x8UL /**> None */ -#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ -#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ -#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ -#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER0_NO_DTI 0x0UL /**> */ -#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ -#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER1_NO_DTI 0x0UL /**> */ -#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER2_NO_DTI 0x0UL /**> */ -#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER3_NO_DTI 0x0UL /**> */ -#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER4_NO_DTI 0x0UL /**> */ -#define USART0_AUTOTX_REG 0x1UL /**> None */ -#define USART0_AUTOTX_REG_B 0x0UL /**> None */ -#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ -#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ -#define USART0_CLK_PRS 0x1UL /**> None */ -#define USART0_CLK_PRS_B 0x0UL /**> New Param */ -#define USART0_FLOW_CONTROL 0x1UL /**> None */ -#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ -#define USART0_I2S 0x1UL /**> None */ -#define USART0_I2S_B 0x0UL /**> New Param */ -#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ -#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_MVDIS_FUNC 0x1UL /**> None */ -#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ -#define USART0_RX_PRS 0x1UL /**> None */ -#define USART0_RX_PRS_B 0x0UL /**> New Param */ -#define USART0_SC_AVAILABLE 0x1UL /**> None */ -#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ -#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ -#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ -#define USART0_TIMER 0x1UL /**> New Param */ -#define USART0_TIMER_B 0x0UL /**> New Param */ -#define BURTC_CNTWIDTH 0x20UL /**> None */ -#define BURTC_PRECNT_WIDTH 0xFUL /**> */ -#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ -#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ -#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ -#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ -#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ -#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ -#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ -#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ -#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ -#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ -#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ -#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ -#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ -#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ -#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ -#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ -#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ -#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ -#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ -#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ -#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ -#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ -#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ -#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ -#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ -#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ -#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ -#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ -#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ -#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ -#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ -#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ -#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ -#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ -#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ -#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ -#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ -#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ -#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ -#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ -#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ -#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ -#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ -#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ -#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ -#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ -#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ -#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ -#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ -#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ -#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ -#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ -#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ -#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ -#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ -#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ -#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ -#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ -#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ -#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ -#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ -#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ -#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ -#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ -#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ -#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ -#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ -#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ -#define ACMP0_DAC_INPUT 0x1UL /**> None */ -#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ -#define ACMP1_DAC_INPUT 0x1UL /**> None */ -#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ -#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ -#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ -#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ -#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ -#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ -#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ -#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ -#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ -#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ -#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ -#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ -#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ -#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ -#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ -#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ -#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ -#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ -#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ -#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ -#define WDOG0_PCNUM 0x2UL /**> None */ -#define WDOG1_PCNUM 0x2UL /**> None */ -#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ -#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ -#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ -#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ -#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ -#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ -#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ -#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ -#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ -#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ -#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ -#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ -#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ -#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ -#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ -#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ -#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ -#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ -#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ -#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ -#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ -#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ -#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ -#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ -#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ -#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ -#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ -#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ -#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ -#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ -#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ -#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ -#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ -#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ - -/* Instance macros for ACMP */ -#define ACMP(n) (((n) == 0) ? ACMP0 \ - : ((n) == 1) ? ACMP1 \ - : 0x0UL) -#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ - : ((ref) == ACMP1) ? 1 \ - : -1) -#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ - : ((n) == 1) ? ACMP1_DAC_INPUT \ - : 0x0UL) -#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ - : ((n) == 1) ? ACMP1_EXT_OVR_IF \ - : 0x0UL) - -/* Instance macros for EUSART */ -#define EUSART(n) (((n) == 0) ? EUSART0 \ - : ((n) == 1) ? EUSART1 \ - : 0x0UL) -#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ - : ((ref) == EUSART1) ? 1 \ - : -1) -#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_EM2_CAPABLE \ - : 0x0UL) -#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ - : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ - : 0x0UL) - -/* Instance macros for HFRCO */ -#define HFRCO(n) (((n) == 0) ? HFRCO0 \ - : ((n) == 1) ? HFRCOEM23 \ - : 0x0UL) -#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ - : ((ref) == HFRCOEM23) ? 1 \ - : -1) -#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ - : 0x0UL) -#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ - : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ - : 0x0UL) - -/* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) - -/* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) - -/* Instance macros for VDAC */ -#define VDAC(n) (((n) == 0) ? VDAC0 \ - : ((n) == 1) ? VDAC1 \ - : 0x0UL) -#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ - : ((ref) == VDAC1) ? 1 \ - : -1) -#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ - : ((n) == 1) ? VDAC1_ALT_WIDTH \ - : 0x0UL) -#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ - : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ - : 0x0UL) -#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ - : ((n) == 1) ? VDAC1_FIFO_DEPTH \ - : 0x0UL) -#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ - : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ - : 0x0UL) -#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ - : ((n) == 1) ? VDAC1_RESOLUTION \ - : 0x0UL) - -/* Instance macros for WDOG */ -#define WDOG(n) (((n) == 0) ? WDOG0 \ - : ((n) == 1) ? WDOG1 \ - : 0x0UL) -#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ - : ((ref) == WDOG1) ? 1 \ - : -1) -#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ - : ((n) == 1) ? WDOG1_PCNUM \ - : 0x0UL) - -/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Parameters */ - -/** @} End of group EFR32MG24B220F1536IM48 */ -/** @}} End of group Parts */ - -#ifdef __cplusplus -} -#endif -#endif +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32MG24B220F1536IM48 + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32MG24B220F1536IM48_H +#define EFR32MG24B220F1536IM48_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48 EFR32MG24B220F1536IM48 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32MG24 Peripheral Interrupt Numbers ******************************************/ + + SMU_SECURE_IRQn = 0, /*!< 0 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 1, /*!< 1 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 2, /*!< 2 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 3, /*!< 3 EFR32 EMU Interrupt */ + TIMER0_IRQn = 4, /*!< 4 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 5, /*!< 5 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 6, /*!< 6 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 7, /*!< 7 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 8, /*!< 8 EFR32 TIMER4 Interrupt */ + USART0_RX_IRQn = 9, /*!< 9 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 10, /*!< 10 EFR32 USART0_TX Interrupt */ + EUSART0_RX_IRQn = 11, /*!< 11 EFR32 EUSART0_RX Interrupt */ + EUSART0_TX_IRQn = 12, /*!< 12 EFR32 EUSART0_TX Interrupt */ + EUSART1_RX_IRQn = 13, /*!< 13 EFR32 EUSART1_RX Interrupt */ + EUSART1_TX_IRQn = 14, /*!< 14 EFR32 EUSART1_TX Interrupt */ + MVP_IRQn = 15, /*!< 15 EFR32 MVP Interrupt */ + ICACHE0_IRQn = 16, /*!< 16 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 17, /*!< 17 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 18, /*!< 18 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 19, /*!< 19 EFR32 SYSCFG Interrupt */ + MPAHBRAM_IRQn = 20, /*!< 20 EFR32 MPAHBRAM Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + AGC_IRQn = 30, /*!< 30 EFR32 AGC Interrupt */ + BUFC_IRQn = 31, /*!< 31 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 32, /*!< 32 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 33, /*!< 33 EFR32 FRC Interrupt */ + MODEM_IRQn = 34, /*!< 34 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 35, /*!< 35 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 36, /*!< 36 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 37, /*!< 37 EFR32 RAC_SEQ Interrupt */ + HOSTMAILBOX_IRQn = 38, /*!< 38 EFR32 HOSTMAILBOX Interrupt */ + SYNTH_IRQn = 39, /*!< 39 EFR32 SYNTH Interrupt */ + ACMP0_IRQn = 40, /*!< 40 EFR32 ACMP0 Interrupt */ + ACMP1_IRQn = 41, /*!< 41 EFR32 ACMP1 Interrupt */ + WDOG0_IRQn = 42, /*!< 42 EFR32 WDOG0 Interrupt */ + WDOG1_IRQn = 43, /*!< 43 EFR32 WDOG1 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + HFRCOEM23_IRQn = 46, /*!< 46 EFR32 HFRCOEM23 Interrupt */ + CMU_IRQn = 47, /*!< 47 EFR32 CMU Interrupt */ + AES_IRQn = 48, /*!< 48 EFR32 AES Interrupt */ + IADC_IRQn = 49, /*!< 49 EFR32 IADC Interrupt */ + MSC_IRQn = 50, /*!< 50 EFR32 MSC Interrupt */ + DPLL0_IRQn = 51, /*!< 51 EFR32 DPLL0 Interrupt */ + EMUEFP_IRQn = 52, /*!< 52 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 53, /*!< 53 EFR32 DCDC Interrupt */ + PCNT0_IRQn = 54, /*!< 54 EFR32 PCNT0 Interrupt */ + SW0_IRQn = 55, /*!< 55 EFR32 SW0 Interrupt */ + SW1_IRQn = 56, /*!< 56 EFR32 SW1 Interrupt */ + SW2_IRQn = 57, /*!< 57 EFR32 SW2 Interrupt */ + SW3_IRQn = 58, /*!< 58 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 59, /*!< 59 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 60, /*!< 60 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 61, /*!< 61 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 62, /*!< 62 EFR32 M33CTI1 Interrupt */ + FPUEXH_IRQn = 63, /*!< 63 EFR32 FPUEXH Interrupt */ + SETAMPERHOST_IRQn = 64, /*!< 64 EFR32 SETAMPERHOST Interrupt */ + SEMBRX_IRQn = 65, /*!< 65 EFR32 SEMBRX Interrupt */ + SEMBTX_IRQn = 66, /*!< 66 EFR32 SEMBTX Interrupt */ + SYSRTC_APP_IRQn = 67, /*!< 67 EFR32 SYSRTC_APP Interrupt */ + SYSRTC_SEQ_IRQn = 68, /*!< 68 EFR32 SYSRTC_SEQ Interrupt */ + KEYSCAN_IRQn = 69, /*!< 69 EFR32 KEYSCAN Interrupt */ + RFECA0_IRQn = 70, /*!< 70 EFR32 RFECA0 Interrupt */ + RFECA1_IRQn = 71, /*!< 71 EFR32 RFECA1 Interrupt */ + VDAC0_IRQn = 72, /*!< 72 EFR32 VDAC0 Interrupt */ + VDAC1_IRQn = 73, /*!< 73 EFR32 VDAC1 Interrupt */ + AHB2AHB0_IRQn = 74, /*!< 74 EFR32 AHB2AHB0 Interrupt */ + AHB2AHB1_IRQn = 75, /*!< 75 EFR32 AHB2AHB1 Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Core EFR32MG24B220F1536IM48 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32MG24B220F1536IM48_Core */ + +/**************************************************************************//** +* @defgroup EFR32MG24B220F1536IM48_Part EFR32MG24B220F1536IM48 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32MG24B220F1536IM48) +#define EFR32MG24B220F1536IM48 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32MG24B220F1536IM48" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_MIGHTY_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_MG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_4 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 4 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_215 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 20 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x08000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00180000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0817FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x15UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x08000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00180000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0817FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x15UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE08400UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE089FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00040000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x2003FFFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x13UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00040000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x13UL) /** RAM_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32MG24B220F1536IM48 */ +#define FLASH_BASE (0x08000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00180000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00040000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 76 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 10U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x03FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PA_PIN9 1U /**< GPIO pin PA9 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 6U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x003FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PB_PIN5 1U /**< GPIO pin PB5 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 10U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x03FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PC_PIN8 1U /**< GPIO pin PC8 is present. */ +#define GPIO_PC_PIN9 1U /**< GPIO pin PC9 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 6U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x003FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ +#define GPIO_PD_PIN4 1U /**< GPIO pin PD4 is present. */ +#define GPIO_PD_PIN5 1U /**< GPIO pin PD5 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_TRACEDATA1_PORT GPIO_PA_INDEX /**< Port of TRACEDATA1.*/ +#define GPIO_TRACEDATA1_PIN 5U /**< Pin of TRACEDATA1.*/ +#define GPIO_TRACEDATA2_PORT GPIO_PA_INDEX /**< Port of TRACEDATA2.*/ +#define GPIO_TRACEDATA2_PIN 6U /**< Pin of TRACEDATA2.*/ +#define GPIO_TRACEDATA3_PORT GPIO_PA_INDEX /**< Port of TRACEDATA3.*/ +#define GPIO_TRACEDATA3_PIN 7U /**< Pin of TRACEDATA3.*/ +#define GPIO_EFP_INT_PORT GPIO_PC_INDEX /**< Port of EFP_INT.*/ +#define GPIO_EFP_INT_PIN 5U /**< Pin of EFP_INT.*/ +#define GPIO_EFP_TX_SCL_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SCL_PIN 2U /**< Pin of EFP_TX_SCL.*/ +#define GPIO_EFP_TX_SDA_PORT GPIO_PC_INDEX /**< Port of EFP_TX_SDA.*/ +#define GPIO_EFP_TX_SDA_PIN 1U /**< Pin of EFP_TX_SDA.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU10_PORT GPIO_PD_INDEX /**< Port of EM4WU10.*/ +#define GPIO_EM4WU10_PIN 5U /**< Pin of EM4WU10.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 9U /**< Pin of THMSW_EN.*/ +#define GPIO_THMSW_HALFSWITCH_PORT GPIO_PC_INDEX /**< Port of THMSW_HALFSWITCH.*/ +#define GPIO_THMSW_HALFSWITCH_PIN 9U /**< Pin of THMSW_HALFSWITCH.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ +#define VDAC0_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC0_CH0_MAIN_OUT_PIN 0U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC0_CH1_MAIN_OUT_PIN 1U /**< Pin of CH1_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH0_MAIN_OUT.*/ +#define VDAC1_CH0_MAIN_OUT_PIN 2U /**< Pin of CH0_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PORT GPIO_PB_INDEX /**< Port of CH1_MAIN_OUT.*/ +#define VDAC1_CH1_MAIN_OUT_PIN 3U /**< Pin of CH1_MAIN_OUT.*/ + +/* Part number capabilities */ +#define ACMP_PRESENT /** ACMP is available in this part */ +#define ACMP_COUNT 2 /** 2 ACMPs available */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DMEM_PRESENT /** DMEM is available in this part */ +#define DMEM_COUNT 1 /** 1 DMEMs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUSART_PRESENT /** EUSART is available in this part */ +#define EUSART_COUNT 2 /** 2 EUSARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFRCOEM23_PRESENT /** HFRCOEM23 is available in this part */ +#define HFRCOEM23_COUNT 1 /** 1 HFRCOEM23s available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define HOSTMAILBOX_PRESENT /** HOSTMAILBOX is available in this part */ +#define HOSTMAILBOX_COUNT 1 /** 1 HOSTMAILBOXs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define KEYSCAN_PRESENT /** KEYSCAN is available in this part */ +#define KEYSCAN_COUNT 1 /** 1 KEYSCANs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define MVP_PRESENT /** MVP is available in this part */ +#define MVP_COUNT 1 /** 1 MVPs available */ +#define PCNT_PRESENT /** PCNT is available in this part */ +#define PCNT_COUNT 1 /** 1 PCNTs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define SCRATCHPAD_PRESENT /** SCRATCHPAD is available in this part */ +#define SCRATCHPAD_COUNT 1 /** 1 SCRATCHPADs available */ +#define SEMAILBOX_PRESENT /** SEMAILBOX is available in this part */ +#define SEMAILBOX_COUNT 1 /** 1 SEMAILBOXs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define SYSRTC_PRESENT /** SYSRTC is available in this part */ +#define SYSRTC_COUNT 1 /** 1 SYSRTCs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 1 /** 1 USARTs available */ +#define VDAC_PRESENT /** VDAC is available in this part */ +#define VDAC_COUNT 2 /** 2 VDACs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 2 /** 2 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32mg24.h" /* System Header File */ + +/** @} End of group EFR32MG24B220F1536IM48_Part */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_TypeDefs EFR32MG24B220F1536IM48 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32mg24_scratchpad.h" +#include "efr32mg24_emu.h" +#include "efr32mg24_cmu.h" +#include "efr32mg24_hfrco.h" +#include "efr32mg24_fsrco.h" +#include "efr32mg24_dpll.h" +#include "efr32mg24_lfxo.h" +#include "efr32mg24_lfrco.h" +#include "efr32mg24_ulfrco.h" +#include "efr32mg24_msc.h" +#include "efr32mg24_icache.h" +#include "efr32mg24_prs.h" +#include "efr32mg24_gpio.h" +#include "efr32mg24_ldma.h" +#include "efr32mg24_ldmaxbar.h" +#include "efr32mg24_timer.h" +#include "efr32mg24_usart.h" +#include "efr32mg24_burtc.h" +#include "efr32mg24_i2c.h" +#include "efr32mg24_syscfg.h" +#include "efr32mg24_buram.h" +#include "efr32mg24_gpcrc.h" +#include "efr32mg24_dcdc.h" +#include "efr32mg24_mailbox.h" +#include "efr32mg24_eusart.h" +#include "efr32mg24_sysrtc.h" +#include "efr32mg24_keyscan.h" +#include "efr32mg24_mpahbram.h" +#include "efr32mg24_aes.h" +#include "efr32mg24_smu.h" +#include "efr32mg24_letimer.h" +#include "efr32mg24_iadc.h" +#include "efr32mg24_acmp.h" +#include "efr32mg24_vdac.h" +#include "efr32mg24_pcnt.h" +#include "efr32mg24_hfxo.h" +#include "efr32mg24_wdog.h" +#include "efr32mg24_semailbox.h" +#include "efr32mg24_mvp.h" +#include "efr32mg24_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32mg24_prs_signals.h" +#include "efr32mg24_dma_descriptor.h" +#include "efr32mg24_ldmaxbar_defines.h" + +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Base EFR32MG24B220F1536IM48 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S_BASE (0x40000000UL) /* SCRATCHPAD_S base address */ +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define HOSTMAILBOX_S_BASE (0x40098000UL) /* HOSTMAILBOX_S base address */ +#define EUSART1_S_BASE (0x400A0000UL) /* EUSART1_S base address */ +#define SYSRTC0_S_BASE (0x400A8000UL) /* SYSRTC0_S base address */ +#define KEYSCAN_S_BASE (0x400B0000UL) /* KEYSCAN_S base address */ +#define DMEM_S_BASE (0x400B4000UL) /* DMEM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define LETIMER0_S_BASE (0x49000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x49004000UL) /* IADC0_S base address */ +#define ACMP0_S_BASE (0x49008000UL) /* ACMP0_S base address */ +#define ACMP1_S_BASE (0x4900C000UL) /* ACMP1_S base address */ +#define VDAC0_S_BASE (0x49024000UL) /* VDAC0_S base address */ +#define VDAC1_S_BASE (0x49028000UL) /* VDAC1_S base address */ +#define PCNT0_S_BASE (0x49030000UL) /* PCNT0_S base address */ +#define HFRCOEM23_S_BASE (0x4A000000UL) /* HFRCOEM23_S base address */ +#define HFXO0_S_BASE (0x4A004000UL) /* HFXO0_S base address */ +#define I2C0_S_BASE (0x4B000000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4B004000UL) /* WDOG0_S base address */ +#define WDOG1_S_BASE (0x4B008000UL) /* WDOG1_S base address */ +#define EUSART0_S_BASE (0x4B010000UL) /* EUSART0_S base address */ +#define SEMAILBOX_S_HOST_BASE (0x4C000000UL) /* SEMAILBOX_S_HOST base address */ +#define MVP_S_BASE (0x4D000000UL) /* MVP_S base address */ +#define SCRATCHPAD_NS_BASE (0x50000000UL) /* SCRATCHPAD_NS base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define HOSTMAILBOX_NS_BASE (0x50098000UL) /* HOSTMAILBOX_NS base address */ +#define EUSART1_NS_BASE (0x500A0000UL) /* EUSART1_NS base address */ +#define SYSRTC0_NS_BASE (0x500A8000UL) /* SYSRTC0_NS base address */ +#define KEYSCAN_NS_BASE (0x500B0000UL) /* KEYSCAN_NS base address */ +#define DMEM_NS_BASE (0x500B4000UL) /* DMEM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define LETIMER0_NS_BASE (0x59000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x59004000UL) /* IADC0_NS base address */ +#define ACMP0_NS_BASE (0x59008000UL) /* ACMP0_NS base address */ +#define ACMP1_NS_BASE (0x5900C000UL) /* ACMP1_NS base address */ +#define VDAC0_NS_BASE (0x59024000UL) /* VDAC0_NS base address */ +#define VDAC1_NS_BASE (0x59028000UL) /* VDAC1_NS base address */ +#define PCNT0_NS_BASE (0x59030000UL) /* PCNT0_NS base address */ +#define HFRCOEM23_NS_BASE (0x5A000000UL) /* HFRCOEM23_NS base address */ +#define HFXO0_NS_BASE (0x5A004000UL) /* HFXO0_NS base address */ +#define I2C0_NS_BASE (0x5B000000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5B004000UL) /* WDOG0_NS base address */ +#define WDOG1_NS_BASE (0x5B008000UL) /* WDOG1_NS base address */ +#define EUSART0_NS_BASE (0x5B010000UL) /* EUSART0_NS base address */ +#define SEMAILBOX_NS_HOST_BASE (0x5C000000UL) /* SEMAILBOX_NS_HOST base address */ +#define MVP_NS_BASE (0x5D000000UL) /* MVP_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S) && (SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S != 0))) +#define SCRATCHPAD_BASE (SCRATCHPAD_S_BASE) /* SCRATCHPAD base address */ +#else +#define SCRATCHPAD_BASE (SCRATCHPAD_NS_BASE) /* SCRATCHPAD base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SCRATCHPAD_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S) && (SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S != 0))) +#define HOSTMAILBOX_BASE (HOSTMAILBOX_S_BASE) /* HOSTMAILBOX base address */ +#else +#define HOSTMAILBOX_BASE (HOSTMAILBOX_NS_BASE) /* HOSTMAILBOX base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HOSTMAILBOX_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART1_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART1_S != 0))) +#define EUSART1_BASE (EUSART1_S_BASE) /* EUSART1 base address */ +#else +#define EUSART1_BASE (EUSART1_NS_BASE) /* EUSART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S) && (SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S != 0))) +#define SYSRTC0_BASE (SYSRTC0_S_BASE) /* SYSRTC0 base address */ +#else +#define SYSRTC0_BASE (SYSRTC0_NS_BASE) /* SYSRTC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSRTC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S) && (SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S != 0))) +#define KEYSCAN_BASE (KEYSCAN_S_BASE) /* KEYSCAN base address */ +#else +#define KEYSCAN_BASE (KEYSCAN_NS_BASE) /* KEYSCAN base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_KEYSCAN_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DMEM_S) && (SL_TRUSTZONE_PERIPHERAL_DMEM_S != 0))) +#define DMEM_BASE (DMEM_S_BASE) /* DMEM base address */ +#else +#define DMEM_BASE (DMEM_NS_BASE) /* DMEM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DMEM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP0_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP0_S != 0))) +#define ACMP0_BASE (ACMP0_S_BASE) /* ACMP0 base address */ +#else +#define ACMP0_BASE (ACMP0_NS_BASE) /* ACMP0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ACMP1_S) && (SL_TRUSTZONE_PERIPHERAL_ACMP1_S != 0))) +#define ACMP1_BASE (ACMP1_S_BASE) /* ACMP1 base address */ +#else +#define ACMP1_BASE (ACMP1_NS_BASE) /* ACMP1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ACMP1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC0_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC0_S != 0))) +#define VDAC0_BASE (VDAC0_S_BASE) /* VDAC0 base address */ +#else +#define VDAC0_BASE (VDAC0_NS_BASE) /* VDAC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_VDAC1_S) && (SL_TRUSTZONE_PERIPHERAL_VDAC1_S != 0))) +#define VDAC1_BASE (VDAC1_S_BASE) /* VDAC1 base address */ +#else +#define VDAC1_BASE (VDAC1_NS_BASE) /* VDAC1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_VDAC1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PCNT0_S) && (SL_TRUSTZONE_PERIPHERAL_PCNT0_S != 0))) +#define PCNT0_BASE (PCNT0_S_BASE) /* PCNT0 base address */ +#else +#define PCNT0_BASE (PCNT0_NS_BASE) /* PCNT0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PCNT0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S != 0))) +#define HFRCOEM23_BASE (HFRCOEM23_S_BASE) /* HFRCOEM23 base address */ +#else +#define HFRCOEM23_BASE (HFRCOEM23_NS_BASE) /* HFRCOEM23 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCOEM23_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG1_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG1_S != 0))) +#define WDOG1_BASE (WDOG1_S_BASE) /* WDOG1 base address */ +#else +#define WDOG1_BASE (WDOG1_NS_BASE) /* WDOG1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUSART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUSART0_S != 0))) +#define EUSART0_BASE (EUSART0_S_BASE) /* EUSART0 base address */ +#else +#define EUSART0_BASE (EUSART0_NS_BASE) /* EUSART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUSART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S) && (SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S != 0))) +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#else +#define SEMAILBOX_HOST_BASE (SEMAILBOX_S_HOST_BASE) /* SEMAILBOX_HOST base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SEMAILBOX_HOST_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MVP_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MVP_S) && (SL_TRUSTZONE_PERIPHERAL_MVP_S != 0))) +#define MVP_BASE (MVP_S_BASE) /* MVP base address */ +#else +#define MVP_BASE (MVP_NS_BASE) /* MVP base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MVP_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Declaration EFR32MG24B220F1536IM48 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define SCRATCHPAD_S ((SCRATCHPAD_TypeDef *) SCRATCHPAD_S_BASE) /**< SCRATCHPAD_S base pointer */ +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define HOSTMAILBOX_S ((MAILBOX_TypeDef *) HOSTMAILBOX_S_BASE) /**< HOSTMAILBOX_S base pointer */ +#define EUSART1_S ((EUSART_TypeDef *) EUSART1_S_BASE) /**< EUSART1_S base pointer */ +#define SYSRTC0_S ((SYSRTC_TypeDef *) SYSRTC0_S_BASE) /**< SYSRTC0_S base pointer */ +#define KEYSCAN_S ((KEYSCAN_TypeDef *) KEYSCAN_S_BASE) /**< KEYSCAN_S base pointer */ +#define DMEM_S ((MPAHBRAM_TypeDef *) DMEM_S_BASE) /**< DMEM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define ACMP0_S ((ACMP_TypeDef *) ACMP0_S_BASE) /**< ACMP0_S base pointer */ +#define ACMP1_S ((ACMP_TypeDef *) ACMP1_S_BASE) /**< ACMP1_S base pointer */ +#define VDAC0_S ((VDAC_TypeDef *) VDAC0_S_BASE) /**< VDAC0_S base pointer */ +#define VDAC1_S ((VDAC_TypeDef *) VDAC1_S_BASE) /**< VDAC1_S base pointer */ +#define PCNT0_S ((PCNT_TypeDef *) PCNT0_S_BASE) /**< PCNT0_S base pointer */ +#define HFRCOEM23_S ((HFRCO_TypeDef *) HFRCOEM23_S_BASE) /**< HFRCOEM23_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define WDOG1_S ((WDOG_TypeDef *) WDOG1_S_BASE) /**< WDOG1_S base pointer */ +#define EUSART0_S ((EUSART_TypeDef *) EUSART0_S_BASE) /**< EUSART0_S base pointer */ +#define SEMAILBOX_S_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_S_HOST_BASE) /**< SEMAILBOX_S_HOST base pointer */ +#define MVP_S ((MVP_TypeDef *) MVP_S_BASE) /**< MVP_S base pointer */ +#define SCRATCHPAD_NS ((SCRATCHPAD_TypeDef *) SCRATCHPAD_NS_BASE) /**< SCRATCHPAD_NS base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define HOSTMAILBOX_NS ((MAILBOX_TypeDef *) HOSTMAILBOX_NS_BASE) /**< HOSTMAILBOX_NS base pointer */ +#define EUSART1_NS ((EUSART_TypeDef *) EUSART1_NS_BASE) /**< EUSART1_NS base pointer */ +#define SYSRTC0_NS ((SYSRTC_TypeDef *) SYSRTC0_NS_BASE) /**< SYSRTC0_NS base pointer */ +#define KEYSCAN_NS ((KEYSCAN_TypeDef *) KEYSCAN_NS_BASE) /**< KEYSCAN_NS base pointer */ +#define DMEM_NS ((MPAHBRAM_TypeDef *) DMEM_NS_BASE) /**< DMEM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define ACMP0_NS ((ACMP_TypeDef *) ACMP0_NS_BASE) /**< ACMP0_NS base pointer */ +#define ACMP1_NS ((ACMP_TypeDef *) ACMP1_NS_BASE) /**< ACMP1_NS base pointer */ +#define VDAC0_NS ((VDAC_TypeDef *) VDAC0_NS_BASE) /**< VDAC0_NS base pointer */ +#define VDAC1_NS ((VDAC_TypeDef *) VDAC1_NS_BASE) /**< VDAC1_NS base pointer */ +#define PCNT0_NS ((PCNT_TypeDef *) PCNT0_NS_BASE) /**< PCNT0_NS base pointer */ +#define HFRCOEM23_NS ((HFRCO_TypeDef *) HFRCOEM23_NS_BASE) /**< HFRCOEM23_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define WDOG1_NS ((WDOG_TypeDef *) WDOG1_NS_BASE) /**< WDOG1_NS base pointer */ +#define EUSART0_NS ((EUSART_TypeDef *) EUSART0_NS_BASE) /**< EUSART0_NS base pointer */ +#define SEMAILBOX_NS_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_NS_HOST_BASE) /**< SEMAILBOX_NS_HOST base pointer */ +#define MVP_NS ((MVP_TypeDef *) MVP_NS_BASE) /**< MVP_NS base pointer */ +#define SCRATCHPAD ((SCRATCHPAD_TypeDef *) SCRATCHPAD_BASE) /**< SCRATCHPAD base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define HOSTMAILBOX ((MAILBOX_TypeDef *) HOSTMAILBOX_BASE) /**< HOSTMAILBOX base pointer */ +#define EUSART1 ((EUSART_TypeDef *) EUSART1_BASE) /**< EUSART1 base pointer */ +#define SYSRTC0 ((SYSRTC_TypeDef *) SYSRTC0_BASE) /**< SYSRTC0 base pointer */ +#define KEYSCAN ((KEYSCAN_TypeDef *) KEYSCAN_BASE) /**< KEYSCAN base pointer */ +#define DMEM ((MPAHBRAM_TypeDef *) DMEM_BASE) /**< DMEM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */ +#define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */ +#define VDAC0 ((VDAC_TypeDef *) VDAC0_BASE) /**< VDAC0 base pointer */ +#define VDAC1 ((VDAC_TypeDef *) VDAC1_BASE) /**< VDAC1 base pointer */ +#define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */ +#define HFRCOEM23 ((HFRCO_TypeDef *) HFRCOEM23_BASE) /**< HFRCOEM23 base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define WDOG1 ((WDOG_TypeDef *) WDOG1_BASE) /**< WDOG1 base pointer */ +#define EUSART0 ((EUSART_TypeDef *) EUSART0_BASE) /**< EUSART0 base pointer */ +#define SEMAILBOX_HOST ((SEMAILBOX_HOST_TypeDef *) SEMAILBOX_HOST_BASE) /**< SEMAILBOX_HOST base pointer */ +#define MVP ((MVP_TypeDef *) MVP_BASE) /**< MVP base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32MG24B220F1536IM48_Peripheral_Parameters EFR32MG24B220F1536IM48 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x0UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x15UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x15UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0x2UL /**> None */ +#define MSC_FLASH_BLOCK_MAIN_PCOUNT 0xD0UL /**> */ +#define MSC_INFOADDRBITS 0xEUL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0xEUL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xDUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xDUL /**> None */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_ROOTMAIN_PRESENT 0x1UL /**> */ +#define MSC_UD_PRESENT 0x1UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define DMEM_AHB_DATA_WIDTH 0x20UL /**> Data width of the AHB interface */ +#define DMEM_BANK0_SIZE 0x4000UL /**> Bank0 size */ +#define DMEM_BANK10_SIZE 0x4000UL /**> Bank10 size */ +#define DMEM_BANK11_SIZE 0x4000UL /**> Bank11 size */ +#define DMEM_BANK12_SIZE 0x4000UL /**> Bank12 size */ +#define DMEM_BANK13_SIZE 0x4000UL /**> Bank13 size */ +#define DMEM_BANK14_SIZE 0x4000UL /**> Bank14 size */ +#define DMEM_BANK15_SIZE 0x4000UL /**> Bank15 size */ +#define DMEM_BANK16_SIZE 0x0UL /**> Bank16 size */ +#define DMEM_BANK17_SIZE 0x0UL /**> Bank17 size */ +#define DMEM_BANK18_SIZE 0x0UL /**> Bank18 size */ +#define DMEM_BANK19_SIZE 0x0UL /**> Bank19 size */ +#define DMEM_BANK1_SIZE 0x4000UL /**> Bank1 size */ +#define DMEM_BANK20_SIZE 0x0UL /**> Bank20 size */ +#define DMEM_BANK21_SIZE 0x0UL /**> Bank21 size */ +#define DMEM_BANK22_SIZE 0x0UL /**> Bank22 size */ +#define DMEM_BANK23_SIZE 0x0UL /**> Bank23 size */ +#define DMEM_BANK24_SIZE 0x0UL /**> Bank24 size */ +#define DMEM_BANK25_SIZE 0x0UL /**> Bank25 size */ +#define DMEM_BANK26_SIZE 0x0UL /**> Bank26 size */ +#define DMEM_BANK27_SIZE 0x0UL /**> Bank27 size */ +#define DMEM_BANK28_SIZE 0x0UL /**> Bank28 size */ +#define DMEM_BANK29_SIZE 0x0UL /**> Bank29 size */ +#define DMEM_BANK2_SIZE 0x4000UL /**> Bank2 size */ +#define DMEM_BANK30_SIZE 0x0UL /**> Bank30 size */ +#define DMEM_BANK31_SIZE 0x0UL /**> Bank31 size */ +#define DMEM_BANK3_SIZE 0x4000UL /**> Bank3 size */ +#define DMEM_BANK4_SIZE 0x4000UL /**> Bank4 size */ +#define DMEM_BANK5_SIZE 0x4000UL /**> Bank5 size */ +#define DMEM_BANK6_SIZE 0x4000UL /**> Bank6 size */ +#define DMEM_BANK7_SIZE 0x4000UL /**> Bank7 size */ +#define DMEM_BANK8_SIZE 0x4000UL /**> Bank8 size */ +#define DMEM_BANK9_SIZE 0x4000UL /**> Bank9 size */ +#define DMEM_ECC_EXCLUDE 0x0UL /**> ECC exclude */ +#define DMEM_MEM_SIZE 0x40000UL /**> Total memory size */ +#define DMEM_NUM_BANKS 0x10UL /**> Number of physical SRAM banks */ +#define DMEM_NUM_PORTS 0x4UL /**> Number of AHB slave ports */ +#define DMEM_NUM_PORTS_IS_2 0x0UL /**> Boolean indicating if NUM_PORTS=2 */ +#define DMEM_WAITSTATE_EXCLUDE 0x0UL /**> Waitstate exclude */ +#define CMU_EXCLUDELCD 0x1UL /**> Exclude LCD */ +#define CMU_EXCLUDELESENSE 0x1UL /**> Exclude LESENSE */ +#define HFRCO0_EM23ONDEMAND 0x0UL /**> EM23 On Demand */ +#define HFRCO0_EXCLUDEEM23ONDEMAND 0x1UL /**> Exclude EM23 On Demand */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x180000UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x8000000UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x0UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x180000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x8000000UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x7UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0x10UL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x5UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x3UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x5UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x3UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x5UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x3UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0xAUL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x2UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x6UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x6UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0xAUL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x2UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x6UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x6UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x3CUL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x2UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define HOSTMAILBOX_NUM_MSGPTRS 0x4UL /**> */ +#define EUSART1_EM2_CAPABLE 0x0UL /**> EM2 Capable instance */ +#define EUSART1_NOT_EM2_CAPABLE 0x1UL /**> Not EM2 Capable instance */ +#define SYSRTC0_GROUP0_ALTIRQDIS 0x1UL /**> Group 0 Alternate IRQ disable */ +#define SYSRTC0_GROUP0_CAPDIS 0x0UL /**> Group 0 Capture disable */ +#define SYSRTC0_GROUP0_CMP1DIS 0x0UL /**> Group 0 Compare1 disable */ +#define SYSRTC0_GROUP0_DIS 0x0UL /**> Group 0 Disable */ +#define SYSRTC0_GROUP0_ROOTDIS 0x1UL /**> Group 0 ROOT disable */ +#define SYSRTC0_GROUP1_ALTIRQDIS 0x0UL /**> Group 1 Alternate IRQ disable */ +#define SYSRTC0_GROUP1_CAPDIS 0x0UL /**> Group 1 Capture disable */ +#define SYSRTC0_GROUP1_CMP1DIS 0x0UL /**> Group 1 Compare1 disable */ +#define SYSRTC0_GROUP1_DIS 0x0UL /**> Group 1 Disable */ +#define SYSRTC0_GROUP1_ROOTDIS 0x1UL /**> Group 1 ROOT disable */ +#define SYSRTC0_GROUP2_ALTIRQDIS 0x1UL /**> Group 2 Alternate IRQ disable */ +#define SYSRTC0_GROUP2_CAPDIS 0x1UL /**> Group 2 Capture disable */ +#define SYSRTC0_GROUP2_CMP1DIS 0x1UL /**> Group 2 Compare1 disable */ +#define SYSRTC0_GROUP2_DIS 0x0UL /**> Group 2 Disable */ +#define SYSRTC0_GROUP2_ROOTDIS 0x0UL /**> Group 2 ROOT disable */ +#define SYSRTC0_GROUP3_ALTIRQDIS 0x1UL /**> Group 3 Alternate IRQ disable */ +#define SYSRTC0_GROUP3_CAPDIS 0x1UL /**> Group 3 Capture disable */ +#define SYSRTC0_GROUP3_CMP1DIS 0x1UL /**> Group 3 Compare1 disable */ +#define SYSRTC0_GROUP3_DIS 0x1UL /**> Group 3 Disable */ +#define SYSRTC0_GROUP3_ROOTDIS 0x1UL /**> Group 3 ROOT disable */ +#define SYSRTC0_GROUP4_ALTIRQDIS 0x1UL /**> Group 4 Alternate IRQ disable */ +#define SYSRTC0_GROUP4_CAPDIS 0x1UL /**> Group 4 Capture disable */ +#define SYSRTC0_GROUP4_CMP1DIS 0x1UL /**> Group 4 Compare1 disable */ +#define SYSRTC0_GROUP4_DIS 0x1UL /**> Group 4 Disable */ +#define SYSRTC0_GROUP4_ROOTDIS 0x1UL /**> Group 4 ROOT disable */ +#define SYSRTC0_GROUP5_ALTIRQDIS 0x1UL /**> Group 5 Alternate IRQ disable */ +#define SYSRTC0_GROUP5_CAPDIS 0x1UL /**> Group 5 Capture disable */ +#define SYSRTC0_GROUP5_CMP1DIS 0x1UL /**> Group 5 Compare1 disable */ +#define SYSRTC0_GROUP5_DIS 0x1UL /**> Group 5 Disable */ +#define SYSRTC0_GROUP5_ROOTDIS 0x1UL /**> Group 5 ROOT disable */ +#define SYSRTC0_GROUP6_ALTIRQDIS 0x1UL /**> Group 6 Alternate IRQ disable */ +#define SYSRTC0_GROUP6_CAPDIS 0x1UL /**> Group 6 Capture disable */ +#define SYSRTC0_GROUP6_CMP1DIS 0x1UL /**> Group 6 Compare1 disable */ +#define SYSRTC0_GROUP6_DIS 0x1UL /**> Group 6 Disable */ +#define SYSRTC0_GROUP6_ROOTDIS 0x1UL /**> Group 6 ROOT disable */ +#define SYSRTC0_GROUP7_ALTIRQDIS 0x1UL /**> Group 7 Alternate IRQ disable */ +#define SYSRTC0_GROUP7_CAPDIS 0x1UL /**> Group 7 Capture disable */ +#define SYSRTC0_GROUP7_CMP1DIS 0x1UL /**> Group 7 Compare1 disable */ +#define SYSRTC0_GROUP7_DIS 0x1UL /**> Group 7 Disable */ +#define SYSRTC0_GROUP7_ROOTDIS 0x1UL /**> Group 7 ROOT disable */ +#define SYSRTC0_ROOTDIS 0x0UL /**> ROOT disable */ +#define KEYSCAN_COLNUM 0x8UL /**> COLNUM */ +#define KEYSCAN_COLWIDTH 0x3UL /**> COLWIDTH */ +#define KEYSCAN_ROWNUM 0x6UL /**> ROWNUM */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x1UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x9UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x36UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x16UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x16UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define ACMP0_DAC_INPUT 0x1UL /**> None */ +#define ACMP0_EXT_OVR_IF 0x1UL /**> None */ +#define ACMP1_DAC_INPUT 0x1UL /**> None */ +#define ACMP1_EXT_OVR_IF 0x1UL /**> None */ +#define VDAC0_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC0_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC0_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC0_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC0_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC0_RESOLUTION 0xCUL /**> DAC Resolution */ +#define VDAC1_ALT_WIDTH 0x6UL /**> VOUT_AUX Out Width */ +#define VDAC1_CH0_TRIG_LESENSE 0x0UL /**> CH0 Trig Source = LESENSE */ +#define VDAC1_CH1_TRIG_LESENSE 0x0UL /**> CH1 Trig Source = LESENSE */ +#define VDAC1_FIFO_DEPTH 0x4UL /**> WFIFO Depth */ +#define VDAC1_INT_PRESC_WIDTH 0x7UL /**> Internal Prescaler Width */ +#define VDAC1_RESOLUTION 0xCUL /**> DAC Resolution */ +#define PCNT0_PCNT_WIDTH 0x10UL /**> None */ +#define HFRCOEM23_EM23ONDEMAND 0x1UL /**> EM23 On Demand */ +#define HFRCOEM23_EXCLUDEEM23ONDEMAND 0x0UL /**> Exclude EM23 On Demand */ +#define HFXO0_BUFOUT 0x1UL /**> BUFOUT */ +#define HFXO0_EXCLUDEBUFOUT 0x0UL /**> Exclude BUFOUT */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define WDOG1_PCNUM 0x2UL /**> None */ +#define EUSART0_EM2_CAPABLE 0x1UL /**> EM2 Capable instance */ +#define EUSART0_NOT_EM2_CAPABLE 0x0UL /**> Not EM2 Capable instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ + +/* Instance macros for ACMP */ +#define ACMP(n) (((n) == 0) ? ACMP0 \ + : ((n) == 1) ? ACMP1 \ + : 0x0UL) +#define ACMP_NUM(ref) (((ref) == ACMP0) ? 0 \ + : ((ref) == ACMP1) ? 1 \ + : -1) +#define ACMP_DAC_INPUT(n) (((n) == 0) ? ACMP0_DAC_INPUT \ + : ((n) == 1) ? ACMP1_DAC_INPUT \ + : 0x0UL) +#define ACMP_EXT_OVR_IF(n) (((n) == 0) ? ACMP0_EXT_OVR_IF \ + : ((n) == 1) ? ACMP1_EXT_OVR_IF \ + : 0x0UL) + +/* Instance macros for EUSART */ +#define EUSART(n) (((n) == 0) ? EUSART0 \ + : ((n) == 1) ? EUSART1 \ + : 0x0UL) +#define EUSART_NUM(ref) (((ref) == EUSART0) ? 0 \ + : ((ref) == EUSART1) ? 1 \ + : -1) +#define EUSART_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_EM2_CAPABLE \ + : 0x0UL) +#define EUSART_NOT_EM2_CAPABLE(n) (((n) == 0) ? EUSART0_NOT_EM2_CAPABLE \ + : ((n) == 1) ? EUSART1_NOT_EM2_CAPABLE \ + : 0x0UL) + +/* Instance macros for HFRCO */ +#define HFRCO(n) (((n) == 0) ? HFRCO0 \ + : ((n) == 1) ? HFRCOEM23 \ + : 0x0UL) +#define HFRCO_NUM(ref) (((ref) == HFRCO0) ? 0 \ + : ((ref) == HFRCOEM23) ? 1 \ + : -1) +#define HFRCO_EM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EM23ONDEMAND \ + : 0x0UL) +#define HFRCO_EXCLUDEEM23ONDEMAND(n) (((n) == 0) ? HFRCO0_EXCLUDEEM23ONDEMAND \ + : ((n) == 1) ? HFRCOEM23_EXCLUDEEM23ONDEMAND \ + : 0x0UL) + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for VDAC */ +#define VDAC(n) (((n) == 0) ? VDAC0 \ + : ((n) == 1) ? VDAC1 \ + : 0x0UL) +#define VDAC_NUM(ref) (((ref) == VDAC0) ? 0 \ + : ((ref) == VDAC1) ? 1 \ + : -1) +#define VDAC_ALT_WIDTH(n) (((n) == 0) ? VDAC0_ALT_WIDTH \ + : ((n) == 1) ? VDAC1_ALT_WIDTH \ + : 0x0UL) +#define VDAC_CH0_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH0_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH0_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_CH1_TRIG_LESENSE(n) (((n) == 0) ? VDAC0_CH1_TRIG_LESENSE \ + : ((n) == 1) ? VDAC1_CH1_TRIG_LESENSE \ + : 0x0UL) +#define VDAC_FIFO_DEPTH(n) (((n) == 0) ? VDAC0_FIFO_DEPTH \ + : ((n) == 1) ? VDAC1_FIFO_DEPTH \ + : 0x0UL) +#define VDAC_INT_PRESC_WIDTH(n) (((n) == 0) ? VDAC0_INT_PRESC_WIDTH \ + : ((n) == 1) ? VDAC1_INT_PRESC_WIDTH \ + : 0x0UL) +#define VDAC_RESOLUTION(n) (((n) == 0) ? VDAC0_RESOLUTION \ + : ((n) == 1) ? VDAC1_RESOLUTION \ + : 0x0UL) + +/* Instance macros for WDOG */ +#define WDOG(n) (((n) == 0) ? WDOG0 \ + : ((n) == 1) ? WDOG1 \ + : 0x0UL) +#define WDOG_NUM(ref) (((ref) == WDOG0) ? 0 \ + : ((ref) == WDOG1) ? 1 \ + : -1) +#define WDOG_PCNUM(n) (((n) == 0) ? WDOG0_PCNUM \ + : ((n) == 1) ? WDOG1_PCNUM \ + : 0x0UL) + +/** @} End of group EFR32MG24B220F1536IM48_Peripheral_Parameters */ + +/** @} End of group EFR32MG24B220F1536IM48 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h index 33f7652..0d7a562 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/em_device.h @@ -1,178 +1,178 @@ -/**************************************************************************//** - * @file - * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories - * microcontroller devices - * - * This is a convenience header file for defining the part number on the - * build command line, instead of specifying the part specific header file. - * - * @verbatim - * Example: Add "-DEFM32G890F128" to your build options, to define part - * Add "#include "em_device.h" to your source files - - * - * @endverbatim - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#ifndef EM_DEVICE_H -#define EM_DEVICE_H -#if defined(EFR32MG24A010F1024IM40) -#include "efr32mg24a010f1024im40.h" - -#elif defined(EFR32MG24A010F1024IM48) -#include "efr32mg24a010f1024im48.h" - -#elif defined(EFR32MG24A010F1536GM40) -#include "efr32mg24a010f1536gm40.h" - -#elif defined(EFR32MG24A010F1536GM48) -#include "efr32mg24a010f1536gm48.h" - -#elif defined(EFR32MG24A010F1536IM40) -#include "efr32mg24a010f1536im40.h" - -#elif defined(EFR32MG24A010F1536IM48) -#include "efr32mg24a010f1536im48.h" - -#elif defined(EFR32MG24A010F768IM40) -#include "efr32mg24a010f768im40.h" - -#elif defined(EFR32MG24A010F768IM48) -#include "efr32mg24a010f768im48.h" - -#elif defined(EFR32MG24A020F1024IM40) -#include "efr32mg24a020f1024im40.h" - -#elif defined(EFR32MG24A020F1024IM48) -#include "efr32mg24a020f1024im48.h" - -#elif defined(EFR32MG24A020F1536GM40) -#include "efr32mg24a020f1536gm40.h" - -#elif defined(EFR32MG24A020F1536GM48) -#include "efr32mg24a020f1536gm48.h" - -#elif defined(EFR32MG24A020F1536IM40) -#include "efr32mg24a020f1536im40.h" - -#elif defined(EFR32MG24A020F1536IM48) -#include "efr32mg24a020f1536im48.h" - -#elif defined(EFR32MG24A020F768IM40) -#include "efr32mg24a020f768im40.h" - -#elif defined(EFR32MG24A021F1024IM40) -#include "efr32mg24a021f1024im40.h" - -#elif defined(EFR32MG24A110F1024IM48) -#include "efr32mg24a110f1024im48.h" - -#elif defined(EFR32MG24A110F1536GM48) -#include "efr32mg24a110f1536gm48.h" - -#elif defined(EFR32MG24A111F1536GM48) -#include "efr32mg24a111f1536gm48.h" - -#elif defined(EFR32MG24A120F1536GM48) -#include "efr32mg24a120f1536gm48.h" - -#elif defined(EFR32MG24A121F1536GM48) -#include "efr32mg24a121f1536gm48.h" - -#elif defined(EFR32MG24A410F1536IM40) -#include "efr32mg24a410f1536im40.h" - -#elif defined(EFR32MG24A410F1536IM48) -#include "efr32mg24a410f1536im48.h" - -#elif defined(EFR32MG24A420F1536IM40) -#include "efr32mg24a420f1536im40.h" - -#elif defined(EFR32MG24A420F1536IM48) -#include "efr32mg24a420f1536im48.h" - -#elif defined(EFR32MG24A610F1536IM40) -#include "efr32mg24a610f1536im40.h" - -#elif defined(EFR32MG24A620F1536IM40) -#include "efr32mg24a620f1536im40.h" - -#elif defined(EFR32MG24B010F1024IM48) -#include "efr32mg24b010f1024im48.h" - -#elif defined(EFR32MG24B010F1536IM40) -#include "efr32mg24b010f1536im40.h" - -#elif defined(EFR32MG24B010F1536IM48) -#include "efr32mg24b010f1536im48.h" - -#elif defined(EFR32MG24B020F1024IM48) -#include "efr32mg24b020f1024im48.h" - -#elif defined(EFR32MG24B020F1536IM40) -#include "efr32mg24b020f1536im40.h" - -#elif defined(EFR32MG24B020F1536IM48) -#include "efr32mg24b020f1536im48.h" - -#elif defined(EFR32MG24B110F1536GM48) -#include "efr32mg24b110f1536gm48.h" - -#elif defined(EFR32MG24B110F1536IM48) -#include "efr32mg24b110f1536im48.h" - -#elif defined(EFR32MG24B120F1536IM48) -#include "efr32mg24b120f1536im48.h" - -#elif defined(EFR32MG24B210F1536IM40) -#include "efr32mg24b210f1536im40.h" - -#elif defined(EFR32MG24B210F1536IM48) -#include "efr32mg24b210f1536im48.h" - -#elif defined(EFR32MG24B220F1536IM48) -#include "efr32mg24b220f1536im48.h" - -#elif defined(EFR32MG24B310F1536IM48) -#include "efr32mg24b310f1536im48.h" - -#elif defined(EFR32MG24B610F1536IM40) -#include "efr32mg24b610f1536im40.h" - -#else -#error "em_device.h: PART NUMBER undefined" -#endif - -#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) -#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." -#endif - -#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) -#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." -#endif -#endif /* EM_DEVICE_H */ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32MG24A010F1024IM40) +#include "efr32mg24a010f1024im40.h" + +#elif defined(EFR32MG24A010F1024IM48) +#include "efr32mg24a010f1024im48.h" + +#elif defined(EFR32MG24A010F1536GM40) +#include "efr32mg24a010f1536gm40.h" + +#elif defined(EFR32MG24A010F1536GM48) +#include "efr32mg24a010f1536gm48.h" + +#elif defined(EFR32MG24A010F1536IM40) +#include "efr32mg24a010f1536im40.h" + +#elif defined(EFR32MG24A010F1536IM48) +#include "efr32mg24a010f1536im48.h" + +#elif defined(EFR32MG24A010F768IM40) +#include "efr32mg24a010f768im40.h" + +#elif defined(EFR32MG24A010F768IM48) +#include "efr32mg24a010f768im48.h" + +#elif defined(EFR32MG24A020F1024IM40) +#include "efr32mg24a020f1024im40.h" + +#elif defined(EFR32MG24A020F1024IM48) +#include "efr32mg24a020f1024im48.h" + +#elif defined(EFR32MG24A020F1536GM40) +#include "efr32mg24a020f1536gm40.h" + +#elif defined(EFR32MG24A020F1536GM48) +#include "efr32mg24a020f1536gm48.h" + +#elif defined(EFR32MG24A020F1536IM40) +#include "efr32mg24a020f1536im40.h" + +#elif defined(EFR32MG24A020F1536IM48) +#include "efr32mg24a020f1536im48.h" + +#elif defined(EFR32MG24A020F768IM40) +#include "efr32mg24a020f768im40.h" + +#elif defined(EFR32MG24A021F1024IM40) +#include "efr32mg24a021f1024im40.h" + +#elif defined(EFR32MG24A110F1024IM48) +#include "efr32mg24a110f1024im48.h" + +#elif defined(EFR32MG24A110F1536GM48) +#include "efr32mg24a110f1536gm48.h" + +#elif defined(EFR32MG24A111F1536GM48) +#include "efr32mg24a111f1536gm48.h" + +#elif defined(EFR32MG24A120F1536GM48) +#include "efr32mg24a120f1536gm48.h" + +#elif defined(EFR32MG24A121F1536GM48) +#include "efr32mg24a121f1536gm48.h" + +#elif defined(EFR32MG24A410F1536IM40) +#include "efr32mg24a410f1536im40.h" + +#elif defined(EFR32MG24A410F1536IM48) +#include "efr32mg24a410f1536im48.h" + +#elif defined(EFR32MG24A420F1536IM40) +#include "efr32mg24a420f1536im40.h" + +#elif defined(EFR32MG24A420F1536IM48) +#include "efr32mg24a420f1536im48.h" + +#elif defined(EFR32MG24A610F1536IM40) +#include "efr32mg24a610f1536im40.h" + +#elif defined(EFR32MG24A620F1536IM40) +#include "efr32mg24a620f1536im40.h" + +#elif defined(EFR32MG24B010F1024IM48) +#include "efr32mg24b010f1024im48.h" + +#elif defined(EFR32MG24B010F1536IM40) +#include "efr32mg24b010f1536im40.h" + +#elif defined(EFR32MG24B010F1536IM48) +#include "efr32mg24b010f1536im48.h" + +#elif defined(EFR32MG24B020F1024IM48) +#include "efr32mg24b020f1024im48.h" + +#elif defined(EFR32MG24B020F1536IM40) +#include "efr32mg24b020f1536im40.h" + +#elif defined(EFR32MG24B020F1536IM48) +#include "efr32mg24b020f1536im48.h" + +#elif defined(EFR32MG24B110F1536GM48) +#include "efr32mg24b110f1536gm48.h" + +#elif defined(EFR32MG24B110F1536IM48) +#include "efr32mg24b110f1536im48.h" + +#elif defined(EFR32MG24B120F1536IM48) +#include "efr32mg24b120f1536im48.h" + +#elif defined(EFR32MG24B210F1536IM40) +#include "efr32mg24b210f1536im40.h" + +#elif defined(EFR32MG24B210F1536IM48) +#include "efr32mg24b210f1536im48.h" + +#elif defined(EFR32MG24B220F1536IM48) +#include "efr32mg24b220f1536im48.h" + +#elif defined(EFR32MG24B310F1536IM48) +#include "efr32mg24b310f1536im48.h" + +#elif defined(EFR32MG24B610F1536IM40) +#include "efr32mg24b610f1536im40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h index 1247439..12e7e54 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Include/system_efr32mg24.h @@ -1,246 +1,246 @@ -/**************************************************************************//** - * @file - * @brief CMSIS system header file for EFR32MG24 - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#ifndef SYSTEM_EFR32MG24_H -#define SYSTEM_EFR32MG24_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/***************************************************************************//** - * @addtogroup Parts - * @{ - ******************************************************************************/ -/***************************************************************************//** - * @addtogroup EFR32MG24 EFR32MG24 - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/* Interrupt vectortable entry */ -typedef union { - void (*VECTOR_TABLE_Type)(void); - void *topOfStack; -} tVectorEntry; - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -#if !defined(SYSTEM_NO_STATIC_MEMORY) -extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ -extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ -#endif - -/*Re-direction of IRQn.*/ -#if defined (SL_TRUSTZONE_SECURE) -#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn -#else -#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn -#endif /* SL_TRUSTZONE_SECURE */ - -/*Re-direction of IRQHandler.*/ -#if defined (SL_TRUSTZONE_SECURE) -#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler -#else -#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler -#endif /* SL_TRUSTZONE_SECURE */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void Reset_Handler(void); /**< Reset Handler */ -void NMI_Handler(void); /**< NMI Handler */ -void HardFault_Handler(void); /**< Hard Fault Handler */ -void MemManage_Handler(void); /**< MPU Fault Handler */ -void BusFault_Handler(void); /**< Bus Fault Handler */ -void UsageFault_Handler(void); /**< Usage Fault Handler */ -void SecureFault_Handler(void); /**< Secure Fault Handler */ -void SVC_Handler(void); /**< SVCall Handler */ -void DebugMon_Handler(void); /**< Debug Monitor Handler */ -void PendSV_Handler(void); /**< PendSV Handler */ -void SysTick_Handler(void); /**< SysTick Handler */ - -/* Part Specific Interrupts */ -void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ -void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ -void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ -void EMU_IRQHandler(void); /**< EMU IRQ Handler */ -void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ -void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ -void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ -void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ -void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ -void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ -void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ -void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ -void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ -void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ -void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ -void MVP_IRQHandler(void); /**< MVP IRQ Handler */ -void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ -void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ -void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ -void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ -void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ -void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ -void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ -void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ -void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ -void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ -void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ -void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ -void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ -void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ -void AGC_IRQHandler(void); /**< AGC IRQ Handler */ -void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ -void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ -void FRC_IRQHandler(void); /**< FRC IRQ Handler */ -void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ -void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ -void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ -void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ -void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */ -void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ -void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ -void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */ -void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ -void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ -void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ -void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ -void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */ -void CMU_IRQHandler(void); /**< CMU IRQ Handler */ -void AES_IRQHandler(void); /**< AES IRQ Handler */ -void IADC_IRQHandler(void); /**< IADC IRQ Handler */ -void MSC_IRQHandler(void); /**< MSC IRQ Handler */ -void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ -void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ -void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ -void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ -void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ -void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ -void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ -void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ -void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ -void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ -void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ -void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ -void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ -void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ -void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ -void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ -void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */ -void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */ -void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */ -void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */ -void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ -void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ -void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */ -void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */ -void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */ - -#if (__FPU_PRESENT == 1) -void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ -#endif - -uint32_t SystemHCLKGet(void); - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that only if changing the core clock frequency through the EMLIB - * CMU API, this variable will be kept updated. This function is only - * provided for CMSIS compliance and if a user modifies the the core clock - * outside the EMLIB CMU API. - *****************************************************************************/ -static __INLINE uint32_t SystemCoreClockGet(void) -{ - return SystemHCLKGet(); -} - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that only if changing the core clock frequency through the EMLIB - * CMU API, this variable will be kept updated. This function is only - * provided for CMSIS compliance and if a user modifies the the core clock - * outside the EMLIB CMU API. - *****************************************************************************/ -static __INLINE void SystemCoreClockUpdate(void) -{ - SystemHCLKGet(); -} - -void SystemInit(void); -#if !defined(SL_LEGACY_LINKER) -void FlashToRamCopy(uint32_t *from, - uint32_t *to, - uint32_t size); -#endif -uint32_t SystemHFRCODPLLClockGet(void); -void SystemHFRCODPLLClockSet(uint32_t freq); -uint32_t SystemSYSCLKGet(void); -uint32_t SystemMaxCoreClockGet(void); -uint32_t SystemFSRCOClockGet(void); -uint32_t SystemHFXOClockGet(void); -void SystemHFXOClockSet(uint32_t freq); -uint32_t SystemCLKIN0Get(void); -uint32_t SystemHFRCOEM23ClockGet(void); -uint32_t SystemLFXOClockGet(void); -void SystemLFXOClockSet(uint32_t freq); -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemULFRCOClockGet(void); - -/** @} End of group */ -/** @} End of group Parts */ - -#ifdef __cplusplus -} -#endif -#endif /* SYSTEM_EFR32MG24_H */ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32MG24 + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32MG24_H +#define SYSTEM_EFR32MG24_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32MG24 EFR32MG24 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void EUSART0_RX_IRQHandler(void); /**< EUSART0_RX IRQ Handler */ +void EUSART0_TX_IRQHandler(void); /**< EUSART0_TX IRQ Handler */ +void EUSART1_RX_IRQHandler(void); /**< EUSART1_RX IRQ Handler */ +void EUSART1_TX_IRQHandler(void); /**< EUSART1_TX IRQ Handler */ +void MVP_IRQHandler(void); /**< MVP IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void MPAHBRAM_IRQHandler(void); /**< MPAHBRAM IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void HOSTMAILBOX_IRQHandler(void); /**< HOSTMAILBOX IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void ACMP0_IRQHandler(void); /**< ACMP0 IRQ Handler */ +void ACMP1_IRQHandler(void); /**< ACMP1 IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void WDOG1_IRQHandler(void); /**< WDOG1 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void HFRCOEM23_IRQHandler(void); /**< HFRCOEM23 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void PCNT0_IRQHandler(void); /**< PCNT0 IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void FPUEXH_IRQHandler(void); /**< FPUEXH IRQ Handler */ +void SETAMPERHOST_IRQHandler(void); /**< SETAMPERHOST IRQ Handler */ +void SEMBRX_IRQHandler(void); /**< SEMBRX IRQ Handler */ +void SEMBTX_IRQHandler(void); /**< SEMBTX IRQ Handler */ +void SYSRTC_APP_IRQHandler(void); /**< SYSRTC_APP IRQ Handler */ +void SYSRTC_SEQ_IRQHandler(void); /**< SYSRTC_SEQ IRQ Handler */ +void KEYSCAN_IRQHandler(void); /**< KEYSCAN IRQ Handler */ +void RFECA0_IRQHandler(void); /**< RFECA0 IRQ Handler */ +void RFECA1_IRQHandler(void); /**< RFECA1 IRQ Handler */ +void VDAC0_IRQHandler(void); /**< VDAC0 IRQ Handler */ +void VDAC1_IRQHandler(void); /**< VDAC1 IRQ Handler */ +void AHB2AHB0_IRQHandler(void); /**< AHB2AHB0 IRQ Handler */ +void AHB2AHB1_IRQHandler(void); /**< AHB2AHB1 IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +#if !defined(SL_LEGACY_LINKER) +void FlashToRamCopy(uint32_t *from, + uint32_t *to, + uint32_t size); +#endif +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +uint32_t SystemSYSCLKGet(void); +uint32_t SystemMaxCoreClockGet(void); +uint32_t SystemFSRCOClockGet(void); +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +uint32_t SystemCLKIN0Get(void); +uint32_t SystemHFRCOEM23ClockGet(void); +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32MG24_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c index abbf0ad..fb51a67 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c @@ -1,430 +1,430 @@ -/****************************************************************************** -* @file startup_efr32mg24.c -* @brief CMSIS-Core(M) Device Startup File for -* Device EFR32MG24 -* @version V2.1.0 -* @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* -******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "em_device.h" - -#ifdef BOOTLOADER_ENABLE -#include "api/btl_interface.h" - -#endif // BOOTLOADER_ENABLE -#ifdef SL_APP_PROPERTIES -#include "api/application_properties.h" - -#endif // SL_APP_PROPERTIES - -#define TOTAL_INTERRUPTS (16 + EXT_IRQ_COUNT) - -#ifdef BOOTLOADER_ENABLE -extern MainBootloaderTable_t mainStageTable; -extern void SystemInit2(void); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void (*VECTOR_TABLE_Type)(void); -#endif - -#ifdef SL_APP_PROPERTIES -extern ApplicationProperties_t sl_app_properties; - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void (*VECTOR_TABLE_Type)(void); -#endif - -/*--------------------------------------------------------------------------- - * External References - *---------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -#if defined (SL_TRUSTZONE_SECURE) -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint64_t __STACK_SEAL; -#endif // __ARM_FEATURE_CMSE -#endif // SL_TRUSTZONE_SECURE - -extern __NO_RETURN void __PROGRAM_START(void); - -#if defined (__START) && defined (__GNUC__) -extern int __START(void) __attribute__((noreturn)); /* main entry point */ -void Copy_Table(); -void Zero_Table(); -#endif // __START -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) -// Function to copy RAM functions from Flash to RAM at startup time -void CopyRamFuncs(); -#endif -#endif - -/*--------------------------------------------------------------------------- - * Internal References - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void); -void Default_Handler(void); - -#if defined (__GNUC__) -#ifndef __STACK_SIZE -#define __STACK_SIZE 0x00000400 -#endif // __STACK_SIZE - -#ifndef __HEAP_SIZE -#define __HEAP_SIZE 0x00000C00 -#endif // __HEAP_SIZE -#endif // __GNUC__ - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Cortex-M Processor Exceptions */ -void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -#ifndef SL_APP_PROPERTIES -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - -/* Part Specific Interrupts */ -void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_S_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUSART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUSART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUSART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUSART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MVP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MPAHBRAM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HOSTMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ACMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HFRCOEM23_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FPUEXH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SETAMPERHOST_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SEMBRX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SEMBTX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYSRTC_APP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYSRTC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void KEYSCAN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RFECA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RFECA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void VDAC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AHB2AHB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AHB2AHB1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined (__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif // __GNUC__ - -#if defined (__ICCARM__) -#pragma data_alignment=512 -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { -#elif defined(__GNUC__) -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __attribute__((aligned(512))) -__VECTOR_TABLE_ATTRIBUTE = { -#else -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { -#endif - { .topOfStack = &__INITIAL_SP }, /* Initial Stack Pointer */ - { Reset_Handler }, /* Reset Handler */ - { NMI_Handler }, /* -14 NMI Handler */ - { HardFault_Handler }, /* -13 Hard Fault Handler */ - { MemManage_Handler }, /* -12 MPU Fault Handler */ - { BusFault_Handler }, /* -11 Bus Fault Handler */ - { UsageFault_Handler }, /* -10 Usage Fault Handler */ - { SecureFault_Handler }, /* -9 Secure Fault Handler */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ -#ifdef BOOTLOADER_ENABLE - { (VECTOR_TABLE_Type) & mainStageTable }, -#else - { Default_Handler }, /* Reserved */ -#endif - { SVC_Handler }, /* -5 SVCall Handler */ - { DebugMon_Handler }, /* -4 Debug Monitor Handler */ -#ifdef SL_APP_PROPERTIES - { (VECTOR_TABLE_Type) & sl_app_properties }, /* Application properties */ -#else - { sl_app_properties }, /* Application properties */ -#endif - { PendSV_Handler }, /* -2 PendSV Handler */ - { SysTick_Handler }, /* -1 SysTick Handler */ - - /* External interrupts */ - { SMU_SECURE_IRQHandler }, /* -16 = SMU_SECURE */ - { SMU_S_PRIVILEGED_IRQHandler }, /* -15 = SMU_S_PRIVILEGED */ - { SMU_NS_PRIVILEGED_IRQHandler }, /* -14 = SMU_NS_PRIVILEGED */ - { EMU_IRQHandler }, /* -13 = EMU */ - { TIMER0_IRQHandler }, /* -12 = TIMER0 */ - { TIMER1_IRQHandler }, /* -11 = TIMER1 */ - { TIMER2_IRQHandler }, /* -10 = TIMER2 */ - { TIMER3_IRQHandler }, /* -9 = TIMER3 */ - { TIMER4_IRQHandler }, /* -8 = TIMER4 */ - { USART0_RX_IRQHandler }, /* -7 = USART0_RX */ - { USART0_TX_IRQHandler }, /* -6 = USART0_TX */ - { EUSART0_RX_IRQHandler }, /* -5 = EUSART0_RX */ - { EUSART0_TX_IRQHandler }, /* -4 = EUSART0_TX */ - { EUSART1_RX_IRQHandler }, /* -3 = EUSART1_RX */ - { EUSART1_TX_IRQHandler }, /* -2 = EUSART1_TX */ - { MVP_IRQHandler }, /* -1 = MVP */ - { ICACHE0_IRQHandler }, /* 00 = ICACHE0 */ - { BURTC_IRQHandler }, /* 01 = BURTC */ - { LETIMER0_IRQHandler }, /* 02 = LETIMER0 */ - { SYSCFG_IRQHandler }, /* 03 = SYSCFG */ - { MPAHBRAM_IRQHandler }, /* 04 = MPAHBRAM */ - { LDMA_IRQHandler }, /* 05 = LDMA */ - { LFXO_IRQHandler }, /* 06 = LFXO */ - { LFRCO_IRQHandler }, /* 07 = LFRCO */ - { ULFRCO_IRQHandler }, /* 08 = ULFRCO */ - { GPIO_ODD_IRQHandler }, /* 09 = GPIO_ODD */ - { GPIO_EVEN_IRQHandler }, /* 10 = GPIO_EVEN */ - { I2C0_IRQHandler }, /* 11 = I2C0 */ - { I2C1_IRQHandler }, /* 12 = I2C1 */ - { EMUDG_IRQHandler }, /* 13 = EMUDG */ - { AGC_IRQHandler }, /* 14 = AGC */ - { BUFC_IRQHandler }, /* 15 = BUFC */ - { FRC_PRI_IRQHandler }, /* 16 = FRC_PRI */ - { FRC_IRQHandler }, /* 17 = FRC */ - { MODEM_IRQHandler }, /* 18 = MODEM */ - { PROTIMER_IRQHandler }, /* 19 = PROTIMER */ - { RAC_RSM_IRQHandler }, /* 20 = RAC_RSM */ - { RAC_SEQ_IRQHandler }, /* 21 = RAC_SEQ */ - { HOSTMAILBOX_IRQHandler }, /* 22 = HOSTMAILBOX */ - { SYNTH_IRQHandler }, /* 23 = SYNTH */ - { ACMP0_IRQHandler }, /* 24 = ACMP0 */ - { ACMP1_IRQHandler }, /* 25 = ACMP1 */ - { WDOG0_IRQHandler }, /* 26 = WDOG0 */ - { WDOG1_IRQHandler }, /* 27 = WDOG1 */ - { HFXO0_IRQHandler }, /* 28 = HFXO0 */ - { HFRCO0_IRQHandler }, /* 29 = HFRCO0 */ - { HFRCOEM23_IRQHandler }, /* 30 = HFRCOEM23 */ - { CMU_IRQHandler }, /* 31 = CMU */ - { AES_IRQHandler }, /* 32 = AES */ - { IADC_IRQHandler }, /* 33 = IADC */ - { MSC_IRQHandler }, /* 34 = MSC */ - { DPLL0_IRQHandler }, /* 35 = DPLL0 */ - { EMUEFP_IRQHandler }, /* 36 = EMUEFP */ - { DCDC_IRQHandler }, /* 37 = DCDC */ - { PCNT0_IRQHandler }, /* 38 = PCNT0 */ - { SW0_IRQHandler }, /* 39 = SW0 */ - { SW1_IRQHandler }, /* 40 = SW1 */ - { SW2_IRQHandler }, /* 41 = SW2 */ - { SW3_IRQHandler }, /* 42 = SW3 */ - { KERNEL0_IRQHandler }, /* 43 = KERNEL0 */ - { KERNEL1_IRQHandler }, /* 44 = KERNEL1 */ - { M33CTI0_IRQHandler }, /* 45 = M33CTI0 */ - { M33CTI1_IRQHandler }, /* 46 = M33CTI1 */ - { FPUEXH_IRQHandler }, /* 47 = FPUEXH */ - { SETAMPERHOST_IRQHandler }, /* 48 = SETAMPERHOST */ - { SEMBRX_IRQHandler }, /* 49 = SEMBRX */ - { SEMBTX_IRQHandler }, /* 50 = SEMBTX */ - { SYSRTC_APP_IRQHandler }, /* 51 = SYSRTC_APP */ - { SYSRTC_SEQ_IRQHandler }, /* 52 = SYSRTC_SEQ */ - { KEYSCAN_IRQHandler }, /* 53 = KEYSCAN */ - { RFECA0_IRQHandler }, /* 54 = RFECA0 */ - { RFECA1_IRQHandler }, /* 55 = RFECA1 */ - { VDAC0_IRQHandler }, /* 56 = VDAC0 */ - { VDAC1_IRQHandler }, /* 57 = VDAC1 */ - { AHB2AHB0_IRQHandler }, /* 58 = AHB2AHB0 */ - { AHB2AHB1_IRQHandler }, /* 59 = AHB2AHB1 */ -}; - -#if defined (__GNUC__) -#pragma GCC diagnostic pop -#endif // __GNUC__ - -#if defined (__START) && defined (__GNUC__) -void Copy_Table() -{ - uint32_t *pSrc, *pDest; - extern uint32_t __etext; - extern uint32_t __data_start__; - extern uint32_t __data_end__; - pSrc = &__etext; - pDest = &__data_start__; - - for (; pDest < &__data_end__; ) { - *pDest++ = *pSrc++; - } -} - -void Zero_Table() -{ - uint32_t *pDest; - extern uint32_t __bss_start__; - extern uint32_t __bss_end__; - pDest = &__bss_start__; - - for (; pDest < &__bss_end__; ) { - *pDest++ = 0UL; - } -} -#endif // __START - -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) -void CopyRamFuncs() -{ - extern uint32_t __lma_ramfuncs_start__; - extern uint32_t __lma_ramfuncs_end__; - extern uint32_t __ramfuncs_start__; - uint32_t size = &__lma_ramfuncs_end__ - &__lma_ramfuncs_start__; - - FlashToRamCopy(&__lma_ramfuncs_start__, &__ramfuncs_start__, size); -} -#endif -#endif - -/*--------------------------------------------------------------------------- - * Reset Handler called on controller reset - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ -#if defined (SL_TRUSTZONE_SECURE) - __set_MSPLIM((uint32_t) (&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *) (&__STACK_SEAL)); -#endif // __ARM_FEATURE_CMSE -#endif // SL_TRUSTZONE_SECURE - - #ifndef __NO_SYSTEM_INIT - SystemInit(); /* CMSIS System Initialization */ - #endif - -#ifdef BOOTLOADER_ENABLE - SystemInit2(); -#endif // BOOTLOADER_ENABLE -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) - CopyRamFuncs(); -#endif -#endif -#if defined (__GNUC__) && defined (__START) - Copy_Table(); - Zero_Table(); - __START(); -#else - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -#endif // __GNUC__ -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif // __ARMCC_VERSION - -/*---------------------------------------------------------------------------- - * Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while (true) { - } -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif // __ARMCC_VERSION +/****************************************************************************** +* @file startup_efr32mg24.c +* @brief CMSIS-Core(M) Device Startup File for +* Device EFR32MG24 +* @version V2.1.0 +* @date 16. December 2020 +******************************************************************************* +* # License +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is Third Party Software licensed by Silicon Labs from a third party +* and is governed by the sections of the MSLA applicable to Third Party +* Software and the additional terms set forth below. +* +******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "em_device.h" + +#ifdef BOOTLOADER_ENABLE +#include "api/btl_interface.h" + +#endif // BOOTLOADER_ENABLE +#ifdef SL_APP_PROPERTIES +#include "api/application_properties.h" + +#endif // SL_APP_PROPERTIES + +#define TOTAL_INTERRUPTS (16 + EXT_IRQ_COUNT) + +#ifdef BOOTLOADER_ENABLE +extern MainBootloaderTable_t mainStageTable; +extern void SystemInit2(void); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +#ifdef SL_APP_PROPERTIES +extern ApplicationProperties_t sl_app_properties; + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +/*--------------------------------------------------------------------------- + * External References + *---------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +#if defined (SL_TRUSTZONE_SECURE) +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + +extern __NO_RETURN void __PROGRAM_START(void); + +#if defined (__START) && defined (__GNUC__) +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +void Copy_Table(); +void Zero_Table(); +#endif // __START +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) +// Function to copy RAM functions from Flash to RAM at startup time +void CopyRamFuncs(); +#endif +#endif + +/*--------------------------------------------------------------------------- + * Internal References + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void); +void Default_Handler(void); + +#if defined (__GNUC__) +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x00000400 +#endif // __STACK_SIZE + +#ifndef __HEAP_SIZE +#define __HEAP_SIZE 0x00000C00 +#endif // __HEAP_SIZE +#endif // __GNUC__ + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M Processor Exceptions */ +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +#ifndef SL_APP_PROPERTIES +/* Provide a dummy value for the sl_app_properties symbol. */ +void sl_app_properties(void); /* Prototype to please MISRA checkers. */ +void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + +/* Part Specific Interrupts */ +void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_S_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUSART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MVP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MPAHBRAM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HOSTMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ACMP0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ACMP1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDOG1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFRCOEM23_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PCNT0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FPUEXH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SETAMPERHOST_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SEMBRX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SEMBTX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSRTC_APP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSRTC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KEYSCAN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RFECA0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RFECA1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void VDAC0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void VDAC1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AHB2AHB0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AHB2AHB1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined (__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif // __GNUC__ + +#if defined (__ICCARM__) +#pragma data_alignment=512 +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#elif defined(__GNUC__) +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __attribute__((aligned(512))) +__VECTOR_TABLE_ATTRIBUTE = { +#else +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#endif + { .topOfStack = &__INITIAL_SP }, /* Initial Stack Pointer */ + { Reset_Handler }, /* Reset Handler */ + { NMI_Handler }, /* -14 NMI Handler */ + { HardFault_Handler }, /* -13 Hard Fault Handler */ + { MemManage_Handler }, /* -12 MPU Fault Handler */ + { BusFault_Handler }, /* -11 Bus Fault Handler */ + { UsageFault_Handler }, /* -10 Usage Fault Handler */ + { SecureFault_Handler }, /* -9 Secure Fault Handler */ + { Default_Handler }, /* Reserved */ + { Default_Handler }, /* Reserved */ +#ifdef BOOTLOADER_ENABLE + { (VECTOR_TABLE_Type) & mainStageTable }, +#else + { Default_Handler }, /* Reserved */ +#endif + { SVC_Handler }, /* -5 SVCall Handler */ + { DebugMon_Handler }, /* -4 Debug Monitor Handler */ +#ifdef SL_APP_PROPERTIES + { (VECTOR_TABLE_Type) & sl_app_properties }, /* Application properties */ +#else + { sl_app_properties }, /* Application properties */ +#endif + { PendSV_Handler }, /* -2 PendSV Handler */ + { SysTick_Handler }, /* -1 SysTick Handler */ + + /* External interrupts */ + { SMU_SECURE_IRQHandler }, /* -16 = SMU_SECURE */ + { SMU_S_PRIVILEGED_IRQHandler }, /* -15 = SMU_S_PRIVILEGED */ + { SMU_NS_PRIVILEGED_IRQHandler }, /* -14 = SMU_NS_PRIVILEGED */ + { EMU_IRQHandler }, /* -13 = EMU */ + { TIMER0_IRQHandler }, /* -12 = TIMER0 */ + { TIMER1_IRQHandler }, /* -11 = TIMER1 */ + { TIMER2_IRQHandler }, /* -10 = TIMER2 */ + { TIMER3_IRQHandler }, /* -9 = TIMER3 */ + { TIMER4_IRQHandler }, /* -8 = TIMER4 */ + { USART0_RX_IRQHandler }, /* -7 = USART0_RX */ + { USART0_TX_IRQHandler }, /* -6 = USART0_TX */ + { EUSART0_RX_IRQHandler }, /* -5 = EUSART0_RX */ + { EUSART0_TX_IRQHandler }, /* -4 = EUSART0_TX */ + { EUSART1_RX_IRQHandler }, /* -3 = EUSART1_RX */ + { EUSART1_TX_IRQHandler }, /* -2 = EUSART1_TX */ + { MVP_IRQHandler }, /* -1 = MVP */ + { ICACHE0_IRQHandler }, /* 00 = ICACHE0 */ + { BURTC_IRQHandler }, /* 01 = BURTC */ + { LETIMER0_IRQHandler }, /* 02 = LETIMER0 */ + { SYSCFG_IRQHandler }, /* 03 = SYSCFG */ + { MPAHBRAM_IRQHandler }, /* 04 = MPAHBRAM */ + { LDMA_IRQHandler }, /* 05 = LDMA */ + { LFXO_IRQHandler }, /* 06 = LFXO */ + { LFRCO_IRQHandler }, /* 07 = LFRCO */ + { ULFRCO_IRQHandler }, /* 08 = ULFRCO */ + { GPIO_ODD_IRQHandler }, /* 09 = GPIO_ODD */ + { GPIO_EVEN_IRQHandler }, /* 10 = GPIO_EVEN */ + { I2C0_IRQHandler }, /* 11 = I2C0 */ + { I2C1_IRQHandler }, /* 12 = I2C1 */ + { EMUDG_IRQHandler }, /* 13 = EMUDG */ + { AGC_IRQHandler }, /* 14 = AGC */ + { BUFC_IRQHandler }, /* 15 = BUFC */ + { FRC_PRI_IRQHandler }, /* 16 = FRC_PRI */ + { FRC_IRQHandler }, /* 17 = FRC */ + { MODEM_IRQHandler }, /* 18 = MODEM */ + { PROTIMER_IRQHandler }, /* 19 = PROTIMER */ + { RAC_RSM_IRQHandler }, /* 20 = RAC_RSM */ + { RAC_SEQ_IRQHandler }, /* 21 = RAC_SEQ */ + { HOSTMAILBOX_IRQHandler }, /* 22 = HOSTMAILBOX */ + { SYNTH_IRQHandler }, /* 23 = SYNTH */ + { ACMP0_IRQHandler }, /* 24 = ACMP0 */ + { ACMP1_IRQHandler }, /* 25 = ACMP1 */ + { WDOG0_IRQHandler }, /* 26 = WDOG0 */ + { WDOG1_IRQHandler }, /* 27 = WDOG1 */ + { HFXO0_IRQHandler }, /* 28 = HFXO0 */ + { HFRCO0_IRQHandler }, /* 29 = HFRCO0 */ + { HFRCOEM23_IRQHandler }, /* 30 = HFRCOEM23 */ + { CMU_IRQHandler }, /* 31 = CMU */ + { AES_IRQHandler }, /* 32 = AES */ + { IADC_IRQHandler }, /* 33 = IADC */ + { MSC_IRQHandler }, /* 34 = MSC */ + { DPLL0_IRQHandler }, /* 35 = DPLL0 */ + { EMUEFP_IRQHandler }, /* 36 = EMUEFP */ + { DCDC_IRQHandler }, /* 37 = DCDC */ + { PCNT0_IRQHandler }, /* 38 = PCNT0 */ + { SW0_IRQHandler }, /* 39 = SW0 */ + { SW1_IRQHandler }, /* 40 = SW1 */ + { SW2_IRQHandler }, /* 41 = SW2 */ + { SW3_IRQHandler }, /* 42 = SW3 */ + { KERNEL0_IRQHandler }, /* 43 = KERNEL0 */ + { KERNEL1_IRQHandler }, /* 44 = KERNEL1 */ + { M33CTI0_IRQHandler }, /* 45 = M33CTI0 */ + { M33CTI1_IRQHandler }, /* 46 = M33CTI1 */ + { FPUEXH_IRQHandler }, /* 47 = FPUEXH */ + { SETAMPERHOST_IRQHandler }, /* 48 = SETAMPERHOST */ + { SEMBRX_IRQHandler }, /* 49 = SEMBRX */ + { SEMBTX_IRQHandler }, /* 50 = SEMBTX */ + { SYSRTC_APP_IRQHandler }, /* 51 = SYSRTC_APP */ + { SYSRTC_SEQ_IRQHandler }, /* 52 = SYSRTC_SEQ */ + { KEYSCAN_IRQHandler }, /* 53 = KEYSCAN */ + { RFECA0_IRQHandler }, /* 54 = RFECA0 */ + { RFECA1_IRQHandler }, /* 55 = RFECA1 */ + { VDAC0_IRQHandler }, /* 56 = VDAC0 */ + { VDAC1_IRQHandler }, /* 57 = VDAC1 */ + { AHB2AHB0_IRQHandler }, /* 58 = AHB2AHB0 */ + { AHB2AHB1_IRQHandler }, /* 59 = AHB2AHB1 */ +}; + +#if defined (__GNUC__) +#pragma GCC diagnostic pop +#endif // __GNUC__ + +#if defined (__START) && defined (__GNUC__) +void Copy_Table() +{ + uint32_t *pSrc, *pDest; + extern uint32_t __etext; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + pSrc = &__etext; + pDest = &__data_start__; + + for (; pDest < &__data_end__; ) { + *pDest++ = *pSrc++; + } +} + +void Zero_Table() +{ + uint32_t *pDest; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + pDest = &__bss_start__; + + for (; pDest < &__bss_end__; ) { + *pDest++ = 0UL; + } +} +#endif // __START + +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) +void CopyRamFuncs() +{ + extern uint32_t __lma_ramfuncs_start__; + extern uint32_t __lma_ramfuncs_end__; + extern uint32_t __ramfuncs_start__; + uint32_t size = &__lma_ramfuncs_end__ - &__lma_ramfuncs_start__; + + FlashToRamCopy(&__lma_ramfuncs_start__, &__ramfuncs_start__, size); +} +#endif +#endif + +/*--------------------------------------------------------------------------- + * Reset Handler called on controller reset + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ +#if defined (SL_TRUSTZONE_SECURE) + __set_MSPLIM((uint32_t) (&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *) (&__STACK_SEAL)); +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + + #ifndef __NO_SYSTEM_INIT + SystemInit(); /* CMSIS System Initialization */ + #endif + +#ifdef BOOTLOADER_ENABLE + SystemInit2(); +#endif // BOOTLOADER_ENABLE +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) + CopyRamFuncs(); +#endif +#endif +#if defined (__GNUC__) && defined (__START) + Copy_Table(); + Zero_Table(); + __START(); +#else + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +#endif // __GNUC__ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif // __ARMCC_VERSION + +/*---------------------------------------------------------------------------- + * Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while (true) { + } +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif // __ARMCC_VERSION diff --git a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c index 97b0f97..90d047c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c +++ b/locator_host/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c @@ -1,682 +1,682 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices. - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#include -#include "em_device.h" - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -// System oscillator frequencies. These frequencies are normally constant -// for a target, but they are made configurable in order to allow run-time -// handling of different boards. The crystal oscillator clocks can be set -// compile time to a non-default value by defining respective nFXO_FREQ -// values according to board design. By defining the nFXO_FREQ to 0, -// one indicates that the oscillator is not present, in order to save some -// SW footprint. - -#if !defined(FSRCO_FREQ) -// FSRCO frequency -#define FSRCO_FREQ (20000000UL) -#endif - -#if !defined(HFXO_FREQ) -// HFXO frequency -#define HFXO_FREQ (39000000UL) -#endif - -#if !defined(HFRCODPLL_STARTUP_FREQ) -// HFRCODPLL startup frequency -#define HFRCODPLL_STARTUP_FREQ (19000000UL) -#endif - -#if !defined(HFRCODPLL_MAX_FREQ) -// Maximum HFRCODPLL frequency -#define HFRCODPLL_MAX_FREQ (80000000UL) -#endif - -// CLKIN0 input -#if !defined(CLKIN0_FREQ) -#define CLKIN0_FREQ (0UL) -#endif - -#if !defined(LFRCO_MAX_FREQ) -// LFRCO frequency, tuned to below frequency during manufacturing. -#define LFRCO_FREQ (32768UL) -#endif - -#if !defined(ULFRCO_FREQ) -// ULFRCO frequency -#define ULFRCO_FREQ (1000UL) -#endif - -#if !defined(LFXO_FREQ) -// LFXO frequency -#define LFXO_FREQ (LFRCO_FREQ) -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) -// NOTE: Gecko bootloaders can't have static variable allocation. -// System HFXO clock frequency -static uint32_t SystemHFXOClock = HFXO_FREQ; -#endif - -#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) -// System LFXO clock frequency -static uint32_t SystemLFXOClock = LFXO_FREQ; -#endif - -#if !defined(SYSTEM_NO_STATIC_MEMORY) -// System HFRCODPLL clock frequency -static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; -#endif - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -#if !defined(SYSTEM_NO_STATIC_MEMORY) - -/** - * @brief - * System System Clock Frequency (Core Clock). - * - * @details - * Required CMSIS global variable that must be kept up-to-date. - */ -uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; - -#endif - -/*--------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *---------------------------------------------------------------------------*/ -extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/**************************************************************************//** - * @brief - * Initialize the system. - * - * @details - * Do required generic HW system init. - * - * @note - * This function is invoked during system init, before the main() routine - * and any data has been initialized. For this reason, it cannot do any - * initialization of variables etc. - *****************************************************************************/ -void SystemInit(void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); -#endif - -#if defined(UNALIGNED_SUPPORT_DISABLE) - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if (__FPU_PRESENT == 1) - SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ - | (3U << 11U * 2U)); /* set CP11 Full Access */ -#endif - -/* Secure app takes care of moving between the security states. - * SL_TRUSTZONE_SECURE MACRO is for secure access. - * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. - * When both the MACROS are not defined, during start-up below code makes sure - * that all the peripherals are accessed from non-secure address except SMU, - * as SMU is used to configure the trustzone state of the system. */ -#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ - && defined(__TZ_PRESENT) - CMU->CLKEN1_SET = CMU_CLKEN1_SMU; - - // config SMU to Secure and other peripherals to Non-Secure. - SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; -#if defined (SEMAILBOX_PRESENT) - SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); -#else - SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); -#endif - - // SAU treats all accesses as non-secure -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SAU->CTRL = SAU_CTRL_ALLNS_Msk; - __DSB(); - __ISB(); -#else - #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." -#endif // __ARM_FEATURE_CMSE - -// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. - NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); - SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; - NVIC_EnableIRQ(SMU_SECURE_IRQn); - SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; -#endif //SL_TRUSTZONE_SECURE -} - -#if !defined(SL_LEGACY_LINKER) -/**************************************************************************//** - * @brief - * Copy data. - * - * @details - * Used to copy data from Flash to Ram at startup and runtime. - * - * @param[in] from - * Pointer to the source address in Flash. - * - * @param[in] to - * Pointer to the destination address in Ram. - * - * @param[in] size - * Size of data to copy. - *****************************************************************************/ -void FlashToRamCopy(uint32_t *from, - uint32_t *to, - uint32_t size) -{ - if (size != 0) { - while (size--) { - *to++ = *from++; - } - } -} -#endif - -/**************************************************************************//** - * @brief - * Get current HFRCODPLL frequency. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * HFRCODPLL frequency in Hz. - *****************************************************************************/ -uint32_t SystemHFRCODPLLClockGet(void) -{ -#if !defined(SYSTEM_NO_STATIC_MEMORY) - return SystemHFRCODPLLClock; -#else - uint32_t ret = 0UL; - - // Get oscillator frequency band - switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) - >> _HFRCO_CAL_FREQRANGE_SHIFT) { - case 0: - switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { - case HFRCO_CAL_CLKDIV_DIV1: - ret = 4000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV2: - ret = 2000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV4: - ret = 1000000UL; - break; - - default: - ret = 0UL; - break; - } - break; - - case 3: - ret = 7000000UL; - break; - - case 6: - ret = 13000000UL; - break; - - case 7: - ret = 16000000UL; - break; - - case 8: - ret = 19000000UL; - break; - - case 10: - ret = 26000000UL; - break; - - case 11: - ret = 32000000UL; - break; - - case 12: - ret = 38000000UL; - break; - - case 13: - ret = 48000000UL; - break; - - case 14: - ret = 56000000UL; - break; - - case 15: - ret = 64000000UL; - break; - - case 16: - ret = 80000000UL; - break; - - default: - break; - } - return ret; -#endif -} - -/**************************************************************************//** - * @brief - * Set HFRCODPLL frequency value. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * HFRCODPLL frequency in Hz. - *****************************************************************************/ -void SystemHFRCODPLLClockSet(uint32_t freq) -{ -#if !defined(SYSTEM_NO_STATIC_MEMORY) - SystemHFRCODPLLClock = freq; -#else - (void) freq; // Unused parameter -#endif -} - -/***************************************************************************//** - * @brief - * Get the current system clock frequency (SYSCLK). - * - * @details - * Calculate and get the current core clock frequency based on the current - * hardware configuration. - * - * @note - * This is an EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * Current system clock (SYSCLK) frequency in Hz. - ******************************************************************************/ -uint32_t SystemSYSCLKGet(void) -{ - uint32_t ret = 0U; - - // Find clock source - switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { - case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: - ret = SystemHFRCODPLLClockGet(); - break; - -#if (HFXO_FREQ > 0U) - case _CMU_SYSCLKCTRL_CLKSEL_HFXO: -#if defined(SYSTEM_NO_STATIC_MEMORY) - ret = HFXO_FREQ; -#else - ret = SystemHFXOClock; -#endif - break; -#endif - -#if (CLKIN0_FREQ > 0U) - case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: - ret = CLKIN0_FREQ; - break; -#endif - - case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: - ret = FSRCO_FREQ; - break; - - default: - // Unknown clock source. - while (1) { - } - } - return ret; -} - -/***************************************************************************//** - * @brief - * Get the current system core clock frequency (HCLK). - * - * @details - * Calculate and get the current core clock frequency based on the current - * configuration. Assuming that the SystemCoreClock global variable is - * maintained, the core clock frequency is stored in that variable as well. - * This function will however calculate the core clock based on actual HW - * configuration. It will also update the SystemCoreClock global variable. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * The current core clock (HCLK) frequency in Hz. - ******************************************************************************/ -uint32_t SystemHCLKGet(void) -{ - uint32_t presc, ret; - - ret = SystemSYSCLKGet(); - - presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; - - ret /= presc + 1U; - -#if !defined(SYSTEM_NO_STATIC_MEMORY) - // Keep CMSIS system clock variable up-to-date - SystemCoreClock = ret; -#endif - - return ret; -} - -/***************************************************************************//** - * @brief - * Get the maximum core clock frequency. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * The maximum core clock frequency in Hz. - ******************************************************************************/ -uint32_t SystemMaxCoreClockGet(void) -{ - return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ - ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); -} - -/**************************************************************************//** - * @brief - * Get high frequency crystal oscillator clock frequency for target system. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. - *****************************************************************************/ -uint32_t SystemHFXOClockGet(void) -{ - // The external crystal oscillator is not present if HFXO_FREQ==0 -#if (HFXO_FREQ > 0U) -#if defined(SYSTEM_NO_STATIC_MEMORY) - return HFXO_FREQ; -#else - return SystemHFXOClock; -#endif -#else - return 0U; -#endif -} - -/**************************************************************************//** - * @brief - * Set high frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * HFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemHFXOClockSet(uint32_t freq) -{ - // External crystal oscillator present? -#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) - SystemHFXOClock = freq; - - // Update core clock frequency if HFXO is used to clock core - if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) - == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { - // This function will update the global variable - SystemHCLKGet(); - } -#else - (void) freq; // Unused parameter -#endif -} - -/**************************************************************************//** - * @brief - * Get current CLKIN0 frequency. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * CLKIN0 frequency in Hz. - *****************************************************************************/ -uint32_t SystemCLKIN0Get(void) -{ - return CLKIN0_FREQ; -} - -/**************************************************************************//** - * @brief - * Get FSRCO frequency. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * FSRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemFSRCOClockGet(void) -{ - return FSRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get current HFRCOEM23 frequency. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * HFRCOEM23 frequency in Hz. - *****************************************************************************/ -uint32_t SystemHFRCOEM23ClockGet(void) -{ - uint32_t ret = 0UL; - - // Get oscillator frequency band - switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) - >> _HFRCO_CAL_FREQRANGE_SHIFT) { - case 0: - switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) { - case HFRCO_CAL_CLKDIV_DIV1: - ret = 4000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV2: - ret = 2000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV4: - ret = 1000000UL; - break; - - default: - ret = 0UL; - break; - } - break; - - case 6: - ret = 13000000UL; - break; - - case 7: - ret = 16000000UL; - break; - - case 8: - ret = 19000000UL; - break; - - case 10: - ret = 26000000UL; - break; - - case 11: - ret = 32000000UL; - break; - - case 12: - ret = 40000000UL; - break; - - default: - break; - } - return ret; -} - -/**************************************************************************//** - * @brief - * Get low frequency RC oscillator clock frequency for target system. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * LFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFRCOClockGet(void) -{ - return LFRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get ultra low frequency RC oscillator clock frequency for target system. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * ULFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemULFRCOClockGet(void) -{ - // The ULFRCO frequency is not tuned, and can be very inaccurate - return ULFRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get low frequency crystal oscillator clock frequency for target system. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @return - * LFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFXOClockGet(void) -{ - // External crystal present? -#if (LFXO_FREQ > 0U) -#if defined(SYSTEM_NO_STATIC_MEMORY) - return LFXO_FREQ; -#else - return SystemLFXOClock; -#endif -#else - return 0U; -#endif -} - -/**************************************************************************//** - * @brief - * Set low frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is a EFR32MG24 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * LFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemLFXOClockSet(uint32_t freq) -{ - // External crystal oscillator present? -#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) - SystemLFXOClock = freq; -#else - (void) freq; // Unused parameter -#endif -} +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32MG24 devices. + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (39000000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +#if !defined(SL_LEGACY_LINKER) +/**************************************************************************//** + * @brief + * Copy data. + * + * @details + * Used to copy data from Flash to Ram at startup and runtime. + * + * @param[in] from + * Pointer to the source address in Flash. + * + * @param[in] to + * Pointer to the destination address in Ram. + * + * @param[in] size + * Size of data to copy. + *****************************************************************************/ +void FlashToRamCopy(uint32_t *from, + uint32_t *to, + uint32_t size) +{ + if (size != 0) { + while (size--) { + *to++ = *from++; + } + } +} +#endif + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get current HFRCOEM23 frequency. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCOEM23 frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCOEM23ClockGet(void) +{ + uint32_t ret = 0UL; + + // Get oscillator frequency band + switch ((HFRCOEM23->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCOEM23->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 40000000UL; + break; + + default: + break; + } + return ret; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32MG24 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h index 6747fc7..ae493ef 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h @@ -1,99 +1,99 @@ -/***************************************************************************//** - * @file - * @brief API "assert" implementation. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_ASSERT_H -#define SL_ASSERT_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(DOXY_DOC_ONLY) -/** Included for documentation purposes only. This define is not present by default. - * DEBUG_EFM should be defined from the compiler to enable the default internal - * assert handler. */ -#define DEBUG_EFM -#endif - -#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) -/***************************************************************************//** - * @addtogroup assert ASSERT - Assert - * @brief Assert/error checking module - * @details - * By default, library assert usage is not included to reduce - * footprint and processing overhead. Further, assert usage is decoupled - * from ISO C assert handling (NDEBUG usage) to allow using ISO C - * assert without including assert statements. - * - * Below are available defines for controlling assert inclusion. The defines - * are typically for a project to be used by the preprocessor. - * - * @li If DEBUG_EFM is defined, the internal library assert handling will - * be used. This is implemented as a simple while(true) loop. DEBUG_EFM is not - * defined by default. - * - * @li If DEBUG_EFM_USER is defined, the user must provide custom - * implementation of the assertEFM() function. - * - * @li If both DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() - * statements are not operational. - * - * @note - * The internal assert is documented because DEBUG_EFM is defined in - * the doxygen configuration. - * @{ - ******************************************************************************/ -/* Due to footprint considerations, we only pass file name and line number, */ -/* not the assert expression (nor function name (C99)) */ -/***************************************************************************//** - * @brief - * Assert function for EFM. - * @param[in] file - path and file name of the assert. - * - * @param[in] line - line number, in the file. - ******************************************************************************/ -void assertEFM(const char *file, int line); -/** Default assertion is not operational */ -#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) - -#else - -/** Default assertion is not operational */ -#define EFM_ASSERT(expr) ((void)(expr)) - -#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ - -/** @} (end addtogroup assert) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_ASSERT_H */ +/***************************************************************************//** + * @file + * @brief API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_ASSERT_H +#define SL_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DOXY_DOC_ONLY) +/** Included for documentation purposes only. This define is not present by default. + * DEBUG_EFM should be defined from the compiler to enable the default internal + * assert handler. */ +#define DEBUG_EFM +#endif + +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) +/***************************************************************************//** + * @addtogroup assert ASSERT - Assert + * @brief Assert/error checking module + * @details + * By default, library assert usage is not included to reduce + * footprint and processing overhead. Further, assert usage is decoupled + * from ISO C assert handling (NDEBUG usage) to allow using ISO C + * assert without including assert statements. + * + * Below are available defines for controlling assert inclusion. The defines + * are typically for a project to be used by the preprocessor. + * + * @li If DEBUG_EFM is defined, the internal library assert handling will + * be used. This is implemented as a simple while(true) loop. DEBUG_EFM is not + * defined by default. + * + * @li If DEBUG_EFM_USER is defined, the user must provide custom + * implementation of the assertEFM() function. + * + * @li If both DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() + * statements are not operational. + * + * @note + * The internal assert is documented because DEBUG_EFM is defined in + * the doxygen configuration. + * @{ + ******************************************************************************/ +/* Due to footprint considerations, we only pass file name and line number, */ +/* not the assert expression (nor function name (C99)) */ +/***************************************************************************//** + * @brief + * Assert function for EFM. + * @param[in] file - path and file name of the assert. + * + * @param[in] line - line number, in the file. + ******************************************************************************/ +void assertEFM(const char *file, int line); +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) + +#else + +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((void)(expr)) + +#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ + +/** @} (end addtogroup assert) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_ASSERT_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h index d3a51ec..8a12995 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h @@ -1,80 +1,80 @@ -/******************************************************************************* - * @file - * @brief Implementation of atomic operations. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_ATOMIC_H -#define SL_ATOMIC_H - -/******************************************************************************* - * @addtogroup atomic Atomic Operations - * @brief Atomic operations provide RAM store and read functionalities. - * @n @section atomic_usage Atomic Operations Usage - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Perform an atomic load. Use when a variable must be read from - * RAM. - * - * @param dest Variable where to copy the loaded value. - * - * @param source Variable from where to load the value. - * - * @note Does only support native types <= 32 bits. - * - * @note Load operation on 32 bit value is atomic on ARM architecture. - * - * @note Only the load operation from 'source' is guaranteed to be - * performed atomically. If writing to 'dest' implies a store, - * the load and store operations are not guaranteed to be - * performed atomically. - ******************************************************************************/ -#define sl_atomic_load(dest, source) ((dest) = (source)) - -/******************************************************************************* - * @brief Perform an atomic store. Use when a value must be stored in - * RAM. - * - * @param dest Variable where to store the value. - * - * @param source Variable that contains the value to store in 'dest'. - * - * @note Does only support native types <= 32 bits. - * - * @note Store operation on 32 bit value is atomic on ARM architecture. - * - * @note Only the store operation to 'dest' is guaranteed to be - * performed atomically. If reading from 'source' implies a load, - * the store and load operations are not guaranteed to be - * performed atomically. - ******************************************************************************/ -#define sl_atomic_store(dest, source) ((dest) = (source)) - -/** @} (end addtogroup atomic) */ - -#endif /* SL_ATOMIC_H */ +/******************************************************************************* + * @file + * @brief Implementation of atomic operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ATOMIC_H +#define SL_ATOMIC_H + +/******************************************************************************* + * @addtogroup atomic Atomic Operations + * @brief Atomic operations provide RAM store and read functionalities. + * @n @section atomic_usage Atomic Operations Usage + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Perform an atomic load. Use when a variable must be read from + * RAM. + * + * @param dest Variable where to copy the loaded value. + * + * @param source Variable from where to load the value. + * + * @note Does only support native types <= 32 bits. + * + * @note Load operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the load operation from 'source' is guaranteed to be + * performed atomically. If writing to 'dest' implies a store, + * the load and store operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_load(dest, source) ((dest) = (source)) + +/******************************************************************************* + * @brief Perform an atomic store. Use when a value must be stored in + * RAM. + * + * @param dest Variable where to store the value. + * + * @param source Variable that contains the value to store in 'dest'. + * + * @note Does only support native types <= 32 bits. + * + * @note Store operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the store operation to 'dest' is guaranteed to be + * performed atomically. If reading from 'source' implies a load, + * the store and load operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_store(dest, source) ((dest) = (source)) + +/** @} (end addtogroup atomic) */ + +#endif /* SL_ATOMIC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_common.h b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_common.h index f5621a7..33d2671 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_common.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_common.h @@ -1,385 +1,385 @@ -/***************************************************************************//** - * @file - * @brief General purpose utilities. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_COMMON_H -#define SL_COMMON_H - -#include -#include -#include "sl_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__STATIC_INLINE) -#if !defined(__unix__) && defined(__arm__) -/* Compiler agnostic definitions */ -#include "cmsis_compiler.h" -#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) -#define __STATIC_INLINE static inline -#else -#warning Please provide a macro for your compiler and architecture -#define __STATIC_INLINE static -#endif -#endif - -/***************************************************************************//** - * @addtogroup common COMMON - Common Utilities - * @brief General purpose utilities and cross-compiler support - * @details - * This SDK supports the following compilers/IDEs: - * @li Simplicity Studio - * @li IAR Embedded Workbench - * @li Keil uVision IDE - * @li Plain armgcc - * - * Certain compiler features such as alignment is implemented differently in the tools. - * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent - * code. - * - * @note RAM code macros are implemented in [RAMFUNC](/gecko-platform//emlib-efm32g/). - * Cross-compiler RAM code support needs extended documentation and it is therefore - * implemented as a separate module. - * - * @{ - ******************************************************************************/ - -/** @brief Macros to concatenate. */ -#define SL_CONCAT_PASTER_2(first, second) first ## second ///< sl concat paster 2. -#define SL_CONCAT_PASTER_3(first, second, third) first ## second ## third ///< sl concat paster 3. -#define SL_CONCAT_PASTER_4(first, second, third, fourth) first ## second ## third ## fourth ///< sl concat paster 4. - -/** @brief Round n up to closest interval of i. */ -#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) - -/** @brief Round n down to closest interval of i. */ -#define SL_FLOOR(n, i) ((n / i) * i) - -/** @brief Stringify X */ -#define STRINGIZE(X) #X - -#if !defined(__GNUC__) -/* Not GCC compilers */ - -/** @brief Macro for getting minimum value. */ -#define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) - -/** @brief Macro for getting maximum value. */ -#define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) - -/** @brief Macros for handling packed structures. */ -#define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) -#define SL_PACK_END() _Pragma("pack()") -#define SL_ATTRIBUTE_PACKED - -#if defined(__CC_ARM) -/** @brief MDK-ARM compiler: Macros for handling aligned structures. */ -#define SL_ALIGN(X) __align(X) - -/** MDK-ARM compiler: Macro for handling weak symbols. */ -#define SL_WEAK __attribute__ ((weak)) - -/** MDK-ARM compiler: Macro for handling non-returning functions. */ -#define SL_NORETURN __attribute__ ((noreturn)) - -/** MDK-ARM compiler: Macro for handling section placement */ -#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) -#endif - -#if defined(__ICCARM__) - -#if (__VER__ >= 8000000) -/** @brief Obsoleted macro from version 8.00 and on . */ -#define _STD_BEGIN -/** @brief Obsoleted macro from version 8.00 and on . */ -#define _STD_END -#endif - -/** @brief IAR Embedded Workbench: Macros for handling aligned structures. */ -#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) - -/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ -#define SL_WEAK __weak - -/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ -#define SL_NORETURN __noreturn - -/* *INDENT-OFF* */ -/** IAR Embedded Workbench: Macro for handling section placement */ -#define SL_ATTRIBUTE_SECTION(X) @ X -#endif -/* *INDENT-ON* */ - -#define SL_ATTRIBUTE_ALIGN(X) - -/** @brief Macro for notifying the compiler of an intended - * switch case fallthrough. */ -#define SL_FALLTHROUGH - -/** @brief A macro for notifying the compiler to ignore type limit check. */ -#define SL_IGNORE_TYPE_LIMIT_BEGIN -#define SL_IGNORE_TYPE_LIMIT_END - -#else // !defined(__GNUC__) -/* GCC compilers */ - -/** @brief A macro for getting the minimum value. No side-effects, a and b are evaluated one time only. */ -#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) - -/** @brief A macro for getting the maximum value. No side-effects, a and b are evaluated one time only. */ -#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) - -/** @brief A GCC style macro for handling packed structures. */ -#define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) - -/** @brief A macro for handling packed structures. - * @n Use this macro before the structure definition. - * @n X denotes the maximum alignment of structure members. X is not supported with - * GCC. GCC always uses 1 byte maximum alignment. - */ -#define SL_PACK_START(x) - -/** @brief A macro for handling packed structures. - * @n Use this macro after the structure definition. - * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure - * definition. - */ -#define SL_PACK_END() - -/** @brief GCC style macro for aligning a variable. */ -#define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) - -/** @brief A macro for aligning a variable. - * @n Use this macro before the variable definition. - * @n X denotes the storage alignment value in bytes. - * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal - * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. - */ -#define SL_ALIGN(X) - -/** @brief A macro for defining a weak symbol. */ -#define SL_WEAK __attribute__ ((weak)) - -/** @brief A macro for handling non-returning functions. */ -#define SL_NORETURN __attribute__ ((noreturn)) - -/** A macro for placing a variable in a section. - * @n Use this macro after the variable definition, before the equal sign or a semicolon. - * @n X denotes the section to place the variable in. - */ -#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) - -/** @brief A macro for notifying the compiler of an intended - * switch case fallthrough. */ -#if __GNUC__ >= 7 - #define SL_FALLTHROUGH __attribute__ ((fallthrough)); -#else - #define SL_FALLTHROUGH -#endif - -/** @brief A macro for notifying the compiler to ignore type limit check. */ -#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) - #define SL_IGNORE_TYPE_LIMIT_BEGIN \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wtype-limits\"") - #define SL_IGNORE_TYPE_LIMIT_END \ - _Pragma("GCC diagnostic pop") -#else - #define SL_IGNORE_TYPE_LIMIT_BEGIN - #define SL_IGNORE_TYPE_LIMIT_END ///< A MACRO to notify the compiler, limit END. -#endif - -#endif // !defined(__GNUC__) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** @brief - * Macro for marking deprecated functions - * - * @details - * SL_DEPRECATED_API_SDK_ is used to mark functions that are - * deprecated and should not be used from a given version of the SDK. - * The accompanying SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_ - * define can be set to suppress warnings generated when using - * deprecated APIs. - */ -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_0 -#define SL_DEPRECATED_API_SDK_3_0 -#else -#define SL_DEPRECATED_API_SDK_3_0 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_2 -#define SL_DEPRECATED_API_SDK_3_2 -#else -#define SL_DEPRECATED_API_SDK_3_2 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_3 -#define SL_DEPRECATED_API_SDK_3_3 -#else -#define SL_DEPRECATED_API_SDK_3_3 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_1 -#define SL_DEPRECATED_API_SDK_4_1 -#else -#define SL_DEPRECATED_API_SDK_4_1 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_2 -#define SL_DEPRECATED_API_SDK_4_2 -#else -#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4 -#define SL_DEPRECATED_API_SDK_4_4 -#else -#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated)) -#endif -/** @endcond */ - -/***************************************************************************//** - * @brief - * Count trailing number of zeros. Use CLZ instruction if available. - * - * @param[in] value - * Data value to check for number of trailing zero bits. - * - * @return - * A number of trailing zeros in value. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_CTZ(uint32_t value) -{ -#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) - return __CLZ(__RBIT(value)); - -#else - uint32_t zeros; - for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { - ; - } - return zeros; -#endif -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated function. New code should use @ref SL_CTZ. */ -__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) -{ - return SL_CTZ(value); -} -/** @endcond */ - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * Data value to reverse. - * - * @return - * A reversed value. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_RBIT(uint32_t value) -{ - uint32_t result; - -#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) - result = __RBIT(value); -#else - int32_t s = 4 * 8 - 1; - - result = value; - for (value >>= 1U; value != 0U; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; -#endif - return result; -} - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * 16-bit data value to reverse. - * - * @return - * A 16-bit reversed value. - ******************************************************************************/ -__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) -{ - return (uint16_t)(SL_RBIT(value) >> 16); -} - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * 8-bit data value to reverse. - * - * @return - * A 8-bit reversed value. - ******************************************************************************/ -__STATIC_INLINE uint8_t SL_RBIT8(uint8_t value) -{ - return (uint8_t)(SL_RBIT(value) >> 24); -} - -/***************************************************************************//** - * @brief - * Convert logarithm of 2 to division factor. - * - * @param[in] log2 - * Logarithm of 2. - * - * @return - * Dividend. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) -{ - EFM_ASSERT(log2 < 32U); - return 1UL << log2; -} - -/** @} (end addtogroup common) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_COMMON_H */ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COMMON_H +#define SL_COMMON_H + +#include +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__STATIC_INLINE) +#if !defined(__unix__) && defined(__arm__) +/* Compiler agnostic definitions */ +#include "cmsis_compiler.h" +#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#define __STATIC_INLINE static inline +#else +#warning Please provide a macro for your compiler and architecture +#define __STATIC_INLINE static +#endif +#endif + +/***************************************************************************//** + * @addtogroup common COMMON - Common Utilities + * @brief General purpose utilities and cross-compiler support + * @details + * This SDK supports the following compilers/IDEs: + * @li Simplicity Studio + * @li IAR Embedded Workbench + * @li Keil uVision IDE + * @li Plain armgcc + * + * Certain compiler features such as alignment is implemented differently in the tools. + * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent + * code. + * + * @note RAM code macros are implemented in [RAMFUNC](/gecko-platform//emlib-efm32g/). + * Cross-compiler RAM code support needs extended documentation and it is therefore + * implemented as a separate module. + * + * @{ + ******************************************************************************/ + +/** @brief Macros to concatenate. */ +#define SL_CONCAT_PASTER_2(first, second) first ## second ///< sl concat paster 2. +#define SL_CONCAT_PASTER_3(first, second, third) first ## second ## third ///< sl concat paster 3. +#define SL_CONCAT_PASTER_4(first, second, third, fourth) first ## second ## third ## fourth ///< sl concat paster 4. + +/** @brief Round n up to closest interval of i. */ +#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) + +/** @brief Round n down to closest interval of i. */ +#define SL_FLOOR(n, i) ((n / i) * i) + +/** @brief Stringify X */ +#define STRINGIZE(X) #X + +#if !defined(__GNUC__) +/* Not GCC compilers */ + +/** @brief Macro for getting minimum value. */ +#define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) + +/** @brief Macro for getting maximum value. */ +#define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) + +/** @brief Macros for handling packed structures. */ +#define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) +#define SL_PACK_END() _Pragma("pack()") +#define SL_ATTRIBUTE_PACKED + +#if defined(__CC_ARM) +/** @brief MDK-ARM compiler: Macros for handling aligned structures. */ +#define SL_ALIGN(X) __align(X) + +/** MDK-ARM compiler: Macro for handling weak symbols. */ +#define SL_WEAK __attribute__ ((weak)) + +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** MDK-ARM compiler: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) +#endif + +#if defined(__ICCARM__) + +#if (__VER__ >= 8000000) +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_BEGIN +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_END +#endif + +/** @brief IAR Embedded Workbench: Macros for handling aligned structures. */ +#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) + +/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ +#define SL_WEAK __weak + +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + +/* *INDENT-OFF* */ +/** IAR Embedded Workbench: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) @ X +#endif +/* *INDENT-ON* */ + +#define SL_ATTRIBUTE_ALIGN(X) + +/** @brief Macro for notifying the compiler of an intended + * switch case fallthrough. */ +#define SL_FALLTHROUGH + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#define SL_IGNORE_TYPE_LIMIT_BEGIN +#define SL_IGNORE_TYPE_LIMIT_END + +#else // !defined(__GNUC__) +/* GCC compilers */ + +/** @brief A macro for getting the minimum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) + +/** @brief A macro for getting the maximum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) + +/** @brief A GCC style macro for handling packed structures. */ +#define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) + +/** @brief A macro for handling packed structures. + * @n Use this macro before the structure definition. + * @n X denotes the maximum alignment of structure members. X is not supported with + * GCC. GCC always uses 1 byte maximum alignment. + */ +#define SL_PACK_START(x) + +/** @brief A macro for handling packed structures. + * @n Use this macro after the structure definition. + * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure + * definition. + */ +#define SL_PACK_END() + +/** @brief GCC style macro for aligning a variable. */ +#define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) + +/** @brief A macro for aligning a variable. + * @n Use this macro before the variable definition. + * @n X denotes the storage alignment value in bytes. + * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal + * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. + */ +#define SL_ALIGN(X) + +/** @brief A macro for defining a weak symbol. */ +#define SL_WEAK __attribute__ ((weak)) + +/** @brief A macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** A macro for placing a variable in a section. + * @n Use this macro after the variable definition, before the equal sign or a semicolon. + * @n X denotes the section to place the variable in. + */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) + +/** @brief A macro for notifying the compiler of an intended + * switch case fallthrough. */ +#if __GNUC__ >= 7 + #define SL_FALLTHROUGH __attribute__ ((fallthrough)); +#else + #define SL_FALLTHROUGH +#endif + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) + #define SL_IGNORE_TYPE_LIMIT_BEGIN \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wtype-limits\"") + #define SL_IGNORE_TYPE_LIMIT_END \ + _Pragma("GCC diagnostic pop") +#else + #define SL_IGNORE_TYPE_LIMIT_BEGIN + #define SL_IGNORE_TYPE_LIMIT_END ///< A MACRO to notify the compiler, limit END. +#endif + +#endif // !defined(__GNUC__) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** @brief + * Macro for marking deprecated functions + * + * @details + * SL_DEPRECATED_API_SDK_ is used to mark functions that are + * deprecated and should not be used from a given version of the SDK. + * The accompanying SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_ + * define can be set to suppress warnings generated when using + * deprecated APIs. + */ +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_0 +#define SL_DEPRECATED_API_SDK_3_0 +#else +#define SL_DEPRECATED_API_SDK_3_0 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_2 +#define SL_DEPRECATED_API_SDK_3_2 +#else +#define SL_DEPRECATED_API_SDK_3_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_3 +#define SL_DEPRECATED_API_SDK_3_3 +#else +#define SL_DEPRECATED_API_SDK_3_3 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_1 +#define SL_DEPRECATED_API_SDK_4_1 +#else +#define SL_DEPRECATED_API_SDK_4_1 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_2 +#define SL_DEPRECATED_API_SDK_4_2 +#else +#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4 +#define SL_DEPRECATED_API_SDK_4_4 +#else +#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated)) +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Count trailing number of zeros. Use CLZ instruction if available. + * + * @param[in] value + * Data value to check for number of trailing zero bits. + * + * @return + * A number of trailing zeros in value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_CTZ(uint32_t value) +{ +#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) + return __CLZ(__RBIT(value)); + +#else + uint32_t zeros; + for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { + ; + } + return zeros; +#endif +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated function. New code should use @ref SL_CTZ. */ +__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) +{ + return SL_CTZ(value); +} +/** @endcond */ + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * Data value to reverse. + * + * @return + * A reversed value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_RBIT(uint32_t value) +{ + uint32_t result; + +#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) + result = __RBIT(value); +#else + int32_t s = 4 * 8 - 1; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; +#endif + return result; +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 16-bit data value to reverse. + * + * @return + * A 16-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) +{ + return (uint16_t)(SL_RBIT(value) >> 16); +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 8-bit data value to reverse. + * + * @return + * A 8-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint8_t SL_RBIT8(uint8_t value) +{ + return (uint8_t)(SL_RBIT(value) >> 24); +} + +/***************************************************************************//** + * @brief + * Convert logarithm of 2 to division factor. + * + * @param[in] log2 + * Logarithm of 2. + * + * @return + * Dividend. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) +{ + EFM_ASSERT(log2 < 32U); + return 1UL << log2; +} + +/** @} (end addtogroup common) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_COMMON_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h index e7e33bb..4240564 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h @@ -1,66 +1,66 @@ -/******************************************************************************* - * @file - * @brief SL_ENUM Implementation - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_ENUM_H -#define SL_ENUM_H - -/******************************************************************************* - * @addtogroup enum Enumerations - * @brief Enumerations with stable binary representation - * @details - * Silicon Labs libraries do not use enumerations because the ARM EABI leaves - * their size ambiguous, which causes problems if the application is built - * with different flags than the library. Instead, uint8_t typedefs - * are used in compiled code for all enumerations. For documentation purposes, - * this is converted to an actual enumeration in documentation. - * @{ - ******************************************************************************/ - -#ifdef DOXYGEN -/// Enumeration mapped to uint8_t -#define SL_ENUM(name) enum name -/// Enumeration mapped to arbitrary type -#define SL_ENUM_GENERIC(name, type) enum name -#else -// NOTE: The following macros might cause MISRA warnings because -// Macro parameters need to be enclosed in parentheses. -// However, it is not possible in C to enclose declaration -// identifiers in parentheses. For example: -// typedef uint8_t (some_identifier); -// is not syntactically correct in the C language (C99). -#define SL_ENUM(name) typedef uint8_t name; enum name##_enum -#define SL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum - -// For debugging, use the following define to turn this back into a proper enumeration -// #define SL_ENUM(name) typedef enum name##_enum name; enum name##_enum -#endif - -/** @} end enum */ - -#endif // SL_ENUM_H +/******************************************************************************* + * @file + * @brief SL_ENUM Implementation + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ENUM_H +#define SL_ENUM_H + +/******************************************************************************* + * @addtogroup enum Enumerations + * @brief Enumerations with stable binary representation + * @details + * Silicon Labs libraries do not use enumerations because the ARM EABI leaves + * their size ambiguous, which causes problems if the application is built + * with different flags than the library. Instead, uint8_t typedefs + * are used in compiled code for all enumerations. For documentation purposes, + * this is converted to an actual enumeration in documentation. + * @{ + ******************************************************************************/ + +#ifdef DOXYGEN +/// Enumeration mapped to uint8_t +#define SL_ENUM(name) enum name +/// Enumeration mapped to arbitrary type +#define SL_ENUM_GENERIC(name, type) enum name +#else +// NOTE: The following macros might cause MISRA warnings because +// Macro parameters need to be enclosed in parentheses. +// However, it is not possible in C to enclose declaration +// identifiers in parentheses. For example: +// typedef uint8_t (some_identifier); +// is not syntactically correct in the C language (C99). +#define SL_ENUM(name) typedef uint8_t name; enum name##_enum +#define SL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum + +// For debugging, use the following define to turn this back into a proper enumeration +// #define SL_ENUM(name) typedef enum name##_enum name; enum name##_enum +#endif + +/** @} end enum */ + +#endif // SL_ENUM_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_status.h b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_status.h index 83a4338..f81a8d3 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_status.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/inc/sl_status.h @@ -1,452 +1,452 @@ -/******************************************************************************* - * @file - * @brief SL Status Codes. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_STATUS_H -#define SL_STATUS_H - -#include - -/******************************************************************************* - * @addtogroup status Status Codes - * @details Status Codes contains error and status code definitions used by GSDK - * software components and stacks. This module also provides routines to - * read the string linked with the error and status codes. - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Space Defines - -#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask. - -#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space. - -#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space. -#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space. -#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space. - -#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space. -#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space. -#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space. -#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space. -#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space. -#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space. -#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space. -#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space. -#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space. -#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space. - -#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space. -#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space. - -#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space. -#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space. -#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space. -#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space. - -#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space. - -#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space. - -// ----------------------------------------------------------------------------- -// Status Defines - -// ----------------------------------------------------------------------------- -// Generic Errors - -#define SL_STATUS_OK ((sl_status_t)0x0000) ///< No error. -#define SL_STATUS_FAIL ((sl_status_t)0x0001) ///< Generic error. - -// State Errors -#define SL_STATUS_INVALID_STATE ((sl_status_t)0x0002) ///< Generic invalid state error. -#define SL_STATUS_NOT_READY ((sl_status_t)0x0003) ///< Module is not ready for requested operation. -#define SL_STATUS_BUSY ((sl_status_t)0x0004) ///< Module is busy and cannot carry out requested operation. -#define SL_STATUS_IN_PROGRESS ((sl_status_t)0x0005) ///< Operation is in progress and not yet complete (pass or fail). -#define SL_STATUS_ABORT ((sl_status_t)0x0006) ///< Operation aborted. -#define SL_STATUS_TIMEOUT ((sl_status_t)0x0007) ///< Operation timed out. -#define SL_STATUS_PERMISSION ((sl_status_t)0x0008) ///< Operation not allowed per permissions. -#define SL_STATUS_WOULD_BLOCK ((sl_status_t)0x0009) ///< Non-blocking operation would block. -#define SL_STATUS_IDLE ((sl_status_t)0x000A) ///< Operation/module is Idle, cannot carry requested operation. -#define SL_STATUS_IS_WAITING ((sl_status_t)0x000B) ///< Operation cannot be done while construct is waiting. -#define SL_STATUS_NONE_WAITING ((sl_status_t)0x000C) ///< No task/construct waiting/pending for that action/event. -#define SL_STATUS_SUSPENDED ((sl_status_t)0x000D) ///< Operation cannot be done while construct is suspended. -#define SL_STATUS_NOT_AVAILABLE ((sl_status_t)0x000E) ///< Feature not available due to software configuration. -#define SL_STATUS_NOT_SUPPORTED ((sl_status_t)0x000F) ///< Feature not supported. -#define SL_STATUS_INITIALIZATION ((sl_status_t)0x0010) ///< Initialization failed. -#define SL_STATUS_NOT_INITIALIZED ((sl_status_t)0x0011) ///< Module has not been initialized. -#define SL_STATUS_ALREADY_INITIALIZED ((sl_status_t)0x0012) ///< Module has already been initialized. -#define SL_STATUS_DELETED ((sl_status_t)0x0013) ///< Object/construct has been deleted. -#define SL_STATUS_ISR ((sl_status_t)0x0014) ///< Illegal call from ISR. -#define SL_STATUS_NETWORK_UP ((sl_status_t)0x0015) ///< Illegal call because network is up. -#define SL_STATUS_NETWORK_DOWN ((sl_status_t)0x0016) ///< Illegal call because network is down. -#define SL_STATUS_NOT_JOINED ((sl_status_t)0x0017) ///< Failure due to not being joined in a network. -#define SL_STATUS_NO_BEACONS ((sl_status_t)0x0018) ///< Invalid operation as there are no beacons. - -// Allocation/ownership Errors -#define SL_STATUS_ALLOCATION_FAILED ((sl_status_t)0x0019) ///< Generic allocation error. -#define SL_STATUS_NO_MORE_RESOURCE ((sl_status_t)0x001A) ///< No more resource available to perform the operation. -#define SL_STATUS_EMPTY ((sl_status_t)0x001B) ///< Item/list/queue is empty. -#define SL_STATUS_FULL ((sl_status_t)0x001C) ///< Item/list/queue is full. -#define SL_STATUS_WOULD_OVERFLOW ((sl_status_t)0x001D) ///< Item would overflow. -#define SL_STATUS_HAS_OVERFLOWED ((sl_status_t)0x001E) ///< Item/list/queue has been overflowed. -#define SL_STATUS_OWNERSHIP ((sl_status_t)0x001F) ///< Generic ownership error. -#define SL_STATUS_IS_OWNER ((sl_status_t)0x0020) ///< Already/still owning resource. - -// Invalid Parameters Errors -#define SL_STATUS_INVALID_PARAMETER ((sl_status_t)0x0021) ///< Generic invalid argument or consequence of invalid argument. -#define SL_STATUS_NULL_POINTER ((sl_status_t)0x0022) ///< Invalid null pointer received as argument. -#define SL_STATUS_INVALID_CONFIGURATION ((sl_status_t)0x0023) ///< Invalid configuration provided. -#define SL_STATUS_INVALID_MODE ((sl_status_t)0x0024) ///< Invalid mode. -#define SL_STATUS_INVALID_HANDLE ((sl_status_t)0x0025) ///< Invalid handle. -#define SL_STATUS_INVALID_TYPE ((sl_status_t)0x0026) ///< Invalid type for operation. -#define SL_STATUS_INVALID_INDEX ((sl_status_t)0x0027) ///< Invalid index. -#define SL_STATUS_INVALID_RANGE ((sl_status_t)0x0028) ///< Invalid range. -#define SL_STATUS_INVALID_KEY ((sl_status_t)0x0029) ///< Invalid key. -#define SL_STATUS_INVALID_CREDENTIALS ((sl_status_t)0x002A) ///< Invalid credentials. -#define SL_STATUS_INVALID_COUNT ((sl_status_t)0x002B) ///< Invalid count. -#define SL_STATUS_INVALID_SIGNATURE ((sl_status_t)0x002C) ///< Invalid signature / verification failed. -#define SL_STATUS_NOT_FOUND ((sl_status_t)0x002D) ///< Item could not be found. -#define SL_STATUS_ALREADY_EXISTS ((sl_status_t)0x002E) ///< Item already exists. - -// IO/Communication Errors -#define SL_STATUS_IO ((sl_status_t)0x002F) ///< Generic I/O failure. -#define SL_STATUS_IO_TIMEOUT ((sl_status_t)0x0030) ///< I/O failure due to timeout. -#define SL_STATUS_TRANSMIT ((sl_status_t)0x0031) ///< Generic transmission error. -#define SL_STATUS_TRANSMIT_UNDERFLOW ((sl_status_t)0x0032) ///< Transmit underflowed. -#define SL_STATUS_TRANSMIT_INCOMPLETE ((sl_status_t)0x0033) ///< Transmit is incomplete. -#define SL_STATUS_TRANSMIT_BUSY ((sl_status_t)0x0034) ///< Transmit is busy. -#define SL_STATUS_RECEIVE ((sl_status_t)0x0035) ///< Generic reception error. -#define SL_STATUS_OBJECT_READ ((sl_status_t)0x0036) ///< Failed to read on/via given object. -#define SL_STATUS_OBJECT_WRITE ((sl_status_t)0x0037) ///< Failed to write on/via given object. -#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long. - -// EEPROM/Flash Errors -#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch. -#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch. -#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited. -#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed. -#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed. -#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed. - -// MAC Errors -#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data. -#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received. -#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout. -#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type. -#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type. -#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure. - -// CLI_STORAGE Errors -#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM - -// Security status codes -#define SL_STATUS_SECURITY_IMAGE_CHECKSUM_ERROR ((sl_status_t)0x0046) ///< Image checksum is not valid. -#define SL_STATUS_SECURITY_DECRYPT_ERROR ((sl_status_t)0x0047) ///< Decryption failed - -// Command status codes -#define SL_STATUS_COMMAND_IS_INVALID ((sl_status_t)0x0048) ///< Command was not recognized -#define SL_STATUS_COMMAND_TOO_LONG ((sl_status_t)0x0049) ///< Command or parameter maximum length exceeded -#define SL_STATUS_COMMAND_INCOMPLETE ((sl_status_t)0x004A) ///< Data received does not form a complete command - -// Misc Errors -#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address - -// Unified MAC Errors -#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure. - -// Scan errors -#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning. -#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type. -#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask. -#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration. - -// Bluetooth status codes -#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. -#define SL_STATUS_BT_UNSPECIFIED ((sl_status_t)0x0403) ///< Unspecified error -#define SL_STATUS_BT_HARDWARE ((sl_status_t)0x0404) ///< Hardware failure -#define SL_STATUS_BT_NO_BONDING ((sl_status_t)0x0406) ///< The bonding does not exist. -#define SL_STATUS_BT_CRYPTO ((sl_status_t)0x0407) ///< Error using crypto functions -#define SL_STATUS_BT_DATA_CORRUPTED ((sl_status_t)0x0408) ///< Data was corrupted. -#define SL_STATUS_BT_INVALID_SYNC_HANDLE ((sl_status_t)0x040A) ///< Invalid periodic advertising sync handle -#define SL_STATUS_BT_INVALID_MODULE_ACTION ((sl_status_t)0x040B) ///< Bluetooth cannot be used on this hardware -#define SL_STATUS_BT_RADIO ((sl_status_t)0x040C) ///< Error received from radio -#define SL_STATUS_BT_L2CAP_REMOTE_DISCONNECTED ((sl_status_t)0x040D) ///< Returned when remote disconnects the connection-oriented channel by sending disconnection request. -#define SL_STATUS_BT_L2CAP_LOCAL_DISCONNECTED ((sl_status_t)0x040E) ///< Returned when local host disconnect the connection-oriented channel by sending disconnection request. -#define SL_STATUS_BT_L2CAP_CID_NOT_EXIST ((sl_status_t)0x040F) ///< Returned when local host did not find a connection-oriented channel with given destination CID. -#define SL_STATUS_BT_L2CAP_LE_DISCONNECTED ((sl_status_t)0x0410) ///< Returned when connection-oriented channel disconnected due to LE connection is dropped. -#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_VIOLATED ((sl_status_t)0x0412) ///< Returned when connection-oriented channel disconnected due to remote end send data even without credit. -#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_CREDIT_OVERFLOWED ((sl_status_t)0x0413) ///< Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. -#define SL_STATUS_BT_L2CAP_NO_FLOW_CONTROL_CREDIT ((sl_status_t)0x0414) ///< Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. -#define SL_STATUS_BT_L2CAP_CONNECTION_REQUEST_TIMEOUT ((sl_status_t)0x0415) ///< Returned when connection-oriented channel has not received connection response message within maximum timeout. -#define SL_STATUS_BT_L2CAP_INVALID_CID ((sl_status_t)0x0416) ///< Returned when local host received a connection-oriented channel connection response with an invalid destination CID. -#define SL_STATUS_BT_L2CAP_WRONG_STATE ((sl_status_t)0x0417) ///< Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. -#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full -#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found -#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level -#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed. - -// Bluetooth controller status codes -#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled. -#define SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE ((sl_status_t)0x1005) ///< Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key -#define SL_STATUS_BT_CTRL_PIN_OR_KEY_MISSING ((sl_status_t)0x1006) ///< Pairing failed because of missing PIN, or authentication failed because of missing Key -#define SL_STATUS_BT_CTRL_MEMORY_CAPACITY_EXCEEDED ((sl_status_t)0x1007) ///< Controller is out of memory. -#define SL_STATUS_BT_CTRL_CONNECTION_TIMEOUT ((sl_status_t)0x1008) ///< Link supervision timeout has expired. -#define SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x1009) ///< Controller is at limit of connections it can support. -#define SL_STATUS_BT_CTRL_SYNCHRONOUS_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x100A) ///< The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. -#define SL_STATUS_BT_CTRL_ACL_CONNECTION_ALREADY_EXISTS ((sl_status_t)0x100B) ///< The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. -#define SL_STATUS_BT_CTRL_COMMAND_DISALLOWED ((sl_status_t)0x100C) ///< Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES ((sl_status_t)0x100D) ///< The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS ((sl_status_t)0x100E) ///< The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR ((sl_status_t)0x100F) ///< The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. -#define SL_STATUS_BT_CTRL_CONNECTION_ACCEPT_TIMEOUT_EXCEEDED ((sl_status_t)0x1010) ///< The Connection Accept Timeout has been exceeded for this connection attempt. -#define SL_STATUS_BT_CTRL_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE ((sl_status_t)0x1011) ///< A feature or parameter value in the HCI command is not supported. -#define SL_STATUS_BT_CTRL_INVALID_COMMAND_PARAMETERS ((sl_status_t)0x1012) ///< Command contained invalid parameters. -#define SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED ((sl_status_t)0x1013) ///< User on the remote device terminated the connection. -#define SL_STATUS_BT_CTRL_REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES ((sl_status_t)0x1014) ///< The remote device terminated the connection because of low resources -#define SL_STATUS_BT_CTRL_REMOTE_POWERING_OFF ((sl_status_t)0x1015) ///< Remote Device Terminated Connection due to Power Off -#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST ((sl_status_t)0x1016) ///< Local device terminated the connection. -#define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. -#define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing -#define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. -#define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. -#define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. -#define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. -#define SL_STATUS_BT_CTRL_ENCRYPTION_MODE_NOT_ACCEPTABLE ((sl_status_t)0x1025) ///< The requested encryption mode is not acceptable at this time. -#define SL_STATUS_BT_CTRL_LINK_KEY_CANNOT_BE_CHANGED ((sl_status_t)0x1026) ///< Link key cannot be changed because a fixed unit key is being used. -#define SL_STATUS_BT_CTRL_INSTANT_PASSED ((sl_status_t)0x1028) ///< LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. -#define SL_STATUS_BT_CTRL_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED ((sl_status_t)0x1029) ///< It was not possible to pair as a unit key was requested and it is not supported. -#define SL_STATUS_BT_CTRL_DIFFERENT_TRANSACTION_COLLISION ((sl_status_t)0x102A) ///< LMP transaction was started that collides with an ongoing transaction. -#define SL_STATUS_BT_CTRL_CHANNEL_ASSESSMENT_NOT_SUPPORTED ((sl_status_t)0x102E) ///< The Controller cannot perform channel assessment because it is not supported. -#define SL_STATUS_BT_CTRL_INSUFFICIENT_SECURITY ((sl_status_t)0x102F) ///< The HCI command or LMP PDU sent is only possible on an encrypted link. -#define SL_STATUS_BT_CTRL_PARAMETER_OUT_OF_MANDATORY_RANGE ((sl_status_t)0x1030) ///< A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. -#define SL_STATUS_BT_CTRL_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST ((sl_status_t)0x1037) ///< The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. -#define SL_STATUS_BT_CTRL_HOST_BUSY_PAIRING ((sl_status_t)0x1038) ///< The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation. -#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request. -#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval. -#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. -#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. -#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. -#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. -#define SL_STATUS_BT_CTRL_COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING ((sl_status_t)0x1040) ///< The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. -#define SL_STATUS_BT_CTRL_UNKNOWN_ADVERTISING_IDENTIFIER ((sl_status_t)0x1042) ///< A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. -#define SL_STATUS_BT_CTRL_LIMIT_REACHED ((sl_status_t)0x1043) ///< Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). -#define SL_STATUS_BT_CTRL_OPERATION_CANCELLED_BY_HOST ((sl_status_t)0x1044) ///< A request to the Controller issued by the Host and still pending was successfully canceled. -#define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. -#define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. -#define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. - -// Bluetooth attribute status codes -#define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server -#define SL_STATUS_BT_ATT_READ_NOT_PERMITTED ((sl_status_t)0x1102) ///< The attribute cannot be read -#define SL_STATUS_BT_ATT_WRITE_NOT_PERMITTED ((sl_status_t)0x1103) ///< The attribute cannot be written -#define SL_STATUS_BT_ATT_INVALID_PDU ((sl_status_t)0x1104) ///< The attribute PDU was invalid -#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHENTICATION ((sl_status_t)0x1105) ///< The attribute requires authentication before it can be read or written. -#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client. -#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute -#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written. -#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued -#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range. -#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request -#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient. -#define SL_STATUS_BT_ATT_INVALID_ATT_LENGTH ((sl_status_t)0x110D) ///< The attribute value length is invalid for the operation -#define SL_STATUS_BT_ATT_UNLIKELY_ERROR ((sl_status_t)0x110E) ///< The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. -#define SL_STATUS_BT_ATT_INSUFFICIENT_ENCRYPTION ((sl_status_t)0x110F) ///< The attribute requires encryption before it can be read or written. -#define SL_STATUS_BT_ATT_UNSUPPORTED_GROUP_TYPE ((sl_status_t)0x1110) ///< The attribute type is not a supported grouping attribute as defined by a higher layer specification. -#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request -#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database. -#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed. -#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. -#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions. -#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service. -#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress. -#define SL_STATUS_BT_ATT_OUT_OF_RANGE ((sl_status_t)0x11FF) ///< The attribute value is out of range as defined by a profile or service specification. - -// Bluetooth Security Manager Protocol status codes -#define SL_STATUS_BT_SMP_PASSKEY_ENTRY_FAILED ((sl_status_t)0x1201) ///< The user input of passkey failed, for example, the user cancelled the operation -#define SL_STATUS_BT_SMP_OOB_NOT_AVAILABLE ((sl_status_t)0x1202) ///< Out of Band data is not available for authentication -#define SL_STATUS_BT_SMP_AUTHENTICATION_REQUIREMENTS ((sl_status_t)0x1203) ///< The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices -#define SL_STATUS_BT_SMP_CONFIRM_VALUE_FAILED ((sl_status_t)0x1204) ///< The confirm value does not match the calculated compare value -#define SL_STATUS_BT_SMP_PAIRING_NOT_SUPPORTED ((sl_status_t)0x1205) ///< Pairing is not supported by the device -#define SL_STATUS_BT_SMP_ENCRYPTION_KEY_SIZE ((sl_status_t)0x1206) ///< The resultant encryption key size is insufficient for the security requirements of this device -#define SL_STATUS_BT_SMP_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1207) ///< The SMP command received is not supported on this device -#define SL_STATUS_BT_SMP_UNSPECIFIED_REASON ((sl_status_t)0x1208) ///< Pairing failed due to an unspecified reason -#define SL_STATUS_BT_SMP_REPEATED_ATTEMPTS ((sl_status_t)0x1209) ///< Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request -#define SL_STATUS_BT_SMP_INVALID_PARAMETERS ((sl_status_t)0x120A) ///< The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. -#define SL_STATUS_BT_SMP_DHKEY_CHECK_FAILED ((sl_status_t)0x120B) ///< Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. -#define SL_STATUS_BT_SMP_NUMERIC_COMPARISON_FAILED ((sl_status_t)0x120C) ///< Indicates that the confirm values in the numeric comparison protocol do not match. -#define SL_STATUS_BT_SMP_BREDR_PAIRING_IN_PROGRESS ((sl_status_t)0x120D) ///< Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. -#define SL_STATUS_BT_SMP_CROSS_TRANSPORT_KEY_DERIVATION_GENERATION_NOT_ALLOWED ((sl_status_t)0x120E) ///< Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. -#define SL_STATUS_BT_SMP_KEY_REJECTED ((sl_status_t)0x120F) ///< Indicates that the device chose not to accept a distributed key. - -// Bluetooth Mesh status codes -#define SL_STATUS_BT_MESH_ALREADY_EXISTS ((sl_status_t)0x0501) ///< Returned when trying to add a key or some other unique resource with an ID which already exists -#define SL_STATUS_BT_MESH_DOES_NOT_EXIST ((sl_status_t)0x0502) ///< Returned when trying to manipulate a key or some other resource with an ID which does not exist -#define SL_STATUS_BT_MESH_LIMIT_REACHED ((sl_status_t)0x0503) ///< Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached -#define SL_STATUS_BT_MESH_INVALID_ADDRESS ((sl_status_t)0x0504) ///< Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device -#define SL_STATUS_BT_MESH_MALFORMED_DATA ((sl_status_t)0x0505) ///< In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data -#define SL_STATUS_BT_MESH_ALREADY_INITIALIZED ((sl_status_t)0x0506) ///< An attempt was made to initialize a subsystem that was already initialized. -#define SL_STATUS_BT_MESH_NOT_INITIALIZED ((sl_status_t)0x0507) ///< An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. -#define SL_STATUS_BT_MESH_NO_FRIEND_OFFER ((sl_status_t)0x0508) ///< Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. -#define SL_STATUS_BT_MESH_PROV_LINK_CLOSED ((sl_status_t)0x0509) ///< Provisioning link was unexpectedly closed before provisioning was complete. -#define SL_STATUS_BT_MESH_PROV_INVALID_PDU ((sl_status_t)0x050A) ///< An unrecognized provisioning PDU was received. -#define SL_STATUS_BT_MESH_PROV_INVALID_PDU_FORMAT ((sl_status_t)0x050B) ///< A provisioning PDU with wrong length or containing field values that are out of bounds was received. -#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_PDU ((sl_status_t)0x050C) ///< An unexpected (out of sequence) provisioning PDU was received. -#define SL_STATUS_BT_MESH_PROV_CONFIRMATION_FAILED ((sl_status_t)0x050D) ///< The computed confirmation value did not match the expected value. -#define SL_STATUS_BT_MESH_PROV_OUT_OF_RESOURCES ((sl_status_t)0x050E) ///< Provisioning could not be continued due to insufficient resources. -#define SL_STATUS_BT_MESH_PROV_DECRYPTION_FAILED ((sl_status_t)0x050F) ///< The provisioning data block could not be decrypted. -#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_ERROR ((sl_status_t)0x0510) ///< An unexpected error happened during provisioning. -#define SL_STATUS_BT_MESH_PROV_CANNOT_ASSIGN_ADDR ((sl_status_t)0x0511) ///< Device could not assign unicast addresses to all of its elements. -#define SL_STATUS_BT_MESH_ADDRESS_TEMPORARILY_UNAVAILABLE ((sl_status_t)0x0512) ///< Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. -#define SL_STATUS_BT_MESH_ADDRESS_ALREADY_USED ((sl_status_t)0x0513) ///< Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. -#define SL_STATUS_BT_MESH_PUBLISH_NOT_CONFIGURED ((sl_status_t)0x0514) ///< Application key or publish address are not set -#define SL_STATUS_BT_MESH_APP_KEY_NOT_BOUND ((sl_status_t)0x0515) ///< Application key is not bound to a model - -// Bluetooth Mesh foundation status codes -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_ADDRESS ((sl_status_t)0x1301) ///< Returned when address in request was not valid -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_MODEL ((sl_status_t)0x1302) ///< Returned when model identified is not found for a given element -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_APP_KEY ((sl_status_t)0x1303) ///< Returned when the key identified by AppKeyIndex is not stored in the node -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_NET_KEY ((sl_status_t)0x1304) ///< Returned when the key identified by NetKeyIndex is not stored in the node -#define SL_STATUS_BT_MESH_FOUNDATION_INSUFFICIENT_RESOURCES ((sl_status_t)0x1305) ///< Returned when The node cannot serve the request due to insufficient resources -#define SL_STATUS_BT_MESH_FOUNDATION_KEY_INDEX_EXISTS ((sl_status_t)0x1306) ///< Returned when the key identified is already stored in the node and the new NetKey value is different -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_PUBLISH_PARAMS ((sl_status_t)0x1307) ///< Returned when the model does not support the publish mechanism -#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUBSCRIBE_MODEL ((sl_status_t)0x1308) ///< Returned when the model does not support the subscribe mechanism -#define SL_STATUS_BT_MESH_FOUNDATION_STORAGE_FAILURE ((sl_status_t)0x1309) ///< Returned when storing of the requested parameters failed -#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUPPORTED ((sl_status_t)0x130A) ///< Returned when requested setting is not supported -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_UPDATE ((sl_status_t)0x130B) ///< Returned when the requested update operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_REMOVE ((sl_status_t)0x130C) ///< Returned when the requested delete operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_BIND ((sl_status_t)0x130D) ///< Returned when the requested bind operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_TEMPORARILY_UNABLE ((sl_status_t)0x130E) ///< Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_SET ((sl_status_t)0x130F) ///< Returned when the requested state cannot be set -#define SL_STATUS_BT_MESH_FOUNDATION_UNSPECIFIED ((sl_status_t)0x1310) ///< Returned when an unspecified error took place -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_BINDING ((sl_status_t)0x1311) ///< Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update - -// ----------------------------------------------------------------------------- -// Wi-Fi Errors - -#define SL_STATUS_WIFI_INVALID_KEY ((sl_status_t)0x0B01) ///< Invalid firmware keyset -#define SL_STATUS_WIFI_FIRMWARE_DOWNLOAD_TIMEOUT ((sl_status_t)0x0B02) ///< The firmware download took too long -#define SL_STATUS_WIFI_UNSUPPORTED_MESSAGE_ID ((sl_status_t)0x0B03) ///< Unknown request ID or wrong interface ID used -#define SL_STATUS_WIFI_WARNING ((sl_status_t)0x0B04) ///< The request is successful but some parameters have been ignored -#define SL_STATUS_WIFI_NO_PACKET_TO_RECEIVE ((sl_status_t)0x0B05) ///< No Packets waiting to be received -#define SL_STATUS_WIFI_SLEEP_GRANTED ((sl_status_t)0x0B08) ///< The sleep mode is granted -#define SL_STATUS_WIFI_SLEEP_NOT_GRANTED ((sl_status_t)0x0B09) ///< The WFx does not go back to sleep -#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ERROR ((sl_status_t)0x0B10) ///< The SecureLink MAC key was not found -#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ALREADY_BURNED ((sl_status_t)0x0B11) ///< The SecureLink MAC key is already installed in OTP -#define SL_STATUS_WIFI_SECURE_LINK_RAM_MODE_NOT_ALLOWED ((sl_status_t)0x0B12) ///< The SecureLink MAC key cannot be installed in RAM -#define SL_STATUS_WIFI_SECURE_LINK_FAILED_UNKNOWN_MODE ((sl_status_t)0x0B13) ///< The SecureLink MAC key installation failed -#define SL_STATUS_WIFI_SECURE_LINK_EXCHANGE_FAILED ((sl_status_t)0x0B14) ///< SecureLink key (re)negotiation failed -#define SL_STATUS_WIFI_WRONG_STATE ((sl_status_t)0x0B18) ///< The device is in an inappropriate state to perform the request -#define SL_STATUS_WIFI_CHANNEL_NOT_ALLOWED ((sl_status_t)0x0B19) ///< The request failed due to regulatory limitations -#define SL_STATUS_WIFI_NO_MATCHING_AP ((sl_status_t)0x0B1A) ///< The connection request failed because no suitable AP was found -#define SL_STATUS_WIFI_CONNECTION_ABORTED ((sl_status_t)0x0B1B) ///< The connection request was aborted by host -#define SL_STATUS_WIFI_CONNECTION_TIMEOUT ((sl_status_t)0x0B1C) ///< The connection request failed because of a timeout -#define SL_STATUS_WIFI_CONNECTION_REJECTED_BY_AP ((sl_status_t)0x0B1D) ///< The connection request failed because the AP rejected the device -#define SL_STATUS_WIFI_CONNECTION_AUTH_FAILURE ((sl_status_t)0x0B1E) ///< The connection request failed because the WPA handshake did not complete successfully -#define SL_STATUS_WIFI_RETRY_EXCEEDED ((sl_status_t)0x0B1F) ///< The request failed because the retry limit was exceeded -#define SL_STATUS_WIFI_TX_LIFETIME_EXCEEDED ((sl_status_t)0x0B20) ///< The request failed because the MSDU life time was exceeded - -// ----------------------------------------------------------------------------- -// MVP Driver and MVP Math status codes -#define SL_STATUS_COMPUTE_DRIVER_FAULT ((sl_status_t)0x1501) ///< Critical fault -#define SL_STATUS_COMPUTE_DRIVER_ALU_NAN ((sl_status_t)0x1502) ///< ALU operation output NaN -#define SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW ((sl_status_t)0x1503) ///< ALU numeric overflow -#define SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW ((sl_status_t)0x1504) ///< ALU numeric underflow -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW ((sl_status_t)0x1505) ///< Overflow during array store -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW ((sl_status_t)0x1506) ///< Underflow during array store conversion -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion - -#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered -#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered -#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow -#define SL_STATUS_COMPUTE_MATH_UNDERFLOW ((sl_status_t)0x1515) ///< MATH numeric underflow - -// ----------------------------------------------------------------------------- -// Data Types -/** @brief define global status variable. */ -typedef uint32_t sl_status_t; - -// ----------------------------------------------------------------------------- -// Functions - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************************************** - * sl_status_get_string_n() - * - * @brief Get a copy of the status string associated to the status code passed, up to - * 'buffer_length' length, if the string associated to the status code is enabled. If not, - * the error code number, in hex, prefixed by "SL_STATUS_" will be copied in the buffer - * instead. - * For example, the buffer would either contain "SL_STATUS_FAIL" if that status string is - * enabled, or "SL_STATUS_0x0001" if the string is disabled, as SL_STATUS_FAIL's - * value is 0x0001. - * - * @param status The status code from which to obtain the status string. - * - * @param buffer Pointer to a buffer in which the status string will be copied. A terminating - * null-character will be appended after the copied status string. - * - * @param buffer_length Maximum number of characters that can be written in the buffer, including the - * terminating null-character. If the status string would be longer than the - * available length, it will be truncated and a null-terminating character will - * be the last character contained in the buffer. - * - * @return The number of characters that would have been written if the buffer_length had been - * sufficiently large, not counting the terminating null character. - * If the status code is invalid, 0 or a negative number is returned. - * Notice that only when this returned value is strictly positive and less than - * buffer_length, the status string has been completely written in the buffer. - *******************************************************************************************************/ -int32_t sl_status_get_string_n(sl_status_t status, char *buffer, uint32_t buffer_length); - -/******************************************************************************************************** - * sl_status_print() - * - * @brief Print, through printf, the string associated to the passed status code. If the string - * associated to the status code is enabled, the status string will be printed, for example - * "SL_STATUS_OK". If the string associated to the status code is disabled, the status number, - * in hex, prefixed by "SL_STATUS_" will be printed instead, for example "SL_STATUS_0x0000", - * as SL_STATUS_OK's value is 0x0000. - * - * @param status The status code of which to print the status string. - *******************************************************************************************************/ -void sl_status_print(sl_status_t status); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup status) */ - -#endif /* SL_STATUS_H */ +/******************************************************************************* + * @file + * @brief SL Status Codes. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_STATUS_H +#define SL_STATUS_H + +#include + +/******************************************************************************* + * @addtogroup status Status Codes + * @details Status Codes contains error and status code definitions used by GSDK + * software components and stacks. This module also provides routines to + * read the string linked with the error and status codes. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Space Defines + +#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask. + +#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space. + +#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space. +#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space. +#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space. + +#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space. +#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space. +#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space. +#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space. +#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space. +#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space. +#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space. +#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space. +#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space. +#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space. + +#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space. +#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space. + +#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space. +#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space. +#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space. +#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space. + +#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space. + +#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space. + +// ----------------------------------------------------------------------------- +// Status Defines + +// ----------------------------------------------------------------------------- +// Generic Errors + +#define SL_STATUS_OK ((sl_status_t)0x0000) ///< No error. +#define SL_STATUS_FAIL ((sl_status_t)0x0001) ///< Generic error. + +// State Errors +#define SL_STATUS_INVALID_STATE ((sl_status_t)0x0002) ///< Generic invalid state error. +#define SL_STATUS_NOT_READY ((sl_status_t)0x0003) ///< Module is not ready for requested operation. +#define SL_STATUS_BUSY ((sl_status_t)0x0004) ///< Module is busy and cannot carry out requested operation. +#define SL_STATUS_IN_PROGRESS ((sl_status_t)0x0005) ///< Operation is in progress and not yet complete (pass or fail). +#define SL_STATUS_ABORT ((sl_status_t)0x0006) ///< Operation aborted. +#define SL_STATUS_TIMEOUT ((sl_status_t)0x0007) ///< Operation timed out. +#define SL_STATUS_PERMISSION ((sl_status_t)0x0008) ///< Operation not allowed per permissions. +#define SL_STATUS_WOULD_BLOCK ((sl_status_t)0x0009) ///< Non-blocking operation would block. +#define SL_STATUS_IDLE ((sl_status_t)0x000A) ///< Operation/module is Idle, cannot carry requested operation. +#define SL_STATUS_IS_WAITING ((sl_status_t)0x000B) ///< Operation cannot be done while construct is waiting. +#define SL_STATUS_NONE_WAITING ((sl_status_t)0x000C) ///< No task/construct waiting/pending for that action/event. +#define SL_STATUS_SUSPENDED ((sl_status_t)0x000D) ///< Operation cannot be done while construct is suspended. +#define SL_STATUS_NOT_AVAILABLE ((sl_status_t)0x000E) ///< Feature not available due to software configuration. +#define SL_STATUS_NOT_SUPPORTED ((sl_status_t)0x000F) ///< Feature not supported. +#define SL_STATUS_INITIALIZATION ((sl_status_t)0x0010) ///< Initialization failed. +#define SL_STATUS_NOT_INITIALIZED ((sl_status_t)0x0011) ///< Module has not been initialized. +#define SL_STATUS_ALREADY_INITIALIZED ((sl_status_t)0x0012) ///< Module has already been initialized. +#define SL_STATUS_DELETED ((sl_status_t)0x0013) ///< Object/construct has been deleted. +#define SL_STATUS_ISR ((sl_status_t)0x0014) ///< Illegal call from ISR. +#define SL_STATUS_NETWORK_UP ((sl_status_t)0x0015) ///< Illegal call because network is up. +#define SL_STATUS_NETWORK_DOWN ((sl_status_t)0x0016) ///< Illegal call because network is down. +#define SL_STATUS_NOT_JOINED ((sl_status_t)0x0017) ///< Failure due to not being joined in a network. +#define SL_STATUS_NO_BEACONS ((sl_status_t)0x0018) ///< Invalid operation as there are no beacons. + +// Allocation/ownership Errors +#define SL_STATUS_ALLOCATION_FAILED ((sl_status_t)0x0019) ///< Generic allocation error. +#define SL_STATUS_NO_MORE_RESOURCE ((sl_status_t)0x001A) ///< No more resource available to perform the operation. +#define SL_STATUS_EMPTY ((sl_status_t)0x001B) ///< Item/list/queue is empty. +#define SL_STATUS_FULL ((sl_status_t)0x001C) ///< Item/list/queue is full. +#define SL_STATUS_WOULD_OVERFLOW ((sl_status_t)0x001D) ///< Item would overflow. +#define SL_STATUS_HAS_OVERFLOWED ((sl_status_t)0x001E) ///< Item/list/queue has been overflowed. +#define SL_STATUS_OWNERSHIP ((sl_status_t)0x001F) ///< Generic ownership error. +#define SL_STATUS_IS_OWNER ((sl_status_t)0x0020) ///< Already/still owning resource. + +// Invalid Parameters Errors +#define SL_STATUS_INVALID_PARAMETER ((sl_status_t)0x0021) ///< Generic invalid argument or consequence of invalid argument. +#define SL_STATUS_NULL_POINTER ((sl_status_t)0x0022) ///< Invalid null pointer received as argument. +#define SL_STATUS_INVALID_CONFIGURATION ((sl_status_t)0x0023) ///< Invalid configuration provided. +#define SL_STATUS_INVALID_MODE ((sl_status_t)0x0024) ///< Invalid mode. +#define SL_STATUS_INVALID_HANDLE ((sl_status_t)0x0025) ///< Invalid handle. +#define SL_STATUS_INVALID_TYPE ((sl_status_t)0x0026) ///< Invalid type for operation. +#define SL_STATUS_INVALID_INDEX ((sl_status_t)0x0027) ///< Invalid index. +#define SL_STATUS_INVALID_RANGE ((sl_status_t)0x0028) ///< Invalid range. +#define SL_STATUS_INVALID_KEY ((sl_status_t)0x0029) ///< Invalid key. +#define SL_STATUS_INVALID_CREDENTIALS ((sl_status_t)0x002A) ///< Invalid credentials. +#define SL_STATUS_INVALID_COUNT ((sl_status_t)0x002B) ///< Invalid count. +#define SL_STATUS_INVALID_SIGNATURE ((sl_status_t)0x002C) ///< Invalid signature / verification failed. +#define SL_STATUS_NOT_FOUND ((sl_status_t)0x002D) ///< Item could not be found. +#define SL_STATUS_ALREADY_EXISTS ((sl_status_t)0x002E) ///< Item already exists. + +// IO/Communication Errors +#define SL_STATUS_IO ((sl_status_t)0x002F) ///< Generic I/O failure. +#define SL_STATUS_IO_TIMEOUT ((sl_status_t)0x0030) ///< I/O failure due to timeout. +#define SL_STATUS_TRANSMIT ((sl_status_t)0x0031) ///< Generic transmission error. +#define SL_STATUS_TRANSMIT_UNDERFLOW ((sl_status_t)0x0032) ///< Transmit underflowed. +#define SL_STATUS_TRANSMIT_INCOMPLETE ((sl_status_t)0x0033) ///< Transmit is incomplete. +#define SL_STATUS_TRANSMIT_BUSY ((sl_status_t)0x0034) ///< Transmit is busy. +#define SL_STATUS_RECEIVE ((sl_status_t)0x0035) ///< Generic reception error. +#define SL_STATUS_OBJECT_READ ((sl_status_t)0x0036) ///< Failed to read on/via given object. +#define SL_STATUS_OBJECT_WRITE ((sl_status_t)0x0037) ///< Failed to write on/via given object. +#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long. + +// EEPROM/Flash Errors +#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch. +#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch. +#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited. +#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed. +#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed. +#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed. + +// MAC Errors +#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data. +#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received. +#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout. +#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type. +#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type. +#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure. + +// CLI_STORAGE Errors +#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM + +// Security status codes +#define SL_STATUS_SECURITY_IMAGE_CHECKSUM_ERROR ((sl_status_t)0x0046) ///< Image checksum is not valid. +#define SL_STATUS_SECURITY_DECRYPT_ERROR ((sl_status_t)0x0047) ///< Decryption failed + +// Command status codes +#define SL_STATUS_COMMAND_IS_INVALID ((sl_status_t)0x0048) ///< Command was not recognized +#define SL_STATUS_COMMAND_TOO_LONG ((sl_status_t)0x0049) ///< Command or parameter maximum length exceeded +#define SL_STATUS_COMMAND_INCOMPLETE ((sl_status_t)0x004A) ///< Data received does not form a complete command + +// Misc Errors +#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address + +// Unified MAC Errors +#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure. + +// Scan errors +#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning. +#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type. +#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask. +#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration. + +// Bluetooth status codes +#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. +#define SL_STATUS_BT_UNSPECIFIED ((sl_status_t)0x0403) ///< Unspecified error +#define SL_STATUS_BT_HARDWARE ((sl_status_t)0x0404) ///< Hardware failure +#define SL_STATUS_BT_NO_BONDING ((sl_status_t)0x0406) ///< The bonding does not exist. +#define SL_STATUS_BT_CRYPTO ((sl_status_t)0x0407) ///< Error using crypto functions +#define SL_STATUS_BT_DATA_CORRUPTED ((sl_status_t)0x0408) ///< Data was corrupted. +#define SL_STATUS_BT_INVALID_SYNC_HANDLE ((sl_status_t)0x040A) ///< Invalid periodic advertising sync handle +#define SL_STATUS_BT_INVALID_MODULE_ACTION ((sl_status_t)0x040B) ///< Bluetooth cannot be used on this hardware +#define SL_STATUS_BT_RADIO ((sl_status_t)0x040C) ///< Error received from radio +#define SL_STATUS_BT_L2CAP_REMOTE_DISCONNECTED ((sl_status_t)0x040D) ///< Returned when remote disconnects the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_LOCAL_DISCONNECTED ((sl_status_t)0x040E) ///< Returned when local host disconnect the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_CID_NOT_EXIST ((sl_status_t)0x040F) ///< Returned when local host did not find a connection-oriented channel with given destination CID. +#define SL_STATUS_BT_L2CAP_LE_DISCONNECTED ((sl_status_t)0x0410) ///< Returned when connection-oriented channel disconnected due to LE connection is dropped. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_VIOLATED ((sl_status_t)0x0412) ///< Returned when connection-oriented channel disconnected due to remote end send data even without credit. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_CREDIT_OVERFLOWED ((sl_status_t)0x0413) ///< Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. +#define SL_STATUS_BT_L2CAP_NO_FLOW_CONTROL_CREDIT ((sl_status_t)0x0414) ///< Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. +#define SL_STATUS_BT_L2CAP_CONNECTION_REQUEST_TIMEOUT ((sl_status_t)0x0415) ///< Returned when connection-oriented channel has not received connection response message within maximum timeout. +#define SL_STATUS_BT_L2CAP_INVALID_CID ((sl_status_t)0x0416) ///< Returned when local host received a connection-oriented channel connection response with an invalid destination CID. +#define SL_STATUS_BT_L2CAP_WRONG_STATE ((sl_status_t)0x0417) ///< Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. +#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full +#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found +#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level +#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed. + +// Bluetooth controller status codes +#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled. +#define SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE ((sl_status_t)0x1005) ///< Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key +#define SL_STATUS_BT_CTRL_PIN_OR_KEY_MISSING ((sl_status_t)0x1006) ///< Pairing failed because of missing PIN, or authentication failed because of missing Key +#define SL_STATUS_BT_CTRL_MEMORY_CAPACITY_EXCEEDED ((sl_status_t)0x1007) ///< Controller is out of memory. +#define SL_STATUS_BT_CTRL_CONNECTION_TIMEOUT ((sl_status_t)0x1008) ///< Link supervision timeout has expired. +#define SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x1009) ///< Controller is at limit of connections it can support. +#define SL_STATUS_BT_CTRL_SYNCHRONOUS_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x100A) ///< The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. +#define SL_STATUS_BT_CTRL_ACL_CONNECTION_ALREADY_EXISTS ((sl_status_t)0x100B) ///< The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. +#define SL_STATUS_BT_CTRL_COMMAND_DISALLOWED ((sl_status_t)0x100C) ///< Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES ((sl_status_t)0x100D) ///< The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS ((sl_status_t)0x100E) ///< The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR ((sl_status_t)0x100F) ///< The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. +#define SL_STATUS_BT_CTRL_CONNECTION_ACCEPT_TIMEOUT_EXCEEDED ((sl_status_t)0x1010) ///< The Connection Accept Timeout has been exceeded for this connection attempt. +#define SL_STATUS_BT_CTRL_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE ((sl_status_t)0x1011) ///< A feature or parameter value in the HCI command is not supported. +#define SL_STATUS_BT_CTRL_INVALID_COMMAND_PARAMETERS ((sl_status_t)0x1012) ///< Command contained invalid parameters. +#define SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED ((sl_status_t)0x1013) ///< User on the remote device terminated the connection. +#define SL_STATUS_BT_CTRL_REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES ((sl_status_t)0x1014) ///< The remote device terminated the connection because of low resources +#define SL_STATUS_BT_CTRL_REMOTE_POWERING_OFF ((sl_status_t)0x1015) ///< Remote Device Terminated Connection due to Power Off +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST ((sl_status_t)0x1016) ///< Local device terminated the connection. +#define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. +#define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing +#define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. +#define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. +#define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. +#define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. +#define SL_STATUS_BT_CTRL_ENCRYPTION_MODE_NOT_ACCEPTABLE ((sl_status_t)0x1025) ///< The requested encryption mode is not acceptable at this time. +#define SL_STATUS_BT_CTRL_LINK_KEY_CANNOT_BE_CHANGED ((sl_status_t)0x1026) ///< Link key cannot be changed because a fixed unit key is being used. +#define SL_STATUS_BT_CTRL_INSTANT_PASSED ((sl_status_t)0x1028) ///< LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. +#define SL_STATUS_BT_CTRL_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED ((sl_status_t)0x1029) ///< It was not possible to pair as a unit key was requested and it is not supported. +#define SL_STATUS_BT_CTRL_DIFFERENT_TRANSACTION_COLLISION ((sl_status_t)0x102A) ///< LMP transaction was started that collides with an ongoing transaction. +#define SL_STATUS_BT_CTRL_CHANNEL_ASSESSMENT_NOT_SUPPORTED ((sl_status_t)0x102E) ///< The Controller cannot perform channel assessment because it is not supported. +#define SL_STATUS_BT_CTRL_INSUFFICIENT_SECURITY ((sl_status_t)0x102F) ///< The HCI command or LMP PDU sent is only possible on an encrypted link. +#define SL_STATUS_BT_CTRL_PARAMETER_OUT_OF_MANDATORY_RANGE ((sl_status_t)0x1030) ///< A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. +#define SL_STATUS_BT_CTRL_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST ((sl_status_t)0x1037) ///< The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. +#define SL_STATUS_BT_CTRL_HOST_BUSY_PAIRING ((sl_status_t)0x1038) ///< The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation. +#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request. +#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval. +#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. +#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. +#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. +#define SL_STATUS_BT_CTRL_COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING ((sl_status_t)0x1040) ///< The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. +#define SL_STATUS_BT_CTRL_UNKNOWN_ADVERTISING_IDENTIFIER ((sl_status_t)0x1042) ///< A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. +#define SL_STATUS_BT_CTRL_LIMIT_REACHED ((sl_status_t)0x1043) ///< Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). +#define SL_STATUS_BT_CTRL_OPERATION_CANCELLED_BY_HOST ((sl_status_t)0x1044) ///< A request to the Controller issued by the Host and still pending was successfully canceled. +#define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. +#define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. +#define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. + +// Bluetooth attribute status codes +#define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server +#define SL_STATUS_BT_ATT_READ_NOT_PERMITTED ((sl_status_t)0x1102) ///< The attribute cannot be read +#define SL_STATUS_BT_ATT_WRITE_NOT_PERMITTED ((sl_status_t)0x1103) ///< The attribute cannot be written +#define SL_STATUS_BT_ATT_INVALID_PDU ((sl_status_t)0x1104) ///< The attribute PDU was invalid +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHENTICATION ((sl_status_t)0x1105) ///< The attribute requires authentication before it can be read or written. +#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client. +#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written. +#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued +#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range. +#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient. +#define SL_STATUS_BT_ATT_INVALID_ATT_LENGTH ((sl_status_t)0x110D) ///< The attribute value length is invalid for the operation +#define SL_STATUS_BT_ATT_UNLIKELY_ERROR ((sl_status_t)0x110E) ///< The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENCRYPTION ((sl_status_t)0x110F) ///< The attribute requires encryption before it can be read or written. +#define SL_STATUS_BT_ATT_UNSUPPORTED_GROUP_TYPE ((sl_status_t)0x1110) ///< The attribute type is not a supported grouping attribute as defined by a higher layer specification. +#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request +#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database. +#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed. +#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. +#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions. +#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service. +#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress. +#define SL_STATUS_BT_ATT_OUT_OF_RANGE ((sl_status_t)0x11FF) ///< The attribute value is out of range as defined by a profile or service specification. + +// Bluetooth Security Manager Protocol status codes +#define SL_STATUS_BT_SMP_PASSKEY_ENTRY_FAILED ((sl_status_t)0x1201) ///< The user input of passkey failed, for example, the user cancelled the operation +#define SL_STATUS_BT_SMP_OOB_NOT_AVAILABLE ((sl_status_t)0x1202) ///< Out of Band data is not available for authentication +#define SL_STATUS_BT_SMP_AUTHENTICATION_REQUIREMENTS ((sl_status_t)0x1203) ///< The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices +#define SL_STATUS_BT_SMP_CONFIRM_VALUE_FAILED ((sl_status_t)0x1204) ///< The confirm value does not match the calculated compare value +#define SL_STATUS_BT_SMP_PAIRING_NOT_SUPPORTED ((sl_status_t)0x1205) ///< Pairing is not supported by the device +#define SL_STATUS_BT_SMP_ENCRYPTION_KEY_SIZE ((sl_status_t)0x1206) ///< The resultant encryption key size is insufficient for the security requirements of this device +#define SL_STATUS_BT_SMP_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1207) ///< The SMP command received is not supported on this device +#define SL_STATUS_BT_SMP_UNSPECIFIED_REASON ((sl_status_t)0x1208) ///< Pairing failed due to an unspecified reason +#define SL_STATUS_BT_SMP_REPEATED_ATTEMPTS ((sl_status_t)0x1209) ///< Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request +#define SL_STATUS_BT_SMP_INVALID_PARAMETERS ((sl_status_t)0x120A) ///< The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. +#define SL_STATUS_BT_SMP_DHKEY_CHECK_FAILED ((sl_status_t)0x120B) ///< Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. +#define SL_STATUS_BT_SMP_NUMERIC_COMPARISON_FAILED ((sl_status_t)0x120C) ///< Indicates that the confirm values in the numeric comparison protocol do not match. +#define SL_STATUS_BT_SMP_BREDR_PAIRING_IN_PROGRESS ((sl_status_t)0x120D) ///< Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. +#define SL_STATUS_BT_SMP_CROSS_TRANSPORT_KEY_DERIVATION_GENERATION_NOT_ALLOWED ((sl_status_t)0x120E) ///< Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. +#define SL_STATUS_BT_SMP_KEY_REJECTED ((sl_status_t)0x120F) ///< Indicates that the device chose not to accept a distributed key. + +// Bluetooth Mesh status codes +#define SL_STATUS_BT_MESH_ALREADY_EXISTS ((sl_status_t)0x0501) ///< Returned when trying to add a key or some other unique resource with an ID which already exists +#define SL_STATUS_BT_MESH_DOES_NOT_EXIST ((sl_status_t)0x0502) ///< Returned when trying to manipulate a key or some other resource with an ID which does not exist +#define SL_STATUS_BT_MESH_LIMIT_REACHED ((sl_status_t)0x0503) ///< Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached +#define SL_STATUS_BT_MESH_INVALID_ADDRESS ((sl_status_t)0x0504) ///< Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device +#define SL_STATUS_BT_MESH_MALFORMED_DATA ((sl_status_t)0x0505) ///< In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data +#define SL_STATUS_BT_MESH_ALREADY_INITIALIZED ((sl_status_t)0x0506) ///< An attempt was made to initialize a subsystem that was already initialized. +#define SL_STATUS_BT_MESH_NOT_INITIALIZED ((sl_status_t)0x0507) ///< An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. +#define SL_STATUS_BT_MESH_NO_FRIEND_OFFER ((sl_status_t)0x0508) ///< Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. +#define SL_STATUS_BT_MESH_PROV_LINK_CLOSED ((sl_status_t)0x0509) ///< Provisioning link was unexpectedly closed before provisioning was complete. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU ((sl_status_t)0x050A) ///< An unrecognized provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU_FORMAT ((sl_status_t)0x050B) ///< A provisioning PDU with wrong length or containing field values that are out of bounds was received. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_PDU ((sl_status_t)0x050C) ///< An unexpected (out of sequence) provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_CONFIRMATION_FAILED ((sl_status_t)0x050D) ///< The computed confirmation value did not match the expected value. +#define SL_STATUS_BT_MESH_PROV_OUT_OF_RESOURCES ((sl_status_t)0x050E) ///< Provisioning could not be continued due to insufficient resources. +#define SL_STATUS_BT_MESH_PROV_DECRYPTION_FAILED ((sl_status_t)0x050F) ///< The provisioning data block could not be decrypted. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_ERROR ((sl_status_t)0x0510) ///< An unexpected error happened during provisioning. +#define SL_STATUS_BT_MESH_PROV_CANNOT_ASSIGN_ADDR ((sl_status_t)0x0511) ///< Device could not assign unicast addresses to all of its elements. +#define SL_STATUS_BT_MESH_ADDRESS_TEMPORARILY_UNAVAILABLE ((sl_status_t)0x0512) ///< Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. +#define SL_STATUS_BT_MESH_ADDRESS_ALREADY_USED ((sl_status_t)0x0513) ///< Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. +#define SL_STATUS_BT_MESH_PUBLISH_NOT_CONFIGURED ((sl_status_t)0x0514) ///< Application key or publish address are not set +#define SL_STATUS_BT_MESH_APP_KEY_NOT_BOUND ((sl_status_t)0x0515) ///< Application key is not bound to a model + +// Bluetooth Mesh foundation status codes +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_ADDRESS ((sl_status_t)0x1301) ///< Returned when address in request was not valid +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_MODEL ((sl_status_t)0x1302) ///< Returned when model identified is not found for a given element +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_APP_KEY ((sl_status_t)0x1303) ///< Returned when the key identified by AppKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_NET_KEY ((sl_status_t)0x1304) ///< Returned when the key identified by NetKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INSUFFICIENT_RESOURCES ((sl_status_t)0x1305) ///< Returned when The node cannot serve the request due to insufficient resources +#define SL_STATUS_BT_MESH_FOUNDATION_KEY_INDEX_EXISTS ((sl_status_t)0x1306) ///< Returned when the key identified is already stored in the node and the new NetKey value is different +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_PUBLISH_PARAMS ((sl_status_t)0x1307) ///< Returned when the model does not support the publish mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUBSCRIBE_MODEL ((sl_status_t)0x1308) ///< Returned when the model does not support the subscribe mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_STORAGE_FAILURE ((sl_status_t)0x1309) ///< Returned when storing of the requested parameters failed +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUPPORTED ((sl_status_t)0x130A) ///< Returned when requested setting is not supported +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_UPDATE ((sl_status_t)0x130B) ///< Returned when the requested update operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_REMOVE ((sl_status_t)0x130C) ///< Returned when the requested delete operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_BIND ((sl_status_t)0x130D) ///< Returned when the requested bind operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_TEMPORARILY_UNABLE ((sl_status_t)0x130E) ///< Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_SET ((sl_status_t)0x130F) ///< Returned when the requested state cannot be set +#define SL_STATUS_BT_MESH_FOUNDATION_UNSPECIFIED ((sl_status_t)0x1310) ///< Returned when an unspecified error took place +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_BINDING ((sl_status_t)0x1311) ///< Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update + +// ----------------------------------------------------------------------------- +// Wi-Fi Errors + +#define SL_STATUS_WIFI_INVALID_KEY ((sl_status_t)0x0B01) ///< Invalid firmware keyset +#define SL_STATUS_WIFI_FIRMWARE_DOWNLOAD_TIMEOUT ((sl_status_t)0x0B02) ///< The firmware download took too long +#define SL_STATUS_WIFI_UNSUPPORTED_MESSAGE_ID ((sl_status_t)0x0B03) ///< Unknown request ID or wrong interface ID used +#define SL_STATUS_WIFI_WARNING ((sl_status_t)0x0B04) ///< The request is successful but some parameters have been ignored +#define SL_STATUS_WIFI_NO_PACKET_TO_RECEIVE ((sl_status_t)0x0B05) ///< No Packets waiting to be received +#define SL_STATUS_WIFI_SLEEP_GRANTED ((sl_status_t)0x0B08) ///< The sleep mode is granted +#define SL_STATUS_WIFI_SLEEP_NOT_GRANTED ((sl_status_t)0x0B09) ///< The WFx does not go back to sleep +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ERROR ((sl_status_t)0x0B10) ///< The SecureLink MAC key was not found +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ALREADY_BURNED ((sl_status_t)0x0B11) ///< The SecureLink MAC key is already installed in OTP +#define SL_STATUS_WIFI_SECURE_LINK_RAM_MODE_NOT_ALLOWED ((sl_status_t)0x0B12) ///< The SecureLink MAC key cannot be installed in RAM +#define SL_STATUS_WIFI_SECURE_LINK_FAILED_UNKNOWN_MODE ((sl_status_t)0x0B13) ///< The SecureLink MAC key installation failed +#define SL_STATUS_WIFI_SECURE_LINK_EXCHANGE_FAILED ((sl_status_t)0x0B14) ///< SecureLink key (re)negotiation failed +#define SL_STATUS_WIFI_WRONG_STATE ((sl_status_t)0x0B18) ///< The device is in an inappropriate state to perform the request +#define SL_STATUS_WIFI_CHANNEL_NOT_ALLOWED ((sl_status_t)0x0B19) ///< The request failed due to regulatory limitations +#define SL_STATUS_WIFI_NO_MATCHING_AP ((sl_status_t)0x0B1A) ///< The connection request failed because no suitable AP was found +#define SL_STATUS_WIFI_CONNECTION_ABORTED ((sl_status_t)0x0B1B) ///< The connection request was aborted by host +#define SL_STATUS_WIFI_CONNECTION_TIMEOUT ((sl_status_t)0x0B1C) ///< The connection request failed because of a timeout +#define SL_STATUS_WIFI_CONNECTION_REJECTED_BY_AP ((sl_status_t)0x0B1D) ///< The connection request failed because the AP rejected the device +#define SL_STATUS_WIFI_CONNECTION_AUTH_FAILURE ((sl_status_t)0x0B1E) ///< The connection request failed because the WPA handshake did not complete successfully +#define SL_STATUS_WIFI_RETRY_EXCEEDED ((sl_status_t)0x0B1F) ///< The request failed because the retry limit was exceeded +#define SL_STATUS_WIFI_TX_LIFETIME_EXCEEDED ((sl_status_t)0x0B20) ///< The request failed because the MSDU life time was exceeded + +// ----------------------------------------------------------------------------- +// MVP Driver and MVP Math status codes +#define SL_STATUS_COMPUTE_DRIVER_FAULT ((sl_status_t)0x1501) ///< Critical fault +#define SL_STATUS_COMPUTE_DRIVER_ALU_NAN ((sl_status_t)0x1502) ///< ALU operation output NaN +#define SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW ((sl_status_t)0x1503) ///< ALU numeric overflow +#define SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW ((sl_status_t)0x1504) ///< ALU numeric underflow +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW ((sl_status_t)0x1505) ///< Overflow during array store +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW ((sl_status_t)0x1506) ///< Underflow during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion + +#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered +#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered +#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow +#define SL_STATUS_COMPUTE_MATH_UNDERFLOW ((sl_status_t)0x1515) ///< MATH numeric underflow + +// ----------------------------------------------------------------------------- +// Data Types +/** @brief define global status variable. */ +typedef uint32_t sl_status_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * sl_status_get_string_n() + * + * @brief Get a copy of the status string associated to the status code passed, up to + * 'buffer_length' length, if the string associated to the status code is enabled. If not, + * the error code number, in hex, prefixed by "SL_STATUS_" will be copied in the buffer + * instead. + * For example, the buffer would either contain "SL_STATUS_FAIL" if that status string is + * enabled, or "SL_STATUS_0x0001" if the string is disabled, as SL_STATUS_FAIL's + * value is 0x0001. + * + * @param status The status code from which to obtain the status string. + * + * @param buffer Pointer to a buffer in which the status string will be copied. A terminating + * null-character will be appended after the copied status string. + * + * @param buffer_length Maximum number of characters that can be written in the buffer, including the + * terminating null-character. If the status string would be longer than the + * available length, it will be truncated and a null-terminating character will + * be the last character contained in the buffer. + * + * @return The number of characters that would have been written if the buffer_length had been + * sufficiently large, not counting the terminating null character. + * If the status code is invalid, 0 or a negative number is returned. + * Notice that only when this returned value is strictly positive and less than + * buffer_length, the status string has been completely written in the buffer. + *******************************************************************************************************/ +int32_t sl_status_get_string_n(sl_status_t status, char *buffer, uint32_t buffer_length); + +/******************************************************************************************************** + * sl_status_print() + * + * @brief Print, through printf, the string associated to the passed status code. If the string + * associated to the status code is enabled, the status string will be printed, for example + * "SL_STATUS_OK". If the string associated to the status code is disabled, the status number, + * in hex, prefixed by "SL_STATUS_" will be printed instead, for example "SL_STATUS_0x0000", + * as SL_STATUS_OK's value is 0x0000. + * + * @param status The status code of which to print the status string. + *******************************************************************************************************/ +void sl_status_print(sl_status_t status); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup status) */ + +#endif /* SL_STATUS_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_assert.c b/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_assert.c index 5b22c4f..12c843a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_assert.c +++ b/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_assert.c @@ -1,76 +1,76 @@ -/***************************************************************************//** - * @file - * @brief Assert API - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_assert.h" -#include - -/***************************************************************************//** - * @addtogroup assert - * @details - * This module contains functions to control the ASSERT peripheral of Silicon - * Labs 32-bit MCUs and SoCs. - * @{ - ******************************************************************************/ - -#if defined(DEBUG_EFM) -/***************************************************************************//** - * @brief - * EFM internal assert handling. - * - * This function is invoked through EFM_ASSERT() macro usage only and should - * not be used explicitly. - * - * This implementation enters an indefinite loop, allowing - * the use of a debugger to determine a cause of failure. By defining - * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version - * of this function must be defined and will be invoked instead, possibly - * providing output of assertion location. - * - * @note - * This function is not used unless DEBUG_EFM is defined - * during preprocessing of EFM_ASSERT() usage. - * - * @param[in] file - * Name of the source file where assertion failed. - * - * @param[in] line - * A line number in the source file where assertion failed. - ******************************************************************************/ -void assertEFM(const char *file, int line) -{ - (void)file; /* Unused parameter */ - (void)line; /* Unused parameter */ - - while (true) { - } -} -#endif /* DEBUG_EFM */ - -/** @} (end addtogroup assert) */ +/***************************************************************************//** + * @file + * @brief Assert API + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include + +/***************************************************************************//** + * @addtogroup assert + * @details + * This module contains functions to control the ASSERT peripheral of Silicon + * Labs 32-bit MCUs and SoCs. + * @{ + ******************************************************************************/ + +#if defined(DEBUG_EFM) +/***************************************************************************//** + * @brief + * EFM internal assert handling. + * + * This function is invoked through EFM_ASSERT() macro usage only and should + * not be used explicitly. + * + * This implementation enters an indefinite loop, allowing + * the use of a debugger to determine a cause of failure. By defining + * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version + * of this function must be defined and will be invoked instead, possibly + * providing output of assertion location. + * + * @note + * This function is not used unless DEBUG_EFM is defined + * during preprocessing of EFM_ASSERT() usage. + * + * @param[in] file + * Name of the source file where assertion failed. + * + * @param[in] line + * A line number in the source file where assertion failed. + ******************************************************************************/ +void assertEFM(const char *file, int line) +{ + (void)file; /* Unused parameter */ + (void)line; /* Unused parameter */ + + while (true) { + } +} +#endif /* DEBUG_EFM */ + +/** @} (end addtogroup assert) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c b/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c index 84949f0..7ab761a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c +++ b/locator_host/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c @@ -1,115 +1,115 @@ -/***************************************************************************//** - * @file - * @brief SystemCall API - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup systemcalls - * @details - * This module reimplements the syscalls that don't have the definition in the - * bare metal project. - * This prevents linker warnings. - * @{ - ******************************************************************************/ -#include "cmsis_compiler.h" - -struct stat; -struct timeval; -struct timezone; - -__WEAK int _close(int file) -{ - (void)file; - return -1; -} - -__WEAK void _exit(int status) -{ - (void)status; - - /* Convince GCC that this function never returns. */ - for (;; ) { - ; - } -} - -__WEAK int _fstat(int file, struct stat *st) -{ - (void)file; - (void)(void *)st; - return 0; -} - -__WEAK int _getpid(void) -{ - return 1; -} - -__WEAK int _isatty(int file) -{ - (void)file; - return 1; -} - -__WEAK int _kill(int pid, int sig) -{ - (void)pid; - (void)sig; - return -1; -} - -__WEAK int _lseek(int file, int ptr, int dir) -{ - (void)file; - (void)ptr; - (void)dir; - return 0; -} - -__WEAK int _read(int file, char *ptr, int len) -{ - (void)file; - (void)(void *)ptr; - (void)len; - return 0; -} - -__WEAK int _write(int file, const char *ptr, int len) -{ - (void)file; - (void)(const void *)ptr; - (void)len; - return 0; -} - -__WEAK int _gettimeofday(struct timeval *tv, struct timezone *tz) -{ - (void)(void *)tv; - (void)(void *)tz; - return 0; -} +/***************************************************************************//** + * @file + * @brief SystemCall API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup systemcalls + * @details + * This module reimplements the syscalls that don't have the definition in the + * bare metal project. + * This prevents linker warnings. + * @{ + ******************************************************************************/ +#include "cmsis_compiler.h" + +struct stat; +struct timeval; +struct timezone; + +__WEAK int _close(int file) +{ + (void)file; + return -1; +} + +__WEAK void _exit(int status) +{ + (void)status; + + /* Convince GCC that this function never returns. */ + for (;; ) { + ; + } +} + +__WEAK int _fstat(int file, struct stat *st) +{ + (void)file; + (void)(void *)st; + return 0; +} + +__WEAK int _getpid(void) +{ + return 1; +} + +__WEAK int _isatty(int file) +{ + (void)file; + return 1; +} + +__WEAK int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + return -1; +} + +__WEAK int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +__WEAK int _read(int file, char *ptr, int len) +{ + (void)file; + (void)(void *)ptr; + (void)len; + return 0; +} + +__WEAK int _write(int file, const char *ptr, int len) +{ + (void)file; + (void)(const void *)ptr; + (void)len; + return 0; +} + +__WEAK int _gettimeofday(struct timeval *tv, struct timezone *tz) +{ + (void)(void *)tv; + (void)(void *)tz; + return 0; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h index 55543c5..f032404 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h @@ -1,40 +1,40 @@ -/***************************************************************************//** - * @file - * @brief GCC startup file - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* The startup files contain a stack and heap symbol in addition - * to the vector table. The size of these internal stack and heap - * objects depend on the build system providing two macros on the - * commandline called __STACK_SIZE and __HEAP_SIZE. - * - * We provide alternative stack and heap symbols in the sl_memory.c - * file which can be configured in a separate config file. Go to - * sl_memory_config.h to configure the stack and heap size. */ -#define __STACK_SIZE 0x0 -#define __HEAP_SIZE 0x0 +/***************************************************************************//** + * @file + * @brief GCC startup file + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* The startup files contain a stack and heap symbol in addition + * to the vector table. The size of these internal stack and heap + * objects depend on the build system providing two macros on the + * commandline called __STACK_SIZE and __HEAP_SIZE. + * + * We provide alternative stack and heap symbols in the sl_memory.c + * file which can be configured in a separate config file. Go to + * sl_memory_config.h to configure the stack and heap size. */ +#define __STACK_SIZE 0x0 +#define __HEAP_SIZE 0x0 diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h index 64152d8..9f39e35 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief Heap and stack memory - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MEMORY_H -#define SL_MEMORY_H - -#include "sl_memory_region.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup linker - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get size and location of the stack. - * - * @return - * description of the region reserved for the c stack. - ******************************************************************************/ -sl_memory_region_t sl_memory_get_stack_region(void); - -/***************************************************************************//** - * @brief - * Get size and location of the heap. - * - * @return - * description of the region reserved for the c heap. - ******************************************************************************/ -sl_memory_region_t sl_memory_get_heap_region(void); - -/** @} end linker */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MEMORY_H +/***************************************************************************//** + * @file + * @brief Heap and stack memory + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MEMORY_H +#define SL_MEMORY_H + +#include "sl_memory_region.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup linker + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get size and location of the stack. + * + * @return + * description of the region reserved for the c stack. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_stack_region(void); + +/***************************************************************************//** + * @brief + * Get size and location of the heap. + * + * @return + * description of the region reserved for the c heap. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_heap_region(void); + +/** @} end linker */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MEMORY_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h index 186f1db..4c73a0f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h +++ b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h @@ -1,49 +1,49 @@ -/***************************************************************************//** - * @file - * @brief Memory region types - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_REGION_H -#define SL_REGION_H - -#include - -/***************************************************************************//** - * @addtogroup linker Linker - * @brief Functions to extract locations of linker sections. - * @{ - ******************************************************************************/ - -/** Memory region structure. */ -typedef struct sl_memory_region_t { - void * addr; ///< Pointer to the beginning of the memory region. Can be NULL. - size_t size; ///< Size of this memory region. -} sl_memory_region_t; - -/** @} end linker */ - -#endif +/***************************************************************************//** + * @file + * @brief Memory region types + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_REGION_H +#define SL_REGION_H + +#include + +/***************************************************************************//** + * @addtogroup linker Linker + * @brief Functions to extract locations of linker sections. + * @{ + ******************************************************************************/ + +/** Memory region structure. */ +typedef struct sl_memory_region_t { + void * addr; ///< Pointer to the beginning of the memory region. Can be NULL. + size_t size; ///< Size of this memory region. +} sl_memory_region_t; + +/** @} end linker */ + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c index e26cb7d..a6c719f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c +++ b/locator_host/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c @@ -1,110 +1,110 @@ -/***************************************************************************//** - * @file - * @brief Heap and stack allocation - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include "em_device.h" -#include "sl_memory.h" -#include "sl_memory_config.h" - -#if defined(__GNUC__) -/* Declare stack object used with gcc */ -static char sl_stack[SL_STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); - -/* Declare the minimum heap object used with gcc */ - #if SL_HEAP_SIZE > 0 -static char sl_heap[SL_HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); - #endif - -/* - * Declare the base and limit of the full heap region used with gcc. To make - * use of otherwise unused memory, the total heap region be larger than the - * minimum heap allocation above. - */ -extern char __HeapBase[]; -extern char __HeapLimit[]; - -#elif defined(__ICCARM__) -/* Declare stack object used with iar */ -__root char sl_stack[SL_STACK_SIZE] @ ".stack"; - -/* Declare the minimum heap object used with iar */ - #if SL_HEAP_SIZE > 0 -__root char sl_heap[SL_HEAP_SIZE] @ ".heap"; - #endif - #pragma section="HEAP" - -#endif - -sl_memory_region_t sl_memory_get_stack_region(void) -{ - sl_memory_region_t region; - - region.addr = &sl_stack; - region.size = SL_STACK_SIZE; - return region; -} - -sl_memory_region_t sl_memory_get_heap_region(void) -{ - sl_memory_region_t region; - - /* - * Report the actual heap region which may be larger then the minimum - * allocation of SL_HEAP_SIZE bytes - */ -#if defined(__GNUC__) - region.addr = __HeapBase; - region.size = (size_t) ((uintptr_t) __HeapLimit - (uintptr_t) __HeapBase); - -#elif defined(__ICCARM__) - region.addr = __section_begin("HEAP"); - region.size = __section_size("HEAP"); - -#endif - - return region; -} - -#if defined(__GNUC__) -__USED void * _sbrk(int incr) -{ - static char *heap_end = __HeapBase; - char *prev_heap_end; - - if ((heap_end + incr) > __HeapLimit) { - // Not enough heap - return (void *) -1; - } - - prev_heap_end = heap_end; - heap_end += incr; - - return prev_heap_end; -} -#endif +/***************************************************************************//** + * @file + * @brief Heap and stack allocation + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include "em_device.h" +#include "sl_memory.h" +#include "sl_memory_config.h" + +#if defined(__GNUC__) +/* Declare stack object used with gcc */ +static char sl_stack[SL_STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +/* Declare the minimum heap object used with gcc */ + #if SL_HEAP_SIZE > 0 +static char sl_heap[SL_HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); + #endif + +/* + * Declare the base and limit of the full heap region used with gcc. To make + * use of otherwise unused memory, the total heap region be larger than the + * minimum heap allocation above. + */ +extern char __HeapBase[]; +extern char __HeapLimit[]; + +#elif defined(__ICCARM__) +/* Declare stack object used with iar */ +__root char sl_stack[SL_STACK_SIZE] @ ".stack"; + +/* Declare the minimum heap object used with iar */ + #if SL_HEAP_SIZE > 0 +__root char sl_heap[SL_HEAP_SIZE] @ ".heap"; + #endif + #pragma section="HEAP" + +#endif + +sl_memory_region_t sl_memory_get_stack_region(void) +{ + sl_memory_region_t region; + + region.addr = &sl_stack; + region.size = SL_STACK_SIZE; + return region; +} + +sl_memory_region_t sl_memory_get_heap_region(void) +{ + sl_memory_region_t region; + + /* + * Report the actual heap region which may be larger then the minimum + * allocation of SL_HEAP_SIZE bytes + */ +#if defined(__GNUC__) + region.addr = __HeapBase; + region.size = (size_t) ((uintptr_t) __HeapLimit - (uintptr_t) __HeapBase); + +#elif defined(__ICCARM__) + region.addr = __section_begin("HEAP"); + region.size = __section_size("HEAP"); + +#endif + + return region; +} + +#if defined(__GNUC__) +__USED void * _sbrk(int incr) +{ + static char *heap_end = __HeapBase; + char *prev_heap_end; + + if ((heap_end + incr) > __HeapLimit) { + // Not enough heap + return (void *) -1; + } + + prev_heap_end = heap_end; + heap_end += incr; + + return prev_heap_end; +} +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp.h b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp.h index c3a1a98..8c80d26 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp.h @@ -1,954 +1,954 @@ -/***************************************************************************//** - * @file - * @brief MVP Driver. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MVP_H -#define SL_MVP_H - -#include "sl_status.h" -#include "em_device.h" -#include "sl_math_types.h" -#include "sl_mvp_types.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/***************************************************************************//** - * @addtogroup mvp MVP API - * @{ - ******************************************************************************/ - -// Defines for each of the 8 MVP registers. -#define SLI_MVP_R0 0 -#define SLI_MVP_R1 1 -#define SLI_MVP_R2 2 -#define SLI_MVP_R3 3 -#define SLI_MVP_R4 4 -#define SLI_MVP_R5 5 -#define SLI_MVP_R6 6 -#define SLI_MVP_R7 7 - -// Defines for Loop/Stream increments. -#define SLI_MVP_NOINCR 0x0 -#define SLI_MVP_NORST 0x0 -#define SLI_MVP_INCRDIM0 0x1 -#define SLI_MVP_INCRDIM1 0x2 -#define SLI_MVP_INCRDIM2 0x4 -#define SLI_MVP_INCRDIM_VEC SLI_MVP_INCRDIM0 -#define SLI_MVP_INCRDIM_ROW SLI_MVP_INCRDIM1 -#define SLI_MVP_INCRDIM_COL SLI_MVP_INCRDIM2 - -// Alternative INCRDIM macros, useful when using "NHWC" tensors. -#define SLI_MVP_INCRDIM_DEPTH SLI_MVP_INCRDIM_VEC -#define SLI_MVP_INCRDIM_HEIGHT SLI_MVP_INCRDIM_ROW -#define SLI_MVP_INCRDIM_WIDTH SLI_MVP_INCRDIM_COL - -// Defines for Loop dimension resets. -#define SLI_MVP_NO_DIM_RESET 0x0 -#define SLI_MVP_RESETDIM0 0x1 -#define SLI_MVP_RESETDIM1 0x2 -#define SLI_MVP_RESETDIM2 0x4 -#define SLI_MVP_RESETDIM_VEC SLI_MVP_RESETDIM0 -#define SLI_MVP_RESETDIM_ROW SLI_MVP_RESETDIM1 -#define SLI_MVP_RESETDIM_COL SLI_MVP_RESETDIM2 - -// Alternative RESETDIM macros, useful when using "NHWC" tensors. -#define SLI_MVP_RESETDIM_DEPTH SLI_MVP_RESETDIM_VEC -#define SLI_MVP_RESETDIM_HEIGHT SLI_MVP_RESETDIM_ROW -#define SLI_MVP_RESETDIM_WIDTH SLI_MVP_RESETDIM_COL - -// Defines for Instruction RegLoad/RegStore selection (for STREAM macro). -#define SLI_MVP_REGLOAD0 0 -#define SLI_MVP_REGLOAD1 1 -#define SLI_MVP_REGSTORE 2 - -// Defines for ALUIN macro. -#define SLI_MVP_ALUIN0 0 -#define SLI_MVP_ALUIN1 1 -#define SLI_MVP_ALUIN2 2 -#define SLI_MVP_ENDPROG 1 -#define SLI_MVP_NONE 0 - -// Defines for ALU register modifiers. -#define SLI_MVP_ALUIN_REALZERO 0x1 -#define SLI_MVP_ALUIN_REALNEGATE 0x2 -#define SLI_MVP_ALUIN_IMAGZERO 0x4 -#define SLI_MVP_ALUIN_IMAGNEGATE 0x8 - -// MVP hardware limits. -#define SLI_MVP_MAX_DIM (3U) -#define SLI_MVP_MAX_VECTOR_COUNT ((_MVP_ARRAYDIM0CFG_SIZE_MASK >> _MVP_ARRAYDIM0CFG_SIZE_SHIFT)+ 1U) -#define SLI_MVP_MAX_ROW_LENGTH ((_MVP_ARRAYDIM1CFG_SIZE_MASK >> _MVP_ARRAYDIM1CFG_SIZE_SHIFT)+ 1U) -#define SLI_MVP_MAX_COLUMN_LENGTH ((_MVP_ARRAYDIM2CFG_SIZE_MASK >> _MVP_ARRAYDIM2CFG_SIZE_SHIFT)+ 1U) -#define SLI_MVP_MAX_VECTOR_STRIDE ((_MVP_ARRAYDIM0CFG_STRIDE_MASK >> (_MVP_ARRAYDIM0CFG_STRIDE_SHIFT+1))) -#define SLI_MVP_MIN_VECTOR_STRIDE (-MAX_VECTOR_STRIDE - 1) -#define SLI_MVP_MAX_ROW_STRIDE ((_MVP_ARRAYDIM1CFG_STRIDE_MASK >> (_MVP_ARRAYDIM1CFG_STRIDE_SHIFT+1))) -#define SLI_MVP_MIN_ROW_STRIDE (-MAX_ROW_STRIDE - 1) -#define SLI_MVP_MAX_COLUMN_STRIDE ((_MVP_ARRAYDIM2CFG_STRIDE_MASK >> (_MVP_ARRAYDIM2CFG_STRIDE_SHIFT+1))) -#define SLI_MVP_MIN_COLUMN_STRIDE (-MAX_COLUMN_STRIDE - 1) - -#define SLI_MVP_FP16_MIN (-65504.0f) -#define SLI_MVP_FP16_MAX 65504.0f - -// Array id macro for readability. -#define SLI_MVP_ARRAY(n) (n) - -// Loop id macro for readability. -#define SLI_MVP_LOOP(n) (n) - -// Instruction id macro for readability. -#define SLI_MVP_INSTR(n) (n) - -// Macro to build up ALUOUT field in CFG0. -#define SLI_MVP_ALUOUT(n) ((n) << _MVP_INSTRCFG0_ALUOUTREGID_SHIFT) - -// Macro to build up ALUIN field in CFG0. The SLI_MVP_ALU_* macros should -// be used instead when building up the ALU configuration when no flags are used. -// r - 0-7=R0-R7 -// f - flags, combination of any of these: -// SLI_MVP_ALUIN_REALZERO -// SLI_MVP_ALUIN_REALNEGATE -// SLI_MVP_ALUIN_IMAGZERO -// SLI_MVP_ALUIN_IMAGNEGATE -#define SLI_MVP_ALUIN_X(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN0))) -#define SLI_MVP_ALUIN_Y(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN1))) -#define SLI_MVP_ALUIN_A(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN2))) - -// First argument to ALU operation. ALU Input X == ALUIN0. -#define SLI_MVP_ALU_X(reg) SLI_MVP_ALUIN_X(reg, 0) - -// Second argument to ALU operation. ALU Input Y == ALUIN1. -#define SLI_MVP_ALU_Y(reg) SLI_MVP_ALUIN_Y(reg, 0) - -// Third argument to ALU operation. ALU Input A == ALUIN2. -#define SLI_MVP_ALU_A(reg) SLI_MVP_ALUIN_A(reg, 0) - -// Used to specify the output register. ALU Output Z == ALUOUT. -#define SLI_MVP_ALU_Z(reg) SLI_MVP_ALUOUT(reg) - -// Macro to build REGLOAD/REGSTORE field in CFG1. -// SLI_MVP_LOAD() or SLI_MVP_STORE() should be used when building instructions. -#define SLI_MVP_STREAM(s, r, a, i) ((((i) << 7) | ((a) << 4) | 0x8 | (r)) << ((s) * 10)) - -// Specify use of Load channel 0 or 1. -// Example: SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM0) -#define SLI_MVP_LOAD(n, r, a, i) SLI_MVP_STREAM(n, r, a, i) - -// Used when storing a register as part of an instruction. -// Example: SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM0) -#define SLI_MVP_STORE(r, a, i) SLI_MVP_STREAM(SLI_MVP_REGSTORE, r, a, i) - -// Define for MVP operation used in instructions. -#define SLI_MVP_OP(x) (_MVP_INSTRCFG2_ALUOP_ ## x) - -// Loop Increment macro. -#define SLI_MVP_LOOP_INCRDIM(array, dim) ((dim) << (4 * (array))) - -// Loop Reset macro. -#define SLI_MVP_LOOP_RSTDIM(array, dim) ((dim) << (4 * (array))) - -// MVP numerical exceptions flag mask. -#define SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK \ - (MVP_IF_ALUNAN | MVP_IF_ALUOF | MVP_IF_ALUUF \ - | MVP_IF_STORECONVERTOF | MVP_IF_STORECONVERTUF \ - | MVP_IF_STORECONVERTINF | MVP_IF_STORECONVERTNAN) - -/** - * ALU Registers are always represented as a complex float16_t type. - * This structure is used to allow a program to assign value to either - * the real or imaginary part of the ALU register. - */ -typedef struct { - struct { - float16_t real; - float16_t imag; - } value; -} sli_mvp_alu_bitfield_t; - -typedef struct { - union { - uint32_t REGSTATE; ///< ALU Rn Register. - sli_mvp_alu_bitfield_t reg; - }; -} sli_mvp_alu_reg_t; - -typedef struct -{ - sli_mvp_addr_reg_t ADDRCFG; ///< Array Base Address - union { - uint32_t DIM0CFG; ///< Dimension 0 Configuration - struct { - uint32_t size : 10; - uint32_t : 2; - uint32_t basetype : 2; - uint32_t complex : 1; - uint32_t : 1; - uint32_t stride : 12; - uint32_t : 4; - } dim0cfg; - }; - union { - uint32_t DIM1CFG; ///< Dimension 1 Configuration - struct { - uint32_t size : 10; - uint32_t : 6; - uint32_t stride : 12; - uint32_t : 4; - } dim1cfg; - }; - union { - uint32_t DIM2CFG; ///< Dimension 2 Configuration - struct { - uint32_t size : 10; - uint32_t : 6; - uint32_t stride : 12; - uint32_t : 4; - } dim2cfg; - }; -} sli_mvp_array_reg_t; - -typedef struct -{ - union { - uint32_t CFG; ///< Loop Configuration - struct { - uint32_t numiters : 10; - uint32_t : 2; - uint32_t array0incrdim0 : 1; - uint32_t array0incrdim1 : 1; - uint32_t array0incrdim2 : 1; - uint32_t : 1; - uint32_t array1incrdim0 : 1; - uint32_t array1incrdim1 : 1; - uint32_t array1incrdim2 : 1; - uint32_t : 1; - uint32_t array2incrdim0 : 1; - uint32_t array2incrdim1 : 1; - uint32_t array2incrdim2 : 1; - uint32_t : 1; - uint32_t array3incrdim0 : 1; - uint32_t array3incrdim1 : 1; - uint32_t array3incrdim2 : 1; - uint32_t : 1; - uint32_t array4incrdim0 : 1; - uint32_t array4incrdim1 : 1; - uint32_t array4incrdim2 : 1; - uint32_t : 1; - } cfg; - }; - union { - uint32_t RST; ///< Loop Reset - struct { - uint32_t : 12; - uint32_t array0resetdim0 : 1; - uint32_t array0resetdim1 : 1; - uint32_t array0resetdim2 : 1; - uint32_t : 1; - uint32_t array1resetdim0 : 1; - uint32_t array1resetdim1 : 1; - uint32_t array1resetdim2 : 1; - uint32_t : 1; - uint32_t array2resetdim0 : 1; - uint32_t array2resetdim1 : 1; - uint32_t array2resetdim2 : 1; - uint32_t : 1; - uint32_t array3resetdim0 : 1; - uint32_t array3resetdim1 : 1; - uint32_t array3resetdim2 : 1; - uint32_t : 1; - uint32_t array4resetdim0 : 1; - uint32_t array4resetdim1 : 1; - uint32_t array4resetdim2 : 1; - uint32_t : 1; - } rst; - }; -} sli_mvp_loop_reg_t; - -typedef struct { - union { - uint32_t CFG0; ///< Instruction Configuration Word 0. - struct { - uint32_t aluin0regid : 3; - uint32_t : 1; - uint32_t aluin0realzero : 1; - uint32_t aluin0realnegate : 1; - uint32_t aluin0imagzero : 1; - uint32_t aluin0imagnegate : 1; - uint32_t aluin1regid : 3; - uint32_t : 1; - uint32_t aluin1realzero : 1; - uint32_t aluin1realnegate : 1; - uint32_t aluin1imagzero : 1; - uint32_t aluin1imagnegate : 1; - uint32_t aluin2regid : 3; - uint32_t : 1; - uint32_t aluin2realzero : 1; - uint32_t aluin2realnegate : 1; - uint32_t aluin2imagzero : 1; - uint32_t aluin2imagnegate : 1; - uint32_t : 4; - uint32_t aluoutregid : 3; - uint32_t : 1; - } cfg0; - }; - union { - uint32_t CFG1; ///< Instruction Configuration Word 1. - struct { - uint32_t istream0regid : 3; - uint32_t istream0load : 1; - uint32_t istream0arrayid : 3; - uint32_t istream0arrayincrdim0 : 1; - uint32_t istream0arrayincrdim1 : 1; - uint32_t istream0arrayincrdim2 : 1; - uint32_t istream1regid : 3; - uint32_t istream1load : 1; - uint32_t istream1arrayid : 3; - uint32_t istream1arrayincrdim0 : 1; - uint32_t istream1arrayincrdim1 : 1; - uint32_t istream1arrayincrdim2 : 1; - uint32_t ostreamregid : 3; - uint32_t ostreamstore : 1; - uint32_t ostreamarrayid : 3; - uint32_t ostreamarrayincrdim0 : 1; - uint32_t ostreamarrayincrdim1 : 1; - uint32_t ostreamarrayincrdim2 : 1; - uint32_t : 2; - } cfg1; - }; - union { - uint32_t CFG2; ///< Instruction Configuration Word 2. - struct { - uint32_t loop0begin : 1; - uint32_t loop0end : 1; - uint32_t loop1begin : 1; - uint32_t loop1end : 1; - uint32_t loop2begin : 1; - uint32_t loop2end : 1; - uint32_t loop3begin : 1; - uint32_t loop3end : 1; - uint32_t loop4begin : 1; - uint32_t loop4end : 1; - uint32_t loop5begin : 1; - uint32_t loop5end : 1; - uint32_t loop6begin : 1; - uint32_t loop6end : 1; - uint32_t loop7begin : 1; - uint32_t loop7end : 1; - uint32_t : 4; - uint32_t aluop : 9; - uint32_t : 2; - uint32_t endprog : 1; - } cfg2; - }; -} sli_mvp_instr_reg_t; - -/** - * Represents a single MVP program that can be loaded onto the hardware. A full - * algorithm can potentially be represented by a number of different program - * structures. - */ -typedef struct { - sli_mvp_alu_reg_t ALU[8U]; - sli_mvp_array_reg_t ARRAY[5U]; - sli_mvp_loop_reg_t LOOP[8U]; - sli_mvp_instr_reg_t INSTR[8U]; - uint32_t CMD; -} sli_mvp_program_t; - -/** - * Type used when configuring performance counters. - */ -typedef enum { - SLI_MVP_PERFCNT_CYCLES = 0, ///< Count MVP cycles - SLI_MVP_PERFCNT_INSTRUCTIONS = 1, ///< Count MVP instructions - SLI_MVP_PERFCNT_STALL = 2 ///< Count number of stalls -} sli_mvp_perfcnt_t; - -typedef enum { - SLI_MVP_DATATYPE_UINT8 = 0x0, - SLI_MVP_DATATYPE_INT8 = 0x1, - SLI_MVP_DATATYPE_BINARY16 = 0x2, - SLI_MVP_DATATYPE_COMPLEX_UINT8 = 0x4, - SLI_MVP_DATATYPE_COMPLEX_INT8 = 0x5, - SLI_MVP_DATATYPE_COMPLEX_BINARY16 = 0x6 -} sli_mvp_datatype_t; - -/** - * Context for using the MVP program builder helper functions. - */ -typedef struct { - sli_mvp_program_t program[2]; ///< Two MVP program buffers. - uint32_t loop_begin_end[8]; ///< Storage for instruction loop begin/end bits. - uint32_t loop_stack[8]; ///< Stack for keeping track of loop nesting level. - sli_mvp_program_t *p; ///< Pointer to active MVP program buffer. - int prog_index; ///< Index used to select one of two possible MVP program buffers. - int last_loop; ///< Loop counter. - int last_instr; ///< Instruction counter. - int loop_level; ///< Loop nesting level. -} sli_mvp_program_context_t; - -/** - * @brief - * Clear MVP exception and fault flags. - * - * @param[in] flags - * A bit mask with one or more flags to clear. Refer to - * sli_mvp_get_error_flags() for a description of bit positions. - */ -void sli_mvp_clear_error_flags(uint32_t flags); - -/** - * @brief - * Get an MVP exception or fault errorcode and optional descriptive - * error message. - * - * @details - * Intended use of this function is to call it repeatedly to iterate over - * existing errors and get errorcodes and optional error message strings. - * - * @param[out] error_code - * The assigned sl_status_t errorcode. - * - * @param[in,out] error_message - * A descriptive error message string. Input a NULL pointer to skip - * the error message. - * - * @param[in] buffer_length - * The size of the error_message buffer. - * - * @return - * Return SL_STATUS_OK when an error is present, this indicates that - * error_code and optionally error_message output parameters are valid. - * Return SL_STATUS_NOT_FOUND when no error to report. - */ -sl_status_t sli_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length); - -/** - * @brief - * Get MVP exception and fault flags. - * - * @details - * The value returned is a bitfield with a layout matching the MVP->IF - * registers numerical exception bit positions. In addition bit 0 is used as - * a concatenation of the fault flags. - * - * @return - * MVP exception and fault flags. - */ -uint32_t sli_mvp_get_error_flags(void); - -/** - * @brief - * Initialize the MVP hardware. - * - * @details - * This function must be called once before any of the other functions are - * used. This function will configure the MVP hardware based on the content - * of the sl_driver_mvp_config.h file. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_init(void); - -/** - * @brief - * De-Initialize the MVP hardware. - * - * @details - * This function can be called when the MVP hardware is no longer being used. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_deinit(void); - -/** - * @brief - * Enable the MVP hardware for command execution. - * - * @details - * This function must be called before a MVP program can be executed. - * - * @note - * The MVP will automatically be disabled by the driver when the command - * has completed execution. - */ -void sli_mvp_cmd_enable(void); - -/** - * @brief - * If there is a program running, wait for it to to complete. - * - * @return - * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on - * MVP faults. - */ -sl_status_t sli_mvp_cmd_wait_for_completion(void); - -/** - * @brief - * Execute a single program on the MVP hardware. - * - * @details - * Used to schedule a program for execution. - * - * @param[in] program - * The program to run on the MVP hardware. - * - * @param[in] wait - * If true then the function will wait for the program to complete before - * returning to the caller. If false then the function will return to the - * caller before the program is completed. - * - * @return - * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on - * MVP faults. - */ -sl_status_t sli_mvp_prog_execute(sli_mvp_program_t *program, bool wait); - - -// Functions for setting register value in an MVP program -void sli_mvp_prog_set_reg_s8(sli_mvp_program_t *prog, uint8_t reg, int8_t value); -void sli_mvp_prog_set_reg_s8c(sli_mvp_program_t *prog, uint8_t reg, int8_t real, int8_t imag); -void sli_mvp_prog_set_reg_s16(sli_mvp_program_t *prog, uint8_t reg, int16_t value); -void sli_mvp_prog_set_reg_s16c(sli_mvp_program_t *prog, uint8_t reg, int16_t real, int16_t imag); -void sli_mvp_prog_set_reg_s32(sli_mvp_program_t *prog, uint8_t reg, int32_t value); -void sli_mvp_prog_set_reg_s32c(sli_mvp_program_t *prog, uint8_t reg, int32_t real, int32_t imag); -void sli_mvp_prog_set_reg_f16(sli_mvp_program_t *prog, uint8_t reg, float16_t value); -void sli_mvp_prog_set_reg_f16c(sli_mvp_program_t *prog, uint8_t reg, float16_t real, float16_t imag); -void sli_mvp_prog_set_reg_f32(sli_mvp_program_t *prog, uint8_t reg, float value); -void sli_mvp_prog_set_reg_f32c(sli_mvp_program_t *prog, uint8_t reg, float real, float imag); - -/** - * @brief - * Configure a specific array in a program, with possibility to specify strides. - * - * @param[in] prog The program to configure. - * @param[in] index Array index. Values in the range 0-4. - * @param[in] addr Base address of the array. - * @param[in] datatype Datatype of each array element. - * @param[in] vecs Number of vectors (DIM0). - * @param[in] rows Number of rows (DIM1). - * @param[in] cols Number of columns (DIM2). - * @param[in] vecstride Number of elements to advance when moving to the next vector (can be negative). - * @param[in] rowstride Number of elements to advance when moving to the next row (can be negative). - * @param[in] colstride Number of elements to advance when moving to the next column (can be negative). - */ -void sli_mvp_prog_set_array_full(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols, - int vecstride, - int rowstride, - int colstride); - -/** - * @brief - * Configure a specific array in a program. - * - * @note - * The resulting memory ordering will be "NCHW" i.e. "vector major". - * This aligns with the memory ordering of a C-language 3D array. - * - * @param[in] prog The program to configure. - * @param[in] index Array index. Values in the range 0-4 - * @param[in] addr Base address of the array. - * @param[in] datatype Datatype of each array element. - * @param[in] vecs Number of vectors (DIM0, major dimension). - * @param[in] rows Number of rows (DIM1). - * @param[in] cols Number of columns (DIM2, minor dimension). - */ -void sli_mvp_prog_set_array(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols); - -/** - * @brief - * Configure a specific vector in a program. - * - * @param[in] prog The program to configure. - * @param[in] index index. Values in the range 0-4 - * @param[in] addr Base address of the vector. - * @param[in] datatype Datatype of each vector element. - * @param[in] len Number of elements in vector (DIM2). - */ -void sli_mvp_prog_set_vector(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short len); - -/** - * @brief - * Configure a specific 2D matrix in a program. - * - * @note - * The resulting memory ordering will be "row major". - * - * @param[in] prog The program to configure. - * @param[in] index index. Values in the range 0-4 - * @param[in] addr Base address of the matrix. - * @param[in] datatype Datatype of each matrix element. - * @param[in] rows Number of rows (DIM1, major dimension). - * @param[in] cols Number of columns (DIM2, minor dimension). - */ -void sli_mvp_prog_set_matrix(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short rows, - unsigned short cols); - -/** - * @brief - * Configure a specific instruction in a program. - * - * @param[in] prog The program to configure. - * @param[in] index Instruction index. Values in the range 0-7 - * @param[in] opcode Operation to perform. - * @param[in] alu_cfg ALU configuration specifying input/output registers to use. - * @param[in] load_cfg Load configuration, specifying 0-2 load streams to use. - * @param[in] store_cfg Store configuration, specifying 0-1 store stream to use. - * @param[in] end True if this is the last instruction of the program, false otherwise. - */ -void sli_mvp_prog_set_instr(sli_mvp_program_t *prog, - uint8_t index, - uint32_t opcode, - uint32_t alu_cfg, - uint32_t load_cfg, - uint32_t store_cfg, - bool end); - -/** - * @brief - * Configure a specific loop in a program. - * - * @param[in] prog The program to configure. - * @param[in] index Loop index. Value in the range 0-7. - * @param[in] count Number of iterations. Value in the range 1-1024. - * @param[in] istart Start instruction of this loop. - * @param[in] iend End instruction of this loop. - * @param[in] incrarray Optional array increment configuration. - * @param[in] rstarray Optional array index reset configuration. - */ -void sli_mvp_prog_set_loop(sli_mvp_program_t *prog, - uint8_t index, - unsigned short count, - uint8_t istart, - uint8_t iend, - uint32_t incrarray, - uint32_t rstarray); - -/** - * @brief - * Configure one of the performance counters. - * - * @details - * Each of the performance counters can track different events. What event to count - * is configurable using the type parameter. - * - * @param[in] id - * The id of the performance counter to configure. - * - * @param[in] type - * Type of event to count. - */ -void sli_mvp_perfcnt_conf(unsigned id, sli_mvp_perfcnt_t type); - -/** - * @brief - * Reset all performance counters. - */ -void sli_mvp_perfcnt_reset_all(void); - -/** - * @brief - * Fetch the current aggregated value of a performance counter. - * - * @param[in] id - * The id of the performance counter to configure. - * - * @return - * Performance counter value. - */ -uint32_t sli_mvp_perfcnt_get(unsigned id); - -/** - * @brief - * Reset program count counter. - */ -void sli_mvp_progcnt_reset(void); - -/** - * @brief - * Fetch the current aggregated value of the program count counter. - * - * @return - * Program count counter value. - */ -uint32_t sli_mvp_progcnt_get(void); - -/** - * @brief - * Start a MVP program loop. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - * @param[in] iterations Loop count. - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER when loop count is exhausted. - * status is only updated when this error occur. - */ -void sli_mvp_pb_begin_loop(sli_mvp_program_context_t *p, int iterations, sl_status_t *status); - -/** - * @brief - * Begin a MVP program, will initialize part of the program context. - * Must be called once for each MVP program, and prior to any loop, compute - * or execute functions. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - */ -void sli_mvp_pb_begin_program(sli_mvp_program_context_t *p); - -/** - * @brief - * Insert a MVP instruction in the program. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - * @param[in] opcode Instruction opcode. - * @param[in] alu_cfg Instruction ALU configuration. - * @param[in] load_cfg Instruction load configuration. - * @param[in] store_cfg Instruction store configuration. - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER when instruction count is exhausted. - * status is only updated when this error occur. - */ -void sli_mvp_pb_compute(sli_mvp_program_context_t *p, uint32_t opcode, uint32_t alu_cfg, uint32_t load_cfg, uint32_t store_cfg, sl_status_t *status); - -/** - * @brief - * Configure a specific 3D array in a program. - * - * @param[in] prog The program to configure. - * @param[in] index Array index. Values in the range 0-4. - * @param[in] addr Base address of the array. - * @param[in] datatype Datatype of each array element. - * @param[in] vecs Number of vectors (DIM0). - * @param[in] rows Number of rows (DIM1). - * @param[in] cols Number of columns (DIM2). - * @param[in] vecstride Number of elements to advance when moving to the next vector (can be negative). - * @param[in] rowstride Number of elements to advance when moving to the next row (can be negative). - * @param[in] colstride Number of elements to advance when moving to the next column (can be negative). - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array - * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid - * array size. - * status is only updated when these errors occur. - */ -void sli_mvp_pb_config_array_full(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols, - int vecstride, - int rowstride, - int colstride, - sl_status_t *status); - -/** - * @brief - * Configure a 3D MVP array in a program in NHWC or "row major" style. - * - * @note - * NHWC: N = batch, H = height, W = width, C = channel. - * NHWC memory ordering is "row major" within each batch, and is the default - * memory ordering used in TensorFlow. - * Since MVP handles only three dimensions, we silently treat n (batches) - * of nhwc as 1. - * - * @param[in] prog The program to configure. - * @param[in] index Array index. Values in the range 0-4 - * @param[in] addr Base address of the array. - * @param[in] datatype Datatype of each array element. - * @param[in] h Matrix height (rows, DIM1, major dimension). - * @param[in] w Matrix width (cols, DIM2). - * @param[in] c Matrix depth (vecs or channels, DIM0, minor dimension). - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array - * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid - * array size. - * status is only updated when these errors occur. - */ -void sli_mvp_pb_config_array_nhwc(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short h, - unsigned short w, - unsigned short c, - sl_status_t *status); - -/** - * @brief - * Configure a specific 2D matrix in a program in "row major" style. - * - * @param[in] prog The program to configure. - * @param[in] index index. Values in the range 0-4 - * @param[in] addr Base address of the matrix. - * @param[in] datatype Datatype of each matrix element. - * @param[in] rows Number of rows (DIM1, major dimension). - * @param[in] cols Number of columns (DIM2, minor dimension). - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array - * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid - * matrix size. - * status is only updated when these errors occur. - */ -void sli_mvp_pb_config_matrix(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short rows, - unsigned short cols, - sl_status_t *status); - -/** - * @brief - * Configure a specific vector in a program. - * - * @param[in] prog The program to configure. - * @param[in] index index. Values in the range 0-4 - * @param[in] addr Base address of the vector. - * @param[in] datatype Datatype of each vector element. - * @param[in] len Number of elements in vector (DIM2). - * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array - * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid - * vector size. - * status is only updated when these errors occur. - */ -void sli_mvp_pb_config_vector(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short len, - sl_status_t *status); - -/** - * @brief - * End a MVP program loop. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - */ -void sli_mvp_pb_end_loop(sli_mvp_program_context_t *p); - -/** - * @brief - * Execute a MVP program. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - * - * @return - * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on - * MVP faults. - */ -sl_status_t sli_mvp_pb_execute_program(sli_mvp_program_context_t *p); - -/** - * @brief - * Initialize a MVP program context. Must be called once before a group of - * MVP programs are executed. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - */ -void sli_mvp_pb_init_program(sli_mvp_program_context_t *p); - -/** - * @brief - * Set array dimension index incrementer in previous loop iterator. - * When used after a call to @ref sli_mvp_end_loop(), the index will increment - * on loop exit. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - * @param[in] array_index Index of array. - * @param[in] dimension Dimension to increment. - */ -void sli_mvp_pb_postloop_incr_dim(sli_mvp_program_context_t *p, uint8_t array_index, uint8_t dimension); - -/** - * @brief - * Set array dimension reset in previous loop iterator. - * When used after a call to @ref sli_mvp_end_loop(), the index will be reset - * on loop exit. - * - * @note - * This function is part of the MVP program builder (pb) convenience API. - * - * @param[in] p Pointer to MVP program context. - * @param[in] array_index Index of array. - * @param[in] dimension Dimension to reset. - */ -void sli_mvp_pb_postloop_reset_dim(sli_mvp_program_context_t *p, uint8_t array_index, uint8_t dimension); - -/** @} (end addtogroup mvp) */ -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif // SL_MVP_H +/***************************************************************************//** + * @file + * @brief MVP Driver. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MVP_H +#define SL_MVP_H + +#include "sl_status.h" +#include "em_device.h" +#include "sl_math_types.h" +#include "sl_mvp_types.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup mvp MVP API + * @{ + ******************************************************************************/ + +// Defines for each of the 8 MVP registers. +#define SLI_MVP_R0 0 +#define SLI_MVP_R1 1 +#define SLI_MVP_R2 2 +#define SLI_MVP_R3 3 +#define SLI_MVP_R4 4 +#define SLI_MVP_R5 5 +#define SLI_MVP_R6 6 +#define SLI_MVP_R7 7 + +// Defines for Loop/Stream increments. +#define SLI_MVP_NOINCR 0x0 +#define SLI_MVP_NORST 0x0 +#define SLI_MVP_INCRDIM0 0x1 +#define SLI_MVP_INCRDIM1 0x2 +#define SLI_MVP_INCRDIM2 0x4 +#define SLI_MVP_INCRDIM_VEC SLI_MVP_INCRDIM0 +#define SLI_MVP_INCRDIM_ROW SLI_MVP_INCRDIM1 +#define SLI_MVP_INCRDIM_COL SLI_MVP_INCRDIM2 + +// Alternative INCRDIM macros, useful when using "NHWC" tensors. +#define SLI_MVP_INCRDIM_DEPTH SLI_MVP_INCRDIM_VEC +#define SLI_MVP_INCRDIM_HEIGHT SLI_MVP_INCRDIM_ROW +#define SLI_MVP_INCRDIM_WIDTH SLI_MVP_INCRDIM_COL + +// Defines for Loop dimension resets. +#define SLI_MVP_NO_DIM_RESET 0x0 +#define SLI_MVP_RESETDIM0 0x1 +#define SLI_MVP_RESETDIM1 0x2 +#define SLI_MVP_RESETDIM2 0x4 +#define SLI_MVP_RESETDIM_VEC SLI_MVP_RESETDIM0 +#define SLI_MVP_RESETDIM_ROW SLI_MVP_RESETDIM1 +#define SLI_MVP_RESETDIM_COL SLI_MVP_RESETDIM2 + +// Alternative RESETDIM macros, useful when using "NHWC" tensors. +#define SLI_MVP_RESETDIM_DEPTH SLI_MVP_RESETDIM_VEC +#define SLI_MVP_RESETDIM_HEIGHT SLI_MVP_RESETDIM_ROW +#define SLI_MVP_RESETDIM_WIDTH SLI_MVP_RESETDIM_COL + +// Defines for Instruction RegLoad/RegStore selection (for STREAM macro). +#define SLI_MVP_REGLOAD0 0 +#define SLI_MVP_REGLOAD1 1 +#define SLI_MVP_REGSTORE 2 + +// Defines for ALUIN macro. +#define SLI_MVP_ALUIN0 0 +#define SLI_MVP_ALUIN1 1 +#define SLI_MVP_ALUIN2 2 +#define SLI_MVP_ENDPROG 1 +#define SLI_MVP_NONE 0 + +// Defines for ALU register modifiers. +#define SLI_MVP_ALUIN_REALZERO 0x1 +#define SLI_MVP_ALUIN_REALNEGATE 0x2 +#define SLI_MVP_ALUIN_IMAGZERO 0x4 +#define SLI_MVP_ALUIN_IMAGNEGATE 0x8 + +// MVP hardware limits. +#define SLI_MVP_MAX_DIM (3U) +#define SLI_MVP_MAX_VECTOR_COUNT ((_MVP_ARRAYDIM0CFG_SIZE_MASK >> _MVP_ARRAYDIM0CFG_SIZE_SHIFT)+ 1U) +#define SLI_MVP_MAX_ROW_LENGTH ((_MVP_ARRAYDIM1CFG_SIZE_MASK >> _MVP_ARRAYDIM1CFG_SIZE_SHIFT)+ 1U) +#define SLI_MVP_MAX_COLUMN_LENGTH ((_MVP_ARRAYDIM2CFG_SIZE_MASK >> _MVP_ARRAYDIM2CFG_SIZE_SHIFT)+ 1U) +#define SLI_MVP_MAX_VECTOR_STRIDE ((_MVP_ARRAYDIM0CFG_STRIDE_MASK >> (_MVP_ARRAYDIM0CFG_STRIDE_SHIFT+1))) +#define SLI_MVP_MIN_VECTOR_STRIDE (-MAX_VECTOR_STRIDE - 1) +#define SLI_MVP_MAX_ROW_STRIDE ((_MVP_ARRAYDIM1CFG_STRIDE_MASK >> (_MVP_ARRAYDIM1CFG_STRIDE_SHIFT+1))) +#define SLI_MVP_MIN_ROW_STRIDE (-MAX_ROW_STRIDE - 1) +#define SLI_MVP_MAX_COLUMN_STRIDE ((_MVP_ARRAYDIM2CFG_STRIDE_MASK >> (_MVP_ARRAYDIM2CFG_STRIDE_SHIFT+1))) +#define SLI_MVP_MIN_COLUMN_STRIDE (-MAX_COLUMN_STRIDE - 1) + +#define SLI_MVP_FP16_MIN (-65504.0f) +#define SLI_MVP_FP16_MAX 65504.0f + +// Array id macro for readability. +#define SLI_MVP_ARRAY(n) (n) + +// Loop id macro for readability. +#define SLI_MVP_LOOP(n) (n) + +// Instruction id macro for readability. +#define SLI_MVP_INSTR(n) (n) + +// Macro to build up ALUOUT field in CFG0. +#define SLI_MVP_ALUOUT(n) ((n) << _MVP_INSTRCFG0_ALUOUTREGID_SHIFT) + +// Macro to build up ALUIN field in CFG0. The SLI_MVP_ALU_* macros should +// be used instead when building up the ALU configuration when no flags are used. +// r - 0-7=R0-R7 +// f - flags, combination of any of these: +// SLI_MVP_ALUIN_REALZERO +// SLI_MVP_ALUIN_REALNEGATE +// SLI_MVP_ALUIN_IMAGZERO +// SLI_MVP_ALUIN_IMAGNEGATE +#define SLI_MVP_ALUIN_X(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN0))) +#define SLI_MVP_ALUIN_Y(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN1))) +#define SLI_MVP_ALUIN_A(r, f) ((((f) << 4) | (r)) << (8 * (SLI_MVP_ALUIN2))) + +// First argument to ALU operation. ALU Input X == ALUIN0. +#define SLI_MVP_ALU_X(reg) SLI_MVP_ALUIN_X(reg, 0) + +// Second argument to ALU operation. ALU Input Y == ALUIN1. +#define SLI_MVP_ALU_Y(reg) SLI_MVP_ALUIN_Y(reg, 0) + +// Third argument to ALU operation. ALU Input A == ALUIN2. +#define SLI_MVP_ALU_A(reg) SLI_MVP_ALUIN_A(reg, 0) + +// Used to specify the output register. ALU Output Z == ALUOUT. +#define SLI_MVP_ALU_Z(reg) SLI_MVP_ALUOUT(reg) + +// Macro to build REGLOAD/REGSTORE field in CFG1. +// SLI_MVP_LOAD() or SLI_MVP_STORE() should be used when building instructions. +#define SLI_MVP_STREAM(s, r, a, i) ((((i) << 7) | ((a) << 4) | 0x8 | (r)) << ((s) * 10)) + +// Specify use of Load channel 0 or 1. +// Example: SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM0) +#define SLI_MVP_LOAD(n, r, a, i) SLI_MVP_STREAM(n, r, a, i) + +// Used when storing a register as part of an instruction. +// Example: SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM0) +#define SLI_MVP_STORE(r, a, i) SLI_MVP_STREAM(SLI_MVP_REGSTORE, r, a, i) + +// Define for MVP operation used in instructions. +#define SLI_MVP_OP(x) (_MVP_INSTRCFG2_ALUOP_ ## x) + +// Loop Increment macro. +#define SLI_MVP_LOOP_INCRDIM(array, dim) ((dim) << (4 * (array))) + +// Loop Reset macro. +#define SLI_MVP_LOOP_RSTDIM(array, dim) ((dim) << (4 * (array))) + +// MVP numerical exceptions flag mask. +#define SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK \ + (MVP_IF_ALUNAN | MVP_IF_ALUOF | MVP_IF_ALUUF \ + | MVP_IF_STORECONVERTOF | MVP_IF_STORECONVERTUF \ + | MVP_IF_STORECONVERTINF | MVP_IF_STORECONVERTNAN) + +/** + * ALU Registers are always represented as a complex float16_t type. + * This structure is used to allow a program to assign value to either + * the real or imaginary part of the ALU register. + */ +typedef struct { + struct { + float16_t real; + float16_t imag; + } value; +} sli_mvp_alu_bitfield_t; + +typedef struct { + union { + uint32_t REGSTATE; ///< ALU Rn Register. + sli_mvp_alu_bitfield_t reg; + }; +} sli_mvp_alu_reg_t; + +typedef struct +{ + sli_mvp_addr_reg_t ADDRCFG; ///< Array Base Address + union { + uint32_t DIM0CFG; ///< Dimension 0 Configuration + struct { + uint32_t size : 10; + uint32_t : 2; + uint32_t basetype : 2; + uint32_t complex : 1; + uint32_t : 1; + uint32_t stride : 12; + uint32_t : 4; + } dim0cfg; + }; + union { + uint32_t DIM1CFG; ///< Dimension 1 Configuration + struct { + uint32_t size : 10; + uint32_t : 6; + uint32_t stride : 12; + uint32_t : 4; + } dim1cfg; + }; + union { + uint32_t DIM2CFG; ///< Dimension 2 Configuration + struct { + uint32_t size : 10; + uint32_t : 6; + uint32_t stride : 12; + uint32_t : 4; + } dim2cfg; + }; +} sli_mvp_array_reg_t; + +typedef struct +{ + union { + uint32_t CFG; ///< Loop Configuration + struct { + uint32_t numiters : 10; + uint32_t : 2; + uint32_t array0incrdim0 : 1; + uint32_t array0incrdim1 : 1; + uint32_t array0incrdim2 : 1; + uint32_t : 1; + uint32_t array1incrdim0 : 1; + uint32_t array1incrdim1 : 1; + uint32_t array1incrdim2 : 1; + uint32_t : 1; + uint32_t array2incrdim0 : 1; + uint32_t array2incrdim1 : 1; + uint32_t array2incrdim2 : 1; + uint32_t : 1; + uint32_t array3incrdim0 : 1; + uint32_t array3incrdim1 : 1; + uint32_t array3incrdim2 : 1; + uint32_t : 1; + uint32_t array4incrdim0 : 1; + uint32_t array4incrdim1 : 1; + uint32_t array4incrdim2 : 1; + uint32_t : 1; + } cfg; + }; + union { + uint32_t RST; ///< Loop Reset + struct { + uint32_t : 12; + uint32_t array0resetdim0 : 1; + uint32_t array0resetdim1 : 1; + uint32_t array0resetdim2 : 1; + uint32_t : 1; + uint32_t array1resetdim0 : 1; + uint32_t array1resetdim1 : 1; + uint32_t array1resetdim2 : 1; + uint32_t : 1; + uint32_t array2resetdim0 : 1; + uint32_t array2resetdim1 : 1; + uint32_t array2resetdim2 : 1; + uint32_t : 1; + uint32_t array3resetdim0 : 1; + uint32_t array3resetdim1 : 1; + uint32_t array3resetdim2 : 1; + uint32_t : 1; + uint32_t array4resetdim0 : 1; + uint32_t array4resetdim1 : 1; + uint32_t array4resetdim2 : 1; + uint32_t : 1; + } rst; + }; +} sli_mvp_loop_reg_t; + +typedef struct { + union { + uint32_t CFG0; ///< Instruction Configuration Word 0. + struct { + uint32_t aluin0regid : 3; + uint32_t : 1; + uint32_t aluin0realzero : 1; + uint32_t aluin0realnegate : 1; + uint32_t aluin0imagzero : 1; + uint32_t aluin0imagnegate : 1; + uint32_t aluin1regid : 3; + uint32_t : 1; + uint32_t aluin1realzero : 1; + uint32_t aluin1realnegate : 1; + uint32_t aluin1imagzero : 1; + uint32_t aluin1imagnegate : 1; + uint32_t aluin2regid : 3; + uint32_t : 1; + uint32_t aluin2realzero : 1; + uint32_t aluin2realnegate : 1; + uint32_t aluin2imagzero : 1; + uint32_t aluin2imagnegate : 1; + uint32_t : 4; + uint32_t aluoutregid : 3; + uint32_t : 1; + } cfg0; + }; + union { + uint32_t CFG1; ///< Instruction Configuration Word 1. + struct { + uint32_t istream0regid : 3; + uint32_t istream0load : 1; + uint32_t istream0arrayid : 3; + uint32_t istream0arrayincrdim0 : 1; + uint32_t istream0arrayincrdim1 : 1; + uint32_t istream0arrayincrdim2 : 1; + uint32_t istream1regid : 3; + uint32_t istream1load : 1; + uint32_t istream1arrayid : 3; + uint32_t istream1arrayincrdim0 : 1; + uint32_t istream1arrayincrdim1 : 1; + uint32_t istream1arrayincrdim2 : 1; + uint32_t ostreamregid : 3; + uint32_t ostreamstore : 1; + uint32_t ostreamarrayid : 3; + uint32_t ostreamarrayincrdim0 : 1; + uint32_t ostreamarrayincrdim1 : 1; + uint32_t ostreamarrayincrdim2 : 1; + uint32_t : 2; + } cfg1; + }; + union { + uint32_t CFG2; ///< Instruction Configuration Word 2. + struct { + uint32_t loop0begin : 1; + uint32_t loop0end : 1; + uint32_t loop1begin : 1; + uint32_t loop1end : 1; + uint32_t loop2begin : 1; + uint32_t loop2end : 1; + uint32_t loop3begin : 1; + uint32_t loop3end : 1; + uint32_t loop4begin : 1; + uint32_t loop4end : 1; + uint32_t loop5begin : 1; + uint32_t loop5end : 1; + uint32_t loop6begin : 1; + uint32_t loop6end : 1; + uint32_t loop7begin : 1; + uint32_t loop7end : 1; + uint32_t : 4; + uint32_t aluop : 9; + uint32_t : 2; + uint32_t endprog : 1; + } cfg2; + }; +} sli_mvp_instr_reg_t; + +/** + * Represents a single MVP program that can be loaded onto the hardware. A full + * algorithm can potentially be represented by a number of different program + * structures. + */ +typedef struct { + sli_mvp_alu_reg_t ALU[8U]; + sli_mvp_array_reg_t ARRAY[5U]; + sli_mvp_loop_reg_t LOOP[8U]; + sli_mvp_instr_reg_t INSTR[8U]; + uint32_t CMD; +} sli_mvp_program_t; + +/** + * Type used when configuring performance counters. + */ +typedef enum { + SLI_MVP_PERFCNT_CYCLES = 0, ///< Count MVP cycles + SLI_MVP_PERFCNT_INSTRUCTIONS = 1, ///< Count MVP instructions + SLI_MVP_PERFCNT_STALL = 2 ///< Count number of stalls +} sli_mvp_perfcnt_t; + +typedef enum { + SLI_MVP_DATATYPE_UINT8 = 0x0, + SLI_MVP_DATATYPE_INT8 = 0x1, + SLI_MVP_DATATYPE_BINARY16 = 0x2, + SLI_MVP_DATATYPE_COMPLEX_UINT8 = 0x4, + SLI_MVP_DATATYPE_COMPLEX_INT8 = 0x5, + SLI_MVP_DATATYPE_COMPLEX_BINARY16 = 0x6 +} sli_mvp_datatype_t; + +/** + * Context for using the MVP program builder helper functions. + */ +typedef struct { + sli_mvp_program_t program[2]; ///< Two MVP program buffers. + uint32_t loop_begin_end[8]; ///< Storage for instruction loop begin/end bits. + uint32_t loop_stack[8]; ///< Stack for keeping track of loop nesting level. + sli_mvp_program_t *p; ///< Pointer to active MVP program buffer. + int prog_index; ///< Index used to select one of two possible MVP program buffers. + int last_loop; ///< Loop counter. + int last_instr; ///< Instruction counter. + int loop_level; ///< Loop nesting level. +} sli_mvp_program_context_t; + +/** + * @brief + * Clear MVP exception and fault flags. + * + * @param[in] flags + * A bit mask with one or more flags to clear. Refer to + * sli_mvp_get_error_flags() for a description of bit positions. + */ +void sli_mvp_clear_error_flags(uint32_t flags); + +/** + * @brief + * Get an MVP exception or fault errorcode and optional descriptive + * error message. + * + * @details + * Intended use of this function is to call it repeatedly to iterate over + * existing errors and get errorcodes and optional error message strings. + * + * @param[out] error_code + * The assigned sl_status_t errorcode. + * + * @param[in,out] error_message + * A descriptive error message string. Input a NULL pointer to skip + * the error message. + * + * @param[in] buffer_length + * The size of the error_message buffer. + * + * @return + * Return SL_STATUS_OK when an error is present, this indicates that + * error_code and optionally error_message output parameters are valid. + * Return SL_STATUS_NOT_FOUND when no error to report. + */ +sl_status_t sli_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length); + +/** + * @brief + * Get MVP exception and fault flags. + * + * @details + * The value returned is a bitfield with a layout matching the MVP->IF + * registers numerical exception bit positions. In addition bit 0 is used as + * a concatenation of the fault flags. + * + * @return + * MVP exception and fault flags. + */ +uint32_t sli_mvp_get_error_flags(void); + +/** + * @brief + * Initialize the MVP hardware. + * + * @details + * This function must be called once before any of the other functions are + * used. This function will configure the MVP hardware based on the content + * of the sl_driver_mvp_config.h file. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_init(void); + +/** + * @brief + * De-Initialize the MVP hardware. + * + * @details + * This function can be called when the MVP hardware is no longer being used. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_deinit(void); + +/** + * @brief + * Enable the MVP hardware for command execution. + * + * @details + * This function must be called before a MVP program can be executed. + * + * @note + * The MVP will automatically be disabled by the driver when the command + * has completed execution. + */ +void sli_mvp_cmd_enable(void); + +/** + * @brief + * If there is a program running, wait for it to to complete. + * + * @return + * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on + * MVP faults. + */ +sl_status_t sli_mvp_cmd_wait_for_completion(void); + +/** + * @brief + * Execute a single program on the MVP hardware. + * + * @details + * Used to schedule a program for execution. + * + * @param[in] program + * The program to run on the MVP hardware. + * + * @param[in] wait + * If true then the function will wait for the program to complete before + * returning to the caller. If false then the function will return to the + * caller before the program is completed. + * + * @return + * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on + * MVP faults. + */ +sl_status_t sli_mvp_prog_execute(sli_mvp_program_t *program, bool wait); + + +// Functions for setting register value in an MVP program +void sli_mvp_prog_set_reg_s8(sli_mvp_program_t *prog, uint8_t reg, int8_t value); +void sli_mvp_prog_set_reg_s8c(sli_mvp_program_t *prog, uint8_t reg, int8_t real, int8_t imag); +void sli_mvp_prog_set_reg_s16(sli_mvp_program_t *prog, uint8_t reg, int16_t value); +void sli_mvp_prog_set_reg_s16c(sli_mvp_program_t *prog, uint8_t reg, int16_t real, int16_t imag); +void sli_mvp_prog_set_reg_s32(sli_mvp_program_t *prog, uint8_t reg, int32_t value); +void sli_mvp_prog_set_reg_s32c(sli_mvp_program_t *prog, uint8_t reg, int32_t real, int32_t imag); +void sli_mvp_prog_set_reg_f16(sli_mvp_program_t *prog, uint8_t reg, float16_t value); +void sli_mvp_prog_set_reg_f16c(sli_mvp_program_t *prog, uint8_t reg, float16_t real, float16_t imag); +void sli_mvp_prog_set_reg_f32(sli_mvp_program_t *prog, uint8_t reg, float value); +void sli_mvp_prog_set_reg_f32c(sli_mvp_program_t *prog, uint8_t reg, float real, float imag); + +/** + * @brief + * Configure a specific array in a program, with possibility to specify strides. + * + * @param[in] prog The program to configure. + * @param[in] index Array index. Values in the range 0-4. + * @param[in] addr Base address of the array. + * @param[in] datatype Datatype of each array element. + * @param[in] vecs Number of vectors (DIM0). + * @param[in] rows Number of rows (DIM1). + * @param[in] cols Number of columns (DIM2). + * @param[in] vecstride Number of elements to advance when moving to the next vector (can be negative). + * @param[in] rowstride Number of elements to advance when moving to the next row (can be negative). + * @param[in] colstride Number of elements to advance when moving to the next column (can be negative). + */ +void sli_mvp_prog_set_array_full(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols, + int vecstride, + int rowstride, + int colstride); + +/** + * @brief + * Configure a specific array in a program. + * + * @note + * The resulting memory ordering will be "NCHW" i.e. "vector major". + * This aligns with the memory ordering of a C-language 3D array. + * + * @param[in] prog The program to configure. + * @param[in] index Array index. Values in the range 0-4 + * @param[in] addr Base address of the array. + * @param[in] datatype Datatype of each array element. + * @param[in] vecs Number of vectors (DIM0, major dimension). + * @param[in] rows Number of rows (DIM1). + * @param[in] cols Number of columns (DIM2, minor dimension). + */ +void sli_mvp_prog_set_array(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols); + +/** + * @brief + * Configure a specific vector in a program. + * + * @param[in] prog The program to configure. + * @param[in] index index. Values in the range 0-4 + * @param[in] addr Base address of the vector. + * @param[in] datatype Datatype of each vector element. + * @param[in] len Number of elements in vector (DIM2). + */ +void sli_mvp_prog_set_vector(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short len); + +/** + * @brief + * Configure a specific 2D matrix in a program. + * + * @note + * The resulting memory ordering will be "row major". + * + * @param[in] prog The program to configure. + * @param[in] index index. Values in the range 0-4 + * @param[in] addr Base address of the matrix. + * @param[in] datatype Datatype of each matrix element. + * @param[in] rows Number of rows (DIM1, major dimension). + * @param[in] cols Number of columns (DIM2, minor dimension). + */ +void sli_mvp_prog_set_matrix(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short rows, + unsigned short cols); + +/** + * @brief + * Configure a specific instruction in a program. + * + * @param[in] prog The program to configure. + * @param[in] index Instruction index. Values in the range 0-7 + * @param[in] opcode Operation to perform. + * @param[in] alu_cfg ALU configuration specifying input/output registers to use. + * @param[in] load_cfg Load configuration, specifying 0-2 load streams to use. + * @param[in] store_cfg Store configuration, specifying 0-1 store stream to use. + * @param[in] end True if this is the last instruction of the program, false otherwise. + */ +void sli_mvp_prog_set_instr(sli_mvp_program_t *prog, + uint8_t index, + uint32_t opcode, + uint32_t alu_cfg, + uint32_t load_cfg, + uint32_t store_cfg, + bool end); + +/** + * @brief + * Configure a specific loop in a program. + * + * @param[in] prog The program to configure. + * @param[in] index Loop index. Value in the range 0-7. + * @param[in] count Number of iterations. Value in the range 1-1024. + * @param[in] istart Start instruction of this loop. + * @param[in] iend End instruction of this loop. + * @param[in] incrarray Optional array increment configuration. + * @param[in] rstarray Optional array index reset configuration. + */ +void sli_mvp_prog_set_loop(sli_mvp_program_t *prog, + uint8_t index, + unsigned short count, + uint8_t istart, + uint8_t iend, + uint32_t incrarray, + uint32_t rstarray); + +/** + * @brief + * Configure one of the performance counters. + * + * @details + * Each of the performance counters can track different events. What event to count + * is configurable using the type parameter. + * + * @param[in] id + * The id of the performance counter to configure. + * + * @param[in] type + * Type of event to count. + */ +void sli_mvp_perfcnt_conf(unsigned id, sli_mvp_perfcnt_t type); + +/** + * @brief + * Reset all performance counters. + */ +void sli_mvp_perfcnt_reset_all(void); + +/** + * @brief + * Fetch the current aggregated value of a performance counter. + * + * @param[in] id + * The id of the performance counter to configure. + * + * @return + * Performance counter value. + */ +uint32_t sli_mvp_perfcnt_get(unsigned id); + +/** + * @brief + * Reset program count counter. + */ +void sli_mvp_progcnt_reset(void); + +/** + * @brief + * Fetch the current aggregated value of the program count counter. + * + * @return + * Program count counter value. + */ +uint32_t sli_mvp_progcnt_get(void); + +/** + * @brief + * Start a MVP program loop. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + * @param[in] iterations Loop count. + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER when loop count is exhausted. + * status is only updated when this error occur. + */ +void sli_mvp_pb_begin_loop(sli_mvp_program_context_t *p, int iterations, sl_status_t *status); + +/** + * @brief + * Begin a MVP program, will initialize part of the program context. + * Must be called once for each MVP program, and prior to any loop, compute + * or execute functions. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + */ +void sli_mvp_pb_begin_program(sli_mvp_program_context_t *p); + +/** + * @brief + * Insert a MVP instruction in the program. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + * @param[in] opcode Instruction opcode. + * @param[in] alu_cfg Instruction ALU configuration. + * @param[in] load_cfg Instruction load configuration. + * @param[in] store_cfg Instruction store configuration. + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER when instruction count is exhausted. + * status is only updated when this error occur. + */ +void sli_mvp_pb_compute(sli_mvp_program_context_t *p, uint32_t opcode, uint32_t alu_cfg, uint32_t load_cfg, uint32_t store_cfg, sl_status_t *status); + +/** + * @brief + * Configure a specific 3D array in a program. + * + * @param[in] prog The program to configure. + * @param[in] index Array index. Values in the range 0-4. + * @param[in] addr Base address of the array. + * @param[in] datatype Datatype of each array element. + * @param[in] vecs Number of vectors (DIM0). + * @param[in] rows Number of rows (DIM1). + * @param[in] cols Number of columns (DIM2). + * @param[in] vecstride Number of elements to advance when moving to the next vector (can be negative). + * @param[in] rowstride Number of elements to advance when moving to the next row (can be negative). + * @param[in] colstride Number of elements to advance when moving to the next column (can be negative). + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array + * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid + * array size. + * status is only updated when these errors occur. + */ +void sli_mvp_pb_config_array_full(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols, + int vecstride, + int rowstride, + int colstride, + sl_status_t *status); + +/** + * @brief + * Configure a 3D MVP array in a program in NHWC or "row major" style. + * + * @note + * NHWC: N = batch, H = height, W = width, C = channel. + * NHWC memory ordering is "row major" within each batch, and is the default + * memory ordering used in TensorFlow. + * Since MVP handles only three dimensions, we silently treat n (batches) + * of nhwc as 1. + * + * @param[in] prog The program to configure. + * @param[in] index Array index. Values in the range 0-4 + * @param[in] addr Base address of the array. + * @param[in] datatype Datatype of each array element. + * @param[in] h Matrix height (rows, DIM1, major dimension). + * @param[in] w Matrix width (cols, DIM2). + * @param[in] c Matrix depth (vecs or channels, DIM0, minor dimension). + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array + * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid + * array size. + * status is only updated when these errors occur. + */ +void sli_mvp_pb_config_array_nhwc(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short h, + unsigned short w, + unsigned short c, + sl_status_t *status); + +/** + * @brief + * Configure a specific 2D matrix in a program in "row major" style. + * + * @param[in] prog The program to configure. + * @param[in] index index. Values in the range 0-4 + * @param[in] addr Base address of the matrix. + * @param[in] datatype Datatype of each matrix element. + * @param[in] rows Number of rows (DIM1, major dimension). + * @param[in] cols Number of columns (DIM2, minor dimension). + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array + * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid + * matrix size. + * status is only updated when these errors occur. + */ +void sli_mvp_pb_config_matrix(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short rows, + unsigned short cols, + sl_status_t *status); + +/** + * @brief + * Configure a specific vector in a program. + * + * @param[in] prog The program to configure. + * @param[in] index index. Values in the range 0-4 + * @param[in] addr Base address of the vector. + * @param[in] datatype Datatype of each vector element. + * @param[in] len Number of elements in vector (DIM2). + * @param[out] status Returns SL_STATUS_INVALID_PARAMETER if an invalid array + * index is specified. Returns SL_STATUS_INVALID_RANGE if invalid + * vector size. + * status is only updated when these errors occur. + */ +void sli_mvp_pb_config_vector(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short len, + sl_status_t *status); + +/** + * @brief + * End a MVP program loop. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + */ +void sli_mvp_pb_end_loop(sli_mvp_program_context_t *p); + +/** + * @brief + * Execute a MVP program. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + * + * @return + * SL_STATUS_OK on success, SL_STATUS_COMPUTE_DRIVER_FAULT on + * MVP faults. + */ +sl_status_t sli_mvp_pb_execute_program(sli_mvp_program_context_t *p); + +/** + * @brief + * Initialize a MVP program context. Must be called once before a group of + * MVP programs are executed. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + */ +void sli_mvp_pb_init_program(sli_mvp_program_context_t *p); + +/** + * @brief + * Set array dimension index incrementer in previous loop iterator. + * When used after a call to @ref sli_mvp_end_loop(), the index will increment + * on loop exit. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + * @param[in] array_index Index of array. + * @param[in] dimension Dimension to increment. + */ +void sli_mvp_pb_postloop_incr_dim(sli_mvp_program_context_t *p, uint8_t array_index, uint8_t dimension); + +/** + * @brief + * Set array dimension reset in previous loop iterator. + * When used after a call to @ref sli_mvp_end_loop(), the index will be reset + * on loop exit. + * + * @note + * This function is part of the MVP program builder (pb) convenience API. + * + * @param[in] p Pointer to MVP program context. + * @param[in] array_index Index of array. + * @param[in] dimension Dimension to reset. + */ +void sli_mvp_pb_postloop_reset_dim(sli_mvp_program_context_t *p, uint8_t array_index, uint8_t dimension); + +/** @} (end addtogroup mvp) */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SL_MVP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_hal.h b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_hal.h index 089f271..f7e897e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_hal.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_hal.h @@ -1,140 +1,140 @@ -/***************************************************************************//** - * @file - * @brief MVP HAL Driver. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MVP_HAL_H -#define SL_MVP_HAL_H - -#include "sl_status.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -typedef void (*sli_mvp_enable_callback)(void); -typedef void (*sli_mvp_disable_callback)(void); -typedef bool (*sli_mvp_isr_callback)(void); - -/** - * MVP configuration parameters. - */ -typedef struct { - bool use_dma; - unsigned dma_ch; -} sli_mvp_hal_config_t; - -/** - * @brief - * Initialize the MVP hardware. - * - * @details - * This function must be called once before any of the other functions are - * used. This function will configure the MVP hardware based on the content - * of the sl_driver_mvp_config.h file. - * - * @param[in] enable Pointer to the function that will be called when the MVP shall be enabled. - * @param[in] disable Pointer to the function that will be called when the MVP shall be disabled. - * @param[in] isr Pointer to the function that will be called when an interrupt occurs. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_hal_init(sli_mvp_enable_callback enable, sli_mvp_disable_callback disable, sli_mvp_isr_callback isr); - -/** - * @brief - * De-Initialize the MVP hardware. - * - * @details - * This function can be called when the MVP hardware is no longer being used. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_hal_deinit(void); - -/** - * @brief - * Configure the operation of the MVP driver. - * - * @details - * This function can be used to reconfigure the MVP driver behavior after - * sli_mvp_init is called. This function can be used to switch between using - * DMA and CPU to load programs at runtime. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_hal_config(sli_mvp_hal_config_t *config); - -/** - * @brief - * Load a program into the MVP registers. - * - * @param[in] src Pointer to the program. - * @param[in] dst Pointer to the MVP register where the program shall be loaded. - * @param[in] length Length of the program in bytes. - * - * @return - * SL_STATUS_OK on success, other value on failure. - */ -sl_status_t sli_mvp_hal_load_program(void *src, void *dst, size_t length); - -/** - * @brief - * Enable the MVP for program execution. This function must be called before - * the MVP command is set and the program is started. - */ -void sli_mvp_hal_cmd_enable(void); - -/** - * @brief - * Check if a program is running. - * - * @return - * True if a program is running, else false. - */ -bool sli_mvp_hal_cmd_is_busy(void); - -/** - * @brief - * If there is a program running, wait for it to to complete. - */ -void sli_mvp_hal_cmd_wait_for_completion(void); - -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif //SL_MVP_HAL_H +/***************************************************************************//** + * @file + * @brief MVP HAL Driver. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MVP_HAL_H +#define SL_MVP_HAL_H + +#include "sl_status.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +typedef void (*sli_mvp_enable_callback)(void); +typedef void (*sli_mvp_disable_callback)(void); +typedef bool (*sli_mvp_isr_callback)(void); + +/** + * MVP configuration parameters. + */ +typedef struct { + bool use_dma; + unsigned dma_ch; +} sli_mvp_hal_config_t; + +/** + * @brief + * Initialize the MVP hardware. + * + * @details + * This function must be called once before any of the other functions are + * used. This function will configure the MVP hardware based on the content + * of the sl_driver_mvp_config.h file. + * + * @param[in] enable Pointer to the function that will be called when the MVP shall be enabled. + * @param[in] disable Pointer to the function that will be called when the MVP shall be disabled. + * @param[in] isr Pointer to the function that will be called when an interrupt occurs. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_hal_init(sli_mvp_enable_callback enable, sli_mvp_disable_callback disable, sli_mvp_isr_callback isr); + +/** + * @brief + * De-Initialize the MVP hardware. + * + * @details + * This function can be called when the MVP hardware is no longer being used. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_hal_deinit(void); + +/** + * @brief + * Configure the operation of the MVP driver. + * + * @details + * This function can be used to reconfigure the MVP driver behavior after + * sli_mvp_init is called. This function can be used to switch between using + * DMA and CPU to load programs at runtime. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_hal_config(sli_mvp_hal_config_t *config); + +/** + * @brief + * Load a program into the MVP registers. + * + * @param[in] src Pointer to the program. + * @param[in] dst Pointer to the MVP register where the program shall be loaded. + * @param[in] length Length of the program in bytes. + * + * @return + * SL_STATUS_OK on success, other value on failure. + */ +sl_status_t sli_mvp_hal_load_program(void *src, void *dst, size_t length); + +/** + * @brief + * Enable the MVP for program execution. This function must be called before + * the MVP command is set and the program is started. + */ +void sli_mvp_hal_cmd_enable(void); + +/** + * @brief + * Check if a program is running. + * + * @return + * True if a program is running, else false. + */ +bool sli_mvp_hal_cmd_is_busy(void); + +/** + * @brief + * If there is a program running, wait for it to to complete. + */ +void sli_mvp_hal_cmd_wait_for_completion(void); + +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif //SL_MVP_HAL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_program_area.h b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_program_area.h index 36f8149..932b66a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_program_area.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_program_area.h @@ -1,93 +1,93 @@ -/***************************************************************************//** - * @file - * @brief MVP Driver program memory allocator. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MVP_PROGRAM_AREA_H -#define SL_MVP_PROGRAM_AREA_H - -#include "sl_mvp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/***************************************************************************//** - * @addtogroup mvp MVP API - * @{ - ******************************************************************************/ - -/** - * @brief - * Get MVP program buffer. - * - * @details - * This function returns a pointer to a MVP program buffer located in RAM. - * - * @return - * Pointer to MVP program buffer. - */ -sli_mvp_program_t *sli_mvp_get_program_area_single(void); - -/** - * @brief - * Get a double MVP program buffer. - * - * @details - * This function returns a pointer to an array of two MVP program buffers - * located in RAM. With two program buffers it is possible to generate the - * next MVP program while current program is executing (ping-pong buffering). - * - * @return - * Pointer to array of two MVP program buffers. - */ -sli_mvp_program_t *sli_mvp_get_program_area_double(void); - -/** - * @brief - * Get a full MVP program buffer context. - * - * @details - * This function returns a pointer to a MVP program context located in RAM. - * A MVP program context contains two MVP program buffers plus MVP - * program builder bookkeeping data. This context can be used with the - * the MVP program builder APIs (sli_mvp_pb_xxx()). - * - * @return - * Pointer to MVP program buffer context. - */ -sli_mvp_program_context_t *sli_mvp_get_program_area_context(void); - -/** @} (end addtogroup mvp) */ -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif // SL_MVP_PROGRAM_AREA_H +/***************************************************************************//** + * @file + * @brief MVP Driver program memory allocator. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MVP_PROGRAM_AREA_H +#define SL_MVP_PROGRAM_AREA_H + +#include "sl_mvp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup mvp MVP API + * @{ + ******************************************************************************/ + +/** + * @brief + * Get MVP program buffer. + * + * @details + * This function returns a pointer to a MVP program buffer located in RAM. + * + * @return + * Pointer to MVP program buffer. + */ +sli_mvp_program_t *sli_mvp_get_program_area_single(void); + +/** + * @brief + * Get a double MVP program buffer. + * + * @details + * This function returns a pointer to an array of two MVP program buffers + * located in RAM. With two program buffers it is possible to generate the + * next MVP program while current program is executing (ping-pong buffering). + * + * @return + * Pointer to array of two MVP program buffers. + */ +sli_mvp_program_t *sli_mvp_get_program_area_double(void); + +/** + * @brief + * Get a full MVP program buffer context. + * + * @details + * This function returns a pointer to a MVP program context located in RAM. + * A MVP program context contains two MVP program buffers plus MVP + * program builder bookkeeping data. This context can be used with the + * the MVP program builder APIs (sli_mvp_pb_xxx()). + * + * @return + * Pointer to MVP program buffer context. + */ +sli_mvp_program_context_t *sli_mvp_get_program_area_context(void); + +/** @} (end addtogroup mvp) */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SL_MVP_PROGRAM_AREA_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_types.h b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_types.h index d6900a0..765d76b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_types.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_types.h @@ -1,56 +1,56 @@ -/***************************************************************************//** - * @file - * @brief MVP Type definitions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MVP_TYPES_H -#define SL_MVP_TYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/***************************************************************************//** - * @addtogroup mvp MVP API - * @{ - ******************************************************************************/ - -#if !defined(SLI_MVP_ADDR_REG_TYPE) -#define SLI_MVP_ADDR_REG_TYPE uint32_t -#endif - -typedef SLI_MVP_ADDR_REG_TYPE sli_mvp_addr_reg_t; - -/** @} (end addtogroup mvp) */ -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif // SL_MVP_TYPES_H +/***************************************************************************//** + * @file + * @brief MVP Type definitions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MVP_TYPES_H +#define SL_MVP_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup mvp MVP API + * @{ + ******************************************************************************/ + +#if !defined(SLI_MVP_ADDR_REG_TYPE) +#define SLI_MVP_ADDR_REG_TYPE uint32_t +#endif + +typedef SLI_MVP_ADDR_REG_TYPE sli_mvp_addr_reg_t; + +/** @} (end addtogroup mvp) */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SL_MVP_TYPES_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_util.h b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_util.h index 8dd117c..b6f14b1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_util.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/inc/sl_mvp_util.h @@ -1,111 +1,111 @@ -/***************************************************************************//** - * @file - * @brief MVP Driver Utility functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MVP_UTIL_H -#define SL_MVP_UTIL_H - -#include "sl_mvp.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/***************************************************************************//** - * @addtogroup mvp MVP API - * @{ - ******************************************************************************/ - -/** - * @brief - * Factorize a number into factors that are not allowed to exceed a - * given maximum value. - * - * @param[in] number Number to factorize. - * @param[in] max Maximum factor value allowed. - * @param[out] m Factor. - * @param[out] n Factor. - * - * @return - * @ref SL_STATUS_OK on success, SL_STATUS_FAIL when unable to factorize. - */ -sl_status_t sli_mvp_util_factorize_number(uint32_t number, - uint32_t max, - uint32_t *m, - uint32_t *n); - -/** - * @brief - * Clear memory using MVP. - * Will clear 2 * batches * vecs * rows * cols bytes in memory. - * This function is a preliminary version of a general purpose function. - * - * @note - * The function will not wait for MVP execution to complete before exit. - * - * @param[in] p Pointer to an initialized program context. - * @param[in] dst Base address of memory area to clear, must be 4-byte aligned. - * @param[in] batches Batches. - * @param[in] vecs Vector dimension size. - * @param[in] rows Row dimension size. - * @param[in] cols Column dimension size. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sli_mvp_util_memclr_f16(sli_mvp_program_context_t *p, - void *dst, - unsigned short batches, - unsigned short vecs, - unsigned short rows, - unsigned short cols); - -/** - * @brief - * Find out if a pointer is word aligned. - * - * @param[in] pointer The pointer to check. - * - * @return - * True if the pointer is word aligned, false if not. - */ -__INLINE bool sli_mvp_util_is_pointer_word_aligned(const void *pointer) -{ - return ((size_t)pointer & 3) == 0; -} - -/** @} (end addtogroup mvp) */ -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif // SL_MVP_UTIL_H +/***************************************************************************//** + * @file + * @brief MVP Driver Utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MVP_UTIL_H +#define SL_MVP_UTIL_H + +#include "sl_mvp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup mvp MVP API + * @{ + ******************************************************************************/ + +/** + * @brief + * Factorize a number into factors that are not allowed to exceed a + * given maximum value. + * + * @param[in] number Number to factorize. + * @param[in] max Maximum factor value allowed. + * @param[out] m Factor. + * @param[out] n Factor. + * + * @return + * @ref SL_STATUS_OK on success, SL_STATUS_FAIL when unable to factorize. + */ +sl_status_t sli_mvp_util_factorize_number(uint32_t number, + uint32_t max, + uint32_t *m, + uint32_t *n); + +/** + * @brief + * Clear memory using MVP. + * Will clear 2 * batches * vecs * rows * cols bytes in memory. + * This function is a preliminary version of a general purpose function. + * + * @note + * The function will not wait for MVP execution to complete before exit. + * + * @param[in] p Pointer to an initialized program context. + * @param[in] dst Base address of memory area to clear, must be 4-byte aligned. + * @param[in] batches Batches. + * @param[in] vecs Vector dimension size. + * @param[in] rows Row dimension size. + * @param[in] cols Column dimension size. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sli_mvp_util_memclr_f16(sli_mvp_program_context_t *p, + void *dst, + unsigned short batches, + unsigned short vecs, + unsigned short rows, + unsigned short cols); + +/** + * @brief + * Find out if a pointer is word aligned. + * + * @param[in] pointer The pointer to check. + * + * @return + * True if the pointer is word aligned, false if not. + */ +__INLINE bool sli_mvp_util_is_pointer_word_aligned(const void *pointer) +{ + return ((size_t)pointer & 3) == 0; +} + +/** @} (end addtogroup mvp) */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SL_MVP_UTIL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp.c b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp.c index dc647b9..887a6b0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp.c @@ -1,637 +1,637 @@ -/***************************************************************************//** - * @file - * @brief MVP Core driver. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "em_device.h" -#include "sl_assert.h" -#include "sl_mvp_hal.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_STATUS_STRING_PRESENT) -#include "sl_status_string_config.h" -#endif - -#include -#include - -#define NUM_PERF_CNT 2 -#define MAX_NUM_ARRAYS 5 -#define MAX_NUM_LOOPS 8 -#define MAX_NUM_INSTRUCTIONS 8 -#define MAX_NUM_REGS 8 -#define MAX_ARRAY_DIM_SIZE 1024 -#define MAX_ARRAY_STRIDE_SIZE 2047 -#define MIN_ARRAY_STRIDE_SIZE -2048 -#define MAX_LOOP_COUNT 1024 - -#define SLI_MVP_FAULT_MASK (MVP_IF_LOOPFAULT | MVP_IF_BUSERRFAULT \ - | MVP_IF_BUSALIGNFAULT | MVP_IF_ALUFAULT \ - | MVP_IF_ARRAYFAULT) - -static uint32_t mvp_numerical_exception_flags; -static volatile bool mvp_fault_flag; -static uint32_t mvp_program_count = 0; -static volatile uint32_t perfcnt[NUM_PERF_CNT] = { 0 }; -// Software retained MVP registers. -static volatile uint32_t mvp_reg_cfg = MVP_CFG_PERF0CNTSEL_RUN | MVP_CFG_PERF1CNTSEL_STALL | MVP_CFG_PERFCNTEN; -static volatile bool mvp_is_enabled = false; - -static void enable_callback(void) -{ - MVP->EN_SET = MVP_EN_EN; - MVP->IEN_SET = MVP_IEN_PERFCNT0 | MVP_IEN_PERFCNT1 | MVP_IEN_PROGDONE - | SLI_MVP_FAULT_MASK; - MVP->CFG = mvp_reg_cfg; - mvp_is_enabled = true; -} - -static void disable_callback(void) -{ - mvp_reg_cfg = MVP->CFG; - MVP->EN_CLR = MVP_EN_EN; - while (MVP->EN & MVP_EN_DISABLING) - ; - MVP->IEN_CLR = 0xffffffff; - mvp_is_enabled = false; -} - -static bool isr_callback(void) -{ - uint32_t pending, tmp; - bool done = false; - - pending = MVP->IF; - pending &= MVP->IEN; - - if (pending & SLI_MVP_FAULT_MASK) { - mvp_fault_flag = true; - done = true; - } - if (pending & MVP_IF_PROGDONE) { - while (!(MVP->STATUS & MVP_STATUS_IDLE)) { - } - tmp = MVP->PERF[0].CNT; - perfcnt[0] += tmp; - tmp = MVP->PERF[1].CNT; - perfcnt[1] += tmp; - done = true; - } - if (pending & MVP_IF_PERFCNT0) { - perfcnt[0] += (_MVP_PERFCNT_COUNT_MASK + 1); - } - if (pending & MVP_IF_PERFCNT1) { - perfcnt[1] += (_MVP_PERFCNT_COUNT_MASK + 1); - } - - MVP->IF_CLR = pending; - - return done; -} - -void sli_mvp_clear_error_flags(uint32_t flags) -{ - mvp_numerical_exception_flags &= ~(flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK); -} - -sl_status_t sli_mvp_get_error(sl_status_t *error_code, - char *error_message, - uint32_t buffer_length) -{ - if (!error_code) { - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t flag = 0; - uint32_t flags = mvp_numerical_exception_flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; - - if (flags & MVP_IF_ALUNAN) { - *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_NAN; - flag = MVP_IF_ALUNAN; - } else if (flags & MVP_IF_ALUOF) { - *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW; - flag = MVP_IF_ALUOF; - } else if (flags & MVP_IF_ALUUF) { - *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW; - flag = MVP_IF_ALUUF; - - } else if (flags & MVP_IF_STORECONVERTOF) { - *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW; - flag = MVP_IF_STORECONVERTOF; - } else if (flags & MVP_IF_STORECONVERTUF) { - *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW; - flag = MVP_IF_STORECONVERTUF; - } else if (flags & MVP_IF_STORECONVERTINF) { - *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY; - flag = MVP_IF_STORECONVERTINF; - } else if (flags & MVP_IF_STORECONVERTNAN) { - *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN; - flag = MVP_IF_STORECONVERTNAN; - - } else { - return SL_STATUS_NOT_FOUND; - } - - mvp_numerical_exception_flags &= ~flag; - -#if defined(SL_CATALOG_STATUS_STRING_PRESENT) && (SL_STATUS_STRING_ENABLE_COMPUTE == 1) - if (error_message != NULL) { - sl_status_get_string_n(*error_code, error_message, buffer_length); - } -#else - if ((error_message != NULL) && (buffer_length > 0)) { - error_message[0] = '\0'; - } -#endif - - return SL_STATUS_OK; -} - -uint32_t sli_mvp_get_error_flags(void) -{ - return mvp_numerical_exception_flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; -} - -sl_status_t sli_mvp_init(void) -{ - mvp_fault_flag = false; - mvp_numerical_exception_flags = 0U; - return sli_mvp_hal_init(enable_callback, disable_callback, isr_callback); -} - -sl_status_t sli_mvp_deinit(void) -{ - return sli_mvp_hal_deinit(); -} - -void sli_mvp_cmd_enable(void) -{ - sli_mvp_hal_cmd_wait_for_completion(); - sli_mvp_hal_cmd_enable(); -} - -sl_status_t sli_mvp_cmd_wait_for_completion(void) -{ - sli_mvp_hal_cmd_wait_for_completion(); - mvp_numerical_exception_flags |= MVP->IF; - MVP->IF_CLR = SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; - sl_status_t status = mvp_fault_flag ? SL_STATUS_COMPUTE_DRIVER_FAULT : SL_STATUS_OK; - mvp_fault_flag = false; - return status; -} - -sl_status_t sli_mvp_prog_execute(sli_mvp_program_t *program, bool wait) -{ - sl_status_t status; - - program->CMD = MVP_CMD_INIT | MVP_CMD_START; - mvp_program_count++; - if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { - return status; - } - sli_mvp_hal_cmd_enable(); - sli_mvp_hal_load_program(program, &MVP->ALU[0], sizeof(sli_mvp_program_t)); - if (wait) { - status = sli_mvp_cmd_wait_for_completion(); - } - return status; -} - -void sli_mvp_prog_set_reg_s8(sli_mvp_program_t *prog, uint8_t reg, int8_t value) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); -} - -void sli_mvp_prog_set_reg_s8c(sli_mvp_program_t *prog, uint8_t reg, int8_t real, int8_t imag) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); -} - -void sli_mvp_prog_set_reg_s16(sli_mvp_program_t *prog, uint8_t reg, int16_t value) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); -} - -void sli_mvp_prog_set_reg_s16c(sli_mvp_program_t *prog, uint8_t reg, int16_t real, int16_t imag) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); -} - -void sli_mvp_prog_set_reg_s32(sli_mvp_program_t *prog, uint8_t reg, int32_t value) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, (float16_t)value, 0); -} - -void sli_mvp_prog_set_reg_s32c(sli_mvp_program_t *prog, uint8_t reg, int32_t real, int32_t imag) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, (float16_t)real, (float16_t)imag); -} - -void sli_mvp_prog_set_reg_f16(sli_mvp_program_t *prog, uint8_t reg, float16_t value) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); -} - -void sli_mvp_prog_set_reg_f16c(sli_mvp_program_t *prog, uint8_t reg, float16_t real, float16_t imag) -{ - EFM_ASSERT(reg < MAX_NUM_REGS); - - prog->ALU[reg].reg.value.real = real; - prog->ALU[reg].reg.value.imag = imag; -} - -void sli_mvp_prog_set_reg_f32(sli_mvp_program_t *prog, uint8_t reg, float value) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); -} - -void sli_mvp_prog_set_reg_f32c(sli_mvp_program_t *prog, uint8_t reg, float real, float imag) -{ - sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); -} - -void sli_mvp_prog_set_array_full(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols, - int vecstride, - int rowstride, - int colstride) -{ - EFM_ASSERT(index < MAX_NUM_ARRAYS); - EFM_ASSERT(vecs <= MAX_ARRAY_DIM_SIZE); - EFM_ASSERT(rows <= MAX_ARRAY_DIM_SIZE); - EFM_ASSERT(cols <= MAX_ARRAY_DIM_SIZE); - EFM_ASSERT(vecstride >= MIN_ARRAY_STRIDE_SIZE && vecstride <= MAX_ARRAY_STRIDE_SIZE); - EFM_ASSERT(rowstride >= MIN_ARRAY_STRIDE_SIZE && rowstride <= MAX_ARRAY_STRIDE_SIZE); - EFM_ASSERT(colstride >= MIN_ARRAY_STRIDE_SIZE && colstride <= MAX_ARRAY_STRIDE_SIZE); - - uint32_t datatype = (uint32_t)type; - prog->ARRAY[index].DIM0CFG = (((vecs - 1) << _MVP_ARRAYDIM0CFG_SIZE_SHIFT) & _MVP_ARRAYDIM0CFG_SIZE_MASK); - prog->ARRAY[index].DIM1CFG = (((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) & _MVP_ARRAYDIM1CFG_SIZE_MASK); - prog->ARRAY[index].DIM2CFG = (((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) & _MVP_ARRAYDIM2CFG_SIZE_MASK); - - // Set up Array Strides This is a 10-bit signed integer between -512 and +511 - prog->ARRAY[index].DIM0CFG |= ((vecstride << _MVP_ARRAYDIM0CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM0CFG_STRIDE_MASK); - prog->ARRAY[index].DIM1CFG |= ((rowstride << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM1CFG_STRIDE_MASK); - prog->ARRAY[index].DIM2CFG |= ((colstride << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM2CFG_STRIDE_MASK); - - // Set up datatype - prog->ARRAY[index].DIM0CFG |= ((datatype << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT) & _MVP_ARRAYDIM0CFG_BASETYPE_MASK); - if ((datatype & 0x4) == 0x4) { - prog->ARRAY[index].DIM0CFG |= (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT); - } - - // Program array base address - prog->ARRAY[index].ADDRCFG = (sli_mvp_addr_reg_t)addr; -} - -void sli_mvp_prog_set_array(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols) -{ - int colstride = 1; - int rowstride = cols; - int vecstride = rows * cols; - sli_mvp_prog_set_array_full(prog, index, addr, type, vecs, rows, cols, vecstride, rowstride, colstride); -} - -void sli_mvp_prog_set_vector(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short len) -{ - int colstride = 1; - sli_mvp_prog_set_array_full(prog, index, addr, type, 1, 1, len, 0, 0, colstride); -} - -void sli_mvp_prog_set_matrix(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short rows, - unsigned short cols) -{ - int colstride = 1; - int rowstride = cols; - sli_mvp_prog_set_array_full(prog, index, addr, type, 1, rows, cols, 0, rowstride, colstride); -} - -void sli_mvp_prog_set_instr(sli_mvp_program_t *prog, - uint8_t index, - uint32_t opcode, - uint32_t alu_cfg, - uint32_t load_cfg, - uint32_t store_cfg, - bool end) -{ - EFM_ASSERT(index < MAX_NUM_INSTRUCTIONS); - - prog->INSTR[index].CFG0 = alu_cfg; - prog->INSTR[index].CFG1 = load_cfg | store_cfg; - // This implicitly clears any loop controls - prog->INSTR[index].CFG2 = opcode << _MVP_INSTRCFG2_ALUOP_SHIFT; - if (end) { - prog->INSTR[index].CFG2 |= MVP_INSTRCFG2_ENDPROG; - } -} - -void sli_mvp_prog_set_loop(sli_mvp_program_t *prog, - uint8_t index, - unsigned short count, - uint8_t istart, - uint8_t iend, - uint32_t incrarray, - uint32_t rstarray) -{ - EFM_ASSERT(index < MAX_NUM_LOOPS); - EFM_ASSERT(count > 0 && count <= MAX_LOOP_COUNT); - EFM_ASSERT(istart < MAX_NUM_INSTRUCTIONS); - EFM_ASSERT(iend < MAX_NUM_INSTRUCTIONS); - - // Program loop iterations, increment and reset bit masks - prog->LOOP[index].CFG = ((count - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | (incrarray << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - prog->LOOP[index].RST = rstarray << _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT; - - // Update instruction field with loop information - // This is done with a read-modify-write since it overlays fields set by the instruction call - if (istart == iend) { - prog->INSTR[istart].CFG2 |= (3 << (2 * index)); - } else { - prog->INSTR[istart].CFG2 |= (1 << (2 * index)); - prog->INSTR[iend].CFG2 |= (2 << (2 * index)); - } -} - -void sli_mvp_perfcnt_conf(unsigned id, sli_mvp_perfcnt_t type) -{ - if (id >= NUM_PERF_CNT) { - return; - } - - if (mvp_is_enabled) { - if (id == 0) { - MVP->CFG = (MVP->CFG & ~(_MVP_CFG_PERF0CNTSEL_MASK)) - | ((uint32_t) type << _MVP_CFG_PERF0CNTSEL_SHIFT); - } else if (id == 1) { - MVP->CFG = (MVP->CFG & ~(_MVP_CFG_PERF1CNTSEL_MASK)) - | ((uint32_t) type << _MVP_CFG_PERF1CNTSEL_SHIFT); - } - } else { - if (id == 0) { - mvp_reg_cfg = (mvp_reg_cfg & ~(_MVP_CFG_PERF0CNTSEL_MASK)) - | ((uint32_t)type << _MVP_CFG_PERF0CNTSEL_SHIFT); - } else if (id == 1) { - mvp_reg_cfg = (mvp_reg_cfg & ~(_MVP_CFG_PERF1CNTSEL_MASK)) - | ((uint32_t)type << _MVP_CFG_PERF1CNTSEL_SHIFT); - } - } - perfcnt[id] = 0; -} - -void sli_mvp_perfcnt_reset_all(void) -{ - for (size_t i = 0; i < NUM_PERF_CNT; i++) { - perfcnt[i] = 0; - } -} - -uint32_t sli_mvp_perfcnt_get(unsigned id) -{ - if (id >= NUM_PERF_CNT) { - return 0; - } - return perfcnt[id]; -} - -void sli_mvp_progcnt_reset(void) -{ - mvp_program_count = 0; -} - -uint32_t sli_mvp_progcnt_get(void) -{ - return mvp_program_count; -} - -void sli_mvp_pb_begin_loop(sli_mvp_program_context_t *p, - int iterations, - sl_status_t *status) -{ - if (p->last_loop >= 7) { - if (status != NULL) { - *status = SL_STATUS_INVALID_PARAMETER; - } - return; - } - - if ((iterations <= 0) || (iterations > MAX_LOOP_COUNT)) { - if (status != NULL) { - *status = SL_STATUS_INVALID_PARAMETER; - } - return; - } - - p->last_loop++; - sli_mvp_prog_set_loop(p->p, - SLI_MVP_LOOP(p->last_loop), - iterations, - 0, 0, 0, 0); - p->loop_level++; - // Update loop stack with loop number of current loop level. - p->loop_stack[p->loop_level] = p->last_loop; - // Record loop begin bit for instruction. - p->loop_begin_end[p->last_instr + 1] |= 1 << (p->last_loop << 1); -} - -void sli_mvp_pb_begin_program(sli_mvp_program_context_t *p) -{ - p->last_loop = -1; - p->last_instr = -1; - p->loop_level = -1; - memset(p->loop_begin_end, 0, sizeof(p->loop_begin_end)); -} - -void sli_mvp_pb_compute(sli_mvp_program_context_t *p, - uint32_t opcode, - uint32_t alu_cfg, - uint32_t load_cfg, - uint32_t store_cfg, - sl_status_t *status) -{ - if (p->last_instr >= 7) { - if (status != NULL) { - *status = SL_STATUS_INVALID_PARAMETER; - } - return; - } - - p->last_instr++; - sli_mvp_prog_set_instr(p->p, p->last_instr, opcode, alu_cfg, load_cfg, store_cfg, false); -} - -void sli_mvp_pb_config_array_full(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short vecs, - unsigned short rows, - unsigned short cols, - int vecstride, - int rowstride, - int colstride, - sl_status_t *status) -{ - if (index >= MAX_NUM_ARRAYS) { - if (status != NULL) { - *status = SL_STATUS_INVALID_PARAMETER; - } - return; - } - - if ((vecs > MAX_ARRAY_DIM_SIZE) - || (rows > MAX_ARRAY_DIM_SIZE) - || (cols > MAX_ARRAY_DIM_SIZE) - || (vecstride < MIN_ARRAY_STRIDE_SIZE || vecstride > MAX_ARRAY_STRIDE_SIZE) - || (rowstride < MIN_ARRAY_STRIDE_SIZE || rowstride > MAX_ARRAY_STRIDE_SIZE) - || (colstride < MIN_ARRAY_STRIDE_SIZE || colstride > MAX_ARRAY_STRIDE_SIZE)) { - if (status != NULL) { - *status = SL_STATUS_INVALID_RANGE; - } - return; - } - - sli_mvp_prog_set_array_full(prog, index, addr, type, - vecs, rows, cols, - vecstride, rowstride, colstride); -} - -void sli_mvp_pb_config_array_nhwc(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short h, - unsigned short w, - unsigned short c, - sl_status_t *status) -{ - sli_mvp_pb_config_array_full(prog, index, addr, type, - c, // vecs (DIM0) - h, // rows (DIM1) - w, // cols (DIM2) - 1, // vecstride - w * c, // rowstride - c, // colstride - status); -} - -void sli_mvp_pb_config_matrix(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short rows, - unsigned short cols, - sl_status_t *status) -{ - int colstride = 1; - int rowstride = cols; - sli_mvp_pb_config_array_full(prog, index, addr, type, - 1, rows, cols, - 0, rowstride, colstride, - status); -} - -void sli_mvp_pb_config_vector(sli_mvp_program_t *prog, - uint8_t index, - void *addr, - sli_mvp_datatype_t type, - unsigned short len, - sl_status_t *status) -{ - int colstride = 1; - sli_mvp_pb_config_array_full(prog, index, addr, type, - 1, 1, len, - 0, 0, colstride, - status); -} - -void sli_mvp_pb_end_loop(sli_mvp_program_context_t *p) -{ - // Record loop end bit for instruction. - p->loop_begin_end[p->last_instr] |= 2 << (p->loop_stack[p->loop_level] << 1); - p->loop_level--; -} - -sl_status_t sli_mvp_pb_execute_program(sli_mvp_program_context_t *p) -{ - sl_status_t status; - - // Patch instruction loop begin & end bits. - for (int i = 0; i <= p->last_instr; i++) { - p->p->INSTR[i].CFG2 = (p->p->INSTR[i].CFG2 & 0xFFFF0000U) | p->loop_begin_end[i]; - } - // Mark end of program. - p->p->INSTR[p->last_instr].cfg2.endprog = 1; - - status = sli_mvp_prog_execute(p->p, false); - p->prog_index ^= 1; - p->p = &p->program[p->prog_index]; - return status; -} - -void sli_mvp_pb_init_program(sli_mvp_program_context_t *p) -{ - p->prog_index = 0; - p->p = &p->program[p->prog_index]; -} - -void sli_mvp_pb_postloop_incr_dim(sli_mvp_program_context_t *p, - uint8_t array_index, - uint8_t dimension) -{ - p->p->LOOP[p->loop_stack[p->loop_level + 1]].CFG - |= dimension << ((array_index * 4) + _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); -} - -void sli_mvp_pb_postloop_reset_dim(sli_mvp_program_context_t *p, - uint8_t array_index, - uint8_t dimension) -{ - p->p->LOOP[p->loop_stack[p->loop_level + 1]].RST - |= dimension << ((array_index * 4) + _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT); -} +/***************************************************************************//** + * @file + * @brief MVP Core driver. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "em_device.h" +#include "sl_assert.h" +#include "sl_mvp_hal.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_STATUS_STRING_PRESENT) +#include "sl_status_string_config.h" +#endif + +#include +#include + +#define NUM_PERF_CNT 2 +#define MAX_NUM_ARRAYS 5 +#define MAX_NUM_LOOPS 8 +#define MAX_NUM_INSTRUCTIONS 8 +#define MAX_NUM_REGS 8 +#define MAX_ARRAY_DIM_SIZE 1024 +#define MAX_ARRAY_STRIDE_SIZE 2047 +#define MIN_ARRAY_STRIDE_SIZE -2048 +#define MAX_LOOP_COUNT 1024 + +#define SLI_MVP_FAULT_MASK (MVP_IF_LOOPFAULT | MVP_IF_BUSERRFAULT \ + | MVP_IF_BUSALIGNFAULT | MVP_IF_ALUFAULT \ + | MVP_IF_ARRAYFAULT) + +static uint32_t mvp_numerical_exception_flags; +static volatile bool mvp_fault_flag; +static uint32_t mvp_program_count = 0; +static volatile uint32_t perfcnt[NUM_PERF_CNT] = { 0 }; +// Software retained MVP registers. +static volatile uint32_t mvp_reg_cfg = MVP_CFG_PERF0CNTSEL_RUN | MVP_CFG_PERF1CNTSEL_STALL | MVP_CFG_PERFCNTEN; +static volatile bool mvp_is_enabled = false; + +static void enable_callback(void) +{ + MVP->EN_SET = MVP_EN_EN; + MVP->IEN_SET = MVP_IEN_PERFCNT0 | MVP_IEN_PERFCNT1 | MVP_IEN_PROGDONE + | SLI_MVP_FAULT_MASK; + MVP->CFG = mvp_reg_cfg; + mvp_is_enabled = true; +} + +static void disable_callback(void) +{ + mvp_reg_cfg = MVP->CFG; + MVP->EN_CLR = MVP_EN_EN; + while (MVP->EN & MVP_EN_DISABLING) + ; + MVP->IEN_CLR = 0xffffffff; + mvp_is_enabled = false; +} + +static bool isr_callback(void) +{ + uint32_t pending, tmp; + bool done = false; + + pending = MVP->IF; + pending &= MVP->IEN; + + if (pending & SLI_MVP_FAULT_MASK) { + mvp_fault_flag = true; + done = true; + } + if (pending & MVP_IF_PROGDONE) { + while (!(MVP->STATUS & MVP_STATUS_IDLE)) { + } + tmp = MVP->PERF[0].CNT; + perfcnt[0] += tmp; + tmp = MVP->PERF[1].CNT; + perfcnt[1] += tmp; + done = true; + } + if (pending & MVP_IF_PERFCNT0) { + perfcnt[0] += (_MVP_PERFCNT_COUNT_MASK + 1); + } + if (pending & MVP_IF_PERFCNT1) { + perfcnt[1] += (_MVP_PERFCNT_COUNT_MASK + 1); + } + + MVP->IF_CLR = pending; + + return done; +} + +void sli_mvp_clear_error_flags(uint32_t flags) +{ + mvp_numerical_exception_flags &= ~(flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK); +} + +sl_status_t sli_mvp_get_error(sl_status_t *error_code, + char *error_message, + uint32_t buffer_length) +{ + if (!error_code) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t flag = 0; + uint32_t flags = mvp_numerical_exception_flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; + + if (flags & MVP_IF_ALUNAN) { + *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_NAN; + flag = MVP_IF_ALUNAN; + } else if (flags & MVP_IF_ALUOF) { + *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW; + flag = MVP_IF_ALUOF; + } else if (flags & MVP_IF_ALUUF) { + *error_code = SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW; + flag = MVP_IF_ALUUF; + + } else if (flags & MVP_IF_STORECONVERTOF) { + *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW; + flag = MVP_IF_STORECONVERTOF; + } else if (flags & MVP_IF_STORECONVERTUF) { + *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW; + flag = MVP_IF_STORECONVERTUF; + } else if (flags & MVP_IF_STORECONVERTINF) { + *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY; + flag = MVP_IF_STORECONVERTINF; + } else if (flags & MVP_IF_STORECONVERTNAN) { + *error_code = SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN; + flag = MVP_IF_STORECONVERTNAN; + + } else { + return SL_STATUS_NOT_FOUND; + } + + mvp_numerical_exception_flags &= ~flag; + +#if defined(SL_CATALOG_STATUS_STRING_PRESENT) && (SL_STATUS_STRING_ENABLE_COMPUTE == 1) + if (error_message != NULL) { + sl_status_get_string_n(*error_code, error_message, buffer_length); + } +#else + if ((error_message != NULL) && (buffer_length > 0)) { + error_message[0] = '\0'; + } +#endif + + return SL_STATUS_OK; +} + +uint32_t sli_mvp_get_error_flags(void) +{ + return mvp_numerical_exception_flags & SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; +} + +sl_status_t sli_mvp_init(void) +{ + mvp_fault_flag = false; + mvp_numerical_exception_flags = 0U; + return sli_mvp_hal_init(enable_callback, disable_callback, isr_callback); +} + +sl_status_t sli_mvp_deinit(void) +{ + return sli_mvp_hal_deinit(); +} + +void sli_mvp_cmd_enable(void) +{ + sli_mvp_hal_cmd_wait_for_completion(); + sli_mvp_hal_cmd_enable(); +} + +sl_status_t sli_mvp_cmd_wait_for_completion(void) +{ + sli_mvp_hal_cmd_wait_for_completion(); + mvp_numerical_exception_flags |= MVP->IF; + MVP->IF_CLR = SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK; + sl_status_t status = mvp_fault_flag ? SL_STATUS_COMPUTE_DRIVER_FAULT : SL_STATUS_OK; + mvp_fault_flag = false; + return status; +} + +sl_status_t sli_mvp_prog_execute(sli_mvp_program_t *program, bool wait) +{ + sl_status_t status; + + program->CMD = MVP_CMD_INIT | MVP_CMD_START; + mvp_program_count++; + if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { + return status; + } + sli_mvp_hal_cmd_enable(); + sli_mvp_hal_load_program(program, &MVP->ALU[0], sizeof(sli_mvp_program_t)); + if (wait) { + status = sli_mvp_cmd_wait_for_completion(); + } + return status; +} + +void sli_mvp_prog_set_reg_s8(sli_mvp_program_t *prog, uint8_t reg, int8_t value) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); +} + +void sli_mvp_prog_set_reg_s8c(sli_mvp_program_t *prog, uint8_t reg, int8_t real, int8_t imag) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); +} + +void sli_mvp_prog_set_reg_s16(sli_mvp_program_t *prog, uint8_t reg, int16_t value) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); +} + +void sli_mvp_prog_set_reg_s16c(sli_mvp_program_t *prog, uint8_t reg, int16_t real, int16_t imag) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); +} + +void sli_mvp_prog_set_reg_s32(sli_mvp_program_t *prog, uint8_t reg, int32_t value) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, (float16_t)value, 0); +} + +void sli_mvp_prog_set_reg_s32c(sli_mvp_program_t *prog, uint8_t reg, int32_t real, int32_t imag) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, (float16_t)real, (float16_t)imag); +} + +void sli_mvp_prog_set_reg_f16(sli_mvp_program_t *prog, uint8_t reg, float16_t value) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); +} + +void sli_mvp_prog_set_reg_f16c(sli_mvp_program_t *prog, uint8_t reg, float16_t real, float16_t imag) +{ + EFM_ASSERT(reg < MAX_NUM_REGS); + + prog->ALU[reg].reg.value.real = real; + prog->ALU[reg].reg.value.imag = imag; +} + +void sli_mvp_prog_set_reg_f32(sli_mvp_program_t *prog, uint8_t reg, float value) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, value, 0); +} + +void sli_mvp_prog_set_reg_f32c(sli_mvp_program_t *prog, uint8_t reg, float real, float imag) +{ + sli_mvp_prog_set_reg_f16c(prog, reg, real, imag); +} + +void sli_mvp_prog_set_array_full(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols, + int vecstride, + int rowstride, + int colstride) +{ + EFM_ASSERT(index < MAX_NUM_ARRAYS); + EFM_ASSERT(vecs <= MAX_ARRAY_DIM_SIZE); + EFM_ASSERT(rows <= MAX_ARRAY_DIM_SIZE); + EFM_ASSERT(cols <= MAX_ARRAY_DIM_SIZE); + EFM_ASSERT(vecstride >= MIN_ARRAY_STRIDE_SIZE && vecstride <= MAX_ARRAY_STRIDE_SIZE); + EFM_ASSERT(rowstride >= MIN_ARRAY_STRIDE_SIZE && rowstride <= MAX_ARRAY_STRIDE_SIZE); + EFM_ASSERT(colstride >= MIN_ARRAY_STRIDE_SIZE && colstride <= MAX_ARRAY_STRIDE_SIZE); + + uint32_t datatype = (uint32_t)type; + prog->ARRAY[index].DIM0CFG = (((vecs - 1) << _MVP_ARRAYDIM0CFG_SIZE_SHIFT) & _MVP_ARRAYDIM0CFG_SIZE_MASK); + prog->ARRAY[index].DIM1CFG = (((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) & _MVP_ARRAYDIM1CFG_SIZE_MASK); + prog->ARRAY[index].DIM2CFG = (((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) & _MVP_ARRAYDIM2CFG_SIZE_MASK); + + // Set up Array Strides This is a 10-bit signed integer between -512 and +511 + prog->ARRAY[index].DIM0CFG |= ((vecstride << _MVP_ARRAYDIM0CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM0CFG_STRIDE_MASK); + prog->ARRAY[index].DIM1CFG |= ((rowstride << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM1CFG_STRIDE_MASK); + prog->ARRAY[index].DIM2CFG |= ((colstride << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT) & _MVP_ARRAYDIM2CFG_STRIDE_MASK); + + // Set up datatype + prog->ARRAY[index].DIM0CFG |= ((datatype << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT) & _MVP_ARRAYDIM0CFG_BASETYPE_MASK); + if ((datatype & 0x4) == 0x4) { + prog->ARRAY[index].DIM0CFG |= (_MVP_ARRAYDIM0CFG_COMPLEX_COMPLEX << _MVP_ARRAYDIM0CFG_COMPLEX_SHIFT); + } + + // Program array base address + prog->ARRAY[index].ADDRCFG = (sli_mvp_addr_reg_t)addr; +} + +void sli_mvp_prog_set_array(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols) +{ + int colstride = 1; + int rowstride = cols; + int vecstride = rows * cols; + sli_mvp_prog_set_array_full(prog, index, addr, type, vecs, rows, cols, vecstride, rowstride, colstride); +} + +void sli_mvp_prog_set_vector(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short len) +{ + int colstride = 1; + sli_mvp_prog_set_array_full(prog, index, addr, type, 1, 1, len, 0, 0, colstride); +} + +void sli_mvp_prog_set_matrix(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short rows, + unsigned short cols) +{ + int colstride = 1; + int rowstride = cols; + sli_mvp_prog_set_array_full(prog, index, addr, type, 1, rows, cols, 0, rowstride, colstride); +} + +void sli_mvp_prog_set_instr(sli_mvp_program_t *prog, + uint8_t index, + uint32_t opcode, + uint32_t alu_cfg, + uint32_t load_cfg, + uint32_t store_cfg, + bool end) +{ + EFM_ASSERT(index < MAX_NUM_INSTRUCTIONS); + + prog->INSTR[index].CFG0 = alu_cfg; + prog->INSTR[index].CFG1 = load_cfg | store_cfg; + // This implicitly clears any loop controls + prog->INSTR[index].CFG2 = opcode << _MVP_INSTRCFG2_ALUOP_SHIFT; + if (end) { + prog->INSTR[index].CFG2 |= MVP_INSTRCFG2_ENDPROG; + } +} + +void sli_mvp_prog_set_loop(sli_mvp_program_t *prog, + uint8_t index, + unsigned short count, + uint8_t istart, + uint8_t iend, + uint32_t incrarray, + uint32_t rstarray) +{ + EFM_ASSERT(index < MAX_NUM_LOOPS); + EFM_ASSERT(count > 0 && count <= MAX_LOOP_COUNT); + EFM_ASSERT(istart < MAX_NUM_INSTRUCTIONS); + EFM_ASSERT(iend < MAX_NUM_INSTRUCTIONS); + + // Program loop iterations, increment and reset bit masks + prog->LOOP[index].CFG = ((count - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | (incrarray << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + prog->LOOP[index].RST = rstarray << _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT; + + // Update instruction field with loop information + // This is done with a read-modify-write since it overlays fields set by the instruction call + if (istart == iend) { + prog->INSTR[istart].CFG2 |= (3 << (2 * index)); + } else { + prog->INSTR[istart].CFG2 |= (1 << (2 * index)); + prog->INSTR[iend].CFG2 |= (2 << (2 * index)); + } +} + +void sli_mvp_perfcnt_conf(unsigned id, sli_mvp_perfcnt_t type) +{ + if (id >= NUM_PERF_CNT) { + return; + } + + if (mvp_is_enabled) { + if (id == 0) { + MVP->CFG = (MVP->CFG & ~(_MVP_CFG_PERF0CNTSEL_MASK)) + | ((uint32_t) type << _MVP_CFG_PERF0CNTSEL_SHIFT); + } else if (id == 1) { + MVP->CFG = (MVP->CFG & ~(_MVP_CFG_PERF1CNTSEL_MASK)) + | ((uint32_t) type << _MVP_CFG_PERF1CNTSEL_SHIFT); + } + } else { + if (id == 0) { + mvp_reg_cfg = (mvp_reg_cfg & ~(_MVP_CFG_PERF0CNTSEL_MASK)) + | ((uint32_t)type << _MVP_CFG_PERF0CNTSEL_SHIFT); + } else if (id == 1) { + mvp_reg_cfg = (mvp_reg_cfg & ~(_MVP_CFG_PERF1CNTSEL_MASK)) + | ((uint32_t)type << _MVP_CFG_PERF1CNTSEL_SHIFT); + } + } + perfcnt[id] = 0; +} + +void sli_mvp_perfcnt_reset_all(void) +{ + for (size_t i = 0; i < NUM_PERF_CNT; i++) { + perfcnt[i] = 0; + } +} + +uint32_t sli_mvp_perfcnt_get(unsigned id) +{ + if (id >= NUM_PERF_CNT) { + return 0; + } + return perfcnt[id]; +} + +void sli_mvp_progcnt_reset(void) +{ + mvp_program_count = 0; +} + +uint32_t sli_mvp_progcnt_get(void) +{ + return mvp_program_count; +} + +void sli_mvp_pb_begin_loop(sli_mvp_program_context_t *p, + int iterations, + sl_status_t *status) +{ + if (p->last_loop >= 7) { + if (status != NULL) { + *status = SL_STATUS_INVALID_PARAMETER; + } + return; + } + + if ((iterations <= 0) || (iterations > MAX_LOOP_COUNT)) { + if (status != NULL) { + *status = SL_STATUS_INVALID_PARAMETER; + } + return; + } + + p->last_loop++; + sli_mvp_prog_set_loop(p->p, + SLI_MVP_LOOP(p->last_loop), + iterations, + 0, 0, 0, 0); + p->loop_level++; + // Update loop stack with loop number of current loop level. + p->loop_stack[p->loop_level] = p->last_loop; + // Record loop begin bit for instruction. + p->loop_begin_end[p->last_instr + 1] |= 1 << (p->last_loop << 1); +} + +void sli_mvp_pb_begin_program(sli_mvp_program_context_t *p) +{ + p->last_loop = -1; + p->last_instr = -1; + p->loop_level = -1; + memset(p->loop_begin_end, 0, sizeof(p->loop_begin_end)); +} + +void sli_mvp_pb_compute(sli_mvp_program_context_t *p, + uint32_t opcode, + uint32_t alu_cfg, + uint32_t load_cfg, + uint32_t store_cfg, + sl_status_t *status) +{ + if (p->last_instr >= 7) { + if (status != NULL) { + *status = SL_STATUS_INVALID_PARAMETER; + } + return; + } + + p->last_instr++; + sli_mvp_prog_set_instr(p->p, p->last_instr, opcode, alu_cfg, load_cfg, store_cfg, false); +} + +void sli_mvp_pb_config_array_full(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short vecs, + unsigned short rows, + unsigned short cols, + int vecstride, + int rowstride, + int colstride, + sl_status_t *status) +{ + if (index >= MAX_NUM_ARRAYS) { + if (status != NULL) { + *status = SL_STATUS_INVALID_PARAMETER; + } + return; + } + + if ((vecs > MAX_ARRAY_DIM_SIZE) + || (rows > MAX_ARRAY_DIM_SIZE) + || (cols > MAX_ARRAY_DIM_SIZE) + || (vecstride < MIN_ARRAY_STRIDE_SIZE || vecstride > MAX_ARRAY_STRIDE_SIZE) + || (rowstride < MIN_ARRAY_STRIDE_SIZE || rowstride > MAX_ARRAY_STRIDE_SIZE) + || (colstride < MIN_ARRAY_STRIDE_SIZE || colstride > MAX_ARRAY_STRIDE_SIZE)) { + if (status != NULL) { + *status = SL_STATUS_INVALID_RANGE; + } + return; + } + + sli_mvp_prog_set_array_full(prog, index, addr, type, + vecs, rows, cols, + vecstride, rowstride, colstride); +} + +void sli_mvp_pb_config_array_nhwc(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short h, + unsigned short w, + unsigned short c, + sl_status_t *status) +{ + sli_mvp_pb_config_array_full(prog, index, addr, type, + c, // vecs (DIM0) + h, // rows (DIM1) + w, // cols (DIM2) + 1, // vecstride + w * c, // rowstride + c, // colstride + status); +} + +void sli_mvp_pb_config_matrix(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short rows, + unsigned short cols, + sl_status_t *status) +{ + int colstride = 1; + int rowstride = cols; + sli_mvp_pb_config_array_full(prog, index, addr, type, + 1, rows, cols, + 0, rowstride, colstride, + status); +} + +void sli_mvp_pb_config_vector(sli_mvp_program_t *prog, + uint8_t index, + void *addr, + sli_mvp_datatype_t type, + unsigned short len, + sl_status_t *status) +{ + int colstride = 1; + sli_mvp_pb_config_array_full(prog, index, addr, type, + 1, 1, len, + 0, 0, colstride, + status); +} + +void sli_mvp_pb_end_loop(sli_mvp_program_context_t *p) +{ + // Record loop end bit for instruction. + p->loop_begin_end[p->last_instr] |= 2 << (p->loop_stack[p->loop_level] << 1); + p->loop_level--; +} + +sl_status_t sli_mvp_pb_execute_program(sli_mvp_program_context_t *p) +{ + sl_status_t status; + + // Patch instruction loop begin & end bits. + for (int i = 0; i <= p->last_instr; i++) { + p->p->INSTR[i].CFG2 = (p->p->INSTR[i].CFG2 & 0xFFFF0000U) | p->loop_begin_end[i]; + } + // Mark end of program. + p->p->INSTR[p->last_instr].cfg2.endprog = 1; + + status = sli_mvp_prog_execute(p->p, false); + p->prog_index ^= 1; + p->p = &p->program[p->prog_index]; + return status; +} + +void sli_mvp_pb_init_program(sli_mvp_program_context_t *p) +{ + p->prog_index = 0; + p->p = &p->program[p->prog_index]; +} + +void sli_mvp_pb_postloop_incr_dim(sli_mvp_program_context_t *p, + uint8_t array_index, + uint8_t dimension) +{ + p->p->LOOP[p->loop_stack[p->loop_level + 1]].CFG + |= dimension << ((array_index * 4) + _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); +} + +void sli_mvp_pb_postloop_reset_dim(sli_mvp_program_context_t *p, + uint8_t array_index, + uint8_t dimension) +{ + p->p->LOOP[p->loop_stack[p->loop_level + 1]].RST + |= dimension << ((array_index * 4) + _MVP_LOOPRST_ARRAY0RESETDIM0_SHIFT); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c index 6a2a0d4..ad3534f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c @@ -1,382 +1,382 @@ -/***************************************************************************//** - * @file - * @brief MVP HAL driver. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp_hal.h" -#include "sl_driver_mvp_config.h" -#include "em_device.h" -#if SL_MVP_ENABLE_DMA -#include "em_ldma.h" -#endif -#include "em_cmu.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_KERNEL_PRESENT) -#include "cmsis_os2.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif -#if SL_MVP_POWER_MODE == 1 -#include "em_emu.h" -#endif - -//************************************ -// Validate configuration - -#if SL_MVP_POWER_MODE == 1 && defined(SL_CATALOG_KERNEL_PRESENT) - #error "SL_MVP_POWER_MODE=1 cannot be used together with an RTOS" -#endif - -#if SL_MVP_POWER_MODE > 2 - #error "Unknown SL_MVP_POWER_MODE value" -#endif - -//************************************ -// Macro definitions - -// This macro is used to configure if the MVP is enabled at all times between -// init and deinit by setting it to 1, or just enabled during command execution -// by setting it to 0. -#define SPEED_OVER_POWER 1 - -#if SL_MVP_POWER_MODE == 2 -#define SL_MVP_EVENT_FLAG_IDLE 0x1 -#endif - -//************************************ -// Static variables - -static sli_mvp_enable_callback callback_enable = NULL; -static sli_mvp_disable_callback callback_disable = NULL; -static sli_mvp_isr_callback callback_isr = NULL; -static volatile bool mvp_is_initialized = false; -static volatile bool mvp_is_busy = false; -static sli_mvp_hal_config_t hal_config = { .use_dma = SL_MVP_ENABLE_DMA, - .dma_ch = SL_MVP_DMA_CHANNEL }; -#if SL_MVP_ENABLE_DMA -static LDMA_Descriptor_t ldma_descriptor = LDMA_DESCRIPTOR_SINGLE_M2M_WORD(0, 0, 0); -static LDMA_TransferCfg_t ldma_config = LDMA_TRANSFER_CFG_MEMORY(); -#endif - -#if SL_MVP_POWER_MODE == 2 -static bool mvp_event_is_initialized = false; -static osEventFlagsId_t mvp_event_id; -#endif - -//************************************ -// Static functions - -/** - * @brief - * Load a program using the CPU. - */ -static void cpu_load(uint32_t *src, uint32_t *dst, size_t length) -{ - length /= sizeof(uint32_t); - for (size_t i = 0; i < length; i++) { - dst[i] = src[i]; - } -} - -#if SL_MVP_ENABLE_DMA -/** - * @brief - * Load a program using the LDMA. - */ -static void dma_load(void *src, void *dst, size_t length) -{ - length /= sizeof(uint32_t); - ldma_descriptor.xfer.srcAddr = (uint32_t)src; - ldma_descriptor.xfer.dstAddr = (uint32_t)dst; - ldma_descriptor.xfer.xferCnt = length - 1; - LDMA_StartTransfer(hal_config.dma_ch, &ldma_config, &ldma_descriptor); -} -#endif - -/** - * @brief - * Disable the MVP program execution. - */ -static void cmd_disable(void) -{ -#if !SPEED_OVER_POWER - if (callback_disable != NULL) { - callback_disable(); - } -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); -#endif - mvp_is_busy = false; -#if SL_MVP_POWER_MODE == 2 - uint32_t ret = osEventFlagsSet(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE); - EFM_ASSERT((int)ret >= 0); -#endif -} - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER -/** - * @brief - * Power manager callback when entering EM2/EM3 or waking up from EM2/EM3. - */ -static void em_transition(sl_power_manager_em_t from, sl_power_manager_em_t to) -{ - (void)from; - - if ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) { - if (callback_disable != NULL) { - callback_disable(); - } - } else if ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0)) { - if (callback_enable != NULL) { - callback_enable(); - } - } -} - -static sl_power_manager_em_transition_event_handle_t em_event_handle; -static const sl_power_manager_em_transition_event_info_t em_event_info = { - .event_mask = (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 - | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 - | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3), - .on_event = em_transition, -}; - -/** - * @brief - * Add power manager transition event handling. - */ -static void em_add_transition_callback(void) -{ - sl_power_manager_subscribe_em_transition_event(&em_event_handle, &em_event_info); -} - -/** - * @brief - * Remove power manager transition event handling. - */ -static void em_remove_transition_callback(void) -{ - sl_power_manager_unsubscribe_em_transition_event(&em_event_handle); -} -#endif - -#if SL_MVP_POWER_MODE == 2 -/** - * @brief - * Set the initial value of the idle flag. - * - * @note - * The os must be running before setting initial flag state. - * When the program is running it is ok to set the flag. - */ -static void set_idle_flag_initially(void) -{ - if (!mvp_event_is_initialized) { - mvp_event_is_initialized = true; - uint32_t ret = osEventFlagsSet(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE); - EFM_ASSERT((int)ret >= 0); - } -} -#endif - -//************************************ -// Exported functions - -sl_status_t sli_mvp_hal_config(sli_mvp_hal_config_t *config) -{ - hal_config = *config; -#if SL_MVP_ENABLE_DMA - if (hal_config.use_dma) { - CMU_ClockEnable(cmuClock_LDMA, true); - LDMA_Init_t ldma_init = LDMA_INIT_DEFAULT; - LDMA_Init(&ldma_init); - } -#endif - return SL_STATUS_OK; -} - -sl_status_t sli_mvp_hal_init(sli_mvp_enable_callback enable, sli_mvp_disable_callback disable, sli_mvp_isr_callback isr) -{ - if (mvp_is_initialized) { - return SL_STATUS_ALREADY_INITIALIZED; - } - callback_enable = enable; - callback_disable = disable; - callback_isr = isr; - CMU->CLKEN1_SET = CMU_CLKEN1_MVP; - sli_mvp_hal_config(&hal_config); - NVIC_EnableIRQ(MVP_IRQn); -#if SPEED_OVER_POWER - if (callback_enable != NULL) { - callback_enable(); - } -#endif -#if SL_MVP_POWER_MODE == 2 - mvp_event_id = osEventFlagsNew(NULL); - EFM_ASSERT(mvp_event_id != NULL); -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER - em_add_transition_callback(); -#endif - mvp_is_initialized = true; - mvp_is_busy = false; - return SL_STATUS_OK; -} - -sl_status_t sli_mvp_hal_deinit(void) -{ - if (!mvp_is_initialized) { - return SL_STATUS_NOT_INITIALIZED; - } - if (mvp_is_busy) { - cmd_disable(); - } -#if SL_MVP_POWER_MODE == 2 - osStatus_t status = osEventFlagsDelete(mvp_event_id); - EFM_ASSERT(status == osOK); -#endif -#if SPEED_OVER_POWER - if (callback_disable != NULL) { - callback_disable(); - } -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER - em_remove_transition_callback(); -#endif - mvp_is_initialized = false; - NVIC_DisableIRQ(MVP_IRQn); - CMU->CLKEN1_CLR = CMU_CLKEN1_MVP; - return SL_STATUS_OK; -} - -sl_status_t sli_mvp_hal_load_program(void *src, void *dst, size_t length) -{ - if (!mvp_is_initialized) { - return SL_STATUS_NOT_INITIALIZED; - } - if (!mvp_is_busy) { - return SL_STATUS_NOT_AVAILABLE; - } -#if SL_MVP_ENABLE_DMA - if (hal_config.use_dma) { - dma_load(src, dst, length); - } else { - cpu_load(src, dst, length); - } -#else - cpu_load(src, dst, length); -#endif - return SL_STATUS_OK; -} - -void sli_mvp_hal_cmd_enable(void) -{ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); -#endif -#if !SPEED_OVER_POWER - if (callback_enable != NULL) { - callback_enable(); - } -#endif - mvp_is_busy = true; -#if SL_MVP_POWER_MODE == 2 - set_idle_flag_initially(); - // Consume the idle flag. - uint32_t ret = osEventFlagsWait(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE, osFlagsWaitAny, osWaitForever); - EFM_ASSERT((int)ret >= 0); -#endif -} - -bool sli_mvp_hal_cmd_is_busy(void) -{ - if (!mvp_is_initialized) { - return false; - } - return mvp_is_busy; -} - -void sli_mvp_hal_cmd_wait_for_completion() -{ -#if SL_MVP_POWER_MODE == 1 - CORE_DECLARE_IRQ_STATE; -#endif - - if (!mvp_is_initialized) { - return; - } -#if SL_MVP_POWER_MODE == 2 - set_idle_flag_initially(); - uint32_t ret = osEventFlagsWait(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE, osFlagsNoClear, osWaitForever); - EFM_ASSERT((int)ret >= 0); -#else - // Logically, just wait for the busy flag to go off. It's cleared in the ISR - // when the operation is complete. - // Because the busy flag is in memory, the MVP may add stalls if the flag is - // accessed during program execution. - // Mitigation: During most of the waiting, wait for the MVP to become idle. - // This is the only improvement that requires knowledge of MVP registers in HAL. - while(!(MVP->STATUS & MVP_STATUS_IDLE)) { - // Wait until the MVP is idle. -#if SL_MVP_POWER_MODE == 1 - CORE_ENTER_CRITICAL(); - if (!(MVP->STATUS & MVP_STATUS_IDLE)) { - EMU_EnterEM1(); - } - CORE_EXIT_CRITICAL(); -#endif - } - // Finally, wait for the interrupt handler to clear the flag. - // It may take a few more cycles after the MVP has become idle. - while (mvp_is_busy) { - } -#endif -} - -/** - * @brief - * MVP Interrupt handler - * - * @details - * This interrupt handler is triggered whenever a program is done or when one - * of the performance counters wraps. - */ -void MVP_IRQHandler(void) -{ - if (callback_isr != NULL) { - bool done; - done = callback_isr(); - if (done) { - cmd_disable(); - } - } -} +/***************************************************************************//** + * @file + * @brief MVP HAL driver. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp_hal.h" +#include "sl_driver_mvp_config.h" +#include "em_device.h" +#if SL_MVP_ENABLE_DMA +#include "em_ldma.h" +#endif +#include "em_cmu.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif +#if SL_MVP_POWER_MODE == 1 +#include "em_emu.h" +#endif + +//************************************ +// Validate configuration + +#if SL_MVP_POWER_MODE == 1 && defined(SL_CATALOG_KERNEL_PRESENT) + #error "SL_MVP_POWER_MODE=1 cannot be used together with an RTOS" +#endif + +#if SL_MVP_POWER_MODE > 2 + #error "Unknown SL_MVP_POWER_MODE value" +#endif + +//************************************ +// Macro definitions + +// This macro is used to configure if the MVP is enabled at all times between +// init and deinit by setting it to 1, or just enabled during command execution +// by setting it to 0. +#define SPEED_OVER_POWER 1 + +#if SL_MVP_POWER_MODE == 2 +#define SL_MVP_EVENT_FLAG_IDLE 0x1 +#endif + +//************************************ +// Static variables + +static sli_mvp_enable_callback callback_enable = NULL; +static sli_mvp_disable_callback callback_disable = NULL; +static sli_mvp_isr_callback callback_isr = NULL; +static volatile bool mvp_is_initialized = false; +static volatile bool mvp_is_busy = false; +static sli_mvp_hal_config_t hal_config = { .use_dma = SL_MVP_ENABLE_DMA, + .dma_ch = SL_MVP_DMA_CHANNEL }; +#if SL_MVP_ENABLE_DMA +static LDMA_Descriptor_t ldma_descriptor = LDMA_DESCRIPTOR_SINGLE_M2M_WORD(0, 0, 0); +static LDMA_TransferCfg_t ldma_config = LDMA_TRANSFER_CFG_MEMORY(); +#endif + +#if SL_MVP_POWER_MODE == 2 +static bool mvp_event_is_initialized = false; +static osEventFlagsId_t mvp_event_id; +#endif + +//************************************ +// Static functions + +/** + * @brief + * Load a program using the CPU. + */ +static void cpu_load(uint32_t *src, uint32_t *dst, size_t length) +{ + length /= sizeof(uint32_t); + for (size_t i = 0; i < length; i++) { + dst[i] = src[i]; + } +} + +#if SL_MVP_ENABLE_DMA +/** + * @brief + * Load a program using the LDMA. + */ +static void dma_load(void *src, void *dst, size_t length) +{ + length /= sizeof(uint32_t); + ldma_descriptor.xfer.srcAddr = (uint32_t)src; + ldma_descriptor.xfer.dstAddr = (uint32_t)dst; + ldma_descriptor.xfer.xferCnt = length - 1; + LDMA_StartTransfer(hal_config.dma_ch, &ldma_config, &ldma_descriptor); +} +#endif + +/** + * @brief + * Disable the MVP program execution. + */ +static void cmd_disable(void) +{ +#if !SPEED_OVER_POWER + if (callback_disable != NULL) { + callback_disable(); + } +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); +#endif + mvp_is_busy = false; +#if SL_MVP_POWER_MODE == 2 + uint32_t ret = osEventFlagsSet(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE); + EFM_ASSERT((int)ret >= 0); +#endif +} + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER +/** + * @brief + * Power manager callback when entering EM2/EM3 or waking up from EM2/EM3. + */ +static void em_transition(sl_power_manager_em_t from, sl_power_manager_em_t to) +{ + (void)from; + + if ((to == SL_POWER_MANAGER_EM2) || (to == SL_POWER_MANAGER_EM3)) { + if (callback_disable != NULL) { + callback_disable(); + } + } else if ((to == SL_POWER_MANAGER_EM1) || (to == SL_POWER_MANAGER_EM0)) { + if (callback_enable != NULL) { + callback_enable(); + } + } +} + +static sl_power_manager_em_transition_event_handle_t em_event_handle; +static const sl_power_manager_em_transition_event_info_t em_event_info = { + .event_mask = (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 + | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 + | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 + | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3), + .on_event = em_transition, +}; + +/** + * @brief + * Add power manager transition event handling. + */ +static void em_add_transition_callback(void) +{ + sl_power_manager_subscribe_em_transition_event(&em_event_handle, &em_event_info); +} + +/** + * @brief + * Remove power manager transition event handling. + */ +static void em_remove_transition_callback(void) +{ + sl_power_manager_unsubscribe_em_transition_event(&em_event_handle); +} +#endif + +#if SL_MVP_POWER_MODE == 2 +/** + * @brief + * Set the initial value of the idle flag. + * + * @note + * The os must be running before setting initial flag state. + * When the program is running it is ok to set the flag. + */ +static void set_idle_flag_initially(void) +{ + if (!mvp_event_is_initialized) { + mvp_event_is_initialized = true; + uint32_t ret = osEventFlagsSet(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE); + EFM_ASSERT((int)ret >= 0); + } +} +#endif + +//************************************ +// Exported functions + +sl_status_t sli_mvp_hal_config(sli_mvp_hal_config_t *config) +{ + hal_config = *config; +#if SL_MVP_ENABLE_DMA + if (hal_config.use_dma) { + CMU_ClockEnable(cmuClock_LDMA, true); + LDMA_Init_t ldma_init = LDMA_INIT_DEFAULT; + LDMA_Init(&ldma_init); + } +#endif + return SL_STATUS_OK; +} + +sl_status_t sli_mvp_hal_init(sli_mvp_enable_callback enable, sli_mvp_disable_callback disable, sli_mvp_isr_callback isr) +{ + if (mvp_is_initialized) { + return SL_STATUS_ALREADY_INITIALIZED; + } + callback_enable = enable; + callback_disable = disable; + callback_isr = isr; + CMU->CLKEN1_SET = CMU_CLKEN1_MVP; + sli_mvp_hal_config(&hal_config); + NVIC_EnableIRQ(MVP_IRQn); +#if SPEED_OVER_POWER + if (callback_enable != NULL) { + callback_enable(); + } +#endif +#if SL_MVP_POWER_MODE == 2 + mvp_event_id = osEventFlagsNew(NULL); + EFM_ASSERT(mvp_event_id != NULL); +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER + em_add_transition_callback(); +#endif + mvp_is_initialized = true; + mvp_is_busy = false; + return SL_STATUS_OK; +} + +sl_status_t sli_mvp_hal_deinit(void) +{ + if (!mvp_is_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + if (mvp_is_busy) { + cmd_disable(); + } +#if SL_MVP_POWER_MODE == 2 + osStatus_t status = osEventFlagsDelete(mvp_event_id); + EFM_ASSERT(status == osOK); +#endif +#if SPEED_OVER_POWER + if (callback_disable != NULL) { + callback_disable(); + } +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && SPEED_OVER_POWER + em_remove_transition_callback(); +#endif + mvp_is_initialized = false; + NVIC_DisableIRQ(MVP_IRQn); + CMU->CLKEN1_CLR = CMU_CLKEN1_MVP; + return SL_STATUS_OK; +} + +sl_status_t sli_mvp_hal_load_program(void *src, void *dst, size_t length) +{ + if (!mvp_is_initialized) { + return SL_STATUS_NOT_INITIALIZED; + } + if (!mvp_is_busy) { + return SL_STATUS_NOT_AVAILABLE; + } +#if SL_MVP_ENABLE_DMA + if (hal_config.use_dma) { + dma_load(src, dst, length); + } else { + cpu_load(src, dst, length); + } +#else + cpu_load(src, dst, length); +#endif + return SL_STATUS_OK; +} + +void sli_mvp_hal_cmd_enable(void) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +#endif +#if !SPEED_OVER_POWER + if (callback_enable != NULL) { + callback_enable(); + } +#endif + mvp_is_busy = true; +#if SL_MVP_POWER_MODE == 2 + set_idle_flag_initially(); + // Consume the idle flag. + uint32_t ret = osEventFlagsWait(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE, osFlagsWaitAny, osWaitForever); + EFM_ASSERT((int)ret >= 0); +#endif +} + +bool sli_mvp_hal_cmd_is_busy(void) +{ + if (!mvp_is_initialized) { + return false; + } + return mvp_is_busy; +} + +void sli_mvp_hal_cmd_wait_for_completion() +{ +#if SL_MVP_POWER_MODE == 1 + CORE_DECLARE_IRQ_STATE; +#endif + + if (!mvp_is_initialized) { + return; + } +#if SL_MVP_POWER_MODE == 2 + set_idle_flag_initially(); + uint32_t ret = osEventFlagsWait(mvp_event_id, SL_MVP_EVENT_FLAG_IDLE, osFlagsNoClear, osWaitForever); + EFM_ASSERT((int)ret >= 0); +#else + // Logically, just wait for the busy flag to go off. It's cleared in the ISR + // when the operation is complete. + // Because the busy flag is in memory, the MVP may add stalls if the flag is + // accessed during program execution. + // Mitigation: During most of the waiting, wait for the MVP to become idle. + // This is the only improvement that requires knowledge of MVP registers in HAL. + while(!(MVP->STATUS & MVP_STATUS_IDLE)) { + // Wait until the MVP is idle. +#if SL_MVP_POWER_MODE == 1 + CORE_ENTER_CRITICAL(); + if (!(MVP->STATUS & MVP_STATUS_IDLE)) { + EMU_EnterEM1(); + } + CORE_EXIT_CRITICAL(); +#endif + } + // Finally, wait for the interrupt handler to clear the flag. + // It may take a few more cycles after the MVP has become idle. + while (mvp_is_busy) { + } +#endif +} + +/** + * @brief + * MVP Interrupt handler + * + * @details + * This interrupt handler is triggered whenever a program is done or when one + * of the performance counters wraps. + */ +void MVP_IRQHandler(void) +{ + if (callback_isr != NULL) { + bool done; + done = callback_isr(); + if (done) { + cmd_disable(); + } + } +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_program_area.c b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_program_area.c index 7bade39..b348dc6 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_program_area.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_program_area.c @@ -1,47 +1,47 @@ -/***************************************************************************//** - * @file - * @brief MVP Driver program memory allocator. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp_program_area.h" - -static sli_mvp_program_context_t context; - -sli_mvp_program_t *sli_mvp_get_program_area_single(void) -{ - return &context.program[0]; -} - -sli_mvp_program_t *sli_mvp_get_program_area_double(void) -{ - return context.program; -} - -sli_mvp_program_context_t *sli_mvp_get_program_area_context(void) -{ - return &context; -} +/***************************************************************************//** + * @file + * @brief MVP Driver program memory allocator. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp_program_area.h" + +static sli_mvp_program_context_t context; + +sli_mvp_program_t *sli_mvp_get_program_area_single(void) +{ + return &context.program[0]; +} + +sli_mvp_program_t *sli_mvp_get_program_area_double(void) +{ + return context.program; +} + +sli_mvp_program_context_t *sli_mvp_get_program_area_context(void) +{ + return &context; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_util.c b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_util.c index 7941d7f..5fbd846 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_util.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/driver/mvp/src/sl_mvp_util.c @@ -1,144 +1,144 @@ -/***************************************************************************//** - * @file - * @brief MVP Utility functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" - -extern __INLINE bool sli_mvp_util_is_pointer_word_aligned(const void *pointer); - -/***************************************************************************//** - * - * sli_mvp_memclr_f16() clears 2 * batches * vecs * rows * cols bytes in memory. - * This is a crude attempt at making a general purpose MVP based memclr() - * function. - * Assumes that *dst is 4 byte aligned. - * - ******************************************************************************/ -sl_status_t sli_mvp_util_memclr_f16(sli_mvp_program_context_t *p, - void *dst, - unsigned short batches, - unsigned short vecs, - unsigned short rows, - unsigned short cols) -{ - int depth = vecs; - int height = rows; - int width = cols; - int8_t *dest = dst; - bool parallel = false; - sl_status_t status = SL_STATUS_OK; - unsigned batch_size = 2 * vecs * rows * cols; - - if (depth % 2 == 0) { - depth /= 2; - parallel = true; - } else if (height % 2 == 0) { - height /= 2; - parallel = true; - } else if (width % 2 == 0) { - width /= 2; - parallel = true; - } - - // Loop through batches which is usually only one. - for (int batch = 0; batch < batches; ++batch) { - sli_mvp_pb_begin_program(p); - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R0, 0, 0); - sli_mvp_pb_config_array_nhwc(p->p, - SLI_MVP_ARRAY(0), - dest, - parallel == true - ? SLI_MVP_DATATYPE_COMPLEX_BINARY16 - : SLI_MVP_DATATYPE_BINARY16, - height, - width, - depth, - &status); - sli_mvp_pb_begin_loop(p, depth, NULL); - sli_mvp_pb_begin_loop(p, width, NULL); - sli_mvp_pb_begin_loop(p, height, NULL); - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - SLI_MVP_NONE, - SLI_MVP_NONE, - SLI_MVP_STORE(SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT), - NULL); - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_DEPTH); - sli_mvp_pb_end_loop(p); - - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - - dest += batch_size; - } - return status; -} - -/***************************************************************************//** - * - * sli_mvp_util_factorize_number() attempts to factorize a number into - * factors that are not allowed to exceed a given max value. - * - ******************************************************************************/ -sl_status_t sli_mvp_util_factorize_number(uint32_t number, uint32_t max, uint32_t *m, uint32_t *n) -{ - static const uint8_t primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; - // Try to split the number into two factors that are less than or equal to max factor. - uint32_t a = 1; - uint32_t b = number; - sl_status_t status = SL_STATUS_OK; - - while ((b > max) || (a > max)) { - uint32_t b_prev = b; - for (size_t i = 0; i < (sizeof(primes) / sizeof(primes[0])); i++) { - uint32_t f = primes[i]; - if (b % f == 0) { - a = a * f; - b = b / f; - break; - } - } - if (b == b_prev) { - // No more factors found - status = SL_STATUS_FAIL; - break; - } - } - - *m = a; - *n = b; - return status; -} +/***************************************************************************//** + * @file + * @brief MVP Utility functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" + +extern __INLINE bool sli_mvp_util_is_pointer_word_aligned(const void *pointer); + +/***************************************************************************//** + * + * sli_mvp_memclr_f16() clears 2 * batches * vecs * rows * cols bytes in memory. + * This is a crude attempt at making a general purpose MVP based memclr() + * function. + * Assumes that *dst is 4 byte aligned. + * + ******************************************************************************/ +sl_status_t sli_mvp_util_memclr_f16(sli_mvp_program_context_t *p, + void *dst, + unsigned short batches, + unsigned short vecs, + unsigned short rows, + unsigned short cols) +{ + int depth = vecs; + int height = rows; + int width = cols; + int8_t *dest = dst; + bool parallel = false; + sl_status_t status = SL_STATUS_OK; + unsigned batch_size = 2 * vecs * rows * cols; + + if (depth % 2 == 0) { + depth /= 2; + parallel = true; + } else if (height % 2 == 0) { + height /= 2; + parallel = true; + } else if (width % 2 == 0) { + width /= 2; + parallel = true; + } + + // Loop through batches which is usually only one. + for (int batch = 0; batch < batches; ++batch) { + sli_mvp_pb_begin_program(p); + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R0, 0, 0); + sli_mvp_pb_config_array_nhwc(p->p, + SLI_MVP_ARRAY(0), + dest, + parallel == true + ? SLI_MVP_DATATYPE_COMPLEX_BINARY16 + : SLI_MVP_DATATYPE_BINARY16, + height, + width, + depth, + &status); + sli_mvp_pb_begin_loop(p, depth, NULL); + sli_mvp_pb_begin_loop(p, width, NULL); + sli_mvp_pb_begin_loop(p, height, NULL); + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + SLI_MVP_NONE, + SLI_MVP_NONE, + SLI_MVP_STORE(SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT), + NULL); + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_DEPTH); + sli_mvp_pb_end_loop(p); + + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + + dest += batch_size; + } + return status; +} + +/***************************************************************************//** + * + * sli_mvp_util_factorize_number() attempts to factorize a number into + * factors that are not allowed to exceed a given max value. + * + ******************************************************************************/ +sl_status_t sli_mvp_util_factorize_number(uint32_t number, uint32_t max, uint32_t *m, uint32_t *n) +{ + static const uint8_t primes[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31}; + // Try to split the number into two factors that are less than or equal to max factor. + uint32_t a = 1; + uint32_t b = number; + sl_status_t status = SL_STATUS_OK; + + while ((b > max) || (a > max)) { + uint32_t b_prev = b; + for (size_t i = 0; i < (sizeof(primes) / sizeof(primes[0])); i++) { + uint32_t f = primes[i]; + if (b % f == 0) { + a = a * f; + b = b / f; + break; + } + } + if (b == b_prev) { + // No more factors found + status = SL_STATUS_FAIL; + break; + } + } + + *m = a; + *n = b; + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_matrix.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_matrix.h index 6672640..74ab461 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_matrix.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_matrix.h @@ -1,72 +1,72 @@ -/***************************************************************************//** - * @file - * @brief Math matrix definitions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MATRIX_H -#define SL_MATH_MATRIX_H - -#include -#include "sl_math_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief - * Matrix data type. - */ -typedef struct { - size_t num_rows; ///< The number of rows in the matrix. - size_t num_cols; ///< The number of columns in the matrix. - float16_t *data; ///< Pointer to the matrix data. -} sl_math_matrix_f16_t; - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Matrix initialization. - * - * @param[in] matrix Pointer to a matrix. - * @param[in] num_rows The number of rows in the matrix. - * @param[in] num_cols The number of cols in the matrix. - * @param[in] data A pointer to the matrix data. - */ -void sl_math_matrix_init_f16(sl_math_matrix_f16_t *matrix, size_t num_rows, size_t num_cols, float16_t *data); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MATRIX_H +/***************************************************************************//** + * @file + * @brief Math matrix definitions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MATRIX_H +#define SL_MATH_MATRIX_H + +#include +#include "sl_math_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief + * Matrix data type. + */ +typedef struct { + size_t num_rows; ///< The number of rows in the matrix. + size_t num_cols; ///< The number of columns in the matrix. + float16_t *data; ///< Pointer to the matrix data. +} sl_math_matrix_f16_t; + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Matrix initialization. + * + * @param[in] matrix Pointer to a matrix. + * @param[in] num_rows The number of rows in the matrix. + * @param[in] num_cols The number of cols in the matrix. + * @param[in] data A pointer to the matrix data. + */ +void sl_math_matrix_init_f16(sl_math_matrix_f16_t *matrix, size_t num_rows, size_t num_cols, float16_t *data); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MATRIX_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_types.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_types.h index dbd3e3b..40b6262 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_types.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/inc/sl_math_types.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief Math type definitions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_TYPES_H -#define SL_MATH_TYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/***************************************************************************//** - * @addtogroup math_types Data types - * @{ - ******************************************************************************/ - -// Define the half precision floating point type, if not defined elsewhere. -// It will default to the 16 bits encoded in binary16 format. -#if !defined(SL_MATH_TYPE_F16) -#define SL_MATH_TYPE_F16 __fp16 -#endif - -// float16_t is a half precision floating point type. -typedef SL_MATH_TYPE_F16 float16_t; - -// Complex float16_t type. -typedef struct { - float16_t real; - float16_t imag; -} sl_math_complex_f16_t; - -/** @} (end addtogroup math_types) */ -/// @endcond - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_TYPES_H +/***************************************************************************//** + * @file + * @brief Math type definitions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_TYPES_H +#define SL_MATH_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/***************************************************************************//** + * @addtogroup math_types Data types + * @{ + ******************************************************************************/ + +// Define the half precision floating point type, if not defined elsewhere. +// It will default to the 16 bits encoded in binary16 format. +#if !defined(SL_MATH_TYPE_F16) +#define SL_MATH_TYPE_F16 __fp16 +#endif + +// float16_t is a half precision floating point type. +typedef SL_MATH_TYPE_F16 float16_t; + +// Complex float16_t type. +typedef struct { + float16_t real; + float16_t imag; +} sl_math_complex_f16_t; + +/** @} (end addtogroup math_types) */ +/// @endcond + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_TYPES_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp.h index 7728d8a..55b3075 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file sl_math_mvp.h - * @brief MVP Math functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_H -#define SL_MATH_MVP_H - -// Utilities -#include "sl_math_mvp_util.h" - -// Matrix -#include "sl_math_mvp_complex_matrix_mult.h" -#include "sl_math_mvp_matrix_add.h" -#include "sl_math_mvp_matrix_mult.h" -#include "sl_math_mvp_matrix_scale.h" -#include "sl_math_mvp_matrix_sub.h" -#include "sl_math_mvp_matrix_transpose.h" -#include "sl_math_mvp_matrix_vector_mult.h" - -// Vector -#include "sl_math_mvp_complex_vector_conjugate.h" -#include "sl_math_mvp_complex_vector_dot_product.h" -#include "sl_math_mvp_complex_vector_mult.h" -#include "sl_math_mvp_complex_vector_magnitude_squared.h" -#include "sl_math_mvp_vector_abs.h" -#include "sl_math_mvp_vector_add.h" -#include "sl_math_mvp_vector_clamp.h" -#include "sl_math_mvp_vector_clip.h" -#include "sl_math_mvp_vector_copy.h" -#include "sl_math_mvp_vector_dot_product.h" -#include "sl_math_mvp_vector_fill.h" -#include "sl_math_mvp_vector_mult.h" -#include "sl_math_mvp_vector_negate.h" -#include "sl_math_mvp_vector_scale.h" -#include "sl_math_mvp_vector_sub.h" - -/* *INDENT-OFF* */ -/************ THIS SECTION IS FOR DOCUMENTATION ONLY !**********************//** - * - * @defgroup math_mvp_vector Vector functions - * @defgroup math_mvp_matrix Matrix functions - * - */ - -#endif // SL_MATH_MVP_H +/***************************************************************************//** + * @file sl_math_mvp.h + * @brief MVP Math functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_H +#define SL_MATH_MVP_H + +// Utilities +#include "sl_math_mvp_util.h" + +// Matrix +#include "sl_math_mvp_complex_matrix_mult.h" +#include "sl_math_mvp_matrix_add.h" +#include "sl_math_mvp_matrix_mult.h" +#include "sl_math_mvp_matrix_scale.h" +#include "sl_math_mvp_matrix_sub.h" +#include "sl_math_mvp_matrix_transpose.h" +#include "sl_math_mvp_matrix_vector_mult.h" + +// Vector +#include "sl_math_mvp_complex_vector_conjugate.h" +#include "sl_math_mvp_complex_vector_dot_product.h" +#include "sl_math_mvp_complex_vector_mult.h" +#include "sl_math_mvp_complex_vector_magnitude_squared.h" +#include "sl_math_mvp_vector_abs.h" +#include "sl_math_mvp_vector_add.h" +#include "sl_math_mvp_vector_clamp.h" +#include "sl_math_mvp_vector_clip.h" +#include "sl_math_mvp_vector_copy.h" +#include "sl_math_mvp_vector_dot_product.h" +#include "sl_math_mvp_vector_fill.h" +#include "sl_math_mvp_vector_mult.h" +#include "sl_math_mvp_vector_negate.h" +#include "sl_math_mvp_vector_scale.h" +#include "sl_math_mvp_vector_sub.h" + +/* *INDENT-OFF* */ +/************ THIS SECTION IS FOR DOCUMENTATION ONLY !**********************//** + * + * @defgroup math_mvp_vector Vector functions + * @defgroup math_mvp_matrix Matrix functions + * + */ + +#endif // SL_MATH_MVP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_matrix_mult.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_matrix_mult.h index d2b72b1..cf3cf93 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_matrix_mult.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_matrix_mult.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mult functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_COMPLEX_MATRIX_MULT_H -#define SL_MATH_MVP_COMPLEX_MATRIX_MULT_H - -#include "sl_status.h" -#include "sl_math_matrix.h" -#include "sl_mvp_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Multiply two matrices of complex 16 bit floats. - * - * @details - * The number of columns of the first matrix must be equal to the number of - * rows of the second matrix. Also the output matrix row count must match - * matrix A row count and output matrix column count must match matrix - * B column count. - * All input and output matrix data buffers must be 4-byte aligned (a complex - * f16 element occupies 4 bytes of storage). - * Maximum matrix size is 1024 x 1024 which is 1M (2^20) complex f16 elements. - * Maximum column and row size is 1024 elements. - * - * @param[in] input_a First input matrix, input A. - * @param[in] input_b Second input matrix, input B. - * @param[out] output Output matrix, output Z. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_COMPLEX_MATRIX_MULT_H +/***************************************************************************//** + * @file + * @brief MVP Math Mult functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_COMPLEX_MATRIX_MULT_H +#define SL_MATH_MVP_COMPLEX_MATRIX_MULT_H + +#include "sl_status.h" +#include "sl_math_matrix.h" +#include "sl_mvp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Multiply two matrices of complex 16 bit floats. + * + * @details + * The number of columns of the first matrix must be equal to the number of + * rows of the second matrix. Also the output matrix row count must match + * matrix A row count and output matrix column count must match matrix + * B column count. + * All input and output matrix data buffers must be 4-byte aligned (a complex + * f16 element occupies 4 bytes of storage). + * Maximum matrix size is 1024 x 1024 which is 1M (2^20) complex f16 elements. + * Maximum column and row size is 1024 elements. + * + * @param[in] input_a First input matrix, input A. + * @param[in] input_b Second input matrix, input B. + * @param[out] output Output matrix, output Z. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_COMPLEX_MATRIX_MULT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_conjugate.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_conjugate.h index dc810ac..022136e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_conjugate.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_conjugate.h @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex conjugate functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H -#define SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Conjugates the elements of a complex data vector. - * - * @details - * Maximum vector length is 1M (2^20), and all vectors must be 4-byte aligned. - * - * @param[in] input Input vector. - * @param[in] output Output Vector. - * @param[in] num_elements The number of complex elements in the vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_vector_conjugate_f16(float16_t *input, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H +/***************************************************************************//** + * @file + * @brief MVP Math vector complex conjugate functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H +#define SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Conjugates the elements of a complex data vector. + * + * @details + * Maximum vector length is 1M (2^20), and all vectors must be 4-byte aligned. + * + * @param[in] input Input vector. + * @param[in] output Output Vector. + * @param[in] num_elements The number of complex elements in the vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_vector_conjugate_f16(float16_t *input, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_COMPLEX_VECTOR_CONJUGATE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_dot_product.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_dot_product.h index d5144af..fc04820 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_dot_product.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_dot_product.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex dot product functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H -#define SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Computes the dot product of two complex vectors. - * The vectors are multiplied element-by-element and then summed. - * - * @details - * Maximum vector length is 1M (2^20), and all vectors must be 4-byte aligned. - * - * @param[in] input_a Input vector a. - * @param[in] input_b Input vector b. - * @param[in] num_elements The number of complex elements in the input vectors. - * @param[out] output Dot product result. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_vector_dot_product_f16(float16_t *input_a, - float16_t *input_b, - size_t num_elements, - float16_t *output); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H +/***************************************************************************//** + * @file + * @brief MVP Math vector complex dot product functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H +#define SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Computes the dot product of two complex vectors. + * The vectors are multiplied element-by-element and then summed. + * + * @details + * Maximum vector length is 1M (2^20), and all vectors must be 4-byte aligned. + * + * @param[in] input_a Input vector a. + * @param[in] input_b Input vector b. + * @param[in] num_elements The number of complex elements in the input vectors. + * @param[out] output Dot product result. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_vector_dot_product_f16(float16_t *input_a, + float16_t *input_b, + size_t num_elements, + float16_t *output); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_COMPLEX_VECTOR_DOT_PRODUCT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_magnitude_squared.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_magnitude_squared.h index 281e04b..efbd155 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_magnitude_squared.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_magnitude_squared.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex magnitude squared functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H -#define SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Computes the magnitude squared of the elements of a complex data vector. - * - * @details - * The input vector shall point to the source that is a vector of complex - * numbers and the output vector shall point to a vector where the result - * will be written. - * - * @param[in] input Input vector. - * @param[in] output Output Vector. - * @param[in] num_elements The number of complex elements in the input vector and - * the number of scalar elements in the output vector. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_vector_magnitude_squared_f16(const float16_t *input, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H +/***************************************************************************//** + * @file + * @brief MVP Math vector complex magnitude squared functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H +#define SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Computes the magnitude squared of the elements of a complex data vector. + * + * @details + * The input vector shall point to the source that is a vector of complex + * numbers and the output vector shall point to a vector where the result + * will be written. + * + * @param[in] input Input vector. + * @param[in] output Output Vector. + * @param[in] num_elements The number of complex elements in the input vector and + * the number of scalar elements in the output vector. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_vector_magnitude_squared_f16(const float16_t *input, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_COMPLEX_VECTOR_MAGNITUDE_SQUARED_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_mult.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_mult.h index 8536b56..376a2cc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_mult.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_complex_vector_mult.h @@ -1,102 +1,102 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mult functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_COMPLEX_VECTOR_MULT_H -#define SL_MATH_MVP_COMPLEX_VECTOR_MULT_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Multiply a vector of complex f16 by a vector of real f16. - * - * @details - * This function will perform the following operation: Z = A * B. - * Both vectors must be of same length. If both vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP complex - * processing. - * Maximum vector length is 1M (2^20) elements in the 4-byte aligned case, - * and 512K when oen or more of the complex vectors are 2-byte aligned. - * - * @param[in] input_a The complex vector, input A. - * @param[in] input_b The real vector, input B. - * @param[out] output The complex output vector, output Z. - * @param[in] num_elements The number of elements in the input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_vector_mult_real_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements); - -/** - * @brief - * Multiply complex f16 vectors. - * - * @details - * This function will multiply two complex vectors. It is assumed that both - * input vectors, and the output vector have same length. All input and output - * buffers must be 4-byte aligned. - * Maximum vector length is 1M (2^20) elements. - * - * @param[in] input_a Complex input vector A. - * @param[in] input_b Complex input vector B. - * @param[out] output Complex output vector. - * @param[in] num_elements The number of complex elements in the input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_vector_mult_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup mvp_math_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_COMPLEX_VECTOR_MULT_H +/***************************************************************************//** + * @file + * @brief MVP Math Mult functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_COMPLEX_VECTOR_MULT_H +#define SL_MATH_MVP_COMPLEX_VECTOR_MULT_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Multiply a vector of complex f16 by a vector of real f16. + * + * @details + * This function will perform the following operation: Z = A * B. + * Both vectors must be of same length. If both vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP complex + * processing. + * Maximum vector length is 1M (2^20) elements in the 4-byte aligned case, + * and 512K when oen or more of the complex vectors are 2-byte aligned. + * + * @param[in] input_a The complex vector, input A. + * @param[in] input_b The real vector, input B. + * @param[out] output The complex output vector, output Z. + * @param[in] num_elements The number of elements in the input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_vector_mult_real_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements); + +/** + * @brief + * Multiply complex f16 vectors. + * + * @details + * This function will multiply two complex vectors. It is assumed that both + * input vectors, and the output vector have same length. All input and output + * buffers must be 4-byte aligned. + * Maximum vector length is 1M (2^20) elements. + * + * @param[in] input_a Complex input vector A. + * @param[in] input_b Complex input vector B. + * @param[out] output Complex output vector. + * @param[in] num_elements The number of complex elements in the input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_vector_mult_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup mvp_math_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_COMPLEX_VECTOR_MULT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_add.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_add.h index 362d7d0..6ffefc3 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_add.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_add.h @@ -1,107 +1,107 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Add function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_ADD_H -#define SL_MATH_MVP_MATRIX_ADD_H - -#include "sl_status.h" -#include "sl_mvp.h" -#include "sl_math_matrix.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Add two matrices of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A + B. - * All matrices must have equal dimensions. If all matrice buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum matrices size is 1M (2^20) elements, and 2M elements in the - * 4-byte aligned case. - * - * @param[in] input_a First input matrix, input A. - * @param[in] input_b Second input matrix, input B. - * @param[out] output Output matrix, output Z. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_add_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output); - -/** - * @brief - * Add two matrices of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A + B. - * The function do not perform any parameter checking, is assumes that - * that has already been taken care of. - * If matrice buffers are 4-byte aligned, the function will operate twice as - * fast using MVP parallel processing. - * Maximum matrices size is 1M (2^20) elements, and 2M elements in the - * 4-byte aligned case. - * - * @param[in] input_a First input matrix data pointer. - * @param[in] input_b Second input matrix data pointer. - * @param[out] output Output matrix data pointer. - * @param[in] num_cols Number of matrix columns. - * @param[in] num_rows Number of matrix rows. - * @param[in] data_type @refSLI_MVP_DATATYPE_BINARY16 or @ref SLI_MVP_DATATYPE_COMPLEX_BINARY16. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sli_math_mvp_matrix_add_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_rows, - size_t num_cols, - sli_mvp_datatype_t data_type); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_ADD_H +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Add function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_ADD_H +#define SL_MATH_MVP_MATRIX_ADD_H + +#include "sl_status.h" +#include "sl_mvp.h" +#include "sl_math_matrix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Add two matrices of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A + B. + * All matrices must have equal dimensions. If all matrice buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum matrices size is 1M (2^20) elements, and 2M elements in the + * 4-byte aligned case. + * + * @param[in] input_a First input matrix, input A. + * @param[in] input_b Second input matrix, input B. + * @param[out] output Output matrix, output Z. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_add_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output); + +/** + * @brief + * Add two matrices of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A + B. + * The function do not perform any parameter checking, is assumes that + * that has already been taken care of. + * If matrice buffers are 4-byte aligned, the function will operate twice as + * fast using MVP parallel processing. + * Maximum matrices size is 1M (2^20) elements, and 2M elements in the + * 4-byte aligned case. + * + * @param[in] input_a First input matrix data pointer. + * @param[in] input_b Second input matrix data pointer. + * @param[out] output Output matrix data pointer. + * @param[in] num_cols Number of matrix columns. + * @param[in] num_rows Number of matrix rows. + * @param[in] data_type @refSLI_MVP_DATATYPE_BINARY16 or @ref SLI_MVP_DATATYPE_COMPLEX_BINARY16. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sli_math_mvp_matrix_add_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_rows, + size_t num_cols, + sli_mvp_datatype_t data_type); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_ADD_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_mult.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_mult.h index 8528ecd..036c1ca 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_mult.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_mult.h @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mult functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_MULT_H -#define SL_MATH_MVP_MATRIX_MULT_H - -#include "sl_status.h" -#include "sl_math_matrix.h" -#include "sl_mvp_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Multiply two matrices of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A * B (matrix multiplication). - * The number of columns of the first matrix must be equal to the number of rows of the second matrix. - * If the input is 4 bytes aligned, and the number of columns in matrix B is divisible by 2, it will be 2x faster. - * - * @param[in] input_a First input matrix, input A. - * @param[in] input_b Second input matrix, input B. - * @param[out] output Output matrix, output Z. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, const sl_math_matrix_f16_t *input_b, sl_math_matrix_f16_t *output); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_MULT_H +/***************************************************************************//** + * @file + * @brief MVP Math Mult functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_MULT_H +#define SL_MATH_MVP_MATRIX_MULT_H + +#include "sl_status.h" +#include "sl_math_matrix.h" +#include "sl_mvp_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Multiply two matrices of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A * B (matrix multiplication). + * The number of columns of the first matrix must be equal to the number of rows of the second matrix. + * If the input is 4 bytes aligned, and the number of columns in matrix B is divisible by 2, it will be 2x faster. + * + * @param[in] input_a First input matrix, input A. + * @param[in] input_b Second input matrix, input B. + * @param[out] output Output matrix, output Z. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, const sl_math_matrix_f16_t *input_b, sl_math_matrix_f16_t *output); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_MULT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_scale.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_scale.h index 6a6ebdc..a74f986 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_scale.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_scale.h @@ -1,67 +1,67 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mult functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_SCALE_H -#define SL_MATH_MVP_MATRIX_SCALE_H - -#include "sl_common.h" -#include "sl_math_matrix.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ -/** - * @brief - * Scale each element in a float16 matrix by a float16 scale. - * - * @details - * This function will multiply each element in the input matrix by a scale, and write the result to the output matrix. - * The input and output matrices must be the same size. - * @param[in] input Input matrix. - * @param[in] scale Scale value. - * @param[out] output Output matrix. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_scale_f16(const sl_math_matrix_f16_t *input, float16_t scale, sl_math_matrix_f16_t *output); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_SCALE_H +/***************************************************************************//** + * @file + * @brief MVP Math Mult functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_SCALE_H +#define SL_MATH_MVP_MATRIX_SCALE_H + +#include "sl_common.h" +#include "sl_math_matrix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ +/** + * @brief + * Scale each element in a float16 matrix by a float16 scale. + * + * @details + * This function will multiply each element in the input matrix by a scale, and write the result to the output matrix. + * The input and output matrices must be the same size. + * @param[in] input Input matrix. + * @param[in] scale Scale value. + * @param[out] output Output matrix. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_scale_f16(const sl_math_matrix_f16_t *input, float16_t scale, sl_math_matrix_f16_t *output); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_SCALE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_sub.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_sub.h index abb2e39..d612b9a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_sub.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_sub.h @@ -1,107 +1,107 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Subtract function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_SUB_H -#define SL_MATH_MVP_MATRIX_SUB_H - -#include "sl_status.h" -#include "sl_mvp.h" -#include "sl_math_matrix.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Subtract two matrices of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A - B. - * All matrices must have equal dimensions. If all matrice buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum matrices size is 1M (2^20) elements, and 2M elements in the - * 4-byte aligned case. - * - * @param[in] input_a First input matrix, input A. - * @param[in] input_b Second input matrix, input B. - * @param[out] output Output matrix, output Z. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_sub_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output); - -/** - * @brief - * Subtract two matrices of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A - B. - * The function do not perform any parameter checking, is assumes that - * that has already been taken care of. - * If matrice buffers are 4-byte aligned, the function will operate twice as - * fast using MVP parallel processing. - * Maximum matrices size is 1M (2^20) elements, and 2M elements in the - * 4-byte aligned case. - * - * @param[in] input_a First input matrix data pointer. - * @param[in] input_b Second input matrix data pointer. - * @param[out] output Output matrix data pointer. - * @param[in] num_cols Number of matrix columns. - * @param[in] num_rows Number of matrix rows. - * @param[in] data_type @refSLI_MVP_DATATYPE_BINARY16 or @ref SLI_MVP_DATATYPE_COMPLEX_BINARY16. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sli_math_mvp_matrix_sub_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_rows, - size_t num_cols, - sli_mvp_datatype_t data_type); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_SUB_H +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Subtract function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_SUB_H +#define SL_MATH_MVP_MATRIX_SUB_H + +#include "sl_status.h" +#include "sl_mvp.h" +#include "sl_math_matrix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Subtract two matrices of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A - B. + * All matrices must have equal dimensions. If all matrice buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum matrices size is 1M (2^20) elements, and 2M elements in the + * 4-byte aligned case. + * + * @param[in] input_a First input matrix, input A. + * @param[in] input_b Second input matrix, input B. + * @param[out] output Output matrix, output Z. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_sub_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output); + +/** + * @brief + * Subtract two matrices of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A - B. + * The function do not perform any parameter checking, is assumes that + * that has already been taken care of. + * If matrice buffers are 4-byte aligned, the function will operate twice as + * fast using MVP parallel processing. + * Maximum matrices size is 1M (2^20) elements, and 2M elements in the + * 4-byte aligned case. + * + * @param[in] input_a First input matrix data pointer. + * @param[in] input_b Second input matrix data pointer. + * @param[out] output Output matrix data pointer. + * @param[in] num_cols Number of matrix columns. + * @param[in] num_rows Number of matrix rows. + * @param[in] data_type @refSLI_MVP_DATATYPE_BINARY16 or @ref SLI_MVP_DATATYPE_COMPLEX_BINARY16. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sli_math_mvp_matrix_sub_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_rows, + size_t num_cols, + sli_mvp_datatype_t data_type); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_SUB_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_transpose.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_transpose.h index 9246587..05750f8 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_transpose.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_transpose.h @@ -1,90 +1,90 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Transpose functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_TRANSPOSE_H -#define SL_MATH_MVP_MATRIX_TRANSPOSE_H - -#include "sl_status.h" -#include "sl_math_matrix.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Transpose a matrix. - * - * @details - * This function will fill the output matrix with the transposed version of - * the input matrix. - * The maximum value for the rows and cols argument is 1024. - * - * @param[in] input Input matrix. - * @param[out] output output matrix. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_transpose_f16(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output); - -/** - * @brief - * Transpose a complex f16 matrix. - * - * @details - * This function will fill the output matrix with the transposed version of - * the input matrix. - * The maximum value for the rows and cols argument is 1024. - * Matrix input and output data buffers must be 4-byte aligned. - * - * @param[in] input Input matrix. - * @param[out] output output matrix. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_complex_matrix_transpose_f16(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_TRANSPOSE_H +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Transpose functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_TRANSPOSE_H +#define SL_MATH_MVP_MATRIX_TRANSPOSE_H + +#include "sl_status.h" +#include "sl_math_matrix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Transpose a matrix. + * + * @details + * This function will fill the output matrix with the transposed version of + * the input matrix. + * The maximum value for the rows and cols argument is 1024. + * + * @param[in] input Input matrix. + * @param[out] output output matrix. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_transpose_f16(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output); + +/** + * @brief + * Transpose a complex f16 matrix. + * + * @details + * This function will fill the output matrix with the transposed version of + * the input matrix. + * The maximum value for the rows and cols argument is 1024. + * Matrix input and output data buffers must be 4-byte aligned. + * + * @param[in] input Input matrix. + * @param[out] output output matrix. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_complex_matrix_transpose_f16(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_TRANSPOSE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_vector_mult.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_vector_mult.h index b9779f0..3dc66e9 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_vector_mult.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_matrix_vector_mult.h @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Vector Mult functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_MATRIX_VECTOR_MULT_H -#define SL_MATH_MVP_MATRIX_VECTOR_MULT_H - -#include "sl_common.h" -#include "sl_math_matrix.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_matrix - * @{ - ******************************************************************************/ - -/** - * @brief - * Multiply a matrix with a vector, both of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A * b (matrix vector multiplication). - * The vector must be equal in length to the number of columns in matrix A. The output vector will be equal in length to the number of rows in matrix A. - * - * @param[in] input_a The input matrix. - * @param[in] input_b The input vector. - * @param[out] output The output vector. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_matrix_vector_mult_f16(const sl_math_matrix_f16_t *input_a, const float16_t *input_b, float16_t *output); - -/** @} (end addtogroup math_mvp_matrix) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_MATRIX_VECTOR_MULT_H +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Vector Mult functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_MATRIX_VECTOR_MULT_H +#define SL_MATH_MVP_MATRIX_VECTOR_MULT_H + +#include "sl_common.h" +#include "sl_math_matrix.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_matrix + * @{ + ******************************************************************************/ + +/** + * @brief + * Multiply a matrix with a vector, both of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A * b (matrix vector multiplication). + * The vector must be equal in length to the number of columns in matrix A. The output vector will be equal in length to the number of rows in matrix A. + * + * @param[in] input_a The input matrix. + * @param[in] input_b The input vector. + * @param[out] output The output vector. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_matrix_vector_mult_f16(const sl_math_matrix_f16_t *input_a, const float16_t *input_b, float16_t *output); + +/** @} (end addtogroup math_mvp_matrix) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_MATRIX_VECTOR_MULT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_util.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_util.h index 2888896..353b941 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_util.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_util.h @@ -1,82 +1,82 @@ -/***************************************************************************//** - * @file - * @brief MVP Math utility functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_UTIL_H -#define SL_MATH_MVP_UTIL_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_util Utility functions - * @{ - ******************************************************************************/ - -/** - * @brief - * Clear all Math exception and fault flags. - */ -void sl_math_mvp_clear_errors(void); - -/** - * @brief - * Get a Math exception or fault errorcode and optional descriptive - * error message. - * - * @details - * Intended use of this function is to call it repeatedly to iterate over - * existing errors and get errorcodes and optional error message strings. - * - * @param[out] error_code - * The assigned sl_status_t errorcode. - * - * @param[in,out] error_message - * A descriptive error message string. Input a NULL pointer to skip - * the error message. - * - * @param[in] buffer_length - * The size of the error_message buffer. - * - * @return - * Return SL_STATUS_OK when an error is present, this indicates that - * error_code and optionally error_message output parameters are valid. - * Return SL_STATUS_NOT_FOUND when no error to report. - */ -sl_status_t sl_math_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length); - -/** @} (end addtogroup math_mvp_util) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_UTIL_H +/***************************************************************************//** + * @file + * @brief MVP Math utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_UTIL_H +#define SL_MATH_MVP_UTIL_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_util Utility functions + * @{ + ******************************************************************************/ + +/** + * @brief + * Clear all Math exception and fault flags. + */ +void sl_math_mvp_clear_errors(void); + +/** + * @brief + * Get a Math exception or fault errorcode and optional descriptive + * error message. + * + * @details + * Intended use of this function is to call it repeatedly to iterate over + * existing errors and get errorcodes and optional error message strings. + * + * @param[out] error_code + * The assigned sl_status_t errorcode. + * + * @param[in,out] error_message + * A descriptive error message string. Input a NULL pointer to skip + * the error message. + * + * @param[in] buffer_length + * The size of the error_message buffer. + * + * @return + * Return SL_STATUS_OK when an error is present, this indicates that + * error_code and optionally error_message output parameters are valid. + * Return SL_STATUS_NOT_FOUND when no error to report. + */ +sl_status_t sl_math_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length); + +/** @} (end addtogroup math_mvp_util) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_UTIL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_abs.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_abs.h index 2755be0..34eacb8 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_abs.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_abs.h @@ -1,72 +1,72 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector ABS functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_ABS_H -#define SL_MATH_MVP_VECTOR_ABS_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Computes the absolute value of a vector on an element-by-element basis. - * - * @details - * The output vector can be the same as or differnt to the input vector. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input Input vector. - * @param[in] output Output Vector. - * @param[in] num_elements The number of elements in the vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_abs_f16(float16_t *input, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_ABS_H +/***************************************************************************//** + * @file + * @brief MVP Math Vector ABS functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_ABS_H +#define SL_MATH_MVP_VECTOR_ABS_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Computes the absolute value of a vector on an element-by-element basis. + * + * @details + * The output vector can be the same as or differnt to the input vector. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input Input vector. + * @param[in] output Output Vector. + * @param[in] num_elements The number of elements in the vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_abs_f16(float16_t *input, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_ABS_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_add.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_add.h index c3ca039..28ed68c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_add.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_add.h @@ -1,100 +1,100 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Add function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_ADD_H -#define SL_MATH_MVP_VECTOR_ADD_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Add two vectors of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A + B. - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input_a First input vector, input A. - * @param[in] input_b Second input vector, input B. - * @param[out] output Output vector, output Z. - * @param[in] num_elements The number of elements in the vectors. - - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_add_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements); - -/** - * @brief - * Add two vectors of signed 8 bit integers. - * - * @details - * All vectors must be of the same length. This function will perform the - * following operation: Z = A + B. The add operation is performing a saturation - * add, which means that the operation will never overflow or underflow. - * When adding two elements would overflow (>127) then the result - * will be 127. When adding two elements would underflow (<-128) - * then the result will be -128. - * - * @param[in] input_a First input vector, input A. - * @param[in] input_b Second input vector, input B. - * @param[out] output Output vector, output Z. - * @param[in] num_elements The number of elements in the vectors. - * - * @return - * @ref SL_STATUS_OK. - */ -sl_status_t sl_math_mvp_vector_add_i8(const int8_t *input_a, const int8_t *input_b, int8_t *output, size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_ADD_H +/***************************************************************************//** + * @file + * @brief MVP Math Vector Add function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_ADD_H +#define SL_MATH_MVP_VECTOR_ADD_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Add two vectors of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A + B. + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input_a First input vector, input A. + * @param[in] input_b Second input vector, input B. + * @param[out] output Output vector, output Z. + * @param[in] num_elements The number of elements in the vectors. + + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_add_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements); + +/** + * @brief + * Add two vectors of signed 8 bit integers. + * + * @details + * All vectors must be of the same length. This function will perform the + * following operation: Z = A + B. The add operation is performing a saturation + * add, which means that the operation will never overflow or underflow. + * When adding two elements would overflow (>127) then the result + * will be 127. When adding two elements would underflow (<-128) + * then the result will be -128. + * + * @param[in] input_a First input vector, input A. + * @param[in] input_b Second input vector, input B. + * @param[out] output Output vector, output Z. + * @param[in] num_elements The number of elements in the vectors. + * + * @return + * @ref SL_STATUS_OK. + */ +sl_status_t sl_math_mvp_vector_add_i8(const int8_t *input_a, const int8_t *input_b, int8_t *output, size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_ADD_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clamp.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clamp.h index 8a338f7..f4707f5 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clamp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clamp.h @@ -1,73 +1,73 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Clamp function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_CLAMP_H -#define SL_MATH_MVP_VECTOR_CLAMP_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Clamp all signed 8 bit integers in a vector to a certain range. - * - * @details - * Given a min/max value, this function will make sure that none of the element - * in the input vector will be < min or > max. If any elements are < min then - * the value will be modified to min. If any elements are > max then value will - * be modified to max. - * - * @param[inout] data Vector with data values. - * @param[in] num_elements The number of elements in the vector. - * @param[in] min Minimum value, after operation no elements will be < min. - * @param[in] max Maximum value, after operation no elements will be > max. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_CLAMP_H +/***************************************************************************//** + * @file + * @brief MVP Math Vector Clamp function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_CLAMP_H +#define SL_MATH_MVP_VECTOR_CLAMP_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Clamp all signed 8 bit integers in a vector to a certain range. + * + * @details + * Given a min/max value, this function will make sure that none of the element + * in the input vector will be < min or > max. If any elements are < min then + * the value will be modified to min. If any elements are > max then value will + * be modified to max. + * + * @param[inout] data Vector with data values. + * @param[in] num_elements The number of elements in the vector. + * @param[in] min Minimum value, after operation no elements will be < min. + * @param[in] max Maximum value, after operation no elements will be > max. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_CLAMP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clip.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clip.h index f417990..8006ffb 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clip.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_clip.h @@ -1,80 +1,80 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector clip functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_CLIP_H -#define SL_MATH_MVP_VECTOR_CLIP_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Element-by-element clipping of a value. - * - * @details - * This function will do an element-by-element clipping of a value. - * The value is constrained between 2 bounds. - * Both vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input Input vector, input A. - * @param[out] output Output vector, output Z. - * @param[in] low Lower bound. - * @param[in] high Higher bound. - * @param[in] num_elements Length of input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_clip_f16(const float16_t *input, - float16_t *output, - float16_t low, - float16_t high, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_CLIP_H +/***************************************************************************//** + * @file + * @brief MVP Math vector clip functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_CLIP_H +#define SL_MATH_MVP_VECTOR_CLIP_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Element-by-element clipping of a value. + * + * @details + * This function will do an element-by-element clipping of a value. + * The value is constrained between 2 bounds. + * Both vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input Input vector, input A. + * @param[out] output Output vector, output Z. + * @param[in] low Lower bound. + * @param[in] high Higher bound. + * @param[in] num_elements Length of input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_clip_f16(const float16_t *input, + float16_t *output, + float16_t low, + float16_t high, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_CLIP_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_copy.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_copy.h index 68cac29..6b64ae1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_copy.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_copy.h @@ -1,75 +1,75 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector copy functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_COPY_H -#define SL_MATH_MVP_VECTOR_COPY_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Copy one 16 bit float vector into another. - * - * @details - * This function will perform the following operation: Z = A. - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input Input vector, input A. - * @param[out] output Output vector, output Z. - * @param[in] num_elements Length of input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_copy_f16(const float16_t *input, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_COPY_H +/***************************************************************************//** + * @file + * @brief MVP Math vector copy functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_COPY_H +#define SL_MATH_MVP_VECTOR_COPY_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Copy one 16 bit float vector into another. + * + * @details + * This function will perform the following operation: Z = A. + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input Input vector, input A. + * @param[out] output Output vector, output Z. + * @param[in] num_elements Length of input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_copy_f16(const float16_t *input, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_COPY_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_dot_product.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_dot_product.h index 3d78607..d026172 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_dot_product.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_dot_product.h @@ -1,83 +1,83 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector dot product functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_DOT_PRODUCT_H -#define SL_MATH_MVP_VECTOR_DOT_PRODUCT_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Computes the dot product of two vectors. - * The vectors are multiplied element-by-element and then summed. - * - * @details - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @note - * Depending on the function arguments, the MVP implementation can calculate - * the dot product in different ways that may effect the rounding errors. - * If the same input vectors are calculated with different memory alignmen, - * the results may not be identical. - * - * @param[in] input_a Input vector a. - * @param[in] input_b Input vector b. - * @param[in] num_elements The number of elements in the input vectors. - * @param[out] output The result. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_dot_product_f16(const float16_t *input_a, - const float16_t *input_b, - size_t num_elements, - float16_t *output); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_DOT_PRODUCT_H +/***************************************************************************//** + * @file + * @brief MVP Math vector dot product functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_DOT_PRODUCT_H +#define SL_MATH_MVP_VECTOR_DOT_PRODUCT_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Computes the dot product of two vectors. + * The vectors are multiplied element-by-element and then summed. + * + * @details + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @note + * Depending on the function arguments, the MVP implementation can calculate + * the dot product in different ways that may effect the rounding errors. + * If the same input vectors are calculated with different memory alignmen, + * the results may not be identical. + * + * @param[in] input_a Input vector a. + * @param[in] input_b Input vector b. + * @param[in] num_elements The number of elements in the input vectors. + * @param[out] output The result. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_dot_product_f16(const float16_t *input_a, + const float16_t *input_b, + size_t num_elements, + float16_t *output); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_DOT_PRODUCT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_fill.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_fill.h index a4a1fde..ef3d23d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_fill.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_fill.h @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector fill functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_FILL_H -#define SL_MATH_MVP_VECTOR_FILL_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Fills a constant value into a floating-point vector. - * - * @details - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] output Vector to fill. - * @param[in] value Fill value. - * @param[in] num_elements Length of the output vector. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_fill_f16(float16_t *output, - const float16_t value, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_FILL_H +/***************************************************************************//** + * @file + * @brief MVP Math vector fill functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_FILL_H +#define SL_MATH_MVP_VECTOR_FILL_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Fills a constant value into a floating-point vector. + * + * @details + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] output Vector to fill. + * @param[in] value Fill value. + * @param[in] num_elements Length of the output vector. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_fill_f16(float16_t *output, + const float16_t value, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_FILL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_mult.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_mult.h index 73b3020..4f80adb 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_mult.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_mult.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mult functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_MULT_H -#define SL_MATH_MVP_VECTOR_MULT_H - -#include "sl_status.h" -#include "sl_mvp_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Elementwise multiply two vectors of 16 bit floats. - * - * @details - * This function will perform the following operation: Z[i] = A[i] * B[i]. - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input_a First input vector, input A. - * @param[in] input_b Second input vector, input B. - * @param[out] output Output vector, output Z. - * @param[in] num_elements Length of all input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_mult_f16(const float16_t *input_a, const float16_t *input_b, float16_t *output, size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_MULT_H +/***************************************************************************//** + * @file + * @brief MVP Math Mult functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_MULT_H +#define SL_MATH_MVP_VECTOR_MULT_H + +#include "sl_status.h" +#include "sl_mvp_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Elementwise multiply two vectors of 16 bit floats. + * + * @details + * This function will perform the following operation: Z[i] = A[i] * B[i]. + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input_a First input vector, input A. + * @param[in] input_b Second input vector, input B. + * @param[out] output Output vector, output Z. + * @param[in] num_elements Length of all input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_mult_f16(const float16_t *input_a, const float16_t *input_b, float16_t *output, size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_MULT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_negate.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_negate.h index a762027..638ae63 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_negate.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_negate.h @@ -1,76 +1,76 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Negate function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_NEGATE_H -#define SL_MATH_MVP_VECTOR_NEGATE_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Negate a vector of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = - A. - * Vectors must be of equal length. If both vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * In-place negation is supported (input and output reference same buffer). - * - * @param[in] input Input vector. - * @param[out] output Output vector. - * @param[in] num_elements Length of input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_negate_f16(const float16_t *input, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_NEGATE_H +/***************************************************************************//** + * @file + * @brief MVP Math Vector Negate function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_NEGATE_H +#define SL_MATH_MVP_VECTOR_NEGATE_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Negate a vector of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = - A. + * Vectors must be of equal length. If both vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * In-place negation is supported (input and output reference same buffer). + * + * @param[in] input Input vector. + * @param[out] output Output vector. + * @param[in] num_elements Length of input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_negate_f16(const float16_t *input, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_NEGATE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_offset.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_offset.h index 63073f2..c028c73 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_offset.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_offset.h @@ -1,73 +1,73 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector offset functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_OFFSET_H -#define SL_MATH_MVP_VECTOR_OFFSET_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Adds a constant offset to each element of a vector. - * - * @details - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input Input vector. - * @param[in] offset Offset value. - * @param[in] output Output vector. - * @param[in] num_elements The number of elements in the input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_offset_f16(const float16_t *input, - const float16_t offset, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_OFFSET_H +/***************************************************************************//** + * @file + * @brief MVP Math vector offset functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_OFFSET_H +#define SL_MATH_MVP_VECTOR_OFFSET_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Adds a constant offset to each element of a vector. + * + * @details + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input Input vector. + * @param[in] offset Offset value. + * @param[in] output Output vector. + * @param[in] num_elements The number of elements in the input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_offset_f16(const float16_t *input, + const float16_t offset, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_OFFSET_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_scale.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_scale.h index 75caee4..e6aeffb 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_scale.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_scale.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Scale functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_SCALE_H -#define SL_MATH_MVP_VECTOR_SCALE_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Scale a vector of 16-bits floats with a float16 scale. - * - * @details - * This function will perform the following operation: Z[i] = A[i] * scale. - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input The input vector. - * @param[in] scale The value by which to scale the vector. - * @param[out] output Output vector, output Z. - * @param[in] num_elements Length of input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_scale_f16(const float16_t *input, float16_t scale, float16_t *output, size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_SCALE_H +/***************************************************************************//** + * @file + * @brief MVP Math Scale functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_SCALE_H +#define SL_MATH_MVP_VECTOR_SCALE_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Scale a vector of 16-bits floats with a float16 scale. + * + * @details + * This function will perform the following operation: Z[i] = A[i] * scale. + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input The input vector. + * @param[in] scale The value by which to scale the vector. + * @param[out] output Output vector, output Z. + * @param[in] num_elements Length of input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_scale_f16(const float16_t *input, float16_t scale, float16_t *output, size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_SCALE_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_sub.h b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_sub.h index 6ca7a5a..115ce3f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_sub.h +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/inc/sl_math_mvp_vector_sub.h @@ -1,77 +1,77 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Sub function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MATH_MVP_VECTOR_SUB_H -#define SL_MATH_MVP_VECTOR_SUB_H - -#include "sl_status.h" -#include "sl_math_types.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup math_mvp_vector - * @{ - ******************************************************************************/ - -/** - * @brief - * Subtract two vectors of 16 bit floats. - * - * @details - * This function will perform the following operation: Z = A - B. - * All vectors must be of equal length. If all vector buffers are 4-byte - * aligned, the function will operate twice as fast using MVP parallel - * processing. - * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. - * - * @param[in] input_a First input vector, input A. - * @param[in] input_b Second input vector, input B. - * @param[out] output Output vector, output Z. - * @param[in] num_elements Length of all input and output vectors. - * - * @return - * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t - * errorcode is returned. - */ -sl_status_t sl_math_mvp_vector_sub_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements); - -/** @} (end addtogroup math_mvp_vector) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MATH_MVP_VECTOR_SUB_H +/***************************************************************************//** + * @file + * @brief MVP Math Vector Sub function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MATH_MVP_VECTOR_SUB_H +#define SL_MATH_MVP_VECTOR_SUB_H + +#include "sl_status.h" +#include "sl_math_types.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup math_mvp_vector + * @{ + ******************************************************************************/ + +/** + * @brief + * Subtract two vectors of 16 bit floats. + * + * @details + * This function will perform the following operation: Z = A - B. + * All vectors must be of equal length. If all vector buffers are 4-byte + * aligned, the function will operate twice as fast using MVP parallel + * processing. + * Maximum vector length is 1M (2^20), and 2M in the 4-byte aligned case. + * + * @param[in] input_a First input vector, input A. + * @param[in] input_b Second input vector, input B. + * @param[out] output Output vector, output Z. + * @param[in] num_elements Length of all input and output vectors. + * + * @return + * @ref SL_STATUS_OK on success. On failure, an appropriate sl_status_t + * errorcode is returned. + */ +sl_status_t sl_math_mvp_vector_sub_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements); + +/** @} (end addtogroup math_mvp_vector) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MATH_MVP_VECTOR_SUB_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c index 915d250..801bdcb 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c @@ -1,194 +1,194 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mul functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_math_mvp_complex_matrix_mult.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_complex_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output) -{ - if (!input_a || !input_b || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((input_a->num_cols == 0) - || (input_a->num_rows == 0) - || (input_b->num_cols == 0) - || (input_b->num_rows == 0) - || (output->num_cols == 0) - || (output->num_rows == 0)) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (input_a->num_cols != input_b->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (output->num_cols != input_b->num_cols || output->num_rows != input_a->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - - // We only process matrices that are word (4-byte) aligned. - if (!sli_mvp_util_is_pointer_word_aligned(input_a->data) - || !sli_mvp_util_is_pointer_word_aligned(input_b->data) - || !sli_mvp_util_is_pointer_word_aligned(output->data)) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((input_a->num_cols > SLI_MVP_MAX_COLUMN_LENGTH) - || (input_a->num_rows > SLI_MVP_MAX_ROW_LENGTH) - || (input_b->num_cols > SLI_MVP_MAX_COLUMN_LENGTH)) { - return SL_STATUS_INVALID_PARAMETER; - } - - const int a_rows = input_a->num_rows; - const int a_cols = input_a->num_cols; - const int b_rows = input_b->num_rows; - const int b_cols = input_b->num_cols; - const int z_rows = output->num_rows; - const int z_cols = output->num_cols; - const int matrix_x = SLI_MVP_ARRAY(0); - const int matrix_y = SLI_MVP_ARRAY(1); - const int matrix_z = SLI_MVP_ARRAY(2); - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - - sl_status_t status = SL_STATUS_OK; - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - // Configure array controllers - sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, a_rows, a_cols, &status); - sli_mvp_pb_config_matrix(p->p, matrix_y, (void*)input_b->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, b_rows, b_cols, &status); - sli_mvp_pb_config_matrix(p->p, matrix_z, (void*)output->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, z_rows, z_cols, &status); - - // This loop iterate over rows of matrix_x - sli_mvp_pb_begin_loop(p, a_rows, &status); { - // This loop iterate over columns of matrix_y - sli_mvp_pb_begin_loop(p, b_cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(CLEAR), - SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - 0, - &status); - // This loop calculates the dot product of a row of matrix_x and a column of matrix_y - sli_mvp_pb_begin_loop(p, a_cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACC), - SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R2) - | SLI_MVP_ALU_A(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) - | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, matrix_y, SLI_MVP_INCRDIM_COL); - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - 0, - 0, - SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); - sli_mvp_pb_postloop_incr_dim(p, matrix_z, SLI_MVP_INCRDIM_ROW); - } - sli_mvp_pb_end_loop(p); - - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM1CFG = ((b_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (b_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = ((b_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM1CFG = ((z_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (z_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM2CFG = ((z_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a->data; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b->data; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output->data; - - // Program loop controllers. - MVP->LOOP[1].RST = MVP->LOOP[2].RST = 0; - MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); - MVP->LOOP[1].CFG = ((b_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW) - | SLI_MVP_LOOP_INCRDIM(matrix_z, SLI_MVP_INCRDIM_ROW)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - MVP->LOOP[2].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | (SLI_MVP_LOOP_INCRDIM(matrix_y, SLI_MVP_INCRDIM_COL) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instructions. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = 0; - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP1BEGIN; - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R2) - | SLI_MVP_ALU_A(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) - | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - MVP->INSTR[2].CFG0 = 0; - MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL); - MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1END - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Mul functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_math_mvp_complex_matrix_mult.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_complex_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output) +{ + if (!input_a || !input_b || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((input_a->num_cols == 0) + || (input_a->num_rows == 0) + || (input_b->num_cols == 0) + || (input_b->num_rows == 0) + || (output->num_cols == 0) + || (output->num_rows == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (input_a->num_cols != input_b->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (output->num_cols != input_b->num_cols || output->num_rows != input_a->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + + // We only process matrices that are word (4-byte) aligned. + if (!sli_mvp_util_is_pointer_word_aligned(input_a->data) + || !sli_mvp_util_is_pointer_word_aligned(input_b->data) + || !sli_mvp_util_is_pointer_word_aligned(output->data)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((input_a->num_cols > SLI_MVP_MAX_COLUMN_LENGTH) + || (input_a->num_rows > SLI_MVP_MAX_ROW_LENGTH) + || (input_b->num_cols > SLI_MVP_MAX_COLUMN_LENGTH)) { + return SL_STATUS_INVALID_PARAMETER; + } + + const int a_rows = input_a->num_rows; + const int a_cols = input_a->num_cols; + const int b_rows = input_b->num_rows; + const int b_cols = input_b->num_cols; + const int z_rows = output->num_rows; + const int z_cols = output->num_cols; + const int matrix_x = SLI_MVP_ARRAY(0); + const int matrix_y = SLI_MVP_ARRAY(1); + const int matrix_z = SLI_MVP_ARRAY(2); + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + + sl_status_t status = SL_STATUS_OK; + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + // Configure array controllers + sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, a_rows, a_cols, &status); + sli_mvp_pb_config_matrix(p->p, matrix_y, (void*)input_b->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, b_rows, b_cols, &status); + sli_mvp_pb_config_matrix(p->p, matrix_z, (void*)output->data, SLI_MVP_DATATYPE_COMPLEX_BINARY16, z_rows, z_cols, &status); + + // This loop iterate over rows of matrix_x + sli_mvp_pb_begin_loop(p, a_rows, &status); { + // This loop iterate over columns of matrix_y + sli_mvp_pb_begin_loop(p, b_cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(CLEAR), + SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + 0, + &status); + // This loop calculates the dot product of a row of matrix_x and a column of matrix_y + sli_mvp_pb_begin_loop(p, a_cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACC), + SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R2) + | SLI_MVP_ALU_A(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) + | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, matrix_y, SLI_MVP_INCRDIM_COL); + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + 0, + 0, + SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); + sli_mvp_pb_postloop_incr_dim(p, matrix_z, SLI_MVP_INCRDIM_ROW); + } + sli_mvp_pb_end_loop(p); + + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM1CFG = ((b_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (b_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = ((b_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM1CFG = ((z_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (z_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM2CFG = ((z_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a->data; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b->data; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output->data; + + // Program loop controllers. + MVP->LOOP[1].RST = MVP->LOOP[2].RST = 0; + MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); + MVP->LOOP[1].CFG = ((b_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW) + | SLI_MVP_LOOP_INCRDIM(matrix_z, SLI_MVP_INCRDIM_ROW)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + MVP->LOOP[2].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | (SLI_MVP_LOOP_INCRDIM(matrix_y, SLI_MVP_INCRDIM_COL) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instructions. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = 0; + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP1BEGIN; + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R2) + | SLI_MVP_ALU_A(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) + | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + MVP->INSTR[2].CFG0 = 0; + MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL); + MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1END + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c index 56b7555..faf6aff 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c @@ -1,197 +1,197 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex conjugate functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_complex_vector_conjugate.h" -#include "sl_common.h" -#include - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_complex_vector_conjugate_f16(float16_t *input, - float16_t *output, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - if (!sli_mvp_util_is_pointer_word_aligned(input) - || !sli_mvp_util_is_pointer_word_aligned(output)) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder++; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder * 2], data_type, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder * 2], data_type, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); -} - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder * 2]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder * 2]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector complex conjugate functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_complex_vector_conjugate.h" +#include "sl_common.h" +#include + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_complex_vector_conjugate_f16(float16_t *input, + float16_t *output, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + if (!sli_mvp_util_is_pointer_word_aligned(input) + || !sli_mvp_util_is_pointer_word_aligned(output)) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder++; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder * 2], data_type, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder * 2], data_type, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); +} + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder * 2]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder * 2]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c index f4d4eec..6f47839 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c @@ -1,239 +1,239 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex dot product functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_complex_vector_dot_product.h" -#include "sl_common.h" -#include - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_complex_vector_dot_product_f16(float16_t *input_a, - float16_t *input_b, - size_t num_elements, - float16_t *output) -{ - sli_mvp_datatype_t data_type; - uint32_t len_matrix; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t rows, cols; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - if (!sli_mvp_util_is_pointer_word_aligned(input_a) - || !sli_mvp_util_is_pointer_word_aligned(input_b) - || !sli_mvp_util_is_pointer_word_aligned(output)) { - return SL_STATUS_INVALID_PARAMETER; - } - - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_matrix = (uint32_t)num_elements; - len_remainder = 0; - - if (len_matrix <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_matrix; - } else { - while (sli_mvp_util_factorize_number(len_matrix, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_matrix--; - len_remainder++; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - const int vector_x1 = SLI_MVP_ARRAY(3); - const int vector_y1 = SLI_MVP_ARRAY(4); - - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, 1, 1, &status); - - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void*)&input_a[ofs_remainder * 2], data_type, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_y1, (void*)&input_b[ofs_remainder * 2], data_type, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - } - - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_NOINCR), - &status); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - // Input - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - // Output - MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = - 0; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Clear the result register. - MVP->ALU[2].REGSTATE = 0; - - // Handle the matrix - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 1; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[3].DIM0CFG = MVP->ARRAY[4].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[3].DIM1CFG = MVP->ARRAY[4].DIM1CFG = - 0; - MVP->ARRAY[3].DIM2CFG = MVP->ARRAY[4].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; - MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder * 2]; - - // Program loop controller. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instruction. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the last instruction index - last_instruction_idx += 1; - } - - MVP->INSTR[last_instruction_idx].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[last_instruction_idx].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_NOINCR); - MVP->INSTR[last_instruction_idx].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector complex dot product functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_complex_vector_dot_product.h" +#include "sl_common.h" +#include + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_complex_vector_dot_product_f16(float16_t *input_a, + float16_t *input_b, + size_t num_elements, + float16_t *output) +{ + sli_mvp_datatype_t data_type; + uint32_t len_matrix; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t rows, cols; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + if (!sli_mvp_util_is_pointer_word_aligned(input_a) + || !sli_mvp_util_is_pointer_word_aligned(input_b) + || !sli_mvp_util_is_pointer_word_aligned(output)) { + return SL_STATUS_INVALID_PARAMETER; + } + + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_matrix = (uint32_t)num_elements; + len_remainder = 0; + + if (len_matrix <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_matrix; + } else { + while (sli_mvp_util_factorize_number(len_matrix, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_matrix--; + len_remainder++; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + const int vector_x1 = SLI_MVP_ARRAY(3); + const int vector_y1 = SLI_MVP_ARRAY(4); + + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, 1, 1, &status); + + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void*)&input_a[ofs_remainder * 2], data_type, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_y1, (void*)&input_b[ofs_remainder * 2], data_type, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + } + + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_NOINCR), + &status); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + // Input + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + // Output + MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = + 0; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Clear the result register. + MVP->ALU[2].REGSTATE = 0; + + // Handle the matrix + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 1; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[3].DIM0CFG = MVP->ARRAY[4].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[3].DIM1CFG = MVP->ARRAY[4].DIM1CFG = + 0; + MVP->ARRAY[3].DIM2CFG = MVP->ARRAY[4].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; + MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder * 2]; + + // Program loop controller. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instruction. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the last instruction index + last_instruction_idx += 1; + } + + MVP->INSTR[last_instruction_idx].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[last_instruction_idx].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_NOINCR); + MVP->INSTR[last_instruction_idx].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c index 988de1c..604938a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c @@ -1,215 +1,215 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector complex magnitude squared functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_complex_vector_magnitude_squared.h" -#include "sl_common.h" -#include - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_complex_vector_magnitude_squared_f16(const float16_t *input, - float16_t *output, - size_t num_elements) -{ - sli_mvp_datatype_t data_type_in, data_type_out; - uint32_t len_matrix; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - if (!sli_mvp_util_is_pointer_word_aligned(input)) { - return SL_STATUS_INVALID_PARAMETER; - } - - data_type_in = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - data_type_out = SLI_MVP_DATATYPE_BINARY16; - len_matrix = num_elements; - len_remainder = 0; - - if (len_matrix <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_matrix; - } else { - while (sli_mvp_util_factorize_number(len_matrix, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_matrix--; - len_remainder++; - } - } - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x2 = SLI_MVP_ARRAY(2); - const int vector_z2 = SLI_MVP_ARRAY(3); - - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type_in, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type_out, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(SQRMAGC2), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x2, (void *)&input[ofs_remainder * 2], data_type_in, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z2, (void *)&output[ofs_remainder], data_type_out, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(SQRMAGC2), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x2, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z2, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - // Matrix input - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[0].DIM0CFG = - data_type_in << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - // Matrix output - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - MVP->ARRAY[1].DIM0CFG = - data_type_out << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - - // Handle the first part of the input as a matrix. - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(SQRMAGC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder * 2]; - MVP->ARRAY[2].DIM0CFG = - data_type_in << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[4].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - MVP->ARRAY[3].DIM0CFG = - data_type_out << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - - // Program loop controller. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(SQRMAGC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Insert end-of-program at correct position - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector complex magnitude squared functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_complex_vector_magnitude_squared.h" +#include "sl_common.h" +#include + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_complex_vector_magnitude_squared_f16(const float16_t *input, + float16_t *output, + size_t num_elements) +{ + sli_mvp_datatype_t data_type_in, data_type_out; + uint32_t len_matrix; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + if (!sli_mvp_util_is_pointer_word_aligned(input)) { + return SL_STATUS_INVALID_PARAMETER; + } + + data_type_in = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + data_type_out = SLI_MVP_DATATYPE_BINARY16; + len_matrix = num_elements; + len_remainder = 0; + + if (len_matrix <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_matrix; + } else { + while (sli_mvp_util_factorize_number(len_matrix, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_matrix--; + len_remainder++; + } + } + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x2 = SLI_MVP_ARRAY(2); + const int vector_z2 = SLI_MVP_ARRAY(3); + + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type_in, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type_out, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(SQRMAGC2), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x2, (void *)&input[ofs_remainder * 2], data_type_in, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z2, (void *)&output[ofs_remainder], data_type_out, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(SQRMAGC2), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x2, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z2, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + // Matrix input + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[0].DIM0CFG = + data_type_in << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + // Matrix output + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + MVP->ARRAY[1].DIM0CFG = + data_type_out << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + + // Handle the first part of the input as a matrix. + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(SQRMAGC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder * 2]; + MVP->ARRAY[2].DIM0CFG = + data_type_in << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[4].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + MVP->ARRAY[3].DIM0CFG = + data_type_out << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + + // Program loop controller. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(SQRMAGC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Insert end-of-program at correct position + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c index 383881e..c0987ef 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c @@ -1,410 +1,410 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mul functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_complex_vector_mult_real_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t rows, cols; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - // Require input vectors that are word (4-byte) aligned. - if (!sli_mvp_util_is_pointer_word_aligned(input_a) - || !sli_mvp_util_is_pointer_word_aligned(input_b) - || !sli_mvp_util_is_pointer_word_aligned(output)) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - - if (num_elements <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder++; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - const int vector_x1 = SLI_MVP_ARRAY(3); - const int vector_y1 = SLI_MVP_ARRAY(4); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, SLI_MVP_DATATYPE_BINARY16, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, SLI_MVP_DATATYPE_COMPLEX_BINARY16, (rows + 1), cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input_a[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_y1, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - // input_a - MVP->ARRAY[0].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - // input_b - MVP->ARRAY[1].DIM0CFG = - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].ADDRCFG = - (sli_mvp_addr_reg_t)input_b; - // output - MVP->ARRAY[2].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = - ((rows) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction(s). - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - // input_a - MVP->ARRAY[3].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; - // input_b - MVP->ARRAY[4].DIM0CFG = - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[4].DIM1CFG = - 0; - MVP->ARRAY[4].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} - -sl_status_t sl_math_mvp_complex_vector_mult_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t rows, cols; - sl_status_t status; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - // Require input vectors that are word (4-byte) aligned. - if (!sli_mvp_util_is_pointer_word_aligned(input_a) - || !sli_mvp_util_is_pointer_word_aligned(input_b) - || !sli_mvp_util_is_pointer_word_aligned(output)) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - - // Factorize vector length into rows * cols. - if (num_elements <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder++; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x, (void *)&input_a[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_y, (void *)&input_b[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z, (void *)&output[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - } - status = sli_mvp_cmd_wait_for_completion(); -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction(s). - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { - return status; - } - - if (len_remainder > 0) { - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - 0; - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder * 2]; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder * 2]; - - // Program loop controllers. - MVP->LOOP[0].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instruction(s). - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - status = sli_mvp_cmd_wait_for_completion(); - } -#endif - - return status; -} +/***************************************************************************//** + * @file + * @brief MVP Math Mul functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_complex_vector_mult_real_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t rows, cols; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + // Require input vectors that are word (4-byte) aligned. + if (!sli_mvp_util_is_pointer_word_aligned(input_a) + || !sli_mvp_util_is_pointer_word_aligned(input_b) + || !sli_mvp_util_is_pointer_word_aligned(output)) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + + if (num_elements <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder++; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + const int vector_x1 = SLI_MVP_ARRAY(3); + const int vector_y1 = SLI_MVP_ARRAY(4); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, SLI_MVP_DATATYPE_BINARY16, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, SLI_MVP_DATATYPE_COMPLEX_BINARY16, (rows + 1), cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input_a[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_y1, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + // input_a + MVP->ARRAY[0].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + // input_b + MVP->ARRAY[1].DIM0CFG = + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].ADDRCFG = + (sli_mvp_addr_reg_t)input_b; + // output + MVP->ARRAY[2].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = + ((rows) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction(s). + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + // input_a + MVP->ARRAY[3].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; + // input_b + MVP->ARRAY[4].DIM0CFG = + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[4].DIM1CFG = + 0; + MVP->ARRAY[4].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} + +sl_status_t sl_math_mvp_complex_vector_mult_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t rows, cols; + sl_status_t status; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + // Require input vectors that are word (4-byte) aligned. + if (!sli_mvp_util_is_pointer_word_aligned(input_a) + || !sli_mvp_util_is_pointer_word_aligned(input_b) + || !sli_mvp_util_is_pointer_word_aligned(output)) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + + // Factorize vector length into rows * cols. + if (num_elements <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder++; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, SLI_MVP_DATATYPE_COMPLEX_BINARY16, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x, (void *)&input_a[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_y, (void *)&input_b[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z, (void *)&output[ofs_remainder * 2], SLI_MVP_DATATYPE_COMPLEX_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R2, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + } + status = sli_mvp_cmd_wait_for_completion(); +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction(s). + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { + return status; + } + + if (len_remainder > 0) { + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + SLI_MVP_DATATYPE_COMPLEX_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + 0; + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder * 2]; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder * 2]; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder * 2]; + + // Program loop controllers. + MVP->LOOP[0].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instruction(s). + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) | SLI_MVP_ALU_Y(SLI_MVP_R1) | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + status = sli_mvp_cmd_wait_for_completion(); + } +#endif + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c index 4e48687..6ae62a1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c @@ -1,186 +1,186 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Add function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_matrix_add.h" -#include "sl_math_mvp_vector_add.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_matrix_add_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output) -{ - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - - if (!input_a || !input_b || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (!((input_a->num_rows == input_b->num_rows) && (input_b->num_rows == output->num_rows)) - || !((input_a->num_cols == input_b->num_cols) && (input_b->num_cols == output->num_cols))) { - return SL_STATUS_INVALID_PARAMETER; - } - - rows = (uint32_t)input_a->num_rows; - cols = (uint32_t)input_a->num_cols; - data_type = SLI_MVP_DATATYPE_BINARY16; - - // Is parallel processing possible ? - if (sli_mvp_util_is_pointer_word_aligned(input_a->data) - && sli_mvp_util_is_pointer_word_aligned(input_b->data) - && sli_mvp_util_is_pointer_word_aligned(output->data) - && ((rows * cols) >= 2U)) { - if (((rows & 1U) == 0U) && ((cols & 1U) == 0U)) { - if (rows > cols) { - rows /= 2U; - } else { - cols /= 2U; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } else if ((rows & 1U) == 0U) { - rows /= 2U; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } else if ((cols & 1U) == 0U) { - cols /= 2U; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } - } - - // Size outside of MVP dimension size limit ? - if ((rows > SLI_MVP_MAX_ROW_LENGTH) || (cols > SLI_MVP_MAX_COLUMN_LENGTH)) { - return sl_math_mvp_vector_add_f16(input_a->data, - input_b->data, - output->data, - input_a->num_rows * input_a->num_cols); - } - - if (!input_a->data || !input_b->data || !output->data - || !input_a->num_rows || !input_a->num_cols) { - return SL_STATUS_INVALID_PARAMETER; - } - - return sli_math_mvp_matrix_add_f16(input_a->data, input_b->data, output->data, - rows, cols, data_type); -} - -sl_status_t sli_math_mvp_matrix_add_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_rows, - size_t num_cols, - sli_mvp_datatype_t data_type) -{ - uint32_t rows, cols; - - rows = (uint32_t)num_rows; - cols = (uint32_t)num_cols; - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - - sl_status_t status = SL_STATUS_OK; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(ADDC), - SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_A(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(ADDC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Add function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_matrix_add.h" +#include "sl_math_mvp_vector_add.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_matrix_add_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output) +{ + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + + if (!input_a || !input_b || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (!((input_a->num_rows == input_b->num_rows) && (input_b->num_rows == output->num_rows)) + || !((input_a->num_cols == input_b->num_cols) && (input_b->num_cols == output->num_cols))) { + return SL_STATUS_INVALID_PARAMETER; + } + + rows = (uint32_t)input_a->num_rows; + cols = (uint32_t)input_a->num_cols; + data_type = SLI_MVP_DATATYPE_BINARY16; + + // Is parallel processing possible ? + if (sli_mvp_util_is_pointer_word_aligned(input_a->data) + && sli_mvp_util_is_pointer_word_aligned(input_b->data) + && sli_mvp_util_is_pointer_word_aligned(output->data) + && ((rows * cols) >= 2U)) { + if (((rows & 1U) == 0U) && ((cols & 1U) == 0U)) { + if (rows > cols) { + rows /= 2U; + } else { + cols /= 2U; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } else if ((rows & 1U) == 0U) { + rows /= 2U; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } else if ((cols & 1U) == 0U) { + cols /= 2U; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } + } + + // Size outside of MVP dimension size limit ? + if ((rows > SLI_MVP_MAX_ROW_LENGTH) || (cols > SLI_MVP_MAX_COLUMN_LENGTH)) { + return sl_math_mvp_vector_add_f16(input_a->data, + input_b->data, + output->data, + input_a->num_rows * input_a->num_cols); + } + + if (!input_a->data || !input_b->data || !output->data + || !input_a->num_rows || !input_a->num_cols) { + return SL_STATUS_INVALID_PARAMETER; + } + + return sli_math_mvp_matrix_add_f16(input_a->data, input_b->data, output->data, + rows, cols, data_type); +} + +sl_status_t sli_math_mvp_matrix_add_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_rows, + size_t num_cols, + sli_mvp_datatype_t data_type) +{ + uint32_t rows, cols; + + rows = (uint32_t)num_rows; + cols = (uint32_t)num_cols; + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + + sl_status_t status = SL_STATUS_OK; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(ADDC), + SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_A(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(ADDC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c index 8cdcb2a..6eaaa8f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c @@ -1,208 +1,208 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mul functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, const sl_math_matrix_f16_t *input_b, sl_math_matrix_f16_t *output) -{ - if (!input_a || !input_b || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - if (input_a->num_cols != input_b->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - if (output->num_cols != input_b->num_cols || output->num_rows != input_a->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - uint32_t a_rows = input_a->num_rows; - uint32_t a_cols = input_a->num_cols; - uint32_t b_rows = input_b->num_rows; - uint32_t b_cols = input_b->num_cols; - uint32_t z_rows = output->num_rows; - uint32_t z_cols = output->num_cols; - sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; - bool parallel = false; - - // Check if all pointers are 4-byte aligned - if (sli_mvp_util_is_pointer_word_aligned(input_a->data) - && sli_mvp_util_is_pointer_word_aligned(input_b->data) - && sli_mvp_util_is_pointer_word_aligned(output->data)) { - // Check that the relevant dimensions are divisible by 2, only need to check input_b because we know output has the same number of columns. - if ((b_cols % 2 == 0)) { - // Enable parallel processing - parallel = true; - b_cols /= 2; - z_cols /= 2; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } - } - const int matrix_x = SLI_MVP_ARRAY(0); - const int matrix_y = SLI_MVP_ARRAY(1); - const int matrix_z = SLI_MVP_ARRAY(2); - - #if USE_MVP_PROGRAMBUILDER - - sl_status_t status; - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - // Configure the matrices - sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, SLI_MVP_DATATYPE_BINARY16, a_rows, a_cols, &status); - sli_mvp_pb_config_matrix(p->p, matrix_y, (void*)input_b->data, data_type, b_rows, b_cols, &status); - sli_mvp_pb_config_matrix(p->p, matrix_z, (void*)output->data, data_type, z_rows, z_cols, &status); - - // This loop moves to the next row of matrix_x - sli_mvp_pb_begin_loop(p, a_rows, &status); { - //This loop moves to the next column of matrix_y - sli_mvp_pb_begin_loop(p, b_cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(CLEAR), - SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - 0, - &status); - // This loop calculates the dot product of a row of matrix_x and a column of matrix_y - sli_mvp_pb_begin_loop(p, a_cols, &status); { - if (parallel) { - /** - * They key here is to scale each pair of values in matrix_y by a single value in matrix_x - * For two equal matrices X and Y with the values: - * 1 2 - * 3 4 - * The parallel computation will look like: - * Z_00 = (1)*1+(2)*3 - * Z_01 = (1)*2+(2)*4 - * Notice that the values marked in parentheses are essentially scale values. - * Scaling can be achieved by using complex MAC with X as a binary16 and Y as complex_binary16. - **/ - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACC), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), - 0, - &status); - } else { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), - 0, - &status); - } - } - sli_mvp_pb_end_loop(p); - - sli_mvp_pb_postloop_incr_dim(p, matrix_y, SLI_MVP_INCRDIM_COL); - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - 0, - 0, - SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL), - &status); - } - sli_mvp_pb_end_loop(p); - - sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); - sli_mvp_pb_postloop_incr_dim(p, matrix_z, SLI_MVP_INCRDIM_ROW); - } - sli_mvp_pb_end_loop(p); - - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - #else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (size_t)input_a->data; - - MVP->ARRAY[1].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[1].DIM1CFG = ((b_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (b_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = ((b_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].ADDRCFG = (size_t)input_b->data; - - MVP->ARRAY[2].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = ((z_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (z_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM2CFG = ((z_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (size_t)output->data; - - // Program loop controllers. - - MVP->LOOP[1].RST = 0; - MVP->LOOP[2].RST = 0; - - MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); - MVP->LOOP[1].CFG = ((b_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW) | SLI_MVP_LOOP_INCRDIM(matrix_z, SLI_MVP_INCRDIM_ROW)) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - MVP->LOOP[2].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | (SLI_MVP_LOOP_INCRDIM(matrix_y, SLI_MVP_INCRDIM_COL) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = 0; - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP1BEGIN; - - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW); - if (parallel) { - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - } else { - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - } - - MVP->INSTR[2].CFG0 = 0; - MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL); - MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1END - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - #endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Mul functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_matrix_mult_f16(const sl_math_matrix_f16_t *input_a, const sl_math_matrix_f16_t *input_b, sl_math_matrix_f16_t *output) +{ + if (!input_a || !input_b || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + if (input_a->num_cols != input_b->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + if (output->num_cols != input_b->num_cols || output->num_rows != input_a->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + uint32_t a_rows = input_a->num_rows; + uint32_t a_cols = input_a->num_cols; + uint32_t b_rows = input_b->num_rows; + uint32_t b_cols = input_b->num_cols; + uint32_t z_rows = output->num_rows; + uint32_t z_cols = output->num_cols; + sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; + bool parallel = false; + + // Check if all pointers are 4-byte aligned + if (sli_mvp_util_is_pointer_word_aligned(input_a->data) + && sli_mvp_util_is_pointer_word_aligned(input_b->data) + && sli_mvp_util_is_pointer_word_aligned(output->data)) { + // Check that the relevant dimensions are divisible by 2, only need to check input_b because we know output has the same number of columns. + if ((b_cols % 2 == 0)) { + // Enable parallel processing + parallel = true; + b_cols /= 2; + z_cols /= 2; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } + } + const int matrix_x = SLI_MVP_ARRAY(0); + const int matrix_y = SLI_MVP_ARRAY(1); + const int matrix_z = SLI_MVP_ARRAY(2); + + #if USE_MVP_PROGRAMBUILDER + + sl_status_t status; + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + // Configure the matrices + sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, SLI_MVP_DATATYPE_BINARY16, a_rows, a_cols, &status); + sli_mvp_pb_config_matrix(p->p, matrix_y, (void*)input_b->data, data_type, b_rows, b_cols, &status); + sli_mvp_pb_config_matrix(p->p, matrix_z, (void*)output->data, data_type, z_rows, z_cols, &status); + + // This loop moves to the next row of matrix_x + sli_mvp_pb_begin_loop(p, a_rows, &status); { + //This loop moves to the next column of matrix_y + sli_mvp_pb_begin_loop(p, b_cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(CLEAR), + SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + 0, + &status); + // This loop calculates the dot product of a row of matrix_x and a column of matrix_y + sli_mvp_pb_begin_loop(p, a_cols, &status); { + if (parallel) { + /** + * They key here is to scale each pair of values in matrix_y by a single value in matrix_x + * For two equal matrices X and Y with the values: + * 1 2 + * 3 4 + * The parallel computation will look like: + * Z_00 = (1)*1+(2)*3 + * Z_01 = (1)*2+(2)*4 + * Notice that the values marked in parentheses are essentially scale values. + * Scaling can be achieved by using complex MAC with X as a binary16 and Y as complex_binary16. + **/ + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACC), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), + 0, + &status); + } else { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW), + 0, + &status); + } + } + sli_mvp_pb_end_loop(p); + + sli_mvp_pb_postloop_incr_dim(p, matrix_y, SLI_MVP_INCRDIM_COL); + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + 0, + 0, + SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL), + &status); + } + sli_mvp_pb_end_loop(p); + + sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); + sli_mvp_pb_postloop_incr_dim(p, matrix_z, SLI_MVP_INCRDIM_ROW); + } + sli_mvp_pb_end_loop(p); + + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + #else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (size_t)input_a->data; + + MVP->ARRAY[1].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[1].DIM1CFG = ((b_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (b_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = ((b_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].ADDRCFG = (size_t)input_b->data; + + MVP->ARRAY[2].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = ((z_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (z_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM2CFG = ((z_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (size_t)output->data; + + // Program loop controllers. + + MVP->LOOP[1].RST = 0; + MVP->LOOP[2].RST = 0; + + MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); + MVP->LOOP[1].CFG = ((b_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW) | SLI_MVP_LOOP_INCRDIM(matrix_z, SLI_MVP_INCRDIM_ROW)) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + MVP->LOOP[2].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | (SLI_MVP_LOOP_INCRDIM(matrix_y, SLI_MVP_INCRDIM_COL) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = 0; + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP1BEGIN; + + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, matrix_y, SLI_MVP_INCRDIM_ROW); + if (parallel) { + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + } else { + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + } + + MVP->INSTR[2].CFG0 = 0; + MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, matrix_z, SLI_MVP_INCRDIM_COL); + MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1END + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + #endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c index d9a3e7b..afe1d1c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c @@ -1,42 +1,42 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mul functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -sl_status_t sl_math_mvp_matrix_scale_f16(const sl_math_matrix_f16_t *input, float16_t scale, sl_math_matrix_f16_t *output) -{ - if (input->num_cols != output->num_cols || input->num_rows != output->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - return sl_math_mvp_vector_scale_f16(input->data, scale, output->data, input->num_rows * input->num_cols); -} +/***************************************************************************//** + * @file + * @brief MVP Math Mul functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +sl_status_t sl_math_mvp_matrix_scale_f16(const sl_math_matrix_f16_t *input, float16_t scale, sl_math_matrix_f16_t *output) +{ + if (input->num_cols != output->num_cols || input->num_rows != output->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + return sl_math_mvp_vector_scale_f16(input->data, scale, output->data, input->num_rows * input->num_cols); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c index 86d1a77..e1b2e3d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c @@ -1,189 +1,189 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Sub function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_matrix_sub.h" -#include "sl_math_mvp_vector_sub.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_matrix_sub_f16(const sl_math_matrix_f16_t *input_a, - const sl_math_matrix_f16_t *input_b, - sl_math_matrix_f16_t *output) -{ - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - - if (!input_a || !input_b || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (!((input_a->num_rows == input_b->num_rows) && (input_b->num_rows == output->num_rows)) - || !((input_a->num_cols == input_b->num_cols) && (input_b->num_cols == output->num_cols))) { - return SL_STATUS_INVALID_PARAMETER; - } - - rows = (uint32_t)input_a->num_rows; - cols = (uint32_t)input_a->num_cols; - data_type = SLI_MVP_DATATYPE_BINARY16; - - // Is parallel processing possible ? - if (sli_mvp_util_is_pointer_word_aligned(input_a->data) - && sli_mvp_util_is_pointer_word_aligned(input_b->data) - && sli_mvp_util_is_pointer_word_aligned(output->data) - && ((rows * cols) >= 2U)) { - if (((rows & 1U) == 0U) && ((cols & 1U) == 0U)) { - if (rows > cols) { - rows /= 2U; - } else { - cols /= 2U; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } else if ((rows & 1U) == 0U) { - rows /= 2U; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } else if ((cols & 1U) == 0U) { - cols /= 2U; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - } - } - - // Size outside of MVP dimension size limit ? - if ((rows > SLI_MVP_MAX_ROW_LENGTH) || (cols > SLI_MVP_MAX_COLUMN_LENGTH)) { - return sl_math_mvp_vector_sub_f16(input_a->data, - input_b->data, - output->data, - input_a->num_rows * input_a->num_cols); - } - - if (!input_a->data || !input_b->data || !output->data - || !input_a->num_rows || !input_a->num_cols) { - return SL_STATUS_INVALID_PARAMETER; - } - - return sli_math_mvp_matrix_sub_f16(input_a->data, input_b->data, output->data, - rows, cols, data_type); -} - -sl_status_t sli_math_mvp_matrix_sub_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_rows, - size_t num_cols, - sli_mvp_datatype_t data_type) -{ - uint32_t rows, cols; - - rows = (uint32_t)num_rows; - cols = (uint32_t)num_cols; - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - - sl_status_t status = SL_STATUS_OK; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - // SUBC(X,_,A) => ADDC(X,_,-A) - SLI_MVP_OP(ADDC), - SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALUIN_A(SLI_MVP_R2, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALUIN_A(SLI_MVP_R2, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(ADDC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Sub function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_matrix_sub.h" +#include "sl_math_mvp_vector_sub.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_matrix_sub_f16(const sl_math_matrix_f16_t *input_a, + const sl_math_matrix_f16_t *input_b, + sl_math_matrix_f16_t *output) +{ + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + + if (!input_a || !input_b || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (!((input_a->num_rows == input_b->num_rows) && (input_b->num_rows == output->num_rows)) + || !((input_a->num_cols == input_b->num_cols) && (input_b->num_cols == output->num_cols))) { + return SL_STATUS_INVALID_PARAMETER; + } + + rows = (uint32_t)input_a->num_rows; + cols = (uint32_t)input_a->num_cols; + data_type = SLI_MVP_DATATYPE_BINARY16; + + // Is parallel processing possible ? + if (sli_mvp_util_is_pointer_word_aligned(input_a->data) + && sli_mvp_util_is_pointer_word_aligned(input_b->data) + && sli_mvp_util_is_pointer_word_aligned(output->data) + && ((rows * cols) >= 2U)) { + if (((rows & 1U) == 0U) && ((cols & 1U) == 0U)) { + if (rows > cols) { + rows /= 2U; + } else { + cols /= 2U; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } else if ((rows & 1U) == 0U) { + rows /= 2U; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } else if ((cols & 1U) == 0U) { + cols /= 2U; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + } + } + + // Size outside of MVP dimension size limit ? + if ((rows > SLI_MVP_MAX_ROW_LENGTH) || (cols > SLI_MVP_MAX_COLUMN_LENGTH)) { + return sl_math_mvp_vector_sub_f16(input_a->data, + input_b->data, + output->data, + input_a->num_rows * input_a->num_cols); + } + + if (!input_a->data || !input_b->data || !output->data + || !input_a->num_rows || !input_a->num_cols) { + return SL_STATUS_INVALID_PARAMETER; + } + + return sli_math_mvp_matrix_sub_f16(input_a->data, input_b->data, output->data, + rows, cols, data_type); +} + +sl_status_t sli_math_mvp_matrix_sub_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_rows, + size_t num_cols, + sli_mvp_datatype_t data_type) +{ + uint32_t rows, cols; + + rows = (uint32_t)num_rows; + cols = (uint32_t)num_cols; + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + + sl_status_t status = SL_STATUS_OK; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void*)input_a, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + // SUBC(X,_,A) => ADDC(X,_,-A) + SLI_MVP_OP(ADDC), + SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALUIN_A(SLI_MVP_R2, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALUIN_A(SLI_MVP_R2, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(ADDC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c index ec1239f..bcf786a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c @@ -1,165 +1,165 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Transpose functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_matrix_transpose.h" - -static sl_status_t matrix_transpose(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output, - sli_mvp_datatype_t data_type); - -sl_status_t sl_math_mvp_matrix_transpose_f16(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output) -{ - return matrix_transpose(input, output, SLI_MVP_DATATYPE_BINARY16); -} - -sl_status_t sl_math_mvp_complex_matrix_transpose_f16(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output) -{ - // We only process matrices that are word (4-byte) aligned. - if (!sli_mvp_util_is_pointer_word_aligned(input->data) - || !sli_mvp_util_is_pointer_word_aligned(output->data)) { - return SL_STATUS_INVALID_PARAMETER; - } - - return matrix_transpose(input, output, SLI_MVP_DATATYPE_COMPLEX_BINARY16); -} - -static sl_status_t matrix_transpose(const sl_math_matrix_f16_t *input, - sl_math_matrix_f16_t *output, - sli_mvp_datatype_t data_type) -{ - if (!input || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((input->num_cols == 0) - || (input->num_rows == 0) - || (output->num_cols == 0) - || (output->num_rows == 0)) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (input->num_rows != output->num_cols || input->num_cols != output->num_rows) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((input->num_rows > SLI_MVP_MAX_ROW_LENGTH) - || (input->num_cols > SLI_MVP_MAX_COLUMN_LENGTH)) { - return SL_STATUS_INVALID_PARAMETER; - } - -#if 0 - // This is the reference MVP program for the optimized setup below. - - sl_status_t status = SL_STATUS_OK; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, input->data, data_type, input->num_rows, input->num_cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, output->data, data_type, output->num_rows, output->num_cols, &status); - - sli_mvp_pb_begin_loop(p, input->num_rows, &status); { - sli_mvp_pb_begin_loop(p, input->num_cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_HEIGHT), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_WIDTH); - } - sli_mvp_pb_end_loop(p); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - - MVP->ARRAY[0].DIM1CFG = - (((uint32_t)input->num_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) - | ((uint32_t)input->num_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = - (((uint32_t)input->num_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) - | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (size_t)input->data; - MVP->ARRAY[1].DIM1CFG = - (((uint32_t)output->num_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) - | ((uint32_t)output->num_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = - (((uint32_t)output->num_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) - | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].ADDRCFG = (size_t)output->data; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = ((uint32_t)input->num_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = (((uint32_t)input->num_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Transpose functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_matrix_transpose.h" + +static sl_status_t matrix_transpose(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output, + sli_mvp_datatype_t data_type); + +sl_status_t sl_math_mvp_matrix_transpose_f16(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output) +{ + return matrix_transpose(input, output, SLI_MVP_DATATYPE_BINARY16); +} + +sl_status_t sl_math_mvp_complex_matrix_transpose_f16(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output) +{ + // We only process matrices that are word (4-byte) aligned. + if (!sli_mvp_util_is_pointer_word_aligned(input->data) + || !sli_mvp_util_is_pointer_word_aligned(output->data)) { + return SL_STATUS_INVALID_PARAMETER; + } + + return matrix_transpose(input, output, SLI_MVP_DATATYPE_COMPLEX_BINARY16); +} + +static sl_status_t matrix_transpose(const sl_math_matrix_f16_t *input, + sl_math_matrix_f16_t *output, + sli_mvp_datatype_t data_type) +{ + if (!input || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((input->num_cols == 0) + || (input->num_rows == 0) + || (output->num_cols == 0) + || (output->num_rows == 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (input->num_rows != output->num_cols || input->num_cols != output->num_rows) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((input->num_rows > SLI_MVP_MAX_ROW_LENGTH) + || (input->num_cols > SLI_MVP_MAX_COLUMN_LENGTH)) { + return SL_STATUS_INVALID_PARAMETER; + } + +#if 0 + // This is the reference MVP program for the optimized setup below. + + sl_status_t status = SL_STATUS_OK; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, input->data, data_type, input->num_rows, input->num_cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, output->data, data_type, output->num_rows, output->num_cols, &status); + + sli_mvp_pb_begin_loop(p, input->num_rows, &status); { + sli_mvp_pb_begin_loop(p, input->num_cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_HEIGHT), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_WIDTH); + } + sli_mvp_pb_end_loop(p); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + + MVP->ARRAY[0].DIM1CFG = + (((uint32_t)input->num_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) + | ((uint32_t)input->num_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = + (((uint32_t)input->num_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) + | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (size_t)input->data; + MVP->ARRAY[1].DIM1CFG = + (((uint32_t)output->num_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) + | ((uint32_t)output->num_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = + (((uint32_t)output->num_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) + | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].ADDRCFG = (size_t)output->data; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = ((uint32_t)input->num_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = (((uint32_t)input->num_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c index 4dab523..822918a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c @@ -1,178 +1,178 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Matrix Vector Mult functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_matrix_vector_mult_f16(const sl_math_matrix_f16_t *input_a, const float16_t *input_b, float16_t *output) -{ - // We could have used the normal matrix mult function, but it will not be able to parallelise when B is a vector (num_cols being 1 and not divisible by 2). - // This function is a different version of the matrix mult function, aimed at transposing B (since B is a vector the transpose is free), - // and then performing parallelisation of the inner loop gaining up to 2x speedup. - - if (!input_a || !input_b || !output) { - return SL_STATUS_INVALID_PARAMETER; - } - uint32_t a_rows = input_a->num_rows; - uint32_t a_cols = input_a->num_cols; - sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; - bool parallel = false; - - // Check if all pointers are 4-byte aligned - if (sli_mvp_util_is_pointer_word_aligned(input_a->data) - && sli_mvp_util_is_pointer_word_aligned(input_b) - && sli_mvp_util_is_pointer_word_aligned(output)) { - // Check that the relevant dimensions are divisible by 2, only need to check input_b because we know output has the same number of columns. - if ((a_cols % 2 == 0)) { - // Enable parallel processing - parallel = true; - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - a_cols /= 2; - } - } - - const int matrix_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - #if USE_MVP_PROGRAMBUILDER - - sl_status_t status; - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - // Configure the matrices - sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, data_type, a_rows, a_cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, 1, a_cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, SLI_MVP_DATATYPE_BINARY16, 1, a_rows, &status); - - // This loop moves to the next row of matrix_x - sli_mvp_pb_begin_loop(p, a_rows, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(CLEAR), - SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - 0, - &status); - // This loop calculates the dot product of a row of matrix_x and vector_y - sli_mvp_pb_begin_loop(p, a_cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_COL), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - if (parallel) { - sli_mvp_pb_compute(p, - SLI_MVP_OP(ADDR), - SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL), - &status); - } else { - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - 0, - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL), - &status); - } - - sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); - } - sli_mvp_pb_end_loop(p); - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - #else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (size_t)input_a->data; - - MVP->ARRAY[1].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[1].DIM1CFG = ((1 - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[1].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].ADDRCFG = (size_t)input_b; - - MVP->ARRAY[2].DIM0CFG = SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = ((1 - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_rows << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM2CFG = ((a_rows - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (size_t)output; - - // Program loop controllers. - - MVP->LOOP[1].RST = 0; - - MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); - MVP->LOOP[1].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW)) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = 0; - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN; - - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_COL); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - if (parallel) { - MVP->INSTR[2].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL); - MVP->INSTR[2].CFG2 = (SLI_MVP_OP(ADDR) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_ENDPROG; - } else { - MVP->INSTR[2].CFG0 = 0; - MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL); - MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_ENDPROG; - } - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - #endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Matrix Vector Mult functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_matrix_vector_mult_f16(const sl_math_matrix_f16_t *input_a, const float16_t *input_b, float16_t *output) +{ + // We could have used the normal matrix mult function, but it will not be able to parallelise when B is a vector (num_cols being 1 and not divisible by 2). + // This function is a different version of the matrix mult function, aimed at transposing B (since B is a vector the transpose is free), + // and then performing parallelisation of the inner loop gaining up to 2x speedup. + + if (!input_a || !input_b || !output) { + return SL_STATUS_INVALID_PARAMETER; + } + uint32_t a_rows = input_a->num_rows; + uint32_t a_cols = input_a->num_cols; + sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; + bool parallel = false; + + // Check if all pointers are 4-byte aligned + if (sli_mvp_util_is_pointer_word_aligned(input_a->data) + && sli_mvp_util_is_pointer_word_aligned(input_b) + && sli_mvp_util_is_pointer_word_aligned(output)) { + // Check that the relevant dimensions are divisible by 2, only need to check input_b because we know output has the same number of columns. + if ((a_cols % 2 == 0)) { + // Enable parallel processing + parallel = true; + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + a_cols /= 2; + } + } + + const int matrix_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + #if USE_MVP_PROGRAMBUILDER + + sl_status_t status; + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + // Configure the matrices + sli_mvp_pb_config_matrix(p->p, matrix_x, (void*)input_a->data, data_type, a_rows, a_cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void*)input_b, data_type, 1, a_cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void*)output, SLI_MVP_DATATYPE_BINARY16, 1, a_rows, &status); + + // This loop moves to the next row of matrix_x + sli_mvp_pb_begin_loop(p, a_rows, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(CLEAR), + SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + 0, + &status); + // This loop calculates the dot product of a row of matrix_x and vector_y + sli_mvp_pb_begin_loop(p, a_cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_COL), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + if (parallel) { + sli_mvp_pb_compute(p, + SLI_MVP_OP(ADDR), + SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL), + &status); + } else { + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + 0, + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL), + &status); + } + + sli_mvp_pb_postloop_incr_dim(p, matrix_x, SLI_MVP_INCRDIM_ROW); + } + sli_mvp_pb_end_loop(p); + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + #else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = ((a_rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (size_t)input_a->data; + + MVP->ARRAY[1].DIM0CFG = data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[1].DIM1CFG = ((1 - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[1].DIM2CFG = ((a_cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].ADDRCFG = (size_t)input_b; + + MVP->ARRAY[2].DIM0CFG = SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = ((1 - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (a_rows << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM2CFG = ((a_rows - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (size_t)output; + + // Program loop controllers. + + MVP->LOOP[1].RST = 0; + + MVP->LOOP[0].CFG = ((a_rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT); + MVP->LOOP[1].CFG = ((a_cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(matrix_x, SLI_MVP_INCRDIM_ROW)) << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = 0; + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLEAR) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN; + + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, matrix_x, SLI_MVP_INCRDIM_COL) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_COL); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + if (parallel) { + MVP->INSTR[2].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R3) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL); + MVP->INSTR[2].CFG2 = (SLI_MVP_OP(ADDR) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_ENDPROG; + } else { + MVP->INSTR[2].CFG0 = 0; + MVP->INSTR[2].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_COL); + MVP->INSTR[2].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_ENDPROG; + } + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + #endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_util.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_util.c index 455f816..e93e49f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_util.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_util.c @@ -1,82 +1,82 @@ -/***************************************************************************//** - * @file - * @brief MVP Math utility functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_math_mvp.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_STATUS_STRING_PRESENT) -#include "sl_status_string_config.h" -#endif - -void sl_math_mvp_clear_errors(void) -{ - sli_mvp_clear_error_flags(SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK); -} - -sl_status_t sl_math_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length) -{ - if (!error_code) { - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t flag; - uint32_t flags = sli_mvp_get_error_flags(); - - if (flags & (MVP_IF_ALUNAN | MVP_IF_STORECONVERTNAN)) { - *error_code = SL_STATUS_COMPUTE_MATH_NAN; - flag = MVP_IF_ALUNAN | MVP_IF_STORECONVERTNAN; - } else if (flags & MVP_IF_STORECONVERTINF) { - *error_code = SL_STATUS_COMPUTE_MATH_INFINITY; - flag = MVP_IF_STORECONVERTINF; - } else if (flags & (MVP_IF_ALUOF | MVP_IF_STORECONVERTOF)) { - *error_code = SL_STATUS_COMPUTE_MATH_OVERFLOW; - flag = MVP_IF_ALUOF | MVP_IF_STORECONVERTOF; - } else if (flags & (MVP_IF_ALUUF | MVP_IF_STORECONVERTUF)) { - *error_code = SL_STATUS_COMPUTE_MATH_UNDERFLOW; - flag = MVP_IF_ALUUF | MVP_IF_STORECONVERTUF; - - } else { - return SL_STATUS_NOT_FOUND; - } - - sli_mvp_clear_error_flags(flag); - -#if defined(SL_CATALOG_STATUS_STRING_PRESENT) && (SL_STATUS_STRING_ENABLE_COMPUTE == 1) - if (error_message != NULL) { - sl_status_get_string_n(*error_code, error_message, buffer_length); - } -#else - if ((error_message != NULL) && (buffer_length > 0)) { - error_message[0] = '\0'; - } -#endif - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief MVP Math utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_math_mvp.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_STATUS_STRING_PRESENT) +#include "sl_status_string_config.h" +#endif + +void sl_math_mvp_clear_errors(void) +{ + sli_mvp_clear_error_flags(SLI_MVP_NUMERIC_EXCEPTION_FLAG_MASK); +} + +sl_status_t sl_math_mvp_get_error(sl_status_t *error_code, char *error_message, uint32_t buffer_length) +{ + if (!error_code) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t flag; + uint32_t flags = sli_mvp_get_error_flags(); + + if (flags & (MVP_IF_ALUNAN | MVP_IF_STORECONVERTNAN)) { + *error_code = SL_STATUS_COMPUTE_MATH_NAN; + flag = MVP_IF_ALUNAN | MVP_IF_STORECONVERTNAN; + } else if (flags & MVP_IF_STORECONVERTINF) { + *error_code = SL_STATUS_COMPUTE_MATH_INFINITY; + flag = MVP_IF_STORECONVERTINF; + } else if (flags & (MVP_IF_ALUOF | MVP_IF_STORECONVERTOF)) { + *error_code = SL_STATUS_COMPUTE_MATH_OVERFLOW; + flag = MVP_IF_ALUOF | MVP_IF_STORECONVERTOF; + } else if (flags & (MVP_IF_ALUUF | MVP_IF_STORECONVERTUF)) { + *error_code = SL_STATUS_COMPUTE_MATH_UNDERFLOW; + flag = MVP_IF_ALUUF | MVP_IF_STORECONVERTUF; + + } else { + return SL_STATUS_NOT_FOUND; + } + + sli_mvp_clear_error_flags(flag); + +#if defined(SL_CATALOG_STATUS_STRING_PRESENT) && (SL_STATUS_STRING_ENABLE_COMPUTE == 1) + if (error_message != NULL) { + sl_status_get_string_n(*error_code, error_message, buffer_length); + } +#else + if ((error_message != NULL) && (buffer_length > 0)) { + error_message[0] = '\0'; + } +#endif + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c index 9c404c7..200de64 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c @@ -1,238 +1,238 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_abs.h" -#include "sl_common.h" -#include - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_abs_f16(float16_t *input, - float16_t *output, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - data_type = SLI_MVP_DATATYPE_BINARY16; - - if (sli_mvp_util_is_pointer_word_aligned(input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (num_elements >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - sli_mvp_pb_compute(p, - SLI_MVP_OP(MAXAC2), - SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - sli_mvp_pb_compute(p, - SLI_MVP_OP(MAXAC2), - SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instructions. - MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP1BEGIN; - - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MAXAC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 1; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[2].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[2].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[2].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN; - - MVP->INSTR[3].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[3].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[3].CFG2 = (SLI_MVP_OP(MAXAC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 2; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Vector functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_abs.h" +#include "sl_common.h" +#include + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_abs_f16(float16_t *input, + float16_t *output, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + data_type = SLI_MVP_DATATYPE_BINARY16; + + if (sli_mvp_util_is_pointer_word_aligned(input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (num_elements >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + sli_mvp_pb_compute(p, + SLI_MVP_OP(MAXAC2), + SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + sli_mvp_pb_compute(p, + SLI_MVP_OP(MAXAC2), + SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instructions. + MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP1BEGIN; + + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MAXAC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 1; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[2].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[2].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[2].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN; + + MVP->INSTR[3].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[3].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[3].CFG2 = (SLI_MVP_OP(MAXAC2) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 2; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c index 97b0393..9ea7779 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Add function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_add.h" -#include "sl_math_mvp_matrix_add.h" - -#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 480 - -sl_status_t sl_math_mvp_vector_add_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - bool use_parallel; - uint32_t len_parallel; - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - sl_status_t status; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_parallel = 1U; - len_remainder = 0U; - data_type = SLI_MVP_DATATYPE_BINARY16; - - // Check if MVP parallel processing is possible. - use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) - && sli_mvp_util_is_pointer_word_aligned(input_b) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2) - && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); - - if (use_parallel) { - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_parallel = 2U; - if (len_vector & 1U) { - len_remainder++; - } - len_vector /= 2U; - } - - // Factorize vector into rows * cols. - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1U; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - if ((status = sli_math_mvp_matrix_add_f16(input_a, input_b, output, rows, cols, data_type)) != SL_STATUS_OK) { - return status; - } - - if (len_remainder) { - ofs_remainder = num_elements - len_remainder; - status = sli_math_mvp_matrix_add_f16(&input_a[ofs_remainder], &input_b[ofs_remainder], &output[ofs_remainder], 1, len_remainder, SLI_MVP_DATATYPE_BINARY16); - } - - return status; -} - -sl_status_t sl_math_mvp_vector_add_i8(const int8_t *input_a, const int8_t *input_b, int8_t *output, size_t num_elements) -{ - sli_mvp_program_t *program = sli_mvp_get_program_area_single(); - - // Configure 3 Arrays: Array0 = input_a Array1 = input_b Array2 = output - sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(0), (void *)input_a, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); - sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(1), (void *)input_b, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); - sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(2), output, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); - - // Instruction 0 - // LOAD(Array0,R1) - // LOAD(Array1,R2) - // R3 = ADDC(R1,_,R2) - // STORE(Array2, R3) - sli_mvp_prog_set_instr(program, - SLI_MVP_INSTR(0), - SLI_MVP_OP(ADDC), - SLI_MVP_ALU_X(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL) - | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), - SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_COL), - SLI_MVP_ENDPROG); - - // Loop 0 is the outer loop, counting down columns - sli_mvp_prog_set_loop(program, - SLI_MVP_LOOP(0), - (unsigned short)num_elements, // iterate (once for each row) - SLI_MVP_INSTR(0), // starts at Instruction 0 - SLI_MVP_INSTR(0), // ends at Instruction 0 - SLI_MVP_NOINCR, // No dimension increments - SLI_MVP_NORST); // No dimension resets - - - return sli_mvp_prog_execute(program, true); -} +/***************************************************************************//** + * @file + * @brief MVP Math Vector Add function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_add.h" +#include "sl_math_mvp_matrix_add.h" + +#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 480 + +sl_status_t sl_math_mvp_vector_add_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + bool use_parallel; + uint32_t len_parallel; + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + sl_status_t status; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_parallel = 1U; + len_remainder = 0U; + data_type = SLI_MVP_DATATYPE_BINARY16; + + // Check if MVP parallel processing is possible. + use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) + && sli_mvp_util_is_pointer_word_aligned(input_b) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2) + && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); + + if (use_parallel) { + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_parallel = 2U; + if (len_vector & 1U) { + len_remainder++; + } + len_vector /= 2U; + } + + // Factorize vector into rows * cols. + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1U; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + if ((status = sli_math_mvp_matrix_add_f16(input_a, input_b, output, rows, cols, data_type)) != SL_STATUS_OK) { + return status; + } + + if (len_remainder) { + ofs_remainder = num_elements - len_remainder; + status = sli_math_mvp_matrix_add_f16(&input_a[ofs_remainder], &input_b[ofs_remainder], &output[ofs_remainder], 1, len_remainder, SLI_MVP_DATATYPE_BINARY16); + } + + return status; +} + +sl_status_t sl_math_mvp_vector_add_i8(const int8_t *input_a, const int8_t *input_b, int8_t *output, size_t num_elements) +{ + sli_mvp_program_t *program = sli_mvp_get_program_area_single(); + + // Configure 3 Arrays: Array0 = input_a Array1 = input_b Array2 = output + sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(0), (void *)input_a, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); + sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(1), (void *)input_b, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); + sli_mvp_prog_set_vector(program, SLI_MVP_ARRAY(2), output, SLI_MVP_DATATYPE_INT8, (unsigned short)num_elements); + + // Instruction 0 + // LOAD(Array0,R1) + // LOAD(Array1,R2) + // R3 = ADDC(R1,_,R2) + // STORE(Array2, R3) + sli_mvp_prog_set_instr(program, + SLI_MVP_INSTR(0), + SLI_MVP_OP(ADDC), + SLI_MVP_ALU_X(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL) + | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), + SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_COL), + SLI_MVP_ENDPROG); + + // Loop 0 is the outer loop, counting down columns + sli_mvp_prog_set_loop(program, + SLI_MVP_LOOP(0), + (unsigned short)num_elements, // iterate (once for each row) + SLI_MVP_INSTR(0), // starts at Instruction 0 + SLI_MVP_INSTR(0), // ends at Instruction 0 + SLI_MVP_NOINCR, // No dimension increments + SLI_MVP_NORST); // No dimension resets + + + return sli_mvp_prog_execute(program, true); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c index adce26c..8b24bce 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c @@ -1,166 +1,166 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Clamp functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_clamp.h" -#include "sl_common.h" - -static void sli_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max); - -sl_status_t sl_math_mvp_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max) -{ - sl_status_t status; - size_t remaining = num_elements; - const size_t threshold = 160; // non-mvp algorithm is faster bellow this threshold - sli_mvp_program_t *prog = sli_mvp_get_program_area_single(); - - if ((min == -128) && (max == 127)) { - return SL_STATUS_OK; // No need to process - } - - // Small datasets are faster to handle by cpu due to overhead of hw accelerator - if (num_elements <= threshold) { - sli_clamp_i8(data, remaining, min, max); - return SL_STATUS_OK; - } - - // Arrays: - // ------- - // A0 - input (data) - // A1 - output (data) - // - // Registers: - // ---------- - // R0 - min value - // R1 - max value - // R2 - data_i0 - // R3 - data_i1 - // - // All datatypes used is int8_t complex so all loads/stores and operations - // will operate on 2 int8_t elements at a time. The loop of the algorithm - // will write 4 elements on each iteration. - // - // Algorithm: - // ---------- - // R0 = min - // R1 = max - // R2 = Load(A0), A0.Dim0++ - // Loop0: cnt=n/4 { - // R3 = Load(A0), A0.Dim0++ - // R2 = CLIP2A(R0,R1,R2) - // Store(A1,R2), A1.Dim0++ - // R2 = Load(A0), A0.Dim0++ - // R3 = CLIP2A(R0,R1,R3) - // Store(A1,R3), A1.Dim0++ - - sli_mvp_prog_set_reg_s8c(prog, SLI_MVP_R0, min, min); - sli_mvp_prog_set_reg_s8c(prog, SLI_MVP_R1, max, max); - - // R2 = Load(A0), A0.Dim0++ - sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(0), - SLI_MVP_OP(NOOP), - 0, - SLI_MVP_LOAD(0, SLI_MVP_R2, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), - 0, - 0); - - // R3 = Load(A0), A0.Dim0++ - // R2 = CLIP2A(R0,R1,R2) - // Store(A1,R2), A1.Dim0++ - sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(1), - SLI_MVP_OP(CLIP2A), - SLI_MVP_ALU_X(SLI_MVP_R0) // X (R0) - Min value - | SLI_MVP_ALU_Y(SLI_MVP_R1) // Y (R1) - Max value - | SLI_MVP_ALU_A(SLI_MVP_R2) // A (R2) - input - | SLI_MVP_ALU_Z(SLI_MVP_R2), // Z (R2) - result - SLI_MVP_LOAD(0, SLI_MVP_R3, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), - SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), - 0); - - // R2 = Load(A0), A0.Dim0++ - // R3 = CLIP2A(R0,R1,R3) - // Store(A1,R3), A1.Dim0++ - sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(2), - SLI_MVP_OP(CLIP2A), - SLI_MVP_ALU_X(SLI_MVP_R0) // X (R0) - Min value - | SLI_MVP_ALU_Y(SLI_MVP_R1) // Y (R1) - Max value - | SLI_MVP_ALU_A(SLI_MVP_R3) // A (R2) - input - | SLI_MVP_ALU_Z(SLI_MVP_R3), // Z (R2) - result - SLI_MVP_LOAD(0, SLI_MVP_R2, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), - SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), - SLI_MVP_ENDPROG); - - while (remaining >= threshold) { - // We can process a maximum of 2048 elements in each mvp program. - size_t max_elements = SL_MIN(2048u, remaining); - size_t batch_size = max_elements / 4; // each loop will process 4 elements - size_t num_elements = batch_size * 4; - size_t array_size = num_elements / 2; - - // Configure input/output arrays - sli_mvp_prog_set_vector(prog, SLI_MVP_ARRAY(0), data, SLI_MVP_DATATYPE_COMPLEX_INT8, array_size); - sli_mvp_prog_set_vector(prog, SLI_MVP_ARRAY(1), data, SLI_MVP_DATATYPE_COMPLEX_INT8, array_size); - - // Loop 0 is iterating over the batch size, handling 4 elements at a time - sli_mvp_prog_set_loop(prog, SLI_MVP_LOOP(0), - batch_size, - SLI_MVP_INSTR(1), - SLI_MVP_INSTR(2), - SLI_MVP_NOINCR, - SLI_MVP_NORST); - - if ((status = sli_mvp_prog_execute(prog, true)) != SL_STATUS_OK) { - return status; - } - - data += num_elements; - remaining -= num_elements; - } - - // Handle the remaining elements in software - if (remaining > 0) { - sli_clamp_i8(data, remaining, min, max); - } - - return SL_STATUS_OK; -} - -static void sli_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max) -{ - for (size_t i = 0; i < num_elements; i++) { - int8_t v = data[i]; - if (v < min) { - data[i] = min; - } else if (v > max) { - data[i] = max; - } - } -} +/***************************************************************************//** + * @file + * @brief MVP Math Vector Clamp functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_clamp.h" +#include "sl_common.h" + +static void sli_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max); + +sl_status_t sl_math_mvp_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max) +{ + sl_status_t status; + size_t remaining = num_elements; + const size_t threshold = 160; // non-mvp algorithm is faster bellow this threshold + sli_mvp_program_t *prog = sli_mvp_get_program_area_single(); + + if ((min == -128) && (max == 127)) { + return SL_STATUS_OK; // No need to process + } + + // Small datasets are faster to handle by cpu due to overhead of hw accelerator + if (num_elements <= threshold) { + sli_clamp_i8(data, remaining, min, max); + return SL_STATUS_OK; + } + + // Arrays: + // ------- + // A0 - input (data) + // A1 - output (data) + // + // Registers: + // ---------- + // R0 - min value + // R1 - max value + // R2 - data_i0 + // R3 - data_i1 + // + // All datatypes used is int8_t complex so all loads/stores and operations + // will operate on 2 int8_t elements at a time. The loop of the algorithm + // will write 4 elements on each iteration. + // + // Algorithm: + // ---------- + // R0 = min + // R1 = max + // R2 = Load(A0), A0.Dim0++ + // Loop0: cnt=n/4 { + // R3 = Load(A0), A0.Dim0++ + // R2 = CLIP2A(R0,R1,R2) + // Store(A1,R2), A1.Dim0++ + // R2 = Load(A0), A0.Dim0++ + // R3 = CLIP2A(R0,R1,R3) + // Store(A1,R3), A1.Dim0++ + + sli_mvp_prog_set_reg_s8c(prog, SLI_MVP_R0, min, min); + sli_mvp_prog_set_reg_s8c(prog, SLI_MVP_R1, max, max); + + // R2 = Load(A0), A0.Dim0++ + sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(0), + SLI_MVP_OP(NOOP), + 0, + SLI_MVP_LOAD(0, SLI_MVP_R2, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), + 0, + 0); + + // R3 = Load(A0), A0.Dim0++ + // R2 = CLIP2A(R0,R1,R2) + // Store(A1,R2), A1.Dim0++ + sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(1), + SLI_MVP_OP(CLIP2A), + SLI_MVP_ALU_X(SLI_MVP_R0) // X (R0) - Min value + | SLI_MVP_ALU_Y(SLI_MVP_R1) // Y (R1) - Max value + | SLI_MVP_ALU_A(SLI_MVP_R2) // A (R2) - input + | SLI_MVP_ALU_Z(SLI_MVP_R2), // Z (R2) - result + SLI_MVP_LOAD(0, SLI_MVP_R3, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), + SLI_MVP_STORE(SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), + 0); + + // R2 = Load(A0), A0.Dim0++ + // R3 = CLIP2A(R0,R1,R3) + // Store(A1,R3), A1.Dim0++ + sli_mvp_prog_set_instr(prog, SLI_MVP_INSTR(2), + SLI_MVP_OP(CLIP2A), + SLI_MVP_ALU_X(SLI_MVP_R0) // X (R0) - Min value + | SLI_MVP_ALU_Y(SLI_MVP_R1) // Y (R1) - Max value + | SLI_MVP_ALU_A(SLI_MVP_R3) // A (R2) - input + | SLI_MVP_ALU_Z(SLI_MVP_R3), // Z (R2) - result + SLI_MVP_LOAD(0, SLI_MVP_R2, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_COL), + SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_COL), + SLI_MVP_ENDPROG); + + while (remaining >= threshold) { + // We can process a maximum of 2048 elements in each mvp program. + size_t max_elements = SL_MIN(2048u, remaining); + size_t batch_size = max_elements / 4; // each loop will process 4 elements + size_t num_elements = batch_size * 4; + size_t array_size = num_elements / 2; + + // Configure input/output arrays + sli_mvp_prog_set_vector(prog, SLI_MVP_ARRAY(0), data, SLI_MVP_DATATYPE_COMPLEX_INT8, array_size); + sli_mvp_prog_set_vector(prog, SLI_MVP_ARRAY(1), data, SLI_MVP_DATATYPE_COMPLEX_INT8, array_size); + + // Loop 0 is iterating over the batch size, handling 4 elements at a time + sli_mvp_prog_set_loop(prog, SLI_MVP_LOOP(0), + batch_size, + SLI_MVP_INSTR(1), + SLI_MVP_INSTR(2), + SLI_MVP_NOINCR, + SLI_MVP_NORST); + + if ((status = sli_mvp_prog_execute(prog, true)) != SL_STATUS_OK) { + return status; + } + + data += num_elements; + remaining -= num_elements; + } + + // Handle the remaining elements in software + if (remaining > 0) { + sli_clamp_i8(data, remaining, min, max); + } + + return SL_STATUS_OK; +} + +static void sli_clamp_i8(int8_t *data, size_t num_elements, int8_t min, int8_t max) +{ + for (size_t i = 0; i < num_elements; i++) { + int8_t v = data[i]; + if (v < min) { + data[i] = min; + } else if (v > max) { + data[i] = max; + } + } +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c index a2b0022..7dd9f45 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c @@ -1,229 +1,229 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector clip functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_clip.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_clip_f16(const float16_t *input, - float16_t *output, - float16_t low, - float16_t high, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - - data_type = SLI_MVP_DATATYPE_BINARY16; - if (sli_mvp_util_is_pointer_word_aligned(input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, low, low); - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R3, high, high); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(CLIP2A), - SLI_MVP_ALU_A(SLI_MVP_R1) - | SLI_MVP_ALU_X(SLI_MVP_R2) - | SLI_MVP_ALU_Y(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R4), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R4, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(CLIP2A), - SLI_MVP_ALU_A(SLI_MVP_R1) - | SLI_MVP_ALU_X(SLI_MVP_R2) - | SLI_MVP_ALU_Y(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R4), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R4, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program the registers - sli_mvp_alu_reg_t r; - r.reg.value.real = low; - r.reg.value.imag = low; - MVP->ALU[2].REGSTATE = r.REGSTATE; - r.reg.value.real = high; - r.reg.value.imag = high; - MVP->ALU[3].REGSTATE = r.REGSTATE; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1) - | SLI_MVP_ALU_X(SLI_MVP_R2) - | SLI_MVP_ALU_Y(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R4); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R4, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLIP2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize len_parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1) - | SLI_MVP_ALU_X(SLI_MVP_R2) - | SLI_MVP_ALU_Y(SLI_MVP_R3) - | SLI_MVP_ALU_Z(SLI_MVP_R4); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R4, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(CLIP2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector clip functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_clip.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_clip_f16(const float16_t *input, + float16_t *output, + float16_t low, + float16_t high, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + + data_type = SLI_MVP_DATATYPE_BINARY16; + if (sli_mvp_util_is_pointer_word_aligned(input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, low, low); + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R3, high, high); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(CLIP2A), + SLI_MVP_ALU_A(SLI_MVP_R1) + | SLI_MVP_ALU_X(SLI_MVP_R2) + | SLI_MVP_ALU_Y(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R4), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R4, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(CLIP2A), + SLI_MVP_ALU_A(SLI_MVP_R1) + | SLI_MVP_ALU_X(SLI_MVP_R2) + | SLI_MVP_ALU_Y(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R4), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R4, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program the registers + sli_mvp_alu_reg_t r; + r.reg.value.real = low; + r.reg.value.imag = low; + MVP->ALU[2].REGSTATE = r.REGSTATE; + r.reg.value.real = high; + r.reg.value.imag = high; + MVP->ALU[3].REGSTATE = r.REGSTATE; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1) + | SLI_MVP_ALU_X(SLI_MVP_R2) + | SLI_MVP_ALU_Y(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R4); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R4, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(CLIP2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize len_parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1) + | SLI_MVP_ALU_X(SLI_MVP_R2) + | SLI_MVP_ALU_Y(SLI_MVP_R3) + | SLI_MVP_ALU_Z(SLI_MVP_R4); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R4, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(CLIP2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c index d224836..2a55f56 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c @@ -1,203 +1,203 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector copy functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_copy.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_copy_f16(const float16_t *input, - float16_t *output, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - - data_type = SLI_MVP_DATATYPE_BINARY16; - if (sli_mvp_util_is_pointer_word_aligned(input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), // COPY: Z = A - SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), // COPY: Z = A - SLI_MVP_ALU_A(SLI_MVP_R0) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector copy functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_copy.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_copy_f16(const float16_t *input, + float16_t *output, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + + data_type = SLI_MVP_DATATYPE_BINARY16; + if (sli_mvp_util_is_pointer_word_aligned(input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), // COPY: Z = A + SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), // COPY: Z = A + SLI_MVP_ALU_A(SLI_MVP_R0) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R0) | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c index be67c65..4d181b3 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c @@ -1,264 +1,264 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector fill functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_dot_product.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -// The local buffer is required when complex type is used. -// It must be large enough to hold two float16_t after alignment if complex -// type is used. -// This is because the output pointer points to a single float16_t. -static float16_t temporary_buffer[3]; - -sl_status_t sl_math_mvp_vector_dot_product_f16(const float16_t *input_a, - const float16_t *input_b, - size_t num_elements, - float16_t *output) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - bool use_complex; - float16_t *temporary_output; - sl_status_t status = SL_STATUS_OK; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_parallel = 1; - len_remainder = 0; - data_type = SLI_MVP_DATATYPE_BINARY16; - temporary_output = output; - - use_complex = sli_mvp_util_is_pointer_word_aligned(input_a) - && sli_mvp_util_is_pointer_word_aligned(input_b) - && (num_elements >= 2U); - - if (use_complex) { - len_parallel = 2U; - if (len_vector & 1U) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - temporary_output = (float16_t *)(((size_t)temporary_buffer + 3) & ~3); - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - const int vector_x1 = SLI_MVP_ARRAY(3); - const int vector_y1 = SLI_MVP_ARRAY(4); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, temporary_output, data_type, 1, 1, &status); - - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACR2A), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input_a[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_y1, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MACR2A), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), - 0, - &status); - } - sli_mvp_pb_end_loop(p); - } - - sli_mvp_pb_compute(p, - SLI_MVP_OP(ADDR), - SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - 0, - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_NOINCR), - &status); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = - (0 << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) - | (1 << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[2].DIM2CFG = - (0 << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) - | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)temporary_output; - - // Clear the result register. - MVP->ALU[2].REGSTATE = 0; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 1; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[3].DIM0CFG = MVP->ARRAY[4].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[3].DIM1CFG = MVP->ARRAY[4].DIM1CFG = - 0; - MVP->ARRAY[3].DIM2CFG = MVP->ARRAY[4].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder]; - MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R2); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the last instruction index - last_instruction_idx += 1; - } - - // And finally, store the result. - // Program instruction. - MVP->INSTR[last_instruction_idx].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[last_instruction_idx].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_NOINCR); - MVP->INSTR[last_instruction_idx].CFG2 = (SLI_MVP_OP(ADDR) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - status = sli_mvp_cmd_wait_for_completion(); - - if (use_complex) { - output[0] = temporary_output[0]; - } - - return status; -} +/***************************************************************************//** + * @file + * @brief MVP Math vector fill functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_dot_product.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +// The local buffer is required when complex type is used. +// It must be large enough to hold two float16_t after alignment if complex +// type is used. +// This is because the output pointer points to a single float16_t. +static float16_t temporary_buffer[3]; + +sl_status_t sl_math_mvp_vector_dot_product_f16(const float16_t *input_a, + const float16_t *input_b, + size_t num_elements, + float16_t *output) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + bool use_complex; + float16_t *temporary_output; + sl_status_t status = SL_STATUS_OK; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_parallel = 1; + len_remainder = 0; + data_type = SLI_MVP_DATATYPE_BINARY16; + temporary_output = output; + + use_complex = sli_mvp_util_is_pointer_word_aligned(input_a) + && sli_mvp_util_is_pointer_word_aligned(input_b) + && (num_elements >= 2U); + + if (use_complex) { + len_parallel = 2U; + if (len_vector & 1U) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + temporary_output = (float16_t *)(((size_t)temporary_buffer + 3) & ~3); + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + const int vector_x1 = SLI_MVP_ARRAY(3); + const int vector_y1 = SLI_MVP_ARRAY(4); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, temporary_output, data_type, 1, 1, &status); + + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACR2A), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input_a[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_y1, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MACR2A), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, vector_y1, SLI_MVP_INCRDIM_WIDTH), + 0, + &status); + } + sli_mvp_pb_end_loop(p); + } + + sli_mvp_pb_compute(p, + SLI_MVP_OP(ADDR), + SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + 0, + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_NOINCR), + &status); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = + (0 << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) + | (1 << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[2].DIM2CFG = + (0 << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) + | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)temporary_output; + + // Clear the result register. + MVP->ALU[2].REGSTATE = 0; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 1; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[3].DIM0CFG = MVP->ARRAY[4].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[3].DIM1CFG = MVP->ARRAY[4].DIM1CFG = + 0; + MVP->ARRAY[3].DIM2CFG = MVP->ARRAY[4].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder]; + MVP->ARRAY[4].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R2); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R1, SLI_MVP_ARRAY(4), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MACR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the last instruction index + last_instruction_idx += 1; + } + + // And finally, store the result. + // Program instruction. + MVP->INSTR[last_instruction_idx].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[last_instruction_idx].CFG1 = SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_NOINCR); + MVP->INSTR[last_instruction_idx].CFG2 = (SLI_MVP_OP(ADDR) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + status = sli_mvp_cmd_wait_for_completion(); + + if (use_complex) { + output[0] = temporary_output[0]; + } + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c index 9e45ec3..d6a8286 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c @@ -1,198 +1,198 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector fill functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_fill.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_fill_f16(float16_t *output, - const float16_t value, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - - if (!output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - data_type = SLI_MVP_DATATYPE_BINARY16; - - if (sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status = SL_STATUS_OK; - const int vector_z = SLI_MVP_ARRAY(0); - const int vector_z1 = SLI_MVP_ARRAY(1); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); - - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R1, value, value); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - SLI_MVP_ALU_Z(SLI_MVP_R1), - 0, - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(NOOP), - SLI_MVP_ALU_Z(SLI_MVP_R1), - 0, - SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)output; - - sli_mvp_alu_reg_t r; - r.reg.value.real = value; - r.reg.value.imag = value; - MVP->ALU[1].REGSTATE = r.REGSTATE; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[1].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[1].DIM1CFG = - 0; - MVP->ARRAY[1].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1); - MVP->INSTR[1].CFG1 = SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector fill functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_fill.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_fill_f16(float16_t *output, + const float16_t value, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + + if (!output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + data_type = SLI_MVP_DATATYPE_BINARY16; + + if (sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status = SL_STATUS_OK; + const int vector_z = SLI_MVP_ARRAY(0); + const int vector_z1 = SLI_MVP_ARRAY(1); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); + + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R1, value, value); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + SLI_MVP_ALU_Z(SLI_MVP_R1), + 0, + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(NOOP), + SLI_MVP_ALU_Z(SLI_MVP_R1), + 0, + SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)output; + + sli_mvp_alu_reg_t r; + r.reg.value.real = value; + r.reg.value.imag = value; + MVP->ALU[1].REGSTATE = r.REGSTATE; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[1].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[1].DIM1CFG = + 0; + MVP->ARRAY[1].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_A(SLI_MVP_R1); + MVP->INSTR[1].CFG1 = SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(NOOP) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c index dc3758b..7934cef 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c @@ -1,232 +1,232 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Mul functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -#if USE_MVP_PROGRAMBUILDER -#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 1000 -#else -#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 320 -#endif - -sl_status_t sl_math_mvp_vector_mult_f16(const float16_t *input_a, const float16_t *input_b, float16_t *output, size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - bool use_parallel; - uint32_t len_parallel; - uint32_t rows, cols; - sl_status_t status; - sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - - // Check if MVP parallel processing is possible and preferred. - use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) - && sli_mvp_util_is_pointer_word_aligned(input_b) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2) - && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); - - if (use_parallel) { - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_parallel = 2; - if (len_vector & 1U) { - len_remainder++; - } - len_vector /= 2; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - - #if USE_MVP_PROGRAMBUILDER - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_y = SLI_MVP_ARRAY(1); - const int vector_z = SLI_MVP_ARRAY(2); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x, (void *)&input_a[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_y, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - } - status = sli_mvp_cmd_wait_for_completion(); -#else - - sli_mvp_cmd_enable(); - - // Handle the main part. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - - // Wait for the program completion. - if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { - return status; - } - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = - 0; - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder]; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[0].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_ENDPROG - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - - // Wait for the program completion. - status = sli_mvp_cmd_wait_for_completion(); - } - #endif - - return status; -} +/***************************************************************************//** + * @file + * @brief MVP Math Mul functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +#if USE_MVP_PROGRAMBUILDER +#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 1000 +#else +#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 320 +#endif + +sl_status_t sl_math_mvp_vector_mult_f16(const float16_t *input_a, const float16_t *input_b, float16_t *output, size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + bool use_parallel; + uint32_t len_parallel; + uint32_t rows, cols; + sl_status_t status; + sli_mvp_datatype_t data_type = SLI_MVP_DATATYPE_BINARY16; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + + // Check if MVP parallel processing is possible and preferred. + use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) + && sli_mvp_util_is_pointer_word_aligned(input_b) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2) + && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); + + if (use_parallel) { + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_parallel = 2; + if (len_vector & 1U) { + len_remainder++; + } + len_vector /= 2; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + + #if USE_MVP_PROGRAMBUILDER + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_y = SLI_MVP_ARRAY(1); + const int vector_z = SLI_MVP_ARRAY(2); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input_a, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_y, (void *)input_b, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_y, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x, (void *)&input_a[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_y, (void *)&input_b[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH) | SLI_MVP_LOAD(1, SLI_MVP_R2, vector_y, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + } + status = sli_mvp_cmd_wait_for_completion(); +#else + + sli_mvp_cmd_enable(); + + // Handle the main part. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input_a; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)input_b; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + + // Wait for the program completion. + if ((status = sli_mvp_cmd_wait_for_completion()) != SL_STATUS_OK) { + return status; + } + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = MVP->ARRAY[2].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = MVP->ARRAY[2].DIM1CFG = + 0; + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = MVP->ARRAY[2].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)&input_a[ofs_remainder]; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)&input_b[ofs_remainder]; + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[0].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_LOAD(1, SLI_MVP_R2, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_ENDPROG + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + + // Wait for the program completion. + status = sli_mvp_cmd_wait_for_completion(); + } + #endif + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c index 79f1c94..452f827 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c @@ -1,205 +1,205 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Negate function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_negate.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_negate_f16(const float16_t *input, - float16_t *output, - size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check if MVP parallel processing is possible. - len_vector = (uint32_t)num_elements; - len_parallel = 1U; - len_remainder = 0U; - data_type = SLI_MVP_DATATYPE_BINARY16; - - if (sli_mvp_util_is_pointer_word_aligned(input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - // Factorize len_vector into rows * cols. - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1U; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - // This is the reference MVP program for the optimized setup below. - - sl_status_t status = SL_STATUS_OK; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), // COPY: Z = A - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(COPY), // COPY: Z = A - SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) - | SLI_MVP_ALU_Z(SLI_MVP_R1); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Vector Negate function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_negate.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_negate_f16(const float16_t *input, + float16_t *output, + size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if MVP parallel processing is possible. + len_vector = (uint32_t)num_elements; + len_parallel = 1U; + len_remainder = 0U; + data_type = SLI_MVP_DATATYPE_BINARY16; + + if (sli_mvp_util_is_pointer_word_aligned(input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + // Factorize len_vector into rows * cols. + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1U; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + // This is the reference MVP program for the optimized setup below. + + sl_status_t status = SL_STATUS_OK; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), // COPY: Z = A + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(COPY), // COPY: Z = A + SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R1, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALUIN_A(SLI_MVP_R0, SLI_MVP_ALUIN_REALNEGATE | SLI_MVP_ALUIN_IMAGNEGATE) + | SLI_MVP_ALU_Z(SLI_MVP_R1); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R1, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(COPY) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c index 2624a7f..1fe72f1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c @@ -1,224 +1,224 @@ -/***************************************************************************//** - * @file - * @brief MVP Math vector offset functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_math_mvp_vector_offset.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_offset_f16(const float16_t *input, - const float16_t offset, - float16_t *output, - size_t num_elements) -{ - sli_mvp_datatype_t data_type; - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_parallel = 1; - len_remainder = 0; - data_type = SLI_MVP_DATATYPE_BINARY16; - - if (sli_mvp_util_is_pointer_word_aligned((float16_t *)input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2U)) { - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_vector /= 2U; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - -#if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); - - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R1, offset, offset); - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(AACC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(AACC), - SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } -#else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - - // Program registers - sli_mvp_alu_reg_t r; - r.reg.value.real = offset; - r.reg.value.imag = offset; - MVP->ALU[1].REGSTATE = r.REGSTATE; - MVP->ALU[2].REGSTATE = 0; - - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(AACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) - | SLI_MVP_ALU_Y(SLI_MVP_R1) - | SLI_MVP_ALU_A(SLI_MVP_R2) - | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(AACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; -#endif // USE_MVP_PROGRAMBUILDER - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math vector offset functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_math_mvp_vector_offset.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_offset_f16(const float16_t *input, + const float16_t offset, + float16_t *output, + size_t num_elements) +{ + sli_mvp_datatype_t data_type; + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_parallel = 1; + len_remainder = 0; + data_type = SLI_MVP_DATATYPE_BINARY16; + + if (sli_mvp_util_is_pointer_word_aligned((float16_t *)input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2U)) { + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_vector /= 2U; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + +#if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, output, data_type, rows, cols, &status); + + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R1, offset, offset); + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, 0, 0); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(AACC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(AACC), + SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R0, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } +#else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + + // Program registers + sli_mvp_alu_reg_t r; + r.reg.value.real = offset; + r.reg.value.imag = offset; + MVP->ALU[1].REGSTATE = r.REGSTATE; + MVP->ALU[2].REGSTATE = 0; + + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(AACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R0) + | SLI_MVP_ALU_Y(SLI_MVP_R1) + | SLI_MVP_ALU_A(SLI_MVP_R2) + | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R0, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(AACC) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; +#endif // USE_MVP_PROGRAMBUILDER + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c index 426e5b0..0b60bc4 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c @@ -1,207 +1,207 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Scale functions. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_math_mvp.h" -#include "sl_mvp_util.h" -#include "sl_mvp_program_area.h" -#include "sl_common.h" - -#define USE_MVP_PROGRAMBUILDER 0 - -sl_status_t sl_math_mvp_vector_scale_f16(const float16_t *input, float16_t scale, float16_t *output, size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - uint32_t len_parallel; - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - - if (!input || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check if MVP parallel processing is possible. - len_vector = (uint32_t)num_elements; - len_remainder = 0; - len_parallel = 1; - data_type = SLI_MVP_DATATYPE_BINARY16; - - if (sli_mvp_util_is_pointer_word_aligned(input) - && sli_mvp_util_is_pointer_word_aligned(output) - && (num_elements >= 2U)) { - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_parallel = 2; - if (len_vector & 1U ) { - len_remainder++; - } - len_vector /= 2; - } - - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - ofs_remainder = num_elements - len_remainder; - - #if USE_MVP_PROGRAMBUILDER - sl_status_t status; - const int vector_x = SLI_MVP_ARRAY(0); - const int vector_z = SLI_MVP_ARRAY(1); - const int vector_x1 = SLI_MVP_ARRAY(2); - const int vector_z1 = SLI_MVP_ARRAY(3); - - sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); - sli_mvp_pb_init_program(p); - sli_mvp_pb_begin_program(p); - - sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); - sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); - - // Set the register to the scale value once, do not have to worry about alignment. - sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, scale, scale); - - sli_mvp_pb_begin_loop(p, rows, &status); { - sli_mvp_pb_begin_loop(p, cols, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); - sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); - } - sli_mvp_pb_end_loop(p); - - if (len_remainder > 0) { - sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); - - sli_mvp_pb_begin_loop(p, len_remainder, &status); { - sli_mvp_pb_compute(p, - SLI_MVP_OP(MULR2A), - SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), - SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x1, SLI_MVP_INCRDIM_WIDTH), - SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), - &status); - } - sli_mvp_pb_end_loop(p); - } - - // Check if any errors found during program generation. - if (status != SL_STATUS_OK) { - return status; - } - if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { - return status; - } - #else - - sli_mvp_cmd_enable(); - - // Program array controllers. - MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = - data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = - ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); - MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = - ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; - MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; - // Program loop controllers. - MVP->LOOP[1].RST = 0; - MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) - | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) - | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) - << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); - // Program registers. - sli_mvp_alu_reg_t r; - r.reg.value.real = scale; - r.reg.value.imag = scale; - MVP->ALU[SLI_MVP_R2].REGSTATE = r.REGSTATE; - // Program instruction. - MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP0BEGIN - | MVP_INSTRCFG2_LOOP0END - | MVP_INSTRCFG2_LOOP1BEGIN - | MVP_INSTRCFG2_LOOP1END; - - size_t last_instruction_idx = 0; - - if (len_remainder > 0) { - // Handle the remainder. - // Program array controllers. - MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = - //Note: The remainder can be any size, cannot utilize parallel execution. - SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; - MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = - 0; - MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = - ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); - MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; - MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; - - // Program loop controllers. - MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; - - // Program instructions. - MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); - MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) - | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); - MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) - | MVP_INSTRCFG2_LOOP2BEGIN - | MVP_INSTRCFG2_LOOP2END; - - // Move the next instruction index - last_instruction_idx += 1; - } - - // Set ENDPROG. - MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; - - // Start program. - MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; - #endif - - return sli_mvp_cmd_wait_for_completion(); -} +/***************************************************************************//** + * @file + * @brief MVP Math Scale functions. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_math_mvp.h" +#include "sl_mvp_util.h" +#include "sl_mvp_program_area.h" +#include "sl_common.h" + +#define USE_MVP_PROGRAMBUILDER 0 + +sl_status_t sl_math_mvp_vector_scale_f16(const float16_t *input, float16_t scale, float16_t *output, size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + uint32_t len_parallel; + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + + if (!input || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check if MVP parallel processing is possible. + len_vector = (uint32_t)num_elements; + len_remainder = 0; + len_parallel = 1; + data_type = SLI_MVP_DATATYPE_BINARY16; + + if (sli_mvp_util_is_pointer_word_aligned(input) + && sli_mvp_util_is_pointer_word_aligned(output) + && (num_elements >= 2U)) { + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_parallel = 2; + if (len_vector & 1U ) { + len_remainder++; + } + len_vector /= 2; + } + + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + ofs_remainder = num_elements - len_remainder; + + #if USE_MVP_PROGRAMBUILDER + sl_status_t status; + const int vector_x = SLI_MVP_ARRAY(0); + const int vector_z = SLI_MVP_ARRAY(1); + const int vector_x1 = SLI_MVP_ARRAY(2); + const int vector_z1 = SLI_MVP_ARRAY(3); + + sli_mvp_program_context_t *p = sli_mvp_get_program_area_context(); + sli_mvp_pb_init_program(p); + sli_mvp_pb_begin_program(p); + + sli_mvp_pb_config_matrix(p->p, vector_x, (void *)input, data_type, rows, cols, &status); + sli_mvp_pb_config_matrix(p->p, vector_z, (void *)output, data_type, rows, cols, &status); + + // Set the register to the scale value once, do not have to worry about alignment. + sli_mvp_prog_set_reg_f16c(p->p, SLI_MVP_R2, scale, scale); + + sli_mvp_pb_begin_loop(p, rows, &status); { + sli_mvp_pb_begin_loop(p, cols, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + sli_mvp_pb_postloop_incr_dim(p, vector_x, SLI_MVP_INCRDIM_HEIGHT); + sli_mvp_pb_postloop_incr_dim(p, vector_z, SLI_MVP_INCRDIM_HEIGHT); + } + sli_mvp_pb_end_loop(p); + + if (len_remainder > 0) { + sli_mvp_pb_config_vector(p->p, vector_x1, (void *)&input[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + sli_mvp_pb_config_vector(p->p, vector_z1, (void *)&output[ofs_remainder], SLI_MVP_DATATYPE_BINARY16, len_remainder, &status); + + sli_mvp_pb_begin_loop(p, len_remainder, &status); { + sli_mvp_pb_compute(p, + SLI_MVP_OP(MULR2A), + SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3), + SLI_MVP_LOAD(0, SLI_MVP_R1, vector_x1, SLI_MVP_INCRDIM_WIDTH), + SLI_MVP_STORE(SLI_MVP_R3, vector_z1, SLI_MVP_INCRDIM_WIDTH), + &status); + } + sli_mvp_pb_end_loop(p); + } + + // Check if any errors found during program generation. + if (status != SL_STATUS_OK) { + return status; + } + if ((status = sli_mvp_pb_execute_program(p)) != SL_STATUS_OK) { + return status; + } + #else + + sli_mvp_cmd_enable(); + + // Program array controllers. + MVP->ARRAY[0].DIM0CFG = MVP->ARRAY[1].DIM0CFG = + data_type << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[0].DIM1CFG = MVP->ARRAY[1].DIM1CFG = + ((rows - 1) << _MVP_ARRAYDIM1CFG_SIZE_SHIFT) | (cols << _MVP_ARRAYDIM1CFG_STRIDE_SHIFT); + MVP->ARRAY[0].DIM2CFG = MVP->ARRAY[1].DIM2CFG = + ((cols - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[0].ADDRCFG = (sli_mvp_addr_reg_t)input; + MVP->ARRAY[1].ADDRCFG = (sli_mvp_addr_reg_t)output; + // Program loop controllers. + MVP->LOOP[1].RST = 0; + MVP->LOOP[0].CFG = (rows - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + MVP->LOOP[1].CFG = ((cols - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT) + | ((SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_HEIGHT) + | SLI_MVP_LOOP_INCRDIM(SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_HEIGHT)) + << _MVP_LOOPCFG_ARRAY0INCRDIM0_SHIFT); + // Program registers. + sli_mvp_alu_reg_t r; + r.reg.value.real = scale; + r.reg.value.imag = scale; + MVP->ALU[SLI_MVP_R2].REGSTATE = r.REGSTATE; + // Program instruction. + MVP->INSTR[0].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[0].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(0), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(1), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[0].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP0BEGIN + | MVP_INSTRCFG2_LOOP0END + | MVP_INSTRCFG2_LOOP1BEGIN + | MVP_INSTRCFG2_LOOP1END; + + size_t last_instruction_idx = 0; + + if (len_remainder > 0) { + // Handle the remainder. + // Program array controllers. + MVP->ARRAY[2].DIM0CFG = MVP->ARRAY[3].DIM0CFG = + //Note: The remainder can be any size, cannot utilize parallel execution. + SLI_MVP_DATATYPE_BINARY16 << _MVP_ARRAYDIM0CFG_BASETYPE_SHIFT; + MVP->ARRAY[2].DIM1CFG = MVP->ARRAY[3].DIM1CFG = + 0; + MVP->ARRAY[2].DIM2CFG = MVP->ARRAY[3].DIM2CFG = + ((len_remainder - 1) << _MVP_ARRAYDIM2CFG_SIZE_SHIFT) | (1 << _MVP_ARRAYDIM2CFG_STRIDE_SHIFT); + MVP->ARRAY[2].ADDRCFG = (sli_mvp_addr_reg_t)&input[ofs_remainder]; + MVP->ARRAY[3].ADDRCFG = (sli_mvp_addr_reg_t)&output[ofs_remainder]; + + // Program loop controllers. + MVP->LOOP[2].CFG = (len_remainder - 1) << _MVP_LOOPCFG_NUMITERS_SHIFT; + + // Program instructions. + MVP->INSTR[1].CFG0 = SLI_MVP_ALU_X(SLI_MVP_R1) | SLI_MVP_ALU_Y(SLI_MVP_R2) | SLI_MVP_ALU_Z(SLI_MVP_R3); + MVP->INSTR[1].CFG1 = SLI_MVP_LOAD(0, SLI_MVP_R1, SLI_MVP_ARRAY(2), SLI_MVP_INCRDIM_WIDTH) + | SLI_MVP_STORE(SLI_MVP_R3, SLI_MVP_ARRAY(3), SLI_MVP_INCRDIM_WIDTH); + MVP->INSTR[1].CFG2 = (SLI_MVP_OP(MULR2A) << _MVP_INSTRCFG2_ALUOP_SHIFT) + | MVP_INSTRCFG2_LOOP2BEGIN + | MVP_INSTRCFG2_LOOP2END; + + // Move the next instruction index + last_instruction_idx += 1; + } + + // Set ENDPROG. + MVP->INSTR[last_instruction_idx].CFG2 |= MVP_INSTRCFG2_ENDPROG; + + // Start program. + MVP->CMD = MVP_CMD_INIT | MVP_CMD_START; + #endif + + return sli_mvp_cmd_wait_for_completion(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c index 050a102..5ca957a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c @@ -1,97 +1,97 @@ -/***************************************************************************//** - * @file - * @brief MVP Math Vector Sub function. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mvp.h" -#include "sl_mvp_util.h" -#include "sl_math_mvp_vector_sub.h" -#include "sl_math_mvp_matrix_sub.h" - -#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 480 - -sl_status_t sl_math_mvp_vector_sub_f16(const float16_t *input_a, - const float16_t *input_b, - float16_t *output, - size_t num_elements) -{ - uint32_t len_vector; - uint32_t len_remainder; - size_t ofs_remainder; - bool use_parallel; - uint32_t len_parallel; - uint32_t rows, cols; - sli_mvp_datatype_t data_type; - sl_status_t status; - - if (!input_a || !input_b || !output || !num_elements) { - return SL_STATUS_INVALID_PARAMETER; - } - - len_vector = (uint32_t)num_elements; - len_parallel = 1U; - len_remainder = 0U; - data_type = SLI_MVP_DATATYPE_BINARY16; - - // Check if MVP parallel processing is possible. - use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) - && sli_mvp_util_is_pointer_word_aligned(input_b) - && sli_mvp_util_is_pointer_word_aligned(output) - && (len_vector >= 2) - && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); - - if (use_parallel) { - data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; - len_parallel = 2U; - if (len_vector & 1U ) { - len_remainder++; - } - len_vector /= 2U; - } - - // Factorize len_vector into rows * cols. - if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { - rows = 1U; - cols = len_vector; - } else { - while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { - len_vector--; - len_remainder += len_parallel; - } - } - - if ((status = sli_math_mvp_matrix_sub_f16(input_a, input_b, output, rows, cols, data_type)) != SL_STATUS_OK) { - return status; - } - - if (len_remainder > 0) { - ofs_remainder = num_elements - len_remainder; - status = sli_math_mvp_matrix_sub_f16(&input_a[ofs_remainder], &input_b[ofs_remainder], &output[ofs_remainder], 1, len_remainder, SLI_MVP_DATATYPE_BINARY16); - } - - return status; -} +/***************************************************************************//** + * @file + * @brief MVP Math Vector Sub function. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mvp.h" +#include "sl_mvp_util.h" +#include "sl_math_mvp_vector_sub.h" +#include "sl_math_mvp_matrix_sub.h" + +#define MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING 480 + +sl_status_t sl_math_mvp_vector_sub_f16(const float16_t *input_a, + const float16_t *input_b, + float16_t *output, + size_t num_elements) +{ + uint32_t len_vector; + uint32_t len_remainder; + size_t ofs_remainder; + bool use_parallel; + uint32_t len_parallel; + uint32_t rows, cols; + sli_mvp_datatype_t data_type; + sl_status_t status; + + if (!input_a || !input_b || !output || !num_elements) { + return SL_STATUS_INVALID_PARAMETER; + } + + len_vector = (uint32_t)num_elements; + len_parallel = 1U; + len_remainder = 0U; + data_type = SLI_MVP_DATATYPE_BINARY16; + + // Check if MVP parallel processing is possible. + use_parallel = sli_mvp_util_is_pointer_word_aligned(input_a) + && sli_mvp_util_is_pointer_word_aligned(input_b) + && sli_mvp_util_is_pointer_word_aligned(output) + && (len_vector >= 2) + && (((len_vector & 1U) == 0) || (len_vector > MIN_VECTOR_LEN_FOR_PARALLEL_PROCESSING)); + + if (use_parallel) { + data_type = SLI_MVP_DATATYPE_COMPLEX_BINARY16; + len_parallel = 2U; + if (len_vector & 1U ) { + len_remainder++; + } + len_vector /= 2U; + } + + // Factorize len_vector into rows * cols. + if (len_vector <= SLI_MVP_MAX_ROW_LENGTH) { + rows = 1U; + cols = len_vector; + } else { + while (sli_mvp_util_factorize_number(len_vector, 1024U, &rows, &cols) != SL_STATUS_OK) { + len_vector--; + len_remainder += len_parallel; + } + } + + if ((status = sli_math_mvp_matrix_sub_f16(input_a, input_b, output, rows, cols, data_type)) != SL_STATUS_OK) { + return status; + } + + if (len_remainder > 0) { + ofs_remainder = num_elements - len_remainder; + status = sli_math_mvp_matrix_sub_f16(&input_a[ofs_remainder], &input_b[ofs_remainder], &output[ofs_remainder], 1, len_remainder, SLI_MVP_DATATYPE_BINARY16); + } + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/compute/math/src/sl_math_matrix.c b/locator_host/gecko_sdk_4.4.1/platform/compute/math/src/sl_math_matrix.c index 08e5a60..2b0bee1 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/compute/math/src/sl_math_matrix.c +++ b/locator_host/gecko_sdk_4.4.1/platform/compute/math/src/sl_math_matrix.c @@ -1,37 +1,37 @@ -/***************************************************************************//** - * @file - * @brief Math matrix definitions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_math_matrix.h" - -void sl_math_matrix_init_f16(sl_math_matrix_f16_t *matrix, size_t num_rows, size_t num_cols, float16_t *data) -{ - matrix->num_rows = num_rows; - matrix->num_cols = num_cols; - matrix->data = data; -} +/***************************************************************************//** + * @file + * @brief Math matrix definitions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_math_matrix.h" + +void sl_math_matrix_init_f16(sl_math_matrix_f16_t *matrix, size_t num_rows, size_t num_cols, float16_t *data) +{ + matrix->num_rows = num_rows; + matrix->num_cols = num_cols; + matrix->data = data; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h b/locator_host/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h index 5529b4c..21b86b8 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h @@ -1,167 +1,167 @@ -/***************************************************************************//** - * @file - * @brief SWO configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEBUG_SWO_H -#define SL_DEBUG_SWO_H - -#include "sl_status.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup debug Debug - * @{ - * @addtogroup debug_swo SWO Debug - * @brief Serial Wire Output Debug Configuration - * @details - * Initializes Serial Wire Output using the DWT and ITM peripherals of - * Cortex-M processors. Configures output of Program Counter samples, - * interrupt events, and data over any ITM channel. - * @{ - */ -/** - * Initialize SWO Debug - * - * @details - * Initializes SWO debug using configuration parameters for frequency, as well - * as whether PC sample events and interrupt events should be emitted. - * - * @note - * This function does not enable any software stimulus ports in the ITM. This - * can be done by calling @ref sl_debug_swo_enable_itm or by using - * @ref sl_debug_swo_write which enables the necessary ports automatically. - * - * @return Status code - * @retval SL_STATUS_OK SWO initialized successfully - */ -sl_status_t sl_debug_swo_init(void); - -/** - * Enable an ITM channel - * - * @details - * Enables the given ITM channel in the Trace Enable Register. - * - * @param[in] channel ITM channel number - * - * @return Status code - * @retval SL_STATUS_OK ITM channel enabled successfully - */ -sl_status_t sl_debug_swo_enable_itm(uint32_t channel); - -/** - * Disable an ITM channel - * - * @details - * Disables the given ITM channel in the Trace Enable Register. - * - * @param[in] channel ITM channel number - * - * @return Status code - * @retval SL_STATUS_OK ITM channel disabled successfully - */ -sl_status_t sl_debug_swo_disable_itm(uint32_t channel); - -/** - * Write a byte to an ITM channel - * - * @details - * Writes the given byte to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. Note that even if the debug port is locked, the byte - * will still be written on the SWO. - * - * @param[in] channel ITM channel number - * @param[in] byte Byte to send - * - * @return Status code - * @retval SL_STATUS_OK Byte sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte); - -/** - * Write a half-word to an ITM channel - * - * @details - * Writes the given half-word to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. - * - * @param[in] channel ITM channel number - * @param[in] half_word Half-word to send - * - * @return Status code - * @retval SL_STATUS_OK half-word sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word); - -/** - * Write a word to an ITM channel - * - * @details - * Writes the given word to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. - * - * @param[in] channel ITM channel number - * @param[in] word Word to send - * - * @return Status code - * @retval SL_STATUS_OK half-word sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word); - -/** - * alias for backward compatibility - */ -#define sl_debug_swo_write sl_debug_swo_write_u8 - -/** @} end debug_swo */ -/** @} end debug */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEBUG_SWO_H +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEBUG_SWO_H +#define SL_DEBUG_SWO_H + +#include "sl_status.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup debug Debug + * @{ + * @addtogroup debug_swo SWO Debug + * @brief Serial Wire Output Debug Configuration + * @details + * Initializes Serial Wire Output using the DWT and ITM peripherals of + * Cortex-M processors. Configures output of Program Counter samples, + * interrupt events, and data over any ITM channel. + * @{ + */ +/** + * Initialize SWO Debug + * + * @details + * Initializes SWO debug using configuration parameters for frequency, as well + * as whether PC sample events and interrupt events should be emitted. + * + * @note + * This function does not enable any software stimulus ports in the ITM. This + * can be done by calling @ref sl_debug_swo_enable_itm or by using + * @ref sl_debug_swo_write which enables the necessary ports automatically. + * + * @return Status code + * @retval SL_STATUS_OK SWO initialized successfully + */ +sl_status_t sl_debug_swo_init(void); + +/** + * Enable an ITM channel + * + * @details + * Enables the given ITM channel in the Trace Enable Register. + * + * @param[in] channel ITM channel number + * + * @return Status code + * @retval SL_STATUS_OK ITM channel enabled successfully + */ +sl_status_t sl_debug_swo_enable_itm(uint32_t channel); + +/** + * Disable an ITM channel + * + * @details + * Disables the given ITM channel in the Trace Enable Register. + * + * @param[in] channel ITM channel number + * + * @return Status code + * @retval SL_STATUS_OK ITM channel disabled successfully + */ +sl_status_t sl_debug_swo_disable_itm(uint32_t channel); + +/** + * Write a byte to an ITM channel + * + * @details + * Writes the given byte to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. Note that even if the debug port is locked, the byte + * will still be written on the SWO. + * + * @param[in] channel ITM channel number + * @param[in] byte Byte to send + * + * @return Status code + * @retval SL_STATUS_OK Byte sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte); + +/** + * Write a half-word to an ITM channel + * + * @details + * Writes the given half-word to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. + * + * @param[in] channel ITM channel number + * @param[in] half_word Half-word to send + * + * @return Status code + * @retval SL_STATUS_OK half-word sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word); + +/** + * Write a word to an ITM channel + * + * @details + * Writes the given word to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. + * + * @param[in] channel ITM channel number + * @param[in] word Word to send + * + * @return Status code + * @retval SL_STATUS_OK half-word sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word); + +/** + * alias for backward compatibility + */ +#define sl_debug_swo_write sl_debug_swo_write_u8 + +/** @} end debug_swo */ +/** @} end debug */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEBUG_SWO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c b/locator_host/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c index 8151608..3b02ab2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c +++ b/locator_host/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c @@ -1,269 +1,269 @@ -/***************************************************************************//** - * @file - * @brief SWO debug - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_debug_swo.h" - -#include "em_device.h" - -#if defined(__CORTEX_M) && (__CORTEX_M >= 3) - -#if _SILICON_LABS_32B_SERIES <= 2 -#include "em_gpio.h" -#else -#include "sl_peripheral_gpio.h" -#endif - -#include "em_cmu.h" -#include "sl_debug_swo_config.h" - -sl_status_t sl_debug_swo_init(void) -{ - uint32_t freq = 0.0f; - uint16_t cyctap = 0U; - uint16_t postpreset = 0U; - -#if _SILICON_LABS_32B_SERIES <= 2 - unsigned int location = 0U; - CMU_ClockEnable(cmuClock_GPIO, true); - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) - // Series 0 - location = SL_DEBUG_ROUTE_LOC; - GPIO_PinModeSet(SL_DEBUG_SWO_PORT, SL_DEBUG_SWO_PIN, gpioModePushPull, 1); -#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) - // Series 1 - location = SL_DEBUG_SWV_LOC; - GPIO_PinModeSet(SL_DEBUG_SWV_PORT, SL_DEBUG_SWV_PIN, gpioModePushPull, 1); -#elif defined(GPIO_SWV_PORT) - // Series 2 - // SWO location is not configurable - GPIO_PinModeSet((GPIO_Port_TypeDef)GPIO_SWV_PORT, GPIO_SWV_PIN, gpioModePushPull, 1); -#endif - - // Set SWO location - GPIO_DbgLocationSet(location); - - // Enable SWO pin - GPIO_DbgSWOEnable(true); - -#else -#if defined(GPIO_SWV_PORT) - sl_gpio_set_pin_mode((sl_gpio_port_t)GPIO_SWV_PORT, GPIO_SWV_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#endif - - sl_gpio_enable_debug_swo(true); -#endif - -#if _SILICON_LABS_32B_SERIES < 2 - // Enable debug clock - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - - // Get debug clock frequency - freq = CMU_ClockFreqGet(cmuClock_DBG); -#else - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) -#if defined(_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) -#if defined(CMU_CLKEN0_HFRCOEM23) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; -#endif - // Select HFRCOEM23 as source for TRACECLK - CMU_CLOCK_SELECT_SET(TRACECLK, HFRCOEM23); -#elif defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) - // Select SYSCLK as source for TRACECLK - CMU_CLOCK_SELECT_SET(TRACECLK, SYSCLK); -#endif -#endif - - freq = CMU_ClockFreqGet(cmuClock_TRACECLK); -#endif - - // Enable trace in core debug - CoreDebug->DHCSR |= CoreDebug_DHCSR_C_DEBUGEN_Msk; - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - //Tap the cyctap and postpreset based on the selected interval -#ifdef SL_DEBUG_SWO_SAMPLE_INTERVAL - if (SL_DEBUG_SWO_SAMPLE_INTERVAL <= 960) { - cyctap = 0; - postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 64); - } else { - cyctap = 1; - postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 1024); - } -#else - cyctap = 1; - postpreset = 0xF; -#endif - // Enable PC and IRQ sampling output - DWT->CTRL = ((4UL << DWT_CTRL_NUMCOMP_Pos) // Number of comparators. Hardwired to 4. - | (SL_DEBUG_SWO_SAMPLE_IRQ << DWT_CTRL_EXCTRCENA_Pos) // Interrupt events - | (SL_DEBUG_SWO_SAMPLE_PC << DWT_CTRL_PCSAMPLENA_Pos) // PC sample events - | (cyctap << DWT_CTRL_CYCTAP_Pos) // Tap cycle counter at bit 10 (vs bit 6 if 0) - | (0xFUL << DWT_CTRL_POSTINIT_Pos) // Post-tap counter - | (postpreset << DWT_CTRL_POSTPRESET_Pos) // Post-tap counter reload value - | (1UL << DWT_CTRL_CYCCNTENA_Pos)); // Enable cycle counter - // Set TPIU prescaler for the current debug clock frequency. ACPR value is div - 1. - TPI->ACPR = ((freq + (SL_DEBUG_SWO_FREQ / 2)) / SL_DEBUG_SWO_FREQ) - 1UL; - - // Set protocol to NRZ - TPI->SPPR = 2UL; - - // Disable continuous formatting - TPI->FFCR = TPI_FFCR_TrigIn_Msk; - - // Unlock ITM and output data - ITM->LAR = 0xC5ACCE55UL; - // CMSIS bitfield naming is inconsistent - 16U maps to - // ITM_TCR_TraceBusID_Pos (v7M) or ITM_TCR_TRACEBUSID_Pos (v8M) - ITM->TCR = ((1UL << 16U) - | (1UL << ITM_TCR_DWTENA_Pos) - | (1UL << ITM_TCR_ITMENA_Pos)); - - // Send data on the SWO channel. This avoids corrupting data - // sent on the SWO channel shortly after initialization. - ITM->TER |= (1UL << 8); - ITM->PORT[8].u8 = 0xFF; - ITM->TER &= ~(1UL << 8); - - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_enable_itm(uint32_t channel) -{ - ITM->TER |= (1UL << channel); - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_disable_itm(uint32_t channel) -{ - ITM->TER &= ~(1UL << channel); - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u8 = byte; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u16 = half_word; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u32 = word; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -#else // __CORTEX_M - -sl_status_t sl_debug_swo_init(void) -{ - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_enable_itm(uint32_t channel) -{ - (void) channel; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_disable_itm(uint32_t channel) -{ - (void) channel; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) -{ - (void) channel; - (void) byte; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) -{ - (void) channel; - (void) half_word; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) -{ - (void) channel; - (void) word; - return SL_STATUS_NOT_SUPPORTED; -} - -#endif // __CORTEX_M +/***************************************************************************//** + * @file + * @brief SWO debug + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_debug_swo.h" + +#include "em_device.h" + +#if defined(__CORTEX_M) && (__CORTEX_M >= 3) + +#if _SILICON_LABS_32B_SERIES <= 2 +#include "em_gpio.h" +#else +#include "sl_peripheral_gpio.h" +#endif + +#include "em_cmu.h" +#include "sl_debug_swo_config.h" + +sl_status_t sl_debug_swo_init(void) +{ + uint32_t freq = 0.0f; + uint16_t cyctap = 0U; + uint16_t postpreset = 0U; + +#if _SILICON_LABS_32B_SERIES <= 2 + unsigned int location = 0U; + CMU_ClockEnable(cmuClock_GPIO, true); + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) + // Series 0 + location = SL_DEBUG_ROUTE_LOC; + GPIO_PinModeSet(SL_DEBUG_SWO_PORT, SL_DEBUG_SWO_PIN, gpioModePushPull, 1); +#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) + // Series 1 + location = SL_DEBUG_SWV_LOC; + GPIO_PinModeSet(SL_DEBUG_SWV_PORT, SL_DEBUG_SWV_PIN, gpioModePushPull, 1); +#elif defined(GPIO_SWV_PORT) + // Series 2 + // SWO location is not configurable + GPIO_PinModeSet((GPIO_Port_TypeDef)GPIO_SWV_PORT, GPIO_SWV_PIN, gpioModePushPull, 1); +#endif + + // Set SWO location + GPIO_DbgLocationSet(location); + + // Enable SWO pin + GPIO_DbgSWOEnable(true); + +#else +#if defined(GPIO_SWV_PORT) + sl_gpio_set_pin_mode((sl_gpio_port_t)GPIO_SWV_PORT, GPIO_SWV_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#endif + + sl_gpio_enable_debug_swo(true); +#endif + +#if _SILICON_LABS_32B_SERIES < 2 + // Enable debug clock + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + + // Get debug clock frequency + freq = CMU_ClockFreqGet(cmuClock_DBG); +#else + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) +#if defined(_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) +#if defined(CMU_CLKEN0_HFRCOEM23) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; +#endif + // Select HFRCOEM23 as source for TRACECLK + CMU_CLOCK_SELECT_SET(TRACECLK, HFRCOEM23); +#elif defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) + // Select SYSCLK as source for TRACECLK + CMU_CLOCK_SELECT_SET(TRACECLK, SYSCLK); +#endif +#endif + + freq = CMU_ClockFreqGet(cmuClock_TRACECLK); +#endif + + // Enable trace in core debug + CoreDebug->DHCSR |= CoreDebug_DHCSR_C_DEBUGEN_Msk; + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + //Tap the cyctap and postpreset based on the selected interval +#ifdef SL_DEBUG_SWO_SAMPLE_INTERVAL + if (SL_DEBUG_SWO_SAMPLE_INTERVAL <= 960) { + cyctap = 0; + postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 64); + } else { + cyctap = 1; + postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 1024); + } +#else + cyctap = 1; + postpreset = 0xF; +#endif + // Enable PC and IRQ sampling output + DWT->CTRL = ((4UL << DWT_CTRL_NUMCOMP_Pos) // Number of comparators. Hardwired to 4. + | (SL_DEBUG_SWO_SAMPLE_IRQ << DWT_CTRL_EXCTRCENA_Pos) // Interrupt events + | (SL_DEBUG_SWO_SAMPLE_PC << DWT_CTRL_PCSAMPLENA_Pos) // PC sample events + | (cyctap << DWT_CTRL_CYCTAP_Pos) // Tap cycle counter at bit 10 (vs bit 6 if 0) + | (0xFUL << DWT_CTRL_POSTINIT_Pos) // Post-tap counter + | (postpreset << DWT_CTRL_POSTPRESET_Pos) // Post-tap counter reload value + | (1UL << DWT_CTRL_CYCCNTENA_Pos)); // Enable cycle counter + // Set TPIU prescaler for the current debug clock frequency. ACPR value is div - 1. + TPI->ACPR = ((freq + (SL_DEBUG_SWO_FREQ / 2)) / SL_DEBUG_SWO_FREQ) - 1UL; + + // Set protocol to NRZ + TPI->SPPR = 2UL; + + // Disable continuous formatting + TPI->FFCR = TPI_FFCR_TrigIn_Msk; + + // Unlock ITM and output data + ITM->LAR = 0xC5ACCE55UL; + // CMSIS bitfield naming is inconsistent - 16U maps to + // ITM_TCR_TraceBusID_Pos (v7M) or ITM_TCR_TRACEBUSID_Pos (v8M) + ITM->TCR = ((1UL << 16U) + | (1UL << ITM_TCR_DWTENA_Pos) + | (1UL << ITM_TCR_ITMENA_Pos)); + + // Send data on the SWO channel. This avoids corrupting data + // sent on the SWO channel shortly after initialization. + ITM->TER |= (1UL << 8); + ITM->PORT[8].u8 = 0xFF; + ITM->TER &= ~(1UL << 8); + + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_enable_itm(uint32_t channel) +{ + ITM->TER |= (1UL << channel); + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_disable_itm(uint32_t channel) +{ + ITM->TER &= ~(1UL << channel); + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u8 = byte; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u16 = half_word; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u32 = word; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +#else // __CORTEX_M + +sl_status_t sl_debug_swo_init(void) +{ + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_enable_itm(uint32_t channel) +{ + (void) channel; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_disable_itm(uint32_t channel) +{ + (void) channel; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) +{ + (void) channel; + (void) byte; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) +{ + (void) channel; + (void) half_word; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) +{ + (void) channel; + (void) word; + return SL_STATUS_NOT_SUPPORTED; +} + +#endif // __CORTEX_M diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h b/locator_host/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h index 033400b..ac23ead 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief Energy Aware drivers error code definitions. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_ECODE_H__ -#define __SILICON_LABS_ECODE_H__ - -#include - -/***************************************************************************//** - * @addtogroup ecode ECODE - Error Codes - * @details ECODE is set of error and status codes related to DMA, RTC, SPI, - * NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and - * status codes are used by the above listed drivers to update the layer - * (using the driver) about an error or status. - * - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Typedef for API function error code return values. - * - * @details - * Bit 24-31: Component, for example emdrv @n - * Bit 16-23: Module, for example @ref uartdrv or @ref spidrv @n - * Bit 0-15: Error code - ******************************************************************************/ -typedef uint32_t Ecode_t; - -#define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. - -#define ECODE_OK (0U) ///< Generic success return value. - -#define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. -#define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. -#define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. -#define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. -#define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. -#define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. -#define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. -#define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. - -/** @} (end addtogroup ecode) */ - -#endif // __SILICON_LABS_ECODE_H__ +/***************************************************************************//** + * @file + * @brief Energy Aware drivers error code definitions. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_ECODE_H__ +#define __SILICON_LABS_ECODE_H__ + +#include + +/***************************************************************************//** + * @addtogroup ecode ECODE - Error Codes + * @details ECODE is set of error and status codes related to DMA, RTC, SPI, + * NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and + * status codes are used by the above listed drivers to update the layer + * (using the driver) about an error or status. + * + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Typedef for API function error code return values. + * + * @details + * Bit 24-31: Component, for example emdrv @n + * Bit 16-23: Module, for example @ref uartdrv or @ref spidrv @n + * Bit 0-15: Error code + ******************************************************************************/ +typedef uint32_t Ecode_t; + +#define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. + +#define ECODE_OK (0U) ///< Generic success return value. + +#define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. +#define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. +#define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. +#define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. +#define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. +#define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. +#define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. +#define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. + +/** @} (end addtogroup ecode) */ + +#endif // __SILICON_LABS_ECODE_H__ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h b/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h index e03d466..99d9b07 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h @@ -1,1047 +1,1047 @@ -/***************************************************************************//** - * @file - * @brief DMADRV API definition. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __SILICON_LABS_DMADRV_H__ -#define __SILICON_LABS_DMADRV_H__ - -#include "em_device.h" -#include "ecode.h" -#include "sl_enum.h" - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define EMDRV_DMADRV_UDMA -#define EMDRV_DMADRV_DMA_PRESENT -#include "em_dma.h" -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#if (_SILICON_LABS_32B_SERIES > 2) -#define EMDRV_DMADRV_LDMA_S3 -#include "sl_peripheral_ldma.h" -#else -#define EMDRV_DMADRV_DMA_PRESENT -#define EMDRV_DMADRV_LDMA -#include "em_ldma.h" -#endif - -#else -#error "No valid DMA engine defined." -#endif - -#include "dmadrv_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup dmadrv - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup dmadrv_error_codes Error Codes - * @{ - ******************************************************************************/ - -#define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. -#define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. -#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. -#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. -#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. -#define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. -#define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. -#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. - -/** @} (end addtogroup error codes) */ -/***************************************************************************//** - * @brief - * DMADRV transfer completion callback function. - * - * @details - * The callback function is called when a transfer is complete. - * - * @param[in] channel - * The DMA channel number. - * - * @param[in] sequenceNo - * The number of times the callback was called. Useful on long chains of - * linked transfers or on endless ping-pong type transfers. - * - * @param[in] userParam - * Optional user parameter supplied on DMA invocation. - * - * @return - * When doing ping-pong transfers, return true to continue or false to - * stop transfers. - ******************************************************************************/ -typedef bool (*DMADRV_Callback_t)(unsigned int channel, - unsigned int sequenceNo, - void *userParam); - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) - -/// Maximum length of one DMA transfer. -#define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1)) - -/// Peripherals that can trigger UDMA transfers. -#ifdef DOXY_DOC_ONLY -SL_ENUM_GENERIC(DMADRV_Peripheralsignal_t, uint32_t) { -#else -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { -#endif - dmadrvPeripheralSignal_NONE = 0, ///< No peripheral selected for DMA triggering. - #if defined(DMAREQ_ADC0_SCAN) - dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN, ///< Trig on ADC0_SCAN. - #endif - #if defined(DMAREQ_ADC0_SINGLE) - dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE, ///< Trig on ADC0_SINGLE. - #endif - #if defined(DMAREQ_AES_DATARD) - dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD, ///< Trig on AES_DATARD. - #endif - #if defined(DMAREQ_AES_DATAWR) - dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR, ///< Trig on AES_DATAWR. - #endif - #if defined(DMAREQ_AES_KEYWR) - dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR, ///< Trig on AES_KEYWR. - #endif - #if defined(DMAREQ_AES_XORDATAWR) - dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR, ///< Trig on AES_XORDATAWR. - #endif - #if defined(DMAREQ_DAC0_CH0) - dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0, ///< Trig on DAC0_CH0. - #endif - #if defined(DMAREQ_DAC0_CH1) - dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1, ///< Trig on DAC0_CH1. - #endif - #if defined(DMAREQ_EBI_DDEMPTY) - dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY, ///< Trig on EBI_DDEMPTY. - #endif - #if defined(DMAREQ_EBI_PXL0EMPTY) - dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY, ///< Trig on EBI_PXL0EMPTY. - #endif - #if defined(DMAREQ_EBI_PXL1EMPTY) - dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY, ///< Trig on EBI_PXL1EMPTY. - #endif - #if defined(DMAREQ_EBI_PXLFULL) - dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL, ///< Trig on EBI_PXLFULL. - #endif - #if defined(DMAREQ_I2C0_RXDATAV) - dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV, ///< Trig on I2C0_RXDATAV. - #endif - #if defined(DMAREQ_I2C0_TXBL) - dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL, ///< Trig on I2C0_TXBL. - #endif - #if defined(DMAREQ_I2C1_RXDATAV) - dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV, ///< Trig on I2C1_RXDATAV. - #endif - #if defined(DMAREQ_I2C1_TXBL) - dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL, ///< Trig on I2C1_TXBL. - #endif - #if defined(DMAREQ_LESENSE_BUFDATAV) - dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV, ///< Trig on LESENSE_BUFDATAV. - #endif - #if defined(DMAREQ_LEUART0_RXDATAV) - dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV, ///< Trig on LEUART0_RXDATAV. - #endif - #if defined(DMAREQ_LEUART0_TXBL) - dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL, ///< Trig on LEUART0_TXBL. - #endif - #if defined(DMAREQ_LEUART0_TXEMPTY) - dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY, ///< Trig on LEUART0_TXEMPTY. - #endif - #if defined(DMAREQ_LEUART1_RXDATAV) - dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV, ///< Trig on LEUART1_RXDATAV. - #endif - #if defined(DMAREQ_LEUART1_TXBL) - dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL, ///< Trig on LEUART1_TXBL. - #endif - #if defined(DMAREQ_LEUART1_TXEMPTY) - dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY, ///< Trig on LEUART1_TXEMPTY. - #endif - #if defined(DMAREQ_MSC_WDATA) - dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA, ///< Trig on MSC_WDATA. - #endif - #if defined(DMAREQ_TIMER0_CC0) - dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0, ///< Trig on TIMER0_CC0. - #endif - #if defined(DMAREQ_TIMER0_CC1) - dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1, ///< Trig on TIMER0_CC1. - #endif - #if defined(DMAREQ_TIMER0_CC2) - dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2, ///< Trig on TIMER0_CC2. - #endif - #if defined(DMAREQ_TIMER0_UFOF) - dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF, ///< Trig on TIMER0_UFOF. - #endif - #if defined(DMAREQ_TIMER1_CC0) - dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0, ///< Trig on TIMER1_CC0. - #endif - #if defined(DMAREQ_TIMER1_CC1) - dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1, ///< Trig on TIMER1_CC1. - #endif - #if defined(DMAREQ_TIMER1_CC2) - dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2, ///< Trig on TIMER1_CC2. - #endif - #if defined(DMAREQ_TIMER1_UFOF) - dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF, ///< Trig on TIMER1_UFOF. - #endif - #if defined(DMAREQ_TIMER2_CC0) - dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0, ///< Trig on TIMER2_CC0. - #endif - #if defined(DMAREQ_TIMER2_CC1) - dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1, ///< Trig on TIMER2_CC1. - #endif - #if defined(DMAREQ_TIMER2_CC2) - dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2, ///< Trig on TIMER2_CC2. - #endif - #if defined(DMAREQ_TIMER2_UFOF) - dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF, ///< Trig on TIMER2_UFOF. - #endif - #if defined(DMAREQ_TIMER3_CC0) - dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0, ///< Trig on TIMER3_CC0. - #endif - #if defined(DMAREQ_TIMER3_CC1) - dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1, ///< Trig on TIMER3_CC1. - #endif - #if defined(DMAREQ_TIMER3_CC2) - dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2, ///< Trig on TIMER3_CC2. - #endif - #if defined(DMAREQ_TIMER3_UFOF) - dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF, ///< Trig on TIMER3_UFOF. - #endif - #if defined(DMAREQ_UART0_RXDATAV) - dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV, ///< Trig on UART0_RXDATAV. - #endif - #if defined(DMAREQ_UART0_TXBL) - dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL, ///< Trig on UART0_TXBL. - #endif - #if defined(DMAREQ_UART0_TXEMPTY) - dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY, ///< Trig on UART0_TXEMPTY. - #endif - #if defined(DMAREQ_UART1_RXDATAV) - dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV, ///< Trig on UART1_RXDATAV. - #endif - #if defined(DMAREQ_UART1_TXBL) - dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL, ///< Trig on UART1_TXBL. - #endif - #if defined(DMAREQ_UART1_TXEMPTY) - dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY, ///< Trig on UART1_TXEMPTY. - #endif - #if defined(DMAREQ_USART0_RXDATAV) - dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV, ///< Trig on USART0_RXDATAV. - #endif - #if defined(DMAREQ_USART0_TXBL) - dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL, ///< Trig on USART0_TXBL. - #endif - #if defined(DMAREQ_USART0_TXEMPTY) - dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY, ///< Trig on USART0_TXEMPTY. - #endif - #if defined(DMAREQ_USARTRF0_RXDATAV) - dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV, ///< Trig on USARTRF0_RXDATAV. - #endif - #if defined(DMAREQ_USARTRF0_TXBL) - dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL, ///< Trig on USARTRF0_TXBL. - #endif - #if defined(DMAREQ_USARTRF0_TXEMPTY) - dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY, ///< Trig on USARTRF0_TXEMPTY. - #endif - #if defined(DMAREQ_USARTRF1_RXDATAV) - dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV, ///< Trig on USARTRF1_RXDATAV. - #endif - #if defined(DMAREQ_USARTRF1_TXBL) - dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL, ///< Trig on USARTRF1_TXBL. - #endif - #if defined(DMAREQ_USARTRF1_TXEMPTY) - dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY, ///< Trig on USARTRF1_TXEMPTY. - #endif - #if defined(DMAREQ_USART1_RXDATAV) - dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV, ///< Trig on USART1_RXDATAV. - #endif - #if defined(DMAREQ_USART1_RXDATAVRIGHT) - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,///< Trig on USART1_RXDATAVRIGHT. - #endif - #if defined(DMAREQ_USART1_TXBL) - dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL, ///< Trig on USART1_TXBL. - #endif - #if defined(DMAREQ_USART1_TXBLRIGHT) - dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT, ///< Trig on USART1_TXBLRIGHT. - #endif - #if defined(DMAREQ_USART1_TXEMPTY) - dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY, ///< Trig on USART1_TXEMPTY. - #endif - #if defined(DMAREQ_USART2_RXDATAV) - dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV, ///< Trig on USART2_RXDATAV. - #endif - #if defined(DMAREQ_USART2_RXDATAVRIGHT) - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,///< Trig on USART2_RXDATAVRIGHT. - #endif - #if defined(DMAREQ_USART2_TXBL) - dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL, ///< Trig on USART2_TXBL. - #endif - #if defined(DMAREQ_USART2_TXBLRIGHT) - dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT, ///< Trig on USART2_TXBLRIGHT. - #endif - #if defined(DMAREQ_USART2_TXEMPTY) - dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY, ///< Trig on USART2_TXEMPTY. - #endif -}; - -/// Data size of one UDMA transfer item. -#ifdef DOXY_DOC_ONLY -SL_ENUM(DMADRV_Datasize_t) { -#else -SL_ENUM(DMADRV_DataSize_t) { -#endif - dmadrvDataSize1 = dmaDataSize1, ///< Byte - dmadrvDataSize2 = dmaDataSize2, ///< Halfword - dmadrvDataSize4 = dmaDataSize4 ///< Word -}; - -#endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 ) - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -/// Maximum length of one DMA transfer. -#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) - -#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) -/// Peripherals that can trigger LDMA transfers. -// TODO CM see if need to add stuff for Rainier XBAR -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { - dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 - dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 - dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 - dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF - dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 - dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 - dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 - dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF - dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV - dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT - dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL - dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT - dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY - dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV - dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL - dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT - dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY - dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV - dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL - dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT - dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY - dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV - dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL - dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV - dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL - dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI - dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF - dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 - dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 - dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 - dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 - dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 - dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF - dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF - dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG - dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN - dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE - dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA - dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 - dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 - dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 - dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF - dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 - dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 - dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 - dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF - dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL - dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL - dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL - dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL - dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL - dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL - dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL - dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL - dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL - dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL - dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART3_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL - dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL - dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_RXBL. - #endif -}; - -#else -/// Peripherals that can trigger LDMA transfers. -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { - dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) - dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) - dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) - dmadrvPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) - dmadrvPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) - dmadrvPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0 - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) - dmadrvPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1 - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_AGCRSSI) - dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) - dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) - dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) - dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) - dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) - dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) - dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) - dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) - dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) - dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) - dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) - dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) - dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) - dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) - dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) - dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) - dmadrvPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) - dmadrvPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) - dmadrvPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) - dmadrvPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) - dmadrvPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) - dmadrvPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) - dmadrvPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) - dmadrvPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV) - dmadrvPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) - dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) - dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) - dmadrvPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) - dmadrvPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) - dmadrvPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) - dmadrvPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) - dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) - dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) - dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) - dmadrvPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) - dmadrvPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) - dmadrvPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG) - dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) - dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF) - dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0) - dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1) - dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2) - dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3) - dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4) - dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF) - dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF) - dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) - dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) - dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) - dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) - dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) - dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC3) - dmadrvPeripheralSignal_TIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) - dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) - dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) - dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) - dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) - dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) - dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) - dmadrvPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) - dmadrvPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) - dmadrvPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC3) - dmadrvPeripheralSignal_TIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) - dmadrvPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) - dmadrvPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) - dmadrvPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) - dmadrvPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC3) - dmadrvPeripheralSignal_TIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) - dmadrvPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) - dmadrvPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) - dmadrvPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) - dmadrvPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC3) - dmadrvPeripheralSignal_TIMER4_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) - dmadrvPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) - dmadrvPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) - dmadrvPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) - dmadrvPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC3) - dmadrvPeripheralSignal_TIMER5_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) - dmadrvPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) - dmadrvPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) - dmadrvPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) - dmadrvPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC3) - dmadrvPeripheralSignal_TIMER6_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) - dmadrvPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) - dmadrvPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) - dmadrvPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) - dmadrvPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3) - dmadrvPeripheralSignal_WTIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) - dmadrvPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) - dmadrvPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) - dmadrvPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) - dmadrvPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) - dmadrvPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) - dmadrvPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) - dmadrvPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) - dmadrvPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) - dmadrvPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3) - dmadrvPeripheralSignal_WTIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) - dmadrvPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) - dmadrvPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) - dmadrvPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) - dmadrvPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3) - dmadrvPeripheralSignal_WTIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) - dmadrvPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) - dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) - dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) - dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) - dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) - dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) - dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) - dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) - dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT) - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) - dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT) - dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) - dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) - dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) - dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) - dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) - dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) - dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) - dmadrvPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) - dmadrvPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) - dmadrvPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) - dmadrvPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) - dmadrvPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) - dmadrvPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT) - dmadrvPeripheralSignal_USART5_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) - dmadrvPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT) - dmadrvPeripheralSignal_USART5_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) - dmadrvPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) - dmadrvPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) - dmadrvPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) - dmadrvPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) - dmadrvPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) - dmadrvPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) - dmadrvPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1 ///< Trig on UART1_TXEMPTY. - #endif -}; -#endif - -/// Data size of one LDMA transfer item. -SL_ENUM(DMADRV_DataSize_t) { -#if defined(EMDRV_DMADRV_LDMA_S3) - dmadrvDataSize1 = SL_HAL_LDMA_CTRL_SIZE_BYTE, ///< Byte - dmadrvDataSize2 = SL_HAL_LDMA_CTRL_SIZE_HALF, ///< Halfword - dmadrvDataSize4 = SL_HAL_LDMA_CTRL_SIZE_WORD ///< Word -#else - dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte - dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword - dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word -#endif -}; - -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ - -Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, - void *capabilities); -Ecode_t DMADRV_DeInit(void); -Ecode_t DMADRV_FreeChannel(unsigned int channelId); -Ecode_t DMADRV_Init(void); - -Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src0, - void *src1, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst0, - void *dst1, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); - -#if defined(EMDRV_DMADRV_LDMA) -Ecode_t DMADRV_LdmaStartTransfer(int channelId, - LDMA_TransferCfg_t *transfer, - LDMA_Descriptor_t *descriptor, - DMADRV_Callback_t callback, - void *cbUserParam); -#endif - -Ecode_t DMADRV_PauseTransfer(unsigned int channelId); -Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); -Ecode_t DMADRV_StopTransfer(unsigned int channelId); -Ecode_t DMADRV_TransferActive(unsigned int channelId, - bool *active); -Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, - bool *pending); -Ecode_t DMADRV_TransferDone(unsigned int channelId, - bool *done); -Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, - int *remaining); - -/** @} (end addtogroup dmadrv) */ - -#ifdef __cplusplus -} -#endif - -#endif /* __SILICON_LABS_DMADRV_H__ */ +/***************************************************************************//** + * @file + * @brief DMADRV API definition. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __SILICON_LABS_DMADRV_H__ +#define __SILICON_LABS_DMADRV_H__ + +#include "em_device.h" +#include "ecode.h" +#include "sl_enum.h" + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define EMDRV_DMADRV_UDMA +#define EMDRV_DMADRV_DMA_PRESENT +#include "em_dma.h" +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#if (_SILICON_LABS_32B_SERIES > 2) +#define EMDRV_DMADRV_LDMA_S3 +#include "sl_peripheral_ldma.h" +#else +#define EMDRV_DMADRV_DMA_PRESENT +#define EMDRV_DMADRV_LDMA +#include "em_ldma.h" +#endif + +#else +#error "No valid DMA engine defined." +#endif + +#include "dmadrv_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dmadrv + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup dmadrv_error_codes Error Codes + * @{ + ******************************************************************************/ + +#define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. +#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. +#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. +#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. +#define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. +#define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. +#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. + +/** @} (end addtogroup error codes) */ +/***************************************************************************//** + * @brief + * DMADRV transfer completion callback function. + * + * @details + * The callback function is called when a transfer is complete. + * + * @param[in] channel + * The DMA channel number. + * + * @param[in] sequenceNo + * The number of times the callback was called. Useful on long chains of + * linked transfers or on endless ping-pong type transfers. + * + * @param[in] userParam + * Optional user parameter supplied on DMA invocation. + * + * @return + * When doing ping-pong transfers, return true to continue or false to + * stop transfers. + ******************************************************************************/ +typedef bool (*DMADRV_Callback_t)(unsigned int channel, + unsigned int sequenceNo, + void *userParam); + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) + +/// Maximum length of one DMA transfer. +#define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1)) + +/// Peripherals that can trigger UDMA transfers. +#ifdef DOXY_DOC_ONLY +SL_ENUM_GENERIC(DMADRV_Peripheralsignal_t, uint32_t) { +#else +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { +#endif + dmadrvPeripheralSignal_NONE = 0, ///< No peripheral selected for DMA triggering. + #if defined(DMAREQ_ADC0_SCAN) + dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN, ///< Trig on ADC0_SCAN. + #endif + #if defined(DMAREQ_ADC0_SINGLE) + dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE, ///< Trig on ADC0_SINGLE. + #endif + #if defined(DMAREQ_AES_DATARD) + dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD, ///< Trig on AES_DATARD. + #endif + #if defined(DMAREQ_AES_DATAWR) + dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR, ///< Trig on AES_DATAWR. + #endif + #if defined(DMAREQ_AES_KEYWR) + dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR, ///< Trig on AES_KEYWR. + #endif + #if defined(DMAREQ_AES_XORDATAWR) + dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR, ///< Trig on AES_XORDATAWR. + #endif + #if defined(DMAREQ_DAC0_CH0) + dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0, ///< Trig on DAC0_CH0. + #endif + #if defined(DMAREQ_DAC0_CH1) + dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1, ///< Trig on DAC0_CH1. + #endif + #if defined(DMAREQ_EBI_DDEMPTY) + dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY, ///< Trig on EBI_DDEMPTY. + #endif + #if defined(DMAREQ_EBI_PXL0EMPTY) + dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY, ///< Trig on EBI_PXL0EMPTY. + #endif + #if defined(DMAREQ_EBI_PXL1EMPTY) + dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY, ///< Trig on EBI_PXL1EMPTY. + #endif + #if defined(DMAREQ_EBI_PXLFULL) + dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL, ///< Trig on EBI_PXLFULL. + #endif + #if defined(DMAREQ_I2C0_RXDATAV) + dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV, ///< Trig on I2C0_RXDATAV. + #endif + #if defined(DMAREQ_I2C0_TXBL) + dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL, ///< Trig on I2C0_TXBL. + #endif + #if defined(DMAREQ_I2C1_RXDATAV) + dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(DMAREQ_I2C1_TXBL) + dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL, ///< Trig on I2C1_TXBL. + #endif + #if defined(DMAREQ_LESENSE_BUFDATAV) + dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(DMAREQ_LEUART0_RXDATAV) + dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV, ///< Trig on LEUART0_RXDATAV. + #endif + #if defined(DMAREQ_LEUART0_TXBL) + dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL, ///< Trig on LEUART0_TXBL. + #endif + #if defined(DMAREQ_LEUART0_TXEMPTY) + dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY, ///< Trig on LEUART0_TXEMPTY. + #endif + #if defined(DMAREQ_LEUART1_RXDATAV) + dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV, ///< Trig on LEUART1_RXDATAV. + #endif + #if defined(DMAREQ_LEUART1_TXBL) + dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL, ///< Trig on LEUART1_TXBL. + #endif + #if defined(DMAREQ_LEUART1_TXEMPTY) + dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY, ///< Trig on LEUART1_TXEMPTY. + #endif + #if defined(DMAREQ_MSC_WDATA) + dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA, ///< Trig on MSC_WDATA. + #endif + #if defined(DMAREQ_TIMER0_CC0) + dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0, ///< Trig on TIMER0_CC0. + #endif + #if defined(DMAREQ_TIMER0_CC1) + dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1, ///< Trig on TIMER0_CC1. + #endif + #if defined(DMAREQ_TIMER0_CC2) + dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2, ///< Trig on TIMER0_CC2. + #endif + #if defined(DMAREQ_TIMER0_UFOF) + dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF, ///< Trig on TIMER0_UFOF. + #endif + #if defined(DMAREQ_TIMER1_CC0) + dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0, ///< Trig on TIMER1_CC0. + #endif + #if defined(DMAREQ_TIMER1_CC1) + dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1, ///< Trig on TIMER1_CC1. + #endif + #if defined(DMAREQ_TIMER1_CC2) + dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2, ///< Trig on TIMER1_CC2. + #endif + #if defined(DMAREQ_TIMER1_UFOF) + dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF, ///< Trig on TIMER1_UFOF. + #endif + #if defined(DMAREQ_TIMER2_CC0) + dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0, ///< Trig on TIMER2_CC0. + #endif + #if defined(DMAREQ_TIMER2_CC1) + dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1, ///< Trig on TIMER2_CC1. + #endif + #if defined(DMAREQ_TIMER2_CC2) + dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2, ///< Trig on TIMER2_CC2. + #endif + #if defined(DMAREQ_TIMER2_UFOF) + dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF, ///< Trig on TIMER2_UFOF. + #endif + #if defined(DMAREQ_TIMER3_CC0) + dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0, ///< Trig on TIMER3_CC0. + #endif + #if defined(DMAREQ_TIMER3_CC1) + dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1, ///< Trig on TIMER3_CC1. + #endif + #if defined(DMAREQ_TIMER3_CC2) + dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2, ///< Trig on TIMER3_CC2. + #endif + #if defined(DMAREQ_TIMER3_UFOF) + dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF, ///< Trig on TIMER3_UFOF. + #endif + #if defined(DMAREQ_UART0_RXDATAV) + dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV, ///< Trig on UART0_RXDATAV. + #endif + #if defined(DMAREQ_UART0_TXBL) + dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL, ///< Trig on UART0_TXBL. + #endif + #if defined(DMAREQ_UART0_TXEMPTY) + dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY, ///< Trig on UART0_TXEMPTY. + #endif + #if defined(DMAREQ_UART1_RXDATAV) + dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV, ///< Trig on UART1_RXDATAV. + #endif + #if defined(DMAREQ_UART1_TXBL) + dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL, ///< Trig on UART1_TXBL. + #endif + #if defined(DMAREQ_UART1_TXEMPTY) + dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY, ///< Trig on UART1_TXEMPTY. + #endif + #if defined(DMAREQ_USART0_RXDATAV) + dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV, ///< Trig on USART0_RXDATAV. + #endif + #if defined(DMAREQ_USART0_TXBL) + dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL, ///< Trig on USART0_TXBL. + #endif + #if defined(DMAREQ_USART0_TXEMPTY) + dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY, ///< Trig on USART0_TXEMPTY. + #endif + #if defined(DMAREQ_USARTRF0_RXDATAV) + dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV, ///< Trig on USARTRF0_RXDATAV. + #endif + #if defined(DMAREQ_USARTRF0_TXBL) + dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL, ///< Trig on USARTRF0_TXBL. + #endif + #if defined(DMAREQ_USARTRF0_TXEMPTY) + dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY, ///< Trig on USARTRF0_TXEMPTY. + #endif + #if defined(DMAREQ_USARTRF1_RXDATAV) + dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV, ///< Trig on USARTRF1_RXDATAV. + #endif + #if defined(DMAREQ_USARTRF1_TXBL) + dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL, ///< Trig on USARTRF1_TXBL. + #endif + #if defined(DMAREQ_USARTRF1_TXEMPTY) + dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY, ///< Trig on USARTRF1_TXEMPTY. + #endif + #if defined(DMAREQ_USART1_RXDATAV) + dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV, ///< Trig on USART1_RXDATAV. + #endif + #if defined(DMAREQ_USART1_RXDATAVRIGHT) + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,///< Trig on USART1_RXDATAVRIGHT. + #endif + #if defined(DMAREQ_USART1_TXBL) + dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL, ///< Trig on USART1_TXBL. + #endif + #if defined(DMAREQ_USART1_TXBLRIGHT) + dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT, ///< Trig on USART1_TXBLRIGHT. + #endif + #if defined(DMAREQ_USART1_TXEMPTY) + dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(DMAREQ_USART2_RXDATAV) + dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV, ///< Trig on USART2_RXDATAV. + #endif + #if defined(DMAREQ_USART2_RXDATAVRIGHT) + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,///< Trig on USART2_RXDATAVRIGHT. + #endif + #if defined(DMAREQ_USART2_TXBL) + dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL, ///< Trig on USART2_TXBL. + #endif + #if defined(DMAREQ_USART2_TXBLRIGHT) + dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT, ///< Trig on USART2_TXBLRIGHT. + #endif + #if defined(DMAREQ_USART2_TXEMPTY) + dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY, ///< Trig on USART2_TXEMPTY. + #endif +}; + +/// Data size of one UDMA transfer item. +#ifdef DOXY_DOC_ONLY +SL_ENUM(DMADRV_Datasize_t) { +#else +SL_ENUM(DMADRV_DataSize_t) { +#endif + dmadrvDataSize1 = dmaDataSize1, ///< Byte + dmadrvDataSize2 = dmaDataSize2, ///< Halfword + dmadrvDataSize4 = dmaDataSize4 ///< Word +}; + +#endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 ) + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +/// Maximum length of one DMA transfer. +#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) +/// Peripherals that can trigger LDMA transfers. +// TODO CM see if need to add stuff for Rainier XBAR +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { + dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA + dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART3_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_RXBL. + #endif +}; + +#else +/// Peripherals that can trigger LDMA transfers. +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { + dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) + dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) + dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) + dmadrvPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) + dmadrvPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + dmadrvPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0 + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + dmadrvPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1 + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_AGCRSSI) + dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) + dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) + dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) + dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) + dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) + dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) + dmadrvPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) + dmadrvPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) + dmadrvPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) + dmadrvPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) + dmadrvPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) + dmadrvPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + dmadrvPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + dmadrvPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV) + dmadrvPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + dmadrvPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + dmadrvPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) + dmadrvPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) + dmadrvPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) + dmadrvPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) + dmadrvPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) + dmadrvPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG) + dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF) + dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0) + dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1) + dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2) + dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3) + dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4) + dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF) + dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF) + dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) + dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) + dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) + dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) + dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) + dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC3) + dmadrvPeripheralSignal_TIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) + dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) + dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) + dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) + dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) + dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) + dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) + dmadrvPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) + dmadrvPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) + dmadrvPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC3) + dmadrvPeripheralSignal_TIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) + dmadrvPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) + dmadrvPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) + dmadrvPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) + dmadrvPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC3) + dmadrvPeripheralSignal_TIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) + dmadrvPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) + dmadrvPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) + dmadrvPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) + dmadrvPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC3) + dmadrvPeripheralSignal_TIMER4_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) + dmadrvPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) + dmadrvPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) + dmadrvPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) + dmadrvPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC3) + dmadrvPeripheralSignal_TIMER5_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) + dmadrvPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) + dmadrvPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) + dmadrvPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) + dmadrvPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC3) + dmadrvPeripheralSignal_TIMER6_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) + dmadrvPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + dmadrvPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + dmadrvPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + dmadrvPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3) + dmadrvPeripheralSignal_WTIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + dmadrvPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + dmadrvPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + dmadrvPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + dmadrvPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + dmadrvPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + dmadrvPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) + dmadrvPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) + dmadrvPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) + dmadrvPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3) + dmadrvPeripheralSignal_WTIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) + dmadrvPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) + dmadrvPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) + dmadrvPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) + dmadrvPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3) + dmadrvPeripheralSignal_WTIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) + dmadrvPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) + dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) + dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) + dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) + dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) + dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) + dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT) + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT) + dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) + dmadrvPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) + dmadrvPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) + dmadrvPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) + dmadrvPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) + dmadrvPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) + dmadrvPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT) + dmadrvPeripheralSignal_USART5_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) + dmadrvPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT) + dmadrvPeripheralSignal_USART5_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) + dmadrvPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) + dmadrvPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) + dmadrvPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) + dmadrvPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) + dmadrvPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) + dmadrvPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) + dmadrvPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1 ///< Trig on UART1_TXEMPTY. + #endif +}; +#endif + +/// Data size of one LDMA transfer item. +SL_ENUM(DMADRV_DataSize_t) { +#if defined(EMDRV_DMADRV_LDMA_S3) + dmadrvDataSize1 = SL_HAL_LDMA_CTRL_SIZE_BYTE, ///< Byte + dmadrvDataSize2 = SL_HAL_LDMA_CTRL_SIZE_HALF, ///< Halfword + dmadrvDataSize4 = SL_HAL_LDMA_CTRL_SIZE_WORD ///< Word +#else + dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte + dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword + dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word +#endif +}; + +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ + +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, + void *capabilities); +Ecode_t DMADRV_DeInit(void); +Ecode_t DMADRV_FreeChannel(unsigned int channelId); +Ecode_t DMADRV_Init(void); + +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA) +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam); +#endif + +Ecode_t DMADRV_PauseTransfer(unsigned int channelId); +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); +Ecode_t DMADRV_StopTransfer(unsigned int channelId); +Ecode_t DMADRV_TransferActive(unsigned int channelId, + bool *active); +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, + bool *pending); +Ecode_t DMADRV_TransferDone(unsigned int channelId, + bool *done); +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining); + +/** @} (end addtogroup dmadrv) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SILICON_LABS_DMADRV_H__ */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c b/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c index b801b42..2b1ad03 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c @@ -1,1664 +1,1664 @@ -/***************************************************************************//** - * @file - * @brief DMADRV API implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include - -#include "em_device.h" -#include "em_core.h" - -#include "dmadrv.h" - -#if defined(EMDRV_DMADRV_UDMA) -#include "em_cmu.h" -#include "dmactrl.h" -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ - || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) -#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT -#endif - -typedef enum { - dmaDirectionMemToPeripheral, - dmaDirectionPeripheralToMem -} DmaDirection_t; - -typedef enum { - dmaModeBasic, - dmaModePingPong -} DmaMode_t; - -typedef struct { - DMADRV_Callback_t callback; - void *userParam; - unsigned int callbackCount; -#if defined(EMDRV_DMADRV_UDMA) - int length; -#endif - bool allocated; -#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) - DmaMode_t mode; -#endif -} ChTable_t; - -static bool initialized = false; -static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; - -#if defined(EMDRV_DMADRV_UDMA) -static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; -#endif - -#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) -#if defined(EMDRV_DMADRV_LDMA) -const LDMA_TransferCfg_t xferCfgPeripheral = LDMA_TRANSFER_CFG_PERIPHERAL(0); -const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); -const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); - -typedef struct { - LDMA_Descriptor_t desc[2]; -} DmaXfer_t; -#else -const sl_hal_ldma_transfer_config_t xferCfgPeripheral = SL_HAL_LDMA_TRANSFER_CFG_PERIPHERAL(0); -const sl_hal_ldma_descriptor_t m2p = SL_HAL_LDMA_DESCRIPTOR_SINGLE_M2P(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); -const sl_hal_ldma_descriptor_t p2m = SL_HAL_LDMA_DESCRIPTOR_SINGLE_P2M(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); - -typedef struct { - sl_hal_ldma_descriptor_t desc[2]; -} DmaXfer_t; -#endif - -static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; -#endif - -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); - -#if defined(EMDRV_DMADRV_LDMA_S3) -static void LDMA_IRQHandlerDefault(uint8_t chnum); -#endif - -/// @endcond - -/***************************************************************************//** - * @brief - * Allocate (reserve) a DMA channel. - * - * @param[out] channelId - * The channel ID assigned by DMADRV. - * - * @param[in] capabilities - * Not used. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) -{ - unsigned int i; - (void)capabilities; - CORE_DECLARE_IRQ_STATE; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId == NULL ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - CORE_ENTER_ATOMIC(); - for ( i = 0U; i < (unsigned int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - if ( !chTable[i].allocated ) { - *channelId = i; - chTable[i].allocated = true; - chTable[i].callback = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - } - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; -} - -/***************************************************************************//** - * @brief - * Deinitialize DMADRV. - * - * @details - * If DMA channels are not currently allocated, it will disable DMA hardware - * and mask associated interrupts. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_DeInit(void) -{ - int i; - bool inUse; - CORE_DECLARE_IRQ_STATE; - - inUse = false; - - CORE_ENTER_ATOMIC(); - for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - if ( chTable[i].allocated ) { - inUse = true; - break; - } - } - - if ( !inUse ) { -#if defined(EMDRV_DMADRV_UDMA) - NVIC_DisableIRQ(DMA_IRQn); - DMA->IEN = _DMA_IEN_RESETVALUE; - DMA->CONFIG = _DMA_CONFIG_RESETVALUE; - CMU_ClockEnable(cmuClock_DMA, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_DeInit(); -#elif defined(EMDRV_DMADRV_LDMA_S3) - NVIC_DisableIRQ(LDMA_CHNL0_IRQn); - NVIC_DisableIRQ(LDMA_CHNL1_IRQn); - NVIC_DisableIRQ(LDMA_CHNL2_IRQn); - NVIC_DisableIRQ(LDMA_CHNL3_IRQn); - NVIC_DisableIRQ(LDMA_CHNL4_IRQn); - NVIC_DisableIRQ(LDMA_CHNL5_IRQn); - NVIC_DisableIRQ(LDMA_CHNL6_IRQn); - NVIC_DisableIRQ(LDMA_CHNL7_IRQn); - - sl_hal_ldma_reset(); - - // TODO CM add call to the equivalent of CMU_ClockEnable() to disable cmuClock_LDMA. It will require to include the proper S3 CMU header file. -#endif - initialized = false; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_DMADRV_IN_USE; -} - -/***************************************************************************//** - * @brief - * Free an allocated (reserved) DMA channel. - * - * @param[in] channelId - * The channel ID to free. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_FreeChannel(unsigned int channelId) -{ - CORE_DECLARE_IRQ_STATE; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - CORE_ENTER_ATOMIC(); - if ( chTable[channelId].allocated ) { - chTable[channelId].allocated = false; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_DMADRV_ALREADY_FREED; -} - -/***************************************************************************//** - * @brief - * Initialize DMADRV. - * - * @details - * The DMA hardware is initialized. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_Init(void) -{ - int i; - CORE_DECLARE_IRQ_STATE; -#if defined(EMDRV_DMADRV_UDMA) - DMA_Init_TypeDef dmaInit; -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; - dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_config_t dmaInit = SL_HAL_LDMA_INIT_DEFAULT; - dmaInit.num_fixed_priority = EMDRV_DMADRV_DMA_CH_PRIORITY; -#endif - - CORE_ENTER_ATOMIC(); - if ( initialized ) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; - } - initialized = true; - CORE_EXIT_ATOMIC(); - - if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY >= (1 << __NVIC_PRIO_BITS) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - chTable[i].allocated = false; - } - -#if defined(EMDRV_DMADRV_UDMA) - NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - dmaInit.hprot = 0; - dmaInit.controlBlock = dmaControlBlock; - DMA_Init(&dmaInit); -#elif defined(EMDRV_DMADRV_LDMA) - dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; - LDMA_Init(&dmaInit); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_init(&dmaInit); - - NVIC_ClearPendingIRQ(LDMA_CHNL0_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL1_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL2_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL3_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL4_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL5_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL6_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL7_IRQn); - - NVIC_SetPriority(LDMA_CHNL0_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL1_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL2_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL3_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL4_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL5_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL6_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL7_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - - NVIC_EnableIRQ(LDMA_CHNL0_IRQn); - NVIC_EnableIRQ(LDMA_CHNL1_IRQn); - NVIC_EnableIRQ(LDMA_CHNL2_IRQn); - NVIC_EnableIRQ(LDMA_CHNL3_IRQn); - NVIC_EnableIRQ(LDMA_CHNL4_IRQn); - NVIC_EnableIRQ(LDMA_CHNL5_IRQn); - NVIC_EnableIRQ(LDMA_CHNL6_IRQn); - NVIC_EnableIRQ(LDMA_CHNL7_IRQn); - - sl_hal_ldma_enable(); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -#if defined(EMDRV_DMADRV_LDMA) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - * - * @details - * This function is similar to the emlib LDMA function. - * - * @param[in] channelId - * The channel ID to use. - * - * @param[in] transfer - * A DMA transfer configuration data structure. - * - * @param[in] descriptor - * A DMA transfer descriptor, can be an array of descriptors linked together. - * - * @param[in] callback - * An optional callback function for signalling completion. May be NULL if not - * needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. May be NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_LdmaStartTransfer(int channelId, - LDMA_TransferCfg_t *transfer, - LDMA_Descriptor_t *descriptor, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - LDMA_StartTransfer(channelId, transfer, descriptor); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif - -/***************************************************************************//** - * @brief - * Start a memory to a peripheral DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination (peripheral register) memory address. - * - * @param[in] src - * A source memory address. - * - * @param[in] srcInc - * Set to true to enable source address increment (increments according to - * @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModeBasic, - dmaDirectionMemToPeripheral, - channelId, - peripheralSignal, - dst, - src, - NULL, - srcInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a memory to a peripheral ping-pong DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination (peripheral register) memory address. - * - * @param[in] src0 - * A source memory address of the first (ping) buffer. - * - * @param[in] src1 - * A source memory address of the second (pong) buffer. - * - * @param[in] srcInc - * Set to true to enable source address increment (increments according to - * @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_MemoryPeripheralPingPong( - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src0, - void *src1, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModePingPong, - dmaDirectionMemToPeripheral, - channelId, - peripheralSignal, - dst, - src0, - src1, - srcInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a peripheral to memory DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination memory address. - * - * @param[in] src - * A source memory (peripheral register) address. - * - * @param[in] dstInc - * Set to true to enable destination address increment (increments according - * to @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModeBasic, - dmaDirectionPeripheralToMem, - channelId, - peripheralSignal, - dst, - src, - NULL, - dstInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a peripheral to memory ping-pong DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst0 - * A destination memory address of the first (ping) buffer. - * - * @param[in] dst1 - * A destination memory address of the second (pong) buffer. - * - * @param[in] src - * A source memory (peripheral register) address. - * - * @param[in] dstInc - * Set to true to enable destination address increment (increments according - * to @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PeripheralMemoryPingPong( - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst0, - void *dst1, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModePingPong, - dmaDirectionPeripheralToMem, - channelId, - peripheralSignal, - dst0, - dst1, - src, - dstInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Pause an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to pause. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PauseTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelRequestEnable(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_EnableChannelRequest(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_disable_channel_request(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Resume an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to resume. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelRequestEnable(channelId, true); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_EnableChannelRequest(channelId, true); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_enable_channel_request(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Stop an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to stop. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_StopTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelEnable(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_StopTransfer(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_stop_transfer(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer is running. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] active - * True if transfer is running, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (active == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - if ( DMA_ChannelEnabled(channelId) ) -#elif defined(EMDRV_DMADRV_LDMA) - if ( LDMA_ChannelEnabled(channelId) ) -#elif defined(EMDRV_DMADRV_LDMA_S3) - if ( sl_hal_ldma_channel_is_enabled(channelId) ) -#endif - { - *active = true; - } else { - *active = false; - } - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer complete is pending. - * - * @details - * Will check the channel interrupt flag. This assumes that the DMA is configured - * to give a completion interrupt. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] pending - * True if a transfer complete is pending, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (pending == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - if ( DMA->IF & (1 << channelId) ) -#elif defined(EMDRV_DMADRV_LDMA) - if ( LDMA->IF & (1 << channelId) ) -#elif defined(EMDRV_DMADRV_LDMA_S3) - if ( sl_hal_ldma_get_interrupts() & (1 << channelId) ) -#endif - { - *pending = true; - } else { - *pending = false; - } - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer has completed. - * - * @note - * This function should be used in a polled environment. - * Will only work reliably for transfers NOT using the completion interrupt. - * On UDMA, it will only work on basic transfers on the primary channel. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] done - * True if a transfer has completed, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) -{ -#if defined(EMDRV_DMADRV_UDMA) - uint32_t remaining, iflag; -#endif - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (done == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - CORE_ATOMIC_SECTION( - /* This works for primary channel only ! */ - remaining = (dmaControlBlock[channelId].CTRL - & _DMA_CTRL_N_MINUS_1_MASK) - >> _DMA_CTRL_N_MINUS_1_SHIFT; - iflag = DMA->IF; - ) - - if ( (remaining == 0) && (iflag & (1 << channelId)) ) { - *done = true; - } else { - *done = false; - } -#elif defined(EMDRV_DMADRV_LDMA) - *done = LDMA_TransferDone(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - *done = sl_hal_ldma_transfer_is_done(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Get number of items remaining in a transfer. - * - * @note - * This function does not take into account that a DMA transfer with - * a chain of linked transfers might be ongoing. It will only check the - * count for the current transfer. - * On UDMA, it will only work on the primary channel. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] remaining - * A number of items remaining in the transfer. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, - int *remaining) -{ -#if defined(EMDRV_DMADRV_UDMA) - uint32_t remain, iflag; -#endif - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (remaining == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - CORE_ATOMIC_SECTION( - /* This works for the primary channel only ! */ - remain = (dmaControlBlock[channelId].CTRL - & _DMA_CTRL_N_MINUS_1_MASK) - >> _DMA_CTRL_N_MINUS_1_SHIFT; - iflag = DMA->IF; - ) - - if ( (remain == 0) && (iflag & (1 << channelId)) ) { - *remaining = 0; - } else { - *remaining = 1 + remain; - } -#elif defined(EMDRV_DMADRV_LDMA) - *remaining = LDMA_TransferRemainingCount(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - *remaining = sl_hal_ldma_transfer_remaining_count(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(EMDRV_DMADRV_LDMA) -/***************************************************************************//** - * @brief - * An interrupt handler for LDMA. - ******************************************************************************/ -void LDMA_IRQHandler(void) -{ - bool stop; - ChTable_t *ch; - uint32_t pending, chnum, chmask; - - /* Get all pending and enabled interrupts. */ - pending = LDMA->IF; - pending &= LDMA->IEN; - - /* Check for LDMA error. */ - if ( pending & LDMA_IF_ERROR ) { - /* Loop to enable debugger to see what has happened. */ - while (true) { - /* Wait forever. */ - } - } - - /* Iterate over all LDMA channels. */ - for ( chnum = 0, chmask = 1; - chnum < EMDRV_DMADRV_DMA_CH_COUNT; - chnum++, chmask <<= 1 ) { - if ( pending & chmask ) { - /* Clear the interrupt flag. */ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chmask; -#else - LDMA->IFC = chmask; -#endif - - ch = &chTable[chnum]; - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); - - if ( (ch->mode == dmaModePingPong) && stop ) { - dmaXfer[chnum].desc[0].xfer.link = 0; - dmaXfer[chnum].desc[1].xfer.link = 0; - } - } - } - } -} -#endif /* defined( EMDRV_DMADRV_LDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA_S3) -/***************************************************************************//** - * @brief - * Default interrupt handler for LDMA common to all interrupt channel lines. - * - * @param[in] chnum - * The channel ID responsible for the interrupt signal trigger. - ******************************************************************************/ -static void LDMA_IRQHandlerDefault(uint8_t chnum) -{ - bool stop; - ChTable_t *ch; - uint32_t pending; - uint32_t chmask; - - /* Get all pending and enabled interrupts. */ - pending = sl_hal_ldma_get_enabled_interrupts(); - - /* Check for LDMA error. */ - if ( pending & (LDMA_IF_ERROR0 << chnum) ) { - /* Loop to enable debugger to see what has happened. */ - while (true) { - /* Wait forever. */ - } - } - - chmask = 1 << chnum; - if ( pending & chmask ) { - /* Clear the interrupt flag. */ - sl_hal_ldma_clear_interrupts(chmask); - - /* Callback called if it was provided for the given channel. */ - ch = &chTable[chnum]; - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); - - /* Continue or not a ping-pong transfer. */ - if ( (ch->mode == dmaModePingPong) && stop ) { - dmaXfer[chnum].desc[0].xfer.link = 0; - dmaXfer[chnum].desc[1].xfer.link = 0; - } - } - } -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 0. - ******************************************************************************/ -void LDMA_CHNL0_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(0); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 1. - ******************************************************************************/ -void LDMA_CHNL1_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(1); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 2. - ******************************************************************************/ -void LDMA_CHNL2_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(2); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 3. - ******************************************************************************/ -void LDMA_CHNL3_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(3); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 4. - ******************************************************************************/ -void LDMA_CHNL4_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(4); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 5. - ******************************************************************************/ -void LDMA_CHNL5_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(5); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 6. - ******************************************************************************/ -void LDMA_CHNL6_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(6); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 7. - ******************************************************************************/ -void LDMA_CHNL7_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(7); -} - -#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * A callback function for UDMA basic transfers. - ******************************************************************************/ -static void DmaBasicCallback(unsigned int channel, bool primary, void *user) -{ - ChTable_t *ch = &chTable[channel]; - (void)user; - (void)primary; - - if ( ch->callback != NULL ) { - ch->callbackCount++; - ch->callback(channel, ch->callbackCount, ch->userParam); - } -} -#endif - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * A callback function for UDMA ping-pong transfers. - ******************************************************************************/ -static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) -{ - bool stop = true; - ChTable_t *ch = &chTable[channel]; - - (void)user; - - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(channel, ch->callbackCount, ch->userParam); - } - - DMA_RefreshPingPong(channel, - primary, - false, - NULL, - NULL, - ch->length - 1, - stop); -} -#endif - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * Start a UDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - DMA_CfgChannel_TypeDef chCfg; - DMA_CfgDescr_TypeDef descrCfg; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - /* Se tup the interrupt callback routine. */ - if ( mode == dmaModeBasic ) { - dmaCallBack[channelId].cbFunc = DmaBasicCallback; - } else { - dmaCallBack[channelId].cbFunc = DmaPingPongCallback; - } - dmaCallBack[channelId].userPtr = NULL; - - /* Set up the channel */ - chCfg.highPri = false; /* Can't use hi pri with peripherals. */ - - /* Whether the interrupt is needed. */ - if ( (callback != NULL) || (mode == dmaModePingPong) ) { - chCfg.enableInt = true; - } else { - chCfg.enableInt = false; - } - chCfg.select = peripheralSignal; - chCfg.cb = &dmaCallBack[channelId]; - DMA_CfgChannel(channelId, &chCfg); - - /* Set up the channel descriptor. */ - if ( direction == dmaDirectionMemToPeripheral ) { - if ( bufInc ) { - if ( size == dmadrvDataSize1 ) { - descrCfg.srcInc = dmaDataInc1; - } else if ( size == dmadrvDataSize2 ) { - descrCfg.srcInc = dmaDataInc2; - } else { /* dmadrvDataSize4 */ - descrCfg.srcInc = dmaDataInc4; - } - } else { - descrCfg.srcInc = dmaDataIncNone; - } - descrCfg.dstInc = dmaDataIncNone; - } else { - if ( bufInc ) { - if ( size == dmadrvDataSize1 ) { - descrCfg.dstInc = dmaDataInc1; - } else if ( size == dmadrvDataSize2 ) { - descrCfg.dstInc = dmaDataInc2; - } else { /* dmadrvDataSize4 */ - descrCfg.dstInc = dmaDataInc4; - } - } else { - descrCfg.dstInc = dmaDataIncNone; - } - descrCfg.srcInc = dmaDataIncNone; - } - descrCfg.size = (DMA_DataSize_TypeDef)size; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr(channelId, true, &descrCfg); - if ( mode == dmaModePingPong ) { - DMA_CfgDescr(channelId, false, &descrCfg); - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->length = len; - - DMA->IFC = 1 << channelId; - - /* Start the DMA cycle. */ - if ( mode == dmaModeBasic ) { - DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); - } else { - if ( direction == dmaDirectionMemToPeripheral ) { - DMA_ActivatePingPong(channelId, - false, - buf0, /* dest */ - buf1, /* src */ - len - 1, - buf0, /* dest */ - buf2, /* src */ - len - 1); - } else { - DMA_ActivatePingPong(channelId, - false, - buf0, /* dest */ - buf2, /* src */ - len - 1, - buf1, /* dest */ - buf2, /* src */ - len - 1); - } - } - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_UDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - LDMA_TransferCfg_t xfer; - LDMA_Descriptor_t *desc; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - xfer = xferCfgPeripheral; - desc = &dmaXfer[channelId].desc[0]; - - if ( direction == dmaDirectionMemToPeripheral ) { - *desc = m2p; - if ( !bufInc ) { - desc->xfer.srcInc = ldmaCtrlSrcIncNone; - } - } else { - *desc = p2m; - if ( !bufInc ) { - desc->xfer.dstInc = ldmaCtrlDstIncNone; - } - } - - xfer.ldmaReqSel = peripheralSignal; - desc->xfer.xferCnt = len - 1; - desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; - desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; - desc->xfer.size = size; - - if ( mode == dmaModePingPong ) { - desc->xfer.linkMode = ldmaLinkModeRel; - desc->xfer.link = 1; - desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ - - /* Set the "pong" descriptor equal to the "ping" descriptor. */ - dmaXfer[channelId].desc[1] = *desc; - /* Refer to the "ping" descriptor. */ - dmaXfer[channelId].desc[1].xfer.linkAddr = -4; - dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; - - if ( direction == dmaDirectionPeripheralToMem ) { - dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; - desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; - } - } - - /* Whether an interrupt is needed. */ - if ( (callback == NULL) && (mode == dmaModeBasic) ) { - desc->xfer.doneIfs = 0; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->mode = mode; - - LDMA_StartTransfer(channelId, &xfer, desc); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_LDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA_S3) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - sl_hal_ldma_transfer_config_t xfer; - sl_hal_ldma_descriptor_t *desc; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - xfer = xferCfgPeripheral; - desc = &dmaXfer[channelId].desc[0]; - - if ( direction == dmaDirectionMemToPeripheral ) { - *desc = m2p; - if ( !bufInc ) { - desc->xfer.src_inc = SL_HAL_LDMA_CTRL_SRC_INC_NONE; - } - } else { - *desc = p2m; - if ( !bufInc ) { - desc->xfer.dst_inc = SL_HAL_LDMA_CTRL_DST_INC_NONE; - } - } - - xfer.request_sel = peripheralSignal; - desc->xfer.xfer_count = len - 1; - desc->xfer.dst_addr = (uint32_t)(uint8_t *)buf0; - desc->xfer.src_addr = (uint32_t)(uint8_t *)buf1; - desc->xfer.size = size; - - if ( mode == dmaModePingPong ) { - desc->xfer.link_mode = SL_HAL_LDMA_LINK_MODE_REL; - desc->xfer.link = 1; - desc->xfer.link_addr = 4; /* Refer to the "pong" descriptor. */ - - /* Set the "pong" descriptor equal to the "ping" descriptor. */ - dmaXfer[channelId].desc[1] = *desc; - /* Refer to the "ping" descriptor. */ - dmaXfer[channelId].desc[1].xfer.link_addr = -4; - dmaXfer[channelId].desc[1].xfer.src_addr = (uint32_t)(uint8_t *)buf2; - - if ( direction == dmaDirectionPeripheralToMem ) { - dmaXfer[channelId].desc[1].xfer.dst_addr = (uint32_t)(uint8_t *)buf1; - desc->xfer.src_addr = (uint32_t)(uint8_t *)buf2; - } - } - - /* Whether an interrupt is needed. */ - if ( (callback == NULL) && (mode == dmaModeBasic) ) { - desc->xfer.done_ifs = 0; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->mode = mode; - - sl_hal_ldma_init_transfer(channelId, &xfer, desc); - sl_hal_ldma_start_transfer(channelId); - sl_hal_ldma_enable_interrupts((0x1UL << channelId)); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ - -/// @endcond - -// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** -/// @addtogroup dmadrv DMADRV - DMA Driver -/// @brief Direct Memory Access Driver -/// @{ -/// -/// @details -/// -/// -/// @n @section dmadrv_intro Introduction -/// -/// The DMADRV driver supports writing code using DMA which will work -/// regardless of the type of the DMA controller on the underlying microcontroller. -/// Additionally, DMA can be used in several modules that are -/// completely unaware of each other. -/// The driver does not preclude use of the native emlib API of the underlying -/// DMA controller. On the contrary, it will often result in more efficient -/// code and is necessary for complex DMA operations. The housekeeping -/// functions of this driver are valuable even in this use-case. -/// -/// The dmadrv.c and dmadrv.h source files are in the -/// emdrv/dmadrv folder. -/// -/// @note DMA transfer completion callback functions are called from within the -/// DMA interrupt handler. -/// -/// @n @section dmadrv_conf Configuration Options -/// -/// Some properties of the DMADRV driver are compile-time configurable. These -/// properties are stored in a file named dmadrv_config.h. A template for this -/// file, containing default values, is in the emdrv/config folder. -/// Currently the configuration options are as follows: -/// @li The interrupt priority of the DMA peripheral. -/// @li A number of DMA channels to support. -/// @li Use the native emlib API belonging to the underlying DMA hardware in -/// combination with the DMADRV API. -/// -/// Both configuration options will help reduce the driver's RAM footprint. -/// -/// To configure DMADRV, provide a custom configuration file. This is an -/// example dmadrv_config.h file: -/// @code{.c} -/// #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ -/// #define __SILICON_LABS_DMADRV_CONFIG_H__ -/// -/// // DMADRV DMA interrupt priority configuration option. -/// // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. -/// #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 -/// -/// // DMADRV channel count configuration option. -/// // A number of DMA channels to support. A lower DMA channel count will reduce -/// // RAM footprint. -/// #define EMDRV_DMADRV_DMA_CH_COUNT 4 -/// -/// #endif -/// @endcode -/// -/// @n @section dmadrv_api The API -/// -/// This section contains brief descriptions of the API functions. -/// For more information about input and output parameters and return values, -/// click on the hyperlinked function names. Most functions return an error -/// code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, -/// see @ref ecode and @ref dmadrv_error_codes for other error codes. -/// -/// The application code must include @em dmadrv.h header file. -/// -/// @ref DMADRV_Init(), @ref DMADRV_DeInit() @n -/// These functions initialize or deinitialize the DMADRV driver. Typically, -/// DMADRV_Init() is called once in the startup code. -/// -/// @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n -/// DMA channel reserve and release functions. It is recommended that -/// application code check that DMADRV_AllocateChannel() -/// returns ECODE_EMDRV_DMADRV_OK before starting a DMA -/// transfer. -/// -/// @ref DMADRV_MemoryPeripheral() @n -/// Start a DMA transfer from memory to a peripheral. -/// -/// @ref DMADRV_PeripheralMemory() @n -/// Start a DMA transfer from a peripheral to memory. -/// -/// @ref DMADRV_MemoryPeripheralPingPong() @n -/// Start a DMA ping-pong transfer from memory to a peripheral. -/// -/// @ref DMADRV_PeripheralMemoryPingPong() @n -/// Start a DMA ping-pong transfer from a peripheral to memory. -/// -/// @ref DMADRV_LdmaStartTransfer() @n -/// Start a DMA transfer on an LDMA controller. -/// -/// @ref DMADRV_StopTransfer() @n -/// Stop an ongoing DMA transfer. -/// -/// @ref DMADRV_TransferActive() @n -/// Check if a transfer is ongoing. -/// -/// @ref DMADRV_TransferCompletePending() @n -/// Check if a transfer completion is pending. -/// -/// @ref DMADRV_TransferDone() @n -/// Check if a transfer has completed. -/// -/// @ref DMADRV_TransferRemainingCount() @n -/// Get number of items remaining in a transfer. -/// -/// @n @section dmadrv_example Example -/// Transfer a text string to USART1. -/// @code{.c} -/// #include "dmadrv.h" -/// -/// char str[] = "Hello DMA !"; -/// unsigned int channel; -/// -/// int main( void ) -/// { -/// // Initialize DMA. -/// DMADRV_Init(); -/// -/// // Request a DMA channel. -/// DMADRV_AllocateChannel( &channel, NULL ); -/// -/// // Start the DMA transfer. -/// DMADRV_MemoryPeripheral( channel, -/// dmadrvPeripheralSignal_USART1_TXBL, -/// (void*)&(USART1->TXDATA), -/// str, -/// true, -/// sizeof( str ), -/// dmadrvDataSize1, -/// NULL, -/// NULL ); -/// -/// return 0; -/// } -/// @endcode -/// -/// @} end group dmadrv ******************************************************** +/***************************************************************************//** + * @file + * @brief DMADRV API implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include + +#include "em_device.h" +#include "em_core.h" + +#include "dmadrv.h" + +#if defined(EMDRV_DMADRV_UDMA) +#include "em_cmu.h" +#include "dmactrl.h" +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ + || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) +#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT +#endif + +typedef enum { + dmaDirectionMemToPeripheral, + dmaDirectionPeripheralToMem +} DmaDirection_t; + +typedef enum { + dmaModeBasic, + dmaModePingPong +} DmaMode_t; + +typedef struct { + DMADRV_Callback_t callback; + void *userParam; + unsigned int callbackCount; +#if defined(EMDRV_DMADRV_UDMA) + int length; +#endif + bool allocated; +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) + DmaMode_t mode; +#endif +} ChTable_t; + +static bool initialized = false; +static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; + +#if defined(EMDRV_DMADRV_UDMA) +static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) +#if defined(EMDRV_DMADRV_LDMA) +const LDMA_TransferCfg_t xferCfgPeripheral = LDMA_TRANSFER_CFG_PERIPHERAL(0); +const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); +const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); + +typedef struct { + LDMA_Descriptor_t desc[2]; +} DmaXfer_t; +#else +const sl_hal_ldma_transfer_config_t xferCfgPeripheral = SL_HAL_LDMA_TRANSFER_CFG_PERIPHERAL(0); +const sl_hal_ldma_descriptor_t m2p = SL_HAL_LDMA_DESCRIPTOR_SINGLE_M2P(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); +const sl_hal_ldma_descriptor_t p2m = SL_HAL_LDMA_DESCRIPTOR_SINGLE_P2M(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); + +typedef struct { + sl_hal_ldma_descriptor_t desc[2]; +} DmaXfer_t; +#endif + +static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA_S3) +static void LDMA_IRQHandlerDefault(uint8_t chnum); +#endif + +/// @endcond + +/***************************************************************************//** + * @brief + * Allocate (reserve) a DMA channel. + * + * @param[out] channelId + * The channel ID assigned by DMADRV. + * + * @param[in] capabilities + * Not used. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) +{ + unsigned int i; + (void)capabilities; + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId == NULL ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + for ( i = 0U; i < (unsigned int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( !chTable[i].allocated ) { + *channelId = i; + chTable[i].allocated = true; + chTable[i].callback = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + } + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; +} + +/***************************************************************************//** + * @brief + * Deinitialize DMADRV. + * + * @details + * If DMA channels are not currently allocated, it will disable DMA hardware + * and mask associated interrupts. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_DeInit(void) +{ + int i; + bool inUse; + CORE_DECLARE_IRQ_STATE; + + inUse = false; + + CORE_ENTER_ATOMIC(); + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( chTable[i].allocated ) { + inUse = true; + break; + } + } + + if ( !inUse ) { +#if defined(EMDRV_DMADRV_UDMA) + NVIC_DisableIRQ(DMA_IRQn); + DMA->IEN = _DMA_IEN_RESETVALUE; + DMA->CONFIG = _DMA_CONFIG_RESETVALUE; + CMU_ClockEnable(cmuClock_DMA, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_DeInit(); +#elif defined(EMDRV_DMADRV_LDMA_S3) + NVIC_DisableIRQ(LDMA_CHNL0_IRQn); + NVIC_DisableIRQ(LDMA_CHNL1_IRQn); + NVIC_DisableIRQ(LDMA_CHNL2_IRQn); + NVIC_DisableIRQ(LDMA_CHNL3_IRQn); + NVIC_DisableIRQ(LDMA_CHNL4_IRQn); + NVIC_DisableIRQ(LDMA_CHNL5_IRQn); + NVIC_DisableIRQ(LDMA_CHNL6_IRQn); + NVIC_DisableIRQ(LDMA_CHNL7_IRQn); + + sl_hal_ldma_reset(); + + // TODO CM add call to the equivalent of CMU_ClockEnable() to disable cmuClock_LDMA. It will require to include the proper S3 CMU header file. +#endif + initialized = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_IN_USE; +} + +/***************************************************************************//** + * @brief + * Free an allocated (reserved) DMA channel. + * + * @param[in] channelId + * The channel ID to free. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_FreeChannel(unsigned int channelId) +{ + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + if ( chTable[channelId].allocated ) { + chTable[channelId].allocated = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_ALREADY_FREED; +} + +/***************************************************************************//** + * @brief + * Initialize DMADRV. + * + * @details + * The DMA hardware is initialized. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_Init(void) +{ + int i; + CORE_DECLARE_IRQ_STATE; +#if defined(EMDRV_DMADRV_UDMA) + DMA_Init_TypeDef dmaInit; +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; + dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_config_t dmaInit = SL_HAL_LDMA_INIT_DEFAULT; + dmaInit.num_fixed_priority = EMDRV_DMADRV_DMA_CH_PRIORITY; +#endif + + CORE_ENTER_ATOMIC(); + if ( initialized ) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; + } + initialized = true; + CORE_EXIT_ATOMIC(); + + if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY >= (1 << __NVIC_PRIO_BITS) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + chTable[i].allocated = false; + } + +#if defined(EMDRV_DMADRV_UDMA) + NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + dmaInit.hprot = 0; + dmaInit.controlBlock = dmaControlBlock; + DMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA) + dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; + LDMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_init(&dmaInit); + + NVIC_ClearPendingIRQ(LDMA_CHNL0_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL1_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL2_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL3_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL4_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL5_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL6_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL7_IRQn); + + NVIC_SetPriority(LDMA_CHNL0_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL1_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL2_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL3_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL4_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL5_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL6_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL7_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + + NVIC_EnableIRQ(LDMA_CHNL0_IRQn); + NVIC_EnableIRQ(LDMA_CHNL1_IRQn); + NVIC_EnableIRQ(LDMA_CHNL2_IRQn); + NVIC_EnableIRQ(LDMA_CHNL3_IRQn); + NVIC_EnableIRQ(LDMA_CHNL4_IRQn); + NVIC_EnableIRQ(LDMA_CHNL5_IRQn); + NVIC_EnableIRQ(LDMA_CHNL6_IRQn); + NVIC_EnableIRQ(LDMA_CHNL7_IRQn); + + sl_hal_ldma_enable(); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +#if defined(EMDRV_DMADRV_LDMA) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + * + * @details + * This function is similar to the emlib LDMA function. + * + * @param[in] channelId + * The channel ID to use. + * + * @param[in] transfer + * A DMA transfer configuration data structure. + * + * @param[in] descriptor + * A DMA transfer descriptor, can be an array of descriptors linked together. + * + * @param[in] callback + * An optional callback function for signalling completion. May be NULL if not + * needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. May be NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + LDMA_StartTransfer(channelId, transfer, descriptor); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src + * A source memory address. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src, + NULL, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src0 + * A source memory address of the first (ping) buffer. + * + * @param[in] src1 + * A source memory address of the second (pong) buffer. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheralPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src0, + src1, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination memory address. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst, + src, + NULL, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst0 + * A destination memory address of the first (ping) buffer. + * + * @param[in] dst1 + * A destination memory address of the second (pong) buffer. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemoryPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst0, + dst1, + src, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Pause an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to pause. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PauseTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_disable_channel_request(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Resume an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to resume. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_enable_channel_request(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Stop an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to stop. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_StopTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_StopTransfer(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_stop_transfer(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer is running. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] active + * True if transfer is running, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (active == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_channel_is_enabled(channelId) ) +#endif + { + *active = true; + } else { + *active = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer complete is pending. + * + * @details + * Will check the channel interrupt flag. This assumes that the DMA is configured + * to give a completion interrupt. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] pending + * True if a transfer complete is pending, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (pending == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_get_interrupts() & (1 << channelId) ) +#endif + { + *pending = true; + } else { + *pending = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer has completed. + * + * @note + * This function should be used in a polled environment. + * Will only work reliably for transfers NOT using the completion interrupt. + * On UDMA, it will only work on basic transfers on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] done + * True if a transfer has completed, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remaining, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (done == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for primary channel only ! */ + remaining = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remaining == 0) && (iflag & (1 << channelId)) ) { + *done = true; + } else { + *done = false; + } +#elif defined(EMDRV_DMADRV_LDMA) + *done = LDMA_TransferDone(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *done = sl_hal_ldma_transfer_is_done(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Get number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * On UDMA, it will only work on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] remaining + * A number of items remaining in the transfer. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remain, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (remaining == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for the primary channel only ! */ + remain = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remain == 0) && (iflag & (1 << channelId)) ) { + *remaining = 0; + } else { + *remaining = 1 + remain; + } +#elif defined(EMDRV_DMADRV_LDMA) + *remaining = LDMA_TransferRemainingCount(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *remaining = sl_hal_ldma_transfer_remaining_count(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * An interrupt handler for LDMA. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + bool stop; + ChTable_t *ch; + uint32_t pending, chnum, chmask; + + /* Get all pending and enabled interrupts. */ + pending = LDMA->IF; + pending &= LDMA->IEN; + + /* Check for LDMA error. */ + if ( pending & LDMA_IF_ERROR ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + /* Iterate over all LDMA channels. */ + for ( chnum = 0, chmask = 1; + chnum < EMDRV_DMADRV_DMA_CH_COUNT; + chnum++, chmask <<= 1 ) { + if ( pending & chmask ) { + /* Clear the interrupt flag. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chmask; +#else + LDMA->IFC = chmask; +#endif + + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } + } +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Default interrupt handler for LDMA common to all interrupt channel lines. + * + * @param[in] chnum + * The channel ID responsible for the interrupt signal trigger. + ******************************************************************************/ +static void LDMA_IRQHandlerDefault(uint8_t chnum) +{ + bool stop; + ChTable_t *ch; + uint32_t pending; + uint32_t chmask; + + /* Get all pending and enabled interrupts. */ + pending = sl_hal_ldma_get_enabled_interrupts(); + + /* Check for LDMA error. */ + if ( pending & (LDMA_IF_ERROR0 << chnum) ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + chmask = 1 << chnum; + if ( pending & chmask ) { + /* Clear the interrupt flag. */ + sl_hal_ldma_clear_interrupts(chmask); + + /* Callback called if it was provided for the given channel. */ + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + /* Continue or not a ping-pong transfer. */ + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 0. + ******************************************************************************/ +void LDMA_CHNL0_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(0); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 1. + ******************************************************************************/ +void LDMA_CHNL1_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(1); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 2. + ******************************************************************************/ +void LDMA_CHNL2_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(2); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 3. + ******************************************************************************/ +void LDMA_CHNL3_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(3); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 4. + ******************************************************************************/ +void LDMA_CHNL4_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(4); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 5. + ******************************************************************************/ +void LDMA_CHNL5_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(5); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 6. + ******************************************************************************/ +void LDMA_CHNL6_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(6); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 7. + ******************************************************************************/ +void LDMA_CHNL7_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(7); +} + +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA basic transfers. + ******************************************************************************/ +static void DmaBasicCallback(unsigned int channel, bool primary, void *user) +{ + ChTable_t *ch = &chTable[channel]; + (void)user; + (void)primary; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + ch->callback(channel, ch->callbackCount, ch->userParam); + } +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA ping-pong transfers. + ******************************************************************************/ +static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) +{ + bool stop = true; + ChTable_t *ch = &chTable[channel]; + + (void)user; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(channel, ch->callbackCount, ch->userParam); + } + + DMA_RefreshPingPong(channel, + primary, + false, + NULL, + NULL, + ch->length - 1, + stop); +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * Start a UDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + DMA_CfgChannel_TypeDef chCfg; + DMA_CfgDescr_TypeDef descrCfg; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + /* Se tup the interrupt callback routine. */ + if ( mode == dmaModeBasic ) { + dmaCallBack[channelId].cbFunc = DmaBasicCallback; + } else { + dmaCallBack[channelId].cbFunc = DmaPingPongCallback; + } + dmaCallBack[channelId].userPtr = NULL; + + /* Set up the channel */ + chCfg.highPri = false; /* Can't use hi pri with peripherals. */ + + /* Whether the interrupt is needed. */ + if ( (callback != NULL) || (mode == dmaModePingPong) ) { + chCfg.enableInt = true; + } else { + chCfg.enableInt = false; + } + chCfg.select = peripheralSignal; + chCfg.cb = &dmaCallBack[channelId]; + DMA_CfgChannel(channelId, &chCfg); + + /* Set up the channel descriptor. */ + if ( direction == dmaDirectionMemToPeripheral ) { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.srcInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.srcInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.srcInc = dmaDataInc4; + } + } else { + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.dstInc = dmaDataIncNone; + } else { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.dstInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.dstInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.dstInc = dmaDataInc4; + } + } else { + descrCfg.dstInc = dmaDataIncNone; + } + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.size = (DMA_DataSize_TypeDef)size; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr(channelId, true, &descrCfg); + if ( mode == dmaModePingPong ) { + DMA_CfgDescr(channelId, false, &descrCfg); + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->length = len; + + DMA->IFC = 1 << channelId; + + /* Start the DMA cycle. */ + if ( mode == dmaModeBasic ) { + DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); + } else { + if ( direction == dmaDirectionMemToPeripheral ) { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf1, /* src */ + len - 1, + buf0, /* dest */ + buf2, /* src */ + len - 1); + } else { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf2, /* src */ + len - 1, + buf1, /* dest */ + buf2, /* src */ + len - 1); + } + } + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_UDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + LDMA_TransferCfg_t xfer; + LDMA_Descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.srcInc = ldmaCtrlSrcIncNone; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dstInc = ldmaCtrlDstIncNone; + } + } + + xfer.ldmaReqSel = peripheralSignal; + desc->xfer.xferCnt = len - 1; + desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.linkMode = ldmaLinkModeRel; + desc->xfer.link = 1; + desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.linkAddr = -4; + dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.doneIfs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + LDMA_StartTransfer(channelId, &xfer, desc); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + sl_hal_ldma_transfer_config_t xfer; + sl_hal_ldma_descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.src_inc = SL_HAL_LDMA_CTRL_SRC_INC_NONE; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dst_inc = SL_HAL_LDMA_CTRL_DST_INC_NONE; + } + } + + xfer.request_sel = peripheralSignal; + desc->xfer.xfer_count = len - 1; + desc->xfer.dst_addr = (uint32_t)(uint8_t *)buf0; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.link_mode = SL_HAL_LDMA_LINK_MODE_REL; + desc->xfer.link = 1; + desc->xfer.link_addr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.link_addr = -4; + dmaXfer[channelId].desc[1].xfer.src_addr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dst_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.done_ifs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + sl_hal_ldma_init_transfer(channelId, &xfer, desc); + sl_hal_ldma_start_transfer(channelId); + sl_hal_ldma_enable_interrupts((0x1UL << channelId)); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +/// @endcond + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup dmadrv DMADRV - DMA Driver +/// @brief Direct Memory Access Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section dmadrv_intro Introduction +/// +/// The DMADRV driver supports writing code using DMA which will work +/// regardless of the type of the DMA controller on the underlying microcontroller. +/// Additionally, DMA can be used in several modules that are +/// completely unaware of each other. +/// The driver does not preclude use of the native emlib API of the underlying +/// DMA controller. On the contrary, it will often result in more efficient +/// code and is necessary for complex DMA operations. The housekeeping +/// functions of this driver are valuable even in this use-case. +/// +/// The dmadrv.c and dmadrv.h source files are in the +/// emdrv/dmadrv folder. +/// +/// @note DMA transfer completion callback functions are called from within the +/// DMA interrupt handler. +/// +/// @n @section dmadrv_conf Configuration Options +/// +/// Some properties of the DMADRV driver are compile-time configurable. These +/// properties are stored in a file named dmadrv_config.h. A template for this +/// file, containing default values, is in the emdrv/config folder. +/// Currently the configuration options are as follows: +/// @li The interrupt priority of the DMA peripheral. +/// @li A number of DMA channels to support. +/// @li Use the native emlib API belonging to the underlying DMA hardware in +/// combination with the DMADRV API. +/// +/// Both configuration options will help reduce the driver's RAM footprint. +/// +/// To configure DMADRV, provide a custom configuration file. This is an +/// example dmadrv_config.h file: +/// @code{.c} +/// #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ +/// #define __SILICON_LABS_DMADRV_CONFIG_H__ +/// +/// // DMADRV DMA interrupt priority configuration option. +/// // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. +/// #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 +/// +/// // DMADRV channel count configuration option. +/// // A number of DMA channels to support. A lower DMA channel count will reduce +/// // RAM footprint. +/// #define EMDRV_DMADRV_DMA_CH_COUNT 4 +/// +/// #endif +/// @endcode +/// +/// @n @section dmadrv_api The API +/// +/// This section contains brief descriptions of the API functions. +/// For more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, +/// see @ref ecode and @ref dmadrv_error_codes for other error codes. +/// +/// The application code must include @em dmadrv.h header file. +/// +/// @ref DMADRV_Init(), @ref DMADRV_DeInit() @n +/// These functions initialize or deinitialize the DMADRV driver. Typically, +/// DMADRV_Init() is called once in the startup code. +/// +/// @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n +/// DMA channel reserve and release functions. It is recommended that +/// application code check that DMADRV_AllocateChannel() +/// returns ECODE_EMDRV_DMADRV_OK before starting a DMA +/// transfer. +/// +/// @ref DMADRV_MemoryPeripheral() @n +/// Start a DMA transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemory() @n +/// Start a DMA transfer from a peripheral to memory. +/// +/// @ref DMADRV_MemoryPeripheralPingPong() @n +/// Start a DMA ping-pong transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemoryPingPong() @n +/// Start a DMA ping-pong transfer from a peripheral to memory. +/// +/// @ref DMADRV_LdmaStartTransfer() @n +/// Start a DMA transfer on an LDMA controller. +/// +/// @ref DMADRV_StopTransfer() @n +/// Stop an ongoing DMA transfer. +/// +/// @ref DMADRV_TransferActive() @n +/// Check if a transfer is ongoing. +/// +/// @ref DMADRV_TransferCompletePending() @n +/// Check if a transfer completion is pending. +/// +/// @ref DMADRV_TransferDone() @n +/// Check if a transfer has completed. +/// +/// @ref DMADRV_TransferRemainingCount() @n +/// Get number of items remaining in a transfer. +/// +/// @n @section dmadrv_example Example +/// Transfer a text string to USART1. +/// @code{.c} +/// #include "dmadrv.h" +/// +/// char str[] = "Hello DMA !"; +/// unsigned int channel; +/// +/// int main( void ) +/// { +/// // Initialize DMA. +/// DMADRV_Init(); +/// +/// // Request a DMA channel. +/// DMADRV_AllocateChannel( &channel, NULL ); +/// +/// // Start the DMA transfer. +/// DMADRV_MemoryPeripheral( channel, +/// dmadrvPeripheralSignal_USART1_TXBL, +/// (void*)&(USART1->TXDATA), +/// str, +/// true, +/// sizeof( str ), +/// dmadrvDataSize1, +/// NULL, +/// NULL ); +/// +/// return 0; +/// } +/// @endcode +/// +/// @} end group dmadrv ******************************************************** diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h b/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h index 2ab8065..74349b6 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h @@ -1,102 +1,102 @@ -/***************************************************************************//** - * @file - * @brief GPIOINT API definition - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef GPIOINTERRUPT_H -#define GPIOINTERRUPT_H - -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup gpioint - * @{ - ******************************************************************************/ -/******************************************************************************* - ***************************** DEFINITIONS ********************************* - ******************************************************************************/ - -#define INTERRUPT_UNAVAILABLE (0xFF) ///< A MACRO for Interrupt Un-available. - -/******************************************************************************* - ******************************* TYPEDEFS ********************************** - ******************************************************************************/ - -/** - * @brief - * GPIO interrupt callback function pointer. - * @details - * Parameters: - * @li intNo - The pin interrupt number the callback function is invoked for. - */ -typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo); - -/** - * @brief - * Extended GPIO interrupt callback function pointer. - * @details - * Parameters: - * @li intNo - The pin interrupt number the callback function is invoked for. - * @li ctx - Pointer to callback context. - */ -typedef void (*GPIOINT_IrqCallbackPtrExt_t)(uint8_t intNo, void *ctx); - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ -void GPIOINT_Init(void); -void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr); -unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx); -__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); - -/***************************************************************************//** - * @brief - * Unregister user callback for a given pin interrupt number. - * - * @details - * Use this function to unregister a callback. - * - * @param[in] intNo - * Pin interrupt number for the callback. - * - ******************************************************************************/ -__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) -{ - GPIOINT_CallbackRegister(intNo, 0); -} - -/** @} (end addtogroup gpioint) */ -#ifdef __cplusplus -} -#endif - -#endif /* GPIOINTERRUPT_H */ +/***************************************************************************//** + * @file + * @brief GPIOINT API definition + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef GPIOINTERRUPT_H +#define GPIOINTERRUPT_H + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup gpioint + * @{ + ******************************************************************************/ +/******************************************************************************* + ***************************** DEFINITIONS ********************************* + ******************************************************************************/ + +#define INTERRUPT_UNAVAILABLE (0xFF) ///< A MACRO for Interrupt Un-available. + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +/** + * @brief + * GPIO interrupt callback function pointer. + * @details + * Parameters: + * @li intNo - The pin interrupt number the callback function is invoked for. + */ +typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo); + +/** + * @brief + * Extended GPIO interrupt callback function pointer. + * @details + * Parameters: + * @li intNo - The pin interrupt number the callback function is invoked for. + * @li ctx - Pointer to callback context. + */ +typedef void (*GPIOINT_IrqCallbackPtrExt_t)(uint8_t intNo, void *ctx); + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ +void GPIOINT_Init(void); +void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr); +unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx); +__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); + +/***************************************************************************//** + * @brief + * Unregister user callback for a given pin interrupt number. + * + * @details + * Use this function to unregister a callback. + * + * @param[in] intNo + * Pin interrupt number for the callback. + * + ******************************************************************************/ +__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) +{ + GPIOINT_CallbackRegister(intNo, 0); +} + +/** @} (end addtogroup gpioint) */ +#ifdef __cplusplus +} +#endif + +#endif /* GPIOINTERRUPT_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c b/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c index 049a970..6358fa7 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c @@ -1,366 +1,366 @@ -/***************************************************************************//** - * @file - * @brief GPIOINT API implementation - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_gpio.h" -#include "em_core.h" -#include "gpiointerrupt.h" -#include "sl_assert.h" -#include "sl_common.h" - -/***************************************************************************//** - * @addtogroup gpioint - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#define _GPIOINT_IF_EVEN_MASK ((_GPIO_IF_MASK) & 0x55555555UL) -#define _GPIOINT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) - -/******************************************************************************* - ******************************** MACROS *********************************** - ******************************************************************************/ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -typedef struct { - /* Pin interrupt number in range of 0 to 31 */ - uint32_t intNo; - /* Pointer to the callback function */ - void *callback; - /* Pointer to the callback context */ - void *context; - /* True if callback takes a context */ - bool context_flag; -} GPIOINT_CallbackDesc_t; - -/******************************************************************************* - ******************************** GLOBALS ********************************** - ******************************************************************************/ - -/* Array of user callbacks. One for each pin interrupt number. */ -static GPIOINT_CallbackDesc_t gpioCallbacks[32] = { 0 }; - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ -static void GPIOINT_IRQDispatcher(uint32_t iflags); - -/** @endcond */ - -/******************************************************************************* - *************************** GLOBAL FUNCTIONS ****************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialization of GPIOINT module. - * - ******************************************************************************/ -void GPIOINT_Init(void) -{ - if (CORE_NvicIRQDisabled(GPIO_ODD_IRQn)) { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - if (CORE_NvicIRQDisabled(GPIO_EVEN_IRQn)) { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } -} - -/***************************************************************************//** - * @brief - * Registers user callback for given pin interrupt number. - * - * @details - * Use this function to register a callback which shall be called upon - * interrupt generated for a given pin interrupt number. - * Interrupt itself must be configured externally. Function overwrites previously - * registered callback. - * - * @param[in] intNo - * Pin interrupt number for the callback. - * @param[in] callbackPtr - * A pointer to callback function. - ******************************************************************************/ -void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr) -{ - CORE_ATOMIC_SECTION( - /* Dispatcher is used */ - gpioCallbacks[intNo].callback = (void *)callbackPtr; - gpioCallbacks[intNo].context_flag = false; - ) -} - -/***************************************************************************//** - * @brief - * Registers user callback for given pin interrupt number. - * - * @details - * Use this function to register a callback with context which shall be called upon - * interrupt generated for a given pin number. - * The function will return an interrupt number if one is available. - * Interrupt itself must be configured externally. - * - * @param[in] pin - * Pin number for the callback. - * @param[in] callbackPtr - * A pointer to callback function. - * @param[in] callbackCtx - * A pointer to the callback context. - * - * @return - * Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use - ******************************************************************************/ -unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx) -{ - CORE_DECLARE_IRQ_STATE; - unsigned int intNo = INTERRUPT_UNAVAILABLE; - - CORE_ENTER_ATOMIC(); - -#if defined(_GPIO_EXTIPINSELL_MASK) - uint32_t intToCheck; - uint32_t intGroupStart = (pin & 0xFFC); - uint32_t intsEnabled = GPIO_EnabledIntGet(); - - // loop through the interrupt group, starting - // from the pin number, and take - // the first available - for (uint8_t i = 0; i < 4; i++) { - intToCheck = intGroupStart + ((pin + i) & 0x3); // modulo 4 - if (((intsEnabled >> intToCheck) & 0x1) == 0) { - intNo = (unsigned int)intToCheck; - break; - } - } -#else - if (gpioCallbacks[pin].callback == 0) { - intNo = (unsigned int)pin; - } -#endif - - if (intNo != INTERRUPT_UNAVAILABLE) { - gpioCallbacks[intNo].callback = (void *)callbackPtr; - gpioCallbacks[intNo].context = callbackCtx; - gpioCallbacks[intNo].context_flag = true; - } - - CORE_EXIT_ATOMIC(); - - return intNo; -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Function calls users callback for registered pin interrupts. - * - * @details - * This function is called when GPIO interrupts are handled by the IRQHandlers. - * Function gets even or odd interrupt flags and calls user callback - * registered for that pin. Function iterates on flags starting from MSB. - * - * @param iflags - * Interrupt flags which shall be handled by the dispatcher. - * - ******************************************************************************/ -static void GPIOINT_IRQDispatcher(uint32_t iflags) -{ - uint32_t irqIdx; - GPIOINT_CallbackDesc_t *callback; - - /* check for all flags set in IF register */ - while (iflags != 0U) { - irqIdx = SL_CTZ(iflags); - - /* clear flag*/ - iflags &= ~(1UL << irqIdx); - - callback = &gpioCallbacks[irqIdx]; - if (callback->callback) { - /* call user callback */ - if (callback->context_flag) { - GPIOINT_IrqCallbackPtrExt_t func = (GPIOINT_IrqCallbackPtrExt_t)(callback->callback); - func((uint8_t)irqIdx, callback->context); - } else { - GPIOINT_IrqCallbackPtr_t func = (GPIOINT_IrqCallbackPtr_t)(callback->callback); - func((uint8_t)irqIdx); - } - } - } -} - -/***************************************************************************//** - * @brief - * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and - * call the dispatcher passing the flags which triggered the interrupt. - * - ******************************************************************************/ -void GPIO_EVEN_IRQHandler(void) -{ - uint32_t iflags; - - /* Get all even interrupts. */ - iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_EVEN_MASK; - - /* Clean only even interrupts. */ - GPIO_IntClear(iflags); - - GPIOINT_IRQDispatcher(iflags); -} - -/***************************************************************************//** - * @brief - * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and - * call the dispatcher passing the flags which triggered the interrupt. - * - ******************************************************************************/ -void GPIO_ODD_IRQHandler(void) -{ - uint32_t iflags; - - /* Get all odd interrupts. */ - iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_ODD_MASK; - - /* Clean only odd interrupts. */ - GPIO_IntClear(iflags); - - GPIOINT_IRQDispatcher(iflags); -} - -/** @endcond */ - -/** @} (end addtogroup gpioint) */ - -/* *INDENT-OFF* */ -// ******* THE REST OF THE FILE IS DOCUMENTATION ONLY !************************ -/// @addtogroup gpioint GPIOINT - GPIO Interrupt -/// @brief GPIOINT General Purpose Input/Output Interrupt dispatcher -/// @{ -/// -/// @details -/// The source files for the GPIO interrupt dispatcher library resides in the -/// emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h. -/// -/// -/// @n @section gpioint_intro Introduction -/// EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more -/// than two interrupts are used then interrupt routine must dispatch from a callback -/// register. This module provides small dispatcher for both GPIO interrupts enabling -/// handling of up to 32 GPIO pin interrupts. -/// -/// It is up to the user to configure and enable interrupt on given pin. This can be done -/// using the GPIO library (emlib). This module handles the dispatch register and clearing of -/// interrupt flags. -/// -/// In order to use this dispatcher, it has to be initialized first by -/// calling GPIOINT_Init(). Then each pin interrupt number must be configured by first -/// registering the callback function for given interrupt number and then configure and -/// enabling the interrupt number in the GPIO module. -/// -/// The extended function GPIOINT_CallbackRegisterExt() may also be used to register a callback -/// with context for a given pin number. The first available interrupt number will be returned. -/// -/// @n @section gpioint_api The API -/// This section contain brief descriptions of the functions in the API. You will -/// find detailed information on parameters by clicking on the hyperlinked function names. -/// -/// Your application code must include one header file: @em gpiointerrupt.h. -/// -/// @ref GPIOINT_Init() @n -/// This functions initializes the dispatcher register. Typically -/// GPIOINT_Init() is called once in your startup code. -/// -/// @ref GPIOINT_CallbackRegister() @n -/// Register a callback function on a pin interrupt number. -/// -/// @ref GPIOINT_CallbackUnRegister() @n -/// Un-register a callback function on a pin interrupt number. -/// -/// @ref GPIOINT_CallbackRegisterExt() @n -/// Register a callback function with context on a pin number. -/// -/// @n @section gpioint_example Example -/// @code{.c} -/// -///#include "gpiointerrupt.h" -/// -///#include "em_chip.h" -///#include "em_cmu.h" -///#include "em_gpio.h" -/// -///// An array to track if given pin callback was called -///volatile uint8_t pinInt[32]; -/// -///// Gpio callbacks called when pin interrupt was triggered. -///void gpioCallback1(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///void gpioCallback3(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///void gpioCallback8(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///int main(void) -///{ -/// CHIP_Init(); -/// -/// // Enable clock for GPIO module, initialize GPIOINT -/// CMU_ClockEnable(cmuClock_GPIO, true); -/// GPIOINT_Init(); -/// -/// // Register callback functions and enable interrupts -/// GPIOINT_CallbackRegister(1, gpioCallback1); -/// GPIOINT_CallbackRegister(3, gpioCallback3); -/// unsigned int intPin8 = GPIOINT_CallbackRegisterExt(8, gpioCallback8, (void *)callback8context); -/// GPIO_IntEnable(1<<1 | 1<<3 | 1<Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_gpio.h" +#include "em_core.h" +#include "gpiointerrupt.h" +#include "sl_assert.h" +#include "sl_common.h" + +/***************************************************************************//** + * @addtogroup gpioint + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#define _GPIOINT_IF_EVEN_MASK ((_GPIO_IF_MASK) & 0x55555555UL) +#define _GPIOINT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) + +/******************************************************************************* + ******************************** MACROS *********************************** + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +typedef struct { + /* Pin interrupt number in range of 0 to 31 */ + uint32_t intNo; + /* Pointer to the callback function */ + void *callback; + /* Pointer to the callback context */ + void *context; + /* True if callback takes a context */ + bool context_flag; +} GPIOINT_CallbackDesc_t; + +/******************************************************************************* + ******************************** GLOBALS ********************************** + ******************************************************************************/ + +/* Array of user callbacks. One for each pin interrupt number. */ +static GPIOINT_CallbackDesc_t gpioCallbacks[32] = { 0 }; + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ +static void GPIOINT_IRQDispatcher(uint32_t iflags); + +/** @endcond */ + +/******************************************************************************* + *************************** GLOBAL FUNCTIONS ****************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialization of GPIOINT module. + * + ******************************************************************************/ +void GPIOINT_Init(void) +{ + if (CORE_NvicIRQDisabled(GPIO_ODD_IRQn)) { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + if (CORE_NvicIRQDisabled(GPIO_EVEN_IRQn)) { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } +} + +/***************************************************************************//** + * @brief + * Registers user callback for given pin interrupt number. + * + * @details + * Use this function to register a callback which shall be called upon + * interrupt generated for a given pin interrupt number. + * Interrupt itself must be configured externally. Function overwrites previously + * registered callback. + * + * @param[in] intNo + * Pin interrupt number for the callback. + * @param[in] callbackPtr + * A pointer to callback function. + ******************************************************************************/ +void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr) +{ + CORE_ATOMIC_SECTION( + /* Dispatcher is used */ + gpioCallbacks[intNo].callback = (void *)callbackPtr; + gpioCallbacks[intNo].context_flag = false; + ) +} + +/***************************************************************************//** + * @brief + * Registers user callback for given pin interrupt number. + * + * @details + * Use this function to register a callback with context which shall be called upon + * interrupt generated for a given pin number. + * The function will return an interrupt number if one is available. + * Interrupt itself must be configured externally. + * + * @param[in] pin + * Pin number for the callback. + * @param[in] callbackPtr + * A pointer to callback function. + * @param[in] callbackCtx + * A pointer to the callback context. + * + * @return + * Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use + ******************************************************************************/ +unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx) +{ + CORE_DECLARE_IRQ_STATE; + unsigned int intNo = INTERRUPT_UNAVAILABLE; + + CORE_ENTER_ATOMIC(); + +#if defined(_GPIO_EXTIPINSELL_MASK) + uint32_t intToCheck; + uint32_t intGroupStart = (pin & 0xFFC); + uint32_t intsEnabled = GPIO_EnabledIntGet(); + + // loop through the interrupt group, starting + // from the pin number, and take + // the first available + for (uint8_t i = 0; i < 4; i++) { + intToCheck = intGroupStart + ((pin + i) & 0x3); // modulo 4 + if (((intsEnabled >> intToCheck) & 0x1) == 0) { + intNo = (unsigned int)intToCheck; + break; + } + } +#else + if (gpioCallbacks[pin].callback == 0) { + intNo = (unsigned int)pin; + } +#endif + + if (intNo != INTERRUPT_UNAVAILABLE) { + gpioCallbacks[intNo].callback = (void *)callbackPtr; + gpioCallbacks[intNo].context = callbackCtx; + gpioCallbacks[intNo].context_flag = true; + } + + CORE_EXIT_ATOMIC(); + + return intNo; +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Function calls users callback for registered pin interrupts. + * + * @details + * This function is called when GPIO interrupts are handled by the IRQHandlers. + * Function gets even or odd interrupt flags and calls user callback + * registered for that pin. Function iterates on flags starting from MSB. + * + * @param iflags + * Interrupt flags which shall be handled by the dispatcher. + * + ******************************************************************************/ +static void GPIOINT_IRQDispatcher(uint32_t iflags) +{ + uint32_t irqIdx; + GPIOINT_CallbackDesc_t *callback; + + /* check for all flags set in IF register */ + while (iflags != 0U) { + irqIdx = SL_CTZ(iflags); + + /* clear flag*/ + iflags &= ~(1UL << irqIdx); + + callback = &gpioCallbacks[irqIdx]; + if (callback->callback) { + /* call user callback */ + if (callback->context_flag) { + GPIOINT_IrqCallbackPtrExt_t func = (GPIOINT_IrqCallbackPtrExt_t)(callback->callback); + func((uint8_t)irqIdx, callback->context); + } else { + GPIOINT_IrqCallbackPtr_t func = (GPIOINT_IrqCallbackPtr_t)(callback->callback); + func((uint8_t)irqIdx); + } + } + } +} + +/***************************************************************************//** + * @brief + * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and + * call the dispatcher passing the flags which triggered the interrupt. + * + ******************************************************************************/ +void GPIO_EVEN_IRQHandler(void) +{ + uint32_t iflags; + + /* Get all even interrupts. */ + iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_EVEN_MASK; + + /* Clean only even interrupts. */ + GPIO_IntClear(iflags); + + GPIOINT_IRQDispatcher(iflags); +} + +/***************************************************************************//** + * @brief + * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and + * call the dispatcher passing the flags which triggered the interrupt. + * + ******************************************************************************/ +void GPIO_ODD_IRQHandler(void) +{ + uint32_t iflags; + + /* Get all odd interrupts. */ + iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_ODD_MASK; + + /* Clean only odd interrupts. */ + GPIO_IntClear(iflags); + + GPIOINT_IRQDispatcher(iflags); +} + +/** @endcond */ + +/** @} (end addtogroup gpioint) */ + +/* *INDENT-OFF* */ +// ******* THE REST OF THE FILE IS DOCUMENTATION ONLY !************************ +/// @addtogroup gpioint GPIOINT - GPIO Interrupt +/// @brief GPIOINT General Purpose Input/Output Interrupt dispatcher +/// @{ +/// +/// @details +/// The source files for the GPIO interrupt dispatcher library resides in the +/// emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h. +/// +/// +/// @n @section gpioint_intro Introduction +/// EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more +/// than two interrupts are used then interrupt routine must dispatch from a callback +/// register. This module provides small dispatcher for both GPIO interrupts enabling +/// handling of up to 32 GPIO pin interrupts. +/// +/// It is up to the user to configure and enable interrupt on given pin. This can be done +/// using the GPIO library (emlib). This module handles the dispatch register and clearing of +/// interrupt flags. +/// +/// In order to use this dispatcher, it has to be initialized first by +/// calling GPIOINT_Init(). Then each pin interrupt number must be configured by first +/// registering the callback function for given interrupt number and then configure and +/// enabling the interrupt number in the GPIO module. +/// +/// The extended function GPIOINT_CallbackRegisterExt() may also be used to register a callback +/// with context for a given pin number. The first available interrupt number will be returned. +/// +/// @n @section gpioint_api The API +/// This section contain brief descriptions of the functions in the API. You will +/// find detailed information on parameters by clicking on the hyperlinked function names. +/// +/// Your application code must include one header file: @em gpiointerrupt.h. +/// +/// @ref GPIOINT_Init() @n +/// This functions initializes the dispatcher register. Typically +/// GPIOINT_Init() is called once in your startup code. +/// +/// @ref GPIOINT_CallbackRegister() @n +/// Register a callback function on a pin interrupt number. +/// +/// @ref GPIOINT_CallbackUnRegister() @n +/// Un-register a callback function on a pin interrupt number. +/// +/// @ref GPIOINT_CallbackRegisterExt() @n +/// Register a callback function with context on a pin number. +/// +/// @n @section gpioint_example Example +/// @code{.c} +/// +///#include "gpiointerrupt.h" +/// +///#include "em_chip.h" +///#include "em_cmu.h" +///#include "em_gpio.h" +/// +///// An array to track if given pin callback was called +///volatile uint8_t pinInt[32]; +/// +///// Gpio callbacks called when pin interrupt was triggered. +///void gpioCallback1(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///void gpioCallback3(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///void gpioCallback8(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///int main(void) +///{ +/// CHIP_Init(); +/// +/// // Enable clock for GPIO module, initialize GPIOINT +/// CMU_ClockEnable(cmuClock_GPIO, true); +/// GPIOINT_Init(); +/// +/// // Register callback functions and enable interrupts +/// GPIOINT_CallbackRegister(1, gpioCallback1); +/// GPIOINT_CallbackRegister(3, gpioCallback3); +/// unsigned int intPin8 = GPIOINT_CallbackRegisterExt(8, gpioCallback8, (void *)callback8context); +/// GPIO_IntEnable(1<<1 | 1<<3 | 1<Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef UARTDRV_H -#define UARTDRV_H - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#include "em_device.h" -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#include "em_usart.h" -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) -#include "em_leuart.h" -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - -#if (_SILICON_LABS_32B_SERIES > 2) -#define UARTDRV_USE_PERIPHERAL -#include "sl_peripheral_eusart.h" -#else -#include "em_eusart.h" -#endif -#endif - -#if defined(UARTDRV_USE_PERIPHERAL) -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 // TODO (PLATFORM_MTL-8363): Remove when sl_gpio will be used. -#include "sl_peripheral_gpio.h" -#else -#include "em_gpio.h" -#endif - -#include "em_cmu.h" -#include "ecode.h" -#include "uartdrv_config.h" -#include "dmadrv.h" -#include "sl_enum.h" -#include "sl_sleeptimer.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup uartdrv_error_codes Error Codes - * @{ - ******************************************************************************/ -#define ECODE_EMDRV_UARTDRV_OK (ECODE_OK) ///< A successful return value. -#define ECODE_EMDRV_UARTDRV_WAITING (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue. -#define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle. -#define ECODE_EMDRV_UARTDRV_PARAM_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter. -#define ECODE_EMDRV_UARTDRV_BUSY (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy. -#define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port. -#define ECODE_EMDRV_UARTDRV_IDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress. -#define ECODE_EMDRV_UARTDRV_ABORTED (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted. -#define ECODE_EMDRV_UARTDRV_QUEUE_FULL (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full. -#define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty. -#define ECODE_EMDRV_UARTDRV_PARITY_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored. -#define ECODE_EMDRV_UARTDRV_FRAME_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored. -#define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels. -#define ECODE_EMDRV_UARTDRV_CLOCK_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate. -/** @} (end addtogroup error codes) */ - -/***************************************************************************//** - * @addtogroup uartdrv_status_codes Status Codes - * @{ - ******************************************************************************/ -#define UARTDRV_STATUS_RXEN (1 << 0) ///< The receiver is enabled. -#define UARTDRV_STATUS_TXEN (1 << 1) ///< The transmitter is enabled. -#define UARTDRV_STATUS_RXBLOCK (1 << 3) ///< The receiver is blocked; incoming frames will be discarded. -#define UARTDRV_STATUS_TXTRI (1 << 4) ///< The transmitter is tristated. -#define UARTDRV_STATUS_TXC (1 << 5) ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register. -#define UARTDRV_STATUS_TXBL (1 << 6) ///< The transmit buffer is empty. -#define UARTDRV_STATUS_RXDATAV (1 << 7) ///< Data is available in the receive buffer. -#define UARTDRV_STATUS_RXFULL (1 << 8) ///< The receive buffer is full. -#if defined(EUSART_STATUS_TXCANDTXIDLE) -#define UARTDRV_STATUS_TXCANDTXIDLE (1 << 9) ///< Set when both TXC and TXIDLE are set. -#endif -#define UARTDRV_STATUS_TXIDLE (1 << 13) ///< The transmitter is idle. -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -#define UARTDRV_STATUS_RXIDLE (1 << 12) ///< The Receiver is idle. -#endif -/** @} (end addtogroup status codes) */ - -typedef uint32_t UARTDRV_Count_t; ///< A UART transfer count -typedef uint32_t UARTDRV_Status_t; ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values. - -/** - * @enum UARTDRV_FlowControlType_t - * @brief UARTDRV Flow Control method. - */ -SL_ENUM(UARTDRV_FlowControlType_t) { - uartdrvFlowControlNone = 0, ///< None - uartdrvFlowControlSw = 1, ///< Software XON/XOFF - uartdrvFlowControlHw = 2, ///< nRTS/nCTS hardware handshake - uartdrvFlowControlHwUart = 3 ///< UART peripheral controls nRTS/nCTS -}; - -/// Flow Control state -SL_ENUM(UARTDRV_FlowControlState_t) { - uartdrvFlowControlOn = 0, ///< XON or nRTS/nCTS low - uartdrvFlowControlOff = 1, ///< XOFF or nRTS/nCTS high - uartdrvFlowControlAuto = 2 ///< This driver controls the state. -}; - -/// Transfer abort type -SL_ENUM(UARTDRV_AbortType_t) { - uartdrvAbortTransmit = 1, ///< Abort current and queued transmit operations - uartdrvAbortReceive = 2, ///< Abort current and queued receive operations - uartdrvAbortAll = 3 ///< Abort all current and queued operations -}; - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/// Type of a UART peripheral -SL_ENUM(UARTDRV_UartType_t) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - uartdrvUartTypeUart = 0, ///< USART/UART peripheral -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - uartdrvUartTypeLeuart = 1 ///< LEUART peripheral -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - uartdrvUartTypeEuart = 2 ///< EUART peripheral -#endif -}; -/// @endcond - -struct UARTDRV_HandleData; - -/***************************************************************************//** - * @brief - * UARTDRV transfer completion callback function. - * - * @details - * Called when a transfer is complete. An - * application should check the transferStatus and itemsTransferred values. - * - * @param[in] handle - * The UARTDRV device handle used to start the transfer. - * - * @param[in] transferStatus - * Completion status of the transfer operation. - * - * @param[in] data - * A pointer to the transfer data buffer. - * - * @param[in] transferCount - * A number of bytes transferred. - ******************************************************************************/ -typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); - -/// UART transfer buffer -typedef struct { - uint8_t *data; ///< Transfer data buffer - UARTDRV_Count_t transferCount; ///< Transfer item count - volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining - UARTDRV_Callback_t callback; ///< Completion callback - Ecode_t transferStatus; ///< Completion status of the transfer operation -} UARTDRV_Buffer_t; - -/// Transfer operation FIFO queue typedef -typedef struct { - volatile uint16_t head; ///< An index of the next byte to send. - volatile uint16_t tail; ///< An index of the location to enqueue the next message. - volatile uint16_t used; ///< A number of bytes queued. - const uint16_t size; ///< FIFO size. - UARTDRV_Buffer_t fifo[1]; ///< FIFO of queued data. Actual size varies. -} UARTDRV_Buffer_FifoQueue_t; - -/// Macros to define FIFO and buffer queues. typedef can't be used because the size -/// of the FIFO array in the queues can change. -#define DEFINE_BUF_QUEUE(qSize, qName) \ - typedef struct { \ - uint16_t head; \ - uint16_t tail; \ - volatile uint16_t used; \ - const uint16_t size; \ - UARTDRV_Buffer_t fifo[qSize]; \ - } _##qName; \ - static volatile _##qName qName = \ - { \ - .head = 0, \ - .tail = 0, \ - .used = 0, \ - .size = qSize, \ - } - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/** - * @struct UARTDRV_InitUart_t - * @brief A UART driver instance initialization structure. - * LEUART driver instance initialization structure. - * Contains a number of UARTDRV configuration options. - * It is required for driver instance initialization. - * This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV - * instance. - */ -typedef struct { - USART_TypeDef *port; ///< The peripheral used for UART - uint32_t baudRate; ///< UART baud rate -#if defined(_USART_ROUTELOC0_MASK) - uint8_t portLocationTx; ///< A location number for UART Tx pin. - uint8_t portLocationRx; ///< A location number for UART Rx pin. -#elif defined(_USART_ROUTE_MASK) - uint8_t portLocation; ///< A location number for UART pins. -#elif defined(_GPIO_USART_ROUTEEN_MASK) - GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. - GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. - uint8_t txPin; ///< Pin number for UART Tx. - uint8_t rxPin; ///< Pin number for UART Rx. - uint8_t uartNum; ///< UART instance number. -#endif - USART_Stopbits_TypeDef stopBits; ///< A number of stop bits. - USART_Parity_TypeDef parity; ///< Parity configuration. - USART_OVS_TypeDef oversampling; ///< Oversampling mode. -#if defined(USART_CTRL_MVDIS) - bool mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#endif - UARTDRV_FlowControlType_t fcType; ///< Flow control mode. - GPIO_Port_TypeDef ctsPort; ///< A CTS pin port number. - uint8_t ctsPin; ///< A CTS pin number. - GPIO_Port_TypeDef rtsPort; ///< An RTS pin port number. - uint8_t rtsPin; ///< An RTS pin number. - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< A receive operation queue. - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< T transmit operation queue. -#if defined(_USART_ROUTELOC1_MASK) - uint8_t portLocationCts; ///< A location number for the UART CTS pin. - uint8_t portLocationRts; ///< A location number for the UART RTS pin. -#endif -} UARTDRV_InitUart_t; -#endif - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -/** - * @struct UARTDRV_InitLeuart_t - * @brief LEUART driver instance initialization structure. - * LEUART driver instance initialization structure. - * Contains a number of UARTDRV configuration options. - * It is required to initialize a driver instance. - * This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV - * instance. - */ -typedef struct { - LEUART_TypeDef *port; ///< The peripheral used for LEUART - uint32_t baudRate; ///< UART baud rate -#if defined(_LEUART_ROUTELOC0_MASK) - uint8_t portLocationTx; ///< Location number for LEUART Tx pin. - uint8_t portLocationRx; ///< Location number for LEUART Rx pin. -#else - uint8_t portLocation; ///< Location number for LEUART pins -#endif - LEUART_Stopbits_TypeDef stopBits; ///< Number of stop bits - LEUART_Parity_TypeDef parity; ///< Parity configuration - UARTDRV_FlowControlType_t fcType; ///< Flow control mode - GPIO_Port_TypeDef ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - GPIO_Port_TypeDef rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue -} UARTDRV_InitLeuart_t; -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -/// UART driver instance initialization structure. -/// Contains a number of UARTDRV configuration options. -/// It is required to initialize a driver instance. -/// This structure is passed to @ref UARTDRV_InitEuart() when initializing a UARTDRV -typedef struct { - EUSART_TypeDef *port; ///< The peripheral used for EUART - bool useLowFrequencyMode; ///< Clock configuration of the EUART - uint32_t baudRate; ///< EUART baud rate -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t txPort; ///< Port for UART Tx pin. - sl_gpio_port_t rxPort; ///< Port for UART Rx pin. -#else - GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. - GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. -#endif - uint8_t txPin; ///< Pin number for UART Tx. - uint8_t rxPin; ///< Pin number for UART Rx. - uint8_t uartNum; ///< EUART instance number. -#if defined(UARTDRV_USE_PERIPHERAL) - sl_hal_eusart_stop_bits_t stopBits; ///< Number of stop bits - sl_hal_eusart_parity_t parity; ///< Parity configuration - sl_hal_eusart_ovs_t oversampling; ///< Oversampling mode. - sl_hal_eusart_majority_vote_t mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#else - EUSART_Stopbits_TypeDef stopBits; ///< Number of stop bits - EUSART_Parity_TypeDef parity; ///< Parity configuration - EUSART_OVS_TypeDef oversampling; ///< Oversampling mode. - EUSART_MajorityVote_TypeDef mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#endif - UARTDRV_FlowControlType_t fcType; ///< Flow control mode -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - sl_gpio_port_t rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number -#else - GPIO_Port_TypeDef ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - GPIO_Port_TypeDef rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number -#endif - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue -} UARTDRV_InitEuart_t; -#endif - -/// A UART driver instance handle data structure. -/// Allocated by the application using UARTDRV. -/// Several concurrent driver instances may exist in an application. The application must -/// not modify the contents of this handle and should not depend on its values. -typedef struct UARTDRV_HandleData{ - /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - union { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - USART_TypeDef * uart; -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - LEUART_TypeDef * leuart; -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - EUSART_TypeDef * euart; -#endif - void * __reserved_space; - } peripheral; - uint8_t uartNum; // UART instance number - unsigned int txDmaCh; // A DMA ch assigned to Tx - unsigned int rxDmaCh; // A DMA ch assigned to Rx - DMADRV_PeripheralSignal_t txDmaSignal; // A DMA Tx trigger source signal - DMADRV_PeripheralSignal_t rxDmaSignal; // A DMA Rx trigger source signal - UARTDRV_FlowControlState_t fcSelfState; // A current self flow control state - UARTDRV_FlowControlState_t fcSelfCfg; // A self flow control override configuration - UARTDRV_FlowControlState_t fcPeerState; // A current peer flow control state -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t txPort; // A Tx pin port number - sl_gpio_port_t rxPort; // An Rx pin port number - sl_gpio_port_t ctsPort; // A CTS pin port number - sl_gpio_port_t rtsPort; // An RTS pin port number -#else - GPIO_Port_TypeDef txPort; // A Tx pin port number - GPIO_Port_TypeDef rxPort; // An Rx pin port number - GPIO_Port_TypeDef ctsPort; // A CTS pin port number - GPIO_Port_TypeDef rtsPort; // An RTS pin port number -#endif - uint8_t txPin; // A Tx pin number - uint8_t rxPin; // An Tx pin number - uint8_t ctsPin; // A CTS pin number - uint8_t rtsPin; // An RTS pin number - CMU_Clock_TypeDef uartClock; // A clock source select - UARTDRV_Buffer_FifoQueue_t *rxQueue; // A receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; // A transmit operation queue - volatile bool rxDmaActive; // A receive DMA is currently active - volatile bool txDmaActive; // A transmit DMA is currently active - volatile uint8_t txDmaPaused; // A transmit DMA pause counter - bool IgnoreRestrain; // A transmit does not respect uartdrvFlowControlOff - bool hasTransmitted; // Indicates whether the handle has transmitted data - UARTDRV_FlowControlType_t fcType; // A flow control mode - UARTDRV_UartType_t type; // A type of UART - volatile int em1RequestCount; // A EM1 request count for the handle - sl_sleeptimer_timer_handle_t delayedTxTimer; // A timer to wait for the last byte out - size_t sleep; // Sleep state on isr return - /// @endcond -} UARTDRV_HandleData_t; - -/// Handle pointer -typedef UARTDRV_HandleData_t * UARTDRV_Handle_t; - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t * initData); -#endif - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t * initData); -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t * initData); -#endif -Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle); - -UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle); - -UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *bytesReceived, - UARTDRV_Count_t *bytesRemaining); - -UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *bytesSent, - UARTDRV_Count_t *bytesRemaining); - -uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle); - -uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback); - -Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback); - -Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t maxLength); - -Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type); - -Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle); - -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle); - -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); - -Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); - -Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void); -#endif - -/** @} (end addtogroup uartdrv) */ - -#ifdef __cplusplus -} -#endif -#endif // UARTDRV_H +/***************************************************************************//** + * @file + * @brief UARTDRV API definition. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef UARTDRV_H +#define UARTDRV_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#include "em_device.h" +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#include "em_usart.h" +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) +#include "em_leuart.h" +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + +#if (_SILICON_LABS_32B_SERIES > 2) +#define UARTDRV_USE_PERIPHERAL +#include "sl_peripheral_eusart.h" +#else +#include "em_eusart.h" +#endif +#endif + +#if defined(UARTDRV_USE_PERIPHERAL) +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 // TODO (PLATFORM_MTL-8363): Remove when sl_gpio will be used. +#include "sl_peripheral_gpio.h" +#else +#include "em_gpio.h" +#endif + +#include "em_cmu.h" +#include "ecode.h" +#include "uartdrv_config.h" +#include "dmadrv.h" +#include "sl_enum.h" +#include "sl_sleeptimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup uartdrv_error_codes Error Codes + * @{ + ******************************************************************************/ +#define ECODE_EMDRV_UARTDRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_UARTDRV_WAITING (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue. +#define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle. +#define ECODE_EMDRV_UARTDRV_PARAM_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter. +#define ECODE_EMDRV_UARTDRV_BUSY (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy. +#define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port. +#define ECODE_EMDRV_UARTDRV_IDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress. +#define ECODE_EMDRV_UARTDRV_ABORTED (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted. +#define ECODE_EMDRV_UARTDRV_QUEUE_FULL (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full. +#define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty. +#define ECODE_EMDRV_UARTDRV_PARITY_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored. +#define ECODE_EMDRV_UARTDRV_FRAME_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored. +#define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels. +#define ECODE_EMDRV_UARTDRV_CLOCK_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate. +/** @} (end addtogroup error codes) */ + +/***************************************************************************//** + * @addtogroup uartdrv_status_codes Status Codes + * @{ + ******************************************************************************/ +#define UARTDRV_STATUS_RXEN (1 << 0) ///< The receiver is enabled. +#define UARTDRV_STATUS_TXEN (1 << 1) ///< The transmitter is enabled. +#define UARTDRV_STATUS_RXBLOCK (1 << 3) ///< The receiver is blocked; incoming frames will be discarded. +#define UARTDRV_STATUS_TXTRI (1 << 4) ///< The transmitter is tristated. +#define UARTDRV_STATUS_TXC (1 << 5) ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register. +#define UARTDRV_STATUS_TXBL (1 << 6) ///< The transmit buffer is empty. +#define UARTDRV_STATUS_RXDATAV (1 << 7) ///< Data is available in the receive buffer. +#define UARTDRV_STATUS_RXFULL (1 << 8) ///< The receive buffer is full. +#if defined(EUSART_STATUS_TXCANDTXIDLE) +#define UARTDRV_STATUS_TXCANDTXIDLE (1 << 9) ///< Set when both TXC and TXIDLE are set. +#endif +#define UARTDRV_STATUS_TXIDLE (1 << 13) ///< The transmitter is idle. +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +#define UARTDRV_STATUS_RXIDLE (1 << 12) ///< The Receiver is idle. +#endif +/** @} (end addtogroup status codes) */ + +typedef uint32_t UARTDRV_Count_t; ///< A UART transfer count +typedef uint32_t UARTDRV_Status_t; ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values. + +/** + * @enum UARTDRV_FlowControlType_t + * @brief UARTDRV Flow Control method. + */ +SL_ENUM(UARTDRV_FlowControlType_t) { + uartdrvFlowControlNone = 0, ///< None + uartdrvFlowControlSw = 1, ///< Software XON/XOFF + uartdrvFlowControlHw = 2, ///< nRTS/nCTS hardware handshake + uartdrvFlowControlHwUart = 3 ///< UART peripheral controls nRTS/nCTS +}; + +/// Flow Control state +SL_ENUM(UARTDRV_FlowControlState_t) { + uartdrvFlowControlOn = 0, ///< XON or nRTS/nCTS low + uartdrvFlowControlOff = 1, ///< XOFF or nRTS/nCTS high + uartdrvFlowControlAuto = 2 ///< This driver controls the state. +}; + +/// Transfer abort type +SL_ENUM(UARTDRV_AbortType_t) { + uartdrvAbortTransmit = 1, ///< Abort current and queued transmit operations + uartdrvAbortReceive = 2, ///< Abort current and queued receive operations + uartdrvAbortAll = 3 ///< Abort all current and queued operations +}; + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/// Type of a UART peripheral +SL_ENUM(UARTDRV_UartType_t) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + uartdrvUartTypeUart = 0, ///< USART/UART peripheral +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + uartdrvUartTypeLeuart = 1 ///< LEUART peripheral +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + uartdrvUartTypeEuart = 2 ///< EUART peripheral +#endif +}; +/// @endcond + +struct UARTDRV_HandleData; + +/***************************************************************************//** + * @brief + * UARTDRV transfer completion callback function. + * + * @details + * Called when a transfer is complete. An + * application should check the transferStatus and itemsTransferred values. + * + * @param[in] handle + * The UARTDRV device handle used to start the transfer. + * + * @param[in] transferStatus + * Completion status of the transfer operation. + * + * @param[in] data + * A pointer to the transfer data buffer. + * + * @param[in] transferCount + * A number of bytes transferred. + ******************************************************************************/ +typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); + +/// UART transfer buffer +typedef struct { + uint8_t *data; ///< Transfer data buffer + UARTDRV_Count_t transferCount; ///< Transfer item count + volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining + UARTDRV_Callback_t callback; ///< Completion callback + Ecode_t transferStatus; ///< Completion status of the transfer operation +} UARTDRV_Buffer_t; + +/// Transfer operation FIFO queue typedef +typedef struct { + volatile uint16_t head; ///< An index of the next byte to send. + volatile uint16_t tail; ///< An index of the location to enqueue the next message. + volatile uint16_t used; ///< A number of bytes queued. + const uint16_t size; ///< FIFO size. + UARTDRV_Buffer_t fifo[1]; ///< FIFO of queued data. Actual size varies. +} UARTDRV_Buffer_FifoQueue_t; + +/// Macros to define FIFO and buffer queues. typedef can't be used because the size +/// of the FIFO array in the queues can change. +#define DEFINE_BUF_QUEUE(qSize, qName) \ + typedef struct { \ + uint16_t head; \ + uint16_t tail; \ + volatile uint16_t used; \ + const uint16_t size; \ + UARTDRV_Buffer_t fifo[qSize]; \ + } _##qName; \ + static volatile _##qName qName = \ + { \ + .head = 0, \ + .tail = 0, \ + .used = 0, \ + .size = qSize, \ + } + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/** + * @struct UARTDRV_InitUart_t + * @brief A UART driver instance initialization structure. + * LEUART driver instance initialization structure. + * Contains a number of UARTDRV configuration options. + * It is required for driver instance initialization. + * This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV + * instance. + */ +typedef struct { + USART_TypeDef *port; ///< The peripheral used for UART + uint32_t baudRate; ///< UART baud rate +#if defined(_USART_ROUTELOC0_MASK) + uint8_t portLocationTx; ///< A location number for UART Tx pin. + uint8_t portLocationRx; ///< A location number for UART Rx pin. +#elif defined(_USART_ROUTE_MASK) + uint8_t portLocation; ///< A location number for UART pins. +#elif defined(_GPIO_USART_ROUTEEN_MASK) + GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. + GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. + uint8_t txPin; ///< Pin number for UART Tx. + uint8_t rxPin; ///< Pin number for UART Rx. + uint8_t uartNum; ///< UART instance number. +#endif + USART_Stopbits_TypeDef stopBits; ///< A number of stop bits. + USART_Parity_TypeDef parity; ///< Parity configuration. + USART_OVS_TypeDef oversampling; ///< Oversampling mode. +#if defined(USART_CTRL_MVDIS) + bool mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#endif + UARTDRV_FlowControlType_t fcType; ///< Flow control mode. + GPIO_Port_TypeDef ctsPort; ///< A CTS pin port number. + uint8_t ctsPin; ///< A CTS pin number. + GPIO_Port_TypeDef rtsPort; ///< An RTS pin port number. + uint8_t rtsPin; ///< An RTS pin number. + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< A receive operation queue. + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< T transmit operation queue. +#if defined(_USART_ROUTELOC1_MASK) + uint8_t portLocationCts; ///< A location number for the UART CTS pin. + uint8_t portLocationRts; ///< A location number for the UART RTS pin. +#endif +} UARTDRV_InitUart_t; +#endif + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +/** + * @struct UARTDRV_InitLeuart_t + * @brief LEUART driver instance initialization structure. + * LEUART driver instance initialization structure. + * Contains a number of UARTDRV configuration options. + * It is required to initialize a driver instance. + * This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV + * instance. + */ +typedef struct { + LEUART_TypeDef *port; ///< The peripheral used for LEUART + uint32_t baudRate; ///< UART baud rate +#if defined(_LEUART_ROUTELOC0_MASK) + uint8_t portLocationTx; ///< Location number for LEUART Tx pin. + uint8_t portLocationRx; ///< Location number for LEUART Rx pin. +#else + uint8_t portLocation; ///< Location number for LEUART pins +#endif + LEUART_Stopbits_TypeDef stopBits; ///< Number of stop bits + LEUART_Parity_TypeDef parity; ///< Parity configuration + UARTDRV_FlowControlType_t fcType; ///< Flow control mode + GPIO_Port_TypeDef ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + GPIO_Port_TypeDef rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue +} UARTDRV_InitLeuart_t; +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +/// UART driver instance initialization structure. +/// Contains a number of UARTDRV configuration options. +/// It is required to initialize a driver instance. +/// This structure is passed to @ref UARTDRV_InitEuart() when initializing a UARTDRV +typedef struct { + EUSART_TypeDef *port; ///< The peripheral used for EUART + bool useLowFrequencyMode; ///< Clock configuration of the EUART + uint32_t baudRate; ///< EUART baud rate +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t txPort; ///< Port for UART Tx pin. + sl_gpio_port_t rxPort; ///< Port for UART Rx pin. +#else + GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. + GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. +#endif + uint8_t txPin; ///< Pin number for UART Tx. + uint8_t rxPin; ///< Pin number for UART Rx. + uint8_t uartNum; ///< EUART instance number. +#if defined(UARTDRV_USE_PERIPHERAL) + sl_hal_eusart_stop_bits_t stopBits; ///< Number of stop bits + sl_hal_eusart_parity_t parity; ///< Parity configuration + sl_hal_eusart_ovs_t oversampling; ///< Oversampling mode. + sl_hal_eusart_majority_vote_t mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#else + EUSART_Stopbits_TypeDef stopBits; ///< Number of stop bits + EUSART_Parity_TypeDef parity; ///< Parity configuration + EUSART_OVS_TypeDef oversampling; ///< Oversampling mode. + EUSART_MajorityVote_TypeDef mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#endif + UARTDRV_FlowControlType_t fcType; ///< Flow control mode +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + sl_gpio_port_t rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number +#else + GPIO_Port_TypeDef ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + GPIO_Port_TypeDef rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number +#endif + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue +} UARTDRV_InitEuart_t; +#endif + +/// A UART driver instance handle data structure. +/// Allocated by the application using UARTDRV. +/// Several concurrent driver instances may exist in an application. The application must +/// not modify the contents of this handle and should not depend on its values. +typedef struct UARTDRV_HandleData{ + /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + union { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + USART_TypeDef * uart; +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + LEUART_TypeDef * leuart; +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + EUSART_TypeDef * euart; +#endif + void * __reserved_space; + } peripheral; + uint8_t uartNum; // UART instance number + unsigned int txDmaCh; // A DMA ch assigned to Tx + unsigned int rxDmaCh; // A DMA ch assigned to Rx + DMADRV_PeripheralSignal_t txDmaSignal; // A DMA Tx trigger source signal + DMADRV_PeripheralSignal_t rxDmaSignal; // A DMA Rx trigger source signal + UARTDRV_FlowControlState_t fcSelfState; // A current self flow control state + UARTDRV_FlowControlState_t fcSelfCfg; // A self flow control override configuration + UARTDRV_FlowControlState_t fcPeerState; // A current peer flow control state +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t txPort; // A Tx pin port number + sl_gpio_port_t rxPort; // An Rx pin port number + sl_gpio_port_t ctsPort; // A CTS pin port number + sl_gpio_port_t rtsPort; // An RTS pin port number +#else + GPIO_Port_TypeDef txPort; // A Tx pin port number + GPIO_Port_TypeDef rxPort; // An Rx pin port number + GPIO_Port_TypeDef ctsPort; // A CTS pin port number + GPIO_Port_TypeDef rtsPort; // An RTS pin port number +#endif + uint8_t txPin; // A Tx pin number + uint8_t rxPin; // An Tx pin number + uint8_t ctsPin; // A CTS pin number + uint8_t rtsPin; // An RTS pin number + CMU_Clock_TypeDef uartClock; // A clock source select + UARTDRV_Buffer_FifoQueue_t *rxQueue; // A receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; // A transmit operation queue + volatile bool rxDmaActive; // A receive DMA is currently active + volatile bool txDmaActive; // A transmit DMA is currently active + volatile uint8_t txDmaPaused; // A transmit DMA pause counter + bool IgnoreRestrain; // A transmit does not respect uartdrvFlowControlOff + bool hasTransmitted; // Indicates whether the handle has transmitted data + UARTDRV_FlowControlType_t fcType; // A flow control mode + UARTDRV_UartType_t type; // A type of UART + volatile int em1RequestCount; // A EM1 request count for the handle + sl_sleeptimer_timer_handle_t delayedTxTimer; // A timer to wait for the last byte out + size_t sleep; // Sleep state on isr return + /// @endcond +} UARTDRV_HandleData_t; + +/// Handle pointer +typedef UARTDRV_HandleData_t * UARTDRV_Handle_t; + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t * initData); +#endif + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t * initData); +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t * initData); +#endif +Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle); + +UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle); + +UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *bytesReceived, + UARTDRV_Count_t *bytesRemaining); + +UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *bytesSent, + UARTDRV_Count_t *bytesRemaining); + +uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle); + +uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback); + +Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback); + +Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t maxLength); + +Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type); + +Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle); + +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle); + +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); + +Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); + +Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void); +#endif + +/** @} (end addtogroup uartdrv) */ + +#ifdef __cplusplus +} +#endif +#endif // UARTDRV_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c b/locator_host/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c index f2142db..68021a7 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c @@ -1,3328 +1,3328 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV API implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#define CURRENT_MODULE_NAME "UARTDRV" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#include "uartdrv.h" -#include "em_device.h" -#include "em_core.h" -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -#include "gpiointerrupt.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#include "sl_sleeptimer.h" -#endif - -#include - -//**************************************************************************** - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(_USART_ROUTEPEN_CTSPEN_MASK) -#define UART_HW_FLOW_CONTROL_SUPPORT -#elif (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(USART_CTRLX_CTSEN) -#define UART_HW_FLOW_CONTROL_SUPPORT -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -#define HANDLES_ARE_AVAILABLE 1 -#elif defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -#define HANDLES_ARE_AVAILABLE 1 -#else -#define HANDLES_ARE_AVAILABLE 0 -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define UART_DMA_IRQ DMA_IRQn -#define UART_DMA_IRQHANDLER() DMA_IRQHandler() -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES <= 2) -#define UART_DMA_IRQ LDMA_IRQn -#define UART_DMA_IRQHANDLER() LDMA_IRQHandler() -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES > 2) -#define UART_DMA_IRQ LDMA_CHNL0_IRQn -#define UART_DMA_IRQHANDLER() LDMA_CHNL0_IRQHandler() -#else -#error "No valid UARTDRV DMA engine defined." -#endif - -// UARTDRV use low-level drivers from platform/peripheral. -#if defined(UARTDRV_USE_PERIPHERAL) - -#define uartdrv_gpio_port_t sl_gpio_port_t -#define UARTDRV_GPIO_MODE_DISABLED SL_GPIO_MODE_DISABLED -#define UARTDRV_GPIO_MODE_INPUT SL_GPIO_MODE_INPUT -#define UARTDRV_GPIO_MODE_INPUT_PULL SL_GPIO_MODE_INPUT_PULL -#define UARTDRV_GPIO_MODE_PUSH_PULL SL_GPIO_MODE_PUSH_PULL - -#define uartdrv_gpio_get_pin_input(port, pin) sl_gpio_get_pin_input(port, pin) -#define uartdrv_gpio_set_pin_output(port, pin) sl_gpio_set_pin_output(port, pin) -#define uartdrv_gpio_clear_pin_output(port, pin) sl_gpio_clear_pin_output(port, pin) -#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) sl_gpio_set_pin_mode(port, pin, mode, output) -#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ - sl_gpio_configure_external_interrupt(port, \ - pin, \ - intNo, \ - (risingEdge * SL_GPIO_INTERRUPT_RISING_EDGE \ - & fallingEdge * SL_GPIO_INTERRUPT_FALLING_EDGE \ - & enable * SL_GPIO_INTERRUPT_ENABLE)) - -#define uartdrv_eusart_data_bits_t sl_hal_eusart_data_bits_t -#define uartdrv_eusart_stop_bits_t sl_hal_eusart_stop_bits_t -#define uartdrv_eusart_parity_t sl_hal_eusart_parity_t -#define uartdrv_eusart_ovs_t sl_hal_eusart_ovs_t -#define uartdrv_eusart_majority_vote_t sl_hal_eusart_majority_vote_t - -#define UARTDRV_EUSART_DISABLE 0x0 -#define UARTDRV_EUSART_ENABLE_RX (EUSART_CMD_RXEN | EUSART_CMD_TXDIS) -#define UARTDRV_EUSART_ENABLE_TX (EUSART_CMD_TXEN | EUSART_CMD_RXDIS) -#define UARTDRV_EUSART_ENABLE (EUSART_CMD_RXEN | EUSART_CMD_TXEN) - -#define uartdrv_eusart_get_status(eusart) sl_hal_eusart_get_status(eusart) -#define uartdrv_eusart_tx(eusart, data) sl_hal_eusart_tx(eusart, data) -#define uartdrv_eusart_reset(eusart) sl_hal_eusart_reset(eusart) -#define uartdrv_eusart_enable(eusart, enable) do { if (enable == UARTDRV_EUSART_DISABLE) \ - { sl_hal_eusart_disable(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE_RX) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_disable_tx(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE_TX) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_tx(eusart); sl_hal_eusart_disable_rx(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_enable_tx(eusart); } } while (0) - -// UARTDRV use low-level drivers from platform/emlib. -#else -#define uartdrv_gpio_port_t GPIO_Port_TypeDef - -#define UARTDRV_GPIO_MODE_DISABLED gpioModeDisabled -#define UARTDRV_GPIO_MODE_INPUT gpioModeInput -#define UARTDRV_GPIO_MODE_INPUT_PULL gpioModeInputPull -#define UARTDRV_GPIO_MODE_PUSH_PULL gpioModePushPull - -#define uartdrv_gpio_get_pin_input(port, pin) GPIO_PinInGet(port, pin) -#define uartdrv_gpio_set_pin_output(port, pin) GPIO_PinOutSet(port, pin) -#define uartdrv_gpio_clear_pin_output(port, pin) GPIO_PinOutClear(port, pin) -#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) GPIO_PinModeSet(port, pin, mode, output) -#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ - GPIO_ExtIntConfig(port, pin, intNo, risingEdge, fallingEdge, enable) - -#define uartdrv_eusart_data_bits_t EUSART_Databits_TypeDef -#define uartdrv_eusart_stop_bits_t EUSART_Stopbits_TypeDef -#define uartdrv_eusart_parity_t EUSART_Parity_TypeDef -#define uartdrv_eusart_ovs_t EUSART_OVS_TypeDef -#define uartdrv_eusart_majority_vote_t EUSART_MajorityVote_TypeDef - -#define UARTDRV_EUSART_DISABLE eusartDisable -#define UARTDRV_EUSART_ENABLE_RX eusartEnableRx -#define UARTDRV_EUSART_ENABLE_TX eusartEnableTx -#define UARTDRV_EUSART_ENABLE eusartEnable - -#define uartdrv_eusart_get_status(eusart) EUSART_StatusGet(eusart) -#define uartdrv_eusart_tx(eusart, data) EUSART_Tx(eusart, data) -#define uartdrv_eusart_reset(eusart) EUSART_Reset(eusart) -#define uartdrv_eusart_enable(eusart, enable) EUSART_Enable(eusart, enable) -#endif - -//**************************************************************************** - -#if (HANDLES_ARE_AVAILABLE) -static bool uartdrvHandleIsInitialized = false; -static UARTDRV_Handle_t uartdrvHandle[EMDRV_UARTDRV_MAX_DRIVER_INSTANCES]; -#endif -static bool enableRxWhenSleeping = UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION; - -//**************************************************************************** - -static bool ReceiveDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam); -static bool TransmitDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam); - -/***************************************************************************//** - * @brief Power management functions for the uartdrv. - ******************************************************************************/ -static void em1RequestAdd(UARTDRV_Handle_t handle) -{ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (handle->em1RequestCount == 0) { - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); - } - handle->em1RequestCount++; - CORE_EXIT_ATOMIC(); -#else - handle->em1RequestCount++; -#endif -} - -static void em1RequestRemove(UARTDRV_Handle_t handle) -{ - EFM_ASSERT(handle->em1RequestCount > 0); -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - handle->em1RequestCount--; - if (handle->em1RequestCount == 0) { - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); - } - CORE_EXIT_ATOMIC(); -#else - handle->em1RequestCount--; -#endif -} - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -static void emRequestInit(UARTDRV_Handle_t handle) -{ - handle->em1RequestCount = 0; -} -#endif - -static void emRequestDeinit(UARTDRV_Handle_t handle) -{ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - sl_status_t status; - bool running; - - CORE_ENTER_ATOMIC(); - status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); - if ((status == SL_STATUS_OK) && (running)) { - sl_sleeptimer_stop_timer(&handle->delayedTxTimer); - } - CORE_EXIT_ATOMIC(); -#endif - if (handle->em1RequestCount > 0) { - handle->em1RequestCount = 1; - em1RequestRemove(handle); - } -} - -/***************************************************************************//** - * @brief Get UARTDRV_Handle_t from GPIO pin number (HW FC CTS pin interrupt). - ******************************************************************************/ -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -static UARTDRV_Handle_t HwFcCtsIrqGetDrvHandle(uint32_t gpioPinNo) -{ - uint32_t i; - - for (i = 0; i < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; i++) { - if (uartdrvHandle[i]->ctsPin == gpioPinNo) { - return uartdrvHandle[i]; - } - } - return NULL; -} - -/***************************************************************************//** - * @brief Get CTS pin state. - ******************************************************************************/ -static UARTDRV_FlowControlState_t HwFcGetClearToSendPin(UARTDRV_Handle_t handle) -{ - if (handle->fcType == uartdrvFlowControlHw) { - return (UARTDRV_FlowControlState_t)uartdrv_gpio_get_pin_input(handle->ctsPort, handle->ctsPin); - } else { - return uartdrvFlowControlOn; - } -} - -/***************************************************************************//** - * @brief Manage CTS pin change. - ******************************************************************************/ -static void HwFcManageClearToSend(uint8_t gpioPinNo) -{ - UARTDRV_Handle_t handle = HwFcCtsIrqGetDrvHandle(gpioPinNo); - - if (handle && handle->fcType == uartdrvFlowControlHw) { - // If not auto mode, assign the CTS pin state to the self state - // If auto mode, also control UART Tx enable - handle->fcSelfState = HwFcGetClearToSendPin(handle); - // Only manage DMA if not already paused by SW - if (handle->fcSelfCfg == uartdrvFlowControlAuto && (handle->txDmaPaused == 0)) { - bool active = false; - Ecode_t status = DMADRV_TransferActive(handle->txDmaCh, &active); - if ((handle->fcSelfState == uartdrvFlowControlOn) || handle->IgnoreRestrain) { - handle->IgnoreRestrain = false; - DMADRV_ResumeTransfer(handle->txDmaCh); - } - // Only pause DMA if currently active - else if ((status == ECODE_EMDRV_DMADRV_OK) && active) { - DMADRV_PauseTransfer(handle->txDmaCh); - } - } - } -} - -static Ecode_t FcApplyState(UARTDRV_Handle_t handle) -{ - uint8_t fcSwCode; - - if (handle->fcType == uartdrvFlowControlHw) { - if (handle->fcSelfCfg == uartdrvFlowControlOn) { - // Assert nRTS (application control) - uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); - } else if (handle->fcSelfCfg == uartdrvFlowControlOff) { - // Deassert nRTS (application control) - uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); - } else { // Auto mode - if (handle->fcSelfState == uartdrvFlowControlOn) { - // Assert nRTS - uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); - } else { // Off - // Deassert nRTS - uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); - } - } - } else if (handle->fcType == uartdrvFlowControlSw) { - if (handle->fcSelfState == uartdrvFlowControlOn) { - fcSwCode = UARTDRV_FC_SW_XON; - // Pause transmit to ensure XON transmits immediately - UARTDRV_PauseTransmit(handle); - UARTDRV_ForceTransmit(handle, &fcSwCode, 1); - UARTDRV_ResumeTransmit(handle); - } else { - fcSwCode = UARTDRV_FC_SW_XOFF; - // Pause transmit to ensure XOFF transmits immediately - UARTDRV_PauseTransmit(handle); - UARTDRV_ForceTransmit(handle, &fcSwCode, 1); - UARTDRV_ResumeTransmit(handle); - } - } - return ECODE_EMDRV_UARTDRV_OK; -} -#else -// CTS pin should always read as uartdrvFlowControlOn when HW FC is disabled -#define HwFcGetClearToSendPin(x) uartdrvFlowControlOn -#endif /* EMDRV_UARTDRV_FLOW_CONTROL_ENABLE */ - -/***************************************************************************//** - * @brief Enqueue UART transfer buffer. - ******************************************************************************/ -static Ecode_t EnqueueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t *inputBuffer, - UARTDRV_Buffer_t **queueBuffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used >= queue->size) { - *queueBuffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_FULL; - } - memcpy((void *)&queue->fifo[queue->head], - (const void *)inputBuffer, - sizeof(UARTDRV_Buffer_t)); - *queueBuffer = &queue->fifo[queue->head]; - queue->head = (queue->head + 1) % queue->size; - queue->used++; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Dequeue UART transfer buffer. - ******************************************************************************/ -static Ecode_t DequeueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - queue->tail = (queue->tail + 1) % queue->size; - queue->used--; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Get tail UART transfer buffer. - ******************************************************************************/ -static Ecode_t GetTailBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Enable UART transmitter. - ******************************************************************************/ -static void EnableTransmitter(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif // LEUART || EUART || EUSART - { - // Enable Tx - handle->peripheral.uart->CMD = USART_CMD_TXEN; - // Wait for Tx to be enabled - while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXENS)) { - } - - // Enable Tx route -#if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_TXPEN; -#elif defined(USART_ROUTE_TXPEN) - handle->peripheral.uart->ROUTE |= USART_ROUTE_TXPEN; -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; -#endif - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Enable Tx - handle->peripheral.leuart->CMD = LEUART_CMD_TXEN; - // Wait for Tx to be enabled - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS)) { - } - - // Enable Tx route -#if defined(LEUART_ROUTEPEN_TXPEN) - handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN; -#else - handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_TXPEN; -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); - } -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; -#endif - } -#endif -} - -/***************************************************************************//** - * @brief Disable UART transmitter. - ******************************************************************************/ -static void DisableTransmitter(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Disable Tx route -#if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_TXPEN; -#elif defined(USART_ROUTE_TXPEN) - handle->peripheral.uart->ROUTE &= ~USART_ROUTE_TXPEN; -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; -#endif - // Disable Tx - handle->peripheral.uart->CMD = USART_CMD_TXDIS; - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Disable Tx route -#if defined(LEUART_ROUTEPEN_TXPEN) - handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_TXPEN; -#else - handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_TXPEN; -#endif - // Disable Tx - handle->peripheral.leuart->CMD = LEUART_CMD_TXDIS; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); - } -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; -#endif - } -#endif -} - -/***************************************************************************//** - * @brief Enable UART receiver. - ******************************************************************************/ -static void EnableReceiver(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Enable Rx - handle->peripheral.uart->CMD = USART_CMD_RXEN; - // Wait for Rx to be enabled - while (!(handle->peripheral.uart->STATUS & USART_STATUS_RXENS)) { - } - - // Enable Rx route -#if defined(USART_ROUTEPEN_RXPEN) - handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_RXPEN) - handle->peripheral.uart->ROUTE |= USART_ROUTE_RXPEN; -#elif defined(GPIO_USART_ROUTEEN_RXPEN) - GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; -#endif - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Enable Rx - handle->peripheral.leuart->CMD = LEUART_CMD_RXEN; - // Wait for Rx to be enabled - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS)) { - } - - // Enable Rx route -#if defined(LEUART_ROUTEPEN_RXPEN) - handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN; -#else - handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_RXPEN; -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); - } - } -#endif -} - -/***************************************************************************//** - * @brief Disable UART receiver. - ******************************************************************************/ -static void DisableReceiver(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Disable Rx route -#if defined(USART_ROUTEPEN_RXPEN) - handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_RXPEN) - handle->peripheral.uart->ROUTE &= ~USART_ROUTE_RXPEN; -#elif defined(GPIO_USART_ROUTEEN_RXPEN) - GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; -#endif - // Disable Rx - handle->peripheral.uart->CMD = USART_CMD_RXDIS; - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for prevous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Disable Rx route -#if defined(LEUART_ROUTEPEN_RXPEN) - handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_RXPEN; -#else - handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_RXPEN; -#endif - // Disable Rx - handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); - } - } -#endif -} - -/***************************************************************************//** - * @brief Start a UART DMA receive operation. - ******************************************************************************/ -static void StartReceiveDma(UARTDRV_Handle_t handle, - UARTDRV_Buffer_t *buffer) -{ - void *rxPort = NULL; - - handle->rxDmaActive = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - rxPort = (void *)&(handle->peripheral.uart->RXDATA); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - rxPort = (void *)&(handle->peripheral.leuart->RXDATA); -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - rxPort = (void *)&(handle->peripheral.euart->RXDATA); -#endif - } else { - handle->rxDmaActive = false; - return; - } - - if (enableRxWhenSleeping) { - em1RequestAdd(handle); - } - DMADRV_PeripheralMemory(handle->rxDmaCh, - handle->rxDmaSignal, - buffer->data, - rxPort, - true, - buffer->transferCount, - dmadrvDataSize1, - ReceiveDmaComplete, - handle); -} - -/***************************************************************************//** - * @brief Start a UART DMA transmit operation. - ******************************************************************************/ -static void StartTransmitDma(UARTDRV_Handle_t handle, - UARTDRV_Buffer_t *buffer) -{ - void *txPort = NULL; - - handle->txDmaActive = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txPort = (void *)&(handle->peripheral.uart->TXDATA); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - // Set TX DMA wakeup request. Needed for transmit while in EM2. - handle->peripheral.leuart->CTRL |= LEUART_CTRL_TXDMAWU; - txPort = (void *)&(handle->peripheral.leuart->TXDATA); -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - txPort = (void *)&(handle->peripheral.euart->TXDATA); -#endif - } else { - handle->txDmaActive = false; - return; - } - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - sl_status_t status; - bool running; - - CORE_ENTER_ATOMIC(); - status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); - if ((status == 0) && (running)) { - sl_sleeptimer_stop_timer(&handle->delayedTxTimer); - em1RequestRemove(handle); - } - CORE_EXIT_ATOMIC(); -#if !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif -#endif - - em1RequestAdd(handle); - DMADRV_MemoryPeripheral(handle->txDmaCh, - handle->txDmaSignal, - txPort, - buffer->data, - true, - buffer->transferCount, - dmadrvDataSize1, - TransmitDmaComplete, - handle); -} - -/***************************************************************************//** - * @brief DMA transfer completion callback. Called by the DMA interrupt handler. - ******************************************************************************/ -static bool ReceiveDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam) -{ - CORE_DECLARE_IRQ_STATE; - UARTDRV_Handle_t handle; - UARTDRV_Buffer_t *buffer; - Ecode_t status; - (void)channel; - (void)sequenceNo; - handle = (UARTDRV_Handle_t)userParam; - status = GetTailBuffer(handle->rxQueue, &buffer); - - if (enableRxWhenSleeping) { - em1RequestRemove(handle); - } - - // If an abort was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return true; - } - - EFM_ASSERT(buffer != NULL); - -#if defined(USART_IF_FERR) - if (handle->type == uartdrvUartTypeUart - && (handle->peripheral.uart->IF & USART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; -#if defined(USART_HAS_SET_CLEAR) - handle->peripheral.uart->IF_CLR = USART_IF_FERR; -#else - handle->peripheral.uart->IFC = USART_IFC_FERR; -#endif - } else -#endif -#if defined(USART_IF_PERR) - if (handle->type == uartdrvUartTypeUart - && (handle->peripheral.uart->IF & USART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; -#if defined(USART_HAS_SET_CLEAR) - handle->peripheral.uart->IF_CLR = USART_IF_PERR; -#else - handle->peripheral.uart->IFC = USART_IFC_PERR; -#endif - } else -#endif -#if defined(LEUART_IF_FERR) - if (handle->type == uartdrvUartTypeLeuart - && (handle->peripheral.leuart->IF & LEUART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.leuart->IFC = LEUART_IFC_FERR; - } else -#endif -#if defined(LEUART_IF_PERR) - if (handle->type == uartdrvUartTypeLeuart - && (handle->peripheral.leuart->IF & LEUART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.leuart->IFC = LEUART_IFC_PERR; - } else -#endif -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) - if (handle->type == uartdrvUartTypeEuart - && (handle->peripheral.euart->IF & EUSART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.euart->IF_CLR = EUSART_IF_FERR; - } else if (handle->type == uartdrvUartTypeEuart - && (handle->peripheral.euart->IF & EUSART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.euart->IF_CLR = EUSART_IF_PERR; - } else -#endif - { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; - buffer->itemsRemaining = 0; - } - - CORE_ENTER_ATOMIC(); - - if (buffer->callback != NULL) { - buffer->callback(handle, buffer->transferStatus, buffer->data, buffer->transferCount - buffer->itemsRemaining); - } - // Dequeue the current tail Rx operation, check if more in queue - DequeueBuffer(handle->rxQueue, &buffer); - - if (handle->rxQueue->used > 0) { - GetTailBuffer(handle->rxQueue, &buffer); - StartReceiveDma(handle, buffer); - } else { -#if EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcSelfState = uartdrvFlowControlOff; - FcApplyState(handle); -#endif - handle->rxDmaActive = false; - - if (handle->fcType != uartdrvFlowControlHwUart) { - DisableReceiver(handle); - } - } - CORE_EXIT_ATOMIC(); - return true; -} - -/***************************************************************************//** - * @brief Calculate the number of sleeptimer ticks to flush the uart tx buffers. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -static uint32_t calculateSleeptimerTicksToFlushTxBuffers(UARTDRV_Handle_t handle) -{ - uint32_t baud = 0; - uint32_t ticks = 0; - - switch (handle->type) { -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - case uartdrvUartTypeLeuart: - baud = LEUART_BaudrateGet(handle->peripheral.leuart); - break; -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - case uartdrvUartTypeEuart: - baud = EUSART_BaudrateGet(handle->peripheral.euart); - break; -#endif -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - case uartdrvUartTypeUart: - default: - baud = USART_BaudrateGet(handle->peripheral.uart); - break; -#endif - } - - if (baud != 0) { // Avoid division by 0 - // Calculate the number of sleeptimer ticks for: - // 3 bytes: two in FIFO and one in shift register. - // 12 bits pr byte: one start bit, 8 data bits, parity and 2 stop bits. - ticks = (sl_sleeptimer_get_timer_frequency() * 3 * 12) / baud; - // Round up. - ticks++; - } - - return ticks; -} -#endif - -/***************************************************************************//** - * @brief Delayed transmit complete timer callback. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -static void TransmitDmaCompleteDelayed(sl_sleeptimer_timer_handle_t *timer_handle, void *userParam) -{ - (void)timer_handle; - UARTDRV_Handle_t uartdrv_handle = (UARTDRV_Handle_t)userParam; - uint32_t reg; - bool txComplete = false; - - // Check if transmit is completed by checking the uart registers. - switch (uartdrv_handle->type) { -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - case uartdrvUartTypeLeuart: - reg = uartdrv_handle->peripheral.leuart->STATUS; - txComplete = reg & LEUART_STATUS_TXC; - break; -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - case uartdrvUartTypeEuart: - reg = uartdrv_handle->peripheral.euart->STATUS; - txComplete = reg & EUSART_STATUS_TXC; - break; -#endif -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - case uartdrvUartTypeUart: - default: - reg = uartdrv_handle->peripheral.uart->STATUS; - txComplete = reg & USART_STATUS_TXC; - break; -#endif - } - - if (txComplete) { - // Remove the power manager request if completed. - em1RequestRemove(uartdrv_handle); -#if !defined(SL_CATALOG_KERNEL_PRESENT) - uartdrv_handle->sleep = SL_POWER_MANAGER_SLEEP; -#endif - } else { - // Restart the timer if not completed. - // May be the case if flow control is used. - uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(uartdrv_handle); - sl_sleeptimer_start_timer(&uartdrv_handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); - } -} -#endif - -/***************************************************************************//** - * @brief DMA transfer completion callback. Called by the DMA interrupt handler. - ******************************************************************************/ -static bool TransmitDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam) -{ - CORE_DECLARE_IRQ_STATE; - UARTDRV_Handle_t handle; - UARTDRV_Buffer_t *buffer; - Ecode_t status; - (void)channel; - (void)sequenceNo; - - handle = (UARTDRV_Handle_t)userParam; - status = GetTailBuffer(handle->txQueue, &buffer); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(handle); - sl_sleeptimer_start_timer(&handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); -#else - em1RequestRemove(handle); -#endif - - // If an abort was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return true; - } - - EFM_ASSERT(buffer != NULL); - - buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; - buffer->itemsRemaining = 0; - - CORE_ENTER_ATOMIC(); - - if (buffer->callback != NULL) { - buffer->callback(handle, ECODE_EMDRV_UARTDRV_OK, buffer->data, buffer->transferCount); - } - // Dequeue the current tail Tx operation, check if more in queue - DequeueBuffer(handle->txQueue, &buffer); - - if (handle->txQueue->used > 0) { - GetTailBuffer(handle->txQueue, &buffer); - StartTransmitDma(handle, buffer); - } else { - handle->txDmaActive = false; -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - if (handle->type == uartdrvUartTypeLeuart) { - // Clear TX DMA Wakeup request - handle->peripheral.leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; - } -#endif - } - CORE_EXIT_ATOMIC(); - return true; -} - -/***************************************************************************//** - * @brief Parameter checking function for blocking transfer API functions. - ******************************************************************************/ -static Ecode_t CheckParams(UARTDRV_Handle_t handle, void *data, uint32_t count) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if ((data == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - return ECODE_EMDRV_UARTDRV_OK; -} - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/***************************************************************************//** - * @brief Store U(S)ART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t * initData) -{ -#if defined(_USART_ROUTELOC0_MASK) - if (false) { -#if defined(USARTRF0) - } else if (handle->peripheral.uart == USARTRF0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocationRx); -#endif -#if defined(USARTRF1) - } else if (handle->peripheral.uart == USARTRF1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART0) - } else if (handle->peripheral.uart == USART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART1) - } else if (handle->peripheral.uart == USART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART1_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART2) - } else if (handle->peripheral.uart == USART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART2_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART2_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART3) - } else if (handle->peripheral.uart == USART3) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART3_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART3_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART3_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART3_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART4) - } else if (handle->peripheral.uart == USART4) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART4_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART4_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART4_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART4_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART5) - } else if (handle->peripheral.uart == USART5) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART5_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART5_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART5_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART5_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART0) - } else if (handle->peripheral.uart == UART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART1) - } else if (handle->peripheral.uart == UART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART1_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART2) - } else if (handle->peripheral.uart == UART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART2_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART2_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART2_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART2_RX_PIN(initData->portLocationRx); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_USART_ROUTE_MASK) - if (false) { -#if defined(USARTRF0) - } else if (handle->peripheral.uart == USARTRF0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocation); - handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocation); - handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocation); -#endif -#if defined(USARTRF1) - } else if (handle->peripheral.uart == USARTRF1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocation); - handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocation); - handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocation); -#endif -#if defined(USART0) - } else if (handle->peripheral.uart == USART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocation); - handle->txPin = AF_USART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART0_RX_PIN(initData->portLocation); -#endif -#if defined(USART1) - } else if (handle->peripheral.uart == USART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocation); - handle->txPin = AF_USART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART1_RX_PIN(initData->portLocation); -#endif -#if defined(USART2) - } else if (handle->peripheral.uart == USART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocation); - handle->txPin = AF_USART2_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART2_RX_PIN(initData->portLocation); -#endif -#if defined(UART0) - } else if (handle->peripheral.uart == UART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocation); - handle->txPin = AF_UART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_UART0_RX_PIN(initData->portLocation); -#endif -#if defined(UART1) - } else if (handle->peripheral.uart == UART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocation); - handle->txPin = AF_UART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_UART1_RX_PIN(initData->portLocation); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_GPIO_USART_ROUTEEN_MASK) - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; -#endif - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif // UART || USART - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief Store LEUART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t * initData) -{ -#if defined(_LEUART_ROUTELOC0_MASK) - if (false) { -#if defined(LEUART0) - } else if (handle->peripheral.leuart == LEUART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_LEUART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(LEUART1) - } else if (handle->peripheral.leuart == LEUART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_LEUART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocationRx); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_USART_ROUTE_MASK) - if (false) { -#if defined(LEUART0) - } else if (handle->peripheral.leuart == LEUART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocation); - handle->txPin = AF_LEUART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocation); -#endif -#if defined(LEUART1) - } else if (handle->peripheral.leuart == LEUART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocation); - handle->txPin = AF_LEUART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocation); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_GPIO_USART_ROUTEEN_MASK) - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; -#endif - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -/***************************************************************************//** - * @brief Store EUART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t * initData) -{ - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief Configure/deconfigure U(S)ART GPIO pins. - ******************************************************************************/ -static Ecode_t ConfigGpio(UARTDRV_Handle_t handle, bool enable) -{ - if (enable) { - uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_PUSH_PULL, 1); - uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_INPUT_PULL, 1); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); - uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, true); - } else if (handle->fcType == uartdrvFlowControlHwUart) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); - } -#endif - } else { - uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_DISABLED, 0); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, false); - } else if (handle->fcType == uartdrvFlowControlHwUart) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - } -#endif - } - return ECODE_EMDRV_UARTDRV_OK; -} - -#if (HANDLES_ARE_AVAILABLE) -/***************************************************************************//** - * @brief Add handle to handle array. - ******************************************************************************/ -static Ecode_t addHandle(UARTDRV_Handle_t handle) -{ - bool handleIsSet; - uint32_t handleIdx; - - // Set handler pointer in handler array - if (!uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - uartdrvHandle[handleIdx] = NULL; - } - uartdrvHandleIsInitialized = true; - } - - // Check if its already in the array - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == handle) { - return ECODE_EMDRV_UARTDRV_OK; - } - } - - // Insert handle - handleIsSet = false; - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == NULL) { - uartdrvHandle[handleIdx] = handle; - handleIsSet = true; - break; - } - } - - if (!handleIsSet) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Remove handle from handle array. - ******************************************************************************/ -static Ecode_t removeHandle(UARTDRV_Handle_t handle) -{ - uint32_t handleIdx; - - if (uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == handle) { - uartdrvHandle[handleIdx] = NULL; - break; - } - } - } - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief Initialize FIFO queues for a handle. - ******************************************************************************/ -static void InitializeQueues(UARTDRV_Handle_t handle, - UARTDRV_Buffer_FifoQueue_t * rxQueue, - UARTDRV_Buffer_FifoQueue_t * txQueue) -{ - handle->rxQueue = rxQueue; - handle->rxQueue->head = 0; - handle->rxQueue->tail = 0; - handle->rxQueue->used = 0; - handle->rxDmaActive = false; - - handle->txQueue = txQueue; - handle->txQueue->head = 0; - handle->txQueue->tail = 0; - handle->txQueue->used = 0; - handle->txDmaActive = false; - - handle->IgnoreRestrain = false; -} - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -/***************************************************************************//** - * @brief Initialize GPIO-driven flow control. - ******************************************************************************/ -static void InitializeGpioFlowControl(UARTDRV_Handle_t handle) -{ - GPIOINT_CallbackRegister(handle->ctsPin, HwFcManageClearToSend); - GPIOINT_Init(); - handle->fcPeerState = uartdrvFlowControlOn; - handle->fcSelfState = uartdrvFlowControlOn; - handle->fcSelfCfg = uartdrvFlowControlAuto; - FcApplyState(handle); -} -#endif - -/***************************************************************************//** - * @brief Initialize DMA channels for a handle. - ******************************************************************************/ -static Ecode_t InitializeDma(UARTDRV_Handle_t handle) -{ - // Initialize DMA. - DMADRV_Init(); - - if (DMADRV_AllocateChannel(&handle->txDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { - return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; - } - - if (DMADRV_AllocateChannel(&handle->rxDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { - return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -/// @endcond - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/***************************************************************************//** - * @brief - * Initialize a U(S)ART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitUart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - emRequestInit(handle); - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - - handle->peripheral.uart = initData->port; - handle->type = uartdrvUartTypeUart; -#if defined(_GPIO_USART_ROUTEEN_MASK) - handle->uartNum = initData->uartNum; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(USART0) - } else if (initData->port == USART0) { - handle->uartClock = cmuClock_USART0; - handle->txDmaSignal = dmadrvPeripheralSignal_USART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART0_RXDATAV; -#endif -#if defined(USART1) - } else if (initData->port == USART1) { - handle->uartClock = cmuClock_USART1; - handle->txDmaSignal = dmadrvPeripheralSignal_USART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART1_RXDATAV; -#endif -#if defined(USART2) - } else if (initData->port == USART2) { - handle->uartClock = cmuClock_USART2; - handle->txDmaSignal = dmadrvPeripheralSignal_USART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART2_RXDATAV; -#endif -#if defined(USART3) - } else if (initData->port == USART3) { - handle->uartClock = cmuClock_USART3; - handle->txDmaSignal = dmadrvPeripheralSignal_USART3_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART3_RXDATAV; -#endif -#if defined(USART4) - } else if (initData->port == USART4) { - handle->uartClock = cmuClock_USART4; - handle->txDmaSignal = dmadrvPeripheralSignal_USART4_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART4_RXDATAV; -#endif -#if defined(USART5) - } else if (initData->port == USART5) { - handle->uartClock = cmuClock_USART5; - handle->txDmaSignal = dmadrvPeripheralSignal_USART5_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART5_RXDATAV; -#endif -#if defined(UART0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (initData->port == UART0) { - handle->uartClock = cmuClock_UART0; - handle->txDmaSignal = dmadrvPeripheralSignal_UART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART0_RXDATAV; -#endif -#if defined(UART1) - } else if (initData->port == UART1) { - handle->uartClock = cmuClock_UART1; - handle->txDmaSignal = dmadrvPeripheralSignal_UART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART1_RXDATAV; -#endif -#if defined(UART2) - } else if (initData->port == UART2) { - handle->uartClock = cmuClock_UART2; - handle->txDmaSignal = dmadrvPeripheralSignal_UART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART2_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - usartInit.baudrate = initData->baudRate; - usartInit.stopbits = initData->stopBits; - usartInit.parity = initData->parity; - usartInit.oversampling = initData->oversampling; -#if defined(USART_CTRL_MVDIS) - usartInit.mvdis = initData->mvdis; -#endif - - // UARTDRV is fixed at 8 bit frames. - usartInit.databits = (USART_Databits_TypeDef)USART_FRAME_DATABITS_EIGHT; - - // Enable clocks -#if defined(_CMU_HFPERCLKEN0_MASK) - CMU_ClockEnable(cmuClock_HFPER, true); -#endif - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(handle->uartClock, true); - - // Init U(S)ART to default async config. - // Rx/Tx enable is done on demand - usartInit.enable = usartDisable; - USART_InitAsync(initData->port, &usartInit); - -#if defined(USART_ROUTEPEN_TXPEN) - initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 - & ~(_USART_ROUTELOC0_TXLOC_MASK - | _USART_ROUTELOC0_RXLOC_MASK)) - | (initData->portLocationTx - << _USART_ROUTELOC0_TXLOC_SHIFT) - | (initData->portLocationRx - << _USART_ROUTELOC0_RXLOC_SHIFT); - - initData->port->ROUTEPEN = USART_ROUTEPEN_TXPEN - | USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_TXPEN) - initData->port->ROUTE = USART_ROUTE_TXPEN - | USART_ROUTE_RXPEN - | (initData->portLocation - << _USART_ROUTE_LOCATION_SHIFT); -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN - | GPIO_USART_ROUTEEN_RXPEN; - GPIO->USARTROUTE[initData->uartNum].TXROUTE = - (initData->txPort << _GPIO_USART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_USART_TXROUTE_PIN_SHIFT); - GPIO->USARTROUTE[initData->uartNum].RXROUTE = - (initData->rxPort << _GPIO_USART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_USART_RXROUTE_PIN_SHIFT); -#endif - - if ((retVal = SetupGpioUart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - CORE_ENTER_ATOMIC(); - - // Configure hardware flow control pins and interrupt vectors -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHwUart) { -#if defined(UART_HW_FLOW_CONTROL_SUPPORT) -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) - initData->port->ROUTELOC1 = (initData->portLocationCts << _USART_ROUTELOC1_CTSLOC_SHIFT) - | (initData->portLocationRts << _USART_ROUTELOC1_RTSLOC_SHIFT); - initData->port->CTRLX |= USART_CTRLX_CTSEN; - initData->port->ROUTEPEN |= USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN; -#elif defined(USART_CTRLX_CTSEN) - GPIO->USARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; - initData->port->CTRLX_SET = USART_CTRLX_CTSEN; - GPIO->USARTROUTE_SET[initData->uartNum].RTSROUTE = - (initData->rtsPort << _GPIO_USART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_USART_RTSROUTE_PIN_SHIFT); - GPIO->USARTROUTE_SET[initData->uartNum].CTSROUTE = - (initData->ctsPort << _GPIO_USART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_USART_CTSROUTE_PIN_SHIFT); -#endif -#else - // Attempting to use USART hardware flow control on a device that does not - // support it. - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; -#endif - } else if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - - // Clear any false IRQ/DMA request - USART_IntClear(initData->port, ~0x0); - - // Enable Tx permanently as the Tx circuit consumes very little energy. - // Rx is enabled on demand as the Rx circuit consumes some energy due to - // continuous (over)sampling. - if (initData->fcType == uartdrvFlowControlHwUart) { - // Rx must be enabled permanently when using USART hw flow control - USART_Enable(initData->port, usartEnable); - } else { - USART_Enable(initData->port, usartEnableTx); - } - - // Discard false frames and/or IRQs - initData->port->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - // Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif // UART || USART - -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Initialize a LEUART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitLeuart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - LEUART_Init_TypeDef leuartInit = LEUART_INIT_DEFAULT; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - if (initData->fcType == uartdrvFlowControlHwUart) { - // LEUART doesn't support peripheral hw flow control - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - - handle->peripheral.leuart = initData->port; - handle->type = uartdrvUartTypeLeuart; -#if defined(_GPIO_USART_ROUTEEN_MASK) - handle->uartNum = initData->uartNum; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(LEUART0) - } else if (initData->port == LEUART0) { - handle->uartClock = cmuClock_LEUART0; - handle->txDmaSignal = dmadrvPeripheralSignal_LEUART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART0_RXDATAV; -#endif -#if defined(LEUART1) - } else if (initData->port == LEUART1) { - handle->uartClock = cmuClock_LEUART1; - handle->txDmaSignal = dmadrvPeripheralSignal_LEUART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART1_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - leuartInit.baudrate = initData->baudRate; - leuartInit.stopbits = initData->stopBits; - leuartInit.parity = initData->parity; - - // UARTDRV is fixed at 8 bit frames. - leuartInit.databits = (LEUART_Databits_TypeDef)LEUART_CTRL_DATABITS_EIGHT; - - // Enable clocks -#if defined(_CMU_HFPERCLKEN0_MASK) - CMU_ClockEnable(cmuClock_HFPER, true); -#endif - CMU_ClockEnable(cmuClock_GPIO, true); -#if defined(_CMU_HFBUSCLKEN0_MASK) || defined(CMU_HFCORECLKEN0_LE) - CMU_ClockEnable(cmuClock_HFLE, true); -#endif - - // Only try to use LF clock if LFXO or LFRCO is enabled and requested baudrate is low - if (CMU->STATUS & CMU_STATUS_LFXOENS - && (leuartInit.baudrate <= SystemLFXOClockGet())) { - CMU_CLOCK_SELECT_SET(LFB, LFXO); - } else if (CMU->STATUS & CMU_STATUS_LFRCOENS - && (leuartInit.baudrate <= SystemLFRCOClockGet())) { - CMU_CLOCK_SELECT_SET(LFB, LFRCO); - } else { - // Try to figure out the prescaler that will give us the best stability - CMU_CLOCK_SELECT_SET(LFB, HFCLKLE); - -#if defined(_SILICON_LABS_32B_SERIES_0) - // Attainable baudrate lies between refclk and refclk/128. For maximum - // accuracy, we want the reference clock to be as high as possible. - uint32_t refclk = CMU_ClockFreqGet(cmuClock_LFB); - uint8_t divisor = 0; - - while (leuartInit.baudrate <= (refclk >> (divisor + 7))) { - divisor++; - } - - // If we ran out of stretch on the clock division, error out. - if (divisor > (_CMU_LFBPRESC0_LEUART0_MASK >> _CMU_LFBPRESC0_LEUART0_SHIFT)) { - return ECODE_EMDRV_UARTDRV_CLOCK_ERROR; - } - CMU_ClockDivSet(handle->uartClock, (CMU_ClkDiv_TypeDef) (1 << divisor)); -#elif defined(_SILICON_LABS_32B_SERIES_1) - // Clock divider in LEUARTn is large enough for any baudrate. -#endif - } - - CMU_ClockEnable(handle->uartClock, true); - - // Init LEUART to default async config. - // Rx/Tx enable is done on demand - leuartInit.enable = leuartDisable; - LEUART_Init(initData->port, &leuartInit); - -#if defined(LEUART_ROUTEPEN_TXPEN) - initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 - & ~(_LEUART_ROUTELOC0_TXLOC_MASK - | _LEUART_ROUTELOC0_RXLOC_MASK)) - | (initData->portLocationTx - << _LEUART_ROUTELOC0_TXLOC_SHIFT) - | (initData->portLocationRx - << _LEUART_ROUTELOC0_RXLOC_SHIFT); - - initData->port->ROUTEPEN = LEUART_ROUTEPEN_TXPEN - | LEUART_ROUTEPEN_RXPEN; -#else - initData->port->ROUTE = LEUART_ROUTE_TXPEN - | LEUART_ROUTE_RXPEN - | (initData->portLocation - << _LEUART_ROUTE_LOCATION_SHIFT); -#endif - - if ((retVal = SetupGpioLeuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - CORE_ENTER_ATOMIC(); - - // Configure hardware flow control pins and interrupt vectors -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - - // Clear any false IRQ/DMA request - LEUART_IntClear(initData->port, ~0x0); - - // Enable Tx permanently as the Tx circuit consumes very little energy. - // Rx is enabled on demand as the Rx circuit consumes some energy due to - // continuous (over)sampling. - LEUART_Enable(initData->port, leuartEnableTx); - - // Wait for previous write (TXEN) to sync before clearing FIFOs - while ((initData->port->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Discard false frames and/or IRQs - initData->port->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; - initData->port->CTRL |= LEUART_CTRL_RXDMAWU; - - // Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - // Wait for everything to be synchronized - while (initData->port->SYNCBUSY != 0U) { - } - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) || defined(DOXYGEN) - -/***************************************************************************//** - * @brief - * Initialize a EUART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitEuart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - #if defined(UARTDRV_USE_PERIPHERAL) - sl_hal_eusart_uart_config_t uartInit = SL_HAL_EUSART_UART_INIT_DEFAULT_HF; - sl_hal_eusart_uart_advanced_config_t uartAdvancedInit = SL_HAL_EUSART_UART_ADVANCED_INIT_DEFAULT; - #else - EUSART_UartInit_TypeDef uartInit = EUSART_UART_INIT_DEFAULT_HF; - EUSART_AdvancedInit_TypeDef uartAdvancedInit = EUSART_ADVANCED_INIT_DEFAULT; - #endif - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - - handle->peripheral.euart = initData->port; - handle->type = uartdrvUartTypeEuart; - handle->uartNum = initData->uartNum; - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(EUART0) - } else if (initData->port == EUART0) { - handle->uartClock = cmuClock_EUART0; - handle->txDmaSignal = dmadrvPeripheralSignal_EUART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUART0_RXDATAV; -#endif -#if defined(EUSART0) - } else if (initData->port == EUSART0) { - handle->uartClock = cmuClock_EUSART0; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART0_RXDATAV; -#endif -#if defined(EUSART1) - } else if (initData->port == EUSART1) { - handle->uartClock = cmuClock_EUSART1; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART1_RXDATAV; -#endif -#if defined(EUSART2) - } else if (initData->port == EUSART2) { - handle->uartClock = cmuClock_EUSART2; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART2_RXDATAV; -#endif -#if defined(EUSART3) - } else if (initData->port == EUSART3) { - handle->uartClock = cmuClock_EUSART3; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART3_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART3_RXDATAV; -#endif -#if defined(EUSART4) - } else if (initData->port == EUSART4) { - handle->uartClock = cmuClock_EUSART4; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART4_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART4_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - // Common configurations to all EUART/EUSART instances. - handle->txDmaActive = false; - handle->rxDmaActive = false; - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - // Enable clocks. - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(handle->uartClock, true); - if (initData->useLowFrequencyMode) { - CMU_ClockEnable(cmuClock_LFRCO, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - CMU_ClockEnable(cmuClock_EM23GRPACLK, true); - CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFRCO); -#if defined(EUART_PRESENT) - CMU_CLOCK_SELECT_SET(EUART0, EM23GRPACLK); -#elif defined (EUSART_PRESENT) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM23GRPACLK); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ - || defined(_SILICON_LABS_32B_SERIES_3) - CMU_CLOCK_SELECT_SET(EUSART0CLK, LFRCO); -#else - #error "Please assign a LF clock to EUSART instance" -#endif - } else { -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - CMU_ClockEnable(cmuClock_EM01GRPACLK, true); -#if defined(EUART_PRESENT) - CMU_CLOCK_SELECT_SET(EUART0CLK, EM01GRPACLK); -#elif defined (EUSART_PRESENT) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPACLK); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ - || defined(_SILICON_LABS_32B_SERIES_3) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPCCLK); -#else - #error "Please assign a HF clock to EUSART instance" -#endif - } - -#if defined(EUART_COUNT) && (EUART_COUNT > 0) - GPIO->EUARTROUTE->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; - GPIO->EUARTROUTE->TXROUTE = (initData->txPort - << _GPIO_EUART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_EUART_TXROUTE_PIN_SHIFT); - GPIO->EUARTROUTE->RXROUTE = (initData->rxPort - << _GPIO_EUART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_EUART_RXROUTE_PIN_SHIFT); -#elif defined(EUSART_COUNT) && (EUSART_COUNT > 0) - GPIO->EUSARTROUTE[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; - GPIO->EUSARTROUTE[initData->uartNum].TXROUTE = (initData->txPort - << _GPIO_EUSART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); - GPIO->EUSARTROUTE[initData->uartNum].RXROUTE = (initData->rxPort - << _GPIO_EUSART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); - #endif - - if ((retVal = SetupGpioEuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - -#if defined(UARTDRV_USE_PERIPHERAL) - // UARTDRV is fixed at 8 bit frames. - uartInit.data_bits = SL_HAL_EUSART_DATA_BITS_8; - - uartInit.clock_div = sl_hal_eusart_uart_calculate_clock_div(CMU_ClockFreqGet(cmuClock_EUSART0), initData->baudRate, initData->oversampling); - uartInit.stop_bits = initData->stopBits; - uartInit.parity = initData->parity; - uartInit.oversampling = initData->oversampling; - uartInit.majority_vote = initData->mvdis; - - uartAdvancedInit.dma_wakeup_on_rx = true; - uartAdvancedInit.dma_wakeup_on_tx = false; - uartInit.advanced_config = &uartAdvancedInit; -#else - // UARTDRV is fixed at 8 bit frames. - uartInit.databits = eusartDataBits8; - - uartInit.baudrate = initData->baudRate; - uartInit.stopbits = initData->stopBits; - uartInit.parity = initData->parity; - uartInit.oversampling = initData->oversampling; - uartInit.majorityVote = initData->mvdis; - - uartAdvancedInit.dmaWakeUpOnRx = true; - uartAdvancedInit.dmaWakeUpOnTx = false; - uartInit.advancedSettings = &uartAdvancedInit; -#endif - - CORE_ENTER_ATOMIC(); - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHwUart) { -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; - GPIO->EUARTROUTE_SET[0].RTSROUTE = - (initData->rtsPort << _GPIO_EUART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_EUART_RTSROUTE_PIN_SHIFT); - GPIO->EUARTROUTE_SET[0].CTSROUTE = - (initData->ctsPort << _GPIO_EUART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_EUART_CTSROUTE_PIN_SHIFT); -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; - GPIO->EUSARTROUTE_SET[initData->uartNum].RTSROUTE = - (initData->rtsPort << _GPIO_EUSART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_EUSART_RTSROUTE_PIN_SHIFT); - GPIO->EUSARTROUTE_SET[initData->uartNum].CTSROUTE = - (initData->ctsPort << _GPIO_EUSART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_EUSART_CTSROUTE_PIN_SHIFT); -#endif - uartAdvancedInit.hwFlowControl = eusartHwFlowControlCtsAndRts; - } else if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - -#if defined(UARTDRV_USE_PERIPHERAL) - if (initData->useLowFrequencyMode) { - sl_hal_eusart_init_uart_lf(initData->port, &uartInit); - } else { - sl_hal_eusart_init_uart_hf(initData->port, &uartInit); - } - - // Set Tx enable to follow USART implementation. - uartdrv_eusart_enable(initData->port, UARTDRV_EUSART_ENABLE_TX); -#else - // Set Tx enable to follow USART implementation. - uartInit.enable = UARTDRV_EUSART_ENABLE_TX; - - if (initData->useLowFrequencyMode) { - EUSART_UartInitLf(initData->port, &uartInit); - } else { - EUSART_UartInitHf(initData->port, &uartInit); - } -#endif - -// Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief - * Deinitialize a UART driver instance. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - // Stop DMA transfers. - UARTDRV_Abort(handle, uartdrvAbortAll); - - // Do not leave any peer restrained on DeInit - UARTDRV_FlowControlSet(handle, uartdrvFlowControlOn); - - ConfigGpio(handle, false); - -#if (HANDLES_ARE_AVAILABLE) - removeHandle(handle); -#endif - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - handle->peripheral.uart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS; -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - LEUART_Reset(handle->peripheral.leuart); - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS; - -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - uartdrv_eusart_reset(handle->peripheral.euart); -#endif - } - - CMU_ClockEnable(handle->uartClock, false); - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - GPIOINT_CallbackRegister(handle->ctsPin, NULL); - } -#endif - - DMADRV_FreeChannel(handle->txDmaCh); - DMADRV_FreeChannel(handle->rxDmaCh); - DMADRV_DeInit(); - - handle->rxQueue->head = 0; - handle->rxQueue->tail = 0; - handle->rxQueue->used = 0; - - handle->txQueue->head = 0; - handle->txQueue->tail = 0; - handle->txQueue->used = 0; - - emRequestDeinit(handle); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Abort ongoing UART transfers. - * - * @details - * All ongoing or queued operations of the given abort type will be aborted. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] type Abort type -- whether to abort only Tx, only Rx, or both. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success, @ref ECODE_EMDRV_UARTDRV_IDLE if - * the UART is idle. On failure, an appropriate UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type) -{ - UARTDRV_Buffer_t *rxBuffer, *txBuffer; - CORE_DECLARE_IRQ_STATE; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - CORE_ENTER_ATOMIC(); - if ((type == uartdrvAbortTransmit) && (handle->txQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } else if ((type == uartdrvAbortReceive) && (handle->rxQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } else if ((type == uartdrvAbortAll) - && (handle->txQueue->used == 0) - && (handle->rxQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } - - // Stop DMA transfers. - if ((type == uartdrvAbortTransmit) || (type == uartdrvAbortAll)) { - // Stop the current transfer - DMADRV_StopTransfer(handle->txDmaCh); - handle->txDmaActive = false; - - if (handle->txQueue->used > 0) { - // Update the transfer status of the active transfer - GetTailBuffer(handle->txQueue, &txBuffer); - DMADRV_TransferRemainingCount(handle->txDmaCh, - (int*)&txBuffer->itemsRemaining); - txBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // Dequeue all transfers and call callback - while (handle->txQueue->used > 0) { - DequeueBuffer(handle->txQueue, &txBuffer); - - // Call the callback with ABORTED error code - if (txBuffer->callback != NULL) { - txBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_ABORTED, - NULL, - txBuffer->itemsRemaining); - } - } - } - - // Wait for peripheral to finish cleaning up, to prevent framing errors - // on subsequent transfers - while (!(UARTDRV_GetPeripheralStatus(handle) & UARTDRV_STATUS_TXIDLE)) { - } - } - if ((type == uartdrvAbortReceive) || (type == uartdrvAbortAll)) { - // Stop the current transfer - DMADRV_StopTransfer(handle->rxDmaCh); - handle->rxDmaActive = false; - - if (handle->rxQueue->used > 0) { - // Update the transfer status of the active transfer - GetTailBuffer(handle->rxQueue, &rxBuffer); - DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int*)&rxBuffer->itemsRemaining); - rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // Dequeue all transfers and call callback - while (handle->rxQueue->used > 0) { - DequeueBuffer(handle->rxQueue, &rxBuffer); - - // Call the callback with ABORTED error code - if (rxBuffer->callback != NULL) { - rxBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_ABORTED, - NULL, - rxBuffer->itemsRemaining); - } - } - } - - // Disable the receiver - if (handle->fcType != uartdrvFlowControlHwUart) { - DisableReceiver(handle); - } - } - - if (handle->em1RequestCount > 0) { - em1RequestRemove(handle); - } - - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Return the status of the UART peripheral associated with a given handle. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * UART status value - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle) -{ - UARTDRV_Status_t status = 0; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (handle->type == uartdrvUartTypeUart) { - status = handle->peripheral.uart->STATUS; - } else if (handle->type == uartdrvUartTypeLeuart) { - uint32_t reg = handle->peripheral.leuart->STATUS; - if (reg & LEUART_STATUS_TXENS) { - status |= UARTDRV_STATUS_TXEN; - } - if (reg & LEUART_STATUS_RXENS) { - status |= UARTDRV_STATUS_RXEN; - } - if (reg & LEUART_STATUS_RXBLOCK) { - status |= UARTDRV_STATUS_RXBLOCK; - } - if (reg & LEUART_STATUS_TXC) { - status |= UARTDRV_STATUS_TXC; - } - if (reg & LEUART_STATUS_TXBL) { - status |= UARTDRV_STATUS_TXBL; - } - if (reg & LEUART_STATUS_RXDATAV) { - status |= UARTDRV_STATUS_RXDATAV; - } -#if defined(LEUART_STATUS_TXIDLE) - if (reg & LEUART_STATUS_TXIDLE) { - status |= UARTDRV_STATUS_TXIDLE; - } -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - status = handle->peripheral.uart->STATUS; -#endif - } else if ((handle->type == uartdrvUartTypeEuart)) { - status = uartdrv_eusart_get_status(handle->peripheral.euart); - } -#else - status = handle->peripheral.uart->STATUS; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) - // Series 0 devices does not have the TXIDLE flag, so we emulate it - if ((status & UARTDRV_STATUS_TXC) || !(handle->hasTransmitted)) { - status |= UARTDRV_STATUS_TXIDLE; - } -#endif - - return status; -} - -/***************************************************************************//** - * @brief - * Return the number of queued receive operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * The number of queued operations. - ******************************************************************************/ -uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle) -{ - return (uint8_t)handle->rxQueue->used; -} - -/***************************************************************************//** - * @brief - * Check the status of the UART and gather information about any ongoing - * receive operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[out] buffer Pointer to the current data buffer. - * - * @param[out] itemsReceived Current bytes received count. - * - * @param[out] itemsRemaining Current bytes remaining count. - * - * @return - * UART status. - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *itemsReceived, - UARTDRV_Count_t *itemsRemaining) -{ - UARTDRV_Buffer_t *rxBuffer = NULL; - Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; - uint32_t remaining = 0; - - if (handle->rxQueue->used > 0) { - retVal = GetTailBuffer(handle->rxQueue, &rxBuffer); - DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int*)&remaining); - } - - if (rxBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { - *itemsReceived = rxBuffer->transferCount - remaining; - *itemsRemaining = remaining; - *buffer = rxBuffer->data; - } else { - *itemsRemaining = 0; - *itemsReceived = 0; - *buffer = NULL; - } - - return UARTDRV_GetPeripheralStatus(handle); -} - -/***************************************************************************//** - * @brief - * Returns the number of queued transmit operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * The number of queued operations. - ******************************************************************************/ -uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle) -{ - return (uint8_t)handle->txQueue->used; -} - -/***************************************************************************//** - * @brief - * Check the status of the UART and gather information about any ongoing - * transmit operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[out] buffer Pointer to the current data buffer. - * - * @param[out] itemsSent Current bytes sent count. - * - * @param[out] itemsRemaining Current bytes remaining count. - * - * @return - * UART status. - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *itemsSent, - UARTDRV_Count_t *itemsRemaining) -{ - UARTDRV_Buffer_t *txBuffer = NULL; - Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; - uint32_t remaining = 0; - - if (handle->txQueue->used > 0) { - retVal = GetTailBuffer(handle->txQueue, &txBuffer); - DMADRV_TransferRemainingCount(handle->txDmaCh, - (int*)&remaining); - } - - if (txBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { - *itemsSent = txBuffer->transferCount - remaining; - *itemsRemaining = remaining; - *buffer = txBuffer->data; - } else { - *itemsRemaining = 0; - *itemsSent = 0; - *buffer = NULL; - } - - return UARTDRV_GetPeripheralStatus(handle); -} - -/***************************************************************************//** - * @brief - * Set UART flow control state. Set nRTS pin if hardware flow control - * is enabled. Send XON/XOFF if software flow control is enabled. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] state Flow control state. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) -{ -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHwUart) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - handle->fcSelfCfg = state; - if (state != uartdrvFlowControlAuto) { - handle->fcSelfState = state; - } - return FcApplyState(handle); -#else - (void) handle; - (void) state; - return ECODE_EMDRV_UARTDRV_OK; -#endif -} - -/***************************************************************************//** - * @brief - * Set peer UART flow control state. Pause/resume transmit accordingly. - * Only for manual software flow control. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] state Flow control state. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) -{ - if ( (handle->fcType != uartdrvFlowControlSw) - || (state == uartdrvFlowControlAuto) ) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - - if (handle->fcPeerState != state) { - handle->fcPeerState = state; - if (state == uartdrvFlowControlOn) { - UARTDRV_ResumeTransmit(handle); - } else if (state == uartdrvFlowControlOff) { - UARTDRV_PauseTransmit(handle); - } - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Check the peer's flow control status. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * Returns uartdrvFlowControlOn if clear to send. - ******************************************************************************/ -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle) -{ - return handle->fcPeerState; -} - -/***************************************************************************//** - * @brief - * Check the self flow control status. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * Returns uartdrvFlowControlOn if requesting to send. - ******************************************************************************/ -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle) -{ - return handle->fcSelfState; -} - -/***************************************************************************//** - * @brief - * Enable transmission when restrained by flow control. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle) -{ - handle->IgnoreRestrain = true; - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Direct receive without interrupts or callback. This is a blocking function. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data pointer to buffer. - * - * @param[in] maxCount Maximum number of bytes to receive. - * - * @return - * Number of bytes received. - ******************************************************************************/ -UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t maxCount) -{ - Ecode_t retVal; - uint32_t rxState; - UARTDRV_Count_t i = 0; - - retVal = CheckParams(handle, data, maxCount); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return 0; - } - - // Wait for DMA receive to complete and clear - while (handle->rxQueue->used > 0) { - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - rxState = (handle->peripheral.uart->STATUS & USART_STATUS_RXENS); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - rxState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS); -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - rxState = (handle->peripheral.euart->STATUS & EUSART_STATUS_RXENS); -#endif - } else { - EFM_ASSERT(false); - rxState = 0; - } - - if (!rxState) { - EnableReceiver(handle); - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - while ((handle->peripheral.uart->STATUS & USART_STATUS_RXDATAV) != 0U) { - *data = (uint8_t)handle->peripheral.uart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - while ((handle->peripheral.leuart->STATUS & LEUART_STATUS_RXDATAV) != 0U) { - *data = (uint8_t)handle->peripheral.leuart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - while ((handle->peripheral.euart->STATUS & EUSART_STATUS_RXFL) != 0U) { - *data = (uint8_t)handle->peripheral.euart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif - } - - data -= i; - - if (!rxState) { - DisableReceiver(handle); - } - return i; -} - -/***************************************************************************//** - * @brief - * Direct transmit without interrupts or callback. This is a blocking function. - * that ignores flow control if enabled. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data Pointer to the buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - uint32_t txState; - bool callDmaIrqHandler; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - // Wait for DMA transmit to complete and clear - callDmaIrqHandler = CORE_IrqIsBlocked(UART_DMA_IRQ); // Loop invariant - while ((handle->txQueue->used > 0) && (!handle->txDmaPaused)) { - if (callDmaIrqHandler) { - UART_DMA_IRQHANDLER(); - } - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; -#endif - } else { - EFM_ASSERT(false); - txState = 0; - } - - if (!txState) { - EnableTransmitter(handle); - } - - handle->hasTransmitted = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - while (count-- != 0U) { - USART_Tx(handle->peripheral.uart, *data++); - } - // Wait for Tx completion - while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXC)) { - } -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - while (count-- != 0U) { - LEUART_Tx(handle->peripheral.leuart, *data++); - } - // Wait for Tx completion - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXC)) { - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - while (count-- != 0U) { - uartdrv_eusart_tx(handle->peripheral.euart, *data++); - } - while (~uartdrv_eusart_get_status(handle->peripheral.euart) & (EUSART_STATUS_TXC | EUSART_STATUS_TXIDLE)) { - } -#endif - } - - if (!txState) { - DisableTransmitter(handle); - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Pause an ongoing transmit operation. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - // Pause the transfer if 1) pause counter is 0 - // 2) HW flow control hasn't already paused the DMA - if ( (handle->txDmaPaused == 0) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { - DMADRV_PauseTransfer(handle->txDmaCh); - } - // Increment counter to allow nested calls - handle->txDmaPaused++; - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a non-blocking receive. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A receive data buffer. - * - * @param[in] count A number of bytes received. - * - * @param[in] callback A transfer completion callback. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback) -{ - Ecode_t retVal; - UARTDRV_Buffer_t outputBuffer; - UARTDRV_Buffer_t *queueBuffer; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - outputBuffer.data = data; - outputBuffer.transferCount = count; - outputBuffer.itemsRemaining = count; - outputBuffer.callback = callback; - outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - - retVal = EnqueueBuffer(handle->rxQueue, &outputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if (!(handle->rxDmaActive)) { - EnableReceiver(handle); - StartReceiveDma(handle, queueBuffer); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType != uartdrvFlowControlHwUart) { - handle->fcSelfState = uartdrvFlowControlOn; - FcApplyState(handle); - } -#endif - } // else: started by ReceiveDmaComplete - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a blocking receive. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A receive data buffer. - * - * @param[in] count A number of bytes received. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - UARTDRV_Buffer_t inputBuffer; - UARTDRV_Buffer_t *queueBuffer; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - inputBuffer.data = data; - inputBuffer.transferCount = count; - inputBuffer.itemsRemaining = count; - inputBuffer.callback = NULL; - inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - - retVal = EnqueueBuffer(handle->rxQueue, &inputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->rxQueue->used > 1) { - } - EnableReceiver(handle); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType != uartdrvFlowControlHwUart) { - handle->fcSelfState = uartdrvFlowControlOn; - FcApplyState(handle); - } -#endif - StartReceiveDma(handle, queueBuffer); - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->rxDmaActive) { - } - return queueBuffer->transferStatus; -} - -/***************************************************************************//** - * @brief - * Resume a paused transmit operation. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - if (handle->txDmaPaused > 0) { - // Resume the transfer if 1) pause counter is 1 - // 2) HW flow control doesn't need to pause the DMA - if ( (handle->txDmaPaused == 1) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { - DMADRV_ResumeTransfer(handle->txDmaCh); - } - handle->txDmaPaused--; - } else { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a non-blocking transmit. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A transmit data buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @param[in] callback A transfer completion callback. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback) -{ - Ecode_t retVal; - UARTDRV_Buffer_t inputBuffer; - UARTDRV_Buffer_t *queueBuffer; - uint32_t txState; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - inputBuffer.data = data; - inputBuffer.transferCount = count; - inputBuffer.itemsRemaining = count; - inputBuffer.callback = callback; - inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); - } else { - EFM_ASSERT(false); - txState = 0; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; - } else { - EFM_ASSERT(false); - txState = 0; - } -#else - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - - if (!txState) { - EnableTransmitter(handle); - } - - retVal = EnqueueBuffer(handle->txQueue, &inputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if (!(handle->txDmaActive)) { - CORE_ATOMIC_SECTION( - if (handle->txQueue->used > 0) { - StartTransmitDma(handle, queueBuffer); - handle->hasTransmitted = true; - } - ) - } // else: started by TransmitDmaComplete - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a blocking transmit. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A transmit data buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - UARTDRV_Buffer_t outputBuffer; - UARTDRV_Buffer_t *queueBuffer; - uint32_t txState; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - outputBuffer.data = data; - outputBuffer.transferCount = count; - outputBuffer.itemsRemaining = count; - outputBuffer.callback = NULL; - outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); - } else { - EFM_ASSERT(false); - txState = 0; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; - } else { - EFM_ASSERT(false); - txState = 0; - } -#else - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - - if (!txState) { - EnableTransmitter(handle); - } - - retVal = EnqueueBuffer(handle->txQueue, &outputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->txQueue->used > 1) { - } - StartTransmitDma(handle, queueBuffer); - handle->hasTransmitted = true; - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->txDmaActive) { - } - - return queueBuffer->transferStatus; -} - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void) -{ - sl_power_manager_on_isr_exit_t result = SL_POWER_MANAGER_IGNORE; - uint32_t handleIdx; - UARTDRV_Handle_t handle; - - if (uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - handle = uartdrvHandle[handleIdx]; - if (handle != NULL) { - if ((sl_power_manager_on_isr_exit_t)handle->sleep == SL_POWER_MANAGER_SLEEP) { - handle->sleep = SL_POWER_MANAGER_IGNORE; - result = SL_POWER_MANAGER_SLEEP; - } - } - } - } - - return result; -} -#endif - -/******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** - * @addtogroup uartdrv UARTDRV - UART Driver - * @brief Universal Asynchronous Receiver/Transmitter Driver - * @{ - - @details - The source files for the UART driver library, uartdrv.c and uartdrv.h, are in the - emdrv/uartdrv folder. - - @n @section uartdrv_intro Introduction - The UART driver supports the UART capabilities of the USART, UART, and LEUART - peripherals. The driver is fully reentrant and supports multiple driver instances. - The driver does not buffer or queue data. However, it queues UART transmit - and receive operations. Both blocking and non-blocking transfer functions are - available. Non-blocking transfer functions report transfer completion with - callback functions. Transfers are done using DMA. Simple direct/forced - transmit and receive functions are also available. Note that these functions - are blocking and not suitable for low energy applications because they use CPU - polling. - - UART hardware flow control (CTS/RTS) is fully supported by the driver. UART - software flow control (XON/XOFF) is partially supported by the driver. For - more information about flow control support, see @ref uartdrv_fc. - - @note Transfer completion callback functions are called from within the DMA - interrupt handler with interrupts disabled. - - @n @section uartdrv_conf Configuration Options - - Some properties of the UARTDRV driver are compile-time configurable. These - properties are set in a uartdrv_config.h file. A template for this - file, containing default values, is in the emdrv/config folder. - To configure UARTDRV for your application, provide a custom configuration file, - or override the defines on the compiler command line. - These are the available configuration parameters with default values defined. - @code - - // Set to 1 to enable hardware flow control. - #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 - - // Maximum number of driver instances. - #define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 - - // UART software flow control code: request peer to start Tx. - #define UARTDRV_FC_SW_XON 0x11 - - // UART software flow control code: request peer to stop Tx. - #define UARTDRV_FC_SW_XOFF 0x13 - @endcode - - The properties of each UART driver instance are set at run-time via the - @ref UARTDRV_InitUart_t data structure input parameter to the @ref UARTDRV_InitUart() - function for UART and USART peripherals, and the @ref UARTDRV_InitLeuart_t - data structure input parameter to the @ref UARTDRV_InitLeuart() function for - LEUART peripherals. - - @n @section uartdrv_api The API - - This section contains brief descriptions of the functions in the API. For more - information on input and output parameters and return values, - click on the hyperlinked function names. Most functions return an error - code, @ref ECODE_EMDRV_UARTDRV_OK is returned on success, - see ecode.h and uartdrv.h for other error codes. - - The application code must include @em uartdrv.h header file. - - @ref UARTDRV_InitUart(), @ref UARTDRV_InitLeuart() and @ref UARTDRV_DeInit() @n - These functions initialize and deinitialize the UARTDRV driver. Typically, - UARTDRV_InitUart() (for UART/USART) or - UARTDRV_InitLeuart() (for LEUART) are called once in - the startup code. - - @ref UARTDRV_GetReceiveStatus() and @ref UARTDRV_GetTransmitStatus() @n - Query the status of a current transmit or receive operations. Reports number - of items (frames) transmitted and remaining. - - @ref UARTDRV_GetReceiveDepth() and @ref UARTDRV_GetTransmitDepth() @n - Get the number of queued receive or transmit operations. - - @ref UARTDRV_Transmit(), UARTDRV_Receive() @n - UARTDRV_TransmitB(), UARTDRV_ReceiveB() @n - UARTDRV_ForceTransmit() and UARTDRV_ForceReceive() @n - Blocking and non-blocking transfer functions are included. - The blocking versions have an uppercase B (for Blocking) at the end of - their function name. Blocking functions do not return before the transfer - is complete. The non-blocking functions signal a transfer completion with a - callback function. @ref UARTDRV_ForceTransmit() and - @ref UARTDRV_ForceReceive() are also blocking. These two functions access - the UART peripheral directly without using DMA or interrupts. - @ref UARTDRV_ForceTransmit() does not respect flow control. - @ref UARTDRV_ForceReceive() forces RTS low. - - @ref UARTDRV_Abort() @n - Abort current transmit or receive operations and remove all queued - operations. - - @ref UARTDRV_FlowControlSet(), @ref UARTDRV_FlowControlGetSelfStatus(), @ref UARTDRV_FlowControlSetPeerStatus() and @ref UARTDRV_FlowControlGetPeerStatus() @n - Set and get flow control status of self or peer device. Note that the return - value from these two functions depends on the flow control mode set by - @ref UARTDRV_FlowControlSet(), @ref UARTDRV_InitUart(), or - @ref UARTDRV_InitLeuart(). - - @ref UARTDRV_FlowControlIgnoreRestrain() @n - Enables transmission when restrained by flow control. - - @ref UARTDRV_PauseTransmit() and @ref UARTDRV_ResumeTransmit() @n - Pause a currently active transmit operation by preventing the DMA from loading - the UART FIFO. Will not override HW flow control state (if applicable), but - can be used in conjunction. - - @n @section uartdrv_fc Flow Control Support - - If UART flow control is not required, make sure that - EMDRV_UARTDRV_FLOW_CONTROL_ENABLE is set to 0. This reduces the code size - and complexity of the driver. - - Both hardware and software flow control are supported. To - enable either of these, set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1 in - uartdrv_config.h. - - @n @subsection uartdrv_fc_hw Hardware Flow Control - - UART hardware flow control uses two additional pins for flow control - handshaking, the clear-to-send (CTS) and ready-to-send (RTS) pins. - RTS is an output and CTS is an input. These are active-low signals. - When CTS is high, the UART transmitter should stop sending frames. - A receiver should set RTS high when it is no longer capable of - receiving data. - - @par Peripheral Hardware Flow Control - - Newer devices natively support CTS/RTS in - the USART peripheral hardware. To enable hardware flow control, perform the - following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - In the @ref UARTDRV_InitUart_t struct passed to @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHwUart. - - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort - and rtsPin in the init struct. - - Also define the CTS and RTS locations by setting portLocationCts and - portLocationRts in the init struct. - - @par GPIO Hardware Flow Control - - To support hardware flow control on devices that don't have UART CTS/RTS - hardware support, the driver includes the GPIOINT driver to emulate a - hardware implementation of UART CTS/RTS flow control on these devices. - - To enable hardware flow control, perform the following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - UART/USART: In the @ref UARTDRV_InitUart_t struct passed to - @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHw. - - LEUART: In the @ref UARTDRV_InitLeuart_t struct passed to - @ref UARTDRV_InitLeuart(), set - @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlHw. - - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort and - rtsPin in the same init struct. - - @note Because of the limitations in GPIO interrupt hardware, you cannot select - CTS pins in multiple driver instances with the same pin number. For example, pin A0 and - B0 cannot serve as CTS pins in two concurrent driver instances. - - RTS is set high whenever there are no Rx operations queued. The UART - transmitter is halted when the CTS pin goes high. The transmitter completes - the current frame before halting. DMA transfers are also halted. - - @n @subsection uartdrv_fc_sw Software Flow Control - - UART software flow control uses in-band signaling, meaning the receiver sends - special flow control characters to the transmitter and thereby removes - the need for dedicated wires for flow control. The two symbols - UARTDRV_FC_SW_XON and UARTDRV_FC_SW_XOFF are defined in uartdrv_config.h. - - To enable support for software flow control, perform the following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - UART/USART: In the @ref UARTDRV_InitUart_t structure passed to - @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlSw. - - LEUART: In the @ref UARTDRV_InitLeuart_t structure passed to - @ref UARTDRV_InitLeuart(), set - @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlSw. - - @note Software flow control is partial only. - - The application must monitor buffers and make decisions on when to send XON/ - XOFF. XON/XOFF can be sent to the peer using @ref UARTDRV_FlowControlSet(). - Though @ref UARTDRV_FlowControlSet() will pause the active transmit operation - to send a flow control character, there is no way to guarantee the order. - If the application implements a specific packet format where the flow control - codes may appear only in fixed positions, the application should not - use @ref UARTDRV_FlowControlSet() but implement read and write of XON/XOFF - into packet buffers. If the application code fully implements all the flow - control logic, EMDRV_UARTDRV_FLOW_CONTROL_ENABLE should be set to 0 - to reduce code space. - - @n @section uartdrv_example Example - @if DOXYDOC_P1_DEVICE - @if DOXYDOC_EFM32G - @include uartdrv_example_p1_nomvdis.c - @endif - @if DOXYDOC_EZR32HG - @include uartdrv_example_p1_usart0.c - @endif - @ifnot (DOXYDOC_EFM32G || DOXYDOC_EZR32HG) - @include uartdrv_example_p1.c - @endif - @endif - @if DOXYDOC_P2_DEVICE - @include uartdrv_example_p2.c - @endif - @if DOXYDOC_S2_DEVICE - @include uartdrv_example_s2.c - @endif - - * @} end group uartdrv *********************************************************/ +/***************************************************************************//** + * @file + * @brief UARTDRV API implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#define CURRENT_MODULE_NAME "UARTDRV" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "uartdrv.h" +#include "em_device.h" +#include "em_core.h" +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +#include "gpiointerrupt.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#include "sl_sleeptimer.h" +#endif + +#include + +//**************************************************************************** + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(_USART_ROUTEPEN_CTSPEN_MASK) +#define UART_HW_FLOW_CONTROL_SUPPORT +#elif (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(USART_CTRLX_CTSEN) +#define UART_HW_FLOW_CONTROL_SUPPORT +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +#define HANDLES_ARE_AVAILABLE 1 +#elif defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +#define HANDLES_ARE_AVAILABLE 1 +#else +#define HANDLES_ARE_AVAILABLE 0 +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define UART_DMA_IRQ DMA_IRQn +#define UART_DMA_IRQHANDLER() DMA_IRQHandler() +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES <= 2) +#define UART_DMA_IRQ LDMA_IRQn +#define UART_DMA_IRQHANDLER() LDMA_IRQHandler() +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES > 2) +#define UART_DMA_IRQ LDMA_CHNL0_IRQn +#define UART_DMA_IRQHANDLER() LDMA_CHNL0_IRQHandler() +#else +#error "No valid UARTDRV DMA engine defined." +#endif + +// UARTDRV use low-level drivers from platform/peripheral. +#if defined(UARTDRV_USE_PERIPHERAL) + +#define uartdrv_gpio_port_t sl_gpio_port_t +#define UARTDRV_GPIO_MODE_DISABLED SL_GPIO_MODE_DISABLED +#define UARTDRV_GPIO_MODE_INPUT SL_GPIO_MODE_INPUT +#define UARTDRV_GPIO_MODE_INPUT_PULL SL_GPIO_MODE_INPUT_PULL +#define UARTDRV_GPIO_MODE_PUSH_PULL SL_GPIO_MODE_PUSH_PULL + +#define uartdrv_gpio_get_pin_input(port, pin) sl_gpio_get_pin_input(port, pin) +#define uartdrv_gpio_set_pin_output(port, pin) sl_gpio_set_pin_output(port, pin) +#define uartdrv_gpio_clear_pin_output(port, pin) sl_gpio_clear_pin_output(port, pin) +#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) sl_gpio_set_pin_mode(port, pin, mode, output) +#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ + sl_gpio_configure_external_interrupt(port, \ + pin, \ + intNo, \ + (risingEdge * SL_GPIO_INTERRUPT_RISING_EDGE \ + & fallingEdge * SL_GPIO_INTERRUPT_FALLING_EDGE \ + & enable * SL_GPIO_INTERRUPT_ENABLE)) + +#define uartdrv_eusart_data_bits_t sl_hal_eusart_data_bits_t +#define uartdrv_eusart_stop_bits_t sl_hal_eusart_stop_bits_t +#define uartdrv_eusart_parity_t sl_hal_eusart_parity_t +#define uartdrv_eusart_ovs_t sl_hal_eusart_ovs_t +#define uartdrv_eusart_majority_vote_t sl_hal_eusart_majority_vote_t + +#define UARTDRV_EUSART_DISABLE 0x0 +#define UARTDRV_EUSART_ENABLE_RX (EUSART_CMD_RXEN | EUSART_CMD_TXDIS) +#define UARTDRV_EUSART_ENABLE_TX (EUSART_CMD_TXEN | EUSART_CMD_RXDIS) +#define UARTDRV_EUSART_ENABLE (EUSART_CMD_RXEN | EUSART_CMD_TXEN) + +#define uartdrv_eusart_get_status(eusart) sl_hal_eusart_get_status(eusart) +#define uartdrv_eusart_tx(eusart, data) sl_hal_eusart_tx(eusart, data) +#define uartdrv_eusart_reset(eusart) sl_hal_eusart_reset(eusart) +#define uartdrv_eusart_enable(eusart, enable) do { if (enable == UARTDRV_EUSART_DISABLE) \ + { sl_hal_eusart_disable(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE_RX) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_disable_tx(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE_TX) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_tx(eusart); sl_hal_eusart_disable_rx(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_enable_tx(eusart); } } while (0) + +// UARTDRV use low-level drivers from platform/emlib. +#else +#define uartdrv_gpio_port_t GPIO_Port_TypeDef + +#define UARTDRV_GPIO_MODE_DISABLED gpioModeDisabled +#define UARTDRV_GPIO_MODE_INPUT gpioModeInput +#define UARTDRV_GPIO_MODE_INPUT_PULL gpioModeInputPull +#define UARTDRV_GPIO_MODE_PUSH_PULL gpioModePushPull + +#define uartdrv_gpio_get_pin_input(port, pin) GPIO_PinInGet(port, pin) +#define uartdrv_gpio_set_pin_output(port, pin) GPIO_PinOutSet(port, pin) +#define uartdrv_gpio_clear_pin_output(port, pin) GPIO_PinOutClear(port, pin) +#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) GPIO_PinModeSet(port, pin, mode, output) +#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ + GPIO_ExtIntConfig(port, pin, intNo, risingEdge, fallingEdge, enable) + +#define uartdrv_eusart_data_bits_t EUSART_Databits_TypeDef +#define uartdrv_eusart_stop_bits_t EUSART_Stopbits_TypeDef +#define uartdrv_eusart_parity_t EUSART_Parity_TypeDef +#define uartdrv_eusart_ovs_t EUSART_OVS_TypeDef +#define uartdrv_eusart_majority_vote_t EUSART_MajorityVote_TypeDef + +#define UARTDRV_EUSART_DISABLE eusartDisable +#define UARTDRV_EUSART_ENABLE_RX eusartEnableRx +#define UARTDRV_EUSART_ENABLE_TX eusartEnableTx +#define UARTDRV_EUSART_ENABLE eusartEnable + +#define uartdrv_eusart_get_status(eusart) EUSART_StatusGet(eusart) +#define uartdrv_eusart_tx(eusart, data) EUSART_Tx(eusart, data) +#define uartdrv_eusart_reset(eusart) EUSART_Reset(eusart) +#define uartdrv_eusart_enable(eusart, enable) EUSART_Enable(eusart, enable) +#endif + +//**************************************************************************** + +#if (HANDLES_ARE_AVAILABLE) +static bool uartdrvHandleIsInitialized = false; +static UARTDRV_Handle_t uartdrvHandle[EMDRV_UARTDRV_MAX_DRIVER_INSTANCES]; +#endif +static bool enableRxWhenSleeping = UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION; + +//**************************************************************************** + +static bool ReceiveDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam); +static bool TransmitDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam); + +/***************************************************************************//** + * @brief Power management functions for the uartdrv. + ******************************************************************************/ +static void em1RequestAdd(UARTDRV_Handle_t handle) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (handle->em1RequestCount == 0) { + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + } + handle->em1RequestCount++; + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount++; +#endif +} + +static void em1RequestRemove(UARTDRV_Handle_t handle) +{ + EFM_ASSERT(handle->em1RequestCount > 0); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + handle->em1RequestCount--; + if (handle->em1RequestCount == 0) { + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + } + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount--; +#endif +} + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +static void emRequestInit(UARTDRV_Handle_t handle) +{ + handle->em1RequestCount = 0; +} +#endif + +static void emRequestDeinit(UARTDRV_Handle_t handle) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + sl_status_t status; + bool running; + + CORE_ENTER_ATOMIC(); + status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); + if ((status == SL_STATUS_OK) && (running)) { + sl_sleeptimer_stop_timer(&handle->delayedTxTimer); + } + CORE_EXIT_ATOMIC(); +#endif + if (handle->em1RequestCount > 0) { + handle->em1RequestCount = 1; + em1RequestRemove(handle); + } +} + +/***************************************************************************//** + * @brief Get UARTDRV_Handle_t from GPIO pin number (HW FC CTS pin interrupt). + ******************************************************************************/ +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +static UARTDRV_Handle_t HwFcCtsIrqGetDrvHandle(uint32_t gpioPinNo) +{ + uint32_t i; + + for (i = 0; i < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; i++) { + if (uartdrvHandle[i]->ctsPin == gpioPinNo) { + return uartdrvHandle[i]; + } + } + return NULL; +} + +/***************************************************************************//** + * @brief Get CTS pin state. + ******************************************************************************/ +static UARTDRV_FlowControlState_t HwFcGetClearToSendPin(UARTDRV_Handle_t handle) +{ + if (handle->fcType == uartdrvFlowControlHw) { + return (UARTDRV_FlowControlState_t)uartdrv_gpio_get_pin_input(handle->ctsPort, handle->ctsPin); + } else { + return uartdrvFlowControlOn; + } +} + +/***************************************************************************//** + * @brief Manage CTS pin change. + ******************************************************************************/ +static void HwFcManageClearToSend(uint8_t gpioPinNo) +{ + UARTDRV_Handle_t handle = HwFcCtsIrqGetDrvHandle(gpioPinNo); + + if (handle && handle->fcType == uartdrvFlowControlHw) { + // If not auto mode, assign the CTS pin state to the self state + // If auto mode, also control UART Tx enable + handle->fcSelfState = HwFcGetClearToSendPin(handle); + // Only manage DMA if not already paused by SW + if (handle->fcSelfCfg == uartdrvFlowControlAuto && (handle->txDmaPaused == 0)) { + bool active = false; + Ecode_t status = DMADRV_TransferActive(handle->txDmaCh, &active); + if ((handle->fcSelfState == uartdrvFlowControlOn) || handle->IgnoreRestrain) { + handle->IgnoreRestrain = false; + DMADRV_ResumeTransfer(handle->txDmaCh); + } + // Only pause DMA if currently active + else if ((status == ECODE_EMDRV_DMADRV_OK) && active) { + DMADRV_PauseTransfer(handle->txDmaCh); + } + } + } +} + +static Ecode_t FcApplyState(UARTDRV_Handle_t handle) +{ + uint8_t fcSwCode; + + if (handle->fcType == uartdrvFlowControlHw) { + if (handle->fcSelfCfg == uartdrvFlowControlOn) { + // Assert nRTS (application control) + uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); + } else if (handle->fcSelfCfg == uartdrvFlowControlOff) { + // Deassert nRTS (application control) + uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); + } else { // Auto mode + if (handle->fcSelfState == uartdrvFlowControlOn) { + // Assert nRTS + uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); + } else { // Off + // Deassert nRTS + uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); + } + } + } else if (handle->fcType == uartdrvFlowControlSw) { + if (handle->fcSelfState == uartdrvFlowControlOn) { + fcSwCode = UARTDRV_FC_SW_XON; + // Pause transmit to ensure XON transmits immediately + UARTDRV_PauseTransmit(handle); + UARTDRV_ForceTransmit(handle, &fcSwCode, 1); + UARTDRV_ResumeTransmit(handle); + } else { + fcSwCode = UARTDRV_FC_SW_XOFF; + // Pause transmit to ensure XOFF transmits immediately + UARTDRV_PauseTransmit(handle); + UARTDRV_ForceTransmit(handle, &fcSwCode, 1); + UARTDRV_ResumeTransmit(handle); + } + } + return ECODE_EMDRV_UARTDRV_OK; +} +#else +// CTS pin should always read as uartdrvFlowControlOn when HW FC is disabled +#define HwFcGetClearToSendPin(x) uartdrvFlowControlOn +#endif /* EMDRV_UARTDRV_FLOW_CONTROL_ENABLE */ + +/***************************************************************************//** + * @brief Enqueue UART transfer buffer. + ******************************************************************************/ +static Ecode_t EnqueueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t *inputBuffer, + UARTDRV_Buffer_t **queueBuffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used >= queue->size) { + *queueBuffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_FULL; + } + memcpy((void *)&queue->fifo[queue->head], + (const void *)inputBuffer, + sizeof(UARTDRV_Buffer_t)); + *queueBuffer = &queue->fifo[queue->head]; + queue->head = (queue->head + 1) % queue->size; + queue->used++; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Dequeue UART transfer buffer. + ******************************************************************************/ +static Ecode_t DequeueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + queue->tail = (queue->tail + 1) % queue->size; + queue->used--; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Get tail UART transfer buffer. + ******************************************************************************/ +static Ecode_t GetTailBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Enable UART transmitter. + ******************************************************************************/ +static void EnableTransmitter(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif // LEUART || EUART || EUSART + { + // Enable Tx + handle->peripheral.uart->CMD = USART_CMD_TXEN; + // Wait for Tx to be enabled + while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXENS)) { + } + + // Enable Tx route +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_TXPEN; +#elif defined(USART_ROUTE_TXPEN) + handle->peripheral.uart->ROUTE |= USART_ROUTE_TXPEN; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; +#endif + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Enable Tx + handle->peripheral.leuart->CMD = LEUART_CMD_TXEN; + // Wait for Tx to be enabled + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS)) { + } + + // Enable Tx route +#if defined(LEUART_ROUTEPEN_TXPEN) + handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN; +#else + handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_TXPEN; +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); + } +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; +#endif + } +#endif +} + +/***************************************************************************//** + * @brief Disable UART transmitter. + ******************************************************************************/ +static void DisableTransmitter(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Disable Tx route +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_TXPEN; +#elif defined(USART_ROUTE_TXPEN) + handle->peripheral.uart->ROUTE &= ~USART_ROUTE_TXPEN; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; +#endif + // Disable Tx + handle->peripheral.uart->CMD = USART_CMD_TXDIS; + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Disable Tx route +#if defined(LEUART_ROUTEPEN_TXPEN) + handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_TXPEN; +#else + handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_TXPEN; +#endif + // Disable Tx + handle->peripheral.leuart->CMD = LEUART_CMD_TXDIS; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); + } +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; +#endif + } +#endif +} + +/***************************************************************************//** + * @brief Enable UART receiver. + ******************************************************************************/ +static void EnableReceiver(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Enable Rx + handle->peripheral.uart->CMD = USART_CMD_RXEN; + // Wait for Rx to be enabled + while (!(handle->peripheral.uart->STATUS & USART_STATUS_RXENS)) { + } + + // Enable Rx route +#if defined(USART_ROUTEPEN_RXPEN) + handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_RXPEN) + handle->peripheral.uart->ROUTE |= USART_ROUTE_RXPEN; +#elif defined(GPIO_USART_ROUTEEN_RXPEN) + GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; +#endif + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Enable Rx + handle->peripheral.leuart->CMD = LEUART_CMD_RXEN; + // Wait for Rx to be enabled + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS)) { + } + + // Enable Rx route +#if defined(LEUART_ROUTEPEN_RXPEN) + handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN; +#else + handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_RXPEN; +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); + } + } +#endif +} + +/***************************************************************************//** + * @brief Disable UART receiver. + ******************************************************************************/ +static void DisableReceiver(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Disable Rx route +#if defined(USART_ROUTEPEN_RXPEN) + handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_RXPEN) + handle->peripheral.uart->ROUTE &= ~USART_ROUTE_RXPEN; +#elif defined(GPIO_USART_ROUTEEN_RXPEN) + GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; +#endif + // Disable Rx + handle->peripheral.uart->CMD = USART_CMD_RXDIS; + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for prevous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Disable Rx route +#if defined(LEUART_ROUTEPEN_RXPEN) + handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_RXPEN; +#else + handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_RXPEN; +#endif + // Disable Rx + handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); + } + } +#endif +} + +/***************************************************************************//** + * @brief Start a UART DMA receive operation. + ******************************************************************************/ +static void StartReceiveDma(UARTDRV_Handle_t handle, + UARTDRV_Buffer_t *buffer) +{ + void *rxPort = NULL; + + handle->rxDmaActive = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + rxPort = (void *)&(handle->peripheral.uart->RXDATA); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + rxPort = (void *)&(handle->peripheral.leuart->RXDATA); +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + rxPort = (void *)&(handle->peripheral.euart->RXDATA); +#endif + } else { + handle->rxDmaActive = false; + return; + } + + if (enableRxWhenSleeping) { + em1RequestAdd(handle); + } + DMADRV_PeripheralMemory(handle->rxDmaCh, + handle->rxDmaSignal, + buffer->data, + rxPort, + true, + buffer->transferCount, + dmadrvDataSize1, + ReceiveDmaComplete, + handle); +} + +/***************************************************************************//** + * @brief Start a UART DMA transmit operation. + ******************************************************************************/ +static void StartTransmitDma(UARTDRV_Handle_t handle, + UARTDRV_Buffer_t *buffer) +{ + void *txPort = NULL; + + handle->txDmaActive = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txPort = (void *)&(handle->peripheral.uart->TXDATA); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + // Set TX DMA wakeup request. Needed for transmit while in EM2. + handle->peripheral.leuart->CTRL |= LEUART_CTRL_TXDMAWU; + txPort = (void *)&(handle->peripheral.leuart->TXDATA); +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + txPort = (void *)&(handle->peripheral.euart->TXDATA); +#endif + } else { + handle->txDmaActive = false; + return; + } + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + sl_status_t status; + bool running; + + CORE_ENTER_ATOMIC(); + status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); + if ((status == 0) && (running)) { + sl_sleeptimer_stop_timer(&handle->delayedTxTimer); + em1RequestRemove(handle); + } + CORE_EXIT_ATOMIC(); +#if !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif +#endif + + em1RequestAdd(handle); + DMADRV_MemoryPeripheral(handle->txDmaCh, + handle->txDmaSignal, + txPort, + buffer->data, + true, + buffer->transferCount, + dmadrvDataSize1, + TransmitDmaComplete, + handle); +} + +/***************************************************************************//** + * @brief DMA transfer completion callback. Called by the DMA interrupt handler. + ******************************************************************************/ +static bool ReceiveDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam) +{ + CORE_DECLARE_IRQ_STATE; + UARTDRV_Handle_t handle; + UARTDRV_Buffer_t *buffer; + Ecode_t status; + (void)channel; + (void)sequenceNo; + handle = (UARTDRV_Handle_t)userParam; + status = GetTailBuffer(handle->rxQueue, &buffer); + + if (enableRxWhenSleeping) { + em1RequestRemove(handle); + } + + // If an abort was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return true; + } + + EFM_ASSERT(buffer != NULL); + +#if defined(USART_IF_FERR) + if (handle->type == uartdrvUartTypeUart + && (handle->peripheral.uart->IF & USART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; +#if defined(USART_HAS_SET_CLEAR) + handle->peripheral.uart->IF_CLR = USART_IF_FERR; +#else + handle->peripheral.uart->IFC = USART_IFC_FERR; +#endif + } else +#endif +#if defined(USART_IF_PERR) + if (handle->type == uartdrvUartTypeUart + && (handle->peripheral.uart->IF & USART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; +#if defined(USART_HAS_SET_CLEAR) + handle->peripheral.uart->IF_CLR = USART_IF_PERR; +#else + handle->peripheral.uart->IFC = USART_IFC_PERR; +#endif + } else +#endif +#if defined(LEUART_IF_FERR) + if (handle->type == uartdrvUartTypeLeuart + && (handle->peripheral.leuart->IF & LEUART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.leuart->IFC = LEUART_IFC_FERR; + } else +#endif +#if defined(LEUART_IF_PERR) + if (handle->type == uartdrvUartTypeLeuart + && (handle->peripheral.leuart->IF & LEUART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.leuart->IFC = LEUART_IFC_PERR; + } else +#endif +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) + if (handle->type == uartdrvUartTypeEuart + && (handle->peripheral.euart->IF & EUSART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.euart->IF_CLR = EUSART_IF_FERR; + } else if (handle->type == uartdrvUartTypeEuart + && (handle->peripheral.euart->IF & EUSART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.euart->IF_CLR = EUSART_IF_PERR; + } else +#endif + { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; + buffer->itemsRemaining = 0; + } + + CORE_ENTER_ATOMIC(); + + if (buffer->callback != NULL) { + buffer->callback(handle, buffer->transferStatus, buffer->data, buffer->transferCount - buffer->itemsRemaining); + } + // Dequeue the current tail Rx operation, check if more in queue + DequeueBuffer(handle->rxQueue, &buffer); + + if (handle->rxQueue->used > 0) { + GetTailBuffer(handle->rxQueue, &buffer); + StartReceiveDma(handle, buffer); + } else { +#if EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcSelfState = uartdrvFlowControlOff; + FcApplyState(handle); +#endif + handle->rxDmaActive = false; + + if (handle->fcType != uartdrvFlowControlHwUart) { + DisableReceiver(handle); + } + } + CORE_EXIT_ATOMIC(); + return true; +} + +/***************************************************************************//** + * @brief Calculate the number of sleeptimer ticks to flush the uart tx buffers. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +static uint32_t calculateSleeptimerTicksToFlushTxBuffers(UARTDRV_Handle_t handle) +{ + uint32_t baud = 0; + uint32_t ticks = 0; + + switch (handle->type) { +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + case uartdrvUartTypeLeuart: + baud = LEUART_BaudrateGet(handle->peripheral.leuart); + break; +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + case uartdrvUartTypeEuart: + baud = EUSART_BaudrateGet(handle->peripheral.euart); + break; +#endif +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + case uartdrvUartTypeUart: + default: + baud = USART_BaudrateGet(handle->peripheral.uart); + break; +#endif + } + + if (baud != 0) { // Avoid division by 0 + // Calculate the number of sleeptimer ticks for: + // 3 bytes: two in FIFO and one in shift register. + // 12 bits pr byte: one start bit, 8 data bits, parity and 2 stop bits. + ticks = (sl_sleeptimer_get_timer_frequency() * 3 * 12) / baud; + // Round up. + ticks++; + } + + return ticks; +} +#endif + +/***************************************************************************//** + * @brief Delayed transmit complete timer callback. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +static void TransmitDmaCompleteDelayed(sl_sleeptimer_timer_handle_t *timer_handle, void *userParam) +{ + (void)timer_handle; + UARTDRV_Handle_t uartdrv_handle = (UARTDRV_Handle_t)userParam; + uint32_t reg; + bool txComplete = false; + + // Check if transmit is completed by checking the uart registers. + switch (uartdrv_handle->type) { +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + case uartdrvUartTypeLeuart: + reg = uartdrv_handle->peripheral.leuart->STATUS; + txComplete = reg & LEUART_STATUS_TXC; + break; +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + case uartdrvUartTypeEuart: + reg = uartdrv_handle->peripheral.euart->STATUS; + txComplete = reg & EUSART_STATUS_TXC; + break; +#endif +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + case uartdrvUartTypeUart: + default: + reg = uartdrv_handle->peripheral.uart->STATUS; + txComplete = reg & USART_STATUS_TXC; + break; +#endif + } + + if (txComplete) { + // Remove the power manager request if completed. + em1RequestRemove(uartdrv_handle); +#if !defined(SL_CATALOG_KERNEL_PRESENT) + uartdrv_handle->sleep = SL_POWER_MANAGER_SLEEP; +#endif + } else { + // Restart the timer if not completed. + // May be the case if flow control is used. + uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(uartdrv_handle); + sl_sleeptimer_start_timer(&uartdrv_handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); + } +} +#endif + +/***************************************************************************//** + * @brief DMA transfer completion callback. Called by the DMA interrupt handler. + ******************************************************************************/ +static bool TransmitDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam) +{ + CORE_DECLARE_IRQ_STATE; + UARTDRV_Handle_t handle; + UARTDRV_Buffer_t *buffer; + Ecode_t status; + (void)channel; + (void)sequenceNo; + + handle = (UARTDRV_Handle_t)userParam; + status = GetTailBuffer(handle->txQueue, &buffer); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(handle); + sl_sleeptimer_start_timer(&handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); +#else + em1RequestRemove(handle); +#endif + + // If an abort was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return true; + } + + EFM_ASSERT(buffer != NULL); + + buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; + buffer->itemsRemaining = 0; + + CORE_ENTER_ATOMIC(); + + if (buffer->callback != NULL) { + buffer->callback(handle, ECODE_EMDRV_UARTDRV_OK, buffer->data, buffer->transferCount); + } + // Dequeue the current tail Tx operation, check if more in queue + DequeueBuffer(handle->txQueue, &buffer); + + if (handle->txQueue->used > 0) { + GetTailBuffer(handle->txQueue, &buffer); + StartTransmitDma(handle, buffer); + } else { + handle->txDmaActive = false; +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + if (handle->type == uartdrvUartTypeLeuart) { + // Clear TX DMA Wakeup request + handle->peripheral.leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; + } +#endif + } + CORE_EXIT_ATOMIC(); + return true; +} + +/***************************************************************************//** + * @brief Parameter checking function for blocking transfer API functions. + ******************************************************************************/ +static Ecode_t CheckParams(UARTDRV_Handle_t handle, void *data, uint32_t count) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if ((data == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + return ECODE_EMDRV_UARTDRV_OK; +} + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/***************************************************************************//** + * @brief Store U(S)ART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t * initData) +{ +#if defined(_USART_ROUTELOC0_MASK) + if (false) { +#if defined(USARTRF0) + } else if (handle->peripheral.uart == USARTRF0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocationRx); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.uart == USARTRF1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART0) + } else if (handle->peripheral.uart == USART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART1) + } else if (handle->peripheral.uart == USART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART1_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART2) + } else if (handle->peripheral.uart == USART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART2_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART2_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART3) + } else if (handle->peripheral.uart == USART3) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART3_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART3_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART3_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART3_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART4) + } else if (handle->peripheral.uart == USART4) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART4_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART4_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART4_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART4_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART5) + } else if (handle->peripheral.uart == USART5) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART5_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART5_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART5_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART5_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART0) + } else if (handle->peripheral.uart == UART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART1) + } else if (handle->peripheral.uart == UART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART1_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART2) + } else if (handle->peripheral.uart == UART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART2_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART2_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART2_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART2_RX_PIN(initData->portLocationRx); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_USART_ROUTE_MASK) + if (false) { +#if defined(USARTRF0) + } else if (handle->peripheral.uart == USARTRF0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocation); + handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocation); + handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocation); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.uart == USARTRF1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocation); + handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocation); + handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocation); +#endif +#if defined(USART0) + } else if (handle->peripheral.uart == USART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocation); + handle->txPin = AF_USART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART0_RX_PIN(initData->portLocation); +#endif +#if defined(USART1) + } else if (handle->peripheral.uart == USART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocation); + handle->txPin = AF_USART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART1_RX_PIN(initData->portLocation); +#endif +#if defined(USART2) + } else if (handle->peripheral.uart == USART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocation); + handle->txPin = AF_USART2_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART2_RX_PIN(initData->portLocation); +#endif +#if defined(UART0) + } else if (handle->peripheral.uart == UART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocation); + handle->txPin = AF_UART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_UART0_RX_PIN(initData->portLocation); +#endif +#if defined(UART1) + } else if (handle->peripheral.uart == UART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocation); + handle->txPin = AF_UART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_UART1_RX_PIN(initData->portLocation); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_GPIO_USART_ROUTEEN_MASK) + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; +#endif + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif // UART || USART + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief Store LEUART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t * initData) +{ +#if defined(_LEUART_ROUTELOC0_MASK) + if (false) { +#if defined(LEUART0) + } else if (handle->peripheral.leuart == LEUART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_LEUART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(LEUART1) + } else if (handle->peripheral.leuart == LEUART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_LEUART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocationRx); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_USART_ROUTE_MASK) + if (false) { +#if defined(LEUART0) + } else if (handle->peripheral.leuart == LEUART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocation); + handle->txPin = AF_LEUART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocation); +#endif +#if defined(LEUART1) + } else if (handle->peripheral.leuart == LEUART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocation); + handle->txPin = AF_LEUART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocation); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_GPIO_USART_ROUTEEN_MASK) + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; +#endif + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +/***************************************************************************//** + * @brief Store EUART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t * initData) +{ + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief Configure/deconfigure U(S)ART GPIO pins. + ******************************************************************************/ +static Ecode_t ConfigGpio(UARTDRV_Handle_t handle, bool enable) +{ + if (enable) { + uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_PUSH_PULL, 1); + uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_INPUT_PULL, 1); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); + uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, true); + } else if (handle->fcType == uartdrvFlowControlHwUart) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); + } +#endif + } else { + uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_DISABLED, 0); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, false); + } else if (handle->fcType == uartdrvFlowControlHwUart) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + } +#endif + } + return ECODE_EMDRV_UARTDRV_OK; +} + +#if (HANDLES_ARE_AVAILABLE) +/***************************************************************************//** + * @brief Add handle to handle array. + ******************************************************************************/ +static Ecode_t addHandle(UARTDRV_Handle_t handle) +{ + bool handleIsSet; + uint32_t handleIdx; + + // Set handler pointer in handler array + if (!uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + uartdrvHandle[handleIdx] = NULL; + } + uartdrvHandleIsInitialized = true; + } + + // Check if its already in the array + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == handle) { + return ECODE_EMDRV_UARTDRV_OK; + } + } + + // Insert handle + handleIsSet = false; + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == NULL) { + uartdrvHandle[handleIdx] = handle; + handleIsSet = true; + break; + } + } + + if (!handleIsSet) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Remove handle from handle array. + ******************************************************************************/ +static Ecode_t removeHandle(UARTDRV_Handle_t handle) +{ + uint32_t handleIdx; + + if (uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == handle) { + uartdrvHandle[handleIdx] = NULL; + break; + } + } + } + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief Initialize FIFO queues for a handle. + ******************************************************************************/ +static void InitializeQueues(UARTDRV_Handle_t handle, + UARTDRV_Buffer_FifoQueue_t * rxQueue, + UARTDRV_Buffer_FifoQueue_t * txQueue) +{ + handle->rxQueue = rxQueue; + handle->rxQueue->head = 0; + handle->rxQueue->tail = 0; + handle->rxQueue->used = 0; + handle->rxDmaActive = false; + + handle->txQueue = txQueue; + handle->txQueue->head = 0; + handle->txQueue->tail = 0; + handle->txQueue->used = 0; + handle->txDmaActive = false; + + handle->IgnoreRestrain = false; +} + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +/***************************************************************************//** + * @brief Initialize GPIO-driven flow control. + ******************************************************************************/ +static void InitializeGpioFlowControl(UARTDRV_Handle_t handle) +{ + GPIOINT_CallbackRegister(handle->ctsPin, HwFcManageClearToSend); + GPIOINT_Init(); + handle->fcPeerState = uartdrvFlowControlOn; + handle->fcSelfState = uartdrvFlowControlOn; + handle->fcSelfCfg = uartdrvFlowControlAuto; + FcApplyState(handle); +} +#endif + +/***************************************************************************//** + * @brief Initialize DMA channels for a handle. + ******************************************************************************/ +static Ecode_t InitializeDma(UARTDRV_Handle_t handle) +{ + // Initialize DMA. + DMADRV_Init(); + + if (DMADRV_AllocateChannel(&handle->txDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; + } + + if (DMADRV_AllocateChannel(&handle->rxDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +/// @endcond + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/***************************************************************************//** + * @brief + * Initialize a U(S)ART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitUart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + emRequestInit(handle); + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + + handle->peripheral.uart = initData->port; + handle->type = uartdrvUartTypeUart; +#if defined(_GPIO_USART_ROUTEEN_MASK) + handle->uartNum = initData->uartNum; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(USART0) + } else if (initData->port == USART0) { + handle->uartClock = cmuClock_USART0; + handle->txDmaSignal = dmadrvPeripheralSignal_USART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART0_RXDATAV; +#endif +#if defined(USART1) + } else if (initData->port == USART1) { + handle->uartClock = cmuClock_USART1; + handle->txDmaSignal = dmadrvPeripheralSignal_USART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART1_RXDATAV; +#endif +#if defined(USART2) + } else if (initData->port == USART2) { + handle->uartClock = cmuClock_USART2; + handle->txDmaSignal = dmadrvPeripheralSignal_USART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART2_RXDATAV; +#endif +#if defined(USART3) + } else if (initData->port == USART3) { + handle->uartClock = cmuClock_USART3; + handle->txDmaSignal = dmadrvPeripheralSignal_USART3_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART3_RXDATAV; +#endif +#if defined(USART4) + } else if (initData->port == USART4) { + handle->uartClock = cmuClock_USART4; + handle->txDmaSignal = dmadrvPeripheralSignal_USART4_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART4_RXDATAV; +#endif +#if defined(USART5) + } else if (initData->port == USART5) { + handle->uartClock = cmuClock_USART5; + handle->txDmaSignal = dmadrvPeripheralSignal_USART5_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART5_RXDATAV; +#endif +#if defined(UART0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (initData->port == UART0) { + handle->uartClock = cmuClock_UART0; + handle->txDmaSignal = dmadrvPeripheralSignal_UART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART0_RXDATAV; +#endif +#if defined(UART1) + } else if (initData->port == UART1) { + handle->uartClock = cmuClock_UART1; + handle->txDmaSignal = dmadrvPeripheralSignal_UART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART1_RXDATAV; +#endif +#if defined(UART2) + } else if (initData->port == UART2) { + handle->uartClock = cmuClock_UART2; + handle->txDmaSignal = dmadrvPeripheralSignal_UART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART2_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + usartInit.baudrate = initData->baudRate; + usartInit.stopbits = initData->stopBits; + usartInit.parity = initData->parity; + usartInit.oversampling = initData->oversampling; +#if defined(USART_CTRL_MVDIS) + usartInit.mvdis = initData->mvdis; +#endif + + // UARTDRV is fixed at 8 bit frames. + usartInit.databits = (USART_Databits_TypeDef)USART_FRAME_DATABITS_EIGHT; + + // Enable clocks +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->uartClock, true); + + // Init U(S)ART to default async config. + // Rx/Tx enable is done on demand + usartInit.enable = usartDisable; + USART_InitAsync(initData->port, &usartInit); + +#if defined(USART_ROUTEPEN_TXPEN) + initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 + & ~(_USART_ROUTELOC0_TXLOC_MASK + | _USART_ROUTELOC0_RXLOC_MASK)) + | (initData->portLocationTx + << _USART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx + << _USART_ROUTELOC0_RXLOC_SHIFT); + + initData->port->ROUTEPEN = USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_TXPEN) + initData->port->ROUTE = USART_ROUTE_TXPEN + | USART_ROUTE_RXPEN + | (initData->portLocation + << _USART_ROUTE_LOCATION_SHIFT); +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_RXPEN; + GPIO->USARTROUTE[initData->uartNum].TXROUTE = + (initData->txPort << _GPIO_USART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_USART_TXROUTE_PIN_SHIFT); + GPIO->USARTROUTE[initData->uartNum].RXROUTE = + (initData->rxPort << _GPIO_USART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_USART_RXROUTE_PIN_SHIFT); +#endif + + if ((retVal = SetupGpioUart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + CORE_ENTER_ATOMIC(); + + // Configure hardware flow control pins and interrupt vectors +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHwUart) { +#if defined(UART_HW_FLOW_CONTROL_SUPPORT) +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) + initData->port->ROUTELOC1 = (initData->portLocationCts << _USART_ROUTELOC1_CTSLOC_SHIFT) + | (initData->portLocationRts << _USART_ROUTELOC1_RTSLOC_SHIFT); + initData->port->CTRLX |= USART_CTRLX_CTSEN; + initData->port->ROUTEPEN |= USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN; +#elif defined(USART_CTRLX_CTSEN) + GPIO->USARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; + initData->port->CTRLX_SET = USART_CTRLX_CTSEN; + GPIO->USARTROUTE_SET[initData->uartNum].RTSROUTE = + (initData->rtsPort << _GPIO_USART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_USART_RTSROUTE_PIN_SHIFT); + GPIO->USARTROUTE_SET[initData->uartNum].CTSROUTE = + (initData->ctsPort << _GPIO_USART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_USART_CTSROUTE_PIN_SHIFT); +#endif +#else + // Attempting to use USART hardware flow control on a device that does not + // support it. + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; +#endif + } else if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + + // Clear any false IRQ/DMA request + USART_IntClear(initData->port, ~0x0); + + // Enable Tx permanently as the Tx circuit consumes very little energy. + // Rx is enabled on demand as the Rx circuit consumes some energy due to + // continuous (over)sampling. + if (initData->fcType == uartdrvFlowControlHwUart) { + // Rx must be enabled permanently when using USART hw flow control + USART_Enable(initData->port, usartEnable); + } else { + USART_Enable(initData->port, usartEnableTx); + } + + // Discard false frames and/or IRQs + initData->port->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + // Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif // UART || USART + +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Initialize a LEUART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitLeuart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + LEUART_Init_TypeDef leuartInit = LEUART_INIT_DEFAULT; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + if (initData->fcType == uartdrvFlowControlHwUart) { + // LEUART doesn't support peripheral hw flow control + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + + handle->peripheral.leuart = initData->port; + handle->type = uartdrvUartTypeLeuart; +#if defined(_GPIO_USART_ROUTEEN_MASK) + handle->uartNum = initData->uartNum; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(LEUART0) + } else if (initData->port == LEUART0) { + handle->uartClock = cmuClock_LEUART0; + handle->txDmaSignal = dmadrvPeripheralSignal_LEUART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART0_RXDATAV; +#endif +#if defined(LEUART1) + } else if (initData->port == LEUART1) { + handle->uartClock = cmuClock_LEUART1; + handle->txDmaSignal = dmadrvPeripheralSignal_LEUART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART1_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + leuartInit.baudrate = initData->baudRate; + leuartInit.stopbits = initData->stopBits; + leuartInit.parity = initData->parity; + + // UARTDRV is fixed at 8 bit frames. + leuartInit.databits = (LEUART_Databits_TypeDef)LEUART_CTRL_DATABITS_EIGHT; + + // Enable clocks +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + CMU_ClockEnable(cmuClock_GPIO, true); +#if defined(_CMU_HFBUSCLKEN0_MASK) || defined(CMU_HFCORECLKEN0_LE) + CMU_ClockEnable(cmuClock_HFLE, true); +#endif + + // Only try to use LF clock if LFXO or LFRCO is enabled and requested baudrate is low + if (CMU->STATUS & CMU_STATUS_LFXOENS + && (leuartInit.baudrate <= SystemLFXOClockGet())) { + CMU_CLOCK_SELECT_SET(LFB, LFXO); + } else if (CMU->STATUS & CMU_STATUS_LFRCOENS + && (leuartInit.baudrate <= SystemLFRCOClockGet())) { + CMU_CLOCK_SELECT_SET(LFB, LFRCO); + } else { + // Try to figure out the prescaler that will give us the best stability + CMU_CLOCK_SELECT_SET(LFB, HFCLKLE); + +#if defined(_SILICON_LABS_32B_SERIES_0) + // Attainable baudrate lies between refclk and refclk/128. For maximum + // accuracy, we want the reference clock to be as high as possible. + uint32_t refclk = CMU_ClockFreqGet(cmuClock_LFB); + uint8_t divisor = 0; + + while (leuartInit.baudrate <= (refclk >> (divisor + 7))) { + divisor++; + } + + // If we ran out of stretch on the clock division, error out. + if (divisor > (_CMU_LFBPRESC0_LEUART0_MASK >> _CMU_LFBPRESC0_LEUART0_SHIFT)) { + return ECODE_EMDRV_UARTDRV_CLOCK_ERROR; + } + CMU_ClockDivSet(handle->uartClock, (CMU_ClkDiv_TypeDef) (1 << divisor)); +#elif defined(_SILICON_LABS_32B_SERIES_1) + // Clock divider in LEUARTn is large enough for any baudrate. +#endif + } + + CMU_ClockEnable(handle->uartClock, true); + + // Init LEUART to default async config. + // Rx/Tx enable is done on demand + leuartInit.enable = leuartDisable; + LEUART_Init(initData->port, &leuartInit); + +#if defined(LEUART_ROUTEPEN_TXPEN) + initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 + & ~(_LEUART_ROUTELOC0_TXLOC_MASK + | _LEUART_ROUTELOC0_RXLOC_MASK)) + | (initData->portLocationTx + << _LEUART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx + << _LEUART_ROUTELOC0_RXLOC_SHIFT); + + initData->port->ROUTEPEN = LEUART_ROUTEPEN_TXPEN + | LEUART_ROUTEPEN_RXPEN; +#else + initData->port->ROUTE = LEUART_ROUTE_TXPEN + | LEUART_ROUTE_RXPEN + | (initData->portLocation + << _LEUART_ROUTE_LOCATION_SHIFT); +#endif + + if ((retVal = SetupGpioLeuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + CORE_ENTER_ATOMIC(); + + // Configure hardware flow control pins and interrupt vectors +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + + // Clear any false IRQ/DMA request + LEUART_IntClear(initData->port, ~0x0); + + // Enable Tx permanently as the Tx circuit consumes very little energy. + // Rx is enabled on demand as the Rx circuit consumes some energy due to + // continuous (over)sampling. + LEUART_Enable(initData->port, leuartEnableTx); + + // Wait for previous write (TXEN) to sync before clearing FIFOs + while ((initData->port->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Discard false frames and/or IRQs + initData->port->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; + initData->port->CTRL |= LEUART_CTRL_RXDMAWU; + + // Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + // Wait for everything to be synchronized + while (initData->port->SYNCBUSY != 0U) { + } + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) || defined(DOXYGEN) + +/***************************************************************************//** + * @brief + * Initialize a EUART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitEuart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + #if defined(UARTDRV_USE_PERIPHERAL) + sl_hal_eusart_uart_config_t uartInit = SL_HAL_EUSART_UART_INIT_DEFAULT_HF; + sl_hal_eusart_uart_advanced_config_t uartAdvancedInit = SL_HAL_EUSART_UART_ADVANCED_INIT_DEFAULT; + #else + EUSART_UartInit_TypeDef uartInit = EUSART_UART_INIT_DEFAULT_HF; + EUSART_AdvancedInit_TypeDef uartAdvancedInit = EUSART_ADVANCED_INIT_DEFAULT; + #endif + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + + handle->peripheral.euart = initData->port; + handle->type = uartdrvUartTypeEuart; + handle->uartNum = initData->uartNum; + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(EUART0) + } else if (initData->port == EUART0) { + handle->uartClock = cmuClock_EUART0; + handle->txDmaSignal = dmadrvPeripheralSignal_EUART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUART0_RXDATAV; +#endif +#if defined(EUSART0) + } else if (initData->port == EUSART0) { + handle->uartClock = cmuClock_EUSART0; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART0_RXDATAV; +#endif +#if defined(EUSART1) + } else if (initData->port == EUSART1) { + handle->uartClock = cmuClock_EUSART1; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART1_RXDATAV; +#endif +#if defined(EUSART2) + } else if (initData->port == EUSART2) { + handle->uartClock = cmuClock_EUSART2; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART2_RXDATAV; +#endif +#if defined(EUSART3) + } else if (initData->port == EUSART3) { + handle->uartClock = cmuClock_EUSART3; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART3_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART3_RXDATAV; +#endif +#if defined(EUSART4) + } else if (initData->port == EUSART4) { + handle->uartClock = cmuClock_EUSART4; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART4_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART4_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + // Common configurations to all EUART/EUSART instances. + handle->txDmaActive = false; + handle->rxDmaActive = false; + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + // Enable clocks. + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->uartClock, true); + if (initData->useLowFrequencyMode) { + CMU_ClockEnable(cmuClock_LFRCO, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + CMU_ClockEnable(cmuClock_EM23GRPACLK, true); + CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFRCO); +#if defined(EUART_PRESENT) + CMU_CLOCK_SELECT_SET(EUART0, EM23GRPACLK); +#elif defined (EUSART_PRESENT) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM23GRPACLK); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_3) + CMU_CLOCK_SELECT_SET(EUSART0CLK, LFRCO); +#else + #error "Please assign a LF clock to EUSART instance" +#endif + } else { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + CMU_ClockEnable(cmuClock_EM01GRPACLK, true); +#if defined(EUART_PRESENT) + CMU_CLOCK_SELECT_SET(EUART0CLK, EM01GRPACLK); +#elif defined (EUSART_PRESENT) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPACLK); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_3) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPCCLK); +#else + #error "Please assign a HF clock to EUSART instance" +#endif + } + +#if defined(EUART_COUNT) && (EUART_COUNT > 0) + GPIO->EUARTROUTE->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; + GPIO->EUARTROUTE->TXROUTE = (initData->txPort + << _GPIO_EUART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_EUART_TXROUTE_PIN_SHIFT); + GPIO->EUARTROUTE->RXROUTE = (initData->rxPort + << _GPIO_EUART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_EUART_RXROUTE_PIN_SHIFT); +#elif defined(EUSART_COUNT) && (EUSART_COUNT > 0) + GPIO->EUSARTROUTE[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; + GPIO->EUSARTROUTE[initData->uartNum].TXROUTE = (initData->txPort + << _GPIO_EUSART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[initData->uartNum].RXROUTE = (initData->rxPort + << _GPIO_EUSART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + #endif + + if ((retVal = SetupGpioEuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + +#if defined(UARTDRV_USE_PERIPHERAL) + // UARTDRV is fixed at 8 bit frames. + uartInit.data_bits = SL_HAL_EUSART_DATA_BITS_8; + + uartInit.clock_div = sl_hal_eusart_uart_calculate_clock_div(CMU_ClockFreqGet(cmuClock_EUSART0), initData->baudRate, initData->oversampling); + uartInit.stop_bits = initData->stopBits; + uartInit.parity = initData->parity; + uartInit.oversampling = initData->oversampling; + uartInit.majority_vote = initData->mvdis; + + uartAdvancedInit.dma_wakeup_on_rx = true; + uartAdvancedInit.dma_wakeup_on_tx = false; + uartInit.advanced_config = &uartAdvancedInit; +#else + // UARTDRV is fixed at 8 bit frames. + uartInit.databits = eusartDataBits8; + + uartInit.baudrate = initData->baudRate; + uartInit.stopbits = initData->stopBits; + uartInit.parity = initData->parity; + uartInit.oversampling = initData->oversampling; + uartInit.majorityVote = initData->mvdis; + + uartAdvancedInit.dmaWakeUpOnRx = true; + uartAdvancedInit.dmaWakeUpOnTx = false; + uartInit.advancedSettings = &uartAdvancedInit; +#endif + + CORE_ENTER_ATOMIC(); + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHwUart) { +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; + GPIO->EUARTROUTE_SET[0].RTSROUTE = + (initData->rtsPort << _GPIO_EUART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_EUART_RTSROUTE_PIN_SHIFT); + GPIO->EUARTROUTE_SET[0].CTSROUTE = + (initData->ctsPort << _GPIO_EUART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_EUART_CTSROUTE_PIN_SHIFT); +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; + GPIO->EUSARTROUTE_SET[initData->uartNum].RTSROUTE = + (initData->rtsPort << _GPIO_EUSART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_EUSART_RTSROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE_SET[initData->uartNum].CTSROUTE = + (initData->ctsPort << _GPIO_EUSART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_EUSART_CTSROUTE_PIN_SHIFT); +#endif + uartAdvancedInit.hwFlowControl = eusartHwFlowControlCtsAndRts; + } else if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + +#if defined(UARTDRV_USE_PERIPHERAL) + if (initData->useLowFrequencyMode) { + sl_hal_eusart_init_uart_lf(initData->port, &uartInit); + } else { + sl_hal_eusart_init_uart_hf(initData->port, &uartInit); + } + + // Set Tx enable to follow USART implementation. + uartdrv_eusart_enable(initData->port, UARTDRV_EUSART_ENABLE_TX); +#else + // Set Tx enable to follow USART implementation. + uartInit.enable = UARTDRV_EUSART_ENABLE_TX; + + if (initData->useLowFrequencyMode) { + EUSART_UartInitLf(initData->port, &uartInit); + } else { + EUSART_UartInitHf(initData->port, &uartInit); + } +#endif + +// Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief + * Deinitialize a UART driver instance. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + // Stop DMA transfers. + UARTDRV_Abort(handle, uartdrvAbortAll); + + // Do not leave any peer restrained on DeInit + UARTDRV_FlowControlSet(handle, uartdrvFlowControlOn); + + ConfigGpio(handle, false); + +#if (HANDLES_ARE_AVAILABLE) + removeHandle(handle); +#endif + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + handle->peripheral.uart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS; +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + LEUART_Reset(handle->peripheral.leuart); + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS; + +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + uartdrv_eusart_reset(handle->peripheral.euart); +#endif + } + + CMU_ClockEnable(handle->uartClock, false); + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + GPIOINT_CallbackRegister(handle->ctsPin, NULL); + } +#endif + + DMADRV_FreeChannel(handle->txDmaCh); + DMADRV_FreeChannel(handle->rxDmaCh); + DMADRV_DeInit(); + + handle->rxQueue->head = 0; + handle->rxQueue->tail = 0; + handle->rxQueue->used = 0; + + handle->txQueue->head = 0; + handle->txQueue->tail = 0; + handle->txQueue->used = 0; + + emRequestDeinit(handle); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Abort ongoing UART transfers. + * + * @details + * All ongoing or queued operations of the given abort type will be aborted. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] type Abort type -- whether to abort only Tx, only Rx, or both. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success, @ref ECODE_EMDRV_UARTDRV_IDLE if + * the UART is idle. On failure, an appropriate UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type) +{ + UARTDRV_Buffer_t *rxBuffer, *txBuffer; + CORE_DECLARE_IRQ_STATE; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + CORE_ENTER_ATOMIC(); + if ((type == uartdrvAbortTransmit) && (handle->txQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } else if ((type == uartdrvAbortReceive) && (handle->rxQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } else if ((type == uartdrvAbortAll) + && (handle->txQueue->used == 0) + && (handle->rxQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } + + // Stop DMA transfers. + if ((type == uartdrvAbortTransmit) || (type == uartdrvAbortAll)) { + // Stop the current transfer + DMADRV_StopTransfer(handle->txDmaCh); + handle->txDmaActive = false; + + if (handle->txQueue->used > 0) { + // Update the transfer status of the active transfer + GetTailBuffer(handle->txQueue, &txBuffer); + DMADRV_TransferRemainingCount(handle->txDmaCh, + (int*)&txBuffer->itemsRemaining); + txBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // Dequeue all transfers and call callback + while (handle->txQueue->used > 0) { + DequeueBuffer(handle->txQueue, &txBuffer); + + // Call the callback with ABORTED error code + if (txBuffer->callback != NULL) { + txBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_ABORTED, + NULL, + txBuffer->itemsRemaining); + } + } + } + + // Wait for peripheral to finish cleaning up, to prevent framing errors + // on subsequent transfers + while (!(UARTDRV_GetPeripheralStatus(handle) & UARTDRV_STATUS_TXIDLE)) { + } + } + if ((type == uartdrvAbortReceive) || (type == uartdrvAbortAll)) { + // Stop the current transfer + DMADRV_StopTransfer(handle->rxDmaCh); + handle->rxDmaActive = false; + + if (handle->rxQueue->used > 0) { + // Update the transfer status of the active transfer + GetTailBuffer(handle->rxQueue, &rxBuffer); + DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int*)&rxBuffer->itemsRemaining); + rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // Dequeue all transfers and call callback + while (handle->rxQueue->used > 0) { + DequeueBuffer(handle->rxQueue, &rxBuffer); + + // Call the callback with ABORTED error code + if (rxBuffer->callback != NULL) { + rxBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_ABORTED, + NULL, + rxBuffer->itemsRemaining); + } + } + } + + // Disable the receiver + if (handle->fcType != uartdrvFlowControlHwUart) { + DisableReceiver(handle); + } + } + + if (handle->em1RequestCount > 0) { + em1RequestRemove(handle); + } + + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Return the status of the UART peripheral associated with a given handle. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * UART status value + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle) +{ + UARTDRV_Status_t status = 0; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (handle->type == uartdrvUartTypeUart) { + status = handle->peripheral.uart->STATUS; + } else if (handle->type == uartdrvUartTypeLeuart) { + uint32_t reg = handle->peripheral.leuart->STATUS; + if (reg & LEUART_STATUS_TXENS) { + status |= UARTDRV_STATUS_TXEN; + } + if (reg & LEUART_STATUS_RXENS) { + status |= UARTDRV_STATUS_RXEN; + } + if (reg & LEUART_STATUS_RXBLOCK) { + status |= UARTDRV_STATUS_RXBLOCK; + } + if (reg & LEUART_STATUS_TXC) { + status |= UARTDRV_STATUS_TXC; + } + if (reg & LEUART_STATUS_TXBL) { + status |= UARTDRV_STATUS_TXBL; + } + if (reg & LEUART_STATUS_RXDATAV) { + status |= UARTDRV_STATUS_RXDATAV; + } +#if defined(LEUART_STATUS_TXIDLE) + if (reg & LEUART_STATUS_TXIDLE) { + status |= UARTDRV_STATUS_TXIDLE; + } +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + status = handle->peripheral.uart->STATUS; +#endif + } else if ((handle->type == uartdrvUartTypeEuart)) { + status = uartdrv_eusart_get_status(handle->peripheral.euart); + } +#else + status = handle->peripheral.uart->STATUS; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) + // Series 0 devices does not have the TXIDLE flag, so we emulate it + if ((status & UARTDRV_STATUS_TXC) || !(handle->hasTransmitted)) { + status |= UARTDRV_STATUS_TXIDLE; + } +#endif + + return status; +} + +/***************************************************************************//** + * @brief + * Return the number of queued receive operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * The number of queued operations. + ******************************************************************************/ +uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle) +{ + return (uint8_t)handle->rxQueue->used; +} + +/***************************************************************************//** + * @brief + * Check the status of the UART and gather information about any ongoing + * receive operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[out] buffer Pointer to the current data buffer. + * + * @param[out] itemsReceived Current bytes received count. + * + * @param[out] itemsRemaining Current bytes remaining count. + * + * @return + * UART status. + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *itemsReceived, + UARTDRV_Count_t *itemsRemaining) +{ + UARTDRV_Buffer_t *rxBuffer = NULL; + Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; + uint32_t remaining = 0; + + if (handle->rxQueue->used > 0) { + retVal = GetTailBuffer(handle->rxQueue, &rxBuffer); + DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int*)&remaining); + } + + if (rxBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { + *itemsReceived = rxBuffer->transferCount - remaining; + *itemsRemaining = remaining; + *buffer = rxBuffer->data; + } else { + *itemsRemaining = 0; + *itemsReceived = 0; + *buffer = NULL; + } + + return UARTDRV_GetPeripheralStatus(handle); +} + +/***************************************************************************//** + * @brief + * Returns the number of queued transmit operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * The number of queued operations. + ******************************************************************************/ +uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle) +{ + return (uint8_t)handle->txQueue->used; +} + +/***************************************************************************//** + * @brief + * Check the status of the UART and gather information about any ongoing + * transmit operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[out] buffer Pointer to the current data buffer. + * + * @param[out] itemsSent Current bytes sent count. + * + * @param[out] itemsRemaining Current bytes remaining count. + * + * @return + * UART status. + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *itemsSent, + UARTDRV_Count_t *itemsRemaining) +{ + UARTDRV_Buffer_t *txBuffer = NULL; + Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; + uint32_t remaining = 0; + + if (handle->txQueue->used > 0) { + retVal = GetTailBuffer(handle->txQueue, &txBuffer); + DMADRV_TransferRemainingCount(handle->txDmaCh, + (int*)&remaining); + } + + if (txBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { + *itemsSent = txBuffer->transferCount - remaining; + *itemsRemaining = remaining; + *buffer = txBuffer->data; + } else { + *itemsRemaining = 0; + *itemsSent = 0; + *buffer = NULL; + } + + return UARTDRV_GetPeripheralStatus(handle); +} + +/***************************************************************************//** + * @brief + * Set UART flow control state. Set nRTS pin if hardware flow control + * is enabled. Send XON/XOFF if software flow control is enabled. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] state Flow control state. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) +{ +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHwUart) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + handle->fcSelfCfg = state; + if (state != uartdrvFlowControlAuto) { + handle->fcSelfState = state; + } + return FcApplyState(handle); +#else + (void) handle; + (void) state; + return ECODE_EMDRV_UARTDRV_OK; +#endif +} + +/***************************************************************************//** + * @brief + * Set peer UART flow control state. Pause/resume transmit accordingly. + * Only for manual software flow control. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] state Flow control state. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) +{ + if ( (handle->fcType != uartdrvFlowControlSw) + || (state == uartdrvFlowControlAuto) ) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + + if (handle->fcPeerState != state) { + handle->fcPeerState = state; + if (state == uartdrvFlowControlOn) { + UARTDRV_ResumeTransmit(handle); + } else if (state == uartdrvFlowControlOff) { + UARTDRV_PauseTransmit(handle); + } + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Check the peer's flow control status. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * Returns uartdrvFlowControlOn if clear to send. + ******************************************************************************/ +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle) +{ + return handle->fcPeerState; +} + +/***************************************************************************//** + * @brief + * Check the self flow control status. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * Returns uartdrvFlowControlOn if requesting to send. + ******************************************************************************/ +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle) +{ + return handle->fcSelfState; +} + +/***************************************************************************//** + * @brief + * Enable transmission when restrained by flow control. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle) +{ + handle->IgnoreRestrain = true; + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Direct receive without interrupts or callback. This is a blocking function. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data pointer to buffer. + * + * @param[in] maxCount Maximum number of bytes to receive. + * + * @return + * Number of bytes received. + ******************************************************************************/ +UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t maxCount) +{ + Ecode_t retVal; + uint32_t rxState; + UARTDRV_Count_t i = 0; + + retVal = CheckParams(handle, data, maxCount); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return 0; + } + + // Wait for DMA receive to complete and clear + while (handle->rxQueue->used > 0) { + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + rxState = (handle->peripheral.uart->STATUS & USART_STATUS_RXENS); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + rxState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS); +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + rxState = (handle->peripheral.euart->STATUS & EUSART_STATUS_RXENS); +#endif + } else { + EFM_ASSERT(false); + rxState = 0; + } + + if (!rxState) { + EnableReceiver(handle); + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + while ((handle->peripheral.uart->STATUS & USART_STATUS_RXDATAV) != 0U) { + *data = (uint8_t)handle->peripheral.uart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + while ((handle->peripheral.leuart->STATUS & LEUART_STATUS_RXDATAV) != 0U) { + *data = (uint8_t)handle->peripheral.leuart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + while ((handle->peripheral.euart->STATUS & EUSART_STATUS_RXFL) != 0U) { + *data = (uint8_t)handle->peripheral.euart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif + } + + data -= i; + + if (!rxState) { + DisableReceiver(handle); + } + return i; +} + +/***************************************************************************//** + * @brief + * Direct transmit without interrupts or callback. This is a blocking function. + * that ignores flow control if enabled. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data Pointer to the buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + uint32_t txState; + bool callDmaIrqHandler; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + // Wait for DMA transmit to complete and clear + callDmaIrqHandler = CORE_IrqIsBlocked(UART_DMA_IRQ); // Loop invariant + while ((handle->txQueue->used > 0) && (!handle->txDmaPaused)) { + if (callDmaIrqHandler) { + UART_DMA_IRQHANDLER(); + } + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; +#endif + } else { + EFM_ASSERT(false); + txState = 0; + } + + if (!txState) { + EnableTransmitter(handle); + } + + handle->hasTransmitted = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + while (count-- != 0U) { + USART_Tx(handle->peripheral.uart, *data++); + } + // Wait for Tx completion + while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXC)) { + } +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + while (count-- != 0U) { + LEUART_Tx(handle->peripheral.leuart, *data++); + } + // Wait for Tx completion + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXC)) { + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + while (count-- != 0U) { + uartdrv_eusart_tx(handle->peripheral.euart, *data++); + } + while (~uartdrv_eusart_get_status(handle->peripheral.euart) & (EUSART_STATUS_TXC | EUSART_STATUS_TXIDLE)) { + } +#endif + } + + if (!txState) { + DisableTransmitter(handle); + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Pause an ongoing transmit operation. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + // Pause the transfer if 1) pause counter is 0 + // 2) HW flow control hasn't already paused the DMA + if ( (handle->txDmaPaused == 0) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { + DMADRV_PauseTransfer(handle->txDmaCh); + } + // Increment counter to allow nested calls + handle->txDmaPaused++; + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a non-blocking receive. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A receive data buffer. + * + * @param[in] count A number of bytes received. + * + * @param[in] callback A transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback) +{ + Ecode_t retVal; + UARTDRV_Buffer_t outputBuffer; + UARTDRV_Buffer_t *queueBuffer; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + outputBuffer.data = data; + outputBuffer.transferCount = count; + outputBuffer.itemsRemaining = count; + outputBuffer.callback = callback; + outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + + retVal = EnqueueBuffer(handle->rxQueue, &outputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if (!(handle->rxDmaActive)) { + EnableReceiver(handle); + StartReceiveDma(handle, queueBuffer); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType != uartdrvFlowControlHwUart) { + handle->fcSelfState = uartdrvFlowControlOn; + FcApplyState(handle); + } +#endif + } // else: started by ReceiveDmaComplete + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a blocking receive. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A receive data buffer. + * + * @param[in] count A number of bytes received. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + UARTDRV_Buffer_t inputBuffer; + UARTDRV_Buffer_t *queueBuffer; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + inputBuffer.data = data; + inputBuffer.transferCount = count; + inputBuffer.itemsRemaining = count; + inputBuffer.callback = NULL; + inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + + retVal = EnqueueBuffer(handle->rxQueue, &inputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->rxQueue->used > 1) { + } + EnableReceiver(handle); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType != uartdrvFlowControlHwUart) { + handle->fcSelfState = uartdrvFlowControlOn; + FcApplyState(handle); + } +#endif + StartReceiveDma(handle, queueBuffer); + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->rxDmaActive) { + } + return queueBuffer->transferStatus; +} + +/***************************************************************************//** + * @brief + * Resume a paused transmit operation. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + if (handle->txDmaPaused > 0) { + // Resume the transfer if 1) pause counter is 1 + // 2) HW flow control doesn't need to pause the DMA + if ( (handle->txDmaPaused == 1) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { + DMADRV_ResumeTransfer(handle->txDmaCh); + } + handle->txDmaPaused--; + } else { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a non-blocking transmit. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A transmit data buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @param[in] callback A transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback) +{ + Ecode_t retVal; + UARTDRV_Buffer_t inputBuffer; + UARTDRV_Buffer_t *queueBuffer; + uint32_t txState; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + inputBuffer.data = data; + inputBuffer.transferCount = count; + inputBuffer.itemsRemaining = count; + inputBuffer.callback = callback; + inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); + } else { + EFM_ASSERT(false); + txState = 0; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; + } else { + EFM_ASSERT(false); + txState = 0; + } +#else + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + + if (!txState) { + EnableTransmitter(handle); + } + + retVal = EnqueueBuffer(handle->txQueue, &inputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if (!(handle->txDmaActive)) { + CORE_ATOMIC_SECTION( + if (handle->txQueue->used > 0) { + StartTransmitDma(handle, queueBuffer); + handle->hasTransmitted = true; + } + ) + } // else: started by TransmitDmaComplete + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a blocking transmit. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A transmit data buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + UARTDRV_Buffer_t outputBuffer; + UARTDRV_Buffer_t *queueBuffer; + uint32_t txState; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + outputBuffer.data = data; + outputBuffer.transferCount = count; + outputBuffer.itemsRemaining = count; + outputBuffer.callback = NULL; + outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); + } else { + EFM_ASSERT(false); + txState = 0; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; + } else { + EFM_ASSERT(false); + txState = 0; + } +#else + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + + if (!txState) { + EnableTransmitter(handle); + } + + retVal = EnqueueBuffer(handle->txQueue, &outputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->txQueue->used > 1) { + } + StartTransmitDma(handle, queueBuffer); + handle->hasTransmitted = true; + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->txDmaActive) { + } + + return queueBuffer->transferStatus; +} + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void) +{ + sl_power_manager_on_isr_exit_t result = SL_POWER_MANAGER_IGNORE; + uint32_t handleIdx; + UARTDRV_Handle_t handle; + + if (uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + handle = uartdrvHandle[handleIdx]; + if (handle != NULL) { + if ((sl_power_manager_on_isr_exit_t)handle->sleep == SL_POWER_MANAGER_SLEEP) { + handle->sleep = SL_POWER_MANAGER_IGNORE; + result = SL_POWER_MANAGER_SLEEP; + } + } + } + } + + return result; +} +#endif + +/******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** + * @addtogroup uartdrv UARTDRV - UART Driver + * @brief Universal Asynchronous Receiver/Transmitter Driver + * @{ + + @details + The source files for the UART driver library, uartdrv.c and uartdrv.h, are in the + emdrv/uartdrv folder. + + @n @section uartdrv_intro Introduction + The UART driver supports the UART capabilities of the USART, UART, and LEUART + peripherals. The driver is fully reentrant and supports multiple driver instances. + The driver does not buffer or queue data. However, it queues UART transmit + and receive operations. Both blocking and non-blocking transfer functions are + available. Non-blocking transfer functions report transfer completion with + callback functions. Transfers are done using DMA. Simple direct/forced + transmit and receive functions are also available. Note that these functions + are blocking and not suitable for low energy applications because they use CPU + polling. + + UART hardware flow control (CTS/RTS) is fully supported by the driver. UART + software flow control (XON/XOFF) is partially supported by the driver. For + more information about flow control support, see @ref uartdrv_fc. + + @note Transfer completion callback functions are called from within the DMA + interrupt handler with interrupts disabled. + + @n @section uartdrv_conf Configuration Options + + Some properties of the UARTDRV driver are compile-time configurable. These + properties are set in a uartdrv_config.h file. A template for this + file, containing default values, is in the emdrv/config folder. + To configure UARTDRV for your application, provide a custom configuration file, + or override the defines on the compiler command line. + These are the available configuration parameters with default values defined. + @code + + // Set to 1 to enable hardware flow control. + #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 + + // Maximum number of driver instances. + #define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 + + // UART software flow control code: request peer to start Tx. + #define UARTDRV_FC_SW_XON 0x11 + + // UART software flow control code: request peer to stop Tx. + #define UARTDRV_FC_SW_XOFF 0x13 + @endcode + + The properties of each UART driver instance are set at run-time via the + @ref UARTDRV_InitUart_t data structure input parameter to the @ref UARTDRV_InitUart() + function for UART and USART peripherals, and the @ref UARTDRV_InitLeuart_t + data structure input parameter to the @ref UARTDRV_InitLeuart() function for + LEUART peripherals. + + @n @section uartdrv_api The API + + This section contains brief descriptions of the functions in the API. For more + information on input and output parameters and return values, + click on the hyperlinked function names. Most functions return an error + code, @ref ECODE_EMDRV_UARTDRV_OK is returned on success, + see ecode.h and uartdrv.h for other error codes. + + The application code must include @em uartdrv.h header file. + + @ref UARTDRV_InitUart(), @ref UARTDRV_InitLeuart() and @ref UARTDRV_DeInit() @n + These functions initialize and deinitialize the UARTDRV driver. Typically, + UARTDRV_InitUart() (for UART/USART) or + UARTDRV_InitLeuart() (for LEUART) are called once in + the startup code. + + @ref UARTDRV_GetReceiveStatus() and @ref UARTDRV_GetTransmitStatus() @n + Query the status of a current transmit or receive operations. Reports number + of items (frames) transmitted and remaining. + + @ref UARTDRV_GetReceiveDepth() and @ref UARTDRV_GetTransmitDepth() @n + Get the number of queued receive or transmit operations. + + @ref UARTDRV_Transmit(), UARTDRV_Receive() @n + UARTDRV_TransmitB(), UARTDRV_ReceiveB() @n + UARTDRV_ForceTransmit() and UARTDRV_ForceReceive() @n + Blocking and non-blocking transfer functions are included. + The blocking versions have an uppercase B (for Blocking) at the end of + their function name. Blocking functions do not return before the transfer + is complete. The non-blocking functions signal a transfer completion with a + callback function. @ref UARTDRV_ForceTransmit() and + @ref UARTDRV_ForceReceive() are also blocking. These two functions access + the UART peripheral directly without using DMA or interrupts. + @ref UARTDRV_ForceTransmit() does not respect flow control. + @ref UARTDRV_ForceReceive() forces RTS low. + + @ref UARTDRV_Abort() @n + Abort current transmit or receive operations and remove all queued + operations. + + @ref UARTDRV_FlowControlSet(), @ref UARTDRV_FlowControlGetSelfStatus(), @ref UARTDRV_FlowControlSetPeerStatus() and @ref UARTDRV_FlowControlGetPeerStatus() @n + Set and get flow control status of self or peer device. Note that the return + value from these two functions depends on the flow control mode set by + @ref UARTDRV_FlowControlSet(), @ref UARTDRV_InitUart(), or + @ref UARTDRV_InitLeuart(). + + @ref UARTDRV_FlowControlIgnoreRestrain() @n + Enables transmission when restrained by flow control. + + @ref UARTDRV_PauseTransmit() and @ref UARTDRV_ResumeTransmit() @n + Pause a currently active transmit operation by preventing the DMA from loading + the UART FIFO. Will not override HW flow control state (if applicable), but + can be used in conjunction. + + @n @section uartdrv_fc Flow Control Support + + If UART flow control is not required, make sure that + EMDRV_UARTDRV_FLOW_CONTROL_ENABLE is set to 0. This reduces the code size + and complexity of the driver. + + Both hardware and software flow control are supported. To + enable either of these, set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1 in + uartdrv_config.h. + + @n @subsection uartdrv_fc_hw Hardware Flow Control + + UART hardware flow control uses two additional pins for flow control + handshaking, the clear-to-send (CTS) and ready-to-send (RTS) pins. + RTS is an output and CTS is an input. These are active-low signals. + When CTS is high, the UART transmitter should stop sending frames. + A receiver should set RTS high when it is no longer capable of + receiving data. + + @par Peripheral Hardware Flow Control + + Newer devices natively support CTS/RTS in + the USART peripheral hardware. To enable hardware flow control, perform the + following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - In the @ref UARTDRV_InitUart_t struct passed to @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHwUart. + - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort + and rtsPin in the init struct. + - Also define the CTS and RTS locations by setting portLocationCts and + portLocationRts in the init struct. + + @par GPIO Hardware Flow Control + + To support hardware flow control on devices that don't have UART CTS/RTS + hardware support, the driver includes the GPIOINT driver to emulate a + hardware implementation of UART CTS/RTS flow control on these devices. + + To enable hardware flow control, perform the following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - UART/USART: In the @ref UARTDRV_InitUart_t struct passed to + @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHw. + - LEUART: In the @ref UARTDRV_InitLeuart_t struct passed to + @ref UARTDRV_InitLeuart(), set + @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlHw. + - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort and + rtsPin in the same init struct. + + @note Because of the limitations in GPIO interrupt hardware, you cannot select + CTS pins in multiple driver instances with the same pin number. For example, pin A0 and + B0 cannot serve as CTS pins in two concurrent driver instances. + + RTS is set high whenever there are no Rx operations queued. The UART + transmitter is halted when the CTS pin goes high. The transmitter completes + the current frame before halting. DMA transfers are also halted. + + @n @subsection uartdrv_fc_sw Software Flow Control + + UART software flow control uses in-band signaling, meaning the receiver sends + special flow control characters to the transmitter and thereby removes + the need for dedicated wires for flow control. The two symbols + UARTDRV_FC_SW_XON and UARTDRV_FC_SW_XOFF are defined in uartdrv_config.h. + + To enable support for software flow control, perform the following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - UART/USART: In the @ref UARTDRV_InitUart_t structure passed to + @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlSw. + - LEUART: In the @ref UARTDRV_InitLeuart_t structure passed to + @ref UARTDRV_InitLeuart(), set + @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlSw. + + @note Software flow control is partial only. + + The application must monitor buffers and make decisions on when to send XON/ + XOFF. XON/XOFF can be sent to the peer using @ref UARTDRV_FlowControlSet(). + Though @ref UARTDRV_FlowControlSet() will pause the active transmit operation + to send a flow control character, there is no way to guarantee the order. + If the application implements a specific packet format where the flow control + codes may appear only in fixed positions, the application should not + use @ref UARTDRV_FlowControlSet() but implement read and write of XON/XOFF + into packet buffers. If the application code fully implements all the flow + control logic, EMDRV_UARTDRV_FLOW_CONTROL_ENABLE should be set to 0 + to reduce code space. + + @n @section uartdrv_example Example + @if DOXYDOC_P1_DEVICE + @if DOXYDOC_EFM32G + @include uartdrv_example_p1_nomvdis.c + @endif + @if DOXYDOC_EZR32HG + @include uartdrv_example_p1_usart0.c + @endif + @ifnot (DOXYDOC_EFM32G || DOXYDOC_EZR32HG) + @include uartdrv_example_p1.c + @endif + @endif + @if DOXYDOC_P2_DEVICE + @include uartdrv_example_p2.c + @endif + @if DOXYDOC_S2_DEVICE + @include uartdrv_example_s2.c + @endif + + * @} end group uartdrv *********************************************************/ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_acmp.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_acmp.h index 3079df8..cf3e815 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_acmp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_acmp.h @@ -1,1146 +1,1146 @@ -/***************************************************************************//** - * @file - * @brief Analog Comparator (ACMP) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_ACMP_H -#define EM_ACMP_H - -#include "em_device.h" -#include "em_gpio.h" - -#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup acmp - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Resistor values used for the internal capacitive sense resistor. See - * data sheet for your device for details on each resistor value. */ -typedef enum { -#if defined(_ACMP_INPUTCTRL_CSRESSEL_MASK) - acmpResistor0 = _ACMP_INPUTCTRL_CSRESSEL_RES0, /**< Resistor value 0 */ - acmpResistor1 = _ACMP_INPUTCTRL_CSRESSEL_RES1, /**< Resistor value 1 */ - acmpResistor2 = _ACMP_INPUTCTRL_CSRESSEL_RES2, /**< Resistor value 2 */ - acmpResistor3 = _ACMP_INPUTCTRL_CSRESSEL_RES3, /**< Resistor value 3 */ - acmpResistor4 = _ACMP_INPUTCTRL_CSRESSEL_RES4, /**< Resistor value 4 */ - acmpResistor5 = _ACMP_INPUTCTRL_CSRESSEL_RES5, /**< Resistor value 5 */ - acmpResistor6 = _ACMP_INPUTCTRL_CSRESSEL_RES6, /**< Resistor value 6 */ -#else - acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */ - acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */ - acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */ - acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3, /**< Resistor value 3 */ -#if defined(_ACMP_INPUTSEL_CSRESSEL_RES4) - acmpResistor4 = _ACMP_INPUTSEL_CSRESSEL_RES4, /**< Resistor value 4 */ - acmpResistor5 = _ACMP_INPUTSEL_CSRESSEL_RES5, /**< Resistor value 5 */ - acmpResistor6 = _ACMP_INPUTSEL_CSRESSEL_RES6, /**< Resistor value 6 */ - acmpResistor7 = _ACMP_INPUTSEL_CSRESSEL_RES7, /**< Resistor value 7 */ -#endif -#endif -} ACMP_CapsenseResistor_TypeDef; - -/** Hysteresis level. See data sheet for your device for details on each - * level. */ -typedef enum { -#if defined(_ACMP_CTRL_HYSTSEL_MASK) - acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */ - acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */ - acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */ - acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */ - acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */ - acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */ - acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */ - acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */ -#endif -#if defined(_ACMP_HYSTERESIS0_HYST_MASK) - acmpHysteresisLevel0 = _ACMP_HYSTERESIS0_HYST_HYST0, /**< Hysteresis level 0 */ - acmpHysteresisLevel1 = _ACMP_HYSTERESIS0_HYST_HYST1, /**< Hysteresis level 1 */ - acmpHysteresisLevel2 = _ACMP_HYSTERESIS0_HYST_HYST2, /**< Hysteresis level 2 */ - acmpHysteresisLevel3 = _ACMP_HYSTERESIS0_HYST_HYST3, /**< Hysteresis level 3 */ - acmpHysteresisLevel4 = _ACMP_HYSTERESIS0_HYST_HYST4, /**< Hysteresis level 4 */ - acmpHysteresisLevel5 = _ACMP_HYSTERESIS0_HYST_HYST5, /**< Hysteresis level 5 */ - acmpHysteresisLevel6 = _ACMP_HYSTERESIS0_HYST_HYST6, /**< Hysteresis level 6 */ - acmpHysteresisLevel7 = _ACMP_HYSTERESIS0_HYST_HYST7, /**< Hysteresis level 7 */ - acmpHysteresisLevel8 = _ACMP_HYSTERESIS0_HYST_HYST8, /**< Hysteresis level 8 */ - acmpHysteresisLevel9 = _ACMP_HYSTERESIS0_HYST_HYST9, /**< Hysteresis level 9 */ - acmpHysteresisLevel10 = _ACMP_HYSTERESIS0_HYST_HYST10, /**< Hysteresis level 10 */ - acmpHysteresisLevel11 = _ACMP_HYSTERESIS0_HYST_HYST11, /**< Hysteresis level 11 */ - acmpHysteresisLevel12 = _ACMP_HYSTERESIS0_HYST_HYST12, /**< Hysteresis level 12 */ - acmpHysteresisLevel13 = _ACMP_HYSTERESIS0_HYST_HYST13, /**< Hysteresis level 13 */ - acmpHysteresisLevel14 = _ACMP_HYSTERESIS0_HYST_HYST14, /**< Hysteresis level 14 */ - acmpHysteresisLevel15 = _ACMP_HYSTERESIS0_HYST_HYST15, /**< Hysteresis level 15 */ -#endif -#if defined(_ACMP_CFG_HYST_MASK) - acmpHysteresisDisabled = _ACMP_CFG_HYST_DISABLED, /**< Mode DISABLED for ACMP_CFG */ - acmpHysteresis10Sym = _ACMP_CFG_HYST_SYM10MV, /**< Mode HYST10SYM for ACMP_CFG */ - acmpHysteresis20Sym = _ACMP_CFG_HYST_SYM20MV, /**< Mode HYST20SYM for ACMP_CFG */ - acmpHysteresis30Sym = _ACMP_CFG_HYST_SYM30MV, /**< Mode HYST30SYM for ACMP_CFG */ - acmpHysteresis10Pos = _ACMP_CFG_HYST_POS10MV, /**< Mode HYST10POS for ACMP_CFG */ - acmpHysteresis20Pos = _ACMP_CFG_HYST_POS20MV, /**< Mode HYST20POS for ACMP_CFG */ - acmpHysteresis30Pos = _ACMP_CFG_HYST_POS30MV, /**< Mode HYST30POS for ACMP_CFG */ - acmpHysteresis10Neg = _ACMP_CFG_HYST_NEG10MV, /**< Mode HYST10NEG for ACMP_CFG */ - acmpHysteresis20Neg = _ACMP_CFG_HYST_NEG20MV, /**< Mode HYST20NEG for ACMP_CFG */ - acmpHysteresis30Neg = _ACMP_CFG_HYST_NEG30MV, /**< Mode HYST30NEG for ACMP_CFG */ -#endif -} ACMP_HysteresisLevel_TypeDef; - -#if defined(_ACMP_CTRL_WARMTIME_MASK) -/** ACMP warmup time. The delay is measured in HFPERCLK / HFPERCCLK cycles and should - * be at least 10 us. */ -typedef enum { - /** 4 cycles warmup */ - acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES, - /** 8 cycles warmup */ - acmpWarmTime8 = _ACMP_CTRL_WARMTIME_8CYCLES, - /** 16 cycles warmup */ - acmpWarmTime16 = _ACMP_CTRL_WARMTIME_16CYCLES, - /** 32 cycles warmup */ - acmpWarmTime32 = _ACMP_CTRL_WARMTIME_32CYCLES, - /** 64 cycles warmup */ - acmpWarmTime64 = _ACMP_CTRL_WARMTIME_64CYCLES, - /** 128 cycles warmup */ - acmpWarmTime128 = _ACMP_CTRL_WARMTIME_128CYCLES, - /** 256 cycles warmup */ - acmpWarmTime256 = _ACMP_CTRL_WARMTIME_256CYCLES, - /** 512 cycles warmup */ - acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES -} ACMP_WarmTime_TypeDef; -#endif - -#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ - || defined(_ACMP_CFG_INPUTRANGE_MASK) -/** - * Adjust ACMP performance for a given input voltage range. - */ -typedef enum { -#if defined(_ACMP_CTRL_INPUTRANGE_MASK) - acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ - acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than VDD/2. */ - acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than VDD/2. */ -#elif defined(_ACMP_CFG_INPUTRANGE_MASK) - acmpInputRangeFull = _ACMP_CFG_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ - acmpInputRangeReduced = _ACMP_CFG_INPUTRANGE_REDUCED, /**< Input can be from 0 to VDD-0.7 V. */ -#endif -} ACMP_InputRange_TypeDef; -#endif - -#if defined(_ACMP_CTRL_PWRSEL_MASK) -/** - * ACMP Power source. - */ -typedef enum { - acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power ACMP using the AVDD supply. */ -#if defined(_ACMP_CTRL_PWRSEL_DVDD) - acmpPowerSourceDvdd = _ACMP_CTRL_PWRSEL_DVDD, /**< Power ACMP using the DVDD supply. */ -#endif - acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power ACMP using the IOVDD/IOVDD0 supply. */ - acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power ACMP using the IOVDD1 supply (if the part has two I/O voltages). */ -} ACMP_PowerSource_TypeDef; -#endif - -#if defined(_ACMP_CTRL_ACCURACY_MASK) \ - || defined(_ACMP_CFG_ACCURACY_MASK) -/** - * ACMP accuracy mode. - */ -typedef enum { -#if defined(_ACMP_CTRL_ACCURACY_MASK) - acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ - acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ -#elif defined(_ACMP_CFG_ACCURACY_MASK) - acmpAccuracyLow = _ACMP_CFG_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ - acmpAccuracyHigh = _ACMP_CFG_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ -#endif -} ACMP_Accuracy_TypeDef; -#endif - -#if defined(_ACMP_INPUTSEL_VASEL_MASK) -/** ACMP input to the VA divider. This enumeration is used to select the input for - * the VA Divider. */ -typedef enum { - acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD, /**< Select VDD for the VA divider. */ - acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0, /**< Select APORT2Y CHannel 0 for the VA divider. */ - acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2, /**< Select APORT2Y CHannel 2 for the VA divider. */ - acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4, /**< Select APORT2Y CHannel 4 for the VA divider. */ - acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6, /**< Select APORT2Y CHannel 6 for the VA divider. */ - acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8, /**< Select APORT2Y CHannel 8 for the VA divider. */ - acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10, /**< Select APORT2Y CHannel 10 for the VA divider. */ - acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12, /**< Select APORT2Y CHannel 12 for the VA divider. */ - acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14, /**< Select APORT2Y CHannel 14 for the VA divider. */ - acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16, /**< Select APORT2Y CHannel 16 for the VA divider. */ - acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18, /**< Select APORT2Y CHannel 18 for the VA divider. */ - acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20, /**< Select APORT2Y CHannel 20 for the VA divider. */ - acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22, /**< Select APORT2Y CHannel 22 for the VA divider. */ - acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24, /**< Select APORT2Y CHannel 24 for the VA divider. */ - acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26, /**< Select APORT2Y CHannel 26 for the VA divider. */ - acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28, /**< Select APORT2Y CHannel 28 for the VA divider. */ - acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30, /**< Select APORT2Y CHannel 30 for the VA divider. */ - acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0, /**< Select APORT1X CHannel 0 for the VA divider. */ - acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1, /**< Select APORT1Y CHannel 1 for the VA divider. */ - acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2, /**< Select APORT1X CHannel 2 for the VA divider. */ - acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3, /**< Select APORT1Y CHannel 3 for the VA divider. */ - acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4, /**< Select APORT1X CHannel 4 for the VA divider. */ - acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5, /**< Select APORT1Y CHannel 5 for the VA divider. */ - acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6, /**< Select APORT1X CHannel 6 for the VA divider. */ - acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7, /**< Select APORT1Y CHannel 7 for the VA divider. */ - acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8, /**< Select APORT1X CHannel 8 for the VA divider. */ - acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9, /**< Select APORT1Y CHannel 9 for the VA divider. */ - acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10, /**< Select APORT1X CHannel 10 for the VA divider. */ - acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11, /**< Select APORT1Y CHannel 11 for the VA divider. */ - acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12, /**< Select APORT1X CHannel 12 for the VA divider. */ - acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13, /**< Select APORT1Y CHannel 13 for the VA divider. */ - acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14, /**< Select APORT1X CHannel 14 for the VA divider. */ - acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15, /**< Select APORT1Y CHannel 15 for the VA divider. */ - acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16, /**< Select APORT1X CHannel 16 for the VA divider. */ - acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17, /**< Select APORT1Y CHannel 17 for the VA divider. */ - acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18, /**< Select APORT1X CHannel 18 for the VA divider. */ - acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19, /**< Select APORT1Y CHannel 19 for the VA divider. */ - acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20, /**< Select APORT1X CHannel 20 for the VA divider. */ - acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21, /**< Select APORT1Y CHannel 21 for the VA divider. */ - acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22, /**< Select APORT1X CHannel 22 for the VA divider. */ - acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23, /**< Select APORT1Y CHannel 23 for the VA divider. */ - acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24, /**< Select APORT1X CHannel 24 for the VA divider. */ - acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25, /**< Select APORT1Y CHannel 25 for the VA divider. */ - acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26, /**< Select APORT1X CHannel 26 for the VA divider. */ - acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27, /**< Select APORT1Y CHannel 27 for the VA divider. */ - acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28, /**< Select APORT1X CHannel 28 for the VA divider. */ - acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29, /**< Select APORT1Y CHannel 29 for the VA divider. */ - acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30, /**< Select APORT1X CHannel 30 for the VA divider. */ - acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31 /**< Select APORT1Y CHannel 31 for the VA divider. */ -} ACMP_VAInput_TypeDef; -#endif - -#if defined(_ACMP_INPUTSEL_VBSEL_MASK) -/** - * ACMP input to the VB divider. This enumeration is used to select the input for - * the VB divider. - */ -typedef enum { - acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25, /**< Mode 1V25 for ACMP_INPUTSEL */ - acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5 /**< Mode 2V5 for ACMP_INPUTSEL */ -} ACMP_VBInput_TypeDef; -#endif - -#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) -/** - * ACMP Low-Power Input Selection. - */ -typedef enum { - acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV, /**< Mode VADIV for ACMP_INPUTSEL */ - acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV /**< Mode VBDIV for ACMP_INPUTSEL */ -} ACMP_VLPInput_Typedef; -#endif - -#if defined(_ACMP_INPUTCTRL_MASK) -/** ACMP Input Selection. */ -typedef enum { - acmpInputVSS = _ACMP_INPUTCTRL_POSSEL_VSS, /**< Select VSS. */ - acmpInputVREFDIVAVDD = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD, /**< Select Divided AVDD. */ - acmpInputVREFDIVAVDDLP = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP, /**< Select Low-Power Divided AVDD. */ - acmpInputVREFDIV1V25 = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25, /**< Select Divided 1V25 reference. */ - acmpInputVREFDIV1V25LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP, /**< Select Low-power Divided 1V25 reference. */ - acmpInputVREFDIV2V5 = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5, /**< Select Divided 2V5 reference. */ - acmpInputVREFDIV2V5LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP, /**< Select Low-power Divided 2V5 reference. */ - acmpInputVSENSE01DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4, /**< Select VSENSE0 divided by 4. */ - acmpInputVSENSE01DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP, /**< Select Low-power VSENSE0 divided by 4. */ - acmpInputVSENSE11DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4, /**< VSENSE1 divided by 4. */ - acmpInputVSENSE11DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP, /**< Low-power VSENSE1 divided by 4. */ - acmpInputCAPSENSE = _ACMP_INPUTCTRL_NEGSEL_CAPSENSE, /**< Select Low-Power Divided AVDD. */ -#if defined(_ACMP_INPUTCTRL_POSSEL_VDACOUT0) - acmpInputVDACOUT0 = _ACMP_INPUTCTRL_POSSEL_VDACOUT0, /**< Select VDAC0 channel 0 output. */ - acmpInputVDACOUT1 = _ACMP_INPUTCTRL_POSSEL_VDACOUT1, /**< Select VDAC0 channel 1 output. */ -#endif -#if defined(_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1) - acmpInputVDAC0OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1, /**< Select VDAC0 channel 1 output. */ - acmpInputVDAC1OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1, /**< Select VDAC1 channel 1 output. */ -#endif -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - acmpInputEXTPA = _ACMP_INPUTCTRL_POSSEL_EXTPA, /**< Select external interface, base is PA0. */ - acmpInputEXTPB = _ACMP_INPUTCTRL_POSSEL_EXTPB, /**< Select external interface, base is PB0. */ - acmpInputEXTPC = _ACMP_INPUTCTRL_POSSEL_EXTPC, /**< Select external interface, base is PC0. */ - acmpInputEXTPD = _ACMP_INPUTCTRL_POSSEL_EXTPD, /**< Select external interface, base is PD0. */ -#endif - acmpInputPA0 = _ACMP_INPUTCTRL_POSSEL_PA0, /**< Select Port A Pin0. */ - acmpInputPA1 = _ACMP_INPUTCTRL_POSSEL_PA1, /**< Select Port A Pin1. */ - acmpInputPA2 = _ACMP_INPUTCTRL_POSSEL_PA2, /**< Select Port A Pin2. */ - acmpInputPA3 = _ACMP_INPUTCTRL_POSSEL_PA3, /**< Select Port A Pin3. */ - acmpInputPA4 = _ACMP_INPUTCTRL_POSSEL_PA4, /**< Select Port A Pin4. */ - acmpInputPA5 = _ACMP_INPUTCTRL_POSSEL_PA5, /**< Select Port A Pin5. */ - acmpInputPA6 = _ACMP_INPUTCTRL_POSSEL_PA6, /**< Select Port A Pin6. */ - acmpInputPA7 = _ACMP_INPUTCTRL_POSSEL_PA7, /**< Select Port A Pin7. */ - acmpInputPA8 = _ACMP_INPUTCTRL_POSSEL_PA8, /**< Select Port A Pin8. */ - acmpInputPA9 = _ACMP_INPUTCTRL_POSSEL_PA9, /**< Select Port A Pin9. */ - acmpInputPA10 = _ACMP_INPUTCTRL_POSSEL_PA10, /**< Select Port A Pin10. */ - acmpInputPA11 = _ACMP_INPUTCTRL_POSSEL_PA11, /**< Select Port A Pin11. */ - acmpInputPA12 = _ACMP_INPUTCTRL_POSSEL_PA12, /**< Select Port A Pin12. */ - acmpInputPA13 = _ACMP_INPUTCTRL_POSSEL_PA13, /**< Select Port A Pin13. */ - acmpInputPA14 = _ACMP_INPUTCTRL_POSSEL_PA14, /**< Select Port A Pin14. */ - acmpInputPA15 = _ACMP_INPUTCTRL_POSSEL_PA15, /**< Select Port A Pin15. */ - acmpInputPB0 = _ACMP_INPUTCTRL_POSSEL_PB0, /**< Select Port B Pin0. */ - acmpInputPB1 = _ACMP_INPUTCTRL_POSSEL_PB1, /**< Select Port B Pin1. */ - acmpInputPB2 = _ACMP_INPUTCTRL_POSSEL_PB2, /**< Select Port B Pin2. */ - acmpInputPB3 = _ACMP_INPUTCTRL_POSSEL_PB3, /**< Select Port B Pin3. */ - acmpInputPB4 = _ACMP_INPUTCTRL_POSSEL_PB4, /**< Select Port B Pin4. */ - acmpInputPB5 = _ACMP_INPUTCTRL_POSSEL_PB5, /**< Select Port B Pin5. */ - acmpInputPB6 = _ACMP_INPUTCTRL_POSSEL_PB6, /**< Select Port B Pin6. */ - acmpInputPB7 = _ACMP_INPUTCTRL_POSSEL_PB7, /**< Select Port B Pin7. */ - acmpInputPB8 = _ACMP_INPUTCTRL_POSSEL_PB8, /**< Select Port B Pin8. */ - acmpInputPB9 = _ACMP_INPUTCTRL_POSSEL_PB9, /**< Select Port B Pin9. */ - acmpInputPB10 = _ACMP_INPUTCTRL_POSSEL_PB10, /**< Select Port B Pin10. */ - acmpInputPB11 = _ACMP_INPUTCTRL_POSSEL_PB11, /**< Select Port B Pin11. */ - acmpInputPB12 = _ACMP_INPUTCTRL_POSSEL_PB12, /**< Select Port B Pin12. */ - acmpInputPB13 = _ACMP_INPUTCTRL_POSSEL_PB13, /**< Select Port B Pin13. */ - acmpInputPB14 = _ACMP_INPUTCTRL_POSSEL_PB14, /**< Select Port B Pin14. */ - acmpInputPB15 = _ACMP_INPUTCTRL_POSSEL_PB15, /**< Select Port B Pin15. */ - acmpInputPC0 = _ACMP_INPUTCTRL_POSSEL_PC0, /**< Select Port C Pin0. */ - acmpInputPC1 = _ACMP_INPUTCTRL_POSSEL_PC1, /**< Select Port C Pin1. */ - acmpInputPC2 = _ACMP_INPUTCTRL_POSSEL_PC2, /**< Select Port C Pin2. */ - acmpInputPC3 = _ACMP_INPUTCTRL_POSSEL_PC3, /**< Select Port C Pin3. */ - acmpInputPC4 = _ACMP_INPUTCTRL_POSSEL_PC4, /**< Select Port C Pin4. */ - acmpInputPC5 = _ACMP_INPUTCTRL_POSSEL_PC5, /**< Select Port C Pin5. */ - acmpInputPC6 = _ACMP_INPUTCTRL_POSSEL_PC6, /**< Select Port C Pin6. */ - acmpInputPC7 = _ACMP_INPUTCTRL_POSSEL_PC7, /**< Select Port C Pin7. */ - acmpInputPC8 = _ACMP_INPUTCTRL_POSSEL_PC8, /**< Select Port C Pin8. */ - acmpInputPC9 = _ACMP_INPUTCTRL_POSSEL_PC9, /**< Select Port C Pin9. */ - acmpInputPC10 = _ACMP_INPUTCTRL_POSSEL_PC10, /**< Select Port C Pin10. */ - acmpInputPC11 = _ACMP_INPUTCTRL_POSSEL_PC11, /**< Select Port C Pin11. */ - acmpInputPC12 = _ACMP_INPUTCTRL_POSSEL_PC12, /**< Select Port C Pin12. */ - acmpInputPC13 = _ACMP_INPUTCTRL_POSSEL_PC13, /**< Select Port C Pin13. */ - acmpInputPC14 = _ACMP_INPUTCTRL_POSSEL_PC14, /**< Select Port C Pin14. */ - acmpInputPC15 = _ACMP_INPUTCTRL_POSSEL_PC15, /**< Select Port C Pin15. */ - acmpInputPD0 = _ACMP_INPUTCTRL_POSSEL_PD0, /**< Select Port D Pin0. */ - acmpInputPD1 = _ACMP_INPUTCTRL_POSSEL_PD1, /**< Select Port D Pin1. */ - acmpInputPD2 = _ACMP_INPUTCTRL_POSSEL_PD2, /**< Select Port D Pin2. */ - acmpInputPD3 = _ACMP_INPUTCTRL_POSSEL_PD3, /**< Select Port D Pin3. */ - acmpInputPD4 = _ACMP_INPUTCTRL_POSSEL_PD4, /**< Select Port D Pin4. */ - acmpInputPD5 = _ACMP_INPUTCTRL_POSSEL_PD5, /**< Select Port D Pin5. */ - acmpInputPD6 = _ACMP_INPUTCTRL_POSSEL_PD6, /**< Select Port D Pin6. */ - acmpInputPD7 = _ACMP_INPUTCTRL_POSSEL_PD7, /**< Select Port D Pin7. */ - acmpInputPD8 = _ACMP_INPUTCTRL_POSSEL_PD8, /**< Select Port D Pin8. */ - acmpInputPD9 = _ACMP_INPUTCTRL_POSSEL_PD9, /**< Select Port D Pin9. */ - acmpInputPD10 = _ACMP_INPUTCTRL_POSSEL_PD10, /**< Select Port D Pin10. */ - acmpInputPD11 = _ACMP_INPUTCTRL_POSSEL_PD11, /**< Select Port D Pin11. */ - acmpInputPD12 = _ACMP_INPUTCTRL_POSSEL_PD12, /**< Select Port D Pin12. */ - acmpInputPD13 = _ACMP_INPUTCTRL_POSSEL_PD13, /**< Select Port D Pin13. */ - acmpInputPD14 = _ACMP_INPUTCTRL_POSSEL_PD14, /**< Select Port D Pin14. */ - acmpInputPD15 = _ACMP_INPUTCTRL_POSSEL_PD15, /**< Select Port D Pin15. */ -} ACMP_Channel_TypeDef; -#elif defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) -/** ACMP Input Selection. */ -typedef enum { - acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0, /**< Select Dedicated APORT0X CHannel 0. */ - acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1, /**< Select Dedicated APORT0X CHannel 1. */ - acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2, /**< Select Dedicated APORT0X CHannel 2. */ - acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3, /**< Select Dedicated APORT0X CHannel 3. */ - acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4, /**< Select Dedicated APORT0X CHannel 4. */ - acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5, /**< Select Dedicated APORT0X CHannel 5. */ - acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6, /**< Select Dedicated APORT0X CHannel 6. */ - acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7, /**< Select Dedicated APORT0X CHannel 7. */ - acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8, /**< Select Dedicated APORT0X CHannel 8. */ - acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9, /**< Select Dedicated APORT0X CHannel 9. */ - acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10, /**< Select Dedicated APORT0X CHannel 10. */ - acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11, /**< Select Dedicated APORT0X CHannel 11. */ - acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12, /**< Select Dedicated APORT0X CHannel 12. */ - acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13, /**< Select Dedicated APORT0X CHannel 13. */ - acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14, /**< Select Dedicated APORT0X CHannel 14. */ - acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15, /**< Select Dedicated APORT0X CHannel 15. */ - acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0, /**< Select Dedicated APORT0Y CHannel 0. */ - acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1, /**< Select Dedicated APORT0Y CHannel 1. */ - acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2, /**< Select Dedicated APORT0Y CHannel 2. */ - acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3, /**< Select Dedicated APORT0Y CHannel 3. */ - acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4, /**< Select Dedicated APORT0Y CHannel 4. */ - acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5, /**< Select Dedicated APORT0Y CHannel 5. */ - acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6, /**< Select Dedicated APORT0Y CHannel 6. */ - acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7, /**< Select Dedicated APORT0Y CHannel 7. */ - acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8, /**< Select Dedicated APORT0Y CHannel 8. */ - acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9, /**< Select Dedicated APORT0Y CHannel 9. */ - acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10, /**< Select Dedicated APORT0Y CHannel 10. */ - acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11, /**< Select Dedicated APORT0Y CHannel 11. */ - acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12, /**< Select Dedicated APORT0Y CHannel 12. */ - acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13, /**< Select Dedicated APORT0Y CHannel 13. */ - acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14, /**< Select Dedicated APORT0Y CHannel 14. */ - acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15, /**< Select Dedicated APORT0Y CHannel 15. */ - acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0, /**< Select Dedicated APORT1X CHannel 0. */ - acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1, /**< Select Dedicated APORT1Y CHannel 1. */ - acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2, /**< Select Dedicated APORT1X CHannel 2. */ - acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3, /**< Select Dedicated APORT1Y CHannel 3. */ - acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4, /**< Select Dedicated APORT1X CHannel 4. */ - acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5, /**< Select Dedicated APORT1Y CHannel 5. */ - acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6, /**< Select Dedicated APORT1X CHannel 6. */ - acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7, /**< Select Dedicated APORT1Y CHannel 7. */ - acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8, /**< Select Dedicated APORT1X CHannel 8. */ - acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9, /**< Select Dedicated APORT1Y CHannel 9. */ - acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10, /**< Select Dedicated APORT1X CHannel 10. */ - acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11, /**< Select Dedicated APORT1Y CHannel 11. */ - acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12, /**< Select Dedicated APORT1X CHannel 12. */ - acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13, /**< Select Dedicated APORT1Y CHannel 13. */ - acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14, /**< Select Dedicated APORT1X CHannel 14. */ - acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15, /**< Select Dedicated APORT1Y CHannel 15. */ - acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16, /**< Select Dedicated APORT1X CHannel 16. */ - acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17, /**< Select Dedicated APORT1Y CHannel 17. */ - acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18, /**< Select Dedicated APORT1X CHannel 18. */ - acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19, /**< Select Dedicated APORT1Y CHannel 19. */ - acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20, /**< Select Dedicated APORT1X CHannel 20. */ - acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21, /**< Select Dedicated APORT1Y CHannel 21. */ - acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22, /**< Select Dedicated APORT1X CHannel 22. */ - acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23, /**< Select Dedicated APORT1Y CHannel 23. */ - acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24, /**< Select Dedicated APORT1X CHannel 24. */ - acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25, /**< Select Dedicated APORT1Y CHannel 25. */ - acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26, /**< Select Dedicated APORT1X CHannel 26. */ - acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27, /**< Select Dedicated APORT1Y CHannel 27. */ - acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28, /**< Select Dedicated APORT1X CHannel 28. */ - acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29, /**< Select Dedicated APORT1Y CHannel 29. */ - acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30, /**< Select Dedicated APORT1X CHannel 30. */ - acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31, /**< Select Dedicated APORT1Y CHannel 31. */ - acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0, /**< Select Dedicated APORT2Y CHannel 0. */ - acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1, /**< Select Dedicated APORT2X CHannel 1. */ - acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2, /**< Select Dedicated APORT2Y CHannel 2. */ - acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3, /**< Select Dedicated APORT2X CHannel 3. */ - acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4, /**< Select Dedicated APORT2Y CHannel 4. */ - acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5, /**< Select Dedicated APORT2X CHannel 5. */ - acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6, /**< Select Dedicated APORT2Y CHannel 6. */ - acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7, /**< Select Dedicated APORT2X CHannel 7. */ - acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8, /**< Select Dedicated APORT2Y CHannel 8. */ - acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9, /**< Select Dedicated APORT2X CHannel 9. */ - acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10, /**< Select Dedicated APORT2Y CHannel 10. */ - acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11, /**< Select Dedicated APORT2X CHannel 11. */ - acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12, /**< Select Dedicated APORT2Y CHannel 12. */ - acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13, /**< Select Dedicated APORT2X CHannel 13. */ - acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14, /**< Select Dedicated APORT2Y CHannel 14. */ - acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15, /**< Select Dedicated APORT2X CHannel 15. */ - acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16, /**< Select Dedicated APORT2Y CHannel 16. */ - acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17, /**< Select Dedicated APORT2X CHannel 17. */ - acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18, /**< Select Dedicated APORT2Y CHannel 18. */ - acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19, /**< Select Dedicated APORT2X CHannel 19. */ - acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20, /**< Select Dedicated APORT2Y CHannel 20. */ - acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21, /**< Select Dedicated APORT2X CHannel 21. */ - acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22, /**< Select Dedicated APORT2Y CHannel 22. */ - acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23, /**< Select Dedicated APORT2X CHannel 23. */ - acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24, /**< Select Dedicated APORT2Y CHannel 24. */ - acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25, /**< Select Dedicated APORT2X CHannel 25. */ - acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26, /**< Select Dedicated APORT2Y CHannel 26. */ - acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27, /**< Select Dedicated APORT2X CHannel 27. */ - acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28, /**< Select Dedicated APORT2Y CHannel 28. */ - acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29, /**< Select Dedicated APORT2X CHannel 29. */ - acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30, /**< Select Dedicated APORT2Y CHannel 30. */ - acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31, /**< Select Dedicated APORT2X CHannel 31. */ - acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0, /**< Select Dedicated APORT3X CHannel 0. */ - acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1, /**< Select Dedicated APORT3Y CHannel 1. */ - acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2, /**< Select Dedicated APORT3X CHannel 2. */ - acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3, /**< Select Dedicated APORT3Y CHannel 3. */ - acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4, /**< Select Dedicated APORT3X CHannel 4. */ - acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5, /**< Select Dedicated APORT3Y CHannel 5. */ - acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6, /**< Select Dedicated APORT3X CHannel 6. */ - acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7, /**< Select Dedicated APORT3Y CHannel 7. */ - acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8, /**< Select Dedicated APORT3X CHannel 8. */ - acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9, /**< Select Dedicated APORT3Y CHannel 9. */ - acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10, /**< Select Dedicated APORT3X CHannel 10. */ - acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11, /**< Select Dedicated APORT3Y CHannel 11. */ - acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12, /**< Select Dedicated APORT3X CHannel 12. */ - acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13, /**< Select Dedicated APORT3Y CHannel 13. */ - acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14, /**< Select Dedicated APORT3X CHannel 14. */ - acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15, /**< Select Dedicated APORT3Y CHannel 15. */ - acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16, /**< Select Dedicated APORT3X CHannel 16. */ - acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17, /**< Select Dedicated APORT3Y CHannel 17. */ - acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18, /**< Select Dedicated APORT3X CHannel 18. */ - acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19, /**< Select Dedicated APORT3Y CHannel 19. */ - acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20, /**< Select Dedicated APORT3X CHannel 20. */ - acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21, /**< Select Dedicated APORT3Y CHannel 21. */ - acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22, /**< Select Dedicated APORT3X CHannel 22. */ - acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23, /**< Select Dedicated APORT3Y CHannel 23. */ - acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24, /**< Select Dedicated APORT3X CHannel 24. */ - acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25, /**< Select Dedicated APORT3Y CHannel 25. */ - acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26, /**< Select Dedicated APORT3X CHannel 26. */ - acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27, /**< Select Dedicated APORT3Y CHannel 27. */ - acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28, /**< Select Dedicated APORT3X CHannel 28. */ - acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29, /**< Select Dedicated APORT3Y CHannel 29. */ - acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30, /**< Select Dedicated APORT3X CHannel 30. */ - acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31, /**< Select Dedicated APORT3Y CHannel 31. */ - acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0, /**< Select Dedicated APORT4Y CHannel 0. */ - acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1, /**< Select Dedicated APORT4X CHannel 1. */ - acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2, /**< Select Dedicated APORT4Y CHannel 2. */ - acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3, /**< Select Dedicated APORT4X CHannel 3. */ - acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4, /**< Select Dedicated APORT4Y CHannel 4. */ - acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5, /**< Select Dedicated APORT4X CHannel 5. */ - acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6, /**< Select Dedicated APORT4Y CHannel 6. */ - acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7, /**< Select Dedicated APORT4X CHannel 7. */ - acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8, /**< Select Dedicated APORT4Y CHannel 8. */ - acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9, /**< Select Dedicated APORT4X CHannel 9. */ - acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10, /**< Select Dedicated APORT4Y CHannel 10. */ - acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11, /**< Select Dedicated APORT4X CHannel 11. */ - acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12, /**< Select Dedicated APORT4Y CHannel 12. */ - acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13, /**< Select Dedicated APORT4X CHannel 13. */ - acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16, /**< Select Dedicated APORT4Y CHannel 14. */ - acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17, /**< Select Dedicated APORT4X CHannel 15. */ - acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18, /**< Select Dedicated APORT4Y CHannel 16. */ - acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19, /**< Select Dedicated APORT4X CHannel 17. */ - acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20, /**< Select Dedicated APORT4Y CHannel 18. */ - acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21, /**< Select Dedicated APORT4X CHannel 19. */ - acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22, /**< Select Dedicated APORT4Y CHannel 20. */ - acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23, /**< Select Dedicated APORT4X CHannel 21. */ - acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24, /**< Select Dedicated APORT4Y CHannel 22. */ - acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25, /**< Select Dedicated APORT4X CHannel 23. */ - acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26, /**< Select Dedicated APORT4Y CHannel 24. */ - acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27, /**< Select Dedicated APORT4X CHannel 25. */ - acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28, /**< Select Dedicated APORT4Y CHannel 26. */ - acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29, /**< Select Dedicated APORT4X CHannel 27. */ - acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30, /**< Select Dedicated APORT4Y CHannel 28. */ - acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, /**< Select Dedicated APORT4X CHannel 29. */ - acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, /**< Select Dedicated APORT4Y CHannel 30. */ - acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, /**< Select Dedicated APORT4X CHannel 31. */ -#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) - acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, /**< Select DAC Channel 0 Output. */ -#endif -#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) - acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, /**< Select DAC Channel 1 Output. */ -#endif - acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, /**< Select Low-Power Sampled Voltage. */ - acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, /**< Select Divided VB Voltage. */ - acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, /**< Select Divided VA Voltage. */ - acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD, /**< ACMPVDD as selected via PWRSEL. */ - acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS, /**< Select VSS. */ -} ACMP_Channel_TypeDef; -#else -/** ACMP inputs. Note that scaled VDD and bandgap references can only be used - * as negative inputs. */ -typedef enum { - /** Channel 0 */ - acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0, - /** Channel 1 */ - acmpChannel1 = _ACMP_INPUTSEL_NEGSEL_CH1, - /** Channel 2 */ - acmpChannel2 = _ACMP_INPUTSEL_NEGSEL_CH2, - /** Channel 3 */ - acmpChannel3 = _ACMP_INPUTSEL_NEGSEL_CH3, - /** Channel 4 */ - acmpChannel4 = _ACMP_INPUTSEL_NEGSEL_CH4, - /** Channel 5 */ - acmpChannel5 = _ACMP_INPUTSEL_NEGSEL_CH5, - /** Channel 6 */ - acmpChannel6 = _ACMP_INPUTSEL_NEGSEL_CH6, - /** Channel 7 */ - acmpChannel7 = _ACMP_INPUTSEL_NEGSEL_CH7, - /** 1.25 V internal reference */ - acmpChannel1V25 = _ACMP_INPUTSEL_NEGSEL_1V25, - /** 2.5 V internal reference */ - acmpChannel2V5 = _ACMP_INPUTSEL_NEGSEL_2V5, - /** Scaled VDD reference */ - acmpChannelVDD = _ACMP_INPUTSEL_NEGSEL_VDD, - -#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH0) - /** DAC0 channel 0 */ - acmpChannelDAC0Ch0 = _ACMP_INPUTSEL_NEGSEL_DAC0CH0, -#endif - -#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) - /** DAC0 channel 1 */ - acmpChannelDAC0Ch1 = _ACMP_INPUTSEL_NEGSEL_DAC0CH1, -#endif - -#if defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) - /** Capacitive sense mode */ - acmpChannelCapSense = _ACMP_INPUTSEL_NEGSEL_CAPSENSE, -#endif -} ACMP_Channel_TypeDef; -#endif - -#if defined(_ACMP_EXTIFCTRL_MASK) -/** - * ACMP external input select. This type is used to select which APORT is - * used by an external module, such as LESENSE, when it's taking control over - * the ACMP input. - */ -typedef enum { - acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, /**< Select APORT0X as an external input. */ - acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, /**< Select APORT0Y as an external input. */ - acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, /**< Select APORT1X as an external input. */ - acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, /**< Select APORT1Y as an external input. */ - acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, /**< Select APORT1XY as an external input. */ - acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, /**< Select APORT2X as an external input. */ - acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, /**< Select APORT2Y as an external input. */ - acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, /**< Select APORT2YX as an external input. */ - acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, /**< Select APORT3X as an external input. */ - acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, /**< Select APORT3Y as an external input. */ - acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, /**< Select APORT3XY as an external input. */ - acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, /**< Select APORT4X as an external input. */ - acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, /**< Select APORT4Y as an external input. */ - acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, /**< Select APORT4YX as an external input. */ -} ACMP_ExternalInput_Typedef; -#endif - -/******************************************************************************* - ****************************** STRUCTS ************************************ - ******************************************************************************/ - -/** Capsense initialization structure. */ -typedef struct { -#if defined(_ACMP_CTRL_FULLBIAS_MASK) - /** Full-bias current. See the ACMP chapter about bias and response time in - * the reference manual for details. */ - bool fullBias; -#endif - -#if defined(_ACMP_CTRL_HALFBIAS_MASK) - /** Half-bias current. See the ACMP chapter about bias and response time in - * the reference manual for details. */ - bool halfBias; -#endif - - /** Bias current. See the ACMP chapter about bias and response time in the - * reference manual for details. */ - uint32_t biasProg; - -#if defined(_ACMP_CTRL_WARMTIME_MASK) - /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be - * about 10 us in wall clock time. */ - ACMP_WarmTime_TypeDef warmTime; -#endif - -#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ - || defined(_ACMP_CFG_HYST_MASK) - /** Hysteresis level. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel; -#else - /** Hysteresis level when ACMP output is 0. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; - - /** Hysteresis level when ACMP output is 1. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; -#endif - - /** A resistor used in the capacitive sensing circuit. For values see - * the device data sheet. */ - ACMP_CapsenseResistor_TypeDef resistor; - -#if defined(_ACMP_INPUTSEL_LPREF_MASK) - /** Low-power reference enabled. This setting, if enabled, reduces the - * power used by VDD and bandgap references. */ - bool lowPowerReferenceEnabled; -#endif - -#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) - /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). - * Valid values are in the 0-63 range. */ - uint32_t vrefDiv; -#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) - /** VDD reference value. VDD_SCALED = (VDD * VDDLEVEL) / 63. - * Valid values are in the 0-63 range. */ - uint32_t vddLevel; -#else - /** - * This value configures the upper voltage threshold of the capsense - * oscillation rail. - * - * The voltage threshold is calculated as follows: - * VDD * (vddLevelHigh + 1) / 64 - */ - uint32_t vddLevelHigh; - - /** - * This value configures the lower voltage threshold of the capsense - * oscillation rail. - * - * The voltage threshold is calculated as follows: - * VDD * (vddLevelLow + 1) / 64 - */ - uint32_t vddLevelLow; -#endif - - /** If true, ACMP is enabled after configuration. */ - bool enable; -} ACMP_CapsenseInit_TypeDef; - -/** A default configuration for capacitive sense mode initialization. */ -#if defined(_ACMP_CFG_MASK) - -// PM5507: provide default configuration that is functional -/** Analog comparator CFG with initial bias value */ -#define PM5507_ACMP_CFG_BIAS_DEFAULT 0x00000004UL -/** Analog comparator reset value */ -#define PM5507_ACMP_CFG_RESETVALUE 0x00000004UL - -/** Capacitive sense mode configuration default values. */ -#define ACMP_CAPSENSE_INIT_DEFAULT \ - { \ - PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ - acmpHysteresisDisabled, /* Disable hysteresis. */ \ - acmpResistor5, /* Use internal resistor value 5. */ \ - 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ - true /* Enable after init. */ \ - } -#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) -#define ACMP_CAPSENSE_INIT_DEFAULT \ - { \ - false, /* Don't use fullBias to lower power consumption. */ \ - 0x20, /* Using biasProg value of 0x20 (32). */ \ - acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0. */ \ - acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1. */ \ - acmpResistor5, /* Use internal resistor value 5. */ \ - 0x30, /* VDD level high. */ \ - 0x10, /* VDD level low. */ \ - true /* Enable after initialization. */ \ - } -#elif defined(_ACMP_CTRL_WARMTIME_MASK) -#define ACMP_CAPSENSE_INIT_DEFAULT \ - { \ - false, /* fullBias */ \ - false, /* halfBias */ \ - 0x7, /* biasProg */ \ - acmpWarmTime512, /* 512 cycle warmup to be safe */ \ - acmpHysteresisLevel5, \ - acmpResistor3, \ - false, /* low power reference */ \ - 0x3D, /* VDD level */ \ - true /* Enable after init. */ \ - } -#else -#define ACMP_CAPSENSE_INIT_DEFAULT \ - { \ - false, /* fullBias */ \ - false, /* halfBias */ \ - 0x7, /* biasProg */ \ - acmpHysteresisLevel5, \ - acmpResistor3, \ - false, /* low power reference */ \ - 0x3D, /* VDD level */ \ - true /* Enable after init. */ \ - } -#endif - -/** ACMP initialization structure. */ -typedef struct { -#if defined(_ACMP_CTRL_FULLBIAS_MASK) - /** Full-bias current. See the ACMP chapter about bias and response time in - * the reference manual for details. */ - bool fullBias; -#endif - -#if defined(_ACMP_CTRL_HALFBIAS_MASK) - /** Half-bias current. See the ACMP chapter about bias and response time in - * the reference manual for details. */ - bool halfBias; -#endif - - /** Bias current. See the ACMP chapter about bias and response time in the - * reference manual for details. Valid values are in the range 0-7. */ - uint32_t biasProg; - -#if defined(_ACMP_CTRL_IFALL_SHIFT) - /** Enable setting the interrupt flag on the falling edge. */ - bool interruptOnFallingEdge; -#endif -#if defined(_ACMP_CTRL_IRISE_SHIFT) - /** Enable setting the interrupt flag on the rising edge. */ - bool interruptOnRisingEdge; -#endif - -#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ - || defined(_ACMP_CFG_INPUTRANGE_MASK) - /** Input range. Adjust this setting to optimize the performance for a - * given input voltage range. */ - ACMP_InputRange_TypeDef inputRange; -#endif - -#if defined(_ACMP_CTRL_ACCURACY_MASK) \ - || defined(_ACMP_CFG_ACCURACY_MASK) - /** ACMP accuracy mode. Select the accuracy mode that matches the - * required current usage and accuracy requirement. Low accuracy - * consumes less current while high accuracy consumes more current. */ - ACMP_Accuracy_TypeDef accuracy; -#endif - -#if defined(_ACMP_CTRL_PWRSEL_MASK) - /** Select the power source for the ACMP. */ - ACMP_PowerSource_TypeDef powerSource; -#endif - -#if defined(_ACMP_CTRL_WARMTIME_MASK) - /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be - * about 10 us in wall clock time. */ - ACMP_WarmTime_TypeDef warmTime; -#endif - -#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ - || defined(_ACMP_CFG_HYST_MASK) - /** Hysteresis level. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel; -#else - /** Hysteresis when ACMP output is 0. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; - - /** Hysteresis when ACMP output is 1. */ - ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; -#endif - -#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) - /** VLP Input source. Select between using VADIV or VBDIV as the VLP - * source. */ - ACMP_VLPInput_Typedef vlpInput; -#endif - - /** Inactive value emitted by ACMP during warmup. */ - bool inactiveValue; - -#if defined(_ACMP_INPUTSEL_LPREF_MASK) - /** Low power reference enabled. This setting, if enabled, reduces the - * power used by the VDD and bandgap references. */ - bool lowPowerReferenceEnabled; -#endif - -#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) - /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). - * Valid values are in the 0-63 range. */ - uint32_t vrefDiv; -#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) - /** VDD reference value. VDD_SCALED = VDD * VDDLEVEL * 50 mV/3.8 V. - * Valid values are in the 0-63 range. */ - uint32_t vddLevel; -#endif - - /** If true, ACMP is enabled after configuration. */ - bool enable; -} ACMP_Init_TypeDef; - -/** Default configuration for ACMP regular initialization. */ -#if defined(_ACMP_CFG_MASK) -#define ACMP_INIT_DEFAULT \ - { \ - PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ - acmpInputRangeFull, /* Input range from 0 to Vdd. */ \ - acmpAccuracyLow, /* Low accuracy, less current usage. */ \ - acmpHysteresisDisabled, /* Disable hysteresis. */ \ - false, /* Output 0 when ACMP is inactive. */ \ - 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ - true /* Enable after init. */ \ - } -#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) -#define ACMP_INIT_DEFAULT \ - { \ - false, /* fullBias */ \ - 0x7, /* biasProg */ \ - false, /* No interrupt on falling edge. */ \ - false, /* No interrupt on rising edge. */ \ - acmpInputRangeFull, /* Input range from 0 to VDD. */ \ - acmpAccuracyLow, /* Low accuracy, less current usage. */ \ - acmpPowerSourceAvdd, /* Use the AVDD supply. */ \ - acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \ - acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \ - acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \ - false, /* Output 0 when ACMP is inactive. */ \ - true /* Enable after init. */ \ - } -#else -#define ACMP_INIT_DEFAULT \ - { \ - false, /* fullBias */ \ - false, /* halfBias */ \ - 0x7, /* biasProg */ \ - false, /* No interrupt on falling edge. */ \ - false, /* No interrupt on rising edge. */ \ - acmpWarmTime512, /* 512 cycle warmup to be safe */ \ - acmpHysteresisLevel5, \ - false, /* Disabled emitting inactive value during warmup. */ \ - false, /* low power reference */ \ - 0x3D, /* VDD level */ \ - true /* Enable after init. */ \ - } -#endif - -#if defined(_ACMP_INPUTSEL_VASEL_MASK) -/** VA Configuration structure. This structure is used to configure the - * VA voltage input source and its dividers. */ -typedef struct { - ACMP_VAInput_TypeDef input; /**< VA voltage input source */ - - /** - * A divider for VA voltage input source when ACMP output is 0. This value is - * used to divide the VA voltage input source by a specific value. The valid - * range is between 0 and 63. - * - * VA divided = VA input * (div0 + 1) / 64 - */ - uint32_t div0; - - /** - * A divider for VA voltage input source when ACMP output is 1. This value is - * used to divide the VA voltage input source by a specific value. The valid - * range is between 0 and 63. - * - * VA divided = VA input * (div1 + 1) / 64 - */ - uint32_t div1; -} ACMP_VAConfig_TypeDef; - -/** VA default configuration. */ -#define ACMP_VACONFIG_DEFAULT \ - { \ - acmpVAInputVDD, /* Use VDD as VA voltage input source. */ \ - 63, /* No division of the VA source when ACMP output is 0. */ \ - 63, /* No division of the VA source when ACMP output is 1. */ \ - } -#endif - -#if defined(_ACMP_INPUTSEL_VBSEL_MASK) -/** VB Configuration structure. This structure is used to configure the - * VB voltage input source and its dividers. */ -typedef struct { - ACMP_VBInput_TypeDef input; /**< VB Voltage input source */ - - /** - * A divider for VB voltage input source when ACMP output is 0. This value is - * used to divide the VB voltage input source by a specific value. The valid - * range is between 0 and 63. - * - * VB divided = VB input * (div0 + 1) / 64 - */ - uint32_t div0; - - /** - * A divider for VB voltage input source when ACMP output is 1. This value is - * used to divide the VB voltage input source by a specific value. The valid - * range is between 0 and 63. - * - * VB divided = VB input * (div1 + 1) / 64 - */ - uint32_t div1; -} ACMP_VBConfig_TypeDef; - -/** VB default configuration. */ -#define ACMP_VBCONFIG_DEFAULT \ - { \ - acmpVBInput1V25, /* Use 1.25 V as VB voltage input source. */ \ - 63, /* No division of the VB source when ACMP output is 0. */ \ - 63, /* No division of the VB source when ACMP output is 1. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init); -void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); -void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); -void ACMP_Disable(ACMP_TypeDef *acmp); -void ACMP_Enable(ACMP_TypeDef *acmp); -#if defined(_ACMP_EXTIFCTRL_MASK) -void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); -#endif -#if defined(_GPIO_ACMP_ROUTEEN_MASK) -void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, unsigned int pin, bool enable, bool invert); -#else -void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); -#endif -void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); -void ACMP_Reset(ACMP_TypeDef *acmp); -#if defined(_ACMP_INPUTSEL_VASEL_MASK) -void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig); -#endif -#if defined(_ACMP_INPUTSEL_VBSEL_MASK) -void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig); -#endif - -/***************************************************************************//** - * @brief - * Clear one or more pending ACMP interrupts. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] flags - * Pending ACMP interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the ACMP module. The flags can be, for instance, - * ACMP_IFC_EDGE or ACMP_IFC_WARMUP. - ******************************************************************************/ -__STATIC_INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags) -{ -#if defined(ACMP_HAS_SET_CLEAR) - acmp->IF_CLR = flags; -#else - acmp->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more ACMP interrupts. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] flags - * ACMP interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the ACMP module. The flags can be, for instance, - * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. - ******************************************************************************/ -__STATIC_INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags) -{ - BUS_RegMaskedClear(&(acmp->IEN), flags); -} - -/***************************************************************************//** - * @brief - * Enable one or more ACMP interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using ACMP_IntClear() prior to enabling - * if a pending interrupt should be ignored. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] flags - * ACMP interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the ACMP module. The flags can be, for instance, - * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. - ******************************************************************************/ -__STATIC_INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags) -{ -#if defined(ACMP_HAS_SET_CLEAR) - acmp->IEN_SET = flags; -#else - acmp->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending ACMP interrupt flags. - * - * @note - * This function does not clear event bits. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @return - * Pending ACMP interrupt sources. A bitwise logic OR combination of valid - * interrupt flags for the ACMP module. The pending interrupt sources can be, - * for instance, ACMP_IF_EDGE or ACMP_IF_WARMUP. - ******************************************************************************/ -__STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp) -{ - return acmp->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending ACMP interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @note - * This function does not clear interrupt flags. - * - * @return - * Pending and enabled ACMP interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in ACMPx_IEN_nnn - * register (ACMPx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the ACMP module - * (ACMPx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp) -{ - uint32_t tmp; - - /* Store ACMPx->IEN in a temporary variable to define the explicit order - * of volatile accesses. */ - tmp = acmp->IEN; - - /* Bitwise AND of pending and enabled interrupts. */ - return acmp->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending ACMP interrupts from software. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] flags - * ACMP interrupt sources to set as pending. Use a bitwise logic OR - * combination of valid interrupt flags for the ACMP module. The flags can be, - * for instance, ACMP_IFS_EDGE or ACMP_IFS_WARMUP. - ******************************************************************************/ -__STATIC_INLINE void ACMP_IntSet(ACMP_TypeDef *acmp, uint32_t flags) -{ -#if defined(ACMP_HAS_SET_CLEAR) - acmp->IF_SET = flags; -#else - acmp->IFS = flags; -#endif -} - -#if defined(_ACMP_INPUTCTRL_MASK) -/***************************************************************************//** - * @brief - * Convert GPIO port/pin to ACMP input selection. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO pin - * - * @return - * ACMP input selection - ******************************************************************************/ -__STATIC_INLINE ACMP_Channel_TypeDef ACMP_PortPinToInput(GPIO_Port_TypeDef port, uint8_t pin) -{ - uint32_t input = (((uint32_t) port + (_ACMP_INPUTCTRL_POSSEL_PA0 >> 4)) << 4) | pin; - - return (ACMP_Channel_TypeDef) input; -} -#endif - -/** @} (end addtogroup acmp) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ -#endif /* EM_ACMP_H */ +/***************************************************************************//** + * @file + * @brief Analog Comparator (ACMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_ACMP_H +#define EM_ACMP_H + +#include "em_device.h" +#include "em_gpio.h" + +#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup acmp + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Resistor values used for the internal capacitive sense resistor. See + * data sheet for your device for details on each resistor value. */ +typedef enum { +#if defined(_ACMP_INPUTCTRL_CSRESSEL_MASK) + acmpResistor0 = _ACMP_INPUTCTRL_CSRESSEL_RES0, /**< Resistor value 0 */ + acmpResistor1 = _ACMP_INPUTCTRL_CSRESSEL_RES1, /**< Resistor value 1 */ + acmpResistor2 = _ACMP_INPUTCTRL_CSRESSEL_RES2, /**< Resistor value 2 */ + acmpResistor3 = _ACMP_INPUTCTRL_CSRESSEL_RES3, /**< Resistor value 3 */ + acmpResistor4 = _ACMP_INPUTCTRL_CSRESSEL_RES4, /**< Resistor value 4 */ + acmpResistor5 = _ACMP_INPUTCTRL_CSRESSEL_RES5, /**< Resistor value 5 */ + acmpResistor6 = _ACMP_INPUTCTRL_CSRESSEL_RES6, /**< Resistor value 6 */ +#else + acmpResistor0 = _ACMP_INPUTSEL_CSRESSEL_RES0, /**< Resistor value 0 */ + acmpResistor1 = _ACMP_INPUTSEL_CSRESSEL_RES1, /**< Resistor value 1 */ + acmpResistor2 = _ACMP_INPUTSEL_CSRESSEL_RES2, /**< Resistor value 2 */ + acmpResistor3 = _ACMP_INPUTSEL_CSRESSEL_RES3, /**< Resistor value 3 */ +#if defined(_ACMP_INPUTSEL_CSRESSEL_RES4) + acmpResistor4 = _ACMP_INPUTSEL_CSRESSEL_RES4, /**< Resistor value 4 */ + acmpResistor5 = _ACMP_INPUTSEL_CSRESSEL_RES5, /**< Resistor value 5 */ + acmpResistor6 = _ACMP_INPUTSEL_CSRESSEL_RES6, /**< Resistor value 6 */ + acmpResistor7 = _ACMP_INPUTSEL_CSRESSEL_RES7, /**< Resistor value 7 */ +#endif +#endif +} ACMP_CapsenseResistor_TypeDef; + +/** Hysteresis level. See data sheet for your device for details on each + * level. */ +typedef enum { +#if defined(_ACMP_CTRL_HYSTSEL_MASK) + acmpHysteresisLevel0 = _ACMP_CTRL_HYSTSEL_HYST0, /**< Hysteresis level 0 */ + acmpHysteresisLevel1 = _ACMP_CTRL_HYSTSEL_HYST1, /**< Hysteresis level 1 */ + acmpHysteresisLevel2 = _ACMP_CTRL_HYSTSEL_HYST2, /**< Hysteresis level 2 */ + acmpHysteresisLevel3 = _ACMP_CTRL_HYSTSEL_HYST3, /**< Hysteresis level 3 */ + acmpHysteresisLevel4 = _ACMP_CTRL_HYSTSEL_HYST4, /**< Hysteresis level 4 */ + acmpHysteresisLevel5 = _ACMP_CTRL_HYSTSEL_HYST5, /**< Hysteresis level 5 */ + acmpHysteresisLevel6 = _ACMP_CTRL_HYSTSEL_HYST6, /**< Hysteresis level 6 */ + acmpHysteresisLevel7 = _ACMP_CTRL_HYSTSEL_HYST7 /**< Hysteresis level 7 */ +#endif +#if defined(_ACMP_HYSTERESIS0_HYST_MASK) + acmpHysteresisLevel0 = _ACMP_HYSTERESIS0_HYST_HYST0, /**< Hysteresis level 0 */ + acmpHysteresisLevel1 = _ACMP_HYSTERESIS0_HYST_HYST1, /**< Hysteresis level 1 */ + acmpHysteresisLevel2 = _ACMP_HYSTERESIS0_HYST_HYST2, /**< Hysteresis level 2 */ + acmpHysteresisLevel3 = _ACMP_HYSTERESIS0_HYST_HYST3, /**< Hysteresis level 3 */ + acmpHysteresisLevel4 = _ACMP_HYSTERESIS0_HYST_HYST4, /**< Hysteresis level 4 */ + acmpHysteresisLevel5 = _ACMP_HYSTERESIS0_HYST_HYST5, /**< Hysteresis level 5 */ + acmpHysteresisLevel6 = _ACMP_HYSTERESIS0_HYST_HYST6, /**< Hysteresis level 6 */ + acmpHysteresisLevel7 = _ACMP_HYSTERESIS0_HYST_HYST7, /**< Hysteresis level 7 */ + acmpHysteresisLevel8 = _ACMP_HYSTERESIS0_HYST_HYST8, /**< Hysteresis level 8 */ + acmpHysteresisLevel9 = _ACMP_HYSTERESIS0_HYST_HYST9, /**< Hysteresis level 9 */ + acmpHysteresisLevel10 = _ACMP_HYSTERESIS0_HYST_HYST10, /**< Hysteresis level 10 */ + acmpHysteresisLevel11 = _ACMP_HYSTERESIS0_HYST_HYST11, /**< Hysteresis level 11 */ + acmpHysteresisLevel12 = _ACMP_HYSTERESIS0_HYST_HYST12, /**< Hysteresis level 12 */ + acmpHysteresisLevel13 = _ACMP_HYSTERESIS0_HYST_HYST13, /**< Hysteresis level 13 */ + acmpHysteresisLevel14 = _ACMP_HYSTERESIS0_HYST_HYST14, /**< Hysteresis level 14 */ + acmpHysteresisLevel15 = _ACMP_HYSTERESIS0_HYST_HYST15, /**< Hysteresis level 15 */ +#endif +#if defined(_ACMP_CFG_HYST_MASK) + acmpHysteresisDisabled = _ACMP_CFG_HYST_DISABLED, /**< Mode DISABLED for ACMP_CFG */ + acmpHysteresis10Sym = _ACMP_CFG_HYST_SYM10MV, /**< Mode HYST10SYM for ACMP_CFG */ + acmpHysteresis20Sym = _ACMP_CFG_HYST_SYM20MV, /**< Mode HYST20SYM for ACMP_CFG */ + acmpHysteresis30Sym = _ACMP_CFG_HYST_SYM30MV, /**< Mode HYST30SYM for ACMP_CFG */ + acmpHysteresis10Pos = _ACMP_CFG_HYST_POS10MV, /**< Mode HYST10POS for ACMP_CFG */ + acmpHysteresis20Pos = _ACMP_CFG_HYST_POS20MV, /**< Mode HYST20POS for ACMP_CFG */ + acmpHysteresis30Pos = _ACMP_CFG_HYST_POS30MV, /**< Mode HYST30POS for ACMP_CFG */ + acmpHysteresis10Neg = _ACMP_CFG_HYST_NEG10MV, /**< Mode HYST10NEG for ACMP_CFG */ + acmpHysteresis20Neg = _ACMP_CFG_HYST_NEG20MV, /**< Mode HYST20NEG for ACMP_CFG */ + acmpHysteresis30Neg = _ACMP_CFG_HYST_NEG30MV, /**< Mode HYST30NEG for ACMP_CFG */ +#endif +} ACMP_HysteresisLevel_TypeDef; + +#if defined(_ACMP_CTRL_WARMTIME_MASK) +/** ACMP warmup time. The delay is measured in HFPERCLK / HFPERCCLK cycles and should + * be at least 10 us. */ +typedef enum { + /** 4 cycles warmup */ + acmpWarmTime4 = _ACMP_CTRL_WARMTIME_4CYCLES, + /** 8 cycles warmup */ + acmpWarmTime8 = _ACMP_CTRL_WARMTIME_8CYCLES, + /** 16 cycles warmup */ + acmpWarmTime16 = _ACMP_CTRL_WARMTIME_16CYCLES, + /** 32 cycles warmup */ + acmpWarmTime32 = _ACMP_CTRL_WARMTIME_32CYCLES, + /** 64 cycles warmup */ + acmpWarmTime64 = _ACMP_CTRL_WARMTIME_64CYCLES, + /** 128 cycles warmup */ + acmpWarmTime128 = _ACMP_CTRL_WARMTIME_128CYCLES, + /** 256 cycles warmup */ + acmpWarmTime256 = _ACMP_CTRL_WARMTIME_256CYCLES, + /** 512 cycles warmup */ + acmpWarmTime512 = _ACMP_CTRL_WARMTIME_512CYCLES +} ACMP_WarmTime_TypeDef; +#endif + +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ + || defined(_ACMP_CFG_INPUTRANGE_MASK) +/** + * Adjust ACMP performance for a given input voltage range. + */ +typedef enum { +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) + acmpInputRangeFull = _ACMP_CTRL_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ + acmpInputRangeHigh = _ACMP_CTRL_INPUTRANGE_GTVDDDIV2, /**< Input will always be greater than VDD/2. */ + acmpInputRangeLow = _ACMP_CTRL_INPUTRANGE_LTVDDDIV2 /**< Input will always be less than VDD/2. */ +#elif defined(_ACMP_CFG_INPUTRANGE_MASK) + acmpInputRangeFull = _ACMP_CFG_INPUTRANGE_FULL, /**< Input can be from 0 to VDD. */ + acmpInputRangeReduced = _ACMP_CFG_INPUTRANGE_REDUCED, /**< Input can be from 0 to VDD-0.7 V. */ +#endif +} ACMP_InputRange_TypeDef; +#endif + +#if defined(_ACMP_CTRL_PWRSEL_MASK) +/** + * ACMP Power source. + */ +typedef enum { + acmpPowerSourceAvdd = _ACMP_CTRL_PWRSEL_AVDD, /**< Power ACMP using the AVDD supply. */ +#if defined(_ACMP_CTRL_PWRSEL_DVDD) + acmpPowerSourceDvdd = _ACMP_CTRL_PWRSEL_DVDD, /**< Power ACMP using the DVDD supply. */ +#endif + acmpPowerSourceIOVdd0 = _ACMP_CTRL_PWRSEL_IOVDD0, /**< Power ACMP using the IOVDD/IOVDD0 supply. */ + acmpPowerSourceIOVdd1 = _ACMP_CTRL_PWRSEL_IOVDD1, /**< Power ACMP using the IOVDD1 supply (if the part has two I/O voltages). */ +} ACMP_PowerSource_TypeDef; +#endif + +#if defined(_ACMP_CTRL_ACCURACY_MASK) \ + || defined(_ACMP_CFG_ACCURACY_MASK) +/** + * ACMP accuracy mode. + */ +typedef enum { +#if defined(_ACMP_CTRL_ACCURACY_MASK) + acmpAccuracyLow = _ACMP_CTRL_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ + acmpAccuracyHigh = _ACMP_CTRL_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ +#elif defined(_ACMP_CFG_ACCURACY_MASK) + acmpAccuracyLow = _ACMP_CFG_ACCURACY_LOW, /**< Low-accuracy mode which consumes less current. */ + acmpAccuracyHigh = _ACMP_CFG_ACCURACY_HIGH /**< High-accuracy mode which consumes more current. */ +#endif +} ACMP_Accuracy_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/** ACMP input to the VA divider. This enumeration is used to select the input for + * the VA Divider. */ +typedef enum { + acmpVAInputVDD = _ACMP_INPUTSEL_VASEL_VDD, /**< Select VDD for the VA divider. */ + acmpVAInputAPORT2YCH0 = _ACMP_INPUTSEL_VASEL_APORT2YCH0, /**< Select APORT2Y CHannel 0 for the VA divider. */ + acmpVAInputAPORT2YCH2 = _ACMP_INPUTSEL_VASEL_APORT2YCH2, /**< Select APORT2Y CHannel 2 for the VA divider. */ + acmpVAInputAPORT2YCH4 = _ACMP_INPUTSEL_VASEL_APORT2YCH4, /**< Select APORT2Y CHannel 4 for the VA divider. */ + acmpVAInputAPORT2YCH6 = _ACMP_INPUTSEL_VASEL_APORT2YCH6, /**< Select APORT2Y CHannel 6 for the VA divider. */ + acmpVAInputAPORT2YCH8 = _ACMP_INPUTSEL_VASEL_APORT2YCH8, /**< Select APORT2Y CHannel 8 for the VA divider. */ + acmpVAInputAPORT2YCH10 = _ACMP_INPUTSEL_VASEL_APORT2YCH10, /**< Select APORT2Y CHannel 10 for the VA divider. */ + acmpVAInputAPORT2YCH12 = _ACMP_INPUTSEL_VASEL_APORT2YCH12, /**< Select APORT2Y CHannel 12 for the VA divider. */ + acmpVAInputAPORT2YCH14 = _ACMP_INPUTSEL_VASEL_APORT2YCH14, /**< Select APORT2Y CHannel 14 for the VA divider. */ + acmpVAInputAPORT2YCH16 = _ACMP_INPUTSEL_VASEL_APORT2YCH16, /**< Select APORT2Y CHannel 16 for the VA divider. */ + acmpVAInputAPORT2YCH18 = _ACMP_INPUTSEL_VASEL_APORT2YCH18, /**< Select APORT2Y CHannel 18 for the VA divider. */ + acmpVAInputAPORT2YCH20 = _ACMP_INPUTSEL_VASEL_APORT2YCH20, /**< Select APORT2Y CHannel 20 for the VA divider. */ + acmpVAInputAPORT2YCH22 = _ACMP_INPUTSEL_VASEL_APORT2YCH22, /**< Select APORT2Y CHannel 22 for the VA divider. */ + acmpVAInputAPORT2YCH24 = _ACMP_INPUTSEL_VASEL_APORT2YCH24, /**< Select APORT2Y CHannel 24 for the VA divider. */ + acmpVAInputAPORT2YCH26 = _ACMP_INPUTSEL_VASEL_APORT2YCH26, /**< Select APORT2Y CHannel 26 for the VA divider. */ + acmpVAInputAPORT2YCH28 = _ACMP_INPUTSEL_VASEL_APORT2YCH28, /**< Select APORT2Y CHannel 28 for the VA divider. */ + acmpVAInputAPORT2YCH30 = _ACMP_INPUTSEL_VASEL_APORT2YCH30, /**< Select APORT2Y CHannel 30 for the VA divider. */ + acmpVAInputAPORT1XCH0 = _ACMP_INPUTSEL_VASEL_APORT1XCH0, /**< Select APORT1X CHannel 0 for the VA divider. */ + acmpVAInputAPORT1YCH1 = _ACMP_INPUTSEL_VASEL_APORT1YCH1, /**< Select APORT1Y CHannel 1 for the VA divider. */ + acmpVAInputAPORT1XCH2 = _ACMP_INPUTSEL_VASEL_APORT1XCH2, /**< Select APORT1X CHannel 2 for the VA divider. */ + acmpVAInputAPORT1YCH3 = _ACMP_INPUTSEL_VASEL_APORT1YCH3, /**< Select APORT1Y CHannel 3 for the VA divider. */ + acmpVAInputAPORT1XCH4 = _ACMP_INPUTSEL_VASEL_APORT1XCH4, /**< Select APORT1X CHannel 4 for the VA divider. */ + acmpVAInputAPORT1YCH5 = _ACMP_INPUTSEL_VASEL_APORT1YCH5, /**< Select APORT1Y CHannel 5 for the VA divider. */ + acmpVAInputAPORT1XCH6 = _ACMP_INPUTSEL_VASEL_APORT1XCH6, /**< Select APORT1X CHannel 6 for the VA divider. */ + acmpVAInputAPORT1YCH7 = _ACMP_INPUTSEL_VASEL_APORT1YCH7, /**< Select APORT1Y CHannel 7 for the VA divider. */ + acmpVAInputAPORT1XCH8 = _ACMP_INPUTSEL_VASEL_APORT1XCH8, /**< Select APORT1X CHannel 8 for the VA divider. */ + acmpVAInputAPORT1YCH9 = _ACMP_INPUTSEL_VASEL_APORT1YCH9, /**< Select APORT1Y CHannel 9 for the VA divider. */ + acmpVAInputAPORT1XCH10 = _ACMP_INPUTSEL_VASEL_APORT1XCH10, /**< Select APORT1X CHannel 10 for the VA divider. */ + acmpVAInputAPORT1YCH11 = _ACMP_INPUTSEL_VASEL_APORT1YCH11, /**< Select APORT1Y CHannel 11 for the VA divider. */ + acmpVAInputAPORT1XCH12 = _ACMP_INPUTSEL_VASEL_APORT1XCH12, /**< Select APORT1X CHannel 12 for the VA divider. */ + acmpVAInputAPORT1YCH13 = _ACMP_INPUTSEL_VASEL_APORT1YCH13, /**< Select APORT1Y CHannel 13 for the VA divider. */ + acmpVAInputAPORT1XCH14 = _ACMP_INPUTSEL_VASEL_APORT1XCH14, /**< Select APORT1X CHannel 14 for the VA divider. */ + acmpVAInputAPORT1YCH15 = _ACMP_INPUTSEL_VASEL_APORT1YCH15, /**< Select APORT1Y CHannel 15 for the VA divider. */ + acmpVAInputAPORT1XCH16 = _ACMP_INPUTSEL_VASEL_APORT1XCH16, /**< Select APORT1X CHannel 16 for the VA divider. */ + acmpVAInputAPORT1YCH17 = _ACMP_INPUTSEL_VASEL_APORT1YCH17, /**< Select APORT1Y CHannel 17 for the VA divider. */ + acmpVAInputAPORT1XCH18 = _ACMP_INPUTSEL_VASEL_APORT1XCH18, /**< Select APORT1X CHannel 18 for the VA divider. */ + acmpVAInputAPORT1YCH19 = _ACMP_INPUTSEL_VASEL_APORT1YCH19, /**< Select APORT1Y CHannel 19 for the VA divider. */ + acmpVAInputAPORT1XCH20 = _ACMP_INPUTSEL_VASEL_APORT1XCH20, /**< Select APORT1X CHannel 20 for the VA divider. */ + acmpVAInputAPORT1YCH21 = _ACMP_INPUTSEL_VASEL_APORT1YCH21, /**< Select APORT1Y CHannel 21 for the VA divider. */ + acmpVAInputAPORT1XCH22 = _ACMP_INPUTSEL_VASEL_APORT1XCH22, /**< Select APORT1X CHannel 22 for the VA divider. */ + acmpVAInputAPORT1YCH23 = _ACMP_INPUTSEL_VASEL_APORT1YCH23, /**< Select APORT1Y CHannel 23 for the VA divider. */ + acmpVAInputAPORT1XCH24 = _ACMP_INPUTSEL_VASEL_APORT1XCH24, /**< Select APORT1X CHannel 24 for the VA divider. */ + acmpVAInputAPORT1YCH25 = _ACMP_INPUTSEL_VASEL_APORT1YCH25, /**< Select APORT1Y CHannel 25 for the VA divider. */ + acmpVAInputAPORT1XCH26 = _ACMP_INPUTSEL_VASEL_APORT1XCH26, /**< Select APORT1X CHannel 26 for the VA divider. */ + acmpVAInputAPORT1YCH27 = _ACMP_INPUTSEL_VASEL_APORT1YCH27, /**< Select APORT1Y CHannel 27 for the VA divider. */ + acmpVAInputAPORT1XCH28 = _ACMP_INPUTSEL_VASEL_APORT1XCH28, /**< Select APORT1X CHannel 28 for the VA divider. */ + acmpVAInputAPORT1YCH29 = _ACMP_INPUTSEL_VASEL_APORT1YCH29, /**< Select APORT1Y CHannel 29 for the VA divider. */ + acmpVAInputAPORT1XCH30 = _ACMP_INPUTSEL_VASEL_APORT1XCH30, /**< Select APORT1X CHannel 30 for the VA divider. */ + acmpVAInputAPORT1YCH31 = _ACMP_INPUTSEL_VASEL_APORT1YCH31 /**< Select APORT1Y CHannel 31 for the VA divider. */ +} ACMP_VAInput_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/** + * ACMP input to the VB divider. This enumeration is used to select the input for + * the VB divider. + */ +typedef enum { + acmpVBInput1V25 = _ACMP_INPUTSEL_VBSEL_1V25, /**< Mode 1V25 for ACMP_INPUTSEL */ + acmpVBInput2V5 = _ACMP_INPUTSEL_VBSEL_2V5 /**< Mode 2V5 for ACMP_INPUTSEL */ +} ACMP_VBInput_TypeDef; +#endif + +#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) +/** + * ACMP Low-Power Input Selection. + */ +typedef enum { + acmpVLPInputVADIV = _ACMP_INPUTSEL_VLPSEL_VADIV, /**< Mode VADIV for ACMP_INPUTSEL */ + acmpVLPInputVBDIV = _ACMP_INPUTSEL_VLPSEL_VBDIV /**< Mode VBDIV for ACMP_INPUTSEL */ +} ACMP_VLPInput_Typedef; +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) +/** ACMP Input Selection. */ +typedef enum { + acmpInputVSS = _ACMP_INPUTCTRL_POSSEL_VSS, /**< Select VSS. */ + acmpInputVREFDIVAVDD = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDD, /**< Select Divided AVDD. */ + acmpInputVREFDIVAVDDLP = _ACMP_INPUTCTRL_POSSEL_VREFDIVAVDDLP, /**< Select Low-Power Divided AVDD. */ + acmpInputVREFDIV1V25 = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25, /**< Select Divided 1V25 reference. */ + acmpInputVREFDIV1V25LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV1V25LP, /**< Select Low-power Divided 1V25 reference. */ + acmpInputVREFDIV2V5 = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5, /**< Select Divided 2V5 reference. */ + acmpInputVREFDIV2V5LP = _ACMP_INPUTCTRL_POSSEL_VREFDIV2V5LP, /**< Select Low-power Divided 2V5 reference. */ + acmpInputVSENSE01DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4, /**< Select VSENSE0 divided by 4. */ + acmpInputVSENSE01DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE01DIV4LP, /**< Select Low-power VSENSE0 divided by 4. */ + acmpInputVSENSE11DIV4 = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4, /**< VSENSE1 divided by 4. */ + acmpInputVSENSE11DIV4LP = _ACMP_INPUTCTRL_POSSEL_VSENSE11DIV4LP, /**< Low-power VSENSE1 divided by 4. */ + acmpInputCAPSENSE = _ACMP_INPUTCTRL_NEGSEL_CAPSENSE, /**< Select Low-Power Divided AVDD. */ +#if defined(_ACMP_INPUTCTRL_POSSEL_VDACOUT0) + acmpInputVDACOUT0 = _ACMP_INPUTCTRL_POSSEL_VDACOUT0, /**< Select VDAC0 channel 0 output. */ + acmpInputVDACOUT1 = _ACMP_INPUTCTRL_POSSEL_VDACOUT1, /**< Select VDAC0 channel 1 output. */ +#endif +#if defined(_ACMP_INPUTCTRL_POSSEL_VDAC0OUT1) + acmpInputVDAC0OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC0OUT1, /**< Select VDAC0 channel 1 output. */ + acmpInputVDAC1OUT1 = _ACMP_INPUTCTRL_POSSEL_VDAC1OUT1, /**< Select VDAC1 channel 1 output. */ +#endif +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + acmpInputEXTPA = _ACMP_INPUTCTRL_POSSEL_EXTPA, /**< Select external interface, base is PA0. */ + acmpInputEXTPB = _ACMP_INPUTCTRL_POSSEL_EXTPB, /**< Select external interface, base is PB0. */ + acmpInputEXTPC = _ACMP_INPUTCTRL_POSSEL_EXTPC, /**< Select external interface, base is PC0. */ + acmpInputEXTPD = _ACMP_INPUTCTRL_POSSEL_EXTPD, /**< Select external interface, base is PD0. */ +#endif + acmpInputPA0 = _ACMP_INPUTCTRL_POSSEL_PA0, /**< Select Port A Pin0. */ + acmpInputPA1 = _ACMP_INPUTCTRL_POSSEL_PA1, /**< Select Port A Pin1. */ + acmpInputPA2 = _ACMP_INPUTCTRL_POSSEL_PA2, /**< Select Port A Pin2. */ + acmpInputPA3 = _ACMP_INPUTCTRL_POSSEL_PA3, /**< Select Port A Pin3. */ + acmpInputPA4 = _ACMP_INPUTCTRL_POSSEL_PA4, /**< Select Port A Pin4. */ + acmpInputPA5 = _ACMP_INPUTCTRL_POSSEL_PA5, /**< Select Port A Pin5. */ + acmpInputPA6 = _ACMP_INPUTCTRL_POSSEL_PA6, /**< Select Port A Pin6. */ + acmpInputPA7 = _ACMP_INPUTCTRL_POSSEL_PA7, /**< Select Port A Pin7. */ + acmpInputPA8 = _ACMP_INPUTCTRL_POSSEL_PA8, /**< Select Port A Pin8. */ + acmpInputPA9 = _ACMP_INPUTCTRL_POSSEL_PA9, /**< Select Port A Pin9. */ + acmpInputPA10 = _ACMP_INPUTCTRL_POSSEL_PA10, /**< Select Port A Pin10. */ + acmpInputPA11 = _ACMP_INPUTCTRL_POSSEL_PA11, /**< Select Port A Pin11. */ + acmpInputPA12 = _ACMP_INPUTCTRL_POSSEL_PA12, /**< Select Port A Pin12. */ + acmpInputPA13 = _ACMP_INPUTCTRL_POSSEL_PA13, /**< Select Port A Pin13. */ + acmpInputPA14 = _ACMP_INPUTCTRL_POSSEL_PA14, /**< Select Port A Pin14. */ + acmpInputPA15 = _ACMP_INPUTCTRL_POSSEL_PA15, /**< Select Port A Pin15. */ + acmpInputPB0 = _ACMP_INPUTCTRL_POSSEL_PB0, /**< Select Port B Pin0. */ + acmpInputPB1 = _ACMP_INPUTCTRL_POSSEL_PB1, /**< Select Port B Pin1. */ + acmpInputPB2 = _ACMP_INPUTCTRL_POSSEL_PB2, /**< Select Port B Pin2. */ + acmpInputPB3 = _ACMP_INPUTCTRL_POSSEL_PB3, /**< Select Port B Pin3. */ + acmpInputPB4 = _ACMP_INPUTCTRL_POSSEL_PB4, /**< Select Port B Pin4. */ + acmpInputPB5 = _ACMP_INPUTCTRL_POSSEL_PB5, /**< Select Port B Pin5. */ + acmpInputPB6 = _ACMP_INPUTCTRL_POSSEL_PB6, /**< Select Port B Pin6. */ + acmpInputPB7 = _ACMP_INPUTCTRL_POSSEL_PB7, /**< Select Port B Pin7. */ + acmpInputPB8 = _ACMP_INPUTCTRL_POSSEL_PB8, /**< Select Port B Pin8. */ + acmpInputPB9 = _ACMP_INPUTCTRL_POSSEL_PB9, /**< Select Port B Pin9. */ + acmpInputPB10 = _ACMP_INPUTCTRL_POSSEL_PB10, /**< Select Port B Pin10. */ + acmpInputPB11 = _ACMP_INPUTCTRL_POSSEL_PB11, /**< Select Port B Pin11. */ + acmpInputPB12 = _ACMP_INPUTCTRL_POSSEL_PB12, /**< Select Port B Pin12. */ + acmpInputPB13 = _ACMP_INPUTCTRL_POSSEL_PB13, /**< Select Port B Pin13. */ + acmpInputPB14 = _ACMP_INPUTCTRL_POSSEL_PB14, /**< Select Port B Pin14. */ + acmpInputPB15 = _ACMP_INPUTCTRL_POSSEL_PB15, /**< Select Port B Pin15. */ + acmpInputPC0 = _ACMP_INPUTCTRL_POSSEL_PC0, /**< Select Port C Pin0. */ + acmpInputPC1 = _ACMP_INPUTCTRL_POSSEL_PC1, /**< Select Port C Pin1. */ + acmpInputPC2 = _ACMP_INPUTCTRL_POSSEL_PC2, /**< Select Port C Pin2. */ + acmpInputPC3 = _ACMP_INPUTCTRL_POSSEL_PC3, /**< Select Port C Pin3. */ + acmpInputPC4 = _ACMP_INPUTCTRL_POSSEL_PC4, /**< Select Port C Pin4. */ + acmpInputPC5 = _ACMP_INPUTCTRL_POSSEL_PC5, /**< Select Port C Pin5. */ + acmpInputPC6 = _ACMP_INPUTCTRL_POSSEL_PC6, /**< Select Port C Pin6. */ + acmpInputPC7 = _ACMP_INPUTCTRL_POSSEL_PC7, /**< Select Port C Pin7. */ + acmpInputPC8 = _ACMP_INPUTCTRL_POSSEL_PC8, /**< Select Port C Pin8. */ + acmpInputPC9 = _ACMP_INPUTCTRL_POSSEL_PC9, /**< Select Port C Pin9. */ + acmpInputPC10 = _ACMP_INPUTCTRL_POSSEL_PC10, /**< Select Port C Pin10. */ + acmpInputPC11 = _ACMP_INPUTCTRL_POSSEL_PC11, /**< Select Port C Pin11. */ + acmpInputPC12 = _ACMP_INPUTCTRL_POSSEL_PC12, /**< Select Port C Pin12. */ + acmpInputPC13 = _ACMP_INPUTCTRL_POSSEL_PC13, /**< Select Port C Pin13. */ + acmpInputPC14 = _ACMP_INPUTCTRL_POSSEL_PC14, /**< Select Port C Pin14. */ + acmpInputPC15 = _ACMP_INPUTCTRL_POSSEL_PC15, /**< Select Port C Pin15. */ + acmpInputPD0 = _ACMP_INPUTCTRL_POSSEL_PD0, /**< Select Port D Pin0. */ + acmpInputPD1 = _ACMP_INPUTCTRL_POSSEL_PD1, /**< Select Port D Pin1. */ + acmpInputPD2 = _ACMP_INPUTCTRL_POSSEL_PD2, /**< Select Port D Pin2. */ + acmpInputPD3 = _ACMP_INPUTCTRL_POSSEL_PD3, /**< Select Port D Pin3. */ + acmpInputPD4 = _ACMP_INPUTCTRL_POSSEL_PD4, /**< Select Port D Pin4. */ + acmpInputPD5 = _ACMP_INPUTCTRL_POSSEL_PD5, /**< Select Port D Pin5. */ + acmpInputPD6 = _ACMP_INPUTCTRL_POSSEL_PD6, /**< Select Port D Pin6. */ + acmpInputPD7 = _ACMP_INPUTCTRL_POSSEL_PD7, /**< Select Port D Pin7. */ + acmpInputPD8 = _ACMP_INPUTCTRL_POSSEL_PD8, /**< Select Port D Pin8. */ + acmpInputPD9 = _ACMP_INPUTCTRL_POSSEL_PD9, /**< Select Port D Pin9. */ + acmpInputPD10 = _ACMP_INPUTCTRL_POSSEL_PD10, /**< Select Port D Pin10. */ + acmpInputPD11 = _ACMP_INPUTCTRL_POSSEL_PD11, /**< Select Port D Pin11. */ + acmpInputPD12 = _ACMP_INPUTCTRL_POSSEL_PD12, /**< Select Port D Pin12. */ + acmpInputPD13 = _ACMP_INPUTCTRL_POSSEL_PD13, /**< Select Port D Pin13. */ + acmpInputPD14 = _ACMP_INPUTCTRL_POSSEL_PD14, /**< Select Port D Pin14. */ + acmpInputPD15 = _ACMP_INPUTCTRL_POSSEL_PD15, /**< Select Port D Pin15. */ +} ACMP_Channel_TypeDef; +#elif defined(_ACMP_INPUTSEL_POSSEL_APORT0XCH0) +/** ACMP Input Selection. */ +typedef enum { + acmpInputAPORT0XCH0 = _ACMP_INPUTSEL_POSSEL_APORT0XCH0, /**< Select Dedicated APORT0X CHannel 0. */ + acmpInputAPORT0XCH1 = _ACMP_INPUTSEL_POSSEL_APORT0XCH1, /**< Select Dedicated APORT0X CHannel 1. */ + acmpInputAPORT0XCH2 = _ACMP_INPUTSEL_POSSEL_APORT0XCH2, /**< Select Dedicated APORT0X CHannel 2. */ + acmpInputAPORT0XCH3 = _ACMP_INPUTSEL_POSSEL_APORT0XCH3, /**< Select Dedicated APORT0X CHannel 3. */ + acmpInputAPORT0XCH4 = _ACMP_INPUTSEL_POSSEL_APORT0XCH4, /**< Select Dedicated APORT0X CHannel 4. */ + acmpInputAPORT0XCH5 = _ACMP_INPUTSEL_POSSEL_APORT0XCH5, /**< Select Dedicated APORT0X CHannel 5. */ + acmpInputAPORT0XCH6 = _ACMP_INPUTSEL_POSSEL_APORT0XCH6, /**< Select Dedicated APORT0X CHannel 6. */ + acmpInputAPORT0XCH7 = _ACMP_INPUTSEL_POSSEL_APORT0XCH7, /**< Select Dedicated APORT0X CHannel 7. */ + acmpInputAPORT0XCH8 = _ACMP_INPUTSEL_POSSEL_APORT0XCH8, /**< Select Dedicated APORT0X CHannel 8. */ + acmpInputAPORT0XCH9 = _ACMP_INPUTSEL_POSSEL_APORT0XCH9, /**< Select Dedicated APORT0X CHannel 9. */ + acmpInputAPORT0XCH10 = _ACMP_INPUTSEL_POSSEL_APORT0XCH10, /**< Select Dedicated APORT0X CHannel 10. */ + acmpInputAPORT0XCH11 = _ACMP_INPUTSEL_POSSEL_APORT0XCH11, /**< Select Dedicated APORT0X CHannel 11. */ + acmpInputAPORT0XCH12 = _ACMP_INPUTSEL_POSSEL_APORT0XCH12, /**< Select Dedicated APORT0X CHannel 12. */ + acmpInputAPORT0XCH13 = _ACMP_INPUTSEL_POSSEL_APORT0XCH13, /**< Select Dedicated APORT0X CHannel 13. */ + acmpInputAPORT0XCH14 = _ACMP_INPUTSEL_POSSEL_APORT0XCH14, /**< Select Dedicated APORT0X CHannel 14. */ + acmpInputAPORT0XCH15 = _ACMP_INPUTSEL_POSSEL_APORT0XCH15, /**< Select Dedicated APORT0X CHannel 15. */ + acmpInputAPORT0YCH0 = _ACMP_INPUTSEL_POSSEL_APORT0YCH0, /**< Select Dedicated APORT0Y CHannel 0. */ + acmpInputAPORT0YCH1 = _ACMP_INPUTSEL_POSSEL_APORT0YCH1, /**< Select Dedicated APORT0Y CHannel 1. */ + acmpInputAPORT0YCH2 = _ACMP_INPUTSEL_POSSEL_APORT0YCH2, /**< Select Dedicated APORT0Y CHannel 2. */ + acmpInputAPORT0YCH3 = _ACMP_INPUTSEL_POSSEL_APORT0YCH3, /**< Select Dedicated APORT0Y CHannel 3. */ + acmpInputAPORT0YCH4 = _ACMP_INPUTSEL_POSSEL_APORT0YCH4, /**< Select Dedicated APORT0Y CHannel 4. */ + acmpInputAPORT0YCH5 = _ACMP_INPUTSEL_POSSEL_APORT0YCH5, /**< Select Dedicated APORT0Y CHannel 5. */ + acmpInputAPORT0YCH6 = _ACMP_INPUTSEL_POSSEL_APORT0YCH6, /**< Select Dedicated APORT0Y CHannel 6. */ + acmpInputAPORT0YCH7 = _ACMP_INPUTSEL_POSSEL_APORT0YCH7, /**< Select Dedicated APORT0Y CHannel 7. */ + acmpInputAPORT0YCH8 = _ACMP_INPUTSEL_POSSEL_APORT0YCH8, /**< Select Dedicated APORT0Y CHannel 8. */ + acmpInputAPORT0YCH9 = _ACMP_INPUTSEL_POSSEL_APORT0YCH9, /**< Select Dedicated APORT0Y CHannel 9. */ + acmpInputAPORT0YCH10 = _ACMP_INPUTSEL_POSSEL_APORT0YCH10, /**< Select Dedicated APORT0Y CHannel 10. */ + acmpInputAPORT0YCH11 = _ACMP_INPUTSEL_POSSEL_APORT0YCH11, /**< Select Dedicated APORT0Y CHannel 11. */ + acmpInputAPORT0YCH12 = _ACMP_INPUTSEL_POSSEL_APORT0YCH12, /**< Select Dedicated APORT0Y CHannel 12. */ + acmpInputAPORT0YCH13 = _ACMP_INPUTSEL_POSSEL_APORT0YCH13, /**< Select Dedicated APORT0Y CHannel 13. */ + acmpInputAPORT0YCH14 = _ACMP_INPUTSEL_POSSEL_APORT0YCH14, /**< Select Dedicated APORT0Y CHannel 14. */ + acmpInputAPORT0YCH15 = _ACMP_INPUTSEL_POSSEL_APORT0YCH15, /**< Select Dedicated APORT0Y CHannel 15. */ + acmpInputAPORT1XCH0 = _ACMP_INPUTSEL_POSSEL_APORT1XCH0, /**< Select Dedicated APORT1X CHannel 0. */ + acmpInputAPORT1YCH1 = _ACMP_INPUTSEL_POSSEL_APORT1YCH1, /**< Select Dedicated APORT1Y CHannel 1. */ + acmpInputAPORT1XCH2 = _ACMP_INPUTSEL_POSSEL_APORT1XCH2, /**< Select Dedicated APORT1X CHannel 2. */ + acmpInputAPORT1YCH3 = _ACMP_INPUTSEL_POSSEL_APORT1YCH3, /**< Select Dedicated APORT1Y CHannel 3. */ + acmpInputAPORT1XCH4 = _ACMP_INPUTSEL_POSSEL_APORT1XCH4, /**< Select Dedicated APORT1X CHannel 4. */ + acmpInputAPORT1YCH5 = _ACMP_INPUTSEL_POSSEL_APORT1YCH5, /**< Select Dedicated APORT1Y CHannel 5. */ + acmpInputAPORT1XCH6 = _ACMP_INPUTSEL_POSSEL_APORT1XCH6, /**< Select Dedicated APORT1X CHannel 6. */ + acmpInputAPORT1YCH7 = _ACMP_INPUTSEL_POSSEL_APORT1YCH7, /**< Select Dedicated APORT1Y CHannel 7. */ + acmpInputAPORT1XCH8 = _ACMP_INPUTSEL_POSSEL_APORT1XCH8, /**< Select Dedicated APORT1X CHannel 8. */ + acmpInputAPORT1YCH9 = _ACMP_INPUTSEL_POSSEL_APORT1YCH9, /**< Select Dedicated APORT1Y CHannel 9. */ + acmpInputAPORT1XCH10 = _ACMP_INPUTSEL_POSSEL_APORT1XCH10, /**< Select Dedicated APORT1X CHannel 10. */ + acmpInputAPORT1YCH11 = _ACMP_INPUTSEL_POSSEL_APORT1YCH11, /**< Select Dedicated APORT1Y CHannel 11. */ + acmpInputAPORT1XCH12 = _ACMP_INPUTSEL_POSSEL_APORT1XCH12, /**< Select Dedicated APORT1X CHannel 12. */ + acmpInputAPORT1YCH13 = _ACMP_INPUTSEL_POSSEL_APORT1YCH13, /**< Select Dedicated APORT1Y CHannel 13. */ + acmpInputAPORT1XCH14 = _ACMP_INPUTSEL_POSSEL_APORT1XCH14, /**< Select Dedicated APORT1X CHannel 14. */ + acmpInputAPORT1YCH15 = _ACMP_INPUTSEL_POSSEL_APORT1YCH15, /**< Select Dedicated APORT1Y CHannel 15. */ + acmpInputAPORT1XCH16 = _ACMP_INPUTSEL_POSSEL_APORT1XCH16, /**< Select Dedicated APORT1X CHannel 16. */ + acmpInputAPORT1YCH17 = _ACMP_INPUTSEL_POSSEL_APORT1YCH17, /**< Select Dedicated APORT1Y CHannel 17. */ + acmpInputAPORT1XCH18 = _ACMP_INPUTSEL_POSSEL_APORT1XCH18, /**< Select Dedicated APORT1X CHannel 18. */ + acmpInputAPORT1YCH19 = _ACMP_INPUTSEL_POSSEL_APORT1YCH19, /**< Select Dedicated APORT1Y CHannel 19. */ + acmpInputAPORT1XCH20 = _ACMP_INPUTSEL_POSSEL_APORT1XCH20, /**< Select Dedicated APORT1X CHannel 20. */ + acmpInputAPORT1YCH21 = _ACMP_INPUTSEL_POSSEL_APORT1YCH21, /**< Select Dedicated APORT1Y CHannel 21. */ + acmpInputAPORT1XCH22 = _ACMP_INPUTSEL_POSSEL_APORT1XCH22, /**< Select Dedicated APORT1X CHannel 22. */ + acmpInputAPORT1YCH23 = _ACMP_INPUTSEL_POSSEL_APORT1YCH23, /**< Select Dedicated APORT1Y CHannel 23. */ + acmpInputAPORT1XCH24 = _ACMP_INPUTSEL_POSSEL_APORT1XCH24, /**< Select Dedicated APORT1X CHannel 24. */ + acmpInputAPORT1YCH25 = _ACMP_INPUTSEL_POSSEL_APORT1YCH25, /**< Select Dedicated APORT1Y CHannel 25. */ + acmpInputAPORT1XCH26 = _ACMP_INPUTSEL_POSSEL_APORT1XCH26, /**< Select Dedicated APORT1X CHannel 26. */ + acmpInputAPORT1YCH27 = _ACMP_INPUTSEL_POSSEL_APORT1YCH27, /**< Select Dedicated APORT1Y CHannel 27. */ + acmpInputAPORT1XCH28 = _ACMP_INPUTSEL_POSSEL_APORT1XCH28, /**< Select Dedicated APORT1X CHannel 28. */ + acmpInputAPORT1YCH29 = _ACMP_INPUTSEL_POSSEL_APORT1YCH29, /**< Select Dedicated APORT1Y CHannel 29. */ + acmpInputAPORT1XCH30 = _ACMP_INPUTSEL_POSSEL_APORT1XCH30, /**< Select Dedicated APORT1X CHannel 30. */ + acmpInputAPORT1YCH31 = _ACMP_INPUTSEL_POSSEL_APORT1YCH31, /**< Select Dedicated APORT1Y CHannel 31. */ + acmpInputAPORT2YCH0 = _ACMP_INPUTSEL_POSSEL_APORT2YCH0, /**< Select Dedicated APORT2Y CHannel 0. */ + acmpInputAPORT2XCH1 = _ACMP_INPUTSEL_POSSEL_APORT2XCH1, /**< Select Dedicated APORT2X CHannel 1. */ + acmpInputAPORT2YCH2 = _ACMP_INPUTSEL_POSSEL_APORT2YCH2, /**< Select Dedicated APORT2Y CHannel 2. */ + acmpInputAPORT2XCH3 = _ACMP_INPUTSEL_POSSEL_APORT2XCH3, /**< Select Dedicated APORT2X CHannel 3. */ + acmpInputAPORT2YCH4 = _ACMP_INPUTSEL_POSSEL_APORT2YCH4, /**< Select Dedicated APORT2Y CHannel 4. */ + acmpInputAPORT2XCH5 = _ACMP_INPUTSEL_POSSEL_APORT2XCH5, /**< Select Dedicated APORT2X CHannel 5. */ + acmpInputAPORT2YCH6 = _ACMP_INPUTSEL_POSSEL_APORT2YCH6, /**< Select Dedicated APORT2Y CHannel 6. */ + acmpInputAPORT2XCH7 = _ACMP_INPUTSEL_POSSEL_APORT2XCH7, /**< Select Dedicated APORT2X CHannel 7. */ + acmpInputAPORT2YCH8 = _ACMP_INPUTSEL_POSSEL_APORT2YCH8, /**< Select Dedicated APORT2Y CHannel 8. */ + acmpInputAPORT2XCH9 = _ACMP_INPUTSEL_POSSEL_APORT2XCH9, /**< Select Dedicated APORT2X CHannel 9. */ + acmpInputAPORT2YCH10 = _ACMP_INPUTSEL_POSSEL_APORT2YCH10, /**< Select Dedicated APORT2Y CHannel 10. */ + acmpInputAPORT2XCH11 = _ACMP_INPUTSEL_POSSEL_APORT2XCH11, /**< Select Dedicated APORT2X CHannel 11. */ + acmpInputAPORT2YCH12 = _ACMP_INPUTSEL_POSSEL_APORT2YCH12, /**< Select Dedicated APORT2Y CHannel 12. */ + acmpInputAPORT2XCH13 = _ACMP_INPUTSEL_POSSEL_APORT2XCH13, /**< Select Dedicated APORT2X CHannel 13. */ + acmpInputAPORT2YCH14 = _ACMP_INPUTSEL_POSSEL_APORT2YCH14, /**< Select Dedicated APORT2Y CHannel 14. */ + acmpInputAPORT2XCH15 = _ACMP_INPUTSEL_POSSEL_APORT2XCH15, /**< Select Dedicated APORT2X CHannel 15. */ + acmpInputAPORT2YCH16 = _ACMP_INPUTSEL_POSSEL_APORT2YCH16, /**< Select Dedicated APORT2Y CHannel 16. */ + acmpInputAPORT2XCH17 = _ACMP_INPUTSEL_POSSEL_APORT2XCH17, /**< Select Dedicated APORT2X CHannel 17. */ + acmpInputAPORT2YCH18 = _ACMP_INPUTSEL_POSSEL_APORT2YCH18, /**< Select Dedicated APORT2Y CHannel 18. */ + acmpInputAPORT2XCH19 = _ACMP_INPUTSEL_POSSEL_APORT2XCH19, /**< Select Dedicated APORT2X CHannel 19. */ + acmpInputAPORT2YCH20 = _ACMP_INPUTSEL_POSSEL_APORT2YCH20, /**< Select Dedicated APORT2Y CHannel 20. */ + acmpInputAPORT2XCH21 = _ACMP_INPUTSEL_POSSEL_APORT2XCH21, /**< Select Dedicated APORT2X CHannel 21. */ + acmpInputAPORT2YCH22 = _ACMP_INPUTSEL_POSSEL_APORT2YCH22, /**< Select Dedicated APORT2Y CHannel 22. */ + acmpInputAPORT2XCH23 = _ACMP_INPUTSEL_POSSEL_APORT2XCH23, /**< Select Dedicated APORT2X CHannel 23. */ + acmpInputAPORT2YCH24 = _ACMP_INPUTSEL_POSSEL_APORT2YCH24, /**< Select Dedicated APORT2Y CHannel 24. */ + acmpInputAPORT2XCH25 = _ACMP_INPUTSEL_POSSEL_APORT2XCH25, /**< Select Dedicated APORT2X CHannel 25. */ + acmpInputAPORT2YCH26 = _ACMP_INPUTSEL_POSSEL_APORT2YCH26, /**< Select Dedicated APORT2Y CHannel 26. */ + acmpInputAPORT2XCH27 = _ACMP_INPUTSEL_POSSEL_APORT2XCH27, /**< Select Dedicated APORT2X CHannel 27. */ + acmpInputAPORT2YCH28 = _ACMP_INPUTSEL_POSSEL_APORT2YCH28, /**< Select Dedicated APORT2Y CHannel 28. */ + acmpInputAPORT2XCH29 = _ACMP_INPUTSEL_POSSEL_APORT2XCH29, /**< Select Dedicated APORT2X CHannel 29. */ + acmpInputAPORT2YCH30 = _ACMP_INPUTSEL_POSSEL_APORT2YCH30, /**< Select Dedicated APORT2Y CHannel 30. */ + acmpInputAPORT2XCH31 = _ACMP_INPUTSEL_POSSEL_APORT2XCH31, /**< Select Dedicated APORT2X CHannel 31. */ + acmpInputAPORT3XCH0 = _ACMP_INPUTSEL_POSSEL_APORT3XCH0, /**< Select Dedicated APORT3X CHannel 0. */ + acmpInputAPORT3YCH1 = _ACMP_INPUTSEL_POSSEL_APORT3YCH1, /**< Select Dedicated APORT3Y CHannel 1. */ + acmpInputAPORT3XCH2 = _ACMP_INPUTSEL_POSSEL_APORT3XCH2, /**< Select Dedicated APORT3X CHannel 2. */ + acmpInputAPORT3YCH3 = _ACMP_INPUTSEL_POSSEL_APORT3YCH3, /**< Select Dedicated APORT3Y CHannel 3. */ + acmpInputAPORT3XCH4 = _ACMP_INPUTSEL_POSSEL_APORT3XCH4, /**< Select Dedicated APORT3X CHannel 4. */ + acmpInputAPORT3YCH5 = _ACMP_INPUTSEL_POSSEL_APORT3YCH5, /**< Select Dedicated APORT3Y CHannel 5. */ + acmpInputAPORT3XCH6 = _ACMP_INPUTSEL_POSSEL_APORT3XCH6, /**< Select Dedicated APORT3X CHannel 6. */ + acmpInputAPORT3YCH7 = _ACMP_INPUTSEL_POSSEL_APORT3YCH7, /**< Select Dedicated APORT3Y CHannel 7. */ + acmpInputAPORT3XCH8 = _ACMP_INPUTSEL_POSSEL_APORT3XCH8, /**< Select Dedicated APORT3X CHannel 8. */ + acmpInputAPORT3YCH9 = _ACMP_INPUTSEL_POSSEL_APORT3YCH9, /**< Select Dedicated APORT3Y CHannel 9. */ + acmpInputAPORT3XCH10 = _ACMP_INPUTSEL_POSSEL_APORT3XCH10, /**< Select Dedicated APORT3X CHannel 10. */ + acmpInputAPORT3YCH11 = _ACMP_INPUTSEL_POSSEL_APORT3YCH11, /**< Select Dedicated APORT3Y CHannel 11. */ + acmpInputAPORT3XCH12 = _ACMP_INPUTSEL_POSSEL_APORT3XCH12, /**< Select Dedicated APORT3X CHannel 12. */ + acmpInputAPORT3YCH13 = _ACMP_INPUTSEL_POSSEL_APORT3YCH13, /**< Select Dedicated APORT3Y CHannel 13. */ + acmpInputAPORT3XCH14 = _ACMP_INPUTSEL_POSSEL_APORT3XCH14, /**< Select Dedicated APORT3X CHannel 14. */ + acmpInputAPORT3YCH15 = _ACMP_INPUTSEL_POSSEL_APORT3YCH15, /**< Select Dedicated APORT3Y CHannel 15. */ + acmpInputAPORT3XCH16 = _ACMP_INPUTSEL_POSSEL_APORT3XCH16, /**< Select Dedicated APORT3X CHannel 16. */ + acmpInputAPORT3YCH17 = _ACMP_INPUTSEL_POSSEL_APORT3YCH17, /**< Select Dedicated APORT3Y CHannel 17. */ + acmpInputAPORT3XCH18 = _ACMP_INPUTSEL_POSSEL_APORT3XCH18, /**< Select Dedicated APORT3X CHannel 18. */ + acmpInputAPORT3YCH19 = _ACMP_INPUTSEL_POSSEL_APORT3YCH19, /**< Select Dedicated APORT3Y CHannel 19. */ + acmpInputAPORT3XCH20 = _ACMP_INPUTSEL_POSSEL_APORT3XCH20, /**< Select Dedicated APORT3X CHannel 20. */ + acmpInputAPORT3YCH21 = _ACMP_INPUTSEL_POSSEL_APORT3YCH21, /**< Select Dedicated APORT3Y CHannel 21. */ + acmpInputAPORT3XCH22 = _ACMP_INPUTSEL_POSSEL_APORT3XCH22, /**< Select Dedicated APORT3X CHannel 22. */ + acmpInputAPORT3YCH23 = _ACMP_INPUTSEL_POSSEL_APORT3YCH23, /**< Select Dedicated APORT3Y CHannel 23. */ + acmpInputAPORT3XCH24 = _ACMP_INPUTSEL_POSSEL_APORT3XCH24, /**< Select Dedicated APORT3X CHannel 24. */ + acmpInputAPORT3YCH25 = _ACMP_INPUTSEL_POSSEL_APORT3YCH25, /**< Select Dedicated APORT3Y CHannel 25. */ + acmpInputAPORT3XCH26 = _ACMP_INPUTSEL_POSSEL_APORT3XCH26, /**< Select Dedicated APORT3X CHannel 26. */ + acmpInputAPORT3YCH27 = _ACMP_INPUTSEL_POSSEL_APORT3YCH27, /**< Select Dedicated APORT3Y CHannel 27. */ + acmpInputAPORT3XCH28 = _ACMP_INPUTSEL_POSSEL_APORT3XCH28, /**< Select Dedicated APORT3X CHannel 28. */ + acmpInputAPORT3YCH29 = _ACMP_INPUTSEL_POSSEL_APORT3YCH29, /**< Select Dedicated APORT3Y CHannel 29. */ + acmpInputAPORT3XCH30 = _ACMP_INPUTSEL_POSSEL_APORT3XCH30, /**< Select Dedicated APORT3X CHannel 30. */ + acmpInputAPORT3YCH31 = _ACMP_INPUTSEL_POSSEL_APORT3YCH31, /**< Select Dedicated APORT3Y CHannel 31. */ + acmpInputAPORT4YCH0 = _ACMP_INPUTSEL_POSSEL_APORT4YCH0, /**< Select Dedicated APORT4Y CHannel 0. */ + acmpInputAPORT4XCH1 = _ACMP_INPUTSEL_POSSEL_APORT4XCH1, /**< Select Dedicated APORT4X CHannel 1. */ + acmpInputAPORT4YCH2 = _ACMP_INPUTSEL_POSSEL_APORT4YCH2, /**< Select Dedicated APORT4Y CHannel 2. */ + acmpInputAPORT4XCH3 = _ACMP_INPUTSEL_POSSEL_APORT4XCH3, /**< Select Dedicated APORT4X CHannel 3. */ + acmpInputAPORT4YCH4 = _ACMP_INPUTSEL_POSSEL_APORT4YCH4, /**< Select Dedicated APORT4Y CHannel 4. */ + acmpInputAPORT4XCH5 = _ACMP_INPUTSEL_POSSEL_APORT4XCH5, /**< Select Dedicated APORT4X CHannel 5. */ + acmpInputAPORT4YCH6 = _ACMP_INPUTSEL_POSSEL_APORT4YCH6, /**< Select Dedicated APORT4Y CHannel 6. */ + acmpInputAPORT4XCH7 = _ACMP_INPUTSEL_POSSEL_APORT4XCH7, /**< Select Dedicated APORT4X CHannel 7. */ + acmpInputAPORT4YCH8 = _ACMP_INPUTSEL_POSSEL_APORT4YCH8, /**< Select Dedicated APORT4Y CHannel 8. */ + acmpInputAPORT4XCH9 = _ACMP_INPUTSEL_POSSEL_APORT4XCH9, /**< Select Dedicated APORT4X CHannel 9. */ + acmpInputAPORT4YCH10 = _ACMP_INPUTSEL_POSSEL_APORT4YCH10, /**< Select Dedicated APORT4Y CHannel 10. */ + acmpInputAPORT4XCH11 = _ACMP_INPUTSEL_POSSEL_APORT4XCH11, /**< Select Dedicated APORT4X CHannel 11. */ + acmpInputAPORT4YCH12 = _ACMP_INPUTSEL_POSSEL_APORT4YCH12, /**< Select Dedicated APORT4Y CHannel 12. */ + acmpInputAPORT4XCH13 = _ACMP_INPUTSEL_POSSEL_APORT4XCH13, /**< Select Dedicated APORT4X CHannel 13. */ + acmpInputAPORT4YCH16 = _ACMP_INPUTSEL_POSSEL_APORT4YCH16, /**< Select Dedicated APORT4Y CHannel 14. */ + acmpInputAPORT4XCH17 = _ACMP_INPUTSEL_POSSEL_APORT4XCH17, /**< Select Dedicated APORT4X CHannel 15. */ + acmpInputAPORT4YCH18 = _ACMP_INPUTSEL_POSSEL_APORT4YCH18, /**< Select Dedicated APORT4Y CHannel 16. */ + acmpInputAPORT4XCH19 = _ACMP_INPUTSEL_POSSEL_APORT4XCH19, /**< Select Dedicated APORT4X CHannel 17. */ + acmpInputAPORT4YCH20 = _ACMP_INPUTSEL_POSSEL_APORT4YCH20, /**< Select Dedicated APORT4Y CHannel 18. */ + acmpInputAPORT4XCH21 = _ACMP_INPUTSEL_POSSEL_APORT4XCH21, /**< Select Dedicated APORT4X CHannel 19. */ + acmpInputAPORT4YCH22 = _ACMP_INPUTSEL_POSSEL_APORT4YCH22, /**< Select Dedicated APORT4Y CHannel 20. */ + acmpInputAPORT4XCH23 = _ACMP_INPUTSEL_POSSEL_APORT4XCH23, /**< Select Dedicated APORT4X CHannel 21. */ + acmpInputAPORT4YCH24 = _ACMP_INPUTSEL_POSSEL_APORT4YCH24, /**< Select Dedicated APORT4Y CHannel 22. */ + acmpInputAPORT4XCH25 = _ACMP_INPUTSEL_POSSEL_APORT4XCH25, /**< Select Dedicated APORT4X CHannel 23. */ + acmpInputAPORT4YCH26 = _ACMP_INPUTSEL_POSSEL_APORT4YCH26, /**< Select Dedicated APORT4Y CHannel 24. */ + acmpInputAPORT4XCH27 = _ACMP_INPUTSEL_POSSEL_APORT4XCH27, /**< Select Dedicated APORT4X CHannel 25. */ + acmpInputAPORT4YCH28 = _ACMP_INPUTSEL_POSSEL_APORT4YCH28, /**< Select Dedicated APORT4Y CHannel 26. */ + acmpInputAPORT4XCH29 = _ACMP_INPUTSEL_POSSEL_APORT4XCH29, /**< Select Dedicated APORT4X CHannel 27. */ + acmpInputAPORT4YCH30 = _ACMP_INPUTSEL_POSSEL_APORT4YCH30, /**< Select Dedicated APORT4Y CHannel 28. */ + acmpInputAPORT4YCH14 = _ACMP_INPUTSEL_POSSEL_APORT4YCH14, /**< Select Dedicated APORT4X CHannel 29. */ + acmpInputAPORT4XCH15 = _ACMP_INPUTSEL_POSSEL_APORT4XCH15, /**< Select Dedicated APORT4Y CHannel 30. */ + acmpInputAPORT4XCH31 = _ACMP_INPUTSEL_POSSEL_APORT4XCH31, /**< Select Dedicated APORT4X CHannel 31. */ +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT0) + acmpInputDACOUT0 = _ACMP_INPUTSEL_POSSEL_DACOUT0, /**< Select DAC Channel 0 Output. */ +#endif +#if defined(_ACMP_INPUTSEL_POSSEL_DACOUT1) + acmpInputDACOUT1 = _ACMP_INPUTSEL_POSSEL_DACOUT1, /**< Select DAC Channel 1 Output. */ +#endif + acmpInputVLP = _ACMP_INPUTSEL_POSSEL_VLP, /**< Select Low-Power Sampled Voltage. */ + acmpInputVBDIV = _ACMP_INPUTSEL_POSSEL_VBDIV, /**< Select Divided VB Voltage. */ + acmpInputVADIV = _ACMP_INPUTSEL_POSSEL_VADIV, /**< Select Divided VA Voltage. */ + acmpInputVDD = _ACMP_INPUTSEL_POSSEL_VDD, /**< ACMPVDD as selected via PWRSEL. */ + acmpInputVSS = _ACMP_INPUTSEL_POSSEL_VSS, /**< Select VSS. */ +} ACMP_Channel_TypeDef; +#else +/** ACMP inputs. Note that scaled VDD and bandgap references can only be used + * as negative inputs. */ +typedef enum { + /** Channel 0 */ + acmpChannel0 = _ACMP_INPUTSEL_NEGSEL_CH0, + /** Channel 1 */ + acmpChannel1 = _ACMP_INPUTSEL_NEGSEL_CH1, + /** Channel 2 */ + acmpChannel2 = _ACMP_INPUTSEL_NEGSEL_CH2, + /** Channel 3 */ + acmpChannel3 = _ACMP_INPUTSEL_NEGSEL_CH3, + /** Channel 4 */ + acmpChannel4 = _ACMP_INPUTSEL_NEGSEL_CH4, + /** Channel 5 */ + acmpChannel5 = _ACMP_INPUTSEL_NEGSEL_CH5, + /** Channel 6 */ + acmpChannel6 = _ACMP_INPUTSEL_NEGSEL_CH6, + /** Channel 7 */ + acmpChannel7 = _ACMP_INPUTSEL_NEGSEL_CH7, + /** 1.25 V internal reference */ + acmpChannel1V25 = _ACMP_INPUTSEL_NEGSEL_1V25, + /** 2.5 V internal reference */ + acmpChannel2V5 = _ACMP_INPUTSEL_NEGSEL_2V5, + /** Scaled VDD reference */ + acmpChannelVDD = _ACMP_INPUTSEL_NEGSEL_VDD, + +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH0) + /** DAC0 channel 0 */ + acmpChannelDAC0Ch0 = _ACMP_INPUTSEL_NEGSEL_DAC0CH0, +#endif + +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) + /** DAC0 channel 1 */ + acmpChannelDAC0Ch1 = _ACMP_INPUTSEL_NEGSEL_DAC0CH1, +#endif + +#if defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) + /** Capacitive sense mode */ + acmpChannelCapSense = _ACMP_INPUTSEL_NEGSEL_CAPSENSE, +#endif +} ACMP_Channel_TypeDef; +#endif + +#if defined(_ACMP_EXTIFCTRL_MASK) +/** + * ACMP external input select. This type is used to select which APORT is + * used by an external module, such as LESENSE, when it's taking control over + * the ACMP input. + */ +typedef enum { + acmpExternalInputAPORT0X = _ACMP_EXTIFCTRL_APORTSEL_APORT0X, /**< Select APORT0X as an external input. */ + acmpExternalInputAPORT0Y = _ACMP_EXTIFCTRL_APORTSEL_APORT0Y, /**< Select APORT0Y as an external input. */ + acmpExternalInputAPORT1X = _ACMP_EXTIFCTRL_APORTSEL_APORT1X, /**< Select APORT1X as an external input. */ + acmpExternalInputAPORT1Y = _ACMP_EXTIFCTRL_APORTSEL_APORT1Y, /**< Select APORT1Y as an external input. */ + acmpExternalInputAPORT1XY = _ACMP_EXTIFCTRL_APORTSEL_APORT1XY, /**< Select APORT1XY as an external input. */ + acmpExternalInputAPORT2X = _ACMP_EXTIFCTRL_APORTSEL_APORT2X, /**< Select APORT2X as an external input. */ + acmpExternalInputAPORT2Y = _ACMP_EXTIFCTRL_APORTSEL_APORT2Y, /**< Select APORT2Y as an external input. */ + acmpExternalInputAPORT2YX = _ACMP_EXTIFCTRL_APORTSEL_APORT2YX, /**< Select APORT2YX as an external input. */ + acmpExternalInputAPORT3X = _ACMP_EXTIFCTRL_APORTSEL_APORT3X, /**< Select APORT3X as an external input. */ + acmpExternalInputAPORT3Y = _ACMP_EXTIFCTRL_APORTSEL_APORT3Y, /**< Select APORT3Y as an external input. */ + acmpExternalInputAPORT3XY = _ACMP_EXTIFCTRL_APORTSEL_APORT3XY, /**< Select APORT3XY as an external input. */ + acmpExternalInputAPORT4X = _ACMP_EXTIFCTRL_APORTSEL_APORT4X, /**< Select APORT4X as an external input. */ + acmpExternalInputAPORT4Y = _ACMP_EXTIFCTRL_APORTSEL_APORT4Y, /**< Select APORT4Y as an external input. */ + acmpExternalInputAPORT4YX = _ACMP_EXTIFCTRL_APORTSEL_APORT4YX, /**< Select APORT4YX as an external input. */ +} ACMP_ExternalInput_Typedef; +#endif + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** Capsense initialization structure. */ +typedef struct { +#if defined(_ACMP_CTRL_FULLBIAS_MASK) + /** Full-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool fullBias; +#endif + +#if defined(_ACMP_CTRL_HALFBIAS_MASK) + /** Half-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool halfBias; +#endif + + /** Bias current. See the ACMP chapter about bias and response time in the + * reference manual for details. */ + uint32_t biasProg; + +#if defined(_ACMP_CTRL_WARMTIME_MASK) + /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be + * about 10 us in wall clock time. */ + ACMP_WarmTime_TypeDef warmTime; +#endif + +#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ + || defined(_ACMP_CFG_HYST_MASK) + /** Hysteresis level. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel; +#else + /** Hysteresis level when ACMP output is 0. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; + + /** Hysteresis level when ACMP output is 1. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; +#endif + + /** A resistor used in the capacitive sensing circuit. For values see + * the device data sheet. */ + ACMP_CapsenseResistor_TypeDef resistor; + +#if defined(_ACMP_INPUTSEL_LPREF_MASK) + /** Low-power reference enabled. This setting, if enabled, reduces the + * power used by VDD and bandgap references. */ + bool lowPowerReferenceEnabled; +#endif + +#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) + /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). + * Valid values are in the 0-63 range. */ + uint32_t vrefDiv; +#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) + /** VDD reference value. VDD_SCALED = (VDD * VDDLEVEL) / 63. + * Valid values are in the 0-63 range. */ + uint32_t vddLevel; +#else + /** + * This value configures the upper voltage threshold of the capsense + * oscillation rail. + * + * The voltage threshold is calculated as follows: + * VDD * (vddLevelHigh + 1) / 64 + */ + uint32_t vddLevelHigh; + + /** + * This value configures the lower voltage threshold of the capsense + * oscillation rail. + * + * The voltage threshold is calculated as follows: + * VDD * (vddLevelLow + 1) / 64 + */ + uint32_t vddLevelLow; +#endif + + /** If true, ACMP is enabled after configuration. */ + bool enable; +} ACMP_CapsenseInit_TypeDef; + +/** A default configuration for capacitive sense mode initialization. */ +#if defined(_ACMP_CFG_MASK) + +// PM5507: provide default configuration that is functional +/** Analog comparator CFG with initial bias value */ +#define PM5507_ACMP_CFG_BIAS_DEFAULT 0x00000004UL +/** Analog comparator reset value */ +#define PM5507_ACMP_CFG_RESETVALUE 0x00000004UL + +/** Capacitive sense mode configuration default values. */ +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ + acmpHysteresisDisabled, /* Disable hysteresis. */ \ + acmpResistor5, /* Use internal resistor value 5. */ \ + 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ + true /* Enable after init. */ \ + } +#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* Don't use fullBias to lower power consumption. */ \ + 0x20, /* Using biasProg value of 0x20 (32). */ \ + acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 0. */ \ + acmpHysteresisLevel8, /* Use hysteresis level 8 when ACMP output is 1. */ \ + acmpResistor5, /* Use internal resistor value 5. */ \ + 0x30, /* VDD level high. */ \ + 0x10, /* VDD level low. */ \ + true /* Enable after initialization. */ \ + } +#elif defined(_ACMP_CTRL_WARMTIME_MASK) +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + acmpWarmTime512, /* 512 cycle warmup to be safe */ \ + acmpHysteresisLevel5, \ + acmpResistor3, \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#else +#define ACMP_CAPSENSE_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + acmpHysteresisLevel5, \ + acmpResistor3, \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#endif + +/** ACMP initialization structure. */ +typedef struct { +#if defined(_ACMP_CTRL_FULLBIAS_MASK) + /** Full-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool fullBias; +#endif + +#if defined(_ACMP_CTRL_HALFBIAS_MASK) + /** Half-bias current. See the ACMP chapter about bias and response time in + * the reference manual for details. */ + bool halfBias; +#endif + + /** Bias current. See the ACMP chapter about bias and response time in the + * reference manual for details. Valid values are in the range 0-7. */ + uint32_t biasProg; + +#if defined(_ACMP_CTRL_IFALL_SHIFT) + /** Enable setting the interrupt flag on the falling edge. */ + bool interruptOnFallingEdge; +#endif +#if defined(_ACMP_CTRL_IRISE_SHIFT) + /** Enable setting the interrupt flag on the rising edge. */ + bool interruptOnRisingEdge; +#endif + +#if defined(_ACMP_CTRL_INPUTRANGE_MASK) \ + || defined(_ACMP_CFG_INPUTRANGE_MASK) + /** Input range. Adjust this setting to optimize the performance for a + * given input voltage range. */ + ACMP_InputRange_TypeDef inputRange; +#endif + +#if defined(_ACMP_CTRL_ACCURACY_MASK) \ + || defined(_ACMP_CFG_ACCURACY_MASK) + /** ACMP accuracy mode. Select the accuracy mode that matches the + * required current usage and accuracy requirement. Low accuracy + * consumes less current while high accuracy consumes more current. */ + ACMP_Accuracy_TypeDef accuracy; +#endif + +#if defined(_ACMP_CTRL_PWRSEL_MASK) + /** Select the power source for the ACMP. */ + ACMP_PowerSource_TypeDef powerSource; +#endif + +#if defined(_ACMP_CTRL_WARMTIME_MASK) + /** Warmup time, which is measured in HFPERCLK / HFPERCCLK cycles and should be + * about 10 us in wall clock time. */ + ACMP_WarmTime_TypeDef warmTime; +#endif + +#if defined(_ACMP_CTRL_HYSTSEL_MASK) \ + || defined(_ACMP_CFG_HYST_MASK) + /** Hysteresis level. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel; +#else + /** Hysteresis when ACMP output is 0. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_0; + + /** Hysteresis when ACMP output is 1. */ + ACMP_HysteresisLevel_TypeDef hysteresisLevel_1; +#endif + +#if defined(_ACMP_INPUTSEL_VLPSEL_MASK) + /** VLP Input source. Select between using VADIV or VBDIV as the VLP + * source. */ + ACMP_VLPInput_Typedef vlpInput; +#endif + + /** Inactive value emitted by ACMP during warmup. */ + bool inactiveValue; + +#if defined(_ACMP_INPUTSEL_LPREF_MASK) + /** Low power reference enabled. This setting, if enabled, reduces the + * power used by the VDD and bandgap references. */ + bool lowPowerReferenceEnabled; +#endif + +#if defined(_ACMP_INPUTCTRL_VREFDIV_MASK) + /** VDD division factor. VREFOUT = VREFIN * (VREFDIV / 63). + * Valid values are in the 0-63 range. */ + uint32_t vrefDiv; +#elif defined(_ACMP_INPUTSEL_VDDLEVEL_MASK) + /** VDD reference value. VDD_SCALED = VDD * VDDLEVEL * 50 mV/3.8 V. + * Valid values are in the 0-63 range. */ + uint32_t vddLevel; +#endif + + /** If true, ACMP is enabled after configuration. */ + bool enable; +} ACMP_Init_TypeDef; + +/** Default configuration for ACMP regular initialization. */ +#if defined(_ACMP_CFG_MASK) +#define ACMP_INIT_DEFAULT \ + { \ + PM5507_ACMP_CFG_BIAS_DEFAULT, /* Using biasProg default value. */ \ + acmpInputRangeFull, /* Input range from 0 to Vdd. */ \ + acmpAccuracyLow, /* Low accuracy, less current usage. */ \ + acmpHysteresisDisabled, /* Disable hysteresis. */ \ + false, /* Output 0 when ACMP is inactive. */ \ + 0x3F, /* Set VREFDIV to maximum to disable divide. */ \ + true /* Enable after init. */ \ + } +#elif defined(_ACMP_HYSTERESIS0_HYST_MASK) +#define ACMP_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + 0x7, /* biasProg */ \ + false, /* No interrupt on falling edge. */ \ + false, /* No interrupt on rising edge. */ \ + acmpInputRangeFull, /* Input range from 0 to VDD. */ \ + acmpAccuracyLow, /* Low accuracy, less current usage. */ \ + acmpPowerSourceAvdd, /* Use the AVDD supply. */ \ + acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 0 */ \ + acmpHysteresisLevel5, /* Use hysteresis level 5 when output is 1 */ \ + acmpVLPInputVADIV, /* Use VADIV as the VLP input source. */ \ + false, /* Output 0 when ACMP is inactive. */ \ + true /* Enable after init. */ \ + } +#else +#define ACMP_INIT_DEFAULT \ + { \ + false, /* fullBias */ \ + false, /* halfBias */ \ + 0x7, /* biasProg */ \ + false, /* No interrupt on falling edge. */ \ + false, /* No interrupt on rising edge. */ \ + acmpWarmTime512, /* 512 cycle warmup to be safe */ \ + acmpHysteresisLevel5, \ + false, /* Disabled emitting inactive value during warmup. */ \ + false, /* low power reference */ \ + 0x3D, /* VDD level */ \ + true /* Enable after init. */ \ + } +#endif + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/** VA Configuration structure. This structure is used to configure the + * VA voltage input source and its dividers. */ +typedef struct { + ACMP_VAInput_TypeDef input; /**< VA voltage input source */ + + /** + * A divider for VA voltage input source when ACMP output is 0. This value is + * used to divide the VA voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VA divided = VA input * (div0 + 1) / 64 + */ + uint32_t div0; + + /** + * A divider for VA voltage input source when ACMP output is 1. This value is + * used to divide the VA voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VA divided = VA input * (div1 + 1) / 64 + */ + uint32_t div1; +} ACMP_VAConfig_TypeDef; + +/** VA default configuration. */ +#define ACMP_VACONFIG_DEFAULT \ + { \ + acmpVAInputVDD, /* Use VDD as VA voltage input source. */ \ + 63, /* No division of the VA source when ACMP output is 0. */ \ + 63, /* No division of the VA source when ACMP output is 1. */ \ + } +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/** VB Configuration structure. This structure is used to configure the + * VB voltage input source and its dividers. */ +typedef struct { + ACMP_VBInput_TypeDef input; /**< VB Voltage input source */ + + /** + * A divider for VB voltage input source when ACMP output is 0. This value is + * used to divide the VB voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VB divided = VB input * (div0 + 1) / 64 + */ + uint32_t div0; + + /** + * A divider for VB voltage input source when ACMP output is 1. This value is + * used to divide the VB voltage input source by a specific value. The valid + * range is between 0 and 63. + * + * VB divided = VB input * (div1 + 1) / 64 + */ + uint32_t div1; +} ACMP_VBConfig_TypeDef; + +/** VB default configuration. */ +#define ACMP_VBCONFIG_DEFAULT \ + { \ + acmpVBInput1V25, /* Use 1.25 V as VB voltage input source. */ \ + 63, /* No division of the VB source when ACMP output is 0. */ \ + 63, /* No division of the VB source when ACMP output is 1. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init); +void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel); +void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, ACMP_Channel_TypeDef posSel); +void ACMP_Disable(ACMP_TypeDef *acmp); +void ACMP_Enable(ACMP_TypeDef *acmp); +#if defined(_ACMP_EXTIFCTRL_MASK) +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport); +#endif +#if defined(_GPIO_ACMP_ROUTEEN_MASK) +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, unsigned int pin, bool enable, bool invert); +#else +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert); +#endif +void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init); +void ACMP_Reset(ACMP_TypeDef *acmp); +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig); +#endif +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig); +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending ACMP interrupts. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * Pending ACMP interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IFC_EDGE or ACMP_IFC_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntClear(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IF_CLR = flags; +#else + acmp->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more ACMP interrupts. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntDisable(ACMP_TypeDef *acmp, uint32_t flags) +{ + BUS_RegMaskedClear(&(acmp->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Enable one or more ACMP interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using ACMP_IntClear() prior to enabling + * if a pending interrupt should be ignored. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the ACMP module. The flags can be, for instance, + * ACMP_IEN_EDGE or ACMP_IEN_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntEnable(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IEN_SET = flags; +#else + acmp->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending ACMP interrupt flags. + * + * @note + * This function does not clear event bits. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @return + * Pending ACMP interrupt sources. A bitwise logic OR combination of valid + * interrupt flags for the ACMP module. The pending interrupt sources can be, + * for instance, ACMP_IF_EDGE or ACMP_IF_WARMUP. + ******************************************************************************/ +__STATIC_INLINE uint32_t ACMP_IntGet(ACMP_TypeDef *acmp) +{ + return acmp->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending ACMP interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @note + * This function does not clear interrupt flags. + * + * @return + * Pending and enabled ACMP interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in ACMPx_IEN_nnn + * register (ACMPx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the ACMP module + * (ACMPx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t ACMP_IntGetEnabled(ACMP_TypeDef *acmp) +{ + uint32_t tmp; + + /* Store ACMPx->IEN in a temporary variable to define the explicit order + * of volatile accesses. */ + tmp = acmp->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return acmp->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending ACMP interrupts from software. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] flags + * ACMP interrupt sources to set as pending. Use a bitwise logic OR + * combination of valid interrupt flags for the ACMP module. The flags can be, + * for instance, ACMP_IFS_EDGE or ACMP_IFS_WARMUP. + ******************************************************************************/ +__STATIC_INLINE void ACMP_IntSet(ACMP_TypeDef *acmp, uint32_t flags) +{ +#if defined(ACMP_HAS_SET_CLEAR) + acmp->IF_SET = flags; +#else + acmp->IFS = flags; +#endif +} + +#if defined(_ACMP_INPUTCTRL_MASK) +/***************************************************************************//** + * @brief + * Convert GPIO port/pin to ACMP input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO pin + * + * @return + * ACMP input selection + ******************************************************************************/ +__STATIC_INLINE ACMP_Channel_TypeDef ACMP_PortPinToInput(GPIO_Port_TypeDef port, uint8_t pin) +{ + uint32_t input = (((uint32_t) port + (_ACMP_INPUTCTRL_POSSEL_PA0 >> 4)) << 4) | pin; + + return (ACMP_Channel_TypeDef) input; +} +#endif + +/** @} (end addtogroup acmp) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ +#endif /* EM_ACMP_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h index f3c14ac..bffa5c2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief Emlib peripheral API "assert" implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_ASSERT_H -#define EM_ASSERT_H - -#include "sl_assert.h" - -#endif /* EM_ASSERT_H */ +/***************************************************************************//** + * @file + * @brief Emlib peripheral API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_ASSERT_H +#define EM_ASSERT_H + +#include "sl_assert.h" + +#endif /* EM_ASSERT_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h index bd2583b..756e362 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h @@ -1,473 +1,473 @@ -/***************************************************************************//** - * @file - * @brief Backup Real Time Counter (BURTC) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_BURTC_H -#define EM_BURTC_H - -#include "em_device.h" -#if defined(BURTC_PRESENT) - -#include -#include "sl_assert.h" -#include "em_bus.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup burtc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** BURTC clock divisors. These values are valid for the BURTC prescaler. */ -#define burtcClkDiv_1 1 /**< Divide clock by 1. */ -#define burtcClkDiv_2 2 /**< Divide clock by 2. */ -#define burtcClkDiv_4 4 /**< Divide clock by 4. */ -#define burtcClkDiv_8 8 /**< Divide clock by 8. */ -#define burtcClkDiv_16 16 /**< Divide clock by 16. */ -#define burtcClkDiv_32 32 /**< Divide clock by 32. */ -#define burtcClkDiv_64 64 /**< Divide clock by 64. */ -#define burtcClkDiv_128 128 /**< Divide clock by 128. */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** BURTC clock selection. */ -typedef enum { - /** Ultra low frequency (1 kHz) clock. */ - burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, - /** Low frequency RC oscillator. */ - burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, - /** Low frequency crystal oscillator. */ - burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO -} BURTC_ClkSel_TypeDef; - -/** BURTC mode of operation. */ -typedef enum { - /** Disable BURTC */ - burtcModeDisable = BURTC_CTRL_MODE_DISABLE, - /** Enable and start BURTC counter in EM0 to EM2. */ - burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, - /** Enable and start BURTC counter in EM0 to EM3. */ - burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, - /** Enable and start BURTC counter in EM0 to EM4. */ - burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, -} BURTC_Mode_TypeDef; - -/** BURTC low power mode. */ -typedef enum { - /** Low Power Mode is disabled. */ - burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, - /** Low Power Mode is always enabled. */ - burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, - /** Low Power Mode when system enters backup mode. */ - burtcLPBU = BURTC_LPMODE_LPMODE_BUEN -} BURTC_LP_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** BURTC initialization structure for Series 0 devices. */ -typedef struct { - bool enable; /**< Enable BURTC after initialization (starts counter). */ - - BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ - bool debugRun; /**< If true, counter will keep running under debug halt. */ - BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ - uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ - - uint32_t lowPowerComp; /**< Number of least significant clock bits to ignore in low power mode. */ - bool timeStamp; /**< Enable time stamp on entering backup power domain. */ - - bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ - - BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ -} BURTC_Init_TypeDef; - -/** Default configuration for BURTC initialization structure. */ -#define BURTC_INIT_DEFAULT \ - { \ - true, \ - burtcModeEM2, \ - false, \ - burtcClkSelULFRCO, \ - burtcClkDiv_1, \ - 0, \ - true, \ - false, \ - burtcLPDisable, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) -/** BURTC initialization structure for Series 2 devices. */ -typedef struct { - bool start; /**< Start BURTC after initialization */ - bool debugRun; /**< If true, counter will keep running under debug halt */ - uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ - bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ - bool em4comp; /**< Enable EM4 wakeup on compare match. */ - bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ -} BURTC_Init_TypeDef; - -/** Default configuration for BURTC init structure */ -#define BURTC_INIT_DEFAULT \ - { \ - true, \ - false, \ - 1, \ - 0, \ - false, \ - false, \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Clear one or more pending BURTC interrupts. - * - * @param[in] flags - * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed - * together to clear multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntClear(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IF_CLR = flags; -#else - BURTC->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more BURTC interrupts. - * - * @param[in] flags - * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed - * together to disable multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntDisable(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IEN_CLR = flags; -#else - BURTC->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more BURTC interrupts. - * - * @note - * Depending on use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling - * if a pending interrupt should be ignored. - * - * @param[in] flags - * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed - * together to set multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntEnable(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IEN_SET = flags; -#else - BURTC->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending BURTC interrupt flags. - * - * @note - * This function does not clear the event bits. - * - * @return - * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed - * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_IntGet(void) -{ - return BURTC->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending BURTC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * Pending BURTC interrupt sources that is also enabled. Returns a set of - * interrupt flags OR-ed together for multiple interrupt sources in the - * BURTC module (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) -{ - uint32_t tmp; - - /* Get enabled interrupts */ - tmp = BURTC->IEN; - - /* Return set interrupts */ - return BURTC->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending BURTC interrupts from SW. - * - * @param[in] flags - * BURTC interrupt sources to set to pending. Use a set of interrupt flags - * OR-ed together to set multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntSet(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IF_SET = flags; -#else - BURTC->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Status of BURTC RAM, timestamp and LP Mode - * - * @return A mask logically OR-ed status bits - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_Status(void) -{ - return BURTC->STATUS; -} - -#if defined(BURTC_CMD_CLRSTATUS) -/***************************************************************************//** - * @brief - * Clear and reset BURTC status register - ******************************************************************************/ -__STATIC_INLINE void BURTC_StatusClear(void) -{ - BURTC->CMD = BURTC_CMD_CLRSTATUS; -} -#endif - -/***************************************************************************//** - * @brief - * Wait for the BURTC to complete all synchronization of register changes - * and commands. - ******************************************************************************/ -__STATIC_INLINE void BURTC_SyncWait(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { - /* Wait for previous synchronization to finish */ - } -#else - while (BURTC->SYNCBUSY != 0U) { - /* Wait for previous synchronization to finish */ - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Start BURTC counter. - * - * This function will send a start command to the BURTC peripheral. The BURTC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref BURTC_SyncWait() function can be used to wait for the start command - * to be executed. - * - * @note - * This function requires the BURTC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Start(void) -{ - BURTC_SyncWait(); - BURTC->CMD = BURTC_CMD_START; -} - -/***************************************************************************//** - * @brief - * Stop the BURTC counter. - * - * This function will send a stop command to the BURTC peripheral. The BURTC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref BURTC_SyncWait() function can be used to wait for the stop command - * to be executed. - * - * @note - * This function requires the BURTC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Stop(void) -{ - BURTC_SyncWait(); - BURTC->CMD = BURTC_CMD_STOP; -} -#endif - -/***************************************************************************//** - * @brief Get BURTC counter. - * - * @return - * BURTC counter value - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_CounterGet(void) -{ - return BURTC->CNT; -} - -#if defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief Get BURTC timestamp for entering BU. - * - * @return - * BURTC Time Stamp value - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_TimestampGet(void) -{ - return BURTC->TIMESTAMP; -} - -/***************************************************************************//** - * @brief Freeze register updates until enabled. - * @param[in] enable If true, registers are not updated until enabled again. - ******************************************************************************/ -__STATIC_INLINE void BURTC_FreezeEnable(bool enable) -{ - BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); -} - -/***************************************************************************//** - * @brief Shut down power to retention register bank. - * @param[in] enable - * If true, shuts off power to retention registers. - * @note - * When power retention is disabled, it can't be enabled again (until - * reset). - ******************************************************************************/ -__STATIC_INLINE void BURTC_Powerdown(bool enable) -{ - BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); -} - -/***************************************************************************//** - * @brief - * Set a value in one of the retention registers. - * - * @param[in] num - * Register to set - * @param[in] data - * Value to put into register - ******************************************************************************/ -__STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) -{ - EFM_ASSERT(num <= 127); - - BURTC->RET[num].REG = data; -} - -/***************************************************************************//** - * @brief - * Read a value from one of the retention registers. - * - * @param[in] num - * Retention Register to read - * - * @return - * Value of the retention register - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) -{ - EFM_ASSERT(num <= 127); - - return BURTC->RET[num].REG; -} -#endif - -/***************************************************************************//** - * @brief - * Lock BURTC registers, which will protect from writing new config settings. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Lock(void) -{ - BURTC->LOCK = 0x0; -} - -/***************************************************************************//** - * @brief - * Unlock BURTC registers, which will enable write access to change configuration. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Unlock(void) -{ - BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; -} - -void BURTC_Reset(void); -void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); -void BURTC_Enable(bool enable); -void BURTC_CounterReset(void); -void BURTC_CompareSet(unsigned int comp, uint32_t value); -uint32_t BURTC_CompareGet(unsigned int comp); -#if defined(_BURTC_CTRL_MASK) -uint32_t BURTC_ClockFreqGet(void); -#endif - -/** @} (end addtogroup burtc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* BURTC_PRESENT */ -#endif /* EM_BURTC_H */ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BURTC_H +#define EM_BURTC_H + +#include "em_device.h" +#if defined(BURTC_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup burtc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** BURTC clock divisors. These values are valid for the BURTC prescaler. */ +#define burtcClkDiv_1 1 /**< Divide clock by 1. */ +#define burtcClkDiv_2 2 /**< Divide clock by 2. */ +#define burtcClkDiv_4 4 /**< Divide clock by 4. */ +#define burtcClkDiv_8 8 /**< Divide clock by 8. */ +#define burtcClkDiv_16 16 /**< Divide clock by 16. */ +#define burtcClkDiv_32 32 /**< Divide clock by 32. */ +#define burtcClkDiv_64 64 /**< Divide clock by 64. */ +#define burtcClkDiv_128 128 /**< Divide clock by 128. */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC clock selection. */ +typedef enum { + /** Ultra low frequency (1 kHz) clock. */ + burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, + /** Low frequency RC oscillator. */ + burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, + /** Low frequency crystal oscillator. */ + burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO +} BURTC_ClkSel_TypeDef; + +/** BURTC mode of operation. */ +typedef enum { + /** Disable BURTC */ + burtcModeDisable = BURTC_CTRL_MODE_DISABLE, + /** Enable and start BURTC counter in EM0 to EM2. */ + burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, + /** Enable and start BURTC counter in EM0 to EM3. */ + burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, + /** Enable and start BURTC counter in EM0 to EM4. */ + burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, +} BURTC_Mode_TypeDef; + +/** BURTC low power mode. */ +typedef enum { + /** Low Power Mode is disabled. */ + burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, + /** Low Power Mode is always enabled. */ + burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, + /** Low Power Mode when system enters backup mode. */ + burtcLPBU = BURTC_LPMODE_LPMODE_BUEN +} BURTC_LP_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC initialization structure for Series 0 devices. */ +typedef struct { + bool enable; /**< Enable BURTC after initialization (starts counter). */ + + BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ + bool debugRun; /**< If true, counter will keep running under debug halt. */ + BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ + uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ + + uint32_t lowPowerComp; /**< Number of least significant clock bits to ignore in low power mode. */ + bool timeStamp; /**< Enable time stamp on entering backup power domain. */ + + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ + + BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC initialization structure. */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + burtcModeEM2, \ + false, \ + burtcClkSelULFRCO, \ + burtcClkDiv_1, \ + 0, \ + true, \ + false, \ + burtcLPDisable, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) +/** BURTC initialization structure for Series 2 devices. */ +typedef struct { + bool start; /**< Start BURTC after initialization */ + bool debugRun; /**< If true, counter will keep running under debug halt */ + uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ + bool em4comp; /**< Enable EM4 wakeup on compare match. */ + bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC init structure */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + false, \ + 1, \ + 0, \ + false, \ + false, \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Clear one or more pending BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntClear(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_CLR = flags; +#else + BURTC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntDisable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_CLR = flags; +#else + BURTC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more BURTC interrupts. + * + * @note + * Depending on use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling + * if a pending interrupt should be ignored. + * + * @param[in] flags + * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntEnable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_SET = flags; +#else + BURTC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending BURTC interrupt flags. + * + * @note + * This function does not clear the event bits. + * + * @return + * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed + * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGet(void) +{ + return BURTC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending BURTC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending BURTC interrupt sources that is also enabled. Returns a set of + * interrupt flags OR-ed together for multiple interrupt sources in the + * BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Get enabled interrupts */ + tmp = BURTC->IEN; + + /* Return set interrupts */ + return BURTC->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending BURTC interrupts from SW. + * + * @param[in] flags + * BURTC interrupt sources to set to pending. Use a set of interrupt flags + * OR-ed together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntSet(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_SET = flags; +#else + BURTC->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Status of BURTC RAM, timestamp and LP Mode + * + * @return A mask logically OR-ed status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_Status(void) +{ + return BURTC->STATUS; +} + +#if defined(BURTC_CMD_CLRSTATUS) +/***************************************************************************//** + * @brief + * Clear and reset BURTC status register + ******************************************************************************/ +__STATIC_INLINE void BURTC_StatusClear(void) +{ + BURTC->CMD = BURTC_CMD_CLRSTATUS; +} +#endif + +/***************************************************************************//** + * @brief + * Wait for the BURTC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +__STATIC_INLINE void BURTC_SyncWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (BURTC->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start BURTC counter. + * + * This function will send a start command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the start command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Start(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_START; +} + +/***************************************************************************//** + * @brief + * Stop the BURTC counter. + * + * This function will send a stop command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the stop command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Stop(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_STOP; +} +#endif + +/***************************************************************************//** + * @brief Get BURTC counter. + * + * @return + * BURTC counter value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_CounterGet(void) +{ + return BURTC->CNT; +} + +#if defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief Get BURTC timestamp for entering BU. + * + * @return + * BURTC Time Stamp value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_TimestampGet(void) +{ + return BURTC->TIMESTAMP; +} + +/***************************************************************************//** + * @brief Freeze register updates until enabled. + * @param[in] enable If true, registers are not updated until enabled again. + ******************************************************************************/ +__STATIC_INLINE void BURTC_FreezeEnable(bool enable) +{ + BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief Shut down power to retention register bank. + * @param[in] enable + * If true, shuts off power to retention registers. + * @note + * When power retention is disabled, it can't be enabled again (until + * reset). + ******************************************************************************/ +__STATIC_INLINE void BURTC_Powerdown(bool enable) +{ + BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Set a value in one of the retention registers. + * + * @param[in] num + * Register to set + * @param[in] data + * Value to put into register + ******************************************************************************/ +__STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) +{ + EFM_ASSERT(num <= 127); + + BURTC->RET[num].REG = data; +} + +/***************************************************************************//** + * @brief + * Read a value from one of the retention registers. + * + * @param[in] num + * Retention Register to read + * + * @return + * Value of the retention register + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) +{ + EFM_ASSERT(num <= 127); + + return BURTC->RET[num].REG; +} +#endif + +/***************************************************************************//** + * @brief + * Lock BURTC registers, which will protect from writing new config settings. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Lock(void) +{ + BURTC->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock BURTC registers, which will enable write access to change configuration. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Unlock(void) +{ + BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; +} + +void BURTC_Reset(void); +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); +void BURTC_Enable(bool enable); +void BURTC_CounterReset(void); +void BURTC_CompareSet(unsigned int comp, uint32_t value); +uint32_t BURTC_CompareGet(unsigned int comp); +#if defined(_BURTC_CTRL_MASK) +uint32_t BURTC_ClockFreqGet(void); +#endif + +/** @} (end addtogroup burtc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* BURTC_PRESENT */ +#endif /* EM_BURTC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h index 6b2e977..9ae27b4 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h @@ -1,341 +1,341 @@ -/***************************************************************************//** - * @file - * @brief RAM and peripheral bit-field set and clear API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_BUS_H -#define EM_BUS_H - -#include "sl_assert.h" -#include "em_core.h" -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup bus BUS - Bitfield Read/Write - * @brief BUS register and RAM bit/field read/write API - * @details - * API to perform bit-band and field set/clear access to RAM and peripherals. - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Perform a single-bit write operation on a 32-bit word in RAM. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read-modify-write operation on a single bit write on a 32-bit word in RAM. - * See the reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. Bit- - * banding is a multi cycle read-modify-write bus operation. RAM bit-banding is - * performed using the memory alias region at BITBAND_RAM_BASE. - * - * @param[in] addr An ddress of a 32-bit word in RAM. - * - * @param[in] bit A bit position to write, 0-31. - * - * @param[in] val A value to set bit to, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, - unsigned int bit, - unsigned int val) -{ -#if defined(BITBAND_RAM_BASE) - uint32_t aliasAddr = - BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - *(volatile uint32_t *)aliasAddr = (uint32_t)val; -#else - uint32_t tmp = *addr; - - /* Make sure val is not more than 1 because only one bit needs to be set. */ - *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit read operation on a 32-bit word in RAM. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. - * RAM bit-banding is performed using the memory alias region - * at BITBAND_RAM_BASE. - * - * @param[in] addr RAM address. - * - * @param[in] bit A bit position to read, 0-31. - * - * @return - * The requested bit shifted to bit position 0 in the return value. - ******************************************************************************/ -__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, - unsigned int bit) -{ -#if defined(BITBAND_RAM_BASE) - uint32_t aliasAddr = - BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - return *(volatile uint32_t *)aliasAddr; -#else - return ((*addr) >> bit) & 1UL; -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit write operation on a peripheral register. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read-modify-write operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. Bit- - * banding is a multi cycle read-modify-write bus operation. Peripheral register - * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] bit A bit position to write, 0-31. - * - * @param[in] val A value to set bit to, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, - unsigned int bit, - unsigned int val) -{ - EFM_ASSERT(bit < 32U); -#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) - uint32_t aliasAddr; - if (val != 0U) { - aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; - } else { - aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; - } - *(volatile uint32_t *)aliasAddr = 1UL << bit; -#elif defined(BITBAND_PER_BASE) - uint32_t aliasAddr = - BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - *(volatile uint32_t *)aliasAddr = (uint32_t)val; -#else - uint32_t tmp = *addr; - - /* Make sure val is not more than 1 because only one bit needs to be set. */ - *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit read operation on a peripheral register. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. - * Peripheral register bit-banding is performed using the memory alias - * region at BITBAND_PER_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] bit A bit position to read, 0-31. - * - * @return - * The requested bit shifted to bit position 0 in the return value. - ******************************************************************************/ -__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, - unsigned int bit) -{ -#if defined(BITBAND_PER_BASE) - uint32_t aliasAddr = - BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); - - return *(volatile uint32_t *)aliasAddr; -#else - return ((*addr) >> bit) & 1UL; -#endif -} - -/***************************************************************************//** - * @brief - * Perform a masked set operation on a peripheral register address. - * - * @details - * A peripheral register masked set provides a single-cycle and atomic set - * operation of a bit-mask in a peripheral register. All 1s in the mask are - * set to 1 in the register. All 0s in the mask are not changed in the - * register. - * RAMs and special peripherals are not supported. See the - * reference manual for more details about the peripheral register field set. - * - * @note - * This function is single-cycle and atomic on cores with peripheral bit set - * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A mask to set. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, - uint32_t mask) -{ -#if defined(PER_REG_BLOCK_SET_OFFSET) - uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; - *(volatile uint32_t *)aliasAddr = mask; -#elif defined(PER_BITSET_MEM_BASE) - uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); - *(volatile uint32_t *)aliasAddr = mask; -#else - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr |= mask; - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a masked clear operation on the peripheral register address. - * - * @details - * A peripheral register masked clear provides a single-cycle and atomic clear - * operation of a bit-mask in a peripheral register. All 1s in the mask are - * set to 0 in the register. - * All 0s in the mask are not changed in the register. - * RAMs and special peripherals are not supported. See the - * reference manual for more details about the peripheral register field clear. - * - * @note - * This function is single-cycle and atomic on cores with peripheral bit set - * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A mask to clear. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, - uint32_t mask) -{ -#if defined(PER_REG_BLOCK_CLR_OFFSET) - uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; - *(volatile uint32_t *)aliasAddr = mask; -#elif defined(PER_BITCLR_MEM_BASE) - uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); - *(volatile uint32_t *)aliasAddr = mask; -#else - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr &= ~mask; - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Perform peripheral register masked write. - * - * @details - * This function first reads the peripheral register and updates only bits - * that are set in the mask with content of val. Typically, the mask is a - * bit-field in the register and the value val is within the mask. - * - * @note - * The read-modify-write operation is executed in a critical section to - * guarantee atomicity. Note that atomicity can only be guaranteed if register - * is modified only by the core, and not by other peripherals (like DMA). - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A peripheral register mask. - * - * @param[in] val A peripheral register value. The value must be shifted to the - correct bit position in the register corresponding to the field - defined by the mask parameter. The register value must be - contained in the field defined by the mask parameter. The - register value is masked to prevent involuntary spillage. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, - uint32_t mask, - uint32_t val) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr = (*addr & ~mask) | (val & mask); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * @brief - * Perform a peripheral register masked read. - * - * @details - * Read an unshifted and masked value from a peripheral register. - * - * @note - * This operation is not hardware accelerated. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A peripheral register mask. - * - * @return - * An unshifted and masked register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, - uint32_t mask) -{ - return *addr & mask; -} - -/** @} (end addtogroup bus) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_BUS_H */ +/***************************************************************************//** + * @file + * @brief RAM and peripheral bit-field set and clear API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BUS_H +#define EM_BUS_H + +#include "sl_assert.h" +#include "em_core.h" +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup bus BUS - Bitfield Read/Write + * @brief BUS register and RAM bit/field read/write API + * @details + * API to perform bit-band and field set/clear access to RAM and peripherals. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single bit write on a 32-bit word in RAM. + * See the reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. RAM bit-banding is + * performed using the memory alias region at BITBAND_RAM_BASE. + * + * @param[in] addr An ddress of a 32-bit word in RAM. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * RAM bit-banding is performed using the memory alias region + * at BITBAND_RAM_BASE. + * + * @param[in] addr RAM address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. Peripheral register + * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ + EFM_ASSERT(bit < 32U); +#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr; + if (val != 0U) { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + } else { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + } + *(volatile uint32_t *)aliasAddr = 1UL << bit; +#elif defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * Peripheral register bit-banding is performed using the memory alias + * region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked set operation on a peripheral register address. + * + * @details + * A peripheral register masked set provides a single-cycle and atomic set + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 1 in the register. All 0s in the mask are not changed in the + * register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field set. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to set. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_SET_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITSET_MEM_BASE) + uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr |= mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked clear operation on the peripheral register address. + * + * @details + * A peripheral register masked clear provides a single-cycle and atomic clear + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 0 in the register. + * All 0s in the mask are not changed in the register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field clear. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to clear. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITCLR_MEM_BASE) + uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr &= ~mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform peripheral register masked write. + * + * @details + * This function first reads the peripheral register and updates only bits + * that are set in the mask with content of val. Typically, the mask is a + * bit-field in the register and the value val is within the mask. + * + * @note + * The read-modify-write operation is executed in a critical section to + * guarantee atomicity. Note that atomicity can only be guaranteed if register + * is modified only by the core, and not by other peripherals (like DMA). + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @param[in] val A peripheral register value. The value must be shifted to the + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. The + register value is masked to prevent involuntary spillage. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, + uint32_t mask, + uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr = (*addr & ~mask) | (val & mask); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Perform a peripheral register masked read. + * + * @details + * Read an unshifted and masked value from a peripheral register. + * + * @note + * This operation is not hardware accelerated. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @return + * An unshifted and masked register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, + uint32_t mask) +{ + return *addr & mask; +} + +/** @} (end addtogroup bus) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_BUS_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h index 1de476a..27b559d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h @@ -1,462 +1,462 @@ -/***************************************************************************//** - * @file - * @brief Chip Errata Workarounds - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CHIP_H -#define EM_CHIP_H - -#include "em_device.h" -#include "sl_common.h" -#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2) -#include "em_system.h" -#endif -#include "em_bus.h" - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#include "em_gpio.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup chip CHIP - Chip Errata Workarounds - * @brief Chip errata workaround APIs - * @details - * API to apply chip errata workarounds at initialization and reset. - * @{ - ******************************************************************************/ - -/**************************************************************************//** - * @brief - * Chip initialization routine for revision errata workarounds. - * - * @note - * This function must be called immediately in main(). - * - * This initialization function configures the device to a state - * as similar to later revisions as possible to improve software compatibility - * with newer parts. See the device-specific errata for details. - *****************************************************************************/ -__STATIC_INLINE void CHIP_Init(void) -{ -#if defined(MSC_CACHECMD_INVCACHE) - MSC->CACHECMD = MSC_CACHECMD_INVCACHE; -#elif defined(MSC_CMD_INVCACHE) - MSC->CMD = MSC_CMD_INVCACHE; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) - uint32_t rev; - SYSTEM_ChipRevision_TypeDef chipRev; - volatile uint32_t *reg; - - rev = *(volatile uint32_t *)(0x0FE081FC); - /* Engineering Sample calibration setup. */ - if ((rev >> 24) == 0) { - reg = (volatile uint32_t *)0x400CA00C; - *reg &= ~(0x70UL); - /* DREG */ - reg = (volatile uint32_t *)0x400C6020; - *reg &= ~(0xE0000000UL); - *reg |= ~(7UL << 25); - } - if ((rev >> 24) <= 3) { - /* DREG */ - reg = (volatile uint32_t *)0x400C6020; - *reg &= ~(0x00001F80UL); - /* Update CMU reset values. */ - reg = (volatile uint32_t *)0x400C8040; - *reg = 0; - reg = (volatile uint32_t *)0x400C8044; - *reg = 0; - reg = (volatile uint32_t *)0x400C8058; - *reg = 0; - reg = (volatile uint32_t *)0x400C8060; - *reg = 0; - reg = (volatile uint32_t *)0x400C8078; - *reg = 0; - } - - SYSTEM_ChipRevisionGet(&chipRev); - if (chipRev.major == 0x01) { - /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ - /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ - if (chipRev.minor == 00) { - reg = (volatile uint32_t *)0x400C8040; - *reg |= 0x2; - } - - /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ - /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ - /* later chip revisions and is only needed for rev A+B. */ - if (chipRev.minor <= 0x01) { - reg = (volatile uint32_t *)0x400C8044; - *reg |= 0x1; - } - } - /* Ensure correct ADC/DAC calibration value. */ - rev = *(volatile uint32_t *)0x0FE081F0; - if (rev < 0x4C8ABA00) { - uint32_t cal; - - /* Enable ADC/DAC clocks. */ - reg = (volatile uint32_t *)0x400C8044UL; - *reg |= (1 << 14 | 1 << 11); - - /* Retrive calibration values. */ - cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) - >> 8) << 24; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) - >> 0) << 16; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) - >> 8) << 8; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) - >> 0) << 0; - - /* ADC0->CAL = 1.25 reference. */ - reg = (volatile uint32_t *)0x40002034UL; - *reg = cal; - - /* DAC0->CAL = 1.25 reference. */ - reg = (volatile uint32_t *)(0x4000402CUL); - cal = *(volatile uint32_t *)0x0FE081C8UL; - *reg = cal; - - /* Turn off ADC/DAC clocks. */ - reg = (volatile uint32_t *)0x400C8044UL; - *reg &= ~(1 << 14 | 1 << 11); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) - - /****************************/ - /* Fix for errata CMU_E113. */ - - uint8_t prodRev; - SYSTEM_ChipRevision_TypeDef chipRev; - - prodRev = SYSTEM_GetProdRev(); - SYSTEM_ChipRevisionGet(&chipRev); - - // All Giant and Leopard parts except Leopard Rev E - if ((prodRev >= 16) && (chipRev.minor >= 3) - && !((chipRev.major == 2) && (chipRev.minor == 4))) { - /* This fixes an issue with the LFXO on high temperatures. */ - *(volatile uint32_t*)0x400C80C0 = - (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - - uint8_t prodRev; - prodRev = SYSTEM_GetProdRev(); - - if (prodRev <= 129) { - /* This fixes a mistaken internal connection between PC0 and PC4. */ - /* This disables an internal pull-down on PC4. */ - *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); - /* This disables an internal LDO test signal driving PC4. */ - *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); - } -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - - /**************************** - * Fixes for errata GPIO_E201 (slewrate) and - * HFXO high-temperature oscillator startup robustness fix. */ - - uint32_t port; - uint32_t clkEn; - uint8_t prodRev; - const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) - | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); - const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE - & ~(_GPIO_P_CTRL_SLEWRATE_MASK - | _GPIO_P_CTRL_SLEWRATEALT_MASK); - - prodRev = SYSTEM_GetProdRev(); - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - /* This errata is fixed in hardware from PRODREV 0x8F. */ - if (prodRev < 0x8F) { - /* Fixes for errata GPIO_E201 (slewrate). */ - - /* Save HFBUSCLK enable state and enable GPIO clock. */ - clkEn = CMU->HFBUSCLKEN0; - CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; - - /* Update slewrate. */ - for (port = 0; port <= GPIO_PORT_MAX; port++) { - GPIO->P[port].CTRL = setVal | resetVal; - } - - /* Restore HFBUSCLK enable state. */ - CMU->HFBUSCLKEN0 = clkEn; - } - - /* This errata is fixed in hardware from PRODREV 0x90. */ - if (prodRev < 0x90) { - /* HFXO high-temperature oscillator startup robustness fix. */ - CMU->HFXOSTARTUPCTRL = - (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) - | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - } - - if (chipRev.major == 0x01) { - /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ - *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; - } - - /**************************** - * Fix for errata DCDC_E206. - * Disable bypass limit enabled temporarily in SystemInit() errata - * workaround. */ - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - uint8_t prodRev = SYSTEM_GetProdRev(); - - /* EM2 current fixes for early samples. */ - if (prodRev == 0U) { - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; - *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; - } - if (prodRev < 2U) { - *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); - } - - /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ - CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) - | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES - | CMU_LFRCOCTRL_ENVREF; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) - MSC->CTRL |= 0x1UL << 8; -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if ((chipRev.major > 1) || (chipRev.minor >= 3)) { - /* PLFRCO trim values */ - *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608; - *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250; - *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118; - *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400; - } -#endif - -/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ -#if defined(_LCD_DISPCTRL_CHGRDST_MASK) -#if defined(_SILICON_LABS_32B_SERIES_1) - CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; - CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; - *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); - CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; - CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ - && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) - /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur - * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */ - *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { - /* Change HFXO default peak detector settings. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) - | 0x00178500U; - /* Change HFXO low power control settings. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) - | 0x0000C000U; - /* Change default SQBUF bias current. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; - } - - if (chipRev.major == 0x01 && chipRev.minor == 0x0) { - /* Trigger RAM read for each RAM instance */ - volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; - for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { - // Force memory read - *dmem; - dmem += (DMEM_BANK0_SIZE / 4U); - } - } - - /* Set TRACE clock to intended reset value. */ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) - | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) -#if defined(SL_TRUSTZONE_SECURE) -#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL) -#else -#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL) -#endif -#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL) - if (SYSTEM_GetProdRev() == 1) { - bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0; - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; - /* Enable HFRCO CLKOUT0. */ - *(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0; - if (hfrcoClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; - } - } -#endif - -/* PM-3503 */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) - { - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - - bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); - DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; - - while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { - /* Wait for previous synchronization to finish */ - } - - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { - /* Wait for BYPASS switch enable. */ - } - - if (dcdcIsLock) { - DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; - } - - if (dcdcClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - } -#endif - -/* PM-5163 */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \ - && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if (chipRev.major == 0x01 && chipRev.minor == 0x00) { - bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0; - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; - - *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) - | 0x0C000000UL; - - if (hfxo0ClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; - } - } -#endif -} - -/**************************************************************************//** - * @brief - * Chip reset routine with errata workarounds. - * - * @note - * This function should be called to reset the chip. It does not return. - * - * This function applies any errata workarounds needed to cleanly reset the - * device and then performs a system reset. See the device-specific errata for - * details. - *****************************************************************************/ -__STATIC_INLINE void CHIP_Reset(void) -{ -#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - /**************************** - * Workaround for errata DCDC_E206. - * Disable radio interference minimization features when resetting */ - - // Ensure access to EMU registers - EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; - - // No need to do anything if the DCDC is not powering DVDD - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { - // Make sure radio cannot accidentally re-enable features - *(volatile uint32_t *)(0x40084040UL) = 0x1UL; - - // If DCDC is in use, disable features - uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; - if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) - || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) { - BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); - BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); - } - } -#endif - - NVIC_SystemReset(); -} - -/** @} (end addtogroup chip) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_CHIP_H */ +/***************************************************************************//** + * @file + * @brief Chip Errata Workarounds + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CHIP_H +#define EM_CHIP_H + +#include "em_device.h" +#include "sl_common.h" +#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2) +#include "em_system.h" +#endif +#include "em_bus.h" + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#include "em_gpio.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup chip CHIP - Chip Errata Workarounds + * @brief Chip errata workaround APIs + * @details + * API to apply chip errata workarounds at initialization and reset. + * @{ + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Chip initialization routine for revision errata workarounds. + * + * @note + * This function must be called immediately in main(). + * + * This initialization function configures the device to a state + * as similar to later revisions as possible to improve software compatibility + * with newer parts. See the device-specific errata for details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Init(void) +{ +#if defined(MSC_CACHECMD_INVCACHE) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#elif defined(MSC_CMD_INVCACHE) + MSC->CMD = MSC_CMD_INVCACHE; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) + uint32_t rev; + SYSTEM_ChipRevision_TypeDef chipRev; + volatile uint32_t *reg; + + rev = *(volatile uint32_t *)(0x0FE081FC); + /* Engineering Sample calibration setup. */ + if ((rev >> 24) == 0) { + reg = (volatile uint32_t *)0x400CA00C; + *reg &= ~(0x70UL); + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0xE0000000UL); + *reg |= ~(7UL << 25); + } + if ((rev >> 24) <= 3) { + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0x00001F80UL); + /* Update CMU reset values. */ + reg = (volatile uint32_t *)0x400C8040; + *reg = 0; + reg = (volatile uint32_t *)0x400C8044; + *reg = 0; + reg = (volatile uint32_t *)0x400C8058; + *reg = 0; + reg = (volatile uint32_t *)0x400C8060; + *reg = 0; + reg = (volatile uint32_t *)0x400C8078; + *reg = 0; + } + + SYSTEM_ChipRevisionGet(&chipRev); + if (chipRev.major == 0x01) { + /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ + /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ + if (chipRev.minor == 00) { + reg = (volatile uint32_t *)0x400C8040; + *reg |= 0x2; + } + + /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ + /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ + /* later chip revisions and is only needed for rev A+B. */ + if (chipRev.minor <= 0x01) { + reg = (volatile uint32_t *)0x400C8044; + *reg |= 0x1; + } + } + /* Ensure correct ADC/DAC calibration value. */ + rev = *(volatile uint32_t *)0x0FE081F0; + if (rev < 0x4C8ABA00) { + uint32_t cal; + + /* Enable ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg |= (1 << 14 | 1 << 11); + + /* Retrive calibration values. */ + cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 24; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 16; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 8; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 0; + + /* ADC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)0x40002034UL; + *reg = cal; + + /* DAC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)(0x4000402CUL); + cal = *(volatile uint32_t *)0x0FE081C8UL; + *reg = cal; + + /* Turn off ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg &= ~(1 << 14 | 1 << 11); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; + SYSTEM_ChipRevision_TypeDef chipRev; + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevisionGet(&chipRev); + + // All Giant and Leopard parts except Leopard Rev E + if ((prodRev >= 16) && (chipRev.minor >= 3) + && !((chipRev.major == 2) && (chipRev.minor == 4))) { + /* This fixes an issue with the LFXO on high temperatures. */ + *(volatile uint32_t*)0x400C80C0 = + (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); + + if (prodRev <= 129) { + /* This fixes a mistaken internal connection between PC0 and PC4. */ + /* This disables an internal pull-down on PC4. */ + *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); + /* This disables an internal LDO test signal driving PC4. */ + *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); + } +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /**************************** + * Fixes for errata GPIO_E201 (slewrate) and + * HFXO high-temperature oscillator startup robustness fix. */ + + uint32_t port; + uint32_t clkEn; + uint8_t prodRev; + const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) + | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); + const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK); + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + /* This errata is fixed in hardware from PRODREV 0x8F. */ + if (prodRev < 0x8F) { + /* Fixes for errata GPIO_E201 (slewrate). */ + + /* Save HFBUSCLK enable state and enable GPIO clock. */ + clkEn = CMU->HFBUSCLKEN0; + CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; + + /* Update slewrate. */ + for (port = 0; port <= GPIO_PORT_MAX; port++) { + GPIO->P[port].CTRL = setVal | resetVal; + } + + /* Restore HFBUSCLK enable state. */ + CMU->HFBUSCLKEN0 = clkEn; + } + + /* This errata is fixed in hardware from PRODREV 0x90. */ + if (prodRev < 0x90) { + /* HFXO high-temperature oscillator startup robustness fix. */ + CMU->HFXOSTARTUPCTRL = + (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) + | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + } + + if (chipRev.major == 0x01) { + /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ + *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; + } + + /**************************** + * Fix for errata DCDC_E206. + * Disable bypass limit enabled temporarily in SystemInit() errata + * workaround. */ + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + uint8_t prodRev = SYSTEM_GetProdRev(); + + /* EM2 current fixes for early samples. */ + if (prodRev == 0U) { + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; + } + if (prodRev < 2U) { + *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1UL << 8; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if ((chipRev.major > 1) || (chipRev.minor >= 3)) { + /* PLFRCO trim values */ + *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608; + *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250; + *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118; + *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400; + } +#endif + +/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ +#if defined(_LCD_DISPCTRL_CHGRDST_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; + CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; + *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); + CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; + CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) + /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */ + *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { + /* Change HFXO default peak detector settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) + | 0x00178500U; + /* Change HFXO low power control settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) + | 0x0000C000U; + /* Change default SQBUF bias current. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; + } + + if (chipRev.major == 0x01 && chipRev.minor == 0x0) { + /* Trigger RAM read for each RAM instance */ + volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; + for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { + // Force memory read + *dmem; + dmem += (DMEM_BANK0_SIZE / 4U); + } + } + + /* Set TRACE clock to intended reset value. */ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) +#if defined(SL_TRUSTZONE_SECURE) +#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL) +#else +#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL) +#endif +#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL) + if (SYSTEM_GetProdRev() == 1) { + bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + /* Enable HFRCO CLKOUT0. */ + *(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0; + if (hfrcoClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; + } + } +#endif + +/* PM-3503 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) + { + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; + + while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { + /* Wait for previous synchronization to finish */ + } + + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { + /* Wait for BYPASS switch enable. */ + } + + if (dcdcIsLock) { + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; + } + + if (dcdcClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + } +#endif + +/* PM-5163 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && chipRev.minor == 0x00) { + bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + + *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) + | 0x0C000000UL; + + if (hfxo0ClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; + } + } +#endif +} + +/**************************************************************************//** + * @brief + * Chip reset routine with errata workarounds. + * + * @note + * This function should be called to reset the chip. It does not return. + * + * This function applies any errata workarounds needed to cleanly reset the + * device and then performs a system reset. See the device-specific errata for + * details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Reset(void) +{ +#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /**************************** + * Workaround for errata DCDC_E206. + * Disable radio interference minimization features when resetting */ + + // Ensure access to EMU registers + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; + + // No need to do anything if the DCDC is not powering DVDD + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + // Make sure radio cannot accidentally re-enable features + *(volatile uint32_t *)(0x40084040UL) = 0x1UL; + + // If DCDC is in use, disable features + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) + || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) { + BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); + BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); + } + } +#endif + + NVIC_SystemReset(); +} + +/** @} (end addtogroup chip) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_CHIP_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h index 3ac9d07..66b9ecc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h @@ -1,3654 +1,3654 @@ -/***************************************************************************//** - * @file - * @brief Clock management unit (CMU) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_CMU_H -#define EM_CMU_H - -#include "em_device.h" -#if defined(CMU_PRESENT) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "em_cmu_compat.h" -#include "em_gpio.h" -#include "sl_common.h" -#include "sl_enum.h" -#include "sl_status.h" -#include "sli_em_cmu.h" -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup cmu - * @{ - ******************************************************************************/ - -/** Macro to set clock sources in the clock tree. */ -#define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel - -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/* Enable register bit positions, for internal use. */ -#define CMU_EN_BIT_POS 0U -#define CMU_EN_BIT_MASK 0x1FU - -/* Enable register ID's for internal use. */ -#define CMU_NO_EN_REG 0 -#define CMU_CLKEN0_EN_REG 1 -#define CMU_CLKEN1_EN_REG 2 -#if defined(_CMU_CLKEN2_MASK) -#define CMU_CLKEN2_EN_REG 3 -#endif -#define CMU_CRYPTOACCCLKCTRL_EN_REG 3 -#define CMU_EN_REG_POS 5U -#define CMU_EN_REG_MASK 0x3U - -/* Clock branch ID's internal use. */ -#define CMU_CORE_BRANCH 0 -#define CMU_SYSCLK_BRANCH 1 -#define CMU_SYSTICK_BRANCH 2 -#define CMU_HCLK_BRANCH 3 -#define CMU_EXPCLK_BRANCH 4 -#define CMU_PCLK_BRANCH 5 -#define CMU_LSPCLK_BRANCH 6 -#define CMU_TRACECLK_BRANCH 7 -#define CMU_EM01GRPACLK_BRANCH 8 -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) -#define CMU_EM01GRPBCLK_BRANCH 9 -#endif -#define CMU_EUART0CLK_BRANCH 10 -#define CMU_IADCCLK_BRANCH 11 -#define CMU_EM23GRPACLK_BRANCH 12 -#define CMU_WDOG0CLK_BRANCH 13 -#if defined(RTCC_PRESENT) -#define CMU_RTCCCLK_BRANCH 14 -#elif defined(SYSRTC_PRESENT) -#define CMU_SYSRTCCLK_BRANCH 14 -#endif -#define CMU_EM4GRPACLK_BRANCH 15 -#if defined(PDM_PRESENT) -#define CMU_PDMREF_BRANCH 16 -#endif -#define CMU_DPLLREFCLK_BRANCH 17 -#if WDOG_COUNT > 1 -#define CMU_WDOG1CLK_BRANCH 18 -#endif -#if defined(LCD_PRESENT) -#define CMU_LCD_BRANCH 19 -#endif -#if defined(VDAC_PRESENT) -#define CMU_VDAC0_BRANCH 20 -#endif -#if defined(PCNT_PRESENT) -#define CMU_PCNT_BRANCH 21 -#endif -#if defined(LESENSE_PRESENT) -#define CMU_LESENSEHF_BRANCH 22 -#define CMU_LESENSE_BRANCH 23 -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -#define CMU_EM01GRPCCLK_BRANCH 24 -#endif -#if defined(VDAC_PRESENT) && (VDAC_COUNT > 1) -#define CMU_VDAC1_BRANCH 25 -#endif -#define CMU_CLK_BRANCH_POS 7U -#define CMU_CLK_BRANCH_MASK 0x1FU -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(_EMU_CMD_EM01VSCALE1_MASK) -/* Maximum clock frequency for VSCALE voltages. */ -#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL -#endif - -/* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API. - * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for - * Series1 parts (highest VSCALE voltage = lowest numerical value). */ -#define VSCALE_EM01_LOW_POWER 1 -#define VSCALE_EM01_HIGH_PERFORMANCE 0 - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define PLFRCO_PRESENT -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Disable clocks configuration */ -#if defined(_SILICON_LABS_32B_SERIES_2) -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */ -#endif // (_SILICON_LABS_32B_SERIES_2) - -/** Clock divider configuration */ -typedef uint32_t CMU_ClkDiv_TypeDef; - -/** HFRCODPLL frequency bands */ -SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) { - cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ - cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ - cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ - cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ - cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ - cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ - cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ - cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ - cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ - cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ - cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ - cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ - cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ - cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */ -#endif - cmuHFRCODPLLFreq_UserDefined = 0, -}; - -#if defined(USBPLL_PRESENT) -/** HFXO reference frequency */ -SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) { - cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (24UL << _USBPLL_CTRL_DIVX_SHIFT) - | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */ - cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (25UL << _USBPLL_CTRL_DIVX_SHIFT) - | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */ - cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (16UL << _USBPLL_CTRL_DIVX_SHIFT) - | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */ - cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (24UL << _USBPLL_CTRL_DIVX_SHIFT) - | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */ -}; -#endif - -/** HFRCODPLL maximum frequency */ -#define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz -/** HFRCODPLL minimum frequency */ -#define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz - -#if defined(HFRCOEM23_PRESENT) -/** HFRCOEM23 frequency bands */ -SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) { - cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ - cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ - cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ - cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ - cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ - cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ - cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ - cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ - cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ - cmuHFRCOEM23Freq_UserDefined = 0, -}; - -/** HFRCOEM23 maximum frequency */ -#define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz -/** HFRCOEM23 minimum frequency */ -#define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz -#endif // defined(HFRCOEM23_PRESENT) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/** Clock points in CMU clock-tree. */ -SL_ENUM(CMU_Clock_TypeDef) { - /*******************/ - /* Clock branches */ - /*******************/ - - cmuClock_SYSCLK, /**< System clock. */ - cmuClock_HCLK, /**< Core and AHB bus interface clock. */ - cmuClock_EXPCLK, /**< Export clock. */ - cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ - cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ - cmuClock_IADCCLK, /**< IADC clock. */ - cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ - cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ - cmuClock_WDOG0CLK, /**< WDOG0 clock. */ - cmuClock_WDOG1CLK, /**< WDOG1 clock. */ - cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ - cmuClock_TRACECLK, /**< Debug trace clock. */ - cmuClock_RTCCCLK, /**< RTCC clock. */ - cmuClock_HFRCOEM23, - - /*********************/ - /* Peripheral clocks */ - /*********************/ - - cmuClock_CORE, /**< Cortex-M33 core clock. */ - cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ - cmuClock_ACMP0, /**< ACMP0 clock. */ - cmuClock_ACMP1, /**< ACMP1 clock. */ - cmuClock_BURTC, /**< BURTC clock. */ - cmuClock_GPCRC, /**< GPCRC clock. */ - cmuClock_GPIO, /**< GPIO clock. */ - cmuClock_I2C0, /**< I2C0 clock. */ - cmuClock_I2C1, /**< I2C1 clock. */ - cmuClock_IADC0, /**< IADC clock. */ - cmuClock_LDMA, /**< LDMA clock. */ - cmuClock_LETIMER0, /**< LETIMER clock. */ - cmuClock_PRS, /**< PRS clock. */ - cmuClock_RTCC, /**< RTCC clock. */ - cmuClock_TIMER0, /**< TIMER0 clock. */ - cmuClock_TIMER1, /**< TIMER1 clock. */ - cmuClock_TIMER2, /**< TIMER2 clock. */ - cmuClock_TIMER3, /**< TIMER3 clock. */ - cmuClock_USART0, /**< USART0 clock. */ - cmuClock_USART1, /**< USART1 clock. */ - cmuClock_USART2, /**< USART2 clock. */ - cmuClock_WDOG0, /**< WDOG0 clock. */ - cmuClock_WDOG1, /**< WDOG1 clock. */ - cmuClock_PDM /**< PDM clock. */ -}; -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -/** Clock points in CMU clock-tree. */ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { - /*******************/ - /* Clock branches */ - /*******************/ - - cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */ - cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */ - cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */ - cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */ - cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */ - cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */ - cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */ - cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */ -#if defined(PDM_PRESENT) - cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */ -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */ -#endif -#if defined(EUART_PRESENT) - cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */ -#elif defined(EUSART_PRESENT) - cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */ -#endif - cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */ - cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */ - cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */ -#if WDOG_COUNT > 1 - cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */ -#endif -#if defined(RTCC_PRESENT) - cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */ -#elif defined(SYSRTC_PRESENT) - cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */ -#endif - cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */ - cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */ -#if defined(CRYPTOACC_PRESENT) - cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */ - cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */ -#endif -#if defined(LCD_PRESENT) - cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */ -#endif -#if defined(VDAC_PRESENT) - cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */ -#if (VDAC_COUNT > 1) - cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */ -#endif -#endif -#if defined(PCNT_PRESENT) - cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */ -#endif -#if defined(LESENSE_PRESENT) - cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */ - cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */ -#endif - - cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */ -#if defined(PDM_PRESENT) - cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */ -#endif - /*********************/ - /* Peripheral clocks */ - /*********************/ - - cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */ - cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */ -#if defined(RADIOAES_PRESENT) - cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */ -#endif - cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */ - cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */ - cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */ - cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */ - cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */ -#if defined(_CMU_CLKEN2_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#elif defined(_CMU_CLKEN1_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#elif defined(_CMU_CLKEN0_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#elif defined(_CMU_CLKEN1_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#elif defined(_CMU_CLKEN0_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#elif defined(_CMU_CLKEN1_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#elif defined(_CMU_CLKEN0_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#elif defined(_CMU_CLKEN1_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#elif defined(_CMU_CLKEN0_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER8_SHIFT) - cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER9_SHIFT) - cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */ -#endif -#if defined(USART_PRESENT) && USART_COUNT > 0 - cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */ -#endif -#if defined(USART_PRESENT) && USART_COUNT > 1 -#if defined(_CMU_CLKEN0_USART1_SHIFT) - cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ -#elif defined(_CMU_CLKEN2_USART1_SHIFT) - cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ -#endif -#endif /* defined(USART_PRESENT) && USART_COUNT > 1 */ -#if defined(USART_PRESENT) && USART_COUNT > 2 - cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */ -#endif /* defined(USART_PRESENT) && USART_COUNT > 2 */ -#if defined(IADC_PRESENT) - cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */ -#endif - cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */ -#if defined(LETIMER_PRESENT) - cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */ -#endif - cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */ -#if WDOG_COUNT > 1 - cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */ -#endif -#if defined(I2C_PRESENT) - cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */ -#if I2C_COUNT > 1 - cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */ -#endif /* I2C_COUNT > 1 */ -#if I2C_COUNT > 2 - cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */ -#endif /* I2C_COUNT > 2 */ -#if I2C_COUNT > 3 - cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */ -#endif /* I2C_COUNT > 3 */ -#endif /* defined(I2C_PRESENT) */ - cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */ - cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */ - cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */ -#if defined(HFRCOEM23_PRESENT) - cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */ -#endif -#if defined(HFXO_PRESENT) - cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */ -#endif - cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */ - cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */ - cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */ - cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */ -#if defined(EUART_PRESENT) - cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */ -#endif -#if defined(PDM_PRESENT) - cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */ -#endif - cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */ - cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */ - cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */ - cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */ -#if defined(RTCC_PRESENT) - cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */ -#endif - cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */ -#if defined(SYSRTC_PRESENT) - cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 - cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#if defined(_CMU_CLKEN1_EUSART2_SHIFT) - cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ -#elif defined(_CMU_CLKEN2_EUSART2_SHIFT) - cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#if defined(_CMU_CLKEN1_EUSART3_SHIFT) - cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ -#elif defined(_CMU_CLKEN2_EUSART3_SHIFT) - cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#if defined(_CMU_CLKEN1_EUSART4_SHIFT) - cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ -#elif defined(_CMU_CLKEN2_EUSART4_SHIFT) - cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */ -#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) - cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */ -#endif -#if defined(CRYPTOACC_PRESENT) - cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */ -#endif -#if defined(SEMAILBOX_PRESENT) - cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */ -#endif - cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */ -#if defined(ICACHE_PRESENT) - cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */ -#endif -#if defined(LESENSE_PRESENT) - cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */ -#endif -#if defined(ACMP_PRESENT) - cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */ -#if ACMP_COUNT > 1 - cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */ -#endif -#endif -#if defined(VDAC_PRESENT) - cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */ -#if (VDAC_COUNT > 1) - cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */ -#endif -#endif -#if defined(PCNT_PRESENT) - cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */ -#endif -#if defined(DMEM_PRESENT) - cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */ -#endif -#if defined(KEYSCAN_PRESENT) - cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */ -#endif -#if defined(LCD_PRESENT) - cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */ -#endif -#if defined(MVP_PRESENT) - cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */ -#endif - cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */ -#if defined(USB_PRESENT) - cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */ -#endif -#if defined(ETAMPDET_PRESENT) - cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */ -#endif -#if defined(RFFPLL_PRESENT) - cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */ -#endif -}; -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/** Oscillator types. */ -SL_ENUM(CMU_Osc_TypeDef) { - cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ - cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ - cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuOsc_HFXO, /**< High frequency crystal oscillator. */ - cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ -#if defined(HFRCOEM23_PRESENT) - cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ -#endif - cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ -}; - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/** Selectable clock sources. */ -SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ - cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ - cmuSelect_CLKIN0, /**< External clock input. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ - cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ - cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ - cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ - cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ - cmuSelect_EXPCLK, /**< Pin export clock. */ - cmuSelect_PRS /**< PRS input as clock. */ -}; -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/** Selectable clock sources. */ -SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */ - cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ - cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */ -#if defined(HFRCOEM23_PRESENT) - cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ -#endif - cmuSelect_CLKIN0, /**< External clock input. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ -#if defined(PLFRCO_PRESENT) - cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */ -#endif - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ - cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ - cmuSelect_SYSCLK, /**< System clock. */ - cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ - cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */ -#endif - cmuSelect_EXPCLK, /**< Pin export clock. */ - cmuSelect_PRS, /**< PRS input as clock. */ -#if defined(PCNT_PRESENT) - cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */ -#endif - cmuSelect_TEMPOSC, /**< Temperature oscillator. */ - cmuSelect_PFMOSC, /**< PFM oscillator. */ - cmuSelect_BIASOSC, /**< BIAS oscillator. */ -#if defined(USBPLL_PRESENT) - cmuSelect_USBPLL0, /**< PLL clock for USB. */ -#endif -#if defined(RFFPLL_PRESENT) - cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */ -#endif -}; -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/** DPLL reference clock edge detect selector. */ -SL_ENUM(CMU_DPLLEdgeSel_TypeDef) { - cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ - cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ -}; - -/** DPLL lock mode selector. */ -SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { - cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ - cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ -}; - -/** LFXO oscillator modes. */ -SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) { - cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ - cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ - cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ -}; - -/** LFXO start-up timeout delay. */ -SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) { - cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ - cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ - cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ - cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ - cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ - cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ - cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ - cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ -}; - -/** HFXO oscillator modes. */ -SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) { - cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ - cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ -#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) - cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */ -#endif -}; - -/** HFXO core bias LSB change timeout. */ -SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) { - cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ - cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ - cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ - cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ - cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ - cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ - cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ - cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ - cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ - cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ - cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ - cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ - cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ - cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ - cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ - cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ -}; - -/** HFXO steady state timeout. */ -SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) { - cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ - cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ - cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ - cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ - cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ - cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ - cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ - cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ - cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ - cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ - cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ - cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ - cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ - cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ - cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ -#if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US) - cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ -#endif -}; - -/** HFXO core degeneration control. */ -SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) { - cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ - cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ - cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ - cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ -}; - -/** HFXO XI and XO pin fixed capacitor control. */ -SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) { - cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ - cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ - cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ - cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ -}; - -/** Oscillator precision modes. */ -SL_ENUM(CMU_Precision_TypeDef) { - cmuPrecisionDefault, /**< Default precision mode. */ - cmuPrecisionHigh, /**< High precision mode. */ -}; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { - uint8_t gain; /**< Startup gain. */ - uint8_t capTune; /**< Internal capacitance tuning. */ - CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ - CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ - bool highAmplitudeEn; /**< High amplitude enable. */ - bool agcEn; /**< AGC enable. */ - bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ - bool failDetEn; /**< Oscillator failure detection enable. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Lock register access. */ -} CMU_LFXOInit_TypeDef; - -/** Default LFXO initialization values for XTAL mode. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - 1, \ - 38, \ - cmuLfxoStartupDelay_4KCycles, \ - cmuLfxoOscMode_Crystal, \ - false, /* highAmplitudeEn */ \ - true, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default LFXO initialization values for external clock mode. */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - 0U, \ - 0U, \ - cmuLfxoStartupDelay_2Cycles, \ - cmuLfxoOscMode_External, \ - false, /* highAmplitudeEn */ \ - false, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default LFXO initialization values for external sine mode. */ -#define CMU_LFXOINIT_EXTERNAL_SINE \ - { \ - 0U, \ - 0U, \ - cmuLfxoStartupDelay_2Cycles, \ - cmuLfxoOscMode_AcCoupledSine, \ - false, /* highAmplitudeEn */ \ - false, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** HFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { - CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ - CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ - CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ - uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ - uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ - uint8_t coreBiasStartup; /**< Core bias startup current. */ - uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ - CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ - CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ - uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ - uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ - uint8_t coreBiasAna; /**< Core bias current. */ - bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ - CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ - bool forceXo2GndAna; /**< Force XO pin to ground. */ - bool forceXi2GndAna; /**< Force XI pin to ground. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ -#if defined(HFXO_CTRL_EM23ONDEMAND) - bool em23OnDemand; /**< Enable deep sleep. */ -#endif - bool regLock; /**< Lock register access. */ -} CMU_HFXOInit_TypeDef; - -#if defined(HFXO_CTRL_EM23ONDEMAND) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -// See [PM-2871] for details. -/** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \ - && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) -// See [PM-5131] for details. -/** - * Default configuration of fixed tuning capacitance on XO for EFR32XG24 - * when high power PA is present and output dBm equal 20 dBm. - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -// See [PM-5638] for details. -/** - * Default configuration of fixed tuning capacitance on XO for EFR32XG25 - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#else -/** - * Default configuration of fixed tuning capacitance on XO and XI. - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both -#endif - -/** Default HFXO initialization values for XTAL mode. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - cmuHfxoCbLsbTimeout_416us, \ - cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ - cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 32U, /* coreBiasStartup */ \ - 32U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \ - _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ - _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ - 60U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna */ \ - cmuHfxoOscMode_Crystal, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode. */ -#define CMU_HFXOINIT_EXTERNAL_SINE \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSine, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode with peak detector. */ -#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSinePkDet, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } -#else -/** Default HFXO initialization values for XTAL mode. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - cmuHfxoCbLsbTimeout_416us, \ - cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ - cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 32U, /* coreBiasStartup */ \ - 32U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_Both, \ - _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ - _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ - 60U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna */ \ - cmuHfxoOscMode_Crystal, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode. */ -#define CMU_HFXOINIT_EXTERNAL_SINE \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSine, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode with peak detector. */ -#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSinePkDet, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } -#endif - -#if defined(_HFXO_BUFOUTCTRL_MASK) - -/** Crystal sharing timeout start up timeout. */ -SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) { - startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */ - startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */ - startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */ - startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */ - startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */ - startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */ - startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */ - startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */ - startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */ - startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */ - startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */ - startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */ - startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */ - startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */ - startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */ - startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */ -}; - -/** Crystal sharing leader initialization structure. */ -typedef struct { - bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */ - CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */ -} CMU_BUFOUTLeaderInit_TypeDef; - -/** Default crystal sharing master initialization values. */ -#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \ - { \ - true, /* minimalStartupDelay */ \ - startupTimeout208Us, /* timeoutStartup */ \ - } -#endif - -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -/** PRS status select output signal. */ -SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) { - PRS_Status_select_0, /**< PRS status 0 output signal. */ - PRS_Status_select_1 /**< PRS status 1 output signal. */ -}; - -/** Crystal sharing follower initialization structure. */ -typedef struct { - CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */ - bool em23OnDemand; /**< Enable em23 on demand. */ - bool regLock; /**< Lock registers. */ -} CMU_CrystalSharingFollowerInit_TypeDef; - -/** Default crystal sharing follower initialization values. */ -#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \ - { \ - PRS_Status_select_0, /* prsStatusSelectOutput */ \ - true, /* em23OnDemand */ \ - false /* regLock */ \ - } -#endif - -/** DPLL initialization structure. - * Frequency will be Fref*(N+1)/(M+1). */ -typedef struct { - uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ - uint16_t n; /**< Factor N. 300 <= N <= 4095 */ - uint16_t m; /**< Factor M. M <= 4095 */ - CMU_Select_TypeDef refClk; /**< Reference clock selector. */ - CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ - CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ - bool autoRecover; /**< Enable automatic lock recovery. */ - bool ditherEn; /**< Enable dither functionality. */ -} CMU_DPLLInit_TypeDef; - -/** - * DPLL initialization values for 39,998,805 Hz using LFXO as reference - * clock, M=2 and N=3661. - */ -#define CMU_DPLL_LFXO_TO_40MHZ \ - { \ - 39998805, /* Target frequency. */ \ - 3661, /* Factor N. */ \ - 2, /* Factor M. */ \ - cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * DPLL initialization values for 76,800,000 Hz using HFXO as reference - * clock, M = 1919, N = 3839 - */ -#define CMU_DPLL_HFXO_TO_76_8MHZ \ - { \ - 76800000, /* Target frequency. */ \ - 3839, /* Factor N. */ \ - 1919, /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * DPLL initialization values for 80,000,000 Hz using HFXO as reference - * clock, M = 1919, N = 3999. - */ -#define CMU_DPLL_HFXO_TO_80MHZ \ - { \ - 80000000, /* Target frequency. */ \ - (4000 - 1), /* Factor N. */ \ - (1920 - 1), /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * Default configurations for DPLL initialization. When using this macro - * you need to modify the N and M factor and the desired frequency to match - * the components placed on the board. - */ -#define CMU_DPLLINIT_DEFAULT \ - { \ - 80000000, /* Target frequency. */ \ - (4000 - 1), /* Factor N. */ \ - (1920 - 1), /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -#if defined(USBPLL_PRESENT) -/** USB PLL initialization structure. */ -typedef struct { - CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */ - bool shuntRegEn; /**< Shunt regulator enable. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Enable register lock. */ -} CMU_USBPLL_Init_TypeDef; - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 38 MHz. - */ -#define CMU_USBPLL_REFFREQ_38MHZ \ - { \ - cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 38.4 MHz. - */ -#define CMU_USBPLL_REFFREQ_38_4MHZ \ - { \ - cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 39 MHz. - */ -#define CMU_USBPLL_REFFREQ_39MHZ \ - { \ - cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 40 MHz. - */ -#define CMU_USBPLL_REFFREQ_40MHZ \ - { \ - cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } -#endif - -#if defined(RFFPLL_PRESENT) -/** - * RFF PLL initialization structure. - * When using this structure you need to modify the X, Y and N factor - * and the desired host target frequency to match the components placed - * on the board (namely the RFFPLL reference clock). - * X, Y, N values for a 39MHz HFXO: - * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY - * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2) - */ -typedef struct { - uint32_t frequency; /**< Host target frequency. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Enable register lock. */ - uint8_t dividerY; /**< Divider Y for digital. */ - uint8_t dividerX; /**< Divider X for Radio. */ - uint8_t dividerN; /**< Feedback divider N. */ -} CMU_RFFPLL_Init_TypeDef; - -/** Radio frequency locked loop default initialization values. */ -#define CMU_RFFPLL_DEFAULT \ - { \ - 100000000UL, /* Host target frequency. */ \ - false, /* Disable on-demand requests. */ \ - false, /* Force enable. */ \ - true, /* Enable register lock. */ \ - _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \ - _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \ - _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \ - } - -/** Radio frequency locked loop initialization values for 97.5MHz. */ -#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \ - { \ - 97500000UL, /* Host target frequency. */ \ - false, /* Disable on-demand requests. */ \ - false, /* Force enable. */ \ - true, /* Enable register lock. */ \ - 20U, /* Divider Y for digital. */ \ - 6U, /* Divider X for Radio. */ \ - 100U /* Feedback divider N. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t cycles, - CMU_Select_TypeDef reference); -void CMU_CalibrateConfig(uint32_t downCycles, - CMU_Select_TypeDef downSel, - CMU_Select_TypeDef upSel); -uint32_t CMU_CalibrateCountGet(void); -void CMU_ClkOutPinConfig(uint32_t clkno, - CMU_Select_TypeDef sel, - CMU_ClkDiv_TypeDef clkdiv, - GPIO_Port_TypeDef port, - unsigned int pin); -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, - CMU_ClkDiv_TypeDef div); -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); -#endif -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, - CMU_Select_TypeDef ref); -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); -void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); -#if defined(USBPLL_PRESENT) -void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit); -__STATIC_INLINE void CMU_WaitUSBPLLLock(void); -#endif -#if defined(RFFPLL_PRESENT) -void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); -__STATIC_INLINE void CMU_WaitRFFPLLLock(void); -#endif -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); -#if defined(HFXO0_BUFOUT) -void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, - GPIO_Port_TypeDef port, - unsigned int pin); -#endif -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, - unsigned int prsAsyncCh, - GPIO_Port_TypeDef port, - unsigned int pin); -#endif -sl_status_t CMU_HFXOCTuneSet(uint32_t ctune); -uint32_t CMU_HFXOCTuneGet(void); -void CMU_HFXOCTuneDeltaSet(int32_t delta); -int32_t CMU_HFXOCTuneDeltaGet(void); -void CMU_HFXOCoreBiasCurrentCalibrate(void); -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); -void CMU_LFXOPrecisionSet(uint16_t precision); -uint16_t CMU_LFXOPrecisionGet(void); -void CMU_HFXOPrecisionSet(uint16_t precision); -uint16_t CMU_HFXOPrecisionGet(void); -#if defined(PLFRCO_PRESENT) -void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision); -#endif -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, - uint32_t val); -void CMU_UpdateWaitStates(uint32_t freq, int vscale); -void CMU_PCNTClockExternalSet(unsigned int instance, bool external); - -#if defined(HFRCOEM23_PRESENT) -CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); -void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @note - * This is a dummy function to solve backward compatibility issues. - * - * @param[in] clock - * The clock to enable/disable. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -__STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - (void)clock; - (void)enable; -} -#endif - -/***************************************************************************//** - * @brief - * Configure continuous calibration mode. - * @param[in] enable - * If true, enables continuous calibration, if false disables continuous - * calibration. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateCont(bool enable) -{ - BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Start calibration. - * @note - * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly - * @ref CMU_CalibrateCont(). - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStart(void) -{ - CMU->CALCMD = CMU_CALCMD_CALSTART; -} - -/***************************************************************************//** - * @brief - * Stop calibration counters. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStop(void) -{ - CMU->CALCMD = CMU_CALCMD_CALSTOP; -} - -/***************************************************************************//** - * @brief - * Unlock the DPLL. - * @note - * The HFRCODPLL oscillator is not turned off. - ******************************************************************************/ -__STATIC_INLINE void CMU_DPLLUnlock(void) -{ - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { - } -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending CMU interrupt flags. - * - * @param[in] flags - * CMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntClear(uint32_t flags) -{ - CMU->IF_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more CMU interrupt sources. - * - * @param[in] flags - * CMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntDisable(uint32_t flags) -{ - CMU->IEN_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more CMU interrupt sources. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using @ref CMU_IntClear() prior to - * enabling if such a pending interrupt should be ignored. - * - * @param[in] flags - * CMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntEnable(uint32_t flags) -{ - CMU->IEN_SET = flags; -} - -/***************************************************************************//** - * @brief - * Get pending CMU interrupt sources. - * - * @return - * CMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGet(void) -{ - return CMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending CMU interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * Pending and enabled CMU interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in CMU_IEN and - * - the pending interrupt flags CMU_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = CMU->IEN; - return CMU->IF & ien; -} - -/**************************************************************************//** - * @brief - * Set one or more pending CMU interrupt sources. - * - * @param[in] flags - * CMU interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void CMU_IntSet(uint32_t flags) -{ - CMU->IF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Lock CMU register access in order to protect registers contents against - * unintended modification. - * - * @details - * See the reference manual for CMU registers that will be - * locked. - * - * @note - * If locking the CMU registers, they must be unlocked prior to using any - * CMU API functions modifying CMU registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_Lock(void) -{ - CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Enable/disable oscillator. - * - * @note - * This is a dummy function to solve backward compatibility issues. - * - * @param[in] osc - * The oscillator to enable/disable. - * - * @param[in] enable - * @li true - enable specified oscillator. - * @li false - disable specified oscillator. - * - * @param[in] wait - * Only used if @p enable is true. - * @li true - wait for oscillator start-up time to timeout before returning. - * @li false - do not wait for oscillator start-up time to timeout before - * returning. - ******************************************************************************/ -__STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, - bool enable, - bool wait) -{ - (void)osc; - (void)enable; - (void)wait; -} - -/***************************************************************************//** - * @brief - * Unlock CMU register access so that writing to registers is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_Unlock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Lock WDOG register access in order to protect registers contents against - * unintended modification. - * - * @note - * If locking the WDOG registers, they must be unlocked prior to using any - * emlib API functions modifying registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_WdogLock(void) -{ - CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Unlock WDOG register access so that writing to registers is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_WdogUnlock(void) -{ - CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; -} - -#if defined(USBPLL_PRESENT) -/***************************************************************************//** - * @brief - * Wait for USB PLL lock and ready. - ******************************************************************************/ -__STATIC_INLINE void CMU_WaitUSBPLLLock() -{ - while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) - != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { - /* Wait for USB PLL lock and ready */ - } -} -#endif - -#if defined(RFFPLL_PRESENT) -/***************************************************************************//** - * @brief - * Wait for RFF PLL lock and ready. - ******************************************************************************/ -__STATIC_INLINE void CMU_WaitRFFPLLLock() -{ - while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) - != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { - /* Wait for RFF PLL lock and ready. */ - } -} -#endif - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/* Select register IDs for internal use. */ -#define CMU_NOSEL_REG 0 -#define CMU_HFCLKSEL_REG 1 -#define CMU_LFACLKSEL_REG 2 -#define CMU_LFBCLKSEL_REG 3 -#define CMU_LFCCLKSEL_REG 4 -#define CMU_LFECLKSEL_REG 5 -#define CMU_DBGCLKSEL_REG 6 -#define CMU_USBCCLKSEL_REG 7 -#define CMU_ADC0ASYNCSEL_REG 8 -#define CMU_ADC1ASYNCSEL_REG 9 -#define CMU_SDIOREFSEL_REG 10 -#define CMU_QSPI0REFSEL_REG 11 -#define CMU_USBRCLKSEL_REG 12 -#define CMU_PDMREFSEL_REG 13 - -#define CMU_SEL_REG_POS 0U -#define CMU_SEL_REG_MASK 0xfU - -/* Divisor/prescaler register IDs for internal use. */ -#define CMU_NODIV_REG 0 -#define CMU_NOPRESC_REG 0 -#define CMU_HFPRESC_REG 1 -#define CMU_HFCLKDIV_REG 1 -#define CMU_HFEXPPRESC_REG 2 -#define CMU_HFCLKLEPRESC_REG 3 -#define CMU_HFPERPRESC_REG 4 -#define CMU_HFPERCLKDIV_REG 4 -#define CMU_HFPERPRESCB_REG 5 -#define CMU_HFPERPRESCC_REG 6 -#define CMU_HFCOREPRESC_REG 7 -#define CMU_HFCORECLKDIV_REG 7 -#define CMU_LFAPRESC0_REG 8 -#define CMU_LFBPRESC0_REG 9 -#define CMU_LFEPRESC0_REG 10 -#define CMU_ADCASYNCDIV_REG 11 -#define CMU_HFBUSPRESC_REG 12 -#define CMU_HFCORECLKLEDIV_REG 13 - -#define CMU_PRESC_REG_POS 4U -#define CMU_DIV_REG_POS CMU_PRESC_REG_POS -#define CMU_PRESC_REG_MASK 0xfU -#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK - -/* Enable register IDs for internal use. */ -#define CMU_NO_EN_REG 0 -#define CMU_CTRL_EN_REG 1 -#define CMU_HFPERCLKDIV_EN_REG 1 -#define CMU_HFPERCLKEN0_EN_REG 2 -#define CMU_HFCORECLKEN0_EN_REG 3 -#define CMU_PDMREF_EN_REG 4 -#define CMU_HFBUSCLKEN0_EN_REG 5 -#define CMU_LFACLKEN0_EN_REG 6 -#define CMU_LFBCLKEN0_EN_REG 7 -#define CMU_LFCCLKEN0_EN_REG 8 -#define CMU_LFECLKEN0_EN_REG 9 -#define CMU_PCNT_EN_REG 10 -#define CMU_SDIOREF_EN_REG 11 -#define CMU_QSPI0REF_EN_REG 12 -#define CMU_QSPI1REF_EN_REG 13 -#define CMU_HFPERCLKEN1_EN_REG 14 -#define CMU_USBRCLK_EN_REG 15 - -#define CMU_EN_REG_POS 8U -#define CMU_EN_REG_MASK 0xfU - -/* Enable register bit positions, for internal use. */ -#define CMU_EN_BIT_POS 12U -#define CMU_EN_BIT_MASK 0x1fU - -/* Clock branch bitfield positions, for internal use. */ -#define CMU_HF_CLK_BRANCH 0 -#define CMU_HFCORE_CLK_BRANCH 1 -#define CMU_HFPER_CLK_BRANCH 2 -#define CMU_HFPERB_CLK_BRANCH 3 -#define CMU_HFPERC_CLK_BRANCH 4 -#define CMU_HFBUS_CLK_BRANCH 5 -#define CMU_HFEXP_CLK_BRANCH 6 -#define CMU_DBG_CLK_BRANCH 7 -#define CMU_AUX_CLK_BRANCH 8 -#define CMU_RTC_CLK_BRANCH 9 -#define CMU_RTCC_CLK_BRANCH 10 -#define CMU_LETIMER0_CLK_BRANCH 11 -#define CMU_LETIMER1_CLK_BRANCH 12 -#define CMU_LEUART0_CLK_BRANCH 13 -#define CMU_LEUART1_CLK_BRANCH 14 -#define CMU_LFA_CLK_BRANCH 15 -#define CMU_LFB_CLK_BRANCH 16 -#define CMU_LFC_CLK_BRANCH 17 -#define CMU_LFE_CLK_BRANCH 18 -#define CMU_USBC_CLK_BRANCH 19 -#define CMU_USBLE_CLK_BRANCH 20 -#define CMU_LCDPRE_CLK_BRANCH 21 -#define CMU_LCD_CLK_BRANCH 22 -#define CMU_LESENSE_CLK_BRANCH 23 -#define CMU_CSEN_LF_CLK_BRANCH 24 -#define CMU_ADC0ASYNC_CLK_BRANCH 25 -#define CMU_ADC1ASYNC_CLK_BRANCH 26 -#define CMU_SDIOREF_CLK_BRANCH 27 -#define CMU_QSPI0REF_CLK_BRANCH 28 -#define CMU_USBR_CLK_BRANCH 29 -#define CMU_PDMREF_CLK_BRANCH 30 -#define CMU_HFLE_CLK_BRANCH 31 - -#define CMU_CLK_BRANCH_POS 17U -#define CMU_CLK_BRANCH_MASK 0x1fU - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) -/* Maximum clock frequency for VSCALE voltages. */ -#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL -#endif - -/* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API. - * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for - * Series1 parts (highest VSCALE voltage = lowest numerical value). */ -#define VSCALE_EM01_LOW_POWER 2 -#define VSCALE_EM01_HIGH_PERFORMANCE 0 - -#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) -#define USBC_CLOCK_PRESENT -#endif -#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) -#define USBR_CLOCK_PRESENT -#endif -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define PLFRCO_PRESENT -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Clock divisors. These values are valid for prescalers. */ -#define cmuClkDiv_1 1 /**< Divide clock by 1. */ -#define cmuClkDiv_2 2 /**< Divide clock by 2. */ -#define cmuClkDiv_4 4 /**< Divide clock by 4. */ -#define cmuClkDiv_8 8 /**< Divide clock by 8. */ -#define cmuClkDiv_16 16 /**< Divide clock by 16. */ -#define cmuClkDiv_32 32 /**< Divide clock by 32. */ -#define cmuClkDiv_64 64 /**< Divide clock by 64. */ -#define cmuClkDiv_128 128 /**< Divide clock by 128. */ -#define cmuClkDiv_256 256 /**< Divide clock by 256. */ -#define cmuClkDiv_512 512 /**< Divide clock by 512. */ -#define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ -#define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ -#define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ -#define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ -#define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ -#define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ - -/** Clock divider configuration */ -typedef uint32_t CMU_ClkDiv_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_1) -/** Clockprescaler configuration */ -typedef uint32_t CMU_ClkPresc_TypeDef; -#endif - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/** High-frequency system RCO bands */ -SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) { - cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ - cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ - cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ - cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ - cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ -#if defined(CMU_HFRCOCTRL_BAND_28MHZ) - cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ -#endif -}; -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/** AUX high-frequency RCO bands */ -SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) { - cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ - cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ - cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ - cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ - cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ -#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) - cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ -#endif -}; -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/** Universal serial high-frequency RC bands */ -SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) { - /** 24 MHz RC band. */ - cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, - /** 48 MHz RC band. */ - cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, -}; -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -/** High-USHFRCO bands */ -SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) { - cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ - cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ - cmuUSHFRCOFreq_UserDefined = 0, -}; -/** USHFRCO minimum frequency */ -#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz -/** USHFRCO maximum frequency */ -#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz -#endif - -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -/** High-frequency system RCO bands */ -SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) { - cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ - cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ - cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ - cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ - cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ - cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ - cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ - cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ -#if defined(_DEVINFO_HFRCOCAL13_MASK) - cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL14_MASK) - cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL15_MASK) - cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL16_MASK) - cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ -#endif - cmuHFRCOFreq_UserDefined = 0, -}; - -/** HFRCO minimum frequency. */ -#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz -#if defined(_DEVINFO_HFRCOCAL16_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz -#elif defined(_DEVINFO_HFRCOCAL15_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz -#elif defined(_DEVINFO_HFRCOCAL14_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz -#elif defined(_DEVINFO_HFRCOCAL13_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz -#else -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz -#endif -#endif - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/** AUX high-frequency RCO bands */ -SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) { - cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ - cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ - cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ - cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ - cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ - cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ - cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ - cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ -#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) - cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ -#endif -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) - cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ -#endif - cmuAUXHFRCOFreq_UserDefined = 0, -}; -/** AUXHFRCO minimum frequency. */ -#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz -#elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz -#else -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz -#endif -#endif - -/** Clock points in CMU. See CMU overview in the reference manual. */ -SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { - /*******************/ - /* HF clock branch */ - /*******************/ - - /** High-frequency clock */ -#if defined(_CMU_CTRL_HFCLKDIV_MASK) \ - || defined(_CMU_HFPRESC_MASK) - cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /** Debug clock */ - cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** AUX clock */ - cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(_CMU_HFEXPPRESC_MASK) - /**********************/ - /* HF export sub-branch */ - /**********************/ - - /** Export clock */ - cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_MASK) -/**********************************/ -/* HF bus clock sub-branch */ -/**********************************/ - - /** High-frequency bus clock */ -#if defined(_CMU_HFBUSPRESC_MASK) - cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO) - /** Cryptography accelerator clock */ - cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO0) - /** Cryptography accelerator 0 clock */ - cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO1) - /** Cryptography accelerator 1 clock */ - cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_LDMA) - /** Direct-memory access controller clock */ - cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_QSPI0) - /** Quad SPI clock */ - cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_GPCRC) - /** General-purpose cyclic redundancy checksum clock */ - cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_GPIO) - /** General-purpose input/output clock */ - cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /** Low-energy clock divided down from HFCLK */ - cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_HFBUSCLKEN0_PRS) - /** Peripheral reflex system clock */ - cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - - /**********************************/ - /* HF peripheral clock sub-branch */ - /**********************************/ - - /** High-frequency peripheral clock */ -#if defined(_CMU_HFPRESC_MASK) - cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERPRESCB_MASK) - /** Branch B figh-frequency peripheral clock */ - cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - /** Branch C figh-frequency peripheral clock */ - cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_PDM) - /** PDM clock */ - cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART0) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USARTRF0) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USARTRF1) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART1) - /** Universal sync/async receiver/transmitter 1 clock */ - cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART2) - /** Universal sync/async receiver/transmitter 2 clock */ - cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCB_MASK) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_USART3) - /** Universal sync/async receiver/transmitter 3 clock */ - cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART4) - /** Universal sync/async receiver/transmitter 4 clock */ - cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART5) - /** Universal sync/async receiver/transmitter 5 clock */ - cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_UART0) - /** Universal async receiver/transmitter 0 clock */ - cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFPERCLKEN1_UART0_MASK) - /** Universal async receiver/transmitter 0 clock */ - cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_UART1) - /** Universal async receiver/transmitter 1 clock */ - cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFPERCLKEN1_UART1_MASK) - /** Universal async receiver/transmitter 1 clock */ - cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER0) - /** Timer 0 clock */ - cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCB_MASK) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER1) - /** Timer 1 clock */ - cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER2) - /** Timer 2 clock */ - cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER3) - /** Timer 3 clock */ - cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER4) - /** Timer 4 clock */ - cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER5) - /** Timer 5 clock */ - cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER6) - /** Timer 6 clock */ - cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_WTIMER0) - /** Wide-timer 0 clock */ - cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_WTIMER0) - /** Wide-timer 0 clock */ - cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_WTIMER1) - /** Wide-timer 1 clock */ - cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_WTIMER1) - /** Wide-timer 1 clock */ - cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN1_WTIMER2) - /** Wide-timer 2 clock */ - cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN1_WTIMER3) - /** Wide-timer 3 clock */ - cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_CRYOTIMER) - /** CRYOtimer clock */ - cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP0) - /** Analog comparator 0 clock */ - cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP1) - /** Analog comparator 1 clock */ - cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP2) - /** Analog comparator 2 clock */ - cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP3) - /** Analog comparator 3 clock */ - cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_PRS) - /** Peripheral-reflex system clock */ - cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_DAC0) - /** Digital-to-analog converter 0 clock */ - cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_VDAC0) - /** Voltage digital-to-analog converter 0 clock */ - cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_VDAC0) - /** Voltage digital-to-analog converter 0 clock */ - cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_IDAC0) - /** Current digital-to-analog converter 0 clock */ - cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_GPIO) - /** General-purpose input/output clock */ - cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_VCMP) - /** Voltage comparator clock */ - cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_ADC0) - /** Analog-to-digital converter 0 clock */ - cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ADC1) - /** Analog-to-digital converter 1 clock */ - cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_I2C0) - /** I2C 0 clock */ - cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_I2C1) - /** I2C 1 clock */ - cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_I2C2) - /** I2C 2 clock */ - cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_CSEN) - /** Capacitive Sense HF clock */ - cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_CSEN) - /** Capacitive Sense HF clock */ - cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TRNG0) - /** True random number generator clock */ - cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERCLKEN1_CAN0_MASK) - /** Controller Area Network 0 clock */ - cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERCLKEN1_CAN1_MASK) - /** Controller Area Network 1 clock. */ - cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /**********************/ - /* HF core sub-branch */ - /**********************/ - - /** Core clock */ - cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_HFCORECLKEN0_AES) - /** Advanced encryption standard accelerator clock */ - cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_DMA) - /** Direct memory access controller clock */ - cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_LE) - /** Low-energy clock divided down from HFCORECLK */ - cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_EBI) - /** External bus interface clock */ - cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) - /** External bus interface clock */ - cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_ETH_MASK) - /** Ethernet clock */ - cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) - /** SDIO clock */ - cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(USBC_CLOCK_PRESENT) - /** USB Core clock */ - cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#if defined (USBR_CLOCK_PRESENT) - /** USB Rate clock */ - cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) - | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_USB) - /** USB clock */ - cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFBUSCLKEN0_USB) - /** USB clock */ - cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /***************/ - /* LF A branch */ - /***************/ - - /** Low-frequency A clock */ - cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFACLKEN0_RTC) - /** Real time counter clock */ - cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) - | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LETIMER0) - /** Low-energy timer 0 clock */ - cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LETIMER1) - /** Low-energy timer 1 clock */ - cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LCD) - /** Liquid crystal display, pre FDIV clock */ - cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** Liquid crystal display clock. Note that FDIV prescaler - * must be set by special API. */ - cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) - | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT0CLKEN) - /** Pulse counter 0 clock */ - cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT1CLKEN) - /** Pulse counter 1 clock */ - cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT2CLKEN) - /** Pulse counter 2 clock */ - cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#if defined(CMU_LFACLKEN0_LESENSE) - /** LESENSE clock */ - cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) - | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /***************/ - /* LF B branch */ - /***************/ - - /** Low-frequency B clock */ - cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFBCLKEN0_LEUART0) - /** Low-energy universal asynchronous receiver/transmitter 0 clock */ - cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_CSEN) - /** Capacitive Sense LF clock */ - cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_LEUART1) - /** Low-energy universal asynchronous receiver/transmitter 1 clock */ - cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_SYSTICK) - /** Cortex SYSTICK LF clock */ - cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_LFCCLKEN0_MASK) - /***************/ - /* LF C branch */ - /***************/ - - /** Low-frequency C clock */ - cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFCCLKEN0_USBLE) - /** USB LE clock */ - cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_LFCCLKEN0_USB) - /** USB LE clock */ - cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - -#if defined(_CMU_LFECLKEN0_MASK) - /***************/ - /* LF E branch */ - /***************/ - - /** Low-frequency E clock */ - cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** Real-time counter and calendar clock */ -#if defined (CMU_LFECLKEN0_RTCC) - cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) - | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - - /**********************************/ - /* Asynchronous peripheral clocks */ - /**********************************/ - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - /** ADC0 asynchronous clock */ - cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) - | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - /** ADC1 asynchronous clock */ - cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) - | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) - /** SDIO reference clock */ - cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) - | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) - | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) - | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) - /** QSPI0 reference clock */ - cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) - | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) - | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) - | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) - /** PDM reference clock */ - cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) - | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) - | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -}; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated CMU_Clock_TypeDef member */ -#define cmuClock_CORELE cmuClock_HFLE -/** @endcond */ - -/** Oscillator types. */ -SL_ENUM(CMU_Osc_TypeDef) { - cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ - cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ - cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ - cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ - cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - cmuOsc_CLKIN0, /**< External oscillator. */ -#endif -#if defined(PLFRCO_PRESENT) - cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ -#endif -}; - -/** Oscillator modes. */ -SL_ENUM(CMU_OscMode_TypeDef) { - cmuOscMode_Crystal, /**< Crystal oscillator. */ - cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ - cmuOscMode_External, /**< External digital clock. */ -}; - -/** Selectable clock sources. */ -SL_ENUM(CMU_Select_TypeDef) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ - cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ - cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ - cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ - cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */ - cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ - cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on - Tiny Gecko and for USBC (not used on Gecko). */ -#if defined(CMU_STATUS_USHFRCOENS) - cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ -#endif -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ -#endif -#if defined(CMU_HFXOCTRL_HFXOX2EN) - cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - cmuSelect_CLKIN0, /**< External clock input. */ -#endif -#if defined(PLFRCO_PRESENT) - cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ -#endif -}; - -#if defined(CMU_HFCORECLKEN0_LE) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated CMU_Select_TypeDef member */ -#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE -/** @endcond */ -#endif - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -/** HFXO tuning modes */ -SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) { - cmuHFXOTuningMode_Auto = 0, - cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ - cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ - | CMU_CMD_HFXOSHUNTOPTSTART, -#endif -}; -#endif - -#if defined(_CMU_CTRL_LFXOBOOST_MASK) -/** LFXO Boost values. */ -SL_ENUM(CMU_LFXOBoost_TypeDef) { - cmuLfxoBoost70 = 0x0, - cmuLfxoBoost100 = 0x2, -#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) - cmuLfxoBoost70Reduced = 0x1, - cmuLfxoBoost100Reduced = 0x3, -#endif -}; -#endif - -#if defined(CMU_OSCENCMD_DPLLEN) -/** DPLL reference clock selector. */ -SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) { - cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ - cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ - cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ -}; - -/** DPLL reference clock edge detect selector. */ -SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) { - cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ - cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ -}; - -/** DPLL lock mode selector. */ -SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { - cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ - cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ -}; -#endif // CMU_OSCENCMD_DPLLEN - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { -#if defined(_CMU_LFXOCTRL_MASK) - uint8_t ctune; /**< CTUNE (load capacitance) value */ - uint8_t gain; /**< Gain/max startup margin */ -#else - CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ -#endif - uint8_t timeout; /**< Startup delay */ - CMU_OscMode_TypeDef mode; /**< Oscillator mode */ -} CMU_LFXOInit_TypeDef; - -#if defined(_CMU_LFXOCTRL_MASK) -/** Default LFXO initialization values. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ - _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ - _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ - cmuOscMode_Crystal, /* Crystal oscillator */ \ - } -/** Default LFXO initialization for external clock */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - 0, /* No CTUNE value needed */ \ - 0, /* No LFXO startup gain */ \ - _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ - cmuOscMode_External, /* External digital clock */ \ - } -#else -/** Default LFXO initialization values. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - cmuLfxoBoost70, \ - _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -/** Default LFXO initialization for external clock */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - cmuLfxoBoost70, \ - _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ - cmuOscMode_External, \ - } -#endif - -/** HFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { -#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) - uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ - uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ - uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ - uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ - uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ - uint8_t timeoutSteady; /**< Timeout - steady-state */ - uint8_t timeoutStartup; /**< Timeout - startup */ -#elif defined(_CMU_HFXOCTRL_MASK) - bool lowPowerMode; /**< Enable low-power mode */ - bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ - uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ - uint8_t regIshSteadyState; /**< Shunt steady-state current */ - uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ - uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ - uint8_t thresholdPeakDetect; /**< Peak detection threshold */ - uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ - uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ - uint8_t timeoutSteady; /**< Timeout - steady-state */ - uint8_t timeoutStartup; /**< Timeout - startup */ -#else - uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ - uint8_t timeout; /**< Startup delay */ - bool glitchDetector; /**< Enable/disable glitch detector */ -#endif - CMU_OscMode_TypeDef mode; /**< Oscillator mode */ -} CMU_HFXOInit_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) -/** Default HFXO init. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -/** Init of HFXO with external clock. */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_External, \ - } -#elif defined(_CMU_HFXOCTRL_MASK) -/** - * Default HFXO initialization values for Platform 2 devices, which contain a - * separate HFXOCTRL register. - */ -#if defined(_EFR_DEVICE) -#define CMU_HFXOINIT_DEFAULT \ - { \ - false, /* Low-noise mode for EFR32 */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - 0xA, /* Default Shunt steady-state current */ \ - 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ - 0x7, /* Recommended steady-state XO core bias current */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0xA, /* Recommended peak detection timeout */ \ - 0x4, /* Recommended steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -#else /* EFM32 device */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - true, /* Low-power mode for EFM32 */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - 0xA, /* Default shunt steady-state current */ \ - 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ - 0x7, /* Recommended steady-state osc core bias current */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0xA, /* Recommended peak detection timeout */ \ - 0x4, /* Recommended steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -#endif /* _EFR_DEVICE */ -/** Init of HFXO with external clock. */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - true, /* Low-power mode */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - 0, /* Startup CTUNE=0 recommended for external clock */ \ - 0, /* Steady CTUNE=0 recommended for external clock */ \ - 0xA, /* Default shunt steady-state current */ \ - 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ - 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0x0, /* Peak-detect not recommended for external clock usage */ \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ - cmuOscMode_External, \ - } -#else /* _CMU_HFXOCTRL_MASK */ -/** - * Default HFXO initialization values for Platform 1 devices. - */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ - _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ - false, /* Disable glitch detector */ \ - cmuOscMode_Crystal, /* Crystal oscillator */ \ - } -/** Default HFXO initialization for external clock */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - 0, /* Minimal HFXO boost, 50% */ \ - _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ - false, /* Disable glitch detector */ \ - cmuOscMode_External, /* External digital clock */ \ - } -#endif /* _CMU_HFXOCTRL_MASK */ - -#if defined(CMU_OSCENCMD_DPLLEN) -/** DPLL initialization structure. - * Frequency will be Fref*(N+1)/(M+1). */ -typedef struct { - uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ - uint16_t n; /**< Factor N. 300 <= N <= 4095 */ - uint16_t m; /**< Factor M. M <= 4095 */ - uint8_t ssInterval; /**< Spread spectrum update interval. */ - uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ - CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ - CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ - CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ - bool autoRecover; /**< Enable automatic lock recovery. */ -} CMU_DPLLInit_TypeDef; - -/** - * DPLL initialization values for 39,998,805 Hz using LFXO as reference - * clock, M=2 and N=3661. - */ -#define CMU_DPLL_LFXO_TO_40MHZ \ - { \ - 39998805, /* Target frequency. */ \ - 3661, /* Factor N. */ \ - 2, /* Factor M. */ \ - 0, /* No spread spectrum clocking. */ \ - 0, /* No spread spectrum clocking. */ \ - cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true /* Enable automatic lock recovery. */ \ - } -#endif // CMU_OSCENCMD_DPLLEN - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); - -#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); -#endif - -uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); - -#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, - CMU_Osc_TypeDef upSel); -#endif - -uint32_t CMU_CalibrateCountGet(void); -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); - -#if defined(_SILICON_LABS_32B_SERIES_1) -void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); -uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); -#endif - -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); - -#if defined(CMU_OSCENCMD_DPLLEN) -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); -#endif -void CMU_FreezeEnable(bool enable); - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); -void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); - -#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); -void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); -#endif - -#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) -uint32_t CMU_HFRCOStartupDelayGet(void); -void CMU_HFRCOStartupDelaySet(uint32_t delay); -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); -void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); -uint32_t CMU_USHFRCOFreqGet(void); -#endif - -#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) -void CMU_HFXOAutostartEnable(uint32_t userSel, - bool enEM0EM1Start, - bool enEM0EM1StartSel); -#endif - -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); - -uint32_t CMU_LCDClkFDIVGet(void); -void CMU_LCDClkFDIVSet(uint32_t div); -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); -void CMU_LFXOPrecisionSet(uint16_t precision); -uint16_t CMU_LFXOPrecisionGet(void); -void CMU_HFXOPrecisionSet(uint16_t precision); -uint16_t CMU_HFXOPrecisionGet(void); - -void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); -bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode, - bool wait); -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) -void CMU_PCNTClockExternalSet(unsigned int instance, bool external); -bool CMU_PCNTClockExternalGet(unsigned int instance); -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); -void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); -uint32_t CMU_USHFRCOFreqGet(void); -#endif -void CMU_UpdateWaitStates(uint32_t freq, int vscale); - -#if defined(CMU_CALCTRL_CONT) -/***************************************************************************//** - * @brief - * Configure continuous calibration mode. - * @param[in] enable - * If true, enables continuous calibration, if false disables continuous - * calibration. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateCont(bool enable) -{ - BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); -} -#endif - -/***************************************************************************//** - * @brief - * Start calibration. - * @note - * This call is usually invoked after CMU_CalibrateConfig() and possibly - * CMU_CalibrateCont(). - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStart(void) -{ - CMU->CMD = CMU_CMD_CALSTART; -} - -#if defined(CMU_CMD_CALSTOP) -/***************************************************************************//** - * @brief - * Stop the calibration counters. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStop(void) -{ - CMU->CMD = CMU_CMD_CALSTOP; -} -#endif - -/***************************************************************************//** - * @brief - * Convert divider to logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param[in] div - * An unscaled divider. - * - * @return - * Logarithm base 2 (binary) value, i.e. exponent as used by fixed - * 2^n prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) -{ - uint32_t log2; - - /* Fixed 2^n prescalers take argument of 32768 or less. */ - EFM_ASSERT((div > 0U) && (div <= 32768U)); - - /* Count leading zeroes and "reverse" result */ - log2 = 31UL - __CLZ(div); - - return log2; -} - -#if defined(CMU_OSCENCMD_DPLLEN) -/***************************************************************************//** - * @brief - * Unlock DPLL. - * @note - * HFRCO is not turned off. - ******************************************************************************/ -__STATIC_INLINE void CMU_DPLLUnlock(void) -{ - CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; -} -#endif - -/***************************************************************************//** - * @brief - * Clear one or more pending CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntClear(uint32_t flags) -{ - CMU->IFC = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntDisable(uint32_t flags) -{ - CMU->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more CMU interrupts. - * - * @note - * Depending on use case, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling - * if the pending interrupt should be ignored. - * - * @param[in] flags - * CMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntEnable(uint32_t flags) -{ - CMU->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending CMU interrupts. - * - * @return - * CMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGet(void) -{ - return CMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending CMU interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * This function does not clear event bits. - * - * @return - * Pending and enabled CMU interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in CMU_IEN and - * - the pending interrupt flags CMU_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = CMU->IEN; - return CMU->IF & ien; -} - -/**************************************************************************//** - * @brief - * Set one or more pending CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void CMU_IntSet(uint32_t flags) -{ - CMU->IFS = flags; -} - -/***************************************************************************//** - * @brief - * Lock the CMU to protect some of its registers against unintended - * modification. - * - * @details - * See the reference manual for CMU registers that will be - * locked. - * - * @note - * If locking the CMU registers, they must be unlocked prior to using any - * CMU API functions modifying CMU registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_Lock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; -} - -/***************************************************************************//** - * @brief - * Unlock the CMU so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_Unlock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; -} - -#endif // defined(_SILICON_LABS_32B_SERIES_2) - -#if !defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Convert prescaler divider to a logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param[in] presc - * Prescaler value used to set the frequency divider. The divider is equal to - * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be - * equal to (divider - 1). - * - * @return - * Logarithm base 2 (binary) value, i.e. exponent as used by fixed - * 2^n prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) -{ - uint32_t log2; - - /* Integer prescalers take argument less than 32768. */ - EFM_ASSERT(presc < 32768U); - - /* Count leading zeroes and "reverse" result. Consider divider value to get - * exponent n from 2^n, so ('presc' +1). */ - log2 = 31UL - __CLZ(presc + (uint32_t) 1); - - /* Check that prescaler is a 2^n number. */ - EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); - - return log2; -} -#endif // !defined(_SILICON_LABS_32B_SERIES_0) - -/** @} (end addtogroup cmu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(CMU_PRESENT) */ -#endif /* EM_CMU_H */ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CMU_H +#define EM_CMU_H + +#include "em_device.h" +#if defined(CMU_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu_compat.h" +#include "em_gpio.h" +#include "sl_common.h" +#include "sl_enum.h" +#include "sl_status.h" +#include "sli_em_cmu.h" +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup cmu + * @{ + ******************************************************************************/ + +/** Macro to set clock sources in the clock tree. */ +#define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 0U +#define CMU_EN_BIT_MASK 0x1FU + +/* Enable register ID's for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CLKEN0_EN_REG 1 +#define CMU_CLKEN1_EN_REG 2 +#if defined(_CMU_CLKEN2_MASK) +#define CMU_CLKEN2_EN_REG 3 +#endif +#define CMU_CRYPTOACCCLKCTRL_EN_REG 3 +#define CMU_EN_REG_POS 5U +#define CMU_EN_REG_MASK 0x3U + +/* Clock branch ID's internal use. */ +#define CMU_CORE_BRANCH 0 +#define CMU_SYSCLK_BRANCH 1 +#define CMU_SYSTICK_BRANCH 2 +#define CMU_HCLK_BRANCH 3 +#define CMU_EXPCLK_BRANCH 4 +#define CMU_PCLK_BRANCH 5 +#define CMU_LSPCLK_BRANCH 6 +#define CMU_TRACECLK_BRANCH 7 +#define CMU_EM01GRPACLK_BRANCH 8 +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) +#define CMU_EM01GRPBCLK_BRANCH 9 +#endif +#define CMU_EUART0CLK_BRANCH 10 +#define CMU_IADCCLK_BRANCH 11 +#define CMU_EM23GRPACLK_BRANCH 12 +#define CMU_WDOG0CLK_BRANCH 13 +#if defined(RTCC_PRESENT) +#define CMU_RTCCCLK_BRANCH 14 +#elif defined(SYSRTC_PRESENT) +#define CMU_SYSRTCCLK_BRANCH 14 +#endif +#define CMU_EM4GRPACLK_BRANCH 15 +#if defined(PDM_PRESENT) +#define CMU_PDMREF_BRANCH 16 +#endif +#define CMU_DPLLREFCLK_BRANCH 17 +#if WDOG_COUNT > 1 +#define CMU_WDOG1CLK_BRANCH 18 +#endif +#if defined(LCD_PRESENT) +#define CMU_LCD_BRANCH 19 +#endif +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_BRANCH 20 +#endif +#if defined(PCNT_PRESENT) +#define CMU_PCNT_BRANCH 21 +#endif +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHF_BRANCH 22 +#define CMU_LESENSE_BRANCH 23 +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_BRANCH 24 +#endif +#if defined(VDAC_PRESENT) && (VDAC_COUNT > 1) +#define CMU_VDAC1_BRANCH 25 +#endif +#define CMU_CLK_BRANCH_POS 7U +#define CMU_CLK_BRANCH_MASK 0x1FU +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_EMU_CMD_EM01VSCALE1_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL +#endif + +/* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 1 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Disable clocks configuration */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#endif // (_SILICON_LABS_32B_SERIES_2) + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +/** HFRCODPLL frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) { + cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ + cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ + cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ + cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ + cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ + cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */ +#endif + cmuHFRCODPLLFreq_UserDefined = 0, +}; + +#if defined(USBPLL_PRESENT) +/** HFXO reference frequency */ +SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) { + cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */ + cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (25UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */ + cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (16UL << _USBPLL_CTRL_DIVX_SHIFT) + | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */ + cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */ +}; +#endif + +/** HFRCODPLL maximum frequency */ +#define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz +/** HFRCODPLL minimum frequency */ +#define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz + +#if defined(HFRCOEM23_PRESENT) +/** HFRCOEM23 frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) { + cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ + cmuHFRCOEM23Freq_UserDefined = 0, +}; + +/** HFRCOEM23 maximum frequency */ +#define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz +/** HFRCOEM23 minimum frequency */ +#define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz +#endif // defined(HFRCOEM23_PRESENT) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Clock points in CMU clock-tree. */ +SL_ENUM(CMU_Clock_TypeDef) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK, /**< System clock. */ + cmuClock_HCLK, /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK, /**< Export clock. */ + cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ + cmuClock_IADCCLK, /**< IADC clock. */ + cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ + cmuClock_WDOG0CLK, /**< WDOG0 clock. */ + cmuClock_WDOG1CLK, /**< WDOG1 clock. */ + cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ + cmuClock_TRACECLK, /**< Debug trace clock. */ + cmuClock_RTCCCLK, /**< RTCC clock. */ + cmuClock_HFRCOEM23, + + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_CORE, /**< Cortex-M33 core clock. */ + cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ + cmuClock_ACMP0, /**< ACMP0 clock. */ + cmuClock_ACMP1, /**< ACMP1 clock. */ + cmuClock_BURTC, /**< BURTC clock. */ + cmuClock_GPCRC, /**< GPCRC clock. */ + cmuClock_GPIO, /**< GPIO clock. */ + cmuClock_I2C0, /**< I2C0 clock. */ + cmuClock_I2C1, /**< I2C1 clock. */ + cmuClock_IADC0, /**< IADC clock. */ + cmuClock_LDMA, /**< LDMA clock. */ + cmuClock_LETIMER0, /**< LETIMER clock. */ + cmuClock_PRS, /**< PRS clock. */ + cmuClock_RTCC, /**< RTCC clock. */ + cmuClock_TIMER0, /**< TIMER0 clock. */ + cmuClock_TIMER1, /**< TIMER1 clock. */ + cmuClock_TIMER2, /**< TIMER2 clock. */ + cmuClock_TIMER3, /**< TIMER3 clock. */ + cmuClock_USART0, /**< USART0 clock. */ + cmuClock_USART1, /**< USART1 clock. */ + cmuClock_USART2, /**< USART2 clock. */ + cmuClock_WDOG0, /**< WDOG0 clock. */ + cmuClock_WDOG1, /**< WDOG1 clock. */ + cmuClock_PDM /**< PDM clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/** Clock points in CMU clock-tree. */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */ + cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */ + cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */ + cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */ + cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */ + cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */ +#if defined(PDM_PRESENT) + cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */ +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */ +#endif +#if defined(EUART_PRESENT) + cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */ +#elif defined(EUSART_PRESENT) + cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */ +#endif + cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */ + cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */ + cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */ +#endif +#if defined(RTCC_PRESENT) + cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */ +#elif defined(SYSRTC_PRESENT) + cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */ +#endif + cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */ + cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */ +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */ + cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */ +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */ + cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */ +#endif + + cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */ +#if defined(PDM_PRESENT) + cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */ +#endif + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */ + cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */ +#if defined(RADIOAES_PRESENT) + cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */ +#endif + cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */ + cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */ + cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */ + cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */ + cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */ +#if defined(_CMU_CLKEN2_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN1_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN0_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN1_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN0_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN1_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN0_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN1_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN0_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER8_SHIFT) + cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER9_SHIFT) + cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 0 + cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 1 +#if defined(_CMU_CLKEN0_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#elif defined(_CMU_CLKEN2_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#endif +#endif /* defined(USART_PRESENT) && USART_COUNT > 1 */ +#if defined(USART_PRESENT) && USART_COUNT > 2 + cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */ +#endif /* defined(USART_PRESENT) && USART_COUNT > 2 */ +#if defined(IADC_PRESENT) + cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */ +#endif + cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */ +#if defined(LETIMER_PRESENT) + cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */ +#endif + cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */ +#endif +#if defined(I2C_PRESENT) + cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */ +#if I2C_COUNT > 1 + cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */ +#endif /* I2C_COUNT > 1 */ +#if I2C_COUNT > 2 + cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */ +#endif /* I2C_COUNT > 2 */ +#if I2C_COUNT > 3 + cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */ +#endif /* I2C_COUNT > 3 */ +#endif /* defined(I2C_PRESENT) */ + cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */ + cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */ + cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */ +#if defined(HFRCOEM23_PRESENT) + cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */ +#endif +#if defined(HFXO_PRESENT) + cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */ +#endif + cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */ + cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */ + cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */ + cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */ +#if defined(EUART_PRESENT) + cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */ +#endif +#if defined(PDM_PRESENT) + cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */ +#endif + cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */ + cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */ + cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */ + cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */ +#if defined(RTCC_PRESENT) + cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */ +#endif + cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */ +#if defined(SYSRTC_PRESENT) + cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#if defined(_CMU_CLKEN1_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#elif defined(_CMU_CLKEN2_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#if defined(_CMU_CLKEN1_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#elif defined(_CMU_CLKEN2_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#if defined(_CMU_CLKEN1_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#elif defined(_CMU_CLKEN2_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */ +#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) + cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */ +#endif +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */ +#endif +#if defined(SEMAILBOX_PRESENT) + cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */ +#endif + cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */ +#if defined(ICACHE_PRESENT) + cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */ +#endif +#if defined(ACMP_PRESENT) + cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */ +#if ACMP_COUNT > 1 + cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */ +#endif +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */ +#endif +#if defined(DMEM_PRESENT) + cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */ +#endif +#if defined(KEYSCAN_PRESENT) + cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */ +#endif +#if defined(MVP_PRESENT) + cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */ +#endif + cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */ +#if defined(USB_PRESENT) + cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */ +#endif +#if defined(ETAMPDET_PRESENT) + cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ + cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuOsc_HFXO, /**< High frequency crystal oscillator. */ + cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +}; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS /**< PRS input as clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */ +#endif + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_SYSCLK, /**< System clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */ +#endif + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS, /**< PRS input as clock. */ +#if defined(PCNT_PRESENT) + cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */ +#endif + cmuSelect_TEMPOSC, /**< Temperature oscillator. */ + cmuSelect_PFMOSC, /**< PFM oscillator. */ + cmuSelect_BIASOSC, /**< BIAS oscillator. */ +#if defined(USBPLL_PRESENT) + cmuSelect_USBPLL0, /**< PLL clock for USB. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** DPLL reference clock edge detect selector. */ +SL_ENUM(CMU_DPLLEdgeSel_TypeDef) { + cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ +}; + +/** LFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) { + cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ + cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ +}; + +/** LFXO start-up timeout delay. */ +SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) { + cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ + cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ + cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ + cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ + cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ + cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ + cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ + cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ +}; + +/** HFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) { + cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ +#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) + cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */ +#endif +}; + +/** HFXO core bias LSB change timeout. */ +SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) { + cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ + cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ + cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ + cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ + cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ + cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ + cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ + cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ + cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ + cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ + cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ + cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ + cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ + cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ + cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ + cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ +}; + +/** HFXO steady state timeout. */ +SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) { + cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ + cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ + cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ + cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ + cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ + cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ + cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ + cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ + cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ + cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ + cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ + cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ + cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ + cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ + cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ +#if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US) + cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ +#endif +}; + +/** HFXO core degeneration control. */ +SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) { + cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ + cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ + cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ + cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ +}; + +/** HFXO XI and XO pin fixed capacitor control. */ +SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) { + cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ + cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ + cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ + cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ +}; + +/** Oscillator precision modes. */ +SL_ENUM(CMU_Precision_TypeDef) { + cmuPrecisionDefault, /**< Default precision mode. */ + cmuPrecisionHigh, /**< High precision mode. */ +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + uint8_t gain; /**< Startup gain. */ + uint8_t capTune; /**< Internal capacitance tuning. */ + CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ + CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool highAmplitudeEn; /**< High amplitude enable. */ + bool agcEn; /**< AGC enable. */ + bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ + bool failDetEn; /**< Oscillator failure detection enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Lock register access. */ +} CMU_LFXOInit_TypeDef; + +/** Default LFXO initialization values for XTAL mode. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + 1, \ + 38, \ + cmuLfxoStartupDelay_4KCycles, \ + cmuLfxoOscMode_Crystal, \ + false, /* highAmplitudeEn */ \ + true, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external clock mode. */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_External, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external sine mode. */ +#define CMU_LFXOINIT_EXTERNAL_SINE \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_AcCoupledSine, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ + uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ + uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ + uint8_t coreBiasStartup; /**< Core bias startup current. */ + uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ + CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ + CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ + uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ + uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ + uint8_t coreBiasAna; /**< Core bias current. */ + bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ + CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool forceXo2GndAna; /**< Force XO pin to ground. */ + bool forceXi2GndAna; /**< Force XI pin to ground. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ +#if defined(HFXO_CTRL_EM23ONDEMAND) + bool em23OnDemand; /**< Enable deep sleep. */ +#endif + bool regLock; /**< Lock register access. */ +} CMU_HFXOInit_TypeDef; + +#if defined(HFXO_CTRL_EM23ONDEMAND) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// See [PM-2871] for details. +/** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) +// See [PM-5131] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG24 + * when high power PA is present and output dBm equal 20 dBm. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +// See [PM-5638] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG25 + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#else +/** + * Default configuration of fixed tuning capacitance on XO and XI. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both +#endif + +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } +#else +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_Both, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } +#endif + +#if defined(_HFXO_BUFOUTCTRL_MASK) + +/** Crystal sharing timeout start up timeout. */ +SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) { + startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */ + startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */ + startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */ + startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */ + startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */ + startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */ + startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */ + startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */ + startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */ + startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */ + startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */ + startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */ + startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */ + startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */ + startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */ + startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */ +}; + +/** Crystal sharing leader initialization structure. */ +typedef struct { + bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */ + CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */ +} CMU_BUFOUTLeaderInit_TypeDef; + +/** Default crystal sharing master initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \ + { \ + true, /* minimalStartupDelay */ \ + startupTimeout208Us, /* timeoutStartup */ \ + } +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/** PRS status select output signal. */ +SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) { + PRS_Status_select_0, /**< PRS status 0 output signal. */ + PRS_Status_select_1 /**< PRS status 1 output signal. */ +}; + +/** Crystal sharing follower initialization structure. */ +typedef struct { + CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */ + bool em23OnDemand; /**< Enable em23 on demand. */ + bool regLock; /**< Lock registers. */ +} CMU_CrystalSharingFollowerInit_TypeDef; + +/** Default crystal sharing follower initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \ + { \ + PRS_Status_select_0, /* prsStatusSelectOutput */ \ + true, /* em23OnDemand */ \ + false /* regLock */ \ + } +#endif + +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + CMU_Select_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ + bool ditherEn; /**< Enable dither functionality. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 76,800,000 Hz using HFXO as reference + * clock, M = 1919, N = 3839 + */ +#define CMU_DPLL_HFXO_TO_76_8MHZ \ + { \ + 76800000, /* Target frequency. */ \ + 3839, /* Factor N. */ \ + 1919, /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 80,000,000 Hz using HFXO as reference + * clock, M = 1919, N = 3999. + */ +#define CMU_DPLL_HFXO_TO_80MHZ \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * Default configurations for DPLL initialization. When using this macro + * you need to modify the N and M factor and the desired frequency to match + * the components placed on the board. + */ +#define CMU_DPLLINIT_DEFAULT \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +#if defined(USBPLL_PRESENT) +/** USB PLL initialization structure. */ +typedef struct { + CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */ + bool shuntRegEn; /**< Shunt regulator enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ +} CMU_USBPLL_Init_TypeDef; + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38 MHz. + */ +#define CMU_USBPLL_REFFREQ_38MHZ \ + { \ + cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38.4 MHz. + */ +#define CMU_USBPLL_REFFREQ_38_4MHZ \ + { \ + cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 39 MHz. + */ +#define CMU_USBPLL_REFFREQ_39MHZ \ + { \ + cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 40 MHz. + */ +#define CMU_USBPLL_REFFREQ_40MHZ \ + { \ + cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } +#endif + +#if defined(RFFPLL_PRESENT) +/** + * RFF PLL initialization structure. + * When using this structure you need to modify the X, Y and N factor + * and the desired host target frequency to match the components placed + * on the board (namely the RFFPLL reference clock). + * X, Y, N values for a 39MHz HFXO: + * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY + * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2) + */ +typedef struct { + uint32_t frequency; /**< Host target frequency. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ + uint8_t dividerY; /**< Divider Y for digital. */ + uint8_t dividerX; /**< Divider X for Radio. */ + uint8_t dividerN; /**< Feedback divider N. */ +} CMU_RFFPLL_Init_TypeDef; + +/** Radio frequency locked loop default initialization values. */ +#define CMU_RFFPLL_DEFAULT \ + { \ + 100000000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \ + _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \ + _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \ + } + +/** Radio frequency locked loop initialization values for 97.5MHz. */ +#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \ + { \ + 97500000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + 20U, /* Divider Y for digital. */ \ + 6U, /* Divider X for Radio. */ \ + 100U /* Feedback divider N. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, + CMU_Select_TypeDef reference); +void CMU_CalibrateConfig(uint32_t downCycles, + CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel); +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClkOutPinConfig(uint32_t clkno, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkdiv, + GPIO_Port_TypeDef port, + unsigned int pin); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, + CMU_ClkDiv_TypeDef div); +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +#endif +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, + CMU_Select_TypeDef ref); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#if defined(USBPLL_PRESENT) +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitUSBPLLLock(void); +#endif +#if defined(RFFPLL_PRESENT) +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitRFFPLLLock(void); +#endif +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); +#if defined(HFXO0_BUFOUT) +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +sl_status_t CMU_HFXOCTuneSet(uint32_t ctune); +uint32_t CMU_HFXOCTuneGet(void); +void CMU_HFXOCTuneDeltaSet(int32_t delta); +int32_t CMU_HFXOCTuneDeltaGet(void); +void CMU_HFXOCoreBiasCurrentCalibrate(void); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); +#if defined(PLFRCO_PRESENT) +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision); +#endif +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, + uint32_t val); +void CMU_UpdateWaitStates(uint32_t freq, int vscale); +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); + +#if defined(HFRCOEM23_PRESENT) +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +__STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + (void)clock; + (void)enable; +} +#endif + +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly + * @ref CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTART; +} + +/***************************************************************************//** + * @brief + * Stop calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTOP; +} + +/***************************************************************************//** + * @brief + * Unlock the DPLL. + * @note + * The HFRCODPLL oscillator is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { + } +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupt flags. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupt sources. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to + * enabling if such a pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupt sources. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Lock CMU register access in order to protect registers contents against + * unintended modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +__STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, + bool enable, + bool wait) +{ + (void)osc; + (void)enable; + (void)wait; +} + +/***************************************************************************//** + * @brief + * Unlock CMU register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Lock WDOG register access in order to protect registers contents against + * unintended modification. + * + * @note + * If locking the WDOG registers, they must be unlocked prior to using any + * emlib API functions modifying registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogLock(void) +{ + CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Unlock WDOG register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogUnlock(void) +{ + CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for USB PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitUSBPLLLock() +{ + while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) + != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { + /* Wait for USB PLL lock and ready */ + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for RFF PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitRFFPLLLock() +{ + while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) + != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { + /* Wait for RFF PLL lock and ready. */ + } +} +#endif + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Select register IDs for internal use. */ +#define CMU_NOSEL_REG 0 +#define CMU_HFCLKSEL_REG 1 +#define CMU_LFACLKSEL_REG 2 +#define CMU_LFBCLKSEL_REG 3 +#define CMU_LFCCLKSEL_REG 4 +#define CMU_LFECLKSEL_REG 5 +#define CMU_DBGCLKSEL_REG 6 +#define CMU_USBCCLKSEL_REG 7 +#define CMU_ADC0ASYNCSEL_REG 8 +#define CMU_ADC1ASYNCSEL_REG 9 +#define CMU_SDIOREFSEL_REG 10 +#define CMU_QSPI0REFSEL_REG 11 +#define CMU_USBRCLKSEL_REG 12 +#define CMU_PDMREFSEL_REG 13 + +#define CMU_SEL_REG_POS 0U +#define CMU_SEL_REG_MASK 0xfU + +/* Divisor/prescaler register IDs for internal use. */ +#define CMU_NODIV_REG 0 +#define CMU_NOPRESC_REG 0 +#define CMU_HFPRESC_REG 1 +#define CMU_HFCLKDIV_REG 1 +#define CMU_HFEXPPRESC_REG 2 +#define CMU_HFCLKLEPRESC_REG 3 +#define CMU_HFPERPRESC_REG 4 +#define CMU_HFPERCLKDIV_REG 4 +#define CMU_HFPERPRESCB_REG 5 +#define CMU_HFPERPRESCC_REG 6 +#define CMU_HFCOREPRESC_REG 7 +#define CMU_HFCORECLKDIV_REG 7 +#define CMU_LFAPRESC0_REG 8 +#define CMU_LFBPRESC0_REG 9 +#define CMU_LFEPRESC0_REG 10 +#define CMU_ADCASYNCDIV_REG 11 +#define CMU_HFBUSPRESC_REG 12 +#define CMU_HFCORECLKLEDIV_REG 13 + +#define CMU_PRESC_REG_POS 4U +#define CMU_DIV_REG_POS CMU_PRESC_REG_POS +#define CMU_PRESC_REG_MASK 0xfU +#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK + +/* Enable register IDs for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CTRL_EN_REG 1 +#define CMU_HFPERCLKDIV_EN_REG 1 +#define CMU_HFPERCLKEN0_EN_REG 2 +#define CMU_HFCORECLKEN0_EN_REG 3 +#define CMU_PDMREF_EN_REG 4 +#define CMU_HFBUSCLKEN0_EN_REG 5 +#define CMU_LFACLKEN0_EN_REG 6 +#define CMU_LFBCLKEN0_EN_REG 7 +#define CMU_LFCCLKEN0_EN_REG 8 +#define CMU_LFECLKEN0_EN_REG 9 +#define CMU_PCNT_EN_REG 10 +#define CMU_SDIOREF_EN_REG 11 +#define CMU_QSPI0REF_EN_REG 12 +#define CMU_QSPI1REF_EN_REG 13 +#define CMU_HFPERCLKEN1_EN_REG 14 +#define CMU_USBRCLK_EN_REG 15 + +#define CMU_EN_REG_POS 8U +#define CMU_EN_REG_MASK 0xfU + +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 12U +#define CMU_EN_BIT_MASK 0x1fU + +/* Clock branch bitfield positions, for internal use. */ +#define CMU_HF_CLK_BRANCH 0 +#define CMU_HFCORE_CLK_BRANCH 1 +#define CMU_HFPER_CLK_BRANCH 2 +#define CMU_HFPERB_CLK_BRANCH 3 +#define CMU_HFPERC_CLK_BRANCH 4 +#define CMU_HFBUS_CLK_BRANCH 5 +#define CMU_HFEXP_CLK_BRANCH 6 +#define CMU_DBG_CLK_BRANCH 7 +#define CMU_AUX_CLK_BRANCH 8 +#define CMU_RTC_CLK_BRANCH 9 +#define CMU_RTCC_CLK_BRANCH 10 +#define CMU_LETIMER0_CLK_BRANCH 11 +#define CMU_LETIMER1_CLK_BRANCH 12 +#define CMU_LEUART0_CLK_BRANCH 13 +#define CMU_LEUART1_CLK_BRANCH 14 +#define CMU_LFA_CLK_BRANCH 15 +#define CMU_LFB_CLK_BRANCH 16 +#define CMU_LFC_CLK_BRANCH 17 +#define CMU_LFE_CLK_BRANCH 18 +#define CMU_USBC_CLK_BRANCH 19 +#define CMU_USBLE_CLK_BRANCH 20 +#define CMU_LCDPRE_CLK_BRANCH 21 +#define CMU_LCD_CLK_BRANCH 22 +#define CMU_LESENSE_CLK_BRANCH 23 +#define CMU_CSEN_LF_CLK_BRANCH 24 +#define CMU_ADC0ASYNC_CLK_BRANCH 25 +#define CMU_ADC1ASYNC_CLK_BRANCH 26 +#define CMU_SDIOREF_CLK_BRANCH 27 +#define CMU_QSPI0REF_CLK_BRANCH 28 +#define CMU_USBR_CLK_BRANCH 29 +#define CMU_PDMREF_CLK_BRANCH 30 +#define CMU_HFLE_CLK_BRANCH 31 + +#define CMU_CLK_BRANCH_POS 17U +#define CMU_CLK_BRANCH_MASK 0x1fU + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL +#endif + +/* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 2 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define USBC_CLOCK_PRESENT +#endif +#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) +#define USBR_CLOCK_PRESENT +#endif +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock divisors. These values are valid for prescalers. */ +#define cmuClkDiv_1 1 /**< Divide clock by 1. */ +#define cmuClkDiv_2 2 /**< Divide clock by 2. */ +#define cmuClkDiv_4 4 /**< Divide clock by 4. */ +#define cmuClkDiv_8 8 /**< Divide clock by 8. */ +#define cmuClkDiv_16 16 /**< Divide clock by 16. */ +#define cmuClkDiv_32 32 /**< Divide clock by 32. */ +#define cmuClkDiv_64 64 /**< Divide clock by 64. */ +#define cmuClkDiv_128 128 /**< Divide clock by 128. */ +#define cmuClkDiv_256 256 /**< Divide clock by 256. */ +#define cmuClkDiv_512 512 /**< Divide clock by 512. */ +#define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ +#define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ +#define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ +#define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ +#define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ +#define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) +/** Clockprescaler configuration */ +typedef uint32_t CMU_ClkPresc_TypeDef; +#endif + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) { + cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ + cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ + cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ + cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ + cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ +#if defined(CMU_HFRCOCTRL_BAND_28MHZ) + cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ +#endif +}; +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) { + cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ + cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ + cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ + cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ + cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ +#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) + cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ +#endif +}; +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/** Universal serial high-frequency RC bands */ +SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) { + /** 24 MHz RC band. */ + cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, + /** 48 MHz RC band. */ + cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, +}; +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/** High-USHFRCO bands */ +SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) { + cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ + cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ + cmuUSHFRCOFreq_UserDefined = 0, +}; +/** USHFRCO minimum frequency */ +#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz +/** USHFRCO maximum frequency */ +#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz +#endif + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) { + cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_HFRCOCAL13_MASK) + cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL14_MASK) + cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL15_MASK) + cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL16_MASK) + cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ +#endif + cmuHFRCOFreq_UserDefined = 0, +}; + +/** HFRCO minimum frequency. */ +#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz +#if defined(_DEVINFO_HFRCOCAL16_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz +#elif defined(_DEVINFO_HFRCOCAL15_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz +#elif defined(_DEVINFO_HFRCOCAL14_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz +#elif defined(_DEVINFO_HFRCOCAL13_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz +#else +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz +#endif +#endif + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) { + cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ +#endif + cmuAUXHFRCOFreq_UserDefined = 0, +}; +/** AUXHFRCO minimum frequency. */ +#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz +#elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz +#else +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz +#endif +#endif + +/** Clock points in CMU. See CMU overview in the reference manual. */ +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* HF clock branch */ + /*******************/ + + /** High-frequency clock */ +#if defined(_CMU_CTRL_HFCLKDIV_MASK) \ + || defined(_CMU_HFPRESC_MASK) + cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Debug clock */ + cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** AUX clock */ + cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(_CMU_HFEXPPRESC_MASK) + /**********************/ + /* HF export sub-branch */ + /**********************/ + + /** Export clock */ + cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) +/**********************************/ +/* HF bus clock sub-branch */ +/**********************************/ + + /** High-frequency bus clock */ +#if defined(_CMU_HFBUSPRESC_MASK) + cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO) + /** Cryptography accelerator clock */ + cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO0) + /** Cryptography accelerator 0 clock */ + cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO1) + /** Cryptography accelerator 1 clock */ + cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_LDMA) + /** Direct-memory access controller clock */ + cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_QSPI0) + /** Quad SPI clock */ + cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPCRC) + /** General-purpose cyclic redundancy checksum clock */ + cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Low-energy clock divided down from HFCLK */ + cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFBUSCLKEN0_PRS) + /** Peripheral reflex system clock */ + cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* HF peripheral clock sub-branch */ + /**********************************/ + + /** High-frequency peripheral clock */ +#if defined(_CMU_HFPRESC_MASK) + cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCB_MASK) + /** Branch B figh-frequency peripheral clock */ + cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + /** Branch C figh-frequency peripheral clock */ + cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PDM) + /** PDM clock */ + cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF1) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART1) + /** Universal sync/async receiver/transmitter 1 clock */ + cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART2) + /** Universal sync/async receiver/transmitter 2 clock */ + cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_USART3) + /** Universal sync/async receiver/transmitter 3 clock */ + cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART4) + /** Universal sync/async receiver/transmitter 4 clock */ + cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART5) + /** Universal sync/async receiver/transmitter 5 clock */ + cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART0) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART0_MASK) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART1) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART1_MASK) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER0) + /** Timer 0 clock */ + cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER1) + /** Timer 1 clock */ + cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER2) + /** Timer 2 clock */ + cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER3) + /** Timer 3 clock */ + cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER4) + /** Timer 4 clock */ + cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER5) + /** Timer 5 clock */ + cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER6) + /** Timer 6 clock */ + cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER2) + /** Wide-timer 2 clock */ + cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER3) + /** Wide-timer 3 clock */ + cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CRYOTIMER) + /** CRYOtimer clock */ + cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP0) + /** Analog comparator 0 clock */ + cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP1) + /** Analog comparator 1 clock */ + cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP2) + /** Analog comparator 2 clock */ + cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP3) + /** Analog comparator 3 clock */ + cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PRS) + /** Peripheral-reflex system clock */ + cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_DAC0) + /** Digital-to-analog converter 0 clock */ + cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_IDAC0) + /** Current digital-to-analog converter 0 clock */ + cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VCMP) + /** Voltage comparator clock */ + cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ADC0) + /** Analog-to-digital converter 0 clock */ + cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ADC1) + /** Analog-to-digital converter 1 clock */ + cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_I2C0) + /** I2C 0 clock */ + cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C1) + /** I2C 1 clock */ + cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C2) + /** I2C 2 clock */ + cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TRNG0) + /** True random number generator clock */ + cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN0_MASK) + /** Controller Area Network 0 clock */ + cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN1_MASK) + /** Controller Area Network 1 clock. */ + cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /**********************/ + /* HF core sub-branch */ + /**********************/ + + /** Core clock */ + cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFCORECLKEN0_AES) + /** Advanced encryption standard accelerator clock */ + cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_DMA) + /** Direct memory access controller clock */ + cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_LE) + /** Low-energy clock divided down from HFCORECLK */ + cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_EBI) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_ETH_MASK) + /** Ethernet clock */ + cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) + /** SDIO clock */ + cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(USBC_CLOCK_PRESENT) + /** USB Core clock */ + cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined (USBR_CLOCK_PRESENT) + /** USB Rate clock */ + cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) + | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFBUSCLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF A branch */ + /***************/ + + /** Low-frequency A clock */ + cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFACLKEN0_RTC) + /** Real time counter clock */ + cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER0) + /** Low-energy timer 0 clock */ + cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER1) + /** Low-energy timer 1 clock */ + cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LCD) + /** Liquid crystal display, pre FDIV clock */ + cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Liquid crystal display clock. Note that FDIV prescaler + * must be set by special API. */ + cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) + | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT0CLKEN) + /** Pulse counter 0 clock */ + cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT1CLKEN) + /** Pulse counter 1 clock */ + cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT2CLKEN) + /** Pulse counter 2 clock */ + cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined(CMU_LFACLKEN0_LESENSE) + /** LESENSE clock */ + cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) + | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF B branch */ + /***************/ + + /** Low-frequency B clock */ + cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFBCLKEN0_LEUART0) + /** Low-energy universal asynchronous receiver/transmitter 0 clock */ + cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_CSEN) + /** Capacitive Sense LF clock */ + cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_LEUART1) + /** Low-energy universal asynchronous receiver/transmitter 1 clock */ + cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_SYSTICK) + /** Cortex SYSTICK LF clock */ + cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_LFCCLKEN0_MASK) + /***************/ + /* LF C branch */ + /***************/ + + /** Low-frequency C clock */ + cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFCCLKEN0_USBLE) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_LFCCLKEN0_USB) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + /***************/ + /* LF E branch */ + /***************/ + + /** Low-frequency E clock */ + cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Real-time counter and calendar clock */ +#if defined (CMU_LFECLKEN0_RTCC) + cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* Asynchronous peripheral clocks */ + /**********************************/ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + /** ADC0 asynchronous clock */ + cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + /** ADC1 asynchronous clock */ + cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) + /** SDIO reference clock */ + cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) + /** QSPI0 reference clock */ + cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) + | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) + | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) + /** PDM reference clock */ + cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +}; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Clock_TypeDef member */ +#define cmuClock_CORELE cmuClock_HFLE +/** @endcond */ + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ + cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ + cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ + cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuOsc_CLKIN0, /**< External oscillator. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +/** Oscillator modes. */ +SL_ENUM(CMU_OscMode_TypeDef) { + cmuOscMode_Crystal, /**< Crystal oscillator. */ + cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ + cmuOscMode_External, /**< External digital clock. */ +}; + +/** Selectable clock sources. */ +SL_ENUM(CMU_Select_TypeDef) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ + cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */ + cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko). */ +#if defined(CMU_STATUS_USHFRCOENS) + cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ +#endif +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ +#endif +#if defined(CMU_HFXOCTRL_HFXOX2EN) + cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuSelect_CLKIN0, /**< External clock input. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +#if defined(CMU_HFCORECLKEN0_LE) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Select_TypeDef member */ +#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE +/** @endcond */ +#endif + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/** HFXO tuning modes */ +SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) { + cmuHFXOTuningMode_Auto = 0, + cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ + cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ + | CMU_CMD_HFXOSHUNTOPTSTART, +#endif +}; +#endif + +#if defined(_CMU_CTRL_LFXOBOOST_MASK) +/** LFXO Boost values. */ +SL_ENUM(CMU_LFXOBoost_TypeDef) { + cmuLfxoBoost70 = 0x0, + cmuLfxoBoost100 = 0x2, +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + cmuLfxoBoost70Reduced = 0x1, + cmuLfxoBoost100Reduced = 0x3, +#endif +}; +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL reference clock selector. */ +SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) { + cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ + cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ + cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ +}; + +/** DPLL reference clock edge detect selector. */ +SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) { + cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ +}; +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_CMU_LFXOCTRL_MASK) + uint8_t ctune; /**< CTUNE (load capacitance) value */ + uint8_t gain; /**< Gain/max startup margin */ +#else + CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ +#endif + uint8_t timeout; /**< Startup delay */ + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_LFXOInit_TypeDef; + +#if defined(_CMU_LFXOCTRL_MASK) +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ + _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ + _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* No CTUNE value needed */ \ + 0, /* No LFXO startup gain */ \ + _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#else +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ + cmuOscMode_External, \ + } +#endif + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#elif defined(_CMU_HFXOCTRL_MASK) + bool lowPowerMode; /**< Enable low-power mode */ + bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint8_t regIshSteadyState; /**< Shunt steady-state current */ + uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t thresholdPeakDetect; /**< Peak detection threshold */ + uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#else + uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ + uint8_t timeout; /**< Startup delay */ + bool glitchDetector; /**< Enable/disable glitch detector */ +#endif + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_HFXOInit_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) +/** Default HFXO init. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_External, \ + } +#elif defined(_CMU_HFXOCTRL_MASK) +/** + * Default HFXO initialization values for Platform 2 devices, which contain a + * separate HFXOCTRL register. + */ +#if defined(_EFR_DEVICE) +#define CMU_HFXOINIT_DEFAULT \ + { \ + false, /* Low-noise mode for EFR32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default Shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state XO core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#else /* EFM32 device */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + true, /* Low-power mode for EFM32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#endif /* _EFR_DEVICE */ +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + true, /* Low-power mode */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + 0, /* Startup CTUNE=0 recommended for external clock */ \ + 0, /* Steady CTUNE=0 recommended for external clock */ \ + 0xA, /* Default shunt steady-state current */ \ + 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ + 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0x0, /* Peak-detect not recommended for external clock usage */ \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ + cmuOscMode_External, \ + } +#else /* _CMU_HFXOCTRL_MASK */ +/** + * Default HFXO initialization values for Platform 1 devices. + */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ + _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default HFXO initialization for external clock */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* Minimal HFXO boost, 50% */ \ + _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#endif /* _CMU_HFXOCTRL_MASK */ + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + uint8_t ssInterval; /**< Spread spectrum update interval. */ + uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ + CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + 0, /* No spread spectrum clocking. */ \ + 0, /* No spread spectrum clocking. */ \ + cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true /* Enable automatic lock recovery. */ \ + } +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); + +#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); +#endif + +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel); +#endif + +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); + +#if defined(_SILICON_LABS_32B_SERIES_1) +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); +#endif + +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); + +#if defined(CMU_OSCENCMD_DPLLEN) +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#endif +void CMU_FreezeEnable(bool enable); + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); + +#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); +#endif + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +uint32_t CMU_HFRCOStartupDelayGet(void); +void CMU_HFRCOStartupDelaySet(uint32_t delay); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); +uint32_t CMU_USHFRCOFreqGet(void); +#endif + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel); +#endif + +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); + +uint32_t CMU_LCDClkFDIVGet(void); +void CMU_LCDClkFDIVSet(uint32_t div); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); + +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait); +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); +bool CMU_PCNTClockExternalGet(unsigned int instance); +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); +uint32_t CMU_USHFRCOFreqGet(void); +#endif +void CMU_UpdateWaitStates(uint32_t freq, int vscale); + +#if defined(CMU_CALCTRL_CONT) +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} +#endif + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after CMU_CalibrateConfig() and possibly + * CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CMD = CMU_CMD_CALSTART; +} + +#if defined(CMU_CMD_CALSTOP) +/***************************************************************************//** + * @brief + * Stop the calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CMD = CMU_CMD_CALSTOP; +} +#endif + +/***************************************************************************//** + * @brief + * Convert divider to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] div + * An unscaled divider. + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) +{ + uint32_t log2; + + /* Fixed 2^n prescalers take argument of 32768 or less. */ + EFM_ASSERT((div > 0U) && (div <= 32768U)); + + /* Count leading zeroes and "reverse" result */ + log2 = 31UL - __CLZ(div); + + return log2; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/***************************************************************************//** + * @brief + * Unlock DPLL. + * @note + * HFRCO is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; +} +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupts. + * + * @note + * Depending on use case, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling + * if the pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupts. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * This function does not clear event bits. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IFS = flags; +} + +/***************************************************************************//** + * @brief + * Lock the CMU to protect some of its registers against unintended + * modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the CMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if !defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Convert prescaler divider to a logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] presc + * Prescaler value used to set the frequency divider. The divider is equal to + * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be + * equal to (divider - 1). + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) +{ + uint32_t log2; + + /* Integer prescalers take argument less than 32768. */ + EFM_ASSERT(presc < 32768U); + + /* Count leading zeroes and "reverse" result. Consider divider value to get + * exponent n from 2^n, so ('presc' +1). */ + log2 = 31UL - __CLZ(presc + (uint32_t) 1); + + /* Check that prescaler is a 2^n number. */ + EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); + + return log2; +} +#endif // !defined(_SILICON_LABS_32B_SERIES_0) + +/** @} (end addtogroup cmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CMU_PRESENT) */ +#endif /* EM_CMU_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h index 1585ec8..1c9c1ca 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h @@ -1,184 +1,184 @@ -/***************************************************************************//** - * @file - * @brief CMU Compatibility Header - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CMU_COMPAT_H -#define EM_CMU_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define CMU_IF_CALRDYIF CMU_IF_CALRDY -#define _CMU_IF_CALRDYIF_SHIFT _CMU_IF_CALRDY_SHIFT -#define _CMU_IF_CALRDYIF_MASK _CMU_IF_CALRDY_MASK -#define _CMU_IF_CALRDYIF_DEFAULT _CMU_IF_CALRDY_DEFAULT -#define CMU_IF_CALRDYIF_DEFAULT CMU_IF_CALRDY_DEFAULT - -#define CMU_IF_CALOFIF CMU_IF_CALOF -#define _CMU_IF_CALOFIF_SHIFT _CMU_IF_CALOF_SHIFT -#define _CMU_IF_CALOFIF_MASK _CMU_IF_CALOF_MASK -#define _CMU_IF_CALOFIF_DEFAULT _CMU_IF_CALOF_DEFAULT -#define CMU_IF_CALOFIF_DEFAULT CMU_IF_CALOF_DEFAULT - -#define CMU_IEN_CALRDYIEN CMU_IEN_CALRDY -#define _CMU_IEN_CALRDYIEN_SHIFT _CMU_IEN_CALRDY_SHIFT -#define _CMU_IEN_CALRDYIEN_MASK _CMU_IEN_CALRDY_MASK -#define _CMU_IEN_CALRDYIEN_DEFAULT _CMU_IEN_CALRDY_DEFAULT -#define CMU_IEN_CALRDYIEN_DEFAULT CMU_IEN_CALRDY_DEFAULT - -#define CMU_IEN_CALOFIEN CMU_IEN_CALOF -#define _CMU_IEN_CALOFIEN_SHIFT _CMU_IEN_CALOF_SHIFT -#define _CMU_IEN_CALOFIEN_MASK _CMU_IEN_CALOF_MASK -#define _CMU_IEN_CALOFIEN_DEFAULT _CMU_IEN_CALOF_DEFAULT -#define CMU_IEN_CALOFIEN_DEFAULT CMU_IEN_CALOF_DEFAULT - - -#define HFRCO_IF_RDYIF HFRCO_IF_RDY -#define _HFRCO_IF_RDYIF_SHIFT _HFRCO_IF_RDY_SHIFT -#define _HFRCO_IF_RDYIF_MASK _HFRCO_IF_RDY_MASK -#define _HFRCO_IF_RDYIF_DEFAULT _HFRCO_IF_RDY_DEFAULT -#define HFRCO_IF_RDYIF_DEFAULT HFRCO_IF_RDY_DEFAULT - -#define HFRCO_IEN_RDYIEN HFRCO_IEN_RDY -#define _HFRCO_IEN_RDYIEN_SHIFT _HFRCO_IEN_RDY_SHIFT -#define _HFRCO_IEN_RDYIEN_MASK _HFRCO_IEN_RDY_MASK -#define _HFRCO_IEN_RDYIEN_DEFAULT _HFRCO_IEN_RDY_DEFAULT -#define HFRCO_IEN_RDYIEN_DEFAULT HFRCO_IEN_RDY_DEFAULT - - -#define LFRCO_IF_RDYIF LFRCO_IF_RDY -#define _LFRCO_IF_RDYIF_SHIFT _LFRCO_IF_RDY_SHIFT -#define _LFRCO_IF_RDYIF_MASK _LFRCO_IF_RDY_MASK -#define _LFRCO_IF_RDYIF_DEFAULT _LFRCO_IF_RDY_DEFAULT -#define LFRCO_IF_RDYIF_DEFAULT LFRCO_IF_RDY_DEFAULT - -#define LFRCO_IF_POSEDGEIF LFRCO_IF_POSEDGE -#define _LFRCO_IF_POSEDGEIF_SHIFT _LFRCO_IF_POSEDGE_SHIFT -#define _LFRCO_IF_POSEDGEIF_MASK _LFRCO_IF_POSEDGE_MASK -#define _LFRCO_IF_POSEDGEIF_DEFAULT _LFRCO_IF_POSEDGE_DEFAULT -#define LFRCO_IF_POSEDGEIF_DEFAULT LFRCO_IF_POSEDGE_DEFAULT - -#define LFRCO_IF_NEGEDGEIF LFRCO_IF_NEGEDGE -#define _LFRCO_IF_NEGEDGEIF_SHIFT _LFRCO_IF_NEGEDGE_SHIFT -#define _LFRCO_IF_NEGEDGEIF_MASK _LFRCO_IF_NEGEDGE_MASK -#define _LFRCO_IF_NEGEDGEIF_DEFAULT _LFRCO_IF_NEGEDGE_DEFAULT -#define LFRCO_IF_NEGEDGEIF_DEFAULT LFRCO_IF_NEGEDGE_DEFAULT - -#define LFRCO_IF_TCDONEIF LFRCO_IF_TCDONE -#define _LFRCO_IF_TCDONEIF_SHIFT _LFRCO_IF_TCDONE_SHIFT -#define _LFRCO_IF_TCDONEIF_MASK _LFRCO_IF_TCDONE_MASK -#define _LFRCO_IF_TCDONEIF_DEFAULT _LFRCO_IF_TCDONE_DEFAULT -#define LFRCO_IF_TCDONEIF_DEFAULT LFRCO_IF_TCDONE_DEFAULT - -#define LFRCO_IF_CALDONEIF LFRCO_IF_CALDONE -#define _LFRCO_IF_CALDONEIF_SHIFT _LFRCO_IF_CALDONE_SHIFT -#define _LFRCO_IF_CALDONEIF_MASK _LFRCO_IF_CALDONE_MASK -#define _LFRCO_IF_CALDONEIF_DEFAULT _LFRCO_IF_CALDONE_DEFAULT -#define LFRCO_IF_CALDONEIF_DEFAULT LFRCO_IF_CALDONE_DEFAULT - -#define LFRCO_IF_TEMPCHANGEIF LFRCO_IF_TEMPCHANGE -#define _LFRCO_IF_TEMPCHANGEIF_SHIFT _LFRCO_IF_TEMPCHANGE_SHIFT -#define _LFRCO_IF_TEMPCHANGEIF_MASK _LFRCO_IF_TEMPCHANGE_MASK -#define _LFRCO_IF_TEMPCHANGEIF_DEFAULT _LFRCO_IF_TEMPCHANGE_DEFAULT -#define LFRCO_IF_TEMPCHANGEIF_DEFAULT LFRCO_IF_TEMPCHANGE_DEFAULT - -#define LFRCO_IF_SCHEDERRIF LFRCO_IF_SCHEDERR -#define _LFRCO_IF_SCHEDERRIF_SHIFT _LFRCO_IF_SCHEDERR_SHIFT -#define _LFRCO_IF_SCHEDERRIF_MASK _LFRCO_IF_SCHEDERR_MASK -#define _LFRCO_IF_SCHEDERRIF_DEFAULT _LFRCO_IF_SCHEDERR_DEFAULT -#define LFRCO_IF_SCHEDERRIF_DEFAULT LFRCO_IF_SCHEDERR_DEFAULT - -#define LFRCO_IF_TCOORIF LFRCO_IF_TCOOR -#define _LFRCO_IF_TCOORIF_SHIFT _LFRCO_IF_TCOOR_SHIFT -#define _LFRCO_IF_TCOORIF_MASK _LFRCO_IF_TCOOR_MASK -#define _LFRCO_IF_TCOORIF_DEFAULT _LFRCO_IF_TCOOR_DEFAULT -#define LFRCO_IF_TCOORIF_DEFAULT LFRCO_IF_TCOOR_DEFAULT - -#define LFRCO_IF_CALOORIF LFRCO_IF_CALOOR -#define _LFRCO_IF_CALOORIF_SHIFT _LFRCO_IF_CALOOR_SHIFT -#define _LFRCO_IF_CALOORIF_MASK _LFRCO_IF_CALOOR_MASK -#define _LFRCO_IF_CALOORIF_DEFAULT _LFRCO_IF_CALOOR_DEFAULT -#define LFRCO_IF_CALOORIF_DEFAULT LFRCO_IF_CALOOR_DEFAULT - -#define LFRCO_IEN_RDYIEN LFRCO_IEN_RDY -#define _LFRCO_IEN_RDYIEN_SHIFT _LFRCO_IEN_RDY_SHIFT -#define _LFRCO_IEN_RDYIEN_MASK _LFRCO_IEN_RDY_MASK -#define _LFRCO_IEN_RDYIEN_DEFAULT _LFRCO_IEN_RDY_DEFAULT -#define LFRCO_IEN_RDYIEN_DEFAULT LFRCO_IEN_RDY_DEFAULT - -#define LFRCO_IEN_POSEDGEIEN LFRCO_IEN_POSEDGE -#define _LFRCO_IEN_POSEDGEIEN_SHIFT _LFRCO_IEN_POSEDGE_SHIFT -#define _LFRCO_IEN_POSEDGEIEN_MASK _LFRCO_IEN_POSEDGE_MASK -#define _LFRCO_IEN_POSEDGEIEN_DEFAULT _LFRCO_IEN_POSEDGE_DEFAULT -#define LFRCO_IEN_POSEDGEIEN_DEFAULT LFRCO_IEN_POSEDGE_DEFAULT - -#define LFRCO_IEN_NEGEDGEIEN LFRCO_IEN_NEGEDGE -#define _LFRCO_IEN_NEGEDGEIEN_SHIFT _LFRCO_IEN_NEGEDGE_SHIFT -#define _LFRCO_IEN_NEGEDGEIEN_MASK _LFRCO_IEN_NEGEDGE_MASK -#define _LFRCO_IEN_NEGEDGEIEN_DEFAULT _LFRCO_IEN_NEGEDGE_DEFAULT -#define LFRCO_IEN_NEGEDGEIEN_DEFAULT LFRCO_IEN_NEGEDGE_DEFAULT - -#define LFRCO_IEN_TCDONEIEN LFRCO_IEN_TCDONE -#define _LFRCO_IEN_TCDONEIEN_SHIFT _LFRCO_IEN_TCDONE_SHIFT -#define _LFRCO_IEN_TCDONEIEN_MASK _LFRCO_IEN_TCDONE_MASK -#define _LFRCO_IEN_TCDONEIEN_DEFAULT _LFRCO_IEN_TCDONE_DEFAULT -#define LFRCO_IEN_TCDONEIEN_DEFAULT LFRCO_IEN_TCDONE_DEFAULT - -#define LFRCO_IEN_CALDONEIEN LFRCO_IEN_CALDONE -#define _LFRCO_IEN_CALDONEIEN_SHIFT _LFRCO_IEN_CALDONE_SHIFT -#define _LFRCO_IEN_CALDONEIEN_MASK _LFRCO_IEN_CALDONE_MASK -#define _LFRCO_IEN_CALDONEIEN_DEFAULT _LFRCO_IEN_CALDONE_DEFAULT -#define LFRCO_IEN_CALDONEIEN_DEFAULT LFRCO_IEN_CALDONE_DEFAULT - -#define LFRCO_IEN_TEMPCHANGEIEN LFRCO_IEN_TEMPCHANGE -#define _LFRCO_IEN_TEMPCHANGEIEN_SHIFT _LFRCO_IEN_TEMPCHANGE_SHIFT -#define _LFRCO_IEN_TEMPCHANGEIEN_MASK _LFRCO_IEN_TEMPCHANGE_MASK -#define _LFRCO_IEN_TEMPCHANGEIEN_DEFAULT _LFRCO_IEN_TEMPCHANGE_DEFAULT -#define LFRCO_IEN_TEMPCHANGEIEN_DEFAULT LFRCO_IEN_TEMPCHANGE_DEFAULT - -#define LFRCO_IEN_SCHEDERRIEN LFRCO_IEN_SCHEDERR -#define _LFRCO_IEN_SCHEDERRIEN_SHIFT _LFRCO_IEN_SCHEDERR_SHIFT -#define _LFRCO_IEN_SCHEDERRIEN_MASK _LFRCO_IEN_SCHEDERR_MASK -#define _LFRCO_IEN_SCHEDERRIEN_DEFAULT _LFRCO_IEN_SCHEDERR_DEFAULT -#define LFRCO_IEN_SCHEDERRIEN_DEFAULT LFRCO_IEN_SCHEDERR_DEFAULT - -#define LFRCO_IEN_TCOORIEN LFRCO_IEN_TCOOR -#define _LFRCO_IEN_TCOORIEN_SHIFT _LFRCO_IEN_TCOOR_SHIFT -#define _LFRCO_IEN_TCOORIEN_MASK _LFRCO_IEN_TCOOR_MASK -#define _LFRCO_IEN_TCOORIEN_DEFAULT _LFRCO_IEN_TCOOR_DEFAULT -#define LFRCO_IEN_TCOORIEN_DEFAULT LFRCO_IEN_TCOOR_DEFAULT - -#define LFRCO_IEN_CALOORIEN LFRCO_IEN_CALOOR -#define _LFRCO_IEN_CALOORIEN_SHIFT _LFRCO_IEN_CALOOR_SHIFT -#define _LFRCO_IEN_CALOORIEN_MASK _LFRCO_IEN_CALOOR_MASK -#define _LFRCO_IEN_CALOORIEN_DEFAULT _LFRCO_IEN_CALOOR_DEFAULT -#define LFRCO_IEN_CALOORIEN_DEFAULT LFRCO_IEN_CALOOR_DEFAULT - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ - -#endif +/***************************************************************************//** + * @file + * @brief CMU Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CMU_COMPAT_H +#define EM_CMU_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define CMU_IF_CALRDYIF CMU_IF_CALRDY +#define _CMU_IF_CALRDYIF_SHIFT _CMU_IF_CALRDY_SHIFT +#define _CMU_IF_CALRDYIF_MASK _CMU_IF_CALRDY_MASK +#define _CMU_IF_CALRDYIF_DEFAULT _CMU_IF_CALRDY_DEFAULT +#define CMU_IF_CALRDYIF_DEFAULT CMU_IF_CALRDY_DEFAULT + +#define CMU_IF_CALOFIF CMU_IF_CALOF +#define _CMU_IF_CALOFIF_SHIFT _CMU_IF_CALOF_SHIFT +#define _CMU_IF_CALOFIF_MASK _CMU_IF_CALOF_MASK +#define _CMU_IF_CALOFIF_DEFAULT _CMU_IF_CALOF_DEFAULT +#define CMU_IF_CALOFIF_DEFAULT CMU_IF_CALOF_DEFAULT + +#define CMU_IEN_CALRDYIEN CMU_IEN_CALRDY +#define _CMU_IEN_CALRDYIEN_SHIFT _CMU_IEN_CALRDY_SHIFT +#define _CMU_IEN_CALRDYIEN_MASK _CMU_IEN_CALRDY_MASK +#define _CMU_IEN_CALRDYIEN_DEFAULT _CMU_IEN_CALRDY_DEFAULT +#define CMU_IEN_CALRDYIEN_DEFAULT CMU_IEN_CALRDY_DEFAULT + +#define CMU_IEN_CALOFIEN CMU_IEN_CALOF +#define _CMU_IEN_CALOFIEN_SHIFT _CMU_IEN_CALOF_SHIFT +#define _CMU_IEN_CALOFIEN_MASK _CMU_IEN_CALOF_MASK +#define _CMU_IEN_CALOFIEN_DEFAULT _CMU_IEN_CALOF_DEFAULT +#define CMU_IEN_CALOFIEN_DEFAULT CMU_IEN_CALOF_DEFAULT + + +#define HFRCO_IF_RDYIF HFRCO_IF_RDY +#define _HFRCO_IF_RDYIF_SHIFT _HFRCO_IF_RDY_SHIFT +#define _HFRCO_IF_RDYIF_MASK _HFRCO_IF_RDY_MASK +#define _HFRCO_IF_RDYIF_DEFAULT _HFRCO_IF_RDY_DEFAULT +#define HFRCO_IF_RDYIF_DEFAULT HFRCO_IF_RDY_DEFAULT + +#define HFRCO_IEN_RDYIEN HFRCO_IEN_RDY +#define _HFRCO_IEN_RDYIEN_SHIFT _HFRCO_IEN_RDY_SHIFT +#define _HFRCO_IEN_RDYIEN_MASK _HFRCO_IEN_RDY_MASK +#define _HFRCO_IEN_RDYIEN_DEFAULT _HFRCO_IEN_RDY_DEFAULT +#define HFRCO_IEN_RDYIEN_DEFAULT HFRCO_IEN_RDY_DEFAULT + + +#define LFRCO_IF_RDYIF LFRCO_IF_RDY +#define _LFRCO_IF_RDYIF_SHIFT _LFRCO_IF_RDY_SHIFT +#define _LFRCO_IF_RDYIF_MASK _LFRCO_IF_RDY_MASK +#define _LFRCO_IF_RDYIF_DEFAULT _LFRCO_IF_RDY_DEFAULT +#define LFRCO_IF_RDYIF_DEFAULT LFRCO_IF_RDY_DEFAULT + +#define LFRCO_IF_POSEDGEIF LFRCO_IF_POSEDGE +#define _LFRCO_IF_POSEDGEIF_SHIFT _LFRCO_IF_POSEDGE_SHIFT +#define _LFRCO_IF_POSEDGEIF_MASK _LFRCO_IF_POSEDGE_MASK +#define _LFRCO_IF_POSEDGEIF_DEFAULT _LFRCO_IF_POSEDGE_DEFAULT +#define LFRCO_IF_POSEDGEIF_DEFAULT LFRCO_IF_POSEDGE_DEFAULT + +#define LFRCO_IF_NEGEDGEIF LFRCO_IF_NEGEDGE +#define _LFRCO_IF_NEGEDGEIF_SHIFT _LFRCO_IF_NEGEDGE_SHIFT +#define _LFRCO_IF_NEGEDGEIF_MASK _LFRCO_IF_NEGEDGE_MASK +#define _LFRCO_IF_NEGEDGEIF_DEFAULT _LFRCO_IF_NEGEDGE_DEFAULT +#define LFRCO_IF_NEGEDGEIF_DEFAULT LFRCO_IF_NEGEDGE_DEFAULT + +#define LFRCO_IF_TCDONEIF LFRCO_IF_TCDONE +#define _LFRCO_IF_TCDONEIF_SHIFT _LFRCO_IF_TCDONE_SHIFT +#define _LFRCO_IF_TCDONEIF_MASK _LFRCO_IF_TCDONE_MASK +#define _LFRCO_IF_TCDONEIF_DEFAULT _LFRCO_IF_TCDONE_DEFAULT +#define LFRCO_IF_TCDONEIF_DEFAULT LFRCO_IF_TCDONE_DEFAULT + +#define LFRCO_IF_CALDONEIF LFRCO_IF_CALDONE +#define _LFRCO_IF_CALDONEIF_SHIFT _LFRCO_IF_CALDONE_SHIFT +#define _LFRCO_IF_CALDONEIF_MASK _LFRCO_IF_CALDONE_MASK +#define _LFRCO_IF_CALDONEIF_DEFAULT _LFRCO_IF_CALDONE_DEFAULT +#define LFRCO_IF_CALDONEIF_DEFAULT LFRCO_IF_CALDONE_DEFAULT + +#define LFRCO_IF_TEMPCHANGEIF LFRCO_IF_TEMPCHANGE +#define _LFRCO_IF_TEMPCHANGEIF_SHIFT _LFRCO_IF_TEMPCHANGE_SHIFT +#define _LFRCO_IF_TEMPCHANGEIF_MASK _LFRCO_IF_TEMPCHANGE_MASK +#define _LFRCO_IF_TEMPCHANGEIF_DEFAULT _LFRCO_IF_TEMPCHANGE_DEFAULT +#define LFRCO_IF_TEMPCHANGEIF_DEFAULT LFRCO_IF_TEMPCHANGE_DEFAULT + +#define LFRCO_IF_SCHEDERRIF LFRCO_IF_SCHEDERR +#define _LFRCO_IF_SCHEDERRIF_SHIFT _LFRCO_IF_SCHEDERR_SHIFT +#define _LFRCO_IF_SCHEDERRIF_MASK _LFRCO_IF_SCHEDERR_MASK +#define _LFRCO_IF_SCHEDERRIF_DEFAULT _LFRCO_IF_SCHEDERR_DEFAULT +#define LFRCO_IF_SCHEDERRIF_DEFAULT LFRCO_IF_SCHEDERR_DEFAULT + +#define LFRCO_IF_TCOORIF LFRCO_IF_TCOOR +#define _LFRCO_IF_TCOORIF_SHIFT _LFRCO_IF_TCOOR_SHIFT +#define _LFRCO_IF_TCOORIF_MASK _LFRCO_IF_TCOOR_MASK +#define _LFRCO_IF_TCOORIF_DEFAULT _LFRCO_IF_TCOOR_DEFAULT +#define LFRCO_IF_TCOORIF_DEFAULT LFRCO_IF_TCOOR_DEFAULT + +#define LFRCO_IF_CALOORIF LFRCO_IF_CALOOR +#define _LFRCO_IF_CALOORIF_SHIFT _LFRCO_IF_CALOOR_SHIFT +#define _LFRCO_IF_CALOORIF_MASK _LFRCO_IF_CALOOR_MASK +#define _LFRCO_IF_CALOORIF_DEFAULT _LFRCO_IF_CALOOR_DEFAULT +#define LFRCO_IF_CALOORIF_DEFAULT LFRCO_IF_CALOOR_DEFAULT + +#define LFRCO_IEN_RDYIEN LFRCO_IEN_RDY +#define _LFRCO_IEN_RDYIEN_SHIFT _LFRCO_IEN_RDY_SHIFT +#define _LFRCO_IEN_RDYIEN_MASK _LFRCO_IEN_RDY_MASK +#define _LFRCO_IEN_RDYIEN_DEFAULT _LFRCO_IEN_RDY_DEFAULT +#define LFRCO_IEN_RDYIEN_DEFAULT LFRCO_IEN_RDY_DEFAULT + +#define LFRCO_IEN_POSEDGEIEN LFRCO_IEN_POSEDGE +#define _LFRCO_IEN_POSEDGEIEN_SHIFT _LFRCO_IEN_POSEDGE_SHIFT +#define _LFRCO_IEN_POSEDGEIEN_MASK _LFRCO_IEN_POSEDGE_MASK +#define _LFRCO_IEN_POSEDGEIEN_DEFAULT _LFRCO_IEN_POSEDGE_DEFAULT +#define LFRCO_IEN_POSEDGEIEN_DEFAULT LFRCO_IEN_POSEDGE_DEFAULT + +#define LFRCO_IEN_NEGEDGEIEN LFRCO_IEN_NEGEDGE +#define _LFRCO_IEN_NEGEDGEIEN_SHIFT _LFRCO_IEN_NEGEDGE_SHIFT +#define _LFRCO_IEN_NEGEDGEIEN_MASK _LFRCO_IEN_NEGEDGE_MASK +#define _LFRCO_IEN_NEGEDGEIEN_DEFAULT _LFRCO_IEN_NEGEDGE_DEFAULT +#define LFRCO_IEN_NEGEDGEIEN_DEFAULT LFRCO_IEN_NEGEDGE_DEFAULT + +#define LFRCO_IEN_TCDONEIEN LFRCO_IEN_TCDONE +#define _LFRCO_IEN_TCDONEIEN_SHIFT _LFRCO_IEN_TCDONE_SHIFT +#define _LFRCO_IEN_TCDONEIEN_MASK _LFRCO_IEN_TCDONE_MASK +#define _LFRCO_IEN_TCDONEIEN_DEFAULT _LFRCO_IEN_TCDONE_DEFAULT +#define LFRCO_IEN_TCDONEIEN_DEFAULT LFRCO_IEN_TCDONE_DEFAULT + +#define LFRCO_IEN_CALDONEIEN LFRCO_IEN_CALDONE +#define _LFRCO_IEN_CALDONEIEN_SHIFT _LFRCO_IEN_CALDONE_SHIFT +#define _LFRCO_IEN_CALDONEIEN_MASK _LFRCO_IEN_CALDONE_MASK +#define _LFRCO_IEN_CALDONEIEN_DEFAULT _LFRCO_IEN_CALDONE_DEFAULT +#define LFRCO_IEN_CALDONEIEN_DEFAULT LFRCO_IEN_CALDONE_DEFAULT + +#define LFRCO_IEN_TEMPCHANGEIEN LFRCO_IEN_TEMPCHANGE +#define _LFRCO_IEN_TEMPCHANGEIEN_SHIFT _LFRCO_IEN_TEMPCHANGE_SHIFT +#define _LFRCO_IEN_TEMPCHANGEIEN_MASK _LFRCO_IEN_TEMPCHANGE_MASK +#define _LFRCO_IEN_TEMPCHANGEIEN_DEFAULT _LFRCO_IEN_TEMPCHANGE_DEFAULT +#define LFRCO_IEN_TEMPCHANGEIEN_DEFAULT LFRCO_IEN_TEMPCHANGE_DEFAULT + +#define LFRCO_IEN_SCHEDERRIEN LFRCO_IEN_SCHEDERR +#define _LFRCO_IEN_SCHEDERRIEN_SHIFT _LFRCO_IEN_SCHEDERR_SHIFT +#define _LFRCO_IEN_SCHEDERRIEN_MASK _LFRCO_IEN_SCHEDERR_MASK +#define _LFRCO_IEN_SCHEDERRIEN_DEFAULT _LFRCO_IEN_SCHEDERR_DEFAULT +#define LFRCO_IEN_SCHEDERRIEN_DEFAULT LFRCO_IEN_SCHEDERR_DEFAULT + +#define LFRCO_IEN_TCOORIEN LFRCO_IEN_TCOOR +#define _LFRCO_IEN_TCOORIEN_SHIFT _LFRCO_IEN_TCOOR_SHIFT +#define _LFRCO_IEN_TCOORIEN_MASK _LFRCO_IEN_TCOOR_MASK +#define _LFRCO_IEN_TCOORIEN_DEFAULT _LFRCO_IEN_TCOOR_DEFAULT +#define LFRCO_IEN_TCOORIEN_DEFAULT LFRCO_IEN_TCOOR_DEFAULT + +#define LFRCO_IEN_CALOORIEN LFRCO_IEN_CALOOR +#define _LFRCO_IEN_CALOORIEN_SHIFT _LFRCO_IEN_CALOOR_SHIFT +#define _LFRCO_IEN_CALOORIEN_MASK _LFRCO_IEN_CALOOR_MASK +#define _LFRCO_IEN_CALOORIEN_DEFAULT _LFRCO_IEN_CALOOR_DEFAULT +#define LFRCO_IEN_CALOORIEN_DEFAULT LFRCO_IEN_CALOOR_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h index cf67370..69a5644 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief General purpose utilities. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_COMMON_H -#define EM_COMMON_H - -#include "em_device.h" -#include "sl_common.h" - -#endif /* EM_COMMON_H */ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_COMMON_H +#define EM_COMMON_H + +#include "em_device.h" +#include "sl_common.h" + +#endif /* EM_COMMON_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h index 3ad28f9..bd4b524 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h @@ -1,229 +1,229 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API (Device Specific) - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_CORE_H -#define EM_CORE_H - -#include "em_device.h" -#include "em_core_generic.h" -#include "sl_common.h" - -#if defined(EMLIB_USER_CONFIG) -#include "emlib_config.h" -#endif - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) -#include "emlib_core_debug_config.h" -#endif - -#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 -#endif - -/***************************************************************************//** - * @addtogroup core - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Number of words in a NVIC mask set. */ -#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) - -/** Number of entries in a default interrupt vector table. */ -#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) - -// Interrupt priorities based on processor architecture -#if defined(__CM3_REV) || defined(__CM4_REV) || defined(__CM7_REV) \ - || defined(__CM23_REV) || defined(__CM33_REV) - -/** Highest priority for core interrupt. */ -#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 - -/** Default priority for core interrupt. */ -#define CORE_INTERRUPT_DEFAULT_PRIORITY 5 - -/** Lowest priority for core interrupt. */ -#define CORE_INTERRUPT_LOWEST_PRIORITY 7 - -/** Default method to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_BASEPRI -#elif defined(__CM0_REV) || defined(__CM0PLUS_REV) - -/** Highest priority for core interrupt. */ -#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 - -/** Default priority for core interrupt. */ -#define CORE_INTERRUPT_DEFAULT_PRIORITY 1 - -/** Lowest priority for core interrupt. */ -#define CORE_INTERRUPT_LOWEST_PRIORITY 3 - -/** Default method to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_PRIMASK -#endif - -#if !defined(CORE_ATOMIC_METHOD) -/** Specify which method to use when implementing ATOMIC sections. You can - * select between BASEPRI or PRIMASK method. - * @note On Cortex-M0+ devices only PRIMASK can be used. */ -#if !defined(SL_CATALOG_DEVICE_INIT_NVIC_PRESENT) -#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK -#else -#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_DEFAULT -#endif -#endif - -// Compile time sanity check. -#if (CORE_NVIC_REG_WORDS > 3) -#error "em_core: Unexpected NVIC external interrupt count." -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ************************ MACRO API *************************************** - ******************************************************************************/ - -// -// NVIC mask section macro API. -// - -/** Allocate storage for NVIC interrupt masks for use by - * CORE_ENTER/EXIT_NVIC() macros. */ -#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState - -/** Allocate storage for NVIC interrupt masks. - * @param[in] x - * The storage variable name to use.*/ -#define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x - -/** Allocate storage for and zero initialize NVIC interrupt mask. - * @param[in] x - * The storage variable name to use.*/ -#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } - -/** NVIC mask style interrupt disable. - * @param[in] mask - * Mask specifying which NVIC interrupts to disable. */ -#define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) - -/** NVIC mask style interrupt enable. - * @param[in] mask - * Mask specifying which NVIC interrupts to enable. */ -#define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) - -/** Convenience macro for implementing a NVIC mask section. - * @param[in] mask - * Mask specifying which NVIC interrupts to disable within the section. - * @param[in] yourcode - * The code for the section. */ -#define CORE_NVIC_SECTION(mask, yourcode) \ - { \ - CORE_DECLARE_NVIC_STATE; \ - CORE_ENTER_NVIC(mask); \ - { \ - yourcode \ - } \ - CORE_EXIT_NVIC(); \ - } - -/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist - * in scope. - * @param[in] disable - * Mask specifying which NVIC interrupts to disable within the section. */ -#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) - -/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist - * in scope. */ -#define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) - -/** NVIC maks style yield. - * @param[in] enable - * Mask specifying which NVIC interrupts to briefly enable. */ -#define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Storage for NVIC interrupt masks. */ -typedef struct { - uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ -} CORE_nvicMask_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -bool CORE_IrqIsBlocked(IRQn_Type irqN); - -void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask); -bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask); - -void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, - const CORE_nvicMask_t *disable); -void CORE_NvicDisableMask(const CORE_nvicMask_t *disable); -void CORE_NvicEnableMask(const CORE_nvicMask_t *enable); -void CORE_YieldNvicMask(const CORE_nvicMask_t *enable); -void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); -void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); -bool CORE_NvicIRQDisabled(IRQn_Type irqN); - -void *CORE_GetNvicRamTableHandler(IRQn_Type irqN); -void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler); -void CORE_InitNvicVectorTable(uint32_t *sourceTable, - uint32_t sourceSize, - uint32_t *targetTable, - uint32_t targetSize, - void *defaultHandler, - bool overwriteActive); - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -uint32_t CORE_get_max_time_critical_section(void); -uint32_t CORE_get_max_time_atomic_section(void); -void CORE_clear_max_time_critical_section(void); -void CORE_clear_max_time_atomic_section(void); -#endif - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup core) */ - -#endif /* EM_CORE_H */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Device Specific) + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CORE_H +#define EM_CORE_H + +#include "em_device.h" +#include "em_core_generic.h" +#include "sl_common.h" + +#if defined(EMLIB_USER_CONFIG) +#include "emlib_config.h" +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) +#include "emlib_core_debug_config.h" +#endif + +#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +#endif + +/***************************************************************************//** + * @addtogroup core + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Number of words in a NVIC mask set. */ +#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) + +/** Number of entries in a default interrupt vector table. */ +#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) + +// Interrupt priorities based on processor architecture +#if defined(__CM3_REV) || defined(__CM4_REV) || defined(__CM7_REV) \ + || defined(__CM23_REV) || defined(__CM33_REV) + +/** Highest priority for core interrupt. */ +#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 + +/** Default priority for core interrupt. */ +#define CORE_INTERRUPT_DEFAULT_PRIORITY 5 + +/** Lowest priority for core interrupt. */ +#define CORE_INTERRUPT_LOWEST_PRIORITY 7 + +/** Default method to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_BASEPRI +#elif defined(__CM0_REV) || defined(__CM0PLUS_REV) + +/** Highest priority for core interrupt. */ +#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 + +/** Default priority for core interrupt. */ +#define CORE_INTERRUPT_DEFAULT_PRIORITY 1 + +/** Lowest priority for core interrupt. */ +#define CORE_INTERRUPT_LOWEST_PRIORITY 3 + +/** Default method to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_PRIMASK +#endif + +#if !defined(CORE_ATOMIC_METHOD) +/** Specify which method to use when implementing ATOMIC sections. You can + * select between BASEPRI or PRIMASK method. + * @note On Cortex-M0+ devices only PRIMASK can be used. */ +#if !defined(SL_CATALOG_DEVICE_INIT_NVIC_PRESENT) +#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK +#else +#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_DEFAULT +#endif +#endif + +// Compile time sanity check. +#if (CORE_NVIC_REG_WORDS > 3) +#error "em_core: Unexpected NVIC external interrupt count." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +// +// NVIC mask section macro API. +// + +/** Allocate storage for NVIC interrupt masks for use by + * CORE_ENTER/EXIT_NVIC() macros. */ +#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState + +/** Allocate storage for NVIC interrupt masks. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x + +/** Allocate storage for and zero initialize NVIC interrupt mask. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } + +/** NVIC mask style interrupt disable. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable. */ +#define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) + +/** NVIC mask style interrupt enable. + * @param[in] mask + * Mask specifying which NVIC interrupts to enable. */ +#define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) + +/** Convenience macro for implementing a NVIC mask section. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable within the section. + * @param[in] yourcode + * The code for the section. */ +#define CORE_NVIC_SECTION(mask, yourcode) \ + { \ + CORE_DECLARE_NVIC_STATE; \ + CORE_ENTER_NVIC(mask); \ + { \ + yourcode \ + } \ + CORE_EXIT_NVIC(); \ + } + +/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. + * @param[in] disable + * Mask specifying which NVIC interrupts to disable within the section. */ +#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) + +/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. */ +#define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) + +/** NVIC maks style yield. + * @param[in] enable + * Mask specifying which NVIC interrupts to briefly enable. */ +#define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Storage for NVIC interrupt masks. */ +typedef struct { + uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ +} CORE_nvicMask_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool CORE_IrqIsBlocked(IRQn_Type irqN); + +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask); +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask); + +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable); +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable); +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable); +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable); +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); +bool CORE_NvicIRQDisabled(IRQn_Type irqN); + +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN); +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler); +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive); + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +uint32_t CORE_get_max_time_critical_section(void); +uint32_t CORE_get_max_time_atomic_section(void); +void CORE_clear_max_time_critical_section(void); +void CORE_clear_max_time_atomic_section(void); +#endif + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup core) */ + +#endif /* EM_CORE_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h index 28b996d..0569570 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h @@ -1,173 +1,173 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API (Generic) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CORE_GENERIC_H -#define EM_CORE_GENERIC_H - -#include -#include - -/***************************************************************************//** - * @addtogroup core - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Use PRIMASK register to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_PRIMASK 0 - -/** Use BASEPRI register to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_BASEPRI 1 - -#if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) -/** The interrupt priority level disabled within ATOMIC regions. Interrupts - * with priority level equal to or lower than this definition will be disabled - * within ATOMIC regions. */ -#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ************************ MACRO API *************************************** - ******************************************************************************/ - -// -// CRITICAL section macro API. -// - -/** Allocate storage for PRIMASK or BASEPRI value for use by - * CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. */ -#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState - -/** CRITICAL style interrupt disable. */ -#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() - -/** CRITICAL style interrupt enable. */ -#define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() - -/** Convenience macro for implementing a CRITICAL section. */ -#define CORE_CRITICAL_SECTION(yourcode) \ - { \ - CORE_DECLARE_IRQ_STATE; \ - CORE_ENTER_CRITICAL(); \ - { \ - yourcode \ - } \ - CORE_EXIT_CRITICAL(); \ - } - -/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() - -/** Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) - -/** CRITICAL style yield. */ -#define CORE_YIELD_CRITICAL() CORE_YieldCritical() - -// -// ATOMIC section macro API. -// - -/** ATOMIC style interrupt disable. */ -#define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() - -/** ATOMIC style interrupt enable. */ -#define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() - -/** Convenience macro for implementing an ATOMIC section. */ -#define CORE_ATOMIC_SECTION(yourcode) \ - { \ - CORE_DECLARE_IRQ_STATE; \ - CORE_ENTER_ATOMIC(); \ - { \ - yourcode \ - } \ - CORE_EXIT_ATOMIC(); \ - } - -/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() - -/** Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) - -/** ATOMIC style yield. */ -#define CORE_YIELD_ATOMIC() CORE_YieldAtomic() - -/** Check if IRQ is disabled. */ -#define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() - -/** Check if inside an IRQ handler. */ -#define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Storage for PRIMASK or BASEPRI value. */ -typedef uint32_t CORE_irqState_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void CORE_CriticalDisableIrq(void); -void CORE_CriticalEnableIrq(void); -void CORE_ExitCritical(CORE_irqState_t irqState); -void CORE_YieldCritical(void); -CORE_irqState_t CORE_EnterCritical(void); - -void CORE_AtomicDisableIrq(void); -void CORE_AtomicEnableIrq(void); -void CORE_ExitAtomic(CORE_irqState_t irqState); -void CORE_YieldAtomic(void); -CORE_irqState_t CORE_EnterAtomic(void); - -bool CORE_InIrqContext(void); -bool CORE_IrqIsDisabled(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup core) */ - -#endif /* EM_CORE_GENERIC_H */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_GENERIC_H +#define EM_CORE_GENERIC_H + +#include +#include + +/***************************************************************************//** + * @addtogroup core + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Use PRIMASK register to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_PRIMASK 0 + +/** Use BASEPRI register to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_BASEPRI 1 + +#if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) +/** The interrupt priority level disabled within ATOMIC regions. Interrupts + * with priority level equal to or lower than this definition will be disabled + * within ATOMIC regions. */ +#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +// +// CRITICAL section macro API. +// + +/** Allocate storage for PRIMASK or BASEPRI value for use by + * CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. */ +#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState + +/** CRITICAL style interrupt disable. */ +#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() + +/** CRITICAL style interrupt enable. */ +#define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() + +/** Convenience macro for implementing a CRITICAL section. */ +#define CORE_CRITICAL_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_CRITICAL(); \ + { \ + yourcode \ + } \ + CORE_EXIT_CRITICAL(); \ + } + +/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() + +/** Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) + +/** CRITICAL style yield. */ +#define CORE_YIELD_CRITICAL() CORE_YieldCritical() + +// +// ATOMIC section macro API. +// + +/** ATOMIC style interrupt disable. */ +#define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() + +/** ATOMIC style interrupt enable. */ +#define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() + +/** Convenience macro for implementing an ATOMIC section. */ +#define CORE_ATOMIC_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_ATOMIC(); \ + { \ + yourcode \ + } \ + CORE_EXIT_ATOMIC(); \ + } + +/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() + +/** Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) + +/** ATOMIC style yield. */ +#define CORE_YIELD_ATOMIC() CORE_YieldAtomic() + +/** Check if IRQ is disabled. */ +#define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() + +/** Check if inside an IRQ handler. */ +#define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Storage for PRIMASK or BASEPRI value. */ +typedef uint32_t CORE_irqState_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void CORE_CriticalDisableIrq(void); +void CORE_CriticalEnableIrq(void); +void CORE_ExitCritical(CORE_irqState_t irqState); +void CORE_YieldCritical(void); +CORE_irqState_t CORE_EnterCritical(void); + +void CORE_AtomicDisableIrq(void); +void CORE_AtomicEnableIrq(void); +void CORE_ExitAtomic(CORE_irqState_t irqState); +void CORE_YieldAtomic(void); +CORE_irqState_t CORE_EnterAtomic(void); + +bool CORE_InIrqContext(void); +bool CORE_IrqIsDisabled(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup core) */ + +#endif /* EM_CORE_GENERIC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h index f69acef..51061fe 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h @@ -1,134 +1,134 @@ -/***************************************************************************//** - * @file - * @brief Debug (DBG) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_DBG_H -#define EM_DBG_H - -#include -#include "em_device.h" - -#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup dbg - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Lock modes */ -typedef enum { - dbgLockModeAllowErase = 1UL, /**< Lock debug access. */ -#if !defined(_SILICON_LABS_32B_SERIES_0) - dbgLockModePermanent = 2UL /**< Lock debug access permanently. */ -#endif -} DBG_LockMode_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(GPIO_ROUTE_SWCLKPEN) \ - || defined(GPIO_ROUTEPEN_SWCLKTCKPEN) \ - || defined(GPIO_DBGROUTEPEN_SWCLKTCKPEN) -/***************************************************************************//** - * @brief - * Check if a debugger is connected (and debug session activated). - * - * @details - * Used to make run-time decisions depending on whether or not a debug session - * has been active since last reset, i.e., using a debug probe or similar. In - * some cases, special handling is required in that scenario. - * - * @return - * True if a debug session is active since last reset, otherwise false. - ******************************************************************************/ -__STATIC_INLINE bool DBG_Connected(void) -{ - return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false; -} -#endif - -#if defined(GPIO_ROUTE_SWOPEN) \ - || defined(GPIO_ROUTEPEN_SWVPEN) \ - || defined(GPIO_TRACEROUTEPEN_SWVPEN) -void DBG_SWOEnable(unsigned int location); -#endif - -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode); -#endif - -#if defined (EMU_CTRL_EM2DBGEN) -/***************************************************************************//** - * @brief - * Enable or disable debug support while in EM2 mode. - * - * @warning - * Disabling debug support in EM2 will reduce current consumption with 1-2 uA, - * but some debuggers will have problems regaining control over a device which - * is in EM2 and has debug support disabled. - * - * To remedy this, set the WSTK switch next to the battery holder to USB - * (powers down the EFR). Execute Simplicity Commander with command line - * parameters: - * "./commander.exe device recover" - * and then immediately move the switch to the AEM position. An additional - * "./commander.exe device masserase" - * command completes the recovery procedure. - * - * @param[in] enable - * Boolean true enables EM2 debug support, false disables. - ******************************************************************************/ -__STATIC_INLINE void DBG_EM2DebugEnable(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; - } else { - EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; - } -} -#endif - -/** @} (end addtogroup dbg) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ - -#endif /* EM_DBG_H */ +/***************************************************************************//** + * @file + * @brief Debug (DBG) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_DBG_H +#define EM_DBG_H + +#include +#include "em_device.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dbg + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Lock modes */ +typedef enum { + dbgLockModeAllowErase = 1UL, /**< Lock debug access. */ +#if !defined(_SILICON_LABS_32B_SERIES_0) + dbgLockModePermanent = 2UL /**< Lock debug access permanently. */ +#endif +} DBG_LockMode_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWCLKPEN) \ + || defined(GPIO_ROUTEPEN_SWCLKTCKPEN) \ + || defined(GPIO_DBGROUTEPEN_SWCLKTCKPEN) +/***************************************************************************//** + * @brief + * Check if a debugger is connected (and debug session activated). + * + * @details + * Used to make run-time decisions depending on whether or not a debug session + * has been active since last reset, i.e., using a debug probe or similar. In + * some cases, special handling is required in that scenario. + * + * @return + * True if a debug session is active since last reset, otherwise false. + ******************************************************************************/ +__STATIC_INLINE bool DBG_Connected(void) +{ + return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false; +} +#endif + +#if defined(GPIO_ROUTE_SWOPEN) \ + || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +void DBG_SWOEnable(unsigned int location); +#endif + +#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) +void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode); +#endif + +#if defined (EMU_CTRL_EM2DBGEN) +/***************************************************************************//** + * @brief + * Enable or disable debug support while in EM2 mode. + * + * @warning + * Disabling debug support in EM2 will reduce current consumption with 1-2 uA, + * but some debuggers will have problems regaining control over a device which + * is in EM2 and has debug support disabled. + * + * To remedy this, set the WSTK switch next to the battery holder to USB + * (powers down the EFR). Execute Simplicity Commander with command line + * parameters: + * "./commander.exe device recover" + * and then immediately move the switch to the AEM position. An additional + * "./commander.exe device masserase" + * command completes the recovery procedure. + * + * @param[in] enable + * Boolean true enables EM2 debug support, false disables. + ******************************************************************************/ +__STATIC_INLINE void DBG_EM2DebugEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; + } +} +#endif + +/** @} (end addtogroup dbg) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ + +#endif /* EM_DBG_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h index 1f1a857..d9b65d0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h @@ -1,1760 +1,1760 @@ -/***************************************************************************//** - * @file - * @brief Energy Management Unit (EMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EMU_H -#define EM_EMU_H - -#include "em_device.h" -#include "sl_status.h" -#if defined(EMU_PRESENT) - -#include -#include "em_bus.h" -#include "sl_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup emu - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) -/** Voltage scaling present */ -#define EMU_VSCALE_PRESENT -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -/** Voltage scaling for EM01 present */ -#define EMU_VSCALE_EM01_PRESENT -#endif -#endif - -#if defined(_EMU_DCDCCTRL_MASK) -/** DC-DC buck converter present */ -#define EMU_SERIES1_DCDC_BUCK_PRESENT -#endif - -#if defined(_SILICON_LABS_DCDC_FEATURE) \ - && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \ - || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) -/** DC-DC buck converter present */ -#define EMU_SERIES2_DCDC_BUCK_PRESENT -#endif - -#if defined(_SILICON_LABS_DCDC_FEATURE) \ - && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \ - || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) -/** DC-DC boost converter present */ -#define EMU_SERIES2_DCDC_BOOST_PRESENT -#endif - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -#if defined(_EMU_EM4CONF_OSC_MASK) -/** EM4 duty oscillator. */ -typedef enum { - /** Select ULFRCO as duty oscillator in EM4. */ - emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, - /** Select LFXO as duty oscillator in EM4. */ - emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, - /** Select LFRCO as duty oscillator in EM4. */ - emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO -} EMU_EM4Osc_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_PROBE_MASK) -/** Backup Power Voltage Probe types. */ -typedef enum { - /** Disable voltage probe. */ - emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, - /** Connect probe to VDD_DREG. */ - emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, - /** Connect probe to BU_IN. */ - emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, - /** Connect probe to BU_OUT. */ - emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT -} EMU_Probe_TypeDef; -#endif - -#if defined(_EMU_PWRCONF_PWRRES_MASK) -/** Backup Power Domain resistor selection. */ -typedef enum { - /** Main power and backup power connected with RES0 series resistance. */ - emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, - /** Main power and backup power connected with RES1 series resistance. */ - emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, - /** Main power and backup power connected with RES2 series resistance. */ - emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, - /** Main power and backup power connected with RES3 series resistance. */ - emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, -} EMU_Resistor_TypeDef; -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/** Backup Power Domain power connection. */ -typedef enum { - /** No connection between main and backup power. */ - emuPower_None = EMU_BUINACT_PWRCON_NONE, - /** Main power and backup power connected through diode, - allowing current from backup to main only. */ - emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, - /** Main power and backup power connected through diode, - allowing current from main to backup only. */ - emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, - /** Main power and backup power connected without diode. */ - emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, -} EMU_Power_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -/** Backup Power Domain power connection configuration when not in backup mode selection. */ -typedef enum { - /** No connection. */ - emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, - /** Allow power from main to backup. */ - emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, - /** Allow power from backup to main. */ - emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, - /** Backup and main power are connected. */ - emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, -} EMU_BUBuInactPwrCon_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -/** Backup Power Domain power connection configuration in backup mode selection. */ -typedef enum { - /** No connection. */ - emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, - /** Allow power from main to backup. */ - emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, - /** Allow power from backup to main. */ - emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, - /** Backup and main power are connected. */ - emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, -} EMU_BUBuActPwrCon_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_PWRRES_MASK) -/** Backup Power Domain resistor selection. */ -typedef enum { - /** Main power and backup power connected with RES0 series resistance. */ - emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, - /** Main power and backup power connected with RES1 series resistance. */ - emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, - /** Main power and backup power connected with RES2 series resistance. */ - emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, - /** Main power and backup power connected with RES3 series resistance. */ - emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, -} EMU_BUPwrRes_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -/** Resistance between backup domain power supply and BU_VOUT. */ -typedef enum { - /** BU_VOUT is not connected. */ - emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, - /** Enable weak switch. */ - emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, - /** Enable medium switch. */ - emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, - /** Enable strong switch. */ - emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, -} EMU_BUVoutRes_TypeDef; -#endif - -/** BOD threshold setting selector, active or inactive mode. */ -typedef enum { - /** Configure BOD threshold for active mode. */ - emuBODMode_Active, - /** Configure BOD threshold for inactive mode. */ - emuBODMode_Inactive, -} EMU_BODMode_TypeDef; - -/** EM4 modes. */ -typedef enum { - /** EM4 Shutoff. */ - emuEM4Shutoff = 0, - /** EM4 Hibernate. */ - emuEM4Hibernate = 1, -} EMU_EM4State_TypeDef; - -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/** EM4 Pin Retention Type. */ -typedef enum { - /** No Retention: Pads enter reset state when entering EM4. */ - emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, - /** Retention through EM4: Pads enter reset state when exiting EM4. */ - emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, - /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to - release pins from retention after EM4 wakeup. */ - emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, -} EMU_EM4PinRetention_TypeDef; -#endif - -/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ -typedef enum { - /** DCDC is connected to DVDD. */ - emuPowerConfig_DcdcToDvdd, -} EMU_PowerConfig_TypeDef; - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC operating modes. */ -typedef enum { - /** DCDC regulator bypass. */ - emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, - /** DCDC low-noise mode. */ - emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, -#if defined(_EMU_DCDCLPEM01CFG_MASK) - /** DCDC low-power mode. */ - emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, -#endif -} EMU_DcdcMode_TypeDef; - -/** DCDC operating modes in EM2 or EM3. */ -typedef enum { - /** DCDC mode is low power. */ - emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER, - /** DCDC mode is according to DCDCMODE field. */ - emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW, -} EMU_DcdcModeEM23_TypeDef; - -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC conduction modes. */ -typedef enum { - /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization - features are available in this mode. */ - emuDcdcConductionMode_ContinuousLN, - /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or - for EFR32 when its radio is not enabled. */ - emuDcdcConductionMode_DiscontinuousLN, -} EMU_DcdcConductionMode_TypeDef; -#endif - -#if defined(_EMU_PWRCTRL_MASK) -/** DCDC to DVDD mode analog peripheral power supply select. */ -typedef enum { - /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ - emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, - /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ - emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD -} EMU_DcdcAnaPeripheralPower_TypeDef; -#endif - -#if defined(_EMU_DCDCMISCCTRL_MASK) -/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ -typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; - -/** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ -#define emuDcdcLnHighEfficiency -1 - -/** Default reverse current for fast transient response mode (low noise). */ -#define emuDcdcLnFastTransient 160 -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC Low-noise RCO band select. */ -typedef enum { - /** Set RCO to 3MHz. */ - emuDcdcLnRcoBand_3MHz = 0, - /** Set RCO to 4MHz. */ - emuDcdcLnRcoBand_4MHz = 1, - /** Set RCO to 5MHz. */ - emuDcdcLnRcoBand_5MHz = 2, - /** Set RCO to 6MHz. */ - emuDcdcLnRcoBand_6MHz = 3, - /** Set RCO to 7MHz. */ - emuDcdcLnRcoBand_7MHz = 4, - /** Set RCO to 8MHz. */ - emuDcdcLnRcoBand_8MHz = 5, - /** Set RCO to 9MHz. */ - emuDcdcLnRcoBand_9MHz = 6, - /** Set RCO to 10MHz. */ - emuDcdcLnRcoBand_10MHz = 7, -} EMU_DcdcLnRcoBand_TypeDef; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated. */ -#define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz -#define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz -#define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz -#define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz -#define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz -#define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz -#define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz -#define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz -/** @endcond */ - -/** DCDC Low Noise Compensator Control register. */ -typedef enum { - /** DCDC capacitor is 1uF. */ - emuDcdcLnCompCtrl_1u0F, - /** DCDC capacitor is 4.7uF. */ - emuDcdcLnCompCtrl_4u7F, -} EMU_DcdcLnCompCtrl_TypeDef; -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) - -/** DCDC mode. */ -typedef enum { - emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */ - emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */ -} EMU_DcdcMode_TypeDef; -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/** VREGIN comparator threshold. */ -typedef enum { - emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */ - emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */ - emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */ - emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */ -} EMU_VreginCmpThreshold_TypeDef; - -/** DCDC Buck Ton max timeout. */ -typedef enum { -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) - emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ - emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ - emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ - emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ - emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ - emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ - emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ - emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */ -#else - emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */ - emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */ - emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */ - emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */ - emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */ - emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */ - emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */ - emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */ - emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */ - emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */ - emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */ - emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */ - emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */ - emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */ - emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */ - emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */ - emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */ - emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */ - emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */ - emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */ - emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */ - emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */ - emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */ - emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */ - emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */ - emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */ - emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */ - emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */ - emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */ - emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */ - emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */ - emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */ -#endif -} EMU_DcdcTonMaxTimeout_TypeDef; - -/** DCDC Buck drive speed. */ -typedef enum { - emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ -} EMU_DcdcDriveSpeed_TypeDef; - -/** DCDC Buck peak current setting. */ -typedef enum { -#if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA) - emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA) - emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA) - emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA) - emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA) - emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA) - emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA) - emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ -#endif - emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ - emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ - emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ - emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ - emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ - emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA) - emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA) - emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA) - emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA) - emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA) - emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ -#endif -} EMU_DcdcPeakCurrent_TypeDef; -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/** DCDC Boost drive speed. */ -typedef enum { - emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ -} EMU_DcdcBoostDriveSpeed_TypeDef; - -/** DCDC Boost EM01 peak current setting. */ -typedef enum { - emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ - emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ - emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ - emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ - emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ - emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ - emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ - emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ - emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ - emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ -} EMU_DcdcBoostEM01PeakCurrent_TypeDef; - -/** DCDC Boost Toff max timeout */ -typedef enum { - emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */ - emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */ - emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */ - emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */ - emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */ - emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */ - emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */ - emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */ -} EMU_DcdcBoostToffMaxTimeout_TypeDef; - -/** DCDC Boost peak current detection maximum timeout */ -typedef enum { - emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ - emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ - emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ - emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ - emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ - emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ - emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ - emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */ -} EMU_DcdcBoostTonMaxTimeout_TypeDef; - -/** DCDC Boost EM23 peak current setting. */ -typedef enum { - emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ -} EMU_DcdcBoostEM23PeakCurrent_TypeDef; -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ - -#if defined(EMU_STATUS_VMONRDY) -/** VMON channels. */ -typedef enum { - emuVmonChannel_AVDD, - emuVmonChannel_ALTAVDD, - emuVmonChannel_DVDD, - emuVmonChannel_IOVDD0, -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - emuVmonChannel_IOVDD1, -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - emuVmonChannel_BUVDD, -#endif -} EMU_VmonChannel_TypeDef; -#endif /* EMU_STATUS_VMONRDY */ - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/** Bias mode configurations. */ -typedef enum { - emuBiasMode_1KHz, - emuBiasMode_4KHz, - emuBiasMode_Continuous -} EMU_BiasMode_TypeDef; -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/** Supported EM0/1 Voltage Scaling Levels. */ -typedef enum { - /** High-performance voltage level. HF clock can be set to any frequency. */ - emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, - /** Low-power optimized voltage level. HF clock must be limited - to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. - EM0/1 voltage scaling is applied when core clock frequency is - changed from @ref cmu or when calling @ref EMU_EM01Init() when HF - clock is already below the limit. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - /** Minimum VSCALE level in EM0/1 is VSCALE1. */ - emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1, -#else - emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, -#endif -} EMU_VScaleEM01_TypeDef; -#endif - -#if defined(EMU_VSCALE_PRESENT) -/** Supported EM2/3 Voltage Scaling Levels. */ -typedef enum { - /** Fast-wakeup voltage level. */ - emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, - /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 - adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled - up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ - emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, -} EMU_VScaleEM23_TypeDef; -#endif - -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) -/** Supported EM4H Voltage Scaling Levels */ -typedef enum { - /** Fast-wakeup voltage level. */ - emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, - /** Low-power optimized voltage level. Using this voltage level in EM4H - adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled - up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ - emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, -} EMU_VScaleEM4H_TypeDef; -#endif - -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -/** Peripheral EM2 and 3 retention control. */ -typedef enum { -#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) - emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) - emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) - emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) - emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) - emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) - emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) - emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) - emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) - emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */ -#endif - emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) - emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */ -#endif - emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) - emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */ -#endif - emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */ - emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */ - emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) - emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) - emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) - emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */ -#endif - emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */ - emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */ - emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) - emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */ - emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */ -#endif - emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */ - - emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */ - emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK -#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK -#endif - | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK -#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK - | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */ -#endif - | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, - emuPeripheralRetention_ALL = emuPeripheralRetention_D1 - | emuPeripheralRetention_D2 -#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) - | emuPeripheralRetention_WDOG1 -#endif - | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */ -} EMU_PeripheralRetention_TypeDef; -#endif - -#if defined(_EMU_TEMP_TEMPAVG_MASK) -/** Number of samples to use for temperature averaging. */ -typedef enum { - /** 16 samples used for temperature averaging. */ - emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16, - /** 64 samples used for temperature averaging. */ - emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64, -} EMU_TempAvgNum_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/** EM0 and 1 initialization structure. Voltage scaling is applied when - the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance - is always enabled. */ -typedef struct { - bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ -} EMU_EM01Init_TypeDef; - -/** Default initialization of EM0 and 1 configuration. */ -#define EMU_EM01INIT_DEFAULT \ - { \ - false /* Do not scale down in EM0/1.*/ \ - } -#endif - -/** EM2 and 3 initialization structure. */ -typedef struct { - bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ -#if defined(EMU_VSCALE_PRESENT) - EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ -#endif -} EMU_EM23Init_TypeDef; - -/** Default initialization of EM2 and 3 configuration. */ -#if defined(EMU_VSCALE_PRESENT) -#define EMU_EM23INIT_DEFAULT \ - { \ - false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ - emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ - } -#else -#define EMU_EM23INIT_DEFAULT \ - { \ - false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ - } -#endif - -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -/** EM4 initialization structure. */ -typedef struct { -#if defined(_EMU_EM4CONF_MASK) - /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ - bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ - bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ - EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ - bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ - bool vreg; /**< Enable EM4 voltage regulator. */ -#elif defined(_EMU_EM4CTRL_MASK) - /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ - bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ - bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ - bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ - EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ - EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ -#endif -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) - EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ -#endif -} EMU_EM4Init_TypeDef; -#endif - -#if defined(_EMU_EM4CONF_MASK) -/** Default initialization of EM4 configuration (Series 0). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Do not lock configuration after it's been set. */ \ - false, /* No reset will be asserted due to BOD in EM4. */ \ - emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ - true, /* Wake up on EM4 BURTC interrupt. */ \ - true, /* Enable VREG. */ \ - } - -#elif defined(_EMU_CTRL_EM4HVSCALE_MASK) -/** Default initialization of EM4 configuration (Series 1 with VSCALE). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Retain LFXO configuration upon EM4 entry. */ \ - false, /* Retain LFRCO configuration upon EM4 entry. */ \ - false, /* Retain ULFRCO configuration upon EM4 entry. */ \ - emuEM4Shutoff, /* Use EM4 shutoff state. */ \ - emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ - emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ - } - -#elif defined(_EMU_EM4CTRL_MASK) -/** Default initialization of EM4 configuration (Series 1 without VSCALE). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Retain LFXO configuration upon EM4 entry. */ \ - false, /* Retain LFRCO configuration upon EM4 entry. */ \ - false, /* Retain ULFRCO configuration upon EM4 entry. */ \ - emuEM4Shutoff, /* Use EM4 shutoff state. */ \ - emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ - } -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/** Backup Power Domain Initialization structure. */ -typedef struct { - /* Backup Power Domain power configuration. */ - - /** Voltage probe select, selects ADC voltage. */ - EMU_Probe_TypeDef probe; - /** Enable BOD calibration mode. */ - bool bodCal; - /** Enable BU_STAT status pin for active BU mode. */ - bool statusPinEnable; - - /* Backup Power Domain connection configuration. */ - /** Power domain resistor. */ - EMU_Resistor_TypeDef resistor; - /** BU_VOUT strong enable. */ - bool voutStrong; - /** BU_VOUT medium enable. */ - bool voutMed; - /** BU_VOUT weak enable. */ - bool voutWeak; - /** Power connection, when not in Backup Mode. */ - EMU_Power_TypeDef inactivePower; - /** Power connection, when in Backup Mode. */ - EMU_Power_TypeDef activePower; - /** Enable backup power domain, and release reset, enable BU_VIN pin. */ - bool enable; -} EMU_BUPDInit_TypeDef; - -/** Default Backup Power Domain configuration. */ -#define EMU_BUPDINIT_DEFAULT \ - { \ - emuProbe_Disable, /* Do not enable voltage probe. */ \ - false, /* Disable BOD calibration mode. */ \ - false, /* Disable BU_STAT pin for backup mode indication. */ \ - \ - emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ - false, /* Do not enable strong switch. */ \ - false, /* Do not enable medium switch. */ \ - false, /* Do not enable weak switch. */ \ - \ - emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ - emuPower_None, /* No connection between main and backup power. (active mode) */ \ - true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ - } -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -/** Backup Power Domain Initialization structure. */ -typedef struct { - bool disMaxComp; /**< Disable MAIN-BU Comparator. */ - EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ - EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ - EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ - EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ - bool buVinProbeEn; /**< Enable BU_VIN probing. */ - bool staEn; /**< Enable backup mode status export. */ - bool enable; /**< Enable backup power domain. */ -} EMU_BUInit_TypeDef; - -/** Default Backup Power Domain configuration. */ -#define EMU_BUINIT_DEFAULT \ - { \ - false, /* MAIN-BU Comparator is not disabled */ \ - emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \ - emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \ - emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \ - emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \ - false, /* BU_VIN probe is disabled */ \ - false, /* Status export is disabled */ \ - true /* Enable backup mode */ \ - } -#endif - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/** DCDC Boost regulator initialization structure. */ -typedef struct { - EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ - bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */ - EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ - EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ - EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ - EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ -} EMU_DCDCBoostInit_TypeDef; - -/** Default DCDC Boost initialization. */ -#define EMU_DCDCBOOSTINIT_DEFAULT \ - { \ - emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ - emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ - emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ - } -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/** DCDC regulator initialization structure. */ -typedef struct { - EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */ - EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */ - EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ -#if defined(_DCDC_CTRL_DCMONLYEN_MASK) - bool dcmOnlyEn; /**< DCM only mode enable. */ -#endif - EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ - EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ - EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ - EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ -} EMU_DCDCInit_TypeDef; - -/** Default DCDC Buck initialization. */ -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ - emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ - emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - true, /**< Enable DCM only mode. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ - emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ - emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ - emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ - emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ - } -#endif -#endif /* SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC initialization structure. */ -typedef struct { - EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. - @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ - EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ - uint16_t mVout; /**< Target output voltage (mV). */ - uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). - This estimate is also used for EM1 optimization; - if EM1 current is expected to be higher than EM0, - then this parameter should hold the higher EM1 current. */ - uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). - This estimate is also used for EM3 and 4 optimization; - if EM3 or 4 current is expected to be higher than EM2, - then this parameter should hold the higher EM3 or 4 current. */ - uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). - This can be set to the maximum for the power source, - for example the maximum for a battery. */ - EMU_DcdcAnaPeripheralPower_TypeDef - anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ - EMU_DcdcLnReverseCurrentControl_TypeDef - reverseCurrentControl; /**< Low-noise reverse current control. - NOTE: this parameter uses special encoding: - >= 0 is forced CCM mode where the parameter is used as the - reverse current threshold in mA. - -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ - EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ -} EMU_DCDCInit_TypeDef; - -/** Default DCDC initialization. */ -#if defined(_EFM_DEVICE) -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ - } -#elif defined(WGM160PX22KGA2) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#else -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#endif - -#else /* EFR32 device. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 15, /* Nominal EM0/1 load current of less than 15mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - 160, /* Maximum reverse current of 160mA. */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ - } -#else -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 15, /* Nominal EM0/1 load current of less than 15mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - 160, /* Maximum reverse current of 160mA. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#endif -#endif -#endif - -#if defined(EMU_STATUS_VMONRDY) -/** VMON initialization structure. */ -typedef struct { - EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ - int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ - bool riseWakeup; /**< Wake up from EM4H on rising edge. */ - bool fallWakeup; /**< Wake up from EM4H on falling edge. */ - bool enable; /**< Enable VMON channel. */ - bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ -} EMU_VmonInit_TypeDef; - -/** Default VMON initialization structure. */ -#define EMU_VMONINIT_DEFAULT \ - { \ - emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ - 3200, /* 3.2 V threshold. */ \ - false, /* Do not wake from EM4H on rising edge. */ \ - false, /* Do not wake from EM4H on falling edge. */ \ - true, /* Enable VMON channel. */ \ - false /* Do not disable IO0 retention */ \ - } - -/** VMON Hysteresis initialization structure. */ -typedef struct { - EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ - int riseThreshold; /**< Rising threshold (mV). */ - int fallThreshold; /**< Falling threshold (mV). */ - bool riseWakeup; /**< Wake up from EM4H on rising edge. */ - bool fallWakeup; /**< Wake up from EM4H on falling edge. */ - bool enable; /**< Enable VMON channel. */ -} EMU_VmonHystInit_TypeDef; - -/** Default VMON Hysteresis initialization structure. */ -#define EMU_VMONHYSTINIT_DEFAULT \ - { \ - emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ - 3200, /* 3.2 V rise threshold. */ \ - 3200, /* 3.2 V fall threshold. */ \ - false, /* Do not wake from EM4H on rising edge. */ \ - false, /* Do not wake from EM4H on falling edge. */ \ - true /* Enable VMON channel. */ \ - } -#endif /* EMU_STATUS_VMONRDY */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); -#endif -void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); -void EMU_EM23PresleepHook(void); -void EMU_EM23PostsleepHook(void); -void EMU_EFPEM23PresleepHook(void); -void EMU_EFPEM23PostsleepHook(void); -void EMU_EnterEM2(bool restore); -void EMU_EnterEM3(bool restore); -void EMU_Save(void); -void EMU_Restore(void); -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); -#endif -void EMU_EM4PresleepHook(void); -void EMU_EFPEM4PresleepHook(void); -void EMU_EnterEM4(void); -void EMU_EnterEM4Wait(void); -#if defined(_EMU_EM4CTRL_MASK) -void EMU_EnterEM4H(void); -void EMU_EnterEM4S(void); -#endif -void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1; -void EMU_RamPowerDown(uint32_t start, uint32_t end); -void EMU_RamPowerUp(void); -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); -#endif -void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1; -#if defined(EMU_VSCALE_EM01_PRESENT) -#if defined(_SILICON_LABS_32B_SERIES_2) -void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage); -#endif -void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); -void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); -#endif -#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) -void EMU_BUDisMaxCompSet(bool disableMainBuComparator); -#endif -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); -#endif -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); -#endif -#if defined(_EMU_BUCTRL_PWRRES_MASK) -void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); -#endif -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); -#endif -#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) -void EMU_BUBuVinProbeEnSet(bool enable); -#endif -#if defined(_EMU_BUCTRL_STATEN_MASK) -void EMU_BUStatEnSet(bool enable); -#endif -#if defined(_EMU_BUCTRL_EN_MASK) -void EMU_BUEnableSet(bool enable); -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -#endif - -#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) -sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -void EMU_DCDCUpdatedHook(void); -#endif - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); -void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); -void EMU_BoostExternalShutdownEnable(bool enable); -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); -bool EMU_DCDCPowerOff(void); -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); -#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) -void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); -#endif -#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) -void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value); -#endif -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#if defined(EMU_DCDCCTRL_DCDCMODEEM23) -void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23); -#endif -void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); -bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); -void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_STATUS_VMONRDY) -void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); -void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); -#endif -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); -#endif -#if defined(_EMU_TEMP_TEMP_MASK) -float EMU_TemperatureGet(void); -#endif -#if defined(EMU_CTRL_EFPDIRECTMODEEN) -void EMU_EFPDirectModeEnable(bool enable); -#endif -#if defined(EMU_CTRL_EFPDRVDECOUPLE) -void EMU_EFPDriveDecoupleSet(bool enable); -#endif -#if defined(EMU_CTRL_EFPDRVDVDD) -void EMU_EFPDriveDvddSet(bool enable); -#endif - -#if defined(_DCDC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Lock DCDC registers in order to protect them against unintended - * modification. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCLock(void) -{ - DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; -} -#endif - -#if defined(_DCDC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Unlock the DCDC so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCUnlock(void) -{ - DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; -} -#endif - -#if defined(_DCDC_SYNCBUSY_MASK) -/***************************************************************************//** - * @brief - * Wait for the DCDC to complete all synchronization of register changes. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCSync(uint32_t mask) -{ - while (0UL != (DCDC->SYNCBUSY & mask)) { - /* Wait for previous synchronization to finish */ - } -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Check status of the internal LDO regulator. - * - * @return - * Return true if the regulator is on, false if regulator is off. - ******************************************************************************/ -__STATIC_INLINE bool EMU_LDOStatusGet(void) -{ - if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) { - return true; - } else { - return false; - } -} -#endif - -/***************************************************************************//** - * @brief - * Enter energy mode 1 (EM1). - * - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - ******************************************************************************/ -__STATIC_INLINE void EMU_EnterEM1(void) -{ - /* Enter sleep mode. */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Wait for voltage scaling to complete. - ******************************************************************************/ -__STATIC_INLINE void EMU_VScaleWait(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip waiting if the LDO regulator is turned off. */ - return; - } -#endif - - while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { - } -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Get current voltage scaling level. - * - * @return - * Current voltage scaling level. - ******************************************************************************/ -__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) -{ - EMU_VScaleWait(); - return (EMU_VScaleEM01_TypeDef)((uint32_t) - ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) - >> _EMU_STATUS_VSCALE_SHIFT)); -} -#endif - -#if defined(_EMU_STATUS_VMONRDY_MASK) -/***************************************************************************//** - * @brief - * Get the status of the voltage monitor (VMON). - * - * @return - * Status of the VMON. True if all the enabled channels are ready, false if - * one or more of the enabled channels are not ready. - ******************************************************************************/ -__STATIC_INLINE bool EMU_VmonStatusGet(void) -{ - return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; -} -#endif /* _EMU_STATUS_VMONRDY_MASK */ - -#if defined(_EMU_IF_MASK) -/***************************************************************************//** - * @brief - * Clear one or more pending EMU interrupts. - * - * @param[in] flags - * Pending EMU interrupt sources to clear. Use one or more valid - * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntClear(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IF_CLR = flags; -#else - EMU->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more EMU interrupts. - * - * @param[in] flags - * EMU interrupt sources to disable. Use one or more valid - * interrupt flags for the EMU module (EMU_IEN_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntDisable(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IEN_CLR = flags; -#else - EMU->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more EMU interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * @ref EMU_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * EMU interrupt sources to enable. Use one or more valid - * interrupt flags for the EMU module (EMU_IEN_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntEnable(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IEN_SET = flags; -#else - EMU->IEN |= flags; -#endif -} - -#if defined(EMU_CTRL_EFPDRVDVDD) -/***************************************************************************//** - * @brief - * Disable one or more EFP interrupts. - * - * @param[in] flags - * EFP interrupt sources to disable. Use one or more valid - * interrupt flags for the EFP module (EFPIENnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags) -{ - EMU->EFPIEN_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more EFP interrupts. - * - * @param[in] flags - * EFP interrupt sources to enable. Use one or more valid - * interrupt flags for the EFP module (EFPIENnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags) -{ - EMU->EFPIEN_SET = flags; -} - -/***************************************************************************//** - * @brief - * Get pending EMU EFP interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * EMU EFP interrupt sources pending. . - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_EFPIntGet(void) -{ - return EMU->EFPIF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending EMU EFP interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled EMU EFP interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in EMU_EFPIEN and - * - the pending interrupt flags EMU_EFPIF. - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void) -{ - uint32_t ien; - - ien = EMU->EFPIEN; - return EMU->EFPIF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending EMU EFP interrupts. - * - * @param[in] flags - * EMU EFP interrupt sources to set to pending. Use one or more valid - * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntSet(uint32_t flags) -{ - EMU->EFPIF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Clear one or more pending EMU EFP interrupts. - * - * @param[in] flags - * Pending EMU EFP interrupt sources to clear. Use one or more valid - * interrupt flags for the EMU EFP module. - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntClear(uint32_t flags) -{ - EMU->EFPIF_CLR = flags; -} -#endif - -/***************************************************************************//** - * @brief - * Get pending EMU interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * EMU interrupt sources pending. Returns one or more valid - * interrupt flags for the EMU module (EMU_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_IntGet(void) -{ - return EMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending EMU interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled EMU interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in EMU_IEN and - * - the pending interrupt flags EMU_IF. - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = EMU->IEN; - return EMU->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending EMU interrupts. - * - * @param[in] flags - * EMU interrupt sources to set to pending. Use one or more valid - * interrupt flags for the EMU module (EMU_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntSet(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IF_SET = flags; -#else - EMU->IFS = flags; -#endif -} -#endif /* _EMU_IF_MASK */ - -#if defined(_EMU_EM4CONF_LOCKCONF_MASK) -/***************************************************************************//** - * @brief - * Enable or disable EM4 lock configuration. - * @param[in] enable - * If true, locks down EM4 configuration. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM4Lock(bool enable) -{ - BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); -} -#endif - -#if defined(_EMU_STATUS_BURDY_MASK) -/***************************************************************************//** - * @brief - * Halts until backup power functionality is ready. - ******************************************************************************/ -__STATIC_INLINE void EMU_BUReady(void) -{ - while (!(EMU->STATUS & EMU_STATUS_BURDY)) - ; -} -#endif - -#if defined(_EMU_ROUTE_BUVINPEN_MASK) -/***************************************************************************//** - * @brief - * Disable BU_VIN support. - * @param[in] enable - * If true, enables BU_VIN input pin support, if false disables it. - ******************************************************************************/ -__STATIC_INLINE void EMU_BUPinEnable(bool enable) -{ - BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); -} -#endif - -/***************************************************************************//** - * @brief - * Lock EMU registers in order to protect them against unintended - * modification. - * - * @note - * If locking EMU registers, they must be unlocked prior to using any - * EMU API functions modifying EMU registers, excluding interrupt control - * and regulator control if the architecture has a EMU_PWRCTRL register. - * An exception to this is the energy mode entering API (EMU_EnterEMn()), - * which can be used when the EMU registers are locked. - ******************************************************************************/ -__STATIC_INLINE void EMU_Lock(void) -{ - EMU->LOCK = 0x0; -} - -/***************************************************************************//** - * @brief - * Unlock the EMU so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_Unlock(void) -{ - EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; -} - -#if defined(_EMU_PWRLOCK_MASK) -/***************************************************************************//** - * @brief - * Lock the EMU regulator control registers in order to protect against - * unintended modification. - ******************************************************************************/ -__STATIC_INLINE void EMU_PowerLock(void) -{ - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; -} - -/***************************************************************************//** - * @brief - * Unlock the EMU power control registers so that writing to - * locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_PowerUnlock(void) -{ - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; -} -#endif - -#if defined(_EMU_CTRL_EM2BLOCK_MASK) -/***************************************************************************//** - * @brief - * Block entering EM2 or higher number energy modes. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM2Block(void) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); -} - -/***************************************************************************//** - * @brief - * Unblock entering EM2 or higher number energy modes. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM2UnBlock(void) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); -} -#endif - -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/***************************************************************************//** - * @brief - * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained - * through EM4 entry and wakeup. The pin state is released by calling this function. - * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), - * and when initialization is done, this function can release pins and return control - * to the peripherals or GPIO. - ******************************************************************************/ -__STATIC_INLINE void EMU_UnlatchPinRetention(void) -{ - EMU->CMD = EMU_CMD_EM4UNLATCH; -} -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/** Zero degrees Celcius in Kelvin */ -#define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f) -/***************************************************************************//** - * @brief - * Temperature measurement ready status - * - * @return - * True if temperature measurement is ready - ******************************************************************************/ -__STATIC_INLINE bool EMU_TemperatureReady(void) -{ -#if defined(EMU_STATUS_FIRSTTEMPDONE) - return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); -#else - return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u); -#endif -} - -#if defined(_EMU_TEMP_TEMPAVG_MASK) -/***************************************************************************//** - * @brief - * Get averaged temperature in degrees Celsius. - * - * @note - * An averaged temperature measurement must first be requested by calling - * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag - * to go high. - * - * @return - * Averaged temperature - ******************************************************************************/ -__STATIC_INLINE float EMU_TemperatureAvgGet(void) -{ - uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK) - >> _EMU_TEMP_TEMPAVG_SHIFT); - return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; -} - -/***************************************************************************//** - * @brief - * Request averaged temperature. - * - * @note - * EMU must be unlocked by calling @ref EMU_Unlock() before this function - * can be called. - * - * @param[in] numSamples - * Number of temperature samples to average - ******************************************************************************/ -__STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples); - EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT; -} - -#endif //defined(_EMU_TEMP_TEMPAVG_MASK) -#endif //defined(_EMU_TEMP_TEMP_MASK) - -/** @} (end addtogroup emu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( EMU_PRESENT ) */ -#endif /* EM_EMU_H */ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EMU_H +#define EM_EMU_H + +#include "em_device.h" +#include "sl_status.h" +#if defined(EMU_PRESENT) + +#include +#include "em_bus.h" +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) +/** Voltage scaling present */ +#define EMU_VSCALE_PRESENT +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +/** Voltage scaling for EM01 present */ +#define EMU_VSCALE_EM01_PRESENT +#endif +#endif + +#if defined(_EMU_DCDCCTRL_MASK) +/** DC-DC buck converter present */ +#define EMU_SERIES1_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC buck converter present */ +#define EMU_SERIES2_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC boost converter present */ +#define EMU_SERIES2_DCDC_BOOST_PRESENT +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_EMU_EM4CONF_OSC_MASK) +/** EM4 duty oscillator. */ +typedef enum { + /** Select ULFRCO as duty oscillator in EM4. */ + emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, + /** Select LFXO as duty oscillator in EM4. */ + emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, + /** Select LFRCO as duty oscillator in EM4. */ + emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO +} EMU_EM4Osc_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PROBE_MASK) +/** Backup Power Voltage Probe types. */ +typedef enum { + /** Disable voltage probe. */ + emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, + /** Connect probe to VDD_DREG. */ + emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, + /** Connect probe to BU_IN. */ + emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, + /** Connect probe to BU_OUT. */ + emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT +} EMU_Probe_TypeDef; +#endif + +#if defined(_EMU_PWRCONF_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, +} EMU_Resistor_TypeDef; +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain power connection. */ +typedef enum { + /** No connection between main and backup power. */ + emuPower_None = EMU_BUINACT_PWRCON_NONE, + /** Main power and backup power connected through diode, + allowing current from backup to main only. */ + emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, + /** Main power and backup power connected through diode, + allowing current from main to backup only. */ + emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, + /** Main power and backup power connected without diode. */ + emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, +} EMU_Power_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/** Backup Power Domain power connection configuration when not in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, +} EMU_BUBuInactPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/** Backup Power Domain power connection configuration in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, +} EMU_BUBuActPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, +} EMU_BUPwrRes_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/** Resistance between backup domain power supply and BU_VOUT. */ +typedef enum { + /** BU_VOUT is not connected. */ + emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, + /** Enable weak switch. */ + emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, + /** Enable medium switch. */ + emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, + /** Enable strong switch. */ + emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, +} EMU_BUVoutRes_TypeDef; +#endif + +/** BOD threshold setting selector, active or inactive mode. */ +typedef enum { + /** Configure BOD threshold for active mode. */ + emuBODMode_Active, + /** Configure BOD threshold for inactive mode. */ + emuBODMode_Inactive, +} EMU_BODMode_TypeDef; + +/** EM4 modes. */ +typedef enum { + /** EM4 Shutoff. */ + emuEM4Shutoff = 0, + /** EM4 Hibernate. */ + emuEM4Hibernate = 1, +} EMU_EM4State_TypeDef; + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/** EM4 Pin Retention Type. */ +typedef enum { + /** No Retention: Pads enter reset state when entering EM4. */ + emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, + /** Retention through EM4: Pads enter reset state when exiting EM4. */ + emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, + /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to + release pins from retention after EM4 wakeup. */ + emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, +} EMU_EM4PinRetention_TypeDef; +#endif + +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ +typedef enum { + /** DCDC is connected to DVDD. */ + emuPowerConfig_DcdcToDvdd, +} EMU_PowerConfig_TypeDef; + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC operating modes. */ +typedef enum { + /** DCDC regulator bypass. */ + emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, + /** DCDC low-noise mode. */ + emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, +#if defined(_EMU_DCDCLPEM01CFG_MASK) + /** DCDC low-power mode. */ + emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, +#endif +} EMU_DcdcMode_TypeDef; + +/** DCDC operating modes in EM2 or EM3. */ +typedef enum { + /** DCDC mode is low power. */ + emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER, + /** DCDC mode is according to DCDCMODE field. */ + emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW, +} EMU_DcdcModeEM23_TypeDef; + +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC conduction modes. */ +typedef enum { + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + for EFR32 when its radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + +#if defined(_EMU_PWRCTRL_MASK) +/** DCDC to DVDD mode analog peripheral power supply select. */ +typedef enum { + /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ + emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, + /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ + emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD +} EMU_DcdcAnaPeripheralPower_TypeDef; +#endif + +#if defined(_EMU_DCDCMISCCTRL_MASK) +/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ +typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; + +/** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ +#define emuDcdcLnHighEfficiency -1 + +/** Default reverse current for fast transient response mode (low noise). */ +#define emuDcdcLnFastTransient 160 +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC Low-noise RCO band select. */ +typedef enum { + /** Set RCO to 3MHz. */ + emuDcdcLnRcoBand_3MHz = 0, + /** Set RCO to 4MHz. */ + emuDcdcLnRcoBand_4MHz = 1, + /** Set RCO to 5MHz. */ + emuDcdcLnRcoBand_5MHz = 2, + /** Set RCO to 6MHz. */ + emuDcdcLnRcoBand_6MHz = 3, + /** Set RCO to 7MHz. */ + emuDcdcLnRcoBand_7MHz = 4, + /** Set RCO to 8MHz. */ + emuDcdcLnRcoBand_8MHz = 5, + /** Set RCO to 9MHz. */ + emuDcdcLnRcoBand_9MHz = 6, + /** Set RCO to 10MHz. */ + emuDcdcLnRcoBand_10MHz = 7, +} EMU_DcdcLnRcoBand_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated. */ +#define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz +#define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz +#define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz +#define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz +#define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz +#define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz +#define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz +#define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz +/** @endcond */ + +/** DCDC Low Noise Compensator Control register. */ +typedef enum { + /** DCDC capacitor is 1uF. */ + emuDcdcLnCompCtrl_1u0F, + /** DCDC capacitor is 4.7uF. */ + emuDcdcLnCompCtrl_4u7F, +} EMU_DcdcLnCompCtrl_TypeDef; +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) + +/** DCDC mode. */ +typedef enum { + emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */ + emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */ +} EMU_DcdcMode_TypeDef; +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** VREGIN comparator threshold. */ +typedef enum { + emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */ + emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */ + emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */ + emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */ +} EMU_VreginCmpThreshold_TypeDef; + +/** DCDC Buck Ton max timeout. */ +typedef enum { +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) + emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */ +#else + emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */ + emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */ + emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */ + emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */ + emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */ + emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */ + emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */ + emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */ + emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */ + emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */ + emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */ + emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */ + emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */ + emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */ + emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */ + emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */ + emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */ + emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */ + emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */ + emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */ + emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */ + emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */ + emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */ + emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */ + emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */ +#endif +} EMU_DcdcTonMaxTimeout_TypeDef; + +/** DCDC Buck drive speed. */ +typedef enum { + emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcDriveSpeed_TypeDef; + +/** DCDC Buck peak current setting. */ +typedef enum { +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA) + emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA) + emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA) + emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ +#endif + emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ + emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ + emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ + emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ + emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ + emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA) + emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA) + emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA) + emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA) + emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA) + emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ +#endif +} EMU_DcdcPeakCurrent_TypeDef; +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost drive speed. */ +typedef enum { + emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcBoostDriveSpeed_TypeDef; + +/** DCDC Boost EM01 peak current setting. */ +typedef enum { + emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ + emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ + emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ + emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ + emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ + emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ + emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ + emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ + emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ + emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ +} EMU_DcdcBoostEM01PeakCurrent_TypeDef; + +/** DCDC Boost Toff max timeout */ +typedef enum { + emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */ + emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */ + emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */ + emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */ + emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */ + emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */ + emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */ + emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */ +} EMU_DcdcBoostToffMaxTimeout_TypeDef; + +/** DCDC Boost peak current detection maximum timeout */ +typedef enum { + emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */ +} EMU_DcdcBoostTonMaxTimeout_TypeDef; + +/** DCDC Boost EM23 peak current setting. */ +typedef enum { + emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ +} EMU_DcdcBoostEM23PeakCurrent_TypeDef; +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ + +#if defined(EMU_STATUS_VMONRDY) +/** VMON channels. */ +typedef enum { + emuVmonChannel_AVDD, + emuVmonChannel_ALTAVDD, + emuVmonChannel_DVDD, + emuVmonChannel_IOVDD0, +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + emuVmonChannel_IOVDD1, +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + emuVmonChannel_BUVDD, +#endif +} EMU_VmonChannel_TypeDef; +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/** Bias mode configurations. */ +typedef enum { + emuBiasMode_1KHz, + emuBiasMode_4KHz, + emuBiasMode_Continuous +} EMU_BiasMode_TypeDef; +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** Supported EM0/1 Voltage Scaling Levels. */ +typedef enum { + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. HF clock must be limited + to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when core clock frequency is + changed from @ref cmu or when calling @ref EMU_EM01Init() when HF + clock is already below the limit. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + /** Minimum VSCALE level in EM0/1 is VSCALE1. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1, +#else + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +#endif +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined(EMU_VSCALE_PRESENT) +/** Supported EM2/3 Voltage Scaling Levels. */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control. */ +typedef enum { +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */ +#endif + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */ +#endif + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */ +#endif + emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */ +#endif + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */ +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2 +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + | emuPeripheralRetention_WDOG1 +#endif + | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */ +} EMU_PeripheralRetention_TypeDef; +#endif + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/** Number of samples to use for temperature averaging. */ +typedef enum { + /** 16 samples used for temperature averaging. */ + emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16, + /** 64 samples used for temperature averaging. */ + emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64, +} EMU_TempAvgNum_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance + is always enabled. */ +typedef struct { + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ +} EMU_EM01Init_TypeDef; + +/** Default initialization of EM0 and 1 configuration. */ +#define EMU_EM01INIT_DEFAULT \ + { \ + false /* Do not scale down in EM0/1.*/ \ + } +#endif + +/** EM2 and 3 initialization structure. */ +typedef struct { + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ +#if defined(EMU_VSCALE_PRESENT) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ +#endif +} EMU_EM23Init_TypeDef; + +/** Default initialization of EM2 and 3 configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ + } +#else +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + } +#endif + +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/** EM4 initialization structure. */ +typedef struct { +#if defined(_EMU_EM4CONF_MASK) + /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ + bool vreg; /**< Enable EM4 voltage regulator. */ +#elif defined(_EMU_EM4CTRL_MASK) + /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ + bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ + bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ + bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ + EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ + EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ +#endif +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ +#endif +} EMU_EM4Init_TypeDef; +#endif + +#if defined(_EMU_EM4CONF_MASK) +/** Default initialization of EM4 configuration (Series 0). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Do not lock configuration after it's been set. */ \ + false, /* No reset will be asserted due to BOD in EM4. */ \ + emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ + true, /* Wake up on EM4 BURTC interrupt. */ \ + true, /* Enable VREG. */ \ + } + +#elif defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Default initialization of EM4 configuration (Series 1 with VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ + } + +#elif defined(_EMU_EM4CTRL_MASK) +/** Default initialization of EM4 configuration (Series 1 without VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain Initialization structure. */ +typedef struct { + /* Backup Power Domain power configuration. */ + + /** Voltage probe select, selects ADC voltage. */ + EMU_Probe_TypeDef probe; + /** Enable BOD calibration mode. */ + bool bodCal; + /** Enable BU_STAT status pin for active BU mode. */ + bool statusPinEnable; + + /* Backup Power Domain connection configuration. */ + /** Power domain resistor. */ + EMU_Resistor_TypeDef resistor; + /** BU_VOUT strong enable. */ + bool voutStrong; + /** BU_VOUT medium enable. */ + bool voutMed; + /** BU_VOUT weak enable. */ + bool voutWeak; + /** Power connection, when not in Backup Mode. */ + EMU_Power_TypeDef inactivePower; + /** Power connection, when in Backup Mode. */ + EMU_Power_TypeDef activePower; + /** Enable backup power domain, and release reset, enable BU_VIN pin. */ + bool enable; +} EMU_BUPDInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUPDINIT_DEFAULT \ + { \ + emuProbe_Disable, /* Do not enable voltage probe. */ \ + false, /* Disable BOD calibration mode. */ \ + false, /* Disable BU_STAT pin for backup mode indication. */ \ + \ + emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ + false, /* Do not enable strong switch. */ \ + false, /* Do not enable medium switch. */ \ + false, /* Do not enable weak switch. */ \ + \ + emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ + emuPower_None, /* No connection between main and backup power. (active mode) */ \ + true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/** Backup Power Domain Initialization structure. */ +typedef struct { + bool disMaxComp; /**< Disable MAIN-BU Comparator. */ + EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ + EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ + EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ + EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ + bool buVinProbeEn; /**< Enable BU_VIN probing. */ + bool staEn; /**< Enable backup mode status export. */ + bool enable; /**< Enable backup power domain. */ +} EMU_BUInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUINIT_DEFAULT \ + { \ + false, /* MAIN-BU Comparator is not disabled */ \ + emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \ + emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \ + emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \ + emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \ + false, /* BU_VIN probe is disabled */ \ + false, /* Status export is disabled */ \ + true /* Enable backup mode */ \ + } +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost regulator initialization structure. */ +typedef struct { + EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ + bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +} EMU_DCDCBoostInit_TypeDef; + +/** Default DCDC Boost initialization. */ +#define EMU_DCDCBOOSTINIT_DEFAULT \ + { \ + emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ + } +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** DCDC regulator initialization structure. */ +typedef struct { + EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */ + EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */ + EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + bool dcmOnlyEn; /**< DCM only mode enable. */ +#endif + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC Buck initialization. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< Enable DCM only mode. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#endif +#endif /* SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC initialization structure. */ +typedef struct { + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ + EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ + uint16_t mVout; /**< Target output voltage (mV). */ + uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). + This estimate is also used for EM1 optimization; + if EM1 current is expected to be higher than EM0, + then this parameter should hold the higher EM1 current. */ + uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). + This estimate is also used for EM3 and 4 optimization; + if EM3 or 4 current is expected to be higher than EM2, + then this parameter should hold the higher EM3 or 4 current. */ + uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). + This can be set to the maximum for the power source, + for example the maximum for a battery. */ + EMU_DcdcAnaPeripheralPower_TypeDef + anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ + EMU_DcdcLnReverseCurrentControl_TypeDef + reverseCurrentControl; /**< Low-noise reverse current control. + NOTE: this parameter uses special encoding: + >= 0 is forced CCM mode where the parameter is used as the + reverse current threshold in mA. + -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ + EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC initialization. */ +#if defined(_EFM_DEVICE) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#elif defined(WGM160PX22KGA2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif + +#else /* EFR32 device. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif +#endif +#endif + +#if defined(EMU_STATUS_VMONRDY) +/** VMON initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ + bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ +} EMU_VmonInit_TypeDef; + +/** Default VMON initialization structure. */ +#define EMU_VMONINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true, /* Enable VMON channel. */ \ + false /* Do not disable IO0 retention */ \ + } + +/** VMON Hysteresis initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int riseThreshold; /**< Rising threshold (mV). */ + int fallThreshold; /**< Falling threshold (mV). */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ +} EMU_VmonHystInit_TypeDef; + +/** Default VMON Hysteresis initialization structure. */ +#define EMU_VMONHYSTINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V rise threshold. */ \ + 3200, /* 3.2 V fall threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true /* Enable VMON channel. */ \ + } +#endif /* EMU_STATUS_VMONRDY */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); +void EMU_EM23PresleepHook(void); +void EMU_EM23PostsleepHook(void); +void EMU_EFPEM23PresleepHook(void); +void EMU_EFPEM23PostsleepHook(void); +void EMU_EnterEM2(bool restore); +void EMU_EnterEM3(bool restore); +void EMU_Save(void); +void EMU_Restore(void); +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); +#endif +void EMU_EM4PresleepHook(void); +void EMU_EFPEM4PresleepHook(void); +void EMU_EnterEM4(void); +void EMU_EnterEM4Wait(void); +#if defined(_EMU_EM4CTRL_MASK) +void EMU_EnterEM4H(void); +void EMU_EnterEM4S(void); +#endif +void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1; +void EMU_RamPowerDown(uint32_t start, uint32_t end); +void EMU_RamPowerUp(void); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif +void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1; +#if defined(EMU_VSCALE_EM01_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) +void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage); +#endif +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); +#endif +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +void EMU_BUDisMaxCompSet(bool disableMainBuComparator); +#endif +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); +#endif +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); +#endif +#if defined(_EMU_BUCTRL_PWRRES_MASK) +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); +#endif +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); +#endif +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +void EMU_BUBuVinProbeEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_STATEN_MASK) +void EMU_BUStatEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_EN_MASK) +void EMU_BUEnableSet(bool enable); +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +void EMU_DCDCUpdatedHook(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); +void EMU_BoostExternalShutdownEnable(bool enable); +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +bool EMU_DCDCPowerOff(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); +#endif +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value); +#endif +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23); +#endif +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); +bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); +#endif +#if defined(_EMU_TEMP_TEMP_MASK) +float EMU_TemperatureGet(void); +#endif +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +void EMU_EFPDirectModeEnable(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +void EMU_EFPDriveDecoupleSet(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDVDD) +void EMU_EFPDriveDvddSet(bool enable); +#endif + +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Lock DCDC registers in order to protect them against unintended + * modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCLock(void) +{ + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Unlock the DCDC so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCUnlock(void) +{ + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_SYNCBUSY_MASK) +/***************************************************************************//** + * @brief + * Wait for the DCDC to complete all synchronization of register changes. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCSync(uint32_t mask) +{ + while (0UL != (DCDC->SYNCBUSY & mask)) { + /* Wait for previous synchronization to finish */ + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Check status of the internal LDO regulator. + * + * @return + * Return true if the regulator is on, false if regulator is off. + ******************************************************************************/ +__STATIC_INLINE bool EMU_LDOStatusGet(void) +{ + if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) { + return true; + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Enter energy mode 1 (EM1). + * + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + ******************************************************************************/ +__STATIC_INLINE void EMU_EnterEM1(void) +{ + /* Enter sleep mode. */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete. + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip waiting if the LDO regulator is turned off. */ + return; + } +#endif + + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Get current voltage scaling level. + * + * @return + * Current voltage scaling level. + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((uint32_t) + ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT)); +} +#endif + +#if defined(_EMU_STATUS_VMONRDY_MASK) +/***************************************************************************//** + * @brief + * Get the status of the voltage monitor (VMON). + * + * @return + * Status of the VMON. True if all the enabled channels are ready, false if + * one or more of the enabled channels are not ready. + ******************************************************************************/ +__STATIC_INLINE bool EMU_VmonStatusGet(void) +{ + return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; +} +#endif /* _EMU_STATUS_VMONRDY_MASK */ + +#if defined(_EMU_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending EMU interrupts. + * + * @param[in] flags + * Pending EMU interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntClear(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_CLR = flags; +#else + EMU->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to disable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntDisable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_CLR = flags; +#else + EMU->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more EMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * @ref EMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * EMU interrupt sources to enable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntEnable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_SET = flags; +#else + EMU->IEN |= flags; +#endif +} + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Disable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to disable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags) +{ + EMU->EFPIEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to enable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags) +{ + EMU->EFPIEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending EMU EFP interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU EFP interrupt sources pending. . + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGet(void) +{ + return EMU->EFPIF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU EFP interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU EFP interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_EFPIEN and + * - the pending interrupt flags EMU_EFPIF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->EFPIEN; + return EMU->EFPIF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU EFP interrupts. + * + * @param[in] flags + * EMU EFP interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntSet(uint32_t flags) +{ + EMU->EFPIF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending EMU EFP interrupts. + * + * @param[in] flags + * Pending EMU EFP interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU EFP module. + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntClear(uint32_t flags) +{ + EMU->EFPIF_CLR = flags; +} +#endif + +/***************************************************************************//** + * @brief + * Get pending EMU interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU interrupt sources pending. Returns one or more valid + * interrupt flags for the EMU module (EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGet(void) +{ + return EMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_IEN and + * - the pending interrupt flags EMU_IF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->IEN; + return EMU->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU module (EMU_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntSet(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_SET = flags; +#else + EMU->IFS = flags; +#endif +} +#endif /* _EMU_IF_MASK */ + +#if defined(_EMU_EM4CONF_LOCKCONF_MASK) +/***************************************************************************//** + * @brief + * Enable or disable EM4 lock configuration. + * @param[in] enable + * If true, locks down EM4 configuration. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM4Lock(bool enable) +{ + BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); +} +#endif + +#if defined(_EMU_STATUS_BURDY_MASK) +/***************************************************************************//** + * @brief + * Halts until backup power functionality is ready. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUReady(void) +{ + while (!(EMU->STATUS & EMU_STATUS_BURDY)) + ; +} +#endif + +#if defined(_EMU_ROUTE_BUVINPEN_MASK) +/***************************************************************************//** + * @brief + * Disable BU_VIN support. + * @param[in] enable + * If true, enables BU_VIN input pin support, if false disables it. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUPinEnable(bool enable) +{ + BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); +} +#endif + +/***************************************************************************//** + * @brief + * Lock EMU registers in order to protect them against unintended + * modification. + * + * @note + * If locking EMU registers, they must be unlocked prior to using any + * EMU API functions modifying EMU registers, excluding interrupt control + * and regulator control if the architecture has a EMU_PWRCTRL register. + * An exception to this is the energy mode entering API (EMU_EnterEMn()), + * which can be used when the EMU registers are locked. + ******************************************************************************/ +__STATIC_INLINE void EMU_Lock(void) +{ + EMU->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_Unlock(void) +{ + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; +} + +#if defined(_EMU_PWRLOCK_MASK) +/***************************************************************************//** + * @brief + * Lock the EMU regulator control registers in order to protect against + * unintended modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerLock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU power control registers so that writing to + * locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerUnlock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; +} +#endif + +#if defined(_EMU_CTRL_EM2BLOCK_MASK) +/***************************************************************************//** + * @brief + * Block entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2Block(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); +} + +/***************************************************************************//** + * @brief + * Unblock entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2UnBlock(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); +} +#endif + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/***************************************************************************//** + * @brief + * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained + * through EM4 entry and wakeup. The pin state is released by calling this function. + * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), + * and when initialization is done, this function can release pins and return control + * to the peripherals or GPIO. + ******************************************************************************/ +__STATIC_INLINE void EMU_UnlatchPinRetention(void) +{ + EMU->CMD = EMU_CMD_EM4UNLATCH; +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/** Zero degrees Celcius in Kelvin */ +#define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f) +/***************************************************************************//** + * @brief + * Temperature measurement ready status + * + * @return + * True if temperature measurement is ready + ******************************************************************************/ +__STATIC_INLINE bool EMU_TemperatureReady(void) +{ +#if defined(EMU_STATUS_FIRSTTEMPDONE) + return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); +#else + return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u); +#endif +} + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/***************************************************************************//** + * @brief + * Get averaged temperature in degrees Celsius. + * + * @note + * An averaged temperature measurement must first be requested by calling + * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag + * to go high. + * + * @return + * Averaged temperature + ******************************************************************************/ +__STATIC_INLINE float EMU_TemperatureAvgGet(void) +{ + uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK) + >> _EMU_TEMP_TEMPAVG_SHIFT); + return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +} + +/***************************************************************************//** + * @brief + * Request averaged temperature. + * + * @note + * EMU must be unlocked by calling @ref EMU_Unlock() before this function + * can be called. + * + * @param[in] numSamples + * Number of temperature samples to average + ******************************************************************************/ +__STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples); + EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT; +} + +#endif //defined(_EMU_TEMP_TEMPAVG_MASK) +#endif //defined(_EMU_TEMP_TEMP_MASK) + +/** @} (end addtogroup emu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( EMU_PRESENT ) */ +#endif /* EM_EMU_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h index b0c6a3b..ecc5589 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h @@ -1,1223 +1,1223 @@ -/***************************************************************************//** - * @file - * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EUSART_H -#define EM_EUSART_H -#include "em_device.h" -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) -#include "sl_enum.h" -#include "em_eusart_compat.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* *INDENT-OFF* */ -// ***************************************************************************** -/// @addtogroup eusart EUSART - Extended USART -/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter -/// -/// @li @ref eusart_intro -/// @li @ref eusart_example -/// @li @ref eusart_em2 -/// -///@n @section eusart_intro Introduction -/// This module contains functions to control the Enhanced Universal Synchronous -/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon -/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, -/// therefore, be connected to an external transceiver to communicate with -/// another host using the serial link. -/// -/// It supports full duplex asynchronous UART communication as well as RS-485, -/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, -/// and IrDA devices. -/// -/// EUSART has a wide selection of operating modes, frame formats, and baud rates. -/// All features are supported through the API of this module. -/// -/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers -/// provide full support for DMA and more. -/// -///@n @section eusart_example Example -/// -/// EUSART Async TX example: -/// @code{.c} -/// { -/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; -/// -/// // Configure the clocks. -/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); -/// CMU_ClockEnable(cmuClock_EUSART0CLK, true); -/// // Initialize the EUSART -/// EUSART_UartInitHf(EUSART0, &init); -/// EUSART_Tx(EUSART0, data); -/// } -/// -/// @endcode -/// -/// EUSART Sync SPI Transaction example: -/// @code{.c} -/// { -/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF; -/// -/// // Configure the clocks. -/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); -/// CMU_ClockEnable(cmuClock_EUSART1, true); -/// CMU_ClockEnable(cmuClock_GPIO, true); -/// -/// //Configure the SPI ports -/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0); -/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0); -/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0); -/// -/// // Connect EUSART to ports -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT) -/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT) -/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) -/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN; -/// -/// // Initialize the EUSART -/// EUSART_SpiInit(EUSART1, &init_master); -/// EUSART_Spi_TxRx(EUSART1, data); -/// } -/// -/// @endcode -///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances -/// -/// @note EUSART instances located in the PD1 power domain are non EM2-capable. -/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used -/// to determine whether or not a EUSART instance is EM2-Capable. -/// -/// Follow theses steps when entering in EM2: -/// -# Wait for the current transaction to complete with TXCIF interrupt -/// -# Disable TX and RX using TXDIS and RXDIS cmd -/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low -/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low -/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled -/// -# Enter EM2 -/// -/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO -/// (SCLKPEN and CSPEN) must be re-enabled. For example: -/// -/// @code{.c} -/// { -/// // Enable TX and RX -/// EUSART_Enable(EUSART0, eusartEnable); -/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN, -/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, -/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); -/// } -/// @endcode -/// -/// @{ -// ***************************************************************************** -/* *INDENT-ON* */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Define EUSART FIFO Depth information */ -#if !defined(EUSART_FIFO_DEPTH) -#if defined(EUART_PRESENT) -#define EUSART0_FIFO_DEPTH 4 -#elif defined(EUSART_PRESENT) -#define EUSART0_FIFO_DEPTH 16 -#endif /* EUART_PRESENT */ -#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH - -#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \ - : ((n) == 1) ? EUSART1_FIFO_DEPTH \ - : ((n) == 2) ? EUSART2_FIFO_DEPTH \ - : ((n) == 3) ? EUSART3_FIFO_DEPTH \ - : ((n) == 4) ? EUSART4_FIFO_DEPTH \ - : 0x0UL) -#endif /* EUSART_FIFO_DEPTH */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/// Enable selection. -typedef enum { - /// Disable the peripheral. - eusartDisable = 0x0, - - /// Enable receiver only, transmitter disabled. - eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS), - - /// Enable transmitter only, receiver disabled. - eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS), - - /// Enable both receiver and transmitter. - eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN) -} EUSART_Enable_TypeDef; - -/// Data bit selection. -typedef enum { - eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits. - eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits. - eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits. -#if defined(EUSART_PRESENT) - eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only. - eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only. - eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only. - eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only. - eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only. - eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only. - eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only. -#endif -} EUSART_Databits_TypeDef; - -/// Parity selection. -typedef enum { - eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity. - eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity. - eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity. -} EUSART_Parity_TypeDef; - -/// Stop bits selection. -typedef enum { - eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits. - eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits. - eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits. - eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits. -} EUSART_Stopbits_TypeDef; - -/// Oversampling selection, used for asynchronous operation. -typedef enum { - eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal). - eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling. - eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling. - eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling. - eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled. -} EUSART_OVS_TypeDef; - -/// HW flow control config. -typedef enum { - eusartHwFlowControlNone = 0, ///< No HW Flow Control. - eusartHwFlowControlCts, ///< CTS HW Flow Control. - eusartHwFlowControlRts, ///< RTS HW Flow Control. - eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control. -} EUSART_HwFlowControl_TypeDef; - -/// Loopback enable. -typedef enum { - eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback. - eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback. -} EUSART_LoopbackEnable_TypeDef; - -/// Majority vote enable. -typedef enum { - eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes. - eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes. -} EUSART_MajorityVote_TypeDef; - -/// Block reception enable. -typedef enum { - eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded. - eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO. -} EUSART_BlockRx_TypeDef; - -/// TX output tristate enable. -typedef enum { - eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output. - eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output. -} EUSART_TristateTx_TypeDef; - -/// IrDA filter enable. -typedef enum { - eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator. - eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator. -} EUSART_IrDARxFilterEnable_TypeDef; - -/// Pulse width selection for IrDA mode. -typedef enum { - /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8 - eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE, - - /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8 - eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO, - - /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8 - eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE, - - /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8 - eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR -} EUSART_IrDAPulseWidth_Typedef; - -/// PRS trigger enable. -typedef enum { - /// Disable trigger on both receiver and transmitter. - eusartPrsTriggerDisable = 0x0, - - /// Enable receive trigger only, transmit disabled. - eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN, - - /// Enable transmit trigger only, receive disabled. - eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN, - - /// Enable trigger on both receive and transmit. - eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN) -} EUSART_PrsTriggerEnable_TypeDef; - -/// PRS Channel type. -typedef uint8_t EUSART_PrsChannel_TypeDef; - -/// IO polarity selection. -typedef enum { - /// Disable inversion on both RX and TX signals. - eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE), - - /// Invert RX signal, before receiver. - eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE, - - /// Invert TX signal, after transmitter. - eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE, - - /// Enable trigger on both receive and transmit. - eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) -} EUSART_InvertIO_TypeDef; - -/// Auto TX delay transmission. -SL_ENUM(EUSART_AutoTxDelay_TypeDef) { - /// Frames are transmitted immediately. - eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE, - - /// Transmission of new frames is delayed by a single bit period. - eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE, - - /// Transmission of new frames is delayed by a two bit periods. - eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE, - - /// Transmission of new frames is delayed by a three bit periods. - eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE -}; - -/// RX FIFO Interrupt ans Status Watermark. -typedef enum { - eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME, - eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES, - eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES, - eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES, -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES, - eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES, - eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES, - eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES, - eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES, - eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES, - eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES, - eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES, - eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES, - eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES, - eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES, - eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES -#endif -} EUSART_RxFifoWatermark_TypeDef; - -/// TX FIFO Interrupt and Status Watermark. -typedef enum { - eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME, - eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES, - eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES, - eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES, -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES, - eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES, - eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES, - eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES, - eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES, - eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES, - eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES, - eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES, - eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES, - eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES, - eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES, - eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES -#endif -} EUSART_TxFifoWatermark_TypeDef; - -#if defined(EUSART_PRESENT) -/// Clock polarity/phase mode. -typedef enum { - /// Clock idle low, sample on rising edge. - eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING, - - /// Clock idle low, sample on falling edge. - eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING, - - /// Clock idle high, sample on falling edge. - eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING, - - /// Clock idle high, sample on rising edge. - eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING -} EUSART_ClockMode_TypeDef; - -/// Chip select polarity. -typedef enum { - /// Chip select active low. - eusartCsActiveLow = EUSART_CFG2_CSINV_AL, - - /// Chip select active high. - eusartCsActiveHigh = EUSART_CFG2_CSINV_AH, -} EUSART_CsPolarity_TypeDef; - -#if defined(EUSART_DALICFG_DALIEN) -/// DALI TX databits (8-32). -typedef enum { - eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits. - eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits. - eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits. - eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. - eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits. - eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. - eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. - eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. - eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. - eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. - eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. - eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. - eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits. - eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. - eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. - eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. - eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. - eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. - eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. - eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. - eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. - eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. - eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits. - eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. - eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. -} EUSART_DaliTxDatabits_TypeDef; - -/// DALI RX databits (8-32). -typedef enum { - eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits. - eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits. - eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits. - eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. - eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits. - eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. - eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. - eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. - eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. - eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. - eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. - eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. - eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits. - eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. - eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. - eusartDaliRxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. - eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. - eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. - eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. - eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. - eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. - eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. - eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits. - eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. - eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. -} EUSART_DaliRxDatabits_TypeDef; -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ -/// Advanced initialization structure. -typedef struct { - /// Hardware flow control mode. - EUSART_HwFlowControl_TypeDef hwFlowControl; - - /// Enable the collision Detection feature. - /// Internal (setting loopbackEnable) or external loopback must be done to use this feature. - bool collisionDetectEnable; - - /// If true, data will be send with most significant bit first. - bool msbFirst; - - /// Enable inversion of RX and/or TX signals. - EUSART_InvertIO_TypeDef invertIO; - - /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. - bool dmaWakeUpOnRx; - - /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation. - bool dmaWakeUpOnTx; - - /// Enable DMA requests blocking while framing or parity errors. - bool dmaHaltOnError; - - /// Start frame that will enable RX operation. 0x00 Disable this feature. - uint8_t startFrame; - - /// Enable automatic tristating of transmistter output when there is nothing to transmit. - bool txAutoTristate; - - /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. - /// The configured RX GPIO signal won't be routed to the EUSART receiver. - bool prsRxEnable; - - /// PRS Channel used to transmit data from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsRxChannel; - - /// Enable Multiprocessor mode. Address and data filtering using the 9th bit. - bool multiProcessorEnable; - - /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise. - bool multiProcessorAddressBitHigh; - - /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed. - EUSART_AutoTxDelay_TypeDef autoTxDelay; - - /// Interrupt and status level of the Receive FIFO. - EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; - - /// Interrupt and status level of the Transmit FIFO. - EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; -} EUSART_AdvancedInit_TypeDef; - -/// Initialization structure. -typedef struct { - /// Specifies whether TX and/or RX will be enabled when initialization completes. - EUSART_Enable_TypeDef enable; - - /// EUSART reference clock assumed when configuring baud rate setup. Set - /// to 0 if using currently configured reference clock. - uint32_t refFreq; - - /// Desired baud rate. If set to 0, Auto Baud feature is enabled and - /// the EUSART will wait for (0x55) frame to detect the Baudrate. - uint32_t baudrate; - - /// Oversampling used. - EUSART_OVS_TypeDef oversampling; - - /// Number of data bits in frame. - EUSART_Databits_TypeDef databits; - - /// Parity mode to use. - EUSART_Parity_TypeDef parity; - - /// Number of stop bits to use. - EUSART_Stopbits_TypeDef stopbits; - - /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes. - EUSART_MajorityVote_TypeDef majorityVote; - - /// Enable Loop Back configuration. - EUSART_LoopbackEnable_TypeDef loopbackEnable; - - /// Advanced initialization structure pointer. It can be NULL. - EUSART_AdvancedInit_TypeDef *advancedSettings; -} EUSART_UartInit_TypeDef; - -/// IrDA Initialization structure. -typedef struct { - /// General EUSART initialization structure. - EUSART_UartInit_TypeDef init; - - /// Enable the IrDA low frequency mode. Only RX operation are enabled. - bool irDALowFrequencyEnable; - - /// Set to enable filter on IrDA demodulator. - EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable; - - /// Configure the pulse width generated by the IrDA modulator as a fraction - /// of the configured EUSART bit period. - EUSART_IrDAPulseWidth_Typedef irDAPulseWidth; -} EUSART_IrDAInit_TypeDef; - -/// PRS Trigger initialization structure. -typedef struct { - /// PRS to EUSART trigger mode. - EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable; - - /// PRS channel to be used to trigger auto transmission. - EUSART_PrsChannel_TypeDef prs_trigger_channel; -} EUSART_PrsTriggerInit_TypeDef; - -#if defined(EUSART_PRESENT) -/// SPI Advanced initialization structure. -typedef struct { - /// Chip select polarity - EUSART_CsPolarity_TypeDef csPolarity; - - /// Enable inversion of RX and/or TX signals. - EUSART_InvertIO_TypeDef invertIO; - - /// Enable automatic chip select. CS is managed by the peripheral. - bool autoCsEnable; - - /// If true, data will be send with most significant bit first. - bool msbFirst; - - /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoCsSetupTime; - - /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoCsHoldTime; - - /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoInterFrameTime; - - /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full. - /// Generates underflow interrupt if the TX FIFO is empty. - bool autoTxEnable; - - /// Default transmitted data when the TXFIFO is empty. - uint16_t defaultTxData; - - /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. - /// Only applicable to EM2 (low frequency) capable EUSART instances. - bool dmaWakeUpOnRx; - - /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. - /// The configured RX GPIO signal won't be routed to the EUSART receiver. - bool prsRxEnable; - - /// PRS Channel used to transmit data from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsRxChannel; - - /// Enable EUSART capability to use a PRS channel as an input SPI Clock. - /// Slave mode only. - bool prsClockEnable; - - /// PRS Channel used to transmit SCLK from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsClockChannel; - - /// Interrupt and status level of the Receive FIFO. - EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; - - /// Interrupt and status level of the Receive FIFO. - EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; - - /// Force load the first FIFO value. - bool forceLoad; - - /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error. - uint8_t setupWindow; -} EUSART_SpiAdvancedInit_TypeDef; - -/// SPI Initialization structure. -typedef struct { - /// Specifies whether TX and/or RX will be enabled when initialization completes. - EUSART_Enable_TypeDef enable; - - /// EUSART reference clock assumed when configuring baud rate setup. Set - /// to 0 if using currently configured reference clock. - uint32_t refFreq; - - /// Desired bit rate in Hz. - /// Depending on EUSART instance clock, not all bitrates - /// are achievable as the divider is limited to 255. - uint32_t bitRate; - - /// Number of data bits in frame. - EUSART_Databits_TypeDef databits; - - /// Select to operate in master or slave mode. - bool master; - - /// Clock polarity/phase mode. - EUSART_ClockMode_TypeDef clockMode; - - /// Enable Loop Back configuration. - EUSART_LoopbackEnable_TypeDef loopbackEnable; - - /// Advanced initialization structure pointer. It can be NULL. - EUSART_SpiAdvancedInit_TypeDef *advancedSettings; -} EUSART_SpiInit_TypeDef; -#endif /* EUSART_PRESENT */ - -/// DALI Initialization structure. -typedef struct { - /// General EUSART initialization structure. - EUSART_UartInit_TypeDef init; - - /// Enable the DALI low frequency mode. - bool daliLowFrequencyEnable; - -#if defined(EUSART_DALICFG_DALIEN) - /// Number of TX data bits in frame. - EUSART_DaliTxDatabits_TypeDef TXdatabits; - /// Number of RX data bits in frame. - EUSART_DaliRxDatabits_TypeDef RXdatabits; -#endif -} EUSART_DaliInit_TypeDef; - -/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock. -#define EUSART_UART_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 115200, /* 115200 bits/s. */ \ - eusartOVS16, /* Oversampling x16. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteEnable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default start frame configuration, i.e. feature disabled. -#define EUSART_DEFAULT_START_FRAME 0x00u - -/// Default configuration for EUSART advanced initialization structure. -#define EUSART_ADVANCED_INIT_DEFAULT \ - { \ - eusartHwFlowControlNone, /* Flow control disabled. */ \ - false, /* Collision detection disabled. */ \ - false, /* Data is sent with the least significant bit first. */ \ - eusartInvertIODisable, /* RX and TX signal active high. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* No DMA wake up on transmission. */ \ - false, /* Halt DMA on error disabled. */ \ - EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ - false, /* TX auto tristate disabled. */ \ - false, /* Do not use PRS signal as RX signal.*/ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ - false, /* Multiprocessor mode disabled. */ \ - false, /* Multiprocessor address bit : 0.*/ \ - eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - } - -/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock. -#define EUSART_UART_INIT_DEFAULT_LF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 9600, /* 9600 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock. -#define EUSART_IRDA_INIT_DEFAULT_HF \ - { \ - EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \ - false, /* Disable IrDA low frequency mode. */ \ - eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ - eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \ - } - -/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock. -#define EUSART_IRDA_INIT_DEFAULT_LF \ - { \ - { \ - eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 9600, /* 9600 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - }, \ - true, /* Enable IrDA low frequency mode. */ \ - eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ - eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \ - } - -#if defined(EUSART_PRESENT) -/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock. -#define EUSART_SPI_ADVANCED_INIT_DEFAULT \ - { \ - eusartCsActiveLow, /* CS active low. */ \ - eusartInvertIODisable, /* RX and TX signal active High. */ \ - true, /* AutoCS enabled. */ \ - false, /* Data is sent with the least significant bit first. */ \ - 0u, /* CS setup time is 0 baud cycles */ \ - 0u, /* CS hold time is 0 baud cycles */ \ - 0u, /* Inter-frame time is 0 baud cycles */ \ - false, /* AutoTX disabled. */ \ - 0x0000, /* Default transmitted data is 0. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* Do not use PRS signal as RX signal. */ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \ - false, /* Do not use PRS signal as SCLK signal. */ \ - (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - true, /* The first byte sent by the slave won't be the default value if a byte is made available \ - after chip select is asserted. */ \ - 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \ - } - -/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock. -#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 10000000, /* 10 Mbits/s. */ \ - eusartDataBits8, /* 8 data bits. */ \ - true, /* Master mode enabled. */ \ - eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock. -#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 10000000, /* 10 Mbits/s. */ \ - eusartDataBits8, /* 8 data bits. */ \ - false, /* Master mode enabled. */ \ - eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -#if defined(EUSART_DALICFG_DALIEN) -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -/// Default configuration for EUSART advanced initialization structure. -#define EUSART_ADVANCED_DALI_INIT_DEFAULT \ - { \ - eusartHwFlowControlNone, /* Flow control disabled. */ \ - false, /* Collision detection disabled. */ \ - true, /* Data is sent with the most significant bit first. */ \ - eusartInvertIODisable, /* RX and TX signal active high. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* No DMA wake up on transmission. */ \ - false, /* Halt DMA on error disabled. */ \ - EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ - false, /* TX auto tristate disabled. */ \ - false, /* Do not use PRS signal as RX signal.*/ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ - false, /* Multiprocessor mode disabled. */ \ - false, /* Multiprocessor address bit : 0.*/ \ - eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -#define EUSART_UART_DALI_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 1200, /* 1200 bits/s. */ \ - eusartOVS16, /* Oversampling x16. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteEnable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. -#define EUSART_UART_DALI_INIT_DEFAULT_LF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 1200, /* 1200 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -#define EUSART_DALI_INIT_DEFAULT_HF \ - { \ - EUSART_UART_DALI_INIT_DEFAULT_HF, \ - false, /* Disable DALI low frequency mode. */ \ - eusartDaliTxDataBits16, /* TX 16 data bits. */ \ - eusartDaliRxDataBits8, /* RX 8 data bits. */ \ - } \ - -/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. -#define EUSART_DALI_INIT_DEFAULT_LF \ - { \ - EUSART_UART_DALI_INIT_DEFAULT_LF, \ - true, /* Enable DALI low frequency mode. */ \ - eusartDaliTxDataBits16, /* TX 16 data bits. */ \ - eusartDaliRxDataBits8, /* RX 8 data bits. */ \ - } \ - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * Initialize EUSART when used in UART mode with the high frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); - -/***************************************************************************//** - * Initialize EUSART when used in UART mode with the low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); - -/***************************************************************************//** - * Initialize EUSART when used in IrDA mode with the high or low - * frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param irdaInit A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_IrDAInit(EUSART_TypeDef *eusart, - const EUSART_IrDAInit_TypeDef *irdaInit); - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initialize EUSART when used in SPI mode. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init); - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Initialize EUSART when used in DALI mode with the high or low - * frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param daliInit A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_DaliInit(EUSART_TypeDef *eusart, - const EUSART_DaliInit_TypeDef *daliInit); - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure EUSART to its reset state. - * - * @param eusart Pointer to the EUSART peripheral register block. - ******************************************************************************/ -void EUSART_Reset(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Enable/disable EUSART receiver and/or transmitter. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the status for the receiver and transmitter. - ******************************************************************************/ -void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable); - -/***************************************************************************//** - * Receive one 8 bit frame, (or part of 9 bit frame). - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one frame when operating with - * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. - * Notice that possible parity/stop bits are not considered a part of the - * specified frame bit length. - * @note This function will stall if buffer is empty until data is received. - * - * @return Data received. - ******************************************************************************/ -uint8_t EUSART_Rx(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Receive one 8-16 bit frame with extended information. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one frame and additional RX - * status information. - * @note This function will stall if buffer is empty until data is received. - * - * @return Data received and receive status. - ******************************************************************************/ -uint16_t EUSART_RxExt(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Transmit one frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Depending on the frame length configuration, 8 (least significant) bits - * from @p data are transmitted. If the frame length is 9, 8 bits are - * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame - * with full control of all 9 bits. - * @note This function will stall if the 4 frame FIFO is full, until the buffer - * becomes available. - ******************************************************************************/ -void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data); - -/***************************************************************************//** - * Transmit one 8-9 bit frame with extended control. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * @note This function will stall if buffer is full until the buffer becomes - * available. - ******************************************************************************/ -void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data); - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Transmit one 8-16 bit frame and return received data. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @return Data received and receive status. - * - * @note SPI master mode only. - * @note This function will stall if the TX buffer is full until the buffer becomes - * available. - ******************************************************************************/ -uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data); - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Transmit one DALI frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Depending on the TXdatabits configuration, N (least significant) bits - * from @p data are transmitted. - * @note This function will stall if the 16 frame FIFO is full, until the buffer - * becomes available. - ******************************************************************************/ -void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data); - -/***************************************************************************//** - * Receive one 8-32 bit DALI frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one DALI frame (RXdatabits). - * @note This function will stall if the 16 frame FIFO is empty until new - * data is received. - * - * @return Data received. Depending on the RXdatabits configuration, N - * (least significant) bits are returned. - ******************************************************************************/ -uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart); -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure the baudrate (or as close as possible to a specified baudrate). - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param refFreq The EUSART reference clock frequency in Hz that will be used. - * If set to 0, the currently configured peripheral clock is - * used. - * @param baudrate A baudrate to try to achieve. - ******************************************************************************/ -void EUSART_BaudrateSet(EUSART_TypeDef *eusart, - uint32_t refFreq, - uint32_t baudrate); - -/***************************************************************************//** - * Get the current baudrate. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return The current baudrate. - ******************************************************************************/ -uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Enable/Disable reception operation until the configured start frame is - * received. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the receiver blocking status. - ******************************************************************************/ -void EUSART_RxBlock(EUSART_TypeDef *eusart, - EUSART_BlockRx_TypeDef enable); - -/***************************************************************************//** - * Enable/Disable the tristating of the transmitter output. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the transmitter tristate status. - ******************************************************************************/ -void EUSART_TxTristateSet(EUSART_TypeDef *eusart, - EUSART_TristateTx_TypeDef enable); - -/***************************************************************************//** - * Initialize the automatic enabling of transmissions and/or reception using - * the PRS as a trigger. - * @note - * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before - * enabling the PRS trigger. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init Pointer to the initialization structure. - ******************************************************************************/ -void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, - const EUSART_PrsTriggerInit_TypeDef *init); - -/***************************************************************************//** - * Get EUSART STATUS register. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return STATUS register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart) -{ - return eusart->STATUS; -} - -/***************************************************************************//** - * Clear one or more pending EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IF_CLR = flags; -} - -/***************************************************************************//** - * Disable one or more EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IEN_CLR = flags; -} - -/***************************************************************************//** - * Enable one or more EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IEN_SET = flags; -} - -/***************************************************************************//** - * Get pending EUSART interrupt flags. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Pending EUSART interrupt sources. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart) -{ - return eusart->IF; -} - -/***************************************************************************//** - * Get enabled and pending EUSART interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Pending and enabled EUSART interrupt sources. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart) -{ - uint32_t tmp; - - /* Store EUSARTx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - tmp = eusart->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return eusart->IF & tmp; -} - -/***************************************************************************//** - * Set one or more pending EUSART interrupts from SW. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IF_SET = flags; -} - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup eusart) */ -#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ -#endif /* EM_EUSART_H */ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_H +#define EM_EUSART_H +#include "em_device.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "sl_enum.h" +#include "em_eusart_compat.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup eusart EUSART - Extended USART +/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter +/// +/// @li @ref eusart_intro +/// @li @ref eusart_example +/// @li @ref eusart_em2 +/// +///@n @section eusart_intro Introduction +/// This module contains functions to control the Enhanced Universal Synchronous +/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon +/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, +/// therefore, be connected to an external transceiver to communicate with +/// another host using the serial link. +/// +/// It supports full duplex asynchronous UART communication as well as RS-485, +/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, +/// and IrDA devices. +/// +/// EUSART has a wide selection of operating modes, frame formats, and baud rates. +/// All features are supported through the API of this module. +/// +/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers +/// provide full support for DMA and more. +/// +///@n @section eusart_example Example +/// +/// EUSART Async TX example: +/// @code{.c} +/// { +/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); +/// CMU_ClockEnable(cmuClock_EUSART0CLK, true); +/// // Initialize the EUSART +/// EUSART_UartInitHf(EUSART0, &init); +/// EUSART_Tx(EUSART0, data); +/// } +/// +/// @endcode +/// +/// EUSART Sync SPI Transaction example: +/// @code{.c} +/// { +/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); +/// CMU_ClockEnable(cmuClock_EUSART1, true); +/// CMU_ClockEnable(cmuClock_GPIO, true); +/// +/// //Configure the SPI ports +/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0); +/// +/// // Connect EUSART to ports +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT) +/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT) +/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) +/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN; +/// +/// // Initialize the EUSART +/// EUSART_SpiInit(EUSART1, &init_master); +/// EUSART_Spi_TxRx(EUSART1, data); +/// } +/// +/// @endcode +///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances +/// +/// @note EUSART instances located in the PD1 power domain are non EM2-capable. +/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used +/// to determine whether or not a EUSART instance is EM2-Capable. +/// +/// Follow theses steps when entering in EM2: +/// -# Wait for the current transaction to complete with TXCIF interrupt +/// -# Disable TX and RX using TXDIS and RXDIS cmd +/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low +/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low +/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled +/// -# Enter EM2 +/// +/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO +/// (SCLKPEN and CSPEN) must be re-enabled. For example: +/// +/// @code{.c} +/// { +/// // Enable TX and RX +/// EUSART_Enable(EUSART0, eusartEnable); +/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN, +/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, +/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); +/// } +/// @endcode +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Define EUSART FIFO Depth information */ +#if !defined(EUSART_FIFO_DEPTH) +#if defined(EUART_PRESENT) +#define EUSART0_FIFO_DEPTH 4 +#elif defined(EUSART_PRESENT) +#define EUSART0_FIFO_DEPTH 16 +#endif /* EUART_PRESENT */ +#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH + +#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \ + : ((n) == 1) ? EUSART1_FIFO_DEPTH \ + : ((n) == 2) ? EUSART2_FIFO_DEPTH \ + : ((n) == 3) ? EUSART3_FIFO_DEPTH \ + : ((n) == 4) ? EUSART4_FIFO_DEPTH \ + : 0x0UL) +#endif /* EUSART_FIFO_DEPTH */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Enable selection. +typedef enum { + /// Disable the peripheral. + eusartDisable = 0x0, + + /// Enable receiver only, transmitter disabled. + eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS), + + /// Enable transmitter only, receiver disabled. + eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS), + + /// Enable both receiver and transmitter. + eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN) +} EUSART_Enable_TypeDef; + +/// Data bit selection. +typedef enum { + eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits. + eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits. + eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits. +#if defined(EUSART_PRESENT) + eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only. + eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only. + eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only. + eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only. + eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only. + eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only. + eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only. +#endif +} EUSART_Databits_TypeDef; + +/// Parity selection. +typedef enum { + eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity. + eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity. + eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity. +} EUSART_Parity_TypeDef; + +/// Stop bits selection. +typedef enum { + eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits. + eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits. + eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits. + eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits. +} EUSART_Stopbits_TypeDef; + +/// Oversampling selection, used for asynchronous operation. +typedef enum { + eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal). + eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling. + eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling. + eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling. + eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled. +} EUSART_OVS_TypeDef; + +/// HW flow control config. +typedef enum { + eusartHwFlowControlNone = 0, ///< No HW Flow Control. + eusartHwFlowControlCts, ///< CTS HW Flow Control. + eusartHwFlowControlRts, ///< RTS HW Flow Control. + eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control. +} EUSART_HwFlowControl_TypeDef; + +/// Loopback enable. +typedef enum { + eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback. + eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback. +} EUSART_LoopbackEnable_TypeDef; + +/// Majority vote enable. +typedef enum { + eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes. + eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes. +} EUSART_MajorityVote_TypeDef; + +/// Block reception enable. +typedef enum { + eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded. + eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO. +} EUSART_BlockRx_TypeDef; + +/// TX output tristate enable. +typedef enum { + eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output. + eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output. +} EUSART_TristateTx_TypeDef; + +/// IrDA filter enable. +typedef enum { + eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator. + eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator. +} EUSART_IrDARxFilterEnable_TypeDef; + +/// Pulse width selection for IrDA mode. +typedef enum { + /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8 + eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE, + + /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8 + eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO, + + /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8 + eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE, + + /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8 + eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR +} EUSART_IrDAPulseWidth_Typedef; + +/// PRS trigger enable. +typedef enum { + /// Disable trigger on both receiver and transmitter. + eusartPrsTriggerDisable = 0x0, + + /// Enable receive trigger only, transmit disabled. + eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN, + + /// Enable transmit trigger only, receive disabled. + eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN, + + /// Enable trigger on both receive and transmit. + eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN) +} EUSART_PrsTriggerEnable_TypeDef; + +/// PRS Channel type. +typedef uint8_t EUSART_PrsChannel_TypeDef; + +/// IO polarity selection. +typedef enum { + /// Disable inversion on both RX and TX signals. + eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE), + + /// Invert RX signal, before receiver. + eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE, + + /// Invert TX signal, after transmitter. + eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE, + + /// Enable trigger on both receive and transmit. + eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) +} EUSART_InvertIO_TypeDef; + +/// Auto TX delay transmission. +SL_ENUM(EUSART_AutoTxDelay_TypeDef) { + /// Frames are transmitted immediately. + eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE, + + /// Transmission of new frames is delayed by a single bit period. + eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE, + + /// Transmission of new frames is delayed by a two bit periods. + eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE, + + /// Transmission of new frames is delayed by a three bit periods. + eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE +}; + +/// RX FIFO Interrupt ans Status Watermark. +typedef enum { + eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME, + eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES, + eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES, + eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES, + eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES, + eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES, + eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES, + eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES, + eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES, + eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES, + eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES, + eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES, + eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES, + eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES, + eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES +#endif +} EUSART_RxFifoWatermark_TypeDef; + +/// TX FIFO Interrupt and Status Watermark. +typedef enum { + eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME, + eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES, + eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES, + eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES, + eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES, + eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES, + eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES, + eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES, + eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES, + eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES, + eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES, + eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES, + eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES, + eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES, + eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES +#endif +} EUSART_TxFifoWatermark_TypeDef; + +#if defined(EUSART_PRESENT) +/// Clock polarity/phase mode. +typedef enum { + /// Clock idle low, sample on rising edge. + eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle low, sample on falling edge. + eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING, + + /// Clock idle high, sample on falling edge. + eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle high, sample on rising edge. + eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING +} EUSART_ClockMode_TypeDef; + +/// Chip select polarity. +typedef enum { + /// Chip select active low. + eusartCsActiveLow = EUSART_CFG2_CSINV_AL, + + /// Chip select active high. + eusartCsActiveHigh = EUSART_CFG2_CSINV_AH, +} EUSART_CsPolarity_TypeDef; + +#if defined(EUSART_DALICFG_DALIEN) +/// DALI TX databits (8-32). +typedef enum { + eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliTxDatabits_TypeDef; + +/// DALI RX databits (8-32). +typedef enum { + eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliRxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliRxDatabits_TypeDef; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ +/// Advanced initialization structure. +typedef struct { + /// Hardware flow control mode. + EUSART_HwFlowControl_TypeDef hwFlowControl; + + /// Enable the collision Detection feature. + /// Internal (setting loopbackEnable) or external loopback must be done to use this feature. + bool collisionDetectEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + bool dmaWakeUpOnRx; + + /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation. + bool dmaWakeUpOnTx; + + /// Enable DMA requests blocking while framing or parity errors. + bool dmaHaltOnError; + + /// Start frame that will enable RX operation. 0x00 Disable this feature. + uint8_t startFrame; + + /// Enable automatic tristating of transmistter output when there is nothing to transmit. + bool txAutoTristate; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable Multiprocessor mode. Address and data filtering using the 9th bit. + bool multiProcessorEnable; + + /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise. + bool multiProcessorAddressBitHigh; + + /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed. + EUSART_AutoTxDelay_TypeDef autoTxDelay; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Transmit FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; +} EUSART_AdvancedInit_TypeDef; + +/// Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired baud rate. If set to 0, Auto Baud feature is enabled and + /// the EUSART will wait for (0x55) frame to detect the Baudrate. + uint32_t baudrate; + + /// Oversampling used. + EUSART_OVS_TypeDef oversampling; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Parity mode to use. + EUSART_Parity_TypeDef parity; + + /// Number of stop bits to use. + EUSART_Stopbits_TypeDef stopbits; + + /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes. + EUSART_MajorityVote_TypeDef majorityVote; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_AdvancedInit_TypeDef *advancedSettings; +} EUSART_UartInit_TypeDef; + +/// IrDA Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the IrDA low frequency mode. Only RX operation are enabled. + bool irDALowFrequencyEnable; + + /// Set to enable filter on IrDA demodulator. + EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable; + + /// Configure the pulse width generated by the IrDA modulator as a fraction + /// of the configured EUSART bit period. + EUSART_IrDAPulseWidth_Typedef irDAPulseWidth; +} EUSART_IrDAInit_TypeDef; + +/// PRS Trigger initialization structure. +typedef struct { + /// PRS to EUSART trigger mode. + EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable; + + /// PRS channel to be used to trigger auto transmission. + EUSART_PrsChannel_TypeDef prs_trigger_channel; +} EUSART_PrsTriggerInit_TypeDef; + +#if defined(EUSART_PRESENT) +/// SPI Advanced initialization structure. +typedef struct { + /// Chip select polarity + EUSART_CsPolarity_TypeDef csPolarity; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable automatic chip select. CS is managed by the peripheral. + bool autoCsEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsSetupTime; + + /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsHoldTime; + + /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoInterFrameTime; + + /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full. + /// Generates underflow interrupt if the TX FIFO is empty. + bool autoTxEnable; + + /// Default transmitted data when the TXFIFO is empty. + uint16_t defaultTxData; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + /// Only applicable to EM2 (low frequency) capable EUSART instances. + bool dmaWakeUpOnRx; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable EUSART capability to use a PRS channel as an input SPI Clock. + /// Slave mode only. + bool prsClockEnable; + + /// PRS Channel used to transmit SCLK from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsClockChannel; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Receive FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; + + /// Force load the first FIFO value. + bool forceLoad; + + /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error. + uint8_t setupWindow; +} EUSART_SpiAdvancedInit_TypeDef; + +/// SPI Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired bit rate in Hz. + /// Depending on EUSART instance clock, not all bitrates + /// are achievable as the divider is limited to 255. + uint32_t bitRate; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Select to operate in master or slave mode. + bool master; + + /// Clock polarity/phase mode. + EUSART_ClockMode_TypeDef clockMode; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_SpiAdvancedInit_TypeDef *advancedSettings; +} EUSART_SpiInit_TypeDef; +#endif /* EUSART_PRESENT */ + +/// DALI Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the DALI low frequency mode. + bool daliLowFrequencyEnable; + +#if defined(EUSART_DALICFG_DALIEN) + /// Number of TX data bits in frame. + EUSART_DaliTxDatabits_TypeDef TXdatabits; + /// Number of RX data bits in frame. + EUSART_DaliRxDatabits_TypeDef RXdatabits; +#endif +} EUSART_DaliInit_TypeDef; + +/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock. +#define EUSART_UART_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 115200, /* 115200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default start frame configuration, i.e. feature disabled. +#define EUSART_DEFAULT_START_FRAME 0x00u + +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock. +#define EUSART_UART_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_HF \ + { \ + EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \ + false, /* Disable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_LF \ + { \ + { \ + eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + }, \ + true, /* Enable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \ + } + +#if defined(EUSART_PRESENT) +/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock. +#define EUSART_SPI_ADVANCED_INIT_DEFAULT \ + { \ + eusartCsActiveLow, /* CS active low. */ \ + eusartInvertIODisable, /* RX and TX signal active High. */ \ + true, /* AutoCS enabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + 0u, /* CS setup time is 0 baud cycles */ \ + 0u, /* CS hold time is 0 baud cycles */ \ + 0u, /* Inter-frame time is 0 baud cycles */ \ + false, /* AutoTX disabled. */ \ + 0x0000, /* Default transmitted data is 0. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* Do not use PRS signal as RX signal. */ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \ + false, /* Do not use PRS signal as SCLK signal. */ \ + (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + true, /* The first byte sent by the slave won't be the default value if a byte is made available \ + after chip select is asserted. */ \ + 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock. +#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + true, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock. +#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + false, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +#if defined(EUSART_DALICFG_DALIEN) +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_DALI_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + true, /* Data is sent with the most significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_HF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_HF, \ + false, /* Disable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_LF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_LF, \ + true, /* Enable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the high frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in IrDA mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param irdaInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initialize EUSART when used in SPI mode. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initialize EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param daliInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit); + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure EUSART to its reset state. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/disable EUSART receiver and/or transmitter. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the status for the receiver and transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable); + +/***************************************************************************//** + * Receive one 8 bit frame, (or part of 9 bit frame). + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame when operating with + * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. + * Notice that possible parity/stop bits are not considered a part of the + * specified frame bit length. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received. + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Receive one 8-16 bit frame with extended information. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame and additional RX + * status information. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received and receive status. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Transmit one frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the frame length configuration, 8 (least significant) bits + * from @p data are transmitted. If the frame length is 9, 8 bits are + * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame + * with full control of all 9 bits. + * @note This function will stall if the 4 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data); + +/***************************************************************************//** + * Transmit one 8-9 bit frame with extended control. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * @note This function will stall if buffer is full until the buffer becomes + * available. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmit one 8-16 bit frame and return received data. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @return Data received and receive status. + * + * @note SPI master mode only. + * @note This function will stall if the TX buffer is full until the buffer becomes + * available. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmit one DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the TXdatabits configuration, N (least significant) bits + * from @p data are transmitted. + * @note This function will stall if the 16 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data); + +/***************************************************************************//** + * Receive one 8-32 bit DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one DALI frame (RXdatabits). + * @note This function will stall if the 16 frame FIFO is empty until new + * data is received. + * + * @return Data received. Depending on the RXdatabits configuration, N + * (least significant) bits are returned. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart); +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the baudrate (or as close as possible to a specified baudrate). + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * If set to 0, the currently configured peripheral clock is + * used. + * @param baudrate A baudrate to try to achieve. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate); + +/***************************************************************************//** + * Get the current baudrate. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return The current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/Disable reception operation until the configured start frame is + * received. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the receiver blocking status. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, + EUSART_BlockRx_TypeDef enable); + +/***************************************************************************//** + * Enable/Disable the tristating of the transmitter output. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the transmitter tristate status. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable); + +/***************************************************************************//** + * Initialize the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + * @note + * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before + * enabling the PRS trigger. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init Pointer to the initialization structure. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * Get EUSART STATUS register. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart) +{ + return eusart->STATUS; +} + +/***************************************************************************//** + * Clear one or more pending EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_CLR = flags; +} + +/***************************************************************************//** + * Disable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_CLR = flags; +} + +/***************************************************************************//** + * Enable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_SET = flags; +} + +/***************************************************************************//** + * Get pending EUSART interrupt flags. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart) +{ + return eusart->IF; +} + +/***************************************************************************//** + * Get enabled and pending EUSART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending and enabled EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart) +{ + uint32_t tmp; + + /* Store EUSARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = eusart->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return eusart->IF & tmp; +} + +/***************************************************************************//** + * Set one or more pending EUSART interrupts from SW. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_SET = flags; +} + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup eusart) */ +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ +#endif /* EM_EUSART_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h index 50822e2..96ac200 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h @@ -1,218 +1,218 @@ -/***************************************************************************//** - * @file - * @brief EUSART Compatibility Header - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EUSART_COMPAT_H -#define EM_EUSART_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define EUSART_IF_TXCIF EUSART_IF_TXC -#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT -#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK -#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT -#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT - -#define EUSART_IF_TXFLIF EUSART_IF_TXFL -#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT -#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK -#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT -#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT - -#define EUSART_IF_RXFLIF EUSART_IF_RXFL -#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT -#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK -#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT -#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT - -#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL -#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT -#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK -#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT -#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT - -#define EUSART_IF_RXOFIF EUSART_IF_RXOF -#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT -#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK -#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT -#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT - -#define EUSART_IF_RXUFIF EUSART_IF_RXUF -#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT -#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK -#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT -#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT - -#define EUSART_IF_TXOFIF EUSART_IF_TXOF -#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT -#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK -#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT -#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT - -#define EUSART_IF_PERRIF EUSART_IF_PERR -#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT -#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK -#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT -#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT - -#define EUSART_IF_FERRIF EUSART_IF_FERR -#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT -#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK -#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT -#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT - -#define EUSART_IF_MPAFIF EUSART_IF_MPAF -#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT -#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK -#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT -#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT - -#define EUSART_IF_CCFIF EUSART_IF_CCF -#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT -#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK -#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT -#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT - -#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE -#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT -#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK -#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT -#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT - -#define EUSART_IF_STARTFIF EUSART_IF_STARTF -#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT -#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK -#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT -#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT - -#define EUSART_IF_SIGFIF EUSART_IF_SIGF -#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT -#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK -#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT -#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT - -#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE -#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT -#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK -#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT -#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT - -#define EUSART_IEN_TXCIEN EUSART_IEN_TXC -#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT -#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK -#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT -#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT - -#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL -#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT -#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK -#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT -#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT - -#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL -#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT -#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK -#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT -#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT - -#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL -#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT -#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK -#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT -#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT - -#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF -#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT -#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK -#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT -#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT - -#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF -#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT -#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK -#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT -#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT - -#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF -#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT -#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK -#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT -#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT - -#define EUSART_IEN_PERRIEN EUSART_IEN_PERR -#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT -#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK -#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT -#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT - -#define EUSART_IEN_FERRIEN EUSART_IEN_FERR -#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT -#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK -#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT -#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT - -#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF -#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT -#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK -#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT -#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT - -#define EUSART_IEN_CCFIEN EUSART_IEN_CCF -#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT -#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK -#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT -#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT - -#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE -#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT -#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK -#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT -#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT - -#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF -#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT -#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK -#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT -#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT - -#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF -#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT -#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK -#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT -#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT - -#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE -#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT -#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK -#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT -#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT - -#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2 - -#endif +/***************************************************************************//** + * @file + * @brief EUSART Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_COMPAT_H +#define EM_EUSART_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define EUSART_IF_TXCIF EUSART_IF_TXC +#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT +#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK +#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT +#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT + +#define EUSART_IF_TXFLIF EUSART_IF_TXFL +#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT +#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK +#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT +#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT + +#define EUSART_IF_RXFLIF EUSART_IF_RXFL +#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT +#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK +#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT +#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT + +#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL +#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT +#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK +#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT +#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT + +#define EUSART_IF_RXOFIF EUSART_IF_RXOF +#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT +#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK +#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT +#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT + +#define EUSART_IF_RXUFIF EUSART_IF_RXUF +#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT +#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK +#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT +#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT + +#define EUSART_IF_TXOFIF EUSART_IF_TXOF +#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT +#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK +#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT +#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT + +#define EUSART_IF_PERRIF EUSART_IF_PERR +#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT +#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK +#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT +#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT + +#define EUSART_IF_FERRIF EUSART_IF_FERR +#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT +#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK +#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT +#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT + +#define EUSART_IF_MPAFIF EUSART_IF_MPAF +#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT +#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK +#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT +#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT + +#define EUSART_IF_CCFIF EUSART_IF_CCF +#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT +#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK +#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT +#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT + +#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE +#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT +#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK +#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT +#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT + +#define EUSART_IF_STARTFIF EUSART_IF_STARTF +#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT +#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK +#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT +#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT + +#define EUSART_IF_SIGFIF EUSART_IF_SIGF +#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT +#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK +#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT +#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT + +#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE +#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT +#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK +#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT +#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT + +#define EUSART_IEN_TXCIEN EUSART_IEN_TXC +#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT +#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK +#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT +#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT + +#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL +#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT +#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK +#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT +#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT + +#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL +#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT +#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK +#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT +#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT + +#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL +#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT +#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK +#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT +#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT + +#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF +#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT +#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK +#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT +#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT + +#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF +#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT +#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK +#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT +#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT + +#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF +#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT +#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK +#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT +#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT + +#define EUSART_IEN_PERRIEN EUSART_IEN_PERR +#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT +#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK +#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT +#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT + +#define EUSART_IEN_FERRIEN EUSART_IEN_FERR +#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT +#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK +#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT +#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT + +#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF +#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT +#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK +#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT +#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT + +#define EUSART_IEN_CCFIEN EUSART_IEN_CCF +#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT +#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK +#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT +#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT + +#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE +#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT +#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK +#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT +#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT + +#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF +#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT +#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK +#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT +#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT + +#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF +#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT +#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK +#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT +#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT + +#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE +#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT +#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK +#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT +#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT + +#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2 + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h index 64f7d19..d20c9e2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h @@ -1,346 +1,346 @@ -/***************************************************************************//** - * @file - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_GPCRC_H -#define EM_GPCRC_H - -#include "em_bus.h" -#include "em_device.h" -#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup gpcrc GPCRC - General Purpose CRC - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API - * - * @details - * The GPCRC API functions provide full support for the GPCRC peripheral. - * - * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check - * (CRC) function. It supports a fixed 32-bit polynomial and a user - * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly - * used IEEE 802.3 polynomial 0x04C11DB7. - * - * When using a 16-bit polynomial it is up to the user to choose a polynomial - * that fits the application. Commonly used 16-bit polynomials are 0x1021 - * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). - * See this link for other polynomials: - * https://en.wikipedia.org/wiki/Cyclic_redundancy_check - * - * Before a CRC calculation can begin, call the - * @ref GPCRC_Start function. This function will reset CRC calculation - * by copying the configured initialization value over to the CRC data register. - * - * There are two ways of sending input data to the GPCRC. Either write - * the input data into the input data register using input functions - * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the - * user can configure @ref ldma to transfer data directly to one of the GPCRC - * input data registers. - * - * Examples of GPCRC usage: - * - * A CRC-32 Calculation: - * - * @include em_gpcrc_crc32.c - * - * A CRC-16 Calculation: - * - * @include em_gpcrc_crc16.c - * - * A CRC-CCITT calculation: - * - * @include em_gpcrc_ccit.c - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** CRC initialization structure. */ -typedef struct { - /** - * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial - * or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial - * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the - * 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field. - * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 - * bits are zero. - * - * The polynomial should be written in normal bit order. For instance, - * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert - * it to hex representation and remove the highest order term - * of the polynomial. This will give 0x8005 as the value to write into - * crcPoly. - */ - uint32_t crcPoly; - - /** - * CRC initialization value. This value is assigned to the GPCRC_INIT register. - * The initValue is loaded into the data register when calling the - * @ref GPCRC_Start function or when one of the data registers are read - * while @ref autoInit is enabled. - */ - uint32_t initValue; - - /** - * Reverse byte order. This has an effect when sending a 32-bit word or - * 16-bit half word input to the CRC calculation. When set to true, the input - * bytes are reversed before entering the CRC calculation. When set to - * false, the input bytes stay in the same order. - */ - bool reverseByteOrder; - - /** - * Reverse bits within each input byte. This setting enables or disables byte - * level bit reversal. When byte-level bit reversal is enabled, then each byte - * of input data will be reversed before entering CRC calculation. - */ - bool reverseBits; - - /** - * Enable/disable byte mode. When byte mode is enabled, then all input - * is treated as single byte input even though the input is a 32-bit word - * or a 16-bit half word. Only the least significant byte of the data-word - * will be used for CRC calculation for all writes. - */ - bool enableByteMode; - - /** - * Enable automatic initialization by re-seeding the CRC result based on - * the init value after reading one of the CRC data registers. - */ - bool autoInit; - - /** Enable/disable GPCRC when initialization is completed. */ - bool enable; -} GPCRC_Init_TypeDef; - -/** Default configuration for GPCRC_Init_TypeDef structure. */ -#define GPCRC_INIT_DEFAULT \ - { \ - 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ - 0x00000000UL, /* Initialization value. */ \ - false, /* Byte order is normal. */ \ - false, /* Bit order is not reversed on output. */ \ - false, /* Disable byte mode. */ \ - false, /* Disable automatic initialization on data read. */ \ - true, /* Enable GPCRC. */ \ - } - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ - -void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); -void GPCRC_Reset(GPCRC_TypeDef * gpcrc); - -/***************************************************************************//** - * @brief - * Enable/disable GPCRC. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] enable - * True to enable GPCRC, false to disable. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) -{ -#if defined(GPCRC_EN_EN) - BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); -#else - BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); -#endif -} - -/***************************************************************************//** - * @brief - * Issue a command to initialize the CRC calculation. - * - * @details - * Issues the command INIT in GPCRC_CMD that initializes the - * CRC calculation by writing the initial values to the DATA register. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) -{ - gpcrc->CMD = GPCRC_CMD_INIT; -} - -/***************************************************************************//** - * @brief - * Set the initialization value of the CRC. - * - * @param [in] initValue - * Value to use to initialize a CRC calculation. This value is moved into - * the data register when calling @ref GPCRC_Start - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) -{ - gpcrc->INIT = initValue; -} - -/***************************************************************************//** - * @brief - * Write a 32-bit value to the input data register of the CRC. - * - * @details - * Use this function to write a 32-bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) -{ - gpcrc->INPUTDATA = data; -} - -/***************************************************************************//** - * @brief - * Write a 16-bit value to the input data register of the CRC. - * - * @details - * Use this function to write a 16 bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) -{ - gpcrc->INPUTDATAHWORD = data; -} - -/***************************************************************************//** - * @brief - * Write an 8-bit value to the CRC input data register. - * - * @details - * Use this function to write an 8-bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) -{ - gpcrc->INPUTDATABYTE = data; -} - -/***************************************************************************//** - * @brief - * Read the CRC data register. - * - * @details - * Use this function to read the calculated CRC value. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATA; -} - -/***************************************************************************//** - * @brief - * Read the data register of the CRC bit reversed. - * - * @details - * Use this function to read the calculated CRC value bit reversed. When - * using a 32-bit polynomial, bits [31:0] are reversed, when using a - * 16-bit polynomial, bits [15:0] are reversed. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register bit reversed. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATAREV; -} - -/***************************************************************************//** - * @brief - * Read the data register of the CRC byte reversed. - * - * @details - * Use this function to read the calculated CRC value byte reversed. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register byte reversed. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATABYTEREV; -} - -/** @} (end addtogroup gpcrc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ -#endif /* EM_GPCRC_H */ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPCRC_H +#define EM_GPCRC_H + +#include "em_bus.h" +#include "em_device.h" +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup gpcrc GPCRC - General Purpose CRC + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API + * + * @details + * The GPCRC API functions provide full support for the GPCRC peripheral. + * + * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check + * (CRC) function. It supports a fixed 32-bit polynomial and a user + * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly + * used IEEE 802.3 polynomial 0x04C11DB7. + * + * When using a 16-bit polynomial it is up to the user to choose a polynomial + * that fits the application. Commonly used 16-bit polynomials are 0x1021 + * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). + * See this link for other polynomials: + * https://en.wikipedia.org/wiki/Cyclic_redundancy_check + * + * Before a CRC calculation can begin, call the + * @ref GPCRC_Start function. This function will reset CRC calculation + * by copying the configured initialization value over to the CRC data register. + * + * There are two ways of sending input data to the GPCRC. Either write + * the input data into the input data register using input functions + * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the + * user can configure @ref ldma to transfer data directly to one of the GPCRC + * input data registers. + * + * Examples of GPCRC usage: + * + * A CRC-32 Calculation: + * + * @include em_gpcrc_crc32.c + * + * A CRC-16 Calculation: + * + * @include em_gpcrc_crc16.c + * + * A CRC-CCITT calculation: + * + * @include em_gpcrc_ccit.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CRC initialization structure. */ +typedef struct { + /** + * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial + * or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial + * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the + * 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field. + * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 + * bits are zero. + * + * The polynomial should be written in normal bit order. For instance, + * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert + * it to hex representation and remove the highest order term + * of the polynomial. This will give 0x8005 as the value to write into + * crcPoly. + */ + uint32_t crcPoly; + + /** + * CRC initialization value. This value is assigned to the GPCRC_INIT register. + * The initValue is loaded into the data register when calling the + * @ref GPCRC_Start function or when one of the data registers are read + * while @ref autoInit is enabled. + */ + uint32_t initValue; + + /** + * Reverse byte order. This has an effect when sending a 32-bit word or + * 16-bit half word input to the CRC calculation. When set to true, the input + * bytes are reversed before entering the CRC calculation. When set to + * false, the input bytes stay in the same order. + */ + bool reverseByteOrder; + + /** + * Reverse bits within each input byte. This setting enables or disables byte + * level bit reversal. When byte-level bit reversal is enabled, then each byte + * of input data will be reversed before entering CRC calculation. + */ + bool reverseBits; + + /** + * Enable/disable byte mode. When byte mode is enabled, then all input + * is treated as single byte input even though the input is a 32-bit word + * or a 16-bit half word. Only the least significant byte of the data-word + * will be used for CRC calculation for all writes. + */ + bool enableByteMode; + + /** + * Enable automatic initialization by re-seeding the CRC result based on + * the init value after reading one of the CRC data registers. + */ + bool autoInit; + + /** Enable/disable GPCRC when initialization is completed. */ + bool enable; +} GPCRC_Init_TypeDef; + +/** Default configuration for GPCRC_Init_TypeDef structure. */ +#define GPCRC_INIT_DEFAULT \ + { \ + 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ + 0x00000000UL, /* Initialization value. */ \ + false, /* Byte order is normal. */ \ + false, /* Bit order is not reversed on output. */ \ + false, /* Disable byte mode. */ \ + false, /* Disable automatic initialization on data read. */ \ + true, /* Enable GPCRC. */ \ + } + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ + +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); +void GPCRC_Reset(GPCRC_TypeDef * gpcrc); + +/***************************************************************************//** + * @brief + * Enable/disable GPCRC. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] enable + * True to enable GPCRC, false to disable. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) +{ +#if defined(GPCRC_EN_EN) + BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Issue a command to initialize the CRC calculation. + * + * @details + * Issues the command INIT in GPCRC_CMD that initializes the + * CRC calculation by writing the initial values to the DATA register. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CMD = GPCRC_CMD_INIT; +} + +/***************************************************************************//** + * @brief + * Set the initialization value of the CRC. + * + * @param [in] initValue + * Value to use to initialize a CRC calculation. This value is moved into + * the data register when calling @ref GPCRC_Start + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) +{ + gpcrc->INIT = initValue; +} + +/***************************************************************************//** + * @brief + * Write a 32-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 32-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) +{ + gpcrc->INPUTDATA = data; +} + +/***************************************************************************//** + * @brief + * Write a 16-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 16 bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) +{ + gpcrc->INPUTDATAHWORD = data; +} + +/***************************************************************************//** + * @brief + * Write an 8-bit value to the CRC input data register. + * + * @details + * Use this function to write an 8-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) +{ + gpcrc->INPUTDATABYTE = data; +} + +/***************************************************************************//** + * @brief + * Read the CRC data register. + * + * @details + * Use this function to read the calculated CRC value. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATA; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC bit reversed. + * + * @details + * Use this function to read the calculated CRC value bit reversed. When + * using a 32-bit polynomial, bits [31:0] are reversed, when using a + * 16-bit polynomial, bits [15:0] are reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register bit reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATAREV; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC byte reversed. + * + * @details + * Use this function to read the calculated CRC value byte reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register byte reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATABYTEREV; +} + +/** @} (end addtogroup gpcrc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ +#endif /* EM_GPCRC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h index db31760..50e980c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h @@ -1,1295 +1,1295 @@ -/***************************************************************************//** - * @file - * @brief General Purpose IO (GPIO) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_GPIO_H -#define EM_GPIO_H - -#include "em_device.h" -#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "sl_common.h" -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 14 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 9 -#define _GPIO_PORT_E_PIN_COUNT 12 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xF77FUL -#define _GPIO_PORT_B_PIN_MASK 0x79F8UL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0x01FFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_EFM32_HAPPY_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 12 -#define _GPIO_PORT_D_PIN_COUNT 4 -#define _GPIO_PORT_E_PIN_COUNT 4 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x0707UL -#define _GPIO_PORT_B_PIN_MASK 0x6980UL -#define _GPIO_PORT_C_PIN_MASK 0xEF1FUL -#define _GPIO_PORT_D_PIN_MASK 0x00F0UL -#define _GPIO_PORT_E_PIN_MASK 0x3C00UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 13 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x1FFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_EFM32_GECKO_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 10 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x03FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - -#define _GPIO_PORT_A_PIN_COUNT 10 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 12 -#define _GPIO_PORT_D_PIN_COUNT 8 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 16 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 4 -#define _GPIO_PORT_J_PIN_COUNT 2 -#define _GPIO_PORT_K_PIN_COUNT 3 - -#define _GPIO_PORT_A_PIN_MASK 0x03FFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFC0UL -#define _GPIO_PORT_C_PIN_MASK 0x0FFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFF00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x000FUL -#define _GPIO_PORT_J_PIN_MASK 0xC000UL -#define _GPIO_PORT_K_PIN_MASK 0x0007UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 15 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x7FFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 16 -#define _GPIO_PORT_G_PIN_COUNT 16 -#define _GPIO_PORT_H_PIN_COUNT 16 -#define _GPIO_PORT_I_PIN_COUNT 16 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_G_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_H_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_I_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - -#define _GPIO_PORT_A_PIN_COUNT 14 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 9 -#define _GPIO_PORT_E_PIN_COUNT 12 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xF77FUL -#define _GPIO_PORT_B_PIN_MASK 0x79F8UL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0x01FFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined (_SILICON_LABS_32B_SERIES_2) - -#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT -#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT -#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT -#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 0 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) -#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) -#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) -#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x0000UL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#else -#warning "Port and pin masks are not defined for this family." -#endif - -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ - : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ - : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ - : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ - : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ - : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ - : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ - : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ - : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ - : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ - : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ - : 0) - -#define _GPIO_PORT_MASK(port) ( \ - ((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ - : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ - : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ - : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ - : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ - : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ - : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ - : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ - : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ - : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ - : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ - : 0UL) - -/** Validation of port and pin. */ -#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) -#define GPIO_PORT_PIN_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) - -#if defined(_GPIO_EXTIPINSELL_MASK) -/** Validation of interrupt number and pin. */ -#define GPIO_INTNO_PIN_VALID(intNo, pin) \ - (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ - == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) -#endif - -/** Highest GPIO pin number. */ -#define GPIO_PIN_MAX 15 - -/** Highest GPIO port number. */ -#if (_GPIO_PORT_K_PIN_COUNT > 0) -#define GPIO_PORT_MAX 10 -#elif (_GPIO_PORT_J_PIN_COUNT > 0) -#define GPIO_PORT_MAX 9 -#elif (_GPIO_PORT_I_PIN_COUNT > 0) -#define GPIO_PORT_MAX 8 -#elif (_GPIO_PORT_H_PIN_COUNT > 0) -#define GPIO_PORT_MAX 7 -#elif (_GPIO_PORT_G_PIN_COUNT > 0) -#define GPIO_PORT_MAX 6 -#elif (_GPIO_PORT_F_PIN_COUNT > 0) -#define GPIO_PORT_MAX 5 -#elif (_GPIO_PORT_E_PIN_COUNT > 0) -#define GPIO_PORT_MAX 4 -#elif (_GPIO_PORT_D_PIN_COUNT > 0) -#define GPIO_PORT_MAX 3 -#else -#error "Max GPIO port number is undefined for this part." -#endif - -/** Highest EXT GPIO interrupt number. */ -#define GPIO_EXTINTNO_MAX 15 - -/***************************************************************************//** - * @addtogroup gpio - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** GPIO ports IDs. */ -SL_ENUM(GPIO_Port_TypeDef) { -#if (_GPIO_PORT_A_PIN_COUNT > 0) - /** Port A. */ - gpioPortA = 0, -#endif -#if (_GPIO_PORT_B_PIN_COUNT > 0) - /** Port B. */ - gpioPortB = 1, -#endif -#if (_GPIO_PORT_C_PIN_COUNT > 0) - /** Port C. */ - gpioPortC = 2, -#endif -#if (_GPIO_PORT_D_PIN_COUNT > 0) - /** Port D. */ - gpioPortD = 3, -#endif -#if (_GPIO_PORT_E_PIN_COUNT > 0) - /** Port E. */ - gpioPortE = 4, -#endif -#if (_GPIO_PORT_F_PIN_COUNT > 0) - /** Port F. */ - gpioPortF = 5, -#endif -#if (_GPIO_PORT_G_PIN_COUNT > 0) - /** Port G. */ - gpioPortG = 6, -#endif -#if (_GPIO_PORT_H_PIN_COUNT > 0) - /** Port H. */ - gpioPortH = 7, -#endif -#if (_GPIO_PORT_I_PIN_COUNT > 0) - /** Port I. */ - gpioPortI = 8, -#endif -#if (_GPIO_PORT_J_PIN_COUNT > 0) - /** Port J. */ - gpioPortJ = 9, -#endif -#if (_GPIO_PORT_K_PIN_COUNT > 0) - /** Port K. */ - gpioPortK = 10, -#endif -}; - -#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) -/** GPIO drive mode. */ -SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { - /** Default 6mA. */ - gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, - /** 0.5 mA. */ - gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, - /** 20 mA. */ - gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, - /** 2 mA. */ - gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW -}; -#endif - -#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) -/** GPIO drive strength. */ -SL_ENUM_GENERIC(GPIO_DriveStrength_TypeDef, uint32_t) { - /** GPIO weak 1mA and alternate function weak 1mA. */ - gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, - - /** GPIO weak 1mA and alternate function strong 10mA. */ - gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, - - /** GPIO strong 10mA and alternate function weak 1mA. */ - gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, - - /** GPIO strong 10mA and alternate function strong 10mA. */ - gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, -}; - -/* Deprecated enums. */ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong -#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak -/** @endcond */ -#endif - -/** Pin mode. For more details on each mode, refer to the - * reference manual. */ -SL_ENUM_GENERIC(GPIO_Mode_TypeDef, uint32_t) { - /** Input disabled. Pull-up if DOUT is set. */ - gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, - /** Input enabled. Filter if DOUT is set. */ - gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, - /** Input enabled. DOUT determines pull direction. */ - gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, - /** Input enabled with filter. DOUT determines pull direction. */ - gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, - /** Push-pull output. */ - gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, -#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) - /** Push-pull output with drive-strength set by DRIVEMODE. */ - gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, -#endif -#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) - /** Push-pull using alternate control. */ - gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, -#endif - /** Wired-or output. */ - gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, - /** Wired-or output with pull-down. */ - gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, - /** Open-drain output. */ - gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, - /** Open-drain output with filter. */ - gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, - /** Open-drain output with pull-up. */ - gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, - /** Open-drain output with filter and pull-up. */ - gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, -#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) - /** Open-drain output with drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, - /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, - /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, - /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER -#endif -#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) - /** Open-drain output using alternate control. */ - gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, - /** Open-drain output using alternate control with filter. */ - gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, - /** Open-drain output using alternate control with pull-up. */ - gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, - /** Open-drain output using alternate control with filter and pull-up. */ - gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, -#endif -}; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void GPIO_DbgLocationSet(unsigned int location); - -/***************************************************************************//** - * @brief - * Enable/disable serial wire clock pin. - * - * @note - * Disabling SWDClk will disable the debug interface, which may result in - * a lockout if done early in startup (before debugger is able to halt core). - * - * @param[in] enable - * @li false - disable serial wire clock. - * @li true - enable serial wire clock (default after reset). - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWCLKPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); -#elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) - BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWCLK pin is not defined." -#endif -} - -/***************************************************************************//** - * @brief - * Enable/disable serial wire data I/O pin. - * - * @note - * Disabling SWDClk will disable the debug interface, which may result in - * a lockout if done early in startup (before debugger is able to halt core). - * - * @param[in] enable - * @li false - disable serial wire data pin. - * @li true - enable serial wire data pin (default after reset). - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWDIOPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); -#elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) - BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWDIO pin is not defined." -#endif -} - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ - || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) -/***************************************************************************//** - * @brief - * Enable/Disable serial wire output pin. - * - * @note - * Enabling this pin is not sufficient to fully enable serial wire output, - * which is also dependent on issues outside the GPIO module. Refer to - * DBG_SWOEnable(). - * - * @warning - * If debug port is locked, SWO pin is not disabled automatically. To avoid - * information leakage through SWO, disable SWO pin after locking debug port. - * - * @param[in] enable - * @li false - disable serial wire viewer pin (default after reset). - * @li true - enable serial wire viewer pin. - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); -#elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) - BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWO/SWV pin is not defined." -#endif -} -#endif - -#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) -void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); -#endif - -#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) -void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); -#endif - -# if defined(_GPIO_EM4WUEN_MASK) -/**************************************************************************//** - * @brief - * Disable GPIO pin wake-up from EM4. - * - * @param[in] pinmask - * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. - * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. - *****************************************************************************/ -__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) -{ - EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); - - GPIO->EM4WUEN &= ~pinmask; -} -#endif - -# if defined(_GPIO_EM4WUEN_MASK) -void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); -#endif - -#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) -/**************************************************************************//** - * @brief - * Check which GPIO pin(s) that caused a wake-up from EM4. - * - * @return - * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the - * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. - *****************************************************************************/ -__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) -{ -#if defined(_GPIO_EM4WUCAUSE_MASK) - return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; -#else - return GPIO->IF & _GPIO_IF_EM4WU_MASK; -#endif -} -#endif - -#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/**************************************************************************//** - * @brief - * Enable GPIO pin retention of output enable, output value, pull enable, and - * pull direction in EM4. - * - * @note - * On series 0 devices EM4 gpio retention can either be turned on or off. On - * series 1 devices there are three EM4 GPIO retention modes available. These - * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the EMU_EM4Init() - * to configure the GPIO retention mode on a series 1 device. - * - * The behavior of this function depends on the configured GPIO retention mode. - * If the GPIO retention mode is configured to be "SWUNLATCH" then this - * function will not change anything. If the retention mode is anything else - * then this function will set the GPIO retention mode to "EM4EXIT" when the - * enable argument is true, and "Disabled" when false. - * - * @param[in] enable - * @li true - enable EM4 pin retention. - * @li false - disable EM4 pin retention. - *****************************************************************************/ -__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) -{ -#if defined(GPIO_CTRL_EM4RET) - BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); -#else - - // Leave configuration alone when software unlatch is used. - uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; - if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { - return; - } - - if (enable) { - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; - } else { - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | EMU_EM4CTRL_EM4IORETMODE_DISABLE; - } -#endif -} -#endif - -void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - unsigned int intNo, - bool risingEdge, - bool fallingEdge, - bool enable); - -#if _SILICON_LABS_32B_SERIES > 0 -void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - uint32_t intNo, - bool polarity, - bool enable); -#endif -/***************************************************************************//** - * @brief - * Enable/disable input sensing. - * - * @details - * Disabling input sensing if not used, can save some energy consumption. - * - * @param[in] val - * Bitwise logic OR of one or more of: - * @li GPIO_INSENSE_INT - interrupt input sensing. - * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. - * - * @param[in] mask - * Mask containing bitwise logic OR of bits similar as for @p val used to - * indicate which input sense options to disable/enable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) -{ -#if defined(_GPIO_INSENSE_MASK) - BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); -#else - (void) val; - (void) mask; -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending GPIO interrupts. - * - * @param[in] flags - * Bitwise logic OR of GPIO interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntClear(uint32_t flags) -{ -#if defined(GPIO_HAS_SET_CLEAR) - GPIO->IF_CLR = flags; -#else - GPIO->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more GPIO interrupts. - * - * @param[in] flags - * GPIO interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntDisable(uint32_t flags) -{ - BUS_RegMaskedClear(&(GPIO->IEN), flags); -} - -/***************************************************************************//** - * @brief - * Enable one or more GPIO interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * GPIO_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * GPIO interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntEnable(uint32_t flags) -{ - BUS_RegMaskedSet(&(GPIO->IEN), flags); -} - -/***************************************************************************//** - * @brief - * Get enabled GPIO interrupts. - * - * @return - * Enabled GPIO interrupt sources. - * - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_EnabledIntGet(void) -{ - return GPIO->IEN; -} - -/***************************************************************************//** - * @brief - * Get pending GPIO interrupts. - * - * @return - * GPIO interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_IntGet(void) -{ - return GPIO->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending GPIO interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled GPIO interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in GPIO_IEN register - * and - * - the OR combination of valid interrupt flags in GPIO_IF register. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) -{ - uint32_t tmp; - - /* Store GPIO->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - tmp = GPIO->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return GPIO->IF & tmp; -} - -/**************************************************************************//** - * @brief - * Set one or more pending GPIO interrupts from SW. - * - * @param[in] flags - * GPIO interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void GPIO_IntSet(uint32_t flags) -{ -#if defined (GPIO_HAS_SET_CLEAR) - GPIO->IF_SET = flags; -#else - GPIO->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Lock the GPIO configuration. - ******************************************************************************/ -__STATIC_INLINE void GPIO_Lock(void) -{ - GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Read the pad value for a single pin in a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number to read. - * - * @return - * The pin value, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - return BUS_RegBitRead(&GPIO->P[port].DIN, pin); -} - -#if defined (_GPIO_P_PINLOCKN_MASK) -/***************************************************************************//** - * @brief - * Lock all GPIO configuration settings for a given pin. - * The lock can only be cleared by a chip reset. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number to lock. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) -{ - BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); -} -#endif - -GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, - unsigned int pin); - -void GPIO_PinModeSet(GPIO_Port_TypeDef port, - unsigned int pin, - GPIO_Mode_TypeDef mode, - unsigned int out); - -/***************************************************************************//** - * @brief - * Set a single pin in GPIO data out port register to 0. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to set. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_P_DOUTCLR_MASK) - GPIO->P[port].DOUTCLR = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_CLR[port].DOUT = 1UL << pin; -#else - BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1UL << pin); -#endif -} - -/***************************************************************************//** - * @brief - * Get current setting for a pin in a GPIO port data out register. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to get setting for. - * - * @return - * The DOUT setting for the requested pin, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); -} - -/***************************************************************************//** - * @brief - * Set a single pin in GPIO data out register to 1. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to set. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_P_DOUTSET_MASK) - GPIO->P[port].DOUTSET = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_SET[port].DOUT = 1UL << pin; -#else - BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1UL << pin); -#endif -} - -/***************************************************************************//** - * @brief - * Toggle a single pin in GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to toggle. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - -#if defined (_GPIO_P_DOUTTGL_MASK) - GPIO->P[port].DOUTTGL = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_TGL[port].DOUT = 1UL << pin; -#else - GPIO->P[port].DOUT ^= 1UL << pin; -#endif -} - -/***************************************************************************//** - * @brief - * Read the pad values for GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @return - * The pad values for the GPIO port. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - return GPIO->P[port].DIN; -} - -/***************************************************************************//** - * @brief - * Set bits in DOUT register for a port to 0. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask for bits to clear in DOUT register. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined(_GPIO_P_DOUTCLR_MASK) - GPIO->P[port].DOUTCLR = pins; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_CLR[port].DOUT = pins; -#else - BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current setting for a GPIO port data out register. - * - * @param[in] port - * The GPIO port to access. - * - * @return - * The data out setting for the requested port. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - return GPIO->P[port].DOUT; -} - -/***************************************************************************//** - * @brief - * Set bits GPIO data out register to 1. - * - * @note - * To ensure that the setting takes effect on the respective output pads, the - * pins must be configured properly. If not, it will take effect - * whenever the pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask for bits to set to 1 in DOUT register. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined(_GPIO_P_DOUTSET_MASK) - GPIO->P[port].DOUTSET = pins; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_SET[port].DOUT = pins; -#else - BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); -#endif -} - -/***************************************************************************//** - * @brief - * Set GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the respective output pads, the - * pins must be configured properly. If not, it will take effect - * whenever the pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] val - * Value to write to port data out register. - * - * @param[in] mask - * Mask indicating which bits to modify. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, - uint32_t val, - uint32_t mask) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); -} - -/***************************************************************************//** - * @brief - * Toggle pins in GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask with pins to toggle. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined (GPIO_HAS_SET_CLEAR) - GPIO->P_TGL[port].DOUT = pins; -#else - GPIO->P[port].DOUTTGL = pins; -#endif -} - -#if defined(_GPIO_P_CTRL_SLEWRATE_MASK) -/***************************************************************************//** - * @brief - * Set slewrate for pins on a GPIO port. - * - * @param[in] port - * The GPIO port to configure. - * - * @param[in] slewrate - * The slewrate to configure for pins on this GPIO port. - * - * @param[in] slewrateAlt - * The slewrate to configure for pins using alternate modes on this GPIO port. - ******************************************************************************/ -__STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, - uint32_t slewrate, - uint32_t slewrateAlt) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK - >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); - EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK - >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); - - GPIO->P[port].CTRL = (GPIO->P[port].CTRL - & ~(_GPIO_P_CTRL_SLEWRATE_MASK - | _GPIO_P_CTRL_SLEWRATEALT_MASK)) - | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) - | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); -} -#endif - -/***************************************************************************//** - * @brief - * Unlock the GPIO configuration. - ******************************************************************************/ -__STATIC_INLINE void GPIO_Unlock(void) -{ - GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; -} - -/** @} (end addtogroup gpio) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ -#endif /* EM_GPIO_H */ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPIO_H +#define EM_GPIO_H + +#include "em_device.h" +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_HAPPY_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 4 +#define _GPIO_PORT_E_PIN_COUNT 4 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x0707UL +#define _GPIO_PORT_B_PIN_MASK 0x6980UL +#define _GPIO_PORT_C_PIN_MASK 0xEF1FUL +#define _GPIO_PORT_D_PIN_MASK 0x00F0UL +#define _GPIO_PORT_E_PIN_MASK 0x3C00UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x1FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_GECKO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x03FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFC0UL +#define _GPIO_PORT_C_PIN_MASK 0x0FFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFF00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x000FUL +#define _GPIO_PORT_J_PIN_MASK 0xC000UL +#define _GPIO_PORT_K_PIN_MASK 0x0007UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 15 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x7FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 16 +#define _GPIO_PORT_H_PIN_COUNT 16 +#define _GPIO_PORT_I_PIN_COUNT 16 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_H_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_I_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_32B_SERIES_2) + +#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT +#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT +#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT +#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 0 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) +#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) +#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) +#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x0000UL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#else +#warning "Port and pin masks are not defined for this family." +#endif + +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ + : 0) + +#define _GPIO_PORT_MASK(port) ( \ + ((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ + : 0UL) + +/** Validation of port and pin. */ +#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) +#define GPIO_PORT_PIN_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) + +#if defined(_GPIO_EXTIPINSELL_MASK) +/** Validation of interrupt number and pin. */ +#define GPIO_INTNO_PIN_VALID(intNo, pin) \ + (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ + == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) +#endif + +/** Highest GPIO pin number. */ +#define GPIO_PIN_MAX 15 + +/** Highest GPIO port number. */ +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define GPIO_PORT_MAX 10 +#elif (_GPIO_PORT_J_PIN_COUNT > 0) +#define GPIO_PORT_MAX 9 +#elif (_GPIO_PORT_I_PIN_COUNT > 0) +#define GPIO_PORT_MAX 8 +#elif (_GPIO_PORT_H_PIN_COUNT > 0) +#define GPIO_PORT_MAX 7 +#elif (_GPIO_PORT_G_PIN_COUNT > 0) +#define GPIO_PORT_MAX 6 +#elif (_GPIO_PORT_F_PIN_COUNT > 0) +#define GPIO_PORT_MAX 5 +#elif (_GPIO_PORT_E_PIN_COUNT > 0) +#define GPIO_PORT_MAX 4 +#elif (_GPIO_PORT_D_PIN_COUNT > 0) +#define GPIO_PORT_MAX 3 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +/** Highest EXT GPIO interrupt number. */ +#define GPIO_EXTINTNO_MAX 15 + +/***************************************************************************//** + * @addtogroup gpio + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** GPIO ports IDs. */ +SL_ENUM(GPIO_Port_TypeDef) { +#if (_GPIO_PORT_A_PIN_COUNT > 0) + /** Port A. */ + gpioPortA = 0, +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) + /** Port B. */ + gpioPortB = 1, +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) + /** Port C. */ + gpioPortC = 2, +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) + /** Port D. */ + gpioPortD = 3, +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) + /** Port E. */ + gpioPortE = 4, +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) + /** Port F. */ + gpioPortF = 5, +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) + /** Port G. */ + gpioPortG = 6, +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) + /** Port H. */ + gpioPortH = 7, +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) + /** Port I. */ + gpioPortI = 8, +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) + /** Port J. */ + gpioPortJ = 9, +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) + /** Port K. */ + gpioPortK = 10, +#endif +}; + +#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) +/** GPIO drive mode. */ +SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { + /** Default 6mA. */ + gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, + /** 0.5 mA. */ + gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, + /** 20 mA. */ + gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, + /** 2 mA. */ + gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW +}; +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) +/** GPIO drive strength. */ +SL_ENUM_GENERIC(GPIO_DriveStrength_TypeDef, uint32_t) { + /** GPIO weak 1mA and alternate function weak 1mA. */ + gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO weak 1mA and alternate function strong 10mA. */ + gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, + + /** GPIO strong 10mA and alternate function weak 1mA. */ + gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO strong 10mA and alternate function strong 10mA. */ + gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, +}; + +/* Deprecated enums. */ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong +#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak +/** @endcond */ +#endif + +/** Pin mode. For more details on each mode, refer to the + * reference manual. */ +SL_ENUM_GENERIC(GPIO_Mode_TypeDef, uint32_t) { + /** Input disabled. Pull-up if DOUT is set. */ + gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, + /** Input enabled. Filter if DOUT is set. */ + gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, + /** Input enabled. DOUT determines pull direction. */ + gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, + /** Input enabled with filter. DOUT determines pull direction. */ + gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, + /** Push-pull output. */ + gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) + /** Push-pull output with drive-strength set by DRIVEMODE. */ + gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + /** Push-pull using alternate control. */ + gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, +#endif + /** Wired-or output. */ + gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, + /** Wired-or output with pull-down. */ + gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, + /** Open-drain output. */ + gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, + /** Open-drain output with filter. */ + gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, + /** Open-drain output with pull-up. */ + gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, + /** Open-drain output with filter and pull-up. */ + gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) + /** Open-drain output with drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, + /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, + /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, + /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + /** Open-drain output using alternate control. */ + gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, + /** Open-drain output using alternate control with filter. */ + gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, + /** Open-drain output using alternate control with pull-up. */ + gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, + /** Open-drain output using alternate control with filter and pull-up. */ + gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, +#endif +}; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void GPIO_DbgLocationSet(unsigned int location); + +/***************************************************************************//** + * @brief + * Enable/disable serial wire clock pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire clock. + * @li true - enable serial wire clock (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWCLKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWCLK pin is not defined." +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable serial wire data I/O pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire data pin. + * @li true - enable serial wire data pin (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWDIOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWDIO pin is not defined." +#endif +} + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ + || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) +/***************************************************************************//** + * @brief + * Enable/Disable serial wire output pin. + * + * @note + * Enabling this pin is not sufficient to fully enable serial wire output, + * which is also dependent on issues outside the GPIO module. Refer to + * DBG_SWOEnable(). + * + * @warning + * If debug port is locked, SWO pin is not disabled automatically. To avoid + * information leakage through SWO, disable SWO pin after locking debug port. + * + * @param[in] enable + * @li false - disable serial wire viewer pin (default after reset). + * @li true - enable serial wire viewer pin. + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); +#elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWO/SWV pin is not defined." +#endif +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Disable GPIO pin wake-up from EM4. + * + * @param[in] pinmask + * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. + * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); + + GPIO->EM4WUEN &= ~pinmask; +} +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); +#endif + +#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) +/**************************************************************************//** + * @brief + * Check which GPIO pin(s) that caused a wake-up from EM4. + * + * @return + * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the + * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) +{ +#if defined(_GPIO_EM4WUCAUSE_MASK) + return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; +#else + return GPIO->IF & _GPIO_IF_EM4WU_MASK; +#endif +} +#endif + +#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin retention of output enable, output value, pull enable, and + * pull direction in EM4. + * + * @note + * On series 0 devices EM4 gpio retention can either be turned on or off. On + * series 1 devices there are three EM4 GPIO retention modes available. These + * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the EMU_EM4Init() + * to configure the GPIO retention mode on a series 1 device. + * + * The behavior of this function depends on the configured GPIO retention mode. + * If the GPIO retention mode is configured to be "SWUNLATCH" then this + * function will not change anything. If the retention mode is anything else + * then this function will set the GPIO retention mode to "EM4EXIT" when the + * enable argument is true, and "Disabled" when false. + * + * @param[in] enable + * @li true - enable EM4 pin retention. + * @li false - disable EM4 pin retention. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) +{ +#if defined(GPIO_CTRL_EM4RET) + BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); +#else + + // Leave configuration alone when software unlatch is used. + uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; + if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { + return; + } + + if (enable) { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; + } else { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_DISABLE; + } +#endif +} +#endif + +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable); + +#if _SILICON_LABS_32B_SERIES > 0 +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable); +#endif +/***************************************************************************//** + * @brief + * Enable/disable input sensing. + * + * @details + * Disabling input sensing if not used, can save some energy consumption. + * + * @param[in] val + * Bitwise logic OR of one or more of: + * @li GPIO_INSENSE_INT - interrupt input sensing. + * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. + * + * @param[in] mask + * Mask containing bitwise logic OR of bits similar as for @p val used to + * indicate which input sense options to disable/enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) +{ +#if defined(_GPIO_INSENSE_MASK) + BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); +#else + (void) val; + (void) mask; +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending GPIO interrupts. + * + * @param[in] flags + * Bitwise logic OR of GPIO interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntClear(uint32_t flags) +{ +#if defined(GPIO_HAS_SET_CLEAR) + GPIO->IF_CLR = flags; +#else + GPIO->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more GPIO interrupts. + * + * @param[in] flags + * GPIO interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntDisable(uint32_t flags) +{ + BUS_RegMaskedClear(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Enable one or more GPIO interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * GPIO_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * GPIO interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntEnable(uint32_t flags) +{ + BUS_RegMaskedSet(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Get enabled GPIO interrupts. + * + * @return + * Enabled GPIO interrupt sources. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EnabledIntGet(void) +{ + return GPIO->IEN; +} + +/***************************************************************************//** + * @brief + * Get pending GPIO interrupts. + * + * @return + * GPIO interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGet(void) +{ + return GPIO->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending GPIO interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled GPIO interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in GPIO_IEN register + * and + * - the OR combination of valid interrupt flags in GPIO_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Store GPIO->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = GPIO->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return GPIO->IF & tmp; +} + +/**************************************************************************//** + * @brief + * Set one or more pending GPIO interrupts from SW. + * + * @param[in] flags + * GPIO interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void GPIO_IntSet(uint32_t flags) +{ +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->IF_SET = flags; +#else + GPIO->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Lock(void) +{ + GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Read the pad value for a single pin in a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to read. + * + * @return + * The pin value, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DIN, pin); +} + +#if defined (_GPIO_P_PINLOCKN_MASK) +/***************************************************************************//** + * @brief + * Lock all GPIO configuration settings for a given pin. + * The lock can only be cleared by a chip reset. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to lock. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) +{ + BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); +} +#endif + +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin); + +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out); + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out port register to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Get current setting for a pin in a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to get setting for. + * + * @return + * The DOUT setting for the requested pin, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); +} + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Toggle a single pin in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + +#if defined (_GPIO_P_DOUTTGL_MASK) + GPIO->P[port].DOUTTGL = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = 1UL << pin; +#else + GPIO->P[port].DOUT ^= 1UL << pin; +#endif +} + +/***************************************************************************//** + * @brief + * Read the pad values for GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The pad values for the GPIO port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DIN; +} + +/***************************************************************************//** + * @brief + * Set bits in DOUT register for a port to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to clear in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = pins; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current setting for a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The data out setting for the requested port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DOUT; +} + +/***************************************************************************//** + * @brief + * Set bits GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to set to 1 in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = pins; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Set GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] val + * Value to write to port data out register. + * + * @param[in] mask + * Mask indicating which bits to modify. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, + uint32_t val, + uint32_t mask) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); +} + +/***************************************************************************//** + * @brief + * Toggle pins in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask with pins to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = pins; +#else + GPIO->P[port].DOUTTGL = pins; +#endif +} + +#if defined(_GPIO_P_CTRL_SLEWRATE_MASK) +/***************************************************************************//** + * @brief + * Set slewrate for pins on a GPIO port. + * + * @param[in] port + * The GPIO port to configure. + * + * @param[in] slewrate + * The slewrate to configure for pins on this GPIO port. + * + * @param[in] slewrateAlt + * The slewrate to configure for pins using alternate modes on this GPIO port. + ******************************************************************************/ +__STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, + uint32_t slewrate, + uint32_t slewrateAlt) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK + >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); + EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK + >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK)) + | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) + | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); +} +#endif + +/***************************************************************************//** + * @brief + * Unlock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Unlock(void) +{ + GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/** @} (end addtogroup gpio) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ +#endif /* EM_GPIO_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h index 74feec9..839b622 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h @@ -1,525 +1,525 @@ -/***************************************************************************//** - * @file - * @brief Inter-integrated circuit (I2C) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_I2C_H -#define EM_I2C_H - -#include "em_device.h" -#if defined(I2C_COUNT) && (I2C_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup i2c - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** - * @brief - * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, - * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use - * worst case value of Tlow or Thigh as base. - * - * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz - * @note - * Due to chip characteristics, max value is somewhat reduced. - */ -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GECKO_FAMILY) \ - || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) \ - || defined(_EFM32_HAPPY_FAMILY)) -#define I2C_FREQ_STANDARD_MAX 93000 -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EFM32_WONDER_FAMILY)) -#define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_SERIES_1) -// None of the chips on this platform has been characterized on this parameter. -// Use same value as on Wonder until further notice. -#define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_SERIES_2) -#define I2C_FREQ_STANDARD_MAX 100000 -#else -#error "Unknown device family." -#endif - -/** - * @brief - * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, - * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use - * worst case value of Tlow or 2xThigh as base. - * - * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz - */ -#define I2C_FREQ_FAST_MAX 392157 - -/** - * @brief - * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, - * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use - * worst case value of Tlow or (11/6)xThigh as base. - * - * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz - */ -#define I2C_FREQ_FASTPLUS_MAX 987167 - -/** - * @brief - * Indicate plain write sequence: S+ADDR(W)+DATA0+P. - * @details - * @li S - Start - * @li ADDR(W) - address with W/R bit cleared - * @li DATA0 - Data taken from buffer with index 0 - * @li P - Stop - */ -#define I2C_FLAG_WRITE 0x0001 - -/** - * @brief - * Indicate plain read sequence: S+ADDR(R)+DATA0+P. - * @details - * @li S - Start - * @li ADDR(R) - Address with W/R bit set - * @li DATA0 - Data read into buffer with index 0 - * @li P - Stop - */ -#define I2C_FLAG_READ 0x0002 - -/** - * @brief - * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. - * @details - * @li S - Start - * @li Sr - Repeated start - * @li ADDR(W) - Address with W/R bit cleared - * @li ADDR(R) - Address with W/R bit set - * @li DATAn - Data written from/read into buffer with index n - * @li P - Stop - */ -#define I2C_FLAG_WRITE_READ 0x0004 - -/** - * @brief - * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. - * @details - * @li S - Start - * @li ADDR(W) - Address with W/R bit cleared - * @li DATAn - Data written from buffer with index n - * @li P - Stop - */ -#define I2C_FLAG_WRITE_WRITE 0x0008 - -/** Use 10 bit address. */ -#define I2C_FLAG_10BIT_ADDR 0x0010 - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Clock low to high ratio settings. */ -typedef enum { - i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ - i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ - i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ -} I2C_ClockHLR_TypeDef; - -/** Return codes for single Controller mode transfer function. */ -typedef enum { - /* In progress code (>0) */ - i2cTransferInProgress = 1, /**< Transfer in progress. */ - - /* Complete code (=0) */ - i2cTransferDone = 0, /**< Transfer completed successfully. */ - - /* Transfer error codes (<0). */ - i2cTransferNack = -1, /**< NACK received during transfer. */ - i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ - i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ - i2cTransferUsageFault = -4, /**< Usage fault. */ - i2cTransferSwFault = -5 /**< SW fault. */ -} I2C_TransferReturn_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** I2C initialization structure. */ -typedef struct { - /** Enable I2C peripheral when initialization completed. */ - bool enable; - - /** Set to Controller (true) or Target (false) mode */ - bool master; - - /** - * I2C reference clock assumed when configuring bus frequency setup. - * Set it to 0 if currently configured reference clock will be used - * This parameter is only applicable if operating in Controller mode. - */ - uint32_t refFreq; - - /** - * (Max) I2C bus frequency to use. This parameter is only applicable - * if operating in Controller mode. - */ - uint32_t freq; - - /** Clock low/high ratio control. */ - I2C_ClockHLR_TypeDef clhr; -} I2C_Init_TypeDef; - -/** Suggested default configuration for I2C initialization structure. */ -#define I2C_INIT_DEFAULT \ - { \ - true, /* Enable when initialization done. */ \ - true, /* Set to Controller mode. */ \ - 0, /* Use currently configured reference clock. */ \ - I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ - /* within I2C specification. */ \ - i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ - } - -/** - * @brief - * Master mode transfer message structure used to define a complete - * I2C transfer sequence (from start to stop). - * @details - * The structure allows for defining the following types of sequences - * (refer to defines for sequence details): - * @li #I2C_FLAG_READ - Data read into buf[0].data - * @li #I2C_FLAG_WRITE - Data written from buf[0].data - * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read - * into buf[1].data - * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and - * buf[1].data - */ -typedef struct { - /** - * @brief - * Address to use after (repeated) start. - * @details - * Layout details, A = Address bit, X = don't care bit (set to 0): - * @li 7 bit address - Use format AAAA AAAX - * @li 10 bit address - Use format XXXX XAAX AAAA AAAA - */ - uint16_t addr; - - /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ - uint16_t flags; - - /** - * Buffers used to hold data to send from or receive into, depending - * on sequence type. - */ - struct { - /** Buffer used for data to transmit/receive, must be @p len long. */ - uint8_t *data; - - /** - * Number of bytes in @p data to send or receive. Notice that when - * receiving data to this buffer, at least 1 byte must be received. - * Setting @p len to 0 in the receive case is considered a usage fault. - * Transmitting 0 bytes is legal, in which case only the address - * is transmitted after the start condition. - */ - uint16_t len; - } buf[2]; -} I2C_TransferSeq_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); -void I2C_BusFreqSet(I2C_TypeDef *i2c, - uint32_t freqRef, - uint32_t freqScl, - I2C_ClockHLR_TypeDef i2cMode); -void I2C_Enable(I2C_TypeDef *i2c, bool enable); -void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending I2C interrupts. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IF_CLR = flags; -#else - i2c->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more I2C interrupts. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IEN_CLR = flags; -#else - i2c->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more I2C interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * I2C_IntClear() prior to enabling the interrupt. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IEN_SET = flags; -#else - i2c->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending I2C interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) -{ - return i2c->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending I2C interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * Pending and enabled I2C interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in I2Cn_IEN and - * - the pending interrupt flags I2Cn_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) -{ - uint32_t ien; - - ien = i2c->IEN; - return i2c->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending I2C interrupts from SW. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to set to pending. Use a bitwise logic OR combination - * of valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IF_SET = flags; -#else - i2c->IFS = flags; -#endif -} - -void I2C_Reset(I2C_TypeDef *i2c); - -/***************************************************************************//** - * @brief - * Get Target address used for I2C peripheral (when operating in Target mode). - * - * @details - * For 10-bit addressing mode, the address is split in two bytes, and only - * the first byte setting is fetched, effectively only controlling the 2 most - * significant bits of the 10-bit address. Full handling of 10-bit addressing - * in Target mode requires additional SW handling. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C Target address in use. The 7 most significant bits define the actual - * address, the least significant bit is reserved and always returned as 0. - ******************************************************************************/ -__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) -{ - return ((uint8_t)(i2c->SADDR)); -} - -/***************************************************************************//** - * @brief - * Set Target address to use for I2C peripheral (when operating in Target mode). - * - * @details - * For 10- bit addressing mode, the address is split in two bytes, and only - * the first byte is set, effectively only controlling the 2 most significant - * bits of the 10-bit address. Full handling of 10-bit addressing in Target - * mode requires additional SW handling. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] addr - * I2C Target address to use. The 7 most significant bits define the actual - * address, the least significant bit is reserved and always set to 0. - ******************************************************************************/ -__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) -{ - i2c->SADDR = (uint32_t)addr & 0xfe; -} - -/***************************************************************************//** - * @brief - * Get Target address mask used for I2C peripheral (when operating in Target - * mode). - * - * @details - * The address mask defines how the comparator works. A bit position with - * value 0 means that the corresponding Target address bit is ignored during - * comparison (don't care). A bit position with value 1 means that the - * corresponding Target address bit must match. - * - * For 10-bit addressing mode, the address is split in two bytes, and only - * the mask for the first address byte is fetched, effectively only - * controlling the 2 most significant bits of the 10-bit address. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C Target address mask in use. The 7 most significant bits define the - * actual address mask, the least significant bit is reserved and always - * returned as 0. - ******************************************************************************/ -__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) -{ - return ((uint8_t)(i2c->SADDRMASK)); -} - -/***************************************************************************//** - * @brief - * Set Target address mask used for I2C peripheral (when operating in Target - * mode). - * - * @details - * The address mask defines how the comparator works. A bit position with - * value 0 means that the corresponding Target address bit is ignored during - * comparison (don't care). A bit position with value 1 means that the - * corresponding Target address bit must match. - * - * For 10-bit addressing mode, the address is split in two bytes, and only - * the mask for the first address byte is set, effectively only controlling - * the 2 most significant bits of the 10-bit address. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] mask - * I2C Target address mask to use. The 7 most significant bits define the - * actual address mask, the least significant bit is reserved and should - * be 0. - ******************************************************************************/ -__STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) -{ - i2c->SADDRMASK = (uint32_t)mask & 0xfe; -} - -I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); -I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, - I2C_TransferSeq_TypeDef *seq); - -/** @} (end addtogroup i2c) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ -#endif /* EM_I2C_H */ +/***************************************************************************//** + * @file + * @brief Inter-integrated circuit (I2C) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_I2C_H +#define EM_I2C_H + +#include "em_device.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup i2c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, + * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use + * worst case value of Tlow or Thigh as base. + * + * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz + * @note + * Due to chip characteristics, max value is somewhat reduced. + */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 93000 +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_1) +// None of the chips on this platform has been characterized on this parameter. +// Use same value as on Wonder until further notice. +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_FREQ_STANDARD_MAX 100000 +#else +#error "Unknown device family." +#endif + +/** + * @brief + * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, + * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use + * worst case value of Tlow or 2xThigh as base. + * + * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz + */ +#define I2C_FREQ_FAST_MAX 392157 + +/** + * @brief + * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, + * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use + * worst case value of Tlow or (11/6)xThigh as base. + * + * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz + */ +#define I2C_FREQ_FASTPLUS_MAX 987167 + +/** + * @brief + * Indicate plain write sequence: S+ADDR(W)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(W) - address with W/R bit cleared + * @li DATA0 - Data taken from buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_WRITE 0x0001 + +/** + * @brief + * Indicate plain read sequence: S+ADDR(R)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(R) - Address with W/R bit set + * @li DATA0 - Data read into buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_READ 0x0002 + +/** + * @brief + * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. + * @details + * @li S - Start + * @li Sr - Repeated start + * @li ADDR(W) - Address with W/R bit cleared + * @li ADDR(R) - Address with W/R bit set + * @li DATAn - Data written from/read into buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_READ 0x0004 + +/** + * @brief + * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. + * @details + * @li S - Start + * @li ADDR(W) - Address with W/R bit cleared + * @li DATAn - Data written from buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_WRITE 0x0008 + +/** Use 10 bit address. */ +#define I2C_FLAG_10BIT_ADDR 0x0010 + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock low to high ratio settings. */ +typedef enum { + i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ + i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ + i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ +} I2C_ClockHLR_TypeDef; + +/** Return codes for single Controller mode transfer function. */ +typedef enum { + /* In progress code (>0) */ + i2cTransferInProgress = 1, /**< Transfer in progress. */ + + /* Complete code (=0) */ + i2cTransferDone = 0, /**< Transfer completed successfully. */ + + /* Transfer error codes (<0). */ + i2cTransferNack = -1, /**< NACK received during transfer. */ + i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ + i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ + i2cTransferUsageFault = -4, /**< Usage fault. */ + i2cTransferSwFault = -5 /**< SW fault. */ +} I2C_TransferReturn_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** I2C initialization structure. */ +typedef struct { + /** Enable I2C peripheral when initialization completed. */ + bool enable; + + /** Set to Controller (true) or Target (false) mode */ + bool master; + + /** + * I2C reference clock assumed when configuring bus frequency setup. + * Set it to 0 if currently configured reference clock will be used + * This parameter is only applicable if operating in Controller mode. + */ + uint32_t refFreq; + + /** + * (Max) I2C bus frequency to use. This parameter is only applicable + * if operating in Controller mode. + */ + uint32_t freq; + + /** Clock low/high ratio control. */ + I2C_ClockHLR_TypeDef clhr; +} I2C_Init_TypeDef; + +/** Suggested default configuration for I2C initialization structure. */ +#define I2C_INIT_DEFAULT \ + { \ + true, /* Enable when initialization done. */ \ + true, /* Set to Controller mode. */ \ + 0, /* Use currently configured reference clock. */ \ + I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ + /* within I2C specification. */ \ + i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ + } + +/** + * @brief + * Master mode transfer message structure used to define a complete + * I2C transfer sequence (from start to stop). + * @details + * The structure allows for defining the following types of sequences + * (refer to defines for sequence details): + * @li #I2C_FLAG_READ - Data read into buf[0].data + * @li #I2C_FLAG_WRITE - Data written from buf[0].data + * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read + * into buf[1].data + * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and + * buf[1].data + */ +typedef struct { + /** + * @brief + * Address to use after (repeated) start. + * @details + * Layout details, A = Address bit, X = don't care bit (set to 0): + * @li 7 bit address - Use format AAAA AAAX + * @li 10 bit address - Use format XXXX XAAX AAAA AAAA + */ + uint16_t addr; + + /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ + uint16_t flags; + + /** + * Buffers used to hold data to send from or receive into, depending + * on sequence type. + */ + struct { + /** Buffer used for data to transmit/receive, must be @p len long. */ + uint8_t *data; + + /** + * Number of bytes in @p data to send or receive. Notice that when + * receiving data to this buffer, at least 1 byte must be received. + * Setting @p len to 0 in the receive case is considered a usage fault. + * Transmitting 0 bytes is legal, in which case only the address + * is transmitted after the start condition. + */ + uint16_t len; + } buf[2]; +} I2C_TransferSeq_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode); +void I2C_Enable(I2C_TypeDef *i2c, bool enable); +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_CLR = flags; +#else + i2c->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_CLR = flags; +#else + i2c->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more I2C interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * I2C_IntClear() prior to enabling the interrupt. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_SET = flags; +#else + i2c->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending I2C interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) +{ + return i2c->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending I2C interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * Pending and enabled I2C interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in I2Cn_IEN and + * - the pending interrupt flags I2Cn_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) +{ + uint32_t ien; + + ien = i2c->IEN; + return i2c->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending I2C interrupts from SW. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_SET = flags; +#else + i2c->IFS = flags; +#endif +} + +void I2C_Reset(I2C_TypeDef *i2c); + +/***************************************************************************//** + * @brief + * Get Target address used for I2C peripheral (when operating in Target mode). + * + * @details + * For 10-bit addressing mode, the address is split in two bytes, and only + * the first byte setting is fetched, effectively only controlling the 2 most + * significant bits of the 10-bit address. Full handling of 10-bit addressing + * in Target mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address in use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDR)); +} + +/***************************************************************************//** + * @brief + * Set Target address to use for I2C peripheral (when operating in Target mode). + * + * @details + * For 10- bit addressing mode, the address is split in two bytes, and only + * the first byte is set, effectively only controlling the 2 most significant + * bits of the 10-bit address. Full handling of 10-bit addressing in Target + * mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] addr + * I2C Target address to use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always set to 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) +{ + i2c->SADDR = (uint32_t)addr & 0xfe; +} + +/***************************************************************************//** + * @brief + * Get Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is fetched, effectively only + * controlling the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address mask in use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and always + * returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDRMASK)); +} + +/***************************************************************************//** + * @brief + * Set Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is set, effectively only controlling + * the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] mask + * I2C Target address mask to use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and should + * be 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) +{ + i2c->SADDRMASK = (uint32_t)mask & 0xfe; +} + +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq); + +/** @} (end addtogroup i2c) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ +#endif /* EM_I2C_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h index 340474b..43b0eea 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h @@ -1,1399 +1,1399 @@ -/***************************************************************************//** - * @file - * @brief Incremental Analog to Digital Converter (IADC) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_IADC_H -#define EM_IADC_H - -#include "em_device.h" -#include "em_gpio.h" -#include "em_system.h" -#if defined(IADC_COUNT) && (IADC_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup iadc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Warm-up mode. */ -typedef enum { - /** IADC shutdown after each conversion. */ - iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL, - - /** ADC is kept in standby mode between conversion. */ - iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY, - - /** ADC and reference selected for scan mode kept warmup, allowing - continuous conversion. */ - iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM -} IADC_Warmup_t; - -/** IADC result alignment. */ -typedef enum { - /** IADC results 12-bit right aligned */ - iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12, - - /** IADC results 12-bit left aligned */ - iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12, - -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - /** IADC results 16-bit right aligned */ - iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16, - - /** IADC results 16-bit left aligned */ - iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16, -#endif - -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - /** IADC results 20-bit right aligned */ - iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20, - - /** IADC results 20-bit left aligned */ - iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20, -#endif -} IADC_Alignment_t; - -/** IADC negative input selection. */ -typedef enum { - /** Ground */ - iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)) - | 1, - /** Ground using even mux */ - iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), - -#if defined(_IADC_SCAN_PORTNEG_DAC1) - /** Direct connection to DAC_1 input pin */ - iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADANA1) - /** Direct connection to Pad_ana_1 input pin */ - iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADANA3) - /** Direct connection to Pad_ana_3 input pin */ - iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADREFNEG) - /** Negative reference pin 0 */ - iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif - /** GPIO port A pin 0 */ - iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), - - /** GPIO port A pin 1 */ - iadcNegInputPortAPin1, - - /** GPIO port A pin 2 */ - iadcNegInputPortAPin2, - - /** GPIO port A pin 3 */ - iadcNegInputPortAPin3, - - /** GPIO port A pin 4 */ - iadcNegInputPortAPin4, - - /** GPIO port A pin 5 */ - iadcNegInputPortAPin5, - - /** GPIO port A pin 6 */ - iadcNegInputPortAPin6, - - /** GPIO port A pin 7 */ - iadcNegInputPortAPin7, - - /** GPIO port A pin 8 */ - iadcNegInputPortAPin8, - - /** GPIO port A pin 9 */ - iadcNegInputPortAPin9, - - /** GPIO port A pin 10 */ - iadcNegInputPortAPin10, - - /** GPIO port A pin 11 */ - iadcNegInputPortAPin11, - - /** GPIO port A pin 12 */ - iadcNegInputPortAPin12, - - /** GPIO port A pin 13 */ - iadcNegInputPortAPin13, - - /** GPIO port A pin 14 */ - iadcNegInputPortAPin14, - - /** GPIO port A pin 15 */ - iadcNegInputPortAPin15, - - /** GPIO port B pin 0 */ - iadcNegInputPortBPin0, - - /** GPIO port B pin 1 */ - iadcNegInputPortBPin1, - - /** GPIO port B pin 2 */ - iadcNegInputPortBPin2, - - /** GPIO port B pin 3 */ - iadcNegInputPortBPin3, - - /** GPIO port B pin 4 */ - iadcNegInputPortBPin4, - - /** GPIO port B pin 5 */ - iadcNegInputPortBPin5, - - /** GPIO port B pin 6 */ - iadcNegInputPortBPin6, - - /** GPIO port B pin 7 */ - iadcNegInputPortBPin7, - - /** GPIO port B pin 8 */ - iadcNegInputPortBPin8, - - /** GPIO port B pin 9 */ - iadcNegInputPortBPin9, - - /** GPIO port B pin 10 */ - iadcNegInputPortBPin10, - - /** GPIO port B pin 11 */ - iadcNegInputPortBPin11, - - /** GPIO port B pin 12 */ - iadcNegInputPortBPin12, - - /** GPIO port B pin 13 */ - iadcNegInputPortBPin13, - - /** GPIO port B pin 14 */ - iadcNegInputPortBPin14, - - /** GPIO port B pin 15 */ - iadcNegInputPortBPin15, - - /** GPIO port C pin 0 */ - iadcNegInputPortCPin0, - - /** GPIO port C pin 1 */ - iadcNegInputPortCPin1, - - /** GPIO port C pin 2 */ - iadcNegInputPortCPin2, - - /** GPIO port C pin 3 */ - iadcNegInputPortCPin3, - - /** GPIO port C pin 4 */ - iadcNegInputPortCPin4, - - /** GPIO port C pin 5 */ - iadcNegInputPortCPin5, - - /** GPIO port C pin 6 */ - iadcNegInputPortCPin6, - - /** GPIO port C pin 7 */ - iadcNegInputPortCPin7, - - /** GPIO port C pin 8 */ - iadcNegInputPortCPin8, - - /** GPIO port C pin 9 */ - iadcNegInputPortCPin9, - - /** GPIO port C pin 10 */ - iadcNegInputPortCPin10, - - /** GPIO port C pin 11 */ - iadcNegInputPortCPin11, - - /** GPIO port C pin 12 */ - iadcNegInputPortCPin12, - - /** GPIO port C pin 13 */ - iadcNegInputPortCPin13, - - /** GPIO port C pin 14 */ - iadcNegInputPortCPin14, - - /** GPIO port C pin 15 */ - iadcNegInputPortCPin15, - - /** GPIO port D pin 0 */ - iadcNegInputPortDPin0, - - /** GPIO port D pin 1 */ - iadcNegInputPortDPin1, - - /** GPIO port D pin 2 */ - iadcNegInputPortDPin2, - - /** GPIO port D pin 3 */ - iadcNegInputPortDPin3, - - /** GPIO port D pin 4 */ - iadcNegInputPortDPin4, - - /** GPIO port D pin 5 */ - iadcNegInputPortDPin5, - - /** GPIO port D pin 6 */ - iadcNegInputPortDPin6, - - /** GPIO port D pin 7 */ - iadcNegInputPortDPin7, - - /** GPIO port D pin 8 */ - iadcNegInputPortDPin8, - - /** GPIO port D pin 9 */ - iadcNegInputPortDPin9, - - /** GPIO port D pin 10 */ - iadcNegInputPortDPin10, - - /** GPIO port D pin 11 */ - iadcNegInputPortDPin11, - - /** GPIO port D pin 12 */ - iadcNegInputPortDPin12, - - /** GPIO port D pin 13 */ - iadcNegInputPortDPin13, - - /** GPIO port D pin 14 */ - iadcNegInputPortDPin14, - - /** GPIO port D pin 15 */ - iadcNegInputPortDPin15 -} IADC_NegInput_t; - -/** IADC positive port selection. */ -typedef enum { - /** Ground */ - iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), - - /** Avdd / 4 */ - iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 0, - - /** Vddio / 4 */ - iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 1, - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - /** Vddio1 / 4 */ - iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 2, - - /** Vddio2 / 4 */ - iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 3, -#else - /** Vss */ - iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 2, - - /** Vss */ - iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 3, -#endif - - /** Dvdd / 4 */ - iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 4, - - /** Decouple */ - iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 7, - -#if defined(_IADC_SCAN_PORTPOS_DAC0) - /** Direct connection to DAC_0 input pin */ - iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADANA0) - /** Direct connection to Pad_ana_0 input pin */ - iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADANA2) - /** Direct connection to Pad_ana_2 input pin */ - iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADREFPOS) - /** Positive reference pin 0 */ - iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif - - /** GPIO port A pin 0 */ - iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), - - /** GPIO port A pin 1 */ - iadcPosInputPortAPin1, - - /** GPIO port A pin 2 */ - iadcPosInputPortAPin2, - - /** GPIO port A pin 3 */ - iadcPosInputPortAPin3, - - /** GPIO port A pin 4 */ - iadcPosInputPortAPin4, - - /** GPIO port A pin 5 */ - iadcPosInputPortAPin5, - - /** GPIO port A pin 6 */ - iadcPosInputPortAPin6, - - /** GPIO port A pin 7 */ - iadcPosInputPortAPin7, - - /** GPIO port A pin 8 */ - iadcPosInputPortAPin8, - - /** GPIO port A pin 9 */ - iadcPosInputPortAPin9, - - /** GPIO port A pin 10 */ - iadcPosInputPortAPin10, - - /** GPIO port A pin 11 */ - iadcPosInputPortAPin11, - - /** GPIO port A pin 12 */ - iadcPosInputPortAPin12, - - /** GPIO port A pin 13 */ - iadcPosInputPortAPin13, - - /** GPIO port A pin 14 */ - iadcPosInputPortAPin14, - - /** GPIO port A pin 15 */ - iadcPosInputPortAPin15, - - /** GPIO port B pin 0 */ - iadcPosInputPortBPin0, - - /** GPIO port B pin 1 */ - iadcPosInputPortBPin1, - - /** GPIO port B pin 2 */ - iadcPosInputPortBPin2, - - /** GPIO port B pin 3 */ - iadcPosInputPortBPin3, - - /** GPIO port B pin 4 */ - iadcPosInputPortBPin4, - - /** GPIO port B pin 5 */ - iadcPosInputPortBPin5, - - /** GPIO port B pin 6 */ - iadcPosInputPortBPin6, - - /** GPIO port B pin 7 */ - iadcPosInputPortBPin7, - - /** GPIO port B pin 8 */ - iadcPosInputPortBPin8, - - /** GPIO port B pin 9 */ - iadcPosInputPortBPin9, - - /** GPIO port B pin 10 */ - iadcPosInputPortBPin10, - - /** GPIO port B pin 11 */ - iadcPosInputPortBPin11, - - /** GPIO port B pin 12 */ - iadcPosInputPortBPin12, - - /** GPIO port B pin 13 */ - iadcPosInputPortBPin13, - - /** GPIO port B pin 14 */ - iadcPosInputPortBPin14, - - /** GPIO port B pin 15 */ - iadcPosInputPortBPin15, - - /** GPIO port C pin 0 */ - iadcPosInputPortCPin0, - - /** GPIO port C pin 1 */ - iadcPosInputPortCPin1, - - /** GPIO port C pin 2 */ - iadcPosInputPortCPin2, - - /** GPIO port C pin 3 */ - iadcPosInputPortCPin3, - - /** GPIO port C pin 4 */ - iadcPosInputPortCPin4, - - /** GPIO port C pin 5 */ - iadcPosInputPortCPin5, - - /** GPIO port C pin 6 */ - iadcPosInputPortCPin6, - - /** GPIO port C pin 7 */ - iadcPosInputPortCPin7, - - /** GPIO port C pin 8 */ - iadcPosInputPortCPin8, - - /** GPIO port C pin 9 */ - iadcPosInputPortCPin9, - - /** GPIO port C pin 10 */ - iadcPosInputPortCPin10, - - /** GPIO port C pin 11 */ - iadcPosInputPortCPin11, - - /** GPIO port C pin 12 */ - iadcPosInputPortCPin12, - - /** GPIO port C pin 13 */ - iadcPosInputPortCPin13, - - /** GPIO port C pin 14 */ - iadcPosInputPortCPin14, - - /** GPIO port C pin 15 */ - iadcPosInputPortCPin15, - - /** GPIO port D pin 0 */ - iadcPosInputPortDPin0, - - /** GPIO port D pin 1 */ - iadcPosInputPortDPin1, - - /** GPIO port D pin 2 */ - iadcPosInputPortDPin2, - - /** GPIO port D pin 3 */ - iadcPosInputPortDPin3, - - /** GPIO port D pin 4 */ - iadcPosInputPortDPin4, - - /** GPIO port D pin 5 */ - iadcPosInputPortDPin5, - - /** GPIO port D pin 6 */ - iadcPosInputPortDPin6, - - /** GPIO port D pin 7 */ - iadcPosInputPortDPin7, - - /** GPIO port D pin 8 */ - iadcPosInputPortDPin8, - - /** GPIO port D pin 9 */ - iadcPosInputPortDPin9, - - /** GPIO port D pin 10 */ - iadcPosInputPortDPin10, - - /** GPIO port D pin 11 */ - iadcPosInputPortDPin11, - - /** GPIO port D pin 12 */ - iadcPosInputPortDPin12, - - /** GPIO port D pin 13 */ - iadcPosInputPortDPin13, - - /** GPIO port D pin 14 */ - iadcPosInputPortDPin14, - - /** GPIO port D pin 15 */ - iadcPosInputPortDPin15 -} IADC_PosInput_t; - -/** IADC Commands. */ -typedef enum { - /** Start single queue */ - iadcCmdStartSingle = IADC_CMD_SINGLESTART, - - /** Stop single queue */ - iadcCmdStopSingle = IADC_CMD_SINGLESTOP, - - /** Start scan queue */ - iadcCmdStartScan = IADC_CMD_SCANSTART, - - /** Stop scan queue */ - iadcCmdStopScan = IADC_CMD_SCANSTOP, - - /** Enable Timer */ - iadcCmdEnableTimer = IADC_CMD_TIMEREN, - - /** Disable Timer */ - iadcCmdDisableTimer = IADC_CMD_TIMERDIS -} IADC_Cmd_t; - -/** IADC Configuration. */ -typedef enum { - /** Normal mode */ - iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL, -#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) - /** High Speed mode */ - iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED, -#endif -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - /** High Accuracy mode */ - iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY -#endif -} IADC_CfgAdcMode_t; - -/** IADC Over sampling rate for high speed. */ -typedef enum { - /** High speed oversampling of 2x */ - iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2, - - /** High speed oversampling of 4x */ - iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4, - - /** High speed oversampling of 8x */ - iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8, - - /** High speed oversampling of 16x */ - iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16, - - /** High speed oversampling of 32x */ - iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32, - - /** High speed oversampling of 64x */ - iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64 -} IADC_CfgOsrHighSpeed_t; - -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** IADC Over sampling rate for high accuracy. */ -typedef enum { - /** High accuracy oversampling of 16x */ - iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16, - - /** High accuracy oversampling of 32x */ - iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32, - - /** High accuracy oversampling of 64x */ - iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64, - - /** High accuracy oversampling of 92x */ - iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92, - - /** High accuracy oversampling of 128x */ - iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128, - - /** High accuracy oversampling of 256x */ - iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256 -} IADC_CfgOsrHighAccuracy_t; -#endif - -/** IADC Analog Gain. */ -typedef enum { -#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) - /** Analog gain of 0.25x */ - iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25, -#endif - /** Analog gain of 0.5x */ - iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5, - - /** Analog gain of 1x */ - iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1, - - /** Analog gain of 2x */ - iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2, - - /** Analog gain of 3x */ - iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3, - - /** Analog gain of 4x */ - iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4 -} IADC_CfgAnalogGain_t; - -/** IADC Reference */ -typedef enum { - /** Internal 1.2V Band Gap Reference (buffered) to ground */ - iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, - - /** External reference (unbuffered) VREFP to VREFN. - * VEVREF up to AVDD. When inputs are routed to external GPIO pins, - * the maximum pin voltage is limited to the lower - * of the IOVDD and AVDD supplies. - * The internal calibration values correspond to a 1.25V reference, - * use of other voltages may require recalibration. - * See AN1189: Incremental Analog to Digital Converter (IADC) */ - iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, - -#if defined(_IADC_CFG_REFSEL_VREF2P5) - /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ - iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, -#endif - - /** VDDX (unbuffered) to ground. */ - iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX, - - /** 0.8 * VDDX (buffered) to ground. */ - iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF, - -#if defined(_IADC_CFG_REFSEL_VREFBUF) - /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */ - iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF, -#endif - -#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) - /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */ - iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF, -#endif -} IADC_CfgReference_t; - -/** IADC Two's complement results */ -typedef enum { - /** Automatic. Single ended => Unipolar, Differential => Bipolar */ - iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO, - - /** All results in unipolar format. Negative diff input gives 0 as result. */ - iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR, - - /** All results in bipolar (2's complement) format. Half range for SE. */ - iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR -} IADC_CfgTwosComp_t; - -/** IADC trigger action */ -typedef enum { - /** Start single/scan queue immediately */ - iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE, - - /** Timer starts single/scan queue */ - iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER, - - /** PRS0 from timer in same clock group starts single/scan queue */ - iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP, - - /** PRS0 positive edge starts single/scan queue */ - iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS, - - /** PRS0 negative edge starts single/scan queue */ - iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG, - -#if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE) - /** LESENSE starts scan queue */ - iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE -#endif -} IADC_TriggerSel_t; - -/** IADC trigger action */ -typedef enum { - /** Convert single/scan queue once per trigger */ - iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE, - - /** Convert single/scan queue continuously */ - iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS, -} IADC_TriggerAction_t; - -/** IADC data valid level before requesting DMA transfer */ -typedef enum { - /** Data valid level is 1 before requesting DMA transfer */ - iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1, - - /** Data valid level is 2 before requesting DMA transfer */ - iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2, - - /** Data valid level is 3 before requesting DMA transfer */ - iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3, - - /** Data valid level is 4 before requesting DMA transfer */ - iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4, - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 2 - /** Data valid level is 5 before requesting DMA transfer */ - iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5, - - /** Data valid level is 6 before requesting DMA transfer */ - iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6, - - /** Data valid level is 7 before requesting DMA transfer */ - iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7, -#endif - -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 3 - /** Data valid level is 8 before requesting DMA transfer */ - iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8 -#endif -#endif -} IADC_FifoCfgDvl_t; - -#if defined(_IADC_CFG_DIGAVG_MASK) -/** IADC digital averaging function. */ -typedef enum { - /** Average over 1 sample (no averaging). */ - iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1, - - /** Average over 2 samples. */ - iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2, - - /** Average over 4 samples. */ - iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4, - - /** Average over 8 samples. */ - iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8, - - /** Average over 16 samples. */ - iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16 -} IADC_DigitalAveraging_t; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** IADC init structure, common for single conversion and scan sequence. */ -typedef struct { - bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */ - bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */ - bool debugHalt; /**< Halt IADC during debug mode. */ - IADC_Warmup_t warmup; /**< IADC warmup mode. */ - uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us. - Used as time reference for IADC delays, e.g. warmup. - If the user sets timebase to 0, then IADC_Init() will - calculate the timebase using the currently defined CMU - clock setting for the IADC. */ - uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which - will be used if the calculated prescaler value is less. */ - uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */ - uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */ - uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */ -} IADC_Init_t; - -/** Default config for IADC init structure. */ -#define IADC_INIT_DEFAULT \ - { \ - false, /* IADC clock not disabled on PRS0*/ \ - false, /* IADC clock not disabled on PRS1 */ \ - false, /* Do not halt during debug */ \ - iadcWarmupNormal, /* IADC shutdown after each conversion. */ \ - 0, /* Calculate timebase. */ \ - 0, /* Max IADC clock rate. */ \ - _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \ - _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \ - _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \ - } - -/** IADC config structure */ -typedef struct { - IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */ - IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */ -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */ -#endif - IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */ - IADC_CfgReference_t reference; /**< Reference selection. */ - IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */ - uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */ - uint32_t vRef; /**< Vref magnitude expressed in millivolts. */ -#if defined(_IADC_CFG_DIGAVG_MASK) - IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */ -#endif -} IADC_Config_t; - -#if defined(_IADC_CFG_DIGAVG_MASK) -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210, /* Vref expressed in millivolts. */ \ - iadcDigitalAverage1 /* No averaging. */ \ - } -#else -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210, /* Vref expressed in millivolts. */ \ - iadcDigitalAverage1 /* No averaging. */ \ - } -#endif -#else -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210 /* Vref expressed in millivolts. */ \ - } -#else -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210 /* Vref expressed in millivolts. */ \ - } -#endif -#endif - -/** Structure for all IADC configs. */ -typedef struct { - /** All IADC configs. */ - IADC_Config_t configs[IADC0_CONFIGNUM]; -} IADC_AllConfigs_t; - -/** Default IADC sructure for all configs. */ -#define IADC_ALLCONFIGS_DEFAULT \ - { \ - { \ - IADC_CONFIG_DEFAULT, \ - IADC_CONFIG_DEFAULT \ - } \ - } - -/** IADC scan init structure */ -typedef struct { - IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ - bool showId; /**< Tag FIFO entry with scan table entry id. */ - IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ - bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ - IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ - IADC_TriggerAction_t triggerAction; /**< Trigger action. */ - bool start; /**< Start scan immediately. */ -} IADC_InitScan_t; - -/** Default config for IADC scan init structure. */ -#define IADC_INITSCAN_DEFAULT \ - { \ - iadcAlignRight12, /* Results 12-bit right aligned */ \ - false, /* Do not show ID in result */ \ - iadcFifoCfgDvl4, /* Use HW default value. */ \ - false, /* Do not wake up DMA on scan FIFO DVL */ \ - iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \ - iadcTriggerActionOnce, /* Convert once on scan trigger */ \ - false /* Do not start scan queue */ \ - } - -/** IADC single init structure */ -typedef struct { - IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ - bool showId; /**< Tag FIFO entry with single indicator (0x20). */ - IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ - bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ - IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ - IADC_TriggerAction_t triggerAction; /**< Trigger action. */ - bool singleTailgate; /**< If true, wait until end of SCAN queue - before single queue warmup and conversion. */ - bool start; /**< Start scan immediately. */ -} IADC_InitSingle_t; - -/** Default config for IADC single init structure. */ -#define IADC_INITSINGLE_DEFAULT \ - { \ - iadcAlignRight12, /* Results 12-bit right aligned */ \ - false, /* Do not show ID in result */ \ - iadcFifoCfgDvl4, /* Use HW default value. */ \ - false, /* Do not wake up DMA on single FIFO DVL */ \ - iadcTriggerSelImmediate, /* Start single immediately on trigger */ \ - iadcTriggerActionOnce, /* Convert once on single trigger */ \ - false, /* No tailgating */ \ - false /* Do not start single queue */ \ - } - -/** IADC single input selection structure */ -typedef struct { - IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ - IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ - uint8_t configId; /**< Configuration id. */ - bool compare; /**< Perform digital window comparison on the result from this entry. */ -} IADC_SingleInput_t; - -/** Default config for IADC single input structure. */ -#define IADC_SINGLEINPUT_DEFAULT \ - { \ - iadcNegInputGnd, /* Negative input GND */ \ - iadcPosInputGnd, /* Positive input GND */ \ - 0, /* Config 0 */ \ - false /* Do not compare results */ \ - } - -/** IADC scan table entry structure */ -typedef struct { - IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ - IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ - uint8_t configId; /**< Configuration id. */ - bool compare; /**< Perform digital window comparison on the result from this entry. */ - bool includeInScan; /**< Include this scan table entry in scan operation. */ -} IADC_ScanTableEntry_t; - -/** Default config for IADC scan table entry structure. */ -#define IADC_SCANTABLEENTRY_DEFAULT \ - { \ - iadcNegInputGnd,/* Negative input GND */ \ - iadcPosInputGnd,/* Positive input GND */ \ - 0, /* Config 0 */ \ - false, /* Do not compare results */ \ - false /* Do not include in scan */ \ - } - -/** Structure for IADC scan table. */ -typedef struct { - /** IADC scan table entries. */ - IADC_ScanTableEntry_t entries[IADC0_ENTRIES]; -} IADC_ScanTable_t; - -/** Default IADC structure for scan table */ -#define IADC_SCANTABLE_DEFAULT \ - { \ - { \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT \ - } \ - } - -/** Structure holding IADC result, including data and ID */ -typedef struct { - uint32_t data; /**< ADC sample data. */ - uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */ -} IADC_Result_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init, - const IADC_AllConfigs_t *allConfigs); -void IADC_reset(IADC_TypeDef *iadc); -void IADC_initScan(IADC_TypeDef *iadc, - const IADC_InitScan_t *init, - const IADC_ScanTable_t *scanTable); -void IADC_updateScanEntry(IADC_TypeDef *iadc, - uint8_t id, - IADC_ScanTableEntry_t *entry); -void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask); -void IADC_initSingle(IADC_TypeDef *iadc, - const IADC_InitSingle_t *init, - const IADC_SingleInput_t *input); -void IADC_updateSingleInput(IADC_TypeDef *iadc, - const IADC_SingleInput_t *input); -uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, - uint32_t srcClkFreq, - uint32_t cmuClkFreq); -uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, - uint32_t adcClkFreq, - uint32_t cmuClkFreq, - IADC_CfgAdcMode_t adcMode, - uint8_t srcClkPrescaler); -uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq); -IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc); -uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference); - -/***************************************************************************//** - * @brief - * Pull data from single data FIFO. If showId was set when initializing - * single mode, the results will contain the ID (0x20). - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc) -{ - return iadc->SINGLEFIFODATA; -} - -/***************************************************************************//** - * @brief - * Read most recent single conversion data. If showId was set when - * initializing single mode, the data will contain the ID (0x20). Calling - * this function will not affect the state of the single data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc) -{ - return iadc->SINGLEDATA; -} - -/***************************************************************************//** - * @brief - * Pull data from scan data FIFO. If showId was set for the scan entry - * initialization, the data will contain the ID of the scan entry. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc) -{ - return iadc->SCANFIFODATA; -} - -/***************************************************************************//** - * @brief - * Read most recent scan conversion data. If showId was set for the scan - * entry initialization, the data will contain the ID of the scan entry. - * Calling this function will not affect the state of the scan data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc) -{ - return iadc->SCANDATA; -} - -/***************************************************************************//** - * @brief - * Clear one or more pending IADC interrupts. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * Pending IADC interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IF_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more IADC interrupts. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags) -{ -#if defined (IADC_HAS_SET_CLEAR) - iadc->IEN_CLR = flags; -#else - iadc->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more IADC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using IADC_intClear() prior to enabling - * if such a pending interrupt should be ignored. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending IADC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * IADC interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc) -{ - return iadc->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending IADC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Pending and enabled IADC interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn - * register (IADCx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the IADC module - * (IADCx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc) -{ - uint32_t ien; - - /* Store IADCx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = iadc->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return iadc->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending IADC interrupts from SW. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to set to pending. Use a bitwise logic OR combination - * of valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Start/stop scan sequence, single conversion and/or timer. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] cmd - * Command to be performed. - ******************************************************************************/ -__STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd) -{ - iadc->CMD = (uint32_t)cmd; -} - -/***************************************************************************//** - * @brief - * Get the scan mask currently used in the IADC. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Mask of scan table entries currently included in scan. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc) -{ - return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT; -} - -/***************************************************************************//** - * @brief - * Get status bits of IADC. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * IADC status bits - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc) -{ - return iadc->STATUS; -} - -/***************************************************************************//** - * @brief - * Get the number of elements in the IADC single FIFO. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Number of elements in single FIFO - ******************************************************************************/ -__STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc) -{ - return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK) - >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get the number of elements in the IADC scan FIFO. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Number of elements in scan FIFO - ******************************************************************************/ -__STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc) -{ - return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK) - >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT); -} - -/***************************************************************************//** - * @brief - * Convert the GPIO port/pin to IADC negative input selection. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO in - * - * @return - * IADC negative input selection - ******************************************************************************/ -__STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port, - uint8_t pin) -{ - uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin; - - return (IADC_NegInput_t) input; -} - -/***************************************************************************//** - * @brief - * Convert the GPIO port/pin to IADC positive input selection. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO in - * - * @return - * IADC positive input selection - ******************************************************************************/ -__STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port, - uint8_t pin) -{ - uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin; - - return (IADC_PosInput_t) input; -} - -/** @} (end addtogroup iadc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ -#endif /* EM_IADC_H */ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_IADC_H +#define EM_IADC_H + +#include "em_device.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iadc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Warm-up mode. */ +typedef enum { + /** IADC shutdown after each conversion. */ + iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL, + + /** ADC is kept in standby mode between conversion. */ + iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY, + + /** ADC and reference selected for scan mode kept warmup, allowing + continuous conversion. */ + iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM +} IADC_Warmup_t; + +/** IADC result alignment. */ +typedef enum { + /** IADC results 12-bit right aligned */ + iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12, + + /** IADC results 12-bit left aligned */ + iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12, + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + /** IADC results 16-bit right aligned */ + iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16, + + /** IADC results 16-bit left aligned */ + iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16, +#endif + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + /** IADC results 20-bit right aligned */ + iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20, + + /** IADC results 20-bit left aligned */ + iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20, +#endif +} IADC_Alignment_t; + +/** IADC negative input selection. */ +typedef enum { + /** Ground */ + iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)) + | 1, + /** Ground using even mux */ + iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + +#if defined(_IADC_SCAN_PORTNEG_DAC1) + /** Direct connection to DAC_1 input pin */ + iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA1) + /** Direct connection to Pad_ana_1 input pin */ + iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA3) + /** Direct connection to Pad_ana_3 input pin */ + iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADREFNEG) + /** Negative reference pin 0 */ + iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif + /** GPIO port A pin 0 */ + iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + + /** GPIO port A pin 1 */ + iadcNegInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcNegInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcNegInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcNegInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcNegInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcNegInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcNegInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcNegInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcNegInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcNegInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcNegInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcNegInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcNegInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcNegInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcNegInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcNegInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcNegInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcNegInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcNegInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcNegInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcNegInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcNegInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcNegInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcNegInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcNegInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcNegInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcNegInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcNegInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcNegInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcNegInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcNegInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcNegInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcNegInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcNegInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcNegInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcNegInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcNegInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcNegInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcNegInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcNegInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcNegInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcNegInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcNegInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcNegInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcNegInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcNegInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcNegInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcNegInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcNegInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcNegInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcNegInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcNegInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcNegInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcNegInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcNegInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcNegInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcNegInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcNegInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcNegInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcNegInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcNegInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcNegInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcNegInputPortDPin15 +} IADC_NegInput_t; + +/** IADC positive port selection. */ +typedef enum { + /** Ground */ + iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** Avdd / 4 */ + iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 0, + + /** Vddio / 4 */ + iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 1, + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + /** Vddio1 / 4 */ + iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vddio2 / 4 */ + iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#else + /** Vss */ + iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vss */ + iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#endif + + /** Dvdd / 4 */ + iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 4, + + /** Decouple */ + iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 7, + +#if defined(_IADC_SCAN_PORTPOS_DAC0) + /** Direct connection to DAC_0 input pin */ + iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA0) + /** Direct connection to Pad_ana_0 input pin */ + iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA2) + /** Direct connection to Pad_ana_2 input pin */ + iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADREFPOS) + /** Positive reference pin 0 */ + iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif + + /** GPIO port A pin 0 */ + iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** GPIO port A pin 1 */ + iadcPosInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcPosInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcPosInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcPosInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcPosInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcPosInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcPosInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcPosInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcPosInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcPosInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcPosInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcPosInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcPosInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcPosInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcPosInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcPosInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcPosInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcPosInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcPosInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcPosInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcPosInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcPosInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcPosInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcPosInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcPosInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcPosInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcPosInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcPosInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcPosInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcPosInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcPosInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcPosInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcPosInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcPosInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcPosInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcPosInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcPosInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcPosInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcPosInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcPosInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcPosInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcPosInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcPosInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcPosInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcPosInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcPosInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcPosInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcPosInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcPosInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcPosInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcPosInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcPosInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcPosInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcPosInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcPosInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcPosInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcPosInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcPosInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcPosInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcPosInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcPosInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcPosInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcPosInputPortDPin15 +} IADC_PosInput_t; + +/** IADC Commands. */ +typedef enum { + /** Start single queue */ + iadcCmdStartSingle = IADC_CMD_SINGLESTART, + + /** Stop single queue */ + iadcCmdStopSingle = IADC_CMD_SINGLESTOP, + + /** Start scan queue */ + iadcCmdStartScan = IADC_CMD_SCANSTART, + + /** Stop scan queue */ + iadcCmdStopScan = IADC_CMD_SCANSTOP, + + /** Enable Timer */ + iadcCmdEnableTimer = IADC_CMD_TIMEREN, + + /** Disable Timer */ + iadcCmdDisableTimer = IADC_CMD_TIMERDIS +} IADC_Cmd_t; + +/** IADC Configuration. */ +typedef enum { + /** Normal mode */ + iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL, +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + /** High Speed mode */ + iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED, +#endif +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + /** High Accuracy mode */ + iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY +#endif +} IADC_CfgAdcMode_t; + +/** IADC Over sampling rate for high speed. */ +typedef enum { + /** High speed oversampling of 2x */ + iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2, + + /** High speed oversampling of 4x */ + iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4, + + /** High speed oversampling of 8x */ + iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8, + + /** High speed oversampling of 16x */ + iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16, + + /** High speed oversampling of 32x */ + iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32, + + /** High speed oversampling of 64x */ + iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64 +} IADC_CfgOsrHighSpeed_t; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** IADC Over sampling rate for high accuracy. */ +typedef enum { + /** High accuracy oversampling of 16x */ + iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16, + + /** High accuracy oversampling of 32x */ + iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32, + + /** High accuracy oversampling of 64x */ + iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64, + + /** High accuracy oversampling of 92x */ + iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92, + + /** High accuracy oversampling of 128x */ + iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128, + + /** High accuracy oversampling of 256x */ + iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256 +} IADC_CfgOsrHighAccuracy_t; +#endif + +/** IADC Analog Gain. */ +typedef enum { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + /** Analog gain of 0.25x */ + iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25, +#endif + /** Analog gain of 0.5x */ + iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5, + + /** Analog gain of 1x */ + iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1, + + /** Analog gain of 2x */ + iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2, + + /** Analog gain of 3x */ + iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3, + + /** Analog gain of 4x */ + iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4 +} IADC_CfgAnalogGain_t; + +/** IADC Reference */ +typedef enum { + /** Internal 1.2V Band Gap Reference (buffered) to ground */ + iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, + + /** External reference (unbuffered) VREFP to VREFN. + * VEVREF up to AVDD. When inputs are routed to external GPIO pins, + * the maximum pin voltage is limited to the lower + * of the IOVDD and AVDD supplies. + * The internal calibration values correspond to a 1.25V reference, + * use of other voltages may require recalibration. + * See AN1189: Incremental Analog to Digital Converter (IADC) */ + iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, + +#if defined(_IADC_CFG_REFSEL_VREF2P5) + /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ + iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, +#endif + + /** VDDX (unbuffered) to ground. */ + iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX, + + /** 0.8 * VDDX (buffered) to ground. */ + iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF, + +#if defined(_IADC_CFG_REFSEL_VREFBUF) + /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */ + iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF, +#endif + +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */ + iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF, +#endif +} IADC_CfgReference_t; + +/** IADC Two's complement results */ +typedef enum { + /** Automatic. Single ended => Unipolar, Differential => Bipolar */ + iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO, + + /** All results in unipolar format. Negative diff input gives 0 as result. */ + iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR, + + /** All results in bipolar (2's complement) format. Half range for SE. */ + iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR +} IADC_CfgTwosComp_t; + +/** IADC trigger action */ +typedef enum { + /** Start single/scan queue immediately */ + iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE, + + /** Timer starts single/scan queue */ + iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER, + + /** PRS0 from timer in same clock group starts single/scan queue */ + iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP, + + /** PRS0 positive edge starts single/scan queue */ + iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS, + + /** PRS0 negative edge starts single/scan queue */ + iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG, + +#if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE) + /** LESENSE starts scan queue */ + iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE +#endif +} IADC_TriggerSel_t; + +/** IADC trigger action */ +typedef enum { + /** Convert single/scan queue once per trigger */ + iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE, + + /** Convert single/scan queue continuously */ + iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS, +} IADC_TriggerAction_t; + +/** IADC data valid level before requesting DMA transfer */ +typedef enum { + /** Data valid level is 1 before requesting DMA transfer */ + iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1, + + /** Data valid level is 2 before requesting DMA transfer */ + iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2, + + /** Data valid level is 3 before requesting DMA transfer */ + iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3, + + /** Data valid level is 4 before requesting DMA transfer */ + iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4, + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 2 + /** Data valid level is 5 before requesting DMA transfer */ + iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5, + + /** Data valid level is 6 before requesting DMA transfer */ + iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6, + + /** Data valid level is 7 before requesting DMA transfer */ + iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7, +#endif + +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 3 + /** Data valid level is 8 before requesting DMA transfer */ + iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8 +#endif +#endif +} IADC_FifoCfgDvl_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +/** IADC digital averaging function. */ +typedef enum { + /** Average over 1 sample (no averaging). */ + iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1, + + /** Average over 2 samples. */ + iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2, + + /** Average over 4 samples. */ + iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4, + + /** Average over 8 samples. */ + iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8, + + /** Average over 16 samples. */ + iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16 +} IADC_DigitalAveraging_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** IADC init structure, common for single conversion and scan sequence. */ +typedef struct { + bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */ + bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */ + bool debugHalt; /**< Halt IADC during debug mode. */ + IADC_Warmup_t warmup; /**< IADC warmup mode. */ + uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us. + Used as time reference for IADC delays, e.g. warmup. + If the user sets timebase to 0, then IADC_Init() will + calculate the timebase using the currently defined CMU + clock setting for the IADC. */ + uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which + will be used if the calculated prescaler value is less. */ + uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */ + uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */ + uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */ +} IADC_Init_t; + +/** Default config for IADC init structure. */ +#define IADC_INIT_DEFAULT \ + { \ + false, /* IADC clock not disabled on PRS0*/ \ + false, /* IADC clock not disabled on PRS1 */ \ + false, /* Do not halt during debug */ \ + iadcWarmupNormal, /* IADC shutdown after each conversion. */ \ + 0, /* Calculate timebase. */ \ + 0, /* Max IADC clock rate. */ \ + _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \ + } + +/** IADC config structure */ +typedef struct { + IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */ + IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */ +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */ +#endif + IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */ + IADC_CfgReference_t reference; /**< Reference selection. */ + IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */ + uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */ + uint32_t vRef; /**< Vref magnitude expressed in millivolts. */ +#if defined(_IADC_CFG_DIGAVG_MASK) + IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */ +#endif +} IADC_Config_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#endif +#else +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#endif +#endif + +/** Structure for all IADC configs. */ +typedef struct { + /** All IADC configs. */ + IADC_Config_t configs[IADC0_CONFIGNUM]; +} IADC_AllConfigs_t; + +/** Default IADC sructure for all configs. */ +#define IADC_ALLCONFIGS_DEFAULT \ + { \ + { \ + IADC_CONFIG_DEFAULT, \ + IADC_CONFIG_DEFAULT \ + } \ + } + +/** IADC scan init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with scan table entry id. */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool start; /**< Start scan immediately. */ +} IADC_InitScan_t; + +/** Default config for IADC scan init structure. */ +#define IADC_INITSCAN_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on scan FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on scan trigger */ \ + false /* Do not start scan queue */ \ + } + +/** IADC single init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with single indicator (0x20). */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool singleTailgate; /**< If true, wait until end of SCAN queue + before single queue warmup and conversion. */ + bool start; /**< Start scan immediately. */ +} IADC_InitSingle_t; + +/** Default config for IADC single init structure. */ +#define IADC_INITSINGLE_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on single FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start single immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on single trigger */ \ + false, /* No tailgating */ \ + false /* Do not start single queue */ \ + } + +/** IADC single input selection structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ +} IADC_SingleInput_t; + +/** Default config for IADC single input structure. */ +#define IADC_SINGLEINPUT_DEFAULT \ + { \ + iadcNegInputGnd, /* Negative input GND */ \ + iadcPosInputGnd, /* Positive input GND */ \ + 0, /* Config 0 */ \ + false /* Do not compare results */ \ + } + +/** IADC scan table entry structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ + bool includeInScan; /**< Include this scan table entry in scan operation. */ +} IADC_ScanTableEntry_t; + +/** Default config for IADC scan table entry structure. */ +#define IADC_SCANTABLEENTRY_DEFAULT \ + { \ + iadcNegInputGnd,/* Negative input GND */ \ + iadcPosInputGnd,/* Positive input GND */ \ + 0, /* Config 0 */ \ + false, /* Do not compare results */ \ + false /* Do not include in scan */ \ + } + +/** Structure for IADC scan table. */ +typedef struct { + /** IADC scan table entries. */ + IADC_ScanTableEntry_t entries[IADC0_ENTRIES]; +} IADC_ScanTable_t; + +/** Default IADC structure for scan table */ +#define IADC_SCANTABLE_DEFAULT \ + { \ + { \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT \ + } \ + } + +/** Structure holding IADC result, including data and ID */ +typedef struct { + uint32_t data; /**< ADC sample data. */ + uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */ +} IADC_Result_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs); +void IADC_reset(IADC_TypeDef *iadc); +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable); +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry); +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask); +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input); +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input); +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq); +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler); +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq); +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc); +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference); + +/***************************************************************************//** + * @brief + * Pull data from single data FIFO. If showId was set when initializing + * single mode, the results will contain the ID (0x20). + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion data. If showId was set when + * initializing single mode, the data will contain the ID (0x20). Calling + * this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEDATA; +} + +/***************************************************************************//** + * @brief + * Pull data from scan data FIFO. If showId was set for the scan entry + * initialization, the data will contain the ID of the scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc) +{ + return iadc->SCANFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion data. If showId was set for the scan + * entry initialization, the data will contain the ID of the scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc) +{ + return iadc->SCANDATA; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * Pending IADC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags) +{ +#if defined (IADC_HAS_SET_CLEAR) + iadc->IEN_CLR = flags; +#else + iadc->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more IADC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using IADC_intClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending IADC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc) +{ + return iadc->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending IADC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Pending and enabled IADC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn + * register (IADCx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the IADC module + * (IADCx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc) +{ + uint32_t ien; + + /* Store IADCx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = iadc->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return iadc->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending IADC interrupts from SW. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Start/stop scan sequence, single conversion and/or timer. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] cmd + * Command to be performed. + ******************************************************************************/ +__STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd) +{ + iadc->CMD = (uint32_t)cmd; +} + +/***************************************************************************//** + * @brief + * Get the scan mask currently used in the IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Mask of scan table entries currently included in scan. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc) +{ + return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT; +} + +/***************************************************************************//** + * @brief + * Get status bits of IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc) +{ + return iadc->STATUS; +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC single FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in single FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC scan FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in scan FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC negative input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC negative input selection + ******************************************************************************/ +__STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin; + + return (IADC_NegInput_t) input; +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC positive input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC positive input selection + ******************************************************************************/ +__STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin; + + return (IADC_PosInput_t) input; +} + +/** @} (end addtogroup iadc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ +#endif /* EM_IADC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h index 5a9bc5f..2c9cfab 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h @@ -1,2819 +1,2819 @@ -/***************************************************************************//** - * @file - * @brief Direct memory access (LDMA) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_LDMA_H -#define EM_LDMA_H - -#include "em_device.h" - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup ldma LDMA - Linked DMA - * @brief Linked Direct Memory Access (LDMA) Peripheral API - * - * @details - * LDMA API functions provide full support for the LDMA peripheral. - * - * LDMA supports these DMA transfer types: - * - * @li Memory to memory. - * @li Memory to peripheral. - * @li Peripheral to memory. - * @li Peripheral to peripheral. - * @li Constant value to memory. - * - * LDMA supports linked lists of DMA descriptors allowing: - * - * @li Circular and ping-pong buffer transfers. - * @li Scatter-gather transfers. - * @li Looped transfers. - * - * LDMA has some advanced features: - * - * @li Intra-channel synchronization (SYNC), allowing hardware events to - * pause and restart a DMA sequence. - * @li Immediate-write (WRI), allowing DMA to write a constant anywhere - * in the memory map. - * @li Complex flow control allowing if-else constructs. - * - * Basic understanding of LDMA controller is assumed. Please refer to - * the reference manual for further details. The LDMA examples described - * in the reference manual are particularly helpful in understanding LDMA - * operations. - * - * In order to use the DMA controller, the initialization function @ref - * LDMA_Init() must have been executed once (normally during system initialization). - * - * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), - * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t - * and @ref LDMA_Descriptor_t structure parameters. - * The LDMA_Descriptor_t structure parameter may be a - * pointer to an array of descriptors, descriptors in array should - * be linked together as needed. - * - * Transfer and descriptor initialization macros are provided for the most common - * transfer types. Due to the flexibility of LDMA peripheral, only a small - * subset of all possible initializer macros are provided, users should create - * new ones when needed. - * - * Examples of LDMA usage: - * - * A simple memory to memory transfer: - * - * @include em_ldma_single.c - * - * @n A linked list of three memory to memory transfers: - * - * @include em_ldma_link_memory.c - * - * @n DMA from serial port peripheral to memory: - * - * @include em_ldma_peripheral.c - * - * @n Ping-pong DMA from serial port peripheral to memory: - * - * @include em_ldma_pingpong.c - * - * @note LDMA module does not implement LDMA interrupt handler. A - * template for an LDMA IRQ handler is included here as an example. - * - * @include em_ldma_irq.c - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** - * Controls the number of unit data transfers per arbitration - * cycle, providing a means to balance DMA channels' load on the controller. - */ -typedef enum { - ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ - ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ - ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ - ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ - ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ - ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ - ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ - ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ -} LDMA_CtrlBlockSize_t; - -/** DMA structure type. */ -typedef enum { - ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ - ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ - ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ -} LDMA_CtrlStructType_t; - -/** DMA transfer block or cycle selector. */ -typedef enum { - ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ - ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ -} LDMA_CtrlReqMode_t; - -/** Source address increment unit size. */ -typedef enum { - ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ - ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ - ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ - ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ -} LDMA_CtrlSrcInc_t; - -/** DMA transfer unit size. */ -typedef enum { - ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ - ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ - ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ -} LDMA_CtrlSize_t; - -/** Destination address increment unit size. */ -typedef enum { - ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ - ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ - ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ - ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ -} LDMA_CtrlDstInc_t; - -/** Source addressing mode. */ -typedef enum { - ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ - ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ -} LDMA_CtrlSrcAddrMode_t; - -/** Destination addressing mode. */ -typedef enum { - ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ - ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ -} LDMA_CtrlDstAddrMode_t; - -/** DMA link load address mode. */ -typedef enum { - ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ - ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ -} LDMA_LinkMode_t; - -/** Insert extra arbitration slots to increase channel arbitration priority. */ -typedef enum { - ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ - ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ - ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ - ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ -} LDMA_CfgArbSlots_t; - -/** Source address increment sign. */ -typedef enum { - ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ - ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ -} LDMA_CfgSrcIncSign_t; - -/** Destination address increment sign. */ -typedef enum { - ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ - ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ -} LDMA_CfgDstIncSign_t; - -#if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK) -/** Structure fetch operation bus port. */ -typedef enum { - ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgStructBusPort_t; -#endif - -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -/** Source operation bus port. */ -typedef enum { - ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgSrcBusPort_t; -#endif - -#if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK) -/** Destination operation bus port. */ -typedef enum { - ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgDstBusPort_t; -#endif - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** Rules table mode (interleaving destination). */ -typedef enum { - ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */ - ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */ - ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */ -} LDMA_RulesTblMode_t; -#endif - -#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) -/** Peripherals that can trigger LDMA transfers. */ -typedef enum { - ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 - ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 - ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 - ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 - ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 - ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF - ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 - ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 - ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 - ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF - ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV - ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT - ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL - ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT - ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY - ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV - ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT - ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL - ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT - ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY - ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV - ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT - ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL - ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT - ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY - ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV - ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL - ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV - ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL - ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI - ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV) - ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF - ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 - ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 - ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 - ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 - ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 - ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF - ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF - ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG - ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN - ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE - ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA - ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 - ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 - ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 - ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF - ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 - ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 - ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 - ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF - ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 - ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 - ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 - ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF - ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 - ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 - ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 - ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF - ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 - ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 - ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 - ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF - ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD - ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 - ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 - ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 - ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF - ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ) - ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ) - ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ) - ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ) - ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL - ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL - ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL - ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL - ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL - ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL - ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL - ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL - ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL - ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL - ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL - ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL - ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO) - ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO. - #endif -} LDMA_PeripheralSignal_t; - -#else -/** Peripherals that can trigger LDMA transfers. */ -typedef enum { - ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) - ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) - ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) - ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) - ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) - ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) - ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) - ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) - ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) - ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) - ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) - ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) - ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) - ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) - ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) - ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) - ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) - ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) - ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) - ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) - ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) - ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) - ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) - ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) - ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) - ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) - ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) - ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) - ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) - ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) - ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) - ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) - ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) - ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) - ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) - ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) - ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) - ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) - ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) - ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) - ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) - ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) - ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) - ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) - ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) - ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) - ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) - ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) - ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) - ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) - ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) - ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) - ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) - ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) - ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) - ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) - ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) - ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) - ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) - ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) - ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) - ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) - ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) - ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) - ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) - ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) - ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) - ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) - ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) - ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) - ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) - ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) - ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) - ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) - ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) - ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) - ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) - ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) - ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) - ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) - ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) - ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) - ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) - ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) - ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) - ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) - ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) - ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) - ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) - ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) - ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) - ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) - ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) - ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) - ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) - ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) - ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) - ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) - ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) - ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) - ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) - ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) - ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) - ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) - ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) - ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) - ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) - ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) - ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) - ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) - ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) - ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) - ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) - ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) - ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) - ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) - ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) - ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) - ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) - ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) - ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) - ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) - ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. - #endif -} LDMA_PeripheralSignal_t; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** - * @brief - * DMA descriptor. - * @details - * The LDMA DMA controller supports three different DMA descriptors. Each - * consists of four WORDs which map directly onto HW control registers for a - * given DMA channel. The three descriptor types are XFER, SYNC and WRI. - * Refer to the reference manual for further information. - */ -typedef union { - /** - * TRANSFER DMA descriptor, this is the only descriptor type which can be - * used to start a DMA transfer. - */ - struct { - uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t srcAddr; /**< DMA source address. */ - uint32_t dstAddr; /**< DMA destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } xfer; - - /** SYNCHRONIZE DMA descriptor, used for intra channel transfer - * synchronization. - */ - struct { - uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ - uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ - uint32_t reserved1 : 16; /**< Reserved. */ - uint32_t matchVal : 8; /**< Sync trigger match value. */ - uint32_t matchEn : 8; /**< Sync trigger match enable. */ - uint32_t reserved2 : 16; /**< Reserved. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } sync; - - /** WRITE DMA descriptor, used for write immediate operations. */ - struct { - uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t immVal; /**< Data to be written at dstAddr. */ - uint32_t dstAddr; /**< DMA write destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } wri; -} LDMA_Descriptor_t; - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA extended descriptor. - * @details - * The extended descriptor adds additional fields for the extended features - * available on the MMLDMA peripheral: destination interleaving and bufferable. - * The same three different DMA descriptors supported by the LDMA DMA controller - * are available. Each consists of seven WORDs (instead of four in non-extended - * descriptors) which map directly onto HW control registers for a given DMA - * channel. The three descriptor types are XFER, SYNC and WRI. But the - * extended fields are true only for XFER. The extended fields are the following: - * - * +- +- CTRL - * | Original | SRC - * | Structure | DST - * Extended | +- LINK - * Structure | XCTRL - * | Reserved for future usage - * +- ILSRC - * - * Refer to the reference manual for further information. - */ -typedef struct { - uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ - uint32_t extend : 1; /**< Extend data structure. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t srcAddr; /**< DMA source address. */ - uint32_t dstAddr; /**< DMA destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - - uint32_t reserved1 : 4; /**< Reserved */ - uint32_t dstIlEn : 1; /**< Destination interleave. */ - uint32_t IlMode : 2; /**< Interleave mode. */ - uint32_t bufferable : 1; /**< Allow AHB buffering. */ - uint32_t reserved2 : 24; /**< Reserved */ - - uint32_t reserved3; /**< Reserved */ - uint32_t IlSrc; /**< DMA rules table base address in memory. */ -} LDMA_DescriptorExtend_t; -#endif - -/** @brief LDMA initialization configuration structure. */ -typedef struct { - uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ - uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ - uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ - uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ -} LDMA_Init_t; - -/** - * @brief - * DMA transfer configuration structure. - * @details - * This structure configures all aspects of a DMA transfer. - */ -typedef struct { - uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ - uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ - uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ - uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ - uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ - bool ldmaReqDis; /**< Mask the PRS trigger input. */ - bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ - LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */ - LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ - LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ - uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) - LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */ - LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */ - LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */ -#endif -} LDMA_TransferCfg_t; - -/******************************************************************************* - ******************************** DEFINES ********************************** - ******************************************************************************/ - -/** @brief Size in words of a non-extended DMA descriptor. */ -#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4 - -/** @brief Size in words of an extended DMA descriptor. */ -#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7 - -/** @brief Maximum transfer size possible per descriptor. */ -#define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) - -/** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */ -#define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT) - -/** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */ -#define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT) - -/******************************************************************************* - ************************** STRUCT INITIALIZERS **************************** - ******************************************************************************/ - -/** @brief Default DMA initialization structure. */ -#define LDMA_INIT_DEFAULT \ - { \ - .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ - .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ - .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ - .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ - } - -/** - * @brief - * Generic DMA transfer configuration for memory to memory transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_MEMORY() \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_MEMORY() \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for looped memory to memory transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ - loopCnt, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ - loopCnt \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for memory to/from peripheral transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for looped memory to/from peripheral transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory word transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory word transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory half-word transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory half-word transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory byte transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory byte transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. - * @param[in] src Peripheral data source register address. - * @param[in] dest Peripheral data destination register address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral - * using the extended descriptor fields. - * @note - * For the extended descriptor, if IlMode uses the absolute addressing, the - * rules are used directly as the destination addresses of the corresponding - * data. Thus the argument 'dest' will be ignored by the DMA engine. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for word transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for word transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral - * using the extended descriptor fields. - * @note - * For the extended descriptor, if IlMode uses the absolute addressing, the - * rules are used directly as the destination addresses of the corresponding - * data. Thus the argument 'dest' will be ignored by the DMA engine. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * @param[in] value Immediate value to write. - * @param[in] address Write address. - */ -#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 1, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] value Immediate value to write. - * @param[in] address Write address. - */ -#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * @param[in] value Immediate value to write. - * @param[in] address Write address. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - */ -#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 1, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - */ -#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * Initializer for the destination interleaving portion of the DMA extended descriptor. - * @param[in] desc Transfer-type descriptor. - * @param[in] ilmode Rules table addressing mode for interleaved data. - * @param[in] ilsrc Base address for rules table in memory. - */ -#define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \ - { \ - (desc).dstIlEn = true; \ - (desc).IlMode = (ilmode); \ - (desc).IlSrc = (uint32_t)(ilsrc); \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void LDMA_DeInit(void); -void LDMA_EnableChannelRequest(int ch, bool enable); -void LDMA_Init(const LDMA_Init_t *init); -void LDMA_StartTransfer(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_Descriptor_t *descriptor); -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -void LDMA_StartTransferExtend(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_DescriptorExtend_t *descriptor_ext); -#endif -void LDMA_StopTransfer(int ch); -bool LDMA_TransferDone(int ch); -uint32_t LDMA_TransferRemainingCount(int ch); - -#if defined(_LDMA_SWRST_MASK) -/***************************************************************************//** - * @brief - * Reset the LDMA. - ******************************************************************************/ -__STATIC_INLINE void LDMA_Reset(void) -{ - LDMA->SWRST_SET = LDMA_SWRST_SWRST; - - /* Wait for reset to complete. */ - while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) { - } -} -#endif - -/***************************************************************************//** - * @brief - * Check if a certain channel is enabled. - * - * @param[in] ch - * LDMA channel to check. - * - * @return - * return true if the LDMA channel is enabled and false if the channel is not - * enabled. - ******************************************************************************/ -__STATIC_INLINE bool LDMA_ChannelEnabled(int ch) -{ - if ((ch < 0) || (ch > 31)) { - return false; - } -#if defined(_LDMA_CHSTATUS_MASK) - return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch))); -#else - // We've already confirmed ch is between 0 and 31, - // so it's now safe to cast it to uint8_t - return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch))); -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending LDMA interrupts. - * - * @param[in] flags - * Pending LDMA interrupt sources to clear. Use one or more valid - * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntClear(uint32_t flags) -{ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = flags; -#else - LDMA->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more LDMA interrupts. - * - * @param[in] flags - * LDMA interrupt sources to disable. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntDisable(uint32_t flags) -{ - LDMA->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more LDMA interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * LDMA_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * LDMA interrupt sources to enable. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntEnable(uint32_t flags) -{ - LDMA->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending LDMA interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * LDMA interrupt sources pending. Returns one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and - * one flag for each LDMA channel. - ******************************************************************************/ -__STATIC_INLINE uint32_t LDMA_IntGet(void) -{ - return LDMA->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending LDMA interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled LDMA interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in LDMA_IEN and - * - the pending interrupt flags LDMA_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) -{ - uint32_t ien; - - ien = LDMA->IEN; - return LDMA->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending LDMA interrupts - * - * @param[in] flags - * LDMA interrupt sources to set to pending. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and - * one done flag for each LDMA channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntSet(uint32_t flags) -{ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_SET = flags; -#else - LDMA->IFS = flags; -#endif -} - -/** @} (end addtogroup ldma) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ -#endif /* EM_LDMA_H */ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LDMA_H +#define EM_LDMA_H + +#include "em_device.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup ldma LDMA - Linked DMA + * @brief Linked Direct Memory Access (LDMA) Peripheral API + * + * @details + * LDMA API functions provide full support for the LDMA peripheral. + * + * LDMA supports these DMA transfer types: + * + * @li Memory to memory. + * @li Memory to peripheral. + * @li Peripheral to memory. + * @li Peripheral to peripheral. + * @li Constant value to memory. + * + * LDMA supports linked lists of DMA descriptors allowing: + * + * @li Circular and ping-pong buffer transfers. + * @li Scatter-gather transfers. + * @li Looped transfers. + * + * LDMA has some advanced features: + * + * @li Intra-channel synchronization (SYNC), allowing hardware events to + * pause and restart a DMA sequence. + * @li Immediate-write (WRI), allowing DMA to write a constant anywhere + * in the memory map. + * @li Complex flow control allowing if-else constructs. + * + * Basic understanding of LDMA controller is assumed. Please refer to + * the reference manual for further details. The LDMA examples described + * in the reference manual are particularly helpful in understanding LDMA + * operations. + * + * In order to use the DMA controller, the initialization function @ref + * LDMA_Init() must have been executed once (normally during system initialization). + * + * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), + * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t + * and @ref LDMA_Descriptor_t structure parameters. + * The LDMA_Descriptor_t structure parameter may be a + * pointer to an array of descriptors, descriptors in array should + * be linked together as needed. + * + * Transfer and descriptor initialization macros are provided for the most common + * transfer types. Due to the flexibility of LDMA peripheral, only a small + * subset of all possible initializer macros are provided, users should create + * new ones when needed. + * + * Examples of LDMA usage: + * + * A simple memory to memory transfer: + * + * @include em_ldma_single.c + * + * @n A linked list of three memory to memory transfers: + * + * @include em_ldma_link_memory.c + * + * @n DMA from serial port peripheral to memory: + * + * @include em_ldma_peripheral.c + * + * @n Ping-pong DMA from serial port peripheral to memory: + * + * @include em_ldma_pingpong.c + * + * @note LDMA module does not implement LDMA interrupt handler. A + * template for an LDMA IRQ handler is included here as an example. + * + * @include em_ldma_irq.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** + * Controls the number of unit data transfers per arbitration + * cycle, providing a means to balance DMA channels' load on the controller. + */ +typedef enum { + ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ + ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ + ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ + ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ + ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ + ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ + ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ + ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ +} LDMA_CtrlBlockSize_t; + +/** DMA structure type. */ +typedef enum { + ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ + ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ + ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ +} LDMA_CtrlStructType_t; + +/** DMA transfer block or cycle selector. */ +typedef enum { + ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ + ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ +} LDMA_CtrlReqMode_t; + +/** Source address increment unit size. */ +typedef enum { + ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ + ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ + ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ + ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ +} LDMA_CtrlSrcInc_t; + +/** DMA transfer unit size. */ +typedef enum { + ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ + ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ + ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ +} LDMA_CtrlSize_t; + +/** Destination address increment unit size. */ +typedef enum { + ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ + ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ + ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ + ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ +} LDMA_CtrlDstInc_t; + +/** Source addressing mode. */ +typedef enum { + ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlSrcAddrMode_t; + +/** Destination addressing mode. */ +typedef enum { + ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlDstAddrMode_t; + +/** DMA link load address mode. */ +typedef enum { + ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ + ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ +} LDMA_LinkMode_t; + +/** Insert extra arbitration slots to increase channel arbitration priority. */ +typedef enum { + ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ + ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ + ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ + ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ +} LDMA_CfgArbSlots_t; + +/** Source address increment sign. */ +typedef enum { + ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ + ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ +} LDMA_CfgSrcIncSign_t; + +/** Destination address increment sign. */ +typedef enum { + ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ + ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ +} LDMA_CfgDstIncSign_t; + +#if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK) +/** Structure fetch operation bus port. */ +typedef enum { + ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgStructBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +/** Source operation bus port. */ +typedef enum { + ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgSrcBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK) +/** Destination operation bus port. */ +typedef enum { + ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgDstBusPort_t; +#endif + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** Rules table mode (interleaving destination). */ +typedef enum { + ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */ + ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */ + ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */ +} LDMA_RulesTblMode_t; +#endif + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA + ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 + ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 + ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 + ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF + ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 + ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 + ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 + ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF + ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 + ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 + ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 + ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF + ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD + ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 + ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 + ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 + ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF + ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ) + ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ) + ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ) + ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ) + ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO. + #endif +} LDMA_PeripheralSignal_t; + +#else +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) + ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) + ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) + ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) + ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) + ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) + ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) + ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) + ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) + ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) + ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) + ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) + ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) + ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) + ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) + ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) + ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) + ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) + ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) + ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) + ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) + ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) + ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) + ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) + ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) + ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) + ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) + ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) + ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) + ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) + ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) + ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) + ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) + ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) + ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) + ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) + ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) + ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) + ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) + ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) + ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) + ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) + ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) + ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) + ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) + ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) + ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) + ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) + ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) + ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) + ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) + ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) + ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) + ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) + ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) + ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) + ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) + ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) + ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) + ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) + ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) + ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) + ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) + ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) + ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) + ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) + ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) + ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) + ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) + ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) + ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) + ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) + ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) + ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) + ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) + ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) + ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) + ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) + ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. + #endif +} LDMA_PeripheralSignal_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** + * @brief + * DMA descriptor. + * @details + * The LDMA DMA controller supports three different DMA descriptors. Each + * consists of four WORDs which map directly onto HW control registers for a + * given DMA channel. The three descriptor types are XFER, SYNC and WRI. + * Refer to the reference manual for further information. + */ +typedef union { + /** + * TRANSFER DMA descriptor, this is the only descriptor type which can be + * used to start a DMA transfer. + */ + struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } xfer; + + /** SYNCHRONIZE DMA descriptor, used for intra channel transfer + * synchronization. + */ + struct { + uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t reserved1 : 16; /**< Reserved. */ + uint32_t matchVal : 8; /**< Sync trigger match value. */ + uint32_t matchEn : 8; /**< Sync trigger match enable. */ + uint32_t reserved2 : 16; /**< Reserved. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } sync; + + /** WRITE DMA descriptor, used for write immediate operations. */ + struct { + uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t immVal; /**< Data to be written at dstAddr. */ + uint32_t dstAddr; /**< DMA write destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } wri; +} LDMA_Descriptor_t; + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA extended descriptor. + * @details + * The extended descriptor adds additional fields for the extended features + * available on the MMLDMA peripheral: destination interleaving and bufferable. + * The same three different DMA descriptors supported by the LDMA DMA controller + * are available. Each consists of seven WORDs (instead of four in non-extended + * descriptors) which map directly onto HW control registers for a given DMA + * channel. The three descriptor types are XFER, SYNC and WRI. But the + * extended fields are true only for XFER. The extended fields are the following: + * + * +- +- CTRL + * | Original | SRC + * | Structure | DST + * Extended | +- LINK + * Structure | XCTRL + * | Reserved for future usage + * +- ILSRC + * + * Refer to the reference manual for further information. + */ +typedef struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t extend : 1; /**< Extend data structure. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + + uint32_t reserved1 : 4; /**< Reserved */ + uint32_t dstIlEn : 1; /**< Destination interleave. */ + uint32_t IlMode : 2; /**< Interleave mode. */ + uint32_t bufferable : 1; /**< Allow AHB buffering. */ + uint32_t reserved2 : 24; /**< Reserved */ + + uint32_t reserved3; /**< Reserved */ + uint32_t IlSrc; /**< DMA rules table base address in memory. */ +} LDMA_DescriptorExtend_t; +#endif + +/** @brief LDMA initialization configuration structure. */ +typedef struct { + uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ + uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ + uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ + uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ +} LDMA_Init_t; + +/** + * @brief + * DMA transfer configuration structure. + * @details + * This structure configures all aspects of a DMA transfer. + */ +typedef struct { + uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ + uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ + uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ + uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ + uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ + bool ldmaReqDis; /**< Mask the PRS trigger input. */ + bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ + LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */ + LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ + LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ + uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */ + LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */ + LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */ +#endif +} LDMA_TransferCfg_t; + +/******************************************************************************* + ******************************** DEFINES ********************************** + ******************************************************************************/ + +/** @brief Size in words of a non-extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4 + +/** @brief Size in words of an extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7 + +/** @brief Maximum transfer size possible per descriptor. */ +#define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +/** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */ +#define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT) + +/** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */ +#define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT) + +/******************************************************************************* + ************************** STRUCT INITIALIZERS **************************** + ******************************************************************************/ + +/** @brief Default DMA initialization structure. */ +#define LDMA_INIT_DEFAULT \ + { \ + .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ + .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ + .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ + .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ + } + +/** + * @brief + * Generic DMA transfer configuration for memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. + * @param[in] src Peripheral data source register address. + * @param[in] dest Peripheral data destination register address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * Initializer for the destination interleaving portion of the DMA extended descriptor. + * @param[in] desc Transfer-type descriptor. + * @param[in] ilmode Rules table addressing mode for interleaved data. + * @param[in] ilsrc Base address for rules table in memory. + */ +#define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \ + { \ + (desc).dstIlEn = true; \ + (desc).IlMode = (ilmode); \ + (desc).IlSrc = (uint32_t)(ilsrc); \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void LDMA_DeInit(void); +void LDMA_EnableChannelRequest(int ch, bool enable); +void LDMA_Init(const LDMA_Init_t *init); +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor); +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext); +#endif +void LDMA_StopTransfer(int ch); +bool LDMA_TransferDone(int ch); +uint32_t LDMA_TransferRemainingCount(int ch); + +#if defined(_LDMA_SWRST_MASK) +/***************************************************************************//** + * @brief + * Reset the LDMA. + ******************************************************************************/ +__STATIC_INLINE void LDMA_Reset(void) +{ + LDMA->SWRST_SET = LDMA_SWRST_SWRST; + + /* Wait for reset to complete. */ + while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) { + } +} +#endif + +/***************************************************************************//** + * @brief + * Check if a certain channel is enabled. + * + * @param[in] ch + * LDMA channel to check. + * + * @return + * return true if the LDMA channel is enabled and false if the channel is not + * enabled. + ******************************************************************************/ +__STATIC_INLINE bool LDMA_ChannelEnabled(int ch) +{ + if ((ch < 0) || (ch > 31)) { + return false; + } +#if defined(_LDMA_CHSTATUS_MASK) + return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch))); +#else + // We've already confirmed ch is between 0 and 31, + // so it's now safe to cast it to uint8_t + return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch))); +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending LDMA interrupts. + * + * @param[in] flags + * Pending LDMA interrupt sources to clear. Use one or more valid + * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntClear(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = flags; +#else + LDMA->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LDMA interrupts. + * + * @param[in] flags + * LDMA interrupt sources to disable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntDisable(uint32_t flags) +{ + LDMA->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LDMA interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LDMA_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * LDMA interrupt sources to enable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntEnable(uint32_t flags) +{ + LDMA->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LDMA interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * LDMA interrupt sources pending. Returns one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and + * one flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGet(void) +{ + return LDMA->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LDMA interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled LDMA interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in LDMA_IEN and + * - the pending interrupt flags LDMA_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) +{ + uint32_t ien; + + ien = LDMA->IEN; + return LDMA->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LDMA interrupts + * + * @param[in] flags + * LDMA interrupt sources to set to pending. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and + * one done flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntSet(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_SET = flags; +#else + LDMA->IFS = flags; +#endif +} + +/** @} (end addtogroup ldma) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ +#endif /* EM_LDMA_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h index 5bbb638..43baefa 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h @@ -1,334 +1,334 @@ -/***************************************************************************//** - * @file - * @brief Low Energy Timer (LETIMER) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_LETIMER_H -#define EM_LETIMER_H - -#include -#include "em_device.h" -#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup letimer - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Repeat mode. */ -typedef enum { - /** Count until stopped by SW. */ - letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, - /** Count REP0 times. */ - letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, - /** - * Count REP0 times, if REP1 has been written to, it is loaded into - * REP0 when REP0 is about to be decremented to 0. - */ - letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, - /** - * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 - * are decremented when counter underflows. - */ - letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE -} LETIMER_RepeatMode_TypeDef; - -/** Underflow action on output. */ -typedef enum { - /** No output action. */ - letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, - /** Toggle output when counter underflows. */ - letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, - /** Hold output one LETIMER clock cycle when counter underflows. */ - letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, - /** Set output idle when counter underflows, and active when matching COMP1. */ - letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM -} LETIMER_UFOA_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LETIMER initialization structure. */ -typedef struct { - bool enable; /**< Start counting when initialization completes. */ - bool debugRun; /**< Counter shall keep running during debug halt. */ -#if defined(LETIMER_CTRL_RTCC0TEN) - bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ - bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ -#endif - bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ - bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ - uint8_t out0Pol; /**< Idle value for output 0. */ - uint8_t out1Pol; /**< Idle value for output 1. */ - LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ - LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ - LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ - uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ -} LETIMER_Init_TypeDef; - -/** Default configuration for LETIMER initialization structure. */ -#if defined(LETIMER_CTRL_RTCC0TEN) -#define LETIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - false, /* Do not start counting on RTC COMP0 match. */ \ - false, /* Do not start counting on RTC COMP1 match. */ \ - false, /* Do not load COMP0 into CNT on underflow. */ \ - false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ - 0, /* Idle value 0 for output 0. */ \ - 0, /* Idle value 0 for output 1. */ \ - letimerUFOANone, /* No action on underflow on output 0. */ \ - letimerUFOANone, /* No action on underflow on output 1. */ \ - letimerRepeatFree, /* Count until stopped by SW. */ \ - 0 /* Use default top Value. */ \ - } -#else -#define LETIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - false, /* Do not load COMP0 into CNT on underflow. */ \ - false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ - 0, /* Idle value 0 for output 0. */ \ - 0, /* Idle value 0 for output 1. */ \ - letimerUFOANone, /* No action on underflow on output 0. */ \ - letimerUFOANone, /* No action on underflow on output 1. */ \ - letimerRepeatFree, /* Count until stopped by SW. */ \ - 0 /* Use default top Value. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); -void LETIMER_CompareSet(LETIMER_TypeDef *letimer, - unsigned int comp, - uint32_t value); -uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer); -#if !defined(_EFM32_GECKO_FAMILY) -void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value); -#endif - -void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); -#if defined(_LETIMER_FREEZE_MASK) -void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); -#endif -void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending LETIMER interrupts. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * Pending LETIMER interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for the LETIMER module - * (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) -{ -#if defined (LETIMER_HAS_SET_CLEAR) - letimer->IF_CLR = flags; -#else - letimer->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more LETIMER interrupts. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) -{ - letimer->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more LETIMER interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * LETIMER_IntClear() prior to enabling the interrupt. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) -{ - letimer->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending LETIMER interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @return - * LETIMER interrupt sources pending. A bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) -{ - return letimer->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending LETIMER interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @return - * Pending and enabled LETIMER interrupt sources. - * Return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn - * register (LETIMER_IEN_nnn) and - * - the OR combination of valid interrupt flags of the LETIMER module - * (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) -{ - uint32_t ien; - - /* Store flags in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = letimer->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return letimer->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending LETIMER interrupts from SW. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to set to pending. Use a bitwise logic OR - * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) -{ -#if defined (LETIMER_HAS_SET_CLEAR) - letimer->IF_SET = flags; -#else - letimer->IFS = flags; -#endif -} - -#if defined(_LETIMER_LOCK_MASK) -/***************************************************************************//** - * @brief - * Lock LETIMER registers. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @note When LETIMER registers are locked LETIMER_EN, LETIMER_SWRST, - * LETIMER_CTRL, LETIMER_CMD, LETIMER_CNT, LETIMER_COMPx, - * LETIMER_TOP, LETIMER_TOPBUFF, LETIMER_REPx, and PRSMODE registers - * cannot be written to. - ******************************************************************************/ -__STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer) -{ - letimer->LOCK = ~LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; -} -#endif - -#if defined(_LETIMER_LOCK_MASK) -/***************************************************************************//** - * @brief - * Unlock LETIMER registers. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void LETIMER_Unlock(LETIMER_TypeDef *letimer) -{ - letimer->LOCK = LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; -} -#endif - -uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); -void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, - unsigned int rep, - uint32_t value); -void LETIMER_Reset(LETIMER_TypeDef *letimer); -void LETIMER_SyncWait(LETIMER_TypeDef *letimer); -void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); -uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer); - -/** @} (end addtogroup letimer) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ -#endif /* EM_LETIMER_H */ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LETIMER_H +#define EM_LETIMER_H + +#include +#include "em_device.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup letimer + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Repeat mode. */ +typedef enum { + /** Count until stopped by SW. */ + letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, + /** Count REP0 times. */ + letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, + /** + * Count REP0 times, if REP1 has been written to, it is loaded into + * REP0 when REP0 is about to be decremented to 0. + */ + letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, + /** + * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 + * are decremented when counter underflows. + */ + letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE +} LETIMER_RepeatMode_TypeDef; + +/** Underflow action on output. */ +typedef enum { + /** No output action. */ + letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, + /** Toggle output when counter underflows. */ + letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, + /** Hold output one LETIMER clock cycle when counter underflows. */ + letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, + /** Set output idle when counter underflows, and active when matching COMP1. */ + letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM +} LETIMER_UFOA_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LETIMER initialization structure. */ +typedef struct { + bool enable; /**< Start counting when initialization completes. */ + bool debugRun; /**< Counter shall keep running during debug halt. */ +#if defined(LETIMER_CTRL_RTCC0TEN) + bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ + bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ +#endif + bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ + bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ + uint8_t out0Pol; /**< Idle value for output 0. */ + uint8_t out1Pol; /**< Idle value for output 1. */ + LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ + LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ + LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ + uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ +} LETIMER_Init_TypeDef; + +/** Default configuration for LETIMER initialization structure. */ +#if defined(LETIMER_CTRL_RTCC0TEN) +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not start counting on RTC COMP0 match. */ \ + false, /* Do not start counting on RTC COMP1 match. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#else +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value); +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer); +#if !defined(_EFM32_GECKO_FAMILY) +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value); +#endif + +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); +#if defined(_LETIMER_FREEZE_MASK) +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); +#endif +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * Pending LETIMER interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_CLR = flags; +#else + letimer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LETIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LETIMER_IntClear() prior to enabling the interrupt. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LETIMER interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * LETIMER interrupt sources pending. A bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) +{ + return letimer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LETIMER interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * Pending and enabled LETIMER interrupt sources. + * Return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn + * register (LETIMER_IEN_nnn) and + * - the OR combination of valid interrupt flags of the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) +{ + uint32_t ien; + + /* Store flags in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = letimer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return letimer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LETIMER interrupts from SW. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_SET = flags; +#else + letimer->IFS = flags; +#endif +} + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Lock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @note When LETIMER registers are locked LETIMER_EN, LETIMER_SWRST, + * LETIMER_CTRL, LETIMER_CMD, LETIMER_CNT, LETIMER_COMPx, + * LETIMER_TOP, LETIMER_TOPBUFF, LETIMER_REPx, and PRSMODE registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = ~LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Unlock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Unlock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value); +void LETIMER_Reset(LETIMER_TypeDef *letimer); +void LETIMER_SyncWait(LETIMER_TypeDef *letimer); +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer); + +/** @} (end addtogroup letimer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ +#endif /* EM_LETIMER_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h index d7fe030..2ced370 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h @@ -1,882 +1,882 @@ -/***************************************************************************//** - * @file - * @brief Flash Controller (MSC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_MSC_H -#define EM_MSC_H - -#include "em_device.h" -#if defined(MSC_COUNT) && (MSC_COUNT > 0) - -#include -#include -#include "em_bus.h" -#include "em_msc_compat.h" -#include "em_ramfunc.h" -#include "sl_assert.h" - -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - #include "sli_tz_ns_interface.h" - #include "sli_tz_service_msc.h" - #include "sli_tz_s_interface.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup msc MSC - Memory System Controller - * @brief Memory System Controller API - * @details - * Contains functions to control the MSC, primarily the Flash. - * Users can perform Flash memory write and erase operations, as well as - * optimization of the CPU instruction fetch interface for the application. - * Available instruction fetch features depends on the MCU or SoC family, but - * features such as instruction pre-fetch, cache, and configurable branch prediction - * are typically available. - * - * @note Flash wait-state configuration is handled by @ref cmu. - * When core clock configuration is changed by a call to functions such as - * CMU_ClockSelectSet() or CMU_HFRCOBandSet(), then Flash wait-state - * configuration is also updated. - * - * MSC resets into a safe state. To initialize the instruction interface - * to recommended settings: - * @include em_msc_init_exec.c - * - * @note The optimal configuration is highly application dependent. Performance - * benchmarking is supported by most families. See MSC_StartCacheMeasurement() - * and MSC_GetCacheMeasurement() for more details. - * - * @note - * The flash write and erase runs from RAM on the EFM32G devices. On all other - * devices the flash write and erase functions run from flash. - * - * @note - * Flash erase may add ms of delay to interrupt latency if executing from Flash. - * - * Flash write and erase operations are supported by @ref MSC_WriteWord(), - * @ref MSC_ErasePage(), and MSC_MassErase(). - * Mass erase is supported for MCU and SoC families with larger Flash sizes. - * - * @note - * @ref MSC_Init() must be called prior to any Flash write or erase operation. - * - * The following steps are necessary to perform a page erase and write: - * @include em_msc_erase_write.c - * - * @deprecated - * The configuration called EM_MSC_RUN_FROM_FLASH is deprecated. This was - * previously used for allocating the flash write functions in either flash - * or RAM. - * - * @note - * The configuration EM_MSC_RUN_FROM_RAM is used to allocate the flash - * write functions in RAM. By default, flash write - * functions are placed in RAM on EFM32G and Series 2 devices - * unless SL_RAMFUNC_DISABLE is defined. For other devices, - * flash write functions are placed in FLASH by default unless - * EM_MSC_RUN_FROM_RAM is defined and SL_RAMFUNC_DISABLE is not defined. - * - * @deprecated - * The function called MSC_WriteWordFast() is deprecated. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************* DEFINES ***************************************** - ******************************************************************************/ - -/** - * @brief - * Timeout used while waiting for Flash to become ready after a write. - * This number indicates the number of iterations to perform before - * issuing a timeout. - * - * @note - * Timeout is set very large (in the order of 100x longer than - * necessary). This is to avoid any corner case. - */ -#define MSC_PROGRAM_TIMEOUT 10000000UL - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if (defined(_EFM32_GECKO_FAMILY) \ - || defined(_SILICON_LABS_32B_SERIES_2) \ - || defined(EM_MSC_RUN_FROM_RAM)) \ - && !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) -#define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR -#define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN -#define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END -#else -#define MSC_RAMFUNC_DECLARATOR -#define MSC_RAMFUNC_DEFINITION_BEGIN -#define MSC_RAMFUNC_DEFINITION_END -#endif -/** @endcond */ - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Return codes for writing/erasing Flash. */ -typedef enum { - mscReturnOk = 0, /**< Flash write/erase successful. */ - mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ - mscReturnLocked = -2, /**< Flash address is locked. */ - mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ - mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ -} MSC_Status_TypeDef; - -#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) -/** Strategy for prioritized bus access. */ -typedef enum { - mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ - mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ - mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ - mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ -} MSC_BusStrategy_Typedef; -#endif - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -/** AHBHOST masters that can use alternate MPAHBRAM ports. */ -typedef enum { - mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, - mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, - mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, - mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, - mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) - mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK) - mscDmemMasterMVPAHBDATA1 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK) - mscDmemMasterMVPAHBDATA2 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_MASK) - mscDmemMasterLDMA1 = _SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_MASK) - mscDmemMasterSRWLDMA = _SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_MASK) - mscDmemMasterUSB = _SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_MASK) - mscDmemMasterBUFC = _SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_SHIFT -#endif -} MSC_DmemMaster_TypeDef; -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -/** AHB port given priority. */ -typedef enum { - mscPortPriorityNone = _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE, - mscPortPriorityPort0 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0, - mscPortPriorityPort1 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1, -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2) - mscPortPriorityPort2 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2, -#endif -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3) - mscPortPriorityPort3 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3, -#endif -} MSC_PortPriority_TypeDef; -#endif - -#if defined(MSC_READCTRL_DOUTBUFEN) || defined(MSC_RDATACTRL_DOUTBUFEN) -/** Code execution configuration */ -typedef struct { - bool doutBufEn; /**< Flash dout pipeline buffer enable */ -} MSC_ExecConfig_TypeDef; - -/** Default MSC ExecConfig initialization */ -#define MSC_EXECCONFIG_DEFAULT \ - { \ - false, \ - } - -#else -/** Code execution configuration. */ -typedef struct { - bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ - bool prefetchEn; /**< Enable MSC prefetching. */ - bool ifcDis; /**< Disable instruction cache. */ - bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ - bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ - bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ -} MSC_ExecConfig_TypeDef; - -/** Default MSC ExecConfig initialization. */ -#define MSC_EXECCONFIG_DEFAULT \ - { \ - false, \ - true, \ - false, \ - false, \ - false, \ - false, \ - } -#endif - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) - -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) -/** EFM32GG11B incorporates 2 memory banks including ECC support. */ -#define MSC_ECC_BANKS (2) - -/** Default MSC EccConfig initialization. */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -/** EFM32GG12B incorporates 3 memory banks including ECC support. */ -#define MSC_ECC_BANKS (3) - -/** Default MSC EccConfig initialization. */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - -/** xG26 chips incorporate 2 memory banks including ECC support. */ -#define MSC_ECC_BANKS (2) -/** Default MSC EccConfig initialization */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) - -/** Series 2 chips incorporate 1 memory bank including ECC support. */ -#define MSC_ECC_BANKS (1) -/** Default MSC EccConfig initialization */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false }, \ - { 0, 1 }, \ - } - -#else -#error Device not supported. -#endif - -/** ECC configuration. */ -typedef struct { - bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable - Error Correcting Code (ECC) for - each RAM bank that supports ECC on - the device. */ - uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to - use for ECC initialization. */ -} MSC_EccConfig_TypeDef; - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated type names. */ -#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef -#define msc_Return_TypeDef MSC_Status_TypeDef -/** @endcond */ - -/******************************************************************************* - ************************* Inline Functions ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the status of the MSC register lock. - * - * @return - * Boolean true if register lock is applied, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool MSC_LockGetLocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return (bool)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_LOCKED_SID); -#elif defined(_MSC_STATUS_REGLOCK_MASK) - return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; -#else - return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED; -#endif -} - -/***************************************************************************//** - * @brief - * Set the MSC register lock to a locked state. - ******************************************************************************/ -__STATIC_INLINE void MSC_LockSetLocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_SET_LOCKED_SID); -#else - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; -#endif -} - -/***************************************************************************//** - * @brief - * Set the MSC register lock to an unlocked state. - ******************************************************************************/ -__STATIC_INLINE void MSC_LockSetUnlocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_SET_UNLOCKED_SID); -#else - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; -#endif -} - -/***************************************************************************//** - * @brief - * Get the current value of the read control register (MSC_READCTRL). - * - * @return - * The 32-bit value read from the MSC_READCTRL register. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_READCTRL_SID); -#else - return MSC->READCTRL; -#endif -} - -/***************************************************************************//** - * @brief - * Write a value to the read control register (MSC_READCTRL). - * - * @param[in] value - * The 32-bit value to write to the MSC_READCTRL register. - ******************************************************************************/ -__STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_READCTRL_SID, - value); -#else - MSC->READCTRL = value; -#endif -} - -#if defined(_MSC_PAGELOCK0_MASK) || defined(_MSC_INST_PAGELOCKWORD0_MASK) - -/***************************************************************************//** - * @brief - * Set the lockbit for a flash page in order to prevent page writes/erases to - * the corresponding page. - * - * @param[in] page_number - * The index of the page to apply the pagelock to. Must be in the range - * [0, (flash_size / page_size) - 1]. - ******************************************************************************/ -__STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_PAGELOCK_SID, - page_number); -#else - EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); - - #if defined(_MSC_PAGELOCK0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; - #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; - #endif - - pagelock_registers[page_number / 32] |= (1 << (page_number % 32)); -#endif -} - -/***************************************************************************//** - * @brief - * Get the value of the lockbit for a flash page. - * - * @param[in] page_number - * The index of the page to get the lockbit value from. Must be in the range - * [0, (flash_size / page_size) - 1]. - * - * @return - * Boolean true if the page is locked, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return (bool)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_GET_PAGELOCK_SID, - page_number); -#else - EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); - - #if defined(_MSC_PAGELOCK0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; - #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; - #endif - - return pagelock_registers[page_number / 32] & (1 << (page_number % 32)); -#endif -} - -#endif // _MSC_PAGELOCK0_MASK || _MSC_INST_PAGELOCKWORD0_MASK - -#if defined(_MSC_USERDATASIZE_MASK) - -/***************************************************************************//** - * @brief - * Get the size of the user data region in flash. - * - * @return - * The size of the user data region divided by 256. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_UserDataGetSize(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_USERDATA_SIZE_SID); -#else - return MSC->USERDATASIZE; -#endif -} - -#endif // _MSC_USERDATASIZE_MASK - -#if defined(_MSC_MISCLOCKWORD_MASK) - -/***************************************************************************//** - * @brief - * Get the current value of the mass erase and user data page lock word - * (MSC_MISCLOCKWORD). - * - * @return - * The 32-bit value read from the MSC_MISCLOCKWORD register. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_MISCLOCKWORD_SID); -#else - return MSC->MISCLOCKWORD; -#endif -} - -/***************************************************************************//** - * @brief - * Write a value to the mass erase and user data page lock word - * (MSC_MISCLOCKWORD). - * - * @param[in] value - * The 32-bit value to write to the MSC_MISCLOCKWORD register. - ******************************************************************************/ -__STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_MISCLOCKWORD_SID, - value); -#else - MSC->MISCLOCKWORD = value; -#endif -} - -#endif // _MSC_USERDATASIZE_MASK - -#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - -/***************************************************************************//** - * @brief - * Clear one or more pending MSC interrupts. - * - * @param[in] flags - * Pending MSC interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntClear(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IF_CLR = flags; -#else - MSC->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more MSC interrupts. - * - * @param[in] flags - * MSC interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntDisable(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IEN_CLR = flags; -#else - MSC->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more MSC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * MSC_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * MSC interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntEnable(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IEN_SET = flags; -#else - MSC->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending MSC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * MSC interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_IntGet(void) -{ - return MSC->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending MSC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled MSC interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in MSC_IEN and - * - the pending interrupt flags MSC_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_IntGetEnabled(void) -{ - uint32_t ien; - - ien = MSC->IEN; - return MSC->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending MSC interrupts from SW. - * - * @param[in] flags - * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntSet(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IF_SET = flags; -#else - MSC->IFS = flags; -#endif -} - -#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) -/***************************************************************************//** - * @brief - * Start measuring the cache hit ratio. - * @details - * Starts performance counters. It is defined inline to - * minimize the impact of this code on the measurement itself. - ******************************************************************************/ -__STATIC_INLINE void MSC_StartCacheMeasurement(void) -{ - /* Clear CMOF and CHOF to catch these later. */ - MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; - - /* Start performance counters. */ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_STARTPC; -#else - MSC->CMD = MSC_CMD_STARTPC; -#endif -} - -/***************************************************************************//** - * @brief - * Stop measuring the hit rate. - * @note - * Defined inline to minimize the impact of this - * code on the measurement itself. - * Only works for relatively short sections of code. - * To measure longer sections of code, implement an IRQ Handler for - * the CHOF and CMOF overflow interrupts. These overflows need to be - * counted and included in the total. - * Functions can then be implemented as follows: - * @verbatim - * volatile uint32_t hitOverflows - * volatile uint32_t missOverflows - * - * void MSC_IRQHandler(void) - * { - * uint32_t flags; - * flags = MSC->IF; - * if (flags & MSC_IF_CHOF) { - * MSC->IFC = MSC_IF_CHOF; - * hitOverflows++; - * } - * if (flags & MSC_IF_CMOF) { - * MSC->IFC = MSC_IF_CMOF; - * missOverflows++; - * } - * } - * - * void startPerformanceCounters(void) - * { - * hitOverflows = 0; - * missOverflows = 0; - * - * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); - * NVIC_EnableIRQ(MSC_IRQn); - * - * MSC_StartCacheMeasurement(); - * } - * @endverbatim - * @return - * Returns -1 if there has been no cache accesses. - * Returns -2 if there has been an overflow in the performance counters. - * If not, it will return the percentage of hits versus misses. - ******************************************************************************/ -__STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) -{ - int32_t total; - int32_t hits; - /* Stop counter before computing hit-rate. */ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_STOPPC; -#else - MSC->CMD = MSC_CMD_STOPPC; -#endif - - /* Check for overflows in performance counters. */ - if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { - return -2; - } - - hits = (int32_t)MSC->CACHEHITS; - total = (int32_t)MSC->CACHEMISSES + hits; - - /* To avoid a division by zero. */ - if (total == 0) { - return -1; - } - - return (hits * 100) / total; -} - -/***************************************************************************//** - * @brief - * Flush contents of instruction cache. - ******************************************************************************/ -__STATIC_INLINE void MSC_FlushCache(void) -{ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_INVCACHE; -#else - MSC->CMD = MSC_CMD_INVCACHE; -#endif -} - -/***************************************************************************//** - * @brief - * Enable or disable instruction cache functionality. - * @param[in] enable - * Enable instruction cache. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableCache(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); -} - -#if defined(MSC_READCTRL_ICCDIS) -/***************************************************************************//** - * @brief - * Enable or disable instruction cache functionality in IRQs. - * @param[in] enable - * Enable instruction cache. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); -} -#endif - -/***************************************************************************//** - * @brief - * Enable or disable instruction cache flushing when writing to flash. - * @param[in] enable - * Enable automatic cache flushing. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); -} -#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ - -#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) -/***************************************************************************//** - * @brief - * Configure which unit should get priority on system bus. - * @param[in] mode - * Unit to prioritize bus accesses for. - ******************************************************************************/ -__STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) -{ - MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; -} -#endif - -/******************************************************************************* - ************************* PROTOTYPES ************************************** - ******************************************************************************/ - -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); -#endif - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port); -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority); -MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void); -#endif - -#if !defined(_SILICON_LABS_32B_SERIES_2) -/* Note that this function is deprecated because we no longer support - * placing msc code in ram. */ -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, - void const *data, - uint32_t numBytes); -#endif - -#if defined(MSC_WRITECMD_ERASEMAIN0) -/***************************************************************************//** - * @brief - * Erase the entire Flash in one operation. - * - * @note - * This command will erase the entire contents of the device. - * Use with care, both a debug session and all contents of the flash will be - * lost. The lock bit, MLW will prevent this operation from executing and - * might prevent a successful mass erase. - * - * @return - * Returns the status of the operation. - ******************************************************************************/ -SL_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_MassErase(void); -#endif - -#endif /* !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT */ - -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); - -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes); - -#if (_SILICON_LABS_32B_SERIES > 0) -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes); -#endif - -void MSC_Init(void); -void MSC_Deinit(void); - -/** @} (end addtogroup msc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ -#endif /* EM_MSC_H */ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_H +#define EM_MSC_H + +#include "em_device.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include +#include +#include "em_bus.h" +#include "em_msc_compat.h" +#include "em_ramfunc.h" +#include "sl_assert.h" + +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + #include "sli_tz_ns_interface.h" + #include "sli_tz_service_msc.h" + #include "sli_tz_s_interface.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup msc MSC - Memory System Controller + * @brief Memory System Controller API + * @details + * Contains functions to control the MSC, primarily the Flash. + * Users can perform Flash memory write and erase operations, as well as + * optimization of the CPU instruction fetch interface for the application. + * Available instruction fetch features depends on the MCU or SoC family, but + * features such as instruction pre-fetch, cache, and configurable branch prediction + * are typically available. + * + * @note Flash wait-state configuration is handled by @ref cmu. + * When core clock configuration is changed by a call to functions such as + * CMU_ClockSelectSet() or CMU_HFRCOBandSet(), then Flash wait-state + * configuration is also updated. + * + * MSC resets into a safe state. To initialize the instruction interface + * to recommended settings: + * @include em_msc_init_exec.c + * + * @note The optimal configuration is highly application dependent. Performance + * benchmarking is supported by most families. See MSC_StartCacheMeasurement() + * and MSC_GetCacheMeasurement() for more details. + * + * @note + * The flash write and erase runs from RAM on the EFM32G devices. On all other + * devices the flash write and erase functions run from flash. + * + * @note + * Flash erase may add ms of delay to interrupt latency if executing from Flash. + * + * Flash write and erase operations are supported by @ref MSC_WriteWord(), + * @ref MSC_ErasePage(), and MSC_MassErase(). + * Mass erase is supported for MCU and SoC families with larger Flash sizes. + * + * @note + * @ref MSC_Init() must be called prior to any Flash write or erase operation. + * + * The following steps are necessary to perform a page erase and write: + * @include em_msc_erase_write.c + * + * @deprecated + * The configuration called EM_MSC_RUN_FROM_FLASH is deprecated. This was + * previously used for allocating the flash write functions in either flash + * or RAM. + * + * @note + * The configuration EM_MSC_RUN_FROM_RAM is used to allocate the flash + * write functions in RAM. By default, flash write + * functions are placed in RAM on EFM32G and Series 2 devices + * unless SL_RAMFUNC_DISABLE is defined. For other devices, + * flash write functions are placed in FLASH by default unless + * EM_MSC_RUN_FROM_RAM is defined and SL_RAMFUNC_DISABLE is not defined. + * + * @deprecated + * The function called MSC_WriteWordFast() is deprecated. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************* DEFINES ***************************************** + ******************************************************************************/ + +/** + * @brief + * Timeout used while waiting for Flash to become ready after a write. + * This number indicates the number of iterations to perform before + * issuing a timeout. + * + * @note + * Timeout is set very large (in the order of 100x longer than + * necessary). This is to avoid any corner case. + */ +#define MSC_PROGRAM_TIMEOUT 10000000UL + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if (defined(_EFM32_GECKO_FAMILY) \ + || defined(_SILICON_LABS_32B_SERIES_2) \ + || defined(EM_MSC_RUN_FROM_RAM)) \ + && !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +#else +#define MSC_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END +#endif +/** @endcond */ + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Return codes for writing/erasing Flash. */ +typedef enum { + mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ + mscReturnLocked = -2, /**< Flash address is locked. */ + mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ + mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ +} MSC_Status_TypeDef; + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/** Strategy for prioritized bus access. */ +typedef enum { + mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ + mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ + mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ + mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ +} MSC_BusStrategy_Typedef; +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/** AHBHOST masters that can use alternate MPAHBRAM ports. */ +typedef enum { + mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, + mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, + mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, + mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, + mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) + mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK) + mscDmemMasterMVPAHBDATA1 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK) + mscDmemMasterMVPAHBDATA2 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_MASK) + mscDmemMasterLDMA1 = _SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_MASK) + mscDmemMasterSRWLDMA = _SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_MASK) + mscDmemMasterUSB = _SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_MASK) + mscDmemMasterBUFC = _SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_SHIFT +#endif +} MSC_DmemMaster_TypeDef; +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/** AHB port given priority. */ +typedef enum { + mscPortPriorityNone = _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE, + mscPortPriorityPort0 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0, + mscPortPriorityPort1 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1, +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2) + mscPortPriorityPort2 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2, +#endif +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3) + mscPortPriorityPort3 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3, +#endif +} MSC_PortPriority_TypeDef; +#endif + +#if defined(MSC_READCTRL_DOUTBUFEN) || defined(MSC_RDATACTRL_DOUTBUFEN) +/** Code execution configuration */ +typedef struct { + bool doutBufEn; /**< Flash dout pipeline buffer enable */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + } + +#else +/** Code execution configuration. */ +typedef struct { + bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ + bool prefetchEn; /**< Enable MSC prefetching. */ + bool ifcDis; /**< Disable instruction cache. */ + bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ + bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ + bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization. */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + true, \ + false, \ + false, \ + false, \ + false, \ + } +#endif + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/** EFM32GG11B incorporates 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/** EFM32GG12B incorporates 3 memory banks including ECC support. */ +#define MSC_ECC_BANKS (3) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + +/** xG26 chips incorporate 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +/** Series 2 chips incorporate 1 memory bank including ECC support. */ +#define MSC_ECC_BANKS (1) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false }, \ + { 0, 1 }, \ + } + +#else +#error Device not supported. +#endif + +/** ECC configuration. */ +typedef struct { + bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable + Error Correcting Code (ECC) for + each RAM bank that supports ECC on + the device. */ + uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to + use for ECC initialization. */ +} MSC_EccConfig_TypeDef; + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated type names. */ +#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef +#define msc_Return_TypeDef MSC_Status_TypeDef +/** @endcond */ + +/******************************************************************************* + ************************* Inline Functions ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the status of the MSC register lock. + * + * @return + * Boolean true if register lock is applied, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_LockGetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_LOCKED_SID); +#elif defined(_MSC_STATUS_REGLOCK_MASK) + return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; +#else + return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to a locked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_LOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to an unlocked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetUnlocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_UNLOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the current value of the read control register (MSC_READCTRL). + * + * @return + * The 32-bit value read from the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_READCTRL_SID); +#else + return MSC->READCTRL; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the read control register (MSC_READCTRL). + * + * @param[in] value + * The 32-bit value to write to the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_READCTRL_SID, + value); +#else + MSC->READCTRL = value; +#endif +} + +#if defined(_MSC_PAGELOCK0_MASK) || defined(_MSC_INST_PAGELOCKWORD0_MASK) + +/***************************************************************************//** + * @brief + * Set the lockbit for a flash page in order to prevent page writes/erases to + * the corresponding page. + * + * @param[in] page_number + * The index of the page to apply the pagelock to. Must be in the range + * [0, (flash_size / page_size) - 1]. + ******************************************************************************/ +__STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + pagelock_registers[page_number / 32] |= (1 << (page_number % 32)); +#endif +} + +/***************************************************************************//** + * @brief + * Get the value of the lockbit for a flash page. + * + * @param[in] page_number + * The index of the page to get the lockbit value from. Must be in the range + * [0, (flash_size / page_size) - 1]. + * + * @return + * Boolean true if the page is locked, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_GET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + return pagelock_registers[page_number / 32] & (1 << (page_number % 32)); +#endif +} + +#endif // _MSC_PAGELOCK0_MASK || _MSC_INST_PAGELOCKWORD0_MASK + +#if defined(_MSC_USERDATASIZE_MASK) + +/***************************************************************************//** + * @brief + * Get the size of the user data region in flash. + * + * @return + * The size of the user data region divided by 256. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_UserDataGetSize(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_USERDATA_SIZE_SID); +#else + return MSC->USERDATASIZE; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if defined(_MSC_MISCLOCKWORD_MASK) + +/***************************************************************************//** + * @brief + * Get the current value of the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @return + * The 32-bit value read from the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_MISCLOCKWORD_SID); +#else + return MSC->MISCLOCKWORD; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @param[in] value + * The 32-bit value to write to the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_MISCLOCKWORD_SID, + value); +#else + MSC->MISCLOCKWORD = value; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + +/***************************************************************************//** + * @brief + * Clear one or more pending MSC interrupts. + * + * @param[in] flags + * Pending MSC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntClear(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_CLR = flags; +#else + MSC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more MSC interrupts. + * + * @param[in] flags + * MSC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntDisable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_CLR = flags; +#else + MSC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more MSC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * MSC_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * MSC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntEnable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_SET = flags; +#else + MSC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending MSC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * MSC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGet(void) +{ + return MSC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending MSC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled MSC interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in MSC_IEN and + * - the pending interrupt flags MSC_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGetEnabled(void) +{ + uint32_t ien; + + ien = MSC->IEN; + return MSC->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending MSC interrupts from SW. + * + * @param[in] flags + * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntSet(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_SET = flags; +#else + MSC->IFS = flags; +#endif +} + +#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) +/***************************************************************************//** + * @brief + * Start measuring the cache hit ratio. + * @details + * Starts performance counters. It is defined inline to + * minimize the impact of this code on the measurement itself. + ******************************************************************************/ +__STATIC_INLINE void MSC_StartCacheMeasurement(void) +{ + /* Clear CMOF and CHOF to catch these later. */ + MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; + + /* Start performance counters. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STARTPC; +#else + MSC->CMD = MSC_CMD_STARTPC; +#endif +} + +/***************************************************************************//** + * @brief + * Stop measuring the hit rate. + * @note + * Defined inline to minimize the impact of this + * code on the measurement itself. + * Only works for relatively short sections of code. + * To measure longer sections of code, implement an IRQ Handler for + * the CHOF and CMOF overflow interrupts. These overflows need to be + * counted and included in the total. + * Functions can then be implemented as follows: + * @verbatim + * volatile uint32_t hitOverflows + * volatile uint32_t missOverflows + * + * void MSC_IRQHandler(void) + * { + * uint32_t flags; + * flags = MSC->IF; + * if (flags & MSC_IF_CHOF) { + * MSC->IFC = MSC_IF_CHOF; + * hitOverflows++; + * } + * if (flags & MSC_IF_CMOF) { + * MSC->IFC = MSC_IF_CMOF; + * missOverflows++; + * } + * } + * + * void startPerformanceCounters(void) + * { + * hitOverflows = 0; + * missOverflows = 0; + * + * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); + * NVIC_EnableIRQ(MSC_IRQn); + * + * MSC_StartCacheMeasurement(); + * } + * @endverbatim + * @return + * Returns -1 if there has been no cache accesses. + * Returns -2 if there has been an overflow in the performance counters. + * If not, it will return the percentage of hits versus misses. + ******************************************************************************/ +__STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) +{ + int32_t total; + int32_t hits; + /* Stop counter before computing hit-rate. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STOPPC; +#else + MSC->CMD = MSC_CMD_STOPPC; +#endif + + /* Check for overflows in performance counters. */ + if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { + return -2; + } + + hits = (int32_t)MSC->CACHEHITS; + total = (int32_t)MSC->CACHEMISSES + hits; + + /* To avoid a division by zero. */ + if (total == 0) { + return -1; + } + + return (hits * 100) / total; +} + +/***************************************************************************//** + * @brief + * Flush contents of instruction cache. + ******************************************************************************/ +__STATIC_INLINE void MSC_FlushCache(void) +{ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#else + MSC->CMD = MSC_CMD_INVCACHE; +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCache(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); +} + +#if defined(MSC_READCTRL_ICCDIS) +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality in IRQs. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); +} +#endif + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache flushing when writing to flash. + * @param[in] enable + * Enable automatic cache flushing. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); +} +#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/***************************************************************************//** + * @brief + * Configure which unit should get priority on system bus. + * @param[in] mode + * Unit to prioritize bus accesses for. + ******************************************************************************/ +__STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) +{ + MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; +} +#endif + +/******************************************************************************* + ************************* PROTOTYPES ************************************** + ******************************************************************************/ + +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port); +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority); +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void); +#endif + +#if !defined(_SILICON_LABS_32B_SERIES_2) +/* Note that this function is deprecated because we no longer support + * placing msc code in ram. */ +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes); +#endif + +#if defined(MSC_WRITECMD_ERASEMAIN0) +/***************************************************************************//** + * @brief + * Erase the entire Flash in one operation. + * + * @note + * This command will erase the entire contents of the device. + * Use with care, both a debug session and all contents of the flash will be + * lost. The lock bit, MLW will prevent this operation from executing and + * might prevent a successful mass erase. + * + * @return + * Returns the status of the operation. + ******************************************************************************/ +SL_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_MassErase(void); +#endif + +#endif /* !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT */ + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes); + +#if (_SILICON_LABS_32B_SERIES > 0) +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes); +#endif + +void MSC_Init(void); +void MSC_Deinit(void); + +/** @} (end addtogroup msc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ +#endif /* EM_MSC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h index d5044ba..77beeda 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h @@ -1,81 +1,81 @@ -/***************************************************************************//** - * @file - * @brief Flash Controller (MSC) Compatibility Header - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_MSC_COMPAT_H -#define EM_MSC_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define MSC_IF_PWROFFIF MSC_IF_PWROFF -#define _MSC_IF_PWROFFIF_SHIFT _MSC_IF_PWROFF_SHIFT -#define _MSC_IF_PWROFFIF_MASK _MSC_IF_PWROFF_MASK -#define _MSC_IF_PWROFFIF_DEFAULT _MSC_IF_PWROFF_DEFAULT -#define MSC_IF_PWROFFIF_DEFAULT MSC_IF_PWROFF_DEFAULT - -#define MSC_IEN_PWROFFIEN MSC_IEN_PWROFF -#define _MSC_IEN_PWROFFIEN_SHIFT _MSC_IEN_PWROFF_SHIFT -#define _MSC_IEN_PWROFFIEN_MASK _MSC_IEN_PWROFF_MASK -#define _MSC_IEN_PWROFFIEN_DEFAULT _MSC_IEN_PWROFF_DEFAULT -#define MSC_IEN_PWROFFIEN_DEFAULT MSC_IEN_PWROFF_DEFAULT - - -#define ICACHE_IEN_RAMERRORIEN ICACHE_IEN_RAMERROR -#define _ICACHE_IEN_RAMERRORIEN_SHIFT _ICACHE_IEN_RAMERROR_SHIFT -#define _ICACHE_IEN_RAMERRORIEN_MASK _ICACHE_IEN_RAMERROR_MASK -#define _ICACHE_IEN_RAMERRORIEN_DEFAULT _ICACHE_IEN_RAMERROR_DEFAULT -#define ICACHE_IEN_RAMERRORIEN_DEFAULT ICACHE_IEN_RAMERROR_DEFAULT - - -#define SYSCFG_IF_FRCRAMERR1BIF SYSCFG_IF_FRCRAMERR1B -#define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT _SYSCFG_IF_FRCRAMERR1B_SHIFT -#define _SYSCFG_IF_FRCRAMERR1BIF_MASK _SYSCFG_IF_FRCRAMERR1B_MASK -#define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT _SYSCFG_IF_FRCRAMERR1B_DEFAULT -#define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT SYSCFG_IF_FRCRAMERR1B_DEFAULT - -#define SYSCFG_IF_FRCRAMERR2BIF SYSCFG_IF_FRCRAMERR2B -#define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT _SYSCFG_IF_FRCRAMERR2B_SHIFT -#define _SYSCFG_IF_FRCRAMERR2BIF_MASK _SYSCFG_IF_FRCRAMERR2B_MASK -#define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT _SYSCFG_IF_FRCRAMERR2B_DEFAULT -#define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT SYSCFG_IF_FRCRAMERR2B_DEFAULT - -#define SYSCFG_IEN_FRCRAMERR1BIEN SYSCFG_IEN_FRCRAMERR1B -#define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR1B_SHIFT -#define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK _SYSCFG_IEN_FRCRAMERR1B_MASK -#define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR1B_DEFAULT -#define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR1B_DEFAULT - -#define SYSCFG_IEN_FRCRAMERR2BIEN SYSCFG_IEN_FRCRAMERR2B -#define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR2B_SHIFT -#define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK _SYSCFG_IEN_FRCRAMERR2B_MASK -#define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR2B_DEFAULT -#define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR2B_DEFAULT - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ -#endif /* EM_MSC_COMPAT_H */ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Compatibility Header + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_COMPAT_H +#define EM_MSC_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define MSC_IF_PWROFFIF MSC_IF_PWROFF +#define _MSC_IF_PWROFFIF_SHIFT _MSC_IF_PWROFF_SHIFT +#define _MSC_IF_PWROFFIF_MASK _MSC_IF_PWROFF_MASK +#define _MSC_IF_PWROFFIF_DEFAULT _MSC_IF_PWROFF_DEFAULT +#define MSC_IF_PWROFFIF_DEFAULT MSC_IF_PWROFF_DEFAULT + +#define MSC_IEN_PWROFFIEN MSC_IEN_PWROFF +#define _MSC_IEN_PWROFFIEN_SHIFT _MSC_IEN_PWROFF_SHIFT +#define _MSC_IEN_PWROFFIEN_MASK _MSC_IEN_PWROFF_MASK +#define _MSC_IEN_PWROFFIEN_DEFAULT _MSC_IEN_PWROFF_DEFAULT +#define MSC_IEN_PWROFFIEN_DEFAULT MSC_IEN_PWROFF_DEFAULT + + +#define ICACHE_IEN_RAMERRORIEN ICACHE_IEN_RAMERROR +#define _ICACHE_IEN_RAMERRORIEN_SHIFT _ICACHE_IEN_RAMERROR_SHIFT +#define _ICACHE_IEN_RAMERRORIEN_MASK _ICACHE_IEN_RAMERROR_MASK +#define _ICACHE_IEN_RAMERRORIEN_DEFAULT _ICACHE_IEN_RAMERROR_DEFAULT +#define ICACHE_IEN_RAMERRORIEN_DEFAULT ICACHE_IEN_RAMERROR_DEFAULT + + +#define SYSCFG_IF_FRCRAMERR1BIF SYSCFG_IF_FRCRAMERR1B +#define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT _SYSCFG_IF_FRCRAMERR1B_SHIFT +#define _SYSCFG_IF_FRCRAMERR1BIF_MASK _SYSCFG_IF_FRCRAMERR1B_MASK +#define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT _SYSCFG_IF_FRCRAMERR1B_DEFAULT +#define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT SYSCFG_IF_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IF_FRCRAMERR2BIF SYSCFG_IF_FRCRAMERR2B +#define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT _SYSCFG_IF_FRCRAMERR2B_SHIFT +#define _SYSCFG_IF_FRCRAMERR2BIF_MASK _SYSCFG_IF_FRCRAMERR2B_MASK +#define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT _SYSCFG_IF_FRCRAMERR2B_DEFAULT +#define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT SYSCFG_IF_FRCRAMERR2B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR1BIEN SYSCFG_IEN_FRCRAMERR1B +#define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR1B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK _SYSCFG_IEN_FRCRAMERR1B_MASK +#define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR1B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR2BIEN SYSCFG_IEN_FRCRAMERR2B +#define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR2B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK _SYSCFG_IEN_FRCRAMERR2B_MASK +#define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR2B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR2B_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ +#endif /* EM_MSC_COMPAT_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_opamp.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_opamp.h index 26f1e8b..82d9b4b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_opamp.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_opamp.h @@ -1,1459 +1,1459 @@ -/***************************************************************************//** - * @file - * @brief Operational Amplifier (OPAMP) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_OPAMP_H -#define EM_OPAMP_H - -#include "em_device.h" -#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ - || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(_SILICON_LABS_32B_SERIES_0) -#include "em_dac.h" -#elif defined (_SILICON_LABS_32B_SERIES_1) -#include "em_vdac.h" -#endif - -/***************************************************************************//** - * @addtogroup opamp - * @{ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of DAC OPA number for assert statements. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#define DAC_OPA_VALID(opa) ((opa) <= OPA2) -#elif defined(_SILICON_LABS_32B_SERIES_1) -#if defined(VDAC_STATUS_OPA3ENS) -#define VDAC_OPA_VALID(opa) ((opa) <= OPA3) -#elif defined(VDAC_STATUS_OPA2ENS) -#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) -#elif defined(VDAC_STATUS_OPA1ENS) -#define VDAC_OPA_VALID(opa) ((opa) <= OPA1) -#else -#define VDAC_OPA_VALID(opa) ((opa) = OPA0) -#endif -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** OPAMP selector values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS) - OPA0 = 0, /**< Select OPA0. */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS) - OPA1 = 1, /**< Select OPA1. */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS) - OPA2 = 2, /**< Select OPA2. */ -#endif -#if defined(VDAC_STATUS_OPA3ENS) - OPA3 = 3, /**< Select OPA3. */ -#endif -} OPAMP_TypeDef; - -/** OPAMP negative terminal input selection values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) - opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ - opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ - opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ - opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ - opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ - opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ - opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ - opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ - opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ - opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ - opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ - opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ - opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ - opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ - opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ - opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ - opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ - opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ - opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ - opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ - opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ - opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ - opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ - opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ - opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ - opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ - opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ - opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ - opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ - opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ - opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ - opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ - opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ - opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ - opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ - opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ - opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ - opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ - opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ - opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ - opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ - opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ - opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ - opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ - opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ - opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ - opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ - opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ - opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ - opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ - opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ - opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ - opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ - opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ - opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ - opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ - opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ - opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ - opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ - opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ - opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ - opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ - opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ - opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ - opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ - opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ - opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ - opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ - opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ - opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ - opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ -} OPAMP_NegSel_TypeDef; - -/** OPAMP positive terminal input selection values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) - opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ - opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ - opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ - opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ - opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ - opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ - opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ - opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ - opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ - opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ - opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ - opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ - opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ - opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ - opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ - opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ - opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ - opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ - opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ - opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ - opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ - opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ - opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ - opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ - opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ - opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ - opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ - opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ - opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ - opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ - opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ - opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ - opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ - opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ - opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ - opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ - opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ - opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ - opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ - opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ - opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ - opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ - opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ - opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ - opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ - opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ - opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ - opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ - opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ - opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ - opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ - opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ - opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ - opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ - opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ - opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ - opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ - opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ - opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ - opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ - opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ - opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ - opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ - opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ - opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ - opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ - opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ - opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ - opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ - opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ - opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ - opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ - opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ -} OPAMP_PosSel_TypeDef; - -/** OPAMP output terminal selection values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) - opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ - opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ - opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ - opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - opaOutModeDisable = 0, /**< OPA output disabled. */ - opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ - opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ - opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ - opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ - opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ - opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ - opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ - opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ - opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ - opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ - opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ - opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ - opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ - opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ - opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ - opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ - opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ - opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ - opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ - opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ - opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ - opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ - opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ - opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ - opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ - opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ - opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ - opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ - opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ - opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ - opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ - opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ - opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ - opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ - opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ - opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ - opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ - opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ - opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ - opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ - opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ - opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ - opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ - opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ - opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ - opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ - opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ - opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ - opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ - opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ - opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ - opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ - opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ - opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ - opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ - opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ - opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ - opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ - opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ - opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ - opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ - opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ - opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ - opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ - opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ - opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ - opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ -} OPAMP_OutMode_TypeDef; - -/** OPAMP gain values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) - opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ - opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ - opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ - opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ - opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */ - opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ - opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ - opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ - opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ - opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ - opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ - opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ - opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ - opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ - opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ - opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ - opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ -} OPAMP_ResSel_TypeDef; - -/** OPAMP resistor ladder input selector values. */ -typedef enum { -#if defined(_SILICON_LABS_32B_SERIES_0) - opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ - opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ - opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ - opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ - opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ - opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ - opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ - opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ - opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. - Direct input to support common reference. */ - opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully - differential instrumentation amplifier. */ - opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ -} OPAMP_ResInMux_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_1) -/** OPAMP PRS Mode. */ -typedef enum { - opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ - opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP - warmup sequence. The end of the warmup sequence - is controlled by timeout settings in OPAxTIMER. */ - opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the - OPAMP warmup sequence. The end of the warmup - sequence is controlled by the edge of the pulse. */ -} OPAMP_PrsMode_TypeDef; - -/** OPAMP PRS Selection. */ -typedef enum { - opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ - opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ - opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ - opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ - opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ - opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ - opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ - opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ - opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ -#if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8) - opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ - opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ - opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ - opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ -#endif -} OPAMP_PrsSel_TypeDef; - -/** OPAMP PRS Output. */ -typedef enum { - opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ - opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ - opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ -} OPAMP_PrsOut_TypeDef; - -/** OPAMP Output Scaling. */ -typedef enum { - opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ - opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ - opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ -} OPAMP_OutScale_Typedef; - -/** OPAMP Drive Strength. */ -typedef enum { - opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ - opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive strength. */ - opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive strength. */ - opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive strength. */ - opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive strength. */ -} OPAMP_DrvStr_Typedef; -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** OPAMP init structure. */ -typedef struct { - OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */ - OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */ - OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */ - OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */ - OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ - uint32_t outPen; /**< Alternate output enable bit mask. This value - should consist one or more of the - @if DOXYDOC_P1_DEVICE - DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags - (defined in \_dac.h) OR'ed together. - @n @n - For OPA0: - @li DAC_OPA0MUX_OUTPEN_OUT0 - @li DAC_OPA0MUX_OUTPEN_OUT1 - @li DAC_OPA0MUX_OUTPEN_OUT2 - @li DAC_OPA0MUX_OUTPEN_OUT3 - @li DAC_OPA0MUX_OUTPEN_OUT4 - - For OPA1: - @li DAC_OPA1MUX_OUTPEN_OUT0 - @li DAC_OPA1MUX_OUTPEN_OUT1 - @li DAC_OPA1MUX_OUTPEN_OUT2 - @li DAC_OPA1MUX_OUTPEN_OUT3 - @li DAC_OPA1MUX_OUTPEN_OUT4 - - For OPA2: - @li DAC_OPA2MUX_OUTPEN_OUT0 - @li DAC_OPA2MUX_OUTPEN_OUT1 - - E.g: @n - init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | - DAC_OPA0MUX_OUTPEN_OUT2 | - DAC_OPA0MUX_OUTPEN_OUT4; - - @elseif DOXYDOC_P2_DEVICE - VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags - (defined in \_vdac.h) OR'ed together. - @n @n - @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 - @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 - @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 - @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 - @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 - - E.g: @n - init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | - VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | - VDAC_OPA_OUT_ALTOUTPADEN_OUT4; - @endif */ -#if defined(_SILICON_LABS_32B_SERIES_0) - uint32_t bias; /**< Set OPAMP bias current. */ - bool halfBias; /**< Divide OPAMP bias current by 2. */ - bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ - bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */ - bool nextOut; /**< Enable NEXTOUT signal source. */ - bool npEn; /**< Enable positive pad. */ - bool ppEn; /**< Enable negative pad. */ - bool shortInputs; /**< Short OPAMP input terminals. */ - bool hcmDisable; /**< Disable input rail-to-rail capability. */ - bool defaultOffset; /**< Use factory calibrated opamp offset value. */ - uint32_t offset; /**< Opamp offset value when @ref defaultOffset is - false. */ -#elif defined(_SILICON_LABS_32B_SERIES_1) - OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ - bool gain3xEn; /**< Enable 3x gain resistor ladder. */ - bool halfDrvStr; /**< Half or full output drive strength. */ - bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ - bool prsEn; /**< Enable PRS as OPAMP trigger. */ - OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ - OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ - OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ - bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ - bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ - uint32_t settleTime; /**< Number of clock cycles to drive the output. */ - uint32_t startupDly; /**< OPAx startup delay in microseconds. */ - bool hcmDisable; /**< Disable input rail-to-rail capability. */ - bool defaultOffsetN; /**< Use factory calibrated opamp inverting input - offset value. */ - uint32_t offsetN; /**< Opamp inverting input offset value when - @ref defaultOffsetN is false. */ - bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting - input offset value. */ - uint32_t offsetP; /**< Opamp non-inverting input offset value when - @ref defaultOffsetP is false. */ -#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ -} OPAMP_Init_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** Configuration of OPA0/1 in unity gain voltage follower mode. */ -#define OPA_INIT_UNITY_GAIN \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Resistor ladder disabled. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in unity gain voltage follower mode. */ -#define OPA_INIT_UNITY_GAIN_OPA2 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Resistor ladder disabled. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0/1 in non-inverting amplifier mode. */ -#define OPA_INIT_NON_INVERTING \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in non-inverting amplifier mode. */ -#define OPA_INIT_NON_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0/1 in inverting amplifier mode. */ -#define OPA_INIT_INVERTING \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - true, /* Negative pad enabled, used as signal input. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in inverting amplifier mode. */ -#define OPA_INIT_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - true, /* Negative pad enabled, used as signal input. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA1). */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA2). */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - false, /* Positive pad disabled. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - false, /* Positive pad disabled. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA0 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA1). */ \ - true, /* Negative pad enabled, used as signal input. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA2). */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in two-opamp differential driver mode. */ -#define OPA_INIT_DIFF_DRIVER_OPA0 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Resistor ladder disabled. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA1). */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in two-opamp differential driver mode. */ -#define OPA_INIT_DIFF_DRIVER_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal ground. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA0 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA2). */ \ - true, /* Negative pad enabled, used as signal ground. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA1 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeAll, /* Both main and alternate outputs. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Disable resistor ladder. */ \ - 0, /* No alternate outputs enabled. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - true, /* Pass output to next stage (OPA2). */ \ - false, /* Negative pad disabled. */ \ - true, /* Positive pad enabled, used as signal input. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA2 \ - { \ - opaNegSelResTap, /* Input from resistor ladder tap. */ \ - opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ - DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \ - _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ - _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ - false, /* No low pass filter on positive pad. */ \ - false, /* No low pass filter on negative pad. */ \ - false, /* No nextout output enabled. */ \ - false, /* Negative pad disabled. */ \ - false, /* Positive pad disabled. */ \ - false, /* No shorting of inputs. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use factory calibrated opamp offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_1) -/** Configuration of OPA in unity gain voltage follower mode. */ -#define OPA_INIT_UNITY_GAIN \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Resistor ladder disabled. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA in non-inverting amplifier mode. */ -#define OPA_INIT_NON_INVERTING \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA in inverting amplifier mode. */ -#define OPA_INIT_INVERTING \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA3 in cascaded non-inverting amplifier mode. */ -#define OPA_INIT_CASCADED_NON_INVERTING_OPA3 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelOpaIn, /* Positive input from OPA2NEXT output. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA0 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA2 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA3 in cascaded inverting amplifier mode. */ -#define OPA_INIT_CASCADED_INVERTING_OPA3 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in two-opamp differential driver mode. */ -#define OPA_INIT_DIFF_DRIVER_OPA0 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Resistor ladder disabled. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in two-opamp differential driver mode. */ -#define OPA_INIT_DIFF_DRIVER_OPA1 \ - { \ - opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA0 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA1 \ - { \ - opaNegSelUnityGain, /* Unity gain. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelDefault, /* Resistor ladder is not used. */ \ - opaResInMuxDisable, /* Disable resistor ladder. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA2 in three-opamp differential receiver mode. */ -#define OPA_INIT_DIFF_RECEIVER_OPA2 \ - { \ - opaNegSelResTap, /* Input from resistor ladder tap. */ \ - opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA3 in three+one opamp differential receiver mode. In this - configuration, OPA3 is a second single-ended output amplifier. */ -#define OPA_INIT_DIFF_RECEIVER_OPA3 \ - { \ - opaNegSelResTap, /* Input from resistor ladder tap. */ \ - opaPosSelResTap, /* Input from OPA2 resistor ladder tap. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ -#define OPA_INIT_INSTR_AMP_OPA0 \ - { \ - opaNegSelResTap, /* Input from resistor ladder tap. */ \ - opaPosSelPosPad, /* Positive input from pad. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ -#define OPA_INIT_INSTR_AMP_OPA1 \ - { \ - opaNegSelNegPad, /* Negative input from pad. */ \ - opaPosSelResTap, /* Input from resistor ladder tap. */ \ - opaOutModeMain, /* Main output enabled. */ \ - opaResSelR2eqR1, /* R2 = R1 */ \ - opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ - 0, /* No alternate outputs enabled. */ \ - opaDrvStrDefault, /* Default opamp operation mode. */ \ - false, /* Disable 3x gain setting. */ \ - false, /* Use full output drive strength. */ \ - false, /* Disable unity-gain bandwidth scaling. */ \ - false, /* Opamp triggered by OPAxEN. */ \ - opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ - opaPrsOutDefault, /* Default PRS output setting. */ \ - false, /* Bus mastering enabled on APORTX. */ \ - false, /* Bus mastering enabled on APORTY. */ \ - 3, /* 3 us settle time with default DrvStr. */ \ - 0, /* No startup delay. */ \ - false, /* Rail-to-rail input enabled. */ \ - true, /* Use calibrated inverting offset. */ \ - 0, /* Opamp offset value (not used). */ \ - true, /* Use calibrated non-inverting offset. */ \ - 0 /* Opamp offset value (not used). */ \ - } - -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) -void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); -void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); -#elif defined(_SILICON_LABS_32B_SERIES_1) -void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); -void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); -#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ - -/** @} (end addtogroup opamp) */ - -#ifdef __cplusplus -} -#endif - -#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) - || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ -#endif /* EM_OPAMP_H */ +/***************************************************************************//** + * @file + * @brief Operational Amplifier (OPAMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_OPAMP_H +#define EM_OPAMP_H + +#include "em_device.h" +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(_SILICON_LABS_32B_SERIES_0) +#include "em_dac.h" +#elif defined (_SILICON_LABS_32B_SERIES_1) +#include "em_vdac.h" +#endif + +/***************************************************************************//** + * @addtogroup opamp + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of DAC OPA number for assert statements. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define DAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(VDAC_STATUS_OPA3ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA3) +#elif defined(VDAC_STATUS_OPA2ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA2) +#elif defined(VDAC_STATUS_OPA1ENS) +#define VDAC_OPA_VALID(opa) ((opa) <= OPA1) +#else +#define VDAC_OPA_VALID(opa) ((opa) = OPA0) +#endif +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** OPAMP selector values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA0ENS) + OPA0 = 0, /**< Select OPA0. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA1ENS) + OPA1 = 1, /**< Select OPA1. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(VDAC_STATUS_OPA2ENS) + OPA2 = 2, /**< Select OPA2. */ +#endif +#if defined(VDAC_STATUS_OPA3ENS) + OPA3 = 3, /**< Select OPA3. */ +#endif +} OPAMP_TypeDef; + +/** OPAMP negative terminal input selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaNegSelDisable = DAC_OPA0MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = DAC_OPA0MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = DAC_OPA0MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = DAC_OPA0MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaNegSelAPORT1YCH1 = VDAC_OPA_MUX_NEGSEL_APORT1YCH1, /**< APORT1YCH1 */ + opaNegSelAPORT1YCH3 = VDAC_OPA_MUX_NEGSEL_APORT1YCH3, /**< APORT1YCH3 */ + opaNegSelAPORT1YCH5 = VDAC_OPA_MUX_NEGSEL_APORT1YCH5, /**< APORT1YCH5 */ + opaNegSelAPORT1YCH7 = VDAC_OPA_MUX_NEGSEL_APORT1YCH7, /**< APORT1YCH7 */ + opaNegSelAPORT1YCH9 = VDAC_OPA_MUX_NEGSEL_APORT1YCH9, /**< APORT1YCH9 */ + opaNegSelAPORT1YCH11 = VDAC_OPA_MUX_NEGSEL_APORT1YCH11, /**< APORT1YCH11 */ + opaNegSelAPORT1YCH13 = VDAC_OPA_MUX_NEGSEL_APORT1YCH13, /**< APORT1YCH13 */ + opaNegSelAPORT1YCH15 = VDAC_OPA_MUX_NEGSEL_APORT1YCH15, /**< APORT1YCH15 */ + opaNegSelAPORT1YCH17 = VDAC_OPA_MUX_NEGSEL_APORT1YCH17, /**< APORT1YCH17 */ + opaNegSelAPORT1YCH19 = VDAC_OPA_MUX_NEGSEL_APORT1YCH19, /**< APORT1YCH19 */ + opaNegSelAPORT1YCH21 = VDAC_OPA_MUX_NEGSEL_APORT1YCH21, /**< APORT1YCH21 */ + opaNegSelAPORT1YCH23 = VDAC_OPA_MUX_NEGSEL_APORT1YCH23, /**< APORT1YCH23 */ + opaNegSelAPORT1YCH25 = VDAC_OPA_MUX_NEGSEL_APORT1YCH25, /**< APORT1YCH25 */ + opaNegSelAPORT1YCH27 = VDAC_OPA_MUX_NEGSEL_APORT1YCH27, /**< APORT1YCH27 */ + opaNegSelAPORT1YCH29 = VDAC_OPA_MUX_NEGSEL_APORT1YCH29, /**< APORT1YCH29 */ + opaNegSelAPORT1YCH31 = VDAC_OPA_MUX_NEGSEL_APORT1YCH31, /**< APORT1YCH31 */ + opaNegSelAPORT2YCH0 = VDAC_OPA_MUX_NEGSEL_APORT2YCH0, /**< APORT2YCH0 */ + opaNegSelAPORT2YCH2 = VDAC_OPA_MUX_NEGSEL_APORT2YCH2, /**< APORT2YCH2 */ + opaNegSelAPORT2YCH4 = VDAC_OPA_MUX_NEGSEL_APORT2YCH4, /**< APORT2YCH4 */ + opaNegSelAPORT2YCH6 = VDAC_OPA_MUX_NEGSEL_APORT2YCH6, /**< APORT2YCH6 */ + opaNegSelAPORT2YCH8 = VDAC_OPA_MUX_NEGSEL_APORT2YCH8, /**< APORT2YCH8 */ + opaNegSelAPORT2YCH10 = VDAC_OPA_MUX_NEGSEL_APORT2YCH10, /**< APORT2YCH10 */ + opaNegSelAPORT2YCH12 = VDAC_OPA_MUX_NEGSEL_APORT2YCH12, /**< APORT2YCH12 */ + opaNegSelAPORT2YCH14 = VDAC_OPA_MUX_NEGSEL_APORT2YCH14, /**< APORT2YCH14 */ + opaNegSelAPORT2YCH16 = VDAC_OPA_MUX_NEGSEL_APORT2YCH16, /**< APORT2YCH16 */ + opaNegSelAPORT2YCH18 = VDAC_OPA_MUX_NEGSEL_APORT2YCH18, /**< APORT2YCH18 */ + opaNegSelAPORT2YCH20 = VDAC_OPA_MUX_NEGSEL_APORT2YCH20, /**< APORT2YCH20 */ + opaNegSelAPORT2YCH22 = VDAC_OPA_MUX_NEGSEL_APORT2YCH22, /**< APORT2YCH22 */ + opaNegSelAPORT2YCH24 = VDAC_OPA_MUX_NEGSEL_APORT2YCH24, /**< APORT2YCH24 */ + opaNegSelAPORT2YCH26 = VDAC_OPA_MUX_NEGSEL_APORT2YCH26, /**< APORT2YCH26 */ + opaNegSelAPORT2YCH28 = VDAC_OPA_MUX_NEGSEL_APORT2YCH28, /**< APORT2YCH28 */ + opaNegSelAPORT2YCH30 = VDAC_OPA_MUX_NEGSEL_APORT2YCH30, /**< APORT2YCH30 */ + opaNegSelAPORT3YCH1 = VDAC_OPA_MUX_NEGSEL_APORT3YCH1, /**< APORT3YCH1 */ + opaNegSelAPORT3YCH3 = VDAC_OPA_MUX_NEGSEL_APORT3YCH3, /**< APORT3YCH3 */ + opaNegSelAPORT3YCH5 = VDAC_OPA_MUX_NEGSEL_APORT3YCH5, /**< APORT3YCH5 */ + opaNegSelAPORT3YCH7 = VDAC_OPA_MUX_NEGSEL_APORT3YCH7, /**< APORT3YCH7 */ + opaNegSelAPORT3YCH9 = VDAC_OPA_MUX_NEGSEL_APORT3YCH9, /**< APORT3YCH9 */ + opaNegSelAPORT3YCH11 = VDAC_OPA_MUX_NEGSEL_APORT3YCH11, /**< APORT3YCH11 */ + opaNegSelAPORT3YCH13 = VDAC_OPA_MUX_NEGSEL_APORT3YCH13, /**< APORT3YCH13 */ + opaNegSelAPORT3YCH15 = VDAC_OPA_MUX_NEGSEL_APORT3YCH15, /**< APORT3YCH15 */ + opaNegSelAPORT3YCH17 = VDAC_OPA_MUX_NEGSEL_APORT3YCH17, /**< APORT3YCH17 */ + opaNegSelAPORT3YCH19 = VDAC_OPA_MUX_NEGSEL_APORT3YCH19, /**< APORT3YCH19 */ + opaNegSelAPORT3YCH21 = VDAC_OPA_MUX_NEGSEL_APORT3YCH21, /**< APORT3YCH21 */ + opaNegSelAPORT3YCH23 = VDAC_OPA_MUX_NEGSEL_APORT3YCH23, /**< APORT3YCH23 */ + opaNegSelAPORT3YCH25 = VDAC_OPA_MUX_NEGSEL_APORT3YCH25, /**< APORT3YCH25 */ + opaNegSelAPORT3YCH27 = VDAC_OPA_MUX_NEGSEL_APORT3YCH27, /**< APORT3YCH27 */ + opaNegSelAPORT3YCH29 = VDAC_OPA_MUX_NEGSEL_APORT3YCH29, /**< APORT3YCH29 */ + opaNegSelAPORT3YCH31 = VDAC_OPA_MUX_NEGSEL_APORT3YCH31, /**< APORT3YCH31 */ + opaNegSelAPORT4YCH0 = VDAC_OPA_MUX_NEGSEL_APORT4YCH0, /**< APORT4YCH0 */ + opaNegSelAPORT4YCH2 = VDAC_OPA_MUX_NEGSEL_APORT4YCH2, /**< APORT4YCH2 */ + opaNegSelAPORT4YCH4 = VDAC_OPA_MUX_NEGSEL_APORT4YCH4, /**< APORT4YCH4 */ + opaNegSelAPORT4YCH6 = VDAC_OPA_MUX_NEGSEL_APORT4YCH6, /**< APORT4YCH6 */ + opaNegSelAPORT4YCH8 = VDAC_OPA_MUX_NEGSEL_APORT4YCH8, /**< APORT4YCH8 */ + opaNegSelAPORT4YCH10 = VDAC_OPA_MUX_NEGSEL_APORT4YCH10, /**< APORT4YCH10 */ + opaNegSelAPORT4YCH12 = VDAC_OPA_MUX_NEGSEL_APORT4YCH12, /**< APORT4YCH12 */ + opaNegSelAPORT4YCH14 = VDAC_OPA_MUX_NEGSEL_APORT4YCH14, /**< APORT4YCH14 */ + opaNegSelAPORT4YCH16 = VDAC_OPA_MUX_NEGSEL_APORT4YCH16, /**< APORT4YCH16 */ + opaNegSelAPORT4YCH18 = VDAC_OPA_MUX_NEGSEL_APORT4YCH18, /**< APORT4YCH18 */ + opaNegSelAPORT4YCH20 = VDAC_OPA_MUX_NEGSEL_APORT4YCH20, /**< APORT4YCH20 */ + opaNegSelAPORT4YCH22 = VDAC_OPA_MUX_NEGSEL_APORT4YCH22, /**< APORT4YCH22 */ + opaNegSelAPORT4YCH24 = VDAC_OPA_MUX_NEGSEL_APORT4YCH24, /**< APORT4YCH24 */ + opaNegSelAPORT4YCH26 = VDAC_OPA_MUX_NEGSEL_APORT4YCH26, /**< APORT4YCH26 */ + opaNegSelAPORT4YCH28 = VDAC_OPA_MUX_NEGSEL_APORT4YCH28, /**< APORT4YCH28 */ + opaNegSelAPORT4YCH30 = VDAC_OPA_MUX_NEGSEL_APORT4YCH30, /**< APORT4YCH30 */ + opaNegSelDisable = VDAC_OPA_MUX_NEGSEL_DISABLE, /**< Input disabled. */ + opaNegSelUnityGain = VDAC_OPA_MUX_NEGSEL_UG, /**< Unity gain feedback path. */ + opaNegSelResTap = VDAC_OPA_MUX_NEGSEL_OPATAP, /**< Feedback resistor ladder tap. */ + opaNegSelNegPad = VDAC_OPA_MUX_NEGSEL_NEGPAD /**< Negative pad as input. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_NegSel_TypeDef; + +/** OPAMP positive terminal input selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaPosSelDisable = DAC_OPA0MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = DAC_OPA0MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = DAC_OPA0MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = DAC_OPA0MUX_POSSEL_OPA0INP, /**< Input from OPAx. */ + opaPosSelResTapOpa0 = DAC_OPA0MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap from OPA0. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaPosSelAPORT1XCH0 = VDAC_OPA_MUX_POSSEL_APORT1XCH0, /**< APORT1XCH0 */ + opaPosSelAPORT1XCH2 = VDAC_OPA_MUX_POSSEL_APORT1XCH2, /**< APORT1XCH2 */ + opaPosSelAPORT1XCH4 = VDAC_OPA_MUX_POSSEL_APORT1XCH4, /**< APORT1XCH4 */ + opaPosSelAPORT1XCH6 = VDAC_OPA_MUX_POSSEL_APORT1XCH6, /**< APORT1XCH6 */ + opaPosSelAPORT1XCH8 = VDAC_OPA_MUX_POSSEL_APORT1XCH8, /**< APORT1XCH8 */ + opaPosSelAPORT1XCH10 = VDAC_OPA_MUX_POSSEL_APORT1XCH10, /**< APORT1XCH10 */ + opaPosSelAPORT1XCH12 = VDAC_OPA_MUX_POSSEL_APORT1XCH12, /**< APORT1XCH12 */ + opaPosSelAPORT1XCH14 = VDAC_OPA_MUX_POSSEL_APORT1XCH14, /**< APORT1XCH14 */ + opaPosSelAPORT1XCH16 = VDAC_OPA_MUX_POSSEL_APORT1XCH16, /**< APORT1XCH16 */ + opaPosSelAPORT1XCH18 = VDAC_OPA_MUX_POSSEL_APORT1XCH18, /**< APORT1XCH18 */ + opaPosSelAPORT1XCH20 = VDAC_OPA_MUX_POSSEL_APORT1XCH20, /**< APORT1XCH20 */ + opaPosSelAPORT1XCH22 = VDAC_OPA_MUX_POSSEL_APORT1XCH22, /**< APORT1XCH22 */ + opaPosSelAPORT1XCH24 = VDAC_OPA_MUX_POSSEL_APORT1XCH24, /**< APORT1XCH24 */ + opaPosSelAPORT1XCH26 = VDAC_OPA_MUX_POSSEL_APORT1XCH26, /**< APORT1XCH26 */ + opaPosSelAPORT1XCH28 = VDAC_OPA_MUX_POSSEL_APORT1XCH28, /**< APORT1XCH28 */ + opaPosSelAPORT1XCH30 = VDAC_OPA_MUX_POSSEL_APORT1XCH30, /**< APORT1XCH30 */ + opaPosSelAPORT2XCH1 = VDAC_OPA_MUX_POSSEL_APORT2XCH1, /**< APORT2XCH1 */ + opaPosSelAPORT2XCH3 = VDAC_OPA_MUX_POSSEL_APORT2XCH3, /**< APORT2XCH3 */ + opaPosSelAPORT2XCH5 = VDAC_OPA_MUX_POSSEL_APORT2XCH5, /**< APORT2XCH5 */ + opaPosSelAPORT2XCH7 = VDAC_OPA_MUX_POSSEL_APORT2XCH7, /**< APORT2XCH7 */ + opaPosSelAPORT2XCH9 = VDAC_OPA_MUX_POSSEL_APORT2XCH9, /**< APORT2XCH9 */ + opaPosSelAPORT2XCH11 = VDAC_OPA_MUX_POSSEL_APORT2XCH11, /**< APORT2XCH11 */ + opaPosSelAPORT2XCH13 = VDAC_OPA_MUX_POSSEL_APORT2XCH13, /**< APORT2XCH13 */ + opaPosSelAPORT2XCH15 = VDAC_OPA_MUX_POSSEL_APORT2XCH15, /**< APORT2XCH15 */ + opaPosSelAPORT2XCH17 = VDAC_OPA_MUX_POSSEL_APORT2XCH17, /**< APORT2XCH17 */ + opaPosSelAPORT2XCH19 = VDAC_OPA_MUX_POSSEL_APORT2XCH19, /**< APORT2XCH19 */ + opaPosSelAPORT2XCH21 = VDAC_OPA_MUX_POSSEL_APORT2XCH21, /**< APORT2XCH21 */ + opaPosSelAPORT2XCH23 = VDAC_OPA_MUX_POSSEL_APORT2XCH23, /**< APORT2XCH23 */ + opaPosSelAPORT2XCH25 = VDAC_OPA_MUX_POSSEL_APORT2XCH25, /**< APORT2XCH25 */ + opaPosSelAPORT2XCH27 = VDAC_OPA_MUX_POSSEL_APORT2XCH27, /**< APORT2XCH27 */ + opaPosSelAPORT2XCH29 = VDAC_OPA_MUX_POSSEL_APORT2XCH29, /**< APORT2XCH29 */ + opaPosSelAPORT2XCH31 = VDAC_OPA_MUX_POSSEL_APORT2XCH31, /**< APORT2XCH31 */ + opaPosSelAPORT3XCH0 = VDAC_OPA_MUX_POSSEL_APORT3XCH0, /**< APORT3XCH0 */ + opaPosSelAPORT3XCH2 = VDAC_OPA_MUX_POSSEL_APORT3XCH2, /**< APORT3XCH2 */ + opaPosSelAPORT3XCH4 = VDAC_OPA_MUX_POSSEL_APORT3XCH4, /**< APORT3XCH4 */ + opaPosSelAPORT3XCH6 = VDAC_OPA_MUX_POSSEL_APORT3XCH6, /**< APORT3XCH6 */ + opaPosSelAPORT3XCH8 = VDAC_OPA_MUX_POSSEL_APORT3XCH8, /**< APORT3XCH8 */ + opaPosSelAPORT3XCH10 = VDAC_OPA_MUX_POSSEL_APORT3XCH10, /**< APORT3XCH10 */ + opaPosSelAPORT3XCH12 = VDAC_OPA_MUX_POSSEL_APORT3XCH12, /**< APORT3XCH12 */ + opaPosSelAPORT3XCH14 = VDAC_OPA_MUX_POSSEL_APORT3XCH14, /**< APORT3XCH14 */ + opaPosSelAPORT3XCH16 = VDAC_OPA_MUX_POSSEL_APORT3XCH16, /**< APORT3XCH16 */ + opaPosSelAPORT3XCH18 = VDAC_OPA_MUX_POSSEL_APORT3XCH18, /**< APORT3XCH18 */ + opaPosSelAPORT3XCH20 = VDAC_OPA_MUX_POSSEL_APORT3XCH20, /**< APORT3XCH20 */ + opaPosSelAPORT3XCH22 = VDAC_OPA_MUX_POSSEL_APORT3XCH22, /**< APORT3XCH22 */ + opaPosSelAPORT3XCH24 = VDAC_OPA_MUX_POSSEL_APORT3XCH24, /**< APORT3XCH24 */ + opaPosSelAPORT3XCH26 = VDAC_OPA_MUX_POSSEL_APORT3XCH26, /**< APORT3XCH26 */ + opaPosSelAPORT3XCH28 = VDAC_OPA_MUX_POSSEL_APORT3XCH28, /**< APORT3XCH28 */ + opaPosSelAPORT3XCH30 = VDAC_OPA_MUX_POSSEL_APORT3XCH30, /**< APORT3XCH30 */ + opaPosSelAPORT4XCH1 = VDAC_OPA_MUX_POSSEL_APORT4XCH1, /**< APORT4XCH1 */ + opaPosSelAPORT4XCH3 = VDAC_OPA_MUX_POSSEL_APORT4XCH3, /**< APORT4XCH3 */ + opaPosSelAPORT4XCH5 = VDAC_OPA_MUX_POSSEL_APORT4XCH5, /**< APORT4XCH5 */ + opaPosSelAPORT4XCH7 = VDAC_OPA_MUX_POSSEL_APORT4XCH7, /**< APORT4XCH7 */ + opaPosSelAPORT4XCH9 = VDAC_OPA_MUX_POSSEL_APORT4XCH9, /**< APORT4XCH9 */ + opaPosSelAPORT4XCH11 = VDAC_OPA_MUX_POSSEL_APORT4XCH11, /**< APORT4XCH11 */ + opaPosSelAPORT4XCH13 = VDAC_OPA_MUX_POSSEL_APORT4XCH13, /**< APORT4XCH13 */ + opaPosSelAPORT4XCH15 = VDAC_OPA_MUX_POSSEL_APORT4XCH15, /**< APORT4XCH15 */ + opaPosSelAPORT4XCH17 = VDAC_OPA_MUX_POSSEL_APORT4XCH17, /**< APORT4XCH17 */ + opaPosSelAPORT4XCH19 = VDAC_OPA_MUX_POSSEL_APORT4XCH19, /**< APORT4XCH19 */ + opaPosSelAPORT4XCH21 = VDAC_OPA_MUX_POSSEL_APORT4XCH21, /**< APORT4XCH21 */ + opaPosSelAPORT4XCH23 = VDAC_OPA_MUX_POSSEL_APORT4XCH23, /**< APORT4XCH23 */ + opaPosSelAPORT4XCH25 = VDAC_OPA_MUX_POSSEL_APORT4XCH25, /**< APORT4XCH25 */ + opaPosSelAPORT4XCH27 = VDAC_OPA_MUX_POSSEL_APORT4XCH27, /**< APORT4XCH27 */ + opaPosSelAPORT4XCH29 = VDAC_OPA_MUX_POSSEL_APORT4XCH29, /**< APORT4XCH29 */ + opaPosSelAPORT4XCH31 = VDAC_OPA_MUX_POSSEL_APORT4XCH31, /**< APORT4XCH31 */ + opaPosSelDisable = VDAC_OPA_MUX_POSSEL_DISABLE, /**< Input disabled. */ + opaPosSelDac = VDAC_OPA_MUX_POSSEL_DAC, /**< DAC as input (not OPA2). */ + opaPosSelPosPad = VDAC_OPA_MUX_POSSEL_POSPAD, /**< Positive pad as input. */ + opaPosSelOpaIn = VDAC_OPA_MUX_POSSEL_OPANEXT, /**< Input from OPAx. */ + opaPosSelResTap = VDAC_OPA_MUX_POSSEL_OPATAP /**< Feedback resistor ladder tap. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_PosSel_TypeDef; + +/** OPAMP output terminal selection values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaOutModeDisable = DAC_OPA0MUX_OUTMODE_DISABLE, /**< OPA output disabled. */ + opaOutModeMain = DAC_OPA0MUX_OUTMODE_MAIN, /**< Main output to pin enabled. */ + opaOutModeAlt = DAC_OPA0MUX_OUTMODE_ALT, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = DAC_OPA0MUX_OUTMODE_ALL /**< Both main and alternate enabled (not OPA2). */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaOutModeDisable = 0, /**< OPA output disabled. */ + opaOutModeMain = VDAC_OPA_OUT_MAINOUTEN, /**< Main output to pin enabled. */ + opaOutModeAlt = VDAC_OPA_OUT_ALTOUTEN, /**< Alternate output(s) enabled (not OPA2). */ + opaOutModeAll = VDAC_OPA_OUT_SHORT, /**< Both main and alternate enabled (not OPA2). */ + opaOutModeAPORT1YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH1), /**< APORT output to APORT1YCH1 pin enabled. */ + opaOutModeAPORT1YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH3), /**< APORT output to APORT1YCH3 pin enabled. */ + opaOutModeAPORT1YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH5), /**< APORT output to APORT1YCH5 pin enabled. */ + opaOutModeAPORT1YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH7), /**< APORT output to APORT1YCH7 pin enabled. */ + opaOutModeAPORT1YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH9), /**< APORT output to APORT1YCH9 pin enabled. */ + opaOutModeAPORT1YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH11), /**< APORT output to APORT1YCH11 pin enabled. */ + opaOutModeAPORT1YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH13), /**< APORT output to APORT1YCH13 pin enabled. */ + opaOutModeAPORT1YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH15), /**< APORT output to APORT1YCH15 pin enabled. */ + opaOutModeAPORT1YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH17), /**< APORT output to APORT1YCH17 pin enabled. */ + opaOutModeAPORT1YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH19), /**< APORT output to APORT1YCH19 pin enabled. */ + opaOutModeAPORT1YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH21), /**< APORT output to APORT1YCH21 pin enabled. */ + opaOutModeAPORT1YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH23), /**< APORT output to APORT1YCH23 pin enabled. */ + opaOutModeAPORT1YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH25), /**< APORT output to APORT1YCH25 pin enabled. */ + opaOutModeAPORT1YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH27), /**< APORT output to APORT1YCH27 pin enabled. */ + opaOutModeAPORT1YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH29), /**< APORT output to APORT1YCH29 pin enabled. */ + opaOutModeAPORT1YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT1YCH31), /**< APORT output to APORT1YCH31 pin enabled. */ + opaOutModeAPORT2YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH0), /**< APORT output to APORT2YCH0 pin enabled. */ + opaOutModeAPORT2YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH2), /**< APORT output to APORT2YCH2 pin enabled. */ + opaOutModeAPORT2YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH4), /**< APORT output to APORT2YCH4 pin enabled. */ + opaOutModeAPORT2YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH6), /**< APORT output to APORT2YCH6 pin enabled. */ + opaOutModeAPORT2YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH8), /**< APORT output to APORT2YCH8 pin enabled. */ + opaOutModeAPORT2YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH10), /**< APORT output to APORT2YCH10 pin enabled. */ + opaOutModeAPORT2YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH12), /**< APORT output to APORT2YCH12 pin enabled. */ + opaOutModeAPORT2YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH14), /**< APORT output to APORT2YCH14 pin enabled. */ + opaOutModeAPORT2YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH16), /**< APORT output to APORT2YCH16 pin enabled. */ + opaOutModeAPORT2YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH18), /**< APORT output to APORT2YCH18 pin enabled. */ + opaOutModeAPORT2YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH20), /**< APORT output to APORT2YCH20 pin enabled. */ + opaOutModeAPORT2YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH22), /**< APORT output to APORT2YCH22 pin enabled. */ + opaOutModeAPORT2YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH24), /**< APORT output to APORT2YCH24 pin enabled. */ + opaOutModeAPORT2YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH26), /**< APORT output to APORT2YCH26 pin enabled. */ + opaOutModeAPORT2YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH28), /**< APORT output to APORT2YCH28 pin enabled. */ + opaOutModeAPORT2YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT2YCH30), /**< APORT output to APORT2YCH30 pin enabled. */ + opaOutModeAPORT3YCH1 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH1), /**< APORT output to APORT3YCH1 pin enabled. */ + opaOutModeAPORT3YCH3 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH3), /**< APORT output to APORT3YCH3 pin enabled. */ + opaOutModeAPORT3YCH5 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH5), /**< APORT output to APORT3YCH5 pin enabled. */ + opaOutModeAPORT3YCH7 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH7), /**< APORT output to APORT3YCH7 pin enabled. */ + opaOutModeAPORT3YCH9 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH9), /**< APORT output to APORT3YCH9 pin enabled. */ + opaOutModeAPORT3YCH11 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH11), /**< APORT output to APORT3YCH11 pin enabled. */ + opaOutModeAPORT3YCH13 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH13), /**< APORT output to APORT3YCH13 pin enabled. */ + opaOutModeAPORT3YCH15 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH15), /**< APORT output to APORT3YCH15 pin enabled. */ + opaOutModeAPORT3YCH17 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH17), /**< APORT output to APORT3YCH17 pin enabled. */ + opaOutModeAPORT3YCH19 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH19), /**< APORT output to APORT3YCH19 pin enabled. */ + opaOutModeAPORT3YCH21 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH21), /**< APORT output to APORT3YCH21 pin enabled. */ + opaOutModeAPORT3YCH23 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH23), /**< APORT output to APORT3YCH23 pin enabled. */ + opaOutModeAPORT3YCH25 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH25), /**< APORT output to APORT3YCH25 pin enabled. */ + opaOutModeAPORT3YCH27 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH27), /**< APORT output to APORT3YCH27 pin enabled. */ + opaOutModeAPORT3YCH29 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH29), /**< APORT output to APORT3YCH29 pin enabled. */ + opaOutModeAPORT3YCH31 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT3YCH31), /**< APORT output to APORT3YCH31 pin enabled. */ + opaOutModeAPORT4YCH0 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH0), /**< APORT output to APORT4YCH0 pin enabled. */ + opaOutModeAPORT4YCH2 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH2), /**< APORT output to APORT4YCH2 pin enabled. */ + opaOutModeAPORT4YCH4 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH4), /**< APORT output to APORT4YCH4 pin enabled. */ + opaOutModeAPORT4YCH6 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH6), /**< APORT output to APORT4YCH6 pin enabled. */ + opaOutModeAPORT4YCH8 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH8), /**< APORT output to APORT4YCH8 pin enabled. */ + opaOutModeAPORT4YCH10 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH10), /**< APORT output to APORT4YCH10 pin enabled. */ + opaOutModeAPORT4YCH12 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH12), /**< APORT output to APORT4YCH12 pin enabled. */ + opaOutModeAPORT4YCH14 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH14), /**< APORT output to APORT4YCH14 pin enabled. */ + opaOutModeAPORT4YCH16 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH16), /**< APORT output to APORT4YCH16 pin enabled. */ + opaOutModeAPORT4YCH18 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH18), /**< APORT output to APORT4YCH18 pin enabled. */ + opaOutModeAPORT4YCH20 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH20), /**< APORT output to APORT4YCH20 pin enabled. */ + opaOutModeAPORT4YCH22 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH22), /**< APORT output to APORT4YCH22 pin enabled. */ + opaOutModeAPORT4YCH24 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH24), /**< APORT output to APORT4YCH24 pin enabled. */ + opaOutModeAPORT4YCH26 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH26), /**< APORT output to APORT4YCH26 pin enabled. */ + opaOutModeAPORT4YCH28 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH28), /**< APORT output to APORT4YCH28 pin enabled. */ + opaOutModeAPORT4YCH30 = (VDAC_OPA_OUT_APORTOUTEN | VDAC_OPA_OUT_APORTOUTSEL_APORT4YCH30), /**< APORT output to APORT4YCH30 pin enabled. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_OutMode_TypeDef; + +/** OPAMP gain values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaResSelDefault = DAC_OPA0MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = DAC_OPA0MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = DAC_OPA0MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = DAC_OPA0MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2R1 = DAC_OPA0MUX_RESSEL_RES3, /**< R2 = 2 * R1 */ + opaResSelR2eq3R1 = DAC_OPA0MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = DAC_OPA0MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = DAC_OPA0MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = DAC_OPA0MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResSelDefault = VDAC_OPA_MUX_RESSEL_DEFAULT, /**< Default value when resistor ladder is unused. */ + opaResSelR2eq0_33R1 = VDAC_OPA_MUX_RESSEL_RES0, /**< R2 = 0.33 * R1 */ + opaResSelR2eqR1 = VDAC_OPA_MUX_RESSEL_RES1, /**< R2 = R1 */ + opaResSelR1eq1_67R1 = VDAC_OPA_MUX_RESSEL_RES2, /**< R2 = 1.67 R1 */ + opaResSelR2eq2_2R1 = VDAC_OPA_MUX_RESSEL_RES3, /**< R2 = 2.2 * R1 */ + opaResSelR2eq3R1 = VDAC_OPA_MUX_RESSEL_RES4, /**< R2 = 3 * R1 */ + opaResSelR2eq4_33R1 = VDAC_OPA_MUX_RESSEL_RES5, /**< R2 = 4.33 * R1 */ + opaResSelR2eq7R1 = VDAC_OPA_MUX_RESSEL_RES6, /**< R2 = 7 * R1 */ + opaResSelR2eq15R1 = VDAC_OPA_MUX_RESSEL_RES7 /**< R2 = 15 * R1 */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_ResSel_TypeDef; + +/** OPAMP resistor ladder input selector values. */ +typedef enum { +#if defined(_SILICON_LABS_32B_SERIES_0) + opaResInMuxDisable = DAC_OPA0MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = DAC_OPA0MUX_RESINMUX_OPA0INP, /**< Input from OPAx. */ + opaResInMuxNegPad = DAC_OPA0MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = DAC_OPA0MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxVss = DAC_OPA0MUX_RESINMUX_VSS /**< Input connected to Vss. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + opaResInMuxDisable = VDAC_OPA_MUX_RESINMUX_DISABLE, /**< Resistor ladder disabled. */ + opaResInMuxOpaIn = VDAC_OPA_MUX_RESINMUX_OPANEXT, /**< Input from OPAx. */ + opaResInMuxNegPad = VDAC_OPA_MUX_RESINMUX_NEGPAD, /**< Input from negative pad. */ + opaResInMuxPosPad = VDAC_OPA_MUX_RESINMUX_POSPAD, /**< Input from positive pad. */ + opaResInMuxComPad = VDAC_OPA_MUX_RESINMUX_COMPAD, /**< Input from negative pad of OPA0. + Direct input to support common reference. */ + opaResInMuxCenter = VDAC_OPA_MUX_RESINMUX_CENTER, /**< OPA0 and OPA1 Resmux connected to form fully + differential instrumentation amplifier. */ + opaResInMuxVss = VDAC_OPA_MUX_RESINMUX_VSS, /**< Input connected to Vss. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ +} OPAMP_ResInMux_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) +/** OPAMP PRS Mode. */ +typedef enum { + opaPrsModeDefault = VDAC_OPA_CTRL_PRSMODE_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsModePulsed = VDAC_OPA_CTRL_PRSMODE_PULSED, /**< PRS trigger is a pulse that starts the OPAMP + warmup sequence. The end of the warmup sequence + is controlled by timeout settings in OPAxTIMER. */ + opaPrsModeTimed = VDAC_OPA_CTRL_PRSMODE_TIMED, /**< PRS trigger is a pulse long enough to provide the + OPAMP warmup sequence. The end of the warmup + sequence is controlled by the edge of the pulse. */ +} OPAMP_PrsMode_TypeDef; + +/** OPAMP PRS Selection. */ +typedef enum { + opaPrsSelDefault = VDAC_OPA_CTRL_PRSSEL_DEFAULT, /**< Default value when PRS is not the trigger. */ + opaPrsSelCh0 = VDAC_OPA_CTRL_PRSSEL_PRSCH0, /**< PRS channel 0 triggers OPAMP. */ + opaPrsSelCh1 = VDAC_OPA_CTRL_PRSSEL_PRSCH1, /**< PRS channel 1 triggers OPAMP. */ + opaPrsSelCh2 = VDAC_OPA_CTRL_PRSSEL_PRSCH2, /**< PRS channel 2 triggers OPAMP. */ + opaPrsSelCh3 = VDAC_OPA_CTRL_PRSSEL_PRSCH3, /**< PRS channel 3 triggers OPAMP. */ + opaPrsSelCh4 = VDAC_OPA_CTRL_PRSSEL_PRSCH4, /**< PRS channel 4 triggers OPAMP. */ + opaPrsSelCh5 = VDAC_OPA_CTRL_PRSSEL_PRSCH5, /**< PRS channel 5 triggers OPAMP. */ + opaPrsSelCh6 = VDAC_OPA_CTRL_PRSSEL_PRSCH6, /**< PRS channel 6 triggers OPAMP. */ + opaPrsSelCh7 = VDAC_OPA_CTRL_PRSSEL_PRSCH7, /**< PRS channel 7 triggers OPAMP. */ +#if defined(VDAC_OPA_CTRL_PRSSEL_PRSCH8) + opaPrsSelCh8 = VDAC_OPA_CTRL_PRSSEL_PRSCH8, /**< PRS channel 8 triggers OPAMP. */ + opaPrsSelCh9 = VDAC_OPA_CTRL_PRSSEL_PRSCH9, /**< PRS channel 9 triggers OPAMP. */ + opaPrsSelCh10 = VDAC_OPA_CTRL_PRSSEL_PRSCH10, /**< PRS channel 10 triggers OPAMP. */ + opaPrsSelCh11 = VDAC_OPA_CTRL_PRSSEL_PRSCH11, /**< PRS channel 11 triggers OPAMP. */ +#endif +} OPAMP_PrsSel_TypeDef; + +/** OPAMP PRS Output. */ +typedef enum { + opaPrsOutDefault = VDAC_OPA_CTRL_PRSOUTMODE_DEFAULT, /**< Default value. */ + opaPrsOutWarm = VDAC_OPA_CTRL_PRSOUTMODE_WARM, /**< Warm status available on PRS. */ + opaPrsOutOutValid = VDAC_OPA_CTRL_PRSOUTMODE_OUTVALID, /**< Outvalid status available on PRS. */ +} OPAMP_PrsOut_TypeDef; + +/** OPAMP Output Scaling. */ +typedef enum { + opaOutScaleDefault = VDAC_OPA_CTRL_OUTSCALE_DEFAULT, /**< Default OPAM output drive strength. */ + opaOutScaleFull = VDAC_OPA_CTRL_OUTSCALE_FULL, /**< OPAMP uses full output drive strength. */ + opaOutSacleHalf = VDAC_OPA_CTRL_OUTSCALE_HALF, /**< OPAMP uses half output drive strength. */ +} OPAMP_OutScale_Typedef; + +/** OPAMP Drive Strength. */ +typedef enum { + opaDrvStrDefault = VDAC_OPA_CTRL_DRIVESTRENGTH_DEFAULT, /**< Default value. */ + opaDrvStrLowerAccLowStr = (0 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Lower accuracy with low drive strength. */ + opaDrvStrLowAccLowStr = (1 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Low accuracy with low drive strength. */ + opaDrvStrHighAccHighStr = (2 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< High accuracy with high drive strength. */ + opaDrvStrHigherAccHighStr = (3 << _VDAC_OPA_CTRL_DRIVESTRENGTH_SHIFT), /**< Higher accuracy with high drive strength. */ +} OPAMP_DrvStr_Typedef; +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** OPAMP init structure. */ +typedef struct { + OPAMP_NegSel_TypeDef negSel; /**< Select input source for negative terminal. */ + OPAMP_PosSel_TypeDef posSel; /**< Select input source for positive terminal. */ + OPAMP_OutMode_TypeDef outMode; /**< Output terminal connection. */ + OPAMP_ResSel_TypeDef resSel; /**< Select R2/R1 resistor ratio. */ + OPAMP_ResInMux_TypeDef resInMux; /**< Select input source for resistor ladder. */ + uint32_t outPen; /**< Alternate output enable bit mask. This value + should consist one or more of the + @if DOXYDOC_P1_DEVICE + DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags + (defined in \_dac.h) OR'ed together. + @n @n + For OPA0: + @li DAC_OPA0MUX_OUTPEN_OUT0 + @li DAC_OPA0MUX_OUTPEN_OUT1 + @li DAC_OPA0MUX_OUTPEN_OUT2 + @li DAC_OPA0MUX_OUTPEN_OUT3 + @li DAC_OPA0MUX_OUTPEN_OUT4 + + For OPA1: + @li DAC_OPA1MUX_OUTPEN_OUT0 + @li DAC_OPA1MUX_OUTPEN_OUT1 + @li DAC_OPA1MUX_OUTPEN_OUT2 + @li DAC_OPA1MUX_OUTPEN_OUT3 + @li DAC_OPA1MUX_OUTPEN_OUT4 + + For OPA2: + @li DAC_OPA2MUX_OUTPEN_OUT0 + @li DAC_OPA2MUX_OUTPEN_OUT1 + + E.g: @n + init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | + DAC_OPA0MUX_OUTPEN_OUT2 | + DAC_OPA0MUX_OUTPEN_OUT4; + + @elseif DOXYDOC_P2_DEVICE + VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + (defined in \_vdac.h) OR'ed together. + @n @n + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + + E.g: @n + init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT2 | + VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + @endif */ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t bias; /**< Set OPAMP bias current. */ + bool halfBias; /**< Divide OPAMP bias current by 2. */ + bool lpfPosPadDisable; /**< Disable low pass filter on positive pad. */ + bool lpfNegPadDisable; /**< Disable low pass filter on negative pad. */ + bool nextOut; /**< Enable NEXTOUT signal source. */ + bool npEn; /**< Enable positive pad. */ + bool ppEn; /**< Enable negative pad. */ + bool shortInputs; /**< Short OPAMP input terminals. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffset; /**< Use factory calibrated opamp offset value. */ + uint32_t offset; /**< Opamp offset value when @ref defaultOffset is + false. */ +#elif defined(_SILICON_LABS_32B_SERIES_1) + OPAMP_DrvStr_Typedef drvStr; /**< OPAx operation mode. */ + bool gain3xEn; /**< Enable 3x gain resistor ladder. */ + bool halfDrvStr; /**< Half or full output drive strength. */ + bool ugBwScale; /**< Unity gain bandwidth scaled by factor of 2.5. */ + bool prsEn; /**< Enable PRS as OPAMP trigger. */ + OPAMP_PrsMode_TypeDef prsMode; /**< Selects PRS trigger mode. */ + OPAMP_PrsSel_TypeDef prsSel; /**< PRS channel trigger select. */ + OPAMP_PrsOut_TypeDef prsOutSel; /**< PRS output select. */ + bool aportYMasterDisable; /**< Disable bus master request on APORT Y. */ + bool aportXMasterDisable; /**< Disable bus master request on APORT X. */ + uint32_t settleTime; /**< Number of clock cycles to drive the output. */ + uint32_t startupDly; /**< OPAx startup delay in microseconds. */ + bool hcmDisable; /**< Disable input rail-to-rail capability. */ + bool defaultOffsetN; /**< Use factory calibrated opamp inverting input + offset value. */ + uint32_t offsetN; /**< Opamp inverting input offset value when + @ref defaultOffsetN is false. */ + bool defaultOffsetP; /**< Use factory calibrated opamp non-inverting + input offset value. */ + uint32_t offsetP; /**< Opamp non-inverting input offset value when + @ref defaultOffsetP is false. */ +#endif /* defined(_SILICON_LABS_32B_SERIES_1) */ +} OPAMP_Init_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** Configuration of OPA0/1 in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN_OPA2 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0/1 in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0/1 in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in inverting amplifier mode. */ +#define OPA_INIT_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + true, /* Negative pad enabled, used as signal input. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Alternate output 0 enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA1). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal ground. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + true, /* Negative pad enabled, used as signal ground. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeAll, /* Both main and alternate outputs. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + true, /* Pass output to next stage (OPA2). */ \ + false, /* Negative pad disabled. */ \ + true, /* Positive pad enabled, used as signal input. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTapOpa0, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + DAC_OPA0MUX_OUTPEN_OUT0, /* Enable alternate output 0. */ \ + _DAC_BIASPROG_BIASPROG_DEFAULT, /* Default bias setting. */ \ + _DAC_BIASPROG_HALFBIAS_DEFAULT, /* Default half-bias setting. */ \ + false, /* No low pass filter on positive pad. */ \ + false, /* No low pass filter on negative pad. */ \ + false, /* No nextout output enabled. */ \ + false, /* Negative pad disabled. */ \ + false, /* Positive pad disabled. */ \ + false, /* No shorting of inputs. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use factory calibrated opamp offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) +/** Configuration of OPA in unity gain voltage follower mode. */ +#define OPA_INIT_UNITY_GAIN \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA in non-inverting amplifier mode. */ +#define OPA_INIT_NON_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA in inverting amplifier mode. */ +#define OPA_INIT_INVERTING \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA0 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA1 output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in cascaded non-inverting amplifier mode. */ +#define OPA_INIT_CASCADED_NON_INVERTING_OPA3 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelOpaIn, /* Positive input from OPA2NEXT output. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eq0_33R1, /* R2 = 1/3 R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA0 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA2 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in cascaded inverting amplifier mode. */ +#define OPA_INIT_CASCADED_INVERTING_OPA3 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Resistor ladder disabled. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp differential driver mode. */ +#define OPA_INIT_DIFF_DRIVER_OPA1 \ + { \ + opaNegSelResTap, /* Negative input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA0. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA0 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxNegPad, /* Resistor ladder input from negative pad. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA1 \ + { \ + opaNegSelUnityGain, /* Unity gain. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelDefault, /* Resistor ladder is not used. */ \ + opaResInMuxDisable, /* Disable resistor ladder. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA2 in three-opamp differential receiver mode. */ +#define OPA_INIT_DIFF_RECEIVER_OPA2 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA0 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA1. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA3 in three+one opamp differential receiver mode. In this + configuration, OPA3 is a second single-ended output amplifier. */ +#define OPA_INIT_DIFF_RECEIVER_OPA3 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelResTap, /* Input from OPA2 resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxOpaIn, /* Resistor ladder input from OPA2. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA0 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA0 \ + { \ + opaNegSelResTap, /* Input from resistor ladder tap. */ \ + opaPosSelPosPad, /* Positive input from pad. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +/** Configuration of OPA1 in two-opamp instrumentation amplifier mode. */ +#define OPA_INIT_INSTR_AMP_OPA1 \ + { \ + opaNegSelNegPad, /* Negative input from pad. */ \ + opaPosSelResTap, /* Input from resistor ladder tap. */ \ + opaOutModeMain, /* Main output enabled. */ \ + opaResSelR2eqR1, /* R2 = R1 */ \ + opaResInMuxCenter, /* OPA0/OPA1 resistor ladders connected. */ \ + 0, /* No alternate outputs enabled. */ \ + opaDrvStrDefault, /* Default opamp operation mode. */ \ + false, /* Disable 3x gain setting. */ \ + false, /* Use full output drive strength. */ \ + false, /* Disable unity-gain bandwidth scaling. */ \ + false, /* Opamp triggered by OPAxEN. */ \ + opaPrsModeDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsSelDefault, /* PRS is not used to trigger opamp. */ \ + opaPrsOutDefault, /* Default PRS output setting. */ \ + false, /* Bus mastering enabled on APORTX. */ \ + false, /* Bus mastering enabled on APORTY. */ \ + 3, /* 3 us settle time with default DrvStr. */ \ + 0, /* No startup delay. */ \ + false, /* Rail-to-rail input enabled. */ \ + true, /* Use calibrated inverting offset. */ \ + 0, /* Opamp offset value (not used). */ \ + true, /* Use calibrated non-inverting offset. */ \ + 0 /* Opamp offset value (not used). */ \ + } + +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +void OPAMP_Disable(DAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#elif defined(_SILICON_LABS_32B_SERIES_1) +void OPAMP_Disable(VDAC_TypeDef *dac, OPAMP_TypeDef opa); +void OPAMP_Enable(VDAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init); +#endif /* defined(_SILICON_LABS_32B_SERIES_0) */ + +/** @} (end addtogroup opamp) */ + +#ifdef __cplusplus +} +#endif + +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ +#endif /* EM_OPAMP_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_pcnt.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_pcnt.h index 3648587..a1c1d2e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_pcnt.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_pcnt.h @@ -1,905 +1,905 @@ -/***************************************************************************//** - * @file - * @brief Pulse Counter (PCNT) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_PCNT_H -#define EM_PCNT_H - -#include "em_device.h" -#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup pcnt - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ -/** PCNT0 Counter register size. */ -#if defined(_EFM32_GECKO_FAMILY) -#define PCNT0_CNT_SIZE (8) /**< PCNT0 counter is 8 bits. */ -#else -#define PCNT0_CNT_SIZE (16) /**< PCNT0 counter is 16 bits. */ -#endif - -#ifdef PCNT1 -/** PCNT1 Counter register size. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#define PCNT1_CNT_SIZE (8) /**< PCNT1 counter is 8 bits. */ -#else -#define PCNT1_CNT_SIZE (16) /**< PCNT1 counter is 16 bits. */ -#endif -#endif - -#ifdef PCNT2 -/** PCNT2 Counter register size. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#define PCNT2_CNT_SIZE (8) /**< PCNT2 counter is 8 bits. */ -#else -#define PCNT2_CNT_SIZE (16) /**< PCNT2 counter is 16 bits. */ -#endif -#endif - -/* Define values that can be used in case some state/mode are not defined for some devices.*/ -/** PCNT mode disable. */ -#define PCNT_MODE_DISABLE 0xFF -/** PCNT count event is none. */ -#define PCNT_CNT_EVENT_NONE 0xFF - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Mode selection. */ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -typedef enum { - /** Disable pulse counter. */ - pcntModeDisable = _PCNT_CTRL_MODE_DISABLE, - - /** Single input LFACLK oversampling mode (available in EM0-EM2). */ - pcntModeOvsSingle = _PCNT_CTRL_MODE_OVSSINGLE, - - /** Externally clocked single input counter mode (available in EM0-EM3). */ - pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE, - - /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ - pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD, - -#if defined(_PCNT_CTRL_MODE_OVSQUAD1X) - /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ - pcntModeOvsQuad1 = _PCNT_CTRL_MODE_OVSQUAD1X, - - /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ - pcntModeOvsQuad2 = _PCNT_CTRL_MODE_OVSQUAD2X, - - /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ - pcntModeOvsQuad4 = _PCNT_CTRL_MODE_OVSQUAD4X, -#endif -} PCNT_Mode_TypeDef; - -#else -typedef enum { - /** Disable pulse counter. */ - pcntModeDisable = PCNT_MODE_DISABLE, - - /** Single input LFACLK oversampling mode (available in EM0-EM2). */ - pcntModeOvsSingle = _PCNT_CFG_MODE_OVSSINGLE, - - /** Externally clocked single input counter mode (available in EM0-EM3). */ - pcntModeExtSingle = _PCNT_CFG_MODE_EXTCLKSINGLE, - - /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ - pcntModeExtQuad = _PCNT_CFG_MODE_EXTCLKQUAD, - - /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ - pcntModeOvsQuad1 = _PCNT_CFG_MODE_OVSQUAD1X, - - /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ - pcntModeOvsQuad2 = _PCNT_CFG_MODE_OVSQUAD2X, - - /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ - pcntModeOvsQuad4 = _PCNT_CFG_MODE_OVSQUAD4X, -} PCNT_Mode_TypeDef; -#endif - -#if defined(_PCNT_CTRL_CNTEV_MASK) -/** Counter event selection. - * Note: unshifted values are being used for enumeration because multiple - * configuration structure members use this type definition. */ -typedef enum { - /** Counts up on up-count and down on down-count events. */ - pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH, - - /** Only counts up on up-count events. */ - pcntCntEventUp = _PCNT_CTRL_CNTEV_UP, - - /** Only counts down on down-count events. */ - pcntCntEventDown = _PCNT_CTRL_CNTEV_DOWN, - - /** Never counts. */ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE -#else - pcntCntEventNone = PCNT_CNT_EVENT_NONE -#endif -} PCNT_CntEvent_TypeDef; -#endif - -/** PRS sources for @p s0PRS and @p s1PRS. */ -#if defined(_PCNT_INPUT_MASK) -typedef enum { - pcntPRSCh0 = 0, /**< PRS channel 0. */ - pcntPRSCh1 = 1, /**< PRS channel 1. */ - pcntPRSCh2 = 2, /**< PRS channel 2. */ - pcntPRSCh3 = 3, /**< PRS channel 3. */ -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH4) - pcntPRSCh4 = 4, /**< PRS channel 4. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH5) - pcntPRSCh5 = 5, /**< PRS channel 5. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH6) - pcntPRSCh6 = 6, /**< PRS channel 6. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH7) - pcntPRSCh7 = 7, /**< PRS channel 7. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH8) - pcntPRSCh8 = 8, /**< PRS channel 8. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH9) - pcntPRSCh9 = 9, /**< PRS channel 9. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH10) - pcntPRSCh10 = 10, /**< PRS channel 10. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11) - pcntPRSCh11 = 11, /**< PRS channel 11. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH12) - pcntPRSCh12 = 12, /**< PRS channel 12. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH13) - pcntPRSCh13 = 13, /**< PRS channel 13. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH14) - pcntPRSCh14 = 14, /**< PRS channel 14. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH15) - pcntPRSCh15 = 15, /**< PRS channel 15. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH16) - pcntPRSCh16 = 16, /**< PRS channel 16. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH17) - pcntPRSCh17 = 17, /**< PRS channel 17. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH18) - pcntPRSCh18 = 18, /**< PRS channel 18. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH19) - pcntPRSCh19 = 19, /**< PRS channel 19. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH20) - pcntPRSCh20 = 20, /**< PRS channel 20. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH21) - pcntPRSCh21 = 21, /**< PRS channel 21. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH22) - pcntPRSCh22 = 22, /**< PRS channel 22. */ -#endif -#if defined(PCNT_INPUT_S0PRSSEL_PRSCH23) - pcntPRSCh23 = 23, /**< PRS channel 23. */ -#endif -} PCNT_PRSSel_TypeDef; -#elif defined(_SILICON_LABS_32B_SERIES_2) -typedef unsigned int PCNT_PRSSel_TypeDef; -#endif - -#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) -/** PRS inputs of PCNT. */ -typedef enum { - pcntPRSInputS0 = 0, /** PRS input 0. */ - pcntPRSInputS1 = 1 /** PRS input 1. */ -} PCNT_PRSInput_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Initialization structure. */ -typedef struct { - /** Mode to operate in. */ - PCNT_Mode_TypeDef mode; - - /** Initial counter value (refer to reference manual for max value allowed). - * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. - * If using #pcntModeExtSingle or #pcntModeExtQuad modes, counter - * value is reset to HW reset value. */ - uint32_t counter; - - /** Initial top value (refer to reference manual for max value allowed). - * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. - * If using #pcntModeExtSingle or #pcntModeExtQuad modes, top - * value is reset to HW reset value. */ - uint32_t top; - - /** Polarity of incoming edge. - * @li #pcntModeExtSingle mode - if false, positive edges are counted, - * otherwise negative edges. - * @li #pcntModeExtQuad mode - if true, counting direction is inverted. */ - bool negEdge; - - /** Counting direction, only applicable for #pcntModeOvsSingle and - * #pcntModeExtSingle modes. */ - bool countDown; - - /** Enable filter, only available in #pcntModeOvsSingle* mode. */ - bool filter; - -#if defined(_SILICON_LABS_32B_SERIES_2) - /** Enable/disable PCNT counting during debug halt. Only in OVSSINGLE and OVSQUAD modes. */ - bool debugHalt; -#endif - -#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) - /** Set to true to enable hysteresis. When enabled, PCNT will always - * overflow and underflow to TOP/2. */ - bool hyst; -#endif - -#if defined(PCNT_CTRL_S1CDIR) - /** Set to true to enable S1 to determine the direction of counting in - * OVSSINGLE or EXTCLKSINGLE modes. @n - * When S1 is high, the count direction is given by CNTDIR, and when S1 is - * low, the count direction is the opposite. */ - bool s1CntDir; -#endif - -#if defined(_PCNT_CTRL_CNTEV_SHIFT) - /** Selects whether the regular counter responds to up-count events, - * down-count events, both, or none. */ - PCNT_CntEvent_TypeDef cntEvent; -#endif - -#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) - /** Selects whether the auxiliary counter responds to up-count events, - * down-count events, both, or none. */ - PCNT_CntEvent_TypeDef auxCntEvent; -#endif - -#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) - /** Select PRS channel as input to S0IN in PCNTx_INPUT register. */ - PCNT_PRSSel_TypeDef s0PRS; - - /** Select PRS channel as input to S1IN in PCNTx_INPUT register. */ - PCNT_PRSSel_TypeDef s1PRS; -#endif -} PCNT_Init_TypeDef; - -/** Default Debug. */ -#if defined(_SILICON_LABS_32B_SERIES_2) -#define DEFAULT_DEBUG_HALT true, -#else -#define DEFAULT_DEBUG_HALT -#endif - -/** Default Mode. */ -#define DEFAULT_MODE pcntModeDisable, /**< Disabled by default. */ - -/** Default Hysteresis. */ -#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) -#define DEFAULT_HYST false, /**< Hysteresis disabled. */ -#else -#define DEFAULT_HYST -#endif - -/** Default counter direction*/ -#if defined(PCNT_CTRL_S1CDIR) -#define DEFAULT_CDIR true, /**< Counter direction is given by CNTDIR. */ -#else -#define DEFAULT_CDIR -#endif - -/** Default count event*/ -#if defined(_PCNT_CTRL_CNTEV_SHIFT) -#define DEFAULT_CNTEV pcntCntEventUp, /**< Regular counter counts up on upcount events. */ -#else -#define DEFAULT_CNTEV -#endif - -/** Default auxiliary count event. */ -#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) -#define DEFAULT_AUXCNTEV pcntCntEventNone, /**< Auxiliary counter doesn't respond to events. */ -#else -#define DEFAULT_AUXCNTEV -#endif - -/** Default selected PRS channel as S0IN and S1IN. */ -#if defined(_PCNT_INPUT_MASK) -#define DEFAULT_PRS_CH pcntPRSCh0, /**< PRS channel 0 selected as S0IN and as S1IN. */ -#elif defined(_SILICON_LABS_32B_SERIES_2) -#define DEFAULT_PRS_CH 0u, -#else -#define DEFAULT_PRS_CH -#endif - -/** Default configuration for PCNT initialization structure. */ -#define PCNT_INIT_DEFAULT \ - { \ - DEFAULT_MODE /* Default mode. */ \ - _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \ - _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \ - false, /* Use positive edge. */ \ - false, /* Up-counting. */ \ - false, /* Filter disabled. */ \ - DEFAULT_DEBUG_HALT /* Debug Halt enabled. */ \ - DEFAULT_HYST /* Default Hysteresis. */ \ - DEFAULT_CDIR /* Default CNTDIR. */ \ - DEFAULT_CNTEV /* Faults CNTEV. */ \ - DEFAULT_AUXCNTEV /* Default AUXCNTEV. */ \ - DEFAULT_PRS_CH /* PRS channel 0 selected as S0IN. */ \ - DEFAULT_PRS_CH /* PRS channel 0 selected as S1IN. */ \ - } - -#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) -/** Filter initialization structure */ -typedef struct { - /** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable filter by - * setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */ - uint8_t filtLen; - - /** When set, removes flutter from Quaddecoder inputs S0IN and S1IN. - * Available only in OVSQUAD1X-4X modes. */ - bool flutterrm; -} PCNT_Filter_TypeDef; -#endif - -/** Default configuration for PCNT initialization structure. */ -#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) -#define PCNT_FILTER_DEFAULT \ - { \ - 0, /* Default length is 5 LFACLK cycles. */ \ - false /* No flutter removal. */ \ - } -#endif - -#if defined(PCNT_CTRL_TCCMODE_DEFAULT) - -/** Modes for Triggered Compare and Clear module. */ -typedef enum { - /** Triggered compare and clear not enabled. */ - tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED, - - /** Compare and clear performed on each (optionally prescaled) LFA clock cycle. */ - tccModeLFA = _PCNT_CTRL_TCCMODE_LFA, - - /** Compare and clear performed on PRS edges. Polarity defined by prsPolarity. */ - tccModePRS = _PCNT_CTRL_TCCMODE_PRS -} PCNT_TCCMode_TypeDef; - -/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */ -typedef enum { - /** Compare and clear event each LFA cycle. */ - tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1, - - /** Compare and clear event every other LFA cycle. */ - tccPrescDiv2 = _PCNT_CTRL_TCCPRESC_DIV2, - - /** Compare and clear event every 4th LFA cycle. */ - tccPrescDiv4 = _PCNT_CTRL_TCCPRESC_DIV4, - - /** Compare and clear event every 8th LFA cycle. */ - tccPrescDiv8 = _PCNT_CTRL_TCCPRESC_DIV8 -} PCNT_TCCPresc_Typedef; - -/** Compare modes for TCC module. */ -typedef enum { - /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */ - tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE, - - /** Compare match if PCNT_CNT is greater than or equal to PCNT_TOP. */ - tccCompGTOE = _PCNT_CTRL_TCCCOMP_GTOE, - - /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater - * than, or equal to PCNT_TOP[7:0]. */ - tccCompRange = _PCNT_CTRL_TCCCOMP_RANGE -} PCNT_TCCComp_Typedef; - -/** TCC initialization structure. */ -typedef struct { - /** Mode to operate in. */ - PCNT_TCCMode_TypeDef mode; - - /** Prescaler value for LFACLK in LFA mode. */ - PCNT_TCCPresc_Typedef prescaler; - - /** Choose the event that will trigger a clear. */ - PCNT_TCCComp_Typedef compare; - - /** PRS input to TCC module, either for gating the PCNT clock, triggering the TCC comparison, or both. */ - PCNT_PRSSel_TypeDef tccPRS; - - /** TCC PRS input polarity. @n - * False = Rising edge for comparison trigger, and PCNT clock gated when PRS signal is high. @n - * True = Falling edge for comparison trigger, and PCNT clock gated when PRS signal is low. */ - bool prsPolarity; - - /** Enable gating PCNT input clock through TCC PRS signal. - * Polarity selection is done through prsPolarity. */ - bool prsGateEnable; -} PCNT_TCC_TypeDef; - -/** TCC Default. */ -#define PCNT_TCC_DEFAULT \ - { \ - tccModeDisabled, /* Disabled by default. */ \ - tccPrescDiv1, /* Do not prescale LFA clock in LFA mode. */ \ - tccCompLTOE, /* Clear when CNT <= TOP. */ \ - pcntPRSCh0, /* Select PRS channel 0 as input to TCC. */ \ - false, /* PRS polarity is rising edge, and gate when 1. */ \ - false /* Do not gate PCNT counter input. */ \ - } - -#endif -/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the pulse counter value. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @return - * Current pulse counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_CounterGet(PCNT_TypeDef *pcnt) -{ - return pcnt->CNT; -} - -#if defined(_PCNT_AUXCNT_MASK) -/***************************************************************************//** - * @brief - * Get the auxiliary counter value. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @return - * Current auxiliary counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_AuxCounterGet(PCNT_TypeDef *pcnt) -{ - return pcnt->AUXCNT; -} -#endif - -void PCNT_CounterReset(PCNT_TypeDef *pcnt); -void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top); - -/***************************************************************************//** - * @brief - * Set a counter value. - * - * @details - * Pulse counter is disabled while changing counter value and re-enabled - * (if originally enabled) when counter value has been set. - * - * @note - * This function will stall until synchronization to low-frequency domain is - * completed. For that reason, it should normally not be used when using - * an external clock to clock the PCNT module since stall time may be - * undefined in that case. The counter should normally only be set when - * operating in (or about to enable) #pcntModeOvsSingle mode. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @param[in] count - * Value to set in counter register. - ******************************************************************************/ -__STATIC_INLINE void PCNT_CounterSet(PCNT_TypeDef *pcnt, uint32_t count) -{ - PCNT_CounterTopSet(pcnt, count, pcnt->TOP); -} - -void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode); -bool PCNT_IsEnabled(PCNT_TypeDef *pcnt); -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable); -#endif -void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init); - -#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) -void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable); -#endif - -#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) -void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, - PCNT_PRSInput_TypeDef prsInput, - bool enable); -#endif - -#if defined(PCNT_CTRL_TCCMODE_DEFAULT) -void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config); -#endif - -/***************************************************************************//** - * @brief - * Clear one or more pending PCNT interrupts. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @param[in] flags - * Pending PCNT interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the PCNT module (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void PCNT_IntClear(PCNT_TypeDef *pcnt, uint32_t flags) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - pcnt->IFC = flags; -#else - pcnt->IF_CLR = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more PCNT interrupts. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @param[in] flags - * PCNT interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for PCNT module (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags) -{ -#if defined(PCNT_HAS_SET_CLEAR) - pcnt->IEN_CLR = flags; -#else - pcnt->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more PCNT interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * PCNT_IntClear() prior to enabling the interrupt. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @param[in] flags - * PCNT interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for PCNT module (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void PCNT_IntEnable(PCNT_TypeDef *pcnt, uint32_t flags) -{ -#if defined(PCNT_HAS_SET_CLEAR) - pcnt->IEN_SET = flags; -#else - pcnt->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending PCNT interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @return - * PCNT interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for PCNT module (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_IntGet(PCNT_TypeDef *pcnt) -{ - return pcnt->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending PCNT interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] pcnt - * Pointer to thePCNT peripheral register block. - * - * @return - * Pending and enabled PCNT interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in PCNT_IEN_nnn - * register (PCNT_IEN_nnn) and - * - the OR combination of valid interrupt flags of the PCNT module - * (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt) -{ - uint32_t ien; - - /* Store pcnt->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = pcnt->IEN; - - /* Bitwise AND of pending and enabled interrupts. */ - return pcnt->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending PCNT interrupts from SW. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @param[in] flags - * PCNT interrupt sources to set to pending. Use a bitwise logic OR combination - * of valid interrupt flags for PCNT module (PCNT_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void PCNT_IntSet(PCNT_TypeDef *pcnt, uint32_t flags) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - pcnt->IFS = flags; -#else - pcnt->IF_SET = flags; -#endif -} - -#if defined(_PCNT_LOCK_MASK) -/***************************************************************************//** - * @brief - * Lock PCNT registers. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @note When PCNT registers are locked PCNT_CFG, PCNT_EN, PCNT_SWRST, PCNT_CMD, - * PCNT_CTRL, PCNT_OVSCTRL, PCNT_CNT, PCNT_TOP, and PCNT_TOPB registers - * cannot be written to. - ******************************************************************************/ -__STATIC_INLINE void PCNT_Lock(PCNT_TypeDef *pcnt) -{ - pcnt->LOCK = ~PCNT_LOCK_PCNTLOCKKEY_UNLOCK; -} -#endif - -#if defined(_PCNT_LOCK_MASK) -/***************************************************************************//** - * @brief - * Unlock PCNT registers. - * - * @param[in] pcnt - * Pointer to thePCNT peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void PCNT_Unlock(PCNT_TypeDef *pcnt) -{ - pcnt->LOCK = PCNT_LOCK_PCNTLOCKKEY_UNLOCK; -} -#endif - -void PCNT_Reset(PCNT_TypeDef *pcnt); - -/***************************************************************************//** - * @brief - * Get the pulse counter top buffer value. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @return - * Current pulse counter top buffer value. - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_TopBufferGet(PCNT_TypeDef *pcnt) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOPB) { - } -#endif - return pcnt->TOPB; -} - -void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val); - -/***************************************************************************//** - * @brief - * Get the pulse counter top value. - * - * @param[in] pcnt - * Pointer to the PCNT peripheral register block. - * - * @return - * Current pulse counter top value. - ******************************************************************************/ -__STATIC_INLINE uint32_t PCNT_TopGet(PCNT_TypeDef *pcnt) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOP) { - } -#endif - return pcnt->TOP; -} - -void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val); - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to low-frequency domain to complete. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask) -{ - /* Avoid deadlock if modifying the same register twice when freeze mode is - * activated. */ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE) { - return; - } -#endif - - /* Wait for any pending previous write operation to have been completed in - * low-frequency domain. */ - while (pcnt->SYNCBUSY & mask) { - } -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Start the main PCNT counter. - * - * @details - * This function will send a start command to the PCNT peripheral. The PCNT - * peripheral will use some LF clock ticks before the command is executed. - * The @ref PCNT_Sync() function can be used to wait for the start command - * to be executed. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @note - * This function requires the PCNT to be enabled. - ******************************************************************************/ -__STATIC_INLINE void PCNT_StartMainCnt(PCNT_TypeDef *pcnt) -{ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD_SET = PCNT_CMD_STARTCNT; -} - -/***************************************************************************//** - * @brief - * Stop the main PCNT counter. - * - * @details - * This function will send a stop command to the PCNT peripheral. The PCNT - * peripheral will use some LF clock ticks before the command is executed. - * The @ref PCNT_Sync() function can be used to wait for the stop command - * to be executed. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @note - * This function requires the PCNT to be enabled. - ******************************************************************************/ -__STATIC_INLINE void PCNT_StopMainCnt(PCNT_TypeDef *pcnt) -{ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD_SET = PCNT_CMD_STOPCNT; -} - -/***************************************************************************//** - * @brief - * Start the auxiliary PCNT counter. - * - * @details - * This function will send a start command to the PCNT peripheral. The PCNT - * peripheral will use some LF clock ticks before the command is executed. - * The @ref PCNT_Sync() function can be used to wait for the start command - * to be executed. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @note - * This function requires the PCNT to be enabled. - ******************************************************************************/ -__STATIC_INLINE void PCNT_StartAuxCnt(PCNT_TypeDef *pcnt) -{ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD_SET = PCNT_CMD_STARTAUXCNT; -} - -/***************************************************************************//** - * @brief - * Stop the auxiliary PCNT counter. - * - * @details - * This function will send a stop command to the PCNT peripheral. The PCNT - * peripheral will use some LF clock ticks before the command is executed. - * The @ref PCNT_Sync() function can be used to wait for the stop command - * to be executed. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @note - * This function requires the PCNT to be enabled. - ******************************************************************************/ -__STATIC_INLINE void PCNT_StopAuxCnt(PCNT_TypeDef *pcnt) -{ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD_SET = PCNT_CMD_STOPAUXCNT; -} -#endif - -/** @} (end addtogroup pcnt) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ -#endif /* EM_PCNT_H */ +/***************************************************************************//** + * @file + * @brief Pulse Counter (PCNT) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_PCNT_H +#define EM_PCNT_H + +#include "em_device.h" +#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup pcnt + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +/** PCNT0 Counter register size. */ +#if defined(_EFM32_GECKO_FAMILY) +#define PCNT0_CNT_SIZE (8) /**< PCNT0 counter is 8 bits. */ +#else +#define PCNT0_CNT_SIZE (16) /**< PCNT0 counter is 16 bits. */ +#endif + +#ifdef PCNT1 +/** PCNT1 Counter register size. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define PCNT1_CNT_SIZE (8) /**< PCNT1 counter is 8 bits. */ +#else +#define PCNT1_CNT_SIZE (16) /**< PCNT1 counter is 16 bits. */ +#endif +#endif + +#ifdef PCNT2 +/** PCNT2 Counter register size. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define PCNT2_CNT_SIZE (8) /**< PCNT2 counter is 8 bits. */ +#else +#define PCNT2_CNT_SIZE (16) /**< PCNT2 counter is 16 bits. */ +#endif +#endif + +/* Define values that can be used in case some state/mode are not defined for some devices.*/ +/** PCNT mode disable. */ +#define PCNT_MODE_DISABLE 0xFF +/** PCNT count event is none. */ +#define PCNT_CNT_EVENT_NONE 0xFF + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Mode selection. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +typedef enum { + /** Disable pulse counter. */ + pcntModeDisable = _PCNT_CTRL_MODE_DISABLE, + + /** Single input LFACLK oversampling mode (available in EM0-EM2). */ + pcntModeOvsSingle = _PCNT_CTRL_MODE_OVSSINGLE, + + /** Externally clocked single input counter mode (available in EM0-EM3). */ + pcntModeExtSingle = _PCNT_CTRL_MODE_EXTCLKSINGLE, + + /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ + pcntModeExtQuad = _PCNT_CTRL_MODE_EXTCLKQUAD, + +#if defined(_PCNT_CTRL_MODE_OVSQUAD1X) + /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ + pcntModeOvsQuad1 = _PCNT_CTRL_MODE_OVSQUAD1X, + + /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ + pcntModeOvsQuad2 = _PCNT_CTRL_MODE_OVSQUAD2X, + + /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ + pcntModeOvsQuad4 = _PCNT_CTRL_MODE_OVSQUAD4X, +#endif +} PCNT_Mode_TypeDef; + +#else +typedef enum { + /** Disable pulse counter. */ + pcntModeDisable = PCNT_MODE_DISABLE, + + /** Single input LFACLK oversampling mode (available in EM0-EM2). */ + pcntModeOvsSingle = _PCNT_CFG_MODE_OVSSINGLE, + + /** Externally clocked single input counter mode (available in EM0-EM3). */ + pcntModeExtSingle = _PCNT_CFG_MODE_EXTCLKSINGLE, + + /** Externally clocked quadrature decoder mode (available in EM0-EM3). */ + pcntModeExtQuad = _PCNT_CFG_MODE_EXTCLKQUAD, + + /** LFACLK oversampling quadrature decoder 1X mode (available in EM0-EM2). */ + pcntModeOvsQuad1 = _PCNT_CFG_MODE_OVSQUAD1X, + + /** LFACLK oversampling quadrature decoder 2X mode (available in EM0-EM2). */ + pcntModeOvsQuad2 = _PCNT_CFG_MODE_OVSQUAD2X, + + /** LFACLK oversampling quadrature decoder 4X mode (available in EM0-EM2). */ + pcntModeOvsQuad4 = _PCNT_CFG_MODE_OVSQUAD4X, +} PCNT_Mode_TypeDef; +#endif + +#if defined(_PCNT_CTRL_CNTEV_MASK) +/** Counter event selection. + * Note: unshifted values are being used for enumeration because multiple + * configuration structure members use this type definition. */ +typedef enum { + /** Counts up on up-count and down on down-count events. */ + pcntCntEventBoth = _PCNT_CTRL_CNTEV_BOTH, + + /** Only counts up on up-count events. */ + pcntCntEventUp = _PCNT_CTRL_CNTEV_UP, + + /** Only counts down on down-count events. */ + pcntCntEventDown = _PCNT_CTRL_CNTEV_DOWN, + + /** Never counts. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcntCntEventNone = _PCNT_CTRL_CNTEV_NONE +#else + pcntCntEventNone = PCNT_CNT_EVENT_NONE +#endif +} PCNT_CntEvent_TypeDef; +#endif + +/** PRS sources for @p s0PRS and @p s1PRS. */ +#if defined(_PCNT_INPUT_MASK) +typedef enum { + pcntPRSCh0 = 0, /**< PRS channel 0. */ + pcntPRSCh1 = 1, /**< PRS channel 1. */ + pcntPRSCh2 = 2, /**< PRS channel 2. */ + pcntPRSCh3 = 3, /**< PRS channel 3. */ +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH4) + pcntPRSCh4 = 4, /**< PRS channel 4. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH5) + pcntPRSCh5 = 5, /**< PRS channel 5. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH6) + pcntPRSCh6 = 6, /**< PRS channel 6. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH7) + pcntPRSCh7 = 7, /**< PRS channel 7. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH8) + pcntPRSCh8 = 8, /**< PRS channel 8. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH9) + pcntPRSCh9 = 9, /**< PRS channel 9. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH10) + pcntPRSCh10 = 10, /**< PRS channel 10. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH11) + pcntPRSCh11 = 11, /**< PRS channel 11. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH12) + pcntPRSCh12 = 12, /**< PRS channel 12. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH13) + pcntPRSCh13 = 13, /**< PRS channel 13. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH14) + pcntPRSCh14 = 14, /**< PRS channel 14. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH15) + pcntPRSCh15 = 15, /**< PRS channel 15. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH16) + pcntPRSCh16 = 16, /**< PRS channel 16. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH17) + pcntPRSCh17 = 17, /**< PRS channel 17. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH18) + pcntPRSCh18 = 18, /**< PRS channel 18. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH19) + pcntPRSCh19 = 19, /**< PRS channel 19. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH20) + pcntPRSCh20 = 20, /**< PRS channel 20. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH21) + pcntPRSCh21 = 21, /**< PRS channel 21. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH22) + pcntPRSCh22 = 22, /**< PRS channel 22. */ +#endif +#if defined(PCNT_INPUT_S0PRSSEL_PRSCH23) + pcntPRSCh23 = 23, /**< PRS channel 23. */ +#endif +} PCNT_PRSSel_TypeDef; +#elif defined(_SILICON_LABS_32B_SERIES_2) +typedef unsigned int PCNT_PRSSel_TypeDef; +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +/** PRS inputs of PCNT. */ +typedef enum { + pcntPRSInputS0 = 0, /** PRS input 0. */ + pcntPRSInputS1 = 1 /** PRS input 1. */ +} PCNT_PRSInput_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Initialization structure. */ +typedef struct { + /** Mode to operate in. */ + PCNT_Mode_TypeDef mode; + + /** Initial counter value (refer to reference manual for max value allowed). + * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. + * If using #pcntModeExtSingle or #pcntModeExtQuad modes, counter + * value is reset to HW reset value. */ + uint32_t counter; + + /** Initial top value (refer to reference manual for max value allowed). + * Only used for #pcntModeOvsSingle (and possibly #pcntModeDisable) modes. + * If using #pcntModeExtSingle or #pcntModeExtQuad modes, top + * value is reset to HW reset value. */ + uint32_t top; + + /** Polarity of incoming edge. + * @li #pcntModeExtSingle mode - if false, positive edges are counted, + * otherwise negative edges. + * @li #pcntModeExtQuad mode - if true, counting direction is inverted. */ + bool negEdge; + + /** Counting direction, only applicable for #pcntModeOvsSingle and + * #pcntModeExtSingle modes. */ + bool countDown; + + /** Enable filter, only available in #pcntModeOvsSingle* mode. */ + bool filter; + +#if defined(_SILICON_LABS_32B_SERIES_2) + /** Enable/disable PCNT counting during debug halt. Only in OVSSINGLE and OVSQUAD modes. */ + bool debugHalt; +#endif + +#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) + /** Set to true to enable hysteresis. When enabled, PCNT will always + * overflow and underflow to TOP/2. */ + bool hyst; +#endif + +#if defined(PCNT_CTRL_S1CDIR) + /** Set to true to enable S1 to determine the direction of counting in + * OVSSINGLE or EXTCLKSINGLE modes. @n + * When S1 is high, the count direction is given by CNTDIR, and when S1 is + * low, the count direction is the opposite. */ + bool s1CntDir; +#endif + +#if defined(_PCNT_CTRL_CNTEV_SHIFT) + /** Selects whether the regular counter responds to up-count events, + * down-count events, both, or none. */ + PCNT_CntEvent_TypeDef cntEvent; +#endif + +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) + /** Selects whether the auxiliary counter responds to up-count events, + * down-count events, both, or none. */ + PCNT_CntEvent_TypeDef auxCntEvent; +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) + /** Select PRS channel as input to S0IN in PCNTx_INPUT register. */ + PCNT_PRSSel_TypeDef s0PRS; + + /** Select PRS channel as input to S1IN in PCNTx_INPUT register. */ + PCNT_PRSSel_TypeDef s1PRS; +#endif +} PCNT_Init_TypeDef; + +/** Default Debug. */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_DEBUG_HALT true, +#else +#define DEFAULT_DEBUG_HALT +#endif + +/** Default Mode. */ +#define DEFAULT_MODE pcntModeDisable, /**< Disabled by default. */ + +/** Default Hysteresis. */ +#if defined(PCNT_CTRL_HYST) || defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_HYST false, /**< Hysteresis disabled. */ +#else +#define DEFAULT_HYST +#endif + +/** Default counter direction*/ +#if defined(PCNT_CTRL_S1CDIR) +#define DEFAULT_CDIR true, /**< Counter direction is given by CNTDIR. */ +#else +#define DEFAULT_CDIR +#endif + +/** Default count event*/ +#if defined(_PCNT_CTRL_CNTEV_SHIFT) +#define DEFAULT_CNTEV pcntCntEventUp, /**< Regular counter counts up on upcount events. */ +#else +#define DEFAULT_CNTEV +#endif + +/** Default auxiliary count event. */ +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) +#define DEFAULT_AUXCNTEV pcntCntEventNone, /**< Auxiliary counter doesn't respond to events. */ +#else +#define DEFAULT_AUXCNTEV +#endif + +/** Default selected PRS channel as S0IN and S1IN. */ +#if defined(_PCNT_INPUT_MASK) +#define DEFAULT_PRS_CH pcntPRSCh0, /**< PRS channel 0 selected as S0IN and as S1IN. */ +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define DEFAULT_PRS_CH 0u, +#else +#define DEFAULT_PRS_CH +#endif + +/** Default configuration for PCNT initialization structure. */ +#define PCNT_INIT_DEFAULT \ + { \ + DEFAULT_MODE /* Default mode. */ \ + _PCNT_CNT_RESETVALUE, /* Default counter HW reset value. */ \ + _PCNT_TOP_RESETVALUE, /* Default counter HW reset value. */ \ + false, /* Use positive edge. */ \ + false, /* Up-counting. */ \ + false, /* Filter disabled. */ \ + DEFAULT_DEBUG_HALT /* Debug Halt enabled. */ \ + DEFAULT_HYST /* Default Hysteresis. */ \ + DEFAULT_CDIR /* Default CNTDIR. */ \ + DEFAULT_CNTEV /* Faults CNTEV. */ \ + DEFAULT_AUXCNTEV /* Default AUXCNTEV. */ \ + DEFAULT_PRS_CH /* PRS channel 0 selected as S0IN. */ \ + DEFAULT_PRS_CH /* PRS channel 0 selected as S1IN. */ \ + } + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +/** Filter initialization structure */ +typedef struct { + /** Used only in OVSINGLE and OVSQUAD1X-4X modes. To use this, enable filter by + * setting filter to true during PCNT_Init(). Filter length = (filtLen + 5) LFACLK cycles. */ + uint8_t filtLen; + + /** When set, removes flutter from Quaddecoder inputs S0IN and S1IN. + * Available only in OVSQUAD1X-4X modes. */ + bool flutterrm; +} PCNT_Filter_TypeDef; +#endif + +/** Default configuration for PCNT initialization structure. */ +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +#define PCNT_FILTER_DEFAULT \ + { \ + 0, /* Default length is 5 LFACLK cycles. */ \ + false /* No flutter removal. */ \ + } +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) + +/** Modes for Triggered Compare and Clear module. */ +typedef enum { + /** Triggered compare and clear not enabled. */ + tccModeDisabled = _PCNT_CTRL_TCCMODE_DISABLED, + + /** Compare and clear performed on each (optionally prescaled) LFA clock cycle. */ + tccModeLFA = _PCNT_CTRL_TCCMODE_LFA, + + /** Compare and clear performed on PRS edges. Polarity defined by prsPolarity. */ + tccModePRS = _PCNT_CTRL_TCCMODE_PRS +} PCNT_TCCMode_TypeDef; + +/** Prescaler values for LFA compare and clear events. Only has effect when TCC mode is LFA. */ +typedef enum { + /** Compare and clear event each LFA cycle. */ + tccPrescDiv1 = _PCNT_CTRL_TCCPRESC_DIV1, + + /** Compare and clear event every other LFA cycle. */ + tccPrescDiv2 = _PCNT_CTRL_TCCPRESC_DIV2, + + /** Compare and clear event every 4th LFA cycle. */ + tccPrescDiv4 = _PCNT_CTRL_TCCPRESC_DIV4, + + /** Compare and clear event every 8th LFA cycle. */ + tccPrescDiv8 = _PCNT_CTRL_TCCPRESC_DIV8 +} PCNT_TCCPresc_Typedef; + +/** Compare modes for TCC module. */ +typedef enum { + /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP. */ + tccCompLTOE = _PCNT_CTRL_TCCCOMP_LTOE, + + /** Compare match if PCNT_CNT is greater than or equal to PCNT_TOP. */ + tccCompGTOE = _PCNT_CTRL_TCCCOMP_GTOE, + + /** Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater + * than, or equal to PCNT_TOP[7:0]. */ + tccCompRange = _PCNT_CTRL_TCCCOMP_RANGE +} PCNT_TCCComp_Typedef; + +/** TCC initialization structure. */ +typedef struct { + /** Mode to operate in. */ + PCNT_TCCMode_TypeDef mode; + + /** Prescaler value for LFACLK in LFA mode. */ + PCNT_TCCPresc_Typedef prescaler; + + /** Choose the event that will trigger a clear. */ + PCNT_TCCComp_Typedef compare; + + /** PRS input to TCC module, either for gating the PCNT clock, triggering the TCC comparison, or both. */ + PCNT_PRSSel_TypeDef tccPRS; + + /** TCC PRS input polarity. @n + * False = Rising edge for comparison trigger, and PCNT clock gated when PRS signal is high. @n + * True = Falling edge for comparison trigger, and PCNT clock gated when PRS signal is low. */ + bool prsPolarity; + + /** Enable gating PCNT input clock through TCC PRS signal. + * Polarity selection is done through prsPolarity. */ + bool prsGateEnable; +} PCNT_TCC_TypeDef; + +/** TCC Default. */ +#define PCNT_TCC_DEFAULT \ + { \ + tccModeDisabled, /* Disabled by default. */ \ + tccPrescDiv1, /* Do not prescale LFA clock in LFA mode. */ \ + tccCompLTOE, /* Clear when CNT <= TOP. */ \ + pcntPRSCh0, /* Select PRS channel 0 as input to TCC. */ \ + false, /* PRS polarity is rising edge, and gate when 1. */ \ + false /* Do not gate PCNT counter input. */ \ + } + +#endif +/* defined(PCNT_CTRL_TCCMODE_DEFAULT) */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the pulse counter value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_CounterGet(PCNT_TypeDef *pcnt) +{ + return pcnt->CNT; +} + +#if defined(_PCNT_AUXCNT_MASK) +/***************************************************************************//** + * @brief + * Get the auxiliary counter value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current auxiliary counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_AuxCounterGet(PCNT_TypeDef *pcnt) +{ + return pcnt->AUXCNT; +} +#endif + +void PCNT_CounterReset(PCNT_TypeDef *pcnt); +void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top); + +/***************************************************************************//** + * @brief + * Set a counter value. + * + * @details + * Pulse counter is disabled while changing counter value and re-enabled + * (if originally enabled) when counter value has been set. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when using + * an external clock to clock the PCNT module since stall time may be + * undefined in that case. The counter should normally only be set when + * operating in (or about to enable) #pcntModeOvsSingle mode. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] count + * Value to set in counter register. + ******************************************************************************/ +__STATIC_INLINE void PCNT_CounterSet(PCNT_TypeDef *pcnt, uint32_t count) +{ + PCNT_CounterTopSet(pcnt, count, pcnt->TOP); +} + +void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode); +bool PCNT_IsEnabled(PCNT_TypeDef *pcnt); +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable); +#endif +void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init); + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable); +#endif + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, + PCNT_PRSInput_TypeDef prsInput, + bool enable); +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) +void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config); +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending PCNT interrupts. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * Pending PCNT interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntClear(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcnt->IFC = flags; +#else + pcnt->IF_CLR = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more PCNT interrupts. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntDisable(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(PCNT_HAS_SET_CLEAR) + pcnt->IEN_CLR = flags; +#else + pcnt->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more PCNT interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * PCNT_IntClear() prior to enabling the interrupt. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntEnable(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(PCNT_HAS_SET_CLEAR) + pcnt->IEN_SET = flags; +#else + pcnt->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending PCNT interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * PCNT interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_IntGet(PCNT_TypeDef *pcnt) +{ + return pcnt->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending PCNT interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] pcnt + * Pointer to thePCNT peripheral register block. + * + * @return + * Pending and enabled PCNT interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in PCNT_IEN_nnn + * register (PCNT_IEN_nnn) and + * - the OR combination of valid interrupt flags of the PCNT module + * (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_IntGetEnabled(PCNT_TypeDef *pcnt) +{ + uint32_t ien; + + /* Store pcnt->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = pcnt->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return pcnt->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending PCNT interrupts from SW. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @param[in] flags + * PCNT interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for PCNT module (PCNT_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void PCNT_IntSet(PCNT_TypeDef *pcnt, uint32_t flags) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + pcnt->IFS = flags; +#else + pcnt->IF_SET = flags; +#endif +} + +#if defined(_PCNT_LOCK_MASK) +/***************************************************************************//** + * @brief + * Lock PCNT registers. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @note When PCNT registers are locked PCNT_CFG, PCNT_EN, PCNT_SWRST, PCNT_CMD, + * PCNT_CTRL, PCNT_OVSCTRL, PCNT_CNT, PCNT_TOP, and PCNT_TOPB registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Lock(PCNT_TypeDef *pcnt) +{ + pcnt->LOCK = ~PCNT_LOCK_PCNTLOCKKEY_UNLOCK; +} +#endif + +#if defined(_PCNT_LOCK_MASK) +/***************************************************************************//** + * @brief + * Unlock PCNT registers. + * + * @param[in] pcnt + * Pointer to thePCNT peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Unlock(PCNT_TypeDef *pcnt) +{ + pcnt->LOCK = PCNT_LOCK_PCNTLOCKKEY_UNLOCK; +} +#endif + +void PCNT_Reset(PCNT_TypeDef *pcnt); + +/***************************************************************************//** + * @brief + * Get the pulse counter top buffer value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter top buffer value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_TopBufferGet(PCNT_TypeDef *pcnt) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOPB) { + } +#endif + return pcnt->TOPB; +} + +void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val); + +/***************************************************************************//** + * @brief + * Get the pulse counter top value. + * + * @param[in] pcnt + * Pointer to the PCNT peripheral register block. + * + * @return + * Current pulse counter top value. + ******************************************************************************/ +__STATIC_INLINE uint32_t PCNT_TopGet(PCNT_TypeDef *pcnt) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while (pcnt->SYNCBUSY & PCNT_SYNCBUSY_TOP) { + } +#endif + return pcnt->TOP; +} + +void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val); + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low-frequency domain to complete. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void PCNT_Sync(PCNT_TypeDef *pcnt, uint32_t mask) +{ + /* Avoid deadlock if modifying the same register twice when freeze mode is + * activated. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + if (pcnt->FREEZE & PCNT_FREEZE_REGFREEZE) { + return; + } +#endif + + /* Wait for any pending previous write operation to have been completed in + * low-frequency domain. */ + while (pcnt->SYNCBUSY & mask) { + } +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start the main PCNT counter. + * + * @details + * This function will send a start command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the start command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StartMainCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STARTCNT; +} + +/***************************************************************************//** + * @brief + * Stop the main PCNT counter. + * + * @details + * This function will send a stop command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the stop command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StopMainCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STOPCNT; +} + +/***************************************************************************//** + * @brief + * Start the auxiliary PCNT counter. + * + * @details + * This function will send a start command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the start command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StartAuxCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STARTAUXCNT; +} + +/***************************************************************************//** + * @brief + * Stop the auxiliary PCNT counter. + * + * @details + * This function will send a stop command to the PCNT peripheral. The PCNT + * peripheral will use some LF clock ticks before the command is executed. + * The @ref PCNT_Sync() function can be used to wait for the stop command + * to be executed. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @note + * This function requires the PCNT to be enabled. + ******************************************************************************/ +__STATIC_INLINE void PCNT_StopAuxCnt(PCNT_TypeDef *pcnt) +{ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_STOPAUXCNT; +} +#endif + +/** @} (end addtogroup pcnt) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ +#endif /* EM_PCNT_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h index 0a27947..2e3cad0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h @@ -1,1164 +1,1164 @@ -/***************************************************************************//** - * @file - * @brief Peripheral Reflex System (PRS) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_PRS_H -#define EM_PRS_H - -#include "em_device.h" -#include "em_gpio.h" - -#include -#include - -#if defined(PRS_COUNT) && (PRS_COUNT > 0) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup prs - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM -#elif defined(_EFM32_GECKO_FAMILY) -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT 0 -#else -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT -#endif - -#if !defined(_EFM32_GECKO_FAMILY) -/** PRS asynchronous support */ -#define PRS_ASYNC_SUPPORTED 1 -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Some devices have renamed signals so some of these signals are mapped to - common names. */ -#if defined(PRS_USART0_RXDATAV) -#define PRS_USART0_RXDATA PRS_USART0_RXDATAV -#endif -#if defined(PRS_USART1_RXDATAV) -#define PRS_USART1_RXDATA PRS_USART1_RXDATAV -#endif -#if defined(PRS_USART2_RXDATAV) -#define PRS_USART2_RXDATA PRS_USART2_RXDATAV -#endif -#if defined(PRS_BURTC_OVERFLOW) -#define PRS_BURTC_OF PRS_BURTC_OVERFLOW -#endif -#if defined(PRS_BURTC_COMP0) -#define PRS_BURTC_COMP PRS_BURTC_COMP0 -#endif -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** PRS Channel type. */ -typedef enum { - prsTypeAsync, /**< Asynchronous channel type. */ - prsTypeSync /**< Synchronous channel type.*/ -} PRS_ChType_t; - -/** Edge detection type. */ -typedef enum { - prsEdgeOff, /**< Leave signal as is. */ - prsEdgePos, /**< Generate pulses on positive edge. */ - prsEdgeNeg, /**< Generate pulses on negative edge. */ - prsEdgeBoth /**< Generate pulses on both edges. */ -} PRS_Edge_TypeDef; - -#if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) -/** Logic functions that can be used when combining two PRS channels. */ -typedef enum { - prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, /**< Logical 0. */ - prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, /**< A NOR B. */ - prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, /**< (!A) NOR B. */ - prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, /**< !A. */ - prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, /**< A AND (!B). */ - prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, /**< !B. */ - prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, /**< A XOR B. */ - prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, /**< A NAND B. */ - prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, /**< A AND B. */ - prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, /**< A XNOR B. */ - prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, /**< B. */ - prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, /**< (!A) OR B. */ - prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, /**< A. */ - prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, /**< A OR (!B). */ - prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, /**< A OR B. */ - prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, /**< Logical 1. */ -} PRS_Logic_t; -#endif - -/** PRS Signal. */ -typedef enum { -#if defined(_PRS_SYNC_CH_CTRL_SOURCESEL_MASK) - prsSignalNone = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x0 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ - prsSignalSW = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x1 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ -#else - prsSignalNone = PRS_CH_CTRL_SOURCESEL_NONE | (0x0 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ - prsSignalSW = PRS_CH_CTRL_SOURCESEL_NONE | (0x1 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ -#endif - -#if defined(PRS_PRS_CH11) - prsSignalPRS_CH0 = PRS_PRS_CH0, /**< PRS_CH0 signal */ - prsSignalPRS_CH1 = PRS_PRS_CH1, /**< PRS_CH1 signal */ - prsSignalPRS_CH2 = PRS_PRS_CH2, /**< PRS_CH2 signal */ - prsSignalPRS_CH3 = PRS_PRS_CH3, /**< PRS_CH3 signal */ - prsSignalPRS_CH4 = PRS_PRS_CH4, /**< PRS_CH4 signal */ - prsSignalPRS_CH5 = PRS_PRS_CH5, /**< PRS_CH5 signal */ - prsSignalPRS_CH6 = PRS_PRS_CH6, /**< PRS_CH6 signal */ - prsSignalPRS_CH7 = PRS_PRS_CH7, /**< PRS_CH7 signal */ - prsSignalPRS_CH8 = PRS_PRS_CH8, /**< PRS_CH8 signal */ - prsSignalPRS_CH9 = PRS_PRS_CH9, /**< PRS_CH9 signal */ - prsSignalPRS_CH10 = PRS_PRS_CH10, /**< PRS_CH10 signal */ - prsSignalPRS_CH11 = PRS_PRS_CH11, /**< PRS_CH11 signal */ -#endif -#if defined(PRS_PRS_CH23) - prsSignalPRS_CH12 = PRS_PRS_CH12, /**< PRS_CH12 signal */ - prsSignalPRS_CH13 = PRS_PRS_CH13, /**< PRS_CH13 signal */ - prsSignalPRS_CH14 = PRS_PRS_CH14, /**< PRS_CH14 signal */ - prsSignalPRS_CH15 = PRS_PRS_CH15, /**< PRS_CH15 signal */ - prsSignalPRS_CH16 = PRS_PRS_CH16, /**< PRS_CH16 signal */ - prsSignalPRS_CH17 = PRS_PRS_CH17, /**< PRS_CH17 signal */ - prsSignalPRS_CH18 = PRS_PRS_CH18, /**< PRS_CH18 signal */ - prsSignalPRS_CH19 = PRS_PRS_CH19, /**< PRS_CH19 signal */ - prsSignalPRS_CH20 = PRS_PRS_CH20, /**< PRS_CH20 signal */ - prsSignalPRS_CH21 = PRS_PRS_CH21, /**< PRS_CH21 signal */ - prsSignalPRS_CH22 = PRS_PRS_CH22, /**< PRS_CH22 signal */ - prsSignalPRS_CH23 = PRS_PRS_CH23, /**< PRS_CH23 signal */ -#endif - -#if defined(PRS_ADC0_SINGLE) - prsSignalADC0_SINGLE = PRS_ADC0_SINGLE, /**< ADC0_SINGLE signal */ - prsSignalADC0_SCAN = PRS_ADC0_SCAN, /**< ADC0_SCAN signal */ -#endif -#if defined(PRS_ADC1_SINGLE) - prsSignalADC1_SINGLE = PRS_ADC1_SINGLE, /**< ADC1_SINGLE signal */ - prsSignalADC1_SCAN = PRS_ADC1_SCAN, /**< ADC1_SCAN signal */ -#endif - - /* Timer Signals */ -#if defined(TIMER0) - prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ - prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ - prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ - prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ - prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER1) - prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ - prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ - prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ - prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ - prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER2) - prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ - prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ - prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ - prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ - prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER3) - prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ - prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ - prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ - prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ - prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ -#if defined(PRS_TIMER1_CC3) - prsSignalTIMER1_CC3 = PRS_TIMER1_CC3, /**< TIMER3 capture/compare channel 3 Signal. */ -#endif -#endif -#if defined(TIMER4) - prsSignalTIMER4_UF = PRS_TIMER4_UF, /**< TIMER4 underflow Signal. */ - prsSignalTIMER4_OF = PRS_TIMER4_OF, /**< TIMER4 overflow Signal. */ - prsSignalTIMER4_CC0 = PRS_TIMER4_CC0, /**< TIMER4 capture/compare channel 0 Signal. */ - prsSignalTIMER4_CC1 = PRS_TIMER4_CC1, /**< TIMER4 capture/compare channel 1 Signal. */ - prsSignalTIMER4_CC2 = PRS_TIMER4_CC2, /**< TIMER4 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER5) - prsSignalTIMER5_UF = PRS_TIMER5_UF, /**< TIMER5 underflow Signal. */ - prsSignalTIMER5_OF = PRS_TIMER5_OF, /**< TIMER5 overflow Signal. */ - prsSignalTIMER5_CC0 = PRS_TIMER5_CC0, /**< TIMER5 capture/compare channel 0 Signal. */ - prsSignalTIMER5_CC1 = PRS_TIMER5_CC1, /**< TIMER5 capture/compare channel 1 Signal. */ - prsSignalTIMER5_CC2 = PRS_TIMER5_CC2, /**< TIMER5 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER6) - prsSignalTIMER6_UF = PRS_TIMER6_UF, /**< TIMER6 underflow Signal. */ - prsSignalTIMER6_OF = PRS_TIMER6_OF, /**< TIMER6 overflow Signal. */ - prsSignalTIMER6_CC0 = PRS_TIMER6_CC0, /**< TIMER6 capture/compare channel 0 Signal. */ - prsSignalTIMER6_CC1 = PRS_TIMER6_CC1, /**< TIMER6 capture/compare channel 1 Signal. */ - prsSignalTIMER6_CC2 = PRS_TIMER6_CC2, /**< TIMER6 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER7) - prsSignalTIMER7_UF = PRS_TIMER7_UF, /**< TIMER7 underflow Signal. */ - prsSignalTIMER7_OF = PRS_TIMER7_OF, /**< TIMER7 overflow Signal. */ - prsSignalTIMER7_CC0 = PRS_TIMER7_CC0, /**< TIMER7 capture/compare channel 0 Signal. */ - prsSignalTIMER7_CC1 = PRS_TIMER7_CC1, /**< TIMER7 capture/compare channel 1 Signal. */ - prsSignalTIMER7_CC2 = PRS_TIMER7_CC2, /**< TIMER7 capture/compare channel 2 Signal. */ -#endif -#if defined(PRS_LETIMER0_CH0) - prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ - prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ -#endif -#if defined(PRS_LETIMER1_CH0) - prsSignalLETIMER1_CH0 = PRS_LETIMER1_CH0, /**< LETIMER1 channel 0 Signal. */ - prsSignalLETIMER1_CH1 = PRS_LETIMER1_CH1, /**< LETIMER1 channel 1 Signal. */ -#endif -#if defined(PRS_PCNT0_TCC) - prsSignalPCNT0_TCC = PRS_PCNT0_TCC, /**< PCNT0_TCC Signal. */ -#endif -#if defined(PRS_PCNT0_UFOF) - prsSignalPCNT0_UFOF = PRS_PCNT0_UFOF, /**< PCNT0_TCC Signal. */ - prsSignalPCNT0_DIR = PRS_PCNT0_DIR, /**< PCNT0_TCC Signal. */ -#endif -#if defined(PRS_PCNT1_TCC) - prsSignalPCNT1_TCC = PRS_PCNT1_TCC, /**< PCNT1_TCC Signal. */ - prsSignalPCNT1_UFOF = PRS_PCNT1_UFOF, /**< PCNT1_TCC Signal. */ - prsSignalPCNT1_DIR = PRS_PCNT1_DIR, /**< PCNT1_TCC Signal. */ -#endif -#if defined(PRS_PCNT2_TCC) - prsSignalPCNT2_TCC = PRS_PCNT2_TCC, /**< PCNT2_TCC Signal. */ - prsSignalPCNT2_UFOF = PRS_PCNT2_UFOF, /**< PCNT2_TCC Signal. */ - prsSignalPCNT2_DIR = PRS_PCNT2_DIR, /**< PCNT2_TCC Signal. */ -#endif -#if defined(PRS_CRYOTIMER_PERIOD) - prsSignalCRYOTIMER_PERIOD = PRS_CRYOTIMER_PERIOD, /**< CRYOTIMER_PERIOD Signal. */ -#endif -#if defined(PRS_CORE_CTIOUT0) - prsSignalCORE_CTIOUT0 = PRS_CORE_CTIOUT0, /**< CORE CTIOUT0 Signal. */ - prsSignalCORE_CTIOUT1 = PRS_CORE_CTIOUT1, /**< CORE CTIOUT1 Signal. */ - prsSignalCORE_CTIOUT2 = PRS_CORE_CTIOUT2, /**< CORE CTIOUT2 Signal. */ - prsSignalCORE_CTIOUT3 = PRS_CORE_CTIOUT3, /**< CORE CTIOUT3 Signal. */ -#endif -#if defined(PRS_CMUL_CLKOUT0) - prsSignalCMUL_CLKOUT0 = PRS_CMUL_CLKOUT0, /**< CMU CLKOUT0 Signal. */ - prsSignalCMUL_CLKOUT1 = PRS_CMUL_CLKOUT1, /**< CMU CLKOUT1 Signal. */ - prsSignalCMUL_CLKOUT2 = PRS_CMUL_CLKOUT2, /**< CMU CLKOUT2 Signal. */ -#endif -#if defined(PRS_PRSL_ASYNCH0) - prsSignalPRSL_ASYNCH0 = PRS_PRSL_ASYNCH0, /**< PRS channel 0 Signal. */ - prsSignalPRSL_ASYNCH1 = PRS_PRSL_ASYNCH1, /**< PRS channel 1 Signal. */ - prsSignalPRSL_ASYNCH2 = PRS_PRSL_ASYNCH2, /**< PRS channel 2 Signal. */ - prsSignalPRSL_ASYNCH3 = PRS_PRSL_ASYNCH3, /**< PRS channel 3 Signal. */ - prsSignalPRSL_ASYNCH4 = PRS_PRSL_ASYNCH4, /**< PRS channel 4 Signal. */ - prsSignalPRSL_ASYNCH5 = PRS_PRSL_ASYNCH5, /**< PRS channel 5 Signal. */ - prsSignalPRSL_ASYNCH6 = PRS_PRSL_ASYNCH6, /**< PRS channel 6 Signal. */ - prsSignalPRSL_ASYNCH7 = PRS_PRSL_ASYNCH7, /**< PRS channel 7 Signal. */ - prsSignalPRS_ASYNCH8 = PRS_PRS_ASYNCH8, /**< PRS channel 8 Signal. */ - prsSignalPRS_ASYNCH9 = PRS_PRS_ASYNCH9, /**< PRS channel 9 Signal. */ - prsSignalPRS_ASYNCH10 = PRS_PRS_ASYNCH10, /**< PRS channel 10 Signal. */ - prsSignalPRS_ASYNCH11 = PRS_PRS_ASYNCH11, /**< PRS channel 11 Signal. */ -#endif - - /* RTC/RTCC/SYSRTC/BURTC Signals */ -#if defined(PRS_RTC_OF) - prsSignalRTC_OF = PRS_RTC_OF, /**< RTC_OF signal. */ - prsSignalRTC_COMP0 = PRS_RTC_COMP0, /**< RTC_COMP0 signal. */ - prsSignalRTC_COMP1 = PRS_RTC_COMP1, /**< RTC_COMP1 signal. */ -#if defined(PRS_RTC_COMP5) - prsSignalRTC_COMP2 = PRS_RTC_COMP2, /**< RTC_COMP2 signal. */ - prsSignalRTC_COMP3 = PRS_RTC_COMP3, /**< RTC_COMP3 signal. */ - prsSignalRTC_COMP4 = PRS_RTC_COMP4, /**< RTC_COMP4 signal. */ - prsSignalRTC_COMP5 = PRS_RTC_COMP5, /**< RTC_COMP5 signal. */ -#endif -#endif -#if defined(RTCC) - prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ - prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ - prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ -#endif -#if defined(BURTC) - prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ - prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ -#endif -#if defined(SYSRTC0) - prsSignalSYSRTC0_GRP0OUT0 = PRS_SYSRTC0_GRP0OUT0, /**< SYSRTC GRP0OUT0 Signal. */ - prsSignalSYSRTC0_GRP0OUT1 = PRS_SYSRTC0_GRP0OUT1, /**< SYSRTC GRP0OUT1 Signal. */ - prsSignalSYSRTC0_GRP1OUT0 = PRS_SYSRTC0_GRP1OUT0, /**< SYSRTC GRP1OUT0 Signal. */ - prsSignalSYSRTC0_GRP1OUT1 = PRS_SYSRTC0_GRP1OUT1, /**< SYSRTC GRP1OUT1 Signal. */ -#endif -#if defined(PRS_HFXO0L_STATUS) - prsSignalHFXO0L_STATUS = PRS_HFXO0L_STATUS, /**< HFXO0L_STATUS Signal. */ - prsSignalHFXO0L_STATUS1 = PRS_HFXO0L_STATUS1, /**< HFXO0L_STATUS1 Signal. */ -#endif -#if defined(PRS_HFRCO0_COREEN) - prsSignalHFRCO0_COREEN = PRS_HFRCO0_COREEN, /**< HFRCO0_COREEN Signal. */ - prsSignalHFRCO0_STATE0 = PRS_HFRCO0_STATE0, /**< HFRCO0_STATE0 Signal. */ - prsSignalHFRCO0_STATE1 = PRS_HFRCO0_STATE1, /**< HFRCO0_STATE1 Signal. */ - prsSignalHFRCO0_STATE2 = PRS_HFRCO0_STATE2, /**< HFRCO0_STATE2 Signal. */ -#endif -#if defined(PRS_HFRCOEM23_COREEN) - prsSignalHFRCOEM23_COREEN = PRS_HFRCOEM23_COREEN, /**< HFRCOEM23_COREEN Signal. */ - prsSignalHFRCOEM23_STATE0 = PRS_HFRCOEM23_STATE0, /**< HFRCOEM23_STATE0 Signal. */ - prsSignalHFRCOEM23_STATE1 = PRS_HFRCOEM23_STATE1, /**< HFRCOEM23_STATE1 Signal. */ - prsSignalHFRCOEM23_STATE2 = PRS_HFRCOEM23_STATE2, /**< HFRCOEM23_STATE2 Signal. */ -#endif - - /* ACMP Signals */ -#if defined(ACMP0) - prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ -#endif -#if defined(ACMP1) - prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ -#endif -#if defined(ACMP2) - prsSignalACMP2_OUT = PRS_ACMP2_OUT, /**< ACMP2 output Signal. */ -#endif -#if defined(ACMP3) - prsSignalACMP3_OUT = PRS_ACMP3_OUT, /**< ACMP3 output Signal. */ -#endif - - /* VDAC Signals */ -#if defined(VDAC0) & (_SILICON_LABS_32B_SERIES >= 2) - prsSignalVDAC0_CH0WARM = PRS_VDAC0L_CH0WARM, /**< VDAC0 channel 0 warmed Signal. */ - prsSignalVDAC0_CH1WARM = PRS_VDAC0L_CH1WARM, /**< VDAC0 channel 1 warmed Signal. */ - prsSignalVDAC0_CH0DONE = PRS_VDAC0L_CH0DONEASYNC, /**< VDAC0 channel 0 conversion done Signal. */ - prsSignalVDAC0_CH1DONE = PRS_VDAC0L_CH1DONEASYNC, /**< VDAC0 channel 1 conversion done Signal. */ - prsSignalVDAC0_INTERNALTIMEROF = PRS_VDAC0L_INTERNALTIMEROF, /**< VDAC0 internal timer overflow Signal. */ - prsSignalVDAC0_REFRESHTIMEROF = PRS_VDAC0L_REFRESHTIMEROF, /**< VDAC0 internal timer overflow Signal. */ -#endif -#if defined(PRS_VDAC0_OPA3) - prsSignalVDAC0_CH0 = PRS_VDAC0_CH0, /**< VDAC0_CH0 Signal. */ - prsSignalVDAC0_CH1 = PRS_VDAC0_CH1, /**< VDAC0_CH1 Signal. */ - prsSignalVDAC0_OPA0 = PRS_VDAC0_OPA0, /**< VDAC0_OPA0 Signal. */ - prsSignalVDAC0_OPA1 = PRS_VDAC0_OPA1, /**< VDAC0_OPA1 Signal. */ - prsSignalVDAC0_OPA2 = PRS_VDAC0_OPA2, /**< VDAC0_OPA2 Signal. */ - prsSignalVDAC0_OPA3 = PRS_VDAC0_OPA3, /**< VDAC0_OPA3 Signal. */ -#endif -#if defined(VDAC1) & (_SILICON_LABS_32B_SERIES >= 2) - prsSignalVDAC1_CH0WARM = PRS_VDAC1L_CH0WARM, /**< VDAC1 channel 0 warmed Signal. */ - prsSignalVDAC1_CH1WARM = PRS_VDAC1L_CH1WARM, /**< VDAC1 channel 1 warmed Signal. */ - prsSignalVDAC1_CH0DONE = PRS_VDAC1L_CH0DONEASYNC, /**< VDAC1 channel 0 conversion done Signal. */ - prsSignalVDAC1_CH1DONE = PRS_VDAC1L_CH1DONEASYNC, /**< VDAC1 channel 1 conversion done Signal. */ - prsSignalVDAC1_INTERNALTIMEROF = PRS_VDAC1L_INTERNALTIMEROF, /**< VDAC1 internal timer overflow Signal. */ - prsSignalVDAC1_REFRESHTIMEROF = PRS_VDAC1L_REFRESHTIMEROF, /**< VDAC1 internal timer overflow Signal. */ -#endif - -#if defined(PRS_LESENSE_SCANRES15) - prsSignalLESENSE_SCANRES0 = PRS_LESENSE_SCANRES0, /**< LESENSE_SCANRES0 Signal. */ - prsSignalLESENSE_SCANRES1 = PRS_LESENSE_SCANRES1, /**< LESENSE_SCANRES1 Signal. */ - prsSignalLESENSE_SCANRES2 = PRS_LESENSE_SCANRES2, /**< LESENSE_SCANRES2 Signal. */ - prsSignalLESENSE_SCANRES3 = PRS_LESENSE_SCANRES3, /**< LESENSE_SCANRES3 Signal. */ - prsSignalLESENSE_SCANRES4 = PRS_LESENSE_SCANRES4, /**< LESENSE_SCANRES4 Signal. */ - prsSignalLESENSE_SCANRES5 = PRS_LESENSE_SCANRES5, /**< LESENSE_SCANRES5 Signal. */ - prsSignalLESENSE_SCANRES6 = PRS_LESENSE_SCANRES6, /**< LESENSE_SCANRES6 Signal. */ - prsSignalLESENSE_SCANRES7 = PRS_LESENSE_SCANRES7, /**< LESENSE_SCANRES7 Signal. */ - prsSignalLESENSE_SCANRES8 = PRS_LESENSE_SCANRES8, /**< LESENSE_SCANRES8 Signal. */ - prsSignalLESENSE_SCANRES9 = PRS_LESENSE_SCANRES9, /**< LESENSE_SCANRES9 Signal. */ - prsSignalLESENSE_SCANRES10 = PRS_LESENSE_SCANRES10, /**< LESENSE_SCANRES10 Signal. */ - prsSignalLESENSE_SCANRES11 = PRS_LESENSE_SCANRES11, /**< LESENSE_SCANRES11 Signal. */ - prsSignalLESENSE_SCANRES12 = PRS_LESENSE_SCANRES12, /**< LESENSE_SCANRES12 Signal. */ - prsSignalLESENSE_SCANRES13 = PRS_LESENSE_SCANRES13, /**< LESENSE_SCANRES13 Signal. */ - prsSignalLESENSE_SCANRES14 = PRS_LESENSE_SCANRES14, /**< LESENSE_SCANRES14 Signal. */ - prsSignalLESENSE_SCANRES15 = PRS_LESENSE_SCANRES15, /**< LESENSE_SCANRES15 Signal. */ -#endif -#if defined(PRS_LESENSE_DEC2) - prsSignalLESENSE_DEC0 = PRS_LESENSE_DEC0, /**< LESENSE_DEC0 Signal. */ - prsSignalLESENSE_DEC1 = PRS_LESENSE_DEC1, /**< LESENSE_DEC1 Signal. */ - prsSignalLESENSE_DEC2 = PRS_LESENSE_DEC2, /**< LESENSE_DEC2 Signal. */ -#endif -#if defined(PRS_LESENSE_DECOUT2) - prsSignalLESENSE_DECOUT0 = PRS_LESENSE_DECOUT0, /**< LESENSE_DECOUT0 Signal. */ - prsSignalLESENSE_DECOUT1 = PRS_LESENSE_DECOUT1, /**< LESENSE_DECOUT1 Signal. */ - prsSignalLESENSE_DECOUT2 = PRS_LESENSE_DECOUT2, /**< LESENSE_DECOUT2 Signal. */ -#endif -#if defined(PRS_LESENSE_DECCMP) - prsSignalLESENSE_DECCMP = PRS_LESENSE_DECCMP, /**< LESENSE_DECCMP Signal. */ -#endif -#if defined(PRS_LESENSE_MEASACT) - prsSignalLESENSE_MEASACT = PRS_LESENSE_MEASACT, /**< LESENSE_MEASACT Signal. */ -#endif - - /* USART Signals */ -#if defined(USART0) - prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 TX complete Signal. */ -#if defined(PRS_USART0_RXDATA) - prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 RX data available Signal. */ -#endif -#if defined(PRS_USART0_RXDATAV) - prsSignalUSART0_RXDATAV = PRS_USART0_RXDATAV, /**< USART0 RX data available Signal. */ -#endif -#if defined(PRS_USART0_IRTX) - prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR TX Signal. */ -#endif -#if defined(PRS_USART0_RTS) - prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ - prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 TX Signal. */ - prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ -#endif -#endif -#if defined(USART1) - prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 TX complete Signal. */ -#if defined(PRS_USART1_RXDATA) - prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 RX data available Signal. */ -#endif -#if defined(PRS_USART1_RXDATAV) - prsSignalUSART1_RXDATAV = PRS_USART1_RXDATAV, /**< USART1 RX data available Signal. */ -#endif -#if defined(PRS_USART1_IRTX) - prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR TX Signal. */ -#endif -#if defined(PRS_USART1_RTS) - prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ - prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 TX Signal. */ - prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ -#endif -#endif -#if defined(USART2) - prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 TX complete Signal. */ -#if defined(PRS_USART2_RXDATA) - prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 RX data available Signal. */ -#endif -#if defined(PRS_USART2_RXDATAV) - prsSignalUSART2_RXDATAV = PRS_USART2_RXDATAV, /**< USART2 RX data available Signal. */ -#endif -#if defined(PRS_USART2_IRTX) - prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR TX Signal. */ -#endif -#if defined(PRS_USART2_RTS) - prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ - prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 TX Signal. */ - prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ -#endif -#endif -#if defined(PRS_USART3_TXC) - prsSignalUSART3_TXC = PRS_USART3_TXC, /**< USART3 TX complete Signal. */ - prsSignalUSART3_RXDATAV = PRS_USART3_RXDATAV, /**< USART3 RX data available Signal. */ - prsSignalUSART3_RTS = PRS_USART3_RTS, /**< USART3 RTS Signal. */ - prsSignalUSART3_TX = PRS_USART3_TX, /**< USART3 TX Signal. */ - prsSignalUSART3_CS = PRS_USART3_CS, /**< USART3 chip select Signal. */ -#endif -#if defined(PRS_USART4_TXC) - prsSignalUSART4_TXC = PRS_USART4_TXC, /**< USART4 TX complete Signal. */ - prsSignalUSART4_RXDATAV = PRS_USART4_RXDATAV, /**< USART4 RX data available Signal. */ - prsSignalUSART4_RTS = PRS_USART4_RTS, /**< USART4 RTS Signal. */ - prsSignalUSART4_TX = PRS_USART4_TX, /**< USART4 TX Signal. */ - prsSignalUSART4_CS = PRS_USART4_CS, /**< USART4 chip select Signal. */ -#endif -#if defined(PRS_USART5_TXC) - prsSignalUSART5_TXC = PRS_USART5_TXC, /**< USART5 TX complete Signal. */ - prsSignalUSART5_RXDATAV = PRS_USART5_RXDATAV, /**< USART5 RX data available Signal. */ - prsSignalUSART5_RTS = PRS_USART5_RTS, /**< USART5 RTS Signal. */ - prsSignalUSART5_TX = PRS_USART5_TX, /**< USART5 TX Signal. */ - prsSignalUSART5_CS = PRS_USART5_CS, /**< USART5 chip select Signal. */ -#endif - -#if defined(UART0) - prsSignalUART0_TXC = PRS_UART0_TXC, /**< UART0 TX complete Signal. */ - prsSignalUART0_RXDATAV = PRS_UART0_RXDATAV, /**< UART0 RX data available Signal. */ -#if defined(PRS_UART1_IRTX) - prsSignalUART0_IRTX = PRS_UART0_IRTX, /**< UART0 IR TX Signal. */ -#endif -#if defined(PRS_UART0_RTS) - prsSignalUART0_RTS = PRS_UART0_RTS, /**< UART0 RTS Signal. */ - prsSignalUART0_TX = PRS_UART0_TX, /**< UART0 TX Signal. */ - prsSignalUART0_CS = PRS_UART0_CS, /**< UART0 chip select Signal. */ -#endif -#endif - -#if defined(UART1) - prsSignalUART1_TXC = PRS_UART1_TXC, /**< UART1 TX complete Signal. */ - prsSignalUART1_RXDATAV = PRS_UART1_RXDATAV, /**< UART1 RX data available Signal. */ -#if defined(PRS_UART1_IRTX) - prsSignalUART1_IRTX = PRS_UART1_IRTX, /**< UART1 IR RX Signal. */ -#endif -#if defined(PRS_UART1_RTS) - prsSignalUART1_RTS = PRS_UART1_RTS, /**< UART1 RTS Signal. */ - prsSignalUART1_TX = PRS_UART1_TX, /**< UART1 RX Signal. */ - prsSignalUART1_CS = PRS_UART1_CS, /**< UART1 chip select Signal. */ -#endif -#endif - -#if defined(PRS_USB_SOF) - prsSignalUSB_SOF = PRS_USB_SOF, /**< USB_SOF Signal. */ - prsSignalUSB_SOFSR = PRS_USB_SOFSR, /**< USB_SOFSR Signal. */ -#endif - -#if defined(PRS_CM4_TXEV) - prsSignalCM4_TXEV = PRS_CM4_TXEV, /**< TXEV Signal. */ -#endif -#if defined(PRS_CM4_ICACHEPCHITSOF) - prsSignalCM4_ICACHEPCHITSOF = PRS_CM4_ICACHEPCHITSOF, /**< ICACHEPCHITSOF Signal. */ - prsSignalCM4_ICACHEPCMISSESOF = PRS_CM4_ICACHEPCMISSESOF, /**< ICACHEPCMISSESOF Signal. */ -#endif - -#if defined(PRS_WTIMER0_UF) - prsSignalWTIMER0_UF = PRS_WTIMER0_UF, /**< WTIMER0_UF Signal. */ - prsSignalWTIMER0_OF = PRS_WTIMER0_OF, /**< WTIMER0_OF Signal. */ - prsSignalWTIMER0_CC0 = PRS_WTIMER0_CC0, /**< WTIMER0_CC0 Signal. */ - prsSignalWTIMER0_CC1 = PRS_WTIMER0_CC1, /**< WTIMER0_CC1 Signal. */ - prsSignalWTIMER0_CC2 = PRS_WTIMER0_CC2, /**< WTIMER0_CC2 Signal. */ -#endif -#if defined(PRS_WTIMER1_UF) - prsSignalWTIMER1_UF = PRS_WTIMER1_UF, /**< WTIMER1_UF Signal. */ - prsSignalWTIMER1_OF = PRS_WTIMER1_OF, /**< WTIMER1_OF Signal. */ - prsSignalWTIMER1_CC0 = PRS_WTIMER1_CC0, /**< WTIMER1_CC0 Signal. */ - prsSignalWTIMER1_CC1 = PRS_WTIMER1_CC1, /**< WTIMER1_CC1 Signal. */ - prsSignalWTIMER1_CC2 = PRS_WTIMER1_CC2, /**< WTIMER1_CC2 Signal. */ - prsSignalWTIMER1_CC3 = PRS_WTIMER1_CC3, /**< WTIMER1_CC3 Signal. */ -#endif -#if defined(PRS_WTIMER2_UF) - prsSignalWTIMER2_UF = PRS_WTIMER2_UF, /**< WTIMER2_UF Signal. */ - prsSignalWTIMER2_OF = PRS_WTIMER2_OF, /**< WTIMER2_OF Signal. */ - prsSignalWTIMER2_CC0 = PRS_WTIMER2_CC0, /**< WTIMER2_CC0 Signal. */ - prsSignalWTIMER2_CC1 = PRS_WTIMER2_CC1, /**< WTIMER2_CC1 Signal. */ - prsSignalWTIMER2_CC2 = PRS_WTIMER2_CC2, /**< WTIMER2_CC2 Signal. */ -#endif -#if defined(PRS_WTIMER3_UF) - prsSignalWTIMER3_UF = PRS_WTIMER3_UF, /**< WTIMER3_UF Signal. */ - prsSignalWTIMER3_OF = PRS_WTIMER3_OF, /**< WTIMER3_OF Signal. */ - prsSignalWTIMER3_CC0 = PRS_WTIMER3_CC0, /**< WTIMER3_CC0 Signal. */ - prsSignalWTIMER3_CC1 = PRS_WTIMER3_CC1, /**< WTIMER3_CC1 Signal. */ - prsSignalWTIMER3_CC2 = PRS_WTIMER3_CC2, /**< WTIMER3_CC2 Signal. */ -#endif - -/* EUSART Signals */ -#if defined(EUSART0) - prsSignalEUSART0_CS = PRS_EUSART0L_CS, /**< EUSART0 chip select Signal. */ - prsSignalEUSART0_IRTX = PRS_EUSART0L_IRDATX, /**< EUSART0 IR RX Signal. */ - prsSignalEUSART0_RTS = PRS_EUSART0L_RTS, /**< EUSART0 RTS Signal. */ - prsSignalEUSART0_RXDATA = PRS_EUSART0L_RXDATAV, /**< EUSART0 RX data available Signal. */ - prsSignalEUSART0_TX = PRS_EUSART0L_TX, /**< EUSART0 TX Signal. */ - prsSignalEUSART0_TXC = PRS_EUSART0L_TXC, /**< EUSART0 TX complete Signal. */ - prsSignalEUSART0_RXFL = PRS_EUSART0L_RXFL, /**< EUSART0 rxfl Signal. */ - prsSignalEUSART0_TXFL = PRS_EUSART0L_TXFL, /**< EUSART0 txfl Signal. */ -#endif -#if defined(EUSART1) - prsSignalEUSART1_CS = PRS_EUSART1L_CS, /**< EUSART1 chip select Signal. */ - prsSignalEUSART1_IRTX = PRS_EUSART1L_IRDATX, /**< EUSART1 IR TX Signal. */ - prsSignalEUSART1_RTS = PRS_EUSART1L_RTS, /**< EUSART1 RTS Signal. */ - prsSignalEUSART1_RXDATA = PRS_EUSART1L_RXDATAV, /**< EUSART1 RX data available Signal. */ - prsSignalEUSART1_TX = PRS_EUSART1L_TX, /**< EUSART1 TX Signal. */ - prsSignalEUSART1_TXC = PRS_EUSART1L_TXC, /**< EUSART1 TX complete Signal. */ - prsSignalEUSART1_RXFL = PRS_EUSART1L_RXFL, /**< EUSART1 rxfl Signal. */ - prsSignalEUSART1_TXFL = PRS_EUSART1L_TXFL, /**< EUSART1 txfl Signal. */ -#endif -#if defined(EUSART2) -#if defined(PRS_EUSART2L_CS) - prsSignalEUSART2_CS = PRS_EUSART2L_CS, /**< EUSART2 chip select Signal. */ - prsSignalEUSART2_IRTX = PRS_EUSART2L_IRDATX, /**< EUSART2 IR TX Signal. */ - prsSignalEUSART2_RTS = PRS_EUSART2L_RTS, /**< EUSART2 RTS Signal. */ - prsSignalEUSART2_RXDATA = PRS_EUSART2L_RXDATAV, /**< EUSART2 RX data available Signal. */ - prsSignalEUSART2_TX = PRS_EUSART2L_TX, /**< EUSART2 TX Signal. */ - prsSignalEUSART2_TXC = PRS_EUSART2L_TXC, /**< EUSART2 TX complete Signal. */ - prsSignalEUSART2_RXFL = PRS_EUSART2L_RXFL, /**< EUSART2 rxfl Signal. */ - prsSignalEUSART2_TXFL = PRS_EUSART2L_TXFL, /**< EUSART2 txfl Signal. */ -#else - prsSignalEUSART2_CS = PRS_EUSART2_CS, /**< EUSART2 chip select Signal. */ - prsSignalEUSART2_IRTX = PRS_EUSART2_IRDATX, /**< EUSART2 IR TX Signal. */ - prsSignalEUSART2_RTS = PRS_EUSART2_RTS, /**< EUSART2 RTS Signal. */ - prsSignalEUSART2_RXDATA = PRS_EUSART2_RXDATAV, /**< EUSART2 RX data available Signal. */ - prsSignalEUSART2_TX = PRS_EUSART2_TX, /**< EUSART2 TX Signal. */ - prsSignalEUSART2_TXC = PRS_EUSART2_TXC, /**< EUSART2 TX complete Signal. */ - prsSignalEUSART2_RXFL = PRS_EUSART2_RXFL, /**< EUSART2 rxfl Signal. */ - prsSignalEUSART2_TXFL = PRS_EUSART2_TXFL, /**< EUSART2 txfl Signal. */ -#endif -#endif -#if defined(EUSART3) -#if defined(PRS_EUSART3L_CS) - prsSignalEUSART3_CS = PRS_EUSART3L_CS, /**< EUSART3 chip select Signal. */ - prsSignalEUSART3_IRTX = PRS_EUSART3L_IRDATX, /**< EUSART3 IR TX Signal. */ - prsSignalEUSART3_RTS = PRS_EUSART3L_RTS, /**< EUSART3 RTS Signal. */ - prsSignalEUSART3_RXDATA = PRS_EUSART3L_RXDATAV, /**< EUSART3 RX data available Signal. */ - prsSignalEUSART3_TX = PRS_EUSART3L_TX, /**< EUSART3 TX Signal. */ - prsSignalEUSART3_TXC = PRS_EUSART3L_TXC, /**< EUSART3 TX complete Signal. */ - prsSignalEUSART3_RXFL = PRS_EUSART3L_RXFL, /**< EUSART3 rxfl Signal. */ - prsSignalEUSART3_TXFL = PRS_EUSART3L_TXFL, /**< EUSART3 txfl Signal. */ -#else - prsSignalEUSART3_CS = PRS_EUSART3_CS, /**< EUSART3 chip select Signal. */ - prsSignalEUSART3_IRTX = PRS_EUSART3_IRDATX, /**< EUSART3 IR TX Signal. */ - prsSignalEUSART3_RTS = PRS_EUSART3_RTS, /**< EUSART3 RTS Signal. */ - prsSignalEUSART3_RXDATA = PRS_EUSART3_RXDATAV, /**< EUSART3 RX data available Signal. */ - prsSignalEUSART3_TX = PRS_EUSART3_TX, /**< EUSART3 TX Signal. */ - prsSignalEUSART3_TXC = PRS_EUSART3_TXC, /**< EUSART3 TX complete Signal. */ - prsSignalEUSART3_RXFL = PRS_EUSART3_RXFL, /**< EUSART3 rxfl Signal. */ - prsSignalEUSART3_TXFL = PRS_EUSART3_TXFL, /**< EUSART3 txfl Signal. */ -#endif -#endif -#if defined(EUSART4) - prsSignalEUSART4_CS = PRS_EUSART4L_CS, /**< EUSART4 chip select Signal. */ - prsSignalEUSART4_IRTX = PRS_EUSART4L_IRDATX, /**< EUSART4 IR TX Signal. */ - prsSignalEUSART4_RTS = PRS_EUSART4L_RTS, /**< EUSART4 RTS Signal. */ - prsSignalEUSART4_RXDATA = PRS_EUSART4L_RXDATAV, /**< EUSART4 RX data available Signal. */ - prsSignalEUSART4_TX = PRS_EUSART4L_TX, /**< EUSART4 TX Signal. */ - prsSignalEUSART4_TXC = PRS_EUSART4L_TXC, /**< EUSART4 TX complete Signal. */ - prsSignalEUSART4_RXFL = PRS_EUSART4L_RXFL, /**< EUSART4 rxfl Signal. */ - prsSignalEUSART4_TXFL = PRS_EUSART4L_TXFL, /**< EUSART4 txfl Signal. */ -#endif - /* ADC Signals */ -#if defined(IADC0) - prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ - prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ - prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ -#endif - - /* GPIO pin Signals */ - prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ - prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ - prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ - prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ - prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ - prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ - prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ - prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ -#if defined(PRS_GPIO_PIN15) - prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ - prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ - prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ - prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ - prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ - prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ - prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ - prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ -#endif -#if defined(PRS_AGCL_CCA) - prsSignalAGCL_CCA = PRS_AGCL_CCA, /**< AGCL_CCA Signal. */ - prsSignalAGCL_CCAREQ = PRS_AGCL_CCAREQ, /**< AGCL_CCAREQ Signal. */ - prsSignalAGCL_GAINADJUST = PRS_AGCL_GAINADJUST, /**< AGCL_GAINADJUST Signal. */ - prsSignalAGCL_GAINOK = PRS_AGCL_GAINOK, /**< AGCL_GAINOK Signal. */ - prsSignalAGCL_GAINREDUCED = PRS_AGCL_GAINREDUCED, /**< AGCL_GAINREDUCED Signal. */ - prsSignalAGCL_IFPKI1 = PRS_AGCL_IFPKI1, /**< AGCL_IFPKI1 Signal. */ - prsSignalAGCL_IFPKQ2 = PRS_AGCL_IFPKQ2, /**< AGCL_IFPKQ2 Signal. */ - prsSignalAGCL_IFPKRST = PRS_AGCL_IFPKRST, /**< AGCL_IFPKRST Signal. */ -#endif -#if defined(PRS_AGC_PEAKDET) - prsSignalAGC_PEAKDET = PRS_AGC_PEAKDET, /**< AGC_PEAKDET Signal. */ - prsSignalAGC_PROPAGATED = PRS_AGC_PROPAGATED, /**< AGC_PROPAGATED Signal. */ - prsSignalAGC_RSSIDONE = PRS_AGC_RSSIDONE, /**< AGC_RSSIDONE Signal. */ -#endif -#if defined(PRS_BUFC_THR0) - prsSignalBUFC_THR0 = PRS_BUFC_THR0, /**< BUFC_THR0 Signal. */ - prsSignalBUFC_THR1 = PRS_BUFC_THR1, /**< BUFC_THR1 Signal. */ - prsSignalBUFC_THR2 = PRS_BUFC_THR2, /**< BUFC_THR2 Signal. */ - prsSignalBUFC_THR3 = PRS_BUFC_THR3, /**< BUFC_THR3 Signal. */ -#endif -#if defined(PRS_BUFC_CNT0) - prsSignalBUFC_CNT0 = PRS_BUFC_CNT0, /**< BUFC_CNT0 Signal. */ - prsSignalBUFC_CNT1 = PRS_BUFC_CNT1, /**< BUFC_CNT1 Signal. */ - prsSignalBUFC_FULL = PRS_BUFC_FULL, /**< BUFC_FULL Signal. */ -#endif -#if defined(PRS_MODEML_ADVANCE) - prsSignalMODEML_ADVANCE = PRS_MODEML_ADVANCE, /**< MODEML_ADVANCE Signal. */ - prsSignalMODEML_ANT0 = PRS_MODEML_ANT0, /**< MODEML_ANT0 Signal. */ - prsSignalMODEML_ANT1 = PRS_MODEML_ANT1, /**< MODEML_ANT1 Signal. */ - prsSignalMODEML_COHDSADET = PRS_MODEML_COHDSADET, /**< MODEML_COHDSADET Signal. */ - prsSignalMODEML_COHDSALIVE = PRS_MODEML_COHDSALIVE, /**< MODEML_COHDSALIVE Signal. */ - prsSignalMODEML_DCLK = PRS_MODEML_DCLK, /**< MODEML_DCLK Signal. */ - prsSignalMODEML_DOUT = PRS_MODEML_DOUT, /**< MODEML_DOUT Signal. */ - prsSignalMODEML_FRAMEDET = PRS_MODEML_FRAMEDET, /**< MODEML_FRAMEDET Signal. */ -#endif -#if defined(PRS_MODEM_FRAMEDET) - prsSignalMODEM_FRAMEDET = PRS_MODEM_FRAMEDET, /**< MODEM_FRAMEDET Signal. */ - prsSignalMODEM_TIMDET = PRS_MODEM_TIMDET, /**< MODEM_TIMDET Signal. */ - prsSignalMODEM_SYNCSENT = PRS_MODEM_SYNCSENT, /**< MODEM_SYNCSENT Signal. */ - prsSignalMODEM_PRESENT = PRS_MODEM_PRESENT, /**< MODEM_PRESENT Signal. */ - prsSignalMODEM_ANT0 = PRS_MODEM_ANT0, /**< MODEM_ANT0 Signal. */ - prsSignalMODEM_ANT1 = PRS_MODEM_ANT1, /**< MODEM_ANT1 Signal. */ -#endif -#if defined(PRS_MODEM_FRAMESENT) - prsSignalMODEM_FRAMESENT = PRS_MODEM_FRAMESENT, /**< MODEM_FRAMESENT Signal. */ -#endif -#if defined(PRS_MODEM_PREDET) - prsSignalMODEM_PREDET = PRS_MODEM_PREDET, /**< MODEM_PREDET Signal. */ -#endif -#if defined(PRS_MODEM_LRDSADET) - prsSignalMODEM_LRDSADET = PRS_MODEM_LRDSADET, /**< MODEM_LRDSADET Signal. */ - prsSignalMODEM_LRDSALIVE = PRS_MODEM_LRDSALIVE, /**< MODEM_LRDSALIVE Signal. */ -#endif -#if defined(PRS_MODEM_LOWCORR) - prsSignalMODEM_LOWCORR = PRS_MODEM_LOWCORR, /**< MODEM_LOWCORR Signal. */ - prsSignalMODEM_NEWSYMBOL = PRS_MODEM_NEWSYMBOL, /**< MODEM_NEWSYMBOL Signal. */ - prsSignalMODEM_NEWWND = PRS_MODEM_NEWWND, /**< MODEM_NEWWND Signal. */ - prsSignalMODEM_POSTPONE = PRS_MODEM_POSTPONE, /**< MODEM_POSTPONE Signal. */ -#endif -#if defined(PRS_MODEMH_PRESENT) - prsSignalMODEMH_PRESENT = PRS_MODEMH_PRESENT, /**< MODEMH_PRESENT Signal. */ - prsSignalMODEMH_RSSIJUMP = PRS_MODEMH_RSSIJUMP, /**< MODEMH_RSSIJUMP Signal. */ - prsSignalMODEMH_SYNCSENT = PRS_MODEMH_SYNCSENT, /**< MODEMH_SYNCSENT Signal. */ - prsSignalMODEMH_TIMDET = PRS_MODEMH_TIMDET, /**< MODEMH_TIMDET Signal. */ - prsSignalMODEMH_WEAK = PRS_MODEMH_WEAK, /**< MODEMH_WEAK Signal. */ - prsSignalMODEMH_EOF = PRS_MODEMH_EOF, /**< MODEMH_EOF Signal. */ -#endif -#if defined(PRS_MODEMH_SI) - prsSignalMODEMH_SI = PRS_MODEMH_SI, /**< MODEMH_SI Signal. */ -#endif -#if defined(PRS_FRC_DCLK) - prsSignalFRC_DCLK = PRS_FRC_DCLK, /**< FRC_DCLK Signal. */ - prsSignalFRC_DOUT = PRS_FRC_DOUT, /**< FRC_DOUT Signal. */ -#endif -#if defined(PRS_PROTIMERL_BOF) - prsSignalPROTIMERL_BOF = PRS_PROTIMERL_BOF, /**< PROTIMERL_BOF Signal. */ - prsSignalPROTIMERL_CC0 = PRS_PROTIMERL_CC0, /**< PROTIMERL_CC0 Signal. */ - prsSignalPROTIMERL_CC1 = PRS_PROTIMERL_CC1, /**< PROTIMERL_CC1 Signal. */ - prsSignalPROTIMERL_CC2 = PRS_PROTIMERL_CC2, /**< PROTIMERL_CC2 Signal. */ - prsSignalPROTIMERL_CC3 = PRS_PROTIMERL_CC3, /**< PROTIMERL_CC3 Signal. */ - prsSignalPROTIMERL_CC4 = PRS_PROTIMERL_CC4, /**< PROTIMERL_CC4 Signal. */ - prsSignalPROTIMERL_LBTF = PRS_PROTIMERL_LBTF, /**< PROTIMERL_LBTF Signal. */ - prsSignalPROTIMERL_LBTR = PRS_PROTIMERL_LBTR, /**< PROTIMERL_LBTR Signal. */ -#endif -#if defined(PRS_PROTIMER_LBTR) - prsSignalPROTIMER_LBTR = PRS_PROTIMER_LBTR, /**< PROTIMER_LBTR Signal. */ - prsSignalPROTIMER_LBTF = PRS_PROTIMER_LBTF, /**< PROTIMER_LBTF Signal. */ -#endif -#if defined(PRS_PROTIMER_LBTS) - prsSignalPROTIMER_LBTS = PRS_PROTIMER_LBTS, /**< PROTIMER_LBTS Signal. */ -#endif -#if defined(PRS_PROTIMER_POF) - prsSignalPROTIMER_POF = PRS_PROTIMER_POF, /**< PROTIMER_POF Signal. */ - prsSignalPROTIMER_T0MATCH = PRS_PROTIMER_T0MATCH, /**< PROTIMER_T0MATCH Signal. */ - prsSignalPROTIMER_T0UF = PRS_PROTIMER_T0UF, /**< PROTIMER_T0UF Signal. */ - prsSignalPROTIMER_T1MATCH = PRS_PROTIMER_T1MATCH, /**< PROTIMER_T1MATCH Signal. */ - prsSignalPROTIMER_T1UF = PRS_PROTIMER_T1UF, /**< PROTIMER_T1UF Signal. */ - prsSignalPROTIMER_WOF = PRS_PROTIMER_WOF, /**< PROTIMER_WOF Signal. */ -#endif -#if defined(PRS_RAC_ACTIVE) - prsSignalRAC_ACTIVE = PRS_RAC_ACTIVE, /**< RAC_ACTIVE Signal. */ - prsSignalRAC_LNAEN = PRS_RAC_LNAEN, /**< RAC_LNAEN Signal. */ - prsSignalRAC_PAEN = PRS_RAC_PAEN, /**< RAC_PAEN Signal. */ - prsSignalRAC_RX = PRS_RAC_RX, /**< RAC_RX Signal. */ - prsSignalRAC_TX = PRS_RAC_TX, /**< RAC_TX Signal. */ -#endif -#if defined(PRS_RACL_ACTIVE) - prsSignalRACL_ACTIVE = PRS_RACL_ACTIVE, /**< RACL_ACTIVE Signal. */ - prsSignalRACL_LNAEN = PRS_RACL_LNAEN, /**< RACL_LNAEN Signal. */ - prsSignalRACL_PAEN = PRS_RACL_PAEN, /**< RACL_PAEN Signal. */ - prsSignalRACL_RX = PRS_RACL_RX, /**< RACL_RX Signal. */ - prsSignalRACL_TX = PRS_RACL_TX, /**< RACL_TX Signal. */ - prsSignalRACL_CTIOUT0 = PRS_RACL_CTIOUT0, /**< RACL_CTIOUT0 Signal. */ - prsSignalRACL_CTIOUT1 = PRS_RACL_CTIOUT1, /**< RACL_CTIOUT1 Signal. */ - prsSignalRACL_CTIOUT2 = PRS_RACL_CTIOUT2, /**< RACL_CTIOUT2 Signal. */ -#endif -#if defined(PRS_RAC_CTIOUT3) - prsSignalRAC_CTIOUT3 = PRS_RAC_CTIOUT3, /**< RAC_CTIOUT3 Signal. */ -#endif -#if defined(PRS_RAC_AUXADCDATA) - prsSignalRAC_AUXADCDATA = PRS_RAC_AUXADCDATA, /**< RAC_AUXADCDATA Signal. */ - prsSignalRAC_AUXADCDATAVALID = PRS_RAC_AUXADCDATAVALID, /**< RAC_AUXADCDATAVALID Signal. */ -#endif -#if defined(PRS_SYNTH_MUX0) - prsSignalSYNTH_MUX0 = PRS_SYNTH_MUX0, /**< SYNTH_MUX0 Signal. */ - prsSignalSYNTH_MUX1 = PRS_SYNTH_MUX1, /**< SYNTH_MUX1 Signal. */ -#endif -#if defined(PRS_PRORTC_CCV0) - prsSignalPRORTC_CCV0 = PRS_PRORTC_CCV0, /**< PRORTC_CCV0 Signal. */ - prsSignalPRORTC_CCV1 = PRS_PRORTC_CCV1, /**< PRORTC_CCV1 Signal. */ -#endif -#if defined(RFFPLL0) - prsSignalRFFPLL0L_CLKDIGDIV4 = PRS_RFFPLL0L_CLKDIGDIV4, /**< RFFPLL0L CLKDIGDIV4 Signal. */ - prsSignalRFFPLL0L_CLKMODEMDIV4 = PRS_RFFPLL0L_CLKMODEMDIV4, /**< RFFPLL0L CLKMODEMDIV4 Signal. */ -#if defined(PRS_RFFPLL0L_RFBIASFSMSTATE0) - prsSignalRFFPLL0L_RFBIASFSMSTATE0 = PRS_RFFPLL0L_RFBIASFSMSTATE0, /**< RFFPLL0L RFBIASFSMSTATE0 Signal. */ - prsSignalRFFPLL0L_RFBIASFSMSTATE1 = PRS_RFFPLL0L_RFBIASFSMSTATE1, /**< RFFPLL0L RFBIASFSMSTATE1 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE0 = PRS_RFFPLL0L_RFFPLLFSMSTATE0, /**< RFFPLL0L RFFPLLFSMSTATE0 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE1 = PRS_RFFPLL0L_RFFPLLFSMSTATE1, /**< RFFPLL0L RFFPLLFSMSTATE1 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE2 = PRS_RFFPLL0L_RFFPLLFSMSTATE2, /**< RFFPLL0L RFFPLLFSMSTATE2 Signal. */ - prsSignalRFFPLL0L_RFBIASFSMSTATE2 = PRS_RFFPLL0L_RFBIASFSMSTATE2, /**< RFFPLL0L RFBIASFSMSTATE2 Signal. */ - prsSignalRFFPLL0_RFFPLLFSMSTATE3 = PRS_RFFPLL0_RFFPLLFSMSTATE3, /**< RFFPLL0 RFFPLLFSMSTATE3 Signal. */ -#endif -#endif -#if defined(FEFILT0) - prsSignalFEFILT0_REMPTY = PRS_FEFILT0_REMPTY, /**< FEFILT0 REMPTY Signal. */ - prsSignalFEFILT0_WFULL = PRS_FEFILT0_WFULL, /**< FEFILT0 WFULL Signal. */ -#endif -#if defined(FEFILT0) - prsSignalFEFILT1_REMPTY = PRS_FEFILT1_REMPTY, /**< FEFILT1 REMPTY Signal. */ - prsSignalFEFILT1_WFULL = PRS_FEFILT1_WFULL, /**< FEFILT1 WFULL Signal. */ -#endif -#if defined(ETAMPDET) - prsSignalETAMPDET_TAMPERSRCETAMPDET = PRS_ETAMPDET_TAMPERSRCETAMPDET, /**< ETAMPDET TAMPERSRCETAMPDET Signal. */ -#endif -#if defined(SMCTRL) - prsSignalSMCTRLL_SOFTM0 = PRS_SMCTRLL_SOFTM0, /**< SMCTRLL SOFTM0 Signal. */ - prsSignalSMCTRLL_SOFTM1 = PRS_SMCTRLL_SOFTM1, /**< SMCTRLL SOFTM1 Signal. */ - prsSignalSMCTRLL_SOFTM2 = PRS_SMCTRLL_SOFTM2, /**< SMCTRLL SOFTM2 Signal. */ - prsSignalSMCTRLL_SOFTM3 = PRS_SMCTRLL_SOFTM3, /**< SMCTRLL SOFTM3 Signal. */ - prsSignalSMCTRLL_SOFTM4 = PRS_SMCTRLL_SOFTM4, /**< SMCTRLL SOFTM4 Signal. */ - prsSignalSMCTRLL_SOFTM5 = PRS_SMCTRLL_SOFTM5, /**< SMCTRLL SOFTM5 Signal. */ - prsSignalSMCTRLL_SOFTM6 = PRS_SMCTRLL_SOFTM6, /**< SMCTRLL SOFTM6 Signal. */ - prsSignalSMCTRLL_SOFTM7 = PRS_SMCTRLL_SOFTM7, /**< SMCTRLL SOFTM7 Signal. */ - prsSignalSMCTRL_SOFTM8 = PRS_SMCTRL_SOFTM8, /**< SMCTRL SOFTM8 Signal. */ - prsSignalSMCTRL_SOFTM9 = PRS_SMCTRL_SOFTM9, /**< SMCTRL SOFTM9 Signal. */ - prsSignalSMCTRL_SOFTM10 = PRS_SMCTRL_SOFTM10, /**< SMCTRL SOFTM10 Signal. */ - prsSignalSMCTRL_SOFTM11 = PRS_SMCTRL_SOFTM11, /**< SMCTRL SOFTM11 Signal. */ -#endif -#if defined(PRS_SEHFRCO_COREEN) - prsSignalSEHFRCO_COREEN = PRS_SEHFRCO_COREEN, /**< SEHFRCO COREEN Signal. */ - prsSignalSEHFRCO_STATE0 = PRS_SEHFRCO_STATE0, /**< SEHFRCO STATE0 Signal. */ - prsSignalSEHFRCO_STATE1 = PRS_SEHFRCO_STATE1, /**< SEHFRCO STATE1 Signal. */ - prsSignalSEHFRCO_STATE2 = PRS_SEHFRCO_STATE2, /**< SEHFRCO STATE2 Signal. */ -#endif -#if defined(PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY) - prsSignalSEATAMPDET_SEATAMPDETSUPTPDELAY = PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY, /**< SEATAMPDET SEATAMPDETSUPTPDELAY Signal. */ -#endif -#if defined(PRS_DCDC_MONO70NSANA) - prsSignalDCDC_MONO70NSANA = PRS_DCDC_MONO70NSANA, /** DCDC Pulses for Coulomb Counter Calibration Signal. */ -#endif -#if defined(PRS_LFRCO_CALMEAS) - prsSignalLFRCO_CALMEAS = PRS_LFRCO_CALMEAS, /** LFRCO Calibration Measure Signal. */ - prsSignalLFRCO_SDM = PRS_LFRCO_SDM, /** LFRCO Sigma Delta Modulator output Signal. */ - prsSignalLFRCO_TCMEAS = PRS_LFRCO_TCMEAS, /** LFRCO Temperature Check Measure Signal. */ -#endif -} PRS_Signal_t; - -#if defined(_SILICON_LABS_32B_SERIES_2) -/** PRS Consumers. */ -typedef enum { - prsConsumerNone = 0x000, /**< No PRS consumer */ - prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ - prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ -#if defined(IADC_PRESENT) - prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ - prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ -#endif - prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ - prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ -#if defined(LETIMER0) - prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_CLEAR), /**< LETIMER0 clear consumer. */ - prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_START), /**< LETIMER0 start consumer. */ - prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_STOP), /**< LETIMER0 stop consumer. */ -#endif - prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ - prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ - prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ - prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ - prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ - prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ - prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ - prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ - prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ - prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ - prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ - prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ -#if defined(TIMER4) - prsConsumerTIMER4_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC0), /**< TIMER4 capture/compare channel 0 consumer. */ - prsConsumerTIMER4_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC1), /**< TIMER4 capture/compare channel 1 consumer. */ - prsConsumerTIMER4_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC2), /**< TIMER4 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER5) - prsConsumerTIMER5_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC0), /**< TIMER5 capture/compare channel 0 consumer. */ - prsConsumerTIMER5_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC1), /**< TIMER5 capture/compare channel 1 consumer. */ - prsConsumerTIMER5_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC2), /**< TIMER5 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER6) - prsConsumerTIMER6_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC0), /**< TIMER6 capture/compare channel 0 consumer. */ - prsConsumerTIMER6_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC1), /**< TIMER6 capture/compare channel 1 consumer. */ - prsConsumerTIMER6_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC2), /**< TIMER6 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER7) - prsConsumerTIMER7_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC0), /**< TIMER7 capture/compare channel 0 consumer. */ - prsConsumerTIMER7_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC1), /**< TIMER7 capture/compare channel 1 consumer. */ - prsConsumerTIMER7_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC2), /**< TIMER7 capture/compare channel 2 consumer. */ -#endif -#if defined(USART0) - prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ - prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ - prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 RX consumer. */ - prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ -#endif -#if defined(USART1) - prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ - prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ - prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 TX consumer. */ - prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ -#endif -#if defined(USART2) - prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ - prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ - prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 RX consumer. */ - prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ -#endif -#if defined(EUSART0) - prsConsumerEUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART0_CLK), /**< EUSART0 clk consumer. */ - prsConsumerEUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART0_RX), /**< EUSART0 RX consumer. */ - prsConsumerEUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART0_TRIGGER), /**< EUSART0 trigger consumer. */ -#endif -#if defined(EUSART1) - prsConsumerEUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART1_CLK), /**< EUSART1 clk consumer. */ - prsConsumerEUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART1_RX), /**< EUSART1 RX consumer. */ - prsConsumerEUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART1_TRIGGER), /**< EUSART1 trigger consumer. */ -#endif -#if defined(EUSART2) - prsConsumerEUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART2_CLK), /**< EUSART1 clk consumer. */ - prsConsumerEUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART2_RX), /**< EUSART2 RX consumer. */ - prsConsumerEUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART2_TRIGGER), /**< EUSART2 trigger consumer. */ -#endif -#if defined(EUSART3) - prsConsumerEUSART3_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART3_RX), /**< EUSART3 RX consumer. */ - prsConsumerEUSART3_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART3_TRIGGER), /**< EUSART3 trigger consumer. */ -#endif -#if defined(EUSART4) - prsConsumerEUSART4_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART4_RX), /**< EUSART4 RX consumer. */ - prsConsumerEUSART4_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART4_TRIGGER), /**< EUSART4 trigger consumer. */ -#endif -#if defined(EUART0) - prsConsumerEUART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUART0_RX), /**< EUART0 RX consumer. */ - prsConsumerEUART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUART0_TRIGGER), /**< EUART0 TRIGGER Consumer. */ -#endif - prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ - prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ -#if defined(WDOG1) - prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ - prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ -#endif -#if defined(PCNT0) - prsConsumerPCNT0_IN0 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S0IN), /**< PCNT0 input 0 consumer. */ - prsConsumerPCNT0_IN1 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S1IN), /**< PCNT0 input 1 consumer. */ -#endif -#if defined(_PRS_CONSUMER_RTCC_CC2_MASK) - prsConsumerRTCC_CC0 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC0), /**< RTCC capture/compare channel 0 consumer. */ - prsConsumerRTCC_CC1 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC1), /**< RTCC capture/compare channel 1 consumer. */ - prsConsumerRTCC_CC2 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC2), /**< RTCC capture/compare channel 2 consumer. */ -#endif -#if defined(SYSRTC0) - prsConsumerSYSRTC0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN0), /**< SYSRTC0 input 0 consumer. */ - prsConsumerSYSRTC0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN1), /**< SYSRTC0 input 1 consumer. */ -#endif -#if defined(_PRS_CONSUMER_HFXO0_OSCREQ_MASK) - prsConsumerHFXO0_OSCREQ = offsetof(PRS_TypeDef, CONSUMER_HFXO0_OSCREQ), /**< OSCREQ consumer. */ - prsConsumerHFXO0_TIMEOUT = offsetof(PRS_TypeDef, CONSUMER_HFXO0_TIMEOUT), /**< HFXO0_TIMEOUT consumer. */ -#endif -#if defined(LESENSE) - prsConsumerLESENSE_START = offsetof(PRS_TypeDef, CONSUMER_LESENSE_START), /**< LESENSE_START consumer. */ -#endif -#if defined(VDAC0) - prsConsumerVDAC0_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH0), /**< VDAC0 ASYNC TRIGER CH0 consumer. */ - prsConsumerVDAC0_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH1), /**< VDAC0 ASYNC TRIGER CH1 consumer. */ - prsConsumerVDAC0_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH0), /**< VDAC0 SYNC TRIGER CH0 consumer. */ - prsConsumerVDAC0_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH1), /**< VDAC0 SYNC TRIGER CH1 consumer. */ -#endif -#if defined(VDAC1) - prsConsumerVDAC1_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH0), /**< VDAC1 ASYNC TRIGER CH0 consumer. */ - prsConsumerVDAC1_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH1), /**< VDAC1 ASYNC TRIGER CH1 consumer. */ - prsConsumerVDAC1_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH0), /**< VDAC1 SYNC TRIGER CH0 consumer. */ - prsConsumerVDAC1_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH1), /**< VDAC1 SYNC TRIGER CH1 consumer. */ -#endif -} PRS_Consumer_t; -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Set level control bit for one or more channels. - * - * @details - * The level value for a channel is XORed with both the pulse possibly issued - * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). - * - * @cond DOXYDOC_S2_DEVICE - * @note - * Note that software level control is only available for asynchronous - * channels on Series 2 devices. - * @endcond - * - * @param[in] level - * Level to use for channels indicated by @p mask. Use logical OR combination - * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. - * - * @param[in] mask - * Mask indicating which channels to set level for. Use logical OR combination - * of PRS_SWLEVEL_CHnLEVEL defines. - ******************************************************************************/ -__STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) -{ -#if defined(_PRS_SWLEVEL_MASK) - PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); -#else - PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); -#endif -} - -/***************************************************************************//** - * @brief - * Get level control bit for all channels. - * - * @return - * The current software level configuration. - ******************************************************************************/ -__STATIC_INLINE uint32_t PRS_LevelGet(void) -{ -#if defined(_PRS_SWLEVEL_MASK) - return PRS->SWLEVEL; -#else - return PRS->ASYNC_SWLEVEL; -#endif -} - -#if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) -/***************************************************************************//** - * @brief - * Get the PRS channel values for all channels. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * The current PRS channel output values for all channels as a bitset. - ******************************************************************************/ -__STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) -{ -#if defined(_PRS_ASYNC_PEEK_MASK) - if (type == prsTypeAsync) { - return PRS->ASYNC_PEEK; - } else { - return PRS->SYNC_PEEK; - } -#else - (void) type; - return PRS->PEEK; -#endif -} - -/***************************************************************************//** - * @brief - * Get the PRS channel value for a single channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * The current PRS channel output value. This is either 0 or 1. - ******************************************************************************/ -__STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) -{ - return (0UL != ((PRS_Values(type) >> ch) & 0x1U)); -} -#endif - -/***************************************************************************//** - * @brief - * Trigger a high pulse (one HFPERCLK) for one or more channels. - * - * @details - * Setting a bit for a channel causes the bit in the register to remain high - * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit - * in PRS SWLEVEL register and the PRS input signal selected for the - * channel(s). - * - * @param[in] channels - * Logical ORed combination of channels to trigger a pulse for. Use - * PRS_SWPULSE_CHnPULSE defines. - ******************************************************************************/ -__STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) -{ -#if defined(_PRS_SWPULSE_MASK) - PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; -#else - PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; -#endif -} - -/***************************************************************************//** - * @brief - * Set the PRS channel level for one asynchronous PRS channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] level - * true to set the level high (1) and false to set the level low (0). - ******************************************************************************/ -__STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) -{ - PRS_LevelSet((uint32_t) level << ch, 0x1UL << ch); -} - -/***************************************************************************//** - * @brief - * Trigger a pulse on one PRS channel. - * - * @param[in] ch - * PRS channel number. - ******************************************************************************/ -__STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) -{ - PRS_PulseTrigger(0x1UL << ch); -} - -void PRS_SourceSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal, - PRS_Edge_TypeDef edge); - -#if defined(PRS_ASYNC_SUPPORTED) -void PRS_SourceAsyncSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal); -#endif -#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) -void PRS_GpioOutputLocation(unsigned int ch, - unsigned int location); -#endif - -int PRS_GetFreeChannel(PRS_ChType_t type); -void PRS_Reset(void); -void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); -#if defined(_SILICON_LABS_32B_SERIES_2) -uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource); -uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal); -void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); -void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); -void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); -#endif - -/** @} (end addtogroup prs) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ -#endif /* EM_PRS_H */ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_PRS_H +#define EM_PRS_H + +#include "em_device.h" +#include "em_gpio.h" + +#include +#include + +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup prs + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM +#elif defined(_EFM32_GECKO_FAMILY) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT 0 +#else +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT +#endif + +#if !defined(_EFM32_GECKO_FAMILY) +/** PRS asynchronous support */ +#define PRS_ASYNC_SUPPORTED 1 +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Some devices have renamed signals so some of these signals are mapped to + common names. */ +#if defined(PRS_USART0_RXDATAV) +#define PRS_USART0_RXDATA PRS_USART0_RXDATAV +#endif +#if defined(PRS_USART1_RXDATAV) +#define PRS_USART1_RXDATA PRS_USART1_RXDATAV +#endif +#if defined(PRS_USART2_RXDATAV) +#define PRS_USART2_RXDATA PRS_USART2_RXDATAV +#endif +#if defined(PRS_BURTC_OVERFLOW) +#define PRS_BURTC_OF PRS_BURTC_OVERFLOW +#endif +#if defined(PRS_BURTC_COMP0) +#define PRS_BURTC_COMP PRS_BURTC_COMP0 +#endif +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** PRS Channel type. */ +typedef enum { + prsTypeAsync, /**< Asynchronous channel type. */ + prsTypeSync /**< Synchronous channel type.*/ +} PRS_ChType_t; + +/** Edge detection type. */ +typedef enum { + prsEdgeOff, /**< Leave signal as is. */ + prsEdgePos, /**< Generate pulses on positive edge. */ + prsEdgeNeg, /**< Generate pulses on negative edge. */ + prsEdgeBoth /**< Generate pulses on both edges. */ +} PRS_Edge_TypeDef; + +#if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) +/** Logic functions that can be used when combining two PRS channels. */ +typedef enum { + prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, /**< Logical 0. */ + prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, /**< A NOR B. */ + prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, /**< (!A) NOR B. */ + prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, /**< !A. */ + prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, /**< A AND (!B). */ + prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, /**< !B. */ + prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, /**< A XOR B. */ + prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, /**< A NAND B. */ + prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, /**< A AND B. */ + prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, /**< A XNOR B. */ + prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, /**< B. */ + prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, /**< (!A) OR B. */ + prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, /**< A. */ + prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, /**< A OR (!B). */ + prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, /**< A OR B. */ + prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, /**< Logical 1. */ +} PRS_Logic_t; +#endif + +/** PRS Signal. */ +typedef enum { +#if defined(_PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + prsSignalNone = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x0 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x1 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#else + prsSignalNone = PRS_CH_CTRL_SOURCESEL_NONE | (0x0 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_CH_CTRL_SOURCESEL_NONE | (0x1 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#endif + +#if defined(PRS_PRS_CH11) + prsSignalPRS_CH0 = PRS_PRS_CH0, /**< PRS_CH0 signal */ + prsSignalPRS_CH1 = PRS_PRS_CH1, /**< PRS_CH1 signal */ + prsSignalPRS_CH2 = PRS_PRS_CH2, /**< PRS_CH2 signal */ + prsSignalPRS_CH3 = PRS_PRS_CH3, /**< PRS_CH3 signal */ + prsSignalPRS_CH4 = PRS_PRS_CH4, /**< PRS_CH4 signal */ + prsSignalPRS_CH5 = PRS_PRS_CH5, /**< PRS_CH5 signal */ + prsSignalPRS_CH6 = PRS_PRS_CH6, /**< PRS_CH6 signal */ + prsSignalPRS_CH7 = PRS_PRS_CH7, /**< PRS_CH7 signal */ + prsSignalPRS_CH8 = PRS_PRS_CH8, /**< PRS_CH8 signal */ + prsSignalPRS_CH9 = PRS_PRS_CH9, /**< PRS_CH9 signal */ + prsSignalPRS_CH10 = PRS_PRS_CH10, /**< PRS_CH10 signal */ + prsSignalPRS_CH11 = PRS_PRS_CH11, /**< PRS_CH11 signal */ +#endif +#if defined(PRS_PRS_CH23) + prsSignalPRS_CH12 = PRS_PRS_CH12, /**< PRS_CH12 signal */ + prsSignalPRS_CH13 = PRS_PRS_CH13, /**< PRS_CH13 signal */ + prsSignalPRS_CH14 = PRS_PRS_CH14, /**< PRS_CH14 signal */ + prsSignalPRS_CH15 = PRS_PRS_CH15, /**< PRS_CH15 signal */ + prsSignalPRS_CH16 = PRS_PRS_CH16, /**< PRS_CH16 signal */ + prsSignalPRS_CH17 = PRS_PRS_CH17, /**< PRS_CH17 signal */ + prsSignalPRS_CH18 = PRS_PRS_CH18, /**< PRS_CH18 signal */ + prsSignalPRS_CH19 = PRS_PRS_CH19, /**< PRS_CH19 signal */ + prsSignalPRS_CH20 = PRS_PRS_CH20, /**< PRS_CH20 signal */ + prsSignalPRS_CH21 = PRS_PRS_CH21, /**< PRS_CH21 signal */ + prsSignalPRS_CH22 = PRS_PRS_CH22, /**< PRS_CH22 signal */ + prsSignalPRS_CH23 = PRS_PRS_CH23, /**< PRS_CH23 signal */ +#endif + +#if defined(PRS_ADC0_SINGLE) + prsSignalADC0_SINGLE = PRS_ADC0_SINGLE, /**< ADC0_SINGLE signal */ + prsSignalADC0_SCAN = PRS_ADC0_SCAN, /**< ADC0_SCAN signal */ +#endif +#if defined(PRS_ADC1_SINGLE) + prsSignalADC1_SINGLE = PRS_ADC1_SINGLE, /**< ADC1_SINGLE signal */ + prsSignalADC1_SCAN = PRS_ADC1_SCAN, /**< ADC1_SCAN signal */ +#endif + + /* Timer Signals */ +#if defined(TIMER0) + prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ + prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ + prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ + prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ + prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER1) + prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ + prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ + prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ + prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ + prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER2) + prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ + prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ + prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ + prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ + prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER3) + prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ + prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ + prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ + prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ + prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ +#if defined(PRS_TIMER1_CC3) + prsSignalTIMER1_CC3 = PRS_TIMER1_CC3, /**< TIMER3 capture/compare channel 3 Signal. */ +#endif +#endif +#if defined(TIMER4) + prsSignalTIMER4_UF = PRS_TIMER4_UF, /**< TIMER4 underflow Signal. */ + prsSignalTIMER4_OF = PRS_TIMER4_OF, /**< TIMER4 overflow Signal. */ + prsSignalTIMER4_CC0 = PRS_TIMER4_CC0, /**< TIMER4 capture/compare channel 0 Signal. */ + prsSignalTIMER4_CC1 = PRS_TIMER4_CC1, /**< TIMER4 capture/compare channel 1 Signal. */ + prsSignalTIMER4_CC2 = PRS_TIMER4_CC2, /**< TIMER4 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER5) + prsSignalTIMER5_UF = PRS_TIMER5_UF, /**< TIMER5 underflow Signal. */ + prsSignalTIMER5_OF = PRS_TIMER5_OF, /**< TIMER5 overflow Signal. */ + prsSignalTIMER5_CC0 = PRS_TIMER5_CC0, /**< TIMER5 capture/compare channel 0 Signal. */ + prsSignalTIMER5_CC1 = PRS_TIMER5_CC1, /**< TIMER5 capture/compare channel 1 Signal. */ + prsSignalTIMER5_CC2 = PRS_TIMER5_CC2, /**< TIMER5 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER6) + prsSignalTIMER6_UF = PRS_TIMER6_UF, /**< TIMER6 underflow Signal. */ + prsSignalTIMER6_OF = PRS_TIMER6_OF, /**< TIMER6 overflow Signal. */ + prsSignalTIMER6_CC0 = PRS_TIMER6_CC0, /**< TIMER6 capture/compare channel 0 Signal. */ + prsSignalTIMER6_CC1 = PRS_TIMER6_CC1, /**< TIMER6 capture/compare channel 1 Signal. */ + prsSignalTIMER6_CC2 = PRS_TIMER6_CC2, /**< TIMER6 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER7) + prsSignalTIMER7_UF = PRS_TIMER7_UF, /**< TIMER7 underflow Signal. */ + prsSignalTIMER7_OF = PRS_TIMER7_OF, /**< TIMER7 overflow Signal. */ + prsSignalTIMER7_CC0 = PRS_TIMER7_CC0, /**< TIMER7 capture/compare channel 0 Signal. */ + prsSignalTIMER7_CC1 = PRS_TIMER7_CC1, /**< TIMER7 capture/compare channel 1 Signal. */ + prsSignalTIMER7_CC2 = PRS_TIMER7_CC2, /**< TIMER7 capture/compare channel 2 Signal. */ +#endif +#if defined(PRS_LETIMER0_CH0) + prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ + prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ +#endif +#if defined(PRS_LETIMER1_CH0) + prsSignalLETIMER1_CH0 = PRS_LETIMER1_CH0, /**< LETIMER1 channel 0 Signal. */ + prsSignalLETIMER1_CH1 = PRS_LETIMER1_CH1, /**< LETIMER1 channel 1 Signal. */ +#endif +#if defined(PRS_PCNT0_TCC) + prsSignalPCNT0_TCC = PRS_PCNT0_TCC, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT0_UFOF) + prsSignalPCNT0_UFOF = PRS_PCNT0_UFOF, /**< PCNT0_TCC Signal. */ + prsSignalPCNT0_DIR = PRS_PCNT0_DIR, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT1_TCC) + prsSignalPCNT1_TCC = PRS_PCNT1_TCC, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_UFOF = PRS_PCNT1_UFOF, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_DIR = PRS_PCNT1_DIR, /**< PCNT1_TCC Signal. */ +#endif +#if defined(PRS_PCNT2_TCC) + prsSignalPCNT2_TCC = PRS_PCNT2_TCC, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_UFOF = PRS_PCNT2_UFOF, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_DIR = PRS_PCNT2_DIR, /**< PCNT2_TCC Signal. */ +#endif +#if defined(PRS_CRYOTIMER_PERIOD) + prsSignalCRYOTIMER_PERIOD = PRS_CRYOTIMER_PERIOD, /**< CRYOTIMER_PERIOD Signal. */ +#endif +#if defined(PRS_CORE_CTIOUT0) + prsSignalCORE_CTIOUT0 = PRS_CORE_CTIOUT0, /**< CORE CTIOUT0 Signal. */ + prsSignalCORE_CTIOUT1 = PRS_CORE_CTIOUT1, /**< CORE CTIOUT1 Signal. */ + prsSignalCORE_CTIOUT2 = PRS_CORE_CTIOUT2, /**< CORE CTIOUT2 Signal. */ + prsSignalCORE_CTIOUT3 = PRS_CORE_CTIOUT3, /**< CORE CTIOUT3 Signal. */ +#endif +#if defined(PRS_CMUL_CLKOUT0) + prsSignalCMUL_CLKOUT0 = PRS_CMUL_CLKOUT0, /**< CMU CLKOUT0 Signal. */ + prsSignalCMUL_CLKOUT1 = PRS_CMUL_CLKOUT1, /**< CMU CLKOUT1 Signal. */ + prsSignalCMUL_CLKOUT2 = PRS_CMUL_CLKOUT2, /**< CMU CLKOUT2 Signal. */ +#endif +#if defined(PRS_PRSL_ASYNCH0) + prsSignalPRSL_ASYNCH0 = PRS_PRSL_ASYNCH0, /**< PRS channel 0 Signal. */ + prsSignalPRSL_ASYNCH1 = PRS_PRSL_ASYNCH1, /**< PRS channel 1 Signal. */ + prsSignalPRSL_ASYNCH2 = PRS_PRSL_ASYNCH2, /**< PRS channel 2 Signal. */ + prsSignalPRSL_ASYNCH3 = PRS_PRSL_ASYNCH3, /**< PRS channel 3 Signal. */ + prsSignalPRSL_ASYNCH4 = PRS_PRSL_ASYNCH4, /**< PRS channel 4 Signal. */ + prsSignalPRSL_ASYNCH5 = PRS_PRSL_ASYNCH5, /**< PRS channel 5 Signal. */ + prsSignalPRSL_ASYNCH6 = PRS_PRSL_ASYNCH6, /**< PRS channel 6 Signal. */ + prsSignalPRSL_ASYNCH7 = PRS_PRSL_ASYNCH7, /**< PRS channel 7 Signal. */ + prsSignalPRS_ASYNCH8 = PRS_PRS_ASYNCH8, /**< PRS channel 8 Signal. */ + prsSignalPRS_ASYNCH9 = PRS_PRS_ASYNCH9, /**< PRS channel 9 Signal. */ + prsSignalPRS_ASYNCH10 = PRS_PRS_ASYNCH10, /**< PRS channel 10 Signal. */ + prsSignalPRS_ASYNCH11 = PRS_PRS_ASYNCH11, /**< PRS channel 11 Signal. */ +#endif + + /* RTC/RTCC/SYSRTC/BURTC Signals */ +#if defined(PRS_RTC_OF) + prsSignalRTC_OF = PRS_RTC_OF, /**< RTC_OF signal. */ + prsSignalRTC_COMP0 = PRS_RTC_COMP0, /**< RTC_COMP0 signal. */ + prsSignalRTC_COMP1 = PRS_RTC_COMP1, /**< RTC_COMP1 signal. */ +#if defined(PRS_RTC_COMP5) + prsSignalRTC_COMP2 = PRS_RTC_COMP2, /**< RTC_COMP2 signal. */ + prsSignalRTC_COMP3 = PRS_RTC_COMP3, /**< RTC_COMP3 signal. */ + prsSignalRTC_COMP4 = PRS_RTC_COMP4, /**< RTC_COMP4 signal. */ + prsSignalRTC_COMP5 = PRS_RTC_COMP5, /**< RTC_COMP5 signal. */ +#endif +#endif +#if defined(RTCC) + prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ + prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ + prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ +#endif +#if defined(BURTC) + prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ + prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ +#endif +#if defined(SYSRTC0) + prsSignalSYSRTC0_GRP0OUT0 = PRS_SYSRTC0_GRP0OUT0, /**< SYSRTC GRP0OUT0 Signal. */ + prsSignalSYSRTC0_GRP0OUT1 = PRS_SYSRTC0_GRP0OUT1, /**< SYSRTC GRP0OUT1 Signal. */ + prsSignalSYSRTC0_GRP1OUT0 = PRS_SYSRTC0_GRP1OUT0, /**< SYSRTC GRP1OUT0 Signal. */ + prsSignalSYSRTC0_GRP1OUT1 = PRS_SYSRTC0_GRP1OUT1, /**< SYSRTC GRP1OUT1 Signal. */ +#endif +#if defined(PRS_HFXO0L_STATUS) + prsSignalHFXO0L_STATUS = PRS_HFXO0L_STATUS, /**< HFXO0L_STATUS Signal. */ + prsSignalHFXO0L_STATUS1 = PRS_HFXO0L_STATUS1, /**< HFXO0L_STATUS1 Signal. */ +#endif +#if defined(PRS_HFRCO0_COREEN) + prsSignalHFRCO0_COREEN = PRS_HFRCO0_COREEN, /**< HFRCO0_COREEN Signal. */ + prsSignalHFRCO0_STATE0 = PRS_HFRCO0_STATE0, /**< HFRCO0_STATE0 Signal. */ + prsSignalHFRCO0_STATE1 = PRS_HFRCO0_STATE1, /**< HFRCO0_STATE1 Signal. */ + prsSignalHFRCO0_STATE2 = PRS_HFRCO0_STATE2, /**< HFRCO0_STATE2 Signal. */ +#endif +#if defined(PRS_HFRCOEM23_COREEN) + prsSignalHFRCOEM23_COREEN = PRS_HFRCOEM23_COREEN, /**< HFRCOEM23_COREEN Signal. */ + prsSignalHFRCOEM23_STATE0 = PRS_HFRCOEM23_STATE0, /**< HFRCOEM23_STATE0 Signal. */ + prsSignalHFRCOEM23_STATE1 = PRS_HFRCOEM23_STATE1, /**< HFRCOEM23_STATE1 Signal. */ + prsSignalHFRCOEM23_STATE2 = PRS_HFRCOEM23_STATE2, /**< HFRCOEM23_STATE2 Signal. */ +#endif + + /* ACMP Signals */ +#if defined(ACMP0) + prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ +#endif +#if defined(ACMP1) + prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ +#endif +#if defined(ACMP2) + prsSignalACMP2_OUT = PRS_ACMP2_OUT, /**< ACMP2 output Signal. */ +#endif +#if defined(ACMP3) + prsSignalACMP3_OUT = PRS_ACMP3_OUT, /**< ACMP3 output Signal. */ +#endif + + /* VDAC Signals */ +#if defined(VDAC0) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC0_CH0WARM = PRS_VDAC0L_CH0WARM, /**< VDAC0 channel 0 warmed Signal. */ + prsSignalVDAC0_CH1WARM = PRS_VDAC0L_CH1WARM, /**< VDAC0 channel 1 warmed Signal. */ + prsSignalVDAC0_CH0DONE = PRS_VDAC0L_CH0DONEASYNC, /**< VDAC0 channel 0 conversion done Signal. */ + prsSignalVDAC0_CH1DONE = PRS_VDAC0L_CH1DONEASYNC, /**< VDAC0 channel 1 conversion done Signal. */ + prsSignalVDAC0_INTERNALTIMEROF = PRS_VDAC0L_INTERNALTIMEROF, /**< VDAC0 internal timer overflow Signal. */ + prsSignalVDAC0_REFRESHTIMEROF = PRS_VDAC0L_REFRESHTIMEROF, /**< VDAC0 internal timer overflow Signal. */ +#endif +#if defined(PRS_VDAC0_OPA3) + prsSignalVDAC0_CH0 = PRS_VDAC0_CH0, /**< VDAC0_CH0 Signal. */ + prsSignalVDAC0_CH1 = PRS_VDAC0_CH1, /**< VDAC0_CH1 Signal. */ + prsSignalVDAC0_OPA0 = PRS_VDAC0_OPA0, /**< VDAC0_OPA0 Signal. */ + prsSignalVDAC0_OPA1 = PRS_VDAC0_OPA1, /**< VDAC0_OPA1 Signal. */ + prsSignalVDAC0_OPA2 = PRS_VDAC0_OPA2, /**< VDAC0_OPA2 Signal. */ + prsSignalVDAC0_OPA3 = PRS_VDAC0_OPA3, /**< VDAC0_OPA3 Signal. */ +#endif +#if defined(VDAC1) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC1_CH0WARM = PRS_VDAC1L_CH0WARM, /**< VDAC1 channel 0 warmed Signal. */ + prsSignalVDAC1_CH1WARM = PRS_VDAC1L_CH1WARM, /**< VDAC1 channel 1 warmed Signal. */ + prsSignalVDAC1_CH0DONE = PRS_VDAC1L_CH0DONEASYNC, /**< VDAC1 channel 0 conversion done Signal. */ + prsSignalVDAC1_CH1DONE = PRS_VDAC1L_CH1DONEASYNC, /**< VDAC1 channel 1 conversion done Signal. */ + prsSignalVDAC1_INTERNALTIMEROF = PRS_VDAC1L_INTERNALTIMEROF, /**< VDAC1 internal timer overflow Signal. */ + prsSignalVDAC1_REFRESHTIMEROF = PRS_VDAC1L_REFRESHTIMEROF, /**< VDAC1 internal timer overflow Signal. */ +#endif + +#if defined(PRS_LESENSE_SCANRES15) + prsSignalLESENSE_SCANRES0 = PRS_LESENSE_SCANRES0, /**< LESENSE_SCANRES0 Signal. */ + prsSignalLESENSE_SCANRES1 = PRS_LESENSE_SCANRES1, /**< LESENSE_SCANRES1 Signal. */ + prsSignalLESENSE_SCANRES2 = PRS_LESENSE_SCANRES2, /**< LESENSE_SCANRES2 Signal. */ + prsSignalLESENSE_SCANRES3 = PRS_LESENSE_SCANRES3, /**< LESENSE_SCANRES3 Signal. */ + prsSignalLESENSE_SCANRES4 = PRS_LESENSE_SCANRES4, /**< LESENSE_SCANRES4 Signal. */ + prsSignalLESENSE_SCANRES5 = PRS_LESENSE_SCANRES5, /**< LESENSE_SCANRES5 Signal. */ + prsSignalLESENSE_SCANRES6 = PRS_LESENSE_SCANRES6, /**< LESENSE_SCANRES6 Signal. */ + prsSignalLESENSE_SCANRES7 = PRS_LESENSE_SCANRES7, /**< LESENSE_SCANRES7 Signal. */ + prsSignalLESENSE_SCANRES8 = PRS_LESENSE_SCANRES8, /**< LESENSE_SCANRES8 Signal. */ + prsSignalLESENSE_SCANRES9 = PRS_LESENSE_SCANRES9, /**< LESENSE_SCANRES9 Signal. */ + prsSignalLESENSE_SCANRES10 = PRS_LESENSE_SCANRES10, /**< LESENSE_SCANRES10 Signal. */ + prsSignalLESENSE_SCANRES11 = PRS_LESENSE_SCANRES11, /**< LESENSE_SCANRES11 Signal. */ + prsSignalLESENSE_SCANRES12 = PRS_LESENSE_SCANRES12, /**< LESENSE_SCANRES12 Signal. */ + prsSignalLESENSE_SCANRES13 = PRS_LESENSE_SCANRES13, /**< LESENSE_SCANRES13 Signal. */ + prsSignalLESENSE_SCANRES14 = PRS_LESENSE_SCANRES14, /**< LESENSE_SCANRES14 Signal. */ + prsSignalLESENSE_SCANRES15 = PRS_LESENSE_SCANRES15, /**< LESENSE_SCANRES15 Signal. */ +#endif +#if defined(PRS_LESENSE_DEC2) + prsSignalLESENSE_DEC0 = PRS_LESENSE_DEC0, /**< LESENSE_DEC0 Signal. */ + prsSignalLESENSE_DEC1 = PRS_LESENSE_DEC1, /**< LESENSE_DEC1 Signal. */ + prsSignalLESENSE_DEC2 = PRS_LESENSE_DEC2, /**< LESENSE_DEC2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECOUT2) + prsSignalLESENSE_DECOUT0 = PRS_LESENSE_DECOUT0, /**< LESENSE_DECOUT0 Signal. */ + prsSignalLESENSE_DECOUT1 = PRS_LESENSE_DECOUT1, /**< LESENSE_DECOUT1 Signal. */ + prsSignalLESENSE_DECOUT2 = PRS_LESENSE_DECOUT2, /**< LESENSE_DECOUT2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECCMP) + prsSignalLESENSE_DECCMP = PRS_LESENSE_DECCMP, /**< LESENSE_DECCMP Signal. */ +#endif +#if defined(PRS_LESENSE_MEASACT) + prsSignalLESENSE_MEASACT = PRS_LESENSE_MEASACT, /**< LESENSE_MEASACT Signal. */ +#endif + + /* USART Signals */ +#if defined(USART0) + prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 TX complete Signal. */ +#if defined(PRS_USART0_RXDATA) + prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_RXDATAV) + prsSignalUSART0_RXDATAV = PRS_USART0_RXDATAV, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_IRTX) + prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR TX Signal. */ +#endif +#if defined(PRS_USART0_RTS) + prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ + prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 TX Signal. */ + prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ +#endif +#endif +#if defined(USART1) + prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 TX complete Signal. */ +#if defined(PRS_USART1_RXDATA) + prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_RXDATAV) + prsSignalUSART1_RXDATAV = PRS_USART1_RXDATAV, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_IRTX) + prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR TX Signal. */ +#endif +#if defined(PRS_USART1_RTS) + prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ + prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 TX Signal. */ + prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ +#endif +#endif +#if defined(USART2) + prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 TX complete Signal. */ +#if defined(PRS_USART2_RXDATA) + prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_RXDATAV) + prsSignalUSART2_RXDATAV = PRS_USART2_RXDATAV, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_IRTX) + prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR TX Signal. */ +#endif +#if defined(PRS_USART2_RTS) + prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ + prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 TX Signal. */ + prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ +#endif +#endif +#if defined(PRS_USART3_TXC) + prsSignalUSART3_TXC = PRS_USART3_TXC, /**< USART3 TX complete Signal. */ + prsSignalUSART3_RXDATAV = PRS_USART3_RXDATAV, /**< USART3 RX data available Signal. */ + prsSignalUSART3_RTS = PRS_USART3_RTS, /**< USART3 RTS Signal. */ + prsSignalUSART3_TX = PRS_USART3_TX, /**< USART3 TX Signal. */ + prsSignalUSART3_CS = PRS_USART3_CS, /**< USART3 chip select Signal. */ +#endif +#if defined(PRS_USART4_TXC) + prsSignalUSART4_TXC = PRS_USART4_TXC, /**< USART4 TX complete Signal. */ + prsSignalUSART4_RXDATAV = PRS_USART4_RXDATAV, /**< USART4 RX data available Signal. */ + prsSignalUSART4_RTS = PRS_USART4_RTS, /**< USART4 RTS Signal. */ + prsSignalUSART4_TX = PRS_USART4_TX, /**< USART4 TX Signal. */ + prsSignalUSART4_CS = PRS_USART4_CS, /**< USART4 chip select Signal. */ +#endif +#if defined(PRS_USART5_TXC) + prsSignalUSART5_TXC = PRS_USART5_TXC, /**< USART5 TX complete Signal. */ + prsSignalUSART5_RXDATAV = PRS_USART5_RXDATAV, /**< USART5 RX data available Signal. */ + prsSignalUSART5_RTS = PRS_USART5_RTS, /**< USART5 RTS Signal. */ + prsSignalUSART5_TX = PRS_USART5_TX, /**< USART5 TX Signal. */ + prsSignalUSART5_CS = PRS_USART5_CS, /**< USART5 chip select Signal. */ +#endif + +#if defined(UART0) + prsSignalUART0_TXC = PRS_UART0_TXC, /**< UART0 TX complete Signal. */ + prsSignalUART0_RXDATAV = PRS_UART0_RXDATAV, /**< UART0 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART0_IRTX = PRS_UART0_IRTX, /**< UART0 IR TX Signal. */ +#endif +#if defined(PRS_UART0_RTS) + prsSignalUART0_RTS = PRS_UART0_RTS, /**< UART0 RTS Signal. */ + prsSignalUART0_TX = PRS_UART0_TX, /**< UART0 TX Signal. */ + prsSignalUART0_CS = PRS_UART0_CS, /**< UART0 chip select Signal. */ +#endif +#endif + +#if defined(UART1) + prsSignalUART1_TXC = PRS_UART1_TXC, /**< UART1 TX complete Signal. */ + prsSignalUART1_RXDATAV = PRS_UART1_RXDATAV, /**< UART1 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART1_IRTX = PRS_UART1_IRTX, /**< UART1 IR RX Signal. */ +#endif +#if defined(PRS_UART1_RTS) + prsSignalUART1_RTS = PRS_UART1_RTS, /**< UART1 RTS Signal. */ + prsSignalUART1_TX = PRS_UART1_TX, /**< UART1 RX Signal. */ + prsSignalUART1_CS = PRS_UART1_CS, /**< UART1 chip select Signal. */ +#endif +#endif + +#if defined(PRS_USB_SOF) + prsSignalUSB_SOF = PRS_USB_SOF, /**< USB_SOF Signal. */ + prsSignalUSB_SOFSR = PRS_USB_SOFSR, /**< USB_SOFSR Signal. */ +#endif + +#if defined(PRS_CM4_TXEV) + prsSignalCM4_TXEV = PRS_CM4_TXEV, /**< TXEV Signal. */ +#endif +#if defined(PRS_CM4_ICACHEPCHITSOF) + prsSignalCM4_ICACHEPCHITSOF = PRS_CM4_ICACHEPCHITSOF, /**< ICACHEPCHITSOF Signal. */ + prsSignalCM4_ICACHEPCMISSESOF = PRS_CM4_ICACHEPCMISSESOF, /**< ICACHEPCMISSESOF Signal. */ +#endif + +#if defined(PRS_WTIMER0_UF) + prsSignalWTIMER0_UF = PRS_WTIMER0_UF, /**< WTIMER0_UF Signal. */ + prsSignalWTIMER0_OF = PRS_WTIMER0_OF, /**< WTIMER0_OF Signal. */ + prsSignalWTIMER0_CC0 = PRS_WTIMER0_CC0, /**< WTIMER0_CC0 Signal. */ + prsSignalWTIMER0_CC1 = PRS_WTIMER0_CC1, /**< WTIMER0_CC1 Signal. */ + prsSignalWTIMER0_CC2 = PRS_WTIMER0_CC2, /**< WTIMER0_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER1_UF) + prsSignalWTIMER1_UF = PRS_WTIMER1_UF, /**< WTIMER1_UF Signal. */ + prsSignalWTIMER1_OF = PRS_WTIMER1_OF, /**< WTIMER1_OF Signal. */ + prsSignalWTIMER1_CC0 = PRS_WTIMER1_CC0, /**< WTIMER1_CC0 Signal. */ + prsSignalWTIMER1_CC1 = PRS_WTIMER1_CC1, /**< WTIMER1_CC1 Signal. */ + prsSignalWTIMER1_CC2 = PRS_WTIMER1_CC2, /**< WTIMER1_CC2 Signal. */ + prsSignalWTIMER1_CC3 = PRS_WTIMER1_CC3, /**< WTIMER1_CC3 Signal. */ +#endif +#if defined(PRS_WTIMER2_UF) + prsSignalWTIMER2_UF = PRS_WTIMER2_UF, /**< WTIMER2_UF Signal. */ + prsSignalWTIMER2_OF = PRS_WTIMER2_OF, /**< WTIMER2_OF Signal. */ + prsSignalWTIMER2_CC0 = PRS_WTIMER2_CC0, /**< WTIMER2_CC0 Signal. */ + prsSignalWTIMER2_CC1 = PRS_WTIMER2_CC1, /**< WTIMER2_CC1 Signal. */ + prsSignalWTIMER2_CC2 = PRS_WTIMER2_CC2, /**< WTIMER2_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER3_UF) + prsSignalWTIMER3_UF = PRS_WTIMER3_UF, /**< WTIMER3_UF Signal. */ + prsSignalWTIMER3_OF = PRS_WTIMER3_OF, /**< WTIMER3_OF Signal. */ + prsSignalWTIMER3_CC0 = PRS_WTIMER3_CC0, /**< WTIMER3_CC0 Signal. */ + prsSignalWTIMER3_CC1 = PRS_WTIMER3_CC1, /**< WTIMER3_CC1 Signal. */ + prsSignalWTIMER3_CC2 = PRS_WTIMER3_CC2, /**< WTIMER3_CC2 Signal. */ +#endif + +/* EUSART Signals */ +#if defined(EUSART0) + prsSignalEUSART0_CS = PRS_EUSART0L_CS, /**< EUSART0 chip select Signal. */ + prsSignalEUSART0_IRTX = PRS_EUSART0L_IRDATX, /**< EUSART0 IR RX Signal. */ + prsSignalEUSART0_RTS = PRS_EUSART0L_RTS, /**< EUSART0 RTS Signal. */ + prsSignalEUSART0_RXDATA = PRS_EUSART0L_RXDATAV, /**< EUSART0 RX data available Signal. */ + prsSignalEUSART0_TX = PRS_EUSART0L_TX, /**< EUSART0 TX Signal. */ + prsSignalEUSART0_TXC = PRS_EUSART0L_TXC, /**< EUSART0 TX complete Signal. */ + prsSignalEUSART0_RXFL = PRS_EUSART0L_RXFL, /**< EUSART0 rxfl Signal. */ + prsSignalEUSART0_TXFL = PRS_EUSART0L_TXFL, /**< EUSART0 txfl Signal. */ +#endif +#if defined(EUSART1) + prsSignalEUSART1_CS = PRS_EUSART1L_CS, /**< EUSART1 chip select Signal. */ + prsSignalEUSART1_IRTX = PRS_EUSART1L_IRDATX, /**< EUSART1 IR TX Signal. */ + prsSignalEUSART1_RTS = PRS_EUSART1L_RTS, /**< EUSART1 RTS Signal. */ + prsSignalEUSART1_RXDATA = PRS_EUSART1L_RXDATAV, /**< EUSART1 RX data available Signal. */ + prsSignalEUSART1_TX = PRS_EUSART1L_TX, /**< EUSART1 TX Signal. */ + prsSignalEUSART1_TXC = PRS_EUSART1L_TXC, /**< EUSART1 TX complete Signal. */ + prsSignalEUSART1_RXFL = PRS_EUSART1L_RXFL, /**< EUSART1 rxfl Signal. */ + prsSignalEUSART1_TXFL = PRS_EUSART1L_TXFL, /**< EUSART1 txfl Signal. */ +#endif +#if defined(EUSART2) +#if defined(PRS_EUSART2L_CS) + prsSignalEUSART2_CS = PRS_EUSART2L_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2L_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2L_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2L_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2L_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2L_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2L_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2L_TXFL, /**< EUSART2 txfl Signal. */ +#else + prsSignalEUSART2_CS = PRS_EUSART2_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2_TXFL, /**< EUSART2 txfl Signal. */ +#endif +#endif +#if defined(EUSART3) +#if defined(PRS_EUSART3L_CS) + prsSignalEUSART3_CS = PRS_EUSART3L_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3L_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3L_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3L_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3L_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3L_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3L_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3L_TXFL, /**< EUSART3 txfl Signal. */ +#else + prsSignalEUSART3_CS = PRS_EUSART3_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3_TXFL, /**< EUSART3 txfl Signal. */ +#endif +#endif +#if defined(EUSART4) + prsSignalEUSART4_CS = PRS_EUSART4L_CS, /**< EUSART4 chip select Signal. */ + prsSignalEUSART4_IRTX = PRS_EUSART4L_IRDATX, /**< EUSART4 IR TX Signal. */ + prsSignalEUSART4_RTS = PRS_EUSART4L_RTS, /**< EUSART4 RTS Signal. */ + prsSignalEUSART4_RXDATA = PRS_EUSART4L_RXDATAV, /**< EUSART4 RX data available Signal. */ + prsSignalEUSART4_TX = PRS_EUSART4L_TX, /**< EUSART4 TX Signal. */ + prsSignalEUSART4_TXC = PRS_EUSART4L_TXC, /**< EUSART4 TX complete Signal. */ + prsSignalEUSART4_RXFL = PRS_EUSART4L_RXFL, /**< EUSART4 rxfl Signal. */ + prsSignalEUSART4_TXFL = PRS_EUSART4L_TXFL, /**< EUSART4 txfl Signal. */ +#endif + /* ADC Signals */ +#if defined(IADC0) + prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ + prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ + prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ +#endif + + /* GPIO pin Signals */ + prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ + prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ + prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ + prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ + prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ + prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ + prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ + prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ +#if defined(PRS_GPIO_PIN15) + prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ + prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ + prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ + prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ + prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ + prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ + prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ + prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ +#endif +#if defined(PRS_AGCL_CCA) + prsSignalAGCL_CCA = PRS_AGCL_CCA, /**< AGCL_CCA Signal. */ + prsSignalAGCL_CCAREQ = PRS_AGCL_CCAREQ, /**< AGCL_CCAREQ Signal. */ + prsSignalAGCL_GAINADJUST = PRS_AGCL_GAINADJUST, /**< AGCL_GAINADJUST Signal. */ + prsSignalAGCL_GAINOK = PRS_AGCL_GAINOK, /**< AGCL_GAINOK Signal. */ + prsSignalAGCL_GAINREDUCED = PRS_AGCL_GAINREDUCED, /**< AGCL_GAINREDUCED Signal. */ + prsSignalAGCL_IFPKI1 = PRS_AGCL_IFPKI1, /**< AGCL_IFPKI1 Signal. */ + prsSignalAGCL_IFPKQ2 = PRS_AGCL_IFPKQ2, /**< AGCL_IFPKQ2 Signal. */ + prsSignalAGCL_IFPKRST = PRS_AGCL_IFPKRST, /**< AGCL_IFPKRST Signal. */ +#endif +#if defined(PRS_AGC_PEAKDET) + prsSignalAGC_PEAKDET = PRS_AGC_PEAKDET, /**< AGC_PEAKDET Signal. */ + prsSignalAGC_PROPAGATED = PRS_AGC_PROPAGATED, /**< AGC_PROPAGATED Signal. */ + prsSignalAGC_RSSIDONE = PRS_AGC_RSSIDONE, /**< AGC_RSSIDONE Signal. */ +#endif +#if defined(PRS_BUFC_THR0) + prsSignalBUFC_THR0 = PRS_BUFC_THR0, /**< BUFC_THR0 Signal. */ + prsSignalBUFC_THR1 = PRS_BUFC_THR1, /**< BUFC_THR1 Signal. */ + prsSignalBUFC_THR2 = PRS_BUFC_THR2, /**< BUFC_THR2 Signal. */ + prsSignalBUFC_THR3 = PRS_BUFC_THR3, /**< BUFC_THR3 Signal. */ +#endif +#if defined(PRS_BUFC_CNT0) + prsSignalBUFC_CNT0 = PRS_BUFC_CNT0, /**< BUFC_CNT0 Signal. */ + prsSignalBUFC_CNT1 = PRS_BUFC_CNT1, /**< BUFC_CNT1 Signal. */ + prsSignalBUFC_FULL = PRS_BUFC_FULL, /**< BUFC_FULL Signal. */ +#endif +#if defined(PRS_MODEML_ADVANCE) + prsSignalMODEML_ADVANCE = PRS_MODEML_ADVANCE, /**< MODEML_ADVANCE Signal. */ + prsSignalMODEML_ANT0 = PRS_MODEML_ANT0, /**< MODEML_ANT0 Signal. */ + prsSignalMODEML_ANT1 = PRS_MODEML_ANT1, /**< MODEML_ANT1 Signal. */ + prsSignalMODEML_COHDSADET = PRS_MODEML_COHDSADET, /**< MODEML_COHDSADET Signal. */ + prsSignalMODEML_COHDSALIVE = PRS_MODEML_COHDSALIVE, /**< MODEML_COHDSALIVE Signal. */ + prsSignalMODEML_DCLK = PRS_MODEML_DCLK, /**< MODEML_DCLK Signal. */ + prsSignalMODEML_DOUT = PRS_MODEML_DOUT, /**< MODEML_DOUT Signal. */ + prsSignalMODEML_FRAMEDET = PRS_MODEML_FRAMEDET, /**< MODEML_FRAMEDET Signal. */ +#endif +#if defined(PRS_MODEM_FRAMEDET) + prsSignalMODEM_FRAMEDET = PRS_MODEM_FRAMEDET, /**< MODEM_FRAMEDET Signal. */ + prsSignalMODEM_TIMDET = PRS_MODEM_TIMDET, /**< MODEM_TIMDET Signal. */ + prsSignalMODEM_SYNCSENT = PRS_MODEM_SYNCSENT, /**< MODEM_SYNCSENT Signal. */ + prsSignalMODEM_PRESENT = PRS_MODEM_PRESENT, /**< MODEM_PRESENT Signal. */ + prsSignalMODEM_ANT0 = PRS_MODEM_ANT0, /**< MODEM_ANT0 Signal. */ + prsSignalMODEM_ANT1 = PRS_MODEM_ANT1, /**< MODEM_ANT1 Signal. */ +#endif +#if defined(PRS_MODEM_FRAMESENT) + prsSignalMODEM_FRAMESENT = PRS_MODEM_FRAMESENT, /**< MODEM_FRAMESENT Signal. */ +#endif +#if defined(PRS_MODEM_PREDET) + prsSignalMODEM_PREDET = PRS_MODEM_PREDET, /**< MODEM_PREDET Signal. */ +#endif +#if defined(PRS_MODEM_LRDSADET) + prsSignalMODEM_LRDSADET = PRS_MODEM_LRDSADET, /**< MODEM_LRDSADET Signal. */ + prsSignalMODEM_LRDSALIVE = PRS_MODEM_LRDSALIVE, /**< MODEM_LRDSALIVE Signal. */ +#endif +#if defined(PRS_MODEM_LOWCORR) + prsSignalMODEM_LOWCORR = PRS_MODEM_LOWCORR, /**< MODEM_LOWCORR Signal. */ + prsSignalMODEM_NEWSYMBOL = PRS_MODEM_NEWSYMBOL, /**< MODEM_NEWSYMBOL Signal. */ + prsSignalMODEM_NEWWND = PRS_MODEM_NEWWND, /**< MODEM_NEWWND Signal. */ + prsSignalMODEM_POSTPONE = PRS_MODEM_POSTPONE, /**< MODEM_POSTPONE Signal. */ +#endif +#if defined(PRS_MODEMH_PRESENT) + prsSignalMODEMH_PRESENT = PRS_MODEMH_PRESENT, /**< MODEMH_PRESENT Signal. */ + prsSignalMODEMH_RSSIJUMP = PRS_MODEMH_RSSIJUMP, /**< MODEMH_RSSIJUMP Signal. */ + prsSignalMODEMH_SYNCSENT = PRS_MODEMH_SYNCSENT, /**< MODEMH_SYNCSENT Signal. */ + prsSignalMODEMH_TIMDET = PRS_MODEMH_TIMDET, /**< MODEMH_TIMDET Signal. */ + prsSignalMODEMH_WEAK = PRS_MODEMH_WEAK, /**< MODEMH_WEAK Signal. */ + prsSignalMODEMH_EOF = PRS_MODEMH_EOF, /**< MODEMH_EOF Signal. */ +#endif +#if defined(PRS_MODEMH_SI) + prsSignalMODEMH_SI = PRS_MODEMH_SI, /**< MODEMH_SI Signal. */ +#endif +#if defined(PRS_FRC_DCLK) + prsSignalFRC_DCLK = PRS_FRC_DCLK, /**< FRC_DCLK Signal. */ + prsSignalFRC_DOUT = PRS_FRC_DOUT, /**< FRC_DOUT Signal. */ +#endif +#if defined(PRS_PROTIMERL_BOF) + prsSignalPROTIMERL_BOF = PRS_PROTIMERL_BOF, /**< PROTIMERL_BOF Signal. */ + prsSignalPROTIMERL_CC0 = PRS_PROTIMERL_CC0, /**< PROTIMERL_CC0 Signal. */ + prsSignalPROTIMERL_CC1 = PRS_PROTIMERL_CC1, /**< PROTIMERL_CC1 Signal. */ + prsSignalPROTIMERL_CC2 = PRS_PROTIMERL_CC2, /**< PROTIMERL_CC2 Signal. */ + prsSignalPROTIMERL_CC3 = PRS_PROTIMERL_CC3, /**< PROTIMERL_CC3 Signal. */ + prsSignalPROTIMERL_CC4 = PRS_PROTIMERL_CC4, /**< PROTIMERL_CC4 Signal. */ + prsSignalPROTIMERL_LBTF = PRS_PROTIMERL_LBTF, /**< PROTIMERL_LBTF Signal. */ + prsSignalPROTIMERL_LBTR = PRS_PROTIMERL_LBTR, /**< PROTIMERL_LBTR Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTR) + prsSignalPROTIMER_LBTR = PRS_PROTIMER_LBTR, /**< PROTIMER_LBTR Signal. */ + prsSignalPROTIMER_LBTF = PRS_PROTIMER_LBTF, /**< PROTIMER_LBTF Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTS) + prsSignalPROTIMER_LBTS = PRS_PROTIMER_LBTS, /**< PROTIMER_LBTS Signal. */ +#endif +#if defined(PRS_PROTIMER_POF) + prsSignalPROTIMER_POF = PRS_PROTIMER_POF, /**< PROTIMER_POF Signal. */ + prsSignalPROTIMER_T0MATCH = PRS_PROTIMER_T0MATCH, /**< PROTIMER_T0MATCH Signal. */ + prsSignalPROTIMER_T0UF = PRS_PROTIMER_T0UF, /**< PROTIMER_T0UF Signal. */ + prsSignalPROTIMER_T1MATCH = PRS_PROTIMER_T1MATCH, /**< PROTIMER_T1MATCH Signal. */ + prsSignalPROTIMER_T1UF = PRS_PROTIMER_T1UF, /**< PROTIMER_T1UF Signal. */ + prsSignalPROTIMER_WOF = PRS_PROTIMER_WOF, /**< PROTIMER_WOF Signal. */ +#endif +#if defined(PRS_RAC_ACTIVE) + prsSignalRAC_ACTIVE = PRS_RAC_ACTIVE, /**< RAC_ACTIVE Signal. */ + prsSignalRAC_LNAEN = PRS_RAC_LNAEN, /**< RAC_LNAEN Signal. */ + prsSignalRAC_PAEN = PRS_RAC_PAEN, /**< RAC_PAEN Signal. */ + prsSignalRAC_RX = PRS_RAC_RX, /**< RAC_RX Signal. */ + prsSignalRAC_TX = PRS_RAC_TX, /**< RAC_TX Signal. */ +#endif +#if defined(PRS_RACL_ACTIVE) + prsSignalRACL_ACTIVE = PRS_RACL_ACTIVE, /**< RACL_ACTIVE Signal. */ + prsSignalRACL_LNAEN = PRS_RACL_LNAEN, /**< RACL_LNAEN Signal. */ + prsSignalRACL_PAEN = PRS_RACL_PAEN, /**< RACL_PAEN Signal. */ + prsSignalRACL_RX = PRS_RACL_RX, /**< RACL_RX Signal. */ + prsSignalRACL_TX = PRS_RACL_TX, /**< RACL_TX Signal. */ + prsSignalRACL_CTIOUT0 = PRS_RACL_CTIOUT0, /**< RACL_CTIOUT0 Signal. */ + prsSignalRACL_CTIOUT1 = PRS_RACL_CTIOUT1, /**< RACL_CTIOUT1 Signal. */ + prsSignalRACL_CTIOUT2 = PRS_RACL_CTIOUT2, /**< RACL_CTIOUT2 Signal. */ +#endif +#if defined(PRS_RAC_CTIOUT3) + prsSignalRAC_CTIOUT3 = PRS_RAC_CTIOUT3, /**< RAC_CTIOUT3 Signal. */ +#endif +#if defined(PRS_RAC_AUXADCDATA) + prsSignalRAC_AUXADCDATA = PRS_RAC_AUXADCDATA, /**< RAC_AUXADCDATA Signal. */ + prsSignalRAC_AUXADCDATAVALID = PRS_RAC_AUXADCDATAVALID, /**< RAC_AUXADCDATAVALID Signal. */ +#endif +#if defined(PRS_SYNTH_MUX0) + prsSignalSYNTH_MUX0 = PRS_SYNTH_MUX0, /**< SYNTH_MUX0 Signal. */ + prsSignalSYNTH_MUX1 = PRS_SYNTH_MUX1, /**< SYNTH_MUX1 Signal. */ +#endif +#if defined(PRS_PRORTC_CCV0) + prsSignalPRORTC_CCV0 = PRS_PRORTC_CCV0, /**< PRORTC_CCV0 Signal. */ + prsSignalPRORTC_CCV1 = PRS_PRORTC_CCV1, /**< PRORTC_CCV1 Signal. */ +#endif +#if defined(RFFPLL0) + prsSignalRFFPLL0L_CLKDIGDIV4 = PRS_RFFPLL0L_CLKDIGDIV4, /**< RFFPLL0L CLKDIGDIV4 Signal. */ + prsSignalRFFPLL0L_CLKMODEMDIV4 = PRS_RFFPLL0L_CLKMODEMDIV4, /**< RFFPLL0L CLKMODEMDIV4 Signal. */ +#if defined(PRS_RFFPLL0L_RFBIASFSMSTATE0) + prsSignalRFFPLL0L_RFBIASFSMSTATE0 = PRS_RFFPLL0L_RFBIASFSMSTATE0, /**< RFFPLL0L RFBIASFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE1 = PRS_RFFPLL0L_RFBIASFSMSTATE1, /**< RFFPLL0L RFBIASFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE0 = PRS_RFFPLL0L_RFFPLLFSMSTATE0, /**< RFFPLL0L RFFPLLFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE1 = PRS_RFFPLL0L_RFFPLLFSMSTATE1, /**< RFFPLL0L RFFPLLFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE2 = PRS_RFFPLL0L_RFFPLLFSMSTATE2, /**< RFFPLL0L RFFPLLFSMSTATE2 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE2 = PRS_RFFPLL0L_RFBIASFSMSTATE2, /**< RFFPLL0L RFBIASFSMSTATE2 Signal. */ + prsSignalRFFPLL0_RFFPLLFSMSTATE3 = PRS_RFFPLL0_RFFPLLFSMSTATE3, /**< RFFPLL0 RFFPLLFSMSTATE3 Signal. */ +#endif +#endif +#if defined(FEFILT0) + prsSignalFEFILT0_REMPTY = PRS_FEFILT0_REMPTY, /**< FEFILT0 REMPTY Signal. */ + prsSignalFEFILT0_WFULL = PRS_FEFILT0_WFULL, /**< FEFILT0 WFULL Signal. */ +#endif +#if defined(FEFILT0) + prsSignalFEFILT1_REMPTY = PRS_FEFILT1_REMPTY, /**< FEFILT1 REMPTY Signal. */ + prsSignalFEFILT1_WFULL = PRS_FEFILT1_WFULL, /**< FEFILT1 WFULL Signal. */ +#endif +#if defined(ETAMPDET) + prsSignalETAMPDET_TAMPERSRCETAMPDET = PRS_ETAMPDET_TAMPERSRCETAMPDET, /**< ETAMPDET TAMPERSRCETAMPDET Signal. */ +#endif +#if defined(SMCTRL) + prsSignalSMCTRLL_SOFTM0 = PRS_SMCTRLL_SOFTM0, /**< SMCTRLL SOFTM0 Signal. */ + prsSignalSMCTRLL_SOFTM1 = PRS_SMCTRLL_SOFTM1, /**< SMCTRLL SOFTM1 Signal. */ + prsSignalSMCTRLL_SOFTM2 = PRS_SMCTRLL_SOFTM2, /**< SMCTRLL SOFTM2 Signal. */ + prsSignalSMCTRLL_SOFTM3 = PRS_SMCTRLL_SOFTM3, /**< SMCTRLL SOFTM3 Signal. */ + prsSignalSMCTRLL_SOFTM4 = PRS_SMCTRLL_SOFTM4, /**< SMCTRLL SOFTM4 Signal. */ + prsSignalSMCTRLL_SOFTM5 = PRS_SMCTRLL_SOFTM5, /**< SMCTRLL SOFTM5 Signal. */ + prsSignalSMCTRLL_SOFTM6 = PRS_SMCTRLL_SOFTM6, /**< SMCTRLL SOFTM6 Signal. */ + prsSignalSMCTRLL_SOFTM7 = PRS_SMCTRLL_SOFTM7, /**< SMCTRLL SOFTM7 Signal. */ + prsSignalSMCTRL_SOFTM8 = PRS_SMCTRL_SOFTM8, /**< SMCTRL SOFTM8 Signal. */ + prsSignalSMCTRL_SOFTM9 = PRS_SMCTRL_SOFTM9, /**< SMCTRL SOFTM9 Signal. */ + prsSignalSMCTRL_SOFTM10 = PRS_SMCTRL_SOFTM10, /**< SMCTRL SOFTM10 Signal. */ + prsSignalSMCTRL_SOFTM11 = PRS_SMCTRL_SOFTM11, /**< SMCTRL SOFTM11 Signal. */ +#endif +#if defined(PRS_SEHFRCO_COREEN) + prsSignalSEHFRCO_COREEN = PRS_SEHFRCO_COREEN, /**< SEHFRCO COREEN Signal. */ + prsSignalSEHFRCO_STATE0 = PRS_SEHFRCO_STATE0, /**< SEHFRCO STATE0 Signal. */ + prsSignalSEHFRCO_STATE1 = PRS_SEHFRCO_STATE1, /**< SEHFRCO STATE1 Signal. */ + prsSignalSEHFRCO_STATE2 = PRS_SEHFRCO_STATE2, /**< SEHFRCO STATE2 Signal. */ +#endif +#if defined(PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY) + prsSignalSEATAMPDET_SEATAMPDETSUPTPDELAY = PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY, /**< SEATAMPDET SEATAMPDETSUPTPDELAY Signal. */ +#endif +#if defined(PRS_DCDC_MONO70NSANA) + prsSignalDCDC_MONO70NSANA = PRS_DCDC_MONO70NSANA, /** DCDC Pulses for Coulomb Counter Calibration Signal. */ +#endif +#if defined(PRS_LFRCO_CALMEAS) + prsSignalLFRCO_CALMEAS = PRS_LFRCO_CALMEAS, /** LFRCO Calibration Measure Signal. */ + prsSignalLFRCO_SDM = PRS_LFRCO_SDM, /** LFRCO Sigma Delta Modulator output Signal. */ + prsSignalLFRCO_TCMEAS = PRS_LFRCO_TCMEAS, /** LFRCO Temperature Check Measure Signal. */ +#endif +} PRS_Signal_t; + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Consumers. */ +typedef enum { + prsConsumerNone = 0x000, /**< No PRS consumer */ + prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ + prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ +#if defined(IADC_PRESENT) + prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ + prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ +#endif + prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ + prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ +#if defined(LETIMER0) + prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_CLEAR), /**< LETIMER0 clear consumer. */ + prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_START), /**< LETIMER0 start consumer. */ + prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_STOP), /**< LETIMER0 stop consumer. */ +#endif + prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ + prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ + prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ + prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ + prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ + prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ + prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ + prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ + prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ + prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ + prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ + prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ +#if defined(TIMER4) + prsConsumerTIMER4_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC0), /**< TIMER4 capture/compare channel 0 consumer. */ + prsConsumerTIMER4_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC1), /**< TIMER4 capture/compare channel 1 consumer. */ + prsConsumerTIMER4_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC2), /**< TIMER4 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER5) + prsConsumerTIMER5_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC0), /**< TIMER5 capture/compare channel 0 consumer. */ + prsConsumerTIMER5_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC1), /**< TIMER5 capture/compare channel 1 consumer. */ + prsConsumerTIMER5_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC2), /**< TIMER5 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER6) + prsConsumerTIMER6_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC0), /**< TIMER6 capture/compare channel 0 consumer. */ + prsConsumerTIMER6_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC1), /**< TIMER6 capture/compare channel 1 consumer. */ + prsConsumerTIMER6_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC2), /**< TIMER6 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER7) + prsConsumerTIMER7_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC0), /**< TIMER7 capture/compare channel 0 consumer. */ + prsConsumerTIMER7_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC1), /**< TIMER7 capture/compare channel 1 consumer. */ + prsConsumerTIMER7_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC2), /**< TIMER7 capture/compare channel 2 consumer. */ +#endif +#if defined(USART0) + prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ + prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ + prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 RX consumer. */ + prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ +#endif +#if defined(USART1) + prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ + prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ + prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 TX consumer. */ + prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ +#endif +#if defined(USART2) + prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ + prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ + prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 RX consumer. */ + prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ +#endif +#if defined(EUSART0) + prsConsumerEUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART0_CLK), /**< EUSART0 clk consumer. */ + prsConsumerEUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART0_RX), /**< EUSART0 RX consumer. */ + prsConsumerEUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART0_TRIGGER), /**< EUSART0 trigger consumer. */ +#endif +#if defined(EUSART1) + prsConsumerEUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART1_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART1_RX), /**< EUSART1 RX consumer. */ + prsConsumerEUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART1_TRIGGER), /**< EUSART1 trigger consumer. */ +#endif +#if defined(EUSART2) + prsConsumerEUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART2_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART2_RX), /**< EUSART2 RX consumer. */ + prsConsumerEUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART2_TRIGGER), /**< EUSART2 trigger consumer. */ +#endif +#if defined(EUSART3) + prsConsumerEUSART3_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART3_RX), /**< EUSART3 RX consumer. */ + prsConsumerEUSART3_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART3_TRIGGER), /**< EUSART3 trigger consumer. */ +#endif +#if defined(EUSART4) + prsConsumerEUSART4_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART4_RX), /**< EUSART4 RX consumer. */ + prsConsumerEUSART4_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART4_TRIGGER), /**< EUSART4 trigger consumer. */ +#endif +#if defined(EUART0) + prsConsumerEUART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUART0_RX), /**< EUART0 RX consumer. */ + prsConsumerEUART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUART0_TRIGGER), /**< EUART0 TRIGGER Consumer. */ +#endif + prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ + prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ +#if defined(WDOG1) + prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ + prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ +#endif +#if defined(PCNT0) + prsConsumerPCNT0_IN0 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S0IN), /**< PCNT0 input 0 consumer. */ + prsConsumerPCNT0_IN1 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S1IN), /**< PCNT0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_RTCC_CC2_MASK) + prsConsumerRTCC_CC0 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC0), /**< RTCC capture/compare channel 0 consumer. */ + prsConsumerRTCC_CC1 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC1), /**< RTCC capture/compare channel 1 consumer. */ + prsConsumerRTCC_CC2 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC2), /**< RTCC capture/compare channel 2 consumer. */ +#endif +#if defined(SYSRTC0) + prsConsumerSYSRTC0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN0), /**< SYSRTC0 input 0 consumer. */ + prsConsumerSYSRTC0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN1), /**< SYSRTC0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_HFXO0_OSCREQ_MASK) + prsConsumerHFXO0_OSCREQ = offsetof(PRS_TypeDef, CONSUMER_HFXO0_OSCREQ), /**< OSCREQ consumer. */ + prsConsumerHFXO0_TIMEOUT = offsetof(PRS_TypeDef, CONSUMER_HFXO0_TIMEOUT), /**< HFXO0_TIMEOUT consumer. */ +#endif +#if defined(LESENSE) + prsConsumerLESENSE_START = offsetof(PRS_TypeDef, CONSUMER_LESENSE_START), /**< LESENSE_START consumer. */ +#endif +#if defined(VDAC0) + prsConsumerVDAC0_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH0), /**< VDAC0 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH1), /**< VDAC0 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH0), /**< VDAC0 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH1), /**< VDAC0 SYNC TRIGER CH1 consumer. */ +#endif +#if defined(VDAC1) + prsConsumerVDAC1_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH0), /**< VDAC1 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH1), /**< VDAC1 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH0), /**< VDAC1 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH1), /**< VDAC1 SYNC TRIGER CH1 consumer. */ +#endif +} PRS_Consumer_t; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set level control bit for one or more channels. + * + * @details + * The level value for a channel is XORed with both the pulse possibly issued + * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Note that software level control is only available for asynchronous + * channels on Series 2 devices. + * @endcond + * + * @param[in] level + * Level to use for channels indicated by @p mask. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. + * + * @param[in] mask + * Mask indicating which channels to set level for. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) +{ +#if defined(_PRS_SWLEVEL_MASK) + PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); +#else + PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); +#endif +} + +/***************************************************************************//** + * @brief + * Get level control bit for all channels. + * + * @return + * The current software level configuration. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_LevelGet(void) +{ +#if defined(_PRS_SWLEVEL_MASK) + return PRS->SWLEVEL; +#else + return PRS->ASYNC_SWLEVEL; +#endif +} + +#if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) +/***************************************************************************//** + * @brief + * Get the PRS channel values for all channels. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output values for all channels as a bitset. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) +{ +#if defined(_PRS_ASYNC_PEEK_MASK) + if (type == prsTypeAsync) { + return PRS->ASYNC_PEEK; + } else { + return PRS->SYNC_PEEK; + } +#else + (void) type; + return PRS->PEEK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the PRS channel value for a single channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output value. This is either 0 or 1. + ******************************************************************************/ +__STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) +{ + return (0UL != ((PRS_Values(type) >> ch) & 0x1U)); +} +#endif + +/***************************************************************************//** + * @brief + * Trigger a high pulse (one HFPERCLK) for one or more channels. + * + * @details + * Setting a bit for a channel causes the bit in the register to remain high + * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit + * in PRS SWLEVEL register and the PRS input signal selected for the + * channel(s). + * + * @param[in] channels + * Logical ORed combination of channels to trigger a pulse for. Use + * PRS_SWPULSE_CHnPULSE defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) +{ +#if defined(_PRS_SWPULSE_MASK) + PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; +#else + PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the PRS channel level for one asynchronous PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] level + * true to set the level high (1) and false to set the level low (0). + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) +{ + PRS_LevelSet((uint32_t) level << ch, 0x1UL << ch); +} + +/***************************************************************************//** + * @brief + * Trigger a pulse on one PRS channel. + * + * @param[in] ch + * PRS channel number. + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) +{ + PRS_PulseTrigger(0x1UL << ch); +} + +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge); + +#if defined(PRS_ASYNC_SUPPORTED) +void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal); +#endif +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location); +#endif + +int PRS_GetFreeChannel(PRS_ChType_t type); +void PRS_Reset(void); +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); +#if defined(_SILICON_LABS_32B_SERIES_2) +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource); +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal); +void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); +void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); +void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); +#endif + +/** @} (end addtogroup prs) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ +#endif /* EM_PRS_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h index 1fc99a0..35243a0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h @@ -1,167 +1,167 @@ -/***************************************************************************//** - * @file - * @brief RAM code support. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_RAMFUNC_H -#define EM_RAMFUNC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* *INDENT-OFF* */ -/***************************************************************************//** - * @addtogroup ramfunc RAMFUNC - RAM Function Support - * @brief RAM code support - * @details - * Provides support for executing code from RAM. - * Provides a unified method to manage RAM code across all supported tools. - * @{ - - @note - Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common). - - @note - Functions executing from RAM should not be declared as static. - - @warning - Standard library facilities are available to the tool with GCC in hosted - mode (default), regardless of the section attribute. Calls to standard - libraries placed in the default section may therefore occur. To disable - hosted mode, add '-ffreestanding' to the build command line. This is the - only way to guarantee no calls to standard libraries with GCC. - Read more at www.gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html - - @warning - Keil/ARM uVision users must add a section named "ram_code" in their linker - scatter file. This section must be in RAM memory. Look in the MCU SDK for - example scatter files (ram_code.sct). - - @n @section ramfunc_usage Usage - - In your .h file: - @verbatim - #include "em_ramfunc.h" - - SL_RAMFUNC_DECLARATOR - void MyPrint(const char* string); - @endverbatim - - Issues have been observed with ARM GCC when there is no declarator. It is - recommended to have a declarator also for internal functions but move the - declarator to the .c file. - - In your .c file: - @verbatim - #include "em_ramfunc.h" - - SL_RAMFUNC_DEFINITION_BEGIN - void MyPrint(const char* string) - { - ... - } - SL_RAMFUNC_DEFINITION_END - @endverbatim - - ******************************************************************************/ -/* *INDENT-ON* */ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -/** - * @brief - * This define is not present by default. By compiling with define - * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros - * will be placed in default code space (Flash) instead. - * - * @note - * This define is not present by default. - */ -#if defined(DOXY_DOC_ONLY) -#define SL_RAMFUNC_DISABLE -#endif - -#if defined(SL_RAMFUNC_DISABLE) -/** @brief Compiler ported function declarator for RAM code. */ -#define SL_RAMFUNC_DECLARATOR - -/** @brief Compiler ported function definition begin marker for RAM code. */ -#define SL_RAMFUNC_DEFINITION_BEGIN - -/** @brief Compiler ported function definition end marker for RAM code. */ -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__CC_ARM) -/* MDK-ARM compiler */ -#define SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") -#define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") - -#elif defined(__ICCARM__) -/* IAR Embedded Workbench */ -#define SL_RAMFUNC_DECLARATOR __ramfunc -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) && (defined(__CROSSWORKS_ARM) || defined(__SES_ARM)) -/* Rowley Crossworks and Segger Embedded Studio */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".fast"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32) -/* Zephyr environment */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) -/* Simplicity Studio, Atollic and Vanilla armgcc */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated macro names */ -#define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR -#define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN -#define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END -/** @endcond */ - -/** @} (end addtogroup ramfunc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_RAMFUNC_H */ +/***************************************************************************//** + * @file + * @brief RAM code support. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RAMFUNC_H +#define EM_RAMFUNC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +/***************************************************************************//** + * @addtogroup ramfunc RAMFUNC - RAM Function Support + * @brief RAM code support + * @details + * Provides support for executing code from RAM. + * Provides a unified method to manage RAM code across all supported tools. + * @{ + + @note + Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common). + + @note + Functions executing from RAM should not be declared as static. + + @warning + Standard library facilities are available to the tool with GCC in hosted + mode (default), regardless of the section attribute. Calls to standard + libraries placed in the default section may therefore occur. To disable + hosted mode, add '-ffreestanding' to the build command line. This is the + only way to guarantee no calls to standard libraries with GCC. + Read more at www.gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html + + @warning + Keil/ARM uVision users must add a section named "ram_code" in their linker + scatter file. This section must be in RAM memory. Look in the MCU SDK for + example scatter files (ram_code.sct). + + @n @section ramfunc_usage Usage + + In your .h file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DECLARATOR + void MyPrint(const char* string); + @endverbatim + + Issues have been observed with ARM GCC when there is no declarator. It is + recommended to have a declarator also for internal functions but move the + declarator to the .c file. + + In your .c file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DEFINITION_BEGIN + void MyPrint(const char* string) + { + ... + } + SL_RAMFUNC_DEFINITION_END + @endverbatim + + ******************************************************************************/ +/* *INDENT-ON* */ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * This define is not present by default. By compiling with define + * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros + * will be placed in default code space (Flash) instead. + * + * @note + * This define is not present by default. + */ +#if defined(DOXY_DOC_ONLY) +#define SL_RAMFUNC_DISABLE +#endif + +#if defined(SL_RAMFUNC_DISABLE) +/** @brief Compiler ported function declarator for RAM code. */ +#define SL_RAMFUNC_DECLARATOR + +/** @brief Compiler ported function definition begin marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_BEGIN + +/** @brief Compiler ported function definition end marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__CC_ARM) +/* MDK-ARM compiler */ +#define SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") +#define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") + +#elif defined(__ICCARM__) +/* IAR Embedded Workbench */ +#define SL_RAMFUNC_DECLARATOR __ramfunc +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && (defined(__CROSSWORKS_ARM) || defined(__SES_ARM)) +/* Rowley Crossworks and Segger Embedded Studio */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".fast"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32) +/* Zephyr environment */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) +/* Simplicity Studio, Atollic and Vanilla armgcc */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated macro names */ +#define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +/** @endcond */ + +/** @} (end addtogroup ramfunc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_RAMFUNC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h index 81304c0..d1b1785 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h @@ -1,178 +1,178 @@ -/***************************************************************************//** - * @file - * @brief Reset Management Unit (RMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_RMU_H -#define EM_RMU_H - -#include "em_device.h" -#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) -#include "sl_assert.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup rmu - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** RMU reset modes. */ -typedef enum { -#if defined(_RMU_CTRL_PINRMODE_MASK) - rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, /**< Reset mode disabled. */ - rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, /**< Reset mode limited. */ - rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, /**< Reset mode extended. */ - rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, /**< Reset mode full. */ -#elif defined(_EMU_RSTCTRL_MASK) - rmuResetModeDisabled = 0, /**< Reset mode disabled. */ - rmuResetModeEnabled = 1, /**< Reset mode enabled. */ -#else - rmuResetModeClear = 0, /**< Reset mode clear. */ - rmuResetModeSet = 1, /**< Reset mode set. */ -#endif -} RMU_ResetMode_TypeDef; - -/** RMU controlled peripheral reset control and reset source control. */ -typedef enum { -#if defined(RMU_CTRL_BURSTEN) - rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ -#endif -#if defined(RMU_CTRL_LOCKUPRDIS) - rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ -#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) - rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ -#endif -#if defined(_RMU_CTRL_WDOGRMODE_MASK) - rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ -#endif -#if defined(_RMU_CTRL_LOCKUPRMODE_MASK) - rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ -#endif -#if defined(_RMU_CTRL_SYSRMODE_MASK) - rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ -#endif -#if defined(_RMU_CTRL_PINRMODE_MASK) - rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ -#endif - -#if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) - rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ -#endif -#if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) - rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ -#endif -#if defined(_EMU_RSTCTRL_SYSRMODE_MASK) - rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ -#endif -#if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) - rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ -#endif -#if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) - rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) - rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD1BODRMODE_MASK) - rmuResetIOVDD1 = _EMU_RSTCTRL_IOVDD1BODRMODE_MASK, /**< IOVDD1 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD2BODRMODE_MASK) - rmuResetIOVDD2 = _EMU_RSTCTRL_IOVDD2BODRMODE_MASK, /**< IOVDD2 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) - rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_SESYSRMODE_MASK) - rmuResetSESys = _EMU_RSTCTRL_SESYSRMODE_MASK, /**< M0+ (SE) system reset select */ -#endif -#if defined(_EMU_RSTCTRL_SELOCKUPRMODE_MASK) - rmuResetSELockup = _EMU_RSTCTRL_SELOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ -#endif -#if defined(_EMU_RSTCTRL_DCIRMODE_MASK) - rmuResetDCI = _EMU_RSTCTRL_DCIRMODE_MASK, /**< DCI reset select */ -#endif -} RMU_Reset_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/** RMU_LockupResetDisable kept for backwards compatibility. */ -#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) - -void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); -void RMU_ResetCauseClear(void); -uint32_t RMU_ResetCauseGet(void); - -#if defined(_RMU_CTRL_RESETSTATE_MASK) -/***************************************************************************//** - * @brief - * Set user reset state. Reset only by a Power-on-reset and a pin reset. - * - * @param[in] userState User state to set - ******************************************************************************/ -__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) -{ - EFM_ASSERT(!(userState - & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); - RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) - | (userState << _RMU_CTRL_RESETSTATE_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get user reset state. Reset only by a Power-on-reset and a pin reset. - * - * @return - * Reset surviving user state. - ******************************************************************************/ -__STATIC_INLINE uint32_t RMU_UserResetStateGet(void) -{ - uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) - >> _RMU_CTRL_RESETSTATE_SHIFT; - return userState; -} -#endif - -/** @} (end addtogroup rmu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ -#endif /* EM_RMU_H */ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RMU_H +#define EM_RMU_H + +#include "em_device.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) +#include "sl_assert.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup rmu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** RMU reset modes. */ +typedef enum { +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, /**< Reset mode disabled. */ + rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, /**< Reset mode limited. */ + rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, /**< Reset mode extended. */ + rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, /**< Reset mode full. */ +#elif defined(_EMU_RSTCTRL_MASK) + rmuResetModeDisabled = 0, /**< Reset mode disabled. */ + rmuResetModeEnabled = 1, /**< Reset mode enabled. */ +#else + rmuResetModeClear = 0, /**< Reset mode clear. */ + rmuResetModeSet = 1, /**< Reset mode set. */ +#endif +} RMU_ResetMode_TypeDef; + +/** RMU controlled peripheral reset control and reset source control. */ +typedef enum { +#if defined(RMU_CTRL_BURSTEN) + rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ +#endif +#if defined(RMU_CTRL_LOCKUPRDIS) + rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ +#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_WDOGRMODE_MASK) + rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ +#endif +#if defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_SYSRMODE_MASK) + rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ +#endif +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ +#endif + +#if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) + rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ +#endif +#if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) + rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ +#endif +#if defined(_EMU_RSTCTRL_SYSRMODE_MASK) + rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ +#endif +#if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ +#endif +#if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) + rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) + rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD1BODRMODE_MASK) + rmuResetIOVDD1 = _EMU_RSTCTRL_IOVDD1BODRMODE_MASK, /**< IOVDD1 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD2BODRMODE_MASK) + rmuResetIOVDD2 = _EMU_RSTCTRL_IOVDD2BODRMODE_MASK, /**< IOVDD2 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) + rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_SESYSRMODE_MASK) + rmuResetSESys = _EMU_RSTCTRL_SESYSRMODE_MASK, /**< M0+ (SE) system reset select */ +#endif +#if defined(_EMU_RSTCTRL_SELOCKUPRMODE_MASK) + rmuResetSELockup = _EMU_RSTCTRL_SELOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ +#endif +#if defined(_EMU_RSTCTRL_DCIRMODE_MASK) + rmuResetDCI = _EMU_RSTCTRL_DCIRMODE_MASK, /**< DCI reset select */ +#endif +} RMU_Reset_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/** RMU_LockupResetDisable kept for backwards compatibility. */ +#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) + +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); +void RMU_ResetCauseClear(void); +uint32_t RMU_ResetCauseGet(void); + +#if defined(_RMU_CTRL_RESETSTATE_MASK) +/***************************************************************************//** + * @brief + * Set user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @param[in] userState User state to set + ******************************************************************************/ +__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) +{ + EFM_ASSERT(!(userState + & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); + RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) + | (userState << _RMU_CTRL_RESETSTATE_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @return + * Reset surviving user state. + ******************************************************************************/ +__STATIC_INLINE uint32_t RMU_UserResetStateGet(void) +{ + uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) + >> _RMU_CTRL_RESETSTATE_SHIFT; + return userState; +} +#endif + +/** @} (end addtogroup rmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ +#endif /* EM_RMU_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h index 6847770..c1e1024 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h @@ -1,640 +1,640 @@ -/***************************************************************************//** - * @file - * @brief Secure Element API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_SE_H -#define EM_SE_H - -#if defined(__linux__) - -#define SLI_EM_SE_HOST - -#else - -#include "em_device.h" - -#endif // __linux__ - -#include "sl_common.h" - -#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup se SE - Secure Element - * - * @brief Secure Element peripheral API - * - * @details - * Abstraction of the Secure Element's mailbox interface. - * - * For series 2 devices with a part number that is xG23 or higher, the - * following step is necessary for basic operation: - * - * Clock enable: - * @code - CMU_ClockEnable(cmuClock_SEMAILBOX, true);@endcode - * - * @note The high-level SE API has been moved to the SE manager, and the - * implementation in em_se should not be used. - * - * @note Using the SE's mailbox is not thread-safe in EMLIB, and accessing the - * SE's mailbox both in regular and IRQ context is not safe. SE operations - * should be performed using the SE manager if possible. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -#if defined(CRYPTOACC_PRESENT) -/** Root Code Mailbox is invalid. */ -#define SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL -/** Root Code Mailbox magic word */ -#define SE_RESPONSE_MAILBOX_VALID 0xE5ECC0DEUL -#endif - -/** Response status codes for the Secure Element */ -#define SE_RESPONSE_MASK 0x000F0000UL -/** Command executed successfully or signature was successfully validated. */ -#define SE_RESPONSE_OK 0x00000000UL - -/** Maximum amount of parameters supported by the hardware FIFO */ -#define SE_FIFO_MAX_PARAMETERS 13U - -/** Stop datatransfer */ -#define SE_DATATRANSFER_STOP 0x00000001UL -/** Discard datatransfer */ -#define SE_DATATRANSFER_DISCARD 0x40000000UL -/** Realign datatransfer */ -#define SE_DATATRANSFER_REALIGN 0x20000000UL -/** Datatransfer Const Address*/ -#define SE_DATATRANSFER_CONSTADDRESS 0x10000000UL -/** Stop Length Mask */ -#define SE_DATATRANSFER_LENGTH_MASK 0x0FFFFFFFUL - -/** Maximum amount of parameters for largest command in defined command set */ -#ifndef SE_MAX_PARAMETERS -#define SE_MAX_PARAMETERS 4U -#endif - -/* Sanity-check defines */ -#if SE_MAX_PARAMETERS > SE_FIFO_MAX_PARAMETERS -#error "Trying to configure more parameters than supported by the hardware" -#endif - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/** - * SE DMA transfer descriptor. Can be linked to each other to provide - * scatter-gather behavior. - */ -typedef struct { - volatile void* volatile data; /**< Data pointer */ - void* volatile next; /**< Next descriptor */ - volatile uint32_t length; /**< Length */ -} SE_DataTransfer_t; - -/** Default initialization of data transfer struct */ -#define SE_DATATRANSFER_DEFAULT(address, length) \ - { \ - (void*)(address), /* Pointer to data block */ \ - (void*)SE_DATATRANSFER_STOP, /* This is the last block by default */ \ - (length) | SE_DATATRANSFER_REALIGN /* Add size, use realign by default */ \ - } - -/** - * SE Command structure to which all commands to the SE must adhere. - */ -typedef struct { - uint32_t command; /**< SE Command */ - SE_DataTransfer_t* data_in; /**< Input data */ - SE_DataTransfer_t* data_out; /**< Output data */ - uint32_t parameters[SE_MAX_PARAMETERS];/**< Parameters */ - size_t num_parameters; /**< Number of parameters */ -} SE_Command_t; - -/** Default initialization of command struct */ -#define SE_COMMAND_DEFAULT(command) \ - { \ - (command), /* Given command */ \ - NULL, /* No data in */ \ - NULL, /* No data out */ \ - { 0, 0, 0, 0 }, /* No parameters */ \ - 0 /* No parameters */ \ - } - -/** Possible responses to a command */ -typedef uint32_t SE_Response_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void SE_addDataInput(SE_Command_t *command, - SE_DataTransfer_t *data); - -void SE_addDataOutput(SE_Command_t *command, - SE_DataTransfer_t *data); - -void SE_addParameter(SE_Command_t *command, uint32_t parameter); - -#if !defined(SLI_EM_SE_HOST) -void SE_executeCommand(SE_Command_t *command); -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(CRYPTOACC_PRESENT) -SE_Response_t SE_getVersion(uint32_t *version); -SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus); -SE_Response_t SE_getOTPVersion(uint32_t *otpVersion); -SE_Response_t SE_ackCommand(SE_Command_t *command); -#endif // #if defined(CRYPTOACC_PRESENT) - -// Utilities -#if defined(SEMAILBOX_PRESENT) -__STATIC_INLINE bool SE_isCommandCompleted(void); -__STATIC_INLINE SE_Response_t SE_readCommandResponse(void); -#elif defined(CRYPTOACC_PRESENT) -bool SE_isCommandCompleted(void); -uint32_t SE_readExecutedCommand(void); -SE_Response_t SE_readCommandResponse(void); -#endif // #if defined(SEMAILBOX_PRESENT) - -#if !defined(SLI_EM_SE_HOST) -__STATIC_INLINE void SE_waitCommandCompletion(void); -__STATIC_INLINE void SE_disableInterrupt(uint32_t flags); -__STATIC_INLINE void SE_enableInterrupt(uint32_t flags); -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Check whether the running command has completed. - * - * @details - * This function polls the SE-to-host mailbox interrupt flag. - * - * @return True if a command has completed and the result is available - ******************************************************************************/ -__STATIC_INLINE bool SE_isCommandCompleted(void) -{ - return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT); -} -#endif // #if defined(SEMAILBOX_PRESENT) - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Read the status of the previously executed command. - * - * @details - * This function reads the status of the previously executed command. - * - * @note - * The command response needs to be read for every executed command, and can - * only be read once per executed command (FIFO behavior). - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully or a signature - * was successfully verified. - ******************************************************************************/ -__STATIC_INLINE SE_Response_t SE_readCommandResponse(void) -{ - SE_waitCommandCompletion(); - return (SE_Response_t)(SEMAILBOX_HOST->RX_HEADER & SE_RESPONSE_MASK); -} -#endif // #if defined(SEMAILBOX_PRESENT) - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * Wait for completion of the current command. - * - * @details - * This function "busy"-waits until the execution of the ongoing instruction - * has completed. - ******************************************************************************/ -__STATIC_INLINE void SE_waitCommandCompletion(void) -{ - /* Wait for completion */ - while (!SE_isCommandCompleted()) { - } -} - -/***************************************************************************//** - * @brief - * Disable one or more SE interrupts. - * - * @param[in] flags - * SE interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the Secure Element module - * (SE_CONFIGURATION_(TX/RX)INTEN). - ******************************************************************************/ -__STATIC_INLINE void SE_disableInterrupt(uint32_t flags) -{ -#if defined(SEMAILBOX_PRESENT) - SEMAILBOX_HOST->CONFIGURATION &= ~flags; -#else - (void) flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more SE interrupts. - * - * @param[in] flags - * SE interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the Secure Element module - * (SEMAILBOX_CONFIGURATION_TXINTEN or SEMAILBOX_CONFIGURATION_RXINTEN). - ******************************************************************************/ -__STATIC_INLINE void SE_enableInterrupt(uint32_t flags) -{ -#if defined(SEMAILBOX_PRESENT) - SEMAILBOX_HOST->CONFIGURATION |= flags; -#else - (void) flags; -#endif -} - -#endif // #if !defined(SLI_EM_SE_HOST) - -/******************************************************************************* - ***************************** DEPRECATED ********************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup se_deprecated Deprecated Functions - * @brief Deprecated Functions - * - * @deprecated - * The following functions have been deprecated and will be removed in a - * future version of EMLIB. All high-level functionality have been moved to - * the SE manager. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -#if !defined(SLI_EM_SE_HOST) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(SEMAILBOX_PRESENT) -/* Command words for the Security Engine. */ -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_WRAP_KEY 0x01000000UL -#define SE_COMMAND_UNWRAP_KEY 0x01020000UL -#define SE_COMMAND_TRANSFER_KEY 0x01060000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_CREATE_KEY 0x02000000UL -#define SE_COMMAND_READPUB_KEY 0x02010000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_DERIVE_KEY_PBKDF2 0x02020002UL -#define SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_HASH 0x03000000UL -#define SE_COMMAND_HASHUPDATE 0x03010000UL -#define SE_COMMAND_HMAC 0x03020000UL - -#define SE_COMMAND_AES_ENCRYPT 0x04000000UL -#define SE_COMMAND_AES_DECRYPT 0x04010000UL -#define SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL -#define SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL -#define SE_COMMAND_AES_CMAC 0x04040000UL -#define SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL -#define SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL - -#define SE_COMMAND_SIGNATURE_SIGN 0x06000000UL -#define SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_EDDSA_SIGN 0x06020000UL -#define SE_COMMAND_EDDSA_VERIFY 0x06030000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL -#define SE_COMMAND_READ_CLOCK 0x07020000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_ATTEST_CERTIFY 0x0A000000UL -#define SE_COMMAND_ATTEST_TIME 0x0A010000UL -#define SE_COMMAND_ATTEST_PUBKEY 0x0A020000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL -#define SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL -#define SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL -#define SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL -#define SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_AEAD_ENCRYPT 0x0C000000UL -#define SE_COMMAND_AEAD_DECRYPT 0x0C010000UL -#define SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL -#define SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL -#define SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_DH 0x0E000000UL - -#endif // #if defined(SEMAILBOX_PRESENT) - -#define SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL -#define SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL -#define SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL -#define SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL -#define SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL -#define SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL - -#if defined(SEMAILBOX_PRESENT) - -#define SE_COMMAND_STATUS_SE_VERSION 0x43080000UL -#define SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL - -#define SE_COMMAND_WRITE_USER_DATA 0x43090000UL -#define SE_COMMAND_ERASE_USER_DATA 0x430A0000UL - -#define SE_COMMAND_DBG_LOCK_APPLY 0x430C0000 -#define SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000 -#define SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000 -#define SE_COMMAND_DEVICE_ERASE 0x430F0000 -#define SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000 -#define SE_COMMAND_DBG_LOCK_STATUS 0x43110000 - -#define SE_COMMAND_PROTECTED_REGISTER 0x43210000 - -#define SE_COMMAND_GET_CHALLENGE 0xFD000000UL -#define SE_COMMAND_ROLL_CHALLENGE 0xFD000100UL -#define SE_COMMAND_OPEN_DEBUG 0xFD010001UL -#define SE_COMMAND_DISABLE_TAMPER 0xFD020001UL - -#define SE_COMMAND_READ_SERIAL 0xFE000000UL -#define SE_COMMAND_GET_STATUS 0xFE010000UL -#define SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL - -#define SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL -#define SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL - -#define SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL -#define SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL -#endif /* SEMAILBOX_PRESENT */ - -#if defined(SEMAILBOX_PRESENT) -/* Command options for the Secure Element commands. */ -/** Use MD5 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_MD5 0x00000100UL -/** Use SHA1 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL -/** Use SHA224 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL -/** Use SHA256 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -/** Use SHA384 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL -/** Use SHA512 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -/** Execute algorithm in ECB mode */ -#define SE_COMMAND_OPTION_MODE_ECB 0x00000100UL -/** Execute algorithm in CBC mode */ -#define SE_COMMAND_OPTION_MODE_CBC 0x00000200UL -/** Execute algorithm in CTR mode */ -#define SE_COMMAND_OPTION_MODE_CTR 0x00000300UL -/** Execute algorithm in CFB mode */ -#define SE_COMMAND_OPTION_MODE_CFB 0x00000400UL -/** Execute algorithm in OFB mode */ -#define SE_COMMAND_OPTION_MODE_OFB 0x00000500UL -/** Execute algorithm in XTS mode */ -#define SE_COMMAND_OPTION_MODE_XTS 0x00000800UL - -#define SE_COMMAND_OPTION_CERT_DEVICE 0x00000100UL -#define SE_COMMAND_OPTION_CERT_BATCH 0x00000200UL -#define SE_COMMAND_OPTION_CERT_FACTORY 0x00000300UL - -/** Pubkey type */ -#define SE_KEY_TYPE_ROOT 0x00000300UL - -/** Run the whole algorithm, all data present */ -#define SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL -/** Start the algorithm, but get a context to later add more data */ -#define SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL -/** End the algorithm, get the result */ -#define SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL -/** Add more data input to the algorithm. Need to supply previous context, - * and get a context back */ -#define SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL - -/** Padding options for signature functionality. */ -#define SE_COMMAND_OPTION_PADDING_NONE 0x00000000UL -#define SE_COMMAND_OPTION_PADDING_EMSA_PKCS 0x00000003UL -#define SE_COMMAND_OPTION_PADDING_PSS 0x00000004UL - -/* Special parameters for the Secure Element commands. */ -#define SE_COMMAND_OPTION_READ 0x00000000UL -#define SE_COMMAND_OPTION_WRITE 0x00000100UL - -/** Magic parameter for deleting user data */ -#define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL - -#endif /* SEMAILBOX_PRESENT */ - -/** Pubkey types */ -#define SE_KEY_TYPE_BOOT 0x00000100UL -#define SE_KEY_TYPE_AUTH 0x00000200UL - -#define SE_COMMAND_INIT_OTP 0xFF000001UL -#define SE_COMMAND_INIT_PUBKEY 0xFF070001UL - -#define SE_COMMAND_READ_PUBKEY 0xFF080001UL - -/** - * Command was not recognized as a valid command, or is not allowed in the - * current context. - */ -#define SE_RESPONSE_INVALID_COMMAND 0x00010000UL -/** - * User did not provide the required credentials to be allowed to execute the - * command. - */ -#define SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL -/** - * Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to - * verify the given signature as being correct. - */ -#define SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL -/** A command started in non-secure mode is trying to access secure memory. */ -#define SE_RESPONSE_BUS_ERROR 0x00040000UL -/** Internal error */ -#define SE_RESPONSE_INTERNAL_ERROR 0x00050000UL -/** An internal error was raised and the command did not execute. */ -#define SE_RESPONSE_CRYPTO_ERROR 0x00060000UL -/** One of the passed parameters is deemed invalid (e.g. out of bounds). */ -#define SE_RESPONSE_INVALID_PARAMETER 0x00070000UL -/** Failure while checking the host for secure boot */ -#define SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL -/** Failure during selftest */ -#define SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL -/** Feature/item not initialized or not present */ -#define SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL -/* Abort status code is given when no operation is attempted. */ -#define SE_RESPONSE_ABORT 0x00FF0000UL - -/** @endcond */ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/** SE OTP initialization struct */ -typedef struct { - /** Enable secure boot for the host. */ - bool enableSecureBoot; - /** Require certificate based secure boot signing. */ - bool verifySecureBootCertificate; - /** Enable anti-rollback for host application upgrades. */ - bool enableAntiRollback; - - /** Set flag to enable locking down all flash pages that cover the - * secure-booted image, except the last page if end of signature is not - * page-aligned. */ - bool secureBootPageLockNarrow; - /** Set flag to enable locking down all flash pages that cover the - * secure-booted image, including the last page if end of signature is not - * page-aligned. */ - bool secureBootPageLockFull; -} SE_OTPInit_t; - -/** SE debug status */ -typedef struct { - /** Whether debug lock is enabled */ - bool debugLockEnabled; - /** Whether device erase is enabled */ - bool deviceEraseEnabled; - /** Whether secure debug is enabled */ - bool secureDebugEnabled; -} SE_DebugStatus_t; - -/** SE status */ -typedef struct { - /** Boot status code / error code (Bits [7:0]). */ - uint32_t bootStatus; - /** SE firmware version. */ - uint32_t seFwVersion; - /** Host firmware version (if available). */ - uint32_t hostFwVersion; - /** Debug lock status. */ - SE_DebugStatus_t debugStatus; - /** Secure boot enabled. */ - bool secureBootEnabled; -} SE_Status_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_initPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) -SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_initPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) SL_DEPRECATED_API_SDK_4_4; - -#if defined(SEMAILBOX_PRESENT) - -// User data commands -SE_Response_t SE_writeUserData(uint32_t offset, - void *data, - uint32_t numBytes) -SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_eraseUserData(void) SL_DEPRECATED_API_SDK_3_0; - -// Initialization commands -SE_Response_t SE_readPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) SL_DEPRECATED_API_SDK_4_4; - -// Debug commands -SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugLockApply(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugSecureEnable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugSecureDisable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_deviceEraseDisable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_deviceErase(void) SL_DEPRECATED_API_SDK_3_0; - -// Device status commands -SE_Response_t SE_getStatus(SE_Status_t *output) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_serialNumber(void *serial) SL_DEPRECATED_API_SDK_3_0; - -#endif // #if defined(SEMAILBOX_PRESENT) -#endif // #if !defined(SLI_EM_SE_HOST) - -/** @} (end addtogroup se_deprecated) */ - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup se) */ - -#endif /* defined(SEMAILBOX_PRESENT) - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) */ - -#endif /* EM_SE_H */ +/***************************************************************************//** + * @file + * @brief Secure Element API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_SE_H +#define EM_SE_H + +#if defined(__linux__) + +#define SLI_EM_SE_HOST + +#else + +#include "em_device.h" + +#endif // __linux__ + +#include "sl_common.h" + +#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup se SE - Secure Element + * + * @brief Secure Element peripheral API + * + * @details + * Abstraction of the Secure Element's mailbox interface. + * + * For series 2 devices with a part number that is xG23 or higher, the + * following step is necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_SEMAILBOX, true);@endcode + * + * @note The high-level SE API has been moved to the SE manager, and the + * implementation in em_se should not be used. + * + * @note Using the SE's mailbox is not thread-safe in EMLIB, and accessing the + * SE's mailbox both in regular and IRQ context is not safe. SE operations + * should be performed using the SE manager if possible. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +#if defined(CRYPTOACC_PRESENT) +/** Root Code Mailbox is invalid. */ +#define SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL +/** Root Code Mailbox magic word */ +#define SE_RESPONSE_MAILBOX_VALID 0xE5ECC0DEUL +#endif + +/** Response status codes for the Secure Element */ +#define SE_RESPONSE_MASK 0x000F0000UL +/** Command executed successfully or signature was successfully validated. */ +#define SE_RESPONSE_OK 0x00000000UL + +/** Maximum amount of parameters supported by the hardware FIFO */ +#define SE_FIFO_MAX_PARAMETERS 13U + +/** Stop datatransfer */ +#define SE_DATATRANSFER_STOP 0x00000001UL +/** Discard datatransfer */ +#define SE_DATATRANSFER_DISCARD 0x40000000UL +/** Realign datatransfer */ +#define SE_DATATRANSFER_REALIGN 0x20000000UL +/** Datatransfer Const Address*/ +#define SE_DATATRANSFER_CONSTADDRESS 0x10000000UL +/** Stop Length Mask */ +#define SE_DATATRANSFER_LENGTH_MASK 0x0FFFFFFFUL + +/** Maximum amount of parameters for largest command in defined command set */ +#ifndef SE_MAX_PARAMETERS +#define SE_MAX_PARAMETERS 4U +#endif + +/* Sanity-check defines */ +#if SE_MAX_PARAMETERS > SE_FIFO_MAX_PARAMETERS +#error "Trying to configure more parameters than supported by the hardware" +#endif + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/** + * SE DMA transfer descriptor. Can be linked to each other to provide + * scatter-gather behavior. + */ +typedef struct { + volatile void* volatile data; /**< Data pointer */ + void* volatile next; /**< Next descriptor */ + volatile uint32_t length; /**< Length */ +} SE_DataTransfer_t; + +/** Default initialization of data transfer struct */ +#define SE_DATATRANSFER_DEFAULT(address, length) \ + { \ + (void*)(address), /* Pointer to data block */ \ + (void*)SE_DATATRANSFER_STOP, /* This is the last block by default */ \ + (length) | SE_DATATRANSFER_REALIGN /* Add size, use realign by default */ \ + } + +/** + * SE Command structure to which all commands to the SE must adhere. + */ +typedef struct { + uint32_t command; /**< SE Command */ + SE_DataTransfer_t* data_in; /**< Input data */ + SE_DataTransfer_t* data_out; /**< Output data */ + uint32_t parameters[SE_MAX_PARAMETERS];/**< Parameters */ + size_t num_parameters; /**< Number of parameters */ +} SE_Command_t; + +/** Default initialization of command struct */ +#define SE_COMMAND_DEFAULT(command) \ + { \ + (command), /* Given command */ \ + NULL, /* No data in */ \ + NULL, /* No data out */ \ + { 0, 0, 0, 0 }, /* No parameters */ \ + 0 /* No parameters */ \ + } + +/** Possible responses to a command */ +typedef uint32_t SE_Response_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void SE_addDataInput(SE_Command_t *command, + SE_DataTransfer_t *data); + +void SE_addDataOutput(SE_Command_t *command, + SE_DataTransfer_t *data); + +void SE_addParameter(SE_Command_t *command, uint32_t parameter); + +#if !defined(SLI_EM_SE_HOST) +void SE_executeCommand(SE_Command_t *command); +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(CRYPTOACC_PRESENT) +SE_Response_t SE_getVersion(uint32_t *version); +SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus); +SE_Response_t SE_getOTPVersion(uint32_t *otpVersion); +SE_Response_t SE_ackCommand(SE_Command_t *command); +#endif // #if defined(CRYPTOACC_PRESENT) + +// Utilities +#if defined(SEMAILBOX_PRESENT) +__STATIC_INLINE bool SE_isCommandCompleted(void); +__STATIC_INLINE SE_Response_t SE_readCommandResponse(void); +#elif defined(CRYPTOACC_PRESENT) +bool SE_isCommandCompleted(void); +uint32_t SE_readExecutedCommand(void); +SE_Response_t SE_readCommandResponse(void); +#endif // #if defined(SEMAILBOX_PRESENT) + +#if !defined(SLI_EM_SE_HOST) +__STATIC_INLINE void SE_waitCommandCompletion(void); +__STATIC_INLINE void SE_disableInterrupt(uint32_t flags); +__STATIC_INLINE void SE_enableInterrupt(uint32_t flags); +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Check whether the running command has completed. + * + * @details + * This function polls the SE-to-host mailbox interrupt flag. + * + * @return True if a command has completed and the result is available + ******************************************************************************/ +__STATIC_INLINE bool SE_isCommandCompleted(void) +{ + return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT); +} +#endif // #if defined(SEMAILBOX_PRESENT) + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Read the status of the previously executed command. + * + * @details + * This function reads the status of the previously executed command. + * + * @note + * The command response needs to be read for every executed command, and can + * only be read once per executed command (FIFO behavior). + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully or a signature + * was successfully verified. + ******************************************************************************/ +__STATIC_INLINE SE_Response_t SE_readCommandResponse(void) +{ + SE_waitCommandCompletion(); + return (SE_Response_t)(SEMAILBOX_HOST->RX_HEADER & SE_RESPONSE_MASK); +} +#endif // #if defined(SEMAILBOX_PRESENT) + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * Wait for completion of the current command. + * + * @details + * This function "busy"-waits until the execution of the ongoing instruction + * has completed. + ******************************************************************************/ +__STATIC_INLINE void SE_waitCommandCompletion(void) +{ + /* Wait for completion */ + while (!SE_isCommandCompleted()) { + } +} + +/***************************************************************************//** + * @brief + * Disable one or more SE interrupts. + * + * @param[in] flags + * SE interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the Secure Element module + * (SE_CONFIGURATION_(TX/RX)INTEN). + ******************************************************************************/ +__STATIC_INLINE void SE_disableInterrupt(uint32_t flags) +{ +#if defined(SEMAILBOX_PRESENT) + SEMAILBOX_HOST->CONFIGURATION &= ~flags; +#else + (void) flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more SE interrupts. + * + * @param[in] flags + * SE interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the Secure Element module + * (SEMAILBOX_CONFIGURATION_TXINTEN or SEMAILBOX_CONFIGURATION_RXINTEN). + ******************************************************************************/ +__STATIC_INLINE void SE_enableInterrupt(uint32_t flags) +{ +#if defined(SEMAILBOX_PRESENT) + SEMAILBOX_HOST->CONFIGURATION |= flags; +#else + (void) flags; +#endif +} + +#endif // #if !defined(SLI_EM_SE_HOST) + +/******************************************************************************* + ***************************** DEPRECATED ********************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup se_deprecated Deprecated Functions + * @brief Deprecated Functions + * + * @deprecated + * The following functions have been deprecated and will be removed in a + * future version of EMLIB. All high-level functionality have been moved to + * the SE manager. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +#if !defined(SLI_EM_SE_HOST) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(SEMAILBOX_PRESENT) +/* Command words for the Security Engine. */ +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_WRAP_KEY 0x01000000UL +#define SE_COMMAND_UNWRAP_KEY 0x01020000UL +#define SE_COMMAND_TRANSFER_KEY 0x01060000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_CREATE_KEY 0x02000000UL +#define SE_COMMAND_READPUB_KEY 0x02010000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_DERIVE_KEY_PBKDF2 0x02020002UL +#define SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_HASH 0x03000000UL +#define SE_COMMAND_HASHUPDATE 0x03010000UL +#define SE_COMMAND_HMAC 0x03020000UL + +#define SE_COMMAND_AES_ENCRYPT 0x04000000UL +#define SE_COMMAND_AES_DECRYPT 0x04010000UL +#define SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL +#define SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL +#define SE_COMMAND_AES_CMAC 0x04040000UL +#define SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL +#define SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL + +#define SE_COMMAND_SIGNATURE_SIGN 0x06000000UL +#define SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_EDDSA_SIGN 0x06020000UL +#define SE_COMMAND_EDDSA_VERIFY 0x06030000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL +#define SE_COMMAND_READ_CLOCK 0x07020000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_ATTEST_CERTIFY 0x0A000000UL +#define SE_COMMAND_ATTEST_TIME 0x0A010000UL +#define SE_COMMAND_ATTEST_PUBKEY 0x0A020000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL +#define SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL +#define SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL +#define SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL +#define SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_AEAD_ENCRYPT 0x0C000000UL +#define SE_COMMAND_AEAD_DECRYPT 0x0C010000UL +#define SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL +#define SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL +#define SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_DH 0x0E000000UL + +#endif // #if defined(SEMAILBOX_PRESENT) + +#define SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL +#define SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL +#define SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL +#define SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL +#define SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL +#define SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL + +#if defined(SEMAILBOX_PRESENT) + +#define SE_COMMAND_STATUS_SE_VERSION 0x43080000UL +#define SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL + +#define SE_COMMAND_WRITE_USER_DATA 0x43090000UL +#define SE_COMMAND_ERASE_USER_DATA 0x430A0000UL + +#define SE_COMMAND_DBG_LOCK_APPLY 0x430C0000 +#define SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000 +#define SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000 +#define SE_COMMAND_DEVICE_ERASE 0x430F0000 +#define SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000 +#define SE_COMMAND_DBG_LOCK_STATUS 0x43110000 + +#define SE_COMMAND_PROTECTED_REGISTER 0x43210000 + +#define SE_COMMAND_GET_CHALLENGE 0xFD000000UL +#define SE_COMMAND_ROLL_CHALLENGE 0xFD000100UL +#define SE_COMMAND_OPEN_DEBUG 0xFD010001UL +#define SE_COMMAND_DISABLE_TAMPER 0xFD020001UL + +#define SE_COMMAND_READ_SERIAL 0xFE000000UL +#define SE_COMMAND_GET_STATUS 0xFE010000UL +#define SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL + +#define SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL +#define SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL + +#define SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL +#define SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL +#endif /* SEMAILBOX_PRESENT */ + +#if defined(SEMAILBOX_PRESENT) +/* Command options for the Secure Element commands. */ +/** Use MD5 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_MD5 0x00000100UL +/** Use SHA1 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL +/** Use SHA224 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL +/** Use SHA256 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +/** Use SHA384 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL +/** Use SHA512 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +/** Execute algorithm in ECB mode */ +#define SE_COMMAND_OPTION_MODE_ECB 0x00000100UL +/** Execute algorithm in CBC mode */ +#define SE_COMMAND_OPTION_MODE_CBC 0x00000200UL +/** Execute algorithm in CTR mode */ +#define SE_COMMAND_OPTION_MODE_CTR 0x00000300UL +/** Execute algorithm in CFB mode */ +#define SE_COMMAND_OPTION_MODE_CFB 0x00000400UL +/** Execute algorithm in OFB mode */ +#define SE_COMMAND_OPTION_MODE_OFB 0x00000500UL +/** Execute algorithm in XTS mode */ +#define SE_COMMAND_OPTION_MODE_XTS 0x00000800UL + +#define SE_COMMAND_OPTION_CERT_DEVICE 0x00000100UL +#define SE_COMMAND_OPTION_CERT_BATCH 0x00000200UL +#define SE_COMMAND_OPTION_CERT_FACTORY 0x00000300UL + +/** Pubkey type */ +#define SE_KEY_TYPE_ROOT 0x00000300UL + +/** Run the whole algorithm, all data present */ +#define SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL +/** Start the algorithm, but get a context to later add more data */ +#define SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL +/** End the algorithm, get the result */ +#define SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL +/** Add more data input to the algorithm. Need to supply previous context, + * and get a context back */ +#define SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL + +/** Padding options for signature functionality. */ +#define SE_COMMAND_OPTION_PADDING_NONE 0x00000000UL +#define SE_COMMAND_OPTION_PADDING_EMSA_PKCS 0x00000003UL +#define SE_COMMAND_OPTION_PADDING_PSS 0x00000004UL + +/* Special parameters for the Secure Element commands. */ +#define SE_COMMAND_OPTION_READ 0x00000000UL +#define SE_COMMAND_OPTION_WRITE 0x00000100UL + +/** Magic parameter for deleting user data */ +#define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL + +#endif /* SEMAILBOX_PRESENT */ + +/** Pubkey types */ +#define SE_KEY_TYPE_BOOT 0x00000100UL +#define SE_KEY_TYPE_AUTH 0x00000200UL + +#define SE_COMMAND_INIT_OTP 0xFF000001UL +#define SE_COMMAND_INIT_PUBKEY 0xFF070001UL + +#define SE_COMMAND_READ_PUBKEY 0xFF080001UL + +/** + * Command was not recognized as a valid command, or is not allowed in the + * current context. + */ +#define SE_RESPONSE_INVALID_COMMAND 0x00010000UL +/** + * User did not provide the required credentials to be allowed to execute the + * command. + */ +#define SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL +/** + * Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to + * verify the given signature as being correct. + */ +#define SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL +/** A command started in non-secure mode is trying to access secure memory. */ +#define SE_RESPONSE_BUS_ERROR 0x00040000UL +/** Internal error */ +#define SE_RESPONSE_INTERNAL_ERROR 0x00050000UL +/** An internal error was raised and the command did not execute. */ +#define SE_RESPONSE_CRYPTO_ERROR 0x00060000UL +/** One of the passed parameters is deemed invalid (e.g. out of bounds). */ +#define SE_RESPONSE_INVALID_PARAMETER 0x00070000UL +/** Failure while checking the host for secure boot */ +#define SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL +/** Failure during selftest */ +#define SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL +/** Feature/item not initialized or not present */ +#define SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL +/* Abort status code is given when no operation is attempted. */ +#define SE_RESPONSE_ABORT 0x00FF0000UL + +/** @endcond */ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/** SE OTP initialization struct */ +typedef struct { + /** Enable secure boot for the host. */ + bool enableSecureBoot; + /** Require certificate based secure boot signing. */ + bool verifySecureBootCertificate; + /** Enable anti-rollback for host application upgrades. */ + bool enableAntiRollback; + + /** Set flag to enable locking down all flash pages that cover the + * secure-booted image, except the last page if end of signature is not + * page-aligned. */ + bool secureBootPageLockNarrow; + /** Set flag to enable locking down all flash pages that cover the + * secure-booted image, including the last page if end of signature is not + * page-aligned. */ + bool secureBootPageLockFull; +} SE_OTPInit_t; + +/** SE debug status */ +typedef struct { + /** Whether debug lock is enabled */ + bool debugLockEnabled; + /** Whether device erase is enabled */ + bool deviceEraseEnabled; + /** Whether secure debug is enabled */ + bool secureDebugEnabled; +} SE_DebugStatus_t; + +/** SE status */ +typedef struct { + /** Boot status code / error code (Bits [7:0]). */ + uint32_t bootStatus; + /** SE firmware version. */ + uint32_t seFwVersion; + /** Host firmware version (if available). */ + uint32_t hostFwVersion; + /** Debug lock status. */ + SE_DebugStatus_t debugStatus; + /** Secure boot enabled. */ + bool secureBootEnabled; +} SE_Status_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_initPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) +SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_initPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) SL_DEPRECATED_API_SDK_4_4; + +#if defined(SEMAILBOX_PRESENT) + +// User data commands +SE_Response_t SE_writeUserData(uint32_t offset, + void *data, + uint32_t numBytes) +SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_eraseUserData(void) SL_DEPRECATED_API_SDK_3_0; + +// Initialization commands +SE_Response_t SE_readPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) SL_DEPRECATED_API_SDK_4_4; + +// Debug commands +SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugLockApply(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugSecureEnable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugSecureDisable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_deviceEraseDisable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_deviceErase(void) SL_DEPRECATED_API_SDK_3_0; + +// Device status commands +SE_Response_t SE_getStatus(SE_Status_t *output) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_serialNumber(void *serial) SL_DEPRECATED_API_SDK_3_0; + +#endif // #if defined(SEMAILBOX_PRESENT) +#endif // #if !defined(SLI_EM_SE_HOST) + +/** @} (end addtogroup se_deprecated) */ + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup se) */ + +#endif /* defined(SEMAILBOX_PRESENT) + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) */ + +#endif /* EM_SE_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h index 2f448f9..10826f4 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h @@ -1,1712 +1,1712 @@ -/***************************************************************************//** - * @file - * @brief Security Management Unit (SMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SMU_H -#define EM_SMU_H - -#include "em_device.h" -#if defined(SMU_COUNT) && (SMU_COUNT > 0) - -#include "sl_assert.h" -#include "em_bus.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup smu SMU - Security Management Unit - * @brief Security Management Unit (SMU) Peripheral API - * - * @details - * SMU forms the control and status/reporting component of bus-level - * security in EFM32/EFR32 devices. - * - * Peripheral-level protection is provided via the Peripheral Protection Unit - * (PPU). PPU provides hardware access barrier to any peripheral that is - * configured to be protected. When an attempt is made to access a peripheral - * without the required privilege/security level, PPU detects the fault - * and intercepts the access. No write or read of the peripheral register - * space occurs, and an all-zero value is returned if the access is a read. - * - * Usage example - * @include em_smu_init.c - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** SMU peripheral identifiers. */ -typedef enum { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ -#if defined(_SMU_PPUPATD0_CSEN_SHIFT) - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ -#endif -#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ -#endif - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ -#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ -#endif - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#if defined(_SMU_PPUPATD0_ACMP0_SHIFT) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ -#endif -#if defined(_SMU_PPUPATD0_ACMP1_SHIFT) - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ -#endif -#if defined(_SMU_PPUPATD0_ADC0_SHIFT) - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ -#endif - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ -#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ -#endif - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ -#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ -#endif - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ -#if defined(_SMU_PPUPATD0_LESENSE_SHIFT) - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ -#endif - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ -#if defined(_SMU_PPUPATD0_PCNT0_SHIFT) - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ -#endif - smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ - smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ -#if defined(_SMU_PPUPATD0_ETH_SHIFT) - smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ -#endif - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ - smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ -#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) - smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ -#endif - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ -#if defined(_SMU_PPUPATD1_SDIO_SHIFT) - smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ - smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ - smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */ - smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */ - smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ - smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */ -#if defined(_SMU_PPUPATD1_USB_SHIFT) - smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */ - smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ -#if defined(_SMU_PPUPATD0_ETH_SHIFT) - smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ -#endif - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ - smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ -#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) - smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ -#endif - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ -#if defined(_SMU_PPUPATD1_SDIO_SHIFT) - smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ - smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ -#if defined(_SMU_PPUPATD1_USB_SHIFT) - smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_32B_SERIES_2) -#if defined(SMU_PPUPATD0_SCRATCHPAD) - smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */ -#endif - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ -#if defined(_SMU_PPUPATD0_HFXO0_SHIFT) - smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif -#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) - smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif - smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */ - smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */ - smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */ - smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */ - smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */ - smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ - smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ - smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */ - smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ - smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ - smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */ - smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */ -#if defined(_SMU_PPUPATD0_TIMER4_SHIFT) - smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER5_SHIFT) - smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER6_SHIFT) - smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER7_SHIFT) - smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */ -#endif -#if defined(_SMU_PPUPATD0_USART0_SHIFT) - smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ -#endif -#if defined(_SMU_PPUPATD0_USART1_SHIFT) - smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ -#endif -#if defined(_SMU_PPUPATD0_USART2_SHIFT) - smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ -#endif - smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */ -#if defined(_SMU_PPUPATD0_I2C1_SHIFT) - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ -#endif -#if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT) - smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */ -#endif -#if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT) - smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */ -#endif - -#if defined(SMU_PPUPATD0_LVGD) - smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */ -#endif - smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */ -#if defined(_SMU_PPUPATD0_BURAM_SHIFT) - smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ -#endif -#if defined(_SMU_PPUPATD1_BURAM_SHIFT) - smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ -#endif -#if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT) - smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/ -#endif -#if defined(_SMU_PPUPATD0_GPCRC_SHIFT) - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ -#endif -#if defined(_SMU_PPUPATD1_GPCRC_SHIFT) - smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ -#endif -#if defined(_SMU_PPUPATD0_DCDC_SHIFT) - smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ -#endif -#if defined(_SMU_PPUPATD0_RTCC_SHIFT) - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ -#endif -#if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT) - smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */ -#endif -#if defined(_SMU_PPUPATD1_EUSART0_SHIFT) - smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */ -#endif -#if defined(_SMU_PPUPATD0_EUSART1_SHIFT) - smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART1_SHIFT) - smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ -#endif -#if defined(_SMU_PPUPATD0_EUSART2_SHIFT) - smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART2_SHIFT) - smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART3_SHIFT) - smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART4_SHIFT) - smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */ -#endif -#if defined(_SMU_PPUPATD1_RTCC_SHIFT) - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ -#endif -#if defined(_SMU_PPUPATD1_SYSRTC_SHIFT) - smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */ -#endif -#if defined(_SMU_PPUPATD1_LCD_SHIFT) - smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */ -#endif -#if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT) - smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */ -#endif -#if defined(_SMU_PPUPATD1_DMEM_SHIFT) - smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */ -#endif -#if defined(_SMU_PPUPATD1_LCDRF_SHIFT) - smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */ -#endif -#if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT) - smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */ -#endif -#if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT) - smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */ -#endif -#if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT) - smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */ -#endif -#if defined(_SMU_PPUPATD1_VDAC0_SHIFT) - smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ -#endif -#if defined(_SMU_PPUPATD1_VDAC1_SHIFT) - smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */ -#endif -#if defined(_SMU_PPUPATD1_PCNT_SHIFT) - smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */ -#endif -#if defined(_SMU_PPUPATD1_LESENSE_SHIFT) - smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ -#endif -#if defined(_SMU_PPUPATD1_HFRCO1_SHIFT) - smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */ -#endif -#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) - smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif -#if defined(_SMU_PPUPATD1_DCDC_SHIFT) - smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ -#endif -#if defined(_SMU_PPUPATD1_PDM_SHIFT) - smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */ -#endif -#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT) - smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */ -#endif -#if defined(_SMU_PPUPATD1_SEPUF_SHIFT) - smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */ -#endif - smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */ -#if defined(_SMU_PPUPATD1_IADC0_SHIFT) - smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */ -#endif -#if defined(_SMU_PPUPATD1_ACMP0_SHIFT) - smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ -#endif -#if defined(_SMU_PPUPATD1_ACMP1_SHIFT) - smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ -#endif -#if defined(_SMU_PPUPATD1_I2C0_SHIFT) - smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ -#endif -#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT) - smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ -#if defined(_SMU_PPUPATD1_WDOG1_SHIFT) - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ -#endif - smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */ -#if defined(_SMU_PPUPATD1_RADIOAES_SHIFT) - smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */ -#endif -#if defined(_SMU_PPUPATD1_EUART0_SHIFT) - smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */ -#endif -#if defined(_SMU_PPUPATD1_BUFC_SHIFT) - smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ -#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT) - smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */ -#endif -#if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT) - smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */ -#endif -#if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT) - smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */ -#endif -#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT) - smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */ -#endif -#if defined(_SMU_PPUPATD1_MVP_SHIFT) - smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */ -#endif -#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT) - smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */ -#endif -#else -#error "No peripherals defined for SMU for this device configuration." -#endif - smuPeripheralEnd /**< SMU peripheral end. */ -} SMU_Peripheral_TypeDef; - -/** SMU peripheral privileged access enablers. */ -typedef struct { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - - bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ - bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedETH : 1; /**< Privileged access enabler for ETH. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ - bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */ - bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */ - bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */ - bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ - bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ - - bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ - bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */ - bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - - bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ - bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ - bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */ - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */ - bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ - bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ - bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ - bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */ - bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */ - bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ - bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */ - bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ - - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ - bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ - bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ - bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#else -#error "No peripherals defined for SMU for this device configuration" -#endif -} SMU_PrivilegedAccess_TypeDef; - -/******************************************************************************* - ****************************** STRUCTS ************************************ - ******************************************************************************/ - -/** SMU initialization structure. */ -typedef struct { - union { -#if defined(_SMU_PPUNSPATD2_MASK) - uint32_t reg[3]; /**< Peripheral access control array.*/ -#else - uint32_t reg[2]; /**< Peripheral access control array.*/ -#endif - SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/ - } ppu; /**< PPU init array.*/ - bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/ -} SMU_Init_TypeDef; - -/** Default SMU initialization structure settings. */ -#define SMU_INIT_DEFAULT { \ - { { 0 } }, /* No peripherals access protected. */ \ - true /* Enable SMU.*/ \ -} - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Enable or disable PPU of SMU. - * - * @param[in] enable - * Set to true to enable PPU; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void SMU_EnablePPU(bool enable) -{ -#if defined (_SMU_PPUCTRL_ENABLE_SHIFT) - BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); -#else - (void)enable; -#endif -} - -/***************************************************************************//** - * @brief - * Initialize PPU of SMU. - * - * @param[in] init - * Pointer to initialization structure that defines which peripherals should - * only be accessed from privileged mode, and if PPU should be enabled. - ******************************************************************************/ -__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0]; - SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1]; -#if defined(_SMU_PPUNSPATD2_MASK) - SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2]; -#endif //defined(_SMU_PPUNSPATD2_MASK) -#else - SMU->PPUPATD0 = init->ppu.reg[0]; - SMU->PPUPATD1 = init->ppu.reg[1]; -#if defined(_SMU_PPUNSPATD2_MASK) - SMU->PPUPATD2 = init->ppu.reg[2]; -#endif //defined(_SMU_PPUNSPATD2_MASK) -#endif //SL_TRUSTZONE_SECURE - - SMU_EnablePPU(init->enable); -} -/***************************************************************************//** - * @brief - * Change access settings for a peripheral. - * - * @details - * Set to limit access of a peripheral from privileged mode. - * - * @param[in] peripheral - * ID of the peripheral to change access settings for. - * - * @param[in] privileged - * Set to true if the peripheral should only be accessed from privileged - * mode; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, - bool privileged) -{ - EFM_ASSERT(peripheral < smuPeripheralEnd); - -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - if (peripheral < 32) { - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged); - } else if (peripheral < 64) { - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged); - } else { -#if defined(_SMU_PPUNSPATD2_MASK) - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); -#else - EFM_ASSERT(false); -#endif //defined(_SMU_PPUNSPATD2_MASK) - } -#else - if (peripheral < 32) { - BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); - } else if (peripheral < 64) { - BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); - } else { -#if defined(_SMU_PPUNSPATD2_MASK) - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); -#else - EFM_ASSERT(false); -#endif //defined(_SMU_PPUNSPATD2_MASK) - } -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Get the ID of the peripheral that caused an access fault. - * - * @note - * The return value is only valid if SMU_IF_PPUPRIV interrupt flag - * is set. - * - * @return - * ID of the peripheral that caused an access fault. - ******************************************************************************/ -__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS; -#else - return (SMU_Peripheral_TypeDef)SMU->PPUFS; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Clear one or more pending SMU interrupts. - * - * @param[in] flags - * Bitwise logic OR of SMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntClear(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIF_CLR = flags; -#else - SMU->IF_CLR = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IFC = flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Disable one or more SMU interrupts. - * - * @param[in] flags - * SMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntDisable(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIEN_CLR = flags; -#else - SMU->IEN_CLR = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IEN &= ~flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Enable one or more SMU interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * SMU_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * SMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntEnable(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIEN_SET = flags; -#else - SMU->IEN_SET = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IEN |= flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Get pending SMU interrupts. - * - * @return - * SMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t SMU_IntGet(void) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - return SMU_NS_CFGNS->NSIF; -#else - return SMU->IF; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Get enabled and pending SMU interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by this function. - * - * @return - * Pending and enabled SMU interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in SMU_IEN register - * and - * - the OR combination of valid interrupt flags in SMU_IF register. - ******************************************************************************/ -__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) -{ - uint32_t tmp; - -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - // Store SMU->IEN in temporary variable to define explicit order - // of volatile accesses. - tmp = SMU_NS_CFGNS->NSIEN; - - // Bitwise AND of pending and enabled interrupts. - return SMU_NS_CFGNS->NSIF & tmp; -#else - // Store SMU->IEN in temporary variable to define explicit order - // of volatile accesses. - tmp = SMU->IEN; - - // Bitwise AND of pending and enabled interrupts. - return SMU->IF & tmp; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Set one or more pending SMU interrupts from SW. - * - * @param[in] flags - * SMU interrupt sources to set to pending. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntSet(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIF_SET = flags; -#else - SMU->IF_SET = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IFS = flags; -#endif //SMU_HAS_SET_CLEAR -} - -/**************************************************************************//** -* @brief -* SMU secure IRQ Handler. -* -* @details -* When a PPU detects an access to a secure peripheral at its non-secure -* address or an access to a non-secure peripheral at its secure -* address, PPUSECIF in SMU_IF is set and the ID of the peripheral being -* accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's -* Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler -* Will handle the interrupt. -******************************************************************************/ -#if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2) -void SMU_SECURE_IRQHandler(void) -{ - if (SMU_IF_PPUSEC) { - EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC); - } - - if (SMU_IF_BMPUSEC) { - EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC); - } - - // PPUFS contains the ID of the peripheral caused the fault - // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields. - EFM_ASSERT(SMU->PPUFS); - - while (1) { - // do nothing - } -} -#endif //SL_TRUSTZONE_SECURE - -/** @} (end addtogroup smu) */ - -#ifdef __cplusplus -} -#endif - -#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) -#endif // EM_SMU_H +/***************************************************************************//** + * @file + * @brief Security Management Unit (SMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup smu SMU - Security Management Unit + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * SMU forms the control and status/reporting component of bus-level + * security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the Peripheral Protection Unit + * (PPU). PPU provides hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ +#if defined(_SMU_PPUPATD0_CSEN_SHIFT) + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ +#endif +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#if defined(_SMU_PPUPATD0_ACMP0_SHIFT) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ +#endif +#if defined(_SMU_PPUPATD0_ACMP1_SHIFT) + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ +#endif +#if defined(_SMU_PPUPATD0_ADC0_SHIFT) + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ +#endif + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ +#if defined(_SMU_PPUPATD0_LESENSE_SHIFT) + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ +#endif + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ +#if defined(_SMU_PPUPATD0_PCNT0_SHIFT) + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ +#endif + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */ + smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */ + smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ + smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */ + smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SMU_PPUPATD0_SCRATCHPAD) + smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */ +#endif + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ +#if defined(_SMU_PPUPATD0_HFXO0_SHIFT) + smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif + smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */ + smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */ + smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */ + smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */ + smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */ + smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */ + smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */ +#if defined(_SMU_PPUPATD0_TIMER4_SHIFT) + smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER5_SHIFT) + smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER6_SHIFT) + smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER7_SHIFT) + smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */ +#endif +#if defined(_SMU_PPUPATD0_USART0_SHIFT) + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ +#endif +#if defined(_SMU_PPUPATD0_USART1_SHIFT) + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ +#endif +#if defined(_SMU_PPUPATD0_USART2_SHIFT) + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ +#endif + smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */ +#if defined(_SMU_PPUPATD0_I2C1_SHIFT) + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ +#endif +#if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT) + smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */ +#endif +#if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT) + smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */ +#endif + +#if defined(SMU_PPUPATD0_LVGD) + smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */ +#endif + smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */ +#if defined(_SMU_PPUPATD0_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD1_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT) + smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/ +#endif +#if defined(_SMU_PPUPATD0_GPCRC_SHIFT) + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD1_GPCRC_SHIFT) + smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD0_DCDC_SHIFT) + smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD0_RTCC_SHIFT) + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT) + smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_EUSART0_SHIFT) + smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART1_SHIFT) + smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART1_SHIFT) + smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART2_SHIFT) + smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART2_SHIFT) + smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART3_SHIFT) + smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART4_SHIFT) + smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */ +#endif +#if defined(_SMU_PPUPATD1_RTCC_SHIFT) + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD1_SYSRTC_SHIFT) + smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */ +#endif +#if defined(_SMU_PPUPATD1_LCD_SHIFT) + smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */ +#endif +#if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT) + smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */ +#endif +#if defined(_SMU_PPUPATD1_DMEM_SHIFT) + smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */ +#endif +#if defined(_SMU_PPUPATD1_LCDRF_SHIFT) + smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */ +#endif +#if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT) + smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */ +#endif +#if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT) + smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */ +#endif +#if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT) + smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */ +#endif +#if defined(_SMU_PPUPATD1_VDAC0_SHIFT) + smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ +#endif +#if defined(_SMU_PPUPATD1_VDAC1_SHIFT) + smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */ +#endif +#if defined(_SMU_PPUPATD1_PCNT_SHIFT) + smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */ +#endif +#if defined(_SMU_PPUPATD1_LESENSE_SHIFT) + smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ +#endif +#if defined(_SMU_PPUPATD1_HFRCO1_SHIFT) + smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_DCDC_SHIFT) + smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD1_PDM_SHIFT) + smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */ +#endif +#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT) + smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */ +#endif +#if defined(_SMU_PPUPATD1_SEPUF_SHIFT) + smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */ +#endif + smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */ +#if defined(_SMU_PPUPATD1_IADC0_SHIFT) + smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP0_SHIFT) + smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP1_SHIFT) + smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ +#endif +#if defined(_SMU_PPUPATD1_I2C0_SHIFT) + smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ +#endif +#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT) + smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ +#if defined(_SMU_PPUPATD1_WDOG1_SHIFT) + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ +#endif + smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */ +#if defined(_SMU_PPUPATD1_RADIOAES_SHIFT) + smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */ +#endif +#if defined(_SMU_PPUPATD1_EUART0_SHIFT) + smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */ +#endif +#if defined(_SMU_PPUPATD1_BUFC_SHIFT) + smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ +#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT) + smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */ +#endif +#if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT) + smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */ +#endif +#if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT) + smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */ +#endif +#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT) + smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_MVP_SHIFT) + smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */ +#endif +#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT) + smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */ +#endif +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd /**< SMU peripheral end. */ +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedETH : 1; /**< Privileged access enabler for ETH. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */ + bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + + bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */ + bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */ + bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */ + bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { +#if defined(_SMU_PPUNSPATD2_MASK) + uint32_t reg[3]; /**< Peripheral access control array.*/ +#else + uint32_t reg[2]; /**< Peripheral access control array.*/ +#endif + SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/ + } ppu; /**< PPU init array.*/ + bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +/** Default SMU initialization structure settings. */ +#define SMU_INIT_DEFAULT { \ + { { 0 } }, /* No peripherals access protected. */ \ + true /* Enable SMU.*/ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable PPU of SMU. + * + * @param[in] enable + * Set to true to enable PPU; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ +#if defined (_SMU_PPUCTRL_ENABLE_SHIFT) + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +#else + (void)enable; +#endif +} + +/***************************************************************************//** + * @brief + * Initialize PPU of SMU. + * + * @param[in] init + * Pointer to initialization structure that defines which peripherals should + * only be accessed from privileged mode, and if PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0]; + SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#else + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU->PPUPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#endif //SL_TRUSTZONE_SECURE + + SMU_EnablePPU(init->enable); +} +/***************************************************************************//** + * @brief + * Change access settings for a peripheral. + * + * @details + * Set to limit access of a peripheral from privileged mode. + * + * @param[in] peripheral + * ID of the peripheral to change access settings for. + * + * @param[in] privileged + * Set to true if the peripheral should only be accessed from privileged + * mode; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + if (peripheral < 32) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#else + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the peripheral that caused an access fault. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS; +#else + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_CLR = flags; +#else + SMU->IF_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFC = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_CLR = flags; +#else + SMU->IEN_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN &= ~flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * SMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_SET = flags; +#else + SMU->IEN_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN |= flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return SMU_NS_CFGNS->NSIF; +#else + return SMU->IF; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU_NS_CFGNS->NSIEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU_NS_CFGNS->NSIF & tmp; +#else + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU->IF & tmp; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_SET = flags; +#else + SMU->IF_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFS = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/**************************************************************************//** +* @brief +* SMU secure IRQ Handler. +* +* @details +* When a PPU detects an access to a secure peripheral at its non-secure +* address or an access to a non-secure peripheral at its secure +* address, PPUSECIF in SMU_IF is set and the ID of the peripheral being +* accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's +* Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler +* Will handle the interrupt. +******************************************************************************/ +#if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2) +void SMU_SECURE_IRQHandler(void) +{ + if (SMU_IF_PPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC); + } + + if (SMU_IF_BMPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC); + } + + // PPUFS contains the ID of the peripheral caused the fault + // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields. + EFM_ASSERT(SMU->PPUFS); + + while (1) { + // do nothing + } +} +#endif //SL_TRUSTZONE_SECURE + +/** @} (end addtogroup smu) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h index fb10b4a..17a4d58 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h @@ -1,171 +1,171 @@ -/***************************************************************************//** - * @file - * @brief API defining acces to SYSCFG registers - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SYSCFG_H -#define EM_SYSCFG_H - -#include "em_device.h" - -#if defined(SL_TRUSTZONE_NONSECURE) -#include "sli_tz_service_syscfg.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(SYSCFG) -/******************************************************************************* - ******************************** TZ SERVICES ********************************** - ******************************************************************************/ - -#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) -/******************************************************************************* - * @brief Reads CHIPREV register - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_readChipRev(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_read_chiprev_register(); -#else - return SYSCFG->CHIPREV; -#endif -} -#endif // defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - -#if defined(_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) -/******************************************************************************* - * @brief Sets DMEM0RAMCTRL RAMWSEN bit to 1 - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); -#else - - SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL | _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; -#endif -} - -/******************************************************************************* - * @brief Clears DMEM0RAMCTRL RAMWSEN bit to 0 - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); -#else - SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; -#endif -} - -/******************************************************************************* - * @brief Reads DMEM0RAMCTRL RAMWSEN bit - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); -#else - return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; -#endif -} - -#endif //_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK -#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) - -/******************************************************************************* - * @brief Reads DMEM0RETNCTRL register - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_read_dmem0retnctrl_register(); -#else - return SYSCFG->DMEM0RETNCTRL; -#endif -} -/******************************************************************************* - * @brief Mask DMEM0RETNCTRL register with provided mask - * - * @param mask - A mask that is to be used to mask the DMEM0RETNCTRL register - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_mask_dmem0retnctrl_register(mask); -#else - SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; -#endif -} - -/******************************************************************************* - * @brief Set DMEM0RETNCTRL to zero - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_zero_dmem0retnctrl_register(); -#else - SYSCFG->DMEM0RETNCTRL = 0x0UL; -#endif -} -#endif // _SYSCFG_DMEM0RETNCTRL_MASK - -#if defined(_SYSCFG_CFGSYSTIC_MASK) -/******************************************************************************* - * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_set_systicextclken_cfgsystic(); -#else - SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); -#endif -} - -/******************************************************************************* - * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_clear_systicextclken_cfgsystic(); -#else - SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); -#endif -} -#endif //_SYSCFG_CFGSYSTIC_MASK -#endif //SYSCFG -#ifdef __cplusplus -} -#endif -#endif // EM_SYSCFG_H +/***************************************************************************//** + * @file + * @brief API defining acces to SYSCFG registers + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSCFG_H +#define EM_SYSCFG_H + +#include "em_device.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_service_syscfg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SYSCFG) +/******************************************************************************* + ******************************** TZ SERVICES ********************************** + ******************************************************************************/ + +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) +/******************************************************************************* + * @brief Reads CHIPREV register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readChipRev(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_chiprev_register(); +#else + return SYSCFG->CHIPREV; +#endif +} +#endif // defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + +#if defined(_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) +/******************************************************************************* + * @brief Sets DMEM0RAMCTRL RAMWSEN bit to 1 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); +#else + + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL | _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Clears DMEM0RAMCTRL RAMWSEN bit to 0 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); +#else + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Reads DMEM0RAMCTRL RAMWSEN bit + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); +#else + return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; +#endif +} + +#endif //_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) + +/******************************************************************************* + * @brief Reads DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_dmem0retnctrl_register(); +#else + return SYSCFG->DMEM0RETNCTRL; +#endif +} +/******************************************************************************* + * @brief Mask DMEM0RETNCTRL register with provided mask + * + * @param mask - A mask that is to be used to mask the DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_mask_dmem0retnctrl_register(mask); +#else + SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; +#endif +} + +/******************************************************************************* + * @brief Set DMEM0RETNCTRL to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_zero_dmem0retnctrl_register(); +#else + SYSCFG->DMEM0RETNCTRL = 0x0UL; +#endif +} +#endif // _SYSCFG_DMEM0RETNCTRL_MASK + +#if defined(_SYSCFG_CFGSYSTIC_MASK) +/******************************************************************************* + * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +/******************************************************************************* + * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} +#endif //_SYSCFG_CFGSYSTIC_MASK +#endif //SYSCFG +#ifdef __cplusplus +} +#endif +#endif // EM_SYSCFG_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h index 88d9f73..6bae748 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h @@ -1,361 +1,361 @@ -/***************************************************************************//** - * @file - * @brief System API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SYSTEM_H -#define EM_SYSTEM_H - -#include "em_device.h" -#include "em_system_generic.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup system SYSTEM - System Utils - * @brief System API - * @details - * This module contains functions to read information such as RAM and Flash size, - * device unique ID, chip revision, family, and part number from DEVINFO and - * SCB blocks. Functions to configure and read status from FPU are available for - * compatible devices. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Family identifiers. */ -typedef enum { -/* New style family #defines */ -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) - systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) - systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) - systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) - systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) - systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) - systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) - systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) - systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) - systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) - systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) - systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) - systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) - systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) - systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) - systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) - systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) - systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) - systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) - systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) - systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) - systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) - systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) - systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) - systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) - systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) - systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) - systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) - systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) - systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) - systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) - systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) - systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) - systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) - systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) - systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) - systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) - systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) - systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) - systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) - systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) - systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) - systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) - systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) - systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) - systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L) - systemPartFamilyZen13L = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L, /**< EFR32 Zen Gecko Series 1 Configuration 3 Led Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S) - systemPartFamilyZen13S = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S, /**< EFR32 Zen Gecko Series 1 Configuration 3 Sensor Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) - systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) - systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) - systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) - systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) - systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) - systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) - systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyMightyRcp21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty RCP Series 2 Config 1 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - systemPartFamilyMighty22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyFlex22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyBlue22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyEfm32Pearl22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - systemPartFamilyFlex23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilyZen23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilyEfm32Pearl23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilySideWalk23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) - systemPartFamilyMighty24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family */ - systemPartFamilyFlex24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 4 Value Device Family */ - systemPartFamilyBlue24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 4 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - systemPartFamilyFlex25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 5 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - systemPartFamilyMighty26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family */ - systemPartFamilyBlue26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 6 Value Device Family */ - systemPartFamilyEfm32Pearl26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - systemPartFamilyMighty27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family */ - systemPartFamilyBlue27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 7 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - systemPartFamilyFlex28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilyZen28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilySideWalk28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilyEfm32Pearl28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family */ -#endif -/* Deprecated family #defines */ -#if defined(_DEVINFO_PART_DEVICE_FAMILY_G) - systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) - systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) - systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) - systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) - systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) - systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) - systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ -#endif - systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. - Family ID is missing - on unprogrammed parts. */ -} SYSTEM_PartFamily_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Chip revision details. */ -typedef struct { - uint8_t minor; /**< Minor revision number. */ - uint8_t major; /**< Major revision number. */ -#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - uint16_t partNumber; /**< Device part number. */ -#else - uint8_t family; /**< Device family number. */ -#endif -} SYSTEM_ChipRevision_TypeDef; - -#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) -/** Floating point co-processor access modes. */ -typedef enum { - fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ - fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ - fpuAccessReserved = (0xA << 20), /**< Reserved. */ - fpuAccessFull = (0xF << 20) /**< Full access. */ -} SYSTEM_FpuAccess_TypeDef; -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); -SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void); - -#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) -/***************************************************************************//** - * @brief - * Get DEVINFO revision. - * - * @return - * Revision of the DEVINFO contents. - ******************************************************************************/ -__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) -{ -#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) - return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) - >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); -#elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) - return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) - >> _DEVINFO_INFO_DEVINFOREV_SHIFT); -#endif -} -#endif - -#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) -/***************************************************************************//** - * @brief - * Set floating point co-processor (FPU) access mode. - * - * @param[in] accessMode - * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef - * for details. - ******************************************************************************/ -__STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) -{ - SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; -} -#endif - -/** @} (end addtogroup system) */ - -#ifdef __cplusplus -} -#endif -#endif /* EM_SYSTEM_H */ +/***************************************************************************//** + * @file + * @brief System API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSTEM_H +#define EM_SYSTEM_H + +#include "em_device.h" +#include "em_system_generic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @brief System API + * @details + * This module contains functions to read information such as RAM and Flash size, + * device unique ID, chip revision, family, and part number from DEVINFO and + * SCB blocks. Functions to configure and read status from FPU are available for + * compatible devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family identifiers. */ +typedef enum { +/* New style family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) + systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) + systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) + systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) + systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) + systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) + systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) + systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) + systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) + systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) + systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) + systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) + systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) + systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) + systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L) + systemPartFamilyZen13L = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L, /**< EFR32 Zen Gecko Series 1 Configuration 3 Led Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S) + systemPartFamilyZen13S = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S, /**< EFR32 Zen Gecko Series 1 Configuration 3 Sensor Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) + systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) + systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) + systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) + systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) + systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) + systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) + systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyMightyRcp21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty RCP Series 2 Config 1 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + systemPartFamilyMighty22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyFlex22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyBlue22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyEfm32Pearl22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + systemPartFamilyFlex23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyZen23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyEfm32Pearl23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilySideWalk23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + systemPartFamilyMighty24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyFlex24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyBlue24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 4 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + systemPartFamilyFlex25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 5 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + systemPartFamilyMighty26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyBlue26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyEfm32Pearl26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + systemPartFamilyMighty27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family */ + systemPartFamilyBlue27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 7 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + systemPartFamilyFlex28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyZen28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilySideWalk28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyEfm32Pearl28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family */ +#endif +/* Deprecated family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_G) + systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) + systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) + systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) + systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) + systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) + systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) + systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ +#endif + systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. + Family ID is missing + on unprogrammed parts. */ +} SYSTEM_PartFamily_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Chip revision details. */ +typedef struct { + uint8_t minor; /**< Minor revision number. */ + uint8_t major; /**< Major revision number. */ +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + uint16_t partNumber; /**< Device part number. */ +#else + uint8_t family; /**< Device family number. */ +#endif +} SYSTEM_ChipRevision_TypeDef; + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/** Floating point co-processor access modes. */ +typedef enum { + fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ + fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ + fpuAccessReserved = (0xA << 20), /**< Reserved. */ + fpuAccessFull = (0xF << 20) /**< Full access. */ +} SYSTEM_FpuAccess_TypeDef; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void); + +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) +/***************************************************************************//** + * @brief + * Get DEVINFO revision. + * + * @return + * Revision of the DEVINFO contents. + ******************************************************************************/ +__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) +{ +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); +#elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) + >> _DEVINFO_INFO_DEVINFOREV_SHIFT); +#endif +} +#endif + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/***************************************************************************//** + * @brief + * Set floating point co-processor (FPU) access mode. + * + * @param[in] accessMode + * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef + * for details. + ******************************************************************************/ +__STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) +{ + SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; +} +#endif + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif +#endif /* EM_SYSTEM_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h index fffec7f..ed96b00 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h @@ -1,91 +1,91 @@ -/***************************************************************************//** - * @file - * @brief System API (Generic) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_SYSTEM_GENERIC_H -#define EM_SYSTEM_GENERIC_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Family security capability. */ -typedef enum { - securityCapabilityUnknown, /**< Unknown security capability. */ - securityCapabilityNA, /**< Security capability not applicable. */ - securityCapabilityBasic, /**< Basic security capability. */ - securityCapabilityRoT, /**< Root of Trust security capability. */ - securityCapabilitySE, /**< Secure Element security capability. */ - securityCapabilityVault /**< Secure Vault security capability. */ -} SYSTEM_SecurityCapability_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** DEVINFO calibration address/value pair. */ -typedef struct { - uint32_t address; /**< Peripheral calibration register address. */ - uint32_t calValue; /**< Calibration value for register at address. */ -} -SYSTEM_CalAddrVal_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); -SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void); -uint64_t SYSTEM_GetUnique(void); -uint8_t SYSTEM_GetProdRev(void); -uint32_t SYSTEM_GetSRAMBaseAddress(void); -uint16_t SYSTEM_GetSRAMSize(void); -uint16_t SYSTEM_GetFlashSize(void); -uint32_t SYSTEM_GetFlashPageSize(void); -uint16_t SYSTEM_GetPartNumber(void); -uint8_t SYSTEM_GetCalibrationTemperature(void); - -/** @} (end addtogroup system) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_SYSTEM_GENERIC_H */ +/***************************************************************************//** + * @file + * @brief System API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_SYSTEM_GENERIC_H +#define EM_SYSTEM_GENERIC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family security capability. */ +typedef enum { + securityCapabilityUnknown, /**< Unknown security capability. */ + securityCapabilityNA, /**< Security capability not applicable. */ + securityCapabilityBasic, /**< Basic security capability. */ + securityCapabilityRoT, /**< Root of Trust security capability. */ + securityCapabilitySE, /**< Secure Element security capability. */ + securityCapabilityVault /**< Secure Vault security capability. */ +} SYSTEM_SecurityCapability_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** DEVINFO calibration address/value pair. */ +typedef struct { + uint32_t address; /**< Peripheral calibration register address. */ + uint32_t calValue; /**< Calibration value for register at address. */ +} +SYSTEM_CalAddrVal_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void); +uint64_t SYSTEM_GetUnique(void); +uint8_t SYSTEM_GetProdRev(void); +uint32_t SYSTEM_GetSRAMBaseAddress(void); +uint16_t SYSTEM_GetSRAMSize(void); +uint16_t SYSTEM_GetFlashSize(void); +uint32_t SYSTEM_GetFlashPageSize(void); +uint16_t SYSTEM_GetPartNumber(void); +uint8_t SYSTEM_GetCalibrationTemperature(void); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_SYSTEM_GENERIC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h index b0ae8e3..8ee671b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h @@ -1,1238 +1,1238 @@ -/***************************************************************************//** - * @file - * @brief Timer/counter (TIMER) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_TIMER_H -#define EM_TIMER_H - -#include "em_device.h" -#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) - -#include -#include "sl_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup timer - * @{ - ****************************************************************************** - * @deprecated - * Deprecated macro TIMER_CH_VALID for SDID 80, new code should use TIMER_REF_CH_VALID.*/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of TIMER register block pointer reference for assert statements. */ -#define TIMER_REF_VALID(ref) TIMER_Valid(ref) - -/** Validation of TIMER compare/capture channel number. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#define TIMER_CH_VALID(ch) ((ch) < 3) -#elif defined(_SILICON_LABS_32B_SERIES_1) -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define TIMER_CH_VALID(ch) _Pragma("GCC warning \"'TIMER_CH_VALID' macro is deprecated for EFR32xG1, Use TIMER_REF_CH_VALID instead\"") ((ch) < 4) -#else -#define TIMER_CH_VALID(ch) ((ch) < 4) -#endif -#else -#define TIMER_CH_VALID(ch) ((ch) < 3) -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define TIMER_REF_CH_VALID(ref, ch) ((ref == TIMER0) ? ((ch) < 3) : ((ch) < 4)) -#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_REF_CH_VALID(ref, ch) -#else -#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_CH_VALID(ch) -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Timer compare/capture mode. */ -typedef enum { -#if defined (_TIMER_CC_CTRL_MODE_MASK) - timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ - timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ - timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ - timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ -#endif -#if defined (_TIMER_CC_CFG_MODE_MASK) - timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ - timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ - timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ - timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ -#endif -} TIMER_CCMode_TypeDef; - -/** Clock select. */ -typedef enum { -#if defined (_TIMER_CTRL_CLKSEL_MASK) - timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ - timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ - timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ -#endif -#if defined (_TIMER_CFG_CLKSEL_MASK) - timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ - timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ - timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ -#endif -} TIMER_ClkSel_TypeDef; - -/** Input capture edge select. */ -typedef enum { - /** Rising edges detected. */ - timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, - - /** Falling edges detected. */ - timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, - - /** Both edges detected. */ - timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, - - /** No edge detection, leave signal as is. */ - timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE -} TIMER_Edge_TypeDef; - -/** Input capture event control. */ -typedef enum { - /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ - timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, - /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ - timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, - /** - * PRS output pulse, interrupt flag, and DMA request set on rising edge (if - * input capture edge = BOTH). - */ - timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, - /** - * PRS output pulse, interrupt flag, and DMA request set on falling edge (if - * input capture edge = BOTH). - */ - timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING -} TIMER_Event_TypeDef; - -/** Input edge action. */ -typedef enum { - /** No action taken. */ - timerInputActionNone = _TIMER_CTRL_FALLA_NONE, - - /** Start counter without reload. */ - timerInputActionStart = _TIMER_CTRL_FALLA_START, - - /** Stop counter without reload. */ - timerInputActionStop = _TIMER_CTRL_FALLA_STOP, - - /** Reload and start counter. */ - timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART -} TIMER_InputAction_TypeDef; - -/** Timer mode. */ -typedef enum { -#if defined (_TIMER_CTRL_MODE_MASK) - timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ - timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ - timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ - timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ -#endif -#if defined (_TIMER_CFG_MODE_MASK) - timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ - timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ - timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ - timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ -#endif -} TIMER_Mode_TypeDef; - -/** Compare/capture output action. */ -typedef enum { - /** No action. */ - timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, - - /** Toggle on event. */ - timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, - - /** Clear on event. */ - timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, - - /** Set on event. */ - timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET -} TIMER_OutputAction_TypeDef; - -/** Prescaler. */ -typedef enum { -#if defined (_TIMER_CTRL_PRESC_MASK) - timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ - timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ - timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ - timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ - timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ - timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ - timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ - timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ - timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ - timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ - timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ -#endif -#if defined (_TIMER_CFG_PRESC_MASK) - timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ - timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ - timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ - timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ - timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ - timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ - timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ - timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ - timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ - timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ - timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ -#endif -} TIMER_Prescale_TypeDef; - -/** Peripheral Reflex System signal. */ -typedef uint8_t TIMER_PRSSEL_TypeDef; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** Deprecated PRS channel selector. New code should use an integer instead of - * using these deprecated enum values. */ -#define timerPRSSELCh0 0UL -#define timerPRSSELCh1 1UL -#define timerPRSSELCh2 2UL -#define timerPRSSELCh3 3UL -#define timerPRSSELCh4 4UL -#define timerPRSSELCh5 5UL -#define timerPRSSELCh6 6UL -#define timerPRSSELCh7 7UL -#define timerPRSSELCh8 8UL -#define timerPRSSELCh9 9UL -#define timerPRSSELCh10 10UL -#define timerPRSSELCh11 11UL -/** @endcond */ - -#if defined (_TIMER_CC_CFG_INSEL_MASK) -/** PRS input type */ -typedef enum { - timerPrsInputNone = 0x0, /**< No PRS input. */ - timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, /**< Synchronous PRS selected. */ - timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, /**< Asynchronous level PRS selected. */ - timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, /**< Asynchronous pulse PRS selected. */ -} TIMER_PrsInput_TypeDef; -#endif - -#if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) -/** DT (Dead Time) Fault Actions. */ -typedef enum { -#if defined(_TIMER_DTFC_DTFA_MASK) - timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ - timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ - timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ - timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ -#endif -#if defined(_TIMER_DTFCFG_DTFA_MASK) - timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ - timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ - timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ - timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ -#endif -} TIMER_DtiFaultAction_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** TIMER initialization structure. */ -typedef struct { - /** Start counting when initialization completed. */ - bool enable; - - /** Counter shall keep running during debug halt. */ - bool debugRun; - - /** Prescaling factor, if HFPER / HFPERB clock used. */ - TIMER_Prescale_TypeDef prescale; - - /** Clock selection. */ - TIMER_ClkSel_TypeDef clkSel; - -#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ - && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) - /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ - bool count2x; - - /** ATI (Always Track Inputs) makes CCPOL always track - * the polarity of the inputs. */ - bool ati; - - /** Reload-Start Sets COIST - * When enabled, compare output is set to COIST value on a Reload-Start event. */ - bool rssCoist; -#endif - - /** Action on falling input edge. */ - TIMER_InputAction_TypeDef fallAction; - - /** Action on rising input edge. */ - TIMER_InputAction_TypeDef riseAction; - - /** Counting mode. */ - TIMER_Mode_TypeDef mode; - - /** DMA request clear on active. */ - bool dmaClrAct; - - /** Select X2 or X4 quadrature decode mode (if used). */ - bool quadModeX4; - - /** Determines if only counting up or down once. */ - bool oneShot; - - /** Timer can be start/stop/reload by other timers. */ - bool sync; - -#if defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT) - /** Disable ability of timer to start/stop/reload other timers that have their SYNC bit set. */ - bool disSyncOut; -#endif -} TIMER_Init_TypeDef; - -/** Default configuration for TIMER initialization structure. */ -#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ - && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) -#if (defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT)) -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - false, /* Not 2x count mode. */ \ - false, /* No ATI. */ \ - false, /* No RSSCOIST. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false, /* Not started/stopped/reloaded by other timers. */ \ - false /* Disable ability to start/stop/reload other timers. */ \ - } -#else -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - false, /* Not 2x count mode. */ \ - false, /* No ATI. */ \ - false, /* No RSSCOIST. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false /* Not started/stopped/reloaded by other timers. */ \ - } -#endif -#else -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false /* Not started/stopped/reloaded by other timers. */ \ - } -#endif - -/** PRS Output configuration. */ -typedef enum { - timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ - timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ - timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ -} TIMER_PrsOutput_t; - -/** TIMER compare/capture initialization structure. */ -typedef struct { - /** Input capture event control. */ - TIMER_Event_TypeDef eventCtrl; - - /** Input capture edge select. */ - TIMER_Edge_TypeDef edge; - - /** - * Peripheral reflex system trigger selection. Only applicable if @p prsInput - * is enabled. - */ - TIMER_PRSSEL_TypeDef prsSel; - - /** Counter underflow output action. */ - TIMER_OutputAction_TypeDef cufoa; - - /** Counter overflow output action. */ - TIMER_OutputAction_TypeDef cofoa; - - /** Counter match output action. */ - TIMER_OutputAction_TypeDef cmoa; - - /** Compare/capture channel mode. */ - TIMER_CCMode_TypeDef mode; - - /** Enable digital filter. */ - bool filter; - - /** Select TIMERnCCx (false) or PRS input (true). */ - bool prsInput; - - /** - * Compare output initial state. Only used in Output Compare and PWM mode. - * When true, the compare/PWM output is set high when the counter is - * disabled. When counting resumes, this value will represent the initial - * value for the compare/PWM output. If the bit is cleared, the output - * will be cleared when the counter is disabled. - */ - bool coist; - - /** Invert output from compare/capture channel. */ - bool outInvert; - - /** - * PRS output configuration. PRS output from a timer can either be a - * pulse output or a level output that follows the CC out value. - */ - TIMER_PrsOutput_t prsOutput; - -#if defined(_TIMER_CC_CFG_INSEL_MASK) - /** When PRS input is used this field is used to configure the type of - * PRS input. */ - TIMER_PrsInput_TypeDef prsInputType; -#endif -} TIMER_InitCC_TypeDef; - -/** Default configuration for TIMER compare/capture initialization structure. */ -#if defined(_TIMER_CC_CFG_INSEL_MASK) -#define TIMER_INITCC_DEFAULT \ - { \ - timerEventEveryEdge, /* Event on every capture. */ \ - timerEdgeRising, /* Input capture edge on rising edge. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerOutputActionNone, /* No action on underflow. */ \ - timerOutputActionNone, /* No action on overflow. */ \ - timerOutputActionNone, /* No action on match. */ \ - timerCCModeOff, /* Disable compare/capture channel. */ \ - false, /* Disable filter. */ \ - false, /* No PRS input. */ \ - false, /* Clear output when counter disabled. */ \ - false, /* Do not invert output. */ \ - timerPrsOutputDefault, /* Use default PRS output configuration. */ \ - timerPrsInputNone /* No PRS input, so input type is none. */ \ - } -#else -#define TIMER_INITCC_DEFAULT \ - { \ - timerEventEveryEdge, /* Event on every capture. */ \ - timerEdgeRising, /* Input capture edge on rising edge. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerOutputActionNone, /* No action on underflow. */ \ - timerOutputActionNone, /* No action on overflow. */ \ - timerOutputActionNone, /* No action on match. */ \ - timerCCModeOff, /* Disable compare/capture channel. */ \ - false, /* Disable filter. */ \ - false, /* No PRS input. */ \ - false, /* Clear output when counter disabled. */ \ - false, /* Do not invert output. */ \ - timerPrsOutputDefault, /* Use default PRS output configuration. */ \ - } -#endif - -#if defined(_TIMER_DTCTRL_MASK) -/** TIMER Dead Time Insertion (DTI) initialization structure. */ -typedef struct { - /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ - bool enable; - - /** DTI Output Polarity. */ - bool activeLowOut; - - /** DTI Complementary Output Invert. */ - bool invertComplementaryOut; - - /** Enable Automatic Start-up functionality (when debugger exits). */ - bool autoRestart; - - /** Enable/disable PRS as DTI input. */ - bool enablePrsSource; - - /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource - is enabled. */ - TIMER_PRSSEL_TypeDef prsSel; - - /** DTI prescaling factor, if HFPER / HFPERB clock used. */ - TIMER_Prescale_TypeDef prescale; - - /** DTI Rise Time */ - unsigned int riseTime; - - /** DTI Fall Time */ - unsigned int fallTime; - - /** DTI outputs enable bit mask, consisting of one bit per DTI - output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. - This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags - (defined in \_timer.h) OR'ed together. */ - uint32_t outputsEnableMask; - - /** Enable core lockup as a fault source. */ - bool enableFaultSourceCoreLockup; - - /** Enable debugger as a fault source. */ - bool enableFaultSourceDebugger; - - /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ - bool enableFaultSourcePrsSel0; - - /** Select which PRS signal to be PRS fault source 0. */ - TIMER_PRSSEL_TypeDef faultSourcePrsSel0; - - /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ - bool enableFaultSourcePrsSel1; - - /** Select which PRS signal to be PRS fault source 1. */ - TIMER_PRSSEL_TypeDef faultSourcePrsSel1; - - /** Fault Action */ - TIMER_DtiFaultAction_TypeDef faultAction; -} TIMER_InitDTI_TypeDef; - -/** Default configuration for TIMER DTI initialization structure. */ -#define TIMER_INITDTI_DEFAULT \ - { \ - true, /* Enable the DTI. */ \ - false, /* CC[0|1|2] outputs are active high. */ \ - false, /* CDTI[0|1|2] outputs are not inverted. */ \ - false, /* No auto restart when debugger exits. */ \ - false, /* No PRS source selected. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerPrescale1, /* No prescaling. */ \ - 0, /* No rise time. */ \ - 0, /* No fall time. */ \ - TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ - true, /* Enable core lockup as fault source. */ \ - true, /* Enable debugger as fault source. */ \ - false, /* Disable PRS fault source 0. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - false, /* Disable PRS fault source 1. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerDtiFaultActionInactive, /* No fault action. */ \ - } -#endif /* _TIMER_DTCTRL_MASK */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(TIMER_STATUS_SYNCBUSY) -void TIMER_SyncWait(TIMER_TypeDef * timer); -#endif - -/***************************************************************************//** - * @brief - * Validate the TIMER register block pointer. - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * True if ref points to a valid timer, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) -{ - return (ref == TIMER0) -#if defined(TIMER1) - || (ref == TIMER1) -#endif -#if defined(TIMER2) - || (ref == TIMER2) -#endif -#if defined(TIMER3) - || (ref == TIMER3) -#endif -#if defined(TIMER4) - || (ref == TIMER4) -#endif -#if defined(TIMER5) - || (ref == TIMER5) -#endif -#if defined(TIMER6) - || (ref == TIMER6) -#endif -#if defined(TIMER7) - || (ref == TIMER7) -#endif -#if defined(TIMER8) - || (ref == TIMER8) -#endif -#if defined(TIMER9) - || (ref == TIMER9) -#endif -#if defined(WTIMER0) - || (ref == WTIMER0) -#endif -#if defined(WTIMER1) - || (ref == WTIMER1) -#endif -#if defined(WTIMER2) - || (ref == WTIMER2) -#endif -#if defined(WTIMER3) - || (ref == WTIMER3) -#endif - ; -} - -/***************************************************************************//** - * @brief - * Check whether the TIMER is valid and supports Dead Timer Insertion (DTI). - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * True if ref points to a valid timer that supports DTI, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool TIMER_SupportsDTI(const TIMER_TypeDef *ref) -{ - (void) ref; - - return 0 -#if defined(TIMER0_DTI) -#if (TIMER0_DTI == 1) - || (ref == TIMER0) -#endif -#elif defined(_TIMER_DTCTRL_MASK) - || (ref == TIMER0) -#endif -#if defined(TIMER1_DTI) && (TIMER1_DTI == 1) - || (ref == TIMER1) -#endif -#if defined(TIMER2_DTI) && (TIMER2_DTI == 1) - || (ref == TIMER2) -#endif -#if defined(TIMER3_DTI) && (TIMER3_DTI == 1) - || (ref == TIMER3) -#endif -#if defined(TIMER4_DTI) && (TIMER4_DTI == 1) - || (ref == TIMER4) -#endif -#if defined(TIMER5_DTI) && (TIMER5_DTI == 1) - || (ref == TIMER5) -#endif -#if defined(TIMER6_DTI) && (TIMER6_DTI == 1) - || (ref == TIMER6) -#endif -#if defined(TIMER7_DTI) && (TIMER7_DTI == 1) - || (ref == TIMER7) -#endif -#if defined(TIMER8_DTI) && (TIMER8_DTI == 1) - || (ref == TIMER8) -#endif -#if defined(TIMER9_DTI) && (TIMER9_DTI == 1) - || (ref == TIMER9) -#endif -#if defined(WTIMER0) - || (ref == WTIMER0) -#endif - ; -} - -/***************************************************************************//** - * @brief - * Get the Max count of the timer. - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * The max count value of the timer. This is 0xFFFF for 16 bit timers - * and 0xFFFFFFFF for 32 bit timers. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) -{ - (void) ref; - -#if defined(WTIMER_PRESENT) - if ((ref == WTIMER0) -#if defined(WTIMER1) - || (ref == WTIMER1) -#endif -#if defined(WTIMER2) - || (ref == WTIMER2) -#endif -#if defined(WTIMER3) - || (ref == WTIMER3) -#endif - ) { - return 0xFFFFFFFFUL; - } -#endif /* defined(WTIMER_PRESENT) */ - -#if defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(TIMER_NUM(ref) != -1); - - return (uint32_t)((1ULL << TIMER_CNTWIDTH(TIMER_NUM(ref))) - 1); -#else - return 0xFFFFUL; -#endif /* defined(_SILICON_LABS_32B_SERIES_2) */ -} - -/***************************************************************************//** - * @brief - * Get compare/capture value for the compare/capture channel. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @return - * Current capture value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) -{ -#if defined (_TIMER_CC_CFG_MASK) - if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { - return timer->CC[ch].ICF; - } else { - return timer->CC[ch].OC; - } -#else - return timer->CC[ch].CCV; -#endif -} - -/***************************************************************************//** - * @brief - * Get the buffered compare/capture value for compare/capture channel. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @return - * Current buffered capture value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) -{ -#if defined (_TIMER_CC_CFG_MASK) - if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { - return timer->CC[ch].ICOF; - } else { - return timer->CC[ch].OCB; - } -#else - return timer->CC[ch].CCVB; -#endif -} - -/***************************************************************************//** - * @brief - * Set the compare value buffer for the compare/capture channel when operating in - * compare or PWM mode. - * - * @details - * The compare value buffer holds the value which will be written to - * TIMERn_CCx_CCV on an update event if the buffer has been updated since - * the last event. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @param[in] val - * Value to set in compare value buffer register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, - unsigned int ch, - uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (_TIMER_CC_CFG_MASK) - EFM_ASSERT(timer->EN & TIMER_EN_EN); - timer->CC[ch].OCB = val; -#else - timer->CC[ch].CCVB = val; -#endif -} - -/***************************************************************************//** - * @brief - * Set the compare value for compare/capture channel when operating in compare - * or PWM mode. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @param[in] val - * Value to set in compare value register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, - unsigned int ch, - uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (_TIMER_CC_CFG_MASK) - EFM_ASSERT(timer->EN & TIMER_EN_EN); - timer->CC[ch].OC = val; -#else - timer->CC[ch].CCV = val; -#endif -} - -/***************************************************************************//** - * @brief - * Get the TIMER counter value. - * - * @param[in] timer - * Pointer to TIMER peripheral register block. - * - * @return - * Current TIMER counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) -{ - return timer->CNT; -} - -/***************************************************************************//** - * @brief - * Set the TIMER counter value. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set counter to. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined(TIMER_HAS_SET_CLEAR) - bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; - timer->EN_SET = TIMER_EN_EN; -#endif - timer->CNT = val; -#if defined(TIMER_HAS_SET_CLEAR) - if (!enabled) { - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - } -#endif -} - -/***************************************************************************//** - * @brief - * Start/stop TIMER. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] enable - * Set to true to enable counting; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - - if (enable) { - timer->CMD = TIMER_CMD_START; - } else { - timer->CMD = TIMER_CMD_STOP; - } -} - -void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); -void TIMER_InitCC(TIMER_TypeDef *timer, - unsigned int ch, - const TIMER_InitCC_TypeDef *init); - -#if defined(_TIMER_DTCTRL_MASK) -void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); - -/***************************************************************************//** - * @brief - * Enable or disable DTI unit. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] enable - * Set to true to enable DTI unit; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) -{ -#if defined(TIMER_HAS_SET_CLEAR) - uint32_t timerEn = timer->EN & TIMER_EN_EN; - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - if (enable) { - timer->DTCFG_SET = TIMER_DTCFG_DTEN; - } else { - timer->DTCFG_CLR = TIMER_DTCFG_DTEN; - } - timer->EN_SET = timerEn; -#else - EFM_ASSERT(TIMER_SupportsDTI(timer)); - - if (enable) { - timer->DTCTRL |= TIMER_DTCTRL_DTEN; - } else { - timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; - } -#endif -} - -/***************************************************************************//** - * @brief - * Get DTI fault source flags status. - * - * @note - * Event bits are not cleared by this function. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * Status of the DTI fault source flags. Returns one or more valid - * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); - return timer->DTFAULT; -} - -/***************************************************************************//** - * @brief - * Clear DTI fault source flags. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * DTI fault source(s) to clear. Use one or more valid DTI fault - * source flags (TIMER_DTFAULT_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) - -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTFAULTC = flags; -} -#endif /* _TIMER_DTCTRL_MASK */ - -/***************************************************************************//** - * @brief - * Clear one or more pending TIMER interrupts. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * Pending TIMER interrupt source(s) to clear. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) -{ -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_CLR = flags; -#else - timer->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more TIMER interrupts. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to disable. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) -{ - timer->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more TIMER interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * TIMER_IntClear() prior to enabling the interrupt. - - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to enable. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) -{ - timer->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending TIMER interrupt flags. - * - * @note - * Event bits are not cleared by this function. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * TIMER interrupt source(s) pending. Returns one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) -{ - return timer->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending TIMER interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @note - * Interrupt flags are not cleared by this function. - * - * @return - * Pending and enabled TIMER interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn - * register (TIMERx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the TIMER module - * (TIMERx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) -{ - uint32_t ien; - - /* Store TIMER->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = timer->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return timer->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending TIMER interrupts from SW. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to set to pending. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) -{ -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_SET = flags; -#else - timer->IFS = flags; -#endif -} - -#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) -/***************************************************************************//** - * @brief - * Lock some TIMER registers to protect them from being - * modified. - * - * @details - * Refer to the reference manual for TIMER registers that will be locked. - * - * @note - * If locking the TIMER registers, they must be unlocked prior to using any - * TIMER API function that modifies TIMER registers protected by the lock. - * - * @param[in] timer - * Pointer to TIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER0 == timer); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; -} -#endif - -void TIMER_Reset(TIMER_TypeDef *timer); - -/***************************************************************************//** - * @brief - * Set the top value buffer for the timer. - * - * @details - * When top value buffer register is updated, value is loaded into - * top value register at the next wrap around. This feature is useful - * in order to update top value safely when timer is running. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set in top value buffer register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->TOPB = val; -} - -/***************************************************************************//** - * @brief - * Get the top value setting for the timer. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * Current top value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) -{ - return timer->TOP; -} - -/***************************************************************************//** - * @brief - * Set the top value for timer. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set in top value register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->TOP = val; -} - -#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) -/***************************************************************************//** - * @brief - * Unlock TIMER to enable writing to locked registers again. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER0 == timer); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; -} -#endif - -/** @} (end addtogroup timer) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ -#endif /* EM_TIMER_H */ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_TIMER_H +#define EM_TIMER_H + +#include "em_device.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup timer + * @{ + ****************************************************************************** + * @deprecated + * Deprecated macro TIMER_CH_VALID for SDID 80, new code should use TIMER_REF_CH_VALID.*/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of TIMER register block pointer reference for assert statements. */ +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) + +/** Validation of TIMER compare/capture channel number. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define TIMER_CH_VALID(ch) ((ch) < 3) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_CH_VALID(ch) _Pragma("GCC warning \"'TIMER_CH_VALID' macro is deprecated for EFR32xG1, Use TIMER_REF_CH_VALID instead\"") ((ch) < 4) +#else +#define TIMER_CH_VALID(ch) ((ch) < 4) +#endif +#else +#define TIMER_CH_VALID(ch) ((ch) < 3) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_REF_CH_VALID(ref, ch) ((ref == TIMER0) ? ((ch) < 3) : ((ch) < 4)) +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_REF_CH_VALID(ref, ch) +#else +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_CH_VALID(ch) +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Timer compare/capture mode. */ +typedef enum { +#if defined (_TIMER_CC_CTRL_MODE_MASK) + timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ +#endif +#if defined (_TIMER_CC_CFG_MODE_MASK) + timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ +#endif +} TIMER_CCMode_TypeDef; + +/** Clock select. */ +typedef enum { +#if defined (_TIMER_CTRL_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ + timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +#if defined (_TIMER_CFG_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ + timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +} TIMER_ClkSel_TypeDef; + +/** Input capture edge select. */ +typedef enum { + /** Rising edges detected. */ + timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, + + /** Falling edges detected. */ + timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, + + /** Both edges detected. */ + timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, + + /** No edge detection, leave signal as is. */ + timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE +} TIMER_Edge_TypeDef; + +/** Input capture event control. */ +typedef enum { + /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ + timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, + /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ + timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, + /** + * PRS output pulse, interrupt flag, and DMA request set on rising edge (if + * input capture edge = BOTH). + */ + timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, + /** + * PRS output pulse, interrupt flag, and DMA request set on falling edge (if + * input capture edge = BOTH). + */ + timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING +} TIMER_Event_TypeDef; + +/** Input edge action. */ +typedef enum { + /** No action taken. */ + timerInputActionNone = _TIMER_CTRL_FALLA_NONE, + + /** Start counter without reload. */ + timerInputActionStart = _TIMER_CTRL_FALLA_START, + + /** Stop counter without reload. */ + timerInputActionStop = _TIMER_CTRL_FALLA_STOP, + + /** Reload and start counter. */ + timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART +} TIMER_InputAction_TypeDef; + +/** Timer mode. */ +typedef enum { +#if defined (_TIMER_CTRL_MODE_MASK) + timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ +#endif +#if defined (_TIMER_CFG_MODE_MASK) + timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ +#endif +} TIMER_Mode_TypeDef; + +/** Compare/capture output action. */ +typedef enum { + /** No action. */ + timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, + + /** Toggle on event. */ + timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, + + /** Clear on event. */ + timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, + + /** Set on event. */ + timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET +} TIMER_OutputAction_TypeDef; + +/** Prescaler. */ +typedef enum { +#if defined (_TIMER_CTRL_PRESC_MASK) + timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +#if defined (_TIMER_CFG_PRESC_MASK) + timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +} TIMER_Prescale_TypeDef; + +/** Peripheral Reflex System signal. */ +typedef uint8_t TIMER_PRSSEL_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector. New code should use an integer instead of + * using these deprecated enum values. */ +#define timerPRSSELCh0 0UL +#define timerPRSSELCh1 1UL +#define timerPRSSELCh2 2UL +#define timerPRSSELCh3 3UL +#define timerPRSSELCh4 4UL +#define timerPRSSELCh5 5UL +#define timerPRSSELCh6 6UL +#define timerPRSSELCh7 7UL +#define timerPRSSELCh8 8UL +#define timerPRSSELCh9 9UL +#define timerPRSSELCh10 10UL +#define timerPRSSELCh11 11UL +/** @endcond */ + +#if defined (_TIMER_CC_CFG_INSEL_MASK) +/** PRS input type */ +typedef enum { + timerPrsInputNone = 0x0, /**< No PRS input. */ + timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, /**< Synchronous PRS selected. */ + timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, /**< Asynchronous level PRS selected. */ + timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, /**< Asynchronous pulse PRS selected. */ +} TIMER_PrsInput_TypeDef; +#endif + +#if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) +/** DT (Dead Time) Fault Actions. */ +typedef enum { +#if defined(_TIMER_DTFC_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +#if defined(_TIMER_DTFCFG_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +} TIMER_DtiFaultAction_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** TIMER initialization structure. */ +typedef struct { + /** Start counting when initialization completed. */ + bool enable; + + /** Counter shall keep running during debug halt. */ + bool debugRun; + + /** Prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** Clock selection. */ + TIMER_ClkSel_TypeDef clkSel; + +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) + /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ + bool count2x; + + /** ATI (Always Track Inputs) makes CCPOL always track + * the polarity of the inputs. */ + bool ati; + + /** Reload-Start Sets COIST + * When enabled, compare output is set to COIST value on a Reload-Start event. */ + bool rssCoist; +#endif + + /** Action on falling input edge. */ + TIMER_InputAction_TypeDef fallAction; + + /** Action on rising input edge. */ + TIMER_InputAction_TypeDef riseAction; + + /** Counting mode. */ + TIMER_Mode_TypeDef mode; + + /** DMA request clear on active. */ + bool dmaClrAct; + + /** Select X2 or X4 quadrature decode mode (if used). */ + bool quadModeX4; + + /** Determines if only counting up or down once. */ + bool oneShot; + + /** Timer can be start/stop/reload by other timers. */ + bool sync; + +#if defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT) + /** Disable ability of timer to start/stop/reload other timers that have their SYNC bit set. */ + bool disSyncOut; +#endif +} TIMER_Init_TypeDef; + +/** Default configuration for TIMER initialization structure. */ +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) +#if (defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT)) +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false, /* Not started/stopped/reloaded by other timers. */ \ + false /* Disable ability to start/stop/reload other timers. */ \ + } +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif + +/** PRS Output configuration. */ +typedef enum { + timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ + timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ + timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ +} TIMER_PrsOutput_t; + +/** TIMER compare/capture initialization structure. */ +typedef struct { + /** Input capture event control. */ + TIMER_Event_TypeDef eventCtrl; + + /** Input capture edge select. */ + TIMER_Edge_TypeDef edge; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p prsInput + * is enabled. + */ + TIMER_PRSSEL_TypeDef prsSel; + + /** Counter underflow output action. */ + TIMER_OutputAction_TypeDef cufoa; + + /** Counter overflow output action. */ + TIMER_OutputAction_TypeDef cofoa; + + /** Counter match output action. */ + TIMER_OutputAction_TypeDef cmoa; + + /** Compare/capture channel mode. */ + TIMER_CCMode_TypeDef mode; + + /** Enable digital filter. */ + bool filter; + + /** Select TIMERnCCx (false) or PRS input (true). */ + bool prsInput; + + /** + * Compare output initial state. Only used in Output Compare and PWM mode. + * When true, the compare/PWM output is set high when the counter is + * disabled. When counting resumes, this value will represent the initial + * value for the compare/PWM output. If the bit is cleared, the output + * will be cleared when the counter is disabled. + */ + bool coist; + + /** Invert output from compare/capture channel. */ + bool outInvert; + + /** + * PRS output configuration. PRS output from a timer can either be a + * pulse output or a level output that follows the CC out value. + */ + TIMER_PrsOutput_t prsOutput; + +#if defined(_TIMER_CC_CFG_INSEL_MASK) + /** When PRS input is used this field is used to configure the type of + * PRS input. */ + TIMER_PrsInput_TypeDef prsInputType; +#endif +} TIMER_InitCC_TypeDef; + +/** Default configuration for TIMER compare/capture initialization structure. */ +#if defined(_TIMER_CC_CFG_INSEL_MASK) +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + timerPrsInputNone /* No PRS input, so input type is none. */ \ + } +#else +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + } +#endif + +#if defined(_TIMER_DTCTRL_MASK) +/** TIMER Dead Time Insertion (DTI) initialization structure. */ +typedef struct { + /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ + bool enable; + + /** DTI Output Polarity. */ + bool activeLowOut; + + /** DTI Complementary Output Invert. */ + bool invertComplementaryOut; + + /** Enable Automatic Start-up functionality (when debugger exits). */ + bool autoRestart; + + /** Enable/disable PRS as DTI input. */ + bool enablePrsSource; + + /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource + is enabled. */ + TIMER_PRSSEL_TypeDef prsSel; + + /** DTI prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** DTI Rise Time */ + unsigned int riseTime; + + /** DTI Fall Time */ + unsigned int fallTime; + + /** DTI outputs enable bit mask, consisting of one bit per DTI + output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. + This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags + (defined in \_timer.h) OR'ed together. */ + uint32_t outputsEnableMask; + + /** Enable core lockup as a fault source. */ + bool enableFaultSourceCoreLockup; + + /** Enable debugger as a fault source. */ + bool enableFaultSourceDebugger; + + /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ + bool enableFaultSourcePrsSel0; + + /** Select which PRS signal to be PRS fault source 0. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel0; + + /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ + bool enableFaultSourcePrsSel1; + + /** Select which PRS signal to be PRS fault source 1. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel1; + + /** Fault Action */ + TIMER_DtiFaultAction_TypeDef faultAction; +} TIMER_InitDTI_TypeDef; + +/** Default configuration for TIMER DTI initialization structure. */ +#define TIMER_INITDTI_DEFAULT \ + { \ + true, /* Enable the DTI. */ \ + false, /* CC[0|1|2] outputs are active high. */ \ + false, /* CDTI[0|1|2] outputs are not inverted. */ \ + false, /* No auto restart when debugger exits. */ \ + false, /* No PRS source selected. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerPrescale1, /* No prescaling. */ \ + 0, /* No rise time. */ \ + 0, /* No fall time. */ \ + TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ + true, /* Enable core lockup as fault source. */ \ + true, /* Enable debugger as fault source. */ \ + false, /* Disable PRS fault source 0. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + false, /* Disable PRS fault source 1. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerDtiFaultActionInactive, /* No fault action. */ \ + } +#endif /* _TIMER_DTCTRL_MASK */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(TIMER_STATUS_SYNCBUSY) +void TIMER_SyncWait(TIMER_TypeDef * timer); +#endif + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(TIMER4) + || (ref == TIMER4) +#endif +#if defined(TIMER5) + || (ref == TIMER5) +#endif +#if defined(TIMER6) + || (ref == TIMER6) +#endif +#if defined(TIMER7) + || (ref == TIMER7) +#endif +#if defined(TIMER8) + || (ref == TIMER8) +#endif +#if defined(TIMER9) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Check whether the TIMER is valid and supports Dead Timer Insertion (DTI). + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer that supports DTI, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_SupportsDTI(const TIMER_TypeDef *ref) +{ + (void) ref; + + return 0 +#if defined(TIMER0_DTI) +#if (TIMER0_DTI == 1) + || (ref == TIMER0) +#endif +#elif defined(_TIMER_DTCTRL_MASK) + || (ref == TIMER0) +#endif +#if defined(TIMER1_DTI) && (TIMER1_DTI == 1) + || (ref == TIMER1) +#endif +#if defined(TIMER2_DTI) && (TIMER2_DTI == 1) + || (ref == TIMER2) +#endif +#if defined(TIMER3_DTI) && (TIMER3_DTI == 1) + || (ref == TIMER3) +#endif +#if defined(TIMER4_DTI) && (TIMER4_DTI == 1) + || (ref == TIMER4) +#endif +#if defined(TIMER5_DTI) && (TIMER5_DTI == 1) + || (ref == TIMER5) +#endif +#if defined(TIMER6_DTI) && (TIMER6_DTI == 1) + || (ref == TIMER6) +#endif +#if defined(TIMER7_DTI) && (TIMER7_DTI == 1) + || (ref == TIMER7) +#endif +#if defined(TIMER8_DTI) && (TIMER8_DTI == 1) + || (ref == TIMER8) +#endif +#if defined(TIMER9_DTI) && (TIMER9_DTI == 1) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ + (void) ref; + +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ) { + return 0xFFFFFFFFUL; + } +#endif /* defined(WTIMER_PRESENT) */ + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(TIMER_NUM(ref) != -1); + + return (uint32_t)((1ULL << TIMER_CNTWIDTH(TIMER_NUM(ref))) - 1); +#else + return 0xFFFFUL; +#endif /* defined(_SILICON_LABS_32B_SERIES_2) */ +} + +/***************************************************************************//** + * @brief + * Get compare/capture value for the compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICF; + } else { + return timer->CC[ch].OC; + } +#else + return timer->CC[ch].CCV; +#endif +} + +/***************************************************************************//** + * @brief + * Get the buffered compare/capture value for compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current buffered capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICOF; + } else { + return timer->CC[ch].OCB; + } +#else + return timer->CC[ch].CCVB; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value buffer for the compare/capture channel when operating in + * compare or PWM mode. + * + * @details + * The compare value buffer holds the value which will be written to + * TIMERn_CCx_CCV on an update event if the buffer has been updated since + * the last event. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OCB = val; +#else + timer->CC[ch].CCVB = val; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value for compare/capture channel when operating in compare + * or PWM mode. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OC = val; +#else + timer->CC[ch].CCV = val; +#endif +} + +/***************************************************************************//** + * @brief + * Get the TIMER counter value. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * Current TIMER counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) +{ + return timer->CNT; +} + +/***************************************************************************//** + * @brief + * Set the TIMER counter value. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set counter to. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined(TIMER_HAS_SET_CLEAR) + bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; + timer->EN_SET = TIMER_EN_EN; +#endif + timer->CNT = val; +#if defined(TIMER_HAS_SET_CLEAR) + if (!enabled) { + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Start/stop TIMER. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable counting; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + + if (enable) { + timer->CMD = TIMER_CMD_START; + } else { + timer->CMD = TIMER_CMD_STOP; + } +} + +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init); + +#if defined(_TIMER_DTCTRL_MASK) +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); + +/***************************************************************************//** + * @brief + * Enable or disable DTI unit. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable DTI unit; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) +{ +#if defined(TIMER_HAS_SET_CLEAR) + uint32_t timerEn = timer->EN & TIMER_EN_EN; + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + if (enable) { + timer->DTCFG_SET = TIMER_DTCFG_DTEN; + } else { + timer->DTCFG_CLR = TIMER_DTCFG_DTEN; + } + timer->EN_SET = timerEn; +#else + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + if (enable) { + timer->DTCTRL |= TIMER_DTCTRL_DTEN; + } else { + timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Get DTI fault source flags status. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Status of the DTI fault source flags. Returns one or more valid + * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + return timer->DTFAULT; +} + +/***************************************************************************//** + * @brief + * Clear DTI fault source flags. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * DTI fault source(s) to clear. Use one or more valid DTI fault + * source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) + +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTFAULTC = flags; +} +#endif /* _TIMER_DTCTRL_MASK */ + +/***************************************************************************//** + * @brief + * Clear one or more pending TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * Pending TIMER interrupt source(s) to clear. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = flags; +#else + timer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to disable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more TIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * TIMER_IntClear() prior to enabling the interrupt. + + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to enable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending TIMER interrupt flags. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * TIMER interrupt source(s) pending. Returns one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) +{ + return timer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending TIMER interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled TIMER interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn + * register (TIMERx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the TIMER module + * (TIMERx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) +{ + uint32_t ien; + + /* Store TIMER->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = timer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return timer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending TIMER interrupts from SW. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_SET = flags; +#else + timer->IFS = flags; +#endif +} + +#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) +/***************************************************************************//** + * @brief + * Lock some TIMER registers to protect them from being + * modified. + * + * @details + * Refer to the reference manual for TIMER registers that will be locked. + * + * @note + * If locking the TIMER registers, they must be unlocked prior to using any + * TIMER API function that modifies TIMER registers protected by the lock. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; +} +#endif + +void TIMER_Reset(TIMER_TypeDef *timer); + +/***************************************************************************//** + * @brief + * Set the top value buffer for the timer. + * + * @details + * When top value buffer register is updated, value is loaded into + * top value register at the next wrap around. This feature is useful + * in order to update top value safely when timer is running. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOPB = val; +} + +/***************************************************************************//** + * @brief + * Get the top value setting for the timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Current top value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) +{ + return timer->TOP; +} + +/***************************************************************************//** + * @brief + * Set the top value for timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOP = val; +} + +#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) +/***************************************************************************//** + * @brief + * Unlock TIMER to enable writing to locked registers again. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; +} +#endif + +/** @} (end addtogroup timer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ +#endif /* EM_TIMER_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h index c4c0305..170b7a9 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h @@ -1,1093 +1,1093 @@ -/***************************************************************************//** - * @file - * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) - * peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_USART_H -#define EM_USART_H - -#include "em_device.h" -#if defined(USART_COUNT) && (USART_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup usart USART - Synchronous/Asynchronous Serial - * @brief Universal Synchronous/Asynchronous Receiver/Transmitter - * Peripheral API - * @details - * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) - * is a very flexible serial I/O module. It supports full duplex asynchronous UART - * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface - * with ISO7816 Smart-Cards, and IrDA devices. - * - * The USART has a wide selection of operating modes, frame formats, and baud rates. - * All features are supported through the API of this module. - * - * Triple buffering and DMA support makes high data-rates possible with minimal - * CPU intervention. It is possible to transmit and receive large frames while - * the MCU remains in EM1 Sleep. - * - * This module does not support DMA configuration. The UARTDRV and SPIDRV drivers - * provide full support for DMA and more. - * - * The following steps are necessary for basic operation: - * - * Clock enable: - * @include em_usart_clock_enable.c - * - * To initialize the USART for asynchronous operation (e.g., UART): - * @include em_usart_init_async.c - * - * To initialize the USART for synchronous operation (e.g., SPI): - * @include em_usart_init_sync.c - * - * After pins are assigned for the application/board, enable pins at the - * desired location. Available locations can be obtained from the Pin Definitions - * section in the data sheet. - * @if DOXYDOC_P1_DEVICE - * @include em_usart_route_p1.c - * @note UART hardware flow control is not directly supported in hardware on - * _SILICON_LABS_32B_SERIES_0 parts. - * @endif - * @if DOXYDOC_P2_DEVICE - * @include em_usart_route_p2.c - * @endif - * @note UARTDRV supports all types of UART flow control. Software assisted - * hardware flow control is available for parts without true UART hardware - * flow control. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Databit selection. */ -typedef enum { - usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ - usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ - usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ - usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ - usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ - usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ - usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ - usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ - usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ - usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ - usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ - usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ - usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ -} USART_Databits_TypeDef; - -/** Enable selection. */ -typedef enum { - /** Disable both receiver and transmitter. */ - usartDisable = 0x0, - - /** Enable receiver only, transmitter disabled. */ - usartEnableRx = USART_CMD_RXEN, - - /** Enable transmitter only, receiver disabled. */ - usartEnableTx = USART_CMD_TXEN, - - /** Enable both receiver and transmitter. */ - usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) -} USART_Enable_TypeDef; - -/** Oversampling selection, used for asynchronous operation. */ -typedef enum { - usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ - usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ - usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ - usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ -} USART_OVS_TypeDef; - -/** Parity selection, mainly used for asynchronous operation. */ -typedef enum { - usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ - usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ - usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ -} USART_Parity_TypeDef; - -/** Stop bits selection, used for asynchronous operation. */ -typedef enum { - usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ - usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ - usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ - usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ -} USART_Stopbits_TypeDef; - -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) -/** Hardware Flow Control Selection. */ -typedef enum { - /** No hardware flow control. */ - usartHwFlowControlNone = 0, - /** CTS signal is enabled for TX flow control. */ - usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, - /** RTS signal is enabled for RX flow control. */ - usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, - /** CTS and RTS signals are enabled for TX and RX flow control. */ - usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, -} USART_HwFlowControl_TypeDef; - -#elif defined(USART_CTRLX_CTSEN) -/** Hardware Flow Control Selection. */ -typedef enum { - /** No hardware flow control. */ - usartHwFlowControlNone = 0, - /** CTS signal is enabled for TX flow control. */ - usartHwFlowControlCts, - /** RTS signal is enabled for RX flow control. */ - usartHwFlowControlRts, - /** CTS and RTS signals are enabled for TX and RX flow control. */ - usartHwFlowControlCtsAndRts -} USART_HwFlowControl_TypeDef; -#endif - -/** Clock polarity/phase mode. */ -typedef enum { - /** Clock idle low, sample on rising edge. */ - usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, - - /** Clock idle low, sample on falling edge. */ - usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, - - /** Clock idle high, sample on falling edge. */ - usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, - - /** Clock idle high, sample on rising edge. */ - usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING -} USART_ClockMode_TypeDef; - -/** Pulse width selection for IrDA mode. */ -typedef enum { - /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ - usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, - - /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ - usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, - - /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ - usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, - - /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ - usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR -} USART_IrDAPw_Typedef; - -/** PRS Channel type */ -typedef uint8_t USART_PRS_Channel_t; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** Deprecated PRS channel selector value. - * New code should use an integer instead. */ -#define usartIrDAPrsCh0 0U -#define usartIrDAPrsCh1 1U -#define usartIrDAPrsCh2 2U -#define usartIrDAPrsCh3 3U -#define usartIrDAPrsCh4 4U -#define usartIrDAPrsCh5 5U -#define usartIrDAPrsCh6 6U -#define usartIrDAPrsCh7 7U -#define usartPrsRxCh0 0U -#define usartPrsRxCh1 1U -#define usartPrsRxCh2 2U -#define usartPrsRxCh3 3U -#define usartPrsRxCh4 4U -#define usartPrsRxCh5 5U -#define usartPrsRxCh6 6U -#define usartPrsRxCh7 7U -#define usartPrsRxCh8 8U -#define usartPrsRxCh9 9U -#define usartPrsRxCh10 10U -#define usartPrsRxCh11 11U -#define usartPrsTriggerCh0 0U -#define usartPrsTriggerCh1 1U -#define usartPrsTriggerCh2 2U -#define usartPrsTriggerCh3 3U -#define usartPrsTriggerCh4 4U -#define usartPrsTriggerCh5 5U -#define usartPrsTriggerCh6 6U -#define usartPrsTriggerCh7 7U -/** @endcond */ - -#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) -/** I2S format selection. */ -typedef enum { - usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ - usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ - usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ - usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ - usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ - usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ - usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ - usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ -} USART_I2sFormat_TypeDef; - -/** I2S frame data justify. */ -typedef enum { - usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ - usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ -} USART_I2sJustify_TypeDef; - -#elif defined(_USART_I2SCTRL_MASK) -/** I2S format selection. */ -typedef enum { - usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ - usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ - usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ - usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ - usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ - usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ - usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ - usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ -} USART_I2sFormat_TypeDef; - -/** I2S frame data justify. */ -typedef enum { - usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ - usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ -} USART_I2sJustify_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Asynchronous mode initialization structure. */ -typedef struct { - /** Specifies whether TX and/or RX is enabled when initialization is completed. */ - USART_Enable_TypeDef enable; - - /** - * USART/UART reference clock assumed when configuring baud rate setup. - * Set to 0 to use the currently configured reference clock. - */ - uint32_t refFreq; - - /** Desired baud rate. */ - uint32_t baudrate; - - /** Oversampling used. */ - USART_OVS_TypeDef oversampling; - - /** Number of data bits in frame. Notice that UART modules only support 8 or - * 9 data bits. */ - USART_Databits_TypeDef databits; - - /** Parity mode to use. */ - USART_Parity_TypeDef parity; - - /** Number of stop bits to use. */ - USART_Stopbits_TypeDef stopbits; - -#if !defined(_EFM32_GECKO_FAMILY) - /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ - bool mvdis; - - /** Enable USART Rx via PRS. */ - bool prsRxEnable; - - /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ - USART_PRS_Channel_t prsRxCh; -#endif - - /** Auto CS enabling. */ - bool autoCsEnable; - - /** Enable CS invert. By default, chip select is active low. - * Set to true to make chip select active high. */ - bool csInv; - -#if (_SILICON_LABS_32B_SERIES > 0) - /** Auto CS hold time in baud cycles. */ - uint8_t autoCsHold; - - /** Auto CS setup time in baud cycles. */ - uint8_t autoCsSetup; - - /** Hardware flow control mode. */ - USART_HwFlowControl_TypeDef hwFlowControl; -#endif -} USART_InitAsync_TypeDef; - -/** USART PRS trigger enable. */ -typedef struct { -#if defined(USART_TRIGCTRL_AUTOTXTEN) - /** Enable AUTOTX. */ - bool autoTxTriggerEnable; -#endif - /** Trigger receive via PRS channel. */ - bool rxTriggerEnable; - /** Trigger transmit via PRS channel. */ - bool txTriggerEnable; - /** PRS channel to be used to trigger auto transmission. */ - USART_PRS_Channel_t prsTriggerChannel; -} USART_PrsTriggerInit_TypeDef; - -/** Default configuration for USART asynchronous initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Async struct for the EFM32G device */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Auto CS functionality enable/disable switch. */ \ - false, /* No CS invert. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Async struct for Series 0 devices */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch. */ \ - false, /* No CS invert. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Async struct for Series 1 and Series 2 devices */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles. */ \ - 0, /* Auto CS Setup cycles. */ \ - usartHwFlowControlNone /* No HW flow control. */ \ - } -#endif - -/** Default configuration for USART PRS triggering structure. */ -#if defined(USART_TRIGCTRL_AUTOTXTEN) -#define USART_INITPRSTRIGGER_DEFAULT \ - { \ - false, /* Do not enable autoTX triggering. */ \ - false, /* Do not enable receive triggering. */ \ - false, /* Do not enable transmit triggering. */ \ - 0 /* Set default channel to zero. */ \ - } -#else -#define USART_INITPRSTRIGGER_DEFAULT \ - { \ - false, /* Do not enable receive triggering. */ \ - false, /* Do not enable transmit triggering. */ \ - 0 /* Set default channel to zero. */ \ - } -#endif - -/** Synchronous mode initialization structure. */ -typedef struct { - /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ - USART_Enable_TypeDef enable; - - /** - * USART/UART reference clock assumed when configuring baud rate setup. - * Set to 0 to use the currently configured reference clock. - */ - uint32_t refFreq; - - /** Desired baud rate. */ - uint32_t baudrate; - - /** Number of data bits in frame. */ - USART_Databits_TypeDef databits; - - /** Select if to operate in master or slave mode. */ - bool master; - - /** Select if to send most or least significant bit first. */ - bool msbf; - - /** Clock polarity/phase mode. */ - USART_ClockMode_TypeDef clockMode; - -#if !defined(_EFM32_GECKO_FAMILY) - /** Enable USART Rx via PRS. */ - bool prsRxEnable; - - /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ - USART_PRS_Channel_t prsRxCh; -#endif - -#if defined(USART_TRIGCTRL_AUTOTXTEN) - /** Enable AUTOTX mode. Transmits as long as RX is not full. - * Generates underflows if TX is empty. */ - bool autoTx; -#endif - - /** Auto CS enabling */ - bool autoCsEnable; - - /** Enable CS invert. By default, chip select is active low. - * Set to true to make chip select active high. */ - bool csInv; - -#if defined(_USART_TIMING_CSHOLD_MASK) - /** Auto CS hold time in baud cycles */ - uint8_t autoCsHold; - - /** Auto CS setup time in baud cycles */ - uint8_t autoCsSetup; -#endif -} USART_InitSync_TypeDef; - -/** Default configuration for USART sync initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Sync configuration for EFM32G devices. */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 data bits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Sync configuration for series 0 devices. */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 data bits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Sync configuration for series 2 devices */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 databits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles. */ \ - 0 /* Auto CS Setup cycles. */ \ - } -#endif - -/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ -typedef struct { - /** General Asynchronous initialization structure. */ - USART_InitAsync_TypeDef async; - - /** Set to invert Rx signal before IrDA demodulator. */ - bool irRxInv; - - /** Set to enable filter on IrDA demodulator. */ - bool irFilt; - - /** Configure the pulse width generated by the IrDA modulator as a fraction - * of the configured USART bit period. */ - USART_IrDAPw_Typedef irPw; - -#if defined(USART_IRCTRL_IRPRSEN) - /** Enable the PRS channel selected by irPrsSel as input to IrDA module - * instead of TX. */ - bool irPrsEn; - - /** PRS can be used as input to the pulse modulator instead of TX. - * This value selects the channel to use. */ - USART_PRS_Channel_t irPrsSel; -#endif -} USART_InitIrDA_TypeDef; - -/** Default configuration for IrDA mode initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART IrDA struct for the EFM32G device */ -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART IrDA struct for Series 0 devices */ -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART IrDA struct for Series 1 and Series 2 devices */ -#if defined(USART_IRCTRL_IRPRSEN) -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0, /* Auto CS Setup cycles */ \ - usartHwFlowControlNone /* No HW flow control */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#else -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0, /* Auto CS Setup cycles */ \ - usartHwFlowControlNone /* No HW flow control */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE /* Pulse width is set to ONE. */ \ - } -#endif -#endif - -#if defined(_USART_I2SCTRL_MASK) -/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ -typedef struct { - /** General Synchronous initialization structure. */ - USART_InitSync_TypeDef sync; - - /** I2S mode. */ - USART_I2sFormat_TypeDef format; - - /** Delay on I2S data. Set to add a one-cycle delay between a transition - * on the word-clock and the start of the I2S word. - * Should be set for standard I2S format. */ - bool delay; - - /** Separate DMA Request For Left/Right Data. */ - bool dmaSplit; - - /** Justification of I2S data within the frame. */ - USART_I2sJustify_TypeDef justify; - - /** Stereo or Mono, set to true for mono. */ - bool mono; -} USART_InitI2s_TypeDef; - -/** Default configuration for I2S mode initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Sync configuration for EFM32G devices. */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Master mode. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Sync configuration for series 0 devices. */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Master mode. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Sync configuration for series 2 devices */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnableTx, /* Enable TX when init completed. */ \ - 0, /* Use current configured reference clock for configuring baudrate. */ \ - 1000000, /* Baudrate 1M bits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Operate as I2S master. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Don't enable USARTRx via PRS. */ \ - usartPrsRxCh0, /* PRS channel selection (dummy). */ \ - false, /* Disable AUTOTX mode. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0 /* Auto CS Setup cycles */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#endif -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void USART_BaudrateAsyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate, - USART_OVS_TypeDef ovs); -uint32_t USART_BaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - bool syncmode, - USART_OVS_TypeDef ovs); -uint32_t USART_BaudrateGet(USART_TypeDef *usart); -void USART_BaudrateSyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate); -void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); - -void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); -void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); -void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); - -#if defined(_USART_I2SCTRL_MASK) -void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); -#endif -void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending USART interrupts. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * Pending USART/UART interrupt source(s) to clear. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) -{ -#if defined (USART_HAS_SET_CLEAR) - usart->IF_CLR = flags; -#else - usart->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more USART interrupts. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to disable. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) -{ - usart->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more USART interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * USART_IntClear() prior to enabling the interrupt. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to enable. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) -{ - usart->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending USART interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @return - * USART/UART interrupt source(s) pending. Returns one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) -{ - return usart->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending USART interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled USART interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn - * register (USARTx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the USART module - * (USARTx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) -{ - uint32_t ien; - - /* Store USARTx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = usart->IEN; - - /* Bitwise AND of pending and enabled interrupts. */ - return usart->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending USART interrupts from SW. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to set to pending. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) -{ -#if defined (USART_HAS_SET_CLEAR) - usart->IF_SET = flags; -#else - usart->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get USART STATUS register. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @return - * STATUS register value. - * - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) -{ - return usart->STATUS; -} - -void USART_Reset(USART_TypeDef *usart); -uint8_t USART_Rx(USART_TypeDef *usart); -uint16_t USART_RxDouble(USART_TypeDef *usart); -uint32_t USART_RxDoubleExt(USART_TypeDef *usart); -uint16_t USART_RxExt(USART_TypeDef *usart); - -/***************************************************************************//** - * @brief - * Receive one 4-8 bit frame, (or part of 10-16 bit frame). - * - * @details - * This function is used to quickly receive one 4-8 bits frame by reading the - * RXDATA register directly, without checking the STATUS register for the - * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, - * i.e., waiting is superfluous, in order to quickly read the received data. - * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. - * - * @note - * Because this function does not check whether the RXDATA register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a - * better choice if the validity of the RXDATA register is not certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) -{ - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Receive two 4-8 bit frames, or one 10-16 bit frame. - * - * @details - * This function is used to quickly receive one 10-16 bits frame or two 4-8 - * bit frames by reading the RXDOUBLE register directly, without checking - * the STATUS register for the RXDATAV flag. This can be useful from the - * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to - * quickly read the received data. - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() - * for reception of two 9 bit frames. - * - * @note - * Because this function does not check whether the RXDOUBLE register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is - * normally a better choice if the validity of the RXDOUBLE register is not - * certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) -{ - return (uint16_t)usart->RXDOUBLE; -} - -/***************************************************************************//** - * @brief - * Receive two 4-9 bit frames, or one 10-16 bit frame with extended - * information. - * - * @details - * This function is used to quickly receive one 10-16 bits frame or two 4-9 - * bit frames by reading the RXDOUBLEX register directly, without checking - * the STATUS register for the RXDATAV flag. This can be useful from the - * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to - * quickly read the received data. - * - * @note - * Because this function does not check whether the RXDOUBLEX register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is - * normally a better choice if the validity of the RXDOUBLEX register is not - * certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) -{ - return usart->RXDOUBLEX; -} - -/***************************************************************************//** - * @brief - * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended - * information. - * - * @details - * This function is used to quickly receive one 4-9 bit frame, (or part of - * 10-16 bit frame) with extended information by reading the RXDATAX register - * directly, without checking the STATUS register for the RXDATAV flag. This - * can be useful from the RXDATAV interrupt handler, i.e., waiting is - * superfluous, in order to quickly read the received data. - * - * @note - * Because this function does not check whether the RXDATAX register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally - * a better choice if the validity of the RXDATAX register is not certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) -{ - return (uint16_t)usart->RXDATAX; -} - -uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); -void USART_Tx(USART_TypeDef *usart, uint8_t data); -void USART_TxDouble(USART_TypeDef *usart, uint16_t data); -void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); -void USART_TxExt(USART_TypeDef *usart, uint16_t data); - -/** @} (end addtogroup usart) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ -#endif /* EM_USART_H */ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_USART_H +#define EM_USART_H + +#include "em_device.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup usart USART - Synchronous/Asynchronous Serial + * @brief Universal Synchronous/Asynchronous Receiver/Transmitter + * Peripheral API + * @details + * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) + * is a very flexible serial I/O module. It supports full duplex asynchronous UART + * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface + * with ISO7816 Smart-Cards, and IrDA devices. + * + * The USART has a wide selection of operating modes, frame formats, and baud rates. + * All features are supported through the API of this module. + * + * Triple buffering and DMA support makes high data-rates possible with minimal + * CPU intervention. It is possible to transmit and receive large frames while + * the MCU remains in EM1 Sleep. + * + * This module does not support DMA configuration. The UARTDRV and SPIDRV drivers + * provide full support for DMA and more. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @include em_usart_clock_enable.c + * + * To initialize the USART for asynchronous operation (e.g., UART): + * @include em_usart_init_async.c + * + * To initialize the USART for synchronous operation (e.g., SPI): + * @include em_usart_init_sync.c + * + * After pins are assigned for the application/board, enable pins at the + * desired location. Available locations can be obtained from the Pin Definitions + * section in the data sheet. + * @if DOXYDOC_P1_DEVICE + * @include em_usart_route_p1.c + * @note UART hardware flow control is not directly supported in hardware on + * _SILICON_LABS_32B_SERIES_0 parts. + * @endif + * @if DOXYDOC_P2_DEVICE + * @include em_usart_route_p2.c + * @endif + * @note UARTDRV supports all types of UART flow control. Software assisted + * hardware flow control is available for parts without true UART hardware + * flow control. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Databit selection. */ +typedef enum { + usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ + usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ + usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ + usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ + usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ + usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ + usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ + usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ + usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ + usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ + usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ + usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ + usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ +} USART_Databits_TypeDef; + +/** Enable selection. */ +typedef enum { + /** Disable both receiver and transmitter. */ + usartDisable = 0x0, + + /** Enable receiver only, transmitter disabled. */ + usartEnableRx = USART_CMD_RXEN, + + /** Enable transmitter only, receiver disabled. */ + usartEnableTx = USART_CMD_TXEN, + + /** Enable both receiver and transmitter. */ + usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) +} USART_Enable_TypeDef; + +/** Oversampling selection, used for asynchronous operation. */ +typedef enum { + usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ + usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ + usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ + usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ +} USART_OVS_TypeDef; + +/** Parity selection, mainly used for asynchronous operation. */ +typedef enum { + usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ + usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ + usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ +} USART_Parity_TypeDef; + +/** Stop bits selection, used for asynchronous operation. */ +typedef enum { + usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ + usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ + usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ + usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ +} USART_Stopbits_TypeDef; + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, +} USART_HwFlowControl_TypeDef; + +#elif defined(USART_CTRLX_CTSEN) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts +} USART_HwFlowControl_TypeDef; +#endif + +/** Clock polarity/phase mode. */ +typedef enum { + /** Clock idle low, sample on rising edge. */ + usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle low, sample on falling edge. */ + usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, + + /** Clock idle high, sample on falling edge. */ + usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle high, sample on rising edge. */ + usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING +} USART_ClockMode_TypeDef; + +/** Pulse width selection for IrDA mode. */ +typedef enum { + /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ + usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, + + /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ + usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, + + /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ + usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, + + /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ + usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR +} USART_IrDAPw_Typedef; + +/** PRS Channel type */ +typedef uint8_t USART_PRS_Channel_t; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector value. + * New code should use an integer instead. */ +#define usartIrDAPrsCh0 0U +#define usartIrDAPrsCh1 1U +#define usartIrDAPrsCh2 2U +#define usartIrDAPrsCh3 3U +#define usartIrDAPrsCh4 4U +#define usartIrDAPrsCh5 5U +#define usartIrDAPrsCh6 6U +#define usartIrDAPrsCh7 7U +#define usartPrsRxCh0 0U +#define usartPrsRxCh1 1U +#define usartPrsRxCh2 2U +#define usartPrsRxCh3 3U +#define usartPrsRxCh4 4U +#define usartPrsRxCh5 5U +#define usartPrsRxCh6 6U +#define usartPrsRxCh7 7U +#define usartPrsRxCh8 8U +#define usartPrsRxCh9 9U +#define usartPrsRxCh10 10U +#define usartPrsRxCh11 11U +#define usartPrsTriggerCh0 0U +#define usartPrsTriggerCh1 1U +#define usartPrsTriggerCh2 2U +#define usartPrsTriggerCh3 3U +#define usartPrsTriggerCh4 4U +#define usartPrsTriggerCh5 5U +#define usartPrsTriggerCh6 6U +#define usartPrsTriggerCh7 7U +/** @endcond */ + +#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ + usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ + usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ + usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ + usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ + usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ + usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ + usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ + usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ +} USART_I2sJustify_TypeDef; + +#elif defined(_USART_I2SCTRL_MASK) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ + usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ + usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ + usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ + usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ + usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ + usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ + usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ + usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ +} USART_I2sJustify_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Asynchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX is enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Oversampling used. */ + USART_OVS_TypeDef oversampling; + + /** Number of data bits in frame. Notice that UART modules only support 8 or + * 9 data bits. */ + USART_Databits_TypeDef databits; + + /** Parity mode to use. */ + USART_Parity_TypeDef parity; + + /** Number of stop bits to use. */ + USART_Stopbits_TypeDef stopbits; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ + bool mvdis; + + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + + /** Auto CS enabling. */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if (_SILICON_LABS_32B_SERIES > 0) + /** Auto CS hold time in baud cycles. */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles. */ + uint8_t autoCsSetup; + + /** Hardware flow control mode. */ + USART_HwFlowControl_TypeDef hwFlowControl; +#endif +} USART_InitAsync_TypeDef; + +/** USART PRS trigger enable. */ +typedef struct { +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX. */ + bool autoTxTriggerEnable; +#endif + /** Trigger receive via PRS channel. */ + bool rxTriggerEnable; + /** Trigger transmit via PRS channel. */ + bool txTriggerEnable; + /** PRS channel to be used to trigger auto transmission. */ + USART_PRS_Channel_t prsTriggerChannel; +} USART_PrsTriggerInit_TypeDef; + +/** Default configuration for USART asynchronous initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Async struct for the EFM32G device */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Async struct for Series 0 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Async struct for Series 1 and Series 2 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0, /* Auto CS Setup cycles. */ \ + usartHwFlowControlNone /* No HW flow control. */ \ + } +#endif + +/** Default configuration for USART PRS triggering structure. */ +#if defined(USART_TRIGCTRL_AUTOTXTEN) +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable autoTX triggering. */ \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#else +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#endif + +/** Synchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Number of data bits in frame. */ + USART_Databits_TypeDef databits; + + /** Select if to operate in master or slave mode. */ + bool master; + + /** Select if to send most or least significant bit first. */ + bool msbf; + + /** Clock polarity/phase mode. */ + USART_ClockMode_TypeDef clockMode; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX mode. Transmits as long as RX is not full. + * Generates underflows if TX is empty. */ + bool autoTx; +#endif + + /** Auto CS enabling */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if defined(_USART_TIMING_CSHOLD_MASK) + /** Auto CS hold time in baud cycles */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles */ + uint8_t autoCsSetup; +#endif +} USART_InitSync_TypeDef; + +/** Default configuration for USART sync initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 databits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0 /* Auto CS Setup cycles. */ \ + } +#endif + +/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ +typedef struct { + /** General Asynchronous initialization structure. */ + USART_InitAsync_TypeDef async; + + /** Set to invert Rx signal before IrDA demodulator. */ + bool irRxInv; + + /** Set to enable filter on IrDA demodulator. */ + bool irFilt; + + /** Configure the pulse width generated by the IrDA modulator as a fraction + * of the configured USART bit period. */ + USART_IrDAPw_Typedef irPw; + +#if defined(USART_IRCTRL_IRPRSEN) + /** Enable the PRS channel selected by irPrsSel as input to IrDA module + * instead of TX. */ + bool irPrsEn; + + /** PRS can be used as input to the pulse modulator instead of TX. + * This value selects the channel to use. */ + USART_PRS_Channel_t irPrsSel; +#endif +} USART_InitIrDA_TypeDef; + +/** Default configuration for IrDA mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART IrDA struct for the EFM32G device */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART IrDA struct for Series 0 devices */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART IrDA struct for Series 1 and Series 2 devices */ +#if defined(USART_IRCTRL_IRPRSEN) +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#else +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE /* Pulse width is set to ONE. */ \ + } +#endif +#endif + +#if defined(_USART_I2SCTRL_MASK) +/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ +typedef struct { + /** General Synchronous initialization structure. */ + USART_InitSync_TypeDef sync; + + /** I2S mode. */ + USART_I2sFormat_TypeDef format; + + /** Delay on I2S data. Set to add a one-cycle delay between a transition + * on the word-clock and the start of the I2S word. + * Should be set for standard I2S format. */ + bool delay; + + /** Separate DMA Request For Left/Right Data. */ + bool dmaSplit; + + /** Justification of I2S data within the frame. */ + USART_I2sJustify_TypeDef justify; + + /** Stereo or Mono, set to true for mono. */ + bool mono; +} USART_InitI2s_TypeDef; + +/** Default configuration for I2S mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnableTx, /* Enable TX when init completed. */ \ + 0, /* Use current configured reference clock for configuring baudrate. */ \ + 1000000, /* Baudrate 1M bits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Operate as I2S master. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Don't enable USARTRx via PRS. */ \ + usartPrsRxCh0, /* PRS channel selection (dummy). */ \ + false, /* Disable AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0 /* Auto CS Setup cycles */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#endif +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateGet(USART_TypeDef *usart); +void USART_BaudrateSyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate); +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); + +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); + +#if defined(_USART_I2SCTRL_MASK) +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); +#endif +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * Pending USART/UART interrupt source(s) to clear. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_CLR = flags; +#else + usart->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to disable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more USART interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * USART_IntClear() prior to enabling the interrupt. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to enable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending USART interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * USART/UART interrupt source(s) pending. Returns one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) +{ + return usart->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending USART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled USART interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn + * register (USARTx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the USART module + * (USARTx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) +{ + uint32_t ien; + + /* Store USARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = usart->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return usart->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending USART interrupts from SW. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_SET = flags; +#else + usart->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get USART STATUS register. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * STATUS register value. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) +{ + return usart->STATUS; +} + +void USART_Reset(USART_TypeDef *usart); +uint8_t USART_Rx(USART_TypeDef *usart); +uint16_t USART_RxDouble(USART_TypeDef *usart); +uint32_t USART_RxDoubleExt(USART_TypeDef *usart); +uint16_t USART_RxExt(USART_TypeDef *usart); + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is used to quickly receive one 4-8 bits frame by reading the + * RXDATA register directly, without checking the STATUS register for the + * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, + * i.e., waiting is superfluous, in order to quickly read the received data. + * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. + * + * @note + * Because this function does not check whether the RXDATA register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a + * better choice if the validity of the RXDATA register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) +{ + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames, or one 10-16 bit frame. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-8 + * bit frames by reading the RXDOUBLE register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() + * for reception of two 9 bit frames. + * + * @note + * Because this function does not check whether the RXDOUBLE register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is + * normally a better choice if the validity of the RXDOUBLE register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-9 + * bit frames by reading the RXDOUBLEX register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * + * @note + * Because this function does not check whether the RXDOUBLEX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is + * normally a better choice if the validity of the RXDOUBLEX register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) +{ + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is used to quickly receive one 4-9 bit frame, (or part of + * 10-16 bit frame) with extended information by reading the RXDATAX register + * directly, without checking the STATUS register for the RXDATAV flag. This + * can be useful from the RXDATAV interrupt handler, i.e., waiting is + * superfluous, in order to quickly read the received data. + * + * @note + * Because this function does not check whether the RXDATAX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally + * a better choice if the validity of the RXDATAX register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDATAX; +} + +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); +void USART_Tx(USART_TypeDef *usart, uint8_t data); +void USART_TxDouble(USART_TypeDef *usart, uint16_t data); +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); +void USART_TxExt(USART_TypeDef *usart, uint16_t data); + +/** @} (end addtogroup usart) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ +#endif /* EM_USART_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_vdac.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_vdac.h index aa2be07..b304d5a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_vdac.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_vdac.h @@ -1,773 +1,773 @@ -/***************************************************************************//** - * @file - * @brief Digital to Analog Converter (VDAC) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_VDAC_H -#define EM_VDAC_H - -#include "em_device.h" - -#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) - -#include "sl_assert.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup vdac VDAC - Voltage DAC - * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API - * - * @details - * This module contains functions to control the VDAC peripheral of Silicon - * Labs' 32-bit MCUs and SoCs. VDAC converts digital values to analog - * signals at up to 500 ksps with 12-bit accuracy. VDAC is designed for - * low energy consumption, but can also provide very good performance. - * - * The following steps are necessary for basic operation: - * - * Clock enable: - * @code - CMU_ClockEnable(cmuClock_VDAC0, true);@endcode - * - * Initialize the VDAC with default settings and modify selected fields: - * @code - VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; - VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; - - // Set prescaler to get 1 MHz VDAC clock frequency. - vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); // function call for series 0/1 - VDAC_Init(VDAC0, &vdacInit); - - vdacChInit.enable = true; - VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode - * - * Perform a conversion: - * @code - VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode - * - * @note The output stage of a VDAC channel consists of an on-chip operational - * amplifier (OPAMP) in the OPAMP module. This OPAMP is highly configurable; - * and to exploit the VDAC functionality fully, configure the OPAMP using - * the OPAMP API. Using the OPAMP API also loads OPAMP calibration values. - * The default (reset) settings of OPAMP is sufficient for many applications. - * @{ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of VDAC register block pointer reference for assert statements.*/ - -#if VDAC_COUNT == 1 -#define VDAC_REF_VALID(ref) ((ref) == VDAC0) -#elif VDAC_COUNT == 2 -#define VDAC_REF_VALID(ref) (((ref) == VDAC0) || ((ref) == VDAC1)) -#else -#error "Undefined number of VDACs." -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -#if !defined(_SILICON_LABS_32B_SERIES_2) -/** Channel refresh period. */ -typedef enum { - vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ - vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ - vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ - vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ -} VDAC_Refresh_TypeDef; - -/** Reference voltage for VDAC. */ -typedef enum { - vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V band gap reference. */ - vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V band gap reference. */ - vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V band gap reference. */ - vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V band gap reference. */ - vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ - vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ -} VDAC_Ref_TypeDef; - -/** Peripheral Reflex System signal used to trigger VDAC channel conversion. */ -typedef enum { - vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS ch 0 triggers conversion. */ - vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS ch 1 triggers conversion. */ - vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS ch 2 triggers conversion. */ - vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS ch 3 triggers conversion. */ - vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS ch 4 triggers conversion. */ - vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS ch 5 triggers conversion. */ - vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS ch 6 triggers conversion. */ - vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS ch 7 triggers conversion. */ -#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH8) - vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS ch 8 triggers conversion. */ -#endif -#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH9) - vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS ch 9 triggers conversion. */ -#endif -#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH10) - vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ -#endif -#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH11) - vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ -#endif -} VDAC_PrsSel_TypeDef; - -/** Channel conversion trigger mode. */ -typedef enum { - vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ - vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ - vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ - vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ - vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ - vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ -} VDAC_TrigMode_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** VDAC initialization structure, common for both channels. */ -typedef struct { - /** Selects between main and alternate output path calibration values. */ - bool mainCalibration; - - /** Selects clock from asynchronous or synchronous (with respect to - peripheral clock) source. */ - bool asyncClockMode; - - /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ - bool warmupKeepOn; - - /** Channel refresh period. */ - VDAC_Refresh_TypeDef refresh; - - /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ - uint32_t prescaler; - - /** Reference voltage to use. */ - VDAC_Ref_TypeDef reference; - - /** Enable/disable reset of prescaler on CH 0 start. */ - bool ch0ResetPre; - - /** Enable/disable output enable control by CH1 PRS signal. */ - bool outEnablePRS; - - /** Enable/disable sine mode. */ - bool sineEnable; - - /** Select if single ended or differential output mode. */ - bool diff; -} VDAC_Init_TypeDef; - -/** Default configuration for VDAC initialization structure. */ -#define VDAC_INIT_DEFAULT \ - { \ - true, /* Use main output path calibration values. */ \ - false, /* Use synchronous clock mode. */ \ - false, /* Turn off between sample off conversions.*/ \ - vdacRefresh8, /* Refresh every 8th cycle. */ \ - 0, /* No prescaling. */ \ - vdacRef1V25Ln, /* 1.25 V internal low noise reference. */ \ - false, /* Do not reset prescaler on CH 0 start. */ \ - false, /* VDAC output enable always on. */ \ - false, /* Disable sine mode. */ \ - false /* Single ended mode. */ \ - } - -/** VDAC channel initialization structure. */ -typedef struct { - /** Enable channel. */ - bool enable; - - /** - * Peripheral reflex system trigger selection. Only applicable if @p trigMode - * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ - VDAC_PrsSel_TypeDef prsSel; - - /** Treat the PRS signal asynchronously. */ - bool prsAsync; - - /** Channel conversion trigger mode. */ - VDAC_TrigMode_TypeDef trigMode; - - /** Set channel conversion mode to sample/shut-off mode. Default is - * continuous.*/ - bool sampleOffMode; -} VDAC_InitChannel_TypeDef; - -/** Default configuration for VDAC channel initialization structure. */ -#define VDAC_INITCHANNEL_DEFAULT \ - { \ - false, /* Leave channel disabled when initialization is done. */ \ - vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ - false, /* Treat PRS channel as a synchronous signal. */ \ - vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ - false, /* Channel conversion set to continuous. */ \ - } -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/** Channel refresh period. */ -typedef enum { - vdacRefresh2 = _VDAC_CFG_REFRESHPERIOD_CYCLES2, /**< Refresh every 2 clock cycles. */ - vdacRefresh4 = _VDAC_CFG_REFRESHPERIOD_CYCLES4, /**< Refresh every 4 clock cycles. */ - vdacRefresh8 = _VDAC_CFG_REFRESHPERIOD_CYCLES8, /**< Refresh every 8 clock cycles. */ - vdacRefresh16 = _VDAC_CFG_REFRESHPERIOD_CYCLES16, /**< Refresh every 16 clock cycles. */ - vdacRefresh32 = _VDAC_CFG_REFRESHPERIOD_CYCLES32, /**< Refresh every 32 clock cycles. */ - vdacRefresh64 = _VDAC_CFG_REFRESHPERIOD_CYCLES64, /**< Refresh every 64 clock cycles. */ - vdacRefresh128 = _VDAC_CFG_REFRESHPERIOD_CYCLES128, /**< Refresh every 128 clock cycles. */ - vdacRefresh256 = _VDAC_CFG_REFRESHPERIOD_CYCLES256, /**< Refresh every 256 clock cycles. */ -} VDAC_Refresh_TypeDef; - -/** Timer overflow period. */ -typedef enum { - vdacCycles2 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2, /**< Overflows every 2 clock cycles. */ - vdacCycles4 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4, /**< Overflows every 4 clock cycles. */ - vdacCycles8 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8, /**< Overflows every 8 clock cycles. */ - vdacCycles16 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16, /**< Overflows every 16 clock cycles. */ - vdacCycles32 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32, /**< Overflows every 32 clock cycles. */ - vdacCycles64 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 /**< Overflows every 64 clock cycles. */ -} VDAC_TimerOverflow_TypeDef; - -/** Reference voltage for VDAC. */ -typedef enum { - vdacRef1V25 = _VDAC_CFG_REFRSEL_V125, /**< Internal 1.25 V band gap reference. */ - vdacRef2V5 = _VDAC_CFG_REFRSEL_V25, /**< Internal 2.5 V band gap reference. */ - vdacRefAvdd = _VDAC_CFG_REFRSEL_VDD, /**< AVDD reference. */ - vdacRefExtPin = _VDAC_CFG_REFRSEL_EXT, /**< External pin reference. */ -} VDAC_Ref_TypeDef; - -/** Refresh source for VDAC. */ -typedef enum { - vdacRefreshSrcNone = _VDAC_CH0CFG_REFRESHSOURCE_NONE, /**< No refresh source. */ - vdacRefreshSrcRefreshTimer = _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER,/**< Refresh triggered by refresh timer overflow. */ - vdacRefreshSrcSyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS, /**< Refresh triggered by sync PRS. */ - vdacRefreshSrcAsyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS, /**< Refresh triggered by async PRS. */ -} VDAC_RefreshSource_TypeDef; - -/** Channel conversion trigger mode. */ -typedef enum { - vdacTrigModeNone = _VDAC_CH0CFG_TRIGMODE_NONE, /**< No conversion trigger source selected. */ - vdacTrigModeSw = _VDAC_CH0CFG_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ - vdacTrigModeSyncPrs = _VDAC_CH0CFG_TRIGMODE_SYNCPRS, /**< Channel is triggered by Sync PRS input. */ -#if defined(LESENSE_PRESENT) && defined(_VDAC_CH0CFG_TRIGMODE_LESENSE) - vdacTrigModeLesense = _VDAC_CH0CFG_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ -#endif - vdacTrigModeInternalTimer = _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER, /**< Channel is triggered by Internal Timer. */ - vdacTrigModeAsyncPrs = _VDAC_CH0CFG_TRIGMODE_ASYNCPRS /**< Channel is triggered by Async PRS input. */ -} VDAC_TrigMode_TypeDef; - -/** Channel power mode. */ -typedef enum { - vdacPowerModeHighPower = _VDAC_CH0CFG_POWERMODE_HIGHPOWER, /**< High power buffer mode. */ - vdacPowerModeLowPower = _VDAC_CH0CFG_POWERMODE_LOWPOWER /**< Low power buffer mode. */ -} VDAC_PowerMode_TypeDef; - -/** VDAC channel Abus port selection. */ -typedef enum { - /** No GPIO selected. */ - vdacChPortNone = _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE, - /** Port A selected. */ - vdacChPortA = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA, - /** Port B selected. */ - vdacChPortB = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB, - /** Port C selected. */ - vdacChPortC = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC, - /** Port D selected. */ - vdacChPortD = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD, -} VDAC_ChPortSel_t; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** VDAC initialization structure, common for both channels. */ -typedef struct { - /** Number of prescaled CLK_DAC + 1 for the vdac to warmup. */ - uint32_t warmupTime; - - /** Halt during debug. */ - bool dbgHalt; - - /** Always allow clk_dac. */ - bool onDemandClk; - - /** DMA Wakeup. */ - bool dmaWakeUp; - - /** Bias keep warm enable. */ - bool biasKeepWarm; - - /** Channel refresh period. */ - VDAC_Refresh_TypeDef refresh; - - /** Internal timer overflow period. */ - VDAC_TimerOverflow_TypeDef timerOverflow; - - /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ - uint32_t prescaler; - - /** Reference voltage to use. */ - VDAC_Ref_TypeDef reference; - - /** Enable/disable reset of prescaler on CH 0 start. */ - bool ch0ResetPre; - - /** Sine reset mode. */ - bool sineReset; - - /** Enable/disable sine mode. */ - bool sineEnable; - - /** Select if single ended or differential output mode. */ - bool diff; - -#if defined(VDAC_CFG_SINEMODEPRS) - /** PRS controlled sinemode enable. */ - bool sineModePrsEnable; -#endif -#if defined(VDAC_CFG_OUTENPRS) - /** PRS controlled channel output enable. */ - bool prsOutEnable; -#endif -} VDAC_Init_TypeDef; - -#if defined(VDAC_CFG_SINEMODEPRS) -/** Default configuration for VDAC initialization structure. */ -#define VDAC_INIT_DEFAULT \ - { \ - _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ - false, /* Continue while debugging. */ \ - false, /* On demand clock. */ \ - false, /* DMA wake up. */ \ - false, /* Bias keep warm. */ \ - vdacRefresh2, /* Refresh every 2th cycle. */ \ - vdacCycles2, /* Internal overflow every 2th cycle. */ \ - 0, /* No prescaling. */ \ - vdacRef1V25, /* 1.25 V internal low noise reference. */ \ - false, /* Do not reset prescaler on CH 0 start. */ \ - false, /* Sine wave is stopped at the sample its currently outputting. */ \ - false, /* Disable sine mode. */ \ - false, /* Differential mode. */ \ - false, /* PRS controlled sinemode. */ \ - false, /* PRS controlled output enable. */ \ - } -#else -/** Default configuration for VDAC initialization structure. */ -#define VDAC_INIT_DEFAULT \ - { \ - _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ - false, /* Continue while debugging. */ \ - false, /* On demand clock. */ \ - false, /* DMA wake up. */ \ - false, /* Bias keep warm. */ \ - vdacRefresh2, /* Refresh every 2th cycle. */ \ - vdacCycles2, /* Internal overflow every 2th cycle. */ \ - 0, /* No prescaling. */ \ - vdacRef1V25, /* 1.25 V internal low noise reference. */ \ - false, /* Do not reset prescaler on CH 0 start. */ \ - false, /* Sine wave is stopped at the sample its currently outputting. */ \ - false, /* Disable sine mode. */ \ - false, /* Differential mode. */ \ - } -#endif - -#if defined(VDAC_CFG_SINEMODEPRS) -/** Sine mode configuration for VDAC initialization structure. */ -#define VDAC_INIT_SINE_GENERATION_MODE \ - { \ - _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ - false, /* Continue while debugging. */ \ - true, /* On demand clock. */ \ - false, /* DMA wake up. */ \ - false, /* Bias keep warm. */ \ - vdacRefresh8, /* Refresh every 8th cycle. */ \ - vdacCycles2, /* Internal overflow every 8th cycle. */ \ - 0, /* No prescaling. */ \ - vdacRef1V25, /* 1.25 V internal low noise reference. */ \ - false, /* Do not reset prescaler on CH 0 start. */ \ - false, /* Sine wave is stopped at the sample its currently outputting. */ \ - true, /* Enable sine mode. */ \ - false, /* Differential mode. */ \ - false, /* PRS controlled sinemode. */ \ - false, /* PRS controlled output enable. */ \ - } -#else -/** Sine mode configuration for VDAC initialization structure. */ -#define VDAC_INIT_SINE_GENERATION_MODE \ - { \ - _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ - false, /* Continue while debugging. */ \ - true, /* On demand clock. */ \ - false, /* DMA wake up. */ \ - false, /* Bias keep warm. */ \ - vdacRefresh8, /* Refresh every 8th cycle. */ \ - vdacCycles2, /* Internal overflow every 8th cycle. */ \ - 0, /* No prescaling. */ \ - vdacRef1V25, /* 1.25 V internal low noise reference. */ \ - false, /* Do not reset prescaler on CH 0 start. */ \ - false, /* Sine wave is stopped at the sample its currently outputting. */ \ - true, /* Enable sine mode. */ \ - false, /* Differential mode. */ \ - } -#endif - -/** VDAC channel initialization structure. */ -typedef struct { - /** Enable channel. */ - bool enable; - - /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ - bool warmupKeepOn; - - /** Select high capacitance load mode in conjunction with high power. */ - bool highCapLoadEnable; - - /** Channel x FIFO Low threshold data valid level. */ - uint32_t fifoLowDataThreshold; - - /** Channel refresh source. */ - VDAC_RefreshSource_TypeDef chRefreshSource; - - /** Channel conversion trigger mode. */ - VDAC_TrigMode_TypeDef trigMode; - - /** Channel power mode. */ - VDAC_PowerMode_TypeDef powerMode; - - /** Set channel conversion mode to sample/shut-off mode. Default is - * continuous.*/ - bool sampleOffMode; - - /** Vdac channel output pin. */ - uint32_t pin; - - /** Vdac channel output port. */ - VDAC_ChPortSel_t port; - - /** Short High power and low power output. */ - bool shortOutput; - - /** Alternative output enable. */ - bool auxOutEnable; - - /** Main output enable. */ - bool mainOutEnable; - - /** Channel output hold time. */ - uint32_t holdOutTime; -} VDAC_InitChannel_TypeDef; - -/** Default configuration for VDAC channel initialization structure. */ -#define VDAC_INITCHANNEL_DEFAULT \ - { \ - false, /* Leave channel disabled when initialization is done. */ \ - false, /* Turn off between sample off conversions.*/ \ - true, /* Enable High cap mode. */ \ - 0, /* FIFO data low watermark at 0. */ \ - vdacRefreshSrcNone, /* Channel refresh source. */ \ - vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ - vdacPowerModeHighPower, /* High power mode enabled. */ \ - false, /* Continuous conversion mode. */ \ - 0, /* ABUS pin selected. */ \ - vdacChPortNone, /* No Analog bus port selected. */ \ - false, /* Output not shorted */ \ - false, /* Alternative output disabled. */ \ - true, /* Main output enabled. */ \ - 0, /* Hold out time. Previously called settle time */ \ - } - -#endif -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, - unsigned int channel, - uint32_t value); -void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); -void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); -void VDAC_InitChannel(VDAC_TypeDef *vdac, - const VDAC_InitChannel_TypeDef *init, - unsigned int ch); - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Start/stop Sinemode. - * - * @details - * This function sends the sine mode start/stop signal to the DAC. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] start - * True to start the Sine mode, false to stop it. - ******************************************************************************/ -__STATIC_INLINE void VDAC_SineModeStart(VDAC_TypeDef *vdac, bool start) -{ - EFM_ASSERT(VDAC_REF_VALID(vdac)); - - while (0UL != (vdac->STATUS & VDAC_STATUS_SYNCBUSY)) { - } - - if (start) { - vdac->CMD = VDAC_CMD_SINEMODESTART; - while (0UL == (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { - } - } else { - vdac->CMD = VDAC_CMD_SINEMODESTOP; - while (0UL != (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { - } - } -} -#endif - -/***************************************************************************//** - * @brief - * Set the output signal of VDAC channel 0 to a given value. - * - * @details - * This function sets the output signal of VDAC channel 0 by writing @p value - * to the CH0DATA register. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] value - * Value to write to channel 0 output register CH0DATA. - ******************************************************************************/ -__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, - uint32_t value) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT(value <= _VDAC_CH0DATA_MASK); - vdac->CH0DATA = value; -#elif defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(value <= _VDAC_CH0F_MASK); - vdac->CH0F = value; -#endif -} - -/***************************************************************************//** - * @brief - * Set the output signal of VDAC channel 1 to a given value. - * - * @details - * This function sets the output signal of VDAC channel 1 by writing @p value - * to the CH1DATA register. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] value - * Value to write to channel 1 output register CH1DATA. - ******************************************************************************/ -__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, - uint32_t value) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT(value <= _VDAC_CH1DATA_MASK); - vdac->CH1DATA = value; -#elif defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(value <= _VDAC_CH1F_MASK); - vdac->CH1F = value; -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending VDAC interrupts. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] flags - * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) -{ -#if defined(VDAC_HAS_SET_CLEAR) - vdac->IF_CLR = flags; -#else - vdac->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more VDAC interrupts. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] flags - * VDAC interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the VDAC module (VDAC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) -{ -#if defined(VDAC_HAS_SET_CLEAR) - vdac->IEN_CLR = flags; -#else - vdac->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more VDAC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * VDAC_IntClear() prior to enabling the interrupt. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] flags - * VDAC interrupt sources to enable. Use a bitwise logic OR combination - * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) -{ -#if defined(VDAC_HAS_SET_CLEAR) - vdac->IEN_SET = flags; -#else - vdac->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending VDAC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @return - * VDAC interrupt sources pending. Use a bitwise logic OR combination - * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) -{ - return vdac->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending VDAC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled VDAC interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn - * register (VDACx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the VDAC module - * (VDACx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) -{ - uint32_t ien = vdac->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return vdac->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending VDAC interrupts from SW. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] flags - * VDAC interrupt sources to set to pending. Use a bitwise logic OR - * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) -{ -#if defined(VDAC_HAS_SET_CLEAR) - vdac->IF_SET = flags; -#else - vdac->IFS = flags; -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Get the VDAC Status register. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @return - * Current STATUS register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t VDAC_GetStatus(VDAC_TypeDef *vdac) -{ - return vdac->STATUS; -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); -#else -uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq); -#endif - -void VDAC_Reset(VDAC_TypeDef *vdac); - -/** @} (end addtogroup vdac) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ -#endif /* EM_VDAC_H */ +/***************************************************************************//** + * @file + * @brief Digital to Analog Converter (VDAC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_VDAC_H +#define EM_VDAC_H + +#include "em_device.h" + +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) + +#include "sl_assert.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup vdac VDAC - Voltage DAC + * @brief Digital to Analog Voltage Converter (VDAC) Peripheral API + * + * @details + * This module contains functions to control the VDAC peripheral of Silicon + * Labs' 32-bit MCUs and SoCs. VDAC converts digital values to analog + * signals at up to 500 ksps with 12-bit accuracy. VDAC is designed for + * low energy consumption, but can also provide very good performance. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_VDAC0, true);@endcode + * + * Initialize the VDAC with default settings and modify selected fields: + * @code + VDAC_Init_TypeDef vdacInit = VDAC_INIT_DEFAULT; + VDAC_InitChannel_TypeDef vdacChInit = VDAC_INITCHANNEL_DEFAULT; + + // Set prescaler to get 1 MHz VDAC clock frequency. + vdacInit.prescaler = VDAC_PrescaleCalc(1000000, true, 0); // function call for series 0/1 + VDAC_Init(VDAC0, &vdacInit); + + vdacChInit.enable = true; + VDAC_InitChannel(VDAC0, &vdacChInit, 0);@endcode + * + * Perform a conversion: + * @code + VDAC_ChannelOutputSet(VDAC0, 0, 250);@endcode + * + * @note The output stage of a VDAC channel consists of an on-chip operational + * amplifier (OPAMP) in the OPAMP module. This OPAMP is highly configurable; + * and to exploit the VDAC functionality fully, configure the OPAMP using + * the OPAMP API. Using the OPAMP API also loads OPAMP calibration values. + * The default (reset) settings of OPAMP is sufficient for many applications. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of VDAC register block pointer reference for assert statements.*/ + +#if VDAC_COUNT == 1 +#define VDAC_REF_VALID(ref) ((ref) == VDAC0) +#elif VDAC_COUNT == 2 +#define VDAC_REF_VALID(ref) (((ref) == VDAC0) || ((ref) == VDAC1)) +#else +#error "Undefined number of VDACs." +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if !defined(_SILICON_LABS_32B_SERIES_2) +/** Channel refresh period. */ +typedef enum { + vdacRefresh8 = _VDAC_CTRL_REFRESHPERIOD_8CYCLES, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CTRL_REFRESHPERIOD_16CYCLES, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CTRL_REFRESHPERIOD_32CYCLES, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CTRL_REFRESHPERIOD_64CYCLES, /**< Refresh every 64 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum { + vdacRef1V25Ln = _VDAC_CTRL_REFSEL_1V25LN, /**< Internal low noise 1.25 V band gap reference. */ + vdacRef2V5Ln = _VDAC_CTRL_REFSEL_2V5LN, /**< Internal low noise 2.5 V band gap reference. */ + vdacRef1V25 = _VDAC_CTRL_REFSEL_1V25, /**< Internal 1.25 V band gap reference. */ + vdacRef2V5 = _VDAC_CTRL_REFSEL_2V5, /**< Internal 2.5 V band gap reference. */ + vdacRefAvdd = _VDAC_CTRL_REFSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CTRL_REFSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Peripheral Reflex System signal used to trigger VDAC channel conversion. */ +typedef enum { + vdacPrsSelCh0 = _VDAC_CH0CTRL_PRSSEL_PRSCH0, /**< PRS ch 0 triggers conversion. */ + vdacPrsSelCh1 = _VDAC_CH0CTRL_PRSSEL_PRSCH1, /**< PRS ch 1 triggers conversion. */ + vdacPrsSelCh2 = _VDAC_CH0CTRL_PRSSEL_PRSCH2, /**< PRS ch 2 triggers conversion. */ + vdacPrsSelCh3 = _VDAC_CH0CTRL_PRSSEL_PRSCH3, /**< PRS ch 3 triggers conversion. */ + vdacPrsSelCh4 = _VDAC_CH0CTRL_PRSSEL_PRSCH4, /**< PRS ch 4 triggers conversion. */ + vdacPrsSelCh5 = _VDAC_CH0CTRL_PRSSEL_PRSCH5, /**< PRS ch 5 triggers conversion. */ + vdacPrsSelCh6 = _VDAC_CH0CTRL_PRSSEL_PRSCH6, /**< PRS ch 6 triggers conversion. */ + vdacPrsSelCh7 = _VDAC_CH0CTRL_PRSSEL_PRSCH7, /**< PRS ch 7 triggers conversion. */ +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH8) + vdacPrsSelCh8 = _VDAC_CH0CTRL_PRSSEL_PRSCH8, /**< PRS ch 8 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH9) + vdacPrsSelCh9 = _VDAC_CH0CTRL_PRSSEL_PRSCH9, /**< PRS ch 9 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH10) + vdacPrsSelCh10 = _VDAC_CH0CTRL_PRSSEL_PRSCH10, /**< PRS ch 10 triggers conversion. */ +#endif +#if defined(_VDAC_CH0CTRL_PRSSEL_PRSCH11) + vdacPrsSelCh11 = _VDAC_CH0CTRL_PRSSEL_PRSCH11, /**< PRS ch 11 triggers conversion. */ +#endif +} VDAC_PrsSel_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum { + vdacTrigModeSw = _VDAC_CH0CTRL_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModePrs = _VDAC_CH0CTRL_TRIGMODE_PRS, /**< Channel is triggered by PRS input. */ + vdacTrigModeRefresh = _VDAC_CH0CTRL_TRIGMODE_REFRESH, /**< Channel is triggered by Refresh timer. */ + vdacTrigModeSwPrs = _VDAC_CH0CTRL_TRIGMODE_SWPRS, /**< Channel is triggered by CHnDATA/COMBDATA write or PRS input. */ + vdacTrigModeSwRefresh = _VDAC_CH0CTRL_TRIGMODE_SWREFRESH, /**< Channel is triggered by CHnDATA/COMBDATA write or Refresh timer. */ + vdacTrigModeLesense = _VDAC_CH0CTRL_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +} VDAC_TrigMode_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC initialization structure, common for both channels. */ +typedef struct { + /** Selects between main and alternate output path calibration values. */ + bool mainCalibration; + + /** Selects clock from asynchronous or synchronous (with respect to + peripheral clock) source. */ + bool asyncClockMode; + + /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Enable/disable output enable control by CH1 PRS signal. */ + bool outEnablePRS; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; +} VDAC_Init_TypeDef; + +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + true, /* Use main output path calibration values. */ \ + false, /* Use synchronous clock mode. */ \ + false, /* Turn off between sample off conversions.*/ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25Ln, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* VDAC output enable always on. */ \ + false, /* Disable sine mode. */ \ + false /* Single ended mode. */ \ + } + +/** VDAC channel initialization structure. */ +typedef struct { + /** Enable channel. */ + bool enable; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p trigMode + * is set to @p vdacTrigModePrs or @p vdacTrigModeSwPrs. */ + VDAC_PrsSel_TypeDef prsSel; + + /** Treat the PRS signal asynchronously. */ + bool prsAsync; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continuous.*/ + bool sampleOffMode; +} VDAC_InitChannel_TypeDef; + +/** Default configuration for VDAC channel initialization structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ + { \ + false, /* Leave channel disabled when initialization is done. */ \ + vdacPrsSelCh0, /* PRS CH 0 triggers conversion. */ \ + false, /* Treat PRS channel as a synchronous signal. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + false, /* Channel conversion set to continuous. */ \ + } +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/** Channel refresh period. */ +typedef enum { + vdacRefresh2 = _VDAC_CFG_REFRESHPERIOD_CYCLES2, /**< Refresh every 2 clock cycles. */ + vdacRefresh4 = _VDAC_CFG_REFRESHPERIOD_CYCLES4, /**< Refresh every 4 clock cycles. */ + vdacRefresh8 = _VDAC_CFG_REFRESHPERIOD_CYCLES8, /**< Refresh every 8 clock cycles. */ + vdacRefresh16 = _VDAC_CFG_REFRESHPERIOD_CYCLES16, /**< Refresh every 16 clock cycles. */ + vdacRefresh32 = _VDAC_CFG_REFRESHPERIOD_CYCLES32, /**< Refresh every 32 clock cycles. */ + vdacRefresh64 = _VDAC_CFG_REFRESHPERIOD_CYCLES64, /**< Refresh every 64 clock cycles. */ + vdacRefresh128 = _VDAC_CFG_REFRESHPERIOD_CYCLES128, /**< Refresh every 128 clock cycles. */ + vdacRefresh256 = _VDAC_CFG_REFRESHPERIOD_CYCLES256, /**< Refresh every 256 clock cycles. */ +} VDAC_Refresh_TypeDef; + +/** Timer overflow period. */ +typedef enum { + vdacCycles2 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES2, /**< Overflows every 2 clock cycles. */ + vdacCycles4 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES4, /**< Overflows every 4 clock cycles. */ + vdacCycles8 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES8, /**< Overflows every 8 clock cycles. */ + vdacCycles16 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES16, /**< Overflows every 16 clock cycles. */ + vdacCycles32 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES32, /**< Overflows every 32 clock cycles. */ + vdacCycles64 = _VDAC_CFG_TIMEROVRFLOWPERIOD_CYCLES64 /**< Overflows every 64 clock cycles. */ +} VDAC_TimerOverflow_TypeDef; + +/** Reference voltage for VDAC. */ +typedef enum { + vdacRef1V25 = _VDAC_CFG_REFRSEL_V125, /**< Internal 1.25 V band gap reference. */ + vdacRef2V5 = _VDAC_CFG_REFRSEL_V25, /**< Internal 2.5 V band gap reference. */ + vdacRefAvdd = _VDAC_CFG_REFRSEL_VDD, /**< AVDD reference. */ + vdacRefExtPin = _VDAC_CFG_REFRSEL_EXT, /**< External pin reference. */ +} VDAC_Ref_TypeDef; + +/** Refresh source for VDAC. */ +typedef enum { + vdacRefreshSrcNone = _VDAC_CH0CFG_REFRESHSOURCE_NONE, /**< No refresh source. */ + vdacRefreshSrcRefreshTimer = _VDAC_CH0CFG_REFRESHSOURCE_REFRESHTIMER,/**< Refresh triggered by refresh timer overflow. */ + vdacRefreshSrcSyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_SYNCPRS, /**< Refresh triggered by sync PRS. */ + vdacRefreshSrcAsyncPrs = _VDAC_CH0CFG_REFRESHSOURCE_ASYNCPRS, /**< Refresh triggered by async PRS. */ +} VDAC_RefreshSource_TypeDef; + +/** Channel conversion trigger mode. */ +typedef enum { + vdacTrigModeNone = _VDAC_CH0CFG_TRIGMODE_NONE, /**< No conversion trigger source selected. */ + vdacTrigModeSw = _VDAC_CH0CFG_TRIGMODE_SW, /**< Channel is triggered by CHnDATA or COMBDATA write. */ + vdacTrigModeSyncPrs = _VDAC_CH0CFG_TRIGMODE_SYNCPRS, /**< Channel is triggered by Sync PRS input. */ +#if defined(LESENSE_PRESENT) && defined(_VDAC_CH0CFG_TRIGMODE_LESENSE) + vdacTrigModeLesense = _VDAC_CH0CFG_TRIGMODE_LESENSE, /**< Channel is triggered by LESENSE. */ +#endif + vdacTrigModeInternalTimer = _VDAC_CH0CFG_TRIGMODE_INTERNALTIMER, /**< Channel is triggered by Internal Timer. */ + vdacTrigModeAsyncPrs = _VDAC_CH0CFG_TRIGMODE_ASYNCPRS /**< Channel is triggered by Async PRS input. */ +} VDAC_TrigMode_TypeDef; + +/** Channel power mode. */ +typedef enum { + vdacPowerModeHighPower = _VDAC_CH0CFG_POWERMODE_HIGHPOWER, /**< High power buffer mode. */ + vdacPowerModeLowPower = _VDAC_CH0CFG_POWERMODE_LOWPOWER /**< Low power buffer mode. */ +} VDAC_PowerMode_TypeDef; + +/** VDAC channel Abus port selection. */ +typedef enum { + /** No GPIO selected. */ + vdacChPortNone = _VDAC_OUTCTRL_ABUSPORTSELCH0_NONE, + /** Port A selected. */ + vdacChPortA = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTA, + /** Port B selected. */ + vdacChPortB = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTB, + /** Port C selected. */ + vdacChPortC = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTC, + /** Port D selected. */ + vdacChPortD = _VDAC_OUTCTRL_ABUSPORTSELCH0_PORTD, +} VDAC_ChPortSel_t; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** VDAC initialization structure, common for both channels. */ +typedef struct { + /** Number of prescaled CLK_DAC + 1 for the vdac to warmup. */ + uint32_t warmupTime; + + /** Halt during debug. */ + bool dbgHalt; + + /** Always allow clk_dac. */ + bool onDemandClk; + + /** DMA Wakeup. */ + bool dmaWakeUp; + + /** Bias keep warm enable. */ + bool biasKeepWarm; + + /** Channel refresh period. */ + VDAC_Refresh_TypeDef refresh; + + /** Internal timer overflow period. */ + VDAC_TimerOverflow_TypeDef timerOverflow; + + /** Prescaler for VDAC clock. Clock is source clock divided by prescaler+1. */ + uint32_t prescaler; + + /** Reference voltage to use. */ + VDAC_Ref_TypeDef reference; + + /** Enable/disable reset of prescaler on CH 0 start. */ + bool ch0ResetPre; + + /** Sine reset mode. */ + bool sineReset; + + /** Enable/disable sine mode. */ + bool sineEnable; + + /** Select if single ended or differential output mode. */ + bool diff; + +#if defined(VDAC_CFG_SINEMODEPRS) + /** PRS controlled sinemode enable. */ + bool sineModePrsEnable; +#endif +#if defined(VDAC_CFG_OUTENPRS) + /** PRS controlled channel output enable. */ + bool prsOutEnable; +#endif +} VDAC_Init_TypeDef; + +#if defined(VDAC_CFG_SINEMODEPRS) +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + false, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh2, /* Refresh every 2th cycle. */ \ + vdacCycles2, /* Internal overflow every 2th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + false, /* Disable sine mode. */ \ + false, /* Differential mode. */ \ + false, /* PRS controlled sinemode. */ \ + false, /* PRS controlled output enable. */ \ + } +#else +/** Default configuration for VDAC initialization structure. */ +#define VDAC_INIT_DEFAULT \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + false, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh2, /* Refresh every 2th cycle. */ \ + vdacCycles2, /* Internal overflow every 2th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + false, /* Disable sine mode. */ \ + false, /* Differential mode. */ \ + } +#endif + +#if defined(VDAC_CFG_SINEMODEPRS) +/** Sine mode configuration for VDAC initialization structure. */ +#define VDAC_INIT_SINE_GENERATION_MODE \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + true, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + vdacCycles2, /* Internal overflow every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + true, /* Enable sine mode. */ \ + false, /* Differential mode. */ \ + false, /* PRS controlled sinemode. */ \ + false, /* PRS controlled output enable. */ \ + } +#else +/** Sine mode configuration for VDAC initialization structure. */ +#define VDAC_INIT_SINE_GENERATION_MODE \ + { \ + _VDAC_CFG_WARMUPTIME_DEFAULT, /* Number of prescaled DAC_CLK for Vdac to warmup. */ \ + false, /* Continue while debugging. */ \ + true, /* On demand clock. */ \ + false, /* DMA wake up. */ \ + false, /* Bias keep warm. */ \ + vdacRefresh8, /* Refresh every 8th cycle. */ \ + vdacCycles2, /* Internal overflow every 8th cycle. */ \ + 0, /* No prescaling. */ \ + vdacRef1V25, /* 1.25 V internal low noise reference. */ \ + false, /* Do not reset prescaler on CH 0 start. */ \ + false, /* Sine wave is stopped at the sample its currently outputting. */ \ + true, /* Enable sine mode. */ \ + false, /* Differential mode. */ \ + } +#endif + +/** VDAC channel initialization structure. */ +typedef struct { + /** Enable channel. */ + bool enable; + + /** Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.*/ + bool warmupKeepOn; + + /** Select high capacitance load mode in conjunction with high power. */ + bool highCapLoadEnable; + + /** Channel x FIFO Low threshold data valid level. */ + uint32_t fifoLowDataThreshold; + + /** Channel refresh source. */ + VDAC_RefreshSource_TypeDef chRefreshSource; + + /** Channel conversion trigger mode. */ + VDAC_TrigMode_TypeDef trigMode; + + /** Channel power mode. */ + VDAC_PowerMode_TypeDef powerMode; + + /** Set channel conversion mode to sample/shut-off mode. Default is + * continuous.*/ + bool sampleOffMode; + + /** Vdac channel output pin. */ + uint32_t pin; + + /** Vdac channel output port. */ + VDAC_ChPortSel_t port; + + /** Short High power and low power output. */ + bool shortOutput; + + /** Alternative output enable. */ + bool auxOutEnable; + + /** Main output enable. */ + bool mainOutEnable; + + /** Channel output hold time. */ + uint32_t holdOutTime; +} VDAC_InitChannel_TypeDef; + +/** Default configuration for VDAC channel initialization structure. */ +#define VDAC_INITCHANNEL_DEFAULT \ + { \ + false, /* Leave channel disabled when initialization is done. */ \ + false, /* Turn off between sample off conversions.*/ \ + true, /* Enable High cap mode. */ \ + 0, /* FIFO data low watermark at 0. */ \ + vdacRefreshSrcNone, /* Channel refresh source. */ \ + vdacTrigModeSw, /* Conversion trigged by CH0DATA or COMBDATA write. */ \ + vdacPowerModeHighPower, /* High power mode enabled. */ \ + false, /* Continuous conversion mode. */ \ + 0, /* ABUS pin selected. */ \ + vdacChPortNone, /* No Analog bus port selected. */ \ + false, /* Output not shorted */ \ + false, /* Alternative output disabled. */ \ + true, /* Main output enabled. */ \ + 0, /* Hold out time. Previously called settle time */ \ + } + +#endif +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value); +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable); +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init); +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch); + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start/stop Sinemode. + * + * @details + * This function sends the sine mode start/stop signal to the DAC. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] start + * True to start the Sine mode, false to stop it. + ******************************************************************************/ +__STATIC_INLINE void VDAC_SineModeStart(VDAC_TypeDef *vdac, bool start) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + + while (0UL != (vdac->STATUS & VDAC_STATUS_SYNCBUSY)) { + } + + if (start) { + vdac->CMD = VDAC_CMD_SINEMODESTART; + while (0UL == (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { + } + } else { + vdac->CMD = VDAC_CMD_SINEMODESTOP; + while (0UL != (vdac->STATUS & VDAC_STATUS_SINEACTIVE)) { + } + } +} +#endif + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 0 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 0 by writing @p value + * to the CH0DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 0 output register CH0DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel0OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(value <= _VDAC_CH0DATA_MASK); + vdac->CH0DATA = value; +#elif defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(value <= _VDAC_CH0F_MASK); + vdac->CH0F = value; +#endif +} + +/***************************************************************************//** + * @brief + * Set the output signal of VDAC channel 1 to a given value. + * + * @details + * This function sets the output signal of VDAC channel 1 by writing @p value + * to the CH1DATA register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] value + * Value to write to channel 1 output register CH1DATA. + ******************************************************************************/ +__STATIC_INLINE void VDAC_Channel1OutputSet(VDAC_TypeDef *vdac, + uint32_t value) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(value <= _VDAC_CH1DATA_MASK); + vdac->CH1DATA = value; +#elif defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(value <= _VDAC_CH1F_MASK); + vdac->CH1F = value; +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * Pending VDAC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntClear(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IF_CLR = flags; +#else + vdac->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more VDAC interrupts. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntDisable(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IEN_CLR = flags; +#else + vdac->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more VDAC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * VDAC_IntClear() prior to enabling the interrupt. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to enable. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntEnable(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IEN_SET = flags; +#else + vdac->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending VDAC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * VDAC interrupt sources pending. Use a bitwise logic OR combination + * of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGet(VDAC_TypeDef *vdac) +{ + return vdac->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending VDAC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled VDAC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in VDACx_IEN_nnn + * register (VDACx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the VDAC module + * (VDACx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_IntGetEnabled(VDAC_TypeDef *vdac) +{ + uint32_t ien = vdac->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return vdac->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending VDAC interrupts from SW. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] flags + * VDAC interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the VDAC module (VDAC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void VDAC_IntSet(VDAC_TypeDef *vdac, uint32_t flags) +{ +#if defined(VDAC_HAS_SET_CLEAR) + vdac->IF_SET = flags; +#else + vdac->IFS = flags; +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Get the VDAC Status register. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @return + * Current STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t VDAC_GetStatus(VDAC_TypeDef *vdac) +{ + return vdac->STATUS; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq); +#else +uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq); +#endif + +void VDAC_Reset(VDAC_TypeDef *vdac); + +/** @} (end addtogroup vdac) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +#endif /* EM_VDAC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h index f44110b..6794f83 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief CMSIS and EMLIB versions - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_VERSION_H -#define EM_VERSION_H - -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup version VERSION - Version Defines - * @brief Version API - * @details - * Macros specifying the EMLIB and CMSIS version. - * @{ - ******************************************************************************/ - -/* *INDENT-OFF* */ -/** Version number of targeted CMSIS package. */ -#define _CMSIS_VERSION 5.8.0 -/* *INDENT-ON* */ - -/** Major version of CMSIS. */ -#define _CMSIS_VERSION_MAJOR 5 - -/** Minor version of CMSIS. */ -#define _CMSIS_VERSION_MINOR 8 - -/** Patch revision of CMSIS. */ -#define _CMSIS_VERSION_PATCH 0 - -/** @} (end addtogroup version) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_VERSION_H */ +/***************************************************************************//** + * @file + * @brief CMSIS and EMLIB versions + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_VERSION_H +#define EM_VERSION_H + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup version VERSION - Version Defines + * @brief Version API + * @details + * Macros specifying the EMLIB and CMSIS version. + * @{ + ******************************************************************************/ + +/* *INDENT-OFF* */ +/** Version number of targeted CMSIS package. */ +#define _CMSIS_VERSION 5.8.0 +/* *INDENT-ON* */ + +/** Major version of CMSIS. */ +#define _CMSIS_VERSION_MAJOR 5 + +/** Minor version of CMSIS. */ +#define _CMSIS_VERSION_MINOR 8 + +/** Patch revision of CMSIS. */ +#define _CMSIS_VERSION_PATCH 0 + +/** @} (end addtogroup version) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_VERSION_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h index f77281a..3461939 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h @@ -1,455 +1,455 @@ -/***************************************************************************//** - * @file - * @brief Watchdog (WDOG) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_WDOG_H -#define EM_WDOG_H - -#include "em_device.h" -#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) - -#include -#include "sl_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup wdog - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Default WDOG instance for deprecated functions. */ -#if !defined(DEFAULT_WDOG) -#if defined(WDOG0) -#define DEFAULT_WDOG WDOG0 -#elif defined(WDOG) -#define DEFAULT_WDOG WDOG -#endif -#endif - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Watchdog clock selection. */ -#if defined(_WDOG_CTRL_CLKSEL_MASK) -typedef enum { - wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */ - wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */ - wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */ -} WDOG_ClkSel_TypeDef; -#endif - -/** Watchdog period selection. */ -typedef enum { - wdogPeriod_9 = 0x0, /**< 9 clock periods */ - wdogPeriod_17 = 0x1, /**< 17 clock periods */ - wdogPeriod_33 = 0x2, /**< 33 clock periods */ - wdogPeriod_65 = 0x3, /**< 65 clock periods */ - wdogPeriod_129 = 0x4, /**< 129 clock periods */ - wdogPeriod_257 = 0x5, /**< 257 clock periods */ - wdogPeriod_513 = 0x6, /**< 513 clock periods */ - wdogPeriod_1k = 0x7, /**< 1025 clock periods */ - wdogPeriod_2k = 0x8, /**< 2049 clock periods */ - wdogPeriod_4k = 0x9, /**< 4097 clock periods */ - wdogPeriod_8k = 0xA, /**< 8193 clock periods */ - wdogPeriod_16k = 0xB, /**< 16385 clock periods */ - wdogPeriod_32k = 0xC, /**< 32769 clock periods */ - wdogPeriod_64k = 0xD, /**< 65537 clock periods */ - wdogPeriod_128k = 0xE, /**< 131073 clock periods */ - wdogPeriod_256k = 0xF /**< 262145 clock periods */ -} WDOG_PeriodSel_TypeDef; - -#if defined(_WDOG_CTRL_WARNSEL_MASK) \ - || defined(_WDOG_CFG_WARNSEL_MASK) -/** Select Watchdog warning timeout period as percentage of timeout. */ -typedef enum { - wdogWarnDisable = 0, /**< Watchdog warning period is disabled. */ - wdogWarnTime25pct = 1, /**< Watchdog warning period is 25% of the timeout. */ - wdogWarnTime50pct = 2, /**< Watchdog warning period is 50% of the timeout. */ - wdogWarnTime75pct = 3, /**< Watchdog warning period is 75% of the timeout. */ -} WDOG_WarnSel_TypeDef; -#endif - -#if defined(_WDOG_CTRL_WINSEL_MASK) \ - || defined(_WDOG_CFG_WINSEL_MASK) -/** Select Watchdog illegal window limit. */ -typedef enum { - wdogIllegalWindowDisable = 0, /**< Watchdog illegal window disabled. */ - wdogIllegalWindowTime12_5pct = 1, /**< Window timeout is 12.5% of the timeout. */ - wdogIllegalWindowTime25_0pct = 2, /**< Window timeout is 25% of the timeout. */ - wdogIllegalWindowTime37_5pct = 3, /**< Window timeout is 37.5% of the timeout. */ - wdogIllegalWindowTime50_0pct = 4, /**< Window timeout is 50% of the timeout. */ - wdogIllegalWindowTime62_5pct = 5, /**< Window timeout is 62.5% of the timeout. */ - wdogIllegalWindowTime75_0pct = 6, /**< Window timeout is 75% of the timeout. */ - wdogIllegalWindowTime87_5pct = 7, /**< Window timeout is 87.5% of the timeout. */ -} WDOG_WinSel_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Watchdog initialization structure. */ -typedef struct { - /** Enable Watchdog when initialization completed. */ - bool enable; - - /** Counter keeps running during debug halt. */ - bool debugRun; - -#if defined(_WDOG_CTRL_CLRSRC_MASK) \ - || defined(_WDOG_CFG_CLRSRC_MASK) - /** Select WDOG clear source: - * False: Write to the clear bit will clear the WDOG counter - * True: Rising edge on the PRS Source 0 will clear the WDOG counter - * */ - bool clrSrc; -#endif - -#if defined(_WDOG_CFG_EM1RUN_MASK) - /** Counter keeps running when in EM1. Available for series2. */ - bool em1Run; -#endif - - /** Counter keeps running when in EM2. */ - bool em2Run; - - /** Counter keeps running when in EM3. */ - bool em3Run; - - /** Block EMU from entering EM4. */ - bool em4Block; - -#if defined(_WDOG_CFG_MASK) - /** When set, a PRS Source 0 missing event will trigger a WDOG reset. */ - bool prs0MissRstEn; - - /** When set, a PRS Source 1 missing event will trigger a WDOG reset. */ - bool prs1MissRstEn; -#endif - - /** Block SW from disabling LFRCO/LFXO oscillators. */ -#if defined(_WDOG_CTRL_SWOSCBLOCK_MASK) - bool swoscBlock; -#endif - - /** Block SW from modifying the configuration (a reset is needed to reconfigure). */ - bool lock; - - /** Clock source to use for Watchdog. */ -#if defined(_WDOG_CTRL_CLKSEL_MASK) - WDOG_ClkSel_TypeDef clkSel; -#endif - - /** Watchdog timeout period. */ - WDOG_PeriodSel_TypeDef perSel; - -#if defined(_WDOG_CTRL_WARNSEL_MASK) \ - || defined(_WDOG_CFG_WARNSEL_MASK) - /** Select warning time as % of the Watchdog timeout */ - WDOG_WarnSel_TypeDef warnSel; -#endif - -#if defined(_WDOG_CTRL_WINSEL_MASK) \ - || defined(_WDOG_CFG_WINSEL_MASK) - /** Select illegal window time as % of the Watchdog timeout */ - WDOG_WinSel_TypeDef winSel; -#endif - -#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ - || defined(_WDOG_CFG_WDOGRSTDIS_MASK) - /** Disable Watchdog reset output if true */ - bool resetDisable; -#endif -} WDOG_Init_TypeDef; - -/** Suggested default configuration for WDOG initialization structure. */ -#if defined(_WDOG_CFG_MASK) && defined(_WDOG_CFG_EM1RUN_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM1. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ - false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#elif defined(_WDOG_CFG_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ - false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#elif defined(_WDOG_CTRL_WARNSEL_MASK) \ - && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ - && defined(_WDOG_CTRL_WINSEL_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogClkSelLFRCO, /* Select 32.768 kHZ WDOG oscillator. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#else -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogClkSelLFRCO, /* Select 32.768 kHz WDOG oscillator. */ \ - wdogPeriod_256k /* Set longest possible timeout period. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable); -void WDOGn_Feed(WDOG_TypeDef *wdog); -void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init); -void WDOGn_Lock(WDOG_TypeDef *wdog); -void WDOGn_SyncWait(WDOG_TypeDef *wdog); -void WDOGn_Unlock(WDOG_TypeDef *wdog); - -#if defined(_WDOG_IF_MASK) -/***************************************************************************//** - * @brief - * Clear one or more pending WDOG interrupts. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to clear. Use a set of interrupt flags OR-ed - * together to clear multiple interrupt sources. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntClear(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IF_CLR = flags; -#else - wdog->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more WDOG interrupts. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to disable. Use a set of interrupt flags OR-ed - * together to disable multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntDisable(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IEN_CLR = flags; -#else - wdog->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more WDOG interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * WDOG_IntClear() prior to enabling the interrupt. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to enable. Use a set of interrupt flags OR-ed - * together to set multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntEnable(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IEN_SET = flags; -#else - wdog->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending WDOG interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * Pending WDOG interrupt sources. Returns a set of interrupt flags OR-ed - * together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t WDOGn_IntGet(WDOG_TypeDef *wdog) -{ - return wdog->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending WDOG interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * Pending and enabled WDOG interrupt sources. Returns a set of interrupt - * flags OR-ed together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t WDOGn_IntGetEnabled(WDOG_TypeDef *wdog) -{ - uint32_t tmp; - - tmp = wdog->IEN; - - /* Bitwise AND of pending and enabled interrupt flags. */ - return wdog->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending WDOG interrupts from SW. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to set to pending. Use a set of interrupt flags - * (WDOG_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IF_SET = flags; -#else - wdog->IFS = flags; -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Get enabled status of the Watchdog. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * True if Watchdog is enabled. - ******************************************************************************/ -__STATIC_INLINE bool WDOGn_IsEnabled(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_EN_MASK) - return (wdog->EN & _WDOG_EN_EN_MASK) == WDOG_EN_EN; -#else - return (wdog->CTRL & _WDOG_CTRL_EN_MASK) == WDOG_CTRL_EN; -#endif -} - -/***************************************************************************//** - * @brief - * Get locked status of the Watchdog. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * True if Watchdog is locked. - ******************************************************************************/ -__STATIC_INLINE bool WDOGn_IsLocked(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_STATUS_MASK) - return (wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED; -#else - return (wdog->CTRL & _WDOG_CTRL_LOCK_MASK) == WDOG_CTRL_LOCK; -#endif -} - -/** @} (end addtogroup wdog) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ -#endif /* EM_WDOG_H */ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_WDOG_H +#define EM_WDOG_H + +#include "em_device.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup wdog + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Default WDOG instance for deprecated functions. */ +#if !defined(DEFAULT_WDOG) +#if defined(WDOG0) +#define DEFAULT_WDOG WDOG0 +#elif defined(WDOG) +#define DEFAULT_WDOG WDOG +#endif +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Watchdog clock selection. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) +typedef enum { + wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */ + wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */ + wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */ +} WDOG_ClkSel_TypeDef; +#endif + +/** Watchdog period selection. */ +typedef enum { + wdogPeriod_9 = 0x0, /**< 9 clock periods */ + wdogPeriod_17 = 0x1, /**< 17 clock periods */ + wdogPeriod_33 = 0x2, /**< 33 clock periods */ + wdogPeriod_65 = 0x3, /**< 65 clock periods */ + wdogPeriod_129 = 0x4, /**< 129 clock periods */ + wdogPeriod_257 = 0x5, /**< 257 clock periods */ + wdogPeriod_513 = 0x6, /**< 513 clock periods */ + wdogPeriod_1k = 0x7, /**< 1025 clock periods */ + wdogPeriod_2k = 0x8, /**< 2049 clock periods */ + wdogPeriod_4k = 0x9, /**< 4097 clock periods */ + wdogPeriod_8k = 0xA, /**< 8193 clock periods */ + wdogPeriod_16k = 0xB, /**< 16385 clock periods */ + wdogPeriod_32k = 0xC, /**< 32769 clock periods */ + wdogPeriod_64k = 0xD, /**< 65537 clock periods */ + wdogPeriod_128k = 0xE, /**< 131073 clock periods */ + wdogPeriod_256k = 0xF /**< 262145 clock periods */ +} WDOG_PeriodSel_TypeDef; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) +/** Select Watchdog warning timeout period as percentage of timeout. */ +typedef enum { + wdogWarnDisable = 0, /**< Watchdog warning period is disabled. */ + wdogWarnTime25pct = 1, /**< Watchdog warning period is 25% of the timeout. */ + wdogWarnTime50pct = 2, /**< Watchdog warning period is 50% of the timeout. */ + wdogWarnTime75pct = 3, /**< Watchdog warning period is 75% of the timeout. */ +} WDOG_WarnSel_TypeDef; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) +/** Select Watchdog illegal window limit. */ +typedef enum { + wdogIllegalWindowDisable = 0, /**< Watchdog illegal window disabled. */ + wdogIllegalWindowTime12_5pct = 1, /**< Window timeout is 12.5% of the timeout. */ + wdogIllegalWindowTime25_0pct = 2, /**< Window timeout is 25% of the timeout. */ + wdogIllegalWindowTime37_5pct = 3, /**< Window timeout is 37.5% of the timeout. */ + wdogIllegalWindowTime50_0pct = 4, /**< Window timeout is 50% of the timeout. */ + wdogIllegalWindowTime62_5pct = 5, /**< Window timeout is 62.5% of the timeout. */ + wdogIllegalWindowTime75_0pct = 6, /**< Window timeout is 75% of the timeout. */ + wdogIllegalWindowTime87_5pct = 7, /**< Window timeout is 87.5% of the timeout. */ +} WDOG_WinSel_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Watchdog initialization structure. */ +typedef struct { + /** Enable Watchdog when initialization completed. */ + bool enable; + + /** Counter keeps running during debug halt. */ + bool debugRun; + +#if defined(_WDOG_CTRL_CLRSRC_MASK) \ + || defined(_WDOG_CFG_CLRSRC_MASK) + /** Select WDOG clear source: + * False: Write to the clear bit will clear the WDOG counter + * True: Rising edge on the PRS Source 0 will clear the WDOG counter + * */ + bool clrSrc; +#endif + +#if defined(_WDOG_CFG_EM1RUN_MASK) + /** Counter keeps running when in EM1. Available for series2. */ + bool em1Run; +#endif + + /** Counter keeps running when in EM2. */ + bool em2Run; + + /** Counter keeps running when in EM3. */ + bool em3Run; + + /** Block EMU from entering EM4. */ + bool em4Block; + +#if defined(_WDOG_CFG_MASK) + /** When set, a PRS Source 0 missing event will trigger a WDOG reset. */ + bool prs0MissRstEn; + + /** When set, a PRS Source 1 missing event will trigger a WDOG reset. */ + bool prs1MissRstEn; +#endif + + /** Block SW from disabling LFRCO/LFXO oscillators. */ +#if defined(_WDOG_CTRL_SWOSCBLOCK_MASK) + bool swoscBlock; +#endif + + /** Block SW from modifying the configuration (a reset is needed to reconfigure). */ + bool lock; + + /** Clock source to use for Watchdog. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) + WDOG_ClkSel_TypeDef clkSel; +#endif + + /** Watchdog timeout period. */ + WDOG_PeriodSel_TypeDef perSel; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) + /** Select warning time as % of the Watchdog timeout */ + WDOG_WarnSel_TypeDef warnSel; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) + /** Select illegal window time as % of the Watchdog timeout */ + WDOG_WinSel_TypeDef winSel; +#endif + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + || defined(_WDOG_CFG_WDOGRSTDIS_MASK) + /** Disable Watchdog reset output if true */ + bool resetDisable; +#endif +} WDOG_Init_TypeDef; + +/** Suggested default configuration for WDOG initialization structure. */ +#if defined(_WDOG_CFG_MASK) && defined(_WDOG_CFG_EM1RUN_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM1. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CFG_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CTRL_WARNSEL_MASK) \ + && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + && defined(_WDOG_CTRL_WINSEL_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHZ WDOG oscillator. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#else +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHz WDOG oscillator. */ \ + wdogPeriod_256k /* Set longest possible timeout period. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable); +void WDOGn_Feed(WDOG_TypeDef *wdog); +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init); +void WDOGn_Lock(WDOG_TypeDef *wdog); +void WDOGn_SyncWait(WDOG_TypeDef *wdog); +void WDOGn_Unlock(WDOG_TypeDef *wdog); + +#if defined(_WDOG_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntClear(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_CLR = flags; +#else + wdog->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntDisable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_CLR = flags; +#else + wdog->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more WDOG interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * WDOG_IntClear() prior to enabling the interrupt. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntEnable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_SET = flags; +#else + wdog->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending WDOG interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending WDOG interrupt sources. Returns a set of interrupt flags OR-ed + * together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGet(WDOG_TypeDef *wdog) +{ + return wdog->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending WDOG interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending and enabled WDOG interrupt sources. Returns a set of interrupt + * flags OR-ed together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGetEnabled(WDOG_TypeDef *wdog) +{ + uint32_t tmp; + + tmp = wdog->IEN; + + /* Bitwise AND of pending and enabled interrupt flags. */ + return wdog->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending WDOG interrupts from SW. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to set to pending. Use a set of interrupt flags + * (WDOG_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_SET = flags; +#else + wdog->IFS = flags; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get enabled status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is enabled. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsEnabled(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_EN_MASK) + return (wdog->EN & _WDOG_EN_EN_MASK) == WDOG_EN_EN; +#else + return (wdog->CTRL & _WDOG_CTRL_EN_MASK) == WDOG_CTRL_EN; +#endif +} + +/***************************************************************************//** + * @brief + * Get locked status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is locked. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsLocked(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_STATUS_MASK) + return (wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED; +#else + return (wdog->CTRL & _WDOG_CTRL_LOCK_MASK) == WDOG_CTRL_LOCK; +#endif +} + +/** @} (end addtogroup wdog) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ +#endif /* EM_WDOG_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h index eb57d5c..9b2e671 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h @@ -1,1899 +1,1899 @@ -/***************************************************************************//** - * @file - * @brief Clock Management Unit Private API definition. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_EM_CMU_H -#define SLI_EM_CMU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(_SILICON_LABS_32B_SERIES_2) - -/***************************************************************************//** - * @brief Performs pre-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPreClockSelect(void); - -/***************************************************************************//** - * @brief Performs post-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPostClockSelect(void); - -/***************************************************************************//** - * @brief Sets the HFXO0 FORCEEN bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK and the selected clock source is HFXO. - ******************************************************************************/ -void sli_em_cmu_HFXOSetForceEnable(void); - -/***************************************************************************//** - * @brief This function will set the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENSet(void); - -/***************************************************************************//** - * @brief This function will clear the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENClear(void); - -#define CMU_SYSCLK_SELECT_HFRCODPLL \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#define CMU_SYSCLK_SELECT_HFXO \ - do { \ - sli_em_cmu_HFXOSetForceEnable(); \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ - } \ - } while (0) - -#define CMU_SYSCLK_SELECT_CLKIN0 \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#define CMU_SYSCLK_SELECT_FSRCO \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#if defined(RFFPLL_PRESENT) - -#define CMU_SYSCLK_SELECT_RFFPLLSYS \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#endif /* RFFPLL_PRESENT */ - -#if defined(IADC_PRESENT) -#define CMU_IADCCLK_SELECT_EM01GRPACLK \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK - -#if defined(HFRCOEM23_PRESENT) -#define CMU_IADCCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 -#endif /* HFRCOEM23_PRESENT */ - -#define CMU_IADCCLK_SELECT_FSRCO \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO -#endif /* IADC_PRESENT */ - -#define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* KEYSCAN_PRESENT*/ - -#define CMU_EM01GRPACLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* KEYSCAN_PRESENT*/ - -#if defined(HFRCOEM23_PRESENT) -#define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* KEYSCAN_PRESENT*/ -#endif /* HFRCOEM23_PRESENT */ - -#define CMU_EM01GRPACLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* KEYSCAN_PRESENT*/ - -#define CMU_EM01GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) -#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* KEYSCAN_PRESENT*/ -#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) -#define CMU_EM01GRPACLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* KEYSCAN_PRESENT*/ -#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ - -#define CMU_SYSTICK_SELECT_EM23GRPACLK \ - do { \ - sli_em_cmu_SYSTICEXTCLKENSet(); \ - SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ - } while (0) - -#define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK -#define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK -#define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK - -#define CMU_SYSTICK_SELECT_HCLK \ - do { \ - sli_em_cmu_SYSTICEXTCLKENClear(); \ - SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ - } while (0) - -#define CMU_EM23GRPACLK_SELECT_LFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#endif /* LESENSE_PRESENT */ - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EM23GRPACLK_SELECT_PLFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#endif /* LESENSE_PRESENT */ -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_EM23GRPACLK_SELECT_LFXO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#endif /* LESENSE_PRESENT */ - -#define CMU_EM23GRPACLK_SELECT_ULFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#endif /* LESENSE_PRESENT */ - -#define CMU_EM23GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_EM4GRPACLK_SELECT_LFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EM4GRPACLK_SELECT_PLFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_EM4GRPACLK_SELECT_LFXO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO - -#define CMU_EM4GRPACLK_SELECT_ULFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO - -#define CMU_EM4GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) -#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL - -#define CMU_EM01GRPBCLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO - -#define CMU_EM01GRPBCLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO - -#define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ - } while (0) - -#define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 - -#define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT - -#define CMU_EM01GRPBCLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT - -#define CMU_EM01GRPBCLK_SELECT_DISABLED \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ - -#define CMU_WDOG0_SELECT_LFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_WDOG0_SELECT_PLFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_WDOG0_SELECT_LFXO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO - -#define CMU_WDOG0_SELECT_ULFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO - -#define CMU_WDOG0_SELECT_HCLKDIV1024 \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 - -#define CMU_WDOG0_SELECT_DISABLED \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED - -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) -#define CMU_WDOG1_SELECT_LFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_WDOG1_SELECT_PLFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_WDOG1_SELECT_LFXO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO - -#define CMU_WDOG1_SELECT_ULFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO - -#define CMU_WDOG1_SELECT_HCLKDIV1024 \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 - -#define CMU_WDOG1_SELECT_DISABLED \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED -#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ - -#define CMU_DPLLREFCLK_SELECT_HFXO \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_LFXO \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_CLKIN0 \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_DISABLED \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) -#define CMU_TRACECLK_RESTORE_TRACE_PRE() \ - bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ - if (restoreTrace) { \ - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ - } \ - do {} while (0) - -#define CMU_TRACECLK_RESTORE_TRACE_POST() \ - if (restoreTrace) { \ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ - } \ - do {} while (0) - -#else -#define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) -#define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#define CMU_TRACECLK_SELECT_HCLK \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - #define CMU_TRACECLK_SELECT_SYSCLK \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#define CMU_TRACECLK_SELECT_HFRCODPLLRT \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) -#define CMU_TRACECLK_SELECT_HFRCOEM23 \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ - -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) -#define CMU_EUART0_SELECT_EM01GRPACLK \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK - -#define CMU_EUART0_SELECT_EM23GRPACLK \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK - -#define CMU_EUART0_SELECT_DISABLED \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED -#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ - -#if defined(EUSART_PRESENT) -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) -#define CMU_EUSART0_SELECT_EM01GRPACLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) -#define CMU_EUSART0_SELECT_EM01GRPCCLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) -#define CMU_EUSART0_SELECT_EM23GRPACLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) -#define CMU_EUSART0_SELECT_FSRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) -#define CMU_EUSART0_SELECT_HFRCOEM23 \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) -#define CMU_EUSART0_SELECT_LFRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EUSART0_SELECT_PLFRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) -#define CMU_EUSART0_SELECT_LFXO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) -#define CMU_EUSART0_SELECT_DISABLED \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ -#endif /* EUSART_PRESENT */ - -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -#define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) -#define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ -#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ - -#define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#define CMU_EM01GRPCCLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#define CMU_EM01GRPCCLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) -#define CMU_EM01GRPCCLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ -#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ -#endif /* _CMU_EM01GRPCCLKCTRL_MASK */ - -#if defined (RTCC_PRESENT) -#define CMU_RTCC_SELECT_LFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_RTCC_SELECT_PLFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_RTCC_SELECT_LFXO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO - -#define CMU_RTCC_SELECT_ULFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO - -#endif /* RTCC_PRESENT */ - -#if defined(SYSRTC_PRESENT) -#define CMU_SYSRTC_SELECT_LFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_SYSRTC_SELECT_PLFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_SYSRTC_SELECT_LFXO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO - -#define CMU_SYSRTC_SELECT_ULFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO - -#define CMU_SYSRTC_SELECT_DISABLED \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED -#endif /* SYSRTC_PRESENT */ - -#if defined(LCD_PRESENT) -#define CMU_LCD_SELECT_LFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_LCD_SELECT_PLFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_LCD_SELECT_LFXO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO - -#define CMU_LCD_SELECT_ULFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO -#endif /* LCD_PRESENT */ - -#if defined(VDAC_PRESENT) -#define CMU_VDAC0_SELECT_FSRCO \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO - -#define CMU_VDAC0_SELECT_HFRCOEM23 \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 - -#define CMU_VDAC0_SELECT_EM01GRPACLK \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK - -#define CMU_VDAC0_SELECT_EM23GRPACLK \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK - -#if (VDAC_COUNT > 1) -#define CMU_VDAC1_SELECT_FSRCO \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO - -#define CMU_VDAC1_SELECT_HFRCOEM23 \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 - -#define CMU_VDAC1_SELECT_EM01GRPACLK \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK - -#define CMU_VDAC1_SELECT_EM23GRPACLK \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK -#endif /* VDAC_COUNT > 1 */ -#endif /* VDAC_PRESENT */ - -#if defined(PCNT_PRESENT) -#define CMU_PCNT0_SELECT_EM23GRPACLK \ - do { \ - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ - | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK - -#define CMU_PCNT0_SELECT_PCNTEXTCLK \ - do { \ - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ - | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ - } while (0) - -#define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK -#endif /* PCNT_PRESENT */ - -#if defined(LESENSE_PRESENT) -#define CMU_LESENSEHFCLK_SELECT_FSRCO \ - do { \ - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ - | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ - | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) -#endif /* LESENSE_PRESENT */ - -#if defined(USB_PRESENT) -#define CMU_USB_SELECT_USBPLL0 \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ - } while (0) - -#define CMU_USB_SELECT_LFXO \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_USB_SELECT_LFRCO \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) -#endif /* USB_PRESENT */ - -#elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the System Core Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the HF Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigHFClock(void); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * an LF clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @param[in]osc - * Reference to a low-frequency oscillator. One of the following values is valid: - * - cmuOsc_LFXO - * - cmuOsc_LFRCO - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and LFXO or LFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFXO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFXO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFXO(void); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCO(void); - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCODIV2(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * CLKIN0 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and CLKIN0 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectCLKIN0(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCO(void); -#endif - -#define CMU_HF_SELECT_LFXO \ - do { \ - sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ - } while (0) - -#define CMU_HF_SELECT_LFRCO \ - do { \ - sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ - } while (0) - -#define CMU_HF_SELECT_HFXO \ - do { \ - sli_em_cmu_HFClockSelectHFXO(); \ - } while (0) - -#define CMU_HF_SELECT_HFRCO \ - do { \ - sli_em_cmu_HFClockSelectHFRCO(); \ - } while (0) - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -#define CMU_HF_SELECT_USHFRCODIV2 \ - do { \ - sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -#define CMU_HF_SELECT_HFRCODIV2 \ - do { \ - sli_em_cmu_HFClockSelectHFRCODIV2(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -#define CMU_HF_SELECT_CLKIN0 \ - do { \ - sli_em_cmu_HFClockSelectCLKIN0(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -#define CMU_HF_SELECT_USHFRCO \ - do { \ - sli_em_cmu_HFClockSelectUSHFRCO(); \ - } while (0) -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ - } while (0) - -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFA_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ - -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigHFClock(); \ - BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ - } while (0) - -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFB_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ - -#if defined(_CMU_LFCCLKSEL_MASK) -#define CMU_LFC_SELECT_DISABLED \ - do { \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ - } while (0) - -#define CMU_LFC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ - } while (0) - -#define CMU_LFC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ - } while (0) - -#define CMU_LFC_SELECT_ULFRCO \ - do { \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ - } while (0) - -#endif /* _CMU_LFCCLKSEL_MASK */ - -#define CMU_LFE_SELECT_DISABLED \ - do { \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ - } while (0) - -#define CMU_LFE_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ - } while (0) - -#define CMU_LFE_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ - } while (0) - -#define CMU_LFE_SELECT_ULFRCO \ - do { \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFE_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ -#endif /* _SILICON_LABS_32B_SERIES_1 */ - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(_CMU_LFCLKSEL_LFAE_MASK) -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) -#endif - -#else -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) -#endif /* CMU_LFA_SELECT_HFCLKLE */ -#endif /* _CMU_LFCLKSEL_LFAE_MASK */ - -#if defined(_CMU_LFCLKSEL_LFBE_MASK) -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) -#endif - -#else -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) -#endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ -#endif /* _CMU_LFCLKSEL_LFBE_MASK */ - -#define CMU_LFC_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) - -#define CMU_LFC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) - -#define CMU_LFC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) -#endif /* _SILICON_LABS_32B_SERIES_0 */ - -#if defined(_CMU_DBGCLKSEL_DBG_MASK) -#define CMU_DBG_SELECT_AUXHFRCO \ - do { \ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ - } while (0) - -#define CMU_DBG_SELECT_HFCLK \ - do { \ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ - } while (0) -#endif /* _CMU_DBGCLKSEL_DBG_MASK */ - -#if defined(CMU_CTRL_DBGCLK) -#define CMU_DBG_SELECT_AUXHFRCO \ - do { \ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ - | CMU_CTRL_DBGCLK_AUXHFRCO; \ - } while (0) - -#define CMU_DBG_SELECT_HFCLK \ - do { \ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ - | CMU_CTRL_DBGCLK_HFCLK; \ - } while (0) -#endif /* CMU_CTRL_DBGCLK */ - -#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) -#define CMU_USBC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ - while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ - } while (0) - -#define CMU_USBC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ - while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ - } while (0) - -#if defined(CMU_STATUS_USBCHFCLKSEL) -#define CMU_USBC_SELECT_HFCLK \ - do { \ - CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ - while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ - } while (0) -#endif /* CMU_STATUS_USBCHFCLKSEL */ - -#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) -#define CMU_USBC_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ - while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ - } while (0) -#endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ -#endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) -#define CMU_ADC0ASYNC_SELECT_DISABLED \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) -#define CMU_ADC1ASYNC_SELECT_DISABLED \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) -#define CMU_SDIOREF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) -#define CMU_QSPI0REF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) -#define CMU_USBR_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFXOX2 \ - do { \ - EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ - CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) -#define CMU_PDMREF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ -#endif /* _SILICON_LABS_32B_SERIES_2 */ -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* SLI_EM_CMU_H */ +/***************************************************************************//** + * @file + * @brief Clock Management Unit Private API definition. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_EM_CMU_H +#define SLI_EM_CMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void); + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(void); + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void); + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void); + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void); + +#define CMU_SYSCLK_SELECT_HFRCODPLL \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#define CMU_SYSCLK_SELECT_HFXO \ + do { \ + sli_em_cmu_HFXOSetForceEnable(); \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ + } \ + } while (0) + +#define CMU_SYSCLK_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#define CMU_SYSCLK_SELECT_FSRCO \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#if defined(RFFPLL_PRESENT) + +#define CMU_SYSCLK_SELECT_RFFPLLSYS \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#endif /* RFFPLL_PRESENT */ + +#if defined(IADC_PRESENT) +#define CMU_IADCCLK_SELECT_EM01GRPACLK \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK + +#if defined(HFRCOEM23_PRESENT) +#define CMU_IADCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_IADCCLK_SELECT_FSRCO \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO +#endif /* IADC_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* KEYSCAN_PRESENT*/ + +#if defined(HFRCOEM23_PRESENT) +#define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* KEYSCAN_PRESENT*/ +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPACLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ + +#define CMU_SYSTICK_SELECT_EM23GRPACLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENSet(); \ + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK + +#define CMU_SYSTICK_SELECT_HCLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENClear(); \ + SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_EM23GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#endif /* LESENSE_PRESENT */ + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM23GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#endif /* LESENSE_PRESENT */ +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM23GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EM4GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM4GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM4GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO + +#define CMU_EM4GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO + +#define CMU_EM4GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL + +#define CMU_EM01GRPBCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO + +#define CMU_EM01GRPBCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO + +#define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 + +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT + +#define CMU_EM01GRPBCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT + +#define CMU_EM01GRPBCLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ + +#define CMU_WDOG0_SELECT_LFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG0_SELECT_PLFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG0_SELECT_LFXO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO + +#define CMU_WDOG0_SELECT_ULFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO + +#define CMU_WDOG0_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 + +#define CMU_WDOG0_SELECT_DISABLED \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +#define CMU_WDOG1_SELECT_LFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG1_SELECT_PLFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG1_SELECT_LFXO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO + +#define CMU_WDOG1_SELECT_ULFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO + +#define CMU_WDOG1_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 + +#define CMU_WDOG1_SELECT_DISABLED \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED +#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ + +#define CMU_DPLLREFCLK_SELECT_HFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_LFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_CLKIN0 \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_DISABLED \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) +#define CMU_TRACECLK_RESTORE_TRACE_PRE() \ + bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ + if (restoreTrace) { \ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#define CMU_TRACECLK_RESTORE_TRACE_POST() \ + if (restoreTrace) { \ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#else +#define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) +#define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define CMU_TRACECLK_SELECT_HCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + #define CMU_TRACECLK_SELECT_SYSCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#define CMU_TRACECLK_SELECT_HFRCODPLLRT \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_TRACECLK_SELECT_HFRCOEM23 \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +#define CMU_EUART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK + +#define CMU_EUART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK + +#define CMU_EUART0_SELECT_DISABLED \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED +#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ + +#if defined(EUSART_PRESENT) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) +#define CMU_EUSART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) +#define CMU_EUSART0_SELECT_EM01GRPCCLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) +#define CMU_EUSART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) +#define CMU_EUSART0_SELECT_FSRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_EUSART0_SELECT_HFRCOEM23 \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) +#define CMU_EUSART0_SELECT_LFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EUSART0_SELECT_PLFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) +#define CMU_EUSART0_SELECT_LFXO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) +#define CMU_EUSART0_SELECT_DISABLED \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ +#endif /* EUSART_PRESENT */ + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ + +#define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#define CMU_EM01GRPCCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#define CMU_EM01GRPCCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPCCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ +#endif /* _CMU_EM01GRPCCLKCTRL_MASK */ + +#if defined (RTCC_PRESENT) +#define CMU_RTCC_SELECT_LFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_RTCC_SELECT_PLFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_RTCC_SELECT_LFXO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO + +#define CMU_RTCC_SELECT_ULFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO + +#endif /* RTCC_PRESENT */ + +#if defined(SYSRTC_PRESENT) +#define CMU_SYSRTC_SELECT_LFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_SYSRTC_SELECT_PLFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_SYSRTC_SELECT_LFXO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO + +#define CMU_SYSRTC_SELECT_ULFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO + +#define CMU_SYSRTC_SELECT_DISABLED \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED +#endif /* SYSRTC_PRESENT */ + +#if defined(LCD_PRESENT) +#define CMU_LCD_SELECT_LFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_LCD_SELECT_PLFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_LCD_SELECT_LFXO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO + +#define CMU_LCD_SELECT_ULFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO +#endif /* LCD_PRESENT */ + +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_SELECT_FSRCO \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO + +#define CMU_VDAC0_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 + +#define CMU_VDAC0_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK + +#define CMU_VDAC0_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK + +#if (VDAC_COUNT > 1) +#define CMU_VDAC1_SELECT_FSRCO \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO + +#define CMU_VDAC1_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 + +#define CMU_VDAC1_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK + +#define CMU_VDAC1_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK +#endif /* VDAC_COUNT > 1 */ +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +#define CMU_PCNT0_SELECT_EM23GRPACLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK + +#define CMU_PCNT0_SELECT_PCNTEXTCLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK +#endif /* PCNT_PRESENT */ + +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHFCLK_SELECT_FSRCO \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) +#endif /* LESENSE_PRESENT */ + +#if defined(USB_PRESENT) +#define CMU_USB_SELECT_USBPLL0 \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ + } while (0) + +#define CMU_USB_SELECT_LFXO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_USB_SELECT_LFRCO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) +#endif /* USB_PRESENT */ + +#elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @param[in]osc + * Reference to a low-frequency oscillator. One of the following values is valid: + * - cmuOsc_LFXO + * - cmuOsc_LFRCO + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void); + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void); +#endif + +#define CMU_HF_SELECT_LFXO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ + } while (0) + +#define CMU_HF_SELECT_LFRCO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ + } while (0) + +#define CMU_HF_SELECT_HFXO \ + do { \ + sli_em_cmu_HFClockSelectHFXO(); \ + } while (0) + +#define CMU_HF_SELECT_HFRCO \ + do { \ + sli_em_cmu_HFClockSelectHFRCO(); \ + } while (0) + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +#define CMU_HF_SELECT_USHFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +#define CMU_HF_SELECT_HFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +#define CMU_HF_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_HFClockSelectCLKIN0(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +#define CMU_HF_SELECT_USHFRCO \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCO(); \ + } while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ + } while (0) + +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFA_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigHFClock(); \ + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ + } while (0) + +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFB_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#if defined(_CMU_LFCCLKSEL_MASK) +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ + } while (0) + +#define CMU_LFC_SELECT_ULFRCO \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ + } while (0) + +#endif /* _CMU_LFCCLKSEL_MASK */ + +#define CMU_LFE_SELECT_DISABLED \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ + } while (0) + +#define CMU_LFE_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ + } while (0) + +#define CMU_LFE_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ + } while (0) + +#define CMU_LFE_SELECT_ULFRCO \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFE_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ +#endif /* _SILICON_LABS_32B_SERIES_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_CMU_LFCLKSEL_LFAE_MASK) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) +#endif /* CMU_LFA_SELECT_HFCLKLE */ +#endif /* _CMU_LFCLKSEL_LFAE_MASK */ + +#if defined(_CMU_LFCLKSEL_LFBE_MASK) +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) +#endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ +#endif /* _CMU_LFCLKSEL_LFBE_MASK */ + +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) +#endif /* _SILICON_LABS_32B_SERIES_0 */ + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ + } while (0) +#endif /* _CMU_DBGCLKSEL_DBG_MASK */ + +#if defined(CMU_CTRL_DBGCLK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_HFCLK; \ + } while (0) +#endif /* CMU_CTRL_DBGCLK */ + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define CMU_USBC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ + } while (0) + +#define CMU_USBC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ + } while (0) + +#if defined(CMU_STATUS_USBCHFCLKSEL) +#define CMU_USBC_SELECT_HFCLK \ + do { \ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ + } while (0) +#endif /* CMU_STATUS_USBCHFCLKSEL */ + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) +#define CMU_USBC_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ + } while (0) +#endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ +#endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +#define CMU_ADC0ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) +#define CMU_ADC1ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) +#define CMU_SDIOREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) +#define CMU_QSPI0REF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) +#define CMU_USBR_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXOX2 \ + do { \ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) +#define CMU_PDMREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ +#endif /* _SILICON_LABS_32B_SERIES_2 */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_EM_CMU_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_acmp.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_acmp.c index ebb7560..a3e8388 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_acmp.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_acmp.c @@ -1,709 +1,709 @@ -/***************************************************************************//** - * @file - * @brief Analog Comparator (ACMP) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_acmp.h" -#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) - -#include -#include "em_bus.h" -#include "sl_assert.h" -#include "em_gpio.h" - -/***************************************************************************//** - * @addtogroup acmp ACMP - Analog Comparator - * @brief Analog comparator (ACMP) Peripheral API - * - * @details - * The Analog Comparator is used to compare voltage of two analog inputs - * with a digital output indicating which input voltage is higher. Inputs can - * either be one of the selectable internal references or from external pins. - * Response time and current consumption can be configured by - * altering the current supply to the comparator. - * - * ACMP is available down to EM3 and is able to wake up the system when - * input signals pass a certain threshold. Use @ref ACMP_IntEnable() to enable - * an edge interrupt to use this functionality. - * - * This example shows how to use the em_acmp.h API for comparing an input - * pin to an internal 2.5 V reference voltage. - * - * @if DOXYDOC_P1_DEVICE - * @include em_acmp_compare_s0.c - * @endif - * - * @if DOXYDOC_P2_DEVICE - * @include em_acmp_compare_s1.c - * @endif - * - * @if DOXYDOC_S2_DEVICE - * @include em_acmp_compare_s2.c - * @endif - * - * @note - * ACMP can also be used to compare two separate input pins. - * - * @details - * ACMP also contains specialized hardware for capacitive sensing. This - * module contains the @ref ACMP_CapsenseInit() function to initialize - * ACMP for capacitive sensing and the @ref ACMP_CapsenseChannelSet() function - * to select the current capsense channel. - * - * For applications that require capacitive sensing it is recommended to use a - * library, such as cslib, which is provided by Silicon Labs. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of ACMP register block pointer reference - * for assert statements. */ -#if (ACMP_COUNT == 1) -#define ACMP_REF_VALID(ref) ((ref) == ACMP0) -#elif (ACMP_COUNT == 2) -#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1)) -#elif (ACMP_COUNT == 3) -#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1) || ((ref) == ACMP2)) -#elif (ACMP_COUNT == 4) -#define ACMP_REF_VALID(ref) (((ref) == ACMP0) \ - || ((ref) == ACMP1) \ - || ((ref) == ACMP2) \ - || ((ref) == ACMP3)) -#else -#error Undefined number of analog comparators (ACMP). -#endif - -/** The maximum value that can be inserted in the route location register - * for the specific device. */ -#if defined(_ACMP_ROUTE_LOCATION_LOC3) -#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC3 -#elif defined(_ACMP_ROUTE_LOCATION_LOC2) -#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC2 -#elif defined(_ACMP_ROUTE_LOCATION_LOC1) -#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC1 -#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31) -#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_LOC31 -#elif defined(_ACMP_ROUTELOC0_OUTLOC_MASK) -#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_MASK -#endif - -/** Map ACMP reference to index of device. */ -#if (ACMP_COUNT == 1) -#define ACMP_DEVICE_ID(acmp) ( \ - (acmp) == ACMP0 ? 0 \ - : 0) -#elif (ACMP_COUNT == 2) -#define ACMP_DEVICE_ID(acmp) ( \ - (acmp) == ACMP0 ? 0 \ - : (acmp) == ACMP1 ? 1 \ - : 0) -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Set up ACMP for use in capacitive sense applications. - * - * @details - * This function sets up ACMP for use in capacitive sense applications. - * To use the capacitive sense functionality in the ACMP, use - * the PRS output of the ACMP module to count the number of oscillations - * in the capacitive sense circuit (possibly using a TIMER). - * - * @note - * A basic example of capacitive sensing can be found in the STK BSP - * (capsense demo). - * - * @cond DOXYDOC_S2_DEVICE - * @note - * A call to ACMP_CapsenseInit will enable and disable the ACMP peripheral, - * which can cause side effects if it was previously set up. - * @endcond - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure ACMP for capacitive - * sensing operation. - ******************************************************************************/ -void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init) -{ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(init->vrefDiv < 64); - EFM_ASSERT(init->biasProg - <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); - - ACMP_Disable(acmp); - acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) - | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); - acmp->CTRL = _ACMP_CTRL_RESETVALUE; - ACMP_Enable(acmp); - acmp->INPUTCTRL = (init->resistor << _ACMP_INPUTCTRL_CSRESSEL_SHIFT) - | (init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT) - | (ACMP_INPUTCTRL_NEGSEL_CAPSENSE); - if (!init->enable) { - ACMP_Disable(acmp); - } - -#elif defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT(init->vddLevelLow < 64); - EFM_ASSERT(init->vddLevelHigh < 64); - EFM_ASSERT(init->biasProg - <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); - - /* Set the control register. No need to set interrupt modes. */ - acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) - | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) - | ACMP_CTRL_ACCURACY_HIGH; - acmp->HYSTERESIS0 = (init->vddLevelHigh << _ACMP_HYSTERESIS0_DIVVA_SHIFT) - | (init->hysteresisLevel_0 << _ACMP_HYSTERESIS0_HYST_SHIFT); - acmp->HYSTERESIS1 = (init->vddLevelLow << _ACMP_HYSTERESIS1_DIVVA_SHIFT) - | (init->hysteresisLevel_1 << _ACMP_HYSTERESIS1_HYST_SHIFT); - /* Select capacitive sensing mode by selecting a resistor and enabling it. */ - acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) - | ACMP_INPUTSEL_CSRESEN - | ACMP_INPUTSEL_VASEL_VDD - | ACMP_INPUTSEL_NEGSEL_VADIV; - BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); - -#elif defined(_SILICON_LABS_32B_SERIES_0) - EFM_ASSERT(init->vddLevel < 64); - EFM_ASSERT(init->biasProg - <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); - - /* Set the control register. No need to set interrupt modes. */ - acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) - | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) - | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) - | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) - | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT); - /* Select capacitive sensing mode by selecting a resistor and enabling it. */ - acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) - | ACMP_INPUTSEL_CSRESEN - | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) - | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT) - | ACMP_INPUTSEL_NEGSEL_CAPSENSE; - BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); -#endif -} - -/***************************************************************************//** - * @brief - * Set the ACMP channel used for capacitive sensing. - * - * @note - * A basic example of capacitive sensing can be found in the STK BSP - * (capsense demo). - * - * @cond DOXYDOC_S2_DEVICE - * @note - * Can only be called when the peripheral is enabled. - * @endcond - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] channel - * The ACMP channel to use for capacitive sensing (Possel). - ******************************************************************************/ -void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_ACMP_INPUTSEL_POSSEL_CH7) - /* Make sure that only external channels are used. */ - EFM_ASSERT(channel <= _ACMP_INPUTSEL_POSSEL_CH7); -#elif defined(_ACMP_INPUTCTRL_POSSEL_PD15) - EFM_ASSERT(channel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); - EFM_ASSERT(_ACMP_INPUTCTRL_POSSEL_PA0 <= channel); - EFM_ASSERT(channel <= _ACMP_INPUTCTRL_POSSEL_PD15); -#endif - -#if defined(_ACMP_INPUTCTRL_MASK) - /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ - EFM_ASSERT(acmp->EN & ACMP_EN_EN); - - while (acmp->SYNCBUSY != 0U) { - /* Wait for synchronization to finish */ - } - /* Set channel as positive channel in ACMP */ - BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_POSSEL_MASK, - channel << _ACMP_INPUTCTRL_POSSEL_SHIFT); -#else - /* Set channel as a positive channel in ACMP. */ - BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, - channel << _ACMP_INPUTSEL_POSSEL_SHIFT); -#endif -} - -/***************************************************************************//** - * @brief - * Disable ACMP. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - ******************************************************************************/ -void ACMP_Disable(ACMP_TypeDef *acmp) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_ACMP_EN_MASK) - while ((acmp->EN != 0U) && (acmp->SYNCBUSY != 0U)) { - /* Wait for synchronization to finish */ - } - acmp->EN_CLR = ACMP_EN_EN; - -#if defined(_ACMP_EN_DISABLING_MASK) - while (acmp->EN & _ACMP_EN_DISABLING_MASK) { - // Wait for disabling to finish - } -#endif - -#else - acmp->CTRL &= ~ACMP_CTRL_EN; -#endif -} - -/***************************************************************************//** - * @brief - * Enable ACMP. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - ******************************************************************************/ -void ACMP_Enable(ACMP_TypeDef *acmp) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_ACMP_EN_MASK) - acmp->EN_SET = ACMP_EN_EN; -#else - acmp->CTRL |= ACMP_CTRL_EN; -#endif -} - -#if defined(_ACMP_EXTIFCTRL_MASK) -/***************************************************************************//** - * @brief - * Select and enable external input. - * - * @details - * This is used when an external module needs to take control of the ACMP - * POSSEL field to configure the APORT input for the ACMP. Modules, - * such as LESENSE, use this to change the ACMP input during a scan sequence. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] aport - * This parameter decides which APORT(s) the ACMP will use when it's - * controlled by an external module. - ******************************************************************************/ -void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) -{ - acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) - | ACMP_EXTIFCTRL_EN; - while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) { - } -} -#endif - -/***************************************************************************//** - * @brief - * Reset ACMP to the same state that it was in after a hardware reset. - * - * @note - * The GPIO ACMP ROUTE register is NOT reset by this function to allow for - * centralized setup of this feature. - * - * @note - * The peripheral may be enabled and disabled during reset. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - ******************************************************************************/ -void ACMP_Reset(ACMP_TypeDef *acmp) -{ - /* Make sure the module exists on the selected chip */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_SILICON_LABS_32B_SERIES_2) -#if defined(ACMP_SWRST_SWRST) - acmp->SWRST_SET = ACMP_SWRST_SWRST; - while (acmp->SWRST & _ACMP_SWRST_RESETTING_MASK) { - } -#else - acmp->IEN = _ACMP_IEN_RESETVALUE; - ACMP_Enable(acmp); - acmp->INPUTCTRL = _ACMP_INPUTCTRL_RESETVALUE; - ACMP_Disable(acmp); - acmp->CFG = PM5507_ACMP_CFG_RESETVALUE; - acmp->CTRL = _ACMP_CTRL_RESETVALUE; - acmp->IF_CLR = _ACMP_IF_MASK; -#endif -#else // Series 0 and Series 1 devices - acmp->IEN = _ACMP_IEN_RESETVALUE; - acmp->CTRL = _ACMP_CTRL_RESETVALUE; - acmp->INPUTSEL = _ACMP_INPUTSEL_RESETVALUE; -#if defined(_ACMP_HYSTERESIS0_HYST_MASK) - acmp->HYSTERESIS0 = _ACMP_HYSTERESIS0_RESETVALUE; - acmp->HYSTERESIS1 = _ACMP_HYSTERESIS1_RESETVALUE; -#endif - acmp->IFC = _ACMP_IF_MASK; -#endif -} - -#if defined(_GPIO_ACMP_ROUTEEN_MASK) -/***************************************************************************//** - * @brief - * Sets up GPIO output from the ACMP. - * - * @note - * GPIO must be enabled in the CMU before this function call, i.e. - * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim - * - * @param[in] acmp - * Pointer to the ACMP peripheral register block. - * - * @param port - * The GPIO port to use. - * - * @param pin - * The GPIO pin to use. - * - * @param enable - * Enable or disable pin output. - * - * @param invert - * Invert output. - ******************************************************************************/ -void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, - unsigned int pin, bool enable, bool invert) -{ - int acmpIndex = ACMP_DEVICE_ID(acmp); - - /* Make sure the module exists on the selected chip */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - - /* Make sure that the port/pin combination is valid. */ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - /* Set GPIO inversion */ - acmp->CTRL = (acmp->CTRL & _ACMP_CTRL_NOTRDYVAL_MASK) - | (invert << _ACMP_CTRL_GPIOINV_SHIFT); - - GPIO->ACMPROUTE[acmpIndex].ACMPOUTROUTE = (port << _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT) - | (pin << _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT); - GPIO->ACMPROUTE[acmpIndex].ROUTEEN = enable ? GPIO_ACMP_ROUTEEN_ACMPOUTPEN : 0; -} -#else -/***************************************************************************//** - * @brief - * Set up GPIO output from ACMP. - * - * @note - * GPIO must be enabled in the CMU before this function call, i.e., - * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param location - * The pin location to use. See the data sheet for location to pin mappings. - * - * @param enable - * Enable or disable pin output. - * - * @param invert - * Invert output. - ******************************************************************************/ -void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert) -{ - /* Make sure the module exists on the selected chip */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - - /* Sanity checking of location */ - EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_MAX); - - /* Set GPIO inversion */ - BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, - invert << _ACMP_CTRL_GPIOINV_SHIFT); - -#if defined(_ACMP_ROUTE_MASK) - acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT) - | (enable << _ACMP_ROUTE_ACMPPEN_SHIFT); -#endif -#if defined(_ACMP_ROUTELOC0_MASK) - acmp->ROUTELOC0 = location << _ACMP_ROUTELOC0_OUTLOC_SHIFT; - acmp->ROUTEPEN = enable ? ACMP_ROUTEPEN_OUTPEN : 0; -#endif -} -#endif /* defined(_GPIO_ACMP_ROUTEEN_MASK) */ - -/***************************************************************************//** - * @brief - * Set which channels should be used in ACMP comparisons. - * - * @cond DOXYDOC_S2_DEVICE - * @note - * Can only be called when the peripheral is enabled. - * - * @note - * If GPIO is used for both posSel and negSel, they cannot both use even - * or odd pins. - * @endcond - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param negSel - * A channel to use on the negative input to the ACMP. - * - * @param posSel - * A channel to use on the positive input to the ACMP. - ******************************************************************************/ -void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, - ACMP_Channel_TypeDef posSel) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - - /* Make sure that posSel and negSel channel selectors are valid. */ -#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) - EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_DAC0CH1); -#elif defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) - EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_CAPSENSE); -#endif - -#if defined(_ACMP_INPUTSEL_POSSEL_CH7) - EFM_ASSERT(posSel <= _ACMP_INPUTSEL_POSSEL_CH7); -#endif - - /* Make sure that posSel and negSel channel selectors are valid. */ -#if defined(_ACMP_INPUTCTRL_POSSEL_PD15) - EFM_ASSERT(negSel <= _ACMP_INPUTCTRL_POSSEL_PD15); - EFM_ASSERT(posSel <= _ACMP_INPUTCTRL_POSSEL_PD15); - EFM_ASSERT(posSel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); - - /* Make sure that posSel and negSel channel selectors don't both - * use odd or even pins. */ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - EFM_ASSERT(!((((posSel >= _ACMP_INPUTCTRL_POSSEL_EXTPA) - && (posSel <= _ACMP_INPUTCTRL_POSSEL_EXTPD)) - || (posSel >= _ACMP_INPUTCTRL_POSSEL_PA0)) - && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) - && (posSel % 2 == negSel % 2))); -#else - EFM_ASSERT(!((posSel >= _ACMP_INPUTCTRL_POSSEL_PA0) - && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) - && (posSel % 2 == negSel % 2))); - -#endif -#endif - -#if defined(_ACMP_INPUTCTRL_MASK) - /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ - EFM_ASSERT(acmp->EN & ACMP_EN_EN); - while (acmp->SYNCBUSY != 0U) { - /* Wait for synchronization to finish */ - } - acmp->INPUTCTRL = (acmp->INPUTCTRL & ~(_ACMP_INPUTCTRL_POSSEL_MASK - | _ACMP_INPUTCTRL_NEGSEL_MASK)) - | (negSel << _ACMP_INPUTCTRL_NEGSEL_SHIFT) - | (posSel << _ACMP_INPUTCTRL_POSSEL_SHIFT); -#else - acmp->INPUTSEL = (acmp->INPUTSEL & ~(_ACMP_INPUTSEL_POSSEL_MASK - | _ACMP_INPUTSEL_NEGSEL_MASK)) - | (negSel << _ACMP_INPUTSEL_NEGSEL_SHIFT) - | (posSel << _ACMP_INPUTSEL_POSSEL_SHIFT); -#endif -} - -/***************************************************************************//** - * @brief - * Initialize ACMP. - * - * @cond DOXYDOC_S2_DEVICE - * @note - * A call to ACMP_Init can cause side effects since it can enable/disable - * the peripheral. - * @endcond - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure ACMP. - ******************************************************************************/ -void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(ACMP_REF_VALID(acmp)); - -#if defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(init->biasProg - <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); - -// PM-5507: enforce that biasProg is a functional value -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - EFM_ASSERT(init->biasProg >= 4); -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - // Allow customer to use BIASPROG in [2; 3] - EFM_ASSERT(init->biasProg >= 2); -#else - // Allow customer to use BIASPROG in [0; 3] - // but the implementation of the wait operation would be their responsibility -#endif - - /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ - ACMP_Disable(acmp); - - acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) - | (init->inputRange << _ACMP_CFG_INPUTRANGE_SHIFT) - | (init->accuracy << _ACMP_CFG_ACCURACY_SHIFT) - | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); - acmp->CTRL = init->inactiveValue << _ACMP_CTRL_NOTRDYVAL_SHIFT; - ACMP_Enable(acmp); - BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_VREFDIV_MASK, - init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT); - -#elif defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT(init->biasProg - <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); - /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ - ACMP_Disable(acmp); - - acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) - | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) - | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) - | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) - | (init->inputRange << _ACMP_CTRL_INPUTRANGE_SHIFT) - | (init->accuracy << _ACMP_CTRL_ACCURACY_SHIFT) - | (init->powerSource << _ACMP_CTRL_PWRSEL_SHIFT) - | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); - acmp->INPUTSEL = init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT; - acmp->HYSTERESIS0 = init->hysteresisLevel_0; - acmp->HYSTERESIS1 = init->hysteresisLevel_1; - -#elif defined(_SILICON_LABS_32B_SERIES_0) - EFM_ASSERT(init->biasProg - <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); - /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ - ACMP_Disable(acmp); - - acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) - | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) - | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) - | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) - | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) - | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) - | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT) - | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); - acmp->INPUTSEL = (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) - | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT); - -#endif - - if (init->enable) { - ACMP_Enable(acmp); - } else { - ACMP_Disable(acmp); - } -} - -#if defined(_ACMP_INPUTSEL_VASEL_MASK) -/***************************************************************************//** - * @brief - * Set up the VA source. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] vaconfig - * A pointer to the structure used to configure the VA source. This structure - * contains the input source and the 2 divider values. - ******************************************************************************/ -void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig) -{ - EFM_ASSERT(vaconfig->div0 < 64); - EFM_ASSERT(vaconfig->div1 < 64); - - BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK, - vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT); - BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK, - vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT); - BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK, - vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT); -} -#endif - -#if defined(_ACMP_INPUTSEL_VBSEL_MASK) -/***************************************************************************//** - * @brief - * Set up the VB Source. - * - * @param[in] acmp - * A pointer to the ACMP peripheral register block. - * - * @param[in] vbconfig - * A pointer to the structure used to configure the VB source. This structure - * contains the input source and the 2 divider values. - ******************************************************************************/ -void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig) -{ - EFM_ASSERT(vbconfig->div0 < 64); - EFM_ASSERT(vbconfig->div1 < 64); - - BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK, - vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT); - BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK, - vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT); - BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK, - vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT); -} -#endif - -/** @} (end addtogroup acmp) */ -#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Analog Comparator (ACMP) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_acmp.h" +#if defined(ACMP_COUNT) && (ACMP_COUNT > 0) + +#include +#include "em_bus.h" +#include "sl_assert.h" +#include "em_gpio.h" + +/***************************************************************************//** + * @addtogroup acmp ACMP - Analog Comparator + * @brief Analog comparator (ACMP) Peripheral API + * + * @details + * The Analog Comparator is used to compare voltage of two analog inputs + * with a digital output indicating which input voltage is higher. Inputs can + * either be one of the selectable internal references or from external pins. + * Response time and current consumption can be configured by + * altering the current supply to the comparator. + * + * ACMP is available down to EM3 and is able to wake up the system when + * input signals pass a certain threshold. Use @ref ACMP_IntEnable() to enable + * an edge interrupt to use this functionality. + * + * This example shows how to use the em_acmp.h API for comparing an input + * pin to an internal 2.5 V reference voltage. + * + * @if DOXYDOC_P1_DEVICE + * @include em_acmp_compare_s0.c + * @endif + * + * @if DOXYDOC_P2_DEVICE + * @include em_acmp_compare_s1.c + * @endif + * + * @if DOXYDOC_S2_DEVICE + * @include em_acmp_compare_s2.c + * @endif + * + * @note + * ACMP can also be used to compare two separate input pins. + * + * @details + * ACMP also contains specialized hardware for capacitive sensing. This + * module contains the @ref ACMP_CapsenseInit() function to initialize + * ACMP for capacitive sensing and the @ref ACMP_CapsenseChannelSet() function + * to select the current capsense channel. + * + * For applications that require capacitive sensing it is recommended to use a + * library, such as cslib, which is provided by Silicon Labs. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of ACMP register block pointer reference + * for assert statements. */ +#if (ACMP_COUNT == 1) +#define ACMP_REF_VALID(ref) ((ref) == ACMP0) +#elif (ACMP_COUNT == 2) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1)) +#elif (ACMP_COUNT == 3) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) || ((ref) == ACMP1) || ((ref) == ACMP2)) +#elif (ACMP_COUNT == 4) +#define ACMP_REF_VALID(ref) (((ref) == ACMP0) \ + || ((ref) == ACMP1) \ + || ((ref) == ACMP2) \ + || ((ref) == ACMP3)) +#else +#error Undefined number of analog comparators (ACMP). +#endif + +/** The maximum value that can be inserted in the route location register + * for the specific device. */ +#if defined(_ACMP_ROUTE_LOCATION_LOC3) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC3 +#elif defined(_ACMP_ROUTE_LOCATION_LOC2) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC2 +#elif defined(_ACMP_ROUTE_LOCATION_LOC1) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTE_LOCATION_LOC1 +#elif defined(_ACMP_ROUTELOC0_OUTLOC_LOC31) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_LOC31 +#elif defined(_ACMP_ROUTELOC0_OUTLOC_MASK) +#define _ACMP_ROUTE_LOCATION_MAX _ACMP_ROUTELOC0_OUTLOC_MASK +#endif + +/** Map ACMP reference to index of device. */ +#if (ACMP_COUNT == 1) +#define ACMP_DEVICE_ID(acmp) ( \ + (acmp) == ACMP0 ? 0 \ + : 0) +#elif (ACMP_COUNT == 2) +#define ACMP_DEVICE_ID(acmp) ( \ + (acmp) == ACMP0 ? 0 \ + : (acmp) == ACMP1 ? 1 \ + : 0) +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set up ACMP for use in capacitive sense applications. + * + * @details + * This function sets up ACMP for use in capacitive sense applications. + * To use the capacitive sense functionality in the ACMP, use + * the PRS output of the ACMP module to count the number of oscillations + * in the capacitive sense circuit (possibly using a TIMER). + * + * @note + * A basic example of capacitive sensing can be found in the STK BSP + * (capsense demo). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * A call to ACMP_CapsenseInit will enable and disable the ACMP peripheral, + * which can cause side effects if it was previously set up. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure ACMP for capacitive + * sensing operation. + ******************************************************************************/ +void ACMP_CapsenseInit(ACMP_TypeDef *acmp, const ACMP_CapsenseInit_TypeDef *init) +{ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(init->vrefDiv < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); + + ACMP_Disable(acmp); + acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) + | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + ACMP_Enable(acmp); + acmp->INPUTCTRL = (init->resistor << _ACMP_INPUTCTRL_CSRESSEL_SHIFT) + | (init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT) + | (ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + if (!init->enable) { + ACMP_Disable(acmp); + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(init->vddLevelLow < 64); + EFM_ASSERT(init->vddLevelHigh < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + + /* Set the control register. No need to set interrupt modes. */ + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | ACMP_CTRL_ACCURACY_HIGH; + acmp->HYSTERESIS0 = (init->vddLevelHigh << _ACMP_HYSTERESIS0_DIVVA_SHIFT) + | (init->hysteresisLevel_0 << _ACMP_HYSTERESIS0_HYST_SHIFT); + acmp->HYSTERESIS1 = (init->vddLevelLow << _ACMP_HYSTERESIS1_DIVVA_SHIFT) + | (init->hysteresisLevel_1 << _ACMP_HYSTERESIS1_HYST_SHIFT); + /* Select capacitive sensing mode by selecting a resistor and enabling it. */ + acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) + | ACMP_INPUTSEL_CSRESEN + | ACMP_INPUTSEL_VASEL_VDD + | ACMP_INPUTSEL_NEGSEL_VADIV; + BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(init->vddLevel < 64); + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + + /* Set the control register. No need to set interrupt modes. */ + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) + | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT); + /* Select capacitive sensing mode by selecting a resistor and enabling it. */ + acmp->INPUTSEL = (init->resistor << _ACMP_INPUTSEL_CSRESSEL_SHIFT) + | ACMP_INPUTSEL_CSRESEN + | (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) + | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT) + | ACMP_INPUTSEL_NEGSEL_CAPSENSE; + BUS_RegBitWrite(&acmp->CTRL, _ACMP_CTRL_EN_SHIFT, init->enable); +#endif +} + +/***************************************************************************//** + * @brief + * Set the ACMP channel used for capacitive sensing. + * + * @note + * A basic example of capacitive sensing can be found in the STK BSP + * (capsense demo). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Can only be called when the peripheral is enabled. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] channel + * The ACMP channel to use for capacitive sensing (Possel). + ******************************************************************************/ +void ACMP_CapsenseChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef channel) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_INPUTSEL_POSSEL_CH7) + /* Make sure that only external channels are used. */ + EFM_ASSERT(channel <= _ACMP_INPUTSEL_POSSEL_CH7); +#elif defined(_ACMP_INPUTCTRL_POSSEL_PD15) + EFM_ASSERT(channel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + EFM_ASSERT(_ACMP_INPUTCTRL_POSSEL_PA0 <= channel); + EFM_ASSERT(channel <= _ACMP_INPUTCTRL_POSSEL_PD15); +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) + /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ + EFM_ASSERT(acmp->EN & ACMP_EN_EN); + + while (acmp->SYNCBUSY != 0U) { + /* Wait for synchronization to finish */ + } + /* Set channel as positive channel in ACMP */ + BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_POSSEL_MASK, + channel << _ACMP_INPUTCTRL_POSSEL_SHIFT); +#else + /* Set channel as a positive channel in ACMP. */ + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_POSSEL_MASK, + channel << _ACMP_INPUTSEL_POSSEL_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Disable ACMP. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Disable(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_EN_MASK) + while ((acmp->EN != 0U) && (acmp->SYNCBUSY != 0U)) { + /* Wait for synchronization to finish */ + } + acmp->EN_CLR = ACMP_EN_EN; + +#if defined(_ACMP_EN_DISABLING_MASK) + while (acmp->EN & _ACMP_EN_DISABLING_MASK) { + // Wait for disabling to finish + } +#endif + +#else + acmp->CTRL &= ~ACMP_CTRL_EN; +#endif +} + +/***************************************************************************//** + * @brief + * Enable ACMP. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Enable(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_ACMP_EN_MASK) + acmp->EN_SET = ACMP_EN_EN; +#else + acmp->CTRL |= ACMP_CTRL_EN; +#endif +} + +#if defined(_ACMP_EXTIFCTRL_MASK) +/***************************************************************************//** + * @brief + * Select and enable external input. + * + * @details + * This is used when an external module needs to take control of the ACMP + * POSSEL field to configure the APORT input for the ACMP. Modules, + * such as LESENSE, use this to change the ACMP input during a scan sequence. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] aport + * This parameter decides which APORT(s) the ACMP will use when it's + * controlled by an external module. + ******************************************************************************/ +void ACMP_ExternalInputSelect(ACMP_TypeDef *acmp, ACMP_ExternalInput_Typedef aport) +{ + acmp->EXTIFCTRL = (aport << _ACMP_EXTIFCTRL_APORTSEL_SHIFT) + | ACMP_EXTIFCTRL_EN; + while (!(acmp->STATUS & ACMP_STATUS_EXTIFACT)) { + } +} +#endif + +/***************************************************************************//** + * @brief + * Reset ACMP to the same state that it was in after a hardware reset. + * + * @note + * The GPIO ACMP ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @note + * The peripheral may be enabled and disabled during reset. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + ******************************************************************************/ +void ACMP_Reset(ACMP_TypeDef *acmp) +{ + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(ACMP_SWRST_SWRST) + acmp->SWRST_SET = ACMP_SWRST_SWRST; + while (acmp->SWRST & _ACMP_SWRST_RESETTING_MASK) { + } +#else + acmp->IEN = _ACMP_IEN_RESETVALUE; + ACMP_Enable(acmp); + acmp->INPUTCTRL = _ACMP_INPUTCTRL_RESETVALUE; + ACMP_Disable(acmp); + acmp->CFG = PM5507_ACMP_CFG_RESETVALUE; + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + acmp->IF_CLR = _ACMP_IF_MASK; +#endif +#else // Series 0 and Series 1 devices + acmp->IEN = _ACMP_IEN_RESETVALUE; + acmp->CTRL = _ACMP_CTRL_RESETVALUE; + acmp->INPUTSEL = _ACMP_INPUTSEL_RESETVALUE; +#if defined(_ACMP_HYSTERESIS0_HYST_MASK) + acmp->HYSTERESIS0 = _ACMP_HYSTERESIS0_RESETVALUE; + acmp->HYSTERESIS1 = _ACMP_HYSTERESIS1_RESETVALUE; +#endif + acmp->IFC = _ACMP_IF_MASK; +#endif +} + +#if defined(_GPIO_ACMP_ROUTEEN_MASK) +/***************************************************************************//** + * @brief + * Sets up GPIO output from the ACMP. + * + * @note + * GPIO must be enabled in the CMU before this function call, i.e. + * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim + * + * @param[in] acmp + * Pointer to the ACMP peripheral register block. + * + * @param port + * The GPIO port to use. + * + * @param pin + * The GPIO pin to use. + * + * @param enable + * Enable or disable pin output. + * + * @param invert + * Invert output. + ******************************************************************************/ +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, GPIO_Port_TypeDef port, + unsigned int pin, bool enable, bool invert) +{ + int acmpIndex = ACMP_DEVICE_ID(acmp); + + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Make sure that the port/pin combination is valid. */ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + /* Set GPIO inversion */ + acmp->CTRL = (acmp->CTRL & _ACMP_CTRL_NOTRDYVAL_MASK) + | (invert << _ACMP_CTRL_GPIOINV_SHIFT); + + GPIO->ACMPROUTE[acmpIndex].ACMPOUTROUTE = (port << _GPIO_ACMP_ACMPOUTROUTE_PORT_SHIFT) + | (pin << _GPIO_ACMP_ACMPOUTROUTE_PIN_SHIFT); + GPIO->ACMPROUTE[acmpIndex].ROUTEEN = enable ? GPIO_ACMP_ROUTEEN_ACMPOUTPEN : 0; +} +#else +/***************************************************************************//** + * @brief + * Set up GPIO output from ACMP. + * + * @note + * GPIO must be enabled in the CMU before this function call, i.e., + * @verbatim CMU_ClockEnable(cmuClock_GPIO, true); @endverbatim + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param location + * The pin location to use. See the data sheet for location to pin mappings. + * + * @param enable + * Enable or disable pin output. + * + * @param invert + * Invert output. + ******************************************************************************/ +void ACMP_GPIOSetup(ACMP_TypeDef *acmp, uint32_t location, bool enable, bool invert) +{ + /* Make sure the module exists on the selected chip */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Sanity checking of location */ + EFM_ASSERT(location <= _ACMP_ROUTE_LOCATION_MAX); + + /* Set GPIO inversion */ + BUS_RegMaskedWrite(&acmp->CTRL, _ACMP_CTRL_GPIOINV_MASK, + invert << _ACMP_CTRL_GPIOINV_SHIFT); + +#if defined(_ACMP_ROUTE_MASK) + acmp->ROUTE = (location << _ACMP_ROUTE_LOCATION_SHIFT) + | (enable << _ACMP_ROUTE_ACMPPEN_SHIFT); +#endif +#if defined(_ACMP_ROUTELOC0_MASK) + acmp->ROUTELOC0 = location << _ACMP_ROUTELOC0_OUTLOC_SHIFT; + acmp->ROUTEPEN = enable ? ACMP_ROUTEPEN_OUTPEN : 0; +#endif +} +#endif /* defined(_GPIO_ACMP_ROUTEEN_MASK) */ + +/***************************************************************************//** + * @brief + * Set which channels should be used in ACMP comparisons. + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Can only be called when the peripheral is enabled. + * + * @note + * If GPIO is used for both posSel and negSel, they cannot both use even + * or odd pins. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param negSel + * A channel to use on the negative input to the ACMP. + * + * @param posSel + * A channel to use on the positive input to the ACMP. + ******************************************************************************/ +void ACMP_ChannelSet(ACMP_TypeDef *acmp, ACMP_Channel_TypeDef negSel, + ACMP_Channel_TypeDef posSel) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + + /* Make sure that posSel and negSel channel selectors are valid. */ +#if defined(_ACMP_INPUTSEL_NEGSEL_DAC0CH1) + EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_DAC0CH1); +#elif defined(_ACMP_INPUTSEL_NEGSEL_CAPSENSE) + EFM_ASSERT(negSel <= _ACMP_INPUTSEL_NEGSEL_CAPSENSE); +#endif + +#if defined(_ACMP_INPUTSEL_POSSEL_CH7) + EFM_ASSERT(posSel <= _ACMP_INPUTSEL_POSSEL_CH7); +#endif + + /* Make sure that posSel and negSel channel selectors are valid. */ +#if defined(_ACMP_INPUTCTRL_POSSEL_PD15) + EFM_ASSERT(negSel <= _ACMP_INPUTCTRL_POSSEL_PD15); + EFM_ASSERT(posSel <= _ACMP_INPUTCTRL_POSSEL_PD15); + EFM_ASSERT(posSel != _ACMP_INPUTCTRL_NEGSEL_CAPSENSE); + + /* Make sure that posSel and negSel channel selectors don't both + * use odd or even pins. */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + EFM_ASSERT(!((((posSel >= _ACMP_INPUTCTRL_POSSEL_EXTPA) + && (posSel <= _ACMP_INPUTCTRL_POSSEL_EXTPD)) + || (posSel >= _ACMP_INPUTCTRL_POSSEL_PA0)) + && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) + && (posSel % 2 == negSel % 2))); +#else + EFM_ASSERT(!((posSel >= _ACMP_INPUTCTRL_POSSEL_PA0) + && (negSel >= _ACMP_INPUTCTRL_NEGSEL_PA0) + && (posSel % 2 == negSel % 2))); + +#endif +#endif + +#if defined(_ACMP_INPUTCTRL_MASK) + /* Make sure that the ACMP is enabled before changing INPUTCTRL. */ + EFM_ASSERT(acmp->EN & ACMP_EN_EN); + while (acmp->SYNCBUSY != 0U) { + /* Wait for synchronization to finish */ + } + acmp->INPUTCTRL = (acmp->INPUTCTRL & ~(_ACMP_INPUTCTRL_POSSEL_MASK + | _ACMP_INPUTCTRL_NEGSEL_MASK)) + | (negSel << _ACMP_INPUTCTRL_NEGSEL_SHIFT) + | (posSel << _ACMP_INPUTCTRL_POSSEL_SHIFT); +#else + acmp->INPUTSEL = (acmp->INPUTSEL & ~(_ACMP_INPUTSEL_POSSEL_MASK + | _ACMP_INPUTSEL_NEGSEL_MASK)) + | (negSel << _ACMP_INPUTSEL_NEGSEL_SHIFT) + | (posSel << _ACMP_INPUTSEL_POSSEL_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Initialize ACMP. + * + * @cond DOXYDOC_S2_DEVICE + * @note + * A call to ACMP_Init can cause side effects since it can enable/disable + * the peripheral. + * @endcond + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure ACMP. + ******************************************************************************/ +void ACMP_Init(ACMP_TypeDef *acmp, const ACMP_Init_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(ACMP_REF_VALID(acmp)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(init->biasProg + <= (_ACMP_CFG_BIAS_MASK >> _ACMP_CFG_BIAS_SHIFT)); + +// PM-5507: enforce that biasProg is a functional value +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT(init->biasProg >= 4); +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Allow customer to use BIASPROG in [2; 3] + EFM_ASSERT(init->biasProg >= 2); +#else + // Allow customer to use BIASPROG in [0; 3] + // but the implementation of the wait operation would be their responsibility +#endif + + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CFG = (init->biasProg << _ACMP_CFG_BIAS_SHIFT) + | (init->inputRange << _ACMP_CFG_INPUTRANGE_SHIFT) + | (init->accuracy << _ACMP_CFG_ACCURACY_SHIFT) + | (init->hysteresisLevel << _ACMP_CFG_HYST_SHIFT); + acmp->CTRL = init->inactiveValue << _ACMP_CTRL_NOTRDYVAL_SHIFT; + ACMP_Enable(acmp); + BUS_RegMaskedWrite(&acmp->INPUTCTRL, _ACMP_INPUTCTRL_VREFDIV_MASK, + init->vrefDiv << _ACMP_INPUTCTRL_VREFDIV_SHIFT); + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) + | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) + | (init->inputRange << _ACMP_CTRL_INPUTRANGE_SHIFT) + | (init->accuracy << _ACMP_CTRL_ACCURACY_SHIFT) + | (init->powerSource << _ACMP_CTRL_PWRSEL_SHIFT) + | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); + acmp->INPUTSEL = init->vlpInput << _ACMP_INPUTSEL_VLPSEL_SHIFT; + acmp->HYSTERESIS0 = init->hysteresisLevel_0; + acmp->HYSTERESIS1 = init->hysteresisLevel_1; + +#elif defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(init->biasProg + <= (_ACMP_CTRL_BIASPROG_MASK >> _ACMP_CTRL_BIASPROG_SHIFT)); + /* Make sure the ACMP is disabled since ACMP power source might be changed.*/ + ACMP_Disable(acmp); + + acmp->CTRL = (init->fullBias << _ACMP_CTRL_FULLBIAS_SHIFT) + | (init->halfBias << _ACMP_CTRL_HALFBIAS_SHIFT) + | (init->biasProg << _ACMP_CTRL_BIASPROG_SHIFT) + | (init->interruptOnFallingEdge << _ACMP_CTRL_IFALL_SHIFT) + | (init->interruptOnRisingEdge << _ACMP_CTRL_IRISE_SHIFT) + | (init->warmTime << _ACMP_CTRL_WARMTIME_SHIFT) + | (init->hysteresisLevel << _ACMP_CTRL_HYSTSEL_SHIFT) + | (init->inactiveValue << _ACMP_CTRL_INACTVAL_SHIFT); + acmp->INPUTSEL = (init->lowPowerReferenceEnabled << _ACMP_INPUTSEL_LPREF_SHIFT) + | (init->vddLevel << _ACMP_INPUTSEL_VDDLEVEL_SHIFT); + +#endif + + if (init->enable) { + ACMP_Enable(acmp); + } else { + ACMP_Disable(acmp); + } +} + +#if defined(_ACMP_INPUTSEL_VASEL_MASK) +/***************************************************************************//** + * @brief + * Set up the VA source. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] vaconfig + * A pointer to the structure used to configure the VA source. This structure + * contains the input source and the 2 divider values. + ******************************************************************************/ +void ACMP_VASetup(ACMP_TypeDef *acmp, const ACMP_VAConfig_TypeDef *vaconfig) +{ + EFM_ASSERT(vaconfig->div0 < 64); + EFM_ASSERT(vaconfig->div1 < 64); + + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VASEL_MASK, + vaconfig->input << _ACMP_INPUTSEL_VASEL_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVA_MASK, + vaconfig->div0 << _ACMP_HYSTERESIS0_DIVVA_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVA_MASK, + vaconfig->div1 << _ACMP_HYSTERESIS1_DIVVA_SHIFT); +} +#endif + +#if defined(_ACMP_INPUTSEL_VBSEL_MASK) +/***************************************************************************//** + * @brief + * Set up the VB Source. + * + * @param[in] acmp + * A pointer to the ACMP peripheral register block. + * + * @param[in] vbconfig + * A pointer to the structure used to configure the VB source. This structure + * contains the input source and the 2 divider values. + ******************************************************************************/ +void ACMP_VBSetup(ACMP_TypeDef *acmp, const ACMP_VBConfig_TypeDef *vbconfig) +{ + EFM_ASSERT(vbconfig->div0 < 64); + EFM_ASSERT(vbconfig->div1 < 64); + + BUS_RegMaskedWrite(&acmp->INPUTSEL, _ACMP_INPUTSEL_VBSEL_MASK, + vbconfig->input << _ACMP_INPUTSEL_VBSEL_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS0, _ACMP_HYSTERESIS0_DIVVB_MASK, + vbconfig->div0 << _ACMP_HYSTERESIS0_DIVVB_SHIFT); + BUS_RegMaskedWrite(&acmp->HYSTERESIS1, _ACMP_HYSTERESIS1_DIVVB_MASK, + vbconfig->div1 << _ACMP_HYSTERESIS1_DIVVB_SHIFT); +} +#endif + +/** @} (end addtogroup acmp) */ +#endif /* defined(ACMP_COUNT) && (ACMP_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c index fef386c..3bf0608 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c @@ -1,431 +1,431 @@ -/***************************************************************************//** - * @file - * @brief Backup Real Time Counter (BURTC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_burtc.h" -#if defined(BURTC_PRESENT) - -/***************************************************************************//** - * @addtogroup burtc BURTC - Backup RTC - * @brief Backup Real Time Counter (BURTC) Peripheral API - * @details - * This module contains functions to control the BURTC peripheral of Silicon - * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all - * energy modes. The Backup RTC is also available when the system is in backup - * mode. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/***************************************************************************//** - * @brief Convert dividend to a prescaler logarithmic value. Only works for even - * numbers equal to 2^n. - * @param[in] div Unscaled dividend, - * @return Base 2 logarithm of input, as used by fixed prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t divToLog2(uint32_t div) -{ - uint32_t log2; - - /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ - EFM_ASSERT((div > 0UL) && (div <= 32768UL)); - - /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ - log2 = (31UL - __CLZ(div)); - - return log2; -} - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to low frequency domain to complete. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void regSync(uint32_t mask) -{ -#if defined(_BURTC_FREEZE_MASK) - /* Avoid deadlock if modifying the same register twice when freeze mode is - activated or when a clock is not selected for the BURTC. If a clock is - not selected, then the sync is done once the clock source is set. */ - if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) - || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) - || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { - return; - } -#endif - - /* Wait for any pending previous write operation to complete */ - /* in low frequency domain. This is only required for the Gecko Family. */ - while ((BURTC->SYNCBUSY & mask) != 0U) { - } -} -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief Initialize BURTC. - * - * @details - * Configures the BURTC peripheral. - * - * @note - * Before initialization, BURTC module must first be enabled by clearing the - * reset bit in the RMU, i.e., - * @verbatim - * RMU_ResetControl(rmuResetBU, rmuResetModeClear); - * @endverbatim - * Compare channel 0 must be configured outside this function, before - * initialization if enable is set to true. The counter will always be reset. - * - * @param[in] burtcInit - * A pointer to the BURTC initialization structure. - ******************************************************************************/ -void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - uint32_t ctrl; - uint32_t presc; - - /* Check initializer structure integrity. */ - EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); - /* Clock divider must be between 1 and 128, really on the form 2^n. */ - EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); - - /* Ignored compare bits during low power operation must be less than 7. */ - /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ - EFM_ASSERT(burtcInit->lowPowerComp <= 6); - /* You cannot enable the BURTC if mode is set to disabled. */ - EFM_ASSERT((burtcInit->enable == false) - || ((burtcInit->enable == true) - && (burtcInit->mode != burtcModeDisable))); - /* Low power mode is only available with LFRCO or LFXO as clock source. */ - EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) - || ((burtcInit->clkSel == burtcClkSelULFRCO) - && (burtcInit->lowPowerMode == burtcLPDisable))); - - /* Calculate a prescaler value from the clock divider input. */ - /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of - value 1 will select a 2 kHz ULFRCO clock, while any other value will - select a 1 kHz ULFRCO clock source. */ - presc = divToLog2(burtcInit->clkDiv); - - /* Make sure all registers are updated simultaneously. */ - if (burtcInit->enable) { - BURTC_FreezeEnable(true); - } - - /* Modification of LPMODE register requires sync with potential ongoing - * register updates in LF domain. */ - regSync(BURTC_SYNCBUSY_LPMODE); - - /* Configure low power mode. */ - BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); - - /* New configuration. */ - ctrl = (BURTC_CTRL_RSTEN - | (burtcInit->mode) - | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) - | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) - | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) - | (presc << _BURTC_CTRL_PRESC_SHIFT) - | (burtcInit->clkSel) - | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); - - /* Clear interrupts. */ - BURTC_IntClear(0xFFFFFFFF); - - /* Set the new configuration. */ - BURTC->CTRL = ctrl; - - /* Enable BURTC and counter. */ - if (burtcInit->enable) { - /* To enable BURTC counter, disable reset. */ - BURTC_Enable(true); - - /* Clear freeze. */ - BURTC_FreezeEnable(false); - } -#elif defined(_SILICON_LABS_32B_SERIES_2) - uint32_t presc; - - presc = divToLog2(burtcInit->clkDiv); - - if (BURTC->EN != 0U) { - BURTC_SyncWait(); - } - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_SYNCBUSY_EN_MASK) - regSync(BURTC_SYNCBUSY_EN); -#elif defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - - BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) - | ((burtcInit->compare0Top ? 1UL : 0UL) << _BURTC_CFG_COMPTOP_SHIFT) - | ((burtcInit->debugRun ? 1UL : 0UL) << _BURTC_CFG_DEBUGRUN_SHIFT); - BURTC->EM4WUEN = ((burtcInit->em4comp ? 1UL : 0UL) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) - | ((burtcInit->em4overflow ? 1UL : 0UL) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); - BURTC->EN_SET = BURTC_EN_EN; - if (burtcInit->start) { - BURTC_Start(); - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Enable or Disable BURTC peripheral. - * - * @param[in] enable - * true to enable, false to disable. - ******************************************************************************/ -void BURTC_Enable(bool enable) -{ -#if defined(_BURTC_SYNCBUSY_EN_MASK) - regSync(BURTC_SYNCBUSY_EN); -#endif - - if ((BURTC->EN == 0U) && !enable) { - /* Trying to disable BURTC when it's already disabled */ - return; - } - - if (BURTC->EN != 0U) { - /* Modifying the enable bit while synchronization is active will BusFault */ - BURTC_SyncWait(); - } - - if (enable) { - BURTC->EN_SET = BURTC_EN_EN; - } else { - BURTC_Stop(); - BURTC_SyncWait(); /* Wait for the stop to synchronize */ - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - } -} -#elif defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Enable or Disable BURTC peripheral reset and start counter - * @param[in] enable - * If true; asserts reset to BURTC, halts counter, if false; deassert reset - ******************************************************************************/ -void BURTC_Enable(bool enable) -{ - /* Note! If mode is disabled, BURTC counter will not start */ - EFM_ASSERT(((enable == true) - && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) - != BURTC_CTRL_MODE_DISABLE)) - || (enable == false)); - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); -} -#endif - -/***************************************************************************//** - * @brief Set BURTC compare channel. - * - * @param[in] comp Compare the channel index, must be 0 for current devices. - * - * @param[in] value New compare value. - ******************************************************************************/ -void BURTC_CompareSet(unsigned int comp, uint32_t value) -{ - (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ - - EFM_ASSERT(comp == 0U); - -#if defined(_BURTC_COMP0_MASK) - /* Modification of COMP0 register requires sync with potential ongoing - * register updates in LF domain. */ - regSync(BURTC_SYNCBUSY_COMP0); - - /* Configure compare channel 0/. */ - BURTC->COMP0 = value; -#else - /* Wait for last potential write to complete. */ - regSync(BURTC_SYNCBUSY_COMP); - - /* Configure compare channel 0 */ - BURTC->COMP = value; - regSync(BURTC_SYNCBUSY_COMP); -#endif -} - -/***************************************************************************//** - * @brief Get the BURTC compare value. - * - * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. - * - * @return The currently configured value for this compare channel. - ******************************************************************************/ -uint32_t BURTC_CompareGet(unsigned int comp) -{ - (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ - - EFM_ASSERT(comp == 0U); -#if defined(_BURTC_COMP0_MASK) - return BURTC->COMP0; -#else - return BURTC->COMP; -#endif -} - -/***************************************************************************//** - * @brief Reset counter - ******************************************************************************/ -void BURTC_CounterReset(void) -{ -#if defined(_BURTC_CTRL_MASK) - /* Set and clear reset bit */ - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); -#else - BURTC_Stop(); - BURTC->CNT = 0U; - BURTC_Start(); -#endif -} - -/***************************************************************************//** - * @brief - * Restore BURTC to reset state. - * @note - * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. - * LOCK will not be reset to default value, as this will disable access - * to core BURTC registers. - ******************************************************************************/ -void BURTC_Reset(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - bool buResetState; - - /* Read reset state, set reset, and restore state. */ - buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); - BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); - BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); -#elif defined(_SILICON_LABS_32B_SERIES_2) - if (BURTC->EN != 0U) { - BURTC_SyncWait(); - } - BURTC->EN_SET = BURTC_EN_EN; - BURTC_Stop(); - BURTC->CNT = 0x0; - BURTC->PRECNT = 0x0; - BURTC->COMP = 0x0; - BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; - BURTC->IEN = _BURTC_IEN_RESETVALUE; - BURTC->IF_CLR = _BURTC_IF_MASK; - /* Wait for all values to synchronize. BusFaults can happen if we don't - * do this before the enable bit is cleared. */ - BURTC_SyncWait(); - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_SYNCBUSY_EN_MASK) - while (BURTC->SYNCBUSY != 0U) { - // Wait for the EN=0 to synchronize - } -#elif defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - BURTC->CFG = _BURTC_CFG_RESETVALUE; -#endif -} - -#if defined(_BURTC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Get the clock frequency of the BURTC. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t BURTC_ClockFreqGet(void) -{ - uint32_t clkSel; - uint32_t clkDiv; - uint32_t frequency; - - clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; - clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; - - switch (clkSel) { - /** Ultra-low frequency (1 kHz) clock. */ - case BURTC_CTRL_CLKSEL_ULFRCO: - if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { - frequency = 2000; /* 2 kHz when clock divisor is 1. */ - } else { - frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different - from 1. */ - } - break; - - /** Low-frequency RC oscillator. */ - case BURTC_CTRL_CLKSEL_LFRCO: - frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ - break; - - /** Low-frequency crystal oscillator. */ - case BURTC_CTRL_CLKSEL_LFXO: - frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ - break; - - default: - /* No clock selected for BURTC. */ - frequency = 0; - } - return frequency; -} -#endif - -/** @} (end addtogroup burtc) */ - -#endif /* BURTC_PRESENT */ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_burtc.h" +#if defined(BURTC_PRESENT) + +/***************************************************************************//** + * @addtogroup burtc BURTC - Backup RTC + * @brief Backup Real Time Counter (BURTC) Peripheral API + * @details + * This module contains functions to control the BURTC peripheral of Silicon + * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all + * energy modes. The Backup RTC is also available when the system is in backup + * mode. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/***************************************************************************//** + * @brief Convert dividend to a prescaler logarithmic value. Only works for even + * numbers equal to 2^n. + * @param[in] div Unscaled dividend, + * @return Base 2 logarithm of input, as used by fixed prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t divToLog2(uint32_t div) +{ + uint32_t log2; + + /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ + EFM_ASSERT((div > 0UL) && (div <= 32768UL)); + + /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ + log2 = (31UL - __CLZ(div)); + + return log2; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(uint32_t mask) +{ +#if defined(_BURTC_FREEZE_MASK) + /* Avoid deadlock if modifying the same register twice when freeze mode is + activated or when a clock is not selected for the BURTC. If a clock is + not selected, then the sync is done once the clock source is set. */ + if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) + || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) + || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { + return; + } +#endif + + /* Wait for any pending previous write operation to complete */ + /* in low frequency domain. This is only required for the Gecko Family. */ + while ((BURTC->SYNCBUSY & mask) != 0U) { + } +} +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief Initialize BURTC. + * + * @details + * Configures the BURTC peripheral. + * + * @note + * Before initialization, BURTC module must first be enabled by clearing the + * reset bit in the RMU, i.e., + * @verbatim + * RMU_ResetControl(rmuResetBU, rmuResetModeClear); + * @endverbatim + * Compare channel 0 must be configured outside this function, before + * initialization if enable is set to true. The counter will always be reset. + * + * @param[in] burtcInit + * A pointer to the BURTC initialization structure. + ******************************************************************************/ +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t ctrl; + uint32_t presc; + + /* Check initializer structure integrity. */ + EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); + /* Clock divider must be between 1 and 128, really on the form 2^n. */ + EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); + + /* Ignored compare bits during low power operation must be less than 7. */ + /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ + EFM_ASSERT(burtcInit->lowPowerComp <= 6); + /* You cannot enable the BURTC if mode is set to disabled. */ + EFM_ASSERT((burtcInit->enable == false) + || ((burtcInit->enable == true) + && (burtcInit->mode != burtcModeDisable))); + /* Low power mode is only available with LFRCO or LFXO as clock source. */ + EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) + || ((burtcInit->clkSel == burtcClkSelULFRCO) + && (burtcInit->lowPowerMode == burtcLPDisable))); + + /* Calculate a prescaler value from the clock divider input. */ + /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of + value 1 will select a 2 kHz ULFRCO clock, while any other value will + select a 1 kHz ULFRCO clock source. */ + presc = divToLog2(burtcInit->clkDiv); + + /* Make sure all registers are updated simultaneously. */ + if (burtcInit->enable) { + BURTC_FreezeEnable(true); + } + + /* Modification of LPMODE register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_LPMODE); + + /* Configure low power mode. */ + BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); + + /* New configuration. */ + ctrl = (BURTC_CTRL_RSTEN + | (burtcInit->mode) + | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) + | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) + | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) + | (presc << _BURTC_CTRL_PRESC_SHIFT) + | (burtcInit->clkSel) + | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); + + /* Clear interrupts. */ + BURTC_IntClear(0xFFFFFFFF); + + /* Set the new configuration. */ + BURTC->CTRL = ctrl; + + /* Enable BURTC and counter. */ + if (burtcInit->enable) { + /* To enable BURTC counter, disable reset. */ + BURTC_Enable(true); + + /* Clear freeze. */ + BURTC_FreezeEnable(false); + } +#elif defined(_SILICON_LABS_32B_SERIES_2) + uint32_t presc; + + presc = divToLog2(burtcInit->clkDiv); + + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + + BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) + | ((burtcInit->compare0Top ? 1UL : 0UL) << _BURTC_CFG_COMPTOP_SHIFT) + | ((burtcInit->debugRun ? 1UL : 0UL) << _BURTC_CFG_DEBUGRUN_SHIFT); + BURTC->EM4WUEN = ((burtcInit->em4comp ? 1UL : 0UL) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) + | ((burtcInit->em4overflow ? 1UL : 0UL) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); + BURTC->EN_SET = BURTC_EN_EN; + if (burtcInit->start) { + BURTC_Start(); + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral. + * + * @param[in] enable + * true to enable, false to disable. + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#endif + + if ((BURTC->EN == 0U) && !enable) { + /* Trying to disable BURTC when it's already disabled */ + return; + } + + if (BURTC->EN != 0U) { + /* Modifying the enable bit while synchronization is active will BusFault */ + BURTC_SyncWait(); + } + + if (enable) { + BURTC->EN_SET = BURTC_EN_EN; + } else { + BURTC_Stop(); + BURTC_SyncWait(); /* Wait for the stop to synchronize */ + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } +} +#elif defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral reset and start counter + * @param[in] enable + * If true; asserts reset to BURTC, halts counter, if false; deassert reset + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ + /* Note! If mode is disabled, BURTC counter will not start */ + EFM_ASSERT(((enable == true) + && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) + != BURTC_CTRL_MODE_DISABLE)) + || (enable == false)); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); +} +#endif + +/***************************************************************************//** + * @brief Set BURTC compare channel. + * + * @param[in] comp Compare the channel index, must be 0 for current devices. + * + * @param[in] value New compare value. + ******************************************************************************/ +void BURTC_CompareSet(unsigned int comp, uint32_t value) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); + +#if defined(_BURTC_COMP0_MASK) + /* Modification of COMP0 register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_COMP0); + + /* Configure compare channel 0/. */ + BURTC->COMP0 = value; +#else + /* Wait for last potential write to complete. */ + regSync(BURTC_SYNCBUSY_COMP); + + /* Configure compare channel 0 */ + BURTC->COMP = value; + regSync(BURTC_SYNCBUSY_COMP); +#endif +} + +/***************************************************************************//** + * @brief Get the BURTC compare value. + * + * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. + * + * @return The currently configured value for this compare channel. + ******************************************************************************/ +uint32_t BURTC_CompareGet(unsigned int comp) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); +#if defined(_BURTC_COMP0_MASK) + return BURTC->COMP0; +#else + return BURTC->COMP; +#endif +} + +/***************************************************************************//** + * @brief Reset counter + ******************************************************************************/ +void BURTC_CounterReset(void) +{ +#if defined(_BURTC_CTRL_MASK) + /* Set and clear reset bit */ + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); +#else + BURTC_Stop(); + BURTC->CNT = 0U; + BURTC_Start(); +#endif +} + +/***************************************************************************//** + * @brief + * Restore BURTC to reset state. + * @note + * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. + * LOCK will not be reset to default value, as this will disable access + * to core BURTC registers. + ******************************************************************************/ +void BURTC_Reset(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + bool buResetState; + + /* Read reset state, set reset, and restore state. */ + buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); +#elif defined(_SILICON_LABS_32B_SERIES_2) + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_SET = BURTC_EN_EN; + BURTC_Stop(); + BURTC->CNT = 0x0; + BURTC->PRECNT = 0x0; + BURTC->COMP = 0x0; + BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; + BURTC->IEN = _BURTC_IEN_RESETVALUE; + BURTC->IF_CLR = _BURTC_IF_MASK; + /* Wait for all values to synchronize. BusFaults can happen if we don't + * do this before the enable bit is cleared. */ + BURTC_SyncWait(); + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + while (BURTC->SYNCBUSY != 0U) { + // Wait for the EN=0 to synchronize + } +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + BURTC->CFG = _BURTC_CFG_RESETVALUE; +#endif +} + +#if defined(_BURTC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Get the clock frequency of the BURTC. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t BURTC_ClockFreqGet(void) +{ + uint32_t clkSel; + uint32_t clkDiv; + uint32_t frequency; + + clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; + clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; + + switch (clkSel) { + /** Ultra-low frequency (1 kHz) clock. */ + case BURTC_CTRL_CLKSEL_ULFRCO: + if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { + frequency = 2000; /* 2 kHz when clock divisor is 1. */ + } else { + frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different + from 1. */ + } + break; + + /** Low-frequency RC oscillator. */ + case BURTC_CTRL_CLKSEL_LFRCO: + frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + /** Low-frequency crystal oscillator. */ + case BURTC_CTRL_CLKSEL_LFXO: + frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + default: + /* No clock selected for BURTC. */ + frequency = 0; + } + return frequency; +} +#endif + +/** @} (end addtogroup burtc) */ + +#endif /* BURTC_PRESENT */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c index 1f37e34..5d91602 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c @@ -1,11811 +1,11811 @@ -/***************************************************************************//** - * @file - * @brief Clock management unit (CMU) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_cmu.h" -#if defined(CMU_PRESENT) - -#include -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "sl_common.h" -#include "em_emu.h" -#include "em_gpio.h" -#include "em_system.h" -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -#include "em_msc.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -/***************************************************************************//** - * @addtogroup cmu CMU - Clock Management Unit - * @brief Clock management unit (CMU) Peripheral API - * @details - * This module contains functions for the CMU peripheral of Silicon Labs 32-bit - * MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock - * multiplexers, pre-scalers, calibration modules and wait-states. - * @{ - ******************************************************************************/ -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -// Maximum allowed core frequency vs. wait-states on flash accesses. -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 40000000UL - -// Maximum allowed core frequency vs. wait-states on sram accesses. -#define CMU_MAX_SRAM_FREQ_0WS 50000000UL -#define CMU_MAX_SRAM_FREQ_1WS 80000000UL - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 40000000UL -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -// Maximum allowed core frequency vs. wait-states and vscale on flash accesses. -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 20000000UL -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define CMU_MAX_FREQ_0WS_1V1 25000000UL -#define CMU_MAX_FREQ_1WS_1V1 50000000UL -#define CMU_MAX_FREQ_2WS_1V1 75000000UL -#else - #warning "MCU flash wait states not supported" -#endif - -// Maximum allowed PCLK frequency. -#define CMU_MAX_PCLK_FREQ 50000000UL - -// Maximum allowed RHCLK frequency. -#define CMU_MAX_RHCLK_FREQ 40000000UL - -#if defined(EMU_VSCALE_EM01_PRESENT) -// This macro is intended to be used as input to CMU_UpdateWaitStates() -#define VSCALE_DEFAULT (2 - (int)EMU_VScaleGet()) -#else -#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE -#endif - -#if defined(PLFRCO_PRESENT) -// Typical frequency for HFXO as recommanded in the datasheets. -// see AN0016: Oscillator Design Considerations -// -// Recommended for most wireless applications -// to meet transceiver electrical specifications -#define XTAL_38M4 38400000UL -// Recommended for implementing Z-Wave devices -#define XTAL_39M0 39000000UL -// High Precision mode calibration Counts for 38.4MHz -#define LFRCO_NOMCAL_XTAL_38M4 _LFRCO_NOMCAL_RESETVALUE -#define LFRCO_NOMCALINV_XTAL_38M4 _LFRCO_NOMCALINV_RESETVALUE -// High Precision mode calibration Counts for 39.0MHz. -#define LFRCO_NOMCAL_XTAL_39M0 0x0005CFBBUL -#define LFRCO_NOMCALINV_XTAL_39M0 0x0000581AUL -#endif - -#define PLL0_USB_OUTPUT_FREQ 48000000UL - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -// Table of HFRCOCAL values and their associated min/max frequencies and -// optional band enumerator. -static const struct hfrcoCalTableElement{ - uint32_t minFreq; - uint32_t maxFreq; - uint32_t value; - CMU_HFRCODPLLFreq_TypeDef band; -} hfrcoCalTable[] = -{ - // minFreq maxFreq HFRCOCAL value band - { 900000UL, 1080000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, - { 1080000UL, 1300000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1300000UL, 1530000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1530000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1800000UL, 2150000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, - { 2150000UL, 2600000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 2600000UL, 3050000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 3050000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 3600000UL, 4300000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, - { 4300000UL, 5200000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 5200000UL, 6100000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 6100000UL, 7800000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, - { 7800000UL, 9800000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 9800000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, - { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, - { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, - { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, - { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, - { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, - { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, - { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, - { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, - { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz }, -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - { 80000000UL, 100000000UL, 0xCCF19F00UL, cmuHFRCODPLLFreq_100M0Hz } -#endif -}; - -static uint16_t lfxo_precision = 0xFFFF; -static uint16_t hfxo_precision = 0xFFFF; - -#define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ - / sizeof(struct hfrcoCalTableElement)) - -// CTUNE delta needed for some series 2 chips. This delta is added to the tuning capacitance on XO. -// The inter-chip buffered crystal sharing feature added from the EFR32xG23 creates an imbalance -// between XI and XO capacitance load internally on the chip. The delta allows to compensate for -// the difference. -#if defined(_SILICON_LABS_32B_SERIES_2) -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -static int8_t ctuneDelta = 40; // Recommendation from analog team to counter the internal chip imbalance. -#else -static int8_t ctuneDelta = 0; -#endif -#endif - -/******************************************************************************* - ************************** LOCAL PROTOTYPES ******************************* - ******************************************************************************/ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -#if defined(PDM_PRESENT) -static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(EUART_PRESENT) -static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(EUSART_PRESENT) -static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#endif -#if defined(LCD_PRESENT) -static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(VDAC_PRESENT) -static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if (VDAC_COUNT > 1) -static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#endif -#if defined(PCNT_PRESENT) -static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(LESENSE_PRESENT) -static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -static void rhclkPrescMax(void); -static void rhclkPrescOptimize(void); -#endif -#endif - -#if defined(HFRCOEM23_PRESENT) -static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); -#endif -static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale); -static void flashWaitStateControl(uint32_t coreFreq, int vscale); -static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); -#if defined(IADC_PRESENT) -static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void pclkDivMax(void); -static void pclkDivOptimize(void); -#if defined(RTCC_PRESENT) -static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#elif defined(SYSRTC_PRESENT) -static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void waitStateMax(void); -static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if WDOG_COUNT > 1 -static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if defined(USB_PRESENT) -static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -/** @endcond */ - -// The following code is common for all SERIES_2 configurations. - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Calibrate an oscillator. - * - * @details - * Run a calibration of a selectable reference clock againt HCLK. Please - * refer to the reference manual, CMU chapter, for further details. - * - * @note - * This function will not return until calibration measurement is completed. - * - * @param[in] cycles - * The number of HCLK cycles to run calibration. Increasing this number - * increases precision, but the calibration will take more time. - * - * @param[in] ref - * The reference clock used to compare against HCLK. - * - * @return - * The number of ticks the selected reference clock ticked while running - * cycles ticks of the HCLK clock. - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) -{ - // Check for cycle count overflow -#if defined(_CMU_CALCTRL_CALTOP_MASK) - EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK - >> _CMU_CALCTRL_CALTOP_SHIFT)); -#elif defined(_CMU_CALTOP_CALTOP_MASK) - EFM_ASSERT(cycles <= (_CMU_CALTOP_CALTOP_MASK - >> _CMU_CALTOP_CALTOP_SHIFT)); -#endif - - CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); - CMU_CalibrateStart(); - return CMU_CalibrateCountGet(); -} - -/***************************************************************************//** - * @brief - * Configure clock calibration. - * - * @details - * Configure a calibration for a selectable clock source against another - * selectable reference clock. - * Refer to the reference manual, CMU chapter, for further details. - * - * @note - * After configuration, a call to @ref CMU_CalibrateStart() is required, and - * the resulting calibration value can be read with the - * @ref CMU_CalibrateCountGet() function call. - * - * @param[in] downCycles - * The number of downSel clock cycles to run calibration. Increasing this - * number increases precision, but the calibration will take more time. - * - * @param[in] downSel - * The clock which will be counted down downCycles cycles. - * - * @param[in] upSel - * The reference clock, the number of cycles generated by this clock will - * be counted and added up, the result can be given with the - * @ref CMU_CalibrateCountGet() function call. - ******************************************************************************/ -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, - CMU_Select_TypeDef upSel) -{ - // Keep untouched configuration settings - uint32_t calCtrl = CMU->CALCTRL - & ~(_CMU_CALCTRL_UPSEL_MASK - | _CMU_CALCTRL_DOWNSEL_MASK -#if defined(_CMU_CALCTRL_CALTOP_MASK) - | _CMU_CALCTRL_CALTOP_MASK -#endif - ); - - // Check for cycle count overflow -#if defined(_CMU_CALCTRL_CALTOP_MASK) - EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK - >> _CMU_CALCTRL_CALTOP_SHIFT)); - calCtrl |= downCycles; -#elif defined(_CMU_CALTOP_CALTOP_MASK) - EFM_ASSERT(downCycles <= (_CMU_CALTOP_CALTOP_MASK >> _CMU_CALTOP_CALTOP_SHIFT)); - CMU->CALTOP = downCycles << _CMU_CALTOP_CALTOP_SHIFT; -#endif - - // Set down counting clock source selector - switch (downSel) { - case cmuSelect_HCLK: - calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; - break; - - case cmuSelect_PRS: - calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; - break; - - case cmuSelect_HFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; - break; - - case cmuSelect_LFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; - break; - - case cmuSelect_HFRCODPLL: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; - break; - - case cmuSelect_ULFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - break; - - default: - EFM_ASSERT(false); - break; - } - - // Set up counting clock source selector - switch (upSel) { - case cmuSelect_PRS: - calCtrl |= CMU_CALCTRL_UPSEL_PRS; - break; - - case cmuSelect_HFXO: - calCtrl |= CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuSelect_LFXO: - calCtrl |= CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuSelect_HFRCODPLL: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; - break; - - case cmuSelect_ULFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - break; - - default: - EFM_ASSERT(false); - break; - } - - CMU->CALCTRL = calCtrl; -} - -/***************************************************************************//** - * @brief - * Get calibration count value. - * - * @note - * If continuous calibration mode is active, calibration busy will almost - * always be off, and reading the value will be just needed, where the normal - * case would be that this function call has been triggered by the CALRDY - * interrupt flag. - * - * @return - * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) - * in the period of DOWNSEL oscillator clock cycles configured by a previous - * write operation to CMU->CALCNT. - ******************************************************************************/ -uint32_t CMU_CalibrateCountGet(void) -{ - // Wait until calibration completes, UNLESS continuous calibration mode is on - if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { - // Wait until calibration completes - while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { - } - } - return CMU->CALCNT; -} - -/***************************************************************************//** - * @brief - * Direct a clock to a GPIO pin. - * - * @param[in] clkNo - * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2. - * - * @param[in] sel - * Select clock source. - * - * @param[in] clkDiv - * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is - * selected as clock source. - * - * @param[in] port - * GPIO port. - * - * @param[in] pin - * GPIO pin. - * - * @note - * Refer to the reference manual and the datasheet for details on which - * GPIO port/pins that are available. - ******************************************************************************/ -void CMU_ClkOutPinConfig(uint32_t clkNo, - CMU_Select_TypeDef sel, - CMU_ClkDiv_TypeDef clkDiv, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - uint32_t tmp = 0U, mask; - - EFM_ASSERT(pin <= 15U); - - switch (clkNo) { - case 0: - case 1: - EFM_ASSERT((port == 2U) || (port == 3U)); - break; - case 2: - EFM_ASSERT((port == 0U) || (port == 1U)); - break; - default: - EFM_ASSERT(false); - break; - } - - switch (sel) { - case cmuSelect_Disabled: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; - break; - - case cmuSelect_FSRCO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; - break; - - case cmuSelect_HFXO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; - break; - - case cmuSelect_HFRCODPLL: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; - break; -#endif - - case cmuSelect_EXPCLK: - EFM_ASSERT((clkDiv > 0U) && (clkDiv <= 32U)); - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; - break; - - case cmuSelect_LFXO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; - break; - - case cmuSelect_HCLK: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; - break; - - default: - EFM_ASSERT(false); - break; - } - - mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK - << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); - tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; - - if (sel == cmuSelect_EXPCLK) { - tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; - mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; - } - - CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; - - if (sel == cmuSelect_Disabled) { - GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; - GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); - } else { - GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; - if (clkNo == 0U) { - GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); - } else if (clkNo == 1) { - GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); - } else { - GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); - } - GPIO_PinModeSet(port, pin, gpioModePushPull, 0); - } -} - -/***************************************************************************//** - * @brief - * Get clock divisor. - * - * @param[in] clock - * Clock point to get divisor for. Notice that not all clock points - * have a divisors. Please refer to CMU overview in reference manual. - * - * @return - * The current clock point divisor. 1 is returned - * if @p clock specifies a clock point without divisor. - ******************************************************************************/ -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - - switch (clock) { - case cmuClock_HCLK: - case cmuClock_CORE: - ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (ret == 2U ) { // Unused value, illegal prescaler - EFM_ASSERT(false); - } -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - if (!((ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV1) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV2) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV4) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV8) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV16))) { - // Illegal prescaler - EFM_ASSERT(false); - } -#endif - break; - -#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) - case cmuClock_TRACECLK: - ret = (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_PRESC_MASK) - >> _CMU_TRACECLKCTRL_PRESC_SHIFT; - if (!((ret == _CMU_TRACECLKCTRL_PRESC_DIV1) - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV2) -#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV3) -#endif - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV4))) { - // Illegal prescaler - EFM_ASSERT(false); - } - break; -#endif - - case cmuClock_EXPCLK: - ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) - >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; - break; - - case cmuClock_PCLK: - ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; - break; - - default: - break; - } - return 1U + ret; -} - -/***************************************************************************//** - * @brief - * Set clock divisor. - * - * @param[in] clock - * Clock point to set divisor for. Notice that not all clock points - * have a divisor, please refer to CMU overview in the reference - * manual. - * - * @param[in] div - * The clock divisor to use. - ******************************************************************************/ -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) -{ -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - bool restoreTrace; -#endif - - switch (clock) { - case cmuClock_HCLK: - case cmuClock_CORE: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U) - || (div == 8U) || (div == 16U)); -#endif - - // Set max wait-states and PCLK divisor while changing core clock - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Set new divisor - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) - | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); - - // Update CMSIS core clock variable and set optimum wait-states - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - break; - -#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) - case cmuClock_TRACECLK: -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; - if (restoreTrace) { - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } -#endif -#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 3U) || (div == 4U)); -#else - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); -#endif - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_PRESC_MASK) - | ((div - 1U) << _CMU_TRACECLKCTRL_PRESC_SHIFT); -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - if (restoreTrace) { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - break; -#endif - - case cmuClock_EXPCLK: - EFM_ASSERT((div >= 1U) && (div <= 32U)); - CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) - | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); - break; - - case cmuClock_PCLK: - EFM_ASSERT((div == 1U) || (div == 2U)); - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) - | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); - break; - - default: - EFM_ASSERT(false); - break; - } -} - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @details - * Module clocks sre disabled after reset. If a module clock is disabled, the - * registers of that module are not accessible and accessing such registers - * will hardfault the Cortex core. - * - * @param[in] clock - * The clock to enable/disable. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - volatile uint32_t *reg = NULL; - uint32_t bit; - - /* Identify the enable register. */ - if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_NO_EN_REG) { - EFM_ASSERT(false); /* No enable for this clock. */ - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN0_EN_REG) { - reg = &CMU->CLKEN0; - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN1_EN_REG) { - reg = &CMU->CLKEN1; -#if defined(_CMU_CLKEN2_MASK) - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN2_EN_REG) { - reg = &CMU->CLKEN2; -#endif - } else { -#if defined(CRYPTOACC_PRESENT) - reg = &CMU->CRYPTOACCCLKCTRL; -#else - // No register to enable clock. Possible hard fault exception. - EFM_ASSERT(false); -#endif - } - - /* Get the bit position used to enable/disable. */ - bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; - - /* Set/clear bit as requested. */ - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/***************************************************************************//** - * @brief - * Get clock frequency for a clock point. - * - * @param[in] clock - * Clock point to fetch frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - - switch (clock) { - case cmuClock_SYSCLK: - ret = SystemSYSCLKGet(); - break; - - case cmuClock_CORE: - case cmuClock_HCLK: - case cmuClock_LDMA: - case cmuClock_GPCRC: - ret = SystemHCLKGet(); - break; - - case cmuClock_EXPCLK: - ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); - break; - - case cmuClock_I2C1: - case cmuClock_PRS: - case cmuClock_PCLK: - case cmuClock_GPIO: - case cmuClock_USART0: - case cmuClock_USART1: - case cmuClock_USART2: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); - break; - - case cmuClock_I2C0: - case cmuClock_LSPCLK: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; - break; - -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(&ret, NULL); - break; -#endif - - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(&ret, NULL); - break; - - case cmuClock_SYSTICK: - sysTickClkGet(&ret, NULL); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: - em23GrpaClkGet(&ret, NULL); - break; - - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: - em4GrpaClkGet(&ret, NULL); - break; - - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(&ret, NULL); - break; - - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(&ret, NULL); - break; - - case cmuClock_DPLLREFCLK: - dpllRefClkGet(&ret, NULL); - break; - - case cmuClock_TRACECLK: - traceClkGet(&ret, NULL); - break; - - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(&ret, NULL); - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/***************************************************************************//** - * @brief - * Get clock frequency for a clock point. - * - * @param[in] clock - * Clock point to fetch frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - uint32_t freq = 0U; - - switch (clock) { - case cmuClock_SYSCLK: - ret = SystemSYSCLKGet(); - break; - - case cmuClock_HCLK: - case cmuClock_CORE: - case cmuClock_ICACHE: - case cmuClock_MSC: - case cmuClock_LDMA: - case cmuClock_SMU: -#if defined(RADIOAES_PRESENT) - case cmuClock_RADIOAES: -#endif -#if defined(CRYPTOACC_PRESENT) - case cmuClock_CRYPTOACC: - case cmuClock_CRYPTOAES: - case cmuClock_CRYPTOPK: -#endif -#if defined(MVP_PRESENT) - case cmuClock_MVP: -#endif - ret = SystemHCLKGet(); - break; - - case cmuClock_EXPCLK: - ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); - break; - - case cmuClock_PCLK: -#if defined(USART_PRESENT) - case cmuClock_USART0: -#if USART_COUNT > 1 - case cmuClock_USART1: -#endif -#endif - case cmuClock_I2C1: - case cmuClock_PRS: - case cmuClock_GPIO: - case cmuClock_GPCRC: - case cmuClock_LDMAXBAR: - case cmuClock_SYSCFG: - case cmuClock_DCDC: - case cmuClock_BURAM: - case cmuClock_DPLL0: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); - break; - - case cmuClock_LSPCLK: - case cmuClock_I2C0: - case cmuClock_AMUXCP0: -#if defined(ACMP_PRESENT) - case cmuClock_ACMP0: -#if ACMP_COUNT > 1 - case cmuClock_ACMP1: -#endif -#endif - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; - break; - - case cmuClock_TRACECLK: - traceClkGet(&freq, NULL); - ret = freq / CMU_ClockDivGet(cmuClock_TRACECLK); - break; - - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(&ret, NULL); - break; -#if defined(PDM_PRESENT) - case cmuClock_PDM: - case cmuClock_EM01GRPBCLK: - em01GrpbClkGet(&ret, NULL); - break; -#endif -#if defined(EUART_PRESENT) - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - euart0ClkGet(&ret, NULL); - break; -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - eusart0ClkGet(&ret, NULL); - break; -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - em01GrpcClkGet(&ret, NULL); - break; -#endif -#endif - -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(&ret, NULL); - break; -#endif - - case cmuClock_SYSTICK: - sysTickClkGet(&ret, NULL); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - em23GrpaClkGet(&ret, NULL); - break; - - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(&ret, NULL); - break; -#if WDOG_COUNT > 1 - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(&ret, NULL); - break; -#endif -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(&ret, NULL); - break; -#endif -#if defined(SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - sysrtcClkGet(&ret, NULL); - break; -#endif -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - lcdClkGet(&ret, NULL); - break; -#endif -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - vdac0ClkGet(&ret, NULL); - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - vdac1ClkGet(&ret, NULL); - break; -#endif -#endif /* VDAC_PRESENT */ -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - pcnt0ClkGet(&ret, NULL); - break; -#endif -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - lesenseHFClkGet(&ret, NULL); - break; -#endif - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - em4GrpaClkGet(&ret, NULL); - break; - -#if defined(USB_PRESENT) - case cmuClock_USB: - usbClkGet(&ret, NULL); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - return ret; -} -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/***************************************************************************//** - * @brief - * Get currently selected reference clock used for a clock branch. - * - * @param[in] clock - * Clock branch to fetch selected ref. clock for. - * - * @return - * Reference clock used for clocking selected branch, #cmuSelect_Error if - * invalid @p clock provided. - ******************************************************************************/ -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef ret = cmuSelect_Error; - - switch (clock) { -// ----------------------------------------------------------------------------- - case cmuClock_SYSCLK: - switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { - case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: - ret = cmuSelect_HFRCODPLL; - break; - - case CMU_SYSCLKCTRL_CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: - ret = cmuSelect_CLKIN0; - break; - - case CMU_SYSCLKCTRL_CLKSEL_FSRCO: - ret = cmuSelect_FSRCO; - break; - -#if defined(RFFPLL_PRESENT) - case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: - ret = cmuSelect_RFFPLLSYS; - break; -#endif - default: - ret = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - break; - -// ----------------------------------------------------------------------------- -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- - case cmuClock_SYSTICK: - sysTickClkGet(NULL, &ret); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - em23GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - em4GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) - case cmuClock_PDMREF: - case cmuClock_EM01GRPBCLK: - em01GrpbClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_DPLLREFCLK: - dpllRefClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) - case cmuClock_TRACECLK: - traceClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - euart0ClkGet(NULL, &ret); - break; -#elif defined(EUSART_PRESENT) - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - eusart0ClkGet(NULL, &ret); - break; - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - em01GrpcClkGet(NULL, &ret); - break; -#endif - #endif - -// ----------------------------------------------------------------------------- -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - sysrtcClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - lcdClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - vdac0ClkGet(NULL, &ret); - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - vdac1ClkGet(NULL, &ret); - break; -#endif -#endif -// ----------------------------------------------------------------------------- -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - pcnt0ClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - lesenseHFClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(USB_PRESENT) - case cmuClock_USB: - usbClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- - default: - EFM_ASSERT(false); - break; - } - return ret; -} - -/***************************************************************************//** - * @brief Performs pre-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPreClockSelect(void) -{ -#if defined(EMU_VSCALE_EM01_PRESENT) - // VSCALE up before changing clock. - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); -#endif - - // Set max wait-states and PCLK divisor while changing core clock. - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif -} - -/***************************************************************************//** - * @brief Performs post-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPostClockSelect(void) -{ - // Update CMSIS core clock variable and set optimum wait-states. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(EMU_VSCALE_EM01_PRESENT) - // Check if possible to downscale VSCALE setting. - EMU_VScaleEM01ByClock(0, true); -#endif - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif -} - -/***************************************************************************//** - * @brief Sets the HFXO0 FORCEEN bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK and the selected clock source is HFXO. - ******************************************************************************/ -void sli_em_cmu_HFXOSetForceEnable(void) -{ -#if defined(_CMU_CLKEN0_MASK) && defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -} - -/***************************************************************************//** - * @brief This function will set the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENSet(void) -{ -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - - SYSCFG_setSysTicExtClkEnCfgSysTic(); - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} - -/***************************************************************************//** - * @brief This function will clear the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENClear(void) -{ -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - - SYSCFG_clearSysTicExtClkEnCfgSysTic(); - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} - -/***************************************************************************//** - * @brief - * Select reference clock/oscillator used for a clock branch. - * - * @param[in] clock - * Clock branch to select reference clock for. - * - * @param[in] ref - * Reference selected for clocking, please refer to reference manual for - * for details on which reference is available for a specific clock branch. - ******************************************************************************/ -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) -{ - uint32_t tmp = 0U; - bool oscForceEnStatus = false; -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - bool syscfgClkIsOff = false; -#endif -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - bool restoreTrace; -#endif - - switch (clock) { -// ----------------------------------------------------------------------------- - case cmuClock_SYSCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; -#if defined(_CMU_CLKEN0_MASK) -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif -#endif - // Make sure HFXO is enabled. - oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_FSRCO: - tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; - break; - -#if defined(RFFPLL_PRESENT) - case cmuSelect_RFFPLLSYS: - tmp = CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - // VSCALE up before changing clock. - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); -#endif - - // Set max wait-states and PCLK divisor while changing core clock. - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Switch to selected oscillator. - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; - - // Update CMSIS core clock variable and set optimum wait-states. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(EMU_VSCALE_EM01_PRESENT) - // Check if possible to downscale VSCALE setting. - EMU_VScaleEM01ByClock(0, true); -#endif - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - - if (oscForceEnStatus == false) { - switch (ref) { - case cmuSelect_HFXO: - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - break; - - default: - break; - } - } - break; - -// ----------------------------------------------------------------------------- -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - switch (ref) { - case cmuSelect_EM01GRPACLK: - tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; - break; - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL - & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -// ----------------------------------------------------------------------------- - case cmuClock_SYSTICK: - switch (ref) { - case cmuSelect_EM23GRPACLK: - case cmuSelect_LFXO: - case cmuSelect_LFRCO: - case cmuSelect_ULFRCO: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSCFG_setSysTicExtClkEnCfgSysTic(); -#else - syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - SYSCFG_setSysTicExtClkEnCfgSysTic(); - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif - SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); - break; - case cmuSelect_HCLK: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSCFG_clearSysTicExtClkEnCfgSysTic(); -#else - syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - SYSCFG_clearSysTicExtClkEnCfgSysTic(); - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif - SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); - break; - default: - EFM_ASSERT(false); - break; - } - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL - & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -// ----------------------------------------------------------------------------- - case cmuClock_BURTC: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - case cmuClock_EM4GRPACLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL - & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_PDMREF: - case cmuClock_EM01GRPBCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; - break; - - case cmuSelect_FSRCO: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; - break; - - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL - & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_HCLKDIV1024: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; - break; - - case cmuSelect_Disabled: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) - | tmp; - break; - -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_HCLKDIV1024: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; - break; - - case cmuSelect_Disabled: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_DPLLREFCLK: - switch (ref) { - case cmuSelect_HFXO: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; - break; - - case cmuSelect_LFXO: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_Disabled: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL - & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; - break; - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_TRACECLK: -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; - if (restoreTrace) { - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - switch (ref) { -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - case cmuSelect_HCLK: - tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - case cmuSelect_SYSCLK: - tmp = CMU_TRACECLKCTRL_CLKSEL_SYSCLK; - break; - - case cmuSelect_HFRCODPLLRT: - tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) - case cmuSelect_HFRCOEM23: - tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) - | tmp; -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - if (restoreTrace) { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - break; -#endif - -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - switch (ref) { - case cmuSelect_EM01GRPACLK: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; - break; - - case cmuSelect_EM23GRPACLK: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - case cmuSelect_Disabled: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#elif defined(EUSART_PRESENT) - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - switch (ref) { -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) - case cmuSelect_EM01GRPACLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - case cmuSelect_EM01GRPCCLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) - case cmuSelect_EM23GRPACLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) - case cmuSelect_FSRCO: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) - case cmuSelect_HFRCOEM23: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) - case cmuSelect_LFXO: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; - break; -#endif - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) - case cmuSelect_Disabled: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) - | tmp; - break; - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif - case cmuSelect_HFRCOEM23: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; - break; - - case cmuSelect_FSRCO: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_HFXO: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -#endif - -// ----------------------------------------------------------------------------- -#if defined (RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined (SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_LCDCLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_LCDCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_LCDCLKCTRL_CLKSEL_ULFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; - break; - case cmuSelect_EM01GRPACLK: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; - break; - case cmuSelect_EM23GRPACLK: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; - break; - case cmuSelect_EM01GRPACLK: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; - break; - case cmuSelect_EM23GRPACLK: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -#endif /* VDAC_PRESENT */ -// ----------------------------------------------------------------------------- -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - switch (ref) { - case cmuSelect_EM23GRPACLK: - tmp = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - case cmuSelect_PCNTEXTCLK: - tmp = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(USB_PRESENT) - case cmuClock_USB: - switch (ref) { - case cmuSelect_USBPLL0: - tmp = CMU_USB0CLKCTRL_CLKSEL_USBPLL0; - break; - case cmuSelect_LFXO: - tmp = CMU_USB0CLKCTRL_CLKSEL_LFXO; - break; - case cmuSelect_LFRCO: - tmp = CMU_USB0CLKCTRL_CLKSEL_LFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified low frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_LFXO: - precision = lfxo_precision; - break; - -#if defined(PLFRCO_PRESENT) -#if defined(LFRCO_CFG_HIGHPRECEN) - case cmuSelect_LFRCO: - case cmuSelect_PLFRCO: - - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; - - if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { - precision = 500; - } else { - precision = 0xFFFF; - } - break; -#endif -#endif - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified high frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_HFXO: - precision = hfxo_precision; - break; - - case cmuSelect_HFRCODPLL: - precision = 0xFFFF; - break; - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Get HFRCODPLL band in use. - * - * @return - * HFRCODPLL band in use. - ******************************************************************************/ -CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) -{ - return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); -} - -/***************************************************************************//** - * @brief - * Set HFRCODPLL band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] freq - * HFRCODPLL frequency band to activate. - ******************************************************************************/ -void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) -{ - uint32_t hfrcoFreqRangeExpected; - uint32_t hfrcoFreqRangeActual; - uint32_t hfrcoCalCurrent; - uint32_t freqCal, sysFreq; -#if defined(EMU_VSCALE_EM01_PRESENT) - uint32_t prevFreq; -#endif - - // Get calibration data from DEVINFO - freqCal = HFRCODPLLDevinfoGet(freq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - -#if defined(CMU_CLKEN0_DPLL0) - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; -#endif - - // Make sure DPLL is disabled before configuring - if (DPLL0->EN == DPLL_EN_EN) { - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while (DPLL0->EN & DPLL_EN_DISABLING) { - } -#else - while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { - } -#endif - } - - // Set max wait-states and PCLK divisor while changing core clock - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - } - - // Set divider for 1, 2 and 4MHz bands - freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; - switch (freq) { - case cmuHFRCODPLLFreq_1M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV4; - break; - - case cmuHFRCODPLLFreq_2M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV2; - break; - - default: - break; - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - prevFreq = SystemHFRCODPLLClockGet(); - - if ((uint32_t)freq > prevFreq) { - /* When increasing frequency voltage scale must be done before the change. */ - EMU_VScaleEM01ByClock((uint32_t)freq, true); - } -#endif - - // updates to the CAL register are deferred if FREQBSY is high, so wait - // until HFRCO is not busy to keep going - while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { - } - - /* - * Some devices have clamped frequency ranges, so instead of the usual [0:16] - * interval, the upper limit is 12. Hardware takes care of clamping the value, - * but a situation might occur where tuning and frequency range are not - * in sync. So try to detect if the value has been clamped, and if it happened - * revert back to the previous value. - */ - hfrcoCalCurrent = HFRCO0->CAL; - HFRCO0->CAL = freqCal; - - // values are not shifted, not necessary for comparison - hfrcoFreqRangeExpected = (freqCal & _HFRCO_CAL_FREQRANGE_MASK); - hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); - - EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); - if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { - // Update CMSIS HFRCODPLL frequency. - SystemHFRCODPLLClockSet(freq); - } else { - // revert back to previous value - HFRCO0->CAL = hfrcoCalCurrent; -#if defined(EMU_VSCALE_EM01_PRESENT) - freq = (CMU_HFRCODPLLFreq_TypeDef)prevFreq; -#endif - } - - // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access - // wait-state configuration and PCLK divisor for this frequency. - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= (uint32_t)freq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - if ((uint32_t)freq <= prevFreq) { - /* When decreasing frequency voltage scale must be done after the change. */ - EMU_VScaleEM01ByClock(0, true); - } -#endif -} - -/**************************************************************************//** - * @brief - * Lock the DPLL to a given frequency. - * The frequency is given by: Fout = Fref * (N+1) / (M+1). - * - * @note - * This function does not check if the given N & M values will actually - * produce the desired target frequency. @n - * N & M limitations: @n - * 300 < N <= 4095 @n - * 0 <= M <= 4095 @n - * Any peripheral running off HFRCODPLL should be switched to a lower - * frequency clock (if possible) prior to calling this function to avoid - * over-clocking. - * - * @param[in] init - * DPLL setup parameter struct. - * - * @return - * Returns false on invalid target frequency or DPLL locking error. - *****************************************************************************/ -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) -{ - int index = 0; - unsigned int i; - bool hclkDivIncreased = false; - uint32_t hfrcoCalVal, lockStatus = 0, hclkDiv = 0, sysFreq; - uint32_t hfrcoFreqRangeExpected; - uint32_t hfrcoFreqRangeActual; - uint32_t hfrcoCalCurrent; - bool hfrcoClamped = false; - bool restoreDpll; - -#if defined(CMU_CLKEN0_DPLL0) - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; -#endif - - restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; - - // Make sure DPLL is disabled before configuring - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while (DPLL0->EN & DPLL_EN_DISABLING) { - } -#else - while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { - } -#endif - EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); - EFM_ASSERT(init->frequency - <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); - - EFM_ASSERT(init->n > 300U); - EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); - EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); - -#if defined(EMU_VSCALE_EM01_PRESENT) - if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) - && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EFM_ASSERT(false); - return false; - } -#endif - - // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. - for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { - if ((init->frequency >= hfrcoCalTable[i].minFreq) - && (init->frequency <= hfrcoCalTable[i].maxFreq)) { - index = (int)i; // Correct band found - break; - } - } - if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { - EFM_ASSERT(false); - return false; // Target frequency out of spec. - } - hfrcoCalVal = hfrcoCalTable[index].value; - - // Check if a calibrated HFRCOCAL.TUNING value is present in device DI page. - if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { - uint32_t tuning; - - tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) - & _HFRCO_CAL_TUNING_MASK) - >> _HFRCO_CAL_TUNING_SHIFT; - hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; - } - - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - // Set max wait-states and PCLK divisor while changing core clock - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Increase HCLK divider value (if possible) while locking DPLL to - // avoid over-clocking. - hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); - hclkDivIncreased = true; - if (hclkDiv == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 2U); - } else if (hclkDiv == 2U) { - CMU_ClockDivSet(cmuClock_HCLK, 4U); - } else { - hclkDivIncreased = false; - } - } - - // updates to the CAL register are deferred if FREQBSY is high, so wait - // until HFRCO is not busy to keep going - while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { - } - - /* - * Some devices have clamped frequency ranges, so instead of the usual [0:16] - * interval, the upper limit is 12. Hardware takes care of clamping the value, - * but a situation might occur where tuning and frequency range are not - * in sync. So try to detect if the value has been clamped, and if it happened - * revert back to the previous value. - */ - hfrcoCalCurrent = HFRCO0->CAL; - HFRCO0->CAL = hfrcoCalVal; - - // values are not shifted, not necessary for comparison - hfrcoFreqRangeExpected = (hfrcoCalVal & _HFRCO_CAL_FREQRANGE_MASK); - hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); - - EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); - if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { - DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) - | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); - - /* For series 2 silicon, macro expansion is used to select clock - * sources since it results in less code size when compared to the legacy - * CMU_ClockSelectSet function. - */ - if (init->refClk == cmuSelect_HFXO) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, HFXO); - } else if (init->refClk == cmuSelect_LFXO) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, LFXO); - } else if (init->refClk == cmuSelect_CLKIN0) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, CLKIN0); - } - - DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) - | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) - | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) - | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); - - // Update CMSIS HFRCODPLL frequency. - SystemHFRCODPLLClockSet(init->frequency); - } else { - hfrcoClamped = true; - HFRCO0->CAL = hfrcoCalCurrent; - } - - /* - * if HFRCO frequency range has been clamped, re-enable DPLL only if it was - * previously enabled - */ - if (!hfrcoClamped || restoreDpll) { - DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; - - // Lock DPLL - DPLL0->EN_SET = DPLL_EN_EN; - while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK - | DPLL_IF_LOCKFAILLOW - | DPLL_IF_LOCKFAILHIGH))) == 0UL) { - } - } - - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - if (hclkDivIncreased) { - // Restore original HCLK divider - CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); - } - - // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= init->frequency); - EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); - EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); - - // Set optimal wait-states and PCLK divisor - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - } - - if (hfrcoClamped) { - return false; - } else if (lockStatus == DPLL_IF_LOCK) { - return true; - } - return false; -} - -#if defined(USBPLL_PRESENT) -/***************************************************************************//** - * @brief - * Initialize the USB PLL control registers. - * - * @note - * The HFXO reference frequency must be updated if crystal value is - * different from default value. - * - * @param[in] pllInit - * USB PLL parameters - ******************************************************************************/ -void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit) -{ - CMU->CLKEN1_SET = CMU_CLKEN1_USB; - - USBPLL0->LOCK = USBPLL_LOCK_LOCKKEY_UNLOCK; - - // Stop the PLL for configuration purposes - USBPLL0->CTRL_SET = USBPLL_CTRL_DISONDEMAND; - USBPLL0->CTRL_CLR = USBPLL_CTRL_FORCEEN; - - while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; - - if (pllInit->hfxoRefFreq == cmuHFXORefFreq_39M0Hz) { - // Set DCO in low frequency mode for 39 MHz crystal. - USBPLL0->DCOCTRL_SET = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; - } else { - USBPLL0->DCOCTRL_CLR = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; - } - - while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; - - USBPLL0->CTRL = (USBPLL0->CTRL & ~(_USBPLL_CTRL_SHUNTREGLPEN_MASK - | _USBPLL_CTRL_DIVR_MASK - | _USBPLL_CTRL_DIVX_MASK - | _USBPLL_CTRL_DIVN_MASK - | _USBPLL_CTRL_DISONDEMAND_MASK - | _USBPLL_CTRL_FORCEEN_MASK)) - | pllInit->hfxoRefFreq - | pllInit->shuntRegEn << _USBPLL_CTRL_SHUNTREGLPEN_SHIFT - | pllInit->disOnDemand << _USBPLL_CTRL_DISONDEMAND_SHIFT - | pllInit->forceEn << _USBPLL_CTRL_FORCEEN_SHIFT; - - while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; - - if (pllInit->forceEn) { - CMU_WaitUSBPLLLock(); - } - - if (pllInit->regLock) { - USBPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -#if defined(RFFPLL_PRESENT) -/***************************************************************************//** - * @brief - * Initialize the RFFPLL control registers. - * - * @param[in] pllInit - * RFF PLL parameters - ******************************************************************************/ -void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit) -{ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_RFFPLLSYS); - EFM_ASSERT(pllInit->dividerY >= 8 && pllInit->dividerY <= 31); - EFM_ASSERT(pllInit->dividerX >= 4 && pllInit->dividerX <= 15); - EFM_ASSERT(pllInit->dividerN >= 32 && pllInit->dividerN <= 127); - - CMU->CLKEN1_SET = CMU_CLKEN1_RFFPLL0; - - RFFPLL0->LOCK = RFFPLL_LOCK_LOCKKEY_UNLOCK; - - RFFPLL0->CTRL = (RFFPLL0->CTRL & ~(_RFFPLL_CTRL_DISONDEMAND_MASK | _RFFPLL_CTRL_FORCEEN_MASK)) - | (pllInit->disOnDemand << _RFFPLL_CTRL_DISONDEMAND_SHIFT) - | (pllInit->forceEn << _RFFPLL_CTRL_FORCEEN_SHIFT); - - RFFPLL0->RFFPLLCTRL1 = (RFFPLL0->RFFPLLCTRL1 & ~(_RFFPLL_RFFPLLCTRL1_DIVY_MASK | _RFFPLL_RFFPLLCTRL1_DIVX_MASK | _RFFPLL_RFFPLLCTRL1_DIVN_MASK)) - | (pllInit->dividerY << _RFFPLL_RFFPLLCTRL1_DIVY_SHIFT) - | (pllInit->dividerX << _RFFPLL_RFFPLLCTRL1_DIVX_SHIFT) - | (pllInit->dividerN << _RFFPLL_RFFPLLCTRL1_DIVN_SHIFT); - - // Update CMSIS RFFPLL frequency. - SystemRFFPLLClockSet(pllInit->frequency); - - if (pllInit->forceEn) { - CMU_WaitRFFPLLLock(); - } - - if (pllInit->regLock) { - RFFPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -/**************************************************************************//** - * @brief - * Initialize all HFXO control registers. - * - * @note - * HFXO configuration should be obtained from a configuration tool, - * app note or crystal datasheet. This function returns early if HFXO is - * already selected as SYSCLK. - * - * @param[in] hfxoInit - * HFXO setup parameters. - *****************************************************************************/ -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) -{ - // Check all initialization structure members which may overflow target - // bitfield. - EFM_ASSERT(hfxoInit->timeoutCbLsb - <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK - >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); - EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock - <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK - >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); - EFM_ASSERT(hfxoInit->timeoutSteady - <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK - >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneXoStartup - <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK - >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneXiStartup - <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK - >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->coreBiasStartup - <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK - >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->imCoreBiasStartup - <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK - >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); - EFM_ASSERT(hfxoInit->coreDegenAna - <= (_HFXO_XTALCTRL_COREDGENANA_MASK - >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneFixAna - <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK - >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); - EFM_ASSERT(hfxoInit->mode - <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); - - // Return early if HFXO is already selected as SYSCLK. - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { - return; - } - -#if defined(CMU_CLKEN0_HFXO0) - // Enable HFXO module clock. - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - // Disable HFXO. - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND -#if defined(_HFXO_CTRL_DISONDEMANDBUFOUT_MASK) - | HFXO_CTRL_DISONDEMANDBUFOUT -#endif - ; - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; - while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { - } -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - -#if defined(_DEVINFO_HFXOCAL_VTRTRIMANA_MASK) && defined(_HFXO_BUFOUTTRIM_MASK) && defined(_HFXO_SWRST_MASK) - { - uint32_t tmp; - - tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, - _DEVINFO_HFXOCAL_VTRTRIMANA_MASK); - tmp >>= _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT; - BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, - _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK, - tmp << _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT); - } -#endif - -#if defined(_DEVINFO_HFXOCAL_SHUNTBIASANA_MASK) && defined(_HFXO_LOWPWRCTRL_MASK) && defined(_HFXO_SWRST_MASK) - { - uint32_t tmp; - - tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, - _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK); - tmp >>= _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT; - BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, - _HFXO_LOWPWRCTRL_SHUNTBIASANA_MASK, - tmp << _HFXO_LOWPWRCTRL_SHUNTBIASANA_SHIFT); - } -#endif - - // Configure HFXO as specified in initialization struct, use - // timeoutSteadyFirstLock as TIMEOUTSTEADY value. - HFXO0->XTALCFG = - (uint32_t)((hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) - | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) - | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) - | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) - | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) - | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); - - HFXO0->XTALCTRL = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) - | (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) - | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) - | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) - | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) - | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - // See [PM-2871] for details. - BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), - 0x00000C00U, - 0x00000002U << 10); -#endif - - HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK - | _HFXO_CFG_ENXIDCBIASANA_MASK - | _HFXO_CFG_MODE_MASK)) - | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) - ? 0 : HFXO_CFG_SQBUFSCHTRGANA) - | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) - | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); - - if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { - // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared. - HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK - | _HFXO_CTRL_FORCEXI2GNDANA_MASK - | _HFXO_CTRL_DISONDEMAND_MASK -#if defined(HFXO_CTRL_EM23ONDEMAND) - | _HFXO_CTRL_EM23ONDEMAND_MASK -#endif - | _HFXO_CTRL_FORCEEN_MASK)) - | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) - | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) -#if defined(HFXO_CTRL_EM23ONDEMAND) - | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) -#endif - | HFXO_CTRL_FORCEEN; - - // Wait for HFXO lock and core bias algorithm to complete. -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY - | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) - != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS - | HFXO_STATUS_FSMLOCK)) { - } -#else - while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY - | HFXO_STATUS_ENS)) - != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS)) { - } -#endif - // Set DISONDEMAND to be able to enter new values for use on subsequent locks. - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD = HFXO_CMD_MANUALOVERRIDE; -#endif -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - } -#endif - // Set new TIMEOUTSTEADY value for use on subsequent locks. - HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) - | (hfxoInit->timeoutSteady - << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); - - // Skip core bias algorithm on subsequent locks. - HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; - - if (hfxoInit->disOnDemand == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; - } - - if (hfxoInit->forceEn == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - } - } else { - // Lock HFXO in EXTERNAL SINE mode. - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - //See [PM-3665] for details. - if (hfxoInit->mode == cmuHfxoOscMode_ExternalSinePkDet) { - HFXO0->XTALCFG = 0; - HFXO0->XTALCTRL = 0; - - const uint32_t PKDETTHSTARTUP_PARAMETER_1 = 2UL; - BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), - 0x0000F000U | 0x00000F00U, - (PKDETTHSTARTUP_PARAMETER_1 << 12) | (PKDETTHSTARTUP_PARAMETER_1 << 8)); - } -#endif - - HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK - | _HFXO_CTRL_FORCEXI2GNDANA_MASK - | _HFXO_CTRL_DISONDEMAND_MASK -#if defined(HFXO_CTRL_EM23ONDEMAND) - | _HFXO_CTRL_EM23ONDEMAND_MASK -#endif - | _HFXO_CTRL_FORCEEN_MASK)) - | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) - | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) -#if defined(HFXO_CTRL_EM23ONDEMAND) - | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) -#endif - | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); - } - - if (hfxoInit->regLock) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } -} - -#if defined(HFXO0_BUFOUT) -/**************************************************************************//** - * @brief - * Initialize HFXO Bufout (Crystal sharing) leader control registers. - * Configure the bufout request input GPIO as a clock request signal - * to add the crystal sharing follower chip as a source of clock request. - * - * @warning - * If EM2 capabilities are needed, a GPIO that fully retains its - * capabilities while in EM2 must be selected. - * - * @param[in] bufoutInit - * Bufout setup parameters. - * - * @param[in] port - * Bufout request GPIO port. - * - * @param[in] pin - * Bufout request GPIO pin. - *****************************************************************************/ -void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - // Configure Bufout request GPIO. - GPIO_PinModeSet(port, pin, gpioModeInput, 0U); - GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT - | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; - - bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; - - BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, - _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK - | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, - bufoutInit->minimalStartupDelay << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT - | bufoutInit->timeoutStartup << _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT); - - if (wasLocked) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -/**************************************************************************//** - * @brief - * Initialize HFXO Bufout (Crystal sharing) follower control registers. - * Configure the clock request signal to a specified GPIO to automatically - * request the high frequency crystal oscillator sine wave clock. - * This function must be used in conjunction with CMU_HFXOInit() configured - * with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode. - * - * @warning - * If EM2 capabilities are needed, a GPIO that fully retains its - * capabilities while in EM2 must be selected. - * - * @note - * This function can be emulated on XG21/XG22 chips by controlling the clock - * request GPIO to ask the crystal sharing leader clock when needed. - * - * @param[in] prsStatusSelectOutput - * Selected HFXO PRS signal output. - * - * @param[in] prsAsyncCh - * PRS producer asynchronous signal channel. - * - * @param[in] port - * Bufout request GPIO port. - * - * @param[in] pin - * Bufout request GPIO pin. - *****************************************************************************/ -void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, - unsigned int prsAsyncCh, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(prsAsyncCh < PRS_ASYNC_CH_NUM); - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - uint32_t mask = 0U, prsSignal = 0U, value = 0U; - - switch (prsStatusSelectOutput) { - case PRS_Status_select_0: - mask = _HFXO_CTRL_PRSSTATUSSEL0_MASK; - value = _HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT; - prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS; - break; - - case PRS_Status_select_1: -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - // Power Manager module requires the HFXO PRS Producer output 1 for its usage. - EFM_ASSERT(false); -#else - mask = _HFXO_CTRL_PRSSTATUSSEL1_MASK; - value = _HFXO_CTRL_PRSSTATUSSEL1_ENS << _HFXO_CTRL_PRSSTATUSSEL1_SHIFT; - prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1; -#endif - break; - - default: - EFM_ASSERT(false); - break; - } - - bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); - - if (wasLocked) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } - - value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT - | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT - | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT - | prsSignal << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; - - mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK - | _PRS_ASYNC_CH_CTRL_FNSEL_MASK - | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK - | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; - - BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); - - GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); - - (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[prsAsyncCh] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT - | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; - GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + prsAsyncCh); -} -#endif - -/**************************************************************************//** - * @brief - * Set the HFXO crystal tuning capacitance. - * - * @param[in] ctune - * The desired tuning capacitance value. Each step corresponds to - * approximately 80fF. Min value is 0. Max value is 255. - * - * @return - * SL_STATUS_OK if initialization parameter is valid. - * SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid. - * - * @note - * While the oscillator is running in steady operation state, it may be - * desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA - * fields in the HFXO_XTALCTRL register. When tuning, care should be taken to - * make small changes to the CTUNE registers. Ideally, change the CTUNE - * registers by one LSB at a time and alternate between the XI and XO - * registers. Sufficient wait time for settling, on the order of - * TIMEOUTSTEADY, should pass before new frequency measurement is taken. - *****************************************************************************/ -sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) -{ - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // Make sure the given CTUNE value is within the allowable range - if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Keep oscillator running, if it is enabled - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - // Manual override needs COREBIASOPTRDY asserted, - // or the command will be ignored. - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - } - } - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - int32_t ctuneXoana = ctune + CMU_HFXOCTuneDeltaGet(); - if (ctuneXoana < 0) { - ctuneXoana = 0; - } else if (ctuneXoana > (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT)) { - ctuneXoana = (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); // Max value - } - - HFXO0->XTALCTRL = ((HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXOANA_MASK | _HFXO_XTALCTRL_CTUNEXIANA_MASK)) - | ((uint32_t)ctuneXoana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) - | ((ctune << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) & _HFXO_XTALCTRL_CTUNEXIANA_MASK)); - - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); - - // Unforce to return control to hardware request - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); - } - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * @brief - * Get the HFXO crystal tuning capacitance. - * - * @return - * The HFXO crystal tuning capacitance. - * - * @note - This function only returns the CTUNE XI value. The XO value can be - different and can be found using the delta (difference between XI and XO). - See @ref CMU_HFXOCTuneDeltaGet to retrieve the delta value. - *****************************************************************************/ -uint32_t CMU_HFXOCTuneGet(void) -{ - uint32_t ctune = 0; - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // Keep oscillator running, if it is enabled - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - // Manual override needs COREBIASOPTRDY asserted, - // or the command will be ignored. - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - } - } - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) - >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); - - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); - - // Unforce to return control to hardware request - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); - } - - return ctune; -} - -/**************************************************************************//** - * @brief - * Set the HFXO crystal tuning delta. - * - * @param[in] delta - * Chip dependent crystal capacitor bank delta between HFXO XI and XO. - * - * @note - * The delta between XI and XO is applicable for the series 2 EFR32xG2x - * devices only. - *****************************************************************************/ -void CMU_HFXOCTuneDeltaSet(int32_t delta) -{ - ctuneDelta = (int8_t)delta; -} - -/**************************************************************************//** - * @brief - * Get the HFXO crystal tuning delta. - * - * @return - * Chip dependent crystal capacitor bank tuning delta. - *****************************************************************************/ -int32_t CMU_HFXOCTuneDeltaGet(void) -{ - return (int32_t)ctuneDelta; -} - -/**************************************************************************//** - * @brief - * Recalibrate the HFXO's Core Bias Current. - * - * @note - * Care should be taken when using this function as it can cause disturbance - * on the HFXO frequency while the optimization is underway. It's recommended - * to only use this function when HFXO isn't being used. It's also a blocking - * function that can be time consuming. - *****************************************************************************/ -void CMU_HFXOCoreBiasCurrentCalibrate(void) -{ - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // These two bits need to be set to allow writing the registers - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) { - // Wait for crystal to startup - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) - != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { - // Making sure HFXO is in steady state - } - - // Start core bias optimization - HFXO0->CMD_SET = HFXO_CMD_COREBIASOPT; - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == HFXO_STATUS_COREBIASOPTRDY) { - // Wait for core bias optimization to start - } - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - // Wait for core bias optimization to finish - } - - // Force COREBIASANA bitfields modification -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - // Wait for core bias current value to be written in COREBIASANA bitfields - } - - BUS_RegMaskedWrite(&HFXO0->CTRL, (_HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK), hfxoCtrlBkup); -} - -/**************************************************************************//** - * @brief - * Initialize LFXO control registers. - * - * @note - * LFXO configuration should be obtained from a configuration tool, - * app note or crystal datasheet. This function disables the LFXO to ensure - * a valid state before update. - * - * @param[in] lfxoInit - * LFXO setup parameters - *****************************************************************************/ -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) -{ - EFM_ASSERT(lfxoInit->timeout - <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); - EFM_ASSERT(lfxoInit->mode - <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); - EFM_ASSERT(lfxoInit->gain - <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); - EFM_ASSERT(lfxoInit->capTune - <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); - - // Max internal capacitance tuning value is 0x4F (20 pF) - uint8_t ctune = (uint8_t) SL_MIN(0x4FU, lfxoInit->capTune); - -#if defined(CMU_CLKEN0_LFXO) - // Enable LFXO module clock. - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - - // Unlock register interface - LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; - - // Disable LFXO - LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; - LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; - while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { - } - - // Configure LFXO as specified - LFXO->CAL = ((uint32_t)lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) - | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); - - LFXO->CFG = (uint32_t)((lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) - | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) - | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) - | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT)); - - LFXO->CTRL = (uint32_t)((lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) - | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) - | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) - | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT)); - - if (lfxoInit->regLock) { - LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; - } -} - -/**************************************************************************//** - * @brief - * Sets LFXO's crystal precision, in PPM. - * - * @note - * LFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_LFXOPrecisionSet(uint16_t precision) -{ - lfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets LFXO's crystal precision, in PPM. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_LFXOPrecisionGet(void) -{ - return lfxo_precision; -} - -/**************************************************************************//** - * @brief - * Sets HFXO's crystal precision, in PPM. - * - * @note - * HFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_HFXOPrecisionSet(uint16_t precision) -{ - hfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets HFXO's crystal precision, in PPM. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_HFXOPrecisionGet(void) -{ - return hfxo_precision; -} - -#if defined(PLFRCO_PRESENT) -/**************************************************************************//** - * @brief - * Configure the LFRCO precision. - * - * @details - * When enabling high precision mode on the LFRCO the hardware will tune - * the oscillator automatically using the HFXO as a reference. - * - * @note - * Refer to the reference manual and the datasheet for details about - * NOMCAL and NOMCALINV calibration count values. - * - * @param[in] precision - * LFRCO precision, this can be either high or default. - *****************************************************************************/ -void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision) -{ - uint32_t ref = 0; - uint32_t nomcal = 0; - uint32_t nomcalinv = 0; - - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; - - LFRCO->CTRL = LFRCO_CTRL_DISONDEMAND; // Force disable - while ((LFRCO->STATUS & LFRCO_STATUS_ENS) != 0U) { - // Wait for LFRCO to stop - } - - if (precision == cmuPrecisionHigh) { - ref = SystemHFXOClockGet(); - // Use precomputed value for HFXO typical frequencies - if (ref == XTAL_38M4) { - nomcal = LFRCO_NOMCAL_XTAL_38M4; - nomcalinv = LFRCO_NOMCALINV_XTAL_38M4; - } else if (ref == XTAL_39M0) { - nomcal = LFRCO_NOMCAL_XTAL_39M0; - nomcalinv = LFRCO_NOMCALINV_XTAL_39M0; - } else { - // Compute calibration count, based on HFXO frequency - nomcal = (5 * ref) >> 9; - nomcalinv = ((1UL << 31) / 5) << 2; - nomcalinv /= (ref >> 9); - } - - LFRCO->NOMCAL = nomcal; - LFRCO->NOMCALINV = nomcalinv; - - LFRCO->CFG = LFRCO_CFG_HIGHPRECEN; - } else { - LFRCO->CFG = 0; - } - LFRCO->CTRL = _LFRCO_CTRL_RESETVALUE; -} -#endif - -/***************************************************************************//** - * @brief - * Get oscillator frequency tuning setting. - * - * @param[in] osc - * Oscillator to get tuning value for. - * - * @return - * The oscillator frequency tuning setting in use. - ******************************************************************************/ -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) -{ - uint32_t ret = 0U; - - switch (osc) { -#if defined(_LFRCO_CAL_FREQTRIM_MASK) - case cmuOsc_LFRCO: -#if defined(CMU_CLKEN0_LFRCO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; -#endif - ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; - break; -#endif - - case cmuOsc_HFRCODPLL: -#if defined(CMU_CLKEN0_HFRCO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; -#endif - ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuOsc_HFRCOEM23: - ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; - break; -#endif - - case cmuOsc_HFXO: -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - ret = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK) >> _HFXO_XTALCTRL_COREBIASANA_SHIFT; - break; - - case cmuOsc_LFXO: -#if defined(CMU_CLKEN0_LFXO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - ret = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the oscillator frequency tuning control. - * - * @note - * Oscillator tuning is done during production, and the tuning value is - * automatically loaded after a reset. Changing the tuning value from the - * calibrated value is for more advanced use. Certain oscillators also have - * build-in tuning optimization. - * - * @param[in] osc - * Oscillator to set tuning value for. - * - * @param[in] val - * The oscillator frequency tuning setting to use. - ******************************************************************************/ -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) -{ - bool disondemand = false; - bool lfxo_lock_status = false; - uint8_t ctune = 0; - - switch (osc) { -#if defined(_LFRCO_CAL_FREQTRIM_MASK) - case cmuOsc_LFRCO: -#if defined(CMU_CLKEN0_LFRCO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; -#endif - EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK - >> _LFRCO_CAL_FREQTRIM_SHIFT)); - val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; - while (LFRCO->SYNCBUSY != 0U) { - } - LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) - | (val << _LFRCO_CAL_FREQTRIM_SHIFT); - break; -#endif - - case cmuOsc_HFRCODPLL: -#if defined(CMU_CLKEN0_HFRCO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; -#endif - EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); - val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; - while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { - } - HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) - | (val << _HFRCO_CAL_TUNING_SHIFT); - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuOsc_HFRCOEM23: - EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); - val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; - while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { - } - HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) - | (val << _HFRCO_CAL_TUNING_SHIFT); - break; -#endif - - case cmuOsc_HFXO: -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - EFM_ASSERT(val <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); - // Make sure HFXO is disable - EFM_ASSERT((HFXO0->STATUS & HFXO_STATUS_ENS) == 0); - - // Set DISONDEMAND if not already set and wait for FSMLOCK to be clear so that - // software can write to register - disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) >> _HFXO_CTRL_DISONDEMAND_SHIFT; - if (disondemand == false) { - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - } -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - } -#endif - // Update Core Bias Ana setting and enable Optimization skip - HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) - | (val << _HFXO_XTALCTRL_COREBIASANA_SHIFT) - | HFXO_XTALCTRL_SKIPCOREBIASOPT; - // Clear back DISONDEMAND if needed - if (disondemand == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; - } - break; - - case cmuOsc_LFXO: -#if defined(CMU_CLKEN0_LFXO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - lfxo_lock_status = (LFXO->STATUS & _LFXO_STATUS_LOCK_MASK) >> _LFXO_STATUS_LOCK_SHIFT; - // Unlock register interface if register is locked before - if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { - LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; - } - - EFM_ASSERT(val <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); - // Max internal capacitance tuning value is 0x4F (20 pF) - ctune = (uint8_t) SL_MIN(0x4FU, val); - - // Wait for CALBSY bit to clear before writing the tuning value to CAL register - while (((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) >> _LFXO_SYNCBUSY_CAL_SHIFT) != 0U) { - } - LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) - | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); - - // Lock register interface again - if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { - LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; - } - break; - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Configure wait state settings necessary to switch to a given core clock - * frequency at a certain voltage scale level. - * - * @details - * This function will set up the necessary flash wait states. Updating the - * wait state configuration must be done before increasing the clock - * frequency and it must be done after decreasing the clock frequency. - * Updating the wait state configuration must be done before core voltage is - * decreased and it must be done after a core voltage is increased. - * - * @param[in] freq - * The core clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 1, higher number is lower voltage. - * @li 0 = 1.1 V (VSCALE2) - * @li 1 = 1.0 V (VSCALE1) - ******************************************************************************/ -void CMU_UpdateWaitStates(uint32_t freq, int vscale) -{ - if (vscale > 0) { - flashWaitStateControl(freq, VSCALE_EM01_LOW_POWER); - } else { - flashWaitStateControl(freq, VSCALE_EM01_HIGH_PERFORMANCE); - } -} - -/**************************************************************************//** - * @brief - * Select the PCNTn clock. - * - * @param[in] instance - * PCNT instance number to set selected clock source for. - * - * @param[in] external - * Set to true to select the external clock, false to select EM23GRPACLK. - *****************************************************************************/ -void CMU_PCNTClockExternalSet(unsigned int instance, bool external) -{ - (void)instance; -#if defined(PCNT_PRESENT) - if (external) { - CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; - } else { - CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; - } -#else - (void)external; -#endif -} - -#if defined(HFRCOEM23_PRESENT) -/***************************************************************************//** - * @brief - * Get HFRCOEM23 band in use. - * - * @return - * HFRCOEM23 band in use. - ******************************************************************************/ -CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) -{ - return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); -} - -/***************************************************************************//** - * @brief - * Set HFRCOEM23 band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] freq - * HFRCOEM23 frequency band to activate. - ******************************************************************************/ -void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) -{ - uint32_t freqCal; - - // Get calibration data from DEVINFO - freqCal = HFRCOEM23DevinfoGet(freq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); -#if defined(CMU_CLKEN0_HFRCOEM23) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; -#endif - - // Set divider for 1, 2 and 4MHz bands - freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; - switch (freq) { - case cmuHFRCOEM23Freq_1M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV4; - break; - - case cmuHFRCOEM23Freq_2M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV2; - break; - - default: - break; - } - - // Activate new band selection - HFRCOEM23->CAL = freqCal; -} -#endif // defined(HFRCOEM23_PRESENT) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -#if defined(PDM_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM01GRPBCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - switch (CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0: - f = SystemCLKIN0Get(); - s = cmuSelect_CLKIN0; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(EUART_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EUART0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - switch (CMU->EUART0CLKCTRL & _CMU_EUART0CLKCTRL_CLKSEL_MASK) { - case CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(freq, sel); - break; - - case CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(freq, sel); - break; - - default: - if (freq != NULL) { - *freq = 0U; - } - if (sel != NULL) { - *sel = cmuSelect_Error; - } - EFM_ASSERT(false); - break; - } -} -#endif - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EUSART0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EUSART0CLKCTRL & _CMU_EUSART0CLKCTRL_CLKSEL_MASK) { -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK: - em01GrpcClkGet(&f, NULL); - s = cmuSelect_EM01GRPCCLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) - case CMU_EUSART0CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) - case CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) - case CMU_EUSART0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFXO) - case CMU_EUSART0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) - case CMU_EUSART0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -/**************************************************************************//** -* @brief -* Get selected oscillator and frequency for @ref cmuClock_EM01GRPCCLK -* clock tree. -* -* @param[out] freq -* The frequency. -* -* @param[out] sel -* The selected oscillator. -******************************************************************************/ -static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - - case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; -#endif - - case _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(_CMU_EM01GRPCCLKCTRL_MASK) -#endif // defined(EUSART_PRESENT) - -#if defined(LCD_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_LCDCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->LCDCLKCTRL & _CMU_LCDCLKCTRL_CLKSEL_MASK) { - case CMU_LCDCLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_LCDCLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_LCDCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(LCD_PRESENT) - -#if defined(VDAC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_VDAC0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->VDAC0CLKCTRL & _CMU_VDAC0CLKCTRL_CLKSEL_MASK) { - case CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if (VDAC_COUNT > 1) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_VDAC1CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->VDAC1CLKCTRL & _CMU_VDAC1CLKCTRL_CLKSEL_MASK) { - case CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif -#endif /* VDAC_PRESENT */ - -#if defined(PCNT_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_PCNT0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->PCNT0CLKCTRL & _CMU_PCNT0CLKCTRL_CLKSEL_MASK) { - case CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0: - f = 0U; // external or PRS source so the frequency is undefined. - s = cmuSelect_PCNTEXTCLK; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(LESENSE_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_LESENSEHFCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->LESENSEHFCLKCTRL & _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) { - case CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -/***************************************************************************//** - * @brief - * Set maximum allowed prescaler for radio clock tree (RHCLK). - ******************************************************************************/ -static void rhclkPrescMax(void) -{ - // Set largest prescaler (DIV2). - CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_RHCLKPRESC; -} - -/***************************************************************************//** - * @brief - * Set radio clock tree prescaler to achieve highest possible frequency - * and still be within spec. - ******************************************************************************/ -static void rhclkPrescOptimize(void) -{ - if (CMU_ClockFreqGet(cmuClock_SYSCLK) <= CMU_MAX_RHCLK_FREQ) { - // Set smallest prescaler (DIV1). - CMU->SYSCLKCTRL_CLR = CMU_SYSCLKCTRL_RHCLKPRESC; - } -} -#endif // ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -#endif // #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(HFRCOEM23_PRESENT) -/***************************************************************************//** - * @brief - * Get calibrated HFRCOEM23 tuning value from Device information (DI) page - * for a given frequency. Calibration value is not available for all frequency - * bands. - * - * @param[in] freq - * HFRCOEM23 frequency band - ******************************************************************************/ -static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) -{ - uint32_t ret = 0U; - - switch (freq) { - // 1, 2 and 4MHz share the same calibration word - case cmuHFRCOEM23Freq_1M0Hz: - case cmuHFRCOEM23Freq_2M0Hz: - case cmuHFRCOEM23Freq_4M0Hz: - ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_13M0Hz: - ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_16M0Hz: - ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_19M0Hz: - ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_26M0Hz: - ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_32M0Hz: - ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_40M0Hz: - ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_UserDefined: - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} -#endif // defined(HFRCOEM23_PRESENT) - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_TRACECLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) - switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { -#if defined(_CMU_TRACECLKCTRL_CLKSEL_HCLK) - case CMU_TRACECLKCTRL_CLKSEL_HCLK: - f = SystemHCLKGet(); - s = cmuSelect_HCLK; - break; -#endif -#if defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) - case CMU_TRACECLKCTRL_CLKSEL_SYSCLK: - f = SystemSYSCLKGet(); - s = cmuSelect_SYSCLK; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) - case CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } -#else - f = SystemSYSCLKGet(); - s = cmuSelect_SYSCLK; -#endif - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { - case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: - f = SystemCLKIN0Get(); - s = cmuSelect_CLKIN0; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - - case CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - -#if defined(HFRCOEM23_PRESENT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - - case CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - case CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale) -{ - uint32_t flashWs = MSC_READCTRL_MODE_WS3; - - if (vscale == 0) { - // VScale 1.1V core frequency ranges for wait-states configurations. - if (0) { - } -#if defined(CMU_MAX_FREQ_2WS_1V1) - else if (freq > CMU_MAX_FREQ_2WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS3; - } -#endif -#if defined(CMU_MAX_FREQ_1WS_1V1) - else if (freq > CMU_MAX_FREQ_1WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS2; - } -#endif -#if defined(CMU_MAX_FREQ_0WS_1V1) - else if (freq > CMU_MAX_FREQ_0WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS1; - } -#endif - else { - flashWs = MSC_READCTRL_MODE_WS0; - } - } else if (vscale >= 1) { - // VScale 1.0V core frequency ranges for wait-states configurations. - if (0) { - } -#if defined(CMU_MAX_FREQ_2WS_1V0) - else if (freq > CMU_MAX_FREQ_2WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS3; - } -#endif -#if defined(CMU_MAX_FREQ_1WS_1V0) - else if (freq > CMU_MAX_FREQ_1WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS2; - } -#endif -#if defined(CMU_MAX_FREQ_0WS_1V0) - else if (freq > CMU_MAX_FREQ_0WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS1; - } -#endif - else { - flashWs = MSC_READCTRL_MODE_WS0; - } - } - return flashWs; -} - -/***************************************************************************//** - * @brief - * Configure flash access wait states to support the given core clock - * frequency and vscale level. - * - * @note Current implementation sets wait states depending on frequency only. - * This assumes that applications running on Vscale enabled microcontrollers - * never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). - * Series 2 Config 1 devices does not support vscale. - * - * @param[in] coreFreq - * The core clock frequency to configure flash wait-states. - * - * @param[in] vscale - * Voltage Scale level. Supported levels are 0 and 1 where 0 is the default. - * @li 0 = 1.1 V (VSCALE2) - * @li 1 = 1.0 V (VSCALE1) - ******************************************************************************/ -static void flashWaitStateControl(uint32_t coreFreq, int vscale) -{ - (void)vscale; - - uint32_t mode; - bool mscLocked; - -#if defined(CMU_CLKEN1_MSC) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - coreFreq *= CMU_ClockDivGet(cmuClock_CORE); -#endif - - // Make sure the MSC is unlocked - mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - // Get current flash read setting - mode = MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK; - - // Set new mode based on the core clock frequency - mode |= getWaitStatesByFrequencyAndVScale(coreFreq, vscale); - - MSC_ReadCTRLSet(mode); - - // Set sram wait states for config 1 mcu. -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - // Set new mode based on the core clock frequency - if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { - SYSCFG_setDmem0RamCtrlRamwsenBit(); - } else { - SYSCFG_clearDmem0RamCtrlRamwsenBit(); - } -#endif - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -/***************************************************************************//** - * @brief - * Get calibrated HFRCODPLL tuning value from Device information (DI) page - * for a given frequency. Calibration value is not available for all frequency - * bands. - * - * @param[in] freq - * HFRCODPLL frequency band - ******************************************************************************/ -static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) -{ - uint32_t ret = 0U; - - switch (freq) { - // 1, 2 and 4MHz share the same calibration word - case cmuHFRCODPLLFreq_1M0Hz: - case cmuHFRCODPLLFreq_2M0Hz: - case cmuHFRCODPLLFreq_4M0Hz: - ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_7M0Hz: - ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_13M0Hz: - ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_16M0Hz: - ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_19M0Hz: - ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_26M0Hz: - ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_32M0Hz: - ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_38M0Hz: - ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_48M0Hz: - ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_56M0Hz: - ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_64M0Hz: - ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_80M0Hz: - ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; - break; - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - case cmuHFRCODPLLFreq_100M0Hz: - ret = DEVINFO->HFRCODPLLCAL[17].HFRCODPLLCAL; - break; -#endif - - case cmuHFRCODPLLFreq_UserDefined: - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} - -#if defined(IADC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_IADCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { - case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - -#if defined(HFRCOEM23_PRESENT) - case CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - - case CMU_IADCCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/***************************************************************************//** - * @brief - * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. - ******************************************************************************/ -static void pclkDivMax(void) -{ - // Set largest divisor for PCLK clock tree. - CMU_ClockDivSet(cmuClock_PCLK, 2U); -} - -/***************************************************************************//** - * @brief - * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible - * frequency and still be within spec. - ******************************************************************************/ -static void pclkDivOptimize(void) -{ - CMU_ClkDiv_TypeDef div = 2U; - - if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { - div = 1U; - } - CMU_ClockDivSet(cmuClock_PCLK, div); -} - -#if defined(RTCC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { - case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_RTCCCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(SYSRTC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_SYSRTCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/***************************************************************************//** - * @brief - * Set wait-states to values valid for maximum allowable core clock frequency. - ******************************************************************************/ -static void waitStateMax(void) -{ - flashWaitStateControl(SystemMaxCoreClockGet(), 0); -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { - case CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: - f = SystemHCLKGet() / 1024U; - s = cmuSelect_HCLKDIV1024; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { - case CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: - f = SystemHCLKGet() / 1024U; - s = cmuSelect_HCLKDIV1024; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_SYSTICK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { - f = SystemHCLKGet(); - s = cmuSelect_HCLK; - } else { - em23GrpaClkGet(&f, &s); - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(USB_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_USB clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->USB0CLKCTRL & _CMU_USB0CLKCTRL_CLKSEL_MASK) { - case CMU_USB0CLKCTRL_CLKSEL_USBPLL0: - f = PLL0_USB_OUTPUT_FREQ; - s = cmuSelect_USBPLL0; - break; - - case CMU_USB0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_USB0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/** @endcond */ - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** The maximum allowed core frequency when using 0 wait-states on flash access. */ -#define CMU_MAX_FREQ_0WS 16000000 -/** The maximum allowed core frequency when using 1 wait-states on flash access */ -#define CMU_MAX_FREQ_1WS 32000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) -// EFR32xG1x and EFM32xG1x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) -// EFR32xG12x and EFM32xG12x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V1 21330000 -#define CMU_MAX_FREQ_1WS_1V1 32000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) -// EFR32xG13x and EFM32xG13x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) -// EFR32xG14x and EFM32xG14x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) -// EFM32GG11x -#define CMU_MAX_FREQ_0WS_1V2 18000000 -#define CMU_MAX_FREQ_1WS_1V2 36000000 -#define CMU_MAX_FREQ_2WS_1V2 54000000 -#define CMU_MAX_FREQ_3WS_1V2 72000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) -// EFM32TG11x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 48000000 -#define CMU_MAX_FREQ_0WS_1V0 10000000 -#define CMU_MAX_FREQ_1WS_1V0 21000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) -// EFM32GG12x -#define CMU_MAX_FREQ_0WS_1V2 18000000 -#define CMU_MAX_FREQ_1WS_1V2 36000000 -#define CMU_MAX_FREQ_2WS_1V2 54000000 -#define CMU_MAX_FREQ_3WS_1V2 72000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#else -#error "Max Flash wait-state frequencies are not defined for this platform." -#endif - -/** The maximum frequency for the HFLE interface. */ -#if defined(CMU_CTRL_HFLE) -/** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_WONDER_FAMILY) \ - || defined(_EZR32_WONDER_FAMILY)) -#define CMU_MAX_FREQ_HFLE 24000000UL -/** The maximum HFLE frequency for other series 0 parts with maximum core clock - higher than 32 MHz. */ -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EZR32_LEOPARD_FAMILY)) -#define CMU_MAX_FREQ_HFLE maxFreqHfle() -#endif -#elif defined(CMU_CTRL_WSHFLE) -/** The maximum HFLE frequency for series 1 parts. */ -#define CMU_MAX_FREQ_HFLE 32000000UL -#endif - -#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) -#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) -#elif defined(CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) -#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) -#endif - -#if defined(CMU_HFXOCTRL_MODE_EXTCLK) -/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ -#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK -#endif - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) -#define VSCALE_DEFAULT ((int)EMU_VScaleGet()) -#else -#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; -#endif -#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) -#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) -#endif - -#if defined(CMU_OSCENCMD_DPLLEN) -/** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and - an optional band enumerator. */ -static const struct hfrcoCtrlTableElement{ - uint32_t minFreq; - uint32_t maxFreq; - uint32_t value; - CMU_HFRCOFreq_TypeDef band; -} hfrcoCtrlTable[] = -{ - // minFreq maxFreq HFRCOCTRL value band - { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, - { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, - { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, - { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, - { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, - { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, - { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, - { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, - { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, - { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, - { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, - { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, - { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } -#else - #error "HFRCOCTRL values not set for this platform." -#endif -}; - -#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ - / sizeof(struct hfrcoCtrlTableElement)) -#endif // CMU_OSCENCMD_DPLLEN - -#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) -/* Devices with Voltage Scaling needs extra handling of wait states. */ -static const struct flashWsTableElement{ - uint32_t maxFreq; - uint8_t vscale; - uint8_t ws; -} flashWsTable[] = -{ -#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) - { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ - { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ - { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ - { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ - { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ - { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ - { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ -#else - { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ - { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ - { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ - { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ - { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ -#endif -}; - -#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ - || defined(_CMU_USHFRCOTUNE_MASK) -#ifndef EFM32_USHFRCO_STARTUP_FREQ -#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) -#endif - -static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; -#endif - -/******************************************************************************* - ************************** LOCAL PROTOTYPES ******************************* - ******************************************************************************/ -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); -#endif - -static void hfperClkSafePrescaler(void); -static void hfperClkOptimizedPrescaler(void); - -static uint16_t lfxo_precision = 0xFFFF; -static uint16_t hfxo_precision = 0xFFFF; - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EZR32_LEOPARD_FAMILY)) -/***************************************************************************//** - * @brief - * Return maximum allowed frequency for low energy peripherals. - ******************************************************************************/ -static uint32_t maxFreqHfle(void) -{ - uint16_t majorMinorRev; - - switch (SYSTEM_GetFamily()) { - case systemPartFamilyEfm32Leopard: - case systemPartFamilyEzr32Leopard: - /* CHIP MAJOR bit [5:0] */ - majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); - /* CHIP MINOR bit [7:4] */ - majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); - /* CHIP MINOR bit [3:0] */ - majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); - - if (majorMinorRev >= 0x0204) { - return 24000000; - } else { - return 32000000; - } - - case systemPartFamilyEfm32Giant: - return 32000000; - - default: - /* Invalid device family. */ - EFM_ASSERT(false); - return 0; - } -} -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Unified definitions for the HFLE wait-state and prescaler fields. */ -#if defined(CMU_CTRL_HFLE) -#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK -#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT -#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV -#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK -#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT -#elif defined(CMU_CTRL_WSHFLE) -#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK -#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT -#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC -#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK -#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT -#endif -/** @endcond */ - -/***************************************************************************//** - * @brief - * Set HFLE wait-states and HFCLKLE prescaler according to wanted HF clock. - * - * @param[in] hfFreq - * The HF clock frequency to use. - * This is: - * CORE clock on Series0 devices. - * HF clock on on Series1 devices. - ******************************************************************************/ -static void setHfLeConfig(uint32_t hfFreq) -{ - unsigned int hfleWs; - uint32_t hflePresc; - - /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the - fields are changed to more than 1 bit. */ - EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); - - /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is - above maxLeFreq. - - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ - - hfleWs = 1; - if (hfFreq <= CMU_MAX_FREQ_HFLE) { - hfleWs = 0; - hflePresc = 0; - } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { - hflePresc = 1; - } else { - hflePresc = 2; - } - BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); - GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) - | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); -} - -#if defined(_CMU_CTRL_HFLE_MASK) -/***************************************************************************//** - * @brief - * Get HFLE wait-state configuration. - * - * @return - * The current wait-state configuration. - ******************************************************************************/ -static uint32_t getHfLeConfig(void) -{ - uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); - return ws; -} -#endif -#endif - -/***************************************************************************//** - * @brief - * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, - * by default also as a debug clock. - * - * @return - * AUX Frequency in Hz. - ******************************************************************************/ -static uint32_t auxClkGet(void) -{ - uint32_t ret; - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) - ret = (uint32_t)auxHfrcoFreq; - -#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) - /* All series 0 families except EFM32G */ - switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { - case CMU_AUXHFRCOCTRL_BAND_1MHZ: - if ( SYSTEM_GetProdRev() >= 19 ) { - ret = 1200000; - } else { - ret = 1000000; - } - break; - - case CMU_AUXHFRCOCTRL_BAND_7MHZ: - if ( SYSTEM_GetProdRev() >= 19 ) { - ret = 6600000; - } else { - ret = 7000000; - } - break; - - case CMU_AUXHFRCOCTRL_BAND_11MHZ: - ret = 11000000; - break; - - case CMU_AUXHFRCOCTRL_BAND_14MHZ: - ret = 14000000; - break; - - case CMU_AUXHFRCOCTRL_BAND_21MHZ: - ret = 21000000; - break; - -#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) - case CMU_AUXHFRCOCTRL_BAND_28MHZ: - ret = 28000000; - break; -#endif - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - -#else - /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ - ret = 14000000; - -#endif - - return ret; -} - -#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ - || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) -/***************************************************************************//** - * @brief - * Get the HFSRCCLK frequency. - * - * @return - * HFSRCCLK Frequency in Hz. - ******************************************************************************/ -static uint32_t hfSrcClkGet(void) -{ - uint32_t ret; - - ret = SystemHFClockGet(); - return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT)); -} -#endif - -/***************************************************************************//** - * @brief - * Get the Debug Trace clock frequency. - * - * @return - * Debug Trace frequency in Hz. - ******************************************************************************/ -static uint32_t dbgClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get selected clock source */ - clk = CMU_ClockSelectGet(cmuClock_DBG); - - switch (clk) { - case cmuSelect_HFCLK: - ret = SystemHFClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) -/***************************************************************************//** - * @brief - * Get the ADC n asynchronous clock frequency. - * - * @return - * ADC n asynchronous frequency in Hz. - ******************************************************************************/ -static uint32_t adcAsyncClkGet(uint32_t adc) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - switch (adc) { - case 0: - clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); - break; - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case 1: - clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); - break; -#endif - - default: - EFM_ASSERT(false); - return 0; - } - - switch (clk) { - case cmuSelect_Disabled: - ret = 0; - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_HFSRCCLK: - ret = hfSrcClkGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_SDIOCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the SDIO reference clock frequency. - * - * @return - * SDIO reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t sdioRefClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_SDIOREF); - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_QSPICTRL_MASK) -/***************************************************************************//** - * @brief - * Get the QSPI n reference clock frequency. - * - * @return - * QSPI n reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t qspiRefClkGet(uint32_t qspi) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - switch (qspi) { - case 0: - clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); - break; - - default: - EFM_ASSERT(false); - return 0; - } - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_PDMCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the PDM reference clock frequency. - * - * @return - * PDM reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t pdmRefClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_PDMREF); - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(USBR_CLOCK_PRESENT) -/***************************************************************************//** - * @brief - * Get the USB rate clock frequency. - * - * @return - * USB rate clock frequency in Hz. - ******************************************************************************/ -static uint32_t usbRateClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - clk = CMU_ClockSelectGet(cmuClock_USBR); - - switch (clk) { - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_HFXOX2: - ret = 2u * SystemHFXOClockGet(); - break; - - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_LFXO: - ret = SystemLFXOClockGet(); - break; - - case cmuSelect_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -/***************************************************************************//** - * @brief - * Configure flash access wait states to support the given core clock - * frequency. - * - * @param[in] coreFreq - * The core clock frequency to configure flash wait-states. - * - * @param[in] vscale - * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. - ******************************************************************************/ -static void flashWaitStateControl(uint32_t coreFreq, int vscale) -{ - uint32_t mode; -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ -#endif - (void) vscale; /* vscale parameter is only used on some devices. */ - - /* Get mode and SCBTP enable. */ - mode = MSC_ReadCTRLGet() & _MSC_READCTRL_MODE_MASK; - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - /* Devices with MODE and SCBTP in the same register field. */ - switch (mode) { - case MSC_READCTRL_MODE_WS0: - case MSC_READCTRL_MODE_WS1: -#if defined(MSC_READCTRL_MODE_WS2) - case MSC_READCTRL_MODE_WS2: -#endif - scbtpEn = false; - break; - - default: /* WSxSCBTP */ - scbtpEn = true; - break; - } - - /* Set mode based on the core clock frequency and SCBTP enable. */ - if (false) { - } -#if defined(MSC_READCTRL_MODE_WS2) - else if (coreFreq > CMU_MAX_FREQ_1WS) { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); - } -#endif - else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); - } else { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); - } -#else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ - - if (coreFreq <= CMU_MAX_FREQ_0WS) { - mode = 0; - } else if (coreFreq <= CMU_MAX_FREQ_1WS) { - mode = 1; - } -#endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ -// End defined(_SILICON_LABS_32B_SERIES_0) - -#elif defined(_SILICON_LABS_32B_SERIES_1) -#if defined(_EMU_STATUS_VSCALE_MASK) - - /* These devices have specific requirements on the supported flash wait state - * depending on the frequency and voltage scale level. */ - uint32_t i; - for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { - if ((flashWsTable[i].vscale == (uint8_t)vscale) - && (coreFreq <= flashWsTable[i].maxFreq)) { - break; // Found a matching entry. - } - } - - if (i == FLASH_WS_TABLE_ENTRIES) { - mode = 3; // Worst case flash wait state for unsupported cases. - EFM_ASSERT(false); - } else { - mode = flashWsTable[i].ws; - } - mode = mode << _MSC_READCTRL_MODE_SHIFT; - -#else - /* Devices where MODE and SCBTP are in separate fields and where the device - * either does not support voltage scale or where the voltage scale does - * not impact the flash wait state configuration. */ - if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { - mode = 0; - } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { - mode = 1; - } -#if defined(MSC_READCTRL_MODE_WS2) - else if (coreFreq <= CMU_MAX_FREQ_2WS) { - mode = 2; - } -#endif -#if defined(MSC_READCTRL_MODE_WS3) - else if (coreFreq <= CMU_MAX_FREQ_3WS) { - mode = 3; - } -#endif - mode = mode << _MSC_READCTRL_MODE_SHIFT; -#endif -// End defined(_SILICON_LABS_32B_SERIES_1) - -#else -#error "Undefined 32B SERIES!" -#endif - - mode = (MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK) | mode; - MSC_ReadCTRLSet(mode); -} - -/***************************************************************************//** - * @brief - * Configure flash access wait states to the most conservative setting for - * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) - * setting. - ******************************************************************************/ -static void flashWaitStateMax(void) -{ - /* Make sure the MSC is unlocked */ - bool mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - flashWaitStateControl(SystemMaxCoreClockGet(), 0); - - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) -/***************************************************************************//** - * @brief - * Configure RAM access wait states to support the given core clock - * frequency. - * - * @param[in] coreFreq - * The core clock frequency to configure RAM wait-states. - * - * @param[in] vscale - * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. - ******************************************************************************/ -static void setRamWaitState(uint32_t coreFreq, int vscale) -{ - uint32_t limit = 38000000; - if (vscale == 2) { - limit = 16000000; - } - - if (coreFreq > limit) { - BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); - } else { - BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); - } -} -#endif - -#if defined(_MSC_CTRL_WAITMODE_MASK) -/***************************************************************************//** - * @brief - * Configure the wait state for peripheral accesses over the bus to support - * the given bus clock frequency. - * - * @param[in] busFreq - * A peripheral bus clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 2. - * - * @li 0 = 1.2 V (VSCALE2) - * @li 2 = 1.0 V (VSCALE0) - * ******************************************************************************/ -static void setBusWaitState(uint32_t busFreq, int vscale) -{ - if ((busFreq > 50000000) && (vscale == 0)) { - BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); - } else { - BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); - } -} -#endif - -#if defined(PLFRCO_PRESENT) -static bool deviceHasPlfrco(void) -{ - SYSTEM_ChipRevision_TypeDef rev; - - if (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) { - // check the xG13 rev and check if it's >= Rev A3 - SYSTEM_ChipRevisionGet(&rev); - return (rev.major > 1) || (rev.minor >= 3); - } else { - return false; - } -} -#endif - -/***************************************************************************//** - * @brief - * Configure various wait states to switch to a certain frequency - * and a certain voltage scale. - * - * @details - * This function will set up the necessary flash, bus, and RAM wait states. - * Updating the wait state configuration must be done before - * increasing the clock frequency and it must be done after decreasing the - * clock frequency. Updating the wait state configuration must be done before - * core voltage is decreased and it must be done after a core voltage is - * increased. - * - * @param[in] freq - * The core clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 2, higher number is lower voltage. - * - * @li 0 = 1.2 V (VSCALE2) - * @li 2 = 1.0 V (VSCALE0) - * - ******************************************************************************/ -void CMU_UpdateWaitStates(uint32_t freq, int vscale) -{ - /* Make sure the MSC is unlocked */ - bool mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - flashWaitStateControl(freq, vscale); -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) - setRamWaitState(freq, vscale); -#endif -#if defined(_MSC_CTRL_WAITMODE_MASK) - setBusWaitState(freq, vscale); -#endif - - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) -/***************************************************************************//** - * @brief - * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. - ******************************************************************************/ -static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) -{ - uint32_t regIshUpper; - const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK - >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; - /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ - regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); - regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; - return regIshUpper; -} -#endif - -#if defined(_CMU_HFXOCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the HFXO tuning mode. - * - * @return - * The current HFXO tuning mode from the HFXOCTRL register. - ******************************************************************************/ -__STATIC_INLINE uint32_t getHfxoTuningMode(void) -{ -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; -#else - return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) - >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; -#endif -} - -/***************************************************************************//** - * @brief - * Set the HFXO tuning mode. - * - * @param[in] mode - * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or - * HFXO_TUNING_MODE_CMD. - ******************************************************************************/ -__STATIC_INLINE void setHfxoTuningMode(uint32_t mode) -{ -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); -#else - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) - | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Get the LFnCLK frequency based on the current configuration. - * - * @param[in] lfClkBranch - * Selected LF branch. - * - * @return - * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is - * returned. - ******************************************************************************/ -static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) -{ - uint32_t sel; - uint32_t ret = 0; - - switch (lfClkBranch) { - case cmuClock_LFA: - case cmuClock_LFB: -#if defined(_CMU_LFCCLKEN0_MASK) - case cmuClock_LFC: -#endif -#if defined(_CMU_LFECLKSEL_MASK) - case cmuClock_LFE: -#endif - break; - - default: - EFM_ASSERT(false); - break; - } - - sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); - - /* Get clock select field */ - switch (lfClkBranch) { - case cmuClock_LFA: -#if defined(_CMU_LFCLKSEL_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; -#elif defined(_CMU_LFACLKSEL_MASK) - sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; - - case cmuClock_LFB: -#if defined(_CMU_LFCLKSEL_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; -#elif defined(_CMU_LFBCLKSEL_MASK) - sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; - -#if defined(_CMU_LFCCLKEN0_MASK) - case cmuClock_LFC: -#if defined(_CMU_LFCLKSEL_LFC_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; -#elif defined(_CMU_LFCCLKSEL_LFC_MASK) - sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; -#endif - -#if defined(_CMU_LFECLKSEL_MASK) - case cmuClock_LFE: - sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - /* Get the clock frequency. */ -#if defined(_CMU_LFCLKSEL_MASK) - switch (sel) { - case _CMU_LFCLKSEL_LFA_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - case _CMU_LFCLKSEL_LFA_LFXO: - ret = SystemLFXOClockGet(); - break; - -#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) - case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: -#if defined(CMU_MAX_FREQ_HFLE) - /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the - * frequency of CMU_HFCORECLKLEDIV2. */ - ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); -#else - ret = SystemCoreClockGet() / 2U; -#endif - break; -#endif - - case _CMU_LFCLKSEL_LFA_DISABLED: - ret = 0; -#if defined(CMU_LFCLKSEL_LFAE) - /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ - if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { - if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA - ? _CMU_LFCLKSEL_LFAE_SHIFT - : _CMU_LFCLKSEL_LFBE_SHIFT)) { - ret = SystemULFRCOClockGet(); - } - } -#endif - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } -#endif /* _CMU_LFCLKSEL_MASK */ - -#if defined(_CMU_LFACLKSEL_MASK) - switch (sel) { - case _CMU_LFACLKSEL_LFA_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - case _CMU_LFACLKSEL_LFA_LFXO: - ret = SystemLFXOClockGet(); - break; - - case _CMU_LFACLKSEL_LFA_ULFRCO: - ret = SystemULFRCOClockGet(); - break; - -#if defined(PLFRCO_PRESENT) - case _CMU_LFACLKSEL_LFA_PLFRCO: - ret = SystemLFRCOClockGet(); - break; -#endif - -#if defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) - case _CMU_LFBCLKSEL_LFB_HFCLKLE: - ret = SystemHFClockGet() - / SL_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) - >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); - break; -#endif - - case _CMU_LFACLKSEL_LFA_DISABLED: - ret = 0; - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } -#endif - - return ret; -} - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to low-frequency domain to complete. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void syncReg(uint32_t mask) -{ - /* Avoid a deadlock if modifying the same register twice when freeze mode is */ - /* activated. */ - if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { - return; - } - - /* Wait for any pending previous write operation to complete */ - /* in low-frequency domain. */ - while ((CMU->SYNCBUSY & mask) != 0UL) { - } -} - -#if defined(USBC_CLOCK_PRESENT) -/***************************************************************************//** - * @brief - * Get the USBC frequency. - * - * @return - * USBC frequency in Hz. - ******************************************************************************/ -static uint32_t usbCClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_USBC); - - switch (clk) { - case cmuSelect_LFXO: - ret = SystemLFXOClockGet(); - break; - case cmuSelect_LFRCO: - ret = SystemLFRCOClockGet(); - break; -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; -#endif - case cmuSelect_HFCLK: - ret = SystemHFClockGet(); - break; - default: - /* Clock is not enabled */ - ret = 0; - break; - } - return ret; -} -#endif - -/***************************************************************************//** - * @brief - * Set HFPER clock tree prescalers to safe values. - * - * @note - * This function applies to EFM32GG11B. There are 3 HFPER clock trees with - * these frequency limits: - * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. - * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - ******************************************************************************/ -static void hfperClkSafePrescaler(void) -{ -#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ - && defined(_CMU_HFPERPRESCC_MASK) - // Assuming a maximum HFCLK of 72MHz, set prescalers to DIV4. - CMU_ClockPrescSet(cmuClock_HFPER, 3U); - CMU_ClockPrescSet(cmuClock_HFPERB, 3U); - CMU_ClockPrescSet(cmuClock_HFPERC, 3U); -#endif -} - -/***************************************************************************//** - * @brief - * Set HFPER clock tree prescalers to give highest possible clock node - * frequency while still beeing within spec. - * - * @note - * This function applies to EFM32GG11B. There are 3 HFPER clock trees with - * these frequency limits: - * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. - * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - ******************************************************************************/ -static void hfperClkOptimizedPrescaler(void) -{ -#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ - && defined(_CMU_HFPERPRESCC_MASK) - uint32_t hfClkFreq, divisor; - - hfClkFreq = SystemHFClockGet(); - - if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { - divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) - if (divisor > 0U) { - divisor--; // Convert to prescaler - } - CMU_ClockPrescSet(cmuClock_HFPER, divisor); - CMU_ClockPrescSet(cmuClock_HFPERB, divisor); - CMU_ClockPrescSet(cmuClock_HFPERC, divisor); - } else { - divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; - if (divisor > 0U) { - divisor--; - } - CMU_ClockPrescSet(cmuClock_HFPER, divisor); - CMU_ClockPrescSet(cmuClock_HFPERC, divisor); - - divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; - if (divisor > 0U) { - divisor--; - } - CMU_ClockPrescSet(cmuClock_HFPERB, divisor); - } -#endif -} - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Get the AUXHFRCO band in use. - * - * @return - * AUXHFRCO band in use. - ******************************************************************************/ -CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) -{ - return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL - & _CMU_AUXHFRCOCTRL_BAND_MASK) - >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); -} -#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Set the AUXHFRCO band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] band - * AUXHFRCO band to activate. - ******************************************************************************/ -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) -{ - uint32_t tuning; - - /* Read a tuning value from the calibration table. */ - switch (band) { - case cmuAUXHFRCOBand_1MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; - break; - - case cmuAUXHFRCOBand_7MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; - break; - - case cmuAUXHFRCOBand_11MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; - break; - - case cmuAUXHFRCOBand_14MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; - break; - - case cmuAUXHFRCOBand_21MHz: - tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) - >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; - break; - -#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) - case cmuAUXHFRCOBand_28MHz: - tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) - >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* Set band/tuning. */ - CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL - & ~(_CMU_AUXHFRCOCTRL_BAND_MASK - | _CMU_AUXHFRCOCTRL_TUNING_MASK)) - | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) - | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -} -#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the AUXHFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * AUXHFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) -{ - switch (freq) { - /* 1, 2, and 4 MHz share the same calibration word. */ - case cmuAUXHFRCOFreq_1M0Hz: - case cmuAUXHFRCOFreq_2M0Hz: - case cmuAUXHFRCOFreq_4M0Hz: - return DEVINFO->AUXHFRCOCAL0; - - case cmuAUXHFRCOFreq_7M0Hz: - return DEVINFO->AUXHFRCOCAL3; - - case cmuAUXHFRCOFreq_13M0Hz: - return DEVINFO->AUXHFRCOCAL6; - - case cmuAUXHFRCOFreq_16M0Hz: - return DEVINFO->AUXHFRCOCAL7; - - case cmuAUXHFRCOFreq_19M0Hz: - return DEVINFO->AUXHFRCOCAL8; - - case cmuAUXHFRCOFreq_26M0Hz: - return DEVINFO->AUXHFRCOCAL10; - - case cmuAUXHFRCOFreq_32M0Hz: - return DEVINFO->AUXHFRCOCAL11; - - case cmuAUXHFRCOFreq_38M0Hz: - return DEVINFO->AUXHFRCOCAL12; - -#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) - case cmuAUXHFRCOFreq_48M0Hz: - return DEVINFO->AUXHFRCOCAL13; -#endif -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) - case cmuAUXHFRCOFreq_50M0Hz: - return DEVINFO->AUXHFRCOCAL14; -#endif - - default: /* cmuAUXHFRCOFreq_UserDefined */ - return 0; - } -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/***************************************************************************//** - * @brief - * Get the current AUXHFRCO frequency. - * - * @return - * AUXHFRCO frequency. - ******************************************************************************/ -CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) -{ - return auxHfrcoFreq; -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/***************************************************************************//** - * @brief - * Set AUXHFRCO calibration for the selected target frequency. - * - * @param[in] setFreq - * AUXHFRCO frequency to set - ******************************************************************************/ -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - - /* Get DEVINFO index and set global auxHfrcoFreq. */ - freqCal = CMU_AUXHFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - auxHfrcoFreq = setFreq; - - /* Wait for any previous sync to complete, then set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { - } - - /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ - switch (setFreq) { - case cmuAUXHFRCOFreq_1M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; - break; - - case cmuAUXHFRCOFreq_2M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; - break; - - case cmuAUXHFRCOFreq_4M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; - break; - - default: - break; - } - CMU->AUXHFRCOCTRL = freqCal; -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -/***************************************************************************//** - * @brief - * Calibrate the clock. - * - * @details - * Run a calibration for HFCLK against a selectable reference clock. - * See the reference manual, CMU chapter, for more details. - * - * @note - * This function will not return until the calibration measurement is completed. - * - * @param[in] HFCycles - * The number of HFCLK cycles to run the calibration. Increasing this number - * increases precision but the calibration will take more time. - * - * @param[in] reference - * The reference clock used to compare HFCLK. - * - * @return - * The number of ticks the reference clock after HFCycles ticks on the HF - * clock. - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) -{ - EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); - - /* Set the reference clock source. */ - switch (reference) { - case cmuOsc_LFXO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuOsc_LFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuOsc_HFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - return 0; - } - - /* Set the top value. */ - CMU->CALCNT = HFCycles; - - /* Start the calibration. */ - CMU->CMD = CMU_CMD_CALSTART; - -#if defined(CMU_STATUS_CALRDY) - /* Wait until calibration completes. */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { - } -#else - /* Wait until calibration completes. */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - - return CMU->CALCNT; -} - -#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) -/***************************************************************************//** - * @brief - * Configure the clock calibration. - * - * @details - * Configure a calibration for a selectable clock source against another - * selectable reference clock. - * See the reference manual, CMU chapter, for more details. - * - * @note - * After configuration, a call to @ref CMU_CalibrateStart() is required and - * the resulting calibration value can be read out with the - * @ref CMU_CalibrateCountGet() function call. - * - * @param[in] downCycles - * The number of downSel clock cycles to run the calibration. Increasing this - * number increases precision but the calibration will take more time. - * - * @param[in] downSel - * The clock, which will be counted down downCycles. - * - * @param[in] upSel - * The reference clock; the number of cycles generated by this clock will - * be counted and added up and the result can be given with the - * @ref CMU_CalibrateCountGet() function call. - ******************************************************************************/ -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, - CMU_Osc_TypeDef upSel) -{ - /* Keep configuration settings untouched. */ - uint32_t calCtrl = CMU->CALCTRL - & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); - - /* 20 bits of precision to calibration count register. */ - EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); - - /* Set down counting clock source - down counter. */ - switch (downSel) { - case cmuOsc_LFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; - break; - - case cmuOsc_LFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; - break; - - case cmuOsc_HFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - /* Set the top value to be counted down by the downSel clock. */ - CMU->CALCNT = downCycles; - - /* Set the reference clock source - up counter. */ - switch (upSel) { - case cmuOsc_LFXO: - calCtrl |= CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuOsc_LFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - calCtrl |= CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuOsc_HFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - CMU->CALCTRL = calCtrl; -} -#endif - -/***************************************************************************//** - * @brief - * Get the calibration count register. - * @note - * If continuous calibration mode is active, calibration busy will almost - * always be off and only the value needs to be read. In a normal case, - * this function call is triggered by the CALRDY - * interrupt flag. - * @return - * The calibration count, the number of UPSEL clocks - * in the period of DOWNSEL oscillator clock cycles configured by a previous - * write operation to CMU->CALCNT. - ******************************************************************************/ -uint32_t CMU_CalibrateCountGet(void) -{ - /* Wait until calibration completes, UNLESS continuous calibration mode is */ - /* active. */ -#if defined(CMU_CALCTRL_CONT) - if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { -#if defined(CMU_STATUS_CALRDY) - /* Wait until calibration completes */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { - } -#else - /* Wait until calibration completes */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - } -#else - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - return CMU->CALCNT; -} - -/***************************************************************************//** - * @brief - * Get the clock divisor/prescaler. - * - * @param[in] clock - * A clock point to get the divisor/prescaler for. Notice that not all clock points - * have a divisor/prescaler. See the CMU overview in the reference manual. - * - * @return - * The current clock point divisor/prescaler. 1 is returned - * if @p clock specifies a clock point without a divisor/prescaler. - ******************************************************************************/ -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - return 1UL + (uint32_t)CMU_ClockPrescGet(clock); - -#elif defined(_SILICON_LABS_32B_SERIES_0) - uint32_t divReg; - CMU_ClkDiv_TypeDef ret; - - /* Get divisor reg ID. */ - divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; - - switch (divReg) { -#if defined(_CMU_CTRL_HFCLKDIV_MASK) - case CMU_HFCLKDIV_REG: - ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) - >> _CMU_CTRL_HFCLKDIV_SHIFT); - break; -#endif - - case CMU_HFPERCLKDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV - & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - - case CMU_HFCORECLKDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV - & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) - >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - case CMU_HFCORECLKLEDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV - & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - >> _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); - ret = SL_Log2ToDiv(ret + 1U); - break; -#endif - - case CMU_LFAPRESC0_REG: - switch (clock) { - case cmuClock_RTC: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCDpre: - ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT) - + CMU_DivToLog2(cmuClkDiv_16)); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - break; - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - - return ret; -#endif -} - -/***************************************************************************//** - * @brief - * Set the clock divisor/prescaler. - * - * @note - * If setting an LF clock prescaler, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * Clock point to set divisor/prescaler for. Notice that not all clock points - * have a divisor/prescaler. See the CMU overview in the reference - * manual. - * - * @param[in] div - * The clock divisor to use (<= cmuClkDiv_512). - ******************************************************************************/ -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); - -#elif defined(_SILICON_LABS_32B_SERIES_0) - uint32_t freq; - uint32_t divReg; - - /* Get the divisor reg ID. */ - divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; - - switch (divReg) { -#if defined(_CMU_CTRL_HFCLKDIV_MASK) - case CMU_HFCLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); - - /* Configure worst case wait states for flash access before setting divisor. */ - flashWaitStateMax(); - - /* Set the divider. */ - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) - | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); - - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - - /* Optimize flash access wait state setting for the current core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - break; -#endif - - case CMU_HFPERCLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); - break; - -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - case CMU_HFCORECLKLEDIV_REG: - /* - This divisor is usually set when changing HF clock to keep HFLE clock - within safe bounds. This code path ignore these constraints. - */ - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div) - 1U; - CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV - & ~_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - | (div << _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); - break; -#endif - - case CMU_HFCORECLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); - - /* Configure worst case wait states for flash access before setting the divisor. */ - flashWaitStateMax(); - -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet() / div); -#endif - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV - & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) - | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); - - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - - /* Optimize wait state setting for the current core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(freq); -#endif - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { - case cmuClock_RTC: - EFM_ASSERT(div <= cmuClkDiv_32768); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) - | (div << _CMU_LFAPRESC0_RTC_SHIFT); - break; - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - EFM_ASSERT(div <= cmuClkDiv_32768); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) - | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); - break; -#endif - -#if defined(LCD_PRESENT) - case cmuClock_LCDpre: - EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) - | ((div - CMU_DivToLog2(cmuClkDiv_16)) - << _CMU_LFAPRESC0_LCD_SHIFT); - break; -#endif /* defined(LCD_PRESENT) */ - -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) - | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); - break; -#endif /* defined(LESENSE_PRESENT) */ - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) - | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) - | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - default: - EFM_ASSERT(false); - break; - } -#endif -} - -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @details - * In general, module clocking is disabled after a reset. If a module - * clock is disabled, the registers of that module are not accessible and - * reading from such registers may return undefined values. Writing to - * registers of clock-disabled modules has no effect. - * Avoid accessing module registers of a module with a disabled clock. - * - * @note - * If enabling/disabling an LF clock, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * The clock to enable/disable. Notice that not all defined clock - * points have separate enable/disable control. See the CMU overview - * in the reference manual. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - volatile uint32_t *reg; - uint32_t bit; - uint32_t sync = 0; - - /* Identify enable register */ - switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { -#if defined(_CMU_CTRL_HFPERCLKEN_MASK) - case CMU_CTRL_EN_REG: - reg = &CMU->CTRL; - break; -#endif - -#if defined(_CMU_HFCORECLKEN0_MASK) - case CMU_HFCORECLKEN0_EN_REG: - reg = &CMU->HFCORECLKEN0; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif - break; -#endif - -#if defined(_CMU_HFBUSCLKEN0_MASK) - case CMU_HFBUSCLKEN0_EN_REG: - reg = &CMU->HFBUSCLKEN0; - break; -#endif - -#if defined(_CMU_HFPERCLKDIV_MASK) - case CMU_HFPERCLKDIV_EN_REG: - reg = &CMU->HFPERCLKDIV; - break; -#endif - - case CMU_HFPERCLKEN0_EN_REG: - reg = &CMU->HFPERCLKEN0; - break; - -#if defined(_CMU_HFPERCLKEN1_MASK) - case CMU_HFPERCLKEN1_EN_REG: - reg = &CMU->HFPERCLKEN1; - break; -#endif - - case CMU_LFACLKEN0_EN_REG: - reg = &CMU->LFACLKEN0; - sync = CMU_SYNCBUSY_LFACLKEN0; - break; - - case CMU_LFBCLKEN0_EN_REG: - reg = &CMU->LFBCLKEN0; - sync = CMU_SYNCBUSY_LFBCLKEN0; - break; - -#if defined(_CMU_LFCCLKEN0_MASK) - case CMU_LFCCLKEN0_EN_REG: - reg = &CMU->LFCCLKEN0; - sync = CMU_SYNCBUSY_LFCCLKEN0; - break; -#endif - -#if defined(_CMU_LFECLKEN0_MASK) - case CMU_LFECLKEN0_EN_REG: - reg = &CMU->LFECLKEN0; - sync = CMU_SYNCBUSY_LFECLKEN0; - break; -#endif - -#if defined(_CMU_SDIOCTRL_MASK) - case CMU_SDIOREF_EN_REG: - reg = &CMU->SDIOCTRL; - enable = !enable; - break; -#endif - -#if defined(_CMU_QSPICTRL_MASK) - case CMU_QSPI0REF_EN_REG: - reg = &CMU->QSPICTRL; - enable = !enable; - break; -#endif -#if defined(_CMU_USBCTRL_MASK) - case CMU_USBRCLK_EN_REG: - reg = &CMU->USBCTRL; - break; -#endif -#if defined(_CMU_PDMCTRL_MASK) - case CMU_PDMREF_EN_REG: - reg = &CMU->PDMCTRL; - break; -#endif - - case CMU_PCNT_EN_REG: - reg = &CMU->PCNTCTRL; - break; - - default: /* Cannot enable/disable a clock point. */ - EFM_ASSERT(false); - return; - } - - /* Get the bit position used to enable/disable. */ - bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; - - /* LF synchronization required. */ - if (sync > 0UL) { - syncReg(sync); - } - - /* Set/clear bit as requested. */ - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Get the clock frequency for a clock point. - * - * @param[in] clock - * A clock point to fetch the frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret; - - switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { - case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - break; - - case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPER divider. */ -#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; -#endif -#if defined(_CMU_HFPERPRESC_PRESC_MASK) - ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) - >> _CMU_HFPERPRESC_PRESC_SHIFT); -#endif - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPERB prescaler. */ - ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) - >> _CMU_HFPERPRESCB_PRESC_SHIFT); - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPERC prescaler. */ - ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) - >> _CMU_HFPERPRESCC_PRESC_SHIFT); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -#if defined(CRYPTO_PRESENT) \ - || defined(LDMA_PRESENT) \ - || defined(GPCRC_PRESENT) \ - || defined(PRS_PRESENT) \ - || defined(GPIO_PRESENT) - case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); -#if defined(_CMU_HFBUSPRESC_MASK) - ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) - >> _CMU_HFBUSPRESC_PRESC_SHIFT); -#endif - break; -#endif - - case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) - >> _CMU_HFCOREPRESC_PRESC_SHIFT); - break; - - case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) - >> _CMU_HFEXPPRESC_PRESC_SHIFT); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(AES_PRESENT) \ - || defined(DMA_PRESENT) \ - || defined(EBI_PRESENT) \ - || defined(USB_PRESENT) - case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - { - ret = SystemCoreClockGet(); - } break; -#endif -#endif - - case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - break; - -#if defined(_CMU_LFACLKEN0_RTC_MASK) - case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT; - break; -#endif - -#if defined(_CMU_LFECLKEN0_RTCC_MASK) - case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFE); - ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) - >> _CMU_LFEPRESC0_RTCC_SHIFT; - break; -#endif - -#if defined(_CMU_LFACLKEN0_LETIMER0_MASK) - case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFACLKEN0_LETIMER1_MASK) - case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFACLKEN0_LCD_MASK) - case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT) - + CMU_DivToLog2(cmuClkDiv_16); -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT); -#endif - break; - -#if defined(_CMU_LCDCTRL_MASK) - case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT; - ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) - >> _CMU_LCDCTRL_FDIV_SHIFT); - break; -#endif -#endif - -#if defined(_CMU_LFACLKEN0_LESENSE_MASK) - case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT; - break; -#endif - - case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); - break; - -#if defined(_CMU_LFBCLKEN0_LEUART0_MASK) - case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFBCLKEN0_LEUART1_MASK) - case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFBCLKEN0_CSEN_MASK) - case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); - ret /= SL_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) - >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); - break; -#endif - -#if defined(CMU_LFCCLKEN0_USB) - case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFC); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) - case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFE); - break; -#endif - - case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = dbgClkGet(); - break; - - case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = auxClkGet(); - break; - -#if defined(USBC_CLOCK_PRESENT) - case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = usbCClkGet(); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = adcAsyncClkGet(0); -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = adcAsyncClkGet(1); -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = sdioRefClkGet(); - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = qspiRefClkGet(0); - break; -#endif - -#if defined(USBR_CLOCK_PRESENT) - case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = usbRateClkGet(); - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = pdmRefClkGet(); - break; -#endif - - case (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - ret = SystemCoreClockGet() / CMU_ClockDivGet(clock); -#elif defined(_CMU_HFPRESC_HFCLKLEPRESC_MASK) - ret = SystemHFClockGet() / CMU_ClockDivGet(clock); -#else - ret = SystemCoreClockGet() / 2; -#endif - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - - return ret; -} - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Get the clock prescaler. - * - * @param[in] clock - * A clock point to get the prescaler for. Notice that not all clock points - * have a prescaler. See the CMU overview in the reference manual. - * - * @return - * The prescaler value of the current clock point. 0 is returned - * if @p clock specifies a clock point without a prescaler. - ******************************************************************************/ -uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) -{ - uint32_t prescReg; - uint32_t ret; - - /* Get the prescaler register ID. */ - prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; - - switch (prescReg) { - case CMU_HFPRESC_REG: - ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT; - break; - - case CMU_HFEXPPRESC_REG: - ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) - >> _CMU_HFEXPPRESC_PRESC_SHIFT; - break; - - case CMU_HFCLKLEPRESC_REG: - ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) - >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; - ret = SL_Log2ToDiv(ret + 1U) - 1U; - break; - - case CMU_HFPERPRESC_REG: - ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) - >> _CMU_HFPERPRESC_PRESC_SHIFT; - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case CMU_HFPERPRESCB_REG: - ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) - >> _CMU_HFPERPRESCB_PRESC_SHIFT; - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case CMU_HFPERPRESCC_REG: - ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) - >> _CMU_HFPERPRESCC_PRESC_SHIFT; - break; -#endif - - case CMU_HFCOREPRESC_REG: - ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) - >> _CMU_HFCOREPRESC_PRESC_SHIFT; - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) - case cmuClock_LETIMER1: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCD: - case cmuClock_LCDpre: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_RTC_MASK) - case cmuClock_RTC: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFBPRESC0_CSEN_MASK) - case cmuClock_CSEN_LF: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) - >> _CMU_LFBPRESC0_CSEN_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret + 4U) - 1U; - break; -#endif - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFEPRESC0_REG: - switch (clock) { -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) - >> _CMU_LFEPRESC0_RTCC_SHIFT; - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; -#endif - } - break; - -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ - || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case CMU_ADCASYNCDIV_REG: - switch (clock) { -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - case cmuClock_ADC0ASYNC: - ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; - break; -#endif -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case cmuClock_ADC1ASYNC: - ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; - break; -#endif - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(_CMU_HFBUSPRESC_MASK) - case CMU_HFBUSPRESC_REG: - ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) - >> _CMU_HFBUSPRESC_PRESC_SHIFT; - break; -#endif - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - - return ret; -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Set the clock prescaler. - * - * @note - * If setting an LF clock prescaler, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * A clock point to set the prescaler for. Notice that not all clock points - * have a prescaler. See the CMU overview in the reference manual. - * - * @param[in] presc - * The clock prescaler. The prescaler value is linked to the clock divider by: - * divider = 'presc' + 1. - ******************************************************************************/ -void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) -{ - uint32_t freq; - uint32_t prescReg; - - /* Get the divisor reg ID. */ - prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; - - switch (prescReg) { - case CMU_HFPRESC_REG: - EFM_ASSERT(presc < 32U); - - /* Configure worst case wait-states for flash and HFLE, set safe HFPER - clock-tree prescalers. */ - flashWaitStateMax(); - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); - hfperClkSafePrescaler(); - - CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) - | (presc << _CMU_HFPRESC_PRESC_SHIFT); - - /* Update the CMSIS core clock variable (this function updates the global - variable). */ - freq = SystemCoreClockGet(); - /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree - prescalers. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - setHfLeConfig(SystemHFClockGet()); - hfperClkOptimizedPrescaler(); - break; - - case CMU_HFEXPPRESC_REG: - EFM_ASSERT(presc < 32U); - - CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) - | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); - break; - - case CMU_HFCLKLEPRESC_REG: - presc = CMU_DivToLog2(presc); - CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) - | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); - break; - - case CMU_HFPERPRESC_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) - | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case CMU_HFPERPRESCB_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) - | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case CMU_HFPERPRESCC_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) - | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); - break; -#endif - - case CMU_HFCOREPRESC_REG: - EFM_ASSERT(presc < 512U); - - /* Configure worst case wait-states for flash. */ - flashWaitStateMax(); - - CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) - | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); - - /* Update the CMSIS core clock variable (this function updates the global variable). - Optimize flash and HFLE wait states. */ - freq = SystemCoreClockGet(); - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { -#if defined(RTC_PRESENT) - case cmuClock_RTC: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) - | (presc << _CMU_LFAPRESC0_RTC_SHIFT); - break; -#endif - -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: -#if defined(_CMU_LFEPRESC0_RTCC_MASK) -#if defined(_CMU_LFEPRESC0_RTCC_DIV4) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); -#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); -#else - EFM_ASSERT(presc <= 0U); -#endif - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFEPRESC0); - - CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) - | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); -#else - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) - | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) - | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) - case cmuClock_LETIMER1: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) - | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) - | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCDpre: - case cmuClock_LCD: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) - | (presc << _CMU_LFAPRESC0_LCD_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) - | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) - | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_CSEN_MASK) - case cmuClock_CSEN_LF: - EFM_ASSERT((presc <= 127U) && (presc >= 15U)); - - /* Convert the prescaler value to a DIV exponent scale. - * DIV16 is the lowest supported prescaler. */ - presc = CMU_PrescToLog2(presc) - 4U; - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) - | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFEPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFEPRESC0_RTCC_MASK) - case cmuClock_RTCC: -#if defined(_CMU_LFEPRESC0_RTCC_DIV4) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); -#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); -#else - EFM_ASSERT(presc <= 0U); -#endif - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFEPRESC0); - - CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) - | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ - || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case CMU_ADCASYNCDIV_REG: - switch (clock) { -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - case cmuClock_ADC0ASYNC: - EFM_ASSERT(presc <= 3); - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) - | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case cmuClock_ADC1ASYNC: - EFM_ASSERT(presc <= 3); - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) - | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); - break; -#endif - default: - EFM_ASSERT(false); - break; - } - break; -#endif - -#if defined(_CMU_HFBUSPRESC_MASK) - case CMU_HFBUSPRESC_REG: - EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); - CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) - | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} -#endif - -/***************************************************************************//** - * @brief - * Get the currently selected reference clock used for a clock branch. - * - * @param[in] clock - * Clock branch to fetch selected ref. clock for. One of: - * @li #cmuClock_HF - * @li #cmuClock_LFA - * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO - * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_SERIES_1 - * @li #cmuClock_LFE - * @endif - * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT - * @li #cmuClock_USBC - * @endif - * - * @return - * The reference clock used for clocking the selected branch, #cmuSelect_Error if - * invalid @p clock provided. - ******************************************************************************/ -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef ret = cmuSelect_Disabled; - uint32_t selReg; - - selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; - - switch (selReg) { - case CMU_HFCLKSEL_REG: -#if defined(_CMU_HFCLKSTATUS_MASK) - switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { - case CMU_HFCLKSTATUS_SELECTED_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_HFCLKSTATUS_SELECTED_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_HFCLKSTATUS_SELECTED_HFXO: - ret = cmuSelect_HFXO; - break; - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: - ret = cmuSelect_HFRCODIV2; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case CMU_HFCLKSTATUS_SELECTED_CLKIN0: - ret = cmuSelect_CLKIN0; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case CMU_HFCLKSTATUS_SELECTED_USHFRCO: - ret = cmuSelect_USHFRCO; - break; -#endif - - default: - ret = cmuSelect_HFRCO; - break; - } -#else - switch (CMU->STATUS - & (CMU_STATUS_HFRCOSEL - | CMU_STATUS_HFXOSEL - | CMU_STATUS_LFRCOSEL -#if defined(CMU_STATUS_USHFRCODIV2SEL) - | CMU_STATUS_USHFRCODIV2SEL -#endif - | CMU_STATUS_LFXOSEL)) { - case CMU_STATUS_LFXOSEL: - ret = cmuSelect_LFXO; - break; - - case CMU_STATUS_LFRCOSEL: - ret = cmuSelect_LFRCO; - break; - - case CMU_STATUS_HFXOSEL: - ret = cmuSelect_HFXO; - break; - -#if defined(CMU_STATUS_USHFRCODIV2SEL) - case CMU_STATUS_USHFRCODIV2SEL: - ret = cmuSelect_USHFRCODIV2; - break; -#endif - - default: - ret = cmuSelect_HFRCO; - break; - } -#endif - break; - -#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) - case CMU_LFACLKSEL_REG: -#if defined(_CMU_LFCLKSEL_MASK) - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { - case CMU_LFCLKSEL_LFA_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFA_LFXO: - ret = cmuSelect_LFXO; - break; - -#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) - case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: - ret = cmuSelect_HFCLKLE; - break; -#endif - - default: -#if defined(CMU_LFCLKSEL_LFAE) - if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { - ret = cmuSelect_ULFRCO; - break; - } -#else - ret = cmuSelect_Disabled; -#endif - break; - } - -#elif defined(_CMU_LFACLKSEL_MASK) - switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { - case CMU_LFACLKSEL_LFA_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFACLKSEL_LFA_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFACLKSEL_LFA_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFACLKSEL_LFA_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } -#endif - break; -#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ - -#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) - case CMU_LFBCLKSEL_REG: -#if defined(_CMU_LFCLKSEL_MASK) - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { - case CMU_LFCLKSEL_LFB_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFB_LFXO: - ret = cmuSelect_LFXO; - break; - -#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) - case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: - ret = cmuSelect_HFCLKLE; - break; -#endif - -#if defined(CMU_LFCLKSEL_LFB_HFCLKLE) - case CMU_LFCLKSEL_LFB_HFCLKLE: - ret = cmuSelect_HFCLKLE; - break; -#endif - - default: -#if defined(CMU_LFCLKSEL_LFBE) - if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { - ret = cmuSelect_ULFRCO; - break; - } -#else - ret = cmuSelect_Disabled; -#endif - break; - } - -#elif defined(_CMU_LFBCLKSEL_MASK) - switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { - case CMU_LFBCLKSEL_LFB_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFBCLKSEL_LFB_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFBCLKSEL_LFB_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - - case CMU_LFBCLKSEL_LFB_HFCLKLE: - ret = cmuSelect_HFCLKLE; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFBCLKSEL_LFB_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } -#endif - break; -#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ - -#if defined(_CMU_LFCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { - case CMU_LFCLKSEL_LFC_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFC_LFXO: - ret = cmuSelect_LFXO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_LFECLKSEL_LFE_MASK) - case CMU_LFECLKSEL_REG: - switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { - case CMU_LFECLKSEL_LFE_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFECLKSEL_LFE_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFECLKSEL_LFE_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFECLKSEL_LFE_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif /* CMU_LFECLKSEL_REG */ - -#if defined(_CMU_LFCCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { - case CMU_LFCCLKSEL_LFC_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCCLKSEL_LFC_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFCCLKSEL_LFC_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif /* CMU_LFCCLKSEL_REG */ - - case CMU_DBGCLKSEL_REG: -#if defined(_CMU_DBGCLKSEL_DBG_MASK) - switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { - case CMU_DBGCLKSEL_DBG_HFCLK: - ret = cmuSelect_HFCLK; - break; - - case CMU_DBGCLKSEL_DBG_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - -#elif defined(_CMU_CTRL_DBGCLK_MASK) - switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { - case CMU_CTRL_DBGCLK_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_CTRL_DBGCLK_HFCLK: - ret = cmuSelect_HFCLK; - break; - } -#else - ret = cmuSelect_AUXHFRCO; -#endif - break; - -#if defined(USBC_CLOCK_PRESENT) - case CMU_USBCCLKSEL_REG: - switch (CMU->STATUS - & (CMU_STATUS_USBCLFXOSEL -#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) - | CMU_STATUS_USBCHFCLKSEL -#endif -#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) - | CMU_STATUS_USBCUSHFRCOSEL -#endif - | CMU_STATUS_USBCLFRCOSEL)) { -#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) - case CMU_STATUS_USBCHFCLKSEL: - ret = cmuSelect_HFCLK; - break; -#endif - -#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) - case CMU_STATUS_USBCUSHFRCOSEL: - ret = cmuSelect_USHFRCO; - break; -#endif - - case CMU_STATUS_USBCLFXOSEL: - ret = cmuSelect_LFXO; - break; - - case CMU_STATUS_USBCLFRCOSEL: - ret = cmuSelect_LFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case CMU_ADC0ASYNCSEL_REG: - switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { - case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: - ret = cmuSelect_Disabled; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: - ret = cmuSelect_HFSRCCLK; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case CMU_ADC1ASYNCSEL_REG: - switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { - case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: - ret = cmuSelect_Disabled; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: - ret = cmuSelect_HFSRCCLK; - break; - } - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case CMU_SDIOREFSEL_REG: - switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { - case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - } - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case CMU_QSPI0REFSEL_REG: - switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { - case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - } - break; -#endif - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) - case CMU_USBRCLKSEL_REG: - switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { - case CMU_USBCTRL_USBCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - - case CMU_USBCTRL_USBCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_USBCTRL_USBCLKSEL_HFXOX2: - ret = cmuSelect_HFXOX2; - break; - - case CMU_USBCTRL_USBCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_USBCTRL_USBCLKSEL_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_USBCTRL_USBCLKSEL_LFRCO: - ret = cmuSelect_LFRCO; - break; - } - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case CMU_PDMREFSEL_REG: - switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { - case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - - case CMU_PDMCTRL_PDMCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_PDMCTRL_PDMCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - } - break; -#endif - - default: - ret = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the System Core Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigSystemCoreClock(void) -{ -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif -} - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the HF Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigHFClock(void) -{ -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * an LF clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and LFXO or LFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc) -{ - if (osc == (uint8_t)cmuOsc_LFXO) { - // Enable LFXO oscillator - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - // Enable LFRCO oscillator - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - } else { - EFM_ASSERT(false); - } - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_SILICON_LABS_32B_SERIES_1) - // Select HF clock source. - if (osc == (uint8_t)cmuOsc_LFXO) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; - } -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - // Select HF clock source. - if (osc == (uint8_t)cmuOsc_LFXO) { - CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; - } -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFXO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFXO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFXO(void) -{ -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = SystemHFXOClockGet(); - EMU_VScaleEM01ByClock(vScaleFrequency, false); -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - // This is known after 'select' is written below. - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif -#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) - // Adjust HFXO buffer current for frequencies above 32 MHz. - if (SystemHFXOClockGet() > 32000000) { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; - } else { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; - } -#endif - - // Enable HFXO oscillator - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Wait for voltage upscaling to complete before the clock is set. - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - -#if defined(CMU_HFCLKSEL_HF_HFXO) - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(CMU_CMD_HFCLKSEL_HFXO) - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Keep EMU module informed on the source HF clock frequency. This will apply voltage - // downscaling after clock is set if downscaling is configured. - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCO(void) -{ -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = 0; /* Use default. */ - if (((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); - } - if (vScaleFrequency != 0UL) { - EMU_VScaleEM01ByClock(vScaleFrequency, false); - } -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - // This is known after 'select' is written below. - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif - - // Enable HFRCO oscillator - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Wait for voltage upscaling to complete before the clock is set. - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Keep EMU module informed on the source HF clock frequency. This will apply voltage - // downscaling after clock is set if downscaling is configured. - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCODIV2(void) -{ - // Enable USHFRCO oscillator - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCODIV2(void) -{ - // Enable HFRCO oscillator - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * CLKIN0 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and CLKIN0 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectCLKIN0(void) -{ - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_CLKIN0; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCO(void) -{ - // Enable USHFRCO oscillator - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_USHFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -/***************************************************************************//** - * @brief - * Select the reference clock/oscillator used for a clock branch. - * - * @details - * Notice that if a selected reference is not enabled prior to selecting its - * use, it will be enabled and this function will wait for the selected - * oscillator to be stable. It will however NOT be disabled if another - * reference clock is selected later. - * - * This feature is particularly important if selecting a new reference - * clock for the clock branch clocking the core. Otherwise, the system - * may halt. - * - * @note - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * A clock branch to select reference clock for. One of: - * @li #cmuClock_HF - * @li #cmuClock_LFA - * @li #cmuClock_LFB - * @if _CMU_LFCCLKEN0_MASK - * @li #cmuClock_LFC - * @endif - * @if _CMU_LFECLKEN0_MASK - * @li #cmuClock_LFE - * @endif - * @li #cmuClock_DBG - * @if _CMU_CMD_USBCLKSEL_MASK - * @li #cmuClock_USBC - * @endif - * @if _CMU_USBCTRL_MASK - * @li #cmuClock_USBR - * @endif - * - * @param[in] ref - * A reference selected for clocking. See the reference manual - * for details about references available for a specific clock branch. - * @li #cmuSelect_HFRCO - * @li #cmuSelect_LFRCO - * @li #cmuSelect_HFXO - * @if _CMU_HFXOCTRL_HFXOX2EN_MASK - * @li #cmuSelect_HFXOX2 - * @endif - * @li #cmuSelect_LFXO - * @li #cmuSelect_HFCLKLE - * @li #cmuSelect_AUXHFRCO - * @if _CMU_USHFRCOCTRL_MASK - * @li #cmuSelect_USHFRCO - * @endif - * @li #cmuSelect_HFCLK - * @ifnot DOXYDOC_EFM32_GECKO_FAMILY - * @li #cmuSelect_ULFRCO - * @endif - * @if CMU_OSCENCMD_PLFRCOEN - * @li #cmuSelect_PLFRCO - * @endif - ******************************************************************************/ -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) -{ - uint32_t select = (uint32_t)cmuOsc_HFRCO; - CMU_Osc_TypeDef osc = cmuOsc_HFRCO; - uint32_t freq; - uint32_t tmp; - uint32_t selRegId; -#if defined(_SILICON_LABS_32B_SERIES_1) - volatile uint32_t *selReg = NULL; -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) - uint32_t lfExtended = 0; -#endif - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = 0; /* Use default. */ - - /* Start voltage upscaling before the clock is set. */ - if (clock == cmuClock_HF) { - if (ref == cmuSelect_HFXO) { - vScaleFrequency = SystemHFXOClockGet(); - } else if ((ref == cmuSelect_HFRCO) - && ((uint32_t)CMU_HFRCOBandGet() - > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); - } else { - /* Use the default frequency. */ - } - if (vScaleFrequency != 0UL) { - EMU_VScaleEM01ByClock(vScaleFrequency, false); - } - } -#endif - - selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; - - switch (selRegId) { - case CMU_HFCLKSEL_REG: - switch (ref) { - case cmuSelect_LFXO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_LFXO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_LFXO; -#endif - osc = cmuOsc_LFXO; - break; - - case cmuSelect_LFRCO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_LFRCO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_LFRCO; -#endif - osc = cmuOsc_LFRCO; - break; - - case cmuSelect_HFXO: -#if defined(CMU_HFCLKSEL_HF_HFXO) - select = CMU_HFCLKSEL_HF_HFXO; -#elif defined(CMU_CMD_HFCLKSEL_HFXO) - select = CMU_CMD_HFCLKSEL_HFXO; -#endif - osc = cmuOsc_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - This is known after 'select' is written below. */ - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif -#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) - /* Adjust HFXO buffer current for frequencies above 32 MHz. */ - if (SystemHFXOClockGet() > 32000000) { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; - } else { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; - } -#endif - break; - - case cmuSelect_HFRCO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_HFRCO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_HFRCO; -#endif - osc = cmuOsc_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - This is known after 'select' is written below. */ - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif - break; - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - case cmuSelect_USHFRCODIV2: - select = CMU_CMD_HFCLKSEL_USHFRCODIV2; - osc = cmuOsc_USHFRCO; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case cmuSelect_HFRCODIV2: - select = CMU_HFCLKSEL_HF_HFRCODIV2; - osc = cmuOsc_HFRCO; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case cmuSelect_CLKIN0: - select = CMU_HFCLKSEL_HF_CLKIN0; - osc = cmuOsc_CLKIN0; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case cmuSelect_USHFRCO: - select = CMU_HFCLKSEL_HF_USHFRCO; - osc = cmuOsc_USHFRCO; - break; -#endif - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - case cmuSelect_ULFRCO: - /* ULFRCO cannot be used as HFCLK. */ - EFM_ASSERT(false); - return; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - if (osc != cmuOsc_CLKIN0) { - CMU_OscillatorEnable(osc, true, true); - } -#else - CMU_OscillatorEnable(osc, true, true); -#endif - - /* Configure worst case wait-states for flash and set safe HFPER - clock-tree prescalers. */ - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* Wait for voltage upscaling to complete before the clock is set. */ - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - - /* Switch to the selected oscillator. */ -#if defined(_CMU_HFCLKSEL_MASK) - CMU->HFCLKSEL = select; -#else - CMU->CMD = select; -#endif - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - -#if defined(CMU_MAX_FREQ_HFLE) - /* Update the HFLE configuration after 'select' is set. - Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ -#if defined(_SILICON_LABS_32B_SERIES_0) - setHfLeConfig(freq); -#else - setHfLeConfig(SystemHFClockGet()); -#endif -#endif - - /* Optimize flash access wait state setting for the currently selected core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* Keep EMU module informed on the source HF clock frequency. This will apply voltage - downscaling after clock is set if downscaling is configured. */ - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - /* Set optimized HFPER clock-tree prescalers. */ - hfperClkOptimizedPrescaler(); - break; - -#if defined(_SILICON_LABS_32B_SERIES_1) - case CMU_LFACLKSEL_REG: - selReg = &CMU->LFACLKSEL; - /* HFCLKCLE can't be used as LFACLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH - /* Fall through and select the clock source. */ - -#if defined(_CMU_LFCCLKSEL_MASK) - case CMU_LFCCLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; - /* HFCLKCLE can't be used as LFCCLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH -#endif - /* Fall through and select the clock source. */ - - case CMU_LFECLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; - /* HFCLKCLE can't be used as LFECLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH - /* Fall through and select the clock source. */ - - case CMU_LFBCLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFACLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFACLKSEL_LFA_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFACLKSEL_LFA_LFRCO; - break; - - case cmuSelect_HFCLKLE: - /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ - setHfLeConfig(SystemHFClockGet()); - BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); - tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; - break; - - case cmuSelect_ULFRCO: - /* ULFRCO is always on, there is no need to enable it. */ - tmp = _CMU_LFACLKSEL_LFA_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); - tmp = _CMU_LFACLKSEL_LFA_PLFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - *selReg = tmp; - break; - -#elif defined(_SILICON_LABS_32B_SERIES_0) - case CMU_LFACLKSEL_REG: - case CMU_LFBCLKSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFCLKSEL_LFA_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFCLKSEL_LFA_LFRCO; - break; - - case cmuSelect_HFCLKLE: -#if defined(CMU_MAX_FREQ_HFLE) - /* Set the HFLE wait-state and divider. */ - freq = SystemCoreClockGet(); - setHfLeConfig(freq); -#endif - /* Ensure HFCORE to LE clocking is enabled. */ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); - tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; - break; - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) - case cmuSelect_ULFRCO: - /* ULFRCO is always enabled. */ - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - lfExtended = 1; - break; -#endif - - default: - /* An illegal clock source for LFA/LFB selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - if (selRegId == CMU_LFACLKSEL_REG) { -#if defined(_CMU_LFCLKSEL_LFAE_MASK) - CMU->LFCLKSEL = (CMU->LFCLKSEL - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) - | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) - | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); -#else - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) - | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); -#endif - } else { -#if defined(_CMU_LFCLKSEL_LFBE_MASK) - CMU->LFCLKSEL = (CMU->LFCLKSEL - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) - | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) - | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); -#else - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) - | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); -#endif - } - break; - -#if defined(_CMU_LFCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFCLKSEL_LFC_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFCLKSEL_LFC_LFRCO; - break; - - default: - /* An illegal clock source for LFC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) - | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); - break; -#endif -#endif - -#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) - case CMU_DBGCLKSEL_REG: - switch (ref) { -#if defined(_CMU_DBGCLKSEL_DBG_MASK) - case cmuSelect_AUXHFRCO: - /* Select AUXHFRCO as a debug clock. */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; - break; - - case cmuSelect_HFCLK: - /* Select divided HFCLK as a debug clock. */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; - break; -#endif - -#if defined(CMU_CTRL_DBGCLK) - case cmuSelect_AUXHFRCO: - /* Select AUXHFRCO as a debug clock. */ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) - | CMU_CTRL_DBGCLK_AUXHFRCO; - break; - - case cmuSelect_HFCLK: - /* Select divided HFCLK as a debug clock. */ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) - | CMU_CTRL_DBGCLK_HFCLK; - break; -#endif - - default: - /* An illegal clock source for debug selected. */ - EFM_ASSERT(false); - return; - } - break; -#endif - -#if defined(USBC_CLOCK_PRESENT) - case CMU_USBCCLKSEL_REG: - switch (ref) { - case cmuSelect_LFXO: - /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { - } - break; - - case cmuSelect_LFRCO: - /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { - } - break; - -#if defined(CMU_STATUS_USBCHFCLKSEL) - case cmuSelect_HFCLK: - /* Select undivided HFCLK as a clock source for USB. */ - /* The oscillator must already be enabled to avoid a core lockup. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { - } - break; -#endif - -#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) - case cmuSelect_USHFRCO: - /* Select USHFRCO as a clock source for USB. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { - } - break; -#endif - - default: - /* An illegal clock source for USB. */ - EFM_ASSERT(false); - return; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case CMU_ADC0ASYNCSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; - break; - - case cmuSelect_HFSRCCLK: - tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; - break; - - default: - /* An illegal clock source for ADC0ASYNC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) - | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case CMU_ADC1ASYNCSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; - break; - - case cmuSelect_HFSRCCLK: - tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; - break; - - default: - /* An illegal clock source for ADC1ASYNC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) - | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case CMU_SDIOREFSEL_REG: - switch (ref) { - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; - break; - - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; - break; - - default: - /* An illegal clock source for SDIOREF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case CMU_QSPI0REFSEL_REG: - switch (ref) { - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; - break; - - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; - break; - - default: - /* An illegal clock source for QSPI0REF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) - case CMU_USBRCLKSEL_REG: - switch (ref) { - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; - break; - - case cmuSelect_HFXOX2: - /* Only allowed for HFXO frequencies up to 25 MHz. */ - EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); - - /* Enable HFXO X2. */ - CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; - - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - - tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; - break; - - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; - break; - - default: - /* An illegal clock source for USBR selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) - | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case CMU_PDMREFSEL_REG: - switch (ref) { - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; - break; - - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; - break; - - default: - /* An illegal clock source for PDMREF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) - | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified low frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_LFXO: - precision = lfxo_precision; - break; - -#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: - precision = 500; - break; -#endif - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified high frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_HFXO: - precision = hfxo_precision; - break; - - case cmuSelect_HFRCO: - precision = 0xFFFF; - break; - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -#if defined(CMU_OSCENCMD_DPLLEN) -/**************************************************************************//** - * @brief - * Lock the DPLL to a given frequency. - * - * The frequency is given by: Fout = Fref * (N+1) / (M+1). - * - * @note - * This function does not check if the given N & M values will actually - * produce the desired target frequency. @n - * N & M limitations: @n - * 300 < N <= 4095 @n - * 0 <= M <= 4095 @n - * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to - * calling this function to avoid over-clocking. - * - * HFCLKLE prescaler is automatically modified before updating HFRCO - * based on the maximum HFLE frequency allowed. - * - * @param[in] init - * DPLL setup parameters. - * - * @return - * Returns false on invalid target frequency or DPLL locking error. - *****************************************************************************/ -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) -{ - int index = 0; - unsigned int i; - bool hfrcoDiv2override = false; - uint32_t hfrcoCtrlVal, lockStatus, sysFreq; - - EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); - EFM_ASSERT(init->frequency - <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); - EFM_ASSERT(init->n > 300U); - EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); - EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); - EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK - >> _CMU_HFRCOSS_SSINV_SHIFT)); - EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK - >> _CMU_HFRCOSS_SSAMP_SHIFT)); - -#if defined(_EMU_STATUS_VSCALE_MASK) - if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) - && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EFM_ASSERT(false); - return false; - } -#endif - - // Find the correct HFRCO band and retrieve a HFRCOCTRL value. - for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { - if ((init->frequency >= hfrcoCtrlTable[i].minFreq) - && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { - index = (int)i; // Correct band found - break; - } - } - if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { - EFM_ASSERT(false); - return false; // Target frequency out of spec. - } - hfrcoCtrlVal = hfrcoCtrlTable[index].value; - - // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. - if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { - uint32_t tuning; - - tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) - & _CMU_HFRCOCTRL_TUNING_MASK) - >> _CMU_HFRCOCTRL_TUNING_SHIFT; - - // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency - // of the band shifts down by 5.8%. 9 is subtracted to compensate. - if (tuning > 9UL) { - tuning -= 9UL; - } else { - tuning = 0UL; - } - - hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; - } - - // Update the CMSIS frequency SystemHfrcoFreq value. - SystemHfrcoFreq = init->frequency; - - // Set maximum wait-states while changing the core clock. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - flashWaitStateMax(); - } - - // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - setHfLeConfig(init->frequency); - - // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. - hfrcoDiv2override = true; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; - } - - CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; - while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { - } - CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW - | CMU_IFC_DPLLLOCKFAILHIGH; - CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) - | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); - CMU->HFRCOCTRL = hfrcoCtrlVal; - CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) - | ((init->autoRecover ? 1UL : 0UL) - << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) - | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) - | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); - CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; - while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY - | CMU_IF_DPLLLOCKFAILLOW - | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { - } - - // Restore to HFRCO - if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) - && (hfrcoDiv2override == true)) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; - } - - // If HFRCO is selected as an HF clock, optimize the flash access wait-state - // configuration for this frequency and update the CMSIS core clock variable. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= init->frequency); - EFM_ASSERT(sysFreq <= SystemHfrcoFreq); - EFM_ASSERT(init->frequency == SystemHfrcoFreq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - } - - // Reduce HFLE frequency if possible. - setHfLeConfig(SystemHFClockGet()); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Update voltage scaling. - EMU_VScaleEM01ByClock(0, true); -#endif - - if (lockStatus == CMU_IF_DPLLRDY) { - return true; - } - return false; -} -#endif // CMU_OSCENCMD_DPLLEN - -/**************************************************************************//** - * @brief - * CMU low frequency register synchronization freeze control. - * - * @details - * Some CMU registers require synchronization into the low-frequency (LF) - * domain. The freeze feature allows for several such registers to be - * modified before passing them to the LF domain simultaneously (which - * takes place when the freeze mode is disabled). - * - * Another use case for this feature is using an API (such - * as the CMU API) for modifying several bit fields consecutively in the - * same register. If freeze mode is enabled during this sequence, stalling - * can be avoided. - * - * @note - * When enabling freeze mode, this function will wait for all current - * ongoing CMU synchronization to LF domain to complete (normally - * synchronization will not be in progress.) However, for this reason, when - * using freeze mode, modifications of registers requiring LF synchronization - * should be done within one freeze enable/disable block to avoid unnecessary - * stalling. - * - * @param[in] enable - * @li true - enable freeze, modified registers are not propagated to the - * LF domain - * @li false - disable freeze, modified registers are propagated to the LF - * domain - *****************************************************************************/ -void CMU_FreezeEnable(bool enable) -{ - if (enable) { - /* Wait for any ongoing LF synchronizations to complete. This */ - /* protects against the rare case when a user */ - /* - modifies a register requiring LF sync */ - /* - then enables freeze before LF sync completed */ - /* - then modifies the same register again */ - /* since modifying a register while it is in sync progress should be */ - /* avoided. */ - while (CMU->SYNCBUSY != 0UL) { - } - - CMU->FREEZE = CMU_FREEZE_REGFREEZE; - } else { - CMU->FREEZE = 0; - } -} - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Get HFRCO band in use. - * - * @return - * HFRCO band in use. - ******************************************************************************/ -CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) -{ - return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) - >> _CMU_HFRCOCTRL_BAND_SHIFT); -} -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Set HFRCO band and the tuning value based on the value in the calibration - * table made during production. - * - * @note - * HFCLKLE prescaler is automatically modified based on the maximum - * HFLE frequency allowed. - * - * @param[in] band - * HFRCO band to activate. - ******************************************************************************/ -void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) -{ - uint32_t tuning; - uint32_t freq; - CMU_Select_TypeDef osc; - - /* Read the tuning value from the calibration table. */ - switch (band) { - case cmuHFRCOBand_1MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) - >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; - break; - - case cmuHFRCOBand_7MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) - >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; - break; - - case cmuHFRCOBand_11MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) - >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; - break; - - case cmuHFRCOBand_14MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) - >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; - break; - - case cmuHFRCOBand_21MHz: - tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) - >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; - break; - -#if defined(_CMU_HFRCOCTRL_BAND_28MHZ) - case cmuHFRCOBand_28MHz: - tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) - >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* If HFRCO is used for the core clock, flash access WS has to be considered. */ - osc = CMU_ClockSelectGet(cmuClock_HF); - if (osc == cmuSelect_HFRCO) { - /* Configure worst case wait states for flash access before setting the divider. */ - flashWaitStateMax(); - } - - /* Set band/tuning. */ - CMU->HFRCOCTRL = (CMU->HFRCOCTRL - & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) - | (band << _CMU_HFRCOCTRL_BAND_SHIFT) - | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); - - /* If HFRCO is used for the core clock, optimize flash WS. */ - if (osc == cmuSelect_HFRCO) { - /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ - freq = SystemCoreClockGet(); - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - } - -#if defined(CMU_MAX_FREQ_HFLE) - /* Reduce HFLE frequency if possible. */ - setHfLeConfig(SystemCoreClockGet()); -#endif -} -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the HFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * HFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) -{ - switch (freq) { - /* 1, 2, and 4 MHz share the same calibration word. */ - case cmuHFRCOFreq_1M0Hz: - case cmuHFRCOFreq_2M0Hz: - case cmuHFRCOFreq_4M0Hz: - return DEVINFO->HFRCOCAL0; - - case cmuHFRCOFreq_7M0Hz: - return DEVINFO->HFRCOCAL3; - - case cmuHFRCOFreq_13M0Hz: - return DEVINFO->HFRCOCAL6; - - case cmuHFRCOFreq_16M0Hz: - return DEVINFO->HFRCOCAL7; - - case cmuHFRCOFreq_19M0Hz: - return DEVINFO->HFRCOCAL8; - - case cmuHFRCOFreq_26M0Hz: - return DEVINFO->HFRCOCAL10; - - case cmuHFRCOFreq_32M0Hz: - return DEVINFO->HFRCOCAL11; - - case cmuHFRCOFreq_38M0Hz: - return DEVINFO->HFRCOCAL12; - -#if defined(_DEVINFO_HFRCOCAL13_MASK) - case cmuHFRCOFreq_48M0Hz: - return DEVINFO->HFRCOCAL13; -#endif - -#if defined(_DEVINFO_HFRCOCAL14_MASK) - case cmuHFRCOFreq_56M0Hz: - return DEVINFO->HFRCOCAL14; -#endif - -#if defined(_DEVINFO_HFRCOCAL15_MASK) - case cmuHFRCOFreq_64M0Hz: - return DEVINFO->HFRCOCAL15; -#endif - -#if defined(_DEVINFO_HFRCOCAL16_MASK) - case cmuHFRCOFreq_72M0Hz: - return DEVINFO->HFRCOCAL16; -#endif - - default: /* cmuHFRCOFreq_UserDefined */ - return 0; - } -} - -/***************************************************************************//** - * @brief - * Get the current HFRCO frequency. - * - * @return - * HFRCO frequency. - ******************************************************************************/ -CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) -{ - return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Set the HFRCO calibration for the selected target frequency. - * - * @note - * HFCLKLE prescaler is automatically modified based on the maximum - * HFLE frequency allowed. - * - * @param[in] setFreq - * HFRCO frequency to set. - ******************************************************************************/ -void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - uint32_t sysFreq; - uint32_t prevFreq; - - /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ - freqCal = CMU_HFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - prevFreq = SystemHfrcoFreq; - SystemHfrcoFreq = (uint32_t)setFreq; - - /* Set maximum wait-states and set safe HFPER clock-tree prescalers while - changing the core clock. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - flashWaitStateMax(); - hfperClkSafePrescaler(); - } - - /* Wait for any previous sync to complete and set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { - } - - /* Check for valid calibration data. */ - EFM_ASSERT(freqCal != UINT_MAX); - - /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ - switch (setFreq) { - case cmuHFRCOFreq_1M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV4; - break; - - case cmuHFRCOFreq_2M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV2; - break; - - case cmuHFRCOFreq_4M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV1; - break; - - default: - break; - } - - /* Update HFLE configuration before updating HFRCO. - Use the new set frequency. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ - setHfLeConfig((uint32_t)setFreq); - } - - if ((uint32_t)setFreq > prevFreq) { -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* When increasing frequency voltage scale must be done before the change. */ - EMU_VScaleEM01ByClock((uint32_t)setFreq, true); -#endif - } - - CMU->HFRCOCTRL = freqCal; - - /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration - for this frequency and update the CMSIS core clock variable. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= (uint32_t)setFreq); - EFM_ASSERT(sysFreq <= SystemHfrcoFreq); - EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - } - - /* Reduce HFLE frequency if possible. */ - setHfLeConfig(SystemHFClockGet()); - - if ((uint32_t)setFreq <= prevFreq) { -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* When decreasing frequency voltage scale must be done after the change */ - EMU_VScaleEM01ByClock(0, true); -#endif - } - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* Set optimized HFPER clock-tree prescalers. */ - hfperClkOptimizedPrescaler(); - } -} -#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) -/***************************************************************************//** - * @brief - * Get the HFRCO startup delay. - * - * @details - * See the reference manual for more details. - * - * @return - * The startup delay in use. - ******************************************************************************/ -uint32_t CMU_HFRCOStartupDelayGet(void) -{ - return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) - >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; -} - -/***************************************************************************//** - * @brief - * Set the HFRCO startup delay. - * - * @details - * See the reference manual for more details. - * - * @param[in] delay - * The startup delay to set (<= 31). - ******************************************************************************/ -void CMU_HFRCOStartupDelaySet(uint32_t delay) -{ - EFM_ASSERT(delay <= 31); - - delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; - CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) - | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); -} -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the USHFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * USHFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) -{ - switch (freq) { - case cmuUSHFRCOFreq_16M0Hz: - return DEVINFO->USHFRCOCAL7; - - case cmuUSHFRCOFreq_32M0Hz: - return DEVINFO->USHFRCOCAL11; - - case cmuUSHFRCOFreq_48M0Hz: - return DEVINFO->USHFRCOCAL13; - - case cmuUSHFRCOFreq_50M0Hz: - return DEVINFO->USHFRCOCAL14; - - default: /* cmuUSHFRCOFreq_UserDefined */ - return 0; - } -} - -/***************************************************************************//** - * @brief - * Get the current USHFRCO frequency. - * - * @return - * HFRCO frequency. - ******************************************************************************/ -CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) -{ - return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Get USHFRCO frequency. - * - * @return - * USHFRCO frequency. - ******************************************************************************/ -uint32_t CMU_USHFRCOFreqGet(void) -{ - return ushfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Set the USHFRCO calibration for the selected target frequency. - * - * @param[in] setFreq - * USHFRCO frequency to set. - ******************************************************************************/ -void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - - /* Get DEVINFO calibration values. */ - freqCal = CMU_USHFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); - ushfrcoFreq = (uint32_t)setFreq; - - /* Wait for any previous sync to complete and set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; - - CMU->USHFRCOCTRL = freqCal; -} -#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) -/***************************************************************************//** - * @brief - * Enable or disable HFXO autostart. - * - * @param[in] userSel - * Additional user specified enable bit. - * - * @param[in] enEM0EM1Start - * If true, HFXO is automatically started upon entering EM0/EM1 entry from - * EM2/EM3. HFXO selection has to be handled by the user. - * If false, HFXO is not started automatically when entering EM0/EM1. - * - * @param[in] enEM0EM1StartSel - * If true, HFXO is automatically started and immediately selected upon - * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of - * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically - * modified if userSel is specified. - * If false, HFXO is not started or selected automatically when entering - * EM0/EM1. - ******************************************************************************/ -void CMU_HFXOAutostartEnable(uint32_t userSel, - bool enEM0EM1Start, - bool enEM0EM1StartSel) -{ - uint32_t hfxoFreq; - uint32_t hfxoCtrl; - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) - if (enEM0EM1StartSel) { - /* Voltage scaling is not compatible with HFXO auto start and select. */ - EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); - } -#endif - - /* Mask supported enable bits. */ -#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) - userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; -#else - userSel = 0; -#endif - - hfxoFreq = SystemHFXOClockGet(); -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Update voltage scaling. - EMU_VScaleEM01ByClock(hfxoFreq, true); -#endif - /* Set wait-states for HFXO if automatic start and select is configured. */ - if ((userSel > 0UL) || enEM0EM1StartSel) { - CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT); - setHfLeConfig(hfxoFreq / CMU_ClockDivGet(cmuClock_HF)); - } - - if (enEM0EM1Start || enEM0EM1StartSel) { - /* Enable the HFXO once in order to finish first time calibrations. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - } - - /* Since call to CMU_OscillatorEnable() can change the CMU->HFXOCTRL register, - * it's important to read the CMU->HFXOCTRL register after the call to CMU_OscillatorEnable(). */ - hfxoCtrl = CMU->HFXOCTRL & ~(userSel - | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK - | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); - - hfxoCtrl |= userSel - | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) - | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); - - /* Update HFXOCTRL after wait-states are updated as HF may automatically switch - to HFXO when automatic select is enabled . */ - CMU->HFXOCTRL = hfxoCtrl; -} -#endif - -/**************************************************************************//** - * @brief - * Set HFXO control registers. - * - * @note - * HFXO configuration should be obtained from a configuration tool, - * app note, or crystal data sheet. This function disables the HFXO to - * ensure a valid state before update. - * - * @param[in] hfxoInit - * HFXO setup parameters. - *****************************************************************************/ -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) -{ - /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); - - /* HFXO must be disabled before reconfiguration. */ - CMU_OscillatorEnable(cmuOsc_HFXO, false, true); - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) - uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; - - switch (hfxoInit->mode) { - case cmuOscMode_Crystal: - tmp = CMU_HFXOCTRL_MODE_XTAL; - break; - case cmuOscMode_External: - tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; - break; - case cmuOscMode_AcCoupled: - tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; - break; - default: - EFM_ASSERT(false); /* Unsupported configuration */ - break; - } - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; - -#if defined(CMU_HFXOCTRL_HFXOX2EN) - /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ - tmp = 0; - if (SystemHFXOClockGet() <= 25000000) { - tmp |= CMU_HFXOCTRL_HFXOX2EN; - } - - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; -#endif - - /* Set tuning for startup and steady state. */ - CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup - << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) - | (hfxoInit->xoCoreBiasTrimStartup - << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK - | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) - | (hfxoInit->ctuneSteadyState - << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) - | (hfxoInit->xoCoreBiasTrimSteadyState - << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); - - /* Set timeouts */ - CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect - << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) - | (hfxoInit->timeoutSteady - << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) - | (hfxoInit->timeoutStartup - << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); - -#elif defined(_CMU_HFXOCTRL_MASK) - uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; - - /* AC coupled external clock not supported. */ - EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); - if (hfxoInit->mode == cmuOscMode_External) { - tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; - } - - /* Apply control settings. */ - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) - | tmp; - BUS_RegBitWrite(&CMU->HFXOCTRL, - _CMU_HFXOCTRL_LOWPOWER_SHIFT, - (unsigned)hfxoInit->lowPowerMode); - - /* Set XTAL tuning parameters. */ - -#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) - /* Set peak detection threshold. */ - CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) - | (hfxoInit->thresholdPeakDetect - << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); -#endif - /* Set tuning for startup and steady state. */ - CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup - << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) - | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup - << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK - | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) - | ((uint32_t)hfxoInit->ctuneSteadyState - << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) - | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState - << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) - | ((uint32_t)hfxoInit->regIshSteadyState - << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) - | getRegIshUpperVal(hfxoInit->regIshSteadyState); - - /* Set timeouts. */ - CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect - << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutSteady - << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutStartup - << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutShuntOptimization - << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); - -#else - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK - | _CMU_CTRL_HFXOBOOST_MASK - | _CMU_CTRL_HFXOMODE_MASK - | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) - | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) - | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) - | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) - | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); -#endif -} - -/***************************************************************************//** - * @brief - * Get the LCD framerate divisor (FDIV) setting. - * - * @return - * The LCD framerate divisor. - ******************************************************************************/ -uint32_t CMU_LCDClkFDIVGet(void) -{ -#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) - return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; -#else - return 0; -#endif /* defined(LCD_PRESENT) */ -} - -/***************************************************************************//** - * @brief - * Set the LCD framerate divisor (FDIV) setting. - * - * @note - * The FDIV field (CMU LCDCTRL register) should only be modified while the - * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function - * will NOT modify FDIV if the LCD module clock is enabled. See - * @ref CMU_ClockEnable() for disabling/enabling LCD clock. - * - * @param[in] div - * The FDIV setting to use. - ******************************************************************************/ -void CMU_LCDClkFDIVSet(uint32_t div) -{ -#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) - EFM_ASSERT(div <= cmuClkDiv_128); - - /* Do not allow modification if LCD clock enabled. */ - if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { - return; - } - - div <<= _CMU_LCDCTRL_FDIV_SHIFT; - div &= _CMU_LCDCTRL_FDIV_MASK; - CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; -#else - (void)div; /* Unused parameter. */ -#endif /* defined(LCD_PRESENT) */ -} - -/**************************************************************************//** - * @brief - * Set LFXO control registers. - * - * @note - * LFXO configuration should be obtained from a configuration tool, - * app note, or crystal data sheet. This function disables the LFXO when - * necessary to ensure a valid state before update. - * - * @param[in] lfxoInit - * LFXO setup parameters. - *****************************************************************************/ -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) -{ - /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); - -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK - | _CMU_LFXOCTRL_GAIN_MASK - | _CMU_LFXOCTRL_TIMEOUT_MASK - | _CMU_LFXOCTRL_MODE_MASK)) - | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) - | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) - | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) - | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); - - /* If LFXO already contains the correct configuration then there is no need - * to stop the oscillator and apply new settings. The LFXO can be running out - * of reset, in which case there is no need to disable it unless necessary. */ - if (reg != CMU->LFXOCTRL) { - CMU_OscillatorEnable(cmuOsc_LFXO, false, true); - CMU->LFXOCTRL = reg; - } -#elif defined(_SILICON_LABS_32B_SERIES_0) - /* LFXO must be disabled before reconfiguration. */ - CMU_OscillatorEnable(cmuOsc_LFXO, false, true); - - bool cmuBoost = (lfxoInit->boost & 0x2); - BUS_RegMaskedWrite(&CMU->CTRL, - _CMU_CTRL_LFXOTIMEOUT_MASK - | _CMU_CTRL_LFXOBOOST_MASK - | _CMU_CTRL_LFXOMODE_MASK, - ((uint32_t)lfxoInit->timeout - << _CMU_CTRL_LFXOTIMEOUT_SHIFT) - | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) - | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); -#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) - /* EFM32GG has a "reduce startup boost" field in the EMU */ - bool emuReduce = (lfxoInit->boost & 0x1); - BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); -#endif -#endif -} - -/**************************************************************************//** - * @brief - * Sets LFXO's crystal precision, in PPM. - * - * @note - * LFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_LFXOPrecisionSet(uint16_t precision) -{ - lfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets LFXO's crystal precision, in PPM. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_LFXOPrecisionGet(void) -{ - return lfxo_precision; -} - -/**************************************************************************//** - * @brief - * Sets HFXO's crystal precision, in PPM. - * - * @note - * HFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_HFXOPrecisionSet(uint16_t precision) -{ - hfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets HFXO's crystal precision, in PPM. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_HFXOPrecisionGet(void) -{ - return hfxo_precision; -} - -/***************************************************************************//** - * @brief - * Enable/disable oscillator. - * - * @note - * WARNING: When this function is called to disable either cmuOsc_LFXO or - * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register - * are reset to the reset value. In other words, if external clock sources are selected - * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared - * and needs to be reconfigured if needed later. - * - * @param[in] osc - * The oscillator to enable/disable. - * - * @param[in] enable - * @li true - enable specified oscillator. - * @li false - disable specified oscillator. - * - * @param[in] wait - * Only used if @p enable is true. - * @li true - wait for oscillator start-up time to timeout before returning. - * @li false - do not wait for oscillator start-up time to timeout before - * returning. - ******************************************************************************/ -void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) -{ - uint32_t rdyBitPos; -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t ensBitPos; -#endif -#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) - uint32_t hfxoTrimStatus; -#endif - - uint32_t enBit; - uint32_t disBit; - - switch (osc) { - case cmuOsc_HFRCO: - enBit = CMU_OSCENCMD_HFRCOEN; - disBit = CMU_OSCENCMD_HFRCODIS; - rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_HFXO: - enBit = CMU_OSCENCMD_HFXOEN; - disBit = CMU_OSCENCMD_HFXODIS; - rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; -#endif - break; - - case cmuOsc_AUXHFRCO: - enBit = CMU_OSCENCMD_AUXHFRCOEN; - disBit = CMU_OSCENCMD_AUXHFRCODIS; - rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_LFRCO: - enBit = CMU_OSCENCMD_LFRCOEN; - disBit = CMU_OSCENCMD_LFRCODIS; - rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_LFXO: - enBit = CMU_OSCENCMD_LFXOEN; - disBit = CMU_OSCENCMD_LFXODIS; - rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; -#endif - break; - -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - case cmuOsc_USHFRCO: - enBit = CMU_OSCENCMD_USHFRCOEN; - disBit = CMU_OSCENCMD_USHFRCODIS; - rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; -#endif - break; -#endif - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - if (!deviceHasPlfrco()) { - while (true) { // PLFRCO is not available - EFM_ASSERT(false); - } - } - enBit = CMU_OSCENCMD_PLFRCOEN; - disBit = CMU_OSCENCMD_PLFRCODIS; - rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; - ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; - break; -#endif - - default: - /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled - and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily - intended for information: the ULFRCO is always on. */ - EFM_ASSERT(false); - return; - } - - if (enable) { - #if defined(_CMU_HFXOCTRL_MASK) - bool firstHfxoEnable = false; - - /* Enabling the HFXO for the first time requires special handling. - * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the - * first time the HFXO is enabled. */ - if (osc == cmuOsc_HFXO) { - if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { - /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); -#endif - - firstHfxoEnable = true; - /* The first time that an external clock is enabled, switch to CMD mode to make sure that - * only SCO and not PDA tuning is performed. */ - if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { - setHfxoTuningMode(HFXO_TUNING_MODE_CMD); - } - } - } -#endif - CMU->OSCENCMD = enBit; - -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Always wait for ENS to go high. */ - while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { - } -#endif - - /* Wait for the clock to become ready after enable. */ - if (wait) { - while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { - } -#if defined(_SILICON_LABS_32B_SERIES_1) - if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { - if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) - == CMU_HFXOCTRL_MODE_DIGEXTCLK) { -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - /* External clock mode should only do shunt current optimization. */ - (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, - cmuHFXOTuningMode_ShuntCommand, - true); -#endif - } else { - /* Wait for the peak detection and shunt current optimization - to complete. */ - (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); - } - - /* Disable the HFXO again to apply the trims. Apply trim from - HFXOTRIMSTATUS when disabled. */ - hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); - CMU_OscillatorEnable(cmuOsc_HFXO, false, true); - CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); - - /* Restart in CMD mode. */ - CMU->OSCENCMD = enBit; - while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { - } - } -#endif - } - } else { - CMU->OSCENCMD = disBit; - -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Always wait for ENS to go low. */ - while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { - } - - if (wait) { - /* Wait for RDY to go low as well. */ - while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { - } - } -#endif - } -} - -/***************************************************************************//** - * @brief - * Get the oscillator frequency tuning setting. - * - * @param[in] osc - * An oscillator to get tuning value for, one of the following: - * @li #cmuOsc_LFRCO - * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK - * @li #cmuOsc_USHFRCO - * @endif - * @li #cmuOsc_AUXHFRCO - * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined - * - * @return - * The oscillator frequency tuning setting in use. - ******************************************************************************/ -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) -{ - uint32_t ret; - - switch (osc) { - case cmuOsc_LFRCO: - ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) - >> _CMU_LFRCOCTRL_TUNING_SHIFT; - break; - - case cmuOsc_HFRCO: - ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) - >> _CMU_HFRCOCTRL_TUNING_SHIFT; - break; - -#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) - case cmuOsc_USHFRCO: - ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) - >> _CMU_USHFRCOCTRL_TUNING_SHIFT; - break; -#endif - - case cmuOsc_AUXHFRCO: - ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) - >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; - break; - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - case cmuOsc_HFXO: - ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK -#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) - | _CMU_HFXOTRIMSTATUS_REGISH_MASK -#endif - ); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - case cmuOsc_LFXO: - ret = (CMU->LFXOCTRL & _CMU_LFXOCTRL_TUNING_MASK) >> _CMU_LFXOCTRL_TUNING_SHIFT; - break; -#endif - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the oscillator frequency tuning control. - * - * @note - * Oscillator tuning is done during production and the tuning value is - * automatically loaded after reset. Changing the tuning value from the - * calibrated value is for more advanced use. Certain oscillators also have - * build-in tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_LFRCO - * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK - * @li #cmuOsc_USHFRCO - * @endif - * @li #cmuOsc_AUXHFRCO - * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. - * - * @param[in] val - * The oscillator frequency tuning setting to use. - ******************************************************************************/ -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - uint8_t ctune = 0; -#endif - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - uint32_t regIshUpper; -#endif - - switch (osc) { - case cmuOsc_LFRCO: - EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK - >> _CMU_LFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) - | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); - break; - - case cmuOsc_HFRCO: - EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK - >> _CMU_HFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) - | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); - break; - -#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) - case cmuOsc_USHFRCO: - EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK - >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { - } -#endif - CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) - | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); - break; -#endif - - case cmuOsc_AUXHFRCO: - EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK - >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) - | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); - break; - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - case cmuOsc_HFXO: - - /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ - EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); - - /* Switch to command mode. Automatic SCO and PDA calibration is not done - at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) - | val - | regIshUpper; -#else - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) - | val; -#endif - - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - case cmuOsc_LFXO: - EFM_ASSERT(val <= (_CMU_LFXOCTRL_TUNING_MASK >> _CMU_LFXOCTRL_TUNING_SHIFT)); - // Max internal capacitance tuning value is 0x4F (20 pF) - ctune = (uint8_t) SL_MIN(0x4FU, val); - - // Wait for the CMU_LFXOCTRL is ready for update - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_LFXOBSY_SHIFT) != 0UL) { - } - CMU->LFXOCTRL = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK)) - | ((uint32_t)ctune << _CMU_LFXOCTRL_TUNING_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -/***************************************************************************//** - * @brief - * Wait for the oscillator tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_HFXO - * - * @param[in] mode - * Tuning optimization mode. - * - * @return - * Returns false on invalid parameters or oscillator error status. - ******************************************************************************/ -bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode) -{ - uint32_t waitFlags; - EFM_ASSERT(osc == cmuOsc_HFXO); - - /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ - (void)osc; - - if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { - waitFlags = HFXO_TUNING_READY_FLAGS; - } else { - /* Set wait flags for each command and wait. */ - switch (mode) { -#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) - case cmuHFXOTuningMode_ShuntCommand: - waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; - break; -#endif - case cmuHFXOTuningMode_Auto: - waitFlags = HFXO_TUNING_READY_FLAGS; - break; - -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - case cmuHFXOTuningMode_PeakShuntCommand: - waitFlags = HFXO_TUNING_READY_FLAGS; - break; -#endif - - default: - waitFlags = _CMU_STATUS_MASK; - EFM_ASSERT(false); - break; - } - } - while ((CMU->STATUS & waitFlags) != waitFlags) { - } - -#if defined(CMU_IF_HFXOPEAKDETERR) - /* Check error flags. */ - if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { - return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; - } -#endif - return true; -} - -/***************************************************************************//** - * @brief - * Start and optionally wait for the oscillator tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_HFXO - * - * @param[in] mode - * Tuning optimization mode. - * - * @param[in] wait - * Wait for tuning optimization to complete. - * true - wait for tuning optimization to complete. - * false - return without waiting. - * - * @return - * Returns false on invalid parameters or oscillator error status. - ******************************************************************************/ -bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode, - bool wait) -{ - switch (osc) { - case cmuOsc_HFXO: - if ((unsigned)mode != 0U) { -#if defined(CMU_IF_HFXOPEAKDETERR) - /* Clear the error flag before command write. */ - CMU->IFC = CMU_IFC_HFXOPEAKDETERR; -#endif - CMU->CMD = (uint32_t)mode; - } - if (wait) { - return CMU_OscillatorTuningWait(osc, mode); - } - break; - - default: - EFM_ASSERT(false); - break; - } - return true; -} -#endif - -/**************************************************************************//** - * @brief - * Determine if the currently selected PCNTn clock used is external or LFBCLK. - * - * @param[in] instance - * PCNT instance number to get currently selected clock source for. - * - * @return - * @li true - selected clock is external clock. - * @li false - selected clock is LFBCLK. - *****************************************************************************/ -bool CMU_PCNTClockExternalGet(unsigned int instance) -{ - uint32_t setting; - - switch (instance) { -#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) - case 0: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; - break; - -#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) - case 1: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; - break; - -#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) - case 2: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; - break; -#endif -#endif -#endif - - default: - setting = 0; - break; - } - return setting > 0UL ? true : false; -} - -/**************************************************************************//** - * @brief - * Select the PCNTn clock. - * - * @param[in] instance - * PCNT instance number to set selected clock source for. - * - * @param[in] external - * Set to true to select the external clock, false to select LFBCLK. - *****************************************************************************/ -void CMU_PCNTClockExternalSet(unsigned int instance, bool external) -{ -#if defined(PCNT_PRESENT) - uint32_t setting = 0; - - EFM_ASSERT(instance < (unsigned)PCNT_COUNT); - - if (external) { - setting = 1; - } - - BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); - -#else - (void)instance; /* An unused parameter */ - (void)external; /* An unused parameter */ -#endif -} - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/***************************************************************************//** - * @brief - * Get USHFRCO band in use. - * - * @return - * USHFRCO band in use. - ******************************************************************************/ -CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) -{ - return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF - & _CMU_USHFRCOCONF_BAND_MASK) - >> _CMU_USHFRCOCONF_BAND_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get USHFRCO frequency. - * - * @return - * USHFRCO frequency. - ******************************************************************************/ -uint32_t CMU_USHFRCOFreqGet(void) -{ - return ushfrcoFreq; -} -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/***************************************************************************//** - * @brief - * Set the USHFRCO band to use. - * - * @param[in] band - * USHFRCO band to activate. - ******************************************************************************/ -void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) -{ - uint32_t tuning; - uint32_t fineTuning; - - /* Cannot switch band if USHFRCO is already selected as HF clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCODIV2); - - /* Read tuning value from calibration table. */ - switch (band) { - case cmuUSHFRCOBand_24MHz: - tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; - fineTuning = (DEVINFO->USHFRCOCAL0 - & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; - ushfrcoFreq = 24000000UL; - break; - - case cmuUSHFRCOBand_48MHz: - tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; - fineTuning = (DEVINFO->USHFRCOCAL0 - & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; - /* Enable the clock divider before switching the band from 24 to 48 MHz */ - BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); - ushfrcoFreq = 48000000UL; - break; - - default: - EFM_ASSERT(false); - return; - } - - /* Set band and tuning. */ - CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) - | (band << _CMU_USHFRCOCONF_BAND_SHIFT); - CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) - | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); - CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) - | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); - - /* Disable the clock divider after switching the band from 48 to 24 MHz. */ - if (band == cmuUSHFRCOBand_24MHz) { - BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); - } -} -#endif - -#endif // defined(_SILICON_LABS_32B_SERIES_2) -/** @} (end addtogroup cmu) */ -#endif /* defined(CMU_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_cmu.h" +#if defined(CMU_PRESENT) + +#include +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "em_emu.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +#include "em_msc.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +/***************************************************************************//** + * @addtogroup cmu CMU - Clock Management Unit + * @brief Clock management unit (CMU) Peripheral API + * @details + * This module contains functions for the CMU peripheral of Silicon Labs 32-bit + * MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock + * multiplexers, pre-scalers, calibration modules and wait-states. + * @{ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +// Maximum allowed core frequency vs. wait-states on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL + +// Maximum allowed core frequency vs. wait-states on sram accesses. +#define CMU_MAX_SRAM_FREQ_0WS 50000000UL +#define CMU_MAX_SRAM_FREQ_1WS 80000000UL + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// Maximum allowed core frequency vs. wait-states and vscale on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 20000000UL +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define CMU_MAX_FREQ_0WS_1V1 25000000UL +#define CMU_MAX_FREQ_1WS_1V1 50000000UL +#define CMU_MAX_FREQ_2WS_1V1 75000000UL +#else + #warning "MCU flash wait states not supported" +#endif + +// Maximum allowed PCLK frequency. +#define CMU_MAX_PCLK_FREQ 50000000UL + +// Maximum allowed RHCLK frequency. +#define CMU_MAX_RHCLK_FREQ 40000000UL + +#if defined(EMU_VSCALE_EM01_PRESENT) +// This macro is intended to be used as input to CMU_UpdateWaitStates() +#define VSCALE_DEFAULT (2 - (int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +#if defined(PLFRCO_PRESENT) +// Typical frequency for HFXO as recommanded in the datasheets. +// see AN0016: Oscillator Design Considerations +// +// Recommended for most wireless applications +// to meet transceiver electrical specifications +#define XTAL_38M4 38400000UL +// Recommended for implementing Z-Wave devices +#define XTAL_39M0 39000000UL +// High Precision mode calibration Counts for 38.4MHz +#define LFRCO_NOMCAL_XTAL_38M4 _LFRCO_NOMCAL_RESETVALUE +#define LFRCO_NOMCALINV_XTAL_38M4 _LFRCO_NOMCALINV_RESETVALUE +// High Precision mode calibration Counts for 39.0MHz. +#define LFRCO_NOMCAL_XTAL_39M0 0x0005CFBBUL +#define LFRCO_NOMCALINV_XTAL_39M0 0x0000581AUL +#endif + +#define PLL0_USB_OUTPUT_FREQ 48000000UL + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Table of HFRCOCAL values and their associated min/max frequencies and +// optional band enumerator. +static const struct hfrcoCalTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCODPLLFreq_TypeDef band; +} hfrcoCalTable[] = +{ + // minFreq maxFreq HFRCOCAL value band + { 900000UL, 1080000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, + { 1080000UL, 1300000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1300000UL, 1530000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1530000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1800000UL, 2150000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, + { 2150000UL, 2600000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 2600000UL, 3050000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3050000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3600000UL, 4300000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, + { 4300000UL, 5200000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 5200000UL, 6100000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 6100000UL, 7800000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, + { 7800000UL, 9800000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 9800000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, + { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, + { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, + { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz }, +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + { 80000000UL, 100000000UL, 0xCCF19F00UL, cmuHFRCODPLLFreq_100M0Hz } +#endif +}; + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +#define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ + / sizeof(struct hfrcoCalTableElement)) + +// CTUNE delta needed for some series 2 chips. This delta is added to the tuning capacitance on XO. +// The inter-chip buffered crystal sharing feature added from the EFR32xG23 creates an imbalance +// between XI and XO capacitance load internally on the chip. The delta allows to compensate for +// the difference. +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +static int8_t ctuneDelta = 40; // Recommendation from analog team to counter the internal chip imbalance. +#else +static int8_t ctuneDelta = 0; +#endif +#endif + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUART_PRESENT) +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUSART_PRESENT) +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(LCD_PRESENT) +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(VDAC_PRESENT) +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if (VDAC_COUNT > 1) +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(PCNT_PRESENT) +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(LESENSE_PRESENT) +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +static void rhclkPrescMax(void); +static void rhclkPrescOptimize(void); +#endif +#endif + +#if defined(HFRCOEM23_PRESENT) +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale); +static void flashWaitStateControl(uint32_t coreFreq, int vscale); +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); +#if defined(IADC_PRESENT) +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void pclkDivMax(void); +static void pclkDivOptimize(void); +#if defined(RTCC_PRESENT) +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#elif defined(SYSRTC_PRESENT) +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void waitStateMax(void); +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if WDOG_COUNT > 1 +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(USB_PRESENT) +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +/** @endcond */ + +// The following code is common for all SERIES_2 configurations. + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Calibrate an oscillator. + * + * @details + * Run a calibration of a selectable reference clock againt HCLK. Please + * refer to the reference manual, CMU chapter, for further details. + * + * @note + * This function will not return until calibration measurement is completed. + * + * @param[in] cycles + * The number of HCLK cycles to run calibration. Increasing this number + * increases precision, but the calibration will take more time. + * + * @param[in] ref + * The reference clock used to compare against HCLK. + * + * @return + * The number of ticks the selected reference clock ticked while running + * cycles ticks of the HCLK clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) +{ + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALTOP_CALTOP_MASK + >> _CMU_CALTOP_CALTOP_SHIFT)); +#endif + + CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); + CMU_CalibrateStart(); + return CMU_CalibrateCountGet(); +} + +/***************************************************************************//** + * @brief + * Configure clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * Refer to the reference manual, CMU chapter, for further details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required, and + * the resulting calibration value can be read with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run calibration. Increasing this + * number increases precision, but the calibration will take more time. + * + * @param[in] downSel + * The clock which will be counted down downCycles cycles. + * + * @param[in] upSel + * The reference clock, the number of cycles generated by this clock will + * be counted and added up, the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel) +{ + // Keep untouched configuration settings + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK + | _CMU_CALCTRL_DOWNSEL_MASK +#if defined(_CMU_CALCTRL_CALTOP_MASK) + | _CMU_CALCTRL_CALTOP_MASK +#endif + ); + + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); + calCtrl |= downCycles; +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALTOP_CALTOP_MASK >> _CMU_CALTOP_CALTOP_SHIFT)); + CMU->CALTOP = downCycles << _CMU_CALTOP_CALTOP_SHIFT; +#endif + + // Set down counting clock source selector + switch (downSel) { + case cmuSelect_HCLK: + calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; + break; + + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + // Set up counting clock source selector + switch (upSel) { + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_UPSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} + +/***************************************************************************//** + * @brief + * Get calibration count value. + * + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off, and reading the value will be just needed, where the normal + * case would be that this function call has been triggered by the CALRDY + * interrupt flag. + * + * @return + * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + // Wait until calibration completes, UNLESS continuous calibration mode is on + if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { + // Wait until calibration completes + while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { + } + } + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Direct a clock to a GPIO pin. + * + * @param[in] clkNo + * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2. + * + * @param[in] sel + * Select clock source. + * + * @param[in] clkDiv + * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is + * selected as clock source. + * + * @param[in] port + * GPIO port. + * + * @param[in] pin + * GPIO pin. + * + * @note + * Refer to the reference manual and the datasheet for details on which + * GPIO port/pins that are available. + ******************************************************************************/ +void CMU_ClkOutPinConfig(uint32_t clkNo, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkDiv, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + uint32_t tmp = 0U, mask; + + EFM_ASSERT(pin <= 15U); + + switch (clkNo) { + case 0: + case 1: + EFM_ASSERT((port == 2U) || (port == 3U)); + break; + case 2: + EFM_ASSERT((port == 0U) || (port == 1U)); + break; + default: + EFM_ASSERT(false); + break; + } + + switch (sel) { + case cmuSelect_Disabled: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; + break; + + case cmuSelect_HFRCODPLL: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; + break; +#endif + + case cmuSelect_EXPCLK: + EFM_ASSERT((clkDiv > 0U) && (clkDiv <= 32U)); + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; + break; + + case cmuSelect_LFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; + break; + + case cmuSelect_HCLK: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; + break; + + default: + EFM_ASSERT(false); + break; + } + + mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK + << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); + tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; + + if (sel == cmuSelect_EXPCLK) { + tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; + } + + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; + + if (sel == cmuSelect_Disabled) { + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); + } else { + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + if (clkNo == 0U) { + GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + } else if (clkNo == 1) { + GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + } else { + GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + } + GPIO_PinModeSet(port, pin, gpioModePushPull, 0); + } +} + +/***************************************************************************//** + * @brief + * Get clock divisor. + * + * @param[in] clock + * Clock point to get divisor for. Notice that not all clock points + * have a divisors. Please refer to CMU overview in reference manual. + * + * @return + * The current clock point divisor. 1 is returned + * if @p clock specifies a clock point without divisor. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (ret == 2U ) { // Unused value, illegal prescaler + EFM_ASSERT(false); + } +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + if (!((ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV1) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV2) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV4) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV8) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV16))) { + // Illegal prescaler + EFM_ASSERT(false); + } +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: + ret = (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_PRESC_MASK) + >> _CMU_TRACECLKCTRL_PRESC_SHIFT; + if (!((ret == _CMU_TRACECLKCTRL_PRESC_DIV1) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV2) +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV3) +#endif + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV4))) { + // Illegal prescaler + EFM_ASSERT(false); + } + break; +#endif + + case cmuClock_EXPCLK: + ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) + >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + break; + + case cmuClock_PCLK: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; + break; + + default: + break; + } + return 1U + ret; +} + +/***************************************************************************//** + * @brief + * Set clock divisor. + * + * @param[in] clock + * Clock point to set divisor for. Notice that not all clock points + * have a divisor, please refer to CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use. + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U) + || (div == 8U) || (div == 16U)); +#endif + + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Set new divisor + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); + + // Update CMSIS core clock variable and set optimum wait-states + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 3U) || (div == 4U)); +#else + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#endif + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_TRACECLKCTRL_PRESC_SHIFT); +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + + case cmuClock_EXPCLK: + EFM_ASSERT((div >= 1U) && (div <= 32U)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); + break; + + case cmuClock_PCLK: + EFM_ASSERT((div == 1U) || (div == 2U)); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); + break; + + default: + EFM_ASSERT(false); + break; + } +} + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * Module clocks sre disabled after reset. If a module clock is disabled, the + * registers of that module are not accessible and accessing such registers + * will hardfault the Cortex core. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg = NULL; + uint32_t bit; + + /* Identify the enable register. */ + if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_NO_EN_REG) { + EFM_ASSERT(false); /* No enable for this clock. */ + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN0_EN_REG) { + reg = &CMU->CLKEN0; + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN1_EN_REG) { + reg = &CMU->CLKEN1; +#if defined(_CMU_CLKEN2_MASK) + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN2_EN_REG) { + reg = &CMU->CLKEN2; +#endif + } else { +#if defined(CRYPTOACC_PRESENT) + reg = &CMU->CRYPTOACCCLKCTRL; +#else + // No register to enable clock. Possible hard fault exception. + EFM_ASSERT(false); +#endif + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_CORE: + case cmuClock_HCLK: + case cmuClock_LDMA: + case cmuClock_GPCRC: + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_I2C1: + case cmuClock_PRS: + case cmuClock_PCLK: + case cmuClock_GPIO: + case cmuClock_USART0: + case cmuClock_USART1: + case cmuClock_USART2: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_I2C0: + case cmuClock_LSPCLK: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: + em4GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; + + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; + + case cmuClock_DPLLREFCLK: + dpllRefClkGet(&ret, NULL); + break; + + case cmuClock_TRACECLK: + traceClkGet(&ret, NULL); + break; + + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + uint32_t freq = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_HCLK: + case cmuClock_CORE: + case cmuClock_ICACHE: + case cmuClock_MSC: + case cmuClock_LDMA: + case cmuClock_SMU: +#if defined(RADIOAES_PRESENT) + case cmuClock_RADIOAES: +#endif +#if defined(CRYPTOACC_PRESENT) + case cmuClock_CRYPTOACC: + case cmuClock_CRYPTOAES: + case cmuClock_CRYPTOPK: +#endif +#if defined(MVP_PRESENT) + case cmuClock_MVP: +#endif + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_PCLK: +#if defined(USART_PRESENT) + case cmuClock_USART0: +#if USART_COUNT > 1 + case cmuClock_USART1: +#endif +#endif + case cmuClock_I2C1: + case cmuClock_PRS: + case cmuClock_GPIO: + case cmuClock_GPCRC: + case cmuClock_LDMAXBAR: + case cmuClock_SYSCFG: + case cmuClock_DCDC: + case cmuClock_BURAM: + case cmuClock_DPLL0: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_LSPCLK: + case cmuClock_I2C0: + case cmuClock_AMUXCP0: +#if defined(ACMP_PRESENT) + case cmuClock_ACMP0: +#if ACMP_COUNT > 1 + case cmuClock_ACMP1: +#endif +#endif + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + + case cmuClock_TRACECLK: + traceClkGet(&freq, NULL); + ret = freq / CMU_ClockDivGet(cmuClock_TRACECLK); + break; + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; +#if defined(PDM_PRESENT) + case cmuClock_PDM: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(&ret, NULL); + break; +#endif +#if defined(EUART_PRESENT) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(&ret, NULL); + break; +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(&ret, NULL); + break; +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(&ret, NULL); + break; +#endif +#endif + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; +#if WDOG_COUNT > 1 + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; +#endif +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; +#endif +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(&ret, NULL); + break; +#endif +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(&ret, NULL); + break; +#endif +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(&ret, NULL); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(&ret, NULL); + break; +#endif +#endif /* VDAC_PRESENT */ +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(&ret, NULL); + break; +#endif +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(&ret, NULL); + break; +#endif + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(&ret, NULL); + break; + +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(&ret, NULL); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/***************************************************************************//** + * @brief + * Get currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. + * + * @return + * Reference clock used for clocking selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Error; + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = cmuSelect_HFRCODPLL; + break; + + case CMU_SYSCLKCTRL_CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = cmuSelect_CLKIN0; + break; + + case CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = cmuSelect_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: + ret = cmuSelect_RFFPLLSYS; + break; +#endif + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + sysTickClkGet(NULL, &ret); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + dpllRefClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + case cmuClock_TRACECLK: + traceClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(NULL, &ret); + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(NULL, &ret); + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(NULL, &ret); + break; +#endif + #endif + +// ----------------------------------------------------------------------------- +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(NULL, &ret); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(NULL, &ret); + break; +#endif +#endif +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void) +{ +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif +} + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(void) +{ + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif +} + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void) +{ +#if defined(_CMU_CLKEN0_MASK) && defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +} + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_setSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief + * Select reference clock/oscillator used for a clock branch. + * + * @param[in] clock + * Clock branch to select reference clock for. + * + * @param[in] ref + * Reference selected for clocking, please refer to reference manual for + * for details on which reference is available for a specific clock branch. + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t tmp = 0U; + bool oscForceEnStatus = false; +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + bool syscfgClkIsOff = false; +#endif +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; +#if defined(_CMU_CLKEN0_MASK) +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif +#endif + // Make sure HFXO is enabled. + oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_FSRCO: + tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case cmuSelect_RFFPLLSYS: + tmp = CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Switch to selected oscillator. + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; + + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + + if (oscForceEnStatus == false) { + switch (ref) { + case cmuSelect_HFXO: + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + break; + + default: + break; + } + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL + & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + case cmuSelect_LFXO: + case cmuSelect_LFRCO: + case cmuSelect_ULFRCO: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_setSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_setSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); + break; + case cmuSelect_HCLK: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_clearSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); + break; + default: + EFM_ASSERT(false); + break; + } + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL + & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + case cmuClock_EM4GRPACLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL + & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; + break; + + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL + & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + switch (ref) { + case cmuSelect_HFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_LFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_Disabled: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL + & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + switch (ref) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + case cmuSelect_HCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + case cmuSelect_SYSCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_SYSCLK; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | tmp; +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_Disabled: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + switch (ref) { +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case cmuSelect_EM01GRPCCLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case cmuSelect_FSRCO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case cmuSelect_LFXO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; + break; +#endif + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case cmuSelect_Disabled: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif + case cmuSelect_HFRCOEM23: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; + break; + + case cmuSelect_FSRCO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif + +// ----------------------------------------------------------------------------- +#if defined (RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined (SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_LCDCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_LCDCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_LCDCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif /* VDAC_PRESENT */ +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_PCNTEXTCLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + switch (ref) { + case cmuSelect_USBPLL0: + tmp = CMU_USB0CLKCTRL_CLKSEL_USBPLL0; + break; + case cmuSelect_LFXO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFXO; + break; + case cmuSelect_LFRCO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(PLFRCO_PRESENT) +#if defined(LFRCO_CFG_HIGHPRECEN) + case cmuSelect_LFRCO: + case cmuSelect_PLFRCO: + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { + precision = 500; + } else { + precision = 0xFFFF; + } + break; +#endif +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCODPLL: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Get HFRCODPLL band in use. + * + * @return + * HFRCODPLL band in use. + ******************************************************************************/ +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) +{ + return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCODPLL band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCODPLL frequency band to activate. + ******************************************************************************/ +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + uint32_t freqCal, sysFreq; +#if defined(EMU_VSCALE_EM01_PRESENT) + uint32_t prevFreq; +#endif + + // Get calibration data from DEVINFO + freqCal = HFRCODPLLDevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + // Make sure DPLL is disabled before configuring + if (DPLL0->EN == DPLL_EN_EN) { + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + } + + // Set max wait-states and PCLK divisor while changing core clock + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + } + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCODPLLFreq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCODPLLFreq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + prevFreq = SystemHFRCODPLLClockGet(); + + if ((uint32_t)freq > prevFreq) { + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)freq, true); + } +#endif + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = freqCal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (freqCal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(freq); + } else { + // revert back to previous value + HFRCO0->CAL = hfrcoCalCurrent; +#if defined(EMU_VSCALE_EM01_PRESENT) + freq = (CMU_HFRCODPLLFreq_TypeDef)prevFreq; +#endif + } + + // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access + // wait-state configuration and PCLK divisor for this frequency. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)freq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((uint32_t)freq <= prevFreq) { + /* When decreasing frequency voltage scale must be done after the change. */ + EMU_VScaleEM01ByClock(0, true); + } +#endif +} + +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCODPLL should be switched to a lower + * frequency clock (if possible) prior to calling this function to avoid + * over-clocking. + * + * @param[in] init + * DPLL setup parameter struct. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hclkDivIncreased = false; + uint32_t hfrcoCalVal, lockStatus = 0, hclkDiv = 0, sysFreq; + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + bool hfrcoClamped = false; + bool restoreDpll; + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; + + // Make sure DPLL is disabled before configuring + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); + + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); + EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. + for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCalTable[i].minFreq) + && (init->frequency <= hfrcoCalTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCalVal = hfrcoCalTable[index].value; + + // Check if a calibrated HFRCOCAL.TUNING value is present in device DI page. + if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) + & _HFRCO_CAL_TUNING_MASK) + >> _HFRCO_CAL_TUNING_SHIFT; + hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Increase HCLK divider value (if possible) while locking DPLL to + // avoid over-clocking. + hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); + hclkDivIncreased = true; + if (hclkDiv == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } else if (hclkDiv == 2U) { + CMU_ClockDivSet(cmuClock_HCLK, 4U); + } else { + hclkDivIncreased = false; + } + } + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = hfrcoCalVal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (hfrcoCalVal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) + | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); + + /* For series 2 silicon, macro expansion is used to select clock + * sources since it results in less code size when compared to the legacy + * CMU_ClockSelectSet function. + */ + if (init->refClk == cmuSelect_HFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, HFXO); + } else if (init->refClk == cmuSelect_LFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, LFXO); + } else if (init->refClk == cmuSelect_CLKIN0) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, CLKIN0); + } + + DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) + | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) + | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); + + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(init->frequency); + } else { + hfrcoClamped = true; + HFRCO0->CAL = hfrcoCalCurrent; + } + + /* + * if HFRCO frequency range has been clamped, re-enable DPLL only if it was + * previously enabled + */ + if (!hfrcoClamped || restoreDpll) { + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + + // Lock DPLL + DPLL0->EN_SET = DPLL_EN_EN; + while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK + | DPLL_IF_LOCKFAILLOW + | DPLL_IF_LOCKFAILHIGH))) == 0UL) { + } + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + if (hclkDivIncreased) { + // Restore original HCLK divider + CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); + } + + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); + EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); + + // Set optimal wait-states and PCLK divisor + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + + if (hfrcoClamped) { + return false; + } else if (lockStatus == DPLL_IF_LOCK) { + return true; + } + return false; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the USB PLL control registers. + * + * @note + * The HFXO reference frequency must be updated if crystal value is + * different from default value. + * + * @param[in] pllInit + * USB PLL parameters + ******************************************************************************/ +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit) +{ + CMU->CLKEN1_SET = CMU_CLKEN1_USB; + + USBPLL0->LOCK = USBPLL_LOCK_LOCKKEY_UNLOCK; + + // Stop the PLL for configuration purposes + USBPLL0->CTRL_SET = USBPLL_CTRL_DISONDEMAND; + USBPLL0->CTRL_CLR = USBPLL_CTRL_FORCEEN; + + while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; + + if (pllInit->hfxoRefFreq == cmuHFXORefFreq_39M0Hz) { + // Set DCO in low frequency mode for 39 MHz crystal. + USBPLL0->DCOCTRL_SET = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } else { + USBPLL0->DCOCTRL_CLR = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + USBPLL0->CTRL = (USBPLL0->CTRL & ~(_USBPLL_CTRL_SHUNTREGLPEN_MASK + | _USBPLL_CTRL_DIVR_MASK + | _USBPLL_CTRL_DIVX_MASK + | _USBPLL_CTRL_DIVN_MASK + | _USBPLL_CTRL_DISONDEMAND_MASK + | _USBPLL_CTRL_FORCEEN_MASK)) + | pllInit->hfxoRefFreq + | pllInit->shuntRegEn << _USBPLL_CTRL_SHUNTREGLPEN_SHIFT + | pllInit->disOnDemand << _USBPLL_CTRL_DISONDEMAND_SHIFT + | pllInit->forceEn << _USBPLL_CTRL_FORCEEN_SHIFT; + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + if (pllInit->forceEn) { + CMU_WaitUSBPLLLock(); + } + + if (pllInit->regLock) { + USBPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the RFFPLL control registers. + * + * @param[in] pllInit + * RFF PLL parameters + ******************************************************************************/ +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit) +{ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_RFFPLLSYS); + EFM_ASSERT(pllInit->dividerY >= 8 && pllInit->dividerY <= 31); + EFM_ASSERT(pllInit->dividerX >= 4 && pllInit->dividerX <= 15); + EFM_ASSERT(pllInit->dividerN >= 32 && pllInit->dividerN <= 127); + + CMU->CLKEN1_SET = CMU_CLKEN1_RFFPLL0; + + RFFPLL0->LOCK = RFFPLL_LOCK_LOCKKEY_UNLOCK; + + RFFPLL0->CTRL = (RFFPLL0->CTRL & ~(_RFFPLL_CTRL_DISONDEMAND_MASK | _RFFPLL_CTRL_FORCEEN_MASK)) + | (pllInit->disOnDemand << _RFFPLL_CTRL_DISONDEMAND_SHIFT) + | (pllInit->forceEn << _RFFPLL_CTRL_FORCEEN_SHIFT); + + RFFPLL0->RFFPLLCTRL1 = (RFFPLL0->RFFPLLCTRL1 & ~(_RFFPLL_RFFPLLCTRL1_DIVY_MASK | _RFFPLL_RFFPLLCTRL1_DIVX_MASK | _RFFPLL_RFFPLLCTRL1_DIVN_MASK)) + | (pllInit->dividerY << _RFFPLL_RFFPLLCTRL1_DIVY_SHIFT) + | (pllInit->dividerX << _RFFPLL_RFFPLLCTRL1_DIVX_SHIFT) + | (pllInit->dividerN << _RFFPLL_RFFPLLCTRL1_DIVN_SHIFT); + + // Update CMSIS RFFPLL frequency. + SystemRFFPLLClockSet(pllInit->frequency); + + if (pllInit->forceEn) { + CMU_WaitRFFPLLLock(); + } + + if (pllInit->regLock) { + RFFPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +/**************************************************************************//** + * @brief + * Initialize all HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function returns early if HFXO is + * already selected as SYSCLK. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + // Check all initialization structure members which may overflow target + // bitfield. + EFM_ASSERT(hfxoInit->timeoutCbLsb + <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK + >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteady + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXoStartup + <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXiStartup + <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->coreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->imCoreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + EFM_ASSERT(hfxoInit->coreDegenAna + <= (_HFXO_XTALCTRL_COREDGENANA_MASK + >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneFixAna + <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK + >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); + EFM_ASSERT(hfxoInit->mode + <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); + + // Return early if HFXO is already selected as SYSCLK. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { + return; + } + +#if defined(CMU_CLKEN0_HFXO0) + // Enable HFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable HFXO. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND +#if defined(_HFXO_CTRL_DISONDEMANDBUFOUT_MASK) + | HFXO_CTRL_DISONDEMANDBUFOUT +#endif + ; + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { + } +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + +#if defined(_DEVINFO_HFXOCAL_VTRTRIMANA_MASK) && defined(_HFXO_BUFOUTTRIM_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_VTRTRIMANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, + _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK, + tmp << _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT); + } +#endif + +#if defined(_DEVINFO_HFXOCAL_SHUNTBIASANA_MASK) && defined(_HFXO_LOWPWRCTRL_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, + _HFXO_LOWPWRCTRL_SHUNTBIASANA_MASK, + tmp << _HFXO_LOWPWRCTRL_SHUNTBIASANA_SHIFT); + } +#endif + + // Configure HFXO as specified in initialization struct, use + // timeoutSteadyFirstLock as TIMEOUTSTEADY value. + HFXO0->XTALCFG = + (uint32_t)((hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) + | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) + | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) + | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) + | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) + | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) + | (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) + | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) + | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) + | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + // See [PM-2871] for details. + BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), + 0x00000C00U, + 0x00000002U << 10); +#endif + + HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK + | _HFXO_CFG_ENXIDCBIASANA_MASK + | _HFXO_CFG_MODE_MASK)) + | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) + ? 0 : HFXO_CFG_SQBUFSCHTRGANA) + | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) + | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); + + if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { + // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared. + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | HFXO_CTRL_FORCEEN; + + // Wait for HFXO lock and core bias algorithm to complete. +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS + | HFXO_STATUS_FSMLOCK)) { + } +#else + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS)) { + } +#endif + // Set DISONDEMAND to be able to enter new values for use on subsequent locks. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD = HFXO_CMD_MANUALOVERRIDE; +#endif +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Set new TIMEOUTSTEADY value for use on subsequent locks. + HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) + | (hfxoInit->timeoutSteady + << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); + + // Skip core bias algorithm on subsequent locks. + HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; + + if (hfxoInit->disOnDemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + + if (hfxoInit->forceEn == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + } + } else { + // Lock HFXO in EXTERNAL SINE mode. + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + //See [PM-3665] for details. + if (hfxoInit->mode == cmuHfxoOscMode_ExternalSinePkDet) { + HFXO0->XTALCFG = 0; + HFXO0->XTALCTRL = 0; + + const uint32_t PKDETTHSTARTUP_PARAMETER_1 = 2UL; + BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), + 0x0000F000U | 0x00000F00U, + (PKDETTHSTARTUP_PARAMETER_1 << 12) | (PKDETTHSTARTUP_PARAMETER_1 << 8)); + } +#endif + + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); + } + + if (hfxoInit->regLock) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +#if defined(HFXO0_BUFOUT) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) leader control registers. + * Configure the bufout request input GPIO as a clock request signal + * to add the crystal sharing follower chip as a source of clock request. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @param[in] bufoutInit + * Bufout setup parameters. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // Configure Bufout request GPIO. + GPIO_PinModeSet(port, pin, gpioModeInput, 0U); + GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT + | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; + + BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, + _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK + | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, + bufoutInit->minimalStartupDelay << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT + | bufoutInit->timeoutStartup << _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) follower control registers. + * Configure the clock request signal to a specified GPIO to automatically + * request the high frequency crystal oscillator sine wave clock. + * This function must be used in conjunction with CMU_HFXOInit() configured + * with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @note + * This function can be emulated on XG21/XG22 chips by controlling the clock + * request GPIO to ask the crystal sharing leader clock when needed. + * + * @param[in] prsStatusSelectOutput + * Selected HFXO PRS signal output. + * + * @param[in] prsAsyncCh + * PRS producer asynchronous signal channel. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(prsAsyncCh < PRS_ASYNC_CH_NUM); + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + uint32_t mask = 0U, prsSignal = 0U, value = 0U; + + switch (prsStatusSelectOutput) { + case PRS_Status_select_0: + mask = _HFXO_CTRL_PRSSTATUSSEL0_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS; + break; + + case PRS_Status_select_1: +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Power Manager module requires the HFXO PRS Producer output 1 for its usage. + EFM_ASSERT(false); +#else + mask = _HFXO_CTRL_PRSSTATUSSEL1_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL1_ENS << _HFXO_CTRL_PRSSTATUSSEL1_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1; +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } + + value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT + | prsSignal << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + + mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK + | _PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK + | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; + + BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); + + GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); + + (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[prsAsyncCh] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT + | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; + GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + prsAsyncCh); +} +#endif + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning capacitance. + * + * @param[in] ctune + * The desired tuning capacitance value. Each step corresponds to + * approximately 80fF. Min value is 0. Max value is 255. + * + * @return + * SL_STATUS_OK if initialization parameter is valid. + * SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid. + * + * @note + * While the oscillator is running in steady operation state, it may be + * desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA + * fields in the HFXO_XTALCTRL register. When tuning, care should be taken to + * make small changes to the CTUNE registers. Ideally, change the CTUNE + * registers by one LSB at a time and alternate between the XI and XO + * registers. Sufficient wait time for settling, on the order of + * TIMEOUTSTEADY, should pass before new frequency measurement is taken. + *****************************************************************************/ +sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Make sure the given CTUNE value is within the allowable range + if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + int32_t ctuneXoana = ctune + CMU_HFXOCTuneDeltaGet(); + if (ctuneXoana < 0) { + ctuneXoana = 0; + } else if (ctuneXoana > (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT)) { + ctuneXoana = (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); // Max value + } + + HFXO0->XTALCTRL = ((HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXOANA_MASK | _HFXO_XTALCTRL_CTUNEXIANA_MASK)) + | ((uint32_t)ctuneXoana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | ((ctune << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) & _HFXO_XTALCTRL_CTUNEXIANA_MASK)); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning capacitance. + * + * @return + * The HFXO crystal tuning capacitance. + * + * @note + This function only returns the CTUNE XI value. The XO value can be + different and can be found using the delta (difference between XI and XO). + See @ref CMU_HFXOCTuneDeltaGet to retrieve the delta value. + *****************************************************************************/ +uint32_t CMU_HFXOCTuneGet(void) +{ + uint32_t ctune = 0; + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) + >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return ctune; +} + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning delta. + * + * @param[in] delta + * Chip dependent crystal capacitor bank delta between HFXO XI and XO. + * + * @note + * The delta between XI and XO is applicable for the series 2 EFR32xG2x + * devices only. + *****************************************************************************/ +void CMU_HFXOCTuneDeltaSet(int32_t delta) +{ + ctuneDelta = (int8_t)delta; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning delta. + * + * @return + * Chip dependent crystal capacitor bank tuning delta. + *****************************************************************************/ +int32_t CMU_HFXOCTuneDeltaGet(void) +{ + return (int32_t)ctuneDelta; +} + +/**************************************************************************//** + * @brief + * Recalibrate the HFXO's Core Bias Current. + * + * @note + * Care should be taken when using this function as it can cause disturbance + * on the HFXO frequency while the optimization is underway. It's recommended + * to only use this function when HFXO isn't being used. It's also a blocking + * function that can be time consuming. + *****************************************************************************/ +void CMU_HFXOCoreBiasCurrentCalibrate(void) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // These two bits need to be set to allow writing the registers + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) { + // Wait for crystal to startup + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) + != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { + // Making sure HFXO is in steady state + } + + // Start core bias optimization + HFXO0->CMD_SET = HFXO_CMD_COREBIASOPT; + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == HFXO_STATUS_COREBIASOPTRDY) { + // Wait for core bias optimization to start + } + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias optimization to finish + } + + // Force COREBIASANA bitfields modification +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias current value to be written in COREBIASANA bitfields + } + + BUS_RegMaskedWrite(&HFXO0->CTRL, (_HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK), hfxoCtrlBkup); +} + +/**************************************************************************//** + * @brief + * Initialize LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function disables the LFXO to ensure + * a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + EFM_ASSERT(lfxoInit->timeout + <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); + EFM_ASSERT(lfxoInit->mode + <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); + EFM_ASSERT(lfxoInit->gain + <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); + EFM_ASSERT(lfxoInit->capTune + <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + + // Max internal capacitance tuning value is 0x4F (20 pF) + uint8_t ctune = (uint8_t) SL_MIN(0x4FU, lfxoInit->capTune); + +#if defined(CMU_CLKEN0_LFXO) + // Enable LFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + + // Unlock register interface + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable LFXO + LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; + LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; + while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { + } + + // Configure LFXO as specified + LFXO->CAL = ((uint32_t)lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + LFXO->CFG = (uint32_t)((lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) + | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) + | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) + | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT)); + + LFXO->CTRL = (uint32_t)((lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) + | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) + | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) + | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT)); + + if (lfxoInit->regLock) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +#if defined(PLFRCO_PRESENT) +/**************************************************************************//** + * @brief + * Configure the LFRCO precision. + * + * @details + * When enabling high precision mode on the LFRCO the hardware will tune + * the oscillator automatically using the HFXO as a reference. + * + * @note + * Refer to the reference manual and the datasheet for details about + * NOMCAL and NOMCALINV calibration count values. + * + * @param[in] precision + * LFRCO precision, this can be either high or default. + *****************************************************************************/ +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision) +{ + uint32_t ref = 0; + uint32_t nomcal = 0; + uint32_t nomcalinv = 0; + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + LFRCO->CTRL = LFRCO_CTRL_DISONDEMAND; // Force disable + while ((LFRCO->STATUS & LFRCO_STATUS_ENS) != 0U) { + // Wait for LFRCO to stop + } + + if (precision == cmuPrecisionHigh) { + ref = SystemHFXOClockGet(); + // Use precomputed value for HFXO typical frequencies + if (ref == XTAL_38M4) { + nomcal = LFRCO_NOMCAL_XTAL_38M4; + nomcalinv = LFRCO_NOMCALINV_XTAL_38M4; + } else if (ref == XTAL_39M0) { + nomcal = LFRCO_NOMCAL_XTAL_39M0; + nomcalinv = LFRCO_NOMCALINV_XTAL_39M0; + } else { + // Compute calibration count, based on HFXO frequency + nomcal = (5 * ref) >> 9; + nomcalinv = ((1UL << 31) / 5) << 2; + nomcalinv /= (ref >> 9); + } + + LFRCO->NOMCAL = nomcal; + LFRCO->NOMCALINV = nomcalinv; + + LFRCO->CFG = LFRCO_CFG_HIGHPRECEN; + } else { + LFRCO->CFG = 0; + } + LFRCO->CTRL = _LFRCO_CTRL_RESETVALUE; +} +#endif + +/***************************************************************************//** + * @brief + * Get oscillator frequency tuning setting. + * + * @param[in] osc + * Oscillator to get tuning value for. + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret = 0U; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + ret = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK) >> _HFXO_XTALCTRL_COREBIASANA_SHIFT; + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + ret = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production, and the tuning value is + * automatically loaded after a reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * Oscillator to set tuning value for. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ + bool disondemand = false; + bool lfxo_lock_status = false; + uint8_t ctune = 0; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK + >> _LFRCO_CAL_FREQTRIM_SHIFT)); + val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; + while (LFRCO->SYNCBUSY != 0U) { + } + LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) + | (val << _LFRCO_CAL_FREQTRIM_SHIFT); + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + EFM_ASSERT(val <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); + // Make sure HFXO is disable + EFM_ASSERT((HFXO0->STATUS & HFXO_STATUS_ENS) == 0); + + // Set DISONDEMAND if not already set and wait for FSMLOCK to be clear so that + // software can write to register + disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) >> _HFXO_CTRL_DISONDEMAND_SHIFT; + if (disondemand == false) { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Update Core Bias Ana setting and enable Optimization skip + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) + | (val << _HFXO_XTALCTRL_COREBIASANA_SHIFT) + | HFXO_XTALCTRL_SKIPCOREBIASOPT; + // Clear back DISONDEMAND if needed + if (disondemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + lfxo_lock_status = (LFXO->STATUS & _LFXO_STATUS_LOCK_MASK) >> _LFXO_STATUS_LOCK_SHIFT; + // Unlock register interface if register is locked before + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + } + + EFM_ASSERT(val <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for CALBSY bit to clear before writing the tuning value to CAL register + while (((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) >> _LFXO_SYNCBUSY_CAL_SHIFT) != 0U) { + } + LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + // Lock register interface again + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure wait state settings necessary to switch to a given core clock + * frequency at a certain voltage scale level. + * + * @details + * This function will set up the necessary flash wait states. Updating the + * wait state configuration must be done before increasing the clock + * frequency and it must be done after decreasing the clock frequency. + * Updating the wait state configuration must be done before core voltage is + * decreased and it must be done after a core voltage is increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 1, higher number is lower voltage. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + if (vscale > 0) { + flashWaitStateControl(freq, VSCALE_EM01_LOW_POWER); + } else { + flashWaitStateControl(freq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select EM23GRPACLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ + (void)instance; +#if defined(PCNT_PRESENT) + if (external) { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + } else { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + } +#else + (void)external; +#endif +} + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get HFRCOEM23 band in use. + * + * @return + * HFRCOEM23 band in use. + ******************************************************************************/ +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) +{ + return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCOEM23 band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCOEM23 frequency band to activate. + ******************************************************************************/ +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t freqCal; + + // Get calibration data from DEVINFO + freqCal = HFRCOEM23DevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); +#if defined(CMU_CLKEN0_HFRCOEM23) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; +#endif + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCOEM23Freq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCOEM23Freq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + + // Activate new band selection + HFRCOEM23->CAL = freqCal; +} +#endif // defined(HFRCOEM23_PRESENT) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPBCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + switch (CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(EUART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + switch (CMU->EUART0CLKCTRL & _CMU_EUART0CLKCTRL_CLKSEL_MASK) { + case CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(freq, sel); + break; + + case CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(freq, sel); + break; + + default: + if (freq != NULL) { + *freq = 0U; + } + if (sel != NULL) { + *sel = cmuSelect_Error; + } + EFM_ASSERT(false); + break; + } +} +#endif + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUSART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EUSART0CLKCTRL & _CMU_EUSART0CLKCTRL_CLKSEL_MASK) { +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK: + em01GrpcClkGet(&f, NULL); + s = cmuSelect_EM01GRPCCLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case CMU_EUSART0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +/**************************************************************************//** +* @brief +* Get selected oscillator and frequency for @ref cmuClock_EM01GRPCCLK +* clock tree. +* +* @param[out] freq +* The frequency. +* +* @param[out] sel +* The selected oscillator. +******************************************************************************/ +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + + case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + case _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_CMU_EM01GRPCCLKCTRL_MASK) +#endif // defined(EUSART_PRESENT) + +#if defined(LCD_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LCDCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LCDCLKCTRL & _CMU_LCDCLKCTRL_CLKSEL_MASK) { + case CMU_LCDCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(LCD_PRESENT) + +#if defined(VDAC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC0CLKCTRL & _CMU_VDAC0CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if (VDAC_COUNT > 1) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC1CLKCTRL & _CMU_VDAC1CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_PCNT0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->PCNT0CLKCTRL & _CMU_PCNT0CLKCTRL_CLKSEL_MASK) { + case CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0: + f = 0U; // external or PRS source so the frequency is undefined. + s = cmuSelect_PCNTEXTCLK; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(LESENSE_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LESENSEHFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LESENSEHFCLKCTRL & _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) { + case CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +/***************************************************************************//** + * @brief + * Set maximum allowed prescaler for radio clock tree (RHCLK). + ******************************************************************************/ +static void rhclkPrescMax(void) +{ + // Set largest prescaler (DIV2). + CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_RHCLKPRESC; +} + +/***************************************************************************//** + * @brief + * Set radio clock tree prescaler to achieve highest possible frequency + * and still be within spec. + ******************************************************************************/ +static void rhclkPrescOptimize(void) +{ + if (CMU_ClockFreqGet(cmuClock_SYSCLK) <= CMU_MAX_RHCLK_FREQ) { + // Set smallest prescaler (DIV1). + CMU->SYSCLKCTRL_CLR = CMU_SYSCLKCTRL_RHCLKPRESC; + } +} +#endif // ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +#endif // #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get calibrated HFRCOEM23 tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCOEM23 frequency band + ******************************************************************************/ +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCOEM23Freq_1M0Hz: + case cmuHFRCOEM23Freq_2M0Hz: + case cmuHFRCOEM23Freq_4M0Hz: + ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_13M0Hz: + ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_16M0Hz: + ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_19M0Hz: + ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_26M0Hz: + ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_32M0Hz: + ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_40M0Hz: + ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(HFRCOEM23_PRESENT) + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_TRACECLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { +#if defined(_CMU_TRACECLKCTRL_CLKSEL_HCLK) + case CMU_TRACECLKCTRL_CLKSEL_HCLK: + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + break; +#endif +#if defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) + case CMU_TRACECLKCTRL_CLKSEL_SYSCLK: + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } +#else + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; +#endif + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { + case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale) +{ + uint32_t flashWs = MSC_READCTRL_MODE_WS3; + + if (vscale == 0) { + // VScale 1.1V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V1) + else if (freq > CMU_MAX_FREQ_2WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V1) + else if (freq > CMU_MAX_FREQ_1WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V1) + else if (freq > CMU_MAX_FREQ_0WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } else if (vscale >= 1) { + // VScale 1.0V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V0) + else if (freq > CMU_MAX_FREQ_2WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V0) + else if (freq > CMU_MAX_FREQ_1WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V0) + else if (freq > CMU_MAX_FREQ_0WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } + return flashWs; +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency and vscale level. + * + * @note Current implementation sets wait states depending on frequency only. + * This assumes that applications running on Vscale enabled microcontrollers + * never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). + * Series 2 Config 1 devices does not support vscale. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 1 where 0 is the default. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + (void)vscale; + + uint32_t mode; + bool mscLocked; + +#if defined(CMU_CLKEN1_MSC) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + coreFreq *= CMU_ClockDivGet(cmuClock_CORE); +#endif + + // Make sure the MSC is unlocked + mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + // Get current flash read setting + mode = MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK; + + // Set new mode based on the core clock frequency + mode |= getWaitStatesByFrequencyAndVScale(coreFreq, vscale); + + MSC_ReadCTRLSet(mode); + + // Set sram wait states for config 1 mcu. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // Set new mode based on the core clock frequency + if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { + SYSCFG_setDmem0RamCtrlRamwsenBit(); + } else { + SYSCFG_clearDmem0RamCtrlRamwsenBit(); + } +#endif + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +/***************************************************************************//** + * @brief + * Get calibrated HFRCODPLL tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCODPLL frequency band + ******************************************************************************/ +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCODPLLFreq_1M0Hz: + case cmuHFRCODPLLFreq_2M0Hz: + case cmuHFRCODPLLFreq_4M0Hz: + ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_7M0Hz: + ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_13M0Hz: + ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_16M0Hz: + ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_19M0Hz: + ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_26M0Hz: + ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_32M0Hz: + ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_38M0Hz: + ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_48M0Hz: + ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_56M0Hz: + ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_64M0Hz: + ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_80M0Hz: + ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; + break; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + case cmuHFRCODPLLFreq_100M0Hz: + ret = DEVINFO->HFRCODPLLCAL[17].HFRCODPLLCAL; + break; +#endif + + case cmuHFRCODPLLFreq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(IADC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_IADCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { + case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_IADCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. + ******************************************************************************/ +static void pclkDivMax(void) +{ + // Set largest divisor for PCLK clock tree. + CMU_ClockDivSet(cmuClock_PCLK, 2U); +} + +/***************************************************************************//** + * @brief + * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible + * frequency and still be within spec. + ******************************************************************************/ +static void pclkDivOptimize(void) +{ + CMU_ClkDiv_TypeDef div = 2U; + + if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { + div = 1U; + } + CMU_ClockDivSet(cmuClock_PCLK, div); +} + +#if defined(RTCC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { + case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(SYSRTC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSRTCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set wait-states to values valid for maximum allowable core clock frequency. + ******************************************************************************/ +static void waitStateMax(void) +{ + flashWaitStateControl(SystemMaxCoreClockGet(), 0); +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSTICK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + } else { + em23GrpaClkGet(&f, &s); + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(USB_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_USB clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->USB0CLKCTRL & _CMU_USB0CLKCTRL_CLKSEL_MASK) { + case CMU_USB0CLKCTRL_CLKSEL_USBPLL0: + f = PLL0_USB_OUTPUT_FREQ; + s = cmuSelect_USBPLL0; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/** @endcond */ + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** The maximum allowed core frequency when using 0 wait-states on flash access. */ +#define CMU_MAX_FREQ_0WS 16000000 +/** The maximum allowed core frequency when using 1 wait-states on flash access */ +#define CMU_MAX_FREQ_1WS 32000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) +// EFR32xG1x and EFM32xG1x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) +// EFR32xG12x and EFM32xG12x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V1 21330000 +#define CMU_MAX_FREQ_1WS_1V1 32000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) +// EFR32xG13x and EFM32xG13x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) +// EFR32xG14x and EFM32xG14x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) +// EFM32GG11x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) +// EFM32TG11x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 48000000 +#define CMU_MAX_FREQ_0WS_1V0 10000000 +#define CMU_MAX_FREQ_1WS_1V0 21000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) +// EFM32GG12x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#else +#error "Max Flash wait-state frequencies are not defined for this platform." +#endif + +/** The maximum frequency for the HFLE interface. */ +#if defined(CMU_CTRL_HFLE) +/** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_WONDER_FAMILY) \ + || defined(_EZR32_WONDER_FAMILY)) +#define CMU_MAX_FREQ_HFLE 24000000UL +/** The maximum HFLE frequency for other series 0 parts with maximum core clock + higher than 32 MHz. */ +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +#define CMU_MAX_FREQ_HFLE maxFreqHfle() +#endif +#elif defined(CMU_CTRL_WSHFLE) +/** The maximum HFLE frequency for series 1 parts. */ +#define CMU_MAX_FREQ_HFLE 32000000UL +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) +#endif + +#if defined(CMU_HFXOCTRL_MODE_EXTCLK) +/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +#define VSCALE_DEFAULT ((int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; +#endif +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) +#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and + an optional band enumerator. */ +static const struct hfrcoCtrlTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCOFreq_TypeDef band; +} hfrcoCtrlTable[] = +{ + // minFreq maxFreq HFRCOCTRL value band + { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, + { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, + { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, + { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, + { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, + { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } +#else + #error "HFRCOCTRL values not set for this platform." +#endif +}; + +#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ + / sizeof(struct hfrcoCtrlTableElement)) +#endif // CMU_OSCENCMD_DPLLEN + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) +/* Devices with Voltage Scaling needs extra handling of wait states. */ +static const struct flashWsTableElement{ + uint32_t maxFreq; + uint8_t vscale; + uint8_t ws; +} flashWsTable[] = +{ +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ + { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ + { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ +#else + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ +#endif +}; + +#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ + || defined(_CMU_USHFRCOTUNE_MASK) +#ifndef EFM32_USHFRCO_STARTUP_FREQ +#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) +#endif + +static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); +#endif + +static void hfperClkSafePrescaler(void); +static void hfperClkOptimizedPrescaler(void); + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +/***************************************************************************//** + * @brief + * Return maximum allowed frequency for low energy peripherals. + ******************************************************************************/ +static uint32_t maxFreqHfle(void) +{ + uint16_t majorMinorRev; + + switch (SYSTEM_GetFamily()) { + case systemPartFamilyEfm32Leopard: + case systemPartFamilyEzr32Leopard: + /* CHIP MAJOR bit [5:0] */ + majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); + /* CHIP MINOR bit [7:4] */ + majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + + if (majorMinorRev >= 0x0204) { + return 24000000; + } else { + return 32000000; + } + + case systemPartFamilyEfm32Giant: + return 32000000; + + default: + /* Invalid device family. */ + EFM_ASSERT(false); + return 0; + } +} +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Unified definitions for the HFLE wait-state and prescaler fields. */ +#if defined(CMU_CTRL_HFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT +#elif defined(CMU_CTRL_WSHFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Set HFLE wait-states and HFCLKLE prescaler according to wanted HF clock. + * + * @param[in] hfFreq + * The HF clock frequency to use. + * This is: + * CORE clock on Series0 devices. + * HF clock on on Series1 devices. + ******************************************************************************/ +static void setHfLeConfig(uint32_t hfFreq) +{ + unsigned int hfleWs; + uint32_t hflePresc; + + /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the + fields are changed to more than 1 bit. */ + EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); + + /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is + above maxLeFreq. + - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ + + hfleWs = 1; + if (hfFreq <= CMU_MAX_FREQ_HFLE) { + hfleWs = 0; + hflePresc = 0; + } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { + hflePresc = 1; + } else { + hflePresc = 2; + } + BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); + GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) + | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); +} + +#if defined(_CMU_CTRL_HFLE_MASK) +/***************************************************************************//** + * @brief + * Get HFLE wait-state configuration. + * + * @return + * The current wait-state configuration. + ******************************************************************************/ +static uint32_t getHfLeConfig(void) +{ + uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); + return ws; +} +#endif +#endif + +/***************************************************************************//** + * @brief + * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, + * by default also as a debug clock. + * + * @return + * AUX Frequency in Hz. + ******************************************************************************/ +static uint32_t auxClkGet(void) +{ + uint32_t ret; + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) + ret = (uint32_t)auxHfrcoFreq; + +#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) + /* All series 0 families except EFM32G */ + switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { + case CMU_AUXHFRCOCTRL_BAND_1MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 1200000; + } else { + ret = 1000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_7MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 6600000; + } else { + ret = 7000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_11MHZ: + ret = 11000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_14MHZ: + ret = 14000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_21MHZ: + ret = 21000000; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case CMU_AUXHFRCOCTRL_BAND_28MHZ: + ret = 28000000; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + +#else + /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ + ret = 14000000; + +#endif + + return ret; +} + +#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ + || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) +/***************************************************************************//** + * @brief + * Get the HFSRCCLK frequency. + * + * @return + * HFSRCCLK Frequency in Hz. + ******************************************************************************/ +static uint32_t hfSrcClkGet(void) +{ + uint32_t ret; + + ret = SystemHFClockGet(); + return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} +#endif + +/***************************************************************************//** + * @brief + * Get the Debug Trace clock frequency. + * + * @return + * Debug Trace frequency in Hz. + ******************************************************************************/ +static uint32_t dbgClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get selected clock source */ + clk = CMU_ClockSelectGet(cmuClock_DBG); + + switch (clk) { + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +/***************************************************************************//** + * @brief + * Get the ADC n asynchronous clock frequency. + * + * @return + * ADC n asynchronous frequency in Hz. + ******************************************************************************/ +static uint32_t adcAsyncClkGet(uint32_t adc) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (adc) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); + break; + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case 1: + clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_Disabled: + ret = 0; + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFSRCCLK: + ret = hfSrcClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_SDIOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the SDIO reference clock frequency. + * + * @return + * SDIO reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t sdioRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_SDIOREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_QSPICTRL_MASK) +/***************************************************************************//** + * @brief + * Get the QSPI n reference clock frequency. + * + * @return + * QSPI n reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t qspiRefClkGet(uint32_t qspi) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (qspi) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); + break; + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_PDMCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the PDM reference clock frequency. + * + * @return + * PDM reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t pdmRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_PDMREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(USBR_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USB rate clock frequency. + * + * @return + * USB rate clock frequency in Hz. + ******************************************************************************/ +static uint32_t usbRateClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + clk = CMU_ClockSelectGet(cmuClock_USBR); + + switch (clk) { + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFXOX2: + ret = 2u * SystemHFXOClockGet(); + break; + + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + uint32_t mode; +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ +#endif + (void) vscale; /* vscale parameter is only used on some devices. */ + + /* Get mode and SCBTP enable. */ + mode = MSC_ReadCTRLGet() & _MSC_READCTRL_MODE_MASK; + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + /* Devices with MODE and SCBTP in the same register field. */ + switch (mode) { + case MSC_READCTRL_MODE_WS0: + case MSC_READCTRL_MODE_WS1: +#if defined(MSC_READCTRL_MODE_WS2) + case MSC_READCTRL_MODE_WS2: +#endif + scbtpEn = false; + break; + + default: /* WSxSCBTP */ + scbtpEn = true; + break; + } + + /* Set mode based on the core clock frequency and SCBTP enable. */ + if (false) { + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq > CMU_MAX_FREQ_1WS) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); + } +#endif + else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); + } else { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); + } +#else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ + + if (coreFreq <= CMU_MAX_FREQ_0WS) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS) { + mode = 1; + } +#endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ +// End defined(_SILICON_LABS_32B_SERIES_0) + +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_EMU_STATUS_VSCALE_MASK) + + /* These devices have specific requirements on the supported flash wait state + * depending on the frequency and voltage scale level. */ + uint32_t i; + for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { + if ((flashWsTable[i].vscale == (uint8_t)vscale) + && (coreFreq <= flashWsTable[i].maxFreq)) { + break; // Found a matching entry. + } + } + + if (i == FLASH_WS_TABLE_ENTRIES) { + mode = 3; // Worst case flash wait state for unsupported cases. + EFM_ASSERT(false); + } else { + mode = flashWsTable[i].ws; + } + mode = mode << _MSC_READCTRL_MODE_SHIFT; + +#else + /* Devices where MODE and SCBTP are in separate fields and where the device + * either does not support voltage scale or where the voltage scale does + * not impact the flash wait state configuration. */ + if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { + mode = 1; + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq <= CMU_MAX_FREQ_2WS) { + mode = 2; + } +#endif +#if defined(MSC_READCTRL_MODE_WS3) + else if (coreFreq <= CMU_MAX_FREQ_3WS) { + mode = 3; + } +#endif + mode = mode << _MSC_READCTRL_MODE_SHIFT; +#endif +// End defined(_SILICON_LABS_32B_SERIES_1) + +#else +#error "Undefined 32B SERIES!" +#endif + + mode = (MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK) | mode; + MSC_ReadCTRLSet(mode); +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to the most conservative setting for + * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) + * setting. + ******************************************************************************/ +static void flashWaitStateMax(void) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(SystemMaxCoreClockGet(), 0); + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) +/***************************************************************************//** + * @brief + * Configure RAM access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure RAM wait-states. + * + * @param[in] vscale + * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void setRamWaitState(uint32_t coreFreq, int vscale) +{ + uint32_t limit = 38000000; + if (vscale == 2) { + limit = 16000000; + } + + if (coreFreq > limit) { + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } else { + BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } +} +#endif + +#if defined(_MSC_CTRL_WAITMODE_MASK) +/***************************************************************************//** + * @brief + * Configure the wait state for peripheral accesses over the bus to support + * the given bus clock frequency. + * + * @param[in] busFreq + * A peripheral bus clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * ******************************************************************************/ +static void setBusWaitState(uint32_t busFreq, int vscale) +{ + if ((busFreq > 50000000) && (vscale == 0)) { + BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } else { + BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } +} +#endif + +#if defined(PLFRCO_PRESENT) +static bool deviceHasPlfrco(void) +{ + SYSTEM_ChipRevision_TypeDef rev; + + if (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) { + // check the xG13 rev and check if it's >= Rev A3 + SYSTEM_ChipRevisionGet(&rev); + return (rev.major > 1) || (rev.minor >= 3); + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Configure various wait states to switch to a certain frequency + * and a certain voltage scale. + * + * @details + * This function will set up the necessary flash, bus, and RAM wait states. + * Updating the wait state configuration must be done before + * increasing the clock frequency and it must be done after decreasing the + * clock frequency. Updating the wait state configuration must be done before + * core voltage is decreased and it must be done after a core voltage is + * increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2, higher number is lower voltage. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(freq, vscale); +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + setRamWaitState(freq, vscale); +#endif +#if defined(_MSC_CTRL_WAITMODE_MASK) + setBusWaitState(freq, vscale); +#endif + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) +/***************************************************************************//** + * @brief + * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. + ******************************************************************************/ +static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) +{ + uint32_t regIshUpper; + const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK + >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ + regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); + regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + return regIshUpper; +} +#endif + +#if defined(_CMU_HFXOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the HFXO tuning mode. + * + * @return + * The current HFXO tuning mode from the HFXOCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t getHfxoTuningMode(void) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; +#else + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; +#endif +} + +/***************************************************************************//** + * @brief + * Set the HFXO tuning mode. + * + * @param[in] mode + * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or + * HFXO_TUNING_MODE_CMD. + ******************************************************************************/ +__STATIC_INLINE void setHfxoTuningMode(uint32_t mode) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); +#else + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get the LFnCLK frequency based on the current configuration. + * + * @param[in] lfClkBranch + * Selected LF branch. + * + * @return + * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is + * returned. + ******************************************************************************/ +static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) +{ + uint32_t sel; + uint32_t ret = 0; + + switch (lfClkBranch) { + case cmuClock_LFA: + case cmuClock_LFB: +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#endif +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); + + /* Get clock select field */ + switch (lfClkBranch) { + case cmuClock_LFA: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; +#elif defined(_CMU_LFACLKSEL_MASK) + sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + + case cmuClock_LFB: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; +#elif defined(_CMU_LFBCLKSEL_MASK) + sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#if defined(_CMU_LFCLKSEL_LFC_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; +#elif defined(_CMU_LFCCLKSEL_LFC_MASK) + sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; +#endif + +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: + sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Get the clock frequency. */ +#if defined(_CMU_LFCLKSEL_MASK) + switch (sel) { + case _CMU_LFCLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFCLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + +#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: +#if defined(CMU_MAX_FREQ_HFLE) + /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the + * frequency of CMU_HFCORECLKLEDIV2. */ + ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); +#else + ret = SystemCoreClockGet() / 2U; +#endif + break; +#endif + + case _CMU_LFCLKSEL_LFA_DISABLED: + ret = 0; +#if defined(CMU_LFCLKSEL_LFAE) + /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ + if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { + if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA + ? _CMU_LFCLKSEL_LFAE_SHIFT + : _CMU_LFCLKSEL_LFBE_SHIFT)) { + ret = SystemULFRCOClockGet(); + } + } +#endif + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif /* _CMU_LFCLKSEL_MASK */ + +#if defined(_CMU_LFACLKSEL_MASK) + switch (sel) { + case _CMU_LFACLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_ULFRCO: + ret = SystemULFRCOClockGet(); + break; + +#if defined(PLFRCO_PRESENT) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + +#if defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) + case _CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = SystemHFClockGet() + / SL_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); + break; +#endif + + case _CMU_LFACLKSEL_LFA_DISABLED: + ret = 0; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low-frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void syncReg(uint32_t mask) +{ + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { + return; + } + + /* Wait for any pending previous write operation to complete */ + /* in low-frequency domain. */ + while ((CMU->SYNCBUSY & mask) != 0UL) { + } +} + +#if defined(USBC_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USBC frequency. + * + * @return + * USBC frequency in Hz. + ******************************************************************************/ +static uint32_t usbCClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_USBC); + + switch (clk) { + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; +#endif + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + default: + /* Clock is not enabled */ + ret = 0; + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to safe values. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkSafePrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + // Assuming a maximum HFCLK of 72MHz, set prescalers to DIV4. + CMU_ClockPrescSet(cmuClock_HFPER, 3U); + CMU_ClockPrescSet(cmuClock_HFPERB, 3U); + CMU_ClockPrescSet(cmuClock_HFPERC, 3U); +#endif +} + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to give highest possible clock node + * frequency while still beeing within spec. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkOptimizedPrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + uint32_t hfClkFreq, divisor; + + hfClkFreq = SystemHFClockGet(); + + if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { + divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) + if (divisor > 0U) { + divisor--; // Convert to prescaler + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + } else { + divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + + divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + } +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get the AUXHFRCO band in use. + * + * @return + * AUXHFRCO band in use. + ******************************************************************************/ +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL + & _CMU_AUXHFRCOCTRL_BAND_MASK) + >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the AUXHFRCO band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] band + * AUXHFRCO band to activate. + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) +{ + uint32_t tuning; + + /* Read a tuning value from the calibration table. */ + switch (band) { + case cmuAUXHFRCOBand_1MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; + break; + + case cmuAUXHFRCOBand_7MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; + break; + + case cmuAUXHFRCOBand_11MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; + break; + + case cmuAUXHFRCOBand_14MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; + break; + + case cmuAUXHFRCOBand_21MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case cmuAUXHFRCOBand_28MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Set band/tuning. */ + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL + & ~(_CMU_AUXHFRCOCTRL_BAND_MASK + | _CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the AUXHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * AUXHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuAUXHFRCOFreq_1M0Hz: + case cmuAUXHFRCOFreq_2M0Hz: + case cmuAUXHFRCOFreq_4M0Hz: + return DEVINFO->AUXHFRCOCAL0; + + case cmuAUXHFRCOFreq_7M0Hz: + return DEVINFO->AUXHFRCOCAL3; + + case cmuAUXHFRCOFreq_13M0Hz: + return DEVINFO->AUXHFRCOCAL6; + + case cmuAUXHFRCOFreq_16M0Hz: + return DEVINFO->AUXHFRCOCAL7; + + case cmuAUXHFRCOFreq_19M0Hz: + return DEVINFO->AUXHFRCOCAL8; + + case cmuAUXHFRCOFreq_26M0Hz: + return DEVINFO->AUXHFRCOCAL10; + + case cmuAUXHFRCOFreq_32M0Hz: + return DEVINFO->AUXHFRCOCAL11; + + case cmuAUXHFRCOFreq_38M0Hz: + return DEVINFO->AUXHFRCOCAL12; + +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + case cmuAUXHFRCOFreq_48M0Hz: + return DEVINFO->AUXHFRCOCAL13; +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + case cmuAUXHFRCOFreq_50M0Hz: + return DEVINFO->AUXHFRCOCAL14; +#endif + + default: /* cmuAUXHFRCOFreq_UserDefined */ + return 0; + } +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Get the current AUXHFRCO frequency. + * + * @return + * AUXHFRCO frequency. + ******************************************************************************/ +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return auxHfrcoFreq; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Set AUXHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * AUXHFRCO frequency to set + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO index and set global auxHfrcoFreq. */ + freqCal = CMU_AUXHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + auxHfrcoFreq = setFreq; + + /* Wait for any previous sync to complete, then set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } + + /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuAUXHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuAUXHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuAUXHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + CMU->AUXHFRCOCTRL = freqCal; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +/***************************************************************************//** + * @brief + * Calibrate the clock. + * + * @details + * Run a calibration for HFCLK against a selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * This function will not return until the calibration measurement is completed. + * + * @param[in] HFCycles + * The number of HFCLK cycles to run the calibration. Increasing this number + * increases precision but the calibration will take more time. + * + * @param[in] reference + * The reference clock used to compare HFCLK. + * + * @return + * The number of ticks the reference clock after HFCycles ticks on the HF + * clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) +{ + EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set the reference clock source. */ + switch (reference) { + case cmuOsc_LFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + /* Set the top value. */ + CMU->CALCNT = HFCycles; + + /* Start the calibration. */ + CMU->CMD = CMU_CMD_CALSTART; + +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + + return CMU->CALCNT; +} + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +/***************************************************************************//** + * @brief + * Configure the clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required and + * the resulting calibration value can be read out with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run the calibration. Increasing this + * number increases precision but the calibration will take more time. + * + * @param[in] downSel + * The clock, which will be counted down downCycles. + * + * @param[in] upSel + * The reference clock; the number of cycles generated by this clock will + * be counted and added up and the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel) +{ + /* Keep configuration settings untouched. */ + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); + + /* 20 bits of precision to calibration count register. */ + EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set down counting clock source - down counter. */ + switch (downSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Set the top value to be counted down by the downSel clock. */ + CMU->CALCNT = downCycles; + + /* Set the reference clock source - up counter. */ + switch (upSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} +#endif + +/***************************************************************************//** + * @brief + * Get the calibration count register. + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off and only the value needs to be read. In a normal case, + * this function call is triggered by the CALRDY + * interrupt flag. + * @return + * The calibration count, the number of UPSEL clocks + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + /* Wait until calibration completes, UNLESS continuous calibration mode is */ + /* active. */ +#if defined(CMU_CALCTRL_CONT) + if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + } +#else + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Get the clock divisor/prescaler. + * + * @param[in] clock + * A clock point to get the divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference manual. + * + * @return + * The current clock point divisor/prescaler. 1 is returned + * if @p clock specifies a clock point without a divisor/prescaler. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + return 1UL + (uint32_t)CMU_ClockPrescGet(clock); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t divReg; + CMU_ClkDiv_TypeDef ret; + + /* Get divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) + >> _CMU_CTRL_HFCLKDIV_SHIFT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV + & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + + case CMU_HFCORECLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + ret = SL_Log2ToDiv(ret + 1U); + break; +#endif + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16)); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + + return ret; +#endif +} + +/***************************************************************************//** + * @brief + * Set the clock divisor/prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * Clock point to set divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use (<= cmuClkDiv_512). + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t freq; + uint32_t divReg; + + /* Get the divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); + + /* Configure worst case wait states for flash access before setting divisor. */ + flashWaitStateMax(); + + /* Set the divider. */ + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) + | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize flash access wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + /* + This divisor is usually set when changing HF clock to keep HFLE clock + within safe bounds. This code path ignore these constraints. + */ + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div) - 1U; + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + break; +#endif + + case CMU_HFCORECLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + + /* Configure worst case wait states for flash access before setting the divisor. */ + flashWaitStateMax(); + +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet() / div); +#endif + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(freq); +#endif + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (div << _CMU_LFAPRESC0_RTC_SHIFT); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(LCD_PRESENT) + case cmuClock_LCDpre: + EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | ((div - CMU_DivToLog2(cmuClkDiv_16)) + << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif /* defined(LCD_PRESENT) */ + +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif /* defined(LESENSE_PRESENT) */ + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + default: + EFM_ASSERT(false); + break; + } +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * In general, module clocking is disabled after a reset. If a module + * clock is disabled, the registers of that module are not accessible and + * reading from such registers may return undefined values. Writing to + * registers of clock-disabled modules has no effect. + * Avoid accessing module registers of a module with a disabled clock. + * + * @note + * If enabling/disabling an LF clock, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * The clock to enable/disable. Notice that not all defined clock + * points have separate enable/disable control. See the CMU overview + * in the reference manual. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg; + uint32_t bit; + uint32_t sync = 0; + + /* Identify enable register */ + switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { +#if defined(_CMU_CTRL_HFPERCLKEN_MASK) + case CMU_CTRL_EN_REG: + reg = &CMU->CTRL; + break; +#endif + +#if defined(_CMU_HFCORECLKEN0_MASK) + case CMU_HFCORECLKEN0_EN_REG: + reg = &CMU->HFCORECLKEN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + break; +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) + case CMU_HFBUSCLKEN0_EN_REG: + reg = &CMU->HFBUSCLKEN0; + break; +#endif + +#if defined(_CMU_HFPERCLKDIV_MASK) + case CMU_HFPERCLKDIV_EN_REG: + reg = &CMU->HFPERCLKDIV; + break; +#endif + + case CMU_HFPERCLKEN0_EN_REG: + reg = &CMU->HFPERCLKEN0; + break; + +#if defined(_CMU_HFPERCLKEN1_MASK) + case CMU_HFPERCLKEN1_EN_REG: + reg = &CMU->HFPERCLKEN1; + break; +#endif + + case CMU_LFACLKEN0_EN_REG: + reg = &CMU->LFACLKEN0; + sync = CMU_SYNCBUSY_LFACLKEN0; + break; + + case CMU_LFBCLKEN0_EN_REG: + reg = &CMU->LFBCLKEN0; + sync = CMU_SYNCBUSY_LFBCLKEN0; + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case CMU_LFCCLKEN0_EN_REG: + reg = &CMU->LFCCLKEN0; + sync = CMU_SYNCBUSY_LFCCLKEN0; + break; +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + case CMU_LFECLKEN0_EN_REG: + reg = &CMU->LFECLKEN0; + sync = CMU_SYNCBUSY_LFECLKEN0; + break; +#endif + +#if defined(_CMU_SDIOCTRL_MASK) + case CMU_SDIOREF_EN_REG: + reg = &CMU->SDIOCTRL; + enable = !enable; + break; +#endif + +#if defined(_CMU_QSPICTRL_MASK) + case CMU_QSPI0REF_EN_REG: + reg = &CMU->QSPICTRL; + enable = !enable; + break; +#endif +#if defined(_CMU_USBCTRL_MASK) + case CMU_USBRCLK_EN_REG: + reg = &CMU->USBCTRL; + break; +#endif +#if defined(_CMU_PDMCTRL_MASK) + case CMU_PDMREF_EN_REG: + reg = &CMU->PDMCTRL; + break; +#endif + + case CMU_PCNT_EN_REG: + reg = &CMU->PCNTCTRL; + break; + + default: /* Cannot enable/disable a clock point. */ + EFM_ASSERT(false); + return; + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* LF synchronization required. */ + if (sync > 0UL) { + syncReg(sync); + } + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the clock frequency for a clock point. + * + * @param[in] clock + * A clock point to fetch the frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret; + + switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { + case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + break; + + case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPER divider. */ +#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; +#endif +#if defined(_CMU_HFPERPRESC_PRESC_MASK) + ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT); +#endif + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERB prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERC prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#if defined(CRYPTO_PRESENT) \ + || defined(LDMA_PRESENT) \ + || defined(GPCRC_PRESENT) \ + || defined(PRS_PRESENT) \ + || defined(GPIO_PRESENT) + case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); +#if defined(_CMU_HFBUSPRESC_MASK) + ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT); +#endif + break; +#endif + + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT); + break; + + case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(AES_PRESENT) \ + || defined(DMA_PRESENT) \ + || defined(EBI_PRESENT) \ + || defined(USB_PRESENT) + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + { + ret = SystemCoreClockGet(); + } break; +#endif +#endif + + case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + break; + +#if defined(_CMU_LFACLKEN0_RTC_MASK) + case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + break; +#endif + +#if defined(_CMU_LFECLKEN0_RTCC_MASK) + case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER0_MASK) + case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER1_MASK) + case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LCD_MASK) + case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16); +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT); +#endif + break; + +#if defined(_CMU_LCDCTRL_MASK) + case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) + >> _CMU_LCDCTRL_FDIV_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_LFACLKEN0_LESENSE_MASK) + case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + break; +#endif + + case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + break; + +#if defined(_CMU_LFBCLKEN0_LEUART0_MASK) + case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_LEUART1_MASK) + case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_CSEN_MASK) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= SL_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); + break; +#endif + +#if defined(CMU_LFCCLKEN0_USB) + case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFC); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + break; +#endif + + case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = dbgClkGet(); + break; + + case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = auxClkGet(); + break; + +#if defined(USBC_CLOCK_PRESENT) + case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbCClkGet(); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(0); +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(1); +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = sdioRefClkGet(); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = qspiRefClkGet(0); + break; +#endif + +#if defined(USBR_CLOCK_PRESENT) + case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbRateClkGet(); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = pdmRefClkGet(); + break; +#endif + + case (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + ret = SystemCoreClockGet() / CMU_ClockDivGet(clock); +#elif defined(_CMU_HFPRESC_HFCLKLEPRESC_MASK) + ret = SystemHFClockGet() / CMU_ClockDivGet(clock); +#else + ret = SystemCoreClockGet() / 2; +#endif + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Get the clock prescaler. + * + * @param[in] clock + * A clock point to get the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @return + * The prescaler value of the current clock point. 0 is returned + * if @p clock specifies a clock point without a prescaler. + ******************************************************************************/ +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) +{ + uint32_t prescReg; + uint32_t ret; + + /* Get the prescaler register ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT; + break; + + case CMU_HFEXPPRESC_REG: + ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT; + break; + + case CMU_HFCLKLEPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; + ret = SL_Log2ToDiv(ret + 1U) - 1U; + break; + + case CMU_HFPERPRESC_REG: + ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT; + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT; + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT; + break; +#endif + + case CMU_HFCOREPRESC_REG: + ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT; + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCD: + case cmuClock_LCDpre: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_RTC_MASK) + case cmuClock_RTC: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret + 4U) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; +#endif + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; + break; +#endif +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Set the clock prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock point to set the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @param[in] presc + * The clock prescaler. The prescaler value is linked to the clock divider by: + * divider = 'presc' + 1. + ******************************************************************************/ +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) +{ + uint32_t freq; + uint32_t prescReg; + + /* Get the divisor reg ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + EFM_ASSERT(presc < 32U); + + /* Configure worst case wait-states for flash and HFLE, set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); + hfperClkSafePrescaler(); + + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) + | (presc << _CMU_HFPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global + variable). */ + freq = SystemCoreClockGet(); + /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree + prescalers. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + setHfLeConfig(SystemHFClockGet()); + hfperClkOptimizedPrescaler(); + break; + + case CMU_HFEXPPRESC_REG: + EFM_ASSERT(presc < 32U); + + CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) + | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); + break; + + case CMU_HFCLKLEPRESC_REG: + presc = CMU_DivToLog2(presc); + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) + | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); + break; + + case CMU_HFPERPRESC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) + | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) + | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) + | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + + case CMU_HFCOREPRESC_REG: + EFM_ASSERT(presc < 512U); + + /* Configure worst case wait-states for flash. */ + flashWaitStateMax(); + + CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) + | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global variable). + Optimize flash and HFLE wait states. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(RTC_PRESENT) + case cmuClock_RTC: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (presc << _CMU_LFAPRESC0_RTC_SHIFT); + break; +#endif + +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_MASK) +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); +#else + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) + | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + case cmuClock_LCD: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | (presc << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert the prescaler value to a DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4U; + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFEPRESC0_RTCC_MASK) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + break; +#endif + +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); + CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) + | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} +#endif + +/***************************************************************************//** + * @brief + * Get the currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO + * @li #cmuClock_LFC + * @endif @if _SILICON_LABS_32B_SERIES_1 + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT + * @li #cmuClock_USBC + * @endif + * + * @return + * The reference clock used for clocking the selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Disabled; + uint32_t selReg; + + selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selReg) { + case CMU_HFCLKSEL_REG: +#if defined(_CMU_HFCLKSTATUS_MASK) + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { + case CMU_HFCLKSTATUS_SELECTED_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: + ret = cmuSelect_HFRCODIV2; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case CMU_HFCLKSTATUS_SELECTED_CLKIN0: + ret = cmuSelect_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case CMU_HFCLKSTATUS_SELECTED_USHFRCO: + ret = cmuSelect_USHFRCO; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#else + switch (CMU->STATUS + & (CMU_STATUS_HFRCOSEL + | CMU_STATUS_HFXOSEL + | CMU_STATUS_LFRCOSEL +#if defined(CMU_STATUS_USHFRCODIV2SEL) + | CMU_STATUS_USHFRCODIV2SEL +#endif + | CMU_STATUS_LFXOSEL)) { + case CMU_STATUS_LFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_LFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + case CMU_STATUS_HFXOSEL: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_STATUS_USHFRCODIV2SEL) + case CMU_STATUS_USHFRCODIV2SEL: + ret = cmuSelect_USHFRCODIV2; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#endif + break; + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) + case CMU_LFACLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { + case CMU_LFCLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFAE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFACLKSEL_MASK) + switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { + case CMU_LFACLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFACLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFACLKSEL_LFA_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) + case CMU_LFBCLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { + case CMU_LFCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFB_HFCLKLE) + case CMU_LFCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFBE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFBCLKSEL_MASK) + switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { + case CMU_LFBCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFBCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFBCLKSEL_LFB_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + case CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { + case CMU_LFCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_LFECLKSEL_LFE_MASK) + case CMU_LFECLKSEL_REG: + switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { + case CMU_LFECLKSEL_LFE_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFECLKSEL_LFE_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFECLKSEL_LFE_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFECLKSEL_REG */ + +#if defined(_CMU_LFCCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { + case CMU_LFCCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFCCLKSEL_LFC_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFCCLKSEL_REG */ + + case CMU_DBGCLKSEL_REG: +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { + case CMU_DBGCLKSEL_DBG_HFCLK: + ret = cmuSelect_HFCLK; + break; + + case CMU_DBGCLKSEL_DBG_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + +#elif defined(_CMU_CTRL_DBGCLK_MASK) + switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { + case CMU_CTRL_DBGCLK_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_CTRL_DBGCLK_HFCLK: + ret = cmuSelect_HFCLK; + break; + } +#else + ret = cmuSelect_AUXHFRCO; +#endif + break; + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (CMU->STATUS + & (CMU_STATUS_USBCLFXOSEL +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + | CMU_STATUS_USBCHFCLKSEL +#endif +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + | CMU_STATUS_USBCUSHFRCOSEL +#endif + | CMU_STATUS_USBCLFRCOSEL)) { +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + case CMU_STATUS_USBCHFCLKSEL: + ret = cmuSelect_HFCLK; + break; +#endif + +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + case CMU_STATUS_USBCUSHFRCOSEL: + ret = cmuSelect_USHFRCO; + break; +#endif + + case CMU_STATUS_USBCLFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_USBCLFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { + case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { + case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + } + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { + case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { + case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { + case CMU_USBCTRL_USBCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXOX2: + ret = cmuSelect_HFXOX2; + break; + + case CMU_USBCTRL_USBCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFRCO: + ret = cmuSelect_LFRCO; + break; + } + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { + case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + } + break; +#endif + + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc) +{ + if (osc == (uint8_t)cmuOsc_LFXO) { + // Enable LFXO oscillator + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + // Enable LFRCO oscillator + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + } else { + EFM_ASSERT(false); + } + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = SystemHFXOClockGet(); + EMU_VScaleEM01ByClock(vScaleFrequency, false); +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + // Adjust HFXO buffer current for frequencies above 32 MHz. + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + + // Enable HFXO oscillator + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(CMU_HFCLKSEL_HF_HFXO) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + if (((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void) +{ + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void) +{ + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_CLKIN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_USHFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +/***************************************************************************//** + * @brief + * Select the reference clock/oscillator used for a clock branch. + * + * @details + * Notice that if a selected reference is not enabled prior to selecting its + * use, it will be enabled and this function will wait for the selected + * oscillator to be stable. It will however NOT be disabled if another + * reference clock is selected later. + * + * This feature is particularly important if selecting a new reference + * clock for the clock branch clocking the core. Otherwise, the system + * may halt. + * + * @note + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock branch to select reference clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB + * @if _CMU_LFCCLKEN0_MASK + * @li #cmuClock_LFC + * @endif + * @if _CMU_LFECLKEN0_MASK + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG + * @if _CMU_CMD_USBCLKSEL_MASK + * @li #cmuClock_USBC + * @endif + * @if _CMU_USBCTRL_MASK + * @li #cmuClock_USBR + * @endif + * + * @param[in] ref + * A reference selected for clocking. See the reference manual + * for details about references available for a specific clock branch. + * @li #cmuSelect_HFRCO + * @li #cmuSelect_LFRCO + * @li #cmuSelect_HFXO + * @if _CMU_HFXOCTRL_HFXOX2EN_MASK + * @li #cmuSelect_HFXOX2 + * @endif + * @li #cmuSelect_LFXO + * @li #cmuSelect_HFCLKLE + * @li #cmuSelect_AUXHFRCO + * @if _CMU_USHFRCOCTRL_MASK + * @li #cmuSelect_USHFRCO + * @endif + * @li #cmuSelect_HFCLK + * @ifnot DOXYDOC_EFM32_GECKO_FAMILY + * @li #cmuSelect_ULFRCO + * @endif + * @if CMU_OSCENCMD_PLFRCOEN + * @li #cmuSelect_PLFRCO + * @endif + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t select = (uint32_t)cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined(_SILICON_LABS_32B_SERIES_1) + volatile uint32_t *selReg = NULL; +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + uint32_t lfExtended = 0; +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + + /* Start voltage upscaling before the clock is set. */ + if (clock == cmuClock_HF) { + if (ref == cmuSelect_HFXO) { + vScaleFrequency = SystemHFXOClockGet(); + } else if ((ref == cmuSelect_HFRCO) + && ((uint32_t)CMU_HFRCOBandGet() + > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } else { + /* Use the default frequency. */ + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } +#endif + + selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selRegId) { + case CMU_HFCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFXO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFXO; +#endif + osc = cmuOsc_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFRCO; +#endif + osc = cmuOsc_LFRCO; + break; + + case cmuSelect_HFXO: +#if defined(CMU_HFCLKSEL_HF_HFXO) + select = CMU_HFCLKSEL_HF_HFXO; +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + select = CMU_CMD_HFCLKSEL_HFXO; +#endif + osc = cmuOsc_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + /* Adjust HFXO buffer current for frequencies above 32 MHz. */ + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + break; + + case cmuSelect_HFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_HFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_HFRCO; +#endif + osc = cmuOsc_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + break; + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + select = CMU_CMD_HFCLKSEL_USHFRCODIV2; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + select = CMU_HFCLKSEL_HF_HFRCODIV2; + osc = cmuOsc_HFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + select = CMU_HFCLKSEL_HF_CLKIN0; + osc = cmuOsc_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + select = CMU_HFCLKSEL_HF_USHFRCO; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO cannot be used as HFCLK. */ + EFM_ASSERT(false); + return; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + if (osc != cmuOsc_CLKIN0) { + CMU_OscillatorEnable(osc, true, true); + } +#else + CMU_OscillatorEnable(osc, true, true); +#endif + + /* Configure worst case wait-states for flash and set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Wait for voltage upscaling to complete before the clock is set. */ + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + + /* Switch to the selected oscillator. */ +#if defined(_CMU_HFCLKSEL_MASK) + CMU->HFCLKSEL = select; +#else + CMU->CMD = select; +#endif + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + +#if defined(CMU_MAX_FREQ_HFLE) + /* Update the HFLE configuration after 'select' is set. + Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + setHfLeConfig(freq); +#else + setHfLeConfig(SystemHFClockGet()); +#endif +#endif + + /* Optimize flash access wait state setting for the currently selected core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Keep EMU module informed on the source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) + case CMU_LFACLKSEL_REG: + selReg = &CMU->LFACLKSEL; + /* HFCLKCLE can't be used as LFACLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + +#if defined(_CMU_LFCCLKSEL_MASK) + case CMU_LFCCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; + /* HFCLKCLE can't be used as LFCCLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH +#endif + /* Fall through and select the clock source. */ + + case CMU_LFECLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; + /* HFCLKCLE can't be used as LFECLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + + case CMU_LFBCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFACLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: + /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ + setHfLeConfig(SystemHFClockGet()); + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; + break; + + case cmuSelect_ULFRCO: + /* ULFRCO is always on, there is no need to enable it. */ + tmp = _CMU_LFACLKSEL_LFA_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + *selReg = tmp; + break; + +#elif defined(_SILICON_LABS_32B_SERIES_0) + case CMU_LFACLKSEL_REG: + case CMU_LFBCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: +#if defined(CMU_MAX_FREQ_HFLE) + /* Set the HFLE wait-state and divider. */ + freq = SystemCoreClockGet(); + setHfLeConfig(freq); +#endif + /* Ensure HFCORE to LE clocking is enabled. */ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; + break; + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO is always enabled. */ + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + lfExtended = 1; + break; +#endif + + default: + /* An illegal clock source for LFA/LFB selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + if (selRegId == CMU_LFACLKSEL_REG) { +#if defined(_CMU_LFCLKSEL_LFAE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); +#endif + } else { +#if defined(_CMU_LFCLKSEL_LFBE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); +#endif + } + break; + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFRCO; + break; + + default: + /* An illegal clock source for LFC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) + | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) + case CMU_DBGCLKSEL_REG: + switch (ref) { +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; + break; +#endif + +#if defined(CMU_CTRL_DBGCLK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_HFCLK; + break; +#endif + + default: + /* An illegal clock source for debug selected. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: + /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { + } + break; + + case cmuSelect_LFRCO: + /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { + } + break; + +#if defined(CMU_STATUS_USBCHFCLKSEL) + case cmuSelect_HFCLK: + /* Select undivided HFCLK as a clock source for USB. */ + /* The oscillator must already be enabled to avoid a core lockup. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { + } + break; +#endif + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) + case cmuSelect_USHFRCO: + /* Select USHFRCO as a clock source for USB. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { + } + break; +#endif + + default: + /* An illegal clock source for USB. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC0ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC1ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for SDIOREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for QSPI0REF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; + break; + + case cmuSelect_HFXOX2: + /* Only allowed for HFXO frequencies up to 25 MHz. */ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); + + /* Enable HFXO X2. */ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; + break; + + default: + /* An illegal clock source for USBR selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) + | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; + break; + + default: + /* An illegal clock source for PDMREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) + | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + precision = 500; + break; +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCO: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to + * calling this function to avoid over-clocking. + * + * HFCLKLE prescaler is automatically modified before updating HFRCO + * based on the maximum HFLE frequency allowed. + * + * @param[in] init + * DPLL setup parameters. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hfrcoDiv2override = false; + uint32_t hfrcoCtrlVal, lockStatus, sysFreq; + + EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); + EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); + EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK + >> _CMU_HFRCOSS_SSINV_SHIFT)); + EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK + >> _CMU_HFRCOSS_SSAMP_SHIFT)); + +#if defined(_EMU_STATUS_VSCALE_MASK) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find the correct HFRCO band and retrieve a HFRCOCTRL value. + for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCtrlTable[i].minFreq) + && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCtrlVal = hfrcoCtrlTable[index].value; + + // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. + if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) + & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + + // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency + // of the band shifts down by 5.8%. 9 is subtracted to compensate. + if (tuning > 9UL) { + tuning -= 9UL; + } else { + tuning = 0UL; + } + + hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; + } + + // Update the CMSIS frequency SystemHfrcoFreq value. + SystemHfrcoFreq = init->frequency; + + // Set maximum wait-states while changing the core clock. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + } + + // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + setHfLeConfig(init->frequency); + + // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. + hfrcoDiv2override = true; + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; + } + + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; + while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { + } + CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW + | CMU_IFC_DPLLLOCKFAILHIGH; + CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) + | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); + CMU->HFRCOCTRL = hfrcoCtrlVal; + CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) + | ((init->autoRecover ? 1UL : 0UL) + << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) + | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); + CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; + while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY + | CMU_IF_DPLLLOCKFAILLOW + | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { + } + + // Restore to HFRCO + if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) + && (hfrcoDiv2override == true)) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + } + + // If HFRCO is selected as an HF clock, optimize the flash access wait-state + // configuration for this frequency and update the CMSIS core clock variable. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT(init->frequency == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + // Reduce HFLE frequency if possible. + setHfLeConfig(SystemHFClockGet()); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(0, true); +#endif + + if (lockStatus == CMU_IF_DPLLRDY) { + return true; + } + return false; +} +#endif // CMU_OSCENCMD_DPLLEN + +/**************************************************************************//** + * @brief + * CMU low frequency register synchronization freeze control. + * + * @details + * Some CMU registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * Another use case for this feature is using an API (such + * as the CMU API) for modifying several bit fields consecutively in the + * same register. If freeze mode is enabled during this sequence, stalling + * can be avoided. + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing CMU synchronization to LF domain to complete (normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring LF synchronization + * should be done within one freeze enable/disable block to avoid unnecessary + * stalling. + * + * @param[in] enable + * @li true - enable freeze, modified registers are not propagated to the + * LF domain + * @li false - disable freeze, modified registers are propagated to the LF + * domain + *****************************************************************************/ +void CMU_FreezeEnable(bool enable) +{ + if (enable) { + /* Wait for any ongoing LF synchronizations to complete. This */ + /* protects against the rare case when a user */ + /* - modifies a register requiring LF sync */ + /* - then enables freeze before LF sync completed */ + /* - then modifies the same register again */ + /* since modifying a register while it is in sync progress should be */ + /* avoided. */ + while (CMU->SYNCBUSY != 0UL) { + } + + CMU->FREEZE = CMU_FREEZE_REGFREEZE; + } else { + CMU->FREEZE = 0; + } +} + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get HFRCO band in use. + * + * @return + * HFRCO band in use. + ******************************************************************************/ +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) + >> _CMU_HFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set HFRCO band and the tuning value based on the value in the calibration + * table made during production. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] band + * HFRCO band to activate. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t freq; + CMU_Select_TypeDef osc; + + /* Read the tuning value from the calibration table. */ + switch (band) { + case cmuHFRCOBand_1MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) + >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; + break; + + case cmuHFRCOBand_7MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) + >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; + break; + + case cmuHFRCOBand_11MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) + >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; + break; + + case cmuHFRCOBand_14MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) + >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; + break; + + case cmuHFRCOBand_21MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) + >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_HFRCOCTRL_BAND_28MHZ) + case cmuHFRCOBand_28MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) + >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* If HFRCO is used for the core clock, flash access WS has to be considered. */ + osc = CMU_ClockSelectGet(cmuClock_HF); + if (osc == cmuSelect_HFRCO) { + /* Configure worst case wait states for flash access before setting the divider. */ + flashWaitStateMax(); + } + + /* Set band/tuning. */ + CMU->HFRCOCTRL = (CMU->HFRCOCTRL + & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) + | (band << _CMU_HFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); + + /* If HFRCO is used for the core clock, optimize flash WS. */ + if (osc == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + } + +#if defined(CMU_MAX_FREQ_HFLE) + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemCoreClockGet()); +#endif +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the HFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * HFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuHFRCOFreq_1M0Hz: + case cmuHFRCOFreq_2M0Hz: + case cmuHFRCOFreq_4M0Hz: + return DEVINFO->HFRCOCAL0; + + case cmuHFRCOFreq_7M0Hz: + return DEVINFO->HFRCOCAL3; + + case cmuHFRCOFreq_13M0Hz: + return DEVINFO->HFRCOCAL6; + + case cmuHFRCOFreq_16M0Hz: + return DEVINFO->HFRCOCAL7; + + case cmuHFRCOFreq_19M0Hz: + return DEVINFO->HFRCOCAL8; + + case cmuHFRCOFreq_26M0Hz: + return DEVINFO->HFRCOCAL10; + + case cmuHFRCOFreq_32M0Hz: + return DEVINFO->HFRCOCAL11; + + case cmuHFRCOFreq_38M0Hz: + return DEVINFO->HFRCOCAL12; + +#if defined(_DEVINFO_HFRCOCAL13_MASK) + case cmuHFRCOFreq_48M0Hz: + return DEVINFO->HFRCOCAL13; +#endif + +#if defined(_DEVINFO_HFRCOCAL14_MASK) + case cmuHFRCOFreq_56M0Hz: + return DEVINFO->HFRCOCAL14; +#endif + +#if defined(_DEVINFO_HFRCOCAL15_MASK) + case cmuHFRCOFreq_64M0Hz: + return DEVINFO->HFRCOCAL15; +#endif + +#if defined(_DEVINFO_HFRCOCAL16_MASK) + case cmuHFRCOFreq_72M0Hz: + return DEVINFO->HFRCOCAL16; +#endif + + default: /* cmuHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current HFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO calibration for the selected target frequency. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] setFreq + * HFRCO frequency to set. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + uint32_t sysFreq; + uint32_t prevFreq; + + /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ + freqCal = CMU_HFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + prevFreq = SystemHfrcoFreq; + SystemHfrcoFreq = (uint32_t)setFreq; + + /* Set maximum wait-states and set safe HFPER clock-tree prescalers while + changing the core clock. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + hfperClkSafePrescaler(); + } + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } + + /* Check for valid calibration data. */ + EFM_ASSERT(freqCal != UINT_MAX); + + /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + + /* Update HFLE configuration before updating HFRCO. + Use the new set frequency. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ + setHfLeConfig((uint32_t)setFreq); + } + + if ((uint32_t)setFreq > prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)setFreq, true); +#endif + } + + CMU->HFRCOCTRL = freqCal; + + /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration + for this frequency and update the CMSIS core clock variable. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)setFreq); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemHFClockGet()); + + if ((uint32_t)setFreq <= prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When decreasing frequency voltage scale must be done after the change */ + EMU_VScaleEM01ByClock(0, true); +#endif + } + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + } +} +#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +/***************************************************************************//** + * @brief + * Get the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @return + * The startup delay in use. + ******************************************************************************/ +uint32_t CMU_HFRCOStartupDelayGet(void) +{ + return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) + >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @param[in] delay + * The startup delay to set (<= 31). + ******************************************************************************/ +void CMU_HFRCOStartupDelaySet(uint32_t delay) +{ + EFM_ASSERT(delay <= 31); + + delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) + | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); +} +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the USHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * USHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) +{ + switch (freq) { + case cmuUSHFRCOFreq_16M0Hz: + return DEVINFO->USHFRCOCAL7; + + case cmuUSHFRCOFreq_32M0Hz: + return DEVINFO->USHFRCOCAL11; + + case cmuUSHFRCOFreq_48M0Hz: + return DEVINFO->USHFRCOCAL13; + + case cmuUSHFRCOFreq_50M0Hz: + return DEVINFO->USHFRCOCAL14; + + default: /* cmuUSHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current USHFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the USHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * USHFRCO frequency to set. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO calibration values. */ + freqCal = CMU_USHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); + ushfrcoFreq = (uint32_t)setFreq; + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; + + CMU->USHFRCOCTRL = freqCal; +} +#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +/***************************************************************************//** + * @brief + * Enable or disable HFXO autostart. + * + * @param[in] userSel + * Additional user specified enable bit. + * + * @param[in] enEM0EM1Start + * If true, HFXO is automatically started upon entering EM0/EM1 entry from + * EM2/EM3. HFXO selection has to be handled by the user. + * If false, HFXO is not started automatically when entering EM0/EM1. + * + * @param[in] enEM0EM1StartSel + * If true, HFXO is automatically started and immediately selected upon + * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of + * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically + * modified if userSel is specified. + * If false, HFXO is not started or selected automatically when entering + * EM0/EM1. + ******************************************************************************/ +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel) +{ + uint32_t hfxoFreq; + uint32_t hfxoCtrl; + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) + if (enEM0EM1StartSel) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); + } +#endif + + /* Mask supported enable bits. */ +#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) + userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; +#else + userSel = 0; +#endif + + hfxoFreq = SystemHFXOClockGet(); +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(hfxoFreq, true); +#endif + /* Set wait-states for HFXO if automatic start and select is configured. */ + if ((userSel > 0UL) || enEM0EM1StartSel) { + CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT); + setHfLeConfig(hfxoFreq / CMU_ClockDivGet(cmuClock_HF)); + } + + if (enEM0EM1Start || enEM0EM1StartSel) { + /* Enable the HFXO once in order to finish first time calibrations. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + } + + /* Since call to CMU_OscillatorEnable() can change the CMU->HFXOCTRL register, + * it's important to read the CMU->HFXOCTRL register after the call to CMU_OscillatorEnable(). */ + hfxoCtrl = CMU->HFXOCTRL & ~(userSel + | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK + | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); + + hfxoCtrl |= userSel + | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) + | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; +} +#endif + +/**************************************************************************//** + * @brief + * Set HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the HFXO to + * ensure a valid state before update. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + + /* HFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + switch (hfxoInit->mode) { + case cmuOscMode_Crystal: + tmp = CMU_HFXOCTRL_MODE_XTAL; + break; + case cmuOscMode_External: + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + break; + case cmuOscMode_AcCoupled: + tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; + break; + default: + EFM_ASSERT(false); /* Unsupported configuration */ + break; + } + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; + +#if defined(CMU_HFXOCTRL_HFXOX2EN) + /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ + tmp = 0; + if (SystemHFXOClockGet() <= 25000000) { + tmp |= CMU_HFXOCTRL_HFXOX2EN; + } + + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; +#endif + + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) + | (hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); + + /* Set timeouts */ + CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | (hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | (hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); + +#elif defined(_CMU_HFXOCTRL_MASK) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + /* AC coupled external clock not supported. */ + EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); + if (hfxoInit->mode == cmuOscMode_External) { + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + } + + /* Apply control settings. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) + | tmp; + BUS_RegBitWrite(&CMU->HFXOCTRL, + _CMU_HFXOCTRL_LOWPOWER_SHIFT, + (unsigned)hfxoInit->lowPowerMode); + + /* Set XTAL tuning parameters. */ + +#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + /* Set peak detection threshold. */ + CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + | (hfxoInit->thresholdPeakDetect + << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); +#endif + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | ((uint32_t)hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) + | ((uint32_t)hfxoInit->regIshSteadyState + << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) + | getRegIshUpperVal(hfxoInit->regIshSteadyState); + + /* Set timeouts. */ + CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutShuntOptimization + << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); + +#else + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK + | _CMU_CTRL_HFXOBOOST_MASK + | _CMU_CTRL_HFXOMODE_MASK + | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) + | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) + | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) + | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) + | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); +#endif +} + +/***************************************************************************//** + * @brief + * Get the LCD framerate divisor (FDIV) setting. + * + * @return + * The LCD framerate divisor. + ******************************************************************************/ +uint32_t CMU_LCDClkFDIVGet(void) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; +#else + return 0; +#endif /* defined(LCD_PRESENT) */ +} + +/***************************************************************************//** + * @brief + * Set the LCD framerate divisor (FDIV) setting. + * + * @note + * The FDIV field (CMU LCDCTRL register) should only be modified while the + * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function + * will NOT modify FDIV if the LCD module clock is enabled. See + * @ref CMU_ClockEnable() for disabling/enabling LCD clock. + * + * @param[in] div + * The FDIV setting to use. + ******************************************************************************/ +void CMU_LCDClkFDIVSet(uint32_t div) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + EFM_ASSERT(div <= cmuClkDiv_128); + + /* Do not allow modification if LCD clock enabled. */ + if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { + return; + } + + div <<= _CMU_LCDCTRL_FDIV_SHIFT; + div &= _CMU_LCDCTRL_FDIV_MASK; + CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; +#else + (void)div; /* Unused parameter. */ +#endif /* defined(LCD_PRESENT) */ +} + +/**************************************************************************//** + * @brief + * Set LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the LFXO when + * necessary to ensure a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters. + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); + +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK + | _CMU_LFXOCTRL_GAIN_MASK + | _CMU_LFXOCTRL_TIMEOUT_MASK + | _CMU_LFXOCTRL_MODE_MASK)) + | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) + | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) + | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); + + /* If LFXO already contains the correct configuration then there is no need + * to stop the oscillator and apply new settings. The LFXO can be running out + * of reset, in which case there is no need to disable it unless necessary. */ + if (reg != CMU->LFXOCTRL) { + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + CMU->LFXOCTRL = reg; + } +#elif defined(_SILICON_LABS_32B_SERIES_0) + /* LFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + + bool cmuBoost = (lfxoInit->boost & 0x2); + BUS_RegMaskedWrite(&CMU->CTRL, + _CMU_CTRL_LFXOTIMEOUT_MASK + | _CMU_CTRL_LFXOBOOST_MASK + | _CMU_CTRL_LFXOMODE_MASK, + ((uint32_t)lfxoInit->timeout + << _CMU_CTRL_LFXOTIMEOUT_SHIFT) + | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + /* EFM32GG has a "reduce startup boost" field in the EMU */ + bool emuReduce = (lfxoInit->boost & 0x1); + BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); +#endif +#endif +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * WARNING: When this function is called to disable either cmuOsc_LFXO or + * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register + * are reset to the reset value. In other words, if external clock sources are selected + * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared + * and needs to be reconfigured if needed later. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) +{ + uint32_t rdyBitPos; +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t ensBitPos; +#endif +#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) + uint32_t hfxoTrimStatus; +#endif + + uint32_t enBit; + uint32_t disBit; + + switch (osc) { + case cmuOsc_HFRCO: + enBit = CMU_OSCENCMD_HFRCOEN; + disBit = CMU_OSCENCMD_HFRCODIS; + rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_HFXO: + enBit = CMU_OSCENCMD_HFXOEN; + disBit = CMU_OSCENCMD_HFXODIS; + rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; +#endif + break; + + case cmuOsc_AUXHFRCO: + enBit = CMU_OSCENCMD_AUXHFRCOEN; + disBit = CMU_OSCENCMD_AUXHFRCODIS; + rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFRCO: + enBit = CMU_OSCENCMD_LFRCOEN; + disBit = CMU_OSCENCMD_LFRCODIS; + rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFXO: + enBit = CMU_OSCENCMD_LFXOEN; + disBit = CMU_OSCENCMD_LFXODIS; + rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; +#endif + break; + +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + case cmuOsc_USHFRCO: + enBit = CMU_OSCENCMD_USHFRCOEN; + disBit = CMU_OSCENCMD_USHFRCODIS; + rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; +#endif + break; +#endif + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + if (!deviceHasPlfrco()) { + while (true) { // PLFRCO is not available + EFM_ASSERT(false); + } + } + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + + default: + /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled + and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily + intended for information: the ULFRCO is always on. */ + EFM_ASSERT(false); + return; + } + + if (enable) { + #if defined(_CMU_HFXOCTRL_MASK) + bool firstHfxoEnable = false; + + /* Enabling the HFXO for the first time requires special handling. + * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the + * first time the HFXO is enabled. */ + if (osc == cmuOsc_HFXO) { + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); +#endif + + firstHfxoEnable = true; + /* The first time that an external clock is enabled, switch to CMD mode to make sure that + * only SCO and not PDA tuning is performed. */ + if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { + setHfxoTuningMode(HFXO_TUNING_MODE_CMD); + } + } + } +#endif + CMU->OSCENCMD = enBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go high. */ + while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { + } +#endif + + /* Wait for the clock to become ready after enable. */ + if (wait) { + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } +#if defined(_SILICON_LABS_32B_SERIES_1) + if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { + if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) + == CMU_HFXOCTRL_MODE_DIGEXTCLK) { +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + /* External clock mode should only do shunt current optimization. */ + (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, + cmuHFXOTuningMode_ShuntCommand, + true); +#endif + } else { + /* Wait for the peak detection and shunt current optimization + to complete. */ + (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); + } + + /* Disable the HFXO again to apply the trims. Apply trim from + HFXOTRIMSTATUS when disabled. */ + hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); + + /* Restart in CMD mode. */ + CMU->OSCENCMD = enBit; + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } + } +#endif + } + } else { + CMU->OSCENCMD = disBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go low. */ + while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { + } + + if (wait) { + /* Wait for RDY to go low as well. */ + while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { + } + } +#endif + } +} + +/***************************************************************************//** + * @brief + * Get the oscillator frequency tuning setting. + * + * @param[in] osc + * An oscillator to get tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret; + + switch (osc) { + case cmuOsc_LFRCO: + ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) + >> _CMU_LFRCOCTRL_TUNING_SHIFT; + break; + + case cmuOsc_HFRCO: + ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) + >> _CMU_USHFRCOCTRL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_AUXHFRCO: + ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK +#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) + | _CMU_HFXOTRIMSTATUS_REGISH_MASK +#endif + ); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + ret = (CMU->LFXOCTRL & _CMU_LFXOCTRL_TUNING_MASK) >> _CMU_LFXOCTRL_TUNING_SHIFT; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production and the tuning value is + * automatically loaded after reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + uint8_t ctune = 0; +#endif + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + uint32_t regIshUpper; +#endif + + switch (osc) { + case cmuOsc_LFRCO: + EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK + >> _CMU_LFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) + | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); + break; + + case cmuOsc_HFRCO: + EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK + >> _CMU_HFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) + | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK + >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { + } +#endif + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_AUXHFRCO: + EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + + /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ + EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); + + /* Switch to command mode. Automatic SCO and PDA calibration is not done + at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | val + | regIshUpper; +#else + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) + | val; +#endif + + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + EFM_ASSERT(val <= (_CMU_LFXOCTRL_TUNING_MASK >> _CMU_LFXOCTRL_TUNING_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for the CMU_LFXOCTRL is ready for update + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFXOBSY_SHIFT) != 0UL) { + } + CMU->LFXOCTRL = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK)) + | ((uint32_t)ctune << _CMU_LFXOCTRL_TUNING_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/***************************************************************************//** + * @brief + * Wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode) +{ + uint32_t waitFlags; + EFM_ASSERT(osc == cmuOsc_HFXO); + + /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ + (void)osc; + + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + waitFlags = HFXO_TUNING_READY_FLAGS; + } else { + /* Set wait flags for each command and wait. */ + switch (mode) { +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) + case cmuHFXOTuningMode_ShuntCommand: + waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; + break; +#endif + case cmuHFXOTuningMode_Auto: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; + +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + case cmuHFXOTuningMode_PeakShuntCommand: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; +#endif + + default: + waitFlags = _CMU_STATUS_MASK; + EFM_ASSERT(false); + break; + } + } + while ((CMU->STATUS & waitFlags) != waitFlags) { + } + +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Check error flags. */ + if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { + return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Start and optionally wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @param[in] wait + * Wait for tuning optimization to complete. + * true - wait for tuning optimization to complete. + * false - return without waiting. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait) +{ + switch (osc) { + case cmuOsc_HFXO: + if ((unsigned)mode != 0U) { +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Clear the error flag before command write. */ + CMU->IFC = CMU_IFC_HFXOPEAKDETERR; +#endif + CMU->CMD = (uint32_t)mode; + } + if (wait) { + return CMU_OscillatorTuningWait(osc, mode); + } + break; + + default: + EFM_ASSERT(false); + break; + } + return true; +} +#endif + +/**************************************************************************//** + * @brief + * Determine if the currently selected PCNTn clock used is external or LFBCLK. + * + * @param[in] instance + * PCNT instance number to get currently selected clock source for. + * + * @return + * @li true - selected clock is external clock. + * @li false - selected clock is LFBCLK. + *****************************************************************************/ +bool CMU_PCNTClockExternalGet(unsigned int instance) +{ + uint32_t setting; + + switch (instance) { +#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) + case 0: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) + case 1: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) + case 2: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; + break; +#endif +#endif +#endif + + default: + setting = 0; + break; + } + return setting > 0UL ? true : false; +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select LFBCLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ +#if defined(PCNT_PRESENT) + uint32_t setting = 0; + + EFM_ASSERT(instance < (unsigned)PCNT_COUNT); + + if (external) { + setting = 1; + } + + BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); + +#else + (void)instance; /* An unused parameter */ + (void)external; /* An unused parameter */ +#endif +} + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Get USHFRCO band in use. + * + * @return + * USHFRCO band in use. + ******************************************************************************/ +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF + & _CMU_USHFRCOCONF_BAND_MASK) + >> _CMU_USHFRCOCONF_BAND_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the USHFRCO band to use. + * + * @param[in] band + * USHFRCO band to activate. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t fineTuning; + + /* Cannot switch band if USHFRCO is already selected as HF clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCODIV2); + + /* Read tuning value from calibration table. */ + switch (band) { + case cmuUSHFRCOBand_24MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; + ushfrcoFreq = 24000000UL; + break; + + case cmuUSHFRCOBand_48MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; + /* Enable the clock divider before switching the band from 24 to 48 MHz */ + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); + ushfrcoFreq = 48000000UL; + break; + + default: + EFM_ASSERT(false); + return; + } + + /* Set band and tuning. */ + CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) + | (band << _CMU_USHFRCOCONF_BAND_SHIFT); + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) + | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); + CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) + | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); + + /* Disable the clock divider after switching the band from 48 to 24 MHz. */ + if (band == cmuUSHFRCOBand_24MHz) { + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); + } +} +#endif + +#endif // defined(_SILICON_LABS_32B_SERIES_2) +/** @} (end addtogroup cmu) */ +#endif /* defined(CMU_PRESENT) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_core.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_core.c index 571ec9b..4c4c434 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_core.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_core.c @@ -1,1028 +1,1028 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_core.h" -#include "sl_assert.h" - -/* *INDENT-OFF* */ -// ***************************************************************************** -/// @addtogroup core CORE - Core Interrupt -/// -///@n @section core_intro Introduction -/// -/// CORE interrupt API provides a simple and safe means -/// to disable and enable interrupts to protect sections of code. -/// -/// This is often referred to as "critical sections". This module provides -/// support for three types of critical sections, each with different interrupt -/// blocking capabilities. -/// -/// @li CRITICAL section: Inside a critical section, all interrupts are -/// disabled (except for fault handlers). The PRIMASK register is always used for -/// interrupt disable/enable. -/// @li ATOMIC section: This type of section is configurable and the default -/// method is to use PRIMASK. With BASEPRI configuration, interrupts with priority -/// equal to or lower than a given configurable level are disabled. The interrupt -/// disable priority level is defined at compile time. The BASEPRI register is not -/// available for all architectures. -/// @li NVIC mask section: Disable NVIC (external interrupts) on an -/// individual manner. -/// -/// em_core also has an API for manipulating RAM-based interrupt vector tables. -/// -///@n @section core_conf Compile-time Configuration -/// -/// The following #defines are used to configure em_core: -/// @code{.c} -/// // The interrupt priority level used inside ATOMIC sections. -/// #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 -/// -/// // A method used for interrupt disable/enable within ATOMIC sections. -/// #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK -/// @endcode -/// -/// If the default values do not support your needs, they can be overridden -/// by supplying -D compiler flags on the compiler command line or by collecting -/// all macro redefinitions in a file named @em emlib_config.h and then supplying -/// -DEMLIB_USER_CONFIG on a compiler command line. -/// -/// @note The default emlib configuration for ATOMIC section interrupt disable -/// method is using PRIMASK, i.e., ATOMIC sections are implemented as -/// CRITICAL sections. -/// -/// @note Due to architectural limitations Cortex-M0+ devices do not support -/// ATOMIC type critical sections using the BASEPRI register. On M0+ -/// devices ATOMIC section helper macros are available but they are -/// implemented as CRITICAL sections using PRIMASK register. -/// -///@n @section core_macro_api Macro API -/// -/// The primary em_core API is the macro API. Macro API will map to correct -/// CORE functions according to the selected @ref CORE_ATOMIC_METHOD and similar -/// configurations (the full CORE API is of course also available). -/// The most useful macros are as follows: -/// -/// @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_ATOMIC() @n -/// @ref CORE_EXIT_ATOMIC()@n -/// Used together to implement an ATOMIC section. -/// @code{.c} -/// { -/// CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to -/// // atomic section entry. -/// -/// CORE_ENTER_ATOMIC(); // Enter atomic section. -/// -/// ... -/// ... your code goes here ... -/// ... -/// -/// CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. -/// } -/// @endcode -/// -/// @n @ref CORE_ATOMIC_SECTION(yourcode)@n -/// A concatenation of all three macros above. -/// @code{.c} -/// { -/// CORE_ATOMIC_SECTION( -/// ... -/// ... your code goes here ... -/// ... -/// ) -/// } -/// @endcode -/// -/// @n @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_CRITICAL() @n -/// @ref CORE_EXIT_CRITICAL() @n @ref CORE_CRITICAL_SECTION(yourcode)@n -/// These macros implement CRITICAL sections in a similar fashion as described -/// above for ATOMIC sections. -/// -/// @n @ref CORE_DECLARE_NVIC_STATE @n @ref CORE_ENTER_NVIC() @n -/// @ref CORE_EXIT_NVIC() @n @ref CORE_NVIC_SECTION(yourcode)@n -/// These macros implement NVIC mask sections in a similar fashion as described -/// above for ATOMIC sections. See @ref core_examples for an example. -/// -/// Refer to @em Macros or Macro Definition Documentation below for a -/// full list of macros. -/// -///@n @section core_reimplementation API reimplementation -/// -/// Most of the functions in the API are implemented as weak functions. This means -/// that it is easy to reimplement when special needs arise. Shown below is a -/// reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: -/// @code{.c} -/// CORE_irqState_t CORE_EnterCritical(void) -/// { -/// vPortEnterCritical(); -/// return 0; -/// } -/// -/// void CORE_ExitCritical(CORE_irqState_t irqState) -/// { -/// (void)irqState; -/// vPortExitCritical(); -/// } -/// @endcode -/// Also note that CORE_Enter/ExitCritical() are not implemented as inline -/// functions. As a result, reimplementations will be possible even when original -/// implementations are inside a linked library. -/// -/// Some RTOSes must be notified on interrupt handler entry and exit. Macros -/// @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable -/// placeholders for inserting such code. Insert these macros in all your -/// interrupt handlers and then override the default macro implementations. -/// This is an example if uC/OS is used: -/// @code{.c} -/// // In emlib_config.h: -/// -/// #define CORE_INTERRUPT_ENTRY() OSIntEnter() -/// #define CORE_INTERRUPT_EXIT() OSIntExit() -/// @endcode -/// -///@n @section core_vector_tables Interrupt vector tables -/// -/// When using RAM based interrupt vector tables it is the user's responsibility -/// to allocate the table space correctly. The tables must be aligned as specified -/// in the CPU reference manual. -/// -/// @ref CORE_InitNvicVectorTable()@n -/// Initialize a RAM based vector table by copying table entries from a source -/// vector table to a target table. VTOR is set to the address of the target -/// vector table. -/// -/// @n @ref CORE_GetNvicRamTableHandler() @n @ref CORE_SetNvicRamTableHandler()@n -/// Use these functions to get or set the interrupt handler for a specific IRQn. -/// They both use the interrupt vector table defined by the current -/// VTOR register value. -/// -///@n @section core_max_timing Maximum Interrupt Disabled Time -/// -/// The maximum time spent (in cycles) in critical and atomic sections can be -/// measured for performance and interrupt latency analysis. -/// To enable the timings, use the SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING -/// configuration option. When enabled, the functions -/// @n @ref CORE_get_max_time_critical_section() -/// @n @ref CORE_get_max_time_atomic_section() @n -/// can be used to get the max timings since startup. -/// -///@n @section core_examples Examples -/// -/// Implement an NVIC critical section: -/// @code{.c} -/// { -/// CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask -/// -/// // Set mask bits for IRQs to block in the NVIC critical section. -/// // In many cases, you can create the disable mask once upon application -/// // startup and use the mask globally throughout the application lifetime. -/// CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); -/// CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); -/// -/// // Enter NVIC critical section with the disable mask -/// CORE_NVIC_SECTION(&mask, -/// ... -/// ... your code goes here ... -/// ... -/// ) -/// } -/// @endcode -/// -///@n @section core_porting Porting from em_int -/// -/// Existing code using INT_Enable() and INT_Disable() must be ported to the -/// em_core API. While em_int used, a global counter to store the interrupt state, -/// em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to -/// be replaced with a declaration of the interrupt state variable before entering -/// the critical section. -/// -/// Since the state variable is in local scope, the critical section exit -/// needs to occur within the scope of the variable. If multiple nested critical -/// sections are used, each needs to have its own state variable in its own scope. -/// -/// In many cases, completely disabling all interrupts using CRITICAL sections -/// might be more heavy-handed than needed. When porting, consider whether other -/// types of sections, such as ATOMIC or NVIC mask, can be used to only disable -/// a subset of the interrupts. -/// -/// Replacing em_int calls with em_core function calls: -/// @code{.c} -/// void func(void) -/// { -/// // INT_Disable(); -/// CORE_DECLARE_IRQ_STATE; -/// CORE_ENTER_ATOMIC(); -/// . -/// . -/// . -/// // INT_Enable(); -/// CORE_EXIT_ATOMIC(); -/// } -/// @endcode -/// @{ -// ***************************************************************************** -/* *INDENT-ON* */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if !defined(CORE_INTERRUPT_ENTRY) -// Some RTOSes must be notified on interrupt entry (and exit). -// Use this macro at the start of all your interrupt handlers. -// Reimplement the macro in emlib_config.h to suit the needs of your RTOS. -/** Placeholder for optional interrupt handler entry code. This might be needed - * when working with an RTOS. */ -#define CORE_INTERRUPT_ENTRY() -#endif - -#if !defined(CORE_INTERRUPT_EXIT) -/** Placeholder for optional interrupt handler exit code. This might be needed - * when working with an RTOS. */ -#define CORE_INTERRUPT_EXIT() -#endif - -// Compile time sanity check. -#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \ - && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI) -#error "em_core: Undefined ATOMIC IRQ handling strategy." -#endif - -/******************************************************************************* - ************************** STRUCTS **************************************** - ******************************************************************************/ -/** A Cycle Counter Instance. */ -typedef struct { - uint32_t start; /*!< Cycle counter at start of recording. */ - uint32_t cycles; /*!< Cycles elapsed in last recording. */ - uint32_t max; /*!< Max recorded cycles since last reset or init. */ -} dwt_cycle_counter_handle_t; - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -// cycle counter to record atomic sections -dwt_cycle_counter_handle_t atomic_cycle_counter = { 0 }; -// cycle counter to record critical sections -dwt_cycle_counter_handle_t critical_cycle_counter = { 0 }; -#endif - -/** @endcond */ - -/******************************************************************************* - *************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -static void cycle_counter_start(dwt_cycle_counter_handle_t *handle); -static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle); -#endif - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable interrupts. - * - * Disable all interrupts by setting PRIMASK. - * (Fault exception handlers will still be enabled). - ******************************************************************************/ -SL_WEAK void CORE_CriticalDisableIrq(void) -{ - __disable_irq(); -} - -/***************************************************************************//** - * @brief - * Enable interrupts. - * - * Enable interrupts by clearing PRIMASK. - ******************************************************************************/ -SL_WEAK void CORE_CriticalEnableIrq(void) -{ - __enable_irq(); -} - -/***************************************************************************//** - * @brief - * Enter a CRITICAL section. - * - * When a CRITICAL section is entered, all interrupts (except fault handlers) - * are disabled. - * - * @return - * The value of PRIMASK register prior to the CRITICAL section entry. - ******************************************************************************/ -SL_WEAK CORE_irqState_t CORE_EnterCritical(void) -{ - CORE_irqState_t irqState = __get_PRIMASK(); - __disable_irq(); - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&critical_cycle_counter); -#endif - } - return irqState; -} - -/***************************************************************************//** - * @brief - * Exit a CRITICAL section. - * - * @param[in] irqState - * The interrupt priority blocking level to restore to PRIMASK when exiting - * the CRITICAL section. This value is usually the one returned by a prior - * call to @ref CORE_EnterCritical(). - ******************************************************************************/ -SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) -{ - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&critical_cycle_counter); -#endif - __enable_irq(); - } -} - -/***************************************************************************//** - * @brief - * Brief interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @note - * Usually used within a CRITICAL section. - ******************************************************************************/ -SL_WEAK void CORE_YieldCritical(void) -{ - if ((__get_PRIMASK() & 1U) != 0U) { - __enable_irq(); - __ISB(); - __disable_irq(); - } -} - -/***************************************************************************//** - * @brief - * Disable interrupts. - * - * Disable interrupts with a priority lower or equal to - * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register - * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_CriticalDisableIrq(). - ******************************************************************************/ -SL_WEAK void CORE_AtomicDisableIrq(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8UL - __NVIC_PRIO_BITS)); -#else - __disable_irq(); -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enable interrupts. - * - * Enable interrupts by setting core BASEPRI register to 0. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK - * is set (CPU is inside a CRITICAL section), interrupts will still be - * disabled after calling this function. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_CriticalEnableIrq(). - ******************************************************************************/ -SL_WEAK void CORE_AtomicEnableIrq(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - __set_BASEPRI(0); -#else - __enable_irq(); -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enter an ATOMIC section. - * - * When an ATOMIC section is entered, interrupts with priority lower or equal - * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_EnterCritical(). - * - * @return - * The value of BASEPRI register prior to ATOMIC section entry. - ******************************************************************************/ -SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - CORE_irqState_t irqState = __get_BASEPRI(); - __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS)); - if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) - != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&atomic_cycle_counter); -#endif - } - return irqState; -#else - CORE_irqState_t irqState = __get_PRIMASK(); - __disable_irq(); - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&atomic_cycle_counter); -#endif - } - return irqState; -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Exit an ATOMIC section. - * - * @param[in] irqState - * The interrupt priority blocking level to restore to BASEPRI when exiting - * the ATOMIC section. This value is usually the one returned by a prior - * call to @ref CORE_EnterAtomic(). - * - * @note - * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_ExitCritical(). - ******************************************************************************/ -SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) - != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&atomic_cycle_counter); -#endif - } - __set_BASEPRI(irqState); -#else - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&atomic_cycle_counter); -#endif - __enable_irq(); - } -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Brief interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @note - * Usully used within an ATOMIC section. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_YieldCritical(). - ******************************************************************************/ -SL_WEAK void CORE_YieldAtomic(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - CORE_irqState_t basepri = __get_BASEPRI(); - if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { - __set_BASEPRI(0); - __ISB(); - __set_BASEPRI(basepri); - } -#else - if ((__get_PRIMASK() & 1U) != 0U) { - __enable_irq(); - __ISB(); - __disable_irq(); - } -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enter a NVIC mask section. - * - * When a NVIC mask section is entered, specified NVIC interrupts - * are disabled. - * - * @param[out] nvicState - * Return NVIC interrupts enable mask prior to section entry. - * - * @param[in] disable - * A mask specifying which NVIC interrupts to disable within the section. - ******************************************************************************/ -void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, - const CORE_nvicMask_t *disable) -{ - CORE_CRITICAL_SECTION( - *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; - ) -} - -/***************************************************************************//** - * @brief - * Disable NVIC interrupts. - * - * @param[in] disable - * A mask specifying which NVIC interrupts to disable. - ******************************************************************************/ -void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) -{ - CORE_CRITICAL_SECTION( - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; - ) -} - -/***************************************************************************//** - * @brief - * Set current NVIC interrupt enable mask. - * - * @param[out] enable - * A mask specifying which NVIC interrupts are currently enabled. - ******************************************************************************/ -void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) -{ - CORE_CRITICAL_SECTION( - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; - ) -} - -/***************************************************************************//** - * @brief - * Brief NVIC interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @param[in] enable - * A mask specifying which NVIC interrupts to briefly enable. - * - * @note - * Usually used within an NVIC mask section. - ******************************************************************************/ -void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) -{ - CORE_nvicMask_t nvicMask; - - // Get current NVIC enable mask. - CORE_CRITICAL_SECTION( - nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) - - // Make a mask with bits set for those interrupts that are currently - // disabled but are set in the enable mask. -#if (CORE_NVIC_REG_WORDS == 1) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - - if (nvicMask.a[0] != 0) { -#elif (CORE_NVIC_REG_WORDS == 2) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[1] &= enable->a[1]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; - - if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { -#elif (CORE_NVIC_REG_WORDS == 3) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[1] &= enable->a[1]; - nvicMask.a[2] &= enable->a[2]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; - nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; - - if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U) || (nvicMask.a[2] != 0U)) { -#endif - - // Enable previously disabled interrupts. - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; - - // Disable those interrupts again. - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; - } -} - -/***************************************************************************//** - * @brief - * Utility function to set an IRQn bit in a NVIC enable/disable mask. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in,out] mask - * The mask to set the interrupt bit in. - ******************************************************************************/ -void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) -{ - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); -} - -/***************************************************************************//** - * @brief - * Utility function to clear an IRQn bit in a NVIC enable/disable mask. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in,out] mask - * The mask to clear the interrupt bit in. - ******************************************************************************/ -void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) -{ - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); -} - -/***************************************************************************//** - * @brief - * Check whether the current CPU operation mode is handler mode. - * - * @return - * True if the CPU is in handler mode (currently executing an interrupt handler). - * @n False if the CPU is in thread mode. - ******************************************************************************/ -SL_WEAK bool CORE_InIrqContext(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; -} - -/***************************************************************************//** - * @brief - * Check if a specific interrupt is disabled or blocked. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt to check. - * - * @return - * True if the interrupt is disabled or blocked. - ******************************************************************************/ -SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) -{ - uint32_t irqPri, activeIrq; - -#if (__CORTEX_M >= 3) - uint32_t basepri; - - EFM_ASSERT((irqN >= MemoryManagement_IRQn) - && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); -#else - EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); -#endif - - if ((__get_PRIMASK() & 1U) != 0U) { - return true; // All IRQs are disabled. - } - - if (CORE_NvicIRQDisabled(irqN)) { - return true; // The IRQ in question is disabled. - } - - irqPri = NVIC_GetPriority(irqN); -#if (__CORTEX_M >= 3) - basepri = __get_BASEPRI(); - if ((basepri != 0U) - && (irqPri >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { - return true; // The IRQ in question has too low - } // priority vs. BASEPRI. -#endif - - // Check if already in an interrupt handler. If so, an interrupt with a - // higher priority (lower priority value) can preempt. - activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; - if (activeIrq != 0U) { - if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { - return true; // The IRQ in question has too low - } // priority vs. current active IRQ - } - - return false; -} - -/***************************************************************************//** - * @brief - * Check if interrupts are disabled. - * - * @return - * True if interrupts are disabled. - ******************************************************************************/ -SL_WEAK bool CORE_IrqIsDisabled(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK) - return (__get_PRIMASK() & 1U) == 1U; - -#elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - return ((__get_PRIMASK() & 1U) == 1U) - || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL - << (8U - __NVIC_PRIO_BITS))); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current NVIC enable mask state. - * - * @param[out] mask - * The current NVIC enable mask. - ******************************************************************************/ -void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) -{ - CORE_CRITICAL_SECTION( - *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) -} - -/***************************************************************************//** - * @brief - * Get NVIC disable state for a given mask. - * - * @param[in] mask - * An NVIC mask to check. - * - * @return - * True if all NVIC interrupt mask bits are clear. - ******************************************************************************/ -bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) -{ - CORE_nvicMask_t nvicMask; - - CORE_CRITICAL_SECTION( - nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) - -#if (CORE_NVIC_REG_WORDS == 1) - return (mask->a[0] & nvicMask.a[0]) == 0U; - -#elif (CORE_NVIC_REG_WORDS == 2) - return ((mask->a[0] & nvicMask.a[0]) == 0U) - && ((mask->a[1] & nvicMask.a[1]) == 0U); - -#elif (CORE_NVIC_REG_WORDS == 3) - return ((mask->a[0] & nvicMask.a[0]) == 0U) - && ((mask->a[1] & nvicMask.a[1]) == 0U) - && ((mask->a[2] & nvicMask.a[2]) == 0U); -#endif -} - -/***************************************************************************//** - * @brief - * Check if an NVIC interrupt is disabled. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt to check. - * - * @return - * True if the interrupt is disabled. - ******************************************************************************/ -bool CORE_NvicIRQDisabled(IRQn_Type irqN) -{ - CORE_nvicMask_t *mask; - - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) - == 0UL; -} - -/***************************************************************************//** - * @brief - * Utility function to get the handler for a specific interrupt. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @return - * The handler address. - * - * @note - * Uses the interrupt vector table defined by the current VTOR register value. - ******************************************************************************/ -void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) -{ - EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); - return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); -} - -/***************************************************************************//** - * @brief - * Utility function to set the handler for a specific interrupt. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in] handler - * The handler address. - * - * @note - * Uses the interrupt vector table defined by the current VTOR register value. - ******************************************************************************/ -void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) -{ - EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); - ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); -} - -/***************************************************************************//** - * @brief - * Initialize an interrupt vector table by copying table entries from a - * source to a target table. - * - * @note This function will set a new VTOR register value. - * - * @param[in] sourceTable - * The address of the source vector table. - * - * @param[in] sourceSize - * A number of entries in the source vector table. - * - * @param[in] targetTable - * The address of the target (new) vector table. - * - * @param[in] targetSize - * A number of entries in the target vector table. - * - * @param[in] defaultHandler - * An address of the interrupt handler used for target entries for which where there - * is no corresponding source entry (i.e., the target table is larger than the source - * table). - * - * @param[in] overwriteActive - * When true, a target table entry is always overwritten with the - * corresponding source entry. If false, a target table entry is only - * overwritten if it is zero. This makes it possible for an application - * to partly initialize a target table before passing it to this function. - * - ******************************************************************************/ -void CORE_InitNvicVectorTable(uint32_t *sourceTable, - uint32_t sourceSize, - uint32_t *targetTable, - uint32_t targetSize, - void *defaultHandler, - bool overwriteActive) -{ - uint32_t i; - - // ASSERT on non SRAM-based target table. - EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) - && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); - - // ASSERT if misaligned with respect to the VTOR register implementation. -#if defined(SCB_VTOR_TBLBASE_Msk) - EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk - | SCB_VTOR_TBLBASE_Msk)) == 0U); -#else - EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); -#endif - - // ASSERT if misaligned with respect to the vector table size. - // The vector table address must be aligned at its size rounded up to nearest 2^n. - EFM_ASSERT(((uint32_t)targetTable - & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) - == 0UL); - - for (i = 0; i < targetSize; i++) { - if (overwriteActive) { // Overwrite target entries. - if (i < sourceSize) { // targetSize <= sourceSize - targetTable[i] = sourceTable[i]; - } else { // targetSize > sourceSize - targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); - } - } else { // Overwrite target entries which are 0. - if (i < sourceSize) { // targetSize <= sourceSize - if (targetTable[i] == 0U) { - targetTable[i] = sourceTable[i]; - } - } else { // targetSize > sourceSize - if (targetTable[i] == 0U) { - targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); - } - } - } - } - SCB->VTOR = (uint32_t)targetTable; -} - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Start a recording. - * - * @param[in] handle - * Pointer to initialized counter handle. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -static void cycle_counter_start(dwt_cycle_counter_handle_t *handle) -{ - handle->start = DWT->CYCCNT; -} - -/***************************************************************************//** - * @brief - * Stop a recording. - * - * @param[in] handle - * Pointer to initialized counter handle. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle) -{ - handle->cycles = DWT->CYCCNT - handle->start; - - if (handle->cycles > handle->max) { - handle->max = handle->cycles; - } -} - -/***************************************************************************//** - * @brief - * Returns the max time spent in critical section. - * - * @return - * The max time spent in critical section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -uint32_t CORE_get_max_time_critical_section(void) -{ - return critical_cycle_counter.max; -} - -/***************************************************************************//** - * @brief - * Returns the max time spent in atomic section. - * - * @return - * The max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -uint32_t CORE_get_max_time_atomic_section(void) -{ - return atomic_cycle_counter.max; -} - -/***************************************************************************//** - * @brief - * Clears the max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -void CORE_clear_max_time_critical_section(void) -{ - critical_cycle_counter.max = 0; -} - -/***************************************************************************//** - * @brief - * Clears the max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -void CORE_clear_max_time_atomic_section(void) -{ - atomic_cycle_counter.max = 0; -} -#endif //(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - -/** @} (end addtogroup core) */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_core.h" +#include "sl_assert.h" + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup core CORE - Core Interrupt +/// +///@n @section core_intro Introduction +/// +/// CORE interrupt API provides a simple and safe means +/// to disable and enable interrupts to protect sections of code. +/// +/// This is often referred to as "critical sections". This module provides +/// support for three types of critical sections, each with different interrupt +/// blocking capabilities. +/// +/// @li CRITICAL section: Inside a critical section, all interrupts are +/// disabled (except for fault handlers). The PRIMASK register is always used for +/// interrupt disable/enable. +/// @li ATOMIC section: This type of section is configurable and the default +/// method is to use PRIMASK. With BASEPRI configuration, interrupts with priority +/// equal to or lower than a given configurable level are disabled. The interrupt +/// disable priority level is defined at compile time. The BASEPRI register is not +/// available for all architectures. +/// @li NVIC mask section: Disable NVIC (external interrupts) on an +/// individual manner. +/// +/// em_core also has an API for manipulating RAM-based interrupt vector tables. +/// +///@n @section core_conf Compile-time Configuration +/// +/// The following #defines are used to configure em_core: +/// @code{.c} +/// // The interrupt priority level used inside ATOMIC sections. +/// #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 +/// +/// // A method used for interrupt disable/enable within ATOMIC sections. +/// #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK +/// @endcode +/// +/// If the default values do not support your needs, they can be overridden +/// by supplying -D compiler flags on the compiler command line or by collecting +/// all macro redefinitions in a file named @em emlib_config.h and then supplying +/// -DEMLIB_USER_CONFIG on a compiler command line. +/// +/// @note The default emlib configuration for ATOMIC section interrupt disable +/// method is using PRIMASK, i.e., ATOMIC sections are implemented as +/// CRITICAL sections. +/// +/// @note Due to architectural limitations Cortex-M0+ devices do not support +/// ATOMIC type critical sections using the BASEPRI register. On M0+ +/// devices ATOMIC section helper macros are available but they are +/// implemented as CRITICAL sections using PRIMASK register. +/// +///@n @section core_macro_api Macro API +/// +/// The primary em_core API is the macro API. Macro API will map to correct +/// CORE functions according to the selected @ref CORE_ATOMIC_METHOD and similar +/// configurations (the full CORE API is of course also available). +/// The most useful macros are as follows: +/// +/// @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_ATOMIC() @n +/// @ref CORE_EXIT_ATOMIC()@n +/// Used together to implement an ATOMIC section. +/// @code{.c} +/// { +/// CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to +/// // atomic section entry. +/// +/// CORE_ENTER_ATOMIC(); // Enter atomic section. +/// +/// ... +/// ... your code goes here ... +/// ... +/// +/// CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. +/// } +/// @endcode +/// +/// @n @ref CORE_ATOMIC_SECTION(yourcode)@n +/// A concatenation of all three macros above. +/// @code{.c} +/// { +/// CORE_ATOMIC_SECTION( +/// ... +/// ... your code goes here ... +/// ... +/// ) +/// } +/// @endcode +/// +/// @n @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_CRITICAL() @n +/// @ref CORE_EXIT_CRITICAL() @n @ref CORE_CRITICAL_SECTION(yourcode)@n +/// These macros implement CRITICAL sections in a similar fashion as described +/// above for ATOMIC sections. +/// +/// @n @ref CORE_DECLARE_NVIC_STATE @n @ref CORE_ENTER_NVIC() @n +/// @ref CORE_EXIT_NVIC() @n @ref CORE_NVIC_SECTION(yourcode)@n +/// These macros implement NVIC mask sections in a similar fashion as described +/// above for ATOMIC sections. See @ref core_examples for an example. +/// +/// Refer to @em Macros or Macro Definition Documentation below for a +/// full list of macros. +/// +///@n @section core_reimplementation API reimplementation +/// +/// Most of the functions in the API are implemented as weak functions. This means +/// that it is easy to reimplement when special needs arise. Shown below is a +/// reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: +/// @code{.c} +/// CORE_irqState_t CORE_EnterCritical(void) +/// { +/// vPortEnterCritical(); +/// return 0; +/// } +/// +/// void CORE_ExitCritical(CORE_irqState_t irqState) +/// { +/// (void)irqState; +/// vPortExitCritical(); +/// } +/// @endcode +/// Also note that CORE_Enter/ExitCritical() are not implemented as inline +/// functions. As a result, reimplementations will be possible even when original +/// implementations are inside a linked library. +/// +/// Some RTOSes must be notified on interrupt handler entry and exit. Macros +/// @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable +/// placeholders for inserting such code. Insert these macros in all your +/// interrupt handlers and then override the default macro implementations. +/// This is an example if uC/OS is used: +/// @code{.c} +/// // In emlib_config.h: +/// +/// #define CORE_INTERRUPT_ENTRY() OSIntEnter() +/// #define CORE_INTERRUPT_EXIT() OSIntExit() +/// @endcode +/// +///@n @section core_vector_tables Interrupt vector tables +/// +/// When using RAM based interrupt vector tables it is the user's responsibility +/// to allocate the table space correctly. The tables must be aligned as specified +/// in the CPU reference manual. +/// +/// @ref CORE_InitNvicVectorTable()@n +/// Initialize a RAM based vector table by copying table entries from a source +/// vector table to a target table. VTOR is set to the address of the target +/// vector table. +/// +/// @n @ref CORE_GetNvicRamTableHandler() @n @ref CORE_SetNvicRamTableHandler()@n +/// Use these functions to get or set the interrupt handler for a specific IRQn. +/// They both use the interrupt vector table defined by the current +/// VTOR register value. +/// +///@n @section core_max_timing Maximum Interrupt Disabled Time +/// +/// The maximum time spent (in cycles) in critical and atomic sections can be +/// measured for performance and interrupt latency analysis. +/// To enable the timings, use the SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING +/// configuration option. When enabled, the functions +/// @n @ref CORE_get_max_time_critical_section() +/// @n @ref CORE_get_max_time_atomic_section() @n +/// can be used to get the max timings since startup. +/// +///@n @section core_examples Examples +/// +/// Implement an NVIC critical section: +/// @code{.c} +/// { +/// CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask +/// +/// // Set mask bits for IRQs to block in the NVIC critical section. +/// // In many cases, you can create the disable mask once upon application +/// // startup and use the mask globally throughout the application lifetime. +/// CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); +/// CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); +/// +/// // Enter NVIC critical section with the disable mask +/// CORE_NVIC_SECTION(&mask, +/// ... +/// ... your code goes here ... +/// ... +/// ) +/// } +/// @endcode +/// +///@n @section core_porting Porting from em_int +/// +/// Existing code using INT_Enable() and INT_Disable() must be ported to the +/// em_core API. While em_int used, a global counter to store the interrupt state, +/// em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to +/// be replaced with a declaration of the interrupt state variable before entering +/// the critical section. +/// +/// Since the state variable is in local scope, the critical section exit +/// needs to occur within the scope of the variable. If multiple nested critical +/// sections are used, each needs to have its own state variable in its own scope. +/// +/// In many cases, completely disabling all interrupts using CRITICAL sections +/// might be more heavy-handed than needed. When porting, consider whether other +/// types of sections, such as ATOMIC or NVIC mask, can be used to only disable +/// a subset of the interrupts. +/// +/// Replacing em_int calls with em_core function calls: +/// @code{.c} +/// void func(void) +/// { +/// // INT_Disable(); +/// CORE_DECLARE_IRQ_STATE; +/// CORE_ENTER_ATOMIC(); +/// . +/// . +/// . +/// // INT_Enable(); +/// CORE_EXIT_ATOMIC(); +/// } +/// @endcode +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if !defined(CORE_INTERRUPT_ENTRY) +// Some RTOSes must be notified on interrupt entry (and exit). +// Use this macro at the start of all your interrupt handlers. +// Reimplement the macro in emlib_config.h to suit the needs of your RTOS. +/** Placeholder for optional interrupt handler entry code. This might be needed + * when working with an RTOS. */ +#define CORE_INTERRUPT_ENTRY() +#endif + +#if !defined(CORE_INTERRUPT_EXIT) +/** Placeholder for optional interrupt handler exit code. This might be needed + * when working with an RTOS. */ +#define CORE_INTERRUPT_EXIT() +#endif + +// Compile time sanity check. +#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \ + && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI) +#error "em_core: Undefined ATOMIC IRQ handling strategy." +#endif + +/******************************************************************************* + ************************** STRUCTS **************************************** + ******************************************************************************/ +/** A Cycle Counter Instance. */ +typedef struct { + uint32_t start; /*!< Cycle counter at start of recording. */ + uint32_t cycles; /*!< Cycles elapsed in last recording. */ + uint32_t max; /*!< Max recorded cycles since last reset or init. */ +} dwt_cycle_counter_handle_t; + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +// cycle counter to record atomic sections +dwt_cycle_counter_handle_t atomic_cycle_counter = { 0 }; +// cycle counter to record critical sections +dwt_cycle_counter_handle_t critical_cycle_counter = { 0 }; +#endif + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle); +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable all interrupts by setting PRIMASK. + * (Fault exception handlers will still be enabled). + ******************************************************************************/ +SL_WEAK void CORE_CriticalDisableIrq(void) +{ + __disable_irq(); +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by clearing PRIMASK. + ******************************************************************************/ +SL_WEAK void CORE_CriticalEnableIrq(void) +{ + __enable_irq(); +} + +/***************************************************************************//** + * @brief + * Enter a CRITICAL section. + * + * When a CRITICAL section is entered, all interrupts (except fault handlers) + * are disabled. + * + * @return + * The value of PRIMASK register prior to the CRITICAL section entry. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterCritical(void) +{ + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&critical_cycle_counter); +#endif + } + return irqState; +} + +/***************************************************************************//** + * @brief + * Exit a CRITICAL section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to PRIMASK when exiting + * the CRITICAL section. This value is usually the one returned by a prior + * call to @ref CORE_EnterCritical(). + ******************************************************************************/ +SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) +{ + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&critical_cycle_counter); +#endif + __enable_irq(); + } +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usually used within a CRITICAL section. + ******************************************************************************/ +SL_WEAK void CORE_YieldCritical(void) +{ + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +} + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable interrupts with a priority lower or equal to + * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register + * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalDisableIrq(). + ******************************************************************************/ +SL_WEAK void CORE_AtomicDisableIrq(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8UL - __NVIC_PRIO_BITS)); +#else + __disable_irq(); +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by setting core BASEPRI register to 0. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK + * is set (CPU is inside a CRITICAL section), interrupts will still be + * disabled after calling this function. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalEnableIrq(). + ******************************************************************************/ +SL_WEAK void CORE_AtomicEnableIrq(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + __set_BASEPRI(0); +#else + __enable_irq(); +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enter an ATOMIC section. + * + * When an ATOMIC section is entered, interrupts with priority lower or equal + * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_EnterCritical(). + * + * @return + * The value of BASEPRI register prior to ATOMIC section entry. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + CORE_irqState_t irqState = __get_BASEPRI(); + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS)); + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&atomic_cycle_counter); +#endif + } + return irqState; +#else + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&atomic_cycle_counter); +#endif + } + return irqState; +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Exit an ATOMIC section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to BASEPRI when exiting + * the ATOMIC section. This value is usually the one returned by a prior + * call to @ref CORE_EnterAtomic(). + * + * @note + * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_ExitCritical(). + ******************************************************************************/ +SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&atomic_cycle_counter); +#endif + } + __set_BASEPRI(irqState); +#else + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&atomic_cycle_counter); +#endif + __enable_irq(); + } +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usully used within an ATOMIC section. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_YieldCritical(). + ******************************************************************************/ +SL_WEAK void CORE_YieldAtomic(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + CORE_irqState_t basepri = __get_BASEPRI(); + if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { + __set_BASEPRI(0); + __ISB(); + __set_BASEPRI(basepri); + } +#else + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enter a NVIC mask section. + * + * When a NVIC mask section is entered, specified NVIC interrupts + * are disabled. + * + * @param[out] nvicState + * Return NVIC interrupts enable mask prior to section entry. + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable within the section. + ******************************************************************************/ +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Disable NVIC interrupts. + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable. + ******************************************************************************/ +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Set current NVIC interrupt enable mask. + * + * @param[out] enable + * A mask specifying which NVIC interrupts are currently enabled. + ******************************************************************************/ +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; + ) +} + +/***************************************************************************//** + * @brief + * Brief NVIC interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @param[in] enable + * A mask specifying which NVIC interrupts to briefly enable. + * + * @note + * Usually used within an NVIC mask section. + ******************************************************************************/ +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) +{ + CORE_nvicMask_t nvicMask; + + // Get current NVIC enable mask. + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + + // Make a mask with bits set for those interrupts that are currently + // disabled but are set in the enable mask. +#if (CORE_NVIC_REG_WORDS == 1) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + + if (nvicMask.a[0] != 0) { +#elif (CORE_NVIC_REG_WORDS == 2) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { +#elif (CORE_NVIC_REG_WORDS == 3) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[2] &= enable->a[2]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U) || (nvicMask.a[2] != 0U)) { +#endif + + // Enable previously disabled interrupts. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; + + // Disable those interrupts again. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; + } +} + +/***************************************************************************//** + * @brief + * Utility function to set an IRQn bit in a NVIC enable/disable mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to set the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Utility function to clear an IRQn bit in a NVIC enable/disable mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to clear the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); +} + +/***************************************************************************//** + * @brief + * Check whether the current CPU operation mode is handler mode. + * + * @return + * True if the CPU is in handler mode (currently executing an interrupt handler). + * @n False if the CPU is in thread mode. + ******************************************************************************/ +SL_WEAK bool CORE_InIrqContext(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; +} + +/***************************************************************************//** + * @brief + * Check if a specific interrupt is disabled or blocked. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled or blocked. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) +{ + uint32_t irqPri, activeIrq; + +#if (__CORTEX_M >= 3) + uint32_t basepri; + + EFM_ASSERT((irqN >= MemoryManagement_IRQn) + && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); +#else + EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); +#endif + + if ((__get_PRIMASK() & 1U) != 0U) { + return true; // All IRQs are disabled. + } + + if (CORE_NvicIRQDisabled(irqN)) { + return true; // The IRQ in question is disabled. + } + + irqPri = NVIC_GetPriority(irqN); +#if (__CORTEX_M >= 3) + basepri = __get_BASEPRI(); + if ((basepri != 0U) + && (irqPri >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { + return true; // The IRQ in question has too low + } // priority vs. BASEPRI. +#endif + + // Check if already in an interrupt handler. If so, an interrupt with a + // higher priority (lower priority value) can preempt. + activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; + if (activeIrq != 0U) { + if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { + return true; // The IRQ in question has too low + } // priority vs. current active IRQ + } + + return false; +} + +/***************************************************************************//** + * @brief + * Check if interrupts are disabled. + * + * @return + * True if interrupts are disabled. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsDisabled(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK) + return (__get_PRIMASK() & 1U) == 1U; + +#elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + return ((__get_PRIMASK() & 1U) == 1U) + || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL + << (8U - __NVIC_PRIO_BITS))); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current NVIC enable mask state. + * + * @param[out] mask + * The current NVIC enable mask. + ******************************************************************************/ +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) +{ + CORE_CRITICAL_SECTION( + *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) +} + +/***************************************************************************//** + * @brief + * Get NVIC disable state for a given mask. + * + * @param[in] mask + * An NVIC mask to check. + * + * @return + * True if all NVIC interrupt mask bits are clear. + ******************************************************************************/ +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) +{ + CORE_nvicMask_t nvicMask; + + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + +#if (CORE_NVIC_REG_WORDS == 1) + return (mask->a[0] & nvicMask.a[0]) == 0U; + +#elif (CORE_NVIC_REG_WORDS == 2) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U); + +#elif (CORE_NVIC_REG_WORDS == 3) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U) + && ((mask->a[2] & nvicMask.a[2]) == 0U); +#endif +} + +/***************************************************************************//** + * @brief + * Check if an NVIC interrupt is disabled. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled. + ******************************************************************************/ +bool CORE_NvicIRQDisabled(IRQn_Type irqN) +{ + CORE_nvicMask_t *mask; + + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) + == 0UL; +} + +/***************************************************************************//** + * @brief + * Utility function to get the handler for a specific interrupt. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @return + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); +} + +/***************************************************************************//** + * @brief + * Utility function to set the handler for a specific interrupt. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in] handler + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); +} + +/***************************************************************************//** + * @brief + * Initialize an interrupt vector table by copying table entries from a + * source to a target table. + * + * @note This function will set a new VTOR register value. + * + * @param[in] sourceTable + * The address of the source vector table. + * + * @param[in] sourceSize + * A number of entries in the source vector table. + * + * @param[in] targetTable + * The address of the target (new) vector table. + * + * @param[in] targetSize + * A number of entries in the target vector table. + * + * @param[in] defaultHandler + * An address of the interrupt handler used for target entries for which where there + * is no corresponding source entry (i.e., the target table is larger than the source + * table). + * + * @param[in] overwriteActive + * When true, a target table entry is always overwritten with the + * corresponding source entry. If false, a target table entry is only + * overwritten if it is zero. This makes it possible for an application + * to partly initialize a target table before passing it to this function. + * + ******************************************************************************/ +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive) +{ + uint32_t i; + + // ASSERT on non SRAM-based target table. + EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) + && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); + + // ASSERT if misaligned with respect to the VTOR register implementation. +#if defined(SCB_VTOR_TBLBASE_Msk) + EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk + | SCB_VTOR_TBLBASE_Msk)) == 0U); +#else + EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); +#endif + + // ASSERT if misaligned with respect to the vector table size. + // The vector table address must be aligned at its size rounded up to nearest 2^n. + EFM_ASSERT(((uint32_t)targetTable + & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) + == 0UL); + + for (i = 0; i < targetSize; i++) { + if (overwriteActive) { // Overwrite target entries. + if (i < sourceSize) { // targetSize <= sourceSize + targetTable[i] = sourceTable[i]; + } else { // targetSize > sourceSize + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } else { // Overwrite target entries which are 0. + if (i < sourceSize) { // targetSize <= sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = sourceTable[i]; + } + } else { // targetSize > sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } + } + } + SCB->VTOR = (uint32_t)targetTable; +} + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Start a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle) +{ + handle->start = DWT->CYCCNT; +} + +/***************************************************************************//** + * @brief + * Stop a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle) +{ + handle->cycles = DWT->CYCCNT - handle->start; + + if (handle->cycles > handle->max) { + handle->max = handle->cycles; + } +} + +/***************************************************************************//** + * @brief + * Returns the max time spent in critical section. + * + * @return + * The max time spent in critical section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +uint32_t CORE_get_max_time_critical_section(void) +{ + return critical_cycle_counter.max; +} + +/***************************************************************************//** + * @brief + * Returns the max time spent in atomic section. + * + * @return + * The max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +uint32_t CORE_get_max_time_atomic_section(void) +{ + return atomic_cycle_counter.max; +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +void CORE_clear_max_time_critical_section(void) +{ + critical_cycle_counter.max = 0; +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +void CORE_clear_max_time_atomic_section(void) +{ + atomic_cycle_counter.max = 0; +} +#endif //(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + +/** @} (end addtogroup core) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c index b9c22a4..b567495 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c @@ -1,214 +1,214 @@ -/***************************************************************************//** - * @file - * @brief Debug (DBG) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_dbg.h" - -#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "em_gpio.h" -#include "em_msc.h" -#if defined(_SILICON_LABS_32B_SERIES_2) -#include "em_se.h" -#endif - -/***************************************************************************//** - * @addtogroup dbg DBG - Debug - * @brief Debug (DBG) Peripheral API - * @details - * This module contains functions to control the DBG peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The Debug Interface is used to program and debug - * Silicon Labs devices. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN) \ - || defined(GPIO_TRACEROUTEPEN_SWVPEN) -/***************************************************************************//** - * @brief - * Enable Serial Wire Output (SWO) pin. - * - * @details - * The SWO pin (sometimes denoted SWV, serial wire viewer) allows for - * miscellaneous output to be passed from the Cortex-M3 debug trace module to - * an external debug probe. By default, the debug trace module and pin output - * may be disabled. - * - * Since the SWO pin is only useful when using a debugger, a suggested use - * of this function during startup may be: - * @verbatim - * if (DBG_Connected()) - * { - * DBG_SWOEnable(1); - * } - * @endverbatim - * By checking if the debugger is attached, a setup leading to a higher energy - * consumption when the debugger is attached can be avoided when not using - * a debugger. - * - * Another alternative may be to set the debugger tool chain to configure - * the required setup (similar to the content of this function) by some - * sort of toolchain scripting during its attach/reset procedure. In that - * case, the above suggested code for enabling the SWO pin is not required - * in the application. - * - * @param[in] location - * A pin location used for SWO pin on the application in use. - ******************************************************************************/ -void DBG_SWOEnable(unsigned int location) -{ - int port; - int pin; - -#if defined(GPIO_SWV_PORT) - - port = GPIO_SWV_PORT; - pin = GPIO_SWV_PIN; - -#else - EFM_ASSERT(location < AFCHANLOC_MAX); - #if defined (AF_DBG_SWO_PORT) - port = AF_DBG_SWO_PORT(location); - pin = AF_DBG_SWO_PIN(location); - #elif defined (AF_DBG_SWV_PORT) - port = AF_DBG_SWV_PORT(location); - pin = AF_DBG_SWV_PIN(location); - - #else - #warning "AF debug port is not defined." - #endif -#endif - - /* Port/pin location not defined for the device. */ - if ((pin < 0) || (port < 0)) { - EFM_ASSERT(0); - return; - } - - /* Ensure that the auxiliary clock going to the Cortex debug trace module is enabled. */ -#if !defined(_SILICON_LABS_32B_SERIES_2) - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, false); -#endif - - /* Set the selected pin location for the SWO pin and enable it. */ - GPIO_DbgLocationSet(location); - GPIO_DbgSWOEnable(true); - - /* Configure the SWO pin for output. */ - GPIO_PinModeSet((GPIO_Port_TypeDef)port, pin, gpioModePushPull, 0); -} -#endif - -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) - -/***************************************************************************//** - * @brief - * Disable debug access. - * - * @cond DOXYDOC_S2_DEVICE - * @details - * SE interface is used to disable debug access. By choosing - * @ref dbgLockModePermanent, debug access is blocked permanently. SE disables - * the device erase command and thereafter disables debug access. - * @endcond - * @cond DOXYDOC_P2_DEVICE - * @ - * @details - * Debug access is blocked using debug lock word. On series 1 devices, - * if @ref dbgLockModePermanent is chosen, debug access is blocked - * permanently using AAP lock word. - * @endcond - * @param[in] lockMode - * Debug lock mode to be used. - * - * @cond !DOXYDOC_P1_DEVICE - * @warning - * If @ref dbgLockModePermanent is chosen as the lock mode, the debug port - * will be closed permanently and is irreversible. - * @endcond - ******************************************************************************/ -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode) -{ -#if defined(SEMAILBOX_PRESENT) - if (lockMode == dbgLockModeAllowErase) { - SE_debugLockApply(); - } else if (lockMode == dbgLockModePermanent) { - SE_deviceEraseDisable(); - SE_debugLockApply(); - } else { - /* Invalid input */ - EFM_ASSERT(0); - } -#else -#if defined(_SILICON_LABS_32B_SERIES_0) - if (lockMode != dbgLockModeAllowErase) { - EFM_ASSERT(0); - } -#else - if ((lockMode != dbgLockModeAllowErase) && (lockMode != dbgLockModePermanent)) { - EFM_ASSERT(0); - } -#endif - - bool wasLocked; - uint32_t lockWord = 0x0; - wasLocked = ((MSC->LOCK & _MSC_LOCK_MASK) != 0U); - MSC_Init(); - - uint32_t *dlw = (uint32_t*)(LOCKBITS_BASE + (127 * 4)); - - if (*dlw == 0xFFFFFFFF) { - MSC_WriteWord(dlw, &lockWord, sizeof(lockWord)); - } -#if !defined(_SILICON_LABS_32B_SERIES_0) - uint32_t *alw = (uint32_t*)(LOCKBITS_BASE + (124 * 4)); - - if (lockMode == dbgLockModePermanent) { - if (*alw == 0xFFFFFFFF) { - MSC_WriteWord(alw, &lockWord, sizeof(lockWord)); - } - } -#endif - - if (wasLocked) { - MSC_Deinit(); - } -#endif -} - -#endif /* defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) */ - -/** @} (end addtogroup dbg) */ -#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ +/***************************************************************************//** + * @file + * @brief Debug (DBG) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_dbg.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "em_gpio.h" +#include "em_msc.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_se.h" +#endif + +/***************************************************************************//** + * @addtogroup dbg DBG - Debug + * @brief Debug (DBG) Peripheral API + * @details + * This module contains functions to control the DBG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The Debug Interface is used to program and debug + * Silicon Labs devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +/***************************************************************************//** + * @brief + * Enable Serial Wire Output (SWO) pin. + * + * @details + * The SWO pin (sometimes denoted SWV, serial wire viewer) allows for + * miscellaneous output to be passed from the Cortex-M3 debug trace module to + * an external debug probe. By default, the debug trace module and pin output + * may be disabled. + * + * Since the SWO pin is only useful when using a debugger, a suggested use + * of this function during startup may be: + * @verbatim + * if (DBG_Connected()) + * { + * DBG_SWOEnable(1); + * } + * @endverbatim + * By checking if the debugger is attached, a setup leading to a higher energy + * consumption when the debugger is attached can be avoided when not using + * a debugger. + * + * Another alternative may be to set the debugger tool chain to configure + * the required setup (similar to the content of this function) by some + * sort of toolchain scripting during its attach/reset procedure. In that + * case, the above suggested code for enabling the SWO pin is not required + * in the application. + * + * @param[in] location + * A pin location used for SWO pin on the application in use. + ******************************************************************************/ +void DBG_SWOEnable(unsigned int location) +{ + int port; + int pin; + +#if defined(GPIO_SWV_PORT) + + port = GPIO_SWV_PORT; + pin = GPIO_SWV_PIN; + +#else + EFM_ASSERT(location < AFCHANLOC_MAX); + #if defined (AF_DBG_SWO_PORT) + port = AF_DBG_SWO_PORT(location); + pin = AF_DBG_SWO_PIN(location); + #elif defined (AF_DBG_SWV_PORT) + port = AF_DBG_SWV_PORT(location); + pin = AF_DBG_SWV_PIN(location); + + #else + #warning "AF debug port is not defined." + #endif +#endif + + /* Port/pin location not defined for the device. */ + if ((pin < 0) || (port < 0)) { + EFM_ASSERT(0); + return; + } + + /* Ensure that the auxiliary clock going to the Cortex debug trace module is enabled. */ +#if !defined(_SILICON_LABS_32B_SERIES_2) + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, false); +#endif + + /* Set the selected pin location for the SWO pin and enable it. */ + GPIO_DbgLocationSet(location); + GPIO_DbgSWOEnable(true); + + /* Configure the SWO pin for output. */ + GPIO_PinModeSet((GPIO_Port_TypeDef)port, pin, gpioModePushPull, 0); +} +#endif + +#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) + +/***************************************************************************//** + * @brief + * Disable debug access. + * + * @cond DOXYDOC_S2_DEVICE + * @details + * SE interface is used to disable debug access. By choosing + * @ref dbgLockModePermanent, debug access is blocked permanently. SE disables + * the device erase command and thereafter disables debug access. + * @endcond + * @cond DOXYDOC_P2_DEVICE + * @ + * @details + * Debug access is blocked using debug lock word. On series 1 devices, + * if @ref dbgLockModePermanent is chosen, debug access is blocked + * permanently using AAP lock word. + * @endcond + * @param[in] lockMode + * Debug lock mode to be used. + * + * @cond !DOXYDOC_P1_DEVICE + * @warning + * If @ref dbgLockModePermanent is chosen as the lock mode, the debug port + * will be closed permanently and is irreversible. + * @endcond + ******************************************************************************/ +void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode) +{ +#if defined(SEMAILBOX_PRESENT) + if (lockMode == dbgLockModeAllowErase) { + SE_debugLockApply(); + } else if (lockMode == dbgLockModePermanent) { + SE_deviceEraseDisable(); + SE_debugLockApply(); + } else { + /* Invalid input */ + EFM_ASSERT(0); + } +#else +#if defined(_SILICON_LABS_32B_SERIES_0) + if (lockMode != dbgLockModeAllowErase) { + EFM_ASSERT(0); + } +#else + if ((lockMode != dbgLockModeAllowErase) && (lockMode != dbgLockModePermanent)) { + EFM_ASSERT(0); + } +#endif + + bool wasLocked; + uint32_t lockWord = 0x0; + wasLocked = ((MSC->LOCK & _MSC_LOCK_MASK) != 0U); + MSC_Init(); + + uint32_t *dlw = (uint32_t*)(LOCKBITS_BASE + (127 * 4)); + + if (*dlw == 0xFFFFFFFF) { + MSC_WriteWord(dlw, &lockWord, sizeof(lockWord)); + } +#if !defined(_SILICON_LABS_32B_SERIES_0) + uint32_t *alw = (uint32_t*)(LOCKBITS_BASE + (124 * 4)); + + if (lockMode == dbgLockModePermanent) { + if (*alw == 0xFFFFFFFF) { + MSC_WriteWord(alw, &lockWord, sizeof(lockWord)); + } + } +#endif + + if (wasLocked) { + MSC_Deinit(); + } +#endif +} + +#endif /* defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) */ + +/** @} (end addtogroup dbg) */ +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c index feadce5..af6b2cc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c @@ -1,4188 +1,4188 @@ -/***************************************************************************//** - * @file - * @brief Energy Management Unit (EMU) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include - -#include "em_emu.h" -#if defined(EMU_PRESENT) && (EMU_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include "em_core.h" -#include "em_system.h" -#include "em_ramfunc.h" - -#if defined(SL_CATALOG_METRIC_EM23_WAKE_PRESENT) -#include "sli_metric_em23_wake.h" -#include "sli_metric_em23_wake_config.h" -#endif - -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) -#include "sli_metric_em4_wake.h" -#endif - -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -/* Consistency check, since restoring assumes similar bit positions in */ -/* CMU OSCENCMD and STATUS regs. */ -#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) -#error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions -#endif -#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) -#error Conflict in HFXOENS and HFXOEN bitpositions -#endif -#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) -#error Conflict in LFRCOENS and LFRCOEN bitpositions -#endif -#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) -#error Conflict in LFXOENS and LFXOEN bitpositions -#endif - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ -#if defined(_SILICON_LABS_32B_SERIES_0) -/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ -#if defined(_EFM32_GECKO_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) -#define NON_WIC_INT_MASK_1 (~(0x0U)) - -#elif defined(_EFM32_TINY_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x001be323U)) -#define NON_WIC_INT_MASK_1 (~(0x0U)) - -#elif defined(_EFM32_GIANT_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) -#define NON_WIC_INT_MASK_1 (~(0x00000046U)) - -#elif defined(_EFM32_WONDER_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) -#define NON_WIC_INT_MASK_1 (~(0x00000046U)) - -#elif defined(_EFM32_ZERO_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x00005c6bU)) -#define NON_WIC_INT_MASK_1 (~(0x00000000U)) - -#elif defined(_EFM32_HAPPY_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x00085c6bU)) -#define NON_WIC_INT_MASK_1 (~(0x00000000U)) - -#endif -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ - || (defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) -// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. -#define ERRATA_FIX_EMU_E110_ENABLE -#endif - -/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) -#define ERRATA_FIX_EMU_E108_ENABLE -#endif - -/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_EMU_E208_ENABLE -#endif - -/* Enable FETCNT tuning errata fix. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE -#endif - -/* Enable LN handshake errata fix. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE -typedef enum { - errataFixDcdcHsInit, - errataFixDcdcHsTrimSet, - errataFixDcdcHsBypassLn, - errataFixDcdcHsLnWaitDone -} errataFixDcdcHs_TypeDef; -static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; -#endif - -/* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S - * while powering the analog peripherals from DVDD, firmware must switch - * over to powering the analog peripherals from AVDD and delay the EM4S entry - * with 30 us. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -#define ERRATA_FIX_EM4S_DELAY_ENTRY -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ - && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) -/* EMU_E220 DECBOD Errata fix. DECBOD Reset can occur - * during voltage scaling after EM2/3 wakeup. */ -#define ERRATA_FIX_EMU_E220_DECBOD_ENABLE -#define EMU_PORBOD (*(volatile uint32_t *) (EMU_BASE + 0x14C)) -#define EMU_PORBOD_GMC_CALIB_DISABLE (0x1UL << 31) -#endif - -/* Used to figure out if a memory address is inside or outside of a RAM block. - * A memory address is inside a RAM block if the address is greater than the - * RAM block address. */ -#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) - -/* RAM Block layout for various device families. Note that some devices - * have special layout in RAM0 and some devices have a special RAM block - * at the end of their block layout. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) -#define RAM1_BLOCKS 2U -#define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) -#define RAM0_BLOCKS 2U -#define RAM0_BLOCK_SIZE 0x4000U -#define RAM1_BLOCKS 2U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#define RAM0_BLOCKS 1U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB block -#define RAM1_BLOCKS 1U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB block -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) -#define RAM0_BLOCKS 8U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM1_BLOCKS 8U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 4U -#define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM1_BLOCKS 4U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 4U -#define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#define RAM0_BLOCKS 6U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) -/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ -#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) -#else -#define RAM0_END RAM_MEM_END -#endif - -#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) -#elif defined(CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#if !defined(PWRCFG_DCDCTODVDD_VMIN) -/** DCDCTODVDD output range maximum. */ -#define PWRCFG_DCDCTODVDD_VMIN 1800U -#endif -#if !defined(PWRCFG_DCDCTODVDD_VMAX) -/** DCDCTODVDD output range minimum. */ -#define PWRCFG_DCDCTODVDD_VMAX 3000U -#endif -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) || defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#define DCDC_LP_PFET_CNT 7 -#define DCDC_LP_NFET_CNT 7 -#endif - -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) -#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/* Translate fields with different names across platform generations to common names. */ -#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT -#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT -#endif -#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT -#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT -#endif - -/* Disable LP mode hysteresis in the state machine control. */ -#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) -/* Comparator threshold on the high side. */ -#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) -#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) - -#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/* EMU DCDC MODE set timeout. */ -#define EMU_DCDC_MODE_SET_TIMEOUT 1000000 -#endif -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) -#define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) -#define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) -#define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/* As the energy mode at which a temperature measurement was taken at is - * not known, the chosen constant for the TEMPCO calculation is midway between - * the EM0/EM1 constant and the EM2/EM3/EM4 constant. - */ -#define EMU_TEMPCO_CONST (0.273f) -#endif - -#define EMU_EM4_ENTRY_WAIT_LOOPS 200 - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -/* Static user configuration. */ -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -static uint16_t dcdcMaxCurrent_mA; -static uint16_t dcdcEm01LoadCurrent_mA; -static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; -#endif -#if defined(EMU_VSCALE_EM01_PRESENT) -static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; -#endif - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/* Convert from level to EM0/1 command bit */ -__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - return EMU_CMD_EM01VSCALE1 << ((uint32_t)level - _EMU_STATUS_VSCALE_VSCALE1); -#else - return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); -#endif -} -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); -SL_RAMFUNC_DEFINITION_BEGIN -static void __attribute__ ((noinline)) ramWFI(void) -{ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) - __WFI(); // Enter EM2 or EM3 - if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { - for (volatile int i = 0; i < 6; i++) { - } // Dummy wait loop ... - } - -#else - __WFI(); // Enter EM2 or EM3 -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif - *(volatile uint32_t*)4; // Clear faulty read data after wakeup -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif -} -SL_RAMFUNC_DEFINITION_END -#endif - -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) -SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); -SL_RAMFUNC_DEFINITION_BEGIN -static void __attribute__ ((noinline)) ramWFI(void) -{ - /* Second part of EMU_E220 DECBOD Errata fix. Calibration needs to be disabled - * quickly when coming out of EM2/EM3. Ram execution is needed to meet timing. - * Calibration is re-enabled after voltage scaling completes. */ - uint32_t temp = EMU_PORBOD | EMU_PORBOD_GMC_CALIB_DISABLE; - __WFI(); - EMU_PORBOD = temp; -} -SL_RAMFUNC_DEFINITION_END -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) -/***************************************************************************//** - * @brief - * Save/restore/update oscillator, core clock and voltage scaling configuration on - * EM2 or EM3 entry/exit. - * - * @details - * Hardware may automatically change the oscillator and the voltage scaling configuration - * when going into or out of an energy mode. Static data in this function keeps track of - * such configuration bits and is used to restore state if needed. - * - ******************************************************************************/ -typedef enum { - emState_Save, /* Save EMU and CMU state. */ - emState_Restore, /* Restore and unlock. */ -} emState_TypeDef; - -static void emState(emState_TypeDef action) -{ - uint32_t oscEnCmd; - uint32_t cmuLocked; - static uint32_t cmuStatus; - static CMU_Select_TypeDef hfClock; -#if defined(EMU_VSCALE_PRESENT) - static uint8_t vScaleStatus; - static uint32_t hfrcoCtrl; -#endif - - /* Save or update state. */ - if (action == emState_Save) { - /* Save configuration. */ - cmuStatus = CMU->STATUS; - hfClock = CMU_ClockSelectGet(cmuClock_HF); -#if defined(EMU_VSCALE_PRESENT) - /* Save vscale. */ - EMU_VScaleWait(); - vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) - >> _EMU_STATUS_VSCALE_SHIFT); - hfrcoCtrl = CMU->HFRCOCTRL; -#endif - } else { /* Restore state. */ - /* Apply saved configuration. */ -#if defined(EMU_VSCALE_PRESENT) -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == true) - /* Restore voltage scaling level if LDO regulator is on. */ -#endif - { - /* Restore EM0 and 1 voltage scaling level. - @ref EMU_VScaleWait() is called later, - just before HF clock select is set. */ - EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); - } -#endif - /* CMU registers may be locked. */ - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); - -#if defined(_CMU_OSCENCMD_MASK) - /* AUXHFRCO are automatically disabled (except if using debugger). */ - /* HFRCO, USHFRCO and HFXO are automatically disabled. */ - /* LFRCO/LFXO may be disabled by SW in EM3. */ - /* Restore according to status prior to entering energy mode. */ - oscEnCmd = 0; - oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U - ? CMU_OSCENCMD_HFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U - ? CMU_OSCENCMD_AUXHFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U - ? CMU_OSCENCMD_LFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U - ? CMU_OSCENCMD_HFXOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U - ? CMU_OSCENCMD_LFXOEN : 0U; -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U - ? CMU_OSCENCMD_USHFRCOEN : 0U; -#endif - CMU->OSCENCMD = oscEnCmd; -#endif - -#if defined(_EMU_STATUS_VSCALE_MASK) - /* Wait for upscale to complete and then restore selected clock. */ - EMU_VScaleWait(); - if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { - /* Restore HFRCO frequency which was automatically adjusted by hardware. */ - while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { - } - CMU->HFRCOCTRL = hfrcoCtrl; - if (hfClock == cmuSelect_HFRCO) { - /* Optimize wait state after EM2/EM3 wakeup because hardware has - * modified them. */ - CMU_UpdateWaitStates(SystemHfrcoFreq, (int)EMU_VScaleGet()); - } - } -#endif - - switch (hfClock) { - case cmuSelect_LFXO: - CMU_CLOCK_SELECT_SET(HF, LFXO); - break; - case cmuSelect_LFRCO: - CMU_CLOCK_SELECT_SET(HF, LFRCO); - break; - case cmuSelect_HFXO: - CMU_CLOCK_SELECT_SET(HF, HFXO); - break; -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - case cmuSelect_USHFRCODIV2: - CMU_CLOCK_SELECT_SET(HF, USHFRCODIV2); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case cmuSelect_HFRCODIV2: - CMU_CLOCK_SELECT_SET(HF, HFRCODIV2); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case cmuSelect_CLKIN0: - CMU_CLOCK_SELECT_SET(HF, CLKIN0); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case cmuSelect_USHFRCO: - CMU_CLOCK_SELECT_SET(HF, USHFRCO); - break; -#endif - } - -#if defined(_CMU_OSCENCMD_MASK) - /* If HFRCO was disabled before entering Energy Mode, turn it off again */ - /* as it is automatically enabled by wake up */ - if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { - CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; - } -#endif - - /* Restore CMU register locking */ - if (cmuLocked != 0U) { - CMU_Lock(); - } - } -} -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) -/* Get enable conditions for errata EMU_E107 fix. */ -__STATIC_INLINE bool getErrataFixEmuE107En(void) -{ -#if defined(_EFM32_HAPPY_FAMILY) \ - || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_WONDER_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) - // all revisions have the errata - return true; -#else - /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation - * would be needed in this case. - */ - uint16_t majorMinorRev; - - /* CHIP MAJOR bit [3:0]. */ - majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) - << 8; - /* CHIP MINOR bit [7:4]. */ - majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) - << 4; - /* CHIP MINOR bit [3:0]. */ - majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; - -#if defined(_EFM32_GECKO_FAMILY) - // all GECKO revisions except Revision E have the errata - return (majorMinorRev <= 0x0103); -#elif defined(_EFM32_GIANT_FAMILY) - // all LEOPARD GECKO (Major = 0x01 Or 0x02) revisions have the errata - // all GIANT GECKO (Major = 0x01) revisions except Revision E have the errata - return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204) || (majorMinorRev == 0x0205); -#else - /* Invalid configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; -#endif -#endif /* #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) #else */ -} -#endif /* #if defined(ERRATA_FIX_EMU_E107_ENABLE) */ - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -/* Get enable conditions for errata EMU_E110 fix. */ -__STATIC_INLINE bool getErrataFixEmuE110En(void) -{ - /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation - * would be needed in this case. - */ - uint16_t majorMinorRev; - - /* CHIP MAJOR bit [3:0]. */ - majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) - << 8; - /* CHIP MINOR bit [7:4]. */ - majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) - << 4; - /* CHIP MINOR bit [3:0]. */ - majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_ZERO_FAMILY) - return (majorMinorRev == 0x0100); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - return ((majorMinorRev == 0x0100 || majorMinorRev == 0x0101)); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_WONDER_FAMILY) - return (majorMinorRev == 0x0100); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) - return (majorMinorRev == 0x0204); -#else - /* Invalid configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; -#endif -} -#endif /* #if defined(ERRATA_FIX_EMU_E110_ENABLE) */ - -/* LP prepare / LN restore P/NFET count. */ -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) -static void currentLimitersUpdate(void); -static void dcdcFetCntSet(bool lpModeSet) -{ - uint32_t tmp; - static uint32_t emuDcdcMiscCtrlReg; - - if (lpModeSet) { - emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; - tmp = EMU->DCDCMISCCTRL - & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); - tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) - | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); - EMU->DCDCMISCCTRL = tmp; - currentLimitersUpdate(); - } else { - EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; - currentLimitersUpdate(); - } -} -#endif - -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) -static void dcdcHsFixLnBlock(void) -{ - if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) - || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { - /* Wait for LNRUNNING */ - if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { - while (!(EMU_DCDCSTATUS & (0x1 << 16))) { - } - } - errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; - } -} -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) -/* Configure EMU and CMU for EM2 and 3 voltage downscale. */ -static void vScaleDownEM23Setup(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - /* Wait until previous scaling is done. */ - EMU_VScaleWait(); - - uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; - uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; - - /* Inverse coding. */ - if (em23vs > em01vs) { - EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) - /* Set RAM wait states for safe EM2 wakeup. */ - BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); -#endif - } else { - EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; - } -} - -/* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ -static void vScaleAfterWakeup(void) -{ - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 - * entry if voltage scaling in EM2/EM3 is enabled. The hardware would - * then update the HFRCO frequency to 19 MHz automatically. */ - uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) - >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; - if (freqRange == 0x08U) { - SystemHfrcoFreq = 19000000; - } - } -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -typedef enum { - dpllState_Save, /* Save DPLL state. */ - dpllState_Restore, /* Restore DPLL. */ -} dpllState_TypeDef; - -/***************************************************************************//** - * @brief - * Save or restore DPLL state. - * - * @param[in] action - * Value to indicate saving DPLL state or restoring its state. - * - * @note - * The function is used in EMU_Save() and EMU_Restore() to handle the - * DPLL state before entering EM2 or EM3 and after exiting EM2 or EM3. - * The function is required for the EFR32xG22 and EFR32xG27 families. - * On those families devices, the DPLL is disabled automatically when - * entering EM2, EM3. But exiting EM2, EM3 won't re-enable automatically - * the DPLL. Hence, the software needs to re-enable the DPLL upon EM2/3 - * exit. - ******************************************************************************/ -static void dpllState(dpllState_TypeDef action) -{ - CMU_ClkDiv_TypeDef div; - static uint32_t dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - - if (action == dpllState_Save) { - dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; - if (DPLL0->EN == DPLL_EN_EN) { - /* DPLL is in use, save reference clock selection. */ - dpllRefClk = CMU->DPLLREFCLKCTRL; - } - } else { /* Restore */ - if ((dpllRefClk != CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED) - && (DPLL0->EN != DPLL_EN_EN)) { - /* Restore DPLL reference clock selection. */ - CMU->DPLLREFCLKCTRL = dpllRefClk; - /* Only wait for DPLL lock if HFRCODPLL is used as SYSCLK. */ - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - /* Set HCLK prescaler to safe value to avoid overclocking while locking. */ - div = CMU_ClockDivGet(cmuClock_HCLK); - if (div == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 2U); - } - - /* Relock DPLL and wait for ready. */ - DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; - DPLL0->EN_SET = DPLL_EN_EN; - while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { - } - - /* Restore HCLK prescaler. */ - if (div == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 1U); - } - } else { - /* Relock DPLL and exit without waiting for ready. */ - DPLL0->EN_SET = DPLL_EN_EN; - } - } - } -} -#endif - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup emu EMU - Energy Management Unit - * @brief Energy Management Unit (EMU) Peripheral API - * @details - * This module contains functions to control the EMU peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes - * in Silicon Labs microcontrollers. - * @{ - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 0 and 1 configuration. - * - * @param[in] em01Init - * Energy Mode 0 and 1 configuration structure. - ******************************************************************************/ -void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) -{ - vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = - em01Init->vScaleEM01LowPowerVoltageEnable; - EMU_VScaleEM01ByClock(0, true); -} -#endif - -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 2 and 3 configuration. - * - * @param[in] em23Init - * Energy Mode 2 and 3 configuration structure. - ******************************************************************************/ -void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) -{ -#if defined(_EMU_CTRL_EMVREG_MASK) - EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) - : (EMU->CTRL & ~EMU_CTRL_EMVREG); -#elif defined(_EMU_CTRL_EM23VREG_MASK) - EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) - : (EMU->CTRL & ~EMU_CTRL_EM23VREG); -#else - (void)em23Init; -#endif - -#if defined(EMU_VSCALE_PRESENT) - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) - | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); -#if defined(CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) - if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { - /* Voltage scaling is not compatible with HFXO auto start and select. */ - EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); - } -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Energy mode 2/3 pre-sleep hook function. - * - * @details - * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions - * just prior to execution of the WFI instruction. The function implementation - * does not perform anything, but it is SL_WEAK so that it can be re- - * implemented in application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM23PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 2/3 pre-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM23PresleepHook() but is reserved - * for EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM23PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Energy mode 2/3 post-sleep hook function. - * - * @details - * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions - * just after wakeup from the WFI instruction. The function implementation - * does not perform anything, but it is SL_WEAK so that it can be re- - * implemented in application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM23PostsleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 2/3 post-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM23PostsleepHook() but is reserved - * for EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM23PostsleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Enter energy mode 2 (EM2). - * - * @details - * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO - * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering - * EM0, HFRCO is re-enabled and the core will be clocked by the configured - * HFRCO band. This ensures a quick wakeup from EM2. - * - * However, prior to entering EM2, the core may have been using another - * oscillator than HFRCO. The @p restore parameter gives the user the option - * to restore all HF oscillators according to state prior to entering EM2, - * as well as the clock used to clock the core. This restore procedure is - * handled by SW. However, since handled by SW, it will not be restored - * before completing the interrupt function(s) waking up the core! - * - * @note - * If restoring core clock to use the HFXO oscillator, which has been - * disabled during EM2 mode, this function will stall until the oscillator - * has stabilized. Stalling time can be reduced by adding interrupt - * support detecting stable oscillator, and an asynchronous switch to the - * original oscillator. See CMU documentation. Such a feature is however - * outside the scope of the implementation in this function. - * @note - * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature - * can not be used. - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - * @par - * If HFXO is re-enabled by this function, and NOT used to clock the core, - * this function will not wait for HFXO to stabilize. This must be considered - * by the application if trying to use features relying on that oscillator - * upon return. - * @par - * If a debugger is attached, the AUXHFRCO will not be disabled if enabled - * upon entering EM2. It will thus remain enabled when returning to EM0 - * regardless of the @p restore parameter. - * @par - * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(), - * the automatic starting and selecting of the core clocks will be done, - * regardless of the @p restore parameter, when waking up on the wakeup - * sources corresponding to the autostart and select setting. - * @par - * If voltage scaling is supported, the restore parameter is true and the EM0 - * voltage scaling level is set higher than the EM2 level, then the EM0 level is - * also restored. - * @par - * On Series 2 Config 2 devices (EFRxG22), this function will also relock the - * DPLL if the DPLL is used and @p restore is true. - * - * Note that the hardware will automatically update the HFRCO frequency in the - * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the - * restore argument to this function is true then software will restore the - * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is - * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and - * all wait states are at a safe value. - * - * @param[in] restore - * @li true - save and restore oscillators, clocks and voltage scaling, see - * function details. - * @li false - do not save and restore oscillators and clocks, see function - * details. - * @par - * The @p restore option should only be used if all clock control is done - * via the CMU API. - ******************************************************************************/ -void EMU_EnterEM2(bool restore) -{ -#if defined(SLI_METRIC_EM2_HOOK) - sli_metric_em23_wake_init(SLI_INIT_EM2_WAKE); -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - bool errataFixEmuE107En; - uint32_t nonWicIntEn[2]; -#endif - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - bool errataFixEmuE110En; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Save); - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Only save EMU and CMU state if restored on wake-up. */ - if (restore) { - emState(emState_Save); - } -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - vScaleDownEM23Setup(); -#endif - - /* Enter Cortex deep sleep mode. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. - Disable the enabled non-WIC interrupts. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - errataFixEmuE107En = getErrataFixEmuE107En(); - if (errataFixEmuE107En) { - nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; - NVIC->ICER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; - NVIC->ICER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - - EMU_EM23PresleepHook(); - EMU_EFPEM23PresleepHook(); -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - errataFixEmuE110En = getErrataFixEmuE110En(); - if (errataFixEmuE110En) { -#endif - CORE_CRITICAL_SECTION(ramWFI(); ) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -} else { - __WFI(); -} -#endif -#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - // Apply errata fix if voltage scaling in EM2 is used. - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - CORE_CRITICAL_SECTION(ramWFI(); ) - } else { - __WFI(); - } -#else - __WFI(); -#endif - EMU_EFPEM23PostsleepHook(); - EMU_EM23PostsleepHook(); - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(false); -#endif - - /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - if (errataFixEmuE107En) { - NVIC->ISER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - NVIC->ISER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Restore oscillators/clocks and voltage scaling if supported. */ - if (restore) { - emState(emState_Restore); - } -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - else { - vScaleAfterWakeup(); - } -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled - * after voltage scaling completes. */ - EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); -#endif -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Restore); - } -#endif - - if (!restore) { - /* If not restoring, and the original clock was not HFRCO, the CMSIS */ - /* core clock variable must be updated since HF clock has changed */ - /* to HFRCO. */ - SystemCoreClockUpdate(); - } -} - -/***************************************************************************//** - * @brief - * Enter energy mode 3 (EM3). - * - * @details - * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, - * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, - * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When - * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the - * configured HFRCO band. This ensures a quick wakeup from EM3. - * - * However, prior to entering EM3, the core may have been using an - * oscillator other than HFRCO. The @p restore parameter gives the user the option - * to restore all HF/LF oscillators according to state prior to entering EM3, - * as well as the clock used to clock the core. This restore procedure is - * handled by software. However, since it is handled by software, it will not be restored - * before completing the interrupt function(s) waking up the core! - * - * @note - * If restoring core clock to use an oscillator other than HFRCO, this - * function will stall until the oscillator has stabilized. Stalling time - * can be reduced by adding interrupt support detecting stable oscillator, - * and an asynchronous switch to the original oscillator. See CMU - * documentation. This feature is, however, outside the scope of the - * implementation in this function. - * @note - * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature - * can't be used. - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - * @par - * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock - * the core, this function will not wait for those oscillators to stabilize. - * This must be considered by the application if trying to use features - * relying on those oscillators upon return. - * @par - * If a debugger is attached, the AUXHFRCO will not be disabled if enabled - * upon entering EM3. It will, therefore, remain enabled when returning to EM0 - * regardless of the @p restore parameter. - * @par - * If voltage scaling is supported, the restore parameter is true and the EM0 - * voltage scaling level is set higher than the EM3 level, then the EM0 level is - * also restored. - * @par - * On Series 2 Config 2 devices (EFRxG22), this function will also relock the - * DPLL if the DPLL is used and @p restore is true. - * - * @param[in] restore - * @li true - save and restore oscillators, clocks and voltage scaling, see - * function details. - * @li false - do not save and restore oscillators and clocks, see function - * details. - * @par - * The @p restore option should only be used if all clock control is done - * via the CMU API. - ******************************************************************************/ -void EMU_EnterEM3(bool restore) -{ -#if defined(SLI_METRIC_EM3_HOOK) - sli_metric_em23_wake_init(SLI_INIT_EM3_WAKE); -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - bool errataFixEmuE107En; - uint32_t nonWicIntEn[2]; -#endif - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - bool errataFixEmuE110En; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Save); - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Only save EMU and CMU state if restored on wake-up. */ - if (restore) { - emState(emState_Save); - } -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - vScaleDownEM23Setup(); -#endif - -#if defined(_CMU_OSCENCMD_MASK) - uint32_t cmuLocked; - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); - - /* Disable LF oscillators. */ - CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; - - /* Restore CMU register locking. */ - if (cmuLocked != 0U) { - CMU_Lock(); - } -#endif - - /* Enter Cortex deep sleep mode. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. - Disable the enabled non-WIC interrupts. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - errataFixEmuE107En = getErrataFixEmuE107En(); - if (errataFixEmuE107En) { - nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; - NVIC->ICER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; - NVIC->ICER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - - EMU_EM23PresleepHook(); -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - errataFixEmuE110En = getErrataFixEmuE110En(); - if (errataFixEmuE110En) { -#endif - CORE_CRITICAL_SECTION(ramWFI(); ) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -} else { - __WFI(); -} -#endif -#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - // Apply errata fix if voltage scaling in EM2 is used. - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - CORE_CRITICAL_SECTION(ramWFI(); ) - } else { - __WFI(); - } -#else - __WFI(); -#endif - EMU_EM23PostsleepHook(); - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(false); -#endif - - /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - if (errataFixEmuE107En) { - NVIC->ISER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - NVIC->ISER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Restore oscillators/clocks and voltage scaling if supported. */ - if (restore) { - emState(emState_Restore); - } -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - else { - vScaleAfterWakeup(); - } -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled - * after voltage scaling completes. */ - EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); -#endif -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Restore); - } -#endif - - if (!restore) { - /* If not restoring, and the original clock was not HFRCO, the CMSIS */ - /* core clock variable must be updated since HF clock has changed */ - /* to HFRCO. */ - SystemCoreClockUpdate(); - } -} - -/***************************************************************************//** - * @brief - * Save the CMU HF clock select state, oscillator enable, and voltage scaling - * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called - * with the restore parameter set to false. Calling this function is - * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the - * restore parameter set to true, but it allows the state to be saved without - * going to sleep. The state can be restored manually by calling - * @ref EMU_Restore(). - ******************************************************************************/ -void EMU_Save(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Save); -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - dpllState(dpllState_Save); -#endif -} - -/***************************************************************************//** - * @brief - * Restore CMU HF clock select state, oscillator enable, and voltage scaling - * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called - * with the restore parameter set to false. Calling this function is - * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the - * restore parameter set to true, but it allows the application to evaluate the - * wakeup reason before restoring state. - ******************************************************************************/ -void EMU_Restore(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Restore); -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - dpllState(dpllState_Restore); -#endif -} - -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 4 configuration. - * - * @param[in] em4Init - * Energy Mode 4 configuration structure. - ******************************************************************************/ -void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) -{ -#if defined(_EMU_EM4CONF_MASK) - /* Initialization for platforms with EMU->EM4CONF register. */ - uint32_t em4conf = EMU->EM4CONF; - - /* Clear fields that will be reconfigured. */ - em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK - | _EMU_EM4CONF_OSC_MASK - | _EMU_EM4CONF_BURTCWU_MASK - | _EMU_EM4CONF_VREGEN_MASK - | _EMU_EM4CONF_BUBODRSTDIS_MASK); - - /* Configure new settings. */ - em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) - | (em4Init->osc) - | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) - | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) - | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); - - /* Apply configuration. Note that lock can be set after this stage. */ - EMU->EM4CONF = em4conf; - -#elif defined(_EMU_EM4CTRL_EM4STATE_MASK) - /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ - - uint32_t em4ctrl = EMU->EM4CTRL; - - em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK - | _EMU_EM4CTRL_RETAINLFRCO_MASK - | _EMU_EM4CTRL_RETAINULFRCO_MASK - | _EMU_EM4CTRL_EM4STATE_MASK - | _EMU_EM4CTRL_EM4IORETMODE_MASK); - - em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) - | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) - | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) - | (em4Init->em4State == emuEM4Hibernate - ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) - | ((uint32_t)em4Init->pinRetentionMode); - - EMU->EM4CTRL = em4ctrl; -#elif defined(_EMU_EM4CTRL_MASK) - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | (uint32_t)em4Init->pinRetentionMode; -#endif - -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) - | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Energy mode 4 pre-sleep hook function. - * - * @details - * This function is called by @ref EMU_EnterEM4() just prior to the sequence - * of writes to put the device in EM4. The function implementation does not - * perform anything, but it is SL_WEAK so that it can be re-implemented in - * application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM4PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 4 pre-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM4PresleepHook() but is reserved for - * EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM4PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 (EM4). - * - * @note - * Only a power on reset or external reset pin can wake the device from EM4. - ******************************************************************************/ -void EMU_EnterEM4(void) -{ -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) - sli_metric_em4_wake_init(); -#endif - int i; - -#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) - uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); -#else - uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) - | (2U << _EMU_CTRL_EM4CTRL_SHIFT); - uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) - | (3U << _EMU_CTRL_EM4CTRL_SHIFT); -#endif - - /* Make sure that the register write lock is disabled. */ - EMU_Unlock(); - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should - * switch to bypass mode before entering EM4S. Other devices handle this - * automatically at the hardware level. */ - if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { - uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; - if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE - || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { - EMU_DCDCModeSet(emuDcdcMode_Bypass); - } - } -#endif - -#if defined(_DCDC_IF_EM4ERR_MASK) - /* Make sure DCDC Mode is not modified, from this point forward, - * by another code section. */ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - - /* Workaround for bug that may cause a Hard Fault on EM4 entry */ - CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); - /* The buck DC-DC is available in all energy modes except for EM4. - * The DC-DC converter must first be turned off and switched over to bypass mode. */ -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ - || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) - EMU_DCDCModeSet(emuDcdcMode_Bypass); -#endif -#endif - -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) - if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { - /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. - * Full description of errata fix can be found in the errata document. */ - __disable_irq(); - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; - *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); - *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); - } -#endif - -#if defined(ERRATA_FIX_EMU_E108_ENABLE) - /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ - __disable_irq(); - *(volatile uint32_t *)0x400C80E4 = 0; -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - -#if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) - /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ - if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { - if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { - BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); - /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement - * before entering EM4. */ - uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV4; - while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { - } - CMU->HFRCOCTRL = freqCal; - CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; - while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { - } - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; - __NOP(); - } - } -#endif - - EMU_EM4PresleepHook(); - EMU_EFPEM4PresleepHook(); - - for (i = 0; i < 4; i++) { -#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) - EMU->EM4CTRL = em4seq2; - EMU->EM4CTRL = em4seq3; - } - EMU->EM4CTRL = em4seq2; -#else - EMU->CTRL = em4seq2; - EMU->CTRL = em4seq3; - } - EMU->CTRL = em4seq2; -#endif - -#if defined(_DCDC_IF_EM4ERR_MASK) - EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 (EM4). - * - * @details - * This function waits after the EM4 entry request to make sure the CPU - * is properly shutdown or the EM4 entry failed. - * - * @note - * Only a power on reset or external reset pin can wake the device from EM4. - ******************************************************************************/ -void EMU_EnterEM4Wait(void) -{ - EMU_EnterEM4(); - - // The EM4 entry waiting loop should take 4 cycles by loop minimally (Compiler dependent). - // We would then wait for (EMU_EM4_ENTRY_WAIT_LOOPS * 4) clock cycles. - for (uint16_t i = 0; i < EMU_EM4_ENTRY_WAIT_LOOPS; i++) { - __NOP(); - } -} - -#if defined(_EMU_EM4CTRL_MASK) -/***************************************************************************//** - * @brief - * Enter energy mode 4 hibernate (EM4H). - * - * @note - * Retention of clocks and GPIO in EM4 can be configured using - * @ref EMU_EM4Init before calling this function. - ******************************************************************************/ -void EMU_EnterEM4H(void) -{ -#if defined(_EMU_EM4CTRL_EM4STATE_MASK) - BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); -#endif - EMU_EnterEM4(); -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 shutoff (EM4S). - * - * @note - * Retention of clocks and GPIO in EM4 can be configured using - * @ref EMU_EM4Init before calling this function. - ******************************************************************************/ -void EMU_EnterEM4S(void) -{ -#if defined(_EMU_EM4CTRL_EM4STATE_MASK) - BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); -#endif - EMU_EnterEM4(); -} -#endif - -/***************************************************************************//** - * @brief - * Power down memory block. - * - * @param[in] blocks - * Specifies a logical OR of bits indicating memory blocks to power down. - * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot - * be disabled. See the reference manual for available - * memory blocks for a device. - * - * @note - * Only a POR reset can power up the specified memory block(s) after power down. - * - * @deprecated - * This function is deprecated, use @ref EMU_RamPowerDown() instead which - * maps a user provided memory range into RAM blocks to power down. - ******************************************************************************/ -void EMU_MemPwrDown(uint32_t blocks) -{ -#if defined(_EMU_MEMCTRL_MASK) - EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; -#elif defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; -#else - (void)blocks; -#endif -} - -/***************************************************************************//** - * @brief - * Power down RAM memory blocks. - * - * @details - * This function will power down all the RAM blocks that are within a given - * range. The RAM block layout is different between device families, so this - * function can be used in a generic way to power down a RAM memory region - * which is known to be unused. - * - * This function will only power down blocks which are completely enclosed - * by the memory range given by [start, end). - * - * This is an example to power down all RAM blocks except the first - * one. The first RAM block is special in that it cannot be powered down - * by the hardware. The size of the first RAM block is device-specific. - * See the reference manual to find the RAM block sizes. - * - * @code - * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); - * @endcode - * - * @note - * Only a reset can power up the specified memory block(s) after power down - * on a series 0 device. The specified memory block(s) will stay off - * until a call to EMU_RamPowerUp() is done on series 1/2. - * - * @param[in] start - * The start address of the RAM region to power down. This address is - * inclusive. - * - * @param[in] end - * The end address of the RAM region to power down. This address is - * exclusive. If this parameter is 0, all RAM blocks contained in the - * region from start to the upper RAM address will be powered down. - ******************************************************************************/ -void EMU_RamPowerDown(uint32_t start, uint32_t end) -{ - uint32_t mask = 0; - (void) start; - - if (end == 0U) { - end = SRAM_BASE + SRAM_SIZE; - } - - // Check to see if something in RAM0 can be powered down. - if (end > RAM0_END) { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 - // Block 0 is 16 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 - // Block 0 is 4 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. - // This condition happens when the block 0 disable bit flag is available in the retention control register. - for (unsigned i = 1; i < RAM0_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i); - } -#elif defined(RAM0_BLOCKS) - // These platforms have equally-sized RAM blocks and block 0 cannot be powered down. - for (unsigned i = 1; i < RAM0_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); - } -#endif - } - - // Power down the selected blocks. -#if defined(_EMU_MEMCTRL_MASK) - EMU->MEMCTRL = EMU->MEMCTRL | mask; -#elif defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = EMU->RAM0CTRL | mask; -#elif defined(_SILICON_LABS_32B_SERIES_2) -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - SYSCFG_maskDmem0RetnCtrl(mask); -#else - // These devices are unable to power down RAM blocks. - (void) mask; - (void) start; -#endif - -#if defined(RAM1_MEM_END) - mask = 0; - if (end > RAM1_MEM_END) { - for (unsigned i = 0; i < RAM1_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; - } - } - EMU->RAM1CTRL |= mask; -#endif - -#if defined(RAM2_MEM_END) - mask = 0; - if (end > RAM2_MEM_END) { - for (unsigned i = 0; i < RAM2_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; - } - } - EMU->RAM2CTRL |= mask; -#endif -} - -/***************************************************************************//** - * @brief - * Power up all available RAM memory blocks. - * - * @details - * This function will power up all the RAM blocks on a device, this means - * that the RAM blocks are retained in EM2/EM3. Note that this functionality - * is not supported on Series 0 devices. Only a reset will power up the RAM - * blocks on a series 0 device. - ******************************************************************************/ -void EMU_RamPowerUp(void) -{ -#if defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = 0x0UL; -#endif -#if defined(_EMU_RAM1CTRL_MASK) - EMU->RAM1CTRL = 0x0UL; -#endif -#if defined(_EMU_RAM2CTRL_MASK) - EMU->RAM2CTRL = 0x0UL; -#endif -#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - SYSCFG_zeroDmem0RetnCtrl(); -#endif -} - -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -/***************************************************************************//** - * @brief - * Set EM2 3 peripheral retention control. - * - * @param[in] periMask - * A peripheral select mask. Use | operator to select multiple peripherals, for example - * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. - * @param[in] enable - * Peripheral retention enable (true) or disable (false). - * - * - * @note - * Only peripheral retention disable is currently supported. Peripherals are - * enabled by default and can only be disabled. - ******************************************************************************/ -void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) -{ - EFM_ASSERT(!enable); - EMU->EM23PERNORETAINCTRL = (uint32_t)periMask - & (uint32_t)emuPeripheralRetention_ALL; -} -#endif - -/***************************************************************************//** - * @brief - * Update EMU module with CMU oscillator selection/enable status. - * - * @deprecated - * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). - ******************************************************************************/ -void EMU_UpdateOscConfig(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Save); -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) && defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Energy mode 01 voltage scaling hook function. - * - * @param[in] voltage - * Voltage scaling level requested. - * - * @details - * This function is called by EMU_VScaleEM01 to let EFP know that voltage scaling - * is requested. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage) -{ - (void)voltage; -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Voltage scale in EM0 and 1 by clock frequency. - * - * @param[in] clockFrequency - * Use CMSIS HF clock if 0 or override to custom clock. Providing a - * custom clock frequency is required if using a non-standard HFXO - * frequency. - * @param[in] wait - * Wait for scaling to complete. - * - * @note - * This function is primarily needed by the @ref cmu. - ******************************************************************************/ -void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) -{ - uint32_t hfSrcClockFrequency; - -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - /* VSCALE frequency is HFSRCCLK. */ - if (clockFrequency == 0U) { -#if defined(_SILICON_LABS_32B_SERIES_2) - hfSrcClockFrequency = SystemSYSCLKGet(); -#else - uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT); - hfSrcClockFrequency = SystemHFClockGet() * hfPresc; -#endif - } else { - hfSrcClockFrequency = clockFrequency; - } - - /* Apply EM0 and 1 voltage scaling command. */ - if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable - && (hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); - } else { - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); - } -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Force voltage scaling in EM0 and 1 to a specific voltage level. - * - * @param[in] voltage - * Target VSCALE voltage level. - * @param[in] wait - * Wait for scaling to complete. - * - * @note - * This function is useful for upscaling before programming Flash from @ref msc - * and downscaling after programming is done. Flash programming is only supported - * at @ref emuVScaleEM01_HighPerformance. - * - * @note - * This function ignores vScaleEM01LowPowerVoltageEnable set from @ref - * EMU_EM01Init(). - ******************************************************************************/ -void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) -{ - uint32_t hfFreq; - uint32_t hfSrcClockFrequency; - -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - if (EMU_VScaleGet() == voltage) { - /* Voltage is already at the correct level. */ - return; - } - -#if defined(_SILICON_LABS_32B_SERIES_2) - (void)wait; - CORE_DECLARE_IRQ_STATE; - - hfFreq = SystemSYSCLKGet(); - hfSrcClockFrequency = hfFreq; - - if (voltage == emuVScaleEM01_LowPower) { - EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); - /* Update wait states before scaling down voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); - } - - CORE_ENTER_CRITICAL(); - EMU->IF_CLR = EMU_IF_VSCALEDONE; - EMU_EFPEM01VScale(voltage); - EMU->CMD = vScaleEM01Cmd(voltage); - - // Note that VSCALEDONE interrupt flag must be used instead of VSCALEBUSY - // because hardware does not set the VSCALEBUSY flag immediately. - while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) - && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { - EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); - // Wait for VSCALE completion. - // SRAM accesses will fault the core while scaling. - } - CORE_EXIT_CRITICAL(); - -#else - uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT); - hfFreq = SystemHFClockGet(); - hfSrcClockFrequency = hfFreq * hfPresc; - - if (voltage == emuVScaleEM01_LowPower) { - EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); - /* Update wait states before scaling down voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); - } - - EMU->CMD = vScaleEM01Cmd(voltage); - - if (wait) { - EMU_VScaleWait(); - } -#endif - - if (voltage == emuVScaleEM01_HighPerformance) { - /* Update wait states after scaling up voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_HIGH_PERFORMANCE); - } -} -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Configure Backup Power Domain settings. - * - * @param[in] bupdInit - * Backup power domain initialization structure. - ******************************************************************************/ -void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) -{ - uint32_t reg; - - /* Set the power connection configuration. */ - reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK - | _EMU_PWRCONF_VOUTSTRONG_MASK - | _EMU_PWRCONF_VOUTMED_MASK - | _EMU_PWRCONF_VOUTWEAK_MASK); - - reg |= bupdInit->resistor - | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) - | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) - | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); - - EMU->PWRCONF = reg; - - /* Set the backup domain inactive mode configuration. */ - reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); - reg |= (bupdInit->inactivePower); - EMU->BUINACT = reg; - - /* Set the backup domain active mode configuration. */ - reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); - reg |= (bupdInit->activePower); - EMU->BUACT = reg; - - /* Set the power control configuration */ - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK - | _EMU_BUCTRL_BODCAL_MASK - | _EMU_BUCTRL_STATEN_MASK - | _EMU_BUCTRL_EN_MASK); - - /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and - release reset. */ - reg |= bupdInit->probe - | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) - | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) - | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); - - /* Enable configuration. */ - EMU->BUCTRL = reg; - - /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ - EMU_BUPinEnable(bupdInit->enable); - - /* If enable is true, release BU reset. If not, keep reset asserted. */ - BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); -} - -/***************************************************************************//** - * @brief - * Configure the Backup Power Domain BOD Threshold value. - * @note - * These values are precalibrated. - * @param[in] mode Active or Inactive mode - * @param[in] value - ******************************************************************************/ -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) -{ - EFM_ASSERT(value < 8); - EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); - - switch (mode) { - case emuBODMode_Active: - EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) - | (value << _EMU_BUACT_BUEXTHRES_SHIFT); - break; - case emuBODMode_Inactive: - EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) - | (value << _EMU_BUINACT_BUENTHRES_SHIFT); - break; - } -} - -/***************************************************************************//** - * @brief - * Configure the Backup Power Domain BOD Threshold Range. - * @note - * These values are precalibrated. - * @param[in] mode Active or Inactive mode - * @param[in] value - ******************************************************************************/ -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) -{ - EFM_ASSERT(value < 4); - EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); - - switch (mode) { - case emuBODMode_Active: - EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) - | (value << _EMU_BUACT_BUEXRANGE_SHIFT); - break; - case emuBODMode_Inactive: - EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) - | (value << _EMU_BUINACT_BUENRANGE_SHIFT); - break; - } -} -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Configure Backup Power Domain settings. - * - * @param[in] buInit - * Backup power domain initialization structure. - ******************************************************************************/ -void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) -{ - uint32_t reg = 0; - - /* Set the backup power configuration. */ - reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); - reg |= (uint32_t)(buInit->inactivePwrCon); - reg |= (uint32_t)(buInit->activePwrCon); - reg |= (uint32_t)(buInit->pwrRes); - reg |= (uint32_t)(buInit->voutRes); - reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); - reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); - reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) -/***************************************************************************//** - * @brief - * Disable Main Backup Power Domain comparator. - * - * @param[in] disableMainBuComparator - * True to disable main BU comparator. - ******************************************************************************/ -void EMU_BUDisMaxCompSet(bool disableMainBuComparator) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); - reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -/***************************************************************************//** - * @brief - * Configure power connection configuration when not in Backup mode. - * - * @param[in] inactPwrCon - * Inactive power configuration. - ******************************************************************************/ -void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); - reg |= (uint32_t)(inactPwrCon); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -/***************************************************************************//** - * @brief - * Configure power connection configuration when in Backup mode. - * - * @param[in] actPwrCon - * Active power configuration. - ******************************************************************************/ -void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); - reg |= (uint32_t)(actPwrCon); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_PWRRES_MASK) -/***************************************************************************//** - * @brief - * Power domain resistor selection. - * - * @param[in] pwrRes - * Resistor selection. - ******************************************************************************/ -void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); - reg |= (uint32_t)(pwrRes); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -/***************************************************************************//** - * @brief - * B_VOUT resistor select. - * - * @param[in] resistorSel - * Resistor selection. - ******************************************************************************/ -void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); - reg |= (uint32_t)(resistorSel); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) -/***************************************************************************//** - * @brief - * Enable BU_VIN probing - * - * @param[in] enable - * True to enable BU_VIN probing. False to disable. - ******************************************************************************/ -void EMU_BUBuVinProbeEnSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); - reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_STATEN_MASK) -/***************************************************************************//** - * @brief - * Enable backup mode status export. - * - * @param[in] enable - * True to enable status export. False to disable. - ******************************************************************************/ -void EMU_BUStatEnSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); - reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_EN_MASK) -/***************************************************************************//** - * @brief - * Enable backup mode. - * - * @param[in] enable - * True to enable backup mode. False to disable. - ******************************************************************************/ -void EMU_BUEnableSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); - reg |= (enable << _EMU_BUCTRL_EN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Internal DCDC trim modes. */ -typedef enum { - dcdcTrimMode_EM234H_LP = 0, -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - dcdcTrimMode_EM01_LP, -#endif - dcdcTrimMode_LN, -} dcdcTrimMode_TypeDef; - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Load DCDC calibration constants from the DI page. A constant means that calibration - * data that does not change depending on other configuration parameters. - * - * @return - * False if calibration registers are locked. - ******************************************************************************/ -static bool dcdcConstCalibrationLoad(void) -{ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint32_t val; - volatile uint32_t *reg; - - /* DI calibration data in Flash. */ - volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); - volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); - volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); - volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); - volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); - volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); - - if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { - val = *(diCal_EMU_DCDCLNFREQCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLNVCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLPCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLPVCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCTRIM0 + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; - *reg = val; - - val = *(diCal_EMU_DCDCTRIM1 + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; - *reg = val; - - return true; - } - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - -#else - return true; -#endif -} - -/***************************************************************************//** - * @brief - * Set recommended and validated current optimization and timing settings. - * - ******************************************************************************/ -static void dcdcValidatedConfigSet(void) -{ - uint32_t lnForceCcm; - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint32_t dcdcTiming; - SYSTEM_ChipRevision_TypeDef rev; -#endif - - /* Enable duty cycling of the bias. */ - EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; - - /* Set low-noise RCO for LNFORCECCM configuration. - * LNFORCECCM is default 1 for EFR32 - * LNFORCECCM is default 0 for EFM32 - */ - lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - if (lnForceCcm != 0U) { - /* 7 MHz is recommended for LNFORCECCM = 1. */ - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); - } else { - /* 3 MHz is recommended for LNFORCECCM = 0. */ - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); - } - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; - EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS - | EMU_DCDCMISCCTRL_LPCMPHYSHI; - - SYSTEM_ChipRevisionGet(&rev); - if ((rev.major == 1) - && (rev.minor < 3) - && (errataFixDcdcHsState == errataFixDcdcHsInit)) { - /* LPCMPWAITDIS = 1 */ - EMU_DCDCSMCTRL |= 1; - - dcdcTiming = EMU->DCDCTIMING; - dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK - | _EMU_DCDCTIMING_LNWAIT_MASK - | _EMU_DCDCTIMING_BYPWAIT_MASK); - - dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) - | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) - | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); - EMU->DCDCTIMING = dcdcTiming; - - errataFixDcdcHsState = errataFixDcdcHsTrimSet; - } -#endif -} - -/***************************************************************************//** - * @brief - * Compute current limiters: - * LNCLIMILIMSEL: LN current limiter threshold - * LPCLIMILIMSEL: LP current limiter threshold - * DCDCZDETCTRL: zero detector limiter threshold - ******************************************************************************/ -static void currentLimitersUpdate(void) -{ - uint32_t lncLimSel; - uint32_t zdetLimSel; - uint32_t pFetCnt; - uint16_t maxReverseCurrent_mA; - - /* 80 mA as recommended peak in Application Note AN0948. - The peak current is the average current plus 50% of the current ripple. - Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also - a constant, lpcLimImSel = 1. The following calculation is provided - for documentation only. */ - const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) - / (5 * (DCDC_LP_PFET_CNT + 1))) - - 1; - const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; - - /* Get enabled PFETs. */ - pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) - >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; - - /* Compute the LN current limiter threshold from the nominal user input current and - LN PFETCNT as described in the register description for - EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ - lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) - + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) - / (5U * (pFetCnt + 1U))) - - 1U; - - /* Saturate the register field value. */ - lncLimSel = SL_MIN(lncLimSel, - _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK - >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); - - lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; - - /* Check for overflow. */ - EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); - EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); - - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK - | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) - | (lncLimSel | lpcLimSel); - - /* Compute the reverse current limit threshold for the zero detector from the user input - maximum reverse current and LN PFETCNT as described in the register description - for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ - if (dcdcReverseCurrentControl >= 0) { - /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ - maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; - - zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) - + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) - / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); - /* Saturate the register field value. */ - zdetLimSel = SL_MIN(zdetLimSel, - _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK - >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); - - zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; - - /* Check for overflow. */ - EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); - - EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) - | zdetLimSel; - } -} - -/***************************************************************************//** - * @brief - * Set static variables that hold the user set maximum peak current - * and reverse current. Update limiters. - * - * @param[in] maxCurrent_mA - * Set the maximum peak current that the DCDC can draw from the power source. - * @param[in] reverseCurrentControl - * Reverse the current control as defined by - * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. - ******************************************************************************/ -static void userCurrentLimitsSet(uint32_t maxCurrent_mA, - EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) -{ - dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; - dcdcReverseCurrentControl = reverseCurrentControl; -} - -/***************************************************************************//** - * @brief - * Set DCDC low noise compensator control register. - * - * @param[in] comp - * Low-noise mode compensator trim setpoint. - ******************************************************************************/ -static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) -{ - switch (comp) { - case emuDcdcLnCompCtrl_1u0F: - EMU->DCDCLNCOMPCTRL = 0x57204077UL; - break; - - case emuDcdcLnCompCtrl_4u7F: - EMU->DCDCLNCOMPCTRL = 0xB7102137UL; - break; - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback - * attenuation, and DEVINFOREV. - * - * @param[in] lpAttenuation - * LP feedback attenuation. - * @param[in] lpCmpBias - * lpCmpBias selection. - * @param[in] trimMode - * DCDC trim mode. - ******************************************************************************/ -static bool lpCmpHystCalibrationLoad(bool lpAttenuation, - uint8_t lpCmpBias, - dcdcTrimMode_TypeDef trimMode) -{ - uint32_t lpcmpHystSel; -#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - (void)lpAttenuation; -#endif - - /* Get calibration data revision. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); - - /* Load LPATT indexed calibration data. */ - if (devinfoRev < 4) { - lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; - - if (lpAttenuation) { - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; - } else { - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; - } - } else -#endif - { - /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ - lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; - switch (lpCmpBias) { - case 0: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; - break; - - case 1: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; - break; - - case 2: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; - break; - - case 3: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - } - - /* Set trims. */ - if (trimMode == dcdcTrimMode_EM234H_LP) { - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; - if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; - } - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) - if (trimMode == dcdcTrimMode_EM01_LP) { - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; - if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; - } -#endif - - return true; -} - -/***************************************************************************//** - * @brief - * Load LPVREF low and high from DEVINFO. - * - * @param[out] vrefL - * LPVREF low from DEVINFO. - * @param[out] vrefH - * LPVREF high from DEVINFO. - * @param[in] lpAttenuation - * LP feedback attenuation. - * @param[in] lpcmpBias - * lpcmpBias to look up in DEVINFO. - ******************************************************************************/ -static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, - uint32_t *vrefH, - bool lpAttenuation, - uint8_t lpcmpBias) -{ - uint32_t vrefLow = 0; - uint32_t vrefHigh = 0; - - /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) - and LPATT (lpAttenuation) */ - uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); - switch (switchVal) { - case ((0 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; - break; - - case ((1 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; - break; - - case ((2 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; - break; - - case ((3 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; - break; - - case ((0 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; - break; - - case ((1 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; - break; - - case ((2 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; - break; - - case ((3 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - *vrefL = vrefLow; - *vrefH = vrefHigh; -} - -/***************************************************************************//** - * @brief - * Configure the DCDC regulator. - * - * @note - * Do not call this function if the power circuit is configured for NODCDC as - * described in the Power Configurations section of the Reference Manual. - * Instead, call @ref EMU_DCDCPowerOff(). - * - * @param[in] dcdcInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) -{ - uint32_t lpCmpBiasSelEM234H; - -#if defined(_EMU_PWRCFG_MASK) - /* Set the external power configuration. This enables writing to the other - DCDC registers. */ - EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; - - /* EMU->PWRCFG is write-once and POR reset only. Check that - the desired power configuration was set. */ - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { - /* If this assert triggers unexpectedly, power cycle the - kit to reset the power configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } -#endif - - /* Load DCDC calibration data from the DI page. */ - (void)dcdcConstCalibrationLoad(); - - /* Check current parameters */ - EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); - EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); - - if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { - /* DCDC low-noise supports max 200 mA. */ - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); - } -#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) - else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { - /* Up to 10 mA is supported for EM01-LP mode. */ - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); - } -#endif - else { - /* No need to check the EM01 load limit. */ - } - - /* EM2/3/4 current above 10 mA is not supported. */ - EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); - - if (dcdcInit->em234LoadCurrent_uA < 75U) { - lpCmpBiasSelEM234H = 0; - } else if (dcdcInit->em234LoadCurrent_uA < 500U) { - lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { - lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } else { - lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } - - /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ - - /* Set DCDC low-power mode comparator bias selection. */ - - /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. - => Updates DCDCMISCCTRL_LNFORCECCM */ - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK - | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) - | ((uint32_t)lpCmpBiasSelEM234H - | (dcdcInit->reverseCurrentControl >= 0 - ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* Only 10 mA EM01-LP current is supported. */ - EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; -#endif - - /* 2. Set recommended and validated current optimization settings. - <= Depends on LNFORCECCM - => Updates DCDCLNFREQCTRL_RCOBAND */ - dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; - dcdcValidatedConfigSet(); - - /* 3. Updated static currents and limits user data. - Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ - userCurrentLimitsSet(dcdcInit->maxCurrent_mA, - dcdcInit->reverseCurrentControl); - - /* 4. Optimize LN slice based on the given user input load current. - <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND - <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl - => Updates DCDCMISCCTRL_P/NFETCNT - => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL - => Updates DCDCZDETCTRL_ZDETILIMSEL */ - EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); - - /* ======================================================= */ - - /* Set DCDC low noise mode compensator control register. */ - compCtrlSet(dcdcInit->dcdcLnCompCtrl); - - /* Set DCDC output voltage. */ - if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - -#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) - /* Select analog peripheral power supply. This must be done before - DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ - BUS_RegBitWrite(&EMU->PWRCTRL, - _EMU_PWRCTRL_ANASW_SHIFT, - dcdcInit->anaPeripheralPower ? 1 : 0); -#endif - -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - /* Select DVDD as input to the digital regulator. The switch to DVDD will take - effect once the DCDC output is stable. */ - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - - /* Set EM0 DCDC operating mode. Output voltage set in - @ref EMU_DCDCOutputVoltageSet() above takes effect if mode - is changed from bypass/off mode. */ - EMU_DCDCModeSet(dcdcInit->dcdcMode); - -#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) - /* Select the analog peripheral power supply. This must be done after - DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ - BUS_RegBitWrite(&EMU->PWRCTRL, - _EMU_PWRCTRL_ANASW_SHIFT, - dcdcInit->anaPeripheralPower - == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); -#endif - - return true; -} - -/***************************************************************************//** - * @brief - * Set DCDC regulator operating mode. - * - * @param[in] dcdcMode - * DCDC mode. - ******************************************************************************/ -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) -{ - bool dcdcLocked; - uint32_t currentDcdcMode; - - dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); - EMU_PowerUnlock(); - - /* Wait for any previous write sync to complete and read DCDC mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); - - /* Enable bypass current limiter when not in bypass mode to prevent - excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ - if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); - } - - if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { - /* Mode already set. If already in bypass, make sure the bypass current limiter - is disabled. */ - if (dcdcMode == emuDcdcMode_Bypass) { - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); - } - return; - } - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - - /* Fix for errata DCDC_E203. */ - if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) - && (dcdcMode == emuDcdcMode_LowNoise)) { - errataFixDcdcHsState = errataFixDcdcHsBypassLn; - } -#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_80) - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - /* Fix for errata DCDC_E204. */ - if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) - && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { - /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ - EMU_IntClear(EMU_IFC_DCDCLNRUNNING); - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; - while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { - } - } -#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - /* Set user-requested mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) - | (uint32_t)dcdcMode; - - /* Disable bypass current limiter after bypass mode is entered. - Enable the limiter if any other mode is entered. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, - _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, - dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); - - if (dcdcLocked) { - EMU_PowerLock(); - } -} - -#if defined(EMU_DCDCCTRL_DCDCMODEEM23) -/***************************************************************************//** - * @brief - * Set DCDC Mode EM23 operating mode. - * - * @param[in] dcdcModeEM23 - * DCDC mode EM23. - ******************************************************************************/ -void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23) -{ - bool dcdcLocked; - - dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); - EMU_PowerUnlock(); - - /* Set user-requested mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) - | (uint32_t)dcdcModeEM23; - - if (dcdcLocked) { - EMU_PowerLock(); - } -} -#endif - -/***************************************************************************//** - * @brief - * Power off the DCDC regulator. - * - * @details - * This function powers off the DCDC controller. This function should only be - * used if the external power circuit is wired for no DCDC. If the external power - * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the - * DCDC in bypass mode to disable DCDC. - * - * @return - * Return false if the DCDC could not be disabled. - ******************************************************************************/ -bool EMU_DCDCPowerOff(void) -{ - bool dcdcModeSet; - -#if defined(_EMU_PWRCFG_MASK) - /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ - EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; -#endif - - /* Select DVDD as input to the digital regulator. */ -#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; -#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - - /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required - mode could be set. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; - - dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); - EFM_ASSERT(dcdcModeSet); - - return dcdcModeSet; -} - -/***************************************************************************//** - * @brief - * Set DCDC LN regulator conduction mode. - * - * @param[in] conductionMode - * DCDC LN conduction mode. - * @param[in] rcoDefaultSet - * The default DCDC RCO band for the conductionMode will be used if true. - * Otherwise, the current RCO configuration is used. - ******************************************************************************/ -void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, - bool rcoDefaultSet) -{ - EMU_DcdcMode_TypeDef currentDcdcMode - = (EMU_DcdcMode_TypeDef)((uint32_t) - (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); - EMU_DcdcLnRcoBand_TypeDef rcoBand - = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) - ((EMU->DCDCLNFREQCTRL - & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); - - /* Set bypass mode and wait for bypass mode to settle before - EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ - EMU_IntClear(EMU_IFC_DCDCINBYPASS); - EMU_DCDCModeSet(emuDcdcMode_Bypass); - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { - } - if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { - EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; - if (rcoDefaultSet) { - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); - } else { - /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ - EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); - } - } else { - EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; - if (rcoDefaultSet) { - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); - } - } - EMU_DCDCModeSet(currentDcdcMode); - /* Update slice configuration as it depends on conduction mode and RCO band.*/ - EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); -} - -/***************************************************************************//** - * @brief - * Set the DCDC output voltage. - * - * @note - * The DCDC is not characterized for the entire valid output voltage range. - * For that reason an upper limit of 3.0V output voltage is enforced. - * - * @param[in] mV - * Target DCDC output voltage in mV. - * - * @param[in] setLpVoltage - * Update LP voltage - * - * @param[in] setLnVoltage - * Update LN voltage - * - * @return - * True if the mV parameter is valid. - ******************************************************************************/ -bool EMU_DCDCOutputVoltageSet(uint32_t mV, - bool setLpVoltage, - bool setLnVoltage) -{ -#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - - bool validOutVoltage; - bool attenuationSet; - uint32_t mVlow = 0; - uint32_t mVhigh = 0; - uint32_t mVdiff; - uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; - uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; - uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; - uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; - - /* Check that the set voltage is within valid range. - Voltages are obtained from the data sheet. */ - validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) - && (mV <= PWRCFG_DCDCTODVDD_VMAX); - - if (!validOutVoltage) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* Set attenuation to use and low/high range. */ - attenuationSet = mV > 1800U; - if (attenuationSet) { - mVlow = 1800; - mVhigh = 3000; - mVdiff = mVhigh - mVlow; - } else { - mVlow = 1200; - mVhigh = 1800; - mVdiff = mVhigh - mVlow; - } - - /* Get 2-point calibration data from DEVINFO. */ - - /* LN mode */ - if (attenuationSet) { - vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; - vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; - vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; - } else { - vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; - vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; - vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; - } - - /* LP EM234H mode */ - lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) - ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) - >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); - lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], - &vrefHigh[dcdcTrimMode_EM234H_LP], - attenuationSet, - lpcmpBias[dcdcTrimMode_EM234H_LP]); - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* LP EM01 mode */ - lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) - ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); - lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], - &vrefHigh[dcdcTrimMode_EM01_LP], - attenuationSet, - lpcmpBias[dcdcTrimMode_EM01_LP]); -#endif - - /* Calculate output voltage trims. */ - vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) - / mVdiff; - vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; - - vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) - / mVdiff; - vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) - / mVdiff; - vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; -#endif - - /* Range checks */ - if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) - || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) - || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) -#endif - || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) - || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* Update output voltage tuning for LN and LP modes. */ - if (setLnVoltage) { - EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) - | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) - | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); - } - - if (setLpVoltage) { - /* Load LP EM234H comparator hysteresis calibration. */ - if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* Load LP EM234H comparator hysteresis calibration. */ - if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* LP VREF is that maximum of trims for EM01 and EM234H. */ - vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); -#endif - - /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ - vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); - EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) - | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) - | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); - } -#endif - return true; -} - -/***************************************************************************//** - * @brief - * Optimize the DCDC slice count based on the estimated average load current - * in EM0. - * - * @param[in] em0LoadCurrentmA - * Estimated average EM0 load current in mA. - ******************************************************************************/ -void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) -{ - uint32_t sliceCount = 0; - uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; - - /* Set the recommended slice count. */ - if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) - && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { - if (em0LoadCurrentmA < 20U) { - sliceCount = 4; - } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) - && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { - if (em0LoadCurrentmA < 10U) { - sliceCount = 4; - } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) - && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { - if (em0LoadCurrentmA < 40U) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else { - /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended - configuration. */ - EFM_ASSERT(false); - } - - /* The selected slices are PSLICESEL + 1. */ - sliceCount--; - - /* Apply slice count to both N and P slice. */ - sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT - | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK - | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) - | sliceCount; - - /* Update the current limiters. */ - currentLimitersUpdate(); -} - -/***************************************************************************//** - * @brief - * Set DCDC Low-noise RCO band. - * - * @param[in] band - * RCO band to set. - ******************************************************************************/ -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) -{ - uint32_t forcedCcm; - forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - - /* DCM mode supports up to 4 MHz LN RCO. */ - EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) - || (forcedCcm != 0U)); - - EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); - - /* Update slice configuration as this depends on the RCO band. */ - EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); -} -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/***************************************************************************//** - * @brief - * Configure the DCDC Boost regulator. - * - * @param[in] dcdcBoostInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) -{ - bool dcdcLocked; - - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif - - DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) - | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); - DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) - | ((uint32_t)dcdcBoostInit->peakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT); - DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) - | ((uint32_t)dcdcBoostInit->peakCurrentEM23 << _DCDC_BSTEM23CTRL_IPKVAL_SHIFT); - - EMU_BoostExternalShutdownEnable(dcdcBoostInit->externalShutdownEn); - - EMU_DCDCModeSet(emuDcdcMode_Regulation); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - - return true; -} - -/***************************************************************************//** - * @brief - * Set EM01 mode Boost Peak Current setting. - * - * @param[in] boostPeakCurrentEM01 - * Boost Peak load current coefficient in EM01 mode. - ******************************************************************************/ -void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - /* Wait for synchronization before writing new value */ -#if defined(_DCDC_SYNCBUSY_MASK) - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif - - BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, - _DCDC_BSTEM01CTRL_IPKVAL_MASK, - ((uint32_t)boostPeakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT)); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} - -/***************************************************************************//** - * @brief - * Enable/disable Boost External Shutdown Mode. - * - * @param[in] enable - * The boost DC-DC converter can be activated or deactivated - * from a dedicated BOOST_EN pin on the device if enable is true. - ******************************************************************************/ -void EMU_BoostExternalShutdownEnable(bool enable) -{ - if (enable) { - EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; - } else { - EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; - } -} -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/***************************************************************************//** - * @brief - * Indicate that the DCDC peripheral bus clock enable has changed allowing - * RAIL to react accordingly. - * - * @details - * This function is called after DCDC has been enabled or disabled. - * The function implementation does not perform anything, but it is SL_WEAK - * so that it can use the RAIL version if needed. - ******************************************************************************/ -SL_WEAK void EMU_DCDCUpdatedHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Set DCDC regulator operating mode. - * - * @param[in] dcdcMode - * DCDC mode. - * @return - * Returns the status of the DCDC mode set operation. - * @verbatim - * SL_STATUS_OK - Operation completed successfully. - * SL_STATUS_TIMEOUT - Operation EMU DCDC set mode timeout. - * @endverbatim - ******************************************************************************/ -sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) -{ - bool dcdcLocked; - uint32_t currentDcdcMode; - sl_status_t error = SL_STATUS_OK; - uint32_t timeout = 0; - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - if (dcdcMode == emuDcdcMode_Bypass) { -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_CTRL_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_CTRL); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif - currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT; - - if (currentDcdcMode != emuDcdcMode_Bypass) { - /* Switch to BYPASS mode if it is not the current mode */ - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for BYPASS switch enable. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } - } -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_CLR = DCDC_EN_EN; -#endif - } else { - while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for VREGIN voltage to rise above threshold. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } else { - DCDC->IF_CLR = DCDC_IF_REGULATION; - DCDC->CTRL_SET = DCDC_CTRL_MODE; - timeout = 0; - while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for DCDC to complete it's startup. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } - } - } - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - return error; -} -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT || EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/***************************************************************************//** - * @brief - * Configure the DCDC regulator. - * - * @param[in] dcdcInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) -{ - bool dcdcLocked; - - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold - << _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT) - | EMU_VREGVDDCMPCTRL_VREGINCMPEN; - -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_CTRL_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_CTRL | DCDC_SYNCBUSY_EM01CTRL0 | DCDC_SYNCBUSY_EM23CTRL0); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif -#if defined(_DCDC_CTRL_DCMONLYEN_MASK) - DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK - | _DCDC_CTRL_DCMONLYEN_MASK)) - | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT) - | ((uint32_t)(dcdcInit->dcmOnlyEn ? 1U : 0U) << _DCDC_CTRL_DCMONLYEN_SHIFT); -#else - DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK)) - | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT); -#endif - DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT) - | ((uint32_t)dcdcInit->peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT); - DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT) - | ((uint32_t)dcdcInit->peakCurrentEM23 << _DCDC_EM23CTRL0_IPKVAL_SHIFT); - - EMU_DCDCModeSet(dcdcInit->mode); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - - return true; -} - -/***************************************************************************//** - * @brief - * Power off the DCDC regulator. - * - * @return - * Returns true. - ******************************************************************************/ -bool EMU_DCDCPowerOff(void) -{ - EMU_DCDCModeSet(emuDcdcMode_Bypass); - return true; -} - -/***************************************************************************//** - * @brief - * Set EMO1 mode Peak Current setting. - * - * @param[in] peakCurrentEM01 - * Peak load current coefficient in EM01 mode. - ******************************************************************************/ -void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - -#if defined(_DCDC_EN_EN_MASK) - bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0); - DCDC->EN_SET = DCDC_EN_EN; -#endif - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - /* Wait for synchronization before writing new value */ -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_EM01CTRL0_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_EM01CTRL0); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif - - BUS_RegMaskedWrite(&DCDC->EM01CTRL0, - _DCDC_EM01CTRL0_IPKVAL_MASK, - ((uint32_t)peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT)); - -#if defined(_DCDC_EN_EN_MASK) - if (!dcdcWasEnabled) { - DCDC->EN_CLR = DCDC_EN_EN; - } -#endif - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} - -#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) -/***************************************************************************//** - * @brief - * Set PFMX mode Peak Current setting. - * - * @param[in] value - * Peak load current coefficient in PFMX mode. - ******************************************************************************/ -void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - /* Verification that the parameter is in range. */ - /* if not, restrict value to maximum allowed. */ - EFM_ASSERT(value <= (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)); - if (value > (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)) { - value = (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT); - } - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - /* Wait for synchronization before writing new value */ - EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); -#endif - - DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK) - | value << _DCDC_PFMXCTRL_IPKVAL_SHIFT); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} -#endif /* _DCDC_PFMXCTRL_IPKVAL_MASK */ - -#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) -/***************************************************************************//** - * @brief - * Set Ton_max timeout control. - * - * @param[in] value - * Maximum time for peak current detection. - ******************************************************************************/ -void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - /* Wait for synchronization before writing new value */ - EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); -#endif - - DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) - | value << _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} -#endif /* _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK */ -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_STATUS_VMONRDY) - -/***************************************************************************//** - * @brief - * Get the calibrated threshold value. - * - * @details - * All VMON channels have two calibration fields in the DI page that - * describes the threshold at 1.86 V and 2.98 V. This function will convert - * the uncalibrated input voltage threshold in millivolts into a calibrated - * threshold. - * - * @param[in] channel - * A VMON channel. - * - * @param[in] threshold - * A desired threshold in millivolts. - * - * @return - * A calibrated threshold value to use. The first digit of the return value is placed - * in the "fine" register fields while the next digits are placed in the - * "coarse" register fields. - ******************************************************************************/ -static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, - int threshold) -{ - uint32_t tDiff = 0; - uint32_t tLow = 0; - uint32_t tHigh = 0; - uint32_t calReg; - - /* Get calibration values for 1.86 V and 2.98 V */ - switch (channel) { - case emuVmonChannel_AVDD: - calReg = DEVINFO->VMONCAL0; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_ALTAVDD: - calReg = DEVINFO->VMONCAL0; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_DVDD: - calReg = DEVINFO->VMONCAL1; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_IOVDD0: - calReg = DEVINFO->VMONCAL1; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - calReg = DEVINFO->VMONCAL2; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - calReg = DEVINFO->VMONCAL2; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); - break; -#endif - default: - EFM_ASSERT(false); - break; - } - - tDiff = tHigh - tLow; - if (tDiff > 0) { - /* Calculate threshold. - * - * Note that volt is used in the reference manual. However, the results - * should be in millivolts. The precision of Va and Vb are increased in the - * calculation instead of using floating points. - */ - uint32_t va = (1120U * 100U) / (tDiff); - uint32_t vb = (1860U * 100U) - (va * tLow); - // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. - if (va != 0) { - /* Round the threshold to the nearest integer value. */ - return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; - } - } - - /* Uncalibrated device guard. */ - return (uint32_t)threshold; -} - -/***************************************************************************//** - * @brief - * Initialize a VMON channel. - * - * @details - * Initialize a VMON channel without hysteresis. If the channel supports - * separate rise and fall triggers, both thresholds will be set to the same - * value. The threshold will be converted to a register field value based - * on calibration values from the DI page. - * - * @param[in] vmonInit - * The VMON initialization structure. - ******************************************************************************/ -void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) -{ - uint32_t thresholdCoarse, thresholdFine; - uint32_t threshold; - - EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); - - threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); - thresholdFine = threshold % 10U; - thresholdCoarse = threshold / 10U; - - /* Saturate the threshold to maximum values. */ - if (thresholdCoarse > 0xFU) { - thresholdCoarse = 0xF; - thresholdFine = 9; - } - - switch (vmonInit->channel) { - case emuVmonChannel_AVDD: - EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) - | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); - break; - case emuVmonChannel_ALTAVDD: - EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); - break; - case emuVmonChannel_DVDD: - EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); - break; - case emuVmonChannel_IOVDD0: - EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) - | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) - | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) - | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) - | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); - break; -#endif - default: - EFM_ASSERT(false); - return; - } -} - -/***************************************************************************//** - * @brief - * Initialize a VMON channel with hysteresis (separate rise and fall triggers). - * - * @details - * Initialize a VMON channel which supports hysteresis. The AVDD channel is - * the only channel to support separate rise and fall triggers. The rise and - * fall thresholds will be converted to a register field value based on the - * calibration values from the DI page. - * - * @param[in] vmonInit - * The VMON hysteresis initialization structure. - ******************************************************************************/ -void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) -{ - uint32_t riseThreshold; - uint32_t fallThreshold; - - /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ - EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); - EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); - /* The fall threshold has to be lower than rise threshold. */ - EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); - - riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); - fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); - - switch (vmonInit->channel) { - case emuVmonChannel_AVDD: - EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) - | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) - | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) - | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); - break; - default: - EFM_ASSERT(false); - return; - } -} - -/***************************************************************************//** - * @brief - * Enable or disable a VMON channel. - * - * @param[in] channel - * A VMON channel to enable/disable. - * - * @param[in] enable - * Indicates whether to enable or disable. - ******************************************************************************/ -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) -{ - uint32_t volatile * reg; - uint32_t bit; - - switch (channel) { - case emuVmonChannel_AVDD: - reg = &(EMU->VMONAVDDCTRL); - bit = _EMU_VMONAVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_ALTAVDD: - reg = &(EMU->VMONALTAVDDCTRL); - bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_DVDD: - reg = &(EMU->VMONDVDDCTRL); - bit = _EMU_VMONDVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_IOVDD0: - reg = &(EMU->VMONIO0CTRL); - bit = _EMU_VMONIO0CTRL_EN_SHIFT; - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - reg = &(EMU->VMONIO1CTRL); - bit = _EMU_VMONIO1CTRL_EN_SHIFT; - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - reg = &(EMU->VMONBUVDDCTRL); - bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; - break; -#endif - default: - EFM_ASSERT(false); - return; - } - - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Get the status of a voltage monitor channel. - * - * @param[in] channel - * A VMON channel to get the status for. - * - * @return - * A status of the selected VMON channel. True if the channel is triggered. - ******************************************************************************/ -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) -{ - uint32_t bit; - switch (channel) { - case emuVmonChannel_AVDD: - bit = _EMU_STATUS_VMONAVDD_SHIFT; - break; - case emuVmonChannel_ALTAVDD: - bit = _EMU_STATUS_VMONALTAVDD_SHIFT; - break; - case emuVmonChannel_DVDD: - bit = _EMU_STATUS_VMONDVDD_SHIFT; - break; - case emuVmonChannel_IOVDD0: - bit = _EMU_STATUS_VMONIO0_SHIFT; - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - bit = _EMU_STATUS_VMONIO1_SHIFT; - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - bit = _EMU_STATUS_VMONBUVDD_SHIFT; - break; -#endif - default: - bit = 0; - EFM_ASSERT(false); - break; - } - - return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; -} -#endif /* EMU_STATUS_VMONRDY */ - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/***************************************************************************//** - * @brief - * Adjust the bias refresh rate. - * - * @details - * This function is only meant to be used under high-temperature operation on - * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will - * increase the typical current consumption. See application note 1027 - * and errata documents for more details. - * - * @param [in] mode - * The new bias refresh rate. - ******************************************************************************/ -void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) -{ - uint32_t freq = 0x2u; - bool emuTestLocked = false; - - if (mode == emuBiasMode_1KHz) { - freq = 0x0u; - } - - if (EMU_TESTLOCK == 0x1u) { - emuTestLocked = true; - EMU_TESTLOCK = 0xADE8u; - } - - if (mode == emuBiasMode_Continuous) { - EMU_BIASCONF &= ~0x74u; - } else { - EMU_BIASCONF |= 0x74u; - } - - EMU_BIASTESTCTRL |= 0x8u; - CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) - | ((freq & 0x3u) << 10u); - EMU_BIASTESTCTRL &= ~0x8u; - - if (emuTestLocked) { - EMU_TESTLOCK = 0u; - } -} -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/***************************************************************************//** - * @brief - * Get temperature in degrees Celsius - * - * @return - * Temperature in degrees Celsius - ******************************************************************************/ -float EMU_TemperatureGet(void) -{ -#if defined(_EMU_TEMP_TEMPLSB_MASK) - return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) - >> _EMU_TEMP_TEMPLSB_SHIFT) - ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; -#else - uint32_t val1; - uint32_t val2; - float tempCo; - uint32_t diTemp, diEmu; - - // Calculate calibration temp based on DI page values - diTemp = ((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); - diEmu = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); - tempCo = EMU_TEMPCO_CONST + (diEmu / 100.0f); - - // Read temperature twice to ensure a stable value - do { - val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) - >> _EMU_TEMP_TEMP_SHIFT; - val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) - >> _EMU_TEMP_TEMP_SHIFT; - } while (val1 != val2); - - return diTemp + tempCo * ((int) diEmu - (int) val1); -#endif -} -#endif // defined(_EMU_TEMP_TEMP_MASK) - -#if defined(EMU_CTRL_EFPDIRECTMODEEN) -/***************************************************************************//** - * @brief - * Enable/disable EFP Direct Mode. - * - * @param[in] enable - * True to enable direct mode. - ******************************************************************************/ -void EMU_EFPDirectModeEnable(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; - } -} -#endif - -#if defined(EMU_CTRL_EFPDRVDECOUPLE) -/***************************************************************************//** - * @brief - * Set to enable EFP to drive Decouple voltage. - * - * @details - * Once set, internal LDO will be disabled, and the EMU will control EFP for - * voltage-scaling. Note that because this bit disables the internal LDO - * powering the core, it should not be set until after EFP's DECOUPLE output has - * been configured and enabled. - * - * @param[in] enable - * True to enable EFP to drive Decouple voltage. - ******************************************************************************/ -void EMU_EFPDriveDecoupleSet(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; - } -} -#endif - -#if defined(EMU_CTRL_EFPDRVDVDD) -/***************************************************************************//** - * @brief - * Set to enable EFP to drive DVDD voltage. - * - * @details - * Set this if EFP's DCDC output is powering DVDD supply. This mode assumes that - * internal DCDC is not being used. - * - * @param[in] enable - * True to enable EFP to drive DVDD voltage. - ******************************************************************************/ -void EMU_EFPDriveDvddSet(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; - } -} -#endif - -/** @} (end addtogroup emu) */ -#endif /* __EM_EMU_H */ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#include "em_emu.h" +#if defined(EMU_PRESENT) && (EMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" +#include "em_ramfunc.h" + +#if defined(SL_CATALOG_METRIC_EM23_WAKE_PRESENT) +#include "sli_metric_em23_wake.h" +#include "sli_metric_em23_wake_config.h" +#endif + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) +#include "sli_metric_em4_wake.h" +#endif + +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/* Consistency check, since restoring assumes similar bit positions in */ +/* CMU OSCENCMD and STATUS regs. */ +#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) +#error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) +#error Conflict in HFXOENS and HFXOEN bitpositions +#endif +#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) +#error Conflict in LFRCOENS and LFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) +#error Conflict in LFXOENS and LFXOEN bitpositions +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined(_EFM32_GECKO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_TINY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x001be323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_GIANT_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_WONDER_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_ZERO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00005c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#elif defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00085c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#endif +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ + || (defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) +// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. +#define ERRATA_FIX_EMU_E110_ENABLE +#endif + +/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E108_ENABLE +#endif + +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_EMU_E208_ENABLE +#endif + +/* Enable FETCNT tuning errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE +#endif + +/* Enable LN handshake errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE +typedef enum { + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; +#endif + +/* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S + * while powering the analog peripherals from DVDD, firmware must switch + * over to powering the analog peripherals from AVDD and delay the EM4S entry + * with 30 us. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define ERRATA_FIX_EM4S_DELAY_ENTRY +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) +/* EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. */ +#define ERRATA_FIX_EMU_E220_DECBOD_ENABLE +#define EMU_PORBOD (*(volatile uint32_t *) (EMU_BASE + 0x14C)) +#define EMU_PORBOD_GMC_CALIB_DISABLE (0x1UL << 31) +#endif + +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0 and some devices have a special RAM block + * at the end of their block layout. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2U +#define RAM0_BLOCK_SIZE 0x4000U +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#define RAM0_BLOCKS 1U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM1_BLOCKS 1U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) +#define RAM0_BLOCKS 8U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 8U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 4U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define RAM0_BLOCKS 6U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if !defined(PWRCFG_DCDCTODVDD_VMIN) +/** DCDCTODVDD output range maximum. */ +#define PWRCFG_DCDCTODVDD_VMIN 1800U +#endif +#if !defined(PWRCFG_DCDCTODVDD_VMAX) +/** DCDCTODVDD output range minimum. */ +#define PWRCFG_DCDCTODVDD_VMAX 3000U +#endif +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) || defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#define DCDC_LP_PFET_CNT 7 +#define DCDC_LP_NFET_CNT 7 +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/* Translate fields with different names across platform generations to common names. */ +#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT +#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT +#endif +#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT +#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT +#endif + +/* Disable LP mode hysteresis in the state machine control. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) +/* Comparator threshold on the high side. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) +#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) + +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/* EMU DCDC MODE set timeout. */ +#define EMU_DCDC_MODE_SET_TIMEOUT 1000000 +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) +#define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) +#define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) +#define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/* As the energy mode at which a temperature measurement was taken at is + * not known, the chosen constant for the TEMPCO calculation is midway between + * the EM0/EM1 constant and the EM2/EM3/EM4 constant. + */ +#define EMU_TEMPCO_CONST (0.273f) +#endif + +#define EMU_EM4_ENTRY_WAIT_LOOPS 200 + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* Static user configuration. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +static uint16_t dcdcMaxCurrent_mA; +static uint16_t dcdcEm01LoadCurrent_mA; +static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; +#endif +#if defined(EMU_VSCALE_EM01_PRESENT) +static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/* Convert from level to EM0/1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + return EMU_CMD_EM01VSCALE1 << ((uint32_t)level - _EMU_STATUS_VSCALE_VSCALE1); +#else + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +#endif +} +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) + __WFI(); // Enter EM2 or EM3 + if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { + for (volatile int i = 0; i < 6; i++) { + } // Dummy wait loop ... + } + +#else + __WFI(); // Enter EM2 or EM3 +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + *(volatile uint32_t*)4; // Clear faulty read data after wakeup +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif +#endif +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ + /* Second part of EMU_E220 DECBOD Errata fix. Calibration needs to be disabled + * quickly when coming out of EM2/EM3. Ram execution is needed to meet timing. + * Calibration is re-enabled after voltage scaling completes. */ + uint32_t temp = EMU_PORBOD | EMU_PORBOD_GMC_CALIB_DISABLE; + __WFI(); + EMU_PORBOD = temp; +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +/***************************************************************************//** + * @brief + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change the oscillator and the voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * + ******************************************************************************/ +typedef enum { + emState_Save, /* Save EMU and CMU state. */ + emState_Restore, /* Restore and unlock. */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) +{ + uint32_t oscEnCmd; + uint32_t cmuLocked; + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined(EMU_VSCALE_PRESENT) + static uint8_t vScaleStatus; + static uint32_t hfrcoCtrl; +#endif + + /* Save or update state. */ + if (action == emState_Save) { + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined(EMU_VSCALE_PRESENT) + /* Save vscale. */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + hfrcoCtrl = CMU->HFRCOCTRL; +#endif + } else { /* Restore state. */ + /* Apply saved configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == true) + /* Restore voltage scaling level if LDO regulator is on. */ +#endif + { + /* Restore EM0 and 1 voltage scaling level. + @ref EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); + } +#endif + /* CMU registers may be locked. */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + +#if defined(_CMU_OSCENCMD_MASK) + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U + ? CMU_OSCENCMD_HFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U + ? CMU_OSCENCMD_AUXHFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U + ? CMU_OSCENCMD_LFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U + ? CMU_OSCENCMD_HFXOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U + ? CMU_OSCENCMD_LFXOEN : 0U; +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U + ? CMU_OSCENCMD_USHFRCOEN : 0U; +#endif + CMU->OSCENCMD = oscEnCmd; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) + /* Wait for upscale to complete and then restore selected clock. */ + EMU_VScaleWait(); + if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { + /* Restore HFRCO frequency which was automatically adjusted by hardware. */ + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { + } + CMU->HFRCOCTRL = hfrcoCtrl; + if (hfClock == cmuSelect_HFRCO) { + /* Optimize wait state after EM2/EM3 wakeup because hardware has + * modified them. */ + CMU_UpdateWaitStates(SystemHfrcoFreq, (int)EMU_VScaleGet()); + } + } +#endif + + switch (hfClock) { + case cmuSelect_LFXO: + CMU_CLOCK_SELECT_SET(HF, LFXO); + break; + case cmuSelect_LFRCO: + CMU_CLOCK_SELECT_SET(HF, LFRCO); + break; + case cmuSelect_HFXO: + CMU_CLOCK_SELECT_SET(HF, HFXO); + break; +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, USHFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, HFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + CMU_CLOCK_SELECT_SET(HF, CLKIN0); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + break; +#endif + } + +#if defined(_CMU_OSCENCMD_MASK) + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } +#endif + + /* Restore CMU register locking */ + if (cmuLocked != 0U) { + CMU_Lock(); + } + } +} +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) +/* Get enable conditions for errata EMU_E107 fix. */ +__STATIC_INLINE bool getErrataFixEmuE107En(void) +{ +#if defined(_EFM32_HAPPY_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) + // all revisions have the errata + return true; +#else + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_EFM32_GECKO_FAMILY) + // all GECKO revisions except Revision E have the errata + return (majorMinorRev <= 0x0103); +#elif defined(_EFM32_GIANT_FAMILY) + // all LEOPARD GECKO (Major = 0x01 Or 0x02) revisions have the errata + // all GIANT GECKO (Major = 0x01) revisions except Revision E have the errata + return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204) || (majorMinorRev == 0x0205); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +#endif /* #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) #else */ +} +#endif /* #if defined(ERRATA_FIX_EMU_E107_ENABLE) */ + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +/* Get enable conditions for errata EMU_E110 fix. */ +__STATIC_INLINE bool getErrataFixEmuE110En(void) +{ + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_ZERO_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + return ((majorMinorRev == 0x0100 || majorMinorRev == 0x0101)); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_WONDER_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + return (majorMinorRev == 0x0204); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +} +#endif /* #if defined(ERRATA_FIX_EMU_E110_ENABLE) */ + +/* LP prepare / LN restore P/NFET count. */ +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) +static void currentLimitersUpdate(void); +static void dcdcFetCntSet(bool lpModeSet) +{ + uint32_t tmp; + static uint32_t emuDcdcMiscCtrlReg; + + if (lpModeSet) { + emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; + tmp = EMU->DCDCMISCCTRL + & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); + tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) + | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = tmp; + currentLimitersUpdate(); + } else { + EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; + currentLimitersUpdate(); + } +} +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +static void dcdcHsFixLnBlock(void) +{ + if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) + || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { + /* Wait for LNRUNNING */ + if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { + while (!(EMU_DCDCSTATUS & (0x1 << 16))) { + } + } + errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; + } +} +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) +/* Configure EMU and CMU for EM2 and 3 voltage downscale. */ +static void vScaleDownEM23Setup(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + + uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; + uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; + + /* Inverse coding. */ + if (em23vs > em01vs) { + EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + /* Set RAM wait states for safe EM2 wakeup. */ + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); +#endif + } else { + EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; + } +} + +/* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ +static void vScaleAfterWakeup(void) +{ + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 + * entry if voltage scaling in EM2/EM3 is enabled. The hardware would + * then update the HFRCO frequency to 19 MHz automatically. */ + uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) + >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; + if (freqRange == 0x08U) { + SystemHfrcoFreq = 19000000; + } + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +typedef enum { + dpllState_Save, /* Save DPLL state. */ + dpllState_Restore, /* Restore DPLL. */ +} dpllState_TypeDef; + +/***************************************************************************//** + * @brief + * Save or restore DPLL state. + * + * @param[in] action + * Value to indicate saving DPLL state or restoring its state. + * + * @note + * The function is used in EMU_Save() and EMU_Restore() to handle the + * DPLL state before entering EM2 or EM3 and after exiting EM2 or EM3. + * The function is required for the EFR32xG22 and EFR32xG27 families. + * On those families devices, the DPLL is disabled automatically when + * entering EM2, EM3. But exiting EM2, EM3 won't re-enable automatically + * the DPLL. Hence, the software needs to re-enable the DPLL upon EM2/3 + * exit. + ******************************************************************************/ +static void dpllState(dpllState_TypeDef action) +{ + CMU_ClkDiv_TypeDef div; + static uint32_t dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + + if (action == dpllState_Save) { + dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; + if (DPLL0->EN == DPLL_EN_EN) { + /* DPLL is in use, save reference clock selection. */ + dpllRefClk = CMU->DPLLREFCLKCTRL; + } + } else { /* Restore */ + if ((dpllRefClk != CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED) + && (DPLL0->EN != DPLL_EN_EN)) { + /* Restore DPLL reference clock selection. */ + CMU->DPLLREFCLKCTRL = dpllRefClk; + /* Only wait for DPLL lock if HFRCODPLL is used as SYSCLK. */ + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + /* Set HCLK prescaler to safe value to avoid overclocking while locking. */ + div = CMU_ClockDivGet(cmuClock_HCLK); + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } + + /* Relock DPLL and wait for ready. */ + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + DPLL0->EN_SET = DPLL_EN_EN; + while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { + } + + /* Restore HCLK prescaler. */ + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 1U); + } + } else { + /* Relock DPLL and exit without waiting for ready. */ + DPLL0->EN_SET = DPLL_EN_EN; + } + } + } +} +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup emu EMU - Energy Management Unit + * @brief Energy Management Unit (EMU) Peripheral API + * @details + * This module contains functions to control the EMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes + * in Silicon Labs microcontrollers. + * @{ + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 0 and 1 configuration. + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure. + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); +} +#endif + +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 2 and 3 configuration. + * + * @param[in] em23Init + * Energy Mode 2 and 3 configuration structure. + ******************************************************************************/ +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) +{ +#if defined(_EMU_CTRL_EMVREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) + : (EMU->CTRL & ~EMU_CTRL_EMVREG); +#elif defined(_EMU_CTRL_EM23VREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) + : (EMU->CTRL & ~EMU_CTRL_EM23VREG); +#else + (void)em23Init; +#endif + +#if defined(EMU_VSCALE_PRESENT) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#if defined(CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) + if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just prior to execution of the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PresleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just after wakeup from the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PostsleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 2 (EM2). + * + * @details + * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO + * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering + * EM0, HFRCO is re-enabled and the core will be clocked by the configured + * HFRCO band. This ensures a quick wakeup from EM2. + * + * However, prior to entering EM2, the core may have been using another + * oscillator than HFRCO. The @p restore parameter gives the user the option + * to restore all HF oscillators according to state prior to entering EM2, + * as well as the clock used to clock the core. This restore procedure is + * handled by SW. However, since handled by SW, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use the HFXO oscillator, which has been + * disabled during EM2 mode, this function will stall until the oscillator + * has stabilized. Stalling time can be reduced by adding interrupt + * support detecting stable oscillator, and an asynchronous switch to the + * original oscillator. See CMU documentation. Such a feature is however + * outside the scope of the implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can not be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO is re-enabled by this function, and NOT used to clock the core, + * this function will not wait for HFXO to stabilize. This must be considered + * by the application if trying to use features relying on that oscillator + * upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM2. It will thus remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(), + * the automatic starting and selecting of the core clocks will be done, + * regardless of the @p restore parameter, when waking up on the wakeup + * sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * Note that the hardware will automatically update the HFRCO frequency in the + * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the + * restore argument to this function is true then software will restore the + * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is + * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and + * all wait states are at a safe value. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM2(bool restore) +{ +#if defined(SLI_METRIC_EM2_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM2_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + + EMU_EM23PresleepHook(); + EMU_EFPEM23PresleepHook(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EFPEM23PostsleepHook(); + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Enter energy mode 3 (EM3). + * + * @details + * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, + * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, + * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When + * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the + * configured HFRCO band. This ensures a quick wakeup from EM3. + * + * However, prior to entering EM3, the core may have been using an + * oscillator other than HFRCO. The @p restore parameter gives the user the option + * to restore all HF/LF oscillators according to state prior to entering EM3, + * as well as the clock used to clock the core. This restore procedure is + * handled by software. However, since it is handled by software, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use an oscillator other than HFRCO, this + * function will stall until the oscillator has stabilized. Stalling time + * can be reduced by adding interrupt support detecting stable oscillator, + * and an asynchronous switch to the original oscillator. See CMU + * documentation. This feature is, however, outside the scope of the + * implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can't be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock + * the core, this function will not wait for those oscillators to stabilize. + * This must be considered by the application if trying to use features + * relying on those oscillators upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM3. It will, therefore, remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM3(bool restore) +{ +#if defined(SLI_METRIC_EM3_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM3_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + +#if defined(_CMU_OSCENCMD_MASK) + uint32_t cmuLocked; + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* Disable LF oscillators. */ + CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; + + /* Restore CMU register locking. */ + if (cmuLocked != 0U) { + CMU_Lock(); + } +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + + EMU_EM23PresleepHook(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Save the CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the state to be saved without + * going to sleep. The state can be restored manually by calling + * @ref EMU_Restore(). + ******************************************************************************/ +void EMU_Save(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Save); +#endif +} + +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Restore); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Restore); +#endif +} + +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 4 configuration. + * + * @param[in] em4Init + * Energy Mode 4 configuration structure. + ******************************************************************************/ +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) +{ +#if defined(_EMU_EM4CONF_MASK) + /* Initialization for platforms with EMU->EM4CONF register. */ + uint32_t em4conf = EMU->EM4CONF; + + /* Clear fields that will be reconfigured. */ + em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK + | _EMU_EM4CONF_OSC_MASK + | _EMU_EM4CONF_BURTCWU_MASK + | _EMU_EM4CONF_VREGEN_MASK + | _EMU_EM4CONF_BUBODRSTDIS_MASK); + + /* Configure new settings. */ + em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) + | (em4Init->osc) + | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) + | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) + | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); + + /* Apply configuration. Note that lock can be set after this stage. */ + EMU->EM4CONF = em4conf; + +#elif defined(_EMU_EM4CTRL_EM4STATE_MASK) + /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ + + uint32_t em4ctrl = EMU->EM4CTRL; + + em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK + | _EMU_EM4CTRL_RETAINLFRCO_MASK + | _EMU_EM4CTRL_RETAINULFRCO_MASK + | _EMU_EM4CTRL_EM4STATE_MASK + | _EMU_EM4CTRL_EM4IORETMODE_MASK); + + em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) + | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) + | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) + | (em4Init->em4State == emuEM4Hibernate + ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) + | ((uint32_t)em4Init->pinRetentionMode); + + EMU->EM4CTRL = em4ctrl; +#elif defined(_EMU_EM4CTRL_MASK) + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | (uint32_t)em4Init->pinRetentionMode; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Energy mode 4 pre-sleep hook function. + * + * @details + * This function is called by @ref EMU_EnterEM4() just prior to the sequence + * of writes to put the device in EM4. The function implementation does not + * perform anything, but it is SL_WEAK so that it can be re-implemented in + * application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 4 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM4PresleepHook() but is reserved for + * EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + ******************************************************************************/ +void EMU_EnterEM4(void) +{ +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) + sli_metric_em4_wake_init(); +#endif + int i; + +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); +#else + uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (2U << _EMU_CTRL_EM4CTRL_SHIFT); + uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (3U << _EMU_CTRL_EM4CTRL_SHIFT); +#endif + + /* Make sure that the register write lock is disabled. */ + EMU_Unlock(); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should + * switch to bypass mode before entering EM4S. Other devices handle this + * automatically at the hardware level. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE + || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { + EMU_DCDCModeSet(emuDcdcMode_Bypass); + } + } +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + /* Make sure DCDC Mode is not modified, from this point forward, + * by another code section. */ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + /* Workaround for bug that may cause a Hard Fault on EM4 entry */ + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + /* The buck DC-DC is available in all energy modes except for EM4. + * The DC-DC converter must first be turned off and switched over to bypass mode. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) + EMU_DCDCModeSet(emuDcdcMode_Bypass); +#endif +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) + if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { + /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. + * Full description of errata fix can be found in the errata document. */ + __disable_irq(); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); + *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); + } +#endif + +#if defined(ERRATA_FIX_EMU_E108_ENABLE) + /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ + __disable_irq(); + *(volatile uint32_t *)0x400C80E4 = 0; +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + +#if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) + /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { + BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); + /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement + * before entering EM4. */ + uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { + } + CMU->HFRCOCTRL = freqCal; + CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; + while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { + } + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + __NOP(); + } + } +#endif + + EMU_EM4PresleepHook(); + EMU_EFPEM4PresleepHook(); + + for (i = 0; i < 4; i++) { +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + EMU->EM4CTRL = em4seq2; + EMU->EM4CTRL = em4seq3; + } + EMU->EM4CTRL = em4seq2; +#else + EMU->CTRL = em4seq2; + EMU->CTRL = em4seq3; + } + EMU->CTRL = em4seq2; +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @details + * This function waits after the EM4 entry request to make sure the CPU + * is properly shutdown or the EM4 entry failed. + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + ******************************************************************************/ +void EMU_EnterEM4Wait(void) +{ + EMU_EnterEM4(); + + // The EM4 entry waiting loop should take 4 cycles by loop minimally (Compiler dependent). + // We would then wait for (EMU_EM4_ENTRY_WAIT_LOOPS * 4) clock cycles. + for (uint16_t i = 0; i < EMU_EM4_ENTRY_WAIT_LOOPS; i++) { + __NOP(); + } +} + +#if defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Enter energy mode 4 hibernate (EM4H). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4H(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); +#endif + EMU_EnterEM4(); +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 shutoff (EM4S). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4S(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); +#endif + EMU_EnterEM4(); +} +#endif + +/***************************************************************************//** + * @brief + * Power down memory block. + * + * @param[in] blocks + * Specifies a logical OR of bits indicating memory blocks to power down. + * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot + * be disabled. See the reference manual for available + * memory blocks for a device. + * + * @note + * Only a POR reset can power up the specified memory block(s) after power down. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. + ******************************************************************************/ +void EMU_MemPwrDown(uint32_t blocks) +{ +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; +#else + (void)blocks; +#endif +} + +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will only power down blocks which are completely enclosed + * by the memory range given by [start, end). + * + * This is an example to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of the first RAM block is device-specific. + * See the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * Only a reset can power up the specified memory block(s) after power down + * on a series 0 device. The specified memory block(s) will stay off + * until a call to EMU_RamPowerUp() is done on series 1/2. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. This address is + * exclusive. If this parameter is 0, all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + (void) start; + + if (end == 0U) { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down. + if (end > RAM0_END) { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 + // Block 0 is 16 kB and cannot be powered off. + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 + // Block 0 is 4 kB and cannot be powered off. + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. + // This condition happens when the block 0 disable bit flag is available in the retention control register. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i); + } +#elif defined(RAM0_BLOCKS) + // These platforms have equally-sized RAM blocks and block 0 cannot be powered down. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); + } +#endif + } + + // Power down the selected blocks. +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_maskDmem0RetnCtrl(mask); +#else + // These devices are unable to power down RAM blocks. + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) { + for (unsigned i = 0; i < RAM1_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif + +#if defined(RAM2_MEM_END) + mask = 0; + if (end > RAM2_MEM_END) { + for (unsigned i = 0; i < RAM2_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; + } + } + EMU->RAM2CTRL |= mask; +#endif +} + +/***************************************************************************//** + * @brief + * Power up all available RAM memory blocks. + * + * @details + * This function will power up all the RAM blocks on a device, this means + * that the RAM blocks are retained in EM2/EM3. Note that this functionality + * is not supported on Series 0 devices. Only a reset will power up the RAM + * blocks on a series 0 device. + ******************************************************************************/ +void EMU_RamPowerUp(void) +{ +#if defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM1CTRL_MASK) + EMU->RAM1CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM2CTRL_MASK) + EMU->RAM2CTRL = 0x0UL; +#endif +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_zeroDmem0RetnCtrl(); +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * A peripheral select mask. Use | operator to select multiple peripherals, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = (uint32_t)periMask + & (uint32_t)emuPeripheralRetention_ALL; +} +#endif + +/***************************************************************************//** + * @brief + * Update EMU module with CMU oscillator selection/enable status. + * + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). + ******************************************************************************/ +void EMU_UpdateOscConfig(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Energy mode 01 voltage scaling hook function. + * + * @param[in] voltage + * Voltage scaling level requested. + * + * @details + * This function is called by EMU_VScaleEM01 to let EFP know that voltage scaling + * is requested. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage) +{ + (void)voltage; +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0 or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is primarily needed by the @ref cmu. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* VSCALE frequency is HFSRCCLK. */ + if (clockFrequency == 0U) { +#if defined(_SILICON_LABS_32B_SERIES_2) + hfSrcClockFrequency = SystemSYSCLKGet(); +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; +#endif + } else { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); + } else { + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is useful for upscaling before programming Flash from @ref msc + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfFreq; + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + if (EMU_VScaleGet() == voltage) { + /* Voltage is already at the correct level. */ + return; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + (void)wait; + CORE_DECLARE_IRQ_STATE; + + hfFreq = SystemSYSCLKGet(); + hfSrcClockFrequency = hfFreq; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + CORE_ENTER_CRITICAL(); + EMU->IF_CLR = EMU_IF_VSCALEDONE; + EMU_EFPEM01VScale(voltage); + EMU->CMD = vScaleEM01Cmd(voltage); + + // Note that VSCALEDONE interrupt flag must be used instead of VSCALEBUSY + // because hardware does not set the VSCALEBUSY flag immediately. + while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) + && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { + EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); + // Wait for VSCALE completion. + // SRAM accesses will fault the core while scaling. + } + CORE_EXIT_CRITICAL(); + +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfFreq = SystemHFClockGet(); + hfSrcClockFrequency = hfFreq * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + + if (wait) { + EMU_VScaleWait(); + } +#endif + + if (voltage == emuVScaleEM01_HighPerformance) { + /* Update wait states after scaling up voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] bupdInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) +{ + uint32_t reg; + + /* Set the power connection configuration. */ + reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK + | _EMU_PWRCONF_VOUTSTRONG_MASK + | _EMU_PWRCONF_VOUTMED_MASK + | _EMU_PWRCONF_VOUTWEAK_MASK); + + reg |= bupdInit->resistor + | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) + | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) + | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); + + EMU->PWRCONF = reg; + + /* Set the backup domain inactive mode configuration. */ + reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); + reg |= (bupdInit->inactivePower); + EMU->BUINACT = reg; + + /* Set the backup domain active mode configuration. */ + reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); + reg |= (bupdInit->activePower); + EMU->BUACT = reg; + + /* Set the power control configuration */ + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK + | _EMU_BUCTRL_BODCAL_MASK + | _EMU_BUCTRL_STATEN_MASK + | _EMU_BUCTRL_EN_MASK); + + /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and + release reset. */ + reg |= bupdInit->probe + | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) + | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) + | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); + + /* Enable configuration. */ + EMU->BUCTRL = reg; + + /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ + EMU_BUPinEnable(bupdInit->enable); + + /* If enable is true, release BU reset. If not, keep reset asserted. */ + BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold value. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 8); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) + | (value << _EMU_BUACT_BUEXTHRES_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) + | (value << _EMU_BUINACT_BUENTHRES_SHIFT); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold Range. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 4); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) + | (value << _EMU_BUACT_BUEXRANGE_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) + | (value << _EMU_BUINACT_BUENRANGE_SHIFT); + break; + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] buInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) +{ + uint32_t reg = 0; + + /* Set the backup power configuration. */ + reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + reg |= (uint32_t)(buInit->inactivePwrCon); + reg |= (uint32_t)(buInit->activePwrCon); + reg |= (uint32_t)(buInit->pwrRes); + reg |= (uint32_t)(buInit->voutRes); + reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); + reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +/***************************************************************************//** + * @brief + * Disable Main Backup Power Domain comparator. + * + * @param[in] disableMainBuComparator + * True to disable main BU comparator. + ******************************************************************************/ +void EMU_BUDisMaxCompSet(bool disableMainBuComparator) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); + reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when not in Backup mode. + * + * @param[in] inactPwrCon + * Inactive power configuration. + ******************************************************************************/ +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); + reg |= (uint32_t)(inactPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when in Backup mode. + * + * @param[in] actPwrCon + * Active power configuration. + ******************************************************************************/ +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); + reg |= (uint32_t)(actPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/***************************************************************************//** + * @brief + * Power domain resistor selection. + * + * @param[in] pwrRes + * Resistor selection. + ******************************************************************************/ +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); + reg |= (uint32_t)(pwrRes); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/***************************************************************************//** + * @brief + * B_VOUT resistor select. + * + * @param[in] resistorSel + * Resistor selection. + ******************************************************************************/ +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); + reg |= (uint32_t)(resistorSel); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +/***************************************************************************//** + * @brief + * Enable BU_VIN probing + * + * @param[in] enable + * True to enable BU_VIN probing. False to disable. + ******************************************************************************/ +void EMU_BUBuVinProbeEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); + reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_STATEN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode status export. + * + * @param[in] enable + * True to enable status export. False to disable. + ******************************************************************************/ +void EMU_BUStatEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); + reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_EN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode. + * + * @param[in] enable + * True to enable backup mode. False to disable. + ******************************************************************************/ +void EMU_BUEnableSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); + reg |= (enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum { + dcdcTrimMode_EM234H_LP = 0, +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Load DCDC calibration constants from the DI page. A constant means that calibration + * data that does not change depending on other configuration parameters. + * + * @return + * False if calibration registers are locked. + ******************************************************************************/ +static bool dcdcConstCalibrationLoad(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t val; + volatile uint32_t *reg; + + /* DI calibration data in Flash. */ + volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); + volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); + volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); + volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); + volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); + volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); + + if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { + val = *(diCal_EMU_DCDCLNFREQCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLNVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM0 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM1 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; + *reg = val; + + return true; + } + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + +#else + return true; +#endif +} + +/***************************************************************************//** + * @brief + * Set recommended and validated current optimization and timing settings. + * + ******************************************************************************/ +static void dcdcValidatedConfigSet(void) +{ + uint32_t lnForceCcm; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t dcdcTiming; + SYSTEM_ChipRevision_TypeDef rev; +#endif + + /* Enable duty cycling of the bias. */ + EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; + + /* Set low-noise RCO for LNFORCECCM configuration. + * LNFORCECCM is default 1 for EFR32 + * LNFORCECCM is default 0 for EFM32 + */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + if (lnForceCcm != 0U) { + /* 7 MHz is recommended for LNFORCECCM = 1. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } else { + /* 3 MHz is recommended for LNFORCECCM = 0. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS + | EMU_DCDCMISCCTRL_LPCMPHYSHI; + + SYSTEM_ChipRevisionGet(&rev); + if ((rev.major == 1) + && (rev.minor < 3) + && (errataFixDcdcHsState == errataFixDcdcHsInit)) { + /* LPCMPWAITDIS = 1 */ + EMU_DCDCSMCTRL |= 1; + + dcdcTiming = EMU->DCDCTIMING; + dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK + | _EMU_DCDCTIMING_LNWAIT_MASK + | _EMU_DCDCTIMING_BYPWAIT_MASK); + + dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) + | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) + | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); + EMU->DCDCTIMING = dcdcTiming; + + errataFixDcdcHsState = errataFixDcdcHsTrimSet; + } +#endif +} + +/***************************************************************************//** + * @brief + * Compute current limiters: + * LNCLIMILIMSEL: LN current limiter threshold + * LPCLIMILIMSEL: LP current limiter threshold + * DCDCZDETCTRL: zero detector limiter threshold + ******************************************************************************/ +static void currentLimitersUpdate(void) +{ + uint32_t lncLimSel; + uint32_t zdetLimSel; + uint32_t pFetCnt; + uint16_t maxReverseCurrent_mA; + + /* 80 mA as recommended peak in Application Note AN0948. + The peak current is the average current plus 50% of the current ripple. + Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also + a constant, lpcLimImSel = 1. The following calculation is provided + for documentation only. */ + const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) + / (5 * (DCDC_LP_PFET_CNT + 1))) + - 1; + const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; + + /* Get enabled PFETs. */ + pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) + >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; + + /* Compute the LN current limiter threshold from the nominal user input current and + LN PFETCNT as described in the register description for + EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ + lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) + + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) + / (5U * (pFetCnt + 1U))) + - 1U; + + /* Saturate the register field value. */ + lncLimSel = SL_MIN(lncLimSel, + _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); + + lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); + EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); + + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) + | (lncLimSel | lpcLimSel); + + /* Compute the reverse current limit threshold for the zero detector from the user input + maximum reverse current and LN PFETCNT as described in the register description + for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ + if (dcdcReverseCurrentControl >= 0) { + /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ + maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; + + zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) + + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) + / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); + /* Saturate the register field value. */ + zdetLimSel = SL_MIN(zdetLimSel, + _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK + >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); + + zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); + + EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) + | zdetLimSel; + } +} + +/***************************************************************************//** + * @brief + * Set static variables that hold the user set maximum peak current + * and reverse current. Update limiters. + * + * @param[in] maxCurrent_mA + * Set the maximum peak current that the DCDC can draw from the power source. + * @param[in] reverseCurrentControl + * Reverse the current control as defined by + * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. + ******************************************************************************/ +static void userCurrentLimitsSet(uint32_t maxCurrent_mA, + EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) +{ + dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; + dcdcReverseCurrentControl = reverseCurrentControl; +} + +/***************************************************************************//** + * @brief + * Set DCDC low noise compensator control register. + * + * @param[in] comp + * Low-noise mode compensator trim setpoint. + ******************************************************************************/ +static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) +{ + switch (comp) { + case emuDcdcLnCompCtrl_1u0F: + EMU->DCDCLNCOMPCTRL = 0x57204077UL; + break; + + case emuDcdcLnCompCtrl_4u7F: + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback + * attenuation, and DEVINFOREV. + * + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpCmpBias + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. + ******************************************************************************/ +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) +{ + uint32_t lpcmpHystSel; +#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + (void)lpAttenuation; +#endif + + /* Get calibration data revision. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); + + /* Load LPATT indexed calibration data. */ + if (devinfoRev < 4) { + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; + + if (lpAttenuation) { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; + } else { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; + } + } else +#endif + { + /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; + switch (lpCmpBias) { + case 0: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; + break; + + case 1: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; + break; + + case 2: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; + break; + + case 3: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + } + + /* Set trims. */ + if (trimMode == dcdcTrimMode_EM234H_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + if (trimMode == dcdcTrimMode_EM01_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to look up in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); + switch (switchVal) { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @note + * Do not call this function if the power circuit is configured for NODCDC as + * described in the Power Configurations section of the Reference Manual. + * Instead, call @ref EMU_DCDCPowerOff(). + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + uint32_t lpCmpBiasSelEM234H; + +#if defined(_EMU_PWRCFG_MASK) + /* Set the external power configuration. This enables writing to the other + DCDC registers. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; + + /* EMU->PWRCFG is write-once and POR reset only. Check that + the desired power configuration was set. */ + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + /* If this assert triggers unexpectedly, power cycle the + kit to reset the power configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } +#endif + + /* Load DCDC calibration data from the DI page. */ + (void)dcdcConstCalibrationLoad(); + + /* Check current parameters */ + EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); + EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); + + if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200 mA. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); + } +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10 mA is supported for EM01-LP mode. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); + } +#endif + else { + /* No need to check the EM01 load limit. */ + } + + /* EM2/3/4 current above 10 mA is not supported. */ + EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); + + if (dcdcInit->em234LoadCurrent_uA < 75U) { + lpCmpBiasSelEM234H = 0; + } else if (dcdcInit->em234LoadCurrent_uA < 500U) { + lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { + lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else { + lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } + + /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ + + /* Set DCDC low-power mode comparator bias selection. */ + + /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. + => Updates DCDCMISCCTRL_LNFORCECCM */ + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK + | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) + | ((uint32_t)lpCmpBiasSelEM234H + | (dcdcInit->reverseCurrentControl >= 0 + ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10 mA EM01-LP current is supported. */ + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; +#endif + + /* 2. Set recommended and validated current optimization settings. + <= Depends on LNFORCECCM + => Updates DCDCLNFREQCTRL_RCOBAND */ + dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; + dcdcValidatedConfigSet(); + + /* 3. Updated static currents and limits user data. + Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ + userCurrentLimitsSet(dcdcInit->maxCurrent_mA, + dcdcInit->reverseCurrentControl); + + /* 4. Optimize LN slice based on the given user input load current. + <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND + <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl + => Updates DCDCMISCCTRL_P/NFETCNT + => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL + => Updates DCDCZDETCTRL_ZDETILIMSEL */ + EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); + + /* ======================================================= */ + + /* Set DCDC low noise mode compensator control register. */ + compCtrlSet(dcdcInit->dcdcLnCompCtrl); + + /* Set DCDC output voltage. */ + if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) + /* Select analog peripheral power supply. This must be done before + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower ? 1 : 0); +#endif + +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set EM0 DCDC operating mode. Output voltage set in + @ref EMU_DCDCOutputVoltageSet() above takes effect if mode + is changed from bypass/off mode. */ + EMU_DCDCModeSet(dcdcInit->dcdcMode); + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + /* Select the analog peripheral power supply. This must be done after + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower + == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + ******************************************************************************/ +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Wait for any previous write sync to complete and read DCDC mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + + /* Enable bypass current limiter when not in bypass mode to prevent + excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ + if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); + } + + if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { + /* Mode already set. If already in bypass, make sure the bypass current limiter + is disabled. */ + if (dcdcMode == emuDcdcMode_Bypass) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); + } + return; + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /* Fix for errata DCDC_E203. */ + if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) + && (dcdcMode == emuDcdcMode_LowNoise)) { + errataFixDcdcHsState = errataFixDcdcHsBypassLn; + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_80) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Fix for errata DCDC_E204. */ + if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) + && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { + /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ + EMU_IntClear(EMU_IFC_DCDCLNRUNNING); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; + while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { + } + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) + | (uint32_t)dcdcMode; + + /* Disable bypass current limiter after bypass mode is entered. + Enable the limiter if any other mode is entered. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, + _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, + dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); + + if (dcdcLocked) { + EMU_PowerLock(); + } +} + +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +/***************************************************************************//** + * @brief + * Set DCDC Mode EM23 operating mode. + * + * @param[in] dcdcModeEM23 + * DCDC mode EM23. + ******************************************************************************/ +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23) +{ + bool dcdcLocked; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) + | (uint32_t)dcdcModeEM23; + + if (dcdcLocked) { + EMU_PowerLock(); + } +} +#endif + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @details + * This function powers off the DCDC controller. This function should only be + * used if the external power circuit is wired for no DCDC. If the external power + * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the + * DCDC in bypass mode to disable DCDC. + * + * @return + * Return false if the DCDC could not be disabled. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + bool dcdcModeSet; + +#if defined(_EMU_PWRCFG_MASK) + /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif + + /* Select DVDD as input to the digital regulator. */ +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required + mode could be set. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; + + dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); + EFM_ASSERT(dcdcModeSet); + + return dcdcModeSet; +} + +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode. + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise, the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, + bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)((uint32_t) + (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) + ((EMU->DCDCLNFREQCTRL + & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { + } + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { + EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } else { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } else { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band.*/ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + +/***************************************************************************//** + * @brief + * Set the DCDC output voltage. + * + * @note + * The DCDC is not characterized for the entire valid output voltage range. + * For that reason an upper limit of 3.0V output voltage is enforced. + * + * @param[in] mV + * Target DCDC output voltage in mV. + * + * @param[in] setLpVoltage + * Update LP voltage + * + * @param[in] setLnVoltage + * Update LN voltage + * + * @return + * True if the mV parameter is valid. + ******************************************************************************/ +bool EMU_DCDCOutputVoltageSet(uint32_t mV, + bool setLpVoltage, + bool setLnVoltage) +{ +#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + + bool validOutVoltage; + bool attenuationSet; + uint32_t mVlow = 0; + uint32_t mVhigh = 0; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; + + /* Check that the set voltage is within valid range. + Voltages are obtained from the data sheet. */ + validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX); + + if (!validOutVoltage) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Set attenuation to use and low/high range. */ + attenuationSet = mV > 1800U; + if (attenuationSet) { + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } else { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } + + /* Get 2-point calibration data from DEVINFO. */ + + /* LN mode */ + if (attenuationSet) { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; + } else { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; + } + + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) + ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) + ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif + + /* Calculate output voltage trims. */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); + } + + if (setLpVoltage) { + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* LP VREF is that maximum of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Optimize the DCDC slice count based on the estimated average load current + * in EM0. + * + * @param[in] em0LoadCurrentmA + * Estimated average EM0 load current in mA. + ******************************************************************************/ +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) +{ + uint32_t sliceCount = 0; + uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; + + /* Set the recommended slice count. */ + if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { + if (em0LoadCurrentmA < 20U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 10U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 40U) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else { + /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended + configuration. */ + EFM_ASSERT(false); + } + + /* The selected slices are PSLICESEL + 1. */ + sliceCount--; + + /* Apply slice count to both N and P slice. */ + sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT + | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK + | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) + | sliceCount; + + /* Update the current limiters. */ + currentLimitersUpdate(); +} + +/***************************************************************************//** + * @brief + * Set DCDC Low-noise RCO band. + * + * @param[in] band + * RCO band to set. + ******************************************************************************/ +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) +{ + uint32_t forcedCcm; + forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + + /* DCM mode supports up to 4 MHz LN RCO. */ + EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) + || (forcedCcm != 0U)); + + EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Update slice configuration as this depends on the RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC Boost regulator. + * + * @param[in] dcdcBoostInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); + DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT); + DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM23 << _DCDC_BSTEM23CTRL_IPKVAL_SHIFT); + + EMU_BoostExternalShutdownEnable(dcdcBoostInit->externalShutdownEn); + + EMU_DCDCModeSet(emuDcdcMode_Regulation); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Set EM01 mode Boost Peak Current setting. + * + * @param[in] boostPeakCurrentEM01 + * Boost Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, + _DCDC_BSTEM01CTRL_IPKVAL_MASK, + ((uint32_t)boostPeakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT)); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +/***************************************************************************//** + * @brief + * Enable/disable Boost External Shutdown Mode. + * + * @param[in] enable + * The boost DC-DC converter can be activated or deactivated + * from a dedicated BOOST_EN pin on the device if enable is true. + ******************************************************************************/ +void EMU_BoostExternalShutdownEnable(bool enable) +{ + if (enable) { + EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; + } else { + EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; + } +} +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Indicate that the DCDC peripheral bus clock enable has changed allowing + * RAIL to react accordingly. + * + * @details + * This function is called after DCDC has been enabled or disabled. + * The function implementation does not perform anything, but it is SL_WEAK + * so that it can use the RAIL version if needed. + ******************************************************************************/ +SL_WEAK void EMU_DCDCUpdatedHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + * @return + * Returns the status of the DCDC mode set operation. + * @verbatim + * SL_STATUS_OK - Operation completed successfully. + * SL_STATUS_TIMEOUT - Operation EMU DCDC set mode timeout. + * @endverbatim + ******************************************************************************/ +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + sl_status_t error = SL_STATUS_OK; + uint32_t timeout = 0; + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + if (dcdcMode == emuDcdcMode_Bypass) { +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT; + + if (currentDcdcMode != emuDcdcMode_Bypass) { + /* Switch to BYPASS mode if it is not the current mode */ + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for BYPASS switch enable. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_CLR = DCDC_EN_EN; +#endif + } else { + while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for VREGIN voltage to rise above threshold. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } else { + DCDC->IF_CLR = DCDC_IF_REGULATION; + DCDC->CTRL_SET = DCDC_CTRL_MODE; + timeout = 0; + while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for DCDC to complete it's startup. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } + } + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + return error; +} +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT || EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold + << _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT) + | EMU_VREGVDDCMPCTRL_VREGINCMPEN; + +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL | DCDC_SYNCBUSY_EM01CTRL0 | DCDC_SYNCBUSY_EM23CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK + | _DCDC_CTRL_DCMONLYEN_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT) + | ((uint32_t)(dcdcInit->dcmOnlyEn ? 1U : 0U) << _DCDC_CTRL_DCMONLYEN_SHIFT); +#else + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT); +#endif + DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT); + DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM23 << _DCDC_EM23CTRL0_IPKVAL_SHIFT); + + EMU_DCDCModeSet(dcdcInit->mode); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @return + * Returns true. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + EMU_DCDCModeSet(emuDcdcMode_Bypass); + return true; +} + +/***************************************************************************//** + * @brief + * Set EMO1 mode Peak Current setting. + * + * @param[in] peakCurrentEM01 + * Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + +#if defined(_DCDC_EN_EN_MASK) + bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0); + DCDC->EN_SET = DCDC_EN_EN; +#endif + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_EM01CTRL0_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_EM01CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + + BUS_RegMaskedWrite(&DCDC->EM01CTRL0, + _DCDC_EM01CTRL0_IPKVAL_MASK, + ((uint32_t)peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT)); + +#if defined(_DCDC_EN_EN_MASK) + if (!dcdcWasEnabled) { + DCDC->EN_CLR = DCDC_EN_EN; + } +#endif + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +/***************************************************************************//** + * @brief + * Set PFMX mode Peak Current setting. + * + * @param[in] value + * Peak load current coefficient in PFMX mode. + ******************************************************************************/ +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + /* Verification that the parameter is in range. */ + /* if not, restrict value to maximum allowed. */ + EFM_ASSERT(value <= (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)); + if (value > (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)) { + value = (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT); + } + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK) + | value << _DCDC_PFMXCTRL_IPKVAL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKVAL_MASK */ + +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +/***************************************************************************//** + * @brief + * Set Ton_max timeout control. + * + * @param[in] value + * Maximum time for peak current detection. + ******************************************************************************/ +void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) + | value << _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK */ +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) + +/***************************************************************************//** + * @brief + * Get the calibrated threshold value. + * + * @details + * All VMON channels have two calibration fields in the DI page that + * describes the threshold at 1.86 V and 2.98 V. This function will convert + * the uncalibrated input voltage threshold in millivolts into a calibrated + * threshold. + * + * @param[in] channel + * A VMON channel. + * + * @param[in] threshold + * A desired threshold in millivolts. + * + * @return + * A calibrated threshold value to use. The first digit of the return value is placed + * in the "fine" register fields while the next digits are placed in the + * "coarse" register fields. + ******************************************************************************/ +static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, + int threshold) +{ + uint32_t tDiff = 0; + uint32_t tLow = 0; + uint32_t tHigh = 0; + uint32_t calReg; + + /* Get calibration values for 1.86 V and 2.98 V */ + switch (channel) { + case emuVmonChannel_AVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_ALTAVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_DVDD: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_IOVDD0: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + tDiff = tHigh - tLow; + if (tDiff > 0) { + /* Calculate threshold. + * + * Note that volt is used in the reference manual. However, the results + * should be in millivolts. The precision of Va and Vb are increased in the + * calculation instead of using floating points. + */ + uint32_t va = (1120U * 100U) / (tDiff); + uint32_t vb = (1860U * 100U) - (va * tLow); + // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. + if (va != 0) { + /* Round the threshold to the nearest integer value. */ + return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; + } + } + + /* Uncalibrated device guard. */ + return (uint32_t)threshold; +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel. + * + * @details + * Initialize a VMON channel without hysteresis. If the channel supports + * separate rise and fall triggers, both thresholds will be set to the same + * value. The threshold will be converted to a register field value based + * on calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON initialization structure. + ******************************************************************************/ +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) +{ + uint32_t thresholdCoarse, thresholdFine; + uint32_t threshold; + + EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); + + threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); + thresholdFine = threshold % 10U; + thresholdCoarse = threshold / 10U; + + /* Saturate the threshold to maximum values. */ + if (thresholdCoarse > 0xFU) { + thresholdCoarse = 0xF; + thresholdFine = 9; + } + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_ALTAVDD: + EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_DVDD: + EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); + break; + case emuVmonChannel_IOVDD0: + EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); + break; +#endif + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel with hysteresis (separate rise and fall triggers). + * + * @details + * Initialize a VMON channel which supports hysteresis. The AVDD channel is + * the only channel to support separate rise and fall triggers. The rise and + * fall thresholds will be converted to a register field value based on the + * calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON hysteresis initialization structure. + ******************************************************************************/ +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) +{ + uint32_t riseThreshold; + uint32_t fallThreshold; + + /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ + EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); + EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); + /* The fall threshold has to be lower than rise threshold. */ + EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); + + riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); + fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Enable or disable a VMON channel. + * + * @param[in] channel + * A VMON channel to enable/disable. + * + * @param[in] enable + * Indicates whether to enable or disable. + ******************************************************************************/ +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) +{ + uint32_t volatile * reg; + uint32_t bit; + + switch (channel) { + case emuVmonChannel_AVDD: + reg = &(EMU->VMONAVDDCTRL); + bit = _EMU_VMONAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + reg = &(EMU->VMONALTAVDDCTRL); + bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_DVDD: + reg = &(EMU->VMONDVDDCTRL); + bit = _EMU_VMONDVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_IOVDD0: + reg = &(EMU->VMONIO0CTRL); + bit = _EMU_VMONIO0CTRL_EN_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + reg = &(EMU->VMONIO1CTRL); + bit = _EMU_VMONIO1CTRL_EN_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + reg = &(EMU->VMONBUVDDCTRL); + bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; + break; +#endif + default: + EFM_ASSERT(false); + return; + } + + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the status of a voltage monitor channel. + * + * @param[in] channel + * A VMON channel to get the status for. + * + * @return + * A status of the selected VMON channel. True if the channel is triggered. + ******************************************************************************/ +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) +{ + uint32_t bit; + switch (channel) { + case emuVmonChannel_AVDD: + bit = _EMU_STATUS_VMONAVDD_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + bit = _EMU_STATUS_VMONALTAVDD_SHIFT; + break; + case emuVmonChannel_DVDD: + bit = _EMU_STATUS_VMONDVDD_SHIFT; + break; + case emuVmonChannel_IOVDD0: + bit = _EMU_STATUS_VMONIO0_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + bit = _EMU_STATUS_VMONIO1_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + bit = _EMU_STATUS_VMONBUVDD_SHIFT; + break; +#endif + default: + bit = 0; + EFM_ASSERT(false); + break; + } + + return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; +} +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/***************************************************************************//** + * @brief + * Adjust the bias refresh rate. + * + * @details + * This function is only meant to be used under high-temperature operation on + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will + * increase the typical current consumption. See application note 1027 + * and errata documents for more details. + * + * @param [in] mode + * The new bias refresh rate. + ******************************************************************************/ +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) +{ + uint32_t freq = 0x2u; + bool emuTestLocked = false; + + if (mode == emuBiasMode_1KHz) { + freq = 0x0u; + } + + if (EMU_TESTLOCK == 0x1u) { + emuTestLocked = true; + EMU_TESTLOCK = 0xADE8u; + } + + if (mode == emuBiasMode_Continuous) { + EMU_BIASCONF &= ~0x74u; + } else { + EMU_BIASCONF |= 0x74u; + } + + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; + + if (emuTestLocked) { + EMU_TESTLOCK = 0u; + } +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/***************************************************************************//** + * @brief + * Get temperature in degrees Celsius + * + * @return + * Temperature in degrees Celsius + ******************************************************************************/ +float EMU_TemperatureGet(void) +{ +#if defined(_EMU_TEMP_TEMPLSB_MASK) + return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) + >> _EMU_TEMP_TEMPLSB_SHIFT) + ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +#else + uint32_t val1; + uint32_t val2; + float tempCo; + uint32_t diTemp, diEmu; + + // Calculate calibration temp based on DI page values + diTemp = ((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); + diEmu = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); + tempCo = EMU_TEMPCO_CONST + (diEmu / 100.0f); + + // Read temperature twice to ensure a stable value + do { + val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + } while (val1 != val2); + + return diTemp + tempCo * ((int) diEmu - (int) val1); +#endif +} +#endif // defined(_EMU_TEMP_TEMP_MASK) + +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +/***************************************************************************//** + * @brief + * Enable/disable EFP Direct Mode. + * + * @param[in] enable + * True to enable direct mode. + ******************************************************************************/ +void EMU_EFPDirectModeEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive Decouple voltage. + * + * @details + * Once set, internal LDO will be disabled, and the EMU will control EFP for + * voltage-scaling. Note that because this bit disables the internal LDO + * powering the core, it should not be set until after EFP's DECOUPLE output has + * been configured and enabled. + * + * @param[in] enable + * True to enable EFP to drive Decouple voltage. + ******************************************************************************/ +void EMU_EFPDriveDecoupleSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive DVDD voltage. + * + * @details + * Set this if EFP's DCDC output is powering DVDD supply. This mode assumes that + * internal DCDC is not being used. + * + * @param[in] enable + * True to enable EFP to drive DVDD voltage. + ******************************************************************************/ +void EMU_EFPDriveDvddSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; + } +} +#endif + +/** @} (end addtogroup emu) */ +#endif /* __EM_EMU_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c index bcfafa1..603ca03 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c @@ -1,1395 +1,1395 @@ -/***************************************************************************//** - * @file - * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_eusart.h" -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) -#include "em_cmu.h" -#include - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -#if defined(EUART_PRESENT) - #define EUSART_REF_VALID(ref) ((ref) == EUART0) - #define EUSART_EM2_CAPABLE(ref) (true) - #define EUSART_RX_FIFO_SIZE 4u -#elif defined(EUSART_PRESENT) - #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1) - #define EUSART_RX_FIFO_SIZE 16u -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ -#if defined(EUSART_DALICFG_DALIEN) -static uint8_t dali_tx_nb_packets[EUSART_COUNT]; -static uint8_t dali_rx_nb_packets[EUSART_COUNT]; -#endif /* EUSART_DALICFG_DALIEN */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart); - -static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_UartInit_TypeDef *init, - const EUSART_IrDAInit_TypeDef *irdaInit, - const EUSART_DaliInit_TypeDef *daliInit); - -#if defined(EUSART_PRESENT) -static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_SpiInit_TypeDef *init); -#endif - -/***************************************************************************//** - * Wait for ongoing sync of register(s) to the low-frequency domain to complete. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param mask A bitmask corresponding to SYNCBUSY register defined bits, - * indicating registers that must complete any ongoing - * synchronization. - ******************************************************************************/ -__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask) -{ - // Wait for any pending previous write operation to have been completed - // in the low-frequency domain. - while ((eusart->SYNCBUSY & mask) != 0U) { - } -} - -/***************************************************************************//** - * Calculate baudrate for a given reference frequency, clock division, - * and oversampling rate. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - EUSART_OVS_TypeDef ovs); - -/***************************************************************************//** - * Execute the EUSART peripheral disabling sequence. - ******************************************************************************/ -__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initializes the EUSART when used with the high frequency clock. - ******************************************************************************/ -void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(init); - - // Assert features specific to HF. - // The oversampling must not be disabled when using a high frequency clock. - EFM_ASSERT(init->oversampling != eusartOVS0); - - // Uart mode only supports up to 9 databits frame. - EFM_ASSERT(init->databits <= eusartDataBits9); - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, init, NULL, NULL); -} - -/***************************************************************************//** - * Initializes the EUSART when used with the low frequency clock. - * - * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral - * clock frequency must be at least three times higher than the - * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), - * thus 32768 / 3 ~ 9600 baudrate. - ******************************************************************************/ -void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) -{ - // Make sure the module exists and is Low frequency capable. - EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // Init structure must be provided. - EFM_ASSERT(init); - - // Assert features specific to LF. - // LFXO, LFRCO, ULFRCO can be a clock source in LF. -#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) - { - CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL; -#if defined(EUART_PRESENT) - if (eusart == EUART0) { - clock_source = CMU_ClockSelectGet(cmuClock_EUART0); - } -#endif -#if defined(EUSART_PRESENT) && defined(EUSART0) - if (eusart == EUSART0) { - clock_source = CMU_ClockSelectGet(cmuClock_EUSART0); - } -#endif - - EFM_ASSERT( - (clock_source == cmuSelect_ULFRCO) - || (clock_source == cmuSelect_LFXO) - || (clock_source == cmuSelect_LFRCO) - || (clock_source == cmuSelect_EM23GRPACLK) -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - || (clock_source == cmuSelect_EM01GRPCCLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK or EM01GRPCCLK */ -#endif - ); - } -#endif - // Uart mode only supports up to 9 databits frame. - EFM_ASSERT(init->databits <= eusartDataBits9); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(init->oversampling == eusartOVS0); - // The Majority Vote must be disabled when using a low frequency clock. - EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable); - // Number of stop bits can only be 1 or 2 in LF. - EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2)); - // In LF, max baudrate is 9600. See Note #1. - EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0); - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, init, NULL, NULL); -} - -/***************************************************************************//** - * Initializes the EUSART when used in IrDA mode with the high or low - * frequency clock. - ******************************************************************************/ -void EUSART_IrDAInit(EUSART_TypeDef *eusart, - const EUSART_IrDAInit_TypeDef *irdaInit) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(irdaInit); - - if (irdaInit->irDALowFrequencyEnable) { - // Validate the low frequency capability of the EUSART instance. - EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0); - // Number of stop bits can only be 1 or 2 in LF. - EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2)); - // In LF, max baudrate is 9600. See Note #1. - EFM_ASSERT(irdaInit->init.baudrate <= 9600); - EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable); - } else { - EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0); - // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. - EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000); - } - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL); -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initializes the EUSART when used in SPI mode. - ******************************************************************************/ -void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(init); - if (init->master) { - EFM_ASSERT(init->bitRate <= 20000000); - - if (init->advancedSettings) { - EFM_ASSERT(!(init->advancedSettings->prsClockEnable)); - } - } else { - EFM_ASSERT(init->bitRate <= 10000000); - if (init->advancedSettings && init->advancedSettings->forceLoad) { - // If baud-rate is more than 5MHz, a value of 4 is recommended, any values - // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz, - // value of 5 is recommended, values higher than 5 can be used but it may make the load - // error easy to occur. The recommended values for frequency bands should be sufficient - // to work all the time. - EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4) - || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5)); - } - } - - EUSART_SyncInitCommon(eusart, init); -} - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Initializes the EUSART when used in DALI mode with the high or low - * frequency clock. - * - * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral - * clock frequency must be at least three times higher than the - * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), - * thus 32768 / 3 ~ 9600 baudrate. - ******************************************************************************/ -void EUSART_DaliInit(EUSART_TypeDef *eusart, - const EUSART_DaliInit_TypeDef *daliInit) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(daliInit); - - if (daliInit->init.loopbackEnable) { - // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, - // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should - // be set the same as DALITXDATABITS. - EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT) - == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT)); - } - - if (daliInit->daliLowFrequencyEnable) { - // Validate the low frequency capability of the EUSART instance. - EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(daliInit->init.oversampling == eusartOVS0); - // In LF, max baudrate is 9600. See Note #1. - // but manchester is running at 2x clock 9600 => 4800 - EFM_ASSERT(daliInit->init.baudrate <= 4800); - } else { - EFM_ASSERT(daliInit->init.oversampling != eusartOVS0); - // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. - // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps - EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600); - } - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit); -} -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure the EUSART to its reset state. - ******************************************************************************/ -void EUSART_Reset(EUSART_TypeDef *eusart) -{ - // 1. Properly disable the module - EUSART_Disable(eusart); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - // Manual toggling tx_sclk_mst to synchronize handshake - // when switching from SPI master to other modes - // so module is disabling correctly. - uint32_t forcedClkCycle = 4u; - - while (forcedClkCycle--) { - eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK; - eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK; - } -#endif - // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set). - // Set all configurable register to its reset value. - // Note: Program desired settings to all registers that have names ending with CFG in the following sequence: - // a. CFG2 -#if defined(EUSART_PRESENT) - eusart->CFG2 = _EUSART_CFG2_RESETVALUE; -#endif - // b. CFG1 - eusart->CFG1 = _EUSART_CFG1_RESETVALUE; - // c. CFG0 - eusart->CFG0 = _EUSART_CFG0_RESETVALUE; - // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence) - eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE; -#if defined(EUSART_PRESENT) - eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE; -#if defined(EUSART_DALICFG_DALIEN) - eusart->DALICFG = _EUSART_DALICFG_RESETVALUE; -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE; - eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE; - eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE; - eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE; - eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE; - eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE; - eusart->IEN = _EUSART_IEN_RESETVALUE; - eusart->IF_CLR = _EUSART_IF_MASK; - - // no need to sync while EN=0, multiple writes can be queued up, - // and the last one will synchronize once EN=1 - eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE; -} - -/***************************************************************************//** - * Enables/disables the EUSART receiver and/or transmitter. - ******************************************************************************/ -void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable) -{ - uint32_t tmp = 0; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - if (enable == eusartDisable) { - EUSART_Disable(eusart); - } else { - // Enable peripheral to configure Rx and Tx. - eusart->EN_SET = EUSART_EN_EN; - - // Enable or disable Rx and/or Tx - tmp = (enable) - & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK - | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK); - - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - eusart->CMD = tmp; - eusart_sync(eusart, - EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN - | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS); - - // Wait for the status register to be updated. - tmp = 0; - if (_EUSART_CMD_RXEN_MASK & enable) { - tmp |= EUSART_STATUS_RXENS; - } - if (_EUSART_CMD_TXEN_MASK & enable) { - tmp |= EUSART_STATUS_TXENS; - } - while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { - } - } -} - -/***************************************************************************//** - * Receives one 8 bit frame, (or part of 9 bit frame). - * - * @note (1) Handles the case where the RX Fifo Watermark has been set to N frames, - * and when N is greater than one. Attempt to read a frame from the RX Fifo. - * If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU - * interrupt flag is set. If the flag is set, wait to read again until the RXFL - * status flag is set, indicating there are N frames in the RX Fifo, where N - * is equal to the RX watermark level. Once there are N frames in the Fifo, - * read and return one frame. For consecutive N-1 reads there will be data available - * in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating - * delays between reads and sending N data frames in "bursts". - ******************************************************************************/ -uint8_t EUSART_Rx(EUSART_TypeDef *eusart) -{ - // If RX watermark has not been configured. - if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) { - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - return (uint8_t)eusart->RXDATA; - } - - // See Note #1. - uint8_t rx_data = eusart->RXDATA; - // If there is underflow i.e Rx data read was unsuccessful - if (eusart->IF & EUSART_IF_RXUF) { - // Wait until data becomes available in Rx fifo - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } - // Read Rx data again once data is available in the fifo - rx_data = eusart->RXDATA; - } - - return rx_data; -} - -/***************************************************************************//** - * Receives one 8-9 bit frame with extended information. - ******************************************************************************/ -uint16_t EUSART_RxExt(EUSART_TypeDef *eusart) -{ - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - - return (uint16_t)eusart->RXDATA; -} - -/***************************************************************************//** - * Transmits one frame. - ******************************************************************************/ -void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - eusart->TXDATA = (uint32_t)data; -} - -/***************************************************************************//** - * Transmits one 8-9 bit frame with extended control. - ******************************************************************************/ -void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - eusart->TXDATA = (uint32_t)data; -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Transmits one 8-16 bit frame and return received data. - ******************************************************************************/ -uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - eusart->TXDATA = (uint32_t)data; - - // Wait for Rx data to be available. - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } - return (uint16_t)eusart->RXDATA; -} - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Transmits one frame. - ******************************************************************************/ -void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data) -{ - uint32_t packet; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) { - // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data - // First write to TXDATA register should contain 16 LSBs of the TX frame. - // Transmission will not start after this first write. - // Second write to TXDATA register should contain the remaining TX frame bits. - // This second write will result in start of transmission. - packet = (data >> (index * 16)); - // To ensure compatibility with future devices, always write bits [31:16] to 0. - packet &= 0x0000FFFF; - eusart->TXDATA = packet; - } -} - -/***************************************************************************//** - * Receive one frame. - ******************************************************************************/ -uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart) -{ - uint32_t data = 0; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - - for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) { - // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data - // When receiving a frame that has more than 16 databits, - // RXDATA register needs to be read twice: - // First read will provide 16 LSBs of the received frame. - // Second read will provide the remaining RX frame bits. - data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16)); - } - return data; -} - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configures the baudrate (or as close as possible to a specified baudrate) - * depending on the current mode of the EU(S)ART peripheral. - * - * @note (1) When the oversampling is disabled, the peripheral clock frequency - * must be at least three times higher than the chosen baud rate. - ******************************************************************************/ -void EUSART_BaudrateSet(EUSART_TypeDef *eusart, - uint32_t refFreq, - uint32_t baudrate) -{ - uint32_t clkdiv; - uint8_t oversample = 0; - - // Prevent dividing by 0. - EFM_ASSERT(baudrate); - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // Get the current frequency. - if (!refFreq) { - refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); - } - -#if defined(EUSART_PRESENT) - // In synchronous mode (ex: SPI) - if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) { - EFM_ASSERT(baudrate <= refFreq); - - EUSART_Enable_TypeDef txrxEnStatus = eusartDisable; - bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true; - clkdiv = refFreq / baudrate - 1UL; - - // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV), - // the resulting spi master bus clock will be undefined because the result will be truncated. - EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT)); - - if (wasEnabled) { - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); - - // Save the state of the reveiver and transmitter before disabling the peripheral. - if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) { - txrxEnStatus = eusartEnable; - } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) { - txrxEnStatus = eusartEnableRx; - } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) { - txrxEnStatus = eusartEnableTx; - } else { - EFM_ASSERT(false); - } - - // Disable the eusart to be able to modify the CFG2 register. - EUSART_Disable(eusart); - } - - // In Synchronous mode the clock divider that is managing the bitRate - // is located inside the sdiv bitfield of the CFG2 register instead of - // the CLKDIV register combined with the oversample setting for asynchronous mode. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK); - - if (wasEnabled) { - EUSART_Enable(eusart, txrxEnStatus); - } - } else // In asynchronous mode (ex: UART) -#endif - { - // The peripheral must be enabled to configure the baud rate. - EFM_ASSERT(eusart->EN == EUSART_EN_EN); - -#if defined(EUSART_DALICFG_DALIEN) - if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { - // adjust for manchester double-clocking scheme - baudrate *= 2; - } -#endif - - /* - * Use integer division to avoid forcing in float division - * utils, and yet keep rounding effect errors to a minimum. - * - * CLKDIV is given by: - * - * CLKDIV = 256 * (fUARTn/(oversample * br) - 1) - * or - * CLKDIV = (256 * fUARTn)/(oversample * br) - 256 - * - * Since fUARTn may be derived from HFCORECLK, consider the overflow when - * using integer arithmetic. - * - * The basic problem with integer division in the above formula is that - * the dividend (256 * fUARTn) may become higher than the maximum 32 bit - * integer. Yet, the dividend should be evaluated first before dividing - * to get as small rounding effects as possible. - * Also, harsh restrictions on the maximum fUARTn value should not be made. - * - * Since the last 3 bits of CLKDIV are don't care, base the - * integer arithmetic on the below formula: - * - * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32 - * - * and calculate 1/8 of CLKDIV first. This allows for fUARTn - * up to 128 MHz without overflowing a 32 bit value. - */ - - // Map oversampling. - switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) { - case eusartOVS16: - EFM_ASSERT(baudrate <= (refFreq / 16)); - oversample = 16; - break; - - case eusartOVS8: - EFM_ASSERT(baudrate <= (refFreq / 8)); - oversample = 8; - break; - - case eusartOVS6: - EFM_ASSERT(baudrate <= (refFreq / 6)); - oversample = 6; - break; - - case eusartOVS4: - EFM_ASSERT(baudrate <= (refFreq / 4)); - oversample = 4; - break; - - case eusartOVS0: - EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1. - oversample = 1; - break; - - default: - // Invalid input - EFM_ASSERT(0); - break; - } - - if (oversample > 0U) { - // Calculate and set the CLKDIV with fractional bits. - clkdiv = (32 * refFreq) / (baudrate * oversample); - clkdiv -= 32; - clkdiv *= 8; - - // Verify that the resulting clock divider is within limits. - EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); - - // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits. - clkdiv &= _EUSART_CLKDIV_MASK; - - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - eusart->CLKDIV = clkdiv; - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - } - } -} - -/***************************************************************************//** - * Gets the current baudrate. - ******************************************************************************/ -uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart) -{ - uint32_t freq; - uint32_t div = 1; - uint32_t br = 0; - EUSART_OVS_TypeDef ovs = eusartOVS0; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); - -#if defined(EUSART_PRESENT) - // In synchronous mode (ex: SPI) - if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) { - div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT; - br = freq / (div + 1); - } - // In asynchronous mode (ex: UART) - else -#endif - { - div = eusart->CLKDIV; - ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK); - br = EUSART_AsyncBaudrateCalc(freq, div, ovs); - -#if defined(EUSART_DALICFG_DALIEN) - if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { - // adjust for manchester double-clocking scheme - br /= 2; - } -#endif - } - - return br; -} - -/***************************************************************************//** - * Enable/Disable reception operations until the configured start frame is - * received. - ******************************************************************************/ -void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - tmp = ((uint32_t)(enable)); - tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK); - - eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); - eusart->CMD_SET = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); - - tmp = 0u; - if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) { - tmp |= EUSART_STATUS_RXBLOCK; - } - while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) { - } // Wait for the status register to be updated. -} - -/***************************************************************************//** - * Enables/Disables the tristating of the transmitter output. - ******************************************************************************/ -void EUSART_TxTristateSet(EUSART_TypeDef *eusart, - EUSART_TristateTx_TypeDef enable) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - tmp = ((uint32_t)(enable)); - tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK); - - eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); - eusart->CMD = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); - - tmp = 0u; - if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) { - tmp |= EUSART_STATUS_TXTRI; - } - while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) { - } // Wait for the status register to be updated. -} - -/***************************************************************************//** - * Initializes the automatic enabling of transmissions and/or reception using - * the PRS as a trigger. - ******************************************************************************/ -void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, - const EUSART_PrsTriggerInit_TypeDef *init) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // The peripheral must be enabled to configure the PRS trigger. - EFM_ASSERT(eusart->EN == EUSART_EN_EN); - -#if defined(EUART_PRESENT) - PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK); -#else - -#if defined(EUSART0) - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK); - } -#endif -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK); - } -#endif -#endif - - tmp = ((uint32_t)(init->prs_trigger_enable)); - tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); - - eusart->TRIGCTRL_SET = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); - - tmp = ~((uint32_t)(init->prs_trigger_enable)); - tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); - eusart->TRIGCTRL_CLR = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); -} - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * Gets the clock associated to the specified EUSART instance. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Clock corresponding to the eusart. - ******************************************************************************/ -static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart) -{ - CMU_Clock_TypeDef clock; - -#if defined(EUART0) - if (eusart == EUART0) { - clock = cmuClock_EUART0; - } -#endif -#if defined(EUSART0) - if (eusart == EUSART0) { - clock = cmuClock_EUSART0; - } -#endif -#if defined(EUSART1) - else if (eusart == EUSART1) { - clock = cmuClock_EUSART1; - } -#endif -#if defined(EUSART2) - else if (eusart == EUSART2) { - clock = cmuClock_EUSART2; - } -#endif -#if defined(EUSART3) - else if (eusart == EUSART3) { - clock = cmuClock_EUSART3; - } -#endif -#if defined(EUSART4) - else if (eusart == EUSART4) { - clock = cmuClock_EUSART4; - } -#endif - else { - EFM_ASSERT(0); - return (CMU_Clock_TypeDef)0u; - } - return clock; -} - -/***************************************************************************//** - * Initializes the EUSART with asynchronous common settings to high - * and low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - * @param irdaInit Pointer to IrDA initialization structure. - ******************************************************************************/ -static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_UartInit_TypeDef *init, - const EUSART_IrDAInit_TypeDef *irdaInit, - const EUSART_DaliInit_TypeDef *daliInit) -{ - // LF register about to be modified requires sync busy check. - if (eusart->EN) { - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - } - // Initialize EUSART registers to hardware reset state. - EUSART_Reset(eusart); - - // Configure frame format - eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK - | _EUSART_FRAMECFG_STOPBITS_MASK - | _EUSART_FRAMECFG_PARITY_MASK)) - | (uint32_t)(init->databits) - | (uint32_t)(init->parity) - | (uint32_t)(init->stopbits); - - // Configure global configuration register 0. - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK - | _EUSART_CFG0_LOOPBK_MASK - | _EUSART_CFG0_MVDIS_MASK)) - | (uint32_t)(init->oversampling) - | (uint32_t)(init->loopbackEnable) - | (uint32_t)(init->majorityVote); - - if (init->baudrate == 0) { - eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN; - } - - if (init->advancedSettings) { - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK - | _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK - | _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK - | _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK)) - | (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT) - | (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT) - | (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK)) - | (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT) - | (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT) - | (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT) - | (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT); - - // Configure global configuration register 1. - eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK - | _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK)) - | (uint32_t)(init->advancedSettings->RxFifoWatermark) - | (uint32_t)(init->advancedSettings->TxFifoWatermark) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT); - - if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts - || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) { - eusart->CFG1 |= EUSART_CFG1_CTSEN; - } - // Enable RTS route pin if necessary. CTS is an input so it is enabled by default. - if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts) - || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) { -#if defined(EUART0) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; -#elif defined(EUSART0) - GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; -#endif - } else { -#if defined(EUART0) - GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; -#elif defined(EUSART0) - GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; -#endif - } - eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame; - if (init->advancedSettings->startFrame) { - eusart->CFG1 |= EUSART_CFG1_SFUBRX; - } - if (init->advancedSettings->prsRxEnable) { - eusart->CFG1 |= EUSART_CFG1_RXPRSEN; - // Configure PRS channel as input data line for EUSART. -#if defined(EUART_PRESENT) - PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK); -#elif defined(EUSART_PRESENT) - - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); - } -#endif -#endif - } - - // Configure global configuration timing register. - eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK) - | (uint32_t)(init->advancedSettings->autoTxDelay); - } - - if (irdaInit) { - if (irdaInit->irDALowFrequencyEnable) { - eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN); - } else { - // Configure IrDA HF configuration register. - eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK - | _EUSART_IRHFCFG_IRHFEN_MASK - | _EUSART_IRHFCFG_IRHFFILT_MASK)) - | (uint32_t)(EUSART_IRHFCFG_IRHFEN) - | (uint32_t)(irdaInit->irDAPulseWidth) - | (uint32_t)(irdaInit->irDARxFilterEnable); - } - } - -#if defined(EUSART_DALICFG_DALIEN) - // DALI-specific configuration section - if (daliInit) { - if (init->loopbackEnable) { - // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, - // then in this case DALIRXENDT should be set to 1. - eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT; - } - - if (EUSART_REF_VALID(eusart)) { - uint8_t index = EUSART_NUM(eusart); - - // keep track of the number of 16-bits packet to send - if (daliInit->TXdatabits <= eusartDaliTxDataBits16) { - dali_tx_nb_packets[index] = 1; - } else { - dali_tx_nb_packets[index] = 2; - } - - // keep track of the number of 16-bits packet to receive - if (daliInit->RXdatabits <= eusartDaliRxDataBits16) { - dali_rx_nb_packets[index] = 1; - } else { - dali_rx_nb_packets[index] = 2; - } - } - - // Configure the numbers of bits per TX and RX frames - eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK - | _EUSART_DALICFG_DALIRXDATABITS_MASK)) - | daliInit->TXdatabits - | daliInit->RXdatabits; - eusart->DALICFG_SET = EUSART_DALICFG_DALIEN; - } -#else - (void)(daliInit); -#endif /* EUSART_DALICFG_DALIEN */ - - // Enable EUSART IP. - EUSART_Enable(eusart, eusartEnable); - - // Configure the baudrate if auto baud detection is not used. - if (init->baudrate) { - EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate); - } - - // Finally enable the Rx and/or Tx channel (as specified). - EUSART_Enable(eusart, init->enable); - while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { - } -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initializes the EUSART with synchronous common settings to high - * and low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, - EUSART_SpiInit_TypeDef const *init) -{ - void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization. - - // LF register about to be modified requires sync busy check. - if (eusart->EN) { - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - } - - // Initialize EUSART registers to hardware reset state. - EUSART_Reset(eusart); - - // Configure global configuration register 2. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK - | _EUSART_CFG2_CLKPOL_MASK - | _EUSART_CFG2_CLKPHA_MASK - | _EUSART_CFG2_FORCELOAD_MASK)) - | (uint32_t)(init->master) - | (uint32_t)(init->clockMode) - | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default. - - if (advancedSetting_ptr) { - // Configure global configuration register 2. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK - | _EUSART_CFG2_AUTOCS_MASK - | _EUSART_CFG2_AUTOTX_MASK - | _EUSART_CFG2_CSINV_MASK - | _EUSART_CFG2_CLKPRSEN_MASK)) - | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT) - | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT) - | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT) - | (uint32_t)(init->advancedSettings->csPolarity) - | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT); - - // Only applicable to EM2 (low frequency) capable EUSART instances. - eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK - | _EUSART_CFG1_TXFIW_MASK)) - | (uint32_t)(init->advancedSettings->RxFifoWatermark) - | (uint32_t)(init->advancedSettings->TxFifoWatermark) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) - | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT); - } - - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK - | _EUSART_CFG0_LOOPBK_MASK)) - | (uint32_t)(_EUSART_CFG0_SYNC_SYNC) - | (uint32_t)(init->loopbackEnable); - - if (advancedSetting_ptr) { - eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK); - eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT; - - // Configure global configurationTiming register. - eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK - | _EUSART_TIMINGCFG_CSHOLD_MASK - | _EUSART_TIMINGCFG_ICS_MASK - | _EUSART_TIMINGCFG_SETUPWINDOW_MASK)) - | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT) - & _EUSART_TIMINGCFG_CSSETUP_MASK) - | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT) - & _EUSART_TIMINGCFG_CSHOLD_MASK) - | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT) - & _EUSART_TIMINGCFG_ICS_MASK) - | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT) - & _EUSART_TIMINGCFG_SETUPWINDOW_MASK) - ; - } - - // Configure frame format - eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK)) - | (uint32_t)(init->databits); - - if (advancedSetting_ptr) { - eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK); - - if (init->advancedSettings->prsRxEnable) { - //Configure PRS channel as input data line for EUSART. - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); - } -#endif - } - - if (init->advancedSettings->prsClockEnable) { - //Configure PRS channel as SCLK input for EUSART. - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK); - } -#endif - } - } - - // Set baudrate for synchronous operation mode. - EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate); - - // Enable EUSART IP. - EUSART_Enable(eusart, eusartEnable); - - // Finally enable the Rx and/or Tx channel (as specified). - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization. - eusart->CMD = (uint32_t)init->enable; - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); - while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { - } -} -#endif - -/***************************************************************************//** - * Calculate baudrate for a given reference frequency, clock division, - * and oversampling rate when the module is in UART mode. - * - * @param refFreq The EUSART reference clock frequency in Hz that will be used. - * @param clkdiv Clock division factor to be used. - * @param ovs Oversampling to be used. - * - * @return Computed baudrate from given settings. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - EUSART_OVS_TypeDef ovs) -{ - uint32_t oversample; - uint64_t divisor; - uint64_t factor; - uint64_t remainder; - uint64_t quotient; - uint32_t br; - - // Out of bound clkdiv. - EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); - - // Mask out unused bits - clkdiv &= _EUSART_CLKDIV_MASK; - - /* Use integer division to avoid forcing in float division - * utils and yet keep rounding effect errors to a minimum. - * - * Baudrate in is given by: - * - * br = fUARTn/(oversample * (1 + (CLKDIV / 256))) - * or - * br = (256 * fUARTn)/(oversample * (256 + CLKDIV)) - * - * 256 factor of the dividend is reduced with a - * (part of) oversample part of the divisor. - */ - - switch (ovs) { - case eusartOVS16: - oversample = 1; - factor = 256 / 16; - break; - - case eusartOVS8: - oversample = 1; - factor = 256 / 8; - break; - - case eusartOVS6: - oversample = 3; - factor = 256 / 2; - break; - - case eusartOVS4: - oversample = 1; - factor = 256 / 4; - break; - - case eusartOVS0: - oversample = 1; - factor = 256; - break; - - default: - return 0u; - break; - } - - /* - * The basic problem with integer division in the above formula is that - * the dividend (factor * fUARTn) may become larger than a 32 bit - * integer. Yet we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. Too harsh restrictions - * should not be made on the maximum fUARTn value either. - * - * For division a/b, - * - * a = qb + r - * - * where q is the quotient and r is the remainder, both integers. - * - * The original baudrate formula can be rewritten as - * - * br = xa / b = x(qb + r)/b = xq + xr/b - * - * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to - * variable names. - */ - - /* - * The divisor will never exceed max 32 bit value since - * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8) - * and 'oversample' has been reduced to <= 3. - */ - divisor = (uint64_t)(oversample * (256 + clkdiv)); - - quotient = refFreq / divisor; - remainder = refFreq % divisor; - - // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum - // 32 bit value. However, factor * remainder can become larger than 32-bit - // because of the size of _EUSART_CLKDIV_DIV_MASK on some families. - br = (uint32_t) (factor * quotient); - - /* - * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which - * means dividend (factor * remainder) worst case is - * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400. - */ - br += (uint32_t) ((factor * remainder) / divisor); - - return br; -} - -/***************************************************************************//** - * Perform EUSART Module disablement - resetting all internal flops/FSM. - * - * @param eusart Pointer to the EUSART peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart) -{ - if (eusart->EN & _EUSART_EN_EN_MASK) { - // This step should be skipped especially in Synchronous Slave mode when - // external SCLK is not running and CS is active -#if defined(EUSART_PRESENT) - if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK)) -#endif - { - // General Programming Guideline to properly disable the module: - // 1a. Disable TX and RX using TXDIS and RXDIS cmd - eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS; - // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low; - eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS)); - // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low - while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) { - } - } -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - eusart->CLKDIV = eusart->CLKDIV; - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - - // Read data until FIFO is emptied - // but taking care not to underflow the receiver - while (eusart->STATUS & EUSART_STATUS_RXFL) { - eusart->RXDATA; - } -#endif - - eusart->EN_CLR = EUSART_EN_EN; - -#if defined(_EUSART_EN_DISABLING_MASK) - // 2. Polling for EUSARTn_EN.DISABLING = 0. - while (eusart->EN & _EUSART_EN_DISABLING_MASK) { - } -#endif - } -} - -#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_eusart.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "em_cmu.h" +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +#if defined(EUART_PRESENT) + #define EUSART_REF_VALID(ref) ((ref) == EUART0) + #define EUSART_EM2_CAPABLE(ref) (true) + #define EUSART_RX_FIFO_SIZE 4u +#elif defined(EUSART_PRESENT) + #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1) + #define EUSART_RX_FIFO_SIZE 16u +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ +#if defined(EUSART_DALICFG_DALIEN) +static uint8_t dali_tx_nb_packets[EUSART_COUNT]; +static uint8_t dali_rx_nb_packets[EUSART_COUNT]; +#endif /* EUSART_DALICFG_DALIEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart); + +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit); + +#if defined(EUSART_PRESENT) +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_SpiInit_TypeDef *init); +#endif + +/***************************************************************************//** + * Wait for ongoing sync of register(s) to the low-frequency domain to complete. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param mask A bitmask corresponding to SYNCBUSY register defined bits, + * indicating registers that must complete any ongoing + * synchronization. + ******************************************************************************/ +__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask) +{ + // Wait for any pending previous write operation to have been completed + // in the low-frequency domain. + while ((eusart->SYNCBUSY & mask) != 0U) { + } +} + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs); + +/***************************************************************************//** + * Execute the EUSART peripheral disabling sequence. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes the EUSART when used with the high frequency clock. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to HF. + // The oversampling must not be disabled when using a high frequency clock. + EFM_ASSERT(init->oversampling != eusartOVS0); + + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used with the low frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists and is Low frequency capable. + EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to LF. + // LFXO, LFRCO, ULFRCO can be a clock source in LF. +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + { + CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL; +#if defined(EUART_PRESENT) + if (eusart == EUART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUART0); + } +#endif +#if defined(EUSART_PRESENT) && defined(EUSART0) + if (eusart == EUSART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUSART0); + } +#endif + + EFM_ASSERT( + (clock_source == cmuSelect_ULFRCO) + || (clock_source == cmuSelect_LFXO) + || (clock_source == cmuSelect_LFRCO) + || (clock_source == cmuSelect_EM23GRPACLK) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + || (clock_source == cmuSelect_EM01GRPCCLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK or EM01GRPCCLK */ +#endif + ); + } +#endif + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(init->oversampling == eusartOVS0); + // The Majority Vote must be disabled when using a low frequency clock. + EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used in IrDA mode with the high or low + * frequency clock. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(irdaInit); + + if (irdaInit->irDALowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(irdaInit->init.baudrate <= 9600); + EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable); + } else { + EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL); +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART when used in SPI mode. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + if (init->master) { + EFM_ASSERT(init->bitRate <= 20000000); + + if (init->advancedSettings) { + EFM_ASSERT(!(init->advancedSettings->prsClockEnable)); + } + } else { + EFM_ASSERT(init->bitRate <= 10000000); + if (init->advancedSettings && init->advancedSettings->forceLoad) { + // If baud-rate is more than 5MHz, a value of 4 is recommended, any values + // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz, + // value of 5 is recommended, values higher than 5 can be used but it may make the load + // error easy to occur. The recommended values for frequency bands should be sufficient + // to work all the time. + EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4) + || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5)); + } + } + + EUSART_SyncInitCommon(eusart, init); +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initializes the EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(daliInit); + + if (daliInit->init.loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should + // be set the same as DALITXDATABITS. + EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT) + == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT)); + } + + if (daliInit->daliLowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(daliInit->init.oversampling == eusartOVS0); + // In LF, max baudrate is 9600. See Note #1. + // but manchester is running at 2x clock 9600 => 4800 + EFM_ASSERT(daliInit->init.baudrate <= 4800); + } else { + EFM_ASSERT(daliInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps + EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit); +} +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the EUSART to its reset state. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart) +{ + // 1. Properly disable the module + EUSART_Disable(eusart); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + // Manual toggling tx_sclk_mst to synchronize handshake + // when switching from SPI master to other modes + // so module is disabling correctly. + uint32_t forcedClkCycle = 4u; + + while (forcedClkCycle--) { + eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK; + eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK; + } +#endif + // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set). + // Set all configurable register to its reset value. + // Note: Program desired settings to all registers that have names ending with CFG in the following sequence: + // a. CFG2 +#if defined(EUSART_PRESENT) + eusart->CFG2 = _EUSART_CFG2_RESETVALUE; +#endif + // b. CFG1 + eusart->CFG1 = _EUSART_CFG1_RESETVALUE; + // c. CFG0 + eusart->CFG0 = _EUSART_CFG0_RESETVALUE; + // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence) + eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE; +#if defined(EUSART_PRESENT) + eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE; +#if defined(EUSART_DALICFG_DALIEN) + eusart->DALICFG = _EUSART_DALICFG_RESETVALUE; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE; + eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE; + eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE; + eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE; + eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE; + eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE; + eusart->IEN = _EUSART_IEN_RESETVALUE; + eusart->IF_CLR = _EUSART_IF_MASK; + + // no need to sync while EN=0, multiple writes can be queued up, + // and the last one will synchronize once EN=1 + eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE; +} + +/***************************************************************************//** + * Enables/disables the EUSART receiver and/or transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable) +{ + uint32_t tmp = 0; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + if (enable == eusartDisable) { + EUSART_Disable(eusart); + } else { + // Enable peripheral to configure Rx and Tx. + eusart->EN_SET = EUSART_EN_EN; + + // Enable or disable Rx and/or Tx + tmp = (enable) + & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK + | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK); + + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + eusart->CMD = tmp; + eusart_sync(eusart, + EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN + | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS); + + // Wait for the status register to be updated. + tmp = 0; + if (_EUSART_CMD_RXEN_MASK & enable) { + tmp |= EUSART_STATUS_RXENS; + } + if (_EUSART_CMD_TXEN_MASK & enable) { + tmp |= EUSART_STATUS_TXENS; + } + while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { + } + } +} + +/***************************************************************************//** + * Receives one 8 bit frame, (or part of 9 bit frame). + * + * @note (1) Handles the case where the RX Fifo Watermark has been set to N frames, + * and when N is greater than one. Attempt to read a frame from the RX Fifo. + * If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU + * interrupt flag is set. If the flag is set, wait to read again until the RXFL + * status flag is set, indicating there are N frames in the RX Fifo, where N + * is equal to the RX watermark level. Once there are N frames in the Fifo, + * read and return one frame. For consecutive N-1 reads there will be data available + * in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating + * delays between reads and sending N data frames in "bursts". + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart) +{ + // If RX watermark has not been configured. + if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) { + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + return (uint8_t)eusart->RXDATA; + } + + // See Note #1. + uint8_t rx_data = eusart->RXDATA; + // If there is underflow i.e Rx data read was unsuccessful + if (eusart->IF & EUSART_IF_RXUF) { + // Wait until data becomes available in Rx fifo + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + // Read Rx data again once data is available in the fifo + rx_data = eusart->RXDATA; + } + + return rx_data; +} + +/***************************************************************************//** + * Receives one 8-9 bit frame with extended information. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart) +{ + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + return (uint16_t)eusart->RXDATA; +} + +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * Transmits one 8-9 bit frame with extended control. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmits one 8-16 bit frame and return received data. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + eusart->TXDATA = (uint32_t)data; + + // Wait for Rx data to be available. + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + return (uint16_t)eusart->RXDATA; +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data) +{ + uint32_t packet; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // First write to TXDATA register should contain 16 LSBs of the TX frame. + // Transmission will not start after this first write. + // Second write to TXDATA register should contain the remaining TX frame bits. + // This second write will result in start of transmission. + packet = (data >> (index * 16)); + // To ensure compatibility with future devices, always write bits [31:16] to 0. + packet &= 0x0000FFFF; + eusart->TXDATA = packet; + } +} + +/***************************************************************************//** + * Receive one frame. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart) +{ + uint32_t data = 0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // When receiving a frame that has more than 16 databits, + // RXDATA register needs to be read twice: + // First read will provide 16 LSBs of the received frame. + // Second read will provide the remaining RX frame bits. + data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16)); + } + return data; +} + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configures the baudrate (or as close as possible to a specified baudrate) + * depending on the current mode of the EU(S)ART peripheral. + * + * @note (1) When the oversampling is disabled, the peripheral clock frequency + * must be at least three times higher than the chosen baud rate. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate) +{ + uint32_t clkdiv; + uint8_t oversample = 0; + + // Prevent dividing by 0. + EFM_ASSERT(baudrate); + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Get the current frequency. + if (!refFreq) { + refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + } + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) { + EFM_ASSERT(baudrate <= refFreq); + + EUSART_Enable_TypeDef txrxEnStatus = eusartDisable; + bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true; + clkdiv = refFreq / baudrate - 1UL; + + // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV), + // the resulting spi master bus clock will be undefined because the result will be truncated. + EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT)); + + if (wasEnabled) { + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + + // Save the state of the reveiver and transmitter before disabling the peripheral. + if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnable; + } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) { + txrxEnStatus = eusartEnableRx; + } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnableTx; + } else { + EFM_ASSERT(false); + } + + // Disable the eusart to be able to modify the CFG2 register. + EUSART_Disable(eusart); + } + + // In Synchronous mode the clock divider that is managing the bitRate + // is located inside the sdiv bitfield of the CFG2 register instead of + // the CLKDIV register combined with the oversample setting for asynchronous mode. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK); + + if (wasEnabled) { + EUSART_Enable(eusart, txrxEnStatus); + } + } else // In asynchronous mode (ex: UART) +#endif + { + // The peripheral must be enabled to configure the baud rate. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + baudrate *= 2; + } +#endif + + /* + * Use integer division to avoid forcing in float division + * utils, and yet keep rounding effect errors to a minimum. + * + * CLKDIV is given by: + * + * CLKDIV = 256 * (fUARTn/(oversample * br) - 1) + * or + * CLKDIV = (256 * fUARTn)/(oversample * br) - 256 + * + * Since fUARTn may be derived from HFCORECLK, consider the overflow when + * using integer arithmetic. + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fUARTn) may become higher than the maximum 32 bit + * integer. Yet, the dividend should be evaluated first before dividing + * to get as small rounding effects as possible. + * Also, harsh restrictions on the maximum fUARTn value should not be made. + * + * Since the last 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula: + * + * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32 + * + * and calculate 1/8 of CLKDIV first. This allows for fUARTn + * up to 128 MHz without overflowing a 32 bit value. + */ + + // Map oversampling. + switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) { + case eusartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case eusartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case eusartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case eusartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + case eusartOVS0: + EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1. + oversample = 1; + break; + + default: + // Invalid input + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + // Calculate and set the CLKDIV with fractional bits. + clkdiv = (32 * refFreq) / (baudrate * oversample); + clkdiv -= 32; + clkdiv *= 8; + + // Verify that the resulting clock divider is within limits. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits. + clkdiv &= _EUSART_CLKDIV_MASK; + + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + eusart->CLKDIV = clkdiv; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + } + } +} + +/***************************************************************************//** + * Gets the current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart) +{ + uint32_t freq; + uint32_t div = 1; + uint32_t br = 0; + EUSART_OVS_TypeDef ovs = eusartOVS0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) { + div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT; + br = freq / (div + 1); + } + // In asynchronous mode (ex: UART) + else +#endif + { + div = eusart->CLKDIV; + ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK); + br = EUSART_AsyncBaudrateCalc(freq, div, ovs); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + br /= 2; + } +#endif + } + + return br; +} + +/***************************************************************************//** + * Enable/Disable reception operations until the configured start frame is + * received. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + eusart->CMD_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + + tmp = 0u; + if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_RXBLOCK; + } + while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Enables/Disables the tristating of the transmitter output. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + eusart->CMD = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + + tmp = 0u; + if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_TXTRI; + } + while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Initializes the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // The peripheral must be enabled to configure the PRS trigger. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK); +#else + +#if defined(EUSART0) + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK); + } +#endif +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK); + } +#endif +#endif + + tmp = ((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + + eusart->TRIGCTRL_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); + + tmp = ~((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + eusart->TRIGCTRL_CLR = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Gets the clock associated to the specified EUSART instance. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Clock corresponding to the eusart. + ******************************************************************************/ +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart) +{ + CMU_Clock_TypeDef clock; + +#if defined(EUART0) + if (eusart == EUART0) { + clock = cmuClock_EUART0; + } +#endif +#if defined(EUSART0) + if (eusart == EUSART0) { + clock = cmuClock_EUSART0; + } +#endif +#if defined(EUSART1) + else if (eusart == EUSART1) { + clock = cmuClock_EUSART1; + } +#endif +#if defined(EUSART2) + else if (eusart == EUSART2) { + clock = cmuClock_EUSART2; + } +#endif +#if defined(EUSART3) + else if (eusart == EUSART3) { + clock = cmuClock_EUSART3; + } +#endif +#if defined(EUSART4) + else if (eusart == EUSART4) { + clock = cmuClock_EUSART4; + } +#endif + else { + EFM_ASSERT(0); + return (CMU_Clock_TypeDef)0u; + } + return clock; +} + +/***************************************************************************//** + * Initializes the EUSART with asynchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + * @param irdaInit Pointer to IrDA initialization structure. + ******************************************************************************/ +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK + | _EUSART_FRAMECFG_STOPBITS_MASK + | _EUSART_FRAMECFG_PARITY_MASK)) + | (uint32_t)(init->databits) + | (uint32_t)(init->parity) + | (uint32_t)(init->stopbits); + + // Configure global configuration register 0. + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK + | _EUSART_CFG0_LOOPBK_MASK + | _EUSART_CFG0_MVDIS_MASK)) + | (uint32_t)(init->oversampling) + | (uint32_t)(init->loopbackEnable) + | (uint32_t)(init->majorityVote); + + if (init->baudrate == 0) { + eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN; + } + + if (init->advancedSettings) { + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK + | _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK + | _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK + | _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK)) + | (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT) + | (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT) + | (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK)) + | (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT) + | (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT); + + // Configure global configuration register 1. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK + | _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT); + + if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts + || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) { + eusart->CFG1 |= EUSART_CFG1_CTSEN; + } + // Enable RTS route pin if necessary. CTS is an input so it is enabled by default. + if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts) + || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) { +#if defined(EUART0) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } else { +#if defined(EUART0) + GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } + eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame; + if (init->advancedSettings->startFrame) { + eusart->CFG1 |= EUSART_CFG1_SFUBRX; + } + if (init->advancedSettings->prsRxEnable) { + eusart->CFG1 |= EUSART_CFG1_RXPRSEN; + // Configure PRS channel as input data line for EUSART. +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK); +#elif defined(EUSART_PRESENT) + + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif +#endif + } + + // Configure global configuration timing register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK) + | (uint32_t)(init->advancedSettings->autoTxDelay); + } + + if (irdaInit) { + if (irdaInit->irDALowFrequencyEnable) { + eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN); + } else { + // Configure IrDA HF configuration register. + eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFFILT_MASK)) + | (uint32_t)(EUSART_IRHFCFG_IRHFEN) + | (uint32_t)(irdaInit->irDAPulseWidth) + | (uint32_t)(irdaInit->irDARxFilterEnable); + } + } + +#if defined(EUSART_DALICFG_DALIEN) + // DALI-specific configuration section + if (daliInit) { + if (init->loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1. + eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT; + } + + if (EUSART_REF_VALID(eusart)) { + uint8_t index = EUSART_NUM(eusart); + + // keep track of the number of 16-bits packet to send + if (daliInit->TXdatabits <= eusartDaliTxDataBits16) { + dali_tx_nb_packets[index] = 1; + } else { + dali_tx_nb_packets[index] = 2; + } + + // keep track of the number of 16-bits packet to receive + if (daliInit->RXdatabits <= eusartDaliRxDataBits16) { + dali_rx_nb_packets[index] = 1; + } else { + dali_rx_nb_packets[index] = 2; + } + } + + // Configure the numbers of bits per TX and RX frames + eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK + | _EUSART_DALICFG_DALIRXDATABITS_MASK)) + | daliInit->TXdatabits + | daliInit->RXdatabits; + eusart->DALICFG_SET = EUSART_DALICFG_DALIEN; + } +#else + (void)(daliInit); +#endif /* EUSART_DALICFG_DALIEN */ + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Configure the baudrate if auto baud detection is not used. + if (init->baudrate) { + EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate); + } + + // Finally enable the Rx and/or Tx channel (as specified). + EUSART_Enable(eusart, init->enable); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART with synchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + EUSART_SpiInit_TypeDef const *init) +{ + void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization. + + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK + | _EUSART_CFG2_CLKPOL_MASK + | _EUSART_CFG2_CLKPHA_MASK + | _EUSART_CFG2_FORCELOAD_MASK)) + | (uint32_t)(init->master) + | (uint32_t)(init->clockMode) + | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default. + + if (advancedSetting_ptr) { + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK + | _EUSART_CFG2_AUTOCS_MASK + | _EUSART_CFG2_AUTOTX_MASK + | _EUSART_CFG2_CSINV_MASK + | _EUSART_CFG2_CLKPRSEN_MASK)) + | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT) + | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT) + | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT) + | (uint32_t)(init->advancedSettings->csPolarity) + | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT); + + // Only applicable to EM2 (low frequency) capable EUSART instances. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK + | _EUSART_CFG1_TXFIW_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT); + } + + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK + | _EUSART_CFG0_LOOPBK_MASK)) + | (uint32_t)(_EUSART_CFG0_SYNC_SYNC) + | (uint32_t)(init->loopbackEnable); + + if (advancedSetting_ptr) { + eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK); + eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT; + + // Configure global configurationTiming register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK + | _EUSART_TIMINGCFG_CSHOLD_MASK + | _EUSART_TIMINGCFG_ICS_MASK + | _EUSART_TIMINGCFG_SETUPWINDOW_MASK)) + | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT) + & _EUSART_TIMINGCFG_CSSETUP_MASK) + | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT) + & _EUSART_TIMINGCFG_CSHOLD_MASK) + | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT) + & _EUSART_TIMINGCFG_ICS_MASK) + | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT) + & _EUSART_TIMINGCFG_SETUPWINDOW_MASK) + ; + } + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK)) + | (uint32_t)(init->databits); + + if (advancedSetting_ptr) { + eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK); + + if (init->advancedSettings->prsRxEnable) { + //Configure PRS channel as input data line for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif + } + + if (init->advancedSettings->prsClockEnable) { + //Configure PRS channel as SCLK input for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK); + } +#endif + } + } + + // Set baudrate for synchronous operation mode. + EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate); + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Finally enable the Rx and/or Tx channel (as specified). + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization. + eusart->CMD = (uint32_t)init->enable; + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} +#endif + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate when the module is in UART mode. + * + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * @param clkdiv Clock division factor to be used. + * @param ovs Oversampling to be used. + * + * @return Computed baudrate from given settings. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + // Out of bound clkdiv. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // Mask out unused bits + clkdiv &= _EUSART_CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * Baudrate in is given by: + * + * br = fUARTn/(oversample * (1 + (CLKDIV / 256))) + * or + * br = (256 * fUARTn)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case eusartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case eusartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case eusartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + case eusartOVS4: + oversample = 1; + factor = 256 / 4; + break; + + case eusartOVS0: + oversample = 1; + factor = 256; + break; + + default: + return 0u; + break; + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fUARTn) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fUARTn value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum + // 32 bit value. However, factor * remainder can become larger than 32-bit + // because of the size of _EUSART_CLKDIV_DIV_MASK on some families. + br = (uint32_t) (factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400. + */ + br += (uint32_t) ((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * Perform EUSART Module disablement - resetting all internal flops/FSM. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart) +{ + if (eusart->EN & _EUSART_EN_EN_MASK) { + // This step should be skipped especially in Synchronous Slave mode when + // external SCLK is not running and CS is active +#if defined(EUSART_PRESENT) + if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK)) +#endif + { + // General Programming Guideline to properly disable the module: + // 1a. Disable TX and RX using TXDIS and RXDIS cmd + eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS; + // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low; + eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS)); + // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low + while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) { + } + } +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + eusart->CLKDIV = eusart->CLKDIV; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + + // Read data until FIFO is emptied + // but taking care not to underflow the receiver + while (eusart->STATUS & EUSART_STATUS_RXFL) { + eusart->RXDATA; + } +#endif + + eusart->EN_CLR = EUSART_EN_EN; + +#if defined(_EUSART_EN_DISABLING_MASK) + // 2. Polling for EUSARTn_EN.DISABLING = 0. + while (eusart->EN & _EUSART_EN_DISABLING_MASK) { + } +#endif + } +} + +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c index 7c55113..7d81d69 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c @@ -1,138 +1,138 @@ -/***************************************************************************//** - * @file - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_common.h" -#include "em_gpcrc.h" -#include "sl_assert.h" - -#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) - -/***************************************************************************//** - * @addtogroup gpcrc - * @{ - ******************************************************************************/ - -/******************************************************************************* - *************************** GLOBAL FUNCTIONS ****************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize the General Purpose Cyclic Redundancy Check (GPCRC) module. - * - * @details - * Use this function to configure the operational parameters of the GPCRC, - * such as the polynomial to use and how the input should be preprocessed - * before entering the CRC calculation. - * - * @note - * This function will not copy the initialization value to the data register - * to prepare for a new CRC calculation. Either call - * @ref GPCRC_Start before each calculation or by use the - * autoInit functionality. - * - * @param[in] gpcrc - * A pointer to the GPCRC peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure the GPCRC. - ******************************************************************************/ -void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init) -{ - uint32_t polySelect; - uint32_t revPoly = 0; - - if (init->crcPoly == 0x04C11DB7) { - polySelect = GPCRC_CTRL_POLYSEL_CRC32; - } else { - // If not using the fixed CRC-32 polynomial, use 16-bit. - EFM_ASSERT((init->crcPoly & 0xFFFF0000UL) == 0U); -#if defined(GPCRC_CTRL_POLYSEL_CRC16) - polySelect = GPCRC_CTRL_POLYSEL_CRC16; -#else - polySelect = GPCRC_CTRL_POLYSEL_16; -#endif - revPoly = SL_RBIT16(init->crcPoly); - } - -#if defined(GPCRC_EN_EN) - if (init->enable) { - gpcrc->EN_SET = GPCRC_EN_EN; - } else { - gpcrc->EN_CLR = GPCRC_EN_EN; - } - - gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) - | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) - | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) - | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) - | polySelect); -#else - gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) - | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) - | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) - | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) - | polySelect - | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT)); -#endif - -#if defined(GPCRC_CTRL_POLYSEL_CRC16) - if (polySelect == GPCRC_CTRL_POLYSEL_CRC16) { -#else - if (polySelect == GPCRC_CTRL_POLYSEL_16) { -#endif - // Set the CRC polynomial value. - gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK; - } - - // Load the CRC initialization value to GPCRC_INIT. - gpcrc->INIT = init->initValue; -} - -/***************************************************************************//** - * @brief - * Reset GPCRC registers to the hardware reset state. - * - * @note - * The data registers are not reset by this function. - * - * @param[in] gpcrc - * A pointer to the GPCRC peripheral register block. - ******************************************************************************/ -void GPCRC_Reset(GPCRC_TypeDef * gpcrc) -{ - gpcrc->CTRL = _GPCRC_CTRL_RESETVALUE; - gpcrc->POLY = _GPCRC_POLY_RESETVALUE; - gpcrc->INIT = _GPCRC_INIT_RESETVALUE; -} - -/** @} (end addtogroup gpcrc) */ - -#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_common.h" +#include "em_gpcrc.h" +#include "sl_assert.h" + +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpcrc + * @{ + ******************************************************************************/ + +/******************************************************************************* + *************************** GLOBAL FUNCTIONS ****************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize the General Purpose Cyclic Redundancy Check (GPCRC) module. + * + * @details + * Use this function to configure the operational parameters of the GPCRC, + * such as the polynomial to use and how the input should be preprocessed + * before entering the CRC calculation. + * + * @note + * This function will not copy the initialization value to the data register + * to prepare for a new CRC calculation. Either call + * @ref GPCRC_Start before each calculation or by use the + * autoInit functionality. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the GPCRC. + ******************************************************************************/ +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init) +{ + uint32_t polySelect; + uint32_t revPoly = 0; + + if (init->crcPoly == 0x04C11DB7) { + polySelect = GPCRC_CTRL_POLYSEL_CRC32; + } else { + // If not using the fixed CRC-32 polynomial, use 16-bit. + EFM_ASSERT((init->crcPoly & 0xFFFF0000UL) == 0U); +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + polySelect = GPCRC_CTRL_POLYSEL_CRC16; +#else + polySelect = GPCRC_CTRL_POLYSEL_16; +#endif + revPoly = SL_RBIT16(init->crcPoly); + } + +#if defined(GPCRC_EN_EN) + if (init->enable) { + gpcrc->EN_SET = GPCRC_EN_EN; + } else { + gpcrc->EN_CLR = GPCRC_EN_EN; + } + + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect); +#else + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect + | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT)); +#endif + +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + if (polySelect == GPCRC_CTRL_POLYSEL_CRC16) { +#else + if (polySelect == GPCRC_CTRL_POLYSEL_16) { +#endif + // Set the CRC polynomial value. + gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK; + } + + // Load the CRC initialization value to GPCRC_INIT. + gpcrc->INIT = init->initValue; +} + +/***************************************************************************//** + * @brief + * Reset GPCRC registers to the hardware reset state. + * + * @note + * The data registers are not reset by this function. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + ******************************************************************************/ +void GPCRC_Reset(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CTRL = _GPCRC_CTRL_RESETVALUE; + gpcrc->POLY = _GPCRC_POLY_RESETVALUE; + gpcrc->INIT = _GPCRC_INIT_RESETVALUE; +} + +/** @} (end addtogroup gpcrc) */ + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c index 9c4ddf4..13704e0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c @@ -1,452 +1,452 @@ -/***************************************************************************//** - * @file - * @brief General Purpose IO (GPIO) peripheral API - * devices. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_gpio.h" - -#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) - -/***************************************************************************//** - * @addtogroup gpio GPIO - General Purpose Input/Output - * @brief General Purpose Input/Output (GPIO) API - * @details - * This module contains functions to control the GPIO peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration - * and direct pin manipulation and sensing as well as routing for peripheral - * pin connections. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the pin typically usable in assert statements. */ -#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) -#define GPIO_STRENGTH_VALID(strength) (!((strength) \ - & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ - | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Sets the pin location of the debug pins (Serial Wire interface). - * - * @note - * Changing the pins used for debugging uncontrolled, may result in a lockout. - * - * @param[in] location - * The debug pin location to use (0-3). - ******************************************************************************/ -void GPIO_DbgLocationSet(unsigned int location) -{ -#if defined (_GPIO_ROUTE_SWLOCATION_MASK) - EFM_ASSERT(location < AFCHANLOC_MAX); - - GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) - | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); -#elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) - EFM_ASSERT(location < AFCHANLOC_MAX); - - GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) - | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); -#else - (void)location; -#endif -} - -#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) -/***************************************************************************//** - * @brief - * Sets drive mode for a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] mode - * Drive mode to use for the port. - ******************************************************************************/ -void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) -{ - EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); - - GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) - | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); -} -#endif - -#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) -/***************************************************************************//** - * @brief - * Sets the drive strength for a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] strength - * The drive strength to use for the port. - ******************************************************************************/ -void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, - GPIO_DriveStrength_TypeDef strength) -{ - EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); - BUS_RegMaskedWrite(&GPIO->P[port].CTRL, - _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, - strength); -} -#endif - -/***************************************************************************//** - * @brief - * Configure the GPIO external pin interrupt. - * - * @details - * It is recommended to disable interrupts before configuring the GPIO pin interrupt. - * See @ref GPIO_IntDisable() for more information. - * - * The GPIO interrupt handler must be in place before enabling the - * interrupt. - * - * Notice that any pending interrupt for the selected interrupt is cleared - * by this function. - * - * @note - * On series 0 devices, the pin number parameter is not used. The - * pin number used on these devices is hardwired to the interrupt with the - * same number. @n - * On series 1 devices, the pin number can be selected freely within a group. - * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin - * number within the interrupt groups are: - * 0: pins 0-3 (interrupt number 0-3) - * 1: pins 4-7 (interrupt number 4-7) - * 2: pins 8-11 (interrupt number 8-11) - * 3: pins 12-15 (interrupt number 12-15) - * - * @param[in] port - * The port to associate with the @p pin. - * - * @param[in] pin - * The pin number on the port. - * - * @param[in] intNo - * The interrupt number to trigger. - * - * @param[in] risingEdge - * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. - * - * @param[in] fallingEdge - * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. - * - * @param[in] enable - * Set to true if the interrupt will be enabled after the configuration is complete. - * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). - ******************************************************************************/ -void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - unsigned int intNo, - bool risingEdge, - bool fallingEdge, - bool enable) -{ -#if defined (_GPIO_EXTIPSELH_MASK) - uint32_t tmp = 0; -#endif -#if !defined(_GPIO_EXTIPINSELL_MASK) - (void)pin; -#endif - - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_EXTIPINSELL_MASK) - EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); -#endif - - /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls - * pins 8-15 of the interrupt configuration. */ - if (intNo < 8) { - BUS_RegMaskedWrite(&GPIO->EXTIPSELL, - _GPIO_EXTIPSELL_EXTIPSEL0_MASK - << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), - (uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); - } else { -#if defined(_GPIO_EXTIPSELH_MASK) - tmp = intNo - 8; -#if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPSELH, - _GPIO_EXTIPSELH_EXTIPSEL0_MASK - << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), - (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); -#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPSELH, - _GPIO_EXTIPSELH_EXTIPSEL8_MASK - << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), - (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); -#else -#error Invalid GPIO_EXTIPINSELH bit fields -#endif -#endif /* #if defined(_GPIO_EXTIPSELH_MASK) */ - } - -#if defined(_GPIO_EXTIPINSELL_MASK) - - /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls - * interrupt 8-15 of the interrupt/pin number mapping. */ - if (intNo < 8) { - BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, - _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK - << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) - << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); - } else { -#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, - _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK - << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) - << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); -#endif -#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, - _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK - << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) - << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); -#endif - } -#endif - - /* Enable/disable the rising edge interrupt. */ - BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); - - /* Enable/disable the falling edge interrupt. */ - BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); - - /* Clear any pending interrupt. */ - GPIO_IntClear(1 << intNo); - - /* Finally enable/disable interrupt. */ - BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); -} - -#if _SILICON_LABS_32B_SERIES > 0 -/***************************************************************************//** - * @brief - * Configure EM4WU pins as external level-sensitive interrupts. - * - * @details - * It is recommended to disable interrupts before configuring the GPIO pin interrupt. - * See @ref GPIO_IntDisable() for more information. - * - * The GPIO interrupt handler must be in place before enabling the - * interrupt. - * - * Notice that any pending interrupt for the selected interrupt is cleared - * by this function. - * - * @note - * The selected port/pin must be mapped to an existant EM4WU interrupt. - * Each EM4WU signal is connected to a fixed pin. - * Refer to the Alternate Function Table in the device Datasheet for the - * location of each EM4WU signal. For example, on xG22 device, the interrupt - * of EM4WU6 is fixed to pin PC00. - * - * @param[in] port - * The port to associate with the @p pin. - * - * @param[in] pin - * The pin number on the port. - * - * @param[in] intNo - * The EM4WU interrupt number to trigger. - * - * @param[in] polarity - * true = Active high level-sensitive interrupt. - * false = Active low level-sensitive interrupt. - * - * @param[in] enable - * Set to true if the interrupt will be enabled after the configuration is complete. - * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). - ******************************************************************************/ -void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - uint32_t intNo, - bool polarity, - bool enable) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - // GPIO pin mode set. - GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity); - - // Enable EM4WU function and set polarity - uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); - uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); - - GPIO_EM4EnablePinWakeup(pinmask, polarityMask); - - // Enable EM4WU interrupt -#if defined(_SILICON_LABS_32B_SERIES_1) - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); -#else - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Set the mode for a GPIO pin. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number in the port. - * - * @param[in] mode - * The desired pin mode. - * - * @param[in] out - * A value to set for the pin in the DOUT register. The DOUT setting is important for - * some input mode configurations to determine the pull-up/down direction. - ******************************************************************************/ -void GPIO_PinModeSet(GPIO_Port_TypeDef port, - unsigned int pin, - GPIO_Mode_TypeDef mode, - unsigned int out) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - /* If disabling a pin, do not modify DOUT to reduce the chance of */ - /* a glitch/spike (may not be sufficient precaution in all use cases). */ - if (mode != gpioModeDisabled) { - if (out) { - GPIO_PinOutSet(port, pin); - } else { - GPIO_PinOutClear(port, pin); - } - } - - /* There are two registers controlling the pins for each port. The MODEL - * register controls pins 0-7 and MODEH controls pins 8-15. */ - if (pin < 8) { - // Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C) - // Compiler assigned 8 bits for enum. Same thing for other branch. - BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); - } else { - BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4)); - } - - if (mode == gpioModeDisabled) { - if (out) { - GPIO_PinOutSet(port, pin); - } else { - GPIO_PinOutClear(port, pin); - } - } -} - -/***************************************************************************//** - * @brief - * Get the mode for a GPIO pin. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number in the port. - * - * @return - * The pin mode. - ******************************************************************************/ -GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - if (pin < 8) { - return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); - } else { - return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); - } -} - -#if defined(_GPIO_EM4WUEN_MASK) -/**************************************************************************//** - * @brief - * Enable GPIO pin wake-up from EM4. When the function exits, - * EM4 mode can be safely entered. - * - * @note - * It is assumed that the GPIO pin modes are set correctly. - * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. - * - * @param[in] pinmask - * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. - * See Reference Manuals for a pinmask to the GPIO port/pin mapping. - * @param[in] polaritymask - * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. - * See Reference Manuals for pinmask-to-GPIO port/pin mapping. - *****************************************************************************/ -void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) -{ - EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); - -#if defined(_GPIO_EM4WUPOL_MASK) - EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); - GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ - GPIO->EM4WUPOL |= pinmask & polaritymask; -#elif defined(_GPIO_EXTILEVEL_MASK) - EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); - GPIO->EXTILEVEL &= ~pinmask; - GPIO->EXTILEVEL |= pinmask & polaritymask; -#endif - GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ - - GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ - -#if defined(_GPIO_CMD_EM4WUCLR_MASK) - GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ -#else - GPIO_IntClear(pinmask); -#endif -} -#endif - -/** @} (end addtogroup gpio) */ - -#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + * devices. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_gpio.h" + +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpio GPIO - General Purpose Input/Output + * @brief General Purpose Input/Output (GPIO) API + * @details + * This module contains functions to control the GPIO peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration + * and direct pin manipulation and sensing as well as routing for peripheral + * pin connections. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the pin typically usable in assert statements. */ +#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) +#define GPIO_STRENGTH_VALID(strength) (!((strength) \ + & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ + | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Sets the pin location of the debug pins (Serial Wire interface). + * + * @note + * Changing the pins used for debugging uncontrolled, may result in a lockout. + * + * @param[in] location + * The debug pin location to use (0-3). + ******************************************************************************/ +void GPIO_DbgLocationSet(unsigned int location) +{ +#if defined (_GPIO_ROUTE_SWLOCATION_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) + | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); +#elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) + | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); +#else + (void)location; +#endif +} + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +/***************************************************************************//** + * @brief + * Sets drive mode for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] mode + * Drive mode to use for the port. + ******************************************************************************/ +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) + | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +/***************************************************************************//** + * @brief + * Sets the drive strength for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] strength + * The drive strength to use for the port. + ******************************************************************************/ +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, + GPIO_DriveStrength_TypeDef strength) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); + BUS_RegMaskedWrite(&GPIO->P[port].CTRL, + _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, + strength); +} +#endif + +/***************************************************************************//** + * @brief + * Configure the GPIO external pin interrupt. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * On series 0 devices, the pin number parameter is not used. The + * pin number used on these devices is hardwired to the interrupt with the + * same number. @n + * On series 1 devices, the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The interrupt number to trigger. + * + * @param[in] risingEdge + * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. + * + * @param[in] fallingEdge + * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable) +{ +#if defined (_GPIO_EXTIPSELH_MASK) + uint32_t tmp = 0; +#endif +#if !defined(_GPIO_EXTIPINSELL_MASK) + (void)pin; +#endif + + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_EXTIPINSELL_MASK) + EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); +#endif + + /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls + * pins 8-15 of the interrupt configuration. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPSELL, + _GPIO_EXTIPSELL_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), + (uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); + } else { +#if defined(_GPIO_EXTIPSELH_MASK) + tmp = intNo - 8; +#if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL8_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#else +#error Invalid GPIO_EXTIPINSELH bit fields +#endif +#endif /* #if defined(_GPIO_EXTIPSELH_MASK) */ + } + +#if defined(_GPIO_EXTIPINSELL_MASK) + + /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls + * interrupt 8-15 of the interrupt/pin number mapping. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, + _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); + } else { +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#endif +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#endif + } +#endif + + /* Enable/disable the rising edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); + + /* Enable/disable the falling edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); + + /* Clear any pending interrupt. */ + GPIO_IntClear(1 << intNo); + + /* Finally enable/disable interrupt. */ + BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); +} + +#if _SILICON_LABS_32B_SERIES > 0 +/***************************************************************************//** + * @brief + * Configure EM4WU pins as external level-sensitive interrupts. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * The selected port/pin must be mapped to an existant EM4WU interrupt. + * Each EM4WU signal is connected to a fixed pin. + * Refer to the Alternate Function Table in the device Datasheet for the + * location of each EM4WU signal. For example, on xG22 device, the interrupt + * of EM4WU6 is fixed to pin PC00. + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The EM4WU interrupt number to trigger. + * + * @param[in] polarity + * true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // GPIO pin mode set. + GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity); + + // Enable EM4WU function and set polarity + uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + + GPIO_EM4EnablePinWakeup(pinmask, polarityMask); + + // Enable EM4WU interrupt +#if defined(_SILICON_LABS_32B_SERIES_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); +#else + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Set the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @param[in] mode + * The desired pin mode. + * + * @param[in] out + * A value to set for the pin in the DOUT register. The DOUT setting is important for + * some input mode configurations to determine the pull-up/down direction. + ******************************************************************************/ +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + /* If disabling a pin, do not modify DOUT to reduce the chance of */ + /* a glitch/spike (may not be sufficient precaution in all use cases). */ + if (mode != gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } + + /* There are two registers controlling the pins for each port. The MODEL + * register controls pins 0-7 and MODEH controls pins 8-15. */ + if (pin < 8) { + // Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C) + // Compiler assigned 8 bits for enum. Same thing for other branch. + BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); + } else { + BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4)); + } + + if (mode == gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } +} + +/***************************************************************************//** + * @brief + * Get the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @return + * The pin mode. + ******************************************************************************/ +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + if (pin < 8) { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); + } else { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); + } +} + +#if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin wake-up from EM4. When the function exits, + * EM4 mode can be safely entered. + * + * @note + * It is assumed that the GPIO pin modes are set correctly. + * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. + * + * @param[in] pinmask + * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. + * See Reference Manuals for a pinmask to the GPIO port/pin mapping. + * @param[in] polaritymask + * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. + * See Reference Manuals for pinmask-to-GPIO port/pin mapping. + *****************************************************************************/ +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); + +#if defined(_GPIO_EM4WUPOL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); + GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ + GPIO->EM4WUPOL |= pinmask & polaritymask; +#elif defined(_GPIO_EXTILEVEL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); + GPIO->EXTILEVEL &= ~pinmask; + GPIO->EXTILEVEL |= pinmask & polaritymask; +#endif + GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ + + GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ + +#if defined(_GPIO_CMD_EM4WUCLR_MASK) + GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ +#else + GPIO_IntClear(pinmask); +#endif +} +#endif + +/** @} (end addtogroup gpio) */ + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c index dde3240..9f53b28 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c @@ -1,940 +1,940 @@ -/***************************************************************************//** - * @file - * @brief Inter-integrated Circuit (I2C) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_i2c.h" -#if defined(I2C_COUNT) && (I2C_COUNT > 0) - -#include "em_cmu.h" -#include "em_bus.h" -#include "sl_assert.h" - - #include - -/***************************************************************************//** - * @addtogroup i2c I2C - Inter-Integrated Circuit - * @brief Inter-integrated Circuit (I2C) Peripheral API - * @details - * This module contains functions to control the I2C peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C - * buses with the lowest energy consumption possible. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the I2C register block pointer reference for assert statements. */ -#if (I2C_COUNT == 1) -#define I2C_REF_VALID(ref) ((ref) == I2C0) -#elif (I2C_COUNT == 2) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) -#elif (I2C_COUNT == 3) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) -#elif (I2C_COUNT == 4) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2) || ((ref) == I2C3)) -#endif - -/** Error flags indicating that the I2C transfer has failed. */ -/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ -/* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ -/* RXUF is only likely to occur with the software if using a debugger peeking into */ -/* the RXDATA register. Therefore, those types of faults are ignored. */ -#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) -#define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) - -/* Maximum I2C transmission rate constant. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY) -#define I2C_CR_MAX 8 -#else -#define I2C_CR_MAX 4 -#endif -#elif defined(_SILICON_LABS_32B_SERIES_1) -#define I2C_CR_MAX 8 -#elif defined(_SILICON_LABS_32B_SERIES_2) -#define I2C_CR_MAX 8 -#else -#warning "Max I2C transmission rate constant is not defined" -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Master mode transfer states. */ -typedef enum { - i2cStateStartAddrSend, /**< Send start + (first part of) address. */ - i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ - i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ - i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ - i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ - i2cStateDataSend, /**< Send data. */ - i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ - i2cStateWFData, /**< Wait for data. */ - i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ - i2cStateDone /**< Transfer completed successfully. */ -} I2C_TransferState_TypeDef; - -/** @endcond */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Structure used to store state information on an ongoing master mode transfer. */ -typedef struct { - /** Current state. */ - I2C_TransferState_TypeDef state; - - /** Result return code. */ - I2C_TransferReturn_TypeDef result; - - /** Offset in the current sequence buffer. */ - uint16_t offset; - - /* Index to the current sequence buffer in use. */ - uint8_t bufIndx; - - /** Reference to the I2C transfer sequence definition provided by the user. */ - I2C_TransferSeq_TypeDef *seq; -} I2C_Transfer_TypeDef; - -/** @endcond */ - -/******************************************************************************* - ***************************** LOCAL DATA *******^************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** - * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined - * index (0x3) to reflect a default setting just in case. - */ -static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; - -/** A transfer state information for an ongoing master mode transfer. */ -static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Empty received data buffer. - ******************************************************************************/ -static void flushRx(I2C_TypeDef *i2c) -{ - while (i2c->STATUS & I2C_STATUS_RXDATAV) { - i2c->RXDATA; - } - -#if defined(_SILICON_LABS_32B_SERIES_2) - /* SW needs to clear RXDATAV IF on Series 2 devices. - Flag is kept high by HW if buffer is not empty. */ - I2C_IntClear(i2c, I2C_IF_RXDATAV); -#endif -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the current configured I2C bus frequency. - * - * @details - * This frequency is only relevant when acting as master. - * - * @note - * The actual frequency is a real number, this function returns a rounded - * down (truncated) integer value. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @return - * The current I2C frequency in Hz. - ******************************************************************************/ -uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) -{ - uint32_t freqHfper = 0; - uint32_t n; - - /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) - * For more details, see the reference manual - * I2C Clock Generation chapter. */ - if (i2c == I2C0) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); -#if defined(I2C1) - } else if (i2c == I2C1) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); -#endif -#if defined(I2C2) - } else if (i2c == I2C2) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); -#endif - } else { - EFM_ASSERT(false); - } - - /* n = Nlow + Nhigh */ - n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) - >> _I2C_CTRL_CLHR_SHIFT]; - return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); -} - -/***************************************************************************//** - * @brief - * Set the I2C bus frequency. - * - * @details - * The bus frequency is only relevant when acting as master. The bus - * frequency should not be set higher than the maximum frequency accepted by the - * slowest device on the bus. - * - * Notice that, due to asymmetric requirements on low and high I2C clock - * cycles in the I2C specification, the maximum frequency allowed - * to comply with the specification may be somewhat lower than expected. - * - * See the reference manual, details on I2C clock generation, - * for maximum allowed theoretical frequencies for different modes. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] freqRef - * An I2C reference clock frequency in Hz that will be used. If set to 0, - * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual - * configured value has the consequence of reducing the real I2C frequency. - * - * @param[in] freqScl - * A bus frequency to set (bus speed may be lower due to integer - * prescaling). Safe (according to the I2C specification) maximum frequencies for - * standard fast and fast+ modes are available using I2C_FREQ_ defines. - * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) - * The slowest slave device on a bus must always be considered. - * - * @param[in] i2cMode - * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, - * make sure all devices on the bus support the specified mode. Using a - * non-standard ratio is useful to achieve a higher bus clock in fast and - * fast+ modes. - ******************************************************************************/ -void I2C_BusFreqSet(I2C_TypeDef *i2c, - uint32_t freqRef, - uint32_t freqScl, - I2C_ClockHLR_TypeDef i2cMode) -{ - uint32_t n, minFreq, denominator; - int32_t div; - - /* Avoid dividing by 0. */ - EFM_ASSERT(freqScl); - if (!freqScl) { - return; - } - - /* Ensure mode is valid */ - i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; - - /* Set the CLHR (clock low-to-high ratio). */ - i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; - BUS_RegMaskedWrite(&i2c->CTRL, - _I2C_CTRL_CLHR_MASK, - i2cMode << _I2C_CTRL_CLHR_SHIFT); - - if (freqRef == 0) { - if (i2c == I2C0) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C0); -#if defined(I2C1) - } else if (i2c == I2C1) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C1); -#endif -#if defined(I2C2) - } else if (i2c == I2C2) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C2); -#endif - } else { - EFM_ASSERT(false); - } - } - - /* Check the minumum HF peripheral clock. */ - minFreq = UINT_MAX; - if (i2c->CTRL & I2C_CTRL_SLAVE) { - switch (i2cMode) { - case i2cClockHLRStandard: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 4200000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 2000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 2000000; break; -#endif - case i2cClockHLRAsymetric: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 11000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 5000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 5000000; break; -#endif - case i2cClockHLRFast: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 24400000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 14000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 14000000; break; -#endif - default: - /* MISRA requires the default case. */ - break; - } - } else { - /* For master mode, platform 1 and 2 share the same - minimum frequencies. */ - switch (i2cMode) { - case i2cClockHLRStandard: - minFreq = 2000000; break; - case i2cClockHLRAsymetric: - minFreq = 9000000; break; - case i2cClockHLRFast: - minFreq = 20000000; break; - default: - /* MISRA requires default case */ - break; - } - } - - /* Frequency most be larger-than. */ - EFM_ASSERT(freqRef > minFreq); - - /* SCL frequency is given by: - * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) - * - * Therefore, - * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 - * - * For more details, see the reference manual - * I2C Clock Generation chapter. */ - - /* n = Nlow + Nhigh */ - n = (uint32_t)i2cNSum[i2cMode]; - denominator = n * freqScl; - - /* Explicitly ensure denominator is never zero. */ - if (denominator == 0) { - EFM_ASSERT(0); - return; - } - /* Perform integer division so that div is rounded up. */ - div = (int32_t)(((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) - / denominator) - 1); - EFM_ASSERT(div >= 0); - EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); - - /* The clock divisor must be at least 1 in slave mode according to the reference */ - /* manual (in which case there is normally no need to set the bus frequency). */ - if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { - div = 1; - } - i2c->CLKDIV = (uint32_t)div; -} - -/***************************************************************************//** - * @brief - * Enable/disable I2C. - * - * @note - * After enabling the I2C (from being disabled), the I2C is in BUSY state. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] enable - * True to enable counting, false to disable. - ******************************************************************************/ -void I2C_Enable(I2C_TypeDef *i2c, bool enable) -{ - EFM_ASSERT(I2C_REF_VALID(i2c)); - -#if defined (_I2C_EN_MASK) - BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); -#else - BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); -#endif -} - -/***************************************************************************//** - * @brief - * Initialize I2C. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] init - * A pointer to the I2C initialization structure. - ******************************************************************************/ -void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) -{ - EFM_ASSERT(I2C_REF_VALID(i2c)); - - i2c->IEN = 0; - I2C_IntClear(i2c, _I2C_IF_MASK); - - /* Set SLAVE select mode. */ - BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); - - I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); - - I2C_Enable(i2c, init->enable); -} - -/***************************************************************************//** - * @brief - * Reset I2C to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * centralized setup of this feature. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - ******************************************************************************/ -void I2C_Reset(I2C_TypeDef *i2c) -{ - // Cancel ongoing operations and clear TX buffer - i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; - i2c->CTRL = _I2C_CTRL_RESETVALUE; - i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; - i2c->SADDR = _I2C_SADDR_RESETVALUE; - i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; - i2c->IEN = _I2C_IEN_RESETVALUE; -#if defined (_I2C_EN_EN_MASK) - i2c->EN = _I2C_EN_RESETVALUE; -#endif - - // Empty received data buffer - flushRx(i2c); - I2C_IntClear(i2c, _I2C_IF_MASK); - /* Do not reset the route register; setting should be done independently. */ -} - -// ***************************************************************************** -/// @brief -/// Continue an initiated I2C transfer (single master mode only). -/// -/// @details -/// This function is used repeatedly after a I2C_TransferInit() to -/// complete a transfer. It may be used in polled mode as the below example -/// shows: -/// @code{.c} -/// I2C_TransferReturn_TypeDef ret; -/// -/// // Do a polled transfer -/// ret = I2C_TransferInit(I2C0, seq); -/// while (ret == i2cTransferInProgress) -/// { -/// ret = I2C_Transfer(I2C0); -/// } -/// @endcode -/// It may also be used in interrupt driven mode, where this function is invoked -/// from the interrupt handler. Notice that, if used in interrupt mode, NVIC -/// interrupts must be configured and enabled for the I2C bus used. I2C -/// peripheral specific interrupts are managed by this software. -/// -/// @note -/// Only single master mode is supported. -/// -/// @param[in] i2c -/// A pointer to the I2C peripheral register block. -/// -/// @return -/// Returns status for an ongoing transfer. -/// @li #i2cTransferInProgress - indicates that transfer not finished. -/// @li #i2cTransferDone - transfer completed successfully. -/// @li otherwise some sort of error has occurred. -/// -// ***************************************************************************** -I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) -{ - uint32_t tmp; - uint32_t pending; - I2C_Transfer_TypeDef *transfer; - I2C_TransferSeq_TypeDef *seq; - bool finished = false; - - EFM_ASSERT(I2C_REF_VALID(i2c)); - - /* Support up to 2 I2C buses. */ - if (i2c == I2C0) { - transfer = i2cTransfer; - } -#if (I2C_COUNT > 1) - else if (i2c == I2C1) { - transfer = i2cTransfer + 1; - } -#endif -#if (I2C_COUNT > 2) - else if (i2c == I2C2) { - transfer = i2cTransfer + 2; - } -#endif -#if (I2C_COUNT > 3) - else if (i2c == I2C3) { - transfer = i2cTransfer + 3; - } -#endif - else { - return i2cTransferUsageFault; - } - - seq = transfer->seq; - while (!finished) { - pending = i2c->IF; - - /* If some sort of fault, abort transfer. */ - if (pending & I2C_IF_ERRORS) { - if (pending & I2C_IF_ARBLOST) { - /* If an arbitration fault, indicates either a slave device */ - /* not responding as expected, or other master which is not */ - /* supported by this software. */ - transfer->result = i2cTransferArbLost; - } else if (pending & I2C_IF_BUSERR) { - /* A bus error indicates a misplaced start or stop, which should */ - /* not occur in master mode controlled by this software. */ - transfer->result = i2cTransferBusErr; - } - - /* Ifan error occurs, it is difficult to know */ - /* an exact cause and how to resolve. It will be up to a wrapper */ - /* to determine how to handle a fault/recovery if possible. */ - transfer->state = i2cStateDone; - break; - } - - switch (transfer->state) { - /***************************************************/ - /* Send the first start+address (first byte if 10 bit). */ - /***************************************************/ - case i2cStateStartAddrSend: - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; - - /* In 10 bit address mode, the address following the first */ - /* start always indicates write. */ - } else { - tmp = (uint32_t)(seq->addr) & 0xfe; - - if (seq->flags & I2C_FLAG_READ) { - /* Indicate read request */ - tmp |= 1; - } - } - - transfer->state = i2cStateAddrWFAckNack; - i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ - i2c->CMD = I2C_CMD_START; - finished = true; - break; - - /*******************************************************/ - /* Wait for ACK/NACK on the address (first byte if 10 bit). */ - /*******************************************************/ - case i2cStateAddrWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* If a 10 bit address, send the 2nd byte of the address. */ - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - transfer->state = i2cStateAddrWF2ndAckNack; - i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; - } else { - /* Determine whether receiving or sending data. */ - if (seq->flags & I2C_FLAG_READ) { - transfer->state = i2cStateWFData; - if (seq->buf[transfer->bufIndx].len == 1) { - i2c->CMD = I2C_CMD_NACK; - } - } else { - transfer->state = i2cStateDataSend; - continue; - } - } - } - finished = true; - break; - - /******************************************************/ - /* Wait for ACK/NACK on the second byte of a 10 bit address. */ - /******************************************************/ - case i2cStateAddrWF2ndAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* If using a plain read sequence with a 10 bit address, switch to send */ - /* a repeated start. */ - if (seq->flags & I2C_FLAG_READ) { - transfer->state = i2cStateRStartAddrSend; - } - /* Otherwise, expected to write 0 or more bytes. */ - else { - transfer->state = i2cStateDataSend; - } - continue; - } - finished = true; - break; - - /*******************************/ - /* Send a repeated start+address */ - /*******************************/ - case i2cStateRStartAddrSend: - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - tmp = (uint32_t)((seq->addr >> 8) & 0x06) | 0xf0; - } else { - tmp = (uint32_t)(seq->addr & 0xfe); - } - - /* If this is a write+read combined sequence, read is about to start. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - /* Indicate a read request. */ - tmp |= 1; - /* If reading only one byte, prepare the NACK now before START command. */ - if (seq->buf[transfer->bufIndx].len == 1) { - i2c->CMD = I2C_CMD_NACK; - } - } - - transfer->state = i2cStateRAddrWFAckNack; - /* The START command has to be written first since repeated start. Otherwise, */ - /* data would be sent first. */ - i2c->CMD = I2C_CMD_START; - i2c->TXDATA = tmp; - - finished = true; - break; - - /**********************************************************************/ - /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ - /**********************************************************************/ - case i2cStateRAddrWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* Determine whether receiving or sending data. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - transfer->state = i2cStateWFData; - } else { - transfer->state = i2cStateDataSend; - continue; - } - } - finished = true; - break; - - /*****************************/ - /* Send a data byte to the slave */ - /*****************************/ - case i2cStateDataSend: - /* Reached end of data buffer. */ - if (transfer->offset >= seq->buf[transfer->bufIndx].len) { - /* Move to the next message part. */ - transfer->offset = 0; - transfer->bufIndx++; - - /* Send a repeated start when switching to read mode on the 2nd buffer. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - transfer->state = i2cStateRStartAddrSend; - continue; - } - - /* Only writing from one buffer or finished both buffers. */ - if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - finished = true; - break; - } - - /* Reprocess in case the next buffer is empty. */ - continue; - } - - /* Send byte. */ - i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); - transfer->state = i2cStateDataWFAckNack; - finished = true; - break; - - /*********************************************************/ - /* Wait for ACK/NACK from the slave after sending data to it. */ - /*********************************************************/ - case i2cStateDataWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - transfer->state = i2cStateDataSend; - continue; - } - finished = true; - break; - - /****************************/ - /* Wait for data from slave */ - /****************************/ - case i2cStateWFData: - if (pending & I2C_IF_RXDATAV) { - uint8_t data; - unsigned int rxLen = seq->buf[transfer->bufIndx].len; - - /* Must read out data not to block further progress. */ - data = (uint8_t)(i2c->RXDATA); - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)) - // Errata I2C_E303. I2C Fails to Indicate New Incoming Data. - uint32_t status = i2c->STATUS; - // look for invalid RXDATAV = 0 and RXFULL = 1 condition - if (((status & I2C_IF_RXDATAV) == 0) & ((status & I2C_IF_RXFULL) != 0)) { - // Performing a dummy read of the RXFIFO (I2C_RXDATA). - // This restores the expected RXDATAV = 1 and RXFULL = 0 condition. - (void)i2c->RXDATA; - // The dummy read will also set the RXUFIF flag bit, which should be ignored and cleared. - I2C_IntClear(i2c, I2C_IF_RXUF); - } -#endif - - /* SW needs to clear RXDATAV IF on Series 2 devices. - Flag is kept high by HW if buffer is not empty. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - I2C_IntClear(i2c, I2C_IF_RXDATAV); -#endif - - /* Make sure that there is no storing beyond the end of the buffer (just in case). */ - if (transfer->offset < rxLen) { - seq->buf[transfer->bufIndx].data[transfer->offset++] = data; - } - - /* If all requested data is read, the sequence should end. */ - if (transfer->offset >= rxLen) { - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else { - /* Send ACK and wait for the next byte. */ - i2c->CMD = I2C_CMD_ACK; - - if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { - /* If receiving more than one byte and this is the next - to last byte, transmit the NACK now before receiving - the last byte. */ - i2c->CMD = I2C_CMD_NACK; - } - } - } - finished = true; - break; - - /***********************************/ - /* Wait for STOP to have been sent */ - /***********************************/ - case i2cStateWFStopSent: - if (pending & I2C_IF_MSTOP) { - I2C_IntClear(i2c, I2C_IF_MSTOP); - transfer->state = i2cStateDone; - } - finished = true; - break; - - /******************************/ - /* An unexpected state, software fault */ - /******************************/ - default: - transfer->result = i2cTransferSwFault; - transfer->state = i2cStateDone; - finished = true; - break; - } - } - - if (transfer->state == i2cStateDone) { - /* Disable interrupt sources when done. */ - i2c->IEN = 0; - - /* Update the result unless a fault has already occurred. */ - if (transfer->result == i2cTransferInProgress) { - transfer->result = i2cTransferDone; - } - } - /* Until transfer is done, keep returning i2cTransferInProgress. */ - else { - return i2cTransferInProgress; - } - - return transfer->result; -} - -/***************************************************************************//** - * @brief - * Prepare and start an I2C transfer (single master mode only). - * - * @details - * This function must be invoked to start an I2C transfer - * sequence. To complete the transfer, I2C_Transfer() must - * be used either in polled mode or by adding a small driver wrapper using - * interrupts. - * - * @note - * Only single master mode is supported. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] seq - * A pointer to the sequence structure defining the I2C transfer to take place. The - * referenced structure must exist until the transfer has fully completed. - * - * @return - * Returns the status for an ongoing transfer: - * @li #i2cTransferInProgress - indicates that the transfer is not finished. - * @li Otherwise, an error has occurred. - ******************************************************************************/ -I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, - I2C_TransferSeq_TypeDef *seq) -{ - I2C_Transfer_TypeDef *transfer; - - EFM_ASSERT(I2C_REF_VALID(i2c)); - EFM_ASSERT(seq); - - /* Support up to 2 I2C buses. */ - if (i2c == I2C0) { - transfer = i2cTransfer; - } -#if (I2C_COUNT > 1) - else if (i2c == I2C1) { - transfer = i2cTransfer + 1; - } -#endif -#if (I2C_COUNT > 2) - else if (i2c == I2C2) { - transfer = i2cTransfer + 2; - } -#endif -#if (I2C_COUNT > 3) - else if (i2c == I2C3) { - transfer = i2cTransfer + 3; - } -#endif - else { - return i2cTransferUsageFault; - } - - /* Check if in a busy state. Since this software assumes a single master, */ - /* issue an abort. The BUSY state is normal after a reset. */ - if (i2c->STATE & I2C_STATE_BUSY) { - i2c->CMD = I2C_CMD_ABORT; - } - - /* Do not try to read 0 bytes. It is not */ - /* possible according to the I2C spec, since the slave will always start */ - /* sending the first byte ACK on an address. The read operation can */ - /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ - if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) - || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) - ) { - return i2cTransferUsageFault; - } - - /* Prepare for a transfer. */ - transfer->state = i2cStateStartAddrSend; - transfer->result = i2cTransferInProgress; - transfer->offset = 0; - transfer->bufIndx = 0; - transfer->seq = seq; - - /* Ensure buffers are empty. */ - i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; - flushRx(i2c); - - /* Clear all pending interrupts prior to starting a transfer. */ - I2C_IntClear(i2c, _I2C_IF_MASK); - - /* Enable relevant interrupts. */ - /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ - /* that is left for an additional driver wrapper. */ - i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP - | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; - - /* Start a transfer. */ - return I2C_Transfer(i2c); -} - -/** @} (end addtogroup i2c) */ -#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Inter-integrated Circuit (I2C) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_i2c.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" + + #include + +/***************************************************************************//** + * @addtogroup i2c I2C - Inter-Integrated Circuit + * @brief Inter-integrated Circuit (I2C) Peripheral API + * @details + * This module contains functions to control the I2C peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C + * buses with the lowest energy consumption possible. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the I2C register block pointer reference for assert statements. */ +#if (I2C_COUNT == 1) +#define I2C_REF_VALID(ref) ((ref) == I2C0) +#elif (I2C_COUNT == 2) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) +#elif (I2C_COUNT == 3) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) +#elif (I2C_COUNT == 4) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2) || ((ref) == I2C3)) +#endif + +/** Error flags indicating that the I2C transfer has failed. */ +/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ +/* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ +/* RXUF is only likely to occur with the software if using a debugger peeking into */ +/* the RXDATA register. Therefore, those types of faults are ignored. */ +#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) +#define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) + +/* Maximum I2C transmission rate constant. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY) +#define I2C_CR_MAX 8 +#else +#define I2C_CR_MAX 4 +#endif +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define I2C_CR_MAX 8 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_CR_MAX 8 +#else +#warning "Max I2C transmission rate constant is not defined" +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Master mode transfer states. */ +typedef enum { + i2cStateStartAddrSend, /**< Send start + (first part of) address. */ + i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ + i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ + i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ + i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ + i2cStateDataSend, /**< Send data. */ + i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ + i2cStateWFData, /**< Wait for data. */ + i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ + i2cStateDone /**< Transfer completed successfully. */ +} I2C_TransferState_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Structure used to store state information on an ongoing master mode transfer. */ +typedef struct { + /** Current state. */ + I2C_TransferState_TypeDef state; + + /** Result return code. */ + I2C_TransferReturn_TypeDef result; + + /** Offset in the current sequence buffer. */ + uint16_t offset; + + /* Index to the current sequence buffer in use. */ + uint8_t bufIndx; + + /** Reference to the I2C transfer sequence definition provided by the user. */ + I2C_TransferSeq_TypeDef *seq; +} I2C_Transfer_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ***************************** LOCAL DATA *******^************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** + * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined + * index (0x3) to reflect a default setting just in case. + */ +static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; + +/** A transfer state information for an ongoing master mode transfer. */ +static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Empty received data buffer. + ******************************************************************************/ +static void flushRx(I2C_TypeDef *i2c) +{ + while (i2c->STATUS & I2C_STATUS_RXDATAV) { + i2c->RXDATA; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current configured I2C bus frequency. + * + * @details + * This frequency is only relevant when acting as master. + * + * @note + * The actual frequency is a real number, this function returns a rounded + * down (truncated) integer value. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @return + * The current I2C frequency in Hz. + ******************************************************************************/ +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) +{ + uint32_t freqHfper = 0; + uint32_t n; + + /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + if (i2c == I2C0) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) + >> _I2C_CTRL_CLHR_SHIFT]; + return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); +} + +/***************************************************************************//** + * @brief + * Set the I2C bus frequency. + * + * @details + * The bus frequency is only relevant when acting as master. The bus + * frequency should not be set higher than the maximum frequency accepted by the + * slowest device on the bus. + * + * Notice that, due to asymmetric requirements on low and high I2C clock + * cycles in the I2C specification, the maximum frequency allowed + * to comply with the specification may be somewhat lower than expected. + * + * See the reference manual, details on I2C clock generation, + * for maximum allowed theoretical frequencies for different modes. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] freqRef + * An I2C reference clock frequency in Hz that will be used. If set to 0, + * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual + * configured value has the consequence of reducing the real I2C frequency. + * + * @param[in] freqScl + * A bus frequency to set (bus speed may be lower due to integer + * prescaling). Safe (according to the I2C specification) maximum frequencies for + * standard fast and fast+ modes are available using I2C_FREQ_ defines. + * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) + * The slowest slave device on a bus must always be considered. + * + * @param[in] i2cMode + * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, + * make sure all devices on the bus support the specified mode. Using a + * non-standard ratio is useful to achieve a higher bus clock in fast and + * fast+ modes. + ******************************************************************************/ +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode) +{ + uint32_t n, minFreq, denominator; + int32_t div; + + /* Avoid dividing by 0. */ + EFM_ASSERT(freqScl); + if (!freqScl) { + return; + } + + /* Ensure mode is valid */ + i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; + + /* Set the CLHR (clock low-to-high ratio). */ + i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; + BUS_RegMaskedWrite(&i2c->CTRL, + _I2C_CTRL_CLHR_MASK, + i2cMode << _I2C_CTRL_CLHR_SHIFT); + + if (freqRef == 0) { + if (i2c == I2C0) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + } + + /* Check the minumum HF peripheral clock. */ + minFreq = UINT_MAX; + if (i2c->CTRL & I2C_CTRL_SLAVE) { + switch (i2cMode) { + case i2cClockHLRStandard: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 4200000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 2000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 2000000; break; +#endif + case i2cClockHLRAsymetric: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 11000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 5000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 5000000; break; +#endif + case i2cClockHLRFast: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 24400000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 14000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 14000000; break; +#endif + default: + /* MISRA requires the default case. */ + break; + } + } else { + /* For master mode, platform 1 and 2 share the same + minimum frequencies. */ + switch (i2cMode) { + case i2cClockHLRStandard: + minFreq = 2000000; break; + case i2cClockHLRAsymetric: + minFreq = 9000000; break; + case i2cClockHLRFast: + minFreq = 20000000; break; + default: + /* MISRA requires default case */ + break; + } + } + + /* Frequency most be larger-than. */ + EFM_ASSERT(freqRef > minFreq); + + /* SCL frequency is given by: + * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) + * + * Therefore, + * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 + * + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[i2cMode]; + denominator = n * freqScl; + + /* Explicitly ensure denominator is never zero. */ + if (denominator == 0) { + EFM_ASSERT(0); + return; + } + /* Perform integer division so that div is rounded up. */ + div = (int32_t)(((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) + / denominator) - 1); + EFM_ASSERT(div >= 0); + EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); + + /* The clock divisor must be at least 1 in slave mode according to the reference */ + /* manual (in which case there is normally no need to set the bus frequency). */ + if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { + div = 1; + } + i2c->CLKDIV = (uint32_t)div; +} + +/***************************************************************************//** + * @brief + * Enable/disable I2C. + * + * @note + * After enabling the I2C (from being disabled), the I2C is in BUSY state. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void I2C_Enable(I2C_TypeDef *i2c, bool enable) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + +#if defined (_I2C_EN_MASK) + BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Initialize I2C. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] init + * A pointer to the I2C initialization structure. + ******************************************************************************/ +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + + i2c->IEN = 0; + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Set SLAVE select mode. */ + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); + + I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); + + I2C_Enable(i2c, init->enable); +} + +/***************************************************************************//** + * @brief + * Reset I2C to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + ******************************************************************************/ +void I2C_Reset(I2C_TypeDef *i2c) +{ + // Cancel ongoing operations and clear TX buffer + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; + i2c->CTRL = _I2C_CTRL_RESETVALUE; + i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; + i2c->SADDR = _I2C_SADDR_RESETVALUE; + i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; + i2c->IEN = _I2C_IEN_RESETVALUE; +#if defined (_I2C_EN_EN_MASK) + i2c->EN = _I2C_EN_RESETVALUE; +#endif + + // Empty received data buffer + flushRx(i2c); + I2C_IntClear(i2c, _I2C_IF_MASK); + /* Do not reset the route register; setting should be done independently. */ +} + +// ***************************************************************************** +/// @brief +/// Continue an initiated I2C transfer (single master mode only). +/// +/// @details +/// This function is used repeatedly after a I2C_TransferInit() to +/// complete a transfer. It may be used in polled mode as the below example +/// shows: +/// @code{.c} +/// I2C_TransferReturn_TypeDef ret; +/// +/// // Do a polled transfer +/// ret = I2C_TransferInit(I2C0, seq); +/// while (ret == i2cTransferInProgress) +/// { +/// ret = I2C_Transfer(I2C0); +/// } +/// @endcode +/// It may also be used in interrupt driven mode, where this function is invoked +/// from the interrupt handler. Notice that, if used in interrupt mode, NVIC +/// interrupts must be configured and enabled for the I2C bus used. I2C +/// peripheral specific interrupts are managed by this software. +/// +/// @note +/// Only single master mode is supported. +/// +/// @param[in] i2c +/// A pointer to the I2C peripheral register block. +/// +/// @return +/// Returns status for an ongoing transfer. +/// @li #i2cTransferInProgress - indicates that transfer not finished. +/// @li #i2cTransferDone - transfer completed successfully. +/// @li otherwise some sort of error has occurred. +/// +// ***************************************************************************** +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) +{ + uint32_t tmp; + uint32_t pending; + I2C_Transfer_TypeDef *transfer; + I2C_TransferSeq_TypeDef *seq; + bool finished = false; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + seq = transfer->seq; + while (!finished) { + pending = i2c->IF; + + /* If some sort of fault, abort transfer. */ + if (pending & I2C_IF_ERRORS) { + if (pending & I2C_IF_ARBLOST) { + /* If an arbitration fault, indicates either a slave device */ + /* not responding as expected, or other master which is not */ + /* supported by this software. */ + transfer->result = i2cTransferArbLost; + } else if (pending & I2C_IF_BUSERR) { + /* A bus error indicates a misplaced start or stop, which should */ + /* not occur in master mode controlled by this software. */ + transfer->result = i2cTransferBusErr; + } + + /* Ifan error occurs, it is difficult to know */ + /* an exact cause and how to resolve. It will be up to a wrapper */ + /* to determine how to handle a fault/recovery if possible. */ + transfer->state = i2cStateDone; + break; + } + + switch (transfer->state) { + /***************************************************/ + /* Send the first start+address (first byte if 10 bit). */ + /***************************************************/ + case i2cStateStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; + + /* In 10 bit address mode, the address following the first */ + /* start always indicates write. */ + } else { + tmp = (uint32_t)(seq->addr) & 0xfe; + + if (seq->flags & I2C_FLAG_READ) { + /* Indicate read request */ + tmp |= 1; + } + } + + transfer->state = i2cStateAddrWFAckNack; + i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ + i2c->CMD = I2C_CMD_START; + finished = true; + break; + + /*******************************************************/ + /* Wait for ACK/NACK on the address (first byte if 10 bit). */ + /*******************************************************/ + case i2cStateAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If a 10 bit address, send the 2nd byte of the address. */ + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + transfer->state = i2cStateAddrWF2ndAckNack; + i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; + } else { + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateWFData; + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + } + finished = true; + break; + + /******************************************************/ + /* Wait for ACK/NACK on the second byte of a 10 bit address. */ + /******************************************************/ + case i2cStateAddrWF2ndAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If using a plain read sequence with a 10 bit address, switch to send */ + /* a repeated start. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateRStartAddrSend; + } + /* Otherwise, expected to write 0 or more bytes. */ + else { + transfer->state = i2cStateDataSend; + } + continue; + } + finished = true; + break; + + /*******************************/ + /* Send a repeated start+address */ + /*******************************/ + case i2cStateRStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (uint32_t)((seq->addr >> 8) & 0x06) | 0xf0; + } else { + tmp = (uint32_t)(seq->addr & 0xfe); + } + + /* If this is a write+read combined sequence, read is about to start. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + /* Indicate a read request. */ + tmp |= 1; + /* If reading only one byte, prepare the NACK now before START command. */ + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } + + transfer->state = i2cStateRAddrWFAckNack; + /* The START command has to be written first since repeated start. Otherwise, */ + /* data would be sent first. */ + i2c->CMD = I2C_CMD_START; + i2c->TXDATA = tmp; + + finished = true; + break; + + /**********************************************************************/ + /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ + /**********************************************************************/ + case i2cStateRAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateWFData; + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + finished = true; + break; + + /*****************************/ + /* Send a data byte to the slave */ + /*****************************/ + case i2cStateDataSend: + /* Reached end of data buffer. */ + if (transfer->offset >= seq->buf[transfer->bufIndx].len) { + /* Move to the next message part. */ + transfer->offset = 0; + transfer->bufIndx++; + + /* Send a repeated start when switching to read mode on the 2nd buffer. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateRStartAddrSend; + continue; + } + + /* Only writing from one buffer or finished both buffers. */ + if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + finished = true; + break; + } + + /* Reprocess in case the next buffer is empty. */ + continue; + } + + /* Send byte. */ + i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); + transfer->state = i2cStateDataWFAckNack; + finished = true; + break; + + /*********************************************************/ + /* Wait for ACK/NACK from the slave after sending data to it. */ + /*********************************************************/ + case i2cStateDataWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + transfer->state = i2cStateDataSend; + continue; + } + finished = true; + break; + + /****************************/ + /* Wait for data from slave */ + /****************************/ + case i2cStateWFData: + if (pending & I2C_IF_RXDATAV) { + uint8_t data; + unsigned int rxLen = seq->buf[transfer->bufIndx].len; + + /* Must read out data not to block further progress. */ + data = (uint8_t)(i2c->RXDATA); + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)) + // Errata I2C_E303. I2C Fails to Indicate New Incoming Data. + uint32_t status = i2c->STATUS; + // look for invalid RXDATAV = 0 and RXFULL = 1 condition + if (((status & I2C_IF_RXDATAV) == 0) & ((status & I2C_IF_RXFULL) != 0)) { + // Performing a dummy read of the RXFIFO (I2C_RXDATA). + // This restores the expected RXDATAV = 1 and RXFULL = 0 condition. + (void)i2c->RXDATA; + // The dummy read will also set the RXUFIF flag bit, which should be ignored and cleared. + I2C_IntClear(i2c, I2C_IF_RXUF); + } +#endif + + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif + + /* Make sure that there is no storing beyond the end of the buffer (just in case). */ + if (transfer->offset < rxLen) { + seq->buf[transfer->bufIndx].data[transfer->offset++] = data; + } + + /* If all requested data is read, the sequence should end. */ + if (transfer->offset >= rxLen) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else { + /* Send ACK and wait for the next byte. */ + i2c->CMD = I2C_CMD_ACK; + + if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { + /* If receiving more than one byte and this is the next + to last byte, transmit the NACK now before receiving + the last byte. */ + i2c->CMD = I2C_CMD_NACK; + } + } + } + finished = true; + break; + + /***********************************/ + /* Wait for STOP to have been sent */ + /***********************************/ + case i2cStateWFStopSent: + if (pending & I2C_IF_MSTOP) { + I2C_IntClear(i2c, I2C_IF_MSTOP); + transfer->state = i2cStateDone; + } + finished = true; + break; + + /******************************/ + /* An unexpected state, software fault */ + /******************************/ + default: + transfer->result = i2cTransferSwFault; + transfer->state = i2cStateDone; + finished = true; + break; + } + } + + if (transfer->state == i2cStateDone) { + /* Disable interrupt sources when done. */ + i2c->IEN = 0; + + /* Update the result unless a fault has already occurred. */ + if (transfer->result == i2cTransferInProgress) { + transfer->result = i2cTransferDone; + } + } + /* Until transfer is done, keep returning i2cTransferInProgress. */ + else { + return i2cTransferInProgress; + } + + return transfer->result; +} + +/***************************************************************************//** + * @brief + * Prepare and start an I2C transfer (single master mode only). + * + * @details + * This function must be invoked to start an I2C transfer + * sequence. To complete the transfer, I2C_Transfer() must + * be used either in polled mode or by adding a small driver wrapper using + * interrupts. + * + * @note + * Only single master mode is supported. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] seq + * A pointer to the sequence structure defining the I2C transfer to take place. The + * referenced structure must exist until the transfer has fully completed. + * + * @return + * Returns the status for an ongoing transfer: + * @li #i2cTransferInProgress - indicates that the transfer is not finished. + * @li Otherwise, an error has occurred. + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq) +{ + I2C_Transfer_TypeDef *transfer; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + EFM_ASSERT(seq); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + /* Check if in a busy state. Since this software assumes a single master, */ + /* issue an abort. The BUSY state is normal after a reset. */ + if (i2c->STATE & I2C_STATE_BUSY) { + i2c->CMD = I2C_CMD_ABORT; + } + + /* Do not try to read 0 bytes. It is not */ + /* possible according to the I2C spec, since the slave will always start */ + /* sending the first byte ACK on an address. The read operation can */ + /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ + if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) + || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) + ) { + return i2cTransferUsageFault; + } + + /* Prepare for a transfer. */ + transfer->state = i2cStateStartAddrSend; + transfer->result = i2cTransferInProgress; + transfer->offset = 0; + transfer->bufIndx = 0; + transfer->seq = seq; + + /* Ensure buffers are empty. */ + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; + flushRx(i2c); + + /* Clear all pending interrupts prior to starting a transfer. */ + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Enable relevant interrupts. */ + /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ + /* that is left for an additional driver wrapper. */ + i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP + | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; + + /* Start a transfer. */ + return I2C_Transfer(i2c); +} + +/** @} (end addtogroup i2c) */ +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c index 8981b26..f2d5f3d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c @@ -1,1178 +1,1178 @@ -/***************************************************************************//** - * @file - * @brief Incremental Analog to Digital Converter (IADC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_iadc.h" - -#if defined(IADC_COUNT) && (IADC_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include - -/***************************************************************************//** - * @addtogroup emlib - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup iadc IADC - Incremental ADC - * @brief Incremental Analog to Digital Converter (IADC) Peripheral API - * @details - * This module contains functions to control the IADC peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The IADC is used to convert analog signals into a - * digital representation. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -// Validation of IADC register block pointer reference for assert statements. -#if defined(IADC_NUM) -#define IADC_REF_VALID(ref) (IADC_NUM(ref) != -1) -#else -#if (IADC_COUNT == 1) -#define IADC_REF_VALID(ref) ((ref) == IADC0) -#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : -1) -#elif (IADC_COUNT == 2) -#define IADC_REF_VALID(ref) (((ref) == IADC0) || ((ref) == IADC1)) -#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : ((ref) == IADC1) ? 1 : -1) -#endif -#endif - -// Max IADC clock rates -#define IADC_CLK_MAX_FREQ 40000000UL -#define IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ 20000000UL -#define IADC_ANA_CLK_NORMAL_MAX_FREQ 10000000UL -#define IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ 5000000UL -#if defined (_IADC_CFG_ADCMODE_HIGHSPEED) -#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ - (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ - : ((adcMode) == iadcCfgModeHighSpeed \ - ? IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ \ - : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ) \ - ) -#else -#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ - (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ - : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ \ - ) -#endif - -#define IADC_ROUND_D2I(n) (int)((n) < 0.0f ? ((n) - 0.5f) : ((n) + 0.5f)) - -#define IADC0_SCANENTRIES IADC0_ENTRIES -#define IADC0_FIFOENTRIES 0x4UL - -#define IADC1_SCANENTRIES IADC1_ENTRIES -#define IADC1_FIFOENTRIES 0x4UL - -#if defined(IADC_ENTRIES) -#define IADC_SCANENTRIES(iadc) IADC_ENTRIES(IADC_NUM(iadc)) -#else -#define IADC_SCANENTRIES(iadc) ( \ - (iadc) == IADC0 ? IADC0_SCANENTRIES \ - : 0UL) -#endif - -#if !defined(IADC_CONFIGNUM) -#define IADC_CONFIGNUM(iadc) ( \ - (iadc) == 0 ? IADC0_CONFIGNUM \ - : 0UL) -#endif - -#define IADC_FIFOENTRIES(iadc) ( \ - (iadc) == IADC0 ? IADC0_FIFOENTRIES \ - : 0UL) - -#define IADC_CMU_CLOCK(iadc) ( \ - (iadc) == IADC0 ? cmuClock_IADC0 \ - : cmuClock_IADC0) - -/** @endcond */ - -/******************************************************************************* - *************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -static void IADC_disable(IADC_TypeDef *iadc) -{ -#if defined(IADC_STATUS_SYNCBUSY) - while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { - // Wait for synchronization to finish before disable - } -#endif - iadc->EN_CLR = IADC_EN_EN; -#if defined(_IADC_EN_DISABLING_MASK) - while (IADC0->EN & _IADC_EN_DISABLING_MASK) { - } -#endif -} - -static void IADC_enable(IADC_TypeDef *iadc) -{ - iadc->EN_SET = IADC_EN_EN; -} - -static IADC_Result_t IADC_ConvertRawDataToResult(uint32_t rawData, - IADC_Alignment_t alignment) -{ - IADC_Result_t result; - - switch (alignment) { - case iadcAlignRight12: -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - case iadcAlignRight16: -#endif -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - case iadcAlignRight20: -#endif - // Mask out ID and replace with sign extension - result.data = (rawData & 0x00FFFFFFUL) - | ((rawData & 0x00800000UL) != 0x0UL ? 0xFF000000UL : 0x0UL); - // Mask out data and shift down - result.id = (uint8_t)((rawData & 0xFF000000UL) >> 24); - break; - - case iadcAlignLeft12: -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - case iadcAlignLeft16: -#endif -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - case iadcAlignLeft20: -#endif - result.data = rawData & 0xFFFFFF00UL; - result.id = (uint8_t)(rawData & 0x000000FFUL); - break; - default: - break; - } - return result; -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize IADC. - * - * @details - * Initializes common parts for both single conversion and scan sequence. - * In addition, single and/or scan control configuration must be done, please - * refer to @ref IADC_initSingle() and @ref IADC_initScan() respectively. - * - * @note - * This function will stop any ongoing conversions. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC initialization structure. - * - * @param[in] allConfigs - * Pointer to structure holding all configs. - ******************************************************************************/ -void IADC_init(IADC_TypeDef *iadc, - const IADC_Init_t *init, - const IADC_AllConfigs_t *allConfigs) -{ - uint32_t tmp; - uint32_t config; - uint16_t wantedPrescale; - uint8_t srcClkPrescale; - uint32_t adcClkPrescale; - uint8_t timebase; - unsigned uiAnaGain; - uint16_t uiGainCAna; - IADC_CfgAdcMode_t adcMode; -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - float anaGain; - int anaGainRound; - float offsetAna; - float offset2; - int offsetLong; - int offsetAna1HiAccInt; - uint8_t osrValue; - float offsetAnaBase; - float gainSysHiAcc; - float refVoltage = 0; - // Over sampling ratio for high accuracy conversions - const float osrHiAcc[6] = { 16.0, 32.0, 64.0, 92.0, 128.0, 256.0 }; -#endif - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - // Calculate min allowed SRC_CLK prescaler setting - srcClkPrescale = IADC_calcSrcClkPrescale(iadc, IADC_CLK_MAX_FREQ, 0); - - wantedPrescale = init->srcClkPrescale; - // Use wanted SRC_CLK prescaler setting instead if it is high enough - if (wantedPrescale >= srcClkPrescale) { - srcClkPrescale = wantedPrescale; - } - - IADC_disable(iadc); - - timebase = init->timebase; - if (timebase == 0) { - // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set - // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. - uint32_t srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); - // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE to obtain valid frequency - if (srcClkFreq >= IADC_CLK_MAX_FREQ) { - srcClkFreq = srcClkFreq / srcClkPrescale; - } - // Calculate timebase based on CMU_IADCCLKCTRL - timebase = IADC_calcTimebase(iadc, srcClkFreq); - } - - tmp = (((uint32_t)(init->warmup) << _IADC_CTRL_WARMUPMODE_SHIFT) - & _IADC_CTRL_WARMUPMODE_MASK) - | (((uint32_t)(timebase) << _IADC_CTRL_TIMEBASE_SHIFT) - & _IADC_CTRL_TIMEBASE_MASK) - | (((uint32_t)(srcClkPrescale) << _IADC_CTRL_HSCLKRATE_SHIFT) - & _IADC_CTRL_HSCLKRATE_MASK); - - if (init->iadcClkSuspend0) { - tmp |= IADC_CTRL_ADCCLKSUSPEND0; - } - if (init->iadcClkSuspend1) { - tmp |= IADC_CTRL_ADCCLKSUSPEND1; - } - if (init->debugHalt) { - tmp |= IADC_CTRL_DBGHALT; - } - iadc->CTRL = tmp; - - iadc->TIMER = ((uint32_t) (init->timerCycles) << _IADC_TIMER_TIMER_SHIFT) - & _IADC_TIMER_TIMER_MASK; - - iadc->CMPTHR = (((uint32_t) (init->greaterThanEqualThres) << _IADC_CMPTHR_ADGT_SHIFT) - & _IADC_CMPTHR_ADGT_MASK) - | (((uint32_t) (init->lessThanEqualThres) << _IADC_CMPTHR_ADLT_SHIFT) - & _IADC_CMPTHR_ADLT_MASK); - - // Write configurations - for (config = 0; config < IADC_CONFIGNUM(IADC_NUM(iadc)); config++) { - // Find min allowed ADC_CLK prescaler setting for given mode - adcMode = allConfigs->configs[config].adcMode; - wantedPrescale = allConfigs->configs[config].adcClkPrescale; - adcClkPrescale = IADC_calcAdcClkPrescale(iadc, - IADC_ANA_CLK_MAX_FREQ(adcMode), - 0, - adcMode, - srcClkPrescale); - - // Use wanted ADC_CLK prescaler setting instead if it is high enough - adcClkPrescale = SL_MAX(adcClkPrescale, wantedPrescale); - - tmp = iadc->CFG[config].CFG & ~(_IADC_CFG_ADCMODE_MASK | _IADC_CFG_OSRHS_MASK - | _IADC_CFG_ANALOGGAIN_MASK | _IADC_CFG_REFSEL_MASK -#if defined(_IADC_CFG_DIGAVG_MASK) - | _IADC_CFG_DIGAVG_MASK -#endif - | _IADC_CFG_TWOSCOMPL_MASK -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - | _IADC_CFG_OSRHA_MASK -#endif - ); - iadc->CFG[config].CFG = tmp - | (((uint32_t)(adcMode) << _IADC_CFG_ADCMODE_SHIFT) & _IADC_CFG_ADCMODE_MASK) - | (((uint32_t)(allConfigs->configs[config].osrHighSpeed) << _IADC_CFG_OSRHS_SHIFT) - & _IADC_CFG_OSRHS_MASK) -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - | (((uint32_t)(allConfigs->configs[config].osrHighAccuracy) << _IADC_CFG_OSRHA_SHIFT) - & _IADC_CFG_OSRHA_MASK) -#endif - | (((uint32_t)(allConfigs->configs[config].analogGain) << _IADC_CFG_ANALOGGAIN_SHIFT) - & _IADC_CFG_ANALOGGAIN_MASK) - | (((uint32_t)(allConfigs->configs[config].reference) << _IADC_CFG_REFSEL_SHIFT) - & _IADC_CFG_REFSEL_MASK) -#if defined(_IADC_CFG_DIGAVG_MASK) - | (((uint32_t)(allConfigs->configs[config].digAvg) << _IADC_CFG_DIGAVG_SHIFT) - & _IADC_CFG_DIGAVG_MASK) -#endif - | (((uint32_t)(allConfigs->configs[config].twosComplement) << _IADC_CFG_TWOSCOMPL_SHIFT) - & _IADC_CFG_TWOSCOMPL_MASK); - - uiAnaGain = (iadc->CFG[config].CFG & _IADC_CFG_ANALOGGAIN_MASK) >> _IADC_CFG_ANALOGGAIN_SHIFT; - switch (uiAnaGain) { -#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) - case iadcCfgAnalogGain0P25x: // 0.25x -#endif - case iadcCfgAnalogGain0P5x: // 0.5x - case iadcCfgAnalogGain1x: // 1x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); - break; - case iadcCfgAnalogGain2x: // 2x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA2_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT); - break; - case iadcCfgAnalogGain3x: // 3x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA3_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT); - break; - case iadcCfgAnalogGain4x: // 4x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA4_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT); - break; - default: // 1x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); - break; - } - - // Gain and offset correction is applied according to adcMode and oversampling rate. - switch (adcMode) { - float offset; - uint32_t scale; - int iOffset, iOsr; - case iadcCfgModeNormal: -#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) - case iadcCfgModeHighSpeed: -#endif - offset = 0.0f; - if (uiAnaGain == iadcCfgAnalogGain2x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT); - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT); - } - } else if (uiAnaGain == iadcCfgAnalogGain3x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 2; - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 2; - } - } else if (uiAnaGain == iadcCfgAnalogGain4x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 3; - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 3; - } - } - - // Set correct gain correction bitfields in scale variable. - tmp = (uint32_t)uiGainCAna & 0x9FFFU; - scale = tmp << _IADC_SCALE_GAIN13LSB_SHIFT; - if ((tmp & 0x8000U) != 0U) { - scale |= IADC_SCALE_GAIN3MSB; - } - - // Adjust offset according to selected OSR. - iOsr = 1U << (((iadc->CFG[config].CFG & _IADC_CFG_OSRHS_MASK) >> _IADC_CFG_OSRHS_SHIFT) + 1U); - if (iOsr == 2) { - if (adcMode == iadcCfgModeNormal) { - offset += (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 & _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK); - } else { - offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 & _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK); - } - } else { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL1 & _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK) - offset; - } else { - offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL1 & _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK) - offset; - } - offset /= iOsr / 2.0f; - offset += (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK); - } - - // Compensate offset according to selected reference voltage. - if (allConfigs->configs[config].reference == iadcCfgReferenceInt1V2) { - // Internal reference voltage (VBGR) depends on the chip revision. - offset *= 1.25f / (IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f); - } else { - offset *= 1.25f / (allConfigs->configs[config].vRef / 1000.0f); - } - - // Compensate offset for systematic offset. - offset = (offset * 4.0f) + (640.0f * (256.0f / iOsr)); - - // Apply gain error correction. - if (scale != 0x80000000U) { - offset = (uiGainCAna / 32768.0f) * (offset + 524288.0f) - 524288.0f; - } - - iOffset = IADC_ROUND_D2I(-offset); - // We only have 18 bits available for OFFSET in SCALE register. - // OFFSET is a 2nd complement number. - if (iOffset > 131071) { // Positive overflow at 0x0001FFFF ? - scale |= 0x1FFFFU; - } else if (iOffset < -131072) { // Negative overflow at 0xFFFE0000 ? - scale |= 0x20000U; - } else { - scale |= (uint32_t)iOffset & 0x3FFFFU; - } - iadc->CFG[config].SCALE = scale; - break; - -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - case iadcCfgModeHighAccuracy: - // Get reference voltage in volts - refVoltage = IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f; - - // Get OSR from config register - osrValue = (iadc->CFG[config].CFG & _IADC_CFG_OSRHA_MASK) >> _IADC_CFG_OSRHA_SHIFT; - - // 1. Calculate gain correction - if ((uint32_t)osrHiAcc[osrValue] == 92U) { - // for OSR = 92, gainSysHiAcc = 0.957457 - gainSysHiAcc = 0.957457; - } else { - // for OSR != 92, gainSysHiAcc = OSR/(OSR + 1) - gainSysHiAcc = osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f); - } - anaGain = (float) uiGainCAna / 32768.0f * gainSysHiAcc; - anaGainRound = IADC_ROUND_D2I(32768.0f * anaGain); - IADC0->CFG[config].SCALE &= ~_IADC_SCALE_MASK; - - // Write GAIN3MSB - if ((uint32_t)anaGainRound & 0x8000) { - IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN100; - } else { - IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN011; - } - // Write GAIN13LSB - IADC0->CFG[config].SCALE |= ((uint32_t)anaGainRound & 0x1FFF) << _IADC_SCALE_GAIN13LSB_SHIFT; - - // Get offset value for high accuracy mode from DEVINFO - offsetAna1HiAccInt = (uint16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK) - >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT; - - // 2. OSR adjustment - // Get offset from DEVINFO - offsetAnaBase = (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK) - >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT; - // 1 << osrValue is the same as pow(2, osrValue) - offsetAna = offsetAnaBase + (offsetAna1HiAccInt) / (1 << osrValue); - - // 3. Reference voltage adjustment - offsetAna = (offsetAna) * (1.25f / refVoltage); - - // 4. Calculate final offset - offset2 = 262144.0f / osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f) + offsetAna * 4.0f + 524288.0f; - offset2 = (uiGainCAna / 32768.0f * (-1.0f)) * offset2 + 524288.0f; - offsetLong = IADC_ROUND_D2I(offset2); - - // 5. Write offset to scale register - IADC0->CFG[config].SCALE |= (uint32_t)(offsetLong & _IADC_SCALE_OFFSET_MASK); - break; -#endif - default: - // Mode not supported. - EFM_ASSERT(false); - break; - } - iadc->CFG[config].SCHED = ((adcClkPrescale << _IADC_SCHED_PRESCALE_SHIFT) - & _IADC_SCHED_PRESCALE_MASK); - } - IADC_enable(iadc); -} - -/***************************************************************************//** - * @brief - * Initialize IADC scan sequence. - * - * @details - * This function will configure scan mode and set up entries in the scan - * table. The scan table mask can be updated by calling IADC_updateScanMask. - * - * @note - * This function will stop any ongoing conversions. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC initialization structure. - * - * @param[in] scanTable - * Pointer to IADC scan table structure. - ******************************************************************************/ -void IADC_initScan(IADC_TypeDef *iadc, - const IADC_InitScan_t *init, - const IADC_ScanTable_t *scanTable) -{ - uint32_t i; - uint32_t tmp; - EFM_ASSERT(IADC_REF_VALID(iadc)); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. - EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); -#endif - - IADC_disable(iadc); - - iadc->SCANFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT) - & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - | (init->showId ? IADC_SCANFIFOCFG_SHOWID : 0UL) - | (((uint32_t) (init->dataValidLevel) << _IADC_SCANFIFOCFG_DVL_SHIFT) - & _IADC_SCANFIFOCFG_DVL_MASK) - | (init->fifoDmaWakeup ? IADC_SCANFIFOCFG_DMAWUFIFOSCAN : 0UL); - - // Clear bitfields for scan conversion in IADCn->TRIGGER and set new values - iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SCANTRIGSEL_MASK - | _IADC_TRIGGER_SCANTRIGACTION_MASK)) - | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SCANTRIGSEL_SHIFT) - & _IADC_TRIGGER_SCANTRIGSEL_MASK) - | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SCANTRIGACTION_SHIFT) - & _IADC_TRIGGER_SCANTRIGACTION_MASK); - - // Write scan table - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - iadc->SCANTABLE[i].SCAN = (((uint32_t) (scanTable->entries[i].negInput) << _IADC_SCAN_PINNEG_SHIFT) - & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) - | (((uint32_t) (scanTable->entries[i].posInput) << _IADC_SCAN_PINPOS_SHIFT) - & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) - | (((uint32_t) (scanTable->entries[i].configId) << _IADC_SCAN_CFG_SHIFT) - & _IADC_SCAN_CFG_MASK) - | (scanTable->entries[i].compare ? IADC_SCAN_CMP : 0UL); - } - - IADC_enable(iadc); - - // Set scan mask - tmp = 0; - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - if (scanTable->entries[i].includeInScan) { - tmp |= (1UL << i) << _IADC_MASKREQ_MASKREQ_SHIFT; - } - } - iadc->MASKREQ = tmp; - - if (init->start) { - IADC_command(iadc, iadcCmdStartScan); - } -} - -/***************************************************************************//** - * @brief - * Initialize single IADC conversion. - * - * @details - * This function will initialize the single conversion and configure the - * single input selection. - * - * @note - * This function will stop any ongoing conversions. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC single initialization structure. - * - * @param[in] input - * Pointer to IADC single input selection initialization structure. - ******************************************************************************/ -void IADC_initSingle(IADC_TypeDef *iadc, - const IADC_InitSingle_t *init, - const IADC_SingleInput_t *input) -{ - EFM_ASSERT(IADC_REF_VALID(iadc)); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. - EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); -#endif - IADC_disable(iadc); - - iadc->SINGLEFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT) - & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - | (init->showId ? IADC_SINGLEFIFOCFG_SHOWID : 0UL) - | (((uint32_t) (init->dataValidLevel) << _IADC_SINGLEFIFOCFG_DVL_SHIFT) - & _IADC_SINGLEFIFOCFG_DVL_MASK) - | (init->fifoDmaWakeup ? IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE : 0UL); - - // Clear bitfields for single conversion in IADCn->TRIGGER and set new values - iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SINGLETRIGSEL_MASK - | _IADC_TRIGGER_SINGLETRIGACTION_MASK - | _IADC_TRIGGER_SINGLETAILGATE_MASK)) - | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SINGLETRIGSEL_SHIFT) - & _IADC_TRIGGER_SINGLETRIGSEL_MASK) - | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SINGLETRIGACTION_SHIFT) - & _IADC_TRIGGER_SINGLETRIGACTION_MASK) - | (init->singleTailgate ? IADC_TRIGGER_SINGLETAILGATE : 0UL); - - IADC_updateSingleInput(iadc, input); - - IADC_enable(iadc); - - if (init->start) { - IADC_command(iadc, iadcCmdStartSingle); - } -} - -/***************************************************************************//** - * @brief - * Update IADC single input selection. - * - * @details - * This function updates the single input selection. The function can be - * called while single and/or scan conversions are ongoing and the new input - * configuration will take place on the next single conversion. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] input - * Pointer to single input selection structure. - ******************************************************************************/ -void IADC_updateSingleInput(IADC_TypeDef *iadc, - const IADC_SingleInput_t *input) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADCn->SINGLE has WSYNC type and can only be written while enabled - IADC_enable(iadc); - - iadc->SINGLE = (((uint32_t) (input->negInput) << _IADC_SINGLE_PINNEG_SHIFT) - & (_IADC_SINGLE_PORTNEG_MASK | _IADC_SINGLE_PINNEG_MASK)) - | (((uint32_t) (input->posInput) << _IADC_SINGLE_PINPOS_SHIFT) - & (_IADC_SINGLE_PORTPOS_MASK | _IADC_SINGLE_PINPOS_MASK)) - | (((uint32_t) (input->configId) << _IADC_SINGLE_CFG_SHIFT) - & _IADC_SINGLE_CFG_MASK) - | (input->compare ? IADC_SINGLE_CMP : 0UL); - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Set mask of IADC scan table entries to include in scan. - * - * @details - * Set mask of scan table entries to include in next scan. This function - * can be called while scan conversions are ongoing, but the new scan mask - * will take effect once the ongoing scan is completed. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] mask - * Mask of scan table entries to include in scan. - ******************************************************************************/ -void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - EFM_ASSERT(mask <= ((1UL << IADC_SCANENTRIES(iadc)) - 1UL)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADC must be enabled to update scan table mask - IADC_enable(iadc); - - iadc->MASKREQ = (mask << _IADC_MASKREQ_MASKREQ_SHIFT) - & _IADC_MASKREQ_MASKREQ_MASK; - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Add/update entry in scan table. - * - * @details - * This function will update or add an entry in the scan table with a specific - * ID. - * - * @note - * This function will stop any ongoing conversions. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] id - * ID of scan table entry to add. - * - * @param[in] entry - * Pointer to scan table entry structure. - ******************************************************************************/ -void IADC_updateScanEntry(IADC_TypeDef *iadc, - uint8_t id, - IADC_ScanTableEntry_t *entry) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADC must be disabled to update scan table - IADC_disable(iadc); - - // Update entry in scan table - iadc->SCANTABLE[id].SCAN = (((uint32_t) (entry->negInput) << _IADC_SCAN_PINNEG_SHIFT) - & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) - | (((uint32_t) (entry->posInput) << _IADC_SCAN_PINPOS_SHIFT) - & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) - | (((uint32_t) (entry->configId) << _IADC_SCAN_CFG_SHIFT) - & _IADC_SCAN_CFG_MASK) - | (entry->compare ? IADC_SCAN_CMP : 0UL); - - // IADC must be enabled to update scan table mask - IADC_enable(iadc); - - if (entry->includeInScan) { - iadc->MASKREQ_SET = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; - } else { - iadc->MASKREQ_CLR = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; - } - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Reset IADC to same state as after a HW reset. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - ******************************************************************************/ -void IADC_reset(IADC_TypeDef *iadc) -{ - uint32_t i; - EFM_ASSERT(IADC_REF_VALID(iadc)); - - // Write all WSYNC registers to reset value while enabled - IADC_enable(iadc); - - // Stop conversions and timer, before resetting other registers. - iadc->CMD = IADC_CMD_SINGLESTOP | IADC_CMD_SCANSTOP | IADC_CMD_TIMERDIS; - - // Wait for all IADC operations to stop - while ((iadc->STATUS & (IADC_STATUS_CONVERTING - | IADC_STATUS_SCANQUEUEPENDING - | IADC_STATUS_SINGLEQUEUEPENDING - | IADC_STATUS_TIMERACTIVE)) - != 0UL) { - } - - // Reset all WSYNC registers - iadc->MASKREQ = _IADC_MASKREQ_RESETVALUE; - iadc->SINGLE = _IADC_SINGLE_RESETVALUE; - - // Wait for SINGLE and MASQREQ writes to propagate to working registers - while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING - | IADC_STATUS_SINGLEWRITEPENDING)) - != 0UL) { - } - - // Pull from FIFOs until they are empty - - // Errata IADC_E305: Check SINGLEFIFOSTAT to make sure that SINGLEFIFO is getting emptied in case - // where STATUS register is incorrect. - while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { - (void) IADC_pullSingleFifoData(iadc); - } - - // Errata IADC_E305: check SCANFIFOSTAT to make sure that SCANFIFO is getting emptied in case - // where STATUS register is incorrect. - while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { - (void) IADC_pullScanFifoData(iadc); - } - - // Read data registers to clear data valid flags - (void) IADC_readSingleData(iadc); - (void) IADC_readScanData(iadc); - - // Write all WSTATIC registers to reset value while disabled - IADC_disable(iadc); - - // Reset all WSTATIC registers - iadc->CTRL = _IADC_CTRL_RESETVALUE; - iadc->TIMER = _IADC_TIMER_RESETVALUE; - iadc->TRIGGER = _IADC_TRIGGER_RESETVALUE; - - iadc->CMPTHR = _IADC_CMPTHR_RESETVALUE; - iadc->SINGLEFIFOCFG = _IADC_SINGLEFIFOCFG_RESETVALUE; - iadc->SCANFIFOCFG = _IADC_SCANFIFOCFG_RESETVALUE; - - for (i = 0; i < IADC_CONFIGNUM(IADC_NUM(iadc)); i++) { - iadc->CFG[i].CFG = _IADC_CFG_RESETVALUE; - iadc->CFG[i].SCALE = _IADC_SCALE_RESETVALUE; - iadc->CFG[i].SCHED = _IADC_SCHED_RESETVALUE; - } - - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - iadc->SCANTABLE[i].SCAN = _IADC_SCAN_RESETVALUE; - } - - // Clear interrupt flags and disable interrupts - IADC_clearInt(iadc, _IADC_IF_MASK); - IADC_disableInt(iadc, _IADC_IEN_MASK); -} - -/***************************************************************************//** - * @brief - * Calculate timebase value in order to get a timebase providing at least 1us. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] srcClkFreq Frequency in Hz of reference CLK_SRC_ADC clock. Set to 0 to - * derive srcClkFreq from CLK_CMU_ADC and prescaler HSCLKRATE. - * - * @return - * Timebase value to use for IADC in order to achieve at least 1 us. - ******************************************************************************/ -uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq) -{ - EFM_ASSERT(IADC_REF_VALID(iadc)); - - if (srcClkFreq == 0UL) { - // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set - // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. - srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); - - // Just in case, make sure we get non-zero frequency for below calculation - if (srcClkFreq == 0UL) { - srcClkFreq = 1; - } - // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE - if (srcClkFreq > IADC_CLK_MAX_FREQ) { - uint32_t prescaler = (uint32_t)(IADC0->CTRL & _IADC_CTRL_HSCLKRATE_MASK) >> _IADC_CTRL_HSCLKRATE_SHIFT; - srcClkFreq /= (prescaler + 1); - } - } - - // Determine number of ADCCLK cycle >= 1us - srcClkFreq += 999999UL; - srcClkFreq /= 1000000UL; - - // Convert to N+1 format - srcClkFreq -= 1UL; - - // Limit to max allowed register setting - srcClkFreq = SL_MIN(srcClkFreq, (_IADC_CTRL_TIMEBASE_MASK >> _IADC_CTRL_TIMEBASE_SHIFT)); - - // Return timebase value - return (uint8_t) srcClkFreq; -} - -/***************************************************************************//** - * @brief - * Calculate prescaler for CLK_SRC_ADC high speed clock - * - * @details - * The IADC high speed clock is given by: CLK_SRC_ADC / (srcClkPrescaler + 1). - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] srcClkFreq CLK_SRC_ADC frequency wanted. The frequency will - * automatically be adjusted to be within valid range according to reference - * manual. - * - * @param[in] cmuClkFreq Frequency in Hz of reference CLK_CMU_ADC. Set to 0 - * to use currently defined CMU clock setting for the IADC. - * - * @return - * Divider value to use for IADC in order to achieve a high speed clock value - * <= @p srcClkFreq. - ******************************************************************************/ -uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, - uint32_t srcClkFreq, - uint32_t cmuClkFreq) -{ - uint32_t ret; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - EFM_ASSERT(srcClkFreq); - - // Make sure wanted CLK_SRC_ADC clock is below max allowed frequency - srcClkFreq = SL_MIN(srcClkFreq, IADC_CLK_MAX_FREQ); - - // Use current CLK_CMU_ADC frequency? - if (cmuClkFreq == 0UL) { - cmuClkFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); - } - - ret = (cmuClkFreq + srcClkFreq - 1UL) / srcClkFreq; - if (ret != 0UL) { - ret--; - } - - // Limit to max allowed register setting - if (ret > _IADC_CTRL_HSCLKRATE_DIV4) { - ret = _IADC_CTRL_HSCLKRATE_DIV4; - } - - return (uint8_t)ret; -} - -/***************************************************************************//** - * @brief - * Calculate prescaler for ADC_CLK clock. - * - * @details - * The ADC_CLK is given by: CLK_SRC_ADC / (adcClkprescale + 1). - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] adcClkFreq ADC_CLK frequency wanted. The frequency will - * automatically be adjusted to be within valid range according to reference - * manual. - * - * @param[in] cmuClkFreq Frequency in Hz of CLK_CMU_ADC Set to 0 to - * use currently defined IADC clock setting (in CMU). - * - * @param[in] adcMode Mode for IADC config. - * - * @param[in] srcClkPrescaler Precaler setting for ADC_CLK - * - * @return - * Divider value to use for IADC in order to achieve a ADC_CLK frequency - * <= @p adcClkFreq. - ******************************************************************************/ -uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, - uint32_t adcClkFreq, - uint32_t cmuClkFreq, - IADC_CfgAdcMode_t adcMode, - uint8_t srcClkPrescaler) -{ - uint32_t ret; - uint32_t resFreq; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - EFM_ASSERT(adcClkFreq); - - // Make sure wanted analog clock is below max allowed frequency for the given - // mode. - if (adcClkFreq > IADC_ANA_CLK_MAX_FREQ(adcMode)) { - adcClkFreq = IADC_ANA_CLK_MAX_FREQ(adcMode); - } - - // Use current CLK_CMU_ADC frequency? - if (cmuClkFreq == 0UL) { - resFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); - } else { - resFreq = cmuClkFreq; - } - - // Apply CLK_SRC_ADC prescaler - resFreq /= srcClkPrescaler + 1UL; - - ret = (resFreq + adcClkFreq - 1UL) / adcClkFreq; - if (ret != 0UL) { - ret--; - } - - // Limit to max allowed register setting - ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); - - return (uint16_t)ret; -} - -/***************************************************************************//** - * @brief - * Pull result from single data FIFO. The result struct includes both the data - * and the ID (0x20) if showId was set when initializing single mode. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SINGLEFIFODATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Read most recent single conversion result. The result struct includes both - * the data and the ID (0x20) if showId was set when initializing single mode. - * Calling this function will not affect the state of the single data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SINGLEDATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Pull result from scan data FIFO. The result struct includes both the data - * and the ID (0x20) if showId was set when initializing scan entry. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SCANFIFODATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Read most recent scan conversion result. The result struct includes both - * the data and the ID (0x20) if showId was set when initializing scan entry. - * Calling this function will not affect the state of the scan data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SCANDATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Get reference voltage selection. - * - * @param[in] reference - * IADC Reference selection. - * - * @return - * IADC reference voltage in millivolts. - ******************************************************************************/ -uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference) -{ - uint32_t refVoltage = 0; - // Get chip revision - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - switch (reference) { - case iadcCfgReferenceInt1V2: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (chipRev.major == 1UL) { - refVoltage = 1210; - } else { - refVoltage = 1180; - } -#else - refVoltage = 1210; -#endif - break; - case iadcCfgReferenceExt1V25: - refVoltage = 1250; - break; -#if defined(_IADC_CFG_REFSEL_VREF2P5) - case iadcCfgReferenceExt2V5: - refVoltage = 2500; - break; -#endif - case iadcCfgReferenceVddx: - refVoltage = 3000; - break; - case iadcCfgReferenceVddX0P8Buf: - refVoltage = 2400; - break; -#if defined(_IADC_CFG_REFSEL_VREFBUF) - case iadcCfgReferenceBuf: - refVoltage = 12500; - break; -#endif -#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) - case iadcCfgReference0P8Buf: - refVoltage = 1000; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - - return refVoltage; -} - -/** @} (end addtogroup iadc) */ -/** @} (end addtogroup emlib) */ -#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_iadc.h" + +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup iadc IADC - Incremental ADC + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + * @details + * This module contains functions to control the IADC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The IADC is used to convert analog signals into a + * digital representation. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +// Validation of IADC register block pointer reference for assert statements. +#if defined(IADC_NUM) +#define IADC_REF_VALID(ref) (IADC_NUM(ref) != -1) +#else +#if (IADC_COUNT == 1) +#define IADC_REF_VALID(ref) ((ref) == IADC0) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : -1) +#elif (IADC_COUNT == 2) +#define IADC_REF_VALID(ref) (((ref) == IADC0) || ((ref) == IADC1)) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : ((ref) == IADC1) ? 1 : -1) +#endif +#endif + +// Max IADC clock rates +#define IADC_CLK_MAX_FREQ 40000000UL +#define IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ 20000000UL +#define IADC_ANA_CLK_NORMAL_MAX_FREQ 10000000UL +#define IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ 5000000UL +#if defined (_IADC_CFG_ADCMODE_HIGHSPEED) +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : ((adcMode) == iadcCfgModeHighSpeed \ + ? IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ) \ + ) +#else +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ \ + ) +#endif + +#define IADC_ROUND_D2I(n) (int)((n) < 0.0f ? ((n) - 0.5f) : ((n) + 0.5f)) + +#define IADC0_SCANENTRIES IADC0_ENTRIES +#define IADC0_FIFOENTRIES 0x4UL + +#define IADC1_SCANENTRIES IADC1_ENTRIES +#define IADC1_FIFOENTRIES 0x4UL + +#if defined(IADC_ENTRIES) +#define IADC_SCANENTRIES(iadc) IADC_ENTRIES(IADC_NUM(iadc)) +#else +#define IADC_SCANENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_SCANENTRIES \ + : 0UL) +#endif + +#if !defined(IADC_CONFIGNUM) +#define IADC_CONFIGNUM(iadc) ( \ + (iadc) == 0 ? IADC0_CONFIGNUM \ + : 0UL) +#endif + +#define IADC_FIFOENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_FIFOENTRIES \ + : 0UL) + +#define IADC_CMU_CLOCK(iadc) ( \ + (iadc) == IADC0 ? cmuClock_IADC0 \ + : cmuClock_IADC0) + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +static void IADC_disable(IADC_TypeDef *iadc) +{ +#if defined(IADC_STATUS_SYNCBUSY) + while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { + // Wait for synchronization to finish before disable + } +#endif + iadc->EN_CLR = IADC_EN_EN; +#if defined(_IADC_EN_DISABLING_MASK) + while (IADC0->EN & _IADC_EN_DISABLING_MASK) { + } +#endif +} + +static void IADC_enable(IADC_TypeDef *iadc) +{ + iadc->EN_SET = IADC_EN_EN; +} + +static IADC_Result_t IADC_ConvertRawDataToResult(uint32_t rawData, + IADC_Alignment_t alignment) +{ + IADC_Result_t result; + + switch (alignment) { + case iadcAlignRight12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignRight16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignRight20: +#endif + // Mask out ID and replace with sign extension + result.data = (rawData & 0x00FFFFFFUL) + | ((rawData & 0x00800000UL) != 0x0UL ? 0xFF000000UL : 0x0UL); + // Mask out data and shift down + result.id = (uint8_t)((rawData & 0xFF000000UL) >> 24); + break; + + case iadcAlignLeft12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignLeft16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignLeft20: +#endif + result.data = rawData & 0xFFFFFF00UL; + result.id = (uint8_t)(rawData & 0x000000FFUL); + break; + default: + break; + } + return result; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize IADC. + * + * @details + * Initializes common parts for both single conversion and scan sequence. + * In addition, single and/or scan control configuration must be done, please + * refer to @ref IADC_initSingle() and @ref IADC_initScan() respectively. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] allConfigs + * Pointer to structure holding all configs. + ******************************************************************************/ +void IADC_init(IADC_TypeDef *iadc, + const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs) +{ + uint32_t tmp; + uint32_t config; + uint16_t wantedPrescale; + uint8_t srcClkPrescale; + uint32_t adcClkPrescale; + uint8_t timebase; + unsigned uiAnaGain; + uint16_t uiGainCAna; + IADC_CfgAdcMode_t adcMode; +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + float anaGain; + int anaGainRound; + float offsetAna; + float offset2; + int offsetLong; + int offsetAna1HiAccInt; + uint8_t osrValue; + float offsetAnaBase; + float gainSysHiAcc; + float refVoltage = 0; + // Over sampling ratio for high accuracy conversions + const float osrHiAcc[6] = { 16.0, 32.0, 64.0, 92.0, 128.0, 256.0 }; +#endif + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Calculate min allowed SRC_CLK prescaler setting + srcClkPrescale = IADC_calcSrcClkPrescale(iadc, IADC_CLK_MAX_FREQ, 0); + + wantedPrescale = init->srcClkPrescale; + // Use wanted SRC_CLK prescaler setting instead if it is high enough + if (wantedPrescale >= srcClkPrescale) { + srcClkPrescale = wantedPrescale; + } + + IADC_disable(iadc); + + timebase = init->timebase; + if (timebase == 0) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + uint32_t srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE to obtain valid frequency + if (srcClkFreq >= IADC_CLK_MAX_FREQ) { + srcClkFreq = srcClkFreq / srcClkPrescale; + } + // Calculate timebase based on CMU_IADCCLKCTRL + timebase = IADC_calcTimebase(iadc, srcClkFreq); + } + + tmp = (((uint32_t)(init->warmup) << _IADC_CTRL_WARMUPMODE_SHIFT) + & _IADC_CTRL_WARMUPMODE_MASK) + | (((uint32_t)(timebase) << _IADC_CTRL_TIMEBASE_SHIFT) + & _IADC_CTRL_TIMEBASE_MASK) + | (((uint32_t)(srcClkPrescale) << _IADC_CTRL_HSCLKRATE_SHIFT) + & _IADC_CTRL_HSCLKRATE_MASK); + + if (init->iadcClkSuspend0) { + tmp |= IADC_CTRL_ADCCLKSUSPEND0; + } + if (init->iadcClkSuspend1) { + tmp |= IADC_CTRL_ADCCLKSUSPEND1; + } + if (init->debugHalt) { + tmp |= IADC_CTRL_DBGHALT; + } + iadc->CTRL = tmp; + + iadc->TIMER = ((uint32_t) (init->timerCycles) << _IADC_TIMER_TIMER_SHIFT) + & _IADC_TIMER_TIMER_MASK; + + iadc->CMPTHR = (((uint32_t) (init->greaterThanEqualThres) << _IADC_CMPTHR_ADGT_SHIFT) + & _IADC_CMPTHR_ADGT_MASK) + | (((uint32_t) (init->lessThanEqualThres) << _IADC_CMPTHR_ADLT_SHIFT) + & _IADC_CMPTHR_ADLT_MASK); + + // Write configurations + for (config = 0; config < IADC_CONFIGNUM(IADC_NUM(iadc)); config++) { + // Find min allowed ADC_CLK prescaler setting for given mode + adcMode = allConfigs->configs[config].adcMode; + wantedPrescale = allConfigs->configs[config].adcClkPrescale; + adcClkPrescale = IADC_calcAdcClkPrescale(iadc, + IADC_ANA_CLK_MAX_FREQ(adcMode), + 0, + adcMode, + srcClkPrescale); + + // Use wanted ADC_CLK prescaler setting instead if it is high enough + adcClkPrescale = SL_MAX(adcClkPrescale, wantedPrescale); + + tmp = iadc->CFG[config].CFG & ~(_IADC_CFG_ADCMODE_MASK | _IADC_CFG_OSRHS_MASK + | _IADC_CFG_ANALOGGAIN_MASK | _IADC_CFG_REFSEL_MASK +#if defined(_IADC_CFG_DIGAVG_MASK) + | _IADC_CFG_DIGAVG_MASK +#endif + | _IADC_CFG_TWOSCOMPL_MASK +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | _IADC_CFG_OSRHA_MASK +#endif + ); + iadc->CFG[config].CFG = tmp + | (((uint32_t)(adcMode) << _IADC_CFG_ADCMODE_SHIFT) & _IADC_CFG_ADCMODE_MASK) + | (((uint32_t)(allConfigs->configs[config].osrHighSpeed) << _IADC_CFG_OSRHS_SHIFT) + & _IADC_CFG_OSRHS_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | (((uint32_t)(allConfigs->configs[config].osrHighAccuracy) << _IADC_CFG_OSRHA_SHIFT) + & _IADC_CFG_OSRHA_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].analogGain) << _IADC_CFG_ANALOGGAIN_SHIFT) + & _IADC_CFG_ANALOGGAIN_MASK) + | (((uint32_t)(allConfigs->configs[config].reference) << _IADC_CFG_REFSEL_SHIFT) + & _IADC_CFG_REFSEL_MASK) +#if defined(_IADC_CFG_DIGAVG_MASK) + | (((uint32_t)(allConfigs->configs[config].digAvg) << _IADC_CFG_DIGAVG_SHIFT) + & _IADC_CFG_DIGAVG_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].twosComplement) << _IADC_CFG_TWOSCOMPL_SHIFT) + & _IADC_CFG_TWOSCOMPL_MASK); + + uiAnaGain = (iadc->CFG[config].CFG & _IADC_CFG_ANALOGGAIN_MASK) >> _IADC_CFG_ANALOGGAIN_SHIFT; + switch (uiAnaGain) { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + case iadcCfgAnalogGain0P25x: // 0.25x +#endif + case iadcCfgAnalogGain0P5x: // 0.5x + case iadcCfgAnalogGain1x: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + case iadcCfgAnalogGain2x: // 2x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA2_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT); + break; + case iadcCfgAnalogGain3x: // 3x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA3_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT); + break; + case iadcCfgAnalogGain4x: // 4x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA4_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT); + break; + default: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + } + + // Gain and offset correction is applied according to adcMode and oversampling rate. + switch (adcMode) { + float offset; + uint32_t scale; + int iOffset, iOsr; + case iadcCfgModeNormal: +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + case iadcCfgModeHighSpeed: +#endif + offset = 0.0f; + if (uiAnaGain == iadcCfgAnalogGain2x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT); + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT); + } + } else if (uiAnaGain == iadcCfgAnalogGain3x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 2; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 2; + } + } else if (uiAnaGain == iadcCfgAnalogGain4x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 3; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 3; + } + } + + // Set correct gain correction bitfields in scale variable. + tmp = (uint32_t)uiGainCAna & 0x9FFFU; + scale = tmp << _IADC_SCALE_GAIN13LSB_SHIFT; + if ((tmp & 0x8000U) != 0U) { + scale |= IADC_SCALE_GAIN3MSB; + } + + // Adjust offset according to selected OSR. + iOsr = 1U << (((iadc->CFG[config].CFG & _IADC_CFG_OSRHS_MASK) >> _IADC_CFG_OSRHS_SHIFT) + 1U); + if (iOsr == 2) { + if (adcMode == iadcCfgModeNormal) { + offset += (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 & _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK); + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 & _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK); + } + } else { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL1 & _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK) - offset; + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL1 & _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK) - offset; + } + offset /= iOsr / 2.0f; + offset += (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK); + } + + // Compensate offset according to selected reference voltage. + if (allConfigs->configs[config].reference == iadcCfgReferenceInt1V2) { + // Internal reference voltage (VBGR) depends on the chip revision. + offset *= 1.25f / (IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f); + } else { + offset *= 1.25f / (allConfigs->configs[config].vRef / 1000.0f); + } + + // Compensate offset for systematic offset. + offset = (offset * 4.0f) + (640.0f * (256.0f / iOsr)); + + // Apply gain error correction. + if (scale != 0x80000000U) { + offset = (uiGainCAna / 32768.0f) * (offset + 524288.0f) - 524288.0f; + } + + iOffset = IADC_ROUND_D2I(-offset); + // We only have 18 bits available for OFFSET in SCALE register. + // OFFSET is a 2nd complement number. + if (iOffset > 131071) { // Positive overflow at 0x0001FFFF ? + scale |= 0x1FFFFU; + } else if (iOffset < -131072) { // Negative overflow at 0xFFFE0000 ? + scale |= 0x20000U; + } else { + scale |= (uint32_t)iOffset & 0x3FFFFU; + } + iadc->CFG[config].SCALE = scale; + break; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + case iadcCfgModeHighAccuracy: + // Get reference voltage in volts + refVoltage = IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f; + + // Get OSR from config register + osrValue = (iadc->CFG[config].CFG & _IADC_CFG_OSRHA_MASK) >> _IADC_CFG_OSRHA_SHIFT; + + // 1. Calculate gain correction + if ((uint32_t)osrHiAcc[osrValue] == 92U) { + // for OSR = 92, gainSysHiAcc = 0.957457 + gainSysHiAcc = 0.957457; + } else { + // for OSR != 92, gainSysHiAcc = OSR/(OSR + 1) + gainSysHiAcc = osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f); + } + anaGain = (float) uiGainCAna / 32768.0f * gainSysHiAcc; + anaGainRound = IADC_ROUND_D2I(32768.0f * anaGain); + IADC0->CFG[config].SCALE &= ~_IADC_SCALE_MASK; + + // Write GAIN3MSB + if ((uint32_t)anaGainRound & 0x8000) { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN100; + } else { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN011; + } + // Write GAIN13LSB + IADC0->CFG[config].SCALE |= ((uint32_t)anaGainRound & 0x1FFF) << _IADC_SCALE_GAIN13LSB_SHIFT; + + // Get offset value for high accuracy mode from DEVINFO + offsetAna1HiAccInt = (uint16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT; + + // 2. OSR adjustment + // Get offset from DEVINFO + offsetAnaBase = (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT; + // 1 << osrValue is the same as pow(2, osrValue) + offsetAna = offsetAnaBase + (offsetAna1HiAccInt) / (1 << osrValue); + + // 3. Reference voltage adjustment + offsetAna = (offsetAna) * (1.25f / refVoltage); + + // 4. Calculate final offset + offset2 = 262144.0f / osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f) + offsetAna * 4.0f + 524288.0f; + offset2 = (uiGainCAna / 32768.0f * (-1.0f)) * offset2 + 524288.0f; + offsetLong = IADC_ROUND_D2I(offset2); + + // 5. Write offset to scale register + IADC0->CFG[config].SCALE |= (uint32_t)(offsetLong & _IADC_SCALE_OFFSET_MASK); + break; +#endif + default: + // Mode not supported. + EFM_ASSERT(false); + break; + } + iadc->CFG[config].SCHED = ((adcClkPrescale << _IADC_SCHED_PRESCALE_SHIFT) + & _IADC_SCHED_PRESCALE_MASK); + } + IADC_enable(iadc); +} + +/***************************************************************************//** + * @brief + * Initialize IADC scan sequence. + * + * @details + * This function will configure scan mode and set up entries in the scan + * table. The scan table mask can be updated by calling IADC_updateScanMask. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] scanTable + * Pointer to IADC scan table structure. + ******************************************************************************/ +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable) +{ + uint32_t i; + uint32_t tmp; + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + + IADC_disable(iadc); + + iadc->SCANFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SCANFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SCANFIFOCFG_DVL_SHIFT) + & _IADC_SCANFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SCANFIFOCFG_DMAWUFIFOSCAN : 0UL); + + // Clear bitfields for scan conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SCANTRIGSEL_MASK + | _IADC_TRIGGER_SCANTRIGACTION_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SCANTRIGSEL_SHIFT) + & _IADC_TRIGGER_SCANTRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SCANTRIGACTION_SHIFT) + & _IADC_TRIGGER_SCANTRIGACTION_MASK); + + // Write scan table + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = (((uint32_t) (scanTable->entries[i].negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (scanTable->entries[i].posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (scanTable->entries[i].configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (scanTable->entries[i].compare ? IADC_SCAN_CMP : 0UL); + } + + IADC_enable(iadc); + + // Set scan mask + tmp = 0; + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + if (scanTable->entries[i].includeInScan) { + tmp |= (1UL << i) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + } + iadc->MASKREQ = tmp; + + if (init->start) { + IADC_command(iadc, iadcCmdStartScan); + } +} + +/***************************************************************************//** + * @brief + * Initialize single IADC conversion. + * + * @details + * This function will initialize the single conversion and configure the + * single input selection. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC single initialization structure. + * + * @param[in] input + * Pointer to IADC single input selection initialization structure. + ******************************************************************************/ +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + IADC_disable(iadc); + + iadc->SINGLEFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SINGLEFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SINGLEFIFOCFG_DVL_SHIFT) + & _IADC_SINGLEFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE : 0UL); + + // Clear bitfields for single conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SINGLETRIGSEL_MASK + | _IADC_TRIGGER_SINGLETRIGACTION_MASK + | _IADC_TRIGGER_SINGLETAILGATE_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SINGLETRIGSEL_SHIFT) + & _IADC_TRIGGER_SINGLETRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SINGLETRIGACTION_SHIFT) + & _IADC_TRIGGER_SINGLETRIGACTION_MASK) + | (init->singleTailgate ? IADC_TRIGGER_SINGLETAILGATE : 0UL); + + IADC_updateSingleInput(iadc, input); + + IADC_enable(iadc); + + if (init->start) { + IADC_command(iadc, iadcCmdStartSingle); + } +} + +/***************************************************************************//** + * @brief + * Update IADC single input selection. + * + * @details + * This function updates the single input selection. The function can be + * called while single and/or scan conversions are ongoing and the new input + * configuration will take place on the next single conversion. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] input + * Pointer to single input selection structure. + ******************************************************************************/ +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADCn->SINGLE has WSYNC type and can only be written while enabled + IADC_enable(iadc); + + iadc->SINGLE = (((uint32_t) (input->negInput) << _IADC_SINGLE_PINNEG_SHIFT) + & (_IADC_SINGLE_PORTNEG_MASK | _IADC_SINGLE_PINNEG_MASK)) + | (((uint32_t) (input->posInput) << _IADC_SINGLE_PINPOS_SHIFT) + & (_IADC_SINGLE_PORTPOS_MASK | _IADC_SINGLE_PINPOS_MASK)) + | (((uint32_t) (input->configId) << _IADC_SINGLE_CFG_SHIFT) + & _IADC_SINGLE_CFG_MASK) + | (input->compare ? IADC_SINGLE_CMP : 0UL); + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Set mask of IADC scan table entries to include in scan. + * + * @details + * Set mask of scan table entries to include in next scan. This function + * can be called while scan conversions are ongoing, but the new scan mask + * will take effect once the ongoing scan is completed. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] mask + * Mask of scan table entries to include in scan. + ******************************************************************************/ +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + EFM_ASSERT(mask <= ((1UL << IADC_SCANENTRIES(iadc)) - 1UL)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + iadc->MASKREQ = (mask << _IADC_MASKREQ_MASKREQ_SHIFT) + & _IADC_MASKREQ_MASKREQ_MASK; + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Add/update entry in scan table. + * + * @details + * This function will update or add an entry in the scan table with a specific + * ID. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] id + * ID of scan table entry to add. + * + * @param[in] entry + * Pointer to scan table entry structure. + ******************************************************************************/ +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be disabled to update scan table + IADC_disable(iadc); + + // Update entry in scan table + iadc->SCANTABLE[id].SCAN = (((uint32_t) (entry->negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (entry->posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (entry->configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (entry->compare ? IADC_SCAN_CMP : 0UL); + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + if (entry->includeInScan) { + iadc->MASKREQ_SET = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } else { + iadc->MASKREQ_CLR = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Reset IADC to same state as after a HW reset. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + ******************************************************************************/ +void IADC_reset(IADC_TypeDef *iadc) +{ + uint32_t i; + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Write all WSYNC registers to reset value while enabled + IADC_enable(iadc); + + // Stop conversions and timer, before resetting other registers. + iadc->CMD = IADC_CMD_SINGLESTOP | IADC_CMD_SCANSTOP | IADC_CMD_TIMERDIS; + + // Wait for all IADC operations to stop + while ((iadc->STATUS & (IADC_STATUS_CONVERTING + | IADC_STATUS_SCANQUEUEPENDING + | IADC_STATUS_SINGLEQUEUEPENDING + | IADC_STATUS_TIMERACTIVE)) + != 0UL) { + } + + // Reset all WSYNC registers + iadc->MASKREQ = _IADC_MASKREQ_RESETVALUE; + iadc->SINGLE = _IADC_SINGLE_RESETVALUE; + + // Wait for SINGLE and MASQREQ writes to propagate to working registers + while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING + | IADC_STATUS_SINGLEWRITEPENDING)) + != 0UL) { + } + + // Pull from FIFOs until they are empty + + // Errata IADC_E305: Check SINGLEFIFOSTAT to make sure that SINGLEFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { + (void) IADC_pullSingleFifoData(iadc); + } + + // Errata IADC_E305: check SCANFIFOSTAT to make sure that SCANFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { + (void) IADC_pullScanFifoData(iadc); + } + + // Read data registers to clear data valid flags + (void) IADC_readSingleData(iadc); + (void) IADC_readScanData(iadc); + + // Write all WSTATIC registers to reset value while disabled + IADC_disable(iadc); + + // Reset all WSTATIC registers + iadc->CTRL = _IADC_CTRL_RESETVALUE; + iadc->TIMER = _IADC_TIMER_RESETVALUE; + iadc->TRIGGER = _IADC_TRIGGER_RESETVALUE; + + iadc->CMPTHR = _IADC_CMPTHR_RESETVALUE; + iadc->SINGLEFIFOCFG = _IADC_SINGLEFIFOCFG_RESETVALUE; + iadc->SCANFIFOCFG = _IADC_SCANFIFOCFG_RESETVALUE; + + for (i = 0; i < IADC_CONFIGNUM(IADC_NUM(iadc)); i++) { + iadc->CFG[i].CFG = _IADC_CFG_RESETVALUE; + iadc->CFG[i].SCALE = _IADC_SCALE_RESETVALUE; + iadc->CFG[i].SCHED = _IADC_SCHED_RESETVALUE; + } + + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = _IADC_SCAN_RESETVALUE; + } + + // Clear interrupt flags and disable interrupts + IADC_clearInt(iadc, _IADC_IF_MASK); + IADC_disableInt(iadc, _IADC_IEN_MASK); +} + +/***************************************************************************//** + * @brief + * Calculate timebase value in order to get a timebase providing at least 1us. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq Frequency in Hz of reference CLK_SRC_ADC clock. Set to 0 to + * derive srcClkFreq from CLK_CMU_ADC and prescaler HSCLKRATE. + * + * @return + * Timebase value to use for IADC in order to achieve at least 1 us. + ******************************************************************************/ +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); + + if (srcClkFreq == 0UL) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + + // Just in case, make sure we get non-zero frequency for below calculation + if (srcClkFreq == 0UL) { + srcClkFreq = 1; + } + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE + if (srcClkFreq > IADC_CLK_MAX_FREQ) { + uint32_t prescaler = (uint32_t)(IADC0->CTRL & _IADC_CTRL_HSCLKRATE_MASK) >> _IADC_CTRL_HSCLKRATE_SHIFT; + srcClkFreq /= (prescaler + 1); + } + } + + // Determine number of ADCCLK cycle >= 1us + srcClkFreq += 999999UL; + srcClkFreq /= 1000000UL; + + // Convert to N+1 format + srcClkFreq -= 1UL; + + // Limit to max allowed register setting + srcClkFreq = SL_MIN(srcClkFreq, (_IADC_CTRL_TIMEBASE_MASK >> _IADC_CTRL_TIMEBASE_SHIFT)); + + // Return timebase value + return (uint8_t) srcClkFreq; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for CLK_SRC_ADC high speed clock + * + * @details + * The IADC high speed clock is given by: CLK_SRC_ADC / (srcClkPrescaler + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq CLK_SRC_ADC frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of reference CLK_CMU_ADC. Set to 0 + * to use currently defined CMU clock setting for the IADC. + * + * @return + * Divider value to use for IADC in order to achieve a high speed clock value + * <= @p srcClkFreq. + ******************************************************************************/ +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq) +{ + uint32_t ret; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(srcClkFreq); + + // Make sure wanted CLK_SRC_ADC clock is below max allowed frequency + srcClkFreq = SL_MIN(srcClkFreq, IADC_CLK_MAX_FREQ); + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + cmuClkFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } + + ret = (cmuClkFreq + srcClkFreq - 1UL) / srcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + if (ret > _IADC_CTRL_HSCLKRATE_DIV4) { + ret = _IADC_CTRL_HSCLKRATE_DIV4; + } + + return (uint8_t)ret; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for ADC_CLK clock. + * + * @details + * The ADC_CLK is given by: CLK_SRC_ADC / (adcClkprescale + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] adcClkFreq ADC_CLK frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of CLK_CMU_ADC Set to 0 to + * use currently defined IADC clock setting (in CMU). + * + * @param[in] adcMode Mode for IADC config. + * + * @param[in] srcClkPrescaler Precaler setting for ADC_CLK + * + * @return + * Divider value to use for IADC in order to achieve a ADC_CLK frequency + * <= @p adcClkFreq. + ******************************************************************************/ +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler) +{ + uint32_t ret; + uint32_t resFreq; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(adcClkFreq); + + // Make sure wanted analog clock is below max allowed frequency for the given + // mode. + if (adcClkFreq > IADC_ANA_CLK_MAX_FREQ(adcMode)) { + adcClkFreq = IADC_ANA_CLK_MAX_FREQ(adcMode); + } + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + resFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } else { + resFreq = cmuClkFreq; + } + + // Apply CLK_SRC_ADC prescaler + resFreq /= srcClkPrescaler + 1UL; + + ret = (resFreq + adcClkFreq - 1UL) / adcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); + + return (uint16_t)ret; +} + +/***************************************************************************//** + * @brief + * Pull result from single data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing single mode. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing single mode. + * Calling this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Pull result from scan data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Get reference voltage selection. + * + * @param[in] reference + * IADC Reference selection. + * + * @return + * IADC reference voltage in millivolts. + ******************************************************************************/ +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference) +{ + uint32_t refVoltage = 0; + // Get chip revision + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + switch (reference) { + case iadcCfgReferenceInt1V2: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (chipRev.major == 1UL) { + refVoltage = 1210; + } else { + refVoltage = 1180; + } +#else + refVoltage = 1210; +#endif + break; + case iadcCfgReferenceExt1V25: + refVoltage = 1250; + break; +#if defined(_IADC_CFG_REFSEL_VREF2P5) + case iadcCfgReferenceExt2V5: + refVoltage = 2500; + break; +#endif + case iadcCfgReferenceVddx: + refVoltage = 3000; + break; + case iadcCfgReferenceVddX0P8Buf: + refVoltage = 2400; + break; +#if defined(_IADC_CFG_REFSEL_VREFBUF) + case iadcCfgReferenceBuf: + refVoltage = 12500; + break; +#endif +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + case iadcCfgReference0P8Buf: + refVoltage = 1000; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + return refVoltage; +} + +/** @} (end addtogroup iadc) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c index 2754046..d19c76a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c @@ -1,498 +1,498 @@ -/***************************************************************************//** - * @file - * @brief Direct memory access (LDMA) module peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_ldma.h" - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "em_cmu.h" -#include "em_core.h" - -/***************************************************************************//** - * @addtogroup ldma - * @{ - ******************************************************************************/ - -#if defined(LDMA_IRQ_HANDLER_TEMPLATE) -/***************************************************************************//** - * @brief - * A template for an LDMA IRQ handler. - ******************************************************************************/ -void LDMA_IRQHandler(void) -{ - uint32_t ch; - /* Get all pending and enabled interrupts. */ - uint32_t pending = LDMA_IntGetEnabled(); - - /* Loop on an LDMA error to enable debugging. */ - while (pending & LDMA_IF_ERROR) { - } - - /* Iterate over all LDMA channels. */ - for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { - uint32_t mask = 0x1 << ch; - if (pending & mask) { - /* Clear the interrupt flag. */ - LDMA->IFC = mask; - - /* Perform more actions here, execute callbacks, and so on. */ - } - } -} -#endif - -/***************************************************************************//** - * @brief - * De-initialize the LDMA controller. - * - * LDMA interrupts are disabled and the LDMA clock is stopped. - ******************************************************************************/ -void LDMA_DeInit(void) -{ - NVIC_DisableIRQ(LDMA_IRQn); - LDMA->IEN = 0; -#if defined(_LDMA_CHDIS_MASK) - LDMA->CHDIS = _LDMA_CHEN_MASK; -#else - LDMA->CHEN = 0; -#endif -#if defined(LDMA_EN_EN) - LDMA->EN = 0; -#if defined(LDMA_EN_DISABLING) - while (LDMA->EN & _LDMA_EN_DISABLING_MASK) { - } -#endif -#endif - - CMU_ClockEnable(cmuClock_LDMA, false); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - CMU_ClockEnable(cmuClock_LDMAXBAR, false); -#endif -} - -/***************************************************************************//** - * @brief - * Enable or disable an LDMA channel request. - * - * @details - * Use this function to enable or disable an LDMA channel request. This will - * prevent the LDMA from proceeding after its current transaction if disabled. - * - * @param[in] ch - * LDMA channel to enable or disable requests. - * - * @param[in] enable - * If 'true', the request will be enabled. If 'false', the request will be disabled. - ******************************************************************************/ -void LDMA_EnableChannelRequest(int ch, bool enable) -{ - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - - BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); -} - -/***************************************************************************//** - * @brief - * Initialize the LDMA controller. - * - * @details - * This function will disable all the LDMA channels and enable the LDMA bus - * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC - * and set the LDMA IRQ priority to a user-configurable priority. The LDMA - * interrupt priority is configured using the @ref LDMA_Init_t structure. - * - * @note - * Since this function enables the LDMA IRQ, always add a custom - * LDMA_IRQHandler to the application to handle any interrupts - * from LDMA. - * - * @param[in] init - * A pointer to the initialization structure used to configure the LDMA. - ******************************************************************************/ -void LDMA_Init(const LDMA_Init_t *init) -{ - uint32_t ldmaCtrlVal; - EFM_ASSERT(init != NULL); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) - & ~_LDMA_CTRL_NUMFIXED_MASK)); - -#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - -#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#endif - - EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); - - CMU_ClockEnable(cmuClock_LDMA, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - CMU_ClockEnable(cmuClock_LDMAXBAR, true); -#endif - -#if defined(LDMA_EN_EN) - LDMA->EN = LDMA_EN_EN; -#endif - - ldmaCtrlVal = (uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; - -#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); -#endif - - LDMA->CTRL = ldmaCtrlVal; - -#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - LDMA->SYNCHWEN = ((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); -#endif - -#if defined(_LDMA_CHDIS_MASK) - LDMA->CHDIS = _LDMA_CHEN_MASK; -#else - LDMA->CHEN = 0; -#endif - LDMA->DBGHALT = 0; - LDMA->REQDIS = 0; - - /* Enable the LDMA error interrupt. */ - LDMA->IEN = LDMA_IEN_ERROR; -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = 0xFFFFFFFFU; -#else - LDMA->IFC = 0xFFFFFFFFU; -#endif - NVIC_ClearPendingIRQ(LDMA_IRQn); - - /* Range is 0-7, where 0 is the highest priority. */ - NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); - - NVIC_EnableIRQ(LDMA_IRQn); -} - -/***************************************************************************//** - * @brief - * Start a DMA transfer. - * - * @param[in] ch - * A DMA channel. - * - * @param[in] transfer - * The initialization structure used to configure the transfer. - * - * @param[in] descriptor - * The transfer descriptor, which can be an array of descriptors linked together. - * Each descriptor's fields stored in RAM will be loaded into the certain - * hardware registers at the proper time to perform the DMA transfer. - ******************************************************************************/ -void LDMA_StartTransfer(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_Descriptor_t *descriptor) -{ -#if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - uint32_t tmp; -#endif - CORE_DECLARE_IRQ_STATE; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - EFM_ASSERT(transfer != NULL); - -#if defined (_LDMAXBAR_CH_REQSEL_MASK) - EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); -#elif defined (_LDMA_CH_REQSEL_MASK) - EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); -#endif - -#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) - & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) - & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) - & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) - & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); - - /* Clear the pending channel interrupt. */ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chMask; -#else - LDMA->IFC = chMask; -#endif - -#if defined(LDMAXBAR) - LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; -#else - LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; -#endif - LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; - LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) - | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) - | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) - | (transfer->ldmaCfgStructBusPort << _LDMA_CH_CFG_STRUCTBUSPORT_SHIFT) - | (transfer->ldmaCfgSrcBusPort << _LDMA_CH_CFG_SRCBUSPORT_SHIFT) - | (transfer->ldmaCfgDstBusPort << _LDMA_CH_CFG_DSTBUSPORT_SHIFT) -#endif - ; - - /* Set the descriptor address. */ - LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; - - /* A critical region. */ - CORE_ENTER_ATOMIC(); - - /* Enable the channel interrupt. */ - LDMA->IEN |= chMask; - - if (transfer->ldmaReqDis) { - LDMA->REQDIS |= chMask; - } - - if (transfer->ldmaDbgHalt) { - LDMA->DBGHALT |= chMask; - } - -#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - - LDMA->SYNCHWEN_CLR = - (((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - & _LDMA_SYNCHWEN_MASK; - - LDMA->SYNCHWEN_SET = - (((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - & _LDMA_SYNCHWEN_MASK; - -#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - - tmp = LDMA->CTRL; - - if (transfer->ldmaCtrlSyncPrsClrOff) { - tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK - | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); - } - - if (transfer->ldmaCtrlSyncPrsClrOn) { - tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; - } - - if (transfer->ldmaCtrlSyncPrsSetOff) { - tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK - | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); - } - - if (transfer->ldmaCtrlSyncPrsSetOn) { - tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; - } - - LDMA->CTRL = tmp; - -#else - - #error "SYNC Set and SYNC Clear not defined" - -#endif - - BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ - LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ - - /* A critical region end. */ - CORE_EXIT_ATOMIC(); -} - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/***************************************************************************//** - * @brief - * Start an extended DMA transfer. - * - * @param[in] ch - * A DMA channel. - * - * @param[in] transfer - * The initialization structure used to configure the transfer. - * - * @param[in] descriptor_ext - * The extended transfer descriptor, which can be an array of descriptors - * linked together. Each descriptor's fields stored in RAM will be loaded - * into the certain hardware registers at the proper time to perform the DMA - * transfer. - ******************************************************************************/ -void LDMA_StartTransferExtend(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_DescriptorExtend_t *descriptor_ext) -{ - // Ensure destination interleaving supported for given channel. - EFM_ASSERT(((1 << ch) & LDMA_ILCHNL)); - - LDMA_StartTransfer(ch, - transfer, - (const LDMA_Descriptor_t *)descriptor_ext); -} -#endif - -/***************************************************************************//** - * @brief - * Stop a DMA transfer. - * - * @note - * The DMA will complete the current AHB burst transfer before stopping. - * - * @param[in] ch - * A DMA channel to stop. - ******************************************************************************/ -void LDMA_StopTransfer(int ch) -{ - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - -#if defined(_LDMA_CHDIS_MASK) - CORE_ATOMIC_SECTION( - LDMA->IEN &= ~chMask; - LDMA->CHDIS = chMask; - ) -#else - CORE_ATOMIC_SECTION( - LDMA->IEN &= ~chMask; - BUS_RegMaskedClear(&LDMA->CHEN, chMask); - ) -#endif -} - -/***************************************************************************//** - * @brief - * Check if a DMA transfer has completed. - * - * @param[in] ch - * A DMA channel to check. - * - * @return - * True if transfer has completed, false if not. - ******************************************************************************/ -bool LDMA_TransferDone(int ch) -{ - bool retVal = false; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - -#if defined(_LDMA_CHSTATUS_MASK) - CORE_ATOMIC_SECTION( - if (((LDMA->CHSTATUS & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { - retVal = true; - } - ) -#else - CORE_ATOMIC_SECTION( - if (((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { - retVal = true; - } - ) -#endif - - return retVal; -} - -/***************************************************************************//** - * @brief - * Get the number of items remaining in a transfer. - * - * @note - * This function does not take into account that a DMA transfer with - * a chain of linked transfers might be ongoing. It will only check the - * count for the current transfer. - * - * @param[in] ch - * The channel number of the transfer to check. - * - * @return - * A number of items remaining in the transfer. - ******************************************************************************/ -uint32_t LDMA_TransferRemainingCount(int ch) -{ - uint32_t remaining, done, iflag; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - - CORE_ATOMIC_SECTION( - iflag = LDMA->IF; - done = LDMA->CHDONE; - remaining = LDMA->CH[ch].CTRL; - ) - - iflag &= chMask; - done &= chMask; - remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) - >> _LDMA_CH_CTRL_XFERCNT_SHIFT; - - if (done || ((remaining == 0) && iflag)) { - return 0; - } - - /* +1 because XFERCNT is 0-based. */ - return remaining + 1; -} - -/** @} (end addtogroup ldma) */ -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_ldma.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup ldma + * @{ + ******************************************************************************/ + +#if defined(LDMA_IRQ_HANDLER_TEMPLATE) +/***************************************************************************//** + * @brief + * A template for an LDMA IRQ handler. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + uint32_t ch; + /* Get all pending and enabled interrupts. */ + uint32_t pending = LDMA_IntGetEnabled(); + + /* Loop on an LDMA error to enable debugging. */ + while (pending & LDMA_IF_ERROR) { + } + + /* Iterate over all LDMA channels. */ + for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { + uint32_t mask = 0x1 << ch; + if (pending & mask) { + /* Clear the interrupt flag. */ + LDMA->IFC = mask; + + /* Perform more actions here, execute callbacks, and so on. */ + } + } +} +#endif + +/***************************************************************************//** + * @brief + * De-initialize the LDMA controller. + * + * LDMA interrupts are disabled and the LDMA clock is stopped. + ******************************************************************************/ +void LDMA_DeInit(void) +{ + NVIC_DisableIRQ(LDMA_IRQn); + LDMA->IEN = 0; +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif +#if defined(LDMA_EN_EN) + LDMA->EN = 0; +#if defined(LDMA_EN_DISABLING) + while (LDMA->EN & _LDMA_EN_DISABLING_MASK) { + } +#endif +#endif + + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable an LDMA channel request. + * + * @details + * Use this function to enable or disable an LDMA channel request. This will + * prevent the LDMA from proceeding after its current transaction if disabled. + * + * @param[in] ch + * LDMA channel to enable or disable requests. + * + * @param[in] enable + * If 'true', the request will be enabled. If 'false', the request will be disabled. + ******************************************************************************/ +void LDMA_EnableChannelRequest(int ch, bool enable) +{ + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); +} + +/***************************************************************************//** + * @brief + * Initialize the LDMA controller. + * + * @details + * This function will disable all the LDMA channels and enable the LDMA bus + * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC + * and set the LDMA IRQ priority to a user-configurable priority. The LDMA + * interrupt priority is configured using the @ref LDMA_Init_t structure. + * + * @note + * Since this function enables the LDMA IRQ, always add a custom + * LDMA_IRQHandler to the application to handle any interrupts + * from LDMA. + * + * @param[in] init + * A pointer to the initialization structure used to configure the LDMA. + ******************************************************************************/ +void LDMA_Init(const LDMA_Init_t *init) +{ + uint32_t ldmaCtrlVal; + EFM_ASSERT(init != NULL); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) + & ~_LDMA_CTRL_NUMFIXED_MASK)); + +#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); +#endif + +#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); +#endif + + EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); + + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif + +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + + ldmaCtrlVal = (uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; + +#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); +#endif + + LDMA->CTRL = ldmaCtrlVal; + +#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + LDMA->SYNCHWEN = ((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); +#endif + +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Enable the LDMA error interrupt. */ + LDMA->IEN = LDMA_IEN_ERROR; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = 0xFFFFFFFFU; +#else + LDMA->IFC = 0xFFFFFFFFU; +#endif + NVIC_ClearPendingIRQ(LDMA_IRQn); + + /* Range is 0-7, where 0 is the highest priority. */ + NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); + + NVIC_EnableIRQ(LDMA_IRQn); +} + +/***************************************************************************//** + * @brief + * Start a DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor + * The transfer descriptor, which can be an array of descriptors linked together. + * Each descriptor's fields stored in RAM will be loaded into the certain + * hardware registers at the proper time to perform the DMA transfer. + ******************************************************************************/ +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor) +{ +#if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + uint32_t tmp; +#endif + CORE_DECLARE_IRQ_STATE; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + EFM_ASSERT(transfer != NULL); + +#if defined (_LDMAXBAR_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); +#elif defined (_LDMA_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); +#endif + +#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); +#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); +#endif + + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) + & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); + + /* Clear the pending channel interrupt. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + +#if defined(LDMAXBAR) + LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; +#else + LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; +#endif + LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; + LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + | (transfer->ldmaCfgStructBusPort << _LDMA_CH_CFG_STRUCTBUSPORT_SHIFT) + | (transfer->ldmaCfgSrcBusPort << _LDMA_CH_CFG_SRCBUSPORT_SHIFT) + | (transfer->ldmaCfgDstBusPort << _LDMA_CH_CFG_DSTBUSPORT_SHIFT) +#endif + ; + + /* Set the descriptor address. */ + LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; + + /* A critical region. */ + CORE_ENTER_ATOMIC(); + + /* Enable the channel interrupt. */ + LDMA->IEN |= chMask; + + if (transfer->ldmaReqDis) { + LDMA->REQDIS |= chMask; + } + + if (transfer->ldmaDbgHalt) { + LDMA->DBGHALT |= chMask; + } + +#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + + LDMA->SYNCHWEN_CLR = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + + LDMA->SYNCHWEN_SET = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + +#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + + tmp = LDMA->CTRL; + + if (transfer->ldmaCtrlSyncPrsClrOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK + | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsClrOn) { + tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; + } + + if (transfer->ldmaCtrlSyncPrsSetOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK + | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsSetOn) { + tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; + } + + LDMA->CTRL = tmp; + +#else + + #error "SYNC Set and SYNC Clear not defined" + +#endif + + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ + LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ + + /* A critical region end. */ + CORE_EXIT_ATOMIC(); +} + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/***************************************************************************//** + * @brief + * Start an extended DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor_ext + * The extended transfer descriptor, which can be an array of descriptors + * linked together. Each descriptor's fields stored in RAM will be loaded + * into the certain hardware registers at the proper time to perform the DMA + * transfer. + ******************************************************************************/ +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext) +{ + // Ensure destination interleaving supported for given channel. + EFM_ASSERT(((1 << ch) & LDMA_ILCHNL)); + + LDMA_StartTransfer(ch, + transfer, + (const LDMA_Descriptor_t *)descriptor_ext); +} +#endif + +/***************************************************************************//** + * @brief + * Stop a DMA transfer. + * + * @note + * The DMA will complete the current AHB burst transfer before stopping. + * + * @param[in] ch + * A DMA channel to stop. + ******************************************************************************/ +void LDMA_StopTransfer(int ch) +{ + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHDIS_MASK) + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + LDMA->CHDIS = chMask; + ) +#else + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + BUS_RegMaskedClear(&LDMA->CHEN, chMask); + ) +#endif +} + +/***************************************************************************//** + * @brief + * Check if a DMA transfer has completed. + * + * @param[in] ch + * A DMA channel to check. + * + * @return + * True if transfer has completed, false if not. + ******************************************************************************/ +bool LDMA_TransferDone(int ch) +{ + bool retVal = false; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHSTATUS_MASK) + CORE_ATOMIC_SECTION( + if (((LDMA->CHSTATUS & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#else + CORE_ATOMIC_SECTION( + if (((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#endif + + return retVal; +} + +/***************************************************************************//** + * @brief + * Get the number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * + * @param[in] ch + * The channel number of the transfer to check. + * + * @return + * A number of items remaining in the transfer. + ******************************************************************************/ +uint32_t LDMA_TransferRemainingCount(int ch) +{ + uint32_t remaining, done, iflag; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + CORE_ATOMIC_SECTION( + iflag = LDMA->IF; + done = LDMA->CHDONE; + remaining = LDMA->CH[ch].CTRL; + ) + + iflag &= chMask; + done &= chMask; + remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) + >> _LDMA_CH_CTRL_XFERCNT_SHIFT; + + if (done || ((remaining == 0) && iflag)) { + return 0; + } + + /* +1 because XFERCNT is 0-based. */ + return remaining + 1; +} + +/** @} (end addtogroup ldma) */ +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c index 230b80a..5abc6f2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c @@ -1,685 +1,685 @@ -/***************************************************************************//** - * @file - * @brief Low Energy Timer (LETIMER) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_letimer.h" -#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) -#include "em_cmu.h" -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup letimer LETIMER - Low Energy Timer - * @brief Low Energy Timer (LETIMER) Peripheral API - * @details - * This module contains functions to control the LETIMER peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track - * of time and output configurable waveforms. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** A validation of the valid comparator register for assert statements. */ -#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) - -/** A validation of the LETIMER register block pointer reference for assert statements. */ -#if (LETIMER_COUNT == 1) -#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) -#elif (LETIMER_COUNT == 2) -#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) -#else -#error Undefined number of analog comparators (ACMP). -#endif - -/** A validation of the valid repeat counter register for assert statements. */ -#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. - * - * @note - * See the reference manual chapter about Access to Low Energy Peripherals - * (Asynchronos Registers) for details. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) -{ -#if defined(_LETIMER_FREEZE_MASK) - /* Avoid a deadlock if modifying the same register twice when freeze mode is */ - /* activated. */ - if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { - return; - } -#endif - - /* Wait for any pending write operation to complete. */ - while (letimer->SYNCBUSY & mask) { - } -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the LETIMER compare register value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] comp - * A compare register to get, either 0 or 1. - * - * @return - * A compare register value, 0 if invalid register selected. - ******************************************************************************/ -uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) -{ - uint32_t ret; - - EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); - - /* Initialize the selected compare value. */ - switch (comp) { - case 0: -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - ret = letimer->COMP0; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_COMP1) - regSync(letimer, LETIMER_SYNCBUSY_COMP1); -#endif - ret = letimer->COMP1; - break; - - default: - /* An unknown compare register selected. */ - ret = 0; - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Get LETIMER counter value. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @return - * Current LETIMER counter value. - ******************************************************************************/ -uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) -{ -#if defined(LETIMER_SYNCBUSY_CNT) - regSync(letimer, LETIMER_SYNCBUSY_CNT); -#endif - return letimer->CNT; -} - -#if !defined(_EFM32_GECKO_FAMILY) -/***************************************************************************//** - * @brief - * Set LETIMER counter value. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @param[in] value - * New counter value. - ******************************************************************************/ -void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value) -{ -#if defined(LETIMER_SYNCBUSY_CNT) - regSync(letimer, LETIMER_SYNCBUSY_CNT); -#endif - letimer->CNT = value; -} -#endif - -/***************************************************************************//** - * @brief - * Set the LETIMER compare register value. - * - * @note - * The setting of a compare register requires synchronization into the - * low frequency domain. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. This only applies to the Gecko Family. See - * comments in the LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] comp - * A compare register to set, either 0 or 1. - * - * @param[in] value - * An initialization value (<= 0x0000ffff). - ******************************************************************************/ -void LETIMER_CompareSet(LETIMER_TypeDef *letimer, - unsigned int comp, - uint32_t value) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer) - && LETIMER_COMP_REG_VALID(comp) - && ((value & ~(_LETIMER_COMP0_COMP0_MASK - >> _LETIMER_COMP0_COMP0_SHIFT)) - == 0)); - - /* Initialize the selected compare value. */ - switch (comp) { - case 0: -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - letimer->COMP0 = value; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_COMP1) - regSync(letimer, LETIMER_SYNCBUSY_COMP1); -#endif - letimer->COMP1 = value; - break; - - default: - /* An unknown compare register selected, abort. */ - break; - } -} - -/***************************************************************************//** - * @brief - * Start/stop LETIMER. - * - * @note - * The enabling/disabling of the LETIMER modifies the LETIMER CMD register - * which requires synchronization into the low-frequency domain. If this - * register is modified before a previous update to the same register has - * completed, this function will stall until the previous synchronization has - * completed. This only applies to the Gecko Family. See comments in the - * LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] enable - * True to enable counting, false to disable. - ******************************************************************************/ -void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer)); - -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) - regSync(letimer, LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START); -#endif - - if (enable) { - letimer->CMD = LETIMER_CMD_START; - } else { - letimer->CMD = LETIMER_CMD_STOP; - } -} - -#if defined(_LETIMER_FREEZE_MASK) -/***************************************************************************//** - * @brief - * LETIMER register synchronization freeze control. - * - * @details - * Some LETIMER registers require synchronization into the low-frequency (LF) - * domain. The freeze feature allows for several such registers to be - * modified before passing them to the LF domain simultaneously (which - * takes place when the freeze mode is disabled). - * - * @note - * When enabling freeze mode, this function will wait for all current - * ongoing LETIMER synchronization to the LF domain to complete (Normally - * synchronization will not be in progress.) However, for this reason, when - * using freeze mode, modifications of registers requiring the LF synchronization - * should be done within one freeze enable/disable block to avoid unecessary - * stalling. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] enable - * @li True - enable freeze, modified registers are not propagated to the - * LF domain - * @li False - disables freeze, modified registers are propagated to the LF - * domain - ******************************************************************************/ -void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) -{ - if (enable) { - /* - * Wait for any ongoing LF synchronization to complete to - * protect against the rare case when a user - * - modifies a register requiring LF sync - * - then enables freeze before LF sync completed - * - then modifies the same register again - * since modifying a register while it is in sync progress should be - * avoided. - */ - while (letimer->SYNCBUSY) { - } - - letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; - } else { - letimer->FREEZE = 0; - } -} -#endif /* defined(_LETIMER_FREEZE_MASK) */ - -/***************************************************************************//** - * @brief - * Initialize LETIMER. - * - * @details - * Note that the compare/repeat values must be set separately with - * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done - * prior using this function if configuring the LETIMER to start when - * initialization is complete. - * - * @note - * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers - * which require synchronization into the low-frequency domain. If any of those - * registers are modified before a previous update to the same register has - * completed, this function will stall until the previous synchronization has - * completed. This only applies to the Gecko Family. See comments in the - * LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] init - * A pointer to the LETIMER initialization structure. - ******************************************************************************/ -void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) -{ - uint32_t tmp = 0; - - EFM_ASSERT(LETIMER_REF_VALID(letimer)); - -#if defined (LETIMER_EN_EN) - letimer->EN_SET = LETIMER_EN_EN; -#endif - - /* Stop the timer if specified to be disabled and running. */ - if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined(LETIMER_SYNCBUSY_STOP) - regSync(letimer, LETIMER_SYNCBUSY_STOP); -#endif - letimer->CMD = LETIMER_CMD_STOP; - } - - /* Configure the DEBUGRUN flag, which sets whether or not the counter should be - * updated when the debugger is active. */ - if (init->debugRun) { - tmp |= LETIMER_CTRL_DEBUGRUN; - } - -#if defined(LETIMER_CTRL_RTCC0TEN) - if (init->rtcComp0Enable) { - tmp |= LETIMER_CTRL_RTCC0TEN; - } - - if (init->rtcComp1Enable) { - tmp |= LETIMER_CTRL_RTCC1TEN; - } -#endif - - if ((init->comp0Top) || (init->topValue != 0U)) { -#if defined (LETIMER_CTRL_COMP0TOP) - tmp |= LETIMER_CTRL_COMP0TOP; - if (init->topValue != 0U) { - letimer->COMP0 = init->topValue; - } -#elif defined (LETIMER_CTRL_CNTTOPEN) - tmp |= LETIMER_CTRL_CNTTOPEN; - if (init->topValue != 0U) { - letimer->TOP = init->topValue; - } -#endif - } - - if (init->bufTop) { - tmp |= LETIMER_CTRL_BUFTOP; - } - - if (init->out0Pol) { - tmp |= LETIMER_CTRL_OPOL0; - } - - if (init->out1Pol) { - tmp |= LETIMER_CTRL_OPOL1; - } - - tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; - tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; - tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; - -#if defined(LETIMER_SYNCBUSY_CTRL) - /* LF register about to be modified requires sync; busy check. */ - regSync(letimer, LETIMER_SYNCBUSY_CTRL); -#endif - letimer->CTRL = tmp; - - /* Start the timer if specified to be enabled and not already running. */ - if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined(LETIMER_SYNCBUSY_START) - regSync(letimer, LETIMER_SYNCBUSY_START); -#endif - letimer->CMD = LETIMER_CMD_START; - } -} - -/***************************************************************************//** - * @brief - * Get the LETIMER repeat register value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] rep - * Repeat register to get, either 0 or 1. - * - * @return - * Repeat register value, 0 if invalid register selected. - ******************************************************************************/ -uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) -{ - uint32_t ret; - - EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); - - /* Initialize the selected compare value. */ - switch (rep) { - case 0: -#if defined(LETIMER_SYNCBUSY_REP0) - /* Wait for sync to complete to read the potentially pending value. */ - regSync(letimer, LETIMER_SYNCBUSY_REP0); -#endif - ret = letimer->REP0; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_REP1) - regSync(letimer, LETIMER_SYNCBUSY_REP1); -#endif - ret = letimer->REP1; - break; - - default: - /* An unknown compare register selected. */ - ret = 0; - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the LETIMER repeat counter register value. - * - * @note - * The setting of a repeat counter register requires synchronization into the - * low-frequency domain. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. This only applies to the Gecko Family. See - * comments in the LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] rep - * Repeat counter register to set, either 0 or 1. - * - * @param[in] value - * An initialization value (<= 0x0000ffff). - ******************************************************************************/ -void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, - unsigned int rep, - uint32_t value) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer) - && LETIMER_REP_REG_VALID(rep) - && ((value & ~(_LETIMER_REP0_REP0_MASK - >> _LETIMER_REP0_REP0_SHIFT)) - == 0)); - - /* Initialize the selected compare value. */ - switch (rep) { - case 0: -#if defined(LETIMER_SYNCBUSY_REP0) - regSync(letimer, LETIMER_SYNCBUSY_REP0); -#endif - letimer->REP0 = value; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_REP1) - regSync(letimer, LETIMER_SYNCBUSY_REP1); -#endif - letimer->REP1 = value; - break; - - default: - /* An unknown compare register selected, abort. */ - break; - } -} - -/***************************************************************************//** - * @brief - * Reset LETIMER to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * a centralized setup of this feature. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - ******************************************************************************/ -void LETIMER_Reset(LETIMER_TypeDef *letimer) -{ -#if defined(LETIMER_EN_EN) - letimer->EN_SET = LETIMER_EN_EN; -#endif - LETIMER_SyncWait(letimer); - -#if defined(LETIMER_SWRST_SWRST) - letimer->SWRST_SET = LETIMER_SWRST_SWRST; - while (letimer->SWRST & _LETIMER_SWRST_RESETTING_MASK) { - } -#else - -#if defined(_LETIMER_FREEZE_MASK) - /* Freeze registers to avoid stalling for LF synchronization. */ - LETIMER_FreezeEnable(letimer, true); -#endif - - /* Make sure disabled first, before resetting other registers. */ - letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR - | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; - letimer->CTRL = _LETIMER_CTRL_RESETVALUE; - letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; - letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; - letimer->REP0 = _LETIMER_REP0_RESETVALUE; - letimer->REP1 = _LETIMER_REP1_RESETVALUE; - letimer->IEN = _LETIMER_IEN_RESETVALUE; - LETIMER_IntClear(letimer, _LETIMER_IF_MASK); - -#if defined(_LETIMER_FREEZE_MASK) - /* Unfreeze registers and pass new settings to LETIMER. */ - LETIMER_FreezeEnable(letimer, false); -#endif - - LETIMER_SyncWait(letimer); - -#if defined (LETIMER_EN_EN) - letimer->EN_CLR = LETIMER_EN_EN; -#if defined(_LETIMER_EN_DISABLING_MASK) - /* - * Currently, there are no chips without SWRST and with LETIMER_EN_DISABLING - * so this code should never be reached, but that way the same pattern of - * checking the disabling bit is spread across emlib, and code is slightly - * more resilient to feature addition/removal. - */ - while (letimer->EN & _LETIMER_EN_DISABLING_MASK) { - } -#endif -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Wait for the LETIMER to complete all synchronization of register changes - * and commands. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - ******************************************************************************/ -void LETIMER_SyncWait(LETIMER_TypeDef *letimer) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { - /* Wait for previous synchronization to finish */ - } -#else - while (letimer->SYNCBUSY != 0U) { - /* Wait for previous synchronization to finish */ - } -#endif -} - -/***************************************************************************//** - * @brief - * Set the LETIMER top value. - * - * @note - * The LETIMER is a down-counter, so when the counter reaches 0 then the top - * value will be loaded into the counter. This function can be used to set - * the top value. - * - * If the LETIMER is not already configured to use a top value then this - * function will enable that functionality for the user. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] value - * The top value. This can be a 16 bit value on series-0 and series-1 devices - * and a 24 bit value on series-2 devices. - ******************************************************************************/ -void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) -{ -#if defined(LETIMER_SYNCBUSY_CTRL) - regSync(letimer, LETIMER_SYNCBUSY_CTRL); -#elif defined(LETIMER_SYNCBUSY_TOP) - regSync(letimer, LETIMER_SYNCBUSY_TOP); -#endif - -#if defined(_LETIMER_TOP_MASK) - /* Make sure TOP value is enabled. */ - if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { - letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; - } - letimer->TOP = value; -#else - /* Make sure TOP value is enabled. */ - if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { - letimer->CTRL |= LETIMER_CTRL_COMP0TOP; - } - LETIMER_CompareSet(letimer, 0, value); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current LETIMER top value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @return - * The top value. This will be a 16 bit value on series-0 and series-1 - * devices and a 24 bit value on series-2 devices. - ******************************************************************************/ -uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) -{ -#if defined(_LETIMER_TOP_MASK) - regSync(letimer, LETIMER_SYNCBUSY_TOP); - return letimer->TOP; -#else -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - return letimer->COMP0; -#endif -} - -/** @} (end addtogroup letimer) */ -#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_letimer.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) +#include "em_cmu.h" +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup letimer LETIMER - Low Energy Timer + * @brief Low Energy Timer (LETIMER) Peripheral API + * @details + * This module contains functions to control the LETIMER peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track + * of time and output configurable waveforms. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** A validation of the valid comparator register for assert statements. */ +#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) + +/** A validation of the LETIMER register block pointer reference for assert statements. */ +#if (LETIMER_COUNT == 1) +#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) +#elif (LETIMER_COUNT == 2) +#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) +#else +#error Undefined number of analog comparators (ACMP). +#endif + +/** A validation of the valid repeat counter register for assert statements. */ +#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. + * + * @note + * See the reference manual chapter about Access to Low Energy Peripherals + * (Asynchronos Registers) for details. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) +{ +#if defined(_LETIMER_FREEZE_MASK) + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { + return; + } +#endif + + /* Wait for any pending write operation to complete. */ + while (letimer->SYNCBUSY & mask) { + } +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the LETIMER compare register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to get, either 0 or 1. + * + * @return + * A compare register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + ret = letimer->COMP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + ret = letimer->COMP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Get LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @return + * Current LETIMER counter value. + ******************************************************************************/ +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + return letimer->CNT; +} + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Set LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] value + * New counter value. + ******************************************************************************/ +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + letimer->CNT = value; +} +#endif + +/***************************************************************************//** + * @brief + * Set the LETIMER compare register value. + * + * @note + * The setting of a compare register requires synchronization into the + * low frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_COMP_REG_VALID(comp) + && ((value & ~(_LETIMER_COMP0_COMP0_MASK + >> _LETIMER_COMP0_COMP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + letimer->COMP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + letimer->COMP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Start/stop LETIMER. + * + * @note + * The enabling/disabling of the LETIMER modifies the LETIMER CMD register + * which requires synchronization into the low-frequency domain. If this + * register is modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START); +#endif + + if (enable) { + letimer->CMD = LETIMER_CMD_START; + } else { + letimer->CMD = LETIMER_CMD_STOP; + } +} + +#if defined(_LETIMER_FREEZE_MASK) +/***************************************************************************//** + * @brief + * LETIMER register synchronization freeze control. + * + * @details + * Some LETIMER registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing LETIMER synchronization to the LF domain to complete (Normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring the LF synchronization + * should be done within one freeze enable/disable block to avoid unecessary + * stalling. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * @li True - enable freeze, modified registers are not propagated to the + * LF domain + * @li False - disables freeze, modified registers are propagated to the LF + * domain + ******************************************************************************/ +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) +{ + if (enable) { + /* + * Wait for any ongoing LF synchronization to complete to + * protect against the rare case when a user + * - modifies a register requiring LF sync + * - then enables freeze before LF sync completed + * - then modifies the same register again + * since modifying a register while it is in sync progress should be + * avoided. + */ + while (letimer->SYNCBUSY) { + } + + letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; + } else { + letimer->FREEZE = 0; + } +} +#endif /* defined(_LETIMER_FREEZE_MASK) */ + +/***************************************************************************//** + * @brief + * Initialize LETIMER. + * + * @details + * Note that the compare/repeat values must be set separately with + * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done + * prior using this function if configuring the LETIMER to start when + * initialization is complete. + * + * @note + * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers + * which require synchronization into the low-frequency domain. If any of those + * registers are modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] init + * A pointer to the LETIMER initialization structure. + ******************************************************************************/ +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) +{ + uint32_t tmp = 0; + + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined (LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled and running. */ + if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP); +#endif + letimer->CMD = LETIMER_CMD_STOP; + } + + /* Configure the DEBUGRUN flag, which sets whether or not the counter should be + * updated when the debugger is active. */ + if (init->debugRun) { + tmp |= LETIMER_CTRL_DEBUGRUN; + } + +#if defined(LETIMER_CTRL_RTCC0TEN) + if (init->rtcComp0Enable) { + tmp |= LETIMER_CTRL_RTCC0TEN; + } + + if (init->rtcComp1Enable) { + tmp |= LETIMER_CTRL_RTCC1TEN; + } +#endif + + if ((init->comp0Top) || (init->topValue != 0U)) { +#if defined (LETIMER_CTRL_COMP0TOP) + tmp |= LETIMER_CTRL_COMP0TOP; + if (init->topValue != 0U) { + letimer->COMP0 = init->topValue; + } +#elif defined (LETIMER_CTRL_CNTTOPEN) + tmp |= LETIMER_CTRL_CNTTOPEN; + if (init->topValue != 0U) { + letimer->TOP = init->topValue; + } +#endif + } + + if (init->bufTop) { + tmp |= LETIMER_CTRL_BUFTOP; + } + + if (init->out0Pol) { + tmp |= LETIMER_CTRL_OPOL0; + } + + if (init->out1Pol) { + tmp |= LETIMER_CTRL_OPOL1; + } + + tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; + tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; + tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; + +#if defined(LETIMER_SYNCBUSY_CTRL) + /* LF register about to be modified requires sync; busy check. */ + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#endif + letimer->CTRL = tmp; + + /* Start the timer if specified to be enabled and not already running. */ + if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_START) + regSync(letimer, LETIMER_SYNCBUSY_START); +#endif + letimer->CMD = LETIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Get the LETIMER repeat register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat register to get, either 0 or 1. + * + * @return + * Repeat register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + /* Wait for sync to complete to read the potentially pending value. */ + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + ret = letimer->REP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + ret = letimer->REP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the LETIMER repeat counter register value. + * + * @note + * The setting of a repeat counter register requires synchronization into the + * low-frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat counter register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_REP_REG_VALID(rep) + && ((value & ~(_LETIMER_REP0_REP0_MASK + >> _LETIMER_REP0_REP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + letimer->REP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + letimer->REP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Reset LETIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_Reset(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + LETIMER_SyncWait(letimer); + +#if defined(LETIMER_SWRST_SWRST) + letimer->SWRST_SET = LETIMER_SWRST_SWRST; + while (letimer->SWRST & _LETIMER_SWRST_RESETTING_MASK) { + } +#else + +#if defined(_LETIMER_FREEZE_MASK) + /* Freeze registers to avoid stalling for LF synchronization. */ + LETIMER_FreezeEnable(letimer, true); +#endif + + /* Make sure disabled first, before resetting other registers. */ + letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR + | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; + letimer->CTRL = _LETIMER_CTRL_RESETVALUE; + letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; + letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; + letimer->REP0 = _LETIMER_REP0_RESETVALUE; + letimer->REP1 = _LETIMER_REP1_RESETVALUE; + letimer->IEN = _LETIMER_IEN_RESETVALUE; + LETIMER_IntClear(letimer, _LETIMER_IF_MASK); + +#if defined(_LETIMER_FREEZE_MASK) + /* Unfreeze registers and pass new settings to LETIMER. */ + LETIMER_FreezeEnable(letimer, false); +#endif + + LETIMER_SyncWait(letimer); + +#if defined (LETIMER_EN_EN) + letimer->EN_CLR = LETIMER_EN_EN; +#if defined(_LETIMER_EN_DISABLING_MASK) + /* + * Currently, there are no chips without SWRST and with LETIMER_EN_DISABLING + * so this code should never be reached, but that way the same pattern of + * checking the disabling bit is spread across emlib, and code is slightly + * more resilient to feature addition/removal. + */ + while (letimer->EN & _LETIMER_EN_DISABLING_MASK) { + } +#endif +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the LETIMER to complete all synchronization of register changes + * and commands. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_SyncWait(LETIMER_TypeDef *letimer) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (letimer->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +/***************************************************************************//** + * @brief + * Set the LETIMER top value. + * + * @note + * The LETIMER is a down-counter, so when the counter reaches 0 then the top + * value will be loaded into the counter. This function can be used to set + * the top value. + * + * If the LETIMER is not already configured to use a top value then this + * function will enable that functionality for the user. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] value + * The top value. This can be a 16 bit value on series-0 and series-1 devices + * and a 24 bit value on series-2 devices. + ******************************************************************************/ +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CTRL) + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#elif defined(LETIMER_SYNCBUSY_TOP) + regSync(letimer, LETIMER_SYNCBUSY_TOP); +#endif + +#if defined(_LETIMER_TOP_MASK) + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { + letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; + } + letimer->TOP = value; +#else + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { + letimer->CTRL |= LETIMER_CTRL_COMP0TOP; + } + LETIMER_CompareSet(letimer, 0, value); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current LETIMER top value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @return + * The top value. This will be a 16 bit value on series-0 and series-1 + * devices and a 24 bit value on series-2 devices. + ******************************************************************************/ +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) +{ +#if defined(_LETIMER_TOP_MASK) + regSync(letimer, LETIMER_SYNCBUSY_TOP); + return letimer->TOP; +#else +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + return letimer->COMP0; +#endif +} + +/** @} (end addtogroup letimer) */ +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c index bca6b0a..0f35292 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c @@ -1,2075 +1,2075 @@ -/***************************************************************************//** - * @file - * @brief Flash controller (MSC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_msc.h" -#if defined(MSC_COUNT) && (MSC_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include "em_core.h" -#include "em_system.h" - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(__ICCARM__) -/* Suppress warnings originating from use of EFM_ASSERT() with IAR Embedded Workbench */ -#pragma diag_suppress=Ta022,Ta023 -#endif - -#if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) -#error "Running Flash write/erase operations from Flash is not supported on EFM32G." -#endif - -/******************************************************************************* - ****************************** DEFINES ****************************** - ******************************************************************************/ -#if defined(MSC_WRITECTRL_WDOUBLE) -#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) -#else -#define WORDS_PER_DATA_PHASE (1) -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/* Fix for errata FLASH_E201 - Potential program failure after Power On */ -#define ERRATA_FIX_FLASH_E201_EN -#endif - -#define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) -/* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 - banks (not RAM2). It is necessary to figure out which is biggest to - calculate the number of DMA descriptors needed. */ -#define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) - -#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) - -#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) - -#define ECC_CTRL_REG (MSC->ECCCTRL) -#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) -#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) -#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) - -#define ECC_IFC_REG (MSC->IFC) -#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ - | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) - -#define ECC_FAULT_CTRL_REG (MSC->CTRL) -#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -/* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and - RAM2 banks. All banks are of equal size. */ -#define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) - -#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) - -#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) - -#define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) -#define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) - -#define ECC_CTRL_REG (MSC->ECCCTRL) -#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) -#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) -#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) -#define ECC_RAM2_SYNDROMES_INIT (MSC_ECCCTRL_RAM2ECCEWEN) -#define ECC_RAM2_CORRECTION_EN (MSC_ECCCTRL_RAM2ECCCHKEN) - -#define ECC_IFC_REG (MSC->IFC) -#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ - | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ - | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) - -#define ECC_FAULT_CTRL_REG (MSC->CTRL) -#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) - -#elif defined(_SILICON_LABS_32B_SERIES_2) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -/* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the - main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ -#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN) - -#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) - -/* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the - main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ -#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEN) -#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) - -#define ECC_IF_REG (SYSCFG->IF) -#define ECC_IF_1BIT_ERROR (SYSCFG_IF_RAMERR1B) - -#elif defined(_MPAHBRAM_CTRL_MASK) - -/* From Series 2 Config 3, aka EFR32XG23, ECC is now standalone in the - * MPAHBRAM module */ -#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) -#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) -#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) -#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) -#endif - -#define ECC_IF_REG (DMEM->IF) -/* number of AHB ports is between 1 and 4 */ -#if defined(MPAHBRAM_IF_AHB3ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B | MPAHBRAM_IF_AHB3ERR1B) -#elif defined(MPAHBRAM_IF_AHB2ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B) -#elif defined(MPAHBRAM_IF_AHB1ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B) -#else -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B) -#endif - -#else - -#error "Unknown device" - -#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */ - -#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - -#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE) -#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE) - -#define ECC_CTRL0_REG (DMEM0->CTRL) -#define ECC_CTRL1_REG (DMEM1->CTRL) - -#define ECC_IFC0_REG (DMEM0->IF_CLR) -#define ECC_IFC1_REG (DMEM1->IF_CLR) -#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) - -#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL) -#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL) -#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) - -#else - -#define ECC_RAM0_MEM_BASE (SRAM_BASE) -#define ECC_RAM0_MEM_SIZE (SRAM_SIZE) - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) -#define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) -#define ECC_IFC_REG (SYSCFG->IF_CLR) -#define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) -#define ECC_FAULT_CTRL_REG (SYSCFG->CTRL) -#define ECC_FAULT_EN (SYSCFG_CTRL_RAMECCERRFAULTEN) - -#elif defined(_MPAHBRAM_CTRL_MASK) -#define ECC_CTRL_REG (DMEM->CTRL) -#define ECC_IFC_REG (DMEM->IF_CLR) -#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) -#define ECC_FAULT_CTRL_REG (DMEM->CTRL) -#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) -#endif - -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#else - -#error Unknown device. - -#endif - -#define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ - >> _LDMA_CH_CTRL_XFERCNT_SHIFT) -#define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ - -#define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -/***************************************************************************//** - * @brief - * Get locked status of the MSC registers. - * - * @detail - * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions - * that can be placed either in flash or in RAM. - ******************************************************************************/ -#if defined(_MSC_STATUS_REGLOCK_MASK) -#define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) -#else -#define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) -#endif - -/******************************************************************************* - ****************************** TYPEDEFS ****************************** - ******************************************************************************/ - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -typedef struct { - uint32_t initSyndromeEnable; - uint32_t correctionEnable; - uint32_t base; - uint32_t size; -} MSC_EccBank_Typedef; - -#endif - -/******************************************************************************* - ****************************** LOCALS ******************************* - ******************************************************************************/ -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -static const MSC_EccBank_Typedef eccBankTbl[MSC_ECC_BANKS] = -{ - { - ECC_RAM0_SYNDROMES_INIT, ECC_RAM0_CORRECTION_EN, - ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE - }, -#if MSC_ECC_BANKS > 1 - { - ECC_RAM1_SYNDROMES_INIT, ECC_RAM1_CORRECTION_EN, - ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE - }, -#if MSC_ECC_BANKS > 2 - { - ECC_RAM2_SYNDROMES_INIT, ECC_RAM2_CORRECTION_EN, - ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE - }, -#endif -#endif -}; -#endif - -/******************************************************************************* - ****************************** FUNCTIONS ****************************** - ******************************************************************************/ -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_WriteWordI(uint32_t *address, - void const *data, - uint32_t numBytes); - -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_LoadWriteData(uint32_t* data, - uint32_t numWords); - -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_LoadVerifyAddress(uint32_t* address); - -/** @endcond */ - -/***************************************************************************//** - * @addtogroup msc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Wait for a specified MSC status or timeout. - * - * @param[in] mask - * MSC->STATUS register mask to apply when testing for specified status. - * @param[in] value - * The value the MSC->STATUS test is waiting to see. - * @return - * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - Specified status criteria fulfilled. - * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * write or erase a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) -{ - uint32_t timeOut = MSC_PROGRAM_TIMEOUT; - - while (timeOut) { - uint32_t status = MSC->STATUS; - - /* if INVADDR is asserted by MSC, BUSY will never go high, can be checked early */ - if (status & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - /* - * if requested operation fails because flash is locked, BUSY will be high - * for a few cycles and it's not safe to clear WRITECTRL.WREN during that - * period. mscStatusWait should return only when it's safe to do so. - * - * So if user is checking BUSY flag, make sure it matches user's expected - * value and only then check the lock bits. Otherwise, do check early and - * bail out if necessary. - */ - - if ((!(mask & MSC_STATUS_BUSY)) - && (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK))) { - return mscReturnLocked; - } - - if ((status & mask) == value) { - if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { - return mscReturnLocked; - } else { - return mscReturnOk; - } - } - - timeOut--; - } - - return mscReturnTimeOut; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. It is assumed that start address is word - * aligned and that numBytes is an integer multiple of four, and that the - * write operation does not cross a flash page boundary. - * - * @param[in] address - * Pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * Returns the status of the write operation, @ref MSC_Status_TypeDef - * @verbatim - * flashReturnOk - Operation completed successfully. - * flashReturnInvalidAddr - Operation tried to write to a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * program a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -msc_Return_TypeDef writeBurst(uint32_t address, - const uint32_t *data, - uint32_t numBytes) -{ - msc_Return_TypeDef retVal; - - MSC->ADDRB = address; - - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - MSC->WDATA = *data++; - numBytes -= 4; - - while (numBytes) { - retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY); - - if (retVal != mscReturnOk) { - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - return retVal; - } - - MSC->WDATA = *data++; - numBytes -= 4; - } - - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - - if (retVal == mscReturnOk) { - // We need to check twice to be sure - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Initialize MSC module. Puts MSC hw in a known state. - ******************************************************************************/ -void MSC_Init(void) -{ -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - // Unlock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; -} - -/***************************************************************************//** - * @brief - * Turn off MSC flash write enable and lock MSC registers. - ******************************************************************************/ -void MSC_Deinit(void) -{ - // Unlock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - // Lock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_CLR = CMU_CLKEN1_MSC; -#endif -} - -/***************************************************************************//** - * @brief - * Set MSC code execution configuration - * - * @param[in] execConfig - * Code execution configuration - ******************************************************************************/ -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) -{ - uint32_t mscReadCtrl; - -#if defined(MSC_RDATACTRL_DOUTBUFEN) - mscReadCtrl = MSC->RDATACTRL & ~MSC_RDATACTRL_DOUTBUFEN; - - if (execConfig->doutBufEn) { - mscReadCtrl |= MSC_RDATACTRL_DOUTBUFEN; - } - - MSC->RDATACTRL = mscReadCtrl; -#elif defined(MSC_READCTRL_DOUTBUFEN) - mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; - - if (execConfig->doutBufEn) { - mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; - } - MSC->READCTRL = mscReadCtrl; -#endif -} - -/***************************************************************************//** - * @brief - * Erases a page in flash memory. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved - * automatically by using attributes in the function proctype. For Keil - * uVision you must define a section called "ram_code" and place this manually - * in your project's scatter file. - * - * @param[in] startAddress - * Pointer to the flash page to erase. Must be aligned to beginning of page - * boundary. - * @return - * Returns the status of erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - Operation completed successfully. - * mscReturnInvalidAddr - Operation tried to erase a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * erase a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) -{ - MSC_Status_TypeDef retVal; - bool wasLocked; - - // Address must be aligned to page boundary - EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; - MSC->ADDRB = (uint32_t)startAddress; - MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; - - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - - if (retVal == mscReturnOk) { - // We need to check twice to be sure - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - } - - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. Write data must be aligned to words and - * contain a number of bytes that is divisible by four. - * @note - * It is recommended to erase the flash page before performing a write. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved - * automatically by using attributes in the function proctype. For Keil - * uVision you must define a section called "ram_code" and place this manually - * in your project's scatter file. - * - * The Flash memory is organized into 64-bit wide double-words. - * Each 64-bit double-word can be written only twice using burst write - * operation between erasing cycles. The user's application must store data in - * RAM to sustain burst write operation. - * - * EFR32XG21 RevC is not able to program every word twice before the next erase. - * - * @param[in] address - * Pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * Returns the status of the write operation, @ref MSC_Status_TypeDef - * @verbatim - * flashReturnOk - Operation completed successfully. - * flashReturnInvalidAddr - Operation tried to write to a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * program a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - uint32_t addr; - const uint8_t *pData; - uint32_t burstLen; - MSC_Status_TypeDef retVal = mscReturnOk; - bool wasLocked; - - // Check alignment (must be aligned to words) - EFM_ASSERT(((uint32_t)address & 0x3U) == 0); - // Check number of bytes, must be divisable by four - EFM_ASSERT((numBytes & 0x3U) == 0); - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - // Enable flash write - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; - - addr = (uint32_t)address; - pData = (uint8_t*)data; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); - - if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) - != mscReturnOk) { - break; - } - - addr += burstLen; - pData += burstLen; - numBytes -= burstLen; - } - - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_MassErase(void) -{ - MSC_Status_TypeDef retVal; - - if (MSC_IS_LOCKED()) { - return mscReturnLocked; - } - - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // Set write enable bit - MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; // Enable Write ctrl access - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; // Start Mass erase procedure - retVal = mscStatusWait(MSC_STATUS_BUSY, 0); // Wait for end of busy flag or a problem (INVADDR, LOCK, REGLOCK, TIMEOUT) - MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; // Reenable mass erase lock bit - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Disable Write ctrl access - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory using the DMA. - * - * @details - * This function uses the LDMA to write data to the internal flash memory. - * This is the fastest way to write data to the flash and should be used when - * the application wants to achieve write speeds like they are reported in the - * datasheet. Note that copying data from flash to flash will be slower than - * copying from RAM to flash. So the source data must be in RAM in order to - * see the write speeds similar to the datasheet numbers. - * - * @note - * This function requires that the LDMA and LDMAXBAR clock is enabled. - * - * @param[in] ch - * DMA channel to use - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * - * @param[in] data - * Data to write to flash and be aligned to words. - * - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * @endverbatim - ******************************************************************************/ -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes) -{ - uint32_t words = numBytes / 4; - uint32_t burstLen; - uint32_t src = (uint32_t) data; - uint32_t dst = (uint32_t) address; - bool wasLocked; - - EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); - - LDMA->EN_SET = 0x1; - LDMAXBAR->CH[ch].REQSEL = LDMAXBAR_CH_REQSEL_SOURCESEL_MSC - | LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA; - LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; - LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; - LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - // Unlock MSC - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Enable writing to the MSC module. - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); - words = burstLen / 4; - - // Load the address. - MSC->ADDRB = dst; - - // Check for an invalid address. - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE - | LDMA_CH_CTRL_SIZE_WORD - | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); - LDMA->CH[ch].SRC = (uint32_t)src; - LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; - - // Enable channel - LDMA->CHEN_SET = (0x1 << ch); - - while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { - ; - } - - LDMA->CHDONE_CLR = (0x1 << ch); - LDMA->CHDIS_SET = (0x1 << ch); - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - dst += burstLen; - src += burstLen; - numBytes -= burstLen; - } - - // Disable writing to the MSC module. - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return mscReturnOk; -} - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/***************************************************************************//** - * @brief - * Enables the flash controller for writing. - * @note - * This function must be called before flash operations when - * AUXHFRCO clock has been changed from a default band. - ******************************************************************************/ -void MSC_Init(void) -{ -#if defined(_MSC_TIMEBASE_MASK) - uint32_t freq, cycles; -#endif - -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done. Flash erase and write requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Unlock the MSC module. */ - MSC->LOCK = MSC_UNLOCK_CODE; - /* Disable writing to the Flash. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - -#if defined(_MSC_TIMEBASE_MASK) - /* Configure MSC->TIMEBASE according to a selected frequency. */ - freq = CMU_ClockFreqGet(cmuClock_AUX); - - /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band - is tuned to 1.2 MHz on newer revisions. */ - if (freq > 1200000) { - /* Calculate a number of clock cycles for 1 us as a base period. */ - freq = (freq * 11) / 10; - cycles = (freq / 1000000) + 1; - - /* Configure clock cycles for flash timing. */ - MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK - | _MSC_TIMEBASE_PERIOD_MASK)) - | MSC_TIMEBASE_PERIOD_1US - | (cycles << _MSC_TIMEBASE_BASE_SHIFT); - } else { - /* Calculate a number of clock cycles for 5 us as a base period. */ - freq = (freq * 5 * 11) / 10; - cycles = (freq / 1000000) + 1; - - /* Configure clock cycles for flash timing */ - MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK - | _MSC_TIMEBASE_PERIOD_MASK)) - | MSC_TIMEBASE_PERIOD_5US - | (cycles << _MSC_TIMEBASE_BASE_SHIFT); - } -#endif -} - -/***************************************************************************//** - * @brief - * Disables the flash controller for writing. - ******************************************************************************/ -void MSC_Deinit(void) -{ - /* Disable writing to the Flash. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - /* Lock the MSC module.*/ - MSC->LOCK = 0; -} - -/***************************************************************************//** - * @brief - * Set the MSC code execution configuration. - * - * @param[in] execConfig - * The code execution configuration. - ******************************************************************************/ -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) -{ - uint32_t mscReadCtrl; - -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; - if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS0; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS1; - } else { - /* No change needed. */ - } -#endif - - mscReadCtrl = MSC->READCTRL & ~(0 -#if defined(MSC_READCTRL_SCBTP) - | MSC_READCTRL_SCBTP -#endif -#if defined(MSC_READCTRL_USEHPROT) - | MSC_READCTRL_USEHPROT -#endif -#if defined(MSC_READCTRL_PREFETCH) - | MSC_READCTRL_PREFETCH -#endif -#if defined(MSC_READCTRL_ICCDIS) - | MSC_READCTRL_ICCDIS -#endif -#if defined(MSC_READCTRL_AIDIS) - | MSC_READCTRL_AIDIS -#endif -#if defined(MSC_READCTRL_IFCDIS) - | MSC_READCTRL_IFCDIS -#endif - ); - mscReadCtrl |= (0 -#if defined(MSC_READCTRL_SCBTP) - | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) -#endif -#if defined(MSC_READCTRL_USEHPROT) - | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) -#endif -#if defined(MSC_READCTRL_PREFETCH) - | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) -#endif -#if defined(MSC_READCTRL_ICCDIS) - | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) -#endif -#if defined(MSC_READCTRL_AIDIS) - | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) -#endif -#if defined(MSC_READCTRL_IFCDIS) - | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) -#endif - ); - - MSC->READCTRL = mscReadCtrl; -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Perform the address phase of the flash write cycle. - * @details - * This function performs the address phase of a flash write operation by - * writing the given flash address to the ADDRB register and issuing the - * LADDRIM command to load the address. - * @param[in] address - * An address in flash memory. Must be aligned at a 4 byte boundary. - * @return - * Returns the status of the address load operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - The operation completed successfully. - * mscReturnInvalidAddr - The operation tried to erase a non-flash area. - * mscReturnLocked - The operation tried to erase a locked area of the Flash. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) -{ - uint32_t timeOut; - - /* Wait for the MSC to become ready. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - /* Load the address. */ - MSC->ADDRB = (uint32_t)address; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - /* Check for an invalid address. */ - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - return mscReturnOk; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Perform a flash data write phase. - * @details - * This function performs the data phase of a flash write operation by loading - * the given number of 32-bit words to the WDATA register. - * @param[in] data - * A pointer to the first data word to load. - * @param[in] numWords - * A number of data words (32-bit) to load. - * @return - * Returns the status of the data load operation. - * @verbatim - * mscReturnOk - An operation completed successfully. - * mscReturnTimeOut - An operation timed out waiting for the flash operation - * to complete. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, - uint32_t numWords) -{ - uint32_t timeOut; - uint32_t wordIndex; - bool useWDouble = false; - MSC_Status_TypeDef retval = mscReturnOk; - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) - /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ - if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { - /* If the number of words to be written is odd, align by writing - a single word first, before setting the WDOUBLE bit. */ - if (numWords & 0x1) { - /* Wait for the MSC to become ready for the next word. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { - timeOut--; - } - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - - /* Clear the double word option to write the initial single word. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; - /* Write first data word. */ - MSC->WDATA = *data++; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - - /* Wait for the operation to finish. It may be required to change the WDOUBLE - configuration after the initial write. It should not be changed while BUSY. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - /* Check for a write protected flash area. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - return mscReturnLocked; - } - /* Subtract this initial odd word for the write loop below. */ - numWords -= 1; - retval = mscReturnOk; - } - /* Set the double word option to write two words per - data phase. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; - useWDouble = true; - } -#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ - - /* Write the rest as a double word write if wordsPerDataPhase == 2 */ - if (numWords > 0) { - /* Requires a system core clock at 1MHz or higher */ - EFM_ASSERT(SystemCoreClock >= 1000000); - wordIndex = 0; - while (wordIndex < numWords) { - if (!useWDouble) { - MSC->WDATA = *data++; - wordIndex++; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - } else { - /* Trigger a double write according to flash properties. */ -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) - MSC->WDATA = *data++; - while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; - MSC->WDATA = *data++; - wordIndex += 2; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; -#endif - } - - /* Wait for the transaction to finish. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for a timeout. */ - if (timeOut == 0) { - retval = mscReturnTimeOut; - break; - } - /* Check for a write protected flash area. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - retval = mscReturnLocked; - break; - } -#if defined(_EFM32_GECKO_FAMILY) - MSC->ADDRB += 4; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; -#endif - } - } - -#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) - /* Clear a double word option, which should not be left on when returning. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; -#endif - - return retval; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * An internal flash write function. - * @param[in] address - * A write address. - * @param[in] data - * A pointer to the first data word to load. - * @param[in] numBytes - * A nsumber of data bytes to load, which must be a multiple of 4 bytes. - * @return - * Returns the status of the data load operation. - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - uint32_t wordCount; - uint32_t numWords; - uint32_t pageWords; - uint32_t* pData; - bool wasLocked; - MSC_Status_TypeDef retval = mscReturnOk; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* Check alignment (must be aligned to words). */ - EFM_ASSERT(((uint32_t) address & 0x3) == 0); - - /* Check a number of bytes. Must be divisible by four. */ - EFM_ASSERT((numBytes & 0x3) == 0); - -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done and flash write requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Convert bytes to words. */ - numWords = numBytes >> 2; - EFM_ASSERT(numWords > 0); - - /* The following loop splits the data into chunks corresponding to flash pages. - The address is loaded only once per page because the hardware automatically - increments the address internally for each data load inside a page. */ - for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { - /* First, the address is loaded. The address is auto-incremented within a page. - Therefore, the address phase is only needed once for each page. */ - retval = MSC_LoadVerifyAddress(address + wordCount); - if (mscReturnOk != retval) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return retval; - } - /* Compute the number of words to write to the current page. */ - pageWords = - (FLASH_PAGE_SIZE - - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) - / sizeof(uint32_t); - if (pageWords > numWords - wordCount) { - pageWords = numWords - wordCount; - } - /* Write the data in the current page. */ - retval = MSC_LoadWriteData(pData, pageWords); - if (mscReturnOk != retval) { - break; - } - wordCount += pageWords; - pData += pageWords; - } - -#if defined(ERRATA_FIX_FLASH_E201_EN) - /* Fix for errata FLASH_E201 - Potential program failure after Power On. - * - * Check if the first word was programmed correctly. If a failure is detected, - * retry programming of the first word. - * - * A full description of the errata is in the errata document. */ - pData = (uint32_t *) data; - if (*address != *pData) { - retval = MSC_LoadVerifyAddress(address); - if (mscReturnOk == retval) { - retval = MSC_LoadWriteData(pData, 1); - } - } -#endif - - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - -#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) -#if (WORDS_PER_DATA_PHASE == 2) - /* Turn off the double word write cycle support. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; -#endif -#endif - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return retval; -} -MSC_RAMFUNC_DEFINITION_END - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Erases a page in flash memory. - * @note - * For the Gecko family, it is required to run this function from RAM. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, this is - * achieved automatically by using attributes in the function proctype. For Keil - * uVision IDE, define a section called "ram_code" and place this manually in - * the project's scatter file. - * - * @param[in] startAddress - * A pointer to the flash page to erase. Must be aligned to the beginning of the page - * boundary. - * @return - * Returns the status of erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - The operation completed successfully. - * mscReturnInvalidAddr - The operation tried to erase a non-flash area. - * mscReturnLocked - The operation tried to erase a locked area of the flash. - * mscReturnTimeOut - The operation timed out waiting for the flash operation - * to complete. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) -{ - uint32_t timeOut = MSC_PROGRAM_TIMEOUT; - bool wasLocked; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* An address must be aligned to pages. */ - EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done and flash erase requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Load an address. */ - MSC->ADDRB = (uint32_t)startAddress; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - /* Check for an invalid address. */ - if (MSC->STATUS & MSC_STATUS_INVADDR) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnInvalidAddr; - } - - /* Send erase page command. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; - - /* Wait for the erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for write protected page. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnLocked; - } - if (timeOut == 0) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnTimeOut; - } - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnOk; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. This function is interrupt-safe, but slower than - * MSC_WriteWordFast(), which writes to flash with interrupts disabled. - * Write data must be aligned to words and contain a number of bytes that is - * divisible by four. - * @note - * It is recommended to erase the flash page before performing a write. - * - * For the Gecko family, it is required to run this function from RAM. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, - * this is done automatically by using attributes in the function proctype. - * For Keil uVision IDE, define a section called "ram_code" and place it - * manually in the project's scatter file. - * - * This function requires a system core clock at 1 MHz or higher. - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * flashReturnLocked - The operation tried to erase a locked area of the Flash. - * flashReturnTimeOut - The operation timed out waiting for the flash operation - * to complete, or the MSC module timed out waiting for the software to write - * the next word into the DWORD register. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - return MSC_WriteWordI(address, data, numBytes); -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. This function is faster than MSC_WriteWord(), - * but it disables interrupts. Write data must be aligned to words and contain - * a number of bytes that is divisible by four. - * @warning - * This function is only available for certain devices. - * @note - * It is recommended to erase the flash page before performing a write. - * It is required to run this function from RAM on parts that include a - * flash write buffer. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, - * this is done automatically by using attributes in the function proctype. - * For Keil uVision IDE, define a section called "ram_code" and place this manually - * in the project's scatter file. - * - * @deprecated - * This function is deprecated, the functionality is the same as calling - * @ref MSC_WriteWord(). - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * A number of bytes to write from the Flash. NB: Must be divisible by four. - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * flashReturnLocked - The operation tried to erase a locked area of the flash. - * flashReturnTimeOut - The operation timed out waiting for flash operation - * to complete. Or the MSC timed out waiting for the software to write - * the next word into the DWORD register. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - return MSC_WriteWord(address, data, numBytes); -} -MSC_RAMFUNC_DEFINITION_END - -#if (_SILICON_LABS_32B_SERIES > 0) -/***************************************************************************//** - * @brief - * Writes data from RAM to flash memory using the DMA. - * - * @details - * This function uses the LDMA to write data to the internal flash memory. - * This is the fastest way to write data to the flash and should be used when - * the application wants to achieve write speeds like they are reported in the - * datasheet. Note that this function only supports writing data from RAM to - * flash, it does not support writing data from flash to flash. - * - * @note - * This function requires that the LDMA clock is enabled. - * - * @param[in] ch - * DMA channel to use - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * - * @param[in] data - * Data to write to flash. Note that this argument must be an address in RAM. - * This function does not support copying data from flash to flash on series-1 - * devices. Must be aligned to words. - * - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * @endverbatim - ******************************************************************************/ -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes) -{ - uint32_t words = numBytes / 4; - uint32_t burstLen; - uint32_t src = (uint32_t) data; - uint32_t dst = (uint32_t) address; - bool wasLocked; - - EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); - - // Verify that the data argument is in RAM - if (((uint32_t)data < SRAM_BASE) || ((uint32_t)data > (SRAM_BASE + SRAM_SIZE))) { - EFM_ASSERT(false); - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].REQSEL = LDMA_CH_REQSEL_SOURCESEL_MSC - | LDMA_CH_REQSEL_SIGSEL_MSCWDATA; - LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; - LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; - LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Enable writing to the MSC module. - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); - words = burstLen / 4; - - // Load the address. - MSC->ADDRB = dst; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - // Check for an invalid address. - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE - | LDMA_CH_CTRL_SIZE_WORD - | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); - LDMA->CH[ch].SRC = (uint32_t)src; - LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; - - // Enable channel - LDMA->CHEN |= (0x1 << ch); - MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; - - while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { - ; - } - BUS_RegMaskedClear(&LDMA->CHDONE, (0x1 << ch)); - BUS_RegMaskedClear(&LDMA->CHEN, (0x1 << ch)); - - dst += burstLen; - src += burstLen; - numBytes -= burstLen; - } - - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - // Disable writing to the MSC module. - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return mscReturnOk; -} -#endif - -#if defined(_MSC_MASSLOCK_MASK) -SL_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_MassErase(void) -{ - bool wasLocked; - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Unlock the device mass erase. */ - MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; - - /* Erase the first 512 K block. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; - - /* Waiting for erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { - } - -#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) - /* Erase the second 512 K block. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; - - /* Waiting for erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { - } -#endif - - /* Restore the mass erase lock. */ - MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; - - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - /* This will only successfully return if calling function is also in SRAM. */ - return mscReturnOk; -} -SL_RAMFUNC_DEFINITION_END -#endif // defined(_MSC_MASSLOCK_MASK) - -#endif // defined(_SILICON_LABS_32B_SERIES_2) - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_MPAHBRAM_CTRL_MASK) - -/***************************************************************************//** - * @brief - * Read and write existing values in RAM (for ECC initialization). - * - * @details - * This function uses core to load and store the existing data - * values in the given RAM bank. - * - * @param[in] eccBank - * Pointer to ECC RAM bank (MSC_EccBank_Typedef) - ******************************************************************************/ -static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) -{ - volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; - const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); - volatile uint32_t *ctrlreg; - uint32_t enableEcc; - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ctrlreg = &ECC_CTRL0_REG; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ctrlreg = &ECC_CTRL1_REG; - } else { - EFM_ASSERT(0); - return; - } -#else - ctrlreg = &ECC_CTRL_REG; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - - EFM_ASSERT(ramptr < endptr); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - enableEcc = eccBank->initSyndromeEnable; -#elif defined(_MPAHBRAM_CTRL_MASK) - /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes - to be written in ECC */ - enableEcc = eccBank->correctionEnable; - - /* Enable ECC syndrome write */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_CTRL0_REG |= eccBank->initSyndromeEnable; - ECC_IFC0_REG = ECC_IFC_MASK; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_CTRL1_REG |= eccBank->initSyndromeEnable; - ECC_IFC1_REG = ECC_IFC_MASK; - } -#else - ECC_CTRL_REG |= eccBank->initSyndromeEnable; - ECC_IFC_REG = ECC_IFC_MASK; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#endif - -#ifndef __GNUC__ -#define __asm__ asm -#endif - - /* - * Performs a read and write of all RAM address to initialize - * ECC syndromes. ECC is initialized by reading a RAM address - * while ECC is disabled and write it back while ECC is enabled. - * - * HardFault could occur if we try to read values from RAM while ECC - * is enabled and not initialized. In this case, ECC tries to correct the - * value and ended giving the wrong value which could be sometimes an - * non-existing address. - * - * So for ECC initialization to work properly, this must ensures that while - * ECC is enabled, RAM will be accessed only through writes, no reads shall - * occur. It's hard to have such guarantee with C code, because the C - * compiler with optimization settings, can get in the way - * and do some unwanted reads while ECC is enabled. Assembly allows such - * guarantee and let ECC be initialized without triggering errors. - */ - - __asm__ volatile ( - "1:\n\t" /* define label 1 */ - "LDR r1, [%[ramptr]]\n\t" /* load content of ramptr into R1, ECC - is disabled to get a correct value */ - "LDR r0, [%[ctrlreg]]\n\t" /* load ctrlreg content into R0 */ - "ORR r0, r0, %[enableEcc]\n\t" /* OR R0 and enableEcc, and store result - in R0 */ - "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is - enabled from now on */ - "STR r1, [%[ramptr]]\n\t" /* write back ram content where it was, - syndrome will be written in ECC */ - "BIC r0, r0, %[enableEcc]\n\t" /* bit clear enableEcc from R0, and store - result in R0 */ - "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is - disabled */ - "ADDS %[ramptr], %[ramptr], #4\n\t" /* increment ramptr by 4 (size of - a word) */ - "CMP %[ramptr], %[endptr]\n\t" /* compare ramptr and endptr... */ - "BCC 1b\n\t" /* ... and jump back to label 1 if Carrry - Clear (meaning ramptr < endptr) */ - "ORR r0, r0, %[enableEcc]\n\t" /* and re-enable ECC ASAP to be sure no */ - "STR r0, [%[ctrlreg]]\n\t" /* STR occurs with ECC disabled */ - :[ramptr] "+r" (ramptr) - :[endptr] "r" (endptr), - [ctrlreg] "r" (ctrlreg), - [enableEcc] "r" (enableEcc) - : "r0", "r1", /* R0 and R1 used as temporary registers */ - "memory" /* Memory pointed by ramptr is modified */ - ); -} - -#else - -/***************************************************************************//** - * @brief - * DMA read and write existing values (for ECC initialization). - * - * @details - * This function uses DMA to read and write the existing data values in - * the RAM region specified by start and size. The function will use the - * 2 DMA channels specified by the channels[2] array. - * - * @param[in] start - * Start address of address range in RAM to read/write. - * - * @param[in] size - * Size of address range in RAM to read/write. - * - * @param[in] channels[2] - * Array of 2 DMA channels to use. - ******************************************************************************/ -static void mscEccReadWriteExistingDma(uint32_t start, - uint32_t size, - uint32_t channels[2]) -{ - uint32_t descCnt = 0; - volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; - uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); - /* Assert that the 2 DMA channel numbers are different. */ - EFM_ASSERT(channels[0] != channels[1]); - - /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order - to match the total xfer size of the descriptor chain with the largest - ECC RAM bank. */ - EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); - - /* Initialize LDMA descriptor chain. */ - do { - dmaDesc[descCnt][0] = /* DMA desc CTRL word */ - LDMA_CH_CTRL_STRUCTTYPE_TRANSFER - | LDMA_CH_CTRL_STRUCTREQ - | _LDMA_CH_CTRL_XFERCNT_MASK - | LDMA_CH_CTRL_BLOCKSIZE_ALL - | LDMA_CH_CTRL_REQMODE_ALL - | LDMA_CH_CTRL_SRCINC_ONE - | LDMA_CH_CTRL_SIZE_WORD - | LDMA_CH_CTRL_DSTINC_ONE; - - /* source and destination address */ - dmaDesc[descCnt][1] = start; - dmaDesc[descCnt][2] = start; - /* link to next descriptor */ - dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK - | (((uint32_t) &dmaDesc[descCnt + 1][0]) - & _LDMA_CH_LINK_LINKADDR_MASK); - - start += ECC_DMA_DESC_SIZE; - size -= ECC_DMA_DESC_SIZE; - descCnt++; - } while (size); - - /* Make sure descCnt is valid to avoid out-of-bounds access when writing to - dmaDesc array. */ - if ((descCnt < 2) || (descCnt > ECC_DMA_DESCS)) { - while (true) { - EFM_ASSERT(false); - } - } - - /* Now, divide the descriptor list in two parts, one for each channel, - by setting the link bit and address 0 of the descriptor in the middle - to 0. */ - dmaDesc[(descCnt / 2) - 1][3] = 0; - - /* Set last descriptor link bit and address to 0. */ - dmaDesc[descCnt - 1][3] = 0; - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - /* Start the LDMA clock now */ - CMU_ClockEnable(cmuClock_LDMA, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - CMU_ClockEnable(cmuClock_LDMAXBAR, true); -#endif -#endif - /* Round robin scheduling for all channels (0 = no fixed priority channels). - */ - LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; -#if defined(LDMA_EN_EN) - LDMA->EN = LDMA_EN_EN; -#endif - LDMA->CHEN = 0; - LDMA->DBGHALT = 0; - LDMA->REQDIS = 0; - - /* Disable LDMA interrupts, and clear interrupt status. */ - LDMA->IEN = 0; -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chMask; -#else - LDMA->IFC = chMask; -#endif - - /* Disable looping */ - LDMA->CH[channels[0]].LOOP = 0; - LDMA->CH[channels[1]].LOOP = 0; - - /* Set descriptor address for first channel. */ - LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) - & _LDMA_CH_LINK_LINKADDR_MASK; - /* Set descriptor address for second channel. */ - LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) - & _LDMA_CH_LINK_LINKADDR_MASK; - /* Clear the channel done flags. */ - BUS_RegMaskedClear(&LDMA->CHDONE, chMask); - - /* Start transfer by loading descriptors. */ - LDMA->LINKLOAD = chMask; - - /* Wait until finished. */ - while (!( -#if defined(_LDMA_CHSTATUS_MASK) - ((LDMA->CHSTATUS & chMask) == 0) -#else - ((LDMA->CHEN & chMask) == 0) -#endif - && ((LDMA->CHDONE & chMask) == chMask))) { - } - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - /* Stop the LDMA clock now */ - CMU_ClockEnable(cmuClock_LDMA, false); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - CMU_ClockEnable(cmuClock_LDMAXBAR, false); -#endif -#endif -} -#endif // #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_MPAHBRAM_CTRL_MASK) - -/***************************************************************************//** - * @brief - * Initialize ECC for a given memory bank. - * - * @brief - * This function initializes ECC for a given memory bank which is specified - * with the MSC_EccBank_Typedef structure input parameter. - * - * @param[in] eccBank - * ECC memory bank device structure. - * - * @param[in] dmaChannels - * Array of 2 DMA channels that may be used during ECC initialization. - * - ******************************************************************************/ -static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, - uint32_t dmaChannels[2]) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_MPAHBRAM_CTRL_MASK) - (void) dmaChannels; -#if !defined(_MPAHBRAM_CTRL_MASK) - /* Disable ECC write */ - ECC_CTRL_REG &= ~eccBank->initSyndromeEnable; -#endif - /* Initialize ECC syndromes by using core cpu to load and store the existing - data values in RAM. */ - mscEccReadWriteExistingPio(eccBank); -#else - /* Enable ECC write */ - ECC_CTRL_REG |= eccBank->initSyndromeEnable; - /* Initialize ECC syndromes by using DMA to read and write the existing - data values in RAM. */ - mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); -#endif - - /* Clear any ECC errors that may have been reported before or during - initialization. */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_IFC0_REG = ECC_IFC_MASK; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_IFC1_REG = ECC_IFC_MASK; - } -#else - ECC_IFC_REG = ECC_IFC_MASK; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#if !defined(_MPAHBRAM_CTRL_MASK) - /* Enable ECC decoder to detect and report ECC errors. */ - ECC_CTRL_REG |= eccBank->correctionEnable; -#endif - - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * @brief - * Disable ECC for a given memory bank. - * - * @brief - * This function disables ECC for a given memory bank which is specified - * with the MSC_EccBank_Typedef structure input parameter. - * - * @param[in] eccBank - * ECC memory bank device structure. - * - ******************************************************************************/ -static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) -{ - /* Disable ECC write (encoder) and checking (decoder). */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); - } -#else - ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ -} - -/***************************************************************************//** - * @brief - * Configure Error Correcting Code (ECC). - * - * @details - * This function configures ECC support according to the configuration - * input parameter. If the user requests enabling ECC for a given RAM bank - * this function will initialize ECC memory (syndromes) for the bank by - * reading and writing the existing values in memory. I.e. all data is - * preserved. The initialization process runs in a critical section - * disallowing interrupts and thread scheduling, and will consume a - * considerable amount of clock cycles. Therefore the user should carefully - * assess where to call this function. The user can consider to increase - * the clock frequency in order to reduce the execution time. - * This function makes use of 2 DMA channels to move data to/from RAM in an - * efficient way. The user can select which 2 DMA channels to use in order - * to avoid conflicts with the application. However the user must make sure - * that no other DMA operations takes place while this function is executing. - * If the application has been using the DMA controller prior to calling this - * function, the application will need to reinitialize DMA registers after - * this function has completed. - * - * @note - * This function protects the ECC initialization procedure from interrupts - * and other threads by using a critical section (defined by em_core.h) - * When running on RTOS the user may need to override CORE_EnterCritical - * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. - * - * @param[in] eccConfig - * ECC configuration - ******************************************************************************/ -void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) -{ - unsigned int cnt; -#if defined(ECC_FAULT_CTRL_REG) - uint32_t faultCtrlReg = ECC_FAULT_CTRL_REG; - /* Disable ECC faults if ecc fault ctrl register is defined. */ - faultCtrlReg &= ~ECC_FAULT_EN; - ECC_FAULT_CTRL_REG = faultCtrlReg; -#endif - - /* Loop through the ECC banks array, enable or disable according to - the eccConfig->enableEccBank array. */ - for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { - if (eccConfig->enableEccBank[cnt]) { - mscEccBankInit(&eccBankTbl[cnt], eccConfig->dmaChannels); - } else { - mscEccBankDisable(&eccBankTbl[cnt]); - } - } - -#if defined(ECC_FAULT_CTRL_REG) && !defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) - /* - * Enable ECC faults if ecc fault ctrl register is set. - * On Series 1 Config 1, aka EFM32GG11, ECC faults should stay disabled. - * Reload register first, in case it was modified and/or shared by bank - * init functions. - */ - faultCtrlReg = ECC_FAULT_CTRL_REG; - faultCtrlReg |= ECC_FAULT_EN; - ECC_FAULT_CTRL_REG = faultCtrlReg; -#endif -} - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -/***************************************************************************//** - * @brief - * Set MPAHBRAM port to use to access DMEM. - * - * @details - * This function configures which MPAHBRAM slave port is used to access DMEM. - * Depending on the use case, it might improve performance by spreading the - * load over the N ports (N is usually 2 or 4), instead of starving because a - * port is used by another master. - * - * @param[in] master - * AHBHOST master to be configured. - * @param[in] port - * AHBHOST slave port to use. - ******************************************************************************/ -void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port) -{ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - uint32_t bitfieldMask = DMEM_NUM_PORTS - 1; -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1; -#endif - - /* make sure master is within the mask of port map that can be changed - * make sure port is a sensible value - */ - EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0); - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - EFM_ASSERT(port < DMEM_NUM_PORTS); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - EFM_ASSERT(port < DMEM0_NUM_PORTS); -#endif - -#if defined(CMU_CLKEN0_SYSCFG) - bool disableSyscfgClk = false; - - if (!(CMU->CLKEN0 & _CMU_CLKEN0_SYSCFG_MASK)) { - disableSyscfgClk = true; - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - } -#endif - - BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, - bitfieldMask << master, - (uint32_t)port << master); - -#if defined(CMU_CLKEN0_SYSCFG) - if (disableSyscfgClk) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -/***************************************************************************//** - * @brief - * Set MPAHBRAM port priority for arbitration when multiple concurrent - * transactions to DMEM. - * - * @details - * This function configures which MPAHBRAM slave port will have priority. - * The AHB port arbitration default scheme, round-robin arbitration, is - * selected when portPriority == mscPortPriorityNone. - * - * @note - * Doing this can potentially starve the others AHB port(s). - * - * @param[in] portPriority - * AHBHOST slave port having elevated priority. - ******************************************************************************/ -void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority) -{ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); - - BUS_RegMaskedWrite(&DMEM->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); - - BUS_RegMaskedWrite(&DMEM0->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); - BUS_RegMaskedWrite(&DMEM1->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -#endif -} - -/***************************************************************************//** - * @brief - * Get MPAHBRAM port arbitration priority selection. - * - * @details - * This function returns the AHBHOST slave with raised priority. - * - * @return - * Returns the AHBHOST slave port given priority or none. - ******************************************************************************/ -MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void) -{ - uint32_t port = 0; - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - port = BUS_RegMaskedRead(&DMEM->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - port = BUS_RegMaskedRead(&DMEM0->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); -#endif - - return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -} -#endif /* if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) */ - -/** @} (end addtogroup msc) */ -#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Flash controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_msc.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(__ICCARM__) +/* Suppress warnings originating from use of EFM_ASSERT() with IAR Embedded Workbench */ +#pragma diag_suppress=Ta022,Ta023 +#endif + +#if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) +#error "Running Flash write/erase operations from Flash is not supported on EFM32G." +#endif + +/******************************************************************************* + ****************************** DEFINES ****************************** + ******************************************************************************/ +#if defined(MSC_WRITECTRL_WDOUBLE) +#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) +#else +#define WORDS_PER_DATA_PHASE (1) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata FLASH_E201 - Potential program failure after Power On */ +#define ERRATA_FIX_FLASH_E201_EN +#endif + +#define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 + banks (not RAM2). It is necessary to figure out which is biggest to + calculate the number of DMA descriptors needed. */ +#define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and + RAM2 banks. All banks are of equal size. */ +#define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) +#define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) +#define ECC_RAM2_SYNDROMES_INIT (MSC_ECCCTRL_RAM2ECCEWEN) +#define ECC_RAM2_CORRECTION_EN (MSC_ECCCTRL_RAM2ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ + | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN) + +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) + +/* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) + +#define ECC_IF_REG (SYSCFG->IF) +#define ECC_IF_1BIT_ERROR (SYSCFG_IF_RAMERR1B) + +#elif defined(_MPAHBRAM_CTRL_MASK) + +/* From Series 2 Config 3, aka EFR32XG23, ECC is now standalone in the + * MPAHBRAM module */ +#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) +#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) +#endif + +#define ECC_IF_REG (DMEM->IF) +/* number of AHB ports is between 1 and 4 */ +#if defined(MPAHBRAM_IF_AHB3ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B | MPAHBRAM_IF_AHB3ERR1B) +#elif defined(MPAHBRAM_IF_AHB2ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B) +#elif defined(MPAHBRAM_IF_AHB1ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B) +#else +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B) +#endif + +#else + +#error "Unknown device" + +#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */ + +#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + +#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE) +#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE) + +#define ECC_CTRL0_REG (DMEM0->CTRL) +#define ECC_CTRL1_REG (DMEM1->CTRL) + +#define ECC_IFC0_REG (DMEM0->IF_CLR) +#define ECC_IFC1_REG (DMEM1->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) + +#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL) +#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) + +#else + +#define ECC_RAM0_MEM_BASE (SRAM_BASE) +#define ECC_RAM0_MEM_SIZE (SRAM_SIZE) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) +#define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) +#define ECC_IFC_REG (SYSCFG->IF_CLR) +#define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) +#define ECC_FAULT_CTRL_REG (SYSCFG->CTRL) +#define ECC_FAULT_EN (SYSCFG_CTRL_RAMECCERRFAULTEN) + +#elif defined(_MPAHBRAM_CTRL_MASK) +#define ECC_CTRL_REG (DMEM->CTRL) +#define ECC_IFC_REG (DMEM->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) +#define ECC_FAULT_CTRL_REG (DMEM->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) +#endif + +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#else + +#error Unknown device. + +#endif + +#define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ + >> _LDMA_CH_CTRL_XFERCNT_SHIFT) +#define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ + +#define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/***************************************************************************//** + * @brief + * Get locked status of the MSC registers. + * + * @detail + * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions + * that can be placed either in flash or in RAM. + ******************************************************************************/ +#if defined(_MSC_STATUS_REGLOCK_MASK) +#define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) +#else +#define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) +#endif + +/******************************************************************************* + ****************************** TYPEDEFS ****************************** + ******************************************************************************/ + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +typedef struct { + uint32_t initSyndromeEnable; + uint32_t correctionEnable; + uint32_t base; + uint32_t size; +} MSC_EccBank_Typedef; + +#endif + +/******************************************************************************* + ****************************** LOCALS ******************************* + ******************************************************************************/ +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +static const MSC_EccBank_Typedef eccBankTbl[MSC_ECC_BANKS] = +{ + { + ECC_RAM0_SYNDROMES_INIT, ECC_RAM0_CORRECTION_EN, + ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE + }, +#if MSC_ECC_BANKS > 1 + { + ECC_RAM1_SYNDROMES_INIT, ECC_RAM1_CORRECTION_EN, + ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE + }, +#if MSC_ECC_BANKS > 2 + { + ECC_RAM2_SYNDROMES_INIT, ECC_RAM2_CORRECTION_EN, + ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE + }, +#endif +#endif +}; +#endif + +/******************************************************************************* + ****************************** FUNCTIONS ****************************** + ******************************************************************************/ +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadWriteData(uint32_t* data, + uint32_t numWords); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadVerifyAddress(uint32_t* address); + +/** @endcond */ + +/***************************************************************************//** + * @addtogroup msc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for a specified MSC status or timeout. + * + * @param[in] mask + * MSC->STATUS register mask to apply when testing for specified status. + * @param[in] value + * The value the MSC->STATUS test is waiting to see. + * @return + * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Specified status criteria fulfilled. + * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * write or erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + + while (timeOut) { + uint32_t status = MSC->STATUS; + + /* if INVADDR is asserted by MSC, BUSY will never go high, can be checked early */ + if (status & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + /* + * if requested operation fails because flash is locked, BUSY will be high + * for a few cycles and it's not safe to clear WRITECTRL.WREN during that + * period. mscStatusWait should return only when it's safe to do so. + * + * So if user is checking BUSY flag, make sure it matches user's expected + * value and only then check the lock bits. Otherwise, do check early and + * bail out if necessary. + */ + + if ((!(mask & MSC_STATUS_BUSY)) + && (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK))) { + return mscReturnLocked; + } + + if ((status & mask) == value) { + if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { + return mscReturnLocked; + } else { + return mscReturnOk; + } + } + + timeOut--; + } + + return mscReturnTimeOut; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. It is assumed that start address is word + * aligned and that numBytes is an integer multiple of four, and that the + * write operation does not cross a flash page boundary. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef writeBurst(uint32_t address, + const uint32_t *data, + uint32_t numBytes) +{ + msc_Return_TypeDef retVal; + + MSC->ADDRB = address; + + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + MSC->WDATA = *data++; + numBytes -= 4; + + while (numBytes) { + retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY); + + if (retVal != mscReturnOk) { + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + return retVal; + } + + MSC->WDATA = *data++; + numBytes -= 4; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Initialize MSC module. Puts MSC hw in a known state. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; +} + +/***************************************************************************//** + * @brief + * Turn off MSC flash write enable and lock MSC registers. + ******************************************************************************/ +void MSC_Deinit(void) +{ + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + // Lock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_CLR = CMU_CLKEN1_MSC; +#endif +} + +/***************************************************************************//** + * @brief + * Set MSC code execution configuration + * + * @param[in] execConfig + * Code execution configuration + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_RDATACTRL_DOUTBUFEN) + mscReadCtrl = MSC->RDATACTRL & ~MSC_RDATACTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_RDATACTRL_DOUTBUFEN; + } + + MSC->RDATACTRL = mscReadCtrl; +#elif defined(MSC_READCTRL_DOUTBUFEN) + mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; + } + MSC->READCTRL = mscReadCtrl; +#endif +} + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * @param[in] startAddress + * Pointer to the flash page to erase. Must be aligned to beginning of page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Operation completed successfully. + * mscReturnInvalidAddr - Operation tried to erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + MSC_Status_TypeDef retVal; + bool wasLocked; + + // Address must be aligned to page boundary + EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. Write data must be aligned to words and + * contain a number of bytes that is divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * The Flash memory is organized into 64-bit wide double-words. + * Each 64-bit double-word can be written only twice using burst write + * operation between erasing cycles. The user's application must store data in + * RAM to sustain burst write operation. + * + * EFR32XG21 RevC is not able to program every word twice before the next erase. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t addr; + const uint8_t *pData; + uint32_t burstLen; + MSC_Status_TypeDef retVal = mscReturnOk; + bool wasLocked; + + // Check alignment (must be aligned to words) + EFM_ASSERT(((uint32_t)address & 0x3U) == 0); + // Check number of bytes, must be divisable by four + EFM_ASSERT((numBytes & 0x3U) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + // Enable flash write + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + + addr = (uint32_t)address; + pData = (uint8_t*)data; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); + + if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) + != mscReturnOk) { + break; + } + + addr += burstLen; + pData += burstLen; + numBytes -= burstLen; + } + + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + MSC_Status_TypeDef retVal; + + if (MSC_IS_LOCKED()) { + return mscReturnLocked; + } + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // Set write enable bit + MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; // Enable Write ctrl access + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; // Start Mass erase procedure + retVal = mscStatusWait(MSC_STATUS_BUSY, 0); // Wait for end of busy flag or a problem (INVADDR, LOCK, REGLOCK, TIMEOUT) + MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; // Reenable mass erase lock bit + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Disable Write ctrl access + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that copying data from flash to flash will be slower than + * copying from RAM to flash. So the source data must be in RAM in order to + * see the write speeds similar to the datasheet numbers. + * + * @note + * This function requires that the LDMA and LDMAXBAR clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash and be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + LDMA->EN_SET = 0x1; + LDMAXBAR->CH[ch].REQSEL = LDMAXBAR_CH_REQSEL_SOURCESEL_MSC + | LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN_SET = (0x1 << ch); + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + + LDMA->CHDONE_CLR = (0x1 << ch); + LDMA->CHDIS_SET = (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief + * Enables the flash controller for writing. + * @note + * This function must be called before flash operations when + * AUXHFRCO clock has been changed from a default band. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_MSC_TIMEBASE_MASK) + uint32_t freq, cycles; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done. Flash erase and write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Unlock the MSC module. */ + MSC->LOCK = MSC_UNLOCK_CODE; + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_TIMEBASE_MASK) + /* Configure MSC->TIMEBASE according to a selected frequency. */ + freq = CMU_ClockFreqGet(cmuClock_AUX); + + /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band + is tuned to 1.2 MHz on newer revisions. */ + if (freq > 1200000) { + /* Calculate a number of clock cycles for 1 us as a base period. */ + freq = (freq * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing. */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_1US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } else { + /* Calculate a number of clock cycles for 5 us as a base period. */ + freq = (freq * 5 * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_5US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } +#endif +} + +/***************************************************************************//** + * @brief + * Disables the flash controller for writing. + ******************************************************************************/ +void MSC_Deinit(void) +{ + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + /* Lock the MSC module.*/ + MSC->LOCK = 0; +} + +/***************************************************************************//** + * @brief + * Set the MSC code execution configuration. + * + * @param[in] execConfig + * The code execution configuration. + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; + if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1; + } else { + /* No change needed. */ + } +#endif + + mscReadCtrl = MSC->READCTRL & ~(0 +#if defined(MSC_READCTRL_SCBTP) + | MSC_READCTRL_SCBTP +#endif +#if defined(MSC_READCTRL_USEHPROT) + | MSC_READCTRL_USEHPROT +#endif +#if defined(MSC_READCTRL_PREFETCH) + | MSC_READCTRL_PREFETCH +#endif +#if defined(MSC_READCTRL_ICCDIS) + | MSC_READCTRL_ICCDIS +#endif +#if defined(MSC_READCTRL_AIDIS) + | MSC_READCTRL_AIDIS +#endif +#if defined(MSC_READCTRL_IFCDIS) + | MSC_READCTRL_IFCDIS +#endif + ); + mscReadCtrl |= (0 +#if defined(MSC_READCTRL_SCBTP) + | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) +#endif +#if defined(MSC_READCTRL_USEHPROT) + | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) +#endif +#if defined(MSC_READCTRL_PREFETCH) + | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) +#endif +#if defined(MSC_READCTRL_ICCDIS) + | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) +#endif +#if defined(MSC_READCTRL_AIDIS) + | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) +#endif +#if defined(MSC_READCTRL_IFCDIS) + | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) +#endif + ); + + MSC->READCTRL = mscReadCtrl; +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Perform the address phase of the flash write cycle. + * @details + * This function performs the address phase of a flash write operation by + * writing the given flash address to the ADDRB register and issuing the + * LADDRIM command to load the address. + * @param[in] address + * An address in flash memory. Must be aligned at a 4 byte boundary. + * @return + * Returns the status of the address load operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the Flash. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) +{ + uint32_t timeOut; + + /* Wait for the MSC to become ready. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Load the address. */ + MSC->ADDRB = (uint32_t)address; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Perform a flash data write phase. + * @details + * This function performs the data phase of a flash write operation by loading + * the given number of 32-bit words to the WDATA register. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numWords + * A number of data words (32-bit) to load. + * @return + * Returns the status of the data load operation. + * @verbatim + * mscReturnOk - An operation completed successfully. + * mscReturnTimeOut - An operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, + uint32_t numWords) +{ + uint32_t timeOut; + uint32_t wordIndex; + bool useWDouble = false; + MSC_Status_TypeDef retval = mscReturnOk; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ + if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { + /* If the number of words to be written is odd, align by writing + a single word first, before setting the WDOUBLE bit. */ + if (numWords & 0x1) { + /* Wait for the MSC to become ready for the next word. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + + /* Clear the double word option to write the initial single word. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; + /* Write first data word. */ + MSC->WDATA = *data++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + + /* Wait for the operation to finish. It may be required to change the WDOUBLE + configuration after the initial write. It should not be changed while BUSY. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + return mscReturnLocked; + } + /* Subtract this initial odd word for the write loop below. */ + numWords -= 1; + retval = mscReturnOk; + } + /* Set the double word option to write two words per + data phase. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; + useWDouble = true; + } +#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ + + /* Write the rest as a double word write if wordsPerDataPhase == 2 */ + if (numWords > 0) { + /* Requires a system core clock at 1MHz or higher */ + EFM_ASSERT(SystemCoreClock >= 1000000); + wordIndex = 0; + while (wordIndex < numWords) { + if (!useWDouble) { + MSC->WDATA = *data++; + wordIndex++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + } else { + /* Trigger a double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + MSC->WDATA = *data++; + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; + MSC->WDATA = *data++; + wordIndex += 2; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; +#endif + } + + /* Wait for the transaction to finish. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for a timeout. */ + if (timeOut == 0) { + retval = mscReturnTimeOut; + break; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + retval = mscReturnLocked; + break; + } +#if defined(_EFM32_GECKO_FAMILY) + MSC->ADDRB += 4; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; +#endif + } + } + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* Clear a double word option, which should not be left on when returning. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif + + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * An internal flash write function. + * @param[in] address + * A write address. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numBytes + * A nsumber of data bytes to load, which must be a multiple of 4 bytes. + * @return + * Returns the status of the data load operation. + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t wordCount; + uint32_t numWords; + uint32_t pageWords; + uint32_t* pData; + bool wasLocked; + MSC_Status_TypeDef retval = mscReturnOk; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Check alignment (must be aligned to words). */ + EFM_ASSERT(((uint32_t) address & 0x3) == 0); + + /* Check a number of bytes. Must be divisible by four. */ + EFM_ASSERT((numBytes & 0x3) == 0); + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Convert bytes to words. */ + numWords = numBytes >> 2; + EFM_ASSERT(numWords > 0); + + /* The following loop splits the data into chunks corresponding to flash pages. + The address is loaded only once per page because the hardware automatically + increments the address internally for each data load inside a page. */ + for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { + /* First, the address is loaded. The address is auto-incremented within a page. + Therefore, the address phase is only needed once for each page. */ + retval = MSC_LoadVerifyAddress(address + wordCount); + if (mscReturnOk != retval) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; + } + /* Compute the number of words to write to the current page. */ + pageWords = + (FLASH_PAGE_SIZE + - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) + / sizeof(uint32_t); + if (pageWords > numWords - wordCount) { + pageWords = numWords - wordCount; + } + /* Write the data in the current page. */ + retval = MSC_LoadWriteData(pData, pageWords); + if (mscReturnOk != retval) { + break; + } + wordCount += pageWords; + pData += pageWords; + } + +#if defined(ERRATA_FIX_FLASH_E201_EN) + /* Fix for errata FLASH_E201 - Potential program failure after Power On. + * + * Check if the first word was programmed correctly. If a failure is detected, + * retry programming of the first word. + * + * A full description of the errata is in the errata document. */ + pData = (uint32_t *) data; + if (*address != *pData) { + retval = MSC_LoadVerifyAddress(address); + if (mscReturnOk == retval) { + retval = MSC_LoadWriteData(pData, 1); + } + } +#endif + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) +#if (WORDS_PER_DATA_PHASE == 2) + /* Turn off the double word write cycle support. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif +#endif + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * @note + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, this is + * achieved automatically by using attributes in the function proctype. For Keil + * uVision IDE, define a section called "ram_code" and place this manually in + * the project's scatter file. + * + * @param[in] startAddress + * A pointer to the flash page to erase. Must be aligned to the beginning of the page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the flash. + * mscReturnTimeOut - The operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + bool wasLocked; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* An address must be aligned to pages. */ + EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash erase requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Load an address. */ + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnInvalidAddr; + } + + /* Send erase page command. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + /* Wait for the erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for write protected page. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnLocked; + } + if (timeOut == 0) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnTimeOut; + } + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is interrupt-safe, but slower than + * MSC_WriteWordFast(), which writes to flash with interrupts disabled. + * Write data must be aligned to words and contain a number of bytes that is + * divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place it + * manually in the project's scatter file. + * + * This function requires a system core clock at 1 MHz or higher. + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the Flash. + * flashReturnTimeOut - The operation timed out waiting for the flash operation + * to complete, or the MSC module timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWordI(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is faster than MSC_WriteWord(), + * but it disables interrupts. Write data must be aligned to words and contain + * a number of bytes that is divisible by four. + * @warning + * This function is only available for certain devices. + * @note + * It is recommended to erase the flash page before performing a write. + * It is required to run this function from RAM on parts that include a + * flash write buffer. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place this manually + * in the project's scatter file. + * + * @deprecated + * This function is deprecated, the functionality is the same as calling + * @ref MSC_WriteWord(). + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from the Flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the flash. + * flashReturnTimeOut - The operation timed out waiting for flash operation + * to complete. Or the MSC timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWord(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +#if (_SILICON_LABS_32B_SERIES > 0) +/***************************************************************************//** + * @brief + * Writes data from RAM to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that this function only supports writing data from RAM to + * flash, it does not support writing data from flash to flash. + * + * @note + * This function requires that the LDMA clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash. Note that this argument must be an address in RAM. + * This function does not support copying data from flash to flash on series-1 + * devices. Must be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + // Verify that the data argument is in RAM + if (((uint32_t)data < SRAM_BASE) || ((uint32_t)data > (SRAM_BASE + SRAM_SIZE))) { + EFM_ASSERT(false); + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].REQSEL = LDMA_CH_REQSEL_SOURCESEL_MSC + | LDMA_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN |= (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + BUS_RegMaskedClear(&LDMA->CHDONE, (0x1 << ch)); + BUS_RegMaskedClear(&LDMA->CHEN, (0x1 << ch)); + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} +#endif + +#if defined(_MSC_MASSLOCK_MASK) +SL_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + bool wasLocked; + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Unlock the device mass erase. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; + + /* Erase the first 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } + +#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) + /* Erase the second 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } +#endif + + /* Restore the mass erase lock. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + /* This will only successfully return if calling function is also in SRAM. */ + return mscReturnOk; +} +SL_RAMFUNC_DEFINITION_END +#endif // defined(_MSC_MASSLOCK_MASK) + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Read and write existing values in RAM (for ECC initialization). + * + * @details + * This function uses core to load and store the existing data + * values in the given RAM bank. + * + * @param[in] eccBank + * Pointer to ECC RAM bank (MSC_EccBank_Typedef) + ******************************************************************************/ +static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) +{ + volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; + const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); + volatile uint32_t *ctrlreg; + uint32_t enableEcc; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ctrlreg = &ECC_CTRL0_REG; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ctrlreg = &ECC_CTRL1_REG; + } else { + EFM_ASSERT(0); + return; + } +#else + ctrlreg = &ECC_CTRL_REG; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + + EFM_ASSERT(ramptr < endptr); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + enableEcc = eccBank->initSyndromeEnable; +#elif defined(_MPAHBRAM_CTRL_MASK) + /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes + to be written in ECC */ + enableEcc = eccBank->correctionEnable; + + /* Enable ECC syndrome write */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG |= eccBank->initSyndromeEnable; + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG |= eccBank->initSyndromeEnable; + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#endif + +#ifndef __GNUC__ +#define __asm__ asm +#endif + + /* + * Performs a read and write of all RAM address to initialize + * ECC syndromes. ECC is initialized by reading a RAM address + * while ECC is disabled and write it back while ECC is enabled. + * + * HardFault could occur if we try to read values from RAM while ECC + * is enabled and not initialized. In this case, ECC tries to correct the + * value and ended giving the wrong value which could be sometimes an + * non-existing address. + * + * So for ECC initialization to work properly, this must ensures that while + * ECC is enabled, RAM will be accessed only through writes, no reads shall + * occur. It's hard to have such guarantee with C code, because the C + * compiler with optimization settings, can get in the way + * and do some unwanted reads while ECC is enabled. Assembly allows such + * guarantee and let ECC be initialized without triggering errors. + */ + + __asm__ volatile ( + "1:\n\t" /* define label 1 */ + "LDR r1, [%[ramptr]]\n\t" /* load content of ramptr into R1, ECC + is disabled to get a correct value */ + "LDR r0, [%[ctrlreg]]\n\t" /* load ctrlreg content into R0 */ + "ORR r0, r0, %[enableEcc]\n\t" /* OR R0 and enableEcc, and store result + in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + enabled from now on */ + "STR r1, [%[ramptr]]\n\t" /* write back ram content where it was, + syndrome will be written in ECC */ + "BIC r0, r0, %[enableEcc]\n\t" /* bit clear enableEcc from R0, and store + result in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + disabled */ + "ADDS %[ramptr], %[ramptr], #4\n\t" /* increment ramptr by 4 (size of + a word) */ + "CMP %[ramptr], %[endptr]\n\t" /* compare ramptr and endptr... */ + "BCC 1b\n\t" /* ... and jump back to label 1 if Carrry + Clear (meaning ramptr < endptr) */ + "ORR r0, r0, %[enableEcc]\n\t" /* and re-enable ECC ASAP to be sure no */ + "STR r0, [%[ctrlreg]]\n\t" /* STR occurs with ECC disabled */ + :[ramptr] "+r" (ramptr) + :[endptr] "r" (endptr), + [ctrlreg] "r" (ctrlreg), + [enableEcc] "r" (enableEcc) + : "r0", "r1", /* R0 and R1 used as temporary registers */ + "memory" /* Memory pointed by ramptr is modified */ + ); +} + +#else + +/***************************************************************************//** + * @brief + * DMA read and write existing values (for ECC initialization). + * + * @details + * This function uses DMA to read and write the existing data values in + * the RAM region specified by start and size. The function will use the + * 2 DMA channels specified by the channels[2] array. + * + * @param[in] start + * Start address of address range in RAM to read/write. + * + * @param[in] size + * Size of address range in RAM to read/write. + * + * @param[in] channels[2] + * Array of 2 DMA channels to use. + ******************************************************************************/ +static void mscEccReadWriteExistingDma(uint32_t start, + uint32_t size, + uint32_t channels[2]) +{ + uint32_t descCnt = 0; + volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; + uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); + /* Assert that the 2 DMA channel numbers are different. */ + EFM_ASSERT(channels[0] != channels[1]); + + /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order + to match the total xfer size of the descriptor chain with the largest + ECC RAM bank. */ + EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); + + /* Initialize LDMA descriptor chain. */ + do { + dmaDesc[descCnt][0] = /* DMA desc CTRL word */ + LDMA_CH_CTRL_STRUCTTYPE_TRANSFER + | LDMA_CH_CTRL_STRUCTREQ + | _LDMA_CH_CTRL_XFERCNT_MASK + | LDMA_CH_CTRL_BLOCKSIZE_ALL + | LDMA_CH_CTRL_REQMODE_ALL + | LDMA_CH_CTRL_SRCINC_ONE + | LDMA_CH_CTRL_SIZE_WORD + | LDMA_CH_CTRL_DSTINC_ONE; + + /* source and destination address */ + dmaDesc[descCnt][1] = start; + dmaDesc[descCnt][2] = start; + /* link to next descriptor */ + dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK + | (((uint32_t) &dmaDesc[descCnt + 1][0]) + & _LDMA_CH_LINK_LINKADDR_MASK); + + start += ECC_DMA_DESC_SIZE; + size -= ECC_DMA_DESC_SIZE; + descCnt++; + } while (size); + + /* Make sure descCnt is valid to avoid out-of-bounds access when writing to + dmaDesc array. */ + if ((descCnt < 2) || (descCnt > ECC_DMA_DESCS)) { + while (true) { + EFM_ASSERT(false); + } + } + + /* Now, divide the descriptor list in two parts, one for each channel, + by setting the link bit and address 0 of the descriptor in the middle + to 0. */ + dmaDesc[(descCnt / 2) - 1][3] = 0; + + /* Set last descriptor link bit and address to 0. */ + dmaDesc[descCnt - 1][3] = 0; + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Start the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif +#endif + /* Round robin scheduling for all channels (0 = no fixed priority channels). + */ + LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + LDMA->CHEN = 0; + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Disable LDMA interrupts, and clear interrupt status. */ + LDMA->IEN = 0; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + + /* Disable looping */ + LDMA->CH[channels[0]].LOOP = 0; + LDMA->CH[channels[1]].LOOP = 0; + + /* Set descriptor address for first channel. */ + LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Set descriptor address for second channel. */ + LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Clear the channel done flags. */ + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); + + /* Start transfer by loading descriptors. */ + LDMA->LINKLOAD = chMask; + + /* Wait until finished. */ + while (!( +#if defined(_LDMA_CHSTATUS_MASK) + ((LDMA->CHSTATUS & chMask) == 0) +#else + ((LDMA->CHEN & chMask) == 0) +#endif + && ((LDMA->CHDONE & chMask) == chMask))) { + } + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Stop the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +#endif +} +#endif // #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Initialize ECC for a given memory bank. + * + * @brief + * This function initializes ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + * @param[in] dmaChannels + * Array of 2 DMA channels that may be used during ECC initialization. + * + ******************************************************************************/ +static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, + uint32_t dmaChannels[2]) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_MPAHBRAM_CTRL_MASK) + (void) dmaChannels; +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Disable ECC write */ + ECC_CTRL_REG &= ~eccBank->initSyndromeEnable; +#endif + /* Initialize ECC syndromes by using core cpu to load and store the existing + data values in RAM. */ + mscEccReadWriteExistingPio(eccBank); +#else + /* Enable ECC write */ + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + /* Initialize ECC syndromes by using DMA to read and write the existing + data values in RAM. */ + mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); +#endif + + /* Clear any ECC errors that may have been reported before or during + initialization. */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Enable ECC decoder to detect and report ECC errors. */ + ECC_CTRL_REG |= eccBank->correctionEnable; +#endif + + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Disable ECC for a given memory bank. + * + * @brief + * This function disables ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + ******************************************************************************/ +static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) +{ + /* Disable ECC write (encoder) and checking (decoder). */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } +#else + ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ +} + +/***************************************************************************//** + * @brief + * Configure Error Correcting Code (ECC). + * + * @details + * This function configures ECC support according to the configuration + * input parameter. If the user requests enabling ECC for a given RAM bank + * this function will initialize ECC memory (syndromes) for the bank by + * reading and writing the existing values in memory. I.e. all data is + * preserved. The initialization process runs in a critical section + * disallowing interrupts and thread scheduling, and will consume a + * considerable amount of clock cycles. Therefore the user should carefully + * assess where to call this function. The user can consider to increase + * the clock frequency in order to reduce the execution time. + * This function makes use of 2 DMA channels to move data to/from RAM in an + * efficient way. The user can select which 2 DMA channels to use in order + * to avoid conflicts with the application. However the user must make sure + * that no other DMA operations takes place while this function is executing. + * If the application has been using the DMA controller prior to calling this + * function, the application will need to reinitialize DMA registers after + * this function has completed. + * + * @note + * This function protects the ECC initialization procedure from interrupts + * and other threads by using a critical section (defined by em_core.h) + * When running on RTOS the user may need to override CORE_EnterCritical + * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. + * + * @param[in] eccConfig + * ECC configuration + ******************************************************************************/ +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) +{ + unsigned int cnt; +#if defined(ECC_FAULT_CTRL_REG) + uint32_t faultCtrlReg = ECC_FAULT_CTRL_REG; + /* Disable ECC faults if ecc fault ctrl register is defined. */ + faultCtrlReg &= ~ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif + + /* Loop through the ECC banks array, enable or disable according to + the eccConfig->enableEccBank array. */ + for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { + if (eccConfig->enableEccBank[cnt]) { + mscEccBankInit(&eccBankTbl[cnt], eccConfig->dmaChannels); + } else { + mscEccBankDisable(&eccBankTbl[cnt]); + } + } + +#if defined(ECC_FAULT_CTRL_REG) && !defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) + /* + * Enable ECC faults if ecc fault ctrl register is set. + * On Series 1 Config 1, aka EFM32GG11, ECC faults should stay disabled. + * Reload register first, in case it was modified and/or shared by bank + * init functions. + */ + faultCtrlReg = ECC_FAULT_CTRL_REG; + faultCtrlReg |= ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif +} + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port to use to access DMEM. + * + * @details + * This function configures which MPAHBRAM slave port is used to access DMEM. + * Depending on the use case, it might improve performance by spreading the + * load over the N ports (N is usually 2 or 4), instead of starving because a + * port is used by another master. + * + * @param[in] master + * AHBHOST master to be configured. + * @param[in] port + * AHBHOST slave port to use. + ******************************************************************************/ +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + uint32_t bitfieldMask = DMEM_NUM_PORTS - 1; +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1; +#endif + + /* make sure master is within the mask of port map that can be changed + * make sure port is a sensible value + */ + EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0); + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(port < DMEM_NUM_PORTS); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(port < DMEM0_NUM_PORTS); +#endif + +#if defined(CMU_CLKEN0_SYSCFG) + bool disableSyscfgClk = false; + + if (!(CMU->CLKEN0 & _CMU_CLKEN0_SYSCFG_MASK)) { + disableSyscfgClk = true; + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + } +#endif + + BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, + bitfieldMask << master, + (uint32_t)port << master); + +#if defined(CMU_CLKEN0_SYSCFG) + if (disableSyscfgClk) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port priority for arbitration when multiple concurrent + * transactions to DMEM. + * + * @details + * This function configures which MPAHBRAM slave port will have priority. + * The AHB port arbitration default scheme, round-robin arbitration, is + * selected when portPriority == mscPortPriorityNone. + * + * @note + * Doing this can potentially starve the others AHB port(s). + * + * @param[in] portPriority + * AHBHOST slave port having elevated priority. + ******************************************************************************/ +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); + BUS_RegMaskedWrite(&DMEM1->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Get MPAHBRAM port arbitration priority selection. + * + * @details + * This function returns the AHBHOST slave with raised priority. + * + * @return + * Returns the AHBHOST slave port given priority or none. + ******************************************************************************/ +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void) +{ + uint32_t port = 0; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + port = BUS_RegMaskedRead(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + port = BUS_RegMaskedRead(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#endif + + return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +} +#endif /* if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) */ + +/** @} (end addtogroup msc) */ +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_opamp.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_opamp.c index d80f485..11eeddf 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_opamp.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_opamp.c @@ -1,700 +1,700 @@ -/***************************************************************************//** - * @file - * @brief Operational Amplifier (OPAMP) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_opamp.h" -#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ - || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) - -#include "em_system.h" -#include "sl_assert.h" - -/* *INDENT-OFF* */ -/***************************************************************************//** - * @addtogroup opamp OPAMP - Operational Amplifier - * @brief Operational Amplifier (OPAMP) peripheral API - * @details - * This module contains functions to: - * @li OPAMP_Enable() Configure and enable OPAMP. - * @li OPAMP_Disable() Disable OPAMP. - * - * @if DOXYDOC_P1_DEVICE - * All OPAMP functions assume that the DAC clock is running. If DAC is not - * used, the clock can be turned off when OPAMPs are configured. - * @elseif DOXYDOC_P2_DEVICE - * All OPAMP functions assume that the VDAC clock is running. If VDAC is not - * used, the clock can be turned off when the OPAMPs are configured. - * @endif - * - * If the available gain values don't suit the application at hand, the resistor - * ladders can be disabled and external gain programming resistors used. - * - * A number of predefined OPAMP setup macros are available for configuration - * of the most common OPAMP topologies (see figures below). - * - * @note - * The terms POSPAD and NEGPAD in the figures are used to indicate that these - * pads should be connected to a suitable signal ground. - * - * \nUnity gain voltage follower.\n - * @if DOXYDOC_P1_DEVICE - * Use predefined macros @ref OPA_INIT_UNITY_GAIN and - * @ref OPA_INIT_UNITY_GAIN_OPA2. - * @elseif DOXYDOC_P2_DEVICE - * Use predefined macro @ref OPA_INIT_UNITY_GAIN. - * @endif - * @verbatim - - |\ - ___________|+\ - | \_______ - ___|_ / | - | | / | - | |/ | - |___________| - @endverbatim - * - * \nNon-inverting amplifier.\n - * @if DOXYDOC_P1_DEVICE - * Use predefined macros @ref OPA_INIT_NON_INVERTING and - * @ref OPA_INIT_NON_INVERTING_OPA2. - * @elseif DOXYDOC_P2_DEVICE - * Use predefined macro @ref OPA_INIT_NON_INVERTING. - * @endif - * @verbatim - - |\ - ___________|+\ - | \_______ - ___|_ / | - | | / | - | |/ | - |_____R2____| - | - R1 - | - NEGPAD @endverbatim - * - * \nInverting amplifier.\n - * @if DOXYDOC_P1_DEVICE - * Use predefined macros @ref OPA_INIT_INVERTING and - * @ref OPA_INIT_INVERTING_OPA2. - * @elseif DOXYDOC_P2_DEVICE - * Use predefined macro @ref OPA_INIT_INVERTING. - * @endif - * @verbatim - - _____R2____ - | | - | |\ | - ____R1_|___|_\ | - | \____|___ - ___| / - | |+/ - | |/ - | - POSPAD @endverbatim - * - * \nCascaded non-inverting amplifiers.\n - * Use predefined macros @ref OPA_INIT_CASCADED_NON_INVERTING_OPA0, - * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA1 and - * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA2. - * @verbatim - - |\ |\ |\ - ___________|+\ OPA0 ___________|+\ OPA1 ___________|+\ OPA2 - | \_________| | \_________| | \_______ - ___|_ / | ___|_ / | ___|_ / | - | | / | | | / | | | / | - | |/ | | |/ | | |/ | - |_____R2____| |_____R2____| |_____R2____| - | | | - R1 R1 R1 - | | | - NEGPAD NEGPAD NEGPAD @endverbatim - * - * \nCascaded inverting amplifiers.\n - * Use predefined macros @ref OPA_INIT_CASCADED_INVERTING_OPA0, - * @ref OPA_INIT_CASCADED_INVERTING_OPA1 and - * @ref OPA_INIT_CASCADED_INVERTING_OPA2. - * @verbatim - - _____R2____ _____R2____ _____R2____ - | | | | | | - | |\ | | |\ | | |\ | - ____R1_|___|_\ | ____R1_|___|_\ | ____R1_|___|_\ | - | \____|____| | \____|___| | \____|__ - ___| / ___| / ___| / - | |+/ OPA0 | |+/ OPA1 | |+/ OPA2 - | |/ | |/ | |/ - | | | - POSPAD POSPAD POSPAD @endverbatim - * - * \nDifferential driver with two opamp's.\n - * Use predefined macros @ref OPA_INIT_DIFF_DRIVER_OPA0 and - * @ref OPA_INIT_DIFF_DRIVER_OPA1. - * @verbatim - - __________________________ - | + - | _____R2____ - |\ | | | - ___________|+\ OPA0 | | |\ OPA1 | - | \_________|____R1_|___|_\ | _ - ___|_ / | | \____|______ - | | / | ___| / - | |/ | | |+/ - |________________| | |/ - | - POSPAD @endverbatim - * - * \nDifferential receiver with three opamp's.\n - * Use predefined macros @ref OPA_INIT_DIFF_RECEIVER_OPA0, - * @ref OPA_INIT_DIFF_RECEIVER_OPA1 and @ref OPA_INIT_DIFF_RECEIVER_OPA2. - * @verbatim - - |\ - __________|+\ OPA1 - _ | \_________ - ___|_ / | | _____R2____ - | | / | | | | - | |/ | | | |\ | - |___________| |____R1_|___|_\ | - | \____|___ - |\ ____R1_ ___| / - +__________|+\ OPA0 | | |+/ OPA2 - | \_________| | |/ - ___|_ / | R2 - | | / | | - | |/ | NEGPAD OPA0 - |___________| - @endverbatim - * - * @if DOXYDOC_P2_DEVICE - * \nInstrumentation amplifier.\n - * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and - * @ref OPA_INIT_INSTR_AMP_OPA1. - * @verbatim - - |\ - __________|+\ OPA1 - | \______________ - ___|_ / | - | | / | - | |/ R2 - |____________| - | - R1 - | - R1 - ____________| - | | - | R2 - | |\ | - |___|+\ OPA0 | - | \_____|________ - __________|_ / - | / - |/ - - @endverbatim - * @endif - * - * @{ - ******************************************************************************/ -/* *INDENT-ON* */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable an Operational Amplifier. - * - * @if DOXYDOC_P1_DEVICE - * @param[in] dac - * A pointer to the DAC peripheral register block. - * @elseif DOXYDOC_P2_DEVICE - * @param[in] dac - * A pointer to the VDAC peripheral register block. - * @endif - * - * @param[in] opa - * Selects an OPA, valid values are OPA0, OPA1, and OPA2. - ******************************************************************************/ -void OPAMP_Disable( -#if defined(_SILICON_LABS_32B_SERIES_0) - DAC_TypeDef *dac, -#elif defined(_SILICON_LABS_32B_SERIES_1) - VDAC_TypeDef *dac, -#endif - OPAMP_TypeDef opa) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - EFM_ASSERT(DAC_REF_VALID(dac)); - EFM_ASSERT(DAC_OPA_VALID(opa)); - - if (opa == OPA0) { - dac->CH0CTRL &= ~DAC_CH0CTRL_EN; - dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN; - } else if (opa == OPA1) { - dac->CH1CTRL &= ~DAC_CH1CTRL_EN; - dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN; - } else { /* OPA2 */ - dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; - } - -#elif defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT(VDAC_REF_VALID(dac)); - EFM_ASSERT(VDAC_OPA_VALID(opa)); - - if (opa == OPA0) { -#if defined(VDAC_STATUS_OPA0ENS) - dac->CMD |= VDAC_CMD_OPA0DIS; - while (dac->STATUS & VDAC_STATUS_OPA0ENS) { - } -#endif -#if defined(VDAC_STATUS_OPA1ENS) - } else if (opa == OPA1) { - dac->CMD |= VDAC_CMD_OPA1DIS; - while (dac->STATUS & VDAC_STATUS_OPA1ENS) { - } -#endif -#if defined(VDAC_STATUS_OPA2ENS) - } else if (opa == OPA2) { - dac->CMD |= VDAC_CMD_OPA2DIS; - while (dac->STATUS & VDAC_STATUS_OPA2ENS) { - } -#endif - } else { /* OPA3 */ -#if defined(VDAC_STATUS_OPA3ENS) - dac->CMD |= VDAC_CMD_OPA3DIS; - while (dac->STATUS & VDAC_STATUS_OPA3ENS) { - } -#endif - } -#endif -} - -/***************************************************************************//** - * @brief - * Configure and enable an Operational Amplifier. - * - * @if DOXYDOC_P1_DEVICE - * @note - * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef - * structure should consist of one or more of the - * DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags - * (defined in \_dac.h) OR'ed together. @n @n - * For OPA0: - * @li DAC_OPA0MUX_OUTPEN_OUT0 - * @li DAC_OPA0MUX_OUTPEN_OUT1 - * @li DAC_OPA0MUX_OUTPEN_OUT2 - * @li DAC_OPA0MUX_OUTPEN_OUT3 - * @li DAC_OPA0MUX_OUTPEN_OUT4 - * - * For OPA1: - * @li DAC_OPA1MUX_OUTPEN_OUT0 - * @li DAC_OPA1MUX_OUTPEN_OUT1 - * @li DAC_OPA1MUX_OUTPEN_OUT2 - * @li DAC_OPA1MUX_OUTPEN_OUT3 - * @li DAC_OPA1MUX_OUTPEN_OUT4 - * - * For OPA2: - * @li DAC_OPA2MUX_OUTPEN_OUT0 - * @li DAC_OPA2MUX_OUTPEN_OUT1 - * - * E.g: @n - * init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT4; - * - * @param[in] dac - * A pointer to the DAC peripheral register block. - * @elseif DOXYDOC_P2_DEVICE - * @note - * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef - * structure should consist of one or more of the - * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags - * (defined in \_vdac.h) OR'ed together. @n @n - * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 - * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 - * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 - * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 - * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 - * - * For example: @n - * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; - * @param[in] dac - * A pointer to the VDAC peripheral register block. - * @endif - * - * @param[in] opa - * Selects an OPA, valid values are OPA0, OPA1, and OPA2. - * - * @param[in] init - * A pointer to a structure containing OPAMP initialization information. - ******************************************************************************/ -void OPAMP_Enable( -#if defined(_SILICON_LABS_32B_SERIES_0) - DAC_TypeDef *dac, -#elif defined(_SILICON_LABS_32B_SERIES_1) - VDAC_TypeDef *dac, -#endif - OPAMP_TypeDef opa, - const OPAMP_Init_TypeDef *init) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - uint32_t gain; - - EFM_ASSERT(DAC_REF_VALID(dac)); - EFM_ASSERT(DAC_OPA_VALID(opa)); - EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK - >> _DAC_BIASPROG_BIASPROG_SHIFT)); - - if (opa == OPA0) { - EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0); - - dac->BIASPROG = (dac->BIASPROG - & ~(_DAC_BIASPROG_BIASPROG_MASK - | DAC_BIASPROG_HALFBIAS)) - | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) - | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); - - if (init->defaultOffset) { - gain = dac->CAL & _DAC_CAL_GAIN_MASK; - SYSTEM_GetCalibrationValue(&dac->CAL); - dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; - } else { - EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK - >> _DAC_CAL_CH0OFFSET_SHIFT)); - - dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK) - | (init->offset << _DAC_CAL_CH0OFFSET_SHIFT); - } - - dac->OPA0MUX = (uint32_t)init->resSel - | (uint32_t)init->outMode - | init->outPen - | (uint32_t)init->resInMux - | (uint32_t)init->negSel - | (uint32_t)init->posSel - | (init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0) - | (init->npEn ? DAC_OPA0MUX_NPEN : 0) - | (init->ppEn ? DAC_OPA0MUX_PPEN : 0); - - dac->CH0CTRL |= DAC_CH0CTRL_EN; - dac->OPACTRL = (dac->OPACTRL - & ~(DAC_OPACTRL_OPA0SHORT - | _DAC_OPACTRL_OPA0LPFDIS_MASK - | DAC_OPACTRL_OPA0HCMDIS)) - | (init->shortInputs ? DAC_OPACTRL_OPA0SHORT : 0) - | (init->lpfPosPadDisable - ? DAC_OPACTRL_OPA0LPFDIS_PLPFDIS : 0) - | (init->lpfNegPadDisable - ? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0) - | (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0) - | DAC_OPACTRL_OPA0EN; - } else if ( opa == OPA1 ) { - EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0); - - dac->BIASPROG = (dac->BIASPROG - & ~(_DAC_BIASPROG_BIASPROG_MASK - | DAC_BIASPROG_HALFBIAS)) - | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) - | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); - - if (init->defaultOffset) { - gain = dac->CAL & _DAC_CAL_GAIN_MASK; - SYSTEM_GetCalibrationValue(&dac->CAL); - dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; - } else { - EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK - >> _DAC_CAL_CH1OFFSET_SHIFT)); - - dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK) - | (init->offset << _DAC_CAL_CH1OFFSET_SHIFT); - } - - dac->OPA1MUX = (uint32_t)init->resSel - | (uint32_t)init->outMode - | init->outPen - | (uint32_t)init->resInMux - | (uint32_t)init->negSel - | (uint32_t)init->posSel - | (init->nextOut ? DAC_OPA1MUX_NEXTOUT : 0) - | (init->npEn ? DAC_OPA1MUX_NPEN : 0) - | (init->ppEn ? DAC_OPA1MUX_PPEN : 0); - - dac->CH1CTRL |= DAC_CH1CTRL_EN; - dac->OPACTRL = (dac->OPACTRL - & ~(DAC_OPACTRL_OPA1SHORT - | _DAC_OPACTRL_OPA1LPFDIS_MASK - | DAC_OPACTRL_OPA1HCMDIS)) - | (init->shortInputs ? DAC_OPACTRL_OPA1SHORT : 0) - | (init->lpfPosPadDisable - ? DAC_OPACTRL_OPA1LPFDIS_PLPFDIS : 0) - | (init->lpfNegPadDisable - ? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0) - | (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0) - | DAC_OPACTRL_OPA1EN; - } else { /* OPA2 */ - EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE) - || (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD) - || (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP) - || (init->posSel == DAC_OPA2MUX_POSSEL_OPATAP)); - - EFM_ASSERT((init->outMode & ~DAC_OPA2MUX_OUTMODE) == 0); - - EFM_ASSERT((init->outPen & ~_DAC_OPA2MUX_OUTPEN_MASK) == 0); - - dac->BIASPROG = (dac->BIASPROG - & ~(_DAC_BIASPROG_OPA2BIASPROG_MASK - | DAC_BIASPROG_OPA2HALFBIAS)) - | (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT) - | (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0); - - if (init->defaultOffset) { - SYSTEM_GetCalibrationValue(&dac->OPAOFFSET); - } else { - EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK - >> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT)); - dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK) - | (init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT); - } - - dac->OPA2MUX = (uint32_t)init->resSel - | (uint32_t)init->outMode - | init->outPen - | (uint32_t)init->resInMux - | (uint32_t)init->negSel - | (uint32_t)init->posSel - | (init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0) - | (init->npEn ? DAC_OPA2MUX_NPEN : 0) - | (init->ppEn ? DAC_OPA2MUX_PPEN : 0); - - dac->OPACTRL = (dac->OPACTRL - & ~(DAC_OPACTRL_OPA2SHORT - | _DAC_OPACTRL_OPA2LPFDIS_MASK - | DAC_OPACTRL_OPA2HCMDIS)) - | (init->shortInputs ? DAC_OPACTRL_OPA2SHORT : 0) - | (init->lpfPosPadDisable - ? DAC_OPACTRL_OPA2LPFDIS_PLPFDIS : 0) - | (init->lpfNegPadDisable - ? DAC_OPACTRL_OPA2LPFDIS_NLPFDIS : 0) - | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) - | DAC_OPACTRL_OPA2EN; - } - -#elif defined(_SILICON_LABS_32B_SERIES_1) - uint32_t calData = 0; - uint32_t warmupTime; - - EFM_ASSERT(VDAC_REF_VALID(dac)); - EFM_ASSERT(VDAC_OPA_VALID(opa)); - EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK - >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); - EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK - >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); - EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); - EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) - || (init->drvStr == opaDrvStrLowAccLowStr) - || (init->drvStr == opaDrvStrHighAccHighStr) - || (init->drvStr == opaDrvStrHigherAccHighStr)); - - /* Disable OPAMP before writing to registers. */ - OPAMP_Disable(dac, opa); - - /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ - switch (opa) { -#if defined(VDAC_STATUS_OPA0ENS) - case OPA0: - switch (init->drvStr) { - case opaDrvStrLowerAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); - break; - case opaDrvStrLowAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); - break; - case opaDrvStrHighAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); - break; - case opaDrvStrHigherAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); - break; - } - break; -#endif - -#if defined(VDAC_STATUS_OPA1ENS) - case OPA1: - switch (init->drvStr) { - case opaDrvStrLowerAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); - break; - case opaDrvStrLowAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); - break; - case opaDrvStrHighAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); - break; - case opaDrvStrHigherAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); - break; - } - break; -#endif - -#if defined(VDAC_STATUS_OPA2ENS) - case OPA2: - switch (init->drvStr) { - case opaDrvStrLowerAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); - break; - case opaDrvStrLowAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); - break; - case opaDrvStrHighAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); - break; - case opaDrvStrHigherAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); - break; - } - break; -#endif - -#if defined(VDAC_STATUS_OPA3ENS) - case OPA3: - switch (init->drvStr) { - case opaDrvStrLowerAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA3CAL0 : DEVINFO->OPA3CAL4); - break; - case opaDrvStrLowAccLowStr: - calData = (init->ugBwScale ? DEVINFO->OPA3CAL1 : DEVINFO->OPA3CAL5); - break; - case opaDrvStrHighAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA3CAL2 : DEVINFO->OPA3CAL6); - break; - case opaDrvStrHigherAccHighStr: - calData = (init->ugBwScale ? DEVINFO->OPA3CAL3 : DEVINFO->OPA3CAL7); - break; - } - break; -#endif - } - if (!init->defaultOffsetN) { - EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK - >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); - calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) - | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); - } - if (!init->defaultOffsetP) { - EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK - >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); - calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) - | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); - } - - dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); - - dac->OPA[opa].MUX = (uint32_t)init->resSel - | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) - | (uint32_t)init->resInMux - | (uint32_t)init->negSel - | (uint32_t)init->posSel; - - dac->OPA[opa].OUT = (uint32_t)init->outMode - | (uint32_t)init->outPen; - - switch (init->drvStr) { - case opaDrvStrHigherAccHighStr: - warmupTime = 6; - break; - - case opaDrvStrHighAccHighStr: - warmupTime = 8; - break; - - case opaDrvStrLowAccLowStr: - warmupTime = 85; - break; - - case opaDrvStrLowerAccLowStr: - default: - warmupTime = 100; - break; - } - - dac->OPA[opa].TIMER = (uint32_t)(init->settleTime - << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) - | (uint32_t)(warmupTime - << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) - | (uint32_t)(init->startupDly - << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); - - dac->OPA[opa].CTRL = (init->aportYMasterDisable - ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) - | (init->aportXMasterDisable - ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) - | (uint32_t)init->prsOutSel - | (uint32_t)init->prsSel - | (uint32_t)init->prsMode - | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) - | (init->halfDrvStr - ? VDAC_OPA_CTRL_OUTSCALE_HALF - : VDAC_OPA_CTRL_OUTSCALE_FULL) - | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) - | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) - | (uint32_t)init->drvStr; - - if (opa == OPA0) { -#if defined(VDAC_STATUS_OPA0ENS) - dac->CMD |= VDAC_CMD_OPA0EN; -#endif -#if defined(VDAC_STATUS_OPA1ENS) - } else if (opa == OPA1) { - dac->CMD |= VDAC_CMD_OPA1EN; -#endif -#if defined(VDAC_STATUS_OPA2ENS) - } else if (opa == OPA2) { - dac->CMD |= VDAC_CMD_OPA2EN; -#endif -#if defined(VDAC_STATUS_OPA3ENS) - } else { /* OPA3 */ - dac->CMD |= VDAC_CMD_OPA3EN; -#endif - } - -#endif -} - -/** @} (end addtogroup opamp) */ - -#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) - || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Operational Amplifier (OPAMP) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_opamp.h" +#if ((defined(_SILICON_LABS_32B_SERIES_0) && defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1)) \ + || (defined(_SILICON_LABS_32B_SERIES_1) && defined(VDAC_PRESENT) && (VDAC_COUNT > 0))) + +#include "em_system.h" +#include "sl_assert.h" + +/* *INDENT-OFF* */ +/***************************************************************************//** + * @addtogroup opamp OPAMP - Operational Amplifier + * @brief Operational Amplifier (OPAMP) peripheral API + * @details + * This module contains functions to: + * @li OPAMP_Enable() Configure and enable OPAMP. + * @li OPAMP_Disable() Disable OPAMP. + * + * @if DOXYDOC_P1_DEVICE + * All OPAMP functions assume that the DAC clock is running. If DAC is not + * used, the clock can be turned off when OPAMPs are configured. + * @elseif DOXYDOC_P2_DEVICE + * All OPAMP functions assume that the VDAC clock is running. If VDAC is not + * used, the clock can be turned off when the OPAMPs are configured. + * @endif + * + * If the available gain values don't suit the application at hand, the resistor + * ladders can be disabled and external gain programming resistors used. + * + * A number of predefined OPAMP setup macros are available for configuration + * of the most common OPAMP topologies (see figures below). + * + * @note + * The terms POSPAD and NEGPAD in the figures are used to indicate that these + * pads should be connected to a suitable signal ground. + * + * \nUnity gain voltage follower.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_UNITY_GAIN and + * @ref OPA_INIT_UNITY_GAIN_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_UNITY_GAIN. + * @endif + * @verbatim + + |\ + ___________|+\ + | \_______ + ___|_ / | + | | / | + | |/ | + |___________| + @endverbatim + * + * \nNon-inverting amplifier.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_NON_INVERTING and + * @ref OPA_INIT_NON_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_NON_INVERTING. + * @endif + * @verbatim + + |\ + ___________|+\ + | \_______ + ___|_ / | + | | / | + | |/ | + |_____R2____| + | + R1 + | + NEGPAD @endverbatim + * + * \nInverting amplifier.\n + * @if DOXYDOC_P1_DEVICE + * Use predefined macros @ref OPA_INIT_INVERTING and + * @ref OPA_INIT_INVERTING_OPA2. + * @elseif DOXYDOC_P2_DEVICE + * Use predefined macro @ref OPA_INIT_INVERTING. + * @endif + * @verbatim + + _____R2____ + | | + | |\ | + ____R1_|___|_\ | + | \____|___ + ___| / + | |+/ + | |/ + | + POSPAD @endverbatim + * + * \nCascaded non-inverting amplifiers.\n + * Use predefined macros @ref OPA_INIT_CASCADED_NON_INVERTING_OPA0, + * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA1 and + * @ref OPA_INIT_CASCADED_NON_INVERTING_OPA2. + * @verbatim + + |\ |\ |\ + ___________|+\ OPA0 ___________|+\ OPA1 ___________|+\ OPA2 + | \_________| | \_________| | \_______ + ___|_ / | ___|_ / | ___|_ / | + | | / | | | / | | | / | + | |/ | | |/ | | |/ | + |_____R2____| |_____R2____| |_____R2____| + | | | + R1 R1 R1 + | | | + NEGPAD NEGPAD NEGPAD @endverbatim + * + * \nCascaded inverting amplifiers.\n + * Use predefined macros @ref OPA_INIT_CASCADED_INVERTING_OPA0, + * @ref OPA_INIT_CASCADED_INVERTING_OPA1 and + * @ref OPA_INIT_CASCADED_INVERTING_OPA2. + * @verbatim + + _____R2____ _____R2____ _____R2____ + | | | | | | + | |\ | | |\ | | |\ | + ____R1_|___|_\ | ____R1_|___|_\ | ____R1_|___|_\ | + | \____|____| | \____|___| | \____|__ + ___| / ___| / ___| / + | |+/ OPA0 | |+/ OPA1 | |+/ OPA2 + | |/ | |/ | |/ + | | | + POSPAD POSPAD POSPAD @endverbatim + * + * \nDifferential driver with two opamp's.\n + * Use predefined macros @ref OPA_INIT_DIFF_DRIVER_OPA0 and + * @ref OPA_INIT_DIFF_DRIVER_OPA1. + * @verbatim + + __________________________ + | + + | _____R2____ + |\ | | | + ___________|+\ OPA0 | | |\ OPA1 | + | \_________|____R1_|___|_\ | _ + ___|_ / | | \____|______ + | | / | ___| / + | |/ | | |+/ + |________________| | |/ + | + POSPAD @endverbatim + * + * \nDifferential receiver with three opamp's.\n + * Use predefined macros @ref OPA_INIT_DIFF_RECEIVER_OPA0, + * @ref OPA_INIT_DIFF_RECEIVER_OPA1 and @ref OPA_INIT_DIFF_RECEIVER_OPA2. + * @verbatim + + |\ + __________|+\ OPA1 + _ | \_________ + ___|_ / | | _____R2____ + | | / | | | | + | |/ | | | |\ | + |___________| |____R1_|___|_\ | + | \____|___ + |\ ____R1_ ___| / + +__________|+\ OPA0 | | |+/ OPA2 + | \_________| | |/ + ___|_ / | R2 + | | / | | + | |/ | NEGPAD OPA0 + |___________| + @endverbatim + * + * @if DOXYDOC_P2_DEVICE + * \nInstrumentation amplifier.\n + * Use predefined macros @ref OPA_INIT_INSTR_AMP_OPA0 and + * @ref OPA_INIT_INSTR_AMP_OPA1. + * @verbatim + + |\ + __________|+\ OPA1 + | \______________ + ___|_ / | + | | / | + | |/ R2 + |____________| + | + R1 + | + R1 + ____________| + | | + | R2 + | |\ | + |___|+\ OPA0 | + | \_____|________ + __________|_ / + | / + |/ + + @endverbatim + * @endif + * + * @{ + ******************************************************************************/ +/* *INDENT-ON* */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable an Operational Amplifier. + * + * @if DOXYDOC_P1_DEVICE + * @param[in] dac + * A pointer to the DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @param[in] dac + * A pointer to the VDAC peripheral register block. + * @endif + * + * @param[in] opa + * Selects an OPA, valid values are OPA0, OPA1, and OPA2. + ******************************************************************************/ +void OPAMP_Disable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + EFM_ASSERT(DAC_REF_VALID(dac)); + EFM_ASSERT(DAC_OPA_VALID(opa)); + + if (opa == OPA0) { + dac->CH0CTRL &= ~DAC_CH0CTRL_EN; + dac->OPACTRL &= ~DAC_OPACTRL_OPA0EN; + } else if (opa == OPA1) { + dac->CH1CTRL &= ~DAC_CH1CTRL_EN; + dac->OPACTRL &= ~DAC_OPACTRL_OPA1EN; + } else { /* OPA2 */ + dac->OPACTRL &= ~DAC_OPACTRL_OPA2EN; + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + + if (opa == OPA0) { +#if defined(VDAC_STATUS_OPA0ENS) + dac->CMD |= VDAC_CMD_OPA0DIS; + while (dac->STATUS & VDAC_STATUS_OPA0ENS) { + } +#endif +#if defined(VDAC_STATUS_OPA1ENS) + } else if (opa == OPA1) { + dac->CMD |= VDAC_CMD_OPA1DIS; + while (dac->STATUS & VDAC_STATUS_OPA1ENS) { + } +#endif +#if defined(VDAC_STATUS_OPA2ENS) + } else if (opa == OPA2) { + dac->CMD |= VDAC_CMD_OPA2DIS; + while (dac->STATUS & VDAC_STATUS_OPA2ENS) { + } +#endif + } else { /* OPA3 */ +#if defined(VDAC_STATUS_OPA3ENS) + dac->CMD |= VDAC_CMD_OPA3DIS; + while (dac->STATUS & VDAC_STATUS_OPA3ENS) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Configure and enable an Operational Amplifier. + * + * @if DOXYDOC_P1_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * DAC_OPA[opa#]MUX_OUTPEN_OUT[output#] flags + * (defined in \_dac.h) OR'ed together. @n @n + * For OPA0: + * @li DAC_OPA0MUX_OUTPEN_OUT0 + * @li DAC_OPA0MUX_OUTPEN_OUT1 + * @li DAC_OPA0MUX_OUTPEN_OUT2 + * @li DAC_OPA0MUX_OUTPEN_OUT3 + * @li DAC_OPA0MUX_OUTPEN_OUT4 + * + * For OPA1: + * @li DAC_OPA1MUX_OUTPEN_OUT0 + * @li DAC_OPA1MUX_OUTPEN_OUT1 + * @li DAC_OPA1MUX_OUTPEN_OUT2 + * @li DAC_OPA1MUX_OUTPEN_OUT3 + * @li DAC_OPA1MUX_OUTPEN_OUT4 + * + * For OPA2: + * @li DAC_OPA2MUX_OUTPEN_OUT0 + * @li DAC_OPA2MUX_OUTPEN_OUT1 + * + * E.g: @n + * init.outPen = DAC_OPA0MUX_OUTPEN_OUT0 | DAC_OPA0MUX_OUTPEN_OUT4; + * + * @param[in] dac + * A pointer to the DAC peripheral register block. + * @elseif DOXYDOC_P2_DEVICE + * @note + * The value of the alternate output enable bit mask in the OPAMP_Init_TypeDef + * structure should consist of one or more of the + * VDAC_OPA_OUT_ALTOUTPADEN_OUT[output#] flags + * (defined in \_vdac.h) OR'ed together. @n @n + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT0 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT1 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT2 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT3 + * @li VDAC_OPA_OUT_ALTOUTPADEN_OUT4 + * + * For example: @n + * init.outPen = VDAC_OPA_OUT_ALTOUTPADEN_OUT0 | VDAC_OPA_OUT_ALTOUTPADEN_OUT4; + * @param[in] dac + * A pointer to the VDAC peripheral register block. + * @endif + * + * @param[in] opa + * Selects an OPA, valid values are OPA0, OPA1, and OPA2. + * + * @param[in] init + * A pointer to a structure containing OPAMP initialization information. + ******************************************************************************/ +void OPAMP_Enable( +#if defined(_SILICON_LABS_32B_SERIES_0) + DAC_TypeDef *dac, +#elif defined(_SILICON_LABS_32B_SERIES_1) + VDAC_TypeDef *dac, +#endif + OPAMP_TypeDef opa, + const OPAMP_Init_TypeDef *init) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t gain; + + EFM_ASSERT(DAC_REF_VALID(dac)); + EFM_ASSERT(DAC_OPA_VALID(opa)); + EFM_ASSERT(init->bias <= (_DAC_BIASPROG_BIASPROG_MASK + >> _DAC_BIASPROG_BIASPROG_SHIFT)); + + if (opa == OPA0) { + EFM_ASSERT((init->outPen & ~_DAC_OPA0MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_BIASPROG_MASK + | DAC_BIASPROG_HALFBIAS)) + | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); + + if (init->defaultOffset) { + gain = dac->CAL & _DAC_CAL_GAIN_MASK; + SYSTEM_GetCalibrationValue(&dac->CAL); + dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; + } else { + EFM_ASSERT(init->offset <= (_DAC_CAL_CH0OFFSET_MASK + >> _DAC_CAL_CH0OFFSET_SHIFT)); + + dac->CAL = (dac->CAL & ~_DAC_CAL_CH0OFFSET_MASK) + | (init->offset << _DAC_CAL_CH0OFFSET_SHIFT); + } + + dac->OPA0MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA0MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA0MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA0MUX_PPEN : 0); + + dac->CH0CTRL |= DAC_CH0CTRL_EN; + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA0SHORT + | _DAC_OPACTRL_OPA0LPFDIS_MASK + | DAC_OPACTRL_OPA0HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA0SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA0LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA0LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA0HCMDIS : 0) + | DAC_OPACTRL_OPA0EN; + } else if ( opa == OPA1 ) { + EFM_ASSERT((init->outPen & ~_DAC_OPA1MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_BIASPROG_MASK + | DAC_BIASPROG_HALFBIAS)) + | (init->bias << _DAC_BIASPROG_BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_HALFBIAS : 0); + + if (init->defaultOffset) { + gain = dac->CAL & _DAC_CAL_GAIN_MASK; + SYSTEM_GetCalibrationValue(&dac->CAL); + dac->CAL = (dac->CAL & ~_DAC_CAL_GAIN_MASK) | gain; + } else { + EFM_ASSERT(init->offset <= (_DAC_CAL_CH1OFFSET_MASK + >> _DAC_CAL_CH1OFFSET_SHIFT)); + + dac->CAL = (dac->CAL & ~_DAC_CAL_CH1OFFSET_MASK) + | (init->offset << _DAC_CAL_CH1OFFSET_SHIFT); + } + + dac->OPA1MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA1MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA1MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA1MUX_PPEN : 0); + + dac->CH1CTRL |= DAC_CH1CTRL_EN; + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA1SHORT + | _DAC_OPACTRL_OPA1LPFDIS_MASK + | DAC_OPACTRL_OPA1HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA1SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA1LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA1LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA1HCMDIS : 0) + | DAC_OPACTRL_OPA1EN; + } else { /* OPA2 */ + EFM_ASSERT((init->posSel == DAC_OPA2MUX_POSSEL_DISABLE) + || (init->posSel == DAC_OPA2MUX_POSSEL_POSPAD) + || (init->posSel == DAC_OPA2MUX_POSSEL_OPA1INP) + || (init->posSel == DAC_OPA2MUX_POSSEL_OPATAP)); + + EFM_ASSERT((init->outMode & ~DAC_OPA2MUX_OUTMODE) == 0); + + EFM_ASSERT((init->outPen & ~_DAC_OPA2MUX_OUTPEN_MASK) == 0); + + dac->BIASPROG = (dac->BIASPROG + & ~(_DAC_BIASPROG_OPA2BIASPROG_MASK + | DAC_BIASPROG_OPA2HALFBIAS)) + | (init->bias << _DAC_BIASPROG_OPA2BIASPROG_SHIFT) + | (init->halfBias ? DAC_BIASPROG_OPA2HALFBIAS : 0); + + if (init->defaultOffset) { + SYSTEM_GetCalibrationValue(&dac->OPAOFFSET); + } else { + EFM_ASSERT(init->offset <= (_DAC_OPAOFFSET_OPA2OFFSET_MASK + >> _DAC_OPAOFFSET_OPA2OFFSET_SHIFT)); + dac->OPAOFFSET = (dac->OPAOFFSET & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK) + | (init->offset << _DAC_OPAOFFSET_OPA2OFFSET_SHIFT); + } + + dac->OPA2MUX = (uint32_t)init->resSel + | (uint32_t)init->outMode + | init->outPen + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel + | (init->nextOut ? DAC_OPA2MUX_NEXTOUT : 0) + | (init->npEn ? DAC_OPA2MUX_NPEN : 0) + | (init->ppEn ? DAC_OPA2MUX_PPEN : 0); + + dac->OPACTRL = (dac->OPACTRL + & ~(DAC_OPACTRL_OPA2SHORT + | _DAC_OPACTRL_OPA2LPFDIS_MASK + | DAC_OPACTRL_OPA2HCMDIS)) + | (init->shortInputs ? DAC_OPACTRL_OPA2SHORT : 0) + | (init->lpfPosPadDisable + ? DAC_OPACTRL_OPA2LPFDIS_PLPFDIS : 0) + | (init->lpfNegPadDisable + ? DAC_OPACTRL_OPA2LPFDIS_NLPFDIS : 0) + | (init->hcmDisable ? DAC_OPACTRL_OPA2HCMDIS : 0) + | DAC_OPACTRL_OPA2EN; + } + +#elif defined(_SILICON_LABS_32B_SERIES_1) + uint32_t calData = 0; + uint32_t warmupTime; + + EFM_ASSERT(VDAC_REF_VALID(dac)); + EFM_ASSERT(VDAC_OPA_VALID(opa)); + EFM_ASSERT(init->settleTime <= (_VDAC_OPA_TIMER_SETTLETIME_MASK + >> _VDAC_OPA_TIMER_SETTLETIME_SHIFT)); + EFM_ASSERT(init->startupDly <= (_VDAC_OPA_TIMER_STARTUPDLY_MASK + >> _VDAC_OPA_TIMER_STARTUPDLY_SHIFT)); + EFM_ASSERT((init->outPen & ~_VDAC_OPA_OUT_ALTOUTPADEN_MASK) == 0); + EFM_ASSERT((init->drvStr == opaDrvStrLowerAccLowStr) + || (init->drvStr == opaDrvStrLowAccLowStr) + || (init->drvStr == opaDrvStrHighAccHighStr) + || (init->drvStr == opaDrvStrHigherAccHighStr)); + + /* Disable OPAMP before writing to registers. */ + OPAMP_Disable(dac, opa); + + /* Get the calibration value based on OPAMP, Drive Strength, and INCBW. */ + switch (opa) { +#if defined(VDAC_STATUS_OPA0ENS) + case OPA0: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL0 : DEVINFO->OPA0CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL1 : DEVINFO->OPA0CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL2 : DEVINFO->OPA0CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA0CAL3 : DEVINFO->OPA0CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA1ENS) + case OPA1: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL0 : DEVINFO->OPA1CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL1 : DEVINFO->OPA1CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL2 : DEVINFO->OPA1CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA1CAL3 : DEVINFO->OPA1CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA2ENS) + case OPA2: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL0 : DEVINFO->OPA2CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL1 : DEVINFO->OPA2CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL2 : DEVINFO->OPA2CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA2CAL3 : DEVINFO->OPA2CAL7); + break; + } + break; +#endif + +#if defined(VDAC_STATUS_OPA3ENS) + case OPA3: + switch (init->drvStr) { + case opaDrvStrLowerAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL0 : DEVINFO->OPA3CAL4); + break; + case opaDrvStrLowAccLowStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL1 : DEVINFO->OPA3CAL5); + break; + case opaDrvStrHighAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL2 : DEVINFO->OPA3CAL6); + break; + case opaDrvStrHigherAccHighStr: + calData = (init->ugBwScale ? DEVINFO->OPA3CAL3 : DEVINFO->OPA3CAL7); + break; + } + break; +#endif + } + if (!init->defaultOffsetN) { + EFM_ASSERT(init->offsetN <= (_VDAC_OPA_CAL_OFFSETN_MASK + >> _VDAC_OPA_CAL_OFFSETN_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETN_MASK) + | (init->offsetN << _VDAC_OPA_CAL_OFFSETN_SHIFT); + } + if (!init->defaultOffsetP) { + EFM_ASSERT(init->offsetP <= (_VDAC_OPA_CAL_OFFSETP_MASK + >> _VDAC_OPA_CAL_OFFSETP_SHIFT)); + calData = (calData & ~_VDAC_OPA_CAL_OFFSETP_MASK) + | (init->offsetP << _VDAC_OPA_CAL_OFFSETP_SHIFT); + } + + dac->OPA[opa].CAL = (calData & _VDAC_OPA_CAL_MASK); + + dac->OPA[opa].MUX = (uint32_t)init->resSel + | (init->gain3xEn ? VDAC_OPA_MUX_GAIN3X : 0) + | (uint32_t)init->resInMux + | (uint32_t)init->negSel + | (uint32_t)init->posSel; + + dac->OPA[opa].OUT = (uint32_t)init->outMode + | (uint32_t)init->outPen; + + switch (init->drvStr) { + case opaDrvStrHigherAccHighStr: + warmupTime = 6; + break; + + case opaDrvStrHighAccHighStr: + warmupTime = 8; + break; + + case opaDrvStrLowAccLowStr: + warmupTime = 85; + break; + + case opaDrvStrLowerAccLowStr: + default: + warmupTime = 100; + break; + } + + dac->OPA[opa].TIMER = (uint32_t)(init->settleTime + << _VDAC_OPA_TIMER_SETTLETIME_SHIFT) + | (uint32_t)(warmupTime + << _VDAC_OPA_TIMER_WARMUPTIME_SHIFT) + | (uint32_t)(init->startupDly + << _VDAC_OPA_TIMER_STARTUPDLY_SHIFT); + + dac->OPA[opa].CTRL = (init->aportYMasterDisable + ? VDAC_OPA_CTRL_APORTYMASTERDIS : 0) + | (init->aportXMasterDisable + ? VDAC_OPA_CTRL_APORTXMASTERDIS : 0) + | (uint32_t)init->prsOutSel + | (uint32_t)init->prsSel + | (uint32_t)init->prsMode + | (init->prsEn ? VDAC_OPA_CTRL_PRSEN : 0) + | (init->halfDrvStr + ? VDAC_OPA_CTRL_OUTSCALE_HALF + : VDAC_OPA_CTRL_OUTSCALE_FULL) + | (init->hcmDisable ? VDAC_OPA_CTRL_HCMDIS : 0) + | (init->ugBwScale ? VDAC_OPA_CTRL_INCBW : 0) + | (uint32_t)init->drvStr; + + if (opa == OPA0) { +#if defined(VDAC_STATUS_OPA0ENS) + dac->CMD |= VDAC_CMD_OPA0EN; +#endif +#if defined(VDAC_STATUS_OPA1ENS) + } else if (opa == OPA1) { + dac->CMD |= VDAC_CMD_OPA1EN; +#endif +#if defined(VDAC_STATUS_OPA2ENS) + } else if (opa == OPA2) { + dac->CMD |= VDAC_CMD_OPA2EN; +#endif +#if defined(VDAC_STATUS_OPA3ENS) + } else { /* OPA3 */ + dac->CMD |= VDAC_CMD_OPA3EN; +#endif + } + +#endif +} + +/** @} (end addtogroup opamp) */ + +#endif /* (defined(OPAMP_PRESENT) && (OPAMP_COUNT == 1) + || defined(VDAC_PRESENT) && (VDAC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_pcnt.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_pcnt.c index aaf007d..1ede21c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_pcnt.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_pcnt.c @@ -1,1067 +1,1067 @@ -/***************************************************************************//** - * @file - * @brief Pulse Counter (PCNT) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_pcnt.h" -#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) - -#include "em_cmu.h" -#include "sl_assert.h" -#include "em_bus.h" - -/***************************************************************************//** - * @addtogroup pcnt PCNT - Pulse Counter - * @brief Pulse Counter (PCNT) Peripheral API - * @details - * This module contains functions to control the PCNT peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The PCNT decodes incoming pulses. The module has - * a quadrature mode which may be used to decode the speed and direction of a - * mechanical shaft. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the PCNT register block pointer reference for assert statements. */ -#if (PCNT_COUNT == 1) -#define PCNT_REF_VALID(ref) ((ref) == PCNT0) -#elif (PCNT_COUNT == 2) -#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1)) -#elif (PCNT_COUNT == 3) -#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) \ - || ((ref) == PCNT2)) -#else -#error "Undefined number of pulse counters (PCNT)." -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ -#if defined(_SILICON_LABS_32B_SERIES_2) -static PCNT_CntEvent_TypeDef initCntEvent; -static PCNT_CntEvent_TypeDef initAuxCntEvent; -#endif - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Map PCNT structure into an instance number. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @return - * An instance number. - ******************************************************************************/ -__STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt) -{ - return ((uint32_t)pcnt - PCNT0_BASE) / 0x400; -} -#endif -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Reset PCNT counters and TOP register. - * - * @note - * Notice that special SYNCBUSY handling is not applicable for the RSTEN - * bit of the control register, so we don't need to wait for it when only - * modifying RSTEN. (It would mean undefined wait time if clocked by an external - * clock.) The SYNCBUSY bit will however be set, leading to a synchronization - * in the LF domain, with, in reality, no changes. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - ******************************************************************************/ -void PCNT_CounterReset(PCNT_TypeDef *pcnt) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* Enable reset of the CNT and TOP register. */ - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); - - /* Disable reset of the CNT and TOP register. */ - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); -#else - /* Reset of the CNT and TOP register. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD_SET = PCNT_CMD_CNTRST | PCNT_CMD_AUXCNTRST; - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); - pcnt->TOP = _PCNT_TOP_RESETVALUE; -#endif -} - -/***************************************************************************//** - * @brief - * Set PCNT operational mode. - * - * @details - * Notice that this function does not do any configuration. Setting operational - * mode is normally only required after initialization is done, and if not - * done as part of initialization or if requiring to disable/reenable pulse - * counter. - * - * @note - * This function may stall until synchronization to low-frequency domain is - * completed. For that reason, it should normally not be used when - * an external clock is used for the PCNT module, since stall time may be - * undefined. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] mode - * An operational mode to use for PCNT. - ******************************************************************************/ -void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode) -{ - uint32_t tmp; - - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - - /* Set as specified. */ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK; - tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT; - - /* LF register about to be modified requires sync; busy check. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - pcnt->CTRL = tmp; -#else - /* Disable module if disable mode is passed. */ - if (mode == pcntModeDisable) { - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif - return; - } - /* Check if given mode is same as already configured. */ - tmp = (pcnt->CFG & _PCNT_CFG_MODE_MASK) >> _PCNT_CFG_MODE_SHIFT; - if (tmp != mode) { - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif - pcnt->CFG_SET = (uint32_t)mode << _PCNT_CFG_MODE_SHIFT; - } - /* Enable module */ - pcnt->EN_SET = PCNT_EN_EN; - /* Start Counters*/ - if (initCntEvent != pcntCntEventNone) { - PCNT_StartMainCnt(pcnt); - } - if (initAuxCntEvent != pcntCntEventNone) { - PCNT_StartAuxCnt(pcnt); - } - -#endif -} - -/***************************************************************************//** - * @brief - * Returns if the PCNT module is enabled or not. - * - * @details - * Notice that this function does not do any configuration. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @return Returns TRUE if the module is enabled. - ******************************************************************************/ -bool PCNT_IsEnabled(PCNT_TypeDef *pcnt) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - return ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE); -#else - return (pcnt->EN & _PCNT_EN_EN_MASK); -#endif -} - -/***************************************************************************//** - * @brief - * Set the counter and top values. - * - * @details - * The pulse counter is disabled while changing these values and reenabled - * (if originally enabled) when values have been set. - * - * @note - * This function will stall until synchronization to low-frequency domain is - * completed. For that reason, it should normally not be used when - * an external clock is used for the PCNT module, since stall time may be - * undefined. The counter should normally only be set when - * operating in (or about to enable) #pcntModeOvsSingle mode. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] count - * A value to set in the counter register. - * - * @param[in] top - * A value to set in the top register. - ******************************************************************************/ -void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - uint32_t ctrl; -#endif - - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#ifdef PCNT0 - if (PCNT0 == pcnt) { - EFM_ASSERT((1 << PCNT0_CNT_SIZE) > count); - EFM_ASSERT((1 << PCNT0_CNT_SIZE) > top); - } -#endif - -#ifdef PCNT1 - if (PCNT1 == pcnt) { - EFM_ASSERT((1 << PCNT1_CNT_SIZE) > count); - EFM_ASSERT((1 << PCNT1_CNT_SIZE) > top); - } -#endif - -#ifdef PCNT2 - if (PCNT2 == pcnt) { - EFM_ASSERT((1 << PCNT2_CNT_SIZE) > count); - EFM_ASSERT((1 << PCNT2_CNT_SIZE) > top); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* Keep the current control setting, must be restored. */ - ctrl = pcnt->CTRL; - - /* If enabled, disable pulse counter before changing values. */ - if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE; - } - - /* Load into TOPB. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); - pcnt->TOPB = count; - - /* Load TOPB value into TOP. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); - - /* This bit has no effect on rev. C and onwards parts - for compatibility. */ - pcnt->CMD = PCNT_CMD_LTOPBIM; - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - - /* Load TOP into CNT. */ - pcnt->CMD = PCNT_CMD_LCNTIM; - - /* Restore TOP. ('count' setting has been loaded into pcnt->TOP, better - * to use 'top' than pcnt->TOP in compare, since latter may not - * be visible yet.) */ - if (top != count) { - /* Wait for the command to sync LCNTIM before setting TOPB. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - - /* Load into TOPB. No need to check for TOPB sync complete, which - * has been ensured above. */ - pcnt->TOPB = top; - - /* Load TOPB value into TOP. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); - pcnt->CMD = PCNT_CMD_LTOPBIM; - } - - /* Reenable if it was enabled. */ - PCNT_Enable(pcnt, (PCNT_Mode_TypeDef)(ctrl & _PCNT_CTRL_MODE_MASK)); - if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD); - pcnt->CTRL = ctrl; - } -#else - /* Load into TOP. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); - pcnt->TOP = count; - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); - - /* Load TOP into CNT. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - pcnt->CMD = PCNT_CMD_LCNTIM; - - if (top != count) { - /* Wait for the command to sync LCNTIM before setting TOPB. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); - - pcnt->TOP = top; - } -#endif -} - -#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Enable/disable the selected PRS input of PCNT. - * - * @details - * Notice that this function does not do any configuration. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] prsInput - * PRS input (S0 or S1) of the selected PCNT module. - * - * @param[in] enable - * Set to true to enable, false to disable the selected PRS input. - ******************************************************************************/ -void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, - PCNT_PRSInput_TypeDef prsInput, - bool enable) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#if defined(_SILICON_LABS_32B_SERIES_2) - bool module_enable = PCNT_IsEnabled(pcnt); - - /* Disable module before writing to CFG register. */ - if (module_enable == true) { - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - } - - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif -#endif - - /* Enable/disable the selected PRS input on the selected PCNT module. */ - switch (prsInput) { - /* Enable/disable PRS input S0. */ - case pcntPRSInputS0: -#if defined(_PCNT_INPUT_MASK) - BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable); -#elif defined(_SILICON_LABS_32B_SERIES_2) - BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S0PRSEN_SHIFT, enable); -#endif - break; - - /* Enable/disable PRS input S1. */ - case pcntPRSInputS1: -#if defined(_PCNT_INPUT_MASK) - BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable); -#elif defined(_SILICON_LABS_32B_SERIES_2) - BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S1PRSEN_SHIFT, enable); -#endif - break; - - /* An invalid parameter, asserted. */ - default: - EFM_ASSERT(0); - break; - } - -#if defined(_SILICON_LABS_32B_SERIES_2) - /* Re-Enable if necessary the PCNT module after change. */ - if (module_enable == true) { - pcnt->EN_SET = PCNT_EN_EN; - } -#endif -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * PCNT register synchronization freeze control. - * - * @details - * Some PCNT registers require synchronization into the low-frequency (LF) - * domain. The freeze feature allows for several registers to be - * modified before passing them to the LF domain simultaneously, which - * takes place when the freeze mode is disabled. - * - * @note - * When enabling freeze mode, this function will wait for all current - * ongoing PCNT synchronization to the LF domain to complete (normally - * synchronization will not be in progress). However, for this reason, when - * using freeze mode, modifications of registers requiring the LF synchronization - * should be done within one freeze enable/disable block to avoid unnecessary - * stalling. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] enable - * @li True - enable freeze, modified registers are not propagated to the - * LF domain. - * @li False - disables freeze, modified registers are propagated to LF - * domain. - ******************************************************************************/ -void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - - if (enable) { - /* Wait for any ongoing LF synchronization to complete to - * protect against the rare case when a user: - * - modifies a register requiring LF sync - * - then enables freeze before LF sync completed - * - then modifies the same register again - * since modifying a register while it is in sync progress should be - * avoided. */ - while (pcnt->SYNCBUSY) { - } - - pcnt->FREEZE = PCNT_FREEZE_REGFREEZE; - } else { - pcnt->FREEZE = 0; - } -} -#endif - -/***************************************************************************//** - * @brief - * Initialize the pulse counter. - * - * @details - * This function will configure the pulse counter. The clock selection is - * configured as follows, depending on operational mode: - * - * @li #pcntModeOvsSingle - Use LFACLK. - * @li #pcntModeExtSingle - Use external PCNTn_S0 pin. - * @li #pcntModeExtQuad - Use external PCNTn_S0 pin. - * - * Notice that the LFACLK must be enabled in all modes, since some basic setup - * is done with this clock even if the external pin clock usage mode is chosen. - * The pulse counter clock for the selected instance must also be enabled - * prior to initialization. - * - * Notice that pins used by the PCNT module must be properly configured - * by the user explicitly through setting the ROUTE register for - * the PCNT to work as intended. - * - * Writing to CNT will not occur in external clock modes (EXTCLKQUAD and - * EXTCLKSINGLE) because the external clock rate is unknown. The user should - * handle it manually depending on the application. - * - * TOPB is written for all modes but in external clock mode it will take - * 3 external clock cycles to sync to TOP. - * - * - * @note - * Initializing requires synchronization into the low-frequency domain. This - * may cause a delay. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure. - ******************************************************************************/ -void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init) -{ - unsigned int inst = 0; - uint32_t tmp; - - (void)&tmp; - - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#ifdef PCNT0 - if (PCNT0 == pcnt) { - EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->counter); - EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->top); - } -#endif - -#ifdef PCNT1 - if (PCNT1 == pcnt) { - EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->counter); - EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->top); - } -#endif - -#ifdef PCNT2 - if (PCNT2 == pcnt) { - EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->counter); - EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->top); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* Map the pointer to an instance. */ - inst = PCNT_Map(pcnt); -#endif - -#if defined(_PCNT_INPUT_MASK) - /* Selecting the PRS channels for the PRS input sources of the PCNT. These are - * written with a Read-Modify-Write sequence to keep the value of the - * input enable bits which can be modified using PCNT_PRSInputEnable(). */ - tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK); - tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) - | ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT); - pcnt->INPUT = tmp; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* Build the CTRL setting, except for mode. */ - tmp = 0; - if (init->negEdge) { - tmp |= PCNT_CTRL_EDGE_NEG; - } - - if (init->countDown) { - tmp |= PCNT_CTRL_CNTDIR_DOWN; - } - -#if defined(PCNT_CTRL_FILT) - if (init->filter) { - tmp |= PCNT_CTRL_FILT; - } -#endif - -#if defined(PCNT_CTRL_HYST) - if (init->hyst) { - tmp |= PCNT_CTRL_HYST; - } -#endif - -#if defined(PCNT_CTRL_S1CDIR) - if (init->s1CntDir) { - tmp |= PCNT_CTRL_S1CDIR; - } -#endif - - /* Configure counter events for regular and auxiliary counters. */ -#if defined(_PCNT_CTRL_CNTEV_SHIFT) - tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; -#endif - -#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) - { - /* Modify the auxCntEvent value before writing to the AUXCNTEV field in - the CTRL register because the AUXCNTEV field values are different than - the CNTEV field values, and cntEvent and auxCntEvent are of the same type - PCNT_CntEvent_TypeDef. - */ - uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */ - switch (init->auxCntEvent) { - case pcntCntEventBoth: - auxCntEventField = pcntCntEventNone; - break; - -#if defined(_PCNT_CTRL_CNTEV_NONE) - case pcntCntEventNone: - auxCntEventField = pcntCntEventBoth; - break; -#endif - - case pcntCntEventUp: - case pcntCntEventDown: - auxCntEventField = init->auxCntEvent; - break; - - default: - /* An invalid parameter, asserted. */ - EFM_ASSERT(0); - break; - } - tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT; - } -#endif - - /* Reset the pulse counter while changing the clock source. The reset bit */ - /* is asynchronous, no need to check for SYNCBUSY. */ - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); - - /* Select LFACLK to clock in the control setting. */ - CMU_PCNTClockExternalSet(inst, false); - - /* Handling depends on whether using an external clock. */ - switch (init->mode) { - case pcntModeExtSingle: - case pcntModeExtQuad: - tmp |= ((uint32_t)init->mode) << _PCNT_CTRL_MODE_SHIFT; - - /* In most cases, the SYNCBUSY bit is set due to the reset bit set and waiting - * for asynchronous reset bit is strictly not necessary. - * In theory, other operations on CTRL register may have been done - * outside this function, so wait. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - - /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing - * the clock source to an external clock. */ - pcnt->CTRL = PCNT_CTRL_RSTEN; - - /* Wait until the CTRL write is synchronized into the LF domain. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - - /* Change to the external clock BEFORE disabling reset. */ - CMU_PCNTClockExternalSet(inst, true); - - /* Write to TOPB. If using the external clock, TOPB will sync to TOP at the same - * time as the mode ensuring that if the user chooses to count - * down, the first "countable" pulse will make CNT go to TOP and not 0xFF - * (default TOP value). */ - pcnt->TOPB = init->top; - - /* This bit has no effect on rev. C and onwards parts - for compatibility. */ - pcnt->CMD = PCNT_CMD_LTOPBIM; - - /* Write the CTRL register with the configurations. - * This should be written after TOPB in the eventuality of a pulse between - * these two writes that would cause the CTRL register to be synced one - * clock cycle earlier than the TOPB. */ - pcnt->CTRL = tmp; - - /* There are no syncs for TOP, CMD, or CTRL because the clock rate is unknown - * and the program could stall. - * These will be synced within 3 clock cycles of the external clock. / - * For the same reason CNT cannot be written here. */ - break; - - /* pcntModeDisable */ - /* pcntModeOvsSingle */ - /* pcntModeOvsQuadx */ - default: - /* No need to set disabled mode if already disabled. */ - if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { - /* Set control to disabled mode and leave reset on until ensured disabled. - * No need to wait for CTRL SYNCBUSY completion. It was - * triggered by the reset bit above, which is asynchronous. */ - pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN; - - /* Wait until the CTRL write is synchronized into the LF domain before proceeding - * to disable reset. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - } - - /* Disable reset bit. The counter should now be in disabled mode. */ - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); - - /* Set the counter and top values as specified. */ - PCNT_CounterTopSet(pcnt, init->counter, init->top); - - /* Enter oversampling mode if selected. */ - if (init->mode != pcntModeDisable) { - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT); - } - break; - } - -#else - /* If PCNT is enabled wait for all SYNCBUSY signals to complete. */ - if (pcnt->EN == 1U) { - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - } - - /* Disable PCNT. */ - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif - /* Build the CFG setting. */ - pcnt->CFG &= ~(_PCNT_CFG_DEBUGHALT_MASK | _PCNT_CFG_FILTEN_MASK | _PCNT_CFG_HYST_MASK); - pcnt->CFG |= (((uint32_t)init->filter) << _PCNT_CFG_FILTEN_SHIFT) - | (((uint32_t)init->hyst) << _PCNT_CFG_HYST_SHIFT) - | (((uint32_t)init->debugHalt) << _PCNT_CFG_DEBUGHALT_SHIFT); - - /* Set Mode setting. */ - /* Write the CFG register with the configurations. */ - if (init->mode != pcntModeDisable) { - pcnt->CFG = ((pcnt->CFG & (~_PCNT_CFG_MODE_MASK)) | (((uint32_t)init->mode) << _PCNT_CFG_MODE_SHIFT)); - } - - pcnt->EN_SET = PCNT_EN_EN; - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - - /* Build the CTRL setting */ - tmp = (((uint32_t)init->negEdge) << _PCNT_CTRL_EDGE_SHIFT) - | (((uint32_t)init->countDown) << _PCNT_CTRL_CNTDIR_SHIFT) - | (((uint32_t)init->s1CntDir) << _PCNT_CTRL_S1CDIR_SHIFT); - - /* Configure counter events for regular and auxiliary counters. */ - if (init->cntEvent != PCNT_CNT_EVENT_NONE) { - tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; - } - if (init->auxCntEvent != PCNT_CNT_EVENT_NONE) { - tmp |= ((uint32_t)init->auxCntEvent) << _PCNT_CTRL_AUXCNTEV_SHIFT; - } - - pcnt->CTRL = tmp; - - /* Set PRS inputs */ - EFM_ASSERT(init->s0PRS < PRS_ASYNC_CH_NUM); - EFM_ASSERT(init->s1PRS < PRS_ASYNC_CH_NUM); - PRS->CONSUMER_PCNT0_S0IN = init->s0PRS; - PRS->CONSUMER_PCNT0_S1IN = init->s1PRS; - - if (init->mode == pcntModeExtSingle || init->mode == pcntModeExtQuad) { - /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing - the clock source to an external clock. */ - pcnt->CMD_SET = PCNT_CMD_CORERST; - /* Change to the external clock. */ - CMU_PCNTClockExternalSet(inst, true); - } else { - /* Change to the internal clock. */ - CMU_PCNTClockExternalSet(inst, false); - } - - /* Start counter(s) */ - if (init->cntEvent != pcntCntEventNone) { - PCNT_StartMainCnt(pcnt); - } - if (init->auxCntEvent != pcntCntEventNone) { - PCNT_StartAuxCnt(pcnt); - } - - PCNT_CounterTopSet(pcnt, init->counter, init->top); - PCNT_TopBufferSet(pcnt, init->top); - - /* Save values of primary and auxiliary counter event. */ - initCntEvent = init->cntEvent; - initAuxCntEvent = init->auxCntEvent; - - if (init->mode == pcntModeDisable) { - /* Disable PCNT. */ - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif - } -#endif -} - -/***************************************************************************//** - * @brief - * Reset PCNT to the same state that it was in after a hardware reset. - * - * @details - * Notice the LFACLK must be enabled, since some basic reset is done with - * this clock. The pulse counter clock for the selected instance must also - * be enabled prior to initialization. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * centralized setup of this feature. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - ******************************************************************************/ -void PCNT_Reset(PCNT_TypeDef *pcnt) -{ - unsigned int inst = 0; - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* A map pointer to the instance and clock information. */ - inst = PCNT_Map(pcnt); - pcnt->IEN = _PCNT_IEN_RESETVALUE; - - /* Notice that special SYNCBUSY handling is not applicable for the RSTEN - * bit of the control register, so no need to wait for it when only - * modifying RSTEN. The SYNCBUSY bit will be set, leading to a - * synchronization in the LF domain, with, in reality, no changes to the LF domain. - * Enable reset of the CNT and TOP register. */ - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); - - /* Select LFACLK as default. */ - CMU_PCNTClockExternalSet(inst, false); - - PCNT_TopBufferSet(pcnt, _PCNT_TOPB_RESETVALUE); - - /* Reset CTRL leaving RSTEN set. */ - pcnt->CTRL = _PCNT_CTRL_RESETVALUE | PCNT_CTRL_RSTEN; - - /* Disable reset after CTRL register has been synchronized. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); - - /* Clear pending interrupts. */ - pcnt->IFC = _PCNT_IFC_MASK; - - /* Do not reset route register, setting should be done independently. */ -#else - /* Disable PCNT module. */ - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - pcnt->EN_CLR = PCNT_EN_EN; - - /* Select LFACLK as default. */ - /* Recommended to switch to internal clock before reset. */ - CMU_PCNTClockExternalSet(inst, false); - - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } - - /* Clear registers. */ - pcnt->SWRST_SET = PCNT_SWRST_SWRST; - - while (pcnt->SWRST & PCNT_SWRST_RESETTING) { - } - -#endif -} - -#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Set the filter configuration. - * - * @details - * This function will configure the PCNT input filter when the PCNT mode is - * configured to take an LFA-derived clock as an input clock. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] config - * A pointer to the configuration structure to be applied. - * - * @param[in] enable - * Indicates whether to enable or disable filtering. - ******************************************************************************/ -void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) -{ - uint32_t ovscfg = 0; -#if defined(_SILICON_LABS_32B_SERIES_2) - bool module_enable = false; -#endif - - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) - /* Construct the new filter setting value. */ - ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT) - | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT); - - /* Set the new configuration. LF register requires sync check before writing. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG); - pcnt->OVSCFG = ovscfg; - - /* Set new state of the filter. LF register requires sync check before writing. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - if (enable) { - pcnt->CTRL |= PCNT_CTRL_FILT; - } else { - pcnt->CTRL &= ~PCNT_CTRL_FILT; - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) - /* Disable module before changing CFG register. */ - module_enable = PCNT_IsEnabled(pcnt); - if (module_enable == true) { - PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); - } - pcnt->EN_CLR = PCNT_EN_EN; -#if defined(_PCNT_EN_DISABLING_MASK) - while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { - } -#endif - /* Construct the new filter setting value. */ - ovscfg = ((config->filtLen & _PCNT_OVSCTRL_FILTLEN_MASK) << _PCNT_OVSCTRL_FILTLEN_SHIFT) - | ((config->flutterrm & 0x1) << _PCNT_OVSCTRL_FLUTTERRM_SHIFT); - - /* Set the new configuration. LF register requires sync check before writing. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCTRL); - pcnt->OVSCTRL = ovscfg; - - /* Set new state of the filter. */ - if (enable) { - pcnt->CFG |= PCNT_CFG_FILTEN; - } else { - pcnt->CFG &= ~PCNT_CFG_FILTEN; - } - - /* Re-Enable module if necessary after change. */ - if (module_enable == true) { - pcnt->EN_SET = PCNT_EN_EN; - } -#endif -} -#endif - -#if defined(PCNT_CTRL_TCCMODE_DEFAULT) -/***************************************************************************//** - * @brief - * Set Triggered Compare and Clear configuration. - * - * @details - * This function will configure the PCNT TCC (Triggered Compare and Clear) - * module. This module can, upon a configurable trigger source, compare the - * current counter value with the configured TOP value. Upon match, the counter - * will be reset and the TCC PRS output and TCC interrupt flag will be set. - * - * Since there is a comparison with the TOP value, the counter will not stop - * counting nor wrap when hitting the TOP value, but it will keep on counting - * until its maximum value. Then, it will not wrap, but stop counting - * and set the overflow flag. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] config - * A pointer to the configuration structure to be applied. - ******************************************************************************/ -void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config) -{ - uint32_t ctrl = 0; - uint32_t mask = _PCNT_CTRL_TCCMODE_MASK - | _PCNT_CTRL_TCCPRESC_MASK - | _PCNT_CTRL_TCCCOMP_MASK - | _PCNT_CTRL_PRSGATEEN_MASK - | _PCNT_CTRL_TCCPRSPOL_MASK - | _PCNT_CTRL_TCCPRSSEL_MASK; - - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - - /* Construct the TCC part of the configuration register. */ - ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT) & _PCNT_CTRL_TCCMODE_MASK; - ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT) & _PCNT_CTRL_TCCPRESC_MASK; - ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT) & _PCNT_CTRL_TCCCOMP_MASK; - ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT) & _PCNT_CTRL_TCCPRSSEL_MASK; - ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT) & _PCNT_CTRL_TCCPRSPOL_MASK; - ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT) & _PCNT_CTRL_PRSGATEEN_MASK; - - /* Load new TCC configuration to PCNT. LF register requires a sync check before write. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); - pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl; -} -#endif - -/***************************************************************************//** - * @brief - * Set top buffer value. - * - * @note - * This function may stall until synchronization to low-frequency domain is - * completed. For that reason, it should normally not be used when - * an external clock is used for the PCNT module since stall time may be - * undefined. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] val - * A value to set in the top buffer register. - ******************************************************************************/ -void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - - /* LF register about to be modified require sync. busy check */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); - pcnt->TOPB = val; -} - -/***************************************************************************//** - * @brief - * Set the top value. - * - * @note - * This function will stall until synchronization to low-frequency domain is - * completed. For that reason, it should normally not be used when - * an external clock is used for the PCNT module since stall time may be - * undefined. - * - * @param[in] pcnt - * A pointer to the PCNT peripheral register block. - * - * @param[in] val - * A value to set in the top register. - ******************************************************************************/ -void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val) -{ - EFM_ASSERT(PCNT_REF_VALID(pcnt)); - -#ifdef PCNT0 - if (PCNT0 == pcnt) { - EFM_ASSERT((1 << PCNT0_CNT_SIZE) > val); - } -#endif - -#ifdef PCNT1 - if (PCNT1 == pcnt) { - EFM_ASSERT((1 << PCNT1_CNT_SIZE) > val); - } -#endif - -#ifdef PCNT2 - if (PCNT2 == pcnt) { - EFM_ASSERT((1 << PCNT2_CNT_SIZE) > val); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - /* LF register about to be modified requires sync; busy check. */ - - /* Load into TOPB. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); - pcnt->TOPB = val; - - /* Load TOPB value into TOP. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); - pcnt->CMD = PCNT_CMD_LTOPBIM; -#else - /* LF register about to be modified requires sync; busy check. */ - PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); - /* Load into TOP. */ - pcnt->TOP = val; -#endif -} - -/** @} (end addtogroup pcnt) */ -#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Pulse Counter (PCNT) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_pcnt.h" +#if defined(PCNT_COUNT) && (PCNT_COUNT > 0) + +#include "em_cmu.h" +#include "sl_assert.h" +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup pcnt PCNT - Pulse Counter + * @brief Pulse Counter (PCNT) Peripheral API + * @details + * This module contains functions to control the PCNT peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The PCNT decodes incoming pulses. The module has + * a quadrature mode which may be used to decode the speed and direction of a + * mechanical shaft. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the PCNT register block pointer reference for assert statements. */ +#if (PCNT_COUNT == 1) +#define PCNT_REF_VALID(ref) ((ref) == PCNT0) +#elif (PCNT_COUNT == 2) +#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1)) +#elif (PCNT_COUNT == 3) +#define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) \ + || ((ref) == PCNT2)) +#else +#error "Undefined number of pulse counters (PCNT)." +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_2) +static PCNT_CntEvent_TypeDef initCntEvent; +static PCNT_CntEvent_TypeDef initAuxCntEvent; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Map PCNT structure into an instance number. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @return + * An instance number. + ******************************************************************************/ +__STATIC_INLINE unsigned int PCNT_Map(PCNT_TypeDef *pcnt) +{ + return ((uint32_t)pcnt - PCNT0_BASE) / 0x400; +} +#endif +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Reset PCNT counters and TOP register. + * + * @note + * Notice that special SYNCBUSY handling is not applicable for the RSTEN + * bit of the control register, so we don't need to wait for it when only + * modifying RSTEN. (It would mean undefined wait time if clocked by an external + * clock.) The SYNCBUSY bit will however be set, leading to a synchronization + * in the LF domain, with, in reality, no changes. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + ******************************************************************************/ +void PCNT_CounterReset(PCNT_TypeDef *pcnt) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Enable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Disable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); +#else + /* Reset of the CNT and TOP register. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD_SET = PCNT_CMD_CNTRST | PCNT_CMD_AUXCNTRST; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + pcnt->TOP = _PCNT_TOP_RESETVALUE; +#endif +} + +/***************************************************************************//** + * @brief + * Set PCNT operational mode. + * + * @details + * Notice that this function does not do any configuration. Setting operational + * mode is normally only required after initialization is done, and if not + * done as part of initialization or if requiring to disable/reenable pulse + * counter. + * + * @note + * This function may stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module, since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] mode + * An operational mode to use for PCNT. + ******************************************************************************/ +void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode) +{ + uint32_t tmp; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* Set as specified. */ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + tmp = pcnt->CTRL & ~_PCNT_CTRL_MODE_MASK; + tmp |= (uint32_t)mode << _PCNT_CTRL_MODE_SHIFT; + + /* LF register about to be modified requires sync; busy check. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = tmp; +#else + /* Disable module if disable mode is passed. */ + if (mode == pcntModeDisable) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + return; + } + /* Check if given mode is same as already configured. */ + tmp = (pcnt->CFG & _PCNT_CFG_MODE_MASK) >> _PCNT_CFG_MODE_SHIFT; + if (tmp != mode) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + pcnt->CFG_SET = (uint32_t)mode << _PCNT_CFG_MODE_SHIFT; + } + /* Enable module */ + pcnt->EN_SET = PCNT_EN_EN; + /* Start Counters*/ + if (initCntEvent != pcntCntEventNone) { + PCNT_StartMainCnt(pcnt); + } + if (initAuxCntEvent != pcntCntEventNone) { + PCNT_StartAuxCnt(pcnt); + } + +#endif +} + +/***************************************************************************//** + * @brief + * Returns if the PCNT module is enabled or not. + * + * @details + * Notice that this function does not do any configuration. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @return Returns TRUE if the module is enabled. + ******************************************************************************/ +bool PCNT_IsEnabled(PCNT_TypeDef *pcnt) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + return ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE); +#else + return (pcnt->EN & _PCNT_EN_EN_MASK); +#endif +} + +/***************************************************************************//** + * @brief + * Set the counter and top values. + * + * @details + * The pulse counter is disabled while changing these values and reenabled + * (if originally enabled) when values have been set. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module, since stall time may be + * undefined. The counter should normally only be set when + * operating in (or about to enable) #pcntModeOvsSingle mode. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] count + * A value to set in the counter register. + * + * @param[in] top + * A value to set in the top register. + ******************************************************************************/ +void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + uint32_t ctrl; +#endif + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > top); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > top); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > count); + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > top); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Keep the current control setting, must be restored. */ + ctrl = pcnt->CTRL; + + /* If enabled, disable pulse counter before changing values. */ + if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = (ctrl & ~_PCNT_CTRL_MODE_MASK) | PCNT_CTRL_MODE_DISABLE; + } + + /* Load into TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = count; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + + /* This bit has no effect on rev. C and onwards parts - for compatibility. */ + pcnt->CMD = PCNT_CMD_LTOPBIM; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + /* Load TOP into CNT. */ + pcnt->CMD = PCNT_CMD_LCNTIM; + + /* Restore TOP. ('count' setting has been loaded into pcnt->TOP, better + * to use 'top' than pcnt->TOP in compare, since latter may not + * be visible yet.) */ + if (top != count) { + /* Wait for the command to sync LCNTIM before setting TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + /* Load into TOPB. No need to check for TOPB sync complete, which + * has been ensured above. */ + pcnt->TOPB = top; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LTOPBIM; + } + + /* Reenable if it was enabled. */ + PCNT_Enable(pcnt, (PCNT_Mode_TypeDef)(ctrl & _PCNT_CTRL_MODE_MASK)); + if ((ctrl & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL | PCNT_SYNCBUSY_CMD); + pcnt->CTRL = ctrl; + } +#else + /* Load into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + pcnt->TOP = count; + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + + /* Load TOP into CNT. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LCNTIM; + + if (top != count) { + /* Wait for the command to sync LCNTIM before setting TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CMD); + + pcnt->TOP = top; + } +#endif +} + +#if defined(_PCNT_INPUT_MASK) || defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Enable/disable the selected PRS input of PCNT. + * + * @details + * Notice that this function does not do any configuration. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] prsInput + * PRS input (S0 or S1) of the selected PCNT module. + * + * @param[in] enable + * Set to true to enable, false to disable the selected PRS input. + ******************************************************************************/ +void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, + PCNT_PRSInput_TypeDef prsInput, + bool enable) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_2) + bool module_enable = PCNT_IsEnabled(pcnt); + + /* Disable module before writing to CFG register. */ + if (module_enable == true) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif +#endif + + /* Enable/disable the selected PRS input on the selected PCNT module. */ + switch (prsInput) { + /* Enable/disable PRS input S0. */ + case pcntPRSInputS0: +#if defined(_PCNT_INPUT_MASK) + BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S0PRSEN_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2) + BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S0PRSEN_SHIFT, enable); +#endif + break; + + /* Enable/disable PRS input S1. */ + case pcntPRSInputS1: +#if defined(_PCNT_INPUT_MASK) + BUS_RegBitWrite(&(pcnt->INPUT), _PCNT_INPUT_S1PRSEN_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2) + BUS_RegBitWrite(&(pcnt->CFG), _PCNT_CFG_S1PRSEN_SHIFT, enable); +#endif + break; + + /* An invalid parameter, asserted. */ + default: + EFM_ASSERT(0); + break; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* Re-Enable if necessary the PCNT module after change. */ + if (module_enable == true) { + pcnt->EN_SET = PCNT_EN_EN; + } +#endif +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * PCNT register synchronization freeze control. + * + * @details + * Some PCNT registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several registers to be + * modified before passing them to the LF domain simultaneously, which + * takes place when the freeze mode is disabled. + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing PCNT synchronization to the LF domain to complete (normally + * synchronization will not be in progress). However, for this reason, when + * using freeze mode, modifications of registers requiring the LF synchronization + * should be done within one freeze enable/disable block to avoid unnecessary + * stalling. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] enable + * @li True - enable freeze, modified registers are not propagated to the + * LF domain. + * @li False - disables freeze, modified registers are propagated to LF + * domain. + ******************************************************************************/ +void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + if (enable) { + /* Wait for any ongoing LF synchronization to complete to + * protect against the rare case when a user: + * - modifies a register requiring LF sync + * - then enables freeze before LF sync completed + * - then modifies the same register again + * since modifying a register while it is in sync progress should be + * avoided. */ + while (pcnt->SYNCBUSY) { + } + + pcnt->FREEZE = PCNT_FREEZE_REGFREEZE; + } else { + pcnt->FREEZE = 0; + } +} +#endif + +/***************************************************************************//** + * @brief + * Initialize the pulse counter. + * + * @details + * This function will configure the pulse counter. The clock selection is + * configured as follows, depending on operational mode: + * + * @li #pcntModeOvsSingle - Use LFACLK. + * @li #pcntModeExtSingle - Use external PCNTn_S0 pin. + * @li #pcntModeExtQuad - Use external PCNTn_S0 pin. + * + * Notice that the LFACLK must be enabled in all modes, since some basic setup + * is done with this clock even if the external pin clock usage mode is chosen. + * The pulse counter clock for the selected instance must also be enabled + * prior to initialization. + * + * Notice that pins used by the PCNT module must be properly configured + * by the user explicitly through setting the ROUTE register for + * the PCNT to work as intended. + * + * Writing to CNT will not occur in external clock modes (EXTCLKQUAD and + * EXTCLKSINGLE) because the external clock rate is unknown. The user should + * handle it manually depending on the application. + * + * TOPB is written for all modes but in external clock mode it will take + * 3 external clock cycles to sync to TOP. + * + * + * @note + * Initializing requires synchronization into the low-frequency domain. This + * may cause a delay. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure. + ******************************************************************************/ +void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init) +{ + unsigned int inst = 0; + uint32_t tmp; + + (void)&tmp; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > init->top); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > init->top); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->counter); + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > init->top); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Map the pointer to an instance. */ + inst = PCNT_Map(pcnt); +#endif + +#if defined(_PCNT_INPUT_MASK) + /* Selecting the PRS channels for the PRS input sources of the PCNT. These are + * written with a Read-Modify-Write sequence to keep the value of the + * input enable bits which can be modified using PCNT_PRSInputEnable(). */ + tmp = pcnt->INPUT & ~(_PCNT_INPUT_S0PRSSEL_MASK | _PCNT_INPUT_S1PRSSEL_MASK); + tmp |= ((uint32_t)init->s0PRS << _PCNT_INPUT_S0PRSSEL_SHIFT) + | ((uint32_t)init->s1PRS << _PCNT_INPUT_S1PRSSEL_SHIFT); + pcnt->INPUT = tmp; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* Build the CTRL setting, except for mode. */ + tmp = 0; + if (init->negEdge) { + tmp |= PCNT_CTRL_EDGE_NEG; + } + + if (init->countDown) { + tmp |= PCNT_CTRL_CNTDIR_DOWN; + } + +#if defined(PCNT_CTRL_FILT) + if (init->filter) { + tmp |= PCNT_CTRL_FILT; + } +#endif + +#if defined(PCNT_CTRL_HYST) + if (init->hyst) { + tmp |= PCNT_CTRL_HYST; + } +#endif + +#if defined(PCNT_CTRL_S1CDIR) + if (init->s1CntDir) { + tmp |= PCNT_CTRL_S1CDIR; + } +#endif + + /* Configure counter events for regular and auxiliary counters. */ +#if defined(_PCNT_CTRL_CNTEV_SHIFT) + tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; +#endif + +#if defined(_PCNT_CTRL_AUXCNTEV_SHIFT) + { + /* Modify the auxCntEvent value before writing to the AUXCNTEV field in + the CTRL register because the AUXCNTEV field values are different than + the CNTEV field values, and cntEvent and auxCntEvent are of the same type + PCNT_CntEvent_TypeDef. + */ + uint32_t auxCntEventField = 0; /* Get rid of compiler warning. */ + switch (init->auxCntEvent) { + case pcntCntEventBoth: + auxCntEventField = pcntCntEventNone; + break; + +#if defined(_PCNT_CTRL_CNTEV_NONE) + case pcntCntEventNone: + auxCntEventField = pcntCntEventBoth; + break; +#endif + + case pcntCntEventUp: + case pcntCntEventDown: + auxCntEventField = init->auxCntEvent; + break; + + default: + /* An invalid parameter, asserted. */ + EFM_ASSERT(0); + break; + } + tmp |= auxCntEventField << _PCNT_CTRL_AUXCNTEV_SHIFT; + } +#endif + + /* Reset the pulse counter while changing the clock source. The reset bit */ + /* is asynchronous, no need to check for SYNCBUSY. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Select LFACLK to clock in the control setting. */ + CMU_PCNTClockExternalSet(inst, false); + + /* Handling depends on whether using an external clock. */ + switch (init->mode) { + case pcntModeExtSingle: + case pcntModeExtQuad: + tmp |= ((uint32_t)init->mode) << _PCNT_CTRL_MODE_SHIFT; + + /* In most cases, the SYNCBUSY bit is set due to the reset bit set and waiting + * for asynchronous reset bit is strictly not necessary. + * In theory, other operations on CTRL register may have been done + * outside this function, so wait. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + + /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing + * the clock source to an external clock. */ + pcnt->CTRL = PCNT_CTRL_RSTEN; + + /* Wait until the CTRL write is synchronized into the LF domain. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + + /* Change to the external clock BEFORE disabling reset. */ + CMU_PCNTClockExternalSet(inst, true); + + /* Write to TOPB. If using the external clock, TOPB will sync to TOP at the same + * time as the mode ensuring that if the user chooses to count + * down, the first "countable" pulse will make CNT go to TOP and not 0xFF + * (default TOP value). */ + pcnt->TOPB = init->top; + + /* This bit has no effect on rev. C and onwards parts - for compatibility. */ + pcnt->CMD = PCNT_CMD_LTOPBIM; + + /* Write the CTRL register with the configurations. + * This should be written after TOPB in the eventuality of a pulse between + * these two writes that would cause the CTRL register to be synced one + * clock cycle earlier than the TOPB. */ + pcnt->CTRL = tmp; + + /* There are no syncs for TOP, CMD, or CTRL because the clock rate is unknown + * and the program could stall. + * These will be synced within 3 clock cycles of the external clock. / + * For the same reason CNT cannot be written here. */ + break; + + /* pcntModeDisable */ + /* pcntModeOvsSingle */ + /* pcntModeOvsQuadx */ + default: + /* No need to set disabled mode if already disabled. */ + if ((pcnt->CTRL & _PCNT_CTRL_MODE_MASK) != PCNT_CTRL_MODE_DISABLE) { + /* Set control to disabled mode and leave reset on until ensured disabled. + * No need to wait for CTRL SYNCBUSY completion. It was + * triggered by the reset bit above, which is asynchronous. */ + pcnt->CTRL = tmp | PCNT_CTRL_MODE_DISABLE | PCNT_CTRL_RSTEN; + + /* Wait until the CTRL write is synchronized into the LF domain before proceeding + * to disable reset. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + } + + /* Disable reset bit. The counter should now be in disabled mode. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); + + /* Set the counter and top values as specified. */ + PCNT_CounterTopSet(pcnt, init->counter, init->top); + + /* Enter oversampling mode if selected. */ + if (init->mode != pcntModeDisable) { + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = tmp | (init->mode << _PCNT_CTRL_MODE_SHIFT); + } + break; + } + +#else + /* If PCNT is enabled wait for all SYNCBUSY signals to complete. */ + if (pcnt->EN == 1U) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + + /* Disable PCNT. */ + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + /* Build the CFG setting. */ + pcnt->CFG &= ~(_PCNT_CFG_DEBUGHALT_MASK | _PCNT_CFG_FILTEN_MASK | _PCNT_CFG_HYST_MASK); + pcnt->CFG |= (((uint32_t)init->filter) << _PCNT_CFG_FILTEN_SHIFT) + | (((uint32_t)init->hyst) << _PCNT_CFG_HYST_SHIFT) + | (((uint32_t)init->debugHalt) << _PCNT_CFG_DEBUGHALT_SHIFT); + + /* Set Mode setting. */ + /* Write the CFG register with the configurations. */ + if (init->mode != pcntModeDisable) { + pcnt->CFG = ((pcnt->CFG & (~_PCNT_CFG_MODE_MASK)) | (((uint32_t)init->mode) << _PCNT_CFG_MODE_SHIFT)); + } + + pcnt->EN_SET = PCNT_EN_EN; + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + + /* Build the CTRL setting */ + tmp = (((uint32_t)init->negEdge) << _PCNT_CTRL_EDGE_SHIFT) + | (((uint32_t)init->countDown) << _PCNT_CTRL_CNTDIR_SHIFT) + | (((uint32_t)init->s1CntDir) << _PCNT_CTRL_S1CDIR_SHIFT); + + /* Configure counter events for regular and auxiliary counters. */ + if (init->cntEvent != PCNT_CNT_EVENT_NONE) { + tmp |= ((uint32_t)init->cntEvent) << _PCNT_CTRL_CNTEV_SHIFT; + } + if (init->auxCntEvent != PCNT_CNT_EVENT_NONE) { + tmp |= ((uint32_t)init->auxCntEvent) << _PCNT_CTRL_AUXCNTEV_SHIFT; + } + + pcnt->CTRL = tmp; + + /* Set PRS inputs */ + EFM_ASSERT(init->s0PRS < PRS_ASYNC_CH_NUM); + EFM_ASSERT(init->s1PRS < PRS_ASYNC_CH_NUM); + PRS->CONSUMER_PCNT0_S0IN = init->s0PRS; + PRS->CONSUMER_PCNT0_S1IN = init->s1PRS; + + if (init->mode == pcntModeExtSingle || init->mode == pcntModeExtQuad) { + /* Enable PCNT Clock Domain Reset. The PCNT must be in reset before changing + the clock source to an external clock. */ + pcnt->CMD_SET = PCNT_CMD_CORERST; + /* Change to the external clock. */ + CMU_PCNTClockExternalSet(inst, true); + } else { + /* Change to the internal clock. */ + CMU_PCNTClockExternalSet(inst, false); + } + + /* Start counter(s) */ + if (init->cntEvent != pcntCntEventNone) { + PCNT_StartMainCnt(pcnt); + } + if (init->auxCntEvent != pcntCntEventNone) { + PCNT_StartAuxCnt(pcnt); + } + + PCNT_CounterTopSet(pcnt, init->counter, init->top); + PCNT_TopBufferSet(pcnt, init->top); + + /* Save values of primary and auxiliary counter event. */ + initCntEvent = init->cntEvent; + initAuxCntEvent = init->auxCntEvent; + + if (init->mode == pcntModeDisable) { + /* Disable PCNT. */ + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Reset PCNT to the same state that it was in after a hardware reset. + * + * @details + * Notice the LFACLK must be enabled, since some basic reset is done with + * this clock. The pulse counter clock for the selected instance must also + * be enabled prior to initialization. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + ******************************************************************************/ +void PCNT_Reset(PCNT_TypeDef *pcnt) +{ + unsigned int inst = 0; + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* A map pointer to the instance and clock information. */ + inst = PCNT_Map(pcnt); + pcnt->IEN = _PCNT_IEN_RESETVALUE; + + /* Notice that special SYNCBUSY handling is not applicable for the RSTEN + * bit of the control register, so no need to wait for it when only + * modifying RSTEN. The SYNCBUSY bit will be set, leading to a + * synchronization in the LF domain, with, in reality, no changes to the LF domain. + * Enable reset of the CNT and TOP register. */ + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 1); + + /* Select LFACLK as default. */ + CMU_PCNTClockExternalSet(inst, false); + + PCNT_TopBufferSet(pcnt, _PCNT_TOPB_RESETVALUE); + + /* Reset CTRL leaving RSTEN set. */ + pcnt->CTRL = _PCNT_CTRL_RESETVALUE | PCNT_CTRL_RSTEN; + + /* Disable reset after CTRL register has been synchronized. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + BUS_RegBitWrite(&(pcnt->CTRL), _PCNT_CTRL_RSTEN_SHIFT, 0); + + /* Clear pending interrupts. */ + pcnt->IFC = _PCNT_IFC_MASK; + + /* Do not reset route register, setting should be done independently. */ +#else + /* Disable PCNT module. */ + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + pcnt->EN_CLR = PCNT_EN_EN; + + /* Select LFACLK as default. */ + /* Recommended to switch to internal clock before reset. */ + CMU_PCNTClockExternalSet(inst, false); + + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } + + /* Clear registers. */ + pcnt->SWRST_SET = PCNT_SWRST_SWRST; + + while (pcnt->SWRST & PCNT_SWRST_RESETTING) { + } + +#endif +} + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) || defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Set the filter configuration. + * + * @details + * This function will configure the PCNT input filter when the PCNT mode is + * configured to take an LFA-derived clock as an input clock. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] config + * A pointer to the configuration structure to be applied. + * + * @param[in] enable + * Indicates whether to enable or disable filtering. + ******************************************************************************/ +void PCNT_FilterConfiguration(PCNT_TypeDef *pcnt, const PCNT_Filter_TypeDef *config, bool enable) +{ + uint32_t ovscfg = 0; +#if defined(_SILICON_LABS_32B_SERIES_2) + bool module_enable = false; +#endif + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#if defined(PCNT_OVSCFG_FILTLEN_DEFAULT) + /* Construct the new filter setting value. */ + ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT) + | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT); + + /* Set the new configuration. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG); + pcnt->OVSCFG = ovscfg; + + /* Set new state of the filter. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + if (enable) { + pcnt->CTRL |= PCNT_CTRL_FILT; + } else { + pcnt->CTRL &= ~PCNT_CTRL_FILT; + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + /* Disable module before changing CFG register. */ + module_enable = PCNT_IsEnabled(pcnt); + if (module_enable == true) { + PCNT_Sync(pcnt, _PCNT_SYNCBUSY_MASK); + } + pcnt->EN_CLR = PCNT_EN_EN; +#if defined(_PCNT_EN_DISABLING_MASK) + while (pcnt->EN & _PCNT_EN_DISABLING_MASK) { + } +#endif + /* Construct the new filter setting value. */ + ovscfg = ((config->filtLen & _PCNT_OVSCTRL_FILTLEN_MASK) << _PCNT_OVSCTRL_FILTLEN_SHIFT) + | ((config->flutterrm & 0x1) << _PCNT_OVSCTRL_FLUTTERRM_SHIFT); + + /* Set the new configuration. LF register requires sync check before writing. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCTRL); + pcnt->OVSCTRL = ovscfg; + + /* Set new state of the filter. */ + if (enable) { + pcnt->CFG |= PCNT_CFG_FILTEN; + } else { + pcnt->CFG &= ~PCNT_CFG_FILTEN; + } + + /* Re-Enable module if necessary after change. */ + if (module_enable == true) { + pcnt->EN_SET = PCNT_EN_EN; + } +#endif +} +#endif + +#if defined(PCNT_CTRL_TCCMODE_DEFAULT) +/***************************************************************************//** + * @brief + * Set Triggered Compare and Clear configuration. + * + * @details + * This function will configure the PCNT TCC (Triggered Compare and Clear) + * module. This module can, upon a configurable trigger source, compare the + * current counter value with the configured TOP value. Upon match, the counter + * will be reset and the TCC PRS output and TCC interrupt flag will be set. + * + * Since there is a comparison with the TOP value, the counter will not stop + * counting nor wrap when hitting the TOP value, but it will keep on counting + * until its maximum value. Then, it will not wrap, but stop counting + * and set the overflow flag. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] config + * A pointer to the configuration structure to be applied. + ******************************************************************************/ +void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config) +{ + uint32_t ctrl = 0; + uint32_t mask = _PCNT_CTRL_TCCMODE_MASK + | _PCNT_CTRL_TCCPRESC_MASK + | _PCNT_CTRL_TCCCOMP_MASK + | _PCNT_CTRL_PRSGATEEN_MASK + | _PCNT_CTRL_TCCPRSPOL_MASK + | _PCNT_CTRL_TCCPRSSEL_MASK; + + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* Construct the TCC part of the configuration register. */ + ctrl |= (config->mode << _PCNT_CTRL_TCCMODE_SHIFT) & _PCNT_CTRL_TCCMODE_MASK; + ctrl |= (config->prescaler << _PCNT_CTRL_TCCPRESC_SHIFT) & _PCNT_CTRL_TCCPRESC_MASK; + ctrl |= (config->compare << _PCNT_CTRL_TCCCOMP_SHIFT) & _PCNT_CTRL_TCCCOMP_MASK; + ctrl |= (config->tccPRS << _PCNT_CTRL_TCCPRSSEL_SHIFT) & _PCNT_CTRL_TCCPRSSEL_MASK; + ctrl |= (config->prsPolarity << _PCNT_CTRL_TCCPRSPOL_SHIFT) & _PCNT_CTRL_TCCPRSPOL_MASK; + ctrl |= (config->prsGateEnable << _PCNT_CTRL_PRSGATEEN_SHIFT) & _PCNT_CTRL_PRSGATEEN_MASK; + + /* Load new TCC configuration to PCNT. LF register requires a sync check before write. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_CTRL); + pcnt->CTRL = (pcnt->CTRL & (~mask)) | ctrl; +} +#endif + +/***************************************************************************//** + * @brief + * Set top buffer value. + * + * @note + * This function may stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] val + * A value to set in the top buffer register. + ******************************************************************************/ +void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + + /* LF register about to be modified require sync. busy check */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = val; +} + +/***************************************************************************//** + * @brief + * Set the top value. + * + * @note + * This function will stall until synchronization to low-frequency domain is + * completed. For that reason, it should normally not be used when + * an external clock is used for the PCNT module since stall time may be + * undefined. + * + * @param[in] pcnt + * A pointer to the PCNT peripheral register block. + * + * @param[in] val + * A value to set in the top register. + ******************************************************************************/ +void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val) +{ + EFM_ASSERT(PCNT_REF_VALID(pcnt)); + +#ifdef PCNT0 + if (PCNT0 == pcnt) { + EFM_ASSERT((1 << PCNT0_CNT_SIZE) > val); + } +#endif + +#ifdef PCNT1 + if (PCNT1 == pcnt) { + EFM_ASSERT((1 << PCNT1_CNT_SIZE) > val); + } +#endif + +#ifdef PCNT2 + if (PCNT2 == pcnt) { + EFM_ASSERT((1 << PCNT2_CNT_SIZE) > val); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + /* LF register about to be modified requires sync; busy check. */ + + /* Load into TOPB. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB); + pcnt->TOPB = val; + + /* Load TOPB value into TOP. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOPB | PCNT_SYNCBUSY_CMD); + pcnt->CMD = PCNT_CMD_LTOPBIM; +#else + /* LF register about to be modified requires sync; busy check. */ + PCNT_Sync(pcnt, PCNT_SYNCBUSY_TOP); + /* Load into TOP. */ + pcnt->TOP = val; +#endif +} + +/** @} (end addtogroup pcnt) */ +#endif /* defined(PCNT_COUNT) && (PCNT_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c index 3dbfc4d..8c0a858 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c @@ -1,661 +1,661 @@ -/***************************************************************************//** - * @file - * @brief Peripheral Reflex System (PRS) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_prs.h" -#if defined(PRS_COUNT) && (PRS_COUNT > 0) - -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup prs PRS - Peripheral Reflex System - * @brief Peripheral Reflex System (PRS) Peripheral API - * @details - * This module contains functions to control the PRS peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous - * communication between peripherals on the MCU or SoC. - * @{ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/* Generic defines for async and sync signals applying to all TIMER instances. - * Those defines map to TIMER2 but it could be any TIMER instance number. */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 - -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get PRS source signal for a channel. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] ch - * channel number. - * - * @return - * PRS signal assigned to the channel. - ******************************************************************************/ -static PRS_Signal_t getSignal(unsigned int ch, PRS_ChType_t type) -{ - PRS_Signal_t signal; - -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) - if (type == prsTypeAsync) { - signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL - & (_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK)); - } else { - signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL - & (_PRS_SYNC_CH_CTRL_SOURCESEL_MASK | _PRS_SYNC_CH_CTRL_SIGSEL_MASK)); - } -#else - (void) type; - signal = (PRS_Signal_t) (PRS->CH[ch].CTRL - & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK)); -#endif - return signal; -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Convert an async PRS source to a sync source. - * - * @details - * This conversion must be done because the id's of the same peripheral - * source is different depending on if it's used as an asynchronous PRS source - * or a synchronous PRS source. - * - * @param[in] asyncSource - * The id of the asynchronous PRS source. - * - * @return - * The id of the corresponding synchronous PRS source. - ******************************************************************************/ -uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource) -{ - uint32_t syncSource = 0; - - switch (asyncSource) { - case _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_NONE; - break; -#if defined(IADC_PRESENT) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; - break; -#endif - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; - break; -#if defined(TIMER4) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4; - break; -#endif -#if defined(TIMER5) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5; - break; -#endif -#if defined(TIMER6) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6; - break; -#endif -#if defined(TIMER7) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7; - break; -#endif -#if defined(VDAC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0; - break; -#endif -#if defined(VDAC1) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - return syncSource; -} - -/***************************************************************************//** - * @brief - * Convert an async PRS signal to a sync signal. - * - * @details - * PRS values for some peripherals signals differ between asynchronous and - * synchronous PRS channels. This function must be used to handle the - * conversion. - * - * @param[in] asyncSource - * The id of the asynchronous PRS source. - * - * @param[in] asyncSignal - * The id of the asynchronous PRS signal. - * - * @return - * The id of the corresponding synchronous PRS signal. - ******************************************************************************/ -uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) -{ - uint32_t syncSignal = asyncSignal; - - switch (asyncSource) { - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: -#endif - /* Async and sync signal values are consistent across all timers instances. - * Generic defines are used. */ - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#if defined(IADC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(VDAC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(VDAC1) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif - default: - // No translation - break; - } - return syncSignal; -} -#endif - -/***************************************************************************//** - * @brief - * Set a source and signal for a channel. - * - * @param[in] ch - * A channel to define the signal and source for. - * - * @param[in] source - * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. - * - * @param[in] signal - * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x - * defines. - * - * @param[in] edge - * An edge (for selected source/signal) to generate the pulse for. - ******************************************************************************/ -void PRS_SourceSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal, - PRS_Edge_TypeDef edge) -{ -#if defined(_PRS_SYNC_CH_CTRL_MASK) - (void) edge; - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) - | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); -#else - EFM_ASSERT(ch < PRS_CHAN_COUNT); - PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) - | (signal & _PRS_CH_CTRL_SIGSEL_MASK) - | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; -#endif -} - -#if defined(PRS_ASYNC_SUPPORTED) -/***************************************************************************//** - * @brief - * Set the source and asynchronous signal for a channel. - * - * @details - * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in - * EM2/EM3. - * There is a limitation to reflexes operating in asynchronous mode in - * that they can only be used by a subset of the reflex consumers. See - * the PRS chapter in the reference manual for the complete list of - * supported asynchronous signals and consumers. - * - * @note - * This function is not supported on EFM32GxxxFyyy parts. - * In asynchronous mode, the edge detector only works in EM0 and should - * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) - * by default. - * - * @param[in] ch - * A channel to define the source and asynchronous signal for. - * - * @param[in] source - * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. - * - * @param[in] signal - * An asynchronous signal (for selected @p source) to use. Use one of the - * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. - ******************************************************************************/ -void PRS_SourceAsyncSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal) -{ - PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); -} -#endif - -#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) -/***************************************************************************//** - * @brief - * Send the output of a PRS channel to a GPIO pin. - * - * @details - * This function is used to send the output of a PRS channel to a GPIO pin. - * Note that there are certain restrictions to where a PRS channel can be - * routed. Consult the datasheet of the device to see if a channel can be - * routed to the requested GPIO pin. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] location - * PRS routing location. - ******************************************************************************/ -void PRS_GpioOutputLocation(unsigned int ch, - unsigned int location) -{ - EFM_ASSERT(ch < PRS_CHAN_COUNT); - -#if defined(_PRS_ROUTE_MASK) - PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) - | (1 << ch); -#else - uint32_t shift = (ch % 4) * 8; - uint32_t mask = location << shift; - uint32_t locationGroup = ch / 4; - /* Since all ROUTELOCx registers are in consecutive memory locations, treat them - * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ - volatile uint32_t * routeloc = &PRS->ROUTELOC0; - routeloc[locationGroup] |= mask; - PRS->ROUTEPEN |= 1 << ch; -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Search for the first free PRS channel. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * Channel number >= 0 if an unused PRS channel was found. If no free PRS - * channel was found then -1 is returned. - ******************************************************************************/ -int PRS_GetFreeChannel(PRS_ChType_t type) -{ - int ch = -1; - PRS_Signal_t signal; - int max; - - if (type == prsTypeAsync) { - max = PRS_ASYNC_CHAN_COUNT; - } else { - max = PRS_SYNC_CHAN_COUNT; - } - - for (int i = 0; i < max; i++) { - signal = getSignal(i, type); - if (signal == prsSignalNone) { - ch = i; - break; - } - } - return ch; -} - -/***************************************************************************//** - * @brief - * Reset all PRS channels - * - * @details - * This function will reset all the PRS channel configuration. - ******************************************************************************/ -void PRS_Reset(void) -{ - unsigned int i; - -#if defined(_SILICON_LABS_32B_SERIES_2) - PRS->ASYNC_SWLEVEL = 0; - for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { - PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; - } - for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { - PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; - } -#else - PRS->SWLEVEL = 0x0; - for (i = 0; i < PRS_CHAN_COUNT; i++) { - PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; - } -#endif -} - -/***************************************************************************//** - * @brief - * Connect a PRS signal to a channel. - * - * @details - * This function will make the PRS signal available on the specific channel. - * Only a single PRS signal can be connected to any given channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] signal - * This is the PRS signal that should be placed on the channel. - ******************************************************************************/ -void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) -{ -#if defined(_PRS_ASYNC_CH_CTRL_MASK) - // Series 2 devices - uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) - >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; - uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) - >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; - if (type == prsTypeAsync) { - EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); - PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A - | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) - | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); - } else { - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - signalField = PRS_ConvertToSyncSignal(sourceField, signalField); - sourceField = PRS_ConvertToSyncSource(sourceField); - PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) - | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); - } -#else - // Series 0 and Series 1 devices - uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK - | _PRS_CH_CTRL_SIGSEL_MASK); - if (type == prsTypeAsync) { -#if defined(PRS_ASYNC_SUPPORTED) - EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); - PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF - | PRS_CH_CTRL_ASYNC - | signalField; -#endif - } else { - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF - | signalField; - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Connect a peripheral consumer to a PRS channel. - * - * @details - * Different peripherals can use PRS channels as their input. This function - * can be used to connect a peripheral consumer to a PRS channel. Multiple - * consumers can be connected to a single PRS channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] consumer - * This is the PRS consumer. - ******************************************************************************/ -void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) -{ - EFM_ASSERT((uint32_t)consumer <= 0xFFF); - volatile uint32_t * addr = (volatile uint32_t *) PRS; - uint32_t offset = (uint32_t) consumer; - addr = addr + offset / 4; - - if (consumer != prsConsumerNone) { - if (type == prsTypeAsync) { - *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; - } else { - *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; - } - } -} - -/***************************************************************************//** - * @brief - * Send the output of a PRS channel to a GPIO pin. - * - * @details - * This function is used to send the output of a PRS channel to a GPIO pin. - * Note that there are certain restrictions to where a PRS channel can be - * routed. Consult the datasheet of the device to see if a channel can be - * routed to the requested GPIO pin. Some devices for instance can only route - * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 - * can only be routed to GPIO pins PCx and PDx - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO pin - ******************************************************************************/ -void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) -{ - volatile uint32_t * addr; - if (type == prsTypeAsync) { - addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; - } else { - addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; - } - addr += ch; - *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) - | ((uint32_t)pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); - - if (type == prsTypeAsync) { - GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); - } else { - GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); - } -} - -/***************************************************************************//** - * @brief - * Combine two PRS channels using a logic function. - * - * @details - * This function allows you to combine the output of one PRS channel with the - * the signal of another PRS channel using various logic functions. Note that - * for series 2, config 1 devices, the hardware only allows a PRS channel to - * be combined with the previous channel. So for instance channel 5 can be - * combined only with channel 4. - * - * The logic function operates on two PRS channels called A and B. The output - * of PRS channel B is combined with the PRS source configured for channel A - * to produce an output. This output is used as the output of channel A. - * - * @param[in] chA - * PRS Channel for the A input. - * - * @param[in] chB - * PRS Channel for the B input. - * - * @param[in] logic - * The logic function to use when combining the Channel A and Channel B. The - * output of the logic function is the output of Channel A. Function like - * AND, OR, XOR, NOT and more are available. - ******************************************************************************/ -void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) -{ - EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); - EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); - PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) - | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); - -#else - PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL - & ~(_PRS_ASYNC_CH_CTRL_FNSEL_MASK - | _PRS_ASYNC_CH_CTRL_AUXSEL_MASK)) - | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT) - | ((uint32_t)chB << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT); -#endif -} -#endif - -/** @} (end addtogroup prs) */ -#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_prs.h" +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup prs PRS - Peripheral Reflex System + * @brief Peripheral Reflex System (PRS) Peripheral API + * @details + * This module contains functions to control the PRS peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous + * communication between peripherals on the MCU or SoC. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/* Generic defines for async and sync signals applying to all TIMER instances. + * Those defines map to TIMER2 but it could be any TIMER instance number. */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get PRS source signal for a channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] ch + * channel number. + * + * @return + * PRS signal assigned to the channel. + ******************************************************************************/ +static PRS_Signal_t getSignal(unsigned int ch, PRS_ChType_t type) +{ + PRS_Signal_t signal; + +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + if (type == prsTypeAsync) { + signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL + & (_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK)); + } else { + signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL + & (_PRS_SYNC_CH_CTRL_SOURCESEL_MASK | _PRS_SYNC_CH_CTRL_SIGSEL_MASK)); + } +#else + (void) type; + signal = (PRS_Signal_t) (PRS->CH[ch].CTRL + & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK)); +#endif + return signal; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Convert an async PRS source to a sync source. + * + * @details + * This conversion must be done because the id's of the same peripheral + * source is different depending on if it's used as an asynchronous PRS source + * or a synchronous PRS source. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @return + * The id of the corresponding synchronous PRS source. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource) +{ + uint32_t syncSource = 0; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_NONE; + break; +#if defined(IADC_PRESENT) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; + break; +#endif + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; + break; +#if defined(TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4; + break; +#endif +#if defined(TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5; + break; +#endif +#if defined(TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6; + break; +#endif +#if defined(TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7; + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0; + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + return syncSource; +} + +/***************************************************************************//** + * @brief + * Convert an async PRS signal to a sync signal. + * + * @details + * PRS values for some peripherals signals differ between asynchronous and + * synchronous PRS channels. This function must be used to handle the + * conversion. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @param[in] asyncSignal + * The id of the asynchronous PRS signal. + * + * @return + * The id of the corresponding synchronous PRS signal. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) +{ + uint32_t syncSignal = asyncSignal; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: +#endif + /* Async and sync signal values are consistent across all timers instances. + * Generic defines are used. */ + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#if defined(IADC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif + default: + // No translation + break; + } + return syncSignal; +} +#endif + +/***************************************************************************//** + * @brief + * Set a source and signal for a channel. + * + * @param[in] ch + * A channel to define the signal and source for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x + * defines. + * + * @param[in] edge + * An edge (for selected source/signal) to generate the pulse for. + ******************************************************************************/ +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge) +{ +#if defined(_PRS_SYNC_CH_CTRL_MASK) + (void) edge; + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); +#else + EFM_ASSERT(ch < PRS_CHAN_COUNT); + PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_CH_CTRL_SIGSEL_MASK) + | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; +#endif +} + +#if defined(PRS_ASYNC_SUPPORTED) +/***************************************************************************//** + * @brief + * Set the source and asynchronous signal for a channel. + * + * @details + * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in + * EM2/EM3. + * There is a limitation to reflexes operating in asynchronous mode in + * that they can only be used by a subset of the reflex consumers. See + * the PRS chapter in the reference manual for the complete list of + * supported asynchronous signals and consumers. + * + * @note + * This function is not supported on EFM32GxxxFyyy parts. + * In asynchronous mode, the edge detector only works in EM0 and should + * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) + * by default. + * + * @param[in] ch + * A channel to define the source and asynchronous signal for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * An asynchronous signal (for selected @p source) to use. Use one of the + * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. + ******************************************************************************/ +void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal) +{ + PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); +} +#endif + +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] location + * PRS routing location. + ******************************************************************************/ +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location) +{ + EFM_ASSERT(ch < PRS_CHAN_COUNT); + +#if defined(_PRS_ROUTE_MASK) + PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) + | (1 << ch); +#else + uint32_t shift = (ch % 4) * 8; + uint32_t mask = location << shift; + uint32_t locationGroup = ch / 4; + /* Since all ROUTELOCx registers are in consecutive memory locations, treat them + * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ + volatile uint32_t * routeloc = &PRS->ROUTELOC0; + routeloc[locationGroup] |= mask; + PRS->ROUTEPEN |= 1 << ch; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Search for the first free PRS channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * Channel number >= 0 if an unused PRS channel was found. If no free PRS + * channel was found then -1 is returned. + ******************************************************************************/ +int PRS_GetFreeChannel(PRS_ChType_t type) +{ + int ch = -1; + PRS_Signal_t signal; + int max; + + if (type == prsTypeAsync) { + max = PRS_ASYNC_CHAN_COUNT; + } else { + max = PRS_SYNC_CHAN_COUNT; + } + + for (int i = 0; i < max; i++) { + signal = getSignal(i, type); + if (signal == prsSignalNone) { + ch = i; + break; + } + } + return ch; +} + +/***************************************************************************//** + * @brief + * Reset all PRS channels + * + * @details + * This function will reset all the PRS channel configuration. + ******************************************************************************/ +void PRS_Reset(void) +{ + unsigned int i; + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS->ASYNC_SWLEVEL = 0; + for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { + PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; + } + for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { + PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; + } +#else + PRS->SWLEVEL = 0x0; + for (i = 0; i < PRS_CHAN_COUNT; i++) { + PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; + } +#endif +} + +/***************************************************************************//** + * @brief + * Connect a PRS signal to a channel. + * + * @details + * This function will make the PRS signal available on the specific channel. + * Only a single PRS signal can be connected to any given channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] signal + * This is the PRS signal that should be placed on the channel. + ******************************************************************************/ +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) +{ +#if defined(_PRS_ASYNC_CH_CTRL_MASK) + // Series 2 devices + uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; + uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + if (type == prsTypeAsync) { + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A + | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + signalField = PRS_ConvertToSyncSignal(sourceField, signalField); + sourceField = PRS_ConvertToSyncSource(sourceField); + PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); + } +#else + // Series 0 and Series 1 devices + uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK + | _PRS_CH_CTRL_SIGSEL_MASK); + if (type == prsTypeAsync) { +#if defined(PRS_ASYNC_SUPPORTED) + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | PRS_CH_CTRL_ASYNC + | signalField; +#endif + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | signalField; + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Connect a peripheral consumer to a PRS channel. + * + * @details + * Different peripherals can use PRS channels as their input. This function + * can be used to connect a peripheral consumer to a PRS channel. Multiple + * consumers can be connected to a single PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] consumer + * This is the PRS consumer. + ******************************************************************************/ +void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) +{ + EFM_ASSERT((uint32_t)consumer <= 0xFFF); + volatile uint32_t * addr = (volatile uint32_t *) PRS; + uint32_t offset = (uint32_t) consumer; + addr = addr + offset / 4; + + if (consumer != prsConsumerNone) { + if (type == prsTypeAsync) { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} + +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. Some devices for instance can only route + * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 + * can only be routed to GPIO pins PCx and PDx + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO pin + ******************************************************************************/ +void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) +{ + volatile uint32_t * addr; + if (type == prsTypeAsync) { + addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; + } else { + addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; + } + addr += ch; + *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) + | ((uint32_t)pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); + + if (type == prsTypeAsync) { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); + } else { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); + } +} + +/***************************************************************************//** + * @brief + * Combine two PRS channels using a logic function. + * + * @details + * This function allows you to combine the output of one PRS channel with the + * the signal of another PRS channel using various logic functions. Note that + * for series 2, config 1 devices, the hardware only allows a PRS channel to + * be combined with the previous channel. So for instance channel 5 can be + * combined only with channel 4. + * + * The logic function operates on two PRS channels called A and B. The output + * of PRS channel B is combined with the PRS source configured for channel A + * to produce an output. This output is used as the output of channel A. + * + * @param[in] chA + * PRS Channel for the A input. + * + * @param[in] chB + * PRS Channel for the B input. + * + * @param[in] logic + * The logic function to use when combining the Channel A and Channel B. The + * output of the logic function is the output of Channel A. Function like + * AND, OR, XOR, NOT and more are available. + ******************************************************************************/ +void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) +{ + EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); + EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); + +#else + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL + & ~(_PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_AUXSEL_MASK)) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT) + | ((uint32_t)chB << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT); +#endif +} +#endif + +/** @} (end addtogroup prs) */ +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c index 30f8062..2709a8a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c @@ -1,382 +1,382 @@ -/***************************************************************************//** - * @file - * @brief Reset Management Unit (RMU) peripheral module peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_rmu.h" -#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) - -#include "sl_common.h" -#include "em_emu.h" -#include "em_bus.h" - -/***************************************************************************//** - * @addtogroup rmu RMU - Reset Management Unit - * @brief Reset Management Unit (RMU) Peripheral API - * @details - * This module contains functions to control the RMU peripheral of Silicon - * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is - * responsible for connecting the different reset sources to the reset lines of - * the MCU or SoC. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ***************************** DEFINES ********************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_RMU_RSTCAUSE_MASK) - -/** Reset cause XMASKS for series-0 and series-1 devices. - Reset cause zero and "don't care" bit definitions (XMASKs). - An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK - is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask - in @ref RMU_ResetCauseMasks_Typedef. */ - -/* EFM32G */ -#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ -#define NUM_RSTCAUSES 7 - -/* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ -#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ -#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ -#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ -#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ -#define NUM_RSTCAUSES 11 - -/* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ -#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ -#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ -#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ -#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ -#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ -#define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ -#define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ -#define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ -#define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ -#define NUM_RSTCAUSES 16 - -/* EFM32xG1, EFM32xG12, EFM32xG13 */ -#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ -#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ -#define NUM_RSTCAUSES 9 - -/* EFM32GG11 */ -#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ -#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ -#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ -#define NUM_RSTCAUSES 10 - -#else -#error "RMU_RSTCAUSE XMASKs are not defined for this family." -#endif - -/* Pin reset definitions. */ -#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) -#define LB_CLW0_PINRESETSOFT (1 << 2) - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ -#define ERRATA_FIX_EMU_E208_EN -#endif - -#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(_RMU_RSTCAUSE_MASK) -/** Reset cause mask type for series-0 and series-1 devices. */ -typedef struct { - /** Reset cause 1 bits. */ - uint32_t resetCauseMask; - /** Reset cause 0 and "don't care" bits. */ - uint32_t resetCauseZeroXMask; -} RMU_ResetCauseMasks_Typedef; -#endif - -/******************************************************************************* - ******************************* TYPEDEFS ********************************** - ******************************************************************************/ - -#if defined(_RMU_RSTCAUSE_MASK) -/** Reset cause mask table. */ -static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = -{ - { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, -#if defined(RMU_RSTCAUSE_BODUNREGRST) - { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODREGRST) - { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_AVDDBOD) - { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_DVDDBOD) - { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_DECBOD) - { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, -#endif - { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, - { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, - { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, - { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, -#if defined(RMU_RSTCAUSE_EM4RST) - { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_EM4WURST) - { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODAVDD0) - { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODAVDD1) - { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) - { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, - { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, - { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, - { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, - { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, -#elif defined(RMU_RSTCAUSE_BUMODERST) - { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, -#endif -}; -#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ - -/******************************************************************************* - ******************************** TEST ******************************** - ******************************************************************************/ -#if defined(EMLIB_REGRESSION_TEST) -/* A test variable that replaces the RSTCAUSE cause register when testing - the RMU_ResetCauseGet function. */ -extern uint32_t rstCause; -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable/enable reset for various peripherals and signal sources. - * - * @param[in] reset Reset types to enable/disable.s - * - * @param[in] mode Reset mode. - ******************************************************************************/ -void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) -{ - /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ -#if defined(_RMU_CTRL_PINRMODE_MASK) - uint32_t val; -#endif - uint32_t shift; - - shift = SL_CTZ((uint32_t)reset); -#if defined(_EMU_RSTCTRL_MASK) - BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); -#elif defined(_RMU_CTRL_PINRMODE_MASK) - val = (uint32_t)mode << shift; - RMU->CTRL = (RMU->CTRL & ~reset) | val; -#else - BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); -#endif -} - -/***************************************************************************//** - * @brief - * Clear the reset cause register. - * - * @details - * This function clears all the reset cause bits of the RSTCAUSE register. - * The reset cause bits must be cleared by software before a new reset occurs. - * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). - ******************************************************************************/ -void RMU_ResetCauseClear(void) -{ -#if defined(_EMU_RSTCTRL_MASK) - EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; -#else - RMU->CMD = RMU_CMD_RCCLR; -#endif - -#if defined(EMU_AUXCTRL_HRCCLR) - { - uint32_t locked; - - /* Clear reset causes not cleared with the RMU CMD register. */ - /* (If EMU registers are locked, they must be unlocked first) */ - locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; - if (locked) { - EMU_Unlock(); - } - - BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); - BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); - - if (locked) { - EMU_Lock(); - } - } -#endif -} - -/***************************************************************************//** - * @brief - * Get the cause of the last reset. - * - * @details - * To be useful, the reset cause must be cleared by software before a new - * reset occurs. Otherwise, reset causes may accumulate. See @ref - * RMU_ResetCauseClear(). This function call will return the main cause for - * reset, which can be a bit mask (several causes) and clear away "noise". - * - * @return - * A reset cause mask. See the reference manual for a description - * of the reset cause mask. - ******************************************************************************/ -uint32_t RMU_ResetCauseGet(void) -{ -#if defined(_EMU_RSTCAUSE_MASK) -#if defined(EMLIB_REGRESSION_TEST) - return rstCause; -#else - return EMU->RSTCAUSE; -#endif -#endif - -#if defined(_RMU_RSTCAUSE_MASK) -#if !defined(EMLIB_REGRESSION_TEST) - uint32_t rstCause = RMU->RSTCAUSE; -#endif - uint32_t validRstCause = 0; - uint32_t zeroXMask; - uint32_t i; - - for (i = 0; i < NUM_RSTCAUSES; i++) { - zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Handle soft/hard pin reset. */ - if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { - /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ - switch (resetCauseMasks[i].resetCauseMask) { - case RMU_RSTCAUSE_LOCKUPRST: - /* Fallthrough */ - case RMU_RSTCAUSE_SYSREQRST: - /* Fallthrough */ - case RMU_RSTCAUSE_WDOGRST: - /* Fallthrough */ - case RMU_RSTCAUSE_EM4RST: - zeroXMask |= RMU_RSTCAUSE_EXTRST; - break; - default: - /* MISRA requires a default case. */ - break; - } - } -#endif - -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) - /* Ignore BOD flags impacted by EMU_E208. */ - if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { - zeroXMask &= ~(RMU_RSTCAUSE_DECBOD - | RMU_RSTCAUSE_DVDDBOD - | RMU_RSTCAUSE_AVDDBOD); - } -#endif - - /* Check reset cause requirements. Note that a bit is "don't care" if 0 in - both resetCauseMask and resetCauseZeroXMask. */ - if ((rstCause & resetCauseMasks[i].resetCauseMask) - && !(rstCause & zeroXMask)) { - /* Add this reset-cause to the mask of qualified reset-causes. */ - validRstCause |= resetCauseMasks[i].resetCauseMask; - } - } -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) - /* Clear BOD flags impacted by EMU_E208. */ - if (validRstCause & RMU_RSTCAUSE_EM4RST) { - validRstCause &= ~(RMU_RSTCAUSE_DECBOD - | RMU_RSTCAUSE_DVDDBOD - | RMU_RSTCAUSE_AVDDBOD); - } -#endif - return validRstCause; -#endif -} - -/** @} (end addtogroup rmu) */ -#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_rmu.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) + +#include "sl_common.h" +#include "em_emu.h" +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup rmu RMU - Reset Management Unit + * @brief Reset Management Unit (RMU) Peripheral API + * @details + * This module contains functions to control the RMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is + * responsible for connecting the different reset sources to the reset lines of + * the MCU or SoC. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ***************************** DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_RMU_RSTCAUSE_MASK) + +/** Reset cause XMASKS for series-0 and series-1 devices. + Reset cause zero and "don't care" bit definitions (XMASKs). + An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK + is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask + in @ref RMU_ResetCauseMasks_Typedef. */ + +/* EFM32G */ +#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ +#define NUM_RSTCAUSES 7 + +/* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ +#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ +#define NUM_RSTCAUSES 11 + +/* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ +#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ +#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ +#define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ +#define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ +#define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ +#define NUM_RSTCAUSES 16 + +/* EFM32xG1, EFM32xG12, EFM32xG13 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 9 + +/* EFM32GG11 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 10 + +#else +#error "RMU_RSTCAUSE XMASKs are not defined for this family." +#endif + +/* Pin reset definitions. */ +#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) +#define LB_CLW0_PINRESETSOFT (1 << 2) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#define ERRATA_FIX_EMU_E208_EN +#endif + +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask type for series-0 and series-1 devices. */ +typedef struct { + /** Reset cause 1 bits. */ + uint32_t resetCauseMask; + /** Reset cause 0 and "don't care" bits. */ + uint32_t resetCauseZeroXMask; +} RMU_ResetCauseMasks_Typedef; +#endif + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask table. */ +static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = +{ + { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, +#if defined(RMU_RSTCAUSE_BODUNREGRST) + { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODREGRST) + { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_AVDDBOD) + { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DVDDBOD) + { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DECBOD) + { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif + { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, + { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, + { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, + { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, +#if defined(RMU_RSTCAUSE_EM4RST) + { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_EM4WURST) + { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD0) + { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD1) + { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) + { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, + { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, + { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, + { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#elif defined(RMU_RSTCAUSE_BUMODERST) + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#endif +}; +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************** TEST ******************************** + ******************************************************************************/ +#if defined(EMLIB_REGRESSION_TEST) +/* A test variable that replaces the RSTCAUSE cause register when testing + the RMU_ResetCauseGet function. */ +extern uint32_t rstCause; +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable/enable reset for various peripherals and signal sources. + * + * @param[in] reset Reset types to enable/disable.s + * + * @param[in] mode Reset mode. + ******************************************************************************/ +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) +{ + /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ +#if defined(_RMU_CTRL_PINRMODE_MASK) + uint32_t val; +#endif + uint32_t shift; + + shift = SL_CTZ((uint32_t)reset); +#if defined(_EMU_RSTCTRL_MASK) + BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); +#elif defined(_RMU_CTRL_PINRMODE_MASK) + val = (uint32_t)mode << shift; + RMU->CTRL = (RMU->CTRL & ~reset) | val; +#else + BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); +#endif +} + +/***************************************************************************//** + * @brief + * Clear the reset cause register. + * + * @details + * This function clears all the reset cause bits of the RSTCAUSE register. + * The reset cause bits must be cleared by software before a new reset occurs. + * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). + ******************************************************************************/ +void RMU_ResetCauseClear(void) +{ +#if defined(_EMU_RSTCTRL_MASK) + EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; +#else + RMU->CMD = RMU_CMD_RCCLR; +#endif + +#if defined(EMU_AUXCTRL_HRCCLR) + { + uint32_t locked; + + /* Clear reset causes not cleared with the RMU CMD register. */ + /* (If EMU registers are locked, they must be unlocked first) */ + locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; + if (locked) { + EMU_Unlock(); + } + + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); + + if (locked) { + EMU_Lock(); + } + } +#endif +} + +/***************************************************************************//** + * @brief + * Get the cause of the last reset. + * + * @details + * To be useful, the reset cause must be cleared by software before a new + * reset occurs. Otherwise, reset causes may accumulate. See @ref + * RMU_ResetCauseClear(). This function call will return the main cause for + * reset, which can be a bit mask (several causes) and clear away "noise". + * + * @return + * A reset cause mask. See the reference manual for a description + * of the reset cause mask. + ******************************************************************************/ +uint32_t RMU_ResetCauseGet(void) +{ +#if defined(_EMU_RSTCAUSE_MASK) +#if defined(EMLIB_REGRESSION_TEST) + return rstCause; +#else + return EMU->RSTCAUSE; +#endif +#endif + +#if defined(_RMU_RSTCAUSE_MASK) +#if !defined(EMLIB_REGRESSION_TEST) + uint32_t rstCause = RMU->RSTCAUSE; +#endif + uint32_t validRstCause = 0; + uint32_t zeroXMask; + uint32_t i; + + for (i = 0; i < NUM_RSTCAUSES; i++) { + zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Handle soft/hard pin reset. */ + if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { + /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ + switch (resetCauseMasks[i].resetCauseMask) { + case RMU_RSTCAUSE_LOCKUPRST: + /* Fallthrough */ + case RMU_RSTCAUSE_SYSREQRST: + /* Fallthrough */ + case RMU_RSTCAUSE_WDOGRST: + /* Fallthrough */ + case RMU_RSTCAUSE_EM4RST: + zeroXMask |= RMU_RSTCAUSE_EXTRST; + break; + default: + /* MISRA requires a default case. */ + break; + } + } +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Ignore BOD flags impacted by EMU_E208. */ + if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { + zeroXMask &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif + + /* Check reset cause requirements. Note that a bit is "don't care" if 0 in + both resetCauseMask and resetCauseZeroXMask. */ + if ((rstCause & resetCauseMasks[i].resetCauseMask) + && !(rstCause & zeroXMask)) { + /* Add this reset-cause to the mask of qualified reset-causes. */ + validRstCause |= resetCauseMasks[i].resetCauseMask; + } + } +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Clear BOD flags impacted by EMU_E208. */ + if (validRstCause & RMU_RSTCAUSE_EM4RST) { + validRstCause &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif + return validRstCause; +#endif +} + +/** @} (end addtogroup rmu) */ +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_se.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_se.c index 649cec5..df9faaf 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_se.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_se.c @@ -1,1372 +1,1372 @@ -/***************************************************************************//** - * @file - * @brief Secure Element API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_se.h" - -#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#include "em_core.h" -#include "sl_assert.h" -#include "em_system.h" - -#endif - -/***************************************************************************//** - * @addtogroup se - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* OTP initialization structure defines. */ -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) - -#if defined(CRYPTOACC_PRESENT) - -/// Signal that OTP version is incorporated into the status field of the output -#define SE_VSE_REPLY_STATUS_OTP_VERSION_SET (1 << 21) -/// Mask defining the region of the status field that contains the OTP version -/// number. -#define SE_VSE_REPLY_STATUS_OTP_VERSION_MASK (0xFF000000UL) -/// Shift to insert a number into the otp version part of the status field -#define SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT (24) - -/* Size of VSE Mailbox instance. - There are two instances, input and output. */ -#define ROOT_MAILBOX_SIZE (512UL) - -/* Base addresses of the VSE Input and Output Mailbox data structures. - (Must be stored in a RAM area which is not used by the VSE) - We use the upper 1KB of FRC RAM for the VSE mailboxes. */ -#define ROOT_MAILBOX_OUTPUT_S_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE) -#define ROOT_MAILBOX_INPUT_S_BASE (ROOT_MAILBOX_OUTPUT_S_BASE - ROOT_MAILBOX_SIZE) - -// SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S is defined in sl_trustzone_secure_config.h -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) \ - || (defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S) && SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) - -#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_S_MEM_BASE - -#define ROOT_MAILBOX_OUTPUT_BASE SYSCFG->ROOTDATA1; -#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED ROOT_MAILBOX_OUTPUT_S_BASE -#else -#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_NS_MEM_BASE - -// VSE will always output the secure address, if NS is desired, caculate the NS address. -#define ROOT_MAILBOX_OUTPUT_BASE (SYSCFG->ROOTDATA1 - RDMEM_FRCRAM_S_MEM_BASE + RDMEM_FRCRAM_NS_MEM_BASE); -#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED (RDMEM_FRCRAM_NS_MEM_END + 1 - ROOT_MAILBOX_SIZE) -#endif -#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - ROOT_MAILBOX_SIZE) - -/* Position of parameter number field in VSE Input Mailbox LENGTH field.*/ -#define ROOT_MB_LENGTH_PARAM_NUM_SHIFT (24) - -/* Done flag indicating that the VSE Mailbox handler has completed - processing the mailbox command. */ -#define ROOT_MB_DONE (1 << 23) - -/* VSE Configuration Status bits mask */ -#define ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK (0xFFFF) - -#endif // #if defined(CRYPTOACC_PRESENT) -/** @endcond */ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ -#if defined(CRYPTOACC_PRESENT) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -// VSE Input Mailbox structure -typedef struct { - volatile uint32_t magic; - volatile uint32_t command; - volatile uint32_t length; - volatile uint32_t data[0]; -} root_InputMailbox_t; - -// VSE Output Mailbox structure -typedef struct { - volatile uint32_t magic; - volatile uint32_t version; - volatile uint32_t status; - volatile uint32_t command; - volatile uint32_t length; - volatile uint32_t data[0]; -} root_OutputMailbox_t; -/** @endcond */ - -#endif // #if defined(CRYPTOACC_PRESENT) - -/******************************************************************************* - ************************** STATIC FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Write to FIFO - * - * @param value - * Value to write to FIFO - ******************************************************************************/ -#if defined(_SEMAILBOX_FIFO_RESETVALUE) -__STATIC_INLINE void writeToFifo(uint32_t value) -{ - SEMAILBOX_HOST->FIFO = value; -} -#else -__STATIC_INLINE void writeToFifo(uint32_t value) -{ - SEMAILBOX_HOST->FIFO[0].DATA = value; -} -#endif - -#endif // SEMAILBOX_PRESENT - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Add input data to a command - * - * @details - * This function adds a buffer of input data to the given SE command structure - * The buffer gets appended by reference at the end of the list of already - * added buffers. - * - * @note - * Note that this function does not copy either the data buffer or the buffer - * structure, so make sure to keep the data object in scope until the command - * has been executed by the secure element. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @param[in] data - * Pointer to a data transfer structure. - ******************************************************************************/ -void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data) -{ - if (command->data_in == NULL) { - command->data_in = data; - } else { - SE_DataTransfer_t *next = command->data_in; - while (next->next != (void*)SE_DATATRANSFER_STOP) { - next = (SE_DataTransfer_t*)next->next; - } - next->next = data; - } -} - -/***************************************************************************//** - * @brief - * Add output data to a command - * - * @details - * This function adds a buffer of output data to the given command structure - * The buffer gets appended by reference at the end of the list of already - * added buffers. - * - * @note - * Note that this function does not copy either the data buffer or the buffer - * structure, so make sure to keep the data object in scope until the command - * has been executed by the secure element. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @param[in] data - * Pointer to a data transfer structure. - ******************************************************************************/ -void SE_addDataOutput(SE_Command_t *command, - SE_DataTransfer_t *data) -{ - if (command->data_out == NULL) { - command->data_out = data; - } else { - SE_DataTransfer_t *next = command->data_out; - while (next->next != (void*)SE_DATATRANSFER_STOP) { - next = (SE_DataTransfer_t*)next->next; - } - next->next = data; - } -} - -/***************************************************************************//** - * @brief - * Add a parameter to a command - * - * @details - * This function adds a parameter word to the passed command. - * - * @note - * Make sure to not exceed @ref SE_MAX_PARAMETERS. - * - * @param[in] command - * Pointer to a filled-out SE command structure. - * @param[in] parameter - * Parameter to add. - ******************************************************************************/ -void SE_addParameter(SE_Command_t *command, uint32_t parameter) -{ - if (command->num_parameters >= SE_MAX_PARAMETERS) { - EFM_ASSERT(command->num_parameters < SE_MAX_PARAMETERS); - return; - } - - command->parameters[command->num_parameters] = parameter; - command->num_parameters += 1; -} - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * Execute the passed command - * - * @details - * This function starts the execution of the passed command by the secure - * element. When started, wait for the RXINT interrupt flag, or call - * @ref SE_waitCommandCompletion to busy-wait. After completion, you have to - * call @ref SE_readCommandResponse to get the command's execution status. - * - * @param[in] command - * Pointer to a filled-out SE command structure. - ******************************************************************************/ -void SE_executeCommand(SE_Command_t *command) -{ - // Don't overflow our struct - if (command->num_parameters > SE_MAX_PARAMETERS) { - EFM_ASSERT(command->num_parameters <= SE_MAX_PARAMETERS); - return; - } - -#if defined(SEMAILBOX_PRESENT) - - // Wait for room available in the mailbox - while (!(SEMAILBOX_HOST->TX_STATUS & SEMAILBOX_TX_STATUS_TXINT)) ; - - // Write header to start transaction - SEMAILBOX_HOST->TX_HEADER = sizeof(uint32_t) * (4 + command->num_parameters); - - // Write command into FIFO - writeToFifo(command->command); - - // Write DMA descriptors into FIFO - writeToFifo((uint32_t)command->data_in); - writeToFifo((uint32_t)command->data_out); - - // Write applicable parameters into FIFO - for (size_t i = 0; i < command->num_parameters; i++) { - writeToFifo(command->parameters[i]); - } - -#elif defined(CRYPTOACC_PRESENT) - // Prepare the VSE Mailbox within a critical section to prevent - // the process from getting interrupted. At this point, the only option - // we have is to go through a reset, so it is safe to enter the critical section. - (void)CORE_EnterCritical(); - - // Setup pointer to the VSE Mailbox Input data structure - // (must be stored in a RAM area which is not used by the VSE) - root_InputMailbox_t *rootInMb = (root_InputMailbox_t*)ROOT_MAILBOX_INPUT_BASE; - uint32_t *mbData; - unsigned int mbDataLen, inDataLen, i; - SE_DataTransfer_t *inDataDesc; - uint32_t *inData; - uint32_t checksum; - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - - // Store the secure memory base addresses for VSE to be able to read from the address - // Set base of Mailbox Input data structure in SYSCFG register in order - // for VSE to find it. - SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_S_BASE; - // Set base of Mailbox Output data structure in SYSCFG register in order - // for VSE to know where to write output data. - // Write command into FIFO - SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_S_BASE; - - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - rootInMb->magic = SE_RESPONSE_MAILBOX_VALID; - rootInMb->command = command->command; - - // Write applicable parameters into Mailbox DATA array - mbData = (uint32_t*) rootInMb->data; - for (mbDataLen = 0; mbDataLen < command->num_parameters; mbDataLen++) { - mbData[mbDataLen] = command->parameters[mbDataLen]; - } - - // Write input data into Mailbox DATA array - inDataLen = 0; - for (inDataDesc = command->data_in; inDataDesc; inDataDesc = (SE_DataTransfer_t*) inDataDesc->next) { - inData = (uint32_t*) inDataDesc->data; - for (i = 0; i < (inDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); i++) { - // Make sure we do not overflow the input mailbox. - EFM_ASSERT(mbDataLen < ROOT_MAILBOX_SIZE); - mbData[mbDataLen++] = inData[i]; - inDataLen++; - } - if (inDataDesc->next == (void*)SE_DATATRANSFER_STOP) { - break; - } - } - - // Write number of parameters and data words to 'length' field of mailbox. - rootInMb->length = - inDataLen | (command->num_parameters << ROOT_MB_LENGTH_PARAM_NUM_SHIFT); - - // Calculate checksum using bitwise XOR over the all words in the mailbox - // data structure, minus the CHECKSUM word (32bit = 4bytes ) at the end. - checksum = rootInMb->magic; - checksum ^= rootInMb->command; - checksum ^= rootInMb->length; - for (i = 0; i < mbDataLen; i++) { - checksum ^= mbData[i]; - } - - // Finally, write the calculated checksum to mailbox checksum field - mbData[mbDataLen] = checksum; - - __NVIC_SystemReset(); - -#endif // #if defined(SEMAILBOX_PRESENT) -} - -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(CRYPTOACC_PRESENT) -/***************************************************************************//** - * @brief - * Check whether the VSE Output Mailbox is valid. - * - * @return True if the VSE Output Mailbox is valid (magic and checksum OK) - ******************************************************************************/ -bool rootIsOutputMailboxValid(void) -{ - // Setup pointer to the VSE Output Mailbox data structure - // (must be stored in a RAM area which is not used by the VSE) - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if ((uint32_t)rootOutMb > ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - || (uint32_t)rootOutMb < RDMEM_FRCRAM_MEM_BASE) { - return false; - } - - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - uint32_t *mbPtr = (uint32_t*) rootOutMb; - uint32_t checksum; - unsigned int mbLen, cnt; - - // Verify magic word of mailbox - if (rootOutMb->magic != SE_RESPONSE_MAILBOX_VALID) { - return false; - } - - // Get length of mailbox - mbLen = sizeof(root_OutputMailbox_t) / sizeof(uint32_t) + rootOutMb->length; - if (mbLen >= ROOT_MAILBOX_SIZE) { - return false; - } - // Calculate checksum using bitwise XOR over all words in the mailbox - // data structure, minus the CHECKSUM word at the end. - for (checksum = 0, cnt = 0; cnt < mbLen; cnt++) { - checksum ^= mbPtr[cnt]; - } - - // Verify that the calculated checksum is equal to the mailbox checksum. - return (mbPtr[mbLen] == checksum); -} - -/***************************************************************************//** - * @brief - * Get current SE version - * - * @details - * This function returns the current VSE version - * - * @param[in] version - * Pointer to location where to copy the version of VSE to. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_getVersion(uint32_t *version) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (version == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Return the 'version' from the Output Mailbox - *version = rootOutMb->version; - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Get VSE configuration and status bits - * - * @details - * This function returns the current VSE configuration and status bits. - * The following list explains what the different bits in cfgStatus indicate. - * A bit value of 1 means enabled, while 0 means disabled: - * * [0]: Secure boot - * * [1]: Verify secure boot certificate - * * [2]: Anti-rollback - * * [3]: Narrow page lock - * * [4]: Full page lock - * The following status bits can be read with VSE versions - * higher than 1.2.2. - * * [10]: Debug port lock - * * [11]: Device erase enabled - * * [12]: Secure debug enabled - * * [15]: Debug port register state, 1 if the debug port is locked. - * - * @param[out] cfgStatus - * Pointer to location to copy Configuration Status bits into. - * - * @note - * This function will check that the mailbox content is valid before - * reading the status bits. If the command response has already been read - * with a call to @ref SE_ackCommand(), the validity check will fail, and - * the config status bits cannot be read before a reset has occurred. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (cfgStatus == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Return the configuration status bits - *cfgStatus = rootOutMb->status & ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK; - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Get the version number of the OTP from the status field of the output - * mailbox - * @details - * This function checks if the OTP version number flag is set in the output - * mailbox. If it is, the version number is writen to @ref otpVersion pointer - * location. If not, it returns error response. - * - * @param[out] otpVersion - * Pointer to location to copy OTP version number into. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - ******************************************************************************/ -SE_Response_t SE_getOTPVersion(uint32_t *otpVersion) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (otpVersion == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - bool isOTPVersionSet = rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_SET; - if (isOTPVersionSet) { - // Return the OTP version from the status field. - *otpVersion = (rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_MASK) >> SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT; - } else { - return SE_RESPONSE_INVALID_COMMAND; - } - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Check whether the running command has completed. - * - * @details - * This function polls the SE-to-host mailbox interrupt flag. - * - * @return True if a command has completed and the result is available - ******************************************************************************/ -bool SE_isCommandCompleted(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the response is ok - if (!rootIsOutputMailboxValid()) { - return false; - } - - // Check status MB_DONE flag of the mailbox - return ((rootOutMb->status & ROOT_MB_DONE) == ROOT_MB_DONE); -} - -/***************************************************************************//** - * @brief - * Read the previously executed command. - * - * @details - * This function reads the previously executed command. - * - * @return - * One of the SE command words. - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid. - ******************************************************************************/ -uint32_t SE_readExecutedCommand(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - return rootOutMb->command; -} - -/***************************************************************************//** - * @brief - * Read the status of the previously executed command. - * - * @details - * This function reads the status of the previously executed command. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully or a signature - * was successfully verified, - * SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, e.g. - * because of conflicting Secure/Non-Secure memory accesses, - * SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_readCommandResponse(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - return (SE_Response_t)(rootOutMb->status & SE_RESPONSE_MASK); -} - -/***************************************************************************//** - * @brief - * Acknowledge and get status and output data of a completed command. - * - * @details - * This function acknowledges and gets the status and output data of a - * completed mailbox command. - * The mailbox command is acknowledged by inverting all bits in the checksum - * (XOR with 0xFFFFFFFF). - * The output data is copied into the linked list of output buffers pointed - * to in the given command data structure. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * @retval SE_RESPONSE_MAILBOX_INVALID when mailbox command not done or invalid - ******************************************************************************/ -SE_Response_t SE_ackCommand(SE_Command_t *command) -{ - // Setup pointer to the VSE Output Mailbox data structure - // (must be stored in a RAM area which is not used by the VSE) - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - uint32_t *mbData = (uint32_t*) rootOutMb->data; - SE_DataTransfer_t *outDataDesc = command->data_out; - unsigned int outDataLen, outDataCnt, i, outDescLen; - uint32_t *outData; - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Get output data length - outDataLen = rootOutMb->length; - - // Acknowledge the output mailbox response by invalidating checksum - mbData[outDataLen] ^= 0xFFFFFFFFUL; - - // Check command status code - if ((rootOutMb->status & SE_RESPONSE_MASK) != SE_RESPONSE_OK) { - return rootOutMb->status & SE_RESPONSE_MASK; - } - - // Copy data from the Output Mailbox to the linked list of output - // buffers provided by the user - outDataCnt = 0; - while (outDataDesc && (outDataCnt < outDataLen)) { - outData = (uint32_t*) outDataDesc->data; - outDescLen = - (outDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); - for (i = 0; (i < outDescLen) && (outDataCnt < outDataLen); i++) { - outData[i] = mbData[outDataCnt++]; - } - // If we have reached the end of a buffer, go to next buffer descriptor - if (i == outDescLen) { - outDataDesc = (SE_DataTransfer_t*) - ((uint32_t)outDataDesc->next & ~SE_DATATRANSFER_STOP); - } - } - - // Check if the output data list is too small to copy all output data in - // mailbox. - if ((outDataDesc == 0) && (outDataCnt < outDataLen)) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - return SE_RESPONSE_OK; -} - -#endif // #if defined(CRYPTOACC_PRESENT) - -/******************************************************************************* - ***************************** DEPRECATED ********************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup se_deprecated - * - * @{ - ******************************************************************************/ - -/******************************************************************************* -* The following functions have been deprecated and will be removed in a future -* version of emlib. All high-level functionality have been moved to the SE -* manager. -*******************************************************************************/ - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Init pubkey or pubkey signature. - * - * @details - * Initialize public key stored in the SE, or its corresponding signature. The - * command can be used to write: - * * SE_KEY_TYPE_BOOT -- public key used to perform secure boot - * * SE_KEY_TYPE_AUTH -- public key used to perform secure debug - * - * @note - * These keys can not be overwritten, so this command can only be issued once - * per key per part. - * - * @param[in] key_type - * ID of key type to initialize. - * - * @param[in] pubkey - * Pointer to a buffer that contains the public key or signature. - * Must be word aligned and have a length of 64 bytes. - * - * @param[in] numBytes - * Length of pubkey buffer (64 bytes). - * - * @param[in] signature - * If true, initialize signature for the specified key type instead of the - * public key itself. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed - ******************************************************************************/ -SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) -{ - uint32_t commandWord = SE_COMMAND_INIT_PUBKEY; - SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; - - EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) - || (key_type == SE_KEY_TYPE_AUTH)); - - EFM_ASSERT(numBytes == 64); - EFM_ASSERT(!((size_t)pubkey & 3U)); - - // Find parity word - volatile uint32_t parity = 0; - for (size_t i = 0; i < numBytes / 4; i++) { - parity = parity ^ ((uint32_t *)pubkey)[i]; - } - - // SE command structures -#if defined(SEMAILBOX_PRESENT) - commandWord = - (signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY; -#elif defined(CRYPTOACC_PRESENT) - (void)signature; -#endif - SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); - - SE_DataTransfer_t parityData = SE_DATATRANSFER_DEFAULT(&parity, 4); - SE_addDataInput(&command, &parityData); - - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); - SE_addDataInput(&command, &pubkeyData); - - SE_executeCommand(&command); -#if defined(SEMAILBOX_PRESENT) - res = SE_readCommandResponse(); -#endif - return res; -} - -/***************************************************************************//** - * @brief - * - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Initialize SE one-time-programmable (OTP) configuration. - * - * @details - * Configuration is performed by setting the desired options in the - * @ref SE_OTPInit_t structure. - * - * This function can be used to enable secure boot, to configure flash page - * locking, and to enable anti-rollback protection when using the SE to - * perform an application upgrade, typically a Gecko bootloader upgrade. - * - * Before secure boot can be enabled, the public key used for secure boot - * verification must be uploaded using @ref SE_initPubkey(). - * - * @warning - * This command can only be executed once per device! When the configuration - * has been programmed it is not possible to update any of the fields. - * - * @param[in] otp_init - * @ref SE_OTPInit_t structure containing the SE configuration. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - ******************************************************************************/ -SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) -{ - uint32_t mcuSettingsFlags = 0; - - SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; - - if (otp_init->enableSecureBoot) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; - -#if defined(SEMAILBOX_PRESENT) - uint8_t pubkey[64]; - { - EFM_ASSERT(!((size_t)pubkey & 3U)); - // SE command structures - SE_Command_t commandPubkeyRead = SE_COMMAND_DEFAULT(SE_COMMAND_READ_PUBKEY | SE_KEY_TYPE_BOOT); - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, sizeof(pubkey)); - SE_addDataOutput(&commandPubkeyRead, &pubkeyData); - SE_executeCommand(&commandPubkeyRead); - res = SE_readCommandResponse(); - if (res != SE_RESPONSE_OK) { - return SE_RESPONSE_ABORT; - } - res = SE_RESPONSE_INVALID_COMMAND; - } -#endif - } - if (otp_init->verifySecureBootCertificate) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; - } - if (otp_init->enableAntiRollback) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; - } - - if (otp_init->secureBootPageLockNarrow && otp_init->secureBootPageLockFull) { - return SE_RESPONSE_ABORT; - } - if (otp_init->secureBootPageLockNarrow) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; - } - if (otp_init->secureBootPageLockFull) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; - } - - // Find parity word - volatile uint32_t parity = 0; - parity = parity ^ mcuSettingsFlags; - - volatile uint32_t parameters[2] = { - parity, - sizeof(mcuSettingsFlags) - }; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_INIT_OTP); - -#if defined(SEMAILBOX_PRESENT) - static struct ReservedSettings { - uint8_t reserved1[16]; - uint8_t reserved2[2]; - uint8_t reserved3[2]; - } reservedSettings = { - { 0x00 }, - { 0xFF }, - { 0x00 } - }; - - for (size_t i = 0; i < 5; i++) { - parity = parity ^ ((uint32_t*)(&reservedSettings))[i]; - } - parameters[0] = parity; - parameters[1] = parameters[1] + sizeof(reservedSettings); - - SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(&command, ¶metersData); - - SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); - SE_addDataInput(&command, &mcuSettingsFlagsData); - - SE_DataTransfer_t reservedSettingsData = SE_DATATRANSFER_DEFAULT((volatile void *)&reservedSettings, sizeof(reservedSettings)); - SE_addDataInput(&command, &reservedSettingsData); - - SE_executeCommand(&command); - - res = SE_readCommandResponse(); -#elif defined(CRYPTOACC_PRESENT) - SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(&command, ¶metersData); - - SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); - SE_addDataInput(&command, &mcuSettingsFlagsData); - - SE_executeCommand(&command); -#else - (void)command; - (void)parameters; -#endif - - return res; -} - -#if defined(SEMAILBOX_PRESENT) - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Writes data to User Data section in MTP. Write data must be aligned to - * word size and contain a number of bytes that is divisable by four. - * - * @note - * It is recommended to erase the flash page before performing a write. - * - * @param[in] offset - * Offset to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -SE_Response_t SE_writeUserData(uint32_t offset, - void *data, - uint32_t numBytes) -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_WRITE_USER_DATA); - SE_DataTransfer_t userData = SE_DATATRANSFER_DEFAULT(data, numBytes); - - SE_addDataInput(&command, &userData); - - SE_addParameter(&command, offset); - SE_addParameter(&command, numBytes); - - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Erases User Data section in MTP. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -SE_Response_t SE_eraseUserData() -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_ERASE_USER_DATA); - - SE_addParameter(&command, SE_COMMAND_OPTION_ERASE_UD); - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Returns the current boot status, versions and system configuration. - * - * @param[out] status - * @ref SE_Status_t containing current SE status. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK upon command completion. Errors are encoded in the - * different parts of the returned status object. - ******************************************************************************/ -SE_Response_t SE_getStatus(SE_Status_t *status) -{ - volatile uint32_t output[9] = { 0 }; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_GET_STATUS); - SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT((void*)output, 4 * 9); - - SE_addDataOutput(&command, &outData); - - // Execute command and return response - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - - // Update status object - status->bootStatus = output[4]; - status->seFwVersion = output[5]; - status->hostFwVersion = output[6]; - - SE_DebugStatus_t debugStatus; - debugStatus.debugLockEnabled = (output[7] & (1 << 0)); - debugStatus.deviceEraseEnabled = (output[7] & (1 << 1)); - debugStatus.secureDebugEnabled = (output[7] & (1 << 2)); - status->debugStatus = debugStatus; - - status->secureBootEnabled = ((output[8] & 0x1) && ((output[8] & ~0x1) == 0)); - - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Read the serial number of the SE module. - * - * @param[out] serial - * Pointer to array of size 16 bytes. - * - * @return - * One of the @ref SE_Response_t return codes. - * @retval SE_RESPONSE_OK when serial number is returned successfully, - * @retval SE_RESPONSE_INTERNAL_ERROR if not. - ******************************************************************************/ -SE_Response_t SE_serialNumber(void *serial) -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_READ_SERIAL); - SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT(serial, 16); - - SE_addDataOutput(&command, &outData); - - // Execute command and return response - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Read pubkey or pubkey signature. - * - * @details - * Read out a public key stored in the SE, or its signature. The command can - * be used to read: - * * SE_KEY_TYPE_BOOT - * * SE_KEY_TYPE_AUTH - * - * @param[in] key_type - * ID of key type to read. - * - * @param[out] pubkey - * Pointer to a buffer to contain the returned public key. - * Must be word aligned and have a length of 64 bytes. - * - * @param[in] numBytes - * Length of pubkey buffer (64 bytes). - * - * @param[in] signature - * If true, the function will return the signature programmed for the - * specified public key instead of the public key itself. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed - ******************************************************************************/ -SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) -{ - EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) - || (key_type == SE_KEY_TYPE_AUTH)); - - EFM_ASSERT(numBytes == 64); - EFM_ASSERT(!((size_t)pubkey & 3U)); - - // SE command structures - uint32_t commandWord = - (signature) ? SE_COMMAND_READ_PUBKEY_SIGNATURE : SE_COMMAND_READ_PUBKEY; - SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); - - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); - SE_addDataOutput(&command, &pubkeyData); - - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Returns the current debug lock configuration. - * @param[out] status - * The command returns a @ref SE_DebugStatus_t with the current status of the - * debug configuration. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there are configuration errors. - ******************************************************************************/ -SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) -{ - SE_Response_t res; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_STATUS); - - volatile uint32_t status_word = 0; - SE_DataTransfer_t statusData = SE_DATATRANSFER_DEFAULT((void*)&status_word, 4); - SE_addDataOutput(&command, &statusData); - - SE_executeCommand(&command); - res = SE_readCommandResponse(); - - status->debugLockEnabled = (status_word & (1 << 0)); - status->deviceEraseEnabled = (status_word & (1 << 1)); - status->secureDebugEnabled = (status_word & (1 << 2)); - - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Enables the debug lock for the part. - * @details - * The debug port will be closed and the only way to open it is through - * device erase (if enabled) or temporarily through secure debug unlock (if - * enabled). - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR there was a problem locking the debug port. - ******************************************************************************/ -SE_Response_t SE_debugLockApply(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_APPLY); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Enables the secure debug functionality. - * @details - * Enables the secure debug functionality. This functionality makes it - * possible to open a locked debug port by signing a cryptographic challenge - * and using the debug command interface (DCI). - * - * This command can only be executed before the debug port is locked, and - * after a secure debug public key has been installed in the SE using - * @ref SE_initPubkey() or the corresponding DCI command. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INVALID_COMMAND if debug port is locked. - * @retval SE_RESPONSE_INVALID_PARAMETER if secure debug certificates are - * missing. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_debugSecureEnable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_ENABLE_SECURE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Disables the secure debug functionality. - * @details - * Disables the secure debug functionality that can be used to open a - * locked debug port. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_debugSecureDisable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_DISABLE_SECURE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Performs a device mass erase and debug unlock. - * - * @details - * Performs a device mass erase and resets the debug configuration to its - * initial unlocked state. Only available before @ref SE_deviceEraseDisable or - * the corresponding DCI command has been executed. - * - * @note - * This command clears and verifies the complete flash and ram of the - * system, excluding the user data pages and one-time programmable - * commissioning information in the secure element. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INVALID_COMMAND if device erase is disabled. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_deviceErase(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Disabled device erase functionality. - * - * @details - * This command disables the device erase command. It does not lock the - * debug interface to the part, but it is a permanent action for the part. - * If device erase is disabled and the device is debug locked, there is no - * way to permanently unlock the part. If secure debug unlock is enabled, - * secure debug unlock can still be used to temporarily open the debug port. - * - * @warning - * This command permanently disables the device erase functionality! - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_deviceEraseDisable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE_DISABLE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -#endif // #if defined(SEMAILBOX_PRESENT) -#endif // #if !defined(SLI_EM_SE_HOST) - -/** @} (end addtogroup deprecated_se) */ -/** @} (end addtogroup se) */ - -#endif /* defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Secure Element API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_se.h" + +#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#include "em_core.h" +#include "sl_assert.h" +#include "em_system.h" + +#endif + +/***************************************************************************//** + * @addtogroup se + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* OTP initialization structure defines. */ +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) + +#if defined(CRYPTOACC_PRESENT) + +/// Signal that OTP version is incorporated into the status field of the output +#define SE_VSE_REPLY_STATUS_OTP_VERSION_SET (1 << 21) +/// Mask defining the region of the status field that contains the OTP version +/// number. +#define SE_VSE_REPLY_STATUS_OTP_VERSION_MASK (0xFF000000UL) +/// Shift to insert a number into the otp version part of the status field +#define SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT (24) + +/* Size of VSE Mailbox instance. + There are two instances, input and output. */ +#define ROOT_MAILBOX_SIZE (512UL) + +/* Base addresses of the VSE Input and Output Mailbox data structures. + (Must be stored in a RAM area which is not used by the VSE) + We use the upper 1KB of FRC RAM for the VSE mailboxes. */ +#define ROOT_MAILBOX_OUTPUT_S_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE) +#define ROOT_MAILBOX_INPUT_S_BASE (ROOT_MAILBOX_OUTPUT_S_BASE - ROOT_MAILBOX_SIZE) + +// SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S is defined in sl_trustzone_secure_config.h +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) \ + || (defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S) && SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) + +#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_S_MEM_BASE + +#define ROOT_MAILBOX_OUTPUT_BASE SYSCFG->ROOTDATA1; +#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED ROOT_MAILBOX_OUTPUT_S_BASE +#else +#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_NS_MEM_BASE + +// VSE will always output the secure address, if NS is desired, caculate the NS address. +#define ROOT_MAILBOX_OUTPUT_BASE (SYSCFG->ROOTDATA1 - RDMEM_FRCRAM_S_MEM_BASE + RDMEM_FRCRAM_NS_MEM_BASE); +#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED (RDMEM_FRCRAM_NS_MEM_END + 1 - ROOT_MAILBOX_SIZE) +#endif +#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - ROOT_MAILBOX_SIZE) + +/* Position of parameter number field in VSE Input Mailbox LENGTH field.*/ +#define ROOT_MB_LENGTH_PARAM_NUM_SHIFT (24) + +/* Done flag indicating that the VSE Mailbox handler has completed + processing the mailbox command. */ +#define ROOT_MB_DONE (1 << 23) + +/* VSE Configuration Status bits mask */ +#define ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK (0xFFFF) + +#endif // #if defined(CRYPTOACC_PRESENT) +/** @endcond */ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ +#if defined(CRYPTOACC_PRESENT) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +// VSE Input Mailbox structure +typedef struct { + volatile uint32_t magic; + volatile uint32_t command; + volatile uint32_t length; + volatile uint32_t data[0]; +} root_InputMailbox_t; + +// VSE Output Mailbox structure +typedef struct { + volatile uint32_t magic; + volatile uint32_t version; + volatile uint32_t status; + volatile uint32_t command; + volatile uint32_t length; + volatile uint32_t data[0]; +} root_OutputMailbox_t; +/** @endcond */ + +#endif // #if defined(CRYPTOACC_PRESENT) + +/******************************************************************************* + ************************** STATIC FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Write to FIFO + * + * @param value + * Value to write to FIFO + ******************************************************************************/ +#if defined(_SEMAILBOX_FIFO_RESETVALUE) +__STATIC_INLINE void writeToFifo(uint32_t value) +{ + SEMAILBOX_HOST->FIFO = value; +} +#else +__STATIC_INLINE void writeToFifo(uint32_t value) +{ + SEMAILBOX_HOST->FIFO[0].DATA = value; +} +#endif + +#endif // SEMAILBOX_PRESENT + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Add input data to a command + * + * @details + * This function adds a buffer of input data to the given SE command structure + * The buffer gets appended by reference at the end of the list of already + * added buffers. + * + * @note + * Note that this function does not copy either the data buffer or the buffer + * structure, so make sure to keep the data object in scope until the command + * has been executed by the secure element. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @param[in] data + * Pointer to a data transfer structure. + ******************************************************************************/ +void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data) +{ + if (command->data_in == NULL) { + command->data_in = data; + } else { + SE_DataTransfer_t *next = command->data_in; + while (next->next != (void*)SE_DATATRANSFER_STOP) { + next = (SE_DataTransfer_t*)next->next; + } + next->next = data; + } +} + +/***************************************************************************//** + * @brief + * Add output data to a command + * + * @details + * This function adds a buffer of output data to the given command structure + * The buffer gets appended by reference at the end of the list of already + * added buffers. + * + * @note + * Note that this function does not copy either the data buffer or the buffer + * structure, so make sure to keep the data object in scope until the command + * has been executed by the secure element. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @param[in] data + * Pointer to a data transfer structure. + ******************************************************************************/ +void SE_addDataOutput(SE_Command_t *command, + SE_DataTransfer_t *data) +{ + if (command->data_out == NULL) { + command->data_out = data; + } else { + SE_DataTransfer_t *next = command->data_out; + while (next->next != (void*)SE_DATATRANSFER_STOP) { + next = (SE_DataTransfer_t*)next->next; + } + next->next = data; + } +} + +/***************************************************************************//** + * @brief + * Add a parameter to a command + * + * @details + * This function adds a parameter word to the passed command. + * + * @note + * Make sure to not exceed @ref SE_MAX_PARAMETERS. + * + * @param[in] command + * Pointer to a filled-out SE command structure. + * @param[in] parameter + * Parameter to add. + ******************************************************************************/ +void SE_addParameter(SE_Command_t *command, uint32_t parameter) +{ + if (command->num_parameters >= SE_MAX_PARAMETERS) { + EFM_ASSERT(command->num_parameters < SE_MAX_PARAMETERS); + return; + } + + command->parameters[command->num_parameters] = parameter; + command->num_parameters += 1; +} + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * Execute the passed command + * + * @details + * This function starts the execution of the passed command by the secure + * element. When started, wait for the RXINT interrupt flag, or call + * @ref SE_waitCommandCompletion to busy-wait. After completion, you have to + * call @ref SE_readCommandResponse to get the command's execution status. + * + * @param[in] command + * Pointer to a filled-out SE command structure. + ******************************************************************************/ +void SE_executeCommand(SE_Command_t *command) +{ + // Don't overflow our struct + if (command->num_parameters > SE_MAX_PARAMETERS) { + EFM_ASSERT(command->num_parameters <= SE_MAX_PARAMETERS); + return; + } + +#if defined(SEMAILBOX_PRESENT) + + // Wait for room available in the mailbox + while (!(SEMAILBOX_HOST->TX_STATUS & SEMAILBOX_TX_STATUS_TXINT)) ; + + // Write header to start transaction + SEMAILBOX_HOST->TX_HEADER = sizeof(uint32_t) * (4 + command->num_parameters); + + // Write command into FIFO + writeToFifo(command->command); + + // Write DMA descriptors into FIFO + writeToFifo((uint32_t)command->data_in); + writeToFifo((uint32_t)command->data_out); + + // Write applicable parameters into FIFO + for (size_t i = 0; i < command->num_parameters; i++) { + writeToFifo(command->parameters[i]); + } + +#elif defined(CRYPTOACC_PRESENT) + // Prepare the VSE Mailbox within a critical section to prevent + // the process from getting interrupted. At this point, the only option + // we have is to go through a reset, so it is safe to enter the critical section. + (void)CORE_EnterCritical(); + + // Setup pointer to the VSE Mailbox Input data structure + // (must be stored in a RAM area which is not used by the VSE) + root_InputMailbox_t *rootInMb = (root_InputMailbox_t*)ROOT_MAILBOX_INPUT_BASE; + uint32_t *mbData; + unsigned int mbDataLen, inDataLen, i; + SE_DataTransfer_t *inDataDesc; + uint32_t *inData; + uint32_t checksum; + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + // Store the secure memory base addresses for VSE to be able to read from the address + // Set base of Mailbox Input data structure in SYSCFG register in order + // for VSE to find it. + SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_S_BASE; + // Set base of Mailbox Output data structure in SYSCFG register in order + // for VSE to know where to write output data. + // Write command into FIFO + SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_S_BASE; + + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + rootInMb->magic = SE_RESPONSE_MAILBOX_VALID; + rootInMb->command = command->command; + + // Write applicable parameters into Mailbox DATA array + mbData = (uint32_t*) rootInMb->data; + for (mbDataLen = 0; mbDataLen < command->num_parameters; mbDataLen++) { + mbData[mbDataLen] = command->parameters[mbDataLen]; + } + + // Write input data into Mailbox DATA array + inDataLen = 0; + for (inDataDesc = command->data_in; inDataDesc; inDataDesc = (SE_DataTransfer_t*) inDataDesc->next) { + inData = (uint32_t*) inDataDesc->data; + for (i = 0; i < (inDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); i++) { + // Make sure we do not overflow the input mailbox. + EFM_ASSERT(mbDataLen < ROOT_MAILBOX_SIZE); + mbData[mbDataLen++] = inData[i]; + inDataLen++; + } + if (inDataDesc->next == (void*)SE_DATATRANSFER_STOP) { + break; + } + } + + // Write number of parameters and data words to 'length' field of mailbox. + rootInMb->length = + inDataLen | (command->num_parameters << ROOT_MB_LENGTH_PARAM_NUM_SHIFT); + + // Calculate checksum using bitwise XOR over the all words in the mailbox + // data structure, minus the CHECKSUM word (32bit = 4bytes ) at the end. + checksum = rootInMb->magic; + checksum ^= rootInMb->command; + checksum ^= rootInMb->length; + for (i = 0; i < mbDataLen; i++) { + checksum ^= mbData[i]; + } + + // Finally, write the calculated checksum to mailbox checksum field + mbData[mbDataLen] = checksum; + + __NVIC_SystemReset(); + +#endif // #if defined(SEMAILBOX_PRESENT) +} + +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @brief + * Check whether the VSE Output Mailbox is valid. + * + * @return True if the VSE Output Mailbox is valid (magic and checksum OK) + ******************************************************************************/ +bool rootIsOutputMailboxValid(void) +{ + // Setup pointer to the VSE Output Mailbox data structure + // (must be stored in a RAM area which is not used by the VSE) + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if ((uint32_t)rootOutMb > ROOT_MAILBOX_OUTPUT_BASE_EXPECTED + || (uint32_t)rootOutMb < RDMEM_FRCRAM_MEM_BASE) { + return false; + } + + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + uint32_t *mbPtr = (uint32_t*) rootOutMb; + uint32_t checksum; + unsigned int mbLen, cnt; + + // Verify magic word of mailbox + if (rootOutMb->magic != SE_RESPONSE_MAILBOX_VALID) { + return false; + } + + // Get length of mailbox + mbLen = sizeof(root_OutputMailbox_t) / sizeof(uint32_t) + rootOutMb->length; + if (mbLen >= ROOT_MAILBOX_SIZE) { + return false; + } + // Calculate checksum using bitwise XOR over all words in the mailbox + // data structure, minus the CHECKSUM word at the end. + for (checksum = 0, cnt = 0; cnt < mbLen; cnt++) { + checksum ^= mbPtr[cnt]; + } + + // Verify that the calculated checksum is equal to the mailbox checksum. + return (mbPtr[mbLen] == checksum); +} + +/***************************************************************************//** + * @brief + * Get current SE version + * + * @details + * This function returns the current VSE version + * + * @param[in] version + * Pointer to location where to copy the version of VSE to. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_getVersion(uint32_t *version) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (version == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Return the 'version' from the Output Mailbox + *version = rootOutMb->version; + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Get VSE configuration and status bits + * + * @details + * This function returns the current VSE configuration and status bits. + * The following list explains what the different bits in cfgStatus indicate. + * A bit value of 1 means enabled, while 0 means disabled: + * * [0]: Secure boot + * * [1]: Verify secure boot certificate + * * [2]: Anti-rollback + * * [3]: Narrow page lock + * * [4]: Full page lock + * The following status bits can be read with VSE versions + * higher than 1.2.2. + * * [10]: Debug port lock + * * [11]: Device erase enabled + * * [12]: Secure debug enabled + * * [15]: Debug port register state, 1 if the debug port is locked. + * + * @param[out] cfgStatus + * Pointer to location to copy Configuration Status bits into. + * + * @note + * This function will check that the mailbox content is valid before + * reading the status bits. If the command response has already been read + * with a call to @ref SE_ackCommand(), the validity check will fail, and + * the config status bits cannot be read before a reset has occurred. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (cfgStatus == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Return the configuration status bits + *cfgStatus = rootOutMb->status & ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK; + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Get the version number of the OTP from the status field of the output + * mailbox + * @details + * This function checks if the OTP version number flag is set in the output + * mailbox. If it is, the version number is writen to @ref otpVersion pointer + * location. If not, it returns error response. + * + * @param[out] otpVersion + * Pointer to location to copy OTP version number into. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + ******************************************************************************/ +SE_Response_t SE_getOTPVersion(uint32_t *otpVersion) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (otpVersion == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + bool isOTPVersionSet = rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_SET; + if (isOTPVersionSet) { + // Return the OTP version from the status field. + *otpVersion = (rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_MASK) >> SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT; + } else { + return SE_RESPONSE_INVALID_COMMAND; + } + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Check whether the running command has completed. + * + * @details + * This function polls the SE-to-host mailbox interrupt flag. + * + * @return True if a command has completed and the result is available + ******************************************************************************/ +bool SE_isCommandCompleted(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the response is ok + if (!rootIsOutputMailboxValid()) { + return false; + } + + // Check status MB_DONE flag of the mailbox + return ((rootOutMb->status & ROOT_MB_DONE) == ROOT_MB_DONE); +} + +/***************************************************************************//** + * @brief + * Read the previously executed command. + * + * @details + * This function reads the previously executed command. + * + * @return + * One of the SE command words. + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid. + ******************************************************************************/ +uint32_t SE_readExecutedCommand(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + return rootOutMb->command; +} + +/***************************************************************************//** + * @brief + * Read the status of the previously executed command. + * + * @details + * This function reads the status of the previously executed command. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully or a signature + * was successfully verified, + * SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, e.g. + * because of conflicting Secure/Non-Secure memory accesses, + * SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_readCommandResponse(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + return (SE_Response_t)(rootOutMb->status & SE_RESPONSE_MASK); +} + +/***************************************************************************//** + * @brief + * Acknowledge and get status and output data of a completed command. + * + * @details + * This function acknowledges and gets the status and output data of a + * completed mailbox command. + * The mailbox command is acknowledged by inverting all bits in the checksum + * (XOR with 0xFFFFFFFF). + * The output data is copied into the linked list of output buffers pointed + * to in the given command data structure. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * @retval SE_RESPONSE_MAILBOX_INVALID when mailbox command not done or invalid + ******************************************************************************/ +SE_Response_t SE_ackCommand(SE_Command_t *command) +{ + // Setup pointer to the VSE Output Mailbox data structure + // (must be stored in a RAM area which is not used by the VSE) + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + uint32_t *mbData = (uint32_t*) rootOutMb->data; + SE_DataTransfer_t *outDataDesc = command->data_out; + unsigned int outDataLen, outDataCnt, i, outDescLen; + uint32_t *outData; + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Get output data length + outDataLen = rootOutMb->length; + + // Acknowledge the output mailbox response by invalidating checksum + mbData[outDataLen] ^= 0xFFFFFFFFUL; + + // Check command status code + if ((rootOutMb->status & SE_RESPONSE_MASK) != SE_RESPONSE_OK) { + return rootOutMb->status & SE_RESPONSE_MASK; + } + + // Copy data from the Output Mailbox to the linked list of output + // buffers provided by the user + outDataCnt = 0; + while (outDataDesc && (outDataCnt < outDataLen)) { + outData = (uint32_t*) outDataDesc->data; + outDescLen = + (outDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); + for (i = 0; (i < outDescLen) && (outDataCnt < outDataLen); i++) { + outData[i] = mbData[outDataCnt++]; + } + // If we have reached the end of a buffer, go to next buffer descriptor + if (i == outDescLen) { + outDataDesc = (SE_DataTransfer_t*) + ((uint32_t)outDataDesc->next & ~SE_DATATRANSFER_STOP); + } + } + + // Check if the output data list is too small to copy all output data in + // mailbox. + if ((outDataDesc == 0) && (outDataCnt < outDataLen)) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + return SE_RESPONSE_OK; +} + +#endif // #if defined(CRYPTOACC_PRESENT) + +/******************************************************************************* + ***************************** DEPRECATED ********************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup se_deprecated + * + * @{ + ******************************************************************************/ + +/******************************************************************************* +* The following functions have been deprecated and will be removed in a future +* version of emlib. All high-level functionality have been moved to the SE +* manager. +*******************************************************************************/ + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Init pubkey or pubkey signature. + * + * @details + * Initialize public key stored in the SE, or its corresponding signature. The + * command can be used to write: + * * SE_KEY_TYPE_BOOT -- public key used to perform secure boot + * * SE_KEY_TYPE_AUTH -- public key used to perform secure debug + * + * @note + * These keys can not be overwritten, so this command can only be issued once + * per key per part. + * + * @param[in] key_type + * ID of key type to initialize. + * + * @param[in] pubkey + * Pointer to a buffer that contains the public key or signature. + * Must be word aligned and have a length of 64 bytes. + * + * @param[in] numBytes + * Length of pubkey buffer (64 bytes). + * + * @param[in] signature + * If true, initialize signature for the specified key type instead of the + * public key itself. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed + ******************************************************************************/ +SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) +{ + uint32_t commandWord = SE_COMMAND_INIT_PUBKEY; + SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; + + EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) + || (key_type == SE_KEY_TYPE_AUTH)); + + EFM_ASSERT(numBytes == 64); + EFM_ASSERT(!((size_t)pubkey & 3U)); + + // Find parity word + volatile uint32_t parity = 0; + for (size_t i = 0; i < numBytes / 4; i++) { + parity = parity ^ ((uint32_t *)pubkey)[i]; + } + + // SE command structures +#if defined(SEMAILBOX_PRESENT) + commandWord = + (signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY; +#elif defined(CRYPTOACC_PRESENT) + (void)signature; +#endif + SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); + + SE_DataTransfer_t parityData = SE_DATATRANSFER_DEFAULT(&parity, 4); + SE_addDataInput(&command, &parityData); + + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); + SE_addDataInput(&command, &pubkeyData); + + SE_executeCommand(&command); +#if defined(SEMAILBOX_PRESENT) + res = SE_readCommandResponse(); +#endif + return res; +} + +/***************************************************************************//** + * @brief + * + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Initialize SE one-time-programmable (OTP) configuration. + * + * @details + * Configuration is performed by setting the desired options in the + * @ref SE_OTPInit_t structure. + * + * This function can be used to enable secure boot, to configure flash page + * locking, and to enable anti-rollback protection when using the SE to + * perform an application upgrade, typically a Gecko bootloader upgrade. + * + * Before secure boot can be enabled, the public key used for secure boot + * verification must be uploaded using @ref SE_initPubkey(). + * + * @warning + * This command can only be executed once per device! When the configuration + * has been programmed it is not possible to update any of the fields. + * + * @param[in] otp_init + * @ref SE_OTPInit_t structure containing the SE configuration. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + ******************************************************************************/ +SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) +{ + uint32_t mcuSettingsFlags = 0; + + SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; + + if (otp_init->enableSecureBoot) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; + +#if defined(SEMAILBOX_PRESENT) + uint8_t pubkey[64]; + { + EFM_ASSERT(!((size_t)pubkey & 3U)); + // SE command structures + SE_Command_t commandPubkeyRead = SE_COMMAND_DEFAULT(SE_COMMAND_READ_PUBKEY | SE_KEY_TYPE_BOOT); + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, sizeof(pubkey)); + SE_addDataOutput(&commandPubkeyRead, &pubkeyData); + SE_executeCommand(&commandPubkeyRead); + res = SE_readCommandResponse(); + if (res != SE_RESPONSE_OK) { + return SE_RESPONSE_ABORT; + } + res = SE_RESPONSE_INVALID_COMMAND; + } +#endif + } + if (otp_init->verifySecureBootCertificate) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; + } + if (otp_init->enableAntiRollback) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; + } + + if (otp_init->secureBootPageLockNarrow && otp_init->secureBootPageLockFull) { + return SE_RESPONSE_ABORT; + } + if (otp_init->secureBootPageLockNarrow) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; + } + if (otp_init->secureBootPageLockFull) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; + } + + // Find parity word + volatile uint32_t parity = 0; + parity = parity ^ mcuSettingsFlags; + + volatile uint32_t parameters[2] = { + parity, + sizeof(mcuSettingsFlags) + }; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_INIT_OTP); + +#if defined(SEMAILBOX_PRESENT) + static struct ReservedSettings { + uint8_t reserved1[16]; + uint8_t reserved2[2]; + uint8_t reserved3[2]; + } reservedSettings = { + { 0x00 }, + { 0xFF }, + { 0x00 } + }; + + for (size_t i = 0; i < 5; i++) { + parity = parity ^ ((uint32_t*)(&reservedSettings))[i]; + } + parameters[0] = parity; + parameters[1] = parameters[1] + sizeof(reservedSettings); + + SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(&command, ¶metersData); + + SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); + SE_addDataInput(&command, &mcuSettingsFlagsData); + + SE_DataTransfer_t reservedSettingsData = SE_DATATRANSFER_DEFAULT((volatile void *)&reservedSettings, sizeof(reservedSettings)); + SE_addDataInput(&command, &reservedSettingsData); + + SE_executeCommand(&command); + + res = SE_readCommandResponse(); +#elif defined(CRYPTOACC_PRESENT) + SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(&command, ¶metersData); + + SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); + SE_addDataInput(&command, &mcuSettingsFlagsData); + + SE_executeCommand(&command); +#else + (void)command; + (void)parameters; +#endif + + return res; +} + +#if defined(SEMAILBOX_PRESENT) + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Writes data to User Data section in MTP. Write data must be aligned to + * word size and contain a number of bytes that is divisable by four. + * + * @note + * It is recommended to erase the flash page before performing a write. + * + * @param[in] offset + * Offset to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +SE_Response_t SE_writeUserData(uint32_t offset, + void *data, + uint32_t numBytes) +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_WRITE_USER_DATA); + SE_DataTransfer_t userData = SE_DATATRANSFER_DEFAULT(data, numBytes); + + SE_addDataInput(&command, &userData); + + SE_addParameter(&command, offset); + SE_addParameter(&command, numBytes); + + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Erases User Data section in MTP. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +SE_Response_t SE_eraseUserData() +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_ERASE_USER_DATA); + + SE_addParameter(&command, SE_COMMAND_OPTION_ERASE_UD); + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Returns the current boot status, versions and system configuration. + * + * @param[out] status + * @ref SE_Status_t containing current SE status. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK upon command completion. Errors are encoded in the + * different parts of the returned status object. + ******************************************************************************/ +SE_Response_t SE_getStatus(SE_Status_t *status) +{ + volatile uint32_t output[9] = { 0 }; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_GET_STATUS); + SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT((void*)output, 4 * 9); + + SE_addDataOutput(&command, &outData); + + // Execute command and return response + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + + // Update status object + status->bootStatus = output[4]; + status->seFwVersion = output[5]; + status->hostFwVersion = output[6]; + + SE_DebugStatus_t debugStatus; + debugStatus.debugLockEnabled = (output[7] & (1 << 0)); + debugStatus.deviceEraseEnabled = (output[7] & (1 << 1)); + debugStatus.secureDebugEnabled = (output[7] & (1 << 2)); + status->debugStatus = debugStatus; + + status->secureBootEnabled = ((output[8] & 0x1) && ((output[8] & ~0x1) == 0)); + + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Read the serial number of the SE module. + * + * @param[out] serial + * Pointer to array of size 16 bytes. + * + * @return + * One of the @ref SE_Response_t return codes. + * @retval SE_RESPONSE_OK when serial number is returned successfully, + * @retval SE_RESPONSE_INTERNAL_ERROR if not. + ******************************************************************************/ +SE_Response_t SE_serialNumber(void *serial) +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_READ_SERIAL); + SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT(serial, 16); + + SE_addDataOutput(&command, &outData); + + // Execute command and return response + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Read pubkey or pubkey signature. + * + * @details + * Read out a public key stored in the SE, or its signature. The command can + * be used to read: + * * SE_KEY_TYPE_BOOT + * * SE_KEY_TYPE_AUTH + * + * @param[in] key_type + * ID of key type to read. + * + * @param[out] pubkey + * Pointer to a buffer to contain the returned public key. + * Must be word aligned and have a length of 64 bytes. + * + * @param[in] numBytes + * Length of pubkey buffer (64 bytes). + * + * @param[in] signature + * If true, the function will return the signature programmed for the + * specified public key instead of the public key itself. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed + ******************************************************************************/ +SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) +{ + EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) + || (key_type == SE_KEY_TYPE_AUTH)); + + EFM_ASSERT(numBytes == 64); + EFM_ASSERT(!((size_t)pubkey & 3U)); + + // SE command structures + uint32_t commandWord = + (signature) ? SE_COMMAND_READ_PUBKEY_SIGNATURE : SE_COMMAND_READ_PUBKEY; + SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); + + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); + SE_addDataOutput(&command, &pubkeyData); + + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Returns the current debug lock configuration. + * @param[out] status + * The command returns a @ref SE_DebugStatus_t with the current status of the + * debug configuration. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there are configuration errors. + ******************************************************************************/ +SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) +{ + SE_Response_t res; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_STATUS); + + volatile uint32_t status_word = 0; + SE_DataTransfer_t statusData = SE_DATATRANSFER_DEFAULT((void*)&status_word, 4); + SE_addDataOutput(&command, &statusData); + + SE_executeCommand(&command); + res = SE_readCommandResponse(); + + status->debugLockEnabled = (status_word & (1 << 0)); + status->deviceEraseEnabled = (status_word & (1 << 1)); + status->secureDebugEnabled = (status_word & (1 << 2)); + + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Enables the debug lock for the part. + * @details + * The debug port will be closed and the only way to open it is through + * device erase (if enabled) or temporarily through secure debug unlock (if + * enabled). + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR there was a problem locking the debug port. + ******************************************************************************/ +SE_Response_t SE_debugLockApply(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_APPLY); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Enables the secure debug functionality. + * @details + * Enables the secure debug functionality. This functionality makes it + * possible to open a locked debug port by signing a cryptographic challenge + * and using the debug command interface (DCI). + * + * This command can only be executed before the debug port is locked, and + * after a secure debug public key has been installed in the SE using + * @ref SE_initPubkey() or the corresponding DCI command. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INVALID_COMMAND if debug port is locked. + * @retval SE_RESPONSE_INVALID_PARAMETER if secure debug certificates are + * missing. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_debugSecureEnable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_ENABLE_SECURE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Disables the secure debug functionality. + * @details + * Disables the secure debug functionality that can be used to open a + * locked debug port. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_debugSecureDisable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_DISABLE_SECURE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Performs a device mass erase and debug unlock. + * + * @details + * Performs a device mass erase and resets the debug configuration to its + * initial unlocked state. Only available before @ref SE_deviceEraseDisable or + * the corresponding DCI command has been executed. + * + * @note + * This command clears and verifies the complete flash and ram of the + * system, excluding the user data pages and one-time programmable + * commissioning information in the secure element. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INVALID_COMMAND if device erase is disabled. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_deviceErase(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Disabled device erase functionality. + * + * @details + * This command disables the device erase command. It does not lock the + * debug interface to the part, but it is a permanent action for the part. + * If device erase is disabled and the device is debug locked, there is no + * way to permanently unlock the part. If secure debug unlock is enabled, + * secure debug unlock can still be used to temporarily open the debug port. + * + * @warning + * This command permanently disables the device erase functionality! + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_deviceEraseDisable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE_DISABLE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +#endif // #if defined(SEMAILBOX_PRESENT) +#endif // #if !defined(SLI_EM_SE_HOST) + +/** @} (end addtogroup deprecated_se) */ +/** @} (end addtogroup se) */ + +#endif /* defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_system.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_system.c index 9af59cf..1e3b64f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_system.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_system.c @@ -1,436 +1,436 @@ -/***************************************************************************//** - * @file - * @brief System Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_system.h" -#include "sl_assert.h" -#include -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/* Bit mask used to extract the part number value without the new naming - * bitfield. */ -#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 -#define SYSCFG_CHIPREV_PARTNUMBER0 0xF - -/* Bit mask to convert NON-SECURE to SECURE */ -#define CONVERT_NS_TO_S (~(1 << 28U)) - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get a chip major/minor revision. - * - * @param[out] rev - * A location to place the chip revision information. - ******************************************************************************/ -void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) -{ -#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - uint32_t chiprev = SYSCFG_readChipRev(); -#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - rev->partNumber = ((chiprev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chiprev & SYSCFG_CHIPREV_PARTNUMBER0); -#else - rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; -#endif - rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; - rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; -#else - uint8_t tmp; - - EFM_ASSERT(rev); - - /* CHIP FAMILY bit [5:2] */ - tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) - >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); - /* CHIP FAMILY bit [1:0] */ - tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) - >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); - rev->family = tmp; - - /* CHIP MAJOR bit [3:0] */ - rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT); - - /* CHIP MINOR bit [7:4] */ - tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); - /* CHIP MINOR bit [3:0] */ - tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); - rev->minor = tmp; -#endif -} - -/***************************************************************************//** - * @brief - * Get a factory calibration value for a given peripheral register. - * - * @param[in] regAddress - * The peripheral calibration register address to get a calibration value for. If - * the calibration value is found, this register is updated with the - * calibration value. - * - * @return - * True if a calibration value exists, false otherwise. - ******************************************************************************/ -bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) -{ - SYSTEM_CalAddrVal_TypeDef * p, * end; - - uint32_t s_regAddress = (uint32_t)regAddress; - s_regAddress = s_regAddress & CONVERT_NS_TO_S; - -#if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) - p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; - end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; -#else - p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); - end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; -#endif - - for (; p < end; p++) { - if (p->address == 0) { - /* p->address == 0 marks the end of the table */ - return false; - } - if (p->address == s_regAddress) { - *regAddress = p->calValue; - return true; - } - } - /* Nothing found for regAddress. */ - return false; -} - -/***************************************************************************//** - * @brief - * Get family security capability. - * - * @note - * This function retrieves the family security capability based on the - * device number. The device number is one letter and 3 digits: - * DEVICENUMBER = (alpha-'A')*1000 + numeric. i.e. 0d = "A000"; 1123d = "B123". - * The security capabilities are represented by ::SYSTEM_SecurityCapability_TypeDef. - * - * @return - * Security capability of MCU. - ******************************************************************************/ -SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void) -{ - SYSTEM_SecurityCapability_TypeDef sc; - -#if (_SILICON_LABS_32B_SERIES == 0) - sc = securityCapabilityNA; -#elif (_SILICON_LABS_32B_SERIES == 1) - sc = securityCapabilityBasic; -#else - sc = securityCapabilityUnknown; -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - uint16_t mcuFeatureSetMajor; - uint16_t deviceNumber; - deviceNumber = SYSTEM_GetPartNumber(); - mcuFeatureSetMajor = 'A' + (deviceNumber / 1000); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" - mcuFeatureSetMajor = 'C'; -#endif - - switch (mcuFeatureSetMajor) { - case 'A': - sc = securityCapabilitySE; - break; - - case 'B': - sc = securityCapabilityVault; - break; - - case 'C': - sc = securityCapabilityRoT; - break; - - default: - sc = securityCapabilityUnknown; - break; - } -#endif - - return sc; -} - -/***************************************************************************//** - * @brief - * Get the unique number for this device. - * - * @return - * Unique number for this device. - ******************************************************************************/ -uint64_t SYSTEM_GetUnique(void) -{ -#if defined (_DEVINFO_EUI64H_MASK) - uint32_t tmp = DEVINFO->EUI64L; - return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; -#elif defined(_DEVINFO_UNIQUEH_MASK) - uint32_t tmp = DEVINFO->UNIQUEL; - return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; -#else -#error (em_system.c): Location of device unique number is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the production revision for this part. - * - * @return - * Production revision for this part. - ******************************************************************************/ -uint8_t SYSTEM_GetProdRev(void) -{ -#if defined (_DEVINFO_PART_PROD_REV_MASK) - return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) - >> _DEVINFO_PART_PROD_REV_SHIFT); -#elif defined (_DEVINFO_INFO_PRODREV_MASK) - return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) - >> _DEVINFO_INFO_PRODREV_SHIFT); -#else -#error (em_system.c): Location of production revision is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the SRAM Base Address. - * - * @note - * This function is used to retrieve the base address of the SRAM. - * - * @return - * Base address SRAM (32-bit unsigned integer). - ******************************************************************************/ -uint32_t SYSTEM_GetSRAMBaseAddress(void) -{ - return (uint32_t)SRAM_BASE; -} - -/***************************************************************************//** - * @brief - * Get the SRAM size (in KB). - * - * @note - * This function retrieves SRAM size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use SRAM_SIZE instead. - * - * @return - * Size of internal SRAM (in KB). - ******************************************************************************/ -uint16_t SYSTEM_GetSRAMSize(void) -{ - uint16_t sizekb; - -#if defined(_EFM32_GECKO_FAMILY) - /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ - if (SYSTEM_GetProdRev() < 5) { - sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT; - } -#endif - sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT); - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) - /* Do not include EFR32xG1 RAMH. */ - sizekb--; -#endif - - return sizekb; -} - -/***************************************************************************//** - * @brief - * Get the flash size (in KB). - * - * @note - * This function retrieves flash size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use FLASH_SIZE instead. - * - * @return - * Size of internal flash (in KB). - ******************************************************************************/ -uint16_t SYSTEM_GetFlashSize(void) -{ -#if defined(_EFM32_GECKO_FAMILY) - /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ - if (SYSTEM_GetProdRev() < 5) { - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT; - } -#endif - return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get the flash page size in bytes. - * - * @note - * This function retrieves flash page size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use FLASH_PAGE_SIZE instead. - * - * @return - * Page size of internal flash in bytes. - ******************************************************************************/ -uint32_t SYSTEM_GetFlashPageSize(void) -{ - uint32_t tmp; - -#if defined(_SILICON_LABS_32B_SERIES_0) - -#if defined(_EFM32_GIANT_FAMILY) - if (SYSTEM_GetProdRev() < 18) { - /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ - return FLASH_PAGE_SIZE; - } -#elif defined(_EFM32_ZERO_FAMILY) - if (SYSTEM_GetProdRev() < 24) { - /* Early Zero devices have an incorrect DEVINFO flash page size */ - return FLASH_PAGE_SIZE; - } -#endif -#endif - -#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) - tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) - >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; -#elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) - tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) - >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; -#else -#error (em_system.c): Location of flash page size is not defined. -#endif - - return 1UL << ((tmp + 10UL) & 0x1FUL); -} - -/***************************************************************************//** - * @brief - * Get the MCU part number. - * - * @return - * The part number of MCU. - ******************************************************************************/ -uint16_t SYSTEM_GetPartNumber(void) -{ -#if defined(_DEVINFO_PART_DEVICENUM_MASK) - return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) - >> _DEVINFO_PART_DEVICENUM_SHIFT); -#elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) - return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) - >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); -#else -#error (em_system.c): Location of device part number is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the calibration temperature (in degrees Celsius). - * - * @return - * Calibration temperature in Celsius. - ******************************************************************************/ -uint8_t SYSTEM_GetCalibrationTemperature(void) -{ -#if defined(_DEVINFO_CAL_TEMP_MASK) - return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) - >> _DEVINFO_CAL_TEMP_SHIFT); -#elif defined(_DEVINFO_CALTEMP_TEMP_MASK) - return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) - >> _DEVINFO_CALTEMP_TEMP_SHIFT); -#else -#error (em_system.c): Location of calibration temperature is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the MCU family identifier. - * - * @note - * This function retrieves family ID by reading the chip's device info - * structure in flash memory. Users can retrieve family ID directly - * by reading DEVINFO->PART item and decode with mask and shift - * \#defines defined in \_devinfo.h (refer to code - * below for details). - * - * @return - * Family identifier of MCU. - ******************************************************************************/ -SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) -{ -#if defined(_DEVINFO_PART_FAMILY_MASK) - return (SYSTEM_PartFamily_TypeDef) - ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK - | _DEVINFO_PART_FAMILYNUM_MASK)))); -#elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) - return (SYSTEM_PartFamily_TypeDef) - ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) - >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); -#else - #error (em_system.h): Location of device family name is not defined. -#endif -} - -/** @} (end addtogroup system) */ +/***************************************************************************//** + * @file + * @brief System Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_system.h" +#include "sl_assert.h" +#include +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Bit mask used to extract the part number value without the new naming + * bitfield. */ +#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 +#define SYSCFG_CHIPREV_PARTNUMBER0 0xF + +/* Bit mask to convert NON-SECURE to SECURE */ +#define CONVERT_NS_TO_S (~(1 << 28U)) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get a chip major/minor revision. + * + * @param[out] rev + * A location to place the chip revision information. + ******************************************************************************/ +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) +{ +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + uint32_t chiprev = SYSCFG_readChipRev(); +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + rev->partNumber = ((chiprev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chiprev & SYSCFG_CHIPREV_PARTNUMBER0); +#else + rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; +#endif + rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; + rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; +#else + uint8_t tmp; + + EFM_ASSERT(rev); + + /* CHIP FAMILY bit [5:2] */ + tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) + >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + /* CHIP FAMILY bit [1:0] */ + tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) + >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + rev->family = tmp; + + /* CHIP MAJOR bit [3:0] */ + rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT); + + /* CHIP MINOR bit [7:4] */ + tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + rev->minor = tmp; +#endif +} + +/***************************************************************************//** + * @brief + * Get a factory calibration value for a given peripheral register. + * + * @param[in] regAddress + * The peripheral calibration register address to get a calibration value for. If + * the calibration value is found, this register is updated with the + * calibration value. + * + * @return + * True if a calibration value exists, false otherwise. + ******************************************************************************/ +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) +{ + SYSTEM_CalAddrVal_TypeDef * p, * end; + + uint32_t s_regAddress = (uint32_t)regAddress; + s_regAddress = s_regAddress & CONVERT_NS_TO_S; + +#if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) + p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; + end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; +#else + p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); + end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; +#endif + + for (; p < end; p++) { + if (p->address == 0) { + /* p->address == 0 marks the end of the table */ + return false; + } + if (p->address == s_regAddress) { + *regAddress = p->calValue; + return true; + } + } + /* Nothing found for regAddress. */ + return false; +} + +/***************************************************************************//** + * @brief + * Get family security capability. + * + * @note + * This function retrieves the family security capability based on the + * device number. The device number is one letter and 3 digits: + * DEVICENUMBER = (alpha-'A')*1000 + numeric. i.e. 0d = "A000"; 1123d = "B123". + * The security capabilities are represented by ::SYSTEM_SecurityCapability_TypeDef. + * + * @return + * Security capability of MCU. + ******************************************************************************/ +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void) +{ + SYSTEM_SecurityCapability_TypeDef sc; + +#if (_SILICON_LABS_32B_SERIES == 0) + sc = securityCapabilityNA; +#elif (_SILICON_LABS_32B_SERIES == 1) + sc = securityCapabilityBasic; +#else + sc = securityCapabilityUnknown; +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + uint16_t mcuFeatureSetMajor; + uint16_t deviceNumber; + deviceNumber = SYSTEM_GetPartNumber(); + mcuFeatureSetMajor = 'A' + (deviceNumber / 1000); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" + mcuFeatureSetMajor = 'C'; +#endif + + switch (mcuFeatureSetMajor) { + case 'A': + sc = securityCapabilitySE; + break; + + case 'B': + sc = securityCapabilityVault; + break; + + case 'C': + sc = securityCapabilityRoT; + break; + + default: + sc = securityCapabilityUnknown; + break; + } +#endif + + return sc; +} + +/***************************************************************************//** + * @brief + * Get the unique number for this device. + * + * @return + * Unique number for this device. + ******************************************************************************/ +uint64_t SYSTEM_GetUnique(void) +{ +#if defined (_DEVINFO_EUI64H_MASK) + uint32_t tmp = DEVINFO->EUI64L; + return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; +#elif defined(_DEVINFO_UNIQUEH_MASK) + uint32_t tmp = DEVINFO->UNIQUEL; + return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; +#else +#error (em_system.c): Location of device unique number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the production revision for this part. + * + * @return + * Production revision for this part. + ******************************************************************************/ +uint8_t SYSTEM_GetProdRev(void) +{ +#if defined (_DEVINFO_PART_PROD_REV_MASK) + return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) + >> _DEVINFO_PART_PROD_REV_SHIFT); +#elif defined (_DEVINFO_INFO_PRODREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) + >> _DEVINFO_INFO_PRODREV_SHIFT); +#else +#error (em_system.c): Location of production revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the SRAM Base Address. + * + * @note + * This function is used to retrieve the base address of the SRAM. + * + * @return + * Base address SRAM (32-bit unsigned integer). + ******************************************************************************/ +uint32_t SYSTEM_GetSRAMBaseAddress(void) +{ + return (uint32_t)SRAM_BASE; +} + +/***************************************************************************//** + * @brief + * Get the SRAM size (in KB). + * + * @note + * This function retrieves SRAM size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use SRAM_SIZE instead. + * + * @return + * Size of internal SRAM (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetSRAMSize(void) +{ + uint16_t sizekb; + +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; + } +#endif + sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH. */ + sizekb--; +#endif + + return sizekb; +} + +/***************************************************************************//** + * @brief + * Get the flash size (in KB). + * + * @note + * This function retrieves flash size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_SIZE instead. + * + * @return + * Size of internal flash (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetFlashSize(void) +{ +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + } +#endif + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the flash page size in bytes. + * + * @note + * This function retrieves flash page size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_PAGE_SIZE instead. + * + * @return + * Page size of internal flash in bytes. + ******************************************************************************/ +uint32_t SYSTEM_GetFlashPageSize(void) +{ + uint32_t tmp; + +#if defined(_SILICON_LABS_32B_SERIES_0) + +#if defined(_EFM32_GIANT_FAMILY) + if (SYSTEM_GetProdRev() < 18) { + /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ + return FLASH_PAGE_SIZE; + } +#elif defined(_EFM32_ZERO_FAMILY) + if (SYSTEM_GetProdRev() < 24) { + /* Early Zero devices have an incorrect DEVINFO flash page size */ + return FLASH_PAGE_SIZE; + } +#endif +#endif + +#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; +#elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; +#else +#error (em_system.c): Location of flash page size is not defined. +#endif + + return 1UL << ((tmp + 10UL) & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Get the MCU part number. + * + * @return + * The part number of MCU. + ******************************************************************************/ +uint16_t SYSTEM_GetPartNumber(void) +{ +#if defined(_DEVINFO_PART_DEVICENUM_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) + >> _DEVINFO_PART_DEVICENUM_SHIFT); +#elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) + >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); +#else +#error (em_system.c): Location of device part number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the calibration temperature (in degrees Celsius). + * + * @return + * Calibration temperature in Celsius. + ******************************************************************************/ +uint8_t SYSTEM_GetCalibrationTemperature(void) +{ +#if defined(_DEVINFO_CAL_TEMP_MASK) + return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) + >> _DEVINFO_CAL_TEMP_SHIFT); +#elif defined(_DEVINFO_CALTEMP_TEMP_MASK) + return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) + >> _DEVINFO_CALTEMP_TEMP_SHIFT); +#else +#error (em_system.c): Location of calibration temperature is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the MCU family identifier. + * + * @note + * This function retrieves family ID by reading the chip's device info + * structure in flash memory. Users can retrieve family ID directly + * by reading DEVINFO->PART item and decode with mask and shift + * \#defines defined in \_devinfo.h (refer to code + * below for details). + * + * @return + * Family identifier of MCU. + ******************************************************************************/ +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) +{ +#if defined(_DEVINFO_PART_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK + | _DEVINFO_PART_FAMILYNUM_MASK)))); +#elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) + >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); +#else + #error (em_system.h): Location of device family name is not defined. +#endif +} + +/** @} (end addtogroup system) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c index c542a8b..033e64a 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c @@ -1,520 +1,520 @@ -/***************************************************************************//** - * @file - * @brief Timer/counter (TIMER) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_timer.h" -#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) - -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup timer TIMER - Timer/Counter - * @brief Timer/Counter (TIMER) Peripheral API - * @details - * The timer module consists of three main parts: - * @li General timer configuration and enable control. - * @li Compare/capture control. - * @li Dead time insertion control (may not be available for all timers). - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) - -/** Map TIMER reference to index of device. */ -#if defined(TIMER9) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : (timer) == TIMER5 ? 5 \ - : (timer) == TIMER6 ? 6 \ - : (timer) == TIMER7 ? 7 \ - : (timer) == TIMER8 ? 8 \ - : (timer) == TIMER9 ? 9 \ - : -1) -#elif defined(TIMER7) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : (timer) == TIMER5 ? 5 \ - : (timer) == TIMER6 ? 6 \ - : (timer) == TIMER7 ? 7 \ - : -1) -#elif defined(TIMER4) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : -1) -#else -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : -1) -#endif - -#define TIMER_INPUT_CHANNEL_DTI 3UL -#define TIMER_INPUT_CHANNEL_DTIFS1 4UL -#define TIMER_INPUT_CHANNEL_DTIFS2 5UL - -/** - * TIMER PRS registers are moved into the PRS register space on series 2 devices. - * The PRS Consumer registers for a timer consist of 6 registers. - * - * [0] - CC0 PRS Consumer - * [1] - CC1 PRS Consumer - * [2] - CC2 PRS Consumer - * [3] - DTI PRS Consumer - * [4] - DTIFS1 PRS Consumer - * [5] - DTIFS2 PRS Consumer - */ -typedef struct { - __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ -} PRS_TIMERn_Consumer_TypeDef; - -typedef struct { - PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; -} PRS_TIMERn_TypeDef; - -/** - * @brief Configure a timer capture/compare channel to use a PRS channel as input. - * - * @param[in] timer - * - * @param[in] cc - * Timer input channel. Valid input is 0-5. - * 0 - CC0 - * 1 - CC1 - * 2 - CC2 - * 3 - DTI - * 4 - DTIFS1 - * 5 - DTIFS2 - * - * @param[in] prsCh - * PRS channel number. - * - * @param[in] async - * true for asynchronous PRS channel, false for synchronous PRS channel. - */ -static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) -{ - int i = TIMER_DEVICE_ID(timer); - volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; - EFM_ASSERT(i >= 0); - - if (i >= 0) { - if (async) { - base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; - } else { - base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; - } - } -} -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize TIMER. - * - * @details - * Notice that the counter top must be configured separately with, for instance - * TIMER_TopSet(). In addition, compare/capture and dead-time insertion - * initialization must be initialized separately if used, which should probably - * be done prior to using this function if configuring the TIMER to - * start when initialization is completed. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] init - * A pointer to the TIMER initialization structure. - ******************************************************************************/ -void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - uint32_t ctrlRegVal = 0; - -#if defined (_TIMER_CFG_PRESC_SHIFT) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) - | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) - | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) - | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) - | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) - | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) - | (init->oneShot ? TIMER_CFG_OSMEN : 0) - | (init->sync ? TIMER_CFG_SYNC : 0) - | (init->disSyncOut ? TIMER_CFG_DISSYNCOUT : 0) - | (init->ati ? TIMER_CFG_ATI : 0) - | (init->rssCoist ? TIMER_CFG_RSSCOIST : 0); - timer->EN_SET = TIMER_EN_EN; -#endif - - /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ - if (!(init->enable)) { - timer->CMD = TIMER_CMD_STOP; - } - - /* Reset the counter. */ - timer->CNT = _TIMER_CNT_RESETVALUE; - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) - | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) - | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) - | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) - | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) - | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) - | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) - | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) - | (init->oneShot ? TIMER_CTRL_OSMEN : 0) -#if defined(TIMER_CTRL_DISSYNCOUT) - | (init->disSyncOut ? TIMER_CTRL_DISSYNCOUT : 0) -#endif - | (init->sync ? TIMER_CTRL_SYNC : 0); - -#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) && defined(TIMER_CTRL_RSSCOIST) - ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) - | (init->ati ? TIMER_CTRL_ATI : 0) - | (init->rssCoist ? TIMER_CTRL_RSSCOIST : 0); -#endif - -#else - ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) - | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) - | (init->count2x ? TIMER_CTRL_X2CNT : 0); -#endif - - timer->CTRL = ctrlRegVal; - - /* Start the timer if specified to be enabled (doesn't hurt if already started). */ - if (init->enable) { - timer->CMD = TIMER_CMD_START; - } -} - -/***************************************************************************//** - * @brief - * Initialize the TIMER compare/capture channel. - * - * @details - * Notice that if operating the channel in compare mode, the CCV and CCVB register - * must be set separately, as required. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] ch - * A compare/capture channel to initialize for. - * - * @param[in] init - * A pointer to the TIMER initialization structure. - ******************************************************************************/ -void TIMER_InitCC(TIMER_TypeDef *timer, - unsigned int ch, - const TIMER_InitCC_TypeDef *init) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - EFM_ASSERT(TIMER_REF_CH_VALIDATE(timer, ch)); - -#if defined (_TIMER_CC_CFG_MASK) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CC[ch].CFG = - ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) - | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) - | (init->coist ? TIMER_CC_CFG_COIST : 0) - | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); - - if (init->prsInput) { - timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; - bool async = (init->prsInputType != timerPrsInputSync); - timerPrsConfig(timer, ch, init->prsSel, async); - } else { - timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; - } - timer->EN_SET = TIMER_EN_EN; - - timer->CC[ch].CTRL = - ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) - | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) - | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) - | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) - | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) - | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); -#else - timer->CC[ch].CTRL = - ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) - | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) - | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) - | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) - | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) - | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) - | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) - | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) - | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) - | (init->coist ? TIMER_CC_CTRL_COIST : 0) - | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) -#if defined(_TIMER_CC_CTRL_PRSCONF_MASK) - | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) -#endif - ; -#endif -} - -#if defined(_TIMER_DTCTRL_MASK) -/***************************************************************************//** - * @brief - * Initialize the TIMER DTI unit. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] init - * A pointer to the TIMER DTI initialization structure. - ******************************************************************************/ -void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); - - /* Make sure the DTI unit is disabled while initializing. */ - TIMER_EnableDTI(timer, false); - -#if defined (_TIMER_DTCFG_MASK) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) - | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); - if (init->enablePrsSource) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); - } - - timer->DTTIMECFG = - ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) - | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) - | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); - - timer->DTFCFG = - (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) - | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) - | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) - | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) - | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); - - if (init->enableFaultSourcePrsSel0) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); - } - if (init->enableFaultSourcePrsSel1) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); - } - - timer->EN_SET = TIMER_EN_EN; -#endif - -#if defined(TIMER_DTCTRL_DTDAS) - /* Set up the DTCTRL register. - The enable bit will be set at the end of the function if specified. */ - timer->DTCTRL = - (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) - | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) - | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) - | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) - | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); -#endif - -#if defined (TIMER_DTCFG_DTDAS) - timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) - | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); -#endif - -#if defined (_TIMER_DTTIME_DTPRESC_SHIFT) - /* Set up the DTTIME register. */ - timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) - | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) - | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); -#endif - -#if defined (TIMER_DTFC_DTLOCKUPFEN) - /* Set up the DTFC register. */ - timer->DTFC = - (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) - | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) - | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) - | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) - | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) - | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) - | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); -#endif - - /* Set up the DTOGEN register. */ - timer->DTOGEN = init->outputsEnableMask; - - /* Clear any previous DTI faults. */ - TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); - - /* Enable/disable before returning. */ - TIMER_EnableDTI(timer, init->enable); -} -#endif - -/***************************************************************************//** - * @brief - * Reset the TIMER to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * a centralized setup of this feature. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - ******************************************************************************/ -void TIMER_Reset(TIMER_TypeDef *timer) -{ - int i; - - EFM_ASSERT(TIMER_REF_VALID(timer)); - -#if defined(TIMER_EN_EN) - timer->EN_SET = TIMER_EN_EN; -#endif - - /* Make sure disabled first, before resetting other registers. */ - timer->CMD = TIMER_CMD_STOP; - - timer->CTRL = _TIMER_CTRL_RESETVALUE; - timer->IEN = _TIMER_IEN_RESETVALUE; -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_CLR = _TIMER_IF_MASK; -#else - timer->IFC = _TIMER_IFC_MASK; -#endif - timer->TOPB = _TIMER_TOPB_RESETVALUE; - /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ - timer->TOP = _TIMER_TOP_RESETVALUE; - timer->CNT = _TIMER_CNT_RESETVALUE; - /* Do not reset the route register, setting should be done independently. */ - /* Note: The ROUTE register may be locked by the DTLOCK register. */ - - for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { - timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; -#if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) - timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; - timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; -#endif -#if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ - && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) - timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; - timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; -#endif - } - - /* Reset dead time insertion module, which has no effect on timers without DTI. */ -#if defined(_TIMER_DTCFG_MASK) - timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; - timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; - timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; - timer->DTFAULTC = _TIMER_DTFAULTC_MASK; -#elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) - /* Unlock DTI registers first if locked. */ - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; - timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; - timer->DTTIME = _TIMER_DTTIME_RESETVALUE; - timer->DTFC = _TIMER_DTFC_RESETVALUE; - timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; - timer->DTFAULTC = _TIMER_DTFAULTC_MASK; -#endif - -#if defined(_TIMER_CFG_MASK) - TIMER_SyncWait(timer); - /* CFG registers must be reset after the timer is disabled */ - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CFG = _TIMER_CFG_RESETVALUE; - for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { - timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; - } - timer->DTCFG = _TIMER_DTCFG_RESETVALUE; - timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; - timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; -#endif -} - -#if defined(TIMER_STATUS_SYNCBUSY) -/** - * @brief Wait for pending synchronization to finish - * - * @param[in] timer - */ -void TIMER_SyncWait(TIMER_TypeDef * timer) -{ - while (((timer->EN & TIMER_EN_EN) != 0U) - && ((timer->STATUS & TIMER_STATUS_SYNCBUSY) != 0U)) { - /* Wait for synchronization to complete */ - } -} -#endif - -/** @} (end addtogroup timer) */ -#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_timer.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup timer TIMER - Timer/Counter + * @brief Timer/Counter (TIMER) Peripheral API + * @details + * The timer module consists of three main parts: + * @li General timer configuration and enable control. + * @li Compare/capture control. + * @li Dead time insertion control (may not be available for all timers). + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) + +/** Map TIMER reference to index of device. */ +#if defined(TIMER9) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : (timer) == TIMER8 ? 8 \ + : (timer) == TIMER9 ? 9 \ + : -1) +#elif defined(TIMER7) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : -1) +#elif defined(TIMER4) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : -1) +#else +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : -1) +#endif + +#define TIMER_INPUT_CHANNEL_DTI 3UL +#define TIMER_INPUT_CHANNEL_DTIFS1 4UL +#define TIMER_INPUT_CHANNEL_DTIFS2 5UL + +/** + * TIMER PRS registers are moved into the PRS register space on series 2 devices. + * The PRS Consumer registers for a timer consist of 6 registers. + * + * [0] - CC0 PRS Consumer + * [1] - CC1 PRS Consumer + * [2] - CC2 PRS Consumer + * [3] - DTI PRS Consumer + * [4] - DTIFS1 PRS Consumer + * [5] - DTIFS2 PRS Consumer + */ +typedef struct { + __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ +} PRS_TIMERn_Consumer_TypeDef; + +typedef struct { + PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; +} PRS_TIMERn_TypeDef; + +/** + * @brief Configure a timer capture/compare channel to use a PRS channel as input. + * + * @param[in] timer + * + * @param[in] cc + * Timer input channel. Valid input is 0-5. + * 0 - CC0 + * 1 - CC1 + * 2 - CC2 + * 3 - DTI + * 4 - DTIFS1 + * 5 - DTIFS2 + * + * @param[in] prsCh + * PRS channel number. + * + * @param[in] async + * true for asynchronous PRS channel, false for synchronous PRS channel. + */ +static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) +{ + int i = TIMER_DEVICE_ID(timer); + volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; + EFM_ASSERT(i >= 0); + + if (i >= 0) { + if (async) { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize TIMER. + * + * @details + * Notice that the counter top must be configured separately with, for instance + * TIMER_TopSet(). In addition, compare/capture and dead-time insertion + * initialization must be initialized separately if used, which should probably + * be done prior to using this function if configuring the TIMER to + * start when initialization is completed. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + uint32_t ctrlRegVal = 0; + +#if defined (_TIMER_CFG_PRESC_SHIFT) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) + | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) + | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) + | (init->oneShot ? TIMER_CFG_OSMEN : 0) + | (init->sync ? TIMER_CFG_SYNC : 0) + | (init->disSyncOut ? TIMER_CFG_DISSYNCOUT : 0) + | (init->ati ? TIMER_CFG_ATI : 0) + | (init->rssCoist ? TIMER_CFG_RSSCOIST : 0); + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ + if (!(init->enable)) { + timer->CMD = TIMER_CMD_STOP; + } + + /* Reset the counter. */ + timer->CNT = _TIMER_CNT_RESETVALUE; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) + | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) + | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) + | (init->oneShot ? TIMER_CTRL_OSMEN : 0) +#if defined(TIMER_CTRL_DISSYNCOUT) + | (init->disSyncOut ? TIMER_CTRL_DISSYNCOUT : 0) +#endif + | (init->sync ? TIMER_CTRL_SYNC : 0); + +#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) && defined(TIMER_CTRL_RSSCOIST) + ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) + | (init->ati ? TIMER_CTRL_ATI : 0) + | (init->rssCoist ? TIMER_CTRL_RSSCOIST : 0); +#endif + +#else + ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | (init->count2x ? TIMER_CTRL_X2CNT : 0); +#endif + + timer->CTRL = ctrlRegVal; + + /* Start the timer if specified to be enabled (doesn't hurt if already started). */ + if (init->enable) { + timer->CMD = TIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Initialize the TIMER compare/capture channel. + * + * @details + * Notice that if operating the channel in compare mode, the CCV and CCVB register + * must be set separately, as required. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] ch + * A compare/capture channel to initialize for. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + EFM_ASSERT(TIMER_REF_CH_VALIDATE(timer, ch)); + +#if defined (_TIMER_CC_CFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CC[ch].CFG = + ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) + | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) + | (init->coist ? TIMER_CC_CFG_COIST : 0) + | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); + + if (init->prsInput) { + timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; + bool async = (init->prsInputType != timerPrsInputSync); + timerPrsConfig(timer, ch, init->prsSel, async); + } else { + timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; + } + timer->EN_SET = TIMER_EN_EN; + + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); +#else + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) + | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) + | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) + | (init->coist ? TIMER_CC_CTRL_COIST : 0) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) +#if defined(_TIMER_CC_CTRL_PRSCONF_MASK) + | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) +#endif + ; +#endif +} + +#if defined(_TIMER_DTCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize the TIMER DTI unit. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER DTI initialization structure. + ******************************************************************************/ +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + /* Make sure the DTI unit is disabled while initializing. */ + TIMER_EnableDTI(timer, false); + +#if defined (_TIMER_DTCFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) + | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); + if (init->enablePrsSource) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); + } + + timer->DTTIMECFG = + ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); + + timer->DTFCFG = + (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) + | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); + + if (init->enableFaultSourcePrsSel0) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); + } + if (init->enableFaultSourcePrsSel1) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); + } + + timer->EN_SET = TIMER_EN_EN; +#endif + +#if defined(TIMER_DTCTRL_DTDAS) + /* Set up the DTCTRL register. + The enable bit will be set at the end of the function if specified. */ + timer->DTCTRL = + (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) + | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) + | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) + | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); +#endif + +#if defined (TIMER_DTCFG_DTDAS) + timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); +#endif + +#if defined (_TIMER_DTTIME_DTPRESC_SHIFT) + /* Set up the DTTIME register. */ + timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); +#endif + +#if defined (TIMER_DTFC_DTLOCKUPFEN) + /* Set up the DTFC register. */ + timer->DTFC = + (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) + | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) + | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) + | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); +#endif + + /* Set up the DTOGEN register. */ + timer->DTOGEN = init->outputsEnableMask; + + /* Clear any previous DTI faults. */ + TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); + + /* Enable/disable before returning. */ + TIMER_EnableDTI(timer, init->enable); +} +#endif + +/***************************************************************************//** + * @brief + * Reset the TIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + ******************************************************************************/ +void TIMER_Reset(TIMER_TypeDef *timer) +{ + int i; + + EFM_ASSERT(TIMER_REF_VALID(timer)); + +#if defined(TIMER_EN_EN) + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Make sure disabled first, before resetting other registers. */ + timer->CMD = TIMER_CMD_STOP; + + timer->CTRL = _TIMER_CTRL_RESETVALUE; + timer->IEN = _TIMER_IEN_RESETVALUE; +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = _TIMER_IF_MASK; +#else + timer->IFC = _TIMER_IFC_MASK; +#endif + timer->TOPB = _TIMER_TOPB_RESETVALUE; + /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ + timer->TOP = _TIMER_TOP_RESETVALUE; + timer->CNT = _TIMER_CNT_RESETVALUE; + /* Do not reset the route register, setting should be done independently. */ + /* Note: The ROUTE register may be locked by the DTLOCK register. */ + + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; +#if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) + timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; + timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; +#endif +#if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ + && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) + timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; + timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; +#endif + } + + /* Reset dead time insertion module, which has no effect on timers without DTI. */ +#if defined(_TIMER_DTCFG_MASK) + timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) + /* Unlock DTI registers first if locked. */ + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTTIME = _TIMER_DTTIME_RESETVALUE; + timer->DTFC = _TIMER_DTFC_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#endif + +#if defined(_TIMER_CFG_MASK) + TIMER_SyncWait(timer); + /* CFG registers must be reset after the timer is disabled */ + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = _TIMER_CFG_RESETVALUE; + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; + } + timer->DTCFG = _TIMER_DTCFG_RESETVALUE; + timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; + timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; +#endif +} + +#if defined(TIMER_STATUS_SYNCBUSY) +/** + * @brief Wait for pending synchronization to finish + * + * @param[in] timer + */ +void TIMER_SyncWait(TIMER_TypeDef * timer) +{ + while (((timer->EN & TIMER_EN_EN) != 0U) + && ((timer->STATUS & TIMER_STATUS_SYNCBUSY) != 0U)) { + /* Wait for synchronization to complete */ + } +} +#endif + +/** @} (end addtogroup timer) */ +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c index 0b8cef0..a76baad 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c @@ -1,1444 +1,1444 @@ -/***************************************************************************//** - * @file - * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) - * Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_usart.h" -#if defined(USART_COUNT) && (USART_COUNT > 0) - -#include "em_cmu.h" -#include "em_bus.h" -#include "sl_assert.h" -#if defined(USART_CTRLX_CTSEN) -#include "em_gpio.h" -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of USART register block pointer reference for assert statements. */ -#if (USART_COUNT == 1) && defined(USART0) -#define USART_REF_VALID(ref) ((ref) == USART0) - -#elif (USART_COUNT == 1) && defined(USART1) -#define USART_REF_VALID(ref) ((ref) == USART1) - -#elif (USART_COUNT == 2) && defined(USART2) -#define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) - -#elif (USART_COUNT == 2) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - -#elif (USART_COUNT == 3) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2)) -#elif (USART_COUNT == 4) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3)) -#elif (USART_COUNT == 5) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3) \ - || ((ref) == USART4)) -#elif (USART_COUNT == 6) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3) \ - || ((ref) == USART4) || ((ref) == USART5)) -#else -#error "Undefined number of USARTs." -#endif - -#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) - #if (USARTRF_COUNT == 1) && defined(USARTRF0) - #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) - #elif (USARTRF_COUNT == 1) && defined(USARTRF1) - #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) - #else - #define USARTRF_REF_VALID(ref) (0) - #endif -#else - #define USARTRF_REF_VALID(ref) (0) -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) -#elif defined(_SILICON_LABS_32B_SERIES_1) - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -// If GG11 or TG11 - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) - #elif defined(USART3) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) - #elif defined(USART2) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) - #else - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - #if defined(_EZR32_HAPPY_FAMILY) - #define USART_IRDA_VALID(ref) ((ref) == USART0) - #elif defined(_EFM32_HAPPY_FAMILY) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #elif defined(USART0) - #define USART_IRDA_VALID(ref) ((ref) == USART0) - #elif (USART_COUNT == 1) && defined(USART1) - #define USART_IRDA_VALID(ref) ((ref) == USART1) - #elif defined(USARTRF0) - #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) - #else - #define USART_IRDA_VALID(ref) (0) - #endif -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - #define USART_I2S_VALID(ref) USART_REF_VALID(ref) -#elif defined(_SILICON_LABS_32B_SERIES_1) - #if defined(USART4) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) - #elif defined(USART3) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) - #else - #define USART_I2S_VALID(ref) ((ref) == USART1) - #endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - #if defined(_EZR32_HAPPY_FAMILY) - #define USART_I2S_VALID(ref) ((ref) == USART0) - #elif defined(_EFM32_HAPPY_FAMILY) - #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) - #define USART_I2S_VALID(ref) ((ref) == USART1) - #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) - #endif -#endif - -#if defined(UART_COUNT) && (UART_COUNT == 1) && !defined(_UART_IPVERSION_MASK) - #define UART_REF_VALID(ref) ((ref) == UART0) -#elif defined(UART_COUNT) && (UART_COUNT == 2) && !defined(_UART_IPVERSION_MASK) - #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) -#else - #define UART_REF_VALID(ref) (0) -#endif - -#if defined(_USART_CLKDIV_DIVEXT_MASK) - #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) -#else - #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if !defined(_EFM32_GECKO_FAMILY) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Rx input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_INPUT_MASK) - usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) - | USART_INPUT_RXPRS; -#elif defined(USART_CTRLX_RXPRSEN) - if (usart == USART0) { - PRS->CONSUMER_USART0_RX = ch; - } -#if defined(USART1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_RX = ch; - } -#endif -#if defined(USART2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_RX = ch; - } -#endif - usart->CTRLX |= USART_CTRLX_RXPRSEN; -#endif -} -#endif - -#if defined(USART_IRCTRL_IRPRSEN) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Ir input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_IRCTRL_IRPRSSEL_SHIFT) - usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) - | USART_IRCTRL_IRPRSEN; -#else - (void)ch; - usart->IRCTRL |= USART_IRCTRL_IRPRSEN; -#endif -} -#endif - -#if defined(USART_IRCTRL_IRPRSEN) && defined(CONSUMER_USART0_IR) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Ir input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ - if (usart == USART0) { - PRS->CONSUMER_USART0_IR = ch; - } -#if defined(USART1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_IR = ch; - } -#endif -#if defined(USART2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_IR = ch; - } -#endif - usart->IRCTRL |= USART_IRCTRL_IRPRSEN; -} -#endif - -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Trigger input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_IRCTRL_IRPRSSEL_MASK) - usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) - | (ch << _USART_TRIGCTRL_TSEL_SHIFT); -#else - if (usart == USART0) { - PRS->CONSUMER_USART0_TRIGGER = ch; - } -#if (USART_COUNT > 1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_TRIGGER = ch; - } -#endif -#if (USART_COUNT > 2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_TRIGGER = ch; - } -#endif -#endif -} - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup usart - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Configure USART/UART operating in asynchronous mode to use a given - * baudrate (or as close as possible to a specified baudrate). - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] refFreq - * USART/UART reference clock frequency in Hz. If set to 0, - * the currently configured reference clock is assumed. - * - * @param[in] baudrate - * Baudrate to try to achieve for USART/UART. - * - * @param[in] ovs - * Oversampling to be used. Normal is 16x oversampling but lower oversampling - * may be used to achieve higher rates or better baudrate accuracy in some - * cases. Notice that lower oversampling frequency makes the channel more - * vulnerable to bit faults during reception due to clock inaccuracies - * compared to the link partner. - ******************************************************************************/ -void USART_BaudrateAsyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate, - USART_OVS_TypeDef ovs) -{ - uint32_t clkdiv; - uint32_t oversample = 0; - - /* Inhibit divide by 0 */ - EFM_ASSERT(baudrate); - - /* - * Use integer division to avoid forcing in float division - * utils and yet keep rounding effect errors to a minimum. - * - * CLKDIV in asynchronous mode is given by: - * - * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) - * or - * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 - * - * The basic problem with integer division in the above formula is that - * the dividend (256 * fHFPERCLK) may become higher than max 32 bit - * integer. Yet, we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. - * Too harsh restrictions on maximum fHFPERCLK value should not be made. - * - * It is possible to factorize 256 and oversample/br. However, - * since the last 6 or 3 bits of CLKDIV are don't care, base the - * integer arithmetic on the below formula - * - * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) - * or - * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) - * - * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK - * up to 1 GHz without overflowing a 32 bit value. - */ - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ - if (!refFreq) { -#if defined(_SILICON_LABS_32B_SERIES_2) - refFreq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - } - - /* Map oversampling. */ - switch (ovs) { - case usartOVS16: - EFM_ASSERT(baudrate <= (refFreq / 16)); - oversample = 16; - break; - - case usartOVS8: - EFM_ASSERT(baudrate <= (refFreq / 8)); - oversample = 8; - break; - - case usartOVS6: - EFM_ASSERT(baudrate <= (refFreq / 6)); - oversample = 6; - break; - - case usartOVS4: - EFM_ASSERT(baudrate <= (refFreq / 4)); - oversample = 4; - break; - - default: - /* Invalid input */ - EFM_ASSERT(0); - break; - } - - if (oversample > 0U) { - /* Calculate and set CLKDIV with fractional bits. - * The added (oversample*baudrate)/2 in the first line is to round the - * divisor to the nearest fractional divisor. */ - #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) - /* Devices with 2 fractional bits. CLKDIV[7:6] */ - clkdiv = 4 * refFreq + (oversample * baudrate) / 2; - clkdiv /= oversample * baudrate; - clkdiv -= 4; - clkdiv *= 64; - #else - /* Devices with 5 fractional bits. CLKDIV[7:3] */ - clkdiv = 32 * refFreq + (oversample * baudrate) / 2; - clkdiv /= oversample * baudrate; - clkdiv -= 32; - clkdiv *= 8; - #endif - - /* Verify that the resulting clock divider is within limits. */ - EFM_ASSERT(clkdiv <= CLKDIV_MASK); - - /* Make sure that reserved bits are not written to. */ - clkdiv &= CLKDIV_MASK; - - usart->CTRL &= ~_USART_CTRL_OVS_MASK; - usart->CTRL |= ovs; - usart->CLKDIV = clkdiv; - } -} - -/***************************************************************************//** - * @brief - * Calculate baudrate for USART/UART given reference frequency, clock division, - * and oversampling rate (if async mode). - * - * @details - * This function returns the baudrate that a USART/UART module will use if - * configured with the given frequency, clock divisor, and mode. Notice that - * this function will not use the hardware configuration. It can be used - * to determine if a given configuration is sufficiently accurate for the - * application. - * - * @param[in] refFreq - * USART/UART HF peripheral frequency used. - * - * @param[in] clkdiv - * A clock division factor to be used. - * - * @param[in] syncmode - * @li True - synchronous mode operation. - * @li False - asynchronous mode operation. - * - * @param[in] ovs - * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. - * - * @return - * Baudrate with given settings. - ******************************************************************************/ -uint32_t USART_BaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - bool syncmode, - USART_OVS_TypeDef ovs) -{ - uint32_t oversample; - uint64_t divisor; - uint64_t factor; - uint64_t remainder; - uint64_t quotient; - uint32_t br; - - /* Out of bound clkdiv. */ - EFM_ASSERT(clkdiv <= CLKDIV_MASK); - - /* Mask out unused bits */ - clkdiv &= CLKDIV_MASK; - - /* Use integer division to avoid forcing in float division */ - /* utils and yet keep rounding effect errors to a minimum. */ - - /* Baudrate calculation depends on if synchronous or asynchronous mode. */ - if (syncmode) { - /* - * Baudrate is given by: - * - * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) - * - * which can be rewritten to - * - * br = (128 * fHFPERCLK)/(256 + CLKDIV) - */ - oversample = 1; /* Not used in sync mode, i.e., 1 */ - factor = 128; - } else { - /* - * Baudrate in asynchronous mode is given by: - * - * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) - * - * which can be rewritten to - * - * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) - * - * 256 factor of the dividend is reduced with a - * (part of) oversample part of the divisor. - */ - - switch (ovs) { - case usartOVS16: - oversample = 1; - factor = 256 / 16; - break; - - case usartOVS8: - oversample = 1; - factor = 256 / 8; - break; - - case usartOVS6: - oversample = 3; - factor = 256 / 2; - break; - - default: - oversample = 1; - factor = 256 / 4; - break; - } - } - - /* - * The basic problem with integer division in the above formula is that - * the dividend (factor * fHFPERCLK) may become larger than a 32 bit - * integer. Yet we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. Too harsh restrictions - * should not be made on the maximum fHFPERCLK value either. - * - * For division a/b, - * - * a = qb + r - * - * where q is the quotient and r is the remainder, both integers. - * - * The original baudrate formula can be rewritten as - * - * br = xa / b = x(qb + r)/b = xq + xr/b - * - * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to - * variable names. - */ - - /* - * The divisor will never exceed max 32 bit value since - * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) - * and 'oversample' has been reduced to <= 3. - */ - divisor = (uint64_t)(oversample * (256 + clkdiv)); - - quotient = refFreq / divisor; - remainder = refFreq % divisor; - - /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ - /* 32 bit value. However, factor * remainder can become larger than 32-bit */ - /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ - br = (uint32_t)(factor * quotient); - - /* - * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which - * means dividend (factor * remainder) worst case is - * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. - */ - br += (uint32_t)((factor * remainder) / divisor); - - return br; -} - -/***************************************************************************//** - * @brief - * Get the current baudrate for USART/UART. - * - * @details - * This function returns the actual baudrate (not considering oscillator - * inaccuracies) used by a USART/UART peripheral. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * The current baudrate. - ******************************************************************************/ -uint32_t USART_BaudrateGet(USART_TypeDef *usart) -{ - uint32_t freq; - USART_OVS_TypeDef ovs; - bool syncmode; - - if (usart->CTRL & USART_CTRL_SYNC) { - syncmode = true; - } else { - syncmode = false; - } - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - freq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - freq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - freq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - freq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); - return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); -} - -/***************************************************************************//** - * @brief - * Configure the USART operating in synchronous mode to use a given baudrate - * (or as close as possible to a specified baudrate). - * - * @details - * The configuration will be set to use a baudrate <= the specified baudrate - * to ensure that the baudrate does not exceed the specified value. - * - * The fractional clock division is suppressed, although the hardware design allows it. - * It could cause half clock cycles to exceed a specified limit and thus - * potentially violate specifications for the slave device. In some special - * situations, a fractional clock division may be useful even in synchronous - * mode, but in those cases it must be directly adjusted, possibly assisted - * by USART_BaudrateCalc(): - * - * @warning - * The consequence of the aforementioned suppression of the fractional part of - * the clock divider is that some frequencies won't be achievable. The divider - * will only be able to be an integer value so the reference clock will only be - * dividable by N (where N is a positive integer). - * - * @param[in] usart - * A pointer to the USART peripheral register block. (Cannot be used on UART - * modules.) - * - * @param[in] refFreq - * A USART reference clock frequency in Hz that will be used. If set to 0, - * the currently-configured reference clock is assumed. - * - * @param[in] baudrate - * Baudrate to try to achieve for USART. - ******************************************************************************/ -void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) -{ - uint32_t clkdiv; - - /* Prevent dividing by 0. */ - EFM_ASSERT(baudrate); - - /* - * CLKDIV in synchronous mode is given by: - * - * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) - */ - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ - if (!refFreq) { -#if defined(_SILICON_LABS_32B_SERIES_2) - refFreq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - } - - /* - * The clock divider computation is done by using unsigned integer. - * The goal is to truncate the fractional part of the resulting - * clock divider value. - * Note: The divider field of the USART->CLKDIV register is of the following form: - * xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider - * and y is the 5 bits fractional part. - */ - clkdiv = (refFreq - 1) / (2 * baudrate); - clkdiv = clkdiv << 8; - - /* Verify that resulting clock divider is within limits. */ - EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); - - usart->CLKDIV = clkdiv; -} - -/***************************************************************************//** - * @brief - * Enable/disable USART/UART receiver and/or transmitter. - * - * @details - * Notice that this function does not do any configuration. Enabling should - * normally be done after initialization (if not enabled as part - * of initialization). - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] enable - * Select the status for the receiver/transmitter. - ******************************************************************************/ -void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) -{ - uint32_t tmp; - - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart)); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - - /* Disable as specified. */ - tmp = ~((uint32_t)enable); - tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; - usart->CMD = tmp << 1; - - /* Enable as specified. */ - usart->CMD = (uint32_t)enable; - -#if defined(USART_EN_EN) - if (enable == usartDisable) { - usart->EN_CLR = USART_EN_EN; - } -#endif -} - -/***************************************************************************//** - * @brief - * Initialize USART/UART for normal asynchronous mode. - * - * @details - * This function will configure basic settings to operate in normal - * asynchronous mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL register. - * - * Notice that pins used by the USART/UART module must be properly configured - * by the user explicitly for the USART/UART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure the basic async setup. - ******************************************************************************/ -void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart)); - - /* Initialize USART registers to hardware reset state. */ - USART_Reset(usart); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - -#if defined(USART_CTRL_MVDIS) - /* Disable the majority vote if specified. */ - if (init->mvdis) { - usart->CTRL |= USART_CTRL_MVDIS; - } -#endif - -#if !defined(_EFM32_GECKO_FAMILY) - /* Configure the PRS input mode. */ - if (init->prsRxEnable) { - prsRxInput(usart, init->prsRxCh); - } -#endif - - /* Configure databits, stopbits, and parity. */ - usart->FRAME = (uint32_t)init->databits - | (uint32_t)init->stopbits - | (uint32_t)init->parity; - - /* Configure baudrate. */ - USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); - - if (init->autoCsEnable) { - usart->CTRL |= USART_CTRL_AUTOCS; - } - if (init->csInv) { - usart->CTRL |= USART_CTRL_CSINV; - } -#if defined(_USART_TIMING_CSHOLD_MASK) - usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) - & _USART_TIMING_CSHOLD_MASK) - | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) - & _USART_TIMING_CSSETUP_MASK); - -#endif - -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) - usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); - usart->ROUTEPEN |= init->hwFlowControl; - -#elif defined(USART_CTRLX_CTSEN) - if ((init->hwFlowControl == usartHwFlowControlRts) - || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { -#if USART_COUNT > 1 - GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#else - //! @todo cleanup when ADM is updated to have USART_NUM macros - GPIO->USARTROUTE_SET[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#endif - } else { -#if USART_COUNT > 1 - GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#else - //! @todo cleanup when ADM is updated to have USART_NUM macros - GPIO->USARTROUTE_CLR[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#endif - } - - if ((init->hwFlowControl == usartHwFlowControlCts) - || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { - usart->CTRLX_SET = USART_CTRLX_CTSEN; - } else { - usart->CTRLX_CLR = USART_CTRLX_CTSEN; - } -#endif - - /* Finally, enable (as specified). */ - usart->CMD = (uint32_t)init->enable; -} - -/***************************************************************************//** - * @brief - * Initialize USART for synchronous mode. - * - * @details - * This function will configure basic settings to operate in - * synchronous mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL register. - * - * Notice that pins used by the USART module must be properly configured - * by the user explicitly for the USART to work as intended. - * (When configuring pins remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. (UART does not support this - * mode.) - * - * @param[in] init - * A pointer to the initialization structure used to configure basic async setup. - ******************************************************************************/ -void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); - - /* Initialize USART registers to hardware reset state. */ - USART_Reset(usart); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - - /* Set bits for synchronous mode. */ - usart->CTRL |= (USART_CTRL_SYNC) - | (uint32_t)init->clockMode - | (init->msbf ? USART_CTRL_MSBF : 0); - -#if defined(_USART_CTRL_AUTOTX_MASK) - usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; -#endif - -#if !defined(_EFM32_GECKO_FAMILY) - if (init->prsRxEnable) { - prsRxInput(usart, init->prsRxCh); - } -#endif - - /* Configure databits, leave stopbits and parity at reset default (not used). */ - usart->FRAME = (uint32_t)init->databits - | USART_FRAME_STOPBITS_DEFAULT - | USART_FRAME_PARITY_DEFAULT; - - /* Configure the baudrate. */ - USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); - - /* Finally, enable (as specified). */ - if (init->master) { - usart->CMD = USART_CMD_MASTEREN; - } - - if (init->autoCsEnable) { - usart->CTRL |= USART_CTRL_AUTOCS; - } - if (init->csInv) { - usart->CTRL |= USART_CTRL_CSINV; - } -#if defined(_USART_TIMING_CSHOLD_MASK) - usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) - & _USART_TIMING_CSHOLD_MASK) - | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) - & _USART_TIMING_CSSETUP_MASK); -#endif - - usart->CMD = (uint32_t)init->enable; -} - -/***************************************************************************//** - * @brief - * Initialize USART for asynchronous IrDA mode. - * - * @details - * This function will configure basic settings to operate in - * asynchronous IrDA mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL and IRCTRL - * registers. - * - * Notice that pins used by the USART/UART module must be properly configured - * by the user explicitly for the USART/UART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure async IrDA setup. - * - * @note - * Not all USART instances support IrDA. See the data sheet for your device. - * - ******************************************************************************/ -void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) -{ - EFM_ASSERT(USART_IRDA_VALID(usart)); - - /* Initialize USART as an async device. */ - USART_InitAsync(usart, &(init->async)); - - /* Set IrDA modulation to RZI (return-to-zero-inverted). */ - usart->CTRL |= USART_CTRL_TXINV; - - /* Invert the Rx signal before the demodulator if enabled. */ - if (init->irRxInv) { - usart->CTRL |= USART_CTRL_RXINV; - } - - /* Configure IrDA. */ - usart->IRCTRL = (uint32_t)init->irPw - | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); - -#if defined(USART_IRCTRL_IRPRSEN) - if (init->irPrsEn) { - prsIrInput(usart, init->irPrsSel); - } -#endif - - /* Enable IrDA. */ - usart->IRCTRL |= USART_IRCTRL_IREN; -} - -#if defined(_USART_I2SCTRL_MASK) -/***************************************************************************//** - * @brief - * Initialize USART for I2S mode. - * - * @details - * This function will configure basic settings to operate in I2S - * mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL and I2SCTRL - * registers. - * - * Notice that pins used by the USART module must be properly configured - * by the user explicitly for the USART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. (UART does not support this - * mode.) - * - * @param[in] init - * A pointer to the initialization structure used to configure the basic I2S setup. - * - * @note - * This function does not apply to all USART's. See the chip Reference Manual. - * - ******************************************************************************/ -void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) -{ - USART_Enable_TypeDef enable; - - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_I2S_VALID(usart)); - - /* Override the enable setting. */ - enable = init->sync.enable; - init->sync.enable = usartDisable; - - /* Initialize USART as a sync device. */ - USART_InitSync(usart, &init->sync); - - /* Configure and enable I2CCTRL register according to the selected mode. */ - usart->I2SCTRL = (uint32_t)init->format - | (uint32_t)init->justify - | (init->delay ? USART_I2SCTRL_DELAY : 0) - | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) - | (init->mono ? USART_I2SCTRL_MONO : 0) - | USART_I2SCTRL_EN; - - if (enable != usartDisable) { - USART_Enable(usart, enable); - } -} -#endif - -/***************************************************************************//** - * @brief - * Initialize the automatic transmissions using PRS channel as a trigger. - * @note - * Initialize USART with USART_Init() before setting up the PRS configuration. - * - * @param[in] usart - * A pointer to USART to configure. - * - * @param[in] init - * A pointer to the initialization structure. - ******************************************************************************/ -void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) -{ - uint32_t trigctrl; - - prsTriggerInput(usart, init->prsTriggerChannel); - /* Clear values that will be reconfigured. */ - trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK - | _USART_TRIGCTRL_TXTEN_MASK -#if defined(USART_TRIGCTRL_AUTOTXTEN) - | _USART_TRIGCTRL_AUTOTXTEN_MASK -#endif - ); - -#if defined(USART_TRIGCTRL_AUTOTXTEN) - if (init->autoTxTriggerEnable) { - trigctrl |= USART_TRIGCTRL_AUTOTXTEN; - } -#endif - if (init->txTriggerEnable) { - trigctrl |= USART_TRIGCTRL_TXTEN; - } - if (init->rxTriggerEnable) { - trigctrl |= USART_TRIGCTRL_RXTEN; - } - usart->TRIGCTRL = trigctrl; -} - -/***************************************************************************//** - * @brief - * Reset USART/UART to the same state that it was in after a hardware reset. - * - * @param[in] usart - * A pointer to USART/UART peripheral register block. - ******************************************************************************/ -void USART_Reset(USART_TypeDef *usart) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart) ); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; - /* Make sure disabled first, before resetting other registers. */ - usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS - | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX - | USART_CMD_CLEARRX; - - usart->CTRL = _USART_CTRL_RESETVALUE; - usart->CTRLX = _USART_CTRLX_RESETVALUE; - usart->FRAME = _USART_FRAME_RESETVALUE; - usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; - usart->CLKDIV = _USART_CLKDIV_RESETVALUE; - usart->IEN = _USART_IEN_RESETVALUE; - usart->IF_CLR = _USART_IF_MASK; - usart->TIMING = _USART_TIMING_RESETVALUE; - - if (USART_IRDA_VALID(usart)) { - usart->IRCTRL = _USART_IRCTRL_RESETVALUE; - } - - if (USART_I2S_VALID(usart)) { - usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; - } - usart->EN_CLR = USART_EN_EN; - -#else - /* Make sure disabled first, before resetting other registers */ - usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS - | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX - | USART_CMD_CLEARRX; - - usart->CTRL = _USART_CTRL_RESETVALUE; - usart->FRAME = _USART_FRAME_RESETVALUE; - usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; - usart->CLKDIV = _USART_CLKDIV_RESETVALUE; - usart->IEN = _USART_IEN_RESETVALUE; - usart->IFC = _USART_IFC_MASK; -#if defined(_USART_TIMING_MASK) - usart->TIMING = _USART_TIMING_RESETVALUE; -#endif -#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) - usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; - usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; - usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; -#else - usart->ROUTE = _USART_ROUTE_RESETVALUE; -#endif - - if (USART_IRDA_VALID(usart)) { - usart->IRCTRL = _USART_IRCTRL_RESETVALUE; - } - -#if defined(_USART_INPUT_RESETVALUE) - usart->INPUT = _USART_INPUT_RESETVALUE; -#endif - -#if defined(_USART_I2SCTRL_RESETVALUE) - if (USART_I2S_VALID(usart)) { - usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; - } -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Receive one 4-8 bit frame, (or part of 10-16 bit frame). - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 4-8 bits. See @ref USART_RxExt() for reception of - * 9 bit frames. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDataGet() to read the RXDATA - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint8_t USART_Rx(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXDATAV)) { - } - - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Receive two 4-8 bit frames or one 10-16 bit frame. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits. See @ref USART_RxDoubleExt() for - * reception of two 9 bit frames. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint16_t USART_RxDouble(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXFULL)) { - } - - return (uint16_t)usart->RXDOUBLE; -} - -/***************************************************************************//** - * @brief - * Receive two 4-9 bit frames, or one 10-16 bit frame with extended - * information. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits and additional RX status information is required. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint32_t USART_RxDoubleExt(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXFULL)) { - } - - return usart->RXDOUBLEX; -} - -/***************************************************************************//** - * @brief - * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended - * information. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 4-9 bits and additional RX status information is required. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint16_t USART_RxExt(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXDATAV)) { - } - - return (uint16_t)usart->RXDATAX; -} - -/***************************************************************************//** - * @brief - * Perform one 8 bit frame SPI transfer. - * - * @note - * This function will stall if the transmit buffer is full. When a transmit - * buffer becomes available, data is written and the function will wait until - * data is fully transmitted. The SPI return value is then read out and - * returned. - * - * @param[in] usart - * A pointer to the USART peripheral register block. - * - * @param[in] data - * Data to transmit. - * - * @return - * Data received. - ******************************************************************************/ -uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) -{ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATA = (uint32_t)data; - while (!(usart->STATUS & USART_STATUS_TXC)) { - } - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Transmit one 4-9 bit frame. - * - * @details - * Depending on the frame length configuration, 4-8 (least significant) bits from - * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from - * @p data and one bit as specified by CTRL register, BIT8DV field. - * See USART_TxExt() for transmitting 9 bit frame with full control of - * all 9 bits. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit. See details above for more information. - ******************************************************************************/ -void USART_Tx(USART_TypeDef *usart, uint8_t data) -{ - /* Check that transmit buffer is empty */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATA = (uint32_t)data; -} - -/***************************************************************************//** - * @brief - * Transmit two 4-9 bit frames or one 10-16 bit frame. - * - * @details - * Depending on the frame length configuration, 4-8 (least significant) bits from - * each byte in @p data are transmitted. If frame length is 9, 8 bits are - * transmitted from each byte in @p data adding one bit as specified by the CTRL - * register, BIT8DV field, to each byte. See USART_TxDoubleExt() - * for transmitting two 9 bit frames with full control of all 9 bits. - * - * If the frame length is 10-16, 10-16 (least significant) bits from @p data - * are transmitted. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit, the least significant byte holds the frame transmitted - * first. See details above for more info. - ******************************************************************************/ -void USART_TxDouble(USART_TypeDef *usart, uint16_t data) -{ - /* Check that transmit buffer is empty */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDOUBLE = (uint32_t)data; -} - -/***************************************************************************//** - * @brief - * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. - * - * @details - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit with extended control. Contains two 16 bit words - * concatenated. Least significant word holds the frame transmitted first. If the frame - * length is 4-9, two frames with 4-9 least significant bits from each 16 bit - * word are transmitted. - * @par - * If the frame length is 10-16 bits, 8 data bits are taken from the least - * significant 16 bit word and the remaining bits from the other 16 bit word. - * @par - * Additional control bits are available as documented in the reference - * manual (set to 0 if not used). For 10-16 bit frame length, these control - * bits are taken from the most significant 16 bit word. - ******************************************************************************/ -void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) -{ - /* Check that transmit buffer is empty. */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDOUBLEX = data; -} - -/***************************************************************************//** - * @brief - * Transmit one 4-9 bit frame with extended control. - * - * @details - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit with extended control. Least significant bit contains - * frame bits. Additional control bits are available as documented in - * the reference manual (set to 0 if not used). - ******************************************************************************/ -void USART_TxExt(USART_TypeDef *usart, uint16_t data) -{ - /* Check that the transmit buffer is empty. */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATAX = (uint32_t)data; -} - -/** @} (end addtogroup usart) */ -#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_usart.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" +#if defined(USART_CTRLX_CTSEN) +#include "em_gpio.h" +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of USART register block pointer reference for assert statements. */ +#if (USART_COUNT == 1) && defined(USART0) +#define USART_REF_VALID(ref) ((ref) == USART0) + +#elif (USART_COUNT == 1) && defined(USART1) +#define USART_REF_VALID(ref) ((ref) == USART1) + +#elif (USART_COUNT == 2) && defined(USART2) +#define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + +#elif (USART_COUNT == 2) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + +#elif (USART_COUNT == 3) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2)) +#elif (USART_COUNT == 4) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3)) +#elif (USART_COUNT == 5) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4)) +#elif (USART_COUNT == 6) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4) || ((ref) == USART5)) +#else +#error "Undefined number of USARTs." +#endif + +#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) + #if (USARTRF_COUNT == 1) && defined(USARTRF0) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) + #elif (USARTRF_COUNT == 1) && defined(USARTRF1) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) + #else + #define USARTRF_REF_VALID(ref) (0) + #endif +#else + #define USARTRF_REF_VALID(ref) (0) +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +// If GG11 or TG11 + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) + #elif defined(USART3) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) + #elif defined(USART2) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) + #else + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(USART0) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif (USART_COUNT == 1) && defined(USART1) + #define USART_IRDA_VALID(ref) ((ref) == USART1) + #elif defined(USARTRF0) + #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) + #else + #define USART_IRDA_VALID(ref) (0) + #endif +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_I2S_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(USART4) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) + #elif defined(USART3) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) + #else + #define USART_I2S_VALID(ref) ((ref) == USART1) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + #endif +#endif + +#if defined(UART_COUNT) && (UART_COUNT == 1) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) ((ref) == UART0) +#elif defined(UART_COUNT) && (UART_COUNT == 2) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) +#else + #define UART_REF_VALID(ref) (0) +#endif + +#if defined(_USART_CLKDIV_DIVEXT_MASK) + #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) +#else + #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Rx input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_INPUT_MASK) + usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) + | USART_INPUT_RXPRS; +#elif defined(USART_CTRLX_RXPRSEN) + if (usart == USART0) { + PRS->CONSUMER_USART0_RX = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_RX = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_RX = ch; + } +#endif + usart->CTRLX |= USART_CTRLX_RXPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_SHIFT) + usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) + | USART_IRCTRL_IRPRSEN; +#else + (void)ch; + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) && defined(CONSUMER_USART0_IR) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ + if (usart == USART0) { + PRS->CONSUMER_USART0_IR = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_IR = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_IR = ch; + } +#endif + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +} +#endif + +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Trigger input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_MASK) + usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) + | (ch << _USART_TRIGCTRL_TSEL_SHIFT); +#else + if (usart == USART0) { + PRS->CONSUMER_USART0_TRIGGER = ch; + } +#if (USART_COUNT > 1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_TRIGGER = ch; + } +#endif +#if (USART_COUNT > 2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_TRIGGER = ch; + } +#endif +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup usart + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Configure USART/UART operating in asynchronous mode to use a given + * baudrate (or as close as possible to a specified baudrate). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] refFreq + * USART/UART reference clock frequency in Hz. If set to 0, + * the currently configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART/UART. + * + * @param[in] ovs + * Oversampling to be used. Normal is 16x oversampling but lower oversampling + * may be used to achieve higher rates or better baudrate accuracy in some + * cases. Notice that lower oversampling frequency makes the channel more + * vulnerable to bit faults during reception due to clock inaccuracies + * compared to the link partner. + ******************************************************************************/ +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs) +{ + uint32_t clkdiv; + uint32_t oversample = 0; + + /* Inhibit divide by 0 */ + EFM_ASSERT(baudrate); + + /* + * Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * CLKDIV in asynchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) + * or + * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fHFPERCLK) may become higher than max 32 bit + * integer. Yet, we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. + * Too harsh restrictions on maximum fHFPERCLK value should not be made. + * + * It is possible to factorize 256 and oversample/br. However, + * since the last 6 or 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula + * + * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) + * or + * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) + * + * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK + * up to 1 GHz without overflowing a 32 bit value. + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* Map oversampling. */ + switch (ovs) { + case usartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case usartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case usartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case usartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + default: + /* Invalid input */ + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + /* Calculate and set CLKDIV with fractional bits. + * The added (oversample*baudrate)/2 in the first line is to round the + * divisor to the nearest fractional divisor. */ + #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) + /* Devices with 2 fractional bits. CLKDIV[7:6] */ + clkdiv = 4 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 4; + clkdiv *= 64; + #else + /* Devices with 5 fractional bits. CLKDIV[7:3] */ + clkdiv = 32 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 32; + clkdiv *= 8; + #endif + + /* Verify that the resulting clock divider is within limits. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Make sure that reserved bits are not written to. */ + clkdiv &= CLKDIV_MASK; + + usart->CTRL &= ~_USART_CTRL_OVS_MASK; + usart->CTRL |= ovs; + usart->CLKDIV = clkdiv; + } +} + +/***************************************************************************//** + * @brief + * Calculate baudrate for USART/UART given reference frequency, clock division, + * and oversampling rate (if async mode). + * + * @details + * This function returns the baudrate that a USART/UART module will use if + * configured with the given frequency, clock divisor, and mode. Notice that + * this function will not use the hardware configuration. It can be used + * to determine if a given configuration is sufficiently accurate for the + * application. + * + * @param[in] refFreq + * USART/UART HF peripheral frequency used. + * + * @param[in] clkdiv + * A clock division factor to be used. + * + * @param[in] syncmode + * @li True - synchronous mode operation. + * @li False - asynchronous mode operation. + * + * @param[in] ovs + * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. + * + * @return + * Baudrate with given settings. + ******************************************************************************/ +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + /* Out of bound clkdiv. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Mask out unused bits */ + clkdiv &= CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division */ + /* utils and yet keep rounding effect errors to a minimum. */ + + /* Baudrate calculation depends on if synchronous or asynchronous mode. */ + if (syncmode) { + /* + * Baudrate is given by: + * + * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (128 * fHFPERCLK)/(256 + CLKDIV) + */ + oversample = 1; /* Not used in sync mode, i.e., 1 */ + factor = 128; + } else { + /* + * Baudrate in asynchronous mode is given by: + * + * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case usartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case usartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case usartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + default: + oversample = 1; + factor = 256 / 4; + break; + } + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fHFPERCLK) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fHFPERCLK value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ + /* 32 bit value. However, factor * remainder can become larger than 32-bit */ + /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ + br = (uint32_t)(factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. + */ + br += (uint32_t)((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * @brief + * Get the current baudrate for USART/UART. + * + * @details + * This function returns the actual baudrate (not considering oscillator + * inaccuracies) used by a USART/UART peripheral. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * The current baudrate. + ******************************************************************************/ +uint32_t USART_BaudrateGet(USART_TypeDef *usart) +{ + uint32_t freq; + USART_OVS_TypeDef ovs; + bool syncmode; + + if (usart->CTRL & USART_CTRL_SYNC) { + syncmode = true; + } else { + syncmode = false; + } + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + freq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + freq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + freq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + freq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); + return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); +} + +/***************************************************************************//** + * @brief + * Configure the USART operating in synchronous mode to use a given baudrate + * (or as close as possible to a specified baudrate). + * + * @details + * The configuration will be set to use a baudrate <= the specified baudrate + * to ensure that the baudrate does not exceed the specified value. + * + * The fractional clock division is suppressed, although the hardware design allows it. + * It could cause half clock cycles to exceed a specified limit and thus + * potentially violate specifications for the slave device. In some special + * situations, a fractional clock division may be useful even in synchronous + * mode, but in those cases it must be directly adjusted, possibly assisted + * by USART_BaudrateCalc(): + * + * @warning + * The consequence of the aforementioned suppression of the fractional part of + * the clock divider is that some frequencies won't be achievable. The divider + * will only be able to be an integer value so the reference clock will only be + * dividable by N (where N is a positive integer). + * + * @param[in] usart + * A pointer to the USART peripheral register block. (Cannot be used on UART + * modules.) + * + * @param[in] refFreq + * A USART reference clock frequency in Hz that will be used. If set to 0, + * the currently-configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART. + ******************************************************************************/ +void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) +{ + uint32_t clkdiv; + + /* Prevent dividing by 0. */ + EFM_ASSERT(baudrate); + + /* + * CLKDIV in synchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* + * The clock divider computation is done by using unsigned integer. + * The goal is to truncate the fractional part of the resulting + * clock divider value. + * Note: The divider field of the USART->CLKDIV register is of the following form: + * xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider + * and y is the 5 bits fractional part. + */ + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; + + /* Verify that resulting clock divider is within limits. */ + EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); + + usart->CLKDIV = clkdiv; +} + +/***************************************************************************//** + * @brief + * Enable/disable USART/UART receiver and/or transmitter. + * + * @details + * Notice that this function does not do any configuration. Enabling should + * normally be done after initialization (if not enabled as part + * of initialization). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] enable + * Select the status for the receiver/transmitter. + ******************************************************************************/ +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) +{ + uint32_t tmp; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Disable as specified. */ + tmp = ~((uint32_t)enable); + tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; + usart->CMD = tmp << 1; + + /* Enable as specified. */ + usart->CMD = (uint32_t)enable; + +#if defined(USART_EN_EN) + if (enable == usartDisable) { + usart->EN_CLR = USART_EN_EN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Initialize USART/UART for normal asynchronous mode. + * + * @details + * This function will configure basic settings to operate in normal + * asynchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic async setup. + ******************************************************************************/ +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + +#if defined(USART_CTRL_MVDIS) + /* Disable the majority vote if specified. */ + if (init->mvdis) { + usart->CTRL |= USART_CTRL_MVDIS; + } +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + /* Configure the PRS input mode. */ + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, stopbits, and parity. */ + usart->FRAME = (uint32_t)init->databits + | (uint32_t)init->stopbits + | (uint32_t)init->parity; + + /* Configure baudrate. */ + USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); + +#endif + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) + usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); + usart->ROUTEPEN |= init->hwFlowControl; + +#elif defined(USART_CTRLX_CTSEN) + if ((init->hwFlowControl == usartHwFlowControlRts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { +#if USART_COUNT > 1 + GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_SET[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } else { +#if USART_COUNT > 1 + GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_CLR[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } + + if ((init->hwFlowControl == usartHwFlowControlCts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { + usart->CTRLX_SET = USART_CTRLX_CTSEN; + } else { + usart->CTRLX_CLR = USART_CTRLX_CTSEN; + } +#endif + + /* Finally, enable (as specified). */ + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for synchronous mode. + * + * @details + * This function will configure basic settings to operate in + * synchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure basic async setup. + ******************************************************************************/ +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Set bits for synchronous mode. */ + usart->CTRL |= (USART_CTRL_SYNC) + | (uint32_t)init->clockMode + | (init->msbf ? USART_CTRL_MSBF : 0); + +#if defined(_USART_CTRL_AUTOTX_MASK) + usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, leave stopbits and parity at reset default (not used). */ + usart->FRAME = (uint32_t)init->databits + | USART_FRAME_STOPBITS_DEFAULT + | USART_FRAME_PARITY_DEFAULT; + + /* Configure the baudrate. */ + USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); + + /* Finally, enable (as specified). */ + if (init->master) { + usart->CMD = USART_CMD_MASTEREN; + } + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); +#endif + + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for asynchronous IrDA mode. + * + * @details + * This function will configure basic settings to operate in + * asynchronous IrDA mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and IRCTRL + * registers. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure async IrDA setup. + * + * @note + * Not all USART instances support IrDA. See the data sheet for your device. + * + ******************************************************************************/ +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) +{ + EFM_ASSERT(USART_IRDA_VALID(usart)); + + /* Initialize USART as an async device. */ + USART_InitAsync(usart, &(init->async)); + + /* Set IrDA modulation to RZI (return-to-zero-inverted). */ + usart->CTRL |= USART_CTRL_TXINV; + + /* Invert the Rx signal before the demodulator if enabled. */ + if (init->irRxInv) { + usart->CTRL |= USART_CTRL_RXINV; + } + + /* Configure IrDA. */ + usart->IRCTRL = (uint32_t)init->irPw + | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); + +#if defined(USART_IRCTRL_IRPRSEN) + if (init->irPrsEn) { + prsIrInput(usart, init->irPrsSel); + } +#endif + + /* Enable IrDA. */ + usart->IRCTRL |= USART_IRCTRL_IREN; +} + +#if defined(_USART_I2SCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize USART for I2S mode. + * + * @details + * This function will configure basic settings to operate in I2S + * mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and I2SCTRL + * registers. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic I2S setup. + * + * @note + * This function does not apply to all USART's. See the chip Reference Manual. + * + ******************************************************************************/ +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) +{ + USART_Enable_TypeDef enable; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_I2S_VALID(usart)); + + /* Override the enable setting. */ + enable = init->sync.enable; + init->sync.enable = usartDisable; + + /* Initialize USART as a sync device. */ + USART_InitSync(usart, &init->sync); + + /* Configure and enable I2CCTRL register according to the selected mode. */ + usart->I2SCTRL = (uint32_t)init->format + | (uint32_t)init->justify + | (init->delay ? USART_I2SCTRL_DELAY : 0) + | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) + | (init->mono ? USART_I2SCTRL_MONO : 0) + | USART_I2SCTRL_EN; + + if (enable != usartDisable) { + USART_Enable(usart, enable); + } +} +#endif + +/***************************************************************************//** + * @brief + * Initialize the automatic transmissions using PRS channel as a trigger. + * @note + * Initialize USART with USART_Init() before setting up the PRS configuration. + * + * @param[in] usart + * A pointer to USART to configure. + * + * @param[in] init + * A pointer to the initialization structure. + ******************************************************************************/ +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) +{ + uint32_t trigctrl; + + prsTriggerInput(usart, init->prsTriggerChannel); + /* Clear values that will be reconfigured. */ + trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK + | _USART_TRIGCTRL_TXTEN_MASK +#if defined(USART_TRIGCTRL_AUTOTXTEN) + | _USART_TRIGCTRL_AUTOTXTEN_MASK +#endif + ); + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + if (init->autoTxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_AUTOTXTEN; + } +#endif + if (init->txTriggerEnable) { + trigctrl |= USART_TRIGCTRL_TXTEN; + } + if (init->rxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_RXTEN; + } + usart->TRIGCTRL = trigctrl; +} + +/***************************************************************************//** + * @brief + * Reset USART/UART to the same state that it was in after a hardware reset. + * + * @param[in] usart + * A pointer to USART/UART peripheral register block. + ******************************************************************************/ +void USART_Reset(USART_TypeDef *usart) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart) ); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; + /* Make sure disabled first, before resetting other registers. */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->CTRLX = _USART_CTRLX_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IF_CLR = _USART_IF_MASK; + usart->TIMING = _USART_TIMING_RESETVALUE; + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } + usart->EN_CLR = USART_EN_EN; + +#else + /* Make sure disabled first, before resetting other registers */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IFC = _USART_IFC_MASK; +#if defined(_USART_TIMING_MASK) + usart->TIMING = _USART_TIMING_RESETVALUE; +#endif +#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) + usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; + usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; +#else + usart->ROUTE = _USART_ROUTE_RESETVALUE; +#endif + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + +#if defined(_USART_INPUT_RESETVALUE) + usart->INPUT = _USART_INPUT_RESETVALUE; +#endif + +#if defined(_USART_I2SCTRL_RESETVALUE) + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-8 bits. See @ref USART_RxExt() for reception of + * 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataGet() to read the RXDATA + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_Rx(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames or one 10-16 bit frame. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. See @ref USART_RxDoubleExt() for + * reception of two 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxDouble(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint32_t USART_RxDoubleExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-9 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint16_t)usart->RXDATAX; +} + +/***************************************************************************//** + * @brief + * Perform one 8 bit frame SPI transfer. + * + * @note + * This function will stall if the transmit buffer is full. When a transmit + * buffer becomes available, data is written and the function will wait until + * data is fully transmitted. The SPI return value is then read out and + * returned. + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] data + * Data to transmit. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) +{ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; + while (!(usart->STATUS & USART_STATUS_TXC)) { + } + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from + * @p data and one bit as specified by CTRL register, BIT8DV field. + * See USART_TxExt() for transmitting 9 bit frame with full control of + * all 9 bits. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit. See details above for more information. + ******************************************************************************/ +void USART_Tx(USART_TypeDef *usart, uint8_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * each byte in @p data are transmitted. If frame length is 9, 8 bits are + * transmitted from each byte in @p data adding one bit as specified by the CTRL + * register, BIT8DV field, to each byte. See USART_TxDoubleExt() + * for transmitting two 9 bit frames with full control of all 9 bits. + * + * If the frame length is 10-16, 10-16 (least significant) bits from @p data + * are transmitted. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit, the least significant byte holds the frame transmitted + * first. See details above for more info. + ******************************************************************************/ +void USART_TxDouble(USART_TypeDef *usart, uint16_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLE = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Contains two 16 bit words + * concatenated. Least significant word holds the frame transmitted first. If the frame + * length is 4-9, two frames with 4-9 least significant bits from each 16 bit + * word are transmitted. + * @par + * If the frame length is 10-16 bits, 8 data bits are taken from the least + * significant 16 bit word and the remaining bits from the other 16 bit word. + * @par + * Additional control bits are available as documented in the reference + * manual (set to 0 if not used). For 10-16 bit frame length, these control + * bits are taken from the most significant 16 bit word. + ******************************************************************************/ +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) +{ + /* Check that transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLEX = data; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Least significant bit contains + * frame bits. Additional control bits are available as documented in + * the reference manual (set to 0 if not used). + ******************************************************************************/ +void USART_TxExt(USART_TypeDef *usart, uint16_t data) +{ + /* Check that the transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATAX = (uint32_t)data; +} + +/** @} (end addtogroup usart) */ +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_vdac.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_vdac.c index c4ad2e3..4a4da14 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_vdac.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_vdac.c @@ -1,636 +1,636 @@ -/***************************************************************************//** - * @file - * @brief Digital to Analog Converter (VDAC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_vdac.h" -#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) -#include "em_cmu.h" - -/***************************************************************************//** - * @addtogroup vdac - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the VDAC channel for assert statements. */ -#define VDAC_CH_VALID(ch) ((ch) <= 1) - -/** A maximum VDAC clock. */ -#define VDAC_MAX_CLOCK 1000000 - -/** The maximum clock frequency of the internal clock oscillator, 10 MHz + 20%. */ -#define VDAC_INTERNAL_CLOCK_FREQ 12000000 - -/** @endcond */ - -/******************************************************************************* - *************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_VDAC_EN_MASK) -static void VDAC_DisableModule(VDAC_TypeDef* vdac) -{ - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - - /* Wait for all synchronizations to finish */ - if (vdac->EN & VDAC_EN_EN) { - vdac->CMD = _VDAC_CMD_CH0DIS_MASK; - while (vdac->STATUS & (VDAC_STATUS_CH0ENS)) { - } - - vdac->CMD = _VDAC_CMD_CH1DIS_MASK; - while (vdac->STATUS & (VDAC_STATUS_CH1ENS)) { - } - -#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - - vdac->CMD = VDAC_CMD_CH0FIFOFLUSH | VDAC_CMD_CH1FIFOFLUSH; - - while (vdac->STATUS & (VDAC_STATUS_SYNCBUSY | VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { - } -#endif - vdac->EN_CLR = _VDAC_EN_EN_MASK; - while (vdac->EN & _VDAC_EN_DISABLING_MASK) { - } - } -} -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Enable/disable the VDAC channel. - * - * @param[in] vdac - * A pointer to the VDAC peripheral register block. - * - * @param[in] ch - * A channel to enable/disable. - * - * @param[in] enable - * True to enable VDAC channel, false to disable. - ******************************************************************************/ -void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) -{ - EFM_ASSERT(VDAC_REF_VALID(vdac)); - EFM_ASSERT(VDAC_CH_VALID(ch)); - -#if defined(_VDAC_STATUS_SYNCBUSY_MASK) - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } -#endif - - if (ch == 0) { - if (enable) { - vdac->CMD = VDAC_CMD_CH0EN; - while ((vdac->STATUS & VDAC_STATUS_CH0ENS) == 0) { - } - } else { - vdac->CMD = VDAC_CMD_CH0DIS; - while (vdac->STATUS & VDAC_STATUS_CH0ENS) { - } -#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - vdac->CMD = VDAC_CMD_CH0FIFOFLUSH; - while (vdac->STATUS & VDAC_STATUS_CH0FIFOFLBUSY) { - } -#endif - } - } else { - if (enable) { - vdac->CMD = VDAC_CMD_CH1EN; - while ((vdac->STATUS & VDAC_STATUS_CH1ENS) == 0) { - } - } else { - vdac->CMD = VDAC_CMD_CH1DIS; - while (vdac->STATUS & VDAC_STATUS_CH1ENS) { - } - -#if defined(_VDAC_CMD_CH1FIFOFLUSH_MASK) - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - vdac->CMD = VDAC_CMD_CH1FIFOFLUSH; - while (vdac->STATUS & VDAC_STATUS_CH1FIFOFLBUSY) { - } -#endif - } - } -} - -/***************************************************************************//** - * @brief - * Initialize VDAC. - * - * @details - * Initializes the common parts for both channels. This function will also load - * calibration values from the Device Information (DI) page into the VDAC - * calibration register. - * To complete a VDAC setup, channel control configuration must also be done. - * See VDAC_InitChannel(). - * - * @note - * This function will disable both channels prior to configuration. - * - * @param[in] vdac - * A pointer to the VDAC peripheral register block. - * - * @param[in] init - * A pointer to the VDAC initialization structure. - ******************************************************************************/ -void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) -{ - EFM_ASSERT(VDAC_REF_VALID(vdac)); - uint32_t config = 0; - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - uint32_t cal; - uint32_t const volatile *calData; - - /* Make sure both channels are disabled. */ - vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; - while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { - } - - /* Get the OFFSETTRIM calibration value. */ - cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) - >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) - << _VDAC_CAL_OFFSETTRIM_SHIFT; - - if (init->mainCalibration) { - calData = &DEVINFO->VDAC0MAINCAL; - } else { - calData = &DEVINFO->VDAC0ALTCAL; - } - - /* Get the correct GAINERRTRIM calibration value. */ - switch (init->reference) { - case vdacRef1V25Ln: - config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) - >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; - break; - - case vdacRef2V5Ln: - config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) - >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; - break; - - case vdacRef1V25: - config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) - >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; - break; - - case vdacRef2V5: - config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) - >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; - break; - - case vdacRefAvdd: - case vdacRefExtPin: - config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) - >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; - break; - } - - /* Set the sGAINERRTRIM calibration value. */ - cal |= config << _VDAC_CAL_GAINERRTRIM_SHIFT; - - /* Get the GAINERRTRIMCH1 calibration value. */ - switch (init->reference) { - case vdacRef1V25Ln: - case vdacRef1V25: - case vdacRefAvdd: - case vdacRefExtPin: - config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) - >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; - break; - - case vdacRef2V5Ln: - case vdacRef2V5: - config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) - >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; - break; - } - - /* Set the GAINERRTRIM calibration value. */ - cal |= config << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; - - config = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) - | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) - | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) - | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) - & _VDAC_CTRL_PRESC_MASK) - | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) - | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) - | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) - | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) - | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); - - /* Write to VDAC registers. */ - vdac->CAL = cal; - vdac->CTRL = config; -#elif defined(_SILICON_LABS_32B_SERIES_2) - - VDAC_DisableModule(vdac); - - config = ( -#if defined(VDAC_CFG_SINEMODEPRS) - ((uint32_t)init->sineModePrsEnable ? VDAC_CFG_SINEMODEPRS : 0U) | -#endif -#if defined(VDAC_CFG_OUTENPRS) - ((uint32_t)init->prsOutEnable ? VDAC_CFG_OUTENPRS : 0U) | -#endif - (((uint32_t)init->warmupTime << _VDAC_CFG_WARMUPTIME_SHIFT) & _VDAC_CFG_WARMUPTIME_MASK) - | ((uint32_t)init->dbgHalt << _VDAC_CFG_DBGHALT_SHIFT) - | ((uint32_t)init->onDemandClk << _VDAC_CFG_ONDEMANDCLK_SHIFT) - | ((uint32_t)init->dmaWakeUp << _VDAC_CFG_DMAWU_SHIFT) - | ((uint32_t)init->biasKeepWarm << _VDAC_CFG_BIASKEEPWARM_SHIFT) - | ((uint32_t)init->refresh << _VDAC_CFG_REFRESHPERIOD_SHIFT) - | ((uint32_t)init->timerOverflow << _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT) - | (((uint32_t)init->prescaler << _VDAC_CFG_PRESC_SHIFT) & _VDAC_CFG_PRESC_MASK) - | ((uint32_t)init->reference << _VDAC_CFG_REFRSEL_SHIFT) - | ((uint32_t)init->ch0ResetPre << _VDAC_CFG_CH0PRESCRST_SHIFT) - | ((uint32_t)init->sineReset << _VDAC_CFG_SINERESET_SHIFT) - | ((uint32_t)init->sineEnable << _VDAC_CFG_SINEMODE_SHIFT) - | ((uint32_t)init->diff << _VDAC_CFG_DIFF_SHIFT)); - - vdac->CFG = config; -#endif -} - -/***************************************************************************//** - * @brief - * Initialize a VDAC channel. - * - * @param[in] vdac - * A pointer to the VDAC peripheral register block. - * - * @param[in] init - * A pointer to the VDAC channel initialization structure. - * - * @param[in] ch - * A channel number to initialize. - ******************************************************************************/ -void VDAC_InitChannel(VDAC_TypeDef *vdac, - const VDAC_InitChannel_TypeDef *init, - unsigned int ch) -{ - uint32_t channelConfig, vdacStatus; - - EFM_ASSERT(VDAC_REF_VALID(vdac)); - EFM_ASSERT(VDAC_CH_VALID(ch)); - - vdacStatus = vdac->STATUS; - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - - /* Make sure both channels are disabled. */ - vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; - while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { - } - - channelConfig = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) - | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) - | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) - | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); - - if (ch == 0) { - vdac->CH0CTRL = channelConfig; - } else { - vdac->CH1CTRL = channelConfig; - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) - - VDAC_DisableModule(vdac); - - channelConfig = ((uint32_t)init->warmupKeepOn << _VDAC_CH0CFG_KEEPWARM_SHIFT) - | ((uint32_t)init->highCapLoadEnable << _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT) - | (((uint32_t)init->fifoLowDataThreshold << _VDAC_CH0CFG_FIFODVL_SHIFT) & _VDAC_CH0CFG_FIFODVL_MASK) - | ((uint32_t)init->chRefreshSource << _VDAC_CH0CFG_REFRESHSOURCE_SHIFT) - | ((uint32_t)init->trigMode << _VDAC_CH0CFG_TRIGMODE_SHIFT) - | ((uint32_t)init->powerMode << _VDAC_CH0CFG_POWERMODE_SHIFT) - | ((uint32_t)init->sampleOffMode << _VDAC_CH0CFG_CONVMODE_SHIFT); - - if (ch == 0) { - vdac->CH0CFG = channelConfig; - - vdac->OUTTIMERCFG = ((uint32_t)(vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK))) - | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK); - - vdac->EN_SET = _VDAC_EN_EN_MASK; - - vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH0_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK | _VDAC_OUTCTRL_SHORTCH0_MASK | _VDAC_OUTCTRL_AUXOUTENCH0_MASK | _VDAC_OUTCTRL_MAINOUTENCH0_MASK))) - | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH0_MASK) - | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT) - | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH0_SHIFT) - | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT) - | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT); - } else if (ch == 1) { - vdac->CH1CFG = channelConfig; - - vdac->OUTTIMERCFG = (vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK)) - | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK); - - vdac->EN_SET = _VDAC_EN_EN_MASK; - - vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH1_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK | _VDAC_OUTCTRL_SHORTCH1_MASK | _VDAC_OUTCTRL_AUXOUTENCH1_MASK | _VDAC_OUTCTRL_MAINOUTENCH1_MASK))) - | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH1_MASK) - | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT) - | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH1_SHIFT) - | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT) - | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT); - } -#endif - - /* Check if the channel must be enabled. */ - if (init->enable) { - if (ch == 0) { - vdac->CMD = VDAC_CMD_CH0EN; - } else { - vdac->CMD = VDAC_CMD_CH1EN; - } - } - - /* Check if the other channel had to be turned off above - * and needs to be turned on again. */ - if (ch == 0) { - if (vdacStatus & VDAC_STATUS_CH1ENS) { - vdac->CMD = VDAC_CMD_CH1EN; - } - } else { - if (vdacStatus & VDAC_STATUS_CH0ENS) { - vdac->CMD = VDAC_CMD_CH0EN; - } - } -} - -/***************************************************************************//** - * @brief - * Set the output signal of a VDAC channel to a given value. - * - * @details - * This function sets the output signal of a VDAC channel by writing @p value - * to the corresponding CHnDATA register. - * - * @param[in] vdac - * A pointer to the VDAC peripheral register block. - * - * @param[in] channel - * A channel number to set the output of. - * - * @param[in] value - * A value to write to the channel output register CHnDATA. - ******************************************************************************/ -void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, - unsigned int channel, - uint32_t value) -{ - switch (channel) { - case 0: - VDAC_Channel0OutputSet(vdac, value); - break; - case 1: - VDAC_Channel1OutputSet(vdac, value); - break; - default: - EFM_ASSERT(0); - break; - } -} - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Calculate the prescaler value used to determine VDAC clock. - * - * @details - * The VDAC clock is given by the input clock divided by the prescaler+1. - * - * VDAC_CLK = IN_CLK / (prescale + 1) - * - * The maximum VDAC clock is 1 MHz. The input clock is HFPERCLK/HFPERCCLK - * when VDAC synchronous mode is selected, or an internal oscillator of - * 10 MHz +/- 20% when asynchronous mode is selected. - * - * @note - * If the requested VDAC frequency is low and the maximum prescaler value can't - * adjust the actual VDAC frequency lower than requested, the maximum prescaler - * value is returned resulting in a higher VDAC frequency than requested. - * - * @param[in] vdacFreq VDAC frequency target. The frequency will automatically - * be adjusted to be below maximum allowed VDAC clock. - * - * @param[in] syncMode Set to true if you intend to use VDAC in synchronous - * mode. - * - * @param[in] hfperFreq Frequency in Hz of HFPERCLK/HFPERCCLK oscillator. - * Set to 0 to use the currently defined HFPERCLK/HFPERCCLK clock setting. - * This parameter is only used when syncMode is set to true. - * - * @return - * A prescaler value to use for VDAC to achieve a clock value less than - * or equal to @p vdacFreq. - ******************************************************************************/ -uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) -{ - uint32_t ret, refFreq; - - /* Make sure that the selected VDAC clock is below the maximum value. */ - if (vdacFreq > VDAC_MAX_CLOCK) { - vdacFreq = VDAC_MAX_CLOCK; - } - - if (!syncMode) { - refFreq = VDAC_INTERNAL_CLOCK_FREQ; - } else { - if (hfperFreq) { - refFreq = hfperFreq; - } else { - refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); - } - } - - /* Iterate to determine the best prescaler value. Start with the lowest */ - /* prescaler value to get the first equal or less VDAC */ - /* frequency value. */ - for (ret = 0; ret <= (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT); ret++) { - if ((refFreq / (ret + 1)) <= vdacFreq) { - break; - } - } - - /* If ret is higher than the maximum prescaler value, make sure to return - the maximum value. */ - if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) { - ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; - } - - return ret; -} -#else -/***************************************************************************//** - * @brief - * Calculate the prescaler value used to determine VDAC clock. - * - * @details - * The VDAC clock is given by the input clock divided by the prescaler+1. - * - * VDAC_CLK = IN_CLK / (prescale + 1) - * - * The maximum VDAC clock is 1 MHz. - * - * @note - * If the requested VDAC frequency is low and the maximum prescaler value can't - * adjust the actual VDAC frequency lower than requested, the maximum prescaler - * value is returned resulting in a higher VDAC frequency than requested. - * - * @param[in] vdac - * Pointer to VDAC peripheral register block. - * - * @param[in] vdacFreq VDAC frequency target. The frequency will automatically - * be adjusted to be below maximum allowed VDAC clock. - * - * @return - * A prescaler value to use for VDAC to achieve a clock value less than - * or equal to @p vdacFreq. - ******************************************************************************/ -uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq) -{ - uint32_t ret = 0; - uint32_t refFreq = 0; - - /* Make sure that the selected VDAC clock is below the maximum value. */ - if (vdacFreq > VDAC_MAX_CLOCK) { - vdacFreq = VDAC_MAX_CLOCK; - } - - if (vdac == VDAC0) { - refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); - } -#if defined(VDAC1) - else if (vdac == VDAC1) { - refFreq = CMU_ClockFreqGet(cmuClock_VDAC1); - } -#endif - else { - EFM_ASSERT(0); - } - - /* Iterate to determine the best prescaler value. Start with the lowest */ - /* prescaler value to get the first equal or less VDAC */ - /* frequency value. */ - for (ret = 0; ret <= (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT); ret++) { - if ((refFreq / (ret + 1)) <= vdacFreq) { - break; - } - } - - /* If ret is higher than the maximum prescaler value, make sure to return - the maximum value. */ - if (ret > (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT)) { - ret = _VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT; - } - - return ret; -} -#endif - -/***************************************************************************//** - * @brief - * Reset VDAC to same state that it was in after a hardwares reset. - * - * @param[in] vdac - * A pointer to the VDAC peripheral register block. - ******************************************************************************/ -void VDAC_Reset(VDAC_TypeDef *vdac) -{ -#if defined(VDAC_SWRST_SWRST) - - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - - /* Wait for all synchronizations to finish and disable the vdac channels */ - if (vdac->EN & VDAC_EN_EN) { - vdac->CMD = _VDAC_CMD_CH0DIS_MASK; - while (vdac->STATUS & VDAC_STATUS_CH0ENS ) { - } - - vdac->CMD = _VDAC_CMD_CH1DIS_MASK; - while (vdac->STATUS & VDAC_STATUS_CH1ENS ) { - } - - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - - vdac->CMD = _VDAC_CMD_CH0FIFOFLUSH_MASK | _VDAC_CMD_CH1FIFOFLUSH_MASK; - while (vdac->STATUS & (VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { - } - - while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { - } - } - - vdac->SWRST_SET = VDAC_SWRST_SWRST; - while (vdac->SWRST & _VDAC_SWRST_RESETTING_MASK) { - } - -#else - /* Disable channels before resetting other registers. */ - vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; - while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { - } - vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; - vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; - vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; - vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; - vdac->CTRL = _VDAC_CTRL_RESETVALUE; - vdac->IEN = _VDAC_IEN_RESETVALUE; - vdac->IFC = _VDAC_IFC_MASK; - vdac->CAL = _VDAC_CAL_RESETVALUE; -#endif -} - -/** @} (end addtogroup vdac) */ -#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Digital to Analog Converter (VDAC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_vdac.h" +#if defined(VDAC_COUNT) && (VDAC_COUNT > 0) +#include "em_cmu.h" + +/***************************************************************************//** + * @addtogroup vdac + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the VDAC channel for assert statements. */ +#define VDAC_CH_VALID(ch) ((ch) <= 1) + +/** A maximum VDAC clock. */ +#define VDAC_MAX_CLOCK 1000000 + +/** The maximum clock frequency of the internal clock oscillator, 10 MHz + 20%. */ +#define VDAC_INTERNAL_CLOCK_FREQ 12000000 + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_VDAC_EN_MASK) +static void VDAC_DisableModule(VDAC_TypeDef* vdac) +{ + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + /* Wait for all synchronizations to finish */ + if (vdac->EN & VDAC_EN_EN) { + vdac->CMD = _VDAC_CMD_CH0DIS_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS)) { + } + + vdac->CMD = _VDAC_CMD_CH1DIS_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH1ENS)) { + } + +#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + vdac->CMD = VDAC_CMD_CH0FIFOFLUSH | VDAC_CMD_CH1FIFOFLUSH; + + while (vdac->STATUS & (VDAC_STATUS_SYNCBUSY | VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { + } +#endif + vdac->EN_CLR = _VDAC_EN_EN_MASK; + while (vdac->EN & _VDAC_EN_DISABLING_MASK) { + } + } +} +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable the VDAC channel. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] ch + * A channel to enable/disable. + * + * @param[in] enable + * True to enable VDAC channel, false to disable. + ******************************************************************************/ +void VDAC_Enable(VDAC_TypeDef *vdac, unsigned int ch, bool enable) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + +#if defined(_VDAC_STATUS_SYNCBUSY_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } +#endif + + if (ch == 0) { + if (enable) { + vdac->CMD = VDAC_CMD_CH0EN; + while ((vdac->STATUS & VDAC_STATUS_CH0ENS) == 0) { + } + } else { + vdac->CMD = VDAC_CMD_CH0DIS; + while (vdac->STATUS & VDAC_STATUS_CH0ENS) { + } +#if defined(_VDAC_CMD_CH0FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + vdac->CMD = VDAC_CMD_CH0FIFOFLUSH; + while (vdac->STATUS & VDAC_STATUS_CH0FIFOFLBUSY) { + } +#endif + } + } else { + if (enable) { + vdac->CMD = VDAC_CMD_CH1EN; + while ((vdac->STATUS & VDAC_STATUS_CH1ENS) == 0) { + } + } else { + vdac->CMD = VDAC_CMD_CH1DIS; + while (vdac->STATUS & VDAC_STATUS_CH1ENS) { + } + +#if defined(_VDAC_CMD_CH1FIFOFLUSH_MASK) + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + vdac->CMD = VDAC_CMD_CH1FIFOFLUSH; + while (vdac->STATUS & VDAC_STATUS_CH1FIFOFLBUSY) { + } +#endif + } + } +} + +/***************************************************************************//** + * @brief + * Initialize VDAC. + * + * @details + * Initializes the common parts for both channels. This function will also load + * calibration values from the Device Information (DI) page into the VDAC + * calibration register. + * To complete a VDAC setup, channel control configuration must also be done. + * See VDAC_InitChannel(). + * + * @note + * This function will disable both channels prior to configuration. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] init + * A pointer to the VDAC initialization structure. + ******************************************************************************/ +void VDAC_Init(VDAC_TypeDef *vdac, const VDAC_Init_TypeDef *init) +{ + EFM_ASSERT(VDAC_REF_VALID(vdac)); + uint32_t config = 0; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + uint32_t cal; + uint32_t const volatile *calData; + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + + /* Get the OFFSETTRIM calibration value. */ + cal = ((DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK) + >> _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT) + << _VDAC_CAL_OFFSETTRIM_SHIFT; + + if (init->mainCalibration) { + calData = &DEVINFO->VDAC0MAINCAL; + } else { + calData = &DEVINFO->VDAC0ALTCAL; + } + + /* Get the correct GAINERRTRIM calibration value. */ + switch (init->reference) { + case vdacRef1V25Ln: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT; + break; + + case vdacRef2V5Ln: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT; + break; + + case vdacRef1V25: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT; + break; + + case vdacRef2V5: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT; + break; + + case vdacRefAvdd: + case vdacRefExtPin: + config = (*calData & _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK) + >> _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT; + break; + } + + /* Set the sGAINERRTRIM calibration value. */ + cal |= config << _VDAC_CAL_GAINERRTRIM_SHIFT; + + /* Get the GAINERRTRIMCH1 calibration value. */ + switch (init->reference) { + case vdacRef1V25Ln: + case vdacRef1V25: + case vdacRefAvdd: + case vdacRefExtPin: + config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT; + break; + + case vdacRef2V5Ln: + case vdacRef2V5: + config = (DEVINFO->VDAC0CH1CAL & _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK) + >> _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT; + break; + } + + /* Set the GAINERRTRIM calibration value. */ + cal |= config << _VDAC_CAL_GAINERRTRIMCH1_SHIFT; + + config = ((uint32_t)init->asyncClockMode << _VDAC_CTRL_DACCLKMODE_SHIFT) + | ((uint32_t)init->warmupKeepOn << _VDAC_CTRL_WARMUPMODE_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CTRL_REFRESHPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CTRL_PRESC_SHIFT) + & _VDAC_CTRL_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CTRL_REFSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CTRL_CH0PRESCRST_SHIFT) + | ((uint32_t)init->outEnablePRS << _VDAC_CTRL_OUTENPRS_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CTRL_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CTRL_DIFF_SHIFT); + + /* Write to VDAC registers. */ + vdac->CAL = cal; + vdac->CTRL = config; +#elif defined(_SILICON_LABS_32B_SERIES_2) + + VDAC_DisableModule(vdac); + + config = ( +#if defined(VDAC_CFG_SINEMODEPRS) + ((uint32_t)init->sineModePrsEnable ? VDAC_CFG_SINEMODEPRS : 0U) | +#endif +#if defined(VDAC_CFG_OUTENPRS) + ((uint32_t)init->prsOutEnable ? VDAC_CFG_OUTENPRS : 0U) | +#endif + (((uint32_t)init->warmupTime << _VDAC_CFG_WARMUPTIME_SHIFT) & _VDAC_CFG_WARMUPTIME_MASK) + | ((uint32_t)init->dbgHalt << _VDAC_CFG_DBGHALT_SHIFT) + | ((uint32_t)init->onDemandClk << _VDAC_CFG_ONDEMANDCLK_SHIFT) + | ((uint32_t)init->dmaWakeUp << _VDAC_CFG_DMAWU_SHIFT) + | ((uint32_t)init->biasKeepWarm << _VDAC_CFG_BIASKEEPWARM_SHIFT) + | ((uint32_t)init->refresh << _VDAC_CFG_REFRESHPERIOD_SHIFT) + | ((uint32_t)init->timerOverflow << _VDAC_CFG_TIMEROVRFLOWPERIOD_SHIFT) + | (((uint32_t)init->prescaler << _VDAC_CFG_PRESC_SHIFT) & _VDAC_CFG_PRESC_MASK) + | ((uint32_t)init->reference << _VDAC_CFG_REFRSEL_SHIFT) + | ((uint32_t)init->ch0ResetPre << _VDAC_CFG_CH0PRESCRST_SHIFT) + | ((uint32_t)init->sineReset << _VDAC_CFG_SINERESET_SHIFT) + | ((uint32_t)init->sineEnable << _VDAC_CFG_SINEMODE_SHIFT) + | ((uint32_t)init->diff << _VDAC_CFG_DIFF_SHIFT)); + + vdac->CFG = config; +#endif +} + +/***************************************************************************//** + * @brief + * Initialize a VDAC channel. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] init + * A pointer to the VDAC channel initialization structure. + * + * @param[in] ch + * A channel number to initialize. + ******************************************************************************/ +void VDAC_InitChannel(VDAC_TypeDef *vdac, + const VDAC_InitChannel_TypeDef *init, + unsigned int ch) +{ + uint32_t channelConfig, vdacStatus; + + EFM_ASSERT(VDAC_REF_VALID(vdac)); + EFM_ASSERT(VDAC_CH_VALID(ch)); + + vdacStatus = vdac->STATUS; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + + /* Make sure both channels are disabled. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + + channelConfig = ((uint32_t)init->prsSel << _VDAC_CH0CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->prsAsync << _VDAC_CH0CTRL_PRSASYNC_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CTRL_TRIGMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CTRL_CONVMODE_SHIFT); + + if (ch == 0) { + vdac->CH0CTRL = channelConfig; + } else { + vdac->CH1CTRL = channelConfig; + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + + VDAC_DisableModule(vdac); + + channelConfig = ((uint32_t)init->warmupKeepOn << _VDAC_CH0CFG_KEEPWARM_SHIFT) + | ((uint32_t)init->highCapLoadEnable << _VDAC_CH0CFG_HIGHCAPLOADEN_SHIFT) + | (((uint32_t)init->fifoLowDataThreshold << _VDAC_CH0CFG_FIFODVL_SHIFT) & _VDAC_CH0CFG_FIFODVL_MASK) + | ((uint32_t)init->chRefreshSource << _VDAC_CH0CFG_REFRESHSOURCE_SHIFT) + | ((uint32_t)init->trigMode << _VDAC_CH0CFG_TRIGMODE_SHIFT) + | ((uint32_t)init->powerMode << _VDAC_CH0CFG_POWERMODE_SHIFT) + | ((uint32_t)init->sampleOffMode << _VDAC_CH0CFG_CONVMODE_SHIFT); + + if (ch == 0) { + vdac->CH0CFG = channelConfig; + + vdac->OUTTIMERCFG = ((uint32_t)(vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK))) + | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH0OUTHOLDTIME_MASK); + + vdac->EN_SET = _VDAC_EN_EN_MASK; + + vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH0_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH0_MASK | _VDAC_OUTCTRL_SHORTCH0_MASK | _VDAC_OUTCTRL_AUXOUTENCH0_MASK | _VDAC_OUTCTRL_MAINOUTENCH0_MASK))) + | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH0_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH0_MASK) + | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH0_SHIFT) + | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH0_SHIFT) + | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH0_SHIFT) + | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH0_SHIFT); + } else if (ch == 1) { + vdac->CH1CFG = channelConfig; + + vdac->OUTTIMERCFG = (vdac->OUTTIMERCFG & ~(_VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK)) + | (((uint32_t)init->holdOutTime << _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_SHIFT) & _VDAC_OUTTIMERCFG_CH1OUTHOLDTIME_MASK); + + vdac->EN_SET = _VDAC_EN_EN_MASK; + + vdac->OUTCTRL = ((uint32_t)(vdac->OUTCTRL & ~(_VDAC_OUTCTRL_ABUSPINSELCH1_MASK | _VDAC_OUTCTRL_ABUSPORTSELCH1_MASK | _VDAC_OUTCTRL_SHORTCH1_MASK | _VDAC_OUTCTRL_AUXOUTENCH1_MASK | _VDAC_OUTCTRL_MAINOUTENCH1_MASK))) + | (((uint32_t)init->pin << _VDAC_OUTCTRL_ABUSPINSELCH1_SHIFT) & _VDAC_OUTCTRL_ABUSPINSELCH1_MASK) + | ((uint32_t)init->port << _VDAC_OUTCTRL_ABUSPORTSELCH1_SHIFT) + | ((uint32_t)init->shortOutput << _VDAC_OUTCTRL_SHORTCH1_SHIFT) + | ((uint32_t)init->auxOutEnable << _VDAC_OUTCTRL_AUXOUTENCH1_SHIFT) + | ((uint32_t)init->mainOutEnable << _VDAC_OUTCTRL_MAINOUTENCH1_SHIFT); + } +#endif + + /* Check if the channel must be enabled. */ + if (init->enable) { + if (ch == 0) { + vdac->CMD = VDAC_CMD_CH0EN; + } else { + vdac->CMD = VDAC_CMD_CH1EN; + } + } + + /* Check if the other channel had to be turned off above + * and needs to be turned on again. */ + if (ch == 0) { + if (vdacStatus & VDAC_STATUS_CH1ENS) { + vdac->CMD = VDAC_CMD_CH1EN; + } + } else { + if (vdacStatus & VDAC_STATUS_CH0ENS) { + vdac->CMD = VDAC_CMD_CH0EN; + } + } +} + +/***************************************************************************//** + * @brief + * Set the output signal of a VDAC channel to a given value. + * + * @details + * This function sets the output signal of a VDAC channel by writing @p value + * to the corresponding CHnDATA register. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + * + * @param[in] channel + * A channel number to set the output of. + * + * @param[in] value + * A value to write to the channel output register CHnDATA. + ******************************************************************************/ +void VDAC_ChannelOutputSet(VDAC_TypeDef *vdac, + unsigned int channel, + uint32_t value) +{ + switch (channel) { + case 0: + VDAC_Channel0OutputSet(vdac, value); + break; + case 1: + VDAC_Channel1OutputSet(vdac, value); + break; + default: + EFM_ASSERT(0); + break; + } +} + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Calculate the prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by the input clock divided by the prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * The maximum VDAC clock is 1 MHz. The input clock is HFPERCLK/HFPERCCLK + * when VDAC synchronous mode is selected, or an internal oscillator of + * 10 MHz +/- 20% when asynchronous mode is selected. + * + * @note + * If the requested VDAC frequency is low and the maximum prescaler value can't + * adjust the actual VDAC frequency lower than requested, the maximum prescaler + * value is returned resulting in a higher VDAC frequency than requested. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below maximum allowed VDAC clock. + * + * @param[in] syncMode Set to true if you intend to use VDAC in synchronous + * mode. + * + * @param[in] hfperFreq Frequency in Hz of HFPERCLK/HFPERCCLK oscillator. + * Set to 0 to use the currently defined HFPERCLK/HFPERCCLK clock setting. + * This parameter is only used when syncMode is set to true. + * + * @return + * A prescaler value to use for VDAC to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(uint32_t vdacFreq, bool syncMode, uint32_t hfperFreq) +{ + uint32_t ret, refFreq; + + /* Make sure that the selected VDAC clock is below the maximum value. */ + if (vdacFreq > VDAC_MAX_CLOCK) { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (!syncMode) { + refFreq = VDAC_INTERNAL_CLOCK_FREQ; + } else { + if (hfperFreq) { + refFreq = hfperFreq; + } else { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); + } + } + + /* Iterate to determine the best prescaler value. Start with the lowest */ + /* prescaler value to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT); ret++) { + if ((refFreq / (ret + 1)) <= vdacFreq) { + break; + } + } + + /* If ret is higher than the maximum prescaler value, make sure to return + the maximum value. */ + if (ret > (_VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT)) { + ret = _VDAC_CTRL_PRESC_MASK >> _VDAC_CTRL_PRESC_SHIFT; + } + + return ret; +} +#else +/***************************************************************************//** + * @brief + * Calculate the prescaler value used to determine VDAC clock. + * + * @details + * The VDAC clock is given by the input clock divided by the prescaler+1. + * + * VDAC_CLK = IN_CLK / (prescale + 1) + * + * The maximum VDAC clock is 1 MHz. + * + * @note + * If the requested VDAC frequency is low and the maximum prescaler value can't + * adjust the actual VDAC frequency lower than requested, the maximum prescaler + * value is returned resulting in a higher VDAC frequency than requested. + * + * @param[in] vdac + * Pointer to VDAC peripheral register block. + * + * @param[in] vdacFreq VDAC frequency target. The frequency will automatically + * be adjusted to be below maximum allowed VDAC clock. + * + * @return + * A prescaler value to use for VDAC to achieve a clock value less than + * or equal to @p vdacFreq. + ******************************************************************************/ +uint32_t VDAC_PrescaleCalc(VDAC_TypeDef *vdac, uint32_t vdacFreq) +{ + uint32_t ret = 0; + uint32_t refFreq = 0; + + /* Make sure that the selected VDAC clock is below the maximum value. */ + if (vdacFreq > VDAC_MAX_CLOCK) { + vdacFreq = VDAC_MAX_CLOCK; + } + + if (vdac == VDAC0) { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC0); + } +#if defined(VDAC1) + else if (vdac == VDAC1) { + refFreq = CMU_ClockFreqGet(cmuClock_VDAC1); + } +#endif + else { + EFM_ASSERT(0); + } + + /* Iterate to determine the best prescaler value. Start with the lowest */ + /* prescaler value to get the first equal or less VDAC */ + /* frequency value. */ + for (ret = 0; ret <= (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT); ret++) { + if ((refFreq / (ret + 1)) <= vdacFreq) { + break; + } + } + + /* If ret is higher than the maximum prescaler value, make sure to return + the maximum value. */ + if (ret > (_VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT)) { + ret = _VDAC_CFG_PRESC_MASK >> _VDAC_CFG_PRESC_SHIFT; + } + + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Reset VDAC to same state that it was in after a hardwares reset. + * + * @param[in] vdac + * A pointer to the VDAC peripheral register block. + ******************************************************************************/ +void VDAC_Reset(VDAC_TypeDef *vdac) +{ +#if defined(VDAC_SWRST_SWRST) + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + /* Wait for all synchronizations to finish and disable the vdac channels */ + if (vdac->EN & VDAC_EN_EN) { + vdac->CMD = _VDAC_CMD_CH0DIS_MASK; + while (vdac->STATUS & VDAC_STATUS_CH0ENS ) { + } + + vdac->CMD = _VDAC_CMD_CH1DIS_MASK; + while (vdac->STATUS & VDAC_STATUS_CH1ENS ) { + } + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + + vdac->CMD = _VDAC_CMD_CH0FIFOFLUSH_MASK | _VDAC_CMD_CH1FIFOFLUSH_MASK; + while (vdac->STATUS & (VDAC_STATUS_CH0FIFOFLBUSY | VDAC_STATUS_CH1FIFOFLBUSY)) { + } + + while (vdac->STATUS & VDAC_STATUS_SYNCBUSY) { + } + } + + vdac->SWRST_SET = VDAC_SWRST_SWRST; + while (vdac->SWRST & _VDAC_SWRST_RESETTING_MASK) { + } + +#else + /* Disable channels before resetting other registers. */ + vdac->CMD = VDAC_CMD_CH0DIS | VDAC_CMD_CH1DIS; + while (vdac->STATUS & (VDAC_STATUS_CH0ENS | VDAC_STATUS_CH1ENS)) { + } + vdac->CH0CTRL = _VDAC_CH0CTRL_RESETVALUE; + vdac->CH1CTRL = _VDAC_CH1CTRL_RESETVALUE; + vdac->CH0DATA = _VDAC_CH0DATA_RESETVALUE; + vdac->CH1DATA = _VDAC_CH1DATA_RESETVALUE; + vdac->CTRL = _VDAC_CTRL_RESETVALUE; + vdac->IEN = _VDAC_IEN_RESETVALUE; + vdac->IFC = _VDAC_IFC_MASK; + vdac->CAL = _VDAC_CAL_RESETVALUE; +#endif +} + +/** @} (end addtogroup vdac) */ +#endif /* defined(VDAC_COUNT) && (VDAC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c index 4fa0346..859b4b7 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c +++ b/locator_host/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c @@ -1,355 +1,355 @@ -/***************************************************************************//** - * @file - * @brief Watchdog (WDOG) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_wdog.h" -#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) - -#include "em_bus.h" -#include "em_core.h" - -/***************************************************************************//** - * @addtogroup wdog WDOG - Watchdog - * @brief Watchdog (WDOG) Peripheral API - * @details - * This module contains functions to control the WDOG peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The WDOG resets the system in case of a fault - * condition. - * @{ - ******************************************************************************/ - -/** In some scenarioes when the watchdog is disabled the synchronization - * register might be set and not be cleared until the watchdog is enabled - * again. This will happen when for instance some watchdog register is modified - * while the watchdog clock is disabled. In these scenarioes we need to make - * sure that the software does not wait forever. */ -#define WDOG_SYNC_TIMEOUT 30000 - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Enable/disable the watchdog timer. - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * A pointer to the WDOG peripheral register block. - * - * @param[in] enable - * True to enable Watchdog, false to disable. Watchdog cannot be disabled if - * it's been locked. - ******************************************************************************/ -void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable) -{ - // SYNCBUSY may stall when locked. -#if defined(_WDOG_STATUS_MASK) - if ((wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED) { - return; - } -#else - if (wdog->CTRL & WDOG_CTRL_LOCK) { - return; - } -#endif - -#if defined(_WDOG_EN_MASK) - if (!enable) { - while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { - } - wdog->EN_CLR = WDOG_EN_EN; -#if defined(_WDOG_EN_DISABLING_MASK) - while (wdog->EN & _WDOG_EN_DISABLING_MASK) { - } -#endif - } else { - wdog->EN_SET = WDOG_EN_EN; - } -#else - // Wait for previous operations/modifications to complete - int i = 0; - while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) - && (i < WDOG_SYNC_TIMEOUT)) { - i++; - } - - bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); - - // Make sure to only write to the CTRL register if we are changing mode - if (wdogState != enable) { - BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); - } -#endif -} - -/***************************************************************************//** - * @brief - * Feed WDOG. - * - * @details - * When WDOG is activated, it must be fed (i.e., clearing the counter) - * before it reaches the defined timeout period. Otherwise, WDOG - * will generate a reset. - * - * @note - * Note that WDOG is an asynchronous peripheral and when calling the - * WDOGn_Feed() function the hardware starts the process of clearing the - * counter. This process takes some time before it completes depending on the - * selected oscillator (up to 4 peripheral clock cycles). When using the - * ULFRCO for instance as the oscillator the watchdog runs on a 1 kHz clock - * and a watchdog clear operation might take up to 4 ms. - * - * If the device enters EM2 or EM3 while a command is in progress then that - * command will be aborted. An application can use @ref WDOGn_SyncWait() - * to wait for a command to complete. - * - * @param[in] wdog - * A pointer to the WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Feed(WDOG_TypeDef *wdog) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - - // WDOG should not be fed while it is disabled. - if (!(wdog->CTRL & WDOG_CTRL_EN)) { - return; - } - - // If a previous clearing is synchronized to the LF domain, there - // is no point in waiting for it to complete before clearing over again. - // This avoids stalling the core in the typical use case where some idle loop - // keeps clearing WDOG. - if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { - return; - } - // Before writing to the WDOG_CMD register, make sure that - // any previous write to the WDOG_CTRL is complete. - while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { - } - - wdog->CMD = WDOG_CMD_CLEAR; - -#else // Series 2 devices - - CORE_DECLARE_IRQ_STATE; - - // WDOG should not be fed while it is disabled. - if ((wdog->EN & WDOG_EN_EN) == 0U) { - return; - } - - // We need an atomic section around the check for sync and the clear command - // because sending a clear command while a previous command is being synchronized - // will cause a BusFault. - CORE_ENTER_ATOMIC(); - if ((wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) == 0U) { - wdog->CMD = WDOG_CMD_CLEAR; - } - CORE_EXIT_ATOMIC(); - -#endif -} - -/***************************************************************************//** - * @brief - * Initialize WDOG (assuming the WDOG configuration has not been - * locked). - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] init - * The structure holding the WDOG configuration. A default setting - * #WDOG_INIT_DEFAULT is available for initialization. - ******************************************************************************/ -void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init) -{ -#if defined(_WDOG_CFG_MASK) - // Handle series-2 devices - - if (wdog->EN != 0U) { - while (wdog->SYNCBUSY != 0U) { - // Wait for any potential synchronization to finish - } - wdog->EN_CLR = WDOG_EN_EN; -#if defined(_WDOG_EN_DISABLING_MASK) - while (wdog->EN & _WDOG_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - } - - wdog->CFG = (init->debugRun ? WDOG_CFG_DEBUGRUN : 0U) - | (init->clrSrc ? WDOG_CFG_CLRSRC : 0U) -#if defined(_WDOG_CFG_EM1RUN_MASK) - | (init->em1Run ? WDOG_CFG_EM1RUN : 0U) -#endif - | (init->em2Run ? WDOG_CFG_EM2RUN : 0U) - | (init->em3Run ? WDOG_CFG_EM3RUN : 0U) - | (init->em4Block ? WDOG_CFG_EM4BLOCK : 0U) - | (init->prs0MissRstEn ? WDOG_CFG_PRS0MISSRSTEN : 0U) - | (init->prs1MissRstEn ? WDOG_CFG_PRS1MISSRSTEN : 0U) - | (init->resetDisable ? WDOG_CFG_WDOGRSTDIS : 0U) - | ((uint32_t)(init->warnSel) << _WDOG_CFG_WARNSEL_SHIFT) - | ((uint32_t)(init->winSel) << _WDOG_CFG_WINSEL_SHIFT) - | ((uint32_t)(init->perSel) << _WDOG_CFG_PERSEL_SHIFT); - - WDOGn_Enable(wdog, init->enable); - - if (init->lock) { - WDOGn_Lock(wdog); - } -#else - // Handle series-0 and series-1 devices - uint32_t setting; - - setting = (init->enable ? WDOG_CTRL_EN : 0U) - | (init->debugRun ? WDOG_CTRL_DEBUGRUN : 0U) -#if defined(_WDOG_CTRL_CLRSRC_MASK) - | (init->clrSrc ? WDOG_CTRL_CLRSRC : 0U) -#endif - | (init->em2Run ? WDOG_CTRL_EM2RUN : 0U) - | (init->em3Run ? WDOG_CTRL_EM3RUN : 0U) - | (init->em4Block ? WDOG_CTRL_EM4BLOCK : 0U) - | (init->swoscBlock ? WDOG_CTRL_SWOSCBLOCK : 0U) - | (init->lock ? WDOG_CTRL_LOCK : 0U) - | ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) - | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT); - -#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) - setting |= (init->resetDisable ? WDOG_CTRL_WDOGRSTDIS : 0U); -#endif -#if defined(_WDOG_CTRL_WARNSEL_MASK) - setting |= ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT); -#endif -#if defined(_WDOG_CTRL_WINSEL_MASK) - setting |= ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT); -#endif - - // Wait for previous operations/modifications to complete - int i = 0; - while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) - && (i < WDOG_SYNC_TIMEOUT)) { - i++; - } - wdog->CTRL = setting; -#endif -} - -/***************************************************************************//** - * @brief - * Lock the WDOG configuration. - * - * @details - * This prevents errors from overwriting the WDOG configuration, possibly - * disabling it. Only a reset can unlock the WDOG configuration once locked. - * - * If the LFRCO or LFXO clocks are used to clock WDOG, - * consider using the option of inhibiting those clocks to be disabled. - * See the WDOG_Enable() initialization structure. - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Lock(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_LOCK_MASK) - wdog->LOCK = _WDOG_LOCK_LOCKKEY_LOCK; -#else - // Wait for any pending previous write operation to have been completed in - // the low-frequency domain. - while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { - } - - // Disable writing to the control register. - BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); -#endif -} - -/***************************************************************************//** - * @brief - * Wait for the WDOG to complete all synchronization of register changes - * and commands. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_SyncWait(WDOG_TypeDef *wdog) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((wdog->EN != 0U) && (wdog->SYNCBUSY != 0U)) { - // Wait for synchronization to finish - } -#else - while (wdog->SYNCBUSY != 0U) { - // Wait for synchronization to finish - } -#endif -} - -/***************************************************************************//** - * @brief - * Unlock the WDOG configuration. - * - * @details - * Note that this function will have no effect on devices where a reset is - * the only way to unlock the watchdog. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Unlock(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_LOCK_MASK) - wdog->LOCK = _WDOG_LOCK_LOCKKEY_UNLOCK; -#else - (void) wdog; -#endif -} - -/** @} (end addtogroup wdog) */ -#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_wdog.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include "em_bus.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup wdog WDOG - Watchdog + * @brief Watchdog (WDOG) Peripheral API + * @details + * This module contains functions to control the WDOG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The WDOG resets the system in case of a fault + * condition. + * @{ + ******************************************************************************/ + +/** In some scenarioes when the watchdog is disabled the synchronization + * register might be set and not be cleared until the watchdog is enabled + * again. This will happen when for instance some watchdog register is modified + * while the watchdog clock is disabled. In these scenarioes we need to make + * sure that the software does not wait forever. */ +#define WDOG_SYNC_TIMEOUT 30000 + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable the watchdog timer. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + * + * @param[in] enable + * True to enable Watchdog, false to disable. Watchdog cannot be disabled if + * it's been locked. + ******************************************************************************/ +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable) +{ + // SYNCBUSY may stall when locked. +#if defined(_WDOG_STATUS_MASK) + if ((wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED) { + return; + } +#else + if (wdog->CTRL & WDOG_CTRL_LOCK) { + return; + } +#endif + +#if defined(_WDOG_EN_MASK) + if (!enable) { + while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + } +#endif + } else { + wdog->EN_SET = WDOG_EN_EN; + } +#else + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + + bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); + + // Make sure to only write to the CTRL register if we are changing mode + if (wdogState != enable) { + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); + } +#endif +} + +/***************************************************************************//** + * @brief + * Feed WDOG. + * + * @details + * When WDOG is activated, it must be fed (i.e., clearing the counter) + * before it reaches the defined timeout period. Otherwise, WDOG + * will generate a reset. + * + * @note + * Note that WDOG is an asynchronous peripheral and when calling the + * WDOGn_Feed() function the hardware starts the process of clearing the + * counter. This process takes some time before it completes depending on the + * selected oscillator (up to 4 peripheral clock cycles). When using the + * ULFRCO for instance as the oscillator the watchdog runs on a 1 kHz clock + * and a watchdog clear operation might take up to 4 ms. + * + * If the device enters EM2 or EM3 while a command is in progress then that + * command will be aborted. An application can use @ref WDOGn_SyncWait() + * to wait for a command to complete. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Feed(WDOG_TypeDef *wdog) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + + // WDOG should not be fed while it is disabled. + if (!(wdog->CTRL & WDOG_CTRL_EN)) { + return; + } + + // If a previous clearing is synchronized to the LF domain, there + // is no point in waiting for it to complete before clearing over again. + // This avoids stalling the core in the typical use case where some idle loop + // keeps clearing WDOG. + if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + return; + } + // Before writing to the WDOG_CMD register, make sure that + // any previous write to the WDOG_CTRL is complete. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + wdog->CMD = WDOG_CMD_CLEAR; + +#else // Series 2 devices + + CORE_DECLARE_IRQ_STATE; + + // WDOG should not be fed while it is disabled. + if ((wdog->EN & WDOG_EN_EN) == 0U) { + return; + } + + // We need an atomic section around the check for sync and the clear command + // because sending a clear command while a previous command is being synchronized + // will cause a BusFault. + CORE_ENTER_ATOMIC(); + if ((wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) == 0U) { + wdog->CMD = WDOG_CMD_CLEAR; + } + CORE_EXIT_ATOMIC(); + +#endif +} + +/***************************************************************************//** + * @brief + * Initialize WDOG (assuming the WDOG configuration has not been + * locked). + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] init + * The structure holding the WDOG configuration. A default setting + * #WDOG_INIT_DEFAULT is available for initialization. + ******************************************************************************/ +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init) +{ +#if defined(_WDOG_CFG_MASK) + // Handle series-2 devices + + if (wdog->EN != 0U) { + while (wdog->SYNCBUSY != 0U) { + // Wait for any potential synchronization to finish + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } + + wdog->CFG = (init->debugRun ? WDOG_CFG_DEBUGRUN : 0U) + | (init->clrSrc ? WDOG_CFG_CLRSRC : 0U) +#if defined(_WDOG_CFG_EM1RUN_MASK) + | (init->em1Run ? WDOG_CFG_EM1RUN : 0U) +#endif + | (init->em2Run ? WDOG_CFG_EM2RUN : 0U) + | (init->em3Run ? WDOG_CFG_EM3RUN : 0U) + | (init->em4Block ? WDOG_CFG_EM4BLOCK : 0U) + | (init->prs0MissRstEn ? WDOG_CFG_PRS0MISSRSTEN : 0U) + | (init->prs1MissRstEn ? WDOG_CFG_PRS1MISSRSTEN : 0U) + | (init->resetDisable ? WDOG_CFG_WDOGRSTDIS : 0U) + | ((uint32_t)(init->warnSel) << _WDOG_CFG_WARNSEL_SHIFT) + | ((uint32_t)(init->winSel) << _WDOG_CFG_WINSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CFG_PERSEL_SHIFT); + + WDOGn_Enable(wdog, init->enable); + + if (init->lock) { + WDOGn_Lock(wdog); + } +#else + // Handle series-0 and series-1 devices + uint32_t setting; + + setting = (init->enable ? WDOG_CTRL_EN : 0U) + | (init->debugRun ? WDOG_CTRL_DEBUGRUN : 0U) +#if defined(_WDOG_CTRL_CLRSRC_MASK) + | (init->clrSrc ? WDOG_CTRL_CLRSRC : 0U) +#endif + | (init->em2Run ? WDOG_CTRL_EM2RUN : 0U) + | (init->em3Run ? WDOG_CTRL_EM3RUN : 0U) + | (init->em4Block ? WDOG_CTRL_EM4BLOCK : 0U) + | (init->swoscBlock ? WDOG_CTRL_SWOSCBLOCK : 0U) + | (init->lock ? WDOG_CTRL_LOCK : 0U) + | ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT); + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) + setting |= (init->resetDisable ? WDOG_CTRL_WDOGRSTDIS : 0U); +#endif +#if defined(_WDOG_CTRL_WARNSEL_MASK) + setting |= ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT); +#endif +#if defined(_WDOG_CTRL_WINSEL_MASK) + setting |= ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT); +#endif + + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + wdog->CTRL = setting; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the WDOG configuration. + * + * @details + * This prevents errors from overwriting the WDOG configuration, possibly + * disabling it. Only a reset can unlock the WDOG configuration once locked. + * + * If the LFRCO or LFXO clocks are used to clock WDOG, + * consider using the option of inhibiting those clocks to be disabled. + * See the WDOG_Enable() initialization structure. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Lock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_LOCK; +#else + // Wait for any pending previous write operation to have been completed in + // the low-frequency domain. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + // Disable writing to the control register. + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the WDOG to complete all synchronization of register changes + * and commands. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_SyncWait(WDOG_TypeDef *wdog) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((wdog->EN != 0U) && (wdog->SYNCBUSY != 0U)) { + // Wait for synchronization to finish + } +#else + while (wdog->SYNCBUSY != 0U) { + // Wait for synchronization to finish + } +#endif +} + +/***************************************************************************//** + * @brief + * Unlock the WDOG configuration. + * + * @details + * Note that this function will have no effect on devices where a reset is + * the only way to unlock the watchdog. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Unlock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_UNLOCK; +#else + (void) wdog; +#endif +} + +/** @} (end addtogroup wdog) */ +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc.h b/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc.h index a433aa5..62d6523 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc.h @@ -1,434 +1,434 @@ -/***************************************************************************//** - * @file - * @brief System Real Time Counter (SYSRTC) peripheral API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef PERIPHERAL_SYSRTC_H -#define PERIPHERAL_SYSRTC_H - -#include "em_device.h" - -#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "peripheral_sysrtc_compat.h" -#include "sl_enum.h" - -/***************************************************************************//** - * @addtogroup sysrtc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/// Minimum compare channels for SYSRTC group. -#define SYSRTC_GROUP_MIN_CHANNEL_COMPARE 1u -/// Maximum compare channels for SYSRTC group. -#define SYSRTC_GROUP_MAX_CHANNEL_COMPARE 2u - -/// Minimum capture channels for SYSRTC group. -#define SYSRTC_GROUP_MIN_CHANNEL_CAPTURE 0u -/// Maximum capture channels for SYSRTC group. -#define SYSRTC_GROUP_MAX_CHANNEL_CAPTURE 1u - -/// Sysrtc group number. -#if !defined(SYSRTC_GROUP_NUMBER) -#define SYSRTC_GROUP_NUMBER 1u -#endif - -/// Validation of valid SYSRTC group for assert statements. -#define SYSRTC_GROUP_VALID(group) ((unsigned)(group) < SYSRTC_GROUP_NUMBER) - -/******************************************************************************* - ********************************* ENUM ************************************ - ******************************************************************************/ - -/// Capture input edge select. -SL_ENUM(sl_hal_sysrtc_capture_edge_t) { - SL_HAL_SYSRTC_CAPTURE_EDGE_RISING = 0, ///< Rising edges detected. - SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING, ///< Falling edges detected. - SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH ///< Both edges detected. -}; - -/// Compare match output action mode. -SL_ENUM(sl_hal_sysrtc_compare_match_out_action_t) { - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR = 0, ///< Clear output. - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET, ///< Set output. - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE, ///< Generate a pulse. - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE, ///< Toggle output. - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF ///< Export CMPIF. -}; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/// SYSRTC configuration structure. -typedef struct { - bool enable_debug_run; ///< Counter shall keep running during debug halt. -} sl_hal_sysrtc_config_t; - -/// Suggested default values for SYSRTC configuration structure. -#define SYSRTC_CONFIG_DEFAULT \ - { \ - false, /* Disable updating during debug halt. */ \ - } - -/// Compare channel configuration structure. -typedef struct { - sl_hal_sysrtc_compare_match_out_action_t compare_match_out_action; ///< Compare mode channel match output action. -} sl_hal_sysrtc_group_channel_compare_config_t; - -/// Capture channel configuration structure. -typedef struct { - sl_hal_sysrtc_capture_edge_t capture_input_edge; ///< Capture mode channel input edge. -} sl_hal_sysrtc_group_channel_capture_config_t; - -/// Group configuration structure. -typedef struct { - bool compare_channel0_enable; ///< Enable/Disable compare channel 0 - bool compare_channel1_enable; ///< Enable/Disable compare channel 1 - bool capture_channel0_enable; ///< Enable/Disable capture channel 0 - sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel0_config; ///< Pointer to compare channel 0 config - sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel1_config; ///< Pointer to compare channel 1 config - sl_hal_sysrtc_group_channel_capture_config_t const *p_capture_channel0_config; ///< Pointer to capture channel 0 config -} sl_hal_sysrtc_group_config_t; - -/// Suggested default values for compare channel configuration structure. -#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_DEFAULT \ - { \ - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE \ - } - -/// Compare channel configuration for starting HFXO using PRS. -#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_EARLY_WAKEUP \ - { \ - SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF \ - } - -/// Suggested default values for capture channel configuration structure. -#define SYSRTC_GROUP_CHANNEL_CAPTURE_CONFIG_DEFAULT \ - { \ - SL_HAL_SYSRTC_CAPTURE_EDGE_RISING \ - } - -/// Suggested default values for SYSRTC group configuration structure. -#define SYSRTC_GROUP_CONFIG_DEFAULT \ - { \ - true, /* Enable compare channel 0. */ \ - false, /* Disable compare channel 1. */ \ - false, /* Disable capture channel 0. */ \ - NULL, /* NULL Pointer to configuration structure for compare channel 0*/ \ - NULL, /* NULL Pointer to configuration structure for compare channel 1*/ \ - NULL /* NULL Pointer to configuration structure for capture channel 0*/ \ - } - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * Initializes SYSRTC module. - * - * Note that the compare values must be set separately with - * (sl_hal_sysrtc_set_group_compare_channel_value()), which should probably be - * done prior to the use of this function if configuring the SYSRTC to start - * when initialization is completed. - * - * @param[in] p_config A pointer to the SYSRTC initialization structure - * variable. - ******************************************************************************/ -void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config); - -/***************************************************************************//** - * Enables SYSRTC counting. - ******************************************************************************/ -void sl_hal_sysrtc_enable(void); - -/***************************************************************************//** - * Disables SYSRTC counting. - ******************************************************************************/ -void sl_hal_sysrtc_disable(void); - -/***************************************************************************//** - * Waits for the SYSRTC to complete all synchronization of register changes - * and commands. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_wait_sync(void) -{ - while ((SYSRTC0->EN & SYSRTC_EN_EN) && (SYSRTC0->SYNCBUSY != 0U)) { - // Wait for all synchronizations to finish - } -} - -/***************************************************************************//** - * Waits for the SYSRTC to complete reseting or disabling procedure. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_wait_ready(void) -{ - while ((SYSRTC0->SWRST & _SYSRTC_SWRST_RESETTING_MASK) || (SYSRTC0->EN & _SYSRTC_EN_DISABLING_MASK) || (SYSRTC0->SYNCBUSY != 0U)) { - // Wait for all synchronizations to finish - } -} - -/***************************************************************************//** - * Starts SYSRTC counter. - * - * This function will send a start command to the SYSRTC peripheral. The SYSRTC - * peripheral will use some LF clock ticks before the command is executed. - * The sl_hal_sysrtc_wait_sync() function can be used to wait for the start - * command to be executed. - * - * @note This function requires the SYSRTC to be enabled. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_start(void) -{ - sl_hal_sysrtc_wait_sync(); - SYSRTC0->CMD = SYSRTC_CMD_START; -} - -/***************************************************************************//** - * Stops the SYSRTC counter. - * - * This function will send a stop command to the SYSRTC peripheral. The SYSRTC - * peripheral will use some LF clock ticks before the command is executed. - * The sl_hal_sysrtc_wait_sync() function can be used to wait for the stop - * command to be executed. - * - * @note This function requires the SYSRTC to be enabled. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_stop(void) -{ - sl_hal_sysrtc_wait_sync(); - SYSRTC0->CMD = SYSRTC_CMD_STOP; -} - -/***************************************************************************//** - * Restores SYSRTC to its reset state. - ******************************************************************************/ -void sl_hal_sysrtc_reset(void); - -/***************************************************************************//** - * Gets SYSRTC STATUS register value. - * - * @return Current STATUS register value. - ******************************************************************************/ -__INLINE uint32_t sl_hal_sysrtc_get_status(void) -{ - return SYSRTC0->STATUS; -} - -/***************************************************************************//** - * Locks SYSRTC registers. - * - * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, - * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written - * to. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_lock(void) -{ - SYSRTC0->LOCK = ~SYSRTC_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * Unlocks SYSRTC registers. - * - * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, - * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written - * to. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_unlock(void) -{ - SYSRTC0->LOCK = SYSRTC_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * Gets SYSRTC counter value. - * - * @return Current SYSRTC counter value. - ******************************************************************************/ -__INLINE uint32_t sl_hal_sysrtc_get_counter(void) -{ - // Wait for Counter to synchronize before getting value - sl_hal_sysrtc_wait_sync(); - - return SYSRTC0->CNT; -} - -/***************************************************************************//** - * Sets the SYSRTC counter value. - * - * @param[in] value The new SYSRTC counter value. - ******************************************************************************/ -__INLINE void sl_hal_sysrtc_set_counter(uint32_t value) -{ - // Wait for Counter to synchronize before getting value - sl_hal_sysrtc_wait_sync(); - - SYSRTC0->CNT = value; -} - -/***************************************************************************//** - * Initializes the selected SYSRTC group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] p_group_config Pointer to group configuration structure - * variable. - ******************************************************************************/ -void sl_hal_sysrtc_init_group(uint8_t group_number, - sl_hal_sysrtc_group_config_t const *p_group_config); - -/***************************************************************************//** - * Enables one or more SYSRTC interrupts for the given group. - * - * @note Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * sl_hal_sysrtc_clear_group_interrupts() prior to enabling the interrupt. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] flags SYSRTC interrupt sources to enable. - * Use a set of interrupt flags OR-ed together to set - * multiple interrupt sources for the given SYSRTC group. - ******************************************************************************/ -void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, - uint32_t flags); - -/***************************************************************************//** - * Disables one or more SYSRTC interrupts for the given group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] flags SYSRTC interrupt sources to disable. - * Use a set of interrupt flags OR-ed together to disable - * multiple interrupt sources for the given SYSRTC group. - ******************************************************************************/ -void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, - uint32_t flags); - -/***************************************************************************//** - * Clears one or more pending SYSRTC interrupts for the given group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] flags SYSRTC interrupt sources to clear. - * Use a set of interrupt flags OR-ed together to clear - * multiple interrupt sources for the given SYSRTC group. - ******************************************************************************/ -void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, - uint32_t flags); - -/***************************************************************************//** - * Gets pending SYSRTC interrupt flags for the given group. - * - * @note Event bits are not cleared by using this function. - * - * @param[in] group_number SYSRTC group number to use. - * - * @return Pending SYSRTC interrupt sources. - * Returns a set of interrupt flags OR-ed together for multiple - * interrupt sources in the SYSRTC group. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number); - -/***************************************************************************//** - * Gets enabled and pending SYSRTC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note Interrupt flags are not cleared by using this function. - * - * @param[in] group_number SYSRTC group number to use. - * - * @return Pending and enabled SYSRTC interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in SYSRTC_GRPx_IEN and - * - the pending interrupt flags SYSRTC_GRPx_IF. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number); - -/***************************************************************************//** - * Sets one or more pending SYSRTC interrupts for the given group from Software. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] flags SYSRTC interrupt sources to set to pending. - * Use a set of interrupt flags OR-ed together to set - * multiple interrupt sources for the SYSRTC group. - ******************************************************************************/ -void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, - uint32_t flags); - -/***************************************************************************//** - * Gets SYSRTC compare register value for selected channel of given group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] channel Channel selector. - * - * @return Compare register value. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, - uint8_t channel); - -/***************************************************************************//** - * Sets SYSRTC compare register value for selected channel of given group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @param[in] channel Channel selector. - * - * @param[in] value Compare register value. - ******************************************************************************/ -void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, - uint8_t channel, - uint32_t value); - -/***************************************************************************//** - * Gets SYSRTC input capture register value for capture channel of given group. - * - * @param[in] group_number SYSRTC group number to use. - * - * @return Capture register value. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number); - -/** @} (end addtogroup sysrtc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ -#endif /* PERIPHERAL_SYSRTC_H */ +/***************************************************************************//** + * @file + * @brief System Real Time Counter (SYSRTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PERIPHERAL_SYSRTC_H +#define PERIPHERAL_SYSRTC_H + +#include "em_device.h" + +#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "peripheral_sysrtc_compat.h" +#include "sl_enum.h" + +/***************************************************************************//** + * @addtogroup sysrtc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/// Minimum compare channels for SYSRTC group. +#define SYSRTC_GROUP_MIN_CHANNEL_COMPARE 1u +/// Maximum compare channels for SYSRTC group. +#define SYSRTC_GROUP_MAX_CHANNEL_COMPARE 2u + +/// Minimum capture channels for SYSRTC group. +#define SYSRTC_GROUP_MIN_CHANNEL_CAPTURE 0u +/// Maximum capture channels for SYSRTC group. +#define SYSRTC_GROUP_MAX_CHANNEL_CAPTURE 1u + +/// Sysrtc group number. +#if !defined(SYSRTC_GROUP_NUMBER) +#define SYSRTC_GROUP_NUMBER 1u +#endif + +/// Validation of valid SYSRTC group for assert statements. +#define SYSRTC_GROUP_VALID(group) ((unsigned)(group) < SYSRTC_GROUP_NUMBER) + +/******************************************************************************* + ********************************* ENUM ************************************ + ******************************************************************************/ + +/// Capture input edge select. +SL_ENUM(sl_hal_sysrtc_capture_edge_t) { + SL_HAL_SYSRTC_CAPTURE_EDGE_RISING = 0, ///< Rising edges detected. + SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING, ///< Falling edges detected. + SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH ///< Both edges detected. +}; + +/// Compare match output action mode. +SL_ENUM(sl_hal_sysrtc_compare_match_out_action_t) { + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR = 0, ///< Clear output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET, ///< Set output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE, ///< Generate a pulse. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE, ///< Toggle output. + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF ///< Export CMPIF. +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/// SYSRTC configuration structure. +typedef struct { + bool enable_debug_run; ///< Counter shall keep running during debug halt. +} sl_hal_sysrtc_config_t; + +/// Suggested default values for SYSRTC configuration structure. +#define SYSRTC_CONFIG_DEFAULT \ + { \ + false, /* Disable updating during debug halt. */ \ + } + +/// Compare channel configuration structure. +typedef struct { + sl_hal_sysrtc_compare_match_out_action_t compare_match_out_action; ///< Compare mode channel match output action. +} sl_hal_sysrtc_group_channel_compare_config_t; + +/// Capture channel configuration structure. +typedef struct { + sl_hal_sysrtc_capture_edge_t capture_input_edge; ///< Capture mode channel input edge. +} sl_hal_sysrtc_group_channel_capture_config_t; + +/// Group configuration structure. +typedef struct { + bool compare_channel0_enable; ///< Enable/Disable compare channel 0 + bool compare_channel1_enable; ///< Enable/Disable compare channel 1 + bool capture_channel0_enable; ///< Enable/Disable capture channel 0 + sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel0_config; ///< Pointer to compare channel 0 config + sl_hal_sysrtc_group_channel_compare_config_t const *p_compare_channel1_config; ///< Pointer to compare channel 1 config + sl_hal_sysrtc_group_channel_capture_config_t const *p_capture_channel0_config; ///< Pointer to capture channel 0 config +} sl_hal_sysrtc_group_config_t; + +/// Suggested default values for compare channel configuration structure. +#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_DEFAULT \ + { \ + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE \ + } + +/// Compare channel configuration for starting HFXO using PRS. +#define SYSRTC_GROUP_CHANNEL_COMPARE_CONFIG_EARLY_WAKEUP \ + { \ + SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF \ + } + +/// Suggested default values for capture channel configuration structure. +#define SYSRTC_GROUP_CHANNEL_CAPTURE_CONFIG_DEFAULT \ + { \ + SL_HAL_SYSRTC_CAPTURE_EDGE_RISING \ + } + +/// Suggested default values for SYSRTC group configuration structure. +#define SYSRTC_GROUP_CONFIG_DEFAULT \ + { \ + true, /* Enable compare channel 0. */ \ + false, /* Disable compare channel 1. */ \ + false, /* Disable capture channel 0. */ \ + NULL, /* NULL Pointer to configuration structure for compare channel 0*/ \ + NULL, /* NULL Pointer to configuration structure for compare channel 1*/ \ + NULL /* NULL Pointer to configuration structure for capture channel 0*/ \ + } + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initializes SYSRTC module. + * + * Note that the compare values must be set separately with + * (sl_hal_sysrtc_set_group_compare_channel_value()), which should probably be + * done prior to the use of this function if configuring the SYSRTC to start + * when initialization is completed. + * + * @param[in] p_config A pointer to the SYSRTC initialization structure + * variable. + ******************************************************************************/ +void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config); + +/***************************************************************************//** + * Enables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_enable(void); + +/***************************************************************************//** + * Disables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_disable(void); + +/***************************************************************************//** + * Waits for the SYSRTC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_wait_sync(void) +{ + while ((SYSRTC0->EN & SYSRTC_EN_EN) && (SYSRTC0->SYNCBUSY != 0U)) { + // Wait for all synchronizations to finish + } +} + +/***************************************************************************//** + * Waits for the SYSRTC to complete reseting or disabling procedure. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_wait_ready(void) +{ + while ((SYSRTC0->SWRST & _SYSRTC_SWRST_RESETTING_MASK) || (SYSRTC0->EN & _SYSRTC_EN_DISABLING_MASK) || (SYSRTC0->SYNCBUSY != 0U)) { + // Wait for all synchronizations to finish + } +} + +/***************************************************************************//** + * Starts SYSRTC counter. + * + * This function will send a start command to the SYSRTC peripheral. The SYSRTC + * peripheral will use some LF clock ticks before the command is executed. + * The sl_hal_sysrtc_wait_sync() function can be used to wait for the start + * command to be executed. + * + * @note This function requires the SYSRTC to be enabled. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_start(void) +{ + sl_hal_sysrtc_wait_sync(); + SYSRTC0->CMD = SYSRTC_CMD_START; +} + +/***************************************************************************//** + * Stops the SYSRTC counter. + * + * This function will send a stop command to the SYSRTC peripheral. The SYSRTC + * peripheral will use some LF clock ticks before the command is executed. + * The sl_hal_sysrtc_wait_sync() function can be used to wait for the stop + * command to be executed. + * + * @note This function requires the SYSRTC to be enabled. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_stop(void) +{ + sl_hal_sysrtc_wait_sync(); + SYSRTC0->CMD = SYSRTC_CMD_STOP; +} + +/***************************************************************************//** + * Restores SYSRTC to its reset state. + ******************************************************************************/ +void sl_hal_sysrtc_reset(void); + +/***************************************************************************//** + * Gets SYSRTC STATUS register value. + * + * @return Current STATUS register value. + ******************************************************************************/ +__INLINE uint32_t sl_hal_sysrtc_get_status(void) +{ + return SYSRTC0->STATUS; +} + +/***************************************************************************//** + * Locks SYSRTC registers. + * + * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, + * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written + * to. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_lock(void) +{ + SYSRTC0->LOCK = ~SYSRTC_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Unlocks SYSRTC registers. + * + * @note When SYSRTC registers are locked SYSRTC_EN, SYSRTC_CFG, SYSRTC_CMD, + * SYSRTC_SWRST, SYSRTC_CNT and SYSRTC_TOPCNT registers cannot be written + * to. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_unlock(void) +{ + SYSRTC0->LOCK = SYSRTC_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * Gets SYSRTC counter value. + * + * @return Current SYSRTC counter value. + ******************************************************************************/ +__INLINE uint32_t sl_hal_sysrtc_get_counter(void) +{ + // Wait for Counter to synchronize before getting value + sl_hal_sysrtc_wait_sync(); + + return SYSRTC0->CNT; +} + +/***************************************************************************//** + * Sets the SYSRTC counter value. + * + * @param[in] value The new SYSRTC counter value. + ******************************************************************************/ +__INLINE void sl_hal_sysrtc_set_counter(uint32_t value) +{ + // Wait for Counter to synchronize before getting value + sl_hal_sysrtc_wait_sync(); + + SYSRTC0->CNT = value; +} + +/***************************************************************************//** + * Initializes the selected SYSRTC group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] p_group_config Pointer to group configuration structure + * variable. + ******************************************************************************/ +void sl_hal_sysrtc_init_group(uint8_t group_number, + sl_hal_sysrtc_group_config_t const *p_group_config); + +/***************************************************************************//** + * Enables one or more SYSRTC interrupts for the given group. + * + * @note Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * sl_hal_sysrtc_clear_group_interrupts() prior to enabling the interrupt. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to enable. + * Use a set of interrupt flags OR-ed together to set + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Disables one or more SYSRTC interrupts for the given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to disable. + * Use a set of interrupt flags OR-ed together to disable + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Clears one or more pending SYSRTC interrupts for the given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to clear. + * Use a set of interrupt flags OR-ed together to clear + * multiple interrupt sources for the given SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Gets pending SYSRTC interrupt flags for the given group. + * + * @note Event bits are not cleared by using this function. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Pending SYSRTC interrupt sources. + * Returns a set of interrupt flags OR-ed together for multiple + * interrupt sources in the SYSRTC group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number); + +/***************************************************************************//** + * Gets enabled and pending SYSRTC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note Interrupt flags are not cleared by using this function. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Pending and enabled SYSRTC interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in SYSRTC_GRPx_IEN and + * - the pending interrupt flags SYSRTC_GRPx_IF. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number); + +/***************************************************************************//** + * Sets one or more pending SYSRTC interrupts for the given group from Software. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] flags SYSRTC interrupt sources to set to pending. + * Use a set of interrupt flags OR-ed together to set + * multiple interrupt sources for the SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, + uint32_t flags); + +/***************************************************************************//** + * Gets SYSRTC compare register value for selected channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] channel Channel selector. + * + * @return Compare register value. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, + uint8_t channel); + +/***************************************************************************//** + * Sets SYSRTC compare register value for selected channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @param[in] channel Channel selector. + * + * @param[in] value Compare register value. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, + uint8_t channel, + uint32_t value); + +/***************************************************************************//** + * Gets SYSRTC input capture register value for capture channel of given group. + * + * @param[in] group_number SYSRTC group number to use. + * + * @return Capture register value. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number); + +/** @} (end addtogroup sysrtc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ +#endif /* PERIPHERAL_SYSRTC_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc_compat.h b/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc_compat.h index addde9c..ff404dc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc_compat.h +++ b/locator_host/gecko_sdk_4.4.1/platform/peripheral/inc/peripheral_sysrtc_compat.h @@ -1,89 +1,89 @@ -/***************************************************************************//** - * @file - * @brief SYSRTC Compatibility Layer. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef PERIPHERAL_SYSRTC_COMPAT_H -#define PERIPHERAL_SYSRTC_COMPAT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -// Enum. -#define SL_SYSRTC_CAPTURE_EDGE_RISING SL_HAL_SYSRTC_CAPTURE_EDGE_RISING -#define SL_SYSRTC_CAPTURE_EDGE_FALLING SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING -#define SL_SYSRTC_CAPTURE_EDGE_BOTH SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH -#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR -#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET -#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE -#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE -#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF -#define sl_sysrtc_capture_edge_t sl_hal_sysrtc_capture_edge_t -#define sl_sysrtc_compare_match_out_action_t sl_hal_sysrtc_compare_match_out_action_t - -// Structure. -#define sl_sysrtc_config_t sl_hal_sysrtc_config_t -#define sl_sysrtc_group_channel_compare_config_t sl_hal_sysrtc_group_channel_compare_config_t -#define sl_sysrtc_group_channel_capture_config_t sl_hal_sysrtc_group_channel_capture_config_t -#define sl_sysrtc_group_config_t sl_hal_sysrtc_group_config_t - -// Function. -#define sl_sysrtc_init sl_hal_sysrtc_init -#define sl_sysrtc_enable sl_hal_sysrtc_enable -#define sl_sysrtc_disable sl_hal_sysrtc_disable -#define sl_sysrtc_wait_sync sl_hal_sysrtc_wait_sync -#define sl_sysrtc_wait_ready sl_hal_sysrtc_wait_ready -#define sl_sysrtc_start sl_hal_sysrtc_start -#define sl_sysrtc_stop sl_hal_sysrtc_stop -#define sl_sysrtc_reset sl_hal_sysrtc_reset -#define sl_sysrtc_get_status sl_hal_sysrtc_get_status -#define sl_sysrtc_lock sl_hal_sysrtc_lock -#define sl_sysrtc_unlock sl_hal_sysrtc_unlock -#define sl_sysrtc_get_counter sl_hal_sysrtc_get_counter -#define sl_sysrtc_set_counter sl_hal_sysrtc_set_counter -#define sl_sysrtc_init_group sl_hal_sysrtc_init_group -#define sl_sysrtc_enable_group_interrupts sl_hal_sysrtc_enable_group_interrupts -#define sl_sysrtc_disable_group_interrupts sl_hal_sysrtc_disable_group_interrupts -#define sl_sysrtc_clear_group_interrupts sl_hal_sysrtc_clear_group_interrupts -#define sl_sysrtc_get_group_interrupts sl_hal_sysrtc_get_group_interrupts -#define sl_sysrtc_get_group_enabled_interrupts sl_hal_sysrtc_get_group_enabled_interrupts -#define sl_sysrtc_set_group_interrupts sl_hal_sysrtc_set_group_interrupts -#define sl_sysrtc_get_group_compare_channel_value sl_hal_sysrtc_get_group_compare_channel_value -#define sl_sysrtc_set_group_compare_channel_value sl_hal_sysrtc_set_group_compare_channel_value -#define sl_sysrtc_get_group_capture_channel_value sl_hal_sysrtc_get_group_capture_channel_value - -#ifdef __cplusplus -} -#endif - -#endif // PERIPHERAL_SYSRTC_COMPAT_H +/***************************************************************************//** + * @file + * @brief SYSRTC Compatibility Layer. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PERIPHERAL_SYSRTC_COMPAT_H +#define PERIPHERAL_SYSRTC_COMPAT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Enum. +#define SL_SYSRTC_CAPTURE_EDGE_RISING SL_HAL_SYSRTC_CAPTURE_EDGE_RISING +#define SL_SYSRTC_CAPTURE_EDGE_FALLING SL_HAL_SYSRTC_CAPTURE_EDGE_FALLING +#define SL_SYSRTC_CAPTURE_EDGE_BOTH SL_HAL_SYSRTC_CAPTURE_EDGE_BOTH +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CLEAR +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_SET +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_PULSE +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_TOGGLE +#define SL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF SL_HAL_SYSRTC_COMPARE_MATCH_OUT_ACTION_CMPIF +#define sl_sysrtc_capture_edge_t sl_hal_sysrtc_capture_edge_t +#define sl_sysrtc_compare_match_out_action_t sl_hal_sysrtc_compare_match_out_action_t + +// Structure. +#define sl_sysrtc_config_t sl_hal_sysrtc_config_t +#define sl_sysrtc_group_channel_compare_config_t sl_hal_sysrtc_group_channel_compare_config_t +#define sl_sysrtc_group_channel_capture_config_t sl_hal_sysrtc_group_channel_capture_config_t +#define sl_sysrtc_group_config_t sl_hal_sysrtc_group_config_t + +// Function. +#define sl_sysrtc_init sl_hal_sysrtc_init +#define sl_sysrtc_enable sl_hal_sysrtc_enable +#define sl_sysrtc_disable sl_hal_sysrtc_disable +#define sl_sysrtc_wait_sync sl_hal_sysrtc_wait_sync +#define sl_sysrtc_wait_ready sl_hal_sysrtc_wait_ready +#define sl_sysrtc_start sl_hal_sysrtc_start +#define sl_sysrtc_stop sl_hal_sysrtc_stop +#define sl_sysrtc_reset sl_hal_sysrtc_reset +#define sl_sysrtc_get_status sl_hal_sysrtc_get_status +#define sl_sysrtc_lock sl_hal_sysrtc_lock +#define sl_sysrtc_unlock sl_hal_sysrtc_unlock +#define sl_sysrtc_get_counter sl_hal_sysrtc_get_counter +#define sl_sysrtc_set_counter sl_hal_sysrtc_set_counter +#define sl_sysrtc_init_group sl_hal_sysrtc_init_group +#define sl_sysrtc_enable_group_interrupts sl_hal_sysrtc_enable_group_interrupts +#define sl_sysrtc_disable_group_interrupts sl_hal_sysrtc_disable_group_interrupts +#define sl_sysrtc_clear_group_interrupts sl_hal_sysrtc_clear_group_interrupts +#define sl_sysrtc_get_group_interrupts sl_hal_sysrtc_get_group_interrupts +#define sl_sysrtc_get_group_enabled_interrupts sl_hal_sysrtc_get_group_enabled_interrupts +#define sl_sysrtc_set_group_interrupts sl_hal_sysrtc_set_group_interrupts +#define sl_sysrtc_get_group_compare_channel_value sl_hal_sysrtc_get_group_compare_channel_value +#define sl_sysrtc_set_group_compare_channel_value sl_hal_sysrtc_set_group_compare_channel_value +#define sl_sysrtc_get_group_capture_channel_value sl_hal_sysrtc_get_group_capture_channel_value + +#ifdef __cplusplus +} +#endif + +#endif // PERIPHERAL_SYSRTC_COMPAT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/peripheral/src/peripheral_sysrtc.c b/locator_host/gecko_sdk_4.4.1/platform/peripheral/src/peripheral_sysrtc.c index 7a0706d..45e897b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/peripheral/src/peripheral_sysrtc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/peripheral/src/peripheral_sysrtc.c @@ -1,1013 +1,1013 @@ -/***************************************************************************//** - * @file - * @brief System Real Time Counter (SYSRTC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "peripheral_sysrtc.h" -#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) -#include "sl_assert.h" -#include "em_bus.h" -#include "stddef.h" - -/***************************************************************************//** - * @addtogroup sysrtc SYSRTC - System Real Time Counter - * @brief System Real Time Counter (SYSRTC) Peripheral API - * @details - * This module contains functions to control the SYSRTC peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The SYSRTC ensures timekeeping in low energy modes. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -extern __INLINE void sl_hal_sysrtc_wait_sync(void); -extern __INLINE void sl_hal_sysrtc_wait_ready(void); -extern __INLINE void sl_hal_sysrtc_start(void); -extern __INLINE void sl_hal_sysrtc_stop(void); -extern __INLINE uint32_t sl_hal_sysrtc_get_status(void); -extern __INLINE void sl_hal_sysrtc_lock(void); -extern __INLINE void sl_hal_sysrtc_unlock(void); -extern __INLINE uint32_t sl_hal_sysrtc_get_counter(void); -extern __INLINE void sl_hal_sysrtc_set_counter(uint32_t value); - -/***************************************************************************//** - * Initializes SYSRTC module. - ******************************************************************************/ -void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config) -{ - // Wait to be ready - sl_hal_sysrtc_wait_ready(); - - if (SYSRTC0->EN == SYSRTC_EN_EN) { - // Disable the module - sl_hal_sysrtc_disable(); - // Wait to be ready - sl_hal_sysrtc_wait_ready(); - } - - // Set configuration - SYSRTC0->CFG = (p_config->enable_debug_run ? 1UL : 0UL) << _SYSRTC_CFG_DEBUGRUN_SHIFT; -} - -/***************************************************************************//** - * Enables SYSRTC counting. - ******************************************************************************/ -void sl_hal_sysrtc_enable(void) -{ - // Wait if disabling - sl_hal_sysrtc_wait_ready(); - - // Enable SYSRTC module - SYSRTC0->EN_SET = SYSRTC_EN_EN; - - // Start counter - SYSRTC0->CMD = SYSRTC_CMD_START; -} - -/***************************************************************************//** - * Disables SYSRTC counting. - ******************************************************************************/ -void sl_hal_sysrtc_disable(void) -{ - if (SYSRTC0->EN != SYSRTC_EN_EN) { - return; - } - - // Stop counter - sl_hal_sysrtc_stop(); - - // Disable module - SYSRTC0->EN_CLR = SYSRTC_EN_EN; -} - -/***************************************************************************//** - * Restores SYSRTC to its reset state. - ******************************************************************************/ -void sl_hal_sysrtc_reset(void) -{ - // Reset timer - SYSRTC0->SWRST = SYSRTC_SWRST_SWRST; -} - -/***************************************************************************//** - * Initializes the selected SYSRTC group. - ******************************************************************************/ -void sl_hal_sysrtc_init_group(uint8_t group_number, - sl_hal_sysrtc_group_config_t const *p_group_config) -{ - uint32_t temp = 0; - - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT); - if (p_group_config->p_compare_channel0_config != NULL) { - temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT); - } - -#ifdef SYSRTC_GRP0_CTRL_CMP1EN - temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT); - if (p_group_config->p_compare_channel1_config != NULL) { - temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); - } -#endif -#ifdef SYSRTC_GRP0_CTRL_CAP0EN - temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT); - if (p_group_config->p_capture_channel0_config != NULL) { - temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); - } -#endif - SYSRTC0->GRP0_CTRL = temp; - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP0EN_SHIFT); - if (p_group_config->p_compare_channel0_config != NULL) { - temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP0CMOA_SHIFT); - } -#ifdef SYSRTC_GRP1_CTRL_CMP1EN - temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP1EN_SHIFT); - if (p_group_config->p_compare_channel1_config != NULL) { - temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP1CMOA_SHIFT); - } -#endif -#ifdef SYSRTC_GRP1_CTRL_CAP0EN - temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CAP0EN_SHIFT); - if (p_group_config->p_capture_channel0_config != NULL) { - temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP1_CTRL_CAP0EDGE_SHIFT); - } -#endif - SYSRTC0->GRP1_CTRL = temp; - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: -// SYSRTC0->GRP2_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP0EN_SHIFT) -// | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP2_CTRL_CMP1EN - SYSRTC0->GRP2_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP2_CTRL_CAP0EN - SYSRTC0->GRP2_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP2_CTRL_CAP0EDGE_SHIFT); -#endif - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - SYSRTC0->GRP3_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP0EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP3_CTRL_CMP1EN - SYSRTC0->GRP3_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP3_CTRL_CAP0EN - SYSRTC0->GRP3_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP3_CTRL_CAP0EDGE_SHIFT); -#endif - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - SYSRTC0->GRP4_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP0EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP4_CTRL_CMP1EN - SYSRTC0->GRP4_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP4_CTRL_CAP0EN - SYSRTC0->GRP4_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP4_CTRL_CAP0EDGE_SHIFT); -#endif - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - SYSRTC0->GRP5_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP0EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP5_CTRL_CMP1EN - SYSRTC0->GRP5_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP5_CTRL_CAP0EN - SYSRTC0->GRP5_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP5_CTRL_CAP0EDGE_SHIFT); -#endif - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - SYSRTC0->GRP6_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP0EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP6_CTRL_CMP1EN - SYSRTC0->GRP6_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP6_CTRL_CAP0EN - SYSRTC0->GRP6_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP6_CTRL_CAP0EDGE_SHIFT); -#endif - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - SYSRTC0->GRP7_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP0EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP0CMOA_SHIFT); -#ifdef SYSRTC_GRP7_CTRL_CMP1EN - SYSRTC0->GRP7_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP1EN_SHIFT) - | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP1CMOA_SHIFT); -#endif -#ifdef SYSRTC_GRP7_CTRL_CAP0EN - SYSRTC0->GRP7_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CAP0EN_SHIFT) - | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP7_CTRL_CAP0EDGE_SHIFT); -#endif - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Enables one or more SYSRTC interrupts for the given group. - ******************************************************************************/ -void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, - uint32_t flags) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - SYSRTC0->GRP0_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - SYSRTC0->GRP1_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - SYSRTC0->GRP2_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - SYSRTC0->GRP3_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - SYSRTC0->GRP4_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - SYSRTC0->GRP5_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - SYSRTC0->GRP6_IEN_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - SYSRTC0->GRP7_IEN_SET = flags; - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Disables one or more SYSRTC interrupts for the given group. - ******************************************************************************/ -void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, - uint32_t flags) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - SYSRTC0->GRP0_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - SYSRTC0->GRP1_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - SYSRTC0->GRP2_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - SYSRTC0->GRP3_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - SYSRTC0->GRP4_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - SYSRTC0->GRP5_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - SYSRTC0->GRP6_IEN_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - SYSRTC0->GRP7_IEN_CLR = flags; - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Clears one or more pending SYSRTC interrupts for the given group. - ******************************************************************************/ -void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, - uint32_t flags) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - SYSRTC0->GRP0_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - SYSRTC0->GRP1_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - SYSRTC0->GRP2_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - SYSRTC0->GRP3_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - SYSRTC0->GRP4_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - SYSRTC0->GRP5_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - SYSRTC0->GRP6_IF_CLR = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - SYSRTC0->GRP7_IF_CLR = flags; - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Gets pending SYSRTC interrupt flags for the given group. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - return SYSRTC0->GRP0_IF; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - return SYSRTC0->GRP1_IF; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - return SYSRTC0->GRP2_IF; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - return SYSRTC0->GRP3_IF; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - return SYSRTC0->GRP4_IF; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - return SYSRTC0->GRP5_IF; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - return SYSRTC0->GRP6_IF; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - return SYSRTC0->GRP7_IF; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - return 0; - } -} - -/***************************************************************************//** - * Gets enabled and pending SYSRTC interrupt flags. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number) -{ - uint32_t ien = 0; - - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - ien = SYSRTC0->GRP0_IEN; - return SYSRTC0->GRP0_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - ien = SYSRTC0->GRP1_IEN; - return SYSRTC0->GRP1_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - ien = SYSRTC0->GRP2_IEN; - return SYSRTC0->GRP2_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - ien = SYSRTC0->GRP3_IEN; - return SYSRTC0->GRP3_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - ien = SYSRTC0->GRP4_IEN; - return SYSRTC0->GRP4_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - ien = SYSRTC0->GRP5_IEN; - return SYSRTC0->GRP5_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - ien = SYSRTC0->GRP6_IEN; - return SYSRTC0->GRP6_IF & ien; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - ien = SYSRTC0->GRP7_IEN; - return SYSRTC0->GRP7_IF & ien; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - return 0; - } -} - -/***************************************************************************//** - * Sets one or more pending SYSRTC interrupts for the given group from Software. - ******************************************************************************/ -void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, - uint32_t flags) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - SYSRTC0->GRP0_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - SYSRTC0->GRP1_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - SYSRTC0->GRP2_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - SYSRTC0->GRP3_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - SYSRTC0->GRP4_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - SYSRTC0->GRP5_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - SYSRTC0->GRP6_IF_SET = flags; - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - SYSRTC0->GRP7_IF_SET = flags; - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Gets SYSRTC compare register value for selected channel of given group. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, - uint8_t channel) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - switch (channel) { - case 0: - return SYSRTC0->GRP0_CMP0VALUE; - -#ifdef SYSRTC_GRP0_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP0_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - switch (channel) { - case 0: - return SYSRTC0->GRP1_CMP0VALUE; - -#ifdef SYSRTC_GRP1_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP1_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - switch (channel) { - case 0: - return SYSRTC0->GRP2_CMP0VALUE; - -#ifdef SYSRTC_GRP2_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP2_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - switch (channel) { - case 0: - return SYSRTC0->GRP3_CMP0VALUE; - -#ifdef SYSRTC_GRP3_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP3_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - switch (channel) { - case 0: - return SYSRTC0->GRP4_CMP0VALUE; - -#ifdef SYSRTC_GRP4_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP4_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - switch (channel) { - case 0: - return SYSRTC0->GRP5_CMP0VALUE; - -#ifdef SYSRTC_GRP5_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP5_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - switch (channel) { - case 0: - return SYSRTC0->GRP6_CMP0VALUE; - -#ifdef SYSRTC_GRP6_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP6_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - switch (channel) { - case 0: - return SYSRTC0->GRP7_CMP0VALUE; - -#ifdef SYSRTC_GRP7_CTRL_CMP1EN - case 1: - return SYSRTC0->GRP7_CMP1VALUE; -#endif - - default: - EFM_ASSERT(1); - return 0; - } - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - return 0; - } -} - -/***************************************************************************//** - * Sets SYSRTC compare register value for selected channel of given group. - ******************************************************************************/ -void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, - uint8_t channel, - uint32_t value) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { - case 0: - switch (channel) { - case 0: - SYSRTC0->GRP0_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP0_CTRL_CMP1EN - case 1: - SYSRTC0->GRP0_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 1 - case 1: - switch (channel) { - case 0: - SYSRTC0->GRP1_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP1_CTRL_CMP1EN - case 1: - SYSRTC0->GRP1_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 2 - case 2: - switch (channel) { - case 0: - SYSRTC0->GRP2_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP2_CTRL_CMP1EN - case 1: - SYSRTC0->GRP2_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 3 - case 3: - switch (channel) { - case 0: - SYSRTC0->GRP3_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP3_CTRL_CMP1EN - case 1: - SYSRTC0->GRP3_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 4 - case 4: - switch (channel) { - case 0: - SYSRTC0->GRP4_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP4_CTRL_CMP1EN - case 1: - SYSRTC0->GRP4_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 5 - case 5: - switch (channel) { - case 0: - SYSRTC0->GRP5_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP5_CTRL_CMP1EN - case 1: - SYSRTC0->GRP5_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 6 - case 6: - switch (channel) { - case 0: - SYSRTC0->GRP6_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP6_CTRL_CMP1EN - case 1: - SYSRTC0->GRP6_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; - -#if SYSRTC_GROUP_NUMBER > 7 - case 7: - switch (channel) { - case 0: - SYSRTC0->GRP7_CMP0VALUE = value; - break; - -#ifdef SYSRTC_GRP7_CTRL_CMP1EN - case 1: - SYSRTC0->GRP7_CMP1VALUE = value; - break; -#endif - - default: - EFM_ASSERT(1); - } - break; -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - } -} - -/***************************************************************************//** - * Gets SYSRTC input capture register value for selected channel of given group. - ******************************************************************************/ -uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number) -{ - EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); - - switch (group_number) { -#ifdef SYSRTC_GRP0_CTRL_CAP0EN - case 0: - return SYSRTC0->GRP0_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 1 -#ifdef SYSRTC_GRP1_CTRL_CAP0EN - case 1: - return SYSRTC0->GRP1_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 2 -#ifdef SYSRTC_GRP2_CTRL_CAP0EN - case 2: - return SYSRTC0->GRP2_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 3 -#ifdef SYSRTC_GRP3_CTRL_CAP0EN - case 3: - return SYSRTC0->GRP3_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 4 -#ifdef SYSRTC_GRP4_CTRL_CAP0EN - case 4: - return SYSRTC0->GRP4_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 5 -#ifdef SYSRTC_GRP5_CTRL_CAP0EN - case 5: - return SYSRTC0->GRP5_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 6 -#ifdef SYSRTC_GRP6_CTRL_CAP0EN - case 6: - return SYSRTC0->GRP6_CAP0VALUE; -#endif - -#if SYSRTC_GROUP_NUMBER > 7 -#ifdef SYSRTC_GRP7_CTRL_CAP0EN - case 7: - return SYSRTC0->GRP7_CAP0VALUE; -#endif -#endif -#endif -#endif -#endif -#endif -#endif -#endif - - default: - EFM_ASSERT(1); - return 0; - } -} - -/** @} (end addtogroup sysrtc) */ -#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief System Real Time Counter (SYSRTC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "peripheral_sysrtc.h" +#if defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) +#include "sl_assert.h" +#include "em_bus.h" +#include "stddef.h" + +/***************************************************************************//** + * @addtogroup sysrtc SYSRTC - System Real Time Counter + * @brief System Real Time Counter (SYSRTC) Peripheral API + * @details + * This module contains functions to control the SYSRTC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The SYSRTC ensures timekeeping in low energy modes. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +extern __INLINE void sl_hal_sysrtc_wait_sync(void); +extern __INLINE void sl_hal_sysrtc_wait_ready(void); +extern __INLINE void sl_hal_sysrtc_start(void); +extern __INLINE void sl_hal_sysrtc_stop(void); +extern __INLINE uint32_t sl_hal_sysrtc_get_status(void); +extern __INLINE void sl_hal_sysrtc_lock(void); +extern __INLINE void sl_hal_sysrtc_unlock(void); +extern __INLINE uint32_t sl_hal_sysrtc_get_counter(void); +extern __INLINE void sl_hal_sysrtc_set_counter(uint32_t value); + +/***************************************************************************//** + * Initializes SYSRTC module. + ******************************************************************************/ +void sl_hal_sysrtc_init(const sl_hal_sysrtc_config_t *p_config) +{ + // Wait to be ready + sl_hal_sysrtc_wait_ready(); + + if (SYSRTC0->EN == SYSRTC_EN_EN) { + // Disable the module + sl_hal_sysrtc_disable(); + // Wait to be ready + sl_hal_sysrtc_wait_ready(); + } + + // Set configuration + SYSRTC0->CFG = (p_config->enable_debug_run ? 1UL : 0UL) << _SYSRTC_CFG_DEBUGRUN_SHIFT; +} + +/***************************************************************************//** + * Enables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_enable(void) +{ + // Wait if disabling + sl_hal_sysrtc_wait_ready(); + + // Enable SYSRTC module + SYSRTC0->EN_SET = SYSRTC_EN_EN; + + // Start counter + SYSRTC0->CMD = SYSRTC_CMD_START; +} + +/***************************************************************************//** + * Disables SYSRTC counting. + ******************************************************************************/ +void sl_hal_sysrtc_disable(void) +{ + if (SYSRTC0->EN != SYSRTC_EN_EN) { + return; + } + + // Stop counter + sl_hal_sysrtc_stop(); + + // Disable module + SYSRTC0->EN_CLR = SYSRTC_EN_EN; +} + +/***************************************************************************//** + * Restores SYSRTC to its reset state. + ******************************************************************************/ +void sl_hal_sysrtc_reset(void) +{ + // Reset timer + SYSRTC0->SWRST = SYSRTC_SWRST_SWRST; +} + +/***************************************************************************//** + * Initializes the selected SYSRTC group. + ******************************************************************************/ +void sl_hal_sysrtc_init_group(uint8_t group_number, + sl_hal_sysrtc_group_config_t const *p_group_config) +{ + uint32_t temp = 0; + + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT); + if (p_group_config->p_compare_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT); + } + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT); + if (p_group_config->p_compare_channel1_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); + } +#endif +#ifdef SYSRTC_GRP0_CTRL_CAP0EN + temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT); + if (p_group_config->p_capture_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); + } +#endif + SYSRTC0->GRP0_CTRL = temp; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + temp = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP0EN_SHIFT); + if (p_group_config->p_compare_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP0CMOA_SHIFT); + } +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + temp |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CMP1EN_SHIFT); + if (p_group_config->p_compare_channel1_config != NULL) { + temp |= ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP1_CTRL_CMP1CMOA_SHIFT); + } +#endif +#ifdef SYSRTC_GRP1_CTRL_CAP0EN + temp |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP1_CTRL_CAP0EN_SHIFT); + if (p_group_config->p_capture_channel0_config != NULL) { + temp |= ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP1_CTRL_CAP0EDGE_SHIFT); + } +#endif + SYSRTC0->GRP1_CTRL = temp; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: +// SYSRTC0->GRP2_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP0EN_SHIFT) +// | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + SYSRTC0->GRP2_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP2_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP2_CTRL_CAP0EN + SYSRTC0->GRP2_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP2_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP2_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + SYSRTC0->GRP3_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP3_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP3_CTRL_CAP0EN + SYSRTC0->GRP3_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP3_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP3_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + SYSRTC0->GRP4_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP4_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP4_CTRL_CAP0EN + SYSRTC0->GRP4_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP4_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP4_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + SYSRTC0->GRP5_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP5_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP5_CTRL_CAP0EN + SYSRTC0->GRP5_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP5_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP5_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + SYSRTC0->GRP6_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP6_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP6_CTRL_CAP0EN + SYSRTC0->GRP6_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP6_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP6_CTRL_CAP0EDGE_SHIFT); +#endif + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_CTRL = ((p_group_config->compare_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP0EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel0_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP0CMOA_SHIFT); +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + SYSRTC0->GRP7_CTRL |= ((p_group_config->compare_channel1_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CMP1EN_SHIFT) + | ((uint32_t)p_group_config->p_compare_channel1_config->compare_match_out_action << _SYSRTC_GRP7_CTRL_CMP1CMOA_SHIFT); +#endif +#ifdef SYSRTC_GRP7_CTRL_CAP0EN + SYSRTC0->GRP7_CTRL |= ((p_group_config->capture_channel0_enable ? 1UL : 0UL) << _SYSRTC_GRP7_CTRL_CAP0EN_SHIFT) + | ((uint32_t)p_group_config->p_capture_channel0_config->capture_input_edge << _SYSRTC_GRP7_CTRL_CAP0EDGE_SHIFT); +#endif + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Enables one or more SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_enable_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IEN_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IEN_SET = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Disables one or more SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_disable_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IEN_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IEN_CLR = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Clears one or more pending SYSRTC interrupts for the given group. + ******************************************************************************/ +void sl_hal_sysrtc_clear_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IF_CLR = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IF_CLR = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets pending SYSRTC interrupt flags for the given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_interrupts(uint8_t group_number) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + return SYSRTC0->GRP0_IF; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + return SYSRTC0->GRP1_IF; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + return SYSRTC0->GRP2_IF; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + return SYSRTC0->GRP3_IF; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + return SYSRTC0->GRP4_IF; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + return SYSRTC0->GRP5_IF; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + return SYSRTC0->GRP6_IF; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + return SYSRTC0->GRP7_IF; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Gets enabled and pending SYSRTC interrupt flags. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_enabled_interrupts(uint8_t group_number) +{ + uint32_t ien = 0; + + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + ien = SYSRTC0->GRP0_IEN; + return SYSRTC0->GRP0_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + ien = SYSRTC0->GRP1_IEN; + return SYSRTC0->GRP1_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + ien = SYSRTC0->GRP2_IEN; + return SYSRTC0->GRP2_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + ien = SYSRTC0->GRP3_IEN; + return SYSRTC0->GRP3_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + ien = SYSRTC0->GRP4_IEN; + return SYSRTC0->GRP4_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + ien = SYSRTC0->GRP5_IEN; + return SYSRTC0->GRP5_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + ien = SYSRTC0->GRP6_IEN; + return SYSRTC0->GRP6_IF & ien; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + ien = SYSRTC0->GRP7_IEN; + return SYSRTC0->GRP7_IF & ien; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Sets one or more pending SYSRTC interrupts for the given group from Software. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_interrupts(uint8_t group_number, + uint32_t flags) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + SYSRTC0->GRP0_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + SYSRTC0->GRP1_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + SYSRTC0->GRP2_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + SYSRTC0->GRP3_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + SYSRTC0->GRP4_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + SYSRTC0->GRP5_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + SYSRTC0->GRP6_IF_SET = flags; + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + SYSRTC0->GRP7_IF_SET = flags; + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets SYSRTC compare register value for selected channel of given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_compare_channel_value(uint8_t group_number, + uint8_t channel) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + switch (channel) { + case 0: + return SYSRTC0->GRP0_CMP0VALUE; + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP0_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + switch (channel) { + case 0: + return SYSRTC0->GRP1_CMP0VALUE; + +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP1_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + switch (channel) { + case 0: + return SYSRTC0->GRP2_CMP0VALUE; + +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP2_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + switch (channel) { + case 0: + return SYSRTC0->GRP3_CMP0VALUE; + +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP3_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + switch (channel) { + case 0: + return SYSRTC0->GRP4_CMP0VALUE; + +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP4_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + switch (channel) { + case 0: + return SYSRTC0->GRP5_CMP0VALUE; + +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP5_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + switch (channel) { + case 0: + return SYSRTC0->GRP6_CMP0VALUE; + +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP6_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + switch (channel) { + case 0: + return SYSRTC0->GRP7_CMP0VALUE; + +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + case 1: + return SYSRTC0->GRP7_CMP1VALUE; +#endif + + default: + EFM_ASSERT(1); + return 0; + } + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/***************************************************************************//** + * Sets SYSRTC compare register value for selected channel of given group. + ******************************************************************************/ +void sl_hal_sysrtc_set_group_compare_channel_value(uint8_t group_number, + uint8_t channel, + uint32_t value) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { + case 0: + switch (channel) { + case 0: + SYSRTC0->GRP0_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP0_CTRL_CMP1EN + case 1: + SYSRTC0->GRP0_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 1 + case 1: + switch (channel) { + case 0: + SYSRTC0->GRP1_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP1_CTRL_CMP1EN + case 1: + SYSRTC0->GRP1_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 2 + case 2: + switch (channel) { + case 0: + SYSRTC0->GRP2_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP2_CTRL_CMP1EN + case 1: + SYSRTC0->GRP2_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 3 + case 3: + switch (channel) { + case 0: + SYSRTC0->GRP3_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP3_CTRL_CMP1EN + case 1: + SYSRTC0->GRP3_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 4 + case 4: + switch (channel) { + case 0: + SYSRTC0->GRP4_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP4_CTRL_CMP1EN + case 1: + SYSRTC0->GRP4_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 5 + case 5: + switch (channel) { + case 0: + SYSRTC0->GRP5_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP5_CTRL_CMP1EN + case 1: + SYSRTC0->GRP5_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 6 + case 6: + switch (channel) { + case 0: + SYSRTC0->GRP6_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP6_CTRL_CMP1EN + case 1: + SYSRTC0->GRP6_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; + +#if SYSRTC_GROUP_NUMBER > 7 + case 7: + switch (channel) { + case 0: + SYSRTC0->GRP7_CMP0VALUE = value; + break; + +#ifdef SYSRTC_GRP7_CTRL_CMP1EN + case 1: + SYSRTC0->GRP7_CMP1VALUE = value; + break; +#endif + + default: + EFM_ASSERT(1); + } + break; +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + } +} + +/***************************************************************************//** + * Gets SYSRTC input capture register value for selected channel of given group. + ******************************************************************************/ +uint32_t sl_hal_sysrtc_get_group_capture_channel_value(uint8_t group_number) +{ + EFM_ASSERT(SYSRTC_GROUP_VALID(group_number)); + + switch (group_number) { +#ifdef SYSRTC_GRP0_CTRL_CAP0EN + case 0: + return SYSRTC0->GRP0_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 1 +#ifdef SYSRTC_GRP1_CTRL_CAP0EN + case 1: + return SYSRTC0->GRP1_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 2 +#ifdef SYSRTC_GRP2_CTRL_CAP0EN + case 2: + return SYSRTC0->GRP2_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 3 +#ifdef SYSRTC_GRP3_CTRL_CAP0EN + case 3: + return SYSRTC0->GRP3_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 4 +#ifdef SYSRTC_GRP4_CTRL_CAP0EN + case 4: + return SYSRTC0->GRP4_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 5 +#ifdef SYSRTC_GRP5_CTRL_CAP0EN + case 5: + return SYSRTC0->GRP5_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 6 +#ifdef SYSRTC_GRP6_CTRL_CAP0EN + case 6: + return SYSRTC0->GRP6_CAP0VALUE; +#endif + +#if SYSRTC_GROUP_NUMBER > 7 +#ifdef SYSRTC_GRP7_CTRL_CAP0EN + case 7: + return SYSRTC0->GRP7_CAP0VALUE; +#endif +#endif +#endif +#endif +#endif +#endif +#endif +#endif + + default: + EFM_ASSERT(1); + return 0; + } +} + +/** @} (end addtogroup sysrtc) */ +#endif /* defined(SYSRTC_COUNT) && (SYSRTC_COUNT > 0) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h index 766f3a6..548774e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h @@ -1,121 +1,121 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for clocks. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_CLOCKS_H -#define SL_DEVICE_INIT_CLOCKS_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init Device Initialization - * @brief Device Initialization - * @details - * The Device Initialization functions assist in bringing the device from the - * reset state to an initialized state by applying errata fixes, starting - * oscillators and configuring certain power control features. - * - * The top-level Device Init component will automatically add required and - * recommended initialization components to the platform init event handled - * by the System Init component based on the selected hardware. - * - * - Errata fixes are applied on all devices - * - EMU initialization is added on all devices - * - Clock tree initialization is added on all devices - * - NVIC initialization is added on all devices - * - DCDC initialization is added on devices with a DCDC converter - * - HFXO initialization is added on Silicon Labs modules and development - * boards with HFXO - * - LFXO initialization is added on Silicon Labs modules and development - * boards with LFXO - * - HFRCO initialization is added on EFR32xG21 devices to set the core - * frequency to 80 MHz (oscillator band is configurable in the component) - * - LFRCO initialization is added on EFR32xG22 devices when Bluetooth is - * present to enable high precision mode (precision mode is configurable - * in the component) - * - * If the individual initialization components are not sufficiently configurable, - * or if any of these default actions are not desired, the top-level device - * initialization component can be removed from the project and replaced by the - * subset of desired initialization components. - * - * @{ - * @addtogroup device_init_clocks Clock Initialization - * @brief Initialize the clock tree. - * @details - * - * Automatically configures the clock tree to use the appropriate high- and - * low-frequency clock sources depending on which other device initialization - * components are present. - * - * ### High Frequency Clocks - * If the **DPLL** or **HFRCO** device init components are present, the - * **HFRCO** oscillator is used as the clock source for high frequency clock - * trees. Otherwise, if the **HFXO** device init component is present, the - * **HFXO** oscillator is used. If no high frequency oscillator device init - * component is present, the **HFRCO** oscillator is used with its default - * settings. - * - * ### Low Frequency Clocks - * If the **LFXO** device init component is present, the **LFXO** oscillator is - * used as the clock source for low frequency clock trees. - * Otherwise, the **LFRCO** oscillator is used. - * - * @note This module has a limited configurability. Users can override the code - * based on the project ask. - * - * @{ - */ - -/** - * Configure the clock tree and enable clocks - * - * @details - * Automatically configures the clock tree to use the appropriate HF and LF - * clock sources depending on which other device initialization components are - * present. - * - * @return Status code - * @retval SL_STATUS_OK Clock tree configured successfully - */ -sl_status_t sl_device_init_clocks(void); - -/** - * @} device_init_clocks - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_CLOCKS_H +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_CLOCKS_H +#define SL_DEVICE_INIT_CLOCKS_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init Device Initialization + * @brief Device Initialization + * @details + * The Device Initialization functions assist in bringing the device from the + * reset state to an initialized state by applying errata fixes, starting + * oscillators and configuring certain power control features. + * + * The top-level Device Init component will automatically add required and + * recommended initialization components to the platform init event handled + * by the System Init component based on the selected hardware. + * + * - Errata fixes are applied on all devices + * - EMU initialization is added on all devices + * - Clock tree initialization is added on all devices + * - NVIC initialization is added on all devices + * - DCDC initialization is added on devices with a DCDC converter + * - HFXO initialization is added on Silicon Labs modules and development + * boards with HFXO + * - LFXO initialization is added on Silicon Labs modules and development + * boards with LFXO + * - HFRCO initialization is added on EFR32xG21 devices to set the core + * frequency to 80 MHz (oscillator band is configurable in the component) + * - LFRCO initialization is added on EFR32xG22 devices when Bluetooth is + * present to enable high precision mode (precision mode is configurable + * in the component) + * + * If the individual initialization components are not sufficiently configurable, + * or if any of these default actions are not desired, the top-level device + * initialization component can be removed from the project and replaced by the + * subset of desired initialization components. + * + * @{ + * @addtogroup device_init_clocks Clock Initialization + * @brief Initialize the clock tree. + * @details + * + * Automatically configures the clock tree to use the appropriate high- and + * low-frequency clock sources depending on which other device initialization + * components are present. + * + * ### High Frequency Clocks + * If the **DPLL** or **HFRCO** device init components are present, the + * **HFRCO** oscillator is used as the clock source for high frequency clock + * trees. Otherwise, if the **HFXO** device init component is present, the + * **HFXO** oscillator is used. If no high frequency oscillator device init + * component is present, the **HFRCO** oscillator is used with its default + * settings. + * + * ### Low Frequency Clocks + * If the **LFXO** device init component is present, the **LFXO** oscillator is + * used as the clock source for low frequency clock trees. + * Otherwise, the **LFRCO** oscillator is used. + * + * @note This module has a limited configurability. Users can override the code + * based on the project ask. + * + * @{ + */ + +/** + * Configure the clock tree and enable clocks + * + * @details + * Automatically configures the clock tree to use the appropriate HF and LF + * clock sources depending on which other device initialization components are + * present. + * + * @return Status code + * @retval SL_STATUS_OK Clock tree configured successfully + */ +sl_status_t sl_device_init_clocks(void); + +/** + * @} device_init_clocks + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_CLOCKS_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h index bfa0e9e..bba6990 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h @@ -1,88 +1,88 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DC/DC converter. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_DCDC_H -#define SL_DEVICE_INIT_DCDC_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_dcdc DCDC Initialization - * @brief Initialize the DC-DC converter. - * @details - * Configures the DC-DC converter. If the DC-DC converter is not to be - * used, the configuration option `SL_DEVICE_INIT_DCDC_ENABLE` can be disabled, - * and the converter will be powered off. On Series 1 devices, this option - * should only be used when DVDD is externally powered. - * - * To enable the bypass switch and short the DC-DC converter input to - * the DC-DC output, set the configuration option `SL_DEVICE_INIT_DCDC_BYPASS`. - * - * See **AN0948 Power Configurations and DC-DC** for further details about DC-DC - * converter configuration and operation. - * - * - Series 1: [AN0948](https://www.silabs.com/documents/public/application-notes/an0948-power-configurations-and-dcdc.pdf) - * - Series 2: [AN0948.2](https://www.silabs.com/documents/public/application-notes/an0948.2-efr32-series-2-power-configurations-and-dcdc.pdf) - * @{ - */ - -// ----------------------------------------------------------------------------- -// Defines - -/// @brief DC/DC Converter Type -#define SL_DEVICE_INIT_DCDC_TYPE_BUCK 0 ///< Buck Type -#define SL_DEVICE_INIT_DCDC_TYPE_BOOST 1 ///< Boost Type - -/** - * Initialize DCDC - * - * @details - * Configure and start the DCDC - * - * @return Status code - * @retval SL_STATUS_OK DC-DC converter initialized successfully - */ -sl_status_t sl_device_init_dcdc(void); - -/** - * @} device_init_dcdc - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_DCDC_H +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_DCDC_H +#define SL_DEVICE_INIT_DCDC_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_dcdc DCDC Initialization + * @brief Initialize the DC-DC converter. + * @details + * Configures the DC-DC converter. If the DC-DC converter is not to be + * used, the configuration option `SL_DEVICE_INIT_DCDC_ENABLE` can be disabled, + * and the converter will be powered off. On Series 1 devices, this option + * should only be used when DVDD is externally powered. + * + * To enable the bypass switch and short the DC-DC converter input to + * the DC-DC output, set the configuration option `SL_DEVICE_INIT_DCDC_BYPASS`. + * + * See **AN0948 Power Configurations and DC-DC** for further details about DC-DC + * converter configuration and operation. + * + * - Series 1: [AN0948](https://www.silabs.com/documents/public/application-notes/an0948-power-configurations-and-dcdc.pdf) + * - Series 2: [AN0948.2](https://www.silabs.com/documents/public/application-notes/an0948.2-efr32-series-2-power-configurations-and-dcdc.pdf) + * @{ + */ + +// ----------------------------------------------------------------------------- +// Defines + +/// @brief DC/DC Converter Type +#define SL_DEVICE_INIT_DCDC_TYPE_BUCK 0 ///< Buck Type +#define SL_DEVICE_INIT_DCDC_TYPE_BOOST 1 ///< Boost Type + +/** + * Initialize DCDC + * + * @details + * Configure and start the DCDC + * + * @return Status code + * @retval SL_STATUS_OK DC-DC converter initialized successfully + */ +sl_status_t sl_device_init_dcdc(void); + +/** + * @} device_init_dcdc + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_DCDC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dpll.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dpll.h index e85ecc1..5f0e5fd 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dpll.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dpll.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DPLL. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_DPLL_H -#define SL_DEVICE_INIT_DPLL_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_dpll DPLL Initialization - * @brief Initialize the Digital PLL - * @details - * Configures and locks the Digital PLL using the configuration in the - * configuration header `sl_device_init_dpll_config.h`, where settings including - * reference frequency, target frequency and lock mode are available. - * - * If using Simplicity Studio, this configuration header is also configurable - * through the Project Configurator, by selecting the "Device Init: DPLL" configuration component. - * - * @{ - */ - -/** - * Initialize DPLL - * - * @details - * Configures and locks the Digital PLL using the configuration in the - * configuration header `sl_device_init_dpll_config.h`, where settings including - * reference frequency, target frequency and lock mode are available. - * - * @return Status code - * @retval SL_STATUS_OK DPLL successfully initialized and locked - * @retval SL_STATUS_FAIL DPLL lock was unsuccessful - */ -sl_status_t sl_device_init_dpll(void); - -/** - * @} device_init_dpll - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_DPLL_H +/***************************************************************************//** + * @file + * @brief Device initialization for DPLL. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_DPLL_H +#define SL_DEVICE_INIT_DPLL_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_dpll DPLL Initialization + * @brief Initialize the Digital PLL + * @details + * Configures and locks the Digital PLL using the configuration in the + * configuration header `sl_device_init_dpll_config.h`, where settings including + * reference frequency, target frequency and lock mode are available. + * + * If using Simplicity Studio, this configuration header is also configurable + * through the Project Configurator, by selecting the "Device Init: DPLL" configuration component. + * + * @{ + */ + +/** + * Initialize DPLL + * + * @details + * Configures and locks the Digital PLL using the configuration in the + * configuration header `sl_device_init_dpll_config.h`, where settings including + * reference frequency, target frequency and lock mode are available. + * + * @return Status code + * @retval SL_STATUS_OK DPLL successfully initialized and locked + * @retval SL_STATUS_FAIL DPLL lock was unsuccessful + */ +sl_status_t sl_device_init_dpll(void); + +/** + * @} device_init_dpll + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_DPLL_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h index 9743224..4d1ffe2 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h @@ -1,89 +1,89 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for EMU. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_EMU_H -#define SL_DEVICE_INIT_EMU_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_emu EMU Initialization - * @brief Initialize the Energy Management Unit. - * @details - * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) - * according to settings in the configuration header - * `sl_device_init_emu_config.h`. - * - * On Series 2 devices, debugging in EM2 is enabled by default by ensuring - * that power to the debug power domain is sustained on EM2 entry. - * Debugging in EM2 can be disabled through the configuration header. If - * using Simplicity Studio, this header can also be configured using the - * Project Configurator by selecting the "Device Init: EMU" configuration - * component. - * - * @note Voltage scaling for Energy Modes 0 to 3 are configured by the - * @ref power_manager. - * @{ - */ - -/** - * Initialize EMU - * - * @details - * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) - * according to settings in the configuration header - * `sl_device_init_emu_config.h`. - * - * On Series 2 devices, debugging in EM2 is enabled by default by ensuring - * that power to the debug power domain is sustained on EM2 entry. - * - * @note Voltage scaling for Energy Modes 0 to 3 are configured by the - * @ref power_manager. - * - * @return Status code - * @retval SL_STATUS_OK EMU initialized successfully - */ -sl_status_t sl_device_init_emu(void); - -/** - * @} device_init_emu - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_EMU_H +/***************************************************************************//** + * @file + * @brief Device initialization for EMU. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_EMU_H +#define SL_DEVICE_INIT_EMU_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_emu EMU Initialization + * @brief Initialize the Energy Management Unit. + * @details + * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) + * according to settings in the configuration header + * `sl_device_init_emu_config.h`. + * + * On Series 2 devices, debugging in EM2 is enabled by default by ensuring + * that power to the debug power domain is sustained on EM2 entry. + * Debugging in EM2 can be disabled through the configuration header. If + * using Simplicity Studio, this header can also be configured using the + * Project Configurator by selecting the "Device Init: EMU" configuration + * component. + * + * @note Voltage scaling for Energy Modes 0 to 3 are configured by the + * @ref power_manager. + * @{ + */ + +/** + * Initialize EMU + * + * @details + * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) + * according to settings in the configuration header + * `sl_device_init_emu_config.h`. + * + * On Series 2 devices, debugging in EM2 is enabled by default by ensuring + * that power to the debug power domain is sustained on EM2 entry. + * + * @note Voltage scaling for Energy Modes 0 to 3 are configured by the + * @ref power_manager. + * + * @return Status code + * @retval SL_STATUS_OK EMU initialized successfully + */ +sl_status_t sl_device_init_emu(void); + +/** + * @} device_init_emu + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_EMU_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h index cb97a3f..d9f2dfc 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h @@ -1,88 +1,88 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for HFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_H -#define SL_DEVICE_INIT_HFXO_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_hfxo HFXO Initialization - * @brief Initialize the HFXO oscillator. - * @details - * Configure the HFXO for crystal or externally-generated waveform operation. - * - * When operating in crystal mode, the value of the variable tuning capacitor - * Ctune is sourced from a prioritized list of locations: - * - * 1. Device-specific tuning value in Device Information page (factory calibrated PCB and SiP modules with integrated HFXO) - * 2. Device-specific tuning value in User Data page at offset 0x100 (manufacturing token `TOKEN_MFG_CTUNE`) - * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` - * 4. Default value in EMLIB initialization struct for HFXO - * - * If using Simplicity Studio, this configuration header is also configurable through the Project Configurator by selecting the - * "Device Init: HFXO" configuration component. - * @{ - */ - -/** - * Initialize HFXO - * - * @details - * Configure the HFXO for crystal or externally-generated waveform operation. - * - * When operating in crystal mode, the value of the variable tuning capacitor - * Ctune is sourced from a prioritized list of locations: - * - * 1. Device-specific tuning value in Device Information page (PCB and SiP modules with integrated HFXO) - * 2. Device-specific tuning value in User Data page at offset 0x100 ("manufacturing token") - * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` - * 4. Default value in EMLIB initialization struct for HFXO - * - * @return Status code - * @retval SL_STATUS_OK HFXO started successfully - */ -sl_status_t sl_device_init_hfxo(void); - -/** - * @} device_init_hfxo - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_HFXO_H +/***************************************************************************//** + * @file + * @brief Device initialization for HFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_HFXO_H +#define SL_DEVICE_INIT_HFXO_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_hfxo HFXO Initialization + * @brief Initialize the HFXO oscillator. + * @details + * Configure the HFXO for crystal or externally-generated waveform operation. + * + * When operating in crystal mode, the value of the variable tuning capacitor + * Ctune is sourced from a prioritized list of locations: + * + * 1. Device-specific tuning value in Device Information page (factory calibrated PCB and SiP modules with integrated HFXO) + * 2. Device-specific tuning value in User Data page at offset 0x100 (manufacturing token `TOKEN_MFG_CTUNE`) + * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` + * 4. Default value in EMLIB initialization struct for HFXO + * + * If using Simplicity Studio, this configuration header is also configurable through the Project Configurator by selecting the + * "Device Init: HFXO" configuration component. + * @{ + */ + +/** + * Initialize HFXO + * + * @details + * Configure the HFXO for crystal or externally-generated waveform operation. + * + * When operating in crystal mode, the value of the variable tuning capacitor + * Ctune is sourced from a prioritized list of locations: + * + * 1. Device-specific tuning value in Device Information page (PCB and SiP modules with integrated HFXO) + * 2. Device-specific tuning value in User Data page at offset 0x100 ("manufacturing token") + * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` + * 4. Default value in EMLIB initialization struct for HFXO + * + * @return Status code + * @retval SL_STATUS_OK HFXO started successfully + */ +sl_status_t sl_device_init_hfxo(void); + +/** + * @} device_init_hfxo + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_HFXO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h index 6cbd57a..c2cff36 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h @@ -1,85 +1,85 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_LFXO_H -#define SL_DEVICE_INIT_LFXO_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_lfxo LFXO Initialization - * @brief Initialize the LFXO oscillator. - * @details - * Configure the low frequency crystal oscillator using settings in the - * configuration header `sl_device_init_lfxo_config.h`. - * - * The precision of the oscillator can be indicated using the configuration - * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless - * stacks to optimize wakeup time for scheduled events (such as Bluetooth - * advertising). - * - * If using Simplicity Studio, this configuration header is also configurable - * through the Project Configurator by selecting the "Device Init: LFXO" - * configuration component. - * @{ - */ - -/** - * Initialize LFXO - * - * @details - * Configure the low frequency crystal oscillator using settings in the - * configuration header `sl_device_init_lfxo_config.h`. - * - * The precision of the oscillator can be indicated using the configuration - * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless - * stacks to optimize wakeup time for scheduled events (such as Bluetooth - * advertising). - * - * @return Status code - * @retval SL_STATUS_OK LFXO initialized successfully - */ -sl_status_t sl_device_init_lfxo(void); - -/** - * @} device_init_lfxo - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_LFXO_H +/***************************************************************************//** + * @file + * @brief Device initialization for LFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_LFXO_H +#define SL_DEVICE_INIT_LFXO_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_lfxo LFXO Initialization + * @brief Initialize the LFXO oscillator. + * @details + * Configure the low frequency crystal oscillator using settings in the + * configuration header `sl_device_init_lfxo_config.h`. + * + * The precision of the oscillator can be indicated using the configuration + * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless + * stacks to optimize wakeup time for scheduled events (such as Bluetooth + * advertising). + * + * If using Simplicity Studio, this configuration header is also configurable + * through the Project Configurator by selecting the "Device Init: LFXO" + * configuration component. + * @{ + */ + +/** + * Initialize LFXO + * + * @details + * Configure the low frequency crystal oscillator using settings in the + * configuration header `sl_device_init_lfxo_config.h`. + * + * The precision of the oscillator can be indicated using the configuration + * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless + * stacks to optimize wakeup time for scheduled events (such as Bluetooth + * advertising). + * + * @return Status code + * @retval SL_STATUS_OK LFXO initialized successfully + */ +sl_status_t sl_device_init_lfxo(void); + +/** + * @} device_init_lfxo + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_LFXO_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h index be8a677..f200448 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for NVIC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_NVIC_H -#define SL_DEVICE_INIT_NVIC_H - -#include "sl_status.h" - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_nvic NVIC Initialization - * @brief Initialize the NVIC Interrupt Handlers priority. - * @details - * Set all interrupt priorities, except the Fault exceptions, to - * `CORE_INTERRUPT_DEFAULT_PRIORITY` value. - * - * When the Device Init NVIC module is present and no configuration overwrites - * the em_core `CORE_ATOMIC_METHOD` define, the atomic method is automatically - * set to BASEPRI (`CORE_ATOMIC_METHOD_BASEPRI`). - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Sets default priority for all configurable interrupts in NVIC. - * - * @return Status code - ******************************************************************************/ -sl_status_t sl_device_init_nvic(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} device_init_nvic - * @} device_init - */ - -#endif // SL_DEVICE_INIT_NVIC_H +/***************************************************************************//** + * @file + * @brief Device initialization for NVIC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_NVIC_H +#define SL_DEVICE_INIT_NVIC_H + +#include "sl_status.h" + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_nvic NVIC Initialization + * @brief Initialize the NVIC Interrupt Handlers priority. + * @details + * Set all interrupt priorities, except the Fault exceptions, to + * `CORE_INTERRUPT_DEFAULT_PRIORITY` value. + * + * When the Device Init NVIC module is present and no configuration overwrites + * the em_core `CORE_ATOMIC_METHOD` define, the atomic method is automatically + * set to BASEPRI (`CORE_ATOMIC_METHOD_BASEPRI`). + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Sets default priority for all configurable interrupts in NVIC. + * + * @return Status code + ******************************************************************************/ +sl_status_t sl_device_init_nvic(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} device_init_nvic + * @} device_init + */ + +#endif // SL_DEVICE_INIT_NVIC_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c index 5227eb4..c5a1005 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DC/DC converter. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_dcdc.h" -#include "sl_device_init_dcdc_config.h" - -#include "em_emu.h" - -sl_status_t sl_device_init_dcdc(void) -{ -#if !defined(SL_DEVICE_INIT_DCDC_TYPE) || (defined(SL_DEVICE_INIT_DCDC_TYPE) && (SL_DEVICE_INIT_DCDC_TYPE == SL_DEVICE_INIT_DCDC_TYPE_BUCK)) -#if SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; -#if SL_DEVICE_INIT_DCDC_BYPASS - dcdcInit.mode = emuDcdcMode_Bypass; -#endif - EMU_DCDCInit(&dcdcInit); -#if SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE - EMU_DCDCSetPFMXModePeakCurrent(SL_DEVICE_INIT_DCDC_PFMX_IPKVAL); -#endif -#else // SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCPowerOff(); -#endif // SL_DEVICE_INIT_DCDC_ENABLE -#else // SL_DEVICE_INIT_DCDC_TYPE -#if SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; - EMU_DCDCBoostInit(&dcdcBoostInit); -#endif -#endif //SL_DEVICE_INIT_DCDC_TYPE - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_dcdc.h" +#include "sl_device_init_dcdc_config.h" + +#include "em_emu.h" + +sl_status_t sl_device_init_dcdc(void) +{ +#if !defined(SL_DEVICE_INIT_DCDC_TYPE) || (defined(SL_DEVICE_INIT_DCDC_TYPE) && (SL_DEVICE_INIT_DCDC_TYPE == SL_DEVICE_INIT_DCDC_TYPE_BUCK)) +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; +#if SL_DEVICE_INIT_DCDC_BYPASS + dcdcInit.mode = emuDcdcMode_Bypass; +#endif + EMU_DCDCInit(&dcdcInit); +#if SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE + EMU_DCDCSetPFMXModePeakCurrent(SL_DEVICE_INIT_DCDC_PFMX_IPKVAL); +#endif +#else // SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCPowerOff(); +#endif // SL_DEVICE_INIT_DCDC_ENABLE +#else // SL_DEVICE_INIT_DCDC_TYPE +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; + EMU_DCDCBoostInit(&dcdcBoostInit); +#endif +#endif //SL_DEVICE_INIT_DCDC_TYPE + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dpll_s2.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dpll_s2.c index 7e43045..916fad3 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dpll_s2.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dpll_s2.c @@ -1,73 +1,73 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DPLL. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_dpll.h" -#include "sl_device_init_dpll_config.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_dpll(void) -{ - CMU_DPLLInit_TypeDef dpll_init = { - .frequency = SL_DEVICE_INIT_DPLL_FREQ, - .n = SL_DEVICE_INIT_DPLL_N, - .m = SL_DEVICE_INIT_DPLL_M, - .refClk = SL_DEVICE_INIT_DPLL_REFCLK, - .edgeSel = SL_DEVICE_INIT_DPLL_EDGE, - .lockMode = SL_DEVICE_INIT_DPLL_LOCKMODE, - .autoRecover = SL_DEVICE_INIT_DPLL_AUTORECOVER, - .ditherEn = SL_DEVICE_INIT_DPLL_DITHER - }; - - CMU_Select_TypeDef selected_sysclk = CMU_ClockSelectGet(cmuClock_SYSCLK); - - if (selected_sysclk == cmuSelect_HFRCODPLL) { - // From Reference Manual: - // The CMU should not be running from the HFRCO. If necessary, the CMU - // should switch to the FSRCO until after the DPLL has locked to avoid - // over-clocking due to overshoot. - CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); - } - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - CMU_ClockEnable(cmuClock_DPLL0, true); -#endif - - bool success = CMU_DPLLLock(&dpll_init); - - if (selected_sysclk == cmuSelect_HFRCODPLL) { - CMU_CLOCK_SELECT_SET(SYSCLK, HFRCODPLL); - } - - if (success) { - return SL_STATUS_OK; - } else { - return SL_STATUS_FAIL; - } -} +/***************************************************************************//** + * @file + * @brief Device initialization for DPLL. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_dpll.h" +#include "sl_device_init_dpll_config.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_dpll(void) +{ + CMU_DPLLInit_TypeDef dpll_init = { + .frequency = SL_DEVICE_INIT_DPLL_FREQ, + .n = SL_DEVICE_INIT_DPLL_N, + .m = SL_DEVICE_INIT_DPLL_M, + .refClk = SL_DEVICE_INIT_DPLL_REFCLK, + .edgeSel = SL_DEVICE_INIT_DPLL_EDGE, + .lockMode = SL_DEVICE_INIT_DPLL_LOCKMODE, + .autoRecover = SL_DEVICE_INIT_DPLL_AUTORECOVER, + .ditherEn = SL_DEVICE_INIT_DPLL_DITHER + }; + + CMU_Select_TypeDef selected_sysclk = CMU_ClockSelectGet(cmuClock_SYSCLK); + + if (selected_sysclk == cmuSelect_HFRCODPLL) { + // From Reference Manual: + // The CMU should not be running from the HFRCO. If necessary, the CMU + // should switch to the FSRCO until after the DPLL has locked to avoid + // over-clocking due to overshoot. + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + } + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_DPLL0, true); +#endif + + bool success = CMU_DPLLLock(&dpll_init); + + if (selected_sysclk == cmuSelect_HFRCODPLL) { + CMU_CLOCK_SELECT_SET(SYSCLK, HFRCODPLL); + } + + if (success) { + return SL_STATUS_OK; + } else { + return SL_STATUS_FAIL; + } +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c index cf54a76..042467e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c @@ -1,49 +1,49 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for EMU. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_device_init_emu.h" -#include "sl_device_init_emu_config.h" - -#include "em_emu.h" - -sl_status_t sl_device_init_emu(void) -{ - // EM2 set debug enable - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) - | (SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE << _EMU_CTRL_EM2DBGEN_SHIFT); - - // EM4 Init - EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; - - em4_init.pinRetentionMode = SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE; - EMU_EM4Init(&em4_init); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for EMU. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_device_init_emu.h" +#include "sl_device_init_emu_config.h" + +#include "em_emu.h" + +sl_status_t sl_device_init_emu(void) +{ + // EM2 set debug enable + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) + | (SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE << _EMU_CTRL_EM2DBGEN_SHIFT); + + // EM4 Init + EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; + + em4_init.pinRetentionMode = SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE; + EMU_EM4Init(&em4_init); + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c index a65242b..673e17b 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c @@ -1,87 +1,87 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for HFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_hfxo.h" -#include "sl_device_init_hfxo_config.h" - -#include "em_cmu.h" - -// Fetch CTUNE value from USERDATA page as a manufacturing token -#define MFG_CTUNE_ADDR 0x0FE00100UL -#define MFG_CTUNE_VAL (*((uint16_t *) (MFG_CTUNE_ADDR))) - -sl_status_t sl_device_init_hfxo(void) -{ - CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; - hfxoInit.mode = SL_DEVICE_INIT_HFXO_MODE; - - if (SL_DEVICE_INIT_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { - hfxoInit = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; - } - - int ctune = -1; - -#if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) - // Use HFXO tuning value from DEVINFO if available (PCB modules) - if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { - ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; - } -#endif - - // Use HFXO tuning value from MFG token in UD page if not already set - if ((ctune == -1) && (MFG_CTUNE_VAL != 0xFFFF)) { - ctune = MFG_CTUNE_VAL; - } - - // Use HFXO tuning value from configuration header as fallback - if (ctune == -1) { - ctune = SL_DEVICE_INIT_HFXO_CTUNE; - } - - // Configure CTUNE XI and XO. - if (ctune != -1) { - hfxoInit.ctuneXiAna = (uint8_t)ctune; - - // Ensure CTUNE XO plus a delta is within the correct range. The delta accounts for internal chip - // load imbalance on some series 2 chips. - ctune += CMU_HFXOCTuneDeltaGet(); - if (ctune < 0) { - ctune = 0; - } else if (ctune > ((int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT))) { - ctune = (int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); - } - hfxoInit.ctuneXoAna = (uint8_t)ctune; - } - - SystemHFXOClockSet(SL_DEVICE_INIT_HFXO_FREQ); - CMU_HFXOInit(&hfxoInit); - CMU_HFXOPrecisionSet(SL_DEVICE_INIT_HFXO_PRECISION); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for HFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_hfxo.h" +#include "sl_device_init_hfxo_config.h" + +#include "em_cmu.h" + +// Fetch CTUNE value from USERDATA page as a manufacturing token +#define MFG_CTUNE_ADDR 0x0FE00100UL +#define MFG_CTUNE_VAL (*((uint16_t *) (MFG_CTUNE_ADDR))) + +sl_status_t sl_device_init_hfxo(void) +{ + CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; + hfxoInit.mode = SL_DEVICE_INIT_HFXO_MODE; + + if (SL_DEVICE_INIT_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { + hfxoInit = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; + } + + int ctune = -1; + +#if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) + // Use HFXO tuning value from DEVINFO if available (PCB modules) + if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { + ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; + } +#endif + + // Use HFXO tuning value from MFG token in UD page if not already set + if ((ctune == -1) && (MFG_CTUNE_VAL != 0xFFFF)) { + ctune = MFG_CTUNE_VAL; + } + + // Use HFXO tuning value from configuration header as fallback + if (ctune == -1) { + ctune = SL_DEVICE_INIT_HFXO_CTUNE; + } + + // Configure CTUNE XI and XO. + if (ctune != -1) { + hfxoInit.ctuneXiAna = (uint8_t)ctune; + + // Ensure CTUNE XO plus a delta is within the correct range. The delta accounts for internal chip + // load imbalance on some series 2 chips. + ctune += CMU_HFXOCTuneDeltaGet(); + if (ctune < 0) { + ctune = 0; + } else if (ctune > ((int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT))) { + ctune = (int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); + } + hfxoInit.ctuneXoAna = (uint8_t)ctune; + } + + SystemHFXOClockSet(SL_DEVICE_INIT_HFXO_FREQ); + CMU_HFXOInit(&hfxoInit); + CMU_HFXOPrecisionSet(SL_DEVICE_INIT_HFXO_PRECISION); + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c index b3a7669..a7821c0 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c @@ -1,47 +1,47 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_lfxo.h" -#include "sl_device_init_lfxo_config.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_lfxo(void) -{ - CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; - - lfxoInit.mode = SL_DEVICE_INIT_LFXO_MODE; - lfxoInit.capTune = SL_DEVICE_INIT_LFXO_CTUNE; - lfxoInit.timeout = SL_DEVICE_INIT_LFXO_TIMEOUT; - - CMU_LFXOInit(&lfxoInit); - CMU_LFXOPrecisionSet(SL_DEVICE_INIT_LFXO_PRECISION); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for LFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_lfxo.h" +#include "sl_device_init_lfxo_config.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_lfxo(void) +{ + CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; + + lfxoInit.mode = SL_DEVICE_INIT_LFXO_MODE; + lfxoInit.capTune = SL_DEVICE_INIT_LFXO_CTUNE; + lfxoInit.timeout = SL_DEVICE_INIT_LFXO_TIMEOUT; + + CMU_LFXOInit(&lfxoInit); + CMU_LFXOPrecisionSet(SL_DEVICE_INIT_LFXO_PRECISION); + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c index 2386a2f..ba08abe 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c @@ -1,46 +1,46 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for NVIC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_status.h" -#include "em_device.h" -#include "em_core.h" - -/***************************************************************************//** - * Sets default priority for all configurable interrupts in NVIC. - * - * @note Fault exceptions are let at priority 0. - ******************************************************************************/ -sl_status_t sl_device_init_nvic(void) -{ - for (IRQn_Type i = SVCall_IRQn; i < EXT_IRQ_COUNT; i++) { - NVIC_SetPriority(i, CORE_INTERRUPT_DEFAULT_PRIORITY); - } - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for NVIC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "em_device.h" +#include "em_core.h" + +/***************************************************************************//** + * Sets default priority for all configurable interrupts in NVIC. + * + * @note Fault exceptions are let at priority 0. + ******************************************************************************/ +sl_status_t sl_device_init_nvic(void) +{ + for (IRQn_Type i = SVCall_IRQn; i < EXT_IRQ_COUNT; i++) { + NVIC_SetPriority(i, CORE_INTERRUPT_DEFAULT_PRIORITY); + } + + return SL_STATUS_OK; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream.h b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream.h index 9c4d65f..61f3629 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream.h @@ -1,286 +1,286 @@ -/***************************************************************************//** - * @file - * @brief IO Stream. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_H -#define SL_IOSTREAM_H - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#include "sl_enum.h" -#include "sl_status.h" - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup iostream I/O Stream - * @brief I/O Stream can be used to read/write different formats of data to various streams. - * The source files for I/O Stream platform software module are present under platform/services/iostream. - * @details - * ## Overview - * - * I/O Stream is a platform module software that provides Input/Output functionalities - * by creating streams. Streams are abstractions allowing a uniform way to read/write - * data regardless of the physical communication interface. - * - * I/O Stream offers many interfaces, see submodules for a list of all types available - * and their specificities.You can load multiple streams in the project and you can - * select the interface that must be used at runtime.Some interface type can also - * be instantiated, meaning that you can have multiple instances of an interface - * type which will be normally bound to a hardware peripheral. - * - * ## Initialization - * - * The I/O Stream core doesn't require any initialization. Instead each stream type has - * their own initialization and their own configuration. See I/O Stream specific type - * to know more about how to initialize a stream. - * - * Note that most stream will set itself as the default stream during their initialization. - * Thus the initial default stream will be the last stream initialized. - * - * ## Default system-wide stream - * - * Multiple streams can be initialized in your application and you can configure a default - * stream that must be used when no stream is specified. Also note that the default stream - * will be used when calling printf and you can change the default stream at runtime. - * The following defines should be used for the default stream: - * - * SL_IOSTREAM_STDIN - * SL_IOSTREAM_STDOUT - * SL_IOSTREAM_STDERR - * - * ## RTOS - Task's default stream - * - * In the case of an RTOS environment, each task can set its own stream. By default, the task - * stream will be set to the system_wide default stream. From your task, you can change the - * default stream assigned to your task without affecting the other tasks' stream. - * - * ## Printf - * - * I/O Stream provides third-party printf integrations. It can work with toolchain implementation - * or with the tiny printf implementation for embedded system. The printf API doesn't have an - * argument for specifying the stream to be used, so I/O Stream provides a printf API that takes - * a stream as an argument and calls the configured third-party implementation of printf. - * - * @{ - ******************************************************************************/ - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -#define SL_IOSTREAM_STDIN 0 ///< Default input stream -#define SL_IOSTREAM_STDOUT 0 ///< Default output stream -#define SL_IOSTREAM_STDERR 0 ///< Default error stream -/// @endcond - -// ----------------------------------------------------------------------------- -// Data Types - -/// @brief Struct representing iostream operations. -typedef struct { - void *context; ///< context - sl_status_t (*write)(void *context, const void *buffer, size_t buffer_length); ///< write - sl_status_t (*read)(void *context, void *buffer, size_t buffer_length, size_t *bytes_read); ///< read -} sl_iostream_t; - -/// @brief Enumeration representing the possible types of iostream instances. -SL_ENUM(sl_iostream_type_t){ - SL_IOSTREAM_TYPE_SWO = 0, ///< SWO Instance - SL_IOSTREAM_TYPE_RTT = 1, ///< RTT Instance - SL_IOSTREAM_TYPE_UART = 2, ///< USART Instance - SL_IOSTREAM_TYPE_VUART = 3, ///< Vuart - SL_IOSTREAM_TYPE_DEBUG_OUTPUT = 4, ///< Backchannel output Instance Type - SL_IOSTREAM_TYPE_LOOPBACK = 5, ///< Loopback Instance - SL_IOSTREAM_TYPE_UNDEFINED = 6, ///< Undefined Instance Type -}; - -/// @brief Struct representing an I/O Stream instance. -typedef struct { - sl_iostream_t *handle; ///< iostream instance handle. - char *name; ///< iostream instance name. - sl_iostream_type_t type; ///< iostream instance type. - uint8_t periph_id; ///< iostream peripheral id. - sl_status_t (*init)(void); ///< iostream instance init function. -} sl_iostream_instance_info_t; - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -// Special stream to be used when you want to avoid printing anything -extern sl_iostream_t sl_iostream_null; -/// @endcond - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * Set the stream as default I/O Stream. - * - * @param[in] stream I/O Stream to set as default. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_set_default(sl_iostream_t *stream); - -/***************************************************************************//** - * Get the default I/O Stream configured. - * - * @return Status result - ******************************************************************************/ -sl_iostream_t *sl_iostream_get_default(void); - -/***************************************************************************//** - * Configure the systemwide default stream. - * - * @param[in] stream I/O Stream to be used. - * - * @return Status result - ******************************************************************************/ -#if defined(SL_CATALOG_KERNEL_PRESENT) -sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream); -#else -#define sl_iostream_set_system_default sl_iostream_set_default -#endif - -/***************************************************************************//** - * Output data on a stream. - * - * @param[in] stream I/O Stream to be used. - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[in] buffer Buffer that contains the data to output. - * - * @param[in] buffer_length Data length contained in the buffer. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_write(sl_iostream_t *stream, - const void *buffer, - size_t buffer_length); - -/***************************************************************************//** - * Get data from a stream. - * - * @param[in] stream I/O Stream to be used. - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[out] buffer Buffer that contains the data to output. - * - * @param[in] buffer_length Data length contained in the buffer. - * - * @param[out] bytes_read Data length copied to the buffer. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_read(sl_iostream_t *stream, - void *buffer, - size_t buffer_length, - size_t *bytes_read); - -/***************************************************************************//** - * Print a character on stream. - * - * @param[in] stream I/O Stream to be used: - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * SL_IOSTREAM_STDERR; Default error output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[in] c Character to print - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_putchar(sl_iostream_t *stream, - char c); - -/***************************************************************************//** - * Print a character on stream. - * - * @param[in] stream I/O Stream to be used. - * SL_IOSTREAM_STDIN; Default input stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[out] c Pointer to variable that will receive the character. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_getchar(sl_iostream_t *stream, - char *c); - -/***************************************************************************//** - * Print a formated string on stream. - * - * @param[in] stream I/O Stream to be used: - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * SL_IOSTREAM_STDERR; Default error output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[in] format String that contains the text to be written. - * - * @param[in] argp A value identifying a variable arguments list. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, - const char *format, - va_list argp); - -#if defined(__GNUC__) -__attribute__((format(printf, 2, 3))) -#endif - -/***************************************************************************//** - * Print a formated string on stream. - * - * @param[in] stream I/O Stream to be used: - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * SL_IOSTREAM_STDERR; Default error output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * @param[in] format String that contains the text to be written. - * - * @param[in] ... Additional arguments. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_printf(sl_iostream_t *stream, - const char *format, - ...); - -/** @} (end addtogroup iostream) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_IOSTREAM_H +/***************************************************************************//** + * @file + * @brief IO Stream. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_H +#define SL_IOSTREAM_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "sl_enum.h" +#include "sl_status.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iostream I/O Stream + * @brief I/O Stream can be used to read/write different formats of data to various streams. + * The source files for I/O Stream platform software module are present under platform/services/iostream. + * @details + * ## Overview + * + * I/O Stream is a platform module software that provides Input/Output functionalities + * by creating streams. Streams are abstractions allowing a uniform way to read/write + * data regardless of the physical communication interface. + * + * I/O Stream offers many interfaces, see submodules for a list of all types available + * and their specificities.You can load multiple streams in the project and you can + * select the interface that must be used at runtime.Some interface type can also + * be instantiated, meaning that you can have multiple instances of an interface + * type which will be normally bound to a hardware peripheral. + * + * ## Initialization + * + * The I/O Stream core doesn't require any initialization. Instead each stream type has + * their own initialization and their own configuration. See I/O Stream specific type + * to know more about how to initialize a stream. + * + * Note that most stream will set itself as the default stream during their initialization. + * Thus the initial default stream will be the last stream initialized. + * + * ## Default system-wide stream + * + * Multiple streams can be initialized in your application and you can configure a default + * stream that must be used when no stream is specified. Also note that the default stream + * will be used when calling printf and you can change the default stream at runtime. + * The following defines should be used for the default stream: + * + * SL_IOSTREAM_STDIN + * SL_IOSTREAM_STDOUT + * SL_IOSTREAM_STDERR + * + * ## RTOS - Task's default stream + * + * In the case of an RTOS environment, each task can set its own stream. By default, the task + * stream will be set to the system_wide default stream. From your task, you can change the + * default stream assigned to your task without affecting the other tasks' stream. + * + * ## Printf + * + * I/O Stream provides third-party printf integrations. It can work with toolchain implementation + * or with the tiny printf implementation for embedded system. The printf API doesn't have an + * argument for specifying the stream to be used, so I/O Stream provides a printf API that takes + * a stream as an argument and calls the configured third-party implementation of printf. + * + * @{ + ******************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define SL_IOSTREAM_STDIN 0 ///< Default input stream +#define SL_IOSTREAM_STDOUT 0 ///< Default output stream +#define SL_IOSTREAM_STDERR 0 ///< Default error stream +/// @endcond + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Struct representing iostream operations. +typedef struct { + void *context; ///< context + sl_status_t (*write)(void *context, const void *buffer, size_t buffer_length); ///< write + sl_status_t (*read)(void *context, void *buffer, size_t buffer_length, size_t *bytes_read); ///< read +} sl_iostream_t; + +/// @brief Enumeration representing the possible types of iostream instances. +SL_ENUM(sl_iostream_type_t){ + SL_IOSTREAM_TYPE_SWO = 0, ///< SWO Instance + SL_IOSTREAM_TYPE_RTT = 1, ///< RTT Instance + SL_IOSTREAM_TYPE_UART = 2, ///< USART Instance + SL_IOSTREAM_TYPE_VUART = 3, ///< Vuart + SL_IOSTREAM_TYPE_DEBUG_OUTPUT = 4, ///< Backchannel output Instance Type + SL_IOSTREAM_TYPE_LOOPBACK = 5, ///< Loopback Instance + SL_IOSTREAM_TYPE_UNDEFINED = 6, ///< Undefined Instance Type +}; + +/// @brief Struct representing an I/O Stream instance. +typedef struct { + sl_iostream_t *handle; ///< iostream instance handle. + char *name; ///< iostream instance name. + sl_iostream_type_t type; ///< iostream instance type. + uint8_t periph_id; ///< iostream peripheral id. + sl_status_t (*init)(void); ///< iostream instance init function. +} sl_iostream_instance_info_t; + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +// Special stream to be used when you want to avoid printing anything +extern sl_iostream_t sl_iostream_null; +/// @endcond + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Set the stream as default I/O Stream. + * + * @param[in] stream I/O Stream to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_set_default(sl_iostream_t *stream); + +/***************************************************************************//** + * Get the default I/O Stream configured. + * + * @return Status result + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_default(void); + +/***************************************************************************//** + * Configure the systemwide default stream. + * + * @param[in] stream I/O Stream to be used. + * + * @return Status result + ******************************************************************************/ +#if defined(SL_CATALOG_KERNEL_PRESENT) +sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream); +#else +#define sl_iostream_set_system_default sl_iostream_set_default +#endif + +/***************************************************************************//** + * Output data on a stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] buffer Buffer that contains the data to output. + * + * @param[in] buffer_length Data length contained in the buffer. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_write(sl_iostream_t *stream, + const void *buffer, + size_t buffer_length); + +/***************************************************************************//** + * Get data from a stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[out] buffer Buffer that contains the data to output. + * + * @param[in] buffer_length Data length contained in the buffer. + * + * @param[out] bytes_read Data length copied to the buffer. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_read(sl_iostream_t *stream, + void *buffer, + size_t buffer_length, + size_t *bytes_read); + +/***************************************************************************//** + * Print a character on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] c Character to print + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_putchar(sl_iostream_t *stream, + char c); + +/***************************************************************************//** + * Print a character on stream. + * + * @param[in] stream I/O Stream to be used. + * SL_IOSTREAM_STDIN; Default input stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[out] c Pointer to variable that will receive the character. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_getchar(sl_iostream_t *stream, + char *c); + +/***************************************************************************//** + * Print a formated string on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] format String that contains the text to be written. + * + * @param[in] argp A value identifying a variable arguments list. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, + const char *format, + va_list argp); + +#if defined(__GNUC__) +__attribute__((format(printf, 2, 3))) +#endif + +/***************************************************************************//** + * Print a formated string on stream. + * + * @param[in] stream I/O Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * @param[in] format String that contains the text to be written. + * + * @param[in] ... Additional arguments. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_printf(sl_iostream_t *stream, + const char *format, + ...); + +/** @} (end addtogroup iostream) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream_rtt.h b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream_rtt.h index 26c8ca1..2c23047 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream_rtt.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/inc/sl_iostream_rtt.h @@ -1,112 +1,112 @@ -/***************************************************************************//** - * @file - * @brief IO Stream RTT Component. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_IOSTREAM_RTT_H -#define SL_IOSTREAM_RTT_H - -#include "sl_iostream.h" -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup iostream - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup iostream_rtt I/O Stream RTT - * @brief I/O Stream RTT - * @details - * ## Overview - * - * Real Time Transfer (RTT) is a bi-directional communication interface developed - * by Segger and used with J-Link module. You need to have the Segger RTT library - * in your project to use this stream. It is offered as a third-party module in - * the Silicon Labs SDK. - * - * RTT module uses a control block structure located in RAM memory with a specific - * ID so that it can be discovered when a connection is established via J-Link. - * The control block references a ring buffer for each configured channel. You can - * configure the number and size of the ring buffers at compile-time in - * SEGGER_RTT_Conf.h configuration file. Please refer to Segger's documentation - * for further information on RTT. - * - * Note that you should only use this stream in a development environment. You - * should avoid using it in production. - * - * ## Initialization - * - * The stream sets itself as the default stream at the end of the initialization - * function.You must reconfigure the default interface if you have multiple streams - * in your project else the last stream initialized will be set as the system default - * stream. - * - * ## Power manager integration - * - * Because RTT communication uses the J-link debug interface when going into EM2 or EM3, - * the system will actually go into a special Energy Mode to maintain the debug - * capabilities and the power consumption will still remain high. Therefore it is unwise - * to keep a debug interface with RTT channel open if you want to test your power - * consumption. - * - * ## Communication channel connection - * - * For connecting to the RTT channel you can use the tools provided by Segger or you - * can open a telnet session and connect to the port 19021 using your host IP - * address when the debugger is connected using USB and using J-Link debugger IP address - * when your debugger is connected over ethernet. - * - * @{ - ******************************************************************************/ - -extern sl_iostream_t *sl_iostream_rtt_handle; ///< sl_iostream_rtt_handle -extern sl_iostream_instance_info_t sl_iostream_instance_rtt_info; ///< sl_iostream_instance_rtt_info - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * RTT Stream init. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_iostream_rtt_init(void); - -/** @} (end addtogroup iostream_rtt) */ -/** @} (end addtogroup iostream) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_IOSTREAM_RTT_H +/***************************************************************************//** + * @file + * @brief IO Stream RTT Component. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_IOSTREAM_RTT_H +#define SL_IOSTREAM_RTT_H + +#include "sl_iostream.h" +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iostream + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup iostream_rtt I/O Stream RTT + * @brief I/O Stream RTT + * @details + * ## Overview + * + * Real Time Transfer (RTT) is a bi-directional communication interface developed + * by Segger and used with J-Link module. You need to have the Segger RTT library + * in your project to use this stream. It is offered as a third-party module in + * the Silicon Labs SDK. + * + * RTT module uses a control block structure located in RAM memory with a specific + * ID so that it can be discovered when a connection is established via J-Link. + * The control block references a ring buffer for each configured channel. You can + * configure the number and size of the ring buffers at compile-time in + * SEGGER_RTT_Conf.h configuration file. Please refer to Segger's documentation + * for further information on RTT. + * + * Note that you should only use this stream in a development environment. You + * should avoid using it in production. + * + * ## Initialization + * + * The stream sets itself as the default stream at the end of the initialization + * function.You must reconfigure the default interface if you have multiple streams + * in your project else the last stream initialized will be set as the system default + * stream. + * + * ## Power manager integration + * + * Because RTT communication uses the J-link debug interface when going into EM2 or EM3, + * the system will actually go into a special Energy Mode to maintain the debug + * capabilities and the power consumption will still remain high. Therefore it is unwise + * to keep a debug interface with RTT channel open if you want to test your power + * consumption. + * + * ## Communication channel connection + * + * For connecting to the RTT channel you can use the tools provided by Segger or you + * can open a telnet session and connect to the port 19021 using your host IP + * address when the debugger is connected using USB and using J-Link debugger IP address + * when your debugger is connected over ethernet. + * + * @{ + ******************************************************************************/ + +extern sl_iostream_t *sl_iostream_rtt_handle; ///< sl_iostream_rtt_handle +extern sl_iostream_instance_info_t sl_iostream_instance_rtt_info; ///< sl_iostream_instance_rtt_info + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * RTT Stream init. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_iostream_rtt_init(void); + +/** @} (end addtogroup iostream_rtt) */ +/** @} (end addtogroup iostream) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_IOSTREAM_RTT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream.c b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream.c index 3117af3..758147c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream.c @@ -1,302 +1,302 @@ -/***************************************************************************//** - * @file - * @brief IO Stream. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_iostream.h" -#include "sl_status.h" -#include "em_core.h" - -#if defined(SL_CATALOG_KERNEL_PRESENT) -#include "cmsis_os2.h" -#include "sli_cmsis_os2_ext_task_register.h" -#endif - -#if defined(SL_CATALOG_PRINTF_PRESENT) -#include "printf.h" -#else -#include -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if defined(SL_CATALOG_KERNEL_PRESENT) -#define TASK_REGISTER_ID_INVALID 0xFF -#endif - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if defined(SL_CATALOG_KERNEL_PRESENT) -static sli_task_register_id_t sli_task_register_id = TASK_REGISTER_ID_INVALID; -static sl_iostream_t *sli_iostream_system_default = NULL; -#endif -static sl_iostream_t *sli_iostream_default = NULL; - -sl_iostream_t sl_iostream_null = { - .write = NULL, - .read = NULL, - .context = NULL -}; - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ - -#if defined(SL_CATALOG_PRINTF_PRESENT) -static void stream_putchar(char character, - void *arg); -#endif - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Registers default IO stream to be used - ******************************************************************************/ -sl_status_t sl_iostream_set_default(sl_iostream_t *stream) -{ -#if defined(SL_CATALOG_KERNEL_PRESENT) - sli_task_register_id_t reg_id; - sl_status_t status; -#endif - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); -#if defined(SL_CATALOG_KERNEL_PRESENT) - if (osThreadGetId() != NULL) { - reg_id = sli_task_register_id; - if (reg_id == TASK_REGISTER_ID_INVALID) { - status = sli_osTaskRegisterNew(®_id); - EFM_ASSERT(status == SL_STATUS_OK); - sli_task_register_id = reg_id; - } - } -#endif - sli_iostream_default = stream; - CORE_EXIT_CRITICAL(); - -#if defined(SL_CATALOG_KERNEL_PRESENT) - if (osThreadGetId() != NULL) { - status = sli_osTaskRegisterSetValue(NULL, reg_id, (uint32_t)stream); - EFM_ASSERT(status == SL_STATUS_OK); - } -#endif - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Get default IO stream configured - ******************************************************************************/ -sl_iostream_t *sl_iostream_get_default(void) -{ -#if defined(SL_CATALOG_KERNEL_PRESENT) - sl_status_t status; - sli_task_register_id_t reg_id; -#endif - sl_iostream_t *stream = NULL; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); -#if defined(SL_CATALOG_KERNEL_PRESENT) - reg_id = sli_task_register_id; -#endif - stream = sli_iostream_default; - CORE_EXIT_CRITICAL(); - -#if defined(SL_CATALOG_KERNEL_PRESENT) - if (osThreadGetId() != NULL) { - if (reg_id != TASK_REGISTER_ID_INVALID) { - uint32_t reg; - - status = sli_osTaskRegisterGetValue(NULL, sli_task_register_id, ®); - EFM_ASSERT(status == SL_STATUS_OK); - - stream = (sl_iostream_t *)reg; - } - } - if (stream == NULL) { - CORE_ENTER_CRITICAL(); - stream = sli_iostream_system_default; - CORE_EXIT_CRITICAL(); - } -#endif - - return stream; -} - -/***************************************************************************//** - * Set systemwide default IO stream - ******************************************************************************/ -#if defined(SL_CATALOG_KERNEL_PRESENT) -sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream) -{ - sl_status_t status = SL_STATUS_OK; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - sli_iostream_system_default = stream; - CORE_EXIT_CRITICAL(); - return status; -} -#endif - -/***************************************************************************//** - * Stream write implementation - ******************************************************************************/ -sl_status_t sl_iostream_write(sl_iostream_t *stream, - const void *buffer, - size_t buffer_length) -{ - if (stream == SL_IOSTREAM_STDOUT) { - stream = sl_iostream_get_default(); - } - - if ((stream != NULL) && (stream->write != NULL)) { - return stream->write(stream->context, buffer, buffer_length); - } else { - return SL_STATUS_INVALID_CONFIGURATION; - } -} - -/***************************************************************************//** - * Stream read implementation - ******************************************************************************/ -sl_status_t sl_iostream_read(sl_iostream_t *stream, - void *buffer, - size_t buffer_length, - size_t *bytes_read) -{ - size_t size; - size_t *read_size = &size; - - if (stream == SL_IOSTREAM_STDIN) { - stream = sl_iostream_get_default(); - } - - if (bytes_read != NULL) { - read_size = bytes_read; - } - - if ((stream != NULL) && (stream->read != NULL)) { - return stream->read(stream->context, buffer, buffer_length, read_size); - } else { - return SL_STATUS_INVALID_CONFIGURATION; - } -} - -/***************************************************************************//** - * Stream putchar implementation - ******************************************************************************/ -sl_status_t sl_iostream_putchar(sl_iostream_t *stream, - char c) -{ - return sl_iostream_write(stream, &c, 1); -} - -/***************************************************************************//** - * Stream getchar implementation - ******************************************************************************/ -sl_status_t sl_iostream_getchar(sl_iostream_t *stream, - char *c) -{ - return sl_iostream_read(stream, c, 1, NULL); -} - -/***************************************************************************//** - * Stream vprintf implementation - ******************************************************************************/ -sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, - const char *format, - va_list argp) -{ -#if !defined(SL_CATALOG_PRINTF_PRESENT) - sl_iostream_t *default_stream; -#endif - sl_iostream_t *output_stream = stream; - sl_status_t status = SL_STATUS_OK; - int ret; - -#if defined(SL_CATALOG_PRINTF_PRESENT) - if (output_stream == SL_IOSTREAM_STDOUT) { - output_stream = sl_iostream_get_default(); - } - ret = vfctprintf(stream_putchar, output_stream, format, argp); -#else - if (output_stream == SL_IOSTREAM_STDOUT) { - default_stream = sl_iostream_get_default(); - output_stream = default_stream; - } else { - default_stream = sl_iostream_get_default(); - if (default_stream != output_stream) { - sl_iostream_set_default(output_stream); - } - } - - ret = vprintf(format, argp); - if (default_stream != output_stream) { - sl_iostream_set_default(default_stream); - } -#endif - if (ret <= 0) { - status = SL_STATUS_OBJECT_WRITE; - } - - return status; -} - -/***************************************************************************//** - * Stream printf implementation - ******************************************************************************/ -sl_status_t sl_iostream_printf(sl_iostream_t *stream, - const char *format, - ...) -{ - sl_status_t status; - va_list argp; - va_start(argp, format); - status = sl_iostream_vprintf(stream, format, argp); - va_end(argp); - return status; -} - -/***************************************************************************//** - * putchar implementation for sl_iostream_printf; called by fnctprintf() - ******************************************************************************/ -#if defined(SL_CATALOG_PRINTF_PRESENT) -static void stream_putchar(char character, - void *arg) -{ - sl_iostream_putchar((sl_iostream_t *)arg, character); -} -#endif +/***************************************************************************//** + * @file + * @brief IO Stream. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_iostream.h" +#include "sl_status.h" +#include "em_core.h" + +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "cmsis_os2.h" +#include "sli_cmsis_os2_ext_task_register.h" +#endif + +#if defined(SL_CATALOG_PRINTF_PRESENT) +#include "printf.h" +#else +#include +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_KERNEL_PRESENT) +#define TASK_REGISTER_ID_INVALID 0xFF +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_KERNEL_PRESENT) +static sli_task_register_id_t sli_task_register_id = TASK_REGISTER_ID_INVALID; +static sl_iostream_t *sli_iostream_system_default = NULL; +#endif +static sl_iostream_t *sli_iostream_default = NULL; + +sl_iostream_t sl_iostream_null = { + .write = NULL, + .read = NULL, + .context = NULL +}; + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +#if defined(SL_CATALOG_PRINTF_PRESENT) +static void stream_putchar(char character, + void *arg); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Registers default IO stream to be used + ******************************************************************************/ +sl_status_t sl_iostream_set_default(sl_iostream_t *stream) +{ +#if defined(SL_CATALOG_KERNEL_PRESENT) + sli_task_register_id_t reg_id; + sl_status_t status; +#endif + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); +#if defined(SL_CATALOG_KERNEL_PRESENT) + if (osThreadGetId() != NULL) { + reg_id = sli_task_register_id; + if (reg_id == TASK_REGISTER_ID_INVALID) { + status = sli_osTaskRegisterNew(®_id); + EFM_ASSERT(status == SL_STATUS_OK); + sli_task_register_id = reg_id; + } + } +#endif + sli_iostream_default = stream; + CORE_EXIT_CRITICAL(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) + if (osThreadGetId() != NULL) { + status = sli_osTaskRegisterSetValue(NULL, reg_id, (uint32_t)stream); + EFM_ASSERT(status == SL_STATUS_OK); + } +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Get default IO stream configured + ******************************************************************************/ +sl_iostream_t *sl_iostream_get_default(void) +{ +#if defined(SL_CATALOG_KERNEL_PRESENT) + sl_status_t status; + sli_task_register_id_t reg_id; +#endif + sl_iostream_t *stream = NULL; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); +#if defined(SL_CATALOG_KERNEL_PRESENT) + reg_id = sli_task_register_id; +#endif + stream = sli_iostream_default; + CORE_EXIT_CRITICAL(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) + if (osThreadGetId() != NULL) { + if (reg_id != TASK_REGISTER_ID_INVALID) { + uint32_t reg; + + status = sli_osTaskRegisterGetValue(NULL, sli_task_register_id, ®); + EFM_ASSERT(status == SL_STATUS_OK); + + stream = (sl_iostream_t *)reg; + } + } + if (stream == NULL) { + CORE_ENTER_CRITICAL(); + stream = sli_iostream_system_default; + CORE_EXIT_CRITICAL(); + } +#endif + + return stream; +} + +/***************************************************************************//** + * Set systemwide default IO stream + ******************************************************************************/ +#if defined(SL_CATALOG_KERNEL_PRESENT) +sl_status_t sl_iostream_set_system_default(sl_iostream_t *stream) +{ + sl_status_t status = SL_STATUS_OK; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_iostream_system_default = stream; + CORE_EXIT_CRITICAL(); + return status; +} +#endif + +/***************************************************************************//** + * Stream write implementation + ******************************************************************************/ +sl_status_t sl_iostream_write(sl_iostream_t *stream, + const void *buffer, + size_t buffer_length) +{ + if (stream == SL_IOSTREAM_STDOUT) { + stream = sl_iostream_get_default(); + } + + if ((stream != NULL) && (stream->write != NULL)) { + return stream->write(stream->context, buffer, buffer_length); + } else { + return SL_STATUS_INVALID_CONFIGURATION; + } +} + +/***************************************************************************//** + * Stream read implementation + ******************************************************************************/ +sl_status_t sl_iostream_read(sl_iostream_t *stream, + void *buffer, + size_t buffer_length, + size_t *bytes_read) +{ + size_t size; + size_t *read_size = &size; + + if (stream == SL_IOSTREAM_STDIN) { + stream = sl_iostream_get_default(); + } + + if (bytes_read != NULL) { + read_size = bytes_read; + } + + if ((stream != NULL) && (stream->read != NULL)) { + return stream->read(stream->context, buffer, buffer_length, read_size); + } else { + return SL_STATUS_INVALID_CONFIGURATION; + } +} + +/***************************************************************************//** + * Stream putchar implementation + ******************************************************************************/ +sl_status_t sl_iostream_putchar(sl_iostream_t *stream, + char c) +{ + return sl_iostream_write(stream, &c, 1); +} + +/***************************************************************************//** + * Stream getchar implementation + ******************************************************************************/ +sl_status_t sl_iostream_getchar(sl_iostream_t *stream, + char *c) +{ + return sl_iostream_read(stream, c, 1, NULL); +} + +/***************************************************************************//** + * Stream vprintf implementation + ******************************************************************************/ +sl_status_t sl_iostream_vprintf(sl_iostream_t *stream, + const char *format, + va_list argp) +{ +#if !defined(SL_CATALOG_PRINTF_PRESENT) + sl_iostream_t *default_stream; +#endif + sl_iostream_t *output_stream = stream; + sl_status_t status = SL_STATUS_OK; + int ret; + +#if defined(SL_CATALOG_PRINTF_PRESENT) + if (output_stream == SL_IOSTREAM_STDOUT) { + output_stream = sl_iostream_get_default(); + } + ret = vfctprintf(stream_putchar, output_stream, format, argp); +#else + if (output_stream == SL_IOSTREAM_STDOUT) { + default_stream = sl_iostream_get_default(); + output_stream = default_stream; + } else { + default_stream = sl_iostream_get_default(); + if (default_stream != output_stream) { + sl_iostream_set_default(output_stream); + } + } + + ret = vprintf(format, argp); + if (default_stream != output_stream) { + sl_iostream_set_default(default_stream); + } +#endif + if (ret <= 0) { + status = SL_STATUS_OBJECT_WRITE; + } + + return status; +} + +/***************************************************************************//** + * Stream printf implementation + ******************************************************************************/ +sl_status_t sl_iostream_printf(sl_iostream_t *stream, + const char *format, + ...) +{ + sl_status_t status; + va_list argp; + va_start(argp, format); + status = sl_iostream_vprintf(stream, format, argp); + va_end(argp); + return status; +} + +/***************************************************************************//** + * putchar implementation for sl_iostream_printf; called by fnctprintf() + ******************************************************************************/ +#if defined(SL_CATALOG_PRINTF_PRESENT) +static void stream_putchar(char character, + void *arg) +{ + sl_iostream_putchar((sl_iostream_t *)arg, character); +} +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream_rtt.c b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream_rtt.c index a94a8fe..6089ee6 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream_rtt.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/iostream/src/sl_iostream_rtt.c @@ -1,144 +1,144 @@ -/***************************************************************************//** - * @file - * @brief IO Stream RTT Component. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_iostream_rtt.h" -#include "SEGGER_RTT.h" -#include "sl_status.h" - -#if !defined(IOSTREAM_RTT_UP_MODE) -#define IOSTREAM_RTT_UP_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM -#endif - -#if !defined(IOSTREAM_RTT_DOWN_MODE) -#define IOSTREAM_RTT_DOWN_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM -#endif - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ - -static sl_status_t rtt_write(void *context, - const void *buffer, - size_t buffer_length); - -static sl_status_t rtt_read(void *context, - void *buffer, - size_t buffer_length, - size_t *bytes_read); - -/******************************************************************************* - ****************************** VARIABLES ********************************** - ******************************************************************************/ - -static sl_iostream_t sl_iostream_rtt = { - .read = rtt_read, - .write = rtt_write, - .context = NULL -}; - -sl_iostream_t *sl_iostream_rtt_handle = &sl_iostream_rtt; - -sl_iostream_instance_info_t sl_iostream_instance_rtt_info = { - .handle = &sl_iostream_rtt, - .name = "rtt", - .type = SL_IOSTREAM_TYPE_RTT, - .periph_id = 0, - .init = sl_iostream_rtt_init, -}; - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * RTT Stream init. - ******************************************************************************/ -sl_status_t sl_iostream_rtt_init(void) -{ - SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_UP_MODE); - SEGGER_RTT_ConfigDownBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_DOWN_MODE); - sl_iostream_set_system_default(&sl_iostream_rtt); - - return SL_STATUS_OK; -} - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * Internal RTT stream write implementation - ******************************************************************************/ -static sl_status_t rtt_write(void *context, - const void *buffer, - size_t buffer_length) -{ - uint32_t ret = 0; - sl_status_t status; - (void)context; - (void)ret; - - ret = SEGGER_RTT_Write(0, buffer, buffer_length); - -#if ((IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_TRIM) \ - || (IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_SKIP)) - status = SL_STATUS_OK; // Ignore error -#else - if (ret > 0) { - status = SL_STATUS_OK; - } else { - status = SL_STATUS_IO; - } -#endif - - return status; -} - -/***************************************************************************//** - * Internal RTT stream read implementation - ******************************************************************************/ -static sl_status_t rtt_read(void *context, - void *buffer, - size_t buffer_length, - size_t *bytes_read) -{ - sl_status_t status; - (void)context; - - *bytes_read = SEGGER_RTT_Read(0, buffer, buffer_length); - - if (*bytes_read > 0) { - status = SL_STATUS_OK; - } else { - status = SL_STATUS_EMPTY; - } - - return status; -} +/***************************************************************************//** + * @file + * @brief IO Stream RTT Component. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_iostream_rtt.h" +#include "SEGGER_RTT.h" +#include "sl_status.h" + +#if !defined(IOSTREAM_RTT_UP_MODE) +#define IOSTREAM_RTT_UP_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM +#endif + +#if !defined(IOSTREAM_RTT_DOWN_MODE) +#define IOSTREAM_RTT_DOWN_MODE SEGGER_RTT_MODE_NO_BLOCK_TRIM +#endif + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +static sl_status_t rtt_write(void *context, + const void *buffer, + size_t buffer_length); + +static sl_status_t rtt_read(void *context, + void *buffer, + size_t buffer_length, + size_t *bytes_read); + +/******************************************************************************* + ****************************** VARIABLES ********************************** + ******************************************************************************/ + +static sl_iostream_t sl_iostream_rtt = { + .read = rtt_read, + .write = rtt_write, + .context = NULL +}; + +sl_iostream_t *sl_iostream_rtt_handle = &sl_iostream_rtt; + +sl_iostream_instance_info_t sl_iostream_instance_rtt_info = { + .handle = &sl_iostream_rtt, + .name = "rtt", + .type = SL_IOSTREAM_TYPE_RTT, + .periph_id = 0, + .init = sl_iostream_rtt_init, +}; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * RTT Stream init. + ******************************************************************************/ +sl_status_t sl_iostream_rtt_init(void) +{ + SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_UP_MODE); + SEGGER_RTT_ConfigDownBuffer(0, NULL, NULL, 0, IOSTREAM_RTT_DOWN_MODE); + sl_iostream_set_system_default(&sl_iostream_rtt); + + return SL_STATUS_OK; +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Internal RTT stream write implementation + ******************************************************************************/ +static sl_status_t rtt_write(void *context, + const void *buffer, + size_t buffer_length) +{ + uint32_t ret = 0; + sl_status_t status; + (void)context; + (void)ret; + + ret = SEGGER_RTT_Write(0, buffer, buffer_length); + +#if ((IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_TRIM) \ + || (IOSTREAM_RTT_UP_MODE == SEGGER_RTT_MODE_NO_BLOCK_SKIP)) + status = SL_STATUS_OK; // Ignore error +#else + if (ret > 0) { + status = SL_STATUS_OK; + } else { + status = SL_STATUS_IO; + } +#endif + + return status; +} + +/***************************************************************************//** + * Internal RTT stream read implementation + ******************************************************************************/ +static sl_status_t rtt_read(void *context, + void *buffer, + size_t buffer_length, + size_t *bytes_read) +{ + sl_status_t status; + (void)context; + + *bytes_read = SEGGER_RTT_Read(0, buffer, buffer_length); + + if (*bytes_read > 0) { + status = SL_STATUS_OK; + } else { + status = SL_STATUS_EMPTY; + } + + return status; +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h b/locator_host/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h index 013fb81..22e0d76 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h @@ -1,87 +1,87 @@ -/***************************************************************************//** - * @file - * @brief MPU API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup mpu RAM execution disable - * @brief RAM execution disable utilities can be used to disable execution from - * RAM and other selected memory regions. - * @details - * RAM execution disable utilities are useful to protect against code injection attacks. - * These utilities make use of MPU to disable execution from RAM and other selected - * memory regions. - * - * @{ - ******************************************************************************/ - -#ifndef SL_MPU_H -#define SL_MPU_H - -#include "sl_status.h" - -#if (defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) || defined(DOXYGEN) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Configures internal SRAM as non-executable and enable MPU. - * - * @note This function configures the MPU in order to make the entire RAM as - * non-executable (with the exception of the functions marked as ramfunc). - ******************************************************************************/ -void sl_mpu_disable_execute_from_ram(void); - -/***************************************************************************//** - * Configures an address range as non-executable and enable MPU. - * - * @note Configures a MPU region in order to make an address range as - * non-executable. The memory region must have a size of at least 32 bytes. - * - * @param address_begin Beginning of memory segment. - * - * @param address_end End of memory segment. - * - * @param size Size of memory segment. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_mpu_disable_execute(uint32_t address_begin, - uint32_t address_end, - uint32_t size); - -#ifdef __cplusplus -} -#endif - -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ -#endif /* SL_MPU_H */ - -/** @} (end addtogroup mpu) */ +/***************************************************************************//** + * @file + * @brief MPU API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup mpu RAM execution disable + * @brief RAM execution disable utilities can be used to disable execution from + * RAM and other selected memory regions. + * @details + * RAM execution disable utilities are useful to protect against code injection attacks. + * These utilities make use of MPU to disable execution from RAM and other selected + * memory regions. + * + * @{ + ******************************************************************************/ + +#ifndef SL_MPU_H +#define SL_MPU_H + +#include "sl_status.h" + +#if (defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) || defined(DOXYGEN) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Configures internal SRAM as non-executable and enable MPU. + * + * @note This function configures the MPU in order to make the entire RAM as + * non-executable (with the exception of the functions marked as ramfunc). + ******************************************************************************/ +void sl_mpu_disable_execute_from_ram(void); + +/***************************************************************************//** + * Configures an address range as non-executable and enable MPU. + * + * @note Configures a MPU region in order to make an address range as + * non-executable. The memory region must have a size of at least 32 bytes. + * + * @param address_begin Beginning of memory segment. + * + * @param address_end End of memory segment. + * + * @param size Size of memory segment. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +#endif /* SL_MPU_H */ + +/** @} (end addtogroup mpu) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c b/locator_host/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c index f0198f2..0d56019 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c @@ -1,403 +1,403 @@ -/***************************************************************************//** - * @file - * @brief MPU API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_device.h" - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "sl_common.h" -#include "em_core.h" -#include "sl_mpu.h" -#include -#include - -#define MPU_RBAR_VALUE ARM_MPU_RBAR(0u, ARM_MPU_SH_NON, 0, 1, 1) - -// ARM memory map SRAM location and size. -#define MPU_ARM_SRAM_MEM_BASE 0x20000000 -#define MPU_ARM_SRAM_MEM_SIZE 0x20000000 - -// Number of sub-regions per MPU region. -#define MPU_SUBREGION_NBR 8u - -// Minimum size of a MPU region to use sub-regions disable feature. -#define MPU_SUBREGION_USE_MIN_SIZE 256u - -// Pre-defined MPU regions. -#define MPU_RAM_BACKGROUND_XN_REGION_NBR 0u -#define MPU_RAM_FUNCTION_REGION_NBR 1u - -#if defined(__ICCARM__) -// iccarm -#pragma section = ".textrw" -#define RAMFUNC_SECTION_BEGIN ((uint32_t)(uint32_t *)__section_begin(".textrw")) -#define RAMFUNC_SECTION_END ((uint32_t)(uint32_t *)__section_end(".textrw")) -#define RAMFUNC_SECTION_SIZE __section_size(".textrw") - -#elif defined(__GNUC__) -// armgcc -extern uint32_t __ram_func_section_start; -extern uint32_t __ram_func_section_end; -#define RAMFUNC_SECTION_BEGIN (uint32_t) &__ram_func_section_start -#define RAMFUNC_SECTION_END (uint32_t) &__ram_func_section_end -#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) - -#elif defined(__CC_ARM) -// armcc -// The section name in the armcc scatter file must be "ram_code". -extern uint32_t ram_code$$Base; -extern uint32_t ram_code$$Limit; -#define RAMFUNC_SECTION_BEGIN (uint32_t) &ram_code$$Base -#define RAMFUNC_SECTION_END (uint32_t) &ram_code$$Limit -#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) - -#endif - -#ifndef ARM_MPU_ARMV8_H -static uint32_t mpu_round_up_next_pwr2(uint32_t nbr); -static uint8_t mpu_region_size_encode(uint32_t region_size); -static void mpu_compute_region_data(uint32_t section_begin, - uint32_t section_end, - uint32_t section_size, - uint32_t *mpu_region_begin, - uint32_t *mpu_region_end, - uint32_t *mpu_region_size); - -#endif - -static uint32_t region_nbr = 0; - -/**************************************************************************//** - *****************************************************************************/ -void sl_mpu_disable_execute_from_ram(void) -{ - uint32_t mpu_region_begin = 0u; - uint32_t mpu_region_end = 0u; - - ARM_MPU_Disable(); - -#ifdef ARM_MPU_ARMV8_H - uint32_t rbar; - - // Region end address LSB are always considered 1F. - mpu_region_begin = MPU_ARM_SRAM_MEM_BASE; - mpu_region_end = (RAMFUNC_SECTION_SIZE > 0) ? (RAMFUNC_SECTION_BEGIN & MPU_RBAR_BASE_Msk) - 32u - : (MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE); - - ARM_MPU_SetMemAttr(0, ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), 0)); - - if (mpu_region_begin <= mpu_region_end) { - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); - region_nbr++; - } - - if (RAMFUNC_SECTION_SIZE > 0u) { - // Region end address LSB are always considered 1F. - mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; - mpu_region_end = MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE - 32u; - - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); - region_nbr++; - } -#else - uint8_t region_size_encoded; - uint32_t mpu_region_size; - - (void) mpu_region_begin; - (void) mpu_region_end; - - // Set background RAM region as execute never - region_size_encoded = mpu_region_size_encode(MPU_ARM_SRAM_MEM_SIZE); - ARM_MPU_SetRegionEx(region_nbr, - MPU_ARM_SRAM_MEM_BASE, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_XN_Msk - | MPU_RASR_ENABLE_Msk); - region_nbr++; - - // Set RAM functions region as executable - if (RAMFUNC_SECTION_SIZE > 0u) { - uint32_t sr_size; - uint8_t srd_msk; - - mpu_compute_region_data(RAMFUNC_SECTION_BEGIN, - RAMFUNC_SECTION_END, - RAMFUNC_SECTION_SIZE, - &mpu_region_begin, - &mpu_region_end, - &mpu_region_size); - - // Compute sub-region Disable (SRD) mask - sr_size = mpu_region_size / MPU_SUBREGION_NBR; - // Check if sr_size is zero to satisfy MISRA - sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; - srd_msk = (uint8_t)((1u << ((mpu_region_end - RAMFUNC_SECTION_END) / sr_size)) - 1u); - srd_msk = (uint8_t)(srd_msk << (((RAMFUNC_SECTION_END - mpu_region_begin - 1u) / sr_size) + 1u)); - srd_msk |= (1u << ((RAMFUNC_SECTION_BEGIN - mpu_region_begin) / sr_size)) - 1u; - - region_size_encoded = mpu_region_size_encode(mpu_region_size); - ARM_MPU_SetRegionEx(region_nbr, - mpu_region_begin, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_ENABLE_Msk - | (srd_msk << MPU_RASR_SRD_Pos)); - region_nbr++; - } -#endif - - // Enable MPU with default background region - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - __DSB(); - __ISB(); -} - -/**************************************************************************//** - * Enables simplified MPU driver. Configures memory address as non-executable. - *****************************************************************************/ -sl_status_t sl_mpu_disable_execute(uint32_t address_begin, - uint32_t address_end, - uint32_t size) -{ - uint32_t mpu_region_begin = 0u; - uint32_t mpu_region_end = 0u; - sl_status_t status = SL_STATUS_OK; - - ARM_MPU_Disable(); - -#ifdef ARM_MPU_ARMV8_H - uint32_t rbar; - uint8_t is_overlapping = 0u; - uint32_t prev_base_address = 0u; - uint32_t prev_limit_address = 0u; - - // Size of memory region must be 32 bytes or more. - if (size >= 32u) { - // Round inside the memory region, if address is not align on 32 bytes. - mpu_region_begin = ((address_begin % 32u) == 0u) ? address_begin - : (address_begin + (32u - (address_begin % 32u))); - - // Round inside the memory region, if address is not align on 32 bytes. - mpu_region_end = ((address_end % 32u) == 0u) ? address_end - : (address_end - (address_end % 32u)); - - // The scanning to check the overlapping region - for (uint8_t index_region = 0; index_region < region_nbr; index_region++) { - // Set to the previous region number - MPU->RNR = index_region; - - // Read the base address that was configured by the region number register before - prev_base_address = (MPU->RBAR & MPU_RBAR_BASE_Msk); - // Read the limit address that was configured by the region number register before - prev_limit_address = (MPU->RLAR & MPU_RLAR_LIMIT_Msk); - - // Check the overlapping region - if ((mpu_region_begin == prev_base_address) && (mpu_region_end == prev_limit_address)) { - // The new region is the same as the previous region - is_overlapping = 1; - status = SL_STATUS_OK; - } else if (!((mpu_region_begin > prev_limit_address) || (mpu_region_end < prev_base_address))) { - // The new region is invalid - is_overlapping = 1; - status = SL_STATUS_INVALID_RANGE; - } - - if (is_overlapping == 1) { - break; - } - - MPU->RNR &= ~MPU_RNR_REGION_Msk; - } - - if (!is_overlapping) { - // Device memory type non Gathering, non Re-ordering, Early Write Acknowledgment - ARM_MPU_SetMemAttr(1, ARM_MPU_ATTR_DEVICE_nGnRE); - - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = ARM_MPU_RBAR(0u, 0u, 0u, 1u, 1u) | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 1u)); - region_nbr++; - } - } -#else - uint8_t region_size_encoded; - uint32_t mpu_region_size; - uint32_t sr_size; - uint8_t srd_msk; - - (void) mpu_region_begin; - (void) mpu_region_end; - - mpu_compute_region_data(address_begin, - address_end, - size, - &mpu_region_begin, - &mpu_region_end, - &mpu_region_size); - - // Compute sub-region Disable (SRD) mask - sr_size = mpu_region_size / MPU_SUBREGION_NBR; - // Check if sr_size is zero to satisfy MISRA - sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; - srd_msk = (uint8_t)((1u << (((mpu_region_end - address_end) + (sr_size - 1)) / sr_size)) - 1u); - srd_msk = (uint8_t)(srd_msk << ((address_end - mpu_region_begin - 1u) / sr_size)); - srd_msk |= (1u << (((address_begin - mpu_region_begin) + (sr_size - 1)) / sr_size)) - 1u; - - if (srd_msk == 0xFF) { - return SL_STATUS_INVALID_RANGE; - } - - // Set region as execute never. - region_size_encoded = mpu_region_size_encode(mpu_region_size); - ARM_MPU_SetRegionEx(region_nbr, - mpu_region_begin, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_XN_Msk - | MPU_RASR_ENABLE_Msk - | (srd_msk << MPU_RASR_SRD_Pos)); - region_nbr++; -#endif - - // Enable MPU with default background region - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - __DSB(); - __ISB(); - - return status; -} - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Rounds up given number to next power of 2. - * - * @param nbr Number to round-up to next power of 2. - *****************************************************************************/ -static uint32_t mpu_round_up_next_pwr2(uint32_t nbr) -{ - nbr--; - nbr |= nbr >> 1; - nbr |= nbr >> 2; - nbr |= nbr >> 4; - nbr |= nbr >> 8; - nbr |= nbr >> 16; - nbr++; - - return nbr; -} -#endif - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Encode region size in RASR register REGION size field format. - * - * @param region_size Size of region. - *****************************************************************************/ -static uint8_t mpu_region_size_encode(uint32_t region_size) -{ - return (uint8_t)(30u - __CLZ(region_size)); -} -#endif - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Compute region size. - * - * @param section_begin Section begin address. - * - * @param section_end Section end address. - * - * @param section_size Size of section. - * - * @param mpu_region_begin Pointer to a region begin variable. - * - * @param mpu_region_end Pointer to a region end variable. - * - * @param mpu_region_size Pointer to a region size variable. - *****************************************************************************/ -static void mpu_compute_region_data(uint32_t section_begin, - uint32_t section_end, - uint32_t section_size, - uint32_t *mpu_region_begin, - uint32_t *mpu_region_end, - uint32_t *mpu_region_size) -{ - uint32_t region_begin; - uint32_t region_end; - uint32_t region_size; - - // Compute MPU region size and begin address - region_size = mpu_round_up_next_pwr2(section_size); - region_size = (region_size < MPU_SUBREGION_USE_MIN_SIZE) ? MPU_SUBREGION_USE_MIN_SIZE : region_size; - - region_begin = section_begin & ~(region_size - 1u); - region_end = region_begin + region_size; - - while (region_end < section_end) { - region_size *= 2u; - region_begin = section_begin & ~(region_size - 1u); - region_end = region_begin + region_size; - } - - *mpu_region_begin = region_begin; - *mpu_region_end = region_end; - *mpu_region_size = region_size; -} -#endif - -#if __CORTEX_M != (0u) -/**************************************************************************//** - * MemManage default exception handler. Reset target. - *****************************************************************************/ -__WEAK void mpu_fault_handler(void) -{ - // Force fail assert to trigger reset - __NVIC_SystemReset(); -} - -/**************************************************************************//** - * MemManage exception handler. - *****************************************************************************/ -void MemManage_Handler(void) -{ - mpu_fault_handler(); -} -#endif - -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +/***************************************************************************//** + * @file + * @brief MPU API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "sl_common.h" +#include "em_core.h" +#include "sl_mpu.h" +#include +#include + +#define MPU_RBAR_VALUE ARM_MPU_RBAR(0u, ARM_MPU_SH_NON, 0, 1, 1) + +// ARM memory map SRAM location and size. +#define MPU_ARM_SRAM_MEM_BASE 0x20000000 +#define MPU_ARM_SRAM_MEM_SIZE 0x20000000 + +// Number of sub-regions per MPU region. +#define MPU_SUBREGION_NBR 8u + +// Minimum size of a MPU region to use sub-regions disable feature. +#define MPU_SUBREGION_USE_MIN_SIZE 256u + +// Pre-defined MPU regions. +#define MPU_RAM_BACKGROUND_XN_REGION_NBR 0u +#define MPU_RAM_FUNCTION_REGION_NBR 1u + +#if defined(__ICCARM__) +// iccarm +#pragma section = ".textrw" +#define RAMFUNC_SECTION_BEGIN ((uint32_t)(uint32_t *)__section_begin(".textrw")) +#define RAMFUNC_SECTION_END ((uint32_t)(uint32_t *)__section_end(".textrw")) +#define RAMFUNC_SECTION_SIZE __section_size(".textrw") + +#elif defined(__GNUC__) +// armgcc +extern uint32_t __ram_func_section_start; +extern uint32_t __ram_func_section_end; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &__ram_func_section_start +#define RAMFUNC_SECTION_END (uint32_t) &__ram_func_section_end +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#elif defined(__CC_ARM) +// armcc +// The section name in the armcc scatter file must be "ram_code". +extern uint32_t ram_code$$Base; +extern uint32_t ram_code$$Limit; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &ram_code$$Base +#define RAMFUNC_SECTION_END (uint32_t) &ram_code$$Limit +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#endif + +#ifndef ARM_MPU_ARMV8_H +static uint32_t mpu_round_up_next_pwr2(uint32_t nbr); +static uint8_t mpu_region_size_encode(uint32_t region_size); +static void mpu_compute_region_data(uint32_t section_begin, + uint32_t section_end, + uint32_t section_size, + uint32_t *mpu_region_begin, + uint32_t *mpu_region_end, + uint32_t *mpu_region_size); + +#endif + +static uint32_t region_nbr = 0; + +/**************************************************************************//** + *****************************************************************************/ +void sl_mpu_disable_execute_from_ram(void) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + + ARM_MPU_Disable(); + +#ifdef ARM_MPU_ARMV8_H + uint32_t rbar; + + // Region end address LSB are always considered 1F. + mpu_region_begin = MPU_ARM_SRAM_MEM_BASE; + mpu_region_end = (RAMFUNC_SECTION_SIZE > 0) ? (RAMFUNC_SECTION_BEGIN & MPU_RBAR_BASE_Msk) - 32u + : (MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE); + + ARM_MPU_SetMemAttr(0, ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), 0)); + + if (mpu_region_begin <= mpu_region_end) { + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); + region_nbr++; + } + + if (RAMFUNC_SECTION_SIZE > 0u) { + // Region end address LSB are always considered 1F. + mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; + mpu_region_end = MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE - 32u; + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); + region_nbr++; + } +#else + uint8_t region_size_encoded; + uint32_t mpu_region_size; + + (void) mpu_region_begin; + (void) mpu_region_end; + + // Set background RAM region as execute never + region_size_encoded = mpu_region_size_encode(MPU_ARM_SRAM_MEM_SIZE); + ARM_MPU_SetRegionEx(region_nbr, + MPU_ARM_SRAM_MEM_BASE, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_XN_Msk + | MPU_RASR_ENABLE_Msk); + region_nbr++; + + // Set RAM functions region as executable + if (RAMFUNC_SECTION_SIZE > 0u) { + uint32_t sr_size; + uint8_t srd_msk; + + mpu_compute_region_data(RAMFUNC_SECTION_BEGIN, + RAMFUNC_SECTION_END, + RAMFUNC_SECTION_SIZE, + &mpu_region_begin, + &mpu_region_end, + &mpu_region_size); + + // Compute sub-region Disable (SRD) mask + sr_size = mpu_region_size / MPU_SUBREGION_NBR; + // Check if sr_size is zero to satisfy MISRA + sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; + srd_msk = (uint8_t)((1u << ((mpu_region_end - RAMFUNC_SECTION_END) / sr_size)) - 1u); + srd_msk = (uint8_t)(srd_msk << (((RAMFUNC_SECTION_END - mpu_region_begin - 1u) / sr_size) + 1u)); + srd_msk |= (1u << ((RAMFUNC_SECTION_BEGIN - mpu_region_begin) / sr_size)) - 1u; + + region_size_encoded = mpu_region_size_encode(mpu_region_size); + ARM_MPU_SetRegionEx(region_nbr, + mpu_region_begin, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_ENABLE_Msk + | (srd_msk << MPU_RASR_SRD_Pos)); + region_nbr++; + } +#endif + + // Enable MPU with default background region + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); +} + +/**************************************************************************//** + * Enables simplified MPU driver. Configures memory address as non-executable. + *****************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + sl_status_t status = SL_STATUS_OK; + + ARM_MPU_Disable(); + +#ifdef ARM_MPU_ARMV8_H + uint32_t rbar; + uint8_t is_overlapping = 0u; + uint32_t prev_base_address = 0u; + uint32_t prev_limit_address = 0u; + + // Size of memory region must be 32 bytes or more. + if (size >= 32u) { + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_begin = ((address_begin % 32u) == 0u) ? address_begin + : (address_begin + (32u - (address_begin % 32u))); + + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_end = ((address_end % 32u) == 0u) ? address_end + : (address_end - (address_end % 32u)); + + // The scanning to check the overlapping region + for (uint8_t index_region = 0; index_region < region_nbr; index_region++) { + // Set to the previous region number + MPU->RNR = index_region; + + // Read the base address that was configured by the region number register before + prev_base_address = (MPU->RBAR & MPU_RBAR_BASE_Msk); + // Read the limit address that was configured by the region number register before + prev_limit_address = (MPU->RLAR & MPU_RLAR_LIMIT_Msk); + + // Check the overlapping region + if ((mpu_region_begin == prev_base_address) && (mpu_region_end == prev_limit_address)) { + // The new region is the same as the previous region + is_overlapping = 1; + status = SL_STATUS_OK; + } else if (!((mpu_region_begin > prev_limit_address) || (mpu_region_end < prev_base_address))) { + // The new region is invalid + is_overlapping = 1; + status = SL_STATUS_INVALID_RANGE; + } + + if (is_overlapping == 1) { + break; + } + + MPU->RNR &= ~MPU_RNR_REGION_Msk; + } + + if (!is_overlapping) { + // Device memory type non Gathering, non Re-ordering, Early Write Acknowledgment + ARM_MPU_SetMemAttr(1, ARM_MPU_ATTR_DEVICE_nGnRE); + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = ARM_MPU_RBAR(0u, 0u, 0u, 1u, 1u) | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 1u)); + region_nbr++; + } + } +#else + uint8_t region_size_encoded; + uint32_t mpu_region_size; + uint32_t sr_size; + uint8_t srd_msk; + + (void) mpu_region_begin; + (void) mpu_region_end; + + mpu_compute_region_data(address_begin, + address_end, + size, + &mpu_region_begin, + &mpu_region_end, + &mpu_region_size); + + // Compute sub-region Disable (SRD) mask + sr_size = mpu_region_size / MPU_SUBREGION_NBR; + // Check if sr_size is zero to satisfy MISRA + sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; + srd_msk = (uint8_t)((1u << (((mpu_region_end - address_end) + (sr_size - 1)) / sr_size)) - 1u); + srd_msk = (uint8_t)(srd_msk << ((address_end - mpu_region_begin - 1u) / sr_size)); + srd_msk |= (1u << (((address_begin - mpu_region_begin) + (sr_size - 1)) / sr_size)) - 1u; + + if (srd_msk == 0xFF) { + return SL_STATUS_INVALID_RANGE; + } + + // Set region as execute never. + region_size_encoded = mpu_region_size_encode(mpu_region_size); + ARM_MPU_SetRegionEx(region_nbr, + mpu_region_begin, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_XN_Msk + | MPU_RASR_ENABLE_Msk + | (srd_msk << MPU_RASR_SRD_Pos)); + region_nbr++; +#endif + + // Enable MPU with default background region + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); + + return status; +} + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Rounds up given number to next power of 2. + * + * @param nbr Number to round-up to next power of 2. + *****************************************************************************/ +static uint32_t mpu_round_up_next_pwr2(uint32_t nbr) +{ + nbr--; + nbr |= nbr >> 1; + nbr |= nbr >> 2; + nbr |= nbr >> 4; + nbr |= nbr >> 8; + nbr |= nbr >> 16; + nbr++; + + return nbr; +} +#endif + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Encode region size in RASR register REGION size field format. + * + * @param region_size Size of region. + *****************************************************************************/ +static uint8_t mpu_region_size_encode(uint32_t region_size) +{ + return (uint8_t)(30u - __CLZ(region_size)); +} +#endif + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Compute region size. + * + * @param section_begin Section begin address. + * + * @param section_end Section end address. + * + * @param section_size Size of section. + * + * @param mpu_region_begin Pointer to a region begin variable. + * + * @param mpu_region_end Pointer to a region end variable. + * + * @param mpu_region_size Pointer to a region size variable. + *****************************************************************************/ +static void mpu_compute_region_data(uint32_t section_begin, + uint32_t section_end, + uint32_t section_size, + uint32_t *mpu_region_begin, + uint32_t *mpu_region_end, + uint32_t *mpu_region_size) +{ + uint32_t region_begin; + uint32_t region_end; + uint32_t region_size; + + // Compute MPU region size and begin address + region_size = mpu_round_up_next_pwr2(section_size); + region_size = (region_size < MPU_SUBREGION_USE_MIN_SIZE) ? MPU_SUBREGION_USE_MIN_SIZE : region_size; + + region_begin = section_begin & ~(region_size - 1u); + region_end = region_begin + region_size; + + while (region_end < section_end) { + region_size *= 2u; + region_begin = section_begin & ~(region_size - 1u); + region_end = region_begin + region_size; + } + + *mpu_region_begin = region_begin; + *mpu_region_end = region_end; + *mpu_region_size = region_size; +} +#endif + +#if __CORTEX_M != (0u) +/**************************************************************************//** + * MemManage default exception handler. Reset target. + *****************************************************************************/ +__WEAK void mpu_fault_handler(void) +{ + // Force fail assert to trigger reset + __NVIC_SystemReset(); +} + +/**************************************************************************//** + * MemManage exception handler. + *****************************************************************************/ +void MemManage_Handler(void) +{ + mpu_fault_handler(); +} +#endif + +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/inc/sl_ram_interrupt_vector_init.h b/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/inc/sl_ram_interrupt_vector_init.h index 706e887..b857630 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/inc/sl_ram_interrupt_vector_init.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/inc/sl_ram_interrupt_vector_init.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief RAM Interrupt vector init API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup ram_interrupt_vector_init RAM interrupt vector initialization - * @brief Simple utility to move the interrupt vector table to RAM. - * - * @details - * This utility will modify the VTOR register to point to a vector table - * located in RAM. The original content of the compiled interrupt vector - * table located in flash is copied in the RAM table. - * - * @{ - ******************************************************************************/ - -#ifndef SL_RAM_INTERRUPT_VECTOR_INIT_H -#define SL_RAM_INTERRUPT_VECTOR_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Configures the interrupt vector pointer (VTOR) to point to a vector table - * in RAM - * - * @note This function is a wrapper around CORE_InitNvicVectorTable function. - * The actual interrupt vector's content is copied into the RAM table - * defined in the source file of the function, and the VTOR pointer - * is set to this new table. - ******************************************************************************/ - -void sl_ram_interrupt_vector_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SL_RAM_INTERRUPT_VECTOR_INIT_H */ - -/** @} (end addtogroup ram_interrupt_vector_init) */ +/***************************************************************************//** + * @file + * @brief RAM Interrupt vector init API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup ram_interrupt_vector_init RAM interrupt vector initialization + * @brief Simple utility to move the interrupt vector table to RAM. + * + * @details + * This utility will modify the VTOR register to point to a vector table + * located in RAM. The original content of the compiled interrupt vector + * table located in flash is copied in the RAM table. + * + * @{ + ******************************************************************************/ + +#ifndef SL_RAM_INTERRUPT_VECTOR_INIT_H +#define SL_RAM_INTERRUPT_VECTOR_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Configures the interrupt vector pointer (VTOR) to point to a vector table + * in RAM + * + * @note This function is a wrapper around CORE_InitNvicVectorTable function. + * The actual interrupt vector's content is copied into the RAM table + * defined in the source file of the function, and the VTOR pointer + * is set to this new table. + ******************************************************************************/ + +void sl_ram_interrupt_vector_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SL_RAM_INTERRUPT_VECTOR_INIT_H */ + +/** @} (end addtogroup ram_interrupt_vector_init) */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c b/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c index 6e1fe71..16b052f 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief RAM interrupt vector initialization implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" -#include "sl_common.h" -#include "em_core.h" -#include "stddef.h" - -#define IRQ_TABLE_SIZE (EXT_IRQ_COUNT + 16) -//if table is larger than 256 bytes, align to 512 -#if IRQ_TABLE_SIZE > 64 -#define IRQ_TABLE_ALIGNMENT 512 -#else -#define IRQ_TABLE_ALIGNMENT 256 -#endif - -typedef void (*vectors_irq_func_ptr)(void); - -__ALIGNED(IRQ_TABLE_ALIGNMENT) vectors_irq_func_ptr gecko_vector_table[IRQ_TABLE_SIZE] = { 0 }; - -void sl_ram_interrupt_vector_init(void) -{ - vectors_irq_func_ptr *user_vector_table = (vectors_irq_func_ptr*)SCB->VTOR; - - //Initialize new table in RAM if not already initialized - if (((uint32_t)user_vector_table < RAM_MEM_BASE) - || ((uint32_t)user_vector_table >= (RAM_MEM_BASE + RAM_MEM_SIZE))) { - CORE_InitNvicVectorTable((uint32_t*)user_vector_table, IRQ_TABLE_SIZE, (uint32_t*) gecko_vector_table, IRQ_TABLE_SIZE, NULL, false); - } -} +/***************************************************************************//** + * @file + * @brief RAM interrupt vector initialization implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#include "sl_common.h" +#include "em_core.h" +#include "stddef.h" + +#define IRQ_TABLE_SIZE (EXT_IRQ_COUNT + 16) +//if table is larger than 256 bytes, align to 512 +#if IRQ_TABLE_SIZE > 64 +#define IRQ_TABLE_ALIGNMENT 512 +#else +#define IRQ_TABLE_ALIGNMENT 256 +#endif + +typedef void (*vectors_irq_func_ptr)(void); + +__ALIGNED(IRQ_TABLE_ALIGNMENT) vectors_irq_func_ptr gecko_vector_table[IRQ_TABLE_SIZE] = { 0 }; + +void sl_ram_interrupt_vector_init(void) +{ + vectors_irq_func_ptr *user_vector_table = (vectors_irq_func_ptr*)SCB->VTOR; + + //Initialize new table in RAM if not already initialized + if (((uint32_t)user_vector_table < RAM_MEM_BASE) + || ((uint32_t)user_vector_table >= (RAM_MEM_BASE + RAM_MEM_SIZE))) { + CORE_InitNvicVectorTable((uint32_t*)user_vector_table, IRQ_TABLE_SIZE, (uint32_t*) gecko_vector_table, IRQ_TABLE_SIZE, NULL, false); + } +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h index d45f2ae..78c2307 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h @@ -1,1131 +1,1131 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup sleeptimer Sleep Timer - * @{ - ******************************************************************************/ - -#ifndef SL_SLEEPTIMER_H -#define SL_SLEEPTIMER_H - -#include -#include -#include -#include "sl_status.h" -#include "sl_common.h" - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -#define SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG (0x01) -#define SL_SLEEPTIMER_ANY_FLAG (0xFF) - -#define SLEEPTIMER_ENUM(name) typedef uint8_t name; enum name##_enum - -/// @endcond - -/// Timestamp, wall clock time in seconds. -typedef uint32_t sl_sleeptimer_timestamp_t; - -// Timestamp, 64 bits wall clock in seconds. -typedef uint64_t sl_sleeptimer_timestamp_64_t; ///< sl sleeptimer timestamp 64 t - -/// Time zone offset from UTC(second). -typedef int32_t sl_sleeptimer_time_zone_offset_t; - -// Forward declaration -typedef struct sl_sleeptimer_timer_handle sl_sleeptimer_timer_handle_t; - -/***************************************************************************//** - * Typedef for the user supplied callback function which is called when - * a timer expires. - * - * @param handle The timer handle. - * - * @param data An extra parameter for the user application. - ******************************************************************************/ -typedef void (*sl_sleeptimer_timer_callback_t)(sl_sleeptimer_timer_handle_t *handle, void *data); - -/// @brief Timer structure for sleeptimer -struct sl_sleeptimer_timer_handle { - void *callback_data; ///< User data to pass to callback function. - uint8_t priority; ///< Priority of timer. - uint16_t option_flags; ///< Option flags. - sl_sleeptimer_timer_handle_t *next; ///< Pointer to next element in list. - sl_sleeptimer_timer_callback_t callback; ///< Function to call when timer expires. - uint32_t timeout_periodic; ///< Periodic timeout. - uint32_t delta; ///< Delay relative to previous element in list. - uint32_t timeout_expected_tc; ///< Expected tick count of the next timeout (only used for periodic timer). - uint16_t conversion_error; ///< The error when converting ms to ticks (thousandths of ticks) - uint16_t accumulated_error; ///< Accumulated conversion error (thousandths of ticks) -}; - -/// @brief Month enum. -SLEEPTIMER_ENUM(sl_sleeptimer_month_t) { - MONTH_JANUARY = 0, - MONTH_FEBRUARY = 1, - MONTH_MARCH = 2, - MONTH_APRIL = 3, - MONTH_MAY = 4, - MONTH_JUNE = 5, - MONTH_JULY = 6, - MONTH_AUGUST = 7, - MONTH_SEPTEMBER = 8, - MONTH_OCTOBER = 9, - MONTH_NOVEMBER = 10, - MONTH_DECEMBER = 11, -}; - -/// @brief Week Day enum. -SLEEPTIMER_ENUM(sl_sleeptimer_weekDay_t) { - DAY_SUNDAY = 0, - DAY_MONDAY = 1, - DAY_TUESDAY = 2, - DAY_WEDNESDAY = 3, - DAY_THURSDAY = 4, - DAY_FRIDAY = 5, - DAY_SATURDAY = 6, -}; - -/// @brief Time and Date structure. -typedef struct time_date { - uint8_t sec; ///< Second (0-59) - uint8_t min; ///< Minute of month (0-59) - uint8_t hour; ///< Hour (0-23) - uint8_t month_day; ///< Day of month (1-31) - sl_sleeptimer_month_t month; ///< Month (0-11) - uint16_t year; ///< Year, based on a 1900 Epoch. - sl_sleeptimer_weekDay_t day_of_week; ///< Day of week (0-6) - uint16_t day_of_year; ///< Day of year (1-366) - sl_sleeptimer_time_zone_offset_t time_zone; ///< Offset, in seconds, from UTC -} sl_sleeptimer_date_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Initializes the Sleeptimer. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_init(void); - -/***************************************************************************//** - * Starts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Starts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer periodic timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer periodic timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Stops a timer. - * - * @param handle Pointer to handle to timer. - * - * @return - ******************************************************************************/ -sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); - -/***************************************************************************//** - * Gets the status of a timer. - * - * @param handle Pointer to handle to timer. - * @param running Pointer to the status of the timer. - * - * @note A non periodic timer is considered not running during its callback. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, - bool *running); - -/***************************************************************************//** - * Gets remaining time until timer expires. - * - * @param handle Pointer to handle to timer. - * @param time Time left in timer ticks. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, - uint32_t *time); - -/**************************************************************************//** - * Gets the time remaining until the first timer with the matching set of flags - * expires. - * - * @param option_flags Set of flags to match: - * - SL_SLEEPTIMER_ANY_TIMER_FLAG - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * - * @param time_remaining Time left in timer ticks. - * - * @return 0 if successful. Error code otherwise. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, - uint32_t *time_remaining); - -/***************************************************************************//** - * Gets current 32 bits global tick count. - * - * @return Current tick count. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_tick_count(void); - -/***************************************************************************//** - * Gets current 64 bits global tick count. - * - * @return Current tick count. - ******************************************************************************/ -uint64_t sl_sleeptimer_get_tick_count64(void); - -/***************************************************************************//** - * Get timer frequency. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_timer_frequency(void); - -/***************************************************************************//** - * Converts a Unix timestamp into a date. - * - * @param time 32 bit Unix timestamp to convert. - * @param time_zone Offset from UTC in second. - * @param date Pointer to converted date. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Converts a 64 bit Unix timestamp into a date. - * - * @param time 64 bit Unix timestamp to convert. - * @param time_zone Offset from UTC in second. - * @param date Pointer to converted date. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Converts a date into a Unix timestamp. - * - * @param date Pointer to date to convert. - * @param time Pointer to converted 32 bit Unix timestamp. - * - * @return 0 if successful. Error code otherwise. - * - * @note Dates are based on the Unix time representation. - * Range of dates supported : - * - January 1, 1970, 00:00:00 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Converts a date into a 64 bit timestamp. - * - * @param date Pointer to date to convert. - * @param time Pointer to converted 64 bit Unix timestamp. - * - * @return 0 if successful. Error code otherwise. - * - * @note Dates are based on the 64 bit Unix time representation. - * Range of dates supported : - * - January 1, 1900, 00:00:00 to December 31, 11899 23:59:59. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_64_t *time); - -/***************************************************************************//** - * Convert date to string. - * - * @param str Output string. - * @param size Size of the input array. - * @param format The format specification character. - * @param date Pointer to date structure. - * - * @return 0 if error. Number of character in the output string. - * - * @note Refer strftime() from UNIX. - * http://man7.org/linux/man-pages/man3/strftime.3.html - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -uint32_t sl_sleeptimer_convert_date_to_str(char *str, - size_t size, - const uint8_t *format, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Sets time zone offset. - * - * @param offset Time zone offset, in seconds. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - ******************************************************************************/ -void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset); - -/***************************************************************************//** - * Gets time zone offset. - * - * @return Time zone offset, in seconds. - ******************************************************************************/ -sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void); - -/***************************************************************************//** - * Retrieves current 32 bit time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return Current timestamps in Unix format. - ******************************************************************************/ -sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); - -/***************************************************************************//** - * Retrieves current 64 bit time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return Current timestamps in Unix format. - ******************************************************************************/ -sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void); - -/***************************************************************************//** - * Sets current time. - * - * @param time timestamp structure to set. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); - -/***************************************************************************//** - * Sets current time. - * - * @param time timestamp structure to set. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time); - -/***************************************************************************//** - * Gets current date. - * - * @param date Pointer to a sl_sleeptimer_date_t structure. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Sets current time, in date format. - * - * @param date Pointer to current date. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters, - * where the maximum supported date is 10:14:07 PM 01/18/2038. - * - * @param date Pointer to the structure to be populated. - * @param year Current year. May be provided based on a 0 Epoch or a 1900 Epoch. - * @param month Months since January. Expected value: 0-11. - * @param month_day Day of the month. Expected value: 1-31. - * @param hour Hours since midnight. Expected value: 0-23. - * @param min Minutes after the hour. Expected value: 0-59. - * @param sec Seconds after the minute. Expected value: 0-59. - * @param tzOffset Offset, in seconds, from UTC. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tzOffset); - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters, - * where the maximum supported date is 11:59:59 PM 12/31/11899. - * - * @param date Pointer to the structure to be populated. - * @param year Current year based on 0 Epoch. - * @param month Months since January. Expected value: 0-11. - * @param month_day Day of the month. Expected value: 1-31. - * @param hour Hours since midnight. Expected value: 0-23. - * @param min Minutes after the hour. Expected value: 0-59. - * @param sec Seconds after the minute. Expected value: 0-59. - * @param tzOffset Offset, in seconds, from UTC. - * - * @note Resulting date structure's year will be based on 1900 epoch - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tzOffset); - -/***************************************************************************//** - * Converts Unix timestamp into NTP timestamp. - * - * @param time Unix timestamp. - * @param ntp_time Pointer to NTP Timestamp. - * - * @note Unix timestamp range supported : 0x0 to 0x7C55 817F - * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, - uint32_t *ntp_time); - -/***************************************************************************//** - * Converts NTP timestamp into Unix timestamp. - * - * @param ntp_time NTP Timestamp. - * @param time Pointer to Unix timestamp. - * - * @note NTP timestamp range supported : 0x83AA 7E80 to 0xFFFF FFFF - * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Converts Unix timestamp into Zigbee timestamp. - * - * @param time Unix timestamp. - * - * @param zigbee_time Pointer to NTP Timestamp. - * - * @note Unix timestamp range supported : 0x386D 4380 to 0x7FFF FFFF - * ie. January 1, 2000, 00:00:0 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, - uint32_t *zigbee_time); - -/***************************************************************************//** - * Converts Zigbee timestamp into Unix timestamp. - * - * @param zigbee_time NTP Timestamp. - * @param time Pointer to Unix timestamp. - * - * @note ZIGBEE timestamp range supported : 0x0 to 0x4792 BC7F - * ie. January 1, 2000, 00:00:00 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Calculates offset for time zone after UTC-0. - * - * @param hours Number of hours from UTC-0. - * @param minutes Number of minutes from UTC-0. - * - * @return The time zone offset in seconds. - ******************************************************************************/ -__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_ahead_utc(uint8_t hours, - uint8_t minutes) -{ - return ((hours * 3600u) + (minutes * 60u)); -} - -/***************************************************************************//** - * Calculates offset for time zone before UTC-0. - * - * @param hours Number of hours to UTC-0. - * @param minutes Number of minutes to UTC-0. - * - * @return The time zone offset in seconds. - ******************************************************************************/ -__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_behind_utc(uint8_t hours, - uint8_t minutes) -{ - return -(sl_sleeptimer_time_zone_offset_t)((hours * 3600u) + (minutes * 60u)); -} - -/***************************************************************************//** - * Active delay. - * - * @param time_ms Delay duration in milliseconds. - ******************************************************************************/ -void sl_sleeptimer_delay_millisecond(uint16_t time_ms); - -/***************************************************************************//** - * Converts milliseconds in ticks. - * - * @param time_ms Number of milliseconds. - * - * @return Corresponding ticks number. - * - * @note The result is "rounded" to the superior tick number. - * This function is light and cannot fail so it should be privilegied to - * perform a millisecond to tick conversion. - ******************************************************************************/ -uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms); - -/***************************************************************************//** - * Converts 32-bits milliseconds in ticks. - * - * @param time_ms Number of milliseconds. - * @param tick Pointer to the converted tick number. - * - * @return 0 if successful. Error code otherwise. - * - * @note The result is "rounded" to the superior tick number. - * If possible the sl_sleeptimer_ms_to_tick() function should be used. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'time_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'time_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, - uint32_t *tick); - -/***************************************************************************//** - * Gets the maximum value that can be passed to the functions that have a - * 32-bits time or timeout argument expressed in milliseconds. - * - * @return Maximum time or timeout value in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_max_ms32_conversion(void); - -/***************************************************************************//** - * Converts ticks in milliseconds. - * - * @param tick Number of tick. - * - * @return Corresponding milliseconds number. - * - * @note The result is rounded to the inferior millisecond. - ******************************************************************************/ -uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick); - -/***************************************************************************//** - * Converts 64-bit ticks in milliseconds. - * - * @param tick Number of tick. - * @param ms Pointer to the converted milliseconds number. - * - * @return 0 if successful. Error code otherwise. - * - * @note The result is rounded to the inferior millisecond. - ******************************************************************************/ -sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, - uint64_t *ms); - -/***************************************************************************//** - * Allow sleep after ISR exit. - * - * @return true if sleep is allowed after ISR exit. False otherwise. - ******************************************************************************/ -bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); - -/**************************************************************************//** - * Starts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - *****************************************************************************/ -__STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - return sl_sleeptimer_start_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - *****************************************************************************/ -__STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - return sl_sleeptimer_restart_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); -} - -/***************************************************************************//** - * Starts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer periodic timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer periodic timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - ******************************************************************************/ -uint16_t sl_sleeptimer_get_clock_accuracy(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup sleeptimer) */ - -/* *INDENT-OFF* */ -/* THE REST OF THE FILE IS DOCUMENTATION ONLY! */ -/// @addtogroup sleeptimer Sleep Timer -/// @{ -/// -/// @details -/// Sleep Timer can be used for creating timers which are tightly integrated with power management. -/// The Power Manager requires precision timing to have all clocks ready on time, so that wakeup -/// happens a little bit earlier to prepare the system to be ready at the right time. -/// Sleep Timer uses one Hardware Timer and creates multiple software timer instances. It is important -/// to note that when sleeptimer is used with WTIMER/TIMER, the MCU cannot go to EM2 energy mode -/// because WTIMER/TIMER uses a high frequency clock source which is not retained in low energy mode. -/// -/// The sleeptimer.c and sleeptimer.h source files for the SLEEPTIMER device driver library are in the -/// service/sleeptimer folder. -/// -/// @n @section sleeptimer_intro Introduction -/// -/// The Sleeptimer driver provides software timers, delays, timekeeping and date functionalities using a low-frequency real-time clock peripheral. -/// -/// All Silicon Labs microcontrollers equipped with the RTC or RTCC peripheral are currently supported. Only one instance of this driver can be initialized by the application. -/// -/// @n @section sleeptimer_functionalities_overview Functionalities overview -/// -/// @n @subsection software_timers Software Timers -/// -/// This functionality allows the user to create periodic and one shot timers. A user callback can be associated with a timer and is called when the timer expires. -/// -/// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. -/// -/// @n @subsection timekeeping Timekeeping -/// -/// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver -/// -/// The `SL_SLEEPTIMER_WALLCLOCK_CONFIG` configuration enables a UNIX timestamp (seconds count since January 1, 1970, 00:00:00). -/// -/// This timestamp can be retrieved/modified using the following API: -/// -/// @li sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); -/// @li sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); -/// -/// Convenience conversion functions are provided to convert UNIX timestamp to/from NTP and Zigbee cluster format : -/// -/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, uint32_t *ntp_time); -/// @li sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, sl_sleeptimer_timestamp_t *time); -/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, uint32_t *zigbee_time); -/// @li sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, sl_sleeptimer_timestamp_t *time); -/// -/// @n @subsection date Date -/// -/// The previously described internal timestamp can also be retrieved/modified in a date format sl_sleeptimer_date_t. -/// -/// @n API : @n -/// -/// @li sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); -/// @li sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); -/// -/// @n @subsection frequency_setup Frequency Setup and Tick Count -/// -/// This driver works with a configurable time unit called tick. -/// -/// The frequency of the ticks is based on the clock source and the internal frequency divider. -/// -/// WTIMER/TIMER peripherals uses high frequency oscillator. To have a reasonable tick frequency, divider is set to maximum value (1024). -/// -/// One of the following clock sources must be enabled before initializing the sleeptimer: -/// -/// @li LFXO: external crystal oscillator. Typically running at 32.768 kHz. -/// @li LFRCO: internal oscillator running at 32.768 kHz -/// @li ULFRCO: Ultra low-frequency oscillator running at 1.000 kHz -/// @li HFXO: High Frequency Crystal Oscillator at 39 Mhz. HFXO is only needed when Sleeptimer runs on TIMER or WTIMER. -/// -/// The frequency divider is selected with the `SL_SLEEPTIMER_FREQ_DIVIDER` configuration. Its value must be a power of two within the range of 1 to 32. The number of ticks per second (sleeptimer frequency) is dictated by the following formula: -/// -/// Tick (seconds) = 1 / (clock_frequency / frequency_divider) -/// -/// The highest resolution for a tick is 30.5 us. It is achieved with a 32.768 kHz clock and a divider of 1. -/// -/// @n @section sleeptimer_getting_started Getting Started -/// -/// @n @subsection clock_selection Clock Selection -/// -/// The sleeptimer relies on the hardware timer to operate. The hardware timer peripheral must be properly clocked from the application. Selecting the appropriate timer is crucial for design considerations. Each timer can potentially be used as a sleeptimer and is also available to the user. However, note that if a timer is used by the sleeptimer, it can't be used by the application and vice versa. -/// -/// For WTIMER/TIMER peripherals, the user must select the appropriate oscillator if it is not the default wanted clock source. -/// -/// When WTIMER/TIMER is selected, sleeptimer uses channel 0 and it is not possible to use other channels of the same instance for other purposes. -/// -/// @n @subsection Clock Selection in a Project without Micrium OS -/// -/// When RTC, RTCC, or BURTC is selected, the clock source for the peripheral must be configured and enabled in the application before initializing the sleeptimer module or any communication stacks. Most of the time, it consists in enabling the desired oscillators and setting up the clock source for the peripheral, like in the following example: -/// -/// @code{.c} -/// CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); -/// CMU_ClockEnable(cmuClock_RTCC, true); -/// @endcode -/// -/// @n @subsection clock_branch_select Clock Branch Select -/// -/// | Clock | Enum | Description | Frequency | -/// |--------|-------------------------|-----------------------------------|-----------| -/// | LFXO | cmuSelect_LFXO | Low-frequency crystal oscillator |32.768 Khz | -/// | LFRCO | cmuSelect_LFRCO | Low-frequency RC oscillator |32.768 Khz | -/// | ULFRCO | cmuSelect_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | -/// -/// @n @subsection timer_clock_enable Timer Clock Enable -/// -/// | Module | Enum | Description | -/// |--------------------|-----------------------|----------------------------------------------------| -/// | RTCC | cmuClock_RTCC | Real-time counter and calendar clock (LF E branch) | -/// | RTC | cmuClock_RTC | Real time counter clock (LF A branch) | -/// | BURTC | cmuClock_BURTC | BURTC clock (EM4 Group A branch) | -/// -/// When the Radio internal RTC (PRORTC) is selected, it is not necessary to configure the clock source for the peripheral. However, it is important to enable the desired oscillator before initializing the sleeptimer module or any communication stacks. The best oscillator available (LFXO being the first choice) will be used by the sleeptimer at initalization. The following example shows how the desired oscilator should be enabled: -/// -/// @code{.c} -/// CMU_OscillatorEnable(cmuSelect_LFXO, true, true); -/// @endcode -/// -/// @n @subsection clock_micrium_os Clock Selection in a Project with Micrium OS -/// -/// When Micrium OS is used, a BSP (all instances) is provided that sets up some parts of the clock tree. The sleeptimer clock source will be enabled by this bsp. However, the desired oscillator remains configurable from the file bsp_cfg.h. -/// -/// The configuration `BSP_LF_CLK_SEL` determines which oscillator will be used by the sleeptimer's hardware timer peripheral. It can take the following values: -/// -/// | Config | Description | Frequency | -/// |--------------------------|-----------------------------------|-----------| -/// | BSP_LF_CLK_LFXO | Low-frequency crystal oscillator |32.768 Khz | -/// | BSP_LF_CLK_LFRCO | Low-frequency RC oscillator |32.768 Khz | -/// | BSP_LF_CLK_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | -/// -/// @n @section sleeptimer_conf Configuration Options -/// -/// `SL_SLEEPTIMER_PERIPHERAL` can be set to one of the following values: -/// -/// | Config | Description | -/// | --------------------------------- |------------------------------------------------------------------------------------------------------| -/// | `SL_SLEEPTIMER_PERIPHERAL_DEFAULT`| Selects either RTC or RTCC, depending of what is available on the platform. | -/// | `SL_SLEEPTIMER_PERIPHERAL_RTCC` | Selects RTCC | -/// | `SL_SLEEPTIMER_PERIPHERAL_RTC` | Selects RTC | -/// | `SL_SLEEPTIMER_PERIPHERAL_PRORTC` | Selects Internal radio RTC. Available only on EFR32XG13, EFR32XG14, EFR32XG21 and EFR32XG22 families.| -/// | `SL_SLEEPTIMER_PERIPHERAL_BURTC` | Selects BURTC. Not available on Series 0 devices. | -/// -/// `SL_SLEEPTIMER_WALLCLOCK_CONFIG` must be set to 1 to enable timestamp and date functionnalities. -/// -/// `SL_SLEEPTIMER_FREQ_DIVIDER` must be a power of 2 within the range 1 to 32. When `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`, `SL_SLEEPTIMER_FREQ_DIVIDER` must be set to 1. -/// -/// `SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER` is only meaningful when `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`. Set to 1 if no communication stack is used in your project. Otherwise, must be set to 0. -/// -/// @n @section sleeptimer_api The API -/// -/// This section contains brief descriptions of the API functions. For -/// more information about input and output parameters and return values, -/// click on the hyperlinked function names. Most functions return an error -/// code, `SL_STATUS_OK` is returned on success, -/// see sl_status.h for other error codes. -/// -/// The application code must include the @em sl_sleeptimer.h header file. -/// -/// All API functions can be called from within interrupt handlers. -/// -/// @ref sl_sleeptimer_init() @n -/// These functions initialize the sleeptimer driver. Typically, -/// sl_sleeptimer_init() is called once in the startup code. -/// -/// @ref sl_sleeptimer_start_timer() @n -/// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_restart_timer() @n -/// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_start_periodic_timer() @n -/// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_restart_periodic_timer() @n -/// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_stop_timer() @n -/// Stop a timer. -/// -/// @ref sl_sleeptimer_get_timer_time_remaining() @n -/// Get the time remaining before the timer expires. -/// -/// @ref sl_sleeptimer_delay_millisecond() @n -/// Delay for the given number of milliseconds. This is an "active wait" delay function. -/// -/// @ref sl_sleeptimer_is_timer_running() @n -/// Check if a timer is running. -/// -/// @ref sl_sleeptimer_get_time(), @ref sl_sleeptimer_set_time() @n -/// Get or set wallclock time. -/// -/// @ref sl_sleeptimer_ms_to_tick(), @ref sl_sleeptimer_ms32_to_tick(), -/// @ref sl_sleeptimer_tick_to_ms(), @ref sl_sleeptimer_tick64_to_ms() @n -/// Convert between milliseconds and RTC/RTCC -/// counter ticks. -/// -/// @n @anchor callback The timer expiry callback function: @n -/// The callback function, prototyped as @ref sl_sleeptimer_timer_callback_t(), is called from -/// within the RTC peripheral interrupt handler on timer expiration. -/// sl_sleeptimer_timer_callback_t(sl_sleeptimer_timer_handle_t *handle, void *data) -/// -/// @n @section sleeptimer_example Example -/// @code{.c} -///#include "sl_sleeptimer.h" -/// -///void my_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data) -///{ -/// //Code executed when the timer expire. -///} -/// -///int start_timer(void) -///{ -/// sl_status_t status; -/// sl_sleeptimer_timer_handle_t my_timer; -/// uint32_t timer_timeout = 300; -/// -/// // We assume the sleeptimer is initialized properly -/// -/// status = sl_sleeptimer_start_timer(&my_timer, -/// timer_timeout, -/// my_timer_callback, -/// (void *)NULL, -/// 0, -/// 0); -/// if(status != SL_STATUS_OK) { -/// return -1; -/// } -/// return 1; -///} -/// @endcode -/// -/// @} (end addtogroup sleeptimer) - -#endif // SL_SLEEPTIMER_H +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sleeptimer Sleep Timer + * @{ + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_H +#define SL_SLEEPTIMER_H + +#include +#include +#include +#include "sl_status.h" +#include "sl_common.h" + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG (0x01) +#define SL_SLEEPTIMER_ANY_FLAG (0xFF) + +#define SLEEPTIMER_ENUM(name) typedef uint8_t name; enum name##_enum + +/// @endcond + +/// Timestamp, wall clock time in seconds. +typedef uint32_t sl_sleeptimer_timestamp_t; + +// Timestamp, 64 bits wall clock in seconds. +typedef uint64_t sl_sleeptimer_timestamp_64_t; ///< sl sleeptimer timestamp 64 t + +/// Time zone offset from UTC(second). +typedef int32_t sl_sleeptimer_time_zone_offset_t; + +// Forward declaration +typedef struct sl_sleeptimer_timer_handle sl_sleeptimer_timer_handle_t; + +/***************************************************************************//** + * Typedef for the user supplied callback function which is called when + * a timer expires. + * + * @param handle The timer handle. + * + * @param data An extra parameter for the user application. + ******************************************************************************/ +typedef void (*sl_sleeptimer_timer_callback_t)(sl_sleeptimer_timer_handle_t *handle, void *data); + +/// @brief Timer structure for sleeptimer +struct sl_sleeptimer_timer_handle { + void *callback_data; ///< User data to pass to callback function. + uint8_t priority; ///< Priority of timer. + uint16_t option_flags; ///< Option flags. + sl_sleeptimer_timer_handle_t *next; ///< Pointer to next element in list. + sl_sleeptimer_timer_callback_t callback; ///< Function to call when timer expires. + uint32_t timeout_periodic; ///< Periodic timeout. + uint32_t delta; ///< Delay relative to previous element in list. + uint32_t timeout_expected_tc; ///< Expected tick count of the next timeout (only used for periodic timer). + uint16_t conversion_error; ///< The error when converting ms to ticks (thousandths of ticks) + uint16_t accumulated_error; ///< Accumulated conversion error (thousandths of ticks) +}; + +/// @brief Month enum. +SLEEPTIMER_ENUM(sl_sleeptimer_month_t) { + MONTH_JANUARY = 0, + MONTH_FEBRUARY = 1, + MONTH_MARCH = 2, + MONTH_APRIL = 3, + MONTH_MAY = 4, + MONTH_JUNE = 5, + MONTH_JULY = 6, + MONTH_AUGUST = 7, + MONTH_SEPTEMBER = 8, + MONTH_OCTOBER = 9, + MONTH_NOVEMBER = 10, + MONTH_DECEMBER = 11, +}; + +/// @brief Week Day enum. +SLEEPTIMER_ENUM(sl_sleeptimer_weekDay_t) { + DAY_SUNDAY = 0, + DAY_MONDAY = 1, + DAY_TUESDAY = 2, + DAY_WEDNESDAY = 3, + DAY_THURSDAY = 4, + DAY_FRIDAY = 5, + DAY_SATURDAY = 6, +}; + +/// @brief Time and Date structure. +typedef struct time_date { + uint8_t sec; ///< Second (0-59) + uint8_t min; ///< Minute of month (0-59) + uint8_t hour; ///< Hour (0-23) + uint8_t month_day; ///< Day of month (1-31) + sl_sleeptimer_month_t month; ///< Month (0-11) + uint16_t year; ///< Year, based on a 1900 Epoch. + sl_sleeptimer_weekDay_t day_of_week; ///< Day of week (0-6) + uint16_t day_of_year; ///< Day of year (1-366) + sl_sleeptimer_time_zone_offset_t time_zone; ///< Offset, in seconds, from UTC +} sl_sleeptimer_date_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Initializes the Sleeptimer. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_init(void); + +/***************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Stops a timer. + * + * @param handle Pointer to handle to timer. + * + * @return + ******************************************************************************/ +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); + +/***************************************************************************//** + * Gets the status of a timer. + * + * @param handle Pointer to handle to timer. + * @param running Pointer to the status of the timer. + * + * @note A non periodic timer is considered not running during its callback. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, + bool *running); + +/***************************************************************************//** + * Gets remaining time until timer expires. + * + * @param handle Pointer to handle to timer. + * @param time Time left in timer ticks. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, + uint32_t *time); + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + * + * @param option_flags Set of flags to match: + * - SL_SLEEPTIMER_ANY_TIMER_FLAG + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * + * @param time_remaining Time left in timer ticks. + * + * @return 0 if successful. Error code otherwise. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining); + +/***************************************************************************//** + * Gets current 32 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_tick_count(void); + +/***************************************************************************//** + * Gets current 64 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +uint64_t sl_sleeptimer_get_tick_count64(void); + +/***************************************************************************//** + * Get timer frequency. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_timer_frequency(void); + +/***************************************************************************//** + * Converts a Unix timestamp into a date. + * + * @param time 32 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a 64 bit Unix timestamp into a date. + * + * @param time 64 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a date into a Unix timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 32 bit Unix timestamp. + * + * @return 0 if successful. Error code otherwise. + * + * @note Dates are based on the Unix time representation. + * Range of dates supported : + * - January 1, 1970, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts a date into a 64 bit timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 64 bit Unix timestamp. + * + * @return 0 if successful. Error code otherwise. + * + * @note Dates are based on the 64 bit Unix time representation. + * Range of dates supported : + * - January 1, 1900, 00:00:00 to December 31, 11899 23:59:59. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time); + +/***************************************************************************//** + * Convert date to string. + * + * @param str Output string. + * @param size Size of the input array. + * @param format The format specification character. + * @param date Pointer to date structure. + * + * @return 0 if error. Number of character in the output string. + * + * @note Refer strftime() from UNIX. + * http://man7.org/linux/man-pages/man3/strftime.3.html + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset); + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void); + +/***************************************************************************//** + * Retrieves current 32 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); + +/***************************************************************************//** + * Retrieves current 64 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time); + +/***************************************************************************//** + * Gets current date. + * + * @param date Pointer to a sl_sleeptimer_date_t structure. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets current time, in date format. + * + * @param date Pointer to current date. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 10:14:07 PM 01/18/2038. + * + * @param date Pointer to the structure to be populated. + * @param year Current year. May be provided based on a 0 Epoch or a 1900 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 11:59:59 PM 12/31/11899. + * + * @param date Pointer to the structure to be populated. + * @param year Current year based on 0 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Resulting date structure's year will be based on 1900 epoch + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Converts Unix timestamp into NTP timestamp. + * + * @param time Unix timestamp. + * @param ntp_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x0 to 0x7C55 817F + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time); + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + * + * @param ntp_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note NTP timestamp range supported : 0x83AA 7E80 to 0xFFFF FFFF + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + * + * @param time Unix timestamp. + * + * @param zigbee_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x386D 4380 to 0x7FFF FFFF + * ie. January 1, 2000, 00:00:0 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time); + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + * + * @param zigbee_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note ZIGBEE timestamp range supported : 0x0 to 0x4792 BC7F + * ie. January 1, 2000, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Calculates offset for time zone after UTC-0. + * + * @param hours Number of hours from UTC-0. + * @param minutes Number of minutes from UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_ahead_utc(uint8_t hours, + uint8_t minutes) +{ + return ((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Calculates offset for time zone before UTC-0. + * + * @param hours Number of hours to UTC-0. + * @param minutes Number of minutes to UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_behind_utc(uint8_t hours, + uint8_t minutes) +{ + return -(sl_sleeptimer_time_zone_offset_t)((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Active delay. + * + * @param time_ms Delay duration in milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms); + +/***************************************************************************//** + * Converts milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * + * @return Corresponding ticks number. + * + * @note The result is "rounded" to the superior tick number. + * This function is light and cannot fail so it should be privilegied to + * perform a millisecond to tick conversion. + ******************************************************************************/ +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms); + +/***************************************************************************//** + * Converts 32-bits milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * @param tick Pointer to the converted tick number. + * + * @return 0 if successful. Error code otherwise. + * + * @note The result is "rounded" to the superior tick number. + * If possible the sl_sleeptimer_ms_to_tick() function should be used. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'time_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'time_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick); + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + * + * @return Maximum time or timeout value in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void); + +/***************************************************************************//** + * Converts ticks in milliseconds. + * + * @param tick Number of tick. + * + * @return Corresponding milliseconds number. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick); + +/***************************************************************************//** + * Converts 64-bit ticks in milliseconds. + * + * @param tick Number of tick. + * @param ms Pointer to the converted milliseconds number. + * + * @return 0 if successful. Error code otherwise. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms); + +/***************************************************************************//** + * Allow sleep after ISR exit. + * + * @return true if sleep is allowed after ISR exit. False otherwise. + ******************************************************************************/ +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); + +/**************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_start_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_restart_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup sleeptimer) */ + +/* *INDENT-OFF* */ +/* THE REST OF THE FILE IS DOCUMENTATION ONLY! */ +/// @addtogroup sleeptimer Sleep Timer +/// @{ +/// +/// @details +/// Sleep Timer can be used for creating timers which are tightly integrated with power management. +/// The Power Manager requires precision timing to have all clocks ready on time, so that wakeup +/// happens a little bit earlier to prepare the system to be ready at the right time. +/// Sleep Timer uses one Hardware Timer and creates multiple software timer instances. It is important +/// to note that when sleeptimer is used with WTIMER/TIMER, the MCU cannot go to EM2 energy mode +/// because WTIMER/TIMER uses a high frequency clock source which is not retained in low energy mode. +/// +/// The sleeptimer.c and sleeptimer.h source files for the SLEEPTIMER device driver library are in the +/// service/sleeptimer folder. +/// +/// @n @section sleeptimer_intro Introduction +/// +/// The Sleeptimer driver provides software timers, delays, timekeeping and date functionalities using a low-frequency real-time clock peripheral. +/// +/// All Silicon Labs microcontrollers equipped with the RTC or RTCC peripheral are currently supported. Only one instance of this driver can be initialized by the application. +/// +/// @n @section sleeptimer_functionalities_overview Functionalities overview +/// +/// @n @subsection software_timers Software Timers +/// +/// This functionality allows the user to create periodic and one shot timers. A user callback can be associated with a timer and is called when the timer expires. +/// +/// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. +/// +/// @n @subsection timekeeping Timekeeping +/// +/// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver +/// +/// The `SL_SLEEPTIMER_WALLCLOCK_CONFIG` configuration enables a UNIX timestamp (seconds count since January 1, 1970, 00:00:00). +/// +/// This timestamp can be retrieved/modified using the following API: +/// +/// @li sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); +/// @li sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); +/// +/// Convenience conversion functions are provided to convert UNIX timestamp to/from NTP and Zigbee cluster format : +/// +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, uint32_t *ntp_time); +/// @li sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, sl_sleeptimer_timestamp_t *time); +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, uint32_t *zigbee_time); +/// @li sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, sl_sleeptimer_timestamp_t *time); +/// +/// @n @subsection date Date +/// +/// The previously described internal timestamp can also be retrieved/modified in a date format sl_sleeptimer_date_t. +/// +/// @n API : @n +/// +/// @li sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); +/// @li sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); +/// +/// @n @subsection frequency_setup Frequency Setup and Tick Count +/// +/// This driver works with a configurable time unit called tick. +/// +/// The frequency of the ticks is based on the clock source and the internal frequency divider. +/// +/// WTIMER/TIMER peripherals uses high frequency oscillator. To have a reasonable tick frequency, divider is set to maximum value (1024). +/// +/// One of the following clock sources must be enabled before initializing the sleeptimer: +/// +/// @li LFXO: external crystal oscillator. Typically running at 32.768 kHz. +/// @li LFRCO: internal oscillator running at 32.768 kHz +/// @li ULFRCO: Ultra low-frequency oscillator running at 1.000 kHz +/// @li HFXO: High Frequency Crystal Oscillator at 39 Mhz. HFXO is only needed when Sleeptimer runs on TIMER or WTIMER. +/// +/// The frequency divider is selected with the `SL_SLEEPTIMER_FREQ_DIVIDER` configuration. Its value must be a power of two within the range of 1 to 32. The number of ticks per second (sleeptimer frequency) is dictated by the following formula: +/// +/// Tick (seconds) = 1 / (clock_frequency / frequency_divider) +/// +/// The highest resolution for a tick is 30.5 us. It is achieved with a 32.768 kHz clock and a divider of 1. +/// +/// @n @section sleeptimer_getting_started Getting Started +/// +/// @n @subsection clock_selection Clock Selection +/// +/// The sleeptimer relies on the hardware timer to operate. The hardware timer peripheral must be properly clocked from the application. Selecting the appropriate timer is crucial for design considerations. Each timer can potentially be used as a sleeptimer and is also available to the user. However, note that if a timer is used by the sleeptimer, it can't be used by the application and vice versa. +/// +/// For WTIMER/TIMER peripherals, the user must select the appropriate oscillator if it is not the default wanted clock source. +/// +/// When WTIMER/TIMER is selected, sleeptimer uses channel 0 and it is not possible to use other channels of the same instance for other purposes. +/// +/// @n @subsection Clock Selection in a Project without Micrium OS +/// +/// When RTC, RTCC, or BURTC is selected, the clock source for the peripheral must be configured and enabled in the application before initializing the sleeptimer module or any communication stacks. Most of the time, it consists in enabling the desired oscillators and setting up the clock source for the peripheral, like in the following example: +/// +/// @code{.c} +/// CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); +/// CMU_ClockEnable(cmuClock_RTCC, true); +/// @endcode +/// +/// @n @subsection clock_branch_select Clock Branch Select +/// +/// | Clock | Enum | Description | Frequency | +/// |--------|-------------------------|-----------------------------------|-----------| +/// | LFXO | cmuSelect_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | LFRCO | cmuSelect_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | ULFRCO | cmuSelect_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @subsection timer_clock_enable Timer Clock Enable +/// +/// | Module | Enum | Description | +/// |--------------------|-----------------------|----------------------------------------------------| +/// | RTCC | cmuClock_RTCC | Real-time counter and calendar clock (LF E branch) | +/// | RTC | cmuClock_RTC | Real time counter clock (LF A branch) | +/// | BURTC | cmuClock_BURTC | BURTC clock (EM4 Group A branch) | +/// +/// When the Radio internal RTC (PRORTC) is selected, it is not necessary to configure the clock source for the peripheral. However, it is important to enable the desired oscillator before initializing the sleeptimer module or any communication stacks. The best oscillator available (LFXO being the first choice) will be used by the sleeptimer at initalization. The following example shows how the desired oscilator should be enabled: +/// +/// @code{.c} +/// CMU_OscillatorEnable(cmuSelect_LFXO, true, true); +/// @endcode +/// +/// @n @subsection clock_micrium_os Clock Selection in a Project with Micrium OS +/// +/// When Micrium OS is used, a BSP (all instances) is provided that sets up some parts of the clock tree. The sleeptimer clock source will be enabled by this bsp. However, the desired oscillator remains configurable from the file bsp_cfg.h. +/// +/// The configuration `BSP_LF_CLK_SEL` determines which oscillator will be used by the sleeptimer's hardware timer peripheral. It can take the following values: +/// +/// | Config | Description | Frequency | +/// |--------------------------|-----------------------------------|-----------| +/// | BSP_LF_CLK_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | BSP_LF_CLK_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | BSP_LF_CLK_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @section sleeptimer_conf Configuration Options +/// +/// `SL_SLEEPTIMER_PERIPHERAL` can be set to one of the following values: +/// +/// | Config | Description | +/// | --------------------------------- |------------------------------------------------------------------------------------------------------| +/// | `SL_SLEEPTIMER_PERIPHERAL_DEFAULT`| Selects either RTC or RTCC, depending of what is available on the platform. | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTCC` | Selects RTCC | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTC` | Selects RTC | +/// | `SL_SLEEPTIMER_PERIPHERAL_PRORTC` | Selects Internal radio RTC. Available only on EFR32XG13, EFR32XG14, EFR32XG21 and EFR32XG22 families.| +/// | `SL_SLEEPTIMER_PERIPHERAL_BURTC` | Selects BURTC. Not available on Series 0 devices. | +/// +/// `SL_SLEEPTIMER_WALLCLOCK_CONFIG` must be set to 1 to enable timestamp and date functionnalities. +/// +/// `SL_SLEEPTIMER_FREQ_DIVIDER` must be a power of 2 within the range 1 to 32. When `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`, `SL_SLEEPTIMER_FREQ_DIVIDER` must be set to 1. +/// +/// `SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER` is only meaningful when `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`. Set to 1 if no communication stack is used in your project. Otherwise, must be set to 0. +/// +/// @n @section sleeptimer_api The API +/// +/// This section contains brief descriptions of the API functions. For +/// more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, `SL_STATUS_OK` is returned on success, +/// see sl_status.h for other error codes. +/// +/// The application code must include the @em sl_sleeptimer.h header file. +/// +/// All API functions can be called from within interrupt handlers. +/// +/// @ref sl_sleeptimer_init() @n +/// These functions initialize the sleeptimer driver. Typically, +/// sl_sleeptimer_init() is called once in the startup code. +/// +/// @ref sl_sleeptimer_start_timer() @n +/// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_timer() @n +/// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_start_periodic_timer() @n +/// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_periodic_timer() @n +/// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_stop_timer() @n +/// Stop a timer. +/// +/// @ref sl_sleeptimer_get_timer_time_remaining() @n +/// Get the time remaining before the timer expires. +/// +/// @ref sl_sleeptimer_delay_millisecond() @n +/// Delay for the given number of milliseconds. This is an "active wait" delay function. +/// +/// @ref sl_sleeptimer_is_timer_running() @n +/// Check if a timer is running. +/// +/// @ref sl_sleeptimer_get_time(), @ref sl_sleeptimer_set_time() @n +/// Get or set wallclock time. +/// +/// @ref sl_sleeptimer_ms_to_tick(), @ref sl_sleeptimer_ms32_to_tick(), +/// @ref sl_sleeptimer_tick_to_ms(), @ref sl_sleeptimer_tick64_to_ms() @n +/// Convert between milliseconds and RTC/RTCC +/// counter ticks. +/// +/// @n @anchor callback The timer expiry callback function: @n +/// The callback function, prototyped as @ref sl_sleeptimer_timer_callback_t(), is called from +/// within the RTC peripheral interrupt handler on timer expiration. +/// sl_sleeptimer_timer_callback_t(sl_sleeptimer_timer_handle_t *handle, void *data) +/// +/// @n @section sleeptimer_example Example +/// @code{.c} +///#include "sl_sleeptimer.h" +/// +///void my_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data) +///{ +/// //Code executed when the timer expire. +///} +/// +///int start_timer(void) +///{ +/// sl_status_t status; +/// sl_sleeptimer_timer_handle_t my_timer; +/// uint32_t timer_timeout = 300; +/// +/// // We assume the sleeptimer is initialized properly +/// +/// status = sl_sleeptimer_start_timer(&my_timer, +/// timer_timeout, +/// my_timer_callback, +/// (void *)NULL, +/// 0, +/// 0); +/// if(status != SL_STATUS_OK) { +/// return -1; +/// } +/// return 1; +///} +/// @endcode +/// +/// @} (end addtogroup sleeptimer) + +#endif // SL_SLEEPTIMER_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h index aaa353a..254323d 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER SDK internal APIs. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_SLEEPTIMER_H -#define SLI_SLEEPTIMER_H - -#include -#include -#include -#include "em_device.h" -#include "sl_sleeptimer_config.h" - -#define SLEEPTIMER_EVENT_OF (0x01) -#define SLEEPTIMER_EVENT_COMP (0x02) - -#define SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG 0x02 -#define SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG 0x04 - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_DEFAULT -#if defined(RTCC_PRESENT) && RTCC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTCC -#elif defined(RTC_PRESENT) && RTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTC -#elif defined(SYSRTC_PRESENT) && SYSRTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_SYSRTC -#elif defined(BURTC_PRESENT) && BURTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_BURTC -#elif defined(WTIMER_PRESENT) && WTIMER_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_WTIMER -#elif defined(TIMER_PRESENT) && TIMER_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_TIMER -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to Power Manager. - ******************************************************************************/ -__WEAK void sli_sleeptimer_hal_power_manager_integration_init(void); - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to HFXO Manager. - ******************************************************************************/ -__WEAK void sli_sleeptimer_hal_hfxo_manager_integration_init(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get interrupt status. - * - * @param local_flag Internal interrupt flag. - * - * @return Boolean indicating if specified interrupt is set. - ******************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag); - -/**************************************************************************//** - * Determines if next timer to expire has the option flag - * "SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". - * - * @return true if power manager will expire at next compare match, - * false otherwise. - *****************************************************************************/ -bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void); - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void); -#endif - -/***************************************************************************//** - * @brief - * Update sleep_on_isr_exit flag. - * - * @param flag Boolean value update_sleep_on_isr_exit will be set to. - ******************************************************************************/ -void sli_sleeptimer_update_sleep_on_isr_exit(bool flag); - -/******************************************************************************* - * Gets the associated peripheral capture channel current value. - * - * @return Capture value - * 0 if capture channel is not valid - ******************************************************************************/ -uint32_t sli_sleeptimer_get_capture(void); - -/******************************************************************************* - * Resets the PRS signal triggered by the associated peripheral. - ******************************************************************************/ -void sli_sleeptimer_reset_prs_signal(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SLI_SLEEPTIMER_H */ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER SDK internal APIs. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SLEEPTIMER_H +#define SLI_SLEEPTIMER_H + +#include +#include +#include +#include "em_device.h" +#include "sl_sleeptimer_config.h" + +#define SLEEPTIMER_EVENT_OF (0x01) +#define SLEEPTIMER_EVENT_COMP (0x02) + +#define SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG 0x02 +#define SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG 0x04 + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_DEFAULT +#if defined(RTCC_PRESENT) && RTCC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTCC +#elif defined(RTC_PRESENT) && RTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTC +#elif defined(SYSRTC_PRESENT) && SYSRTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_SYSRTC +#elif defined(BURTC_PRESENT) && BURTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_BURTC +#elif defined(WTIMER_PRESENT) && WTIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_WTIMER +#elif defined(TIMER_PRESENT) && TIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_TIMER +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to Power Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_power_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to HFXO Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_hfxo_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get interrupt status. + * + * @param local_flag Internal interrupt flag. + * + * @return Boolean indicating if specified interrupt is set. + ******************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag); + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @return true if power manager will expire at next compare match, + * false otherwise. + *****************************************************************************/ +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void); + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void); +#endif + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Boolean value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag); + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + * + * @return Capture value + * 0 if capture channel is not valid + ******************************************************************************/ +uint32_t sli_sleeptimer_get_capture(void); + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +void sli_sleeptimer_reset_prs_signal(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_SLEEPTIMER_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c index 1f7cbd2..8cf245e 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c @@ -1,1942 +1,1942 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include - -#include "em_device.h" -#include "em_core_generic.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "sl_atomic.h" -#include "sl_sleeptimer_config.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#include "sli_power_manager.h" -#endif - -#define TIME_UNIX_EPOCH (1970u) -#define TIME_NTP_EPOCH (1900u) -#define TIME_ZIGBEE_EPOCH (2000u) -#define TIME_64_EPOCH TIME_NTP_EPOCH -#define TIME_NTP_UNIX_EPOCH_DIFF (TIME_UNIX_EPOCH - TIME_NTP_EPOCH) -#define TIME_ZIGBEE_UNIX_EPOCH_DIFF (TIME_ZIGBEE_EPOCH - TIME_UNIX_EPOCH) -#define TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH (TIME_NTP_UNIX_EPOCH_DIFF * 365u + 17u) ///< 70 years and 17 leap days -#define TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH (TIME_ZIGBEE_UNIX_EPOCH_DIFF * 365u + 7u) ///< 30 years and 7 leap days -#define TIME_SEC_PER_DAY (60u * 60u * 24u) -#define TIME_NTP_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) -#define TIME_ZIGBEE_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) -#define TIME_DAY_PER_YEAR (365u) -#define TIME_SEC_PER_YEAR (TIME_SEC_PER_DAY * TIME_DAY_PER_YEAR) -#define TIME_UNIX_TIMESTAMP_MAX (0x7FFFFFFF) -#define TIME_64_BIT_UNIX_TIMESTAMP_MAX (0x497968BD7F) /// Max 64 bit timestamp supported is 11:59:59 PM 12/31/11899 -#define TIME_UNIX_YEAR_MAX (2038u - TIME_NTP_EPOCH) ///< Max UNIX year based from a 1900 epoch -#define TIME_64_BIT_YEAR_MAX (11899u - TIME_NTP_EPOCH) ///< Max 64 bit format year based from a 1900 epoch -#define TIME_64_TO_32_EPOCH_OFFSET_SEC TIME_NTP_EPOCH_OFFSET_SEC -#define TIME_UNIX_TO_NTP_MAX (0xFFFFFFFF - TIME_NTP_EPOCH_OFFSET_SEC) - -// Minimum count difference used when evaluating if a timer expired or not after an interrupt -// by comparing the current count value and the expected expiration count value. -// The difference should be null or of few ticks since the counter never stop. -#define MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION 2 - -/// @brief Time Format. -SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { - TIME_FORMAT_UNIX = 0, ///< Number of seconds since January 1, 1970, 00:00. Type is signed, so represented on 31 bit. - TIME_FORMAT_NTP = 1, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 32 bit. - TIME_FORMAT_ZIGBEE_CLUSTER = 2, ///< Number of seconds since January 1, 2000, 00:00. Type is unsigned, so represented on 32 bit. - TIME_FORMAT_UNIX_64_BIT = 3, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 64 bit. -}; - -// tick_count, it can wrap around. -typedef uint32_t sl_sleeptimer_tick_count_t; - -// Overflow counter used to provide 64-bits tick count. -static volatile uint16_t overflow_counter; - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -// Current time count. -static sl_sleeptimer_timestamp_64_t second_count; -// Tick rest when the frequency is not a divider of the timer width. -static uint32_t overflow_tick_rest = 0; -// Current time zone offset. -static sl_sleeptimer_time_zone_offset_t tz_offset = 0; -// Precalculated tick rest in case of overflow. -static uint32_t calculated_tick_rest = 0; -// Precalculated timer overflow duration in seconds. -static uint32_t calculated_sec_count = 0; -#endif - -// Timer frequency in Hz. -static uint32_t timer_frequency; - -// Head of timer list. -static sl_sleeptimer_timer_handle_t *timer_head; - -// Count at last update of delta of first timer. -static volatile sl_sleeptimer_tick_count_t last_delta_update_count; - -// Initialization flag. -static bool is_sleeptimer_initialized = false; - -// Flag that indicates if power manager's timer will expire at next compare match. -static bool next_timer_to_expire_is_power_manager = false; - -// Precalculated value to avoid millisecond to tick conversion overflow. -static uint32_t max_millisecond_conversion; - -// Sleep on ISR exit flag. -static bool sleep_on_isr_exit = false; - -static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout); - -static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); - -static void set_comparator_for_next_timer(void); - -static void update_delta_list(void); - -__STATIC_INLINE uint32_t div_to_log2(uint32_t div); - -__STATIC_INLINE bool is_power_of_2(uint32_t nbr); - -static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout_initial, - sl_sleeptimer_tick_count_t timeout_periodic, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -static void update_next_timer_to_expire_is_power_manager(void); - -static void delay_callback(sl_sleeptimer_timer_handle_t *handle, - void *data); - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -static bool is_leap_year(uint16_t year); -static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year); - -static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day); -static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day); -static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool isLeapYear); - -static bool is_valid_time(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone); - -static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone); - -static bool is_valid_date(sl_sleeptimer_date_t *date); - -static bool is_valid_date_64(sl_sleeptimer_date_t *date); - -static const uint8_t days_in_month[2u][12] = { - /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ - { 31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u }, - { 31u, 29u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u } -}; -#endif - -/**************************************************************************//** - * Initializes sleep timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_init(void) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (!is_sleeptimer_initialized) { - timer_head = NULL; - last_delta_update_count = 0u; - overflow_counter = 0u; - sleeptimer_hal_init_timer(); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_OF); - timer_frequency = sleeptimer_hal_get_timer_frequency(); - if (timer_frequency == 0) { - CORE_EXIT_ATOMIC(); - return SL_STATUS_INVALID_CONFIGURATION; - } - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG - second_count = 0; - calculated_tick_rest = ((uint64_t)UINT32_MAX + 1) % (uint64_t)timer_frequency; - calculated_sec_count = (((uint64_t)UINT32_MAX + 1) / (uint64_t)timer_frequency); -#endif - max_millisecond_conversion = (uint32_t)(((uint64_t)UINT32_MAX * (uint64_t)1000u) / timer_frequency); - is_sleeptimer_initialized = true; - } - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Starts a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_NOT_READY; - } - - return create_timer(handle, - timeout, - 0, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer is not running. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout, - 0, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Starts a 32 bits periodic timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_INVALID_STATE; - } - - return create_timer(handle, - timeout, - timeout, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Starts a 32 bits periodic timer using milliseconds as the timebase. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - sl_status_t status; - uint32_t timeout_tick; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_INVALID_STATE; - } - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - // Calculate ms to ticks conversion error - handle->conversion_error = 1000 - - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) - % 1000); - if (handle->conversion_error == 1000) { - handle->conversion_error = 0; - } - // Initialize accumulated error to 0. The calculated conversion error will - // be added to this variable each time a timer in the series of periodic timers - // expires. - handle->accumulated_error = 0; - - return create_timer(handle, - timeout_tick, - timeout_tick, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits periodic timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout, - timeout, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits periodic timer using milliseconds as the timebase. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - // Calculate ms to ticks conversion error - handle->conversion_error = 1000 - - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) - % 1000); - if (handle->conversion_error == 1000) { - handle->conversion_error = 0; - } - - // Initialize accumulated error to 0. The calculated conversion error will - // be added to this variable each time a timer in the series of periodic timers - // expires. - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout_tick, - timeout_tick, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Stops a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) -{ - CORE_DECLARE_IRQ_STATE; - sl_status_t error; - bool set_comparator = false; - - // Disable PRS compare and capture channel, if configured for early wakeup -#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ - && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - if (handle->option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { - sleeptimer_hal_disable_prs_compare_and_capture_channel(); - } -#endif - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - CORE_ENTER_CRITICAL(); - update_delta_list(); - - // If first timer in list, update timer comparator. - if (timer_head == handle) { - set_comparator = true; - } - - error = delta_list_remove_timer(handle); - if (error != SL_STATUS_OK) { - CORE_EXIT_CRITICAL(); - - return error; - } - - if (set_comparator && timer_head) { - set_comparator_for_next_timer(); - } else if (!timer_head) { - sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); - } - - CORE_EXIT_CRITICAL(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets the status of a timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, - bool *running) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - - if (handle == NULL || running == NULL) { - return SL_STATUS_NULL_POINTER; - } else { - *running = false; - CORE_ENTER_ATOMIC(); - current = timer_head; - while (current != NULL && !*running) { - if (current == handle) { - *running = true; - } else { - current = current->next; - } - } - CORE_EXIT_ATOMIC(); - } - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets a 32 bits timer's time remaining. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, - uint32_t *time) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - - if (handle == NULL || time == NULL) { - return SL_STATUS_NULL_POINTER; - } - - CORE_ENTER_ATOMIC(); - - update_delta_list(); - *time = handle->delta; - - // Retrieve timer in list and add the deltas. - current = timer_head; - while (current != handle && current != NULL) { - *time += current->delta; - current = current->next; - } - - if (current != handle) { - CORE_EXIT_ATOMIC(); - - return SL_STATUS_NOT_READY; - } - - // Substract time since last compare match. - if (*time > sleeptimer_hal_get_counter() - last_delta_update_count) { - *time -= sleeptimer_hal_get_counter() - last_delta_update_count; - } else { - *time = 0; - } - - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets the time remaining until the first timer with the matching set of flags - * expires. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, - uint32_t *time_remaining) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - uint32_t time = 0; - - CORE_ENTER_ATOMIC(); - // parse list and retrieve first timer with option flags requirement. - current = timer_head; - while (current != NULL) { - // save time remaining for timer. - time += current->delta; - // Check if the current timer has the flags requested - if (current->option_flags == option_flags - || option_flags == SL_SLEEPTIMER_ANY_FLAG) { - // Substract time since last compare match. - if (time > (sleeptimer_hal_get_counter() - last_delta_update_count)) { - time -= (sleeptimer_hal_get_counter() - last_delta_update_count); - } else { - time = 0; - } - *time_remaining = time; - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; - } - current = current->next; - } - CORE_EXIT_ATOMIC(); - - return SL_STATUS_EMPTY; -} - -/**************************************************************************//** - * Determines if next timer to expire has the option flag - * "SL_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". - * - * @note This function is for internal use only. - * - * @note A check to validate that the Power Manager Sleeptimer is expired on - * top of being the next timer was added. This is because - * this function is called when coming back from EM2 sleep to validate - * that the system woke up because of this precise timer expiration. - * Some race conditions, seen with FreeRTOS, could create invalid RTC - * interrupt leading to believe that the power manager timer was expired - * when it was not. - *****************************************************************************/ -bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) -{ - bool next_timer_is_power_manager; - - sl_atomic_load(next_timer_is_power_manager, next_timer_to_expire_is_power_manager); - - // Make sure that the Power Manager Sleeptimer is actually expired in addition - // to being the next timer. - if ((next_timer_is_power_manager) - && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { - next_timer_is_power_manager = false; - } - - return next_timer_is_power_manager; -} - -/***************************************************************************//** -* Gets current 32 bits tick count. -*******************************************************************************/ -uint32_t sl_sleeptimer_get_tick_count(void) -{ - uint32_t cnt; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - cnt = sleeptimer_hal_get_counter(); - CORE_EXIT_ATOMIC(); - - return cnt; -} - -/***************************************************************************//** -* Gets current 64 bits tick count. -*******************************************************************************/ -uint64_t sl_sleeptimer_get_tick_count64(void) -{ - uint32_t tick_cnt; - uint32_t of_cnt; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - tick_cnt = sleeptimer_hal_get_counter(); - of_cnt = overflow_counter; - - if (sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_OF)) { - tick_cnt = sleeptimer_hal_get_counter(); - of_cnt++; - } - CORE_EXIT_ATOMIC(); - - return (((uint64_t) of_cnt) << 32) | tick_cnt; -} - -/***************************************************************************//** - * Get timer frequency. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_timer_frequency(void) -{ - return timer_frequency; -} - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -/***************************************************************************//** - * Retrieves current 32 bit time. - ******************************************************************************/ -sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void) -{ - uint64_t temp_time = sl_sleeptimer_get_time_64(); - // Add offset for 64 to 32 bit time - if (temp_time >= TIME_64_TO_32_EPOCH_OFFSET_SEC) { - temp_time -= TIME_64_TO_32_EPOCH_OFFSET_SEC; - } - // Return lower 32 bits of 64 bit time - uint32_t time = (temp_time & 0xFFFFFFFF); - - return time; -} - -/***************************************************************************//** - * Retrieves current 64 bit time. - ******************************************************************************/ -sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void) -{ - uint32_t cnt = 0u; - uint32_t freq = 0u; - sl_sleeptimer_timestamp_64_t time; - CORE_DECLARE_IRQ_STATE; - - cnt = sleeptimer_hal_get_counter(); - freq = sl_sleeptimer_get_timer_frequency(); - - CORE_ENTER_ATOMIC(); - time = second_count + cnt / freq; - - if (cnt % freq + overflow_tick_rest >= freq) { - time++; - } - CORE_EXIT_ATOMIC(); - - return time; -} - -/***************************************************************************//** - * Sets current time from 32 bit variable. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time) -{ - // convert 32 bit time to 64 bit time - uint64_t temp_time = time + TIME_64_TO_32_EPOCH_OFFSET_SEC; - sl_status_t err_code = sl_sleeptimer_set_time_64(temp_time); - return err_code; -} - -/***************************************************************************//** - * Sets current time from 64 bit variable. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time) -{ - uint32_t freq = 0u; - uint32_t counter_sec = 0u; - uint32_t cnt = 0; - CORE_DECLARE_IRQ_STATE; - - // convert 64 bit time to 32 bit time - if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } - - freq = sl_sleeptimer_get_timer_frequency(); - cnt = sleeptimer_hal_get_counter(); - - CORE_ENTER_ATOMIC(); - // store 64 bit time as 64 bits's - second_count = time; - - // Convert 64 bit time to 32 bit time in order to check for overflow - // i.e. if 32 bit time is >=counter_sec - uint64_t temp_time = second_count - TIME_64_TO_32_EPOCH_OFFSET_SEC; - uint32_t second_time_32 = (temp_time & 0xFFFFFFFF); - - overflow_tick_rest = 0; - counter_sec = cnt / freq; - - if (second_time_32 >= counter_sec) { - second_count -= counter_sec; - } else { - CORE_EXIT_ATOMIC(); - - return SL_STATUS_INVALID_PARAMETER; - } - - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Gets current date. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date) -{ - sl_sleeptimer_timestamp_64_t time = 0u; - sl_sleeptimer_time_zone_offset_t tz; - sl_status_t err_code = SL_STATUS_OK; - - // Fetch 64 bit timestamp - time = sl_sleeptimer_get_time_64(); - tz = sl_sleeptimer_get_tz(); - err_code = sl_sleeptimer_convert_time_to_date_64(time, tz, date); - - return err_code; -} - -/***************************************************************************//** - * Sets current time, in date format. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date) -{ - sl_sleeptimer_timestamp_64_t time = 0u; - sl_status_t err_code = SL_STATUS_OK; - CORE_DECLARE_IRQ_STATE; - - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - err_code = sl_sleeptimer_convert_date_to_time_64(date, &time); - if (err_code != SL_STATUS_OK) { - return err_code; - } - - CORE_ENTER_ATOMIC(); - // sets the 64 bit second_time value - err_code = sl_sleeptimer_set_time_64(time); - if (err_code == SL_STATUS_OK) { - sl_sleeptimer_set_tz(date->time_zone); - } - CORE_EXIT_ATOMIC(); - - return err_code; -} - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tz_offset) -{ - if (date == NULL) { - return SL_STATUS_NULL_POINTER; - } - - // If year is smaller than 1900, assume NTP Epoch is used. - date->year = ((year < TIME_NTP_EPOCH) ? year : (year - TIME_NTP_EPOCH)); - date->month = month; - date->month_day = month_day; - date->hour = hour; - date->min = min; - date->sec = sec; - date->time_zone = tz_offset; - - // Validate that input parameters are correct before filing the missing fields - if (!is_valid_date(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); - date->day_of_week = compute_day_of_week(((date->year - TIME_NTP_UNIX_EPOCH_DIFF) * TIME_DAY_PER_YEAR) - + number_of_leap_days(TIME_UNIX_EPOCH, (date->year + TIME_NTP_EPOCH)) - + date->day_of_year - 1); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tz_offset) -{ - if (date == NULL) { - return SL_STATUS_NULL_POINTER; - } - - // Ensure that year is greater than 1900 and based on 0 epoch - if (year < TIME_NTP_EPOCH) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Convert year based on 0 epoch to a valid date->year based on 1900 epoch - date->year = (year - TIME_NTP_EPOCH); - date->month = month; - date->month_day = month_day; - date->hour = hour; - date->min = min; - date->sec = sec; - date->time_zone = tz_offset; - - // Validate that input parameters are correct before filing the missing fields - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); - date->day_of_week = compute_day_of_week_64((date->year * TIME_DAY_PER_YEAR) - + number_of_leap_days(TIME_NTP_EPOCH, (date->year + TIME_NTP_EPOCH)) - + date->day_of_year - 1); - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a 32 bit time stamp into a date structure. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date) -{ - // convert 32 bit timestamp to 64 bit - sl_sleeptimer_timestamp_64_t temp_time = (uint64_t)time + TIME_64_TO_32_EPOCH_OFFSET_SEC; - sl_status_t err_code = sl_sleeptimer_convert_time_to_date_64(temp_time, time_zone, date); - return err_code; -} - -/******************************************************************************* - * Convert a 64 bit time stamp into a date structure. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date) -{ - uint16_t full_year = 0; - uint16_t leap_day = 0; - uint8_t leap_year_flag = 0; - uint8_t current_month = 0; - - if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, time_zone)) { - return SL_STATUS_INVALID_PARAMETER; - } - - time += time_zone; // add UTC offset to convert to Standard Time - date->sec = time % 60; - time /= 60; - date->min = time % 60; - time /= 60; - date->hour = time % 24; - time /= 24; // time is now the number of days since 1900 - - date->day_of_week = (sl_sleeptimer_weekDay_t)compute_day_of_week_64(time); - - full_year = time / TIME_DAY_PER_YEAR; // Approximates the number of full years - uint32_t base_year = 1900u; - uint32_t current_year = full_year + base_year; - - if (full_year > 4) { // 1904 is the first leap year since 1900 - leap_day = number_of_leap_days(base_year, current_year); // Approximates the number of leap days. - full_year = (time - leap_day) / TIME_DAY_PER_YEAR; // Computes the number of year integrating the leap days. - current_year = full_year + base_year; - leap_day = number_of_leap_days(base_year, current_year); // Computes the actual number of leap days of the previous years. - } - date->year = full_year; // Year in date struct must be based on a 1900 epoch. - if (is_leap_year(date->year)) { - leap_year_flag = 1; - } - - time = (time - leap_day) - (TIME_DAY_PER_YEAR * full_year); // Subtracts days of previous year. - date->day_of_year = time + 1; - - while (time >= days_in_month[leap_year_flag][current_month]) { - time -= days_in_month[leap_year_flag][current_month]; // Subtracts the number of days of the passed month. - current_month++; - } - date->month = (sl_sleeptimer_month_t)current_month; - date->month_day = time + 1; - date->time_zone = time_zone; - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a date structure into a 32 bit time stamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_t *time) -{ - // Create a 64 bit time stamp - sl_sleeptimer_timestamp_64_t temp_time = 0; - sl_status_t err_code = sl_sleeptimer_convert_date_to_time_64(date, &temp_time); - - if (err_code != SL_STATUS_OK) { - return err_code; - } - // Convert 64 bit time to 32 bit time - - sl_sleeptimer_timestamp_64_t time_32 = temp_time; - time_32 -= TIME_64_TO_32_EPOCH_OFFSET_SEC; - *time = (time_32 & 0xFFFFFFFF); - - return err_code; -} - -/******************************************************************************* - * Convert a date structure into a 64 bit time stamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_64_t *time) -{ - uint16_t month_days = 0; - uint8_t month; - uint16_t full_year = 0; - uint8_t leap_year_flag = 0; - uint16_t leap_days = 0; - - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - full_year = (date->year); // base year for 64 bits its 1900 not 1970 - month = date->month; // offset to get months value from 1 to 12. - - uint32_t base_year = 1900u; - uint32_t current_year = full_year + base_year; - - *time = (full_year * (uint64_t)TIME_SEC_PER_YEAR); - - if (full_year > 4) { // 1904 is the first leap year since 1900 - leap_days = number_of_leap_days(base_year, current_year); - month_days = leap_days; - } - - if (is_leap_year(date->year)) { - leap_year_flag = 1; - } - - for (int i = 0; i < month; i++) { - month_days += days_in_month[leap_year_flag][i]; // Add the number of days of the month of the year. - } - - month_days += (date->month_day - 1); // Add full days of the current month. - *time += month_days * TIME_SEC_PER_DAY; - *time += (3600 * date->hour) + (60 * date->min) + date->sec; - *time -= date->time_zone; - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a date structure to string. - ******************************************************************************/ -uint32_t sl_sleeptimer_convert_date_to_str(char *str, - size_t size, - const uint8_t *format, - sl_sleeptimer_date_t *date) -{ - uint32_t return_size = 0u; - if (is_valid_date(date)) { - struct tm date_struct; - - date_struct.tm_hour = date->hour; - date_struct.tm_mday = date->month_day; - date_struct.tm_min = date->min; - date_struct.tm_mon = date->month; - date_struct.tm_sec = date->sec; - date_struct.tm_wday = date->day_of_week; - date_struct.tm_yday = date->day_of_year; - date_struct.tm_year = date->year; - - return_size = strftime(str, - size, - (const char *)format, - &date_struct); - } - - return return_size; -} - -/***************************************************************************//** - * Sets time zone offset. - * - * @param offset Time zone offset, in seconds. - ******************************************************************************/ -void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - tz_offset = offset; - CORE_EXIT_ATOMIC(); -} - -/***************************************************************************//** - * Gets time zone offset. - * - * @return Time zone offset, in seconds. - ******************************************************************************/ -sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void) -{ - sl_sleeptimer_time_zone_offset_t offset; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - offset = tz_offset; - CORE_EXIT_ATOMIC(); - - return offset; -} - -/***************************************************************************//** - * Converts Unix 32 timestamp into NTP timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, - uint32_t *ntp_time) -{ - if (time > TIME_UNIX_TO_NTP_MAX) { - // Maximum Unix timestamp that can be converted to NTP is 2085978495 - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t temp_ntp_time; - temp_ntp_time = time + TIME_NTP_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_ntp_time, TIME_FORMAT_NTP, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *ntp_time = temp_ntp_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts NTP timestamp into Unix timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, - sl_sleeptimer_timestamp_t *time) -{ - uint32_t temp_time; - temp_time = ntp_time - TIME_NTP_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *time = temp_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts Unix timestamp into Zigbee timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, - uint32_t *zigbee_time) -{ - uint32_t temp_zigbee_time; - temp_zigbee_time = time - TIME_ZIGBEE_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_zigbee_time, TIME_FORMAT_ZIGBEE_CLUSTER, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *zigbee_time = temp_zigbee_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts Zigbee timestamp into Unix timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, - sl_sleeptimer_timestamp_t *time) -{ - uint32_t temp_time; - temp_time = zigbee_time + TIME_ZIGBEE_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *time = temp_time; - return SL_STATUS_OK; - } -} - -#endif // SL_SLEEPTIMER_WALLCLOCK_CONFIG - -/******************************************************************************* - * Active delay of 'time_ms' milliseconds. - ******************************************************************************/ -void sl_sleeptimer_delay_millisecond(uint16_t time_ms) -{ - volatile bool wait = true; - sl_status_t error_code; - sl_sleeptimer_timer_handle_t delay_timer; - uint32_t delay = sl_sleeptimer_ms_to_tick(time_ms); - - error_code = sl_sleeptimer_start_timer(&delay_timer, - delay, - delay_callback, - (void *)&wait, - 0, - 0); - if (error_code == SL_STATUS_OK) { - while (wait) { // Active delay loop. - } - } -} - -/******************************************************************************* - * Converts milliseconds in ticks. - ******************************************************************************/ -uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms) -{ - return (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000); -} - -/******************************************************************************* - * Converts 32-bits milliseconds in ticks. - ******************************************************************************/ -sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, - uint32_t *tick) -{ - if (time_ms <= max_millisecond_conversion) { - *tick = (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000u); - return SL_STATUS_OK; - } else { - return SL_STATUS_INVALID_PARAMETER; - } -} - -/***************************************************************************//** - * Gets the maximum value that can be passed to the functions that have a - * 32-bits time or timeout argument expressed in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_max_ms32_conversion(void) -{ - return max_millisecond_conversion; -} - -/******************************************************************************* - * Converts ticks in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick) -{ - uint32_t time_ms; - time_ms = 0; - - if (timer_frequency != 0u) { - if (is_power_of_2(timer_frequency)) { - time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); - } else { - time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); - } - } - - return time_ms; -} - -/******************************************************************************* - * Converts 64-bits ticks in milliseconds. - ******************************************************************************/ -sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, - uint64_t *ms) - -{ - if ((tick <= UINT64_MAX / 1000) - && (timer_frequency != 0u)) { - if (is_power_of_2(timer_frequency)) { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); - return SL_STATUS_OK; - } else { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); - return SL_STATUS_OK; - } - } else { - return SL_STATUS_INVALID_PARAMETER; - } -} - -/******************************************************************************* - * Process timer interrupt. - * - * @param local_flag Flag indicating the type of timer interrupt. - ******************************************************************************/ -void process_timer_irq(uint8_t local_flag) -{ - CORE_DECLARE_IRQ_STATE; - if (local_flag & SLEEPTIMER_EVENT_OF) { -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG - uint32_t timer_freq = sl_sleeptimer_get_timer_frequency(); - - overflow_tick_rest += calculated_tick_rest; - if (overflow_tick_rest >= timer_freq) { - second_count++; - overflow_tick_rest -= timer_freq; - } - second_count = second_count + calculated_sec_count; -#endif - overflow_counter++; - - update_delta_list(); - - if (timer_head) { - set_comparator_for_next_timer(); - } - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - sl_sleeptimer_timer_handle_t *current = NULL; - - uint32_t nb_timer_expire = 0u; - uint16_t option_flags = 0; - - CORE_ENTER_ATOMIC(); - // Make sure the timers list is up to date with the time elapsed since the last update - update_delta_list(); - - // Process all timers that have expired. - while ((timer_head) && (timer_head->delta == 0)) { - sl_sleeptimer_timer_handle_t *temp = timer_head; - current = timer_head; - int32_t periodic_correction = 0u; - int64_t timeout_temp = 0; - bool skip_remove = false; - - // Process timers with higher priority first - while ((temp != NULL) && (temp->delta == 0)) { - if (current->priority > temp->priority) { - current = temp; - } - temp = temp->next; - } - CORE_EXIT_ATOMIC(); - - // Check if current periodic timer was delayed more than its actual timeout value - // and keep it at the head of the timers list if it's the case so that the - // callback function can be called the number of required time. - if (current->timeout_periodic != 0u) { - timeout_temp = current->timeout_periodic; - - periodic_correction = sleeptimer_hal_get_counter() - current->timeout_expected_tc; - if (periodic_correction > timeout_temp) { - skip_remove = true; - current->timeout_expected_tc += current->timeout_periodic; - } - } - - // Remove current timer from timer list except if the current timer is a periodic timer - // that was intentionally kept at the head of the timers list. - if (skip_remove != true) { - CORE_ENTER_ATOMIC(); - delta_list_remove_timer(current); - CORE_EXIT_ATOMIC(); - } - - // Re-insert periodic timer that was previsouly removed from the list - // and compensate for any deviation from the periodic timer frequency. - if (current->timeout_periodic != 0u && skip_remove != true) { - timeout_temp -= periodic_correction; - EFM_ASSERT(timeout_temp >= 0); - // Compensate for drift caused by ms to ticks conversion - if (current->conversion_error > 0) { - // Increment accumulated error by the ms to ticks conversion error - current->accumulated_error += current->conversion_error; - // If the accumulated error exceeds a tick, subtract that tick from the next - // periodic timer's timeout value. - if (current->accumulated_error >= 1000) { - current->accumulated_error -= 1000; - timeout_temp -= 1; - current->timeout_expected_tc -= 1; - } - } - CORE_ENTER_ATOMIC(); - delta_list_insert_timer(current, (sl_sleeptimer_tick_count_t)timeout_temp); - current->timeout_expected_tc += current->timeout_periodic; - CORE_EXIT_ATOMIC(); - } - - // Save current option flag and the number of timers that expired. - option_flags = current->option_flags; - nb_timer_expire++; - - // Call current timer callback function if any. - if (current->callback != NULL) { - current->callback(current, current->callback_data); - } - - CORE_ENTER_ATOMIC(); - - // Re-update the list to account for delays during timer's callback. - update_delta_list(); - } - - // If the only timer expired is the internal Power Manager one, - // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. - sleep_on_isr_exit = false; - if (nb_timer_expire == 1u) { - if (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { - sleep_on_isr_exit = true; - } - } - - if (timer_head) { - set_comparator_for_next_timer(); - } else { - sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_ATOMIC(); - } -} - -/******************************************************************************* - * Timer expiration callback for the delay function. - * - * @param handle Pointer to handle to timer. - * @param data Pointer to delay flag. - ******************************************************************************/ -static void delay_callback(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - volatile bool *wait_flag = (bool *)data; - - (void)handle; // Unused parameter. - - *wait_flag = false; -} - -/******************************************************************************* - * Inserts a timer in the delta list. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in ticks. - ******************************************************************************/ -static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout) -{ - sl_sleeptimer_tick_count_t local_handle_delta = timeout; - -#ifdef SL_CATALOG_POWER_MANAGER_PRESENT - // If Power Manager is present, it's possible that a clock restore is needed right away - // if we are in the context of a deepsleep and the timeout value is smaller than the restore time. - // If it's the case, the restore will be started and the timeout value will be updated to match - // the restore delay. - if (handle->option_flags == 0) { - uint32_t wakeup_delay = sli_power_manager_get_restore_delay(); - - if (local_handle_delta < wakeup_delay) { - local_handle_delta = wakeup_delay; - sli_power_manager_initiate_restore(); - } - } -#endif - - handle->delta = local_handle_delta; - - if (timer_head != NULL) { - sl_sleeptimer_timer_handle_t *prev = NULL; - sl_sleeptimer_timer_handle_t *current = timer_head; - // Find timer position taking into accounts the deltas and priority. - while (current != NULL - && (local_handle_delta >= current->delta || current->delta == 0u - || (((local_handle_delta - current->delta) == 0) && (handle->priority > current->priority)))) { - local_handle_delta -= current->delta; - handle->delta = local_handle_delta; - prev = current; - current = current->next; - } - - // Insert timer in middle of delta list. - if (prev != NULL) { - prev->next = handle; - } else { - timer_head = handle; - } - handle->next = current; - - if (current != NULL) { - current->delta -= local_handle_delta; - } - } else { - timer_head = handle; - handle->next = NULL; - } -} - -/******************************************************************************* - * Removes a timer from delta list. - * - * @param handle Pointer to handle to timer. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) -{ - sl_sleeptimer_timer_handle_t *prev = NULL; - sl_sleeptimer_timer_handle_t *current = timer_head; - - // Retrieve timer in delta list. - while (current != NULL && current != handle) { - prev = current; - current = current->next; - } - - if (current != handle) { - return SL_STATUS_INVALID_STATE; - } - - if (prev != NULL) { - prev->next = handle->next; - } else { - timer_head = handle->next; - } - - // Update delta of next timer - if (handle->next != NULL) { - handle->next->delta += handle->delta; - } - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Sets comparator for next timer. - ******************************************************************************/ -static void set_comparator_for_next_timer(void) -{ - if (timer_head->delta > 0) { - sl_sleeptimer_tick_count_t compare_value; - - compare_value = last_delta_update_count + timer_head->delta; - - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_compare(compare_value); - } else { - // In case timer has already expire, don't attempt to set comparator. Just - // trigger compare match interrupt. - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); - } - - update_next_timer_to_expire_is_power_manager(); -} - -/******************************************************************************* - * Updates timer list's deltas. - ******************************************************************************/ -static void update_delta_list(void) -{ - sl_sleeptimer_tick_count_t current_cnt = sleeptimer_hal_get_counter(); - sl_sleeptimer_timer_handle_t *timer_handle = timer_head; - sl_sleeptimer_tick_count_t time_diff = current_cnt - last_delta_update_count; - - // Go through the delta timer list and update every necessary deltas - // according to the time elapsed since the last update. - while (timer_handle != NULL && time_diff > 0) { - if (timer_handle->delta >= time_diff) { - timer_handle->delta -= time_diff; - time_diff = 0; - } else { - time_diff -= timer_handle->delta; - timer_handle->delta = 0; - } - timer_handle = timer_handle->next; - } - - last_delta_update_count = current_cnt; -} - -/******************************************************************************* - * Creates and start a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_initial Initial timeout, in timer ticks. - * @param timeout_periodic Periodic timeout, in timer ticks. This timeout - * applies once timeoutInitial expires. Can be set to 0 for a one - * shot timer. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout_initial, - sl_sleeptimer_tick_count_t timeout_periodic, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - CORE_DECLARE_IRQ_STATE; - - handle->priority = priority; - handle->callback_data = callback_data; - handle->next = NULL; - handle->timeout_periodic = timeout_periodic; - handle->callback = callback; - handle->option_flags = option_flags; - if (timeout_periodic == 0) { - handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_initial; - } else { - handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_periodic; - } - - if (timeout_initial == 0) { - handle->delta = 0; - if (handle->callback != NULL) { - handle->callback(handle, handle->callback_data); - } - if (timeout_periodic != 0) { - timeout_initial = timeout_periodic; - } else { - return SL_STATUS_OK; - } - } - -#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ - && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - if (option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { - HFXO0->CTRL |= HFXO_CTRL_EM23ONDEMAND; - sleeptimer_hal_set_compare_prs_hfxo_startup(timeout_initial); - return SL_STATUS_OK; - } -#endif - - CORE_ENTER_CRITICAL(); - update_delta_list(); - delta_list_insert_timer(handle, timeout_initial); - - // If first timer, update timer comparator. - if (timer_head == handle) { - set_comparator_for_next_timer(); - } - - CORE_EXIT_CRITICAL(); - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Updates internal flag that indicates if next timer to expire is the power - * manager's one. - ******************************************************************************/ -static void update_next_timer_to_expire_is_power_manager(void) -{ - sl_sleeptimer_timer_handle_t *current = timer_head; - uint32_t delta_diff_with_first = 0; - - next_timer_to_expire_is_power_manager = false; - - while (delta_diff_with_first <= 1) { - if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { - next_timer_to_expire_is_power_manager = true; - break; - } - - current = current->next; - if (current == NULL) { - break; - } - - delta_diff_with_first += current->delta; - } -} - -/**************************************************************************//** - * Determines if the power manager's early wakeup expired during the last ISR - * and it was the only timer to expire in that period. - * - * @return true if power manager sleep can return to sleep, - * false otherwise. - *****************************************************************************/ -bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void) -{ - CORE_DECLARE_IRQ_STATE; - bool sleep; - - CORE_ENTER_ATOMIC(); - sleep = sleep_on_isr_exit; - CORE_EXIT_ATOMIC(); - - return sleep; -} - -/******************************************************************************* - * Convert dividend to logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param div An unscaled dividend. - * - * @return Logarithm of 2. - ******************************************************************************/ -__STATIC_INLINE uint32_t div_to_log2(uint32_t div) -{ - return 31UL - __CLZ(div); // Count leading zeroes and "reverse" result. -} - -/******************************************************************************* - * Determines if a number is a power of two. - * - * @param nbr Input value. - * - * @return True if the number is a power of two. - ******************************************************************************/ -__STATIC_INLINE bool is_power_of_2(uint32_t nbr) -{ - if ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u))) { - return true; - } else { - return false; - } -} - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -/******************************************************************************* - * Compute the day of the week. - * - * @param day Days since January 1st of 1970. - * - * @return the day of the week. - ******************************************************************************/ -static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day) -{ - return (sl_sleeptimer_weekDay_t)((day + 4) % 7); // January 1st was a Thursday(4) in 1970 -} - -/******************************************************************************* - * Compute the day of the week. - * - * @param day Days since January 1st of 1900. - * - * @return the day of the week. - ******************************************************************************/ -static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day) -{ - return (sl_sleeptimer_weekDay_t)((day + 1) % 7); // January 1st was a Monday(1) in 1900 -} - -/******************************************************************************* - * Compute the day of the year. This function assumes that the inputs are properly - * sanitized. - * - * @param month Number of months since January. - * @param day Day of the month - * @param is_leap_year Specifies if the year computed against is a leap year. - * - * @return the number of days since the beginning of the year - ******************************************************************************/ -static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool is_leap_year) -{ - uint8_t i; - uint16_t dayOfYear = 0; - - for (i = 0; i < month; ++i) { - dayOfYear += days_in_month[is_leap_year][i]; - } - dayOfYear += day; - - return dayOfYear; -} - -/******************************************************************************* - * Checks if the year is a leap year. - * - * @param year Year to check. - * - * @return true if the year is a leap year. False otherwise. - ******************************************************************************/ -static bool is_leap_year(uint16_t year) -{ - // 1900 is not a leap year but 0 % anything is 0. - if (year == 0) { - return false; - } - - bool leap_year; - - leap_year = (((year % 4u) == 0u) - && (((year % 100u) != 0u) || ((year % 400u) == 0u))) ? true : false; - - return (leap_year); -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param base_year Year to start from to compute leap days. - * @param current_year Year end at for computing leap days. - * - * @return leap_days Days number of leap days between base_year and current_year. - ******************************************************************************/ -static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year) -{ - // Regular leap years - uint16_t lo_reg = (base_year - 0) / 4; - uint16_t hi_reg = (current_year - 1) / 4; - uint16_t leap_days = hi_reg - lo_reg; - - // Account for non leap years - uint16_t lo_century = (base_year - 0) / 100; - uint16_t hi_century = (current_year - 1) / 100; - leap_days -= hi_century - lo_century; - - // Account for quad century leap years - uint16_t lo_quad = (base_year - 0) / 400; - uint16_t hi_quad = (current_year - 1) / 400; - leap_days += hi_quad - lo_quad; - - return (leap_days); -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param time Time stamp to check. - * @param format Format of the time. - * @param time_zone Time zone offset in second. - * - * @return true if the time is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_time(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone) -{ - bool valid_time = false; - - // Check for overflow. - if ((time_zone < 0 && time > (uint32_t)abs(time_zone)) \ - || (time_zone >= 0 && (time <= UINT32_MAX - time_zone))) { - valid_time = true; - } - if (format == TIME_FORMAT_UNIX) { - if (time > TIME_UNIX_TIMESTAMP_MAX) { // Check if Unix time stamp is an unsigned 31 bits. - valid_time = false; - } - } else { - if ((format == TIME_FORMAT_NTP) && (time >= TIME_NTP_EPOCH_OFFSET_SEC)) { - valid_time &= true; - } else if ((format == TIME_FORMAT_ZIGBEE_CLUSTER) && (time <= TIME_UNIX_TIMESTAMP_MAX - TIME_ZIGBEE_EPOCH_OFFSET_SEC)) { - valid_time &= true; - } else { - valid_time = false; - } - } - return valid_time; -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param time Time stamp to check. - * @param format Format of the time. - * @param time_zone Time zone offset in second. - * - * @return true if the time is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone) -{ - bool valid_time = false; - - // Check for overflow. - if ((time_zone < 0 && time > (uint64_t)abs(time_zone)) - || (time_zone >= 0 && (time <= UINT64_MAX - time_zone))) { - valid_time = true; - } - if (format == TIME_FORMAT_UNIX_64_BIT) { - if (time > TIME_64_BIT_UNIX_TIMESTAMP_MAX) { // Check if time stamp is an unsigned 64 bits. - valid_time = false; - } - } - return valid_time; -} - -/******************************************************************************* - * Checks if the date is valid. - * - * @param date Date to check. - * - * @return true if the date is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_date(sl_sleeptimer_date_t *date) -{ - if ((date == NULL) - || (date->year > TIME_UNIX_YEAR_MAX) - || (date->month > MONTH_DECEMBER) - || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) - || (date->hour > 23) - || (date->min > 59) - || (date->sec > 59)) { - return false; - } - - // Unix is valid until the 19th of January 2038 at 03:14:07 - if (date->year == TIME_UNIX_YEAR_MAX) { - if ((uint8_t)date->month > (uint8_t)MONTH_JANUARY) { - return false; - } else if (date->month_day > 19) { - return false; - } else if (date->hour > 3) { - return false; - } else if (date->min > 14) { - return false; - } else if (date->sec > 7) { - return false; - } - } - - return true; -} - -/******************************************************************************* - * Checks if the date is valid. - * - * @param date Date to check. - * - * @return true if the date is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_date_64(sl_sleeptimer_date_t *date) -{ - if ((date == NULL) - || (date->year > TIME_64_BIT_YEAR_MAX) - || (date->month > MONTH_DECEMBER) - || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) - || (date->hour > 23) - || (date->min > 59) - || (date->sec > 59)) { - return false; - } - return true; -} -#endif - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sl_sleeptimer_get_clock_accuracy(void) -{ - return sleeptimer_hal_get_clock_accuracy(); -} - -/***************************************************************************//** - * @brief - * Update sleep_on_isr_exit flag. - * - * @param flag Value update_sleep_on_isr_exit will be set to. - ******************************************************************************/ -void sli_sleeptimer_update_sleep_on_isr_exit(bool flag) -{ - sleep_on_isr_exit = flag; -} - -/******************************************************************************* - * Gets the associated peripheral capture channel current value. - ******************************************************************************/ -uint32_t sli_sleeptimer_get_capture(void) -{ - return sleeptimer_hal_get_capture(); -} - -/******************************************************************************* - * Resets the PRS signal triggered by the associated peripheral. - ******************************************************************************/ -void sli_sleeptimer_reset_prs_signal(void) -{ - sleeptimer_hal_reset_prs_signal(); -} +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include + +#include "em_device.h" +#include "em_core_generic.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "sl_atomic.h" +#include "sl_sleeptimer_config.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#include "sli_power_manager.h" +#endif + +#define TIME_UNIX_EPOCH (1970u) +#define TIME_NTP_EPOCH (1900u) +#define TIME_ZIGBEE_EPOCH (2000u) +#define TIME_64_EPOCH TIME_NTP_EPOCH +#define TIME_NTP_UNIX_EPOCH_DIFF (TIME_UNIX_EPOCH - TIME_NTP_EPOCH) +#define TIME_ZIGBEE_UNIX_EPOCH_DIFF (TIME_ZIGBEE_EPOCH - TIME_UNIX_EPOCH) +#define TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH (TIME_NTP_UNIX_EPOCH_DIFF * 365u + 17u) ///< 70 years and 17 leap days +#define TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH (TIME_ZIGBEE_UNIX_EPOCH_DIFF * 365u + 7u) ///< 30 years and 7 leap days +#define TIME_SEC_PER_DAY (60u * 60u * 24u) +#define TIME_NTP_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_ZIGBEE_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_DAY_PER_YEAR (365u) +#define TIME_SEC_PER_YEAR (TIME_SEC_PER_DAY * TIME_DAY_PER_YEAR) +#define TIME_UNIX_TIMESTAMP_MAX (0x7FFFFFFF) +#define TIME_64_BIT_UNIX_TIMESTAMP_MAX (0x497968BD7F) /// Max 64 bit timestamp supported is 11:59:59 PM 12/31/11899 +#define TIME_UNIX_YEAR_MAX (2038u - TIME_NTP_EPOCH) ///< Max UNIX year based from a 1900 epoch +#define TIME_64_BIT_YEAR_MAX (11899u - TIME_NTP_EPOCH) ///< Max 64 bit format year based from a 1900 epoch +#define TIME_64_TO_32_EPOCH_OFFSET_SEC TIME_NTP_EPOCH_OFFSET_SEC +#define TIME_UNIX_TO_NTP_MAX (0xFFFFFFFF - TIME_NTP_EPOCH_OFFSET_SEC) + +// Minimum count difference used when evaluating if a timer expired or not after an interrupt +// by comparing the current count value and the expected expiration count value. +// The difference should be null or of few ticks since the counter never stop. +#define MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION 2 + +/// @brief Time Format. +SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { + TIME_FORMAT_UNIX = 0, ///< Number of seconds since January 1, 1970, 00:00. Type is signed, so represented on 31 bit. + TIME_FORMAT_NTP = 1, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_ZIGBEE_CLUSTER = 2, ///< Number of seconds since January 1, 2000, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_UNIX_64_BIT = 3, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 64 bit. +}; + +// tick_count, it can wrap around. +typedef uint32_t sl_sleeptimer_tick_count_t; + +// Overflow counter used to provide 64-bits tick count. +static volatile uint16_t overflow_counter; + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +// Current time count. +static sl_sleeptimer_timestamp_64_t second_count; +// Tick rest when the frequency is not a divider of the timer width. +static uint32_t overflow_tick_rest = 0; +// Current time zone offset. +static sl_sleeptimer_time_zone_offset_t tz_offset = 0; +// Precalculated tick rest in case of overflow. +static uint32_t calculated_tick_rest = 0; +// Precalculated timer overflow duration in seconds. +static uint32_t calculated_sec_count = 0; +#endif + +// Timer frequency in Hz. +static uint32_t timer_frequency; + +// Head of timer list. +static sl_sleeptimer_timer_handle_t *timer_head; + +// Count at last update of delta of first timer. +static volatile sl_sleeptimer_tick_count_t last_delta_update_count; + +// Initialization flag. +static bool is_sleeptimer_initialized = false; + +// Flag that indicates if power manager's timer will expire at next compare match. +static bool next_timer_to_expire_is_power_manager = false; + +// Precalculated value to avoid millisecond to tick conversion overflow. +static uint32_t max_millisecond_conversion; + +// Sleep on ISR exit flag. +static bool sleep_on_isr_exit = false; + +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout); + +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); + +static void set_comparator_for_next_timer(void); + +static void update_delta_list(void); + +__STATIC_INLINE uint32_t div_to_log2(uint32_t div); + +__STATIC_INLINE bool is_power_of_2(uint32_t nbr); + +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +static void update_next_timer_to_expire_is_power_manager(void); + +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data); + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +static bool is_leap_year(uint16_t year); +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year); + +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day); +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day); +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool isLeapYear); + +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_date(sl_sleeptimer_date_t *date); + +static bool is_valid_date_64(sl_sleeptimer_date_t *date); + +static const uint8_t days_in_month[2u][12] = { + /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ + { 31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u }, + { 31u, 29u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u } +}; +#endif + +/**************************************************************************//** + * Initializes sleep timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (!is_sleeptimer_initialized) { + timer_head = NULL; + last_delta_update_count = 0u; + overflow_counter = 0u; + sleeptimer_hal_init_timer(); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_OF); + timer_frequency = sleeptimer_hal_get_timer_frequency(); + if (timer_frequency == 0) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_INVALID_CONFIGURATION; + } + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + second_count = 0; + calculated_tick_rest = ((uint64_t)UINT32_MAX + 1) % (uint64_t)timer_frequency; + calculated_sec_count = (((uint64_t)UINT32_MAX + 1) / (uint64_t)timer_frequency); +#endif + max_millisecond_conversion = (uint32_t)(((uint64_t)UINT32_MAX * (uint64_t)1000u) / timer_frequency); + is_sleeptimer_initialized = true; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Starts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_NOT_READY; + } + + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer is not running. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Stops a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t error; + bool set_comparator = false; + + // Disable PRS compare and capture channel, if configured for early wakeup +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (handle->option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + sleeptimer_hal_disable_prs_compare_and_capture_channel(); + } +#endif + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_CRITICAL(); + update_delta_list(); + + // If first timer in list, update timer comparator. + if (timer_head == handle) { + set_comparator = true; + } + + error = delta_list_remove_timer(handle); + if (error != SL_STATUS_OK) { + CORE_EXIT_CRITICAL(); + + return error; + } + + if (set_comparator && timer_head) { + set_comparator_for_next_timer(); + } else if (!timer_head) { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the status of a timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, + bool *running) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || running == NULL) { + return SL_STATUS_NULL_POINTER; + } else { + *running = false; + CORE_ENTER_ATOMIC(); + current = timer_head; + while (current != NULL && !*running) { + if (current == handle) { + *running = true; + } else { + current = current->next; + } + } + CORE_EXIT_ATOMIC(); + } + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets a 32 bits timer's time remaining. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, + uint32_t *time) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || time == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + update_delta_list(); + *time = handle->delta; + + // Retrieve timer in list and add the deltas. + current = timer_head; + while (current != handle && current != NULL) { + *time += current->delta; + current = current->next; + } + + if (current != handle) { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_NOT_READY; + } + + // Substract time since last compare match. + if (*time > sleeptimer_hal_get_counter() - last_delta_update_count) { + *time -= sleeptimer_hal_get_counter() - last_delta_update_count; + } else { + *time = 0; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + uint32_t time = 0; + + CORE_ENTER_ATOMIC(); + // parse list and retrieve first timer with option flags requirement. + current = timer_head; + while (current != NULL) { + // save time remaining for timer. + time += current->delta; + // Check if the current timer has the flags requested + if (current->option_flags == option_flags + || option_flags == SL_SLEEPTIMER_ANY_FLAG) { + // Substract time since last compare match. + if (time > (sleeptimer_hal_get_counter() - last_delta_update_count)) { + time -= (sleeptimer_hal_get_counter() - last_delta_update_count); + } else { + time = 0; + } + *time_remaining = time; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; + } + current = current->next; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_EMPTY; +} + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SL_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @note This function is for internal use only. + * + * @note A check to validate that the Power Manager Sleeptimer is expired on + * top of being the next timer was added. This is because + * this function is called when coming back from EM2 sleep to validate + * that the system woke up because of this precise timer expiration. + * Some race conditions, seen with FreeRTOS, could create invalid RTC + * interrupt leading to believe that the power manager timer was expired + * when it was not. + *****************************************************************************/ +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) +{ + bool next_timer_is_power_manager; + + sl_atomic_load(next_timer_is_power_manager, next_timer_to_expire_is_power_manager); + + // Make sure that the Power Manager Sleeptimer is actually expired in addition + // to being the next timer. + if ((next_timer_is_power_manager) + && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { + next_timer_is_power_manager = false; + } + + return next_timer_is_power_manager; +} + +/***************************************************************************//** +* Gets current 32 bits tick count. +*******************************************************************************/ +uint32_t sl_sleeptimer_get_tick_count(void) +{ + uint32_t cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + cnt = sleeptimer_hal_get_counter(); + CORE_EXIT_ATOMIC(); + + return cnt; +} + +/***************************************************************************//** +* Gets current 64 bits tick count. +*******************************************************************************/ +uint64_t sl_sleeptimer_get_tick_count64(void) +{ + uint32_t tick_cnt; + uint32_t of_cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt = overflow_counter; + + if (sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_OF)) { + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt++; + } + CORE_EXIT_ATOMIC(); + + return (((uint64_t) of_cnt) << 32) | tick_cnt; +} + +/***************************************************************************//** + * Get timer frequency. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_timer_frequency(void) +{ + return timer_frequency; +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/***************************************************************************//** + * Retrieves current 32 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void) +{ + uint64_t temp_time = sl_sleeptimer_get_time_64(); + // Add offset for 64 to 32 bit time + if (temp_time >= TIME_64_TO_32_EPOCH_OFFSET_SEC) { + temp_time -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + } + // Return lower 32 bits of 64 bit time + uint32_t time = (temp_time & 0xFFFFFFFF); + + return time; +} + +/***************************************************************************//** + * Retrieves current 64 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void) +{ + uint32_t cnt = 0u; + uint32_t freq = 0u; + sl_sleeptimer_timestamp_64_t time; + CORE_DECLARE_IRQ_STATE; + + cnt = sleeptimer_hal_get_counter(); + freq = sl_sleeptimer_get_timer_frequency(); + + CORE_ENTER_ATOMIC(); + time = second_count + cnt / freq; + + if (cnt % freq + overflow_tick_rest >= freq) { + time++; + } + CORE_EXIT_ATOMIC(); + + return time; +} + +/***************************************************************************//** + * Sets current time from 32 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time) +{ + // convert 32 bit time to 64 bit time + uint64_t temp_time = time + TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_set_time_64(temp_time); + return err_code; +} + +/***************************************************************************//** + * Sets current time from 64 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time) +{ + uint32_t freq = 0u; + uint32_t counter_sec = 0u; + uint32_t cnt = 0; + CORE_DECLARE_IRQ_STATE; + + // convert 64 bit time to 32 bit time + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } + + freq = sl_sleeptimer_get_timer_frequency(); + cnt = sleeptimer_hal_get_counter(); + + CORE_ENTER_ATOMIC(); + // store 64 bit time as 64 bits's + second_count = time; + + // Convert 64 bit time to 32 bit time in order to check for overflow + // i.e. if 32 bit time is >=counter_sec + uint64_t temp_time = second_count - TIME_64_TO_32_EPOCH_OFFSET_SEC; + uint32_t second_time_32 = (temp_time & 0xFFFFFFFF); + + overflow_tick_rest = 0; + counter_sec = cnt / freq; + + if (second_time_32 >= counter_sec) { + second_count -= counter_sec; + } else { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets current date. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_sleeptimer_time_zone_offset_t tz; + sl_status_t err_code = SL_STATUS_OK; + + // Fetch 64 bit timestamp + time = sl_sleeptimer_get_time_64(); + tz = sl_sleeptimer_get_tz(); + err_code = sl_sleeptimer_convert_time_to_date_64(time, tz, date); + + return err_code; +} + +/***************************************************************************//** + * Sets current time, in date format. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_status_t err_code = SL_STATUS_OK; + CORE_DECLARE_IRQ_STATE; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + err_code = sl_sleeptimer_convert_date_to_time_64(date, &time); + if (err_code != SL_STATUS_OK) { + return err_code; + } + + CORE_ENTER_ATOMIC(); + // sets the 64 bit second_time value + err_code = sl_sleeptimer_set_time_64(time); + if (err_code == SL_STATUS_OK) { + sl_sleeptimer_set_tz(date->time_zone); + } + CORE_EXIT_ATOMIC(); + + return err_code; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // If year is smaller than 1900, assume NTP Epoch is used. + date->year = ((year < TIME_NTP_EPOCH) ? year : (year - TIME_NTP_EPOCH)); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week(((date->year - TIME_NTP_UNIX_EPOCH_DIFF) * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_UNIX_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Ensure that year is greater than 1900 and based on 0 epoch + if (year < TIME_NTP_EPOCH) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Convert year based on 0 epoch to a valid date->year based on 1900 epoch + date->year = (year - TIME_NTP_EPOCH); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week_64((date->year * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_NTP_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a 32 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + // convert 32 bit timestamp to 64 bit + sl_sleeptimer_timestamp_64_t temp_time = (uint64_t)time + TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_convert_time_to_date_64(temp_time, time_zone, date); + return err_code; +} + +/******************************************************************************* + * Convert a 64 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + uint16_t full_year = 0; + uint16_t leap_day = 0; + uint8_t leap_year_flag = 0; + uint8_t current_month = 0; + + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, time_zone)) { + return SL_STATUS_INVALID_PARAMETER; + } + + time += time_zone; // add UTC offset to convert to Standard Time + date->sec = time % 60; + time /= 60; + date->min = time % 60; + time /= 60; + date->hour = time % 24; + time /= 24; // time is now the number of days since 1900 + + date->day_of_week = (sl_sleeptimer_weekDay_t)compute_day_of_week_64(time); + + full_year = time / TIME_DAY_PER_YEAR; // Approximates the number of full years + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_day = number_of_leap_days(base_year, current_year); // Approximates the number of leap days. + full_year = (time - leap_day) / TIME_DAY_PER_YEAR; // Computes the number of year integrating the leap days. + current_year = full_year + base_year; + leap_day = number_of_leap_days(base_year, current_year); // Computes the actual number of leap days of the previous years. + } + date->year = full_year; // Year in date struct must be based on a 1900 epoch. + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + time = (time - leap_day) - (TIME_DAY_PER_YEAR * full_year); // Subtracts days of previous year. + date->day_of_year = time + 1; + + while (time >= days_in_month[leap_year_flag][current_month]) { + time -= days_in_month[leap_year_flag][current_month]; // Subtracts the number of days of the passed month. + current_month++; + } + date->month = (sl_sleeptimer_month_t)current_month; + date->month_day = time + 1; + date->time_zone = time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure into a 32 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time) +{ + // Create a 64 bit time stamp + sl_sleeptimer_timestamp_64_t temp_time = 0; + sl_status_t err_code = sl_sleeptimer_convert_date_to_time_64(date, &temp_time); + + if (err_code != SL_STATUS_OK) { + return err_code; + } + // Convert 64 bit time to 32 bit time + + sl_sleeptimer_timestamp_64_t time_32 = temp_time; + time_32 -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + *time = (time_32 & 0xFFFFFFFF); + + return err_code; +} + +/******************************************************************************* + * Convert a date structure into a 64 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time) +{ + uint16_t month_days = 0; + uint8_t month; + uint16_t full_year = 0; + uint8_t leap_year_flag = 0; + uint16_t leap_days = 0; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + full_year = (date->year); // base year for 64 bits its 1900 not 1970 + month = date->month; // offset to get months value from 1 to 12. + + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + *time = (full_year * (uint64_t)TIME_SEC_PER_YEAR); + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_days = number_of_leap_days(base_year, current_year); + month_days = leap_days; + } + + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + for (int i = 0; i < month; i++) { + month_days += days_in_month[leap_year_flag][i]; // Add the number of days of the month of the year. + } + + month_days += (date->month_day - 1); // Add full days of the current month. + *time += month_days * TIME_SEC_PER_DAY; + *time += (3600 * date->hour) + (60 * date->min) + date->sec; + *time -= date->time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure to string. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date) +{ + uint32_t return_size = 0u; + if (is_valid_date(date)) { + struct tm date_struct; + + date_struct.tm_hour = date->hour; + date_struct.tm_mday = date->month_day; + date_struct.tm_min = date->min; + date_struct.tm_mon = date->month; + date_struct.tm_sec = date->sec; + date_struct.tm_wday = date->day_of_week; + date_struct.tm_yday = date->day_of_year; + date_struct.tm_year = date->year; + + return_size = strftime(str, + size, + (const char *)format, + &date_struct); + } + + return return_size; +} + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tz_offset = offset; + CORE_EXIT_ATOMIC(); +} + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void) +{ + sl_sleeptimer_time_zone_offset_t offset; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + offset = tz_offset; + CORE_EXIT_ATOMIC(); + + return offset; +} + +/***************************************************************************//** + * Converts Unix 32 timestamp into NTP timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time) +{ + if (time > TIME_UNIX_TO_NTP_MAX) { + // Maximum Unix timestamp that can be converted to NTP is 2085978495 + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t temp_ntp_time; + temp_ntp_time = time + TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_ntp_time, TIME_FORMAT_NTP, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *ntp_time = temp_ntp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = ntp_time - TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time) +{ + uint32_t temp_zigbee_time; + temp_zigbee_time = time - TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_zigbee_time, TIME_FORMAT_ZIGBEE_CLUSTER, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *zigbee_time = temp_zigbee_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = zigbee_time + TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +#endif // SL_SLEEPTIMER_WALLCLOCK_CONFIG + +/******************************************************************************* + * Active delay of 'time_ms' milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms) +{ + volatile bool wait = true; + sl_status_t error_code; + sl_sleeptimer_timer_handle_t delay_timer; + uint32_t delay = sl_sleeptimer_ms_to_tick(time_ms); + + error_code = sl_sleeptimer_start_timer(&delay_timer, + delay, + delay_callback, + (void *)&wait, + 0, + 0); + if (error_code == SL_STATUS_OK) { + while (wait) { // Active delay loop. + } + } +} + +/******************************************************************************* + * Converts milliseconds in ticks. + ******************************************************************************/ +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms) +{ + return (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000); +} + +/******************************************************************************* + * Converts 32-bits milliseconds in ticks. + ******************************************************************************/ +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick) +{ + if (time_ms <= max_millisecond_conversion) { + *tick = (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000u); + return SL_STATUS_OK; + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void) +{ + return max_millisecond_conversion; +} + +/******************************************************************************* + * Converts ticks in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick) +{ + uint32_t time_ms; + time_ms = 0; + + if (timer_frequency != 0u) { + if (is_power_of_2(timer_frequency)) { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + } else { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + } + } + + return time_ms; +} + +/******************************************************************************* + * Converts 64-bits ticks in milliseconds. + ******************************************************************************/ +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms) + +{ + if ((tick <= UINT64_MAX / 1000) + && (timer_frequency != 0u)) { + if (is_power_of_2(timer_frequency)) { + *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + return SL_STATUS_OK; + } else { + *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + return SL_STATUS_OK; + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/******************************************************************************* + * Process timer interrupt. + * + * @param local_flag Flag indicating the type of timer interrupt. + ******************************************************************************/ +void process_timer_irq(uint8_t local_flag) +{ + CORE_DECLARE_IRQ_STATE; + if (local_flag & SLEEPTIMER_EVENT_OF) { +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + uint32_t timer_freq = sl_sleeptimer_get_timer_frequency(); + + overflow_tick_rest += calculated_tick_rest; + if (overflow_tick_rest >= timer_freq) { + second_count++; + overflow_tick_rest -= timer_freq; + } + second_count = second_count + calculated_sec_count; +#endif + overflow_counter++; + + update_delta_list(); + + if (timer_head) { + set_comparator_for_next_timer(); + } + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sl_sleeptimer_timer_handle_t *current = NULL; + + uint32_t nb_timer_expire = 0u; + uint16_t option_flags = 0; + + CORE_ENTER_ATOMIC(); + // Make sure the timers list is up to date with the time elapsed since the last update + update_delta_list(); + + // Process all timers that have expired. + while ((timer_head) && (timer_head->delta == 0)) { + sl_sleeptimer_timer_handle_t *temp = timer_head; + current = timer_head; + int32_t periodic_correction = 0u; + int64_t timeout_temp = 0; + bool skip_remove = false; + + // Process timers with higher priority first + while ((temp != NULL) && (temp->delta == 0)) { + if (current->priority > temp->priority) { + current = temp; + } + temp = temp->next; + } + CORE_EXIT_ATOMIC(); + + // Check if current periodic timer was delayed more than its actual timeout value + // and keep it at the head of the timers list if it's the case so that the + // callback function can be called the number of required time. + if (current->timeout_periodic != 0u) { + timeout_temp = current->timeout_periodic; + + periodic_correction = sleeptimer_hal_get_counter() - current->timeout_expected_tc; + if (periodic_correction > timeout_temp) { + skip_remove = true; + current->timeout_expected_tc += current->timeout_periodic; + } + } + + // Remove current timer from timer list except if the current timer is a periodic timer + // that was intentionally kept at the head of the timers list. + if (skip_remove != true) { + CORE_ENTER_ATOMIC(); + delta_list_remove_timer(current); + CORE_EXIT_ATOMIC(); + } + + // Re-insert periodic timer that was previsouly removed from the list + // and compensate for any deviation from the periodic timer frequency. + if (current->timeout_periodic != 0u && skip_remove != true) { + timeout_temp -= periodic_correction; + EFM_ASSERT(timeout_temp >= 0); + // Compensate for drift caused by ms to ticks conversion + if (current->conversion_error > 0) { + // Increment accumulated error by the ms to ticks conversion error + current->accumulated_error += current->conversion_error; + // If the accumulated error exceeds a tick, subtract that tick from the next + // periodic timer's timeout value. + if (current->accumulated_error >= 1000) { + current->accumulated_error -= 1000; + timeout_temp -= 1; + current->timeout_expected_tc -= 1; + } + } + CORE_ENTER_ATOMIC(); + delta_list_insert_timer(current, (sl_sleeptimer_tick_count_t)timeout_temp); + current->timeout_expected_tc += current->timeout_periodic; + CORE_EXIT_ATOMIC(); + } + + // Save current option flag and the number of timers that expired. + option_flags = current->option_flags; + nb_timer_expire++; + + // Call current timer callback function if any. + if (current->callback != NULL) { + current->callback(current, current->callback_data); + } + + CORE_ENTER_ATOMIC(); + + // Re-update the list to account for delays during timer's callback. + update_delta_list(); + } + + // If the only timer expired is the internal Power Manager one, + // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. + sleep_on_isr_exit = false; + if (nb_timer_expire == 1u) { + if (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { + sleep_on_isr_exit = true; + } + } + + if (timer_head) { + set_comparator_for_next_timer(); + } else { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_ATOMIC(); + } +} + +/******************************************************************************* + * Timer expiration callback for the delay function. + * + * @param handle Pointer to handle to timer. + * @param data Pointer to delay flag. + ******************************************************************************/ +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + volatile bool *wait_flag = (bool *)data; + + (void)handle; // Unused parameter. + + *wait_flag = false; +} + +/******************************************************************************* + * Inserts a timer in the delta list. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in ticks. + ******************************************************************************/ +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout) +{ + sl_sleeptimer_tick_count_t local_handle_delta = timeout; + +#ifdef SL_CATALOG_POWER_MANAGER_PRESENT + // If Power Manager is present, it's possible that a clock restore is needed right away + // if we are in the context of a deepsleep and the timeout value is smaller than the restore time. + // If it's the case, the restore will be started and the timeout value will be updated to match + // the restore delay. + if (handle->option_flags == 0) { + uint32_t wakeup_delay = sli_power_manager_get_restore_delay(); + + if (local_handle_delta < wakeup_delay) { + local_handle_delta = wakeup_delay; + sli_power_manager_initiate_restore(); + } + } +#endif + + handle->delta = local_handle_delta; + + if (timer_head != NULL) { + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + // Find timer position taking into accounts the deltas and priority. + while (current != NULL + && (local_handle_delta >= current->delta || current->delta == 0u + || (((local_handle_delta - current->delta) == 0) && (handle->priority > current->priority)))) { + local_handle_delta -= current->delta; + handle->delta = local_handle_delta; + prev = current; + current = current->next; + } + + // Insert timer in middle of delta list. + if (prev != NULL) { + prev->next = handle; + } else { + timer_head = handle; + } + handle->next = current; + + if (current != NULL) { + current->delta -= local_handle_delta; + } + } else { + timer_head = handle; + handle->next = NULL; + } +} + +/******************************************************************************* + * Removes a timer from delta list. + * + * @param handle Pointer to handle to timer. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) +{ + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + + // Retrieve timer in delta list. + while (current != NULL && current != handle) { + prev = current; + current = current->next; + } + + if (current != handle) { + return SL_STATUS_INVALID_STATE; + } + + if (prev != NULL) { + prev->next = handle->next; + } else { + timer_head = handle->next; + } + + // Update delta of next timer + if (handle->next != NULL) { + handle->next->delta += handle->delta; + } + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Sets comparator for next timer. + ******************************************************************************/ +static void set_comparator_for_next_timer(void) +{ + if (timer_head->delta > 0) { + sl_sleeptimer_tick_count_t compare_value; + + compare_value = last_delta_update_count + timer_head->delta; + + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_compare(compare_value); + } else { + // In case timer has already expire, don't attempt to set comparator. Just + // trigger compare match interrupt. + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); + } + + update_next_timer_to_expire_is_power_manager(); +} + +/******************************************************************************* + * Updates timer list's deltas. + ******************************************************************************/ +static void update_delta_list(void) +{ + sl_sleeptimer_tick_count_t current_cnt = sleeptimer_hal_get_counter(); + sl_sleeptimer_timer_handle_t *timer_handle = timer_head; + sl_sleeptimer_tick_count_t time_diff = current_cnt - last_delta_update_count; + + // Go through the delta timer list and update every necessary deltas + // according to the time elapsed since the last update. + while (timer_handle != NULL && time_diff > 0) { + if (timer_handle->delta >= time_diff) { + timer_handle->delta -= time_diff; + time_diff = 0; + } else { + time_diff -= timer_handle->delta; + timer_handle->delta = 0; + } + timer_handle = timer_handle->next; + } + + last_delta_update_count = current_cnt; +} + +/******************************************************************************* + * Creates and start a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_initial Initial timeout, in timer ticks. + * @param timeout_periodic Periodic timeout, in timer ticks. This timeout + * applies once timeoutInitial expires. Can be set to 0 for a one + * shot timer. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + CORE_DECLARE_IRQ_STATE; + + handle->priority = priority; + handle->callback_data = callback_data; + handle->next = NULL; + handle->timeout_periodic = timeout_periodic; + handle->callback = callback; + handle->option_flags = option_flags; + if (timeout_periodic == 0) { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_initial; + } else { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_periodic; + } + + if (timeout_initial == 0) { + handle->delta = 0; + if (handle->callback != NULL) { + handle->callback(handle, handle->callback_data); + } + if (timeout_periodic != 0) { + timeout_initial = timeout_periodic; + } else { + return SL_STATUS_OK; + } + } + +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + HFXO0->CTRL |= HFXO_CTRL_EM23ONDEMAND; + sleeptimer_hal_set_compare_prs_hfxo_startup(timeout_initial); + return SL_STATUS_OK; + } +#endif + + CORE_ENTER_CRITICAL(); + update_delta_list(); + delta_list_insert_timer(handle, timeout_initial); + + // If first timer, update timer comparator. + if (timer_head == handle) { + set_comparator_for_next_timer(); + } + + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Updates internal flag that indicates if next timer to expire is the power + * manager's one. + ******************************************************************************/ +static void update_next_timer_to_expire_is_power_manager(void) +{ + sl_sleeptimer_timer_handle_t *current = timer_head; + uint32_t delta_diff_with_first = 0; + + next_timer_to_expire_is_power_manager = false; + + while (delta_diff_with_first <= 1) { + if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { + next_timer_to_expire_is_power_manager = true; + break; + } + + current = current->next; + if (current == NULL) { + break; + } + + delta_diff_with_first += current->delta; + } +} + +/**************************************************************************//** + * Determines if the power manager's early wakeup expired during the last ISR + * and it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + *****************************************************************************/ +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void) +{ + CORE_DECLARE_IRQ_STATE; + bool sleep; + + CORE_ENTER_ATOMIC(); + sleep = sleep_on_isr_exit; + CORE_EXIT_ATOMIC(); + + return sleep; +} + +/******************************************************************************* + * Convert dividend to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param div An unscaled dividend. + * + * @return Logarithm of 2. + ******************************************************************************/ +__STATIC_INLINE uint32_t div_to_log2(uint32_t div) +{ + return 31UL - __CLZ(div); // Count leading zeroes and "reverse" result. +} + +/******************************************************************************* + * Determines if a number is a power of two. + * + * @param nbr Input value. + * + * @return True if the number is a power of two. + ******************************************************************************/ +__STATIC_INLINE bool is_power_of_2(uint32_t nbr) +{ + if ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u))) { + return true; + } else { + return false; + } +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1970. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 4) % 7); // January 1st was a Thursday(4) in 1970 +} + +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1900. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 1) % 7); // January 1st was a Monday(1) in 1900 +} + +/******************************************************************************* + * Compute the day of the year. This function assumes that the inputs are properly + * sanitized. + * + * @param month Number of months since January. + * @param day Day of the month + * @param is_leap_year Specifies if the year computed against is a leap year. + * + * @return the number of days since the beginning of the year + ******************************************************************************/ +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool is_leap_year) +{ + uint8_t i; + uint16_t dayOfYear = 0; + + for (i = 0; i < month; ++i) { + dayOfYear += days_in_month[is_leap_year][i]; + } + dayOfYear += day; + + return dayOfYear; +} + +/******************************************************************************* + * Checks if the year is a leap year. + * + * @param year Year to check. + * + * @return true if the year is a leap year. False otherwise. + ******************************************************************************/ +static bool is_leap_year(uint16_t year) +{ + // 1900 is not a leap year but 0 % anything is 0. + if (year == 0) { + return false; + } + + bool leap_year; + + leap_year = (((year % 4u) == 0u) + && (((year % 100u) != 0u) || ((year % 400u) == 0u))) ? true : false; + + return (leap_year); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param base_year Year to start from to compute leap days. + * @param current_year Year end at for computing leap days. + * + * @return leap_days Days number of leap days between base_year and current_year. + ******************************************************************************/ +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year) +{ + // Regular leap years + uint16_t lo_reg = (base_year - 0) / 4; + uint16_t hi_reg = (current_year - 1) / 4; + uint16_t leap_days = hi_reg - lo_reg; + + // Account for non leap years + uint16_t lo_century = (base_year - 0) / 100; + uint16_t hi_century = (current_year - 1) / 100; + leap_days -= hi_century - lo_century; + + // Account for quad century leap years + uint16_t lo_quad = (base_year - 0) / 400; + uint16_t hi_quad = (current_year - 1) / 400; + leap_days += hi_quad - lo_quad; + + return (leap_days); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint32_t)abs(time_zone)) \ + || (time_zone >= 0 && (time <= UINT32_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX) { + if (time > TIME_UNIX_TIMESTAMP_MAX) { // Check if Unix time stamp is an unsigned 31 bits. + valid_time = false; + } + } else { + if ((format == TIME_FORMAT_NTP) && (time >= TIME_NTP_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else if ((format == TIME_FORMAT_ZIGBEE_CLUSTER) && (time <= TIME_UNIX_TIMESTAMP_MAX - TIME_ZIGBEE_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else { + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint64_t)abs(time_zone)) + || (time_zone >= 0 && (time <= UINT64_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX_64_BIT) { + if (time > TIME_64_BIT_UNIX_TIMESTAMP_MAX) { // Check if time stamp is an unsigned 64 bits. + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_UNIX_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + + // Unix is valid until the 19th of January 2038 at 03:14:07 + if (date->year == TIME_UNIX_YEAR_MAX) { + if ((uint8_t)date->month > (uint8_t)MONTH_JANUARY) { + return false; + } else if (date->month_day > 19) { + return false; + } else if (date->hour > 3) { + return false; + } else if (date->min > 14) { + return false; + } else if (date->sec > 7) { + return false; + } + } + + return true; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date_64(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_64_BIT_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + return true; +} +#endif + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void) +{ + return sleeptimer_hal_get_clock_accuracy(); +} + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag) +{ + sleep_on_isr_exit = flag; +} + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + ******************************************************************************/ +uint32_t sli_sleeptimer_get_capture(void) +{ + return sleeptimer_hal_get_capture(); +} + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +void sli_sleeptimer_reset_prs_signal(void) +{ + sleeptimer_hal_reset_prs_signal(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c index a2435f4..6ea3a09 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c @@ -1,325 +1,325 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER Hardware abstraction implementation for BURTC. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" -#if defined(_SILICON_LABS_32B_SERIES_2) - -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_burtc.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_BURTC - -#if defined(_SILICON_LABS_32B_SERIES_0) -#error BURTC implementation of the sleeptimer not available on Series 0 chips -#endif - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define SLEEPTIMER_COMPARE_MIN_DIFF (5 + 1) -#else -#define SLEEPTIMER_COMPARE_MIN_DIFF (4 + 1) -#endif - -#define SLEEPTIMER_TMR_WIDTH (_BURTC_CNT_MASK) - -static uint32_t get_time_diff(uint32_t a, uint32_t b); - -/****************************************************************************** - * Convert HAL interrupt flag BURTC-interrupt-enable bitmask - *****************************************************************************/ -static uint32_t irqien_hal2burtc(uint8_t hal_flag) -{ - uint32_t burtc_if = 0u; - - if (hal_flag & SLEEPTIMER_EVENT_OF) { - burtc_if |= BURTC_IEN_OF; - } - - if (hal_flag & SLEEPTIMER_EVENT_COMP) { - burtc_if |= BURTC_IEN_COMP; - } - - return burtc_if; -} - -/****************************************************************************** - * Convert BURTC interrupt flags to HAL events - *****************************************************************************/ -static uint8_t irqflags_burtc2hal(uint32_t burtc_flag) -{ - uint8_t hal_if = 0u; - - if (burtc_flag & BURTC_IF_OF) { - hal_if |= SLEEPTIMER_EVENT_OF; - } - - if (burtc_flag & BURTC_IF_COMP) { - hal_if |= SLEEPTIMER_EVENT_COMP; - } - - return hal_if; -} - -/****************************************************************************** - * Initializes BURTC sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer() -{ - BURTC_Init_TypeDef burtc_init = BURTC_INIT_DEFAULT; - - CMU_ClockEnable(cmuClock_BURTC, true); - - burtc_init.start = false; - burtc_init.clkDiv = SL_SLEEPTIMER_FREQ_DIVIDER; -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - burtc_init.debugRun = true; -#endif - - BURTC_Init(&burtc_init); - BURTC_IntDisable(_BURTC_IEN_MASK); - BURTC_IntClear(_BURTC_IF_MASK); - BURTC_CounterReset(); - - BURTC_Start(); - BURTC_SyncWait(); - - // Setup BURTC interrupt - NVIC_ClearPendingIRQ(BURTC_IRQn); - NVIC_EnableIRQ(BURTC_IRQn); -} - -/****************************************************************************** - * Gets BURTC counter. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return BURTC_CounterGet(); -} - -/****************************************************************************** - * Gets BURTC compare value - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return BURTC_CompareGet(0U); -} - -/****************************************************************************** - * Sets BURTC compare value - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the BURTC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare_current; - uint32_t compare_new = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare_current = sleeptimer_hal_get_compare(); - - if (((BURTC_IntGet() & _BURTC_IF_COMP_MASK) != 0) - || get_time_diff(compare_current, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare_current == counter) { - // Add margin if necessary - if (get_time_diff(compare_new, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_new = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - - // wrap around if necessary - compare_new %= SLEEPTIMER_TMR_WIDTH; - - BURTC_CompareSet(0U, compare_new - 1); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_CRITICAL(); -} - -/****************************************************************************** - * Enables BURTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - BURTC_IntEnable(irqien_hal2burtc(local_flag)); -} - -/****************************************************************************** - * Disables BURTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - BURTC_IntDisable(irqien_hal2burtc(local_flag)); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - BURTC_IntSet(irqien_hal2burtc(local_flag)); -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = BURTC_IntGet(); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = (irq_flag & BURTC_IF_COMP); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = (irq_flag & BURTC_IF_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * Gets BURTC timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - return (CMU_ClockFreqGet(cmuClock_BURTC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); -} - -/******************************************************************************* - * BURTC interrupt handler. - ******************************************************************************/ -void BURTC_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = BURTC_IntGet(); - local_flag = irqflags_burtc2hal(irq_flag); - - BURTC_IntClear(irq_flag & (BURTC_IF_OF | BURTC_IF_COMP)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -static uint32_t get_time_diff(uint32_t a, uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ - return CMU_LF_ClockPrecisionGet(cmuClock_BURTC); -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for BURTC peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for BURTC peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ - switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: - case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -} -#endif -#endif - -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER Hardware abstraction implementation for BURTC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) + +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_burtc.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_BURTC + +#if defined(_SILICON_LABS_32B_SERIES_0) +#error BURTC implementation of the sleeptimer not available on Series 0 chips +#endif + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define SLEEPTIMER_COMPARE_MIN_DIFF (5 + 1) +#else +#define SLEEPTIMER_COMPARE_MIN_DIFF (4 + 1) +#endif + +#define SLEEPTIMER_TMR_WIDTH (_BURTC_CNT_MASK) + +static uint32_t get_time_diff(uint32_t a, uint32_t b); + +/****************************************************************************** + * Convert HAL interrupt flag BURTC-interrupt-enable bitmask + *****************************************************************************/ +static uint32_t irqien_hal2burtc(uint8_t hal_flag) +{ + uint32_t burtc_if = 0u; + + if (hal_flag & SLEEPTIMER_EVENT_OF) { + burtc_if |= BURTC_IEN_OF; + } + + if (hal_flag & SLEEPTIMER_EVENT_COMP) { + burtc_if |= BURTC_IEN_COMP; + } + + return burtc_if; +} + +/****************************************************************************** + * Convert BURTC interrupt flags to HAL events + *****************************************************************************/ +static uint8_t irqflags_burtc2hal(uint32_t burtc_flag) +{ + uint8_t hal_if = 0u; + + if (burtc_flag & BURTC_IF_OF) { + hal_if |= SLEEPTIMER_EVENT_OF; + } + + if (burtc_flag & BURTC_IF_COMP) { + hal_if |= SLEEPTIMER_EVENT_COMP; + } + + return hal_if; +} + +/****************************************************************************** + * Initializes BURTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer() +{ + BURTC_Init_TypeDef burtc_init = BURTC_INIT_DEFAULT; + + CMU_ClockEnable(cmuClock_BURTC, true); + + burtc_init.start = false; + burtc_init.clkDiv = SL_SLEEPTIMER_FREQ_DIVIDER; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + burtc_init.debugRun = true; +#endif + + BURTC_Init(&burtc_init); + BURTC_IntDisable(_BURTC_IEN_MASK); + BURTC_IntClear(_BURTC_IF_MASK); + BURTC_CounterReset(); + + BURTC_Start(); + BURTC_SyncWait(); + + // Setup BURTC interrupt + NVIC_ClearPendingIRQ(BURTC_IRQn); + NVIC_EnableIRQ(BURTC_IRQn); +} + +/****************************************************************************** + * Gets BURTC counter. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return BURTC_CounterGet(); +} + +/****************************************************************************** + * Gets BURTC compare value + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return BURTC_CompareGet(0U); +} + +/****************************************************************************** + * Sets BURTC compare value + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the BURTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare_current; + uint32_t compare_new = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare_current = sleeptimer_hal_get_compare(); + + if (((BURTC_IntGet() & _BURTC_IF_COMP_MASK) != 0) + || get_time_diff(compare_current, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare_current == counter) { + // Add margin if necessary + if (get_time_diff(compare_new, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_new = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + + // wrap around if necessary + compare_new %= SLEEPTIMER_TMR_WIDTH; + + BURTC_CompareSet(0U, compare_new - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + BURTC_IntEnable(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Disables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + BURTC_IntDisable(irqien_hal2burtc(local_flag)); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + BURTC_IntSet(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = BURTC_IntGet(); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = (irq_flag & BURTC_IF_COMP); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = (irq_flag & BURTC_IF_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * Gets BURTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + return (CMU_ClockFreqGet(cmuClock_BURTC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); +} + +/******************************************************************************* + * BURTC interrupt handler. + ******************************************************************************/ +void BURTC_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = BURTC_IntGet(); + local_flag = irqflags_burtc2hal(irq_flag); + + BURTC_IntClear(irq_flag & (BURTC_IF_OF | BURTC_IF_COMP)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +static uint32_t get_time_diff(uint32_t a, uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + return CMU_LF_ClockPrecisionGet(cmuClock_BURTC); +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +} +#endif +#endif + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c index 769f88f..4b97cfa 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c @@ -1,424 +1,424 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction implementation for SYSRTC. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#include "peripheral_sysrtc.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) || defined(SL_CATALOG_HFXO_MANAGER_PRESENT) -#if defined(_SILICON_LABS_32B_SERIES_2) -#include "em_prs.h" -#else -#include "sl_peripheral_prs.h" -#endif -#endif - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) - -#define SLEEPTIMER_TMR_WIDTH (_SYSRTC_CNT_MASK) - -static bool cc_disabled = true; - -static bool cc1_disabled = true; - -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b); - -/****************************************************************************** - * Initializes SYSRTC sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer(void) -{ - sl_hal_sysrtc_config_t sysrtc_config = SYSRTC_CONFIG_DEFAULT; - sl_hal_sysrtc_group_config_t group_config = SYSRTC_GROUP_CONFIG_DEFAULT; - - CMU_ClockEnable(cmuClock_SYSRTC, true); - -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - sysrtc_config.enable_debug_run = true; -#endif - - sl_hal_sysrtc_init(&sysrtc_config); - - group_config.compare_channel0_enable = false; - - sl_hal_sysrtc_init_group(0u, &group_config); - - sl_hal_sysrtc_disable_group_interrupts(0u, _SYSRTC_GRP0_IEN_MASK); - sl_hal_sysrtc_clear_group_interrupts(0u, _SYSRTC_GRP0_IF_MASK); - sl_hal_sysrtc_enable(); - sl_hal_sysrtc_set_counter(0u); - - NVIC_ClearPendingIRQ(SYSRTC_APP_IRQn); - NVIC_EnableIRQ(SYSRTC_APP_IRQn); -} - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to Power Manager. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_hal_power_manager_integration_init(void) -{ - // Initialize PRS to start HFXO for early wakeup - CMU_ClockEnable(cmuClock_PRS, true); - -#if defined(_SILICON_LABS_32B_SERIES_2) - PRS_ConnectSignal(1UL, prsTypeAsync, prsSignalSYSRTC0_GRP0OUT1); - PRS_ConnectConsumer(1UL, prsTypeAsync, prsConsumerHFXO0_OSCREQ); -#else - sl_hal_prs_async_connect_channel_producer(1UL, SL_HAL_PRS_ASYNC_SYSRTC0_GRP0OUT1); - sl_hal_prs_connect_channel_consumer(1UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_HFXO0_OSCREQ); -#endif - - // Set SYSRTC Compare Channel 1 - SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); -} -#endif - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to HFXO Manager. - ******************************************************************************/ -#if defined(SL_CATALOG_HFXO_MANAGER_PRESENT) -void sli_sleeptimer_hal_hfxo_manager_integration_init(void) -{ - // Set PRS signal from HFXO to SYSRTC capture channel - CMU_ClockEnable(cmuClock_PRS, true); - -#if defined(_SILICON_LABS_32B_SERIES_2) - PRS_ConnectSignal(2UL, prsTypeAsync, prsSignalHFXO0L_STATUS1); - PRS_ConnectConsumer(2UL, prsTypeAsync, prsConsumerSYSRTC0_SRC0); -#else - sl_hal_prs_async_connect_channel_producer(2UL, SL_HAL_PRS_ASYNC_SYXO0L_STATUS1); - sl_hal_prs_connect_channel_consumer(2UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_SYSRTC0_IN0); -#endif - - // Set SYSRTC Capture Channel - SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); -} -#endif - -/****************************************************************************** - * Gets SYSRTC counter value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return sl_hal_sysrtc_get_counter(); -} - -/****************************************************************************** - * Gets SYSRTC channel zero's compare value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return sl_hal_sysrtc_get_group_compare_channel_value(0u, 0u); -} - -/****************************************************************************** - * Sets SYSRTC channel zero's compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the SYSRTC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare; - uint32_t compare_value = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare = sleeptimer_hal_get_compare(); - - if (((sl_hal_sysrtc_get_group_interrupts(0u) & SYSRTC_GRP0_IEN_CMP0) != 0) - || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare == counter) { - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - compare_value %= SLEEPTIMER_TMR_WIDTH; - - sl_hal_sysrtc_set_group_compare_channel_value(0u, 0u, compare_value - 1); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_CRITICAL(); - - if (cc_disabled) { - SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP0EN; - cc_disabled = false; - } -} - -/******************************************************************************* - * Sets SYSRTC channel one's compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the SYSRTC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - ******************************************************************************/ -void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare_value; - - CORE_ENTER_CRITICAL(); - - counter = sleeptimer_hal_get_counter(); - - compare_value = value + counter; - - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - - compare_value %= SLEEPTIMER_TMR_WIDTH; - - sl_hal_sysrtc_set_group_compare_channel_value(0u, 1u, compare_value - 1); - - CORE_EXIT_CRITICAL(); - - if (cc1_disabled) { - SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP1EN; - SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CAP0EN; - cc1_disabled = false; - } -} - -/****************************************************************************** - * Enables SYSRTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - uint32_t sysrtc_ien = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - sysrtc_ien |= SYSRTC_GRP0_IEN_OVF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - sysrtc_ien |= SYSRTC_GRP0_IEN_CMP0; - } - - sl_hal_sysrtc_enable_group_interrupts(0u, sysrtc_ien); -} - -/****************************************************************************** - * Disables SYSRTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - uint32_t sysrtc_int_dis = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - sysrtc_int_dis |= SYSRTC_GRP0_IEN_OVF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - sysrtc_int_dis |= SYSRTC_GRP0_IEN_CMP0; - - cc_disabled = true; - SYSRTC0->GRP0_CTRL &= ~_SYSRTC_GRP0_CTRL_CMP0EN_MASK; - } - - sl_hal_sysrtc_disable_group_interrupts(0u, sysrtc_int_dis); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - if (local_flag & SLEEPTIMER_EVENT_COMP) { - SYSRTC0->GRP0_IF_SET = SYSRTC_GRP0_IF_CMP0; - } -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = ((irq_flag & SYSRTC_GRP0_IF_CMP0) == SYSRTC_GRP0_IF_CMP0); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = ((irq_flag & SYSRTC_GRP0_IF_OVF) == SYSRTC_GRP0_IF_OVF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * SYSRTC interrupt handler. - ******************************************************************************/ -void SYSRTC_APP_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); - - if (irq_flag & SYSRTC_GRP0_IF_OVF) { - local_flag |= SLEEPTIMER_EVENT_OF; - } - - if (irq_flag & SYSRTC_GRP0_IF_CMP0) { - local_flag |= SLEEPTIMER_EVENT_COMP; - } - sl_hal_sysrtc_clear_group_interrupts(0u, irq_flag & (SYSRTC_GRP0_IF_OVF | SYSRTC_GRP0_IF_CMP0)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Gets SYSRTC timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - return (CMU_ClockFreqGet(cmuClock_SYSRTC)); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ - return CMU_LF_ClockPrecisionGet(cmuClock_SYSRTC); -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - if ((sl_hal_sysrtc_get_group_interrupts(0) & _SYSRTC_GRP0_IF_CAP0_MASK) != 0) { - sl_hal_sysrtc_clear_group_interrupts(0, _SYSRTC_GRP0_IF_CAP0_MASK); - return sl_hal_sysrtc_get_group_capture_channel_value(0); - } else { - return 0; - } -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - sl_hal_sysrtc_clear_group_interrupts(0, SYSRTC_GRP0_IF_CMP1); -} - -/******************************************************************************* - * Hardware Abstraction Layer to disable PRS compare and capture channel. - ******************************************************************************/ -void sleeptimer_hal_disable_prs_compare_and_capture_channel(void) -{ - if (!cc1_disabled) { - SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CMP1EN; - SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CAP0EN; - cc1_disabled = true; - } -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ - switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for SYSRTC. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#include "peripheral_sysrtc.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) || defined(SL_CATALOG_HFXO_MANAGER_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_prs.h" +#else +#include "sl_peripheral_prs.h" +#endif +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) + +#define SLEEPTIMER_TMR_WIDTH (_SYSRTC_CNT_MASK) + +static bool cc_disabled = true; + +static bool cc1_disabled = true; + +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes SYSRTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + sl_hal_sysrtc_config_t sysrtc_config = SYSRTC_CONFIG_DEFAULT; + sl_hal_sysrtc_group_config_t group_config = SYSRTC_GROUP_CONFIG_DEFAULT; + + CMU_ClockEnable(cmuClock_SYSRTC, true); + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + sysrtc_config.enable_debug_run = true; +#endif + + sl_hal_sysrtc_init(&sysrtc_config); + + group_config.compare_channel0_enable = false; + + sl_hal_sysrtc_init_group(0u, &group_config); + + sl_hal_sysrtc_disable_group_interrupts(0u, _SYSRTC_GRP0_IEN_MASK); + sl_hal_sysrtc_clear_group_interrupts(0u, _SYSRTC_GRP0_IF_MASK); + sl_hal_sysrtc_enable(); + sl_hal_sysrtc_set_counter(0u); + + NVIC_ClearPendingIRQ(SYSRTC_APP_IRQn); + NVIC_EnableIRQ(SYSRTC_APP_IRQn); +} + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to Power Manager. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_hal_power_manager_integration_init(void) +{ + // Initialize PRS to start HFXO for early wakeup + CMU_ClockEnable(cmuClock_PRS, true); + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS_ConnectSignal(1UL, prsTypeAsync, prsSignalSYSRTC0_GRP0OUT1); + PRS_ConnectConsumer(1UL, prsTypeAsync, prsConsumerHFXO0_OSCREQ); +#else + sl_hal_prs_async_connect_channel_producer(1UL, SL_HAL_PRS_ASYNC_SYSRTC0_GRP0OUT1); + sl_hal_prs_connect_channel_consumer(1UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_HFXO0_OSCREQ); +#endif + + // Set SYSRTC Compare Channel 1 + SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT); +} +#endif + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to HFXO Manager. + ******************************************************************************/ +#if defined(SL_CATALOG_HFXO_MANAGER_PRESENT) +void sli_sleeptimer_hal_hfxo_manager_integration_init(void) +{ + // Set PRS signal from HFXO to SYSRTC capture channel + CMU_ClockEnable(cmuClock_PRS, true); + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS_ConnectSignal(2UL, prsTypeAsync, prsSignalHFXO0L_STATUS1); + PRS_ConnectConsumer(2UL, prsTypeAsync, prsConsumerSYSRTC0_SRC0); +#else + sl_hal_prs_async_connect_channel_producer(2UL, SL_HAL_PRS_ASYNC_SYXO0L_STATUS1); + sl_hal_prs_connect_channel_consumer(2UL, SL_HAL_PRS_TYPE_ASYNC, SL_HAL_PRS_CONSUMER_SYSRTC0_IN0); +#endif + + // Set SYSRTC Capture Channel + SYSRTC0->GRP0_CTRL |= (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT); +} +#endif + +/****************************************************************************** + * Gets SYSRTC counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return sl_hal_sysrtc_get_counter(); +} + +/****************************************************************************** + * Gets SYSRTC channel zero's compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return sl_hal_sysrtc_get_group_compare_channel_value(0u, 0u); +} + +/****************************************************************************** + * Sets SYSRTC channel zero's compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the SYSRTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((sl_hal_sysrtc_get_group_interrupts(0u) & SYSRTC_GRP0_IEN_CMP0) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + sl_hal_sysrtc_set_group_compare_channel_value(0u, 0u, compare_value - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); + + if (cc_disabled) { + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP0EN; + cc_disabled = false; + } +} + +/******************************************************************************* + * Sets SYSRTC channel one's compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the SYSRTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + ******************************************************************************/ +void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare_value; + + CORE_ENTER_CRITICAL(); + + counter = sleeptimer_hal_get_counter(); + + compare_value = value + counter; + + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + + compare_value %= SLEEPTIMER_TMR_WIDTH; + + sl_hal_sysrtc_set_group_compare_channel_value(0u, 1u, compare_value - 1); + + CORE_EXIT_CRITICAL(); + + if (cc1_disabled) { + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CMP1EN; + SYSRTC0->GRP0_CTRL |= SYSRTC_GRP0_CTRL_CAP0EN; + cc1_disabled = false; + } +} + +/****************************************************************************** + * Enables SYSRTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t sysrtc_ien = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + sysrtc_ien |= SYSRTC_GRP0_IEN_OVF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sysrtc_ien |= SYSRTC_GRP0_IEN_CMP0; + } + + sl_hal_sysrtc_enable_group_interrupts(0u, sysrtc_ien); +} + +/****************************************************************************** + * Disables SYSRTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t sysrtc_int_dis = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + sysrtc_int_dis |= SYSRTC_GRP0_IEN_OVF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sysrtc_int_dis |= SYSRTC_GRP0_IEN_CMP0; + + cc_disabled = true; + SYSRTC0->GRP0_CTRL &= ~_SYSRTC_GRP0_CTRL_CMP0EN_MASK; + } + + sl_hal_sysrtc_disable_group_interrupts(0u, sysrtc_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + SYSRTC0->GRP0_IF_SET = SYSRTC_GRP0_IF_CMP0; + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & SYSRTC_GRP0_IF_CMP0) == SYSRTC_GRP0_IF_CMP0); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & SYSRTC_GRP0_IF_OVF) == SYSRTC_GRP0_IF_OVF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * SYSRTC interrupt handler. + ******************************************************************************/ +void SYSRTC_APP_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = sl_hal_sysrtc_get_group_interrupts(0u); + + if (irq_flag & SYSRTC_GRP0_IF_OVF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + + if (irq_flag & SYSRTC_GRP0_IF_CMP0) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + sl_hal_sysrtc_clear_group_interrupts(0u, irq_flag & (SYSRTC_GRP0_IF_OVF | SYSRTC_GRP0_IF_CMP0)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets SYSRTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + return (CMU_ClockFreqGet(cmuClock_SYSRTC)); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + return CMU_LF_ClockPrecisionGet(cmuClock_SYSRTC); +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + if ((sl_hal_sysrtc_get_group_interrupts(0) & _SYSRTC_GRP0_IF_CAP0_MASK) != 0) { + sl_hal_sysrtc_clear_group_interrupts(0, _SYSRTC_GRP0_IF_CAP0_MASK); + return sl_hal_sysrtc_get_group_capture_channel_value(0); + } else { + return 0; + } +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + sl_hal_sysrtc_clear_group_interrupts(0, SYSRTC_GRP0_IF_CMP1); +} + +/******************************************************************************* + * Hardware Abstraction Layer to disable PRS compare and capture channel. + ******************************************************************************/ +void sleeptimer_hal_disable_prs_compare_and_capture_channel(void) +{ + if (!cc1_disabled) { + SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CMP1EN; + SYSRTC0->GRP0_CTRL &= ~SYSRTC_GRP0_CTRL_CAP0EN; + cc1_disabled = true; + } +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +} +#endif +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c index 54702bb..75feff4 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c @@ -1,363 +1,363 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction implementation for WTIMER/TIMER. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_timer.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ - || (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#define SLEEPTIMER_COMPARE_MIN_DIFF (1 + 1) - -// Macros used to constructs WTIMER/TIMER instance -#define _CONCAT_TWO_TOKENS(token_1, token_2) token_1 ## token_2 -#define _CONCAT_THREE_TOKENS(token_1, token_2, token_3) token_1 ## token_2 ## token_3 -#define CONCAT_TWO_TOKENS(token_1, token_2) _CONCAT_TWO_TOKENS(token_1, token_2) -#define CONCAT_THREE_TOKENS(token_1, token_2, token_3) _CONCAT_THREE_TOKENS(token_1, token_2, token_3) - -#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) -#if defined(WTIMER_PRESENT) \ - && (SL_SLEEPTIMER_TIMER_INSTANCE < WTIMER_COUNT) \ - && (_WTIMER_CNT_MASK == 0xFFFFFFFFUL) - #define SLEEPTIMER_TIMER_INSTANCE CONCAT_TWO_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_CHANNEL 0 - #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) - #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) - #define SLEEPTIMER_TIMER_IEN_COMPARE WTIMER_IEN_CC0 - #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_TOP_MAX _WTIMER_TOP_MASK - #define SLEEPTIMER_TMR_WIDTH _WTIMER_CNT_MASK -#else - #define TIMER_UNSUPORTED -#endif - -#elif (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ - && (_SILICON_LABS_32B_SERIES > 1) -#if defined(TIMER_PRESENT) \ - && (SL_SLEEPTIMER_TIMER_INSTANCE < TIMER_COUNT) \ - && (TIMER_CNTWIDTH(SL_SLEEPTIMER_TIMER_INSTANCE) == 0x20) - #define SLEEPTIMER_TIMER_INSTANCE TIMER(SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_CHANNEL 0 - #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) - #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) - #define SLEEPTIMER_TIMER_IEN_COMPARE TIMER_IEN_CC0 - #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_TOP_MAX _TIMER_TOP_MASK - #define SLEEPTIMER_TMR_WIDTH _TIMER_CNT_MASK -#else - #define TIMER_UNSUPORTED -#endif - -#else - #define TIMER_UNSUPORTED -#endif - -#if defined(TIMER_UNSUPORTED) -#error "The WTIMER/TIMER peripheral instance or channel is not supported. It must be a valid 32-bits size instance." -#endif -static bool comp_int_disabled = true; - -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b); - -/****************************************************************************** - * Initializes TIMER sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer(void) -{ - TIMER_Init_TypeDef init_config = TIMER_INIT_DEFAULT; - TIMER_InitCC_TypeDef init_config_cc = TIMER_INITCC_DEFAULT; - - CMU_ClockEnable(SLEEPTIMER_TIMER_CLK, true); - - init_config_cc.mode = timerCCModeCompare; - TIMER_InitCC(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); - TIMER_TopSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); - -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - init_config.debugRun = true; -#endif - - // - init_config.prescale = timerPrescale1024; - - TIMER_Init(SLEEPTIMER_TIMER_INSTANCE, &init_config); -#if defined(TIMER_STATUS_SYNCBUSY) - TIMER_SyncWait(SLEEPTIMER_TIMER_INSTANCE); -#endif - - TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); - - TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); - - NVIC_ClearPendingIRQ(SLEEPTIMER_TIMER_IRQ); - NVIC_EnableIRQ(SLEEPTIMER_TIMER_IRQ); -} - -/****************************************************************************** - * Gets TIMER counter value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return TIMER_CounterGet(SLEEPTIMER_TIMER_INSTANCE); -} - -/****************************************************************************** - * Gets TIMER compare value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return TIMER_CaptureGet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL); -} - -/****************************************************************************** - * Sets TIMER compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the TIMER compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare; - uint32_t compare_value = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare = sleeptimer_hal_get_compare(); - - if (((TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE) & SLEEPTIMER_TIMER_IEN_COMPARE) != 0) - || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare == counter) { - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - compare_value %= SLEEPTIMER_TMR_WIDTH; - - TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, compare_value - 1); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - comp_int_disabled = false; - } - CORE_EXIT_CRITICAL(); -} - -/****************************************************************************** - * Enables TIMER interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - uint32_t timer_ien = 0UL; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - timer_ien |= TIMER_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - if (comp_int_disabled == true) { - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); - comp_int_disabled = false; - } - timer_ien |= SLEEPTIMER_TIMER_IEN_COMPARE; - } - - TIMER_IntEnable(SLEEPTIMER_TIMER_INSTANCE, timer_ien); -} - -/****************************************************************************** - * Disables TIMER interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - uint32_t timer_int_dis = 0UL; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - timer_int_dis |= TIMER_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - timer_int_dis |= SLEEPTIMER_TIMER_IEN_COMPARE; - - comp_int_disabled = true; - } - - TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, timer_int_dis); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - if (local_flag & SLEEPTIMER_EVENT_COMP) { - TIMER_IntSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); - } -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = ((irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) == SLEEPTIMER_TIMER_IEN_COMPARE); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = ((irq_flag & TIMER_IEN_OF) == TIMER_IEN_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * TIMER interrupt handler. - ******************************************************************************/ -void SLEEPTIMER_TIMER_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); - - if (irq_flag & TIMER_IEN_OF) { - local_flag |= SLEEPTIMER_EVENT_OF; - } - - if (irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) { - local_flag |= SLEEPTIMER_EVENT_COMP; - } - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, irq_flag & (TIMER_IEN_OF | SLEEPTIMER_TIMER_IEN_COMPARE)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Gets TIMER timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - // Returns source frequency divided by max prescaler value 1024. - return (CMU_ClockFreqGet(SLEEPTIMER_TIMER_CLK) >> 10UL); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ -#if defined(WTIMER_PRESENT) - return CMU_HF_ClockPrecisionGet(cmuClock_HF); -#else - return CMU_HF_ClockPrecisionGet(SLEEPTIMER_TIMER_CLK); -#endif -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - * - * @return Capture value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for TIMER peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for TIMER peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note Lowest possible energy mode for WTIMER and TIMER peripheral is EM1. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for WTIMER/TIMER. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_timer.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ + || (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (1 + 1) + +// Macros used to constructs WTIMER/TIMER instance +#define _CONCAT_TWO_TOKENS(token_1, token_2) token_1 ## token_2 +#define _CONCAT_THREE_TOKENS(token_1, token_2, token_3) token_1 ## token_2 ## token_3 +#define CONCAT_TWO_TOKENS(token_1, token_2) _CONCAT_TWO_TOKENS(token_1, token_2) +#define CONCAT_THREE_TOKENS(token_1, token_2, token_3) _CONCAT_THREE_TOKENS(token_1, token_2, token_3) + +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) +#if defined(WTIMER_PRESENT) \ + && (SL_SLEEPTIMER_TIMER_INSTANCE < WTIMER_COUNT) \ + && (_WTIMER_CNT_MASK == 0xFFFFFFFFUL) + #define SLEEPTIMER_TIMER_INSTANCE CONCAT_TWO_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_CHANNEL 0 + #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) + #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) + #define SLEEPTIMER_TIMER_IEN_COMPARE WTIMER_IEN_CC0 + #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_TOP_MAX _WTIMER_TOP_MASK + #define SLEEPTIMER_TMR_WIDTH _WTIMER_CNT_MASK +#else + #define TIMER_UNSUPORTED +#endif + +#elif (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ + && (_SILICON_LABS_32B_SERIES > 1) +#if defined(TIMER_PRESENT) \ + && (SL_SLEEPTIMER_TIMER_INSTANCE < TIMER_COUNT) \ + && (TIMER_CNTWIDTH(SL_SLEEPTIMER_TIMER_INSTANCE) == 0x20) + #define SLEEPTIMER_TIMER_INSTANCE TIMER(SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_CHANNEL 0 + #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) + #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) + #define SLEEPTIMER_TIMER_IEN_COMPARE TIMER_IEN_CC0 + #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_TOP_MAX _TIMER_TOP_MASK + #define SLEEPTIMER_TMR_WIDTH _TIMER_CNT_MASK +#else + #define TIMER_UNSUPORTED +#endif + +#else + #define TIMER_UNSUPORTED +#endif + +#if defined(TIMER_UNSUPORTED) +#error "The WTIMER/TIMER peripheral instance or channel is not supported. It must be a valid 32-bits size instance." +#endif +static bool comp_int_disabled = true; + +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes TIMER sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + TIMER_Init_TypeDef init_config = TIMER_INIT_DEFAULT; + TIMER_InitCC_TypeDef init_config_cc = TIMER_INITCC_DEFAULT; + + CMU_ClockEnable(SLEEPTIMER_TIMER_CLK, true); + + init_config_cc.mode = timerCCModeCompare; + TIMER_InitCC(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); + TIMER_TopSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + init_config.debugRun = true; +#endif + + // + init_config.prescale = timerPrescale1024; + + TIMER_Init(SLEEPTIMER_TIMER_INSTANCE, &init_config); +#if defined(TIMER_STATUS_SYNCBUSY) + TIMER_SyncWait(SLEEPTIMER_TIMER_INSTANCE); +#endif + + TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + + TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); + + NVIC_ClearPendingIRQ(SLEEPTIMER_TIMER_IRQ); + NVIC_EnableIRQ(SLEEPTIMER_TIMER_IRQ); +} + +/****************************************************************************** + * Gets TIMER counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return TIMER_CounterGet(SLEEPTIMER_TIMER_INSTANCE); +} + +/****************************************************************************** + * Gets TIMER compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return TIMER_CaptureGet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL); +} + +/****************************************************************************** + * Sets TIMER compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the TIMER compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE) & SLEEPTIMER_TIMER_IEN_COMPARE) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, compare_value - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + comp_int_disabled = false; + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t timer_ien = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_ien |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + if (comp_int_disabled == true) { + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + comp_int_disabled = false; + } + timer_ien |= SLEEPTIMER_TIMER_IEN_COMPARE; + } + + TIMER_IntEnable(SLEEPTIMER_TIMER_INSTANCE, timer_ien); +} + +/****************************************************************************** + * Disables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t timer_int_dis = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_int_dis |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + timer_int_dis |= SLEEPTIMER_TIMER_IEN_COMPARE; + + comp_int_disabled = true; + } + + TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, timer_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + TIMER_IntSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) == SLEEPTIMER_TIMER_IEN_COMPARE); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & TIMER_IEN_OF) == TIMER_IEN_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * TIMER interrupt handler. + ******************************************************************************/ +void SLEEPTIMER_TIMER_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); + + if (irq_flag & TIMER_IEN_OF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + + if (irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, irq_flag & (TIMER_IEN_OF | SLEEPTIMER_TIMER_IEN_COMPARE)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets TIMER timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + // Returns source frequency divided by max prescaler value 1024. + return (CMU_ClockFreqGet(SLEEPTIMER_TIMER_CLK) >> 10UL); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ +#if defined(WTIMER_PRESENT) + return CMU_HF_ClockPrecisionGet(cmuClock_HF); +#else + return CMU_HF_ClockPrecisionGet(SLEEPTIMER_TIMER_CLK); +#endif +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @return Capture value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note Lowest possible energy mode for WTIMER and TIMER peripheral is EM1. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +} +#endif +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h index a6f06b0..10c3d87 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h @@ -1,146 +1,146 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction layer definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SLEEPTIMER_HAL_H -#define SL_SLEEPTIMER_HAL_H - -#include -#include -#include -#include "em_device.h" -#include "sli_sleeptimer.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * Hardware Abstraction Layer of the sleep timer init. - ******************************************************************************/ -void sleeptimer_hal_init_timer(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get the current timer count. - * - * @return Value in ticks of the timer counter. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get a timer comparator value. - * - * @return Value in ticks of the timer comparator. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void); - -/******************************************************************************* - * Hardware Abstraction Layer to set a timer comparator value. - * - * @param value Number of ticks to set. - ******************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value); - -/******************************************************************************* - * Hardware Abstraction Layer to set a comparator value to trigger a - * peripheral request signal to initialize. - * - * @param value Number of ticks to set. - ******************************************************************************/ -void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value); - -/******************************************************************************* - * Hardware Abstraction Layer to get the timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void); - -/******************************************************************************* - * Hardware Abstraction Layer to enable timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to disable timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to get the sleeptimer's clock accuracy. - * - * @return Clock accuracy in PPM. - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - * - * @note Not supported by all peripherals Sleeptimer can use. - * - * @return Capture value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void); - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - * - * @note Not supported by all peripherals Sleeptimer can use. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void); - -/******************************************************************************* - * Hardware Abstraction Layer to disable PRS compare and capture channel. - * - * @note Not supported by all peripherals Sleeptimer can use. - ******************************************************************************/ -void sleeptimer_hal_disable_prs_compare_and_capture_channel(void); - -/******************************************************************************* - * Process the timer interrupt. - * - * @param flags Internal interrupt flag. - ******************************************************************************/ -void process_timer_irq(uint8_t local_flag); - -#ifdef __cplusplus -} -#endif - -#endif /* SL_SLEEPTIMER_HAL_H */ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction layer definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_HAL_H +#define SL_SLEEPTIMER_HAL_H + +#include +#include +#include +#include "em_device.h" +#include "sli_sleeptimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer of the sleep timer init. + ******************************************************************************/ +void sleeptimer_hal_init_timer(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the current timer count. + * + * @return Value in ticks of the timer counter. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get a timer comparator value. + * + * @return Value in ticks of the timer comparator. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void); + +/******************************************************************************* + * Hardware Abstraction Layer to set a timer comparator value. + * + * @param value Number of ticks to set. + ******************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to set a comparator value to trigger a + * peripheral request signal to initialize. + * + * @param value Number of ticks to set. + ******************************************************************************/ +void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to get the timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void); + +/******************************************************************************* + * Hardware Abstraction Layer to enable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to disable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to get the sleeptimer's clock accuracy. + * + * @return Clock accuracy in PPM. + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @note Not supported by all peripherals Sleeptimer can use. + * + * @return Capture value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void); + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void); + +/******************************************************************************* + * Hardware Abstraction Layer to disable PRS compare and capture channel. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +void sleeptimer_hal_disable_prs_compare_and_capture_channel(void); + +/******************************************************************************* + * Process the timer interrupt. + * + * @param flags Internal interrupt flag. + ******************************************************************************/ +void process_timer_irq(uint8_t local_flag); + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SLEEPTIMER_HAL_H */ diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h b/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h index 9bdd8ea..597a00c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h @@ -1,153 +1,153 @@ -/***************************************************************************//** - * @file - * @brief System Initialization. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SYSTEM_INIT_H -#define SL_SYSTEM_INIT_H - -/***************************************************************************//** - * @addtogroup system System Initialization and Action Processing - * @brief System Initialization and Action Processing - * @details - * ### System Init - * System Init provides a function for initializing the system and the products: - * - * - sl_system_init(). - * - * This function calls a set of functions that are automatically generated - * and located in `autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - platform_init -> sl_platform_init() - * - driver_init -> sl_driver_init() - * - service_init -> sl_service_init() - * - stack_init -> sl_stack_init() - * - internal_app_init -> sl_internal_app_init() - * - * These events are fired in the order listed above when `sl_system_init()` - * is called. - * - * ### System Kernel - * - * System Kernel component provides a function for starting the kernel: - * - * - sl_system_kernel_start(). - * - * This function calls a functions that is automatically generated - * and located in `$autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - kernel_start -> sl_kernel_start() - * - * The event is fired when `sl_system_kernel_start()` is called. - * - * ### System Process Action - * - * System Process Action component provides a function for running - * the products from a super loop: - * - * - sl_system_process_action(). - * - * This function calls a set of functions that are automatically generated - * and located in `$autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - platform_process_action -> sl_platform_process_action() - * - service_process_action -> sl_service_process_action() - * - stack_process_action -> sl_stack_process_action() - * - internal_app_process_action -> sl_internal_process_action() - * - * These events are fired in the order listed above when `sl_system_process_action()` - * is called. - * - * Usage example: - * - * @code{.c} - * #if defined(SL_COMPONENT_CATALOG_PRESENT) - * #include "sl_component_catalog.h" - * #endif - * #include "sl_system_init.h" - * #include "sl_power_manager.h" - * #include "app.h" - * #if defined(SL_CATALOG_KERNEL_PRESENT) - * #include "sl_system_kernel.h" - * #else - * #include "sl_system_process_action.h" - * #endif - * - * int main(void) - * { - * // Initialize Silicon Labs device, system, service(s) and protocol stack(s). - * // Note that if the kernel is present, processing task(s) will be created by - * // this call. - * sl_system_init(); - * - * // Initialize the application. - * app_init(); - * - * #if defined(SL_CATALOG_KERNEL_PRESENT) - * // Start the kernel. Task(s) created in app_init() will start running. - * sl_system_kernel_start(); - * #else - * do { - * // Do not remove this call: Silicon Labs components process action routine - * // must be called from the super loop. - * sl_system_process_action(); - * - * // Application process. - * app_process_action(); - * - * // Let the CPU go to sleep if the system allow it. - * sl_power_manager_sleep(); - * } while (1); - * #endif // SL_CATALOG_KERNEL_PRESENT - * } - * @endcode - * @{ - * - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize Silicon Labs products - */ -void sl_system_init(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup system) */ - -#endif // SL_SYSTEM_INIT_H +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_INIT_H +#define SL_SYSTEM_INIT_H + +/***************************************************************************//** + * @addtogroup system System Initialization and Action Processing + * @brief System Initialization and Action Processing + * @details + * ### System Init + * System Init provides a function for initializing the system and the products: + * + * - sl_system_init(). + * + * This function calls a set of functions that are automatically generated + * and located in `autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_init -> sl_platform_init() + * - driver_init -> sl_driver_init() + * - service_init -> sl_service_init() + * - stack_init -> sl_stack_init() + * - internal_app_init -> sl_internal_app_init() + * + * These events are fired in the order listed above when `sl_system_init()` + * is called. + * + * ### System Kernel + * + * System Kernel component provides a function for starting the kernel: + * + * - sl_system_kernel_start(). + * + * This function calls a functions that is automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - kernel_start -> sl_kernel_start() + * + * The event is fired when `sl_system_kernel_start()` is called. + * + * ### System Process Action + * + * System Process Action component provides a function for running + * the products from a super loop: + * + * - sl_system_process_action(). + * + * This function calls a set of functions that are automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_process_action -> sl_platform_process_action() + * - service_process_action -> sl_service_process_action() + * - stack_process_action -> sl_stack_process_action() + * - internal_app_process_action -> sl_internal_process_action() + * + * These events are fired in the order listed above when `sl_system_process_action()` + * is called. + * + * Usage example: + * + * @code{.c} + * #if defined(SL_COMPONENT_CATALOG_PRESENT) + * #include "sl_component_catalog.h" + * #endif + * #include "sl_system_init.h" + * #include "sl_power_manager.h" + * #include "app.h" + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * #include "sl_system_kernel.h" + * #else + * #include "sl_system_process_action.h" + * #endif + * + * int main(void) + * { + * // Initialize Silicon Labs device, system, service(s) and protocol stack(s). + * // Note that if the kernel is present, processing task(s) will be created by + * // this call. + * sl_system_init(); + * + * // Initialize the application. + * app_init(); + * + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * // Start the kernel. Task(s) created in app_init() will start running. + * sl_system_kernel_start(); + * #else + * do { + * // Do not remove this call: Silicon Labs components process action routine + * // must be called from the super loop. + * sl_system_process_action(); + * + * // Application process. + * app_process_action(); + * + * // Let the CPU go to sleep if the system allow it. + * sl_power_manager_sleep(); + * } while (1); + * #endif // SL_CATALOG_KERNEL_PRESENT + * } + * @endcode + * @{ + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize Silicon Labs products + */ +void sl_system_init(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_INIT_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h b/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h index a6dceba..c37dffa 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h @@ -1,53 +1,53 @@ -/***************************************************************************//** - * @file - * @brief System process action. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SYSTEM_PROCESS_ACTION_H -#define SL_SYSTEM_PROCESS_ACTION_H - -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * System processing action - */ -void sl_system_process_action(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup system) */ - -#endif // SL_SYSTEM_PROCESS_ACTION_H +/***************************************************************************//** + * @file + * @brief System process action. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_PROCESS_ACTION_H +#define SL_SYSTEM_PROCESS_ACTION_H + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * System processing action + */ +void sl_system_process_action(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_PROCESS_ACTION_H diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c b/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c index 9e4988f..595baf7 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c @@ -1,39 +1,39 @@ -/***************************************************************************//** - * @file - * @brief System Initialization. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_event_handler.h" - -void sl_system_init(void) -{ - sl_platform_init(); - sl_driver_init(); - sl_service_init(); - sl_stack_init(); - sl_internal_app_init(); -} +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_init(void) +{ + sl_platform_init(); + sl_driver_init(); + sl_service_init(); + sl_stack_init(); + sl_internal_app_init(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c b/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c index 83be324..a4be21c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c @@ -1,38 +1,38 @@ -/***************************************************************************//** - * @file - * @brief System process action. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_event_handler.h" - -void sl_system_process_action(void) -{ - sl_platform_process_action(); - sl_service_process_action(); - sl_stack_process_action(); - sl_internal_app_process_action(); -} +/***************************************************************************//** + * @file + * @brief System process action. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_process_action(void) +{ + sl_platform_process_action(); + sl_service_process_action(); + sl_stack_process_action(); + sl_internal_app_process_action(); +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h index e26a356..67dfa4c 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h +++ b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef UDELAY_H -#define UDELAY_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup udelay Microsecond Delay - * @brief Microsecond delay function - * @{ - ******************************************************************************/ - -/** - * @brief - * Delay a number of microseconds - * - * @details - * This function will use a busy loop to delay code execution by a certain - * number of microseconds before returning to the caller. This function will - * not return to the caller earlier than the time given as the input parameter. - * This function will not use any hardware timing peripherals, it is using - * the core clock frequency to calculate the delay. - * - * Note that there will always be some overhead associated with calling this - * function in addition to the internal delay loop. This overhead is relatively - * small when the delay is large (>= 100us). - * - * The accuracy of this delay loop will be affected by interrupts and context - * switching. If accuracy is needed, a hardware timer should be used - * to handle delays. - * - * @param[in] us - * This is the number of microseconds to delay execution. This function will - * return after this amount of time has elapsed. Minimum value is 0 us and - * maximum value is 100 000 us (100 ms). It is however recommended to use - * the sleeptimer api for delays of more than 1 ms as it is using a hardware - * counter and will result in better accuracy. - */ -void sl_udelay_wait(unsigned us); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup udelay) */ - -#endif +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef UDELAY_H +#define UDELAY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup udelay Microsecond Delay + * @brief Microsecond delay function + * @{ + ******************************************************************************/ + +/** + * @brief + * Delay a number of microseconds + * + * @details + * This function will use a busy loop to delay code execution by a certain + * number of microseconds before returning to the caller. This function will + * not return to the caller earlier than the time given as the input parameter. + * This function will not use any hardware timing peripherals, it is using + * the core clock frequency to calculate the delay. + * + * Note that there will always be some overhead associated with calling this + * function in addition to the internal delay loop. This overhead is relatively + * small when the delay is large (>= 100us). + * + * The accuracy of this delay loop will be affected by interrupts and context + * switching. If accuracy is needed, a hardware timer should be used + * to handle delays. + * + * @param[in] us + * This is the number of microseconds to delay execution. This function will + * return after this amount of time has elapsed. Minimum value is 0 us and + * maximum value is 100 000 us (100 ms). It is however recommended to use + * the sleeptimer api for delays of more than 1 ms as it is using a hardware + * counter and will result in better accuracy. + */ +void sl_udelay_wait(unsigned us); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup udelay) */ + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c index aa2931e..51860ea 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c +++ b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_udelay.h" -#include "em_device.h" -#include "sl_assert.h" -#include - -/* The Cortex-M33 has a faster execution of the hw loop - * with the same arm instructions. */ -#if defined(__CORTEX_M) && (__CORTEX_M == 33U) - #define HW_LOOP_CYCLE 3 -#else - #define HW_LOOP_CYCLE 4 -#endif - -void sli_delay_loop(unsigned n); - -void sl_udelay_wait(unsigned us) -{ - uint32_t freq_khz; - uint32_t ns_period; - uint32_t cycles; - uint32_t loops; - - freq_khz = SystemCoreClockGet() / 1000U; - if (freq_khz == 0) { - EFM_ASSERT(false); - return; - } - - ns_period = 1000000U / freq_khz; - if (ns_period == 0) { - EFM_ASSERT(false); - return; - } - - cycles = us * 1000U / ns_period; - loops = cycles / HW_LOOP_CYCLE; - if (loops > 0U) { - sli_delay_loop(loops); - } -} +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_udelay.h" +#include "em_device.h" +#include "sl_assert.h" +#include + +/* The Cortex-M33 has a faster execution of the hw loop + * with the same arm instructions. */ +#if defined(__CORTEX_M) && (__CORTEX_M == 33U) + #define HW_LOOP_CYCLE 3 +#else + #define HW_LOOP_CYCLE 4 +#endif + +void sli_delay_loop(unsigned n); + +void sl_udelay_wait(unsigned us) +{ + uint32_t freq_khz; + uint32_t ns_period; + uint32_t cycles; + uint32_t loops; + + freq_khz = SystemCoreClockGet() / 1000U; + if (freq_khz == 0) { + EFM_ASSERT(false); + return; + } + + ns_period = 1000000U / freq_khz; + if (ns_period == 0) { + EFM_ASSERT(false); + return; + } + + cycles = us * 1000U / ns_period; + loops = cycles / HW_LOOP_CYCLE; + if (loops > 0U) { + sli_delay_loop(loops); + } +} diff --git a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S index bb16feb..2fcc720 100644 --- a/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S +++ b/locator_host/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S @@ -1,60 +1,60 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - .text - .align 4 - .syntax unified - .thumb_func - .global sli_delay_loop - -/* - * @brief - * Hardware delay loop - * - * @detail - * This is the hardware specific delay loop. It is designed specifically to - * execute in 4 or 3 cycles for each iteration depending on the architecture. - * Using this information the caller can use the core clock frequency to - * calculate the number of loops required in order to delay a specific time - * period. - * - * @param[in] n (r0) - * n is the number of loops to execute. Each loop will execute in 4 cycles. - * Note that we assume that r0 > 0, so this invariant should be checked by - * the caller. - */ -sli_delay_loop: - subs r0, r0, #1 - beq done - b.n sli_delay_loop -done: - bx lr - - .end +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func + .global sli_delay_loop + +/* + * @brief + * Hardware delay loop + * + * @detail + * This is the hardware specific delay loop. It is designed specifically to + * execute in 4 or 3 cycles for each iteration depending on the architecture. + * Using this information the caller can use the core clock frequency to + * calculate the number of loops required in order to delay a specific time + * period. + * + * @param[in] n (r0) + * n is the number of loops to execute. Each loop will execute in 4 cycles. + * Note that we assume that r0 > 0, so this invariant should be checked by + * the caller. + */ +sli_delay_loop: + subs r0, r0, #1 + beq done + b.n sli_delay_loop +done: + bx lr + + .end diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h index df5e418..e6643ea 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h @@ -1,310 +1,310 @@ -/***************************************************************************//** - * @brief Silicon Labs BGAPI types and macros - ******************************************************************************* - * # License - * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BGAPI_H -#define SL_BGAPI_H - -#include -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Macros to declare deprecated functions */ -#if defined(__IAR_SYSTEMS_ICC__) - #define SL_BGAPI_DEPRECATED _Pragma("deprecated") -#elif defined(__GNUC__) - #define SL_BGAPI_DEPRECATED __attribute__((deprecated)) -#else - #define SL_BGAPI_DEPRECATED -#endif - -/* Compatibility */ -#ifndef PACKSTRUCT -/*Default packed configuration*/ -#ifdef __GNUC__ -#ifdef _WIN32 -#define PACKSTRUCT(decl) decl __attribute__((__packed__, gcc_struct)) -#else -#define PACKSTRUCT(decl) decl __attribute__((__packed__)) -#endif -#define ALIGNED __attribute__((aligned(0x4))) -#elif __IAR_SYSTEMS_ICC__ - -#define PACKSTRUCT(decl) __packed decl - -#define ALIGNED -#elif _MSC_VER /*msvc*/ - -#define PACKSTRUCT(decl) __pragma(pack(push, 1) ) decl __pragma(pack(pop) ) -#define ALIGNED -#else -#define PACKSTRUCT(a) a PACKED -#endif -#endif - -/** - * The maximum BGAPI command payload size. - */ -#ifndef SL_BGAPI_MAX_PAYLOAD_SIZE -#define SL_BGAPI_MAX_PAYLOAD_SIZE 256 -#endif - -/***************************************************************************//** - * @addtogroup sl_bgapi_types BGAPI Types - * @brief Common types in BGAPI protocol - * @{ - */ - -#ifndef SL_BT_TYPE_UINT8ARRARY -#define SL_BT_TYPE_UINT8ARRARY -/** @brief Variable-length uint8_t array. Maximum length: 255 */ -typedef struct { - uint8_t len; /**< Number of bytes stored in @p data */ - uint8_t data[]; /**< Data bytes*/ -} uint8array; -#endif - -#ifndef SL_BT_TYPE_BYTE_ARRARY -#define SL_BT_TYPE_BYTE_ARRARY -/** @brief Variable-length int8_t array. Maximum length: 65535 */ -typedef struct { - uint16_t len; /**< Number of bytes stored in @p data */ - int8_t data[]; /**< Data bytes*/ -} byte_array; -#endif - -#ifndef SL_BT_TYPE_BDADDR -#define SL_BT_TYPE_BDADDR -/** @brief Bluetooth address */ -typedef struct { - uint8_t addr[6]; /**< @brief Bluetooth address in reverse byte order */ -} bd_addr; -#endif - -#ifndef SL_BT_TYPE_UUID128 -#define SL_BT_TYPE_UUID128 -/** @brief 128-bit UUID */ -typedef struct { - uint8_t data[16]; /**< 128-bit UUID */ -} uuid_128; -#endif - -#ifndef SL_BT_TYPE_AES_KEY128 -#define SL_BT_TYPE_AES_KEY128 -/** @brief 128-bit AES key */ -typedef struct { - uint8_t data[16]; /**< 128-bit AES key */ -} aes_key_128; -#endif - -#ifndef SL_BT_TYPE_UUID16 -#define SL_BT_TYPE_UUID16 -/** @brief 16-bit UUID */ -typedef struct { - uint8_t data[2]; /**< 16-bit UUID */ -} sl_bt_uuid_16_t; -#endif - -#ifndef SL_BT_TYPE_UUID64 -#define SL_BT_TYPE_UUID64 -/** @brief 64-bit UUID */ -typedef struct { - uint8_t data[8]; /**< 64-bit UUID */ -} sl_bt_uuid_64_t; -#endif - -/** @} */ // end addtogroup sl_bgapi_types -/******************************************************************************/ - -/** @brief Internal function prototype for BGAPI command handlers */ -typedef void (*sl_bgapi_handler)(const void*); - -typedef enum sl_bgapi_msg_types { - sl_bgapi_msg_type_cmd = 0x00, - sl_bgapi_msg_type_rsp = 0x00, - sl_bgapi_msg_type_evt = 0x80 -} sl_bgapi_msg_types_t; - -enum sl_bgapi_dev_types { - sl_bgapi_dev_type_app = 0x00, - sl_bgapi_dev_type_bt = 0x20, - sl_bgapi_dev_type_btmesh = 0x28, - sl_bgapi_dev_type_bgapi_debug = 0x30, -}; - -/***************************************************************************//** - * @addtogroup sl_bgapi_types BGAPI Types - * @brief Common types in BGAPI protocol - * @{ - */ - -/** - * @brief The length of a BGAPI message header which is 4 bytes - */ -#define SL_BGAPI_MSG_HEADER_LEN (4) - -/** - * @brief Get the device type of a BGAPI message - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_DEVICE_TYPE(HDR) ((HDR) & 0x38) - -/** - * @brief Get the identifier of a BGAPI message including device type, class ID, - * message type and message ID. - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_ID(HDR) ((HDR) & 0xffff00f8) - -/** - * @brief Get the data payload length in a BGAPI message. - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_LEN(HDR) ((((HDR) & 0x7) << 8) | (((HDR) & 0xff00) >> 8)) - -/** - * @brief The bit indicating whether data of a BGAPI message is encrypted - */ -#define SL_BGAPI_BIT_ENCRYPTED (1 << 6) // Bit - -/** - * @brief Check whether data of a BGAPI message is encrypted. - * - * @param HDR The BGAPI header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_ENCRYPTED(HDR) ((HDR)&SL_BGAPI_BIT_ENCRYPTED) - -/** @} */ // end addtogroup sl_bgapi_types -/******************************************************************************/ - -/** - * Internal function for setting the command handler function. Used by API library. - * - * @param cmd_handler_delegate Pointer to command handler delegate function - */ -void sli_bgapi_set_cmd_handler_delegate(void (*cmd_handler_delegate)(uint32_t, - sl_bgapi_handler, - const void*)); - -/** - * @addtogroup sl_bgapi_functions BGAPI Functions - * @{ - * - * @brief Functions provided by the BGAPI protocol - */ - -/** - * @brief Lock the BGAPI for exclusive access. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format in an application that - * uses an RTOS. Normal application code that issues BGAPI commands by calling - * API functions defined by protocol stacks must never call this function - * directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - * - * @return SL_STATUS_OK if the lock has been obtained, otherwise an error code - */ -sl_status_t sl_bgapi_lock(void); - -/** - * @brief Release the lock obtained by @ref sl_bgapi_lock - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format in an application that - * uses an RTOS. Normal application code that issues BGAPI commands by calling - * API functions defined by protocol stacks must never call this function - * directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - */ -void sl_bgapi_unlock(void); - -/** - * @brief Handle a BGAPI command in binary format. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format. Normal application code - * that issues BGAPI commands by calling API functions defined by protocol - * stacks must never call this function directly. - * - * If the application uses an RTOS, the caller must protect the BGAPI handling - * by obtaining the BGAPI lock with @ref sl_bgapi_lock, handle the command with - * @ref sl_bgapi_handle_command, read the response from the buffer returned by - * @ref sl_bgapi_get_command_response, and then release the lock with @ref - * sl_bgapi_unlock. Here's an example of the full sequence that's required: - * - * @code - * // Lock BGAPI for exclusive access - * sl_status_t status = sl_bgapi_lock(); - * if (status != SL_STATUS_OK) { - * // Locking will only fail if there are fatal unrecoverable errors with the - * // RTOS primitives, so caller may choose to just assert in case of errors. - * } - * - * // Process the command - * sl_bgapi_handle_command(hdr, data); - * - * // Read the response - * void *rsp = sl_bgapi_get_command_response(); - * uint32_t rsp_header = *((uint32_t *)rsp); - * size_t rsp_len = SL_BGAPI_MSG_LEN(rsp_header) + SL_BGAPI_MSG_HEADER_LEN; - * // Send the `rsp_len` bytes of response starting from `rsp` - * - * // Finally unlock the BGAPI to allow other commands to proceed - * sl_bgapi_unlock(); - * @endcode - * - * Empty stub implementations are provided for @ref sl_bgapi_lock and @ref - * sl_bgapi_unlock, so the same sequence can be used for all NCP/CPC - * implementations even if an RTOS is not present. - * - * @param[in] hdr The BGAPI command header - * @param[in] data The payload data associated with the command - */ -void sl_bgapi_handle_command(uint32_t hdr, const void* data); - -/** - * @brief Get the response of a handled BGAPI command. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format. Normal application code - * that issues BGAPI commands by calling API functions defined by protocol - * stacks must never call this function directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - * - * @return Pointer to the BGAPI response structure that was filled when the - * command was executed in @ref sl_bgapi_handle_command. - */ -void* sl_bgapi_get_command_response(void); - -/** @} */ // end addtogroup sl_bgapi_functions - -#ifdef __cplusplus -} -#endif - -#endif +/***************************************************************************//** + * @brief Silicon Labs BGAPI types and macros + ******************************************************************************* + * # License + * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BGAPI_H +#define SL_BGAPI_H + +#include +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros to declare deprecated functions */ +#if defined(__IAR_SYSTEMS_ICC__) + #define SL_BGAPI_DEPRECATED _Pragma("deprecated") +#elif defined(__GNUC__) + #define SL_BGAPI_DEPRECATED __attribute__((deprecated)) +#else + #define SL_BGAPI_DEPRECATED +#endif + +/* Compatibility */ +#ifndef PACKSTRUCT +/*Default packed configuration*/ +#ifdef __GNUC__ +#ifdef _WIN32 +#define PACKSTRUCT(decl) decl __attribute__((__packed__, gcc_struct)) +#else +#define PACKSTRUCT(decl) decl __attribute__((__packed__)) +#endif +#define ALIGNED __attribute__((aligned(0x4))) +#elif __IAR_SYSTEMS_ICC__ + +#define PACKSTRUCT(decl) __packed decl + +#define ALIGNED +#elif _MSC_VER /*msvc*/ + +#define PACKSTRUCT(decl) __pragma(pack(push, 1) ) decl __pragma(pack(pop) ) +#define ALIGNED +#else +#define PACKSTRUCT(a) a PACKED +#endif +#endif + +/** + * The maximum BGAPI command payload size. + */ +#ifndef SL_BGAPI_MAX_PAYLOAD_SIZE +#define SL_BGAPI_MAX_PAYLOAD_SIZE 256 +#endif + +/***************************************************************************//** + * @addtogroup sl_bgapi_types BGAPI Types + * @brief Common types in BGAPI protocol + * @{ + */ + +#ifndef SL_BT_TYPE_UINT8ARRARY +#define SL_BT_TYPE_UINT8ARRARY +/** @brief Variable-length uint8_t array. Maximum length: 255 */ +typedef struct { + uint8_t len; /**< Number of bytes stored in @p data */ + uint8_t data[]; /**< Data bytes*/ +} uint8array; +#endif + +#ifndef SL_BT_TYPE_BYTE_ARRARY +#define SL_BT_TYPE_BYTE_ARRARY +/** @brief Variable-length int8_t array. Maximum length: 65535 */ +typedef struct { + uint16_t len; /**< Number of bytes stored in @p data */ + int8_t data[]; /**< Data bytes*/ +} byte_array; +#endif + +#ifndef SL_BT_TYPE_BDADDR +#define SL_BT_TYPE_BDADDR +/** @brief Bluetooth address */ +typedef struct { + uint8_t addr[6]; /**< @brief Bluetooth address in reverse byte order */ +} bd_addr; +#endif + +#ifndef SL_BT_TYPE_UUID128 +#define SL_BT_TYPE_UUID128 +/** @brief 128-bit UUID */ +typedef struct { + uint8_t data[16]; /**< 128-bit UUID */ +} uuid_128; +#endif + +#ifndef SL_BT_TYPE_AES_KEY128 +#define SL_BT_TYPE_AES_KEY128 +/** @brief 128-bit AES key */ +typedef struct { + uint8_t data[16]; /**< 128-bit AES key */ +} aes_key_128; +#endif + +#ifndef SL_BT_TYPE_UUID16 +#define SL_BT_TYPE_UUID16 +/** @brief 16-bit UUID */ +typedef struct { + uint8_t data[2]; /**< 16-bit UUID */ +} sl_bt_uuid_16_t; +#endif + +#ifndef SL_BT_TYPE_UUID64 +#define SL_BT_TYPE_UUID64 +/** @brief 64-bit UUID */ +typedef struct { + uint8_t data[8]; /**< 64-bit UUID */ +} sl_bt_uuid_64_t; +#endif + +/** @} */ // end addtogroup sl_bgapi_types +/******************************************************************************/ + +/** @brief Internal function prototype for BGAPI command handlers */ +typedef void (*sl_bgapi_handler)(const void*); + +typedef enum sl_bgapi_msg_types { + sl_bgapi_msg_type_cmd = 0x00, + sl_bgapi_msg_type_rsp = 0x00, + sl_bgapi_msg_type_evt = 0x80 +} sl_bgapi_msg_types_t; + +enum sl_bgapi_dev_types { + sl_bgapi_dev_type_app = 0x00, + sl_bgapi_dev_type_bt = 0x20, + sl_bgapi_dev_type_btmesh = 0x28, + sl_bgapi_dev_type_bgapi_debug = 0x30, +}; + +/***************************************************************************//** + * @addtogroup sl_bgapi_types BGAPI Types + * @brief Common types in BGAPI protocol + * @{ + */ + +/** + * @brief The length of a BGAPI message header which is 4 bytes + */ +#define SL_BGAPI_MSG_HEADER_LEN (4) + +/** + * @brief Get the device type of a BGAPI message + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_DEVICE_TYPE(HDR) ((HDR) & 0x38) + +/** + * @brief Get the identifier of a BGAPI message including device type, class ID, + * message type and message ID. + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_ID(HDR) ((HDR) & 0xffff00f8) + +/** + * @brief Get the data payload length in a BGAPI message. + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_LEN(HDR) ((((HDR) & 0x7) << 8) | (((HDR) & 0xff00) >> 8)) + +/** + * @brief The bit indicating whether data of a BGAPI message is encrypted + */ +#define SL_BGAPI_BIT_ENCRYPTED (1 << 6) // Bit + +/** + * @brief Check whether data of a BGAPI message is encrypted. + * + * @param HDR The BGAPI header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_ENCRYPTED(HDR) ((HDR)&SL_BGAPI_BIT_ENCRYPTED) + +/** @} */ // end addtogroup sl_bgapi_types +/******************************************************************************/ + +/** + * Internal function for setting the command handler function. Used by API library. + * + * @param cmd_handler_delegate Pointer to command handler delegate function + */ +void sli_bgapi_set_cmd_handler_delegate(void (*cmd_handler_delegate)(uint32_t, + sl_bgapi_handler, + const void*)); + +/** + * @addtogroup sl_bgapi_functions BGAPI Functions + * @{ + * + * @brief Functions provided by the BGAPI protocol + */ + +/** + * @brief Lock the BGAPI for exclusive access. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format in an application that + * uses an RTOS. Normal application code that issues BGAPI commands by calling + * API functions defined by protocol stacks must never call this function + * directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + * + * @return SL_STATUS_OK if the lock has been obtained, otherwise an error code + */ +sl_status_t sl_bgapi_lock(void); + +/** + * @brief Release the lock obtained by @ref sl_bgapi_lock + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format in an application that + * uses an RTOS. Normal application code that issues BGAPI commands by calling + * API functions defined by protocol stacks must never call this function + * directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + */ +void sl_bgapi_unlock(void); + +/** + * @brief Handle a BGAPI command in binary format. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format. Normal application code + * that issues BGAPI commands by calling API functions defined by protocol + * stacks must never call this function directly. + * + * If the application uses an RTOS, the caller must protect the BGAPI handling + * by obtaining the BGAPI lock with @ref sl_bgapi_lock, handle the command with + * @ref sl_bgapi_handle_command, read the response from the buffer returned by + * @ref sl_bgapi_get_command_response, and then release the lock with @ref + * sl_bgapi_unlock. Here's an example of the full sequence that's required: + * + * @code + * // Lock BGAPI for exclusive access + * sl_status_t status = sl_bgapi_lock(); + * if (status != SL_STATUS_OK) { + * // Locking will only fail if there are fatal unrecoverable errors with the + * // RTOS primitives, so caller may choose to just assert in case of errors. + * } + * + * // Process the command + * sl_bgapi_handle_command(hdr, data); + * + * // Read the response + * void *rsp = sl_bgapi_get_command_response(); + * uint32_t rsp_header = *((uint32_t *)rsp); + * size_t rsp_len = SL_BGAPI_MSG_LEN(rsp_header) + SL_BGAPI_MSG_HEADER_LEN; + * // Send the `rsp_len` bytes of response starting from `rsp` + * + * // Finally unlock the BGAPI to allow other commands to proceed + * sl_bgapi_unlock(); + * @endcode + * + * Empty stub implementations are provided for @ref sl_bgapi_lock and @ref + * sl_bgapi_unlock, so the same sequence can be used for all NCP/CPC + * implementations even if an RTOS is not present. + * + * @param[in] hdr The BGAPI command header + * @param[in] data The payload data associated with the command + */ +void sl_bgapi_handle_command(uint32_t hdr, const void* data); + +/** + * @brief Get the response of a handled BGAPI command. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format. Normal application code + * that issues BGAPI commands by calling API functions defined by protocol + * stacks must never call this function directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + * + * @return Pointer to the BGAPI response structure that was filled when the + * command was executed in @ref sl_bgapi_handle_command. + */ +void* sl_bgapi_get_command_response(void); + +/** @} */ // end addtogroup sl_bgapi_functions + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h index 793d765..f970827 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h @@ -1,15633 +1,15633 @@ -/***************************************************************************//** - * @brief SL_BT_API command declarations - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - - -#ifndef SL_BT_API_H -#define SL_BT_API_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include "sl_status.h" -#include "sl_bgapi.h" -#include "sl_bt_api_compatibility.h" - - -/* SL_BT_ synonyms for BGAPI header macros */ -#define SL_BT_MSG_ID(HDR) SL_BGAPI_MSG_ID(HDR) -#define SL_BT_MSG_HEADER_LEN SL_BGAPI_MSG_HEADER_LEN -#define SL_BT_MSG_LEN(HDR) SL_BGAPI_MSG_LEN(HDR) -#define SL_BT_BIT_ENCRYPTED SL_BGAPI_BIT_ENCRYPTED -#define SL_BT_MSG_ENCRYPTED(HDR) SL_BGAPI_MSG_ENCRYPTED(HDR) - -/** - * @addtogroup sl_bt_common_types BT Common Types - * @{ - * - * @brief BT common types - */ - -/** - * @brief Value used to indicate an invalid connection handle - */ -#define SL_BT_INVALID_CONNECTION_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid bonding handle - */ -#define SL_BT_INVALID_BONDING_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid advertising set handle - */ -#define SL_BT_INVALID_ADVERTISING_SET_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid sync handle - */ -#define SL_BT_INVALID_SYNC_HANDLE ((uint16_t) 0xFFFF) - -/** - * @brief Value used to indicate an invalid connection analyzer handle - */ -#define SL_BT_INVALID_CONNECTION_ANALYZER_HANDLE ((uint8_t) 0xFF) - -/** @} */ // end addtogroup sl_bt_common_types - - -/** - * @brief ABR subevent length - */ -typedef struct { - uint8_t data[3]; /**< ABR subevent length */ -} sl_bt_cs_subevent_length_t; - -/** - * @brief DRBG key - */ -typedef struct { - uint8_t data[16]; /**< DRBG key */ -} sl_bt_drbg_key_t; - -/** - * @brief 79 1-bit fields containing the values of the ABR channel index - */ -typedef struct { - uint8_t data[10]; /**< 79 1-bit fields containing the values of the ABR channel index */ -} sl_bt_cs_channel_map_t; - -/** - * @brief 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection - */ -typedef struct { - uint8_t data[5]; /**< 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection */ -} sl_bt_connection_channel_map_t; - - - -/** - * @addtogroup sl_bt_dfu Device Firmware Update - * @{ - * - * @brief Device Firmware Update - * - * These commands and events are related to controlling firmware updates over - * the configured host interface and are available only when the device is - * booted in DFU mode. DFU process: - * 1. Boot device to DFU mode with the Bootloader interface - * 2. Wait for @ref sl_bt_evt_dfu_boot event - * 3. Send command @ref sl_bt_dfu_flash_set_address command to start the - * firmware update - * 4. Upload the firmware with @ref sl_bt_dfu_flash_upload commands until all - * data is uploaded - * 5. Send @ref sl_bt_dfu_flash_upload_finish command when all data is - * uploaded - * 6. Finalize DFU firmware update with @ref sl_bt_system_reset command - * - * DFU mode is using the UART baudrate set in bootloader. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_dfu_flash_set_address_id 0x01000020 -#define sl_bt_cmd_dfu_flash_upload_id 0x02000020 -#define sl_bt_cmd_dfu_flash_upload_finish_id 0x03000020 -#define sl_bt_rsp_dfu_flash_set_address_id 0x01000020 -#define sl_bt_rsp_dfu_flash_upload_id 0x02000020 -#define sl_bt_rsp_dfu_flash_upload_finish_id 0x03000020 - -/** - * @addtogroup sl_bt_evt_dfu_boot sl_bt_evt_dfu_boot - * @{ - * @brief This event indicates that the device booted in DFU mode and is now - * ready to receive commands related to device firmware upgrade (DFU). - */ - -/** @brief Identifier of the boot event */ -#define sl_bt_evt_dfu_boot_id 0x000000a0 - -/***************************************************************************//** - * @brief Data structure of the boot event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_dfu_boot_s -{ - uint32_t version; /**< The version of the bootloader */ -}); - -typedef struct sl_bt_evt_dfu_boot_s sl_bt_evt_dfu_boot_t; - -/** @} */ // end addtogroup sl_bt_evt_dfu_boot - -/** - * @addtogroup sl_bt_evt_dfu_boot_failure sl_bt_evt_dfu_boot_failure - * @{ - * @brief This event indicates that an error, which prevents the device from - * booting, has occurred in bootloader. - */ - -/** @brief Identifier of the boot_failure event */ -#define sl_bt_evt_dfu_boot_failure_id 0x010000a0 - -/***************************************************************************//** - * @brief Data structure of the boot_failure event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_dfu_boot_failure_s -{ - uint16_t reason; /**< The reason for boot failure. */ -}); - -typedef struct sl_bt_evt_dfu_boot_failure_s sl_bt_evt_dfu_boot_failure_t; - -/** @} */ // end addtogroup sl_bt_evt_dfu_boot_failure - -/***************************************************************************//** - * - * After re-booting the local device in DFU mode, this command defines the - * starting address on the flash where the new firmware will be written. - * - * @param[in] address The offset in the flash where the new firmware is uploaded - * to. Always use the value 0x00000000. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_set_address(uint32_t address); - -/***************************************************************************//** - * - * Upload the whole firmware image file into the Bluetooth device. The passed - * data length must be a multiple of 4 bytes. Because the BGAPI command payload - * size is limited, multiple commands need to be issued one after the other - * until the whole firmware image file is uploaded to the device. After each - * command, the next address of the flash sector in memory to write to is - * automatically updated by the bootloader. - * - * @param[in] data_len Length of data in @p data - * @param[in] data An array of data which will be written onto the flash. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data); - -/***************************************************************************//** - * - * Inform the device that the DFU file is fully uploaded. To return the device - * back to normal mode, issue the command @ref sl_bt_system_reset. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_upload_finish(); - -/** @} */ // end addtogroup sl_bt_dfu - -/** - * @addtogroup sl_bt_system System - * @{ - * - * @brief System - * - * Commands and events in this class can be used to access and query the local - * device. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_system_hello_id 0x00010020 -#define sl_bt_cmd_system_start_bluetooth_id 0x1c010020 -#define sl_bt_cmd_system_stop_bluetooth_id 0x1d010020 -#define sl_bt_cmd_system_forcefully_stop_bluetooth_id 0x1e010020 -#define sl_bt_cmd_system_get_version_id 0x1b010020 -#define sl_bt_cmd_system_reset_id 0x01010020 -#define sl_bt_cmd_system_halt_id 0x0c010020 -#define sl_bt_cmd_system_linklayer_configure_id 0x0e010020 -#define sl_bt_cmd_system_set_tx_power_id 0x17010020 -#define sl_bt_cmd_system_get_tx_power_setting_id 0x18010020 -#define sl_bt_cmd_system_set_identity_address_id 0x13010020 -#define sl_bt_cmd_system_get_identity_address_id 0x15010020 -#define sl_bt_cmd_system_get_random_data_id 0x0b010020 -#define sl_bt_cmd_system_data_buffer_write_id 0x12010020 -#define sl_bt_cmd_system_data_buffer_clear_id 0x14010020 -#define sl_bt_cmd_system_get_counters_id 0x0f010020 -#define sl_bt_cmd_system_set_lazy_soft_timer_id 0x1a010020 -#define sl_bt_rsp_system_hello_id 0x00010020 -#define sl_bt_rsp_system_start_bluetooth_id 0x1c010020 -#define sl_bt_rsp_system_stop_bluetooth_id 0x1d010020 -#define sl_bt_rsp_system_forcefully_stop_bluetooth_id 0x1e010020 -#define sl_bt_rsp_system_get_version_id 0x1b010020 -#define sl_bt_rsp_system_reset_id 0x01010020 -#define sl_bt_rsp_system_halt_id 0x0c010020 -#define sl_bt_rsp_system_linklayer_configure_id 0x0e010020 -#define sl_bt_rsp_system_set_tx_power_id 0x17010020 -#define sl_bt_rsp_system_get_tx_power_setting_id 0x18010020 -#define sl_bt_rsp_system_set_identity_address_id 0x13010020 -#define sl_bt_rsp_system_get_identity_address_id 0x15010020 -#define sl_bt_rsp_system_get_random_data_id 0x0b010020 -#define sl_bt_rsp_system_data_buffer_write_id 0x12010020 -#define sl_bt_rsp_system_data_buffer_clear_id 0x14010020 -#define sl_bt_rsp_system_get_counters_id 0x0f010020 -#define sl_bt_rsp_system_set_lazy_soft_timer_id 0x1a010020 - -/** - * @brief Specifies the mode that the system will boot into. - */ -typedef enum -{ - sl_bt_system_boot_mode_normal = 0x0, /**< (0x0) Boot to normal mode */ - sl_bt_system_boot_mode_uart_dfu = 0x1, /**< (0x1) Boot to UART DFU mode */ - sl_bt_system_boot_mode_ota_dfu = 0x2 /**< (0x2) Boot to OTA DFU mode */ -} sl_bt_system_boot_mode_t; - -/** - * @brief These Keys are used to configure Link Layer Operation - */ -typedef enum -{ - sl_bt_system_linklayer_config_key_halt = 0x1, /**< - (0x1) - Same - as - system_halt - command, - value-0 - Stop - Radio - 1- - Start - Radio */ - sl_bt_system_linklayer_config_key_priority_range = 0x2, /**< - (0x2) - Sets - the - RAIL - priority_mapping - offset - field - of - the - link - layer - priority - configuration - structure - to - the - first - byte - of - the - value - field. */ - sl_bt_system_linklayer_config_key_scan_channels = 0x3, /**< - (0x3) - Sets - channels - to - scan - on. - The - first - byte - of - the - value - is - the - channel - map. - 0x1 - = - Channel - 37, - 0x2 - = - Channel - 38, - 0x4 - = - Channel - 39 */ - sl_bt_system_linklayer_config_key_set_flags = 0x4, /**< - (0x4) - Sets - the - link - layer - configuration - flags. - The - value - is - a - little - endian - 32-bit - integer. - Flag - Values: - - 0x00000001 - \- - Disable - Feature - Exchange - in - peripheral - role - of - the - connection - - 0x00000002 - \- - Disable - Feature - Exchange - in - central - role - of - the - connection */ - sl_bt_system_linklayer_config_key_clr_flags = 0x5, /**< - (0x5) - The - value - is - flags - to - clear. - Flags - are - the - same - as - in - SET_FLAGS - command. */ - sl_bt_system_linklayer_config_key_set_afh_interval = 0x7, /**< - (0x7) - Set - the - afh_scan_interval. - Value - is - in - units - of - 10 - ms. - Setting - the - interval - to - 0 - will - result - in - using - the - default - value - of - 1 - second. */ - sl_bt_system_linklayer_config_key_set_priority_table = 0x9, /**< - (0x9) - The - value - contains - a - priority - table - to - be - copied - over - the - existing - table. - If - the - value - is - smaller - than - the - full - table, - only - those - values - are - updated. - See - sl_bt_bluetooth_ll_priorities - struct - for - the - definition - of - a - priority - table. */ - sl_bt_system_linklayer_config_key_set_rx_packet_filtering = 0xa, /**< - (0xa) - Configure - and - enable - or - disable - RX - packet - filtering - feature. - Value: - >= - 5 - bytes. - - Byte - 1 - \- - The - filter - count - - Byte - 2 - \- - The - filter - offset - - Byte - 3 - \- - The - length - of - the - filter - list - - Byte - 4 - \- - The - bitmask - flags - - Rest - of - the - data - \- - The - filter - list */ - sl_bt_system_linklayer_config_key_set_simultaneous_scanning = 0xb, /**< - (0xb) - Enable - or - disable - simultaneous - scanning - on - the - 1M - and - Coded - PHYs. - Value: - 1 - byte. - - 0 - \- - Disable - simultaneous - scanning. - - 1 - \- - Enable - simultaneous - scanning. */ - sl_bt_system_linklayer_config_key_set_channelmap_flags = 0xc, /**< - (0xc) - Configure - channelmap - adaptivity - flags. - Value: - 4 - bytes. */ - sl_bt_system_linklayer_config_key_power_control_golden_range = 0x10, /**< - (0x10) - Set - Power - Control - golden - range - parameters. - The - value - is - a - 8-bytes - long - array - that - consists - of - 4 - pairs - of - golden - range - configurations. - In - each - pair, - the - first - byte - is - the - lower - RSSI - boundary - and - the - second - byte - is - the - upper - RSSI - boundary. - RSSI - values - are - in - dBm. - This - configuration - is - not - allowed - if - there - are - active - Bluetooth - connections. - - Byte - 1 - \- - Minimal - RSSI - on - 1M - PHY - - Byte - 2 - \- - Maximal - RSSI - on - 1M - PHY - - Byte - 3 - \- - Minimal - RSSI - on - 2M - PHY - - Byte - 4 - \- - Maximal - RSSI - on - 2M - PHY - - Byte - 5 - \- - Minimal - RSSI - on - Coded - PHY - S=8 - - Byte - 6 - \- - Maximal - RSSI - on - Coded - PHY - S=8 - - Byte - 7 - \- - Minimal - RSSI - on - Coded - PHY - S=2 - - Byte - 8 - \- - Maximal - RSSI - on - Coded - PHY - S=2 */ - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit = 0x11, /**< - (0x11) - Value: - uint16_t - Adjust - upper - limit - for - backoff - counter. - If - 0 - restores - default - value - of - 256 - Value - must - be - between - 16 - \- - 256 */ - sl_bt_system_linklayer_config_key_afh_rssi_threshold = 0x12, /**< - (0x12) - Value: - int8_t - Configures - RSSI - limit - for - AFH - channel - blocking */ - sl_bt_system_linklayer_config_key_afh_channel_cooldown = 0x13, /**< - (0x13) - Value: - int16_t - Configures - how - long - channel - is - blocked - after - activity - is - detected - Default: - 8000 */ - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps = 0x14 /**< - (0x14) - Value: - uint8_t - 0 - \- - default, - only - reports - scan - responses - that - is - received - after - sending - scan_req - nonzero - \- - Will - report - all - scan - responses - that - are - received - on - primary - advertising - channels */ -} sl_bt_system_linklayer_config_key_t; - -/** - * @addtogroup sl_bt_evt_system_boot sl_bt_evt_system_boot - * @{ - * @brief Indicates that the device has started and the radio is ready - * - * This event carries the firmware build number and other software and hardware - * identification codes. - */ - -/** @brief Identifier of the boot event */ -#define sl_bt_evt_system_boot_id 0x000100a0 - -/***************************************************************************//** - * @brief Data structure of the boot event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_boot_s -{ - uint16_t major; /**< Major release version */ - uint16_t minor; /**< Minor release version */ - uint16_t patch; /**< Patch release number */ - uint16_t build; /**< Build number */ - uint32_t bootloader; /**< Unused. Ignore this field. */ - uint16_t hw; /**< Hardware type: the major chip revision number in the - most significant byte and the minor revision in the - least significant byte */ - uint32_t hash; /**< Version hash */ -}); - -typedef struct sl_bt_evt_system_boot_s sl_bt_evt_system_boot_t; - -/** @} */ // end addtogroup sl_bt_evt_system_boot - -/** - * @addtogroup sl_bt_evt_system_stopped sl_bt_evt_system_stopped - * @{ - * @brief When the Bluetooth on-demand start component is included in the - * application build, this event is triggered when stopping the Bluetooth stack - * using commands @ref sl_bt_system_stop_bluetooth or @ref - * sl_bt_system_forcefully_stop_bluetooth has completed. - */ - -/** @brief Identifier of the stopped event */ -#define sl_bt_evt_system_stopped_id 0x010100a0 - -/** @} */ // end addtogroup sl_bt_evt_system_stopped - -/** - * @addtogroup sl_bt_evt_system_error sl_bt_evt_system_error - * @{ - * @brief Indicates that an error has occurred - * - * See error codes table for more information. - */ - -/** @brief Identifier of the error event */ -#define sl_bt_evt_system_error_id 0x060100a0 - -/***************************************************************************//** - * @brief Data structure of the error event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_error_s -{ - uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ - uint8array data; /**< Data related to the error; this field can be empty. */ -}); - -typedef struct sl_bt_evt_system_error_s sl_bt_evt_system_error_t; - -/** @} */ // end addtogroup sl_bt_evt_system_error - -/** - * @addtogroup sl_bt_evt_system_hardware_error sl_bt_evt_system_hardware_error - * @{ - * @brief Indicates that a hardware-related error has occurred. - */ - -/** @brief Identifier of the hardware_error event */ -#define sl_bt_evt_system_hardware_error_id 0x050100a0 - -/***************************************************************************//** - * @brief Data structure of the hardware_error event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_hardware_error_s -{ - uint16_t status; /**< SL_STATUS_OK if successful. Error code otherwise. */ -}); - -typedef struct sl_bt_evt_system_hardware_error_s sl_bt_evt_system_hardware_error_t; - -/** @} */ // end addtogroup sl_bt_evt_system_hardware_error - -/** - * @addtogroup sl_bt_evt_system_resource_exhausted sl_bt_evt_system_resource_exhausted - * @{ - * @brief Indicates that a system resource has been exhausted during the - * operation of the Bluetooth stack - * - * If resource errors occur already when the Bluetooth stack is starting, the - * error is reported directly as a return value from sl_bt_stack_init (when the - * Bluetooth on-demand start component is not included in the application - * build), or from @ref sl_bt_system_start_bluetooth (when the on-demand start - * component is included). The fields of this event indicate how many failures - * have occurred for a specific resource. If further resource failures occur - * while this event is already queued in the BGAPI event queue but not yet - * delivered to the application, the new failures are included in the already - * queued event. When the application receives this event, the fields represent - * the number of failures that have occurred since the previous @ref - * sl_bt_evt_system_resource_exhausted event. - */ - -/** @brief Identifier of the resource_exhausted event */ -#define sl_bt_evt_system_resource_exhausted_id 0x080100a0 - -/***************************************************************************//** - * @brief Data structure of the resource_exhausted event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_resource_exhausted_s -{ - uint8_t num_buffers_discarded; /**< The system has temporarily run - out of the pre-allocated data - buffers that are allocated based - on SL_BT_CONFIG_BUFFER_SIZE - configuration and some expendable - data or event had to be discarded - to satisfy a non-expendble buffer - allocation. A typical case is - discarding scan reports when a - large inflow of scan reports - exceeds the speed at which the - application drains the BGAPI - event queue. */ - uint8_t num_buffer_allocation_failures; /**< The system has run out of the - pre-allocated data buffers that - are allocated based on - SL_BT_CONFIG_BUFFER_SIZE - configuration and a buffer - allocation has failed. */ - uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed to - make an allocation from the heap. - Note that only allocations made - by the Bluetooth stack are - detected and reported by this - field. Allocation failures in - other components that use - sl_malloc() or malloc() are not - included in this count. */ -}); - -typedef struct sl_bt_evt_system_resource_exhausted_s sl_bt_evt_system_resource_exhausted_t; - -/** @} */ // end addtogroup sl_bt_evt_system_resource_exhausted - -/** - * @addtogroup sl_bt_evt_system_external_signal sl_bt_evt_system_external_signal - * @{ - * @brief Indicates that the external signals have been received - * - * External signals are generated from the native application. - */ - -/** @brief Identifier of the external_signal event */ -#define sl_bt_evt_system_external_signal_id 0x030100a0 - -/***************************************************************************//** - * @brief Data structure of the external_signal event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_external_signal_s -{ - uint32_t extsignals; /**< Bitmask of external signals received since last - event. */ -}); - -typedef struct sl_bt_evt_system_external_signal_s sl_bt_evt_system_external_signal_t; - -/** @} */ // end addtogroup sl_bt_evt_system_external_signal - -/** - * @addtogroup sl_bt_evt_system_awake sl_bt_evt_system_awake - * @{ - * @brief Indicates that the device is awake and no longer in sleep mode - * - * NOTE: Stack does not generate this event by itself because sleep and - * wakeup are managed by applications. If this event is needed, call function - * @ref sl_bt_send_system_awake, which signals the stack to send the event. - */ - -/** @brief Identifier of the awake event */ -#define sl_bt_evt_system_awake_id 0x040100a0 - -/** @} */ // end addtogroup sl_bt_evt_system_awake - -/** - * @addtogroup sl_bt_evt_system_soft_timer sl_bt_evt_system_soft_timer - * @{ - * @brief Indicates that a soft timer has lapsed. - */ - -/** @brief Identifier of the soft_timer event */ -#define sl_bt_evt_system_soft_timer_id 0x070100a0 - -/***************************************************************************//** - * @brief Data structure of the soft_timer event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_soft_timer_s -{ - uint8_t handle; /**< Timer Handle */ -}); - -typedef struct sl_bt_evt_system_soft_timer_s sl_bt_evt_system_soft_timer_t; - -/** @} */ // end addtogroup sl_bt_evt_system_soft_timer - -/***************************************************************************//** - * - * Verify whether the communication between the host and the device is - * functional. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_hello(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the on-demand start command is not available and the - * command returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to request starting the - * Bluetooth stack when the application needs it. If the command returns a - * success result, the stack starts to asynchronously allocate the resources and - * configure the Bluetooth stack based on the configuration passed at - * initialization time. - * - * The Bluetooth stack cannot be restarted while it's still stopping after - * issuing the command @ref sl_bt_system_stop_bluetooth. If @ref - * sl_bt_system_start_bluetooth is called when stopping is still on-going the - * command returns the error SL_STATUS_INVALID_STATE. The application must wait - * for the @ref sl_bt_evt_system_stopped event before attempting to restart the - * stack. - * - * Successful start of the stack is indicated by the @ref sl_bt_evt_system_boot - * event. The configured classes and Bluetooth stack features are available - * after the application has received the @ref sl_bt_evt_system_boot event. If - * starting the Bluetooth stack fails, the error is indicated to the application - * with the @ref sl_bt_evt_system_error event. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_boot - Triggered when the Bluetooth stack has - * succesfully started and is ready to accept commands from the application - * - @ref sl_bt_evt_system_error - Triggered if the command to start the - * Bluetooth stack was accepted but the asynchronous starting of the stack - * has failed - * - ******************************************************************************/ -sl_status_t sl_bt_system_start_bluetooth(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the stop command is not available and the command - * returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to stop the Bluetooth stack - * when the application no longer needs it. This command gracefully restores - * Bluetooth to an idle state by disconnecting any active connections and - * stopping any on-going advertising and scanning. Any resources that were - * allocated when the stack was started are freed when the stack has finished - * stopping. After this command, the BGAPI classes other than @ref sl_bt_system - * become unavailable. - * - * Stopping the Bluetooth stack with this command is asynchronous and the - * completion is indicated by the @ref sl_bt_evt_system_stopped event. The - * application can use the command @ref sl_bt_system_start_bluetooth to restart - * the stack any time after it has received the @ref sl_bt_evt_system_stopped - * event. If the application needs to stop the Bluetooth stack immediately, use - * the command @ref sl_bt_system_forcefully_stop_bluetooth. That command can - * also be used to immediately complete the asynchronous stopping if the command - * @ref sl_bt_system_stop_bluetooth has not completed in expected time period. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_stopped - Triggered when stopping the Bluetooth - * stack has completed - * - ******************************************************************************/ -sl_status_t sl_bt_system_stop_bluetooth(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the stop command is not available and the command - * returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to forcefully stop the - * Bluetooth stack when the application no longer needs it. This command - * immediately stops all active Bluetooth operations such as advertising, - * scanning, and connections. Active connections are forcefully closed without - * performing the ACL Termination procedure. This can result in the observation - * of connection loss or supervision timeout on the remote device. Only use this - * command for special cases, for example, when stopping Bluetooth with @ref - * sl_bt_system_stop_bluetooth did not complete in expected time period. - * - * Stopping the Bluetooth stack with this command is immediate and it directly - * triggers the @ref sl_bt_evt_system_stopped event. Any resources that were - * allocated when the stack was started are freed. After this command, the BGAPI - * classes other than @ref sl_bt_system become unavailable. The application can - * use the command @ref sl_bt_system_start_bluetooth to continue using Bluetooth - * later. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_stopped - Triggered immediately to indicate the - * Bluetooth stack has stopped - * - ******************************************************************************/ -sl_status_t sl_bt_system_forcefully_stop_bluetooth(); - -/***************************************************************************//** - * - * Get the firmware version information. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * @param[out] major Major release version - * @param[out] minor Minor release version - * @param[out] patch Patch release number - * @param[out] build Build number - * @param[out] bootloader Unused. Ignore this field. - * @param[out] hash Version hash - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_version(uint16_t *major, - uint16_t *minor, - uint16_t *patch, - uint16_t *build, - uint32_t *bootloader, - uint32_t *hash); - -/***************************************************************************//** - * - * Reset the system. This command does not have a response. - * - * On EFR series 1 devices, this command boots into the given mode and triggers - * one of the boot events (normal reset or boot to DFU mode) depending on the - * given boot mode. - * - * On EFR series 2 devices, the @p dfu parameter is ignored and this command - * always boots the user application. To boot into a DFU mode on series 2, use - * the Bootloader API @c bootloader_rebootAndInstall. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * @param[in] dfu @parblock - * Enum @ref sl_bt_system_boot_mode_t. Boot mode. Values: - * - sl_bt_system_boot_mode_normal (0x0): Boot to normal mode - * - sl_bt_system_boot_mode_uart_dfu (0x1): Boot to UART DFU mode - * - sl_bt_system_boot_mode_ota_dfu (0x2): Boot to OTA DFU mode - * - * This parameter is ignored on EFR series 2 devices. - * @endparblock - * - * @b Events - * - @ref sl_bt_evt_system_boot - Sent after the device has booted in normal - * mode. - * - @ref sl_bt_evt_dfu_boot - Sent after the device has booted in UART DFU - * mode. - * - ******************************************************************************/ -void sl_bt_system_reset(uint8_t dfu); - -/***************************************************************************//** - * - * Force radio to idle state and allow device to sleep. Advertising, scanning, - * connections, and software timers are halted by this command. Halted - * operations resume after calling this command with parameter 0. Connections - * stay alive if the system is resumed before connection supervision timeout. - * - * Use this command only for a short time period (maximum few seconds). Although - * it halts Bluetooth activity, all tasks and operations still exist inside the - * stack with their own concepts of time. Halting the system for a long time - * period may have negative consequences on stack's internal states. - * - * NOTE: The software timer is also halted. Hardware interrupts are the - * only way to wake up from energy mode 2 when the system is halted. - * - * @param[in] halt Values: - * - 1: halt - * - 0: resume - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_halt(uint8_t halt); - -/***************************************************************************//** - * - * Send configuration data to the link layer. This command fine tunes low-level - * Bluetooth operations. - * - * @param[in] key @parblock - * Enum @ref sl_bt_system_linklayer_config_key_t. Key to configure. Values: - * - sl_bt_system_linklayer_config_key_halt (0x1): Same as - * system_halt command, value-0 Stop Radio 1- Start Radio - * - sl_bt_system_linklayer_config_key_priority_range (0x2): Sets the - * RAIL priority_mapping offset field of the link layer priority - * configuration structure to the first byte of the value field. - * - sl_bt_system_linklayer_config_key_scan_channels (0x3): Sets - * channels to scan on. The first byte of the value is the channel map. - * 0x1 = Channel 37, 0x2 = Channel 38, 0x4 = Channel 39 - * - sl_bt_system_linklayer_config_key_set_flags (0x4): Sets the link - * layer configuration flags. The value is a little endian 32-bit integer. - * Flag Values: - * - 0x00000001 - Disable Feature Exchange in peripheral role of the - * connection - * - 0x00000002 - Disable Feature Exchange in central role of the - * connection - * - * - sl_bt_system_linklayer_config_key_clr_flags (0x5): The value is - * flags to clear. Flags are the same as in SET_FLAGS command. - * - sl_bt_system_linklayer_config_key_set_afh_interval (0x7): Set - * the afh_scan_interval. Value is in units of 10 ms. Setting the interval - * to 0 will result in using the default value of 1 second. - * - sl_bt_system_linklayer_config_key_set_priority_table (0x9): The - * value contains a priority table to be copied over the existing table. - * If the value is smaller than the full table, only those values are - * updated. See sl_bt_bluetooth_ll_priorities struct for the definition of - * a priority table. - * - sl_bt_system_linklayer_config_key_set_rx_packet_filtering (0xa): - * Configure and enable or disable RX packet filtering feature. Value: >= - * 5 bytes. - * - Byte 1 - The filter count - * - Byte 2 - The filter offset - * - Byte 3 - The length of the filter list - * - Byte 4 - The bitmask flags - * - Rest of the data - The filter list - * - * - sl_bt_system_linklayer_config_key_set_simultaneous_scanning - * (0xb): Enable or disable simultaneous scanning on the 1M and Coded - * PHYs. Value: 1 byte. - * - 0 - Disable simultaneous scanning. - * - 1 - Enable simultaneous scanning. - * - * - sl_bt_system_linklayer_config_key_set_channelmap_flags (0xc): - * Configure channelmap adaptivity flags. Value: 4 bytes. - * - sl_bt_system_linklayer_config_key_power_control_golden_range - * (0x10): Set Power Control golden range parameters. The value is a - * 8-bytes long array that consists of 4 pairs of golden range - * configurations. In each pair, the first byte is the lower RSSI boundary - * and the second byte is the upper RSSI boundary. RSSI values are in dBm. - * This configuration is not allowed if there are active Bluetooth - * connections. - * - Byte 1 - Minimal RSSI on 1M PHY - * - Byte 2 - Maximal RSSI on 1M PHY - * - Byte 3 - Minimal RSSI on 2M PHY - * - Byte 4 - Maximal RSSI on 2M PHY - * - Byte 5 - Minimal RSSI on Coded PHY S=8 - * - Byte 6 - Maximal RSSI on Coded PHY S=8 - * - Byte 7 - Minimal RSSI on Coded PHY S=2 - * - Byte 8 - Maximal RSSI on Coded PHY S=2 - * - * - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit - * (0x11): Value: uint16_t Adjust upper limit for backoff counter. If - * 0 restores default value of 256 Value must be between 16 - 256 - * - sl_bt_system_linklayer_config_key_afh_rssi_threshold (0x12): - * Value: int8_t Configures RSSI limit for AFH channel blocking - * - sl_bt_system_linklayer_config_key_afh_channel_cooldown (0x13): - * Value: int16_t Configures how long channel is blocked after activity is - * detected Default: 8000 - * - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps - * (0x14): Value: uint8_t 0 - default, only reports scan responses - * that is received after sending scan_req nonzero - Will report all scan - * responses that are received on primary advertising channels - * @endparblock - * @param[in] data_len Length of data in @p data - * @param[in] data Configuration data. Length and contents of the data field - * depend on the key value used. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_linklayer_configure(uint8_t key, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set the global minimum and maximum radiated TX power levels for Bluetooth. - * This returns selected power levels that are radiated from the antenna at TX. - * The transmitter power at antenna pin will apply the RF TX path gain to match - * this setting. RF TX path gain can be set in the Bluetooth configuration. If - * the GATT server contains a TX power service, the TX Power Level attribute - * will be updated with the selected maximum power level. - * - * A selected power level may be different than the requested value because of - * Bluetooth feature restrictions or the device's radio characteristics. For - * Bluetooth connections, the maximum radiated TX power is limited to 10 dBm if - * Adaptive Frequency Hopping (AFH) is not enabled. - * - * The minimum TX power setting is used by LE power control. It has no effect in - * Bluetooth stack if the LE power control feature is not enabled. However, the - * application may still use this setting for other purposes, e.g., setting the - * minimum TX power for DTM transmitter test. - * - * The minimum and maximum radiated TX power levels can also be configured in - * the Bluetooth configuration and passed into the Bluetooth stack - * initialization. By default, the minimum radiated TX power level is configured - * to -3 dBm and the maximum radiated TX power level to 8 dBm. - * - * NOTE: Do not use this command while advertising or scanning. - * Furthermore, the stack does not allow setting TX powers during connections. - * - * @param[in] min_power Minimum radiated TX power. Unit: 0.1 dBm. For example, - * the value 10 means 1 dBm. - * @param[in] max_power Maximum radiated TX power. Unit: 0.1 dBm. For example, - * the value 10 means 1 dBm. - * @param[out] set_min The selected minimum radiated TX power. Unit: 0.1 dBm - * @param[out] set_max The selected maximum radiated TX power. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_tx_power(int16_t min_power, - int16_t max_power, - int16_t *set_min, - int16_t *set_max); - -/***************************************************************************//** - * - * Get TX power settings including the minimum and maximum radiated TX power - * levels the device supports, the minimum and maximum radiated TX power levels - * currently set in the stack, and the TX RF path gain configuration. - * - * @param[out] support_min The minimum radiated TX power the device supports. - * Unit: 0.1 dBm - * @param[out] support_max The maximum radiated TX power the device supports. - * Unit: 0.1 dBm - * @param[out] set_min The minimum radiated TX power currently set in stack. - * Unit: 0.1 dBm - * @param[out] set_max The maximum radiated TX power currently set in stack. - * Unit: 0.1 dBm - * @param[out] rf_path_gain TX RF path gain. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, - int16_t *support_max, - int16_t *set_min, - int16_t *set_max, - int16_t *rf_path_gain); - -/***************************************************************************//** - * - * Store the device's Bluetooth identity address in persistent storage using NVM - * keys. The address can be a public device address or a static device address. - * The stack returns an error if the static device address does not conform to - * the Bluetooth specification. - * - * The new address will be effective in the next system reboot. The stack will - * use the address in the NVM keys when present. Otherwise, it uses the default - * Bluetooth public device address which is programmed at production. - * - * The stack treats 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid - * addresses. Therefore, passing one of them into this command will cause the - * stack to delete the NVM keys and use the default address in the next system - * reboot. - * - * Note: Because the NVM keys are located in flash and flash wearing can - * occur, avoid calling this command regularly. - * - * @param[in] address Bluetooth identity address in little endian format - * @param[in] type Enum @ref sl_bt_gap_address_type_t. Identity address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type); - -/***************************************************************************//** - * - * Read the Bluetooth identity address used by the device, which can be a public - * or random static device address. - * - * @param[out] address Bluetooth identity address in little endian format - * @param[out] type Enum @ref sl_bt_gap_address_type_t. Identity address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type); - -/***************************************************************************//** - * - * Get random data. - * - * @param[in] length Length of random data. - * @param[in] max_data_size Size of output buffer passed in @p data - * @param[out] data_len On return, set to the length of output data written to - * @p data - * @param[out] data Random data - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_random_data(uint8_t length, - size_t max_data_size, - size_t *data_len, - uint8_t *data); - -/***************************************************************************//** - * - * Write data into the system data buffer. Data will be appended to the end of - * existing data. - * - * @param[in] data_len Length of data in @p data - * @param[in] data Data to write - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_data_buffer_write(size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Remove all data from the system data buffer. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_data_buffer_clear(); - -/***************************************************************************//** - * - * Get packet and error counters. Passing a non-zero value also resets counters. - * - * @param[in] reset Reset counters if the parameter value is not zero. - * @param[out] tx_packets The number of successfully transmitted packets - * @param[out] rx_packets The number of successfully received packets - * @param[out] crc_errors The number of received packets with CRC errors - * @param[out] failures The number of radio failures, such as aborted TX/RX - * packets, scheduling failures, and so on. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_counters(uint8_t reset, - uint16_t *tx_packets, - uint16_t *rx_packets, - uint16_t *crc_errors, - uint16_t *failures); - -/***************************************************************************//** - * - * Deprecated . Use the sleeptimer component (in platform services - * category) for timers. Because the sleeptimer does not support a timer with - * slack yet, the Bluetooth stack will continue to support this command until - * another component provides the functionality. - * - * Start a software timer with slack. The slack parameter allows the stack to - * optimize wakeups and save power. The timer event is triggered between time - * and time + @p slack. - * - * Multiple concurrent timers can be running simultaneously. 256 unique timer - * handles (IDs) are available. The maximum number of concurrent timers is - * configurable at device initialization. Up to 16 concurrent timers can be - * configured. The default configuration is 4. As the RAM for storing timer data - * is pre-allocated at initialization, an application should not configure the - * amount more than it needs for minimizing RAM usage. - * - * @param[in] time @parblock - * An interval between how often to send events in hardware clock ticks (1 - * second is equal to 32768 ticks). - * - * The smallest interval value supported is 328, which is around 10 - * milliseconds. Any parameters between 0 and 328 will be rounded up to 328. - * The maximum value is 2147483647, which corresponds to about 18.2 hours. - * - * If @p time is 0, removes the scheduled timer with the same handle. - * @endparblock - * @param[in] slack Slack time in hardware clock ticks - * @param[in] handle Timer handle to use, which is returned in timeout event - * @param[in] single_shot Timer mode. Values: - * - 0: false (timer is repeating) - * - 1: true (timer runs only once) - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_soft_timer - Sent after this timer has lapsed. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, - uint32_t slack, - uint8_t handle, - uint8_t single_shot); - -/** @} */ // end addtogroup sl_bt_system - -/** - * @addtogroup sl_bt_resource Resource Report - * @{ - * - * @brief Resource Report - * - * Commands and events in this class can be used to query and receive the memory - * buffer usage status. The memory buffer is used by the Bluetooth stack for - * storing application data (e.g., API commands and events), user data over - * Bluetooth connections, advertising, scanning, etc. Total buffer size is - * defined by the application using the SL_BT_CONFIG_BUFFER_SIZE configuration. - * The Bluetooth stack does not partition the buffer, instead, the buffer is a - * shared resource for all features. Therefore, the available memory for one - * feature could be affected by another feature in simultaneous use cases. This - * API class provides a utility for application to get some insight of the - * buffer usage. As allocations in the memory buffer have overhead, the actual - * amount of memory that can be used for user data is less than a reported free - * memory amount. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_resource_get_status_id 0x005f0020 -#define sl_bt_cmd_resource_set_report_threshold_id 0x015f0020 -#define sl_bt_cmd_resource_enable_connection_tx_report_id 0x025f0020 -#define sl_bt_cmd_resource_get_connection_tx_status_id 0x035f0020 -#define sl_bt_cmd_resource_disable_connection_tx_report_id 0x045f0020 -#define sl_bt_rsp_resource_get_status_id 0x005f0020 -#define sl_bt_rsp_resource_set_report_threshold_id 0x015f0020 -#define sl_bt_rsp_resource_enable_connection_tx_report_id 0x025f0020 -#define sl_bt_rsp_resource_get_connection_tx_status_id 0x035f0020 -#define sl_bt_rsp_resource_disable_connection_tx_report_id 0x045f0020 - -/** - * @addtogroup sl_bt_resource_connection_tx_flags Connection TX status flags - * @{ - * - * Defines the connection TX status flags reported by @ref - * sl_bt_resource_get_connection_tx_status. - */ - -/** - * - * The number of TX packets queued on a connection has overflowed the @p - * packet_count that was effective at the time the connection opened. The packet - * count is configured with command @ref - * sl_bt_resource_enable_connection_tx_report and is valid for subsequent - * connections. - * - * When this bit is set, the @p packet_count returned by @ref - * sl_bt_resource_get_connection_tx_status is correct, but @p data_len excludes - * the data bytes in the packets that overflowed the configured packet count. - * - * */ -#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_PACKET_OVERFLOW 0x1 - -/** - * - * Internal inconsistency has been detected in the connection TX bookkeeping. - * When this bit is set, the application should consider both @p packet_count - * and @p data_len returned by @ref sl_bt_resource_get_connection_tx_status to - * be unreliable. - * - * */ -#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_CORRUPT 0x2 - -/** @} */ // end Connection TX status flags - -/** - * @addtogroup sl_bt_evt_resource_status sl_bt_evt_resource_status - * @{ - * @brief Indicates that the memory buffer usage has crossed a threshold - */ - -/** @brief Identifier of the status event */ -#define sl_bt_evt_resource_status_id 0x005f00a0 - -/***************************************************************************//** - * @brief Data structure of the status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_resource_status_s -{ - uint32_t free_bytes; /**< The number of free bytes in the memory buffer */ -}); - -typedef struct sl_bt_evt_resource_status_s sl_bt_evt_resource_status_t; - -/** @} */ // end addtogroup sl_bt_evt_resource_status - -/***************************************************************************//** - * - * Get the present memory buffer usage status. - * - * @param[out] total_bytes The number of total bytes in the memory buffer - * @param[out] free_bytes The number of free bytes in the memory buffer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, - uint32_t *free_bytes); - -/***************************************************************************//** - * - * Set low and high thresholds of memory buffer usage reports. Value 0 in - * parameter @p low for the low threshold disables the reporting, and a non-zero - * value in @p low enables the reporting. - * - * When the reporting is enabled, event @ref sl_bt_evt_resource_status will be - * generated to report the status when the free buffer amount decreases and - * crosses the low threshold, and later another event will be generated if the - * free buffer amount increases and crosses the high threshold. If only the high - * threshold is crossed but the low threshold isn't, no event will be generated. - * - * By default, low and high threshold values are 0, i.e., no report event is - * generated. - * - * @param[in] low The low threshold of free bytes in the memory buffer, or 0 to - * disable the reporting - * @param[in] high A non-zero value as the high threshold that must be greater - * than parameter @p low, or 0 for not reporting the status for high threshold - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high); - -/***************************************************************************//** - * - * Enable tracking and reporting data packet TX status of future new - * connections. Existing connections are not affected by this command. - * - * @param[in] packet_count The maximum number of data packets to track on a - * connection - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_server_notification_tx_completed - Sent when GATT - * notifications from the GATT server were transmitted. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count); - -/***************************************************************************//** - * - * Get the data packet TX status of a connection. - * - * @param[in] connection Connection handle - * @param[out] flags Flags that indicate the status of connection TX packet - * reporting. This value is a bitmask of @ref - * sl_bt_resource_connection_tx_flags. - * @param[out] packet_count Number of data packets in the TX queue waiting to be - * transmitted - * @param[out] data_len Total number of bytes of data packets in the TX queue - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, - uint16_t *flags, - uint16_t *packet_count, - uint32_t *data_len); - -/***************************************************************************//** - * - * Disable tracking and reporting data packet TX status of future new - * connections. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_disable_connection_tx_report(); - -/** @} */ // end addtogroup sl_bt_resource - -/** - * @addtogroup sl_bt_gap GAP - * @{ - * - * @brief GAP - * - * The commands and events in this class are related to the Generic Access - * Profile (GAP) in Bluetooth. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gap_set_privacy_mode_id 0x01020020 -#define sl_bt_cmd_gap_set_data_channel_classification_id 0x02020020 -#define sl_bt_cmd_gap_enable_whitelisting_id 0x03020020 -#define sl_bt_cmd_gap_set_identity_address_id 0x04020020 -#define sl_bt_rsp_gap_set_privacy_mode_id 0x01020020 -#define sl_bt_rsp_gap_set_data_channel_classification_id 0x02020020 -#define sl_bt_rsp_gap_enable_whitelisting_id 0x03020020 -#define sl_bt_rsp_gap_set_identity_address_id 0x04020020 - -/** - * @brief These values define Bluetooth device address types. Commands and - * events that have Bluetooth device address parameters will specify which - * values are valid for that particular command or event. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, most Bluetooth - * commands and events use a coarse address type that only differentiates - * between a public address and any random address. When the application - * includes the bluetooth_feature_use_accurate_api_address_types component, - * Bluetooth commands and events that include an address type will - * systematically use values of this @ref sl_bt_gap_address_type_t enumeration - * to indicate the accurate address type. - * - * The values @ref sl_bt_gap_public_address_resolved_from_rpa and @ref - * sl_bt_gap_static_address_resolved_from_rpa are reported by the Bluetooth - * stack only when the application includes the bluetooth_feature_resolving_list - * component and the address was resolved in the Bluetooth controller. If the - * application uses these two types in input parameters, they are treated as - * synonyms of @ref sl_bt_gap_public_address and @ref sl_bt_gap_static_address, - * respectively. - */ -typedef enum -{ - sl_bt_gap_public_address = 0x0, /**< (0x0) Public device - address */ - sl_bt_gap_static_address = 0x1, /**< (0x1) Static device - address */ - sl_bt_gap_random_resolvable_address = 0x2, /**< (0x2) Resolvable - private random address */ - sl_bt_gap_random_nonresolvable_address = 0x3, /**< (0x3) Non-resolvable - private random address */ - sl_bt_gap_public_address_resolved_from_rpa = 0x4, /**< (0x4) Public identity - address resolved from - a resolvable private - address (RPA) */ - sl_bt_gap_static_address_resolved_from_rpa = 0x5, /**< (0x5) Static identity - address resolved from - a resolvable private - address (RPA) */ - sl_bt_gap_anonymous_address = 0xff /**< (0xff) No address - provided (anonymous - advertising) */ -} sl_bt_gap_address_type_t; - -/** - * @brief Types of PHYs - */ -typedef enum -{ - sl_bt_gap_phy_1m = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_phy_2m = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_phy_coded = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ - sl_bt_gap_phy_any = 0xff /**< (0xff) Any PHYs the device supports */ -} sl_bt_gap_phy_t; - -/** - * @brief PHY types with coding schemes - */ -typedef enum -{ - sl_bt_gap_phy_coding_1m_uncoded = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_phy_coding_2m_uncoded = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_phy_coding_125k_coded = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ - sl_bt_gap_phy_coding_500k_coded = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ -} sl_bt_gap_phy_coding_t; - -/** - * @brief Types of channel selection algorithms in Link Layer - */ -typedef enum -{ - sl_bt_gap_channel_selection_algorithm_1 = 0x0, /**< (0x0) Channel selection - algorithm #1 */ - sl_bt_gap_channel_selection_algorithm_2 = 0x1 /**< (0x1) Channel selection - algorithm #2 */ -} sl_bt_gap_channel_selection_algorithm_t; - -/***************************************************************************//** - * - * Enable or disable the privacy feature on all GAP roles. New privacy mode will - * take effect for advertising next time advertising is enabled, for scanning - * next time scanning is enabled, and for initiating on the next open connection - * command. - * - * When privacy is enabled and the device is advertising or scanning, the stack - * will maintain a periodic timer with the specified time interval as a timeout - * value. At each timeout, the stack generates a new resolvable private address - * and uses it in scanning requests. For advertisers, the stack generates a new - * resolvable or non-resolvable private address and uses it in advertising data - * packets for each advertising set if its address is not application-managed, - * i.e., the address was not set by the application (with the @ref - * sl_bt_advertiser_set_random_address command). The application is fully - * responsible for application-managed advertiser addresses. For an - * application-managed resolvable private address, the application should - * schedule periodic address updates for enhancing the privacy. It is - * recommended to use different schedules for different advertising sets. - * - * Disabling the privacy during active advertising or scanning is not allowed. - * - * By default, privacy feature is disabled. - * - * @param[in] privacy Values: - * - 0: Disable privacy - * - 1: Enable privacy - * @param[in] interval The minimum time interval between a private address - * change. This parameter is ignored if this command is issued to disable - * privacy mode. Values: - * - 0: Use default interval, 15 minutes - * - others: The time interval in minutes - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval); - -/***************************************************************************//** - * - * Specify a channel classification for data channels. This classification - * persists until overwritten with a subsequent command or until the system is - * reset. The value length of @p channel_map must be 5 bytes. - * - * @param[in] channel_map_len Length of data in @p channel_map - * @param[in] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Bits 37-39 are reserved for future use and must be set to 0. - * - * A channel is bad when its bit is 0. A channel is unknown when its bit is 1. - * At least two channels shall be marked as unknown. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, - const uint8_t* channel_map); - -/***************************************************************************//** - * - * Deprecated and replaced by functionality-specific settings provided by - * the bluetooth_feature_accept_list component. For advertising, use the command - * @ref sl_bt_advertiser_configure and @p flags bits @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to configure the - * advertising filter policy. For scanning, use the command @ref - * sl_bt_scanner_set_parameters_and_filter to control the scanning filter - * policy. - * - * Enable or disable accept list filtering. The setting will be effective the - * next time that scanning is enabled. Use command @ref - * sl_bt_sm_add_to_whitelist to add devices to the accept list. - * - * When the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) is used, bonded devices are - * added into the accept list automatically by the stack. Note that the - * Bluetooth stack uses the built-in bonding database by default. - * - * When the application specifically uses the external bonding database - * (bluetooth_feature_external_bonding_database), the application is fully - * responsible for managing the accept list using @ref sl_bt_sm_add_to_whitelist - * and @ref sl_bt_sm_delete_bondings commands. - * - * @param[in] enable 1 enable, 0 disable accept list filtering. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable); - -/***************************************************************************//** - * - * Set the device's Bluetooth identity address to be used in advertising, - * scanning, connection initiation, and identity address exchange in bonding. - * The address is stored in RAM only and does not change the identity address in - * persistent storage. The address can be a public device address or static - * device address. It will be effective immediately in the next advertising, - * scanning, connection initiation, and bonding. Error - * SL_STATUS_INVALID_PARAMETER is returned if the address does not conform to - * the Bluetooth specification. - * - * Note that advertising sets that have own addresses set by @ref - * sl_bt_advertiser_set_random_address are not affected by this command, i.e., - * they will continue to use their own user defined addresses. - * - * @param[in] address The address in little endian format - * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. The address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type); - -/** @} */ // end addtogroup sl_bt_gap - -/** - * @addtogroup sl_bt_advertiser Advertiser - * @{ - * - * @brief Advertiser - * - * This is the base class of legacy, extended, and periodic advertisings for - * common functionalities including advertising set management, TX power - * setting, advertising address, and so on. - * - * On an advertising set, either the legacy or extended advertising can be - * enabled at a time but they cannot be enabled simultaneously on the same - * advertising set. For example, the following sequence shows how to start the - * legacy advertising on an advertising set. Starting the extended advertising - * is similar. The only difference is to use the extended_advertiser API class. - * 1. Create an advertise set with the @ref sl_bt_advertiser_create_set - * command. - * 2. Configure and set advertising parameters for the advertising set as - * needed. - * 3. Set the advertising data with the @ref sl_bt_legacy_advertiser_set_data - * or @ref sl_bt_legacy_advertiser_generate_data command. - * 4. Start the legacy advertising with the @ref sl_bt_legacy_advertiser_start - * command. - * - * Periodic advertising can be enabled independently on the advertising set - * regardless of the state of the legacy or extended advertising. However, to - * ensure that scanners can find the periodic advertising information and - * establish a synchronization, the extended advertising must be enabled - * simultaneously with the periodic advertising. - * - * When the bluetooth_feature_legacy_advertiser, - * bluetooth_feature_extended_advertiser or - * bluetooth_feature_periodic_advertiser component is included by the - * application, commands that have been superseded by the new classes are no - * longer available for use in the advertiser class. Calling them will receive - * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: @ref - * sl_bt_advertiser_set_phy, @ref sl_bt_advertiser_set_configuration, @ref - * sl_bt_advertiser_clear_configuration, @ref sl_bt_advertiser_set_data, @ref - * sl_bt_advertiser_set_long_data, @ref sl_bt_advertiser_start, @ref - * sl_bt_advertiser_start_periodic_advertising, and @ref - * sl_bt_advertiser_stop_periodic_advertising. See the command descriptions for - * the replacements. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_advertiser_create_set_id 0x01040020 -#define sl_bt_cmd_advertiser_configure_id 0x12040020 -#define sl_bt_cmd_advertiser_set_timing_id 0x03040020 -#define sl_bt_cmd_advertiser_set_channel_map_id 0x04040020 -#define sl_bt_cmd_advertiser_set_tx_power_id 0x0b040020 -#define sl_bt_cmd_advertiser_set_report_scan_request_id 0x05040020 -#define sl_bt_cmd_advertiser_set_random_address_id 0x10040020 -#define sl_bt_cmd_advertiser_clear_random_address_id 0x11040020 -#define sl_bt_cmd_advertiser_stop_id 0x0a040020 -#define sl_bt_cmd_advertiser_delete_set_id 0x02040020 -#define sl_bt_cmd_advertiser_set_phy_id 0x06040020 -#define sl_bt_cmd_advertiser_set_configuration_id 0x07040020 -#define sl_bt_cmd_advertiser_clear_configuration_id 0x08040020 -#define sl_bt_cmd_advertiser_set_data_id 0x0f040020 -#define sl_bt_cmd_advertiser_set_long_data_id 0x0e040020 -#define sl_bt_cmd_advertiser_start_id 0x09040020 -#define sl_bt_cmd_advertiser_start_periodic_advertising_id 0x0c040020 -#define sl_bt_cmd_advertiser_stop_periodic_advertising_id 0x0d040020 -#define sl_bt_rsp_advertiser_create_set_id 0x01040020 -#define sl_bt_rsp_advertiser_configure_id 0x12040020 -#define sl_bt_rsp_advertiser_set_timing_id 0x03040020 -#define sl_bt_rsp_advertiser_set_channel_map_id 0x04040020 -#define sl_bt_rsp_advertiser_set_tx_power_id 0x0b040020 -#define sl_bt_rsp_advertiser_set_report_scan_request_id 0x05040020 -#define sl_bt_rsp_advertiser_set_random_address_id 0x10040020 -#define sl_bt_rsp_advertiser_clear_random_address_id 0x11040020 -#define sl_bt_rsp_advertiser_stop_id 0x0a040020 -#define sl_bt_rsp_advertiser_delete_set_id 0x02040020 -#define sl_bt_rsp_advertiser_set_phy_id 0x06040020 -#define sl_bt_rsp_advertiser_set_configuration_id 0x07040020 -#define sl_bt_rsp_advertiser_clear_configuration_id 0x08040020 -#define sl_bt_rsp_advertiser_set_data_id 0x0f040020 -#define sl_bt_rsp_advertiser_set_long_data_id 0x0e040020 -#define sl_bt_rsp_advertiser_start_id 0x09040020 -#define sl_bt_rsp_advertiser_start_periodic_advertising_id 0x0c040020 -#define sl_bt_rsp_advertiser_stop_periodic_advertising_id 0x0d040020 - -/** - * @brief These values define the available connection modes, which indicate - * whether the device accepts connection requests or scan requests. - */ -typedef enum -{ - sl_bt_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable - non-scannable */ - sl_bt_advertiser_connectable_scannable = 0x2, /**< (0x2) Undirected - connectable scannable. - This mode can only be - used in legacy - advertising PDUs. */ - sl_bt_advertiser_scannable_non_connectable = 0x3, /**< (0x3) Undirected - scannable - (Non-connectable but - responds to scan - requests) */ - sl_bt_advertiser_connectable_non_scannable = 0x4 /**< (0x4) Undirected - connectable - non-scannable. This - mode can only be used - in extended advertising - PDUs. */ -} sl_bt_advertiser_connection_mode_t; - -/** - * @brief These values define the available discovery modes, which dictate how - * the device is visible to other devices in the legacy and extended - * advertising. - */ -typedef enum -{ - sl_bt_advertiser_non_discoverable = 0x0, /**< (0x0) Not discoverable */ - sl_bt_advertiser_limited_discoverable = 0x1, /**< (0x1) Discoverable by both - limited and general - discovery procedures */ - sl_bt_advertiser_general_discoverable = 0x2, /**< (0x2) Discoverable by the - general discovery procedure */ - sl_bt_advertiser_broadcast = 0x3, /**< (0x3) Device is not - discoverable in either - limited or generic discovery - procedure but may be - discovered using the - Observation procedure. */ - sl_bt_advertiser_user_data = 0x4 /**< (0x4) Send advertising - and/or scan response data - defined by the user. The - discovery mode is defined by - the user. */ -} sl_bt_advertiser_discovery_mode_t; - -/** - * @brief Address type to use for the legacy and extended advertising - */ -typedef enum -{ - sl_bt_advertiser_identity_address = 0x0, /**< (0x0) Use public or static - device address, or an identity - address if privacy mode is - enabled. */ - sl_bt_advertiser_non_resolvable = 0x1 /**< (0x1) Use non-resolvable address - type; the advertising must be - non-connectable. */ -} sl_bt_advertiser_adv_address_type_t; - -/** - * @brief These values define the packet types in legacy and extended - * advertising. - */ -typedef enum -{ - sl_bt_advertiser_advertising_data_packet = 0x0, /**< (0x0) Advertising data - packet */ - sl_bt_advertiser_scan_response_packet = 0x1 /**< (0x1) Scan response - packet */ -} sl_bt_advertiser_packet_type_t; - -/** - * @addtogroup sl_bt_advertiser_flags Generic Advertising Configuration Flags - * @{ - * - * This enum defines configuration flags common for legacy and extended - * advertisings. - */ - -/** Use a non-resolvable private address managed by the stack. The advertising - * must be non-connectable when using this configuration. The stack generates a - * non-resolvable private address for the advertising set and the stack will - * update the address periodically in privacy mode. By default this flag is not - * set, i.e., the advertising address uses the device identity address. This - * configuration has no effect if the advertising address has been set with the - * @ref sl_bt_advertiser_set_random_address command. */ -#define SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS 0x4 - -/** Use the device identity address when privacy mode is enabled. By default, - * this flag is not set, i.e., the advertising address uses a resolvable private - * address managed by the stack in privacy mode. This configuration has no - * effect if the @ref SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS flag is set or - * the advertising address has been set with the @ref - * sl_bt_advertiser_set_random_address command. */ -#define SL_BT_ADVERTISER_USE_DEVICE_IDENTITY_IN_PRIVACY 0x10 - -/** - * - * Use the Filter Accept List to filter scan requests received while performing - * scannable advertising with this advertising set. By default, this flag is not - * set and scan requests from all devices are processed. If the application sets - * this flag, scan requests are processed only from those devices that the - * application has added to the Filter Accept List. - * - * This configuration is supported only when the application has included the - * Bluetooth component bluetooth_feature_accept_list. - * - * */ -#define SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS 0x20 - -/** - * - * Use the Filter Accept List to filter connection requests received while - * performing connectable advertising with this advertising set. By default, - * this flag is not set and connection requests from all devices are processed. - * If the application sets this flag, connection requests are processed only - * from those devices that the application has added to the Filter Accept List. - * - * This configuration is supported only when the application has included the - * Bluetooth component bluetooth_feature_accept_list. - * - * */ -#define SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS 0x40 - -/** @} */ // end Generic Advertising Configuration Flags - -/** - * @addtogroup sl_bt_evt_advertiser_timeout sl_bt_evt_advertiser_timeout - * @{ - * @brief Indicates the legacy or extended advertising on an advertising set has - * stopped because the advertiser has completed the configured number of - * advertising events or the advertising has reached the configured duration - * - * The maximum number of advertising events or advertising duration can be - * configured by the @p maxevents or @p duration parameter in the command @ref - * sl_bt_advertiser_set_timing. - */ - -/** @brief Identifier of the timeout event */ -#define sl_bt_evt_advertiser_timeout_id 0x010400a0 - -/***************************************************************************//** - * @brief Data structure of the timeout event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_advertiser_timeout_s -{ - uint8_t handle; /**< The advertising set handle */ -}); - -typedef struct sl_bt_evt_advertiser_timeout_s sl_bt_evt_advertiser_timeout_t; - -/** @} */ // end addtogroup sl_bt_evt_advertiser_timeout - -/** - * @addtogroup sl_bt_evt_advertiser_scan_request sl_bt_evt_advertiser_scan_request - * @{ - * @brief Reports a scan request received during the legacy or extended - * advertising advertising if the scan request notification is enabled - * - * Do not confuse this event with the @ref sl_bt_evt_scanner_scan_report event. - */ - -/** @brief Identifier of the scan_request event */ -#define sl_bt_evt_advertiser_scan_request_id 0x020400a0 - -/***************************************************************************//** - * @brief Data structure of the scan_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_advertiser_scan_request_s -{ - uint8_t handle; /**< Advertising set handle where the scan request was - received */ - bd_addr address; /**< Bluetooth address of the scanner */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Scanner address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): Public - device address - - sl_bt_gap_static_address (0x1): Static - device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote scanning device has - previously bonded with the local device. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): No - bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_advertiser_scan_request_s sl_bt_evt_advertiser_scan_request_t; - -/** @} */ // end addtogroup sl_bt_evt_advertiser_scan_request - -/***************************************************************************//** - * - * Create an advertising set that can be used for legacy, extended, or periodic - * advertising. The handle of the created advertising set is returned in - * response if the operation succeeds. - * - * The maximum number of advertising sets for user advertisers is limited by the - * SL_BT_CONFIG_USER_ADVERTISERS configuration. - * - * @param[out] handle Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_create_set(uint8_t *handle); - -/***************************************************************************//** - * - * Configure the legacy and extended advertising on an advertising set. The - * configuration will take effect next time the legacy or extended advertising - * is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] flags @parblock - * Configuration flags. Value: 0 or bitmask of @ref sl_bt_advertiser_flags - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags); - -/***************************************************************************//** - * - * Set the timing parameters for legacy or extended advertising on an - * advertising set. This setting will take effect next time the legacy or - * extended advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum advertising interval. Value in units of 0.625 ms - * - Range: 0x20 to 0xFFFFFF - * - Time range: 20 ms to 10485.759375 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum advertising interval. Value in units of 0.625 ms - * - Range: 0x20 to 0xFFFFFF - * - Time range: 20 ms to 10485.759375 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] duration @parblock - * Advertising duration for this advertising set. Value 0 indicates no - * advertising duration limit and advertising continues until it is disabled. - * A non-zero value sets the duration in units of 10 ms. The duration begins - * at the start of the first advertising event of this advertising set. - * - Range: 0x0001 to 0xFFFF - * - Time range: 10 ms to 655.35 s - * - * Default value: 0 - * @endparblock - * @param[in] maxevents @parblock - * If non-zero, indicates the maximum number of advertising events to send - * before the advertiser is stopped. Value 0 indicates no maximum number - * limit. - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, - uint32_t interval_min, - uint32_t interval_max, - uint16_t duration, - uint8_t maxevents); - -/***************************************************************************//** - * - * Set the primary advertising channel map on an advertising set. This setting - * will take effect next time when the legacy or extended advertising is - * enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] channel_map @parblock - * Advertising channel map which determines, which of the three channels will - * be used for advertising. This value is given as a bitmask. Values: - * - 1: Advertise on CH37 - * - 2: Advertise on CH38 - * - 3: Advertise on CH37 and CH38 - * - 4: Advertise on CH39 - * - 5: Advertise on CH37 and CH39 - * - 6: Advertise on CH38 and CH39 - * - 7: Advertise on all channels - * - * Recommended value: 7 - * - * Default value: 7 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, - uint8_t channel_map); - -/***************************************************************************//** - * - * Limit the maximum advertising TX power on an advertising set. If the value - * goes over the global value that was set using the @ref - * sl_bt_system_set_tx_power command, the global value will be the maximum - * limit. The maximum TX power of legacy advertising is further constrained to - * be less than +10 dBm. Extended advertising TX power can be +10 dBm and over - * if Adaptive Frequency Hopping is enabled. This setting has no effect on - * periodic advertising. - * - * This setting will take effect next time the legacy or extended advertising is - * enabled. - * - * By default, maximum advertising TX power is limited by the global value. - * - * @param[in] advertising_set Advertising set handle - * @param[in] power TX power in 0.1 dBm steps. For example, the value of 10 is 1 - * dBm and 55 is 5.5 dBm. - * @param[out] set_power The selected maximum advertising TX power - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, - int16_t power, - int16_t *set_power); - -/***************************************************************************//** - * - * Enable or disable the scan request notification on an advertising set. This - * setting will take effect next time the legacy or extended advertising is - * enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] report_scan_req @parblock - * If non-zero, enables scan request notification and scan requests will be - * reported as events. - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_scan_request - Triggered when a scan request is - * received during advertising if the scan request notification is enabled - * by this command. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, - uint8_t report_scan_req); - -/***************************************************************************//** - * - * Set the advertiser on an advertising set to use a random address. This - * overrides the default advertiser address, which is either the public device - * address programmed at production or the address written into persistent - * storage using @ref sl_bt_system_set_identity_address command. This setting is - * stored in RAM only and does not change the identity address in persistent - * storage. In privacy mode, the stack does not change an advertiser address set - * by this command. To ensure that the stack can manage the address update - * periodically in privacy mode, the address setting should be removed with the - * @ref sl_bt_advertiser_clear_random_address command. - * - * When setting a resolvable random address, the address parameter is ignored. - * The stack generates one and set it as the advertiser address. The generated - * address is returned in the response. To enhance the privacy, the application - * should schedule periodic address updates by calling this command - * periodically. Use different schedules for different advertising sets. - * - * To use the default advertiser address, remove this setting using @ref - * sl_bt_advertiser_clear_random_address command. - * - * Wrong state error is returned if advertising has been enabled on the - * advertising set. Invalid parameter error is returned if the advertising set - * handle is invalid or the address does not conform to the Bluetooth - * specification. - * - * @param[in] advertising_set Advertising set handle - * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. Address type. - * Values: - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address. This type can only be used for non-connectable - * advertising. - * @param[in] address The random address to set. Ignore this field when setting - * a resolvable random address. - * @param[out] address_out The resolvable random address set for the advertiser. - * Ignore this field when setting other types of random addresses. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, - uint8_t addr_type, - bd_addr address, - bd_addr *address_out); - -/***************************************************************************//** - * - * Clear the random address previously set for the advertiser address on an - * advertising set. To set a random address, use @ref - * sl_bt_advertiser_set_random_address command. The default advertiser address - * will be used after this operation. - * - * The error SL_STATUS_INVALID_STATE is returned if advertising has been enabled - * on the advertising set. An invalid parameter error is returned if the - * advertising set handle is invalid. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set); - -/***************************************************************************//** - * - * Stop the legacy or extended advertising on an advertising set. Counterpart - * with @ref sl_bt_legacy_advertiser_start or @ref - * sl_bt_extended_advertiser_start. - * - * This command does not affect the enable state of the periodic advertising on - * the advertising set, i.e., periodic advertising is not stopped. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set); - -/***************************************************************************//** - * - * Delete an advertising set. Any enabled legacy, extended, or periodic - * advertising is stopped before the deletion. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_extended_advertiser_set_phy. - * - * Set the primary and secondary advertising PHYs used for extended and periodic - * advertising on an advertising set. This setting will take effect next time - * extended or periodic advertising is enabled. When advertising on the LE Coded - * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is - * returned if a PHY value is invalid or the device does not support a given - * PHY. - * - * @param[in] advertising_set Advertising set handle - * @param[in] primary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the primary advertising channel. If legacy advertising PDUs - * are used, 1M PHY must be used. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * @param[in] secondary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the secondary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_advertiser_configure command. - * - * Enable advertising configuration flags on an advertising set. The - * configuration change will take effect next time the legacy or extended - * advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] configurations @parblock - * Advertising configuration flags to enable. This value can be a bitmask of - * multiple flags. Flags: - * - 1 (Bit 0): Use legacy advertising PDUs. - * - 2 (Bit 1): Omit advertiser's address from all PDUs (anonymous - * advertising). This flag is effective only in extended advertising. - * - 4 (Bit 2): Use a non-resolvable private address. When this - * configuration is enabled, the advertising must use non-connectable - * mode. The stack generates a non-resolvable private address for the - * advertising set and the stack will update the address periodically when - * the privacy mode is enabled. This configuration is ignored if the - * advertiser address has been set with the @ref - * sl_bt_advertiser_set_random_address command. - * - 8 (Bit 3): Include TX power in advertising packets. This flag is - * effective only in extended advertising. - * - 16 (Bit 4): Use the device identity address when the privacy - * mode is enabled in the stack. This configuration is ignored if the - * configuration of using non-resolvable private address is enabled or the - * advertising address has been set with the @ref - * sl_bt_advertiser_set_random_address command. - * - * Default value: 1 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, - uint32_t configurations); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_advertiser_configure command. - * - * Disable advertising configuration flags on an advertising set. The - * configuration change will take effect next time the legacy or extended - * advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] configurations Advertising configuration flags to disable. This - * value can be a bitmask of multiple flags. See @ref - * sl_bt_advertiser_set_configuration for possible flags. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, - uint32_t configurations); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_legacy_advertiser_set_data for - * legacy advertising PDUs, @ref sl_bt_extended_advertiser_set_data for extended - * advertising PDUs, and @ref sl_bt_periodic_advertiser_set_data for periodic - * advertising PDUs. - * - * Set user-defined data in advertising packets, scan response packets, or - * periodic advertising packets. Maximum 31 bytes of data can be set for legacy - * advertising. Maximum 191 bytes of data can be set for connectable extended - * advertising. Maximum 253 bytes of data can be set for periodic and - * non-connectable extended advertising. For setting longer advertising data, - * use command @ref sl_bt_advertiser_set_long_data. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_advertiser_start. Periodic advertising mode can be enabled using - * command @ref sl_bt_advertiser_start_periodic_advertising. - * - * The invalid parameter error will be returned in the following situations: - * - Data length is more than 31 bytes but the advertiser can only advertise - * using legacy advertising PDUs. - * - Data is too long to fit into a single advertisement. - * - Set data of the advertising data packet when the scannable advertising is - * enabled using extended advertising PDUs. - * - Set data of the scan response data packet when the connectable - * advertising is enabled using extended advertising PDUs. - * - * Note that the user-defined data may be overwritten by the system when the - * advertising is later enabled in a discovery mode other than user_data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] packet_type This value selects whether data is intended for - * advertising packets, scan response packets, or periodic advertising - * packets. - * - 0: Advertising packets - * - 1: Scan response packets - * - 8: Periodic advertising packets - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, - uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_extended_advertiser_set_long_data for extended advertising PDUs and - * @ref sl_bt_periodic_advertiser_set_long_data for periodic advertising PDUs. - * - * Set advertising data for a specified packet type and advertising set. Data - * currently in the system data buffer will be extracted as the advertising - * data. The buffer will be emptied after this command regardless of the - * completion status. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. - * - * Maximum 31 bytes of data can be set for legacy advertising. Maximum 191 bytes - * of data can be set for connectable extended advertising. Maximum 1650 bytes - * of data can be set for periodic and non-connectable extended advertising, but - * advertising parameters may limit the amount of data that can be sent in a - * single advertisement. - * - * See @ref sl_bt_advertiser_set_data for more details on advertising data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] packet_type This value selects whether data is intended for - * advertising packets, scan response packets, or periodic advertising - * packets. Values: - * - 0: Advertising packets - * - 1: Scan response packets - * - 8: Periodic advertising packets - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, - uint8_t packet_type); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_legacy_advertiser_start and @ref - * sl_bt_extended_advertiser_start commands. - * - * Start the legacy or extended advertising on an advertising set with specified - * discovery and connection modes. - * - * The number of concurrent connectable advertisings is limited by the number of - * connections reserved by the user application (the - * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other - * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This - * command fails with the connection limit exceeded error if it may cause the - * number of connections exceeding the configured value in future. For example, - * only one connectable advertising can be enabled if the device has - * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. - * This limitation does not apply to non-connectable advertising. - * - * The default advertising configuration in the stack is set to using legacy - * advertising PDUs on 1M PHY. The stack will automatically select extended - * advertising PDUs if either of the following has occurred with the default - * configuration: - * 1. The connection mode is set to @ref - * sl_bt_advertiser_connectable_non_scannable. - * 2. The primary advertising PHY is set to Coded PHY by @ref - * sl_bt_extended_advertiser_set_phy. - * 3. The user advertising data length is more than 31 bytes. - * 4. Periodic advertising is enabled. - * - * This command fails with the invalid parameter error if one of the following - * cases occurs: - * 1. Non-resolvable random address is used but the connection mode is - * advertiser_connectable_scannable or - * advertiser_connectable_non_scannable. - * 2. advertiser_connectable_non_scannable is the connection mode but using - * legacy advertising PDUs has been explicitly enabled with command @ref - * sl_bt_advertiser_set_configuration. - * 3. Coded PHY is the primary advertising PHY but using legacy advertising - * PDUs has been explicitly enabled with command @ref - * sl_bt_advertiser_set_configuration. - * 4. advertiser_connectable_scannable is the connection mode but using - * extended advertising PDUs has been explicitly enabled or the primary - * advertising PHY is set to Coded PHY. - * - * If advertising is enabled in user_data mode, use @ref - * sl_bt_advertiser_set_data to set advertising and scan response data before - * issuing this command. When advertising is enabled in modes other than - * user_data, advertising and scan response data is generated by the stack using - * the following procedure: - * 1. Add a flags field to advertising data. - * 2. Add a TX power level field to advertising data if the TX power service - * exists in the local GATT database. - * 3. Add a peripheral connection interval range field to advertising data if - * the GAP peripheral preferred connection parameters characteristic exists - * in the local GATT database. - * 4. Add a list of 16-bit service UUIDs to advertising data if there are one - * or more 16-bit service UUIDs to advertise. The list is complete if all - * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is - * incomplete. - * 5. Add a list of 128-bit service UUIDs to advertising data if there are one - * or more 128-bit service UUIDs to advertise and there is still free space - * for this field. The list is complete if all advertised 128-bit UUIDs are - * in advertising data. Otherwise, the list is incomplete. Note that an - * advertising data packet can contain at most one 128-bit service UUID. - * 6. Try to add the full local name to advertising data if the device is not - * in privacy mode. If the full local name does not fit into the remaining - * free space, the advertised name is a shortened version by cutting off - * the end if the free space has at least 6 bytes. Otherwise, the local - * name is added to scan response data. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. Discovery - * mode. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - sl_bt_advertiser_broadcast (0x3): Device is not discoverable in - * either limited or generic discovery procedure but may be discovered - * using the Observation procedure. - * - sl_bt_advertiser_user_data (0x4): Send advertising and/or scan - * response data defined by the user. The discovery mode is defined by the - * user. - * @param[in] connect Enum @ref sl_bt_advertiser_connection_mode_t. Connection - * mode. Values: - * - sl_bt_advertiser_non_connectable (0x0): Non-connectable - * non-scannable - * - sl_bt_advertiser_connectable_scannable (0x2): Undirected - * connectable scannable. This mode can only be used in legacy advertising - * PDUs. - * - sl_bt_advertiser_scannable_non_connectable (0x3): Undirected - * scannable (Non-connectable but responds to scan requests) - * - sl_bt_advertiser_connectable_non_scannable (0x4): Undirected - * connectable non-scannable. This mode can only be used in extended - * advertising PDUs. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and advertising has stopped on an advertising set. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, - uint8_t discover, - uint8_t connect); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_periodic_advertiser_start - * command. - * - * Start periodic advertising on an advertising set. The stack enables the - * advertising set automatically if the set was not enabled and the set can - * advertise using extended advertising PDUs beside the syncInfo, which is - * needed for the periodic advertising. - * - * The invalid parameter error is returned if the application has configured - * legacy advertising PDUs or anonymous advertising, or the advertising set is - * enabled using legacy advertising PDUs. - * - * To stop periodic advertising, use @ref - * sl_bt_advertiser_stop_periodic_advertising command with the handle received - * in response from this command. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Periodic advertising configurations. Bitmask of the - * following: - * - Bit 0: Include TX power in advertising PDU - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_periodic_advertiser_stop - * command. - * - * Stop periodic advertising on an advertising set. Counterpart with @ref - * sl_bt_advertiser_start_periodic_advertising. - * - * This command does not affect the enable state of the advertising set, i.e., - * legacy or extended advertising is not stopped. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_advertiser - -/** - * @addtogroup sl_bt_legacy_advertiser Legacy Advertiser - * @{ - * - * @brief Legacy Advertiser - * - * The commands and events in this class are related to legacy advertising - * functionalities. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_legacy_advertiser_set_data_id 0x00560020 -#define sl_bt_cmd_legacy_advertiser_generate_data_id 0x01560020 -#define sl_bt_cmd_legacy_advertiser_start_id 0x02560020 -#define sl_bt_cmd_legacy_advertiser_start_directed_id 0x03560020 -#define sl_bt_rsp_legacy_advertiser_set_data_id 0x00560020 -#define sl_bt_rsp_legacy_advertiser_generate_data_id 0x01560020 -#define sl_bt_rsp_legacy_advertiser_start_id 0x02560020 -#define sl_bt_rsp_legacy_advertiser_start_directed_id 0x03560020 - -/** - * @brief These values define the available connection modes of undirected - * legacy advertising. - */ -typedef enum -{ - sl_bt_legacy_advertiser_non_connectable = 0x0, /**< (0x0) Undirected - non-connectable and - non-scannable legacy - advertising */ - sl_bt_legacy_advertiser_connectable = 0x2, /**< (0x2) Undirected - connectable and scannable - legacy advertising */ - sl_bt_legacy_advertiser_scannable = 0x3 /**< (0x3) Undirected scannable - and non-connectable legacy - advertising */ -} sl_bt_legacy_advertiser_connection_mode_t; - -/** - * @brief These values define the available connection modes of directed legacy - * advertising. - */ -typedef enum -{ - sl_bt_legacy_advertiser_high_duty_directed_connectable = 0x1, /**< (0x1) High - duty cycle - directed - connectable - legacy - advertising */ - sl_bt_legacy_advertiser_low_duty_directed_connectable = 0x5 /**< (0x5) Low - duty cycle - directed - connectable - legacy - advertising */ -} sl_bt_legacy_advertiser_directed_connection_mode_t; - -/***************************************************************************//** - * - * Set user-defined advertising data packet or scan response packet on an - * advertising set. This overwrites the existing advertising data packet and - * scan response packet on this advertising set regardless of whether the data - * was set for the legacy or extended advertising. Maximum 31 bytes of data can - * be set with this command. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_legacy_advertiser_start. - * - * @param[in] advertising_set Advertising set handle - * @param[in] type Enum @ref sl_bt_advertiser_packet_type_t. The advertising - * packet type - * @param[in] data_len Length of data in @p data - * @param[in] data Data to set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Ask the stack to generate the advertising data packet and scan response - * packet on an advertising set. Alternatively, the user-defined advertising - * data can be set using the @ref sl_bt_legacy_advertiser_set_data command. - * - * This overwrites the existing advertising data packet and scan response packet - * on this advertising set regardless of whether the data was set for the legacy - * or extended advertising. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. To enable advertising mode, use command @ref - * sl_bt_legacy_advertiser_start. - * - * The stack generates the advertising data and scan response packet using the - * following logic. - * 1. Add a flags field to advertising data. - * 2. Add a TX power level field to advertising data if the TX power service - * exists in the local GATT database. - * 3. Add a peripheral connection interval range field to advertising data if - * the GAP peripheral preferred connection parameters characteristic exists - * in the local GATT database. - * 4. Add a list of 16-bit service UUIDs to advertising data if there are one - * or more 16-bit service UUIDs to advertise. The list is complete if all - * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is - * incomplete. - * 5. Add a list of 128-bit service UUIDs to advertising data if there are one - * or more 128-bit service UUIDs to advertise and there is still free space - * for this field. The list is complete if all advertised 128-bit UUIDs are - * in advertising data. Otherwise, the list is incomplete. Note that an - * advertising data packet can contain at most one 128-bit service UUID. - * 6. Try to add the full local name to advertising data if the device is not - * in privacy mode. If the full local name does not fit into the remaining - * free space, the advertised name is a shortened version by cutting off - * the end if the free space has at least 6 bytes. Otherwise, the local - * name is added to scan response data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The - * discovery mode for the Flags data field in the packet. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover); - -/***************************************************************************//** - * - * Start undirected legacy advertising on an advertising set with the specified - * connection mode. Use @ref sl_bt_advertiser_stop to stop the advertising. - * - * Use the @ref sl_bt_legacy_advertiser_set_data or @ref - * sl_bt_legacy_advertiser_generate_data command to set the advertising data - * before calling this command. The advertising data is added into the - * advertising data packet and scan response packet if the connection mode is - * connectable and/or scannable. The data is only added into the advertising - * data packet when the connection mode is non-connectable and non-scannable. - * - * The number of concurrent connectable advertisings is limited by the number of - * connections reserved by the user application (the - * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other - * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This - * command fails with the connection limit exceeded error if it may cause the - * number of connections exceeding the configured value in future. For example, - * only one connectable advertising can be enabled if the device has - * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. - * This limitation does not apply to non-connectable advertising. - * - * This command fails with the invalid parameter error if non-resolvable random - * address is used but the connection mode is @ref - * sl_bt_legacy_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_legacy_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_legacy_advertiser_non_connectable (0x0): Undirected - * non-connectable and non-scannable legacy advertising - * - sl_bt_legacy_advertiser_connectable (0x2): Undirected - * connectable and scannable legacy advertising - * - sl_bt_legacy_advertiser_scannable (0x3): Undirected scannable - * and non-connectable legacy advertising - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, - uint8_t connect); - -/***************************************************************************//** - * - * Start directed legacy advertising on an advertising set with the specified - * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to - * stop the advertising. - * - * Directed legacy advertising does not allow any advertising data. When the - * connection mode is @ref - * sl_bt_legacy_advertiser_high_duty_directed_connectable, the stack defaults - * the advertising duration to 0.64 s if the application has not set the - * parameter. The duration is reduced to 1.28 s if the application has set a - * larger duration value. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if non-resolvable random - * address is set as the advertising address. - * - * Event @ref sl_bt_evt_connection_opened will be received when the target - * device opens a connection to the advertiser on this advertising set. As a - * result, the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising - * stops and no Bluetooth connection is opened to it. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref - * sl_bt_legacy_advertiser_directed_connection_mode_t. Connection mode. - * Values: - * - sl_bt_legacy_advertiser_high_duty_directed_connectable (0x1): - * High duty cycle directed connectable legacy advertising - * - sl_bt_legacy_advertiser_low_duty_directed_connectable (0x5): Low - * duty cycle directed connectable legacy advertising - * @param[in] peer_addr Address of the peer target device the advertising is - * directed to - * @param[in] peer_addr_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Peer target device address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - bd_addr peer_addr, - uint8_t peer_addr_type); - -/** @} */ // end addtogroup sl_bt_legacy_advertiser - -/** - * @addtogroup sl_bt_extended_advertiser Extended Advertiser - * @{ - * - * @brief Extended Advertiser - * - * The commands and events in this class are related to extended advertising - * functionalities in GAP peripheral and broadcaster roles. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_extended_advertiser_set_phy_id 0x00570020 -#define sl_bt_cmd_extended_advertiser_set_data_id 0x01570020 -#define sl_bt_cmd_extended_advertiser_set_long_data_id 0x02570020 -#define sl_bt_cmd_extended_advertiser_generate_data_id 0x03570020 -#define sl_bt_cmd_extended_advertiser_start_id 0x04570020 -#define sl_bt_cmd_extended_advertiser_start_directed_id 0x05570020 -#define sl_bt_rsp_extended_advertiser_set_phy_id 0x00570020 -#define sl_bt_rsp_extended_advertiser_set_data_id 0x01570020 -#define sl_bt_rsp_extended_advertiser_set_long_data_id 0x02570020 -#define sl_bt_rsp_extended_advertiser_generate_data_id 0x03570020 -#define sl_bt_rsp_extended_advertiser_start_id 0x04570020 -#define sl_bt_rsp_extended_advertiser_start_directed_id 0x05570020 - -/** - * @brief These values define the available connection modes in extended - * advertising. - */ -typedef enum -{ - sl_bt_extended_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable - and non-scannable - extended advertising */ - sl_bt_extended_advertiser_scannable = 0x3, /**< (0x3) Scannable extended - advertising */ - sl_bt_extended_advertiser_connectable = 0x4 /**< (0x4) Connectable - extended advertising */ -} sl_bt_extended_advertiser_connection_mode_t; - -/** - * @addtogroup sl_bt_extended_advertiser_flags Extended Advertising Configuration Flags - * @{ - * - * This enum defines configuration flags for the extended advertising. - */ - -/** Omit advertiser's address from all PDUs (anonymous advertising). The - * advertising cannot be connectable or scannable if this flag is set. */ -#define SL_BT_EXTENDED_ADVERTISER_ANONYMOUS_ADVERTISING 0x1 - -/** Include the TX power in advertising packets. */ -#define SL_BT_EXTENDED_ADVERTISER_INCLUDE_TX_POWER 0x2 - -/** @} */ // end Extended Advertising Configuration Flags - -/***************************************************************************//** - * - * Set the primary and secondary advertising PHYs used for extended and periodic - * advertising on an advertising set. This setting will take effect next time - * extended or periodic advertising is enabled. When advertising on the LE Coded - * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is - * returned if a PHY value is invalid or the device does not support a given - * PHY. - * - * @param[in] advertising_set Advertising set handle - * @param[in] primary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the primary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * @param[in] secondary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the secondary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy); - -/***************************************************************************//** - * - * Set user-defined data for extended advertising. This overwrites the existing - * advertising data packet and scan response packet on this advertising set - * regardless of whether the data was set for the legacy or extended - * advertising. Maximum 191 bytes of data can be set for connectable extended - * advertising. Maximum 253 bytes of data can be set for non-connectable - * extended advertising. For setting longer advertising data, use command @ref - * sl_bt_extended_advertiser_set_long_data. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_extended_advertiser_start. - * - * The invalid parameter error is returned if the data is too long to fit into a - * single advertisement. - * - * @param[in] advertising_set Advertising set handle - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set long user-defined data for extended advertising. This overwrites the - * existing advertising data packet and scan response packet on this advertising - * set regardless of whether the data was set for the legacy or extended - * advertising. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. When this command is called, - * the data in the system data buffer is extracted as the advertising data. The - * buffer will be emptied after this command regardless of the completion - * status. - * - * Maximum 191 bytes of data can be set for connectable extended advertising. - * Maximum 1650 bytes of data can be set for non-connectable extended - * advertising. Advertising parameters may limit the amount of data that can be - * sent in a single advertisement. See @ref sl_bt_extended_advertiser_set_data - * for more details. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set); - -/***************************************************************************//** - * - * Ask the stack to generate the extended advertising data on an advertising - * set. Alternatively, user-defined advertising data can be set using the @ref - * sl_bt_extended_advertiser_set_data command. - * - * This overwrites the existing advertising data packet and scan response packet - * on this advertising set regardless of whether the data was set for the legacy - * or extended advertising. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. To enable advertising mode, use command @ref - * sl_bt_extended_advertiser_start. - * - * See @ref sl_bt_legacy_advertiser_generate_data for the advertising data - * generation logic. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The - * discovery mode for the Flags data field in the packet. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover); - -/***************************************************************************//** - * - * Start undirected extended advertising on an advertising set with the - * specified connection mode. Use @ref sl_bt_advertiser_stop to stop the - * advertising. - * - * Use the @ref sl_bt_extended_advertiser_set_data or @ref - * sl_bt_extended_advertiser_generate_data command to set the advertising data - * before calling this command. Advertising data is added into the scan response - * packet if the connection mode is scannable. Otherwise, data is in the - * advertising data packet. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if the advertising uses a - * non-resolvable random address but the connection mode is @ref - * sl_bt_extended_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable - * and non-scannable extended advertising - * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended - * advertising - * - sl_bt_extended_advertiser_connectable (0x4): Connectable - * extended advertising - * @param[in] flags Additional extended advertising options. Value: 0 or bitmask - * of @ref sl_bt_extended_advertiser_flags - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and advertising has stopped on an advertising set. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, - uint8_t connect, - uint32_t flags); - -/***************************************************************************//** - * - * Start directed extended advertising on an advertising set with the specified - * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to - * stop the advertising. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if the advertising uses a - * non-resolvable random address but the connection mode is @ref - * sl_bt_extended_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when the target - * device opens a connection to the advertiser on this advertising set. As a - * result, the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising - * stops and no Bluetooth connection is opened to it. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable - * and non-scannable extended advertising - * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended - * advertising - * - sl_bt_extended_advertiser_connectable (0x4): Connectable - * extended advertising - * @param[in] flags Additional extended advertising options. Value: 0 or bitmask - * of @ref sl_bt_extended_advertiser_flags - * @param[in] peer_addr Address of the peer target device the advertising is - * directed to - * @param[in] peer_addr_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Peer target device address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - uint32_t flags, - bd_addr peer_addr, - uint8_t peer_addr_type); - -/** @} */ // end addtogroup sl_bt_extended_advertiser - -/** - * @addtogroup sl_bt_periodic_advertiser Periodic Advertiser - * @{ - * - * @brief Periodic Advertiser - * - * Provides support for advertising with periodic advertising trains that do not - * have subevents or response slots. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_periodic_advertiser_set_data_id 0x00580020 -#define sl_bt_cmd_periodic_advertiser_set_long_data_id 0x01580020 -#define sl_bt_cmd_periodic_advertiser_start_id 0x02580020 -#define sl_bt_cmd_periodic_advertiser_stop_id 0x03580020 -#define sl_bt_rsp_periodic_advertiser_set_data_id 0x00580020 -#define sl_bt_rsp_periodic_advertiser_set_long_data_id 0x01580020 -#define sl_bt_rsp_periodic_advertiser_start_id 0x02580020 -#define sl_bt_rsp_periodic_advertiser_stop_id 0x03580020 - -/** - * @addtogroup sl_bt_periodic_advertiser_flags Periodic Advertising Configuration Flags - * @{ - * - * Defines configuration flags for periodic advertising. - */ - -/** Include the TX power in advertising packets. */ -#define SL_BT_PERIODIC_ADVERTISER_INCLUDE_TX_POWER 0x1 - -/** Automatically start the extended advertising on the advertising set. The - * advertising will be started in non-connectable and non-scannable mode. */ -#define SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING 0x2 - -/** @} */ // end Periodic Advertising Configuration Flags - -/** - * @cond RESTRICTED - * - * @addtogroup sl_bt_evt_periodic_advertiser_status sl_bt_evt_periodic_advertiser_status - * @{ - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * @brief This event indicates a status update in the periodic advertising. - */ - -/** @brief Identifier of the status event */ -#define sl_bt_evt_periodic_advertiser_status_id 0x005800a0 - -/***************************************************************************//** - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * @brief Data structure of the status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_advertiser_status_s -{ - uint8_t advertising_set; /**< The advertising set handle */ - uint32_t status; /**< Reserved for future */ -}); - -typedef struct sl_bt_evt_periodic_advertiser_status_s sl_bt_evt_periodic_advertiser_status_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_advertiser_status -/** @endcond */ // end restricted event - -/***************************************************************************//** - * - * Set the data for periodic advertising on an advertising set. Maximum 254 - * bytes of data can be set with this command. For setting longer advertising - * data, use command @ref sl_bt_periodic_advertiser_set_long_data. - * - * If the periodic advertising is currently enabled, the new advertising data - * will be used immediately. Periodic advertising can be enabled using the - * command @ref sl_bt_periodic_advertiser_start. - * - * The invalid parameter error will be returned if the data is too long to fit - * into the advertisement. - * - * @param[in] advertising_set Advertising set handle - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set data for periodic advertising on an advertising set. Data currently in - * the system data buffer will be extracted as the advertising data. The buffer - * will be emptied after this command regardless of the completion status. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. - * - * Maximum 1650 bytes of data can be set for periodic advertising. Advertising - * parameters may limit the amount of data that can be sent. - * - * See @ref sl_bt_periodic_advertiser_set_data for more details. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set); - -/***************************************************************************//** - * - * Start periodic advertising on an advertising set. - * - * According to the Bluetooth Core specification, periodic advertising PDUs - * cannot be transmitted until at least one extended advertising event has been - * completed. If the application needs exact control over the extended - * advertising data and parameters, use the @ref sl_bt_advertiser class to - * configure the parameters of the advertising set and the @ref - * sl_bt_extended_advertiser class to set or generate the desired extended - * advertising data payload. If the application does not configure the - * parameters or set the data, the default parameters and empty advertising data - * are used for the extended advertising. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p - * flags, the stack will automatically start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. The application may stop the automatically started extended - * advertising using the @ref sl_bt_advertiser_stop command. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in - * @p flags, the stack will momentarily start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. Unless the application starts extended advertising before - * the first extended advertising event has completed, the stack will - * automatically stop the momentary extended advertising after the first - * extended advertising event. - * - * Periodic advertising PDUs are transmitted on the secondary PHY configured for - * the advertising set with the @ref sl_bt_extended_advertiser_set_phy command. - * - * Use @ref sl_bt_periodic_advertiser_stop command to stop the periodic - * advertising. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask - * of @ref sl_bt_periodic_advertiser_flags - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags); - -/***************************************************************************//** - * - * Stop the periodic advertising on an advertising set. Counterpart to @ref - * sl_bt_periodic_advertiser_start. - * - * This command does not affect the enable state of the legacy or extended - * advertising on the advertising set, i.e., the legacy or extended advertising - * is not stopped.. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_periodic_advertiser - -/** - * @addtogroup sl_bt_scanner Scanner - * @{ - * - * @brief Scanner - * - * This is the scanning feature that is brought in when the application includes - * a software component for the scanning functionality. The functionality - * differences are listed below for various component inclusion scenario: - * - The bluetooth_feature_scanner component is included but neither - * bluetooth_feature_legacy_scanner nor bluetooth_feature_extended_scanner - * is included: - * - The scanner can scan advertising devices that use legacy or extended - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_scan_report event is used to report the - * received advertisements. - * - * - The bluetooth_feature_legacy_scanner component is included but the - * bluetooth_feature_extended_scanner is not: - * - The scanner can only scan advertising devices that use legacy - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used - * to report the received advertisements. - * - * - The bluetooth_feature_extended_scanner component is included: - * - The scanner can scan advertising devices that use legacy or extended - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used - * to report the received advertisements that use legacy advertising - * PDUs, and the @ref sl_bt_evt_scanner_extended_advertisement_report - * event is used to report the received advertisements that use extended - * advertising PDUs. - * - * - Either the bluetooth_feature_legacy_scanner or - * bluetooth_feature_extended_scanner component is included: - * - The @ref sl_bt_scanner_set_timing and @ref sl_bt_scanner_set_mode - * commands are not available to use. They are superseded by the @ref - * sl_bt_scanner_set_parameters command. - * - Calling a superseded command receives SL_STATUS_NOT_SUPPORTED error - * code. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_scanner_set_parameters_id 0x06050020 -#define sl_bt_cmd_scanner_set_parameters_and_filter_id 0x07050020 -#define sl_bt_cmd_scanner_stop_id 0x05050020 -#define sl_bt_cmd_scanner_set_timing_id 0x01050020 -#define sl_bt_cmd_scanner_set_mode_id 0x02050020 -#define sl_bt_cmd_scanner_start_id 0x03050020 -#define sl_bt_rsp_scanner_set_parameters_id 0x06050020 -#define sl_bt_rsp_scanner_set_parameters_and_filter_id 0x07050020 -#define sl_bt_rsp_scanner_stop_id 0x05050020 -#define sl_bt_rsp_scanner_set_timing_id 0x01050020 -#define sl_bt_rsp_scanner_set_mode_id 0x02050020 -#define sl_bt_rsp_scanner_start_id 0x03050020 - -/** - * @brief These values indicate which Bluetooth discovery mode to use when - * scanning for advertising devices. - */ -typedef enum -{ - sl_bt_scanner_discover_limited = 0x0, /**< (0x0) Discover only limited - discoverable devices. */ - sl_bt_scanner_discover_generic = 0x1, /**< (0x1) Discover limited and - general discoverable devices. */ - sl_bt_scanner_discover_observation = 0x2 /**< (0x2) Discover - non-discoverable, limited and - general discoverable devices. */ -} sl_bt_scanner_discover_mode_t; - -/** - * @brief The scanning modes. - */ -typedef enum -{ - sl_bt_scanner_scan_mode_passive = 0x0, /**< (0x0) Passive scanning mode where - the device only listens to - advertising packets and does not - transmit packets */ - sl_bt_scanner_scan_mode_active = 0x1 /**< (0x1) Active scanning mode where - the device sends out a scan - request packet upon receiving a - scannable advertising packet from - a remote device and listens to the - scan response packet from the - remote device */ -} sl_bt_scanner_scan_mode_t; - -/** - * @brief The enum defines the scanning PHYs. - */ -typedef enum -{ - sl_bt_scanner_scan_phy_1m = 0x1, /**< (0x1) Initiate the scanning on - the 1M PHY */ - sl_bt_scanner_scan_phy_coded = 0x4, /**< (0x4) Initiate the scanning on - the Coded PHY */ - sl_bt_scanner_scan_phy_1m_and_coded = 0x5 /**< (0x5) Simultaneous scanning by - initiating the scanning on the - 1M and Coded PHY alternatively */ -} sl_bt_scanner_scan_phy_t; - -/** - * @brief Defines the data completeness status types of an advertisement - * reported by the scanner. - */ -typedef enum -{ - sl_bt_scanner_data_status_complete = 0x0, /**< (0x0) All data of the - advertisement has been - reported. */ - sl_bt_scanner_data_status_incomplete_more = 0x1, /**< (0x1) Data of the - advertisement is - incomplete in this - event, and more data - will come in new - events. */ - sl_bt_scanner_data_status_incomplete_nomore = 0x2 /**< (0x2) Data of the - advertisement is - incomplete in this - event, but no more - data will come, i.e., - the data of the - advertisement is - truncated. */ -} sl_bt_scanner_data_status_t; - -/** - * @brief The scanning filter policy setting determines which advertisements and - * scan responses are delivered to the application when scanning. See the - * Bluetooth Core specification Volume 6, Part B, Section 4.3.3 "Scanning filter - * policy" for a detailed description of this setting. - * - * Note that some filter policies require the application to include additional - * Bluetooth feature components. Filter policies that use the Filter Accept List - * require that the application has included the bluetooth_feature_accept_list - * component. Filter policies that require the Bluetooth controller to resolve a - * Resolvable Private Address require that the application has included the - * bluetooth_feature_resolving_list component. - */ -typedef enum -{ - sl_bt_scanner_filter_policy_basic_unfiltered = 0x0, /**< (0x0) Advertising - and scan response - PDUs are processed - from all devices. - For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - a Resolvable - Private Address - that is resolved - to the local - device by the - Bluetooth - controller. */ - sl_bt_scanner_filter_policy_basic_filtered = 0x1, /**< (0x1) Advertising - and scan response - PDUs are processed - only from devices - that the - application has - added to the - Filter Accept - List. For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - a Resolvable - Private Address - that is resolved - to the local - device by the - Bluetooth - controller. */ - sl_bt_scanner_filter_policy_extended_unfiltered = 0x2, /**< (0x2) Advertising - and scan response - PDUs are processed - from all devices. - For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - any Resolvable - Private Address. */ - sl_bt_scanner_filter_policy_extended_filtered = 0x3 /**< (0x3) Advertising - and scan response - PDUs are processed - only from devices - that the - application has - added to the - Filter Accept - List. For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - any Resolvable - Private Address. */ -} sl_bt_scanner_filter_policy_t; - -/** - * @addtogroup sl_bt_scanner_event_flag Event Type Flags of Advertisement Reports - * @{ - * - * Defines the event type flags of the advertisement packets the scanner - * reports. An advertisement packet could have multiple applicable flags. - */ - -/** A connectable advertising data packet */ -#define SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE 0x1 - -/** A scannable advertising data packet */ -#define SL_BT_SCANNER_EVENT_FLAG_SCANNABLE 0x2 - -/** Directed advertising */ -#define SL_BT_SCANNER_EVENT_FLAG_DIRECTED 0x4 - -/** A scan response packet that can be received in active scan mode only */ -#define SL_BT_SCANNER_EVENT_FLAG_SCAN_RESPONSE 0x8 - -/** @} */ // end Event Type Flags of Advertisement Reports - -/** - * @addtogroup sl_bt_evt_scanner_legacy_advertisement_report sl_bt_evt_scanner_legacy_advertisement_report - * @{ - * @brief Reports an advertising data or scan response packet from an - * advertising device that uses legacy advertising PDUs. - * - * This event is used to report advertisements only if the application includes - * the bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component - * - * Otherwise, the @ref sl_bt_evt_scanner_scan_report event is used for - * maintaining the backwards compatibility. - */ - -/** @brief Identifier of the legacy_advertisement_report event */ -#define sl_bt_evt_scanner_legacy_advertisement_report_id 0x000500a0 - -/***************************************************************************//** - * @brief Data structure of the legacy_advertisement_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_legacy_advertisement_report_s -{ - uint8_t event_flags; /**< The event type flag(s) in the - advertisement packet. Value: One or more - flags defined in @ref - sl_bt_scanner_event_flag */ - bd_addr address; /**< Advertiser address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the - local device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last - packet was received */ - bd_addr target_address; /**< The target address if the advertisement - is from directed advertising, otherwise - ignored */ - uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - The target address type if the - advertisement is from directed - advertising, otherwise ignored. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - the following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - enum @ref sl_bt_gap_address_type_t - values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8array data; /**< Advertising or scan response data. Ignore - if this is directed advertising. */ -}); - -typedef struct sl_bt_evt_scanner_legacy_advertisement_report_s sl_bt_evt_scanner_legacy_advertisement_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_legacy_advertisement_report - -/** - * @addtogroup sl_bt_evt_scanner_extended_advertisement_report sl_bt_evt_scanner_extended_advertisement_report - * @{ - * @brief Reports an advertising or scan response packet from an advertising - * device that uses extended advertising PDUs - * - * Multiple events may be reported for single advertisement train. - * - * This event is used to report advertisements only if the application includes - * the bluetooth_feature_extended_scanner component. Otherwise, the @ref - * sl_bt_evt_scanner_scan_report event is used for maintaining the backwards - * compatibility. - */ - -/** @brief Identifier of the extended_advertisement_report event */ -#define sl_bt_evt_scanner_extended_advertisement_report_id 0x020500a0 - -/***************************************************************************//** - * @brief Data structure of the extended_advertisement_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_extended_advertisement_report_s -{ - uint8_t event_flags; /**< The event type flag(s) in the - advertisement packet. Value: One or more - flags defined in @ref - sl_bt_scanner_event_flag */ - bd_addr address; /**< Advertiser address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the - local device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last - packet was received */ - bd_addr target_address; /**< The target address if this is directed - advertising, otherwise ignored */ - uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - The target address type if the - advertisement is from directed - advertising, otherwise ignored. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - the following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - enum @ref sl_bt_gap_address_type_t - values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_sid; /**< Advertising set identifier */ - uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on - which advertising packets are transmitted - on the primary advertising channel - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on - which advertising packets are transmitted - on the secondary advertising channel - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - int8_t tx_power; /**< TX power value in the received packet - header. Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - uint16_t periodic_interval; /**< The periodic advertising interval. Value - 0 indicates no periodic advertising. - Otherwise, - - Range: 0x06 to 0xFFFF - - Unit: 1.25 ms - - Time range: 7.5 ms to 81.92 s */ - uint8_t data_completeness; /**< Enum @ref sl_bt_scanner_data_status_t. - The data completeness status. Values: - - sl_bt_scanner_data_status_complete - (0x0): All data of the - advertisement has been reported. - - sl_bt_scanner_data_status_incomplete_more - (0x1): Data of the advertisement - is incomplete in this event, and more - data will come in new events. - - sl_bt_scanner_data_status_incomplete_nomore - (0x2): Data of the advertisement - is incomplete in this event, but no - more data will come, i.e., the data - of the advertisement is truncated. */ - uint8_t counter; /**< The monotonically increasing counter as - the sequence number of the event. This - counter is specific to @ref - sl_bt_evt_scanner_extended_advertisement_report_id. - It can be used to detect if one more @ref - sl_bt_evt_scanner_extended_advertisement_report - events were dropped due to temporarily - out of resources or other reasons. Ignore - this field if event loss is not a - concern. */ - uint8array data; /**< Advertising or scan response data */ -}); - -typedef struct sl_bt_evt_scanner_extended_advertisement_report_s sl_bt_evt_scanner_extended_advertisement_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_extended_advertisement_report - -/** - * @addtogroup sl_bt_evt_scanner_scan_report sl_bt_evt_scanner_scan_report - * @{ - * @brief Deprecated and replaced by new @ref - * sl_bt_evt_scanner_legacy_advertisement_report and @ref - * sl_bt_evt_scanner_extended_advertisement_report events - * - * To use these new events, the application needs to include the - * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component. - * - * Reports an advertising or scan response packet from an advertising device - * that uses legacy or extended advertising PDUs. - */ - -/** @brief Identifier of the scan_report event */ -#define sl_bt_evt_scanner_scan_report_id 0x010500a0 - -/***************************************************************************//** - * @brief Data structure of the scan_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_scan_report_s -{ - uint8_t packet_type; /**< Bits 0..2 : advertising packet type - - 000 : Connectable scannable - undirected advertising - - 001 : Connectable undirected - advertising - - 010 : Scannable undirected - advertising - - 011 : Non-connectable - non-scannable undirected advertising - - 100 : Scan Response. Note that - this is received only if the device is - in active scan mode. - - Bits 3..4 : Reserved for future - - Bits 5..6 : data completeness - - 00: Complete - - 01: Incomplete, more data to - come in new events - - 10: Incomplete, data truncated, - no more to come - - Bit 7 : legacy or extended - advertising - - 0: Legacy advertising PDUs used - - 1: Extended advertising PDUs - used */ - bd_addr address; /**< Bluetooth address of the remote device */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the local - device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which - advertising packets are transmitted on the - primary advertising channel. Ignore this - field if the report is for a legacy - advertising PDU. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_coded (0x4): Coded - PHY, 125k (S=8) or 500k (S=2) */ - uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which - advertising packets are transmitted on the - secondary advertising channel. Ignore this - field if the report is for a legacy - advertising PDU. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded - PHY, 125k (S=8) or 500k (S=2) */ - uint8_t adv_sid; /**< Advertising set identifier */ - int8_t tx_power; /**< TX power value in the received packet - header. Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last packet - was received */ - uint16_t periodic_interval; /**< The periodic advertising interval. Value 0 - indicates no periodic advertising. - Otherwise, - - Range: 0x06 to 0xFFFF - - Unit: 1.25 ms - - Time range: 7.5 ms to 81.92 s */ - uint8array data; /**< Advertising or scan response data */ -}); - -typedef struct sl_bt_evt_scanner_scan_report_s sl_bt_evt_scanner_scan_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_scan_report - -/***************************************************************************//** - * - * Set scan parameters for subsequent scanning operations. If the device is - * currently scanning, new parameters will take effect when scanning is - * restarted. - * - * This command sets the scanning filter policy to the default value @ref - * sl_bt_scanner_filter_policy_basic_unfiltered. Use the command @ref - * sl_bt_scanner_set_parameters_and_filter to set a specific scanning filter - * policy. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * Passive or active scan. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * @param[in] interval @parblock - * The time interval when the device starts its last scan until it begins the - * subsequent scan. In other words, how often to scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] window @parblock - * The scan window, i.e., the duration of the scan, which must be less than or - * equal to the @p interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * Note that the packet reception is aborted if it's started just before the - * scan window ends. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, - uint16_t interval, - uint16_t window); - -/***************************************************************************//** - * - * Set scan parameters and the scanning filter policy for subsequent scanning - * operations. If the device is currently scanning, new parameters will take - * effect when scanning is restarted. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * Passive or active scan. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * @param[in] interval @parblock - * The time interval when the device starts its last scan until it begins the - * subsequent scan. In other words, how often to scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] window @parblock - * The scan window, i.e., the duration of the scan, which must be less than or - * equal to the @p interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * Note that the packet reception is aborted if it's started just before the - * scan window ends. - * @endparblock - * @param[in] flags No flags are currently defined. Set this parameter to 0. - * @param[in] filter_policy @parblock - * Enum @ref sl_bt_scanner_filter_policy_t. - * - * The scanning filter policy to use when scanning is started. The filter - * policy determines which advertisements and scan responses are delivered to - * the application. Values: - * - sl_bt_scanner_filter_policy_basic_unfiltered (0x0): Advertising - * and scan response PDUs are processed from all devices. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be a Resolvable Private Address that is - * resolved to the local device by the Bluetooth controller. - * - sl_bt_scanner_filter_policy_basic_filtered (0x1): Advertising - * and scan response PDUs are processed only from devices that the - * application has added to the Filter Accept List. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be a Resolvable Private Address that is - * resolved to the local device by the Bluetooth controller. - * - sl_bt_scanner_filter_policy_extended_unfiltered (0x2): - * Advertising and scan response PDUs are processed from all devices. For - * directed advertising, the target address must additionally match the - * identity address of the local device or be any Resolvable Private - * Address. - * - sl_bt_scanner_filter_policy_extended_filtered (0x3): Advertising - * and scan response PDUs are processed only from devices that the - * application has added to the Filter Accept List. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be any Resolvable Private Address. - * - * Default value: @ref sl_bt_scanner_filter_policy_basic_unfiltered - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, - uint16_t interval, - uint16_t window, - uint32_t flags, - uint8_t filter_policy); - -/***************************************************************************//** - * - * Stop scanning for advertising devices. For more information about the - * discovery, see the @ref sl_bt_scanner_start command. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_stop(); - -/***************************************************************************//** - * - * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters - * command. - * - * Set the scanning timing parameters on the specified PHY(s). If the device is - * currently scanning, new parameters will take effect when scanning is - * restarted. - * - * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the - * setting is set for. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs - * @param[in] scan_interval @parblock - * Scan interval is defined as the time interval when the device starts its - * last scan until it begins the subsequent scan. In other words, how often to - * scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case-dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] scan_window @parblock - * Scan window defines the duration of the scan which must be less than or - * equal to the @p scan_interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms Note that the packet reception is aborted if it's - * started just before the scan window ends. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, - uint16_t scan_interval, - uint16_t scan_window); - -/***************************************************************************//** - * - * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters - * command. - * - * Set the scan mode on the specified PHY(s). If the device is currently - * scanning, new parameters will take effect when scanning is restarted. - * - * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the - * setting is set for. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs - * @param[in] scan_mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * The scan mode. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode); - -/***************************************************************************//** - * - * Start the GAP discovery procedure to scan for advertising devices that use - * legacy or extended advertising PDUs. To cancel an ongoing discovery - * procedure, use the @ref sl_bt_scanner_stop command. - * - * The invalid parameter error will be returned if the value of scanning PHYs is - * invalid or the device does not support a PHY. - * - * Received advertising packets are not filtered in any way, so multiple events - * will be received for every advertising device in range. - * - * @param[in] scanning_phy @parblock - * Enum @ref sl_bt_scanner_scan_phy_t. - * - * The scanning PHY(s). - * - * In simultaneous scanning, the stack alternates the scanning on two PHYs by - * switching the PHY at every scan interval. When a timing parameter is set - * differently on 1M and Coded PHY, the stack chooses the most relaxed value - * for both PHYs during simultaneous scanning, i.e., the largest scan interval - * or the smallest scan window. If one PHY is set to passive scanning and the - * other to active scanning, passive scanning is chosen for simultaneous - * scanning. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): Initiate the scanning on the 1M - * PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Initiate the scanning on the - * Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): Simultaneous scanning - * by initiating the scanning on the 1M and Coded PHY alternatively - * @endparblock - * @param[in] discover_mode Enum @ref sl_bt_scanner_discover_mode_t. Bluetooth - * discovery Mode. Values: - * - sl_bt_scanner_discover_limited (0x0): Discover only limited - * discoverable devices. - * - sl_bt_scanner_discover_generic (0x1): Discover limited and - * general discoverable devices. - * - sl_bt_scanner_discover_observation (0x2): Discover - * non-discoverable, limited and general discoverable devices. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_scanner_scan_report - This event is triggered for - * reporting a received advertisement if the application includes the - * bluetooth_feature_scanner component but does not include any other - * scanner component. - * - @ref sl_bt_evt_scanner_legacy_advertisement_report - This event is - * triggered for reporting a received advertisement that uses legacy - * advertising PDUs if the application includes the - * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component. - * - @ref sl_bt_evt_scanner_extended_advertisement_report - This event is - * triggered for reporting a received advertisement that uses extended - * advertising PDUs if the application includes the - * bluetooth_feature_extended_scanner component. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode); - -/** @} */ // end addtogroup sl_bt_scanner - -/** - * @addtogroup sl_bt_sync Synchronization - * @{ - * - * @brief Synchronization - * - * Provides the base functionality of periodic advertising synchronization. Use - * bluetooth_feature_sync_scanner and/or bluetooth_feature_past_receiver - * components to include the synchronization mechanisms that the application - * requires. Use bluetooth_feature_periodic_sync to include support for trains - * that do not have subevents or response slots, and/or - * bluetooth_feature_pawr_sync to include support for Periodic Advertising with - * Responses (PAwR) trains. - * - * Some functionality in this class is considered deprecated and has been - * superseded by new classes. When one or more of - * bluetooth_feature_sync_scanner, bluetooth_feature_periodic_sync, or - * bluetooth_feature_pawr_sync components is included by the application, - * commands that have been superseded by the new classes are no longer available - * for use in the @ref sl_bt_sync class. Calling them will receive - * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: - * - @ref sl_bt_sync_set_parameters - * - @ref sl_bt_sync_open - * - * See the command descriptions for the replacements. - * - * Events that are deprecated and superseded by the new classes are no longer - * triggered by the @ref sl_bt_sync class if any of the new classes are included - * in the application. See event descriptions for the replacements. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_set_parameters_id 0x02420020 -#define sl_bt_cmd_sync_open_id 0x00420020 -#define sl_bt_cmd_sync_set_reporting_mode_id 0x03420020 -#define sl_bt_cmd_sync_update_sync_parameters_id 0x04420020 -#define sl_bt_cmd_sync_close_id 0x01420020 -#define sl_bt_rsp_sync_set_parameters_id 0x02420020 -#define sl_bt_rsp_sync_open_id 0x00420020 -#define sl_bt_rsp_sync_set_reporting_mode_id 0x03420020 -#define sl_bt_rsp_sync_update_sync_parameters_id 0x04420020 -#define sl_bt_rsp_sync_close_id 0x01420020 - -/** - * @brief Specifies the mode for periodic advertising reports. - */ -typedef enum -{ - sl_bt_sync_report_none = 0x0, /**< (0x0) Data received in periodic advertising - trains is not reported to the application. */ - sl_bt_sync_report_all = 0x1 /**< (0x1) Data received in periodic advertising - trains is reported to the application. */ -} sl_bt_sync_reporting_mode_t; - -/** - * @brief These values indicate the advertiser clock accuracy in a periodic - * advertising synchronization. - */ -typedef enum -{ - sl_bt_sync_clock_accuracy_500 = 0x1f4, /**< (0x1f4) Clock accuracy 500 ppm */ - sl_bt_sync_clock_accuracy_250 = 0xfa, /**< (0xfa) Clock accuracy 250 ppm */ - sl_bt_sync_clock_accuracy_150 = 0x96, /**< (0x96) Clock accuracy 150 ppm */ - sl_bt_sync_clock_accuracy_100 = 0x64, /**< (0x64) Clock accuracy 100 ppm */ - sl_bt_sync_clock_accuracy_75 = 0x4b, /**< (0x4b) Clock accuracy 75 ppm */ - sl_bt_sync_clock_accuracy_50 = 0x32, /**< (0x32) Clock accuracy 50 ppm */ - sl_bt_sync_clock_accuracy_30 = 0x1e, /**< (0x1e) Clock accuracy 30 ppm */ - sl_bt_sync_clock_accuracy_20 = 0x14 /**< (0x14) Clock accuracy 20 ppm */ -} sl_bt_sync_advertiser_clock_accuracy_t; - -/** - * @addtogroup sl_bt_evt_sync_opened sl_bt_evt_sync_opened - * @{ - * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_opened - * for periodic advertising trains that do not have subevents or response slots, - * and with @ref sl_bt_evt_pawr_sync_opened for Periodic Advertising with - * Responses (PAwR) trains. - * - * Indicates that a periodic advertising synchronization has been opened. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_sync_opened_id 0x004200a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_opened_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_sync_opened_s sl_bt_evt_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_opened - -/** - * @addtogroup sl_bt_evt_sync_transfer_received sl_bt_evt_sync_transfer_received - * @{ - * @brief Deprecated and replaced by @ref - * sl_bt_evt_periodic_sync_transfer_received for periodic advertising trains - * that do not have subevents or response slots responses, and with @ref - * sl_bt_evt_pawr_sync_transfer_received for Periodic Advertising with Responses - * (PAwR) trains. - * - * Indicates that synchronization information for a periodic advertising train - * has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_sync_transfer_received_id 0x034200a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was established. - Other values indicate that the sync failed to - get established. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_sync_transfer_received_s sl_bt_evt_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_sync_data sl_bt_evt_sync_data - * @{ - * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_report. - * - * Reports a received periodic advertisement packet. - */ - -/** @brief Identifier of the data event */ -#define sl_bt_evt_sync_data_id 0x024200a0 - -/***************************************************************************//** - * @brief Data structure of the data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_data_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the latest - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no more - to come */ - uint8array data; /**< Periodic advertising data */ -}); - -typedef struct sl_bt_evt_sync_data_s sl_bt_evt_sync_data_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_data - -/** - * @addtogroup sl_bt_evt_sync_closed sl_bt_evt_sync_closed - * @{ - * @brief Indicates that periodic advertising synchronization was lost or a - * synchronization establishment procedure was canceled - * - * The synchronization establishment procedure can be canceled explicitly by the - * application by issuing command @ref sl_bt_sync_close, or internally due to - * synchronization failing. Synchronization can fail for example due to - * incompatible sync CTE type. - */ - -/** @brief Identifier of the closed event */ -#define sl_bt_evt_sync_closed_id 0x014200a0 - -/***************************************************************************//** - * @brief Data structure of the closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_closed_s -{ - uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ -}); - -typedef struct sl_bt_evt_sync_closed_s sl_bt_evt_sync_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_closed - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_sync_scanner_set_sync_parameters. - * - * Configure periodic advertiser synchronization parameters. The specified - * parameters take effect immediately for all advertisers that have not already - * established synchronization. - * - * The application should determine skip and timeout values based on the - * periodic advertising interval provided by the advertiser. Ensure that you use - * a long enough timeout to allow multiple receives. If @p skip and @p timeout - * are used, select appropriate values so that they allow a few receiving - * attempts. Periodic advertising intervals are reported in event @ref - * sl_bt_evt_scanner_scan_report. - * - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] flags No flags defined currently - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, - uint16_t timeout, - uint32_t flags); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_sync_scanner_open. - * - * Start establishing synchronization with the specified periodic advertiser in - * parallel with other advertisers given in previous invocations of this - * command. The stack will internally enable scanning when needed so that - * synchronizations can occur. The scanning responses from the internal scanning - * are not passed to the application unless the application has also enabled - * scanning. - * - * Advertisers that have not already synced before the invocation of this - * command will be synced using the @p skip and @p timeout values configured in - * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. - * - * @param[in] address Address of the advertiser - * @param[in] address_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Advertiser address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * @param[in] adv_sid Advertising set identifier - * @param[out] sync A handle that will be assigned to the periodic advertising - * synchronization after the synchronization is established. This handle is - * valid only if the result code of this response is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_opened - Triggered after the synchronization is - * established. - * - @ref sl_bt_evt_sync_data - Indicates that a periodic advertisement packet - * is received. - * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising - * synchronization was lost or explicitly closed, or a synchronization - * establishment procedure was canceled. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync); - -/***************************************************************************//** - * - * Set data reporting mode of the periodic advertising synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] reporting_mode Enum @ref sl_bt_sync_reporting_mode_t. Specifies - * the mode for reporting data received in the periodic advertising train. - * Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Update synchronization parameters for a periodic sync that was already - * established. - * - * When a sync is established by scanning (see @ref sl_bt_sync_scanner) or by - * receiving Periodic Advertising Synchronization Transfer (see @ref - * sl_bt_past_receiver), the sync gets the @p skip and @p timeout parameters - * that were configured in the corresponding class. The application can use this - * command @ref sl_bt_sync_update_sync_parameters to update the values of a sync - * that has been established. The application can for example update the values - * to better match the actual interval of the periodic advertising train, or to - * increase the @p skip value to minimize wakeups when power saving is - * prioritized over receiving every periodic advertisement. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, - uint16_t skip, - uint16_t timeout); - -/***************************************************************************//** - * - * Close a periodic advertising synchronization or cancel an ongoing attempt of - * establishing a synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_closed - Triggered after a periodic advertising - * synchronization has been closed or canceled. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_close(uint16_t sync); - -/** @} */ // end addtogroup sl_bt_sync - -/** - * @addtogroup sl_bt_sync_scanner Periodic Advertising Sync Scanner - * @{ - * - * @brief Periodic Advertising Sync Scanner - * - * Synchronize to periodic advertising trains by scanning for extended - * advertisements that provide the synchronization information. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_scanner_set_sync_parameters_id 0x00500020 -#define sl_bt_cmd_sync_scanner_open_id 0x01500020 -#define sl_bt_rsp_sync_scanner_set_sync_parameters_id 0x00500020 -#define sl_bt_rsp_sync_scanner_open_id 0x01500020 - -/***************************************************************************//** - * - * Configure synchronization parameters for synchronizing to periodic - * advertising trains. The specified parameters take effect immediately for all - * periodic advertising trains that have not already established - * synchronization. - * - * The application should determine skip and timeout values based on the - * periodic advertising interval provided by the advertiser. Ensure that you use - * a long enough timeout to allow multiple receives. If @p skip and @p timeout - * are used, select appropriate values so that they allow a few receiving - * attempts. Periodic advertising intervals are reported in @ref - * sl_bt_evt_scanner_scan_report or @ref - * sl_bt_evt_scanner_extended_advertisement_report event. - * - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Start establishing synchronization with the specified periodic advertiser in - * parallel with other advertisers given in previous invocations of this - * command. - * - * If the application has not already started scanning with the @ref - * sl_bt_scanner_start command, the stack will internally enable scanning so - * that synchronizations can occur. The internal scanning uses the PHY that was - * most recently used with @ref sl_bt_scanner_start and the parameters that have - * been configured with @ref sl_bt_scanner_set_timing. The internal scanning is - * automatically stopped when all requested synchronizations have occurred. - * - * The scanning responses from the internal scanning are not passed to the - * application unless the application starts scanning with the @ref - * sl_bt_scanner_start command. If the application starts scanning while - * synchronizations are being established, the scanning PHY and settings set by - * the application take effect immediately and scanning for synchronizations - * continues with the new settings. When the application has started scanning - * with the @ref sl_bt_scanner_start command, scanning continues until the - * application stops scanning with the @ref sl_bt_scanner_stop command. - * - * Advertisers that have not already synced before the invocation of this - * command will be synced using the @p skip and @p timeout values configured in - * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. - * - * @param[in] address Address of the advertiser - * @param[in] address_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Advertiser address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * @param[in] adv_sid Advertising set identifier - * @param[out] sync A handle that will be assigned to the periodic advertising - * synchronization after the synchronization is established. This handle is - * valid only if the result code of this response is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_periodic_sync_opened - Triggered after synchronization is - * established to a periodic advertising train that does not have subevents - * or response slots. - * - @ref sl_bt_evt_pawr_sync_opened - Triggered after synchronization is - * established to a Periodic Advertising with Responses (PAwR) train. - * - @ref sl_bt_evt_periodic_sync_report - Triggered when data for periodic - * advertising train that does not have subevents or response slots is - * received and accepted by the reporting mode currently set to the train. - * - @ref sl_bt_evt_pawr_sync_subevent_report - Triggered when subevent data - * for Periodic Advertising with Responses (PAwR) train is received and - * accepted by the reporting mode currently set to the train. - * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising - * synchronization was lost or explicitly closed, or a synchronization - * establishment procedure was canceled. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_scanner_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync); - -/** @} */ // end addtogroup sl_bt_sync_scanner - -/** - * @addtogroup sl_bt_past_receiver PAST Receiver - * @{ - * - * @brief PAST Receiver - * - * Synchronize to periodic advertising trains by receiving Periodic Advertising - * Synchronization Transfer over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id 0x00510020 -#define sl_bt_cmd_past_receiver_set_sync_receive_parameters_id 0x01510020 -#define sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_id 0x00510020 -#define sl_bt_rsp_past_receiver_set_sync_receive_parameters_id 0x01510020 - -/** - * @brief Specifies the mode for receiving synchronization transfers - */ -typedef enum -{ - sl_bt_past_receiver_mode_ignore = 0x0, /**< (0x0) No attempt is made to - synchronize to a periodic - advertising train for which - the synchronization - information was received. No - event will be triggered - towards the application. */ - sl_bt_past_receiver_mode_synchronize = 0x1 /**< (0x1) Attempt to synchronize - to a periodic advertising - train for which the - synchronization information - was received. When the - information is received, an - event will be triggered to - indicate success or failure - and to provide the - application with the periodic - advertising synchronization - handle. */ -} sl_bt_past_receiver_mode_t; - -/***************************************************************************//** - * - * Set the default parameters for receiving Periodic Advertising Synchronization - * Transfers (PAST) over connections. The default parameters will be in effect - * for all subsequent connections, unless overridden by command @ref - * sl_bt_past_receiver_set_sync_receive_parameters after the connection is - * opened. - * - * This command sets parameters that do not limit the synchronization based on - * the CTE type. If the application includes bluetooth_feature_aoa_receiver or - * bluetooth_feature_aod_receiver component and wants to specify a particular - * CTE limitation, the application should use the command @ref - * sl_bt_cte_receiver_set_default_sync_receive_parameters to set the default - * parameters. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Set the parameters for receiving Periodic Advertising Synchronization - * Transfers (PAST) over the specified connection. The parameters do not affect - * periodic advertising trains that the device has already synchronized to. - * - * This command sets parameters that do not limit the synchronization based on - * the CTE type. If the application includes bluetooth_feature_aoa_receiver or - * bluetooth_feature_aod_receiver component and wants to specify a particular - * CTE limitation, the application should use the command @ref - * sl_bt_cte_receiver_set_sync_receive_parameters to set the parameters. - * - * @param[in] connection Connection handle of the connection used to receive the - * sync transfer - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/** @} */ // end addtogroup sl_bt_past_receiver - -/** - * @addtogroup sl_bt_advertiser_past Advertiser PAST - * @{ - * - * @brief Advertiser PAST - * - * Transfer the synchronization information of a local active periodic - * advertising set to a remote device using Periodic Advertising Synchronization - * Transfer (PAST) over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_advertiser_past_transfer_id 0x00520020 -#define sl_bt_rsp_advertiser_past_transfer_id 0x00520020 - -/***************************************************************************//** - * - * Transfer the synchronization information of an advertising set that is - * actively performing periodic advertising. - * - * @param[in] connection Connection handle of the connection used to transmit - * the sync transfer - * @param[in] service_data A value provided by the application for use by the - * peer device. - * @param[in] advertising_set Handle of the periodic advertising set to transfer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, - uint16_t service_data, - uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_advertiser_past - -/** - * @addtogroup sl_bt_sync_past Sync PAST - * @{ - * - * @brief Sync PAST - * - * Transfer the synchronization information of a synchronized periodic - * advertising train to a remote device using Periodic Advertising - * Synchronization Transfer (PAST) over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_past_transfer_id 0x005b0020 -#define sl_bt_rsp_sync_past_transfer_id 0x005b0020 - -/***************************************************************************//** - * - * Transfer the synchronization information of a periodic advertising train for - * which a sync has been established. - * - * @param[in] connection Connection handle of the connection used to transmit - * the sync transfer - * @param[in] service_data A value provided by the application for use by the - * peer device. - * @param[in] sync Handle of the periodic advertising synchronization to - * transfer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_past_transfer(uint8_t connection, - uint16_t service_data, - uint16_t sync); - -/** @} */ // end addtogroup sl_bt_sync_past - -/** - * @addtogroup sl_bt_periodic_sync Periodic Advertising without responses Synchronization - * @{ - * - * @brief Periodic Advertising without responses Synchronization - * - * Provides events and control for synchronized periodic advertising trains that - * do not have subevents or response slots. Synchronization is achieved by - * scanning (see @ref sl_bt_sync_scanner) or by receiving Periodic Advertising - * Synchronization Transfer (see @ref sl_bt_past_receiver). - */ - -/* Command and Response IDs */ - -/** - * @addtogroup sl_bt_evt_periodic_sync_opened sl_bt_evt_periodic_sync_opened - * @{ - * @brief Indicates that synchronization to a periodic advertising train that - * does not have subevents or response slots has been opened by scanning - * - * See command @ref sl_bt_sync_scanner_open. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_periodic_sync_opened_id 0x005300a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_opened_s -{ - uint16_t sync; /**< Periodic Advertising synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The Periodic Advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_periodic_sync_opened_s sl_bt_evt_periodic_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_opened - -/** - * @addtogroup sl_bt_evt_periodic_sync_transfer_received sl_bt_evt_periodic_sync_transfer_received - * @{ - * @brief Indicates that synchronization information for a periodic advertising - * train that does not have subevents or response slots has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_periodic_sync_transfer_received_id 0x015300a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was established. - Other values indicate that the sync failed to - get established. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_periodic_sync_transfer_received_s sl_bt_evt_periodic_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_periodic_sync_report sl_bt_evt_periodic_sync_report - * @{ - * @brief Reports a periodic advertising packet for periodic advertising train - * that does not have subevents or response slots - */ - -/** @brief Identifier of the report event */ -#define sl_bt_evt_periodic_sync_report_id 0x025300a0 - -/***************************************************************************//** - * @brief Data structure of the report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_report_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the latest - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no more - to come */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_periodic_sync_report event as a - monotonically increasing counter that wraps from - 255 to 0. There is a single counter for this - event type that starts from value 0 when the - Bluetooth stack is started and is never reset - while the stack is running. This counter can be - used to detect if one or more @ref - sl_bt_evt_periodic_sync_report events have been - created by the stack but dropped due to problems - such as temporarily running out of resources - before the event reached the application. */ - uint8array data; /**< Periodic advertising data */ -}); - -typedef struct sl_bt_evt_periodic_sync_report_s sl_bt_evt_periodic_sync_report_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_report - -/** @} */ // end addtogroup sl_bt_periodic_sync - -/** - * @addtogroup sl_bt_pawr_sync Periodic Advertising with responses Synchronization - * @{ - * - * @brief Periodic Advertising with responses Synchronization - * - * Provides events and control for synchronized Periodic Advertising with - * Responses (PAwR) trains. Synchronization is achieved by scanning (see @ref - * sl_bt_sync_scanner) or by receiving Periodic Advertising Synchronization - * Transfer (see @ref sl_bt_past_receiver). - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_pawr_sync_set_sync_subevents_id 0x02540020 -#define sl_bt_cmd_pawr_sync_set_response_data_id 0x03540020 -#define sl_bt_rsp_pawr_sync_set_sync_subevents_id 0x02540020 -#define sl_bt_rsp_pawr_sync_set_response_data_id 0x03540020 - -/** - * @addtogroup sl_bt_evt_pawr_sync_opened sl_bt_evt_pawr_sync_opened - * @{ - * @brief Indicates that synchronization to a Periodic Advertising with - * Responses (PAwR) train has been opened by scanning - * - * See command @ref sl_bt_sync_scanner_open. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_pawr_sync_opened_id 0x005400a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_opened_s -{ - uint16_t sync; /**< PAwR synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser - PHY. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value - in units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. - The advertiser clock accuracy. */ - uint8_t num_subevents; /**< The number of subevents. - - Range: 0x01 to 0x80 */ - uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 - ms. - - Range: 0x06 to 0xFF - - Time range: 7.5 ms to 318.75 ms */ - uint8_t response_slot_delay; /**< Time between the advertising packet in a - subevent and the first response slot. - Value in units of 1.25 ms. - - Range: 0x01 to 0xFE - - Time range: 1.25 ms to 317.5 ms */ - uint8_t response_slot_spacing; /**< Time between response slots. Value in - units of 0.125 ms. - - Range: 0x02 to 0xFF - - Time range: 0.25 ms to 31.875 ms */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_pawr_sync_opened_s sl_bt_evt_pawr_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_opened - -/** - * @addtogroup sl_bt_evt_pawr_sync_transfer_received sl_bt_evt_pawr_sync_transfer_received - * @{ - * @brief Indicates that synchronization information for Periodic Advertising - * with Responses (PAwR) train has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_pawr_sync_transfer_received_id 0x015400a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was - established. Other values indicate that - the sync failed to get established. */ - uint16_t sync; /**< PAwR synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device. */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser - PHY. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value - in units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. - The advertiser clock accuracy. */ - uint8_t num_subevents; /**< The number of subevents. - - Range: 0x01 to 0x80 */ - uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 - ms. - - Range: 0x06 to 0xFF - - Time range: 7.5 ms to 318.75 ms */ - uint8_t response_slot_delay; /**< Time between the advertising packet in a - subevent and the first response slot. - Value in units of 1.25 ms. - - Range: 0x01 to 0xFE - - Time range: 1.25 ms to 317.5 ms */ - uint8_t response_slot_spacing; /**< Time between response slots. Value in - units of 0.125 ms. - - Range: 0x02 to 0xFF - - Time range: 0.25 ms to 31.875 ms */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_pawr_sync_transfer_received_s sl_bt_evt_pawr_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_pawr_sync_subevent_report sl_bt_evt_pawr_sync_subevent_report - * @{ - * @brief Reports that the device's radio has received a periodic advertisement - * in a subevent of an active PAwR train - * - * This event reports also empty advertisements, i.e., advertisements that - * contained no payload data. In this case the @p data parameter has zero - * length. - */ - -/** @brief Identifier of the subevent_report event */ -#define sl_bt_evt_pawr_sync_subevent_report_id 0x025400a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_subevent_report_s -{ - uint16_t sync; /**< PAwR synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) of the - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint16_t event_counter; /**< The value of the periodic advertising event - counter (paEventCounter) of the event in which - the advertisement was received. If the - application responds to this advertisement, use - this field as the value of @p request_event - parameter for the @ref - sl_bt_pawr_sync_set_response_data command. */ - uint8_t subevent; /**< The subevent in which the advertisement was - received. If the application responds to this - advertisement, use this field as the value of - @p request_subevent parameter for the @ref - sl_bt_pawr_sync_set_response_data command. */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no - more to come - - 255: Failed to receive subevent data - in this subevent */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_pawr_sync_subevent_report event as a - monotonically increasing counter that wraps - from 255 to 0. There is a single counter for - this event type that starts from value 0 when - the Bluetooth stack is started and is never - reset while the stack is running. This counter - can be used to detect if one or more @ref - sl_bt_evt_pawr_sync_subevent_report events have - been created by the stack but dropped due to - problems such as temporarily running out of - resources before the event reached the - application. */ - uint8array data; /**< The advertisement data that was received */ -}); - -typedef struct sl_bt_evt_pawr_sync_subevent_report_s sl_bt_evt_pawr_sync_subevent_report_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_subevent_report - -/***************************************************************************//** - * - * Specify the subevents that this device will synchronize to on the specified - * PAwR train. - * - * @param[in] sync PAwR synchronization handle - * @param[in] subevents_len Length of data in @p subevents - * @param[in] subevents Array of subevent indexes to synchronize to - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, - size_t subevents_len, - const uint8_t* subevents); - -/***************************************************************************//** - * - * Set the data to be sent in the specified response slot of a subevent of an - * active PAwR train. - * - * Use this command when the application receives the @ref - * sl_bt_evt_pawr_sync_subevent_report event and the application needs to send a - * response. The application needs to set the response data within the timing - * requirements implied by the parameters of the PAwR train that the device is - * synchronized to. If the response data is set too late, this command will fail - * with result SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT. - * - * @param[in] sync PAwR synchronization handle - * @param[in] request_event The periodic advertising event counter - * (paEventCounter) of the request. Set this parameter to the value of the @p - * event_counter field of the @ref sl_bt_evt_pawr_sync_subevent_report_id - * event that the application is responding to. - * @param[in] request_subevent The subevent of the request. Set this parameter - * to the value of the @p subevent field of the @ref - * sl_bt_evt_pawr_sync_subevent_report_id event that the application is - * responding to. - * @param[in] response_subevent The subevent in which the response is to be sent - * @param[in] response_slot The response slot in which the response is to be - * sent - * @param[in] response_data_len Length of data in @p response_data - * @param[in] response_data Data to be sent in the specified response slot. - * Maximum of 248 bytes of data can be set with this command. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, - uint16_t request_event, - uint8_t request_subevent, - uint8_t response_subevent, - uint8_t response_slot, - size_t response_data_len, - const uint8_t* response_data); - -/** @} */ // end addtogroup sl_bt_pawr_sync - -/** - * @addtogroup sl_bt_pawr_advertiser PAwR Advertiser - * @{ - * - * @brief PAwR Advertiser - * - * Provides support for advertising with Periodic Advertising with Responses - * (PAwR) trains. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_pawr_advertiser_start_id 0x00550020 -#define sl_bt_cmd_pawr_advertiser_set_subevent_data_id 0x01550020 -#define sl_bt_cmd_pawr_advertiser_create_connection_id 0x02550020 -#define sl_bt_cmd_pawr_advertiser_stop_id 0x03550020 -#define sl_bt_rsp_pawr_advertiser_start_id 0x00550020 -#define sl_bt_rsp_pawr_advertiser_set_subevent_data_id 0x01550020 -#define sl_bt_rsp_pawr_advertiser_create_connection_id 0x02550020 -#define sl_bt_rsp_pawr_advertiser_stop_id 0x03550020 - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request sl_bt_evt_pawr_advertiser_subevent_data_request - * @{ - * @brief This event is triggered to indicate that the Bluetooth stack is ready - * to accept data for the specified subevents of the PAwR train. - * - * To ensure effective use of the available memory, applications are encouraged - * to observe these events and set data using @ref - * sl_bt_pawr_advertiser_set_subevent_data for the subevents that are being - * requested and for which the application has data to send - * - * If the application has no data to send, it does not need to call @ref - * sl_bt_pawr_advertiser_set_subevent_data for that subevent. The application - * can attempt to set data for that subevent later when the application has new - * data to send. - */ - -/** @brief Identifier of the subevent_data_request event */ -#define sl_bt_evt_pawr_advertiser_subevent_data_request_id 0x005500a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_data_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_data_request_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle */ - uint8_t subevent_start; /**< The first subevent that data is requested - for */ - uint8_t subevent_data_count; /**< The number of subevents that data is - requested for */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_subevent_data_request_s sl_bt_evt_pawr_advertiser_subevent_data_request_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed sl_bt_evt_pawr_advertiser_subevent_tx_failed - * @{ - * @brief This event is triggered if subevent data was successfully set using - * @ref sl_bt_pawr_advertiser_set_subevent_data command but the attempt to - * transmit the subevent data has failed - * - * This error is not fatal. The event is provided to the application so that it - * knows not to expect response reports for this subevent and can set subevent - * data again for retransmission without needing to timeout waiting for response - * reports that will not be received because the transmission failed. - */ - -/** @brief Identifier of the subevent_tx_failed event */ -#define sl_bt_evt_pawr_advertiser_subevent_tx_failed_id 0x025500a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_tx_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle for the PAwR - train that failed to transmit subevent data */ - uint8_t subevent; /**< The subevent that failed to transmit subevent - data */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s sl_bt_evt_pawr_advertiser_subevent_tx_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_response_report sl_bt_evt_pawr_advertiser_response_report - * @{ - * @brief Reports the status and data of a used response slot of an active PAwR - * train - * - * The report is given for every response slot that was marked as used in the - * @ref sl_bt_pawr_advertiser_set_subevent_data command. - */ - -/** @brief Identifier of the response_report event */ -#define sl_bt_evt_pawr_advertiser_response_report_id 0x015500a0 - -/***************************************************************************//** - * @brief Data structure of the response_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_response_report_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle */ - uint8_t subevent; /**< The subevent that this report corresponds to */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) of the - received packet. Units: dBm - - Valid value range: -127 to +20 - - Value 127: information unavailable */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint8_t response_slot; /**< The response slot that this report - corresponds to */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come - in new events - - 2: Incomplete, data truncated, no - more to come - - 255: Failed to receive subevent - response in this response slot */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_pawr_advertiser_response_report - event as a monotonically increasing counter - that wraps from 255 to 0. There is a single - counter for this event type that starts from - value 0 when the Bluetooth stack is started - and is never reset while the stack is - running. This counter can be used to detect - if one or more @ref - sl_bt_evt_pawr_advertiser_response_report - events have been created by the stack but - dropped due to problems such as temporarily - running out of resources before the event - reached the application. */ - uint8array data; /**< The response data that was received, if any */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_response_report_s sl_bt_evt_pawr_advertiser_response_report_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_response_report - -/***************************************************************************//** - * - * Start PAwR advertising on the specified advertising set. - * - * According to the Bluetooth Core specification, PAwR advertising PDUs cannot - * be transmitted until at least one extended advertising event has been - * completed. If the application needs exact control over the extended - * advertising data and parameters, use the @ref sl_bt_advertiser class to - * configure the parameters of the advertising set and the @ref - * sl_bt_extended_advertiser class to set or generate the desired extended - * advertising data payload. If the application does not configure the - * parameters or set the data, the default parameters and empty advertising data - * are used for the extended advertising. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p - * flags, the stack will automatically start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. The application may stop the automatically started extended - * advertising using the @ref sl_bt_advertiser_stop command. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in - * @p flags, the stack will momentarily start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. Unless the application starts extended advertising before - * the first extended advertising event has completed, the stack will - * automatically stop the momentary extended advertising after the first - * extended advertising event. - * - * PAwR advertising PDUs are transmitted on the secondary PHY configured for the - * advertising set with the @ref sl_bt_extended_advertiser_set_phy command. - * - * To stop PAwR advertising, use @ref sl_bt_pawr_advertiser_stop command. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask - * of @ref sl_bt_periodic_advertiser_flags - * @param[in] num_subevents The number of subevents. - * - Range: 0x01 to 0x80 - * @param[in] subevent_interval Subevent interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFF - * - Time range: 7.5 ms to 318.75 ms - * @param[in] response_slot_delay Time between the advertising packet in a - * subevent and the first response slot. Value in units of 1.25 ms. - * - Range: 0x01 to 0xFE - * - Time range: 1.25 ms to 317.5 ms - * @param[in] response_slot_spacing Time between response slots. Value in units - * of 0.125 ms. - * - Range: 0x02 to 0xFF - * - Time range: 0.25 ms to 31.875 ms - * @param[in] response_slots Number of subevent response slots. - * - Range: 0x01 to 0xFF - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags, - uint8_t num_subevents, - uint8_t subevent_interval, - uint8_t response_slot_delay, - uint8_t response_slot_spacing, - uint8_t response_slots); - -/***************************************************************************//** - * - * Set data to be sent in the specified subevent of an active PAwR train. Data - * is transmitted only once and is discarded after it has been transmitted. - * - * Data given to this command is passed to the Bluetooth controller, which will - * queue data and transmit it at the correct time. The application may always - * opportunistically try to queue more data with this command, but the - * controller may reject data and return an error if the queuing capacity is - * exceeded. In this case, the Bluetooth stack will trigger the @ref - * sl_bt_evt_pawr_advertiser_subevent_data_request event later when the - * controller is ready to accept more data. - * - * To ensure effective use of the available memory, applications are encouraged - * to observe the @ref sl_bt_evt_pawr_advertiser_subevent_data_request events - * and set data for the subevents that are being requested and for which the - * application has data to send. Applications should also note that PAwR is an - * unreliable transport and cannot guarantee delivery. If reliability is - * required, the application must implement an acknowledgment mechanism using - * response slots of the PAwR train and set subevent data again for a - * re-transmission if it was not successfully delivered. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] subevent The subevent in which the data is to be sent - * @param[in] response_slot_start The first response slot to be used in this - * subevent - * @param[in] response_slot_count The number of response slots to be used - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be sent in the specified subevent - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_pawr_advertiser_subevent_data_request - This event is - * triggered when the Bluetooth stack is ready to accept more subevent data. - * - @ref sl_bt_evt_pawr_advertiser_subevent_tx_failed - This event is - * triggered if transmitting the subevent data has failed. - * - @ref sl_bt_evt_pawr_advertiser_response_report - If the subevent data was - * successfully transmitted, this event is triggered for each response slot - * that was marked as used in this subevent. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, - uint8_t subevent, - uint8_t response_slot_start, - uint8_t response_slot_count, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Initiate a connection request to a device that is synchronized to the - * specified active PAwR train. The connection is established on the secondary - * PHY configured for the advertising set with the @ref - * sl_bt_extended_advertiser_set_phy command. The connection uses the parameters - * configured with command @ref sl_bt_connection_set_default_parameters. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] subevent The subevent in which the connection request is to be - * sent - * @param[in] address Address of the device to connect to - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device to connect to. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @param[out] connection Handle that will be assigned to the connection after - * the connection is established. This handle is valid only if the result code - * of this command is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - This event is triggered if the - * connection failed to be created. - * - @ref sl_bt_evt_connection_opened - This event is triggered after the - * connection is opened and indicates whether the devices are already bonded - * and the role of the device in this connection. - * - @ref sl_bt_evt_connection_parameters - This event indicates the - * connection parameters and security mode of the connection. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, - uint8_t subevent, - bd_addr address, - uint8_t address_type, - uint8_t *connection); - -/***************************************************************************//** - * - * Stop PAwR advertising on an advertising set. Counterpart to @ref - * sl_bt_pawr_advertiser_start. - * - * This command does not affect the enable state of the advertising set, i.e., - * legacy or extended advertising is not stopped. - * - * @param[in] advertising_set The PAwR advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_pawr_advertiser - -/** - * @addtogroup sl_bt_connection Connection - * @{ - * - * @brief Connection - * - * The commands and events in this class are related to managing connection - * establishment, parameter setting, and disconnection procedures. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_connection_set_default_parameters_id 0x00060020 -#define sl_bt_cmd_connection_set_default_preferred_phy_id 0x01060020 -#define sl_bt_cmd_connection_set_default_data_length_id 0x10060020 -#define sl_bt_cmd_connection_open_id 0x04060020 -#define sl_bt_cmd_connection_set_parameters_id 0x06060020 -#define sl_bt_cmd_connection_set_preferred_phy_id 0x08060020 -#define sl_bt_cmd_connection_disable_slave_latency_id 0x03060020 -#define sl_bt_cmd_connection_get_median_rssi_id 0x15060020 -#define sl_bt_cmd_connection_read_channel_map_id 0x07060020 -#define sl_bt_cmd_connection_set_power_reporting_id 0x09060020 -#define sl_bt_cmd_connection_set_remote_power_reporting_id 0x0a060020 -#define sl_bt_cmd_connection_get_tx_power_id 0x0b060020 -#define sl_bt_cmd_connection_get_remote_tx_power_id 0x0c060020 -#define sl_bt_cmd_connection_set_tx_power_id 0x12060020 -#define sl_bt_cmd_connection_read_remote_used_features_id 0x0d060020 -#define sl_bt_cmd_connection_get_security_status_id 0x0e060020 -#define sl_bt_cmd_connection_set_data_length_id 0x11060020 -#define sl_bt_cmd_connection_read_statistics_id 0x13060020 -#define sl_bt_cmd_connection_get_scheduling_details_id 0x14060020 -#define sl_bt_cmd_connection_close_id 0x05060020 -#define sl_bt_cmd_connection_forcefully_close_id 0x0f060020 -#define sl_bt_cmd_connection_get_rssi_id 0x02060020 -#define sl_bt_rsp_connection_set_default_parameters_id 0x00060020 -#define sl_bt_rsp_connection_set_default_preferred_phy_id 0x01060020 -#define sl_bt_rsp_connection_set_default_data_length_id 0x10060020 -#define sl_bt_rsp_connection_open_id 0x04060020 -#define sl_bt_rsp_connection_set_parameters_id 0x06060020 -#define sl_bt_rsp_connection_set_preferred_phy_id 0x08060020 -#define sl_bt_rsp_connection_disable_slave_latency_id 0x03060020 -#define sl_bt_rsp_connection_get_median_rssi_id 0x15060020 -#define sl_bt_rsp_connection_read_channel_map_id 0x07060020 -#define sl_bt_rsp_connection_set_power_reporting_id 0x09060020 -#define sl_bt_rsp_connection_set_remote_power_reporting_id 0x0a060020 -#define sl_bt_rsp_connection_get_tx_power_id 0x0b060020 -#define sl_bt_rsp_connection_get_remote_tx_power_id 0x0c060020 -#define sl_bt_rsp_connection_set_tx_power_id 0x12060020 -#define sl_bt_rsp_connection_read_remote_used_features_id 0x0d060020 -#define sl_bt_rsp_connection_get_security_status_id 0x0e060020 -#define sl_bt_rsp_connection_set_data_length_id 0x11060020 -#define sl_bt_rsp_connection_read_statistics_id 0x13060020 -#define sl_bt_rsp_connection_get_scheduling_details_id 0x14060020 -#define sl_bt_rsp_connection_close_id 0x05060020 -#define sl_bt_rsp_connection_forcefully_close_id 0x0f060020 -#define sl_bt_rsp_connection_get_rssi_id 0x02060020 - -/** - * @brief Types of device roles in a Bluetooth connection - */ -typedef enum -{ - sl_bt_connection_role_peripheral = 0x0, /**< (0x0) The Peripheral role */ - sl_bt_connection_role_central = 0x1 /**< (0x1) The Central role */ -} sl_bt_connection_role_t; - -/** - * @brief Indicate the Bluetooth Security Mode. - */ -typedef enum -{ - sl_bt_connection_mode1_level1 = 0x0, /**< (0x0) No security */ - sl_bt_connection_mode1_level2 = 0x1, /**< (0x1) Unauthenticated pairing with - encryption */ - sl_bt_connection_mode1_level3 = 0x2, /**< (0x2) Authenticated pairing with - encryption */ - sl_bt_connection_mode1_level4 = 0x3 /**< (0x3) Authenticated Secure - Connections pairing with encryption - using a 128-bit strength encryption - key */ -} sl_bt_connection_security_t; - -/** - * @brief These values define transmit power reporting modes in LE power - * control. - */ -typedef enum -{ - sl_bt_connection_power_reporting_disable = 0x0, /**< (0x0) Disable transmit - power reporting */ - sl_bt_connection_power_reporting_enable = 0x1 /**< (0x1) Enable transmit - power reporting */ -} sl_bt_connection_power_reporting_mode_t; - -/** - * @brief This enum defines the flag values for a reported transmit power level. - */ -typedef enum -{ - sl_bt_connection_tx_power_flag_none = 0x0, /**< (0x0) No flag is defined for - the reported TX power level */ - sl_bt_connection_tx_power_at_minimum = 0x1, /**< (0x1) Transmit power level is - at minimum level. */ - sl_bt_connection_tx_power_at_maximum = 0x2 /**< (0x2) Transmit power level is - at maximum level. */ -} sl_bt_connection_tx_power_flag_t; - -/** - * @addtogroup sl_bt_connection_rssi_const RSSI Value Constants - * @{ - * - * Constants for RSSI value - */ - -/** RSSI value is unavailable */ -#define SL_BT_CONNECTION_RSSI_UNAVAILABLE 0x7f - -/** @} */ // end RSSI Value Constants - -/** - * @addtogroup sl_bt_connection_tx_power_const Transmit Power Reporting Constants - * @{ - * - * Constants in transmit power reporting - */ - -/** Remote device is not managing power levels. */ -#define SL_BT_CONNECTION_TX_POWER_UNMANAGED 0x7e - -/** Transmit power level is not available. */ -#define SL_BT_CONNECTION_TX_POWER_UNAVAILABLE 0x7f - -/** Change is not available or is out of range. */ -#define SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE 0x7f - -/** @} */ // end Transmit Power Reporting Constants - -/** - * @addtogroup sl_bt_evt_connection_opened sl_bt_evt_connection_opened - * @{ - * @brief Indicates that a new connection was opened - * - * The specific semantics depend on the role of the device: - * - On the central device (parameter @p master set to @ref - * sl_bt_connection_role_central) the event is triggered when the Link Layer - * has sent a connect request to the remote device. - * - On the peripheral device (parameter @p master set to @ref - * sl_bt_connection_role_peripheral) the event is triggered when the Link - * Layer has responded to the connect request of the remote device. - * - * This event does not indicate the connection has been established (i.e., that - * a data packet was received within 6 connection intervals). If the connection - * is not established, an @ref sl_bt_evt_connection_closed event will - * immediately follow. - * - * An open connection can be closed with @ref sl_bt_connection_close command by - * giving the connection handle obtained from this event. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_connection_opened_id 0x000600a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_opened_s -{ - bd_addr address; /**< Remote device address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. Remote device - address type. Values: - - sl_bt_gap_public_address (0x0): Public - device address - - sl_bt_gap_static_address (0x1): Static - device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t master; /**< Enum @ref sl_bt_connection_role_t. The role this - device operates in the connection. Values: - - sl_bt_connection_role_peripheral (0x0): - The Peripheral role - - sl_bt_connection_role_central (0x1): - The Central role */ - uint8_t connection; /**< Handle for new connection */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): No - bonding - - Other: Bonding handle */ - uint8_t advertiser; /**< The local advertising set that this connection was - opened to. Values: - - SL_BT_INVALID_ADVERTISING_SET_HANDLE - (0xff): Invalid value or not applicable. - Ignore this field - - Other: The advertising set handle */ - uint16_t sync; /**< The sync handle if the local device is in the - peripheral-role and the connection was opened via - a Periodic Advertising with Responses (PAwR) train - that the local device has synchronized to. Values: - - SL_BT_INVALID_SYNC_HANDLE (0xffff): The - connection was not opened over a PAwR train - that the local device is synchronized to - - Other: The sync handle for the PAwR - train that was used to open the connection */ -}); - -typedef struct sl_bt_evt_connection_opened_s sl_bt_evt_connection_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_opened - -/** - * @addtogroup sl_bt_evt_connection_parameters sl_bt_evt_connection_parameters - * @{ - * @brief Triggered whenever the connection parameters are changed and at any - * time a connection is established - */ - -/** @brief Identifier of the parameters event */ -#define sl_bt_evt_connection_parameters_id 0x020600a0 - -/***************************************************************************//** - * @brief Data structure of the parameters event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_parameters_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t interval; /**< Connection interval. Time = Value x 1.25 ms */ - uint16_t latency; /**< Peripheral latency (how many connection intervals - the peripheral can skip) */ - uint16_t timeout; /**< Supervision timeout. Time = Value x 10 ms */ - uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection - security mode. Values: - - sl_bt_connection_mode1_level1 (0x0): - No security - - sl_bt_connection_mode1_level2 (0x1): - Unauthenticated pairing with encryption - - sl_bt_connection_mode1_level3 (0x2): - Authenticated pairing with encryption - - sl_bt_connection_mode1_level4 (0x3): - Authenticated Secure Connections pairing with - encryption using a 128-bit strength - encryption key */ - uint16_t txsize; /**< Deprecated and no longer used for - reporting the connection data length update. Use - the event @ref sl_bt_evt_connection_data_length - instead. */ -}); - -typedef struct sl_bt_evt_connection_parameters_s sl_bt_evt_connection_parameters_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_parameters - -/** - * @addtogroup sl_bt_evt_connection_set_parameters_failed sl_bt_evt_connection_set_parameters_failed - * @{ - * @brief Triggered when the peer device rejected an L2CAP connection parameter - * update request as a result of calling command @ref - * sl_bt_connection_set_parameters to change connection parameters on the @ref - * sl_bt_connection_role_peripheral role - */ - -/** @brief Identifier of the set_parameters_failed event */ -#define sl_bt_evt_connection_set_parameters_failed_id 0x100600a0 - -/***************************************************************************//** - * @brief Data structure of the set_parameters_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_set_parameters_failed_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_connection_set_parameters_failed_s sl_bt_evt_connection_set_parameters_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_set_parameters_failed - -/** - * @addtogroup sl_bt_evt_connection_phy_status sl_bt_evt_connection_phy_status - * @{ - * @brief Indicates that PHY update procedure is completed. - */ - -/** @brief Identifier of the phy_status event */ -#define sl_bt_evt_connection_phy_status_id 0x040600a0 - -/***************************************************************************//** - * @brief Data structure of the phy_status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_phy_status_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t phy; /**< Current active PHY. See values from @ref - sl_bt_connection_set_preferred_phy command. */ -}); - -typedef struct sl_bt_evt_connection_phy_status_s sl_bt_evt_connection_phy_status_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_phy_status - -/** - * @addtogroup sl_bt_evt_connection_get_remote_tx_power_completed sl_bt_evt_connection_get_remote_tx_power_completed - * @{ - * @brief Indicates that reading remote transmit power initiated by @ref - * sl_bt_connection_get_remote_tx_power command has completed - */ - -/** @brief Identifier of the get_remote_tx_power_completed event */ -#define sl_bt_evt_connection_get_remote_tx_power_completed_id 0x050600a0 - -/***************************************************************************//** - * @brief Data structure of the get_remote_tx_power_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_get_remote_tx_power_completed_s -{ - uint16_t status; /**< SL_STATUS_OK or another error code indicating the - reading remote transmit power operation failed. */ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY for which - the transmit power is reported. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): - 1M PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): - 2M PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED - (0x7E): Remote device is not managing power - levels on this PHY. - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. - Transmit power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out - of range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_get_remote_tx_power_completed_s sl_bt_evt_connection_get_remote_tx_power_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_get_remote_tx_power_completed - -/** - * @addtogroup sl_bt_evt_connection_tx_power sl_bt_evt_connection_tx_power - * @{ - * @brief Reports a transmit power change on the local device of a connection if - * transmit power reporting has been enabled - * - * Enable or disable transmit power reporting using @ref - * sl_bt_connection_set_power_reporting command. Local transmit power reporting - * is enabled by default for new connections. - * - * When enabled, local transmit power change events may get triggered in the - * following situations: - * - When the connection has just opened and the initial transmit power is set - * - When the application explicitly changes the system TX power using the - * @ref sl_bt_system_set_tx_power command - * - When the bluetooth_feature_power_control component is included and - * enabled in the application and the local transmit power is adjusted by - * the power control feature - * - When the bluetooth_feature_afh component for Adaptive Frequency Hopping - * is included and enabled in the application and the local transmit power - * is adjusted due to changes in the availability of good channels. - */ - -/** @brief Identifier of the tx_power event */ -#define sl_bt_evt_connection_tx_power_id 0x060600a0 - -/***************************************************************************//** - * @brief Data structure of the tx_power event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_tx_power_s -{ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the - transmit power is reported for. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M - PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M - PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit - power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out of - range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_tx_power_s sl_bt_evt_connection_tx_power_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_tx_power - -/** - * @addtogroup sl_bt_evt_connection_remote_tx_power sl_bt_evt_connection_remote_tx_power - * @{ - * @brief Reports a transmit power change of the connection on the remote device - * that supports the LE Power Control for the connection - * - * This event is enabled if reporting the remote transmit power change has been - * enabled with the @ref sl_bt_connection_set_remote_power_reporting command. - */ - -/** @brief Identifier of the remote_tx_power event */ -#define sl_bt_evt_connection_remote_tx_power_id 0x070600a0 - -/***************************************************************************//** - * @brief Data structure of the remote_tx_power event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_remote_tx_power_s -{ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the - transmit power is reported for. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M - PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M - PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED - (0x7E): Remote device is not managing power - levels on this PHY. - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit - power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out of - range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_remote_tx_power_s sl_bt_evt_connection_remote_tx_power_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_remote_tx_power - -/** - * @addtogroup sl_bt_evt_connection_remote_used_features sl_bt_evt_connection_remote_used_features - * @{ - * @brief List of link layer features supported by the remote device. - */ - -/** @brief Identifier of the remote_used_features event */ -#define sl_bt_evt_connection_remote_used_features_id 0x080600a0 - -/***************************************************************************//** - * @brief Data structure of the remote_used_features event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_remote_used_features_s -{ - uint8_t connection; /**< Connection handle */ - uint8array features; /**< This parameter is 8 bytes in little endian format - and contains bit fields describing the supported - link layer features of the remote device. Bit - value 1 means that the feature is supported. - - The bits are explained in Bluetooth specification - Vol 6, Part B, 4.6. */ -}); - -typedef struct sl_bt_evt_connection_remote_used_features_s sl_bt_evt_connection_remote_used_features_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_remote_used_features - -/** - * @addtogroup sl_bt_evt_connection_data_length sl_bt_evt_connection_data_length - * @{ - * @brief Reports a change to the maximum payload length or maximum TX time in - * either direction of a connection. - */ - -/** @brief Identifier of the data_length event */ -#define sl_bt_evt_connection_data_length_id 0x090600a0 - -/***************************************************************************//** - * @brief Data structure of the data_length event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_data_length_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t tx_data_len; /**< The maximum payload octets of a packet that the - local Controller will send */ - uint16_t tx_time_us; /**< The maximum time in microseconds that the local - Controller will take to send a data packet */ - uint16_t rx_data_len; /**< The maximum payload octets of a packet that the - local Controller expects to receive */ - uint16_t rx_time_us; /**< The maximum time in microseconds that the local - Controller expects to take to receive a data packet */ -}); - -typedef struct sl_bt_evt_connection_data_length_s sl_bt_evt_connection_data_length_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_data_length - -/** - * @addtogroup sl_bt_evt_connection_statistics sl_bt_evt_connection_statistics - * @{ - * @brief Provides the connection statistic values when the application includes - * the component bluetooth_feature_connection_statistics - * - * When the component is included by the application, this event is - * automatically triggered to provide the final statistics for the connection - * just before the @ref sl_bt_evt_connection_closed event indicates that a - * connection has been closed. This event is also triggered when the application - * has requested reading the statistics using the command @ref - * sl_bt_connection_read_statistics. - */ - -/** @brief Identifier of the statistics event */ -#define sl_bt_evt_connection_statistics_id 0x0a0600a0 - -/***************************************************************************//** - * @brief Data structure of the statistics event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_statistics_s -{ - uint8_t connection; /**< Handle of the connection */ - int8_t rssi_min; /**< The minimum Received Signal - Strength Indicator (RSSI) - value measured for packets - that have been successfully - received on this connection. - Units: dBm - - Valid value range: -127 to - +20 - - Value 127: information - unavailable */ - int8_t rssi_max; /**< The maximum Received Signal - Strength Indicator (RSSI) - value measured for packets - that have been successfully - received on this connection. - Units: dBm - - Valid value range: -127 to - +20 - - Value 127: information - unavailable */ - uint32_t num_total_connection_events; /**< The total number of connection - events that would have - occurred on this connection if - no packets were lost. This - count therefore includes also - connection events that were - missed due to errors (see @p - num_missed_connection_events). - In the Peripheral device this - count does not include - connection events where the - Peripheral deliberately did - not listen due to Peripheral - latency. */ - uint32_t num_missed_connection_events; /**< The number of connection - events that have been missed - on this connection. This - includes connection events - where the first packet of a - connection event was either - not received at all or was - corrupted so that it was not - recognized as belonging to - this connection. */ - uint32_t num_successful_connection_events; /**< The number of connection - events that have occured on - this connection without - errors. */ - uint32_t num_crc_errors; /**< The number of packets that - have been received on this - connection with a Cyclic - Redundancy Check (CRC) error. */ -}); - -typedef struct sl_bt_evt_connection_statistics_s sl_bt_evt_connection_statistics_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_statistics - -/** - * @addtogroup sl_bt_evt_connection_closed sl_bt_evt_connection_closed - * @{ - * @brief Indicates that a connection was either closed or that no connection - * was established from a high duty cycle directed advertising. - * - * If the application includes the component - * bluetooth_feature_connection_statistics and the connection was successfully - * opened, the event @ref sl_bt_evt_connection_statistics is automatically - * triggered just before the connection closed event to provide the application - * with the final statistic values of the connection. - */ - -/** @brief Identifier of the closed event */ -#define sl_bt_evt_connection_closed_id 0x010600a0 - -/***************************************************************************//** - * @brief Data structure of the closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_closed_s -{ - uint16_t reason; /**< Reason of connection close. - - Error code SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT - indicates that the high duty cycle directed - advertising timed out and no connection was - established. Ignore the value of @p connection in - this case. */ - uint8_t connection; /**< Handle of the closed connection */ -}); - -typedef struct sl_bt_evt_connection_closed_s sl_bt_evt_connection_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_closed - -/** - * @addtogroup sl_bt_evt_connection_rssi sl_bt_evt_connection_rssi - * @{ - * @brief Triggered when a @ref sl_bt_connection_get_rssi command has completed - * - * This event is only used by deprecated @ref sl_bt_connection_get_rssi that - * returns the RSSI value asynchronously. - * - * Use the @ref sl_bt_connection_get_median_rssi command to get the RSSI - * synchronously. - */ - -/** @brief Identifier of the rssi event */ -#define sl_bt_evt_connection_rssi_id 0x030600a0 - -/***************************************************************************//** - * @brief Data structure of the rssi event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_rssi_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t status; /**< Command complete status which is always SL_STATUS_OK */ - int8_t rssi; /**< The median of the last seven measured RSSI values on - the connection. Units: dBm. Range: -127 to +20. */ -}); - -typedef struct sl_bt_evt_connection_rssi_s sl_bt_evt_connection_rssi_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_rssi - -/***************************************************************************//** - * - * Set default Bluetooth connection parameters. The values are valid for all - * subsequent connections initiated by this device. - * - * @p min_ce_length and @p max_ce_length specify the preference of the - * connection event length so that the Link Layer can prioritize tasks - * accordingly in simultaneous connections, or scanning and so on. A connection - * event starts at an anchor point of a connection interval and lasts until the - * lesser of @p max_ce_length and the actual connection interval. Packets that - * do not fit into the connection event will be sent in the next connection - * interval. - * - * To change parameters of an already established connection, use the command - * @ref sl_bt_connection_set_parameters. - * - * @param[in] min_interval @parblock - * Minimum value for the connection event interval. This must be set less than - * or equal to @p max_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * - * Default value: 20 ms - * @endparblock - * @param[in] max_interval @parblock - * Maximum value for the connection event interval. This must be set greater - * than or equal to @p min_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * - * Default value: 50 ms - * @endparblock - * @param[in] latency @parblock - * Peripheral latency, which defines how many connection intervals the - * peripheral can skip if it has no data to send - * - Range: 0x0000 to 0x01f3 - * - * Default value: 0 - * @endparblock - * @param[in] timeout @parblock - * Supervision timeout, which defines the time that the connection is - * maintained although the devices can't communicate at the currently - * configured connection intervals. - * - Range: 0x000a to 0x0c80 - * - Time = Value x 10 ms - * - Time Range: 100 ms to 32 s - * - The value in milliseconds must be larger than (1 + @p latency) * @p - * max_interval * 2, where @p max_interval is given in milliseconds - * - * Set the supervision timeout at a value which allows communication attempts - * over at least a few connection intervals. - * - * Default value: 1000 ms - * @endparblock - * @param[in] min_ce_length @parblock - * Minimum length of the connection event. It must be less than or equal to @p - * max_ce_length. - * - * This value defines the minimum time that should be given to the connection - * event in a situation where other tasks need to run immediately after the - * connection event. When the value is very small, the connection event still - * has at least one TX/RX operation. If this value is increased, more time is - * reserved for the connection event so it can transmit and receive more - * packets in a connection interval. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0x0000 - * @endparblock - * @param[in] max_ce_length @parblock - * Maximum length of the connection event. It must be greater than or equal to - * @p min_ce_length. - * - * This value is used for limiting the connection event length so that a - * connection that has large amounts of data to transmit or receive doesn't - * block other tasks. Limiting the connection event is a hard stop. If there - * is no enough time to send or receive a packet, the connection event will be - * closed. - * - * If the value is set to 0, the connection event still has at least one TX/RX - * operation. This is useful to limit power consumption or leave more time to - * other tasks. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0xffff - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length); - -/***************************************************************************//** - * - * Set default preferred and accepted PHYs. PHY settings will be used for all - * subsequent connections. Non-preferred PHY can also be set if the remote - * device does not accept any of the preferred PHYs. - * - * The parameter @p accepted_phy is used to specify PHYs that the stack can - * accept in a remotely-initiated PHY update request. A PHY update will not - * happen if none of the accepted PHYs are present in the request. - * - * NOTE: 2M and Coded PHYs are not supported by all devices. - * - * @param[in] preferred_phy @parblock - * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (no preference) - * @endparblock - * @param[in] accepted_phy @parblock - * Accepted PHYs in remotely-initiated PHY update request. This parameter is a - * bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (all PHYs accepted) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, - uint8_t accepted_phy); - -/***************************************************************************//** - * - * Set the default preferred maximum TX payload length to be used for new - * connections. - * - * When a connection is open, the maximum TX payload length is 27. Either device - * could initiate a data length update procedure and event @ref - * sl_bt_evt_connection_data_length is generated when the data length has been - * changed on the connection. - * - * @param[in] tx_data_len @parblock - * Preferred maximum payload octets of a packet that the local Controller will - * send - * - * Range: Range: 27 (0x1B) to 251 (0xFB) - * - * Default: 251 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len); - -/***************************************************************************//** - * - * Connect to an advertising device with the specified initiating PHY on which - * connectable advertisements on primary advertising channels are received. The - * Bluetooth stack will enter a state where it continuously scans for the - * connectable advertising packets from the remote device, which matches the - * Bluetooth address given as a parameter. Scan parameters set in @ref - * sl_bt_scanner_set_timing are used in this operation. Upon receiving the - * advertising packet, the module will send a connection request packet to the - * target device to initiate a Bluetooth connection. To cancel an ongoing - * connection process, use @ref sl_bt_connection_close command with the handle - * received in response from this command. - * - * A connection is opened in no-security mode. If the GATT client needs to read - * or write the attributes on GATT server requiring encryption or - * authentication, it must first encrypt the connection using an appropriate - * authentication method. - * - * If a connection can't be established, for example, the remote device has gone - * out of range, has entered into deep sleep, or is not advertising, the stack - * will try to connect forever. In this case, the application will not get an - * event related to the connection request. To recover from this situation, the - * application can implement a timeout and call @ref sl_bt_connection_close to - * cancel the connection request. - * - * This command fails with the connection limit exceeded error if the number of - * connections attempted exceeds the configured MAX_CONNECTIONS value. - * - * This command fails with the invalid parameter error if the initiating PHY - * value is invalid or the device does not support PHY. - * - * Subsequent calls of this command have to wait for the ongoing command to - * complete. A received event @ref sl_bt_evt_connection_opened indicates that - * the connection opened successfully and a received event @ref - * sl_bt_evt_connection_closed indicates that connection failures have occurred. - * - * @param[in] address Address of the device to connect to - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device to connect to. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @param[in] initiating_phy Enum @ref sl_bt_gap_phy_t. The initiating PHY. - * Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] connection Handle that will be assigned to the connection after - * the connection is established. This handle is valid only if the result code - * of this response is 0 (zero). - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_opened - This event is triggered after the - * connection is opened and indicates whether the devices are already bonded - * and the role of the device in this connection. - * - @ref sl_bt_evt_connection_parameters - This event indicates the - * connection parameters and security mode of the connection. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_open(bd_addr address, - uint8_t address_type, - uint8_t initiating_phy, - uint8_t *connection); - -/***************************************************************************//** - * - * Request a change in the connection parameters of a Bluetooth connection. - * - On the central device the HCI LE Connection Update command is used to - * update the parameters. - * - On the peripheral device an L2CAP connection parameter update request is - * sent to the peer device to update the parameters. - * - * @p min_ce_length and @p max_ce_length specify the preference of the - * connection event length so that the Link Layer can prioritize tasks - * accordingly in simultaneous connections, or scanning and so on. A connection - * event starts at an anchor point of a connection interval and lasts until the - * lesser of @p max_ce_length and the actual connection interval. Packets that - * do not fit into the connection event will be sent in the next connection - * interval. - * - * @param[in] connection Connection Handle - * @param[in] min_interval Minimum value for the connection event interval. This - * must be set less than or equal to @p max_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * @param[in] max_interval Maximum value for the connection event interval. This - * must be set greater than or equal to @p min_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * @param[in] latency Peripheral latency, which defines how many connection - * intervals the peripheral can skip if it has no data to send - * - Range: 0x0000 to 0x01f3 - * @param[in] timeout @parblock - * Supervision timeout, which defines the time that the connection is - * maintained although the devices can't communicate at the currently - * configured connection intervals. - * - Range: 0x000a to 0x0c80 - * - Time = Value x 10 ms - * - Time Range: 100 ms to 32 s - * - The value in milliseconds must be larger than (1 + @p latency) * @p - * max_interval * 2, where @p max_interval is given in milliseconds - * - * Set the supervision timeout at a value which allows communication attempts - * over at least a few connection intervals. - * @endparblock - * @param[in] min_ce_length @parblock - * Minimum length of the connection event. It must be less than or equal to @p - * max_ce_length. - * - * This value defines the minimum time that should be given to the connection - * event in a situation where other tasks need to run immediately after the - * connection event. When the value is very small, the connection event still - * has at least one TX/RX operation. If this value is increased, more time is - * reserved for the connection event so it can transmit and receive more - * packets in a connection interval. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0x0000 - * @endparblock - * @param[in] max_ce_length @parblock - * Maximum length of the connection event. It must be greater than or equal to - * @p min_ce_length. - * - * This value is used for limiting the connection event length so that a - * connection that has large amounts of data to transmit or receive doesn't - * block other tasks. Limiting the connection event is a hard stop. If there - * is no enough time to send or receive a packet, the connection event will be - * closed. - * - * If the value is set to 0, the connection event still has at least one TX/RX - * operation. This is useful to limit power consumption or leave more time to - * other tasks. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0xffff - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_parameters - Triggered after new connection - * parameters are applied on the connection. - * - @ref sl_bt_evt_connection_set_parameters_failed - Triggered when the peer - * device rejected an L2CAP connection parameter update request. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_parameters(uint8_t connection, - uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length); - -/***************************************************************************//** - * - * Set preferred and accepted PHYs for a given connection. Event @ref - * sl_bt_evt_connection_phy_status is received when PHY update procedure is - * completed. Non-preferred PHY can also be set if remote device does not accept - * any of the preferred PHYs. - * - * The parameter @p accepted_phy is used for specifying the PHYs that the stack - * can accept in a remote initiated PHY update request. A PHY update will not - * occur if none of the accepted PHYs presents in the request. - * - * NOTE: 2M and Coded PHYs are not supported by all devices. - * - * @param[in] connection Connection handle - * @param[in] preferred_phy @parblock - * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: 125k Coded PHY (S=8) - * - 0x08: 500k Coded PHY (S=2) - * - * Default: 0xff (no preference) - * @endparblock - * @param[in] accepted_phy @parblock - * Accepted PHYs in remotely-initiated PHY update requests. This parameter is - * a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (all PHYs accepted) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_phy_status - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, - uint8_t preferred_phy, - uint8_t accepted_phy); - -/***************************************************************************//** - * - * Temporarily enable or disable peripheral latency. Used only when Bluetooth - * device is acting as a peripheral. When peripheral latency is disabled, the - * peripheral latency connection parameter is not set to 0 but the device will - * wake up on every connection interval to receive and send packets. - * - * @param[in] connection Connection Handle - * @param[in] disable 0 enable, 1 disable peripheral latency. Default: 0 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, - uint8_t disable); - -/***************************************************************************//** - * - * Get the RSSI value measured on a connection. - * - * @param[in] connection Connection handle - * @param[out] rssi The median of the last seven measured RSSI values. Units: - * dBm. Range: -127 to +20. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi); - -/***************************************************************************//** - * - * Read channel map for a specified connection. - * - * @param[in] connection Connection Handle - * @param[in] max_channel_map_size Size of output buffer passed in @p - * channel_map - * @param[out] channel_map_len On return, set to the length of output data - * written to @p channel_map - * @param[out] channel_map @parblock - * This parameter is 5 bytes and contains 37 1-bit fields. - * - * The nth field (in the range 0 to 36) contains the value for the link layer - * channel index n. - * - * - 0: Channel n is unused. - * - 1: Channel n is used. - * - * The most significant bits are reserved for future use. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, - size_t max_channel_map_size, - size_t *channel_map_len, - uint8_t *channel_map); - -/***************************************************************************//** - * - * Enable or disable the transmit power reporting for the local device on a - * connection. When transmit power reporting is enabled, event @ref - * sl_bt_evt_connection_tx_power is generated when transmit power on the local - * device changes. - * - * The command is a built-in feature in the stack and is supported regardless of - * whether the LE Power Control feature is used. By default, power reporting for - * local device is enabled. - * - * @param[in] connection Handle of the connection - * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit - * power reporting mode. Values: - * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit - * power reporting - * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit - * power reporting - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_tx_power - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, - uint8_t mode); - -/***************************************************************************//** - * - * Enable or disable reporting the transmit power change on the remote device. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. - * - * When the remote transmit power reporting is enabled, event @ref - * sl_bt_evt_connection_remote_tx_power is generated when transmit power on the - * remote device changes. - * - * By default, power reporting for the remote device is disabled. - * - * @param[in] connection Handle of the connection - * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit - * power reporting mode. Values: - * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit - * power reporting - * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit - * power reporting - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_remote_tx_power - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, - uint8_t mode); - -/***************************************************************************//** - * - * Get the transmit power of the local device on the given connection and PHY. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. - * - * @param[in] connection Handle of the connection - * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: - * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY - * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY - * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) - * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) - * @param[out] current_level The current transmit power level of the PHY on the - * connection. Values: - * - Range -127 to 20: The transmit power level in dBm - * - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE (0x7F): Transmit - * power level is not available. - * @param[out] max_level The maximum transmit power level of the PHY on the - * connection. Values: Range -127 to +20 in dBm. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, - uint8_t phy, - int8_t *current_level, - int8_t *max_level); - -/***************************************************************************//** - * - * Get the transmit power of the remote device on the given connection and PHY. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. Transmit - * power levels are returned in event @ref - * sl_bt_evt_connection_get_remote_tx_power_completed after the operation - * completed. - * - * @param[in] connection Handle of the connection - * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: - * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY - * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY - * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) - * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) - * - * @return SL_STATUS_OK if the command is accepted. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_get_remote_tx_power_completed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, - uint8_t phy); - -/***************************************************************************//** - * - * Set the transmit power of a connection. The application must include - * component bluetooth_feature_user_power_control in order to use this command - * for controlling the transmit power of the connection at application level. - * This command is unavailable if the standard Bluetooth feature LE power - * control (component bluetooth_feature_power_control) is used by the - * application. - * - * The actual selected power level is returned from this command. The value may - * be different than the requested one because of Bluetooth feature restrictions - * or radio characteristics. - * - * @param[in] connection The connection handle - * @param[in] tx_power The requested TX power. Unit: 0.1 dBm - * @param[out] tx_power_out The selected TX power. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, - int16_t tx_power, - int16_t *tx_power_out); - -/***************************************************************************//** - * - * Read link layer features supported by the remote device. - * - * @param[in] connection Connection Handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_remote_used_features - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection); - -/***************************************************************************//** - * - * Get the security status of the connection. - * - * @param[in] connection Connection handle - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size The size of encryption key - * @param[out] bonding_handle Bonding handle. Values: - * - SL_BT_INVALID_BONDING_HANDLE (0xff): No bonding - * - Other: Bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_security_status(uint8_t connection, - uint8_t *security_mode, - uint8_t *key_size, - uint8_t *bonding_handle); - -/***************************************************************************//** - * - * Request to update the maximum TX payload length and maximum packet TX time of - * a Bluetooth connection. - * - * Event @ref sl_bt_evt_connection_data_length is generated when the data length - * has been changed on the connection. - * - * @param[in] connection Connection handle - * @param[in] tx_data_len @parblock - * Preferred maximum payload octets of a packet that the local Controller will - * send - * - * Range: 27 (0x1B) to 251 (0xFB) - * @endparblock - * @param[in] tx_time_us @parblock - * Preferred maximum TX time in microseconds that the local Controller will - * take to send a packet - * - * Range: 328 (0x0148) to 17040 (0x4290) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_data_length - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_data_length(uint8_t connection, - uint16_t tx_data_len, - uint16_t tx_time_us); - -/***************************************************************************//** - * - * Read the statistic values collected on the specified connection. The - * application must include component bluetooth_feature_connection_statistics in - * order to use this command. If the component is not included in the - * application this command returns the error SL_STATUS_NOT_AVAILABLE. If this - * command is called before the connection has opened, the command returns the - * error SL_STATUS_NOT_READY. - * - * @param[in] connection The connection handle - * @param[in] reset Reset statistics if parameter value is not zero - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_statistics - Triggered to deliver the statistic - * values of the connection at the time the command was issued. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset); - -/***************************************************************************//** - * - * Get parameters and next connection event scheduling details of a connection. - * Returned values from this command provide the necessary information for - * following the packet transmissions of the connection on an external device. - * Note that the stack cannot ensure a determined timing latency from the time - * when issuing this command to the time when another device starts to follow - * the connection, and the stack cannot guarantee that a scheduled connection - * event will always happen. - * - * @param[in] connection Connection handle - * @param[out] access_address Access address of the connection - * @param[out] role Enum @ref sl_bt_connection_role_t. The role the local device - * operates in the connection. Values: - * - sl_bt_connection_role_peripheral (0x0): The Peripheral role - * - sl_bt_connection_role_central (0x1): The Central role - * @param[out] crc_init The CRC initialization value - * @param[out] interval The connection interval. Time = Value x 1.25 ms - * @param[out] supervision_timeout The connection supervision time. Time = Value - * x 10 ms - * @param[out] central_clock_accuracy The central device's clock accuracy index - * value - * @param[out] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central - * device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the - * Peripheral device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] channel_selection_algorithm Enum @ref - * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. - * Values: - * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection - * algorithm #1 - * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection - * algorithm #2 - * @param[out] hop The hop increment when the channel selection algorithm #1 is - * used on the connection. Ignore if @p channel_selection_algorithm indicates - * that the connection uses channel selection algorithm #2. - * @param[out] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Ignore bits 37-39 that are reserved for future use. - * - * A channel is unused when its bit is 0. A channel is used when its bit is 1. - * @endparblock - * @param[out] channel The data channel number that transmissions will use in - * the next connection event - * @param[out] event_counter The event counter of the next connection event - * @param[out] start_time_us Time in microseconds from the PROTIMER tick when - * the next connection event is scheduled to happen - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, - uint32_t *access_address, - uint8_t *role, - uint32_t *crc_init, - uint16_t *interval, - uint16_t *supervision_timeout, - uint8_t *central_clock_accuracy, - uint8_t *central_phy, - uint8_t *peripheral_phy, - uint8_t *channel_selection_algorithm, - uint8_t *hop, - sl_bt_connection_channel_map_t *channel_map, - uint8_t *channel, - uint16_t *event_counter, - uint32_t *start_time_us); - -/***************************************************************************//** - * - * Close a Bluetooth connection gracefully by performing the ACL Termination - * procedure or cancel an ongoing connection establishment process. The - * parameter is a connection handle which is reported in @ref - * sl_bt_evt_connection_opened event or @ref sl_bt_connection_open command - * response. - * - * Disconnecting a connection is an asynchronous operation. The disconnection is - * completed when a @ref sl_bt_evt_connection_closed event for the given - * connection handle is received. To open a new connection to the same remote - * device, wait for the @ref sl_bt_evt_connection_closed event and then initiate - * the connection. - * - * @param[in] connection Handle of the connection to be closed - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_close(uint8_t connection); - -/***************************************************************************//** - * - * Forcefully close a Bluetooth connection without performing the ACL - * Termination procedure. The parameter is a connection handle which is reported - * in @ref sl_bt_evt_connection_opened event or @ref sl_bt_connection_open - * command response. - * - * Closing a connection using this command could result in the observation of - * connection loss or supervision timeout on the remote device. Only use this - * command for special cases, for example, when disconnecting a connection with - * @ref sl_bt_connection_close did not complete in expected time period. - * - * @param[in] connection Handle of the connection to be closed - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_forcefully_close(uint8_t connection); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_connection_get_median_rssi which - * synchronously returns the value. - * - * Get the latest RSSI value of a Bluetooth connection. The RSSI value will be - * reported in a @ref sl_bt_evt_connection_rssi event if the command returns - * SL_STATUS_OK. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_rssi - Triggered when this command has - * completed. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection); - -/** @} */ // end addtogroup sl_bt_connection - -/** - * @addtogroup sl_bt_gatt GATT Client - * @{ - * - * @brief GATT Client - * - * The commands and events in this class are used to browse and manage - * attributes in a remote GATT server. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gatt_set_max_mtu_id 0x00090020 -#define sl_bt_cmd_gatt_discover_primary_services_id 0x01090020 -#define sl_bt_cmd_gatt_discover_primary_services_by_uuid_id 0x02090020 -#define sl_bt_cmd_gatt_find_included_services_id 0x10090020 -#define sl_bt_cmd_gatt_discover_characteristics_id 0x03090020 -#define sl_bt_cmd_gatt_discover_characteristics_by_uuid_id 0x04090020 -#define sl_bt_cmd_gatt_discover_descriptors_id 0x06090020 -#define sl_bt_cmd_gatt_discover_characteristic_descriptors_id 0x14090020 -#define sl_bt_cmd_gatt_set_characteristic_notification_id 0x05090020 -#define sl_bt_cmd_gatt_send_characteristic_confirmation_id 0x0d090020 -#define sl_bt_cmd_gatt_read_characteristic_value_id 0x07090020 -#define sl_bt_cmd_gatt_read_characteristic_value_from_offset_id 0x12090020 -#define sl_bt_cmd_gatt_read_multiple_characteristic_values_id 0x11090020 -#define sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id 0x08090020 -#define sl_bt_cmd_gatt_write_characteristic_value_id 0x09090020 -#define sl_bt_cmd_gatt_write_characteristic_value_without_response_id 0x0a090020 -#define sl_bt_cmd_gatt_prepare_characteristic_value_write_id 0x0b090020 -#define sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 -#define sl_bt_cmd_gatt_execute_characteristic_value_write_id 0x0c090020 -#define sl_bt_cmd_gatt_read_descriptor_value_id 0x0e090020 -#define sl_bt_cmd_gatt_write_descriptor_value_id 0x0f090020 -#define sl_bt_rsp_gatt_set_max_mtu_id 0x00090020 -#define sl_bt_rsp_gatt_discover_primary_services_id 0x01090020 -#define sl_bt_rsp_gatt_discover_primary_services_by_uuid_id 0x02090020 -#define sl_bt_rsp_gatt_find_included_services_id 0x10090020 -#define sl_bt_rsp_gatt_discover_characteristics_id 0x03090020 -#define sl_bt_rsp_gatt_discover_characteristics_by_uuid_id 0x04090020 -#define sl_bt_rsp_gatt_discover_descriptors_id 0x06090020 -#define sl_bt_rsp_gatt_discover_characteristic_descriptors_id 0x14090020 -#define sl_bt_rsp_gatt_set_characteristic_notification_id 0x05090020 -#define sl_bt_rsp_gatt_send_characteristic_confirmation_id 0x0d090020 -#define sl_bt_rsp_gatt_read_characteristic_value_id 0x07090020 -#define sl_bt_rsp_gatt_read_characteristic_value_from_offset_id 0x12090020 -#define sl_bt_rsp_gatt_read_multiple_characteristic_values_id 0x11090020 -#define sl_bt_rsp_gatt_read_characteristic_value_by_uuid_id 0x08090020 -#define sl_bt_rsp_gatt_write_characteristic_value_id 0x09090020 -#define sl_bt_rsp_gatt_write_characteristic_value_without_response_id 0x0a090020 -#define sl_bt_rsp_gatt_prepare_characteristic_value_write_id 0x0b090020 -#define sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 -#define sl_bt_rsp_gatt_execute_characteristic_value_write_id 0x0c090020 -#define sl_bt_rsp_gatt_read_descriptor_value_id 0x0e090020 -#define sl_bt_rsp_gatt_write_descriptor_value_id 0x0f090020 - -/** - * @brief These values indicate which attribute request or response has caused - * the event. - */ -typedef enum -{ - sl_bt_gatt_read_by_type_request = 0x8, /**< (0x8) Read by type request */ - sl_bt_gatt_read_by_type_response = 0x9, /**< (0x9) Read by type response */ - sl_bt_gatt_read_request = 0xa, /**< (0xa) Read request */ - sl_bt_gatt_read_response = 0xb, /**< (0xb) Read response */ - sl_bt_gatt_read_blob_request = 0xc, /**< (0xc) Read blob request */ - sl_bt_gatt_read_blob_response = 0xd, /**< (0xd) Read blob response */ - sl_bt_gatt_read_multiple_request = 0xe, /**< (0xe) Read multiple request */ - sl_bt_gatt_read_multiple_response = 0xf, /**< (0xf) Read multiple response */ - sl_bt_gatt_write_request = 0x12, /**< (0x12) Write request */ - sl_bt_gatt_write_response = 0x13, /**< (0x13) Write response */ - sl_bt_gatt_write_command = 0x52, /**< (0x52) Write command */ - sl_bt_gatt_prepare_write_request = 0x16, /**< (0x16) Prepare write request */ - sl_bt_gatt_prepare_write_response = 0x17, /**< (0x17) Prepare write - response */ - sl_bt_gatt_execute_write_request = 0x18, /**< (0x18) Execute write request */ - sl_bt_gatt_execute_write_response = 0x19, /**< (0x19) Execute write - response */ - sl_bt_gatt_handle_value_notification = 0x1b, /**< (0x1b) Notification */ - sl_bt_gatt_handle_value_indication = 0x1d /**< (0x1d) Indication */ -} sl_bt_gatt_att_opcode_t; - -/** - * @brief These values define whether the client is to receive notifications or - * indications from a remote GATT server. - */ -typedef enum -{ - sl_bt_gatt_disable = 0x0, /**< (0x0) Disable notifications and - indications */ - sl_bt_gatt_notification = 0x1, /**< (0x1) Notification */ - sl_bt_gatt_indication = 0x2 /**< (0x2) Indication */ -} sl_bt_gatt_client_config_flag_t; - -/** - * @brief These values define whether the GATT server is to cancel all queued - * writes or commit all queued writes to a remote database. - */ -typedef enum -{ - sl_bt_gatt_cancel = 0x0, /**< (0x0) Cancel all queued writes */ - sl_bt_gatt_commit = 0x1 /**< (0x1) Commit all queued writes */ -} sl_bt_gatt_execute_write_flag_t; - -/** - * @addtogroup sl_bt_evt_gatt_mtu_exchanged sl_bt_evt_gatt_mtu_exchanged - * @{ - * @brief Indicates that an ATT_MTU exchange procedure is completed - * - * The @p mtu parameter describes new MTU size. MTU size 23 is used before this - * event is received. - */ - -/** @brief Identifier of the mtu_exchanged event */ -#define sl_bt_evt_gatt_mtu_exchanged_id 0x000900a0 - -/***************************************************************************//** - * @brief Data structure of the mtu_exchanged event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_mtu_exchanged_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t mtu; /**< Exchanged ATT_MTU */ -}); - -typedef struct sl_bt_evt_gatt_mtu_exchanged_s sl_bt_evt_gatt_mtu_exchanged_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_mtu_exchanged - -/** - * @addtogroup sl_bt_evt_gatt_service sl_bt_evt_gatt_service - * @{ - * @brief Indicates that a GATT service in the remote GATT database was - * discovered - * - * This event is generated after issuing either the @ref - * sl_bt_gatt_discover_primary_services or @ref - * sl_bt_gatt_discover_primary_services_by_uuid command. - */ - -/** @brief Identifier of the service event */ -#define sl_bt_evt_gatt_service_id 0x010900a0 - -/***************************************************************************//** - * @brief Data structure of the service event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_service_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t service; /**< GATT service handle */ - uint8array uuid; /**< Service UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_service_s sl_bt_evt_gatt_service_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_service - -/** - * @addtogroup sl_bt_evt_gatt_characteristic sl_bt_evt_gatt_characteristic - * @{ - * @brief Indicates that a GATT characteristic in the remote GATT database was - * discovered - * - * This event is generated after issuing either the @ref - * sl_bt_gatt_discover_characteristics or @ref - * sl_bt_gatt_discover_characteristics_by_uuid command. - */ - -/** @brief Identifier of the characteristic event */ -#define sl_bt_evt_gatt_characteristic_id 0x020900a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle */ - uint8_t properties; /**< Characteristic properties */ - uint8array uuid; /**< Characteristic UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_characteristic_s sl_bt_evt_gatt_characteristic_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic - -/** - * @addtogroup sl_bt_evt_gatt_descriptor sl_bt_evt_gatt_descriptor - * @{ - * @brief Indicates that a GATT characteristic descriptor in the remote GATT - * database was discovered - * - * It is generated after issuing the @ref sl_bt_gatt_discover_descriptors or - * @ref sl_bt_gatt_discover_characteristic_descriptors command. - */ - -/** @brief Identifier of the descriptor event */ -#define sl_bt_evt_gatt_descriptor_id 0x030900a0 - -/***************************************************************************//** - * @brief Data structure of the descriptor event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t descriptor; /**< GATT characteristic descriptor handle */ - uint8array uuid; /**< Descriptor UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_descriptor_s sl_bt_evt_gatt_descriptor_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor - -/** - * @addtogroup sl_bt_evt_gatt_characteristic_value sl_bt_evt_gatt_characteristic_value - * @{ - * @brief Indicates that the value of one or several characteristics in the - * remote GATT server was received - * - * It is triggered by several commands: @ref - * sl_bt_gatt_read_characteristic_value, @ref - * sl_bt_gatt_read_characteristic_value_from_offset, @ref - * sl_bt_gatt_read_characteristic_value_by_uuid, @ref - * sl_bt_gatt_read_multiple_characteristic_values; and when the remote GATT - * server sends indications or notifications after enabling notifications with - * @ref sl_bt_gatt_set_characteristic_notification. The parameter @p att_opcode - * indicates which type of GATT transaction triggered this event. In particular, - * if the @p att_opcode type is @ref sl_bt_gatt_handle_value_indication (0x1d), - * the application needs to confirm the indication with @ref - * sl_bt_gatt_send_characteristic_confirmation. - */ - -/** @brief Identifier of the characteristic_value event */ -#define sl_bt_evt_gatt_characteristic_value_id 0x040900a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode, which indicates the GATT transaction - used. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Characteristic value */ -}); - -typedef struct sl_bt_evt_gatt_characteristic_value_s sl_bt_evt_gatt_characteristic_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic_value - -/** - * @addtogroup sl_bt_evt_gatt_descriptor_value sl_bt_evt_gatt_descriptor_value - * @{ - * @brief Indicates that the value of a descriptor in the remote GATT server was - * received - * - * This event is generated by the @ref sl_bt_gatt_read_descriptor_value command. - */ - -/** @brief Identifier of the descriptor_value event */ -#define sl_bt_evt_gatt_descriptor_value_id 0x050900a0 - -/***************************************************************************//** - * @brief Data structure of the descriptor_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t descriptor; /**< GATT characteristic descriptor handle */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Descriptor value */ -}); - -typedef struct sl_bt_evt_gatt_descriptor_value_s sl_bt_evt_gatt_descriptor_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor_value - -/** - * @addtogroup sl_bt_evt_gatt_procedure_completed sl_bt_evt_gatt_procedure_completed - * @{ - * @brief Indicates that the current GATT procedure was completed successfully - * or that it failed with an error - * - * All GATT commands excluding @ref - * sl_bt_gatt_write_characteristic_value_without_response and @ref - * sl_bt_gatt_send_characteristic_confirmation will trigger this event. As a - * result, the application must wait for this event before issuing another GATT - * command (excluding the two aforementioned exceptions). - * - * Note: After a failed GATT procedure with SL_STATUS_TIMEOUT error, - * further GATT transactions over this connection are not allowed by the stack. - */ - -/** @brief Identifier of the procedure_completed event */ -#define sl_bt_evt_gatt_procedure_completed_id 0x060900a0 - -/***************************************************************************//** - * @brief Data structure of the procedure_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_procedure_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t result; /**< SL_STATUS_OK if successful. Error code otherwise. */ -}); - -typedef struct sl_bt_evt_gatt_procedure_completed_s sl_bt_evt_gatt_procedure_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_procedure_completed - -/***************************************************************************//** - * - * Set the maximum size of ATT Message Transfer Units (MTU). Functionality is - * the same as @ref sl_bt_gatt_server_set_max_mtu and this setting applies to - * both GATT client and server. If the given value is too large according to the - * maximum BGAPI payload size, the system will select the maximum possible value - * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT - * client in the stack will automatically send an MTU exchange request after a - * Bluetooth connection has been established. - * - * @param[in] max_mtu @parblock - * Maximum size of Message Transfer Units (MTU) allowed - * - Range: 23 to 250 - * - * Default: 247 - * @endparblock - * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this - * command succeeds - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out); - -/***************************************************************************//** - * - * Discover all primary services of a remote GATT database. This command - * generates a unique gatt_service event for every discovered primary service. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection); - -/***************************************************************************//** - * - * Discover primary services with the specified UUID in a remote GATT database. - * This command generates unique gatt_service event for every discovered primary - * service. Received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that this GATT procedure was successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Service UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Find the services that are included by a service in a remote GATT database. - * This command generates a unique gatt_service event for each included service. - * The received @ref sl_bt_evt_gatt_procedure_completed event indicates that - * this GATT procedure was successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, - uint32_t service); - -/***************************************************************************//** - * - * Discover all characteristics of a GATT service from a remote GATT database. - * This command generates a unique gatt_characteristic event for every - * discovered characteristic. Received @ref sl_bt_evt_gatt_procedure_completed - * event indicates that this GATT procedure was successfully completed or failed - * with an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from - * remote GATT database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, - uint32_t service); - -/***************************************************************************//** - * - * Discover all characteristics of a GATT service in a remote GATT database - * having the specified UUID. This command generates a unique - * gatt_characteristic event for every discovered characteristic having the - * specified UUID. Received @ref sl_bt_evt_gatt_procedure_completed event - * indicates that this GATT procedure was successfully completed or failed with - * an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Characteristic UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from - * remote GATT database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Discover all descriptors in a remote GATT database starting from handle. It - * generates a unique gatt_descriptor event for every discovered descriptor. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, - uint16_t characteristic); - -/***************************************************************************//** - * - * Discover all descriptors of a GATT characteristic in a remote GATT database. - * It generates a unique gatt_descriptor event for every discovered descriptor. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] start GATT characteristic handle. This value is normally received - * from the gatt_characteristic event. - * @param[in] end GATT characteristic handle. This value is normally received - * from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, - uint16_t start, - uint16_t end); - -/***************************************************************************//** - * - * Enable or disable the notifications and indications sent from a remote GATT - * server. This procedure discovers a characteristic client configuration - * descriptor and writes the related configuration flags to a remote GATT - * database. A received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that this GATT procedure was successfully completed or that it failed with an - * error. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] flags Enum @ref sl_bt_gatt_client_config_flag_t. Characteristic - * client configuration flags. Values: - * - sl_bt_gatt_disable (0x0): Disable notifications and indications - * - sl_bt_gatt_notification (0x1): Notification - * - sl_bt_gatt_indication (0x2): Indication - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - @ref sl_bt_evt_gatt_characteristic_value - If an indication or - * notification has been enabled for a characteristic, this event is - * triggered whenever an indication or notification is sent by the remote - * GATT server. The triggering conditions of the GATT server are defined by - * an upper level, for example by a profile. As a result, it is possible - * that no values are ever received, or that it may take time, depending on - * how the server is configured. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, - uint16_t characteristic, - uint8_t flags); - -/***************************************************************************//** - * - * Send a confirmation to a remote GATT server after receiving a characteristic - * indication. The @ref sl_bt_evt_gatt_characteristic_value event carries the @p - * att_opcode containing @ref sl_bt_gatt_handle_value_indication (0x1d), which - * reveals that an indication has been received and must be confirmed with this - * command. The confirmation needs to be sent within 30 seconds, otherwise - * further GATT transactions are not allowed by the remote side. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection); - -/***************************************************************************//** - * - * Read the value of a characteristic from a remote GATT database. A single @ref - * sl_bt_evt_gatt_characteristic_value is generated if the characteristic value - * fits in one ATT PDU. Otherwise, more than one @ref - * sl_bt_evt_gatt_characteristic_value event is generated because the firmware - * will automatically use the Read Long Characteristic Values procedure. A - * received @ref sl_bt_evt_gatt_procedure_completed event indicates that all - * data was read successfully or that an error response was received. - * - * Note that the GATT client does not verify if the requested attribute is a - * characteristic value. Therefore, before calling this command, ensure that the - * attribute handle is for a characteristic value, for example, by performing - * characteristic discovery. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, - uint16_t characteristic); - -/***************************************************************************//** - * - * Read a partial characteristic value with a specified offset and maximum - * length from a remote GATT database. It is equivalent to @ref - * sl_bt_gatt_read_characteristic_value if both the offset and maximum length - * parameters are 0. A single @ref sl_bt_evt_gatt_characteristic_value event is - * generated if the value to read fits in one ATT PDU. Otherwise, more than one - * @ref sl_bt_evt_gatt_characteristic_value events are generated because the - * firmware will automatically use the Read Long Characteristic Values - * procedure. A received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that all data was read successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] maxlen Maximum bytes to read. If this parameter is 0, all - * characteristic values starting at a given offset will be read. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - uint16_t maxlen); - -/***************************************************************************//** - * - * Read values of multiple characteristics from a remote GATT database at once. - * The GATT server returns values in one ATT PDU as the response. If the total - * set of values is greater than (ATT_MTU - 1) bytes in length, only the first - * (ATT_MTU - 1) bytes are included. A single @ref - * sl_bt_evt_gatt_characteristic_value event is generated, in which the - * characteristic is set to 0 and data in the value parameter is a concatenation - * of characteristic values in the order they were requested. The received @ref - * sl_bt_evt_gatt_procedure_completed event indicates either that this GATT - * procedure was successfully completed or failed with an error. - * - * Use this command only for characteristics values that have a known fixed - * size, except the last one that could have variable length. - * - * When the remote GATT server is from Silicon Labs Bluetooth stack, the server - * returns ATT Invalid PDU (0x04) if this command only reads one characteristic - * value. The server returns ATT Application Error 0x80 if this command reads - * the value of a user-type characteristic. - * - * @param[in] connection Connection handle - * @param[in] characteristic_list_len Length of data in @p characteristic_list - * @param[in] characteristic_list List of uint16 characteristic handles each in - * little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - A concatenation of - * characteristic values in the order they were requested - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was either - * successfully completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, - size_t characteristic_list_len, - const uint8_t* characteristic_list); - -/***************************************************************************//** - * - * Read characteristic values of a service from a remote GATT database by giving - * the UUID of the characteristic and the handle of the service containing this - * characteristic. If multiple characteristic values are received in one ATT - * PDU, one @ref sl_bt_evt_gatt_characteristic_value event is generated for each - * value. If the first characteristic value does not fit in one ATT PDU, the - * firmware automatically uses the Read Long Characteristic Values procedure and - * generate more @ref sl_bt_evt_gatt_characteristic_value events until the value - * has been completely read. A received @ref sl_bt_evt_gatt_procedure_completed - * event indicates that all data was read successfully or that an error response - * was received. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Characteristic UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Write the value of a characteristic in a remote GATT database. If the value - * length is greater than (ATT_MTU - 3) and does not fit in one ATT PDU, "write - * long" GATT procedure is used automatically. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that all data was written - * successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Write the value of a characteristic in a remote GATT server. It does not - * generate an event. All failures on the server are ignored silently. For - * example, if an error is generated in the remote GATT server and the given - * value is not written into the database, no error message will be reported to - * the local GATT client. Note that this command can't be used to write long - * values. At most ATT_MTU - 3 number of bytes can be sent once. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Add a characteristic value to the write queue of a remote GATT server. It can - * be used when long attributes need to be written or a set of values needs to - * be written atomically. At most ATT_MTU - 5 number of bytes can be sent at one - * time. Writes are executed or canceled with the @ref - * sl_bt_gatt_execute_characteristic_value_write command. Whether the writes - * succeed or not is indicated in the response of the @ref - * sl_bt_gatt_execute_characteristic_value_write command. - * - * In all use cases where the amount of data to transfer fits into the BGAPI - * payload, use the command @ref sl_bt_gatt_write_characteristic_value to write - * long values because it transparently performs the prepare_write and - * execute_write commands. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] value_len Length of data in @p value - * @param[in] value Value to write into the specified characteristic of the - * remote GATT database - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Add a characteristic value to the write queue of a remote GATT server and - * verify whether the value was correctly received by the server. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that this GATT procedure - * was successfully completed or failed with an error. Specifically, error code - * 0x0194 (data_corrupted) will be returned if the value received from the GATT - * server's response fails to pass the reliable write verification. At most, - * ATT_MTU - 5 number of bytes can be sent at one time. Writes are executed or - * canceled with the @ref sl_bt_gatt_execute_characteristic_value_write command. - * Whether the writes succeed or not is indicated in the response of the @ref - * sl_bt_gatt_execute_characteristic_value_write command. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] value_len Length of data in @p value - * @param[in] value Value to write into the specified characteristic of the - * remote GATT database - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Commit or cancel previously queued writes to a long characteristic of a - * remote GATT server. Writes are sent to the queue with @ref - * sl_bt_gatt_prepare_characteristic_value_write command. Content, offset, and - * length of queued values are validated by this procedure. A received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that all data was written - * successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] flags Enum @ref sl_bt_gatt_execute_write_flag_t. Execute write - * flag. Values: - * - sl_bt_gatt_cancel (0x0): Cancel all queued writes - * - sl_bt_gatt_commit (0x1): Commit all queued writes - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, - uint8_t flags); - -/***************************************************************************//** - * - * Read the descriptor value of a characteristic in a remote GATT database. A - * single @ref sl_bt_evt_gatt_descriptor_value event is generated if the - * descriptor value fits in one ATT PDU. Otherwise, more than one @ref - * sl_bt_evt_gatt_descriptor_value events are generated because the firmware - * automatically uses the Read Long Characteristic Values procedure. A received - * @ref sl_bt_evt_gatt_procedure_completed event indicates that all data was - * read successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] descriptor GATT characteristic descriptor handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor_value - Descriptor value received from the - * remote GATT server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, - uint16_t descriptor); - -/***************************************************************************//** - * - * Write the value of a characteristic descriptor in a remote GATT database. If - * the value length is greater than ATT_MTU - 3 and does not fit in one ATT PDU, - * "write long" GATT procedure is used automatically. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates either that all data was - * written successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] descriptor GATT characteristic descriptor handle - * @param[in] value_len Length of data in @p value - * @param[in] value Descriptor value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, - uint16_t descriptor, - size_t value_len, - const uint8_t* value); - -/** @} */ // end addtogroup sl_bt_gatt - -/** - * @addtogroup sl_bt_gattdb GATT Database - * @{ - * - * @brief GATT Database - * - * These commands and events are used for managing the local GATT database. - * - * Many commands in this class return the handles of created attributes. These - * handles may change during commit if attributes are not created in the order - * they present in the database. For example, when creating a new service using - * the @ref sl_bt_gattdb_add_service command, the service declaration handle - * returned from this command becomes invalid later when an attribute is added - * or removed in front of this service. If the user requires that the attribute - * handles returned from these commands must remain valid after the database - * update has been committed, attributes must be created in the order they - * present in the database. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gattdb_new_session_id 0x00460020 -#define sl_bt_cmd_gattdb_add_service_id 0x01460020 -#define sl_bt_cmd_gattdb_remove_service_id 0x02460020 -#define sl_bt_cmd_gattdb_add_included_service_id 0x03460020 -#define sl_bt_cmd_gattdb_remove_included_service_id 0x04460020 -#define sl_bt_cmd_gattdb_add_uuid16_characteristic_id 0x05460020 -#define sl_bt_cmd_gattdb_add_uuid128_characteristic_id 0x06460020 -#define sl_bt_cmd_gattdb_remove_characteristic_id 0x07460020 -#define sl_bt_cmd_gattdb_add_uuid16_descriptor_id 0x08460020 -#define sl_bt_cmd_gattdb_add_uuid128_descriptor_id 0x09460020 -#define sl_bt_cmd_gattdb_remove_descriptor_id 0x0a460020 -#define sl_bt_cmd_gattdb_start_service_id 0x0b460020 -#define sl_bt_cmd_gattdb_stop_service_id 0x0c460020 -#define sl_bt_cmd_gattdb_start_characteristic_id 0x0d460020 -#define sl_bt_cmd_gattdb_stop_characteristic_id 0x0e460020 -#define sl_bt_cmd_gattdb_commit_id 0x0f460020 -#define sl_bt_cmd_gattdb_abort_id 0x10460020 -#define sl_bt_rsp_gattdb_new_session_id 0x00460020 -#define sl_bt_rsp_gattdb_add_service_id 0x01460020 -#define sl_bt_rsp_gattdb_remove_service_id 0x02460020 -#define sl_bt_rsp_gattdb_add_included_service_id 0x03460020 -#define sl_bt_rsp_gattdb_remove_included_service_id 0x04460020 -#define sl_bt_rsp_gattdb_add_uuid16_characteristic_id 0x05460020 -#define sl_bt_rsp_gattdb_add_uuid128_characteristic_id 0x06460020 -#define sl_bt_rsp_gattdb_remove_characteristic_id 0x07460020 -#define sl_bt_rsp_gattdb_add_uuid16_descriptor_id 0x08460020 -#define sl_bt_rsp_gattdb_add_uuid128_descriptor_id 0x09460020 -#define sl_bt_rsp_gattdb_remove_descriptor_id 0x0a460020 -#define sl_bt_rsp_gattdb_start_service_id 0x0b460020 -#define sl_bt_rsp_gattdb_stop_service_id 0x0c460020 -#define sl_bt_rsp_gattdb_start_characteristic_id 0x0d460020 -#define sl_bt_rsp_gattdb_stop_characteristic_id 0x0e460020 -#define sl_bt_rsp_gattdb_commit_id 0x0f460020 -#define sl_bt_rsp_gattdb_abort_id 0x10460020 - -/** - * @brief This enum defines GATT service types. - */ -typedef enum -{ - sl_bt_gattdb_primary_service = 0x0, /**< (0x0) Primary service */ - sl_bt_gattdb_secondary_service = 0x1 /**< (0x1) Secondary service */ -} sl_bt_gattdb_service_type_t; - -/** - * @brief This enum defines characteristic and descriptor value types. - */ -typedef enum -{ - sl_bt_gattdb_fixed_length_value = 0x1, /**< (0x1) A fixed-length value - managed by the local GATT - server for responding the read - and write requests of remote - GATT clients */ - sl_bt_gattdb_variable_length_value = 0x2, /**< (0x2) A variable-length value - managed by the local GATT - server for responding the read - and write requests of remote - GATT clients */ - sl_bt_gattdb_user_managed_value = 0x3 /**< (0x3) A value managed by the - user application for responding - the read and write requests of - remote GATT clients. */ -} sl_bt_gattdb_value_type_t; - -/** - * @addtogroup sl_bt_gattdb_service_property_flags GATT Service Property Flags - * @{ - * - * This enum defines GATT service property flags. - */ - -/** The service should be advertised. */ -#define SL_BT_GATTDB_ADVERTISED_SERVICE 0x1 - -/** @} */ // end GATT Service Property Flags - -/** - * @addtogroup sl_bt_gattdb_security_requirements GATT Attribute Security Requirement Flags - * @{ - * - * This enum defines the security requirement flags for GATT characteristic - * value properties. - */ - -/** The read property requires pairing and encrypted connection. */ -#define SL_BT_GATTDB_ENCRYPTED_READ 0x1 - -/** The read property requires bonding and encrypted connection. */ -#define SL_BT_GATTDB_BONDED_READ 0x2 - -/** The read property requires authenticated pairing and encrypted connection. - * */ -#define SL_BT_GATTDB_AUTHENTICATED_READ 0x4 - -/** The write property requires pairing and encrypted connection. */ -#define SL_BT_GATTDB_ENCRYPTED_WRITE 0x8 - -/** The write property requires bonding and encrypted connection. */ -#define SL_BT_GATTDB_BONDED_WRITE 0x10 - -/** The write property requires authenticated pairing and encrypted connection. - * */ -#define SL_BT_GATTDB_AUTHENTICATED_WRITE 0x20 - -/** The notification and indication properties require pairing and encrypted - * connection. */ -#define SL_BT_GATTDB_ENCRYPTED_NOTIFY 0x40 - -/** The notification and indication properties require bonding and encrypted - * connection. */ -#define SL_BT_GATTDB_BONDED_NOTIFY 0x80 - -/** The notification and indication properties require authenticated pairing and - * encrypted connection. */ -#define SL_BT_GATTDB_AUTHENTICATED_NOTIFY 0x100 - -/** @} */ // end GATT Attribute Security Requirement Flags - -/** - * @addtogroup sl_bt_gattdb_flags GATT Database Flags - * @{ - * - * This enum defines the options of GATT attribute management. - */ - -/** Do not automatically create a Client Characteristic Configuration descriptor - * when adding a characteristic that has the notify or indicate property. */ -#define SL_BT_GATTDB_NO_AUTO_CCCD 0x1 - -/** @} */ // end GATT Database Flags - -/** - * @addtogroup sl_bt_gattdb_characteristic_properties GATT Characteristic Property Flags - * @{ - * - * This enum defines the property flags for GATT characteristic values. Lower - * byte is Characteristic Properties and higher byte is Characteristic Extended - * Properties. - */ - -/** A GATT client can read the characteristic value. */ -#define SL_BT_GATTDB_CHARACTERISTIC_READ 0x2 - -/** A GATT client can write the characteristic value without a response. */ -#define SL_BT_GATTDB_CHARACTERISTIC_WRITE_NO_RESPONSE 0x4 - -/** A GATT client can write the characteristic value. */ -#define SL_BT_GATTDB_CHARACTERISTIC_WRITE 0x8 - -/** The characteristic value can be notified without acknowledgment. */ -#define SL_BT_GATTDB_CHARACTERISTIC_NOTIFY 0x10 - -/** The characteristic value can be notified with acknowledgment. */ -#define SL_BT_GATTDB_CHARACTERISTIC_INDICATE 0x20 - -/** The additional characteristic properties are defined. */ -#define SL_BT_GATTDB_CHARACTERISTIC_EXTENDED_PROPS 0x80 - -/** The characteristic value supports reliable write. */ -#define SL_BT_GATTDB_CHARACTERISTIC_RELIABLE_WRITE 0x101 - -/** @} */ // end GATT Characteristic Property Flags - -/** - * @addtogroup sl_bt_gattdb_descriptor_properties GATT Descriptor Property Flags - * @{ - * - * This enum defines the property flags for GATT characteristic descriptors. - */ - -/** A GATT client can read the descriptor value. */ -#define SL_BT_GATTDB_DESCRIPTOR_READ 0x1 - -/** A GATT client can write the descriptor value. */ -#define SL_BT_GATTDB_DESCRIPTOR_WRITE 0x2 - -/** The descriptor is local only and should be invisible to GATT clients. */ -#define SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY 0x200 - -/** @} */ // end GATT Descriptor Property Flags - -/***************************************************************************//** - * - * Start a new GATT database update session. If the operation is successful, the - * Bluetooth stack returns a session ID, with which the GATT database can be - * updated by calling other database management APIs of this class. Changes in - * the database are not immediately saved. Unsaved changes are invisible to a - * connected remote GATT client. - * - * After all changes were performed successfully, commit the changes using the - * @ref sl_bt_gattdb_commit command. The Bluetooth stack will save the changes - * and handle GATT caching as needed. Unsaved database changes can also be - * canceled by calling the @ref sl_bt_gattdb_abort command. In either case, - * after a commit or abort command is called, the current session is closed and - * the session ID becomes invalid. - * - * Only one session is allowed at a time. Error SL_STATUS_ALREADY_EXISTS is - * returned if another session has been started already. - * - * @param[out] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_new_session(uint16_t *session); - -/***************************************************************************//** - * - * Add a service into the local GATT database. When successful, the service is - * appended to the service list and is in stopped state. Use @ref - * sl_bt_gattdb_start_service command to set it visible to remote GATT clients. - * - * You are not allowed to add the Generic Attribute Profile service. If the - * application needs GATT caching, enable the feature in the configuration of - * this component and the GATT server will handle GATT caching according to the - * procedures specified by the Bluetooth core specification. - * - * @param[in] session The database update session ID - * @param[in] type Enum @ref sl_bt_gattdb_service_type_t. The service type. - * Values: - * - sl_bt_gattdb_primary_service (0x0): Primary service - * - sl_bt_gattdb_secondary_service (0x1): Secondary service - * @param[in] property Service properties. Value: 0 or bit flag @ref - * SL_BT_GATTDB_ADVERTISED_SERVICE - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid The service UUID in little endian format - * @param[out] service The service declaration attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_service(uint16_t session, - uint8_t type, - uint8_t property, - size_t uuid_len, - const uint8_t* uuid, - uint16_t *service); - -/***************************************************************************//** - * - * Remove a service and its characteristics from the local GATT database. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Add an included-service attribute to a service. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the included-service attribute is added to - * @param[in] included_service The service declaration attribute handle of the - * service to be included - * @param[out] attribute The included-service attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, - uint16_t service, - uint16_t included_service, - uint16_t *attribute); - -/***************************************************************************//** - * - * Remove an included-service attribute from a service. - * - * @param[in] session The database update session ID - * @param[in] attribute The included-service attribute handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, - uint16_t attribute); - -/***************************************************************************//** - * - * Add a 16-bits UUID characteristic to a service. On success, the - * characteristic is appended to the characteristic list of the service and it - * inherits the started or stopped state of the service. In addition, it can be - * started and stopped separately with the @ref - * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic - * commands. - * - * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the - * stack will automatically add a Client Characteristic Configuration descriptor - * to this characteristic when it has the notify or indicate property. If @ref - * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the - * descriptor separately as needed. - * - * A Characteristic Extended Properties descriptor is automatically added if the - * reliable write property is set. - * - * Use the @ref sl_bt_gattdb_add_uuid128_characteristic command to add a - * 128-bits UUID characteristic. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the characteristic is added to - * @param[in] property Characteristic value properties. Value: bitmask of @ref - * sl_bt_gattdb_characteristic_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the characteristic - * value. - * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. - * @param[in] uuid The 16-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the characteristic value. Ignored if - * @p value_type is @ref sl_bt_gattdb_user_managed_value. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial characteristic value. Length of this value must - * be less than or equal to @p maxlen. Ignored if @p value_type is @ref - * sl_bt_gattdb_user_managed_value. - * @param[out] characteristic The characteristic value attribute handle. This - * handle is ensured valid in current session. It may change after the session - * if attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic); - -/***************************************************************************//** - * - * Add a 128-bits UUID characteristic to a service. When successful, the - * characteristic is appended to the characteristic list of the service and - * inherits the started or stopped state of the service. Additionally, it can be - * started and stopped separately with the @ref - * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic - * commands. - * - * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the - * stack will automatically add a Client Characteristic Configuration descriptor - * to this characteristic when it has the notify or indicate property. If @ref - * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the - * descriptor separately as needed. - * - * A Characteristic Extended Properties descriptor is automatically added if the - * reliable write property is set. - * - * Use the @ref sl_bt_gattdb_add_uuid16_characteristic command to add a 16-bits - * UUID characteristic. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the characteristic is added to - * @param[in] property Characteristic value properties. Value: bitmask of @ref - * sl_bt_gattdb_characteristic_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the characteristic - * value. - * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. - * @param[in] uuid The 128-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the characteristic value. Ignored if - * @p value_type is @ref sl_bt_gattdb_user_managed_value. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial characteristic value. Length of this value must - * be less than or equal to @p maxlen. Ignored if @p value_type is @ref - * sl_bt_gattdb_user_managed_value. - * @param[out] characteristic The characteristic value attribute handle. This - * handle is ensured valid in current session. It may change after the session - * if attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic); - -/***************************************************************************//** - * - * Remove a characteristic and its descriptors from a service. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Add a 16-bits UUID descriptor to a characteristic. When successful, the - * descriptor is appended to the descriptor list of the characteristic and - * inherits the started or stopped state of the characteristic. - * - * This command does not support adding Characteristic Extended Properties - * descriptors. This descriptor is automatically added if the characteristic - * value has the reliable-write property or when a Characteristic User - * Description descriptor is added and the user description has the write - * property. - * - * Use the @ref sl_bt_gattdb_add_uuid128_descriptor command to add a 128-bits - * UUID descriptor. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic the descriptor is added to - * @param[in] property The descriptor properties. Value: bitmask of @ref - * sl_bt_gattdb_descriptor_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the descriptor. - * @param[in] uuid The 16-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Ignored if this is a Client Characteristic Configuration descriptor. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p - * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client - * Characteristic Configuration descriptor. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial descriptor value. Length of this value must be - * less than or equal to @p maxlen. Ingored if value type is @ref - * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic - * Configuration descriptor. - * @param[out] descriptor The descriptor attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor); - -/***************************************************************************//** - * - * Add a 128-bits UUID descriptor to a characteristic. When successful, the - * descriptor is appended to the descriptor list of the characteristic and - * inherits the started or stopped state of the characteristic. - * - * This command does not support adding Characteristic Extended Properties - * descriptors. This descriptor is automatically added if the characteristic - * value has the reliable-write property or when a Characteristic User - * Description descriptor is added and the user description has the write - * property. - * - * Use the @ref sl_bt_gattdb_add_uuid16_descriptor command to add a 16-bits UUID - * descriptor. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic the descriptor is added to - * @param[in] property Bitmask of characteristic descriptor properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the descriptor. - * @param[in] uuid The 128-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Ignored if this is a Client Characteristic Configuration descriptor. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p - * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client - * Characteristic Configuration descriptor. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial descriptor value. Length of this value must be - * less than or equal to @p maxlen. Ignored if value type is @ref - * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic - * Configuration descriptor. - * @param[out] descriptor The descriptor attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor); - -/***************************************************************************//** - * - * Remove a descriptor from a characteristic. - * - * @param[in] session The database update session ID - * @param[in] descriptor The descriptor handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, - uint16_t descriptor); - -/***************************************************************************//** - * - * Start a service, so that the service and its attributes including - * characteristics and descriptors become visible to remote GATT clients after - * this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Stop a service, so that the service and its attributes including - * characteristics and descriptors become invisible to remote GATT clients after - * this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Start a characteristic, so that the characteristic and its attributes become - * visible to remote GATT clients after this change has been committed. - * SL_STATUS_INVALID_STATE error is returned if the parent service is not - * started. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Stop a characteristic, so that the characteristic and its attributes become - * invisible to remote GATT clients after this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Save all changes performed in the current session and close the session. The - * stack will assign final handles to new and affected attributes and handle - * GATT caching as needed. The stack removes the client characteristic - * configurations of non-connected GATT clients except the service-changed - * configuration. For connected GATT clients during this database change, the - * stack removes the configurations to the removed characteristics. The session - * ID, temporary attribute handles returned during this session, and other - * existing attribute handles that are after newly added or removed attributes - * are invalidated. - * - * Some attribute handles returned in this session may become invalid if - * attributes are not created in the order they present in the database. In this - * case, attribute handle cache of the database in the user application must be - * refreshed to avoid accidentally using an invalidated handle in subsequent - * operations. - * - * @param[in] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_commit(uint16_t session); - -/***************************************************************************//** - * - * Cancel all changes performed in the current session and close the session. - * The database remains in the same state it was in just before the session was - * started. The session ID and all temporary attribute handles returned during - * this session are invalidated. - * - * @param[in] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_abort(uint16_t session); - -/** @} */ // end addtogroup sl_bt_gattdb - -/** - * @addtogroup sl_bt_gatt_server GATT Server - * @{ - * - * @brief GATT Server - * - * These commands and events are used for accessing to the local GATT server and - * database. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gatt_server_set_max_mtu_id 0x0a0a0020 -#define sl_bt_cmd_gatt_server_get_mtu_id 0x0b0a0020 -#define sl_bt_cmd_gatt_server_find_attribute_id 0x060a0020 -#define sl_bt_cmd_gatt_server_read_attribute_value_id 0x000a0020 -#define sl_bt_cmd_gatt_server_read_attribute_type_id 0x010a0020 -#define sl_bt_cmd_gatt_server_write_attribute_value_id 0x020a0020 -#define sl_bt_cmd_gatt_server_send_user_read_response_id 0x030a0020 -#define sl_bt_cmd_gatt_server_send_user_write_response_id 0x040a0020 -#define sl_bt_cmd_gatt_server_send_notification_id 0x0f0a0020 -#define sl_bt_cmd_gatt_server_send_indication_id 0x100a0020 -#define sl_bt_cmd_gatt_server_notify_all_id 0x110a0020 -#define sl_bt_cmd_gatt_server_read_client_configuration_id 0x120a0020 -#define sl_bt_cmd_gatt_server_send_user_prepare_write_response_id 0x140a0020 -#define sl_bt_cmd_gatt_server_set_capabilities_id 0x080a0020 -#define sl_bt_cmd_gatt_server_enable_capabilities_id 0x0c0a0020 -#define sl_bt_cmd_gatt_server_disable_capabilities_id 0x0d0a0020 -#define sl_bt_cmd_gatt_server_get_enabled_capabilities_id 0x0e0a0020 -#define sl_bt_cmd_gatt_server_read_client_supported_features_id 0x150a0020 -#define sl_bt_rsp_gatt_server_set_max_mtu_id 0x0a0a0020 -#define sl_bt_rsp_gatt_server_get_mtu_id 0x0b0a0020 -#define sl_bt_rsp_gatt_server_find_attribute_id 0x060a0020 -#define sl_bt_rsp_gatt_server_read_attribute_value_id 0x000a0020 -#define sl_bt_rsp_gatt_server_read_attribute_type_id 0x010a0020 -#define sl_bt_rsp_gatt_server_write_attribute_value_id 0x020a0020 -#define sl_bt_rsp_gatt_server_send_user_read_response_id 0x030a0020 -#define sl_bt_rsp_gatt_server_send_user_write_response_id 0x040a0020 -#define sl_bt_rsp_gatt_server_send_notification_id 0x0f0a0020 -#define sl_bt_rsp_gatt_server_send_indication_id 0x100a0020 -#define sl_bt_rsp_gatt_server_notify_all_id 0x110a0020 -#define sl_bt_rsp_gatt_server_read_client_configuration_id 0x120a0020 -#define sl_bt_rsp_gatt_server_send_user_prepare_write_response_id 0x140a0020 -#define sl_bt_rsp_gatt_server_set_capabilities_id 0x080a0020 -#define sl_bt_rsp_gatt_server_enable_capabilities_id 0x0c0a0020 -#define sl_bt_rsp_gatt_server_disable_capabilities_id 0x0d0a0020 -#define sl_bt_rsp_gatt_server_get_enabled_capabilities_id 0x0e0a0020 -#define sl_bt_rsp_gatt_server_read_client_supported_features_id 0x150a0020 - -/** - * @brief These values define whether the server is to sent notifications or - * indications to a remote GATT server. - */ -typedef enum -{ - sl_bt_gatt_server_disable = 0x0, /**< (0x0) Disable - notifications and - indications. */ - sl_bt_gatt_server_notification = 0x1, /**< (0x1) The - characteristic value - shall be notified. */ - sl_bt_gatt_server_indication = 0x2, /**< (0x2) The - characteristic value - shall be indicated. */ - sl_bt_gatt_server_notification_and_indication = 0x3 /**< (0x3) The - characteristic value - notification and - indication are - enabled, application - decides which one to - send. */ -} sl_bt_gatt_server_client_configuration_t; - -/** - * @brief These values describe whether the characteristic client configuration - * was changed or whether a characteristic confirmation was received. - */ -typedef enum -{ - sl_bt_gatt_server_client_config = 0x1, /**< (0x1) Characteristic client - configuration has been changed. */ - sl_bt_gatt_server_confirmation = 0x2 /**< (0x2) Characteristic confirmation - has been received. */ -} sl_bt_gatt_server_characteristic_status_flag_t; - -/** - * @addtogroup sl_bt_evt_gatt_server_attribute_value sl_bt_evt_gatt_server_attribute_value - * @{ - * @brief Indicates that the value of an attribute in the local GATT database - * was changed by a remote GATT client - * - * The parameter @p att_opcode describes which GATT procedure was used to change - * the value. - */ - -/** @brief Identifier of the attribute_value event */ -#define sl_bt_evt_gatt_server_attribute_value_id 0x000a00a0 - -/***************************************************************************//** - * @brief Data structure of the attribute_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_attribute_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t attribute; /**< Attribute Handle */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which the - value was received. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Value */ -}); - -typedef struct sl_bt_evt_gatt_server_attribute_value_s sl_bt_evt_gatt_server_attribute_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_attribute_value - -/** - * @addtogroup sl_bt_evt_gatt_server_user_read_request sl_bt_evt_gatt_server_user_read_request - * @{ - * @brief Indicates that a remote GATT client is attempting to read a value of - * an attribute from the local GATT database, where the attribute was defined in - * the GATT database XML file to have the type="user" - * - * The parameter @p att_opcode informs which GATT procedure was used to read the - * value. The application needs to respond to this request by using the @ref - * sl_bt_gatt_server_send_user_read_response command within 30 seconds, - * otherwise further GATT transactions are not allowed by the remote side. - */ - -/** @brief Identifier of the user_read_request event */ -#define sl_bt_evt_gatt_server_user_read_request_id 0x010a00a0 - -/***************************************************************************//** - * @brief Data structure of the user_read_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_user_read_request_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which the - value was received. */ - uint16_t offset; /**< Value offset */ -}); - -typedef struct sl_bt_evt_gatt_server_user_read_request_s sl_bt_evt_gatt_server_user_read_request_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_read_request - -/** - * @addtogroup sl_bt_evt_gatt_server_user_write_request sl_bt_evt_gatt_server_user_write_request - * @{ - * @brief Indicates that a remote GATT client is attempting to write a value of - * an attribute into the local GATT database, where the attribute was defined in - * the GATT database XML file to have the type="user" - * - * The parameter @p att_opcode informs which attribute procedure was used to - * write the value. If the @p att_opcode is @ref sl_bt_gatt_write_request (see - * @ref sl_bt_gatt_att_opcode_t), the application needs to respond to this - * request by using the @ref sl_bt_gatt_server_send_user_write_response command - * within 30 seconds, otherwise further GATT transactions are not allowed by the - * remote side. If the @p att_opcode is @ref sl_bt_gatt_prepare_write_request, - * the application needs to respond to this request by using the @ref - * sl_bt_gatt_server_send_user_prepare_write_response command within 30 seconds, - * otherwise further GATT transactions are not allowed by the remote side. If - * the value of @p att_opcode is @ref sl_bt_gatt_execute_write_request, it - * indicates that there was one or more prepare writes earlier and now the GATT - * server is processing the execute write, the value of @p characteristic is set - * to 0 and should be ignored. The event @ref - * sl_bt_evt_gatt_server_execute_write_completed will be emitted after - * responding to @ref sl_bt_gatt_execute_write_request by using @ref - * sl_bt_gatt_server_send_user_write_response. - */ - -/** @brief Identifier of the user_write_request event */ -#define sl_bt_evt_gatt_server_user_write_request_id 0x020a00a0 - -/***************************************************************************//** - * @brief Data structure of the user_write_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_user_write_request_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which - the value was received. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Value */ -}); - -typedef struct sl_bt_evt_gatt_server_user_write_request_s sl_bt_evt_gatt_server_user_write_request_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_write_request - -/** - * @addtogroup sl_bt_evt_gatt_server_characteristic_status sl_bt_evt_gatt_server_characteristic_status - * @{ - * @brief Indicates either that a local Client Characteristic Configuration - * descriptor was changed by the remote GATT client, or that a confirmation from - * the remote GATT client was received upon a successful reception of the - * indication - * - * A confirmation by the remote GATT client should be received within 30 seconds - * after an indication was sent with the @ref sl_bt_gatt_server_send_indication - * command, otherwise further GATT transactions over this connection are not - * allowed by the stack. - */ - -/** @brief Identifier of the characteristic_status event */ -#define sl_bt_evt_gatt_server_characteristic_status_id 0x030a00a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic_status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_characteristic_status_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the - gatt_characteristic event. */ - uint8_t status_flags; /**< Enum @ref - sl_bt_gatt_server_characteristic_status_flag_t. - Describes whether Client Characteristic - Configuration was changed or if a - confirmation was received. Values: - - sl_bt_gatt_server_client_config - (0x1): Characteristic client - configuration has been changed. - - sl_bt_gatt_server_confirmation - (0x2): Characteristic confirmation - has been received. */ - uint16_t client_config_flags; /**< Enum @ref - sl_bt_gatt_server_client_configuration_t. - This field carries the new value of the - Client Characteristic Configuration. If the - status_flags is 0x2 (confirmation - received), the value of this field can be - ignored. */ - uint16_t client_config; /**< The handle of client-config descriptor. */ -}); - -typedef struct sl_bt_evt_gatt_server_characteristic_status_s sl_bt_evt_gatt_server_characteristic_status_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_characteristic_status - -/** - * @addtogroup sl_bt_evt_gatt_server_execute_write_completed sl_bt_evt_gatt_server_execute_write_completed - * @{ - * @brief Indicates that the execute write command from a remote GATT client has - * completed with the given result - */ - -/** @brief Identifier of the execute_write_completed event */ -#define sl_bt_evt_gatt_server_execute_write_completed_id 0x040a00a0 - -/***************************************************************************//** - * @brief Data structure of the execute_write_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_execute_write_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t result; /**< Execute write result */ -}); - -typedef struct sl_bt_evt_gatt_server_execute_write_completed_s sl_bt_evt_gatt_server_execute_write_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_execute_write_completed - -/** - * @addtogroup sl_bt_evt_gatt_server_indication_timeout sl_bt_evt_gatt_server_indication_timeout - * @{ - * @brief Indicates confirmation from the remote GATT client has not been - * received within 30 seconds after an indication was sent - * - * Furthermore, the stack does not allow GATT transactions over this connection. - */ - -/** @brief Identifier of the indication_timeout event */ -#define sl_bt_evt_gatt_server_indication_timeout_id 0x050a00a0 - -/***************************************************************************//** - * @brief Data structure of the indication_timeout event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_indication_timeout_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_gatt_server_indication_timeout_s sl_bt_evt_gatt_server_indication_timeout_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_indication_timeout - -/** - * @addtogroup sl_bt_evt_gatt_server_notification_tx_completed sl_bt_evt_gatt_server_notification_tx_completed - * @{ - * @brief Indicates that one or more GATT notifications have been transmitted. - * - * By default, this event is not enabled on Bluetooth connections due to - * additional resource usages - * - * Following enablers are required to enable the Bluetooth stack's functionality - * for supporting this event, - * - Include feature bluetooth_feature_resource_report in the application - * project. - * - Use command @ref sl_bt_resource_enable_connection_tx_report to enable - * data packet TX status reports before this Bluetooth connection is - * established. - */ - -/** @brief Identifier of the notification_tx_completed event */ -#define sl_bt_evt_gatt_server_notification_tx_completed_id 0x060a00a0 - -/***************************************************************************//** - * @brief Data structure of the notification_tx_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_notification_tx_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t count; /**< Number of notifications that have been transmitted */ -}); - -typedef struct sl_bt_evt_gatt_server_notification_tx_completed_s sl_bt_evt_gatt_server_notification_tx_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_notification_tx_completed - -/***************************************************************************//** - * - * Set the maximum size of ATT Message Transfer Units (MTU). The functionality - * is the same as @ref sl_bt_gatt_set_max_mtu and this setting applies to both - * GATT client and server. If the given value is too large according to the - * maximum BGAPI payload size, the system will select the maximum possible value - * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT - * client in the stack will automatically send an MTU exchange request after a - * Bluetooth connection was established. - * - * @param[in] max_mtu @parblock - * Maximum size of Message Transfer Units (MTU) allowed - * - Range: 23 to 250 - * - * Default: 247 - * @endparblock - * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this - * command succeeded - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, - uint16_t *max_mtu_out); - -/***************************************************************************//** - * - * Get the size of ATT Message Transfer Units (MTU) for a connection. - * - * @param[in] connection Connection handle - * @param[out] mtu The maximum ATT_MTU used by the connection - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu); - -/***************************************************************************//** - * - * Find attributes of a certain type from a local GATT database. The type is - * usually given as a 16-bit or 128-bit UUID in little endian format. - * - * @param[in] start Search start handle - * @param[in] type_len Length of data in @p type - * @param[in] type The attribute type UUID - * @param[out] attribute Attribute handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, - size_t type_len, - const uint8_t* type, - uint16_t *attribute); - -/***************************************************************************//** - * - * Read the value of an attribute from a local GATT database. Only (maximum - * BGAPI payload size - 3) amount of data can be read at once. The application - * can continue reading with increased offset value if it receives (maximum - * BGAPI payload size - 3) number of bytes. - * - * @param[in] attribute Attribute handle - * @param[in] offset Value offset - * @param[in] max_value_size Size of output buffer passed in @p value - * @param[out] value_len On return, set to the length of output data written to - * @p value - * @param[out] value The attribute value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, - uint16_t offset, - size_t max_value_size, - size_t *value_len, - uint8_t *value); - -/***************************************************************************//** - * - * Read the type of an attribute from a local GATT database. The type is a UUID, - * usually 16 or 128 bits long in little endian format. - * - * @param[in] attribute Attribute handle - * @param[in] max_type_size Size of output buffer passed in @p type - * @param[out] type_len On return, set to the length of output data written to - * @p type - * @param[out] type The attribute type UUID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, - size_t max_type_size, - size_t *type_len, - uint8_t *type); - -/***************************************************************************//** - * - * Write the value of an attribute in the local GATT database. Writing the value - * of a characteristic of the local GATT database will not trigger notifications - * or indications to the remote GATT client if the characteristic has a property - * to indicate or notify and the client has enabled notification or indication. - * Notifications and indications are sent to the remote GATT client using @ref - * sl_bt_gatt_server_send_notification or @ref sl_bt_gatt_server_send_indication - * commands. - * - * @param[in] attribute Attribute handle - * @param[in] offset Value offset - * @param[in] value_len Length of data in @p value - * @param[in] value Value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, - uint16_t offset, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_read_request event. The - * response needs to be sent within 30 seconds, otherwise no more GATT - * transactions are allowed by the remote side. If attr_errorcode is set to 0, - * the characteristic value is sent to the remote GATT client in the standard - * way. Other attr_errorcode values will cause the local GATT server to send an - * attribute protocol error response instead of the actual data. Maximum number - * of bytes this command can send depends on the value of parameter att_opcode - * in @ref sl_bt_evt_gatt_server_user_read_request event: - * - ATT_MTU - 1 if the opcode is @ref sl_bt_gatt_read_request or @ref - * sl_bt_gatt_read_blob_request - * - ATT_MTU - 4 if the opcode is @ref sl_bt_gatt_read_by_type_request - * - * If the data length in @p value exceeds the limit, the first maximum number of - * bytes will be sent and rest data is ignored. The actual number of bytes that - * was sent is retruned in the response of this command. - * - * The client will continue reading by sending a new read blob request with an - * increased offset value if it receives the maximum amount of attribute data - * the read respond packet can contain. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle received in the @ref - * sl_bt_evt_gatt_server_user_read_request event. - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value to send to the GATT client. Ignored if - * att_errorcode is not 0. - * @param[out] sent_len The length of data sent to the remote GATT client - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when - * parameter @p att_opcode in the event is @ref sl_bt_gatt_write_request or @ref - * sl_bt_gatt_execute_write_request (see @ref sl_bt_gatt_att_opcode_t). The - * response needs to be sent within 30 seconds, otherwise no more GATT - * transactions are allowed by the remote side. When responding to @ref - * sl_bt_gatt_execute_write_request, the value of parameter @p characteristic is - * ignored. If attr_errorcode is set to 0, the ATT protocol's write response is - * sent to indicate to the remote GATT client that the write operation was - * processed successfully. Other values will cause the local GATT server to send - * an ATT protocol error response. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle received in the @ref - * sl_bt_evt_gatt_server_user_write_request event - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode); - -/***************************************************************************//** - * - * Send a notification to a remote GATT client. At most, ATT_MTU - 3 number of - * bytes can be sent in a notification. An error SL_STATUS_COMMAND_TOO_LONG is - * returned if the value length exceeds ATT_MTU - 3. - * - * A notification is sent only if the client has enabled it by setting the - * corresponding flag to the Client Characteristic Configuration descriptor. The - * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not - * have the notification property. The error SL_STATUS_INVALID_STATE is returned - * if the client has not enabled the notification. - * - * @param[in] connection A handle of the connection over which the notification - * is sent. - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be notified - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send an indication to a remote GATT client. At most, ATT_MTU - 3 number of - * bytes can be sent in an indication. An error SL_STATUS_COMMAND_TOO_LONG is - * returned if the value length exceeds ATT_MTU - 3. - * - * An indication is sent only if the client has enabled it by setting the - * corresponding flag to the Client Characteristic Configuration descriptor. The - * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not - * have the indication property. The error SL_STATUS_INVALID_STATE is returned - * if the client has not enabled the indication. - * - * A new indication to a GATT client can't be sent until an outstanding - * indication procedure with the same client has completed. The procedure is - * completed when a confirmation from the client is received. The confirmation - * is indicated by @ref sl_bt_evt_gatt_server_characteristic_status. - * - * The error SL_STATUS_IN_PROGRESS is returned if an indication procedure with - * the same client is outstanding. Always wait for confirmation for previous - * indication before sending a new indication. - * - * @param[in] connection A handle of the connection over which the indication is - * sent. - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be indicated - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_server_characteristic_status - This event is - * triggered after the confirmation from the client is received. - * - @ref sl_bt_evt_gatt_server_indication_timeout - This event indicates - * confirmation from the remote GATT client has not been received within 30 - * seconds after an indication was sent. Further GATT transactions over this - * connection are not allowed by the stack. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send notifications or indications to all connected remote GATT clients. At - * most, ATT_MTU - 3 number of bytes can be sent in a notification or - * indication. If the value length exceeds the limit on a connection, the first - * ATT_MTU - 3 bytes will be sent and rest of data is ignored. - * - * A notification or indication is sent only if the client has enabled it by - * setting the corresponding flag to the Client Characteristic Configuration - * descriptor. If the Client Characteristic Configuration descriptor supports - * both notifications and indications, the stack will always send a notification - * even when the client has enabled both. - * - * A new indication to a GATT client can't be sent until an outstanding - * indication procedure with the same client has completed, and the operation - * will continue for the next client. The procedure is completed when a - * confirmation from the client is received. The confirmation is indicated by - * @ref sl_bt_evt_gatt_server_characteristic_status. - * - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be notified or indicated - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Read client characteristic configuration of a remote GATT client. - * - * @param[in] connection A handle of the connection to a remote client. - * @param[in] characteristic Characteristic handle - * @param[out] client_config_flags Enum @ref - * sl_bt_gatt_server_client_configuration_t. Client characteristic - * configuration of a remote client. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, - uint16_t characteristic, - uint16_t *client_config_flags); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when - * parameter @p att_opcode in the event is @ref sl_bt_gatt_prepare_write_request - * (see @ref sl_bt_gatt_att_opcode_t). The response needs to be sent within 30 - * seconds, otherwise no more GATT transactions are allowed by the remote side. - * If @p att_errorcode is set to 0, the ATT protocol's prepare write response is - * sent to indicate to the remote GATT client that the write operation was - * processed successfully. Other values will cause the local GATT server to send - * an ATT protocol error response. The application should set values of - * parameters @p offset and @p value to identical values from the @ref - * sl_bt_evt_gatt_server_user_write_request event. The values will be verified - * on the client side in case the request is a reliable write (by Bluetooth Core - * Specification Volume 3, Part G, 4.9.5). - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * @param[in] offset Value offset - * @param[in] value_len Length of data in @p value - * @param[in] value Value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - uint16_t offset, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Reset capabilities that should be enabled by the GATT database. A service is - * visible to remote GATT clients if at least one of its capabilities is - * enabled. The same applies to a characteristic and its attributes. Capability - * identifiers and their corresponding bit flag values are in the auto-generated - * database header file. See UG118: Blue Gecko Bluetooth Profile Toolkit - * Developer's Guide for how to declare capabilities in the GATT database. - * - * Changing the capabilities of a database effectively causes a database change - * (attributes being added or removed) from a remote GATT client point of view. - * If the database has a Generic Attribute service and Service Changed - * characteristic, the stack will monitor the local database change status and - * manage service changed indications for a GATT client that has enabled the - * indication configuration of the Service Changed characteristic. - * - * @param[in] caps Bit flags of capabilities to reset. Value 0 sets the default - * database capabilities. - * @param[in] reserved Use the value 0 on this reserved field. Do not use - * none-zero values because they are reserved for future use. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, - uint32_t reserved); - -/***************************************************************************//** - * - * Enable additional capabilities in the local GATT database. Already enabled - * capabilities keep unchanged after this command. See @ref - * sl_bt_gatt_server_set_capabilities for more information. - * - * @param[in] caps Capabilities to enable - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps); - -/***************************************************************************//** - * - * Disable the given capabilities in the local GATT database. See @ref - * sl_bt_gatt_server_set_capabilities for more information. - * - * @param[in] caps Capabilities to disable - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps); - -/***************************************************************************//** - * - * Get capabilities currently enabled in the local GATT database. - * - * @param[out] caps Enabled capabilities - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps); - -/***************************************************************************//** - * - * Read client supported features of a remote GATT client. - * - * @param[in] connection A handle of the connection to a remote client. - * @param[out] client_features Bit field describing client supported features of - * a remote client. See Bluetooth specification Vol 3, Part G, 7.2 for the - * values. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, - uint8_t *client_features); - -/** @} */ // end addtogroup sl_bt_gatt_server - -/** - * @addtogroup sl_bt_nvm NVM - * @{ - * - * @brief NVM - * - * Provide an interface to manage user data objects (key/value pairs) in the - * flash memory. User data stored within the flash memory is persistent across - * reset and power cycling of the device. Because Bluetooth bondings are also - * stored in the flash area, in addition to the flash storage size, the space - * available for user data also depends on the number of bondings the device has - * at the time. - * - * On EFR32[B|M]G1x devices, either PS Store or NVM3 data storage driver can be - * used. PS Store is supported by the Bluetooth stack only. Using NVM3 is - * recommended if the device needs to support Dynamic Multiple Protocol (DMP). - * On EFR32[B|M]G2x devices, only NVM3 is supported. When NVM3 is used, - * applications can also use the NVM3 APIs directly. - * - * In PS Store, the flash storage size is fixed at 2048 bytes. The maximum data - * object size associated to a key is 56 bytes. A Bluetooth bonding uses at - * maximum 138 bytes for secure connections and 174 bytes for legacy pairing. - * - * In NVM3, the flash store size is configurable and the minimum is 3 flash - * pages. The maximum data object size is configurable up to 4096 bytes. A - * Bluetooth bonding uses maximum 110 bytes for secure connections and 138 bytes - * for legacy pairing. For more details, see AN1135 "Using Third Generation - * NonVolatile Memory (NVM3) Data Storage". - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_nvm_save_id 0x020d0020 -#define sl_bt_cmd_nvm_load_id 0x030d0020 -#define sl_bt_cmd_nvm_erase_id 0x040d0020 -#define sl_bt_cmd_nvm_erase_all_id 0x010d0020 -#define sl_bt_rsp_nvm_save_id 0x020d0020 -#define sl_bt_rsp_nvm_load_id 0x030d0020 -#define sl_bt_rsp_nvm_erase_id 0x040d0020 -#define sl_bt_rsp_nvm_erase_all_id 0x010d0020 - -/** - * @addtogroup sl_bt_nvm_keys Defined Keys - * @{ - * - * Define keys - */ - -/** Crystal tuning value override */ -#define SL_BT_NVM_KEY_CTUNE 0x32 - -/** @} */ // end Defined Keys - -/***************************************************************************//** - * - * Store a value into the specified NVM key. Allowed NVM keys are in range from - * 0x4000 to 0x407F. At most, 56 bytes user data can be stored in one NVM key. - * The error code 0x018a (command_too_long) is returned if the value data is - * more than 56 bytes. - * - * @param[in] key NVM key - * @param[in] value_len Length of data in @p value - * @param[in] value Value to store into the specified NVM key - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_save(uint16_t key, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Retrieve the value of the specified NVM key. - * - * @param[in] key NVM key of the value to be retrieved - * @param[in] max_value_size Size of output buffer passed in @p value - * @param[out] value_len On return, set to the length of output data written to - * @p value - * @param[out] value The returned value of the specified NVM key - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_load(uint16_t key, - size_t max_value_size, - size_t *value_len, - uint8_t *value); - -/***************************************************************************//** - * - * Delete a single NVM key and its value from the persistent store. - * - * @param[in] key NVM key to delete - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_erase(uint16_t key); - -/***************************************************************************//** - * - * Delete all NVM keys and their corresponding values. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_erase_all(); - -/** @} */ // end addtogroup sl_bt_nvm - -/** - * @addtogroup sl_bt_test Testing Commands - * @{ - * - * @brief Testing Commands - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_test_dtm_tx_v4_id 0x030e0020 -#define sl_bt_cmd_test_dtm_tx_cw_id 0x040e0020 -#define sl_bt_cmd_test_dtm_rx_id 0x010e0020 -#define sl_bt_cmd_test_dtm_end_id 0x020e0020 -#define sl_bt_rsp_test_dtm_tx_v4_id 0x030e0020 -#define sl_bt_rsp_test_dtm_tx_cw_id 0x040e0020 -#define sl_bt_rsp_test_dtm_rx_id 0x010e0020 -#define sl_bt_rsp_test_dtm_end_id 0x020e0020 - -/** - * @brief Test packet types supported by the stack - */ -typedef enum -{ - sl_bt_test_pkt_prbs9 = 0x0, /**< (0x0) PRBS9 packet payload */ - sl_bt_test_pkt_11110000 = 0x1, /**< (0x1) 11110000 packet payload */ - sl_bt_test_pkt_10101010 = 0x2, /**< (0x2) 10101010 packet payload */ - sl_bt_test_pkt_11111111 = 0x4, /**< (0x4) 11111111 packet payload */ - sl_bt_test_pkt_00000000 = 0x5, /**< (0x5) 00000000 packet payload */ - sl_bt_test_pkt_00001111 = 0x6, /**< (0x6) 00001111 packet payload */ - sl_bt_test_pkt_01010101 = 0x7, /**< (0x7) 01010101 packet payload */ - sl_bt_test_pkt_pn9 = 0xfd, /**< (0xfd) PN9 continuously modulated output */ - sl_bt_test_pkt_carrier = 0xfe /**< (0xfe) Unmodulated carrier */ -} sl_bt_test_packet_type_t; - -/** - * @brief Test PHY types - */ -typedef enum -{ - sl_bt_test_phy_1m = 0x1, /**< (0x1) 1M PHY */ - sl_bt_test_phy_2m = 0x2, /**< (0x2) 2M PHY */ - sl_bt_test_phy_125k = 0x3, /**< (0x3) 125k Coded PHY */ - sl_bt_test_phy_500k = 0x4 /**< (0x4) 500k Coded PHY */ -} sl_bt_test_phy_t; - -/** - * @addtogroup sl_bt_evt_test_dtm_completed sl_bt_evt_test_dtm_completed - * @{ - * @brief Indicates that the radio has processed a test start or end command - * - * The @p result parameter indicates the success of the command. - * - * After the receiver or transmitter test is stopped, the @p number_of_packets - * parameter in this event indicates the number of received or transmitted - * packets. - */ - -/** @brief Identifier of the dtm_completed event */ -#define sl_bt_evt_test_dtm_completed_id 0x000e00a0 - -/***************************************************************************//** - * @brief Data structure of the dtm_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_test_dtm_completed_s -{ - uint16_t result; /**< Command result */ - uint16_t number_of_packets; /**< Number of packets - - Only valid for @ref sl_bt_test_dtm_end - command. */ -}); - -typedef struct sl_bt_evt_test_dtm_completed_s sl_bt_evt_test_dtm_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_test_dtm_completed - -/***************************************************************************//** - * - * Start a transmitter test against a separate Bluetooth tester device. When the - * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event - * is triggered. This event indicates whether the test started successfully. - * - * In the transmitter test, the device sends packets continuously with a fixed - * interval. The type and length of each packet is set by @p packet_type and @p - * length parameters. The parameter @p phy specifies which PHY is used to - * transmit the packets. All devices support at least 1M PHY. A special packet - * type, test_pkt_carrier , can be used to transmit continuous - * unmodulated carrier. The length field is ignored in this mode. As this - * command has the limitation within the value of @p power_level, use of @ref - * sl_bt_test_dtm_tx_cw for custom waves is recommended. - * - * Stop the test using the @ref sl_bt_test_dtm_end command. - * - * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to - * transmit. Values: - * - sl_bt_test_pkt_prbs9 (0x0): PRBS9 packet payload - * - sl_bt_test_pkt_11110000 (0x1): 11110000 packet payload - * - sl_bt_test_pkt_10101010 (0x2): 10101010 packet payload - * - sl_bt_test_pkt_11111111 (0x4): 11111111 packet payload - * - sl_bt_test_pkt_00000000 (0x5): 00000000 packet payload - * - sl_bt_test_pkt_00001111 (0x6): 00001111 packet payload - * - sl_bt_test_pkt_01010101 (0x7): 01010101 packet payload - * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output - * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier - * @param[in] length @parblock - * Packet length in bytes - * - * Range: 0-255 - * @endparblock - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * @param[in] power_level @parblock - * TX power level in unit dBm. Values: - * - -127 to +20: Use specified or the nearest TX power level. The - * minimum -127 dBm is specified in the Bluetooth specification. However, - * a device may not support this low TX power. In addition, only some - * devices support 20 dBm TX power. Effective TX power will be limited by - * the global system TX power that can be set with the @ref - * sl_bt_system_set_tx_power command. - * - 0x7E: Use minimum TX power level the device supports. - * - 0x7F: Use the smallest of the maximum TX power level the device - * supports and the global maximum TX power setting in stack. - * - * For continuous unmodulated carrier mode, the values are set in 0.1 dBm - * unit. If the value exceeds the range of power level value allowed by the - * device, the command will adjust the power level to the closest minimum or - * maximum value. - * @endparblock - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, - uint8_t length, - uint8_t channel, - uint8_t phy, - int8_t power_level); - -/***************************************************************************//** - * - * Start a transmitter test for a custom wave. When the command is processed by - * the radio, a @ref sl_bt_evt_test_dtm_completed event is triggered. This event - * indicates whether the test started successfully. - * - * In the custom wave transmitter test, the device continuously transmits the - * career. The parameter @p packet_type specifies the packet type. The parameter - * @p phy specifies which PHY is used to transmit the packets. All devices - * support at least 1M PHY. - * - * Stop the test using the @ref sl_bt_test_dtm_end command. - * - * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to - * transmit. Values: - * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output - * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * @param[in] power_level @parblock - * TX power level. Unit: 0.1 dBm. - * - * If the value exceeds the range of power level value, allowed by the device, - * the command will adjust the power level to the closest minimum or maximum - * value. - * @endparblock - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, - uint8_t channel, - uint8_t phy, - int16_t power_level); - -/***************************************************************************//** - * - * Start a receiver test against a separate Bluetooth tester device. When the - * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event - * is triggered. This event indicates whether the test started successfully. - * - * Parameter @p phy specifies which PHY is used to receive the packets. All - * devices support at least 1M PHY. - * - * The test may be stopped using @ref sl_bt_test_dtm_end command. This will - * trigger another @ref sl_bt_evt_test_dtm_completed event, which carries the - * number of packets received during the test. - * - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy); - -/***************************************************************************//** - * - * End a transmitter or a receiver test. When the command is processed by the - * radio and the test has ended, a @ref sl_bt_evt_test_dtm_completed event is - * triggered. - * - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - Received when the command is - * processed by the radio and the test has ended. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_end(); - -/** @} */ // end addtogroup sl_bt_test - -/** - * @addtogroup sl_bt_sm Security Manager - * @{ - * - * @brief Security Manager - * - * The commands in this class manage Bluetooth security, including commands for - * starting and stopping encryption and commands for management of all bonding - * operations. - * - * Use the following procedure to bond with a remote device: - * - Use the command @ref sl_bt_sm_configure to configure security - * requirements and I/O capabilities of this device. - * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into - * bondable mode. - * - Use the command @ref sl_bt_connection_open to open a connection to the - * remote device. - * - After the connection is open, use command @ref sl_bt_sm_increase_security - * to encrypt the connection. This will also start the bonding process. - * - * Use the following procedure to respond to the bonding initiated by a remote - * device: - * - Use the command @ref sl_bt_sm_configure to configure security - * requirements and I/O capabilities of this device. - * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into - * bondable mode. - * - Use the command @ref sl_bt_advertiser_start to start connectable - * advertising. - * - Open a connection to this device from the remote device. - * - After the connection is open, start the bonding process on the remote - * device. - * - * If MITM is required, the application needs to display or ask the user to - * enter a passkey during the process. See events @ref - * sl_bt_evt_sm_passkey_display and @ref sl_bt_evt_sm_passkey_request for more - * information. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sm_configure_id 0x010f0020 -#define sl_bt_cmd_sm_set_minimum_key_size_id 0x140f0020 -#define sl_bt_cmd_sm_set_debug_mode_id 0x0f0f0020 -#define sl_bt_cmd_sm_add_to_whitelist_id 0x130f0020 -#define sl_bt_cmd_sm_store_bonding_configuration_id 0x020f0020 -#define sl_bt_cmd_sm_set_bondable_mode_id 0x000f0020 -#define sl_bt_cmd_sm_set_passkey_id 0x100f0020 -#define sl_bt_cmd_sm_increase_security_id 0x040f0020 -#define sl_bt_cmd_sm_enter_passkey_id 0x080f0020 -#define sl_bt_cmd_sm_passkey_confirm_id 0x090f0020 -#define sl_bt_cmd_sm_bonding_confirm_id 0x0e0f0020 -#define sl_bt_cmd_sm_delete_bonding_id 0x060f0020 -#define sl_bt_cmd_sm_delete_bondings_id 0x070f0020 -#define sl_bt_cmd_sm_get_bonding_handles_id 0x150f0020 -#define sl_bt_cmd_sm_get_bonding_details_id 0x160f0020 -#define sl_bt_cmd_sm_find_bonding_by_address_id 0x170f0020 -#define sl_bt_cmd_sm_resolve_rpa_id 0x1d0f0020 -#define sl_bt_cmd_sm_set_bonding_key_id 0x180f0020 -#define sl_bt_cmd_sm_set_legacy_oob_id 0x190f0020 -#define sl_bt_cmd_sm_set_oob_id 0x1a0f0020 -#define sl_bt_cmd_sm_set_remote_oob_id 0x1b0f0020 -#define sl_bt_cmd_sm_set_bonding_data_id 0x1c0f0020 -#define sl_bt_rsp_sm_configure_id 0x010f0020 -#define sl_bt_rsp_sm_set_minimum_key_size_id 0x140f0020 -#define sl_bt_rsp_sm_set_debug_mode_id 0x0f0f0020 -#define sl_bt_rsp_sm_add_to_whitelist_id 0x130f0020 -#define sl_bt_rsp_sm_store_bonding_configuration_id 0x020f0020 -#define sl_bt_rsp_sm_set_bondable_mode_id 0x000f0020 -#define sl_bt_rsp_sm_set_passkey_id 0x100f0020 -#define sl_bt_rsp_sm_increase_security_id 0x040f0020 -#define sl_bt_rsp_sm_enter_passkey_id 0x080f0020 -#define sl_bt_rsp_sm_passkey_confirm_id 0x090f0020 -#define sl_bt_rsp_sm_bonding_confirm_id 0x0e0f0020 -#define sl_bt_rsp_sm_delete_bonding_id 0x060f0020 -#define sl_bt_rsp_sm_delete_bondings_id 0x070f0020 -#define sl_bt_rsp_sm_get_bonding_handles_id 0x150f0020 -#define sl_bt_rsp_sm_get_bonding_details_id 0x160f0020 -#define sl_bt_rsp_sm_find_bonding_by_address_id 0x170f0020 -#define sl_bt_rsp_sm_resolve_rpa_id 0x1d0f0020 -#define sl_bt_rsp_sm_set_bonding_key_id 0x180f0020 -#define sl_bt_rsp_sm_set_legacy_oob_id 0x190f0020 -#define sl_bt_rsp_sm_set_oob_id 0x1a0f0020 -#define sl_bt_rsp_sm_set_remote_oob_id 0x1b0f0020 -#define sl_bt_rsp_sm_set_bonding_data_id 0x1c0f0020 - -/** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * @brief These values define the bonding keys of the bonded device stored in - * the persistent store. - */ -typedef enum -{ - sl_bt_sm_bonding_key_remote_ltk = 0x1, /**< (0x1) LTK used as central device, - always used when paired using - secure connections and local LTK - does not exist */ - sl_bt_sm_bonding_key_local_ltk = 0x2, /**< (0x2) LTK used as peripheral - device when using legacy pairing, - only used with secure connections - pairing if key exists */ - sl_bt_sm_bonding_key_irk = 0x3 /**< (0x3) Identity resolving key for - resolvable private addresses */ -} sl_bt_sm_bonding_key_t; -/** @endcond */ // end restricted enum type - -/** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * @brief These values define the bonding data types, which are stored in the - * persistent store. - */ -typedef enum -{ - sl_bt_sm_bonding_data_remote_address = 0x0, /**< (0x0) Identity address - of the remote device */ - sl_bt_sm_bonding_data_remote_ltk = 0x1, /**< (0x1) LTK used as - central device */ - sl_bt_sm_bonding_data_local_ltk = 0x2, /**< (0x2) LTK used as - peripheral device */ - sl_bt_sm_bonding_data_remote_master_inf = 0x3, /**< (0x3) Idenfication info - used as central device */ - sl_bt_sm_bonding_data_local_master_inf = 0x4, /**< (0x4) Idenfication info - used as central device */ - sl_bt_sm_bonding_data_irk = 0x5, /**< (0x5) IRK of the remote - device */ - sl_bt_sm_bonding_data_meta = 0x6, /**< (0x6) Metadata about - the bonding */ - sl_bt_sm_bonding_data_gatt_client_config = 0x7, /**< (0x7) GATT database - client configuration */ - sl_bt_sm_bonding_data_gatt_client_features = 0x8, /**< (0x8) GATT client - supported features */ - sl_bt_sm_bonding_data_gatt_db_hash = 0x9 /**< (0x9) GATT database - hash */ -} sl_bt_sm_bonding_data_t; -/** @endcond */ // end restricted enum type - -/** - * @brief These values define the security management related I/O capabilities - * supported by the device. - */ -typedef enum -{ - sl_bt_sm_io_capability_displayonly = 0x0, /**< (0x0) Display Only */ - sl_bt_sm_io_capability_displayyesno = 0x1, /**< (0x1) Display with - Yes/No-buttons */ - sl_bt_sm_io_capability_keyboardonly = 0x2, /**< (0x2) Keyboard Only */ - sl_bt_sm_io_capability_noinputnooutput = 0x3, /**< (0x3) No Input and No - Output */ - sl_bt_sm_io_capability_keyboarddisplay = 0x4 /**< (0x4) Display with Keyboard */ -} sl_bt_sm_io_capability_t; - -/** - * @addtogroup sl_bt_sm_configuration Security Manager configuration flags - * @{ - * - * These values are used to configure security requirements. - */ - -/** Bonding requires authentication (Man-in-the-Middle protection). */ -#define SL_BT_SM_CONFIGURATION_MITM_REQUIRED 0x1 - -/** Encryption requires bonding. Note that this setting will also enable - * bonding. */ -#define SL_BT_SM_CONFIGURATION_BONDING_REQUIRED 0x2 - -/** Require secure connections pairing. */ -#define SL_BT_SM_CONFIGURATION_SC_ONLY 0x4 - -/** Bonding requests need to be confirmed. Received bonding requests are - * notified by @ref sl_bt_evt_sm_confirm_bonding. */ -#define SL_BT_SM_CONFIGURATION_BONDING_REQUEST_REQUIRED 0x8 - -/** Allow connections only from bonded devices. This option is ignored when the - * application includes the bluetooth_feature_external_bonding_database feature. - * */ -#define SL_BT_SM_CONFIGURATION_CONNECTIONS_FROM_BONDED_DEVICES_ONLY 0x10 - -/** Prefer authenticated pairing when both options are possible based on the - * settings. Otherwise just works pairing is preferred. */ -#define SL_BT_SM_CONFIGURATION_PREFER_MITM 0x20 - -/** Require secure connections OOB data from both devices. */ -#define SL_BT_SM_CONFIGURATION_OOB_FROM_BOTH_DEVICES_REQUIRED 0x40 - -/** Reject pairing if remote device uses debug keys. */ -#define SL_BT_SM_CONFIGURATION_REJECT_DEBUG_KEYS 0x80 - -/** @} */ // end Security Manager configuration flags - -/** - * @addtogroup sl_bt_evt_sm_passkey_display sl_bt_evt_sm_passkey_display - * @{ - * @brief Indicates a request to display the passkey to the user. - */ - -/** @brief Identifier of the passkey_display event */ -#define sl_bt_evt_sm_passkey_display_id 0x000f00a0 - -/***************************************************************************//** - * @brief Data structure of the passkey_display event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_passkey_display_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t passkey; /**< Passkey. Range: 0 to 999999. - - NOTE! When displaying the passkey to the user, - prefix the number with zeros to obtain a 6 digit - number - - Example: Passkey value is 42 - - Number to display to the user is 000042 */ -}); - -typedef struct sl_bt_evt_sm_passkey_display_s sl_bt_evt_sm_passkey_display_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_passkey_display - -/** - * @addtogroup sl_bt_evt_sm_passkey_request sl_bt_evt_sm_passkey_request - * @{ - * @brief Indicates a request for the passkey prompt displayed on the remote - * device - * - * Use the command @ref sl_bt_sm_enter_passkey to input the passkey value. - */ - -/** @brief Identifier of the passkey_request event */ -#define sl_bt_evt_sm_passkey_request_id 0x010f00a0 - -/***************************************************************************//** - * @brief Data structure of the passkey_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_passkey_request_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_sm_passkey_request_s sl_bt_evt_sm_passkey_request_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_passkey_request - -/** - * @addtogroup sl_bt_evt_sm_confirm_passkey sl_bt_evt_sm_confirm_passkey - * @{ - * @brief Indicates a request for passkey display and confirmation by the user - * - * Use the command @ref sl_bt_sm_passkey_confirm to accept or reject the - * displayed passkey. - */ - -/** @brief Identifier of the confirm_passkey event */ -#define sl_bt_evt_sm_confirm_passkey_id 0x020f00a0 - -/***************************************************************************//** - * @brief Data structure of the confirm_passkey event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_confirm_passkey_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t passkey; /**< Passkey. Range: 0 to 999999. - - NOTE! When displaying the passkey to the user, - prefix the number with zeros to obtain a 6 digit - number - - Example: Passkey value is 42 - - Number to display to the user is 000042 */ -}); - -typedef struct sl_bt_evt_sm_confirm_passkey_s sl_bt_evt_sm_confirm_passkey_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_confirm_passkey - -/** - * @addtogroup sl_bt_evt_sm_bonded sl_bt_evt_sm_bonded - * @{ - * @brief Triggered when the pairing or bonding procedure is successfully - * completed. - */ - -/** @brief Identifier of the bonded event */ -#define sl_bt_evt_sm_bonded_id 0x030f00a0 - -/***************************************************************************//** - * @brief Data structure of the bonded event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_bonded_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - Pairing completed without bonding - the - pairing key will be discarded after - disconnection. - - Other: Procedure completed, pairing key - stored with given bonding handle */ - uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection - security mode. Values: - - sl_bt_connection_mode1_level2 (0x1): - Unauthenticated pairing with encryption - - sl_bt_connection_mode1_level3 (0x2): - Authenticated pairing with encryption - - sl_bt_connection_mode1_level4 (0x3): - Authenticated Secure Connections pairing with - encryption using a 128-bit strength encryption - key */ -}); - -typedef struct sl_bt_evt_sm_bonded_s sl_bt_evt_sm_bonded_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_bonded - -/** - * @addtogroup sl_bt_evt_sm_bonding_failed sl_bt_evt_sm_bonding_failed - * @{ - * @brief This event is triggered if the pairing or bonding procedure fails. - */ - -/** @brief Identifier of the bonding_failed event */ -#define sl_bt_evt_sm_bonding_failed_id 0x040f00a0 - -/***************************************************************************//** - * @brief Data structure of the bonding_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_bonding_failed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t reason; /**< Describes error that occurred */ -}); - -typedef struct sl_bt_evt_sm_bonding_failed_s sl_bt_evt_sm_bonding_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_bonding_failed - -/** - * @addtogroup sl_bt_evt_sm_confirm_bonding sl_bt_evt_sm_confirm_bonding - * @{ - * @brief Indicates a user request to display that the new bonding request is - * received and for the user to confirm the request - * - * Use the command @ref sl_bt_sm_bonding_confirm to accept or reject the bonding - * request. - */ - -/** @brief Identifier of the confirm_bonding event */ -#define sl_bt_evt_sm_confirm_bonding_id 0x090f00a0 - -/***************************************************************************//** - * @brief Data structure of the confirm_bonding event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_confirm_bonding_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t bonding_handle; /**< Bonding handle for the request. Range: 0 to 31, - or SL_BT_INVALID_BONDING_HANDLE (0xff). - - NOTE! When the bonding handle is anything - other than SL_BT_INVALID_BONDING_HANDLE - (0xff), a bonding already exists for this - connection. Overwriting the existing bonding - is a potential security risk. */ -}); - -typedef struct sl_bt_evt_sm_confirm_bonding_s sl_bt_evt_sm_confirm_bonding_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_confirm_bonding - -/***************************************************************************//** - * - * Configure security requirements and I/O capabilities of the system. - * - * @param[in] flags @parblock - * Security requirement flags. This value can be a bitmask of multiple flags - * from @ref sl_bt_sm_configuration - * - * Bit 0: - * - 0: Allow bonding without authentication - * - 1: Bonding requires authentication (Man-in-the-Middle - * protection) - * - * Bit 1: - * - 0: Allow encryption without bonding - * - 1: Encryption requires bonding. Note that this setting will also - * enable bonding. - * - * Bit 2: - * - 0: Allow bonding with legacy pairing - * - 1: Secure connections only - * - * Bit 3: - * - 0: Bonding request does not need to be confirmed - * - 1: Bonding requests need to be confirmed. Received bonding - * requests are notified by @ref sl_bt_evt_sm_confirm_bonding - * - * Bit 4: This option is ignored when the application includes the - * bluetooth_feature_external_bonding_database feature. - * - 0: Allow all connections - * - 1: Allow connections only from bonded devices - * - * Bit 5: - * - 0: Prefer just works pairing when both options are possible - * based on the settings. - * - 1: Prefer authenticated pairing when both options are possible - * based on the settings. - * - * Bit 6: - * - 0: Allow secure connections OOB pairing with OOB data from only - * one device. - * - 1: Require secure connections OOB data from both devices. - * - * Bit 7: - * - 0: Allow debug keys from remote device. - * - 1: Reject pairing if remote device uses debug keys. - * - * Default value: 0x00 - * @endparblock - * @param[in] io_capabilities Enum @ref sl_bt_sm_io_capability_t. I/O - * Capabilities. The default I/O Capability used by the stack is No Input and - * No Output. Values: - * - sl_bt_sm_io_capability_displayonly (0x0): Display Only - * - sl_bt_sm_io_capability_displayyesno (0x1): Display with - * Yes/No-buttons - * - sl_bt_sm_io_capability_keyboardonly (0x2): Keyboard Only - * - sl_bt_sm_io_capability_noinputnooutput (0x3): No Input and No - * Output - * - sl_bt_sm_io_capability_keyboarddisplay (0x4): Display with - * Keyboard - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities); - -/***************************************************************************//** - * - * Set the minimum allowed key size used for bonding. The default value is 16 - * bytes. - * - * @param[in] minimum_key_size Minimum allowed key size for bonding. Range: 7 to - * 16 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size); - -/***************************************************************************//** - * - * Set Security Manager in debug mode. In this mode, the secure connections - * bonding uses known debug keys, so that the encrypted packet can be opened by - * Bluetooth protocol analyzer. To disable the debug mode, restart the device. - * - * Bondings made in debug mode are unsecure. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_debug_mode(); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_accept_list_add_device_by_bonding and @ref - * sl_bt_accept_list_add_device_by_address provided by the - * bluetooth_feature_accept_list component. - * - * Add device to accept list, which can be enabled with @ref - * sl_bt_gap_enable_whitelisting. - * - * When using external bonding database, the accept list size must be set before - * adding devices to the list using @ref sl_bt_sm_store_bonding_configuration. - * - * @param[in] address Address of the device added to accept list - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device added to accept list. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type); - -/***************************************************************************//** - * - * Set the maximum allowed bonding count and bonding policy. The maximum number - * of bondings that can be supported depends on how much user data is stored in - * the NVM and the NVM size. When bond policy value 1 or 2 is selected, the - * stack will automatically write the new bond, as per the policy, only if the - * maximum allowed bonding count has been reached. If the stack can't write a - * new bond for any other reason (e.g., NVM is full), an error will be thrown - * through the bonding_failed event indicating why the bonding was not written. - * The application has to manually release space from the NVM (e.g., by deleting - * one of the existing bonds or application data) so that a new bond can be - * saved. The default value is 13. - * - * When using external bonding database with accept list filtering, this command - * must be called before adding devices to the accept list to define the list - * size. Calling this function empties the existing accept list. - * - * @param[in] max_bonding_count @parblock - * Maximum allowed bonding count. Range: 1 to 32 - * - * Sets the accept list size with external bonding database. - * @endparblock - * @param[in] policy_flags @parblock - * Bonding policy. Values: - * - 0: If database is full, new bonding attempts will fail - * - 1: New bonding will overwrite the oldest existing bonding - * - 2: New bonding will overwrite the bonding that was used the - * longest time ago - * - * Default: 0 - * - * With external bonding database the parameter is ignored. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, - uint8_t policy_flags); - -/***************************************************************************//** - * - * Set whether the device should accept new bondings. By default, the device - * does not accept new bondings. - * - * @param[in] bondable @parblock - * Bondable mode. Values: - * - 0: New bondings not accepted - * - 1: Bondings allowed - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable); - -/***************************************************************************//** - * - * Enter a fixed passkey, which will be used in the @ref - * sl_bt_evt_sm_passkey_display event. - * - * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to disable and - * start using random passkeys. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_passkey(int32_t passkey); - -/***************************************************************************//** - * - * Enhance the security of a connection to current security requirements. On an - * unencrypted connection, it will encrypt the connection and will also perform - * bonding if requested by both devices. On an encrypted connection, it will - * cause the connection to be re-encrypted. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_parameters - Triggered after increasing - * security has been completed successfully and indicates the latest - * security mode of the connection. - * - @ref sl_bt_evt_sm_bonded - Triggered if pairing or bonding was performed - * in this operation and the result is successful. - * - @ref sl_bt_evt_sm_bonding_failed - Triggered if pairing or bonding was - * performed in this operation and the result has failed. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_increase_security(uint8_t connection); - -/***************************************************************************//** - * - * Enter a passkey after receiving a passkey request event. - * - * @param[in] connection Connection handle - * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to cancel pairing. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey); - -/***************************************************************************//** - * - * Accept or reject the reported passkey confirm value. - * - * @param[in] connection Connection handle - * @param[in] confirm Acceptance. Values: - * - 0: Reject - * - 1: Accept confirm value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm); - -/***************************************************************************//** - * - * Accept or reject the bonding request. - * - * @param[in] connection Connection handle - * @param[in] confirm Acceptance. Values: - * - 0: Reject - * - 1: Accept bonding request - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm); - -/***************************************************************************//** - * - * Delete the specified bonding or accept list filtering. The connection will be - * closed if the remote device is connected currently. - * - * This commands deletes the information from the persistent bonding database - * when the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) is used. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] bonding Bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding); - -/***************************************************************************//** - * - * Delete all bondings, accept list filtering and device local identity - * resolving key (IRK). All connections to affected devices are closed as well. - * - * This command empties the persistent bonding database when the built-in - * bonding database (bluetooth_feature_builtin_bonding_database) is used. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_delete_bondings(); - -/***************************************************************************//** - * - * Get number of entries and bitmask of their handles saved in the bonding - * database. The entry in the bonding database can be either bonding or accept - * list filtering device. - * - * To get the bonding type and peer device address of a bonding, use the @ref - * sl_bt_sm_get_bonding_details command. The bonding handle can be calculated - * from the handle bitmask returned by this command, or alternatively, repeat - * calling the @ref sl_bt_sm_get_bonding_details command to get the detailed - * information of all bondings. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] reserved Use the value 0 on this reserved field. Do not use - * none-zero values because they are reserved for future use. - * @param[out] num_bondings Total number of bondings and accept list filtering - * devices stored in bonding database. - * @param[in] max_bondings_size Size of output buffer passed in @p bondings - * @param[out] bondings_len On return, set to the length of output data written - * to @p bondings - * @param[out] bondings 4 byte bit field of used bonding handles in little - * endian format. Bit 0 of first byte is bonding handle 0, bit 0 of second - * byte is bonding handle 8 etc. If the bit is 1 that bonding handle exists in - * the bonding database. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, - uint32_t *num_bondings, - size_t max_bondings_size, - size_t *bondings_len, - uint8_t *bondings); - -/***************************************************************************//** - * - * Get the detailed information for a bonding entry. Data includes remote device - * address and address type as well as security mode for bonding and a used - * encryption key length. - * - * To get the detailed information of all bondings, repeat calling this command - * starting from 0 as the bonding handle value until the maximum number of - * configured bondings are reached. Use 32 as the maximum number if the - * configured number is unknown. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] bonding Bonding handle - * @param[out] address Bluetooth address of the remote device - * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Accept list filtering entry has security mode as no - * security. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size Key length in bytes, 0 for accept list filtering entry - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, - bd_addr *address, - uint8_t *address_type, - uint8_t *security_mode, - uint8_t *key_size); - -/***************************************************************************//** - * - * Find the bonding or accept list filtering entry by using a Bluetooth device - * address. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] address The Bluetooth device address - * @param[out] bonding The bonding handle - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Accept list filtering entry has security mode as no - * security. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size Key length in bytes, 0 for accept list filtering entry - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, - uint32_t *bonding, - uint8_t *security_mode, - uint8_t *key_size); - -/***************************************************************************//** - * - * Find the identity address of bonded device by using resolvable private - * address (RPA). - * - * The error SL_STATUS_NOT_FOUND is returned if the RPA cannot be resolved. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] rpa Resolvable private address to be resolved - * @param[out] address The identity adderss of the bonded device - * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Identity address - * type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[out] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, - bd_addr *address, - uint8_t *address_type, - uint32_t *bonding); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Set key for bonding or accept list filtering entry overwriting any possible - * existing key. If there is error which leaves bonding entry in inconsistent - * state the bonding will be deleted. Only IRK can be added to accept list - * filtering entry. - * - * @param[in] bonding Bonding handle - * @param[in] key_type Enum @ref sl_bt_sm_bonding_key_t. Key type. Values: - * - sl_bt_sm_bonding_key_remote_ltk (0x1): LTK used as central - * device, always used when paired using secure connections and local LTK - * does not exist - * - sl_bt_sm_bonding_key_local_ltk (0x2): LTK used as peripheral - * device when using legacy pairing, only used with secure connections - * pairing if key exists - * - sl_bt_sm_bonding_key_irk (0x3): Identity resolving key for - * resolvable private addresses - * @param[in] key Bonding key in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, - uint8_t key_type, - aes_key_128 key); - -/***************************************************************************//** - * - * Set Out-Of-Band (OOB) encryption data for a legacy pairing of a device. OOB - * data may be, for example, a PIN code exchanged over an alternate path, such - * as NFC. The device will not allow any other bonding if OOB data is set. OOB - * data can't be set simultaneously with secure connections OOB data. - * - * @param[in] enable Enable OOB with legacy pairing. Values: - * - 0: disable - * - 1: enable - * @param[in] oob_data 16-byte legacy pairing OOB data in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data); - -/***************************************************************************//** - * - * Enable the use of Out-Of-Band (OOB) encryption data for a device for secure - * connections pairing. Enabling will generate new OOB data and confirm values, - * which can be sent to the remote device. After enabling the secure connections - * OOB data, the remote devices OOB data can be set with @ref - * sl_bt_sm_set_remote_oob. Calling this function will erase any set remote - * device OOB data and confirm values. The device will not allow any other - * bonding if OOB data is set. The secure connections OOB data cannot be enabled - * simultaneously with legacy pairing OOB data. - * - * @param[in] enable Enable OOB with secure connections pairing. Values: - * - 0: disable - * - 1: enable - * @param[out] random 16-byte randomly-generated secure connections OOB data in - * little endian format. - * @param[out] confirm 16-byte confirm value for the OOB random value in little - * endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_oob(uint8_t enable, - aes_key_128 *random, - aes_key_128 *confirm); - -/***************************************************************************//** - * - * Set Out-Of-Band (OOB) data and confirm values received from the remote device - * for secure connections pairing. OOB data must be enabled with @ref - * sl_bt_sm_set_oob before setting the remote device OOB data. - * - * @param[in] enable Enable remote device OOB data with secure connections - * pairing. Values: - * - 0: disable - * - 1: enable - * @param[in] random 16-byte remote device secure connections OOB data in little - * endian format. - * @param[in] confirm 16-byte remote device confirm value for the OOB random - * value in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, - aes_key_128 random, - aes_key_128 confirm); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Set bonding data for connection from external bonding database. - * - * @param[in] connection Connection handle - * @param[in] type Enum @ref sl_bt_sm_bonding_data_t. Bonding data type. Values: - * - sl_bt_sm_bonding_data_remote_address (0x0): Identity address of - * the remote device - * - sl_bt_sm_bonding_data_remote_ltk (0x1): LTK used as central - * device - * - sl_bt_sm_bonding_data_local_ltk (0x2): LTK used as peripheral - * device - * - sl_bt_sm_bonding_data_remote_master_inf (0x3): Idenfication info - * used as central device - * - sl_bt_sm_bonding_data_local_master_inf (0x4): Idenfication info - * used as central device - * - sl_bt_sm_bonding_data_irk (0x5): IRK of the remote device - * - sl_bt_sm_bonding_data_meta (0x6): Metadata about the bonding - * - sl_bt_sm_bonding_data_gatt_client_config (0x7): GATT database - * client configuration - * - sl_bt_sm_bonding_data_gatt_client_features (0x8): GATT client - * supported features - * - sl_bt_sm_bonding_data_gatt_db_hash (0x9): GATT database hash - * @param[in] data_len Length of data in @p data - * @param[in] data Bonding data. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/** @} */ // end addtogroup sl_bt_sm - -/** - * @addtogroup sl_bt_external_bondingdb External Bonding Database - * @{ - * - * @brief External Bonding Database - * - * Receive and respond to requests related to managing an external bonding - * database. When the application uses the - * bluetooth_feature_external_bonding_database feature, the Bluetooth stack and - * the application use the commands and events in this class to store and - * retrieve data from the persistent bonding storage. - * - * When this feature is used, the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) and the address resolving in the - * Bluetooth stack are excluded. The user application and external bonding - * database are responsible for the following functionalities: - * - The external bonding database must be able to reliably and permanently - * store the bonding data and type tuples that are provided by the stack in - * the @ref sl_bt_evt_external_bondingdb_data_request event. Data types @ref - * sl_bt_external_bondingdb_data_remote_address and @ref - * sl_bt_external_bondingdb_data_remote_address_type can be used by the - * application to identify the device, but they are not used by the stack - * and hence the stack will not ask for their values. Other data types in - * @ref sl_bt_external_bondingdb_data_t are needed by the Bluetooth Security - * Manager or GATT Server. The Long Term Keys (LTK) and Identity Resolving - * Keys (IRK) must be stored securely. When the database is on a separate - * host device, they must be securely transmitted between the host and - * target over the NCP transport. The application also needs to manage the - * bondings in the storage, e.g., delete a bonding when requested by the - * business logic. - * - Manage a local RAM-based bookkeeping to keep track of open connections. - * At a minimum, the remote Bluetooth address address and address type must - * be stored in the bookkeeping when a @ref sl_bt_evt_connection_opened - * event is received. If the remote Bluetooth device address is a resolvable - * private random (RPA) address, the application may perform address - * resolving using the IRK keys of the remote devices stored in the bonding - * database. Address resolving is required for identifying a connected - * device using an RPA address. When the scanner or periodic advertising - * synchronization feature is used, RPA addresses in advertisement report or - * sync events may need to be resolved if required by the business - * requirements. - * - When the Bluetooth stack requires bonding data, it will send an @ref - * sl_bt_evt_external_bondingdb_data_request event. The application must - * respond to the request by sending the data value using the @ref - * sl_bt_external_bondingdb_set_data command. The GATT server will pend the - * requests from the remote GATT client and encryption or bonding is not - * possible until all requested bonding data has been sent to the stack. The - * stack will send @ref sl_bt_evt_external_bondingdb_data_ready when it has - * received all the necessary bonding data from the application. - * - * In this configuration, the value of @p bonding parameter in @ref - * sl_bt_evt_advertiser_scan_request, @ref sl_bt_evt_connection_opened, @ref - * sl_bt_evt_sm_bonded, @ref sl_bt_evt_scanner_scan_report, @ref - * sl_bt_evt_scanner_legacy_advertisement_report, @ref - * sl_bt_evt_scanner_extended_advertisement_report, @ref sl_bt_evt_sync_opened, - * and @ref sl_bt_evt_sync_transfer_received is always - * SL_BT_INVALID_BONDING_HANDLE (0xff). Resolving the bonding handle is the - * responsibility of the external bonding database. Additionally, the following - * BGAPI commands are not available and will return the SL_STATUS_NOT_AVAILABLE - * error: - * - @ref sl_bt_sm_delete_bonding - * - @ref sl_bt_sm_get_bonding_handles - * - @ref sl_bt_sm_get_bonding_details - * - @ref sl_bt_sm_find_bonding_by_address - * - @ref sl_bt_sm_resolve_rpa - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_external_bondingdb_set_data_id 0x005c0020 -#define sl_bt_rsp_external_bondingdb_set_data_id 0x005c0020 - -/** - * @brief These values define the bonding data types, which are stored in the - * persistent store. - */ -typedef enum -{ - sl_bt_external_bondingdb_data_remote_address = 0x0, /**< (0x0) Identity - address of the - remote device, - which a - resolvable - random address - can be resolved - to */ - sl_bt_external_bondingdb_data_remote_address_type = 0x1, /**< (0x1) Type of - the remote - device identity - address. Value - 0 is public - device address - and 1 is static - device address */ - sl_bt_external_bondingdb_data_remote_ltk = 0x2, /**< (0x2) Long Term - Key (LTK) used - as central - device. The - value of this - type must be - stored - securely. */ - sl_bt_external_bondingdb_data_local_ltk = 0x3, /**< (0x3) Long Term - Key (LTK) used - as peripheral - device. The - value of this - type must be - stored - securely. */ - sl_bt_external_bondingdb_data_remote_central_inf = 0x4, /**< (0x4) - Identification - info used as a - central device */ - sl_bt_external_bondingdb_data_local_central_inf = 0x5, /**< (0x5) - Identification - info used as a - central device */ - sl_bt_external_bondingdb_data_irk = 0x6, /**< (0x6) Identity - Resolving Key - (IRK) of the - remote device - that is used - for resolving - its RPA - addresses when - the device is - in privacy - mode. The value - of this type - must be stored - securely. */ - sl_bt_external_bondingdb_data_meta = 0x7, /**< (0x7) Metadata - about the - bonding */ - sl_bt_external_bondingdb_data_gatt_client_config = 0x8, /**< (0x8) The - remote GATT - client - characteristic - configurations */ - sl_bt_external_bondingdb_data_gatt_client_features = 0x9, /**< (0x9) The - remote GATT - client - supported - features */ - sl_bt_external_bondingdb_data_gatt_db_hash = 0xa /**< (0xa) Latest - local GATT - database hash - value that the - remote client - has seen for - GATT robust - caching feature */ -} sl_bt_external_bondingdb_data_t; - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data_request sl_bt_evt_external_bondingdb_data_request - * @{ - * @brief Indicates that the Bluetooth stack requests the bonding data of a - * connection from the external bonding database - * - * The application must respond by setting bonding data using the @ref - * sl_bt_external_bondingdb_set_data command. - * - * The Bluetooth stack will send this event one or more times after a connection - * is open following the @ref sl_bt_evt_connection_opened event to get ready for - * security related operations. - */ - -/** @brief Identifier of the data_request event */ -#define sl_bt_evt_external_bondingdb_data_request_id 0x005c00a0 - -/***************************************************************************//** - * @brief Data structure of the data_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_request_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The - requested bonding data type. Values: - - sl_bt_external_bondingdb_data_remote_address - (0x0): Identity address of the remote device, - which a resolvable random address can be resolved - to - - sl_bt_external_bondingdb_data_remote_address_type - (0x1): Type of the remote device identity - address. Value 0 is public device address and 1 - is static device address - - sl_bt_external_bondingdb_data_remote_ltk - (0x2): Long Term Key (LTK) used as central - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_local_ltk - (0x3): Long Term Key (LTK) used as peripheral - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_remote_central_inf - (0x4): Identification info used as a central - device - - sl_bt_external_bondingdb_data_local_central_inf - (0x5): Identification info used as a central - device - - sl_bt_external_bondingdb_data_irk (0x6): - Identity Resolving Key (IRK) of the remote device - that is used for resolving its RPA addresses when - the device is in privacy mode. The value of this - type must be stored securely. - - sl_bt_external_bondingdb_data_meta (0x7): - Metadata about the bonding - - sl_bt_external_bondingdb_data_gatt_client_config - (0x8): The remote GATT client characteristic - configurations - - sl_bt_external_bondingdb_data_gatt_client_features - (0x9): The remote GATT client supported - features - - sl_bt_external_bondingdb_data_gatt_db_hash - (0xa): Latest local GATT database hash value - that the remote client has seen for GATT robust - caching feature */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_request_s sl_bt_evt_external_bondingdb_data_request_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_request - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data sl_bt_evt_external_bondingdb_data - * @{ - * @brief Indicates that updated bonding data of a connection is available - * - * The application must store it in the external bonding database permanently. - */ - -/** @brief Identifier of the data event */ -#define sl_bt_evt_external_bondingdb_data_id 0x015c00a0 - -/***************************************************************************//** - * @brief Data structure of the data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The - bonding data type. Values: - - sl_bt_external_bondingdb_data_remote_address - (0x0): Identity address of the remote - device, which a resolvable random address can - be resolved to - - sl_bt_external_bondingdb_data_remote_address_type - (0x1): Type of the remote device identity - address. Value 0 is public device address and - 1 is static device address - - sl_bt_external_bondingdb_data_remote_ltk - (0x2): Long Term Key (LTK) used as central - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_local_ltk - (0x3): Long Term Key (LTK) used as - peripheral device. The value of this type must - be stored securely. - - sl_bt_external_bondingdb_data_remote_central_inf - (0x4): Identification info used as a - central device - - sl_bt_external_bondingdb_data_local_central_inf - (0x5): Identification info used as a - central device - - sl_bt_external_bondingdb_data_irk - (0x6): Identity Resolving Key (IRK) of the - remote device that is used for resolving its - RPA addresses when the device is in privacy - mode. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_meta - (0x7): Metadata about the bonding - - sl_bt_external_bondingdb_data_gatt_client_config - (0x8): The remote GATT client - characteristic configurations - - sl_bt_external_bondingdb_data_gatt_client_features - (0x9): The remote GATT client supported - features - - sl_bt_external_bondingdb_data_gatt_db_hash - (0xa): Latest local GATT database hash - value that the remote client has seen for GATT - robust caching feature */ - uint8array data; /**< Bonding data */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_s sl_bt_evt_external_bondingdb_data_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data_ready sl_bt_evt_external_bondingdb_data_ready - * @{ - * @brief Indicates that stack has received all the necessary bonding data from - * the application and is now fully functional - */ - -/** @brief Identifier of the data_ready event */ -#define sl_bt_evt_external_bondingdb_data_ready_id 0x025c00a0 - -/***************************************************************************//** - * @brief Data structure of the data_ready event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_ready_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_ready_s sl_bt_evt_external_bondingdb_data_ready_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_ready - -/***************************************************************************//** - * - * Set bonding data of a connection from the external bonding database. When the - * Bluetooth stack needs bonding data, it will send the request to user - * application with a @ref sl_bt_evt_external_bondingdb_data_request event that - * contains the requested data type. The application must respond to the request - * by sending data using this command. - * - * Send 0 length data to the stack with this command if the requested data is - * not available in the external bonding database. - * - * @param[in] connection Connection handle - * @param[in] type Enum @ref sl_bt_external_bondingdb_data_t. Bonding data type. - * Values: - * - sl_bt_external_bondingdb_data_remote_address (0x0): Identity - * address of the remote device, which a resolvable random address can be - * resolved to - * - sl_bt_external_bondingdb_data_remote_address_type (0x1): Type of - * the remote device identity address. Value 0 is public device address - * and 1 is static device address - * - sl_bt_external_bondingdb_data_remote_ltk (0x2): Long Term Key - * (LTK) used as central device. The value of this type must be stored - * securely. - * - sl_bt_external_bondingdb_data_local_ltk (0x3): Long Term Key - * (LTK) used as peripheral device. The value of this type must be stored - * securely. - * - sl_bt_external_bondingdb_data_remote_central_inf (0x4): - * Identification info used as a central device - * - sl_bt_external_bondingdb_data_local_central_inf (0x5): - * Identification info used as a central device - * - sl_bt_external_bondingdb_data_irk (0x6): Identity Resolving Key - * (IRK) of the remote device that is used for resolving its RPA addresses - * when the device is in privacy mode. The value of this type must be - * stored securely. - * - sl_bt_external_bondingdb_data_meta (0x7): Metadata about the - * bonding - * - sl_bt_external_bondingdb_data_gatt_client_config (0x8): The - * remote GATT client characteristic configurations - * - sl_bt_external_bondingdb_data_gatt_client_features (0x9): The - * remote GATT client supported features - * - sl_bt_external_bondingdb_data_gatt_db_hash (0xa): Latest local - * GATT database hash value that the remote client has seen for GATT - * robust caching feature - * @param[in] data_len Length of data in @p data - * @param[in] data Bonding data - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/** @} */ // end addtogroup sl_bt_external_bondingdb - -/** - * @addtogroup sl_bt_resolving_list Address Resolving List - * @{ - * - * @brief Address Resolving List - * - * Provides support for adding and removing devices from the Resolving List in - * controller-based privacy. - * - * Adding a peer device to the Resolving List allows the Bluetooth controller to - * resolve the address when the peer device is using privacy and is transmitting - * with a Resolvable Private Address (RPA). When the controller has resolved an - * address in a received Bluetooth packet such as an advertisement, the - * corresponding event will report the peer device's identity address even if a - * Resolvable Private Address was used over the air. - * - * When the application has added a peer device to the Resolving List, the - * application may use the peer device's identity address in commands such as - * @ref sl_bt_connection_open or @ref sl_bt_sync_scanner_open even if the peer - * device is using privacy and is using a Resolvable Private Address over the - * air. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_resolving_list_add_device_by_bonding_id 0x005d0020 -#define sl_bt_cmd_resolving_list_add_device_by_address_id 0x015d0020 -#define sl_bt_cmd_resolving_list_remove_device_by_bonding_id 0x025d0020 -#define sl_bt_cmd_resolving_list_remove_device_by_address_id 0x035d0020 -#define sl_bt_cmd_resolving_list_remove_all_devices_id 0x045d0020 -#define sl_bt_rsp_resolving_list_add_device_by_bonding_id 0x005d0020 -#define sl_bt_rsp_resolving_list_add_device_by_address_id 0x015d0020 -#define sl_bt_rsp_resolving_list_remove_device_by_bonding_id 0x025d0020 -#define sl_bt_rsp_resolving_list_remove_device_by_address_id 0x035d0020 -#define sl_bt_rsp_resolving_list_remove_all_devices_id 0x045d0020 - -/** - * @brief Specifies the Privacy Mode used for a peer device in the Resolving - * List - */ -typedef enum -{ - sl_bt_resolving_list_privacy_mode_network = 0x0, /**< (0x0) Use Network - Privacy Mode for the - peer device */ - sl_bt_resolving_list_privacy_mode_device = 0x1 /**< (0x1) Use Device Privacy - Mode for the peer device */ -} sl_bt_resolving_list_privacy_mode_t; - -/***************************************************************************//** - * - * Add a device to the Resolving List based on its bonding handle. - * - * This command is not available if the application uses the external bonding - * database provided by the component - * bluetooth_feature_external_bonding_database. In that configuration the - * application can use the command @ref - * sl_bt_resolving_list_add_device_by_address and provide the peer's identity - * address and its Identity Resolving Key (IRK). - * - * @param[in] bonding The bonding handle - * @param[in] privacy_mode @parblock - * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for - * the peer device. Values: - * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network - * Privacy Mode for the peer device - * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device - * Privacy Mode for the peer device - * - * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network - * Privacy Mode for the peer device) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, - uint8_t privacy_mode); - -/***************************************************************************//** - * - * Add a device to the Resolving List based on its identity address and its - * Identity Resolving Key (IRK). - * - * This command is typically only needed when the application uses the external - * bonding database provided by the component - * bluetooth_feature_external_bonding_database. When the application uses the - * built-in bonding database, the command @ref - * sl_bt_resolving_list_add_device_by_bonding is more convenient. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[in] key Identity Resolving Key (IRK) of the peer device in little - * endian format. - * @param[in] privacy_mode @parblock - * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for - * the peer device. Values: - * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network - * Privacy Mode for the peer device - * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device - * Privacy Mode for the peer device - * - * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network - * Privacy Mode for the peer device) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, - uint8_t address_type, - aes_key_128 key, - uint8_t privacy_mode); - -/***************************************************************************//** - * - * Remove a device from the Resolving List based on its bonding handle. - * - * This command is not available if the application uses the external bonding - * database provided by the component - * bluetooth_feature_external_bonding_database. In that configuration the - * application can use the command @ref - * sl_bt_resolving_list_remove_device_by_address and provide the peer's identity - * address. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Remove a device from the Resolving List based on its identity address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove all devices from the Resolving List. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_all_devices(); - -/** @} */ // end addtogroup sl_bt_resolving_list - -/** - * @addtogroup sl_bt_accept_list Filter Accept List - * @{ - * - * @brief Filter Accept List - * - * Provides support for adding and removing devices from the Filter Accept List - * in the Bluetooth controller. - * - * The Filter Accept List allows filtering transmissions from other Bluetooth - * devices so that the local device only receives/accepts transmissions from the - * devices that it's interested in or wants to communicate with. Operations that - * support filtering provide a means to control how the Filter Accept List is - * used: - * - For advertising, use the command @ref sl_bt_advertiser_configure and @p - * flags bits @ref SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to control the - * advertising filter policy - * - For scanning, use the command @ref - * sl_bt_scanner_set_parameters_and_filter to control the scanning filter - * policy - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_accept_list_add_device_by_bonding_id 0x005e0020 -#define sl_bt_cmd_accept_list_add_device_by_address_id 0x015e0020 -#define sl_bt_cmd_accept_list_remove_device_by_bonding_id 0x025e0020 -#define sl_bt_cmd_accept_list_remove_device_by_address_id 0x035e0020 -#define sl_bt_cmd_accept_list_remove_all_devices_id 0x045e0020 -#define sl_bt_rsp_accept_list_add_device_by_bonding_id 0x005e0020 -#define sl_bt_rsp_accept_list_add_device_by_address_id 0x015e0020 -#define sl_bt_rsp_accept_list_remove_device_by_bonding_id 0x025e0020 -#define sl_bt_rsp_accept_list_remove_device_by_address_id 0x035e0020 -#define sl_bt_rsp_accept_list_remove_all_devices_id 0x045e0020 - -/***************************************************************************//** - * - * Add a device to the Filter Accept List based on its bonding handle. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Add a device to the Filter Accept List based on its identity address. - * - * Use the special address type @ref sl_bt_gap_anonymous_address to add an entry - * that matches all advertisements sent with no address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter - * Accept List entry with this type matches all advertisements sent with - * no address. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove a device from the Filter Accept List based on its bonding handle. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Remove a device from the Filter Accept List based on its identity address. - * - * Use the special address type @ref sl_bt_gap_anonymous_address to remove an - * entry that matches all advertisements sent with no address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter - * Accept List entry with this type matches all advertisements sent with - * no address. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove all devices from the Filter Accept List. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_all_devices(); - -/** @} */ // end addtogroup sl_bt_accept_list - -/** - * @addtogroup sl_bt_ota OTA - * @{ - * - * @brief OTA - * - * Commands in this class are used for configuring OTA DFU using the Apploader. - * - * Note that this class is used on EFR series 1 and is not available for series - * 2 devices. The Apploader runs as a Bootloader communication plugin on series - * 2 and the Apploader plugin API supports setting device name and advertising - * data. Other configurations can be implemented in the Apploader plugin - * application space. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_ota_set_device_name_id 0x01100020 -#define sl_bt_cmd_ota_set_advertising_data_id 0x02100020 -#define sl_bt_cmd_ota_set_configuration_id 0x03100020 -#define sl_bt_cmd_ota_set_rf_path_id 0x04100020 -#define sl_bt_rsp_ota_set_device_name_id 0x01100020 -#define sl_bt_rsp_ota_set_advertising_data_id 0x02100020 -#define sl_bt_rsp_ota_set_configuration_id 0x03100020 -#define sl_bt_rsp_ota_set_rf_path_id 0x04100020 - -/***************************************************************************//** - * - * Set the device name to be used during the OTA update. The name is stored in - * the persistent store. Maximum name length is 17 bytes. - * - * Default is "OTA" if a name is not set. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] name_len Length of data in @p name - * @param[in] name OTA device name - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name); - -/***************************************************************************//** - * - * Set advertising packets in OTA. Maximum 31 bytes of data can be set. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] packet_type This value selects whether data is intended for - * advertising packets or scan response packets. - * - 2: OTA advertising packets - * - 4: OTA scan response packets - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Set OTA configuration. The setting is stored in the persistent store. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] flags @parblock - * OTA configuration flags. This value is given as a bitmask. Flags: - * - * Bit 0: Advertising address - * - * - 0: Use public device address - * - 1: Use a random address - * - * Bit 1: Application update version check. Check the version number and - * product ID of the application upgrade before applying. If the version - * number of the current application can't be determined, this implementation - * will assume that it is OK to apply the new image. Note that this is not a - * security feature. - * - * - 0: Disable version check - * - 1: Enable version check - * - * Bit 2 to 31: Reserved - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_configuration(uint32_t flags); - -/***************************************************************************//** - * - * Set RF path antenna for OTA. This command should be used only if the device - * has multiple antenna ports. The setting is stored in the persistent store. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] enable If enabled antenna selection is used in OTA, otherwise - * default antenna is used. - * @param[in] antenna Set antenna used in OTA. Value should be come from - * RAIL_AntennaSel_t enum. See antenna path selection in RAIL - * rail_chip_specific.h. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna); - -/** @} */ // end addtogroup sl_bt_ota - -/** - * @addtogroup sl_bt_coex Coexistence - * @{ - * - * @brief Coexistence - * - * Coexistence BGAPI class. Coexistence interface is enabled and initialized - * with sl_bt_init_coex_hal function. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_coex_set_options_id 0x00200020 -#define sl_bt_cmd_coex_set_parameters_id 0x02200020 -#define sl_bt_cmd_coex_set_directional_priority_pulse_id 0x03200020 -#define sl_bt_cmd_coex_get_parameters_id 0x04200020 -#define sl_bt_cmd_coex_get_counters_id 0x01200020 -#define sl_bt_rsp_coex_set_options_id 0x00200020 -#define sl_bt_rsp_coex_set_parameters_id 0x02200020 -#define sl_bt_rsp_coex_set_directional_priority_pulse_id 0x03200020 -#define sl_bt_rsp_coex_get_parameters_id 0x04200020 -#define sl_bt_rsp_coex_get_counters_id 0x01200020 - -/** - * @brief Coexistence configuration options - */ -typedef enum -{ - sl_bt_coex_option_enable = 0x100, /**< (0x100) Enable coexistence - feature */ - sl_bt_coex_option_tx_abort = 0x400, /**< (0x400) Abort transmission if - grant is denied */ - sl_bt_coex_option_high_priority = 0x800 /**< (0x800) Enable priority signal */ -} sl_bt_coex_option_t; - -/***************************************************************************//** - * - * Configure coexistence options at runtime. - * - * @param[in] mask Bitmask of following coexistence options to change - * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence - * feature - * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if - * grant is denied - * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority - * signal - * @param[in] options Bitmask of following coexistence option values to set - * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence - * feature - * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if - * grant is denied - * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority - * signal - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options); - -/***************************************************************************//** - * - * Configure coexistence parameters. - * - * @param[in] priority Coexistence priority threshold. Coexistence priority is - * toggled if priority is below this value. - * @param[in] request Coexistence request threshold. Coexistence request is - * toggled if priority is below this value. - * @param[in] pwm_period PWM functionality period length in 1 ms units - * @param[in] pwm_dutycycle PWM functionality duty cycle in percentage - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_parameters(uint8_t priority, - uint8_t request, - uint8_t pwm_period, - uint8_t pwm_dutycycle); - -/***************************************************************************//** - * - * Set Directional Priority Pulse Width. - * - * @param[in] pulse Directional priority pulse width in us - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse); - -/***************************************************************************//** - * - * Get the coexistence parameters. - * - * @param[out] priority Coexistence priority threshold. Coexistence priority is - * toggled if priority is below this value. - * @param[out] request Coexistence request threshold. Coexistence request is - * toggled if priority is below this value. - * @param[out] pwm_period PWM functionality period length in 1 ms units - * @param[out] pwm_dutycycle PWM functionality duty cycle in percentage - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, - uint8_t *request, - uint8_t *pwm_period, - uint8_t *pwm_dutycycle); - -/***************************************************************************//** - * - * Read coexistence statistic counters from the device. Response contains the - * list of uint32 type counter values. Counters in the list are in following - * order: low priority requested, high priority requested, low priority denied, - * high priority denied, low-priority TX aborted, and high-priority TX aborted. - * Passing a non-zero value also resets counters. - * - * @param[in] reset Reset counters if parameter value is not zero. - * @param[in] max_counters_size Size of output buffer passed in @p counters - * @param[out] counters_len On return, set to the length of output data written - * to @p counters - * @param[out] counters Coexistence statistic counters - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_get_counters(uint8_t reset, - size_t max_counters_size, - size_t *counters_len, - uint8_t *counters); - -/** @} */ // end addtogroup sl_bt_coex - -/** - * @addtogroup sl_bt_cs Accurate Bluetooth Ranging - * @{ - * - * @brief Accurate Bluetooth Ranging - * - * This class provides commands and events for Accurate Bluetooth Ranging (ABR) - * between Bluetooth devices. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cs_security_enable_id 0x00590020 -#define sl_bt_cmd_cs_set_default_settings_id 0x01590020 -#define sl_bt_cmd_cs_create_config_id 0x02590020 -#define sl_bt_cmd_cs_remove_config_id 0x03590020 -#define sl_bt_cmd_cs_set_channel_classification_id 0x04590020 -#define sl_bt_cmd_cs_set_procedure_parameters_id 0x05590020 -#define sl_bt_cmd_cs_procedure_enable_id 0x06590020 -#define sl_bt_cmd_cs_set_antenna_configuration_id 0x07590020 -#define sl_bt_cmd_cs_read_local_supported_capabilities_id 0x08590020 -#define sl_bt_rsp_cs_security_enable_id 0x00590020 -#define sl_bt_rsp_cs_set_default_settings_id 0x01590020 -#define sl_bt_rsp_cs_create_config_id 0x02590020 -#define sl_bt_rsp_cs_remove_config_id 0x03590020 -#define sl_bt_rsp_cs_set_channel_classification_id 0x04590020 -#define sl_bt_rsp_cs_set_procedure_parameters_id 0x05590020 -#define sl_bt_rsp_cs_procedure_enable_id 0x06590020 -#define sl_bt_rsp_cs_set_antenna_configuration_id 0x07590020 -#define sl_bt_rsp_cs_read_local_supported_capabilities_id 0x08590020 - -/** - * @brief Specifies the role for the device during ABR procedure. - */ -typedef enum -{ - sl_bt_cs_role_initiator = 0x0, /**< (0x0) The device will initiate the - procedure */ - sl_bt_cs_role_reflector = 0x1 /**< (0x1) The device will reciprocate - transmission */ -} sl_bt_cs_role_t; - -/** - * @brief Defines the status of a given role for an ABR capable device. - */ -typedef enum -{ - sl_bt_cs_role_status_disable = 0x0, /**< (0x0) The given role is disabled */ - sl_bt_cs_role_status_enable = 0x1 /**< (0x1) The given role is enabled */ -} sl_bt_cs_role_status_t; - -/** - * @brief Defines the status of a companion signal. - */ -typedef enum -{ - sl_bt_cs_companion_signal_status_disable = 0x0, /**< (0x0) The companion - signal is disabled */ - sl_bt_cs_companion_signal_status_enable = 0x1 /**< (0x1) The companion - signal is enabled */ -} sl_bt_cs_companion_signal_status_t; - -/** - * @brief Defines the ABR procedure state for the device. - */ -typedef enum -{ - sl_bt_cs_procedure_state_disabled = 0x0, /**< (0x0) ABR procedures are - disabled */ - sl_bt_cs_procedure_state_enabled = 0x1 /**< (0x1) ABR procedures are enabled */ -} sl_bt_cs_procedure_state_t; - -/** - * @brief Defines the different modes for ABR steps. - */ -typedef enum -{ - sl_bt_cs_mode_rtt = 0x1, /**< (0x1) Round Trip Time (RTT) measurement */ - sl_bt_cs_mode_pbr = 0x2, /**< (0x2) Phase-Based Ranging (PBR) - measurement */ - sl_bt_cs_submode_disabled = 0xff /**< (0xff) Submode disabled for the - procedure. */ -} sl_bt_cs_mode_t; - -/** - * @brief Defines the Round Trip Time (RTT) payload types used during the ABR - * sequence. - */ -typedef enum -{ - sl_bt_cs_rtt_type_coarse = 0x0, /**< (0x0) RTT Coarse */ - sl_bt_cs_rtt_type_fractional_96_bit_sounding = 0x2 /**< (0x2) RTT Fractional - with 96-bit Sounding - Sequence */ -} sl_bt_cs_rtt_type_t; - -/** - * @brief Specifies the ABR channel selection algorithms. - */ -typedef enum -{ - sl_bt_cs_channel_selection_algorithm_3b = 0x0, /**< (0x0) - Use - Channel - Selection - Algorithm - #3b - for - non-mode - 0 ABR - steps */ - sl_bt_cs_channel_selection_algorithm_3c = 0x1, /**< (0x1) - Use - Channel - Selection - Algorithm - #3c - for - non-mode - 0 ABR - steps */ - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved = 0x2 /**< (0x2) - Use - Interleaved - shape - for - user - specified - channel - sequence */ -} sl_bt_cs_channel_selection_algorithm_t; - -/** - * @brief Specifies the ch3c shapes. - */ -typedef enum -{ - sl_bt_cs_ch3c_shape_hat = 0x0, /**< (0x0) Use Hat shape for user - specified channel sequence */ - sl_bt_cs_chc3_shape_interleaved = 0x1 /**< (0x1) Use Interleaved shape for - user specified channel sequence */ -} sl_bt_cs_ch3c_shape_t; - -/** - * @brief Describes the current status of the procedure or subevents. - */ -typedef enum -{ - sl_bt_cs_done_status_complete = 0x0, /**< (0x0) All results - complete for the - ABR procedure or - subevent */ - sl_bt_cs_done_status_partial_results_continue = 0x1, /**< (0x1) Partial - results with more - to follow */ - sl_bt_cs_done_status_current_aborted = 0xfe, /**< (0xfe) Current ABR - procedure or - subevent aborted */ - sl_bt_cs_done_status_all_aborted = 0xff /**< (0xff) Current and - all subsequent - subevents in the - procedure aborted */ -} sl_bt_cs_done_status_t; - -/** - * @brief Describes the abort reasons for ABR procedures and subevents and is - * represented by 4 bits in a byte - */ -typedef enum -{ - sl_bt_cs_abort_reason_no_abort = 0x0, /**< (0x0) Not aborted */ - sl_bt_cs_abort_reason_host_request = 0x1, /**< (0x1) Local or remote - host request */ - sl_bt_cs_abort_reason_insufficient_channels = 0x2, /**< (0x2) Filtered channel - has less than 15 - channels */ - sl_bt_cs_abort_reason_no_map_update = 0x3, /**< (0x3) Channel map - update instant has - passed */ - sl_bt_cs_abort_reason_unspecified = 0xf /**< (0xf) Unspecified - reasons for abortion */ -} sl_bt_cs_abort_reason_t; - -/** - * @brief Specifies the role for the device during ABR procedure. - */ -typedef enum -{ - sl_bt_cs_config_state_removed = 0x0, /**< (0x0) The ABR device configuration - is removed */ - sl_bt_cs_config_state_created = 0x1 /**< (0x1) The ABR device configuration - is created */ -} sl_bt_cs_config_state_t; - -/** - * @addtogroup sl_bt_evt_cs_security_enable_complete sl_bt_evt_cs_security_enable_complete - * @{ - * @brief Indicates that a locally initiated ABR security start procedure has - * completed or the local controller has responded to a channel security request - * from the remote controller - */ - -/** @brief Identifier of the security_enable_complete event */ -#define sl_bt_evt_cs_security_enable_complete_id 0x005900a0 - -/***************************************************************************//** - * @brief Data structure of the security_enable_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_security_enable_complete_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_cs_security_enable_complete_s sl_bt_evt_cs_security_enable_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_security_enable_complete - -/** - * @addtogroup sl_bt_evt_cs_config_complete sl_bt_evt_cs_config_complete - * @{ - * @brief Indicates that a locally initiated ABR configuration procedure has - * completed or the local controller has responded to an ABR configuration - * request from the remote controller - */ - -/** @brief Identifier of the config_complete event */ -#define sl_bt_evt_cs_config_complete_id 0x015900a0 - -/***************************************************************************//** - * @brief Data structure of the config_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_config_complete_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t config_id; /**< ABR configuration - identifier. - - Range: 0 to 3 */ - uint16_t status; /**< SL_STATUS_OK if - successful. Error code - otherwise. */ - uint8_t config_state; /**< Enum @ref - sl_bt_cs_config_state_t. - ABR configuration state - Values: - - sl_bt_cs_config_state_removed - (0x0): The ABR - device configuration - is removed - - sl_bt_cs_config_state_created - (0x1): The ABR - device configuration - is created */ - uint8_t main_mode_type; /**< Enum @ref - sl_bt_cs_mode_t. Main - mode type. Values: - - sl_bt_cs_mode_rtt - (0x1): Round Trip - Time (RTT) - measurement - - sl_bt_cs_mode_pbr - (0x2): - Phase-Based Ranging - (PBR) measurement - - sl_bt_cs_submode_disabled - (0xff): Submode - disabled for the - procedure. */ - uint8_t sub_mode_type; /**< Enum @ref - sl_bt_cs_mode_t. Sub mode - type. Values: - - sl_bt_cs_mode_rtt - (0x1): Round Trip - Time (RTT) - measurement - - sl_bt_cs_mode_pbr - (0x2): - Phase-Based Ranging - (PBR) measurement - - sl_bt_cs_submode_disabled - (0xff): Submode - disabled for the - procedure. */ - uint8_t min_main_mode_steps; /**< Minimum number of ABR - main mode steps to be - executed prior to a sub - mode step. - - Range: 1 to 160 */ - uint8_t max_main_mode_steps; /**< Maximum number of ABR - main mode steps to be - executed prior to a sub - mode step. - - Range: 1 to 160 */ - uint8_t main_mode_repetition; /**< Number of main mode steps - taken from the end of the - last ABR subevent to be - repeated at the beginning - of the current ABR - subevent directly after - the last Mode 0 step of - that event. - - Range: 0 to 3 */ - uint8_t mode_calibration_steps; /**< Number of calibration - mode steps to be included - at the beginning of the - test ABR subevent. - - Range: 1 to 3 */ - uint8_t role; /**< Enum @ref - sl_bt_cs_role_t. Device - role during the ABR - procedure Values: - - sl_bt_cs_role_initiator - (0x0): The device - will initiate the - procedure - - sl_bt_cs_role_reflector - (0x1): The device - will reciprocate - transmission */ - uint8_t rtt_type; /**< Enum @ref - sl_bt_cs_rtt_type_t. RTT - payload type used in the - ABR procedure Values: - - sl_bt_cs_rtt_type_coarse - (0x0): RTT Coarse - - sl_bt_cs_rtt_type_fractional_96_bit_sounding - (0x2): RTT - Fractional with - 96-bit Sounding - Sequence */ - uint8_t cs_sync_phy; /**< Enum @ref - sl_bt_gap_phy_t. Used PHY - for ABR SYNC exchanges - during a procedure - Values: - - sl_bt_gap_phy_1m - (0x1): 1M PHY */ - sl_bt_cs_channel_map_t channel_map; /**< A fixed length byte array - of 10 bytes consisting of - 79 1-bit fields. - - The nth field (in the - range 0 to 78) contains - the value for the ABR - channel index n. - - - Bit value 0: Channel - n is disabled - - Bit value 1: Channel - n is enabled - - The rest of most - significant bits are - reserved for future use - and must be set to 0. - Channels n = 0, 1, 23, - 24, 25, 77 and 78 shall - be ignored and not used - for ABR. At least 15 - channels shall be marked - as used. */ - uint8_t channel_map_repetition; /**< Number of times the - channel_map field will be - cycled through for - non-Mode 0 steps within a - ABR procedure. - - Range: 0x01 to 0xFF */ - uint8_t channel_selection_type; /**< Enum @ref - sl_bt_cs_channel_selection_algorithm_t. - ABR algorithm to be used - during the procedure for - non-mode 0 steps Value: - - sl_bt_cs_channel_selection_algorithm_3b - (0x0): Use - Channel Selection - Algorithm #3b for - non-mode 0 ABR steps - - sl_bt_cs_channel_selection_algorithm_3c - (0x1): Use - Channel Selection - Algorithm #3c for - non-mode 0 ABR steps - - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved - (0x2): Use - Interleaved shape for - user specified - channel sequence */ - uint8_t ch3c_shape; /**< Enum @ref - sl_bt_cs_ch3c_shape_t. - Shape for user-specified - channel sequence Values: - - sl_bt_cs_ch3c_shape_hat - (0x0): Use Hat - shape for user - specified channel - sequence - - sl_bt_cs_chc3_shape_interleaved - (0x1): Use - Interleaved shape for - user specified - channel sequence */ - uint8_t ch3c_jump; /**< Number of channels - skipped in each rising - and falling sequence - - Range: 0x03 to 0x08 */ - uint8_t companion_signal_enable; /**< Enum @ref - sl_bt_cs_companion_signal_status_t. - Enabled or disabled - companion signal status - Values: - - sl_bt_cs_companion_signal_status_disable - (0x0): The - companion signal is - disabled - - sl_bt_cs_companion_signal_status_enable - (0x1): The - companion signal is - enabled */ - uint8_t ip1_time_us; /**< Interlude time in - microseconds between the - RTT packets. Values: - 0x0A, 0x14, 0x1E, 0x28, - 0x32, 0x3C, 0x50, or - 0x91. All other values - are reserved for future - use. */ - uint8_t ip2_time_us; /**< Interlude time in - microseconds between the - CS tones. Values: 0x0A, - 0x14, 0x1E, 0x28, 0x32, - 0x3C, 0x50, or 0x91. All - other values are reserved - for future use. */ - uint8_t fcs_time_us; /**< Time in microseconds for - frequency changes. - Values: 0x0F, 0x14, 0x1E, - 0x28, 0x32, 0x3C, 0x50, - 0x64, 0x78, or 0x96. All - other values are reserved - for future use. */ - uint8_t pm_time_us; /**< Time in microseconds for - the phase measurement - period of the CS tones. - Values: 0x0A, 0x14, or - 0x28. All other values - are reserved for future - use. */ -}); - -typedef struct sl_bt_evt_cs_config_complete_s sl_bt_evt_cs_config_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_config_complete - -/** - * @addtogroup sl_bt_evt_cs_procedure_enable_complete sl_bt_evt_cs_procedure_enable_complete - * @{ - * @brief Indicates the controller has scheduled a new ABR procedure - * measurement, as a result of @ref sl_bt_cs_procedure_enable command or - * disabled an ongoing, as a result of @ref sl_bt_cs_procedure_enable command. - */ - -/** @brief Identifier of the procedure_enable_complete event */ -#define sl_bt_evt_cs_procedure_enable_complete_id 0x025900a0 - -/***************************************************************************//** - * @brief Data structure of the procedure_enable_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_procedure_enable_complete_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t config_id; /**< ABR configuration identifier. - - Range: 0 to 3 */ - uint16_t status; /**< SL_STATUS_OK if successful. Error code - otherwise. */ - uint8_t state; /**< Enum @ref sl_bt_cs_procedure_state_t. - ABR procedure enabled or disabled - Values: - - sl_bt_cs_procedure_state_disabled - (0x0): ABR procedures are - disabled - - sl_bt_cs_procedure_state_enabled - (0x1): ABR procedures are - enabled */ - uint8_t antenna_config; /**< Antenna configuration index - - Range: 0 to 7 */ - int8_t tx_power; /**< Transmit power level used in the - transmission. Units: dBm. - - Range: -127 to +20 - - Value: 0x07F. Transmit power level - is unavailable */ - uint32_t subevent_len; /**< Duration for each subevent in - microseconds - - Range: 1250 μs to 4 s */ - uint8_t subevents_per_interval; /**< Number of subevents anchored off the - same ACL connection event - - Range: 1 to 16 */ - uint16_t subevent_interval; /**< Duration in microseconds between - consecutive ABR subevents anchored off - the same ACL connection event. Units: - 0.625 ms. */ - uint16_t event_interval; /**< Number of ACL connection events between - consecutive ABR event anchor points */ - uint16_t procedure_interval; /**< Number of ACL connection events between - consecutive ABR procedure anchor points */ - uint16_t procedure_count; /**< Number of procedures to continue until - disabled. Maximum number of procedures - to be scheduled. - - Range: 0x01 to 0xFFFF. */ -}); - -typedef struct sl_bt_evt_cs_procedure_enable_complete_s sl_bt_evt_cs_procedure_enable_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_procedure_enable_complete - -/** - * @addtogroup sl_bt_evt_cs_result sl_bt_evt_cs_result - * @{ - * @brief Reports results of every ABR subevent within the ABR procedure - */ - -/** @brief Identifier of the result event */ -#define sl_bt_evt_cs_result_id 0x035900a0 - -/***************************************************************************//** - * @brief Data structure of the result event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_result_s -{ - uint8_t connection; /**< Connection handle. Returns a - SL_BT_INVALID_CONNECTION_HANDLE (0xFF) - when triggered as a result of @ref - sl_bt_cs_test_start command */ - uint8_t config_id; /**< ABR configuration identifier - - Range: 0 to 3 */ - uint16_t start_acl_conn_event; /**< Starting an ACL connection event count - for the results reported in the event. - This is reported only in the first - subevent in the procedure. For - subsequent subevents, this value is - set to 0. */ - uint16_t procedure_counter; /**< Indicates the associated ABR procedure - count for the results reported in this - event */ - int16_t frequency_compensation; /**< Frequency compensation value. Units: - 0.01 ppm (15-bit signed integer). - - Range: -10000 to 10000 - - Value: 0xC000. Frequency - compensation value is not - available or the role is not - initiator. This is reported only - in the first subevent in the - procedure. For subsequent - subevents, this value is set to 0. */ - uint8_t procedure_done_status; /**< Enum @ref sl_bt_cs_done_status_t. - Current status of the ABR procedure - Values: - - sl_bt_cs_done_status_complete - (0x0): All results complete - for the ABR procedure or subevent - - sl_bt_cs_done_status_partial_results_continue - (0x1): Partial results with - more to follow - - sl_bt_cs_done_status_current_aborted - (0xfe): Current ABR procedure - or subevent aborted - - sl_bt_cs_done_status_all_aborted - (0xff): Current and all - subsequent subevents in the - procedure aborted */ - uint8_t subevent_done_status; /**< Enum @ref sl_bt_cs_done_status_t. - Current status of the ABR subevent - Values: - - sl_bt_cs_done_status_complete - (0x0): All results complete - for the ABR procedure or subevent - - sl_bt_cs_done_status_partial_results_continue - (0x1): Partial results with - more to follow - - sl_bt_cs_done_status_current_aborted - (0xfe): Current ABR procedure - or subevent aborted - - sl_bt_cs_done_status_all_aborted - (0xff): Current and all - subsequent subevents in the - procedure aborted */ - uint8_t abort_reason; /**< Enum @ref sl_bt_cs_abort_reason_t. - Indicates the abort reason when the - procedure_done_status or - subevent_done_status is set to 0xF, - otherwise the default value is set to - zero. The first 4 bits are related to - the procedure abort reasons and the - last 4 bits are related to the - subevent done. Values: - - sl_bt_cs_abort_reason_no_abort - (0x0): Not aborted - - sl_bt_cs_abort_reason_host_request - (0x1): Local or remote host - request - - sl_bt_cs_abort_reason_insufficient_channels - (0x2): Filtered channel has - less than 15 channels - - sl_bt_cs_abort_reason_no_map_update - (0x3): Channel map update - instant has passed - - sl_bt_cs_abort_reason_unspecified - (0xf): Unspecified reasons for - abortion */ - int8_t reference_power_level; /**< Reference power level used by the - transmission. Units: dBm. - - Range: -127 to 20 - - Value: 0x07F. The reference power - level is not applicable */ - uint8_t num_antenna_paths; /**< Number of antenna paths supported by - the local controller for the ABR tone - exchanges. - - Range: 1 to 4. The number of - antenna paths used during the - phase measurement stage of the ABR - step - - Value: 0. Phase measurement does - not occur during the ABR step, - therefore ignored */ - uint8_t num_steps; /**< Number of steps in the ABR subevent - for which results are reported. - - Range: 1 to 160 */ - uint8array data; /**< The result data is structured as - follows: - - step_status: 1 octet for each - num_steps. 0x00 for step scheduled - and reported. 0xFE for step - aborted. - - step_mode: 1 octet for each - num_steps. Mode type. Range 0 to - 3. - - step_channel: 1 octet for each - num_steps. Channel index. Range 1 - to 78. - - step_data_length: 1 octet for each - num_steps. Length of mode and role - specific information being - reported. Range 0x00 to 0xFF. - - step_data: step_data_length octet - for each corresponding steps in - num_steps. */ -}); - -typedef struct sl_bt_evt_cs_result_s sl_bt_evt_cs_result_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_result - -/***************************************************************************//** - * - * Start or restart ABR security start procedure for the specified connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_security_enable_complete - Triggered when ABR security - * start procedure has completed. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_security_enable(uint8_t connection); - -/***************************************************************************//** - * - * Set the default ABR settings for the specified connection. By default, all - * roles are disabled and the antenna is set to 1. - * - * @param[in] connection Connection handle - * @param[in] initiator_status Enum @ref sl_bt_cs_role_status_t. Enable or - * disable status of the Initiator role. Values: - * - sl_bt_cs_role_status_disable (0x0): The given role is disabled - * - sl_bt_cs_role_status_enable (0x1): The given role is enabled - * @param[in] reflector_status Enum @ref sl_bt_cs_role_status_t. Enable or - * disable status of the Reflector role. Values: - * - sl_bt_cs_role_status_disable (0x0): The given role is disabled - * - sl_bt_cs_role_status_enable (0x1): The given role is enabled - * @param[in] antenna_identifier Antenna identifier to be used for ABR sync - * packets. - * - Range: 1 to 4 - * @param[in] max_tx_power Maximum transmit power level to be used in all ABR - * transmissions. Units: dBm. - * - Range: -127 to +20 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, - uint8_t initiator_status, - uint8_t reflector_status, - uint8_t antenna_identifier, - int8_t max_tx_power); - -/***************************************************************************//** - * - * Create a new ABR configuration in the local and remote controller. The role - * used in this command must be enabled prior to issuing this command using @ref - * sl_bt_cs_set_default_settings command. - * - * @param[in] connection The connection handle - * @param[in] config_id ABR configuration identifier. - * - Range: 0 to 3 - * @param[in] create_context Defines in which device the created configuration - * will be written - * - Value: 0x00. Write ABR configuration in the local controller only - * - Value: 0x01. Write ABR configuration in both the local and remote - * controller using a configuration procedure - * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] min_main_mode_steps Minimum number of ABR main mode steps to be - * executed prior to a sub mode step. - * - Range: 1 to 160 - * @param[in] max_main_mode_steps Maximum number of ABR main mode steps to be - * executed prior to a sub mode step. - * - Range: 1 to 160 - * @param[in] main_mode_repetition Number of main mode steps taken from the end - * of the last ABR subevent to be repeated at the beginning of the current ABR - * subevent directly after the value r last Mode 0 step of that event. - * - Range: 0 to 3 - * @param[in] mode_calibration_steps Number of Mode 0 steps to be included at - * the beginning of the test ABR subevent - * - Range: 1 to 3 - * @param[in] role Enum @ref sl_bt_cs_role_t. Device's role during the ABR - * procedure Values: - * - sl_bt_cs_role_initiator (0x0): The device will initiate the - * procedure - * - sl_bt_cs_role_reflector (0x1): The device will reciprocate - * transmission - * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in - * the ABR procedure Values: - * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse - * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT - * Fractional with 96-bit Sounding Sequence - * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC - * exchanges during a procedure Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * @param[in] channel_map @parblock - * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. - * - * The nth such field (in the range 0 to 78) contains the value for the ABR - * channel index n. - * - * - Bit value 0: Channel n is disabled - * - Bit value 1: Channel n is enabled - * - * The rest of most significant bits are reserved for future use and must be - * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not - * used for ABR. At least 15 channels shall be marked as used. - * @endparblock - * @param[in] channel_map_repetition Number of times the channel_map field will - * be cycled through for non-Mode 0 steps within an ABR procedure. - * - Range: 0x01 to 0xFF - * @param[in] channel_selection_type Enum @ref - * sl_bt_cs_channel_selection_algorithm_t. Channel selection algorithm Values: - * - sl_bt_cs_channel_selection_algorithm_3b (0x0): Use Channel - * Selection Algorithm #3b for non-mode 0 ABR steps - * - sl_bt_cs_channel_selection_algorithm_3c (0x1): Use Channel - * Selection Algorithm #3c for non-mode 0 ABR steps - * - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved - * (0x2): Use Interleaved shape for user specified channel sequence - * @param[in] ch3c_shape Enum @ref sl_bt_cs_ch3c_shape_t. Ch3c shape Values: - * - sl_bt_cs_ch3c_shape_hat (0x0): Use Hat shape for user specified - * channel sequence - * - sl_bt_cs_chc3_shape_interleaved (0x1): Use Interleaved shape for - * user specified channel sequence - * @param[in] ch3c_jump Number of channels skipped in each rising and falling - * sequence. - * - Range: 2 to 8 - * @param[in] companion_signal_state Enum @ref - * sl_bt_cs_companion_signal_status_t. Companion device's signal status - * Values: - * - sl_bt_cs_companion_signal_status_disable (0x0): The companion - * signal is disabled - * - sl_bt_cs_companion_signal_status_enable (0x1): The companion - * signal is enabled - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration - * procedure completed - * - ******************************************************************************/ -sl_status_t sl_bt_cs_create_config(uint8_t connection, - uint8_t config_id, - uint8_t create_context, - uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t min_main_mode_steps, - uint8_t max_main_mode_steps, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - const sl_bt_cs_channel_map_t *channel_map, - uint8_t channel_map_repetition, - uint8_t channel_selection_type, - uint8_t ch3c_shape, - uint8_t ch3c_jump, - uint8_t companion_signal_state); - -/***************************************************************************//** - * - * Remove an ABR configuration from the local controller. - * - * @param[in] connection Connection handle - * @param[in] config_id ABR configuration identifier - * - Range: 0 to 3 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration - * procedure is completed - * - ******************************************************************************/ -sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id); - -/***************************************************************************//** - * - * Update the channel classification for ABR. This classification persists until - * overwritten with a subsequent command or until the system is reset. - * - * @param[in] channel_map @parblock - * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. - * - * The nth field (in the range 0 to 78) contains the value for the link layer - * channel index n. - * - * - Bit value 0: Channel n is disabled. - * - Bit value 1: Channel n is enabled. - * - * The rest of most significant bits are reserved for future use and must be - * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not - * used for ABR. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map); - -/***************************************************************************//** - * - * Set the parameters for scheduling ABR procedures with the remote device. - * - * @param[in] connection The connection handle - * @param[in] config_id ABR configuration identifier. - * - Range: 0 to 3. - * @param[in] max_procedure_len Maximum duration for each measurement procedure. - * Value in units of 0.625 ms. - * - Range: 0x0001 to 0xFFFF. - * - Time: N x 0.625ms. N being the input. - * - Time range: 0.625 ms to 40.959375 s. - * @param[in] min_procedure_interval Minimum duration in number of connection - * events between consecutive measurement procedure. - * - Range: 0x01 to 0xFFFF. - * @param[in] max_procedure_interval Maximum duration in number of connection - * events between consecutive measurement procedure. - * - Range: 0x01 to 0xFFFF. - * @param[in] max_procedure_count Maximum number of ABR procedures to be - * scheduled - * - Range: 0x01 to 0xFFFF: Maximum number of procedures to be scheduled. - * - Value: 0x00. Procedures to continue until disabled. - * @param[in] min_subevent_len Minimum suggested duration for each ABR subevent. - * Units: microseconds. - * - Range: 0x01 to 0xFFFFFF - * - Time range: 1250 us to 4s - * @param[in] max_subevent_len Maximum suggested duration for each ABR subevent. - * Units: microseconds. - * - Range: 0x01 to 0xFFFFFF - * - Time range: 1250 us to 4s - * @param[in] tone_antenna_config_selection Antenna configuration index - * - Range: 0 to 7 - * @param[in] phy Enum @ref sl_bt_gap_phy_t. PHY on which the ABR transmission - * will take place Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports - * @param[in] tx_pwr_delta Transmit power delta. Units: dB. - * - Value: 0x80. Host does not have a recommendation for transmit power - * delta - * @param[in] preferred_peer_antenna Preferred peer-ordered antenna elements to - * be used by the remote device for the antenna configuration denoted by the - * tone antenna config selection. - * - Bit 0: Use first ordered antenna element - * - Bit 1: Use second ordered antenna element - * - Bit 2: Use third ordered antenna element - * - Bit 3: Use fourth ordered antenna element - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, - uint8_t config_id, - uint16_t max_procedure_len, - uint16_t min_procedure_interval, - uint16_t max_procedure_interval, - uint16_t max_procedure_count, - uint32_t min_subevent_len, - uint32_t max_subevent_len, - uint8_t tone_antenna_config_selection, - uint8_t phy, - int8_t tx_pwr_delta, - uint8_t preferred_peer_antenna); - -/***************************************************************************//** - * - * Enable or disable scheduling ABR procedures with the remote device. - * - * @param[in] connection The connection handle - * @param[in] enable Enum @ref sl_bt_cs_procedure_state_t. Enabled or disabled - * ABR procedure state. Values: - * - sl_bt_cs_procedure_state_disabled (0x0): ABR procedures are - * disabled - * - sl_bt_cs_procedure_state_enabled (0x1): ABR procedures are - * enabled - * @param[in] config_id ABR configuration identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_procedure_enable_complete - Triggered when local - * controller has scheduled or disabled an ABR procedure measurement - * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to - * report for every ABR event within the ABR procedure - * - ******************************************************************************/ -sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, - uint8_t enable, - uint8_t config_id); - -/***************************************************************************//** - * - * Set the antenna configuration for the ABR feature. - * - * @param[in] antenna_element_offset_len Length of data in @p - * antenna_element_offset - * @param[in] antenna_element_offset Offset of each antenna, each element is a - * signed 16-bit integer stored in two consecutive bytes in little-endian - * order. Units: 1 cm. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, - const uint8_t* antenna_element_offset); - -/***************************************************************************//** - * - * Read the ABR capabilities of the local controller. - * - * @param[out] num_config The number of ABR configurations supported per - * connection. - * - Range: 0x01-0x04 - * @param[out] max_consecutive_procedures The maximum number of consecutive ABR - * procedures supported. - * - 0x00: Fixed number of consecutive procedures and for an - * indefinite number of procedures until termination - * - 0x0001-0xFFFF: Maximum number of consecutive procedures - * supported - * @param[out] num_antennas The number of antenna elements available for ABR - * tone exchanges. - * - Range: 0x01-0x04 - * @param[out] max_antenna_paths The maximum number of antenna paths supported. - * - Range: 0x01-0x04 - * @param[out] roles This value is a bitmask of flags to indicate which ABR - * roles are supported by the controller. Flags: - * - 0x01, bit 0: Initiator role - * - 0x02, bit 1: Reflector role - * @param[out] optional_modes This value is a bitmask of flags to indicate which - * Optional ABR modes are supported. Flags: - * - 0x02, bit 0: Mode 3 is supported - * @param[out] rtt_capability This value is a bitmask of flags to indicate which - * Round Trip Time (RTT) ABR capabilities accuracy requirement in @p - * rtt_aa_only_n, @p rtt_sounding_n, and @p rtt_random_payload. Flags: - * - 0x01, bit 0: 10 ns time-of-flight (ToF) precision requirement - * for @p rtt_aa_only if set; otherwise 150 ns ToF - * - 0x02, bit 1: 10 ns ToF precision requirement for @p rtt_sounding - * if set; otherwise 150 ns ToF - * - 0x04, bit 2: 10 ns ToF precision requirement for @p - * rtt_random_payload if set; otherwise 150 ns ToF - * @param[out] rtt_aa_only RTT Access Address(AA) is supported by the controller - * - 0x00: RTT AA Only is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] rtt_sounding RTT Sounding is supported by the controller - * - 0x00: RTT Sounding is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] rtt_random_payload RTT Random Payload is supported by the - * controller - * - 0x00: RTT Random Payload is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] optional_cs_sync_phys This value is a bitmask of flags to - * indicate which ABR SYNC packages supported in an specific PHY. Flags: - * - 0x02, bit 1: LE 2M PHY ABR SYNC packages are supported - * @param[out] optional_subfeatures This value is a bitmask of flags to indicate - * which Optional ABR subfeatures supported is supported. Flags: - * - 0x01, bit 0: ABR Companion Signal is supported - * - 0x02, bit 1: ABR with zero Frequency Actuation Error relative to - * Mode 0 transmissions in reflector role is supported - * - 0x04, bit 2: ABR Channel Selection Algorithm #3c is supported - * - 0x08, bit 3: ABR phase-based ranging from a sounding sequence is - * supported - * @param[out] optional_t_ip1_times This value is a bitmask of flags to indicate - * which Time for Interlude Period 1 (IP1) supported is supported. Flags: - * - 0x0001, bit 0: Time durantion of 10 microseconds is supported - * - 0x0002, bit 1: Time durantion of 20 microseconds is supported - * - 0x0004, bit 2: Time durantion of 30 microseconds is supported - * - 0x0008, bit 3: Time durantion of 40 microseconds is supported - * - 0x0010, bit 4: Time durantion of 50 microseconds is supported - * - 0x0020, bit 5: Time durantion of 60 microseconds is supported - * - 0x0040, bit 6: Time durantion of 80 microseconds is supported - * @param[out] optional_t_ip2_times This value is a bitmask of flags to indicate - * which Time for Interlude Period 2 (IP2) supported is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * - 0x0004, bit 2: Time duration of 30 microseconds is supported - * - 0x0008, bit 3: Time duration of 40 microseconds is supported - * - 0x0010, bit 4: Time duration of 50 microseconds is supported - * - 0x0020, bit 5: Time duration of 60 microseconds is supported - * - 0x0040, bit 6: Time duration of 80 microseconds is supported - * @param[out] optional_t_fcs_times This value is a bitmask of flags to indicate - * which Time for Frequency Change Spaceing (FCS) is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * - 0x0004, bit 2: Time duration of 30 microseconds is supported - * - 0x0008, bit 3: Time duration of 40 microseconds is supported - * - 0x0010, bit 4: Time duration of 50 microseconds is supported - * - 0x0020, bit 5: Time duration of 60 microseconds is supported - * - 0x0040, bit 6: Time duration of 80 microseconds is supported - * - 0x0100, bit 7: Time duration of 100 microseconds is supported - * - 0x0200, bit 8: Time duration of 120 microseconds is supported - * @param[out] optional_t_pm_times This value is a bitmask of flags to indicate - * which Time for Phase Measurement (PM) supported is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * @param[out] t_sw_times Time in microseconds for the antenna switch period of - * the ABR tones. - * - Values: 0x02, 0x02, 0x04 and 0x0A - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, - uint16_t *max_consecutive_procedures, - uint8_t *num_antennas, - uint8_t *max_antenna_paths, - uint8_t *roles, - uint8_t *optional_modes, - uint8_t *rtt_capability, - uint8_t *rtt_aa_only, - uint8_t *rtt_sounding, - uint8_t *rtt_random_payload, - uint8_t *optional_cs_sync_phys, - uint16_t *optional_subfeatures, - uint16_t *optional_t_ip1_times, - uint16_t *optional_t_ip2_times, - uint16_t *optional_t_fcs_times, - uint16_t *optional_t_pm_times, - uint8_t *t_sw_times); - -/** @} */ // end addtogroup sl_bt_cs - -/** - * @addtogroup sl_bt_cs_test Accurate Bluetooth Ranging Test - * @{ - * - * @brief Accurate Bluetooth Ranging Test - * - * This class provides optional test commands and events for ABR between - * Bluetooth devices. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cs_test_start_id 0x005a0020 -#define sl_bt_rsp_cs_test_start_id 0x005a0020 - -/** - * @brief Defines tone extension for ABR test - */ -typedef enum -{ - sl_bt_cs_test_tone_extension_both_without = 0x0, /**< (0x0) Initiator and - Reflector tones - sent without tone - extension */ - sl_bt_cs_test_tone_extension_reflector_without = 0x1, /**< (0x1) Initiator - tone sent with - extension; - Reflector tone sent - without extension */ - sl_bt_cs_test_tone_extension_initiator_without = 0x2, /**< (0x2) Initiator - tone sent without - extension; - Reflector tone sent - with extension */ - sl_bt_cs_test_tone_extension_both_with = 0x3, /**< (0x3) Initiator and - Reflector tones - sent with extension */ - sl_bt_cs_test_tone_extension_round_robin = 0x4 /**< (0x4) Loop through - values 0x00 to 0x03 */ -} sl_bt_cs_test_tone_extension_t; - -/** - * @brief This defines sounding sequence marker for ABR test - */ -typedef enum -{ - sl_bt_cs_test_sounding_sequence_marker_1 = 0x0, /**< (0x0) Use - 0b0011 as the - Sounding - Sequence marker */ - sl_bt_cs_test_sounding_sequence_marker_2 = 0x1, /**< (0x1) Use - 0b1100 as the - Sounding - Sequence marker */ - sl_bt_cs_test_sounding_sequence_marker_round_robin = 0x2 /**< (0x2) Loop - through 0b0011 - and 0b1100 */ -} sl_bt_cs_test_sounding_sequence_marker_t; - -/***************************************************************************//** - * - * Start a single ABR procedure using the given configuration. The reflector - * must be initialized before starting the initiator. To stop an ongoing test, - * use the @ref sl_bt_test_dtm_end command. - * - * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values : - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] main_mode_repetition Number of main mode steps taken from the end - * of the last ABR subevent to be repeated at the beginning of the current ABR - * subevent directly after the last Mode 0 step of that event. - * - Range: 0 to 3 - * @param[in] mode_calibration_steps Number of calibration mode steps to be - * included at the beginning of the test ABR subevent - * - Range: 1 to 3 - * @param[in] role Enum @ref sl_bt_cs_role_t. Role during ABR procedure Values: - * - sl_bt_cs_role_initiator (0x0): The device will initiate the - * procedure - * - sl_bt_cs_role_reflector (0x1): The device will reciprocate - * transmission - * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in - * the ABR procedure Values: - * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse - * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT - * Fractional with 96-bit Sounding Sequence - * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC - * exchanges during a procedure Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports - * @param[in] antenna_selection Antenna Identifier to be used for RTT packets - * - Range: 1 to 4 - * @param[in] subevent_len ABR subevent length in units of microseconds. - * @param[in] subevent_interval Interval between the start of two consecutive - * ABR events. Units: 0.625 ms. - * - Value: 0x0000. Single ABR subevent - * @param[in] tx_power Transmit power level for the transmission. Units: dBm. - * - Range: -127 to +20 - * - Value: 0x7E. Set transmitter to minimum transmit power level - * - Value: 0x7F. Set transmitter to maximum transmit power level - * @param[in] t_ip1_time Idle time in microseconds between the RTT packets - * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 - * @param[in] t_ip2_time Interlude time in microseconds between the ABR tones - * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 - * @param[in] t_fcs_time Time in microseconds for frequency changes - * - Values: 15, 20, 30, 40, 50, 60, 80, 100, 120 or 150 - * @param[in] t_pm_time Time in microseconds for the phase measurement period of - * the ABR tones - * - Values: 10, 20 or 40 - * @param[in] t_sw_time Time in microseconds for the antenna switch period of - * the ABR tones - * - Values: 0, 1, 2, 4 or 10 - * @param[in] tone_antenna_config Antenna Configuration Index used during - * antenna switching - * - Range: 0 to 7 - * @param[in] companion_signal_state Enum @ref - * sl_bt_cs_companion_signal_status_t. Enable or disable status of the - * companion signal. Values: - * - sl_bt_cs_companion_signal_status_disable (0x0): The companion - * signal is disabled - * - sl_bt_cs_companion_signal_status_enable (0x1): The companion - * signal is enabled - * @param[in] drbg_nonce Antenna Configuration Index used during antenna - * switching - * - Range: 0 to 7 - * @param[in] override_config Configuration of the parameters in - * override_parameters - * - Bit 0: The channel sequence for the subevent is determined by the - * values of channel map repetition, channel length, and channel - * parameters. - * - Bit 2: The number of main mode ABR steps to be executed before a sub - * mode ABR step during the ABR procedure is determined by the value of - * main mode steps parameter. - * - Bit 3: The transmission of tone extensions within each Mode 2 or Mode 3 - * step is determined by the value of T_PM_Tone_Ext parameter. - * - Bit 4: The Tone antenna permutation index for each Mode 2 or Mode 3 - * step is determined by the value of Tone_Antenna_Permutation parameter. - * - Bit 5: The ABR Access Address of all packets sent by the initiator is - * determined by ABR_SYNC_AA_Initiator parameter. The ABR Access Address - * of all packets sent by the reflector is determined by - * ABR_SYNC_AA_Reflector parameter. - * B - * - Bit 6: The Marker positions for each ABR SYNC packet with a marker is - * determined by the value of SS_Marker1_Position and SS_Marker2_Position - * parameters. - * - Bit 7: The Marker value for each marker within a ABR SYNC packet is - * determined by SS_Marker_Value parameter. - * - Bit 8: The payload of the ABR SYNC packet is determined by the value of - * ABR_SYNC_Payload_Pattern parameter. - * - Bit 10: Stable Phase test - * @param[in] override_parameters_len Length of data in @p override_parameters - * @param[in] override_parameters Variable set of parameters which are present - * dependent on the bits set in the override config parameter. - * - Bit 0: channel_map_repetition, channel_length and channel - * - Bit 2: main_mode_steps - * - Bit 3: t_pm_tone_ext - * - Bit 4: tone_antenna_permutation - * - Bit 5: aa_initiator and aa_reflector - * - Bit 6: ss_marker1_position and ss_marker2_position - * - Bit 7: ss_marker_value - * - Bit 8: ABR_SYNC_Payload_Pattern and ABR_SYNC_User_Payload - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to - * report for every ABR subevent within the ABR procedure - * - ******************************************************************************/ -sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - uint8_t antenna_selection, - const sl_bt_cs_subevent_length_t *subevent_len, - uint16_t subevent_interval, - int8_t tx_power, - uint8_t t_ip1_time, - uint8_t t_ip2_time, - uint8_t t_fcs_time, - uint8_t t_pm_time, - uint8_t t_sw_time, - uint8_t tone_antenna_config, - uint8_t companion_signal_state, - uint16_t drbg_nonce, - uint16_t override_config, - size_t override_parameters_len, - const uint8_t* override_parameters); - -/** @} */ // end addtogroup sl_bt_cs_test - -/** - * @addtogroup sl_bt_l2cap L2CAP Connection Oriented Channels - * @{ - * - * @brief L2CAP Connection Oriented Channels - * - * The commands and events in this class provide Logical Link Control and - * Adaptation Protocol (L2CAP) credit-based logical channels. - * - * An L2CAP credit-based logical channel is a logical link identified by a - * channel identifier (the @p cid parameter in the commands and events of this - * API class). These channels use a credit-based flow control mechanism. The - * credit can be configured at the channel opening and later dynamically updated - * on the channel. - * - * The Simplified Protocol/Service Multiplexer (SPSM) of a channel specifies the - * protocol or services the channel implements. It can be a value for a fixed - * service assigned by the Bluetooth SIG or a dynamically-allocated value and - * used with services defined in the GATT Server. The dynamically-assigned value - * may be used to support multiple implementations of a particular protocol. See - * the Bluetooth core specification for more details. The application specifies - * the SPSM value in a channel open request in the @p spsm parameter of the @ref - * sl_bt_l2cap_open_le_channel command. - * - * Each of the local and peer channel endpoints must specify the maximum Service - * Data Unit (SDU) size (the 'MTU' field of the L2CAP packets in the Bluetooth - * Core specification) that it can receive on the channel. The application - * specifies the maximum Service Data Unit size (the @p max_sdu parameter in - * commands and events) of the local channel endpoint. - * - * Each channel endpoint has a maximum PDU payload Size that the L2CAP layer can - * receive in a single data packet on the channel. The maximum PDU payload size - * supported by the stack for local channel endpoints is 252 bytes, which is the - * maximum data length the @ref sl_bt_evt_l2cap_channel_data event can support. - * The application specifies the max PDU payload size (the @p max_pdu parameter - * in commands and events). Additionally, the application is responsible for - * handling the segmentation from SDU to PDU and reassembly from PDU to SDU. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_l2cap_open_le_channel_id 0x01430020 -#define sl_bt_cmd_l2cap_send_le_channel_open_response_id 0x02430020 -#define sl_bt_cmd_l2cap_channel_send_data_id 0x03430020 -#define sl_bt_cmd_l2cap_channel_send_credit_id 0x04430020 -#define sl_bt_cmd_l2cap_close_channel_id 0x05430020 -#define sl_bt_rsp_l2cap_open_le_channel_id 0x01430020 -#define sl_bt_rsp_l2cap_send_le_channel_open_response_id 0x02430020 -#define sl_bt_rsp_l2cap_channel_send_data_id 0x03430020 -#define sl_bt_rsp_l2cap_channel_send_credit_id 0x04430020 -#define sl_bt_rsp_l2cap_close_channel_id 0x05430020 - -/** - * @brief Defines possible result values in the responses to credit based - * channel connection requests. - */ -typedef enum -{ - sl_bt_l2cap_connection_result_successful = 0x0, /**< (0x0) - Connection - successful */ - sl_bt_l2cap_connection_result_spsm_not_supported = 0x2, /**< (0x2) - Connection - refused - \- - SPSM - not - supported */ - sl_bt_l2cap_connection_result_no_resources_available = 0x4, /**< (0x4) - Connection - refused - \- no - resources - available */ - sl_bt_l2cap_connection_result_insufficient_authentication = 0x5, /**< (0x5) - Connection - refused - \- - insufficient - authentication */ - sl_bt_l2cap_connection_result_insufficient_authorization = 0x6, /**< (0x6) - Connection - refused - \- - insufficient - authorization */ - sl_bt_l2cap_connection_result_encryption_key_size_too_short = 0x7, /**< (0x7) - Connection - refused - \- - encryption - key - size - too - short */ - sl_bt_l2cap_connection_result_insufficient_encryption = 0x8, /**< (0x8) - Connection - refused - \- - insufficient - encryption */ - sl_bt_l2cap_connection_result_invalid_source_cid = 0x9, /**< (0x9) - Connection - refused - \- - invalid - Source - CID */ - sl_bt_l2cap_connection_result_source_cid_already_allocated = 0xa, /**< (0xa) - Connection - refused - \- - Source - CID - already - allocated */ - sl_bt_l2cap_connection_result_unacceptable_parameters = 0xb /**< (0xb) - Connection - refused - \- - unacceptable - parameters */ -} sl_bt_l2cap_connection_result_t; - -/** - * @brief Describes why a request command was rejected. - */ -typedef enum -{ - sl_bt_l2cap_command_not_understood = 0x0, /**< (0x0) Command not understood - e.g., unknown command code */ - sl_bt_l2cap_signaling_mtu_exceeded = 0x1, /**< (0x1) Command size has exceeded - the signaling MTU size */ - sl_bt_l2cap_invalid_cid_request = 0x2 /**< (0x2) An invalid CID is - included in the command */ -} sl_bt_l2cap_command_reject_reason_t; - -/** - * @brief Describes which of the request commands has been rejected. - */ -typedef enum -{ - sl_bt_l2cap_disconnection_request = 0x6, /**< (0x6) A disconnection request */ - sl_bt_l2cap_le_connection_request = 0x14, /**< (0x14) An LE credit-based - connection request */ - sl_bt_l2cap_flow_control_credit = 0x16 /**< (0x16) A Flow Control Credit - packet */ -} sl_bt_l2cap_command_code_t; - -/** - * @addtogroup sl_bt_evt_l2cap_le_channel_open_request sl_bt_evt_l2cap_le_channel_open_request - * @{ - * @brief Indicates that an LE credit-based connection request on a Bluetooth - * connection is received - * - * The application must respond with the @ref - * sl_bt_l2cap_send_le_channel_open_response command. - */ - -/** @brief Identifier of the le_channel_open_request event */ -#define sl_bt_evt_l2cap_le_channel_open_request_id 0x014300a0 - -/***************************************************************************//** - * @brief Data structure of the le_channel_open_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_request_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t spsm; /**< The protocol/services implemented by the peer - channel endpoint */ - uint16_t cid; /**< The channel identifier on the local device */ - uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer - channel endpoint */ - uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel - endpoint */ - uint16_t credit; /**< The initial credit value of the peer channel - endpoint, i.e., number of PDUs that the local - channel endpoint can send */ - uint16_t remote_cid; /**< The channel identifier on the peer device */ -}); - -typedef struct sl_bt_evt_l2cap_le_channel_open_request_s sl_bt_evt_l2cap_le_channel_open_request_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_request - -/** - * @addtogroup sl_bt_evt_l2cap_le_channel_open_response sl_bt_evt_l2cap_le_channel_open_response - * @{ - * @brief Indicates that an LE credit-based connection response is received - * - * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode - * implies that the logical channel is established and data can be sent or - * received on the channel. - * - * If the connection request was rejected by the peer, indicated by @p - * errorcode, the stack automatically closes the local channel and the user - * application should clean up the resources associated to the channel - * identifier. - */ - -/** @brief Identifier of the le_channel_open_response event */ -#define sl_bt_evt_l2cap_le_channel_open_response_id 0x024300a0 - -/***************************************************************************//** - * @brief Data structure of the le_channel_open_response event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_response_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the - response is received */ - uint16_t cid; /**< The channel identifier on the local device */ - uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer - channel endpoint */ - uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel - endpoint */ - uint16_t credit; /**< The initial credit value of the peer channel - endpoint, i.e., number of PDUs the local channel - endpoint can send */ - uint16_t errorcode; /**< Enum @ref sl_bt_l2cap_connection_result_t. - - An L2CAP error code as the outcome of the connection - request. - - Result @ref sl_bt_l2cap_connection_result_successful - indicates the connection request was accepted and - the logical channel is established. Other error code - value indicates the connection request was refused - by the peer device and other parameters of this - event must be ignored. */ - uint16_t remote_cid; /**< The channel identifier on the peer device */ -}); - -typedef struct sl_bt_evt_l2cap_le_channel_open_response_s sl_bt_evt_l2cap_le_channel_open_response_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_response - -/** - * @addtogroup sl_bt_evt_l2cap_channel_data sl_bt_evt_l2cap_channel_data - * @{ - * @brief Indicates that data is received on a channel - * - * Each event should contain a K-frame of payload. The length of SDU should be - * specified in the first 2 bytes of the first K-frame. The sum of the payload - * lengths in received K-frames should be equal to the specified SDU length. - * Otherwise, application should disconnect the channel using @ref - * sl_bt_l2cap_close_channel command. The same should happen also if the SDU - * length exceeds the max_sdu of local channel endpoint. - */ - -/** @brief Identifier of the channel_data event */ -#define sl_bt_evt_l2cap_channel_data_id 0x034300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_data_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t cid; /**< The channel identifier */ - uint8array data; /**< Data received */ -}); - -typedef struct sl_bt_evt_l2cap_channel_data_s sl_bt_evt_l2cap_channel_data_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_data - -/** - * @addtogroup sl_bt_evt_l2cap_channel_credit sl_bt_evt_l2cap_channel_credit - * @{ - * @brief Indicates that flow control credits are received on a channel - * informing that the peer channel endpoint is capable of receiving more data - */ - -/** @brief Identifier of the channel_credit event */ -#define sl_bt_evt_l2cap_channel_credit_id 0x044300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_credit event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_credit_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the credit - is received */ - uint16_t cid; /**< The channel identifier */ - uint16_t credit; /**< The credit value, i.e., the additional number of - PDUs the peer channel endpoint can receive */ -}); - -typedef struct sl_bt_evt_l2cap_channel_credit_s sl_bt_evt_l2cap_channel_credit_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_credit - -/** - * @addtogroup sl_bt_evt_l2cap_channel_closed sl_bt_evt_l2cap_channel_closed - * @{ - * @brief Indicates that a credit-based logical channel is closed by the local - * or peer device. - */ - -/** @brief Identifier of the channel_closed event */ -#define sl_bt_evt_l2cap_channel_closed_id 0x054300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_closed_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t cid; /**< The channel identifier */ - uint16_t reason; /**< The disconnection reason */ -}); - -typedef struct sl_bt_evt_l2cap_channel_closed_s sl_bt_evt_l2cap_channel_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_closed - -/** - * @addtogroup sl_bt_evt_l2cap_command_rejected sl_bt_evt_l2cap_command_rejected - * @{ - * @brief Indicates that the peer device rejected a command - * - * This might happen if, for example, the device does not support the feature or - * the command has an incorrect CID. - */ - -/** @brief Identifier of the command_rejected event */ -#define sl_bt_evt_l2cap_command_rejected_id 0x064300a0 - -/***************************************************************************//** - * @brief Data structure of the command_rejected event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_command_rejected_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the event - is received */ - uint8_t code; /**< Enum @ref sl_bt_l2cap_command_code_t. Code of the - rejected command */ - uint16_t reason; /**< Enum @ref sl_bt_l2cap_command_reject_reason_t. The - rejection reason */ - uint16_t cid; /**< The channel identifier */ -}); - -typedef struct sl_bt_evt_l2cap_command_rejected_s sl_bt_evt_l2cap_command_rejected_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_command_rejected - -/***************************************************************************//** - * - * Create and configure an L2CAP channel on a Bluetooth connection using the LE - * credit based connection request packet. Event @ref - * sl_bt_evt_l2cap_le_channel_open_response or @ref - * sl_bt_evt_l2cap_command_rejected will be received after the peer device - * responded to the request. - * - * @param[in] connection The connection handle - * @param[in] spsm The protocol/services implemented by the local channel - * endpoint - * @param[in] max_sdu @parblock - * The Maximum Service Data Unit size the local channel endpoint can accept - * - * Range: 23 to 65533. - * @endparblock - * @param[in] max_pdu @parblock - * The maximum PDU payload size the local channel endpoint can accept - * - * Range: 23 to 252. - * @endparblock - * @param[in] credit The initial credit value of the local channel endpoint, - * i.e., number of PDUs the peer channel endpoint can send - * @param[out] cid The channel identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_l2cap_command_rejected - Triggered when the peer device - * rejected the connection request. Typically a legacy peer device that does - * not support the feature could send this response. When this event is - * received under the context of opening a channel using this command, the - * stack automatically closes the local channel and the user application - * should clean up the resources associated to the channel identifier. - * - @ref sl_bt_evt_l2cap_le_channel_open_response - Triggered when an LE - * credit-based connection response has been received in response to this - * command. If the result code in @p errorcode of the event is not equal to - * @ref sl_bt_l2cap_connection_result_successful, it means that connection - * request was rejected by the peer device. In this case, the stack - * automatically closes the local channel and the user application should - * clean up the resources associated to the channel identifier. - * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an LE credit-based - * connection response has not been received within 30 seconds after this - * command has been issued. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, - uint16_t spsm, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t *cid); - -/***************************************************************************//** - * - * Send an LE credit-based connection response to an LE credit-based connection - * request received in the @ref sl_bt_evt_l2cap_le_channel_open_request event. - * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode - * implies that the logical channel is established and data can be sent or - * received on the channel. - * - * To reject the connection request, use a result code other than - * sl_bt_l2cap_connection_result_successful in @p errorcode. Other parameters in - * this command are ignored in this case. The stack automatically closes the - * local channel and the user application should clean up the resources - * associated to the channel identifier. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] max_sdu @parblock - * The Maximum Service Data Unit size the local channel endpoint can accept - * - * Range: 23 to 65533. - * @endparblock - * @param[in] max_pdu @parblock - * The maximum PDU payload size the local channel endpoint can accept - * - * Range:23 to 252. - * @endparblock - * @param[in] credit The initial credit value of the local channel endpoint, - * i.e., number of PDUs that the peer channel endpoint can send - * @param[in] errorcode Enum @ref sl_bt_l2cap_connection_result_t. An L2CAP - * error code as the outcome of the connection request - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, - uint16_t cid, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t errorcode); - -/***************************************************************************//** - * - * Send data to the peer channel endpoint on a Bluetooth connection. If the SDU - * length is larger than max_pdu size or 250 bytes, the application should - * fragment the SDU into multiple K-frames and call this command once for each - * K-frame. - * - * The first K-frame of the SDU should start with 2 bytes of SDU length followed - * with payload. Therefore, the first K-frame contains PDU length minus 2 bytes - * of the actual payload. All subsequent K-frames of the same SDU contain PDU - * length of the payload. The sum of the payload lengths for K-frames should be - * equal to the specified SDU length. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be sent. The data length must not be greater than the - * lesser of the peer channel endpoint max_pdu and 252 bytes, which is the - * maximum data length this command can send. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, - uint16_t cid, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Send flow control credits to the peer channel endpoint indicating that the - * local channel endpoint is capable of receiving more data. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] credit @parblock - * The credit value, i.e., the additional number of PDUs the peer channel - * endpoint can send - * - * Range: 1 to 65535. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, - uint16_t cid, - uint16_t credit); - -/***************************************************************************//** - * - * Send a disconnect request to close a credit-based logical channel. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an credit-based - * logical channel is closed in response to this command. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid); - -/** @} */ // end addtogroup sl_bt_l2cap - -/** - * @addtogroup sl_bt_cte_transmitter CTE Transmitter - * @{ - * - * @brief CTE Transmitter - * - * Commands and events in this class manage Constant Tone Extension (CTE) - * transmission. - * - * CTE feature is only supported by specific devices. Commands from this class - * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cte_transmitter_set_dtm_parameters_id 0x04440020 -#define sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id 0x05440020 -#define sl_bt_cmd_cte_transmitter_enable_connection_cte_id 0x00440020 -#define sl_bt_cmd_cte_transmitter_disable_connection_cte_id 0x01440020 -#define sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id 0x02440020 -#define sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id 0x03440020 -#define sl_bt_cmd_cte_transmitter_enable_silabs_cte_id 0x06440020 -#define sl_bt_cmd_cte_transmitter_disable_silabs_cte_id 0x07440020 -#define sl_bt_rsp_cte_transmitter_set_dtm_parameters_id 0x04440020 -#define sl_bt_rsp_cte_transmitter_clear_dtm_parameters_id 0x05440020 -#define sl_bt_rsp_cte_transmitter_enable_connection_cte_id 0x00440020 -#define sl_bt_rsp_cte_transmitter_disable_connection_cte_id 0x01440020 -#define sl_bt_rsp_cte_transmitter_enable_connectionless_cte_id 0x02440020 -#define sl_bt_rsp_cte_transmitter_disable_connectionless_cte_id 0x03440020 -#define sl_bt_rsp_cte_transmitter_enable_silabs_cte_id 0x06440020 -#define sl_bt_rsp_cte_transmitter_disable_silabs_cte_id 0x07440020 - -/***************************************************************************//** - * - * Set the CTE-related parameters of the LE transmitter test. - * - * @param[in] cte_length @parblock - * The length of the Constant Tone Extension in 8 us units - * - 0: No CTE - * - 0x02 to 0x14: CTE length - * - * Default: 0 (no CTE) - * @endparblock - * @param[in] cte_type @parblock - * CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * - * Default: 0 - * @endparblock - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. This can be - * an empty array if CTE is unused. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Clear CTE-related parameters that were previously set for LE transmitter - * test. Default values will be restored for these parameters. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters(); - -/***************************************************************************//** - * - * Enable different types of CTE responses on a connection. CTE response will be - * sent once requested by the peer device using the CTE Request procedure. - * - * @param[in] connection Connection handle - * @param[in] cte_types CTE types. Bitmask of the following: - * - Bit 0: AoA CTE response - * - Bit 1: AoD CTE response with 1 us slots - * - Bit 2: AoD CTE response with 2 us slots - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, - uint8_t cte_types, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable CTE responses on a connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection); - -/***************************************************************************//** - * - * Start a connectionless CTE transmit. CTEs will be transmitted in periodic - * advertisement packets. As a result, a periodic advertising has to be started - * prior to this command. - * - * @param[in] handle Periodic advertising handle - * @param[in] cte_length CTE length in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] cte_count The number of CTEs to be transmitted in each periodic - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop the connectionless CTE transmit. - * - * @param[in] handle Periodic advertising handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle); - -/***************************************************************************//** - * - * Enable Silicon Labs CTE transmit. CTEs will be transmitted in extended - * advertisement packets. As a result, extended advertising has to be started - * prior this command. - * - * @param[in] handle Advertising handle - * @param[in] cte_length CTE length in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] cte_count The number of CTEs to be transmitted in each extended - * advertising interval. Currently, only cte_count = 1 is supported. - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable Silicon Labs CTE transmit. - * - * @param[in] handle Advertising handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle); - -/** @} */ // end addtogroup sl_bt_cte_transmitter - -/** - * @addtogroup sl_bt_cte_receiver CTE Receiver - * @{ - * - * @brief CTE Receiver - * - * Commands and events in this class manage Constant Tone Extension (CTE) - * receiving. - * - * CTE feature is only supported by specific devices. Commands from this class - * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cte_receiver_set_dtm_parameters_id 0x05450020 -#define sl_bt_cmd_cte_receiver_clear_dtm_parameters_id 0x06450020 -#define sl_bt_cmd_cte_receiver_set_sync_cte_type_id 0x09450020 -#define sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 -#define sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id 0x0b450020 -#define sl_bt_cmd_cte_receiver_configure_id 0x00450020 -#define sl_bt_cmd_cte_receiver_enable_connection_cte_id 0x01450020 -#define sl_bt_cmd_cte_receiver_disable_connection_cte_id 0x02450020 -#define sl_bt_cmd_cte_receiver_enable_connectionless_cte_id 0x03450020 -#define sl_bt_cmd_cte_receiver_disable_connectionless_cte_id 0x04450020 -#define sl_bt_cmd_cte_receiver_enable_silabs_cte_id 0x07450020 -#define sl_bt_cmd_cte_receiver_disable_silabs_cte_id 0x08450020 -#define sl_bt_rsp_cte_receiver_set_dtm_parameters_id 0x05450020 -#define sl_bt_rsp_cte_receiver_clear_dtm_parameters_id 0x06450020 -#define sl_bt_rsp_cte_receiver_set_sync_cte_type_id 0x09450020 -#define sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 -#define sl_bt_rsp_cte_receiver_set_sync_receive_parameters_id 0x0b450020 -#define sl_bt_rsp_cte_receiver_configure_id 0x00450020 -#define sl_bt_rsp_cte_receiver_enable_connection_cte_id 0x01450020 -#define sl_bt_rsp_cte_receiver_disable_connection_cte_id 0x02450020 -#define sl_bt_rsp_cte_receiver_enable_connectionless_cte_id 0x03450020 -#define sl_bt_rsp_cte_receiver_disable_connectionless_cte_id 0x04450020 -#define sl_bt_rsp_cte_receiver_enable_silabs_cte_id 0x07450020 -#define sl_bt_rsp_cte_receiver_disable_silabs_cte_id 0x08450020 - -/** - * @addtogroup sl_bt_cte_receiver_sync_cte_type CTE type flags for limiting periodic advertising synchronization - * @{ - * - * Defines sync CTE type flags that are used to limit what types of periodic - * advertisers to sync to when scanning for periodic advertising synchronization - * or receiving periodic advertising synchronization transfers. - */ - -/** Do not sync to packets with an AoA Constant Tone Extension */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA 0x1 - -/** Do not sync to packets with an AoD Constant Tone Extension with 1 us slots - * */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US 0x2 - -/** Do not sync to packets with an AoD Constant Tone Extension with 2 us slots - * */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US 0x4 - -/** Do not sync to packets without a Constant Tone Extension */ -#define SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY 0x10 - -/** @} */ // end CTE type flags for limiting periodic advertising synchronization - -/** - * @addtogroup sl_bt_evt_cte_receiver_dtm_iq_report sl_bt_evt_cte_receiver_dtm_iq_report - * @{ - * @brief IQ sample report from DTM CTE packets. - */ - -/** @brief Identifier of the dtm_iq_report event */ -#define sl_bt_evt_cte_receiver_dtm_iq_report_id 0x024500a0 - -/***************************************************************************//** - * @brief Data structure of the dtm_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_dtm_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the periodic advertising - train or the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_dtm_iq_report_s sl_bt_evt_cte_receiver_dtm_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_dtm_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_connection_iq_report sl_bt_evt_cte_receiver_connection_iq_report - * @{ - * @brief IQ sample report from connection CTE packets. - */ - -/** @brief Identifier of the connection_iq_report event */ -#define sl_bt_evt_cte_receiver_connection_iq_report_id 0x004500a0 - -/***************************************************************************//** - * @brief Data structure of the connection_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_connection_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint8_t connection; /**< Connection handle or periodic advertising - synchronization handle */ - uint8_t phy; /**< The PHY on which the packet is received. - - 1: 1M PHY - - 2: 2M PHY */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_connection_iq_report_s sl_bt_evt_cte_receiver_connection_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connection_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report sl_bt_evt_cte_receiver_connectionless_iq_report - * @{ - * @brief IQ sample report from connectionless CTE packets. - */ - -/** @brief Identifier of the connectionless_iq_report event */ -#define sl_bt_evt_cte_receiver_connectionless_iq_report_id 0x014500a0 - -/***************************************************************************//** - * @brief Data structure of the connectionless_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_connectionless_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the periodic advertising - train */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_connectionless_iq_report_s sl_bt_evt_cte_receiver_connectionless_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_silabs_iq_report sl_bt_evt_cte_receiver_silabs_iq_report - * @{ - * @brief IQ samples report from Silicon Labs CTE packets. - */ - -/** @brief Identifier of the silabs_iq_report event */ -#define sl_bt_evt_cte_receiver_silabs_iq_report_id 0x034500a0 - -/***************************************************************************//** - * @brief Data structure of the silabs_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_silabs_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - bd_addr address; /**< Bluetooth address of the remote device */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t phy; /**< The PHY on which the packet is received. - - 1: 1M PHY - - 2: 2M PHY */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t packet_counter; /**< The event counter of the periodic advertising - train or the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_silabs_iq_report_s sl_bt_evt_cte_receiver_silabs_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_silabs_iq_report - -/***************************************************************************//** - * - * Set CTE-related parameters of LE receiver test. - * - * @param[in] cte_length @parblock - * Expected CTE length in 8 us units - * - 0: No CTE - * - 0x02 to 0x14: Expected CTE length - * - * Default: 0 (no CTE) - * @endparblock - * @param[in] cte_type @parblock - * Expected CTE type - * - 0: Expect AoA CTE - * - 1: Expect AoD CTE with 1 us slots - * - 2: Expect AoD CTE with 2 us slots - * - * Default: 0 - * @endparblock - * @param[in] slot_durations @parblock - * Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * - * Default: 1 - * @endparblock - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. This can be - * an empty array if CTE is unused. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_dtm_iq_report - Triggered when IQ samples - * have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Clear CTE-related parameters that were previously set for LE receiver test. - * Default values will be restored for these parameters. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_clear_dtm_parameters(); - -/***************************************************************************//** - * - * Set the sync CTE type to limit what types of periodic advertisers to sync to - * when scanning for periodic advertising synchronization. The set parameter - * takes effect immediately for all advertisers that have not already - * established synchronization. - * - * @param[in] sync_cte_type @parblock - * Sync CTE type flags. This value can be a bitmask of multiple flags from - * @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type); - -/***************************************************************************//** - * - * Set the default parameters and the CTE type limitation for receiving Periodic - * Advertising Synchronization Transfers (PAST) over connections. The default - * parameters will be in effect for all subsequent connections and do not affect - * connections that have already opened. The parameters can be overridden for a - * specific connection using command @ref - * sl_bt_cte_receiver_set_sync_receive_parameters after the connection is - * opened. - * - * This command is relevant and available only when the application has included - * the bluetooth_feature_past_receiver component into the build. If the PAST - * receiver component is not included, this command returns the error - * SL_STATUS_NOT_AVAILABLE. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] sync_cte_type @parblock - * Sync CTE type flags to limit what types of periodic advertising trains to - * sync to when receiving sync transfers. This value can be a bitmask of - * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 (do not limit synchronization by CTE type) - * @endparblock - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Set the parameters and the CTE type limitation for receiving Periodic - * Advertising Synchronization Transfers (PAST) over the specified connection. - * The parameters do not affect periodic advertising trains that the device has - * already synchronized to. - * - * This command is relevant and available only when the application has included - * the bluetooth_feature_past_receiver component into the build. If the PAST - * receiver component is not included, this command returns the error - * SL_STATUS_NOT_AVAILABLE. - * - * @param[in] connection Connection handle - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] sync_cte_type @parblock - * Sync CTE type flags to limit what types of periodic advertising trains to - * sync to when receiving sync transfers. This value can be a bitmask of - * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 (do not limit synchronization by CTE type) - * @endparblock - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Configure the CTE sampling mode. - * - * @param[in] flags @parblock - * Values: - * - 0: Disable raw sample mode, only picked IQ samples are reported - * (1 IQ sample pair / slot) - * - 1: Enable raw sample mode, every IQ sample is reported. - * - * Default: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_configure(uint8_t flags); - -/***************************************************************************//** - * - * Start IQ samplings on a connection. A CTE requests will be initiated - * periodically on the given connection and IQ sampling will be made on the - * received CTE responses. - * - * @param[in] connection Connection handle - * @param[in] interval Measurement interval. CTE requests may be sent less - * often. For example, if a connection event is missed for any reason, the CTE - * request will be sent in the next connection event. - * - 0: No interval. The request is initiated only once. - * - Other values N: Initiate the request every N-th connection - * events - * @param[in] cte_length Minimum CTE length requested in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type Requested CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_connection_iq_report - Triggered when IQ - * samples have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, - uint16_t interval, - uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop the IQ sampling on a connection. CTEs will not be requested on the given - * connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection); - -/***************************************************************************//** - * - * Start IQ sampling on a periodic advertising synchronization. IQ samples are - * taken on each CTE found in the periodic advertisements. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] cte_count - 0: Sample and report all available CTEs - * - Other values: Maximum number of sampled CTEs in each periodic - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_connectionless_iq_report - Triggered when IQ - * samples have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, - uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop IQ sampling on a periodic advertising synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync); - -/***************************************************************************//** - * - * Enable IQ sampling of Silicon Labs CTE found in extended advertisements. - * - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] cte_count - 0: Sample and report all available CTEs - * - Other values: Maximum number of sampled CTEs in each extended - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_silabs_iq_report - Triggered when IQ samples - * of Silicon Labs CTE have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable IQ sampling of Silicon Labs CTE. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_silabs_cte(); - -/** @} */ // end addtogroup sl_bt_cte_receiver - -/** - * @addtogroup sl_bt_connection_analyzer Connection Analyzer - * @{ - * - * @brief Connection Analyzer - * - * Analyze Bluetooth packets that are transmitted on the connections of external - * devices. Include component bluetooth_feature_connection_analyzer to use the - * commands and events in this class. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_connection_analyzer_start_id 0x00480020 -#define sl_bt_cmd_connection_analyzer_stop_id 0x01480020 -#define sl_bt_rsp_connection_analyzer_start_id 0x00480020 -#define sl_bt_rsp_connection_analyzer_stop_id 0x01480020 - -/** - * @addtogroup sl_bt_connection_analyzer_flags Connection Analyzer Configuration flags - * @{ - * - * Defines the configuration flags in connection analyzer. - */ - -/** Indicates a given time value, e.g., @p start_time_us in @ref - * sl_bt_connection_analyzer_start, is a value relative to the current time. */ -#define SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME 0x1 - -/** @} */ // end Connection Analyzer Configuration flags - -/** - * @addtogroup sl_bt_evt_connection_analyzer_report sl_bt_evt_connection_analyzer_report - * @{ - * @brief Triggered when packets transmitted on a connection are captured. - */ - -/** @brief Identifier of the report event */ -#define sl_bt_evt_connection_analyzer_report_id 0x004800a0 - -/***************************************************************************//** - * @brief Data structure of the report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_analyzer_report_s -{ - uint8_t analyzer; /**< The handle of the connection analyzer */ - int8_t central_rssi; /**< RSSI measurement of the packet transmitted by - the Central device. Units: dBm. Range: -127 to - +20. */ - int8_t peripheral_rssi; /**< RSSI measurement of the packet transmitted by - the Peripheral device. Units: dBm. Range: -127 - to +20. */ -}); - -typedef struct sl_bt_evt_connection_analyzer_report_s sl_bt_evt_connection_analyzer_report_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_report - -/** - * @addtogroup sl_bt_evt_connection_analyzer_completed sl_bt_evt_connection_analyzer_completed - * @{ - * @brief Triggered when the operation of analyzing a connection is completed. - */ - -/** @brief Identifier of the completed event */ -#define sl_bt_evt_connection_analyzer_completed_id 0x014800a0 - -/***************************************************************************//** - * @brief Data structure of the completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_analyzer_completed_s -{ - uint8_t analyzer; /**< The handle of the connection analyzer */ - uint16_t reason; /**< The reason of stopping the operation */ -}); - -typedef struct sl_bt_evt_connection_analyzer_completed_s sl_bt_evt_connection_analyzer_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_completed - -/***************************************************************************//** - * - * Start to analyze another device's connection and report the RSSI - * measurements. The parameters in this command provide necessary information to - * identify the connection and schedule operations to follow its transmissions. - * - * If the other device uses Silabs' Bluetooth stack, the information of the - * connection could be retrieved with command @ref - * sl_bt_connection_get_scheduling_details. The method of passing the - * information to this device is application layer logic. - * - * @param[in] access_address Access address of the connection - * @param[in] crc_init The CRC initialization value - * @param[in] interval The connection interval. Time = Value x 1.25 ms - * @param[in] supervision_timeout The connection supervision time. Time = Value - * x 10 ms - * @param[in] central_clock_accuracy The central device's clock accuracy index - * value - * @param[in] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central - * device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[in] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the - * Peripheral device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[in] channel_selection_algorithm Enum @ref - * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. - * Values: - * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection - * algorithm #1 - * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection - * algorithm #2 - * @param[in] hop The hop increment when the channel selection algorithm #1 is - * used on the connection. Ignored if @p channel_selection_algorithm indicates - * that the connection uses channel selection algorithm #2. - * @param[in] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Ignore bits 37-39 that are reserved for future use. - * - * A channel is unused when its bit is 0. A channel is used when its bit is 1. - * @endparblock - * @param[in] channel The data channel number that transmissions will use in the - * next connection event - * @param[in] event_counter The event counter of the next connection event - * @param[in] start_time_us The start time of the given connection event in - * microseconds. The semantics depend on whether the configuration flag - * SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME is set in parameter @p flags: - * - When the flag is set, the value is a time relative to the current time. - * A negative value means that the start time was in the past. - * - When the flag is not set, the value is an absolute time converted from - * the PROTIMER tick. - * @param[in] flags Configuration flags. This value is a bitmask of @ref - * sl_bt_connection_analyzer_flags. - * @param[out] analyzer A handle that is assigned to the connection analyzer. - * This handle is valid only if the result code of this command is - * SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_analyzer_report - Triggered when a packet - * transmitted from the given device is captured. - * - @ref sl_bt_evt_connection_analyzer_completed - Triggered when analyzing a - * connection is completed in the Link Layer for some reason. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, - uint32_t crc_init, - uint16_t interval, - uint16_t supervision_timeout, - uint8_t central_clock_accuracy, - uint8_t central_phy, - uint8_t peripheral_phy, - uint8_t channel_selection_algorithm, - uint8_t hop, - const sl_bt_connection_channel_map_t *channel_map, - uint8_t channel, - uint16_t event_counter, - int32_t start_time_us, - uint32_t flags, - uint8_t *analyzer); - -/***************************************************************************//** - * - * Stop analyzing another device's Bluetooth connection. The operation is - * stopped when this command returns, and the stack does not send additional - * event. - * - * @param[in] analyzer The handle of the connection analyzer to stop - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer); - -/** @} */ // end addtogroup sl_bt_connection_analyzer - -/** - * @addtogroup sl_bt_user User Messaging - * @{ - * - * @brief User Messaging - * - * This class provides commands and events, which can be used by a NCP host and - * target to implement a communication mechanism with a custom proprietary - * protocol. An application must decide whether and how the command and event - * are used. The stack does not produce or consume any messages belonging to - * this class. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_user_message_to_target_id 0x00ff0020 -#define sl_bt_cmd_user_manage_event_filter_id 0x01ff0020 -#define sl_bt_cmd_user_reset_to_dfu_id 0x02ff0020 -#define sl_bt_rsp_user_message_to_target_id 0x00ff0020 -#define sl_bt_rsp_user_manage_event_filter_id 0x01ff0020 -#define sl_bt_rsp_user_reset_to_dfu_id 0x02ff0020 - -/** - * @addtogroup sl_bt_evt_user_message_to_host sl_bt_evt_user_message_to_host - * @{ - * @brief Used by the target application on a device to initiate communication - * and send a message to the NCP host - * - * Do not send event messages in the context of the user command handling. - */ - -/** @brief Identifier of the message_to_host event */ -#define sl_bt_evt_user_message_to_host_id 0x00ff00a0 - -/***************************************************************************//** - * @brief Data structure of the message_to_host event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_user_message_to_host_s -{ - uint8array message; /**< The message */ -}); - -typedef struct sl_bt_evt_user_message_to_host_s sl_bt_evt_user_message_to_host_t; - -/** @} */ // end addtogroup sl_bt_evt_user_message_to_host - -/***************************************************************************//** - * - * Used by an NCP host to send a message to the target application on device. - * The application on the target must send the response with @ref - * sl_bt_send_rsp_user_message_to_target. - * - * @param[in] data_len Length of data in @p data - * @param[in] data The message - * @param[in] max_response_size Size of output buffer passed in @p response - * @param[out] response_len On return, set to the length of output data written - * to @p response - * @param[out] response The response message - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_user_message_to_target(size_t data_len, - const uint8_t* data, - size_t max_response_size, - size_t *response_len, - uint8_t *response); - -/***************************************************************************//** - * - * Manage NCP event filter. When the event filter is in use, API events passing - * the filter will be sent to the host and those that do not pass are discarded - * by the target. For functionality details, see the NCP component in the - * Bluetooth SDK. - * - * By default, the NCP does not use the event filter. - * - * @param[in] data_len Length of data in @p data - * @param[in] data The message for managing event filter - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_user_manage_event_filter(size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Reset the target device to DFU mode from the NCP host. This command is used - * by specific SDK DFU component on the target device for the functionality - * related to DFU. Do not use it in other circumstances. This command does not - * have a response. - * - * - ******************************************************************************/ -void sl_bt_user_reset_to_dfu(); - -/** @} */ // end addtogroup sl_bt_user - - -/***************************************************************************//** - * @addtogroup sl_bt_common_types BT Common Types - * @{ - * @brief BT common types - */ - -/** - * @brief Data structure of BT API messages - */ -PACKSTRUCT( struct sl_bt_msg { - /** API protocol header consisting of event identifier and data length */ - uint32_t header; - - /** Union of API event types */ - union { - uint8_t handle; - sl_bt_evt_dfu_boot_t evt_dfu_boot; /**< Data field for dfu boot event*/ - sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; /**< Data field for dfu boot_failure event*/ - sl_bt_evt_system_boot_t evt_system_boot; /**< Data field for system boot event*/ - sl_bt_evt_system_error_t evt_system_error; /**< Data field for system error event*/ - sl_bt_evt_system_hardware_error_t evt_system_hardware_error; /**< Data field for system hardware_error event*/ - sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; /**< Data field for system resource_exhausted event*/ - sl_bt_evt_system_external_signal_t evt_system_external_signal; /**< Data field for system external_signal event*/ - sl_bt_evt_system_soft_timer_t evt_system_soft_timer; /**< Data field for system soft_timer event*/ - sl_bt_evt_resource_status_t evt_resource_status; /**< Data field for resource status event*/ - sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; /**< Data field for advertiser timeout event*/ - sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; /**< Data field for advertiser scan_request event*/ - sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; /**< Data field for periodic_advertiser status event*/ - sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; /**< Data field for scanner legacy_advertisement_report event*/ - sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; /**< Data field for scanner extended_advertisement_report event*/ - sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; /**< Data field for scanner scan_report event*/ - sl_bt_evt_sync_opened_t evt_sync_opened; /**< Data field for sync opened event*/ - sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; /**< Data field for sync transfer_received event*/ - sl_bt_evt_sync_data_t evt_sync_data; /**< Data field for sync data event*/ - sl_bt_evt_sync_closed_t evt_sync_closed; /**< Data field for sync closed event*/ - sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; /**< Data field for periodic_sync opened event*/ - sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; /**< Data field for periodic_sync transfer_received event*/ - sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; /**< Data field for periodic_sync report event*/ - sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; /**< Data field for pawr_sync opened event*/ - sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; /**< Data field for pawr_sync transfer_received event*/ - sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; /**< Data field for pawr_sync subevent_report event*/ - sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; /**< Data field for pawr_advertiser subevent_data_request event*/ - sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; /**< Data field for pawr_advertiser subevent_tx_failed event*/ - sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; /**< Data field for pawr_advertiser response_report event*/ - sl_bt_evt_connection_opened_t evt_connection_opened; /**< Data field for connection opened event*/ - sl_bt_evt_connection_parameters_t evt_connection_parameters; /**< Data field for connection parameters event*/ - sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; /**< Data field for connection set_parameters_failed event*/ - sl_bt_evt_connection_phy_status_t evt_connection_phy_status; /**< Data field for connection phy_status event*/ - sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; /**< Data field for connection get_remote_tx_power_completed event*/ - sl_bt_evt_connection_tx_power_t evt_connection_tx_power; /**< Data field for connection tx_power event*/ - sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; /**< Data field for connection remote_tx_power event*/ - sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; /**< Data field for connection remote_used_features event*/ - sl_bt_evt_connection_data_length_t evt_connection_data_length; /**< Data field for connection data_length event*/ - sl_bt_evt_connection_statistics_t evt_connection_statistics; /**< Data field for connection statistics event*/ - sl_bt_evt_connection_closed_t evt_connection_closed; /**< Data field for connection closed event*/ - sl_bt_evt_connection_rssi_t evt_connection_rssi; /**< Data field for connection rssi event*/ - sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; /**< Data field for gatt mtu_exchanged event*/ - sl_bt_evt_gatt_service_t evt_gatt_service; /**< Data field for gatt service event*/ - sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; /**< Data field for gatt characteristic event*/ - sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; /**< Data field for gatt descriptor event*/ - sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; /**< Data field for gatt characteristic_value event*/ - sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; /**< Data field for gatt descriptor_value event*/ - sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; /**< Data field for gatt procedure_completed event*/ - sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; /**< Data field for gatt_server attribute_value event*/ - sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; /**< Data field for gatt_server user_read_request event*/ - sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; /**< Data field for gatt_server user_write_request event*/ - sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; /**< Data field for gatt_server characteristic_status event*/ - sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; /**< Data field for gatt_server execute_write_completed event*/ - sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; /**< Data field for gatt_server indication_timeout event*/ - sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; /**< Data field for gatt_server notification_tx_completed event*/ - sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; /**< Data field for test dtm_completed event*/ - sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; /**< Data field for sm passkey_display event*/ - sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; /**< Data field for sm passkey_request event*/ - sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; /**< Data field for sm confirm_passkey event*/ - sl_bt_evt_sm_bonded_t evt_sm_bonded; /**< Data field for sm bonded event*/ - sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; /**< Data field for sm bonding_failed event*/ - sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; /**< Data field for sm confirm_bonding event*/ - sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; /**< Data field for external_bondingdb data_request event*/ - sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; /**< Data field for external_bondingdb data event*/ - sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; /**< Data field for external_bondingdb data_ready event*/ - sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; /**< Data field for cs security_enable_complete event*/ - sl_bt_evt_cs_config_complete_t evt_cs_config_complete; /**< Data field for cs config_complete event*/ - sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; /**< Data field for cs procedure_enable_complete event*/ - sl_bt_evt_cs_result_t evt_cs_result; /**< Data field for cs result event*/ - sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; /**< Data field for l2cap le_channel_open_request event*/ - sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; /**< Data field for l2cap le_channel_open_response event*/ - sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; /**< Data field for l2cap channel_data event*/ - sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; /**< Data field for l2cap channel_credit event*/ - sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; /**< Data field for l2cap channel_closed event*/ - sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; /**< Data field for l2cap command_rejected event*/ - sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; /**< Data field for cte_receiver dtm_iq_report event*/ - sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; /**< Data field for cte_receiver connection_iq_report event*/ - sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; /**< Data field for cte_receiver connectionless_iq_report event*/ - sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; /**< Data field for cte_receiver silabs_iq_report event*/ - sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; /**< Data field for connection_analyzer report event*/ - sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; /**< Data field for connection_analyzer completed event*/ - sl_bt_evt_user_message_to_host_t evt_user_message_to_host; /**< Data field for user message_to_host event*/ - uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; - } data; -}); - -/** - * @brief Type definition for the data structure of BT API messages - */ -typedef struct sl_bt_msg sl_bt_msg_t; - -/** @} */ // end addtogroup sl_bt_common_types -/******************************************************************************/ - -/***************************************************************************//** - * @addtogroup sl_bt_utility_functions Utility Functions - * @brief Utility functions for applications on SoC - * @{ - */ - -/** - * Get the next event that requires processing by user application. Application - * is not blocked if no event is waiting. - * - * @param event the pointer for storing the new event - * @return SL_STATUS_OK if a new event is returned, or SL_STATUS_NOT_FOUND if no - * event is waiting; other value indicates an error occurred - */ -sl_status_t sl_bt_pop_event(sl_bt_msg_t* event); - -/** - * Check whether events are in queue pending for processing. - * Call @ref sl_bt_pop_event to process pending events. - * - * @return true if event is pending; false otherwise - */ -bool sl_bt_event_pending(void); - -/** - * Check whether events are in queue pending for processing and return the next - * event length in bytes if events are pending. - * Call @ref sl_bt_pop_event to process pending events. - * - * @return the next event length if event is pending; 0 otherwise - */ -uint32_t sl_bt_event_pending_len(void); - - -/** - * Run the Bluetooth stack to process scheduled tasks. Events for user - * application may be generated as a result of this operation. - */ -void sl_bt_run(); - -/** - * Handle an API command in binary format. - * - * This is provided to NCP target applications for processing commands received - * from NCP transport. This function is a synonym for a generic BGAPI function - * @ref sl_bgapi_handle_command. If the NCP application uses an RTOS, use the - * sequence documented in @ref sl_bgapi_handle_command to handle the BGAPI - * command in a thread-safe manner. - * - * @param hdr the command header - * @param data the command payload in a byte array - */ -void sl_bt_handle_command(uint32_t hdr, void* data); - -/** - * Get the response to the command currently been handled. - * - * This is provided to NCP target applications for processing commands received - * from NCP transport. This function is a synonym for a generic BGAPI function - * @ref sl_bgapi_get_command_response. - */ -static inline sl_bt_msg_t* sl_bt_get_command_response() -{ - return (sl_bt_msg_t*) sl_bgapi_get_command_response(); -} - -/** - * Priority message handler function if user application requires the use of - * PendSV interrupt. - * - * If scheduler_callback function pointer in configuration struct is something - * else than NULL, then stack will not install its own PendSV IRQ handler but - * instead uses callback/handler functions. - * - * When application receives call to the scheduler_callback function it must - * schedule the call to gecko_priority_handle function to later time to run on - * high priority thread. This callback may happen inside radio IRQ so processing - * must not block and has to happen as fast as possible. - * - * Recommended implementation: High priority thread is loop that waits on binary - * semaphore and calls gecko_priority_handler. The scheduler_callback is simple - * function that only signals the semaphore. - * - */ -void sl_bt_priority_handle(void); - -/** - * @brief Signal the Bluetooth stack that an external event has happened. - * - * Signals can be used to report status changes from interrupt context or from - * other threads to application. Signals are bits that are automatically cleared - * after application has been notified. - * - * If the Platform Core Interrupt API has been configured to use the - * CORE_ATOMIC_METHOD_BASEPRI as the implementation method of atomic sections, - * this function must not be called from an interrupt handler with a priority - * higher than CORE_ATOMIC_BASE_PRIORITY_LEVEL. - * - * @param signals is a bitmask defining active signals that are reported back to - * the application by system_external_signal-event. - * @return SL_STATUS_OK if the operation is successful, - * SL_STATUS_NO_MORE_RESOURCE indicating the request could not be processed - * due to resource limitation at the moment, or SL_STATUS_INVALID_STATE when - * the on-demand start feature is used and the stack is currently stopped. - */ -sl_status_t sl_bt_external_signal(uint32_t signals); - -/** - * Signals stack to send system_awake event when application received wakeup - * signal. - */ -void sl_bt_send_system_awake(); - -/** - * Signals stack to send system_error event when in case of an error. - */ -void sl_bt_send_system_error(uint16_t reason, uint8_t data_len, const uint8_t *data); - -/** - * Tells if a SL_BT_API message is sensitive. - * - * @param[in] message_header The header of the SL_BT_API message - * @return 1 if the message is sensitive; otherwise 0 - */ -uint8_t sl_bt_is_sensitive_message(uint32_t message_header); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_rsp_user_message_to_target_id. - * - * This a utility helping a NCP host and target application to exchange user - * data. Do not use it in SoC mode. - */ -void sl_bt_send_rsp_user_message_to_target(uint16_t result, uint8_t data_len, uint8_t *data); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_evt_user_message_to_host_id. - * - * This a utility helping a NCP host and target application to exchange user - * data. Do not use it in SoC mode. - */ -void sl_bt_send_evt_user_message_to_host(uint8_t data_len, uint8_t *data); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_rsp_user_manage_event_filter_id. - * - * This a utility helping a NCP host and target application to manage event - * filter. Do not use it in SoC mode. - */ -void sl_bt_send_rsp_user_manage_event_filter(uint16_t result); - - -/** @} */ // end addtogroup sl_bt_utility_functions -/******************************************************************************/ - -#ifdef __cplusplus -} -#endif - +/***************************************************************************//** + * @brief SL_BT_API command declarations + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + + +#ifndef SL_BT_API_H +#define SL_BT_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include "sl_status.h" +#include "sl_bgapi.h" +#include "sl_bt_api_compatibility.h" + + +/* SL_BT_ synonyms for BGAPI header macros */ +#define SL_BT_MSG_ID(HDR) SL_BGAPI_MSG_ID(HDR) +#define SL_BT_MSG_HEADER_LEN SL_BGAPI_MSG_HEADER_LEN +#define SL_BT_MSG_LEN(HDR) SL_BGAPI_MSG_LEN(HDR) +#define SL_BT_BIT_ENCRYPTED SL_BGAPI_BIT_ENCRYPTED +#define SL_BT_MSG_ENCRYPTED(HDR) SL_BGAPI_MSG_ENCRYPTED(HDR) + +/** + * @addtogroup sl_bt_common_types BT Common Types + * @{ + * + * @brief BT common types + */ + +/** + * @brief Value used to indicate an invalid connection handle + */ +#define SL_BT_INVALID_CONNECTION_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid bonding handle + */ +#define SL_BT_INVALID_BONDING_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid advertising set handle + */ +#define SL_BT_INVALID_ADVERTISING_SET_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid sync handle + */ +#define SL_BT_INVALID_SYNC_HANDLE ((uint16_t) 0xFFFF) + +/** + * @brief Value used to indicate an invalid connection analyzer handle + */ +#define SL_BT_INVALID_CONNECTION_ANALYZER_HANDLE ((uint8_t) 0xFF) + +/** @} */ // end addtogroup sl_bt_common_types + + +/** + * @brief ABR subevent length + */ +typedef struct { + uint8_t data[3]; /**< ABR subevent length */ +} sl_bt_cs_subevent_length_t; + +/** + * @brief DRBG key + */ +typedef struct { + uint8_t data[16]; /**< DRBG key */ +} sl_bt_drbg_key_t; + +/** + * @brief 79 1-bit fields containing the values of the ABR channel index + */ +typedef struct { + uint8_t data[10]; /**< 79 1-bit fields containing the values of the ABR channel index */ +} sl_bt_cs_channel_map_t; + +/** + * @brief 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection + */ +typedef struct { + uint8_t data[5]; /**< 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection */ +} sl_bt_connection_channel_map_t; + + + +/** + * @addtogroup sl_bt_dfu Device Firmware Update + * @{ + * + * @brief Device Firmware Update + * + * These commands and events are related to controlling firmware updates over + * the configured host interface and are available only when the device is + * booted in DFU mode. DFU process: + * 1. Boot device to DFU mode with the Bootloader interface + * 2. Wait for @ref sl_bt_evt_dfu_boot event + * 3. Send command @ref sl_bt_dfu_flash_set_address command to start the + * firmware update + * 4. Upload the firmware with @ref sl_bt_dfu_flash_upload commands until all + * data is uploaded + * 5. Send @ref sl_bt_dfu_flash_upload_finish command when all data is + * uploaded + * 6. Finalize DFU firmware update with @ref sl_bt_system_reset command + * + * DFU mode is using the UART baudrate set in bootloader. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_dfu_flash_set_address_id 0x01000020 +#define sl_bt_cmd_dfu_flash_upload_id 0x02000020 +#define sl_bt_cmd_dfu_flash_upload_finish_id 0x03000020 +#define sl_bt_rsp_dfu_flash_set_address_id 0x01000020 +#define sl_bt_rsp_dfu_flash_upload_id 0x02000020 +#define sl_bt_rsp_dfu_flash_upload_finish_id 0x03000020 + +/** + * @addtogroup sl_bt_evt_dfu_boot sl_bt_evt_dfu_boot + * @{ + * @brief This event indicates that the device booted in DFU mode and is now + * ready to receive commands related to device firmware upgrade (DFU). + */ + +/** @brief Identifier of the boot event */ +#define sl_bt_evt_dfu_boot_id 0x000000a0 + +/***************************************************************************//** + * @brief Data structure of the boot event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_dfu_boot_s +{ + uint32_t version; /**< The version of the bootloader */ +}); + +typedef struct sl_bt_evt_dfu_boot_s sl_bt_evt_dfu_boot_t; + +/** @} */ // end addtogroup sl_bt_evt_dfu_boot + +/** + * @addtogroup sl_bt_evt_dfu_boot_failure sl_bt_evt_dfu_boot_failure + * @{ + * @brief This event indicates that an error, which prevents the device from + * booting, has occurred in bootloader. + */ + +/** @brief Identifier of the boot_failure event */ +#define sl_bt_evt_dfu_boot_failure_id 0x010000a0 + +/***************************************************************************//** + * @brief Data structure of the boot_failure event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_dfu_boot_failure_s +{ + uint16_t reason; /**< The reason for boot failure. */ +}); + +typedef struct sl_bt_evt_dfu_boot_failure_s sl_bt_evt_dfu_boot_failure_t; + +/** @} */ // end addtogroup sl_bt_evt_dfu_boot_failure + +/***************************************************************************//** + * + * After re-booting the local device in DFU mode, this command defines the + * starting address on the flash where the new firmware will be written. + * + * @param[in] address The offset in the flash where the new firmware is uploaded + * to. Always use the value 0x00000000. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_set_address(uint32_t address); + +/***************************************************************************//** + * + * Upload the whole firmware image file into the Bluetooth device. The passed + * data length must be a multiple of 4 bytes. Because the BGAPI command payload + * size is limited, multiple commands need to be issued one after the other + * until the whole firmware image file is uploaded to the device. After each + * command, the next address of the flash sector in memory to write to is + * automatically updated by the bootloader. + * + * @param[in] data_len Length of data in @p data + * @param[in] data An array of data which will be written onto the flash. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data); + +/***************************************************************************//** + * + * Inform the device that the DFU file is fully uploaded. To return the device + * back to normal mode, issue the command @ref sl_bt_system_reset. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_upload_finish(); + +/** @} */ // end addtogroup sl_bt_dfu + +/** + * @addtogroup sl_bt_system System + * @{ + * + * @brief System + * + * Commands and events in this class can be used to access and query the local + * device. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_system_hello_id 0x00010020 +#define sl_bt_cmd_system_start_bluetooth_id 0x1c010020 +#define sl_bt_cmd_system_stop_bluetooth_id 0x1d010020 +#define sl_bt_cmd_system_forcefully_stop_bluetooth_id 0x1e010020 +#define sl_bt_cmd_system_get_version_id 0x1b010020 +#define sl_bt_cmd_system_reset_id 0x01010020 +#define sl_bt_cmd_system_halt_id 0x0c010020 +#define sl_bt_cmd_system_linklayer_configure_id 0x0e010020 +#define sl_bt_cmd_system_set_tx_power_id 0x17010020 +#define sl_bt_cmd_system_get_tx_power_setting_id 0x18010020 +#define sl_bt_cmd_system_set_identity_address_id 0x13010020 +#define sl_bt_cmd_system_get_identity_address_id 0x15010020 +#define sl_bt_cmd_system_get_random_data_id 0x0b010020 +#define sl_bt_cmd_system_data_buffer_write_id 0x12010020 +#define sl_bt_cmd_system_data_buffer_clear_id 0x14010020 +#define sl_bt_cmd_system_get_counters_id 0x0f010020 +#define sl_bt_cmd_system_set_lazy_soft_timer_id 0x1a010020 +#define sl_bt_rsp_system_hello_id 0x00010020 +#define sl_bt_rsp_system_start_bluetooth_id 0x1c010020 +#define sl_bt_rsp_system_stop_bluetooth_id 0x1d010020 +#define sl_bt_rsp_system_forcefully_stop_bluetooth_id 0x1e010020 +#define sl_bt_rsp_system_get_version_id 0x1b010020 +#define sl_bt_rsp_system_reset_id 0x01010020 +#define sl_bt_rsp_system_halt_id 0x0c010020 +#define sl_bt_rsp_system_linklayer_configure_id 0x0e010020 +#define sl_bt_rsp_system_set_tx_power_id 0x17010020 +#define sl_bt_rsp_system_get_tx_power_setting_id 0x18010020 +#define sl_bt_rsp_system_set_identity_address_id 0x13010020 +#define sl_bt_rsp_system_get_identity_address_id 0x15010020 +#define sl_bt_rsp_system_get_random_data_id 0x0b010020 +#define sl_bt_rsp_system_data_buffer_write_id 0x12010020 +#define sl_bt_rsp_system_data_buffer_clear_id 0x14010020 +#define sl_bt_rsp_system_get_counters_id 0x0f010020 +#define sl_bt_rsp_system_set_lazy_soft_timer_id 0x1a010020 + +/** + * @brief Specifies the mode that the system will boot into. + */ +typedef enum +{ + sl_bt_system_boot_mode_normal = 0x0, /**< (0x0) Boot to normal mode */ + sl_bt_system_boot_mode_uart_dfu = 0x1, /**< (0x1) Boot to UART DFU mode */ + sl_bt_system_boot_mode_ota_dfu = 0x2 /**< (0x2) Boot to OTA DFU mode */ +} sl_bt_system_boot_mode_t; + +/** + * @brief These Keys are used to configure Link Layer Operation + */ +typedef enum +{ + sl_bt_system_linklayer_config_key_halt = 0x1, /**< + (0x1) + Same + as + system_halt + command, + value-0 + Stop + Radio + 1- + Start + Radio */ + sl_bt_system_linklayer_config_key_priority_range = 0x2, /**< + (0x2) + Sets + the + RAIL + priority_mapping + offset + field + of + the + link + layer + priority + configuration + structure + to + the + first + byte + of + the + value + field. */ + sl_bt_system_linklayer_config_key_scan_channels = 0x3, /**< + (0x3) + Sets + channels + to + scan + on. + The + first + byte + of + the + value + is + the + channel + map. + 0x1 + = + Channel + 37, + 0x2 + = + Channel + 38, + 0x4 + = + Channel + 39 */ + sl_bt_system_linklayer_config_key_set_flags = 0x4, /**< + (0x4) + Sets + the + link + layer + configuration + flags. + The + value + is + a + little + endian + 32-bit + integer. + Flag + Values: + - 0x00000001 + \- + Disable + Feature + Exchange + in + peripheral + role + of + the + connection + - 0x00000002 + \- + Disable + Feature + Exchange + in + central + role + of + the + connection */ + sl_bt_system_linklayer_config_key_clr_flags = 0x5, /**< + (0x5) + The + value + is + flags + to + clear. + Flags + are + the + same + as + in + SET_FLAGS + command. */ + sl_bt_system_linklayer_config_key_set_afh_interval = 0x7, /**< + (0x7) + Set + the + afh_scan_interval. + Value + is + in + units + of + 10 + ms. + Setting + the + interval + to + 0 + will + result + in + using + the + default + value + of + 1 + second. */ + sl_bt_system_linklayer_config_key_set_priority_table = 0x9, /**< + (0x9) + The + value + contains + a + priority + table + to + be + copied + over + the + existing + table. + If + the + value + is + smaller + than + the + full + table, + only + those + values + are + updated. + See + sl_bt_bluetooth_ll_priorities + struct + for + the + definition + of + a + priority + table. */ + sl_bt_system_linklayer_config_key_set_rx_packet_filtering = 0xa, /**< + (0xa) + Configure + and + enable + or + disable + RX + packet + filtering + feature. + Value: + >= + 5 + bytes. + - Byte + 1 + \- + The + filter + count + - Byte + 2 + \- + The + filter + offset + - Byte + 3 + \- + The + length + of + the + filter + list + - Byte + 4 + \- + The + bitmask + flags + - Rest + of + the + data + \- + The + filter + list */ + sl_bt_system_linklayer_config_key_set_simultaneous_scanning = 0xb, /**< + (0xb) + Enable + or + disable + simultaneous + scanning + on + the + 1M + and + Coded + PHYs. + Value: + 1 + byte. + - 0 + \- + Disable + simultaneous + scanning. + - 1 + \- + Enable + simultaneous + scanning. */ + sl_bt_system_linklayer_config_key_set_channelmap_flags = 0xc, /**< + (0xc) + Configure + channelmap + adaptivity + flags. + Value: + 4 + bytes. */ + sl_bt_system_linklayer_config_key_power_control_golden_range = 0x10, /**< + (0x10) + Set + Power + Control + golden + range + parameters. + The + value + is + a + 8-bytes + long + array + that + consists + of + 4 + pairs + of + golden + range + configurations. + In + each + pair, + the + first + byte + is + the + lower + RSSI + boundary + and + the + second + byte + is + the + upper + RSSI + boundary. + RSSI + values + are + in + dBm. + This + configuration + is + not + allowed + if + there + are + active + Bluetooth + connections. + - Byte + 1 + \- + Minimal + RSSI + on + 1M + PHY + - Byte + 2 + \- + Maximal + RSSI + on + 1M + PHY + - Byte + 3 + \- + Minimal + RSSI + on + 2M + PHY + - Byte + 4 + \- + Maximal + RSSI + on + 2M + PHY + - Byte + 5 + \- + Minimal + RSSI + on + Coded + PHY + S=8 + - Byte + 6 + \- + Maximal + RSSI + on + Coded + PHY + S=8 + - Byte + 7 + \- + Minimal + RSSI + on + Coded + PHY + S=2 + - Byte + 8 + \- + Maximal + RSSI + on + Coded + PHY + S=2 */ + sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit = 0x11, /**< + (0x11) + Value: + uint16_t + Adjust + upper + limit + for + backoff + counter. + If + 0 + restores + default + value + of + 256 + Value + must + be + between + 16 + \- + 256 */ + sl_bt_system_linklayer_config_key_afh_rssi_threshold = 0x12, /**< + (0x12) + Value: + int8_t + Configures + RSSI + limit + for + AFH + channel + blocking */ + sl_bt_system_linklayer_config_key_afh_channel_cooldown = 0x13, /**< + (0x13) + Value: + int16_t + Configures + how + long + channel + is + blocked + after + activity + is + detected + Default: + 8000 */ + sl_bt_system_linklayer_config_key_set_report_all_scan_rsps = 0x14 /**< + (0x14) + Value: + uint8_t + 0 + \- + default, + only + reports + scan + responses + that + is + received + after + sending + scan_req + nonzero + \- + Will + report + all + scan + responses + that + are + received + on + primary + advertising + channels */ +} sl_bt_system_linklayer_config_key_t; + +/** + * @addtogroup sl_bt_evt_system_boot sl_bt_evt_system_boot + * @{ + * @brief Indicates that the device has started and the radio is ready + * + * This event carries the firmware build number and other software and hardware + * identification codes. + */ + +/** @brief Identifier of the boot event */ +#define sl_bt_evt_system_boot_id 0x000100a0 + +/***************************************************************************//** + * @brief Data structure of the boot event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_boot_s +{ + uint16_t major; /**< Major release version */ + uint16_t minor; /**< Minor release version */ + uint16_t patch; /**< Patch release number */ + uint16_t build; /**< Build number */ + uint32_t bootloader; /**< Unused. Ignore this field. */ + uint16_t hw; /**< Hardware type: the major chip revision number in the + most significant byte and the minor revision in the + least significant byte */ + uint32_t hash; /**< Version hash */ +}); + +typedef struct sl_bt_evt_system_boot_s sl_bt_evt_system_boot_t; + +/** @} */ // end addtogroup sl_bt_evt_system_boot + +/** + * @addtogroup sl_bt_evt_system_stopped sl_bt_evt_system_stopped + * @{ + * @brief When the Bluetooth on-demand start component is included in the + * application build, this event is triggered when stopping the Bluetooth stack + * using commands @ref sl_bt_system_stop_bluetooth or @ref + * sl_bt_system_forcefully_stop_bluetooth has completed. + */ + +/** @brief Identifier of the stopped event */ +#define sl_bt_evt_system_stopped_id 0x010100a0 + +/** @} */ // end addtogroup sl_bt_evt_system_stopped + +/** + * @addtogroup sl_bt_evt_system_error sl_bt_evt_system_error + * @{ + * @brief Indicates that an error has occurred + * + * See error codes table for more information. + */ + +/** @brief Identifier of the error event */ +#define sl_bt_evt_system_error_id 0x060100a0 + +/***************************************************************************//** + * @brief Data structure of the error event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_error_s +{ + uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ + uint8array data; /**< Data related to the error; this field can be empty. */ +}); + +typedef struct sl_bt_evt_system_error_s sl_bt_evt_system_error_t; + +/** @} */ // end addtogroup sl_bt_evt_system_error + +/** + * @addtogroup sl_bt_evt_system_hardware_error sl_bt_evt_system_hardware_error + * @{ + * @brief Indicates that a hardware-related error has occurred. + */ + +/** @brief Identifier of the hardware_error event */ +#define sl_bt_evt_system_hardware_error_id 0x050100a0 + +/***************************************************************************//** + * @brief Data structure of the hardware_error event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_hardware_error_s +{ + uint16_t status; /**< SL_STATUS_OK if successful. Error code otherwise. */ +}); + +typedef struct sl_bt_evt_system_hardware_error_s sl_bt_evt_system_hardware_error_t; + +/** @} */ // end addtogroup sl_bt_evt_system_hardware_error + +/** + * @addtogroup sl_bt_evt_system_resource_exhausted sl_bt_evt_system_resource_exhausted + * @{ + * @brief Indicates that a system resource has been exhausted during the + * operation of the Bluetooth stack + * + * If resource errors occur already when the Bluetooth stack is starting, the + * error is reported directly as a return value from sl_bt_stack_init (when the + * Bluetooth on-demand start component is not included in the application + * build), or from @ref sl_bt_system_start_bluetooth (when the on-demand start + * component is included). The fields of this event indicate how many failures + * have occurred for a specific resource. If further resource failures occur + * while this event is already queued in the BGAPI event queue but not yet + * delivered to the application, the new failures are included in the already + * queued event. When the application receives this event, the fields represent + * the number of failures that have occurred since the previous @ref + * sl_bt_evt_system_resource_exhausted event. + */ + +/** @brief Identifier of the resource_exhausted event */ +#define sl_bt_evt_system_resource_exhausted_id 0x080100a0 + +/***************************************************************************//** + * @brief Data structure of the resource_exhausted event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_resource_exhausted_s +{ + uint8_t num_buffers_discarded; /**< The system has temporarily run + out of the pre-allocated data + buffers that are allocated based + on SL_BT_CONFIG_BUFFER_SIZE + configuration and some expendable + data or event had to be discarded + to satisfy a non-expendble buffer + allocation. A typical case is + discarding scan reports when a + large inflow of scan reports + exceeds the speed at which the + application drains the BGAPI + event queue. */ + uint8_t num_buffer_allocation_failures; /**< The system has run out of the + pre-allocated data buffers that + are allocated based on + SL_BT_CONFIG_BUFFER_SIZE + configuration and a buffer + allocation has failed. */ + uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed to + make an allocation from the heap. + Note that only allocations made + by the Bluetooth stack are + detected and reported by this + field. Allocation failures in + other components that use + sl_malloc() or malloc() are not + included in this count. */ +}); + +typedef struct sl_bt_evt_system_resource_exhausted_s sl_bt_evt_system_resource_exhausted_t; + +/** @} */ // end addtogroup sl_bt_evt_system_resource_exhausted + +/** + * @addtogroup sl_bt_evt_system_external_signal sl_bt_evt_system_external_signal + * @{ + * @brief Indicates that the external signals have been received + * + * External signals are generated from the native application. + */ + +/** @brief Identifier of the external_signal event */ +#define sl_bt_evt_system_external_signal_id 0x030100a0 + +/***************************************************************************//** + * @brief Data structure of the external_signal event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_external_signal_s +{ + uint32_t extsignals; /**< Bitmask of external signals received since last + event. */ +}); + +typedef struct sl_bt_evt_system_external_signal_s sl_bt_evt_system_external_signal_t; + +/** @} */ // end addtogroup sl_bt_evt_system_external_signal + +/** + * @addtogroup sl_bt_evt_system_awake sl_bt_evt_system_awake + * @{ + * @brief Indicates that the device is awake and no longer in sleep mode + * + * NOTE: Stack does not generate this event by itself because sleep and + * wakeup are managed by applications. If this event is needed, call function + * @ref sl_bt_send_system_awake, which signals the stack to send the event. + */ + +/** @brief Identifier of the awake event */ +#define sl_bt_evt_system_awake_id 0x040100a0 + +/** @} */ // end addtogroup sl_bt_evt_system_awake + +/** + * @addtogroup sl_bt_evt_system_soft_timer sl_bt_evt_system_soft_timer + * @{ + * @brief Indicates that a soft timer has lapsed. + */ + +/** @brief Identifier of the soft_timer event */ +#define sl_bt_evt_system_soft_timer_id 0x070100a0 + +/***************************************************************************//** + * @brief Data structure of the soft_timer event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_soft_timer_s +{ + uint8_t handle; /**< Timer Handle */ +}); + +typedef struct sl_bt_evt_system_soft_timer_s sl_bt_evt_system_soft_timer_t; + +/** @} */ // end addtogroup sl_bt_evt_system_soft_timer + +/***************************************************************************//** + * + * Verify whether the communication between the host and the device is + * functional. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_hello(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the on-demand start command is not available and the + * command returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to request starting the + * Bluetooth stack when the application needs it. If the command returns a + * success result, the stack starts to asynchronously allocate the resources and + * configure the Bluetooth stack based on the configuration passed at + * initialization time. + * + * The Bluetooth stack cannot be restarted while it's still stopping after + * issuing the command @ref sl_bt_system_stop_bluetooth. If @ref + * sl_bt_system_start_bluetooth is called when stopping is still on-going the + * command returns the error SL_STATUS_INVALID_STATE. The application must wait + * for the @ref sl_bt_evt_system_stopped event before attempting to restart the + * stack. + * + * Successful start of the stack is indicated by the @ref sl_bt_evt_system_boot + * event. The configured classes and Bluetooth stack features are available + * after the application has received the @ref sl_bt_evt_system_boot event. If + * starting the Bluetooth stack fails, the error is indicated to the application + * with the @ref sl_bt_evt_system_error event. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_boot - Triggered when the Bluetooth stack has + * succesfully started and is ready to accept commands from the application + * - @ref sl_bt_evt_system_error - Triggered if the command to start the + * Bluetooth stack was accepted but the asynchronous starting of the stack + * has failed + * + ******************************************************************************/ +sl_status_t sl_bt_system_start_bluetooth(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the stop command is not available and the command + * returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to stop the Bluetooth stack + * when the application no longer needs it. This command gracefully restores + * Bluetooth to an idle state by disconnecting any active connections and + * stopping any on-going advertising and scanning. Any resources that were + * allocated when the stack was started are freed when the stack has finished + * stopping. After this command, the BGAPI classes other than @ref sl_bt_system + * become unavailable. + * + * Stopping the Bluetooth stack with this command is asynchronous and the + * completion is indicated by the @ref sl_bt_evt_system_stopped event. The + * application can use the command @ref sl_bt_system_start_bluetooth to restart + * the stack any time after it has received the @ref sl_bt_evt_system_stopped + * event. If the application needs to stop the Bluetooth stack immediately, use + * the command @ref sl_bt_system_forcefully_stop_bluetooth. That command can + * also be used to immediately complete the asynchronous stopping if the command + * @ref sl_bt_system_stop_bluetooth has not completed in expected time period. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_stopped - Triggered when stopping the Bluetooth + * stack has completed + * + ******************************************************************************/ +sl_status_t sl_bt_system_stop_bluetooth(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the stop command is not available and the command + * returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to forcefully stop the + * Bluetooth stack when the application no longer needs it. This command + * immediately stops all active Bluetooth operations such as advertising, + * scanning, and connections. Active connections are forcefully closed without + * performing the ACL Termination procedure. This can result in the observation + * of connection loss or supervision timeout on the remote device. Only use this + * command for special cases, for example, when stopping Bluetooth with @ref + * sl_bt_system_stop_bluetooth did not complete in expected time period. + * + * Stopping the Bluetooth stack with this command is immediate and it directly + * triggers the @ref sl_bt_evt_system_stopped event. Any resources that were + * allocated when the stack was started are freed. After this command, the BGAPI + * classes other than @ref sl_bt_system become unavailable. The application can + * use the command @ref sl_bt_system_start_bluetooth to continue using Bluetooth + * later. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_stopped - Triggered immediately to indicate the + * Bluetooth stack has stopped + * + ******************************************************************************/ +sl_status_t sl_bt_system_forcefully_stop_bluetooth(); + +/***************************************************************************//** + * + * Get the firmware version information. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * @param[out] major Major release version + * @param[out] minor Minor release version + * @param[out] patch Patch release number + * @param[out] build Build number + * @param[out] bootloader Unused. Ignore this field. + * @param[out] hash Version hash + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_version(uint16_t *major, + uint16_t *minor, + uint16_t *patch, + uint16_t *build, + uint32_t *bootloader, + uint32_t *hash); + +/***************************************************************************//** + * + * Reset the system. This command does not have a response. + * + * On EFR series 1 devices, this command boots into the given mode and triggers + * one of the boot events (normal reset or boot to DFU mode) depending on the + * given boot mode. + * + * On EFR series 2 devices, the @p dfu parameter is ignored and this command + * always boots the user application. To boot into a DFU mode on series 2, use + * the Bootloader API @c bootloader_rebootAndInstall. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * @param[in] dfu @parblock + * Enum @ref sl_bt_system_boot_mode_t. Boot mode. Values: + * - sl_bt_system_boot_mode_normal (0x0): Boot to normal mode + * - sl_bt_system_boot_mode_uart_dfu (0x1): Boot to UART DFU mode + * - sl_bt_system_boot_mode_ota_dfu (0x2): Boot to OTA DFU mode + * + * This parameter is ignored on EFR series 2 devices. + * @endparblock + * + * @b Events + * - @ref sl_bt_evt_system_boot - Sent after the device has booted in normal + * mode. + * - @ref sl_bt_evt_dfu_boot - Sent after the device has booted in UART DFU + * mode. + * + ******************************************************************************/ +void sl_bt_system_reset(uint8_t dfu); + +/***************************************************************************//** + * + * Force radio to idle state and allow device to sleep. Advertising, scanning, + * connections, and software timers are halted by this command. Halted + * operations resume after calling this command with parameter 0. Connections + * stay alive if the system is resumed before connection supervision timeout. + * + * Use this command only for a short time period (maximum few seconds). Although + * it halts Bluetooth activity, all tasks and operations still exist inside the + * stack with their own concepts of time. Halting the system for a long time + * period may have negative consequences on stack's internal states. + * + * NOTE: The software timer is also halted. Hardware interrupts are the + * only way to wake up from energy mode 2 when the system is halted. + * + * @param[in] halt Values: + * - 1: halt + * - 0: resume + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_halt(uint8_t halt); + +/***************************************************************************//** + * + * Send configuration data to the link layer. This command fine tunes low-level + * Bluetooth operations. + * + * @param[in] key @parblock + * Enum @ref sl_bt_system_linklayer_config_key_t. Key to configure. Values: + * - sl_bt_system_linklayer_config_key_halt (0x1): Same as + * system_halt command, value-0 Stop Radio 1- Start Radio + * - sl_bt_system_linklayer_config_key_priority_range (0x2): Sets the + * RAIL priority_mapping offset field of the link layer priority + * configuration structure to the first byte of the value field. + * - sl_bt_system_linklayer_config_key_scan_channels (0x3): Sets + * channels to scan on. The first byte of the value is the channel map. + * 0x1 = Channel 37, 0x2 = Channel 38, 0x4 = Channel 39 + * - sl_bt_system_linklayer_config_key_set_flags (0x4): Sets the link + * layer configuration flags. The value is a little endian 32-bit integer. + * Flag Values: + * - 0x00000001 - Disable Feature Exchange in peripheral role of the + * connection + * - 0x00000002 - Disable Feature Exchange in central role of the + * connection + * + * - sl_bt_system_linklayer_config_key_clr_flags (0x5): The value is + * flags to clear. Flags are the same as in SET_FLAGS command. + * - sl_bt_system_linklayer_config_key_set_afh_interval (0x7): Set + * the afh_scan_interval. Value is in units of 10 ms. Setting the interval + * to 0 will result in using the default value of 1 second. + * - sl_bt_system_linklayer_config_key_set_priority_table (0x9): The + * value contains a priority table to be copied over the existing table. + * If the value is smaller than the full table, only those values are + * updated. See sl_bt_bluetooth_ll_priorities struct for the definition of + * a priority table. + * - sl_bt_system_linklayer_config_key_set_rx_packet_filtering (0xa): + * Configure and enable or disable RX packet filtering feature. Value: >= + * 5 bytes. + * - Byte 1 - The filter count + * - Byte 2 - The filter offset + * - Byte 3 - The length of the filter list + * - Byte 4 - The bitmask flags + * - Rest of the data - The filter list + * + * - sl_bt_system_linklayer_config_key_set_simultaneous_scanning + * (0xb): Enable or disable simultaneous scanning on the 1M and Coded + * PHYs. Value: 1 byte. + * - 0 - Disable simultaneous scanning. + * - 1 - Enable simultaneous scanning. + * + * - sl_bt_system_linklayer_config_key_set_channelmap_flags (0xc): + * Configure channelmap adaptivity flags. Value: 4 bytes. + * - sl_bt_system_linklayer_config_key_power_control_golden_range + * (0x10): Set Power Control golden range parameters. The value is a + * 8-bytes long array that consists of 4 pairs of golden range + * configurations. In each pair, the first byte is the lower RSSI boundary + * and the second byte is the upper RSSI boundary. RSSI values are in dBm. + * This configuration is not allowed if there are active Bluetooth + * connections. + * - Byte 1 - Minimal RSSI on 1M PHY + * - Byte 2 - Maximal RSSI on 1M PHY + * - Byte 3 - Minimal RSSI on 2M PHY + * - Byte 4 - Maximal RSSI on 2M PHY + * - Byte 5 - Minimal RSSI on Coded PHY S=8 + * - Byte 6 - Maximal RSSI on Coded PHY S=8 + * - Byte 7 - Minimal RSSI on Coded PHY S=2 + * - Byte 8 - Maximal RSSI on Coded PHY S=2 + * + * - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit + * (0x11): Value: uint16_t Adjust upper limit for backoff counter. If + * 0 restores default value of 256 Value must be between 16 - 256 + * - sl_bt_system_linklayer_config_key_afh_rssi_threshold (0x12): + * Value: int8_t Configures RSSI limit for AFH channel blocking + * - sl_bt_system_linklayer_config_key_afh_channel_cooldown (0x13): + * Value: int16_t Configures how long channel is blocked after activity is + * detected Default: 8000 + * - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps + * (0x14): Value: uint8_t 0 - default, only reports scan responses + * that is received after sending scan_req nonzero - Will report all scan + * responses that are received on primary advertising channels + * @endparblock + * @param[in] data_len Length of data in @p data + * @param[in] data Configuration data. Length and contents of the data field + * depend on the key value used. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_linklayer_configure(uint8_t key, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set the global minimum and maximum radiated TX power levels for Bluetooth. + * This returns selected power levels that are radiated from the antenna at TX. + * The transmitter power at antenna pin will apply the RF TX path gain to match + * this setting. RF TX path gain can be set in the Bluetooth configuration. If + * the GATT server contains a TX power service, the TX Power Level attribute + * will be updated with the selected maximum power level. + * + * A selected power level may be different than the requested value because of + * Bluetooth feature restrictions or the device's radio characteristics. For + * Bluetooth connections, the maximum radiated TX power is limited to 10 dBm if + * Adaptive Frequency Hopping (AFH) is not enabled. + * + * The minimum TX power setting is used by LE power control. It has no effect in + * Bluetooth stack if the LE power control feature is not enabled. However, the + * application may still use this setting for other purposes, e.g., setting the + * minimum TX power for DTM transmitter test. + * + * The minimum and maximum radiated TX power levels can also be configured in + * the Bluetooth configuration and passed into the Bluetooth stack + * initialization. By default, the minimum radiated TX power level is configured + * to -3 dBm and the maximum radiated TX power level to 8 dBm. + * + * NOTE: Do not use this command while advertising or scanning. + * Furthermore, the stack does not allow setting TX powers during connections. + * + * @param[in] min_power Minimum radiated TX power. Unit: 0.1 dBm. For example, + * the value 10 means 1 dBm. + * @param[in] max_power Maximum radiated TX power. Unit: 0.1 dBm. For example, + * the value 10 means 1 dBm. + * @param[out] set_min The selected minimum radiated TX power. Unit: 0.1 dBm + * @param[out] set_max The selected maximum radiated TX power. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_tx_power(int16_t min_power, + int16_t max_power, + int16_t *set_min, + int16_t *set_max); + +/***************************************************************************//** + * + * Get TX power settings including the minimum and maximum radiated TX power + * levels the device supports, the minimum and maximum radiated TX power levels + * currently set in the stack, and the TX RF path gain configuration. + * + * @param[out] support_min The minimum radiated TX power the device supports. + * Unit: 0.1 dBm + * @param[out] support_max The maximum radiated TX power the device supports. + * Unit: 0.1 dBm + * @param[out] set_min The minimum radiated TX power currently set in stack. + * Unit: 0.1 dBm + * @param[out] set_max The maximum radiated TX power currently set in stack. + * Unit: 0.1 dBm + * @param[out] rf_path_gain TX RF path gain. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, + int16_t *support_max, + int16_t *set_min, + int16_t *set_max, + int16_t *rf_path_gain); + +/***************************************************************************//** + * + * Store the device's Bluetooth identity address in persistent storage using NVM + * keys. The address can be a public device address or a static device address. + * The stack returns an error if the static device address does not conform to + * the Bluetooth specification. + * + * The new address will be effective in the next system reboot. The stack will + * use the address in the NVM keys when present. Otherwise, it uses the default + * Bluetooth public device address which is programmed at production. + * + * The stack treats 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid + * addresses. Therefore, passing one of them into this command will cause the + * stack to delete the NVM keys and use the default address in the next system + * reboot. + * + * Note: Because the NVM keys are located in flash and flash wearing can + * occur, avoid calling this command regularly. + * + * @param[in] address Bluetooth identity address in little endian format + * @param[in] type Enum @ref sl_bt_gap_address_type_t. Identity address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type); + +/***************************************************************************//** + * + * Read the Bluetooth identity address used by the device, which can be a public + * or random static device address. + * + * @param[out] address Bluetooth identity address in little endian format + * @param[out] type Enum @ref sl_bt_gap_address_type_t. Identity address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type); + +/***************************************************************************//** + * + * Get random data. + * + * @param[in] length Length of random data. + * @param[in] max_data_size Size of output buffer passed in @p data + * @param[out] data_len On return, set to the length of output data written to + * @p data + * @param[out] data Random data + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_random_data(uint8_t length, + size_t max_data_size, + size_t *data_len, + uint8_t *data); + +/***************************************************************************//** + * + * Write data into the system data buffer. Data will be appended to the end of + * existing data. + * + * @param[in] data_len Length of data in @p data + * @param[in] data Data to write + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_data_buffer_write(size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Remove all data from the system data buffer. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_data_buffer_clear(); + +/***************************************************************************//** + * + * Get packet and error counters. Passing a non-zero value also resets counters. + * + * @param[in] reset Reset counters if the parameter value is not zero. + * @param[out] tx_packets The number of successfully transmitted packets + * @param[out] rx_packets The number of successfully received packets + * @param[out] crc_errors The number of received packets with CRC errors + * @param[out] failures The number of radio failures, such as aborted TX/RX + * packets, scheduling failures, and so on. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_counters(uint8_t reset, + uint16_t *tx_packets, + uint16_t *rx_packets, + uint16_t *crc_errors, + uint16_t *failures); + +/***************************************************************************//** + * + * Deprecated . Use the sleeptimer component (in platform services + * category) for timers. Because the sleeptimer does not support a timer with + * slack yet, the Bluetooth stack will continue to support this command until + * another component provides the functionality. + * + * Start a software timer with slack. The slack parameter allows the stack to + * optimize wakeups and save power. The timer event is triggered between time + * and time + @p slack. + * + * Multiple concurrent timers can be running simultaneously. 256 unique timer + * handles (IDs) are available. The maximum number of concurrent timers is + * configurable at device initialization. Up to 16 concurrent timers can be + * configured. The default configuration is 4. As the RAM for storing timer data + * is pre-allocated at initialization, an application should not configure the + * amount more than it needs for minimizing RAM usage. + * + * @param[in] time @parblock + * An interval between how often to send events in hardware clock ticks (1 + * second is equal to 32768 ticks). + * + * The smallest interval value supported is 328, which is around 10 + * milliseconds. Any parameters between 0 and 328 will be rounded up to 328. + * The maximum value is 2147483647, which corresponds to about 18.2 hours. + * + * If @p time is 0, removes the scheduled timer with the same handle. + * @endparblock + * @param[in] slack Slack time in hardware clock ticks + * @param[in] handle Timer handle to use, which is returned in timeout event + * @param[in] single_shot Timer mode. Values: + * - 0: false (timer is repeating) + * - 1: true (timer runs only once) + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_soft_timer - Sent after this timer has lapsed. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, + uint32_t slack, + uint8_t handle, + uint8_t single_shot); + +/** @} */ // end addtogroup sl_bt_system + +/** + * @addtogroup sl_bt_resource Resource Report + * @{ + * + * @brief Resource Report + * + * Commands and events in this class can be used to query and receive the memory + * buffer usage status. The memory buffer is used by the Bluetooth stack for + * storing application data (e.g., API commands and events), user data over + * Bluetooth connections, advertising, scanning, etc. Total buffer size is + * defined by the application using the SL_BT_CONFIG_BUFFER_SIZE configuration. + * The Bluetooth stack does not partition the buffer, instead, the buffer is a + * shared resource for all features. Therefore, the available memory for one + * feature could be affected by another feature in simultaneous use cases. This + * API class provides a utility for application to get some insight of the + * buffer usage. As allocations in the memory buffer have overhead, the actual + * amount of memory that can be used for user data is less than a reported free + * memory amount. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_resource_get_status_id 0x005f0020 +#define sl_bt_cmd_resource_set_report_threshold_id 0x015f0020 +#define sl_bt_cmd_resource_enable_connection_tx_report_id 0x025f0020 +#define sl_bt_cmd_resource_get_connection_tx_status_id 0x035f0020 +#define sl_bt_cmd_resource_disable_connection_tx_report_id 0x045f0020 +#define sl_bt_rsp_resource_get_status_id 0x005f0020 +#define sl_bt_rsp_resource_set_report_threshold_id 0x015f0020 +#define sl_bt_rsp_resource_enable_connection_tx_report_id 0x025f0020 +#define sl_bt_rsp_resource_get_connection_tx_status_id 0x035f0020 +#define sl_bt_rsp_resource_disable_connection_tx_report_id 0x045f0020 + +/** + * @addtogroup sl_bt_resource_connection_tx_flags Connection TX status flags + * @{ + * + * Defines the connection TX status flags reported by @ref + * sl_bt_resource_get_connection_tx_status. + */ + +/** + * + * The number of TX packets queued on a connection has overflowed the @p + * packet_count that was effective at the time the connection opened. The packet + * count is configured with command @ref + * sl_bt_resource_enable_connection_tx_report and is valid for subsequent + * connections. + * + * When this bit is set, the @p packet_count returned by @ref + * sl_bt_resource_get_connection_tx_status is correct, but @p data_len excludes + * the data bytes in the packets that overflowed the configured packet count. + * + * */ +#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_PACKET_OVERFLOW 0x1 + +/** + * + * Internal inconsistency has been detected in the connection TX bookkeeping. + * When this bit is set, the application should consider both @p packet_count + * and @p data_len returned by @ref sl_bt_resource_get_connection_tx_status to + * be unreliable. + * + * */ +#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_CORRUPT 0x2 + +/** @} */ // end Connection TX status flags + +/** + * @addtogroup sl_bt_evt_resource_status sl_bt_evt_resource_status + * @{ + * @brief Indicates that the memory buffer usage has crossed a threshold + */ + +/** @brief Identifier of the status event */ +#define sl_bt_evt_resource_status_id 0x005f00a0 + +/***************************************************************************//** + * @brief Data structure of the status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_resource_status_s +{ + uint32_t free_bytes; /**< The number of free bytes in the memory buffer */ +}); + +typedef struct sl_bt_evt_resource_status_s sl_bt_evt_resource_status_t; + +/** @} */ // end addtogroup sl_bt_evt_resource_status + +/***************************************************************************//** + * + * Get the present memory buffer usage status. + * + * @param[out] total_bytes The number of total bytes in the memory buffer + * @param[out] free_bytes The number of free bytes in the memory buffer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, + uint32_t *free_bytes); + +/***************************************************************************//** + * + * Set low and high thresholds of memory buffer usage reports. Value 0 in + * parameter @p low for the low threshold disables the reporting, and a non-zero + * value in @p low enables the reporting. + * + * When the reporting is enabled, event @ref sl_bt_evt_resource_status will be + * generated to report the status when the free buffer amount decreases and + * crosses the low threshold, and later another event will be generated if the + * free buffer amount increases and crosses the high threshold. If only the high + * threshold is crossed but the low threshold isn't, no event will be generated. + * + * By default, low and high threshold values are 0, i.e., no report event is + * generated. + * + * @param[in] low The low threshold of free bytes in the memory buffer, or 0 to + * disable the reporting + * @param[in] high A non-zero value as the high threshold that must be greater + * than parameter @p low, or 0 for not reporting the status for high threshold + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high); + +/***************************************************************************//** + * + * Enable tracking and reporting data packet TX status of future new + * connections. Existing connections are not affected by this command. + * + * @param[in] packet_count The maximum number of data packets to track on a + * connection + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_server_notification_tx_completed - Sent when GATT + * notifications from the GATT server were transmitted. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count); + +/***************************************************************************//** + * + * Get the data packet TX status of a connection. + * + * @param[in] connection Connection handle + * @param[out] flags Flags that indicate the status of connection TX packet + * reporting. This value is a bitmask of @ref + * sl_bt_resource_connection_tx_flags. + * @param[out] packet_count Number of data packets in the TX queue waiting to be + * transmitted + * @param[out] data_len Total number of bytes of data packets in the TX queue + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, + uint16_t *flags, + uint16_t *packet_count, + uint32_t *data_len); + +/***************************************************************************//** + * + * Disable tracking and reporting data packet TX status of future new + * connections. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_disable_connection_tx_report(); + +/** @} */ // end addtogroup sl_bt_resource + +/** + * @addtogroup sl_bt_gap GAP + * @{ + * + * @brief GAP + * + * The commands and events in this class are related to the Generic Access + * Profile (GAP) in Bluetooth. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gap_set_privacy_mode_id 0x01020020 +#define sl_bt_cmd_gap_set_data_channel_classification_id 0x02020020 +#define sl_bt_cmd_gap_enable_whitelisting_id 0x03020020 +#define sl_bt_cmd_gap_set_identity_address_id 0x04020020 +#define sl_bt_rsp_gap_set_privacy_mode_id 0x01020020 +#define sl_bt_rsp_gap_set_data_channel_classification_id 0x02020020 +#define sl_bt_rsp_gap_enable_whitelisting_id 0x03020020 +#define sl_bt_rsp_gap_set_identity_address_id 0x04020020 + +/** + * @brief These values define Bluetooth device address types. Commands and + * events that have Bluetooth device address parameters will specify which + * values are valid for that particular command or event. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, most Bluetooth + * commands and events use a coarse address type that only differentiates + * between a public address and any random address. When the application + * includes the bluetooth_feature_use_accurate_api_address_types component, + * Bluetooth commands and events that include an address type will + * systematically use values of this @ref sl_bt_gap_address_type_t enumeration + * to indicate the accurate address type. + * + * The values @ref sl_bt_gap_public_address_resolved_from_rpa and @ref + * sl_bt_gap_static_address_resolved_from_rpa are reported by the Bluetooth + * stack only when the application includes the bluetooth_feature_resolving_list + * component and the address was resolved in the Bluetooth controller. If the + * application uses these two types in input parameters, they are treated as + * synonyms of @ref sl_bt_gap_public_address and @ref sl_bt_gap_static_address, + * respectively. + */ +typedef enum +{ + sl_bt_gap_public_address = 0x0, /**< (0x0) Public device + address */ + sl_bt_gap_static_address = 0x1, /**< (0x1) Static device + address */ + sl_bt_gap_random_resolvable_address = 0x2, /**< (0x2) Resolvable + private random address */ + sl_bt_gap_random_nonresolvable_address = 0x3, /**< (0x3) Non-resolvable + private random address */ + sl_bt_gap_public_address_resolved_from_rpa = 0x4, /**< (0x4) Public identity + address resolved from + a resolvable private + address (RPA) */ + sl_bt_gap_static_address_resolved_from_rpa = 0x5, /**< (0x5) Static identity + address resolved from + a resolvable private + address (RPA) */ + sl_bt_gap_anonymous_address = 0xff /**< (0xff) No address + provided (anonymous + advertising) */ +} sl_bt_gap_address_type_t; + +/** + * @brief Types of PHYs + */ +typedef enum +{ + sl_bt_gap_phy_1m = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_phy_2m = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_phy_coded = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ + sl_bt_gap_phy_any = 0xff /**< (0xff) Any PHYs the device supports */ +} sl_bt_gap_phy_t; + +/** + * @brief PHY types with coding schemes + */ +typedef enum +{ + sl_bt_gap_phy_coding_1m_uncoded = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_phy_coding_2m_uncoded = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_phy_coding_125k_coded = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ + sl_bt_gap_phy_coding_500k_coded = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ +} sl_bt_gap_phy_coding_t; + +/** + * @brief Types of channel selection algorithms in Link Layer + */ +typedef enum +{ + sl_bt_gap_channel_selection_algorithm_1 = 0x0, /**< (0x0) Channel selection + algorithm #1 */ + sl_bt_gap_channel_selection_algorithm_2 = 0x1 /**< (0x1) Channel selection + algorithm #2 */ +} sl_bt_gap_channel_selection_algorithm_t; + +/***************************************************************************//** + * + * Enable or disable the privacy feature on all GAP roles. New privacy mode will + * take effect for advertising next time advertising is enabled, for scanning + * next time scanning is enabled, and for initiating on the next open connection + * command. + * + * When privacy is enabled and the device is advertising or scanning, the stack + * will maintain a periodic timer with the specified time interval as a timeout + * value. At each timeout, the stack generates a new resolvable private address + * and uses it in scanning requests. For advertisers, the stack generates a new + * resolvable or non-resolvable private address and uses it in advertising data + * packets for each advertising set if its address is not application-managed, + * i.e., the address was not set by the application (with the @ref + * sl_bt_advertiser_set_random_address command). The application is fully + * responsible for application-managed advertiser addresses. For an + * application-managed resolvable private address, the application should + * schedule periodic address updates for enhancing the privacy. It is + * recommended to use different schedules for different advertising sets. + * + * Disabling the privacy during active advertising or scanning is not allowed. + * + * By default, privacy feature is disabled. + * + * @param[in] privacy Values: + * - 0: Disable privacy + * - 1: Enable privacy + * @param[in] interval The minimum time interval between a private address + * change. This parameter is ignored if this command is issued to disable + * privacy mode. Values: + * - 0: Use default interval, 15 minutes + * - others: The time interval in minutes + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval); + +/***************************************************************************//** + * + * Specify a channel classification for data channels. This classification + * persists until overwritten with a subsequent command or until the system is + * reset. The value length of @p channel_map must be 5 bytes. + * + * @param[in] channel_map_len Length of data in @p channel_map + * @param[in] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Bits 37-39 are reserved for future use and must be set to 0. + * + * A channel is bad when its bit is 0. A channel is unknown when its bit is 1. + * At least two channels shall be marked as unknown. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, + const uint8_t* channel_map); + +/***************************************************************************//** + * + * Deprecated and replaced by functionality-specific settings provided by + * the bluetooth_feature_accept_list component. For advertising, use the command + * @ref sl_bt_advertiser_configure and @p flags bits @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to configure the + * advertising filter policy. For scanning, use the command @ref + * sl_bt_scanner_set_parameters_and_filter to control the scanning filter + * policy. + * + * Enable or disable accept list filtering. The setting will be effective the + * next time that scanning is enabled. Use command @ref + * sl_bt_sm_add_to_whitelist to add devices to the accept list. + * + * When the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) is used, bonded devices are + * added into the accept list automatically by the stack. Note that the + * Bluetooth stack uses the built-in bonding database by default. + * + * When the application specifically uses the external bonding database + * (bluetooth_feature_external_bonding_database), the application is fully + * responsible for managing the accept list using @ref sl_bt_sm_add_to_whitelist + * and @ref sl_bt_sm_delete_bondings commands. + * + * @param[in] enable 1 enable, 0 disable accept list filtering. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable); + +/***************************************************************************//** + * + * Set the device's Bluetooth identity address to be used in advertising, + * scanning, connection initiation, and identity address exchange in bonding. + * The address is stored in RAM only and does not change the identity address in + * persistent storage. The address can be a public device address or static + * device address. It will be effective immediately in the next advertising, + * scanning, connection initiation, and bonding. Error + * SL_STATUS_INVALID_PARAMETER is returned if the address does not conform to + * the Bluetooth specification. + * + * Note that advertising sets that have own addresses set by @ref + * sl_bt_advertiser_set_random_address are not affected by this command, i.e., + * they will continue to use their own user defined addresses. + * + * @param[in] address The address in little endian format + * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. The address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type); + +/** @} */ // end addtogroup sl_bt_gap + +/** + * @addtogroup sl_bt_advertiser Advertiser + * @{ + * + * @brief Advertiser + * + * This is the base class of legacy, extended, and periodic advertisings for + * common functionalities including advertising set management, TX power + * setting, advertising address, and so on. + * + * On an advertising set, either the legacy or extended advertising can be + * enabled at a time but they cannot be enabled simultaneously on the same + * advertising set. For example, the following sequence shows how to start the + * legacy advertising on an advertising set. Starting the extended advertising + * is similar. The only difference is to use the extended_advertiser API class. + * 1. Create an advertise set with the @ref sl_bt_advertiser_create_set + * command. + * 2. Configure and set advertising parameters for the advertising set as + * needed. + * 3. Set the advertising data with the @ref sl_bt_legacy_advertiser_set_data + * or @ref sl_bt_legacy_advertiser_generate_data command. + * 4. Start the legacy advertising with the @ref sl_bt_legacy_advertiser_start + * command. + * + * Periodic advertising can be enabled independently on the advertising set + * regardless of the state of the legacy or extended advertising. However, to + * ensure that scanners can find the periodic advertising information and + * establish a synchronization, the extended advertising must be enabled + * simultaneously with the periodic advertising. + * + * When the bluetooth_feature_legacy_advertiser, + * bluetooth_feature_extended_advertiser or + * bluetooth_feature_periodic_advertiser component is included by the + * application, commands that have been superseded by the new classes are no + * longer available for use in the advertiser class. Calling them will receive + * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: @ref + * sl_bt_advertiser_set_phy, @ref sl_bt_advertiser_set_configuration, @ref + * sl_bt_advertiser_clear_configuration, @ref sl_bt_advertiser_set_data, @ref + * sl_bt_advertiser_set_long_data, @ref sl_bt_advertiser_start, @ref + * sl_bt_advertiser_start_periodic_advertising, and @ref + * sl_bt_advertiser_stop_periodic_advertising. See the command descriptions for + * the replacements. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_advertiser_create_set_id 0x01040020 +#define sl_bt_cmd_advertiser_configure_id 0x12040020 +#define sl_bt_cmd_advertiser_set_timing_id 0x03040020 +#define sl_bt_cmd_advertiser_set_channel_map_id 0x04040020 +#define sl_bt_cmd_advertiser_set_tx_power_id 0x0b040020 +#define sl_bt_cmd_advertiser_set_report_scan_request_id 0x05040020 +#define sl_bt_cmd_advertiser_set_random_address_id 0x10040020 +#define sl_bt_cmd_advertiser_clear_random_address_id 0x11040020 +#define sl_bt_cmd_advertiser_stop_id 0x0a040020 +#define sl_bt_cmd_advertiser_delete_set_id 0x02040020 +#define sl_bt_cmd_advertiser_set_phy_id 0x06040020 +#define sl_bt_cmd_advertiser_set_configuration_id 0x07040020 +#define sl_bt_cmd_advertiser_clear_configuration_id 0x08040020 +#define sl_bt_cmd_advertiser_set_data_id 0x0f040020 +#define sl_bt_cmd_advertiser_set_long_data_id 0x0e040020 +#define sl_bt_cmd_advertiser_start_id 0x09040020 +#define sl_bt_cmd_advertiser_start_periodic_advertising_id 0x0c040020 +#define sl_bt_cmd_advertiser_stop_periodic_advertising_id 0x0d040020 +#define sl_bt_rsp_advertiser_create_set_id 0x01040020 +#define sl_bt_rsp_advertiser_configure_id 0x12040020 +#define sl_bt_rsp_advertiser_set_timing_id 0x03040020 +#define sl_bt_rsp_advertiser_set_channel_map_id 0x04040020 +#define sl_bt_rsp_advertiser_set_tx_power_id 0x0b040020 +#define sl_bt_rsp_advertiser_set_report_scan_request_id 0x05040020 +#define sl_bt_rsp_advertiser_set_random_address_id 0x10040020 +#define sl_bt_rsp_advertiser_clear_random_address_id 0x11040020 +#define sl_bt_rsp_advertiser_stop_id 0x0a040020 +#define sl_bt_rsp_advertiser_delete_set_id 0x02040020 +#define sl_bt_rsp_advertiser_set_phy_id 0x06040020 +#define sl_bt_rsp_advertiser_set_configuration_id 0x07040020 +#define sl_bt_rsp_advertiser_clear_configuration_id 0x08040020 +#define sl_bt_rsp_advertiser_set_data_id 0x0f040020 +#define sl_bt_rsp_advertiser_set_long_data_id 0x0e040020 +#define sl_bt_rsp_advertiser_start_id 0x09040020 +#define sl_bt_rsp_advertiser_start_periodic_advertising_id 0x0c040020 +#define sl_bt_rsp_advertiser_stop_periodic_advertising_id 0x0d040020 + +/** + * @brief These values define the available connection modes, which indicate + * whether the device accepts connection requests or scan requests. + */ +typedef enum +{ + sl_bt_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable + non-scannable */ + sl_bt_advertiser_connectable_scannable = 0x2, /**< (0x2) Undirected + connectable scannable. + This mode can only be + used in legacy + advertising PDUs. */ + sl_bt_advertiser_scannable_non_connectable = 0x3, /**< (0x3) Undirected + scannable + (Non-connectable but + responds to scan + requests) */ + sl_bt_advertiser_connectable_non_scannable = 0x4 /**< (0x4) Undirected + connectable + non-scannable. This + mode can only be used + in extended advertising + PDUs. */ +} sl_bt_advertiser_connection_mode_t; + +/** + * @brief These values define the available discovery modes, which dictate how + * the device is visible to other devices in the legacy and extended + * advertising. + */ +typedef enum +{ + sl_bt_advertiser_non_discoverable = 0x0, /**< (0x0) Not discoverable */ + sl_bt_advertiser_limited_discoverable = 0x1, /**< (0x1) Discoverable by both + limited and general + discovery procedures */ + sl_bt_advertiser_general_discoverable = 0x2, /**< (0x2) Discoverable by the + general discovery procedure */ + sl_bt_advertiser_broadcast = 0x3, /**< (0x3) Device is not + discoverable in either + limited or generic discovery + procedure but may be + discovered using the + Observation procedure. */ + sl_bt_advertiser_user_data = 0x4 /**< (0x4) Send advertising + and/or scan response data + defined by the user. The + discovery mode is defined by + the user. */ +} sl_bt_advertiser_discovery_mode_t; + +/** + * @brief Address type to use for the legacy and extended advertising + */ +typedef enum +{ + sl_bt_advertiser_identity_address = 0x0, /**< (0x0) Use public or static + device address, or an identity + address if privacy mode is + enabled. */ + sl_bt_advertiser_non_resolvable = 0x1 /**< (0x1) Use non-resolvable address + type; the advertising must be + non-connectable. */ +} sl_bt_advertiser_adv_address_type_t; + +/** + * @brief These values define the packet types in legacy and extended + * advertising. + */ +typedef enum +{ + sl_bt_advertiser_advertising_data_packet = 0x0, /**< (0x0) Advertising data + packet */ + sl_bt_advertiser_scan_response_packet = 0x1 /**< (0x1) Scan response + packet */ +} sl_bt_advertiser_packet_type_t; + +/** + * @addtogroup sl_bt_advertiser_flags Generic Advertising Configuration Flags + * @{ + * + * This enum defines configuration flags common for legacy and extended + * advertisings. + */ + +/** Use a non-resolvable private address managed by the stack. The advertising + * must be non-connectable when using this configuration. The stack generates a + * non-resolvable private address for the advertising set and the stack will + * update the address periodically in privacy mode. By default this flag is not + * set, i.e., the advertising address uses the device identity address. This + * configuration has no effect if the advertising address has been set with the + * @ref sl_bt_advertiser_set_random_address command. */ +#define SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS 0x4 + +/** Use the device identity address when privacy mode is enabled. By default, + * this flag is not set, i.e., the advertising address uses a resolvable private + * address managed by the stack in privacy mode. This configuration has no + * effect if the @ref SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS flag is set or + * the advertising address has been set with the @ref + * sl_bt_advertiser_set_random_address command. */ +#define SL_BT_ADVERTISER_USE_DEVICE_IDENTITY_IN_PRIVACY 0x10 + +/** + * + * Use the Filter Accept List to filter scan requests received while performing + * scannable advertising with this advertising set. By default, this flag is not + * set and scan requests from all devices are processed. If the application sets + * this flag, scan requests are processed only from those devices that the + * application has added to the Filter Accept List. + * + * This configuration is supported only when the application has included the + * Bluetooth component bluetooth_feature_accept_list. + * + * */ +#define SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS 0x20 + +/** + * + * Use the Filter Accept List to filter connection requests received while + * performing connectable advertising with this advertising set. By default, + * this flag is not set and connection requests from all devices are processed. + * If the application sets this flag, connection requests are processed only + * from those devices that the application has added to the Filter Accept List. + * + * This configuration is supported only when the application has included the + * Bluetooth component bluetooth_feature_accept_list. + * + * */ +#define SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS 0x40 + +/** @} */ // end Generic Advertising Configuration Flags + +/** + * @addtogroup sl_bt_evt_advertiser_timeout sl_bt_evt_advertiser_timeout + * @{ + * @brief Indicates the legacy or extended advertising on an advertising set has + * stopped because the advertiser has completed the configured number of + * advertising events or the advertising has reached the configured duration + * + * The maximum number of advertising events or advertising duration can be + * configured by the @p maxevents or @p duration parameter in the command @ref + * sl_bt_advertiser_set_timing. + */ + +/** @brief Identifier of the timeout event */ +#define sl_bt_evt_advertiser_timeout_id 0x010400a0 + +/***************************************************************************//** + * @brief Data structure of the timeout event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_advertiser_timeout_s +{ + uint8_t handle; /**< The advertising set handle */ +}); + +typedef struct sl_bt_evt_advertiser_timeout_s sl_bt_evt_advertiser_timeout_t; + +/** @} */ // end addtogroup sl_bt_evt_advertiser_timeout + +/** + * @addtogroup sl_bt_evt_advertiser_scan_request sl_bt_evt_advertiser_scan_request + * @{ + * @brief Reports a scan request received during the legacy or extended + * advertising advertising if the scan request notification is enabled + * + * Do not confuse this event with the @ref sl_bt_evt_scanner_scan_report event. + */ + +/** @brief Identifier of the scan_request event */ +#define sl_bt_evt_advertiser_scan_request_id 0x020400a0 + +/***************************************************************************//** + * @brief Data structure of the scan_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_advertiser_scan_request_s +{ + uint8_t handle; /**< Advertising set handle where the scan request was + received */ + bd_addr address; /**< Bluetooth address of the scanner */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Scanner address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): Public + device address + - sl_bt_gap_static_address (0x1): Static + device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote scanning device has + previously bonded with the local device. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): No + bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_advertiser_scan_request_s sl_bt_evt_advertiser_scan_request_t; + +/** @} */ // end addtogroup sl_bt_evt_advertiser_scan_request + +/***************************************************************************//** + * + * Create an advertising set that can be used for legacy, extended, or periodic + * advertising. The handle of the created advertising set is returned in + * response if the operation succeeds. + * + * The maximum number of advertising sets for user advertisers is limited by the + * SL_BT_CONFIG_USER_ADVERTISERS configuration. + * + * @param[out] handle Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_create_set(uint8_t *handle); + +/***************************************************************************//** + * + * Configure the legacy and extended advertising on an advertising set. The + * configuration will take effect next time the legacy or extended advertising + * is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] flags @parblock + * Configuration flags. Value: 0 or bitmask of @ref sl_bt_advertiser_flags + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags); + +/***************************************************************************//** + * + * Set the timing parameters for legacy or extended advertising on an + * advertising set. This setting will take effect next time the legacy or + * extended advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum advertising interval. Value in units of 0.625 ms + * - Range: 0x20 to 0xFFFFFF + * - Time range: 20 ms to 10485.759375 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum advertising interval. Value in units of 0.625 ms + * - Range: 0x20 to 0xFFFFFF + * - Time range: 20 ms to 10485.759375 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] duration @parblock + * Advertising duration for this advertising set. Value 0 indicates no + * advertising duration limit and advertising continues until it is disabled. + * A non-zero value sets the duration in units of 10 ms. The duration begins + * at the start of the first advertising event of this advertising set. + * - Range: 0x0001 to 0xFFFF + * - Time range: 10 ms to 655.35 s + * + * Default value: 0 + * @endparblock + * @param[in] maxevents @parblock + * If non-zero, indicates the maximum number of advertising events to send + * before the advertiser is stopped. Value 0 indicates no maximum number + * limit. + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, + uint32_t interval_min, + uint32_t interval_max, + uint16_t duration, + uint8_t maxevents); + +/***************************************************************************//** + * + * Set the primary advertising channel map on an advertising set. This setting + * will take effect next time when the legacy or extended advertising is + * enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] channel_map @parblock + * Advertising channel map which determines, which of the three channels will + * be used for advertising. This value is given as a bitmask. Values: + * - 1: Advertise on CH37 + * - 2: Advertise on CH38 + * - 3: Advertise on CH37 and CH38 + * - 4: Advertise on CH39 + * - 5: Advertise on CH37 and CH39 + * - 6: Advertise on CH38 and CH39 + * - 7: Advertise on all channels + * + * Recommended value: 7 + * + * Default value: 7 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, + uint8_t channel_map); + +/***************************************************************************//** + * + * Limit the maximum advertising TX power on an advertising set. If the value + * goes over the global value that was set using the @ref + * sl_bt_system_set_tx_power command, the global value will be the maximum + * limit. The maximum TX power of legacy advertising is further constrained to + * be less than +10 dBm. Extended advertising TX power can be +10 dBm and over + * if Adaptive Frequency Hopping is enabled. This setting has no effect on + * periodic advertising. + * + * This setting will take effect next time the legacy or extended advertising is + * enabled. + * + * By default, maximum advertising TX power is limited by the global value. + * + * @param[in] advertising_set Advertising set handle + * @param[in] power TX power in 0.1 dBm steps. For example, the value of 10 is 1 + * dBm and 55 is 5.5 dBm. + * @param[out] set_power The selected maximum advertising TX power + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, + int16_t power, + int16_t *set_power); + +/***************************************************************************//** + * + * Enable or disable the scan request notification on an advertising set. This + * setting will take effect next time the legacy or extended advertising is + * enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] report_scan_req @parblock + * If non-zero, enables scan request notification and scan requests will be + * reported as events. + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_scan_request - Triggered when a scan request is + * received during advertising if the scan request notification is enabled + * by this command. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, + uint8_t report_scan_req); + +/***************************************************************************//** + * + * Set the advertiser on an advertising set to use a random address. This + * overrides the default advertiser address, which is either the public device + * address programmed at production or the address written into persistent + * storage using @ref sl_bt_system_set_identity_address command. This setting is + * stored in RAM only and does not change the identity address in persistent + * storage. In privacy mode, the stack does not change an advertiser address set + * by this command. To ensure that the stack can manage the address update + * periodically in privacy mode, the address setting should be removed with the + * @ref sl_bt_advertiser_clear_random_address command. + * + * When setting a resolvable random address, the address parameter is ignored. + * The stack generates one and set it as the advertiser address. The generated + * address is returned in the response. To enhance the privacy, the application + * should schedule periodic address updates by calling this command + * periodically. Use different schedules for different advertising sets. + * + * To use the default advertiser address, remove this setting using @ref + * sl_bt_advertiser_clear_random_address command. + * + * Wrong state error is returned if advertising has been enabled on the + * advertising set. Invalid parameter error is returned if the advertising set + * handle is invalid or the address does not conform to the Bluetooth + * specification. + * + * @param[in] advertising_set Advertising set handle + * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. Address type. + * Values: + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address. This type can only be used for non-connectable + * advertising. + * @param[in] address The random address to set. Ignore this field when setting + * a resolvable random address. + * @param[out] address_out The resolvable random address set for the advertiser. + * Ignore this field when setting other types of random addresses. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, + uint8_t addr_type, + bd_addr address, + bd_addr *address_out); + +/***************************************************************************//** + * + * Clear the random address previously set for the advertiser address on an + * advertising set. To set a random address, use @ref + * sl_bt_advertiser_set_random_address command. The default advertiser address + * will be used after this operation. + * + * The error SL_STATUS_INVALID_STATE is returned if advertising has been enabled + * on the advertising set. An invalid parameter error is returned if the + * advertising set handle is invalid. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set); + +/***************************************************************************//** + * + * Stop the legacy or extended advertising on an advertising set. Counterpart + * with @ref sl_bt_legacy_advertiser_start or @ref + * sl_bt_extended_advertiser_start. + * + * This command does not affect the enable state of the periodic advertising on + * the advertising set, i.e., periodic advertising is not stopped. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set); + +/***************************************************************************//** + * + * Delete an advertising set. Any enabled legacy, extended, or periodic + * advertising is stopped before the deletion. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_extended_advertiser_set_phy. + * + * Set the primary and secondary advertising PHYs used for extended and periodic + * advertising on an advertising set. This setting will take effect next time + * extended or periodic advertising is enabled. When advertising on the LE Coded + * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is + * returned if a PHY value is invalid or the device does not support a given + * PHY. + * + * @param[in] advertising_set Advertising set handle + * @param[in] primary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the primary advertising channel. If legacy advertising PDUs + * are used, 1M PHY must be used. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * @param[in] secondary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the secondary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_advertiser_configure command. + * + * Enable advertising configuration flags on an advertising set. The + * configuration change will take effect next time the legacy or extended + * advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] configurations @parblock + * Advertising configuration flags to enable. This value can be a bitmask of + * multiple flags. Flags: + * - 1 (Bit 0): Use legacy advertising PDUs. + * - 2 (Bit 1): Omit advertiser's address from all PDUs (anonymous + * advertising). This flag is effective only in extended advertising. + * - 4 (Bit 2): Use a non-resolvable private address. When this + * configuration is enabled, the advertising must use non-connectable + * mode. The stack generates a non-resolvable private address for the + * advertising set and the stack will update the address periodically when + * the privacy mode is enabled. This configuration is ignored if the + * advertiser address has been set with the @ref + * sl_bt_advertiser_set_random_address command. + * - 8 (Bit 3): Include TX power in advertising packets. This flag is + * effective only in extended advertising. + * - 16 (Bit 4): Use the device identity address when the privacy + * mode is enabled in the stack. This configuration is ignored if the + * configuration of using non-resolvable private address is enabled or the + * advertising address has been set with the @ref + * sl_bt_advertiser_set_random_address command. + * + * Default value: 1 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, + uint32_t configurations); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_advertiser_configure command. + * + * Disable advertising configuration flags on an advertising set. The + * configuration change will take effect next time the legacy or extended + * advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] configurations Advertising configuration flags to disable. This + * value can be a bitmask of multiple flags. See @ref + * sl_bt_advertiser_set_configuration for possible flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, + uint32_t configurations); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_legacy_advertiser_set_data for + * legacy advertising PDUs, @ref sl_bt_extended_advertiser_set_data for extended + * advertising PDUs, and @ref sl_bt_periodic_advertiser_set_data for periodic + * advertising PDUs. + * + * Set user-defined data in advertising packets, scan response packets, or + * periodic advertising packets. Maximum 31 bytes of data can be set for legacy + * advertising. Maximum 191 bytes of data can be set for connectable extended + * advertising. Maximum 253 bytes of data can be set for periodic and + * non-connectable extended advertising. For setting longer advertising data, + * use command @ref sl_bt_advertiser_set_long_data. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_advertiser_start. Periodic advertising mode can be enabled using + * command @ref sl_bt_advertiser_start_periodic_advertising. + * + * The invalid parameter error will be returned in the following situations: + * - Data length is more than 31 bytes but the advertiser can only advertise + * using legacy advertising PDUs. + * - Data is too long to fit into a single advertisement. + * - Set data of the advertising data packet when the scannable advertising is + * enabled using extended advertising PDUs. + * - Set data of the scan response data packet when the connectable + * advertising is enabled using extended advertising PDUs. + * + * Note that the user-defined data may be overwritten by the system when the + * advertising is later enabled in a discovery mode other than user_data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] packet_type This value selects whether data is intended for + * advertising packets, scan response packets, or periodic advertising + * packets. + * - 0: Advertising packets + * - 1: Scan response packets + * - 8: Periodic advertising packets + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, + uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_extended_advertiser_set_long_data for extended advertising PDUs and + * @ref sl_bt_periodic_advertiser_set_long_data for periodic advertising PDUs. + * + * Set advertising data for a specified packet type and advertising set. Data + * currently in the system data buffer will be extracted as the advertising + * data. The buffer will be emptied after this command regardless of the + * completion status. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. + * + * Maximum 31 bytes of data can be set for legacy advertising. Maximum 191 bytes + * of data can be set for connectable extended advertising. Maximum 1650 bytes + * of data can be set for periodic and non-connectable extended advertising, but + * advertising parameters may limit the amount of data that can be sent in a + * single advertisement. + * + * See @ref sl_bt_advertiser_set_data for more details on advertising data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] packet_type This value selects whether data is intended for + * advertising packets, scan response packets, or periodic advertising + * packets. Values: + * - 0: Advertising packets + * - 1: Scan response packets + * - 8: Periodic advertising packets + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, + uint8_t packet_type); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_legacy_advertiser_start and @ref + * sl_bt_extended_advertiser_start commands. + * + * Start the legacy or extended advertising on an advertising set with specified + * discovery and connection modes. + * + * The number of concurrent connectable advertisings is limited by the number of + * connections reserved by the user application (the + * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other + * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This + * command fails with the connection limit exceeded error if it may cause the + * number of connections exceeding the configured value in future. For example, + * only one connectable advertising can be enabled if the device has + * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. + * This limitation does not apply to non-connectable advertising. + * + * The default advertising configuration in the stack is set to using legacy + * advertising PDUs on 1M PHY. The stack will automatically select extended + * advertising PDUs if either of the following has occurred with the default + * configuration: + * 1. The connection mode is set to @ref + * sl_bt_advertiser_connectable_non_scannable. + * 2. The primary advertising PHY is set to Coded PHY by @ref + * sl_bt_extended_advertiser_set_phy. + * 3. The user advertising data length is more than 31 bytes. + * 4. Periodic advertising is enabled. + * + * This command fails with the invalid parameter error if one of the following + * cases occurs: + * 1. Non-resolvable random address is used but the connection mode is + * advertiser_connectable_scannable or + * advertiser_connectable_non_scannable. + * 2. advertiser_connectable_non_scannable is the connection mode but using + * legacy advertising PDUs has been explicitly enabled with command @ref + * sl_bt_advertiser_set_configuration. + * 3. Coded PHY is the primary advertising PHY but using legacy advertising + * PDUs has been explicitly enabled with command @ref + * sl_bt_advertiser_set_configuration. + * 4. advertiser_connectable_scannable is the connection mode but using + * extended advertising PDUs has been explicitly enabled or the primary + * advertising PHY is set to Coded PHY. + * + * If advertising is enabled in user_data mode, use @ref + * sl_bt_advertiser_set_data to set advertising and scan response data before + * issuing this command. When advertising is enabled in modes other than + * user_data, advertising and scan response data is generated by the stack using + * the following procedure: + * 1. Add a flags field to advertising data. + * 2. Add a TX power level field to advertising data if the TX power service + * exists in the local GATT database. + * 3. Add a peripheral connection interval range field to advertising data if + * the GAP peripheral preferred connection parameters characteristic exists + * in the local GATT database. + * 4. Add a list of 16-bit service UUIDs to advertising data if there are one + * or more 16-bit service UUIDs to advertise. The list is complete if all + * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is + * incomplete. + * 5. Add a list of 128-bit service UUIDs to advertising data if there are one + * or more 128-bit service UUIDs to advertise and there is still free space + * for this field. The list is complete if all advertised 128-bit UUIDs are + * in advertising data. Otherwise, the list is incomplete. Note that an + * advertising data packet can contain at most one 128-bit service UUID. + * 6. Try to add the full local name to advertising data if the device is not + * in privacy mode. If the full local name does not fit into the remaining + * free space, the advertised name is a shortened version by cutting off + * the end if the free space has at least 6 bytes. Otherwise, the local + * name is added to scan response data. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. Discovery + * mode. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * - sl_bt_advertiser_broadcast (0x3): Device is not discoverable in + * either limited or generic discovery procedure but may be discovered + * using the Observation procedure. + * - sl_bt_advertiser_user_data (0x4): Send advertising and/or scan + * response data defined by the user. The discovery mode is defined by the + * user. + * @param[in] connect Enum @ref sl_bt_advertiser_connection_mode_t. Connection + * mode. Values: + * - sl_bt_advertiser_non_connectable (0x0): Non-connectable + * non-scannable + * - sl_bt_advertiser_connectable_scannable (0x2): Undirected + * connectable scannable. This mode can only be used in legacy advertising + * PDUs. + * - sl_bt_advertiser_scannable_non_connectable (0x3): Undirected + * scannable (Non-connectable but responds to scan requests) + * - sl_bt_advertiser_connectable_non_scannable (0x4): Undirected + * connectable non-scannable. This mode can only be used in extended + * advertising PDUs. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and advertising has stopped on an advertising set. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, + uint8_t discover, + uint8_t connect); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_periodic_advertiser_start + * command. + * + * Start periodic advertising on an advertising set. The stack enables the + * advertising set automatically if the set was not enabled and the set can + * advertise using extended advertising PDUs beside the syncInfo, which is + * needed for the periodic advertising. + * + * The invalid parameter error is returned if the application has configured + * legacy advertising PDUs or anonymous advertising, or the advertising set is + * enabled using legacy advertising PDUs. + * + * To stop periodic advertising, use @ref + * sl_bt_advertiser_stop_periodic_advertising command with the handle received + * in response from this command. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Periodic advertising configurations. Bitmask of the + * following: + * - Bit 0: Include TX power in advertising PDU + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_periodic_advertiser_stop + * command. + * + * Stop periodic advertising on an advertising set. Counterpart with @ref + * sl_bt_advertiser_start_periodic_advertising. + * + * This command does not affect the enable state of the advertising set, i.e., + * legacy or extended advertising is not stopped. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_advertiser + +/** + * @addtogroup sl_bt_legacy_advertiser Legacy Advertiser + * @{ + * + * @brief Legacy Advertiser + * + * The commands and events in this class are related to legacy advertising + * functionalities. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_legacy_advertiser_set_data_id 0x00560020 +#define sl_bt_cmd_legacy_advertiser_generate_data_id 0x01560020 +#define sl_bt_cmd_legacy_advertiser_start_id 0x02560020 +#define sl_bt_cmd_legacy_advertiser_start_directed_id 0x03560020 +#define sl_bt_rsp_legacy_advertiser_set_data_id 0x00560020 +#define sl_bt_rsp_legacy_advertiser_generate_data_id 0x01560020 +#define sl_bt_rsp_legacy_advertiser_start_id 0x02560020 +#define sl_bt_rsp_legacy_advertiser_start_directed_id 0x03560020 + +/** + * @brief These values define the available connection modes of undirected + * legacy advertising. + */ +typedef enum +{ + sl_bt_legacy_advertiser_non_connectable = 0x0, /**< (0x0) Undirected + non-connectable and + non-scannable legacy + advertising */ + sl_bt_legacy_advertiser_connectable = 0x2, /**< (0x2) Undirected + connectable and scannable + legacy advertising */ + sl_bt_legacy_advertiser_scannable = 0x3 /**< (0x3) Undirected scannable + and non-connectable legacy + advertising */ +} sl_bt_legacy_advertiser_connection_mode_t; + +/** + * @brief These values define the available connection modes of directed legacy + * advertising. + */ +typedef enum +{ + sl_bt_legacy_advertiser_high_duty_directed_connectable = 0x1, /**< (0x1) High + duty cycle + directed + connectable + legacy + advertising */ + sl_bt_legacy_advertiser_low_duty_directed_connectable = 0x5 /**< (0x5) Low + duty cycle + directed + connectable + legacy + advertising */ +} sl_bt_legacy_advertiser_directed_connection_mode_t; + +/***************************************************************************//** + * + * Set user-defined advertising data packet or scan response packet on an + * advertising set. This overwrites the existing advertising data packet and + * scan response packet on this advertising set regardless of whether the data + * was set for the legacy or extended advertising. Maximum 31 bytes of data can + * be set with this command. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_legacy_advertiser_start. + * + * @param[in] advertising_set Advertising set handle + * @param[in] type Enum @ref sl_bt_advertiser_packet_type_t. The advertising + * packet type + * @param[in] data_len Length of data in @p data + * @param[in] data Data to set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Ask the stack to generate the advertising data packet and scan response + * packet on an advertising set. Alternatively, the user-defined advertising + * data can be set using the @ref sl_bt_legacy_advertiser_set_data command. + * + * This overwrites the existing advertising data packet and scan response packet + * on this advertising set regardless of whether the data was set for the legacy + * or extended advertising. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. To enable advertising mode, use command @ref + * sl_bt_legacy_advertiser_start. + * + * The stack generates the advertising data and scan response packet using the + * following logic. + * 1. Add a flags field to advertising data. + * 2. Add a TX power level field to advertising data if the TX power service + * exists in the local GATT database. + * 3. Add a peripheral connection interval range field to advertising data if + * the GAP peripheral preferred connection parameters characteristic exists + * in the local GATT database. + * 4. Add a list of 16-bit service UUIDs to advertising data if there are one + * or more 16-bit service UUIDs to advertise. The list is complete if all + * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is + * incomplete. + * 5. Add a list of 128-bit service UUIDs to advertising data if there are one + * or more 128-bit service UUIDs to advertise and there is still free space + * for this field. The list is complete if all advertised 128-bit UUIDs are + * in advertising data. Otherwise, the list is incomplete. Note that an + * advertising data packet can contain at most one 128-bit service UUID. + * 6. Try to add the full local name to advertising data if the device is not + * in privacy mode. If the full local name does not fit into the remaining + * free space, the advertised name is a shortened version by cutting off + * the end if the free space has at least 6 bytes. Otherwise, the local + * name is added to scan response data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The + * discovery mode for the Flags data field in the packet. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover); + +/***************************************************************************//** + * + * Start undirected legacy advertising on an advertising set with the specified + * connection mode. Use @ref sl_bt_advertiser_stop to stop the advertising. + * + * Use the @ref sl_bt_legacy_advertiser_set_data or @ref + * sl_bt_legacy_advertiser_generate_data command to set the advertising data + * before calling this command. The advertising data is added into the + * advertising data packet and scan response packet if the connection mode is + * connectable and/or scannable. The data is only added into the advertising + * data packet when the connection mode is non-connectable and non-scannable. + * + * The number of concurrent connectable advertisings is limited by the number of + * connections reserved by the user application (the + * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other + * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This + * command fails with the connection limit exceeded error if it may cause the + * number of connections exceeding the configured value in future. For example, + * only one connectable advertising can be enabled if the device has + * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. + * This limitation does not apply to non-connectable advertising. + * + * This command fails with the invalid parameter error if non-resolvable random + * address is used but the connection mode is @ref + * sl_bt_legacy_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_legacy_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_legacy_advertiser_non_connectable (0x0): Undirected + * non-connectable and non-scannable legacy advertising + * - sl_bt_legacy_advertiser_connectable (0x2): Undirected + * connectable and scannable legacy advertising + * - sl_bt_legacy_advertiser_scannable (0x3): Undirected scannable + * and non-connectable legacy advertising + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, + uint8_t connect); + +/***************************************************************************//** + * + * Start directed legacy advertising on an advertising set with the specified + * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to + * stop the advertising. + * + * Directed legacy advertising does not allow any advertising data. When the + * connection mode is @ref + * sl_bt_legacy_advertiser_high_duty_directed_connectable, the stack defaults + * the advertising duration to 0.64 s if the application has not set the + * parameter. The duration is reduced to 1.28 s if the application has set a + * larger duration value. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if non-resolvable random + * address is set as the advertising address. + * + * Event @ref sl_bt_evt_connection_opened will be received when the target + * device opens a connection to the advertiser on this advertising set. As a + * result, the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising + * stops and no Bluetooth connection is opened to it. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref + * sl_bt_legacy_advertiser_directed_connection_mode_t. Connection mode. + * Values: + * - sl_bt_legacy_advertiser_high_duty_directed_connectable (0x1): + * High duty cycle directed connectable legacy advertising + * - sl_bt_legacy_advertiser_low_duty_directed_connectable (0x5): Low + * duty cycle directed connectable legacy advertising + * @param[in] peer_addr Address of the peer target device the advertising is + * directed to + * @param[in] peer_addr_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Peer target device address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + bd_addr peer_addr, + uint8_t peer_addr_type); + +/** @} */ // end addtogroup sl_bt_legacy_advertiser + +/** + * @addtogroup sl_bt_extended_advertiser Extended Advertiser + * @{ + * + * @brief Extended Advertiser + * + * The commands and events in this class are related to extended advertising + * functionalities in GAP peripheral and broadcaster roles. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_extended_advertiser_set_phy_id 0x00570020 +#define sl_bt_cmd_extended_advertiser_set_data_id 0x01570020 +#define sl_bt_cmd_extended_advertiser_set_long_data_id 0x02570020 +#define sl_bt_cmd_extended_advertiser_generate_data_id 0x03570020 +#define sl_bt_cmd_extended_advertiser_start_id 0x04570020 +#define sl_bt_cmd_extended_advertiser_start_directed_id 0x05570020 +#define sl_bt_rsp_extended_advertiser_set_phy_id 0x00570020 +#define sl_bt_rsp_extended_advertiser_set_data_id 0x01570020 +#define sl_bt_rsp_extended_advertiser_set_long_data_id 0x02570020 +#define sl_bt_rsp_extended_advertiser_generate_data_id 0x03570020 +#define sl_bt_rsp_extended_advertiser_start_id 0x04570020 +#define sl_bt_rsp_extended_advertiser_start_directed_id 0x05570020 + +/** + * @brief These values define the available connection modes in extended + * advertising. + */ +typedef enum +{ + sl_bt_extended_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable + and non-scannable + extended advertising */ + sl_bt_extended_advertiser_scannable = 0x3, /**< (0x3) Scannable extended + advertising */ + sl_bt_extended_advertiser_connectable = 0x4 /**< (0x4) Connectable + extended advertising */ +} sl_bt_extended_advertiser_connection_mode_t; + +/** + * @addtogroup sl_bt_extended_advertiser_flags Extended Advertising Configuration Flags + * @{ + * + * This enum defines configuration flags for the extended advertising. + */ + +/** Omit advertiser's address from all PDUs (anonymous advertising). The + * advertising cannot be connectable or scannable if this flag is set. */ +#define SL_BT_EXTENDED_ADVERTISER_ANONYMOUS_ADVERTISING 0x1 + +/** Include the TX power in advertising packets. */ +#define SL_BT_EXTENDED_ADVERTISER_INCLUDE_TX_POWER 0x2 + +/** @} */ // end Extended Advertising Configuration Flags + +/***************************************************************************//** + * + * Set the primary and secondary advertising PHYs used for extended and periodic + * advertising on an advertising set. This setting will take effect next time + * extended or periodic advertising is enabled. When advertising on the LE Coded + * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is + * returned if a PHY value is invalid or the device does not support a given + * PHY. + * + * @param[in] advertising_set Advertising set handle + * @param[in] primary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the primary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * @param[in] secondary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the secondary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy); + +/***************************************************************************//** + * + * Set user-defined data for extended advertising. This overwrites the existing + * advertising data packet and scan response packet on this advertising set + * regardless of whether the data was set for the legacy or extended + * advertising. Maximum 191 bytes of data can be set for connectable extended + * advertising. Maximum 253 bytes of data can be set for non-connectable + * extended advertising. For setting longer advertising data, use command @ref + * sl_bt_extended_advertiser_set_long_data. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_extended_advertiser_start. + * + * The invalid parameter error is returned if the data is too long to fit into a + * single advertisement. + * + * @param[in] advertising_set Advertising set handle + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set long user-defined data for extended advertising. This overwrites the + * existing advertising data packet and scan response packet on this advertising + * set regardless of whether the data was set for the legacy or extended + * advertising. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. When this command is called, + * the data in the system data buffer is extracted as the advertising data. The + * buffer will be emptied after this command regardless of the completion + * status. + * + * Maximum 191 bytes of data can be set for connectable extended advertising. + * Maximum 1650 bytes of data can be set for non-connectable extended + * advertising. Advertising parameters may limit the amount of data that can be + * sent in a single advertisement. See @ref sl_bt_extended_advertiser_set_data + * for more details. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set); + +/***************************************************************************//** + * + * Ask the stack to generate the extended advertising data on an advertising + * set. Alternatively, user-defined advertising data can be set using the @ref + * sl_bt_extended_advertiser_set_data command. + * + * This overwrites the existing advertising data packet and scan response packet + * on this advertising set regardless of whether the data was set for the legacy + * or extended advertising. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. To enable advertising mode, use command @ref + * sl_bt_extended_advertiser_start. + * + * See @ref sl_bt_legacy_advertiser_generate_data for the advertising data + * generation logic. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The + * discovery mode for the Flags data field in the packet. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover); + +/***************************************************************************//** + * + * Start undirected extended advertising on an advertising set with the + * specified connection mode. Use @ref sl_bt_advertiser_stop to stop the + * advertising. + * + * Use the @ref sl_bt_extended_advertiser_set_data or @ref + * sl_bt_extended_advertiser_generate_data command to set the advertising data + * before calling this command. Advertising data is added into the scan response + * packet if the connection mode is scannable. Otherwise, data is in the + * advertising data packet. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if the advertising uses a + * non-resolvable random address but the connection mode is @ref + * sl_bt_extended_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable + * and non-scannable extended advertising + * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended + * advertising + * - sl_bt_extended_advertiser_connectable (0x4): Connectable + * extended advertising + * @param[in] flags Additional extended advertising options. Value: 0 or bitmask + * of @ref sl_bt_extended_advertiser_flags + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and advertising has stopped on an advertising set. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, + uint8_t connect, + uint32_t flags); + +/***************************************************************************//** + * + * Start directed extended advertising on an advertising set with the specified + * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to + * stop the advertising. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if the advertising uses a + * non-resolvable random address but the connection mode is @ref + * sl_bt_extended_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when the target + * device opens a connection to the advertiser on this advertising set. As a + * result, the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising + * stops and no Bluetooth connection is opened to it. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable + * and non-scannable extended advertising + * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended + * advertising + * - sl_bt_extended_advertiser_connectable (0x4): Connectable + * extended advertising + * @param[in] flags Additional extended advertising options. Value: 0 or bitmask + * of @ref sl_bt_extended_advertiser_flags + * @param[in] peer_addr Address of the peer target device the advertising is + * directed to + * @param[in] peer_addr_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Peer target device address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + uint32_t flags, + bd_addr peer_addr, + uint8_t peer_addr_type); + +/** @} */ // end addtogroup sl_bt_extended_advertiser + +/** + * @addtogroup sl_bt_periodic_advertiser Periodic Advertiser + * @{ + * + * @brief Periodic Advertiser + * + * Provides support for advertising with periodic advertising trains that do not + * have subevents or response slots. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_periodic_advertiser_set_data_id 0x00580020 +#define sl_bt_cmd_periodic_advertiser_set_long_data_id 0x01580020 +#define sl_bt_cmd_periodic_advertiser_start_id 0x02580020 +#define sl_bt_cmd_periodic_advertiser_stop_id 0x03580020 +#define sl_bt_rsp_periodic_advertiser_set_data_id 0x00580020 +#define sl_bt_rsp_periodic_advertiser_set_long_data_id 0x01580020 +#define sl_bt_rsp_periodic_advertiser_start_id 0x02580020 +#define sl_bt_rsp_periodic_advertiser_stop_id 0x03580020 + +/** + * @addtogroup sl_bt_periodic_advertiser_flags Periodic Advertising Configuration Flags + * @{ + * + * Defines configuration flags for periodic advertising. + */ + +/** Include the TX power in advertising packets. */ +#define SL_BT_PERIODIC_ADVERTISER_INCLUDE_TX_POWER 0x1 + +/** Automatically start the extended advertising on the advertising set. The + * advertising will be started in non-connectable and non-scannable mode. */ +#define SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING 0x2 + +/** @} */ // end Periodic Advertising Configuration Flags + +/** + * @cond RESTRICTED + * + * @addtogroup sl_bt_evt_periodic_advertiser_status sl_bt_evt_periodic_advertiser_status + * @{ + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * @brief This event indicates a status update in the periodic advertising. + */ + +/** @brief Identifier of the status event */ +#define sl_bt_evt_periodic_advertiser_status_id 0x005800a0 + +/***************************************************************************//** + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * @brief Data structure of the status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_advertiser_status_s +{ + uint8_t advertising_set; /**< The advertising set handle */ + uint32_t status; /**< Reserved for future */ +}); + +typedef struct sl_bt_evt_periodic_advertiser_status_s sl_bt_evt_periodic_advertiser_status_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_advertiser_status +/** @endcond */ // end restricted event + +/***************************************************************************//** + * + * Set the data for periodic advertising on an advertising set. Maximum 254 + * bytes of data can be set with this command. For setting longer advertising + * data, use command @ref sl_bt_periodic_advertiser_set_long_data. + * + * If the periodic advertising is currently enabled, the new advertising data + * will be used immediately. Periodic advertising can be enabled using the + * command @ref sl_bt_periodic_advertiser_start. + * + * The invalid parameter error will be returned if the data is too long to fit + * into the advertisement. + * + * @param[in] advertising_set Advertising set handle + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set data for periodic advertising on an advertising set. Data currently in + * the system data buffer will be extracted as the advertising data. The buffer + * will be emptied after this command regardless of the completion status. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. + * + * Maximum 1650 bytes of data can be set for periodic advertising. Advertising + * parameters may limit the amount of data that can be sent. + * + * See @ref sl_bt_periodic_advertiser_set_data for more details. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set); + +/***************************************************************************//** + * + * Start periodic advertising on an advertising set. + * + * According to the Bluetooth Core specification, periodic advertising PDUs + * cannot be transmitted until at least one extended advertising event has been + * completed. If the application needs exact control over the extended + * advertising data and parameters, use the @ref sl_bt_advertiser class to + * configure the parameters of the advertising set and the @ref + * sl_bt_extended_advertiser class to set or generate the desired extended + * advertising data payload. If the application does not configure the + * parameters or set the data, the default parameters and empty advertising data + * are used for the extended advertising. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p + * flags, the stack will automatically start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. The application may stop the automatically started extended + * advertising using the @ref sl_bt_advertiser_stop command. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in + * @p flags, the stack will momentarily start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. Unless the application starts extended advertising before + * the first extended advertising event has completed, the stack will + * automatically stop the momentary extended advertising after the first + * extended advertising event. + * + * Periodic advertising PDUs are transmitted on the secondary PHY configured for + * the advertising set with the @ref sl_bt_extended_advertiser_set_phy command. + * + * Use @ref sl_bt_periodic_advertiser_stop command to stop the periodic + * advertising. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask + * of @ref sl_bt_periodic_advertiser_flags + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags); + +/***************************************************************************//** + * + * Stop the periodic advertising on an advertising set. Counterpart to @ref + * sl_bt_periodic_advertiser_start. + * + * This command does not affect the enable state of the legacy or extended + * advertising on the advertising set, i.e., the legacy or extended advertising + * is not stopped.. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_periodic_advertiser + +/** + * @addtogroup sl_bt_scanner Scanner + * @{ + * + * @brief Scanner + * + * This is the scanning feature that is brought in when the application includes + * a software component for the scanning functionality. The functionality + * differences are listed below for various component inclusion scenario: + * - The bluetooth_feature_scanner component is included but neither + * bluetooth_feature_legacy_scanner nor bluetooth_feature_extended_scanner + * is included: + * - The scanner can scan advertising devices that use legacy or extended + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_scan_report event is used to report the + * received advertisements. + * + * - The bluetooth_feature_legacy_scanner component is included but the + * bluetooth_feature_extended_scanner is not: + * - The scanner can only scan advertising devices that use legacy + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used + * to report the received advertisements. + * + * - The bluetooth_feature_extended_scanner component is included: + * - The scanner can scan advertising devices that use legacy or extended + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used + * to report the received advertisements that use legacy advertising + * PDUs, and the @ref sl_bt_evt_scanner_extended_advertisement_report + * event is used to report the received advertisements that use extended + * advertising PDUs. + * + * - Either the bluetooth_feature_legacy_scanner or + * bluetooth_feature_extended_scanner component is included: + * - The @ref sl_bt_scanner_set_timing and @ref sl_bt_scanner_set_mode + * commands are not available to use. They are superseded by the @ref + * sl_bt_scanner_set_parameters command. + * - Calling a superseded command receives SL_STATUS_NOT_SUPPORTED error + * code. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_scanner_set_parameters_id 0x06050020 +#define sl_bt_cmd_scanner_set_parameters_and_filter_id 0x07050020 +#define sl_bt_cmd_scanner_stop_id 0x05050020 +#define sl_bt_cmd_scanner_set_timing_id 0x01050020 +#define sl_bt_cmd_scanner_set_mode_id 0x02050020 +#define sl_bt_cmd_scanner_start_id 0x03050020 +#define sl_bt_rsp_scanner_set_parameters_id 0x06050020 +#define sl_bt_rsp_scanner_set_parameters_and_filter_id 0x07050020 +#define sl_bt_rsp_scanner_stop_id 0x05050020 +#define sl_bt_rsp_scanner_set_timing_id 0x01050020 +#define sl_bt_rsp_scanner_set_mode_id 0x02050020 +#define sl_bt_rsp_scanner_start_id 0x03050020 + +/** + * @brief These values indicate which Bluetooth discovery mode to use when + * scanning for advertising devices. + */ +typedef enum +{ + sl_bt_scanner_discover_limited = 0x0, /**< (0x0) Discover only limited + discoverable devices. */ + sl_bt_scanner_discover_generic = 0x1, /**< (0x1) Discover limited and + general discoverable devices. */ + sl_bt_scanner_discover_observation = 0x2 /**< (0x2) Discover + non-discoverable, limited and + general discoverable devices. */ +} sl_bt_scanner_discover_mode_t; + +/** + * @brief The scanning modes. + */ +typedef enum +{ + sl_bt_scanner_scan_mode_passive = 0x0, /**< (0x0) Passive scanning mode where + the device only listens to + advertising packets and does not + transmit packets */ + sl_bt_scanner_scan_mode_active = 0x1 /**< (0x1) Active scanning mode where + the device sends out a scan + request packet upon receiving a + scannable advertising packet from + a remote device and listens to the + scan response packet from the + remote device */ +} sl_bt_scanner_scan_mode_t; + +/** + * @brief The enum defines the scanning PHYs. + */ +typedef enum +{ + sl_bt_scanner_scan_phy_1m = 0x1, /**< (0x1) Initiate the scanning on + the 1M PHY */ + sl_bt_scanner_scan_phy_coded = 0x4, /**< (0x4) Initiate the scanning on + the Coded PHY */ + sl_bt_scanner_scan_phy_1m_and_coded = 0x5 /**< (0x5) Simultaneous scanning by + initiating the scanning on the + 1M and Coded PHY alternatively */ +} sl_bt_scanner_scan_phy_t; + +/** + * @brief Defines the data completeness status types of an advertisement + * reported by the scanner. + */ +typedef enum +{ + sl_bt_scanner_data_status_complete = 0x0, /**< (0x0) All data of the + advertisement has been + reported. */ + sl_bt_scanner_data_status_incomplete_more = 0x1, /**< (0x1) Data of the + advertisement is + incomplete in this + event, and more data + will come in new + events. */ + sl_bt_scanner_data_status_incomplete_nomore = 0x2 /**< (0x2) Data of the + advertisement is + incomplete in this + event, but no more + data will come, i.e., + the data of the + advertisement is + truncated. */ +} sl_bt_scanner_data_status_t; + +/** + * @brief The scanning filter policy setting determines which advertisements and + * scan responses are delivered to the application when scanning. See the + * Bluetooth Core specification Volume 6, Part B, Section 4.3.3 "Scanning filter + * policy" for a detailed description of this setting. + * + * Note that some filter policies require the application to include additional + * Bluetooth feature components. Filter policies that use the Filter Accept List + * require that the application has included the bluetooth_feature_accept_list + * component. Filter policies that require the Bluetooth controller to resolve a + * Resolvable Private Address require that the application has included the + * bluetooth_feature_resolving_list component. + */ +typedef enum +{ + sl_bt_scanner_filter_policy_basic_unfiltered = 0x0, /**< (0x0) Advertising + and scan response + PDUs are processed + from all devices. + For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + a Resolvable + Private Address + that is resolved + to the local + device by the + Bluetooth + controller. */ + sl_bt_scanner_filter_policy_basic_filtered = 0x1, /**< (0x1) Advertising + and scan response + PDUs are processed + only from devices + that the + application has + added to the + Filter Accept + List. For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + a Resolvable + Private Address + that is resolved + to the local + device by the + Bluetooth + controller. */ + sl_bt_scanner_filter_policy_extended_unfiltered = 0x2, /**< (0x2) Advertising + and scan response + PDUs are processed + from all devices. + For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + any Resolvable + Private Address. */ + sl_bt_scanner_filter_policy_extended_filtered = 0x3 /**< (0x3) Advertising + and scan response + PDUs are processed + only from devices + that the + application has + added to the + Filter Accept + List. For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + any Resolvable + Private Address. */ +} sl_bt_scanner_filter_policy_t; + +/** + * @addtogroup sl_bt_scanner_event_flag Event Type Flags of Advertisement Reports + * @{ + * + * Defines the event type flags of the advertisement packets the scanner + * reports. An advertisement packet could have multiple applicable flags. + */ + +/** A connectable advertising data packet */ +#define SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE 0x1 + +/** A scannable advertising data packet */ +#define SL_BT_SCANNER_EVENT_FLAG_SCANNABLE 0x2 + +/** Directed advertising */ +#define SL_BT_SCANNER_EVENT_FLAG_DIRECTED 0x4 + +/** A scan response packet that can be received in active scan mode only */ +#define SL_BT_SCANNER_EVENT_FLAG_SCAN_RESPONSE 0x8 + +/** @} */ // end Event Type Flags of Advertisement Reports + +/** + * @addtogroup sl_bt_evt_scanner_legacy_advertisement_report sl_bt_evt_scanner_legacy_advertisement_report + * @{ + * @brief Reports an advertising data or scan response packet from an + * advertising device that uses legacy advertising PDUs. + * + * This event is used to report advertisements only if the application includes + * the bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component + * + * Otherwise, the @ref sl_bt_evt_scanner_scan_report event is used for + * maintaining the backwards compatibility. + */ + +/** @brief Identifier of the legacy_advertisement_report event */ +#define sl_bt_evt_scanner_legacy_advertisement_report_id 0x000500a0 + +/***************************************************************************//** + * @brief Data structure of the legacy_advertisement_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_legacy_advertisement_report_s +{ + uint8_t event_flags; /**< The event type flag(s) in the + advertisement packet. Value: One or more + flags defined in @ref + sl_bt_scanner_event_flag */ + bd_addr address; /**< Advertiser address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the + local device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last + packet was received */ + bd_addr target_address; /**< The target address if the advertisement + is from directed advertising, otherwise + ignored */ + uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + The target address type if the + advertisement is from directed + advertising, otherwise ignored. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + the following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + enum @ref sl_bt_gap_address_type_t + values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8array data; /**< Advertising or scan response data. Ignore + if this is directed advertising. */ +}); + +typedef struct sl_bt_evt_scanner_legacy_advertisement_report_s sl_bt_evt_scanner_legacy_advertisement_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_legacy_advertisement_report + +/** + * @addtogroup sl_bt_evt_scanner_extended_advertisement_report sl_bt_evt_scanner_extended_advertisement_report + * @{ + * @brief Reports an advertising or scan response packet from an advertising + * device that uses extended advertising PDUs + * + * Multiple events may be reported for single advertisement train. + * + * This event is used to report advertisements only if the application includes + * the bluetooth_feature_extended_scanner component. Otherwise, the @ref + * sl_bt_evt_scanner_scan_report event is used for maintaining the backwards + * compatibility. + */ + +/** @brief Identifier of the extended_advertisement_report event */ +#define sl_bt_evt_scanner_extended_advertisement_report_id 0x020500a0 + +/***************************************************************************//** + * @brief Data structure of the extended_advertisement_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_extended_advertisement_report_s +{ + uint8_t event_flags; /**< The event type flag(s) in the + advertisement packet. Value: One or more + flags defined in @ref + sl_bt_scanner_event_flag */ + bd_addr address; /**< Advertiser address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the + local device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last + packet was received */ + bd_addr target_address; /**< The target address if this is directed + advertising, otherwise ignored */ + uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + The target address type if the + advertisement is from directed + advertising, otherwise ignored. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + the following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + enum @ref sl_bt_gap_address_type_t + values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_sid; /**< Advertising set identifier */ + uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on + which advertising packets are transmitted + on the primary advertising channel + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on + which advertising packets are transmitted + on the secondary advertising channel + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + int8_t tx_power; /**< TX power value in the received packet + header. Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + uint16_t periodic_interval; /**< The periodic advertising interval. Value + 0 indicates no periodic advertising. + Otherwise, + - Range: 0x06 to 0xFFFF + - Unit: 1.25 ms + - Time range: 7.5 ms to 81.92 s */ + uint8_t data_completeness; /**< Enum @ref sl_bt_scanner_data_status_t. + The data completeness status. Values: + - sl_bt_scanner_data_status_complete + (0x0): All data of the + advertisement has been reported. + - sl_bt_scanner_data_status_incomplete_more + (0x1): Data of the advertisement + is incomplete in this event, and more + data will come in new events. + - sl_bt_scanner_data_status_incomplete_nomore + (0x2): Data of the advertisement + is incomplete in this event, but no + more data will come, i.e., the data + of the advertisement is truncated. */ + uint8_t counter; /**< The monotonically increasing counter as + the sequence number of the event. This + counter is specific to @ref + sl_bt_evt_scanner_extended_advertisement_report_id. + It can be used to detect if one more @ref + sl_bt_evt_scanner_extended_advertisement_report + events were dropped due to temporarily + out of resources or other reasons. Ignore + this field if event loss is not a + concern. */ + uint8array data; /**< Advertising or scan response data */ +}); + +typedef struct sl_bt_evt_scanner_extended_advertisement_report_s sl_bt_evt_scanner_extended_advertisement_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_extended_advertisement_report + +/** + * @addtogroup sl_bt_evt_scanner_scan_report sl_bt_evt_scanner_scan_report + * @{ + * @brief Deprecated and replaced by new @ref + * sl_bt_evt_scanner_legacy_advertisement_report and @ref + * sl_bt_evt_scanner_extended_advertisement_report events + * + * To use these new events, the application needs to include the + * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component. + * + * Reports an advertising or scan response packet from an advertising device + * that uses legacy or extended advertising PDUs. + */ + +/** @brief Identifier of the scan_report event */ +#define sl_bt_evt_scanner_scan_report_id 0x010500a0 + +/***************************************************************************//** + * @brief Data structure of the scan_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_scan_report_s +{ + uint8_t packet_type; /**< Bits 0..2 : advertising packet type + - 000 : Connectable scannable + undirected advertising + - 001 : Connectable undirected + advertising + - 010 : Scannable undirected + advertising + - 011 : Non-connectable + non-scannable undirected advertising + - 100 : Scan Response. Note that + this is received only if the device is + in active scan mode. + + Bits 3..4 : Reserved for future + + Bits 5..6 : data completeness + - 00: Complete + - 01: Incomplete, more data to + come in new events + - 10: Incomplete, data truncated, + no more to come + + Bit 7 : legacy or extended + advertising + - 0: Legacy advertising PDUs used + - 1: Extended advertising PDUs + used */ + bd_addr address; /**< Bluetooth address of the remote device */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the local + device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which + advertising packets are transmitted on the + primary advertising channel. Ignore this + field if the report is for a legacy + advertising PDU. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_coded (0x4): Coded + PHY, 125k (S=8) or 500k (S=2) */ + uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which + advertising packets are transmitted on the + secondary advertising channel. Ignore this + field if the report is for a legacy + advertising PDU. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded + PHY, 125k (S=8) or 500k (S=2) */ + uint8_t adv_sid; /**< Advertising set identifier */ + int8_t tx_power; /**< TX power value in the received packet + header. Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last packet + was received */ + uint16_t periodic_interval; /**< The periodic advertising interval. Value 0 + indicates no periodic advertising. + Otherwise, + - Range: 0x06 to 0xFFFF + - Unit: 1.25 ms + - Time range: 7.5 ms to 81.92 s */ + uint8array data; /**< Advertising or scan response data */ +}); + +typedef struct sl_bt_evt_scanner_scan_report_s sl_bt_evt_scanner_scan_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_scan_report + +/***************************************************************************//** + * + * Set scan parameters for subsequent scanning operations. If the device is + * currently scanning, new parameters will take effect when scanning is + * restarted. + * + * This command sets the scanning filter policy to the default value @ref + * sl_bt_scanner_filter_policy_basic_unfiltered. Use the command @ref + * sl_bt_scanner_set_parameters_and_filter to set a specific scanning filter + * policy. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * Passive or active scan. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * @param[in] interval @parblock + * The time interval when the device starts its last scan until it begins the + * subsequent scan. In other words, how often to scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] window @parblock + * The scan window, i.e., the duration of the scan, which must be less than or + * equal to the @p interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * Note that the packet reception is aborted if it's started just before the + * scan window ends. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, + uint16_t interval, + uint16_t window); + +/***************************************************************************//** + * + * Set scan parameters and the scanning filter policy for subsequent scanning + * operations. If the device is currently scanning, new parameters will take + * effect when scanning is restarted. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * Passive or active scan. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * @param[in] interval @parblock + * The time interval when the device starts its last scan until it begins the + * subsequent scan. In other words, how often to scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] window @parblock + * The scan window, i.e., the duration of the scan, which must be less than or + * equal to the @p interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * Note that the packet reception is aborted if it's started just before the + * scan window ends. + * @endparblock + * @param[in] flags No flags are currently defined. Set this parameter to 0. + * @param[in] filter_policy @parblock + * Enum @ref sl_bt_scanner_filter_policy_t. + * + * The scanning filter policy to use when scanning is started. The filter + * policy determines which advertisements and scan responses are delivered to + * the application. Values: + * - sl_bt_scanner_filter_policy_basic_unfiltered (0x0): Advertising + * and scan response PDUs are processed from all devices. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be a Resolvable Private Address that is + * resolved to the local device by the Bluetooth controller. + * - sl_bt_scanner_filter_policy_basic_filtered (0x1): Advertising + * and scan response PDUs are processed only from devices that the + * application has added to the Filter Accept List. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be a Resolvable Private Address that is + * resolved to the local device by the Bluetooth controller. + * - sl_bt_scanner_filter_policy_extended_unfiltered (0x2): + * Advertising and scan response PDUs are processed from all devices. For + * directed advertising, the target address must additionally match the + * identity address of the local device or be any Resolvable Private + * Address. + * - sl_bt_scanner_filter_policy_extended_filtered (0x3): Advertising + * and scan response PDUs are processed only from devices that the + * application has added to the Filter Accept List. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be any Resolvable Private Address. + * + * Default value: @ref sl_bt_scanner_filter_policy_basic_unfiltered + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, + uint16_t interval, + uint16_t window, + uint32_t flags, + uint8_t filter_policy); + +/***************************************************************************//** + * + * Stop scanning for advertising devices. For more information about the + * discovery, see the @ref sl_bt_scanner_start command. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_stop(); + +/***************************************************************************//** + * + * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters + * command. + * + * Set the scanning timing parameters on the specified PHY(s). If the device is + * currently scanning, new parameters will take effect when scanning is + * restarted. + * + * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the + * setting is set for. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs + * @param[in] scan_interval @parblock + * Scan interval is defined as the time interval when the device starts its + * last scan until it begins the subsequent scan. In other words, how often to + * scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case-dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] scan_window @parblock + * Scan window defines the duration of the scan which must be less than or + * equal to the @p scan_interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms Note that the packet reception is aborted if it's + * started just before the scan window ends. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, + uint16_t scan_interval, + uint16_t scan_window); + +/***************************************************************************//** + * + * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters + * command. + * + * Set the scan mode on the specified PHY(s). If the device is currently + * scanning, new parameters will take effect when scanning is restarted. + * + * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the + * setting is set for. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs + * @param[in] scan_mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * The scan mode. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode); + +/***************************************************************************//** + * + * Start the GAP discovery procedure to scan for advertising devices that use + * legacy or extended advertising PDUs. To cancel an ongoing discovery + * procedure, use the @ref sl_bt_scanner_stop command. + * + * The invalid parameter error will be returned if the value of scanning PHYs is + * invalid or the device does not support a PHY. + * + * Received advertising packets are not filtered in any way, so multiple events + * will be received for every advertising device in range. + * + * @param[in] scanning_phy @parblock + * Enum @ref sl_bt_scanner_scan_phy_t. + * + * The scanning PHY(s). + * + * In simultaneous scanning, the stack alternates the scanning on two PHYs by + * switching the PHY at every scan interval. When a timing parameter is set + * differently on 1M and Coded PHY, the stack chooses the most relaxed value + * for both PHYs during simultaneous scanning, i.e., the largest scan interval + * or the smallest scan window. If one PHY is set to passive scanning and the + * other to active scanning, passive scanning is chosen for simultaneous + * scanning. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): Initiate the scanning on the 1M + * PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Initiate the scanning on the + * Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): Simultaneous scanning + * by initiating the scanning on the 1M and Coded PHY alternatively + * @endparblock + * @param[in] discover_mode Enum @ref sl_bt_scanner_discover_mode_t. Bluetooth + * discovery Mode. Values: + * - sl_bt_scanner_discover_limited (0x0): Discover only limited + * discoverable devices. + * - sl_bt_scanner_discover_generic (0x1): Discover limited and + * general discoverable devices. + * - sl_bt_scanner_discover_observation (0x2): Discover + * non-discoverable, limited and general discoverable devices. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_scanner_scan_report - This event is triggered for + * reporting a received advertisement if the application includes the + * bluetooth_feature_scanner component but does not include any other + * scanner component. + * - @ref sl_bt_evt_scanner_legacy_advertisement_report - This event is + * triggered for reporting a received advertisement that uses legacy + * advertising PDUs if the application includes the + * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component. + * - @ref sl_bt_evt_scanner_extended_advertisement_report - This event is + * triggered for reporting a received advertisement that uses extended + * advertising PDUs if the application includes the + * bluetooth_feature_extended_scanner component. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode); + +/** @} */ // end addtogroup sl_bt_scanner + +/** + * @addtogroup sl_bt_sync Synchronization + * @{ + * + * @brief Synchronization + * + * Provides the base functionality of periodic advertising synchronization. Use + * bluetooth_feature_sync_scanner and/or bluetooth_feature_past_receiver + * components to include the synchronization mechanisms that the application + * requires. Use bluetooth_feature_periodic_sync to include support for trains + * that do not have subevents or response slots, and/or + * bluetooth_feature_pawr_sync to include support for Periodic Advertising with + * Responses (PAwR) trains. + * + * Some functionality in this class is considered deprecated and has been + * superseded by new classes. When one or more of + * bluetooth_feature_sync_scanner, bluetooth_feature_periodic_sync, or + * bluetooth_feature_pawr_sync components is included by the application, + * commands that have been superseded by the new classes are no longer available + * for use in the @ref sl_bt_sync class. Calling them will receive + * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: + * - @ref sl_bt_sync_set_parameters + * - @ref sl_bt_sync_open + * + * See the command descriptions for the replacements. + * + * Events that are deprecated and superseded by the new classes are no longer + * triggered by the @ref sl_bt_sync class if any of the new classes are included + * in the application. See event descriptions for the replacements. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_set_parameters_id 0x02420020 +#define sl_bt_cmd_sync_open_id 0x00420020 +#define sl_bt_cmd_sync_set_reporting_mode_id 0x03420020 +#define sl_bt_cmd_sync_update_sync_parameters_id 0x04420020 +#define sl_bt_cmd_sync_close_id 0x01420020 +#define sl_bt_rsp_sync_set_parameters_id 0x02420020 +#define sl_bt_rsp_sync_open_id 0x00420020 +#define sl_bt_rsp_sync_set_reporting_mode_id 0x03420020 +#define sl_bt_rsp_sync_update_sync_parameters_id 0x04420020 +#define sl_bt_rsp_sync_close_id 0x01420020 + +/** + * @brief Specifies the mode for periodic advertising reports. + */ +typedef enum +{ + sl_bt_sync_report_none = 0x0, /**< (0x0) Data received in periodic advertising + trains is not reported to the application. */ + sl_bt_sync_report_all = 0x1 /**< (0x1) Data received in periodic advertising + trains is reported to the application. */ +} sl_bt_sync_reporting_mode_t; + +/** + * @brief These values indicate the advertiser clock accuracy in a periodic + * advertising synchronization. + */ +typedef enum +{ + sl_bt_sync_clock_accuracy_500 = 0x1f4, /**< (0x1f4) Clock accuracy 500 ppm */ + sl_bt_sync_clock_accuracy_250 = 0xfa, /**< (0xfa) Clock accuracy 250 ppm */ + sl_bt_sync_clock_accuracy_150 = 0x96, /**< (0x96) Clock accuracy 150 ppm */ + sl_bt_sync_clock_accuracy_100 = 0x64, /**< (0x64) Clock accuracy 100 ppm */ + sl_bt_sync_clock_accuracy_75 = 0x4b, /**< (0x4b) Clock accuracy 75 ppm */ + sl_bt_sync_clock_accuracy_50 = 0x32, /**< (0x32) Clock accuracy 50 ppm */ + sl_bt_sync_clock_accuracy_30 = 0x1e, /**< (0x1e) Clock accuracy 30 ppm */ + sl_bt_sync_clock_accuracy_20 = 0x14 /**< (0x14) Clock accuracy 20 ppm */ +} sl_bt_sync_advertiser_clock_accuracy_t; + +/** + * @addtogroup sl_bt_evt_sync_opened sl_bt_evt_sync_opened + * @{ + * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_opened + * for periodic advertising trains that do not have subevents or response slots, + * and with @ref sl_bt_evt_pawr_sync_opened for Periodic Advertising with + * Responses (PAwR) trains. + * + * Indicates that a periodic advertising synchronization has been opened. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_sync_opened_id 0x004200a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_opened_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_sync_opened_s sl_bt_evt_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_opened + +/** + * @addtogroup sl_bt_evt_sync_transfer_received sl_bt_evt_sync_transfer_received + * @{ + * @brief Deprecated and replaced by @ref + * sl_bt_evt_periodic_sync_transfer_received for periodic advertising trains + * that do not have subevents or response slots responses, and with @ref + * sl_bt_evt_pawr_sync_transfer_received for Periodic Advertising with Responses + * (PAwR) trains. + * + * Indicates that synchronization information for a periodic advertising train + * has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_sync_transfer_received_id 0x034200a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was established. + Other values indicate that the sync failed to + get established. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_sync_transfer_received_s sl_bt_evt_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_sync_data sl_bt_evt_sync_data + * @{ + * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_report. + * + * Reports a received periodic advertisement packet. + */ + +/** @brief Identifier of the data event */ +#define sl_bt_evt_sync_data_id 0x024200a0 + +/***************************************************************************//** + * @brief Data structure of the data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_data_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the latest + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no more + to come */ + uint8array data; /**< Periodic advertising data */ +}); + +typedef struct sl_bt_evt_sync_data_s sl_bt_evt_sync_data_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_data + +/** + * @addtogroup sl_bt_evt_sync_closed sl_bt_evt_sync_closed + * @{ + * @brief Indicates that periodic advertising synchronization was lost or a + * synchronization establishment procedure was canceled + * + * The synchronization establishment procedure can be canceled explicitly by the + * application by issuing command @ref sl_bt_sync_close, or internally due to + * synchronization failing. Synchronization can fail for example due to + * incompatible sync CTE type. + */ + +/** @brief Identifier of the closed event */ +#define sl_bt_evt_sync_closed_id 0x014200a0 + +/***************************************************************************//** + * @brief Data structure of the closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_closed_s +{ + uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ +}); + +typedef struct sl_bt_evt_sync_closed_s sl_bt_evt_sync_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_closed + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_sync_scanner_set_sync_parameters. + * + * Configure periodic advertiser synchronization parameters. The specified + * parameters take effect immediately for all advertisers that have not already + * established synchronization. + * + * The application should determine skip and timeout values based on the + * periodic advertising interval provided by the advertiser. Ensure that you use + * a long enough timeout to allow multiple receives. If @p skip and @p timeout + * are used, select appropriate values so that they allow a few receiving + * attempts. Periodic advertising intervals are reported in event @ref + * sl_bt_evt_scanner_scan_report. + * + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] flags No flags defined currently + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, + uint16_t timeout, + uint32_t flags); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_sync_scanner_open. + * + * Start establishing synchronization with the specified periodic advertiser in + * parallel with other advertisers given in previous invocations of this + * command. The stack will internally enable scanning when needed so that + * synchronizations can occur. The scanning responses from the internal scanning + * are not passed to the application unless the application has also enabled + * scanning. + * + * Advertisers that have not already synced before the invocation of this + * command will be synced using the @p skip and @p timeout values configured in + * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. + * + * @param[in] address Address of the advertiser + * @param[in] address_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Advertiser address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * @param[in] adv_sid Advertising set identifier + * @param[out] sync A handle that will be assigned to the periodic advertising + * synchronization after the synchronization is established. This handle is + * valid only if the result code of this response is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_opened - Triggered after the synchronization is + * established. + * - @ref sl_bt_evt_sync_data - Indicates that a periodic advertisement packet + * is received. + * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising + * synchronization was lost or explicitly closed, or a synchronization + * establishment procedure was canceled. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync); + +/***************************************************************************//** + * + * Set data reporting mode of the periodic advertising synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] reporting_mode Enum @ref sl_bt_sync_reporting_mode_t. Specifies + * the mode for reporting data received in the periodic advertising train. + * Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Update synchronization parameters for a periodic sync that was already + * established. + * + * When a sync is established by scanning (see @ref sl_bt_sync_scanner) or by + * receiving Periodic Advertising Synchronization Transfer (see @ref + * sl_bt_past_receiver), the sync gets the @p skip and @p timeout parameters + * that were configured in the corresponding class. The application can use this + * command @ref sl_bt_sync_update_sync_parameters to update the values of a sync + * that has been established. The application can for example update the values + * to better match the actual interval of the periodic advertising train, or to + * increase the @p skip value to minimize wakeups when power saving is + * prioritized over receiving every periodic advertisement. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, + uint16_t skip, + uint16_t timeout); + +/***************************************************************************//** + * + * Close a periodic advertising synchronization or cancel an ongoing attempt of + * establishing a synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_closed - Triggered after a periodic advertising + * synchronization has been closed or canceled. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_close(uint16_t sync); + +/** @} */ // end addtogroup sl_bt_sync + +/** + * @addtogroup sl_bt_sync_scanner Periodic Advertising Sync Scanner + * @{ + * + * @brief Periodic Advertising Sync Scanner + * + * Synchronize to periodic advertising trains by scanning for extended + * advertisements that provide the synchronization information. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_scanner_set_sync_parameters_id 0x00500020 +#define sl_bt_cmd_sync_scanner_open_id 0x01500020 +#define sl_bt_rsp_sync_scanner_set_sync_parameters_id 0x00500020 +#define sl_bt_rsp_sync_scanner_open_id 0x01500020 + +/***************************************************************************//** + * + * Configure synchronization parameters for synchronizing to periodic + * advertising trains. The specified parameters take effect immediately for all + * periodic advertising trains that have not already established + * synchronization. + * + * The application should determine skip and timeout values based on the + * periodic advertising interval provided by the advertiser. Ensure that you use + * a long enough timeout to allow multiple receives. If @p skip and @p timeout + * are used, select appropriate values so that they allow a few receiving + * attempts. Periodic advertising intervals are reported in @ref + * sl_bt_evt_scanner_scan_report or @ref + * sl_bt_evt_scanner_extended_advertisement_report event. + * + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Start establishing synchronization with the specified periodic advertiser in + * parallel with other advertisers given in previous invocations of this + * command. + * + * If the application has not already started scanning with the @ref + * sl_bt_scanner_start command, the stack will internally enable scanning so + * that synchronizations can occur. The internal scanning uses the PHY that was + * most recently used with @ref sl_bt_scanner_start and the parameters that have + * been configured with @ref sl_bt_scanner_set_timing. The internal scanning is + * automatically stopped when all requested synchronizations have occurred. + * + * The scanning responses from the internal scanning are not passed to the + * application unless the application starts scanning with the @ref + * sl_bt_scanner_start command. If the application starts scanning while + * synchronizations are being established, the scanning PHY and settings set by + * the application take effect immediately and scanning for synchronizations + * continues with the new settings. When the application has started scanning + * with the @ref sl_bt_scanner_start command, scanning continues until the + * application stops scanning with the @ref sl_bt_scanner_stop command. + * + * Advertisers that have not already synced before the invocation of this + * command will be synced using the @p skip and @p timeout values configured in + * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. + * + * @param[in] address Address of the advertiser + * @param[in] address_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Advertiser address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * @param[in] adv_sid Advertising set identifier + * @param[out] sync A handle that will be assigned to the periodic advertising + * synchronization after the synchronization is established. This handle is + * valid only if the result code of this response is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_periodic_sync_opened - Triggered after synchronization is + * established to a periodic advertising train that does not have subevents + * or response slots. + * - @ref sl_bt_evt_pawr_sync_opened - Triggered after synchronization is + * established to a Periodic Advertising with Responses (PAwR) train. + * - @ref sl_bt_evt_periodic_sync_report - Triggered when data for periodic + * advertising train that does not have subevents or response slots is + * received and accepted by the reporting mode currently set to the train. + * - @ref sl_bt_evt_pawr_sync_subevent_report - Triggered when subevent data + * for Periodic Advertising with Responses (PAwR) train is received and + * accepted by the reporting mode currently set to the train. + * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising + * synchronization was lost or explicitly closed, or a synchronization + * establishment procedure was canceled. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_scanner_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync); + +/** @} */ // end addtogroup sl_bt_sync_scanner + +/** + * @addtogroup sl_bt_past_receiver PAST Receiver + * @{ + * + * @brief PAST Receiver + * + * Synchronize to periodic advertising trains by receiving Periodic Advertising + * Synchronization Transfer over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id 0x00510020 +#define sl_bt_cmd_past_receiver_set_sync_receive_parameters_id 0x01510020 +#define sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_id 0x00510020 +#define sl_bt_rsp_past_receiver_set_sync_receive_parameters_id 0x01510020 + +/** + * @brief Specifies the mode for receiving synchronization transfers + */ +typedef enum +{ + sl_bt_past_receiver_mode_ignore = 0x0, /**< (0x0) No attempt is made to + synchronize to a periodic + advertising train for which + the synchronization + information was received. No + event will be triggered + towards the application. */ + sl_bt_past_receiver_mode_synchronize = 0x1 /**< (0x1) Attempt to synchronize + to a periodic advertising + train for which the + synchronization information + was received. When the + information is received, an + event will be triggered to + indicate success or failure + and to provide the + application with the periodic + advertising synchronization + handle. */ +} sl_bt_past_receiver_mode_t; + +/***************************************************************************//** + * + * Set the default parameters for receiving Periodic Advertising Synchronization + * Transfers (PAST) over connections. The default parameters will be in effect + * for all subsequent connections, unless overridden by command @ref + * sl_bt_past_receiver_set_sync_receive_parameters after the connection is + * opened. + * + * This command sets parameters that do not limit the synchronization based on + * the CTE type. If the application includes bluetooth_feature_aoa_receiver or + * bluetooth_feature_aod_receiver component and wants to specify a particular + * CTE limitation, the application should use the command @ref + * sl_bt_cte_receiver_set_default_sync_receive_parameters to set the default + * parameters. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Set the parameters for receiving Periodic Advertising Synchronization + * Transfers (PAST) over the specified connection. The parameters do not affect + * periodic advertising trains that the device has already synchronized to. + * + * This command sets parameters that do not limit the synchronization based on + * the CTE type. If the application includes bluetooth_feature_aoa_receiver or + * bluetooth_feature_aod_receiver component and wants to specify a particular + * CTE limitation, the application should use the command @ref + * sl_bt_cte_receiver_set_sync_receive_parameters to set the parameters. + * + * @param[in] connection Connection handle of the connection used to receive the + * sync transfer + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/** @} */ // end addtogroup sl_bt_past_receiver + +/** + * @addtogroup sl_bt_advertiser_past Advertiser PAST + * @{ + * + * @brief Advertiser PAST + * + * Transfer the synchronization information of a local active periodic + * advertising set to a remote device using Periodic Advertising Synchronization + * Transfer (PAST) over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_advertiser_past_transfer_id 0x00520020 +#define sl_bt_rsp_advertiser_past_transfer_id 0x00520020 + +/***************************************************************************//** + * + * Transfer the synchronization information of an advertising set that is + * actively performing periodic advertising. + * + * @param[in] connection Connection handle of the connection used to transmit + * the sync transfer + * @param[in] service_data A value provided by the application for use by the + * peer device. + * @param[in] advertising_set Handle of the periodic advertising set to transfer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, + uint16_t service_data, + uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_advertiser_past + +/** + * @addtogroup sl_bt_sync_past Sync PAST + * @{ + * + * @brief Sync PAST + * + * Transfer the synchronization information of a synchronized periodic + * advertising train to a remote device using Periodic Advertising + * Synchronization Transfer (PAST) over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_past_transfer_id 0x005b0020 +#define sl_bt_rsp_sync_past_transfer_id 0x005b0020 + +/***************************************************************************//** + * + * Transfer the synchronization information of a periodic advertising train for + * which a sync has been established. + * + * @param[in] connection Connection handle of the connection used to transmit + * the sync transfer + * @param[in] service_data A value provided by the application for use by the + * peer device. + * @param[in] sync Handle of the periodic advertising synchronization to + * transfer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_past_transfer(uint8_t connection, + uint16_t service_data, + uint16_t sync); + +/** @} */ // end addtogroup sl_bt_sync_past + +/** + * @addtogroup sl_bt_periodic_sync Periodic Advertising without responses Synchronization + * @{ + * + * @brief Periodic Advertising without responses Synchronization + * + * Provides events and control for synchronized periodic advertising trains that + * do not have subevents or response slots. Synchronization is achieved by + * scanning (see @ref sl_bt_sync_scanner) or by receiving Periodic Advertising + * Synchronization Transfer (see @ref sl_bt_past_receiver). + */ + +/* Command and Response IDs */ + +/** + * @addtogroup sl_bt_evt_periodic_sync_opened sl_bt_evt_periodic_sync_opened + * @{ + * @brief Indicates that synchronization to a periodic advertising train that + * does not have subevents or response slots has been opened by scanning + * + * See command @ref sl_bt_sync_scanner_open. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_periodic_sync_opened_id 0x005300a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_opened_s +{ + uint16_t sync; /**< Periodic Advertising synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The Periodic Advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_periodic_sync_opened_s sl_bt_evt_periodic_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_opened + +/** + * @addtogroup sl_bt_evt_periodic_sync_transfer_received sl_bt_evt_periodic_sync_transfer_received + * @{ + * @brief Indicates that synchronization information for a periodic advertising + * train that does not have subevents or response slots has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_periodic_sync_transfer_received_id 0x015300a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was established. + Other values indicate that the sync failed to + get established. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_periodic_sync_transfer_received_s sl_bt_evt_periodic_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_periodic_sync_report sl_bt_evt_periodic_sync_report + * @{ + * @brief Reports a periodic advertising packet for periodic advertising train + * that does not have subevents or response slots + */ + +/** @brief Identifier of the report event */ +#define sl_bt_evt_periodic_sync_report_id 0x025300a0 + +/***************************************************************************//** + * @brief Data structure of the report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_report_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the latest + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no more + to come */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_periodic_sync_report event as a + monotonically increasing counter that wraps from + 255 to 0. There is a single counter for this + event type that starts from value 0 when the + Bluetooth stack is started and is never reset + while the stack is running. This counter can be + used to detect if one or more @ref + sl_bt_evt_periodic_sync_report events have been + created by the stack but dropped due to problems + such as temporarily running out of resources + before the event reached the application. */ + uint8array data; /**< Periodic advertising data */ +}); + +typedef struct sl_bt_evt_periodic_sync_report_s sl_bt_evt_periodic_sync_report_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_report + +/** @} */ // end addtogroup sl_bt_periodic_sync + +/** + * @addtogroup sl_bt_pawr_sync Periodic Advertising with responses Synchronization + * @{ + * + * @brief Periodic Advertising with responses Synchronization + * + * Provides events and control for synchronized Periodic Advertising with + * Responses (PAwR) trains. Synchronization is achieved by scanning (see @ref + * sl_bt_sync_scanner) or by receiving Periodic Advertising Synchronization + * Transfer (see @ref sl_bt_past_receiver). + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_pawr_sync_set_sync_subevents_id 0x02540020 +#define sl_bt_cmd_pawr_sync_set_response_data_id 0x03540020 +#define sl_bt_rsp_pawr_sync_set_sync_subevents_id 0x02540020 +#define sl_bt_rsp_pawr_sync_set_response_data_id 0x03540020 + +/** + * @addtogroup sl_bt_evt_pawr_sync_opened sl_bt_evt_pawr_sync_opened + * @{ + * @brief Indicates that synchronization to a Periodic Advertising with + * Responses (PAwR) train has been opened by scanning + * + * See command @ref sl_bt_sync_scanner_open. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_pawr_sync_opened_id 0x005400a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_opened_s +{ + uint16_t sync; /**< PAwR synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser + PHY. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value + in units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. + The advertiser clock accuracy. */ + uint8_t num_subevents; /**< The number of subevents. + - Range: 0x01 to 0x80 */ + uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 + ms. + - Range: 0x06 to 0xFF + - Time range: 7.5 ms to 318.75 ms */ + uint8_t response_slot_delay; /**< Time between the advertising packet in a + subevent and the first response slot. + Value in units of 1.25 ms. + - Range: 0x01 to 0xFE + - Time range: 1.25 ms to 317.5 ms */ + uint8_t response_slot_spacing; /**< Time between response slots. Value in + units of 0.125 ms. + - Range: 0x02 to 0xFF + - Time range: 0.25 ms to 31.875 ms */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_pawr_sync_opened_s sl_bt_evt_pawr_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_opened + +/** + * @addtogroup sl_bt_evt_pawr_sync_transfer_received sl_bt_evt_pawr_sync_transfer_received + * @{ + * @brief Indicates that synchronization information for Periodic Advertising + * with Responses (PAwR) train has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_pawr_sync_transfer_received_id 0x015400a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was + established. Other values indicate that + the sync failed to get established. */ + uint16_t sync; /**< PAwR synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device. */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser + PHY. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value + in units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. + The advertiser clock accuracy. */ + uint8_t num_subevents; /**< The number of subevents. + - Range: 0x01 to 0x80 */ + uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 + ms. + - Range: 0x06 to 0xFF + - Time range: 7.5 ms to 318.75 ms */ + uint8_t response_slot_delay; /**< Time between the advertising packet in a + subevent and the first response slot. + Value in units of 1.25 ms. + - Range: 0x01 to 0xFE + - Time range: 1.25 ms to 317.5 ms */ + uint8_t response_slot_spacing; /**< Time between response slots. Value in + units of 0.125 ms. + - Range: 0x02 to 0xFF + - Time range: 0.25 ms to 31.875 ms */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_pawr_sync_transfer_received_s sl_bt_evt_pawr_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_pawr_sync_subevent_report sl_bt_evt_pawr_sync_subevent_report + * @{ + * @brief Reports that the device's radio has received a periodic advertisement + * in a subevent of an active PAwR train + * + * This event reports also empty advertisements, i.e., advertisements that + * contained no payload data. In this case the @p data parameter has zero + * length. + */ + +/** @brief Identifier of the subevent_report event */ +#define sl_bt_evt_pawr_sync_subevent_report_id 0x025400a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_subevent_report_s +{ + uint16_t sync; /**< PAwR synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) of the + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint16_t event_counter; /**< The value of the periodic advertising event + counter (paEventCounter) of the event in which + the advertisement was received. If the + application responds to this advertisement, use + this field as the value of @p request_event + parameter for the @ref + sl_bt_pawr_sync_set_response_data command. */ + uint8_t subevent; /**< The subevent in which the advertisement was + received. If the application responds to this + advertisement, use this field as the value of + @p request_subevent parameter for the @ref + sl_bt_pawr_sync_set_response_data command. */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no + more to come + - 255: Failed to receive subevent data + in this subevent */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_pawr_sync_subevent_report event as a + monotonically increasing counter that wraps + from 255 to 0. There is a single counter for + this event type that starts from value 0 when + the Bluetooth stack is started and is never + reset while the stack is running. This counter + can be used to detect if one or more @ref + sl_bt_evt_pawr_sync_subevent_report events have + been created by the stack but dropped due to + problems such as temporarily running out of + resources before the event reached the + application. */ + uint8array data; /**< The advertisement data that was received */ +}); + +typedef struct sl_bt_evt_pawr_sync_subevent_report_s sl_bt_evt_pawr_sync_subevent_report_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_subevent_report + +/***************************************************************************//** + * + * Specify the subevents that this device will synchronize to on the specified + * PAwR train. + * + * @param[in] sync PAwR synchronization handle + * @param[in] subevents_len Length of data in @p subevents + * @param[in] subevents Array of subevent indexes to synchronize to + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, + size_t subevents_len, + const uint8_t* subevents); + +/***************************************************************************//** + * + * Set the data to be sent in the specified response slot of a subevent of an + * active PAwR train. + * + * Use this command when the application receives the @ref + * sl_bt_evt_pawr_sync_subevent_report event and the application needs to send a + * response. The application needs to set the response data within the timing + * requirements implied by the parameters of the PAwR train that the device is + * synchronized to. If the response data is set too late, this command will fail + * with result SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT. + * + * @param[in] sync PAwR synchronization handle + * @param[in] request_event The periodic advertising event counter + * (paEventCounter) of the request. Set this parameter to the value of the @p + * event_counter field of the @ref sl_bt_evt_pawr_sync_subevent_report_id + * event that the application is responding to. + * @param[in] request_subevent The subevent of the request. Set this parameter + * to the value of the @p subevent field of the @ref + * sl_bt_evt_pawr_sync_subevent_report_id event that the application is + * responding to. + * @param[in] response_subevent The subevent in which the response is to be sent + * @param[in] response_slot The response slot in which the response is to be + * sent + * @param[in] response_data_len Length of data in @p response_data + * @param[in] response_data Data to be sent in the specified response slot. + * Maximum of 248 bytes of data can be set with this command. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, + uint16_t request_event, + uint8_t request_subevent, + uint8_t response_subevent, + uint8_t response_slot, + size_t response_data_len, + const uint8_t* response_data); + +/** @} */ // end addtogroup sl_bt_pawr_sync + +/** + * @addtogroup sl_bt_pawr_advertiser PAwR Advertiser + * @{ + * + * @brief PAwR Advertiser + * + * Provides support for advertising with Periodic Advertising with Responses + * (PAwR) trains. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_pawr_advertiser_start_id 0x00550020 +#define sl_bt_cmd_pawr_advertiser_set_subevent_data_id 0x01550020 +#define sl_bt_cmd_pawr_advertiser_create_connection_id 0x02550020 +#define sl_bt_cmd_pawr_advertiser_stop_id 0x03550020 +#define sl_bt_rsp_pawr_advertiser_start_id 0x00550020 +#define sl_bt_rsp_pawr_advertiser_set_subevent_data_id 0x01550020 +#define sl_bt_rsp_pawr_advertiser_create_connection_id 0x02550020 +#define sl_bt_rsp_pawr_advertiser_stop_id 0x03550020 + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request sl_bt_evt_pawr_advertiser_subevent_data_request + * @{ + * @brief This event is triggered to indicate that the Bluetooth stack is ready + * to accept data for the specified subevents of the PAwR train. + * + * To ensure effective use of the available memory, applications are encouraged + * to observe these events and set data using @ref + * sl_bt_pawr_advertiser_set_subevent_data for the subevents that are being + * requested and for which the application has data to send + * + * If the application has no data to send, it does not need to call @ref + * sl_bt_pawr_advertiser_set_subevent_data for that subevent. The application + * can attempt to set data for that subevent later when the application has new + * data to send. + */ + +/** @brief Identifier of the subevent_data_request event */ +#define sl_bt_evt_pawr_advertiser_subevent_data_request_id 0x005500a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_data_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_data_request_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle */ + uint8_t subevent_start; /**< The first subevent that data is requested + for */ + uint8_t subevent_data_count; /**< The number of subevents that data is + requested for */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_subevent_data_request_s sl_bt_evt_pawr_advertiser_subevent_data_request_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed sl_bt_evt_pawr_advertiser_subevent_tx_failed + * @{ + * @brief This event is triggered if subevent data was successfully set using + * @ref sl_bt_pawr_advertiser_set_subevent_data command but the attempt to + * transmit the subevent data has failed + * + * This error is not fatal. The event is provided to the application so that it + * knows not to expect response reports for this subevent and can set subevent + * data again for retransmission without needing to timeout waiting for response + * reports that will not be received because the transmission failed. + */ + +/** @brief Identifier of the subevent_tx_failed event */ +#define sl_bt_evt_pawr_advertiser_subevent_tx_failed_id 0x025500a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_tx_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle for the PAwR + train that failed to transmit subevent data */ + uint8_t subevent; /**< The subevent that failed to transmit subevent + data */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s sl_bt_evt_pawr_advertiser_subevent_tx_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_response_report sl_bt_evt_pawr_advertiser_response_report + * @{ + * @brief Reports the status and data of a used response slot of an active PAwR + * train + * + * The report is given for every response slot that was marked as used in the + * @ref sl_bt_pawr_advertiser_set_subevent_data command. + */ + +/** @brief Identifier of the response_report event */ +#define sl_bt_evt_pawr_advertiser_response_report_id 0x015500a0 + +/***************************************************************************//** + * @brief Data structure of the response_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_response_report_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle */ + uint8_t subevent; /**< The subevent that this report corresponds to */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) of the + received packet. Units: dBm + - Valid value range: -127 to +20 + - Value 127: information unavailable */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint8_t response_slot; /**< The response slot that this report + corresponds to */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come + in new events + - 2: Incomplete, data truncated, no + more to come + - 255: Failed to receive subevent + response in this response slot */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_pawr_advertiser_response_report + event as a monotonically increasing counter + that wraps from 255 to 0. There is a single + counter for this event type that starts from + value 0 when the Bluetooth stack is started + and is never reset while the stack is + running. This counter can be used to detect + if one or more @ref + sl_bt_evt_pawr_advertiser_response_report + events have been created by the stack but + dropped due to problems such as temporarily + running out of resources before the event + reached the application. */ + uint8array data; /**< The response data that was received, if any */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_response_report_s sl_bt_evt_pawr_advertiser_response_report_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_response_report + +/***************************************************************************//** + * + * Start PAwR advertising on the specified advertising set. + * + * According to the Bluetooth Core specification, PAwR advertising PDUs cannot + * be transmitted until at least one extended advertising event has been + * completed. If the application needs exact control over the extended + * advertising data and parameters, use the @ref sl_bt_advertiser class to + * configure the parameters of the advertising set and the @ref + * sl_bt_extended_advertiser class to set or generate the desired extended + * advertising data payload. If the application does not configure the + * parameters or set the data, the default parameters and empty advertising data + * are used for the extended advertising. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p + * flags, the stack will automatically start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. The application may stop the automatically started extended + * advertising using the @ref sl_bt_advertiser_stop command. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in + * @p flags, the stack will momentarily start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. Unless the application starts extended advertising before + * the first extended advertising event has completed, the stack will + * automatically stop the momentary extended advertising after the first + * extended advertising event. + * + * PAwR advertising PDUs are transmitted on the secondary PHY configured for the + * advertising set with the @ref sl_bt_extended_advertiser_set_phy command. + * + * To stop PAwR advertising, use @ref sl_bt_pawr_advertiser_stop command. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask + * of @ref sl_bt_periodic_advertiser_flags + * @param[in] num_subevents The number of subevents. + * - Range: 0x01 to 0x80 + * @param[in] subevent_interval Subevent interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFF + * - Time range: 7.5 ms to 318.75 ms + * @param[in] response_slot_delay Time between the advertising packet in a + * subevent and the first response slot. Value in units of 1.25 ms. + * - Range: 0x01 to 0xFE + * - Time range: 1.25 ms to 317.5 ms + * @param[in] response_slot_spacing Time between response slots. Value in units + * of 0.125 ms. + * - Range: 0x02 to 0xFF + * - Time range: 0.25 ms to 31.875 ms + * @param[in] response_slots Number of subevent response slots. + * - Range: 0x01 to 0xFF + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags, + uint8_t num_subevents, + uint8_t subevent_interval, + uint8_t response_slot_delay, + uint8_t response_slot_spacing, + uint8_t response_slots); + +/***************************************************************************//** + * + * Set data to be sent in the specified subevent of an active PAwR train. Data + * is transmitted only once and is discarded after it has been transmitted. + * + * Data given to this command is passed to the Bluetooth controller, which will + * queue data and transmit it at the correct time. The application may always + * opportunistically try to queue more data with this command, but the + * controller may reject data and return an error if the queuing capacity is + * exceeded. In this case, the Bluetooth stack will trigger the @ref + * sl_bt_evt_pawr_advertiser_subevent_data_request event later when the + * controller is ready to accept more data. + * + * To ensure effective use of the available memory, applications are encouraged + * to observe the @ref sl_bt_evt_pawr_advertiser_subevent_data_request events + * and set data for the subevents that are being requested and for which the + * application has data to send. Applications should also note that PAwR is an + * unreliable transport and cannot guarantee delivery. If reliability is + * required, the application must implement an acknowledgment mechanism using + * response slots of the PAwR train and set subevent data again for a + * re-transmission if it was not successfully delivered. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] subevent The subevent in which the data is to be sent + * @param[in] response_slot_start The first response slot to be used in this + * subevent + * @param[in] response_slot_count The number of response slots to be used + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be sent in the specified subevent + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_pawr_advertiser_subevent_data_request - This event is + * triggered when the Bluetooth stack is ready to accept more subevent data. + * - @ref sl_bt_evt_pawr_advertiser_subevent_tx_failed - This event is + * triggered if transmitting the subevent data has failed. + * - @ref sl_bt_evt_pawr_advertiser_response_report - If the subevent data was + * successfully transmitted, this event is triggered for each response slot + * that was marked as used in this subevent. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, + uint8_t subevent, + uint8_t response_slot_start, + uint8_t response_slot_count, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Initiate a connection request to a device that is synchronized to the + * specified active PAwR train. The connection is established on the secondary + * PHY configured for the advertising set with the @ref + * sl_bt_extended_advertiser_set_phy command. The connection uses the parameters + * configured with command @ref sl_bt_connection_set_default_parameters. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] subevent The subevent in which the connection request is to be + * sent + * @param[in] address Address of the device to connect to + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device to connect to. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @param[out] connection Handle that will be assigned to the connection after + * the connection is established. This handle is valid only if the result code + * of this command is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed - This event is triggered if the + * connection failed to be created. + * - @ref sl_bt_evt_connection_opened - This event is triggered after the + * connection is opened and indicates whether the devices are already bonded + * and the role of the device in this connection. + * - @ref sl_bt_evt_connection_parameters - This event indicates the + * connection parameters and security mode of the connection. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, + uint8_t subevent, + bd_addr address, + uint8_t address_type, + uint8_t *connection); + +/***************************************************************************//** + * + * Stop PAwR advertising on an advertising set. Counterpart to @ref + * sl_bt_pawr_advertiser_start. + * + * This command does not affect the enable state of the advertising set, i.e., + * legacy or extended advertising is not stopped. + * + * @param[in] advertising_set The PAwR advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_pawr_advertiser + +/** + * @addtogroup sl_bt_connection Connection + * @{ + * + * @brief Connection + * + * The commands and events in this class are related to managing connection + * establishment, parameter setting, and disconnection procedures. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_connection_set_default_parameters_id 0x00060020 +#define sl_bt_cmd_connection_set_default_preferred_phy_id 0x01060020 +#define sl_bt_cmd_connection_set_default_data_length_id 0x10060020 +#define sl_bt_cmd_connection_open_id 0x04060020 +#define sl_bt_cmd_connection_set_parameters_id 0x06060020 +#define sl_bt_cmd_connection_set_preferred_phy_id 0x08060020 +#define sl_bt_cmd_connection_disable_slave_latency_id 0x03060020 +#define sl_bt_cmd_connection_get_median_rssi_id 0x15060020 +#define sl_bt_cmd_connection_read_channel_map_id 0x07060020 +#define sl_bt_cmd_connection_set_power_reporting_id 0x09060020 +#define sl_bt_cmd_connection_set_remote_power_reporting_id 0x0a060020 +#define sl_bt_cmd_connection_get_tx_power_id 0x0b060020 +#define sl_bt_cmd_connection_get_remote_tx_power_id 0x0c060020 +#define sl_bt_cmd_connection_set_tx_power_id 0x12060020 +#define sl_bt_cmd_connection_read_remote_used_features_id 0x0d060020 +#define sl_bt_cmd_connection_get_security_status_id 0x0e060020 +#define sl_bt_cmd_connection_set_data_length_id 0x11060020 +#define sl_bt_cmd_connection_read_statistics_id 0x13060020 +#define sl_bt_cmd_connection_get_scheduling_details_id 0x14060020 +#define sl_bt_cmd_connection_close_id 0x05060020 +#define sl_bt_cmd_connection_forcefully_close_id 0x0f060020 +#define sl_bt_cmd_connection_get_rssi_id 0x02060020 +#define sl_bt_rsp_connection_set_default_parameters_id 0x00060020 +#define sl_bt_rsp_connection_set_default_preferred_phy_id 0x01060020 +#define sl_bt_rsp_connection_set_default_data_length_id 0x10060020 +#define sl_bt_rsp_connection_open_id 0x04060020 +#define sl_bt_rsp_connection_set_parameters_id 0x06060020 +#define sl_bt_rsp_connection_set_preferred_phy_id 0x08060020 +#define sl_bt_rsp_connection_disable_slave_latency_id 0x03060020 +#define sl_bt_rsp_connection_get_median_rssi_id 0x15060020 +#define sl_bt_rsp_connection_read_channel_map_id 0x07060020 +#define sl_bt_rsp_connection_set_power_reporting_id 0x09060020 +#define sl_bt_rsp_connection_set_remote_power_reporting_id 0x0a060020 +#define sl_bt_rsp_connection_get_tx_power_id 0x0b060020 +#define sl_bt_rsp_connection_get_remote_tx_power_id 0x0c060020 +#define sl_bt_rsp_connection_set_tx_power_id 0x12060020 +#define sl_bt_rsp_connection_read_remote_used_features_id 0x0d060020 +#define sl_bt_rsp_connection_get_security_status_id 0x0e060020 +#define sl_bt_rsp_connection_set_data_length_id 0x11060020 +#define sl_bt_rsp_connection_read_statistics_id 0x13060020 +#define sl_bt_rsp_connection_get_scheduling_details_id 0x14060020 +#define sl_bt_rsp_connection_close_id 0x05060020 +#define sl_bt_rsp_connection_forcefully_close_id 0x0f060020 +#define sl_bt_rsp_connection_get_rssi_id 0x02060020 + +/** + * @brief Types of device roles in a Bluetooth connection + */ +typedef enum +{ + sl_bt_connection_role_peripheral = 0x0, /**< (0x0) The Peripheral role */ + sl_bt_connection_role_central = 0x1 /**< (0x1) The Central role */ +} sl_bt_connection_role_t; + +/** + * @brief Indicate the Bluetooth Security Mode. + */ +typedef enum +{ + sl_bt_connection_mode1_level1 = 0x0, /**< (0x0) No security */ + sl_bt_connection_mode1_level2 = 0x1, /**< (0x1) Unauthenticated pairing with + encryption */ + sl_bt_connection_mode1_level3 = 0x2, /**< (0x2) Authenticated pairing with + encryption */ + sl_bt_connection_mode1_level4 = 0x3 /**< (0x3) Authenticated Secure + Connections pairing with encryption + using a 128-bit strength encryption + key */ +} sl_bt_connection_security_t; + +/** + * @brief These values define transmit power reporting modes in LE power + * control. + */ +typedef enum +{ + sl_bt_connection_power_reporting_disable = 0x0, /**< (0x0) Disable transmit + power reporting */ + sl_bt_connection_power_reporting_enable = 0x1 /**< (0x1) Enable transmit + power reporting */ +} sl_bt_connection_power_reporting_mode_t; + +/** + * @brief This enum defines the flag values for a reported transmit power level. + */ +typedef enum +{ + sl_bt_connection_tx_power_flag_none = 0x0, /**< (0x0) No flag is defined for + the reported TX power level */ + sl_bt_connection_tx_power_at_minimum = 0x1, /**< (0x1) Transmit power level is + at minimum level. */ + sl_bt_connection_tx_power_at_maximum = 0x2 /**< (0x2) Transmit power level is + at maximum level. */ +} sl_bt_connection_tx_power_flag_t; + +/** + * @addtogroup sl_bt_connection_rssi_const RSSI Value Constants + * @{ + * + * Constants for RSSI value + */ + +/** RSSI value is unavailable */ +#define SL_BT_CONNECTION_RSSI_UNAVAILABLE 0x7f + +/** @} */ // end RSSI Value Constants + +/** + * @addtogroup sl_bt_connection_tx_power_const Transmit Power Reporting Constants + * @{ + * + * Constants in transmit power reporting + */ + +/** Remote device is not managing power levels. */ +#define SL_BT_CONNECTION_TX_POWER_UNMANAGED 0x7e + +/** Transmit power level is not available. */ +#define SL_BT_CONNECTION_TX_POWER_UNAVAILABLE 0x7f + +/** Change is not available or is out of range. */ +#define SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE 0x7f + +/** @} */ // end Transmit Power Reporting Constants + +/** + * @addtogroup sl_bt_evt_connection_opened sl_bt_evt_connection_opened + * @{ + * @brief Indicates that a new connection was opened + * + * The specific semantics depend on the role of the device: + * - On the central device (parameter @p master set to @ref + * sl_bt_connection_role_central) the event is triggered when the Link Layer + * has sent a connect request to the remote device. + * - On the peripheral device (parameter @p master set to @ref + * sl_bt_connection_role_peripheral) the event is triggered when the Link + * Layer has responded to the connect request of the remote device. + * + * This event does not indicate the connection has been established (i.e., that + * a data packet was received within 6 connection intervals). If the connection + * is not established, an @ref sl_bt_evt_connection_closed event will + * immediately follow. + * + * An open connection can be closed with @ref sl_bt_connection_close command by + * giving the connection handle obtained from this event. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_connection_opened_id 0x000600a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_opened_s +{ + bd_addr address; /**< Remote device address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. Remote device + address type. Values: + - sl_bt_gap_public_address (0x0): Public + device address + - sl_bt_gap_static_address (0x1): Static + device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t master; /**< Enum @ref sl_bt_connection_role_t. The role this + device operates in the connection. Values: + - sl_bt_connection_role_peripheral (0x0): + The Peripheral role + - sl_bt_connection_role_central (0x1): + The Central role */ + uint8_t connection; /**< Handle for new connection */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): No + bonding + - Other: Bonding handle */ + uint8_t advertiser; /**< The local advertising set that this connection was + opened to. Values: + - SL_BT_INVALID_ADVERTISING_SET_HANDLE + (0xff): Invalid value or not applicable. + Ignore this field + - Other: The advertising set handle */ + uint16_t sync; /**< The sync handle if the local device is in the + peripheral-role and the connection was opened via + a Periodic Advertising with Responses (PAwR) train + that the local device has synchronized to. Values: + - SL_BT_INVALID_SYNC_HANDLE (0xffff): The + connection was not opened over a PAwR train + that the local device is synchronized to + - Other: The sync handle for the PAwR + train that was used to open the connection */ +}); + +typedef struct sl_bt_evt_connection_opened_s sl_bt_evt_connection_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_opened + +/** + * @addtogroup sl_bt_evt_connection_parameters sl_bt_evt_connection_parameters + * @{ + * @brief Triggered whenever the connection parameters are changed and at any + * time a connection is established + */ + +/** @brief Identifier of the parameters event */ +#define sl_bt_evt_connection_parameters_id 0x020600a0 + +/***************************************************************************//** + * @brief Data structure of the parameters event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_parameters_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t interval; /**< Connection interval. Time = Value x 1.25 ms */ + uint16_t latency; /**< Peripheral latency (how many connection intervals + the peripheral can skip) */ + uint16_t timeout; /**< Supervision timeout. Time = Value x 10 ms */ + uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection + security mode. Values: + - sl_bt_connection_mode1_level1 (0x0): + No security + - sl_bt_connection_mode1_level2 (0x1): + Unauthenticated pairing with encryption + - sl_bt_connection_mode1_level3 (0x2): + Authenticated pairing with encryption + - sl_bt_connection_mode1_level4 (0x3): + Authenticated Secure Connections pairing with + encryption using a 128-bit strength + encryption key */ + uint16_t txsize; /**< Deprecated and no longer used for + reporting the connection data length update. Use + the event @ref sl_bt_evt_connection_data_length + instead. */ +}); + +typedef struct sl_bt_evt_connection_parameters_s sl_bt_evt_connection_parameters_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_parameters + +/** + * @addtogroup sl_bt_evt_connection_set_parameters_failed sl_bt_evt_connection_set_parameters_failed + * @{ + * @brief Triggered when the peer device rejected an L2CAP connection parameter + * update request as a result of calling command @ref + * sl_bt_connection_set_parameters to change connection parameters on the @ref + * sl_bt_connection_role_peripheral role + */ + +/** @brief Identifier of the set_parameters_failed event */ +#define sl_bt_evt_connection_set_parameters_failed_id 0x100600a0 + +/***************************************************************************//** + * @brief Data structure of the set_parameters_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_set_parameters_failed_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_connection_set_parameters_failed_s sl_bt_evt_connection_set_parameters_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_set_parameters_failed + +/** + * @addtogroup sl_bt_evt_connection_phy_status sl_bt_evt_connection_phy_status + * @{ + * @brief Indicates that PHY update procedure is completed. + */ + +/** @brief Identifier of the phy_status event */ +#define sl_bt_evt_connection_phy_status_id 0x040600a0 + +/***************************************************************************//** + * @brief Data structure of the phy_status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_phy_status_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t phy; /**< Current active PHY. See values from @ref + sl_bt_connection_set_preferred_phy command. */ +}); + +typedef struct sl_bt_evt_connection_phy_status_s sl_bt_evt_connection_phy_status_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_phy_status + +/** + * @addtogroup sl_bt_evt_connection_get_remote_tx_power_completed sl_bt_evt_connection_get_remote_tx_power_completed + * @{ + * @brief Indicates that reading remote transmit power initiated by @ref + * sl_bt_connection_get_remote_tx_power command has completed + */ + +/** @brief Identifier of the get_remote_tx_power_completed event */ +#define sl_bt_evt_connection_get_remote_tx_power_completed_id 0x050600a0 + +/***************************************************************************//** + * @brief Data structure of the get_remote_tx_power_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_get_remote_tx_power_completed_s +{ + uint16_t status; /**< SL_STATUS_OK or another error code indicating the + reading remote transmit power operation failed. */ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY for which + the transmit power is reported. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): + 1M PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): + 2M PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED + (0x7E): Remote device is not managing power + levels on this PHY. + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. + Transmit power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out + of range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_get_remote_tx_power_completed_s sl_bt_evt_connection_get_remote_tx_power_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_get_remote_tx_power_completed + +/** + * @addtogroup sl_bt_evt_connection_tx_power sl_bt_evt_connection_tx_power + * @{ + * @brief Reports a transmit power change on the local device of a connection if + * transmit power reporting has been enabled + * + * Enable or disable transmit power reporting using @ref + * sl_bt_connection_set_power_reporting command. Local transmit power reporting + * is enabled by default for new connections. + * + * When enabled, local transmit power change events may get triggered in the + * following situations: + * - When the connection has just opened and the initial transmit power is set + * - When the application explicitly changes the system TX power using the + * @ref sl_bt_system_set_tx_power command + * - When the bluetooth_feature_power_control component is included and + * enabled in the application and the local transmit power is adjusted by + * the power control feature + * - When the bluetooth_feature_afh component for Adaptive Frequency Hopping + * is included and enabled in the application and the local transmit power + * is adjusted due to changes in the availability of good channels. + */ + +/** @brief Identifier of the tx_power event */ +#define sl_bt_evt_connection_tx_power_id 0x060600a0 + +/***************************************************************************//** + * @brief Data structure of the tx_power event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_tx_power_s +{ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the + transmit power is reported for. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M + PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M + PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit + power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out of + range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_tx_power_s sl_bt_evt_connection_tx_power_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_tx_power + +/** + * @addtogroup sl_bt_evt_connection_remote_tx_power sl_bt_evt_connection_remote_tx_power + * @{ + * @brief Reports a transmit power change of the connection on the remote device + * that supports the LE Power Control for the connection + * + * This event is enabled if reporting the remote transmit power change has been + * enabled with the @ref sl_bt_connection_set_remote_power_reporting command. + */ + +/** @brief Identifier of the remote_tx_power event */ +#define sl_bt_evt_connection_remote_tx_power_id 0x070600a0 + +/***************************************************************************//** + * @brief Data structure of the remote_tx_power event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_remote_tx_power_s +{ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the + transmit power is reported for. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M + PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M + PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED + (0x7E): Remote device is not managing power + levels on this PHY. + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit + power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out of + range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_remote_tx_power_s sl_bt_evt_connection_remote_tx_power_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_remote_tx_power + +/** + * @addtogroup sl_bt_evt_connection_remote_used_features sl_bt_evt_connection_remote_used_features + * @{ + * @brief List of link layer features supported by the remote device. + */ + +/** @brief Identifier of the remote_used_features event */ +#define sl_bt_evt_connection_remote_used_features_id 0x080600a0 + +/***************************************************************************//** + * @brief Data structure of the remote_used_features event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_remote_used_features_s +{ + uint8_t connection; /**< Connection handle */ + uint8array features; /**< This parameter is 8 bytes in little endian format + and contains bit fields describing the supported + link layer features of the remote device. Bit + value 1 means that the feature is supported. + + The bits are explained in Bluetooth specification + Vol 6, Part B, 4.6. */ +}); + +typedef struct sl_bt_evt_connection_remote_used_features_s sl_bt_evt_connection_remote_used_features_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_remote_used_features + +/** + * @addtogroup sl_bt_evt_connection_data_length sl_bt_evt_connection_data_length + * @{ + * @brief Reports a change to the maximum payload length or maximum TX time in + * either direction of a connection. + */ + +/** @brief Identifier of the data_length event */ +#define sl_bt_evt_connection_data_length_id 0x090600a0 + +/***************************************************************************//** + * @brief Data structure of the data_length event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_data_length_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t tx_data_len; /**< The maximum payload octets of a packet that the + local Controller will send */ + uint16_t tx_time_us; /**< The maximum time in microseconds that the local + Controller will take to send a data packet */ + uint16_t rx_data_len; /**< The maximum payload octets of a packet that the + local Controller expects to receive */ + uint16_t rx_time_us; /**< The maximum time in microseconds that the local + Controller expects to take to receive a data packet */ +}); + +typedef struct sl_bt_evt_connection_data_length_s sl_bt_evt_connection_data_length_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_data_length + +/** + * @addtogroup sl_bt_evt_connection_statistics sl_bt_evt_connection_statistics + * @{ + * @brief Provides the connection statistic values when the application includes + * the component bluetooth_feature_connection_statistics + * + * When the component is included by the application, this event is + * automatically triggered to provide the final statistics for the connection + * just before the @ref sl_bt_evt_connection_closed event indicates that a + * connection has been closed. This event is also triggered when the application + * has requested reading the statistics using the command @ref + * sl_bt_connection_read_statistics. + */ + +/** @brief Identifier of the statistics event */ +#define sl_bt_evt_connection_statistics_id 0x0a0600a0 + +/***************************************************************************//** + * @brief Data structure of the statistics event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_statistics_s +{ + uint8_t connection; /**< Handle of the connection */ + int8_t rssi_min; /**< The minimum Received Signal + Strength Indicator (RSSI) + value measured for packets + that have been successfully + received on this connection. + Units: dBm + - Valid value range: -127 to + +20 + - Value 127: information + unavailable */ + int8_t rssi_max; /**< The maximum Received Signal + Strength Indicator (RSSI) + value measured for packets + that have been successfully + received on this connection. + Units: dBm + - Valid value range: -127 to + +20 + - Value 127: information + unavailable */ + uint32_t num_total_connection_events; /**< The total number of connection + events that would have + occurred on this connection if + no packets were lost. This + count therefore includes also + connection events that were + missed due to errors (see @p + num_missed_connection_events). + In the Peripheral device this + count does not include + connection events where the + Peripheral deliberately did + not listen due to Peripheral + latency. */ + uint32_t num_missed_connection_events; /**< The number of connection + events that have been missed + on this connection. This + includes connection events + where the first packet of a + connection event was either + not received at all or was + corrupted so that it was not + recognized as belonging to + this connection. */ + uint32_t num_successful_connection_events; /**< The number of connection + events that have occured on + this connection without + errors. */ + uint32_t num_crc_errors; /**< The number of packets that + have been received on this + connection with a Cyclic + Redundancy Check (CRC) error. */ +}); + +typedef struct sl_bt_evt_connection_statistics_s sl_bt_evt_connection_statistics_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_statistics + +/** + * @addtogroup sl_bt_evt_connection_closed sl_bt_evt_connection_closed + * @{ + * @brief Indicates that a connection was either closed or that no connection + * was established from a high duty cycle directed advertising. + * + * If the application includes the component + * bluetooth_feature_connection_statistics and the connection was successfully + * opened, the event @ref sl_bt_evt_connection_statistics is automatically + * triggered just before the connection closed event to provide the application + * with the final statistic values of the connection. + */ + +/** @brief Identifier of the closed event */ +#define sl_bt_evt_connection_closed_id 0x010600a0 + +/***************************************************************************//** + * @brief Data structure of the closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_closed_s +{ + uint16_t reason; /**< Reason of connection close. + + Error code SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT + indicates that the high duty cycle directed + advertising timed out and no connection was + established. Ignore the value of @p connection in + this case. */ + uint8_t connection; /**< Handle of the closed connection */ +}); + +typedef struct sl_bt_evt_connection_closed_s sl_bt_evt_connection_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_closed + +/** + * @addtogroup sl_bt_evt_connection_rssi sl_bt_evt_connection_rssi + * @{ + * @brief Triggered when a @ref sl_bt_connection_get_rssi command has completed + * + * This event is only used by deprecated @ref sl_bt_connection_get_rssi that + * returns the RSSI value asynchronously. + * + * Use the @ref sl_bt_connection_get_median_rssi command to get the RSSI + * synchronously. + */ + +/** @brief Identifier of the rssi event */ +#define sl_bt_evt_connection_rssi_id 0x030600a0 + +/***************************************************************************//** + * @brief Data structure of the rssi event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_rssi_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t status; /**< Command complete status which is always SL_STATUS_OK */ + int8_t rssi; /**< The median of the last seven measured RSSI values on + the connection. Units: dBm. Range: -127 to +20. */ +}); + +typedef struct sl_bt_evt_connection_rssi_s sl_bt_evt_connection_rssi_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_rssi + +/***************************************************************************//** + * + * Set default Bluetooth connection parameters. The values are valid for all + * subsequent connections initiated by this device. + * + * @p min_ce_length and @p max_ce_length specify the preference of the + * connection event length so that the Link Layer can prioritize tasks + * accordingly in simultaneous connections, or scanning and so on. A connection + * event starts at an anchor point of a connection interval and lasts until the + * lesser of @p max_ce_length and the actual connection interval. Packets that + * do not fit into the connection event will be sent in the next connection + * interval. + * + * To change parameters of an already established connection, use the command + * @ref sl_bt_connection_set_parameters. + * + * @param[in] min_interval @parblock + * Minimum value for the connection event interval. This must be set less than + * or equal to @p max_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * + * Default value: 20 ms + * @endparblock + * @param[in] max_interval @parblock + * Maximum value for the connection event interval. This must be set greater + * than or equal to @p min_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * + * Default value: 50 ms + * @endparblock + * @param[in] latency @parblock + * Peripheral latency, which defines how many connection intervals the + * peripheral can skip if it has no data to send + * - Range: 0x0000 to 0x01f3 + * + * Default value: 0 + * @endparblock + * @param[in] timeout @parblock + * Supervision timeout, which defines the time that the connection is + * maintained although the devices can't communicate at the currently + * configured connection intervals. + * - Range: 0x000a to 0x0c80 + * - Time = Value x 10 ms + * - Time Range: 100 ms to 32 s + * - The value in milliseconds must be larger than (1 + @p latency) * @p + * max_interval * 2, where @p max_interval is given in milliseconds + * + * Set the supervision timeout at a value which allows communication attempts + * over at least a few connection intervals. + * + * Default value: 1000 ms + * @endparblock + * @param[in] min_ce_length @parblock + * Minimum length of the connection event. It must be less than or equal to @p + * max_ce_length. + * + * This value defines the minimum time that should be given to the connection + * event in a situation where other tasks need to run immediately after the + * connection event. When the value is very small, the connection event still + * has at least one TX/RX operation. If this value is increased, more time is + * reserved for the connection event so it can transmit and receive more + * packets in a connection interval. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0x0000 + * @endparblock + * @param[in] max_ce_length @parblock + * Maximum length of the connection event. It must be greater than or equal to + * @p min_ce_length. + * + * This value is used for limiting the connection event length so that a + * connection that has large amounts of data to transmit or receive doesn't + * block other tasks. Limiting the connection event is a hard stop. If there + * is no enough time to send or receive a packet, the connection event will be + * closed. + * + * If the value is set to 0, the connection event still has at least one TX/RX + * operation. This is useful to limit power consumption or leave more time to + * other tasks. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0xffff + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length); + +/***************************************************************************//** + * + * Set default preferred and accepted PHYs. PHY settings will be used for all + * subsequent connections. Non-preferred PHY can also be set if the remote + * device does not accept any of the preferred PHYs. + * + * The parameter @p accepted_phy is used to specify PHYs that the stack can + * accept in a remotely-initiated PHY update request. A PHY update will not + * happen if none of the accepted PHYs are present in the request. + * + * NOTE: 2M and Coded PHYs are not supported by all devices. + * + * @param[in] preferred_phy @parblock + * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (no preference) + * @endparblock + * @param[in] accepted_phy @parblock + * Accepted PHYs in remotely-initiated PHY update request. This parameter is a + * bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (all PHYs accepted) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, + uint8_t accepted_phy); + +/***************************************************************************//** + * + * Set the default preferred maximum TX payload length to be used for new + * connections. + * + * When a connection is open, the maximum TX payload length is 27. Either device + * could initiate a data length update procedure and event @ref + * sl_bt_evt_connection_data_length is generated when the data length has been + * changed on the connection. + * + * @param[in] tx_data_len @parblock + * Preferred maximum payload octets of a packet that the local Controller will + * send + * + * Range: Range: 27 (0x1B) to 251 (0xFB) + * + * Default: 251 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len); + +/***************************************************************************//** + * + * Connect to an advertising device with the specified initiating PHY on which + * connectable advertisements on primary advertising channels are received. The + * Bluetooth stack will enter a state where it continuously scans for the + * connectable advertising packets from the remote device, which matches the + * Bluetooth address given as a parameter. Scan parameters set in @ref + * sl_bt_scanner_set_timing are used in this operation. Upon receiving the + * advertising packet, the module will send a connection request packet to the + * target device to initiate a Bluetooth connection. To cancel an ongoing + * connection process, use @ref sl_bt_connection_close command with the handle + * received in response from this command. + * + * A connection is opened in no-security mode. If the GATT client needs to read + * or write the attributes on GATT server requiring encryption or + * authentication, it must first encrypt the connection using an appropriate + * authentication method. + * + * If a connection can't be established, for example, the remote device has gone + * out of range, has entered into deep sleep, or is not advertising, the stack + * will try to connect forever. In this case, the application will not get an + * event related to the connection request. To recover from this situation, the + * application can implement a timeout and call @ref sl_bt_connection_close to + * cancel the connection request. + * + * This command fails with the connection limit exceeded error if the number of + * connections attempted exceeds the configured MAX_CONNECTIONS value. + * + * This command fails with the invalid parameter error if the initiating PHY + * value is invalid or the device does not support PHY. + * + * Subsequent calls of this command have to wait for the ongoing command to + * complete. A received event @ref sl_bt_evt_connection_opened indicates that + * the connection opened successfully and a received event @ref + * sl_bt_evt_connection_closed indicates that connection failures have occurred. + * + * @param[in] address Address of the device to connect to + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device to connect to. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @param[in] initiating_phy Enum @ref sl_bt_gap_phy_t. The initiating PHY. + * Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] connection Handle that will be assigned to the connection after + * the connection is established. This handle is valid only if the result code + * of this response is 0 (zero). + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_opened - This event is triggered after the + * connection is opened and indicates whether the devices are already bonded + * and the role of the device in this connection. + * - @ref sl_bt_evt_connection_parameters - This event indicates the + * connection parameters and security mode of the connection. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_open(bd_addr address, + uint8_t address_type, + uint8_t initiating_phy, + uint8_t *connection); + +/***************************************************************************//** + * + * Request a change in the connection parameters of a Bluetooth connection. + * - On the central device the HCI LE Connection Update command is used to + * update the parameters. + * - On the peripheral device an L2CAP connection parameter update request is + * sent to the peer device to update the parameters. + * + * @p min_ce_length and @p max_ce_length specify the preference of the + * connection event length so that the Link Layer can prioritize tasks + * accordingly in simultaneous connections, or scanning and so on. A connection + * event starts at an anchor point of a connection interval and lasts until the + * lesser of @p max_ce_length and the actual connection interval. Packets that + * do not fit into the connection event will be sent in the next connection + * interval. + * + * @param[in] connection Connection Handle + * @param[in] min_interval Minimum value for the connection event interval. This + * must be set less than or equal to @p max_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * @param[in] max_interval Maximum value for the connection event interval. This + * must be set greater than or equal to @p min_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * @param[in] latency Peripheral latency, which defines how many connection + * intervals the peripheral can skip if it has no data to send + * - Range: 0x0000 to 0x01f3 + * @param[in] timeout @parblock + * Supervision timeout, which defines the time that the connection is + * maintained although the devices can't communicate at the currently + * configured connection intervals. + * - Range: 0x000a to 0x0c80 + * - Time = Value x 10 ms + * - Time Range: 100 ms to 32 s + * - The value in milliseconds must be larger than (1 + @p latency) * @p + * max_interval * 2, where @p max_interval is given in milliseconds + * + * Set the supervision timeout at a value which allows communication attempts + * over at least a few connection intervals. + * @endparblock + * @param[in] min_ce_length @parblock + * Minimum length of the connection event. It must be less than or equal to @p + * max_ce_length. + * + * This value defines the minimum time that should be given to the connection + * event in a situation where other tasks need to run immediately after the + * connection event. When the value is very small, the connection event still + * has at least one TX/RX operation. If this value is increased, more time is + * reserved for the connection event so it can transmit and receive more + * packets in a connection interval. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0x0000 + * @endparblock + * @param[in] max_ce_length @parblock + * Maximum length of the connection event. It must be greater than or equal to + * @p min_ce_length. + * + * This value is used for limiting the connection event length so that a + * connection that has large amounts of data to transmit or receive doesn't + * block other tasks. Limiting the connection event is a hard stop. If there + * is no enough time to send or receive a packet, the connection event will be + * closed. + * + * If the value is set to 0, the connection event still has at least one TX/RX + * operation. This is useful to limit power consumption or leave more time to + * other tasks. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0xffff + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_parameters - Triggered after new connection + * parameters are applied on the connection. + * - @ref sl_bt_evt_connection_set_parameters_failed - Triggered when the peer + * device rejected an L2CAP connection parameter update request. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_parameters(uint8_t connection, + uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length); + +/***************************************************************************//** + * + * Set preferred and accepted PHYs for a given connection. Event @ref + * sl_bt_evt_connection_phy_status is received when PHY update procedure is + * completed. Non-preferred PHY can also be set if remote device does not accept + * any of the preferred PHYs. + * + * The parameter @p accepted_phy is used for specifying the PHYs that the stack + * can accept in a remote initiated PHY update request. A PHY update will not + * occur if none of the accepted PHYs presents in the request. + * + * NOTE: 2M and Coded PHYs are not supported by all devices. + * + * @param[in] connection Connection handle + * @param[in] preferred_phy @parblock + * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: 125k Coded PHY (S=8) + * - 0x08: 500k Coded PHY (S=2) + * + * Default: 0xff (no preference) + * @endparblock + * @param[in] accepted_phy @parblock + * Accepted PHYs in remotely-initiated PHY update requests. This parameter is + * a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (all PHYs accepted) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_phy_status + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, + uint8_t preferred_phy, + uint8_t accepted_phy); + +/***************************************************************************//** + * + * Temporarily enable or disable peripheral latency. Used only when Bluetooth + * device is acting as a peripheral. When peripheral latency is disabled, the + * peripheral latency connection parameter is not set to 0 but the device will + * wake up on every connection interval to receive and send packets. + * + * @param[in] connection Connection Handle + * @param[in] disable 0 enable, 1 disable peripheral latency. Default: 0 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, + uint8_t disable); + +/***************************************************************************//** + * + * Get the RSSI value measured on a connection. + * + * @param[in] connection Connection handle + * @param[out] rssi The median of the last seven measured RSSI values. Units: + * dBm. Range: -127 to +20. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi); + +/***************************************************************************//** + * + * Read channel map for a specified connection. + * + * @param[in] connection Connection Handle + * @param[in] max_channel_map_size Size of output buffer passed in @p + * channel_map + * @param[out] channel_map_len On return, set to the length of output data + * written to @p channel_map + * @param[out] channel_map @parblock + * This parameter is 5 bytes and contains 37 1-bit fields. + * + * The nth field (in the range 0 to 36) contains the value for the link layer + * channel index n. + * + * - 0: Channel n is unused. + * - 1: Channel n is used. + * + * The most significant bits are reserved for future use. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, + size_t max_channel_map_size, + size_t *channel_map_len, + uint8_t *channel_map); + +/***************************************************************************//** + * + * Enable or disable the transmit power reporting for the local device on a + * connection. When transmit power reporting is enabled, event @ref + * sl_bt_evt_connection_tx_power is generated when transmit power on the local + * device changes. + * + * The command is a built-in feature in the stack and is supported regardless of + * whether the LE Power Control feature is used. By default, power reporting for + * local device is enabled. + * + * @param[in] connection Handle of the connection + * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit + * power reporting mode. Values: + * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit + * power reporting + * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit + * power reporting + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_tx_power + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, + uint8_t mode); + +/***************************************************************************//** + * + * Enable or disable reporting the transmit power change on the remote device. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. + * + * When the remote transmit power reporting is enabled, event @ref + * sl_bt_evt_connection_remote_tx_power is generated when transmit power on the + * remote device changes. + * + * By default, power reporting for the remote device is disabled. + * + * @param[in] connection Handle of the connection + * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit + * power reporting mode. Values: + * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit + * power reporting + * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit + * power reporting + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_remote_tx_power + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, + uint8_t mode); + +/***************************************************************************//** + * + * Get the transmit power of the local device on the given connection and PHY. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. + * + * @param[in] connection Handle of the connection + * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: + * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY + * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY + * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) + * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) + * @param[out] current_level The current transmit power level of the PHY on the + * connection. Values: + * - Range -127 to 20: The transmit power level in dBm + * - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE (0x7F): Transmit + * power level is not available. + * @param[out] max_level The maximum transmit power level of the PHY on the + * connection. Values: Range -127 to +20 in dBm. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, + uint8_t phy, + int8_t *current_level, + int8_t *max_level); + +/***************************************************************************//** + * + * Get the transmit power of the remote device on the given connection and PHY. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. Transmit + * power levels are returned in event @ref + * sl_bt_evt_connection_get_remote_tx_power_completed after the operation + * completed. + * + * @param[in] connection Handle of the connection + * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: + * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY + * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY + * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) + * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) + * + * @return SL_STATUS_OK if the command is accepted. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_get_remote_tx_power_completed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, + uint8_t phy); + +/***************************************************************************//** + * + * Set the transmit power of a connection. The application must include + * component bluetooth_feature_user_power_control in order to use this command + * for controlling the transmit power of the connection at application level. + * This command is unavailable if the standard Bluetooth feature LE power + * control (component bluetooth_feature_power_control) is used by the + * application. + * + * The actual selected power level is returned from this command. The value may + * be different than the requested one because of Bluetooth feature restrictions + * or radio characteristics. + * + * @param[in] connection The connection handle + * @param[in] tx_power The requested TX power. Unit: 0.1 dBm + * @param[out] tx_power_out The selected TX power. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, + int16_t tx_power, + int16_t *tx_power_out); + +/***************************************************************************//** + * + * Read link layer features supported by the remote device. + * + * @param[in] connection Connection Handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_remote_used_features + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection); + +/***************************************************************************//** + * + * Get the security status of the connection. + * + * @param[in] connection Connection handle + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size The size of encryption key + * @param[out] bonding_handle Bonding handle. Values: + * - SL_BT_INVALID_BONDING_HANDLE (0xff): No bonding + * - Other: Bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_security_status(uint8_t connection, + uint8_t *security_mode, + uint8_t *key_size, + uint8_t *bonding_handle); + +/***************************************************************************//** + * + * Request to update the maximum TX payload length and maximum packet TX time of + * a Bluetooth connection. + * + * Event @ref sl_bt_evt_connection_data_length is generated when the data length + * has been changed on the connection. + * + * @param[in] connection Connection handle + * @param[in] tx_data_len @parblock + * Preferred maximum payload octets of a packet that the local Controller will + * send + * + * Range: 27 (0x1B) to 251 (0xFB) + * @endparblock + * @param[in] tx_time_us @parblock + * Preferred maximum TX time in microseconds that the local Controller will + * take to send a packet + * + * Range: 328 (0x0148) to 17040 (0x4290) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_data_length + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_data_length(uint8_t connection, + uint16_t tx_data_len, + uint16_t tx_time_us); + +/***************************************************************************//** + * + * Read the statistic values collected on the specified connection. The + * application must include component bluetooth_feature_connection_statistics in + * order to use this command. If the component is not included in the + * application this command returns the error SL_STATUS_NOT_AVAILABLE. If this + * command is called before the connection has opened, the command returns the + * error SL_STATUS_NOT_READY. + * + * @param[in] connection The connection handle + * @param[in] reset Reset statistics if parameter value is not zero + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_statistics - Triggered to deliver the statistic + * values of the connection at the time the command was issued. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset); + +/***************************************************************************//** + * + * Get parameters and next connection event scheduling details of a connection. + * Returned values from this command provide the necessary information for + * following the packet transmissions of the connection on an external device. + * Note that the stack cannot ensure a determined timing latency from the time + * when issuing this command to the time when another device starts to follow + * the connection, and the stack cannot guarantee that a scheduled connection + * event will always happen. + * + * @param[in] connection Connection handle + * @param[out] access_address Access address of the connection + * @param[out] role Enum @ref sl_bt_connection_role_t. The role the local device + * operates in the connection. Values: + * - sl_bt_connection_role_peripheral (0x0): The Peripheral role + * - sl_bt_connection_role_central (0x1): The Central role + * @param[out] crc_init The CRC initialization value + * @param[out] interval The connection interval. Time = Value x 1.25 ms + * @param[out] supervision_timeout The connection supervision time. Time = Value + * x 10 ms + * @param[out] central_clock_accuracy The central device's clock accuracy index + * value + * @param[out] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central + * device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the + * Peripheral device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] channel_selection_algorithm Enum @ref + * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. + * Values: + * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection + * algorithm #1 + * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection + * algorithm #2 + * @param[out] hop The hop increment when the channel selection algorithm #1 is + * used on the connection. Ignore if @p channel_selection_algorithm indicates + * that the connection uses channel selection algorithm #2. + * @param[out] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Ignore bits 37-39 that are reserved for future use. + * + * A channel is unused when its bit is 0. A channel is used when its bit is 1. + * @endparblock + * @param[out] channel The data channel number that transmissions will use in + * the next connection event + * @param[out] event_counter The event counter of the next connection event + * @param[out] start_time_us Time in microseconds from the PROTIMER tick when + * the next connection event is scheduled to happen + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, + uint32_t *access_address, + uint8_t *role, + uint32_t *crc_init, + uint16_t *interval, + uint16_t *supervision_timeout, + uint8_t *central_clock_accuracy, + uint8_t *central_phy, + uint8_t *peripheral_phy, + uint8_t *channel_selection_algorithm, + uint8_t *hop, + sl_bt_connection_channel_map_t *channel_map, + uint8_t *channel, + uint16_t *event_counter, + uint32_t *start_time_us); + +/***************************************************************************//** + * + * Close a Bluetooth connection gracefully by performing the ACL Termination + * procedure or cancel an ongoing connection establishment process. The + * parameter is a connection handle which is reported in @ref + * sl_bt_evt_connection_opened event or @ref sl_bt_connection_open command + * response. + * + * Disconnecting a connection is an asynchronous operation. The disconnection is + * completed when a @ref sl_bt_evt_connection_closed event for the given + * connection handle is received. To open a new connection to the same remote + * device, wait for the @ref sl_bt_evt_connection_closed event and then initiate + * the connection. + * + * @param[in] connection Handle of the connection to be closed + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_close(uint8_t connection); + +/***************************************************************************//** + * + * Forcefully close a Bluetooth connection without performing the ACL + * Termination procedure. The parameter is a connection handle which is reported + * in @ref sl_bt_evt_connection_opened event or @ref sl_bt_connection_open + * command response. + * + * Closing a connection using this command could result in the observation of + * connection loss or supervision timeout on the remote device. Only use this + * command for special cases, for example, when disconnecting a connection with + * @ref sl_bt_connection_close did not complete in expected time period. + * + * @param[in] connection Handle of the connection to be closed + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_forcefully_close(uint8_t connection); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_connection_get_median_rssi which + * synchronously returns the value. + * + * Get the latest RSSI value of a Bluetooth connection. The RSSI value will be + * reported in a @ref sl_bt_evt_connection_rssi event if the command returns + * SL_STATUS_OK. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_rssi - Triggered when this command has + * completed. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection); + +/** @} */ // end addtogroup sl_bt_connection + +/** + * @addtogroup sl_bt_gatt GATT Client + * @{ + * + * @brief GATT Client + * + * The commands and events in this class are used to browse and manage + * attributes in a remote GATT server. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gatt_set_max_mtu_id 0x00090020 +#define sl_bt_cmd_gatt_discover_primary_services_id 0x01090020 +#define sl_bt_cmd_gatt_discover_primary_services_by_uuid_id 0x02090020 +#define sl_bt_cmd_gatt_find_included_services_id 0x10090020 +#define sl_bt_cmd_gatt_discover_characteristics_id 0x03090020 +#define sl_bt_cmd_gatt_discover_characteristics_by_uuid_id 0x04090020 +#define sl_bt_cmd_gatt_discover_descriptors_id 0x06090020 +#define sl_bt_cmd_gatt_discover_characteristic_descriptors_id 0x14090020 +#define sl_bt_cmd_gatt_set_characteristic_notification_id 0x05090020 +#define sl_bt_cmd_gatt_send_characteristic_confirmation_id 0x0d090020 +#define sl_bt_cmd_gatt_read_characteristic_value_id 0x07090020 +#define sl_bt_cmd_gatt_read_characteristic_value_from_offset_id 0x12090020 +#define sl_bt_cmd_gatt_read_multiple_characteristic_values_id 0x11090020 +#define sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id 0x08090020 +#define sl_bt_cmd_gatt_write_characteristic_value_id 0x09090020 +#define sl_bt_cmd_gatt_write_characteristic_value_without_response_id 0x0a090020 +#define sl_bt_cmd_gatt_prepare_characteristic_value_write_id 0x0b090020 +#define sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 +#define sl_bt_cmd_gatt_execute_characteristic_value_write_id 0x0c090020 +#define sl_bt_cmd_gatt_read_descriptor_value_id 0x0e090020 +#define sl_bt_cmd_gatt_write_descriptor_value_id 0x0f090020 +#define sl_bt_rsp_gatt_set_max_mtu_id 0x00090020 +#define sl_bt_rsp_gatt_discover_primary_services_id 0x01090020 +#define sl_bt_rsp_gatt_discover_primary_services_by_uuid_id 0x02090020 +#define sl_bt_rsp_gatt_find_included_services_id 0x10090020 +#define sl_bt_rsp_gatt_discover_characteristics_id 0x03090020 +#define sl_bt_rsp_gatt_discover_characteristics_by_uuid_id 0x04090020 +#define sl_bt_rsp_gatt_discover_descriptors_id 0x06090020 +#define sl_bt_rsp_gatt_discover_characteristic_descriptors_id 0x14090020 +#define sl_bt_rsp_gatt_set_characteristic_notification_id 0x05090020 +#define sl_bt_rsp_gatt_send_characteristic_confirmation_id 0x0d090020 +#define sl_bt_rsp_gatt_read_characteristic_value_id 0x07090020 +#define sl_bt_rsp_gatt_read_characteristic_value_from_offset_id 0x12090020 +#define sl_bt_rsp_gatt_read_multiple_characteristic_values_id 0x11090020 +#define sl_bt_rsp_gatt_read_characteristic_value_by_uuid_id 0x08090020 +#define sl_bt_rsp_gatt_write_characteristic_value_id 0x09090020 +#define sl_bt_rsp_gatt_write_characteristic_value_without_response_id 0x0a090020 +#define sl_bt_rsp_gatt_prepare_characteristic_value_write_id 0x0b090020 +#define sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 +#define sl_bt_rsp_gatt_execute_characteristic_value_write_id 0x0c090020 +#define sl_bt_rsp_gatt_read_descriptor_value_id 0x0e090020 +#define sl_bt_rsp_gatt_write_descriptor_value_id 0x0f090020 + +/** + * @brief These values indicate which attribute request or response has caused + * the event. + */ +typedef enum +{ + sl_bt_gatt_read_by_type_request = 0x8, /**< (0x8) Read by type request */ + sl_bt_gatt_read_by_type_response = 0x9, /**< (0x9) Read by type response */ + sl_bt_gatt_read_request = 0xa, /**< (0xa) Read request */ + sl_bt_gatt_read_response = 0xb, /**< (0xb) Read response */ + sl_bt_gatt_read_blob_request = 0xc, /**< (0xc) Read blob request */ + sl_bt_gatt_read_blob_response = 0xd, /**< (0xd) Read blob response */ + sl_bt_gatt_read_multiple_request = 0xe, /**< (0xe) Read multiple request */ + sl_bt_gatt_read_multiple_response = 0xf, /**< (0xf) Read multiple response */ + sl_bt_gatt_write_request = 0x12, /**< (0x12) Write request */ + sl_bt_gatt_write_response = 0x13, /**< (0x13) Write response */ + sl_bt_gatt_write_command = 0x52, /**< (0x52) Write command */ + sl_bt_gatt_prepare_write_request = 0x16, /**< (0x16) Prepare write request */ + sl_bt_gatt_prepare_write_response = 0x17, /**< (0x17) Prepare write + response */ + sl_bt_gatt_execute_write_request = 0x18, /**< (0x18) Execute write request */ + sl_bt_gatt_execute_write_response = 0x19, /**< (0x19) Execute write + response */ + sl_bt_gatt_handle_value_notification = 0x1b, /**< (0x1b) Notification */ + sl_bt_gatt_handle_value_indication = 0x1d /**< (0x1d) Indication */ +} sl_bt_gatt_att_opcode_t; + +/** + * @brief These values define whether the client is to receive notifications or + * indications from a remote GATT server. + */ +typedef enum +{ + sl_bt_gatt_disable = 0x0, /**< (0x0) Disable notifications and + indications */ + sl_bt_gatt_notification = 0x1, /**< (0x1) Notification */ + sl_bt_gatt_indication = 0x2 /**< (0x2) Indication */ +} sl_bt_gatt_client_config_flag_t; + +/** + * @brief These values define whether the GATT server is to cancel all queued + * writes or commit all queued writes to a remote database. + */ +typedef enum +{ + sl_bt_gatt_cancel = 0x0, /**< (0x0) Cancel all queued writes */ + sl_bt_gatt_commit = 0x1 /**< (0x1) Commit all queued writes */ +} sl_bt_gatt_execute_write_flag_t; + +/** + * @addtogroup sl_bt_evt_gatt_mtu_exchanged sl_bt_evt_gatt_mtu_exchanged + * @{ + * @brief Indicates that an ATT_MTU exchange procedure is completed + * + * The @p mtu parameter describes new MTU size. MTU size 23 is used before this + * event is received. + */ + +/** @brief Identifier of the mtu_exchanged event */ +#define sl_bt_evt_gatt_mtu_exchanged_id 0x000900a0 + +/***************************************************************************//** + * @brief Data structure of the mtu_exchanged event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_mtu_exchanged_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t mtu; /**< Exchanged ATT_MTU */ +}); + +typedef struct sl_bt_evt_gatt_mtu_exchanged_s sl_bt_evt_gatt_mtu_exchanged_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_mtu_exchanged + +/** + * @addtogroup sl_bt_evt_gatt_service sl_bt_evt_gatt_service + * @{ + * @brief Indicates that a GATT service in the remote GATT database was + * discovered + * + * This event is generated after issuing either the @ref + * sl_bt_gatt_discover_primary_services or @ref + * sl_bt_gatt_discover_primary_services_by_uuid command. + */ + +/** @brief Identifier of the service event */ +#define sl_bt_evt_gatt_service_id 0x010900a0 + +/***************************************************************************//** + * @brief Data structure of the service event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_service_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t service; /**< GATT service handle */ + uint8array uuid; /**< Service UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_service_s sl_bt_evt_gatt_service_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_service + +/** + * @addtogroup sl_bt_evt_gatt_characteristic sl_bt_evt_gatt_characteristic + * @{ + * @brief Indicates that a GATT characteristic in the remote GATT database was + * discovered + * + * This event is generated after issuing either the @ref + * sl_bt_gatt_discover_characteristics or @ref + * sl_bt_gatt_discover_characteristics_by_uuid command. + */ + +/** @brief Identifier of the characteristic event */ +#define sl_bt_evt_gatt_characteristic_id 0x020900a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle */ + uint8_t properties; /**< Characteristic properties */ + uint8array uuid; /**< Characteristic UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_characteristic_s sl_bt_evt_gatt_characteristic_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic + +/** + * @addtogroup sl_bt_evt_gatt_descriptor sl_bt_evt_gatt_descriptor + * @{ + * @brief Indicates that a GATT characteristic descriptor in the remote GATT + * database was discovered + * + * It is generated after issuing the @ref sl_bt_gatt_discover_descriptors or + * @ref sl_bt_gatt_discover_characteristic_descriptors command. + */ + +/** @brief Identifier of the descriptor event */ +#define sl_bt_evt_gatt_descriptor_id 0x030900a0 + +/***************************************************************************//** + * @brief Data structure of the descriptor event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t descriptor; /**< GATT characteristic descriptor handle */ + uint8array uuid; /**< Descriptor UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_descriptor_s sl_bt_evt_gatt_descriptor_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor + +/** + * @addtogroup sl_bt_evt_gatt_characteristic_value sl_bt_evt_gatt_characteristic_value + * @{ + * @brief Indicates that the value of one or several characteristics in the + * remote GATT server was received + * + * It is triggered by several commands: @ref + * sl_bt_gatt_read_characteristic_value, @ref + * sl_bt_gatt_read_characteristic_value_from_offset, @ref + * sl_bt_gatt_read_characteristic_value_by_uuid, @ref + * sl_bt_gatt_read_multiple_characteristic_values; and when the remote GATT + * server sends indications or notifications after enabling notifications with + * @ref sl_bt_gatt_set_characteristic_notification. The parameter @p att_opcode + * indicates which type of GATT transaction triggered this event. In particular, + * if the @p att_opcode type is @ref sl_bt_gatt_handle_value_indication (0x1d), + * the application needs to confirm the indication with @ref + * sl_bt_gatt_send_characteristic_confirmation. + */ + +/** @brief Identifier of the characteristic_value event */ +#define sl_bt_evt_gatt_characteristic_value_id 0x040900a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode, which indicates the GATT transaction + used. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Characteristic value */ +}); + +typedef struct sl_bt_evt_gatt_characteristic_value_s sl_bt_evt_gatt_characteristic_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic_value + +/** + * @addtogroup sl_bt_evt_gatt_descriptor_value sl_bt_evt_gatt_descriptor_value + * @{ + * @brief Indicates that the value of a descriptor in the remote GATT server was + * received + * + * This event is generated by the @ref sl_bt_gatt_read_descriptor_value command. + */ + +/** @brief Identifier of the descriptor_value event */ +#define sl_bt_evt_gatt_descriptor_value_id 0x050900a0 + +/***************************************************************************//** + * @brief Data structure of the descriptor_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t descriptor; /**< GATT characteristic descriptor handle */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Descriptor value */ +}); + +typedef struct sl_bt_evt_gatt_descriptor_value_s sl_bt_evt_gatt_descriptor_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor_value + +/** + * @addtogroup sl_bt_evt_gatt_procedure_completed sl_bt_evt_gatt_procedure_completed + * @{ + * @brief Indicates that the current GATT procedure was completed successfully + * or that it failed with an error + * + * All GATT commands excluding @ref + * sl_bt_gatt_write_characteristic_value_without_response and @ref + * sl_bt_gatt_send_characteristic_confirmation will trigger this event. As a + * result, the application must wait for this event before issuing another GATT + * command (excluding the two aforementioned exceptions). + * + * Note: After a failed GATT procedure with SL_STATUS_TIMEOUT error, + * further GATT transactions over this connection are not allowed by the stack. + */ + +/** @brief Identifier of the procedure_completed event */ +#define sl_bt_evt_gatt_procedure_completed_id 0x060900a0 + +/***************************************************************************//** + * @brief Data structure of the procedure_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_procedure_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t result; /**< SL_STATUS_OK if successful. Error code otherwise. */ +}); + +typedef struct sl_bt_evt_gatt_procedure_completed_s sl_bt_evt_gatt_procedure_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_procedure_completed + +/***************************************************************************//** + * + * Set the maximum size of ATT Message Transfer Units (MTU). Functionality is + * the same as @ref sl_bt_gatt_server_set_max_mtu and this setting applies to + * both GATT client and server. If the given value is too large according to the + * maximum BGAPI payload size, the system will select the maximum possible value + * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT + * client in the stack will automatically send an MTU exchange request after a + * Bluetooth connection has been established. + * + * @param[in] max_mtu @parblock + * Maximum size of Message Transfer Units (MTU) allowed + * - Range: 23 to 250 + * + * Default: 247 + * @endparblock + * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this + * command succeeds + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out); + +/***************************************************************************//** + * + * Discover all primary services of a remote GATT database. This command + * generates a unique gatt_service event for every discovered primary service. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection); + +/***************************************************************************//** + * + * Discover primary services with the specified UUID in a remote GATT database. + * This command generates unique gatt_service event for every discovered primary + * service. Received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that this GATT procedure was successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Service UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Find the services that are included by a service in a remote GATT database. + * This command generates a unique gatt_service event for each included service. + * The received @ref sl_bt_evt_gatt_procedure_completed event indicates that + * this GATT procedure was successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, + uint32_t service); + +/***************************************************************************//** + * + * Discover all characteristics of a GATT service from a remote GATT database. + * This command generates a unique gatt_characteristic event for every + * discovered characteristic. Received @ref sl_bt_evt_gatt_procedure_completed + * event indicates that this GATT procedure was successfully completed or failed + * with an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from + * remote GATT database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, + uint32_t service); + +/***************************************************************************//** + * + * Discover all characteristics of a GATT service in a remote GATT database + * having the specified UUID. This command generates a unique + * gatt_characteristic event for every discovered characteristic having the + * specified UUID. Received @ref sl_bt_evt_gatt_procedure_completed event + * indicates that this GATT procedure was successfully completed or failed with + * an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Characteristic UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from + * remote GATT database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Discover all descriptors in a remote GATT database starting from handle. It + * generates a unique gatt_descriptor event for every discovered descriptor. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, + uint16_t characteristic); + +/***************************************************************************//** + * + * Discover all descriptors of a GATT characteristic in a remote GATT database. + * It generates a unique gatt_descriptor event for every discovered descriptor. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] start GATT characteristic handle. This value is normally received + * from the gatt_characteristic event. + * @param[in] end GATT characteristic handle. This value is normally received + * from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, + uint16_t start, + uint16_t end); + +/***************************************************************************//** + * + * Enable or disable the notifications and indications sent from a remote GATT + * server. This procedure discovers a characteristic client configuration + * descriptor and writes the related configuration flags to a remote GATT + * database. A received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that this GATT procedure was successfully completed or that it failed with an + * error. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] flags Enum @ref sl_bt_gatt_client_config_flag_t. Characteristic + * client configuration flags. Values: + * - sl_bt_gatt_disable (0x0): Disable notifications and indications + * - sl_bt_gatt_notification (0x1): Notification + * - sl_bt_gatt_indication (0x2): Indication + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * - @ref sl_bt_evt_gatt_characteristic_value - If an indication or + * notification has been enabled for a characteristic, this event is + * triggered whenever an indication or notification is sent by the remote + * GATT server. The triggering conditions of the GATT server are defined by + * an upper level, for example by a profile. As a result, it is possible + * that no values are ever received, or that it may take time, depending on + * how the server is configured. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, + uint16_t characteristic, + uint8_t flags); + +/***************************************************************************//** + * + * Send a confirmation to a remote GATT server after receiving a characteristic + * indication. The @ref sl_bt_evt_gatt_characteristic_value event carries the @p + * att_opcode containing @ref sl_bt_gatt_handle_value_indication (0x1d), which + * reveals that an indication has been received and must be confirmed with this + * command. The confirmation needs to be sent within 30 seconds, otherwise + * further GATT transactions are not allowed by the remote side. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection); + +/***************************************************************************//** + * + * Read the value of a characteristic from a remote GATT database. A single @ref + * sl_bt_evt_gatt_characteristic_value is generated if the characteristic value + * fits in one ATT PDU. Otherwise, more than one @ref + * sl_bt_evt_gatt_characteristic_value event is generated because the firmware + * will automatically use the Read Long Characteristic Values procedure. A + * received @ref sl_bt_evt_gatt_procedure_completed event indicates that all + * data was read successfully or that an error response was received. + * + * Note that the GATT client does not verify if the requested attribute is a + * characteristic value. Therefore, before calling this command, ensure that the + * attribute handle is for a characteristic value, for example, by performing + * characteristic discovery. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, + uint16_t characteristic); + +/***************************************************************************//** + * + * Read a partial characteristic value with a specified offset and maximum + * length from a remote GATT database. It is equivalent to @ref + * sl_bt_gatt_read_characteristic_value if both the offset and maximum length + * parameters are 0. A single @ref sl_bt_evt_gatt_characteristic_value event is + * generated if the value to read fits in one ATT PDU. Otherwise, more than one + * @ref sl_bt_evt_gatt_characteristic_value events are generated because the + * firmware will automatically use the Read Long Characteristic Values + * procedure. A received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that all data was read successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] maxlen Maximum bytes to read. If this parameter is 0, all + * characteristic values starting at a given offset will be read. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + uint16_t maxlen); + +/***************************************************************************//** + * + * Read values of multiple characteristics from a remote GATT database at once. + * The GATT server returns values in one ATT PDU as the response. If the total + * set of values is greater than (ATT_MTU - 1) bytes in length, only the first + * (ATT_MTU - 1) bytes are included. A single @ref + * sl_bt_evt_gatt_characteristic_value event is generated, in which the + * characteristic is set to 0 and data in the value parameter is a concatenation + * of characteristic values in the order they were requested. The received @ref + * sl_bt_evt_gatt_procedure_completed event indicates either that this GATT + * procedure was successfully completed or failed with an error. + * + * Use this command only for characteristics values that have a known fixed + * size, except the last one that could have variable length. + * + * When the remote GATT server is from Silicon Labs Bluetooth stack, the server + * returns ATT Invalid PDU (0x04) if this command only reads one characteristic + * value. The server returns ATT Application Error 0x80 if this command reads + * the value of a user-type characteristic. + * + * @param[in] connection Connection handle + * @param[in] characteristic_list_len Length of data in @p characteristic_list + * @param[in] characteristic_list List of uint16 characteristic handles each in + * little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - A concatenation of + * characteristic values in the order they were requested + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was either + * successfully completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, + size_t characteristic_list_len, + const uint8_t* characteristic_list); + +/***************************************************************************//** + * + * Read characteristic values of a service from a remote GATT database by giving + * the UUID of the characteristic and the handle of the service containing this + * characteristic. If multiple characteristic values are received in one ATT + * PDU, one @ref sl_bt_evt_gatt_characteristic_value event is generated for each + * value. If the first characteristic value does not fit in one ATT PDU, the + * firmware automatically uses the Read Long Characteristic Values procedure and + * generate more @ref sl_bt_evt_gatt_characteristic_value events until the value + * has been completely read. A received @ref sl_bt_evt_gatt_procedure_completed + * event indicates that all data was read successfully or that an error response + * was received. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Characteristic UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Write the value of a characteristic in a remote GATT database. If the value + * length is greater than (ATT_MTU - 3) and does not fit in one ATT PDU, "write + * long" GATT procedure is used automatically. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that all data was written + * successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Write the value of a characteristic in a remote GATT server. It does not + * generate an event. All failures on the server are ignored silently. For + * example, if an error is generated in the remote GATT server and the given + * value is not written into the database, no error message will be reported to + * the local GATT client. Note that this command can't be used to write long + * values. At most ATT_MTU - 3 number of bytes can be sent once. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Add a characteristic value to the write queue of a remote GATT server. It can + * be used when long attributes need to be written or a set of values needs to + * be written atomically. At most ATT_MTU - 5 number of bytes can be sent at one + * time. Writes are executed or canceled with the @ref + * sl_bt_gatt_execute_characteristic_value_write command. Whether the writes + * succeed or not is indicated in the response of the @ref + * sl_bt_gatt_execute_characteristic_value_write command. + * + * In all use cases where the amount of data to transfer fits into the BGAPI + * payload, use the command @ref sl_bt_gatt_write_characteristic_value to write + * long values because it transparently performs the prepare_write and + * execute_write commands. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] value_len Length of data in @p value + * @param[in] value Value to write into the specified characteristic of the + * remote GATT database + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Add a characteristic value to the write queue of a remote GATT server and + * verify whether the value was correctly received by the server. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that this GATT procedure + * was successfully completed or failed with an error. Specifically, error code + * 0x0194 (data_corrupted) will be returned if the value received from the GATT + * server's response fails to pass the reliable write verification. At most, + * ATT_MTU - 5 number of bytes can be sent at one time. Writes are executed or + * canceled with the @ref sl_bt_gatt_execute_characteristic_value_write command. + * Whether the writes succeed or not is indicated in the response of the @ref + * sl_bt_gatt_execute_characteristic_value_write command. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] value_len Length of data in @p value + * @param[in] value Value to write into the specified characteristic of the + * remote GATT database + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Commit or cancel previously queued writes to a long characteristic of a + * remote GATT server. Writes are sent to the queue with @ref + * sl_bt_gatt_prepare_characteristic_value_write command. Content, offset, and + * length of queued values are validated by this procedure. A received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that all data was written + * successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] flags Enum @ref sl_bt_gatt_execute_write_flag_t. Execute write + * flag. Values: + * - sl_bt_gatt_cancel (0x0): Cancel all queued writes + * - sl_bt_gatt_commit (0x1): Commit all queued writes + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, + uint8_t flags); + +/***************************************************************************//** + * + * Read the descriptor value of a characteristic in a remote GATT database. A + * single @ref sl_bt_evt_gatt_descriptor_value event is generated if the + * descriptor value fits in one ATT PDU. Otherwise, more than one @ref + * sl_bt_evt_gatt_descriptor_value events are generated because the firmware + * automatically uses the Read Long Characteristic Values procedure. A received + * @ref sl_bt_evt_gatt_procedure_completed event indicates that all data was + * read successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] descriptor GATT characteristic descriptor handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor_value - Descriptor value received from the + * remote GATT server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, + uint16_t descriptor); + +/***************************************************************************//** + * + * Write the value of a characteristic descriptor in a remote GATT database. If + * the value length is greater than ATT_MTU - 3 and does not fit in one ATT PDU, + * "write long" GATT procedure is used automatically. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates either that all data was + * written successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] descriptor GATT characteristic descriptor handle + * @param[in] value_len Length of data in @p value + * @param[in] value Descriptor value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, + uint16_t descriptor, + size_t value_len, + const uint8_t* value); + +/** @} */ // end addtogroup sl_bt_gatt + +/** + * @addtogroup sl_bt_gattdb GATT Database + * @{ + * + * @brief GATT Database + * + * These commands and events are used for managing the local GATT database. + * + * Many commands in this class return the handles of created attributes. These + * handles may change during commit if attributes are not created in the order + * they present in the database. For example, when creating a new service using + * the @ref sl_bt_gattdb_add_service command, the service declaration handle + * returned from this command becomes invalid later when an attribute is added + * or removed in front of this service. If the user requires that the attribute + * handles returned from these commands must remain valid after the database + * update has been committed, attributes must be created in the order they + * present in the database. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gattdb_new_session_id 0x00460020 +#define sl_bt_cmd_gattdb_add_service_id 0x01460020 +#define sl_bt_cmd_gattdb_remove_service_id 0x02460020 +#define sl_bt_cmd_gattdb_add_included_service_id 0x03460020 +#define sl_bt_cmd_gattdb_remove_included_service_id 0x04460020 +#define sl_bt_cmd_gattdb_add_uuid16_characteristic_id 0x05460020 +#define sl_bt_cmd_gattdb_add_uuid128_characteristic_id 0x06460020 +#define sl_bt_cmd_gattdb_remove_characteristic_id 0x07460020 +#define sl_bt_cmd_gattdb_add_uuid16_descriptor_id 0x08460020 +#define sl_bt_cmd_gattdb_add_uuid128_descriptor_id 0x09460020 +#define sl_bt_cmd_gattdb_remove_descriptor_id 0x0a460020 +#define sl_bt_cmd_gattdb_start_service_id 0x0b460020 +#define sl_bt_cmd_gattdb_stop_service_id 0x0c460020 +#define sl_bt_cmd_gattdb_start_characteristic_id 0x0d460020 +#define sl_bt_cmd_gattdb_stop_characteristic_id 0x0e460020 +#define sl_bt_cmd_gattdb_commit_id 0x0f460020 +#define sl_bt_cmd_gattdb_abort_id 0x10460020 +#define sl_bt_rsp_gattdb_new_session_id 0x00460020 +#define sl_bt_rsp_gattdb_add_service_id 0x01460020 +#define sl_bt_rsp_gattdb_remove_service_id 0x02460020 +#define sl_bt_rsp_gattdb_add_included_service_id 0x03460020 +#define sl_bt_rsp_gattdb_remove_included_service_id 0x04460020 +#define sl_bt_rsp_gattdb_add_uuid16_characteristic_id 0x05460020 +#define sl_bt_rsp_gattdb_add_uuid128_characteristic_id 0x06460020 +#define sl_bt_rsp_gattdb_remove_characteristic_id 0x07460020 +#define sl_bt_rsp_gattdb_add_uuid16_descriptor_id 0x08460020 +#define sl_bt_rsp_gattdb_add_uuid128_descriptor_id 0x09460020 +#define sl_bt_rsp_gattdb_remove_descriptor_id 0x0a460020 +#define sl_bt_rsp_gattdb_start_service_id 0x0b460020 +#define sl_bt_rsp_gattdb_stop_service_id 0x0c460020 +#define sl_bt_rsp_gattdb_start_characteristic_id 0x0d460020 +#define sl_bt_rsp_gattdb_stop_characteristic_id 0x0e460020 +#define sl_bt_rsp_gattdb_commit_id 0x0f460020 +#define sl_bt_rsp_gattdb_abort_id 0x10460020 + +/** + * @brief This enum defines GATT service types. + */ +typedef enum +{ + sl_bt_gattdb_primary_service = 0x0, /**< (0x0) Primary service */ + sl_bt_gattdb_secondary_service = 0x1 /**< (0x1) Secondary service */ +} sl_bt_gattdb_service_type_t; + +/** + * @brief This enum defines characteristic and descriptor value types. + */ +typedef enum +{ + sl_bt_gattdb_fixed_length_value = 0x1, /**< (0x1) A fixed-length value + managed by the local GATT + server for responding the read + and write requests of remote + GATT clients */ + sl_bt_gattdb_variable_length_value = 0x2, /**< (0x2) A variable-length value + managed by the local GATT + server for responding the read + and write requests of remote + GATT clients */ + sl_bt_gattdb_user_managed_value = 0x3 /**< (0x3) A value managed by the + user application for responding + the read and write requests of + remote GATT clients. */ +} sl_bt_gattdb_value_type_t; + +/** + * @addtogroup sl_bt_gattdb_service_property_flags GATT Service Property Flags + * @{ + * + * This enum defines GATT service property flags. + */ + +/** The service should be advertised. */ +#define SL_BT_GATTDB_ADVERTISED_SERVICE 0x1 + +/** @} */ // end GATT Service Property Flags + +/** + * @addtogroup sl_bt_gattdb_security_requirements GATT Attribute Security Requirement Flags + * @{ + * + * This enum defines the security requirement flags for GATT characteristic + * value properties. + */ + +/** The read property requires pairing and encrypted connection. */ +#define SL_BT_GATTDB_ENCRYPTED_READ 0x1 + +/** The read property requires bonding and encrypted connection. */ +#define SL_BT_GATTDB_BONDED_READ 0x2 + +/** The read property requires authenticated pairing and encrypted connection. + * */ +#define SL_BT_GATTDB_AUTHENTICATED_READ 0x4 + +/** The write property requires pairing and encrypted connection. */ +#define SL_BT_GATTDB_ENCRYPTED_WRITE 0x8 + +/** The write property requires bonding and encrypted connection. */ +#define SL_BT_GATTDB_BONDED_WRITE 0x10 + +/** The write property requires authenticated pairing and encrypted connection. + * */ +#define SL_BT_GATTDB_AUTHENTICATED_WRITE 0x20 + +/** The notification and indication properties require pairing and encrypted + * connection. */ +#define SL_BT_GATTDB_ENCRYPTED_NOTIFY 0x40 + +/** The notification and indication properties require bonding and encrypted + * connection. */ +#define SL_BT_GATTDB_BONDED_NOTIFY 0x80 + +/** The notification and indication properties require authenticated pairing and + * encrypted connection. */ +#define SL_BT_GATTDB_AUTHENTICATED_NOTIFY 0x100 + +/** @} */ // end GATT Attribute Security Requirement Flags + +/** + * @addtogroup sl_bt_gattdb_flags GATT Database Flags + * @{ + * + * This enum defines the options of GATT attribute management. + */ + +/** Do not automatically create a Client Characteristic Configuration descriptor + * when adding a characteristic that has the notify or indicate property. */ +#define SL_BT_GATTDB_NO_AUTO_CCCD 0x1 + +/** @} */ // end GATT Database Flags + +/** + * @addtogroup sl_bt_gattdb_characteristic_properties GATT Characteristic Property Flags + * @{ + * + * This enum defines the property flags for GATT characteristic values. Lower + * byte is Characteristic Properties and higher byte is Characteristic Extended + * Properties. + */ + +/** A GATT client can read the characteristic value. */ +#define SL_BT_GATTDB_CHARACTERISTIC_READ 0x2 + +/** A GATT client can write the characteristic value without a response. */ +#define SL_BT_GATTDB_CHARACTERISTIC_WRITE_NO_RESPONSE 0x4 + +/** A GATT client can write the characteristic value. */ +#define SL_BT_GATTDB_CHARACTERISTIC_WRITE 0x8 + +/** The characteristic value can be notified without acknowledgment. */ +#define SL_BT_GATTDB_CHARACTERISTIC_NOTIFY 0x10 + +/** The characteristic value can be notified with acknowledgment. */ +#define SL_BT_GATTDB_CHARACTERISTIC_INDICATE 0x20 + +/** The additional characteristic properties are defined. */ +#define SL_BT_GATTDB_CHARACTERISTIC_EXTENDED_PROPS 0x80 + +/** The characteristic value supports reliable write. */ +#define SL_BT_GATTDB_CHARACTERISTIC_RELIABLE_WRITE 0x101 + +/** @} */ // end GATT Characteristic Property Flags + +/** + * @addtogroup sl_bt_gattdb_descriptor_properties GATT Descriptor Property Flags + * @{ + * + * This enum defines the property flags for GATT characteristic descriptors. + */ + +/** A GATT client can read the descriptor value. */ +#define SL_BT_GATTDB_DESCRIPTOR_READ 0x1 + +/** A GATT client can write the descriptor value. */ +#define SL_BT_GATTDB_DESCRIPTOR_WRITE 0x2 + +/** The descriptor is local only and should be invisible to GATT clients. */ +#define SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY 0x200 + +/** @} */ // end GATT Descriptor Property Flags + +/***************************************************************************//** + * + * Start a new GATT database update session. If the operation is successful, the + * Bluetooth stack returns a session ID, with which the GATT database can be + * updated by calling other database management APIs of this class. Changes in + * the database are not immediately saved. Unsaved changes are invisible to a + * connected remote GATT client. + * + * After all changes were performed successfully, commit the changes using the + * @ref sl_bt_gattdb_commit command. The Bluetooth stack will save the changes + * and handle GATT caching as needed. Unsaved database changes can also be + * canceled by calling the @ref sl_bt_gattdb_abort command. In either case, + * after a commit or abort command is called, the current session is closed and + * the session ID becomes invalid. + * + * Only one session is allowed at a time. Error SL_STATUS_ALREADY_EXISTS is + * returned if another session has been started already. + * + * @param[out] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_new_session(uint16_t *session); + +/***************************************************************************//** + * + * Add a service into the local GATT database. When successful, the service is + * appended to the service list and is in stopped state. Use @ref + * sl_bt_gattdb_start_service command to set it visible to remote GATT clients. + * + * You are not allowed to add the Generic Attribute Profile service. If the + * application needs GATT caching, enable the feature in the configuration of + * this component and the GATT server will handle GATT caching according to the + * procedures specified by the Bluetooth core specification. + * + * @param[in] session The database update session ID + * @param[in] type Enum @ref sl_bt_gattdb_service_type_t. The service type. + * Values: + * - sl_bt_gattdb_primary_service (0x0): Primary service + * - sl_bt_gattdb_secondary_service (0x1): Secondary service + * @param[in] property Service properties. Value: 0 or bit flag @ref + * SL_BT_GATTDB_ADVERTISED_SERVICE + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid The service UUID in little endian format + * @param[out] service The service declaration attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_service(uint16_t session, + uint8_t type, + uint8_t property, + size_t uuid_len, + const uint8_t* uuid, + uint16_t *service); + +/***************************************************************************//** + * + * Remove a service and its characteristics from the local GATT database. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Add an included-service attribute to a service. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the included-service attribute is added to + * @param[in] included_service The service declaration attribute handle of the + * service to be included + * @param[out] attribute The included-service attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, + uint16_t service, + uint16_t included_service, + uint16_t *attribute); + +/***************************************************************************//** + * + * Remove an included-service attribute from a service. + * + * @param[in] session The database update session ID + * @param[in] attribute The included-service attribute handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, + uint16_t attribute); + +/***************************************************************************//** + * + * Add a 16-bits UUID characteristic to a service. On success, the + * characteristic is appended to the characteristic list of the service and it + * inherits the started or stopped state of the service. In addition, it can be + * started and stopped separately with the @ref + * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic + * commands. + * + * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the + * stack will automatically add a Client Characteristic Configuration descriptor + * to this characteristic when it has the notify or indicate property. If @ref + * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the + * descriptor separately as needed. + * + * A Characteristic Extended Properties descriptor is automatically added if the + * reliable write property is set. + * + * Use the @ref sl_bt_gattdb_add_uuid128_characteristic command to add a + * 128-bits UUID characteristic. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the characteristic is added to + * @param[in] property Characteristic value properties. Value: bitmask of @ref + * sl_bt_gattdb_characteristic_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the characteristic + * value. + * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. + * @param[in] uuid The 16-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the characteristic value. Ignored if + * @p value_type is @ref sl_bt_gattdb_user_managed_value. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial characteristic value. Length of this value must + * be less than or equal to @p maxlen. Ignored if @p value_type is @ref + * sl_bt_gattdb_user_managed_value. + * @param[out] characteristic The characteristic value attribute handle. This + * handle is ensured valid in current session. It may change after the session + * if attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic); + +/***************************************************************************//** + * + * Add a 128-bits UUID characteristic to a service. When successful, the + * characteristic is appended to the characteristic list of the service and + * inherits the started or stopped state of the service. Additionally, it can be + * started and stopped separately with the @ref + * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic + * commands. + * + * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the + * stack will automatically add a Client Characteristic Configuration descriptor + * to this characteristic when it has the notify or indicate property. If @ref + * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the + * descriptor separately as needed. + * + * A Characteristic Extended Properties descriptor is automatically added if the + * reliable write property is set. + * + * Use the @ref sl_bt_gattdb_add_uuid16_characteristic command to add a 16-bits + * UUID characteristic. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the characteristic is added to + * @param[in] property Characteristic value properties. Value: bitmask of @ref + * sl_bt_gattdb_characteristic_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the characteristic + * value. + * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. + * @param[in] uuid The 128-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the characteristic value. Ignored if + * @p value_type is @ref sl_bt_gattdb_user_managed_value. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial characteristic value. Length of this value must + * be less than or equal to @p maxlen. Ignored if @p value_type is @ref + * sl_bt_gattdb_user_managed_value. + * @param[out] characteristic The characteristic value attribute handle. This + * handle is ensured valid in current session. It may change after the session + * if attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic); + +/***************************************************************************//** + * + * Remove a characteristic and its descriptors from a service. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Add a 16-bits UUID descriptor to a characteristic. When successful, the + * descriptor is appended to the descriptor list of the characteristic and + * inherits the started or stopped state of the characteristic. + * + * This command does not support adding Characteristic Extended Properties + * descriptors. This descriptor is automatically added if the characteristic + * value has the reliable-write property or when a Characteristic User + * Description descriptor is added and the user description has the write + * property. + * + * Use the @ref sl_bt_gattdb_add_uuid128_descriptor command to add a 128-bits + * UUID descriptor. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic the descriptor is added to + * @param[in] property The descriptor properties. Value: bitmask of @ref + * sl_bt_gattdb_descriptor_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the descriptor. + * @param[in] uuid The 16-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Ignored if this is a Client Characteristic Configuration descriptor. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p + * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client + * Characteristic Configuration descriptor. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial descriptor value. Length of this value must be + * less than or equal to @p maxlen. Ingored if value type is @ref + * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic + * Configuration descriptor. + * @param[out] descriptor The descriptor attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor); + +/***************************************************************************//** + * + * Add a 128-bits UUID descriptor to a characteristic. When successful, the + * descriptor is appended to the descriptor list of the characteristic and + * inherits the started or stopped state of the characteristic. + * + * This command does not support adding Characteristic Extended Properties + * descriptors. This descriptor is automatically added if the characteristic + * value has the reliable-write property or when a Characteristic User + * Description descriptor is added and the user description has the write + * property. + * + * Use the @ref sl_bt_gattdb_add_uuid16_descriptor command to add a 16-bits UUID + * descriptor. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic the descriptor is added to + * @param[in] property Bitmask of characteristic descriptor properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the descriptor. + * @param[in] uuid The 128-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Ignored if this is a Client Characteristic Configuration descriptor. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p + * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client + * Characteristic Configuration descriptor. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial descriptor value. Length of this value must be + * less than or equal to @p maxlen. Ignored if value type is @ref + * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic + * Configuration descriptor. + * @param[out] descriptor The descriptor attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor); + +/***************************************************************************//** + * + * Remove a descriptor from a characteristic. + * + * @param[in] session The database update session ID + * @param[in] descriptor The descriptor handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, + uint16_t descriptor); + +/***************************************************************************//** + * + * Start a service, so that the service and its attributes including + * characteristics and descriptors become visible to remote GATT clients after + * this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Stop a service, so that the service and its attributes including + * characteristics and descriptors become invisible to remote GATT clients after + * this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Start a characteristic, so that the characteristic and its attributes become + * visible to remote GATT clients after this change has been committed. + * SL_STATUS_INVALID_STATE error is returned if the parent service is not + * started. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Stop a characteristic, so that the characteristic and its attributes become + * invisible to remote GATT clients after this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Save all changes performed in the current session and close the session. The + * stack will assign final handles to new and affected attributes and handle + * GATT caching as needed. The stack removes the client characteristic + * configurations of non-connected GATT clients except the service-changed + * configuration. For connected GATT clients during this database change, the + * stack removes the configurations to the removed characteristics. The session + * ID, temporary attribute handles returned during this session, and other + * existing attribute handles that are after newly added or removed attributes + * are invalidated. + * + * Some attribute handles returned in this session may become invalid if + * attributes are not created in the order they present in the database. In this + * case, attribute handle cache of the database in the user application must be + * refreshed to avoid accidentally using an invalidated handle in subsequent + * operations. + * + * @param[in] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_commit(uint16_t session); + +/***************************************************************************//** + * + * Cancel all changes performed in the current session and close the session. + * The database remains in the same state it was in just before the session was + * started. The session ID and all temporary attribute handles returned during + * this session are invalidated. + * + * @param[in] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_abort(uint16_t session); + +/** @} */ // end addtogroup sl_bt_gattdb + +/** + * @addtogroup sl_bt_gatt_server GATT Server + * @{ + * + * @brief GATT Server + * + * These commands and events are used for accessing to the local GATT server and + * database. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gatt_server_set_max_mtu_id 0x0a0a0020 +#define sl_bt_cmd_gatt_server_get_mtu_id 0x0b0a0020 +#define sl_bt_cmd_gatt_server_find_attribute_id 0x060a0020 +#define sl_bt_cmd_gatt_server_read_attribute_value_id 0x000a0020 +#define sl_bt_cmd_gatt_server_read_attribute_type_id 0x010a0020 +#define sl_bt_cmd_gatt_server_write_attribute_value_id 0x020a0020 +#define sl_bt_cmd_gatt_server_send_user_read_response_id 0x030a0020 +#define sl_bt_cmd_gatt_server_send_user_write_response_id 0x040a0020 +#define sl_bt_cmd_gatt_server_send_notification_id 0x0f0a0020 +#define sl_bt_cmd_gatt_server_send_indication_id 0x100a0020 +#define sl_bt_cmd_gatt_server_notify_all_id 0x110a0020 +#define sl_bt_cmd_gatt_server_read_client_configuration_id 0x120a0020 +#define sl_bt_cmd_gatt_server_send_user_prepare_write_response_id 0x140a0020 +#define sl_bt_cmd_gatt_server_set_capabilities_id 0x080a0020 +#define sl_bt_cmd_gatt_server_enable_capabilities_id 0x0c0a0020 +#define sl_bt_cmd_gatt_server_disable_capabilities_id 0x0d0a0020 +#define sl_bt_cmd_gatt_server_get_enabled_capabilities_id 0x0e0a0020 +#define sl_bt_cmd_gatt_server_read_client_supported_features_id 0x150a0020 +#define sl_bt_rsp_gatt_server_set_max_mtu_id 0x0a0a0020 +#define sl_bt_rsp_gatt_server_get_mtu_id 0x0b0a0020 +#define sl_bt_rsp_gatt_server_find_attribute_id 0x060a0020 +#define sl_bt_rsp_gatt_server_read_attribute_value_id 0x000a0020 +#define sl_bt_rsp_gatt_server_read_attribute_type_id 0x010a0020 +#define sl_bt_rsp_gatt_server_write_attribute_value_id 0x020a0020 +#define sl_bt_rsp_gatt_server_send_user_read_response_id 0x030a0020 +#define sl_bt_rsp_gatt_server_send_user_write_response_id 0x040a0020 +#define sl_bt_rsp_gatt_server_send_notification_id 0x0f0a0020 +#define sl_bt_rsp_gatt_server_send_indication_id 0x100a0020 +#define sl_bt_rsp_gatt_server_notify_all_id 0x110a0020 +#define sl_bt_rsp_gatt_server_read_client_configuration_id 0x120a0020 +#define sl_bt_rsp_gatt_server_send_user_prepare_write_response_id 0x140a0020 +#define sl_bt_rsp_gatt_server_set_capabilities_id 0x080a0020 +#define sl_bt_rsp_gatt_server_enable_capabilities_id 0x0c0a0020 +#define sl_bt_rsp_gatt_server_disable_capabilities_id 0x0d0a0020 +#define sl_bt_rsp_gatt_server_get_enabled_capabilities_id 0x0e0a0020 +#define sl_bt_rsp_gatt_server_read_client_supported_features_id 0x150a0020 + +/** + * @brief These values define whether the server is to sent notifications or + * indications to a remote GATT server. + */ +typedef enum +{ + sl_bt_gatt_server_disable = 0x0, /**< (0x0) Disable + notifications and + indications. */ + sl_bt_gatt_server_notification = 0x1, /**< (0x1) The + characteristic value + shall be notified. */ + sl_bt_gatt_server_indication = 0x2, /**< (0x2) The + characteristic value + shall be indicated. */ + sl_bt_gatt_server_notification_and_indication = 0x3 /**< (0x3) The + characteristic value + notification and + indication are + enabled, application + decides which one to + send. */ +} sl_bt_gatt_server_client_configuration_t; + +/** + * @brief These values describe whether the characteristic client configuration + * was changed or whether a characteristic confirmation was received. + */ +typedef enum +{ + sl_bt_gatt_server_client_config = 0x1, /**< (0x1) Characteristic client + configuration has been changed. */ + sl_bt_gatt_server_confirmation = 0x2 /**< (0x2) Characteristic confirmation + has been received. */ +} sl_bt_gatt_server_characteristic_status_flag_t; + +/** + * @addtogroup sl_bt_evt_gatt_server_attribute_value sl_bt_evt_gatt_server_attribute_value + * @{ + * @brief Indicates that the value of an attribute in the local GATT database + * was changed by a remote GATT client + * + * The parameter @p att_opcode describes which GATT procedure was used to change + * the value. + */ + +/** @brief Identifier of the attribute_value event */ +#define sl_bt_evt_gatt_server_attribute_value_id 0x000a00a0 + +/***************************************************************************//** + * @brief Data structure of the attribute_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_attribute_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t attribute; /**< Attribute Handle */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which the + value was received. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Value */ +}); + +typedef struct sl_bt_evt_gatt_server_attribute_value_s sl_bt_evt_gatt_server_attribute_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_attribute_value + +/** + * @addtogroup sl_bt_evt_gatt_server_user_read_request sl_bt_evt_gatt_server_user_read_request + * @{ + * @brief Indicates that a remote GATT client is attempting to read a value of + * an attribute from the local GATT database, where the attribute was defined in + * the GATT database XML file to have the type="user" + * + * The parameter @p att_opcode informs which GATT procedure was used to read the + * value. The application needs to respond to this request by using the @ref + * sl_bt_gatt_server_send_user_read_response command within 30 seconds, + * otherwise further GATT transactions are not allowed by the remote side. + */ + +/** @brief Identifier of the user_read_request event */ +#define sl_bt_evt_gatt_server_user_read_request_id 0x010a00a0 + +/***************************************************************************//** + * @brief Data structure of the user_read_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_user_read_request_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which the + value was received. */ + uint16_t offset; /**< Value offset */ +}); + +typedef struct sl_bt_evt_gatt_server_user_read_request_s sl_bt_evt_gatt_server_user_read_request_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_read_request + +/** + * @addtogroup sl_bt_evt_gatt_server_user_write_request sl_bt_evt_gatt_server_user_write_request + * @{ + * @brief Indicates that a remote GATT client is attempting to write a value of + * an attribute into the local GATT database, where the attribute was defined in + * the GATT database XML file to have the type="user" + * + * The parameter @p att_opcode informs which attribute procedure was used to + * write the value. If the @p att_opcode is @ref sl_bt_gatt_write_request (see + * @ref sl_bt_gatt_att_opcode_t), the application needs to respond to this + * request by using the @ref sl_bt_gatt_server_send_user_write_response command + * within 30 seconds, otherwise further GATT transactions are not allowed by the + * remote side. If the @p att_opcode is @ref sl_bt_gatt_prepare_write_request, + * the application needs to respond to this request by using the @ref + * sl_bt_gatt_server_send_user_prepare_write_response command within 30 seconds, + * otherwise further GATT transactions are not allowed by the remote side. If + * the value of @p att_opcode is @ref sl_bt_gatt_execute_write_request, it + * indicates that there was one or more prepare writes earlier and now the GATT + * server is processing the execute write, the value of @p characteristic is set + * to 0 and should be ignored. The event @ref + * sl_bt_evt_gatt_server_execute_write_completed will be emitted after + * responding to @ref sl_bt_gatt_execute_write_request by using @ref + * sl_bt_gatt_server_send_user_write_response. + */ + +/** @brief Identifier of the user_write_request event */ +#define sl_bt_evt_gatt_server_user_write_request_id 0x020a00a0 + +/***************************************************************************//** + * @brief Data structure of the user_write_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_user_write_request_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which + the value was received. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Value */ +}); + +typedef struct sl_bt_evt_gatt_server_user_write_request_s sl_bt_evt_gatt_server_user_write_request_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_write_request + +/** + * @addtogroup sl_bt_evt_gatt_server_characteristic_status sl_bt_evt_gatt_server_characteristic_status + * @{ + * @brief Indicates either that a local Client Characteristic Configuration + * descriptor was changed by the remote GATT client, or that a confirmation from + * the remote GATT client was received upon a successful reception of the + * indication + * + * A confirmation by the remote GATT client should be received within 30 seconds + * after an indication was sent with the @ref sl_bt_gatt_server_send_indication + * command, otherwise further GATT transactions over this connection are not + * allowed by the stack. + */ + +/** @brief Identifier of the characteristic_status event */ +#define sl_bt_evt_gatt_server_characteristic_status_id 0x030a00a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic_status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_characteristic_status_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the + gatt_characteristic event. */ + uint8_t status_flags; /**< Enum @ref + sl_bt_gatt_server_characteristic_status_flag_t. + Describes whether Client Characteristic + Configuration was changed or if a + confirmation was received. Values: + - sl_bt_gatt_server_client_config + (0x1): Characteristic client + configuration has been changed. + - sl_bt_gatt_server_confirmation + (0x2): Characteristic confirmation + has been received. */ + uint16_t client_config_flags; /**< Enum @ref + sl_bt_gatt_server_client_configuration_t. + This field carries the new value of the + Client Characteristic Configuration. If the + status_flags is 0x2 (confirmation + received), the value of this field can be + ignored. */ + uint16_t client_config; /**< The handle of client-config descriptor. */ +}); + +typedef struct sl_bt_evt_gatt_server_characteristic_status_s sl_bt_evt_gatt_server_characteristic_status_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_characteristic_status + +/** + * @addtogroup sl_bt_evt_gatt_server_execute_write_completed sl_bt_evt_gatt_server_execute_write_completed + * @{ + * @brief Indicates that the execute write command from a remote GATT client has + * completed with the given result + */ + +/** @brief Identifier of the execute_write_completed event */ +#define sl_bt_evt_gatt_server_execute_write_completed_id 0x040a00a0 + +/***************************************************************************//** + * @brief Data structure of the execute_write_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_execute_write_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t result; /**< Execute write result */ +}); + +typedef struct sl_bt_evt_gatt_server_execute_write_completed_s sl_bt_evt_gatt_server_execute_write_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_execute_write_completed + +/** + * @addtogroup sl_bt_evt_gatt_server_indication_timeout sl_bt_evt_gatt_server_indication_timeout + * @{ + * @brief Indicates confirmation from the remote GATT client has not been + * received within 30 seconds after an indication was sent + * + * Furthermore, the stack does not allow GATT transactions over this connection. + */ + +/** @brief Identifier of the indication_timeout event */ +#define sl_bt_evt_gatt_server_indication_timeout_id 0x050a00a0 + +/***************************************************************************//** + * @brief Data structure of the indication_timeout event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_indication_timeout_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_gatt_server_indication_timeout_s sl_bt_evt_gatt_server_indication_timeout_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_indication_timeout + +/** + * @addtogroup sl_bt_evt_gatt_server_notification_tx_completed sl_bt_evt_gatt_server_notification_tx_completed + * @{ + * @brief Indicates that one or more GATT notifications have been transmitted. + * + * By default, this event is not enabled on Bluetooth connections due to + * additional resource usages + * + * Following enablers are required to enable the Bluetooth stack's functionality + * for supporting this event, + * - Include feature bluetooth_feature_resource_report in the application + * project. + * - Use command @ref sl_bt_resource_enable_connection_tx_report to enable + * data packet TX status reports before this Bluetooth connection is + * established. + */ + +/** @brief Identifier of the notification_tx_completed event */ +#define sl_bt_evt_gatt_server_notification_tx_completed_id 0x060a00a0 + +/***************************************************************************//** + * @brief Data structure of the notification_tx_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_notification_tx_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t count; /**< Number of notifications that have been transmitted */ +}); + +typedef struct sl_bt_evt_gatt_server_notification_tx_completed_s sl_bt_evt_gatt_server_notification_tx_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_notification_tx_completed + +/***************************************************************************//** + * + * Set the maximum size of ATT Message Transfer Units (MTU). The functionality + * is the same as @ref sl_bt_gatt_set_max_mtu and this setting applies to both + * GATT client and server. If the given value is too large according to the + * maximum BGAPI payload size, the system will select the maximum possible value + * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT + * client in the stack will automatically send an MTU exchange request after a + * Bluetooth connection was established. + * + * @param[in] max_mtu @parblock + * Maximum size of Message Transfer Units (MTU) allowed + * - Range: 23 to 250 + * + * Default: 247 + * @endparblock + * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this + * command succeeded + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, + uint16_t *max_mtu_out); + +/***************************************************************************//** + * + * Get the size of ATT Message Transfer Units (MTU) for a connection. + * + * @param[in] connection Connection handle + * @param[out] mtu The maximum ATT_MTU used by the connection + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu); + +/***************************************************************************//** + * + * Find attributes of a certain type from a local GATT database. The type is + * usually given as a 16-bit or 128-bit UUID in little endian format. + * + * @param[in] start Search start handle + * @param[in] type_len Length of data in @p type + * @param[in] type The attribute type UUID + * @param[out] attribute Attribute handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, + size_t type_len, + const uint8_t* type, + uint16_t *attribute); + +/***************************************************************************//** + * + * Read the value of an attribute from a local GATT database. Only (maximum + * BGAPI payload size - 3) amount of data can be read at once. The application + * can continue reading with increased offset value if it receives (maximum + * BGAPI payload size - 3) number of bytes. + * + * @param[in] attribute Attribute handle + * @param[in] offset Value offset + * @param[in] max_value_size Size of output buffer passed in @p value + * @param[out] value_len On return, set to the length of output data written to + * @p value + * @param[out] value The attribute value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, + uint16_t offset, + size_t max_value_size, + size_t *value_len, + uint8_t *value); + +/***************************************************************************//** + * + * Read the type of an attribute from a local GATT database. The type is a UUID, + * usually 16 or 128 bits long in little endian format. + * + * @param[in] attribute Attribute handle + * @param[in] max_type_size Size of output buffer passed in @p type + * @param[out] type_len On return, set to the length of output data written to + * @p type + * @param[out] type The attribute type UUID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, + size_t max_type_size, + size_t *type_len, + uint8_t *type); + +/***************************************************************************//** + * + * Write the value of an attribute in the local GATT database. Writing the value + * of a characteristic of the local GATT database will not trigger notifications + * or indications to the remote GATT client if the characteristic has a property + * to indicate or notify and the client has enabled notification or indication. + * Notifications and indications are sent to the remote GATT client using @ref + * sl_bt_gatt_server_send_notification or @ref sl_bt_gatt_server_send_indication + * commands. + * + * @param[in] attribute Attribute handle + * @param[in] offset Value offset + * @param[in] value_len Length of data in @p value + * @param[in] value Value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, + uint16_t offset, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_read_request event. The + * response needs to be sent within 30 seconds, otherwise no more GATT + * transactions are allowed by the remote side. If attr_errorcode is set to 0, + * the characteristic value is sent to the remote GATT client in the standard + * way. Other attr_errorcode values will cause the local GATT server to send an + * attribute protocol error response instead of the actual data. Maximum number + * of bytes this command can send depends on the value of parameter att_opcode + * in @ref sl_bt_evt_gatt_server_user_read_request event: + * - ATT_MTU - 1 if the opcode is @ref sl_bt_gatt_read_request or @ref + * sl_bt_gatt_read_blob_request + * - ATT_MTU - 4 if the opcode is @ref sl_bt_gatt_read_by_type_request + * + * If the data length in @p value exceeds the limit, the first maximum number of + * bytes will be sent and rest data is ignored. The actual number of bytes that + * was sent is retruned in the response of this command. + * + * The client will continue reading by sending a new read blob request with an + * increased offset value if it receives the maximum amount of attribute data + * the read respond packet can contain. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle received in the @ref + * sl_bt_evt_gatt_server_user_read_request event. + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value to send to the GATT client. Ignored if + * att_errorcode is not 0. + * @param[out] sent_len The length of data sent to the remote GATT client + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when + * parameter @p att_opcode in the event is @ref sl_bt_gatt_write_request or @ref + * sl_bt_gatt_execute_write_request (see @ref sl_bt_gatt_att_opcode_t). The + * response needs to be sent within 30 seconds, otherwise no more GATT + * transactions are allowed by the remote side. When responding to @ref + * sl_bt_gatt_execute_write_request, the value of parameter @p characteristic is + * ignored. If attr_errorcode is set to 0, the ATT protocol's write response is + * sent to indicate to the remote GATT client that the write operation was + * processed successfully. Other values will cause the local GATT server to send + * an ATT protocol error response. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle received in the @ref + * sl_bt_evt_gatt_server_user_write_request event + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode); + +/***************************************************************************//** + * + * Send a notification to a remote GATT client. At most, ATT_MTU - 3 number of + * bytes can be sent in a notification. An error SL_STATUS_COMMAND_TOO_LONG is + * returned if the value length exceeds ATT_MTU - 3. + * + * A notification is sent only if the client has enabled it by setting the + * corresponding flag to the Client Characteristic Configuration descriptor. The + * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not + * have the notification property. The error SL_STATUS_INVALID_STATE is returned + * if the client has not enabled the notification. + * + * @param[in] connection A handle of the connection over which the notification + * is sent. + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be notified + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send an indication to a remote GATT client. At most, ATT_MTU - 3 number of + * bytes can be sent in an indication. An error SL_STATUS_COMMAND_TOO_LONG is + * returned if the value length exceeds ATT_MTU - 3. + * + * An indication is sent only if the client has enabled it by setting the + * corresponding flag to the Client Characteristic Configuration descriptor. The + * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not + * have the indication property. The error SL_STATUS_INVALID_STATE is returned + * if the client has not enabled the indication. + * + * A new indication to a GATT client can't be sent until an outstanding + * indication procedure with the same client has completed. The procedure is + * completed when a confirmation from the client is received. The confirmation + * is indicated by @ref sl_bt_evt_gatt_server_characteristic_status. + * + * The error SL_STATUS_IN_PROGRESS is returned if an indication procedure with + * the same client is outstanding. Always wait for confirmation for previous + * indication before sending a new indication. + * + * @param[in] connection A handle of the connection over which the indication is + * sent. + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be indicated + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_server_characteristic_status - This event is + * triggered after the confirmation from the client is received. + * - @ref sl_bt_evt_gatt_server_indication_timeout - This event indicates + * confirmation from the remote GATT client has not been received within 30 + * seconds after an indication was sent. Further GATT transactions over this + * connection are not allowed by the stack. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send notifications or indications to all connected remote GATT clients. At + * most, ATT_MTU - 3 number of bytes can be sent in a notification or + * indication. If the value length exceeds the limit on a connection, the first + * ATT_MTU - 3 bytes will be sent and rest of data is ignored. + * + * A notification or indication is sent only if the client has enabled it by + * setting the corresponding flag to the Client Characteristic Configuration + * descriptor. If the Client Characteristic Configuration descriptor supports + * both notifications and indications, the stack will always send a notification + * even when the client has enabled both. + * + * A new indication to a GATT client can't be sent until an outstanding + * indication procedure with the same client has completed, and the operation + * will continue for the next client. The procedure is completed when a + * confirmation from the client is received. The confirmation is indicated by + * @ref sl_bt_evt_gatt_server_characteristic_status. + * + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be notified or indicated + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Read client characteristic configuration of a remote GATT client. + * + * @param[in] connection A handle of the connection to a remote client. + * @param[in] characteristic Characteristic handle + * @param[out] client_config_flags Enum @ref + * sl_bt_gatt_server_client_configuration_t. Client characteristic + * configuration of a remote client. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, + uint16_t characteristic, + uint16_t *client_config_flags); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when + * parameter @p att_opcode in the event is @ref sl_bt_gatt_prepare_write_request + * (see @ref sl_bt_gatt_att_opcode_t). The response needs to be sent within 30 + * seconds, otherwise no more GATT transactions are allowed by the remote side. + * If @p att_errorcode is set to 0, the ATT protocol's prepare write response is + * sent to indicate to the remote GATT client that the write operation was + * processed successfully. Other values will cause the local GATT server to send + * an ATT protocol error response. The application should set values of + * parameters @p offset and @p value to identical values from the @ref + * sl_bt_evt_gatt_server_user_write_request event. The values will be verified + * on the client side in case the request is a reliable write (by Bluetooth Core + * Specification Volume 3, Part G, 4.9.5). + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * @param[in] offset Value offset + * @param[in] value_len Length of data in @p value + * @param[in] value Value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + uint16_t offset, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Reset capabilities that should be enabled by the GATT database. A service is + * visible to remote GATT clients if at least one of its capabilities is + * enabled. The same applies to a characteristic and its attributes. Capability + * identifiers and their corresponding bit flag values are in the auto-generated + * database header file. See UG118: Blue Gecko Bluetooth Profile Toolkit + * Developer's Guide for how to declare capabilities in the GATT database. + * + * Changing the capabilities of a database effectively causes a database change + * (attributes being added or removed) from a remote GATT client point of view. + * If the database has a Generic Attribute service and Service Changed + * characteristic, the stack will monitor the local database change status and + * manage service changed indications for a GATT client that has enabled the + * indication configuration of the Service Changed characteristic. + * + * @param[in] caps Bit flags of capabilities to reset. Value 0 sets the default + * database capabilities. + * @param[in] reserved Use the value 0 on this reserved field. Do not use + * none-zero values because they are reserved for future use. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, + uint32_t reserved); + +/***************************************************************************//** + * + * Enable additional capabilities in the local GATT database. Already enabled + * capabilities keep unchanged after this command. See @ref + * sl_bt_gatt_server_set_capabilities for more information. + * + * @param[in] caps Capabilities to enable + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps); + +/***************************************************************************//** + * + * Disable the given capabilities in the local GATT database. See @ref + * sl_bt_gatt_server_set_capabilities for more information. + * + * @param[in] caps Capabilities to disable + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps); + +/***************************************************************************//** + * + * Get capabilities currently enabled in the local GATT database. + * + * @param[out] caps Enabled capabilities + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps); + +/***************************************************************************//** + * + * Read client supported features of a remote GATT client. + * + * @param[in] connection A handle of the connection to a remote client. + * @param[out] client_features Bit field describing client supported features of + * a remote client. See Bluetooth specification Vol 3, Part G, 7.2 for the + * values. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, + uint8_t *client_features); + +/** @} */ // end addtogroup sl_bt_gatt_server + +/** + * @addtogroup sl_bt_nvm NVM + * @{ + * + * @brief NVM + * + * Provide an interface to manage user data objects (key/value pairs) in the + * flash memory. User data stored within the flash memory is persistent across + * reset and power cycling of the device. Because Bluetooth bondings are also + * stored in the flash area, in addition to the flash storage size, the space + * available for user data also depends on the number of bondings the device has + * at the time. + * + * On EFR32[B|M]G1x devices, either PS Store or NVM3 data storage driver can be + * used. PS Store is supported by the Bluetooth stack only. Using NVM3 is + * recommended if the device needs to support Dynamic Multiple Protocol (DMP). + * On EFR32[B|M]G2x devices, only NVM3 is supported. When NVM3 is used, + * applications can also use the NVM3 APIs directly. + * + * In PS Store, the flash storage size is fixed at 2048 bytes. The maximum data + * object size associated to a key is 56 bytes. A Bluetooth bonding uses at + * maximum 138 bytes for secure connections and 174 bytes for legacy pairing. + * + * In NVM3, the flash store size is configurable and the minimum is 3 flash + * pages. The maximum data object size is configurable up to 4096 bytes. A + * Bluetooth bonding uses maximum 110 bytes for secure connections and 138 bytes + * for legacy pairing. For more details, see AN1135 "Using Third Generation + * NonVolatile Memory (NVM3) Data Storage". + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_nvm_save_id 0x020d0020 +#define sl_bt_cmd_nvm_load_id 0x030d0020 +#define sl_bt_cmd_nvm_erase_id 0x040d0020 +#define sl_bt_cmd_nvm_erase_all_id 0x010d0020 +#define sl_bt_rsp_nvm_save_id 0x020d0020 +#define sl_bt_rsp_nvm_load_id 0x030d0020 +#define sl_bt_rsp_nvm_erase_id 0x040d0020 +#define sl_bt_rsp_nvm_erase_all_id 0x010d0020 + +/** + * @addtogroup sl_bt_nvm_keys Defined Keys + * @{ + * + * Define keys + */ + +/** Crystal tuning value override */ +#define SL_BT_NVM_KEY_CTUNE 0x32 + +/** @} */ // end Defined Keys + +/***************************************************************************//** + * + * Store a value into the specified NVM key. Allowed NVM keys are in range from + * 0x4000 to 0x407F. At most, 56 bytes user data can be stored in one NVM key. + * The error code 0x018a (command_too_long) is returned if the value data is + * more than 56 bytes. + * + * @param[in] key NVM key + * @param[in] value_len Length of data in @p value + * @param[in] value Value to store into the specified NVM key + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_save(uint16_t key, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Retrieve the value of the specified NVM key. + * + * @param[in] key NVM key of the value to be retrieved + * @param[in] max_value_size Size of output buffer passed in @p value + * @param[out] value_len On return, set to the length of output data written to + * @p value + * @param[out] value The returned value of the specified NVM key + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_load(uint16_t key, + size_t max_value_size, + size_t *value_len, + uint8_t *value); + +/***************************************************************************//** + * + * Delete a single NVM key and its value from the persistent store. + * + * @param[in] key NVM key to delete + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_erase(uint16_t key); + +/***************************************************************************//** + * + * Delete all NVM keys and their corresponding values. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_erase_all(); + +/** @} */ // end addtogroup sl_bt_nvm + +/** + * @addtogroup sl_bt_test Testing Commands + * @{ + * + * @brief Testing Commands + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_test_dtm_tx_v4_id 0x030e0020 +#define sl_bt_cmd_test_dtm_tx_cw_id 0x040e0020 +#define sl_bt_cmd_test_dtm_rx_id 0x010e0020 +#define sl_bt_cmd_test_dtm_end_id 0x020e0020 +#define sl_bt_rsp_test_dtm_tx_v4_id 0x030e0020 +#define sl_bt_rsp_test_dtm_tx_cw_id 0x040e0020 +#define sl_bt_rsp_test_dtm_rx_id 0x010e0020 +#define sl_bt_rsp_test_dtm_end_id 0x020e0020 + +/** + * @brief Test packet types supported by the stack + */ +typedef enum +{ + sl_bt_test_pkt_prbs9 = 0x0, /**< (0x0) PRBS9 packet payload */ + sl_bt_test_pkt_11110000 = 0x1, /**< (0x1) 11110000 packet payload */ + sl_bt_test_pkt_10101010 = 0x2, /**< (0x2) 10101010 packet payload */ + sl_bt_test_pkt_11111111 = 0x4, /**< (0x4) 11111111 packet payload */ + sl_bt_test_pkt_00000000 = 0x5, /**< (0x5) 00000000 packet payload */ + sl_bt_test_pkt_00001111 = 0x6, /**< (0x6) 00001111 packet payload */ + sl_bt_test_pkt_01010101 = 0x7, /**< (0x7) 01010101 packet payload */ + sl_bt_test_pkt_pn9 = 0xfd, /**< (0xfd) PN9 continuously modulated output */ + sl_bt_test_pkt_carrier = 0xfe /**< (0xfe) Unmodulated carrier */ +} sl_bt_test_packet_type_t; + +/** + * @brief Test PHY types + */ +typedef enum +{ + sl_bt_test_phy_1m = 0x1, /**< (0x1) 1M PHY */ + sl_bt_test_phy_2m = 0x2, /**< (0x2) 2M PHY */ + sl_bt_test_phy_125k = 0x3, /**< (0x3) 125k Coded PHY */ + sl_bt_test_phy_500k = 0x4 /**< (0x4) 500k Coded PHY */ +} sl_bt_test_phy_t; + +/** + * @addtogroup sl_bt_evt_test_dtm_completed sl_bt_evt_test_dtm_completed + * @{ + * @brief Indicates that the radio has processed a test start or end command + * + * The @p result parameter indicates the success of the command. + * + * After the receiver or transmitter test is stopped, the @p number_of_packets + * parameter in this event indicates the number of received or transmitted + * packets. + */ + +/** @brief Identifier of the dtm_completed event */ +#define sl_bt_evt_test_dtm_completed_id 0x000e00a0 + +/***************************************************************************//** + * @brief Data structure of the dtm_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_test_dtm_completed_s +{ + uint16_t result; /**< Command result */ + uint16_t number_of_packets; /**< Number of packets + + Only valid for @ref sl_bt_test_dtm_end + command. */ +}); + +typedef struct sl_bt_evt_test_dtm_completed_s sl_bt_evt_test_dtm_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_test_dtm_completed + +/***************************************************************************//** + * + * Start a transmitter test against a separate Bluetooth tester device. When the + * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event + * is triggered. This event indicates whether the test started successfully. + * + * In the transmitter test, the device sends packets continuously with a fixed + * interval. The type and length of each packet is set by @p packet_type and @p + * length parameters. The parameter @p phy specifies which PHY is used to + * transmit the packets. All devices support at least 1M PHY. A special packet + * type, test_pkt_carrier , can be used to transmit continuous + * unmodulated carrier. The length field is ignored in this mode. As this + * command has the limitation within the value of @p power_level, use of @ref + * sl_bt_test_dtm_tx_cw for custom waves is recommended. + * + * Stop the test using the @ref sl_bt_test_dtm_end command. + * + * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to + * transmit. Values: + * - sl_bt_test_pkt_prbs9 (0x0): PRBS9 packet payload + * - sl_bt_test_pkt_11110000 (0x1): 11110000 packet payload + * - sl_bt_test_pkt_10101010 (0x2): 10101010 packet payload + * - sl_bt_test_pkt_11111111 (0x4): 11111111 packet payload + * - sl_bt_test_pkt_00000000 (0x5): 00000000 packet payload + * - sl_bt_test_pkt_00001111 (0x6): 00001111 packet payload + * - sl_bt_test_pkt_01010101 (0x7): 01010101 packet payload + * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output + * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier + * @param[in] length @parblock + * Packet length in bytes + * + * Range: 0-255 + * @endparblock + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * @param[in] power_level @parblock + * TX power level in unit dBm. Values: + * - -127 to +20: Use specified or the nearest TX power level. The + * minimum -127 dBm is specified in the Bluetooth specification. However, + * a device may not support this low TX power. In addition, only some + * devices support 20 dBm TX power. Effective TX power will be limited by + * the global system TX power that can be set with the @ref + * sl_bt_system_set_tx_power command. + * - 0x7E: Use minimum TX power level the device supports. + * - 0x7F: Use the smallest of the maximum TX power level the device + * supports and the global maximum TX power setting in stack. + * + * For continuous unmodulated carrier mode, the values are set in 0.1 dBm + * unit. If the value exceeds the range of power level value allowed by the + * device, the command will adjust the power level to the closest minimum or + * maximum value. + * @endparblock + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, + uint8_t length, + uint8_t channel, + uint8_t phy, + int8_t power_level); + +/***************************************************************************//** + * + * Start a transmitter test for a custom wave. When the command is processed by + * the radio, a @ref sl_bt_evt_test_dtm_completed event is triggered. This event + * indicates whether the test started successfully. + * + * In the custom wave transmitter test, the device continuously transmits the + * career. The parameter @p packet_type specifies the packet type. The parameter + * @p phy specifies which PHY is used to transmit the packets. All devices + * support at least 1M PHY. + * + * Stop the test using the @ref sl_bt_test_dtm_end command. + * + * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to + * transmit. Values: + * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output + * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * @param[in] power_level @parblock + * TX power level. Unit: 0.1 dBm. + * + * If the value exceeds the range of power level value, allowed by the device, + * the command will adjust the power level to the closest minimum or maximum + * value. + * @endparblock + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, + uint8_t channel, + uint8_t phy, + int16_t power_level); + +/***************************************************************************//** + * + * Start a receiver test against a separate Bluetooth tester device. When the + * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event + * is triggered. This event indicates whether the test started successfully. + * + * Parameter @p phy specifies which PHY is used to receive the packets. All + * devices support at least 1M PHY. + * + * The test may be stopped using @ref sl_bt_test_dtm_end command. This will + * trigger another @ref sl_bt_evt_test_dtm_completed event, which carries the + * number of packets received during the test. + * + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy); + +/***************************************************************************//** + * + * End a transmitter or a receiver test. When the command is processed by the + * radio and the test has ended, a @ref sl_bt_evt_test_dtm_completed event is + * triggered. + * + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - Received when the command is + * processed by the radio and the test has ended. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_end(); + +/** @} */ // end addtogroup sl_bt_test + +/** + * @addtogroup sl_bt_sm Security Manager + * @{ + * + * @brief Security Manager + * + * The commands in this class manage Bluetooth security, including commands for + * starting and stopping encryption and commands for management of all bonding + * operations. + * + * Use the following procedure to bond with a remote device: + * - Use the command @ref sl_bt_sm_configure to configure security + * requirements and I/O capabilities of this device. + * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into + * bondable mode. + * - Use the command @ref sl_bt_connection_open to open a connection to the + * remote device. + * - After the connection is open, use command @ref sl_bt_sm_increase_security + * to encrypt the connection. This will also start the bonding process. + * + * Use the following procedure to respond to the bonding initiated by a remote + * device: + * - Use the command @ref sl_bt_sm_configure to configure security + * requirements and I/O capabilities of this device. + * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into + * bondable mode. + * - Use the command @ref sl_bt_advertiser_start to start connectable + * advertising. + * - Open a connection to this device from the remote device. + * - After the connection is open, start the bonding process on the remote + * device. + * + * If MITM is required, the application needs to display or ask the user to + * enter a passkey during the process. See events @ref + * sl_bt_evt_sm_passkey_display and @ref sl_bt_evt_sm_passkey_request for more + * information. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sm_configure_id 0x010f0020 +#define sl_bt_cmd_sm_set_minimum_key_size_id 0x140f0020 +#define sl_bt_cmd_sm_set_debug_mode_id 0x0f0f0020 +#define sl_bt_cmd_sm_add_to_whitelist_id 0x130f0020 +#define sl_bt_cmd_sm_store_bonding_configuration_id 0x020f0020 +#define sl_bt_cmd_sm_set_bondable_mode_id 0x000f0020 +#define sl_bt_cmd_sm_set_passkey_id 0x100f0020 +#define sl_bt_cmd_sm_increase_security_id 0x040f0020 +#define sl_bt_cmd_sm_enter_passkey_id 0x080f0020 +#define sl_bt_cmd_sm_passkey_confirm_id 0x090f0020 +#define sl_bt_cmd_sm_bonding_confirm_id 0x0e0f0020 +#define sl_bt_cmd_sm_delete_bonding_id 0x060f0020 +#define sl_bt_cmd_sm_delete_bondings_id 0x070f0020 +#define sl_bt_cmd_sm_get_bonding_handles_id 0x150f0020 +#define sl_bt_cmd_sm_get_bonding_details_id 0x160f0020 +#define sl_bt_cmd_sm_find_bonding_by_address_id 0x170f0020 +#define sl_bt_cmd_sm_resolve_rpa_id 0x1d0f0020 +#define sl_bt_cmd_sm_set_bonding_key_id 0x180f0020 +#define sl_bt_cmd_sm_set_legacy_oob_id 0x190f0020 +#define sl_bt_cmd_sm_set_oob_id 0x1a0f0020 +#define sl_bt_cmd_sm_set_remote_oob_id 0x1b0f0020 +#define sl_bt_cmd_sm_set_bonding_data_id 0x1c0f0020 +#define sl_bt_rsp_sm_configure_id 0x010f0020 +#define sl_bt_rsp_sm_set_minimum_key_size_id 0x140f0020 +#define sl_bt_rsp_sm_set_debug_mode_id 0x0f0f0020 +#define sl_bt_rsp_sm_add_to_whitelist_id 0x130f0020 +#define sl_bt_rsp_sm_store_bonding_configuration_id 0x020f0020 +#define sl_bt_rsp_sm_set_bondable_mode_id 0x000f0020 +#define sl_bt_rsp_sm_set_passkey_id 0x100f0020 +#define sl_bt_rsp_sm_increase_security_id 0x040f0020 +#define sl_bt_rsp_sm_enter_passkey_id 0x080f0020 +#define sl_bt_rsp_sm_passkey_confirm_id 0x090f0020 +#define sl_bt_rsp_sm_bonding_confirm_id 0x0e0f0020 +#define sl_bt_rsp_sm_delete_bonding_id 0x060f0020 +#define sl_bt_rsp_sm_delete_bondings_id 0x070f0020 +#define sl_bt_rsp_sm_get_bonding_handles_id 0x150f0020 +#define sl_bt_rsp_sm_get_bonding_details_id 0x160f0020 +#define sl_bt_rsp_sm_find_bonding_by_address_id 0x170f0020 +#define sl_bt_rsp_sm_resolve_rpa_id 0x1d0f0020 +#define sl_bt_rsp_sm_set_bonding_key_id 0x180f0020 +#define sl_bt_rsp_sm_set_legacy_oob_id 0x190f0020 +#define sl_bt_rsp_sm_set_oob_id 0x1a0f0020 +#define sl_bt_rsp_sm_set_remote_oob_id 0x1b0f0020 +#define sl_bt_rsp_sm_set_bonding_data_id 0x1c0f0020 + +/** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * @brief These values define the bonding keys of the bonded device stored in + * the persistent store. + */ +typedef enum +{ + sl_bt_sm_bonding_key_remote_ltk = 0x1, /**< (0x1) LTK used as central device, + always used when paired using + secure connections and local LTK + does not exist */ + sl_bt_sm_bonding_key_local_ltk = 0x2, /**< (0x2) LTK used as peripheral + device when using legacy pairing, + only used with secure connections + pairing if key exists */ + sl_bt_sm_bonding_key_irk = 0x3 /**< (0x3) Identity resolving key for + resolvable private addresses */ +} sl_bt_sm_bonding_key_t; +/** @endcond */ // end restricted enum type + +/** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * @brief These values define the bonding data types, which are stored in the + * persistent store. + */ +typedef enum +{ + sl_bt_sm_bonding_data_remote_address = 0x0, /**< (0x0) Identity address + of the remote device */ + sl_bt_sm_bonding_data_remote_ltk = 0x1, /**< (0x1) LTK used as + central device */ + sl_bt_sm_bonding_data_local_ltk = 0x2, /**< (0x2) LTK used as + peripheral device */ + sl_bt_sm_bonding_data_remote_master_inf = 0x3, /**< (0x3) Idenfication info + used as central device */ + sl_bt_sm_bonding_data_local_master_inf = 0x4, /**< (0x4) Idenfication info + used as central device */ + sl_bt_sm_bonding_data_irk = 0x5, /**< (0x5) IRK of the remote + device */ + sl_bt_sm_bonding_data_meta = 0x6, /**< (0x6) Metadata about + the bonding */ + sl_bt_sm_bonding_data_gatt_client_config = 0x7, /**< (0x7) GATT database + client configuration */ + sl_bt_sm_bonding_data_gatt_client_features = 0x8, /**< (0x8) GATT client + supported features */ + sl_bt_sm_bonding_data_gatt_db_hash = 0x9 /**< (0x9) GATT database + hash */ +} sl_bt_sm_bonding_data_t; +/** @endcond */ // end restricted enum type + +/** + * @brief These values define the security management related I/O capabilities + * supported by the device. + */ +typedef enum +{ + sl_bt_sm_io_capability_displayonly = 0x0, /**< (0x0) Display Only */ + sl_bt_sm_io_capability_displayyesno = 0x1, /**< (0x1) Display with + Yes/No-buttons */ + sl_bt_sm_io_capability_keyboardonly = 0x2, /**< (0x2) Keyboard Only */ + sl_bt_sm_io_capability_noinputnooutput = 0x3, /**< (0x3) No Input and No + Output */ + sl_bt_sm_io_capability_keyboarddisplay = 0x4 /**< (0x4) Display with Keyboard */ +} sl_bt_sm_io_capability_t; + +/** + * @addtogroup sl_bt_sm_configuration Security Manager configuration flags + * @{ + * + * These values are used to configure security requirements. + */ + +/** Bonding requires authentication (Man-in-the-Middle protection). */ +#define SL_BT_SM_CONFIGURATION_MITM_REQUIRED 0x1 + +/** Encryption requires bonding. Note that this setting will also enable + * bonding. */ +#define SL_BT_SM_CONFIGURATION_BONDING_REQUIRED 0x2 + +/** Require secure connections pairing. */ +#define SL_BT_SM_CONFIGURATION_SC_ONLY 0x4 + +/** Bonding requests need to be confirmed. Received bonding requests are + * notified by @ref sl_bt_evt_sm_confirm_bonding. */ +#define SL_BT_SM_CONFIGURATION_BONDING_REQUEST_REQUIRED 0x8 + +/** Allow connections only from bonded devices. This option is ignored when the + * application includes the bluetooth_feature_external_bonding_database feature. + * */ +#define SL_BT_SM_CONFIGURATION_CONNECTIONS_FROM_BONDED_DEVICES_ONLY 0x10 + +/** Prefer authenticated pairing when both options are possible based on the + * settings. Otherwise just works pairing is preferred. */ +#define SL_BT_SM_CONFIGURATION_PREFER_MITM 0x20 + +/** Require secure connections OOB data from both devices. */ +#define SL_BT_SM_CONFIGURATION_OOB_FROM_BOTH_DEVICES_REQUIRED 0x40 + +/** Reject pairing if remote device uses debug keys. */ +#define SL_BT_SM_CONFIGURATION_REJECT_DEBUG_KEYS 0x80 + +/** @} */ // end Security Manager configuration flags + +/** + * @addtogroup sl_bt_evt_sm_passkey_display sl_bt_evt_sm_passkey_display + * @{ + * @brief Indicates a request to display the passkey to the user. + */ + +/** @brief Identifier of the passkey_display event */ +#define sl_bt_evt_sm_passkey_display_id 0x000f00a0 + +/***************************************************************************//** + * @brief Data structure of the passkey_display event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_passkey_display_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t passkey; /**< Passkey. Range: 0 to 999999. + - NOTE! When displaying the passkey to the user, + prefix the number with zeros to obtain a 6 digit + number + - Example: Passkey value is 42 + - Number to display to the user is 000042 */ +}); + +typedef struct sl_bt_evt_sm_passkey_display_s sl_bt_evt_sm_passkey_display_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_passkey_display + +/** + * @addtogroup sl_bt_evt_sm_passkey_request sl_bt_evt_sm_passkey_request + * @{ + * @brief Indicates a request for the passkey prompt displayed on the remote + * device + * + * Use the command @ref sl_bt_sm_enter_passkey to input the passkey value. + */ + +/** @brief Identifier of the passkey_request event */ +#define sl_bt_evt_sm_passkey_request_id 0x010f00a0 + +/***************************************************************************//** + * @brief Data structure of the passkey_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_passkey_request_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_sm_passkey_request_s sl_bt_evt_sm_passkey_request_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_passkey_request + +/** + * @addtogroup sl_bt_evt_sm_confirm_passkey sl_bt_evt_sm_confirm_passkey + * @{ + * @brief Indicates a request for passkey display and confirmation by the user + * + * Use the command @ref sl_bt_sm_passkey_confirm to accept or reject the + * displayed passkey. + */ + +/** @brief Identifier of the confirm_passkey event */ +#define sl_bt_evt_sm_confirm_passkey_id 0x020f00a0 + +/***************************************************************************//** + * @brief Data structure of the confirm_passkey event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_confirm_passkey_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t passkey; /**< Passkey. Range: 0 to 999999. + - NOTE! When displaying the passkey to the user, + prefix the number with zeros to obtain a 6 digit + number + - Example: Passkey value is 42 + - Number to display to the user is 000042 */ +}); + +typedef struct sl_bt_evt_sm_confirm_passkey_s sl_bt_evt_sm_confirm_passkey_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_confirm_passkey + +/** + * @addtogroup sl_bt_evt_sm_bonded sl_bt_evt_sm_bonded + * @{ + * @brief Triggered when the pairing or bonding procedure is successfully + * completed. + */ + +/** @brief Identifier of the bonded event */ +#define sl_bt_evt_sm_bonded_id 0x030f00a0 + +/***************************************************************************//** + * @brief Data structure of the bonded event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_bonded_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + Pairing completed without bonding - the + pairing key will be discarded after + disconnection. + - Other: Procedure completed, pairing key + stored with given bonding handle */ + uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection + security mode. Values: + - sl_bt_connection_mode1_level2 (0x1): + Unauthenticated pairing with encryption + - sl_bt_connection_mode1_level3 (0x2): + Authenticated pairing with encryption + - sl_bt_connection_mode1_level4 (0x3): + Authenticated Secure Connections pairing with + encryption using a 128-bit strength encryption + key */ +}); + +typedef struct sl_bt_evt_sm_bonded_s sl_bt_evt_sm_bonded_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_bonded + +/** + * @addtogroup sl_bt_evt_sm_bonding_failed sl_bt_evt_sm_bonding_failed + * @{ + * @brief This event is triggered if the pairing or bonding procedure fails. + */ + +/** @brief Identifier of the bonding_failed event */ +#define sl_bt_evt_sm_bonding_failed_id 0x040f00a0 + +/***************************************************************************//** + * @brief Data structure of the bonding_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_bonding_failed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t reason; /**< Describes error that occurred */ +}); + +typedef struct sl_bt_evt_sm_bonding_failed_s sl_bt_evt_sm_bonding_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_bonding_failed + +/** + * @addtogroup sl_bt_evt_sm_confirm_bonding sl_bt_evt_sm_confirm_bonding + * @{ + * @brief Indicates a user request to display that the new bonding request is + * received and for the user to confirm the request + * + * Use the command @ref sl_bt_sm_bonding_confirm to accept or reject the bonding + * request. + */ + +/** @brief Identifier of the confirm_bonding event */ +#define sl_bt_evt_sm_confirm_bonding_id 0x090f00a0 + +/***************************************************************************//** + * @brief Data structure of the confirm_bonding event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_confirm_bonding_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t bonding_handle; /**< Bonding handle for the request. Range: 0 to 31, + or SL_BT_INVALID_BONDING_HANDLE (0xff). + - NOTE! When the bonding handle is anything + other than SL_BT_INVALID_BONDING_HANDLE + (0xff), a bonding already exists for this + connection. Overwriting the existing bonding + is a potential security risk. */ +}); + +typedef struct sl_bt_evt_sm_confirm_bonding_s sl_bt_evt_sm_confirm_bonding_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_confirm_bonding + +/***************************************************************************//** + * + * Configure security requirements and I/O capabilities of the system. + * + * @param[in] flags @parblock + * Security requirement flags. This value can be a bitmask of multiple flags + * from @ref sl_bt_sm_configuration + * + * Bit 0: + * - 0: Allow bonding without authentication + * - 1: Bonding requires authentication (Man-in-the-Middle + * protection) + * + * Bit 1: + * - 0: Allow encryption without bonding + * - 1: Encryption requires bonding. Note that this setting will also + * enable bonding. + * + * Bit 2: + * - 0: Allow bonding with legacy pairing + * - 1: Secure connections only + * + * Bit 3: + * - 0: Bonding request does not need to be confirmed + * - 1: Bonding requests need to be confirmed. Received bonding + * requests are notified by @ref sl_bt_evt_sm_confirm_bonding + * + * Bit 4: This option is ignored when the application includes the + * bluetooth_feature_external_bonding_database feature. + * - 0: Allow all connections + * - 1: Allow connections only from bonded devices + * + * Bit 5: + * - 0: Prefer just works pairing when both options are possible + * based on the settings. + * - 1: Prefer authenticated pairing when both options are possible + * based on the settings. + * + * Bit 6: + * - 0: Allow secure connections OOB pairing with OOB data from only + * one device. + * - 1: Require secure connections OOB data from both devices. + * + * Bit 7: + * - 0: Allow debug keys from remote device. + * - 1: Reject pairing if remote device uses debug keys. + * + * Default value: 0x00 + * @endparblock + * @param[in] io_capabilities Enum @ref sl_bt_sm_io_capability_t. I/O + * Capabilities. The default I/O Capability used by the stack is No Input and + * No Output. Values: + * - sl_bt_sm_io_capability_displayonly (0x0): Display Only + * - sl_bt_sm_io_capability_displayyesno (0x1): Display with + * Yes/No-buttons + * - sl_bt_sm_io_capability_keyboardonly (0x2): Keyboard Only + * - sl_bt_sm_io_capability_noinputnooutput (0x3): No Input and No + * Output + * - sl_bt_sm_io_capability_keyboarddisplay (0x4): Display with + * Keyboard + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities); + +/***************************************************************************//** + * + * Set the minimum allowed key size used for bonding. The default value is 16 + * bytes. + * + * @param[in] minimum_key_size Minimum allowed key size for bonding. Range: 7 to + * 16 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size); + +/***************************************************************************//** + * + * Set Security Manager in debug mode. In this mode, the secure connections + * bonding uses known debug keys, so that the encrypted packet can be opened by + * Bluetooth protocol analyzer. To disable the debug mode, restart the device. + * + * Bondings made in debug mode are unsecure. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_debug_mode(); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_accept_list_add_device_by_bonding and @ref + * sl_bt_accept_list_add_device_by_address provided by the + * bluetooth_feature_accept_list component. + * + * Add device to accept list, which can be enabled with @ref + * sl_bt_gap_enable_whitelisting. + * + * When using external bonding database, the accept list size must be set before + * adding devices to the list using @ref sl_bt_sm_store_bonding_configuration. + * + * @param[in] address Address of the device added to accept list + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device added to accept list. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type); + +/***************************************************************************//** + * + * Set the maximum allowed bonding count and bonding policy. The maximum number + * of bondings that can be supported depends on how much user data is stored in + * the NVM and the NVM size. When bond policy value 1 or 2 is selected, the + * stack will automatically write the new bond, as per the policy, only if the + * maximum allowed bonding count has been reached. If the stack can't write a + * new bond for any other reason (e.g., NVM is full), an error will be thrown + * through the bonding_failed event indicating why the bonding was not written. + * The application has to manually release space from the NVM (e.g., by deleting + * one of the existing bonds or application data) so that a new bond can be + * saved. The default value is 13. + * + * When using external bonding database with accept list filtering, this command + * must be called before adding devices to the accept list to define the list + * size. Calling this function empties the existing accept list. + * + * @param[in] max_bonding_count @parblock + * Maximum allowed bonding count. Range: 1 to 32 + * + * Sets the accept list size with external bonding database. + * @endparblock + * @param[in] policy_flags @parblock + * Bonding policy. Values: + * - 0: If database is full, new bonding attempts will fail + * - 1: New bonding will overwrite the oldest existing bonding + * - 2: New bonding will overwrite the bonding that was used the + * longest time ago + * + * Default: 0 + * + * With external bonding database the parameter is ignored. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, + uint8_t policy_flags); + +/***************************************************************************//** + * + * Set whether the device should accept new bondings. By default, the device + * does not accept new bondings. + * + * @param[in] bondable @parblock + * Bondable mode. Values: + * - 0: New bondings not accepted + * - 1: Bondings allowed + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable); + +/***************************************************************************//** + * + * Enter a fixed passkey, which will be used in the @ref + * sl_bt_evt_sm_passkey_display event. + * + * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to disable and + * start using random passkeys. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_passkey(int32_t passkey); + +/***************************************************************************//** + * + * Enhance the security of a connection to current security requirements. On an + * unencrypted connection, it will encrypt the connection and will also perform + * bonding if requested by both devices. On an encrypted connection, it will + * cause the connection to be re-encrypted. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_parameters - Triggered after increasing + * security has been completed successfully and indicates the latest + * security mode of the connection. + * - @ref sl_bt_evt_sm_bonded - Triggered if pairing or bonding was performed + * in this operation and the result is successful. + * - @ref sl_bt_evt_sm_bonding_failed - Triggered if pairing or bonding was + * performed in this operation and the result has failed. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_increase_security(uint8_t connection); + +/***************************************************************************//** + * + * Enter a passkey after receiving a passkey request event. + * + * @param[in] connection Connection handle + * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to cancel pairing. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey); + +/***************************************************************************//** + * + * Accept or reject the reported passkey confirm value. + * + * @param[in] connection Connection handle + * @param[in] confirm Acceptance. Values: + * - 0: Reject + * - 1: Accept confirm value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm); + +/***************************************************************************//** + * + * Accept or reject the bonding request. + * + * @param[in] connection Connection handle + * @param[in] confirm Acceptance. Values: + * - 0: Reject + * - 1: Accept bonding request + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm); + +/***************************************************************************//** + * + * Delete the specified bonding or accept list filtering. The connection will be + * closed if the remote device is connected currently. + * + * This commands deletes the information from the persistent bonding database + * when the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) is used. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] bonding Bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding); + +/***************************************************************************//** + * + * Delete all bondings, accept list filtering and device local identity + * resolving key (IRK). All connections to affected devices are closed as well. + * + * This command empties the persistent bonding database when the built-in + * bonding database (bluetooth_feature_builtin_bonding_database) is used. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_delete_bondings(); + +/***************************************************************************//** + * + * Get number of entries and bitmask of their handles saved in the bonding + * database. The entry in the bonding database can be either bonding or accept + * list filtering device. + * + * To get the bonding type and peer device address of a bonding, use the @ref + * sl_bt_sm_get_bonding_details command. The bonding handle can be calculated + * from the handle bitmask returned by this command, or alternatively, repeat + * calling the @ref sl_bt_sm_get_bonding_details command to get the detailed + * information of all bondings. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] reserved Use the value 0 on this reserved field. Do not use + * none-zero values because they are reserved for future use. + * @param[out] num_bondings Total number of bondings and accept list filtering + * devices stored in bonding database. + * @param[in] max_bondings_size Size of output buffer passed in @p bondings + * @param[out] bondings_len On return, set to the length of output data written + * to @p bondings + * @param[out] bondings 4 byte bit field of used bonding handles in little + * endian format. Bit 0 of first byte is bonding handle 0, bit 0 of second + * byte is bonding handle 8 etc. If the bit is 1 that bonding handle exists in + * the bonding database. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, + uint32_t *num_bondings, + size_t max_bondings_size, + size_t *bondings_len, + uint8_t *bondings); + +/***************************************************************************//** + * + * Get the detailed information for a bonding entry. Data includes remote device + * address and address type as well as security mode for bonding and a used + * encryption key length. + * + * To get the detailed information of all bondings, repeat calling this command + * starting from 0 as the bonding handle value until the maximum number of + * configured bondings are reached. Use 32 as the maximum number if the + * configured number is unknown. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] bonding Bonding handle + * @param[out] address Bluetooth address of the remote device + * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Accept list filtering entry has security mode as no + * security. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size Key length in bytes, 0 for accept list filtering entry + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, + bd_addr *address, + uint8_t *address_type, + uint8_t *security_mode, + uint8_t *key_size); + +/***************************************************************************//** + * + * Find the bonding or accept list filtering entry by using a Bluetooth device + * address. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] address The Bluetooth device address + * @param[out] bonding The bonding handle + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Accept list filtering entry has security mode as no + * security. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size Key length in bytes, 0 for accept list filtering entry + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, + uint32_t *bonding, + uint8_t *security_mode, + uint8_t *key_size); + +/***************************************************************************//** + * + * Find the identity address of bonded device by using resolvable private + * address (RPA). + * + * The error SL_STATUS_NOT_FOUND is returned if the RPA cannot be resolved. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] rpa Resolvable private address to be resolved + * @param[out] address The identity adderss of the bonded device + * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Identity address + * type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[out] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, + bd_addr *address, + uint8_t *address_type, + uint32_t *bonding); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Set key for bonding or accept list filtering entry overwriting any possible + * existing key. If there is error which leaves bonding entry in inconsistent + * state the bonding will be deleted. Only IRK can be added to accept list + * filtering entry. + * + * @param[in] bonding Bonding handle + * @param[in] key_type Enum @ref sl_bt_sm_bonding_key_t. Key type. Values: + * - sl_bt_sm_bonding_key_remote_ltk (0x1): LTK used as central + * device, always used when paired using secure connections and local LTK + * does not exist + * - sl_bt_sm_bonding_key_local_ltk (0x2): LTK used as peripheral + * device when using legacy pairing, only used with secure connections + * pairing if key exists + * - sl_bt_sm_bonding_key_irk (0x3): Identity resolving key for + * resolvable private addresses + * @param[in] key Bonding key in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, + uint8_t key_type, + aes_key_128 key); + +/***************************************************************************//** + * + * Set Out-Of-Band (OOB) encryption data for a legacy pairing of a device. OOB + * data may be, for example, a PIN code exchanged over an alternate path, such + * as NFC. The device will not allow any other bonding if OOB data is set. OOB + * data can't be set simultaneously with secure connections OOB data. + * + * @param[in] enable Enable OOB with legacy pairing. Values: + * - 0: disable + * - 1: enable + * @param[in] oob_data 16-byte legacy pairing OOB data in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data); + +/***************************************************************************//** + * + * Enable the use of Out-Of-Band (OOB) encryption data for a device for secure + * connections pairing. Enabling will generate new OOB data and confirm values, + * which can be sent to the remote device. After enabling the secure connections + * OOB data, the remote devices OOB data can be set with @ref + * sl_bt_sm_set_remote_oob. Calling this function will erase any set remote + * device OOB data and confirm values. The device will not allow any other + * bonding if OOB data is set. The secure connections OOB data cannot be enabled + * simultaneously with legacy pairing OOB data. + * + * @param[in] enable Enable OOB with secure connections pairing. Values: + * - 0: disable + * - 1: enable + * @param[out] random 16-byte randomly-generated secure connections OOB data in + * little endian format. + * @param[out] confirm 16-byte confirm value for the OOB random value in little + * endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_oob(uint8_t enable, + aes_key_128 *random, + aes_key_128 *confirm); + +/***************************************************************************//** + * + * Set Out-Of-Band (OOB) data and confirm values received from the remote device + * for secure connections pairing. OOB data must be enabled with @ref + * sl_bt_sm_set_oob before setting the remote device OOB data. + * + * @param[in] enable Enable remote device OOB data with secure connections + * pairing. Values: + * - 0: disable + * - 1: enable + * @param[in] random 16-byte remote device secure connections OOB data in little + * endian format. + * @param[in] confirm 16-byte remote device confirm value for the OOB random + * value in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, + aes_key_128 random, + aes_key_128 confirm); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Set bonding data for connection from external bonding database. + * + * @param[in] connection Connection handle + * @param[in] type Enum @ref sl_bt_sm_bonding_data_t. Bonding data type. Values: + * - sl_bt_sm_bonding_data_remote_address (0x0): Identity address of + * the remote device + * - sl_bt_sm_bonding_data_remote_ltk (0x1): LTK used as central + * device + * - sl_bt_sm_bonding_data_local_ltk (0x2): LTK used as peripheral + * device + * - sl_bt_sm_bonding_data_remote_master_inf (0x3): Idenfication info + * used as central device + * - sl_bt_sm_bonding_data_local_master_inf (0x4): Idenfication info + * used as central device + * - sl_bt_sm_bonding_data_irk (0x5): IRK of the remote device + * - sl_bt_sm_bonding_data_meta (0x6): Metadata about the bonding + * - sl_bt_sm_bonding_data_gatt_client_config (0x7): GATT database + * client configuration + * - sl_bt_sm_bonding_data_gatt_client_features (0x8): GATT client + * supported features + * - sl_bt_sm_bonding_data_gatt_db_hash (0x9): GATT database hash + * @param[in] data_len Length of data in @p data + * @param[in] data Bonding data. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/** @} */ // end addtogroup sl_bt_sm + +/** + * @addtogroup sl_bt_external_bondingdb External Bonding Database + * @{ + * + * @brief External Bonding Database + * + * Receive and respond to requests related to managing an external bonding + * database. When the application uses the + * bluetooth_feature_external_bonding_database feature, the Bluetooth stack and + * the application use the commands and events in this class to store and + * retrieve data from the persistent bonding storage. + * + * When this feature is used, the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) and the address resolving in the + * Bluetooth stack are excluded. The user application and external bonding + * database are responsible for the following functionalities: + * - The external bonding database must be able to reliably and permanently + * store the bonding data and type tuples that are provided by the stack in + * the @ref sl_bt_evt_external_bondingdb_data_request event. Data types @ref + * sl_bt_external_bondingdb_data_remote_address and @ref + * sl_bt_external_bondingdb_data_remote_address_type can be used by the + * application to identify the device, but they are not used by the stack + * and hence the stack will not ask for their values. Other data types in + * @ref sl_bt_external_bondingdb_data_t are needed by the Bluetooth Security + * Manager or GATT Server. The Long Term Keys (LTK) and Identity Resolving + * Keys (IRK) must be stored securely. When the database is on a separate + * host device, they must be securely transmitted between the host and + * target over the NCP transport. The application also needs to manage the + * bondings in the storage, e.g., delete a bonding when requested by the + * business logic. + * - Manage a local RAM-based bookkeeping to keep track of open connections. + * At a minimum, the remote Bluetooth address address and address type must + * be stored in the bookkeeping when a @ref sl_bt_evt_connection_opened + * event is received. If the remote Bluetooth device address is a resolvable + * private random (RPA) address, the application may perform address + * resolving using the IRK keys of the remote devices stored in the bonding + * database. Address resolving is required for identifying a connected + * device using an RPA address. When the scanner or periodic advertising + * synchronization feature is used, RPA addresses in advertisement report or + * sync events may need to be resolved if required by the business + * requirements. + * - When the Bluetooth stack requires bonding data, it will send an @ref + * sl_bt_evt_external_bondingdb_data_request event. The application must + * respond to the request by sending the data value using the @ref + * sl_bt_external_bondingdb_set_data command. The GATT server will pend the + * requests from the remote GATT client and encryption or bonding is not + * possible until all requested bonding data has been sent to the stack. The + * stack will send @ref sl_bt_evt_external_bondingdb_data_ready when it has + * received all the necessary bonding data from the application. + * + * In this configuration, the value of @p bonding parameter in @ref + * sl_bt_evt_advertiser_scan_request, @ref sl_bt_evt_connection_opened, @ref + * sl_bt_evt_sm_bonded, @ref sl_bt_evt_scanner_scan_report, @ref + * sl_bt_evt_scanner_legacy_advertisement_report, @ref + * sl_bt_evt_scanner_extended_advertisement_report, @ref sl_bt_evt_sync_opened, + * and @ref sl_bt_evt_sync_transfer_received is always + * SL_BT_INVALID_BONDING_HANDLE (0xff). Resolving the bonding handle is the + * responsibility of the external bonding database. Additionally, the following + * BGAPI commands are not available and will return the SL_STATUS_NOT_AVAILABLE + * error: + * - @ref sl_bt_sm_delete_bonding + * - @ref sl_bt_sm_get_bonding_handles + * - @ref sl_bt_sm_get_bonding_details + * - @ref sl_bt_sm_find_bonding_by_address + * - @ref sl_bt_sm_resolve_rpa + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_external_bondingdb_set_data_id 0x005c0020 +#define sl_bt_rsp_external_bondingdb_set_data_id 0x005c0020 + +/** + * @brief These values define the bonding data types, which are stored in the + * persistent store. + */ +typedef enum +{ + sl_bt_external_bondingdb_data_remote_address = 0x0, /**< (0x0) Identity + address of the + remote device, + which a + resolvable + random address + can be resolved + to */ + sl_bt_external_bondingdb_data_remote_address_type = 0x1, /**< (0x1) Type of + the remote + device identity + address. Value + 0 is public + device address + and 1 is static + device address */ + sl_bt_external_bondingdb_data_remote_ltk = 0x2, /**< (0x2) Long Term + Key (LTK) used + as central + device. The + value of this + type must be + stored + securely. */ + sl_bt_external_bondingdb_data_local_ltk = 0x3, /**< (0x3) Long Term + Key (LTK) used + as peripheral + device. The + value of this + type must be + stored + securely. */ + sl_bt_external_bondingdb_data_remote_central_inf = 0x4, /**< (0x4) + Identification + info used as a + central device */ + sl_bt_external_bondingdb_data_local_central_inf = 0x5, /**< (0x5) + Identification + info used as a + central device */ + sl_bt_external_bondingdb_data_irk = 0x6, /**< (0x6) Identity + Resolving Key + (IRK) of the + remote device + that is used + for resolving + its RPA + addresses when + the device is + in privacy + mode. The value + of this type + must be stored + securely. */ + sl_bt_external_bondingdb_data_meta = 0x7, /**< (0x7) Metadata + about the + bonding */ + sl_bt_external_bondingdb_data_gatt_client_config = 0x8, /**< (0x8) The + remote GATT + client + characteristic + configurations */ + sl_bt_external_bondingdb_data_gatt_client_features = 0x9, /**< (0x9) The + remote GATT + client + supported + features */ + sl_bt_external_bondingdb_data_gatt_db_hash = 0xa /**< (0xa) Latest + local GATT + database hash + value that the + remote client + has seen for + GATT robust + caching feature */ +} sl_bt_external_bondingdb_data_t; + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data_request sl_bt_evt_external_bondingdb_data_request + * @{ + * @brief Indicates that the Bluetooth stack requests the bonding data of a + * connection from the external bonding database + * + * The application must respond by setting bonding data using the @ref + * sl_bt_external_bondingdb_set_data command. + * + * The Bluetooth stack will send this event one or more times after a connection + * is open following the @ref sl_bt_evt_connection_opened event to get ready for + * security related operations. + */ + +/** @brief Identifier of the data_request event */ +#define sl_bt_evt_external_bondingdb_data_request_id 0x005c00a0 + +/***************************************************************************//** + * @brief Data structure of the data_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_request_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The + requested bonding data type. Values: + - sl_bt_external_bondingdb_data_remote_address + (0x0): Identity address of the remote device, + which a resolvable random address can be resolved + to + - sl_bt_external_bondingdb_data_remote_address_type + (0x1): Type of the remote device identity + address. Value 0 is public device address and 1 + is static device address + - sl_bt_external_bondingdb_data_remote_ltk + (0x2): Long Term Key (LTK) used as central + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_local_ltk + (0x3): Long Term Key (LTK) used as peripheral + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_remote_central_inf + (0x4): Identification info used as a central + device + - sl_bt_external_bondingdb_data_local_central_inf + (0x5): Identification info used as a central + device + - sl_bt_external_bondingdb_data_irk (0x6): + Identity Resolving Key (IRK) of the remote device + that is used for resolving its RPA addresses when + the device is in privacy mode. The value of this + type must be stored securely. + - sl_bt_external_bondingdb_data_meta (0x7): + Metadata about the bonding + - sl_bt_external_bondingdb_data_gatt_client_config + (0x8): The remote GATT client characteristic + configurations + - sl_bt_external_bondingdb_data_gatt_client_features + (0x9): The remote GATT client supported + features + - sl_bt_external_bondingdb_data_gatt_db_hash + (0xa): Latest local GATT database hash value + that the remote client has seen for GATT robust + caching feature */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_request_s sl_bt_evt_external_bondingdb_data_request_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_request + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data sl_bt_evt_external_bondingdb_data + * @{ + * @brief Indicates that updated bonding data of a connection is available + * + * The application must store it in the external bonding database permanently. + */ + +/** @brief Identifier of the data event */ +#define sl_bt_evt_external_bondingdb_data_id 0x015c00a0 + +/***************************************************************************//** + * @brief Data structure of the data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The + bonding data type. Values: + - sl_bt_external_bondingdb_data_remote_address + (0x0): Identity address of the remote + device, which a resolvable random address can + be resolved to + - sl_bt_external_bondingdb_data_remote_address_type + (0x1): Type of the remote device identity + address. Value 0 is public device address and + 1 is static device address + - sl_bt_external_bondingdb_data_remote_ltk + (0x2): Long Term Key (LTK) used as central + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_local_ltk + (0x3): Long Term Key (LTK) used as + peripheral device. The value of this type must + be stored securely. + - sl_bt_external_bondingdb_data_remote_central_inf + (0x4): Identification info used as a + central device + - sl_bt_external_bondingdb_data_local_central_inf + (0x5): Identification info used as a + central device + - sl_bt_external_bondingdb_data_irk + (0x6): Identity Resolving Key (IRK) of the + remote device that is used for resolving its + RPA addresses when the device is in privacy + mode. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_meta + (0x7): Metadata about the bonding + - sl_bt_external_bondingdb_data_gatt_client_config + (0x8): The remote GATT client + characteristic configurations + - sl_bt_external_bondingdb_data_gatt_client_features + (0x9): The remote GATT client supported + features + - sl_bt_external_bondingdb_data_gatt_db_hash + (0xa): Latest local GATT database hash + value that the remote client has seen for GATT + robust caching feature */ + uint8array data; /**< Bonding data */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_s sl_bt_evt_external_bondingdb_data_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data_ready sl_bt_evt_external_bondingdb_data_ready + * @{ + * @brief Indicates that stack has received all the necessary bonding data from + * the application and is now fully functional + */ + +/** @brief Identifier of the data_ready event */ +#define sl_bt_evt_external_bondingdb_data_ready_id 0x025c00a0 + +/***************************************************************************//** + * @brief Data structure of the data_ready event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_ready_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_ready_s sl_bt_evt_external_bondingdb_data_ready_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_ready + +/***************************************************************************//** + * + * Set bonding data of a connection from the external bonding database. When the + * Bluetooth stack needs bonding data, it will send the request to user + * application with a @ref sl_bt_evt_external_bondingdb_data_request event that + * contains the requested data type. The application must respond to the request + * by sending data using this command. + * + * Send 0 length data to the stack with this command if the requested data is + * not available in the external bonding database. + * + * @param[in] connection Connection handle + * @param[in] type Enum @ref sl_bt_external_bondingdb_data_t. Bonding data type. + * Values: + * - sl_bt_external_bondingdb_data_remote_address (0x0): Identity + * address of the remote device, which a resolvable random address can be + * resolved to + * - sl_bt_external_bondingdb_data_remote_address_type (0x1): Type of + * the remote device identity address. Value 0 is public device address + * and 1 is static device address + * - sl_bt_external_bondingdb_data_remote_ltk (0x2): Long Term Key + * (LTK) used as central device. The value of this type must be stored + * securely. + * - sl_bt_external_bondingdb_data_local_ltk (0x3): Long Term Key + * (LTK) used as peripheral device. The value of this type must be stored + * securely. + * - sl_bt_external_bondingdb_data_remote_central_inf (0x4): + * Identification info used as a central device + * - sl_bt_external_bondingdb_data_local_central_inf (0x5): + * Identification info used as a central device + * - sl_bt_external_bondingdb_data_irk (0x6): Identity Resolving Key + * (IRK) of the remote device that is used for resolving its RPA addresses + * when the device is in privacy mode. The value of this type must be + * stored securely. + * - sl_bt_external_bondingdb_data_meta (0x7): Metadata about the + * bonding + * - sl_bt_external_bondingdb_data_gatt_client_config (0x8): The + * remote GATT client characteristic configurations + * - sl_bt_external_bondingdb_data_gatt_client_features (0x9): The + * remote GATT client supported features + * - sl_bt_external_bondingdb_data_gatt_db_hash (0xa): Latest local + * GATT database hash value that the remote client has seen for GATT + * robust caching feature + * @param[in] data_len Length of data in @p data + * @param[in] data Bonding data + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/** @} */ // end addtogroup sl_bt_external_bondingdb + +/** + * @addtogroup sl_bt_resolving_list Address Resolving List + * @{ + * + * @brief Address Resolving List + * + * Provides support for adding and removing devices from the Resolving List in + * controller-based privacy. + * + * Adding a peer device to the Resolving List allows the Bluetooth controller to + * resolve the address when the peer device is using privacy and is transmitting + * with a Resolvable Private Address (RPA). When the controller has resolved an + * address in a received Bluetooth packet such as an advertisement, the + * corresponding event will report the peer device's identity address even if a + * Resolvable Private Address was used over the air. + * + * When the application has added a peer device to the Resolving List, the + * application may use the peer device's identity address in commands such as + * @ref sl_bt_connection_open or @ref sl_bt_sync_scanner_open even if the peer + * device is using privacy and is using a Resolvable Private Address over the + * air. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_resolving_list_add_device_by_bonding_id 0x005d0020 +#define sl_bt_cmd_resolving_list_add_device_by_address_id 0x015d0020 +#define sl_bt_cmd_resolving_list_remove_device_by_bonding_id 0x025d0020 +#define sl_bt_cmd_resolving_list_remove_device_by_address_id 0x035d0020 +#define sl_bt_cmd_resolving_list_remove_all_devices_id 0x045d0020 +#define sl_bt_rsp_resolving_list_add_device_by_bonding_id 0x005d0020 +#define sl_bt_rsp_resolving_list_add_device_by_address_id 0x015d0020 +#define sl_bt_rsp_resolving_list_remove_device_by_bonding_id 0x025d0020 +#define sl_bt_rsp_resolving_list_remove_device_by_address_id 0x035d0020 +#define sl_bt_rsp_resolving_list_remove_all_devices_id 0x045d0020 + +/** + * @brief Specifies the Privacy Mode used for a peer device in the Resolving + * List + */ +typedef enum +{ + sl_bt_resolving_list_privacy_mode_network = 0x0, /**< (0x0) Use Network + Privacy Mode for the + peer device */ + sl_bt_resolving_list_privacy_mode_device = 0x1 /**< (0x1) Use Device Privacy + Mode for the peer device */ +} sl_bt_resolving_list_privacy_mode_t; + +/***************************************************************************//** + * + * Add a device to the Resolving List based on its bonding handle. + * + * This command is not available if the application uses the external bonding + * database provided by the component + * bluetooth_feature_external_bonding_database. In that configuration the + * application can use the command @ref + * sl_bt_resolving_list_add_device_by_address and provide the peer's identity + * address and its Identity Resolving Key (IRK). + * + * @param[in] bonding The bonding handle + * @param[in] privacy_mode @parblock + * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for + * the peer device. Values: + * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network + * Privacy Mode for the peer device + * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device + * Privacy Mode for the peer device + * + * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network + * Privacy Mode for the peer device) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, + uint8_t privacy_mode); + +/***************************************************************************//** + * + * Add a device to the Resolving List based on its identity address and its + * Identity Resolving Key (IRK). + * + * This command is typically only needed when the application uses the external + * bonding database provided by the component + * bluetooth_feature_external_bonding_database. When the application uses the + * built-in bonding database, the command @ref + * sl_bt_resolving_list_add_device_by_bonding is more convenient. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[in] key Identity Resolving Key (IRK) of the peer device in little + * endian format. + * @param[in] privacy_mode @parblock + * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for + * the peer device. Values: + * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network + * Privacy Mode for the peer device + * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device + * Privacy Mode for the peer device + * + * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network + * Privacy Mode for the peer device) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, + uint8_t address_type, + aes_key_128 key, + uint8_t privacy_mode); + +/***************************************************************************//** + * + * Remove a device from the Resolving List based on its bonding handle. + * + * This command is not available if the application uses the external bonding + * database provided by the component + * bluetooth_feature_external_bonding_database. In that configuration the + * application can use the command @ref + * sl_bt_resolving_list_remove_device_by_address and provide the peer's identity + * address. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Remove a device from the Resolving List based on its identity address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove all devices from the Resolving List. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_all_devices(); + +/** @} */ // end addtogroup sl_bt_resolving_list + +/** + * @addtogroup sl_bt_accept_list Filter Accept List + * @{ + * + * @brief Filter Accept List + * + * Provides support for adding and removing devices from the Filter Accept List + * in the Bluetooth controller. + * + * The Filter Accept List allows filtering transmissions from other Bluetooth + * devices so that the local device only receives/accepts transmissions from the + * devices that it's interested in or wants to communicate with. Operations that + * support filtering provide a means to control how the Filter Accept List is + * used: + * - For advertising, use the command @ref sl_bt_advertiser_configure and @p + * flags bits @ref SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to control the + * advertising filter policy + * - For scanning, use the command @ref + * sl_bt_scanner_set_parameters_and_filter to control the scanning filter + * policy + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_accept_list_add_device_by_bonding_id 0x005e0020 +#define sl_bt_cmd_accept_list_add_device_by_address_id 0x015e0020 +#define sl_bt_cmd_accept_list_remove_device_by_bonding_id 0x025e0020 +#define sl_bt_cmd_accept_list_remove_device_by_address_id 0x035e0020 +#define sl_bt_cmd_accept_list_remove_all_devices_id 0x045e0020 +#define sl_bt_rsp_accept_list_add_device_by_bonding_id 0x005e0020 +#define sl_bt_rsp_accept_list_add_device_by_address_id 0x015e0020 +#define sl_bt_rsp_accept_list_remove_device_by_bonding_id 0x025e0020 +#define sl_bt_rsp_accept_list_remove_device_by_address_id 0x035e0020 +#define sl_bt_rsp_accept_list_remove_all_devices_id 0x045e0020 + +/***************************************************************************//** + * + * Add a device to the Filter Accept List based on its bonding handle. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Add a device to the Filter Accept List based on its identity address. + * + * Use the special address type @ref sl_bt_gap_anonymous_address to add an entry + * that matches all advertisements sent with no address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter + * Accept List entry with this type matches all advertisements sent with + * no address. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove a device from the Filter Accept List based on its bonding handle. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Remove a device from the Filter Accept List based on its identity address. + * + * Use the special address type @ref sl_bt_gap_anonymous_address to remove an + * entry that matches all advertisements sent with no address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter + * Accept List entry with this type matches all advertisements sent with + * no address. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove all devices from the Filter Accept List. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_all_devices(); + +/** @} */ // end addtogroup sl_bt_accept_list + +/** + * @addtogroup sl_bt_ota OTA + * @{ + * + * @brief OTA + * + * Commands in this class are used for configuring OTA DFU using the Apploader. + * + * Note that this class is used on EFR series 1 and is not available for series + * 2 devices. The Apploader runs as a Bootloader communication plugin on series + * 2 and the Apploader plugin API supports setting device name and advertising + * data. Other configurations can be implemented in the Apploader plugin + * application space. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_ota_set_device_name_id 0x01100020 +#define sl_bt_cmd_ota_set_advertising_data_id 0x02100020 +#define sl_bt_cmd_ota_set_configuration_id 0x03100020 +#define sl_bt_cmd_ota_set_rf_path_id 0x04100020 +#define sl_bt_rsp_ota_set_device_name_id 0x01100020 +#define sl_bt_rsp_ota_set_advertising_data_id 0x02100020 +#define sl_bt_rsp_ota_set_configuration_id 0x03100020 +#define sl_bt_rsp_ota_set_rf_path_id 0x04100020 + +/***************************************************************************//** + * + * Set the device name to be used during the OTA update. The name is stored in + * the persistent store. Maximum name length is 17 bytes. + * + * Default is "OTA" if a name is not set. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] name_len Length of data in @p name + * @param[in] name OTA device name + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name); + +/***************************************************************************//** + * + * Set advertising packets in OTA. Maximum 31 bytes of data can be set. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] packet_type This value selects whether data is intended for + * advertising packets or scan response packets. + * - 2: OTA advertising packets + * - 4: OTA scan response packets + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Set OTA configuration. The setting is stored in the persistent store. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] flags @parblock + * OTA configuration flags. This value is given as a bitmask. Flags: + * + * Bit 0: Advertising address + * + * - 0: Use public device address + * - 1: Use a random address + * + * Bit 1: Application update version check. Check the version number and + * product ID of the application upgrade before applying. If the version + * number of the current application can't be determined, this implementation + * will assume that it is OK to apply the new image. Note that this is not a + * security feature. + * + * - 0: Disable version check + * - 1: Enable version check + * + * Bit 2 to 31: Reserved + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_configuration(uint32_t flags); + +/***************************************************************************//** + * + * Set RF path antenna for OTA. This command should be used only if the device + * has multiple antenna ports. The setting is stored in the persistent store. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] enable If enabled antenna selection is used in OTA, otherwise + * default antenna is used. + * @param[in] antenna Set antenna used in OTA. Value should be come from + * RAIL_AntennaSel_t enum. See antenna path selection in RAIL + * rail_chip_specific.h. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna); + +/** @} */ // end addtogroup sl_bt_ota + +/** + * @addtogroup sl_bt_coex Coexistence + * @{ + * + * @brief Coexistence + * + * Coexistence BGAPI class. Coexistence interface is enabled and initialized + * with sl_bt_init_coex_hal function. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_coex_set_options_id 0x00200020 +#define sl_bt_cmd_coex_set_parameters_id 0x02200020 +#define sl_bt_cmd_coex_set_directional_priority_pulse_id 0x03200020 +#define sl_bt_cmd_coex_get_parameters_id 0x04200020 +#define sl_bt_cmd_coex_get_counters_id 0x01200020 +#define sl_bt_rsp_coex_set_options_id 0x00200020 +#define sl_bt_rsp_coex_set_parameters_id 0x02200020 +#define sl_bt_rsp_coex_set_directional_priority_pulse_id 0x03200020 +#define sl_bt_rsp_coex_get_parameters_id 0x04200020 +#define sl_bt_rsp_coex_get_counters_id 0x01200020 + +/** + * @brief Coexistence configuration options + */ +typedef enum +{ + sl_bt_coex_option_enable = 0x100, /**< (0x100) Enable coexistence + feature */ + sl_bt_coex_option_tx_abort = 0x400, /**< (0x400) Abort transmission if + grant is denied */ + sl_bt_coex_option_high_priority = 0x800 /**< (0x800) Enable priority signal */ +} sl_bt_coex_option_t; + +/***************************************************************************//** + * + * Configure coexistence options at runtime. + * + * @param[in] mask Bitmask of following coexistence options to change + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal + * @param[in] options Bitmask of following coexistence option values to set + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options); + +/***************************************************************************//** + * + * Configure coexistence parameters. + * + * @param[in] priority Coexistence priority threshold. Coexistence priority is + * toggled if priority is below this value. + * @param[in] request Coexistence request threshold. Coexistence request is + * toggled if priority is below this value. + * @param[in] pwm_period PWM functionality period length in 1 ms units + * @param[in] pwm_dutycycle PWM functionality duty cycle in percentage + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_parameters(uint8_t priority, + uint8_t request, + uint8_t pwm_period, + uint8_t pwm_dutycycle); + +/***************************************************************************//** + * + * Set Directional Priority Pulse Width. + * + * @param[in] pulse Directional priority pulse width in us + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse); + +/***************************************************************************//** + * + * Get the coexistence parameters. + * + * @param[out] priority Coexistence priority threshold. Coexistence priority is + * toggled if priority is below this value. + * @param[out] request Coexistence request threshold. Coexistence request is + * toggled if priority is below this value. + * @param[out] pwm_period PWM functionality period length in 1 ms units + * @param[out] pwm_dutycycle PWM functionality duty cycle in percentage + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, + uint8_t *request, + uint8_t *pwm_period, + uint8_t *pwm_dutycycle); + +/***************************************************************************//** + * + * Read coexistence statistic counters from the device. Response contains the + * list of uint32 type counter values. Counters in the list are in following + * order: low priority requested, high priority requested, low priority denied, + * high priority denied, low-priority TX aborted, and high-priority TX aborted. + * Passing a non-zero value also resets counters. + * + * @param[in] reset Reset counters if parameter value is not zero. + * @param[in] max_counters_size Size of output buffer passed in @p counters + * @param[out] counters_len On return, set to the length of output data written + * to @p counters + * @param[out] counters Coexistence statistic counters + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_get_counters(uint8_t reset, + size_t max_counters_size, + size_t *counters_len, + uint8_t *counters); + +/** @} */ // end addtogroup sl_bt_coex + +/** + * @addtogroup sl_bt_cs Accurate Bluetooth Ranging + * @{ + * + * @brief Accurate Bluetooth Ranging + * + * This class provides commands and events for Accurate Bluetooth Ranging (ABR) + * between Bluetooth devices. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cs_security_enable_id 0x00590020 +#define sl_bt_cmd_cs_set_default_settings_id 0x01590020 +#define sl_bt_cmd_cs_create_config_id 0x02590020 +#define sl_bt_cmd_cs_remove_config_id 0x03590020 +#define sl_bt_cmd_cs_set_channel_classification_id 0x04590020 +#define sl_bt_cmd_cs_set_procedure_parameters_id 0x05590020 +#define sl_bt_cmd_cs_procedure_enable_id 0x06590020 +#define sl_bt_cmd_cs_set_antenna_configuration_id 0x07590020 +#define sl_bt_cmd_cs_read_local_supported_capabilities_id 0x08590020 +#define sl_bt_rsp_cs_security_enable_id 0x00590020 +#define sl_bt_rsp_cs_set_default_settings_id 0x01590020 +#define sl_bt_rsp_cs_create_config_id 0x02590020 +#define sl_bt_rsp_cs_remove_config_id 0x03590020 +#define sl_bt_rsp_cs_set_channel_classification_id 0x04590020 +#define sl_bt_rsp_cs_set_procedure_parameters_id 0x05590020 +#define sl_bt_rsp_cs_procedure_enable_id 0x06590020 +#define sl_bt_rsp_cs_set_antenna_configuration_id 0x07590020 +#define sl_bt_rsp_cs_read_local_supported_capabilities_id 0x08590020 + +/** + * @brief Specifies the role for the device during ABR procedure. + */ +typedef enum +{ + sl_bt_cs_role_initiator = 0x0, /**< (0x0) The device will initiate the + procedure */ + sl_bt_cs_role_reflector = 0x1 /**< (0x1) The device will reciprocate + transmission */ +} sl_bt_cs_role_t; + +/** + * @brief Defines the status of a given role for an ABR capable device. + */ +typedef enum +{ + sl_bt_cs_role_status_disable = 0x0, /**< (0x0) The given role is disabled */ + sl_bt_cs_role_status_enable = 0x1 /**< (0x1) The given role is enabled */ +} sl_bt_cs_role_status_t; + +/** + * @brief Defines the status of a companion signal. + */ +typedef enum +{ + sl_bt_cs_companion_signal_status_disable = 0x0, /**< (0x0) The companion + signal is disabled */ + sl_bt_cs_companion_signal_status_enable = 0x1 /**< (0x1) The companion + signal is enabled */ +} sl_bt_cs_companion_signal_status_t; + +/** + * @brief Defines the ABR procedure state for the device. + */ +typedef enum +{ + sl_bt_cs_procedure_state_disabled = 0x0, /**< (0x0) ABR procedures are + disabled */ + sl_bt_cs_procedure_state_enabled = 0x1 /**< (0x1) ABR procedures are enabled */ +} sl_bt_cs_procedure_state_t; + +/** + * @brief Defines the different modes for ABR steps. + */ +typedef enum +{ + sl_bt_cs_mode_rtt = 0x1, /**< (0x1) Round Trip Time (RTT) measurement */ + sl_bt_cs_mode_pbr = 0x2, /**< (0x2) Phase-Based Ranging (PBR) + measurement */ + sl_bt_cs_submode_disabled = 0xff /**< (0xff) Submode disabled for the + procedure. */ +} sl_bt_cs_mode_t; + +/** + * @brief Defines the Round Trip Time (RTT) payload types used during the ABR + * sequence. + */ +typedef enum +{ + sl_bt_cs_rtt_type_coarse = 0x0, /**< (0x0) RTT Coarse */ + sl_bt_cs_rtt_type_fractional_96_bit_sounding = 0x2 /**< (0x2) RTT Fractional + with 96-bit Sounding + Sequence */ +} sl_bt_cs_rtt_type_t; + +/** + * @brief Specifies the ABR channel selection algorithms. + */ +typedef enum +{ + sl_bt_cs_channel_selection_algorithm_3b = 0x0, /**< (0x0) + Use + Channel + Selection + Algorithm + #3b + for + non-mode + 0 ABR + steps */ + sl_bt_cs_channel_selection_algorithm_3c = 0x1, /**< (0x1) + Use + Channel + Selection + Algorithm + #3c + for + non-mode + 0 ABR + steps */ + sl_bt_cs_channel_selection_algorithm_user_shape_interleaved = 0x2 /**< (0x2) + Use + Interleaved + shape + for + user + specified + channel + sequence */ +} sl_bt_cs_channel_selection_algorithm_t; + +/** + * @brief Specifies the ch3c shapes. + */ +typedef enum +{ + sl_bt_cs_ch3c_shape_hat = 0x0, /**< (0x0) Use Hat shape for user + specified channel sequence */ + sl_bt_cs_chc3_shape_interleaved = 0x1 /**< (0x1) Use Interleaved shape for + user specified channel sequence */ +} sl_bt_cs_ch3c_shape_t; + +/** + * @brief Describes the current status of the procedure or subevents. + */ +typedef enum +{ + sl_bt_cs_done_status_complete = 0x0, /**< (0x0) All results + complete for the + ABR procedure or + subevent */ + sl_bt_cs_done_status_partial_results_continue = 0x1, /**< (0x1) Partial + results with more + to follow */ + sl_bt_cs_done_status_current_aborted = 0xfe, /**< (0xfe) Current ABR + procedure or + subevent aborted */ + sl_bt_cs_done_status_all_aborted = 0xff /**< (0xff) Current and + all subsequent + subevents in the + procedure aborted */ +} sl_bt_cs_done_status_t; + +/** + * @brief Describes the abort reasons for ABR procedures and subevents and is + * represented by 4 bits in a byte + */ +typedef enum +{ + sl_bt_cs_abort_reason_no_abort = 0x0, /**< (0x0) Not aborted */ + sl_bt_cs_abort_reason_host_request = 0x1, /**< (0x1) Local or remote + host request */ + sl_bt_cs_abort_reason_insufficient_channels = 0x2, /**< (0x2) Filtered channel + has less than 15 + channels */ + sl_bt_cs_abort_reason_no_map_update = 0x3, /**< (0x3) Channel map + update instant has + passed */ + sl_bt_cs_abort_reason_unspecified = 0xf /**< (0xf) Unspecified + reasons for abortion */ +} sl_bt_cs_abort_reason_t; + +/** + * @brief Specifies the role for the device during ABR procedure. + */ +typedef enum +{ + sl_bt_cs_config_state_removed = 0x0, /**< (0x0) The ABR device configuration + is removed */ + sl_bt_cs_config_state_created = 0x1 /**< (0x1) The ABR device configuration + is created */ +} sl_bt_cs_config_state_t; + +/** + * @addtogroup sl_bt_evt_cs_security_enable_complete sl_bt_evt_cs_security_enable_complete + * @{ + * @brief Indicates that a locally initiated ABR security start procedure has + * completed or the local controller has responded to a channel security request + * from the remote controller + */ + +/** @brief Identifier of the security_enable_complete event */ +#define sl_bt_evt_cs_security_enable_complete_id 0x005900a0 + +/***************************************************************************//** + * @brief Data structure of the security_enable_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_security_enable_complete_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_cs_security_enable_complete_s sl_bt_evt_cs_security_enable_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_security_enable_complete + +/** + * @addtogroup sl_bt_evt_cs_config_complete sl_bt_evt_cs_config_complete + * @{ + * @brief Indicates that a locally initiated ABR configuration procedure has + * completed or the local controller has responded to an ABR configuration + * request from the remote controller + */ + +/** @brief Identifier of the config_complete event */ +#define sl_bt_evt_cs_config_complete_id 0x015900a0 + +/***************************************************************************//** + * @brief Data structure of the config_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_config_complete_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t config_id; /**< ABR configuration + identifier. + - Range: 0 to 3 */ + uint16_t status; /**< SL_STATUS_OK if + successful. Error code + otherwise. */ + uint8_t config_state; /**< Enum @ref + sl_bt_cs_config_state_t. + ABR configuration state + Values: + - sl_bt_cs_config_state_removed + (0x0): The ABR + device configuration + is removed + - sl_bt_cs_config_state_created + (0x1): The ABR + device configuration + is created */ + uint8_t main_mode_type; /**< Enum @ref + sl_bt_cs_mode_t. Main + mode type. Values: + - sl_bt_cs_mode_rtt + (0x1): Round Trip + Time (RTT) + measurement + - sl_bt_cs_mode_pbr + (0x2): + Phase-Based Ranging + (PBR) measurement + - sl_bt_cs_submode_disabled + (0xff): Submode + disabled for the + procedure. */ + uint8_t sub_mode_type; /**< Enum @ref + sl_bt_cs_mode_t. Sub mode + type. Values: + - sl_bt_cs_mode_rtt + (0x1): Round Trip + Time (RTT) + measurement + - sl_bt_cs_mode_pbr + (0x2): + Phase-Based Ranging + (PBR) measurement + - sl_bt_cs_submode_disabled + (0xff): Submode + disabled for the + procedure. */ + uint8_t min_main_mode_steps; /**< Minimum number of ABR + main mode steps to be + executed prior to a sub + mode step. + - Range: 1 to 160 */ + uint8_t max_main_mode_steps; /**< Maximum number of ABR + main mode steps to be + executed prior to a sub + mode step. + - Range: 1 to 160 */ + uint8_t main_mode_repetition; /**< Number of main mode steps + taken from the end of the + last ABR subevent to be + repeated at the beginning + of the current ABR + subevent directly after + the last Mode 0 step of + that event. + - Range: 0 to 3 */ + uint8_t mode_calibration_steps; /**< Number of calibration + mode steps to be included + at the beginning of the + test ABR subevent. + - Range: 1 to 3 */ + uint8_t role; /**< Enum @ref + sl_bt_cs_role_t. Device + role during the ABR + procedure Values: + - sl_bt_cs_role_initiator + (0x0): The device + will initiate the + procedure + - sl_bt_cs_role_reflector + (0x1): The device + will reciprocate + transmission */ + uint8_t rtt_type; /**< Enum @ref + sl_bt_cs_rtt_type_t. RTT + payload type used in the + ABR procedure Values: + - sl_bt_cs_rtt_type_coarse + (0x0): RTT Coarse + - sl_bt_cs_rtt_type_fractional_96_bit_sounding + (0x2): RTT + Fractional with + 96-bit Sounding + Sequence */ + uint8_t cs_sync_phy; /**< Enum @ref + sl_bt_gap_phy_t. Used PHY + for ABR SYNC exchanges + during a procedure + Values: + - sl_bt_gap_phy_1m + (0x1): 1M PHY */ + sl_bt_cs_channel_map_t channel_map; /**< A fixed length byte array + of 10 bytes consisting of + 79 1-bit fields. + + The nth field (in the + range 0 to 78) contains + the value for the ABR + channel index n. + + - Bit value 0: Channel + n is disabled + - Bit value 1: Channel + n is enabled + + The rest of most + significant bits are + reserved for future use + and must be set to 0. + Channels n = 0, 1, 23, + 24, 25, 77 and 78 shall + be ignored and not used + for ABR. At least 15 + channels shall be marked + as used. */ + uint8_t channel_map_repetition; /**< Number of times the + channel_map field will be + cycled through for + non-Mode 0 steps within a + ABR procedure. + - Range: 0x01 to 0xFF */ + uint8_t channel_selection_type; /**< Enum @ref + sl_bt_cs_channel_selection_algorithm_t. + ABR algorithm to be used + during the procedure for + non-mode 0 steps Value: + - sl_bt_cs_channel_selection_algorithm_3b + (0x0): Use + Channel Selection + Algorithm #3b for + non-mode 0 ABR steps + - sl_bt_cs_channel_selection_algorithm_3c + (0x1): Use + Channel Selection + Algorithm #3c for + non-mode 0 ABR steps + - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved + (0x2): Use + Interleaved shape for + user specified + channel sequence */ + uint8_t ch3c_shape; /**< Enum @ref + sl_bt_cs_ch3c_shape_t. + Shape for user-specified + channel sequence Values: + - sl_bt_cs_ch3c_shape_hat + (0x0): Use Hat + shape for user + specified channel + sequence + - sl_bt_cs_chc3_shape_interleaved + (0x1): Use + Interleaved shape for + user specified + channel sequence */ + uint8_t ch3c_jump; /**< Number of channels + skipped in each rising + and falling sequence + - Range: 0x03 to 0x08 */ + uint8_t companion_signal_enable; /**< Enum @ref + sl_bt_cs_companion_signal_status_t. + Enabled or disabled + companion signal status + Values: + - sl_bt_cs_companion_signal_status_disable + (0x0): The + companion signal is + disabled + - sl_bt_cs_companion_signal_status_enable + (0x1): The + companion signal is + enabled */ + uint8_t ip1_time_us; /**< Interlude time in + microseconds between the + RTT packets. Values: + 0x0A, 0x14, 0x1E, 0x28, + 0x32, 0x3C, 0x50, or + 0x91. All other values + are reserved for future + use. */ + uint8_t ip2_time_us; /**< Interlude time in + microseconds between the + CS tones. Values: 0x0A, + 0x14, 0x1E, 0x28, 0x32, + 0x3C, 0x50, or 0x91. All + other values are reserved + for future use. */ + uint8_t fcs_time_us; /**< Time in microseconds for + frequency changes. + Values: 0x0F, 0x14, 0x1E, + 0x28, 0x32, 0x3C, 0x50, + 0x64, 0x78, or 0x96. All + other values are reserved + for future use. */ + uint8_t pm_time_us; /**< Time in microseconds for + the phase measurement + period of the CS tones. + Values: 0x0A, 0x14, or + 0x28. All other values + are reserved for future + use. */ +}); + +typedef struct sl_bt_evt_cs_config_complete_s sl_bt_evt_cs_config_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_config_complete + +/** + * @addtogroup sl_bt_evt_cs_procedure_enable_complete sl_bt_evt_cs_procedure_enable_complete + * @{ + * @brief Indicates the controller has scheduled a new ABR procedure + * measurement, as a result of @ref sl_bt_cs_procedure_enable command or + * disabled an ongoing, as a result of @ref sl_bt_cs_procedure_enable command. + */ + +/** @brief Identifier of the procedure_enable_complete event */ +#define sl_bt_evt_cs_procedure_enable_complete_id 0x025900a0 + +/***************************************************************************//** + * @brief Data structure of the procedure_enable_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_procedure_enable_complete_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t config_id; /**< ABR configuration identifier. + - Range: 0 to 3 */ + uint16_t status; /**< SL_STATUS_OK if successful. Error code + otherwise. */ + uint8_t state; /**< Enum @ref sl_bt_cs_procedure_state_t. + ABR procedure enabled or disabled + Values: + - sl_bt_cs_procedure_state_disabled + (0x0): ABR procedures are + disabled + - sl_bt_cs_procedure_state_enabled + (0x1): ABR procedures are + enabled */ + uint8_t antenna_config; /**< Antenna configuration index + - Range: 0 to 7 */ + int8_t tx_power; /**< Transmit power level used in the + transmission. Units: dBm. + - Range: -127 to +20 + - Value: 0x07F. Transmit power level + is unavailable */ + uint32_t subevent_len; /**< Duration for each subevent in + microseconds + - Range: 1250 μs to 4 s */ + uint8_t subevents_per_interval; /**< Number of subevents anchored off the + same ACL connection event + - Range: 1 to 16 */ + uint16_t subevent_interval; /**< Duration in microseconds between + consecutive ABR subevents anchored off + the same ACL connection event. Units: + 0.625 ms. */ + uint16_t event_interval; /**< Number of ACL connection events between + consecutive ABR event anchor points */ + uint16_t procedure_interval; /**< Number of ACL connection events between + consecutive ABR procedure anchor points */ + uint16_t procedure_count; /**< Number of procedures to continue until + disabled. Maximum number of procedures + to be scheduled. + - Range: 0x01 to 0xFFFF. */ +}); + +typedef struct sl_bt_evt_cs_procedure_enable_complete_s sl_bt_evt_cs_procedure_enable_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_procedure_enable_complete + +/** + * @addtogroup sl_bt_evt_cs_result sl_bt_evt_cs_result + * @{ + * @brief Reports results of every ABR subevent within the ABR procedure + */ + +/** @brief Identifier of the result event */ +#define sl_bt_evt_cs_result_id 0x035900a0 + +/***************************************************************************//** + * @brief Data structure of the result event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_result_s +{ + uint8_t connection; /**< Connection handle. Returns a + SL_BT_INVALID_CONNECTION_HANDLE (0xFF) + when triggered as a result of @ref + sl_bt_cs_test_start command */ + uint8_t config_id; /**< ABR configuration identifier + - Range: 0 to 3 */ + uint16_t start_acl_conn_event; /**< Starting an ACL connection event count + for the results reported in the event. + This is reported only in the first + subevent in the procedure. For + subsequent subevents, this value is + set to 0. */ + uint16_t procedure_counter; /**< Indicates the associated ABR procedure + count for the results reported in this + event */ + int16_t frequency_compensation; /**< Frequency compensation value. Units: + 0.01 ppm (15-bit signed integer). + - Range: -10000 to 10000 + - Value: 0xC000. Frequency + compensation value is not + available or the role is not + initiator. This is reported only + in the first subevent in the + procedure. For subsequent + subevents, this value is set to 0. */ + uint8_t procedure_done_status; /**< Enum @ref sl_bt_cs_done_status_t. + Current status of the ABR procedure + Values: + - sl_bt_cs_done_status_complete + (0x0): All results complete + for the ABR procedure or subevent + - sl_bt_cs_done_status_partial_results_continue + (0x1): Partial results with + more to follow + - sl_bt_cs_done_status_current_aborted + (0xfe): Current ABR procedure + or subevent aborted + - sl_bt_cs_done_status_all_aborted + (0xff): Current and all + subsequent subevents in the + procedure aborted */ + uint8_t subevent_done_status; /**< Enum @ref sl_bt_cs_done_status_t. + Current status of the ABR subevent + Values: + - sl_bt_cs_done_status_complete + (0x0): All results complete + for the ABR procedure or subevent + - sl_bt_cs_done_status_partial_results_continue + (0x1): Partial results with + more to follow + - sl_bt_cs_done_status_current_aborted + (0xfe): Current ABR procedure + or subevent aborted + - sl_bt_cs_done_status_all_aborted + (0xff): Current and all + subsequent subevents in the + procedure aborted */ + uint8_t abort_reason; /**< Enum @ref sl_bt_cs_abort_reason_t. + Indicates the abort reason when the + procedure_done_status or + subevent_done_status is set to 0xF, + otherwise the default value is set to + zero. The first 4 bits are related to + the procedure abort reasons and the + last 4 bits are related to the + subevent done. Values: + - sl_bt_cs_abort_reason_no_abort + (0x0): Not aborted + - sl_bt_cs_abort_reason_host_request + (0x1): Local or remote host + request + - sl_bt_cs_abort_reason_insufficient_channels + (0x2): Filtered channel has + less than 15 channels + - sl_bt_cs_abort_reason_no_map_update + (0x3): Channel map update + instant has passed + - sl_bt_cs_abort_reason_unspecified + (0xf): Unspecified reasons for + abortion */ + int8_t reference_power_level; /**< Reference power level used by the + transmission. Units: dBm. + - Range: -127 to 20 + - Value: 0x07F. The reference power + level is not applicable */ + uint8_t num_antenna_paths; /**< Number of antenna paths supported by + the local controller for the ABR tone + exchanges. + - Range: 1 to 4. The number of + antenna paths used during the + phase measurement stage of the ABR + step + - Value: 0. Phase measurement does + not occur during the ABR step, + therefore ignored */ + uint8_t num_steps; /**< Number of steps in the ABR subevent + for which results are reported. + - Range: 1 to 160 */ + uint8array data; /**< The result data is structured as + follows: + - step_status: 1 octet for each + num_steps. 0x00 for step scheduled + and reported. 0xFE for step + aborted. + - step_mode: 1 octet for each + num_steps. Mode type. Range 0 to + 3. + - step_channel: 1 octet for each + num_steps. Channel index. Range 1 + to 78. + - step_data_length: 1 octet for each + num_steps. Length of mode and role + specific information being + reported. Range 0x00 to 0xFF. + - step_data: step_data_length octet + for each corresponding steps in + num_steps. */ +}); + +typedef struct sl_bt_evt_cs_result_s sl_bt_evt_cs_result_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_result + +/***************************************************************************//** + * + * Start or restart ABR security start procedure for the specified connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_security_enable_complete - Triggered when ABR security + * start procedure has completed. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_security_enable(uint8_t connection); + +/***************************************************************************//** + * + * Set the default ABR settings for the specified connection. By default, all + * roles are disabled and the antenna is set to 1. + * + * @param[in] connection Connection handle + * @param[in] initiator_status Enum @ref sl_bt_cs_role_status_t. Enable or + * disable status of the Initiator role. Values: + * - sl_bt_cs_role_status_disable (0x0): The given role is disabled + * - sl_bt_cs_role_status_enable (0x1): The given role is enabled + * @param[in] reflector_status Enum @ref sl_bt_cs_role_status_t. Enable or + * disable status of the Reflector role. Values: + * - sl_bt_cs_role_status_disable (0x0): The given role is disabled + * - sl_bt_cs_role_status_enable (0x1): The given role is enabled + * @param[in] antenna_identifier Antenna identifier to be used for ABR sync + * packets. + * - Range: 1 to 4 + * @param[in] max_tx_power Maximum transmit power level to be used in all ABR + * transmissions. Units: dBm. + * - Range: -127 to +20 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, + uint8_t initiator_status, + uint8_t reflector_status, + uint8_t antenna_identifier, + int8_t max_tx_power); + +/***************************************************************************//** + * + * Create a new ABR configuration in the local and remote controller. The role + * used in this command must be enabled prior to issuing this command using @ref + * sl_bt_cs_set_default_settings command. + * + * @param[in] connection The connection handle + * @param[in] config_id ABR configuration identifier. + * - Range: 0 to 3 + * @param[in] create_context Defines in which device the created configuration + * will be written + * - Value: 0x00. Write ABR configuration in the local controller only + * - Value: 0x01. Write ABR configuration in both the local and remote + * controller using a configuration procedure + * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] min_main_mode_steps Minimum number of ABR main mode steps to be + * executed prior to a sub mode step. + * - Range: 1 to 160 + * @param[in] max_main_mode_steps Maximum number of ABR main mode steps to be + * executed prior to a sub mode step. + * - Range: 1 to 160 + * @param[in] main_mode_repetition Number of main mode steps taken from the end + * of the last ABR subevent to be repeated at the beginning of the current ABR + * subevent directly after the value r last Mode 0 step of that event. + * - Range: 0 to 3 + * @param[in] mode_calibration_steps Number of Mode 0 steps to be included at + * the beginning of the test ABR subevent + * - Range: 1 to 3 + * @param[in] role Enum @ref sl_bt_cs_role_t. Device's role during the ABR + * procedure Values: + * - sl_bt_cs_role_initiator (0x0): The device will initiate the + * procedure + * - sl_bt_cs_role_reflector (0x1): The device will reciprocate + * transmission + * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in + * the ABR procedure Values: + * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse + * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT + * Fractional with 96-bit Sounding Sequence + * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC + * exchanges during a procedure Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * @param[in] channel_map @parblock + * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. + * + * The nth such field (in the range 0 to 78) contains the value for the ABR + * channel index n. + * + * - Bit value 0: Channel n is disabled + * - Bit value 1: Channel n is enabled + * + * The rest of most significant bits are reserved for future use and must be + * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not + * used for ABR. At least 15 channels shall be marked as used. + * @endparblock + * @param[in] channel_map_repetition Number of times the channel_map field will + * be cycled through for non-Mode 0 steps within an ABR procedure. + * - Range: 0x01 to 0xFF + * @param[in] channel_selection_type Enum @ref + * sl_bt_cs_channel_selection_algorithm_t. Channel selection algorithm Values: + * - sl_bt_cs_channel_selection_algorithm_3b (0x0): Use Channel + * Selection Algorithm #3b for non-mode 0 ABR steps + * - sl_bt_cs_channel_selection_algorithm_3c (0x1): Use Channel + * Selection Algorithm #3c for non-mode 0 ABR steps + * - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved + * (0x2): Use Interleaved shape for user specified channel sequence + * @param[in] ch3c_shape Enum @ref sl_bt_cs_ch3c_shape_t. Ch3c shape Values: + * - sl_bt_cs_ch3c_shape_hat (0x0): Use Hat shape for user specified + * channel sequence + * - sl_bt_cs_chc3_shape_interleaved (0x1): Use Interleaved shape for + * user specified channel sequence + * @param[in] ch3c_jump Number of channels skipped in each rising and falling + * sequence. + * - Range: 2 to 8 + * @param[in] companion_signal_state Enum @ref + * sl_bt_cs_companion_signal_status_t. Companion device's signal status + * Values: + * - sl_bt_cs_companion_signal_status_disable (0x0): The companion + * signal is disabled + * - sl_bt_cs_companion_signal_status_enable (0x1): The companion + * signal is enabled + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration + * procedure completed + * + ******************************************************************************/ +sl_status_t sl_bt_cs_create_config(uint8_t connection, + uint8_t config_id, + uint8_t create_context, + uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t min_main_mode_steps, + uint8_t max_main_mode_steps, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + const sl_bt_cs_channel_map_t *channel_map, + uint8_t channel_map_repetition, + uint8_t channel_selection_type, + uint8_t ch3c_shape, + uint8_t ch3c_jump, + uint8_t companion_signal_state); + +/***************************************************************************//** + * + * Remove an ABR configuration from the local controller. + * + * @param[in] connection Connection handle + * @param[in] config_id ABR configuration identifier + * - Range: 0 to 3 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration + * procedure is completed + * + ******************************************************************************/ +sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id); + +/***************************************************************************//** + * + * Update the channel classification for ABR. This classification persists until + * overwritten with a subsequent command or until the system is reset. + * + * @param[in] channel_map @parblock + * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. + * + * The nth field (in the range 0 to 78) contains the value for the link layer + * channel index n. + * + * - Bit value 0: Channel n is disabled. + * - Bit value 1: Channel n is enabled. + * + * The rest of most significant bits are reserved for future use and must be + * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not + * used for ABR. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map); + +/***************************************************************************//** + * + * Set the parameters for scheduling ABR procedures with the remote device. + * + * @param[in] connection The connection handle + * @param[in] config_id ABR configuration identifier. + * - Range: 0 to 3. + * @param[in] max_procedure_len Maximum duration for each measurement procedure. + * Value in units of 0.625 ms. + * - Range: 0x0001 to 0xFFFF. + * - Time: N x 0.625ms. N being the input. + * - Time range: 0.625 ms to 40.959375 s. + * @param[in] min_procedure_interval Minimum duration in number of connection + * events between consecutive measurement procedure. + * - Range: 0x01 to 0xFFFF. + * @param[in] max_procedure_interval Maximum duration in number of connection + * events between consecutive measurement procedure. + * - Range: 0x01 to 0xFFFF. + * @param[in] max_procedure_count Maximum number of ABR procedures to be + * scheduled + * - Range: 0x01 to 0xFFFF: Maximum number of procedures to be scheduled. + * - Value: 0x00. Procedures to continue until disabled. + * @param[in] min_subevent_len Minimum suggested duration for each ABR subevent. + * Units: microseconds. + * - Range: 0x01 to 0xFFFFFF + * - Time range: 1250 us to 4s + * @param[in] max_subevent_len Maximum suggested duration for each ABR subevent. + * Units: microseconds. + * - Range: 0x01 to 0xFFFFFF + * - Time range: 1250 us to 4s + * @param[in] tone_antenna_config_selection Antenna configuration index + * - Range: 0 to 7 + * @param[in] phy Enum @ref sl_bt_gap_phy_t. PHY on which the ABR transmission + * will take place Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports + * @param[in] tx_pwr_delta Transmit power delta. Units: dB. + * - Value: 0x80. Host does not have a recommendation for transmit power + * delta + * @param[in] preferred_peer_antenna Preferred peer-ordered antenna elements to + * be used by the remote device for the antenna configuration denoted by the + * tone antenna config selection. + * - Bit 0: Use first ordered antenna element + * - Bit 1: Use second ordered antenna element + * - Bit 2: Use third ordered antenna element + * - Bit 3: Use fourth ordered antenna element + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, + uint8_t config_id, + uint16_t max_procedure_len, + uint16_t min_procedure_interval, + uint16_t max_procedure_interval, + uint16_t max_procedure_count, + uint32_t min_subevent_len, + uint32_t max_subevent_len, + uint8_t tone_antenna_config_selection, + uint8_t phy, + int8_t tx_pwr_delta, + uint8_t preferred_peer_antenna); + +/***************************************************************************//** + * + * Enable or disable scheduling ABR procedures with the remote device. + * + * @param[in] connection The connection handle + * @param[in] enable Enum @ref sl_bt_cs_procedure_state_t. Enabled or disabled + * ABR procedure state. Values: + * - sl_bt_cs_procedure_state_disabled (0x0): ABR procedures are + * disabled + * - sl_bt_cs_procedure_state_enabled (0x1): ABR procedures are + * enabled + * @param[in] config_id ABR configuration identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_procedure_enable_complete - Triggered when local + * controller has scheduled or disabled an ABR procedure measurement + * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to + * report for every ABR event within the ABR procedure + * + ******************************************************************************/ +sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, + uint8_t enable, + uint8_t config_id); + +/***************************************************************************//** + * + * Set the antenna configuration for the ABR feature. + * + * @param[in] antenna_element_offset_len Length of data in @p + * antenna_element_offset + * @param[in] antenna_element_offset Offset of each antenna, each element is a + * signed 16-bit integer stored in two consecutive bytes in little-endian + * order. Units: 1 cm. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, + const uint8_t* antenna_element_offset); + +/***************************************************************************//** + * + * Read the ABR capabilities of the local controller. + * + * @param[out] num_config The number of ABR configurations supported per + * connection. + * - Range: 0x01-0x04 + * @param[out] max_consecutive_procedures The maximum number of consecutive ABR + * procedures supported. + * - 0x00: Fixed number of consecutive procedures and for an + * indefinite number of procedures until termination + * - 0x0001-0xFFFF: Maximum number of consecutive procedures + * supported + * @param[out] num_antennas The number of antenna elements available for ABR + * tone exchanges. + * - Range: 0x01-0x04 + * @param[out] max_antenna_paths The maximum number of antenna paths supported. + * - Range: 0x01-0x04 + * @param[out] roles This value is a bitmask of flags to indicate which ABR + * roles are supported by the controller. Flags: + * - 0x01, bit 0: Initiator role + * - 0x02, bit 1: Reflector role + * @param[out] optional_modes This value is a bitmask of flags to indicate which + * Optional ABR modes are supported. Flags: + * - 0x02, bit 0: Mode 3 is supported + * @param[out] rtt_capability This value is a bitmask of flags to indicate which + * Round Trip Time (RTT) ABR capabilities accuracy requirement in @p + * rtt_aa_only_n, @p rtt_sounding_n, and @p rtt_random_payload. Flags: + * - 0x01, bit 0: 10 ns time-of-flight (ToF) precision requirement + * for @p rtt_aa_only if set; otherwise 150 ns ToF + * - 0x02, bit 1: 10 ns ToF precision requirement for @p rtt_sounding + * if set; otherwise 150 ns ToF + * - 0x04, bit 2: 10 ns ToF precision requirement for @p + * rtt_random_payload if set; otherwise 150 ns ToF + * @param[out] rtt_aa_only RTT Access Address(AA) is supported by the controller + * - 0x00: RTT AA Only is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] rtt_sounding RTT Sounding is supported by the controller + * - 0x00: RTT Sounding is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] rtt_random_payload RTT Random Payload is supported by the + * controller + * - 0x00: RTT Random Payload is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] optional_cs_sync_phys This value is a bitmask of flags to + * indicate which ABR SYNC packages supported in an specific PHY. Flags: + * - 0x02, bit 1: LE 2M PHY ABR SYNC packages are supported + * @param[out] optional_subfeatures This value is a bitmask of flags to indicate + * which Optional ABR subfeatures supported is supported. Flags: + * - 0x01, bit 0: ABR Companion Signal is supported + * - 0x02, bit 1: ABR with zero Frequency Actuation Error relative to + * Mode 0 transmissions in reflector role is supported + * - 0x04, bit 2: ABR Channel Selection Algorithm #3c is supported + * - 0x08, bit 3: ABR phase-based ranging from a sounding sequence is + * supported + * @param[out] optional_t_ip1_times This value is a bitmask of flags to indicate + * which Time for Interlude Period 1 (IP1) supported is supported. Flags: + * - 0x0001, bit 0: Time durantion of 10 microseconds is supported + * - 0x0002, bit 1: Time durantion of 20 microseconds is supported + * - 0x0004, bit 2: Time durantion of 30 microseconds is supported + * - 0x0008, bit 3: Time durantion of 40 microseconds is supported + * - 0x0010, bit 4: Time durantion of 50 microseconds is supported + * - 0x0020, bit 5: Time durantion of 60 microseconds is supported + * - 0x0040, bit 6: Time durantion of 80 microseconds is supported + * @param[out] optional_t_ip2_times This value is a bitmask of flags to indicate + * which Time for Interlude Period 2 (IP2) supported is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * - 0x0004, bit 2: Time duration of 30 microseconds is supported + * - 0x0008, bit 3: Time duration of 40 microseconds is supported + * - 0x0010, bit 4: Time duration of 50 microseconds is supported + * - 0x0020, bit 5: Time duration of 60 microseconds is supported + * - 0x0040, bit 6: Time duration of 80 microseconds is supported + * @param[out] optional_t_fcs_times This value is a bitmask of flags to indicate + * which Time for Frequency Change Spaceing (FCS) is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * - 0x0004, bit 2: Time duration of 30 microseconds is supported + * - 0x0008, bit 3: Time duration of 40 microseconds is supported + * - 0x0010, bit 4: Time duration of 50 microseconds is supported + * - 0x0020, bit 5: Time duration of 60 microseconds is supported + * - 0x0040, bit 6: Time duration of 80 microseconds is supported + * - 0x0100, bit 7: Time duration of 100 microseconds is supported + * - 0x0200, bit 8: Time duration of 120 microseconds is supported + * @param[out] optional_t_pm_times This value is a bitmask of flags to indicate + * which Time for Phase Measurement (PM) supported is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * @param[out] t_sw_times Time in microseconds for the antenna switch period of + * the ABR tones. + * - Values: 0x02, 0x02, 0x04 and 0x0A + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, + uint16_t *max_consecutive_procedures, + uint8_t *num_antennas, + uint8_t *max_antenna_paths, + uint8_t *roles, + uint8_t *optional_modes, + uint8_t *rtt_capability, + uint8_t *rtt_aa_only, + uint8_t *rtt_sounding, + uint8_t *rtt_random_payload, + uint8_t *optional_cs_sync_phys, + uint16_t *optional_subfeatures, + uint16_t *optional_t_ip1_times, + uint16_t *optional_t_ip2_times, + uint16_t *optional_t_fcs_times, + uint16_t *optional_t_pm_times, + uint8_t *t_sw_times); + +/** @} */ // end addtogroup sl_bt_cs + +/** + * @addtogroup sl_bt_cs_test Accurate Bluetooth Ranging Test + * @{ + * + * @brief Accurate Bluetooth Ranging Test + * + * This class provides optional test commands and events for ABR between + * Bluetooth devices. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cs_test_start_id 0x005a0020 +#define sl_bt_rsp_cs_test_start_id 0x005a0020 + +/** + * @brief Defines tone extension for ABR test + */ +typedef enum +{ + sl_bt_cs_test_tone_extension_both_without = 0x0, /**< (0x0) Initiator and + Reflector tones + sent without tone + extension */ + sl_bt_cs_test_tone_extension_reflector_without = 0x1, /**< (0x1) Initiator + tone sent with + extension; + Reflector tone sent + without extension */ + sl_bt_cs_test_tone_extension_initiator_without = 0x2, /**< (0x2) Initiator + tone sent without + extension; + Reflector tone sent + with extension */ + sl_bt_cs_test_tone_extension_both_with = 0x3, /**< (0x3) Initiator and + Reflector tones + sent with extension */ + sl_bt_cs_test_tone_extension_round_robin = 0x4 /**< (0x4) Loop through + values 0x00 to 0x03 */ +} sl_bt_cs_test_tone_extension_t; + +/** + * @brief This defines sounding sequence marker for ABR test + */ +typedef enum +{ + sl_bt_cs_test_sounding_sequence_marker_1 = 0x0, /**< (0x0) Use + 0b0011 as the + Sounding + Sequence marker */ + sl_bt_cs_test_sounding_sequence_marker_2 = 0x1, /**< (0x1) Use + 0b1100 as the + Sounding + Sequence marker */ + sl_bt_cs_test_sounding_sequence_marker_round_robin = 0x2 /**< (0x2) Loop + through 0b0011 + and 0b1100 */ +} sl_bt_cs_test_sounding_sequence_marker_t; + +/***************************************************************************//** + * + * Start a single ABR procedure using the given configuration. The reflector + * must be initialized before starting the initiator. To stop an ongoing test, + * use the @ref sl_bt_test_dtm_end command. + * + * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values : + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] main_mode_repetition Number of main mode steps taken from the end + * of the last ABR subevent to be repeated at the beginning of the current ABR + * subevent directly after the last Mode 0 step of that event. + * - Range: 0 to 3 + * @param[in] mode_calibration_steps Number of calibration mode steps to be + * included at the beginning of the test ABR subevent + * - Range: 1 to 3 + * @param[in] role Enum @ref sl_bt_cs_role_t. Role during ABR procedure Values: + * - sl_bt_cs_role_initiator (0x0): The device will initiate the + * procedure + * - sl_bt_cs_role_reflector (0x1): The device will reciprocate + * transmission + * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in + * the ABR procedure Values: + * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse + * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT + * Fractional with 96-bit Sounding Sequence + * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC + * exchanges during a procedure Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports + * @param[in] antenna_selection Antenna Identifier to be used for RTT packets + * - Range: 1 to 4 + * @param[in] subevent_len ABR subevent length in units of microseconds. + * @param[in] subevent_interval Interval between the start of two consecutive + * ABR events. Units: 0.625 ms. + * - Value: 0x0000. Single ABR subevent + * @param[in] tx_power Transmit power level for the transmission. Units: dBm. + * - Range: -127 to +20 + * - Value: 0x7E. Set transmitter to minimum transmit power level + * - Value: 0x7F. Set transmitter to maximum transmit power level + * @param[in] t_ip1_time Idle time in microseconds between the RTT packets + * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 + * @param[in] t_ip2_time Interlude time in microseconds between the ABR tones + * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 + * @param[in] t_fcs_time Time in microseconds for frequency changes + * - Values: 15, 20, 30, 40, 50, 60, 80, 100, 120 or 150 + * @param[in] t_pm_time Time in microseconds for the phase measurement period of + * the ABR tones + * - Values: 10, 20 or 40 + * @param[in] t_sw_time Time in microseconds for the antenna switch period of + * the ABR tones + * - Values: 0, 1, 2, 4 or 10 + * @param[in] tone_antenna_config Antenna Configuration Index used during + * antenna switching + * - Range: 0 to 7 + * @param[in] companion_signal_state Enum @ref + * sl_bt_cs_companion_signal_status_t. Enable or disable status of the + * companion signal. Values: + * - sl_bt_cs_companion_signal_status_disable (0x0): The companion + * signal is disabled + * - sl_bt_cs_companion_signal_status_enable (0x1): The companion + * signal is enabled + * @param[in] drbg_nonce Antenna Configuration Index used during antenna + * switching + * - Range: 0 to 7 + * @param[in] override_config Configuration of the parameters in + * override_parameters + * - Bit 0: The channel sequence for the subevent is determined by the + * values of channel map repetition, channel length, and channel + * parameters. + * - Bit 2: The number of main mode ABR steps to be executed before a sub + * mode ABR step during the ABR procedure is determined by the value of + * main mode steps parameter. + * - Bit 3: The transmission of tone extensions within each Mode 2 or Mode 3 + * step is determined by the value of T_PM_Tone_Ext parameter. + * - Bit 4: The Tone antenna permutation index for each Mode 2 or Mode 3 + * step is determined by the value of Tone_Antenna_Permutation parameter. + * - Bit 5: The ABR Access Address of all packets sent by the initiator is + * determined by ABR_SYNC_AA_Initiator parameter. The ABR Access Address + * of all packets sent by the reflector is determined by + * ABR_SYNC_AA_Reflector parameter. + * B + * - Bit 6: The Marker positions for each ABR SYNC packet with a marker is + * determined by the value of SS_Marker1_Position and SS_Marker2_Position + * parameters. + * - Bit 7: The Marker value for each marker within a ABR SYNC packet is + * determined by SS_Marker_Value parameter. + * - Bit 8: The payload of the ABR SYNC packet is determined by the value of + * ABR_SYNC_Payload_Pattern parameter. + * - Bit 10: Stable Phase test + * @param[in] override_parameters_len Length of data in @p override_parameters + * @param[in] override_parameters Variable set of parameters which are present + * dependent on the bits set in the override config parameter. + * - Bit 0: channel_map_repetition, channel_length and channel + * - Bit 2: main_mode_steps + * - Bit 3: t_pm_tone_ext + * - Bit 4: tone_antenna_permutation + * - Bit 5: aa_initiator and aa_reflector + * - Bit 6: ss_marker1_position and ss_marker2_position + * - Bit 7: ss_marker_value + * - Bit 8: ABR_SYNC_Payload_Pattern and ABR_SYNC_User_Payload + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to + * report for every ABR subevent within the ABR procedure + * + ******************************************************************************/ +sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + uint8_t antenna_selection, + const sl_bt_cs_subevent_length_t *subevent_len, + uint16_t subevent_interval, + int8_t tx_power, + uint8_t t_ip1_time, + uint8_t t_ip2_time, + uint8_t t_fcs_time, + uint8_t t_pm_time, + uint8_t t_sw_time, + uint8_t tone_antenna_config, + uint8_t companion_signal_state, + uint16_t drbg_nonce, + uint16_t override_config, + size_t override_parameters_len, + const uint8_t* override_parameters); + +/** @} */ // end addtogroup sl_bt_cs_test + +/** + * @addtogroup sl_bt_l2cap L2CAP Connection Oriented Channels + * @{ + * + * @brief L2CAP Connection Oriented Channels + * + * The commands and events in this class provide Logical Link Control and + * Adaptation Protocol (L2CAP) credit-based logical channels. + * + * An L2CAP credit-based logical channel is a logical link identified by a + * channel identifier (the @p cid parameter in the commands and events of this + * API class). These channels use a credit-based flow control mechanism. The + * credit can be configured at the channel opening and later dynamically updated + * on the channel. + * + * The Simplified Protocol/Service Multiplexer (SPSM) of a channel specifies the + * protocol or services the channel implements. It can be a value for a fixed + * service assigned by the Bluetooth SIG or a dynamically-allocated value and + * used with services defined in the GATT Server. The dynamically-assigned value + * may be used to support multiple implementations of a particular protocol. See + * the Bluetooth core specification for more details. The application specifies + * the SPSM value in a channel open request in the @p spsm parameter of the @ref + * sl_bt_l2cap_open_le_channel command. + * + * Each of the local and peer channel endpoints must specify the maximum Service + * Data Unit (SDU) size (the 'MTU' field of the L2CAP packets in the Bluetooth + * Core specification) that it can receive on the channel. The application + * specifies the maximum Service Data Unit size (the @p max_sdu parameter in + * commands and events) of the local channel endpoint. + * + * Each channel endpoint has a maximum PDU payload Size that the L2CAP layer can + * receive in a single data packet on the channel. The maximum PDU payload size + * supported by the stack for local channel endpoints is 252 bytes, which is the + * maximum data length the @ref sl_bt_evt_l2cap_channel_data event can support. + * The application specifies the max PDU payload size (the @p max_pdu parameter + * in commands and events). Additionally, the application is responsible for + * handling the segmentation from SDU to PDU and reassembly from PDU to SDU. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_l2cap_open_le_channel_id 0x01430020 +#define sl_bt_cmd_l2cap_send_le_channel_open_response_id 0x02430020 +#define sl_bt_cmd_l2cap_channel_send_data_id 0x03430020 +#define sl_bt_cmd_l2cap_channel_send_credit_id 0x04430020 +#define sl_bt_cmd_l2cap_close_channel_id 0x05430020 +#define sl_bt_rsp_l2cap_open_le_channel_id 0x01430020 +#define sl_bt_rsp_l2cap_send_le_channel_open_response_id 0x02430020 +#define sl_bt_rsp_l2cap_channel_send_data_id 0x03430020 +#define sl_bt_rsp_l2cap_channel_send_credit_id 0x04430020 +#define sl_bt_rsp_l2cap_close_channel_id 0x05430020 + +/** + * @brief Defines possible result values in the responses to credit based + * channel connection requests. + */ +typedef enum +{ + sl_bt_l2cap_connection_result_successful = 0x0, /**< (0x0) + Connection + successful */ + sl_bt_l2cap_connection_result_spsm_not_supported = 0x2, /**< (0x2) + Connection + refused + \- + SPSM + not + supported */ + sl_bt_l2cap_connection_result_no_resources_available = 0x4, /**< (0x4) + Connection + refused + \- no + resources + available */ + sl_bt_l2cap_connection_result_insufficient_authentication = 0x5, /**< (0x5) + Connection + refused + \- + insufficient + authentication */ + sl_bt_l2cap_connection_result_insufficient_authorization = 0x6, /**< (0x6) + Connection + refused + \- + insufficient + authorization */ + sl_bt_l2cap_connection_result_encryption_key_size_too_short = 0x7, /**< (0x7) + Connection + refused + \- + encryption + key + size + too + short */ + sl_bt_l2cap_connection_result_insufficient_encryption = 0x8, /**< (0x8) + Connection + refused + \- + insufficient + encryption */ + sl_bt_l2cap_connection_result_invalid_source_cid = 0x9, /**< (0x9) + Connection + refused + \- + invalid + Source + CID */ + sl_bt_l2cap_connection_result_source_cid_already_allocated = 0xa, /**< (0xa) + Connection + refused + \- + Source + CID + already + allocated */ + sl_bt_l2cap_connection_result_unacceptable_parameters = 0xb /**< (0xb) + Connection + refused + \- + unacceptable + parameters */ +} sl_bt_l2cap_connection_result_t; + +/** + * @brief Describes why a request command was rejected. + */ +typedef enum +{ + sl_bt_l2cap_command_not_understood = 0x0, /**< (0x0) Command not understood + e.g., unknown command code */ + sl_bt_l2cap_signaling_mtu_exceeded = 0x1, /**< (0x1) Command size has exceeded + the signaling MTU size */ + sl_bt_l2cap_invalid_cid_request = 0x2 /**< (0x2) An invalid CID is + included in the command */ +} sl_bt_l2cap_command_reject_reason_t; + +/** + * @brief Describes which of the request commands has been rejected. + */ +typedef enum +{ + sl_bt_l2cap_disconnection_request = 0x6, /**< (0x6) A disconnection request */ + sl_bt_l2cap_le_connection_request = 0x14, /**< (0x14) An LE credit-based + connection request */ + sl_bt_l2cap_flow_control_credit = 0x16 /**< (0x16) A Flow Control Credit + packet */ +} sl_bt_l2cap_command_code_t; + +/** + * @addtogroup sl_bt_evt_l2cap_le_channel_open_request sl_bt_evt_l2cap_le_channel_open_request + * @{ + * @brief Indicates that an LE credit-based connection request on a Bluetooth + * connection is received + * + * The application must respond with the @ref + * sl_bt_l2cap_send_le_channel_open_response command. + */ + +/** @brief Identifier of the le_channel_open_request event */ +#define sl_bt_evt_l2cap_le_channel_open_request_id 0x014300a0 + +/***************************************************************************//** + * @brief Data structure of the le_channel_open_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_request_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t spsm; /**< The protocol/services implemented by the peer + channel endpoint */ + uint16_t cid; /**< The channel identifier on the local device */ + uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer + channel endpoint */ + uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel + endpoint */ + uint16_t credit; /**< The initial credit value of the peer channel + endpoint, i.e., number of PDUs that the local + channel endpoint can send */ + uint16_t remote_cid; /**< The channel identifier on the peer device */ +}); + +typedef struct sl_bt_evt_l2cap_le_channel_open_request_s sl_bt_evt_l2cap_le_channel_open_request_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_request + +/** + * @addtogroup sl_bt_evt_l2cap_le_channel_open_response sl_bt_evt_l2cap_le_channel_open_response + * @{ + * @brief Indicates that an LE credit-based connection response is received + * + * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode + * implies that the logical channel is established and data can be sent or + * received on the channel. + * + * If the connection request was rejected by the peer, indicated by @p + * errorcode, the stack automatically closes the local channel and the user + * application should clean up the resources associated to the channel + * identifier. + */ + +/** @brief Identifier of the le_channel_open_response event */ +#define sl_bt_evt_l2cap_le_channel_open_response_id 0x024300a0 + +/***************************************************************************//** + * @brief Data structure of the le_channel_open_response event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_response_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the + response is received */ + uint16_t cid; /**< The channel identifier on the local device */ + uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer + channel endpoint */ + uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel + endpoint */ + uint16_t credit; /**< The initial credit value of the peer channel + endpoint, i.e., number of PDUs the local channel + endpoint can send */ + uint16_t errorcode; /**< Enum @ref sl_bt_l2cap_connection_result_t. + + An L2CAP error code as the outcome of the connection + request. + + Result @ref sl_bt_l2cap_connection_result_successful + indicates the connection request was accepted and + the logical channel is established. Other error code + value indicates the connection request was refused + by the peer device and other parameters of this + event must be ignored. */ + uint16_t remote_cid; /**< The channel identifier on the peer device */ +}); + +typedef struct sl_bt_evt_l2cap_le_channel_open_response_s sl_bt_evt_l2cap_le_channel_open_response_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_response + +/** + * @addtogroup sl_bt_evt_l2cap_channel_data sl_bt_evt_l2cap_channel_data + * @{ + * @brief Indicates that data is received on a channel + * + * Each event should contain a K-frame of payload. The length of SDU should be + * specified in the first 2 bytes of the first K-frame. The sum of the payload + * lengths in received K-frames should be equal to the specified SDU length. + * Otherwise, application should disconnect the channel using @ref + * sl_bt_l2cap_close_channel command. The same should happen also if the SDU + * length exceeds the max_sdu of local channel endpoint. + */ + +/** @brief Identifier of the channel_data event */ +#define sl_bt_evt_l2cap_channel_data_id 0x034300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_data_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t cid; /**< The channel identifier */ + uint8array data; /**< Data received */ +}); + +typedef struct sl_bt_evt_l2cap_channel_data_s sl_bt_evt_l2cap_channel_data_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_data + +/** + * @addtogroup sl_bt_evt_l2cap_channel_credit sl_bt_evt_l2cap_channel_credit + * @{ + * @brief Indicates that flow control credits are received on a channel + * informing that the peer channel endpoint is capable of receiving more data + */ + +/** @brief Identifier of the channel_credit event */ +#define sl_bt_evt_l2cap_channel_credit_id 0x044300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_credit event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_credit_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the credit + is received */ + uint16_t cid; /**< The channel identifier */ + uint16_t credit; /**< The credit value, i.e., the additional number of + PDUs the peer channel endpoint can receive */ +}); + +typedef struct sl_bt_evt_l2cap_channel_credit_s sl_bt_evt_l2cap_channel_credit_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_credit + +/** + * @addtogroup sl_bt_evt_l2cap_channel_closed sl_bt_evt_l2cap_channel_closed + * @{ + * @brief Indicates that a credit-based logical channel is closed by the local + * or peer device. + */ + +/** @brief Identifier of the channel_closed event */ +#define sl_bt_evt_l2cap_channel_closed_id 0x054300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_closed_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t cid; /**< The channel identifier */ + uint16_t reason; /**< The disconnection reason */ +}); + +typedef struct sl_bt_evt_l2cap_channel_closed_s sl_bt_evt_l2cap_channel_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_closed + +/** + * @addtogroup sl_bt_evt_l2cap_command_rejected sl_bt_evt_l2cap_command_rejected + * @{ + * @brief Indicates that the peer device rejected a command + * + * This might happen if, for example, the device does not support the feature or + * the command has an incorrect CID. + */ + +/** @brief Identifier of the command_rejected event */ +#define sl_bt_evt_l2cap_command_rejected_id 0x064300a0 + +/***************************************************************************//** + * @brief Data structure of the command_rejected event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_command_rejected_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the event + is received */ + uint8_t code; /**< Enum @ref sl_bt_l2cap_command_code_t. Code of the + rejected command */ + uint16_t reason; /**< Enum @ref sl_bt_l2cap_command_reject_reason_t. The + rejection reason */ + uint16_t cid; /**< The channel identifier */ +}); + +typedef struct sl_bt_evt_l2cap_command_rejected_s sl_bt_evt_l2cap_command_rejected_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_command_rejected + +/***************************************************************************//** + * + * Create and configure an L2CAP channel on a Bluetooth connection using the LE + * credit based connection request packet. Event @ref + * sl_bt_evt_l2cap_le_channel_open_response or @ref + * sl_bt_evt_l2cap_command_rejected will be received after the peer device + * responded to the request. + * + * @param[in] connection The connection handle + * @param[in] spsm The protocol/services implemented by the local channel + * endpoint + * @param[in] max_sdu @parblock + * The Maximum Service Data Unit size the local channel endpoint can accept + * + * Range: 23 to 65533. + * @endparblock + * @param[in] max_pdu @parblock + * The maximum PDU payload size the local channel endpoint can accept + * + * Range: 23 to 252. + * @endparblock + * @param[in] credit The initial credit value of the local channel endpoint, + * i.e., number of PDUs the peer channel endpoint can send + * @param[out] cid The channel identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_l2cap_command_rejected - Triggered when the peer device + * rejected the connection request. Typically a legacy peer device that does + * not support the feature could send this response. When this event is + * received under the context of opening a channel using this command, the + * stack automatically closes the local channel and the user application + * should clean up the resources associated to the channel identifier. + * - @ref sl_bt_evt_l2cap_le_channel_open_response - Triggered when an LE + * credit-based connection response has been received in response to this + * command. If the result code in @p errorcode of the event is not equal to + * @ref sl_bt_l2cap_connection_result_successful, it means that connection + * request was rejected by the peer device. In this case, the stack + * automatically closes the local channel and the user application should + * clean up the resources associated to the channel identifier. + * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an LE credit-based + * connection response has not been received within 30 seconds after this + * command has been issued. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, + uint16_t spsm, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t *cid); + +/***************************************************************************//** + * + * Send an LE credit-based connection response to an LE credit-based connection + * request received in the @ref sl_bt_evt_l2cap_le_channel_open_request event. + * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode + * implies that the logical channel is established and data can be sent or + * received on the channel. + * + * To reject the connection request, use a result code other than + * sl_bt_l2cap_connection_result_successful in @p errorcode. Other parameters in + * this command are ignored in this case. The stack automatically closes the + * local channel and the user application should clean up the resources + * associated to the channel identifier. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] max_sdu @parblock + * The Maximum Service Data Unit size the local channel endpoint can accept + * + * Range: 23 to 65533. + * @endparblock + * @param[in] max_pdu @parblock + * The maximum PDU payload size the local channel endpoint can accept + * + * Range:23 to 252. + * @endparblock + * @param[in] credit The initial credit value of the local channel endpoint, + * i.e., number of PDUs that the peer channel endpoint can send + * @param[in] errorcode Enum @ref sl_bt_l2cap_connection_result_t. An L2CAP + * error code as the outcome of the connection request + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, + uint16_t cid, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t errorcode); + +/***************************************************************************//** + * + * Send data to the peer channel endpoint on a Bluetooth connection. If the SDU + * length is larger than max_pdu size or 250 bytes, the application should + * fragment the SDU into multiple K-frames and call this command once for each + * K-frame. + * + * The first K-frame of the SDU should start with 2 bytes of SDU length followed + * with payload. Therefore, the first K-frame contains PDU length minus 2 bytes + * of the actual payload. All subsequent K-frames of the same SDU contain PDU + * length of the payload. The sum of the payload lengths for K-frames should be + * equal to the specified SDU length. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be sent. The data length must not be greater than the + * lesser of the peer channel endpoint max_pdu and 252 bytes, which is the + * maximum data length this command can send. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, + uint16_t cid, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Send flow control credits to the peer channel endpoint indicating that the + * local channel endpoint is capable of receiving more data. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] credit @parblock + * The credit value, i.e., the additional number of PDUs the peer channel + * endpoint can send + * + * Range: 1 to 65535. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, + uint16_t cid, + uint16_t credit); + +/***************************************************************************//** + * + * Send a disconnect request to close a credit-based logical channel. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an credit-based + * logical channel is closed in response to this command. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid); + +/** @} */ // end addtogroup sl_bt_l2cap + +/** + * @addtogroup sl_bt_cte_transmitter CTE Transmitter + * @{ + * + * @brief CTE Transmitter + * + * Commands and events in this class manage Constant Tone Extension (CTE) + * transmission. + * + * CTE feature is only supported by specific devices. Commands from this class + * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cte_transmitter_set_dtm_parameters_id 0x04440020 +#define sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id 0x05440020 +#define sl_bt_cmd_cte_transmitter_enable_connection_cte_id 0x00440020 +#define sl_bt_cmd_cte_transmitter_disable_connection_cte_id 0x01440020 +#define sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id 0x02440020 +#define sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id 0x03440020 +#define sl_bt_cmd_cte_transmitter_enable_silabs_cte_id 0x06440020 +#define sl_bt_cmd_cte_transmitter_disable_silabs_cte_id 0x07440020 +#define sl_bt_rsp_cte_transmitter_set_dtm_parameters_id 0x04440020 +#define sl_bt_rsp_cte_transmitter_clear_dtm_parameters_id 0x05440020 +#define sl_bt_rsp_cte_transmitter_enable_connection_cte_id 0x00440020 +#define sl_bt_rsp_cte_transmitter_disable_connection_cte_id 0x01440020 +#define sl_bt_rsp_cte_transmitter_enable_connectionless_cte_id 0x02440020 +#define sl_bt_rsp_cte_transmitter_disable_connectionless_cte_id 0x03440020 +#define sl_bt_rsp_cte_transmitter_enable_silabs_cte_id 0x06440020 +#define sl_bt_rsp_cte_transmitter_disable_silabs_cte_id 0x07440020 + +/***************************************************************************//** + * + * Set the CTE-related parameters of the LE transmitter test. + * + * @param[in] cte_length @parblock + * The length of the Constant Tone Extension in 8 us units + * - 0: No CTE + * - 0x02 to 0x14: CTE length + * + * Default: 0 (no CTE) + * @endparblock + * @param[in] cte_type @parblock + * CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * + * Default: 0 + * @endparblock + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. This can be + * an empty array if CTE is unused. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Clear CTE-related parameters that were previously set for LE transmitter + * test. Default values will be restored for these parameters. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters(); + +/***************************************************************************//** + * + * Enable different types of CTE responses on a connection. CTE response will be + * sent once requested by the peer device using the CTE Request procedure. + * + * @param[in] connection Connection handle + * @param[in] cte_types CTE types. Bitmask of the following: + * - Bit 0: AoA CTE response + * - Bit 1: AoD CTE response with 1 us slots + * - Bit 2: AoD CTE response with 2 us slots + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, + uint8_t cte_types, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable CTE responses on a connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection); + +/***************************************************************************//** + * + * Start a connectionless CTE transmit. CTEs will be transmitted in periodic + * advertisement packets. As a result, a periodic advertising has to be started + * prior to this command. + * + * @param[in] handle Periodic advertising handle + * @param[in] cte_length CTE length in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] cte_count The number of CTEs to be transmitted in each periodic + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop the connectionless CTE transmit. + * + * @param[in] handle Periodic advertising handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle); + +/***************************************************************************//** + * + * Enable Silicon Labs CTE transmit. CTEs will be transmitted in extended + * advertisement packets. As a result, extended advertising has to be started + * prior this command. + * + * @param[in] handle Advertising handle + * @param[in] cte_length CTE length in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] cte_count The number of CTEs to be transmitted in each extended + * advertising interval. Currently, only cte_count = 1 is supported. + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable Silicon Labs CTE transmit. + * + * @param[in] handle Advertising handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle); + +/** @} */ // end addtogroup sl_bt_cte_transmitter + +/** + * @addtogroup sl_bt_cte_receiver CTE Receiver + * @{ + * + * @brief CTE Receiver + * + * Commands and events in this class manage Constant Tone Extension (CTE) + * receiving. + * + * CTE feature is only supported by specific devices. Commands from this class + * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cte_receiver_set_dtm_parameters_id 0x05450020 +#define sl_bt_cmd_cte_receiver_clear_dtm_parameters_id 0x06450020 +#define sl_bt_cmd_cte_receiver_set_sync_cte_type_id 0x09450020 +#define sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 +#define sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id 0x0b450020 +#define sl_bt_cmd_cte_receiver_configure_id 0x00450020 +#define sl_bt_cmd_cte_receiver_enable_connection_cte_id 0x01450020 +#define sl_bt_cmd_cte_receiver_disable_connection_cte_id 0x02450020 +#define sl_bt_cmd_cte_receiver_enable_connectionless_cte_id 0x03450020 +#define sl_bt_cmd_cte_receiver_disable_connectionless_cte_id 0x04450020 +#define sl_bt_cmd_cte_receiver_enable_silabs_cte_id 0x07450020 +#define sl_bt_cmd_cte_receiver_disable_silabs_cte_id 0x08450020 +#define sl_bt_rsp_cte_receiver_set_dtm_parameters_id 0x05450020 +#define sl_bt_rsp_cte_receiver_clear_dtm_parameters_id 0x06450020 +#define sl_bt_rsp_cte_receiver_set_sync_cte_type_id 0x09450020 +#define sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 +#define sl_bt_rsp_cte_receiver_set_sync_receive_parameters_id 0x0b450020 +#define sl_bt_rsp_cte_receiver_configure_id 0x00450020 +#define sl_bt_rsp_cte_receiver_enable_connection_cte_id 0x01450020 +#define sl_bt_rsp_cte_receiver_disable_connection_cte_id 0x02450020 +#define sl_bt_rsp_cte_receiver_enable_connectionless_cte_id 0x03450020 +#define sl_bt_rsp_cte_receiver_disable_connectionless_cte_id 0x04450020 +#define sl_bt_rsp_cte_receiver_enable_silabs_cte_id 0x07450020 +#define sl_bt_rsp_cte_receiver_disable_silabs_cte_id 0x08450020 + +/** + * @addtogroup sl_bt_cte_receiver_sync_cte_type CTE type flags for limiting periodic advertising synchronization + * @{ + * + * Defines sync CTE type flags that are used to limit what types of periodic + * advertisers to sync to when scanning for periodic advertising synchronization + * or receiving periodic advertising synchronization transfers. + */ + +/** Do not sync to packets with an AoA Constant Tone Extension */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA 0x1 + +/** Do not sync to packets with an AoD Constant Tone Extension with 1 us slots + * */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US 0x2 + +/** Do not sync to packets with an AoD Constant Tone Extension with 2 us slots + * */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US 0x4 + +/** Do not sync to packets without a Constant Tone Extension */ +#define SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY 0x10 + +/** @} */ // end CTE type flags for limiting periodic advertising synchronization + +/** + * @addtogroup sl_bt_evt_cte_receiver_dtm_iq_report sl_bt_evt_cte_receiver_dtm_iq_report + * @{ + * @brief IQ sample report from DTM CTE packets. + */ + +/** @brief Identifier of the dtm_iq_report event */ +#define sl_bt_evt_cte_receiver_dtm_iq_report_id 0x024500a0 + +/***************************************************************************//** + * @brief Data structure of the dtm_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_dtm_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the periodic advertising + train or the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_dtm_iq_report_s sl_bt_evt_cte_receiver_dtm_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_dtm_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_connection_iq_report sl_bt_evt_cte_receiver_connection_iq_report + * @{ + * @brief IQ sample report from connection CTE packets. + */ + +/** @brief Identifier of the connection_iq_report event */ +#define sl_bt_evt_cte_receiver_connection_iq_report_id 0x004500a0 + +/***************************************************************************//** + * @brief Data structure of the connection_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_connection_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint8_t connection; /**< Connection handle or periodic advertising + synchronization handle */ + uint8_t phy; /**< The PHY on which the packet is received. + - 1: 1M PHY + - 2: 2M PHY */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_connection_iq_report_s sl_bt_evt_cte_receiver_connection_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connection_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report sl_bt_evt_cte_receiver_connectionless_iq_report + * @{ + * @brief IQ sample report from connectionless CTE packets. + */ + +/** @brief Identifier of the connectionless_iq_report event */ +#define sl_bt_evt_cte_receiver_connectionless_iq_report_id 0x014500a0 + +/***************************************************************************//** + * @brief Data structure of the connectionless_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_connectionless_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the periodic advertising + train */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_connectionless_iq_report_s sl_bt_evt_cte_receiver_connectionless_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_silabs_iq_report sl_bt_evt_cte_receiver_silabs_iq_report + * @{ + * @brief IQ samples report from Silicon Labs CTE packets. + */ + +/** @brief Identifier of the silabs_iq_report event */ +#define sl_bt_evt_cte_receiver_silabs_iq_report_id 0x034500a0 + +/***************************************************************************//** + * @brief Data structure of the silabs_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_silabs_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + bd_addr address; /**< Bluetooth address of the remote device */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t phy; /**< The PHY on which the packet is received. + - 1: 1M PHY + - 2: 2M PHY */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t packet_counter; /**< The event counter of the periodic advertising + train or the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_silabs_iq_report_s sl_bt_evt_cte_receiver_silabs_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_silabs_iq_report + +/***************************************************************************//** + * + * Set CTE-related parameters of LE receiver test. + * + * @param[in] cte_length @parblock + * Expected CTE length in 8 us units + * - 0: No CTE + * - 0x02 to 0x14: Expected CTE length + * + * Default: 0 (no CTE) + * @endparblock + * @param[in] cte_type @parblock + * Expected CTE type + * - 0: Expect AoA CTE + * - 1: Expect AoD CTE with 1 us slots + * - 2: Expect AoD CTE with 2 us slots + * + * Default: 0 + * @endparblock + * @param[in] slot_durations @parblock + * Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * + * Default: 1 + * @endparblock + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. This can be + * an empty array if CTE is unused. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_dtm_iq_report - Triggered when IQ samples + * have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Clear CTE-related parameters that were previously set for LE receiver test. + * Default values will be restored for these parameters. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_clear_dtm_parameters(); + +/***************************************************************************//** + * + * Set the sync CTE type to limit what types of periodic advertisers to sync to + * when scanning for periodic advertising synchronization. The set parameter + * takes effect immediately for all advertisers that have not already + * established synchronization. + * + * @param[in] sync_cte_type @parblock + * Sync CTE type flags. This value can be a bitmask of multiple flags from + * @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type); + +/***************************************************************************//** + * + * Set the default parameters and the CTE type limitation for receiving Periodic + * Advertising Synchronization Transfers (PAST) over connections. The default + * parameters will be in effect for all subsequent connections and do not affect + * connections that have already opened. The parameters can be overridden for a + * specific connection using command @ref + * sl_bt_cte_receiver_set_sync_receive_parameters after the connection is + * opened. + * + * This command is relevant and available only when the application has included + * the bluetooth_feature_past_receiver component into the build. If the PAST + * receiver component is not included, this command returns the error + * SL_STATUS_NOT_AVAILABLE. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] sync_cte_type @parblock + * Sync CTE type flags to limit what types of periodic advertising trains to + * sync to when receiving sync transfers. This value can be a bitmask of + * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 (do not limit synchronization by CTE type) + * @endparblock + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Set the parameters and the CTE type limitation for receiving Periodic + * Advertising Synchronization Transfers (PAST) over the specified connection. + * The parameters do not affect periodic advertising trains that the device has + * already synchronized to. + * + * This command is relevant and available only when the application has included + * the bluetooth_feature_past_receiver component into the build. If the PAST + * receiver component is not included, this command returns the error + * SL_STATUS_NOT_AVAILABLE. + * + * @param[in] connection Connection handle + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] sync_cte_type @parblock + * Sync CTE type flags to limit what types of periodic advertising trains to + * sync to when receiving sync transfers. This value can be a bitmask of + * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 (do not limit synchronization by CTE type) + * @endparblock + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Configure the CTE sampling mode. + * + * @param[in] flags @parblock + * Values: + * - 0: Disable raw sample mode, only picked IQ samples are reported + * (1 IQ sample pair / slot) + * - 1: Enable raw sample mode, every IQ sample is reported. + * + * Default: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_configure(uint8_t flags); + +/***************************************************************************//** + * + * Start IQ samplings on a connection. A CTE requests will be initiated + * periodically on the given connection and IQ sampling will be made on the + * received CTE responses. + * + * @param[in] connection Connection handle + * @param[in] interval Measurement interval. CTE requests may be sent less + * often. For example, if a connection event is missed for any reason, the CTE + * request will be sent in the next connection event. + * - 0: No interval. The request is initiated only once. + * - Other values N: Initiate the request every N-th connection + * events + * @param[in] cte_length Minimum CTE length requested in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type Requested CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_connection_iq_report - Triggered when IQ + * samples have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, + uint16_t interval, + uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop the IQ sampling on a connection. CTEs will not be requested on the given + * connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection); + +/***************************************************************************//** + * + * Start IQ sampling on a periodic advertising synchronization. IQ samples are + * taken on each CTE found in the periodic advertisements. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] cte_count - 0: Sample and report all available CTEs + * - Other values: Maximum number of sampled CTEs in each periodic + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_connectionless_iq_report - Triggered when IQ + * samples have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, + uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop IQ sampling on a periodic advertising synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync); + +/***************************************************************************//** + * + * Enable IQ sampling of Silicon Labs CTE found in extended advertisements. + * + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] cte_count - 0: Sample and report all available CTEs + * - Other values: Maximum number of sampled CTEs in each extended + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_silabs_iq_report - Triggered when IQ samples + * of Silicon Labs CTE have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable IQ sampling of Silicon Labs CTE. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_silabs_cte(); + +/** @} */ // end addtogroup sl_bt_cte_receiver + +/** + * @addtogroup sl_bt_connection_analyzer Connection Analyzer + * @{ + * + * @brief Connection Analyzer + * + * Analyze Bluetooth packets that are transmitted on the connections of external + * devices. Include component bluetooth_feature_connection_analyzer to use the + * commands and events in this class. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_connection_analyzer_start_id 0x00480020 +#define sl_bt_cmd_connection_analyzer_stop_id 0x01480020 +#define sl_bt_rsp_connection_analyzer_start_id 0x00480020 +#define sl_bt_rsp_connection_analyzer_stop_id 0x01480020 + +/** + * @addtogroup sl_bt_connection_analyzer_flags Connection Analyzer Configuration flags + * @{ + * + * Defines the configuration flags in connection analyzer. + */ + +/** Indicates a given time value, e.g., @p start_time_us in @ref + * sl_bt_connection_analyzer_start, is a value relative to the current time. */ +#define SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME 0x1 + +/** @} */ // end Connection Analyzer Configuration flags + +/** + * @addtogroup sl_bt_evt_connection_analyzer_report sl_bt_evt_connection_analyzer_report + * @{ + * @brief Triggered when packets transmitted on a connection are captured. + */ + +/** @brief Identifier of the report event */ +#define sl_bt_evt_connection_analyzer_report_id 0x004800a0 + +/***************************************************************************//** + * @brief Data structure of the report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_analyzer_report_s +{ + uint8_t analyzer; /**< The handle of the connection analyzer */ + int8_t central_rssi; /**< RSSI measurement of the packet transmitted by + the Central device. Units: dBm. Range: -127 to + +20. */ + int8_t peripheral_rssi; /**< RSSI measurement of the packet transmitted by + the Peripheral device. Units: dBm. Range: -127 + to +20. */ +}); + +typedef struct sl_bt_evt_connection_analyzer_report_s sl_bt_evt_connection_analyzer_report_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_report + +/** + * @addtogroup sl_bt_evt_connection_analyzer_completed sl_bt_evt_connection_analyzer_completed + * @{ + * @brief Triggered when the operation of analyzing a connection is completed. + */ + +/** @brief Identifier of the completed event */ +#define sl_bt_evt_connection_analyzer_completed_id 0x014800a0 + +/***************************************************************************//** + * @brief Data structure of the completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_analyzer_completed_s +{ + uint8_t analyzer; /**< The handle of the connection analyzer */ + uint16_t reason; /**< The reason of stopping the operation */ +}); + +typedef struct sl_bt_evt_connection_analyzer_completed_s sl_bt_evt_connection_analyzer_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_completed + +/***************************************************************************//** + * + * Start to analyze another device's connection and report the RSSI + * measurements. The parameters in this command provide necessary information to + * identify the connection and schedule operations to follow its transmissions. + * + * If the other device uses Silabs' Bluetooth stack, the information of the + * connection could be retrieved with command @ref + * sl_bt_connection_get_scheduling_details. The method of passing the + * information to this device is application layer logic. + * + * @param[in] access_address Access address of the connection + * @param[in] crc_init The CRC initialization value + * @param[in] interval The connection interval. Time = Value x 1.25 ms + * @param[in] supervision_timeout The connection supervision time. Time = Value + * x 10 ms + * @param[in] central_clock_accuracy The central device's clock accuracy index + * value + * @param[in] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central + * device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[in] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the + * Peripheral device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[in] channel_selection_algorithm Enum @ref + * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. + * Values: + * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection + * algorithm #1 + * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection + * algorithm #2 + * @param[in] hop The hop increment when the channel selection algorithm #1 is + * used on the connection. Ignored if @p channel_selection_algorithm indicates + * that the connection uses channel selection algorithm #2. + * @param[in] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Ignore bits 37-39 that are reserved for future use. + * + * A channel is unused when its bit is 0. A channel is used when its bit is 1. + * @endparblock + * @param[in] channel The data channel number that transmissions will use in the + * next connection event + * @param[in] event_counter The event counter of the next connection event + * @param[in] start_time_us The start time of the given connection event in + * microseconds. The semantics depend on whether the configuration flag + * SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME is set in parameter @p flags: + * - When the flag is set, the value is a time relative to the current time. + * A negative value means that the start time was in the past. + * - When the flag is not set, the value is an absolute time converted from + * the PROTIMER tick. + * @param[in] flags Configuration flags. This value is a bitmask of @ref + * sl_bt_connection_analyzer_flags. + * @param[out] analyzer A handle that is assigned to the connection analyzer. + * This handle is valid only if the result code of this command is + * SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_analyzer_report - Triggered when a packet + * transmitted from the given device is captured. + * - @ref sl_bt_evt_connection_analyzer_completed - Triggered when analyzing a + * connection is completed in the Link Layer for some reason. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, + uint32_t crc_init, + uint16_t interval, + uint16_t supervision_timeout, + uint8_t central_clock_accuracy, + uint8_t central_phy, + uint8_t peripheral_phy, + uint8_t channel_selection_algorithm, + uint8_t hop, + const sl_bt_connection_channel_map_t *channel_map, + uint8_t channel, + uint16_t event_counter, + int32_t start_time_us, + uint32_t flags, + uint8_t *analyzer); + +/***************************************************************************//** + * + * Stop analyzing another device's Bluetooth connection. The operation is + * stopped when this command returns, and the stack does not send additional + * event. + * + * @param[in] analyzer The handle of the connection analyzer to stop + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer); + +/** @} */ // end addtogroup sl_bt_connection_analyzer + +/** + * @addtogroup sl_bt_user User Messaging + * @{ + * + * @brief User Messaging + * + * This class provides commands and events, which can be used by a NCP host and + * target to implement a communication mechanism with a custom proprietary + * protocol. An application must decide whether and how the command and event + * are used. The stack does not produce or consume any messages belonging to + * this class. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_user_message_to_target_id 0x00ff0020 +#define sl_bt_cmd_user_manage_event_filter_id 0x01ff0020 +#define sl_bt_cmd_user_reset_to_dfu_id 0x02ff0020 +#define sl_bt_rsp_user_message_to_target_id 0x00ff0020 +#define sl_bt_rsp_user_manage_event_filter_id 0x01ff0020 +#define sl_bt_rsp_user_reset_to_dfu_id 0x02ff0020 + +/** + * @addtogroup sl_bt_evt_user_message_to_host sl_bt_evt_user_message_to_host + * @{ + * @brief Used by the target application on a device to initiate communication + * and send a message to the NCP host + * + * Do not send event messages in the context of the user command handling. + */ + +/** @brief Identifier of the message_to_host event */ +#define sl_bt_evt_user_message_to_host_id 0x00ff00a0 + +/***************************************************************************//** + * @brief Data structure of the message_to_host event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_user_message_to_host_s +{ + uint8array message; /**< The message */ +}); + +typedef struct sl_bt_evt_user_message_to_host_s sl_bt_evt_user_message_to_host_t; + +/** @} */ // end addtogroup sl_bt_evt_user_message_to_host + +/***************************************************************************//** + * + * Used by an NCP host to send a message to the target application on device. + * The application on the target must send the response with @ref + * sl_bt_send_rsp_user_message_to_target. + * + * @param[in] data_len Length of data in @p data + * @param[in] data The message + * @param[in] max_response_size Size of output buffer passed in @p response + * @param[out] response_len On return, set to the length of output data written + * to @p response + * @param[out] response The response message + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_user_message_to_target(size_t data_len, + const uint8_t* data, + size_t max_response_size, + size_t *response_len, + uint8_t *response); + +/***************************************************************************//** + * + * Manage NCP event filter. When the event filter is in use, API events passing + * the filter will be sent to the host and those that do not pass are discarded + * by the target. For functionality details, see the NCP component in the + * Bluetooth SDK. + * + * By default, the NCP does not use the event filter. + * + * @param[in] data_len Length of data in @p data + * @param[in] data The message for managing event filter + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_user_manage_event_filter(size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Reset the target device to DFU mode from the NCP host. This command is used + * by specific SDK DFU component on the target device for the functionality + * related to DFU. Do not use it in other circumstances. This command does not + * have a response. + * + * + ******************************************************************************/ +void sl_bt_user_reset_to_dfu(); + +/** @} */ // end addtogroup sl_bt_user + + +/***************************************************************************//** + * @addtogroup sl_bt_common_types BT Common Types + * @{ + * @brief BT common types + */ + +/** + * @brief Data structure of BT API messages + */ +PACKSTRUCT( struct sl_bt_msg { + /** API protocol header consisting of event identifier and data length */ + uint32_t header; + + /** Union of API event types */ + union { + uint8_t handle; + sl_bt_evt_dfu_boot_t evt_dfu_boot; /**< Data field for dfu boot event*/ + sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; /**< Data field for dfu boot_failure event*/ + sl_bt_evt_system_boot_t evt_system_boot; /**< Data field for system boot event*/ + sl_bt_evt_system_error_t evt_system_error; /**< Data field for system error event*/ + sl_bt_evt_system_hardware_error_t evt_system_hardware_error; /**< Data field for system hardware_error event*/ + sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; /**< Data field for system resource_exhausted event*/ + sl_bt_evt_system_external_signal_t evt_system_external_signal; /**< Data field for system external_signal event*/ + sl_bt_evt_system_soft_timer_t evt_system_soft_timer; /**< Data field for system soft_timer event*/ + sl_bt_evt_resource_status_t evt_resource_status; /**< Data field for resource status event*/ + sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; /**< Data field for advertiser timeout event*/ + sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; /**< Data field for advertiser scan_request event*/ + sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; /**< Data field for periodic_advertiser status event*/ + sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; /**< Data field for scanner legacy_advertisement_report event*/ + sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; /**< Data field for scanner extended_advertisement_report event*/ + sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; /**< Data field for scanner scan_report event*/ + sl_bt_evt_sync_opened_t evt_sync_opened; /**< Data field for sync opened event*/ + sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; /**< Data field for sync transfer_received event*/ + sl_bt_evt_sync_data_t evt_sync_data; /**< Data field for sync data event*/ + sl_bt_evt_sync_closed_t evt_sync_closed; /**< Data field for sync closed event*/ + sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; /**< Data field for periodic_sync opened event*/ + sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; /**< Data field for periodic_sync transfer_received event*/ + sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; /**< Data field for periodic_sync report event*/ + sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; /**< Data field for pawr_sync opened event*/ + sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; /**< Data field for pawr_sync transfer_received event*/ + sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; /**< Data field for pawr_sync subevent_report event*/ + sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; /**< Data field for pawr_advertiser subevent_data_request event*/ + sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; /**< Data field for pawr_advertiser subevent_tx_failed event*/ + sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; /**< Data field for pawr_advertiser response_report event*/ + sl_bt_evt_connection_opened_t evt_connection_opened; /**< Data field for connection opened event*/ + sl_bt_evt_connection_parameters_t evt_connection_parameters; /**< Data field for connection parameters event*/ + sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; /**< Data field for connection set_parameters_failed event*/ + sl_bt_evt_connection_phy_status_t evt_connection_phy_status; /**< Data field for connection phy_status event*/ + sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; /**< Data field for connection get_remote_tx_power_completed event*/ + sl_bt_evt_connection_tx_power_t evt_connection_tx_power; /**< Data field for connection tx_power event*/ + sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; /**< Data field for connection remote_tx_power event*/ + sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; /**< Data field for connection remote_used_features event*/ + sl_bt_evt_connection_data_length_t evt_connection_data_length; /**< Data field for connection data_length event*/ + sl_bt_evt_connection_statistics_t evt_connection_statistics; /**< Data field for connection statistics event*/ + sl_bt_evt_connection_closed_t evt_connection_closed; /**< Data field for connection closed event*/ + sl_bt_evt_connection_rssi_t evt_connection_rssi; /**< Data field for connection rssi event*/ + sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; /**< Data field for gatt mtu_exchanged event*/ + sl_bt_evt_gatt_service_t evt_gatt_service; /**< Data field for gatt service event*/ + sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; /**< Data field for gatt characteristic event*/ + sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; /**< Data field for gatt descriptor event*/ + sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; /**< Data field for gatt characteristic_value event*/ + sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; /**< Data field for gatt descriptor_value event*/ + sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; /**< Data field for gatt procedure_completed event*/ + sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; /**< Data field for gatt_server attribute_value event*/ + sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; /**< Data field for gatt_server user_read_request event*/ + sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; /**< Data field for gatt_server user_write_request event*/ + sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; /**< Data field for gatt_server characteristic_status event*/ + sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; /**< Data field for gatt_server execute_write_completed event*/ + sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; /**< Data field for gatt_server indication_timeout event*/ + sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; /**< Data field for gatt_server notification_tx_completed event*/ + sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; /**< Data field for test dtm_completed event*/ + sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; /**< Data field for sm passkey_display event*/ + sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; /**< Data field for sm passkey_request event*/ + sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; /**< Data field for sm confirm_passkey event*/ + sl_bt_evt_sm_bonded_t evt_sm_bonded; /**< Data field for sm bonded event*/ + sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; /**< Data field for sm bonding_failed event*/ + sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; /**< Data field for sm confirm_bonding event*/ + sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; /**< Data field for external_bondingdb data_request event*/ + sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; /**< Data field for external_bondingdb data event*/ + sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; /**< Data field for external_bondingdb data_ready event*/ + sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; /**< Data field for cs security_enable_complete event*/ + sl_bt_evt_cs_config_complete_t evt_cs_config_complete; /**< Data field for cs config_complete event*/ + sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; /**< Data field for cs procedure_enable_complete event*/ + sl_bt_evt_cs_result_t evt_cs_result; /**< Data field for cs result event*/ + sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; /**< Data field for l2cap le_channel_open_request event*/ + sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; /**< Data field for l2cap le_channel_open_response event*/ + sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; /**< Data field for l2cap channel_data event*/ + sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; /**< Data field for l2cap channel_credit event*/ + sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; /**< Data field for l2cap channel_closed event*/ + sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; /**< Data field for l2cap command_rejected event*/ + sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; /**< Data field for cte_receiver dtm_iq_report event*/ + sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; /**< Data field for cte_receiver connection_iq_report event*/ + sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; /**< Data field for cte_receiver connectionless_iq_report event*/ + sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; /**< Data field for cte_receiver silabs_iq_report event*/ + sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; /**< Data field for connection_analyzer report event*/ + sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; /**< Data field for connection_analyzer completed event*/ + sl_bt_evt_user_message_to_host_t evt_user_message_to_host; /**< Data field for user message_to_host event*/ + uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; + } data; +}); + +/** + * @brief Type definition for the data structure of BT API messages + */ +typedef struct sl_bt_msg sl_bt_msg_t; + +/** @} */ // end addtogroup sl_bt_common_types +/******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sl_bt_utility_functions Utility Functions + * @brief Utility functions for applications on SoC + * @{ + */ + +/** + * Get the next event that requires processing by user application. Application + * is not blocked if no event is waiting. + * + * @param event the pointer for storing the new event + * @return SL_STATUS_OK if a new event is returned, or SL_STATUS_NOT_FOUND if no + * event is waiting; other value indicates an error occurred + */ +sl_status_t sl_bt_pop_event(sl_bt_msg_t* event); + +/** + * Check whether events are in queue pending for processing. + * Call @ref sl_bt_pop_event to process pending events. + * + * @return true if event is pending; false otherwise + */ +bool sl_bt_event_pending(void); + +/** + * Check whether events are in queue pending for processing and return the next + * event length in bytes if events are pending. + * Call @ref sl_bt_pop_event to process pending events. + * + * @return the next event length if event is pending; 0 otherwise + */ +uint32_t sl_bt_event_pending_len(void); + + +/** + * Run the Bluetooth stack to process scheduled tasks. Events for user + * application may be generated as a result of this operation. + */ +void sl_bt_run(); + +/** + * Handle an API command in binary format. + * + * This is provided to NCP target applications for processing commands received + * from NCP transport. This function is a synonym for a generic BGAPI function + * @ref sl_bgapi_handle_command. If the NCP application uses an RTOS, use the + * sequence documented in @ref sl_bgapi_handle_command to handle the BGAPI + * command in a thread-safe manner. + * + * @param hdr the command header + * @param data the command payload in a byte array + */ +void sl_bt_handle_command(uint32_t hdr, void* data); + +/** + * Get the response to the command currently been handled. + * + * This is provided to NCP target applications for processing commands received + * from NCP transport. This function is a synonym for a generic BGAPI function + * @ref sl_bgapi_get_command_response. + */ +static inline sl_bt_msg_t* sl_bt_get_command_response() +{ + return (sl_bt_msg_t*) sl_bgapi_get_command_response(); +} + +/** + * Priority message handler function if user application requires the use of + * PendSV interrupt. + * + * If scheduler_callback function pointer in configuration struct is something + * else than NULL, then stack will not install its own PendSV IRQ handler but + * instead uses callback/handler functions. + * + * When application receives call to the scheduler_callback function it must + * schedule the call to gecko_priority_handle function to later time to run on + * high priority thread. This callback may happen inside radio IRQ so processing + * must not block and has to happen as fast as possible. + * + * Recommended implementation: High priority thread is loop that waits on binary + * semaphore and calls gecko_priority_handler. The scheduler_callback is simple + * function that only signals the semaphore. + * + */ +void sl_bt_priority_handle(void); + +/** + * @brief Signal the Bluetooth stack that an external event has happened. + * + * Signals can be used to report status changes from interrupt context or from + * other threads to application. Signals are bits that are automatically cleared + * after application has been notified. + * + * If the Platform Core Interrupt API has been configured to use the + * CORE_ATOMIC_METHOD_BASEPRI as the implementation method of atomic sections, + * this function must not be called from an interrupt handler with a priority + * higher than CORE_ATOMIC_BASE_PRIORITY_LEVEL. + * + * @param signals is a bitmask defining active signals that are reported back to + * the application by system_external_signal-event. + * @return SL_STATUS_OK if the operation is successful, + * SL_STATUS_NO_MORE_RESOURCE indicating the request could not be processed + * due to resource limitation at the moment, or SL_STATUS_INVALID_STATE when + * the on-demand start feature is used and the stack is currently stopped. + */ +sl_status_t sl_bt_external_signal(uint32_t signals); + +/** + * Signals stack to send system_awake event when application received wakeup + * signal. + */ +void sl_bt_send_system_awake(); + +/** + * Signals stack to send system_error event when in case of an error. + */ +void sl_bt_send_system_error(uint16_t reason, uint8_t data_len, const uint8_t *data); + +/** + * Tells if a SL_BT_API message is sensitive. + * + * @param[in] message_header The header of the SL_BT_API message + * @return 1 if the message is sensitive; otherwise 0 + */ +uint8_t sl_bt_is_sensitive_message(uint32_t message_header); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_rsp_user_message_to_target_id. + * + * This a utility helping a NCP host and target application to exchange user + * data. Do not use it in SoC mode. + */ +void sl_bt_send_rsp_user_message_to_target(uint16_t result, uint8_t data_len, uint8_t *data); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_evt_user_message_to_host_id. + * + * This a utility helping a NCP host and target application to exchange user + * data. Do not use it in SoC mode. + */ +void sl_bt_send_evt_user_message_to_host(uint8_t data_len, uint8_t *data); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_rsp_user_manage_event_filter_id. + * + * This a utility helping a NCP host and target application to manage event + * filter. Do not use it in SoC mode. + */ +void sl_bt_send_rsp_user_manage_event_filter(uint16_t result); + + +/** @} */ // end addtogroup sl_bt_utility_functions +/******************************************************************************/ + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h index 06cdcd6..52903bd 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h @@ -1,51 +1,51 @@ -/***************************************************************************//** - * @brief BT API source code compatibility for deprecated items - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_API_COMPATIBILITY_H -#define SL_BT_API_COMPATIBILITY_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Deprecated and replaced by sl_bt_gap_phy_t. - */ -typedef enum -{ - sl_bt_gap_1m_phy = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_2m_phy = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_coded_phy = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ - sl_bt_gap_any_phys = 0xff /**< (0xff) Any PHYs the device supports */ -} sl_bt_gap_phy_type_t; - -/** - * Deprecated and replaced by sl_bt_gap_phy_coding_t. - */ -typedef enum -{ - sl_bt_gap_1m_phy_uncoded = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_2m_phy_uncoded = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_coded_phy_125k = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ - sl_bt_gap_coded_phy_500k = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ -} sl_bt_gap_phy_and_coding_type_t; - - -#ifdef __cplusplus -} -#endif - +/***************************************************************************//** + * @brief BT API source code compatibility for deprecated items + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_API_COMPATIBILITY_H +#define SL_BT_API_COMPATIBILITY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Deprecated and replaced by sl_bt_gap_phy_t. + */ +typedef enum +{ + sl_bt_gap_1m_phy = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_2m_phy = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_coded_phy = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ + sl_bt_gap_any_phys = 0xff /**< (0xff) Any PHYs the device supports */ +} sl_bt_gap_phy_type_t; + +/** + * Deprecated and replaced by sl_bt_gap_phy_coding_t. + */ +typedef enum +{ + sl_bt_gap_1m_phy_uncoded = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_2m_phy_uncoded = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_coded_phy_125k = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ + sl_bt_gap_coded_phy_500k = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ +} sl_bt_gap_phy_and_coding_type_t; + + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ncp_host.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ncp_host.h index 937b829..2d16f8b 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ncp_host.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ncp_host.h @@ -1,165 +1,165 @@ -/***************************************************************************//** - * @brief Adaptation layer between host application and SL_BT_API protocol - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_NCP_HOST_H -#define SL_BT_NCP_HOST_H - -/***************************************************************************** - * - * This is an adaptation layer between host application and SL_BT_API protocol. - * It provides synchronization mechanism for SL_BT_API-protocol that allows - * using same application architecture between application in mcu and external - * host. - * - * Synchronization is done by waiting for response after each command. If - * any events are received during response waiting, they are queued and - * delivered next time sl_bt_wait_event is called. - * - * Queue length is controlled by defining macro "SL_BT_API_QUEUE_LEN", default is 30. - * Queue length depends on use cases and allowed host memory usage. - * - * SL_BT_API usage: - * Define library, it must be defined globally: - * SL_BT_API_DEFINE(); - * - * Declare and define output function, prototype is: - * void my_output(uint16_t len,uint8_t* data); - * Function sends "len" amount of data from pointer "data" to device. - * - * Declare and define input function, prototype is: - * void my_input(uint16_t len,uint8_t* data); - * Function reads "len" amount of data to pointer "data" from device. - * Function return nonzero if it failed. - * - * Initialize library,and provide output and input function: - * SL_BT_API_INITIALIZE(my_output,my_input); - * - * - * Receiving event: - * Events are received by sl_bt_wait_event-function. - * - * prototype: - * sl_bt_msg_t* sl_bt_wait_event(void) - * - * Event ID can be read from header of event by SL_BT_API_MSG_ID-macro. - * - * Event data can be accessed thru returned pointer. - * - * Example: - * sl_bt_msg_t *p; - * - * p=sl_bt_wait_event() - * - * if(SL_BT_API_MSG_ID(p->header)==sl_bt_evt_gatt_server_characteristic_status_id) - * { - * c=evt->evt_gatt_server_characteristic_status.connection;//accesses connection field of event data - * } - * - * Sending commands: - * SL_BT_API-commands can be sent by calling helper functions, that then build SL_BT_API-message and call output-function. - * Function then waits for response and return pointer to that message. - * - * Example: - * //Test that connection to the device is working - * if(sl_bt_system_hello() == SL_STATUS_OK) - * {//function call was successful - * - * } - * - * - ****************************************************************************/ - -#if _MSC_VER //msvc -#define inline __inline -#endif - -#include "sl_bt_api.h" - -#ifndef SL_BT_API_QUEUE_LEN -#define SL_BT_API_QUEUE_LEN 30 -#endif - -/** - * Structure defining a device type and the event queue where events of that - * type should be stored. - */ -typedef struct { - enum sl_bgapi_dev_types device_type; /*< Protocol/device type */ - uint32_t write_offset; /*< Pointer to the protocol consumer's write offset counter */ - uint32_t read_offset; /*< Pointer to the protocol consumer's write offset counter */ - sl_bt_msg_t *buffer; /*< Pointer to the protocol consumer's event queue buffer */ - uint32_t len; /*< Number of events possible to store in the queue */ -} bgapi_device_type_queue_t; - -extern bgapi_device_type_queue_t sl_bt_api_queue; - -sl_status_t sli_bgapi_register_device(bgapi_device_type_queue_t *queue); -bool sli_bgapi_device_queue_has_events(bgapi_device_type_queue_t *device_queue); -bool sli_bgapi_other_events_in_queue(enum sl_bgapi_dev_types my_device_type); -sl_status_t sli_bgapi_get_event(int block, sl_bt_msg_t *event, bgapi_device_type_queue_t *device_queue); - -/** - * Function that sends a message to the serial port. - * - * @param msg_len Length of the message - * @param msg_data The message data - */ -typedef void(*tx_func)(uint32_t msg_len, uint8_t* msg_data); - -/** - * @brief Function that reads data from serial port. - * - * @param[in] dataLength The amount of bytes to read. - * @param[out] data Buffer used for storing the data. - * @return The amount of bytes read or -1 on failure. - */ -typedef int32_t(*rx_func)(uint32_t dataLength, uint8_t* data); - -/** - * @brief Returns the number of bytes in the input buffer. - * @return The number of bytes in the input buffer or -1 on failure. - */ -typedef int32_t(*rx_peek_func)(void); - -/** - * Initialize NCP host Bluetooth API. - * - * @param ofunc The function for sending api messages - * @param ifunc The function for receiving api messages - * @return Status code - */ -sl_status_t sl_bt_api_initialize(tx_func ofunc, rx_func ifunc); - -/** - * Initialize NCP host Bluetooth API. - * - * @param ofunc The function for sending api messages - * @param ifunc The function for receiving api messages - * @param pfunc The function for getting the number of bytes in the input buffer - * @return Status code - */ -sl_status_t sl_bt_api_initialize_nonblock(tx_func ofunc, rx_func ifunc, rx_peek_func pfunc); - -extern void(*sl_bt_api_output)(uint32_t len1, uint8_t* data1); -extern int32_t (*sl_bt_api_input)(uint32_t len1, uint8_t* data1); -extern int32_t(*sl_bt_api_peek)(void); -void sl_bt_host_handle_command(); -void sl_bt_host_handle_command_noresponse(); -sl_status_t sl_bt_wait_event(sl_bt_msg_t *p); - -sl_bt_msg_t* sli_wait_for_bgapi_message(sl_bt_msg_t *response_buf); - -#endif +/***************************************************************************//** + * @brief Adaptation layer between host application and SL_BT_API protocol + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_NCP_HOST_H +#define SL_BT_NCP_HOST_H + +/***************************************************************************** + * + * This is an adaptation layer between host application and SL_BT_API protocol. + * It provides synchronization mechanism for SL_BT_API-protocol that allows + * using same application architecture between application in mcu and external + * host. + * + * Synchronization is done by waiting for response after each command. If + * any events are received during response waiting, they are queued and + * delivered next time sl_bt_wait_event is called. + * + * Queue length is controlled by defining macro "SL_BT_API_QUEUE_LEN", default is 30. + * Queue length depends on use cases and allowed host memory usage. + * + * SL_BT_API usage: + * Define library, it must be defined globally: + * SL_BT_API_DEFINE(); + * + * Declare and define output function, prototype is: + * void my_output(uint16_t len,uint8_t* data); + * Function sends "len" amount of data from pointer "data" to device. + * + * Declare and define input function, prototype is: + * void my_input(uint16_t len,uint8_t* data); + * Function reads "len" amount of data to pointer "data" from device. + * Function return nonzero if it failed. + * + * Initialize library,and provide output and input function: + * SL_BT_API_INITIALIZE(my_output,my_input); + * + * + * Receiving event: + * Events are received by sl_bt_wait_event-function. + * + * prototype: + * sl_bt_msg_t* sl_bt_wait_event(void) + * + * Event ID can be read from header of event by SL_BT_API_MSG_ID-macro. + * + * Event data can be accessed thru returned pointer. + * + * Example: + * sl_bt_msg_t *p; + * + * p=sl_bt_wait_event() + * + * if(SL_BT_API_MSG_ID(p->header)==sl_bt_evt_gatt_server_characteristic_status_id) + * { + * c=evt->evt_gatt_server_characteristic_status.connection;//accesses connection field of event data + * } + * + * Sending commands: + * SL_BT_API-commands can be sent by calling helper functions, that then build SL_BT_API-message and call output-function. + * Function then waits for response and return pointer to that message. + * + * Example: + * //Test that connection to the device is working + * if(sl_bt_system_hello() == SL_STATUS_OK) + * {//function call was successful + * + * } + * + * + ****************************************************************************/ + +#if _MSC_VER //msvc +#define inline __inline +#endif + +#include "sl_bt_api.h" + +#ifndef SL_BT_API_QUEUE_LEN +#define SL_BT_API_QUEUE_LEN 30 +#endif + +/** + * Structure defining a device type and the event queue where events of that + * type should be stored. + */ +typedef struct { + enum sl_bgapi_dev_types device_type; /*< Protocol/device type */ + uint32_t write_offset; /*< Pointer to the protocol consumer's write offset counter */ + uint32_t read_offset; /*< Pointer to the protocol consumer's write offset counter */ + sl_bt_msg_t *buffer; /*< Pointer to the protocol consumer's event queue buffer */ + uint32_t len; /*< Number of events possible to store in the queue */ +} bgapi_device_type_queue_t; + +extern bgapi_device_type_queue_t sl_bt_api_queue; + +sl_status_t sli_bgapi_register_device(bgapi_device_type_queue_t *queue); +bool sli_bgapi_device_queue_has_events(bgapi_device_type_queue_t *device_queue); +bool sli_bgapi_other_events_in_queue(enum sl_bgapi_dev_types my_device_type); +sl_status_t sli_bgapi_get_event(int block, sl_bt_msg_t *event, bgapi_device_type_queue_t *device_queue); + +/** + * Function that sends a message to the serial port. + * + * @param msg_len Length of the message + * @param msg_data The message data + */ +typedef void(*tx_func)(uint32_t msg_len, uint8_t* msg_data); + +/** + * @brief Function that reads data from serial port. + * + * @param[in] dataLength The amount of bytes to read. + * @param[out] data Buffer used for storing the data. + * @return The amount of bytes read or -1 on failure. + */ +typedef int32_t(*rx_func)(uint32_t dataLength, uint8_t* data); + +/** + * @brief Returns the number of bytes in the input buffer. + * @return The number of bytes in the input buffer or -1 on failure. + */ +typedef int32_t(*rx_peek_func)(void); + +/** + * Initialize NCP host Bluetooth API. + * + * @param ofunc The function for sending api messages + * @param ifunc The function for receiving api messages + * @return Status code + */ +sl_status_t sl_bt_api_initialize(tx_func ofunc, rx_func ifunc); + +/** + * Initialize NCP host Bluetooth API. + * + * @param ofunc The function for sending api messages + * @param ifunc The function for receiving api messages + * @param pfunc The function for getting the number of bytes in the input buffer + * @return Status code + */ +sl_status_t sl_bt_api_initialize_nonblock(tx_func ofunc, rx_func ifunc, rx_peek_func pfunc); + +extern void(*sl_bt_api_output)(uint32_t len1, uint8_t* data1); +extern int32_t (*sl_bt_api_input)(uint32_t len1, uint8_t* data1); +extern int32_t(*sl_bt_api_peek)(void); +void sl_bt_host_handle_command(); +void sl_bt_host_handle_command_noresponse(); +sl_status_t sl_bt_wait_event(sl_bt_msg_t *p); + +sl_bt_msg_t* sli_wait_for_bgapi_message(sl_bt_msg_t *response_buf); + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h index 934163f..78fc2d6 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h @@ -1,22 +1,22 @@ -/***************************************************************************//** - * @brief Deprecated Bluetooth API data type header - ******************************************************************************* - * # License - * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -/* - * "sl_bt_types.h" is deprecated and replaced by "sl_bt_api.h". We include - * "sl_bt_api.h" here to maintain source code compatibility with files that only - * include "sl_bt_types.h". - */ -#include "sl_bt_api.h" +/***************************************************************************//** + * @brief Deprecated Bluetooth API data type header + ******************************************************************************* + * # License + * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +/* + * "sl_bt_types.h" is deprecated and replaced by "sl_bt_api.h". We include + * "sl_bt_api.h" here to maintain source code compatibility with files that only + * include "sl_bt_types.h". + */ +#include "sl_bt_api.h" diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h index 66e9c9c..621010e 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h @@ -1,84 +1,84 @@ -/***************************************************************************//** - * @brief Bluetooth stack version definition - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_VERSION_H -#define SL_BT_VERSION_H - -/***************************************************************************//** - * @addtogroup sl_bt_version Bluetooth SDK version - * @brief Bluetooth SDK version information - * @{ - */ - -/** - * @brief The major number of Bluetooth SDK version - * - * An increment indicates incompatible Bluetooth API changes. - */ -#define SL_BT_VERSION_MAJOR 7 - -/** - * @brief The minor number of Bluetooth SDK version - * - * An increment indicates new backwards compatible functionalities. - */ -#define SL_BT_VERSION_MINOR 0 - -/** - * @brief The patch number of Bluetooth SDK version - * - * An increment indicates backwards compatible bug fixes. - */ -#define SL_BT_VERSION_PATCH 1 - -/** - * @brief The build number which the Bluetooth SDK was created from - */ -#define SL_BT_VERSION_BUILD 206 - -/** - * @brief The hash value of the build the Bluetooth SDK was created from - */ -#define SL_BT_VERSION_HASH {0x5b,0x56,0x2c,0x1a,0x0e,0x64,0x78,0xa5,0x6f,0x6d,0xcd,0xd4,0x17,0x91,0x18,0x7e,0xaf,0x86,0x8e,0xf6} - -/** - * Deprecated and replaced by SL_BT_VERSION_MAJOR - */ -#define BG_VERSION_MAJOR SL_BT_VERSION_MAJOR - -/** - * Deprecated and replaced by SL_BT_VERSION_MINOR - */ -#define BG_VERSION_MINOR SL_BT_VERSION_MINOR - -/** - * Deprecated and replaced by SL_BT_VERSION_PATCH - */ -#define BG_VERSION_PATCH SL_BT_VERSION_PATCH - -/** - * Deprecated and replaced by SL_BT_VERSION_BUILD - */ -#define BG_VERSION_BUILD SL_BT_VERSION_BUILD - -/** - * Deprecated and replaced by SL_BT_VERSION_HASH - */ -#define BG_VERSION_HASH SL_BT_VERSION_HASH - -/** @} */ // end addtogroup sl_bt_version - -#endif +/***************************************************************************//** + * @brief Bluetooth stack version definition + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_VERSION_H +#define SL_BT_VERSION_H + +/***************************************************************************//** + * @addtogroup sl_bt_version Bluetooth SDK version + * @brief Bluetooth SDK version information + * @{ + */ + +/** + * @brief The major number of Bluetooth SDK version + * + * An increment indicates incompatible Bluetooth API changes. + */ +#define SL_BT_VERSION_MAJOR 7 + +/** + * @brief The minor number of Bluetooth SDK version + * + * An increment indicates new backwards compatible functionalities. + */ +#define SL_BT_VERSION_MINOR 0 + +/** + * @brief The patch number of Bluetooth SDK version + * + * An increment indicates backwards compatible bug fixes. + */ +#define SL_BT_VERSION_PATCH 1 + +/** + * @brief The build number which the Bluetooth SDK was created from + */ +#define SL_BT_VERSION_BUILD 206 + +/** + * @brief The hash value of the build the Bluetooth SDK was created from + */ +#define SL_BT_VERSION_HASH {0x5b,0x56,0x2c,0x1a,0x0e,0x64,0x78,0xa5,0x6f,0x6d,0xcd,0xd4,0x17,0x91,0x18,0x7e,0xaf,0x86,0x8e,0xf6} + +/** + * Deprecated and replaced by SL_BT_VERSION_MAJOR + */ +#define BG_VERSION_MAJOR SL_BT_VERSION_MAJOR + +/** + * Deprecated and replaced by SL_BT_VERSION_MINOR + */ +#define BG_VERSION_MINOR SL_BT_VERSION_MINOR + +/** + * Deprecated and replaced by SL_BT_VERSION_PATCH + */ +#define BG_VERSION_PATCH SL_BT_VERSION_PATCH + +/** + * Deprecated and replaced by SL_BT_VERSION_BUILD + */ +#define BG_VERSION_BUILD SL_BT_VERSION_BUILD + +/** + * Deprecated and replaced by SL_BT_VERSION_HASH + */ +#define BG_VERSION_HASH SL_BT_VERSION_HASH + +/** @} */ // end addtogroup sl_bt_version + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_api.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_api.h index a7af15a..e1459ee 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_api.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_api.h @@ -1,5536 +1,5536 @@ -/***************************************************************************//** - * @brief SL_BT_API library at application layer provided as source code - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_API_H -#define SLI_BT_API_H -#define VERSION no_link_tables - -#include "sl_bt_api.h" - -#ifdef __cplusplus -extern "C" { -#endif - -enum sli_bt_class_id -{ - sli_bt_dfu_class_id = 0x00, - sli_bt_system_class_id = 0x01, - sli_bt_resource_class_id = 0x5f, - sli_bt_gap_class_id = 0x02, - sli_bt_advertiser_class_id = 0x04, - sli_bt_legacy_advertiser_class_id = 0x56, - sli_bt_extended_advertiser_class_id = 0x57, - sli_bt_periodic_advertiser_class_id = 0x58, - sli_bt_scanner_class_id = 0x05, - sli_bt_sync_class_id = 0x42, - sli_bt_sync_scanner_class_id = 0x50, - sli_bt_past_receiver_class_id = 0x51, - sli_bt_advertiser_past_class_id = 0x52, - sli_bt_sync_past_class_id = 0x5b, - sli_bt_periodic_sync_class_id = 0x53, - sli_bt_pawr_sync_class_id = 0x54, - sli_bt_pawr_advertiser_class_id = 0x55, - sli_bt_connection_class_id = 0x06, - sli_bt_gatt_class_id = 0x09, - sli_bt_gattdb_class_id = 0x46, - sli_bt_gatt_server_class_id = 0x0a, - sli_bt_nvm_class_id = 0x0d, - sli_bt_test_class_id = 0x0e, - sli_bt_sm_class_id = 0x0f, - sli_bt_external_bondingdb_class_id = 0x5c, - sli_bt_resolving_list_class_id = 0x5d, - sli_bt_accept_list_class_id = 0x5e, - sli_bt_ota_class_id = 0x10, - sli_bt_coex_class_id = 0x20, - sli_bt_cs_class_id = 0x59, - sli_bt_cs_test_class_id = 0x5A, - sli_bt_l2cap_class_id = 0x43, - sli_bt_cte_transmitter_class_id = 0x44, - sli_bt_cte_receiver_class_id = 0x45, - sli_bt_connection_analyzer_class_id = 0x48, - sli_bt_user_class_id = 0xff, -}; - -enum sli_bt_command_id -{ - sli_bt_dfu_flash_set_address_command_id = 0x01, - sli_bt_dfu_flash_upload_command_id = 0x02, - sli_bt_dfu_flash_upload_finish_command_id = 0x03, - sli_bt_system_hello_command_id = 0x00, - sli_bt_system_start_bluetooth_command_id = 0x1c, - sli_bt_system_stop_bluetooth_command_id = 0x1d, - sli_bt_system_forcefully_stop_bluetooth_command_id = 0x1e, - sli_bt_system_get_version_command_id = 0x1b, - sli_bt_system_reset_command_id = 0x01, - sli_bt_system_halt_command_id = 0x0c, - sli_bt_system_linklayer_configure_command_id = 0x0e, - sli_bt_system_set_tx_power_command_id = 0x17, - sli_bt_system_get_tx_power_setting_command_id = 0x18, - sli_bt_system_set_identity_address_command_id = 0x13, - sli_bt_system_get_identity_address_command_id = 0x15, - sli_bt_system_get_random_data_command_id = 0x0b, - sli_bt_system_data_buffer_write_command_id = 0x12, - sli_bt_system_data_buffer_clear_command_id = 0x14, - sli_bt_system_get_counters_command_id = 0x0f, - sli_bt_system_set_lazy_soft_timer_command_id = 0x1a, - sli_bt_resource_get_status_command_id = 0x00, - sli_bt_resource_set_report_threshold_command_id = 0x01, - sli_bt_resource_enable_connection_tx_report_command_id = 0x02, - sli_bt_resource_get_connection_tx_status_command_id = 0x03, - sli_bt_resource_disable_connection_tx_report_command_id = 0x04, - sli_bt_gap_set_privacy_mode_command_id = 0x01, - sli_bt_gap_set_data_channel_classification_command_id = 0x02, - sli_bt_gap_enable_whitelisting_command_id = 0x03, - sli_bt_gap_set_identity_address_command_id = 0x04, - sli_bt_advertiser_create_set_command_id = 0x01, - sli_bt_advertiser_configure_command_id = 0x12, - sli_bt_advertiser_set_timing_command_id = 0x03, - sli_bt_advertiser_set_channel_map_command_id = 0x04, - sli_bt_advertiser_set_tx_power_command_id = 0x0b, - sli_bt_advertiser_set_report_scan_request_command_id = 0x05, - sli_bt_advertiser_set_random_address_command_id = 0x10, - sli_bt_advertiser_clear_random_address_command_id = 0x11, - sli_bt_advertiser_stop_command_id = 0x0a, - sli_bt_advertiser_delete_set_command_id = 0x02, - sli_bt_advertiser_set_phy_command_id = 0x06, - sli_bt_advertiser_set_configuration_command_id = 0x07, - sli_bt_advertiser_clear_configuration_command_id = 0x08, - sli_bt_advertiser_set_data_command_id = 0x0f, - sli_bt_advertiser_set_long_data_command_id = 0x0e, - sli_bt_advertiser_start_command_id = 0x09, - sli_bt_advertiser_start_periodic_advertising_command_id = 0x0c, - sli_bt_advertiser_stop_periodic_advertising_command_id = 0x0d, - sli_bt_legacy_advertiser_set_data_command_id = 0x00, - sli_bt_legacy_advertiser_generate_data_command_id = 0x01, - sli_bt_legacy_advertiser_start_command_id = 0x02, - sli_bt_legacy_advertiser_start_directed_command_id = 0x03, - sli_bt_extended_advertiser_set_phy_command_id = 0x00, - sli_bt_extended_advertiser_set_data_command_id = 0x01, - sli_bt_extended_advertiser_set_long_data_command_id = 0x02, - sli_bt_extended_advertiser_generate_data_command_id = 0x03, - sli_bt_extended_advertiser_start_command_id = 0x04, - sli_bt_extended_advertiser_start_directed_command_id = 0x05, - sli_bt_periodic_advertiser_set_data_command_id = 0x00, - sli_bt_periodic_advertiser_set_long_data_command_id = 0x01, - sli_bt_periodic_advertiser_start_command_id = 0x02, - sli_bt_periodic_advertiser_stop_command_id = 0x03, - sli_bt_scanner_set_parameters_command_id = 0x06, - sli_bt_scanner_set_parameters_and_filter_command_id = 0x07, - sli_bt_scanner_stop_command_id = 0x05, - sli_bt_scanner_set_timing_command_id = 0x01, - sli_bt_scanner_set_mode_command_id = 0x02, - sli_bt_scanner_start_command_id = 0x03, - sli_bt_sync_set_parameters_command_id = 0x02, - sli_bt_sync_open_command_id = 0x00, - sli_bt_sync_set_reporting_mode_command_id = 0x03, - sli_bt_sync_update_sync_parameters_command_id = 0x04, - sli_bt_sync_close_command_id = 0x01, - sli_bt_sync_scanner_set_sync_parameters_command_id = 0x00, - sli_bt_sync_scanner_open_command_id = 0x01, - sli_bt_past_receiver_set_default_sync_receive_parameters_command_id = 0x00, - sli_bt_past_receiver_set_sync_receive_parameters_command_id = 0x01, - sli_bt_advertiser_past_transfer_command_id = 0x00, - sli_bt_sync_past_transfer_command_id = 0x00, - sli_bt_pawr_sync_set_sync_subevents_command_id = 0x02, - sli_bt_pawr_sync_set_response_data_command_id = 0x03, - sli_bt_pawr_advertiser_start_command_id = 0x00, - sli_bt_pawr_advertiser_set_subevent_data_command_id = 0x01, - sli_bt_pawr_advertiser_create_connection_command_id = 0x02, - sli_bt_pawr_advertiser_stop_command_id = 0x03, - sli_bt_connection_set_default_parameters_command_id = 0x00, - sli_bt_connection_set_default_preferred_phy_command_id = 0x01, - sli_bt_connection_set_default_data_length_command_id = 0x10, - sli_bt_connection_open_command_id = 0x04, - sli_bt_connection_set_parameters_command_id = 0x06, - sli_bt_connection_set_preferred_phy_command_id = 0x08, - sli_bt_connection_disable_slave_latency_command_id = 0x03, - sli_bt_connection_get_median_rssi_command_id = 0x15, - sli_bt_connection_read_channel_map_command_id = 0x07, - sli_bt_connection_set_power_reporting_command_id = 0x09, - sli_bt_connection_set_remote_power_reporting_command_id = 0x0a, - sli_bt_connection_get_tx_power_command_id = 0x0b, - sli_bt_connection_get_remote_tx_power_command_id = 0x0c, - sli_bt_connection_set_tx_power_command_id = 0x12, - sli_bt_connection_read_remote_used_features_command_id = 0x0d, - sli_bt_connection_get_security_status_command_id = 0x0e, - sli_bt_connection_set_data_length_command_id = 0x11, - sli_bt_connection_read_statistics_command_id = 0x13, - sli_bt_connection_get_scheduling_details_command_id = 0x14, - sli_bt_connection_close_command_id = 0x05, - sli_bt_connection_forcefully_close_command_id = 0x0f, - sli_bt_connection_get_rssi_command_id = 0x02, - sli_bt_gatt_set_max_mtu_command_id = 0x00, - sli_bt_gatt_discover_primary_services_command_id = 0x01, - sli_bt_gatt_discover_primary_services_by_uuid_command_id = 0x02, - sli_bt_gatt_find_included_services_command_id = 0x10, - sli_bt_gatt_discover_characteristics_command_id = 0x03, - sli_bt_gatt_discover_characteristics_by_uuid_command_id = 0x04, - sli_bt_gatt_discover_descriptors_command_id = 0x06, - sli_bt_gatt_discover_characteristic_descriptors_command_id = 0x14, - sli_bt_gatt_set_characteristic_notification_command_id = 0x05, - sli_bt_gatt_send_characteristic_confirmation_command_id = 0x0d, - sli_bt_gatt_read_characteristic_value_command_id = 0x07, - sli_bt_gatt_read_characteristic_value_from_offset_command_id = 0x12, - sli_bt_gatt_read_multiple_characteristic_values_command_id = 0x11, - sli_bt_gatt_read_characteristic_value_by_uuid_command_id = 0x08, - sli_bt_gatt_write_characteristic_value_command_id = 0x09, - sli_bt_gatt_write_characteristic_value_without_response_command_id = 0x0a, - sli_bt_gatt_prepare_characteristic_value_write_command_id = 0x0b, - sli_bt_gatt_prepare_characteristic_value_reliable_write_command_id = 0x13, - sli_bt_gatt_execute_characteristic_value_write_command_id = 0x0c, - sli_bt_gatt_read_descriptor_value_command_id = 0x0e, - sli_bt_gatt_write_descriptor_value_command_id = 0x0f, - sli_bt_gattdb_new_session_command_id = 0x00, - sli_bt_gattdb_add_service_command_id = 0x01, - sli_bt_gattdb_remove_service_command_id = 0x02, - sli_bt_gattdb_add_included_service_command_id = 0x03, - sli_bt_gattdb_remove_included_service_command_id = 0x04, - sli_bt_gattdb_add_uuid16_characteristic_command_id = 0x05, - sli_bt_gattdb_add_uuid128_characteristic_command_id = 0x06, - sli_bt_gattdb_remove_characteristic_command_id = 0x07, - sli_bt_gattdb_add_uuid16_descriptor_command_id = 0x08, - sli_bt_gattdb_add_uuid128_descriptor_command_id = 0x09, - sli_bt_gattdb_remove_descriptor_command_id = 0x0a, - sli_bt_gattdb_start_service_command_id = 0x0b, - sli_bt_gattdb_stop_service_command_id = 0x0c, - sli_bt_gattdb_start_characteristic_command_id = 0x0d, - sli_bt_gattdb_stop_characteristic_command_id = 0x0e, - sli_bt_gattdb_commit_command_id = 0x0f, - sli_bt_gattdb_abort_command_id = 0x10, - sli_bt_gatt_server_set_max_mtu_command_id = 0x0a, - sli_bt_gatt_server_get_mtu_command_id = 0x0b, - sli_bt_gatt_server_find_attribute_command_id = 0x06, - sli_bt_gatt_server_read_attribute_value_command_id = 0x00, - sli_bt_gatt_server_read_attribute_type_command_id = 0x01, - sli_bt_gatt_server_write_attribute_value_command_id = 0x02, - sli_bt_gatt_server_send_user_read_response_command_id = 0x03, - sli_bt_gatt_server_send_user_write_response_command_id = 0x04, - sli_bt_gatt_server_send_notification_command_id = 0x0f, - sli_bt_gatt_server_send_indication_command_id = 0x10, - sli_bt_gatt_server_notify_all_command_id = 0x11, - sli_bt_gatt_server_read_client_configuration_command_id = 0x12, - sli_bt_gatt_server_send_user_prepare_write_response_command_id = 0x14, - sli_bt_gatt_server_set_capabilities_command_id = 0x08, - sli_bt_gatt_server_enable_capabilities_command_id = 0x0c, - sli_bt_gatt_server_disable_capabilities_command_id = 0x0d, - sli_bt_gatt_server_get_enabled_capabilities_command_id = 0x0e, - sli_bt_gatt_server_read_client_supported_features_command_id = 0x15, - sli_bt_nvm_save_command_id = 0x02, - sli_bt_nvm_load_command_id = 0x03, - sli_bt_nvm_erase_command_id = 0x04, - sli_bt_nvm_erase_all_command_id = 0x01, - sli_bt_test_dtm_tx_v4_command_id = 0x03, - sli_bt_test_dtm_tx_cw_command_id = 0x04, - sli_bt_test_dtm_rx_command_id = 0x01, - sli_bt_test_dtm_end_command_id = 0x02, - sli_bt_sm_configure_command_id = 0x01, - sli_bt_sm_set_minimum_key_size_command_id = 0x14, - sli_bt_sm_set_debug_mode_command_id = 0x0f, - sli_bt_sm_add_to_whitelist_command_id = 0x13, - sli_bt_sm_store_bonding_configuration_command_id = 0x02, - sli_bt_sm_set_bondable_mode_command_id = 0x00, - sli_bt_sm_set_passkey_command_id = 0x10, - sli_bt_sm_increase_security_command_id = 0x04, - sli_bt_sm_enter_passkey_command_id = 0x08, - sli_bt_sm_passkey_confirm_command_id = 0x09, - sli_bt_sm_bonding_confirm_command_id = 0x0e, - sli_bt_sm_delete_bonding_command_id = 0x06, - sli_bt_sm_delete_bondings_command_id = 0x07, - sli_bt_sm_get_bonding_handles_command_id = 0x15, - sli_bt_sm_get_bonding_details_command_id = 0x16, - sli_bt_sm_find_bonding_by_address_command_id = 0x17, - sli_bt_sm_resolve_rpa_command_id = 0x1d, - sli_bt_sm_set_bonding_key_command_id = 0x18, - sli_bt_sm_set_legacy_oob_command_id = 0x19, - sli_bt_sm_set_oob_command_id = 0x1a, - sli_bt_sm_set_remote_oob_command_id = 0x1b, - sli_bt_sm_set_bonding_data_command_id = 0x1c, - sli_bt_external_bondingdb_set_data_command_id = 0x00, - sli_bt_resolving_list_add_device_by_bonding_command_id = 0x00, - sli_bt_resolving_list_add_device_by_address_command_id = 0x01, - sli_bt_resolving_list_remove_device_by_bonding_command_id = 0x02, - sli_bt_resolving_list_remove_device_by_address_command_id = 0x03, - sli_bt_resolving_list_remove_all_devices_command_id = 0x04, - sli_bt_accept_list_add_device_by_bonding_command_id = 0x00, - sli_bt_accept_list_add_device_by_address_command_id = 0x01, - sli_bt_accept_list_remove_device_by_bonding_command_id = 0x02, - sli_bt_accept_list_remove_device_by_address_command_id = 0x03, - sli_bt_accept_list_remove_all_devices_command_id = 0x04, - sli_bt_ota_set_device_name_command_id = 0x01, - sli_bt_ota_set_advertising_data_command_id = 0x02, - sli_bt_ota_set_configuration_command_id = 0x03, - sli_bt_ota_set_rf_path_command_id = 0x04, - sli_bt_coex_set_options_command_id = 0x00, - sli_bt_coex_set_parameters_command_id = 0x02, - sli_bt_coex_set_directional_priority_pulse_command_id = 0x03, - sli_bt_coex_get_parameters_command_id = 0x04, - sli_bt_coex_get_counters_command_id = 0x01, - sli_bt_cs_security_enable_command_id = 0x00, - sli_bt_cs_set_default_settings_command_id = 0x01, - sli_bt_cs_create_config_command_id = 0x02, - sli_bt_cs_remove_config_command_id = 0x03, - sli_bt_cs_set_channel_classification_command_id = 0x04, - sli_bt_cs_set_procedure_parameters_command_id = 0x05, - sli_bt_cs_procedure_enable_command_id = 0x06, - sli_bt_cs_set_antenna_configuration_command_id = 0x07, - sli_bt_cs_read_local_supported_capabilities_command_id = 0x08, - sli_bt_cs_test_start_command_id = 0x00, - sli_bt_l2cap_open_le_channel_command_id = 0x01, - sli_bt_l2cap_send_le_channel_open_response_command_id = 0x02, - sli_bt_l2cap_channel_send_data_command_id = 0x03, - sli_bt_l2cap_channel_send_credit_command_id = 0x04, - sli_bt_l2cap_close_channel_command_id = 0x05, - sli_bt_cte_transmitter_set_dtm_parameters_command_id = 0x04, - sli_bt_cte_transmitter_clear_dtm_parameters_command_id = 0x05, - sli_bt_cte_transmitter_enable_connection_cte_command_id = 0x00, - sli_bt_cte_transmitter_disable_connection_cte_command_id = 0x01, - sli_bt_cte_transmitter_enable_connectionless_cte_command_id = 0x02, - sli_bt_cte_transmitter_disable_connectionless_cte_command_id = 0x03, - sli_bt_cte_transmitter_enable_silabs_cte_command_id = 0x06, - sli_bt_cte_transmitter_disable_silabs_cte_command_id = 0x07, - sli_bt_cte_receiver_set_dtm_parameters_command_id = 0x05, - sli_bt_cte_receiver_clear_dtm_parameters_command_id = 0x06, - sli_bt_cte_receiver_set_sync_cte_type_command_id = 0x09, - sli_bt_cte_receiver_set_default_sync_receive_parameters_command_id = 0x0a, - sli_bt_cte_receiver_set_sync_receive_parameters_command_id = 0x0b, - sli_bt_cte_receiver_configure_command_id = 0x00, - sli_bt_cte_receiver_enable_connection_cte_command_id = 0x01, - sli_bt_cte_receiver_disable_connection_cte_command_id = 0x02, - sli_bt_cte_receiver_enable_connectionless_cte_command_id = 0x03, - sli_bt_cte_receiver_disable_connectionless_cte_command_id = 0x04, - sli_bt_cte_receiver_enable_silabs_cte_command_id = 0x07, - sli_bt_cte_receiver_disable_silabs_cte_command_id = 0x08, - sli_bt_connection_analyzer_start_command_id = 0x00, - sli_bt_connection_analyzer_stop_command_id = 0x01, - sli_bt_user_message_to_target_command_id = 0x00, - sli_bt_user_manage_event_filter_command_id = 0x01, - sli_bt_user_reset_to_dfu_command_id = 0x02, -}; - -enum sli_bt_response_id -{ - sli_bt_dfu_flash_set_address_response_id = 0x01, - sli_bt_dfu_flash_upload_response_id = 0x02, - sli_bt_dfu_flash_upload_finish_response_id = 0x03, - sli_bt_system_hello_response_id = 0x00, - sli_bt_system_start_bluetooth_response_id = 0x1c, - sli_bt_system_stop_bluetooth_response_id = 0x1d, - sli_bt_system_forcefully_stop_bluetooth_response_id = 0x1e, - sli_bt_system_get_version_response_id = 0x1b, - sli_bt_system_reset_response_id = 0x01, - sli_bt_system_halt_response_id = 0x0c, - sli_bt_system_linklayer_configure_response_id = 0x0e, - sli_bt_system_set_tx_power_response_id = 0x17, - sli_bt_system_get_tx_power_setting_response_id = 0x18, - sli_bt_system_set_identity_address_response_id = 0x13, - sli_bt_system_get_identity_address_response_id = 0x15, - sli_bt_system_get_random_data_response_id = 0x0b, - sli_bt_system_data_buffer_write_response_id = 0x12, - sli_bt_system_data_buffer_clear_response_id = 0x14, - sli_bt_system_get_counters_response_id = 0x0f, - sli_bt_system_set_lazy_soft_timer_response_id = 0x1a, - sli_bt_resource_get_status_response_id = 0x00, - sli_bt_resource_set_report_threshold_response_id = 0x01, - sli_bt_resource_enable_connection_tx_report_response_id = 0x02, - sli_bt_resource_get_connection_tx_status_response_id = 0x03, - sli_bt_resource_disable_connection_tx_report_response_id = 0x04, - sli_bt_gap_set_privacy_mode_response_id = 0x01, - sli_bt_gap_set_data_channel_classification_response_id = 0x02, - sli_bt_gap_enable_whitelisting_response_id = 0x03, - sli_bt_gap_set_identity_address_response_id = 0x04, - sli_bt_advertiser_create_set_response_id = 0x01, - sli_bt_advertiser_configure_response_id = 0x12, - sli_bt_advertiser_set_timing_response_id = 0x03, - sli_bt_advertiser_set_channel_map_response_id = 0x04, - sli_bt_advertiser_set_tx_power_response_id = 0x0b, - sli_bt_advertiser_set_report_scan_request_response_id = 0x05, - sli_bt_advertiser_set_random_address_response_id = 0x10, - sli_bt_advertiser_clear_random_address_response_id = 0x11, - sli_bt_advertiser_stop_response_id = 0x0a, - sli_bt_advertiser_delete_set_response_id = 0x02, - sli_bt_advertiser_set_phy_response_id = 0x06, - sli_bt_advertiser_set_configuration_response_id = 0x07, - sli_bt_advertiser_clear_configuration_response_id = 0x08, - sli_bt_advertiser_set_data_response_id = 0x0f, - sli_bt_advertiser_set_long_data_response_id = 0x0e, - sli_bt_advertiser_start_response_id = 0x09, - sli_bt_advertiser_start_periodic_advertising_response_id = 0x0c, - sli_bt_advertiser_stop_periodic_advertising_response_id = 0x0d, - sli_bt_legacy_advertiser_set_data_response_id = 0x00, - sli_bt_legacy_advertiser_generate_data_response_id = 0x01, - sli_bt_legacy_advertiser_start_response_id = 0x02, - sli_bt_legacy_advertiser_start_directed_response_id = 0x03, - sli_bt_extended_advertiser_set_phy_response_id = 0x00, - sli_bt_extended_advertiser_set_data_response_id = 0x01, - sli_bt_extended_advertiser_set_long_data_response_id = 0x02, - sli_bt_extended_advertiser_generate_data_response_id = 0x03, - sli_bt_extended_advertiser_start_response_id = 0x04, - sli_bt_extended_advertiser_start_directed_response_id = 0x05, - sli_bt_periodic_advertiser_set_data_response_id = 0x00, - sli_bt_periodic_advertiser_set_long_data_response_id = 0x01, - sli_bt_periodic_advertiser_start_response_id = 0x02, - sli_bt_periodic_advertiser_stop_response_id = 0x03, - sli_bt_scanner_set_parameters_response_id = 0x06, - sli_bt_scanner_set_parameters_and_filter_response_id = 0x07, - sli_bt_scanner_stop_response_id = 0x05, - sli_bt_scanner_set_timing_response_id = 0x01, - sli_bt_scanner_set_mode_response_id = 0x02, - sli_bt_scanner_start_response_id = 0x03, - sli_bt_sync_set_parameters_response_id = 0x02, - sli_bt_sync_open_response_id = 0x00, - sli_bt_sync_set_reporting_mode_response_id = 0x03, - sli_bt_sync_update_sync_parameters_response_id = 0x04, - sli_bt_sync_close_response_id = 0x01, - sli_bt_sync_scanner_set_sync_parameters_response_id = 0x00, - sli_bt_sync_scanner_open_response_id = 0x01, - sli_bt_past_receiver_set_default_sync_receive_parameters_response_id = 0x00, - sli_bt_past_receiver_set_sync_receive_parameters_response_id = 0x01, - sli_bt_advertiser_past_transfer_response_id = 0x00, - sli_bt_sync_past_transfer_response_id = 0x00, - sli_bt_pawr_sync_set_sync_subevents_response_id = 0x02, - sli_bt_pawr_sync_set_response_data_response_id = 0x03, - sli_bt_pawr_advertiser_start_response_id = 0x00, - sli_bt_pawr_advertiser_set_subevent_data_response_id = 0x01, - sli_bt_pawr_advertiser_create_connection_response_id = 0x02, - sli_bt_pawr_advertiser_stop_response_id = 0x03, - sli_bt_connection_set_default_parameters_response_id = 0x00, - sli_bt_connection_set_default_preferred_phy_response_id = 0x01, - sli_bt_connection_set_default_data_length_response_id = 0x10, - sli_bt_connection_open_response_id = 0x04, - sli_bt_connection_set_parameters_response_id = 0x06, - sli_bt_connection_set_preferred_phy_response_id = 0x08, - sli_bt_connection_disable_slave_latency_response_id = 0x03, - sli_bt_connection_get_median_rssi_response_id = 0x15, - sli_bt_connection_read_channel_map_response_id = 0x07, - sli_bt_connection_set_power_reporting_response_id = 0x09, - sli_bt_connection_set_remote_power_reporting_response_id = 0x0a, - sli_bt_connection_get_tx_power_response_id = 0x0b, - sli_bt_connection_get_remote_tx_power_response_id = 0x0c, - sli_bt_connection_set_tx_power_response_id = 0x12, - sli_bt_connection_read_remote_used_features_response_id = 0x0d, - sli_bt_connection_get_security_status_response_id = 0x0e, - sli_bt_connection_set_data_length_response_id = 0x11, - sli_bt_connection_read_statistics_response_id = 0x13, - sli_bt_connection_get_scheduling_details_response_id = 0x14, - sli_bt_connection_close_response_id = 0x05, - sli_bt_connection_forcefully_close_response_id = 0x0f, - sli_bt_connection_get_rssi_response_id = 0x02, - sli_bt_gatt_set_max_mtu_response_id = 0x00, - sli_bt_gatt_discover_primary_services_response_id = 0x01, - sli_bt_gatt_discover_primary_services_by_uuid_response_id = 0x02, - sli_bt_gatt_find_included_services_response_id = 0x10, - sli_bt_gatt_discover_characteristics_response_id = 0x03, - sli_bt_gatt_discover_characteristics_by_uuid_response_id = 0x04, - sli_bt_gatt_discover_descriptors_response_id = 0x06, - sli_bt_gatt_discover_characteristic_descriptors_response_id = 0x14, - sli_bt_gatt_set_characteristic_notification_response_id = 0x05, - sli_bt_gatt_send_characteristic_confirmation_response_id = 0x0d, - sli_bt_gatt_read_characteristic_value_response_id = 0x07, - sli_bt_gatt_read_characteristic_value_from_offset_response_id = 0x12, - sli_bt_gatt_read_multiple_characteristic_values_response_id = 0x11, - sli_bt_gatt_read_characteristic_value_by_uuid_response_id = 0x08, - sli_bt_gatt_write_characteristic_value_response_id = 0x09, - sli_bt_gatt_write_characteristic_value_without_response_response_id = 0x0a, - sli_bt_gatt_prepare_characteristic_value_write_response_id = 0x0b, - sli_bt_gatt_prepare_characteristic_value_reliable_write_response_id = 0x13, - sli_bt_gatt_execute_characteristic_value_write_response_id = 0x0c, - sli_bt_gatt_read_descriptor_value_response_id = 0x0e, - sli_bt_gatt_write_descriptor_value_response_id = 0x0f, - sli_bt_gattdb_new_session_response_id = 0x00, - sli_bt_gattdb_add_service_response_id = 0x01, - sli_bt_gattdb_remove_service_response_id = 0x02, - sli_bt_gattdb_add_included_service_response_id = 0x03, - sli_bt_gattdb_remove_included_service_response_id = 0x04, - sli_bt_gattdb_add_uuid16_characteristic_response_id = 0x05, - sli_bt_gattdb_add_uuid128_characteristic_response_id = 0x06, - sli_bt_gattdb_remove_characteristic_response_id = 0x07, - sli_bt_gattdb_add_uuid16_descriptor_response_id = 0x08, - sli_bt_gattdb_add_uuid128_descriptor_response_id = 0x09, - sli_bt_gattdb_remove_descriptor_response_id = 0x0a, - sli_bt_gattdb_start_service_response_id = 0x0b, - sli_bt_gattdb_stop_service_response_id = 0x0c, - sli_bt_gattdb_start_characteristic_response_id = 0x0d, - sli_bt_gattdb_stop_characteristic_response_id = 0x0e, - sli_bt_gattdb_commit_response_id = 0x0f, - sli_bt_gattdb_abort_response_id = 0x10, - sli_bt_gatt_server_set_max_mtu_response_id = 0x0a, - sli_bt_gatt_server_get_mtu_response_id = 0x0b, - sli_bt_gatt_server_find_attribute_response_id = 0x06, - sli_bt_gatt_server_read_attribute_value_response_id = 0x00, - sli_bt_gatt_server_read_attribute_type_response_id = 0x01, - sli_bt_gatt_server_write_attribute_value_response_id = 0x02, - sli_bt_gatt_server_send_user_read_response_response_id = 0x03, - sli_bt_gatt_server_send_user_write_response_response_id = 0x04, - sli_bt_gatt_server_send_notification_response_id = 0x0f, - sli_bt_gatt_server_send_indication_response_id = 0x10, - sli_bt_gatt_server_notify_all_response_id = 0x11, - sli_bt_gatt_server_read_client_configuration_response_id = 0x12, - sli_bt_gatt_server_send_user_prepare_write_response_response_id = 0x14, - sli_bt_gatt_server_set_capabilities_response_id = 0x08, - sli_bt_gatt_server_enable_capabilities_response_id = 0x0c, - sli_bt_gatt_server_disable_capabilities_response_id = 0x0d, - sli_bt_gatt_server_get_enabled_capabilities_response_id = 0x0e, - sli_bt_gatt_server_read_client_supported_features_response_id = 0x15, - sli_bt_nvm_save_response_id = 0x02, - sli_bt_nvm_load_response_id = 0x03, - sli_bt_nvm_erase_response_id = 0x04, - sli_bt_nvm_erase_all_response_id = 0x01, - sli_bt_test_dtm_tx_v4_response_id = 0x03, - sli_bt_test_dtm_tx_cw_response_id = 0x04, - sli_bt_test_dtm_rx_response_id = 0x01, - sli_bt_test_dtm_end_response_id = 0x02, - sli_bt_sm_configure_response_id = 0x01, - sli_bt_sm_set_minimum_key_size_response_id = 0x14, - sli_bt_sm_set_debug_mode_response_id = 0x0f, - sli_bt_sm_add_to_whitelist_response_id = 0x13, - sli_bt_sm_store_bonding_configuration_response_id = 0x02, - sli_bt_sm_set_bondable_mode_response_id = 0x00, - sli_bt_sm_set_passkey_response_id = 0x10, - sli_bt_sm_increase_security_response_id = 0x04, - sli_bt_sm_enter_passkey_response_id = 0x08, - sli_bt_sm_passkey_confirm_response_id = 0x09, - sli_bt_sm_bonding_confirm_response_id = 0x0e, - sli_bt_sm_delete_bonding_response_id = 0x06, - sli_bt_sm_delete_bondings_response_id = 0x07, - sli_bt_sm_get_bonding_handles_response_id = 0x15, - sli_bt_sm_get_bonding_details_response_id = 0x16, - sli_bt_sm_find_bonding_by_address_response_id = 0x17, - sli_bt_sm_resolve_rpa_response_id = 0x1d, - sli_bt_sm_set_bonding_key_response_id = 0x18, - sli_bt_sm_set_legacy_oob_response_id = 0x19, - sli_bt_sm_set_oob_response_id = 0x1a, - sli_bt_sm_set_remote_oob_response_id = 0x1b, - sli_bt_sm_set_bonding_data_response_id = 0x1c, - sli_bt_external_bondingdb_set_data_response_id = 0x00, - sli_bt_resolving_list_add_device_by_bonding_response_id = 0x00, - sli_bt_resolving_list_add_device_by_address_response_id = 0x01, - sli_bt_resolving_list_remove_device_by_bonding_response_id = 0x02, - sli_bt_resolving_list_remove_device_by_address_response_id = 0x03, - sli_bt_resolving_list_remove_all_devices_response_id = 0x04, - sli_bt_accept_list_add_device_by_bonding_response_id = 0x00, - sli_bt_accept_list_add_device_by_address_response_id = 0x01, - sli_bt_accept_list_remove_device_by_bonding_response_id = 0x02, - sli_bt_accept_list_remove_device_by_address_response_id = 0x03, - sli_bt_accept_list_remove_all_devices_response_id = 0x04, - sli_bt_ota_set_device_name_response_id = 0x01, - sli_bt_ota_set_advertising_data_response_id = 0x02, - sli_bt_ota_set_configuration_response_id = 0x03, - sli_bt_ota_set_rf_path_response_id = 0x04, - sli_bt_coex_set_options_response_id = 0x00, - sli_bt_coex_set_parameters_response_id = 0x02, - sli_bt_coex_set_directional_priority_pulse_response_id = 0x03, - sli_bt_coex_get_parameters_response_id = 0x04, - sli_bt_coex_get_counters_response_id = 0x01, - sli_bt_cs_security_enable_response_id = 0x00, - sli_bt_cs_set_default_settings_response_id = 0x01, - sli_bt_cs_create_config_response_id = 0x02, - sli_bt_cs_remove_config_response_id = 0x03, - sli_bt_cs_set_channel_classification_response_id = 0x04, - sli_bt_cs_set_procedure_parameters_response_id = 0x05, - sli_bt_cs_procedure_enable_response_id = 0x06, - sli_bt_cs_set_antenna_configuration_response_id = 0x07, - sli_bt_cs_read_local_supported_capabilities_response_id = 0x08, - sli_bt_cs_test_start_response_id = 0x00, - sli_bt_l2cap_open_le_channel_response_id = 0x01, - sli_bt_l2cap_send_le_channel_open_response_response_id = 0x02, - sli_bt_l2cap_channel_send_data_response_id = 0x03, - sli_bt_l2cap_channel_send_credit_response_id = 0x04, - sli_bt_l2cap_close_channel_response_id = 0x05, - sli_bt_cte_transmitter_set_dtm_parameters_response_id = 0x04, - sli_bt_cte_transmitter_clear_dtm_parameters_response_id = 0x05, - sli_bt_cte_transmitter_enable_connection_cte_response_id = 0x00, - sli_bt_cte_transmitter_disable_connection_cte_response_id = 0x01, - sli_bt_cte_transmitter_enable_connectionless_cte_response_id = 0x02, - sli_bt_cte_transmitter_disable_connectionless_cte_response_id = 0x03, - sli_bt_cte_transmitter_enable_silabs_cte_response_id = 0x06, - sli_bt_cte_transmitter_disable_silabs_cte_response_id = 0x07, - sli_bt_cte_receiver_set_dtm_parameters_response_id = 0x05, - sli_bt_cte_receiver_clear_dtm_parameters_response_id = 0x06, - sli_bt_cte_receiver_set_sync_cte_type_response_id = 0x09, - sli_bt_cte_receiver_set_default_sync_receive_parameters_response_id = 0x0a, - sli_bt_cte_receiver_set_sync_receive_parameters_response_id = 0x0b, - sli_bt_cte_receiver_configure_response_id = 0x00, - sli_bt_cte_receiver_enable_connection_cte_response_id = 0x01, - sli_bt_cte_receiver_disable_connection_cte_response_id = 0x02, - sli_bt_cte_receiver_enable_connectionless_cte_response_id = 0x03, - sli_bt_cte_receiver_disable_connectionless_cte_response_id = 0x04, - sli_bt_cte_receiver_enable_silabs_cte_response_id = 0x07, - sli_bt_cte_receiver_disable_silabs_cte_response_id = 0x08, - sli_bt_connection_analyzer_start_response_id = 0x00, - sli_bt_connection_analyzer_stop_response_id = 0x01, - sli_bt_user_message_to_target_response_id = 0x00, - sli_bt_user_manage_event_filter_response_id = 0x01, - sli_bt_user_reset_to_dfu_response_id = 0x02, -}; - -enum sli_bt_event_id -{ - sli_bt_dfu_boot_event_id = 0x00, - sli_bt_dfu_boot_failure_event_id = 0x01, - sli_bt_system_boot_event_id = 0x00, - sli_bt_system_stopped_event_id = 0x01, - sli_bt_system_error_event_id = 0x06, - sli_bt_system_hardware_error_event_id = 0x05, - sli_bt_system_resource_exhausted_event_id = 0x08, - sli_bt_system_external_signal_event_id = 0x03, - sli_bt_system_awake_event_id = 0x04, - sli_bt_system_soft_timer_event_id = 0x07, - sli_bt_resource_status_event_id = 0x00, - sli_bt_advertiser_timeout_event_id = 0x01, - sli_bt_advertiser_scan_request_event_id = 0x02, - sli_bt_periodic_advertiser_status_event_id = 0x00, - sli_bt_scanner_legacy_advertisement_report_event_id = 0x00, - sli_bt_scanner_extended_advertisement_report_event_id = 0x02, - sli_bt_scanner_scan_report_event_id = 0x01, - sli_bt_sync_opened_event_id = 0x00, - sli_bt_sync_transfer_received_event_id = 0x03, - sli_bt_sync_data_event_id = 0x02, - sli_bt_sync_closed_event_id = 0x01, - sli_bt_periodic_sync_opened_event_id = 0x00, - sli_bt_periodic_sync_transfer_received_event_id = 0x01, - sli_bt_periodic_sync_report_event_id = 0x02, - sli_bt_pawr_sync_opened_event_id = 0x00, - sli_bt_pawr_sync_transfer_received_event_id = 0x01, - sli_bt_pawr_sync_subevent_report_event_id = 0x02, - sli_bt_pawr_advertiser_subevent_data_request_event_id = 0x00, - sli_bt_pawr_advertiser_subevent_tx_failed_event_id = 0x02, - sli_bt_pawr_advertiser_response_report_event_id = 0x01, - sli_bt_connection_opened_event_id = 0x00, - sli_bt_connection_parameters_event_id = 0x02, - sli_bt_connection_set_parameters_failed_event_id = 0x10, - sli_bt_connection_phy_status_event_id = 0x04, - sli_bt_connection_get_remote_tx_power_completed_event_id = 0x05, - sli_bt_connection_tx_power_event_id = 0x06, - sli_bt_connection_remote_tx_power_event_id = 0x07, - sli_bt_connection_remote_used_features_event_id = 0x08, - sli_bt_connection_data_length_event_id = 0x09, - sli_bt_connection_statistics_event_id = 0x0a, - sli_bt_connection_closed_event_id = 0x01, - sli_bt_connection_rssi_event_id = 0x03, - sli_bt_gatt_mtu_exchanged_event_id = 0x00, - sli_bt_gatt_service_event_id = 0x01, - sli_bt_gatt_characteristic_event_id = 0x02, - sli_bt_gatt_descriptor_event_id = 0x03, - sli_bt_gatt_characteristic_value_event_id = 0x04, - sli_bt_gatt_descriptor_value_event_id = 0x05, - sli_bt_gatt_procedure_completed_event_id = 0x06, - sli_bt_gatt_server_attribute_value_event_id = 0x00, - sli_bt_gatt_server_user_read_request_event_id = 0x01, - sli_bt_gatt_server_user_write_request_event_id = 0x02, - sli_bt_gatt_server_characteristic_status_event_id = 0x03, - sli_bt_gatt_server_execute_write_completed_event_id = 0x04, - sli_bt_gatt_server_indication_timeout_event_id = 0x05, - sli_bt_gatt_server_notification_tx_completed_event_id = 0x06, - sli_bt_test_dtm_completed_event_id = 0x00, - sli_bt_sm_passkey_display_event_id = 0x00, - sli_bt_sm_passkey_request_event_id = 0x01, - sli_bt_sm_confirm_passkey_event_id = 0x02, - sli_bt_sm_bonded_event_id = 0x03, - sli_bt_sm_bonding_failed_event_id = 0x04, - sli_bt_sm_confirm_bonding_event_id = 0x09, - sli_bt_external_bondingdb_data_request_event_id = 0x00, - sli_bt_external_bondingdb_data_event_id = 0x01, - sli_bt_external_bondingdb_data_ready_event_id = 0x02, - sli_bt_cs_security_enable_complete_event_id = 0x00, - sli_bt_cs_config_complete_event_id = 0x01, - sli_bt_cs_procedure_enable_complete_event_id = 0x02, - sli_bt_cs_result_event_id = 0x03, - sli_bt_l2cap_le_channel_open_request_event_id = 0x01, - sli_bt_l2cap_le_channel_open_response_event_id = 0x02, - sli_bt_l2cap_channel_data_event_id = 0x03, - sli_bt_l2cap_channel_credit_event_id = 0x04, - sli_bt_l2cap_channel_closed_event_id = 0x05, - sli_bt_l2cap_command_rejected_event_id = 0x06, - sli_bt_cte_receiver_dtm_iq_report_event_id = 0x02, - sli_bt_cte_receiver_connection_iq_report_event_id = 0x00, - sli_bt_cte_receiver_connectionless_iq_report_event_id = 0x01, - sli_bt_cte_receiver_silabs_iq_report_event_id = 0x03, - sli_bt_connection_analyzer_report_event_id = 0x00, - sli_bt_connection_analyzer_completed_event_id = 0x01, - sli_bt_user_message_to_host_event_id = 0x00, -}; - -PACKSTRUCT( struct sl_bt_rsp_error_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_error_s sl_bt_rsp_error_t; - -PACKSTRUCT( struct sl_bt_cmd_dfu_flash_set_address_s -{ - uint32_t address; -}); - -typedef struct sl_bt_cmd_dfu_flash_set_address_s sl_bt_cmd_dfu_flash_set_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_dfu_flash_upload_s -{ - uint8array data; -}); - -typedef struct sl_bt_cmd_dfu_flash_upload_s sl_bt_cmd_dfu_flash_upload_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_reset_s -{ - uint8_t dfu; -}); - -typedef struct sl_bt_cmd_system_reset_s sl_bt_cmd_system_reset_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_halt_s -{ - uint8_t halt; -}); - -typedef struct sl_bt_cmd_system_halt_s sl_bt_cmd_system_halt_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_linklayer_configure_s -{ - uint8_t key; - uint8array data; -}); - -typedef struct sl_bt_cmd_system_linklayer_configure_s sl_bt_cmd_system_linklayer_configure_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_set_tx_power_s -{ - int16_t min_power; - int16_t max_power; -}); - -typedef struct sl_bt_cmd_system_set_tx_power_s sl_bt_cmd_system_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_set_identity_address_s -{ - bd_addr address; - uint8_t type; -}); - -typedef struct sl_bt_cmd_system_set_identity_address_s sl_bt_cmd_system_set_identity_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_get_random_data_s -{ - uint8_t length; -}); - -typedef struct sl_bt_cmd_system_get_random_data_s sl_bt_cmd_system_get_random_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_data_buffer_write_s -{ - uint8array data; -}); - -typedef struct sl_bt_cmd_system_data_buffer_write_s sl_bt_cmd_system_data_buffer_write_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_get_counters_s -{ - uint8_t reset; -}); - -typedef struct sl_bt_cmd_system_get_counters_s sl_bt_cmd_system_get_counters_t; - - -PACKSTRUCT( struct sl_bt_cmd_system_set_lazy_soft_timer_s -{ - uint32_t time; - uint32_t slack; - uint8_t handle; - uint8_t single_shot; -}); - -typedef struct sl_bt_cmd_system_set_lazy_soft_timer_s sl_bt_cmd_system_set_lazy_soft_timer_t; - - -PACKSTRUCT( struct sl_bt_cmd_resource_set_report_threshold_s -{ - uint32_t low; - uint32_t high; -}); - -typedef struct sl_bt_cmd_resource_set_report_threshold_s sl_bt_cmd_resource_set_report_threshold_t; - - -PACKSTRUCT( struct sl_bt_cmd_resource_enable_connection_tx_report_s -{ - uint16_t packet_count; -}); - -typedef struct sl_bt_cmd_resource_enable_connection_tx_report_s sl_bt_cmd_resource_enable_connection_tx_report_t; - - -PACKSTRUCT( struct sl_bt_cmd_resource_get_connection_tx_status_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_resource_get_connection_tx_status_s sl_bt_cmd_resource_get_connection_tx_status_t; - - -PACKSTRUCT( struct sl_bt_cmd_gap_set_privacy_mode_s -{ - uint8_t privacy; - uint8_t interval; -}); - -typedef struct sl_bt_cmd_gap_set_privacy_mode_s sl_bt_cmd_gap_set_privacy_mode_t; - - -PACKSTRUCT( struct sl_bt_cmd_gap_set_data_channel_classification_s -{ - uint8array channel_map; -}); - -typedef struct sl_bt_cmd_gap_set_data_channel_classification_s sl_bt_cmd_gap_set_data_channel_classification_t; - - -PACKSTRUCT( struct sl_bt_cmd_gap_enable_whitelisting_s -{ - uint8_t enable; -}); - -typedef struct sl_bt_cmd_gap_enable_whitelisting_s sl_bt_cmd_gap_enable_whitelisting_t; - - -PACKSTRUCT( struct sl_bt_cmd_gap_set_identity_address_s -{ - bd_addr address; - uint8_t addr_type; -}); - -typedef struct sl_bt_cmd_gap_set_identity_address_s sl_bt_cmd_gap_set_identity_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_configure_s -{ - uint8_t advertising_set; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_advertiser_configure_s sl_bt_cmd_advertiser_configure_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_timing_s -{ - uint8_t advertising_set; - uint32_t interval_min; - uint32_t interval_max; - uint16_t duration; - uint8_t maxevents; -}); - -typedef struct sl_bt_cmd_advertiser_set_timing_s sl_bt_cmd_advertiser_set_timing_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_channel_map_s -{ - uint8_t advertising_set; - uint8_t channel_map; -}); - -typedef struct sl_bt_cmd_advertiser_set_channel_map_s sl_bt_cmd_advertiser_set_channel_map_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_tx_power_s -{ - uint8_t advertising_set; - int16_t power; -}); - -typedef struct sl_bt_cmd_advertiser_set_tx_power_s sl_bt_cmd_advertiser_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_report_scan_request_s -{ - uint8_t advertising_set; - uint8_t report_scan_req; -}); - -typedef struct sl_bt_cmd_advertiser_set_report_scan_request_s sl_bt_cmd_advertiser_set_report_scan_request_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_random_address_s -{ - uint8_t advertising_set; - uint8_t addr_type; - bd_addr address; -}); - -typedef struct sl_bt_cmd_advertiser_set_random_address_s sl_bt_cmd_advertiser_set_random_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_clear_random_address_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_advertiser_clear_random_address_s sl_bt_cmd_advertiser_clear_random_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_stop_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_advertiser_stop_s sl_bt_cmd_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_delete_set_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_advertiser_delete_set_s sl_bt_cmd_advertiser_delete_set_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_phy_s -{ - uint8_t advertising_set; - uint8_t primary_phy; - uint8_t secondary_phy; -}); - -typedef struct sl_bt_cmd_advertiser_set_phy_s sl_bt_cmd_advertiser_set_phy_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_configuration_s -{ - uint8_t advertising_set; - uint32_t configurations; -}); - -typedef struct sl_bt_cmd_advertiser_set_configuration_s sl_bt_cmd_advertiser_set_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_clear_configuration_s -{ - uint8_t advertising_set; - uint32_t configurations; -}); - -typedef struct sl_bt_cmd_advertiser_clear_configuration_s sl_bt_cmd_advertiser_clear_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_data_s -{ - uint8_t advertising_set; - uint8_t packet_type; - uint8array adv_data; -}); - -typedef struct sl_bt_cmd_advertiser_set_data_s sl_bt_cmd_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_set_long_data_s -{ - uint8_t advertising_set; - uint8_t packet_type; -}); - -typedef struct sl_bt_cmd_advertiser_set_long_data_s sl_bt_cmd_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_start_s -{ - uint8_t advertising_set; - uint8_t discover; - uint8_t connect; -}); - -typedef struct sl_bt_cmd_advertiser_start_s sl_bt_cmd_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_start_periodic_advertising_s -{ - uint8_t advertising_set; - uint16_t interval_min; - uint16_t interval_max; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_advertiser_start_periodic_advertising_s sl_bt_cmd_advertiser_start_periodic_advertising_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_stop_periodic_advertising_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_advertiser_stop_periodic_advertising_s sl_bt_cmd_advertiser_stop_periodic_advertising_t; - - -PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_set_data_s -{ - uint8_t advertising_set; - uint8_t type; - uint8array data; -}); - -typedef struct sl_bt_cmd_legacy_advertiser_set_data_s sl_bt_cmd_legacy_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_generate_data_s -{ - uint8_t advertising_set; - uint8_t discover; -}); - -typedef struct sl_bt_cmd_legacy_advertiser_generate_data_s sl_bt_cmd_legacy_advertiser_generate_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_start_s -{ - uint8_t advertising_set; - uint8_t connect; -}); - -typedef struct sl_bt_cmd_legacy_advertiser_start_s sl_bt_cmd_legacy_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_start_directed_s -{ - uint8_t advertising_set; - uint8_t connect; - bd_addr peer_addr; - uint8_t peer_addr_type; -}); - -typedef struct sl_bt_cmd_legacy_advertiser_start_directed_s sl_bt_cmd_legacy_advertiser_start_directed_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_phy_s -{ - uint8_t advertising_set; - uint8_t primary_phy; - uint8_t secondary_phy; -}); - -typedef struct sl_bt_cmd_extended_advertiser_set_phy_s sl_bt_cmd_extended_advertiser_set_phy_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_data_s -{ - uint8_t advertising_set; - uint8array data; -}); - -typedef struct sl_bt_cmd_extended_advertiser_set_data_s sl_bt_cmd_extended_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_long_data_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_extended_advertiser_set_long_data_s sl_bt_cmd_extended_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_generate_data_s -{ - uint8_t advertising_set; - uint8_t discover; -}); - -typedef struct sl_bt_cmd_extended_advertiser_generate_data_s sl_bt_cmd_extended_advertiser_generate_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_start_s -{ - uint8_t advertising_set; - uint8_t connect; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_extended_advertiser_start_s sl_bt_cmd_extended_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_start_directed_s -{ - uint8_t advertising_set; - uint8_t connect; - uint32_t flags; - bd_addr peer_addr; - uint8_t peer_addr_type; -}); - -typedef struct sl_bt_cmd_extended_advertiser_start_directed_s sl_bt_cmd_extended_advertiser_start_directed_t; - - -PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_set_data_s -{ - uint8_t advertising_set; - uint8array data; -}); - -typedef struct sl_bt_cmd_periodic_advertiser_set_data_s sl_bt_cmd_periodic_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_set_long_data_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_periodic_advertiser_set_long_data_s sl_bt_cmd_periodic_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_start_s -{ - uint8_t advertising_set; - uint16_t interval_min; - uint16_t interval_max; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_periodic_advertiser_start_s sl_bt_cmd_periodic_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_stop_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_periodic_advertiser_stop_s sl_bt_cmd_periodic_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_cmd_scanner_set_parameters_s -{ - uint8_t mode; - uint16_t interval; - uint16_t window; -}); - -typedef struct sl_bt_cmd_scanner_set_parameters_s sl_bt_cmd_scanner_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_scanner_set_parameters_and_filter_s -{ - uint8_t mode; - uint16_t interval; - uint16_t window; - uint32_t flags; - uint8_t filter_policy; -}); - -typedef struct sl_bt_cmd_scanner_set_parameters_and_filter_s sl_bt_cmd_scanner_set_parameters_and_filter_t; - - -PACKSTRUCT( struct sl_bt_cmd_scanner_set_timing_s -{ - uint8_t phys; - uint16_t scan_interval; - uint16_t scan_window; -}); - -typedef struct sl_bt_cmd_scanner_set_timing_s sl_bt_cmd_scanner_set_timing_t; - - -PACKSTRUCT( struct sl_bt_cmd_scanner_set_mode_s -{ - uint8_t phys; - uint8_t scan_mode; -}); - -typedef struct sl_bt_cmd_scanner_set_mode_s sl_bt_cmd_scanner_set_mode_t; - - -PACKSTRUCT( struct sl_bt_cmd_scanner_start_s -{ - uint8_t scanning_phy; - uint8_t discover_mode; -}); - -typedef struct sl_bt_cmd_scanner_start_s sl_bt_cmd_scanner_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_set_parameters_s -{ - uint16_t skip; - uint16_t timeout; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_sync_set_parameters_s sl_bt_cmd_sync_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_open_s -{ - bd_addr address; - uint8_t address_type; - uint8_t adv_sid; -}); - -typedef struct sl_bt_cmd_sync_open_s sl_bt_cmd_sync_open_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_set_reporting_mode_s -{ - uint16_t sync; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_sync_set_reporting_mode_s sl_bt_cmd_sync_set_reporting_mode_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_update_sync_parameters_s -{ - uint16_t sync; - uint16_t skip; - uint16_t timeout; -}); - -typedef struct sl_bt_cmd_sync_update_sync_parameters_s sl_bt_cmd_sync_update_sync_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_close_s -{ - uint16_t sync; -}); - -typedef struct sl_bt_cmd_sync_close_s sl_bt_cmd_sync_close_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_scanner_set_sync_parameters_s -{ - uint16_t skip; - uint16_t timeout; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_sync_scanner_set_sync_parameters_s sl_bt_cmd_sync_scanner_set_sync_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_scanner_open_s -{ - bd_addr address; - uint8_t address_type; - uint8_t adv_sid; -}); - -typedef struct sl_bt_cmd_sync_scanner_open_s sl_bt_cmd_sync_scanner_open_t; - - -PACKSTRUCT( struct sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_s -{ - uint8_t mode; - uint16_t skip; - uint16_t timeout; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_s sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_past_receiver_set_sync_receive_parameters_s -{ - uint8_t connection; - uint8_t mode; - uint16_t skip; - uint16_t timeout; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_past_receiver_set_sync_receive_parameters_s sl_bt_cmd_past_receiver_set_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_advertiser_past_transfer_s -{ - uint8_t connection; - uint16_t service_data; - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_advertiser_past_transfer_s sl_bt_cmd_advertiser_past_transfer_t; - - -PACKSTRUCT( struct sl_bt_cmd_sync_past_transfer_s -{ - uint8_t connection; - uint16_t service_data; - uint16_t sync; -}); - -typedef struct sl_bt_cmd_sync_past_transfer_s sl_bt_cmd_sync_past_transfer_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_sync_set_sync_subevents_s -{ - uint16_t sync; - uint8array subevents; -}); - -typedef struct sl_bt_cmd_pawr_sync_set_sync_subevents_s sl_bt_cmd_pawr_sync_set_sync_subevents_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_sync_set_response_data_s -{ - uint16_t sync; - uint16_t request_event; - uint8_t request_subevent; - uint8_t response_subevent; - uint8_t response_slot; - uint8array response_data; -}); - -typedef struct sl_bt_cmd_pawr_sync_set_response_data_s sl_bt_cmd_pawr_sync_set_response_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_start_s -{ - uint8_t advertising_set; - uint16_t interval_min; - uint16_t interval_max; - uint32_t flags; - uint8_t num_subevents; - uint8_t subevent_interval; - uint8_t response_slot_delay; - uint8_t response_slot_spacing; - uint8_t response_slots; -}); - -typedef struct sl_bt_cmd_pawr_advertiser_start_s sl_bt_cmd_pawr_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_set_subevent_data_s -{ - uint8_t advertising_set; - uint8_t subevent; - uint8_t response_slot_start; - uint8_t response_slot_count; - uint8array adv_data; -}); - -typedef struct sl_bt_cmd_pawr_advertiser_set_subevent_data_s sl_bt_cmd_pawr_advertiser_set_subevent_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_create_connection_s -{ - uint8_t advertising_set; - uint8_t subevent; - bd_addr address; - uint8_t address_type; -}); - -typedef struct sl_bt_cmd_pawr_advertiser_create_connection_s sl_bt_cmd_pawr_advertiser_create_connection_t; - - -PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_stop_s -{ - uint8_t advertising_set; -}); - -typedef struct sl_bt_cmd_pawr_advertiser_stop_s sl_bt_cmd_pawr_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_default_parameters_s -{ - uint16_t min_interval; - uint16_t max_interval; - uint16_t latency; - uint16_t timeout; - uint16_t min_ce_length; - uint16_t max_ce_length; -}); - -typedef struct sl_bt_cmd_connection_set_default_parameters_s sl_bt_cmd_connection_set_default_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_default_preferred_phy_s -{ - uint8_t preferred_phy; - uint8_t accepted_phy; -}); - -typedef struct sl_bt_cmd_connection_set_default_preferred_phy_s sl_bt_cmd_connection_set_default_preferred_phy_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_default_data_length_s -{ - uint16_t tx_data_len; -}); - -typedef struct sl_bt_cmd_connection_set_default_data_length_s sl_bt_cmd_connection_set_default_data_length_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_open_s -{ - bd_addr address; - uint8_t address_type; - uint8_t initiating_phy; -}); - -typedef struct sl_bt_cmd_connection_open_s sl_bt_cmd_connection_open_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_parameters_s -{ - uint8_t connection; - uint16_t min_interval; - uint16_t max_interval; - uint16_t latency; - uint16_t timeout; - uint16_t min_ce_length; - uint16_t max_ce_length; -}); - -typedef struct sl_bt_cmd_connection_set_parameters_s sl_bt_cmd_connection_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_preferred_phy_s -{ - uint8_t connection; - uint8_t preferred_phy; - uint8_t accepted_phy; -}); - -typedef struct sl_bt_cmd_connection_set_preferred_phy_s sl_bt_cmd_connection_set_preferred_phy_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_disable_slave_latency_s -{ - uint8_t connection; - uint8_t disable; -}); - -typedef struct sl_bt_cmd_connection_disable_slave_latency_s sl_bt_cmd_connection_disable_slave_latency_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_median_rssi_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_get_median_rssi_s sl_bt_cmd_connection_get_median_rssi_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_read_channel_map_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_read_channel_map_s sl_bt_cmd_connection_read_channel_map_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_power_reporting_s -{ - uint8_t connection; - uint8_t mode; -}); - -typedef struct sl_bt_cmd_connection_set_power_reporting_s sl_bt_cmd_connection_set_power_reporting_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_remote_power_reporting_s -{ - uint8_t connection; - uint8_t mode; -}); - -typedef struct sl_bt_cmd_connection_set_remote_power_reporting_s sl_bt_cmd_connection_set_remote_power_reporting_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_tx_power_s -{ - uint8_t connection; - uint8_t phy; -}); - -typedef struct sl_bt_cmd_connection_get_tx_power_s sl_bt_cmd_connection_get_tx_power_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_remote_tx_power_s -{ - uint8_t connection; - uint8_t phy; -}); - -typedef struct sl_bt_cmd_connection_get_remote_tx_power_s sl_bt_cmd_connection_get_remote_tx_power_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_tx_power_s -{ - uint8_t connection; - int16_t tx_power; -}); - -typedef struct sl_bt_cmd_connection_set_tx_power_s sl_bt_cmd_connection_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_read_remote_used_features_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_read_remote_used_features_s sl_bt_cmd_connection_read_remote_used_features_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_security_status_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_get_security_status_s sl_bt_cmd_connection_get_security_status_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_set_data_length_s -{ - uint8_t connection; - uint16_t tx_data_len; - uint16_t tx_time_us; -}); - -typedef struct sl_bt_cmd_connection_set_data_length_s sl_bt_cmd_connection_set_data_length_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_read_statistics_s -{ - uint8_t connection; - uint8_t reset; -}); - -typedef struct sl_bt_cmd_connection_read_statistics_s sl_bt_cmd_connection_read_statistics_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_scheduling_details_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_get_scheduling_details_s sl_bt_cmd_connection_get_scheduling_details_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_close_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_close_s sl_bt_cmd_connection_close_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_forcefully_close_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_forcefully_close_s sl_bt_cmd_connection_forcefully_close_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_get_rssi_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_connection_get_rssi_s sl_bt_cmd_connection_get_rssi_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_set_max_mtu_s -{ - uint16_t max_mtu; -}); - -typedef struct sl_bt_cmd_gatt_set_max_mtu_s sl_bt_cmd_gatt_set_max_mtu_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_primary_services_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_gatt_discover_primary_services_s sl_bt_cmd_gatt_discover_primary_services_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_primary_services_by_uuid_s -{ - uint8_t connection; - uint8array uuid; -}); - -typedef struct sl_bt_cmd_gatt_discover_primary_services_by_uuid_s sl_bt_cmd_gatt_discover_primary_services_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_find_included_services_s -{ - uint8_t connection; - uint32_t service; -}); - -typedef struct sl_bt_cmd_gatt_find_included_services_s sl_bt_cmd_gatt_find_included_services_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristics_s -{ - uint8_t connection; - uint32_t service; -}); - -typedef struct sl_bt_cmd_gatt_discover_characteristics_s sl_bt_cmd_gatt_discover_characteristics_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristics_by_uuid_s -{ - uint8_t connection; - uint32_t service; - uint8array uuid; -}); - -typedef struct sl_bt_cmd_gatt_discover_characteristics_by_uuid_s sl_bt_cmd_gatt_discover_characteristics_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_descriptors_s -{ - uint8_t connection; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gatt_discover_descriptors_s sl_bt_cmd_gatt_discover_descriptors_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristic_descriptors_s -{ - uint8_t connection; - uint16_t start; - uint16_t end; -}); - -typedef struct sl_bt_cmd_gatt_discover_characteristic_descriptors_s sl_bt_cmd_gatt_discover_characteristic_descriptors_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_set_characteristic_notification_s -{ - uint8_t connection; - uint16_t characteristic; - uint8_t flags; -}); - -typedef struct sl_bt_cmd_gatt_set_characteristic_notification_s sl_bt_cmd_gatt_set_characteristic_notification_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_send_characteristic_confirmation_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_gatt_send_characteristic_confirmation_s sl_bt_cmd_gatt_send_characteristic_confirmation_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_s -{ - uint8_t connection; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gatt_read_characteristic_value_s sl_bt_cmd_gatt_read_characteristic_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_from_offset_s -{ - uint8_t connection; - uint16_t characteristic; - uint16_t offset; - uint16_t maxlen; -}); - -typedef struct sl_bt_cmd_gatt_read_characteristic_value_from_offset_s sl_bt_cmd_gatt_read_characteristic_value_from_offset_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_read_multiple_characteristic_values_s -{ - uint8_t connection; - uint8array characteristic_list; -}); - -typedef struct sl_bt_cmd_gatt_read_multiple_characteristic_values_s sl_bt_cmd_gatt_read_multiple_characteristic_values_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_by_uuid_s -{ - uint8_t connection; - uint32_t service; - uint8array uuid; -}); - -typedef struct sl_bt_cmd_gatt_read_characteristic_value_by_uuid_s sl_bt_cmd_gatt_read_characteristic_value_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_write_characteristic_value_s -{ - uint8_t connection; - uint16_t characteristic; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_write_characteristic_value_s sl_bt_cmd_gatt_write_characteristic_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_write_characteristic_value_without_response_s -{ - uint8_t connection; - uint16_t characteristic; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_write_characteristic_value_without_response_s sl_bt_cmd_gatt_write_characteristic_value_without_response_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_prepare_characteristic_value_write_s -{ - uint8_t connection; - uint16_t characteristic; - uint16_t offset; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_prepare_characteristic_value_write_s sl_bt_cmd_gatt_prepare_characteristic_value_write_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_s -{ - uint8_t connection; - uint16_t characteristic; - uint16_t offset; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_s sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_execute_characteristic_value_write_s -{ - uint8_t connection; - uint8_t flags; -}); - -typedef struct sl_bt_cmd_gatt_execute_characteristic_value_write_s sl_bt_cmd_gatt_execute_characteristic_value_write_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_read_descriptor_value_s -{ - uint8_t connection; - uint16_t descriptor; -}); - -typedef struct sl_bt_cmd_gatt_read_descriptor_value_s sl_bt_cmd_gatt_read_descriptor_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_write_descriptor_value_s -{ - uint8_t connection; - uint16_t descriptor; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_write_descriptor_value_s sl_bt_cmd_gatt_write_descriptor_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_service_s -{ - uint16_t session; - uint8_t type; - uint8_t property; - uint8array uuid; -}); - -typedef struct sl_bt_cmd_gattdb_add_service_s sl_bt_cmd_gattdb_add_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_service_s -{ - uint16_t session; - uint16_t service; -}); - -typedef struct sl_bt_cmd_gattdb_remove_service_s sl_bt_cmd_gattdb_remove_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_included_service_s -{ - uint16_t session; - uint16_t service; - uint16_t included_service; -}); - -typedef struct sl_bt_cmd_gattdb_add_included_service_s sl_bt_cmd_gattdb_add_included_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_included_service_s -{ - uint16_t session; - uint16_t attribute; -}); - -typedef struct sl_bt_cmd_gattdb_remove_included_service_s sl_bt_cmd_gattdb_remove_included_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid16_characteristic_s -{ - uint16_t session; - uint16_t service; - uint16_t property; - uint16_t security; - uint8_t flag; - sl_bt_uuid_16_t uuid; - uint8_t value_type; - uint16_t maxlen; - byte_array value; -}); - -typedef struct sl_bt_cmd_gattdb_add_uuid16_characteristic_s sl_bt_cmd_gattdb_add_uuid16_characteristic_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid128_characteristic_s -{ - uint16_t session; - uint16_t service; - uint16_t property; - uint16_t security; - uint8_t flag; - uuid_128 uuid; - uint8_t value_type; - uint16_t maxlen; - byte_array value; -}); - -typedef struct sl_bt_cmd_gattdb_add_uuid128_characteristic_s sl_bt_cmd_gattdb_add_uuid128_characteristic_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_characteristic_s -{ - uint16_t session; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gattdb_remove_characteristic_s sl_bt_cmd_gattdb_remove_characteristic_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid16_descriptor_s -{ - uint16_t session; - uint16_t characteristic; - uint16_t property; - uint16_t security; - sl_bt_uuid_16_t uuid; - uint8_t value_type; - uint16_t maxlen; - byte_array value; -}); - -typedef struct sl_bt_cmd_gattdb_add_uuid16_descriptor_s sl_bt_cmd_gattdb_add_uuid16_descriptor_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid128_descriptor_s -{ - uint16_t session; - uint16_t characteristic; - uint16_t property; - uint16_t security; - uuid_128 uuid; - uint8_t value_type; - uint16_t maxlen; - byte_array value; -}); - -typedef struct sl_bt_cmd_gattdb_add_uuid128_descriptor_s sl_bt_cmd_gattdb_add_uuid128_descriptor_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_descriptor_s -{ - uint16_t session; - uint16_t descriptor; -}); - -typedef struct sl_bt_cmd_gattdb_remove_descriptor_s sl_bt_cmd_gattdb_remove_descriptor_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_start_service_s -{ - uint16_t session; - uint16_t service; -}); - -typedef struct sl_bt_cmd_gattdb_start_service_s sl_bt_cmd_gattdb_start_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_stop_service_s -{ - uint16_t session; - uint16_t service; -}); - -typedef struct sl_bt_cmd_gattdb_stop_service_s sl_bt_cmd_gattdb_stop_service_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_start_characteristic_s -{ - uint16_t session; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gattdb_start_characteristic_s sl_bt_cmd_gattdb_start_characteristic_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_stop_characteristic_s -{ - uint16_t session; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gattdb_stop_characteristic_s sl_bt_cmd_gattdb_stop_characteristic_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_commit_s -{ - uint16_t session; -}); - -typedef struct sl_bt_cmd_gattdb_commit_s sl_bt_cmd_gattdb_commit_t; - - -PACKSTRUCT( struct sl_bt_cmd_gattdb_abort_s -{ - uint16_t session; -}); - -typedef struct sl_bt_cmd_gattdb_abort_s sl_bt_cmd_gattdb_abort_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_set_max_mtu_s -{ - uint16_t max_mtu; -}); - -typedef struct sl_bt_cmd_gatt_server_set_max_mtu_s sl_bt_cmd_gatt_server_set_max_mtu_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_get_mtu_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_gatt_server_get_mtu_s sl_bt_cmd_gatt_server_get_mtu_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_find_attribute_s -{ - uint16_t start; - uint8array type; -}); - -typedef struct sl_bt_cmd_gatt_server_find_attribute_s sl_bt_cmd_gatt_server_find_attribute_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_attribute_value_s -{ - uint16_t attribute; - uint16_t offset; -}); - -typedef struct sl_bt_cmd_gatt_server_read_attribute_value_s sl_bt_cmd_gatt_server_read_attribute_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_attribute_type_s -{ - uint16_t attribute; -}); - -typedef struct sl_bt_cmd_gatt_server_read_attribute_type_s sl_bt_cmd_gatt_server_read_attribute_type_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_write_attribute_value_s -{ - uint16_t attribute; - uint16_t offset; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_write_attribute_value_s sl_bt_cmd_gatt_server_write_attribute_value_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_read_response_s -{ - uint8_t connection; - uint16_t characteristic; - uint8_t att_errorcode; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_send_user_read_response_s sl_bt_cmd_gatt_server_send_user_read_response_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_write_response_s -{ - uint8_t connection; - uint16_t characteristic; - uint8_t att_errorcode; -}); - -typedef struct sl_bt_cmd_gatt_server_send_user_write_response_s sl_bt_cmd_gatt_server_send_user_write_response_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_notification_s -{ - uint8_t connection; - uint16_t characteristic; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_send_notification_s sl_bt_cmd_gatt_server_send_notification_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_indication_s -{ - uint8_t connection; - uint16_t characteristic; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_send_indication_s sl_bt_cmd_gatt_server_send_indication_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_notify_all_s -{ - uint16_t characteristic; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_notify_all_s sl_bt_cmd_gatt_server_notify_all_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_client_configuration_s -{ - uint8_t connection; - uint16_t characteristic; -}); - -typedef struct sl_bt_cmd_gatt_server_read_client_configuration_s sl_bt_cmd_gatt_server_read_client_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_prepare_write_response_s -{ - uint8_t connection; - uint16_t characteristic; - uint8_t att_errorcode; - uint16_t offset; - uint8array value; -}); - -typedef struct sl_bt_cmd_gatt_server_send_user_prepare_write_response_s sl_bt_cmd_gatt_server_send_user_prepare_write_response_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_set_capabilities_s -{ - uint32_t caps; - uint32_t reserved; -}); - -typedef struct sl_bt_cmd_gatt_server_set_capabilities_s sl_bt_cmd_gatt_server_set_capabilities_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_enable_capabilities_s -{ - uint32_t caps; -}); - -typedef struct sl_bt_cmd_gatt_server_enable_capabilities_s sl_bt_cmd_gatt_server_enable_capabilities_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_disable_capabilities_s -{ - uint32_t caps; -}); - -typedef struct sl_bt_cmd_gatt_server_disable_capabilities_s sl_bt_cmd_gatt_server_disable_capabilities_t; - - -PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_client_supported_features_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_gatt_server_read_client_supported_features_s sl_bt_cmd_gatt_server_read_client_supported_features_t; - - -PACKSTRUCT( struct sl_bt_cmd_nvm_save_s -{ - uint16_t key; - uint8array value; -}); - -typedef struct sl_bt_cmd_nvm_save_s sl_bt_cmd_nvm_save_t; - - -PACKSTRUCT( struct sl_bt_cmd_nvm_load_s -{ - uint16_t key; -}); - -typedef struct sl_bt_cmd_nvm_load_s sl_bt_cmd_nvm_load_t; - - -PACKSTRUCT( struct sl_bt_cmd_nvm_erase_s -{ - uint16_t key; -}); - -typedef struct sl_bt_cmd_nvm_erase_s sl_bt_cmd_nvm_erase_t; - - -PACKSTRUCT( struct sl_bt_cmd_test_dtm_tx_v4_s -{ - uint8_t packet_type; - uint8_t length; - uint8_t channel; - uint8_t phy; - int8_t power_level; -}); - -typedef struct sl_bt_cmd_test_dtm_tx_v4_s sl_bt_cmd_test_dtm_tx_v4_t; - - -PACKSTRUCT( struct sl_bt_cmd_test_dtm_tx_cw_s -{ - uint8_t packet_type; - uint8_t channel; - uint8_t phy; - int16_t power_level; -}); - -typedef struct sl_bt_cmd_test_dtm_tx_cw_s sl_bt_cmd_test_dtm_tx_cw_t; - - -PACKSTRUCT( struct sl_bt_cmd_test_dtm_rx_s -{ - uint8_t channel; - uint8_t phy; -}); - -typedef struct sl_bt_cmd_test_dtm_rx_s sl_bt_cmd_test_dtm_rx_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_configure_s -{ - uint8_t flags; - uint8_t io_capabilities; -}); - -typedef struct sl_bt_cmd_sm_configure_s sl_bt_cmd_sm_configure_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_minimum_key_size_s -{ - uint8_t minimum_key_size; -}); - -typedef struct sl_bt_cmd_sm_set_minimum_key_size_s sl_bt_cmd_sm_set_minimum_key_size_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_add_to_whitelist_s -{ - bd_addr address; - uint8_t address_type; -}); - -typedef struct sl_bt_cmd_sm_add_to_whitelist_s sl_bt_cmd_sm_add_to_whitelist_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_store_bonding_configuration_s -{ - uint8_t max_bonding_count; - uint8_t policy_flags; -}); - -typedef struct sl_bt_cmd_sm_store_bonding_configuration_s sl_bt_cmd_sm_store_bonding_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_bondable_mode_s -{ - uint8_t bondable; -}); - -typedef struct sl_bt_cmd_sm_set_bondable_mode_s sl_bt_cmd_sm_set_bondable_mode_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_passkey_s -{ - int32_t passkey; -}); - -typedef struct sl_bt_cmd_sm_set_passkey_s sl_bt_cmd_sm_set_passkey_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_increase_security_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_sm_increase_security_s sl_bt_cmd_sm_increase_security_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_enter_passkey_s -{ - uint8_t connection; - int32_t passkey; -}); - -typedef struct sl_bt_cmd_sm_enter_passkey_s sl_bt_cmd_sm_enter_passkey_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_passkey_confirm_s -{ - uint8_t connection; - uint8_t confirm; -}); - -typedef struct sl_bt_cmd_sm_passkey_confirm_s sl_bt_cmd_sm_passkey_confirm_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_bonding_confirm_s -{ - uint8_t connection; - uint8_t confirm; -}); - -typedef struct sl_bt_cmd_sm_bonding_confirm_s sl_bt_cmd_sm_bonding_confirm_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_delete_bonding_s -{ - uint8_t bonding; -}); - -typedef struct sl_bt_cmd_sm_delete_bonding_s sl_bt_cmd_sm_delete_bonding_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_get_bonding_handles_s -{ - uint32_t reserved; -}); - -typedef struct sl_bt_cmd_sm_get_bonding_handles_s sl_bt_cmd_sm_get_bonding_handles_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_get_bonding_details_s -{ - uint32_t bonding; -}); - -typedef struct sl_bt_cmd_sm_get_bonding_details_s sl_bt_cmd_sm_get_bonding_details_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_find_bonding_by_address_s -{ - bd_addr address; -}); - -typedef struct sl_bt_cmd_sm_find_bonding_by_address_s sl_bt_cmd_sm_find_bonding_by_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_resolve_rpa_s -{ - bd_addr rpa; -}); - -typedef struct sl_bt_cmd_sm_resolve_rpa_s sl_bt_cmd_sm_resolve_rpa_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_bonding_key_s -{ - uint32_t bonding; - uint8_t key_type; - aes_key_128 key; -}); - -typedef struct sl_bt_cmd_sm_set_bonding_key_s sl_bt_cmd_sm_set_bonding_key_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_legacy_oob_s -{ - uint8_t enable; - aes_key_128 oob_data; -}); - -typedef struct sl_bt_cmd_sm_set_legacy_oob_s sl_bt_cmd_sm_set_legacy_oob_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_oob_s -{ - uint8_t enable; -}); - -typedef struct sl_bt_cmd_sm_set_oob_s sl_bt_cmd_sm_set_oob_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_remote_oob_s -{ - uint8_t enable; - aes_key_128 random; - aes_key_128 confirm; -}); - -typedef struct sl_bt_cmd_sm_set_remote_oob_s sl_bt_cmd_sm_set_remote_oob_t; - - -PACKSTRUCT( struct sl_bt_cmd_sm_set_bonding_data_s -{ - uint8_t connection; - uint8_t type; - uint8array data; -}); - -typedef struct sl_bt_cmd_sm_set_bonding_data_s sl_bt_cmd_sm_set_bonding_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_external_bondingdb_set_data_s -{ - uint8_t connection; - uint8_t type; - uint8array data; -}); - -typedef struct sl_bt_cmd_external_bondingdb_set_data_s sl_bt_cmd_external_bondingdb_set_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_resolving_list_add_device_by_bonding_s -{ - uint32_t bonding; - uint8_t privacy_mode; -}); - -typedef struct sl_bt_cmd_resolving_list_add_device_by_bonding_s sl_bt_cmd_resolving_list_add_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_cmd_resolving_list_add_device_by_address_s -{ - bd_addr address; - uint8_t address_type; - aes_key_128 key; - uint8_t privacy_mode; -}); - -typedef struct sl_bt_cmd_resolving_list_add_device_by_address_s sl_bt_cmd_resolving_list_add_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_resolving_list_remove_device_by_bonding_s -{ - uint32_t bonding; -}); - -typedef struct sl_bt_cmd_resolving_list_remove_device_by_bonding_s sl_bt_cmd_resolving_list_remove_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_cmd_resolving_list_remove_device_by_address_s -{ - bd_addr address; - uint8_t address_type; -}); - -typedef struct sl_bt_cmd_resolving_list_remove_device_by_address_s sl_bt_cmd_resolving_list_remove_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_accept_list_add_device_by_bonding_s -{ - uint32_t bonding; -}); - -typedef struct sl_bt_cmd_accept_list_add_device_by_bonding_s sl_bt_cmd_accept_list_add_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_cmd_accept_list_add_device_by_address_s -{ - bd_addr address; - uint8_t address_type; -}); - -typedef struct sl_bt_cmd_accept_list_add_device_by_address_s sl_bt_cmd_accept_list_add_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_accept_list_remove_device_by_bonding_s -{ - uint32_t bonding; -}); - -typedef struct sl_bt_cmd_accept_list_remove_device_by_bonding_s sl_bt_cmd_accept_list_remove_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_cmd_accept_list_remove_device_by_address_s -{ - bd_addr address; - uint8_t address_type; -}); - -typedef struct sl_bt_cmd_accept_list_remove_device_by_address_s sl_bt_cmd_accept_list_remove_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_cmd_ota_set_device_name_s -{ - uint8array name; -}); - -typedef struct sl_bt_cmd_ota_set_device_name_s sl_bt_cmd_ota_set_device_name_t; - - -PACKSTRUCT( struct sl_bt_cmd_ota_set_advertising_data_s -{ - uint8_t packet_type; - uint8array adv_data; -}); - -typedef struct sl_bt_cmd_ota_set_advertising_data_s sl_bt_cmd_ota_set_advertising_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_ota_set_configuration_s -{ - uint32_t flags; -}); - -typedef struct sl_bt_cmd_ota_set_configuration_s sl_bt_cmd_ota_set_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_ota_set_rf_path_s -{ - uint8_t enable; - uint8_t antenna; -}); - -typedef struct sl_bt_cmd_ota_set_rf_path_s sl_bt_cmd_ota_set_rf_path_t; - - -PACKSTRUCT( struct sl_bt_cmd_coex_set_options_s -{ - uint32_t mask; - uint32_t options; -}); - -typedef struct sl_bt_cmd_coex_set_options_s sl_bt_cmd_coex_set_options_t; - - -PACKSTRUCT( struct sl_bt_cmd_coex_set_parameters_s -{ - uint8_t priority; - uint8_t request; - uint8_t pwm_period; - uint8_t pwm_dutycycle; -}); - -typedef struct sl_bt_cmd_coex_set_parameters_s sl_bt_cmd_coex_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_coex_set_directional_priority_pulse_s -{ - uint8_t pulse; -}); - -typedef struct sl_bt_cmd_coex_set_directional_priority_pulse_s sl_bt_cmd_coex_set_directional_priority_pulse_t; - - -PACKSTRUCT( struct sl_bt_cmd_coex_get_counters_s -{ - uint8_t reset; -}); - -typedef struct sl_bt_cmd_coex_get_counters_s sl_bt_cmd_coex_get_counters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_security_enable_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_cs_security_enable_s sl_bt_cmd_cs_security_enable_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_set_default_settings_s -{ - uint8_t connection; - uint8_t initiator_status; - uint8_t reflector_status; - uint8_t antenna_identifier; - int8_t max_tx_power; -}); - -typedef struct sl_bt_cmd_cs_set_default_settings_s sl_bt_cmd_cs_set_default_settings_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_create_config_s -{ - uint8_t connection; - uint8_t config_id; - uint8_t create_context; - uint8_t main_mode_type; - uint8_t sub_mode_type; - uint8_t min_main_mode_steps; - uint8_t max_main_mode_steps; - uint8_t main_mode_repetition; - uint8_t mode_calibration_steps; - uint8_t role; - uint8_t rtt_type; - uint8_t cs_sync_phy; - sl_bt_cs_channel_map_t channel_map; - uint8_t channel_map_repetition; - uint8_t channel_selection_type; - uint8_t ch3c_shape; - uint8_t ch3c_jump; - uint8_t companion_signal_state; -}); - -typedef struct sl_bt_cmd_cs_create_config_s sl_bt_cmd_cs_create_config_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_remove_config_s -{ - uint8_t connection; - uint8_t config_id; -}); - -typedef struct sl_bt_cmd_cs_remove_config_s sl_bt_cmd_cs_remove_config_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_set_channel_classification_s -{ - sl_bt_cs_channel_map_t channel_map; -}); - -typedef struct sl_bt_cmd_cs_set_channel_classification_s sl_bt_cmd_cs_set_channel_classification_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_set_procedure_parameters_s -{ - uint8_t connection; - uint8_t config_id; - uint16_t max_procedure_len; - uint16_t min_procedure_interval; - uint16_t max_procedure_interval; - uint16_t max_procedure_count; - uint32_t min_subevent_len; - uint32_t max_subevent_len; - uint8_t tone_antenna_config_selection; - uint8_t phy; - int8_t tx_pwr_delta; - uint8_t preferred_peer_antenna; -}); - -typedef struct sl_bt_cmd_cs_set_procedure_parameters_s sl_bt_cmd_cs_set_procedure_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_procedure_enable_s -{ - uint8_t connection; - uint8_t enable; - uint8_t config_id; -}); - -typedef struct sl_bt_cmd_cs_procedure_enable_s sl_bt_cmd_cs_procedure_enable_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_set_antenna_configuration_s -{ - uint8array antenna_element_offset; -}); - -typedef struct sl_bt_cmd_cs_set_antenna_configuration_s sl_bt_cmd_cs_set_antenna_configuration_t; - - -PACKSTRUCT( struct sl_bt_cmd_cs_test_start_s -{ - uint8_t main_mode_type; - uint8_t sub_mode_type; - uint8_t main_mode_repetition; - uint8_t mode_calibration_steps; - uint8_t role; - uint8_t rtt_type; - uint8_t cs_sync_phy; - uint8_t antenna_selection; - sl_bt_cs_subevent_length_t subevent_len; - uint16_t subevent_interval; - int8_t tx_power; - uint8_t t_ip1_time; - uint8_t t_ip2_time; - uint8_t t_fcs_time; - uint8_t t_pm_time; - uint8_t t_sw_time; - uint8_t tone_antenna_config; - uint8_t companion_signal_state; - uint16_t drbg_nonce; - uint16_t override_config; - uint8array override_parameters; -}); - -typedef struct sl_bt_cmd_cs_test_start_s sl_bt_cmd_cs_test_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_l2cap_open_le_channel_s -{ - uint8_t connection; - uint16_t spsm; - uint16_t max_sdu; - uint16_t max_pdu; - uint16_t credit; -}); - -typedef struct sl_bt_cmd_l2cap_open_le_channel_s sl_bt_cmd_l2cap_open_le_channel_t; - - -PACKSTRUCT( struct sl_bt_cmd_l2cap_send_le_channel_open_response_s -{ - uint8_t connection; - uint16_t cid; - uint16_t max_sdu; - uint16_t max_pdu; - uint16_t credit; - uint16_t errorcode; -}); - -typedef struct sl_bt_cmd_l2cap_send_le_channel_open_response_s sl_bt_cmd_l2cap_send_le_channel_open_response_t; - - -PACKSTRUCT( struct sl_bt_cmd_l2cap_channel_send_data_s -{ - uint8_t connection; - uint16_t cid; - uint8array data; -}); - -typedef struct sl_bt_cmd_l2cap_channel_send_data_s sl_bt_cmd_l2cap_channel_send_data_t; - - -PACKSTRUCT( struct sl_bt_cmd_l2cap_channel_send_credit_s -{ - uint8_t connection; - uint16_t cid; - uint16_t credit; -}); - -typedef struct sl_bt_cmd_l2cap_channel_send_credit_s sl_bt_cmd_l2cap_channel_send_credit_t; - - -PACKSTRUCT( struct sl_bt_cmd_l2cap_close_channel_s -{ - uint8_t connection; - uint16_t cid; -}); - -typedef struct sl_bt_cmd_l2cap_close_channel_s sl_bt_cmd_l2cap_close_channel_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_set_dtm_parameters_s -{ - uint8_t cte_length; - uint8_t cte_type; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_transmitter_set_dtm_parameters_s sl_bt_cmd_cte_transmitter_set_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_connection_cte_s -{ - uint8_t connection; - uint8_t cte_types; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_transmitter_enable_connection_cte_s sl_bt_cmd_cte_transmitter_enable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_connection_cte_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_cte_transmitter_disable_connection_cte_s sl_bt_cmd_cte_transmitter_disable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_connectionless_cte_s -{ - uint8_t handle; - uint8_t cte_length; - uint8_t cte_type; - uint8_t cte_count; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_transmitter_enable_connectionless_cte_s sl_bt_cmd_cte_transmitter_enable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_connectionless_cte_s -{ - uint8_t handle; -}); - -typedef struct sl_bt_cmd_cte_transmitter_disable_connectionless_cte_s sl_bt_cmd_cte_transmitter_disable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_silabs_cte_s -{ - uint8_t handle; - uint8_t cte_length; - uint8_t cte_type; - uint8_t cte_count; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_transmitter_enable_silabs_cte_s sl_bt_cmd_cte_transmitter_enable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_silabs_cte_s -{ - uint8_t handle; -}); - -typedef struct sl_bt_cmd_cte_transmitter_disable_silabs_cte_s sl_bt_cmd_cte_transmitter_disable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_dtm_parameters_s -{ - uint8_t cte_length; - uint8_t cte_type; - uint8_t slot_durations; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_receiver_set_dtm_parameters_s sl_bt_cmd_cte_receiver_set_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_sync_cte_type_s -{ - uint8_t sync_cte_type; -}); - -typedef struct sl_bt_cmd_cte_receiver_set_sync_cte_type_s sl_bt_cmd_cte_receiver_set_sync_cte_type_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_s -{ - uint8_t mode; - uint16_t skip; - uint16_t timeout; - uint8_t sync_cte_type; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_s sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_sync_receive_parameters_s -{ - uint8_t connection; - uint8_t mode; - uint16_t skip; - uint16_t timeout; - uint8_t sync_cte_type; - uint8_t reporting_mode; -}); - -typedef struct sl_bt_cmd_cte_receiver_set_sync_receive_parameters_s sl_bt_cmd_cte_receiver_set_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_configure_s -{ - uint8_t flags; -}); - -typedef struct sl_bt_cmd_cte_receiver_configure_s sl_bt_cmd_cte_receiver_configure_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_connection_cte_s -{ - uint8_t connection; - uint16_t interval; - uint8_t cte_length; - uint8_t cte_type; - uint8_t slot_durations; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_receiver_enable_connection_cte_s sl_bt_cmd_cte_receiver_enable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_disable_connection_cte_s -{ - uint8_t connection; -}); - -typedef struct sl_bt_cmd_cte_receiver_disable_connection_cte_s sl_bt_cmd_cte_receiver_disable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_connectionless_cte_s -{ - uint16_t sync; - uint8_t slot_durations; - uint8_t cte_count; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_receiver_enable_connectionless_cte_s sl_bt_cmd_cte_receiver_enable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_disable_connectionless_cte_s -{ - uint16_t sync; -}); - -typedef struct sl_bt_cmd_cte_receiver_disable_connectionless_cte_s sl_bt_cmd_cte_receiver_disable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_silabs_cte_s -{ - uint8_t slot_durations; - uint8_t cte_count; - uint8array switching_pattern; -}); - -typedef struct sl_bt_cmd_cte_receiver_enable_silabs_cte_s sl_bt_cmd_cte_receiver_enable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_analyzer_start_s -{ - uint32_t access_address; - uint32_t crc_init; - uint16_t interval; - uint16_t supervision_timeout; - uint8_t central_clock_accuracy; - uint8_t central_phy; - uint8_t peripheral_phy; - uint8_t channel_selection_algorithm; - uint8_t hop; - sl_bt_connection_channel_map_t channel_map; - uint8_t channel; - uint16_t event_counter; - int32_t start_time_us; - uint32_t flags; -}); - -typedef struct sl_bt_cmd_connection_analyzer_start_s sl_bt_cmd_connection_analyzer_start_t; - - -PACKSTRUCT( struct sl_bt_cmd_connection_analyzer_stop_s -{ - uint8_t analyzer; -}); - -typedef struct sl_bt_cmd_connection_analyzer_stop_s sl_bt_cmd_connection_analyzer_stop_t; - - -PACKSTRUCT( struct sl_bt_cmd_user_message_to_target_s -{ - uint8array data; -}); - -typedef struct sl_bt_cmd_user_message_to_target_s sl_bt_cmd_user_message_to_target_t; - - -PACKSTRUCT( struct sl_bt_cmd_user_manage_event_filter_s -{ - uint8array data; -}); - -typedef struct sl_bt_cmd_user_manage_event_filter_s sl_bt_cmd_user_manage_event_filter_t; - - - - -PACKSTRUCT( struct sl_bt_rsp_dfu_flash_set_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_dfu_flash_set_address_s sl_bt_rsp_dfu_flash_set_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_dfu_flash_upload_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_dfu_flash_upload_s sl_bt_rsp_dfu_flash_upload_t; - - -PACKSTRUCT( struct sl_bt_rsp_dfu_flash_upload_finish_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_dfu_flash_upload_finish_s sl_bt_rsp_dfu_flash_upload_finish_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_hello_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_hello_s sl_bt_rsp_system_hello_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_start_bluetooth_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_start_bluetooth_s sl_bt_rsp_system_start_bluetooth_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_stop_bluetooth_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_stop_bluetooth_s sl_bt_rsp_system_stop_bluetooth_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_forcefully_stop_bluetooth_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_forcefully_stop_bluetooth_s sl_bt_rsp_system_forcefully_stop_bluetooth_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_get_version_s -{ - uint16_t result; - uint16_t major; - uint16_t minor; - uint16_t patch; - uint16_t build; - uint32_t bootloader; - uint32_t hash; -}); - -typedef struct sl_bt_rsp_system_get_version_s sl_bt_rsp_system_get_version_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_halt_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_halt_s sl_bt_rsp_system_halt_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_linklayer_configure_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_linklayer_configure_s sl_bt_rsp_system_linklayer_configure_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_set_tx_power_s -{ - uint16_t result; - int16_t set_min; - int16_t set_max; -}); - -typedef struct sl_bt_rsp_system_set_tx_power_s sl_bt_rsp_system_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_get_tx_power_setting_s -{ - uint16_t result; - int16_t support_min; - int16_t support_max; - int16_t set_min; - int16_t set_max; - int16_t rf_path_gain; -}); - -typedef struct sl_bt_rsp_system_get_tx_power_setting_s sl_bt_rsp_system_get_tx_power_setting_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_set_identity_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_set_identity_address_s sl_bt_rsp_system_set_identity_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_get_identity_address_s -{ - uint16_t result; - bd_addr address; - uint8_t type; -}); - -typedef struct sl_bt_rsp_system_get_identity_address_s sl_bt_rsp_system_get_identity_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_get_random_data_s -{ - uint16_t result; - uint8array data; -}); - -typedef struct sl_bt_rsp_system_get_random_data_s sl_bt_rsp_system_get_random_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_data_buffer_write_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_data_buffer_write_s sl_bt_rsp_system_data_buffer_write_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_data_buffer_clear_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_data_buffer_clear_s sl_bt_rsp_system_data_buffer_clear_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_get_counters_s -{ - uint16_t result; - uint16_t tx_packets; - uint16_t rx_packets; - uint16_t crc_errors; - uint16_t failures; -}); - -typedef struct sl_bt_rsp_system_get_counters_s sl_bt_rsp_system_get_counters_t; - - -PACKSTRUCT( struct sl_bt_rsp_system_set_lazy_soft_timer_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_system_set_lazy_soft_timer_s sl_bt_rsp_system_set_lazy_soft_timer_t; - - -PACKSTRUCT( struct sl_bt_rsp_resource_get_status_s -{ - uint16_t result; - uint32_t total_bytes; - uint32_t free_bytes; -}); - -typedef struct sl_bt_rsp_resource_get_status_s sl_bt_rsp_resource_get_status_t; - - -PACKSTRUCT( struct sl_bt_rsp_resource_set_report_threshold_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resource_set_report_threshold_s sl_bt_rsp_resource_set_report_threshold_t; - - -PACKSTRUCT( struct sl_bt_rsp_resource_enable_connection_tx_report_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resource_enable_connection_tx_report_s sl_bt_rsp_resource_enable_connection_tx_report_t; - - -PACKSTRUCT( struct sl_bt_rsp_resource_get_connection_tx_status_s -{ - uint16_t result; - uint16_t flags; - uint16_t packet_count; - uint32_t data_len; -}); - -typedef struct sl_bt_rsp_resource_get_connection_tx_status_s sl_bt_rsp_resource_get_connection_tx_status_t; - - -PACKSTRUCT( struct sl_bt_rsp_resource_disable_connection_tx_report_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resource_disable_connection_tx_report_s sl_bt_rsp_resource_disable_connection_tx_report_t; - - -PACKSTRUCT( struct sl_bt_rsp_gap_set_privacy_mode_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gap_set_privacy_mode_s sl_bt_rsp_gap_set_privacy_mode_t; - - -PACKSTRUCT( struct sl_bt_rsp_gap_set_data_channel_classification_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gap_set_data_channel_classification_s sl_bt_rsp_gap_set_data_channel_classification_t; - - -PACKSTRUCT( struct sl_bt_rsp_gap_enable_whitelisting_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gap_enable_whitelisting_s sl_bt_rsp_gap_enable_whitelisting_t; - - -PACKSTRUCT( struct sl_bt_rsp_gap_set_identity_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gap_set_identity_address_s sl_bt_rsp_gap_set_identity_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_create_set_s -{ - uint16_t result; - uint8_t handle; -}); - -typedef struct sl_bt_rsp_advertiser_create_set_s sl_bt_rsp_advertiser_create_set_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_configure_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_configure_s sl_bt_rsp_advertiser_configure_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_timing_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_timing_s sl_bt_rsp_advertiser_set_timing_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_channel_map_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_channel_map_s sl_bt_rsp_advertiser_set_channel_map_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_tx_power_s -{ - uint16_t result; - int16_t set_power; -}); - -typedef struct sl_bt_rsp_advertiser_set_tx_power_s sl_bt_rsp_advertiser_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_report_scan_request_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_report_scan_request_s sl_bt_rsp_advertiser_set_report_scan_request_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_random_address_s -{ - uint16_t result; - bd_addr address_out; -}); - -typedef struct sl_bt_rsp_advertiser_set_random_address_s sl_bt_rsp_advertiser_set_random_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_clear_random_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_clear_random_address_s sl_bt_rsp_advertiser_clear_random_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_stop_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_stop_s sl_bt_rsp_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_delete_set_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_delete_set_s sl_bt_rsp_advertiser_delete_set_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_phy_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_phy_s sl_bt_rsp_advertiser_set_phy_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_configuration_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_configuration_s sl_bt_rsp_advertiser_set_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_clear_configuration_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_clear_configuration_s sl_bt_rsp_advertiser_clear_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_data_s sl_bt_rsp_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_set_long_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_set_long_data_s sl_bt_rsp_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_start_s sl_bt_rsp_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_start_periodic_advertising_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_start_periodic_advertising_s sl_bt_rsp_advertiser_start_periodic_advertising_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_stop_periodic_advertising_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_stop_periodic_advertising_s sl_bt_rsp_advertiser_stop_periodic_advertising_t; - - -PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_set_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_legacy_advertiser_set_data_s sl_bt_rsp_legacy_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_generate_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_legacy_advertiser_generate_data_s sl_bt_rsp_legacy_advertiser_generate_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_legacy_advertiser_start_s sl_bt_rsp_legacy_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_start_directed_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_legacy_advertiser_start_directed_s sl_bt_rsp_legacy_advertiser_start_directed_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_phy_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_set_phy_s sl_bt_rsp_extended_advertiser_set_phy_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_set_data_s sl_bt_rsp_extended_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_long_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_set_long_data_s sl_bt_rsp_extended_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_generate_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_generate_data_s sl_bt_rsp_extended_advertiser_generate_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_start_s sl_bt_rsp_extended_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_start_directed_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_extended_advertiser_start_directed_s sl_bt_rsp_extended_advertiser_start_directed_t; - - -PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_set_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_periodic_advertiser_set_data_s sl_bt_rsp_periodic_advertiser_set_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_set_long_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_periodic_advertiser_set_long_data_s sl_bt_rsp_periodic_advertiser_set_long_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_periodic_advertiser_start_s sl_bt_rsp_periodic_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_stop_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_periodic_advertiser_stop_s sl_bt_rsp_periodic_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_set_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_set_parameters_s sl_bt_rsp_scanner_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_set_parameters_and_filter_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_set_parameters_and_filter_s sl_bt_rsp_scanner_set_parameters_and_filter_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_stop_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_stop_s sl_bt_rsp_scanner_stop_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_set_timing_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_set_timing_s sl_bt_rsp_scanner_set_timing_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_set_mode_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_set_mode_s sl_bt_rsp_scanner_set_mode_t; - - -PACKSTRUCT( struct sl_bt_rsp_scanner_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_scanner_start_s sl_bt_rsp_scanner_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_set_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_set_parameters_s sl_bt_rsp_sync_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_open_s -{ - uint16_t result; - uint16_t sync; -}); - -typedef struct sl_bt_rsp_sync_open_s sl_bt_rsp_sync_open_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_set_reporting_mode_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_set_reporting_mode_s sl_bt_rsp_sync_set_reporting_mode_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_update_sync_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_update_sync_parameters_s sl_bt_rsp_sync_update_sync_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_close_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_close_s sl_bt_rsp_sync_close_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_scanner_set_sync_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_scanner_set_sync_parameters_s sl_bt_rsp_sync_scanner_set_sync_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_scanner_open_s -{ - uint16_t result; - uint16_t sync; -}); - -typedef struct sl_bt_rsp_sync_scanner_open_s sl_bt_rsp_sync_scanner_open_t; - - -PACKSTRUCT( struct sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_s sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_past_receiver_set_sync_receive_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_past_receiver_set_sync_receive_parameters_s sl_bt_rsp_past_receiver_set_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_advertiser_past_transfer_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_advertiser_past_transfer_s sl_bt_rsp_advertiser_past_transfer_t; - - -PACKSTRUCT( struct sl_bt_rsp_sync_past_transfer_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sync_past_transfer_s sl_bt_rsp_sync_past_transfer_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_sync_set_sync_subevents_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_pawr_sync_set_sync_subevents_s sl_bt_rsp_pawr_sync_set_sync_subevents_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_sync_set_response_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_pawr_sync_set_response_data_s sl_bt_rsp_pawr_sync_set_response_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_pawr_advertiser_start_s sl_bt_rsp_pawr_advertiser_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_set_subevent_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_pawr_advertiser_set_subevent_data_s sl_bt_rsp_pawr_advertiser_set_subevent_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_create_connection_s -{ - uint16_t result; - uint8_t connection; -}); - -typedef struct sl_bt_rsp_pawr_advertiser_create_connection_s sl_bt_rsp_pawr_advertiser_create_connection_t; - - -PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_stop_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_pawr_advertiser_stop_s sl_bt_rsp_pawr_advertiser_stop_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_default_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_default_parameters_s sl_bt_rsp_connection_set_default_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_default_preferred_phy_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_default_preferred_phy_s sl_bt_rsp_connection_set_default_preferred_phy_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_default_data_length_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_default_data_length_s sl_bt_rsp_connection_set_default_data_length_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_open_s -{ - uint16_t result; - uint8_t connection; -}); - -typedef struct sl_bt_rsp_connection_open_s sl_bt_rsp_connection_open_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_parameters_s sl_bt_rsp_connection_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_preferred_phy_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_preferred_phy_s sl_bt_rsp_connection_set_preferred_phy_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_disable_slave_latency_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_disable_slave_latency_s sl_bt_rsp_connection_disable_slave_latency_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_median_rssi_s -{ - uint16_t result; - int8_t rssi; -}); - -typedef struct sl_bt_rsp_connection_get_median_rssi_s sl_bt_rsp_connection_get_median_rssi_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_read_channel_map_s -{ - uint16_t result; - uint8array channel_map; -}); - -typedef struct sl_bt_rsp_connection_read_channel_map_s sl_bt_rsp_connection_read_channel_map_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_power_reporting_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_power_reporting_s sl_bt_rsp_connection_set_power_reporting_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_remote_power_reporting_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_remote_power_reporting_s sl_bt_rsp_connection_set_remote_power_reporting_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_tx_power_s -{ - uint16_t result; - int8_t current_level; - int8_t max_level; -}); - -typedef struct sl_bt_rsp_connection_get_tx_power_s sl_bt_rsp_connection_get_tx_power_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_remote_tx_power_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_get_remote_tx_power_s sl_bt_rsp_connection_get_remote_tx_power_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_tx_power_s -{ - uint16_t result; - int16_t tx_power_out; -}); - -typedef struct sl_bt_rsp_connection_set_tx_power_s sl_bt_rsp_connection_set_tx_power_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_read_remote_used_features_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_read_remote_used_features_s sl_bt_rsp_connection_read_remote_used_features_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_security_status_s -{ - uint16_t result; - uint8_t security_mode; - uint8_t key_size; - uint8_t bonding_handle; -}); - -typedef struct sl_bt_rsp_connection_get_security_status_s sl_bt_rsp_connection_get_security_status_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_set_data_length_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_set_data_length_s sl_bt_rsp_connection_set_data_length_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_read_statistics_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_read_statistics_s sl_bt_rsp_connection_read_statistics_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_scheduling_details_s -{ - uint16_t result; - uint32_t access_address; - uint8_t role; - uint32_t crc_init; - uint16_t interval; - uint16_t supervision_timeout; - uint8_t central_clock_accuracy; - uint8_t central_phy; - uint8_t peripheral_phy; - uint8_t channel_selection_algorithm; - uint8_t hop; - sl_bt_connection_channel_map_t channel_map; - uint8_t channel; - uint16_t event_counter; - uint32_t start_time_us; -}); - -typedef struct sl_bt_rsp_connection_get_scheduling_details_s sl_bt_rsp_connection_get_scheduling_details_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_close_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_close_s sl_bt_rsp_connection_close_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_forcefully_close_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_forcefully_close_s sl_bt_rsp_connection_forcefully_close_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_get_rssi_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_get_rssi_s sl_bt_rsp_connection_get_rssi_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_set_max_mtu_s -{ - uint16_t result; - uint16_t max_mtu_out; -}); - -typedef struct sl_bt_rsp_gatt_set_max_mtu_s sl_bt_rsp_gatt_set_max_mtu_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_primary_services_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_primary_services_s sl_bt_rsp_gatt_discover_primary_services_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_primary_services_by_uuid_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_primary_services_by_uuid_s sl_bt_rsp_gatt_discover_primary_services_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_find_included_services_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_find_included_services_s sl_bt_rsp_gatt_find_included_services_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristics_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_characteristics_s sl_bt_rsp_gatt_discover_characteristics_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristics_by_uuid_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_characteristics_by_uuid_s sl_bt_rsp_gatt_discover_characteristics_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_descriptors_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_descriptors_s sl_bt_rsp_gatt_discover_descriptors_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristic_descriptors_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_discover_characteristic_descriptors_s sl_bt_rsp_gatt_discover_characteristic_descriptors_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_set_characteristic_notification_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_set_characteristic_notification_s sl_bt_rsp_gatt_set_characteristic_notification_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_send_characteristic_confirmation_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_send_characteristic_confirmation_s sl_bt_rsp_gatt_send_characteristic_confirmation_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_read_characteristic_value_s sl_bt_rsp_gatt_read_characteristic_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_from_offset_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_read_characteristic_value_from_offset_s sl_bt_rsp_gatt_read_characteristic_value_from_offset_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_read_multiple_characteristic_values_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_read_multiple_characteristic_values_s sl_bt_rsp_gatt_read_multiple_characteristic_values_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_by_uuid_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_read_characteristic_value_by_uuid_s sl_bt_rsp_gatt_read_characteristic_value_by_uuid_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_write_characteristic_value_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_write_characteristic_value_s sl_bt_rsp_gatt_write_characteristic_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_write_characteristic_value_without_response_s -{ - uint16_t result; - uint16_t sent_len; -}); - -typedef struct sl_bt_rsp_gatt_write_characteristic_value_without_response_s sl_bt_rsp_gatt_write_characteristic_value_without_response_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_prepare_characteristic_value_write_s -{ - uint16_t result; - uint16_t sent_len; -}); - -typedef struct sl_bt_rsp_gatt_prepare_characteristic_value_write_s sl_bt_rsp_gatt_prepare_characteristic_value_write_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_s -{ - uint16_t result; - uint16_t sent_len; -}); - -typedef struct sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_s sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_execute_characteristic_value_write_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_execute_characteristic_value_write_s sl_bt_rsp_gatt_execute_characteristic_value_write_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_read_descriptor_value_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_read_descriptor_value_s sl_bt_rsp_gatt_read_descriptor_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_write_descriptor_value_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_write_descriptor_value_s sl_bt_rsp_gatt_write_descriptor_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_new_session_s -{ - uint16_t result; - uint16_t session; -}); - -typedef struct sl_bt_rsp_gattdb_new_session_s sl_bt_rsp_gattdb_new_session_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_service_s -{ - uint16_t result; - uint16_t service; -}); - -typedef struct sl_bt_rsp_gattdb_add_service_s sl_bt_rsp_gattdb_add_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_service_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_remove_service_s sl_bt_rsp_gattdb_remove_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_included_service_s -{ - uint16_t result; - uint16_t attribute; -}); - -typedef struct sl_bt_rsp_gattdb_add_included_service_s sl_bt_rsp_gattdb_add_included_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_included_service_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_remove_included_service_s sl_bt_rsp_gattdb_remove_included_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid16_characteristic_s -{ - uint16_t result; - uint16_t characteristic; -}); - -typedef struct sl_bt_rsp_gattdb_add_uuid16_characteristic_s sl_bt_rsp_gattdb_add_uuid16_characteristic_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid128_characteristic_s -{ - uint16_t result; - uint16_t characteristic; -}); - -typedef struct sl_bt_rsp_gattdb_add_uuid128_characteristic_s sl_bt_rsp_gattdb_add_uuid128_characteristic_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_characteristic_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_remove_characteristic_s sl_bt_rsp_gattdb_remove_characteristic_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid16_descriptor_s -{ - uint16_t result; - uint16_t descriptor; -}); - -typedef struct sl_bt_rsp_gattdb_add_uuid16_descriptor_s sl_bt_rsp_gattdb_add_uuid16_descriptor_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid128_descriptor_s -{ - uint16_t result; - uint16_t descriptor; -}); - -typedef struct sl_bt_rsp_gattdb_add_uuid128_descriptor_s sl_bt_rsp_gattdb_add_uuid128_descriptor_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_descriptor_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_remove_descriptor_s sl_bt_rsp_gattdb_remove_descriptor_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_start_service_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_start_service_s sl_bt_rsp_gattdb_start_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_stop_service_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_stop_service_s sl_bt_rsp_gattdb_stop_service_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_start_characteristic_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_start_characteristic_s sl_bt_rsp_gattdb_start_characteristic_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_stop_characteristic_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_stop_characteristic_s sl_bt_rsp_gattdb_stop_characteristic_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_commit_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_commit_s sl_bt_rsp_gattdb_commit_t; - - -PACKSTRUCT( struct sl_bt_rsp_gattdb_abort_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gattdb_abort_s sl_bt_rsp_gattdb_abort_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_set_max_mtu_s -{ - uint16_t result; - uint16_t max_mtu_out; -}); - -typedef struct sl_bt_rsp_gatt_server_set_max_mtu_s sl_bt_rsp_gatt_server_set_max_mtu_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_get_mtu_s -{ - uint16_t result; - uint16_t mtu; -}); - -typedef struct sl_bt_rsp_gatt_server_get_mtu_s sl_bt_rsp_gatt_server_get_mtu_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_find_attribute_s -{ - uint16_t result; - uint16_t attribute; -}); - -typedef struct sl_bt_rsp_gatt_server_find_attribute_s sl_bt_rsp_gatt_server_find_attribute_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_attribute_value_s -{ - uint16_t result; - uint8array value; -}); - -typedef struct sl_bt_rsp_gatt_server_read_attribute_value_s sl_bt_rsp_gatt_server_read_attribute_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_attribute_type_s -{ - uint16_t result; - uint8array type; -}); - -typedef struct sl_bt_rsp_gatt_server_read_attribute_type_s sl_bt_rsp_gatt_server_read_attribute_type_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_write_attribute_value_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_write_attribute_value_s sl_bt_rsp_gatt_server_write_attribute_value_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_read_response_s -{ - uint16_t result; - uint16_t sent_len; -}); - -typedef struct sl_bt_rsp_gatt_server_send_user_read_response_s sl_bt_rsp_gatt_server_send_user_read_response_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_write_response_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_send_user_write_response_s sl_bt_rsp_gatt_server_send_user_write_response_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_notification_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_send_notification_s sl_bt_rsp_gatt_server_send_notification_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_indication_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_send_indication_s sl_bt_rsp_gatt_server_send_indication_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_notify_all_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_notify_all_s sl_bt_rsp_gatt_server_notify_all_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_client_configuration_s -{ - uint16_t result; - uint16_t client_config_flags; -}); - -typedef struct sl_bt_rsp_gatt_server_read_client_configuration_s sl_bt_rsp_gatt_server_read_client_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_prepare_write_response_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_send_user_prepare_write_response_s sl_bt_rsp_gatt_server_send_user_prepare_write_response_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_set_capabilities_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_set_capabilities_s sl_bt_rsp_gatt_server_set_capabilities_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_enable_capabilities_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_enable_capabilities_s sl_bt_rsp_gatt_server_enable_capabilities_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_disable_capabilities_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_gatt_server_disable_capabilities_s sl_bt_rsp_gatt_server_disable_capabilities_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_get_enabled_capabilities_s -{ - uint16_t result; - uint32_t caps; -}); - -typedef struct sl_bt_rsp_gatt_server_get_enabled_capabilities_s sl_bt_rsp_gatt_server_get_enabled_capabilities_t; - - -PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_client_supported_features_s -{ - uint16_t result; - uint8_t client_features; -}); - -typedef struct sl_bt_rsp_gatt_server_read_client_supported_features_s sl_bt_rsp_gatt_server_read_client_supported_features_t; - - -PACKSTRUCT( struct sl_bt_rsp_nvm_save_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_nvm_save_s sl_bt_rsp_nvm_save_t; - - -PACKSTRUCT( struct sl_bt_rsp_nvm_load_s -{ - uint16_t result; - uint8array value; -}); - -typedef struct sl_bt_rsp_nvm_load_s sl_bt_rsp_nvm_load_t; - - -PACKSTRUCT( struct sl_bt_rsp_nvm_erase_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_nvm_erase_s sl_bt_rsp_nvm_erase_t; - - -PACKSTRUCT( struct sl_bt_rsp_nvm_erase_all_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_nvm_erase_all_s sl_bt_rsp_nvm_erase_all_t; - - -PACKSTRUCT( struct sl_bt_rsp_test_dtm_tx_v4_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_test_dtm_tx_v4_s sl_bt_rsp_test_dtm_tx_v4_t; - - -PACKSTRUCT( struct sl_bt_rsp_test_dtm_tx_cw_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_test_dtm_tx_cw_s sl_bt_rsp_test_dtm_tx_cw_t; - - -PACKSTRUCT( struct sl_bt_rsp_test_dtm_rx_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_test_dtm_rx_s sl_bt_rsp_test_dtm_rx_t; - - -PACKSTRUCT( struct sl_bt_rsp_test_dtm_end_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_test_dtm_end_s sl_bt_rsp_test_dtm_end_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_configure_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_configure_s sl_bt_rsp_sm_configure_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_minimum_key_size_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_minimum_key_size_s sl_bt_rsp_sm_set_minimum_key_size_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_debug_mode_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_debug_mode_s sl_bt_rsp_sm_set_debug_mode_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_add_to_whitelist_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_add_to_whitelist_s sl_bt_rsp_sm_add_to_whitelist_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_store_bonding_configuration_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_store_bonding_configuration_s sl_bt_rsp_sm_store_bonding_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_bondable_mode_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_bondable_mode_s sl_bt_rsp_sm_set_bondable_mode_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_passkey_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_passkey_s sl_bt_rsp_sm_set_passkey_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_increase_security_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_increase_security_s sl_bt_rsp_sm_increase_security_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_enter_passkey_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_enter_passkey_s sl_bt_rsp_sm_enter_passkey_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_passkey_confirm_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_passkey_confirm_s sl_bt_rsp_sm_passkey_confirm_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_bonding_confirm_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_bonding_confirm_s sl_bt_rsp_sm_bonding_confirm_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_delete_bonding_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_delete_bonding_s sl_bt_rsp_sm_delete_bonding_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_delete_bondings_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_delete_bondings_s sl_bt_rsp_sm_delete_bondings_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_get_bonding_handles_s -{ - uint16_t result; - uint32_t num_bondings; - uint8array bondings; -}); - -typedef struct sl_bt_rsp_sm_get_bonding_handles_s sl_bt_rsp_sm_get_bonding_handles_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_get_bonding_details_s -{ - uint16_t result; - bd_addr address; - uint8_t address_type; - uint8_t security_mode; - uint8_t key_size; -}); - -typedef struct sl_bt_rsp_sm_get_bonding_details_s sl_bt_rsp_sm_get_bonding_details_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_find_bonding_by_address_s -{ - uint16_t result; - uint32_t bonding; - uint8_t security_mode; - uint8_t key_size; -}); - -typedef struct sl_bt_rsp_sm_find_bonding_by_address_s sl_bt_rsp_sm_find_bonding_by_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_resolve_rpa_s -{ - uint16_t result; - bd_addr address; - uint8_t address_type; - uint32_t bonding; -}); - -typedef struct sl_bt_rsp_sm_resolve_rpa_s sl_bt_rsp_sm_resolve_rpa_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_bonding_key_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_bonding_key_s sl_bt_rsp_sm_set_bonding_key_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_legacy_oob_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_legacy_oob_s sl_bt_rsp_sm_set_legacy_oob_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_oob_s -{ - uint16_t result; - aes_key_128 random; - aes_key_128 confirm; -}); - -typedef struct sl_bt_rsp_sm_set_oob_s sl_bt_rsp_sm_set_oob_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_remote_oob_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_remote_oob_s sl_bt_rsp_sm_set_remote_oob_t; - - -PACKSTRUCT( struct sl_bt_rsp_sm_set_bonding_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_sm_set_bonding_data_s sl_bt_rsp_sm_set_bonding_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_external_bondingdb_set_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_external_bondingdb_set_data_s sl_bt_rsp_external_bondingdb_set_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_resolving_list_add_device_by_bonding_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resolving_list_add_device_by_bonding_s sl_bt_rsp_resolving_list_add_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_rsp_resolving_list_add_device_by_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resolving_list_add_device_by_address_s sl_bt_rsp_resolving_list_add_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_device_by_bonding_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resolving_list_remove_device_by_bonding_s sl_bt_rsp_resolving_list_remove_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_device_by_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resolving_list_remove_device_by_address_s sl_bt_rsp_resolving_list_remove_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_all_devices_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_resolving_list_remove_all_devices_s sl_bt_rsp_resolving_list_remove_all_devices_t; - - -PACKSTRUCT( struct sl_bt_rsp_accept_list_add_device_by_bonding_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_accept_list_add_device_by_bonding_s sl_bt_rsp_accept_list_add_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_rsp_accept_list_add_device_by_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_accept_list_add_device_by_address_s sl_bt_rsp_accept_list_add_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_device_by_bonding_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_accept_list_remove_device_by_bonding_s sl_bt_rsp_accept_list_remove_device_by_bonding_t; - - -PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_device_by_address_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_accept_list_remove_device_by_address_s sl_bt_rsp_accept_list_remove_device_by_address_t; - - -PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_all_devices_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_accept_list_remove_all_devices_s sl_bt_rsp_accept_list_remove_all_devices_t; - - -PACKSTRUCT( struct sl_bt_rsp_ota_set_device_name_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_ota_set_device_name_s sl_bt_rsp_ota_set_device_name_t; - - -PACKSTRUCT( struct sl_bt_rsp_ota_set_advertising_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_ota_set_advertising_data_s sl_bt_rsp_ota_set_advertising_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_ota_set_configuration_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_ota_set_configuration_s sl_bt_rsp_ota_set_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_ota_set_rf_path_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_ota_set_rf_path_s sl_bt_rsp_ota_set_rf_path_t; - - -PACKSTRUCT( struct sl_bt_rsp_coex_set_options_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_coex_set_options_s sl_bt_rsp_coex_set_options_t; - - -PACKSTRUCT( struct sl_bt_rsp_coex_set_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_coex_set_parameters_s sl_bt_rsp_coex_set_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_coex_set_directional_priority_pulse_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_coex_set_directional_priority_pulse_s sl_bt_rsp_coex_set_directional_priority_pulse_t; - - -PACKSTRUCT( struct sl_bt_rsp_coex_get_parameters_s -{ - uint16_t result; - uint8_t priority; - uint8_t request; - uint8_t pwm_period; - uint8_t pwm_dutycycle; -}); - -typedef struct sl_bt_rsp_coex_get_parameters_s sl_bt_rsp_coex_get_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_coex_get_counters_s -{ - uint16_t result; - uint8array counters; -}); - -typedef struct sl_bt_rsp_coex_get_counters_s sl_bt_rsp_coex_get_counters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_security_enable_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_security_enable_s sl_bt_rsp_cs_security_enable_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_set_default_settings_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_set_default_settings_s sl_bt_rsp_cs_set_default_settings_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_create_config_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_create_config_s sl_bt_rsp_cs_create_config_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_remove_config_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_remove_config_s sl_bt_rsp_cs_remove_config_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_set_channel_classification_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_set_channel_classification_s sl_bt_rsp_cs_set_channel_classification_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_set_procedure_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_set_procedure_parameters_s sl_bt_rsp_cs_set_procedure_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_procedure_enable_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_procedure_enable_s sl_bt_rsp_cs_procedure_enable_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_set_antenna_configuration_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_set_antenna_configuration_s sl_bt_rsp_cs_set_antenna_configuration_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_read_local_supported_capabilities_s -{ - uint16_t result; - uint8_t num_config; - uint16_t max_consecutive_procedures; - uint8_t num_antennas; - uint8_t max_antenna_paths; - uint8_t roles; - uint8_t optional_modes; - uint8_t rtt_capability; - uint8_t rtt_aa_only; - uint8_t rtt_sounding; - uint8_t rtt_random_payload; - uint8_t optional_cs_sync_phys; - uint16_t optional_subfeatures; - uint16_t optional_t_ip1_times; - uint16_t optional_t_ip2_times; - uint16_t optional_t_fcs_times; - uint16_t optional_t_pm_times; - uint8_t t_sw_times; -}); - -typedef struct sl_bt_rsp_cs_read_local_supported_capabilities_s sl_bt_rsp_cs_read_local_supported_capabilities_t; - - -PACKSTRUCT( struct sl_bt_rsp_cs_test_start_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cs_test_start_s sl_bt_rsp_cs_test_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_l2cap_open_le_channel_s -{ - uint16_t result; - uint16_t cid; -}); - -typedef struct sl_bt_rsp_l2cap_open_le_channel_s sl_bt_rsp_l2cap_open_le_channel_t; - - -PACKSTRUCT( struct sl_bt_rsp_l2cap_send_le_channel_open_response_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_l2cap_send_le_channel_open_response_s sl_bt_rsp_l2cap_send_le_channel_open_response_t; - - -PACKSTRUCT( struct sl_bt_rsp_l2cap_channel_send_data_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_l2cap_channel_send_data_s sl_bt_rsp_l2cap_channel_send_data_t; - - -PACKSTRUCT( struct sl_bt_rsp_l2cap_channel_send_credit_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_l2cap_channel_send_credit_s sl_bt_rsp_l2cap_channel_send_credit_t; - - -PACKSTRUCT( struct sl_bt_rsp_l2cap_close_channel_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_l2cap_close_channel_s sl_bt_rsp_l2cap_close_channel_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_set_dtm_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_set_dtm_parameters_s sl_bt_rsp_cte_transmitter_set_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_clear_dtm_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_clear_dtm_parameters_s sl_bt_rsp_cte_transmitter_clear_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_connection_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_enable_connection_cte_s sl_bt_rsp_cte_transmitter_enable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_connection_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_disable_connection_cte_s sl_bt_rsp_cte_transmitter_disable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_connectionless_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_enable_connectionless_cte_s sl_bt_rsp_cte_transmitter_enable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_connectionless_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_disable_connectionless_cte_s sl_bt_rsp_cte_transmitter_disable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_silabs_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_enable_silabs_cte_s sl_bt_rsp_cte_transmitter_enable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_silabs_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_transmitter_disable_silabs_cte_s sl_bt_rsp_cte_transmitter_disable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_dtm_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_set_dtm_parameters_s sl_bt_rsp_cte_receiver_set_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_clear_dtm_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_clear_dtm_parameters_s sl_bt_rsp_cte_receiver_clear_dtm_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_sync_cte_type_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_set_sync_cte_type_s sl_bt_rsp_cte_receiver_set_sync_cte_type_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_s sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_sync_receive_parameters_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_set_sync_receive_parameters_s sl_bt_rsp_cte_receiver_set_sync_receive_parameters_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_configure_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_configure_s sl_bt_rsp_cte_receiver_configure_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_connection_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_enable_connection_cte_s sl_bt_rsp_cte_receiver_enable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_connection_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_disable_connection_cte_s sl_bt_rsp_cte_receiver_disable_connection_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_connectionless_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_enable_connectionless_cte_s sl_bt_rsp_cte_receiver_enable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_connectionless_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_disable_connectionless_cte_s sl_bt_rsp_cte_receiver_disable_connectionless_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_silabs_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_enable_silabs_cte_s sl_bt_rsp_cte_receiver_enable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_silabs_cte_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_cte_receiver_disable_silabs_cte_s sl_bt_rsp_cte_receiver_disable_silabs_cte_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_analyzer_start_s -{ - uint16_t result; - uint8_t analyzer; -}); - -typedef struct sl_bt_rsp_connection_analyzer_start_s sl_bt_rsp_connection_analyzer_start_t; - - -PACKSTRUCT( struct sl_bt_rsp_connection_analyzer_stop_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_connection_analyzer_stop_s sl_bt_rsp_connection_analyzer_stop_t; - - -PACKSTRUCT( struct sl_bt_rsp_user_message_to_target_s -{ - uint16_t result; - uint8array response; -}); - -typedef struct sl_bt_rsp_user_message_to_target_s sl_bt_rsp_user_message_to_target_t; - - -PACKSTRUCT( struct sl_bt_rsp_user_manage_event_filter_s -{ - uint16_t result; -}); - -typedef struct sl_bt_rsp_user_manage_event_filter_s sl_bt_rsp_user_manage_event_filter_t; - - - -PACKSTRUCT( struct sl_bt_packet { - uint32_t header; - union { - uint8_t handle; - sl_bt_rsp_error_t rsp_error; - sl_bt_cmd_dfu_flash_set_address_t cmd_dfu_flash_set_address; - sl_bt_cmd_dfu_flash_upload_t cmd_dfu_flash_upload; - sl_bt_cmd_system_reset_t cmd_system_reset; - sl_bt_cmd_system_halt_t cmd_system_halt; - sl_bt_cmd_system_linklayer_configure_t cmd_system_linklayer_configure; - sl_bt_cmd_system_set_tx_power_t cmd_system_set_tx_power; - sl_bt_cmd_system_set_identity_address_t cmd_system_set_identity_address; - sl_bt_cmd_system_get_random_data_t cmd_system_get_random_data; - sl_bt_cmd_system_data_buffer_write_t cmd_system_data_buffer_write; - sl_bt_cmd_system_get_counters_t cmd_system_get_counters; - sl_bt_cmd_system_set_lazy_soft_timer_t cmd_system_set_lazy_soft_timer; - sl_bt_cmd_resource_set_report_threshold_t cmd_resource_set_report_threshold; - sl_bt_cmd_resource_enable_connection_tx_report_t cmd_resource_enable_connection_tx_report; - sl_bt_cmd_resource_get_connection_tx_status_t cmd_resource_get_connection_tx_status; - sl_bt_cmd_gap_set_privacy_mode_t cmd_gap_set_privacy_mode; - sl_bt_cmd_gap_set_data_channel_classification_t cmd_gap_set_data_channel_classification; - sl_bt_cmd_gap_enable_whitelisting_t cmd_gap_enable_whitelisting; - sl_bt_cmd_gap_set_identity_address_t cmd_gap_set_identity_address; - sl_bt_cmd_advertiser_configure_t cmd_advertiser_configure; - sl_bt_cmd_advertiser_set_timing_t cmd_advertiser_set_timing; - sl_bt_cmd_advertiser_set_channel_map_t cmd_advertiser_set_channel_map; - sl_bt_cmd_advertiser_set_tx_power_t cmd_advertiser_set_tx_power; - sl_bt_cmd_advertiser_set_report_scan_request_t cmd_advertiser_set_report_scan_request; - sl_bt_cmd_advertiser_set_random_address_t cmd_advertiser_set_random_address; - sl_bt_cmd_advertiser_clear_random_address_t cmd_advertiser_clear_random_address; - sl_bt_cmd_advertiser_stop_t cmd_advertiser_stop; - sl_bt_cmd_advertiser_delete_set_t cmd_advertiser_delete_set; - sl_bt_cmd_advertiser_set_phy_t cmd_advertiser_set_phy; - sl_bt_cmd_advertiser_set_configuration_t cmd_advertiser_set_configuration; - sl_bt_cmd_advertiser_clear_configuration_t cmd_advertiser_clear_configuration; - sl_bt_cmd_advertiser_set_data_t cmd_advertiser_set_data; - sl_bt_cmd_advertiser_set_long_data_t cmd_advertiser_set_long_data; - sl_bt_cmd_advertiser_start_t cmd_advertiser_start; - sl_bt_cmd_advertiser_start_periodic_advertising_t cmd_advertiser_start_periodic_advertising; - sl_bt_cmd_advertiser_stop_periodic_advertising_t cmd_advertiser_stop_periodic_advertising; - sl_bt_cmd_legacy_advertiser_set_data_t cmd_legacy_advertiser_set_data; - sl_bt_cmd_legacy_advertiser_generate_data_t cmd_legacy_advertiser_generate_data; - sl_bt_cmd_legacy_advertiser_start_t cmd_legacy_advertiser_start; - sl_bt_cmd_legacy_advertiser_start_directed_t cmd_legacy_advertiser_start_directed; - sl_bt_cmd_extended_advertiser_set_phy_t cmd_extended_advertiser_set_phy; - sl_bt_cmd_extended_advertiser_set_data_t cmd_extended_advertiser_set_data; - sl_bt_cmd_extended_advertiser_set_long_data_t cmd_extended_advertiser_set_long_data; - sl_bt_cmd_extended_advertiser_generate_data_t cmd_extended_advertiser_generate_data; - sl_bt_cmd_extended_advertiser_start_t cmd_extended_advertiser_start; - sl_bt_cmd_extended_advertiser_start_directed_t cmd_extended_advertiser_start_directed; - sl_bt_cmd_periodic_advertiser_set_data_t cmd_periodic_advertiser_set_data; - sl_bt_cmd_periodic_advertiser_set_long_data_t cmd_periodic_advertiser_set_long_data; - sl_bt_cmd_periodic_advertiser_start_t cmd_periodic_advertiser_start; - sl_bt_cmd_periodic_advertiser_stop_t cmd_periodic_advertiser_stop; - sl_bt_cmd_scanner_set_parameters_t cmd_scanner_set_parameters; - sl_bt_cmd_scanner_set_parameters_and_filter_t cmd_scanner_set_parameters_and_filter; - sl_bt_cmd_scanner_set_timing_t cmd_scanner_set_timing; - sl_bt_cmd_scanner_set_mode_t cmd_scanner_set_mode; - sl_bt_cmd_scanner_start_t cmd_scanner_start; - sl_bt_cmd_sync_set_parameters_t cmd_sync_set_parameters; - sl_bt_cmd_sync_open_t cmd_sync_open; - sl_bt_cmd_sync_set_reporting_mode_t cmd_sync_set_reporting_mode; - sl_bt_cmd_sync_update_sync_parameters_t cmd_sync_update_sync_parameters; - sl_bt_cmd_sync_close_t cmd_sync_close; - sl_bt_cmd_sync_scanner_set_sync_parameters_t cmd_sync_scanner_set_sync_parameters; - sl_bt_cmd_sync_scanner_open_t cmd_sync_scanner_open; - sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_t cmd_past_receiver_set_default_sync_receive_parameters; - sl_bt_cmd_past_receiver_set_sync_receive_parameters_t cmd_past_receiver_set_sync_receive_parameters; - sl_bt_cmd_advertiser_past_transfer_t cmd_advertiser_past_transfer; - sl_bt_cmd_sync_past_transfer_t cmd_sync_past_transfer; - sl_bt_cmd_pawr_sync_set_sync_subevents_t cmd_pawr_sync_set_sync_subevents; - sl_bt_cmd_pawr_sync_set_response_data_t cmd_pawr_sync_set_response_data; - sl_bt_cmd_pawr_advertiser_start_t cmd_pawr_advertiser_start; - sl_bt_cmd_pawr_advertiser_set_subevent_data_t cmd_pawr_advertiser_set_subevent_data; - sl_bt_cmd_pawr_advertiser_create_connection_t cmd_pawr_advertiser_create_connection; - sl_bt_cmd_pawr_advertiser_stop_t cmd_pawr_advertiser_stop; - sl_bt_cmd_connection_set_default_parameters_t cmd_connection_set_default_parameters; - sl_bt_cmd_connection_set_default_preferred_phy_t cmd_connection_set_default_preferred_phy; - sl_bt_cmd_connection_set_default_data_length_t cmd_connection_set_default_data_length; - sl_bt_cmd_connection_open_t cmd_connection_open; - sl_bt_cmd_connection_set_parameters_t cmd_connection_set_parameters; - sl_bt_cmd_connection_set_preferred_phy_t cmd_connection_set_preferred_phy; - sl_bt_cmd_connection_disable_slave_latency_t cmd_connection_disable_slave_latency; - sl_bt_cmd_connection_get_median_rssi_t cmd_connection_get_median_rssi; - sl_bt_cmd_connection_read_channel_map_t cmd_connection_read_channel_map; - sl_bt_cmd_connection_set_power_reporting_t cmd_connection_set_power_reporting; - sl_bt_cmd_connection_set_remote_power_reporting_t cmd_connection_set_remote_power_reporting; - sl_bt_cmd_connection_get_tx_power_t cmd_connection_get_tx_power; - sl_bt_cmd_connection_get_remote_tx_power_t cmd_connection_get_remote_tx_power; - sl_bt_cmd_connection_set_tx_power_t cmd_connection_set_tx_power; - sl_bt_cmd_connection_read_remote_used_features_t cmd_connection_read_remote_used_features; - sl_bt_cmd_connection_get_security_status_t cmd_connection_get_security_status; - sl_bt_cmd_connection_set_data_length_t cmd_connection_set_data_length; - sl_bt_cmd_connection_read_statistics_t cmd_connection_read_statistics; - sl_bt_cmd_connection_get_scheduling_details_t cmd_connection_get_scheduling_details; - sl_bt_cmd_connection_close_t cmd_connection_close; - sl_bt_cmd_connection_forcefully_close_t cmd_connection_forcefully_close; - sl_bt_cmd_connection_get_rssi_t cmd_connection_get_rssi; - sl_bt_cmd_gatt_set_max_mtu_t cmd_gatt_set_max_mtu; - sl_bt_cmd_gatt_discover_primary_services_t cmd_gatt_discover_primary_services; - sl_bt_cmd_gatt_discover_primary_services_by_uuid_t cmd_gatt_discover_primary_services_by_uuid; - sl_bt_cmd_gatt_find_included_services_t cmd_gatt_find_included_services; - sl_bt_cmd_gatt_discover_characteristics_t cmd_gatt_discover_characteristics; - sl_bt_cmd_gatt_discover_characteristics_by_uuid_t cmd_gatt_discover_characteristics_by_uuid; - sl_bt_cmd_gatt_discover_descriptors_t cmd_gatt_discover_descriptors; - sl_bt_cmd_gatt_discover_characteristic_descriptors_t cmd_gatt_discover_characteristic_descriptors; - sl_bt_cmd_gatt_set_characteristic_notification_t cmd_gatt_set_characteristic_notification; - sl_bt_cmd_gatt_send_characteristic_confirmation_t cmd_gatt_send_characteristic_confirmation; - sl_bt_cmd_gatt_read_characteristic_value_t cmd_gatt_read_characteristic_value; - sl_bt_cmd_gatt_read_characteristic_value_from_offset_t cmd_gatt_read_characteristic_value_from_offset; - sl_bt_cmd_gatt_read_multiple_characteristic_values_t cmd_gatt_read_multiple_characteristic_values; - sl_bt_cmd_gatt_read_characteristic_value_by_uuid_t cmd_gatt_read_characteristic_value_by_uuid; - sl_bt_cmd_gatt_write_characteristic_value_t cmd_gatt_write_characteristic_value; - sl_bt_cmd_gatt_write_characteristic_value_without_response_t cmd_gatt_write_characteristic_value_without_response; - sl_bt_cmd_gatt_prepare_characteristic_value_write_t cmd_gatt_prepare_characteristic_value_write; - sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_t cmd_gatt_prepare_characteristic_value_reliable_write; - sl_bt_cmd_gatt_execute_characteristic_value_write_t cmd_gatt_execute_characteristic_value_write; - sl_bt_cmd_gatt_read_descriptor_value_t cmd_gatt_read_descriptor_value; - sl_bt_cmd_gatt_write_descriptor_value_t cmd_gatt_write_descriptor_value; - sl_bt_cmd_gattdb_add_service_t cmd_gattdb_add_service; - sl_bt_cmd_gattdb_remove_service_t cmd_gattdb_remove_service; - sl_bt_cmd_gattdb_add_included_service_t cmd_gattdb_add_included_service; - sl_bt_cmd_gattdb_remove_included_service_t cmd_gattdb_remove_included_service; - sl_bt_cmd_gattdb_add_uuid16_characteristic_t cmd_gattdb_add_uuid16_characteristic; - sl_bt_cmd_gattdb_add_uuid128_characteristic_t cmd_gattdb_add_uuid128_characteristic; - sl_bt_cmd_gattdb_remove_characteristic_t cmd_gattdb_remove_characteristic; - sl_bt_cmd_gattdb_add_uuid16_descriptor_t cmd_gattdb_add_uuid16_descriptor; - sl_bt_cmd_gattdb_add_uuid128_descriptor_t cmd_gattdb_add_uuid128_descriptor; - sl_bt_cmd_gattdb_remove_descriptor_t cmd_gattdb_remove_descriptor; - sl_bt_cmd_gattdb_start_service_t cmd_gattdb_start_service; - sl_bt_cmd_gattdb_stop_service_t cmd_gattdb_stop_service; - sl_bt_cmd_gattdb_start_characteristic_t cmd_gattdb_start_characteristic; - sl_bt_cmd_gattdb_stop_characteristic_t cmd_gattdb_stop_characteristic; - sl_bt_cmd_gattdb_commit_t cmd_gattdb_commit; - sl_bt_cmd_gattdb_abort_t cmd_gattdb_abort; - sl_bt_cmd_gatt_server_set_max_mtu_t cmd_gatt_server_set_max_mtu; - sl_bt_cmd_gatt_server_get_mtu_t cmd_gatt_server_get_mtu; - sl_bt_cmd_gatt_server_find_attribute_t cmd_gatt_server_find_attribute; - sl_bt_cmd_gatt_server_read_attribute_value_t cmd_gatt_server_read_attribute_value; - sl_bt_cmd_gatt_server_read_attribute_type_t cmd_gatt_server_read_attribute_type; - sl_bt_cmd_gatt_server_write_attribute_value_t cmd_gatt_server_write_attribute_value; - sl_bt_cmd_gatt_server_send_user_read_response_t cmd_gatt_server_send_user_read_response; - sl_bt_cmd_gatt_server_send_user_write_response_t cmd_gatt_server_send_user_write_response; - sl_bt_cmd_gatt_server_send_notification_t cmd_gatt_server_send_notification; - sl_bt_cmd_gatt_server_send_indication_t cmd_gatt_server_send_indication; - sl_bt_cmd_gatt_server_notify_all_t cmd_gatt_server_notify_all; - sl_bt_cmd_gatt_server_read_client_configuration_t cmd_gatt_server_read_client_configuration; - sl_bt_cmd_gatt_server_send_user_prepare_write_response_t cmd_gatt_server_send_user_prepare_write_response; - sl_bt_cmd_gatt_server_set_capabilities_t cmd_gatt_server_set_capabilities; - sl_bt_cmd_gatt_server_enable_capabilities_t cmd_gatt_server_enable_capabilities; - sl_bt_cmd_gatt_server_disable_capabilities_t cmd_gatt_server_disable_capabilities; - sl_bt_cmd_gatt_server_read_client_supported_features_t cmd_gatt_server_read_client_supported_features; - sl_bt_cmd_nvm_save_t cmd_nvm_save; - sl_bt_cmd_nvm_load_t cmd_nvm_load; - sl_bt_cmd_nvm_erase_t cmd_nvm_erase; - sl_bt_cmd_test_dtm_tx_v4_t cmd_test_dtm_tx_v4; - sl_bt_cmd_test_dtm_tx_cw_t cmd_test_dtm_tx_cw; - sl_bt_cmd_test_dtm_rx_t cmd_test_dtm_rx; - sl_bt_cmd_sm_configure_t cmd_sm_configure; - sl_bt_cmd_sm_set_minimum_key_size_t cmd_sm_set_minimum_key_size; - sl_bt_cmd_sm_add_to_whitelist_t cmd_sm_add_to_whitelist; - sl_bt_cmd_sm_store_bonding_configuration_t cmd_sm_store_bonding_configuration; - sl_bt_cmd_sm_set_bondable_mode_t cmd_sm_set_bondable_mode; - sl_bt_cmd_sm_set_passkey_t cmd_sm_set_passkey; - sl_bt_cmd_sm_increase_security_t cmd_sm_increase_security; - sl_bt_cmd_sm_enter_passkey_t cmd_sm_enter_passkey; - sl_bt_cmd_sm_passkey_confirm_t cmd_sm_passkey_confirm; - sl_bt_cmd_sm_bonding_confirm_t cmd_sm_bonding_confirm; - sl_bt_cmd_sm_delete_bonding_t cmd_sm_delete_bonding; - sl_bt_cmd_sm_get_bonding_handles_t cmd_sm_get_bonding_handles; - sl_bt_cmd_sm_get_bonding_details_t cmd_sm_get_bonding_details; - sl_bt_cmd_sm_find_bonding_by_address_t cmd_sm_find_bonding_by_address; - sl_bt_cmd_sm_resolve_rpa_t cmd_sm_resolve_rpa; - sl_bt_cmd_sm_set_bonding_key_t cmd_sm_set_bonding_key; - sl_bt_cmd_sm_set_legacy_oob_t cmd_sm_set_legacy_oob; - sl_bt_cmd_sm_set_oob_t cmd_sm_set_oob; - sl_bt_cmd_sm_set_remote_oob_t cmd_sm_set_remote_oob; - sl_bt_cmd_sm_set_bonding_data_t cmd_sm_set_bonding_data; - sl_bt_cmd_external_bondingdb_set_data_t cmd_external_bondingdb_set_data; - sl_bt_cmd_resolving_list_add_device_by_bonding_t cmd_resolving_list_add_device_by_bonding; - sl_bt_cmd_resolving_list_add_device_by_address_t cmd_resolving_list_add_device_by_address; - sl_bt_cmd_resolving_list_remove_device_by_bonding_t cmd_resolving_list_remove_device_by_bonding; - sl_bt_cmd_resolving_list_remove_device_by_address_t cmd_resolving_list_remove_device_by_address; - sl_bt_cmd_accept_list_add_device_by_bonding_t cmd_accept_list_add_device_by_bonding; - sl_bt_cmd_accept_list_add_device_by_address_t cmd_accept_list_add_device_by_address; - sl_bt_cmd_accept_list_remove_device_by_bonding_t cmd_accept_list_remove_device_by_bonding; - sl_bt_cmd_accept_list_remove_device_by_address_t cmd_accept_list_remove_device_by_address; - sl_bt_cmd_ota_set_device_name_t cmd_ota_set_device_name; - sl_bt_cmd_ota_set_advertising_data_t cmd_ota_set_advertising_data; - sl_bt_cmd_ota_set_configuration_t cmd_ota_set_configuration; - sl_bt_cmd_ota_set_rf_path_t cmd_ota_set_rf_path; - sl_bt_cmd_coex_set_options_t cmd_coex_set_options; - sl_bt_cmd_coex_set_parameters_t cmd_coex_set_parameters; - sl_bt_cmd_coex_set_directional_priority_pulse_t cmd_coex_set_directional_priority_pulse; - sl_bt_cmd_coex_get_counters_t cmd_coex_get_counters; - sl_bt_cmd_cs_security_enable_t cmd_cs_security_enable; - sl_bt_cmd_cs_set_default_settings_t cmd_cs_set_default_settings; - sl_bt_cmd_cs_create_config_t cmd_cs_create_config; - sl_bt_cmd_cs_remove_config_t cmd_cs_remove_config; - sl_bt_cmd_cs_set_channel_classification_t cmd_cs_set_channel_classification; - sl_bt_cmd_cs_set_procedure_parameters_t cmd_cs_set_procedure_parameters; - sl_bt_cmd_cs_procedure_enable_t cmd_cs_procedure_enable; - sl_bt_cmd_cs_set_antenna_configuration_t cmd_cs_set_antenna_configuration; - sl_bt_cmd_cs_test_start_t cmd_cs_test_start; - sl_bt_cmd_l2cap_open_le_channel_t cmd_l2cap_open_le_channel; - sl_bt_cmd_l2cap_send_le_channel_open_response_t cmd_l2cap_send_le_channel_open_response; - sl_bt_cmd_l2cap_channel_send_data_t cmd_l2cap_channel_send_data; - sl_bt_cmd_l2cap_channel_send_credit_t cmd_l2cap_channel_send_credit; - sl_bt_cmd_l2cap_close_channel_t cmd_l2cap_close_channel; - sl_bt_cmd_cte_transmitter_set_dtm_parameters_t cmd_cte_transmitter_set_dtm_parameters; - sl_bt_cmd_cte_transmitter_enable_connection_cte_t cmd_cte_transmitter_enable_connection_cte; - sl_bt_cmd_cte_transmitter_disable_connection_cte_t cmd_cte_transmitter_disable_connection_cte; - sl_bt_cmd_cte_transmitter_enable_connectionless_cte_t cmd_cte_transmitter_enable_connectionless_cte; - sl_bt_cmd_cte_transmitter_disable_connectionless_cte_t cmd_cte_transmitter_disable_connectionless_cte; - sl_bt_cmd_cte_transmitter_enable_silabs_cte_t cmd_cte_transmitter_enable_silabs_cte; - sl_bt_cmd_cte_transmitter_disable_silabs_cte_t cmd_cte_transmitter_disable_silabs_cte; - sl_bt_cmd_cte_receiver_set_dtm_parameters_t cmd_cte_receiver_set_dtm_parameters; - sl_bt_cmd_cte_receiver_set_sync_cte_type_t cmd_cte_receiver_set_sync_cte_type; - sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_t cmd_cte_receiver_set_default_sync_receive_parameters; - sl_bt_cmd_cte_receiver_set_sync_receive_parameters_t cmd_cte_receiver_set_sync_receive_parameters; - sl_bt_cmd_cte_receiver_configure_t cmd_cte_receiver_configure; - sl_bt_cmd_cte_receiver_enable_connection_cte_t cmd_cte_receiver_enable_connection_cte; - sl_bt_cmd_cte_receiver_disable_connection_cte_t cmd_cte_receiver_disable_connection_cte; - sl_bt_cmd_cte_receiver_enable_connectionless_cte_t cmd_cte_receiver_enable_connectionless_cte; - sl_bt_cmd_cte_receiver_disable_connectionless_cte_t cmd_cte_receiver_disable_connectionless_cte; - sl_bt_cmd_cte_receiver_enable_silabs_cte_t cmd_cte_receiver_enable_silabs_cte; - sl_bt_cmd_connection_analyzer_start_t cmd_connection_analyzer_start; - sl_bt_cmd_connection_analyzer_stop_t cmd_connection_analyzer_stop; - sl_bt_cmd_user_message_to_target_t cmd_user_message_to_target; - sl_bt_cmd_user_manage_event_filter_t cmd_user_manage_event_filter; - sl_bt_rsp_dfu_flash_set_address_t rsp_dfu_flash_set_address; - sl_bt_rsp_dfu_flash_upload_t rsp_dfu_flash_upload; - sl_bt_rsp_dfu_flash_upload_finish_t rsp_dfu_flash_upload_finish; - sl_bt_rsp_system_hello_t rsp_system_hello; - sl_bt_rsp_system_start_bluetooth_t rsp_system_start_bluetooth; - sl_bt_rsp_system_stop_bluetooth_t rsp_system_stop_bluetooth; - sl_bt_rsp_system_forcefully_stop_bluetooth_t rsp_system_forcefully_stop_bluetooth; - sl_bt_rsp_system_get_version_t rsp_system_get_version; - sl_bt_rsp_system_halt_t rsp_system_halt; - sl_bt_rsp_system_linklayer_configure_t rsp_system_linklayer_configure; - sl_bt_rsp_system_set_tx_power_t rsp_system_set_tx_power; - sl_bt_rsp_system_get_tx_power_setting_t rsp_system_get_tx_power_setting; - sl_bt_rsp_system_set_identity_address_t rsp_system_set_identity_address; - sl_bt_rsp_system_get_identity_address_t rsp_system_get_identity_address; - sl_bt_rsp_system_get_random_data_t rsp_system_get_random_data; - sl_bt_rsp_system_data_buffer_write_t rsp_system_data_buffer_write; - sl_bt_rsp_system_data_buffer_clear_t rsp_system_data_buffer_clear; - sl_bt_rsp_system_get_counters_t rsp_system_get_counters; - sl_bt_rsp_system_set_lazy_soft_timer_t rsp_system_set_lazy_soft_timer; - sl_bt_rsp_resource_get_status_t rsp_resource_get_status; - sl_bt_rsp_resource_set_report_threshold_t rsp_resource_set_report_threshold; - sl_bt_rsp_resource_enable_connection_tx_report_t rsp_resource_enable_connection_tx_report; - sl_bt_rsp_resource_get_connection_tx_status_t rsp_resource_get_connection_tx_status; - sl_bt_rsp_resource_disable_connection_tx_report_t rsp_resource_disable_connection_tx_report; - sl_bt_rsp_gap_set_privacy_mode_t rsp_gap_set_privacy_mode; - sl_bt_rsp_gap_set_data_channel_classification_t rsp_gap_set_data_channel_classification; - sl_bt_rsp_gap_enable_whitelisting_t rsp_gap_enable_whitelisting; - sl_bt_rsp_gap_set_identity_address_t rsp_gap_set_identity_address; - sl_bt_rsp_advertiser_create_set_t rsp_advertiser_create_set; - sl_bt_rsp_advertiser_configure_t rsp_advertiser_configure; - sl_bt_rsp_advertiser_set_timing_t rsp_advertiser_set_timing; - sl_bt_rsp_advertiser_set_channel_map_t rsp_advertiser_set_channel_map; - sl_bt_rsp_advertiser_set_tx_power_t rsp_advertiser_set_tx_power; - sl_bt_rsp_advertiser_set_report_scan_request_t rsp_advertiser_set_report_scan_request; - sl_bt_rsp_advertiser_set_random_address_t rsp_advertiser_set_random_address; - sl_bt_rsp_advertiser_clear_random_address_t rsp_advertiser_clear_random_address; - sl_bt_rsp_advertiser_stop_t rsp_advertiser_stop; - sl_bt_rsp_advertiser_delete_set_t rsp_advertiser_delete_set; - sl_bt_rsp_advertiser_set_phy_t rsp_advertiser_set_phy; - sl_bt_rsp_advertiser_set_configuration_t rsp_advertiser_set_configuration; - sl_bt_rsp_advertiser_clear_configuration_t rsp_advertiser_clear_configuration; - sl_bt_rsp_advertiser_set_data_t rsp_advertiser_set_data; - sl_bt_rsp_advertiser_set_long_data_t rsp_advertiser_set_long_data; - sl_bt_rsp_advertiser_start_t rsp_advertiser_start; - sl_bt_rsp_advertiser_start_periodic_advertising_t rsp_advertiser_start_periodic_advertising; - sl_bt_rsp_advertiser_stop_periodic_advertising_t rsp_advertiser_stop_periodic_advertising; - sl_bt_rsp_legacy_advertiser_set_data_t rsp_legacy_advertiser_set_data; - sl_bt_rsp_legacy_advertiser_generate_data_t rsp_legacy_advertiser_generate_data; - sl_bt_rsp_legacy_advertiser_start_t rsp_legacy_advertiser_start; - sl_bt_rsp_legacy_advertiser_start_directed_t rsp_legacy_advertiser_start_directed; - sl_bt_rsp_extended_advertiser_set_phy_t rsp_extended_advertiser_set_phy; - sl_bt_rsp_extended_advertiser_set_data_t rsp_extended_advertiser_set_data; - sl_bt_rsp_extended_advertiser_set_long_data_t rsp_extended_advertiser_set_long_data; - sl_bt_rsp_extended_advertiser_generate_data_t rsp_extended_advertiser_generate_data; - sl_bt_rsp_extended_advertiser_start_t rsp_extended_advertiser_start; - sl_bt_rsp_extended_advertiser_start_directed_t rsp_extended_advertiser_start_directed; - sl_bt_rsp_periodic_advertiser_set_data_t rsp_periodic_advertiser_set_data; - sl_bt_rsp_periodic_advertiser_set_long_data_t rsp_periodic_advertiser_set_long_data; - sl_bt_rsp_periodic_advertiser_start_t rsp_periodic_advertiser_start; - sl_bt_rsp_periodic_advertiser_stop_t rsp_periodic_advertiser_stop; - sl_bt_rsp_scanner_set_parameters_t rsp_scanner_set_parameters; - sl_bt_rsp_scanner_set_parameters_and_filter_t rsp_scanner_set_parameters_and_filter; - sl_bt_rsp_scanner_stop_t rsp_scanner_stop; - sl_bt_rsp_scanner_set_timing_t rsp_scanner_set_timing; - sl_bt_rsp_scanner_set_mode_t rsp_scanner_set_mode; - sl_bt_rsp_scanner_start_t rsp_scanner_start; - sl_bt_rsp_sync_set_parameters_t rsp_sync_set_parameters; - sl_bt_rsp_sync_open_t rsp_sync_open; - sl_bt_rsp_sync_set_reporting_mode_t rsp_sync_set_reporting_mode; - sl_bt_rsp_sync_update_sync_parameters_t rsp_sync_update_sync_parameters; - sl_bt_rsp_sync_close_t rsp_sync_close; - sl_bt_rsp_sync_scanner_set_sync_parameters_t rsp_sync_scanner_set_sync_parameters; - sl_bt_rsp_sync_scanner_open_t rsp_sync_scanner_open; - sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_t rsp_past_receiver_set_default_sync_receive_parameters; - sl_bt_rsp_past_receiver_set_sync_receive_parameters_t rsp_past_receiver_set_sync_receive_parameters; - sl_bt_rsp_advertiser_past_transfer_t rsp_advertiser_past_transfer; - sl_bt_rsp_sync_past_transfer_t rsp_sync_past_transfer; - sl_bt_rsp_pawr_sync_set_sync_subevents_t rsp_pawr_sync_set_sync_subevents; - sl_bt_rsp_pawr_sync_set_response_data_t rsp_pawr_sync_set_response_data; - sl_bt_rsp_pawr_advertiser_start_t rsp_pawr_advertiser_start; - sl_bt_rsp_pawr_advertiser_set_subevent_data_t rsp_pawr_advertiser_set_subevent_data; - sl_bt_rsp_pawr_advertiser_create_connection_t rsp_pawr_advertiser_create_connection; - sl_bt_rsp_pawr_advertiser_stop_t rsp_pawr_advertiser_stop; - sl_bt_rsp_connection_set_default_parameters_t rsp_connection_set_default_parameters; - sl_bt_rsp_connection_set_default_preferred_phy_t rsp_connection_set_default_preferred_phy; - sl_bt_rsp_connection_set_default_data_length_t rsp_connection_set_default_data_length; - sl_bt_rsp_connection_open_t rsp_connection_open; - sl_bt_rsp_connection_set_parameters_t rsp_connection_set_parameters; - sl_bt_rsp_connection_set_preferred_phy_t rsp_connection_set_preferred_phy; - sl_bt_rsp_connection_disable_slave_latency_t rsp_connection_disable_slave_latency; - sl_bt_rsp_connection_get_median_rssi_t rsp_connection_get_median_rssi; - sl_bt_rsp_connection_read_channel_map_t rsp_connection_read_channel_map; - sl_bt_rsp_connection_set_power_reporting_t rsp_connection_set_power_reporting; - sl_bt_rsp_connection_set_remote_power_reporting_t rsp_connection_set_remote_power_reporting; - sl_bt_rsp_connection_get_tx_power_t rsp_connection_get_tx_power; - sl_bt_rsp_connection_get_remote_tx_power_t rsp_connection_get_remote_tx_power; - sl_bt_rsp_connection_set_tx_power_t rsp_connection_set_tx_power; - sl_bt_rsp_connection_read_remote_used_features_t rsp_connection_read_remote_used_features; - sl_bt_rsp_connection_get_security_status_t rsp_connection_get_security_status; - sl_bt_rsp_connection_set_data_length_t rsp_connection_set_data_length; - sl_bt_rsp_connection_read_statistics_t rsp_connection_read_statistics; - sl_bt_rsp_connection_get_scheduling_details_t rsp_connection_get_scheduling_details; - sl_bt_rsp_connection_close_t rsp_connection_close; - sl_bt_rsp_connection_forcefully_close_t rsp_connection_forcefully_close; - sl_bt_rsp_connection_get_rssi_t rsp_connection_get_rssi; - sl_bt_rsp_gatt_set_max_mtu_t rsp_gatt_set_max_mtu; - sl_bt_rsp_gatt_discover_primary_services_t rsp_gatt_discover_primary_services; - sl_bt_rsp_gatt_discover_primary_services_by_uuid_t rsp_gatt_discover_primary_services_by_uuid; - sl_bt_rsp_gatt_find_included_services_t rsp_gatt_find_included_services; - sl_bt_rsp_gatt_discover_characteristics_t rsp_gatt_discover_characteristics; - sl_bt_rsp_gatt_discover_characteristics_by_uuid_t rsp_gatt_discover_characteristics_by_uuid; - sl_bt_rsp_gatt_discover_descriptors_t rsp_gatt_discover_descriptors; - sl_bt_rsp_gatt_discover_characteristic_descriptors_t rsp_gatt_discover_characteristic_descriptors; - sl_bt_rsp_gatt_set_characteristic_notification_t rsp_gatt_set_characteristic_notification; - sl_bt_rsp_gatt_send_characteristic_confirmation_t rsp_gatt_send_characteristic_confirmation; - sl_bt_rsp_gatt_read_characteristic_value_t rsp_gatt_read_characteristic_value; - sl_bt_rsp_gatt_read_characteristic_value_from_offset_t rsp_gatt_read_characteristic_value_from_offset; - sl_bt_rsp_gatt_read_multiple_characteristic_values_t rsp_gatt_read_multiple_characteristic_values; - sl_bt_rsp_gatt_read_characteristic_value_by_uuid_t rsp_gatt_read_characteristic_value_by_uuid; - sl_bt_rsp_gatt_write_characteristic_value_t rsp_gatt_write_characteristic_value; - sl_bt_rsp_gatt_write_characteristic_value_without_response_t rsp_gatt_write_characteristic_value_without_response; - sl_bt_rsp_gatt_prepare_characteristic_value_write_t rsp_gatt_prepare_characteristic_value_write; - sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_t rsp_gatt_prepare_characteristic_value_reliable_write; - sl_bt_rsp_gatt_execute_characteristic_value_write_t rsp_gatt_execute_characteristic_value_write; - sl_bt_rsp_gatt_read_descriptor_value_t rsp_gatt_read_descriptor_value; - sl_bt_rsp_gatt_write_descriptor_value_t rsp_gatt_write_descriptor_value; - sl_bt_rsp_gattdb_new_session_t rsp_gattdb_new_session; - sl_bt_rsp_gattdb_add_service_t rsp_gattdb_add_service; - sl_bt_rsp_gattdb_remove_service_t rsp_gattdb_remove_service; - sl_bt_rsp_gattdb_add_included_service_t rsp_gattdb_add_included_service; - sl_bt_rsp_gattdb_remove_included_service_t rsp_gattdb_remove_included_service; - sl_bt_rsp_gattdb_add_uuid16_characteristic_t rsp_gattdb_add_uuid16_characteristic; - sl_bt_rsp_gattdb_add_uuid128_characteristic_t rsp_gattdb_add_uuid128_characteristic; - sl_bt_rsp_gattdb_remove_characteristic_t rsp_gattdb_remove_characteristic; - sl_bt_rsp_gattdb_add_uuid16_descriptor_t rsp_gattdb_add_uuid16_descriptor; - sl_bt_rsp_gattdb_add_uuid128_descriptor_t rsp_gattdb_add_uuid128_descriptor; - sl_bt_rsp_gattdb_remove_descriptor_t rsp_gattdb_remove_descriptor; - sl_bt_rsp_gattdb_start_service_t rsp_gattdb_start_service; - sl_bt_rsp_gattdb_stop_service_t rsp_gattdb_stop_service; - sl_bt_rsp_gattdb_start_characteristic_t rsp_gattdb_start_characteristic; - sl_bt_rsp_gattdb_stop_characteristic_t rsp_gattdb_stop_characteristic; - sl_bt_rsp_gattdb_commit_t rsp_gattdb_commit; - sl_bt_rsp_gattdb_abort_t rsp_gattdb_abort; - sl_bt_rsp_gatt_server_set_max_mtu_t rsp_gatt_server_set_max_mtu; - sl_bt_rsp_gatt_server_get_mtu_t rsp_gatt_server_get_mtu; - sl_bt_rsp_gatt_server_find_attribute_t rsp_gatt_server_find_attribute; - sl_bt_rsp_gatt_server_read_attribute_value_t rsp_gatt_server_read_attribute_value; - sl_bt_rsp_gatt_server_read_attribute_type_t rsp_gatt_server_read_attribute_type; - sl_bt_rsp_gatt_server_write_attribute_value_t rsp_gatt_server_write_attribute_value; - sl_bt_rsp_gatt_server_send_user_read_response_t rsp_gatt_server_send_user_read_response; - sl_bt_rsp_gatt_server_send_user_write_response_t rsp_gatt_server_send_user_write_response; - sl_bt_rsp_gatt_server_send_notification_t rsp_gatt_server_send_notification; - sl_bt_rsp_gatt_server_send_indication_t rsp_gatt_server_send_indication; - sl_bt_rsp_gatt_server_notify_all_t rsp_gatt_server_notify_all; - sl_bt_rsp_gatt_server_read_client_configuration_t rsp_gatt_server_read_client_configuration; - sl_bt_rsp_gatt_server_send_user_prepare_write_response_t rsp_gatt_server_send_user_prepare_write_response; - sl_bt_rsp_gatt_server_set_capabilities_t rsp_gatt_server_set_capabilities; - sl_bt_rsp_gatt_server_enable_capabilities_t rsp_gatt_server_enable_capabilities; - sl_bt_rsp_gatt_server_disable_capabilities_t rsp_gatt_server_disable_capabilities; - sl_bt_rsp_gatt_server_get_enabled_capabilities_t rsp_gatt_server_get_enabled_capabilities; - sl_bt_rsp_gatt_server_read_client_supported_features_t rsp_gatt_server_read_client_supported_features; - sl_bt_rsp_nvm_save_t rsp_nvm_save; - sl_bt_rsp_nvm_load_t rsp_nvm_load; - sl_bt_rsp_nvm_erase_t rsp_nvm_erase; - sl_bt_rsp_nvm_erase_all_t rsp_nvm_erase_all; - sl_bt_rsp_test_dtm_tx_v4_t rsp_test_dtm_tx_v4; - sl_bt_rsp_test_dtm_tx_cw_t rsp_test_dtm_tx_cw; - sl_bt_rsp_test_dtm_rx_t rsp_test_dtm_rx; - sl_bt_rsp_test_dtm_end_t rsp_test_dtm_end; - sl_bt_rsp_sm_configure_t rsp_sm_configure; - sl_bt_rsp_sm_set_minimum_key_size_t rsp_sm_set_minimum_key_size; - sl_bt_rsp_sm_set_debug_mode_t rsp_sm_set_debug_mode; - sl_bt_rsp_sm_add_to_whitelist_t rsp_sm_add_to_whitelist; - sl_bt_rsp_sm_store_bonding_configuration_t rsp_sm_store_bonding_configuration; - sl_bt_rsp_sm_set_bondable_mode_t rsp_sm_set_bondable_mode; - sl_bt_rsp_sm_set_passkey_t rsp_sm_set_passkey; - sl_bt_rsp_sm_increase_security_t rsp_sm_increase_security; - sl_bt_rsp_sm_enter_passkey_t rsp_sm_enter_passkey; - sl_bt_rsp_sm_passkey_confirm_t rsp_sm_passkey_confirm; - sl_bt_rsp_sm_bonding_confirm_t rsp_sm_bonding_confirm; - sl_bt_rsp_sm_delete_bonding_t rsp_sm_delete_bonding; - sl_bt_rsp_sm_delete_bondings_t rsp_sm_delete_bondings; - sl_bt_rsp_sm_get_bonding_handles_t rsp_sm_get_bonding_handles; - sl_bt_rsp_sm_get_bonding_details_t rsp_sm_get_bonding_details; - sl_bt_rsp_sm_find_bonding_by_address_t rsp_sm_find_bonding_by_address; - sl_bt_rsp_sm_resolve_rpa_t rsp_sm_resolve_rpa; - sl_bt_rsp_sm_set_bonding_key_t rsp_sm_set_bonding_key; - sl_bt_rsp_sm_set_legacy_oob_t rsp_sm_set_legacy_oob; - sl_bt_rsp_sm_set_oob_t rsp_sm_set_oob; - sl_bt_rsp_sm_set_remote_oob_t rsp_sm_set_remote_oob; - sl_bt_rsp_sm_set_bonding_data_t rsp_sm_set_bonding_data; - sl_bt_rsp_external_bondingdb_set_data_t rsp_external_bondingdb_set_data; - sl_bt_rsp_resolving_list_add_device_by_bonding_t rsp_resolving_list_add_device_by_bonding; - sl_bt_rsp_resolving_list_add_device_by_address_t rsp_resolving_list_add_device_by_address; - sl_bt_rsp_resolving_list_remove_device_by_bonding_t rsp_resolving_list_remove_device_by_bonding; - sl_bt_rsp_resolving_list_remove_device_by_address_t rsp_resolving_list_remove_device_by_address; - sl_bt_rsp_resolving_list_remove_all_devices_t rsp_resolving_list_remove_all_devices; - sl_bt_rsp_accept_list_add_device_by_bonding_t rsp_accept_list_add_device_by_bonding; - sl_bt_rsp_accept_list_add_device_by_address_t rsp_accept_list_add_device_by_address; - sl_bt_rsp_accept_list_remove_device_by_bonding_t rsp_accept_list_remove_device_by_bonding; - sl_bt_rsp_accept_list_remove_device_by_address_t rsp_accept_list_remove_device_by_address; - sl_bt_rsp_accept_list_remove_all_devices_t rsp_accept_list_remove_all_devices; - sl_bt_rsp_ota_set_device_name_t rsp_ota_set_device_name; - sl_bt_rsp_ota_set_advertising_data_t rsp_ota_set_advertising_data; - sl_bt_rsp_ota_set_configuration_t rsp_ota_set_configuration; - sl_bt_rsp_ota_set_rf_path_t rsp_ota_set_rf_path; - sl_bt_rsp_coex_set_options_t rsp_coex_set_options; - sl_bt_rsp_coex_set_parameters_t rsp_coex_set_parameters; - sl_bt_rsp_coex_set_directional_priority_pulse_t rsp_coex_set_directional_priority_pulse; - sl_bt_rsp_coex_get_parameters_t rsp_coex_get_parameters; - sl_bt_rsp_coex_get_counters_t rsp_coex_get_counters; - sl_bt_rsp_cs_security_enable_t rsp_cs_security_enable; - sl_bt_rsp_cs_set_default_settings_t rsp_cs_set_default_settings; - sl_bt_rsp_cs_create_config_t rsp_cs_create_config; - sl_bt_rsp_cs_remove_config_t rsp_cs_remove_config; - sl_bt_rsp_cs_set_channel_classification_t rsp_cs_set_channel_classification; - sl_bt_rsp_cs_set_procedure_parameters_t rsp_cs_set_procedure_parameters; - sl_bt_rsp_cs_procedure_enable_t rsp_cs_procedure_enable; - sl_bt_rsp_cs_set_antenna_configuration_t rsp_cs_set_antenna_configuration; - sl_bt_rsp_cs_read_local_supported_capabilities_t rsp_cs_read_local_supported_capabilities; - sl_bt_rsp_cs_test_start_t rsp_cs_test_start; - sl_bt_rsp_l2cap_open_le_channel_t rsp_l2cap_open_le_channel; - sl_bt_rsp_l2cap_send_le_channel_open_response_t rsp_l2cap_send_le_channel_open_response; - sl_bt_rsp_l2cap_channel_send_data_t rsp_l2cap_channel_send_data; - sl_bt_rsp_l2cap_channel_send_credit_t rsp_l2cap_channel_send_credit; - sl_bt_rsp_l2cap_close_channel_t rsp_l2cap_close_channel; - sl_bt_rsp_cte_transmitter_set_dtm_parameters_t rsp_cte_transmitter_set_dtm_parameters; - sl_bt_rsp_cte_transmitter_clear_dtm_parameters_t rsp_cte_transmitter_clear_dtm_parameters; - sl_bt_rsp_cte_transmitter_enable_connection_cte_t rsp_cte_transmitter_enable_connection_cte; - sl_bt_rsp_cte_transmitter_disable_connection_cte_t rsp_cte_transmitter_disable_connection_cte; - sl_bt_rsp_cte_transmitter_enable_connectionless_cte_t rsp_cte_transmitter_enable_connectionless_cte; - sl_bt_rsp_cte_transmitter_disable_connectionless_cte_t rsp_cte_transmitter_disable_connectionless_cte; - sl_bt_rsp_cte_transmitter_enable_silabs_cte_t rsp_cte_transmitter_enable_silabs_cte; - sl_bt_rsp_cte_transmitter_disable_silabs_cte_t rsp_cte_transmitter_disable_silabs_cte; - sl_bt_rsp_cte_receiver_set_dtm_parameters_t rsp_cte_receiver_set_dtm_parameters; - sl_bt_rsp_cte_receiver_clear_dtm_parameters_t rsp_cte_receiver_clear_dtm_parameters; - sl_bt_rsp_cte_receiver_set_sync_cte_type_t rsp_cte_receiver_set_sync_cte_type; - sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_t rsp_cte_receiver_set_default_sync_receive_parameters; - sl_bt_rsp_cte_receiver_set_sync_receive_parameters_t rsp_cte_receiver_set_sync_receive_parameters; - sl_bt_rsp_cte_receiver_configure_t rsp_cte_receiver_configure; - sl_bt_rsp_cte_receiver_enable_connection_cte_t rsp_cte_receiver_enable_connection_cte; - sl_bt_rsp_cte_receiver_disable_connection_cte_t rsp_cte_receiver_disable_connection_cte; - sl_bt_rsp_cte_receiver_enable_connectionless_cte_t rsp_cte_receiver_enable_connectionless_cte; - sl_bt_rsp_cte_receiver_disable_connectionless_cte_t rsp_cte_receiver_disable_connectionless_cte; - sl_bt_rsp_cte_receiver_enable_silabs_cte_t rsp_cte_receiver_enable_silabs_cte; - sl_bt_rsp_cte_receiver_disable_silabs_cte_t rsp_cte_receiver_disable_silabs_cte; - sl_bt_rsp_connection_analyzer_start_t rsp_connection_analyzer_start; - sl_bt_rsp_connection_analyzer_stop_t rsp_connection_analyzer_stop; - sl_bt_rsp_user_message_to_target_t rsp_user_message_to_target; - sl_bt_rsp_user_manage_event_filter_t rsp_user_manage_event_filter; - sl_bt_evt_dfu_boot_t evt_dfu_boot; - sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; - sl_bt_evt_system_boot_t evt_system_boot; - sl_bt_evt_system_error_t evt_system_error; - sl_bt_evt_system_hardware_error_t evt_system_hardware_error; - sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; - sl_bt_evt_system_external_signal_t evt_system_external_signal; - sl_bt_evt_system_soft_timer_t evt_system_soft_timer; - sl_bt_evt_resource_status_t evt_resource_status; - sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; - sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; - sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; - sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; - sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; - sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; - sl_bt_evt_sync_opened_t evt_sync_opened; - sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; - sl_bt_evt_sync_data_t evt_sync_data; - sl_bt_evt_sync_closed_t evt_sync_closed; - sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; - sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; - sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; - sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; - sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; - sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; - sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; - sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; - sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; - sl_bt_evt_connection_opened_t evt_connection_opened; - sl_bt_evt_connection_parameters_t evt_connection_parameters; - sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; - sl_bt_evt_connection_phy_status_t evt_connection_phy_status; - sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; - sl_bt_evt_connection_tx_power_t evt_connection_tx_power; - sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; - sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; - sl_bt_evt_connection_data_length_t evt_connection_data_length; - sl_bt_evt_connection_statistics_t evt_connection_statistics; - sl_bt_evt_connection_closed_t evt_connection_closed; - sl_bt_evt_connection_rssi_t evt_connection_rssi; - sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; - sl_bt_evt_gatt_service_t evt_gatt_service; - sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; - sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; - sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; - sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; - sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; - sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; - sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; - sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; - sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; - sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; - sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; - sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; - sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; - sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; - sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; - sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; - sl_bt_evt_sm_bonded_t evt_sm_bonded; - sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; - sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; - sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; - sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; - sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; - sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; - sl_bt_evt_cs_config_complete_t evt_cs_config_complete; - sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; - sl_bt_evt_cs_result_t evt_cs_result; - sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; - sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; - sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; - sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; - sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; - sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; - sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; - sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; - sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; - sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; - sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; - sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; - sl_bt_evt_user_message_to_host_t evt_user_message_to_host; - uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; - } data; -}); - -#ifdef __cplusplus -} -#endif - +/***************************************************************************//** + * @brief SL_BT_API library at application layer provided as source code + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_API_H +#define SLI_BT_API_H +#define VERSION no_link_tables + +#include "sl_bt_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum sli_bt_class_id +{ + sli_bt_dfu_class_id = 0x00, + sli_bt_system_class_id = 0x01, + sli_bt_resource_class_id = 0x5f, + sli_bt_gap_class_id = 0x02, + sli_bt_advertiser_class_id = 0x04, + sli_bt_legacy_advertiser_class_id = 0x56, + sli_bt_extended_advertiser_class_id = 0x57, + sli_bt_periodic_advertiser_class_id = 0x58, + sli_bt_scanner_class_id = 0x05, + sli_bt_sync_class_id = 0x42, + sli_bt_sync_scanner_class_id = 0x50, + sli_bt_past_receiver_class_id = 0x51, + sli_bt_advertiser_past_class_id = 0x52, + sli_bt_sync_past_class_id = 0x5b, + sli_bt_periodic_sync_class_id = 0x53, + sli_bt_pawr_sync_class_id = 0x54, + sli_bt_pawr_advertiser_class_id = 0x55, + sli_bt_connection_class_id = 0x06, + sli_bt_gatt_class_id = 0x09, + sli_bt_gattdb_class_id = 0x46, + sli_bt_gatt_server_class_id = 0x0a, + sli_bt_nvm_class_id = 0x0d, + sli_bt_test_class_id = 0x0e, + sli_bt_sm_class_id = 0x0f, + sli_bt_external_bondingdb_class_id = 0x5c, + sli_bt_resolving_list_class_id = 0x5d, + sli_bt_accept_list_class_id = 0x5e, + sli_bt_ota_class_id = 0x10, + sli_bt_coex_class_id = 0x20, + sli_bt_cs_class_id = 0x59, + sli_bt_cs_test_class_id = 0x5A, + sli_bt_l2cap_class_id = 0x43, + sli_bt_cte_transmitter_class_id = 0x44, + sli_bt_cte_receiver_class_id = 0x45, + sli_bt_connection_analyzer_class_id = 0x48, + sli_bt_user_class_id = 0xff, +}; + +enum sli_bt_command_id +{ + sli_bt_dfu_flash_set_address_command_id = 0x01, + sli_bt_dfu_flash_upload_command_id = 0x02, + sli_bt_dfu_flash_upload_finish_command_id = 0x03, + sli_bt_system_hello_command_id = 0x00, + sli_bt_system_start_bluetooth_command_id = 0x1c, + sli_bt_system_stop_bluetooth_command_id = 0x1d, + sli_bt_system_forcefully_stop_bluetooth_command_id = 0x1e, + sli_bt_system_get_version_command_id = 0x1b, + sli_bt_system_reset_command_id = 0x01, + sli_bt_system_halt_command_id = 0x0c, + sli_bt_system_linklayer_configure_command_id = 0x0e, + sli_bt_system_set_tx_power_command_id = 0x17, + sli_bt_system_get_tx_power_setting_command_id = 0x18, + sli_bt_system_set_identity_address_command_id = 0x13, + sli_bt_system_get_identity_address_command_id = 0x15, + sli_bt_system_get_random_data_command_id = 0x0b, + sli_bt_system_data_buffer_write_command_id = 0x12, + sli_bt_system_data_buffer_clear_command_id = 0x14, + sli_bt_system_get_counters_command_id = 0x0f, + sli_bt_system_set_lazy_soft_timer_command_id = 0x1a, + sli_bt_resource_get_status_command_id = 0x00, + sli_bt_resource_set_report_threshold_command_id = 0x01, + sli_bt_resource_enable_connection_tx_report_command_id = 0x02, + sli_bt_resource_get_connection_tx_status_command_id = 0x03, + sli_bt_resource_disable_connection_tx_report_command_id = 0x04, + sli_bt_gap_set_privacy_mode_command_id = 0x01, + sli_bt_gap_set_data_channel_classification_command_id = 0x02, + sli_bt_gap_enable_whitelisting_command_id = 0x03, + sli_bt_gap_set_identity_address_command_id = 0x04, + sli_bt_advertiser_create_set_command_id = 0x01, + sli_bt_advertiser_configure_command_id = 0x12, + sli_bt_advertiser_set_timing_command_id = 0x03, + sli_bt_advertiser_set_channel_map_command_id = 0x04, + sli_bt_advertiser_set_tx_power_command_id = 0x0b, + sli_bt_advertiser_set_report_scan_request_command_id = 0x05, + sli_bt_advertiser_set_random_address_command_id = 0x10, + sli_bt_advertiser_clear_random_address_command_id = 0x11, + sli_bt_advertiser_stop_command_id = 0x0a, + sli_bt_advertiser_delete_set_command_id = 0x02, + sli_bt_advertiser_set_phy_command_id = 0x06, + sli_bt_advertiser_set_configuration_command_id = 0x07, + sli_bt_advertiser_clear_configuration_command_id = 0x08, + sli_bt_advertiser_set_data_command_id = 0x0f, + sli_bt_advertiser_set_long_data_command_id = 0x0e, + sli_bt_advertiser_start_command_id = 0x09, + sli_bt_advertiser_start_periodic_advertising_command_id = 0x0c, + sli_bt_advertiser_stop_periodic_advertising_command_id = 0x0d, + sli_bt_legacy_advertiser_set_data_command_id = 0x00, + sli_bt_legacy_advertiser_generate_data_command_id = 0x01, + sli_bt_legacy_advertiser_start_command_id = 0x02, + sli_bt_legacy_advertiser_start_directed_command_id = 0x03, + sli_bt_extended_advertiser_set_phy_command_id = 0x00, + sli_bt_extended_advertiser_set_data_command_id = 0x01, + sli_bt_extended_advertiser_set_long_data_command_id = 0x02, + sli_bt_extended_advertiser_generate_data_command_id = 0x03, + sli_bt_extended_advertiser_start_command_id = 0x04, + sli_bt_extended_advertiser_start_directed_command_id = 0x05, + sli_bt_periodic_advertiser_set_data_command_id = 0x00, + sli_bt_periodic_advertiser_set_long_data_command_id = 0x01, + sli_bt_periodic_advertiser_start_command_id = 0x02, + sli_bt_periodic_advertiser_stop_command_id = 0x03, + sli_bt_scanner_set_parameters_command_id = 0x06, + sli_bt_scanner_set_parameters_and_filter_command_id = 0x07, + sli_bt_scanner_stop_command_id = 0x05, + sli_bt_scanner_set_timing_command_id = 0x01, + sli_bt_scanner_set_mode_command_id = 0x02, + sli_bt_scanner_start_command_id = 0x03, + sli_bt_sync_set_parameters_command_id = 0x02, + sli_bt_sync_open_command_id = 0x00, + sli_bt_sync_set_reporting_mode_command_id = 0x03, + sli_bt_sync_update_sync_parameters_command_id = 0x04, + sli_bt_sync_close_command_id = 0x01, + sli_bt_sync_scanner_set_sync_parameters_command_id = 0x00, + sli_bt_sync_scanner_open_command_id = 0x01, + sli_bt_past_receiver_set_default_sync_receive_parameters_command_id = 0x00, + sli_bt_past_receiver_set_sync_receive_parameters_command_id = 0x01, + sli_bt_advertiser_past_transfer_command_id = 0x00, + sli_bt_sync_past_transfer_command_id = 0x00, + sli_bt_pawr_sync_set_sync_subevents_command_id = 0x02, + sli_bt_pawr_sync_set_response_data_command_id = 0x03, + sli_bt_pawr_advertiser_start_command_id = 0x00, + sli_bt_pawr_advertiser_set_subevent_data_command_id = 0x01, + sli_bt_pawr_advertiser_create_connection_command_id = 0x02, + sli_bt_pawr_advertiser_stop_command_id = 0x03, + sli_bt_connection_set_default_parameters_command_id = 0x00, + sli_bt_connection_set_default_preferred_phy_command_id = 0x01, + sli_bt_connection_set_default_data_length_command_id = 0x10, + sli_bt_connection_open_command_id = 0x04, + sli_bt_connection_set_parameters_command_id = 0x06, + sli_bt_connection_set_preferred_phy_command_id = 0x08, + sli_bt_connection_disable_slave_latency_command_id = 0x03, + sli_bt_connection_get_median_rssi_command_id = 0x15, + sli_bt_connection_read_channel_map_command_id = 0x07, + sli_bt_connection_set_power_reporting_command_id = 0x09, + sli_bt_connection_set_remote_power_reporting_command_id = 0x0a, + sli_bt_connection_get_tx_power_command_id = 0x0b, + sli_bt_connection_get_remote_tx_power_command_id = 0x0c, + sli_bt_connection_set_tx_power_command_id = 0x12, + sli_bt_connection_read_remote_used_features_command_id = 0x0d, + sli_bt_connection_get_security_status_command_id = 0x0e, + sli_bt_connection_set_data_length_command_id = 0x11, + sli_bt_connection_read_statistics_command_id = 0x13, + sli_bt_connection_get_scheduling_details_command_id = 0x14, + sli_bt_connection_close_command_id = 0x05, + sli_bt_connection_forcefully_close_command_id = 0x0f, + sli_bt_connection_get_rssi_command_id = 0x02, + sli_bt_gatt_set_max_mtu_command_id = 0x00, + sli_bt_gatt_discover_primary_services_command_id = 0x01, + sli_bt_gatt_discover_primary_services_by_uuid_command_id = 0x02, + sli_bt_gatt_find_included_services_command_id = 0x10, + sli_bt_gatt_discover_characteristics_command_id = 0x03, + sli_bt_gatt_discover_characteristics_by_uuid_command_id = 0x04, + sli_bt_gatt_discover_descriptors_command_id = 0x06, + sli_bt_gatt_discover_characteristic_descriptors_command_id = 0x14, + sli_bt_gatt_set_characteristic_notification_command_id = 0x05, + sli_bt_gatt_send_characteristic_confirmation_command_id = 0x0d, + sli_bt_gatt_read_characteristic_value_command_id = 0x07, + sli_bt_gatt_read_characteristic_value_from_offset_command_id = 0x12, + sli_bt_gatt_read_multiple_characteristic_values_command_id = 0x11, + sli_bt_gatt_read_characteristic_value_by_uuid_command_id = 0x08, + sli_bt_gatt_write_characteristic_value_command_id = 0x09, + sli_bt_gatt_write_characteristic_value_without_response_command_id = 0x0a, + sli_bt_gatt_prepare_characteristic_value_write_command_id = 0x0b, + sli_bt_gatt_prepare_characteristic_value_reliable_write_command_id = 0x13, + sli_bt_gatt_execute_characteristic_value_write_command_id = 0x0c, + sli_bt_gatt_read_descriptor_value_command_id = 0x0e, + sli_bt_gatt_write_descriptor_value_command_id = 0x0f, + sli_bt_gattdb_new_session_command_id = 0x00, + sli_bt_gattdb_add_service_command_id = 0x01, + sli_bt_gattdb_remove_service_command_id = 0x02, + sli_bt_gattdb_add_included_service_command_id = 0x03, + sli_bt_gattdb_remove_included_service_command_id = 0x04, + sli_bt_gattdb_add_uuid16_characteristic_command_id = 0x05, + sli_bt_gattdb_add_uuid128_characteristic_command_id = 0x06, + sli_bt_gattdb_remove_characteristic_command_id = 0x07, + sli_bt_gattdb_add_uuid16_descriptor_command_id = 0x08, + sli_bt_gattdb_add_uuid128_descriptor_command_id = 0x09, + sli_bt_gattdb_remove_descriptor_command_id = 0x0a, + sli_bt_gattdb_start_service_command_id = 0x0b, + sli_bt_gattdb_stop_service_command_id = 0x0c, + sli_bt_gattdb_start_characteristic_command_id = 0x0d, + sli_bt_gattdb_stop_characteristic_command_id = 0x0e, + sli_bt_gattdb_commit_command_id = 0x0f, + sli_bt_gattdb_abort_command_id = 0x10, + sli_bt_gatt_server_set_max_mtu_command_id = 0x0a, + sli_bt_gatt_server_get_mtu_command_id = 0x0b, + sli_bt_gatt_server_find_attribute_command_id = 0x06, + sli_bt_gatt_server_read_attribute_value_command_id = 0x00, + sli_bt_gatt_server_read_attribute_type_command_id = 0x01, + sli_bt_gatt_server_write_attribute_value_command_id = 0x02, + sli_bt_gatt_server_send_user_read_response_command_id = 0x03, + sli_bt_gatt_server_send_user_write_response_command_id = 0x04, + sli_bt_gatt_server_send_notification_command_id = 0x0f, + sli_bt_gatt_server_send_indication_command_id = 0x10, + sli_bt_gatt_server_notify_all_command_id = 0x11, + sli_bt_gatt_server_read_client_configuration_command_id = 0x12, + sli_bt_gatt_server_send_user_prepare_write_response_command_id = 0x14, + sli_bt_gatt_server_set_capabilities_command_id = 0x08, + sli_bt_gatt_server_enable_capabilities_command_id = 0x0c, + sli_bt_gatt_server_disable_capabilities_command_id = 0x0d, + sli_bt_gatt_server_get_enabled_capabilities_command_id = 0x0e, + sli_bt_gatt_server_read_client_supported_features_command_id = 0x15, + sli_bt_nvm_save_command_id = 0x02, + sli_bt_nvm_load_command_id = 0x03, + sli_bt_nvm_erase_command_id = 0x04, + sli_bt_nvm_erase_all_command_id = 0x01, + sli_bt_test_dtm_tx_v4_command_id = 0x03, + sli_bt_test_dtm_tx_cw_command_id = 0x04, + sli_bt_test_dtm_rx_command_id = 0x01, + sli_bt_test_dtm_end_command_id = 0x02, + sli_bt_sm_configure_command_id = 0x01, + sli_bt_sm_set_minimum_key_size_command_id = 0x14, + sli_bt_sm_set_debug_mode_command_id = 0x0f, + sli_bt_sm_add_to_whitelist_command_id = 0x13, + sli_bt_sm_store_bonding_configuration_command_id = 0x02, + sli_bt_sm_set_bondable_mode_command_id = 0x00, + sli_bt_sm_set_passkey_command_id = 0x10, + sli_bt_sm_increase_security_command_id = 0x04, + sli_bt_sm_enter_passkey_command_id = 0x08, + sli_bt_sm_passkey_confirm_command_id = 0x09, + sli_bt_sm_bonding_confirm_command_id = 0x0e, + sli_bt_sm_delete_bonding_command_id = 0x06, + sli_bt_sm_delete_bondings_command_id = 0x07, + sli_bt_sm_get_bonding_handles_command_id = 0x15, + sli_bt_sm_get_bonding_details_command_id = 0x16, + sli_bt_sm_find_bonding_by_address_command_id = 0x17, + sli_bt_sm_resolve_rpa_command_id = 0x1d, + sli_bt_sm_set_bonding_key_command_id = 0x18, + sli_bt_sm_set_legacy_oob_command_id = 0x19, + sli_bt_sm_set_oob_command_id = 0x1a, + sli_bt_sm_set_remote_oob_command_id = 0x1b, + sli_bt_sm_set_bonding_data_command_id = 0x1c, + sli_bt_external_bondingdb_set_data_command_id = 0x00, + sli_bt_resolving_list_add_device_by_bonding_command_id = 0x00, + sli_bt_resolving_list_add_device_by_address_command_id = 0x01, + sli_bt_resolving_list_remove_device_by_bonding_command_id = 0x02, + sli_bt_resolving_list_remove_device_by_address_command_id = 0x03, + sli_bt_resolving_list_remove_all_devices_command_id = 0x04, + sli_bt_accept_list_add_device_by_bonding_command_id = 0x00, + sli_bt_accept_list_add_device_by_address_command_id = 0x01, + sli_bt_accept_list_remove_device_by_bonding_command_id = 0x02, + sli_bt_accept_list_remove_device_by_address_command_id = 0x03, + sli_bt_accept_list_remove_all_devices_command_id = 0x04, + sli_bt_ota_set_device_name_command_id = 0x01, + sli_bt_ota_set_advertising_data_command_id = 0x02, + sli_bt_ota_set_configuration_command_id = 0x03, + sli_bt_ota_set_rf_path_command_id = 0x04, + sli_bt_coex_set_options_command_id = 0x00, + sli_bt_coex_set_parameters_command_id = 0x02, + sli_bt_coex_set_directional_priority_pulse_command_id = 0x03, + sli_bt_coex_get_parameters_command_id = 0x04, + sli_bt_coex_get_counters_command_id = 0x01, + sli_bt_cs_security_enable_command_id = 0x00, + sli_bt_cs_set_default_settings_command_id = 0x01, + sli_bt_cs_create_config_command_id = 0x02, + sli_bt_cs_remove_config_command_id = 0x03, + sli_bt_cs_set_channel_classification_command_id = 0x04, + sli_bt_cs_set_procedure_parameters_command_id = 0x05, + sli_bt_cs_procedure_enable_command_id = 0x06, + sli_bt_cs_set_antenna_configuration_command_id = 0x07, + sli_bt_cs_read_local_supported_capabilities_command_id = 0x08, + sli_bt_cs_test_start_command_id = 0x00, + sli_bt_l2cap_open_le_channel_command_id = 0x01, + sli_bt_l2cap_send_le_channel_open_response_command_id = 0x02, + sli_bt_l2cap_channel_send_data_command_id = 0x03, + sli_bt_l2cap_channel_send_credit_command_id = 0x04, + sli_bt_l2cap_close_channel_command_id = 0x05, + sli_bt_cte_transmitter_set_dtm_parameters_command_id = 0x04, + sli_bt_cte_transmitter_clear_dtm_parameters_command_id = 0x05, + sli_bt_cte_transmitter_enable_connection_cte_command_id = 0x00, + sli_bt_cte_transmitter_disable_connection_cte_command_id = 0x01, + sli_bt_cte_transmitter_enable_connectionless_cte_command_id = 0x02, + sli_bt_cte_transmitter_disable_connectionless_cte_command_id = 0x03, + sli_bt_cte_transmitter_enable_silabs_cte_command_id = 0x06, + sli_bt_cte_transmitter_disable_silabs_cte_command_id = 0x07, + sli_bt_cte_receiver_set_dtm_parameters_command_id = 0x05, + sli_bt_cte_receiver_clear_dtm_parameters_command_id = 0x06, + sli_bt_cte_receiver_set_sync_cte_type_command_id = 0x09, + sli_bt_cte_receiver_set_default_sync_receive_parameters_command_id = 0x0a, + sli_bt_cte_receiver_set_sync_receive_parameters_command_id = 0x0b, + sli_bt_cte_receiver_configure_command_id = 0x00, + sli_bt_cte_receiver_enable_connection_cte_command_id = 0x01, + sli_bt_cte_receiver_disable_connection_cte_command_id = 0x02, + sli_bt_cte_receiver_enable_connectionless_cte_command_id = 0x03, + sli_bt_cte_receiver_disable_connectionless_cte_command_id = 0x04, + sli_bt_cte_receiver_enable_silabs_cte_command_id = 0x07, + sli_bt_cte_receiver_disable_silabs_cte_command_id = 0x08, + sli_bt_connection_analyzer_start_command_id = 0x00, + sli_bt_connection_analyzer_stop_command_id = 0x01, + sli_bt_user_message_to_target_command_id = 0x00, + sli_bt_user_manage_event_filter_command_id = 0x01, + sli_bt_user_reset_to_dfu_command_id = 0x02, +}; + +enum sli_bt_response_id +{ + sli_bt_dfu_flash_set_address_response_id = 0x01, + sli_bt_dfu_flash_upload_response_id = 0x02, + sli_bt_dfu_flash_upload_finish_response_id = 0x03, + sli_bt_system_hello_response_id = 0x00, + sli_bt_system_start_bluetooth_response_id = 0x1c, + sli_bt_system_stop_bluetooth_response_id = 0x1d, + sli_bt_system_forcefully_stop_bluetooth_response_id = 0x1e, + sli_bt_system_get_version_response_id = 0x1b, + sli_bt_system_reset_response_id = 0x01, + sli_bt_system_halt_response_id = 0x0c, + sli_bt_system_linklayer_configure_response_id = 0x0e, + sli_bt_system_set_tx_power_response_id = 0x17, + sli_bt_system_get_tx_power_setting_response_id = 0x18, + sli_bt_system_set_identity_address_response_id = 0x13, + sli_bt_system_get_identity_address_response_id = 0x15, + sli_bt_system_get_random_data_response_id = 0x0b, + sli_bt_system_data_buffer_write_response_id = 0x12, + sli_bt_system_data_buffer_clear_response_id = 0x14, + sli_bt_system_get_counters_response_id = 0x0f, + sli_bt_system_set_lazy_soft_timer_response_id = 0x1a, + sli_bt_resource_get_status_response_id = 0x00, + sli_bt_resource_set_report_threshold_response_id = 0x01, + sli_bt_resource_enable_connection_tx_report_response_id = 0x02, + sli_bt_resource_get_connection_tx_status_response_id = 0x03, + sli_bt_resource_disable_connection_tx_report_response_id = 0x04, + sli_bt_gap_set_privacy_mode_response_id = 0x01, + sli_bt_gap_set_data_channel_classification_response_id = 0x02, + sli_bt_gap_enable_whitelisting_response_id = 0x03, + sli_bt_gap_set_identity_address_response_id = 0x04, + sli_bt_advertiser_create_set_response_id = 0x01, + sli_bt_advertiser_configure_response_id = 0x12, + sli_bt_advertiser_set_timing_response_id = 0x03, + sli_bt_advertiser_set_channel_map_response_id = 0x04, + sli_bt_advertiser_set_tx_power_response_id = 0x0b, + sli_bt_advertiser_set_report_scan_request_response_id = 0x05, + sli_bt_advertiser_set_random_address_response_id = 0x10, + sli_bt_advertiser_clear_random_address_response_id = 0x11, + sli_bt_advertiser_stop_response_id = 0x0a, + sli_bt_advertiser_delete_set_response_id = 0x02, + sli_bt_advertiser_set_phy_response_id = 0x06, + sli_bt_advertiser_set_configuration_response_id = 0x07, + sli_bt_advertiser_clear_configuration_response_id = 0x08, + sli_bt_advertiser_set_data_response_id = 0x0f, + sli_bt_advertiser_set_long_data_response_id = 0x0e, + sli_bt_advertiser_start_response_id = 0x09, + sli_bt_advertiser_start_periodic_advertising_response_id = 0x0c, + sli_bt_advertiser_stop_periodic_advertising_response_id = 0x0d, + sli_bt_legacy_advertiser_set_data_response_id = 0x00, + sli_bt_legacy_advertiser_generate_data_response_id = 0x01, + sli_bt_legacy_advertiser_start_response_id = 0x02, + sli_bt_legacy_advertiser_start_directed_response_id = 0x03, + sli_bt_extended_advertiser_set_phy_response_id = 0x00, + sli_bt_extended_advertiser_set_data_response_id = 0x01, + sli_bt_extended_advertiser_set_long_data_response_id = 0x02, + sli_bt_extended_advertiser_generate_data_response_id = 0x03, + sli_bt_extended_advertiser_start_response_id = 0x04, + sli_bt_extended_advertiser_start_directed_response_id = 0x05, + sli_bt_periodic_advertiser_set_data_response_id = 0x00, + sli_bt_periodic_advertiser_set_long_data_response_id = 0x01, + sli_bt_periodic_advertiser_start_response_id = 0x02, + sli_bt_periodic_advertiser_stop_response_id = 0x03, + sli_bt_scanner_set_parameters_response_id = 0x06, + sli_bt_scanner_set_parameters_and_filter_response_id = 0x07, + sli_bt_scanner_stop_response_id = 0x05, + sli_bt_scanner_set_timing_response_id = 0x01, + sli_bt_scanner_set_mode_response_id = 0x02, + sli_bt_scanner_start_response_id = 0x03, + sli_bt_sync_set_parameters_response_id = 0x02, + sli_bt_sync_open_response_id = 0x00, + sli_bt_sync_set_reporting_mode_response_id = 0x03, + sli_bt_sync_update_sync_parameters_response_id = 0x04, + sli_bt_sync_close_response_id = 0x01, + sli_bt_sync_scanner_set_sync_parameters_response_id = 0x00, + sli_bt_sync_scanner_open_response_id = 0x01, + sli_bt_past_receiver_set_default_sync_receive_parameters_response_id = 0x00, + sli_bt_past_receiver_set_sync_receive_parameters_response_id = 0x01, + sli_bt_advertiser_past_transfer_response_id = 0x00, + sli_bt_sync_past_transfer_response_id = 0x00, + sli_bt_pawr_sync_set_sync_subevents_response_id = 0x02, + sli_bt_pawr_sync_set_response_data_response_id = 0x03, + sli_bt_pawr_advertiser_start_response_id = 0x00, + sli_bt_pawr_advertiser_set_subevent_data_response_id = 0x01, + sli_bt_pawr_advertiser_create_connection_response_id = 0x02, + sli_bt_pawr_advertiser_stop_response_id = 0x03, + sli_bt_connection_set_default_parameters_response_id = 0x00, + sli_bt_connection_set_default_preferred_phy_response_id = 0x01, + sli_bt_connection_set_default_data_length_response_id = 0x10, + sli_bt_connection_open_response_id = 0x04, + sli_bt_connection_set_parameters_response_id = 0x06, + sli_bt_connection_set_preferred_phy_response_id = 0x08, + sli_bt_connection_disable_slave_latency_response_id = 0x03, + sli_bt_connection_get_median_rssi_response_id = 0x15, + sli_bt_connection_read_channel_map_response_id = 0x07, + sli_bt_connection_set_power_reporting_response_id = 0x09, + sli_bt_connection_set_remote_power_reporting_response_id = 0x0a, + sli_bt_connection_get_tx_power_response_id = 0x0b, + sli_bt_connection_get_remote_tx_power_response_id = 0x0c, + sli_bt_connection_set_tx_power_response_id = 0x12, + sli_bt_connection_read_remote_used_features_response_id = 0x0d, + sli_bt_connection_get_security_status_response_id = 0x0e, + sli_bt_connection_set_data_length_response_id = 0x11, + sli_bt_connection_read_statistics_response_id = 0x13, + sli_bt_connection_get_scheduling_details_response_id = 0x14, + sli_bt_connection_close_response_id = 0x05, + sli_bt_connection_forcefully_close_response_id = 0x0f, + sli_bt_connection_get_rssi_response_id = 0x02, + sli_bt_gatt_set_max_mtu_response_id = 0x00, + sli_bt_gatt_discover_primary_services_response_id = 0x01, + sli_bt_gatt_discover_primary_services_by_uuid_response_id = 0x02, + sli_bt_gatt_find_included_services_response_id = 0x10, + sli_bt_gatt_discover_characteristics_response_id = 0x03, + sli_bt_gatt_discover_characteristics_by_uuid_response_id = 0x04, + sli_bt_gatt_discover_descriptors_response_id = 0x06, + sli_bt_gatt_discover_characteristic_descriptors_response_id = 0x14, + sli_bt_gatt_set_characteristic_notification_response_id = 0x05, + sli_bt_gatt_send_characteristic_confirmation_response_id = 0x0d, + sli_bt_gatt_read_characteristic_value_response_id = 0x07, + sli_bt_gatt_read_characteristic_value_from_offset_response_id = 0x12, + sli_bt_gatt_read_multiple_characteristic_values_response_id = 0x11, + sli_bt_gatt_read_characteristic_value_by_uuid_response_id = 0x08, + sli_bt_gatt_write_characteristic_value_response_id = 0x09, + sli_bt_gatt_write_characteristic_value_without_response_response_id = 0x0a, + sli_bt_gatt_prepare_characteristic_value_write_response_id = 0x0b, + sli_bt_gatt_prepare_characteristic_value_reliable_write_response_id = 0x13, + sli_bt_gatt_execute_characteristic_value_write_response_id = 0x0c, + sli_bt_gatt_read_descriptor_value_response_id = 0x0e, + sli_bt_gatt_write_descriptor_value_response_id = 0x0f, + sli_bt_gattdb_new_session_response_id = 0x00, + sli_bt_gattdb_add_service_response_id = 0x01, + sli_bt_gattdb_remove_service_response_id = 0x02, + sli_bt_gattdb_add_included_service_response_id = 0x03, + sli_bt_gattdb_remove_included_service_response_id = 0x04, + sli_bt_gattdb_add_uuid16_characteristic_response_id = 0x05, + sli_bt_gattdb_add_uuid128_characteristic_response_id = 0x06, + sli_bt_gattdb_remove_characteristic_response_id = 0x07, + sli_bt_gattdb_add_uuid16_descriptor_response_id = 0x08, + sli_bt_gattdb_add_uuid128_descriptor_response_id = 0x09, + sli_bt_gattdb_remove_descriptor_response_id = 0x0a, + sli_bt_gattdb_start_service_response_id = 0x0b, + sli_bt_gattdb_stop_service_response_id = 0x0c, + sli_bt_gattdb_start_characteristic_response_id = 0x0d, + sli_bt_gattdb_stop_characteristic_response_id = 0x0e, + sli_bt_gattdb_commit_response_id = 0x0f, + sli_bt_gattdb_abort_response_id = 0x10, + sli_bt_gatt_server_set_max_mtu_response_id = 0x0a, + sli_bt_gatt_server_get_mtu_response_id = 0x0b, + sli_bt_gatt_server_find_attribute_response_id = 0x06, + sli_bt_gatt_server_read_attribute_value_response_id = 0x00, + sli_bt_gatt_server_read_attribute_type_response_id = 0x01, + sli_bt_gatt_server_write_attribute_value_response_id = 0x02, + sli_bt_gatt_server_send_user_read_response_response_id = 0x03, + sli_bt_gatt_server_send_user_write_response_response_id = 0x04, + sli_bt_gatt_server_send_notification_response_id = 0x0f, + sli_bt_gatt_server_send_indication_response_id = 0x10, + sli_bt_gatt_server_notify_all_response_id = 0x11, + sli_bt_gatt_server_read_client_configuration_response_id = 0x12, + sli_bt_gatt_server_send_user_prepare_write_response_response_id = 0x14, + sli_bt_gatt_server_set_capabilities_response_id = 0x08, + sli_bt_gatt_server_enable_capabilities_response_id = 0x0c, + sli_bt_gatt_server_disable_capabilities_response_id = 0x0d, + sli_bt_gatt_server_get_enabled_capabilities_response_id = 0x0e, + sli_bt_gatt_server_read_client_supported_features_response_id = 0x15, + sli_bt_nvm_save_response_id = 0x02, + sli_bt_nvm_load_response_id = 0x03, + sli_bt_nvm_erase_response_id = 0x04, + sli_bt_nvm_erase_all_response_id = 0x01, + sli_bt_test_dtm_tx_v4_response_id = 0x03, + sli_bt_test_dtm_tx_cw_response_id = 0x04, + sli_bt_test_dtm_rx_response_id = 0x01, + sli_bt_test_dtm_end_response_id = 0x02, + sli_bt_sm_configure_response_id = 0x01, + sli_bt_sm_set_minimum_key_size_response_id = 0x14, + sli_bt_sm_set_debug_mode_response_id = 0x0f, + sli_bt_sm_add_to_whitelist_response_id = 0x13, + sli_bt_sm_store_bonding_configuration_response_id = 0x02, + sli_bt_sm_set_bondable_mode_response_id = 0x00, + sli_bt_sm_set_passkey_response_id = 0x10, + sli_bt_sm_increase_security_response_id = 0x04, + sli_bt_sm_enter_passkey_response_id = 0x08, + sli_bt_sm_passkey_confirm_response_id = 0x09, + sli_bt_sm_bonding_confirm_response_id = 0x0e, + sli_bt_sm_delete_bonding_response_id = 0x06, + sli_bt_sm_delete_bondings_response_id = 0x07, + sli_bt_sm_get_bonding_handles_response_id = 0x15, + sli_bt_sm_get_bonding_details_response_id = 0x16, + sli_bt_sm_find_bonding_by_address_response_id = 0x17, + sli_bt_sm_resolve_rpa_response_id = 0x1d, + sli_bt_sm_set_bonding_key_response_id = 0x18, + sli_bt_sm_set_legacy_oob_response_id = 0x19, + sli_bt_sm_set_oob_response_id = 0x1a, + sli_bt_sm_set_remote_oob_response_id = 0x1b, + sli_bt_sm_set_bonding_data_response_id = 0x1c, + sli_bt_external_bondingdb_set_data_response_id = 0x00, + sli_bt_resolving_list_add_device_by_bonding_response_id = 0x00, + sli_bt_resolving_list_add_device_by_address_response_id = 0x01, + sli_bt_resolving_list_remove_device_by_bonding_response_id = 0x02, + sli_bt_resolving_list_remove_device_by_address_response_id = 0x03, + sli_bt_resolving_list_remove_all_devices_response_id = 0x04, + sli_bt_accept_list_add_device_by_bonding_response_id = 0x00, + sli_bt_accept_list_add_device_by_address_response_id = 0x01, + sli_bt_accept_list_remove_device_by_bonding_response_id = 0x02, + sli_bt_accept_list_remove_device_by_address_response_id = 0x03, + sli_bt_accept_list_remove_all_devices_response_id = 0x04, + sli_bt_ota_set_device_name_response_id = 0x01, + sli_bt_ota_set_advertising_data_response_id = 0x02, + sli_bt_ota_set_configuration_response_id = 0x03, + sli_bt_ota_set_rf_path_response_id = 0x04, + sli_bt_coex_set_options_response_id = 0x00, + sli_bt_coex_set_parameters_response_id = 0x02, + sli_bt_coex_set_directional_priority_pulse_response_id = 0x03, + sli_bt_coex_get_parameters_response_id = 0x04, + sli_bt_coex_get_counters_response_id = 0x01, + sli_bt_cs_security_enable_response_id = 0x00, + sli_bt_cs_set_default_settings_response_id = 0x01, + sli_bt_cs_create_config_response_id = 0x02, + sli_bt_cs_remove_config_response_id = 0x03, + sli_bt_cs_set_channel_classification_response_id = 0x04, + sli_bt_cs_set_procedure_parameters_response_id = 0x05, + sli_bt_cs_procedure_enable_response_id = 0x06, + sli_bt_cs_set_antenna_configuration_response_id = 0x07, + sli_bt_cs_read_local_supported_capabilities_response_id = 0x08, + sli_bt_cs_test_start_response_id = 0x00, + sli_bt_l2cap_open_le_channel_response_id = 0x01, + sli_bt_l2cap_send_le_channel_open_response_response_id = 0x02, + sli_bt_l2cap_channel_send_data_response_id = 0x03, + sli_bt_l2cap_channel_send_credit_response_id = 0x04, + sli_bt_l2cap_close_channel_response_id = 0x05, + sli_bt_cte_transmitter_set_dtm_parameters_response_id = 0x04, + sli_bt_cte_transmitter_clear_dtm_parameters_response_id = 0x05, + sli_bt_cte_transmitter_enable_connection_cte_response_id = 0x00, + sli_bt_cte_transmitter_disable_connection_cte_response_id = 0x01, + sli_bt_cte_transmitter_enable_connectionless_cte_response_id = 0x02, + sli_bt_cte_transmitter_disable_connectionless_cte_response_id = 0x03, + sli_bt_cte_transmitter_enable_silabs_cte_response_id = 0x06, + sli_bt_cte_transmitter_disable_silabs_cte_response_id = 0x07, + sli_bt_cte_receiver_set_dtm_parameters_response_id = 0x05, + sli_bt_cte_receiver_clear_dtm_parameters_response_id = 0x06, + sli_bt_cte_receiver_set_sync_cte_type_response_id = 0x09, + sli_bt_cte_receiver_set_default_sync_receive_parameters_response_id = 0x0a, + sli_bt_cte_receiver_set_sync_receive_parameters_response_id = 0x0b, + sli_bt_cte_receiver_configure_response_id = 0x00, + sli_bt_cte_receiver_enable_connection_cte_response_id = 0x01, + sli_bt_cte_receiver_disable_connection_cte_response_id = 0x02, + sli_bt_cte_receiver_enable_connectionless_cte_response_id = 0x03, + sli_bt_cte_receiver_disable_connectionless_cte_response_id = 0x04, + sli_bt_cte_receiver_enable_silabs_cte_response_id = 0x07, + sli_bt_cte_receiver_disable_silabs_cte_response_id = 0x08, + sli_bt_connection_analyzer_start_response_id = 0x00, + sli_bt_connection_analyzer_stop_response_id = 0x01, + sli_bt_user_message_to_target_response_id = 0x00, + sli_bt_user_manage_event_filter_response_id = 0x01, + sli_bt_user_reset_to_dfu_response_id = 0x02, +}; + +enum sli_bt_event_id +{ + sli_bt_dfu_boot_event_id = 0x00, + sli_bt_dfu_boot_failure_event_id = 0x01, + sli_bt_system_boot_event_id = 0x00, + sli_bt_system_stopped_event_id = 0x01, + sli_bt_system_error_event_id = 0x06, + sli_bt_system_hardware_error_event_id = 0x05, + sli_bt_system_resource_exhausted_event_id = 0x08, + sli_bt_system_external_signal_event_id = 0x03, + sli_bt_system_awake_event_id = 0x04, + sli_bt_system_soft_timer_event_id = 0x07, + sli_bt_resource_status_event_id = 0x00, + sli_bt_advertiser_timeout_event_id = 0x01, + sli_bt_advertiser_scan_request_event_id = 0x02, + sli_bt_periodic_advertiser_status_event_id = 0x00, + sli_bt_scanner_legacy_advertisement_report_event_id = 0x00, + sli_bt_scanner_extended_advertisement_report_event_id = 0x02, + sli_bt_scanner_scan_report_event_id = 0x01, + sli_bt_sync_opened_event_id = 0x00, + sli_bt_sync_transfer_received_event_id = 0x03, + sli_bt_sync_data_event_id = 0x02, + sli_bt_sync_closed_event_id = 0x01, + sli_bt_periodic_sync_opened_event_id = 0x00, + sli_bt_periodic_sync_transfer_received_event_id = 0x01, + sli_bt_periodic_sync_report_event_id = 0x02, + sli_bt_pawr_sync_opened_event_id = 0x00, + sli_bt_pawr_sync_transfer_received_event_id = 0x01, + sli_bt_pawr_sync_subevent_report_event_id = 0x02, + sli_bt_pawr_advertiser_subevent_data_request_event_id = 0x00, + sli_bt_pawr_advertiser_subevent_tx_failed_event_id = 0x02, + sli_bt_pawr_advertiser_response_report_event_id = 0x01, + sli_bt_connection_opened_event_id = 0x00, + sli_bt_connection_parameters_event_id = 0x02, + sli_bt_connection_set_parameters_failed_event_id = 0x10, + sli_bt_connection_phy_status_event_id = 0x04, + sli_bt_connection_get_remote_tx_power_completed_event_id = 0x05, + sli_bt_connection_tx_power_event_id = 0x06, + sli_bt_connection_remote_tx_power_event_id = 0x07, + sli_bt_connection_remote_used_features_event_id = 0x08, + sli_bt_connection_data_length_event_id = 0x09, + sli_bt_connection_statistics_event_id = 0x0a, + sli_bt_connection_closed_event_id = 0x01, + sli_bt_connection_rssi_event_id = 0x03, + sli_bt_gatt_mtu_exchanged_event_id = 0x00, + sli_bt_gatt_service_event_id = 0x01, + sli_bt_gatt_characteristic_event_id = 0x02, + sli_bt_gatt_descriptor_event_id = 0x03, + sli_bt_gatt_characteristic_value_event_id = 0x04, + sli_bt_gatt_descriptor_value_event_id = 0x05, + sli_bt_gatt_procedure_completed_event_id = 0x06, + sli_bt_gatt_server_attribute_value_event_id = 0x00, + sli_bt_gatt_server_user_read_request_event_id = 0x01, + sli_bt_gatt_server_user_write_request_event_id = 0x02, + sli_bt_gatt_server_characteristic_status_event_id = 0x03, + sli_bt_gatt_server_execute_write_completed_event_id = 0x04, + sli_bt_gatt_server_indication_timeout_event_id = 0x05, + sli_bt_gatt_server_notification_tx_completed_event_id = 0x06, + sli_bt_test_dtm_completed_event_id = 0x00, + sli_bt_sm_passkey_display_event_id = 0x00, + sli_bt_sm_passkey_request_event_id = 0x01, + sli_bt_sm_confirm_passkey_event_id = 0x02, + sli_bt_sm_bonded_event_id = 0x03, + sli_bt_sm_bonding_failed_event_id = 0x04, + sli_bt_sm_confirm_bonding_event_id = 0x09, + sli_bt_external_bondingdb_data_request_event_id = 0x00, + sli_bt_external_bondingdb_data_event_id = 0x01, + sli_bt_external_bondingdb_data_ready_event_id = 0x02, + sli_bt_cs_security_enable_complete_event_id = 0x00, + sli_bt_cs_config_complete_event_id = 0x01, + sli_bt_cs_procedure_enable_complete_event_id = 0x02, + sli_bt_cs_result_event_id = 0x03, + sli_bt_l2cap_le_channel_open_request_event_id = 0x01, + sli_bt_l2cap_le_channel_open_response_event_id = 0x02, + sli_bt_l2cap_channel_data_event_id = 0x03, + sli_bt_l2cap_channel_credit_event_id = 0x04, + sli_bt_l2cap_channel_closed_event_id = 0x05, + sli_bt_l2cap_command_rejected_event_id = 0x06, + sli_bt_cte_receiver_dtm_iq_report_event_id = 0x02, + sli_bt_cte_receiver_connection_iq_report_event_id = 0x00, + sli_bt_cte_receiver_connectionless_iq_report_event_id = 0x01, + sli_bt_cte_receiver_silabs_iq_report_event_id = 0x03, + sli_bt_connection_analyzer_report_event_id = 0x00, + sli_bt_connection_analyzer_completed_event_id = 0x01, + sli_bt_user_message_to_host_event_id = 0x00, +}; + +PACKSTRUCT( struct sl_bt_rsp_error_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_error_s sl_bt_rsp_error_t; + +PACKSTRUCT( struct sl_bt_cmd_dfu_flash_set_address_s +{ + uint32_t address; +}); + +typedef struct sl_bt_cmd_dfu_flash_set_address_s sl_bt_cmd_dfu_flash_set_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_dfu_flash_upload_s +{ + uint8array data; +}); + +typedef struct sl_bt_cmd_dfu_flash_upload_s sl_bt_cmd_dfu_flash_upload_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_reset_s +{ + uint8_t dfu; +}); + +typedef struct sl_bt_cmd_system_reset_s sl_bt_cmd_system_reset_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_halt_s +{ + uint8_t halt; +}); + +typedef struct sl_bt_cmd_system_halt_s sl_bt_cmd_system_halt_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_linklayer_configure_s +{ + uint8_t key; + uint8array data; +}); + +typedef struct sl_bt_cmd_system_linklayer_configure_s sl_bt_cmd_system_linklayer_configure_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_set_tx_power_s +{ + int16_t min_power; + int16_t max_power; +}); + +typedef struct sl_bt_cmd_system_set_tx_power_s sl_bt_cmd_system_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_set_identity_address_s +{ + bd_addr address; + uint8_t type; +}); + +typedef struct sl_bt_cmd_system_set_identity_address_s sl_bt_cmd_system_set_identity_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_get_random_data_s +{ + uint8_t length; +}); + +typedef struct sl_bt_cmd_system_get_random_data_s sl_bt_cmd_system_get_random_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_data_buffer_write_s +{ + uint8array data; +}); + +typedef struct sl_bt_cmd_system_data_buffer_write_s sl_bt_cmd_system_data_buffer_write_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_get_counters_s +{ + uint8_t reset; +}); + +typedef struct sl_bt_cmd_system_get_counters_s sl_bt_cmd_system_get_counters_t; + + +PACKSTRUCT( struct sl_bt_cmd_system_set_lazy_soft_timer_s +{ + uint32_t time; + uint32_t slack; + uint8_t handle; + uint8_t single_shot; +}); + +typedef struct sl_bt_cmd_system_set_lazy_soft_timer_s sl_bt_cmd_system_set_lazy_soft_timer_t; + + +PACKSTRUCT( struct sl_bt_cmd_resource_set_report_threshold_s +{ + uint32_t low; + uint32_t high; +}); + +typedef struct sl_bt_cmd_resource_set_report_threshold_s sl_bt_cmd_resource_set_report_threshold_t; + + +PACKSTRUCT( struct sl_bt_cmd_resource_enable_connection_tx_report_s +{ + uint16_t packet_count; +}); + +typedef struct sl_bt_cmd_resource_enable_connection_tx_report_s sl_bt_cmd_resource_enable_connection_tx_report_t; + + +PACKSTRUCT( struct sl_bt_cmd_resource_get_connection_tx_status_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_resource_get_connection_tx_status_s sl_bt_cmd_resource_get_connection_tx_status_t; + + +PACKSTRUCT( struct sl_bt_cmd_gap_set_privacy_mode_s +{ + uint8_t privacy; + uint8_t interval; +}); + +typedef struct sl_bt_cmd_gap_set_privacy_mode_s sl_bt_cmd_gap_set_privacy_mode_t; + + +PACKSTRUCT( struct sl_bt_cmd_gap_set_data_channel_classification_s +{ + uint8array channel_map; +}); + +typedef struct sl_bt_cmd_gap_set_data_channel_classification_s sl_bt_cmd_gap_set_data_channel_classification_t; + + +PACKSTRUCT( struct sl_bt_cmd_gap_enable_whitelisting_s +{ + uint8_t enable; +}); + +typedef struct sl_bt_cmd_gap_enable_whitelisting_s sl_bt_cmd_gap_enable_whitelisting_t; + + +PACKSTRUCT( struct sl_bt_cmd_gap_set_identity_address_s +{ + bd_addr address; + uint8_t addr_type; +}); + +typedef struct sl_bt_cmd_gap_set_identity_address_s sl_bt_cmd_gap_set_identity_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_configure_s +{ + uint8_t advertising_set; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_advertiser_configure_s sl_bt_cmd_advertiser_configure_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_timing_s +{ + uint8_t advertising_set; + uint32_t interval_min; + uint32_t interval_max; + uint16_t duration; + uint8_t maxevents; +}); + +typedef struct sl_bt_cmd_advertiser_set_timing_s sl_bt_cmd_advertiser_set_timing_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_channel_map_s +{ + uint8_t advertising_set; + uint8_t channel_map; +}); + +typedef struct sl_bt_cmd_advertiser_set_channel_map_s sl_bt_cmd_advertiser_set_channel_map_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_tx_power_s +{ + uint8_t advertising_set; + int16_t power; +}); + +typedef struct sl_bt_cmd_advertiser_set_tx_power_s sl_bt_cmd_advertiser_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_report_scan_request_s +{ + uint8_t advertising_set; + uint8_t report_scan_req; +}); + +typedef struct sl_bt_cmd_advertiser_set_report_scan_request_s sl_bt_cmd_advertiser_set_report_scan_request_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_random_address_s +{ + uint8_t advertising_set; + uint8_t addr_type; + bd_addr address; +}); + +typedef struct sl_bt_cmd_advertiser_set_random_address_s sl_bt_cmd_advertiser_set_random_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_clear_random_address_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_advertiser_clear_random_address_s sl_bt_cmd_advertiser_clear_random_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_stop_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_advertiser_stop_s sl_bt_cmd_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_delete_set_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_advertiser_delete_set_s sl_bt_cmd_advertiser_delete_set_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_phy_s +{ + uint8_t advertising_set; + uint8_t primary_phy; + uint8_t secondary_phy; +}); + +typedef struct sl_bt_cmd_advertiser_set_phy_s sl_bt_cmd_advertiser_set_phy_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_configuration_s +{ + uint8_t advertising_set; + uint32_t configurations; +}); + +typedef struct sl_bt_cmd_advertiser_set_configuration_s sl_bt_cmd_advertiser_set_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_clear_configuration_s +{ + uint8_t advertising_set; + uint32_t configurations; +}); + +typedef struct sl_bt_cmd_advertiser_clear_configuration_s sl_bt_cmd_advertiser_clear_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_data_s +{ + uint8_t advertising_set; + uint8_t packet_type; + uint8array adv_data; +}); + +typedef struct sl_bt_cmd_advertiser_set_data_s sl_bt_cmd_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_set_long_data_s +{ + uint8_t advertising_set; + uint8_t packet_type; +}); + +typedef struct sl_bt_cmd_advertiser_set_long_data_s sl_bt_cmd_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_start_s +{ + uint8_t advertising_set; + uint8_t discover; + uint8_t connect; +}); + +typedef struct sl_bt_cmd_advertiser_start_s sl_bt_cmd_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_start_periodic_advertising_s +{ + uint8_t advertising_set; + uint16_t interval_min; + uint16_t interval_max; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_advertiser_start_periodic_advertising_s sl_bt_cmd_advertiser_start_periodic_advertising_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_stop_periodic_advertising_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_advertiser_stop_periodic_advertising_s sl_bt_cmd_advertiser_stop_periodic_advertising_t; + + +PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_set_data_s +{ + uint8_t advertising_set; + uint8_t type; + uint8array data; +}); + +typedef struct sl_bt_cmd_legacy_advertiser_set_data_s sl_bt_cmd_legacy_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_generate_data_s +{ + uint8_t advertising_set; + uint8_t discover; +}); + +typedef struct sl_bt_cmd_legacy_advertiser_generate_data_s sl_bt_cmd_legacy_advertiser_generate_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_start_s +{ + uint8_t advertising_set; + uint8_t connect; +}); + +typedef struct sl_bt_cmd_legacy_advertiser_start_s sl_bt_cmd_legacy_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_legacy_advertiser_start_directed_s +{ + uint8_t advertising_set; + uint8_t connect; + bd_addr peer_addr; + uint8_t peer_addr_type; +}); + +typedef struct sl_bt_cmd_legacy_advertiser_start_directed_s sl_bt_cmd_legacy_advertiser_start_directed_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_phy_s +{ + uint8_t advertising_set; + uint8_t primary_phy; + uint8_t secondary_phy; +}); + +typedef struct sl_bt_cmd_extended_advertiser_set_phy_s sl_bt_cmd_extended_advertiser_set_phy_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_data_s +{ + uint8_t advertising_set; + uint8array data; +}); + +typedef struct sl_bt_cmd_extended_advertiser_set_data_s sl_bt_cmd_extended_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_set_long_data_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_extended_advertiser_set_long_data_s sl_bt_cmd_extended_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_generate_data_s +{ + uint8_t advertising_set; + uint8_t discover; +}); + +typedef struct sl_bt_cmd_extended_advertiser_generate_data_s sl_bt_cmd_extended_advertiser_generate_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_start_s +{ + uint8_t advertising_set; + uint8_t connect; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_extended_advertiser_start_s sl_bt_cmd_extended_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_extended_advertiser_start_directed_s +{ + uint8_t advertising_set; + uint8_t connect; + uint32_t flags; + bd_addr peer_addr; + uint8_t peer_addr_type; +}); + +typedef struct sl_bt_cmd_extended_advertiser_start_directed_s sl_bt_cmd_extended_advertiser_start_directed_t; + + +PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_set_data_s +{ + uint8_t advertising_set; + uint8array data; +}); + +typedef struct sl_bt_cmd_periodic_advertiser_set_data_s sl_bt_cmd_periodic_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_set_long_data_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_periodic_advertiser_set_long_data_s sl_bt_cmd_periodic_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_start_s +{ + uint8_t advertising_set; + uint16_t interval_min; + uint16_t interval_max; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_periodic_advertiser_start_s sl_bt_cmd_periodic_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_periodic_advertiser_stop_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_periodic_advertiser_stop_s sl_bt_cmd_periodic_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_cmd_scanner_set_parameters_s +{ + uint8_t mode; + uint16_t interval; + uint16_t window; +}); + +typedef struct sl_bt_cmd_scanner_set_parameters_s sl_bt_cmd_scanner_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_scanner_set_parameters_and_filter_s +{ + uint8_t mode; + uint16_t interval; + uint16_t window; + uint32_t flags; + uint8_t filter_policy; +}); + +typedef struct sl_bt_cmd_scanner_set_parameters_and_filter_s sl_bt_cmd_scanner_set_parameters_and_filter_t; + + +PACKSTRUCT( struct sl_bt_cmd_scanner_set_timing_s +{ + uint8_t phys; + uint16_t scan_interval; + uint16_t scan_window; +}); + +typedef struct sl_bt_cmd_scanner_set_timing_s sl_bt_cmd_scanner_set_timing_t; + + +PACKSTRUCT( struct sl_bt_cmd_scanner_set_mode_s +{ + uint8_t phys; + uint8_t scan_mode; +}); + +typedef struct sl_bt_cmd_scanner_set_mode_s sl_bt_cmd_scanner_set_mode_t; + + +PACKSTRUCT( struct sl_bt_cmd_scanner_start_s +{ + uint8_t scanning_phy; + uint8_t discover_mode; +}); + +typedef struct sl_bt_cmd_scanner_start_s sl_bt_cmd_scanner_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_set_parameters_s +{ + uint16_t skip; + uint16_t timeout; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_sync_set_parameters_s sl_bt_cmd_sync_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_open_s +{ + bd_addr address; + uint8_t address_type; + uint8_t adv_sid; +}); + +typedef struct sl_bt_cmd_sync_open_s sl_bt_cmd_sync_open_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_set_reporting_mode_s +{ + uint16_t sync; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_sync_set_reporting_mode_s sl_bt_cmd_sync_set_reporting_mode_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_update_sync_parameters_s +{ + uint16_t sync; + uint16_t skip; + uint16_t timeout; +}); + +typedef struct sl_bt_cmd_sync_update_sync_parameters_s sl_bt_cmd_sync_update_sync_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_close_s +{ + uint16_t sync; +}); + +typedef struct sl_bt_cmd_sync_close_s sl_bt_cmd_sync_close_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_scanner_set_sync_parameters_s +{ + uint16_t skip; + uint16_t timeout; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_sync_scanner_set_sync_parameters_s sl_bt_cmd_sync_scanner_set_sync_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_scanner_open_s +{ + bd_addr address; + uint8_t address_type; + uint8_t adv_sid; +}); + +typedef struct sl_bt_cmd_sync_scanner_open_s sl_bt_cmd_sync_scanner_open_t; + + +PACKSTRUCT( struct sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_s +{ + uint8_t mode; + uint16_t skip; + uint16_t timeout; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_s sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_past_receiver_set_sync_receive_parameters_s +{ + uint8_t connection; + uint8_t mode; + uint16_t skip; + uint16_t timeout; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_past_receiver_set_sync_receive_parameters_s sl_bt_cmd_past_receiver_set_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_advertiser_past_transfer_s +{ + uint8_t connection; + uint16_t service_data; + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_advertiser_past_transfer_s sl_bt_cmd_advertiser_past_transfer_t; + + +PACKSTRUCT( struct sl_bt_cmd_sync_past_transfer_s +{ + uint8_t connection; + uint16_t service_data; + uint16_t sync; +}); + +typedef struct sl_bt_cmd_sync_past_transfer_s sl_bt_cmd_sync_past_transfer_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_sync_set_sync_subevents_s +{ + uint16_t sync; + uint8array subevents; +}); + +typedef struct sl_bt_cmd_pawr_sync_set_sync_subevents_s sl_bt_cmd_pawr_sync_set_sync_subevents_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_sync_set_response_data_s +{ + uint16_t sync; + uint16_t request_event; + uint8_t request_subevent; + uint8_t response_subevent; + uint8_t response_slot; + uint8array response_data; +}); + +typedef struct sl_bt_cmd_pawr_sync_set_response_data_s sl_bt_cmd_pawr_sync_set_response_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_start_s +{ + uint8_t advertising_set; + uint16_t interval_min; + uint16_t interval_max; + uint32_t flags; + uint8_t num_subevents; + uint8_t subevent_interval; + uint8_t response_slot_delay; + uint8_t response_slot_spacing; + uint8_t response_slots; +}); + +typedef struct sl_bt_cmd_pawr_advertiser_start_s sl_bt_cmd_pawr_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_set_subevent_data_s +{ + uint8_t advertising_set; + uint8_t subevent; + uint8_t response_slot_start; + uint8_t response_slot_count; + uint8array adv_data; +}); + +typedef struct sl_bt_cmd_pawr_advertiser_set_subevent_data_s sl_bt_cmd_pawr_advertiser_set_subevent_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_create_connection_s +{ + uint8_t advertising_set; + uint8_t subevent; + bd_addr address; + uint8_t address_type; +}); + +typedef struct sl_bt_cmd_pawr_advertiser_create_connection_s sl_bt_cmd_pawr_advertiser_create_connection_t; + + +PACKSTRUCT( struct sl_bt_cmd_pawr_advertiser_stop_s +{ + uint8_t advertising_set; +}); + +typedef struct sl_bt_cmd_pawr_advertiser_stop_s sl_bt_cmd_pawr_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_default_parameters_s +{ + uint16_t min_interval; + uint16_t max_interval; + uint16_t latency; + uint16_t timeout; + uint16_t min_ce_length; + uint16_t max_ce_length; +}); + +typedef struct sl_bt_cmd_connection_set_default_parameters_s sl_bt_cmd_connection_set_default_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_default_preferred_phy_s +{ + uint8_t preferred_phy; + uint8_t accepted_phy; +}); + +typedef struct sl_bt_cmd_connection_set_default_preferred_phy_s sl_bt_cmd_connection_set_default_preferred_phy_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_default_data_length_s +{ + uint16_t tx_data_len; +}); + +typedef struct sl_bt_cmd_connection_set_default_data_length_s sl_bt_cmd_connection_set_default_data_length_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_open_s +{ + bd_addr address; + uint8_t address_type; + uint8_t initiating_phy; +}); + +typedef struct sl_bt_cmd_connection_open_s sl_bt_cmd_connection_open_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_parameters_s +{ + uint8_t connection; + uint16_t min_interval; + uint16_t max_interval; + uint16_t latency; + uint16_t timeout; + uint16_t min_ce_length; + uint16_t max_ce_length; +}); + +typedef struct sl_bt_cmd_connection_set_parameters_s sl_bt_cmd_connection_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_preferred_phy_s +{ + uint8_t connection; + uint8_t preferred_phy; + uint8_t accepted_phy; +}); + +typedef struct sl_bt_cmd_connection_set_preferred_phy_s sl_bt_cmd_connection_set_preferred_phy_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_disable_slave_latency_s +{ + uint8_t connection; + uint8_t disable; +}); + +typedef struct sl_bt_cmd_connection_disable_slave_latency_s sl_bt_cmd_connection_disable_slave_latency_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_median_rssi_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_get_median_rssi_s sl_bt_cmd_connection_get_median_rssi_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_read_channel_map_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_read_channel_map_s sl_bt_cmd_connection_read_channel_map_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_power_reporting_s +{ + uint8_t connection; + uint8_t mode; +}); + +typedef struct sl_bt_cmd_connection_set_power_reporting_s sl_bt_cmd_connection_set_power_reporting_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_remote_power_reporting_s +{ + uint8_t connection; + uint8_t mode; +}); + +typedef struct sl_bt_cmd_connection_set_remote_power_reporting_s sl_bt_cmd_connection_set_remote_power_reporting_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_tx_power_s +{ + uint8_t connection; + uint8_t phy; +}); + +typedef struct sl_bt_cmd_connection_get_tx_power_s sl_bt_cmd_connection_get_tx_power_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_remote_tx_power_s +{ + uint8_t connection; + uint8_t phy; +}); + +typedef struct sl_bt_cmd_connection_get_remote_tx_power_s sl_bt_cmd_connection_get_remote_tx_power_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_tx_power_s +{ + uint8_t connection; + int16_t tx_power; +}); + +typedef struct sl_bt_cmd_connection_set_tx_power_s sl_bt_cmd_connection_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_read_remote_used_features_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_read_remote_used_features_s sl_bt_cmd_connection_read_remote_used_features_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_security_status_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_get_security_status_s sl_bt_cmd_connection_get_security_status_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_set_data_length_s +{ + uint8_t connection; + uint16_t tx_data_len; + uint16_t tx_time_us; +}); + +typedef struct sl_bt_cmd_connection_set_data_length_s sl_bt_cmd_connection_set_data_length_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_read_statistics_s +{ + uint8_t connection; + uint8_t reset; +}); + +typedef struct sl_bt_cmd_connection_read_statistics_s sl_bt_cmd_connection_read_statistics_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_scheduling_details_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_get_scheduling_details_s sl_bt_cmd_connection_get_scheduling_details_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_close_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_close_s sl_bt_cmd_connection_close_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_forcefully_close_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_forcefully_close_s sl_bt_cmd_connection_forcefully_close_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_get_rssi_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_connection_get_rssi_s sl_bt_cmd_connection_get_rssi_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_set_max_mtu_s +{ + uint16_t max_mtu; +}); + +typedef struct sl_bt_cmd_gatt_set_max_mtu_s sl_bt_cmd_gatt_set_max_mtu_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_primary_services_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_gatt_discover_primary_services_s sl_bt_cmd_gatt_discover_primary_services_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_primary_services_by_uuid_s +{ + uint8_t connection; + uint8array uuid; +}); + +typedef struct sl_bt_cmd_gatt_discover_primary_services_by_uuid_s sl_bt_cmd_gatt_discover_primary_services_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_find_included_services_s +{ + uint8_t connection; + uint32_t service; +}); + +typedef struct sl_bt_cmd_gatt_find_included_services_s sl_bt_cmd_gatt_find_included_services_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristics_s +{ + uint8_t connection; + uint32_t service; +}); + +typedef struct sl_bt_cmd_gatt_discover_characteristics_s sl_bt_cmd_gatt_discover_characteristics_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristics_by_uuid_s +{ + uint8_t connection; + uint32_t service; + uint8array uuid; +}); + +typedef struct sl_bt_cmd_gatt_discover_characteristics_by_uuid_s sl_bt_cmd_gatt_discover_characteristics_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_descriptors_s +{ + uint8_t connection; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gatt_discover_descriptors_s sl_bt_cmd_gatt_discover_descriptors_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_discover_characteristic_descriptors_s +{ + uint8_t connection; + uint16_t start; + uint16_t end; +}); + +typedef struct sl_bt_cmd_gatt_discover_characteristic_descriptors_s sl_bt_cmd_gatt_discover_characteristic_descriptors_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_set_characteristic_notification_s +{ + uint8_t connection; + uint16_t characteristic; + uint8_t flags; +}); + +typedef struct sl_bt_cmd_gatt_set_characteristic_notification_s sl_bt_cmd_gatt_set_characteristic_notification_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_send_characteristic_confirmation_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_gatt_send_characteristic_confirmation_s sl_bt_cmd_gatt_send_characteristic_confirmation_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_s +{ + uint8_t connection; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gatt_read_characteristic_value_s sl_bt_cmd_gatt_read_characteristic_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_from_offset_s +{ + uint8_t connection; + uint16_t characteristic; + uint16_t offset; + uint16_t maxlen; +}); + +typedef struct sl_bt_cmd_gatt_read_characteristic_value_from_offset_s sl_bt_cmd_gatt_read_characteristic_value_from_offset_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_read_multiple_characteristic_values_s +{ + uint8_t connection; + uint8array characteristic_list; +}); + +typedef struct sl_bt_cmd_gatt_read_multiple_characteristic_values_s sl_bt_cmd_gatt_read_multiple_characteristic_values_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_read_characteristic_value_by_uuid_s +{ + uint8_t connection; + uint32_t service; + uint8array uuid; +}); + +typedef struct sl_bt_cmd_gatt_read_characteristic_value_by_uuid_s sl_bt_cmd_gatt_read_characteristic_value_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_write_characteristic_value_s +{ + uint8_t connection; + uint16_t characteristic; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_write_characteristic_value_s sl_bt_cmd_gatt_write_characteristic_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_write_characteristic_value_without_response_s +{ + uint8_t connection; + uint16_t characteristic; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_write_characteristic_value_without_response_s sl_bt_cmd_gatt_write_characteristic_value_without_response_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_prepare_characteristic_value_write_s +{ + uint8_t connection; + uint16_t characteristic; + uint16_t offset; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_prepare_characteristic_value_write_s sl_bt_cmd_gatt_prepare_characteristic_value_write_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_s +{ + uint8_t connection; + uint16_t characteristic; + uint16_t offset; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_s sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_execute_characteristic_value_write_s +{ + uint8_t connection; + uint8_t flags; +}); + +typedef struct sl_bt_cmd_gatt_execute_characteristic_value_write_s sl_bt_cmd_gatt_execute_characteristic_value_write_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_read_descriptor_value_s +{ + uint8_t connection; + uint16_t descriptor; +}); + +typedef struct sl_bt_cmd_gatt_read_descriptor_value_s sl_bt_cmd_gatt_read_descriptor_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_write_descriptor_value_s +{ + uint8_t connection; + uint16_t descriptor; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_write_descriptor_value_s sl_bt_cmd_gatt_write_descriptor_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_service_s +{ + uint16_t session; + uint8_t type; + uint8_t property; + uint8array uuid; +}); + +typedef struct sl_bt_cmd_gattdb_add_service_s sl_bt_cmd_gattdb_add_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_service_s +{ + uint16_t session; + uint16_t service; +}); + +typedef struct sl_bt_cmd_gattdb_remove_service_s sl_bt_cmd_gattdb_remove_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_included_service_s +{ + uint16_t session; + uint16_t service; + uint16_t included_service; +}); + +typedef struct sl_bt_cmd_gattdb_add_included_service_s sl_bt_cmd_gattdb_add_included_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_included_service_s +{ + uint16_t session; + uint16_t attribute; +}); + +typedef struct sl_bt_cmd_gattdb_remove_included_service_s sl_bt_cmd_gattdb_remove_included_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid16_characteristic_s +{ + uint16_t session; + uint16_t service; + uint16_t property; + uint16_t security; + uint8_t flag; + sl_bt_uuid_16_t uuid; + uint8_t value_type; + uint16_t maxlen; + byte_array value; +}); + +typedef struct sl_bt_cmd_gattdb_add_uuid16_characteristic_s sl_bt_cmd_gattdb_add_uuid16_characteristic_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid128_characteristic_s +{ + uint16_t session; + uint16_t service; + uint16_t property; + uint16_t security; + uint8_t flag; + uuid_128 uuid; + uint8_t value_type; + uint16_t maxlen; + byte_array value; +}); + +typedef struct sl_bt_cmd_gattdb_add_uuid128_characteristic_s sl_bt_cmd_gattdb_add_uuid128_characteristic_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_characteristic_s +{ + uint16_t session; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gattdb_remove_characteristic_s sl_bt_cmd_gattdb_remove_characteristic_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid16_descriptor_s +{ + uint16_t session; + uint16_t characteristic; + uint16_t property; + uint16_t security; + sl_bt_uuid_16_t uuid; + uint8_t value_type; + uint16_t maxlen; + byte_array value; +}); + +typedef struct sl_bt_cmd_gattdb_add_uuid16_descriptor_s sl_bt_cmd_gattdb_add_uuid16_descriptor_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_add_uuid128_descriptor_s +{ + uint16_t session; + uint16_t characteristic; + uint16_t property; + uint16_t security; + uuid_128 uuid; + uint8_t value_type; + uint16_t maxlen; + byte_array value; +}); + +typedef struct sl_bt_cmd_gattdb_add_uuid128_descriptor_s sl_bt_cmd_gattdb_add_uuid128_descriptor_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_remove_descriptor_s +{ + uint16_t session; + uint16_t descriptor; +}); + +typedef struct sl_bt_cmd_gattdb_remove_descriptor_s sl_bt_cmd_gattdb_remove_descriptor_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_start_service_s +{ + uint16_t session; + uint16_t service; +}); + +typedef struct sl_bt_cmd_gattdb_start_service_s sl_bt_cmd_gattdb_start_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_stop_service_s +{ + uint16_t session; + uint16_t service; +}); + +typedef struct sl_bt_cmd_gattdb_stop_service_s sl_bt_cmd_gattdb_stop_service_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_start_characteristic_s +{ + uint16_t session; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gattdb_start_characteristic_s sl_bt_cmd_gattdb_start_characteristic_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_stop_characteristic_s +{ + uint16_t session; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gattdb_stop_characteristic_s sl_bt_cmd_gattdb_stop_characteristic_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_commit_s +{ + uint16_t session; +}); + +typedef struct sl_bt_cmd_gattdb_commit_s sl_bt_cmd_gattdb_commit_t; + + +PACKSTRUCT( struct sl_bt_cmd_gattdb_abort_s +{ + uint16_t session; +}); + +typedef struct sl_bt_cmd_gattdb_abort_s sl_bt_cmd_gattdb_abort_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_set_max_mtu_s +{ + uint16_t max_mtu; +}); + +typedef struct sl_bt_cmd_gatt_server_set_max_mtu_s sl_bt_cmd_gatt_server_set_max_mtu_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_get_mtu_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_gatt_server_get_mtu_s sl_bt_cmd_gatt_server_get_mtu_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_find_attribute_s +{ + uint16_t start; + uint8array type; +}); + +typedef struct sl_bt_cmd_gatt_server_find_attribute_s sl_bt_cmd_gatt_server_find_attribute_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_attribute_value_s +{ + uint16_t attribute; + uint16_t offset; +}); + +typedef struct sl_bt_cmd_gatt_server_read_attribute_value_s sl_bt_cmd_gatt_server_read_attribute_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_attribute_type_s +{ + uint16_t attribute; +}); + +typedef struct sl_bt_cmd_gatt_server_read_attribute_type_s sl_bt_cmd_gatt_server_read_attribute_type_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_write_attribute_value_s +{ + uint16_t attribute; + uint16_t offset; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_write_attribute_value_s sl_bt_cmd_gatt_server_write_attribute_value_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_read_response_s +{ + uint8_t connection; + uint16_t characteristic; + uint8_t att_errorcode; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_send_user_read_response_s sl_bt_cmd_gatt_server_send_user_read_response_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_write_response_s +{ + uint8_t connection; + uint16_t characteristic; + uint8_t att_errorcode; +}); + +typedef struct sl_bt_cmd_gatt_server_send_user_write_response_s sl_bt_cmd_gatt_server_send_user_write_response_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_notification_s +{ + uint8_t connection; + uint16_t characteristic; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_send_notification_s sl_bt_cmd_gatt_server_send_notification_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_indication_s +{ + uint8_t connection; + uint16_t characteristic; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_send_indication_s sl_bt_cmd_gatt_server_send_indication_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_notify_all_s +{ + uint16_t characteristic; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_notify_all_s sl_bt_cmd_gatt_server_notify_all_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_client_configuration_s +{ + uint8_t connection; + uint16_t characteristic; +}); + +typedef struct sl_bt_cmd_gatt_server_read_client_configuration_s sl_bt_cmd_gatt_server_read_client_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_send_user_prepare_write_response_s +{ + uint8_t connection; + uint16_t characteristic; + uint8_t att_errorcode; + uint16_t offset; + uint8array value; +}); + +typedef struct sl_bt_cmd_gatt_server_send_user_prepare_write_response_s sl_bt_cmd_gatt_server_send_user_prepare_write_response_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_set_capabilities_s +{ + uint32_t caps; + uint32_t reserved; +}); + +typedef struct sl_bt_cmd_gatt_server_set_capabilities_s sl_bt_cmd_gatt_server_set_capabilities_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_enable_capabilities_s +{ + uint32_t caps; +}); + +typedef struct sl_bt_cmd_gatt_server_enable_capabilities_s sl_bt_cmd_gatt_server_enable_capabilities_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_disable_capabilities_s +{ + uint32_t caps; +}); + +typedef struct sl_bt_cmd_gatt_server_disable_capabilities_s sl_bt_cmd_gatt_server_disable_capabilities_t; + + +PACKSTRUCT( struct sl_bt_cmd_gatt_server_read_client_supported_features_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_gatt_server_read_client_supported_features_s sl_bt_cmd_gatt_server_read_client_supported_features_t; + + +PACKSTRUCT( struct sl_bt_cmd_nvm_save_s +{ + uint16_t key; + uint8array value; +}); + +typedef struct sl_bt_cmd_nvm_save_s sl_bt_cmd_nvm_save_t; + + +PACKSTRUCT( struct sl_bt_cmd_nvm_load_s +{ + uint16_t key; +}); + +typedef struct sl_bt_cmd_nvm_load_s sl_bt_cmd_nvm_load_t; + + +PACKSTRUCT( struct sl_bt_cmd_nvm_erase_s +{ + uint16_t key; +}); + +typedef struct sl_bt_cmd_nvm_erase_s sl_bt_cmd_nvm_erase_t; + + +PACKSTRUCT( struct sl_bt_cmd_test_dtm_tx_v4_s +{ + uint8_t packet_type; + uint8_t length; + uint8_t channel; + uint8_t phy; + int8_t power_level; +}); + +typedef struct sl_bt_cmd_test_dtm_tx_v4_s sl_bt_cmd_test_dtm_tx_v4_t; + + +PACKSTRUCT( struct sl_bt_cmd_test_dtm_tx_cw_s +{ + uint8_t packet_type; + uint8_t channel; + uint8_t phy; + int16_t power_level; +}); + +typedef struct sl_bt_cmd_test_dtm_tx_cw_s sl_bt_cmd_test_dtm_tx_cw_t; + + +PACKSTRUCT( struct sl_bt_cmd_test_dtm_rx_s +{ + uint8_t channel; + uint8_t phy; +}); + +typedef struct sl_bt_cmd_test_dtm_rx_s sl_bt_cmd_test_dtm_rx_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_configure_s +{ + uint8_t flags; + uint8_t io_capabilities; +}); + +typedef struct sl_bt_cmd_sm_configure_s sl_bt_cmd_sm_configure_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_minimum_key_size_s +{ + uint8_t minimum_key_size; +}); + +typedef struct sl_bt_cmd_sm_set_minimum_key_size_s sl_bt_cmd_sm_set_minimum_key_size_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_add_to_whitelist_s +{ + bd_addr address; + uint8_t address_type; +}); + +typedef struct sl_bt_cmd_sm_add_to_whitelist_s sl_bt_cmd_sm_add_to_whitelist_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_store_bonding_configuration_s +{ + uint8_t max_bonding_count; + uint8_t policy_flags; +}); + +typedef struct sl_bt_cmd_sm_store_bonding_configuration_s sl_bt_cmd_sm_store_bonding_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_bondable_mode_s +{ + uint8_t bondable; +}); + +typedef struct sl_bt_cmd_sm_set_bondable_mode_s sl_bt_cmd_sm_set_bondable_mode_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_passkey_s +{ + int32_t passkey; +}); + +typedef struct sl_bt_cmd_sm_set_passkey_s sl_bt_cmd_sm_set_passkey_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_increase_security_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_sm_increase_security_s sl_bt_cmd_sm_increase_security_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_enter_passkey_s +{ + uint8_t connection; + int32_t passkey; +}); + +typedef struct sl_bt_cmd_sm_enter_passkey_s sl_bt_cmd_sm_enter_passkey_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_passkey_confirm_s +{ + uint8_t connection; + uint8_t confirm; +}); + +typedef struct sl_bt_cmd_sm_passkey_confirm_s sl_bt_cmd_sm_passkey_confirm_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_bonding_confirm_s +{ + uint8_t connection; + uint8_t confirm; +}); + +typedef struct sl_bt_cmd_sm_bonding_confirm_s sl_bt_cmd_sm_bonding_confirm_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_delete_bonding_s +{ + uint8_t bonding; +}); + +typedef struct sl_bt_cmd_sm_delete_bonding_s sl_bt_cmd_sm_delete_bonding_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_get_bonding_handles_s +{ + uint32_t reserved; +}); + +typedef struct sl_bt_cmd_sm_get_bonding_handles_s sl_bt_cmd_sm_get_bonding_handles_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_get_bonding_details_s +{ + uint32_t bonding; +}); + +typedef struct sl_bt_cmd_sm_get_bonding_details_s sl_bt_cmd_sm_get_bonding_details_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_find_bonding_by_address_s +{ + bd_addr address; +}); + +typedef struct sl_bt_cmd_sm_find_bonding_by_address_s sl_bt_cmd_sm_find_bonding_by_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_resolve_rpa_s +{ + bd_addr rpa; +}); + +typedef struct sl_bt_cmd_sm_resolve_rpa_s sl_bt_cmd_sm_resolve_rpa_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_bonding_key_s +{ + uint32_t bonding; + uint8_t key_type; + aes_key_128 key; +}); + +typedef struct sl_bt_cmd_sm_set_bonding_key_s sl_bt_cmd_sm_set_bonding_key_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_legacy_oob_s +{ + uint8_t enable; + aes_key_128 oob_data; +}); + +typedef struct sl_bt_cmd_sm_set_legacy_oob_s sl_bt_cmd_sm_set_legacy_oob_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_oob_s +{ + uint8_t enable; +}); + +typedef struct sl_bt_cmd_sm_set_oob_s sl_bt_cmd_sm_set_oob_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_remote_oob_s +{ + uint8_t enable; + aes_key_128 random; + aes_key_128 confirm; +}); + +typedef struct sl_bt_cmd_sm_set_remote_oob_s sl_bt_cmd_sm_set_remote_oob_t; + + +PACKSTRUCT( struct sl_bt_cmd_sm_set_bonding_data_s +{ + uint8_t connection; + uint8_t type; + uint8array data; +}); + +typedef struct sl_bt_cmd_sm_set_bonding_data_s sl_bt_cmd_sm_set_bonding_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_external_bondingdb_set_data_s +{ + uint8_t connection; + uint8_t type; + uint8array data; +}); + +typedef struct sl_bt_cmd_external_bondingdb_set_data_s sl_bt_cmd_external_bondingdb_set_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_resolving_list_add_device_by_bonding_s +{ + uint32_t bonding; + uint8_t privacy_mode; +}); + +typedef struct sl_bt_cmd_resolving_list_add_device_by_bonding_s sl_bt_cmd_resolving_list_add_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_cmd_resolving_list_add_device_by_address_s +{ + bd_addr address; + uint8_t address_type; + aes_key_128 key; + uint8_t privacy_mode; +}); + +typedef struct sl_bt_cmd_resolving_list_add_device_by_address_s sl_bt_cmd_resolving_list_add_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_resolving_list_remove_device_by_bonding_s +{ + uint32_t bonding; +}); + +typedef struct sl_bt_cmd_resolving_list_remove_device_by_bonding_s sl_bt_cmd_resolving_list_remove_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_cmd_resolving_list_remove_device_by_address_s +{ + bd_addr address; + uint8_t address_type; +}); + +typedef struct sl_bt_cmd_resolving_list_remove_device_by_address_s sl_bt_cmd_resolving_list_remove_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_accept_list_add_device_by_bonding_s +{ + uint32_t bonding; +}); + +typedef struct sl_bt_cmd_accept_list_add_device_by_bonding_s sl_bt_cmd_accept_list_add_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_cmd_accept_list_add_device_by_address_s +{ + bd_addr address; + uint8_t address_type; +}); + +typedef struct sl_bt_cmd_accept_list_add_device_by_address_s sl_bt_cmd_accept_list_add_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_accept_list_remove_device_by_bonding_s +{ + uint32_t bonding; +}); + +typedef struct sl_bt_cmd_accept_list_remove_device_by_bonding_s sl_bt_cmd_accept_list_remove_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_cmd_accept_list_remove_device_by_address_s +{ + bd_addr address; + uint8_t address_type; +}); + +typedef struct sl_bt_cmd_accept_list_remove_device_by_address_s sl_bt_cmd_accept_list_remove_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_cmd_ota_set_device_name_s +{ + uint8array name; +}); + +typedef struct sl_bt_cmd_ota_set_device_name_s sl_bt_cmd_ota_set_device_name_t; + + +PACKSTRUCT( struct sl_bt_cmd_ota_set_advertising_data_s +{ + uint8_t packet_type; + uint8array adv_data; +}); + +typedef struct sl_bt_cmd_ota_set_advertising_data_s sl_bt_cmd_ota_set_advertising_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_ota_set_configuration_s +{ + uint32_t flags; +}); + +typedef struct sl_bt_cmd_ota_set_configuration_s sl_bt_cmd_ota_set_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_ota_set_rf_path_s +{ + uint8_t enable; + uint8_t antenna; +}); + +typedef struct sl_bt_cmd_ota_set_rf_path_s sl_bt_cmd_ota_set_rf_path_t; + + +PACKSTRUCT( struct sl_bt_cmd_coex_set_options_s +{ + uint32_t mask; + uint32_t options; +}); + +typedef struct sl_bt_cmd_coex_set_options_s sl_bt_cmd_coex_set_options_t; + + +PACKSTRUCT( struct sl_bt_cmd_coex_set_parameters_s +{ + uint8_t priority; + uint8_t request; + uint8_t pwm_period; + uint8_t pwm_dutycycle; +}); + +typedef struct sl_bt_cmd_coex_set_parameters_s sl_bt_cmd_coex_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_coex_set_directional_priority_pulse_s +{ + uint8_t pulse; +}); + +typedef struct sl_bt_cmd_coex_set_directional_priority_pulse_s sl_bt_cmd_coex_set_directional_priority_pulse_t; + + +PACKSTRUCT( struct sl_bt_cmd_coex_get_counters_s +{ + uint8_t reset; +}); + +typedef struct sl_bt_cmd_coex_get_counters_s sl_bt_cmd_coex_get_counters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_security_enable_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_cs_security_enable_s sl_bt_cmd_cs_security_enable_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_set_default_settings_s +{ + uint8_t connection; + uint8_t initiator_status; + uint8_t reflector_status; + uint8_t antenna_identifier; + int8_t max_tx_power; +}); + +typedef struct sl_bt_cmd_cs_set_default_settings_s sl_bt_cmd_cs_set_default_settings_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_create_config_s +{ + uint8_t connection; + uint8_t config_id; + uint8_t create_context; + uint8_t main_mode_type; + uint8_t sub_mode_type; + uint8_t min_main_mode_steps; + uint8_t max_main_mode_steps; + uint8_t main_mode_repetition; + uint8_t mode_calibration_steps; + uint8_t role; + uint8_t rtt_type; + uint8_t cs_sync_phy; + sl_bt_cs_channel_map_t channel_map; + uint8_t channel_map_repetition; + uint8_t channel_selection_type; + uint8_t ch3c_shape; + uint8_t ch3c_jump; + uint8_t companion_signal_state; +}); + +typedef struct sl_bt_cmd_cs_create_config_s sl_bt_cmd_cs_create_config_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_remove_config_s +{ + uint8_t connection; + uint8_t config_id; +}); + +typedef struct sl_bt_cmd_cs_remove_config_s sl_bt_cmd_cs_remove_config_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_set_channel_classification_s +{ + sl_bt_cs_channel_map_t channel_map; +}); + +typedef struct sl_bt_cmd_cs_set_channel_classification_s sl_bt_cmd_cs_set_channel_classification_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_set_procedure_parameters_s +{ + uint8_t connection; + uint8_t config_id; + uint16_t max_procedure_len; + uint16_t min_procedure_interval; + uint16_t max_procedure_interval; + uint16_t max_procedure_count; + uint32_t min_subevent_len; + uint32_t max_subevent_len; + uint8_t tone_antenna_config_selection; + uint8_t phy; + int8_t tx_pwr_delta; + uint8_t preferred_peer_antenna; +}); + +typedef struct sl_bt_cmd_cs_set_procedure_parameters_s sl_bt_cmd_cs_set_procedure_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_procedure_enable_s +{ + uint8_t connection; + uint8_t enable; + uint8_t config_id; +}); + +typedef struct sl_bt_cmd_cs_procedure_enable_s sl_bt_cmd_cs_procedure_enable_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_set_antenna_configuration_s +{ + uint8array antenna_element_offset; +}); + +typedef struct sl_bt_cmd_cs_set_antenna_configuration_s sl_bt_cmd_cs_set_antenna_configuration_t; + + +PACKSTRUCT( struct sl_bt_cmd_cs_test_start_s +{ + uint8_t main_mode_type; + uint8_t sub_mode_type; + uint8_t main_mode_repetition; + uint8_t mode_calibration_steps; + uint8_t role; + uint8_t rtt_type; + uint8_t cs_sync_phy; + uint8_t antenna_selection; + sl_bt_cs_subevent_length_t subevent_len; + uint16_t subevent_interval; + int8_t tx_power; + uint8_t t_ip1_time; + uint8_t t_ip2_time; + uint8_t t_fcs_time; + uint8_t t_pm_time; + uint8_t t_sw_time; + uint8_t tone_antenna_config; + uint8_t companion_signal_state; + uint16_t drbg_nonce; + uint16_t override_config; + uint8array override_parameters; +}); + +typedef struct sl_bt_cmd_cs_test_start_s sl_bt_cmd_cs_test_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_l2cap_open_le_channel_s +{ + uint8_t connection; + uint16_t spsm; + uint16_t max_sdu; + uint16_t max_pdu; + uint16_t credit; +}); + +typedef struct sl_bt_cmd_l2cap_open_le_channel_s sl_bt_cmd_l2cap_open_le_channel_t; + + +PACKSTRUCT( struct sl_bt_cmd_l2cap_send_le_channel_open_response_s +{ + uint8_t connection; + uint16_t cid; + uint16_t max_sdu; + uint16_t max_pdu; + uint16_t credit; + uint16_t errorcode; +}); + +typedef struct sl_bt_cmd_l2cap_send_le_channel_open_response_s sl_bt_cmd_l2cap_send_le_channel_open_response_t; + + +PACKSTRUCT( struct sl_bt_cmd_l2cap_channel_send_data_s +{ + uint8_t connection; + uint16_t cid; + uint8array data; +}); + +typedef struct sl_bt_cmd_l2cap_channel_send_data_s sl_bt_cmd_l2cap_channel_send_data_t; + + +PACKSTRUCT( struct sl_bt_cmd_l2cap_channel_send_credit_s +{ + uint8_t connection; + uint16_t cid; + uint16_t credit; +}); + +typedef struct sl_bt_cmd_l2cap_channel_send_credit_s sl_bt_cmd_l2cap_channel_send_credit_t; + + +PACKSTRUCT( struct sl_bt_cmd_l2cap_close_channel_s +{ + uint8_t connection; + uint16_t cid; +}); + +typedef struct sl_bt_cmd_l2cap_close_channel_s sl_bt_cmd_l2cap_close_channel_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_set_dtm_parameters_s +{ + uint8_t cte_length; + uint8_t cte_type; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_transmitter_set_dtm_parameters_s sl_bt_cmd_cte_transmitter_set_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_connection_cte_s +{ + uint8_t connection; + uint8_t cte_types; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_transmitter_enable_connection_cte_s sl_bt_cmd_cte_transmitter_enable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_connection_cte_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_cte_transmitter_disable_connection_cte_s sl_bt_cmd_cte_transmitter_disable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_connectionless_cte_s +{ + uint8_t handle; + uint8_t cte_length; + uint8_t cte_type; + uint8_t cte_count; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_transmitter_enable_connectionless_cte_s sl_bt_cmd_cte_transmitter_enable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_connectionless_cte_s +{ + uint8_t handle; +}); + +typedef struct sl_bt_cmd_cte_transmitter_disable_connectionless_cte_s sl_bt_cmd_cte_transmitter_disable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_enable_silabs_cte_s +{ + uint8_t handle; + uint8_t cte_length; + uint8_t cte_type; + uint8_t cte_count; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_transmitter_enable_silabs_cte_s sl_bt_cmd_cte_transmitter_enable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_transmitter_disable_silabs_cte_s +{ + uint8_t handle; +}); + +typedef struct sl_bt_cmd_cte_transmitter_disable_silabs_cte_s sl_bt_cmd_cte_transmitter_disable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_dtm_parameters_s +{ + uint8_t cte_length; + uint8_t cte_type; + uint8_t slot_durations; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_receiver_set_dtm_parameters_s sl_bt_cmd_cte_receiver_set_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_sync_cte_type_s +{ + uint8_t sync_cte_type; +}); + +typedef struct sl_bt_cmd_cte_receiver_set_sync_cte_type_s sl_bt_cmd_cte_receiver_set_sync_cte_type_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_s +{ + uint8_t mode; + uint16_t skip; + uint16_t timeout; + uint8_t sync_cte_type; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_s sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_set_sync_receive_parameters_s +{ + uint8_t connection; + uint8_t mode; + uint16_t skip; + uint16_t timeout; + uint8_t sync_cte_type; + uint8_t reporting_mode; +}); + +typedef struct sl_bt_cmd_cte_receiver_set_sync_receive_parameters_s sl_bt_cmd_cte_receiver_set_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_configure_s +{ + uint8_t flags; +}); + +typedef struct sl_bt_cmd_cte_receiver_configure_s sl_bt_cmd_cte_receiver_configure_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_connection_cte_s +{ + uint8_t connection; + uint16_t interval; + uint8_t cte_length; + uint8_t cte_type; + uint8_t slot_durations; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_receiver_enable_connection_cte_s sl_bt_cmd_cte_receiver_enable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_disable_connection_cte_s +{ + uint8_t connection; +}); + +typedef struct sl_bt_cmd_cte_receiver_disable_connection_cte_s sl_bt_cmd_cte_receiver_disable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_connectionless_cte_s +{ + uint16_t sync; + uint8_t slot_durations; + uint8_t cte_count; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_receiver_enable_connectionless_cte_s sl_bt_cmd_cte_receiver_enable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_disable_connectionless_cte_s +{ + uint16_t sync; +}); + +typedef struct sl_bt_cmd_cte_receiver_disable_connectionless_cte_s sl_bt_cmd_cte_receiver_disable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_cte_receiver_enable_silabs_cte_s +{ + uint8_t slot_durations; + uint8_t cte_count; + uint8array switching_pattern; +}); + +typedef struct sl_bt_cmd_cte_receiver_enable_silabs_cte_s sl_bt_cmd_cte_receiver_enable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_analyzer_start_s +{ + uint32_t access_address; + uint32_t crc_init; + uint16_t interval; + uint16_t supervision_timeout; + uint8_t central_clock_accuracy; + uint8_t central_phy; + uint8_t peripheral_phy; + uint8_t channel_selection_algorithm; + uint8_t hop; + sl_bt_connection_channel_map_t channel_map; + uint8_t channel; + uint16_t event_counter; + int32_t start_time_us; + uint32_t flags; +}); + +typedef struct sl_bt_cmd_connection_analyzer_start_s sl_bt_cmd_connection_analyzer_start_t; + + +PACKSTRUCT( struct sl_bt_cmd_connection_analyzer_stop_s +{ + uint8_t analyzer; +}); + +typedef struct sl_bt_cmd_connection_analyzer_stop_s sl_bt_cmd_connection_analyzer_stop_t; + + +PACKSTRUCT( struct sl_bt_cmd_user_message_to_target_s +{ + uint8array data; +}); + +typedef struct sl_bt_cmd_user_message_to_target_s sl_bt_cmd_user_message_to_target_t; + + +PACKSTRUCT( struct sl_bt_cmd_user_manage_event_filter_s +{ + uint8array data; +}); + +typedef struct sl_bt_cmd_user_manage_event_filter_s sl_bt_cmd_user_manage_event_filter_t; + + + + +PACKSTRUCT( struct sl_bt_rsp_dfu_flash_set_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_dfu_flash_set_address_s sl_bt_rsp_dfu_flash_set_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_dfu_flash_upload_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_dfu_flash_upload_s sl_bt_rsp_dfu_flash_upload_t; + + +PACKSTRUCT( struct sl_bt_rsp_dfu_flash_upload_finish_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_dfu_flash_upload_finish_s sl_bt_rsp_dfu_flash_upload_finish_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_hello_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_hello_s sl_bt_rsp_system_hello_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_start_bluetooth_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_start_bluetooth_s sl_bt_rsp_system_start_bluetooth_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_stop_bluetooth_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_stop_bluetooth_s sl_bt_rsp_system_stop_bluetooth_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_forcefully_stop_bluetooth_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_forcefully_stop_bluetooth_s sl_bt_rsp_system_forcefully_stop_bluetooth_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_get_version_s +{ + uint16_t result; + uint16_t major; + uint16_t minor; + uint16_t patch; + uint16_t build; + uint32_t bootloader; + uint32_t hash; +}); + +typedef struct sl_bt_rsp_system_get_version_s sl_bt_rsp_system_get_version_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_halt_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_halt_s sl_bt_rsp_system_halt_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_linklayer_configure_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_linklayer_configure_s sl_bt_rsp_system_linklayer_configure_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_set_tx_power_s +{ + uint16_t result; + int16_t set_min; + int16_t set_max; +}); + +typedef struct sl_bt_rsp_system_set_tx_power_s sl_bt_rsp_system_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_get_tx_power_setting_s +{ + uint16_t result; + int16_t support_min; + int16_t support_max; + int16_t set_min; + int16_t set_max; + int16_t rf_path_gain; +}); + +typedef struct sl_bt_rsp_system_get_tx_power_setting_s sl_bt_rsp_system_get_tx_power_setting_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_set_identity_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_set_identity_address_s sl_bt_rsp_system_set_identity_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_get_identity_address_s +{ + uint16_t result; + bd_addr address; + uint8_t type; +}); + +typedef struct sl_bt_rsp_system_get_identity_address_s sl_bt_rsp_system_get_identity_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_get_random_data_s +{ + uint16_t result; + uint8array data; +}); + +typedef struct sl_bt_rsp_system_get_random_data_s sl_bt_rsp_system_get_random_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_data_buffer_write_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_data_buffer_write_s sl_bt_rsp_system_data_buffer_write_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_data_buffer_clear_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_data_buffer_clear_s sl_bt_rsp_system_data_buffer_clear_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_get_counters_s +{ + uint16_t result; + uint16_t tx_packets; + uint16_t rx_packets; + uint16_t crc_errors; + uint16_t failures; +}); + +typedef struct sl_bt_rsp_system_get_counters_s sl_bt_rsp_system_get_counters_t; + + +PACKSTRUCT( struct sl_bt_rsp_system_set_lazy_soft_timer_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_system_set_lazy_soft_timer_s sl_bt_rsp_system_set_lazy_soft_timer_t; + + +PACKSTRUCT( struct sl_bt_rsp_resource_get_status_s +{ + uint16_t result; + uint32_t total_bytes; + uint32_t free_bytes; +}); + +typedef struct sl_bt_rsp_resource_get_status_s sl_bt_rsp_resource_get_status_t; + + +PACKSTRUCT( struct sl_bt_rsp_resource_set_report_threshold_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resource_set_report_threshold_s sl_bt_rsp_resource_set_report_threshold_t; + + +PACKSTRUCT( struct sl_bt_rsp_resource_enable_connection_tx_report_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resource_enable_connection_tx_report_s sl_bt_rsp_resource_enable_connection_tx_report_t; + + +PACKSTRUCT( struct sl_bt_rsp_resource_get_connection_tx_status_s +{ + uint16_t result; + uint16_t flags; + uint16_t packet_count; + uint32_t data_len; +}); + +typedef struct sl_bt_rsp_resource_get_connection_tx_status_s sl_bt_rsp_resource_get_connection_tx_status_t; + + +PACKSTRUCT( struct sl_bt_rsp_resource_disable_connection_tx_report_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resource_disable_connection_tx_report_s sl_bt_rsp_resource_disable_connection_tx_report_t; + + +PACKSTRUCT( struct sl_bt_rsp_gap_set_privacy_mode_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gap_set_privacy_mode_s sl_bt_rsp_gap_set_privacy_mode_t; + + +PACKSTRUCT( struct sl_bt_rsp_gap_set_data_channel_classification_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gap_set_data_channel_classification_s sl_bt_rsp_gap_set_data_channel_classification_t; + + +PACKSTRUCT( struct sl_bt_rsp_gap_enable_whitelisting_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gap_enable_whitelisting_s sl_bt_rsp_gap_enable_whitelisting_t; + + +PACKSTRUCT( struct sl_bt_rsp_gap_set_identity_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gap_set_identity_address_s sl_bt_rsp_gap_set_identity_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_create_set_s +{ + uint16_t result; + uint8_t handle; +}); + +typedef struct sl_bt_rsp_advertiser_create_set_s sl_bt_rsp_advertiser_create_set_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_configure_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_configure_s sl_bt_rsp_advertiser_configure_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_timing_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_timing_s sl_bt_rsp_advertiser_set_timing_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_channel_map_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_channel_map_s sl_bt_rsp_advertiser_set_channel_map_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_tx_power_s +{ + uint16_t result; + int16_t set_power; +}); + +typedef struct sl_bt_rsp_advertiser_set_tx_power_s sl_bt_rsp_advertiser_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_report_scan_request_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_report_scan_request_s sl_bt_rsp_advertiser_set_report_scan_request_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_random_address_s +{ + uint16_t result; + bd_addr address_out; +}); + +typedef struct sl_bt_rsp_advertiser_set_random_address_s sl_bt_rsp_advertiser_set_random_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_clear_random_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_clear_random_address_s sl_bt_rsp_advertiser_clear_random_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_stop_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_stop_s sl_bt_rsp_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_delete_set_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_delete_set_s sl_bt_rsp_advertiser_delete_set_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_phy_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_phy_s sl_bt_rsp_advertiser_set_phy_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_configuration_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_configuration_s sl_bt_rsp_advertiser_set_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_clear_configuration_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_clear_configuration_s sl_bt_rsp_advertiser_clear_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_data_s sl_bt_rsp_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_set_long_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_set_long_data_s sl_bt_rsp_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_start_s sl_bt_rsp_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_start_periodic_advertising_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_start_periodic_advertising_s sl_bt_rsp_advertiser_start_periodic_advertising_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_stop_periodic_advertising_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_stop_periodic_advertising_s sl_bt_rsp_advertiser_stop_periodic_advertising_t; + + +PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_set_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_legacy_advertiser_set_data_s sl_bt_rsp_legacy_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_generate_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_legacy_advertiser_generate_data_s sl_bt_rsp_legacy_advertiser_generate_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_legacy_advertiser_start_s sl_bt_rsp_legacy_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_legacy_advertiser_start_directed_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_legacy_advertiser_start_directed_s sl_bt_rsp_legacy_advertiser_start_directed_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_phy_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_set_phy_s sl_bt_rsp_extended_advertiser_set_phy_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_set_data_s sl_bt_rsp_extended_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_set_long_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_set_long_data_s sl_bt_rsp_extended_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_generate_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_generate_data_s sl_bt_rsp_extended_advertiser_generate_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_start_s sl_bt_rsp_extended_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_extended_advertiser_start_directed_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_extended_advertiser_start_directed_s sl_bt_rsp_extended_advertiser_start_directed_t; + + +PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_set_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_periodic_advertiser_set_data_s sl_bt_rsp_periodic_advertiser_set_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_set_long_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_periodic_advertiser_set_long_data_s sl_bt_rsp_periodic_advertiser_set_long_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_periodic_advertiser_start_s sl_bt_rsp_periodic_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_periodic_advertiser_stop_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_periodic_advertiser_stop_s sl_bt_rsp_periodic_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_set_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_set_parameters_s sl_bt_rsp_scanner_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_set_parameters_and_filter_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_set_parameters_and_filter_s sl_bt_rsp_scanner_set_parameters_and_filter_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_stop_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_stop_s sl_bt_rsp_scanner_stop_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_set_timing_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_set_timing_s sl_bt_rsp_scanner_set_timing_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_set_mode_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_set_mode_s sl_bt_rsp_scanner_set_mode_t; + + +PACKSTRUCT( struct sl_bt_rsp_scanner_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_scanner_start_s sl_bt_rsp_scanner_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_set_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_set_parameters_s sl_bt_rsp_sync_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_open_s +{ + uint16_t result; + uint16_t sync; +}); + +typedef struct sl_bt_rsp_sync_open_s sl_bt_rsp_sync_open_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_set_reporting_mode_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_set_reporting_mode_s sl_bt_rsp_sync_set_reporting_mode_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_update_sync_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_update_sync_parameters_s sl_bt_rsp_sync_update_sync_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_close_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_close_s sl_bt_rsp_sync_close_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_scanner_set_sync_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_scanner_set_sync_parameters_s sl_bt_rsp_sync_scanner_set_sync_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_scanner_open_s +{ + uint16_t result; + uint16_t sync; +}); + +typedef struct sl_bt_rsp_sync_scanner_open_s sl_bt_rsp_sync_scanner_open_t; + + +PACKSTRUCT( struct sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_s sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_past_receiver_set_sync_receive_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_past_receiver_set_sync_receive_parameters_s sl_bt_rsp_past_receiver_set_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_advertiser_past_transfer_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_advertiser_past_transfer_s sl_bt_rsp_advertiser_past_transfer_t; + + +PACKSTRUCT( struct sl_bt_rsp_sync_past_transfer_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sync_past_transfer_s sl_bt_rsp_sync_past_transfer_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_sync_set_sync_subevents_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_pawr_sync_set_sync_subevents_s sl_bt_rsp_pawr_sync_set_sync_subevents_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_sync_set_response_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_pawr_sync_set_response_data_s sl_bt_rsp_pawr_sync_set_response_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_pawr_advertiser_start_s sl_bt_rsp_pawr_advertiser_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_set_subevent_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_pawr_advertiser_set_subevent_data_s sl_bt_rsp_pawr_advertiser_set_subevent_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_create_connection_s +{ + uint16_t result; + uint8_t connection; +}); + +typedef struct sl_bt_rsp_pawr_advertiser_create_connection_s sl_bt_rsp_pawr_advertiser_create_connection_t; + + +PACKSTRUCT( struct sl_bt_rsp_pawr_advertiser_stop_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_pawr_advertiser_stop_s sl_bt_rsp_pawr_advertiser_stop_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_default_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_default_parameters_s sl_bt_rsp_connection_set_default_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_default_preferred_phy_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_default_preferred_phy_s sl_bt_rsp_connection_set_default_preferred_phy_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_default_data_length_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_default_data_length_s sl_bt_rsp_connection_set_default_data_length_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_open_s +{ + uint16_t result; + uint8_t connection; +}); + +typedef struct sl_bt_rsp_connection_open_s sl_bt_rsp_connection_open_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_parameters_s sl_bt_rsp_connection_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_preferred_phy_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_preferred_phy_s sl_bt_rsp_connection_set_preferred_phy_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_disable_slave_latency_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_disable_slave_latency_s sl_bt_rsp_connection_disable_slave_latency_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_median_rssi_s +{ + uint16_t result; + int8_t rssi; +}); + +typedef struct sl_bt_rsp_connection_get_median_rssi_s sl_bt_rsp_connection_get_median_rssi_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_read_channel_map_s +{ + uint16_t result; + uint8array channel_map; +}); + +typedef struct sl_bt_rsp_connection_read_channel_map_s sl_bt_rsp_connection_read_channel_map_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_power_reporting_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_power_reporting_s sl_bt_rsp_connection_set_power_reporting_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_remote_power_reporting_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_remote_power_reporting_s sl_bt_rsp_connection_set_remote_power_reporting_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_tx_power_s +{ + uint16_t result; + int8_t current_level; + int8_t max_level; +}); + +typedef struct sl_bt_rsp_connection_get_tx_power_s sl_bt_rsp_connection_get_tx_power_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_remote_tx_power_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_get_remote_tx_power_s sl_bt_rsp_connection_get_remote_tx_power_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_tx_power_s +{ + uint16_t result; + int16_t tx_power_out; +}); + +typedef struct sl_bt_rsp_connection_set_tx_power_s sl_bt_rsp_connection_set_tx_power_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_read_remote_used_features_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_read_remote_used_features_s sl_bt_rsp_connection_read_remote_used_features_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_security_status_s +{ + uint16_t result; + uint8_t security_mode; + uint8_t key_size; + uint8_t bonding_handle; +}); + +typedef struct sl_bt_rsp_connection_get_security_status_s sl_bt_rsp_connection_get_security_status_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_set_data_length_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_set_data_length_s sl_bt_rsp_connection_set_data_length_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_read_statistics_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_read_statistics_s sl_bt_rsp_connection_read_statistics_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_scheduling_details_s +{ + uint16_t result; + uint32_t access_address; + uint8_t role; + uint32_t crc_init; + uint16_t interval; + uint16_t supervision_timeout; + uint8_t central_clock_accuracy; + uint8_t central_phy; + uint8_t peripheral_phy; + uint8_t channel_selection_algorithm; + uint8_t hop; + sl_bt_connection_channel_map_t channel_map; + uint8_t channel; + uint16_t event_counter; + uint32_t start_time_us; +}); + +typedef struct sl_bt_rsp_connection_get_scheduling_details_s sl_bt_rsp_connection_get_scheduling_details_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_close_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_close_s sl_bt_rsp_connection_close_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_forcefully_close_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_forcefully_close_s sl_bt_rsp_connection_forcefully_close_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_get_rssi_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_get_rssi_s sl_bt_rsp_connection_get_rssi_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_set_max_mtu_s +{ + uint16_t result; + uint16_t max_mtu_out; +}); + +typedef struct sl_bt_rsp_gatt_set_max_mtu_s sl_bt_rsp_gatt_set_max_mtu_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_primary_services_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_primary_services_s sl_bt_rsp_gatt_discover_primary_services_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_primary_services_by_uuid_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_primary_services_by_uuid_s sl_bt_rsp_gatt_discover_primary_services_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_find_included_services_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_find_included_services_s sl_bt_rsp_gatt_find_included_services_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristics_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_characteristics_s sl_bt_rsp_gatt_discover_characteristics_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristics_by_uuid_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_characteristics_by_uuid_s sl_bt_rsp_gatt_discover_characteristics_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_descriptors_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_descriptors_s sl_bt_rsp_gatt_discover_descriptors_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_discover_characteristic_descriptors_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_discover_characteristic_descriptors_s sl_bt_rsp_gatt_discover_characteristic_descriptors_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_set_characteristic_notification_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_set_characteristic_notification_s sl_bt_rsp_gatt_set_characteristic_notification_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_send_characteristic_confirmation_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_send_characteristic_confirmation_s sl_bt_rsp_gatt_send_characteristic_confirmation_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_read_characteristic_value_s sl_bt_rsp_gatt_read_characteristic_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_from_offset_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_read_characteristic_value_from_offset_s sl_bt_rsp_gatt_read_characteristic_value_from_offset_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_read_multiple_characteristic_values_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_read_multiple_characteristic_values_s sl_bt_rsp_gatt_read_multiple_characteristic_values_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_read_characteristic_value_by_uuid_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_read_characteristic_value_by_uuid_s sl_bt_rsp_gatt_read_characteristic_value_by_uuid_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_write_characteristic_value_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_write_characteristic_value_s sl_bt_rsp_gatt_write_characteristic_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_write_characteristic_value_without_response_s +{ + uint16_t result; + uint16_t sent_len; +}); + +typedef struct sl_bt_rsp_gatt_write_characteristic_value_without_response_s sl_bt_rsp_gatt_write_characteristic_value_without_response_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_prepare_characteristic_value_write_s +{ + uint16_t result; + uint16_t sent_len; +}); + +typedef struct sl_bt_rsp_gatt_prepare_characteristic_value_write_s sl_bt_rsp_gatt_prepare_characteristic_value_write_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_s +{ + uint16_t result; + uint16_t sent_len; +}); + +typedef struct sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_s sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_execute_characteristic_value_write_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_execute_characteristic_value_write_s sl_bt_rsp_gatt_execute_characteristic_value_write_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_read_descriptor_value_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_read_descriptor_value_s sl_bt_rsp_gatt_read_descriptor_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_write_descriptor_value_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_write_descriptor_value_s sl_bt_rsp_gatt_write_descriptor_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_new_session_s +{ + uint16_t result; + uint16_t session; +}); + +typedef struct sl_bt_rsp_gattdb_new_session_s sl_bt_rsp_gattdb_new_session_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_service_s +{ + uint16_t result; + uint16_t service; +}); + +typedef struct sl_bt_rsp_gattdb_add_service_s sl_bt_rsp_gattdb_add_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_service_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_remove_service_s sl_bt_rsp_gattdb_remove_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_included_service_s +{ + uint16_t result; + uint16_t attribute; +}); + +typedef struct sl_bt_rsp_gattdb_add_included_service_s sl_bt_rsp_gattdb_add_included_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_included_service_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_remove_included_service_s sl_bt_rsp_gattdb_remove_included_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid16_characteristic_s +{ + uint16_t result; + uint16_t characteristic; +}); + +typedef struct sl_bt_rsp_gattdb_add_uuid16_characteristic_s sl_bt_rsp_gattdb_add_uuid16_characteristic_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid128_characteristic_s +{ + uint16_t result; + uint16_t characteristic; +}); + +typedef struct sl_bt_rsp_gattdb_add_uuid128_characteristic_s sl_bt_rsp_gattdb_add_uuid128_characteristic_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_characteristic_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_remove_characteristic_s sl_bt_rsp_gattdb_remove_characteristic_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid16_descriptor_s +{ + uint16_t result; + uint16_t descriptor; +}); + +typedef struct sl_bt_rsp_gattdb_add_uuid16_descriptor_s sl_bt_rsp_gattdb_add_uuid16_descriptor_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_add_uuid128_descriptor_s +{ + uint16_t result; + uint16_t descriptor; +}); + +typedef struct sl_bt_rsp_gattdb_add_uuid128_descriptor_s sl_bt_rsp_gattdb_add_uuid128_descriptor_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_remove_descriptor_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_remove_descriptor_s sl_bt_rsp_gattdb_remove_descriptor_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_start_service_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_start_service_s sl_bt_rsp_gattdb_start_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_stop_service_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_stop_service_s sl_bt_rsp_gattdb_stop_service_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_start_characteristic_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_start_characteristic_s sl_bt_rsp_gattdb_start_characteristic_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_stop_characteristic_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_stop_characteristic_s sl_bt_rsp_gattdb_stop_characteristic_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_commit_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_commit_s sl_bt_rsp_gattdb_commit_t; + + +PACKSTRUCT( struct sl_bt_rsp_gattdb_abort_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gattdb_abort_s sl_bt_rsp_gattdb_abort_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_set_max_mtu_s +{ + uint16_t result; + uint16_t max_mtu_out; +}); + +typedef struct sl_bt_rsp_gatt_server_set_max_mtu_s sl_bt_rsp_gatt_server_set_max_mtu_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_get_mtu_s +{ + uint16_t result; + uint16_t mtu; +}); + +typedef struct sl_bt_rsp_gatt_server_get_mtu_s sl_bt_rsp_gatt_server_get_mtu_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_find_attribute_s +{ + uint16_t result; + uint16_t attribute; +}); + +typedef struct sl_bt_rsp_gatt_server_find_attribute_s sl_bt_rsp_gatt_server_find_attribute_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_attribute_value_s +{ + uint16_t result; + uint8array value; +}); + +typedef struct sl_bt_rsp_gatt_server_read_attribute_value_s sl_bt_rsp_gatt_server_read_attribute_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_attribute_type_s +{ + uint16_t result; + uint8array type; +}); + +typedef struct sl_bt_rsp_gatt_server_read_attribute_type_s sl_bt_rsp_gatt_server_read_attribute_type_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_write_attribute_value_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_write_attribute_value_s sl_bt_rsp_gatt_server_write_attribute_value_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_read_response_s +{ + uint16_t result; + uint16_t sent_len; +}); + +typedef struct sl_bt_rsp_gatt_server_send_user_read_response_s sl_bt_rsp_gatt_server_send_user_read_response_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_write_response_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_send_user_write_response_s sl_bt_rsp_gatt_server_send_user_write_response_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_notification_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_send_notification_s sl_bt_rsp_gatt_server_send_notification_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_indication_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_send_indication_s sl_bt_rsp_gatt_server_send_indication_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_notify_all_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_notify_all_s sl_bt_rsp_gatt_server_notify_all_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_client_configuration_s +{ + uint16_t result; + uint16_t client_config_flags; +}); + +typedef struct sl_bt_rsp_gatt_server_read_client_configuration_s sl_bt_rsp_gatt_server_read_client_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_send_user_prepare_write_response_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_send_user_prepare_write_response_s sl_bt_rsp_gatt_server_send_user_prepare_write_response_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_set_capabilities_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_set_capabilities_s sl_bt_rsp_gatt_server_set_capabilities_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_enable_capabilities_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_enable_capabilities_s sl_bt_rsp_gatt_server_enable_capabilities_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_disable_capabilities_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_gatt_server_disable_capabilities_s sl_bt_rsp_gatt_server_disable_capabilities_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_get_enabled_capabilities_s +{ + uint16_t result; + uint32_t caps; +}); + +typedef struct sl_bt_rsp_gatt_server_get_enabled_capabilities_s sl_bt_rsp_gatt_server_get_enabled_capabilities_t; + + +PACKSTRUCT( struct sl_bt_rsp_gatt_server_read_client_supported_features_s +{ + uint16_t result; + uint8_t client_features; +}); + +typedef struct sl_bt_rsp_gatt_server_read_client_supported_features_s sl_bt_rsp_gatt_server_read_client_supported_features_t; + + +PACKSTRUCT( struct sl_bt_rsp_nvm_save_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_nvm_save_s sl_bt_rsp_nvm_save_t; + + +PACKSTRUCT( struct sl_bt_rsp_nvm_load_s +{ + uint16_t result; + uint8array value; +}); + +typedef struct sl_bt_rsp_nvm_load_s sl_bt_rsp_nvm_load_t; + + +PACKSTRUCT( struct sl_bt_rsp_nvm_erase_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_nvm_erase_s sl_bt_rsp_nvm_erase_t; + + +PACKSTRUCT( struct sl_bt_rsp_nvm_erase_all_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_nvm_erase_all_s sl_bt_rsp_nvm_erase_all_t; + + +PACKSTRUCT( struct sl_bt_rsp_test_dtm_tx_v4_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_test_dtm_tx_v4_s sl_bt_rsp_test_dtm_tx_v4_t; + + +PACKSTRUCT( struct sl_bt_rsp_test_dtm_tx_cw_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_test_dtm_tx_cw_s sl_bt_rsp_test_dtm_tx_cw_t; + + +PACKSTRUCT( struct sl_bt_rsp_test_dtm_rx_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_test_dtm_rx_s sl_bt_rsp_test_dtm_rx_t; + + +PACKSTRUCT( struct sl_bt_rsp_test_dtm_end_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_test_dtm_end_s sl_bt_rsp_test_dtm_end_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_configure_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_configure_s sl_bt_rsp_sm_configure_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_minimum_key_size_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_minimum_key_size_s sl_bt_rsp_sm_set_minimum_key_size_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_debug_mode_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_debug_mode_s sl_bt_rsp_sm_set_debug_mode_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_add_to_whitelist_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_add_to_whitelist_s sl_bt_rsp_sm_add_to_whitelist_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_store_bonding_configuration_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_store_bonding_configuration_s sl_bt_rsp_sm_store_bonding_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_bondable_mode_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_bondable_mode_s sl_bt_rsp_sm_set_bondable_mode_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_passkey_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_passkey_s sl_bt_rsp_sm_set_passkey_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_increase_security_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_increase_security_s sl_bt_rsp_sm_increase_security_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_enter_passkey_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_enter_passkey_s sl_bt_rsp_sm_enter_passkey_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_passkey_confirm_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_passkey_confirm_s sl_bt_rsp_sm_passkey_confirm_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_bonding_confirm_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_bonding_confirm_s sl_bt_rsp_sm_bonding_confirm_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_delete_bonding_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_delete_bonding_s sl_bt_rsp_sm_delete_bonding_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_delete_bondings_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_delete_bondings_s sl_bt_rsp_sm_delete_bondings_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_get_bonding_handles_s +{ + uint16_t result; + uint32_t num_bondings; + uint8array bondings; +}); + +typedef struct sl_bt_rsp_sm_get_bonding_handles_s sl_bt_rsp_sm_get_bonding_handles_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_get_bonding_details_s +{ + uint16_t result; + bd_addr address; + uint8_t address_type; + uint8_t security_mode; + uint8_t key_size; +}); + +typedef struct sl_bt_rsp_sm_get_bonding_details_s sl_bt_rsp_sm_get_bonding_details_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_find_bonding_by_address_s +{ + uint16_t result; + uint32_t bonding; + uint8_t security_mode; + uint8_t key_size; +}); + +typedef struct sl_bt_rsp_sm_find_bonding_by_address_s sl_bt_rsp_sm_find_bonding_by_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_resolve_rpa_s +{ + uint16_t result; + bd_addr address; + uint8_t address_type; + uint32_t bonding; +}); + +typedef struct sl_bt_rsp_sm_resolve_rpa_s sl_bt_rsp_sm_resolve_rpa_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_bonding_key_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_bonding_key_s sl_bt_rsp_sm_set_bonding_key_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_legacy_oob_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_legacy_oob_s sl_bt_rsp_sm_set_legacy_oob_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_oob_s +{ + uint16_t result; + aes_key_128 random; + aes_key_128 confirm; +}); + +typedef struct sl_bt_rsp_sm_set_oob_s sl_bt_rsp_sm_set_oob_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_remote_oob_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_remote_oob_s sl_bt_rsp_sm_set_remote_oob_t; + + +PACKSTRUCT( struct sl_bt_rsp_sm_set_bonding_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_sm_set_bonding_data_s sl_bt_rsp_sm_set_bonding_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_external_bondingdb_set_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_external_bondingdb_set_data_s sl_bt_rsp_external_bondingdb_set_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_resolving_list_add_device_by_bonding_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resolving_list_add_device_by_bonding_s sl_bt_rsp_resolving_list_add_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_rsp_resolving_list_add_device_by_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resolving_list_add_device_by_address_s sl_bt_rsp_resolving_list_add_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_device_by_bonding_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resolving_list_remove_device_by_bonding_s sl_bt_rsp_resolving_list_remove_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_device_by_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resolving_list_remove_device_by_address_s sl_bt_rsp_resolving_list_remove_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_resolving_list_remove_all_devices_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_resolving_list_remove_all_devices_s sl_bt_rsp_resolving_list_remove_all_devices_t; + + +PACKSTRUCT( struct sl_bt_rsp_accept_list_add_device_by_bonding_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_accept_list_add_device_by_bonding_s sl_bt_rsp_accept_list_add_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_rsp_accept_list_add_device_by_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_accept_list_add_device_by_address_s sl_bt_rsp_accept_list_add_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_device_by_bonding_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_accept_list_remove_device_by_bonding_s sl_bt_rsp_accept_list_remove_device_by_bonding_t; + + +PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_device_by_address_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_accept_list_remove_device_by_address_s sl_bt_rsp_accept_list_remove_device_by_address_t; + + +PACKSTRUCT( struct sl_bt_rsp_accept_list_remove_all_devices_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_accept_list_remove_all_devices_s sl_bt_rsp_accept_list_remove_all_devices_t; + + +PACKSTRUCT( struct sl_bt_rsp_ota_set_device_name_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_ota_set_device_name_s sl_bt_rsp_ota_set_device_name_t; + + +PACKSTRUCT( struct sl_bt_rsp_ota_set_advertising_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_ota_set_advertising_data_s sl_bt_rsp_ota_set_advertising_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_ota_set_configuration_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_ota_set_configuration_s sl_bt_rsp_ota_set_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_ota_set_rf_path_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_ota_set_rf_path_s sl_bt_rsp_ota_set_rf_path_t; + + +PACKSTRUCT( struct sl_bt_rsp_coex_set_options_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_coex_set_options_s sl_bt_rsp_coex_set_options_t; + + +PACKSTRUCT( struct sl_bt_rsp_coex_set_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_coex_set_parameters_s sl_bt_rsp_coex_set_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_coex_set_directional_priority_pulse_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_coex_set_directional_priority_pulse_s sl_bt_rsp_coex_set_directional_priority_pulse_t; + + +PACKSTRUCT( struct sl_bt_rsp_coex_get_parameters_s +{ + uint16_t result; + uint8_t priority; + uint8_t request; + uint8_t pwm_period; + uint8_t pwm_dutycycle; +}); + +typedef struct sl_bt_rsp_coex_get_parameters_s sl_bt_rsp_coex_get_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_coex_get_counters_s +{ + uint16_t result; + uint8array counters; +}); + +typedef struct sl_bt_rsp_coex_get_counters_s sl_bt_rsp_coex_get_counters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_security_enable_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_security_enable_s sl_bt_rsp_cs_security_enable_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_set_default_settings_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_set_default_settings_s sl_bt_rsp_cs_set_default_settings_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_create_config_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_create_config_s sl_bt_rsp_cs_create_config_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_remove_config_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_remove_config_s sl_bt_rsp_cs_remove_config_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_set_channel_classification_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_set_channel_classification_s sl_bt_rsp_cs_set_channel_classification_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_set_procedure_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_set_procedure_parameters_s sl_bt_rsp_cs_set_procedure_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_procedure_enable_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_procedure_enable_s sl_bt_rsp_cs_procedure_enable_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_set_antenna_configuration_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_set_antenna_configuration_s sl_bt_rsp_cs_set_antenna_configuration_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_read_local_supported_capabilities_s +{ + uint16_t result; + uint8_t num_config; + uint16_t max_consecutive_procedures; + uint8_t num_antennas; + uint8_t max_antenna_paths; + uint8_t roles; + uint8_t optional_modes; + uint8_t rtt_capability; + uint8_t rtt_aa_only; + uint8_t rtt_sounding; + uint8_t rtt_random_payload; + uint8_t optional_cs_sync_phys; + uint16_t optional_subfeatures; + uint16_t optional_t_ip1_times; + uint16_t optional_t_ip2_times; + uint16_t optional_t_fcs_times; + uint16_t optional_t_pm_times; + uint8_t t_sw_times; +}); + +typedef struct sl_bt_rsp_cs_read_local_supported_capabilities_s sl_bt_rsp_cs_read_local_supported_capabilities_t; + + +PACKSTRUCT( struct sl_bt_rsp_cs_test_start_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cs_test_start_s sl_bt_rsp_cs_test_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_l2cap_open_le_channel_s +{ + uint16_t result; + uint16_t cid; +}); + +typedef struct sl_bt_rsp_l2cap_open_le_channel_s sl_bt_rsp_l2cap_open_le_channel_t; + + +PACKSTRUCT( struct sl_bt_rsp_l2cap_send_le_channel_open_response_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_l2cap_send_le_channel_open_response_s sl_bt_rsp_l2cap_send_le_channel_open_response_t; + + +PACKSTRUCT( struct sl_bt_rsp_l2cap_channel_send_data_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_l2cap_channel_send_data_s sl_bt_rsp_l2cap_channel_send_data_t; + + +PACKSTRUCT( struct sl_bt_rsp_l2cap_channel_send_credit_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_l2cap_channel_send_credit_s sl_bt_rsp_l2cap_channel_send_credit_t; + + +PACKSTRUCT( struct sl_bt_rsp_l2cap_close_channel_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_l2cap_close_channel_s sl_bt_rsp_l2cap_close_channel_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_set_dtm_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_set_dtm_parameters_s sl_bt_rsp_cte_transmitter_set_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_clear_dtm_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_clear_dtm_parameters_s sl_bt_rsp_cte_transmitter_clear_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_connection_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_enable_connection_cte_s sl_bt_rsp_cte_transmitter_enable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_connection_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_disable_connection_cte_s sl_bt_rsp_cte_transmitter_disable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_connectionless_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_enable_connectionless_cte_s sl_bt_rsp_cte_transmitter_enable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_connectionless_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_disable_connectionless_cte_s sl_bt_rsp_cte_transmitter_disable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_enable_silabs_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_enable_silabs_cte_s sl_bt_rsp_cte_transmitter_enable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_transmitter_disable_silabs_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_transmitter_disable_silabs_cte_s sl_bt_rsp_cte_transmitter_disable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_dtm_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_set_dtm_parameters_s sl_bt_rsp_cte_receiver_set_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_clear_dtm_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_clear_dtm_parameters_s sl_bt_rsp_cte_receiver_clear_dtm_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_sync_cte_type_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_set_sync_cte_type_s sl_bt_rsp_cte_receiver_set_sync_cte_type_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_s sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_set_sync_receive_parameters_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_set_sync_receive_parameters_s sl_bt_rsp_cte_receiver_set_sync_receive_parameters_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_configure_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_configure_s sl_bt_rsp_cte_receiver_configure_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_connection_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_enable_connection_cte_s sl_bt_rsp_cte_receiver_enable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_connection_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_disable_connection_cte_s sl_bt_rsp_cte_receiver_disable_connection_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_connectionless_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_enable_connectionless_cte_s sl_bt_rsp_cte_receiver_enable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_connectionless_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_disable_connectionless_cte_s sl_bt_rsp_cte_receiver_disable_connectionless_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_enable_silabs_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_enable_silabs_cte_s sl_bt_rsp_cte_receiver_enable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_cte_receiver_disable_silabs_cte_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_cte_receiver_disable_silabs_cte_s sl_bt_rsp_cte_receiver_disable_silabs_cte_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_analyzer_start_s +{ + uint16_t result; + uint8_t analyzer; +}); + +typedef struct sl_bt_rsp_connection_analyzer_start_s sl_bt_rsp_connection_analyzer_start_t; + + +PACKSTRUCT( struct sl_bt_rsp_connection_analyzer_stop_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_connection_analyzer_stop_s sl_bt_rsp_connection_analyzer_stop_t; + + +PACKSTRUCT( struct sl_bt_rsp_user_message_to_target_s +{ + uint16_t result; + uint8array response; +}); + +typedef struct sl_bt_rsp_user_message_to_target_s sl_bt_rsp_user_message_to_target_t; + + +PACKSTRUCT( struct sl_bt_rsp_user_manage_event_filter_s +{ + uint16_t result; +}); + +typedef struct sl_bt_rsp_user_manage_event_filter_s sl_bt_rsp_user_manage_event_filter_t; + + + +PACKSTRUCT( struct sl_bt_packet { + uint32_t header; + union { + uint8_t handle; + sl_bt_rsp_error_t rsp_error; + sl_bt_cmd_dfu_flash_set_address_t cmd_dfu_flash_set_address; + sl_bt_cmd_dfu_flash_upload_t cmd_dfu_flash_upload; + sl_bt_cmd_system_reset_t cmd_system_reset; + sl_bt_cmd_system_halt_t cmd_system_halt; + sl_bt_cmd_system_linklayer_configure_t cmd_system_linklayer_configure; + sl_bt_cmd_system_set_tx_power_t cmd_system_set_tx_power; + sl_bt_cmd_system_set_identity_address_t cmd_system_set_identity_address; + sl_bt_cmd_system_get_random_data_t cmd_system_get_random_data; + sl_bt_cmd_system_data_buffer_write_t cmd_system_data_buffer_write; + sl_bt_cmd_system_get_counters_t cmd_system_get_counters; + sl_bt_cmd_system_set_lazy_soft_timer_t cmd_system_set_lazy_soft_timer; + sl_bt_cmd_resource_set_report_threshold_t cmd_resource_set_report_threshold; + sl_bt_cmd_resource_enable_connection_tx_report_t cmd_resource_enable_connection_tx_report; + sl_bt_cmd_resource_get_connection_tx_status_t cmd_resource_get_connection_tx_status; + sl_bt_cmd_gap_set_privacy_mode_t cmd_gap_set_privacy_mode; + sl_bt_cmd_gap_set_data_channel_classification_t cmd_gap_set_data_channel_classification; + sl_bt_cmd_gap_enable_whitelisting_t cmd_gap_enable_whitelisting; + sl_bt_cmd_gap_set_identity_address_t cmd_gap_set_identity_address; + sl_bt_cmd_advertiser_configure_t cmd_advertiser_configure; + sl_bt_cmd_advertiser_set_timing_t cmd_advertiser_set_timing; + sl_bt_cmd_advertiser_set_channel_map_t cmd_advertiser_set_channel_map; + sl_bt_cmd_advertiser_set_tx_power_t cmd_advertiser_set_tx_power; + sl_bt_cmd_advertiser_set_report_scan_request_t cmd_advertiser_set_report_scan_request; + sl_bt_cmd_advertiser_set_random_address_t cmd_advertiser_set_random_address; + sl_bt_cmd_advertiser_clear_random_address_t cmd_advertiser_clear_random_address; + sl_bt_cmd_advertiser_stop_t cmd_advertiser_stop; + sl_bt_cmd_advertiser_delete_set_t cmd_advertiser_delete_set; + sl_bt_cmd_advertiser_set_phy_t cmd_advertiser_set_phy; + sl_bt_cmd_advertiser_set_configuration_t cmd_advertiser_set_configuration; + sl_bt_cmd_advertiser_clear_configuration_t cmd_advertiser_clear_configuration; + sl_bt_cmd_advertiser_set_data_t cmd_advertiser_set_data; + sl_bt_cmd_advertiser_set_long_data_t cmd_advertiser_set_long_data; + sl_bt_cmd_advertiser_start_t cmd_advertiser_start; + sl_bt_cmd_advertiser_start_periodic_advertising_t cmd_advertiser_start_periodic_advertising; + sl_bt_cmd_advertiser_stop_periodic_advertising_t cmd_advertiser_stop_periodic_advertising; + sl_bt_cmd_legacy_advertiser_set_data_t cmd_legacy_advertiser_set_data; + sl_bt_cmd_legacy_advertiser_generate_data_t cmd_legacy_advertiser_generate_data; + sl_bt_cmd_legacy_advertiser_start_t cmd_legacy_advertiser_start; + sl_bt_cmd_legacy_advertiser_start_directed_t cmd_legacy_advertiser_start_directed; + sl_bt_cmd_extended_advertiser_set_phy_t cmd_extended_advertiser_set_phy; + sl_bt_cmd_extended_advertiser_set_data_t cmd_extended_advertiser_set_data; + sl_bt_cmd_extended_advertiser_set_long_data_t cmd_extended_advertiser_set_long_data; + sl_bt_cmd_extended_advertiser_generate_data_t cmd_extended_advertiser_generate_data; + sl_bt_cmd_extended_advertiser_start_t cmd_extended_advertiser_start; + sl_bt_cmd_extended_advertiser_start_directed_t cmd_extended_advertiser_start_directed; + sl_bt_cmd_periodic_advertiser_set_data_t cmd_periodic_advertiser_set_data; + sl_bt_cmd_periodic_advertiser_set_long_data_t cmd_periodic_advertiser_set_long_data; + sl_bt_cmd_periodic_advertiser_start_t cmd_periodic_advertiser_start; + sl_bt_cmd_periodic_advertiser_stop_t cmd_periodic_advertiser_stop; + sl_bt_cmd_scanner_set_parameters_t cmd_scanner_set_parameters; + sl_bt_cmd_scanner_set_parameters_and_filter_t cmd_scanner_set_parameters_and_filter; + sl_bt_cmd_scanner_set_timing_t cmd_scanner_set_timing; + sl_bt_cmd_scanner_set_mode_t cmd_scanner_set_mode; + sl_bt_cmd_scanner_start_t cmd_scanner_start; + sl_bt_cmd_sync_set_parameters_t cmd_sync_set_parameters; + sl_bt_cmd_sync_open_t cmd_sync_open; + sl_bt_cmd_sync_set_reporting_mode_t cmd_sync_set_reporting_mode; + sl_bt_cmd_sync_update_sync_parameters_t cmd_sync_update_sync_parameters; + sl_bt_cmd_sync_close_t cmd_sync_close; + sl_bt_cmd_sync_scanner_set_sync_parameters_t cmd_sync_scanner_set_sync_parameters; + sl_bt_cmd_sync_scanner_open_t cmd_sync_scanner_open; + sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_t cmd_past_receiver_set_default_sync_receive_parameters; + sl_bt_cmd_past_receiver_set_sync_receive_parameters_t cmd_past_receiver_set_sync_receive_parameters; + sl_bt_cmd_advertiser_past_transfer_t cmd_advertiser_past_transfer; + sl_bt_cmd_sync_past_transfer_t cmd_sync_past_transfer; + sl_bt_cmd_pawr_sync_set_sync_subevents_t cmd_pawr_sync_set_sync_subevents; + sl_bt_cmd_pawr_sync_set_response_data_t cmd_pawr_sync_set_response_data; + sl_bt_cmd_pawr_advertiser_start_t cmd_pawr_advertiser_start; + sl_bt_cmd_pawr_advertiser_set_subevent_data_t cmd_pawr_advertiser_set_subevent_data; + sl_bt_cmd_pawr_advertiser_create_connection_t cmd_pawr_advertiser_create_connection; + sl_bt_cmd_pawr_advertiser_stop_t cmd_pawr_advertiser_stop; + sl_bt_cmd_connection_set_default_parameters_t cmd_connection_set_default_parameters; + sl_bt_cmd_connection_set_default_preferred_phy_t cmd_connection_set_default_preferred_phy; + sl_bt_cmd_connection_set_default_data_length_t cmd_connection_set_default_data_length; + sl_bt_cmd_connection_open_t cmd_connection_open; + sl_bt_cmd_connection_set_parameters_t cmd_connection_set_parameters; + sl_bt_cmd_connection_set_preferred_phy_t cmd_connection_set_preferred_phy; + sl_bt_cmd_connection_disable_slave_latency_t cmd_connection_disable_slave_latency; + sl_bt_cmd_connection_get_median_rssi_t cmd_connection_get_median_rssi; + sl_bt_cmd_connection_read_channel_map_t cmd_connection_read_channel_map; + sl_bt_cmd_connection_set_power_reporting_t cmd_connection_set_power_reporting; + sl_bt_cmd_connection_set_remote_power_reporting_t cmd_connection_set_remote_power_reporting; + sl_bt_cmd_connection_get_tx_power_t cmd_connection_get_tx_power; + sl_bt_cmd_connection_get_remote_tx_power_t cmd_connection_get_remote_tx_power; + sl_bt_cmd_connection_set_tx_power_t cmd_connection_set_tx_power; + sl_bt_cmd_connection_read_remote_used_features_t cmd_connection_read_remote_used_features; + sl_bt_cmd_connection_get_security_status_t cmd_connection_get_security_status; + sl_bt_cmd_connection_set_data_length_t cmd_connection_set_data_length; + sl_bt_cmd_connection_read_statistics_t cmd_connection_read_statistics; + sl_bt_cmd_connection_get_scheduling_details_t cmd_connection_get_scheduling_details; + sl_bt_cmd_connection_close_t cmd_connection_close; + sl_bt_cmd_connection_forcefully_close_t cmd_connection_forcefully_close; + sl_bt_cmd_connection_get_rssi_t cmd_connection_get_rssi; + sl_bt_cmd_gatt_set_max_mtu_t cmd_gatt_set_max_mtu; + sl_bt_cmd_gatt_discover_primary_services_t cmd_gatt_discover_primary_services; + sl_bt_cmd_gatt_discover_primary_services_by_uuid_t cmd_gatt_discover_primary_services_by_uuid; + sl_bt_cmd_gatt_find_included_services_t cmd_gatt_find_included_services; + sl_bt_cmd_gatt_discover_characteristics_t cmd_gatt_discover_characteristics; + sl_bt_cmd_gatt_discover_characteristics_by_uuid_t cmd_gatt_discover_characteristics_by_uuid; + sl_bt_cmd_gatt_discover_descriptors_t cmd_gatt_discover_descriptors; + sl_bt_cmd_gatt_discover_characteristic_descriptors_t cmd_gatt_discover_characteristic_descriptors; + sl_bt_cmd_gatt_set_characteristic_notification_t cmd_gatt_set_characteristic_notification; + sl_bt_cmd_gatt_send_characteristic_confirmation_t cmd_gatt_send_characteristic_confirmation; + sl_bt_cmd_gatt_read_characteristic_value_t cmd_gatt_read_characteristic_value; + sl_bt_cmd_gatt_read_characteristic_value_from_offset_t cmd_gatt_read_characteristic_value_from_offset; + sl_bt_cmd_gatt_read_multiple_characteristic_values_t cmd_gatt_read_multiple_characteristic_values; + sl_bt_cmd_gatt_read_characteristic_value_by_uuid_t cmd_gatt_read_characteristic_value_by_uuid; + sl_bt_cmd_gatt_write_characteristic_value_t cmd_gatt_write_characteristic_value; + sl_bt_cmd_gatt_write_characteristic_value_without_response_t cmd_gatt_write_characteristic_value_without_response; + sl_bt_cmd_gatt_prepare_characteristic_value_write_t cmd_gatt_prepare_characteristic_value_write; + sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_t cmd_gatt_prepare_characteristic_value_reliable_write; + sl_bt_cmd_gatt_execute_characteristic_value_write_t cmd_gatt_execute_characteristic_value_write; + sl_bt_cmd_gatt_read_descriptor_value_t cmd_gatt_read_descriptor_value; + sl_bt_cmd_gatt_write_descriptor_value_t cmd_gatt_write_descriptor_value; + sl_bt_cmd_gattdb_add_service_t cmd_gattdb_add_service; + sl_bt_cmd_gattdb_remove_service_t cmd_gattdb_remove_service; + sl_bt_cmd_gattdb_add_included_service_t cmd_gattdb_add_included_service; + sl_bt_cmd_gattdb_remove_included_service_t cmd_gattdb_remove_included_service; + sl_bt_cmd_gattdb_add_uuid16_characteristic_t cmd_gattdb_add_uuid16_characteristic; + sl_bt_cmd_gattdb_add_uuid128_characteristic_t cmd_gattdb_add_uuid128_characteristic; + sl_bt_cmd_gattdb_remove_characteristic_t cmd_gattdb_remove_characteristic; + sl_bt_cmd_gattdb_add_uuid16_descriptor_t cmd_gattdb_add_uuid16_descriptor; + sl_bt_cmd_gattdb_add_uuid128_descriptor_t cmd_gattdb_add_uuid128_descriptor; + sl_bt_cmd_gattdb_remove_descriptor_t cmd_gattdb_remove_descriptor; + sl_bt_cmd_gattdb_start_service_t cmd_gattdb_start_service; + sl_bt_cmd_gattdb_stop_service_t cmd_gattdb_stop_service; + sl_bt_cmd_gattdb_start_characteristic_t cmd_gattdb_start_characteristic; + sl_bt_cmd_gattdb_stop_characteristic_t cmd_gattdb_stop_characteristic; + sl_bt_cmd_gattdb_commit_t cmd_gattdb_commit; + sl_bt_cmd_gattdb_abort_t cmd_gattdb_abort; + sl_bt_cmd_gatt_server_set_max_mtu_t cmd_gatt_server_set_max_mtu; + sl_bt_cmd_gatt_server_get_mtu_t cmd_gatt_server_get_mtu; + sl_bt_cmd_gatt_server_find_attribute_t cmd_gatt_server_find_attribute; + sl_bt_cmd_gatt_server_read_attribute_value_t cmd_gatt_server_read_attribute_value; + sl_bt_cmd_gatt_server_read_attribute_type_t cmd_gatt_server_read_attribute_type; + sl_bt_cmd_gatt_server_write_attribute_value_t cmd_gatt_server_write_attribute_value; + sl_bt_cmd_gatt_server_send_user_read_response_t cmd_gatt_server_send_user_read_response; + sl_bt_cmd_gatt_server_send_user_write_response_t cmd_gatt_server_send_user_write_response; + sl_bt_cmd_gatt_server_send_notification_t cmd_gatt_server_send_notification; + sl_bt_cmd_gatt_server_send_indication_t cmd_gatt_server_send_indication; + sl_bt_cmd_gatt_server_notify_all_t cmd_gatt_server_notify_all; + sl_bt_cmd_gatt_server_read_client_configuration_t cmd_gatt_server_read_client_configuration; + sl_bt_cmd_gatt_server_send_user_prepare_write_response_t cmd_gatt_server_send_user_prepare_write_response; + sl_bt_cmd_gatt_server_set_capabilities_t cmd_gatt_server_set_capabilities; + sl_bt_cmd_gatt_server_enable_capabilities_t cmd_gatt_server_enable_capabilities; + sl_bt_cmd_gatt_server_disable_capabilities_t cmd_gatt_server_disable_capabilities; + sl_bt_cmd_gatt_server_read_client_supported_features_t cmd_gatt_server_read_client_supported_features; + sl_bt_cmd_nvm_save_t cmd_nvm_save; + sl_bt_cmd_nvm_load_t cmd_nvm_load; + sl_bt_cmd_nvm_erase_t cmd_nvm_erase; + sl_bt_cmd_test_dtm_tx_v4_t cmd_test_dtm_tx_v4; + sl_bt_cmd_test_dtm_tx_cw_t cmd_test_dtm_tx_cw; + sl_bt_cmd_test_dtm_rx_t cmd_test_dtm_rx; + sl_bt_cmd_sm_configure_t cmd_sm_configure; + sl_bt_cmd_sm_set_minimum_key_size_t cmd_sm_set_minimum_key_size; + sl_bt_cmd_sm_add_to_whitelist_t cmd_sm_add_to_whitelist; + sl_bt_cmd_sm_store_bonding_configuration_t cmd_sm_store_bonding_configuration; + sl_bt_cmd_sm_set_bondable_mode_t cmd_sm_set_bondable_mode; + sl_bt_cmd_sm_set_passkey_t cmd_sm_set_passkey; + sl_bt_cmd_sm_increase_security_t cmd_sm_increase_security; + sl_bt_cmd_sm_enter_passkey_t cmd_sm_enter_passkey; + sl_bt_cmd_sm_passkey_confirm_t cmd_sm_passkey_confirm; + sl_bt_cmd_sm_bonding_confirm_t cmd_sm_bonding_confirm; + sl_bt_cmd_sm_delete_bonding_t cmd_sm_delete_bonding; + sl_bt_cmd_sm_get_bonding_handles_t cmd_sm_get_bonding_handles; + sl_bt_cmd_sm_get_bonding_details_t cmd_sm_get_bonding_details; + sl_bt_cmd_sm_find_bonding_by_address_t cmd_sm_find_bonding_by_address; + sl_bt_cmd_sm_resolve_rpa_t cmd_sm_resolve_rpa; + sl_bt_cmd_sm_set_bonding_key_t cmd_sm_set_bonding_key; + sl_bt_cmd_sm_set_legacy_oob_t cmd_sm_set_legacy_oob; + sl_bt_cmd_sm_set_oob_t cmd_sm_set_oob; + sl_bt_cmd_sm_set_remote_oob_t cmd_sm_set_remote_oob; + sl_bt_cmd_sm_set_bonding_data_t cmd_sm_set_bonding_data; + sl_bt_cmd_external_bondingdb_set_data_t cmd_external_bondingdb_set_data; + sl_bt_cmd_resolving_list_add_device_by_bonding_t cmd_resolving_list_add_device_by_bonding; + sl_bt_cmd_resolving_list_add_device_by_address_t cmd_resolving_list_add_device_by_address; + sl_bt_cmd_resolving_list_remove_device_by_bonding_t cmd_resolving_list_remove_device_by_bonding; + sl_bt_cmd_resolving_list_remove_device_by_address_t cmd_resolving_list_remove_device_by_address; + sl_bt_cmd_accept_list_add_device_by_bonding_t cmd_accept_list_add_device_by_bonding; + sl_bt_cmd_accept_list_add_device_by_address_t cmd_accept_list_add_device_by_address; + sl_bt_cmd_accept_list_remove_device_by_bonding_t cmd_accept_list_remove_device_by_bonding; + sl_bt_cmd_accept_list_remove_device_by_address_t cmd_accept_list_remove_device_by_address; + sl_bt_cmd_ota_set_device_name_t cmd_ota_set_device_name; + sl_bt_cmd_ota_set_advertising_data_t cmd_ota_set_advertising_data; + sl_bt_cmd_ota_set_configuration_t cmd_ota_set_configuration; + sl_bt_cmd_ota_set_rf_path_t cmd_ota_set_rf_path; + sl_bt_cmd_coex_set_options_t cmd_coex_set_options; + sl_bt_cmd_coex_set_parameters_t cmd_coex_set_parameters; + sl_bt_cmd_coex_set_directional_priority_pulse_t cmd_coex_set_directional_priority_pulse; + sl_bt_cmd_coex_get_counters_t cmd_coex_get_counters; + sl_bt_cmd_cs_security_enable_t cmd_cs_security_enable; + sl_bt_cmd_cs_set_default_settings_t cmd_cs_set_default_settings; + sl_bt_cmd_cs_create_config_t cmd_cs_create_config; + sl_bt_cmd_cs_remove_config_t cmd_cs_remove_config; + sl_bt_cmd_cs_set_channel_classification_t cmd_cs_set_channel_classification; + sl_bt_cmd_cs_set_procedure_parameters_t cmd_cs_set_procedure_parameters; + sl_bt_cmd_cs_procedure_enable_t cmd_cs_procedure_enable; + sl_bt_cmd_cs_set_antenna_configuration_t cmd_cs_set_antenna_configuration; + sl_bt_cmd_cs_test_start_t cmd_cs_test_start; + sl_bt_cmd_l2cap_open_le_channel_t cmd_l2cap_open_le_channel; + sl_bt_cmd_l2cap_send_le_channel_open_response_t cmd_l2cap_send_le_channel_open_response; + sl_bt_cmd_l2cap_channel_send_data_t cmd_l2cap_channel_send_data; + sl_bt_cmd_l2cap_channel_send_credit_t cmd_l2cap_channel_send_credit; + sl_bt_cmd_l2cap_close_channel_t cmd_l2cap_close_channel; + sl_bt_cmd_cte_transmitter_set_dtm_parameters_t cmd_cte_transmitter_set_dtm_parameters; + sl_bt_cmd_cte_transmitter_enable_connection_cte_t cmd_cte_transmitter_enable_connection_cte; + sl_bt_cmd_cte_transmitter_disable_connection_cte_t cmd_cte_transmitter_disable_connection_cte; + sl_bt_cmd_cte_transmitter_enable_connectionless_cte_t cmd_cte_transmitter_enable_connectionless_cte; + sl_bt_cmd_cte_transmitter_disable_connectionless_cte_t cmd_cte_transmitter_disable_connectionless_cte; + sl_bt_cmd_cte_transmitter_enable_silabs_cte_t cmd_cte_transmitter_enable_silabs_cte; + sl_bt_cmd_cte_transmitter_disable_silabs_cte_t cmd_cte_transmitter_disable_silabs_cte; + sl_bt_cmd_cte_receiver_set_dtm_parameters_t cmd_cte_receiver_set_dtm_parameters; + sl_bt_cmd_cte_receiver_set_sync_cte_type_t cmd_cte_receiver_set_sync_cte_type; + sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_t cmd_cte_receiver_set_default_sync_receive_parameters; + sl_bt_cmd_cte_receiver_set_sync_receive_parameters_t cmd_cte_receiver_set_sync_receive_parameters; + sl_bt_cmd_cte_receiver_configure_t cmd_cte_receiver_configure; + sl_bt_cmd_cte_receiver_enable_connection_cte_t cmd_cte_receiver_enable_connection_cte; + sl_bt_cmd_cte_receiver_disable_connection_cte_t cmd_cte_receiver_disable_connection_cte; + sl_bt_cmd_cte_receiver_enable_connectionless_cte_t cmd_cte_receiver_enable_connectionless_cte; + sl_bt_cmd_cte_receiver_disable_connectionless_cte_t cmd_cte_receiver_disable_connectionless_cte; + sl_bt_cmd_cte_receiver_enable_silabs_cte_t cmd_cte_receiver_enable_silabs_cte; + sl_bt_cmd_connection_analyzer_start_t cmd_connection_analyzer_start; + sl_bt_cmd_connection_analyzer_stop_t cmd_connection_analyzer_stop; + sl_bt_cmd_user_message_to_target_t cmd_user_message_to_target; + sl_bt_cmd_user_manage_event_filter_t cmd_user_manage_event_filter; + sl_bt_rsp_dfu_flash_set_address_t rsp_dfu_flash_set_address; + sl_bt_rsp_dfu_flash_upload_t rsp_dfu_flash_upload; + sl_bt_rsp_dfu_flash_upload_finish_t rsp_dfu_flash_upload_finish; + sl_bt_rsp_system_hello_t rsp_system_hello; + sl_bt_rsp_system_start_bluetooth_t rsp_system_start_bluetooth; + sl_bt_rsp_system_stop_bluetooth_t rsp_system_stop_bluetooth; + sl_bt_rsp_system_forcefully_stop_bluetooth_t rsp_system_forcefully_stop_bluetooth; + sl_bt_rsp_system_get_version_t rsp_system_get_version; + sl_bt_rsp_system_halt_t rsp_system_halt; + sl_bt_rsp_system_linklayer_configure_t rsp_system_linklayer_configure; + sl_bt_rsp_system_set_tx_power_t rsp_system_set_tx_power; + sl_bt_rsp_system_get_tx_power_setting_t rsp_system_get_tx_power_setting; + sl_bt_rsp_system_set_identity_address_t rsp_system_set_identity_address; + sl_bt_rsp_system_get_identity_address_t rsp_system_get_identity_address; + sl_bt_rsp_system_get_random_data_t rsp_system_get_random_data; + sl_bt_rsp_system_data_buffer_write_t rsp_system_data_buffer_write; + sl_bt_rsp_system_data_buffer_clear_t rsp_system_data_buffer_clear; + sl_bt_rsp_system_get_counters_t rsp_system_get_counters; + sl_bt_rsp_system_set_lazy_soft_timer_t rsp_system_set_lazy_soft_timer; + sl_bt_rsp_resource_get_status_t rsp_resource_get_status; + sl_bt_rsp_resource_set_report_threshold_t rsp_resource_set_report_threshold; + sl_bt_rsp_resource_enable_connection_tx_report_t rsp_resource_enable_connection_tx_report; + sl_bt_rsp_resource_get_connection_tx_status_t rsp_resource_get_connection_tx_status; + sl_bt_rsp_resource_disable_connection_tx_report_t rsp_resource_disable_connection_tx_report; + sl_bt_rsp_gap_set_privacy_mode_t rsp_gap_set_privacy_mode; + sl_bt_rsp_gap_set_data_channel_classification_t rsp_gap_set_data_channel_classification; + sl_bt_rsp_gap_enable_whitelisting_t rsp_gap_enable_whitelisting; + sl_bt_rsp_gap_set_identity_address_t rsp_gap_set_identity_address; + sl_bt_rsp_advertiser_create_set_t rsp_advertiser_create_set; + sl_bt_rsp_advertiser_configure_t rsp_advertiser_configure; + sl_bt_rsp_advertiser_set_timing_t rsp_advertiser_set_timing; + sl_bt_rsp_advertiser_set_channel_map_t rsp_advertiser_set_channel_map; + sl_bt_rsp_advertiser_set_tx_power_t rsp_advertiser_set_tx_power; + sl_bt_rsp_advertiser_set_report_scan_request_t rsp_advertiser_set_report_scan_request; + sl_bt_rsp_advertiser_set_random_address_t rsp_advertiser_set_random_address; + sl_bt_rsp_advertiser_clear_random_address_t rsp_advertiser_clear_random_address; + sl_bt_rsp_advertiser_stop_t rsp_advertiser_stop; + sl_bt_rsp_advertiser_delete_set_t rsp_advertiser_delete_set; + sl_bt_rsp_advertiser_set_phy_t rsp_advertiser_set_phy; + sl_bt_rsp_advertiser_set_configuration_t rsp_advertiser_set_configuration; + sl_bt_rsp_advertiser_clear_configuration_t rsp_advertiser_clear_configuration; + sl_bt_rsp_advertiser_set_data_t rsp_advertiser_set_data; + sl_bt_rsp_advertiser_set_long_data_t rsp_advertiser_set_long_data; + sl_bt_rsp_advertiser_start_t rsp_advertiser_start; + sl_bt_rsp_advertiser_start_periodic_advertising_t rsp_advertiser_start_periodic_advertising; + sl_bt_rsp_advertiser_stop_periodic_advertising_t rsp_advertiser_stop_periodic_advertising; + sl_bt_rsp_legacy_advertiser_set_data_t rsp_legacy_advertiser_set_data; + sl_bt_rsp_legacy_advertiser_generate_data_t rsp_legacy_advertiser_generate_data; + sl_bt_rsp_legacy_advertiser_start_t rsp_legacy_advertiser_start; + sl_bt_rsp_legacy_advertiser_start_directed_t rsp_legacy_advertiser_start_directed; + sl_bt_rsp_extended_advertiser_set_phy_t rsp_extended_advertiser_set_phy; + sl_bt_rsp_extended_advertiser_set_data_t rsp_extended_advertiser_set_data; + sl_bt_rsp_extended_advertiser_set_long_data_t rsp_extended_advertiser_set_long_data; + sl_bt_rsp_extended_advertiser_generate_data_t rsp_extended_advertiser_generate_data; + sl_bt_rsp_extended_advertiser_start_t rsp_extended_advertiser_start; + sl_bt_rsp_extended_advertiser_start_directed_t rsp_extended_advertiser_start_directed; + sl_bt_rsp_periodic_advertiser_set_data_t rsp_periodic_advertiser_set_data; + sl_bt_rsp_periodic_advertiser_set_long_data_t rsp_periodic_advertiser_set_long_data; + sl_bt_rsp_periodic_advertiser_start_t rsp_periodic_advertiser_start; + sl_bt_rsp_periodic_advertiser_stop_t rsp_periodic_advertiser_stop; + sl_bt_rsp_scanner_set_parameters_t rsp_scanner_set_parameters; + sl_bt_rsp_scanner_set_parameters_and_filter_t rsp_scanner_set_parameters_and_filter; + sl_bt_rsp_scanner_stop_t rsp_scanner_stop; + sl_bt_rsp_scanner_set_timing_t rsp_scanner_set_timing; + sl_bt_rsp_scanner_set_mode_t rsp_scanner_set_mode; + sl_bt_rsp_scanner_start_t rsp_scanner_start; + sl_bt_rsp_sync_set_parameters_t rsp_sync_set_parameters; + sl_bt_rsp_sync_open_t rsp_sync_open; + sl_bt_rsp_sync_set_reporting_mode_t rsp_sync_set_reporting_mode; + sl_bt_rsp_sync_update_sync_parameters_t rsp_sync_update_sync_parameters; + sl_bt_rsp_sync_close_t rsp_sync_close; + sl_bt_rsp_sync_scanner_set_sync_parameters_t rsp_sync_scanner_set_sync_parameters; + sl_bt_rsp_sync_scanner_open_t rsp_sync_scanner_open; + sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_t rsp_past_receiver_set_default_sync_receive_parameters; + sl_bt_rsp_past_receiver_set_sync_receive_parameters_t rsp_past_receiver_set_sync_receive_parameters; + sl_bt_rsp_advertiser_past_transfer_t rsp_advertiser_past_transfer; + sl_bt_rsp_sync_past_transfer_t rsp_sync_past_transfer; + sl_bt_rsp_pawr_sync_set_sync_subevents_t rsp_pawr_sync_set_sync_subevents; + sl_bt_rsp_pawr_sync_set_response_data_t rsp_pawr_sync_set_response_data; + sl_bt_rsp_pawr_advertiser_start_t rsp_pawr_advertiser_start; + sl_bt_rsp_pawr_advertiser_set_subevent_data_t rsp_pawr_advertiser_set_subevent_data; + sl_bt_rsp_pawr_advertiser_create_connection_t rsp_pawr_advertiser_create_connection; + sl_bt_rsp_pawr_advertiser_stop_t rsp_pawr_advertiser_stop; + sl_bt_rsp_connection_set_default_parameters_t rsp_connection_set_default_parameters; + sl_bt_rsp_connection_set_default_preferred_phy_t rsp_connection_set_default_preferred_phy; + sl_bt_rsp_connection_set_default_data_length_t rsp_connection_set_default_data_length; + sl_bt_rsp_connection_open_t rsp_connection_open; + sl_bt_rsp_connection_set_parameters_t rsp_connection_set_parameters; + sl_bt_rsp_connection_set_preferred_phy_t rsp_connection_set_preferred_phy; + sl_bt_rsp_connection_disable_slave_latency_t rsp_connection_disable_slave_latency; + sl_bt_rsp_connection_get_median_rssi_t rsp_connection_get_median_rssi; + sl_bt_rsp_connection_read_channel_map_t rsp_connection_read_channel_map; + sl_bt_rsp_connection_set_power_reporting_t rsp_connection_set_power_reporting; + sl_bt_rsp_connection_set_remote_power_reporting_t rsp_connection_set_remote_power_reporting; + sl_bt_rsp_connection_get_tx_power_t rsp_connection_get_tx_power; + sl_bt_rsp_connection_get_remote_tx_power_t rsp_connection_get_remote_tx_power; + sl_bt_rsp_connection_set_tx_power_t rsp_connection_set_tx_power; + sl_bt_rsp_connection_read_remote_used_features_t rsp_connection_read_remote_used_features; + sl_bt_rsp_connection_get_security_status_t rsp_connection_get_security_status; + sl_bt_rsp_connection_set_data_length_t rsp_connection_set_data_length; + sl_bt_rsp_connection_read_statistics_t rsp_connection_read_statistics; + sl_bt_rsp_connection_get_scheduling_details_t rsp_connection_get_scheduling_details; + sl_bt_rsp_connection_close_t rsp_connection_close; + sl_bt_rsp_connection_forcefully_close_t rsp_connection_forcefully_close; + sl_bt_rsp_connection_get_rssi_t rsp_connection_get_rssi; + sl_bt_rsp_gatt_set_max_mtu_t rsp_gatt_set_max_mtu; + sl_bt_rsp_gatt_discover_primary_services_t rsp_gatt_discover_primary_services; + sl_bt_rsp_gatt_discover_primary_services_by_uuid_t rsp_gatt_discover_primary_services_by_uuid; + sl_bt_rsp_gatt_find_included_services_t rsp_gatt_find_included_services; + sl_bt_rsp_gatt_discover_characteristics_t rsp_gatt_discover_characteristics; + sl_bt_rsp_gatt_discover_characteristics_by_uuid_t rsp_gatt_discover_characteristics_by_uuid; + sl_bt_rsp_gatt_discover_descriptors_t rsp_gatt_discover_descriptors; + sl_bt_rsp_gatt_discover_characteristic_descriptors_t rsp_gatt_discover_characteristic_descriptors; + sl_bt_rsp_gatt_set_characteristic_notification_t rsp_gatt_set_characteristic_notification; + sl_bt_rsp_gatt_send_characteristic_confirmation_t rsp_gatt_send_characteristic_confirmation; + sl_bt_rsp_gatt_read_characteristic_value_t rsp_gatt_read_characteristic_value; + sl_bt_rsp_gatt_read_characteristic_value_from_offset_t rsp_gatt_read_characteristic_value_from_offset; + sl_bt_rsp_gatt_read_multiple_characteristic_values_t rsp_gatt_read_multiple_characteristic_values; + sl_bt_rsp_gatt_read_characteristic_value_by_uuid_t rsp_gatt_read_characteristic_value_by_uuid; + sl_bt_rsp_gatt_write_characteristic_value_t rsp_gatt_write_characteristic_value; + sl_bt_rsp_gatt_write_characteristic_value_without_response_t rsp_gatt_write_characteristic_value_without_response; + sl_bt_rsp_gatt_prepare_characteristic_value_write_t rsp_gatt_prepare_characteristic_value_write; + sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_t rsp_gatt_prepare_characteristic_value_reliable_write; + sl_bt_rsp_gatt_execute_characteristic_value_write_t rsp_gatt_execute_characteristic_value_write; + sl_bt_rsp_gatt_read_descriptor_value_t rsp_gatt_read_descriptor_value; + sl_bt_rsp_gatt_write_descriptor_value_t rsp_gatt_write_descriptor_value; + sl_bt_rsp_gattdb_new_session_t rsp_gattdb_new_session; + sl_bt_rsp_gattdb_add_service_t rsp_gattdb_add_service; + sl_bt_rsp_gattdb_remove_service_t rsp_gattdb_remove_service; + sl_bt_rsp_gattdb_add_included_service_t rsp_gattdb_add_included_service; + sl_bt_rsp_gattdb_remove_included_service_t rsp_gattdb_remove_included_service; + sl_bt_rsp_gattdb_add_uuid16_characteristic_t rsp_gattdb_add_uuid16_characteristic; + sl_bt_rsp_gattdb_add_uuid128_characteristic_t rsp_gattdb_add_uuid128_characteristic; + sl_bt_rsp_gattdb_remove_characteristic_t rsp_gattdb_remove_characteristic; + sl_bt_rsp_gattdb_add_uuid16_descriptor_t rsp_gattdb_add_uuid16_descriptor; + sl_bt_rsp_gattdb_add_uuid128_descriptor_t rsp_gattdb_add_uuid128_descriptor; + sl_bt_rsp_gattdb_remove_descriptor_t rsp_gattdb_remove_descriptor; + sl_bt_rsp_gattdb_start_service_t rsp_gattdb_start_service; + sl_bt_rsp_gattdb_stop_service_t rsp_gattdb_stop_service; + sl_bt_rsp_gattdb_start_characteristic_t rsp_gattdb_start_characteristic; + sl_bt_rsp_gattdb_stop_characteristic_t rsp_gattdb_stop_characteristic; + sl_bt_rsp_gattdb_commit_t rsp_gattdb_commit; + sl_bt_rsp_gattdb_abort_t rsp_gattdb_abort; + sl_bt_rsp_gatt_server_set_max_mtu_t rsp_gatt_server_set_max_mtu; + sl_bt_rsp_gatt_server_get_mtu_t rsp_gatt_server_get_mtu; + sl_bt_rsp_gatt_server_find_attribute_t rsp_gatt_server_find_attribute; + sl_bt_rsp_gatt_server_read_attribute_value_t rsp_gatt_server_read_attribute_value; + sl_bt_rsp_gatt_server_read_attribute_type_t rsp_gatt_server_read_attribute_type; + sl_bt_rsp_gatt_server_write_attribute_value_t rsp_gatt_server_write_attribute_value; + sl_bt_rsp_gatt_server_send_user_read_response_t rsp_gatt_server_send_user_read_response; + sl_bt_rsp_gatt_server_send_user_write_response_t rsp_gatt_server_send_user_write_response; + sl_bt_rsp_gatt_server_send_notification_t rsp_gatt_server_send_notification; + sl_bt_rsp_gatt_server_send_indication_t rsp_gatt_server_send_indication; + sl_bt_rsp_gatt_server_notify_all_t rsp_gatt_server_notify_all; + sl_bt_rsp_gatt_server_read_client_configuration_t rsp_gatt_server_read_client_configuration; + sl_bt_rsp_gatt_server_send_user_prepare_write_response_t rsp_gatt_server_send_user_prepare_write_response; + sl_bt_rsp_gatt_server_set_capabilities_t rsp_gatt_server_set_capabilities; + sl_bt_rsp_gatt_server_enable_capabilities_t rsp_gatt_server_enable_capabilities; + sl_bt_rsp_gatt_server_disable_capabilities_t rsp_gatt_server_disable_capabilities; + sl_bt_rsp_gatt_server_get_enabled_capabilities_t rsp_gatt_server_get_enabled_capabilities; + sl_bt_rsp_gatt_server_read_client_supported_features_t rsp_gatt_server_read_client_supported_features; + sl_bt_rsp_nvm_save_t rsp_nvm_save; + sl_bt_rsp_nvm_load_t rsp_nvm_load; + sl_bt_rsp_nvm_erase_t rsp_nvm_erase; + sl_bt_rsp_nvm_erase_all_t rsp_nvm_erase_all; + sl_bt_rsp_test_dtm_tx_v4_t rsp_test_dtm_tx_v4; + sl_bt_rsp_test_dtm_tx_cw_t rsp_test_dtm_tx_cw; + sl_bt_rsp_test_dtm_rx_t rsp_test_dtm_rx; + sl_bt_rsp_test_dtm_end_t rsp_test_dtm_end; + sl_bt_rsp_sm_configure_t rsp_sm_configure; + sl_bt_rsp_sm_set_minimum_key_size_t rsp_sm_set_minimum_key_size; + sl_bt_rsp_sm_set_debug_mode_t rsp_sm_set_debug_mode; + sl_bt_rsp_sm_add_to_whitelist_t rsp_sm_add_to_whitelist; + sl_bt_rsp_sm_store_bonding_configuration_t rsp_sm_store_bonding_configuration; + sl_bt_rsp_sm_set_bondable_mode_t rsp_sm_set_bondable_mode; + sl_bt_rsp_sm_set_passkey_t rsp_sm_set_passkey; + sl_bt_rsp_sm_increase_security_t rsp_sm_increase_security; + sl_bt_rsp_sm_enter_passkey_t rsp_sm_enter_passkey; + sl_bt_rsp_sm_passkey_confirm_t rsp_sm_passkey_confirm; + sl_bt_rsp_sm_bonding_confirm_t rsp_sm_bonding_confirm; + sl_bt_rsp_sm_delete_bonding_t rsp_sm_delete_bonding; + sl_bt_rsp_sm_delete_bondings_t rsp_sm_delete_bondings; + sl_bt_rsp_sm_get_bonding_handles_t rsp_sm_get_bonding_handles; + sl_bt_rsp_sm_get_bonding_details_t rsp_sm_get_bonding_details; + sl_bt_rsp_sm_find_bonding_by_address_t rsp_sm_find_bonding_by_address; + sl_bt_rsp_sm_resolve_rpa_t rsp_sm_resolve_rpa; + sl_bt_rsp_sm_set_bonding_key_t rsp_sm_set_bonding_key; + sl_bt_rsp_sm_set_legacy_oob_t rsp_sm_set_legacy_oob; + sl_bt_rsp_sm_set_oob_t rsp_sm_set_oob; + sl_bt_rsp_sm_set_remote_oob_t rsp_sm_set_remote_oob; + sl_bt_rsp_sm_set_bonding_data_t rsp_sm_set_bonding_data; + sl_bt_rsp_external_bondingdb_set_data_t rsp_external_bondingdb_set_data; + sl_bt_rsp_resolving_list_add_device_by_bonding_t rsp_resolving_list_add_device_by_bonding; + sl_bt_rsp_resolving_list_add_device_by_address_t rsp_resolving_list_add_device_by_address; + sl_bt_rsp_resolving_list_remove_device_by_bonding_t rsp_resolving_list_remove_device_by_bonding; + sl_bt_rsp_resolving_list_remove_device_by_address_t rsp_resolving_list_remove_device_by_address; + sl_bt_rsp_resolving_list_remove_all_devices_t rsp_resolving_list_remove_all_devices; + sl_bt_rsp_accept_list_add_device_by_bonding_t rsp_accept_list_add_device_by_bonding; + sl_bt_rsp_accept_list_add_device_by_address_t rsp_accept_list_add_device_by_address; + sl_bt_rsp_accept_list_remove_device_by_bonding_t rsp_accept_list_remove_device_by_bonding; + sl_bt_rsp_accept_list_remove_device_by_address_t rsp_accept_list_remove_device_by_address; + sl_bt_rsp_accept_list_remove_all_devices_t rsp_accept_list_remove_all_devices; + sl_bt_rsp_ota_set_device_name_t rsp_ota_set_device_name; + sl_bt_rsp_ota_set_advertising_data_t rsp_ota_set_advertising_data; + sl_bt_rsp_ota_set_configuration_t rsp_ota_set_configuration; + sl_bt_rsp_ota_set_rf_path_t rsp_ota_set_rf_path; + sl_bt_rsp_coex_set_options_t rsp_coex_set_options; + sl_bt_rsp_coex_set_parameters_t rsp_coex_set_parameters; + sl_bt_rsp_coex_set_directional_priority_pulse_t rsp_coex_set_directional_priority_pulse; + sl_bt_rsp_coex_get_parameters_t rsp_coex_get_parameters; + sl_bt_rsp_coex_get_counters_t rsp_coex_get_counters; + sl_bt_rsp_cs_security_enable_t rsp_cs_security_enable; + sl_bt_rsp_cs_set_default_settings_t rsp_cs_set_default_settings; + sl_bt_rsp_cs_create_config_t rsp_cs_create_config; + sl_bt_rsp_cs_remove_config_t rsp_cs_remove_config; + sl_bt_rsp_cs_set_channel_classification_t rsp_cs_set_channel_classification; + sl_bt_rsp_cs_set_procedure_parameters_t rsp_cs_set_procedure_parameters; + sl_bt_rsp_cs_procedure_enable_t rsp_cs_procedure_enable; + sl_bt_rsp_cs_set_antenna_configuration_t rsp_cs_set_antenna_configuration; + sl_bt_rsp_cs_read_local_supported_capabilities_t rsp_cs_read_local_supported_capabilities; + sl_bt_rsp_cs_test_start_t rsp_cs_test_start; + sl_bt_rsp_l2cap_open_le_channel_t rsp_l2cap_open_le_channel; + sl_bt_rsp_l2cap_send_le_channel_open_response_t rsp_l2cap_send_le_channel_open_response; + sl_bt_rsp_l2cap_channel_send_data_t rsp_l2cap_channel_send_data; + sl_bt_rsp_l2cap_channel_send_credit_t rsp_l2cap_channel_send_credit; + sl_bt_rsp_l2cap_close_channel_t rsp_l2cap_close_channel; + sl_bt_rsp_cte_transmitter_set_dtm_parameters_t rsp_cte_transmitter_set_dtm_parameters; + sl_bt_rsp_cte_transmitter_clear_dtm_parameters_t rsp_cte_transmitter_clear_dtm_parameters; + sl_bt_rsp_cte_transmitter_enable_connection_cte_t rsp_cte_transmitter_enable_connection_cte; + sl_bt_rsp_cte_transmitter_disable_connection_cte_t rsp_cte_transmitter_disable_connection_cte; + sl_bt_rsp_cte_transmitter_enable_connectionless_cte_t rsp_cte_transmitter_enable_connectionless_cte; + sl_bt_rsp_cte_transmitter_disable_connectionless_cte_t rsp_cte_transmitter_disable_connectionless_cte; + sl_bt_rsp_cte_transmitter_enable_silabs_cte_t rsp_cte_transmitter_enable_silabs_cte; + sl_bt_rsp_cte_transmitter_disable_silabs_cte_t rsp_cte_transmitter_disable_silabs_cte; + sl_bt_rsp_cte_receiver_set_dtm_parameters_t rsp_cte_receiver_set_dtm_parameters; + sl_bt_rsp_cte_receiver_clear_dtm_parameters_t rsp_cte_receiver_clear_dtm_parameters; + sl_bt_rsp_cte_receiver_set_sync_cte_type_t rsp_cte_receiver_set_sync_cte_type; + sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_t rsp_cte_receiver_set_default_sync_receive_parameters; + sl_bt_rsp_cte_receiver_set_sync_receive_parameters_t rsp_cte_receiver_set_sync_receive_parameters; + sl_bt_rsp_cte_receiver_configure_t rsp_cte_receiver_configure; + sl_bt_rsp_cte_receiver_enable_connection_cte_t rsp_cte_receiver_enable_connection_cte; + sl_bt_rsp_cte_receiver_disable_connection_cte_t rsp_cte_receiver_disable_connection_cte; + sl_bt_rsp_cte_receiver_enable_connectionless_cte_t rsp_cte_receiver_enable_connectionless_cte; + sl_bt_rsp_cte_receiver_disable_connectionless_cte_t rsp_cte_receiver_disable_connectionless_cte; + sl_bt_rsp_cte_receiver_enable_silabs_cte_t rsp_cte_receiver_enable_silabs_cte; + sl_bt_rsp_cte_receiver_disable_silabs_cte_t rsp_cte_receiver_disable_silabs_cte; + sl_bt_rsp_connection_analyzer_start_t rsp_connection_analyzer_start; + sl_bt_rsp_connection_analyzer_stop_t rsp_connection_analyzer_stop; + sl_bt_rsp_user_message_to_target_t rsp_user_message_to_target; + sl_bt_rsp_user_manage_event_filter_t rsp_user_manage_event_filter; + sl_bt_evt_dfu_boot_t evt_dfu_boot; + sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; + sl_bt_evt_system_boot_t evt_system_boot; + sl_bt_evt_system_error_t evt_system_error; + sl_bt_evt_system_hardware_error_t evt_system_hardware_error; + sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; + sl_bt_evt_system_external_signal_t evt_system_external_signal; + sl_bt_evt_system_soft_timer_t evt_system_soft_timer; + sl_bt_evt_resource_status_t evt_resource_status; + sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; + sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; + sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; + sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; + sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; + sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; + sl_bt_evt_sync_opened_t evt_sync_opened; + sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; + sl_bt_evt_sync_data_t evt_sync_data; + sl_bt_evt_sync_closed_t evt_sync_closed; + sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; + sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; + sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; + sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; + sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; + sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; + sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; + sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; + sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; + sl_bt_evt_connection_opened_t evt_connection_opened; + sl_bt_evt_connection_parameters_t evt_connection_parameters; + sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; + sl_bt_evt_connection_phy_status_t evt_connection_phy_status; + sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; + sl_bt_evt_connection_tx_power_t evt_connection_tx_power; + sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; + sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; + sl_bt_evt_connection_data_length_t evt_connection_data_length; + sl_bt_evt_connection_statistics_t evt_connection_statistics; + sl_bt_evt_connection_closed_t evt_connection_closed; + sl_bt_evt_connection_rssi_t evt_connection_rssi; + sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; + sl_bt_evt_gatt_service_t evt_gatt_service; + sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; + sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; + sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; + sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; + sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; + sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; + sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; + sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; + sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; + sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; + sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; + sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; + sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; + sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; + sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; + sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; + sl_bt_evt_sm_bonded_t evt_sm_bonded; + sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; + sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; + sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; + sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; + sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; + sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; + sl_bt_evt_cs_config_complete_t evt_cs_config_complete; + sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; + sl_bt_evt_cs_result_t evt_cs_result; + sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; + sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; + sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; + sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; + sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; + sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; + sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; + sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; + sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; + sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; + sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; + sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; + sl_bt_evt_user_message_to_host_t evt_user_message_to_host; + uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; + } data; +}); + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h index 20d298f..f1f0f02 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h @@ -1,108 +1,108 @@ -/***************************************************************************//** - * @brief Bluetooth GATT database structure definition - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_GATT_DEF_H -#define SLI_BT_GATT_DEF_H - -#include -#include - -typedef struct { - uint16_t len; //size of buffer - uint8_t data[]; -} sli_bt_gattdb_value_t; - -typedef struct { - uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop - uint16_t max_len; //Maximum length of data in buffer - uint16_t len; //current size of data in buffer - uint8_t data[]; //size is max_len -} sli_bt_gattdb_attribute_chrvalue_t; - -typedef struct { - uint8_t flags; //client characteristic flags allowed 1-notification, 2-indication) - uint8_t clientconfig_index; // index to client config. -} sli_bt_gattdb_attribute_config_t; - -typedef struct { - uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop - uint16_t char_uuid; // characteristic UUID handle -} sli_bt_gattdb_attribute_characteristic_t; - -typedef struct { - uint16_t start; //Included Service Attribute Handle - uint16_t end; //End Group Handle -} sli_bt_gattdb_attribute_service_include_t; - -typedef struct { - uint16_t handle; - uint16_t uuid; - uint16_t permissions; //gatt_attribute_permission - uint16_t caps; // Capability bit flags - uint8_t datatype; //Just use uint8_t Do not use enum type, may cause compatibility troubles - uint8_t state; - union { - const sli_bt_gattdb_value_t *constdata; //generic constant data - sli_bt_gattdb_attribute_chrvalue_t *dynamicdata; //Modifiable data - sli_bt_gattdb_attribute_config_t configdata; - sli_bt_gattdb_attribute_characteristic_t characteristic; - sli_bt_gattdb_attribute_service_include_t service_include; - }; -} sli_bt_gattdb_attribute_t; - -struct sli_bt_gattdb_s { - const sli_bt_gattdb_attribute_t *attributes; - uint16_t attribute_table_size; - uint16_t attribute_num; - const uint16_t *uuid16; - uint16_t uuid16_table_size; - uint16_t uuid16_num; - const uint8_t *uuid128; - uint16_t uuid128_table_size; - uint16_t uuid128_num; - uint8_t num_ccfg; - uint16_t caps_mask; - uint16_t enabled_caps; -}; - -typedef struct sli_bt_gattdb_s sli_bt_gattdb_t; - -extern const sli_bt_gattdb_t *static_gattdb; - -/** - * @addtogroup dynamic_gatt_config - * - * Dynamic GATT database configuration. - */ - -/** - * Flag indicating GATT caching should be enabled. When enabled, a Generic - * Attribute Profile Service will be created in database if one doesn't exist. - **/ -#define SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING (0x01) - -/** - * Flag indicating the static database should be included if one exists. - */ -#define SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB (0X02) - -typedef struct { - uint32_t flags; -} sli_bt_gattdb_config_t; - -/** @} (end addtogroup dynamic_gatt_config) */ - -#endif +/***************************************************************************//** + * @brief Bluetooth GATT database structure definition + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_GATT_DEF_H +#define SLI_BT_GATT_DEF_H + +#include +#include + +typedef struct { + uint16_t len; //size of buffer + uint8_t data[]; +} sli_bt_gattdb_value_t; + +typedef struct { + uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop + uint16_t max_len; //Maximum length of data in buffer + uint16_t len; //current size of data in buffer + uint8_t data[]; //size is max_len +} sli_bt_gattdb_attribute_chrvalue_t; + +typedef struct { + uint8_t flags; //client characteristic flags allowed 1-notification, 2-indication) + uint8_t clientconfig_index; // index to client config. +} sli_bt_gattdb_attribute_config_t; + +typedef struct { + uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop + uint16_t char_uuid; // characteristic UUID handle +} sli_bt_gattdb_attribute_characteristic_t; + +typedef struct { + uint16_t start; //Included Service Attribute Handle + uint16_t end; //End Group Handle +} sli_bt_gattdb_attribute_service_include_t; + +typedef struct { + uint16_t handle; + uint16_t uuid; + uint16_t permissions; //gatt_attribute_permission + uint16_t caps; // Capability bit flags + uint8_t datatype; //Just use uint8_t Do not use enum type, may cause compatibility troubles + uint8_t state; + union { + const sli_bt_gattdb_value_t *constdata; //generic constant data + sli_bt_gattdb_attribute_chrvalue_t *dynamicdata; //Modifiable data + sli_bt_gattdb_attribute_config_t configdata; + sli_bt_gattdb_attribute_characteristic_t characteristic; + sli_bt_gattdb_attribute_service_include_t service_include; + }; +} sli_bt_gattdb_attribute_t; + +struct sli_bt_gattdb_s { + const sli_bt_gattdb_attribute_t *attributes; + uint16_t attribute_table_size; + uint16_t attribute_num; + const uint16_t *uuid16; + uint16_t uuid16_table_size; + uint16_t uuid16_num; + const uint8_t *uuid128; + uint16_t uuid128_table_size; + uint16_t uuid128_num; + uint8_t num_ccfg; + uint16_t caps_mask; + uint16_t enabled_caps; +}; + +typedef struct sli_bt_gattdb_s sli_bt_gattdb_t; + +extern const sli_bt_gattdb_t *static_gattdb; + +/** + * @addtogroup dynamic_gatt_config + * + * Dynamic GATT database configuration. + */ + +/** + * Flag indicating GATT caching should be enabled. When enabled, a Generic + * Attribute Profile Service will be created in database if one doesn't exist. + **/ +#define SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING (0x01) + +/** + * Flag indicating the static database should be included if one exists. + */ +#define SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB (0X02) + +typedef struct { + uint32_t flags; +} sli_bt_gattdb_config_t; + +/** @} (end addtogroup dynamic_gatt_config) */ + +#endif diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host.c b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host.c index 91cf4e7..e3ffea9 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host.c +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host.c @@ -1,289 +1,289 @@ -/***************************************************************************//** - * @brief Adaptation layer between host application and SL_BT_API protocol - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_bt_ncp_host.h" -#include "sl_status.h" - -// We only have bt and btmesh -#define SL_BGAPI_DEVICE_TYPES 2 - -bgapi_device_type_queue_t* device_event_queues[SL_BGAPI_DEVICE_TYPES] = { 0 }; -static size_t registered_devices_count = 0; - -sl_bt_msg_t _sl_bt_cmd_msg; -sl_bt_msg_t _sl_bt_rsp_msg; -sl_bt_msg_t *sl_bt_cmd_msg = &_sl_bt_cmd_msg; -sl_bt_msg_t *sl_bt_rsp_msg = &_sl_bt_rsp_msg; -void (*sl_bt_api_output)(uint32_t len1, uint8_t* data1); -int32_t (*sl_bt_api_input)(uint32_t len1, uint8_t* data1); -int32_t (*sl_bt_api_peek)(void); -uint8_t _sl_bt_queue_buffer[SL_BT_API_QUEUE_LEN * (SL_BGAPI_MSG_HEADER_LEN + SL_BGAPI_MAX_PAYLOAD_SIZE)]; - -bgapi_device_type_queue_t sl_bt_api_queue = { - sl_bgapi_dev_type_bt, - 0, // Write and read offsets start from zero. - 0, - (sl_bt_msg_t *)_sl_bt_queue_buffer, - SL_BT_API_QUEUE_LEN -}; - -sl_status_t sli_bgapi_register_device(bgapi_device_type_queue_t *queue) -{ - size_t i; - for (i = 0; i < SL_BGAPI_DEVICE_TYPES; i++) { - if (device_event_queues[i] == NULL) { - device_event_queues[i] = queue; - registered_devices_count++; - return SL_STATUS_OK; - } - } - return SL_STATUS_ALREADY_INITIALIZED; -} - -sl_status_t sl_bt_api_initialize(tx_func ofunc, rx_func ifunc) -{ - if (!ofunc || !ifunc) { - return SL_STATUS_INVALID_PARAMETER; - } - sl_bt_api_output = ofunc; - sl_bt_api_input = ifunc; - sl_bt_api_peek = NULL; - return sli_bgapi_register_device(&sl_bt_api_queue); -} - -sl_status_t sl_bt_api_initialize_nonblock(tx_func ofunc, rx_func ifunc, rx_peek_func pfunc) -{ - if (!ofunc || !ifunc || !pfunc) { - return SL_STATUS_INVALID_PARAMETER; - } - sl_bt_api_output = ofunc; - sl_bt_api_input = ifunc; - sl_bt_api_peek = pfunc; - return sli_bgapi_register_device(&sl_bt_api_queue); -} - -/** - * Check if the device queue has any pending events. - */ -bool sli_bgapi_device_queue_has_events(bgapi_device_type_queue_t *device_queue) -{ - if (device_queue->write_offset != device_queue->read_offset) { - return true; - } - return false; -} - -/** - * Check if any device type other than my_device_type has events waiting. - */ -bool sli_bgapi_other_events_in_queue(enum sl_bgapi_dev_types my_device_type) -{ - size_t i; - for (i = 0; i < registered_devices_count; i++) { - // Go through all registered device types that don't match the current device type. - if (device_event_queues[i] && device_event_queues[i]->device_type != my_device_type) { - if (sli_bgapi_device_queue_has_events(device_event_queues[i])) { - // Another device type has some events in the queue - return true; - } - } - } - return false; -} - -/** - * This function attempts to read a BGAPI event or response from the input data pipe. - * - * If there is no data, or a proper header cannot be recognized, returns NULL and - * discards any read data. - * - * If an event is found, it is put into the corresponding event queue, as indicated - * by the registered event queue struct device type. Then NULL is returned. - * - * If a response is found, it is copied into the response_buffer parameter. - * Then a pointer to response_buffer is returned. - */ -sl_bt_msg_t* sli_wait_for_bgapi_message(sl_bt_msg_t *response_buffer) -{ - uint32_t msg_length; - uint32_t header; - uint8_t *payload; - sl_bt_msg_t *packet_ptr, *retVal = NULL; - int ret; - size_t i; - bgapi_device_type_queue_t *queue = NULL; - //sync to header byte - ret = sl_bt_api_input(1, (uint8_t*)&header); - if (ret < 0) { - return 0; // Failed to read header byte - } - for (i = 0; i < SL_BGAPI_DEVICE_TYPES; i++) { - if ((device_event_queues[i] != NULL) - && ((header & 0x78) == device_event_queues[i]->device_type)) { - queue = device_event_queues[i]; - break; - } - } - if (queue == NULL) { - return 0; // Unrecognized device - } - ret = sl_bt_api_input(SL_BGAPI_MSG_HEADER_LEN - 1, &((uint8_t*)&header)[1]); - if (ret < 0) { - return 0; - } - - msg_length = SL_BT_MSG_LEN(header); - - if (msg_length > SL_BGAPI_MAX_PAYLOAD_SIZE) { - return 0; - } - - if ((header & 0xf8) == ( (uint32_t)(queue->device_type) | (uint32_t)sl_bgapi_msg_type_evt)) { - //received event - if (((queue->write_offset + 1) % queue->len == queue->read_offset)) { - // Would write over the next item we'd due to read - queue full! - if (msg_length) { - // Discard payload if it exists - uint8_t discard_buf[SL_BGAPI_MAX_PAYLOAD_SIZE]; - sl_bt_api_input(msg_length, discard_buf); - } - return 0; - } - packet_ptr = &queue->buffer[queue->write_offset]; - // Move write offset to next slot or wrap around to beginning. - queue->write_offset = (queue->write_offset + 1) % queue->len; - } else if ((header & 0xf8) == queue->device_type) {//response - // Note that in the case of a response we don't need to split it into two buffer types, - // because we can't have multiple pending commands and responses in parallel. - // Whoever sent the last command will wait for the response. - retVal = packet_ptr = response_buffer; - } else { - //fail - return 0; - } - packet_ptr->header = header; - payload = (uint8_t*)&packet_ptr->data.payload; - /** - * Read the payload data if required and store it after the header. - */ - if (msg_length) { - ret = sl_bt_api_input(msg_length, payload); - if (ret < 0) { - return 0; - } - } - - // Using retVal avoid double handling of event msg types in outer function. - // If retVal is non-null we got a response packet. If null, an event was placed - // in one of the event queues. - return retVal; -} - -bool sl_bt_event_pending(void) -{ - if (sli_bgapi_device_queue_has_events(&sl_bt_api_queue)) {//event is waiting in queue - return true; - } - - //something in uart waiting to be read - if (sl_bt_api_peek && sl_bt_api_peek()) { - return true; - } - - return false; -} - -/** - * Attempts to get an event that is already in the event queue, or an - * event or response from the input pipe. - * - * If BGAPI was initialized in blocking mode, this function will block - * until a valid event or response is found. - * - * Note that this function will return even when an event of a different - * type that was expected is found. It will return SL_STATUS_BUSY in that case. - * Otherwise we would be stuck until the event type we checked for arrives. - **/ -sl_status_t sli_bgapi_get_event(int block, sl_bt_msg_t *event, bgapi_device_type_queue_t *device_queue) -{ - sl_bt_msg_t *rsp; - while (1) { - // First check if we already have events waiting for us. - if (sli_bgapi_device_queue_has_events(device_queue)) { - // Copy event from queue to event parameter, then nudge the read offset forward - // by one message, or wrap around to beginning. - memcpy(event, &device_queue->buffer[device_queue->read_offset], sizeof(sl_bt_msg_t)); - device_queue->read_offset = (device_queue->read_offset + 1) % device_queue->len; - return SL_STATUS_OK; - } else if (sli_bgapi_other_events_in_queue(device_queue->device_type)) { - // If some other device type has messages, we need to yield here in order to let the - // events be processed. - return SL_STATUS_BUSY; - } - - //if not blocking and nothing in uart -> out - if (!block && sl_bt_api_peek && sl_bt_api_peek() == 0) { - return SL_STATUS_WOULD_BLOCK; - } - - //read more messages from device - if ( (rsp = sli_wait_for_bgapi_message(sl_bt_rsp_msg)) ) { - // Note that we copy the event to the event pointer here only if it is a response. - // Regular events are handled in the above blocks. - memcpy(event, rsp, sizeof(sl_bt_msg_t)); - return SL_STATUS_OK; - } - } -} - -sl_status_t sl_bt_wait_event(sl_bt_msg_t* event) -{ - return sli_bgapi_get_event(1, event, &sl_bt_api_queue); -} - -sl_status_t sl_bt_pop_event(sl_bt_msg_t* event) -{ - return sli_bgapi_get_event(0, event, &sl_bt_api_queue); -} - -/** - * This function will block until a response is found from the data pipe. - * Any events that arrive before the response will be put into their corresponding - * event queues. - */ -sl_bt_msg_t* sl_bt_wait_response(void) -{ - sl_bt_msg_t* rsp; - while (1) { - rsp = sli_wait_for_bgapi_message(sl_bt_rsp_msg); // Will return a valid pointer only if we got a response. - if (rsp) { - return rsp; - } - } -} - -void sl_bt_host_handle_command() -{ - //packet in sl_bt_cmd_msg is waiting for output - sl_bt_api_output(SL_BGAPI_MSG_HEADER_LEN + SL_BT_MSG_LEN(sl_bt_cmd_msg->header), (uint8_t*)sl_bt_cmd_msg); - sl_bt_wait_response(); -} - -void sl_bt_host_handle_command_noresponse() -{ - //packet in sl_bt_cmd_msg is waiting for output - sl_bt_api_output(SL_BGAPI_MSG_HEADER_LEN + SL_BT_MSG_LEN(sl_bt_cmd_msg->header), (uint8_t*)sl_bt_cmd_msg); -} +/***************************************************************************//** + * @brief Adaptation layer between host application and SL_BT_API protocol + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_bt_ncp_host.h" +#include "sl_status.h" + +// We only have bt and btmesh +#define SL_BGAPI_DEVICE_TYPES 2 + +bgapi_device_type_queue_t* device_event_queues[SL_BGAPI_DEVICE_TYPES] = { 0 }; +static size_t registered_devices_count = 0; + +sl_bt_msg_t _sl_bt_cmd_msg; +sl_bt_msg_t _sl_bt_rsp_msg; +sl_bt_msg_t *sl_bt_cmd_msg = &_sl_bt_cmd_msg; +sl_bt_msg_t *sl_bt_rsp_msg = &_sl_bt_rsp_msg; +void (*sl_bt_api_output)(uint32_t len1, uint8_t* data1); +int32_t (*sl_bt_api_input)(uint32_t len1, uint8_t* data1); +int32_t (*sl_bt_api_peek)(void); +uint8_t _sl_bt_queue_buffer[SL_BT_API_QUEUE_LEN * (SL_BGAPI_MSG_HEADER_LEN + SL_BGAPI_MAX_PAYLOAD_SIZE)]; + +bgapi_device_type_queue_t sl_bt_api_queue = { + sl_bgapi_dev_type_bt, + 0, // Write and read offsets start from zero. + 0, + (sl_bt_msg_t *)_sl_bt_queue_buffer, + SL_BT_API_QUEUE_LEN +}; + +sl_status_t sli_bgapi_register_device(bgapi_device_type_queue_t *queue) +{ + size_t i; + for (i = 0; i < SL_BGAPI_DEVICE_TYPES; i++) { + if (device_event_queues[i] == NULL) { + device_event_queues[i] = queue; + registered_devices_count++; + return SL_STATUS_OK; + } + } + return SL_STATUS_ALREADY_INITIALIZED; +} + +sl_status_t sl_bt_api_initialize(tx_func ofunc, rx_func ifunc) +{ + if (!ofunc || !ifunc) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_bt_api_output = ofunc; + sl_bt_api_input = ifunc; + sl_bt_api_peek = NULL; + return sli_bgapi_register_device(&sl_bt_api_queue); +} + +sl_status_t sl_bt_api_initialize_nonblock(tx_func ofunc, rx_func ifunc, rx_peek_func pfunc) +{ + if (!ofunc || !ifunc || !pfunc) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_bt_api_output = ofunc; + sl_bt_api_input = ifunc; + sl_bt_api_peek = pfunc; + return sli_bgapi_register_device(&sl_bt_api_queue); +} + +/** + * Check if the device queue has any pending events. + */ +bool sli_bgapi_device_queue_has_events(bgapi_device_type_queue_t *device_queue) +{ + if (device_queue->write_offset != device_queue->read_offset) { + return true; + } + return false; +} + +/** + * Check if any device type other than my_device_type has events waiting. + */ +bool sli_bgapi_other_events_in_queue(enum sl_bgapi_dev_types my_device_type) +{ + size_t i; + for (i = 0; i < registered_devices_count; i++) { + // Go through all registered device types that don't match the current device type. + if (device_event_queues[i] && device_event_queues[i]->device_type != my_device_type) { + if (sli_bgapi_device_queue_has_events(device_event_queues[i])) { + // Another device type has some events in the queue + return true; + } + } + } + return false; +} + +/** + * This function attempts to read a BGAPI event or response from the input data pipe. + * + * If there is no data, or a proper header cannot be recognized, returns NULL and + * discards any read data. + * + * If an event is found, it is put into the corresponding event queue, as indicated + * by the registered event queue struct device type. Then NULL is returned. + * + * If a response is found, it is copied into the response_buffer parameter. + * Then a pointer to response_buffer is returned. + */ +sl_bt_msg_t* sli_wait_for_bgapi_message(sl_bt_msg_t *response_buffer) +{ + uint32_t msg_length; + uint32_t header; + uint8_t *payload; + sl_bt_msg_t *packet_ptr, *retVal = NULL; + int ret; + size_t i; + bgapi_device_type_queue_t *queue = NULL; + //sync to header byte + ret = sl_bt_api_input(1, (uint8_t*)&header); + if (ret < 0) { + return 0; // Failed to read header byte + } + for (i = 0; i < SL_BGAPI_DEVICE_TYPES; i++) { + if ((device_event_queues[i] != NULL) + && ((header & 0x78) == device_event_queues[i]->device_type)) { + queue = device_event_queues[i]; + break; + } + } + if (queue == NULL) { + return 0; // Unrecognized device + } + ret = sl_bt_api_input(SL_BGAPI_MSG_HEADER_LEN - 1, &((uint8_t*)&header)[1]); + if (ret < 0) { + return 0; + } + + msg_length = SL_BT_MSG_LEN(header); + + if (msg_length > SL_BGAPI_MAX_PAYLOAD_SIZE) { + return 0; + } + + if ((header & 0xf8) == ( (uint32_t)(queue->device_type) | (uint32_t)sl_bgapi_msg_type_evt)) { + //received event + if (((queue->write_offset + 1) % queue->len == queue->read_offset)) { + // Would write over the next item we'd due to read - queue full! + if (msg_length) { + // Discard payload if it exists + uint8_t discard_buf[SL_BGAPI_MAX_PAYLOAD_SIZE]; + sl_bt_api_input(msg_length, discard_buf); + } + return 0; + } + packet_ptr = &queue->buffer[queue->write_offset]; + // Move write offset to next slot or wrap around to beginning. + queue->write_offset = (queue->write_offset + 1) % queue->len; + } else if ((header & 0xf8) == queue->device_type) {//response + // Note that in the case of a response we don't need to split it into two buffer types, + // because we can't have multiple pending commands and responses in parallel. + // Whoever sent the last command will wait for the response. + retVal = packet_ptr = response_buffer; + } else { + //fail + return 0; + } + packet_ptr->header = header; + payload = (uint8_t*)&packet_ptr->data.payload; + /** + * Read the payload data if required and store it after the header. + */ + if (msg_length) { + ret = sl_bt_api_input(msg_length, payload); + if (ret < 0) { + return 0; + } + } + + // Using retVal avoid double handling of event msg types in outer function. + // If retVal is non-null we got a response packet. If null, an event was placed + // in one of the event queues. + return retVal; +} + +bool sl_bt_event_pending(void) +{ + if (sli_bgapi_device_queue_has_events(&sl_bt_api_queue)) {//event is waiting in queue + return true; + } + + //something in uart waiting to be read + if (sl_bt_api_peek && sl_bt_api_peek()) { + return true; + } + + return false; +} + +/** + * Attempts to get an event that is already in the event queue, or an + * event or response from the input pipe. + * + * If BGAPI was initialized in blocking mode, this function will block + * until a valid event or response is found. + * + * Note that this function will return even when an event of a different + * type that was expected is found. It will return SL_STATUS_BUSY in that case. + * Otherwise we would be stuck until the event type we checked for arrives. + **/ +sl_status_t sli_bgapi_get_event(int block, sl_bt_msg_t *event, bgapi_device_type_queue_t *device_queue) +{ + sl_bt_msg_t *rsp; + while (1) { + // First check if we already have events waiting for us. + if (sli_bgapi_device_queue_has_events(device_queue)) { + // Copy event from queue to event parameter, then nudge the read offset forward + // by one message, or wrap around to beginning. + memcpy(event, &device_queue->buffer[device_queue->read_offset], sizeof(sl_bt_msg_t)); + device_queue->read_offset = (device_queue->read_offset + 1) % device_queue->len; + return SL_STATUS_OK; + } else if (sli_bgapi_other_events_in_queue(device_queue->device_type)) { + // If some other device type has messages, we need to yield here in order to let the + // events be processed. + return SL_STATUS_BUSY; + } + + //if not blocking and nothing in uart -> out + if (!block && sl_bt_api_peek && sl_bt_api_peek() == 0) { + return SL_STATUS_WOULD_BLOCK; + } + + //read more messages from device + if ( (rsp = sli_wait_for_bgapi_message(sl_bt_rsp_msg)) ) { + // Note that we copy the event to the event pointer here only if it is a response. + // Regular events are handled in the above blocks. + memcpy(event, rsp, sizeof(sl_bt_msg_t)); + return SL_STATUS_OK; + } + } +} + +sl_status_t sl_bt_wait_event(sl_bt_msg_t* event) +{ + return sli_bgapi_get_event(1, event, &sl_bt_api_queue); +} + +sl_status_t sl_bt_pop_event(sl_bt_msg_t* event) +{ + return sli_bgapi_get_event(0, event, &sl_bt_api_queue); +} + +/** + * This function will block until a response is found from the data pipe. + * Any events that arrive before the response will be put into their corresponding + * event queues. + */ +sl_bt_msg_t* sl_bt_wait_response(void) +{ + sl_bt_msg_t* rsp; + while (1) { + rsp = sli_wait_for_bgapi_message(sl_bt_rsp_msg); // Will return a valid pointer only if we got a response. + if (rsp) { + return rsp; + } + } +} + +void sl_bt_host_handle_command() +{ + //packet in sl_bt_cmd_msg is waiting for output + sl_bt_api_output(SL_BGAPI_MSG_HEADER_LEN + SL_BT_MSG_LEN(sl_bt_cmd_msg->header), (uint8_t*)sl_bt_cmd_msg); + sl_bt_wait_response(); +} + +void sl_bt_host_handle_command_noresponse() +{ + //packet in sl_bt_cmd_msg is waiting for output + sl_bt_api_output(SL_BGAPI_MSG_HEADER_LEN + SL_BT_MSG_LEN(sl_bt_cmd_msg->header), (uint8_t*)sl_bt_cmd_msg); +} diff --git a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host_api.c b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host_api.c index 7c25368..e1dc711 100644 --- a/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host_api.c +++ b/locator_host/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_ncp_host_api.c @@ -1,5281 +1,5281 @@ -/***************************************************************************//** - * @brief SL_BT_API commands for NCP host - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_bt_api.h" -#include "sli_bt_api.h" - -void sl_bt_host_handle_command(); -void sl_bt_host_handle_command_noresponse(); -extern sl_bt_msg_t *sl_bt_cmd_msg; -extern sl_bt_msg_t *sl_bt_rsp_msg; - -sl_status_t sl_bt_dfu_flash_set_address(uint32_t address) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_dfu_flash_set_address.address=address; - - cmd->header=sl_bt_cmd_dfu_flash_set_address_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_dfu_flash_set_address.result; - -} - -sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_dfu_flash_upload.data.len=data_len; - memcpy(cmd->data.cmd_dfu_flash_upload.data.data,data,data_len); - - cmd->header=sl_bt_cmd_dfu_flash_upload_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_dfu_flash_upload.result; - -} - -sl_status_t sl_bt_dfu_flash_upload_finish() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_dfu_flash_upload_finish_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_dfu_flash_upload_finish.result; - -} - -sl_status_t sl_bt_system_hello() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_hello_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_hello.result; - -} - -sl_status_t sl_bt_system_start_bluetooth() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_start_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_start_bluetooth.result; - -} - -sl_status_t sl_bt_system_stop_bluetooth() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_stop_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_stop_bluetooth.result; - -} - -sl_status_t sl_bt_system_forcefully_stop_bluetooth() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_forcefully_stop_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_forcefully_stop_bluetooth.result; - -} - -sl_status_t sl_bt_system_get_version(uint16_t *major, - uint16_t *minor, - uint16_t *patch, - uint16_t *build, - uint32_t *bootloader, - uint32_t *hash) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_get_version_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (major) { - *major = rsp->data.rsp_system_get_version.major; - } - if (minor) { - *minor = rsp->data.rsp_system_get_version.minor; - } - if (patch) { - *patch = rsp->data.rsp_system_get_version.patch; - } - if (build) { - *build = rsp->data.rsp_system_get_version.build; - } - if (bootloader) { - *bootloader = rsp->data.rsp_system_get_version.bootloader; - } - if (hash) { - *hash = rsp->data.rsp_system_get_version.hash; - } - return rsp->data.rsp_system_get_version.result; - -} - -void sl_bt_system_reset(uint8_t dfu) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - cmd->data.cmd_system_reset.dfu=dfu; - - cmd->header=sl_bt_cmd_system_reset_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command_noresponse(); -} - -sl_status_t sl_bt_system_halt(uint8_t halt) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_halt.halt=halt; - - cmd->header=sl_bt_cmd_system_halt_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_halt.result; - -} - -sl_status_t sl_bt_system_linklayer_configure(uint8_t key, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_linklayer_configure.key=key; - if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_system_linklayer_configure.data.len=data_len; - memcpy(cmd->data.cmd_system_linklayer_configure.data.data,data,data_len); - - cmd->header=sl_bt_cmd_system_linklayer_configure_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_linklayer_configure.result; - -} - -sl_status_t sl_bt_system_set_tx_power(int16_t min_power, - int16_t max_power, - int16_t *set_min, - int16_t *set_max) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_set_tx_power.min_power=min_power; - cmd->data.cmd_system_set_tx_power.max_power=max_power; - - cmd->header=sl_bt_cmd_system_set_tx_power_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (set_min) { - *set_min = rsp->data.rsp_system_set_tx_power.set_min; - } - if (set_max) { - *set_max = rsp->data.rsp_system_set_tx_power.set_max; - } - return rsp->data.rsp_system_set_tx_power.result; - -} - -sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, - int16_t *support_max, - int16_t *set_min, - int16_t *set_max, - int16_t *rf_path_gain) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_get_tx_power_setting_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (support_min) { - *support_min = rsp->data.rsp_system_get_tx_power_setting.support_min; - } - if (support_max) { - *support_max = rsp->data.rsp_system_get_tx_power_setting.support_max; - } - if (set_min) { - *set_min = rsp->data.rsp_system_get_tx_power_setting.set_min; - } - if (set_max) { - *set_max = rsp->data.rsp_system_get_tx_power_setting.set_max; - } - if (rf_path_gain) { - *rf_path_gain = rsp->data.rsp_system_get_tx_power_setting.rf_path_gain; - } - return rsp->data.rsp_system_get_tx_power_setting.result; - -} - -sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_system_set_identity_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_system_set_identity_address.type=type; - - cmd->header=sl_bt_cmd_system_set_identity_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_set_identity_address.result; - -} - -sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_get_identity_address_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (address) { - memcpy(address,&rsp->data.rsp_system_get_identity_address.address,sizeof(bd_addr)); - } - if (type) { - *type = rsp->data.rsp_system_get_identity_address.type; - } - return rsp->data.rsp_system_get_identity_address.result; - -} - -sl_status_t sl_bt_system_get_random_data(uint8_t length, - size_t max_data_size, - size_t *data_len, - uint8_t *data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_get_random_data.length=length; - - cmd->header=sl_bt_cmd_system_get_random_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (data_len) { - *data_len = rsp->data.rsp_system_get_random_data.data.len; - } - if (data && (rsp->data.rsp_system_get_random_data.data.len <= max_data_size)) { - memcpy(data,rsp->data.rsp_system_get_random_data.data.data,rsp->data.rsp_system_get_random_data.data.len); - } - return rsp->data.rsp_system_get_random_data.result; - -} - -sl_status_t sl_bt_system_data_buffer_write(size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_system_data_buffer_write.data.len=data_len; - memcpy(cmd->data.cmd_system_data_buffer_write.data.data,data,data_len); - - cmd->header=sl_bt_cmd_system_data_buffer_write_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_data_buffer_write.result; - -} - -sl_status_t sl_bt_system_data_buffer_clear() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_system_data_buffer_clear_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_data_buffer_clear.result; - -} - -sl_status_t sl_bt_system_get_counters(uint8_t reset, - uint16_t *tx_packets, - uint16_t *rx_packets, - uint16_t *crc_errors, - uint16_t *failures) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_get_counters.reset=reset; - - cmd->header=sl_bt_cmd_system_get_counters_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (tx_packets) { - *tx_packets = rsp->data.rsp_system_get_counters.tx_packets; - } - if (rx_packets) { - *rx_packets = rsp->data.rsp_system_get_counters.rx_packets; - } - if (crc_errors) { - *crc_errors = rsp->data.rsp_system_get_counters.crc_errors; - } - if (failures) { - *failures = rsp->data.rsp_system_get_counters.failures; - } - return rsp->data.rsp_system_get_counters.result; - -} - -sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, - uint32_t slack, - uint8_t handle, - uint8_t single_shot) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_system_set_lazy_soft_timer.time=time; - cmd->data.cmd_system_set_lazy_soft_timer.slack=slack; - cmd->data.cmd_system_set_lazy_soft_timer.handle=handle; - cmd->data.cmd_system_set_lazy_soft_timer.single_shot=single_shot; - - cmd->header=sl_bt_cmd_system_set_lazy_soft_timer_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_system_set_lazy_soft_timer.result; - -} - -sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, - uint32_t *free_bytes) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_resource_get_status_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (total_bytes) { - *total_bytes = rsp->data.rsp_resource_get_status.total_bytes; - } - if (free_bytes) { - *free_bytes = rsp->data.rsp_resource_get_status.free_bytes; - } - return rsp->data.rsp_resource_get_status.result; - -} - -sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_resource_set_report_threshold.low=low; - cmd->data.cmd_resource_set_report_threshold.high=high; - - cmd->header=sl_bt_cmd_resource_set_report_threshold_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resource_set_report_threshold.result; - -} - -sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_resource_enable_connection_tx_report.packet_count=packet_count; - - cmd->header=sl_bt_cmd_resource_enable_connection_tx_report_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resource_enable_connection_tx_report.result; - -} - -sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, - uint16_t *flags, - uint16_t *packet_count, - uint32_t *data_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_resource_get_connection_tx_status.connection=connection; - - cmd->header=sl_bt_cmd_resource_get_connection_tx_status_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (flags) { - *flags = rsp->data.rsp_resource_get_connection_tx_status.flags; - } - if (packet_count) { - *packet_count = rsp->data.rsp_resource_get_connection_tx_status.packet_count; - } - if (data_len) { - *data_len = rsp->data.rsp_resource_get_connection_tx_status.data_len; - } - return rsp->data.rsp_resource_get_connection_tx_status.result; - -} - -sl_status_t sl_bt_resource_disable_connection_tx_report() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_resource_disable_connection_tx_report_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resource_disable_connection_tx_report.result; - -} - -sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gap_set_privacy_mode.privacy=privacy; - cmd->data.cmd_gap_set_privacy_mode.interval=interval; - - cmd->header=sl_bt_cmd_gap_set_privacy_mode_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gap_set_privacy_mode.result; - -} - -sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, - const uint8_t* channel_map) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+channel_map_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gap_set_data_channel_classification.channel_map.len=channel_map_len; - memcpy(cmd->data.cmd_gap_set_data_channel_classification.channel_map.data,channel_map,channel_map_len); - - cmd->header=sl_bt_cmd_gap_set_data_channel_classification_id+(((1+channel_map_len)&0xff)<<8)+(((1+channel_map_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gap_set_data_channel_classification.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gap_enable_whitelisting.enable=enable; - - cmd->header=sl_bt_cmd_gap_enable_whitelisting_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gap_enable_whitelisting.result; - -} - -sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_gap_set_identity_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_gap_set_identity_address.addr_type=addr_type; - - cmd->header=sl_bt_cmd_gap_set_identity_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gap_set_identity_address.result; - -} - -sl_status_t sl_bt_advertiser_create_set(uint8_t *handle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_advertiser_create_set_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (handle) { - *handle = rsp->data.rsp_advertiser_create_set.handle; - } - return rsp->data.rsp_advertiser_create_set.result; - -} - -sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_configure.advertising_set=advertising_set; - cmd->data.cmd_advertiser_configure.flags=flags; - - cmd->header=sl_bt_cmd_advertiser_configure_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_configure.result; - -} - -sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, - uint32_t interval_min, - uint32_t interval_max, - uint16_t duration, - uint8_t maxevents) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_timing.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_timing.interval_min=interval_min; - cmd->data.cmd_advertiser_set_timing.interval_max=interval_max; - cmd->data.cmd_advertiser_set_timing.duration=duration; - cmd->data.cmd_advertiser_set_timing.maxevents=maxevents; - - cmd->header=sl_bt_cmd_advertiser_set_timing_id+(((12)&0xff)<<8)+(((12)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_timing.result; - -} - -sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, - uint8_t channel_map) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_channel_map.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_channel_map.channel_map=channel_map; - - cmd->header=sl_bt_cmd_advertiser_set_channel_map_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_channel_map.result; - -} - -sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, - int16_t power, - int16_t *set_power) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_tx_power.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_tx_power.power=power; - - cmd->header=sl_bt_cmd_advertiser_set_tx_power_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (set_power) { - *set_power = rsp->data.rsp_advertiser_set_tx_power.set_power; - } - return rsp->data.rsp_advertiser_set_tx_power.result; - -} - -sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, - uint8_t report_scan_req) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_report_scan_request.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_report_scan_request.report_scan_req=report_scan_req; - - cmd->header=sl_bt_cmd_advertiser_set_report_scan_request_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_report_scan_request.result; - -} - -sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, - uint8_t addr_type, - bd_addr address, - bd_addr *address_out) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_random_address.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_random_address.addr_type=addr_type; - memcpy(&cmd->data.cmd_advertiser_set_random_address.address,&address,sizeof(bd_addr)); - - cmd->header=sl_bt_cmd_advertiser_set_random_address_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (address_out) { - memcpy(address_out,&rsp->data.rsp_advertiser_set_random_address.address_out,sizeof(bd_addr)); - } - return rsp->data.rsp_advertiser_set_random_address.result; - -} - -sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_clear_random_address.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_advertiser_clear_random_address_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_clear_random_address.result; - -} - -sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_stop.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_stop.result; - -} - -sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_delete_set.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_advertiser_delete_set_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_delete_set.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_phy.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_phy.primary_phy=primary_phy; - cmd->data.cmd_advertiser_set_phy.secondary_phy=secondary_phy; - - cmd->header=sl_bt_cmd_advertiser_set_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_phy.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, - uint32_t configurations) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_configuration.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_configuration.configurations=configurations; - - cmd->header=sl_bt_cmd_advertiser_set_configuration_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_configuration.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, - uint32_t configurations) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_clear_configuration.advertising_set=advertising_set; - cmd->data.cmd_advertiser_clear_configuration.configurations=configurations; - - cmd->header=sl_bt_cmd_advertiser_clear_configuration_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_clear_configuration.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, - uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_data.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_data.packet_type=packet_type; - if ((3+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_advertiser_set_data.adv_data.len=adv_data_len; - memcpy(cmd->data.cmd_advertiser_set_data.adv_data.data,adv_data,adv_data_len); - - cmd->header=sl_bt_cmd_advertiser_set_data_id+(((3+adv_data_len)&0xff)<<8)+(((3+adv_data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_data.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, - uint8_t packet_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_set_long_data.advertising_set=advertising_set; - cmd->data.cmd_advertiser_set_long_data.packet_type=packet_type; - - cmd->header=sl_bt_cmd_advertiser_set_long_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_set_long_data.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, - uint8_t discover, - uint8_t connect) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_start.advertising_set=advertising_set; - cmd->data.cmd_advertiser_start.discover=discover; - cmd->data.cmd_advertiser_start.connect=connect; - - cmd->header=sl_bt_cmd_advertiser_start_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_start.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_start_periodic_advertising.advertising_set=advertising_set; - cmd->data.cmd_advertiser_start_periodic_advertising.interval_min=interval_min; - cmd->data.cmd_advertiser_start_periodic_advertising.interval_max=interval_max; - cmd->data.cmd_advertiser_start_periodic_advertising.flags=flags; - - cmd->header=sl_bt_cmd_advertiser_start_periodic_advertising_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_start_periodic_advertising.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_stop_periodic_advertising.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_advertiser_stop_periodic_advertising_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_stop_periodic_advertising.result; - -} - -sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, - uint8_t type, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_legacy_advertiser_set_data.advertising_set=advertising_set; - cmd->data.cmd_legacy_advertiser_set_data.type=type; - if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_legacy_advertiser_set_data.data.len=data_len; - memcpy(cmd->data.cmd_legacy_advertiser_set_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_legacy_advertiser_set_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_legacy_advertiser_set_data.result; - -} - -sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_legacy_advertiser_generate_data.advertising_set=advertising_set; - cmd->data.cmd_legacy_advertiser_generate_data.discover=discover; - - cmd->header=sl_bt_cmd_legacy_advertiser_generate_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_legacy_advertiser_generate_data.result; - -} - -sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, - uint8_t connect) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_legacy_advertiser_start.advertising_set=advertising_set; - cmd->data.cmd_legacy_advertiser_start.connect=connect; - - cmd->header=sl_bt_cmd_legacy_advertiser_start_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_legacy_advertiser_start.result; - -} - -sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - bd_addr peer_addr, - uint8_t peer_addr_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_legacy_advertiser_start_directed.advertising_set=advertising_set; - cmd->data.cmd_legacy_advertiser_start_directed.connect=connect; - memcpy(&cmd->data.cmd_legacy_advertiser_start_directed.peer_addr,&peer_addr,sizeof(bd_addr)); - cmd->data.cmd_legacy_advertiser_start_directed.peer_addr_type=peer_addr_type; - - cmd->header=sl_bt_cmd_legacy_advertiser_start_directed_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_legacy_advertiser_start_directed.result; - -} - -sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_set_phy.advertising_set=advertising_set; - cmd->data.cmd_extended_advertiser_set_phy.primary_phy=primary_phy; - cmd->data.cmd_extended_advertiser_set_phy.secondary_phy=secondary_phy; - - cmd->header=sl_bt_cmd_extended_advertiser_set_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_set_phy.result; - -} - -sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_set_data.advertising_set=advertising_set; - if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_extended_advertiser_set_data.data.len=data_len; - memcpy(cmd->data.cmd_extended_advertiser_set_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_extended_advertiser_set_data_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_set_data.result; - -} - -sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_set_long_data.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_extended_advertiser_set_long_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_set_long_data.result; - -} - -sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_generate_data.advertising_set=advertising_set; - cmd->data.cmd_extended_advertiser_generate_data.discover=discover; - - cmd->header=sl_bt_cmd_extended_advertiser_generate_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_generate_data.result; - -} - -sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, - uint8_t connect, - uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_start.advertising_set=advertising_set; - cmd->data.cmd_extended_advertiser_start.connect=connect; - cmd->data.cmd_extended_advertiser_start.flags=flags; - - cmd->header=sl_bt_cmd_extended_advertiser_start_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_start.result; - -} - -sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - uint32_t flags, - bd_addr peer_addr, - uint8_t peer_addr_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_extended_advertiser_start_directed.advertising_set=advertising_set; - cmd->data.cmd_extended_advertiser_start_directed.connect=connect; - cmd->data.cmd_extended_advertiser_start_directed.flags=flags; - memcpy(&cmd->data.cmd_extended_advertiser_start_directed.peer_addr,&peer_addr,sizeof(bd_addr)); - cmd->data.cmd_extended_advertiser_start_directed.peer_addr_type=peer_addr_type; - - cmd->header=sl_bt_cmd_extended_advertiser_start_directed_id+(((13)&0xff)<<8)+(((13)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_extended_advertiser_start_directed.result; - -} - -sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_periodic_advertiser_set_data.advertising_set=advertising_set; - if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_periodic_advertiser_set_data.data.len=data_len; - memcpy(cmd->data.cmd_periodic_advertiser_set_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_periodic_advertiser_set_data_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_periodic_advertiser_set_data.result; - -} - -sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_periodic_advertiser_set_long_data.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_periodic_advertiser_set_long_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_periodic_advertiser_set_long_data.result; - -} - -sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_periodic_advertiser_start.advertising_set=advertising_set; - cmd->data.cmd_periodic_advertiser_start.interval_min=interval_min; - cmd->data.cmd_periodic_advertiser_start.interval_max=interval_max; - cmd->data.cmd_periodic_advertiser_start.flags=flags; - - cmd->header=sl_bt_cmd_periodic_advertiser_start_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_periodic_advertiser_start.result; - -} - -sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_periodic_advertiser_stop.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_periodic_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_periodic_advertiser_stop.result; - -} - -sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, - uint16_t interval, - uint16_t window) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_scanner_set_parameters.mode=mode; - cmd->data.cmd_scanner_set_parameters.interval=interval; - cmd->data.cmd_scanner_set_parameters.window=window; - - cmd->header=sl_bt_cmd_scanner_set_parameters_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_set_parameters.result; - -} - -sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, - uint16_t interval, - uint16_t window, - uint32_t flags, - uint8_t filter_policy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_scanner_set_parameters_and_filter.mode=mode; - cmd->data.cmd_scanner_set_parameters_and_filter.interval=interval; - cmd->data.cmd_scanner_set_parameters_and_filter.window=window; - cmd->data.cmd_scanner_set_parameters_and_filter.flags=flags; - cmd->data.cmd_scanner_set_parameters_and_filter.filter_policy=filter_policy; - - cmd->header=sl_bt_cmd_scanner_set_parameters_and_filter_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_set_parameters_and_filter.result; - -} - -sl_status_t sl_bt_scanner_stop() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_scanner_stop_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_stop.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, - uint16_t scan_interval, - uint16_t scan_window) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_scanner_set_timing.phys=phys; - cmd->data.cmd_scanner_set_timing.scan_interval=scan_interval; - cmd->data.cmd_scanner_set_timing.scan_window=scan_window; - - cmd->header=sl_bt_cmd_scanner_set_timing_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_set_timing.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_scanner_set_mode.phys=phys; - cmd->data.cmd_scanner_set_mode.scan_mode=scan_mode; - - cmd->header=sl_bt_cmd_scanner_set_mode_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_set_mode.result; - -} - -sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_scanner_start.scanning_phy=scanning_phy; - cmd->data.cmd_scanner_start.discover_mode=discover_mode; - - cmd->header=sl_bt_cmd_scanner_start_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_scanner_start.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, - uint16_t timeout, - uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_set_parameters.skip=skip; - cmd->data.cmd_sync_set_parameters.timeout=timeout; - cmd->data.cmd_sync_set_parameters.flags=flags; - - cmd->header=sl_bt_cmd_sync_set_parameters_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_set_parameters.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_sync_open.address,&address,sizeof(bd_addr)); - cmd->data.cmd_sync_open.address_type=address_type; - cmd->data.cmd_sync_open.adv_sid=adv_sid; - - cmd->header=sl_bt_cmd_sync_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sync) { - *sync = rsp->data.rsp_sync_open.sync; - } - return rsp->data.rsp_sync_open.result; - -} - -sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_set_reporting_mode.sync=sync; - cmd->data.cmd_sync_set_reporting_mode.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_sync_set_reporting_mode_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_set_reporting_mode.result; - -} - -sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, - uint16_t skip, - uint16_t timeout) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_update_sync_parameters.sync=sync; - cmd->data.cmd_sync_update_sync_parameters.skip=skip; - cmd->data.cmd_sync_update_sync_parameters.timeout=timeout; - - cmd->header=sl_bt_cmd_sync_update_sync_parameters_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_update_sync_parameters.result; - -} - -sl_status_t sl_bt_sync_close(uint16_t sync) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_close.sync=sync; - - cmd->header=sl_bt_cmd_sync_close_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_close.result; - -} - -sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_scanner_set_sync_parameters.skip=skip; - cmd->data.cmd_sync_scanner_set_sync_parameters.timeout=timeout; - cmd->data.cmd_sync_scanner_set_sync_parameters.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_sync_scanner_set_sync_parameters_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_scanner_set_sync_parameters.result; - -} - -sl_status_t sl_bt_sync_scanner_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_sync_scanner_open.address,&address,sizeof(bd_addr)); - cmd->data.cmd_sync_scanner_open.address_type=address_type; - cmd->data.cmd_sync_scanner_open.adv_sid=adv_sid; - - cmd->header=sl_bt_cmd_sync_scanner_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sync) { - *sync = rsp->data.rsp_sync_scanner_open.sync; - } - return rsp->data.rsp_sync_scanner_open.result; - -} - -sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.mode=mode; - cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.skip=skip; - cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.timeout=timeout; - cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_past_receiver_set_default_sync_receive_parameters.result; - -} - -sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_past_receiver_set_sync_receive_parameters.connection=connection; - cmd->data.cmd_past_receiver_set_sync_receive_parameters.mode=mode; - cmd->data.cmd_past_receiver_set_sync_receive_parameters.skip=skip; - cmd->data.cmd_past_receiver_set_sync_receive_parameters.timeout=timeout; - cmd->data.cmd_past_receiver_set_sync_receive_parameters.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_past_receiver_set_sync_receive_parameters_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_past_receiver_set_sync_receive_parameters.result; - -} - -sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, - uint16_t service_data, - uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_advertiser_past_transfer.connection=connection; - cmd->data.cmd_advertiser_past_transfer.service_data=service_data; - cmd->data.cmd_advertiser_past_transfer.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_advertiser_past_transfer_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_advertiser_past_transfer.result; - -} - -sl_status_t sl_bt_sync_past_transfer(uint8_t connection, - uint16_t service_data, - uint16_t sync) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sync_past_transfer.connection=connection; - cmd->data.cmd_sync_past_transfer.service_data=service_data; - cmd->data.cmd_sync_past_transfer.sync=sync; - - cmd->header=sl_bt_cmd_sync_past_transfer_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sync_past_transfer.result; - -} - -sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, - size_t subevents_len, - const uint8_t* subevents) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_sync_set_sync_subevents.sync=sync; - if ((3+subevents_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_pawr_sync_set_sync_subevents.subevents.len=subevents_len; - memcpy(cmd->data.cmd_pawr_sync_set_sync_subevents.subevents.data,subevents,subevents_len); - - cmd->header=sl_bt_cmd_pawr_sync_set_sync_subevents_id+(((3+subevents_len)&0xff)<<8)+(((3+subevents_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_pawr_sync_set_sync_subevents.result; - -} - -sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, - uint16_t request_event, - uint8_t request_subevent, - uint8_t response_subevent, - uint8_t response_slot, - size_t response_data_len, - const uint8_t* response_data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_sync_set_response_data.sync=sync; - cmd->data.cmd_pawr_sync_set_response_data.request_event=request_event; - cmd->data.cmd_pawr_sync_set_response_data.request_subevent=request_subevent; - cmd->data.cmd_pawr_sync_set_response_data.response_subevent=response_subevent; - cmd->data.cmd_pawr_sync_set_response_data.response_slot=response_slot; - if ((8+response_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_pawr_sync_set_response_data.response_data.len=response_data_len; - memcpy(cmd->data.cmd_pawr_sync_set_response_data.response_data.data,response_data,response_data_len); - - cmd->header=sl_bt_cmd_pawr_sync_set_response_data_id+(((8+response_data_len)&0xff)<<8)+(((8+response_data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_pawr_sync_set_response_data.result; - -} - -sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags, - uint8_t num_subevents, - uint8_t subevent_interval, - uint8_t response_slot_delay, - uint8_t response_slot_spacing, - uint8_t response_slots) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_advertiser_start.advertising_set=advertising_set; - cmd->data.cmd_pawr_advertiser_start.interval_min=interval_min; - cmd->data.cmd_pawr_advertiser_start.interval_max=interval_max; - cmd->data.cmd_pawr_advertiser_start.flags=flags; - cmd->data.cmd_pawr_advertiser_start.num_subevents=num_subevents; - cmd->data.cmd_pawr_advertiser_start.subevent_interval=subevent_interval; - cmd->data.cmd_pawr_advertiser_start.response_slot_delay=response_slot_delay; - cmd->data.cmd_pawr_advertiser_start.response_slot_spacing=response_slot_spacing; - cmd->data.cmd_pawr_advertiser_start.response_slots=response_slots; - - cmd->header=sl_bt_cmd_pawr_advertiser_start_id+(((14)&0xff)<<8)+(((14)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_pawr_advertiser_start.result; - -} - -sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, - uint8_t subevent, - uint8_t response_slot_start, - uint8_t response_slot_count, - size_t adv_data_len, - const uint8_t* adv_data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_advertiser_set_subevent_data.advertising_set=advertising_set; - cmd->data.cmd_pawr_advertiser_set_subevent_data.subevent=subevent; - cmd->data.cmd_pawr_advertiser_set_subevent_data.response_slot_start=response_slot_start; - cmd->data.cmd_pawr_advertiser_set_subevent_data.response_slot_count=response_slot_count; - if ((5+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_pawr_advertiser_set_subevent_data.adv_data.len=adv_data_len; - memcpy(cmd->data.cmd_pawr_advertiser_set_subevent_data.adv_data.data,adv_data,adv_data_len); - - cmd->header=sl_bt_cmd_pawr_advertiser_set_subevent_data_id+(((5+adv_data_len)&0xff)<<8)+(((5+adv_data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_pawr_advertiser_set_subevent_data.result; - -} - -sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, - uint8_t subevent, - bd_addr address, - uint8_t address_type, - uint8_t *connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_advertiser_create_connection.advertising_set=advertising_set; - cmd->data.cmd_pawr_advertiser_create_connection.subevent=subevent; - memcpy(&cmd->data.cmd_pawr_advertiser_create_connection.address,&address,sizeof(bd_addr)); - cmd->data.cmd_pawr_advertiser_create_connection.address_type=address_type; - - cmd->header=sl_bt_cmd_pawr_advertiser_create_connection_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (connection) { - *connection = rsp->data.rsp_pawr_advertiser_create_connection.connection; - } - return rsp->data.rsp_pawr_advertiser_create_connection.result; - -} - -sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_pawr_advertiser_stop.advertising_set=advertising_set; - - cmd->header=sl_bt_cmd_pawr_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_pawr_advertiser_stop.result; - -} - -sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_default_parameters.min_interval=min_interval; - cmd->data.cmd_connection_set_default_parameters.max_interval=max_interval; - cmd->data.cmd_connection_set_default_parameters.latency=latency; - cmd->data.cmd_connection_set_default_parameters.timeout=timeout; - cmd->data.cmd_connection_set_default_parameters.min_ce_length=min_ce_length; - cmd->data.cmd_connection_set_default_parameters.max_ce_length=max_ce_length; - - cmd->header=sl_bt_cmd_connection_set_default_parameters_id+(((12)&0xff)<<8)+(((12)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_default_parameters.result; - -} - -sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, - uint8_t accepted_phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_default_preferred_phy.preferred_phy=preferred_phy; - cmd->data.cmd_connection_set_default_preferred_phy.accepted_phy=accepted_phy; - - cmd->header=sl_bt_cmd_connection_set_default_preferred_phy_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_default_preferred_phy.result; - -} - -sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_default_data_length.tx_data_len=tx_data_len; - - cmd->header=sl_bt_cmd_connection_set_default_data_length_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_default_data_length.result; - -} - -sl_status_t sl_bt_connection_open(bd_addr address, - uint8_t address_type, - uint8_t initiating_phy, - uint8_t *connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_connection_open.address,&address,sizeof(bd_addr)); - cmd->data.cmd_connection_open.address_type=address_type; - cmd->data.cmd_connection_open.initiating_phy=initiating_phy; - - cmd->header=sl_bt_cmd_connection_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (connection) { - *connection = rsp->data.rsp_connection_open.connection; - } - return rsp->data.rsp_connection_open.result; - -} - -sl_status_t sl_bt_connection_set_parameters(uint8_t connection, - uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_parameters.connection=connection; - cmd->data.cmd_connection_set_parameters.min_interval=min_interval; - cmd->data.cmd_connection_set_parameters.max_interval=max_interval; - cmd->data.cmd_connection_set_parameters.latency=latency; - cmd->data.cmd_connection_set_parameters.timeout=timeout; - cmd->data.cmd_connection_set_parameters.min_ce_length=min_ce_length; - cmd->data.cmd_connection_set_parameters.max_ce_length=max_ce_length; - - cmd->header=sl_bt_cmd_connection_set_parameters_id+(((13)&0xff)<<8)+(((13)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_parameters.result; - -} - -sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, - uint8_t preferred_phy, - uint8_t accepted_phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_preferred_phy.connection=connection; - cmd->data.cmd_connection_set_preferred_phy.preferred_phy=preferred_phy; - cmd->data.cmd_connection_set_preferred_phy.accepted_phy=accepted_phy; - - cmd->header=sl_bt_cmd_connection_set_preferred_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_preferred_phy.result; - -} - -sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, - uint8_t disable) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_disable_slave_latency.connection=connection; - cmd->data.cmd_connection_disable_slave_latency.disable=disable; - - cmd->header=sl_bt_cmd_connection_disable_slave_latency_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_disable_slave_latency.result; - -} - -sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_median_rssi.connection=connection; - - cmd->header=sl_bt_cmd_connection_get_median_rssi_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (rssi) { - *rssi = rsp->data.rsp_connection_get_median_rssi.rssi; - } - return rsp->data.rsp_connection_get_median_rssi.result; - -} - -sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, - size_t max_channel_map_size, - size_t *channel_map_len, - uint8_t *channel_map) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_read_channel_map.connection=connection; - - cmd->header=sl_bt_cmd_connection_read_channel_map_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (channel_map_len) { - *channel_map_len = rsp->data.rsp_connection_read_channel_map.channel_map.len; - } - if (channel_map && (rsp->data.rsp_connection_read_channel_map.channel_map.len <= max_channel_map_size)) { - memcpy(channel_map,rsp->data.rsp_connection_read_channel_map.channel_map.data,rsp->data.rsp_connection_read_channel_map.channel_map.len); - } - return rsp->data.rsp_connection_read_channel_map.result; - -} - -sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, - uint8_t mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_power_reporting.connection=connection; - cmd->data.cmd_connection_set_power_reporting.mode=mode; - - cmd->header=sl_bt_cmd_connection_set_power_reporting_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_power_reporting.result; - -} - -sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, - uint8_t mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_remote_power_reporting.connection=connection; - cmd->data.cmd_connection_set_remote_power_reporting.mode=mode; - - cmd->header=sl_bt_cmd_connection_set_remote_power_reporting_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_remote_power_reporting.result; - -} - -sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, - uint8_t phy, - int8_t *current_level, - int8_t *max_level) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_tx_power.connection=connection; - cmd->data.cmd_connection_get_tx_power.phy=phy; - - cmd->header=sl_bt_cmd_connection_get_tx_power_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (current_level) { - *current_level = rsp->data.rsp_connection_get_tx_power.current_level; - } - if (max_level) { - *max_level = rsp->data.rsp_connection_get_tx_power.max_level; - } - return rsp->data.rsp_connection_get_tx_power.result; - -} - -sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, - uint8_t phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_remote_tx_power.connection=connection; - cmd->data.cmd_connection_get_remote_tx_power.phy=phy; - - cmd->header=sl_bt_cmd_connection_get_remote_tx_power_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_get_remote_tx_power.result; - -} - -sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, - int16_t tx_power, - int16_t *tx_power_out) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_tx_power.connection=connection; - cmd->data.cmd_connection_set_tx_power.tx_power=tx_power; - - cmd->header=sl_bt_cmd_connection_set_tx_power_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (tx_power_out) { - *tx_power_out = rsp->data.rsp_connection_set_tx_power.tx_power_out; - } - return rsp->data.rsp_connection_set_tx_power.result; - -} - -sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_read_remote_used_features.connection=connection; - - cmd->header=sl_bt_cmd_connection_read_remote_used_features_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_read_remote_used_features.result; - -} - -sl_status_t sl_bt_connection_get_security_status(uint8_t connection, - uint8_t *security_mode, - uint8_t *key_size, - uint8_t *bonding_handle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_security_status.connection=connection; - - cmd->header=sl_bt_cmd_connection_get_security_status_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (security_mode) { - *security_mode = rsp->data.rsp_connection_get_security_status.security_mode; - } - if (key_size) { - *key_size = rsp->data.rsp_connection_get_security_status.key_size; - } - if (bonding_handle) { - *bonding_handle = rsp->data.rsp_connection_get_security_status.bonding_handle; - } - return rsp->data.rsp_connection_get_security_status.result; - -} - -sl_status_t sl_bt_connection_set_data_length(uint8_t connection, - uint16_t tx_data_len, - uint16_t tx_time_us) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_set_data_length.connection=connection; - cmd->data.cmd_connection_set_data_length.tx_data_len=tx_data_len; - cmd->data.cmd_connection_set_data_length.tx_time_us=tx_time_us; - - cmd->header=sl_bt_cmd_connection_set_data_length_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_set_data_length.result; - -} - -sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_read_statistics.connection=connection; - cmd->data.cmd_connection_read_statistics.reset=reset; - - cmd->header=sl_bt_cmd_connection_read_statistics_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_read_statistics.result; - -} - -sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, - uint32_t *access_address, - uint8_t *role, - uint32_t *crc_init, - uint16_t *interval, - uint16_t *supervision_timeout, - uint8_t *central_clock_accuracy, - uint8_t *central_phy, - uint8_t *peripheral_phy, - uint8_t *channel_selection_algorithm, - uint8_t *hop, - sl_bt_connection_channel_map_t *channel_map, - uint8_t *channel, - uint16_t *event_counter, - uint32_t *start_time_us) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_scheduling_details.connection=connection; - - cmd->header=sl_bt_cmd_connection_get_scheduling_details_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (access_address) { - *access_address = rsp->data.rsp_connection_get_scheduling_details.access_address; - } - if (role) { - *role = rsp->data.rsp_connection_get_scheduling_details.role; - } - if (crc_init) { - *crc_init = rsp->data.rsp_connection_get_scheduling_details.crc_init; - } - if (interval) { - *interval = rsp->data.rsp_connection_get_scheduling_details.interval; - } - if (supervision_timeout) { - *supervision_timeout = rsp->data.rsp_connection_get_scheduling_details.supervision_timeout; - } - if (central_clock_accuracy) { - *central_clock_accuracy = rsp->data.rsp_connection_get_scheduling_details.central_clock_accuracy; - } - if (central_phy) { - *central_phy = rsp->data.rsp_connection_get_scheduling_details.central_phy; - } - if (peripheral_phy) { - *peripheral_phy = rsp->data.rsp_connection_get_scheduling_details.peripheral_phy; - } - if (channel_selection_algorithm) { - *channel_selection_algorithm = rsp->data.rsp_connection_get_scheduling_details.channel_selection_algorithm; - } - if (hop) { - *hop = rsp->data.rsp_connection_get_scheduling_details.hop; - } - if (channel_map) { - memcpy(channel_map,&rsp->data.rsp_connection_get_scheduling_details.channel_map,sizeof(sl_bt_connection_channel_map_t)); - } - if (channel) { - *channel = rsp->data.rsp_connection_get_scheduling_details.channel; - } - if (event_counter) { - *event_counter = rsp->data.rsp_connection_get_scheduling_details.event_counter; - } - if (start_time_us) { - *start_time_us = rsp->data.rsp_connection_get_scheduling_details.start_time_us; - } - return rsp->data.rsp_connection_get_scheduling_details.result; - -} - -sl_status_t sl_bt_connection_close(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_close.connection=connection; - - cmd->header=sl_bt_cmd_connection_close_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_close.result; - -} - -sl_status_t sl_bt_connection_forcefully_close(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_forcefully_close.connection=connection; - - cmd->header=sl_bt_cmd_connection_forcefully_close_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_forcefully_close.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_get_rssi.connection=connection; - - cmd->header=sl_bt_cmd_connection_get_rssi_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_get_rssi.result; - -} - -sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_set_max_mtu.max_mtu=max_mtu; - - cmd->header=sl_bt_cmd_gatt_set_max_mtu_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (max_mtu_out) { - *max_mtu_out = rsp->data.rsp_gatt_set_max_mtu.max_mtu_out; - } - return rsp->data.rsp_gatt_set_max_mtu.result; - -} - -sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_primary_services.connection=connection; - - cmd->header=sl_bt_cmd_gatt_discover_primary_services_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_primary_services.result; - -} - -sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, - size_t uuid_len, - const uint8_t* uuid) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_primary_services_by_uuid.connection=connection; - if ((2+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.len=uuid_len; - memcpy(cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.data,uuid,uuid_len); - - cmd->header=sl_bt_cmd_gatt_discover_primary_services_by_uuid_id+(((2+uuid_len)&0xff)<<8)+(((2+uuid_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_primary_services_by_uuid.result; - -} - -sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, - uint32_t service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_find_included_services.connection=connection; - cmd->data.cmd_gatt_find_included_services.service=service; - - cmd->header=sl_bt_cmd_gatt_find_included_services_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_find_included_services.result; - -} - -sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, - uint32_t service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_characteristics.connection=connection; - cmd->data.cmd_gatt_discover_characteristics.service=service; - - cmd->header=sl_bt_cmd_gatt_discover_characteristics_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_characteristics.result; - -} - -sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_characteristics_by_uuid.connection=connection; - cmd->data.cmd_gatt_discover_characteristics_by_uuid.service=service; - if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.len=uuid_len; - memcpy(cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.data,uuid,uuid_len); - - cmd->header=sl_bt_cmd_gatt_discover_characteristics_by_uuid_id+(((6+uuid_len)&0xff)<<8)+(((6+uuid_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_characteristics_by_uuid.result; - -} - -sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, - uint16_t characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_descriptors.connection=connection; - cmd->data.cmd_gatt_discover_descriptors.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gatt_discover_descriptors_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_descriptors.result; - -} - -sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, - uint16_t start, - uint16_t end) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_discover_characteristic_descriptors.connection=connection; - cmd->data.cmd_gatt_discover_characteristic_descriptors.start=start; - cmd->data.cmd_gatt_discover_characteristic_descriptors.end=end; - - cmd->header=sl_bt_cmd_gatt_discover_characteristic_descriptors_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_discover_characteristic_descriptors.result; - -} - -sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, - uint16_t characteristic, - uint8_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_set_characteristic_notification.connection=connection; - cmd->data.cmd_gatt_set_characteristic_notification.characteristic=characteristic; - cmd->data.cmd_gatt_set_characteristic_notification.flags=flags; - - cmd->header=sl_bt_cmd_gatt_set_characteristic_notification_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_set_characteristic_notification.result; - -} - -sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_send_characteristic_confirmation.connection=connection; - - cmd->header=sl_bt_cmd_gatt_send_characteristic_confirmation_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_send_characteristic_confirmation.result; - -} - -sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, - uint16_t characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_read_characteristic_value.connection=connection; - cmd->data.cmd_gatt_read_characteristic_value.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gatt_read_characteristic_value_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_read_characteristic_value.result; - -} - -sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - uint16_t maxlen) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_read_characteristic_value_from_offset.connection=connection; - cmd->data.cmd_gatt_read_characteristic_value_from_offset.characteristic=characteristic; - cmd->data.cmd_gatt_read_characteristic_value_from_offset.offset=offset; - cmd->data.cmd_gatt_read_characteristic_value_from_offset.maxlen=maxlen; - - cmd->header=sl_bt_cmd_gatt_read_characteristic_value_from_offset_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_read_characteristic_value_from_offset.result; - -} - -sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, - size_t characteristic_list_len, - const uint8_t* characteristic_list) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_read_multiple_characteristic_values.connection=connection; - if ((2+characteristic_list_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.len=characteristic_list_len; - memcpy(cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.data,characteristic_list,characteristic_list_len); - - cmd->header=sl_bt_cmd_gatt_read_multiple_characteristic_values_id+(((2+characteristic_list_len)&0xff)<<8)+(((2+characteristic_list_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_read_multiple_characteristic_values.result; - -} - -sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_read_characteristic_value_by_uuid.connection=connection; - cmd->data.cmd_gatt_read_characteristic_value_by_uuid.service=service; - if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.len=uuid_len; - memcpy(cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.data,uuid,uuid_len); - - cmd->header=sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id+(((6+uuid_len)&0xff)<<8)+(((6+uuid_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_read_characteristic_value_by_uuid.result; - -} - -sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_write_characteristic_value.connection=connection; - cmd->data.cmd_gatt_write_characteristic_value.characteristic=characteristic; - if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_write_characteristic_value.value.len=value_len; - memcpy(cmd->data.cmd_gatt_write_characteristic_value.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_write_characteristic_value_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_write_characteristic_value.result; - -} - -sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_write_characteristic_value_without_response.connection=connection; - cmd->data.cmd_gatt_write_characteristic_value_without_response.characteristic=characteristic; - if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_write_characteristic_value_without_response.value.len=value_len; - memcpy(cmd->data.cmd_gatt_write_characteristic_value_without_response.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_write_characteristic_value_without_response_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sent_len) { - *sent_len = rsp->data.rsp_gatt_write_characteristic_value_without_response.sent_len; - } - return rsp->data.rsp_gatt_write_characteristic_value_without_response.result; - -} - -sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_prepare_characteristic_value_write.connection=connection; - cmd->data.cmd_gatt_prepare_characteristic_value_write.characteristic=characteristic; - cmd->data.cmd_gatt_prepare_characteristic_value_write.offset=offset; - if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_prepare_characteristic_value_write.value.len=value_len; - memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_write.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_prepare_characteristic_value_write_id+(((6+value_len)&0xff)<<8)+(((6+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sent_len) { - *sent_len = rsp->data.rsp_gatt_prepare_characteristic_value_write.sent_len; - } - return rsp->data.rsp_gatt_prepare_characteristic_value_write.result; - -} - -sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.connection=connection; - cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.characteristic=characteristic; - cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.offset=offset; - if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.len=value_len; - memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id+(((6+value_len)&0xff)<<8)+(((6+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sent_len) { - *sent_len = rsp->data.rsp_gatt_prepare_characteristic_value_reliable_write.sent_len; - } - return rsp->data.rsp_gatt_prepare_characteristic_value_reliable_write.result; - -} - -sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, - uint8_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_execute_characteristic_value_write.connection=connection; - cmd->data.cmd_gatt_execute_characteristic_value_write.flags=flags; - - cmd->header=sl_bt_cmd_gatt_execute_characteristic_value_write_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_execute_characteristic_value_write.result; - -} - -sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, - uint16_t descriptor) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_read_descriptor_value.connection=connection; - cmd->data.cmd_gatt_read_descriptor_value.descriptor=descriptor; - - cmd->header=sl_bt_cmd_gatt_read_descriptor_value_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_read_descriptor_value.result; - -} - -sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, - uint16_t descriptor, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_write_descriptor_value.connection=connection; - cmd->data.cmd_gatt_write_descriptor_value.descriptor=descriptor; - if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_write_descriptor_value.value.len=value_len; - memcpy(cmd->data.cmd_gatt_write_descriptor_value.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_write_descriptor_value_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_write_descriptor_value.result; - -} - -sl_status_t sl_bt_gattdb_new_session(uint16_t *session) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_gattdb_new_session_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (session) { - *session = rsp->data.rsp_gattdb_new_session.session; - } - return rsp->data.rsp_gattdb_new_session.result; - -} - -sl_status_t sl_bt_gattdb_add_service(uint16_t session, - uint8_t type, - uint8_t property, - size_t uuid_len, - const uint8_t* uuid, - uint16_t *service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_service.session=session; - cmd->data.cmd_gattdb_add_service.type=type; - cmd->data.cmd_gattdb_add_service.property=property; - if ((5+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gattdb_add_service.uuid.len=uuid_len; - memcpy(cmd->data.cmd_gattdb_add_service.uuid.data,uuid,uuid_len); - - cmd->header=sl_bt_cmd_gattdb_add_service_id+(((5+uuid_len)&0xff)<<8)+(((5+uuid_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (service) { - *service = rsp->data.rsp_gattdb_add_service.service; - } - return rsp->data.rsp_gattdb_add_service.result; - -} - -sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_remove_service.session=session; - cmd->data.cmd_gattdb_remove_service.service=service; - - cmd->header=sl_bt_cmd_gattdb_remove_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_remove_service.result; - -} - -sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, - uint16_t service, - uint16_t included_service, - uint16_t *attribute) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_included_service.session=session; - cmd->data.cmd_gattdb_add_included_service.service=service; - cmd->data.cmd_gattdb_add_included_service.included_service=included_service; - - cmd->header=sl_bt_cmd_gattdb_add_included_service_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (attribute) { - *attribute = rsp->data.rsp_gattdb_add_included_service.attribute; - } - return rsp->data.rsp_gattdb_add_included_service.result; - -} - -sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, - uint16_t attribute) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_remove_included_service.session=session; - cmd->data.cmd_gattdb_remove_included_service.attribute=attribute; - - cmd->header=sl_bt_cmd_gattdb_remove_included_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_remove_included_service.result; - -} - -sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_uuid16_characteristic.session=session; - cmd->data.cmd_gattdb_add_uuid16_characteristic.service=service; - cmd->data.cmd_gattdb_add_uuid16_characteristic.property=property; - cmd->data.cmd_gattdb_add_uuid16_characteristic.security=security; - cmd->data.cmd_gattdb_add_uuid16_characteristic.flag=flag; - cmd->data.cmd_gattdb_add_uuid16_characteristic.uuid=uuid; - cmd->data.cmd_gattdb_add_uuid16_characteristic.value_type=value_type; - cmd->data.cmd_gattdb_add_uuid16_characteristic.maxlen=maxlen; - if ((16+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gattdb_add_uuid16_characteristic.value.len=value_len; - memcpy(cmd->data.cmd_gattdb_add_uuid16_characteristic.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gattdb_add_uuid16_characteristic_id+(((16+value_len)&0xff)<<8)+(((16+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (characteristic) { - *characteristic = rsp->data.rsp_gattdb_add_uuid16_characteristic.characteristic; - } - return rsp->data.rsp_gattdb_add_uuid16_characteristic.result; - -} - -sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_uuid128_characteristic.session=session; - cmd->data.cmd_gattdb_add_uuid128_characteristic.service=service; - cmd->data.cmd_gattdb_add_uuid128_characteristic.property=property; - cmd->data.cmd_gattdb_add_uuid128_characteristic.security=security; - cmd->data.cmd_gattdb_add_uuid128_characteristic.flag=flag; - cmd->data.cmd_gattdb_add_uuid128_characteristic.uuid=uuid; - cmd->data.cmd_gattdb_add_uuid128_characteristic.value_type=value_type; - cmd->data.cmd_gattdb_add_uuid128_characteristic.maxlen=maxlen; - if ((30+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gattdb_add_uuid128_characteristic.value.len=value_len; - memcpy(cmd->data.cmd_gattdb_add_uuid128_characteristic.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gattdb_add_uuid128_characteristic_id+(((30+value_len)&0xff)<<8)+(((30+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (characteristic) { - *characteristic = rsp->data.rsp_gattdb_add_uuid128_characteristic.characteristic; - } - return rsp->data.rsp_gattdb_add_uuid128_characteristic.result; - -} - -sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, - uint16_t characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_remove_characteristic.session=session; - cmd->data.cmd_gattdb_remove_characteristic.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gattdb_remove_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_remove_characteristic.result; - -} - -sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_uuid16_descriptor.session=session; - cmd->data.cmd_gattdb_add_uuid16_descriptor.characteristic=characteristic; - cmd->data.cmd_gattdb_add_uuid16_descriptor.property=property; - cmd->data.cmd_gattdb_add_uuid16_descriptor.security=security; - cmd->data.cmd_gattdb_add_uuid16_descriptor.uuid=uuid; - cmd->data.cmd_gattdb_add_uuid16_descriptor.value_type=value_type; - cmd->data.cmd_gattdb_add_uuid16_descriptor.maxlen=maxlen; - if ((15+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gattdb_add_uuid16_descriptor.value.len=value_len; - memcpy(cmd->data.cmd_gattdb_add_uuid16_descriptor.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gattdb_add_uuid16_descriptor_id+(((15+value_len)&0xff)<<8)+(((15+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (descriptor) { - *descriptor = rsp->data.rsp_gattdb_add_uuid16_descriptor.descriptor; - } - return rsp->data.rsp_gattdb_add_uuid16_descriptor.result; - -} - -sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_add_uuid128_descriptor.session=session; - cmd->data.cmd_gattdb_add_uuid128_descriptor.characteristic=characteristic; - cmd->data.cmd_gattdb_add_uuid128_descriptor.property=property; - cmd->data.cmd_gattdb_add_uuid128_descriptor.security=security; - cmd->data.cmd_gattdb_add_uuid128_descriptor.uuid=uuid; - cmd->data.cmd_gattdb_add_uuid128_descriptor.value_type=value_type; - cmd->data.cmd_gattdb_add_uuid128_descriptor.maxlen=maxlen; - if ((29+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gattdb_add_uuid128_descriptor.value.len=value_len; - memcpy(cmd->data.cmd_gattdb_add_uuid128_descriptor.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gattdb_add_uuid128_descriptor_id+(((29+value_len)&0xff)<<8)+(((29+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (descriptor) { - *descriptor = rsp->data.rsp_gattdb_add_uuid128_descriptor.descriptor; - } - return rsp->data.rsp_gattdb_add_uuid128_descriptor.result; - -} - -sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, - uint16_t descriptor) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_remove_descriptor.session=session; - cmd->data.cmd_gattdb_remove_descriptor.descriptor=descriptor; - - cmd->header=sl_bt_cmd_gattdb_remove_descriptor_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_remove_descriptor.result; - -} - -sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_start_service.session=session; - cmd->data.cmd_gattdb_start_service.service=service; - - cmd->header=sl_bt_cmd_gattdb_start_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_start_service.result; - -} - -sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_stop_service.session=session; - cmd->data.cmd_gattdb_stop_service.service=service; - - cmd->header=sl_bt_cmd_gattdb_stop_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_stop_service.result; - -} - -sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, - uint16_t characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_start_characteristic.session=session; - cmd->data.cmd_gattdb_start_characteristic.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gattdb_start_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_start_characteristic.result; - -} - -sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, - uint16_t characteristic) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_stop_characteristic.session=session; - cmd->data.cmd_gattdb_stop_characteristic.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gattdb_stop_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_stop_characteristic.result; - -} - -sl_status_t sl_bt_gattdb_commit(uint16_t session) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_commit.session=session; - - cmd->header=sl_bt_cmd_gattdb_commit_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_commit.result; - -} - -sl_status_t sl_bt_gattdb_abort(uint16_t session) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gattdb_abort.session=session; - - cmd->header=sl_bt_cmd_gattdb_abort_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gattdb_abort.result; - -} - -sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, - uint16_t *max_mtu_out) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_set_max_mtu.max_mtu=max_mtu; - - cmd->header=sl_bt_cmd_gatt_server_set_max_mtu_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (max_mtu_out) { - *max_mtu_out = rsp->data.rsp_gatt_server_set_max_mtu.max_mtu_out; - } - return rsp->data.rsp_gatt_server_set_max_mtu.result; - -} - -sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_get_mtu.connection=connection; - - cmd->header=sl_bt_cmd_gatt_server_get_mtu_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (mtu) { - *mtu = rsp->data.rsp_gatt_server_get_mtu.mtu; - } - return rsp->data.rsp_gatt_server_get_mtu.result; - -} - -sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, - size_t type_len, - const uint8_t* type, - uint16_t *attribute) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_find_attribute.start=start; - if ((3+type_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_find_attribute.type.len=type_len; - memcpy(cmd->data.cmd_gatt_server_find_attribute.type.data,type,type_len); - - cmd->header=sl_bt_cmd_gatt_server_find_attribute_id+(((3+type_len)&0xff)<<8)+(((3+type_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (attribute) { - *attribute = rsp->data.rsp_gatt_server_find_attribute.attribute; - } - return rsp->data.rsp_gatt_server_find_attribute.result; - -} - -sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, - uint16_t offset, - size_t max_value_size, - size_t *value_len, - uint8_t *value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_read_attribute_value.attribute=attribute; - cmd->data.cmd_gatt_server_read_attribute_value.offset=offset; - - cmd->header=sl_bt_cmd_gatt_server_read_attribute_value_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (value_len) { - *value_len = rsp->data.rsp_gatt_server_read_attribute_value.value.len; - } - if (value && (rsp->data.rsp_gatt_server_read_attribute_value.value.len <= max_value_size)) { - memcpy(value,rsp->data.rsp_gatt_server_read_attribute_value.value.data,rsp->data.rsp_gatt_server_read_attribute_value.value.len); - } - return rsp->data.rsp_gatt_server_read_attribute_value.result; - -} - -sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, - size_t max_type_size, - size_t *type_len, - uint8_t *type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_read_attribute_type.attribute=attribute; - - cmd->header=sl_bt_cmd_gatt_server_read_attribute_type_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (type_len) { - *type_len = rsp->data.rsp_gatt_server_read_attribute_type.type.len; - } - if (type && (rsp->data.rsp_gatt_server_read_attribute_type.type.len <= max_type_size)) { - memcpy(type,rsp->data.rsp_gatt_server_read_attribute_type.type.data,rsp->data.rsp_gatt_server_read_attribute_type.type.len); - } - return rsp->data.rsp_gatt_server_read_attribute_type.result; - -} - -sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, - uint16_t offset, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_write_attribute_value.attribute=attribute; - cmd->data.cmd_gatt_server_write_attribute_value.offset=offset; - if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_write_attribute_value.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_write_attribute_value.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_write_attribute_value_id+(((5+value_len)&0xff)<<8)+(((5+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_write_attribute_value.result; - -} - -sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_send_user_read_response.connection=connection; - cmd->data.cmd_gatt_server_send_user_read_response.characteristic=characteristic; - cmd->data.cmd_gatt_server_send_user_read_response.att_errorcode=att_errorcode; - if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_send_user_read_response.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_send_user_read_response.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_send_user_read_response_id+(((5+value_len)&0xff)<<8)+(((5+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (sent_len) { - *sent_len = rsp->data.rsp_gatt_server_send_user_read_response.sent_len; - } - return rsp->data.rsp_gatt_server_send_user_read_response.result; - -} - -sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_send_user_write_response.connection=connection; - cmd->data.cmd_gatt_server_send_user_write_response.characteristic=characteristic; - cmd->data.cmd_gatt_server_send_user_write_response.att_errorcode=att_errorcode; - - cmd->header=sl_bt_cmd_gatt_server_send_user_write_response_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_send_user_write_response.result; - -} - -sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_send_notification.connection=connection; - cmd->data.cmd_gatt_server_send_notification.characteristic=characteristic; - if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_send_notification.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_send_notification.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_send_notification_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_send_notification.result; - -} - -sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_send_indication.connection=connection; - cmd->data.cmd_gatt_server_send_indication.characteristic=characteristic; - if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_send_indication.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_send_indication.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_send_indication_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_send_indication.result; - -} - -sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_notify_all.characteristic=characteristic; - if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_notify_all.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_notify_all.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_notify_all_id+(((3+value_len)&0xff)<<8)+(((3+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_notify_all.result; - -} - -sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, - uint16_t characteristic, - uint16_t *client_config_flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_read_client_configuration.connection=connection; - cmd->data.cmd_gatt_server_read_client_configuration.characteristic=characteristic; - - cmd->header=sl_bt_cmd_gatt_server_read_client_configuration_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (client_config_flags) { - *client_config_flags = rsp->data.rsp_gatt_server_read_client_configuration.client_config_flags; - } - return rsp->data.rsp_gatt_server_read_client_configuration.result; - -} - -sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - uint16_t offset, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_send_user_prepare_write_response.connection=connection; - cmd->data.cmd_gatt_server_send_user_prepare_write_response.characteristic=characteristic; - cmd->data.cmd_gatt_server_send_user_prepare_write_response.att_errorcode=att_errorcode; - cmd->data.cmd_gatt_server_send_user_prepare_write_response.offset=offset; - if ((7+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.len=value_len; - memcpy(cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.data,value,value_len); - - cmd->header=sl_bt_cmd_gatt_server_send_user_prepare_write_response_id+(((7+value_len)&0xff)<<8)+(((7+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_send_user_prepare_write_response.result; - -} - -sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, - uint32_t reserved) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_set_capabilities.caps=caps; - cmd->data.cmd_gatt_server_set_capabilities.reserved=reserved; - - cmd->header=sl_bt_cmd_gatt_server_set_capabilities_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_set_capabilities.result; - -} - -sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_enable_capabilities.caps=caps; - - cmd->header=sl_bt_cmd_gatt_server_enable_capabilities_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_enable_capabilities.result; - -} - -sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_disable_capabilities.caps=caps; - - cmd->header=sl_bt_cmd_gatt_server_disable_capabilities_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_gatt_server_disable_capabilities.result; - -} - -sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_gatt_server_get_enabled_capabilities_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (caps) { - *caps = rsp->data.rsp_gatt_server_get_enabled_capabilities.caps; - } - return rsp->data.rsp_gatt_server_get_enabled_capabilities.result; - -} - -sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, - uint8_t *client_features) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_gatt_server_read_client_supported_features.connection=connection; - - cmd->header=sl_bt_cmd_gatt_server_read_client_supported_features_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (client_features) { - *client_features = rsp->data.rsp_gatt_server_read_client_supported_features.client_features; - } - return rsp->data.rsp_gatt_server_read_client_supported_features.result; - -} - -sl_status_t sl_bt_nvm_save(uint16_t key, - size_t value_len, - const uint8_t* value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_nvm_save.key=key; - if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_nvm_save.value.len=value_len; - memcpy(cmd->data.cmd_nvm_save.value.data,value,value_len); - - cmd->header=sl_bt_cmd_nvm_save_id+(((3+value_len)&0xff)<<8)+(((3+value_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_nvm_save.result; - -} - -sl_status_t sl_bt_nvm_load(uint16_t key, - size_t max_value_size, - size_t *value_len, - uint8_t *value) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_nvm_load.key=key; - - cmd->header=sl_bt_cmd_nvm_load_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (value_len) { - *value_len = rsp->data.rsp_nvm_load.value.len; - } - if (value && (rsp->data.rsp_nvm_load.value.len <= max_value_size)) { - memcpy(value,rsp->data.rsp_nvm_load.value.data,rsp->data.rsp_nvm_load.value.len); - } - return rsp->data.rsp_nvm_load.result; - -} - -sl_status_t sl_bt_nvm_erase(uint16_t key) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_nvm_erase.key=key; - - cmd->header=sl_bt_cmd_nvm_erase_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_nvm_erase.result; - -} - -sl_status_t sl_bt_nvm_erase_all() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_nvm_erase_all_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_nvm_erase_all.result; - -} - -sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, - uint8_t length, - uint8_t channel, - uint8_t phy, - int8_t power_level) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_test_dtm_tx_v4.packet_type=packet_type; - cmd->data.cmd_test_dtm_tx_v4.length=length; - cmd->data.cmd_test_dtm_tx_v4.channel=channel; - cmd->data.cmd_test_dtm_tx_v4.phy=phy; - cmd->data.cmd_test_dtm_tx_v4.power_level=power_level; - - cmd->header=sl_bt_cmd_test_dtm_tx_v4_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_test_dtm_tx_v4.result; - -} - -sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, - uint8_t channel, - uint8_t phy, - int16_t power_level) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_test_dtm_tx_cw.packet_type=packet_type; - cmd->data.cmd_test_dtm_tx_cw.channel=channel; - cmd->data.cmd_test_dtm_tx_cw.phy=phy; - cmd->data.cmd_test_dtm_tx_cw.power_level=power_level; - - cmd->header=sl_bt_cmd_test_dtm_tx_cw_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_test_dtm_tx_cw.result; - -} - -sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_test_dtm_rx.channel=channel; - cmd->data.cmd_test_dtm_rx.phy=phy; - - cmd->header=sl_bt_cmd_test_dtm_rx_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_test_dtm_rx.result; - -} - -sl_status_t sl_bt_test_dtm_end() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_test_dtm_end_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_test_dtm_end.result; - -} - -sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_configure.flags=flags; - cmd->data.cmd_sm_configure.io_capabilities=io_capabilities; - - cmd->header=sl_bt_cmd_sm_configure_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_configure.result; - -} - -sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_minimum_key_size.minimum_key_size=minimum_key_size; - - cmd->header=sl_bt_cmd_sm_set_minimum_key_size_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_minimum_key_size.result; - -} - -sl_status_t sl_bt_sm_set_debug_mode() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_sm_set_debug_mode_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_debug_mode.result; - -} - -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_sm_add_to_whitelist.address,&address,sizeof(bd_addr)); - cmd->data.cmd_sm_add_to_whitelist.address_type=address_type; - - cmd->header=sl_bt_cmd_sm_add_to_whitelist_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_add_to_whitelist.result; - -} - -sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, - uint8_t policy_flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_store_bonding_configuration.max_bonding_count=max_bonding_count; - cmd->data.cmd_sm_store_bonding_configuration.policy_flags=policy_flags; - - cmd->header=sl_bt_cmd_sm_store_bonding_configuration_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_store_bonding_configuration.result; - -} - -sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_bondable_mode.bondable=bondable; - - cmd->header=sl_bt_cmd_sm_set_bondable_mode_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_bondable_mode.result; - -} - -sl_status_t sl_bt_sm_set_passkey(int32_t passkey) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_passkey.passkey=passkey; - - cmd->header=sl_bt_cmd_sm_set_passkey_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_passkey.result; - -} - -sl_status_t sl_bt_sm_increase_security(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_increase_security.connection=connection; - - cmd->header=sl_bt_cmd_sm_increase_security_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_increase_security.result; - -} - -sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_enter_passkey.connection=connection; - cmd->data.cmd_sm_enter_passkey.passkey=passkey; - - cmd->header=sl_bt_cmd_sm_enter_passkey_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_enter_passkey.result; - -} - -sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_passkey_confirm.connection=connection; - cmd->data.cmd_sm_passkey_confirm.confirm=confirm; - - cmd->header=sl_bt_cmd_sm_passkey_confirm_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_passkey_confirm.result; - -} - -sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_bonding_confirm.connection=connection; - cmd->data.cmd_sm_bonding_confirm.confirm=confirm; - - cmd->header=sl_bt_cmd_sm_bonding_confirm_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_bonding_confirm.result; - -} - -sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_delete_bonding.bonding=bonding; - - cmd->header=sl_bt_cmd_sm_delete_bonding_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_delete_bonding.result; - -} - -sl_status_t sl_bt_sm_delete_bondings() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_sm_delete_bondings_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_delete_bondings.result; - -} - -sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, - uint32_t *num_bondings, - size_t max_bondings_size, - size_t *bondings_len, - uint8_t *bondings) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_get_bonding_handles.reserved=reserved; - - cmd->header=sl_bt_cmd_sm_get_bonding_handles_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (num_bondings) { - *num_bondings = rsp->data.rsp_sm_get_bonding_handles.num_bondings; - } - if (bondings_len) { - *bondings_len = rsp->data.rsp_sm_get_bonding_handles.bondings.len; - } - if (bondings && (rsp->data.rsp_sm_get_bonding_handles.bondings.len <= max_bondings_size)) { - memcpy(bondings,rsp->data.rsp_sm_get_bonding_handles.bondings.data,rsp->data.rsp_sm_get_bonding_handles.bondings.len); - } - return rsp->data.rsp_sm_get_bonding_handles.result; - -} - -sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, - bd_addr *address, - uint8_t *address_type, - uint8_t *security_mode, - uint8_t *key_size) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_get_bonding_details.bonding=bonding; - - cmd->header=sl_bt_cmd_sm_get_bonding_details_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (address) { - memcpy(address,&rsp->data.rsp_sm_get_bonding_details.address,sizeof(bd_addr)); - } - if (address_type) { - *address_type = rsp->data.rsp_sm_get_bonding_details.address_type; - } - if (security_mode) { - *security_mode = rsp->data.rsp_sm_get_bonding_details.security_mode; - } - if (key_size) { - *key_size = rsp->data.rsp_sm_get_bonding_details.key_size; - } - return rsp->data.rsp_sm_get_bonding_details.result; - -} - -sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, - uint32_t *bonding, - uint8_t *security_mode, - uint8_t *key_size) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_sm_find_bonding_by_address.address,&address,sizeof(bd_addr)); - - cmd->header=sl_bt_cmd_sm_find_bonding_by_address_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (bonding) { - *bonding = rsp->data.rsp_sm_find_bonding_by_address.bonding; - } - if (security_mode) { - *security_mode = rsp->data.rsp_sm_find_bonding_by_address.security_mode; - } - if (key_size) { - *key_size = rsp->data.rsp_sm_find_bonding_by_address.key_size; - } - return rsp->data.rsp_sm_find_bonding_by_address.result; - -} - -sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, - bd_addr *address, - uint8_t *address_type, - uint32_t *bonding) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_sm_resolve_rpa.rpa,&rpa,sizeof(bd_addr)); - - cmd->header=sl_bt_cmd_sm_resolve_rpa_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (address) { - memcpy(address,&rsp->data.rsp_sm_resolve_rpa.address,sizeof(bd_addr)); - } - if (address_type) { - *address_type = rsp->data.rsp_sm_resolve_rpa.address_type; - } - if (bonding) { - *bonding = rsp->data.rsp_sm_resolve_rpa.bonding; - } - return rsp->data.rsp_sm_resolve_rpa.result; - -} - -sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, - uint8_t key_type, - aes_key_128 key) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_bonding_key.bonding=bonding; - cmd->data.cmd_sm_set_bonding_key.key_type=key_type; - memcpy(&cmd->data.cmd_sm_set_bonding_key.key,&key,sizeof(aes_key_128)); - - cmd->header=sl_bt_cmd_sm_set_bonding_key_id+(((21)&0xff)<<8)+(((21)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_bonding_key.result; - -} - -sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_legacy_oob.enable=enable; - memcpy(&cmd->data.cmd_sm_set_legacy_oob.oob_data,&oob_data,sizeof(aes_key_128)); - - cmd->header=sl_bt_cmd_sm_set_legacy_oob_id+(((17)&0xff)<<8)+(((17)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_legacy_oob.result; - -} - -sl_status_t sl_bt_sm_set_oob(uint8_t enable, - aes_key_128 *random, - aes_key_128 *confirm) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_oob.enable=enable; - - cmd->header=sl_bt_cmd_sm_set_oob_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (random) { - memcpy(random,&rsp->data.rsp_sm_set_oob.random,sizeof(aes_key_128)); - } - if (confirm) { - memcpy(confirm,&rsp->data.rsp_sm_set_oob.confirm,sizeof(aes_key_128)); - } - return rsp->data.rsp_sm_set_oob.result; - -} - -sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, - aes_key_128 random, - aes_key_128 confirm) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_remote_oob.enable=enable; - memcpy(&cmd->data.cmd_sm_set_remote_oob.random,&random,sizeof(aes_key_128)); - memcpy(&cmd->data.cmd_sm_set_remote_oob.confirm,&confirm,sizeof(aes_key_128)); - - cmd->header=sl_bt_cmd_sm_set_remote_oob_id+(((33)&0xff)<<8)+(((33)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_remote_oob.result; - -} - -sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_sm_set_bonding_data.connection=connection; - cmd->data.cmd_sm_set_bonding_data.type=type; - if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_sm_set_bonding_data.data.len=data_len; - memcpy(cmd->data.cmd_sm_set_bonding_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_sm_set_bonding_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_sm_set_bonding_data.result; - -} - -sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_external_bondingdb_set_data.connection=connection; - cmd->data.cmd_external_bondingdb_set_data.type=type; - if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_external_bondingdb_set_data.data.len=data_len; - memcpy(cmd->data.cmd_external_bondingdb_set_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_external_bondingdb_set_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_external_bondingdb_set_data.result; - -} - -sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, - uint8_t privacy_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_resolving_list_add_device_by_bonding.bonding=bonding; - cmd->data.cmd_resolving_list_add_device_by_bonding.privacy_mode=privacy_mode; - - cmd->header=sl_bt_cmd_resolving_list_add_device_by_bonding_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resolving_list_add_device_by_bonding.result; - -} - -sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, - uint8_t address_type, - aes_key_128 key, - uint8_t privacy_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_resolving_list_add_device_by_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_resolving_list_add_device_by_address.address_type=address_type; - memcpy(&cmd->data.cmd_resolving_list_add_device_by_address.key,&key,sizeof(aes_key_128)); - cmd->data.cmd_resolving_list_add_device_by_address.privacy_mode=privacy_mode; - - cmd->header=sl_bt_cmd_resolving_list_add_device_by_address_id+(((24)&0xff)<<8)+(((24)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resolving_list_add_device_by_address.result; - -} - -sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_resolving_list_remove_device_by_bonding.bonding=bonding; - - cmd->header=sl_bt_cmd_resolving_list_remove_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resolving_list_remove_device_by_bonding.result; - -} - -sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, - uint8_t address_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_resolving_list_remove_device_by_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_resolving_list_remove_device_by_address.address_type=address_type; - - cmd->header=sl_bt_cmd_resolving_list_remove_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resolving_list_remove_device_by_address.result; - -} - -sl_status_t sl_bt_resolving_list_remove_all_devices() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_resolving_list_remove_all_devices_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_resolving_list_remove_all_devices.result; - -} - -sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_accept_list_add_device_by_bonding.bonding=bonding; - - cmd->header=sl_bt_cmd_accept_list_add_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_accept_list_add_device_by_bonding.result; - -} - -sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, - uint8_t address_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_accept_list_add_device_by_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_accept_list_add_device_by_address.address_type=address_type; - - cmd->header=sl_bt_cmd_accept_list_add_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_accept_list_add_device_by_address.result; - -} - -sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_accept_list_remove_device_by_bonding.bonding=bonding; - - cmd->header=sl_bt_cmd_accept_list_remove_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_accept_list_remove_device_by_bonding.result; - -} - -sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, - uint8_t address_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_accept_list_remove_device_by_address.address,&address,sizeof(bd_addr)); - cmd->data.cmd_accept_list_remove_device_by_address.address_type=address_type; - - cmd->header=sl_bt_cmd_accept_list_remove_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_accept_list_remove_device_by_address.result; - -} - -sl_status_t sl_bt_accept_list_remove_all_devices() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_accept_list_remove_all_devices_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_accept_list_remove_all_devices.result; - -} - -sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+name_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_ota_set_device_name.name.len=name_len; - memcpy(cmd->data.cmd_ota_set_device_name.name.data,name,name_len); - - cmd->header=sl_bt_cmd_ota_set_device_name_id+(((1+name_len)&0xff)<<8)+(((1+name_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_ota_set_device_name.result; - -} - -sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_ota_set_advertising_data.packet_type=packet_type; - if ((2+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_ota_set_advertising_data.adv_data.len=adv_data_len; - memcpy(cmd->data.cmd_ota_set_advertising_data.adv_data.data,adv_data,adv_data_len); - - cmd->header=sl_bt_cmd_ota_set_advertising_data_id+(((2+adv_data_len)&0xff)<<8)+(((2+adv_data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_ota_set_advertising_data.result; - -} - -sl_status_t sl_bt_ota_set_configuration(uint32_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_ota_set_configuration.flags=flags; - - cmd->header=sl_bt_cmd_ota_set_configuration_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_ota_set_configuration.result; - -} - -sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_ota_set_rf_path.enable=enable; - cmd->data.cmd_ota_set_rf_path.antenna=antenna; - - cmd->header=sl_bt_cmd_ota_set_rf_path_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_ota_set_rf_path.result; - -} - -sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_coex_set_options.mask=mask; - cmd->data.cmd_coex_set_options.options=options; - - cmd->header=sl_bt_cmd_coex_set_options_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_coex_set_options.result; - -} - -sl_status_t sl_bt_coex_set_parameters(uint8_t priority, - uint8_t request, - uint8_t pwm_period, - uint8_t pwm_dutycycle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_coex_set_parameters.priority=priority; - cmd->data.cmd_coex_set_parameters.request=request; - cmd->data.cmd_coex_set_parameters.pwm_period=pwm_period; - cmd->data.cmd_coex_set_parameters.pwm_dutycycle=pwm_dutycycle; - - cmd->header=sl_bt_cmd_coex_set_parameters_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_coex_set_parameters.result; - -} - -sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_coex_set_directional_priority_pulse.pulse=pulse; - - cmd->header=sl_bt_cmd_coex_set_directional_priority_pulse_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_coex_set_directional_priority_pulse.result; - -} - -sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, - uint8_t *request, - uint8_t *pwm_period, - uint8_t *pwm_dutycycle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_coex_get_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (priority) { - *priority = rsp->data.rsp_coex_get_parameters.priority; - } - if (request) { - *request = rsp->data.rsp_coex_get_parameters.request; - } - if (pwm_period) { - *pwm_period = rsp->data.rsp_coex_get_parameters.pwm_period; - } - if (pwm_dutycycle) { - *pwm_dutycycle = rsp->data.rsp_coex_get_parameters.pwm_dutycycle; - } - return rsp->data.rsp_coex_get_parameters.result; - -} - -sl_status_t sl_bt_coex_get_counters(uint8_t reset, - size_t max_counters_size, - size_t *counters_len, - uint8_t *counters) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_coex_get_counters.reset=reset; - - cmd->header=sl_bt_cmd_coex_get_counters_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (counters_len) { - *counters_len = rsp->data.rsp_coex_get_counters.counters.len; - } - if (counters && (rsp->data.rsp_coex_get_counters.counters.len <= max_counters_size)) { - memcpy(counters,rsp->data.rsp_coex_get_counters.counters.data,rsp->data.rsp_coex_get_counters.counters.len); - } - return rsp->data.rsp_coex_get_counters.result; - -} - -sl_status_t sl_bt_cs_security_enable(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_security_enable.connection=connection; - - cmd->header=sl_bt_cmd_cs_security_enable_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_security_enable.result; - -} - -sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, - uint8_t initiator_status, - uint8_t reflector_status, - uint8_t antenna_identifier, - int8_t max_tx_power) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_set_default_settings.connection=connection; - cmd->data.cmd_cs_set_default_settings.initiator_status=initiator_status; - cmd->data.cmd_cs_set_default_settings.reflector_status=reflector_status; - cmd->data.cmd_cs_set_default_settings.antenna_identifier=antenna_identifier; - cmd->data.cmd_cs_set_default_settings.max_tx_power=max_tx_power; - - cmd->header=sl_bt_cmd_cs_set_default_settings_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_set_default_settings.result; - -} - -sl_status_t sl_bt_cs_create_config(uint8_t connection, - uint8_t config_id, - uint8_t create_context, - uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t min_main_mode_steps, - uint8_t max_main_mode_steps, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - const sl_bt_cs_channel_map_t *channel_map, - uint8_t channel_map_repetition, - uint8_t channel_selection_type, - uint8_t ch3c_shape, - uint8_t ch3c_jump, - uint8_t companion_signal_state) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_create_config.connection=connection; - cmd->data.cmd_cs_create_config.config_id=config_id; - cmd->data.cmd_cs_create_config.create_context=create_context; - cmd->data.cmd_cs_create_config.main_mode_type=main_mode_type; - cmd->data.cmd_cs_create_config.sub_mode_type=sub_mode_type; - cmd->data.cmd_cs_create_config.min_main_mode_steps=min_main_mode_steps; - cmd->data.cmd_cs_create_config.max_main_mode_steps=max_main_mode_steps; - cmd->data.cmd_cs_create_config.main_mode_repetition=main_mode_repetition; - cmd->data.cmd_cs_create_config.mode_calibration_steps=mode_calibration_steps; - cmd->data.cmd_cs_create_config.role=role; - cmd->data.cmd_cs_create_config.rtt_type=rtt_type; - cmd->data.cmd_cs_create_config.cs_sync_phy=cs_sync_phy; - memcpy(&cmd->data.cmd_cs_create_config.channel_map,channel_map,sizeof(sl_bt_cs_channel_map_t)); - cmd->data.cmd_cs_create_config.channel_map_repetition=channel_map_repetition; - cmd->data.cmd_cs_create_config.channel_selection_type=channel_selection_type; - cmd->data.cmd_cs_create_config.ch3c_shape=ch3c_shape; - cmd->data.cmd_cs_create_config.ch3c_jump=ch3c_jump; - cmd->data.cmd_cs_create_config.companion_signal_state=companion_signal_state; - - cmd->header=sl_bt_cmd_cs_create_config_id+(((27)&0xff)<<8)+(((27)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_create_config.result; - -} - -sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_remove_config.connection=connection; - cmd->data.cmd_cs_remove_config.config_id=config_id; - - cmd->header=sl_bt_cmd_cs_remove_config_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_remove_config.result; - -} - -sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - memcpy(&cmd->data.cmd_cs_set_channel_classification.channel_map,channel_map,sizeof(sl_bt_cs_channel_map_t)); - - cmd->header=sl_bt_cmd_cs_set_channel_classification_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_set_channel_classification.result; - -} - -sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, - uint8_t config_id, - uint16_t max_procedure_len, - uint16_t min_procedure_interval, - uint16_t max_procedure_interval, - uint16_t max_procedure_count, - uint32_t min_subevent_len, - uint32_t max_subevent_len, - uint8_t tone_antenna_config_selection, - uint8_t phy, - int8_t tx_pwr_delta, - uint8_t preferred_peer_antenna) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_set_procedure_parameters.connection=connection; - cmd->data.cmd_cs_set_procedure_parameters.config_id=config_id; - cmd->data.cmd_cs_set_procedure_parameters.max_procedure_len=max_procedure_len; - cmd->data.cmd_cs_set_procedure_parameters.min_procedure_interval=min_procedure_interval; - cmd->data.cmd_cs_set_procedure_parameters.max_procedure_interval=max_procedure_interval; - cmd->data.cmd_cs_set_procedure_parameters.max_procedure_count=max_procedure_count; - cmd->data.cmd_cs_set_procedure_parameters.min_subevent_len=min_subevent_len; - cmd->data.cmd_cs_set_procedure_parameters.max_subevent_len=max_subevent_len; - cmd->data.cmd_cs_set_procedure_parameters.tone_antenna_config_selection=tone_antenna_config_selection; - cmd->data.cmd_cs_set_procedure_parameters.phy=phy; - cmd->data.cmd_cs_set_procedure_parameters.tx_pwr_delta=tx_pwr_delta; - cmd->data.cmd_cs_set_procedure_parameters.preferred_peer_antenna=preferred_peer_antenna; - - cmd->header=sl_bt_cmd_cs_set_procedure_parameters_id+(((22)&0xff)<<8)+(((22)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_set_procedure_parameters.result; - -} - -sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, - uint8_t enable, - uint8_t config_id) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_procedure_enable.connection=connection; - cmd->data.cmd_cs_procedure_enable.enable=enable; - cmd->data.cmd_cs_procedure_enable.config_id=config_id; - - cmd->header=sl_bt_cmd_cs_procedure_enable_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_procedure_enable.result; - -} - -sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, - const uint8_t* antenna_element_offset) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+antenna_element_offset_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cs_set_antenna_configuration.antenna_element_offset.len=antenna_element_offset_len; - memcpy(cmd->data.cmd_cs_set_antenna_configuration.antenna_element_offset.data,antenna_element_offset,antenna_element_offset_len); - - cmd->header=sl_bt_cmd_cs_set_antenna_configuration_id+(((1+antenna_element_offset_len)&0xff)<<8)+(((1+antenna_element_offset_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_set_antenna_configuration.result; - -} - -sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, - uint16_t *max_consecutive_procedures, - uint8_t *num_antennas, - uint8_t *max_antenna_paths, - uint8_t *roles, - uint8_t *optional_modes, - uint8_t *rtt_capability, - uint8_t *rtt_aa_only, - uint8_t *rtt_sounding, - uint8_t *rtt_random_payload, - uint8_t *optional_cs_sync_phys, - uint16_t *optional_subfeatures, - uint16_t *optional_t_ip1_times, - uint16_t *optional_t_ip2_times, - uint16_t *optional_t_fcs_times, - uint16_t *optional_t_pm_times, - uint8_t *t_sw_times) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_cs_read_local_supported_capabilities_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (num_config) { - *num_config = rsp->data.rsp_cs_read_local_supported_capabilities.num_config; - } - if (max_consecutive_procedures) { - *max_consecutive_procedures = rsp->data.rsp_cs_read_local_supported_capabilities.max_consecutive_procedures; - } - if (num_antennas) { - *num_antennas = rsp->data.rsp_cs_read_local_supported_capabilities.num_antennas; - } - if (max_antenna_paths) { - *max_antenna_paths = rsp->data.rsp_cs_read_local_supported_capabilities.max_antenna_paths; - } - if (roles) { - *roles = rsp->data.rsp_cs_read_local_supported_capabilities.roles; - } - if (optional_modes) { - *optional_modes = rsp->data.rsp_cs_read_local_supported_capabilities.optional_modes; - } - if (rtt_capability) { - *rtt_capability = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_capability; - } - if (rtt_aa_only) { - *rtt_aa_only = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_aa_only; - } - if (rtt_sounding) { - *rtt_sounding = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_sounding; - } - if (rtt_random_payload) { - *rtt_random_payload = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_random_payload; - } - if (optional_cs_sync_phys) { - *optional_cs_sync_phys = rsp->data.rsp_cs_read_local_supported_capabilities.optional_cs_sync_phys; - } - if (optional_subfeatures) { - *optional_subfeatures = rsp->data.rsp_cs_read_local_supported_capabilities.optional_subfeatures; - } - if (optional_t_ip1_times) { - *optional_t_ip1_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_ip1_times; - } - if (optional_t_ip2_times) { - *optional_t_ip2_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_ip2_times; - } - if (optional_t_fcs_times) { - *optional_t_fcs_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_fcs_times; - } - if (optional_t_pm_times) { - *optional_t_pm_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_pm_times; - } - if (t_sw_times) { - *t_sw_times = rsp->data.rsp_cs_read_local_supported_capabilities.t_sw_times; - } - return rsp->data.rsp_cs_read_local_supported_capabilities.result; - -} - -sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - uint8_t antenna_selection, - const sl_bt_cs_subevent_length_t *subevent_len, - uint16_t subevent_interval, - int8_t tx_power, - uint8_t t_ip1_time, - uint8_t t_ip2_time, - uint8_t t_fcs_time, - uint8_t t_pm_time, - uint8_t t_sw_time, - uint8_t tone_antenna_config, - uint8_t companion_signal_state, - uint16_t drbg_nonce, - uint16_t override_config, - size_t override_parameters_len, - const uint8_t* override_parameters) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cs_test_start.main_mode_type=main_mode_type; - cmd->data.cmd_cs_test_start.sub_mode_type=sub_mode_type; - cmd->data.cmd_cs_test_start.main_mode_repetition=main_mode_repetition; - cmd->data.cmd_cs_test_start.mode_calibration_steps=mode_calibration_steps; - cmd->data.cmd_cs_test_start.role=role; - cmd->data.cmd_cs_test_start.rtt_type=rtt_type; - cmd->data.cmd_cs_test_start.cs_sync_phy=cs_sync_phy; - cmd->data.cmd_cs_test_start.antenna_selection=antenna_selection; - memcpy(&cmd->data.cmd_cs_test_start.subevent_len,subevent_len,sizeof(sl_bt_cs_subevent_length_t)); - cmd->data.cmd_cs_test_start.subevent_interval=subevent_interval; - cmd->data.cmd_cs_test_start.tx_power=tx_power; - cmd->data.cmd_cs_test_start.t_ip1_time=t_ip1_time; - cmd->data.cmd_cs_test_start.t_ip2_time=t_ip2_time; - cmd->data.cmd_cs_test_start.t_fcs_time=t_fcs_time; - cmd->data.cmd_cs_test_start.t_pm_time=t_pm_time; - cmd->data.cmd_cs_test_start.t_sw_time=t_sw_time; - cmd->data.cmd_cs_test_start.tone_antenna_config=tone_antenna_config; - cmd->data.cmd_cs_test_start.companion_signal_state=companion_signal_state; - cmd->data.cmd_cs_test_start.drbg_nonce=drbg_nonce; - cmd->data.cmd_cs_test_start.override_config=override_config; - if ((26+override_parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cs_test_start.override_parameters.len=override_parameters_len; - memcpy(cmd->data.cmd_cs_test_start.override_parameters.data,override_parameters,override_parameters_len); - - cmd->header=sl_bt_cmd_cs_test_start_id+(((26+override_parameters_len)&0xff)<<8)+(((26+override_parameters_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cs_test_start.result; - -} - -sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, - uint16_t spsm, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t *cid) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_l2cap_open_le_channel.connection=connection; - cmd->data.cmd_l2cap_open_le_channel.spsm=spsm; - cmd->data.cmd_l2cap_open_le_channel.max_sdu=max_sdu; - cmd->data.cmd_l2cap_open_le_channel.max_pdu=max_pdu; - cmd->data.cmd_l2cap_open_le_channel.credit=credit; - - cmd->header=sl_bt_cmd_l2cap_open_le_channel_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (cid) { - *cid = rsp->data.rsp_l2cap_open_le_channel.cid; - } - return rsp->data.rsp_l2cap_open_le_channel.result; - -} - -sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, - uint16_t cid, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t errorcode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_l2cap_send_le_channel_open_response.connection=connection; - cmd->data.cmd_l2cap_send_le_channel_open_response.cid=cid; - cmd->data.cmd_l2cap_send_le_channel_open_response.max_sdu=max_sdu; - cmd->data.cmd_l2cap_send_le_channel_open_response.max_pdu=max_pdu; - cmd->data.cmd_l2cap_send_le_channel_open_response.credit=credit; - cmd->data.cmd_l2cap_send_le_channel_open_response.errorcode=errorcode; - - cmd->header=sl_bt_cmd_l2cap_send_le_channel_open_response_id+(((11)&0xff)<<8)+(((11)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_l2cap_send_le_channel_open_response.result; - -} - -sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, - uint16_t cid, - size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_l2cap_channel_send_data.connection=connection; - cmd->data.cmd_l2cap_channel_send_data.cid=cid; - if ((4+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_l2cap_channel_send_data.data.len=data_len; - memcpy(cmd->data.cmd_l2cap_channel_send_data.data.data,data,data_len); - - cmd->header=sl_bt_cmd_l2cap_channel_send_data_id+(((4+data_len)&0xff)<<8)+(((4+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_l2cap_channel_send_data.result; - -} - -sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, - uint16_t cid, - uint16_t credit) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_l2cap_channel_send_credit.connection=connection; - cmd->data.cmd_l2cap_channel_send_credit.cid=cid; - cmd->data.cmd_l2cap_channel_send_credit.credit=credit; - - cmd->header=sl_bt_cmd_l2cap_channel_send_credit_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_l2cap_channel_send_credit.result; - -} - -sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_l2cap_close_channel.connection=connection; - cmd->data.cmd_l2cap_close_channel.cid=cid; - - cmd->header=sl_bt_cmd_l2cap_close_channel_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_l2cap_close_channel.result; - -} - -sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_length=cte_length; - cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_type=cte_type; - if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_transmitter_set_dtm_parameters_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_set_dtm_parameters.result; - -} - -sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_clear_dtm_parameters.result; - -} - -sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, - uint8_t cte_types, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_enable_connection_cte.connection=connection; - cmd->data.cmd_cte_transmitter_enable_connection_cte.cte_types=cte_types; - if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_transmitter_enable_connection_cte_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_enable_connection_cte.result; - -} - -sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_disable_connection_cte.connection=connection; - - cmd->header=sl_bt_cmd_cte_transmitter_disable_connection_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_disable_connection_cte.result; - -} - -sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_enable_connectionless_cte.handle=handle; - cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_length=cte_length; - cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_type=cte_type; - cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_count=cte_count; - if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_enable_connectionless_cte.result; - -} - -sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_disable_connectionless_cte.handle=handle; - - cmd->header=sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_disable_connectionless_cte.result; - -} - -sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_enable_silabs_cte.handle=handle; - cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_length=cte_length; - cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_type=cte_type; - cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_count=cte_count; - if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_transmitter_enable_silabs_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_enable_silabs_cte.result; - -} - -sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_transmitter_disable_silabs_cte.handle=handle; - - cmd->header=sl_bt_cmd_cte_transmitter_disable_silabs_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_transmitter_disable_silabs_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_length=cte_length; - cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_type=cte_type; - cmd->data.cmd_cte_receiver_set_dtm_parameters.slot_durations=slot_durations; - if ((4+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_receiver_set_dtm_parameters_id+(((4+switching_pattern_len)&0xff)<<8)+(((4+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_set_dtm_parameters.result; - -} - -sl_status_t sl_bt_cte_receiver_clear_dtm_parameters() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_cte_receiver_clear_dtm_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_clear_dtm_parameters.result; - -} - -sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_set_sync_cte_type.sync_cte_type=sync_cte_type; - - cmd->header=sl_bt_cmd_cte_receiver_set_sync_cte_type_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_set_sync_cte_type.result; - -} - -sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.mode=mode; - cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.skip=skip; - cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.timeout=timeout; - cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.sync_cte_type=sync_cte_type; - cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_set_default_sync_receive_parameters.result; - -} - -sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.connection=connection; - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.mode=mode; - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.skip=skip; - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.timeout=timeout; - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.sync_cte_type=sync_cte_type; - cmd->data.cmd_cte_receiver_set_sync_receive_parameters.reporting_mode=reporting_mode; - - cmd->header=sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_set_sync_receive_parameters.result; - -} - -sl_status_t sl_bt_cte_receiver_configure(uint8_t flags) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_configure.flags=flags; - - cmd->header=sl_bt_cmd_cte_receiver_configure_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_configure.result; - -} - -sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, - uint16_t interval, - uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_enable_connection_cte.connection=connection; - cmd->data.cmd_cte_receiver_enable_connection_cte.interval=interval; - cmd->data.cmd_cte_receiver_enable_connection_cte.cte_length=cte_length; - cmd->data.cmd_cte_receiver_enable_connection_cte.cte_type=cte_type; - cmd->data.cmd_cte_receiver_enable_connection_cte.slot_durations=slot_durations; - if ((7+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_receiver_enable_connection_cte_id+(((7+switching_pattern_len)&0xff)<<8)+(((7+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_enable_connection_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_disable_connection_cte.connection=connection; - - cmd->header=sl_bt_cmd_cte_receiver_disable_connection_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_disable_connection_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, - uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_enable_connectionless_cte.sync=sync; - cmd->data.cmd_cte_receiver_enable_connectionless_cte.slot_durations=slot_durations; - cmd->data.cmd_cte_receiver_enable_connectionless_cte.cte_count=cte_count; - if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_receiver_enable_connectionless_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_enable_connectionless_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_disable_connectionless_cte.sync=sync; - - cmd->header=sl_bt_cmd_cte_receiver_disable_connectionless_cte_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_disable_connectionless_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_cte_receiver_enable_silabs_cte.slot_durations=slot_durations; - cmd->data.cmd_cte_receiver_enable_silabs_cte.cte_count=cte_count; - if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.len=switching_pattern_len; - memcpy(cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); - - cmd->header=sl_bt_cmd_cte_receiver_enable_silabs_cte_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_enable_silabs_cte.result; - -} - -sl_status_t sl_bt_cte_receiver_disable_silabs_cte() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - - cmd->header=sl_bt_cmd_cte_receiver_disable_silabs_cte_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_cte_receiver_disable_silabs_cte.result; - -} - -sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, - uint32_t crc_init, - uint16_t interval, - uint16_t supervision_timeout, - uint8_t central_clock_accuracy, - uint8_t central_phy, - uint8_t peripheral_phy, - uint8_t channel_selection_algorithm, - uint8_t hop, - const sl_bt_connection_channel_map_t *channel_map, - uint8_t channel, - uint16_t event_counter, - int32_t start_time_us, - uint32_t flags, - uint8_t *analyzer) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_analyzer_start.access_address=access_address; - cmd->data.cmd_connection_analyzer_start.crc_init=crc_init; - cmd->data.cmd_connection_analyzer_start.interval=interval; - cmd->data.cmd_connection_analyzer_start.supervision_timeout=supervision_timeout; - cmd->data.cmd_connection_analyzer_start.central_clock_accuracy=central_clock_accuracy; - cmd->data.cmd_connection_analyzer_start.central_phy=central_phy; - cmd->data.cmd_connection_analyzer_start.peripheral_phy=peripheral_phy; - cmd->data.cmd_connection_analyzer_start.channel_selection_algorithm=channel_selection_algorithm; - cmd->data.cmd_connection_analyzer_start.hop=hop; - memcpy(&cmd->data.cmd_connection_analyzer_start.channel_map,channel_map,sizeof(sl_bt_connection_channel_map_t)); - cmd->data.cmd_connection_analyzer_start.channel=channel; - cmd->data.cmd_connection_analyzer_start.event_counter=event_counter; - cmd->data.cmd_connection_analyzer_start.start_time_us=start_time_us; - cmd->data.cmd_connection_analyzer_start.flags=flags; - - cmd->header=sl_bt_cmd_connection_analyzer_start_id+(((33)&0xff)<<8)+(((33)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (analyzer) { - *analyzer = rsp->data.rsp_connection_analyzer_start.analyzer; - } - return rsp->data.rsp_connection_analyzer_start.result; - -} - -sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - cmd->data.cmd_connection_analyzer_stop.analyzer=analyzer; - - cmd->header=sl_bt_cmd_connection_analyzer_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_connection_analyzer_stop.result; - -} - -sl_status_t sl_bt_user_message_to_target(size_t data_len, - const uint8_t* data, - size_t max_response_size, - size_t *response_len, - uint8_t *response) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_user_message_to_target.data.len=data_len; - memcpy(cmd->data.cmd_user_message_to_target.data.data,data,data_len); - - cmd->header=sl_bt_cmd_user_message_to_target_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - if (response_len) { - *response_len = rsp->data.rsp_user_message_to_target.response.len; - } - if (response && (rsp->data.rsp_user_message_to_target.response.len <= max_response_size)) { - memcpy(response,rsp->data.rsp_user_message_to_target.response.data,rsp->data.rsp_user_message_to_target.response.len); - } - return rsp->data.rsp_user_message_to_target.result; - -} - -sl_status_t sl_bt_user_manage_event_filter(size_t data_len, - const uint8_t* data) { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; - - if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) - { - return SL_STATUS_COMMAND_TOO_LONG; - } - cmd->data.cmd_user_manage_event_filter.data.len=data_len; - memcpy(cmd->data.cmd_user_manage_event_filter.data.data,data,data_len); - - cmd->header=sl_bt_cmd_user_manage_event_filter_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); - - - sl_bt_host_handle_command(); - return rsp->data.rsp_user_manage_event_filter.result; - -} - -void sl_bt_user_reset_to_dfu() { - struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; - - - cmd->header=sl_bt_cmd_user_reset_to_dfu_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); - - - sl_bt_host_handle_command_noresponse(); -} +/***************************************************************************//** + * @brief SL_BT_API commands for NCP host + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_bt_api.h" +#include "sli_bt_api.h" + +void sl_bt_host_handle_command(); +void sl_bt_host_handle_command_noresponse(); +extern sl_bt_msg_t *sl_bt_cmd_msg; +extern sl_bt_msg_t *sl_bt_rsp_msg; + +sl_status_t sl_bt_dfu_flash_set_address(uint32_t address) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_dfu_flash_set_address.address=address; + + cmd->header=sl_bt_cmd_dfu_flash_set_address_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_dfu_flash_set_address.result; + +} + +sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_dfu_flash_upload.data.len=data_len; + memcpy(cmd->data.cmd_dfu_flash_upload.data.data,data,data_len); + + cmd->header=sl_bt_cmd_dfu_flash_upload_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_dfu_flash_upload.result; + +} + +sl_status_t sl_bt_dfu_flash_upload_finish() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_dfu_flash_upload_finish_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_dfu_flash_upload_finish.result; + +} + +sl_status_t sl_bt_system_hello() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_hello_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_hello.result; + +} + +sl_status_t sl_bt_system_start_bluetooth() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_start_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_start_bluetooth.result; + +} + +sl_status_t sl_bt_system_stop_bluetooth() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_stop_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_stop_bluetooth.result; + +} + +sl_status_t sl_bt_system_forcefully_stop_bluetooth() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_forcefully_stop_bluetooth_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_forcefully_stop_bluetooth.result; + +} + +sl_status_t sl_bt_system_get_version(uint16_t *major, + uint16_t *minor, + uint16_t *patch, + uint16_t *build, + uint32_t *bootloader, + uint32_t *hash) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_get_version_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (major) { + *major = rsp->data.rsp_system_get_version.major; + } + if (minor) { + *minor = rsp->data.rsp_system_get_version.minor; + } + if (patch) { + *patch = rsp->data.rsp_system_get_version.patch; + } + if (build) { + *build = rsp->data.rsp_system_get_version.build; + } + if (bootloader) { + *bootloader = rsp->data.rsp_system_get_version.bootloader; + } + if (hash) { + *hash = rsp->data.rsp_system_get_version.hash; + } + return rsp->data.rsp_system_get_version.result; + +} + +void sl_bt_system_reset(uint8_t dfu) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + cmd->data.cmd_system_reset.dfu=dfu; + + cmd->header=sl_bt_cmd_system_reset_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command_noresponse(); +} + +sl_status_t sl_bt_system_halt(uint8_t halt) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_halt.halt=halt; + + cmd->header=sl_bt_cmd_system_halt_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_halt.result; + +} + +sl_status_t sl_bt_system_linklayer_configure(uint8_t key, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_linklayer_configure.key=key; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_system_linklayer_configure.data.len=data_len; + memcpy(cmd->data.cmd_system_linklayer_configure.data.data,data,data_len); + + cmd->header=sl_bt_cmd_system_linklayer_configure_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_linklayer_configure.result; + +} + +sl_status_t sl_bt_system_set_tx_power(int16_t min_power, + int16_t max_power, + int16_t *set_min, + int16_t *set_max) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_set_tx_power.min_power=min_power; + cmd->data.cmd_system_set_tx_power.max_power=max_power; + + cmd->header=sl_bt_cmd_system_set_tx_power_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (set_min) { + *set_min = rsp->data.rsp_system_set_tx_power.set_min; + } + if (set_max) { + *set_max = rsp->data.rsp_system_set_tx_power.set_max; + } + return rsp->data.rsp_system_set_tx_power.result; + +} + +sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, + int16_t *support_max, + int16_t *set_min, + int16_t *set_max, + int16_t *rf_path_gain) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_get_tx_power_setting_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (support_min) { + *support_min = rsp->data.rsp_system_get_tx_power_setting.support_min; + } + if (support_max) { + *support_max = rsp->data.rsp_system_get_tx_power_setting.support_max; + } + if (set_min) { + *set_min = rsp->data.rsp_system_get_tx_power_setting.set_min; + } + if (set_max) { + *set_max = rsp->data.rsp_system_get_tx_power_setting.set_max; + } + if (rf_path_gain) { + *rf_path_gain = rsp->data.rsp_system_get_tx_power_setting.rf_path_gain; + } + return rsp->data.rsp_system_get_tx_power_setting.result; + +} + +sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_system_set_identity_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_system_set_identity_address.type=type; + + cmd->header=sl_bt_cmd_system_set_identity_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_set_identity_address.result; + +} + +sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_get_identity_address_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (address) { + memcpy(address,&rsp->data.rsp_system_get_identity_address.address,sizeof(bd_addr)); + } + if (type) { + *type = rsp->data.rsp_system_get_identity_address.type; + } + return rsp->data.rsp_system_get_identity_address.result; + +} + +sl_status_t sl_bt_system_get_random_data(uint8_t length, + size_t max_data_size, + size_t *data_len, + uint8_t *data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_get_random_data.length=length; + + cmd->header=sl_bt_cmd_system_get_random_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (data_len) { + *data_len = rsp->data.rsp_system_get_random_data.data.len; + } + if (data && (rsp->data.rsp_system_get_random_data.data.len <= max_data_size)) { + memcpy(data,rsp->data.rsp_system_get_random_data.data.data,rsp->data.rsp_system_get_random_data.data.len); + } + return rsp->data.rsp_system_get_random_data.result; + +} + +sl_status_t sl_bt_system_data_buffer_write(size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_system_data_buffer_write.data.len=data_len; + memcpy(cmd->data.cmd_system_data_buffer_write.data.data,data,data_len); + + cmd->header=sl_bt_cmd_system_data_buffer_write_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_data_buffer_write.result; + +} + +sl_status_t sl_bt_system_data_buffer_clear() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_system_data_buffer_clear_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_data_buffer_clear.result; + +} + +sl_status_t sl_bt_system_get_counters(uint8_t reset, + uint16_t *tx_packets, + uint16_t *rx_packets, + uint16_t *crc_errors, + uint16_t *failures) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_get_counters.reset=reset; + + cmd->header=sl_bt_cmd_system_get_counters_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (tx_packets) { + *tx_packets = rsp->data.rsp_system_get_counters.tx_packets; + } + if (rx_packets) { + *rx_packets = rsp->data.rsp_system_get_counters.rx_packets; + } + if (crc_errors) { + *crc_errors = rsp->data.rsp_system_get_counters.crc_errors; + } + if (failures) { + *failures = rsp->data.rsp_system_get_counters.failures; + } + return rsp->data.rsp_system_get_counters.result; + +} + +sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, + uint32_t slack, + uint8_t handle, + uint8_t single_shot) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_system_set_lazy_soft_timer.time=time; + cmd->data.cmd_system_set_lazy_soft_timer.slack=slack; + cmd->data.cmd_system_set_lazy_soft_timer.handle=handle; + cmd->data.cmd_system_set_lazy_soft_timer.single_shot=single_shot; + + cmd->header=sl_bt_cmd_system_set_lazy_soft_timer_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_system_set_lazy_soft_timer.result; + +} + +sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, + uint32_t *free_bytes) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_resource_get_status_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (total_bytes) { + *total_bytes = rsp->data.rsp_resource_get_status.total_bytes; + } + if (free_bytes) { + *free_bytes = rsp->data.rsp_resource_get_status.free_bytes; + } + return rsp->data.rsp_resource_get_status.result; + +} + +sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_resource_set_report_threshold.low=low; + cmd->data.cmd_resource_set_report_threshold.high=high; + + cmd->header=sl_bt_cmd_resource_set_report_threshold_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resource_set_report_threshold.result; + +} + +sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_resource_enable_connection_tx_report.packet_count=packet_count; + + cmd->header=sl_bt_cmd_resource_enable_connection_tx_report_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resource_enable_connection_tx_report.result; + +} + +sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, + uint16_t *flags, + uint16_t *packet_count, + uint32_t *data_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_resource_get_connection_tx_status.connection=connection; + + cmd->header=sl_bt_cmd_resource_get_connection_tx_status_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (flags) { + *flags = rsp->data.rsp_resource_get_connection_tx_status.flags; + } + if (packet_count) { + *packet_count = rsp->data.rsp_resource_get_connection_tx_status.packet_count; + } + if (data_len) { + *data_len = rsp->data.rsp_resource_get_connection_tx_status.data_len; + } + return rsp->data.rsp_resource_get_connection_tx_status.result; + +} + +sl_status_t sl_bt_resource_disable_connection_tx_report() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_resource_disable_connection_tx_report_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resource_disable_connection_tx_report.result; + +} + +sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gap_set_privacy_mode.privacy=privacy; + cmd->data.cmd_gap_set_privacy_mode.interval=interval; + + cmd->header=sl_bt_cmd_gap_set_privacy_mode_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gap_set_privacy_mode.result; + +} + +sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, + const uint8_t* channel_map) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+channel_map_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gap_set_data_channel_classification.channel_map.len=channel_map_len; + memcpy(cmd->data.cmd_gap_set_data_channel_classification.channel_map.data,channel_map,channel_map_len); + + cmd->header=sl_bt_cmd_gap_set_data_channel_classification_id+(((1+channel_map_len)&0xff)<<8)+(((1+channel_map_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gap_set_data_channel_classification.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gap_enable_whitelisting.enable=enable; + + cmd->header=sl_bt_cmd_gap_enable_whitelisting_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gap_enable_whitelisting.result; + +} + +sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_gap_set_identity_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_gap_set_identity_address.addr_type=addr_type; + + cmd->header=sl_bt_cmd_gap_set_identity_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gap_set_identity_address.result; + +} + +sl_status_t sl_bt_advertiser_create_set(uint8_t *handle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_advertiser_create_set_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (handle) { + *handle = rsp->data.rsp_advertiser_create_set.handle; + } + return rsp->data.rsp_advertiser_create_set.result; + +} + +sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_configure.advertising_set=advertising_set; + cmd->data.cmd_advertiser_configure.flags=flags; + + cmd->header=sl_bt_cmd_advertiser_configure_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_configure.result; + +} + +sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, + uint32_t interval_min, + uint32_t interval_max, + uint16_t duration, + uint8_t maxevents) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_timing.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_timing.interval_min=interval_min; + cmd->data.cmd_advertiser_set_timing.interval_max=interval_max; + cmd->data.cmd_advertiser_set_timing.duration=duration; + cmd->data.cmd_advertiser_set_timing.maxevents=maxevents; + + cmd->header=sl_bt_cmd_advertiser_set_timing_id+(((12)&0xff)<<8)+(((12)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_timing.result; + +} + +sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, + uint8_t channel_map) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_channel_map.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_channel_map.channel_map=channel_map; + + cmd->header=sl_bt_cmd_advertiser_set_channel_map_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_channel_map.result; + +} + +sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, + int16_t power, + int16_t *set_power) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_tx_power.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_tx_power.power=power; + + cmd->header=sl_bt_cmd_advertiser_set_tx_power_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (set_power) { + *set_power = rsp->data.rsp_advertiser_set_tx_power.set_power; + } + return rsp->data.rsp_advertiser_set_tx_power.result; + +} + +sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, + uint8_t report_scan_req) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_report_scan_request.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_report_scan_request.report_scan_req=report_scan_req; + + cmd->header=sl_bt_cmd_advertiser_set_report_scan_request_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_report_scan_request.result; + +} + +sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, + uint8_t addr_type, + bd_addr address, + bd_addr *address_out) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_random_address.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_random_address.addr_type=addr_type; + memcpy(&cmd->data.cmd_advertiser_set_random_address.address,&address,sizeof(bd_addr)); + + cmd->header=sl_bt_cmd_advertiser_set_random_address_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (address_out) { + memcpy(address_out,&rsp->data.rsp_advertiser_set_random_address.address_out,sizeof(bd_addr)); + } + return rsp->data.rsp_advertiser_set_random_address.result; + +} + +sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_clear_random_address.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_advertiser_clear_random_address_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_clear_random_address.result; + +} + +sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_stop.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_stop.result; + +} + +sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_delete_set.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_advertiser_delete_set_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_delete_set.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_phy.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_phy.primary_phy=primary_phy; + cmd->data.cmd_advertiser_set_phy.secondary_phy=secondary_phy; + + cmd->header=sl_bt_cmd_advertiser_set_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_phy.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, + uint32_t configurations) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_configuration.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_configuration.configurations=configurations; + + cmd->header=sl_bt_cmd_advertiser_set_configuration_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_configuration.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, + uint32_t configurations) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_clear_configuration.advertising_set=advertising_set; + cmd->data.cmd_advertiser_clear_configuration.configurations=configurations; + + cmd->header=sl_bt_cmd_advertiser_clear_configuration_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_clear_configuration.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, + uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_data.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_data.packet_type=packet_type; + if ((3+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_advertiser_set_data.adv_data.len=adv_data_len; + memcpy(cmd->data.cmd_advertiser_set_data.adv_data.data,adv_data,adv_data_len); + + cmd->header=sl_bt_cmd_advertiser_set_data_id+(((3+adv_data_len)&0xff)<<8)+(((3+adv_data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_data.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, + uint8_t packet_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_set_long_data.advertising_set=advertising_set; + cmd->data.cmd_advertiser_set_long_data.packet_type=packet_type; + + cmd->header=sl_bt_cmd_advertiser_set_long_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_set_long_data.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, + uint8_t discover, + uint8_t connect) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_start.advertising_set=advertising_set; + cmd->data.cmd_advertiser_start.discover=discover; + cmd->data.cmd_advertiser_start.connect=connect; + + cmd->header=sl_bt_cmd_advertiser_start_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_start.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_start_periodic_advertising.advertising_set=advertising_set; + cmd->data.cmd_advertiser_start_periodic_advertising.interval_min=interval_min; + cmd->data.cmd_advertiser_start_periodic_advertising.interval_max=interval_max; + cmd->data.cmd_advertiser_start_periodic_advertising.flags=flags; + + cmd->header=sl_bt_cmd_advertiser_start_periodic_advertising_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_start_periodic_advertising.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_stop_periodic_advertising.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_advertiser_stop_periodic_advertising_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_stop_periodic_advertising.result; + +} + +sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, + uint8_t type, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_legacy_advertiser_set_data.advertising_set=advertising_set; + cmd->data.cmd_legacy_advertiser_set_data.type=type; + if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_legacy_advertiser_set_data.data.len=data_len; + memcpy(cmd->data.cmd_legacy_advertiser_set_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_legacy_advertiser_set_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_legacy_advertiser_set_data.result; + +} + +sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_legacy_advertiser_generate_data.advertising_set=advertising_set; + cmd->data.cmd_legacy_advertiser_generate_data.discover=discover; + + cmd->header=sl_bt_cmd_legacy_advertiser_generate_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_legacy_advertiser_generate_data.result; + +} + +sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, + uint8_t connect) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_legacy_advertiser_start.advertising_set=advertising_set; + cmd->data.cmd_legacy_advertiser_start.connect=connect; + + cmd->header=sl_bt_cmd_legacy_advertiser_start_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_legacy_advertiser_start.result; + +} + +sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + bd_addr peer_addr, + uint8_t peer_addr_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_legacy_advertiser_start_directed.advertising_set=advertising_set; + cmd->data.cmd_legacy_advertiser_start_directed.connect=connect; + memcpy(&cmd->data.cmd_legacy_advertiser_start_directed.peer_addr,&peer_addr,sizeof(bd_addr)); + cmd->data.cmd_legacy_advertiser_start_directed.peer_addr_type=peer_addr_type; + + cmd->header=sl_bt_cmd_legacy_advertiser_start_directed_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_legacy_advertiser_start_directed.result; + +} + +sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_set_phy.advertising_set=advertising_set; + cmd->data.cmd_extended_advertiser_set_phy.primary_phy=primary_phy; + cmd->data.cmd_extended_advertiser_set_phy.secondary_phy=secondary_phy; + + cmd->header=sl_bt_cmd_extended_advertiser_set_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_set_phy.result; + +} + +sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_set_data.advertising_set=advertising_set; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_extended_advertiser_set_data.data.len=data_len; + memcpy(cmd->data.cmd_extended_advertiser_set_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_extended_advertiser_set_data_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_set_data.result; + +} + +sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_set_long_data.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_extended_advertiser_set_long_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_set_long_data.result; + +} + +sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_generate_data.advertising_set=advertising_set; + cmd->data.cmd_extended_advertiser_generate_data.discover=discover; + + cmd->header=sl_bt_cmd_extended_advertiser_generate_data_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_generate_data.result; + +} + +sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, + uint8_t connect, + uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_start.advertising_set=advertising_set; + cmd->data.cmd_extended_advertiser_start.connect=connect; + cmd->data.cmd_extended_advertiser_start.flags=flags; + + cmd->header=sl_bt_cmd_extended_advertiser_start_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_start.result; + +} + +sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + uint32_t flags, + bd_addr peer_addr, + uint8_t peer_addr_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_extended_advertiser_start_directed.advertising_set=advertising_set; + cmd->data.cmd_extended_advertiser_start_directed.connect=connect; + cmd->data.cmd_extended_advertiser_start_directed.flags=flags; + memcpy(&cmd->data.cmd_extended_advertiser_start_directed.peer_addr,&peer_addr,sizeof(bd_addr)); + cmd->data.cmd_extended_advertiser_start_directed.peer_addr_type=peer_addr_type; + + cmd->header=sl_bt_cmd_extended_advertiser_start_directed_id+(((13)&0xff)<<8)+(((13)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_extended_advertiser_start_directed.result; + +} + +sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_periodic_advertiser_set_data.advertising_set=advertising_set; + if ((2+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_periodic_advertiser_set_data.data.len=data_len; + memcpy(cmd->data.cmd_periodic_advertiser_set_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_periodic_advertiser_set_data_id+(((2+data_len)&0xff)<<8)+(((2+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_periodic_advertiser_set_data.result; + +} + +sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_periodic_advertiser_set_long_data.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_periodic_advertiser_set_long_data_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_periodic_advertiser_set_long_data.result; + +} + +sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_periodic_advertiser_start.advertising_set=advertising_set; + cmd->data.cmd_periodic_advertiser_start.interval_min=interval_min; + cmd->data.cmd_periodic_advertiser_start.interval_max=interval_max; + cmd->data.cmd_periodic_advertiser_start.flags=flags; + + cmd->header=sl_bt_cmd_periodic_advertiser_start_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_periodic_advertiser_start.result; + +} + +sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_periodic_advertiser_stop.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_periodic_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_periodic_advertiser_stop.result; + +} + +sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, + uint16_t interval, + uint16_t window) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_scanner_set_parameters.mode=mode; + cmd->data.cmd_scanner_set_parameters.interval=interval; + cmd->data.cmd_scanner_set_parameters.window=window; + + cmd->header=sl_bt_cmd_scanner_set_parameters_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_set_parameters.result; + +} + +sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, + uint16_t interval, + uint16_t window, + uint32_t flags, + uint8_t filter_policy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_scanner_set_parameters_and_filter.mode=mode; + cmd->data.cmd_scanner_set_parameters_and_filter.interval=interval; + cmd->data.cmd_scanner_set_parameters_and_filter.window=window; + cmd->data.cmd_scanner_set_parameters_and_filter.flags=flags; + cmd->data.cmd_scanner_set_parameters_and_filter.filter_policy=filter_policy; + + cmd->header=sl_bt_cmd_scanner_set_parameters_and_filter_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_set_parameters_and_filter.result; + +} + +sl_status_t sl_bt_scanner_stop() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_scanner_stop_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_stop.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, + uint16_t scan_interval, + uint16_t scan_window) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_scanner_set_timing.phys=phys; + cmd->data.cmd_scanner_set_timing.scan_interval=scan_interval; + cmd->data.cmd_scanner_set_timing.scan_window=scan_window; + + cmd->header=sl_bt_cmd_scanner_set_timing_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_set_timing.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_scanner_set_mode.phys=phys; + cmd->data.cmd_scanner_set_mode.scan_mode=scan_mode; + + cmd->header=sl_bt_cmd_scanner_set_mode_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_set_mode.result; + +} + +sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_scanner_start.scanning_phy=scanning_phy; + cmd->data.cmd_scanner_start.discover_mode=discover_mode; + + cmd->header=sl_bt_cmd_scanner_start_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_scanner_start.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, + uint16_t timeout, + uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_set_parameters.skip=skip; + cmd->data.cmd_sync_set_parameters.timeout=timeout; + cmd->data.cmd_sync_set_parameters.flags=flags; + + cmd->header=sl_bt_cmd_sync_set_parameters_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_set_parameters.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_sync_open.address,&address,sizeof(bd_addr)); + cmd->data.cmd_sync_open.address_type=address_type; + cmd->data.cmd_sync_open.adv_sid=adv_sid; + + cmd->header=sl_bt_cmd_sync_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sync) { + *sync = rsp->data.rsp_sync_open.sync; + } + return rsp->data.rsp_sync_open.result; + +} + +sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_set_reporting_mode.sync=sync; + cmd->data.cmd_sync_set_reporting_mode.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_sync_set_reporting_mode_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_set_reporting_mode.result; + +} + +sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, + uint16_t skip, + uint16_t timeout) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_update_sync_parameters.sync=sync; + cmd->data.cmd_sync_update_sync_parameters.skip=skip; + cmd->data.cmd_sync_update_sync_parameters.timeout=timeout; + + cmd->header=sl_bt_cmd_sync_update_sync_parameters_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_update_sync_parameters.result; + +} + +sl_status_t sl_bt_sync_close(uint16_t sync) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_close.sync=sync; + + cmd->header=sl_bt_cmd_sync_close_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_close.result; + +} + +sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_scanner_set_sync_parameters.skip=skip; + cmd->data.cmd_sync_scanner_set_sync_parameters.timeout=timeout; + cmd->data.cmd_sync_scanner_set_sync_parameters.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_sync_scanner_set_sync_parameters_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_scanner_set_sync_parameters.result; + +} + +sl_status_t sl_bt_sync_scanner_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_sync_scanner_open.address,&address,sizeof(bd_addr)); + cmd->data.cmd_sync_scanner_open.address_type=address_type; + cmd->data.cmd_sync_scanner_open.adv_sid=adv_sid; + + cmd->header=sl_bt_cmd_sync_scanner_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sync) { + *sync = rsp->data.rsp_sync_scanner_open.sync; + } + return rsp->data.rsp_sync_scanner_open.result; + +} + +sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.mode=mode; + cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.skip=skip; + cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.timeout=timeout; + cmd->data.cmd_past_receiver_set_default_sync_receive_parameters.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_past_receiver_set_default_sync_receive_parameters.result; + +} + +sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_past_receiver_set_sync_receive_parameters.connection=connection; + cmd->data.cmd_past_receiver_set_sync_receive_parameters.mode=mode; + cmd->data.cmd_past_receiver_set_sync_receive_parameters.skip=skip; + cmd->data.cmd_past_receiver_set_sync_receive_parameters.timeout=timeout; + cmd->data.cmd_past_receiver_set_sync_receive_parameters.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_past_receiver_set_sync_receive_parameters_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_past_receiver_set_sync_receive_parameters.result; + +} + +sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, + uint16_t service_data, + uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_advertiser_past_transfer.connection=connection; + cmd->data.cmd_advertiser_past_transfer.service_data=service_data; + cmd->data.cmd_advertiser_past_transfer.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_advertiser_past_transfer_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_advertiser_past_transfer.result; + +} + +sl_status_t sl_bt_sync_past_transfer(uint8_t connection, + uint16_t service_data, + uint16_t sync) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sync_past_transfer.connection=connection; + cmd->data.cmd_sync_past_transfer.service_data=service_data; + cmd->data.cmd_sync_past_transfer.sync=sync; + + cmd->header=sl_bt_cmd_sync_past_transfer_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sync_past_transfer.result; + +} + +sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, + size_t subevents_len, + const uint8_t* subevents) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_sync_set_sync_subevents.sync=sync; + if ((3+subevents_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_pawr_sync_set_sync_subevents.subevents.len=subevents_len; + memcpy(cmd->data.cmd_pawr_sync_set_sync_subevents.subevents.data,subevents,subevents_len); + + cmd->header=sl_bt_cmd_pawr_sync_set_sync_subevents_id+(((3+subevents_len)&0xff)<<8)+(((3+subevents_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_pawr_sync_set_sync_subevents.result; + +} + +sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, + uint16_t request_event, + uint8_t request_subevent, + uint8_t response_subevent, + uint8_t response_slot, + size_t response_data_len, + const uint8_t* response_data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_sync_set_response_data.sync=sync; + cmd->data.cmd_pawr_sync_set_response_data.request_event=request_event; + cmd->data.cmd_pawr_sync_set_response_data.request_subevent=request_subevent; + cmd->data.cmd_pawr_sync_set_response_data.response_subevent=response_subevent; + cmd->data.cmd_pawr_sync_set_response_data.response_slot=response_slot; + if ((8+response_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_pawr_sync_set_response_data.response_data.len=response_data_len; + memcpy(cmd->data.cmd_pawr_sync_set_response_data.response_data.data,response_data,response_data_len); + + cmd->header=sl_bt_cmd_pawr_sync_set_response_data_id+(((8+response_data_len)&0xff)<<8)+(((8+response_data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_pawr_sync_set_response_data.result; + +} + +sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags, + uint8_t num_subevents, + uint8_t subevent_interval, + uint8_t response_slot_delay, + uint8_t response_slot_spacing, + uint8_t response_slots) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_advertiser_start.advertising_set=advertising_set; + cmd->data.cmd_pawr_advertiser_start.interval_min=interval_min; + cmd->data.cmd_pawr_advertiser_start.interval_max=interval_max; + cmd->data.cmd_pawr_advertiser_start.flags=flags; + cmd->data.cmd_pawr_advertiser_start.num_subevents=num_subevents; + cmd->data.cmd_pawr_advertiser_start.subevent_interval=subevent_interval; + cmd->data.cmd_pawr_advertiser_start.response_slot_delay=response_slot_delay; + cmd->data.cmd_pawr_advertiser_start.response_slot_spacing=response_slot_spacing; + cmd->data.cmd_pawr_advertiser_start.response_slots=response_slots; + + cmd->header=sl_bt_cmd_pawr_advertiser_start_id+(((14)&0xff)<<8)+(((14)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_pawr_advertiser_start.result; + +} + +sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, + uint8_t subevent, + uint8_t response_slot_start, + uint8_t response_slot_count, + size_t adv_data_len, + const uint8_t* adv_data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_advertiser_set_subevent_data.advertising_set=advertising_set; + cmd->data.cmd_pawr_advertiser_set_subevent_data.subevent=subevent; + cmd->data.cmd_pawr_advertiser_set_subevent_data.response_slot_start=response_slot_start; + cmd->data.cmd_pawr_advertiser_set_subevent_data.response_slot_count=response_slot_count; + if ((5+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_pawr_advertiser_set_subevent_data.adv_data.len=adv_data_len; + memcpy(cmd->data.cmd_pawr_advertiser_set_subevent_data.adv_data.data,adv_data,adv_data_len); + + cmd->header=sl_bt_cmd_pawr_advertiser_set_subevent_data_id+(((5+adv_data_len)&0xff)<<8)+(((5+adv_data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_pawr_advertiser_set_subevent_data.result; + +} + +sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, + uint8_t subevent, + bd_addr address, + uint8_t address_type, + uint8_t *connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_advertiser_create_connection.advertising_set=advertising_set; + cmd->data.cmd_pawr_advertiser_create_connection.subevent=subevent; + memcpy(&cmd->data.cmd_pawr_advertiser_create_connection.address,&address,sizeof(bd_addr)); + cmd->data.cmd_pawr_advertiser_create_connection.address_type=address_type; + + cmd->header=sl_bt_cmd_pawr_advertiser_create_connection_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (connection) { + *connection = rsp->data.rsp_pawr_advertiser_create_connection.connection; + } + return rsp->data.rsp_pawr_advertiser_create_connection.result; + +} + +sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_pawr_advertiser_stop.advertising_set=advertising_set; + + cmd->header=sl_bt_cmd_pawr_advertiser_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_pawr_advertiser_stop.result; + +} + +sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_default_parameters.min_interval=min_interval; + cmd->data.cmd_connection_set_default_parameters.max_interval=max_interval; + cmd->data.cmd_connection_set_default_parameters.latency=latency; + cmd->data.cmd_connection_set_default_parameters.timeout=timeout; + cmd->data.cmd_connection_set_default_parameters.min_ce_length=min_ce_length; + cmd->data.cmd_connection_set_default_parameters.max_ce_length=max_ce_length; + + cmd->header=sl_bt_cmd_connection_set_default_parameters_id+(((12)&0xff)<<8)+(((12)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_default_parameters.result; + +} + +sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, + uint8_t accepted_phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_default_preferred_phy.preferred_phy=preferred_phy; + cmd->data.cmd_connection_set_default_preferred_phy.accepted_phy=accepted_phy; + + cmd->header=sl_bt_cmd_connection_set_default_preferred_phy_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_default_preferred_phy.result; + +} + +sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_default_data_length.tx_data_len=tx_data_len; + + cmd->header=sl_bt_cmd_connection_set_default_data_length_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_default_data_length.result; + +} + +sl_status_t sl_bt_connection_open(bd_addr address, + uint8_t address_type, + uint8_t initiating_phy, + uint8_t *connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_connection_open.address,&address,sizeof(bd_addr)); + cmd->data.cmd_connection_open.address_type=address_type; + cmd->data.cmd_connection_open.initiating_phy=initiating_phy; + + cmd->header=sl_bt_cmd_connection_open_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (connection) { + *connection = rsp->data.rsp_connection_open.connection; + } + return rsp->data.rsp_connection_open.result; + +} + +sl_status_t sl_bt_connection_set_parameters(uint8_t connection, + uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_parameters.connection=connection; + cmd->data.cmd_connection_set_parameters.min_interval=min_interval; + cmd->data.cmd_connection_set_parameters.max_interval=max_interval; + cmd->data.cmd_connection_set_parameters.latency=latency; + cmd->data.cmd_connection_set_parameters.timeout=timeout; + cmd->data.cmd_connection_set_parameters.min_ce_length=min_ce_length; + cmd->data.cmd_connection_set_parameters.max_ce_length=max_ce_length; + + cmd->header=sl_bt_cmd_connection_set_parameters_id+(((13)&0xff)<<8)+(((13)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_parameters.result; + +} + +sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, + uint8_t preferred_phy, + uint8_t accepted_phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_preferred_phy.connection=connection; + cmd->data.cmd_connection_set_preferred_phy.preferred_phy=preferred_phy; + cmd->data.cmd_connection_set_preferred_phy.accepted_phy=accepted_phy; + + cmd->header=sl_bt_cmd_connection_set_preferred_phy_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_preferred_phy.result; + +} + +sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, + uint8_t disable) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_disable_slave_latency.connection=connection; + cmd->data.cmd_connection_disable_slave_latency.disable=disable; + + cmd->header=sl_bt_cmd_connection_disable_slave_latency_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_disable_slave_latency.result; + +} + +sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_median_rssi.connection=connection; + + cmd->header=sl_bt_cmd_connection_get_median_rssi_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (rssi) { + *rssi = rsp->data.rsp_connection_get_median_rssi.rssi; + } + return rsp->data.rsp_connection_get_median_rssi.result; + +} + +sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, + size_t max_channel_map_size, + size_t *channel_map_len, + uint8_t *channel_map) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_read_channel_map.connection=connection; + + cmd->header=sl_bt_cmd_connection_read_channel_map_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (channel_map_len) { + *channel_map_len = rsp->data.rsp_connection_read_channel_map.channel_map.len; + } + if (channel_map && (rsp->data.rsp_connection_read_channel_map.channel_map.len <= max_channel_map_size)) { + memcpy(channel_map,rsp->data.rsp_connection_read_channel_map.channel_map.data,rsp->data.rsp_connection_read_channel_map.channel_map.len); + } + return rsp->data.rsp_connection_read_channel_map.result; + +} + +sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, + uint8_t mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_power_reporting.connection=connection; + cmd->data.cmd_connection_set_power_reporting.mode=mode; + + cmd->header=sl_bt_cmd_connection_set_power_reporting_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_power_reporting.result; + +} + +sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, + uint8_t mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_remote_power_reporting.connection=connection; + cmd->data.cmd_connection_set_remote_power_reporting.mode=mode; + + cmd->header=sl_bt_cmd_connection_set_remote_power_reporting_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_remote_power_reporting.result; + +} + +sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, + uint8_t phy, + int8_t *current_level, + int8_t *max_level) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_tx_power.connection=connection; + cmd->data.cmd_connection_get_tx_power.phy=phy; + + cmd->header=sl_bt_cmd_connection_get_tx_power_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (current_level) { + *current_level = rsp->data.rsp_connection_get_tx_power.current_level; + } + if (max_level) { + *max_level = rsp->data.rsp_connection_get_tx_power.max_level; + } + return rsp->data.rsp_connection_get_tx_power.result; + +} + +sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, + uint8_t phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_remote_tx_power.connection=connection; + cmd->data.cmd_connection_get_remote_tx_power.phy=phy; + + cmd->header=sl_bt_cmd_connection_get_remote_tx_power_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_get_remote_tx_power.result; + +} + +sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, + int16_t tx_power, + int16_t *tx_power_out) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_tx_power.connection=connection; + cmd->data.cmd_connection_set_tx_power.tx_power=tx_power; + + cmd->header=sl_bt_cmd_connection_set_tx_power_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (tx_power_out) { + *tx_power_out = rsp->data.rsp_connection_set_tx_power.tx_power_out; + } + return rsp->data.rsp_connection_set_tx_power.result; + +} + +sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_read_remote_used_features.connection=connection; + + cmd->header=sl_bt_cmd_connection_read_remote_used_features_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_read_remote_used_features.result; + +} + +sl_status_t sl_bt_connection_get_security_status(uint8_t connection, + uint8_t *security_mode, + uint8_t *key_size, + uint8_t *bonding_handle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_security_status.connection=connection; + + cmd->header=sl_bt_cmd_connection_get_security_status_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (security_mode) { + *security_mode = rsp->data.rsp_connection_get_security_status.security_mode; + } + if (key_size) { + *key_size = rsp->data.rsp_connection_get_security_status.key_size; + } + if (bonding_handle) { + *bonding_handle = rsp->data.rsp_connection_get_security_status.bonding_handle; + } + return rsp->data.rsp_connection_get_security_status.result; + +} + +sl_status_t sl_bt_connection_set_data_length(uint8_t connection, + uint16_t tx_data_len, + uint16_t tx_time_us) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_set_data_length.connection=connection; + cmd->data.cmd_connection_set_data_length.tx_data_len=tx_data_len; + cmd->data.cmd_connection_set_data_length.tx_time_us=tx_time_us; + + cmd->header=sl_bt_cmd_connection_set_data_length_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_set_data_length.result; + +} + +sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_read_statistics.connection=connection; + cmd->data.cmd_connection_read_statistics.reset=reset; + + cmd->header=sl_bt_cmd_connection_read_statistics_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_read_statistics.result; + +} + +sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, + uint32_t *access_address, + uint8_t *role, + uint32_t *crc_init, + uint16_t *interval, + uint16_t *supervision_timeout, + uint8_t *central_clock_accuracy, + uint8_t *central_phy, + uint8_t *peripheral_phy, + uint8_t *channel_selection_algorithm, + uint8_t *hop, + sl_bt_connection_channel_map_t *channel_map, + uint8_t *channel, + uint16_t *event_counter, + uint32_t *start_time_us) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_scheduling_details.connection=connection; + + cmd->header=sl_bt_cmd_connection_get_scheduling_details_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (access_address) { + *access_address = rsp->data.rsp_connection_get_scheduling_details.access_address; + } + if (role) { + *role = rsp->data.rsp_connection_get_scheduling_details.role; + } + if (crc_init) { + *crc_init = rsp->data.rsp_connection_get_scheduling_details.crc_init; + } + if (interval) { + *interval = rsp->data.rsp_connection_get_scheduling_details.interval; + } + if (supervision_timeout) { + *supervision_timeout = rsp->data.rsp_connection_get_scheduling_details.supervision_timeout; + } + if (central_clock_accuracy) { + *central_clock_accuracy = rsp->data.rsp_connection_get_scheduling_details.central_clock_accuracy; + } + if (central_phy) { + *central_phy = rsp->data.rsp_connection_get_scheduling_details.central_phy; + } + if (peripheral_phy) { + *peripheral_phy = rsp->data.rsp_connection_get_scheduling_details.peripheral_phy; + } + if (channel_selection_algorithm) { + *channel_selection_algorithm = rsp->data.rsp_connection_get_scheduling_details.channel_selection_algorithm; + } + if (hop) { + *hop = rsp->data.rsp_connection_get_scheduling_details.hop; + } + if (channel_map) { + memcpy(channel_map,&rsp->data.rsp_connection_get_scheduling_details.channel_map,sizeof(sl_bt_connection_channel_map_t)); + } + if (channel) { + *channel = rsp->data.rsp_connection_get_scheduling_details.channel; + } + if (event_counter) { + *event_counter = rsp->data.rsp_connection_get_scheduling_details.event_counter; + } + if (start_time_us) { + *start_time_us = rsp->data.rsp_connection_get_scheduling_details.start_time_us; + } + return rsp->data.rsp_connection_get_scheduling_details.result; + +} + +sl_status_t sl_bt_connection_close(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_close.connection=connection; + + cmd->header=sl_bt_cmd_connection_close_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_close.result; + +} + +sl_status_t sl_bt_connection_forcefully_close(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_forcefully_close.connection=connection; + + cmd->header=sl_bt_cmd_connection_forcefully_close_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_forcefully_close.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_get_rssi.connection=connection; + + cmd->header=sl_bt_cmd_connection_get_rssi_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_get_rssi.result; + +} + +sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_set_max_mtu.max_mtu=max_mtu; + + cmd->header=sl_bt_cmd_gatt_set_max_mtu_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (max_mtu_out) { + *max_mtu_out = rsp->data.rsp_gatt_set_max_mtu.max_mtu_out; + } + return rsp->data.rsp_gatt_set_max_mtu.result; + +} + +sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_primary_services.connection=connection; + + cmd->header=sl_bt_cmd_gatt_discover_primary_services_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_primary_services.result; + +} + +sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, + size_t uuid_len, + const uint8_t* uuid) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_primary_services_by_uuid.connection=connection; + if ((2+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.len=uuid_len; + memcpy(cmd->data.cmd_gatt_discover_primary_services_by_uuid.uuid.data,uuid,uuid_len); + + cmd->header=sl_bt_cmd_gatt_discover_primary_services_by_uuid_id+(((2+uuid_len)&0xff)<<8)+(((2+uuid_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_primary_services_by_uuid.result; + +} + +sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, + uint32_t service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_find_included_services.connection=connection; + cmd->data.cmd_gatt_find_included_services.service=service; + + cmd->header=sl_bt_cmd_gatt_find_included_services_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_find_included_services.result; + +} + +sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, + uint32_t service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_characteristics.connection=connection; + cmd->data.cmd_gatt_discover_characteristics.service=service; + + cmd->header=sl_bt_cmd_gatt_discover_characteristics_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_characteristics.result; + +} + +sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_characteristics_by_uuid.connection=connection; + cmd->data.cmd_gatt_discover_characteristics_by_uuid.service=service; + if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.len=uuid_len; + memcpy(cmd->data.cmd_gatt_discover_characteristics_by_uuid.uuid.data,uuid,uuid_len); + + cmd->header=sl_bt_cmd_gatt_discover_characteristics_by_uuid_id+(((6+uuid_len)&0xff)<<8)+(((6+uuid_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_characteristics_by_uuid.result; + +} + +sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, + uint16_t characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_descriptors.connection=connection; + cmd->data.cmd_gatt_discover_descriptors.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gatt_discover_descriptors_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_descriptors.result; + +} + +sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, + uint16_t start, + uint16_t end) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_discover_characteristic_descriptors.connection=connection; + cmd->data.cmd_gatt_discover_characteristic_descriptors.start=start; + cmd->data.cmd_gatt_discover_characteristic_descriptors.end=end; + + cmd->header=sl_bt_cmd_gatt_discover_characteristic_descriptors_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_discover_characteristic_descriptors.result; + +} + +sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, + uint16_t characteristic, + uint8_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_set_characteristic_notification.connection=connection; + cmd->data.cmd_gatt_set_characteristic_notification.characteristic=characteristic; + cmd->data.cmd_gatt_set_characteristic_notification.flags=flags; + + cmd->header=sl_bt_cmd_gatt_set_characteristic_notification_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_set_characteristic_notification.result; + +} + +sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_send_characteristic_confirmation.connection=connection; + + cmd->header=sl_bt_cmd_gatt_send_characteristic_confirmation_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_send_characteristic_confirmation.result; + +} + +sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, + uint16_t characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_read_characteristic_value.connection=connection; + cmd->data.cmd_gatt_read_characteristic_value.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gatt_read_characteristic_value_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_read_characteristic_value.result; + +} + +sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + uint16_t maxlen) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_read_characteristic_value_from_offset.connection=connection; + cmd->data.cmd_gatt_read_characteristic_value_from_offset.characteristic=characteristic; + cmd->data.cmd_gatt_read_characteristic_value_from_offset.offset=offset; + cmd->data.cmd_gatt_read_characteristic_value_from_offset.maxlen=maxlen; + + cmd->header=sl_bt_cmd_gatt_read_characteristic_value_from_offset_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_read_characteristic_value_from_offset.result; + +} + +sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, + size_t characteristic_list_len, + const uint8_t* characteristic_list) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_read_multiple_characteristic_values.connection=connection; + if ((2+characteristic_list_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.len=characteristic_list_len; + memcpy(cmd->data.cmd_gatt_read_multiple_characteristic_values.characteristic_list.data,characteristic_list,characteristic_list_len); + + cmd->header=sl_bt_cmd_gatt_read_multiple_characteristic_values_id+(((2+characteristic_list_len)&0xff)<<8)+(((2+characteristic_list_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_read_multiple_characteristic_values.result; + +} + +sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_read_characteristic_value_by_uuid.connection=connection; + cmd->data.cmd_gatt_read_characteristic_value_by_uuid.service=service; + if ((6+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.len=uuid_len; + memcpy(cmd->data.cmd_gatt_read_characteristic_value_by_uuid.uuid.data,uuid,uuid_len); + + cmd->header=sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id+(((6+uuid_len)&0xff)<<8)+(((6+uuid_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_read_characteristic_value_by_uuid.result; + +} + +sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_write_characteristic_value.connection=connection; + cmd->data.cmd_gatt_write_characteristic_value.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_write_characteristic_value.value.len=value_len; + memcpy(cmd->data.cmd_gatt_write_characteristic_value.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_write_characteristic_value_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_write_characteristic_value.result; + +} + +sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_write_characteristic_value_without_response.connection=connection; + cmd->data.cmd_gatt_write_characteristic_value_without_response.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_write_characteristic_value_without_response.value.len=value_len; + memcpy(cmd->data.cmd_gatt_write_characteristic_value_without_response.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_write_characteristic_value_without_response_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sent_len) { + *sent_len = rsp->data.rsp_gatt_write_characteristic_value_without_response.sent_len; + } + return rsp->data.rsp_gatt_write_characteristic_value_without_response.result; + +} + +sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_prepare_characteristic_value_write.connection=connection; + cmd->data.cmd_gatt_prepare_characteristic_value_write.characteristic=characteristic; + cmd->data.cmd_gatt_prepare_characteristic_value_write.offset=offset; + if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_prepare_characteristic_value_write.value.len=value_len; + memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_write.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_prepare_characteristic_value_write_id+(((6+value_len)&0xff)<<8)+(((6+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sent_len) { + *sent_len = rsp->data.rsp_gatt_prepare_characteristic_value_write.sent_len; + } + return rsp->data.rsp_gatt_prepare_characteristic_value_write.result; + +} + +sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.connection=connection; + cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.characteristic=characteristic; + cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.offset=offset; + if ((6+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.len=value_len; + memcpy(cmd->data.cmd_gatt_prepare_characteristic_value_reliable_write.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id+(((6+value_len)&0xff)<<8)+(((6+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sent_len) { + *sent_len = rsp->data.rsp_gatt_prepare_characteristic_value_reliable_write.sent_len; + } + return rsp->data.rsp_gatt_prepare_characteristic_value_reliable_write.result; + +} + +sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, + uint8_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_execute_characteristic_value_write.connection=connection; + cmd->data.cmd_gatt_execute_characteristic_value_write.flags=flags; + + cmd->header=sl_bt_cmd_gatt_execute_characteristic_value_write_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_execute_characteristic_value_write.result; + +} + +sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, + uint16_t descriptor) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_read_descriptor_value.connection=connection; + cmd->data.cmd_gatt_read_descriptor_value.descriptor=descriptor; + + cmd->header=sl_bt_cmd_gatt_read_descriptor_value_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_read_descriptor_value.result; + +} + +sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, + uint16_t descriptor, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_write_descriptor_value.connection=connection; + cmd->data.cmd_gatt_write_descriptor_value.descriptor=descriptor; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_write_descriptor_value.value.len=value_len; + memcpy(cmd->data.cmd_gatt_write_descriptor_value.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_write_descriptor_value_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_write_descriptor_value.result; + +} + +sl_status_t sl_bt_gattdb_new_session(uint16_t *session) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_gattdb_new_session_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (session) { + *session = rsp->data.rsp_gattdb_new_session.session; + } + return rsp->data.rsp_gattdb_new_session.result; + +} + +sl_status_t sl_bt_gattdb_add_service(uint16_t session, + uint8_t type, + uint8_t property, + size_t uuid_len, + const uint8_t* uuid, + uint16_t *service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_service.session=session; + cmd->data.cmd_gattdb_add_service.type=type; + cmd->data.cmd_gattdb_add_service.property=property; + if ((5+uuid_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gattdb_add_service.uuid.len=uuid_len; + memcpy(cmd->data.cmd_gattdb_add_service.uuid.data,uuid,uuid_len); + + cmd->header=sl_bt_cmd_gattdb_add_service_id+(((5+uuid_len)&0xff)<<8)+(((5+uuid_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (service) { + *service = rsp->data.rsp_gattdb_add_service.service; + } + return rsp->data.rsp_gattdb_add_service.result; + +} + +sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_remove_service.session=session; + cmd->data.cmd_gattdb_remove_service.service=service; + + cmd->header=sl_bt_cmd_gattdb_remove_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_remove_service.result; + +} + +sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, + uint16_t service, + uint16_t included_service, + uint16_t *attribute) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_included_service.session=session; + cmd->data.cmd_gattdb_add_included_service.service=service; + cmd->data.cmd_gattdb_add_included_service.included_service=included_service; + + cmd->header=sl_bt_cmd_gattdb_add_included_service_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (attribute) { + *attribute = rsp->data.rsp_gattdb_add_included_service.attribute; + } + return rsp->data.rsp_gattdb_add_included_service.result; + +} + +sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, + uint16_t attribute) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_remove_included_service.session=session; + cmd->data.cmd_gattdb_remove_included_service.attribute=attribute; + + cmd->header=sl_bt_cmd_gattdb_remove_included_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_remove_included_service.result; + +} + +sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_uuid16_characteristic.session=session; + cmd->data.cmd_gattdb_add_uuid16_characteristic.service=service; + cmd->data.cmd_gattdb_add_uuid16_characteristic.property=property; + cmd->data.cmd_gattdb_add_uuid16_characteristic.security=security; + cmd->data.cmd_gattdb_add_uuid16_characteristic.flag=flag; + cmd->data.cmd_gattdb_add_uuid16_characteristic.uuid=uuid; + cmd->data.cmd_gattdb_add_uuid16_characteristic.value_type=value_type; + cmd->data.cmd_gattdb_add_uuid16_characteristic.maxlen=maxlen; + if ((16+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gattdb_add_uuid16_characteristic.value.len=value_len; + memcpy(cmd->data.cmd_gattdb_add_uuid16_characteristic.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gattdb_add_uuid16_characteristic_id+(((16+value_len)&0xff)<<8)+(((16+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (characteristic) { + *characteristic = rsp->data.rsp_gattdb_add_uuid16_characteristic.characteristic; + } + return rsp->data.rsp_gattdb_add_uuid16_characteristic.result; + +} + +sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_uuid128_characteristic.session=session; + cmd->data.cmd_gattdb_add_uuid128_characteristic.service=service; + cmd->data.cmd_gattdb_add_uuid128_characteristic.property=property; + cmd->data.cmd_gattdb_add_uuid128_characteristic.security=security; + cmd->data.cmd_gattdb_add_uuid128_characteristic.flag=flag; + cmd->data.cmd_gattdb_add_uuid128_characteristic.uuid=uuid; + cmd->data.cmd_gattdb_add_uuid128_characteristic.value_type=value_type; + cmd->data.cmd_gattdb_add_uuid128_characteristic.maxlen=maxlen; + if ((30+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gattdb_add_uuid128_characteristic.value.len=value_len; + memcpy(cmd->data.cmd_gattdb_add_uuid128_characteristic.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gattdb_add_uuid128_characteristic_id+(((30+value_len)&0xff)<<8)+(((30+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (characteristic) { + *characteristic = rsp->data.rsp_gattdb_add_uuid128_characteristic.characteristic; + } + return rsp->data.rsp_gattdb_add_uuid128_characteristic.result; + +} + +sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, + uint16_t characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_remove_characteristic.session=session; + cmd->data.cmd_gattdb_remove_characteristic.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gattdb_remove_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_remove_characteristic.result; + +} + +sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_uuid16_descriptor.session=session; + cmd->data.cmd_gattdb_add_uuid16_descriptor.characteristic=characteristic; + cmd->data.cmd_gattdb_add_uuid16_descriptor.property=property; + cmd->data.cmd_gattdb_add_uuid16_descriptor.security=security; + cmd->data.cmd_gattdb_add_uuid16_descriptor.uuid=uuid; + cmd->data.cmd_gattdb_add_uuid16_descriptor.value_type=value_type; + cmd->data.cmd_gattdb_add_uuid16_descriptor.maxlen=maxlen; + if ((15+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gattdb_add_uuid16_descriptor.value.len=value_len; + memcpy(cmd->data.cmd_gattdb_add_uuid16_descriptor.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gattdb_add_uuid16_descriptor_id+(((15+value_len)&0xff)<<8)+(((15+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (descriptor) { + *descriptor = rsp->data.rsp_gattdb_add_uuid16_descriptor.descriptor; + } + return rsp->data.rsp_gattdb_add_uuid16_descriptor.result; + +} + +sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_add_uuid128_descriptor.session=session; + cmd->data.cmd_gattdb_add_uuid128_descriptor.characteristic=characteristic; + cmd->data.cmd_gattdb_add_uuid128_descriptor.property=property; + cmd->data.cmd_gattdb_add_uuid128_descriptor.security=security; + cmd->data.cmd_gattdb_add_uuid128_descriptor.uuid=uuid; + cmd->data.cmd_gattdb_add_uuid128_descriptor.value_type=value_type; + cmd->data.cmd_gattdb_add_uuid128_descriptor.maxlen=maxlen; + if ((29+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gattdb_add_uuid128_descriptor.value.len=value_len; + memcpy(cmd->data.cmd_gattdb_add_uuid128_descriptor.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gattdb_add_uuid128_descriptor_id+(((29+value_len)&0xff)<<8)+(((29+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (descriptor) { + *descriptor = rsp->data.rsp_gattdb_add_uuid128_descriptor.descriptor; + } + return rsp->data.rsp_gattdb_add_uuid128_descriptor.result; + +} + +sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, + uint16_t descriptor) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_remove_descriptor.session=session; + cmd->data.cmd_gattdb_remove_descriptor.descriptor=descriptor; + + cmd->header=sl_bt_cmd_gattdb_remove_descriptor_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_remove_descriptor.result; + +} + +sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_start_service.session=session; + cmd->data.cmd_gattdb_start_service.service=service; + + cmd->header=sl_bt_cmd_gattdb_start_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_start_service.result; + +} + +sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_stop_service.session=session; + cmd->data.cmd_gattdb_stop_service.service=service; + + cmd->header=sl_bt_cmd_gattdb_stop_service_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_stop_service.result; + +} + +sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, + uint16_t characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_start_characteristic.session=session; + cmd->data.cmd_gattdb_start_characteristic.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gattdb_start_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_start_characteristic.result; + +} + +sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, + uint16_t characteristic) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_stop_characteristic.session=session; + cmd->data.cmd_gattdb_stop_characteristic.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gattdb_stop_characteristic_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_stop_characteristic.result; + +} + +sl_status_t sl_bt_gattdb_commit(uint16_t session) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_commit.session=session; + + cmd->header=sl_bt_cmd_gattdb_commit_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_commit.result; + +} + +sl_status_t sl_bt_gattdb_abort(uint16_t session) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gattdb_abort.session=session; + + cmd->header=sl_bt_cmd_gattdb_abort_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gattdb_abort.result; + +} + +sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, + uint16_t *max_mtu_out) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_set_max_mtu.max_mtu=max_mtu; + + cmd->header=sl_bt_cmd_gatt_server_set_max_mtu_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (max_mtu_out) { + *max_mtu_out = rsp->data.rsp_gatt_server_set_max_mtu.max_mtu_out; + } + return rsp->data.rsp_gatt_server_set_max_mtu.result; + +} + +sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_get_mtu.connection=connection; + + cmd->header=sl_bt_cmd_gatt_server_get_mtu_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (mtu) { + *mtu = rsp->data.rsp_gatt_server_get_mtu.mtu; + } + return rsp->data.rsp_gatt_server_get_mtu.result; + +} + +sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, + size_t type_len, + const uint8_t* type, + uint16_t *attribute) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_find_attribute.start=start; + if ((3+type_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_find_attribute.type.len=type_len; + memcpy(cmd->data.cmd_gatt_server_find_attribute.type.data,type,type_len); + + cmd->header=sl_bt_cmd_gatt_server_find_attribute_id+(((3+type_len)&0xff)<<8)+(((3+type_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (attribute) { + *attribute = rsp->data.rsp_gatt_server_find_attribute.attribute; + } + return rsp->data.rsp_gatt_server_find_attribute.result; + +} + +sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, + uint16_t offset, + size_t max_value_size, + size_t *value_len, + uint8_t *value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_read_attribute_value.attribute=attribute; + cmd->data.cmd_gatt_server_read_attribute_value.offset=offset; + + cmd->header=sl_bt_cmd_gatt_server_read_attribute_value_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (value_len) { + *value_len = rsp->data.rsp_gatt_server_read_attribute_value.value.len; + } + if (value && (rsp->data.rsp_gatt_server_read_attribute_value.value.len <= max_value_size)) { + memcpy(value,rsp->data.rsp_gatt_server_read_attribute_value.value.data,rsp->data.rsp_gatt_server_read_attribute_value.value.len); + } + return rsp->data.rsp_gatt_server_read_attribute_value.result; + +} + +sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, + size_t max_type_size, + size_t *type_len, + uint8_t *type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_read_attribute_type.attribute=attribute; + + cmd->header=sl_bt_cmd_gatt_server_read_attribute_type_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (type_len) { + *type_len = rsp->data.rsp_gatt_server_read_attribute_type.type.len; + } + if (type && (rsp->data.rsp_gatt_server_read_attribute_type.type.len <= max_type_size)) { + memcpy(type,rsp->data.rsp_gatt_server_read_attribute_type.type.data,rsp->data.rsp_gatt_server_read_attribute_type.type.len); + } + return rsp->data.rsp_gatt_server_read_attribute_type.result; + +} + +sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, + uint16_t offset, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_write_attribute_value.attribute=attribute; + cmd->data.cmd_gatt_server_write_attribute_value.offset=offset; + if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_write_attribute_value.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_write_attribute_value.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_write_attribute_value_id+(((5+value_len)&0xff)<<8)+(((5+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_write_attribute_value.result; + +} + +sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_send_user_read_response.connection=connection; + cmd->data.cmd_gatt_server_send_user_read_response.characteristic=characteristic; + cmd->data.cmd_gatt_server_send_user_read_response.att_errorcode=att_errorcode; + if ((5+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_send_user_read_response.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_send_user_read_response.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_send_user_read_response_id+(((5+value_len)&0xff)<<8)+(((5+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (sent_len) { + *sent_len = rsp->data.rsp_gatt_server_send_user_read_response.sent_len; + } + return rsp->data.rsp_gatt_server_send_user_read_response.result; + +} + +sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_send_user_write_response.connection=connection; + cmd->data.cmd_gatt_server_send_user_write_response.characteristic=characteristic; + cmd->data.cmd_gatt_server_send_user_write_response.att_errorcode=att_errorcode; + + cmd->header=sl_bt_cmd_gatt_server_send_user_write_response_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_send_user_write_response.result; + +} + +sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_send_notification.connection=connection; + cmd->data.cmd_gatt_server_send_notification.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_send_notification.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_send_notification.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_send_notification_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_send_notification.result; + +} + +sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_send_indication.connection=connection; + cmd->data.cmd_gatt_server_send_indication.characteristic=characteristic; + if ((4+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_send_indication.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_send_indication.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_send_indication_id+(((4+value_len)&0xff)<<8)+(((4+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_send_indication.result; + +} + +sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_notify_all.characteristic=characteristic; + if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_notify_all.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_notify_all.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_notify_all_id+(((3+value_len)&0xff)<<8)+(((3+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_notify_all.result; + +} + +sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, + uint16_t characteristic, + uint16_t *client_config_flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_read_client_configuration.connection=connection; + cmd->data.cmd_gatt_server_read_client_configuration.characteristic=characteristic; + + cmd->header=sl_bt_cmd_gatt_server_read_client_configuration_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (client_config_flags) { + *client_config_flags = rsp->data.rsp_gatt_server_read_client_configuration.client_config_flags; + } + return rsp->data.rsp_gatt_server_read_client_configuration.result; + +} + +sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + uint16_t offset, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_send_user_prepare_write_response.connection=connection; + cmd->data.cmd_gatt_server_send_user_prepare_write_response.characteristic=characteristic; + cmd->data.cmd_gatt_server_send_user_prepare_write_response.att_errorcode=att_errorcode; + cmd->data.cmd_gatt_server_send_user_prepare_write_response.offset=offset; + if ((7+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.len=value_len; + memcpy(cmd->data.cmd_gatt_server_send_user_prepare_write_response.value.data,value,value_len); + + cmd->header=sl_bt_cmd_gatt_server_send_user_prepare_write_response_id+(((7+value_len)&0xff)<<8)+(((7+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_send_user_prepare_write_response.result; + +} + +sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, + uint32_t reserved) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_set_capabilities.caps=caps; + cmd->data.cmd_gatt_server_set_capabilities.reserved=reserved; + + cmd->header=sl_bt_cmd_gatt_server_set_capabilities_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_set_capabilities.result; + +} + +sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_enable_capabilities.caps=caps; + + cmd->header=sl_bt_cmd_gatt_server_enable_capabilities_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_enable_capabilities.result; + +} + +sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_disable_capabilities.caps=caps; + + cmd->header=sl_bt_cmd_gatt_server_disable_capabilities_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_gatt_server_disable_capabilities.result; + +} + +sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_gatt_server_get_enabled_capabilities_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (caps) { + *caps = rsp->data.rsp_gatt_server_get_enabled_capabilities.caps; + } + return rsp->data.rsp_gatt_server_get_enabled_capabilities.result; + +} + +sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, + uint8_t *client_features) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_gatt_server_read_client_supported_features.connection=connection; + + cmd->header=sl_bt_cmd_gatt_server_read_client_supported_features_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (client_features) { + *client_features = rsp->data.rsp_gatt_server_read_client_supported_features.client_features; + } + return rsp->data.rsp_gatt_server_read_client_supported_features.result; + +} + +sl_status_t sl_bt_nvm_save(uint16_t key, + size_t value_len, + const uint8_t* value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_nvm_save.key=key; + if ((3+value_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_nvm_save.value.len=value_len; + memcpy(cmd->data.cmd_nvm_save.value.data,value,value_len); + + cmd->header=sl_bt_cmd_nvm_save_id+(((3+value_len)&0xff)<<8)+(((3+value_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_nvm_save.result; + +} + +sl_status_t sl_bt_nvm_load(uint16_t key, + size_t max_value_size, + size_t *value_len, + uint8_t *value) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_nvm_load.key=key; + + cmd->header=sl_bt_cmd_nvm_load_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (value_len) { + *value_len = rsp->data.rsp_nvm_load.value.len; + } + if (value && (rsp->data.rsp_nvm_load.value.len <= max_value_size)) { + memcpy(value,rsp->data.rsp_nvm_load.value.data,rsp->data.rsp_nvm_load.value.len); + } + return rsp->data.rsp_nvm_load.result; + +} + +sl_status_t sl_bt_nvm_erase(uint16_t key) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_nvm_erase.key=key; + + cmd->header=sl_bt_cmd_nvm_erase_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_nvm_erase.result; + +} + +sl_status_t sl_bt_nvm_erase_all() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_nvm_erase_all_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_nvm_erase_all.result; + +} + +sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, + uint8_t length, + uint8_t channel, + uint8_t phy, + int8_t power_level) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_test_dtm_tx_v4.packet_type=packet_type; + cmd->data.cmd_test_dtm_tx_v4.length=length; + cmd->data.cmd_test_dtm_tx_v4.channel=channel; + cmd->data.cmd_test_dtm_tx_v4.phy=phy; + cmd->data.cmd_test_dtm_tx_v4.power_level=power_level; + + cmd->header=sl_bt_cmd_test_dtm_tx_v4_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_test_dtm_tx_v4.result; + +} + +sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, + uint8_t channel, + uint8_t phy, + int16_t power_level) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_test_dtm_tx_cw.packet_type=packet_type; + cmd->data.cmd_test_dtm_tx_cw.channel=channel; + cmd->data.cmd_test_dtm_tx_cw.phy=phy; + cmd->data.cmd_test_dtm_tx_cw.power_level=power_level; + + cmd->header=sl_bt_cmd_test_dtm_tx_cw_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_test_dtm_tx_cw.result; + +} + +sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_test_dtm_rx.channel=channel; + cmd->data.cmd_test_dtm_rx.phy=phy; + + cmd->header=sl_bt_cmd_test_dtm_rx_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_test_dtm_rx.result; + +} + +sl_status_t sl_bt_test_dtm_end() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_test_dtm_end_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_test_dtm_end.result; + +} + +sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_configure.flags=flags; + cmd->data.cmd_sm_configure.io_capabilities=io_capabilities; + + cmd->header=sl_bt_cmd_sm_configure_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_configure.result; + +} + +sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_minimum_key_size.minimum_key_size=minimum_key_size; + + cmd->header=sl_bt_cmd_sm_set_minimum_key_size_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_minimum_key_size.result; + +} + +sl_status_t sl_bt_sm_set_debug_mode() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_sm_set_debug_mode_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_debug_mode.result; + +} + +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_sm_add_to_whitelist.address,&address,sizeof(bd_addr)); + cmd->data.cmd_sm_add_to_whitelist.address_type=address_type; + + cmd->header=sl_bt_cmd_sm_add_to_whitelist_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_add_to_whitelist.result; + +} + +sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, + uint8_t policy_flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_store_bonding_configuration.max_bonding_count=max_bonding_count; + cmd->data.cmd_sm_store_bonding_configuration.policy_flags=policy_flags; + + cmd->header=sl_bt_cmd_sm_store_bonding_configuration_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_store_bonding_configuration.result; + +} + +sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_bondable_mode.bondable=bondable; + + cmd->header=sl_bt_cmd_sm_set_bondable_mode_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_bondable_mode.result; + +} + +sl_status_t sl_bt_sm_set_passkey(int32_t passkey) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_passkey.passkey=passkey; + + cmd->header=sl_bt_cmd_sm_set_passkey_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_passkey.result; + +} + +sl_status_t sl_bt_sm_increase_security(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_increase_security.connection=connection; + + cmd->header=sl_bt_cmd_sm_increase_security_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_increase_security.result; + +} + +sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_enter_passkey.connection=connection; + cmd->data.cmd_sm_enter_passkey.passkey=passkey; + + cmd->header=sl_bt_cmd_sm_enter_passkey_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_enter_passkey.result; + +} + +sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_passkey_confirm.connection=connection; + cmd->data.cmd_sm_passkey_confirm.confirm=confirm; + + cmd->header=sl_bt_cmd_sm_passkey_confirm_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_passkey_confirm.result; + +} + +sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_bonding_confirm.connection=connection; + cmd->data.cmd_sm_bonding_confirm.confirm=confirm; + + cmd->header=sl_bt_cmd_sm_bonding_confirm_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_bonding_confirm.result; + +} + +sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_delete_bonding.bonding=bonding; + + cmd->header=sl_bt_cmd_sm_delete_bonding_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_delete_bonding.result; + +} + +sl_status_t sl_bt_sm_delete_bondings() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_sm_delete_bondings_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_delete_bondings.result; + +} + +sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, + uint32_t *num_bondings, + size_t max_bondings_size, + size_t *bondings_len, + uint8_t *bondings) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_get_bonding_handles.reserved=reserved; + + cmd->header=sl_bt_cmd_sm_get_bonding_handles_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (num_bondings) { + *num_bondings = rsp->data.rsp_sm_get_bonding_handles.num_bondings; + } + if (bondings_len) { + *bondings_len = rsp->data.rsp_sm_get_bonding_handles.bondings.len; + } + if (bondings && (rsp->data.rsp_sm_get_bonding_handles.bondings.len <= max_bondings_size)) { + memcpy(bondings,rsp->data.rsp_sm_get_bonding_handles.bondings.data,rsp->data.rsp_sm_get_bonding_handles.bondings.len); + } + return rsp->data.rsp_sm_get_bonding_handles.result; + +} + +sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, + bd_addr *address, + uint8_t *address_type, + uint8_t *security_mode, + uint8_t *key_size) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_get_bonding_details.bonding=bonding; + + cmd->header=sl_bt_cmd_sm_get_bonding_details_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (address) { + memcpy(address,&rsp->data.rsp_sm_get_bonding_details.address,sizeof(bd_addr)); + } + if (address_type) { + *address_type = rsp->data.rsp_sm_get_bonding_details.address_type; + } + if (security_mode) { + *security_mode = rsp->data.rsp_sm_get_bonding_details.security_mode; + } + if (key_size) { + *key_size = rsp->data.rsp_sm_get_bonding_details.key_size; + } + return rsp->data.rsp_sm_get_bonding_details.result; + +} + +sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, + uint32_t *bonding, + uint8_t *security_mode, + uint8_t *key_size) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_sm_find_bonding_by_address.address,&address,sizeof(bd_addr)); + + cmd->header=sl_bt_cmd_sm_find_bonding_by_address_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (bonding) { + *bonding = rsp->data.rsp_sm_find_bonding_by_address.bonding; + } + if (security_mode) { + *security_mode = rsp->data.rsp_sm_find_bonding_by_address.security_mode; + } + if (key_size) { + *key_size = rsp->data.rsp_sm_find_bonding_by_address.key_size; + } + return rsp->data.rsp_sm_find_bonding_by_address.result; + +} + +sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, + bd_addr *address, + uint8_t *address_type, + uint32_t *bonding) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_sm_resolve_rpa.rpa,&rpa,sizeof(bd_addr)); + + cmd->header=sl_bt_cmd_sm_resolve_rpa_id+(((6)&0xff)<<8)+(((6)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (address) { + memcpy(address,&rsp->data.rsp_sm_resolve_rpa.address,sizeof(bd_addr)); + } + if (address_type) { + *address_type = rsp->data.rsp_sm_resolve_rpa.address_type; + } + if (bonding) { + *bonding = rsp->data.rsp_sm_resolve_rpa.bonding; + } + return rsp->data.rsp_sm_resolve_rpa.result; + +} + +sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, + uint8_t key_type, + aes_key_128 key) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_bonding_key.bonding=bonding; + cmd->data.cmd_sm_set_bonding_key.key_type=key_type; + memcpy(&cmd->data.cmd_sm_set_bonding_key.key,&key,sizeof(aes_key_128)); + + cmd->header=sl_bt_cmd_sm_set_bonding_key_id+(((21)&0xff)<<8)+(((21)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_bonding_key.result; + +} + +sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_legacy_oob.enable=enable; + memcpy(&cmd->data.cmd_sm_set_legacy_oob.oob_data,&oob_data,sizeof(aes_key_128)); + + cmd->header=sl_bt_cmd_sm_set_legacy_oob_id+(((17)&0xff)<<8)+(((17)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_legacy_oob.result; + +} + +sl_status_t sl_bt_sm_set_oob(uint8_t enable, + aes_key_128 *random, + aes_key_128 *confirm) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_oob.enable=enable; + + cmd->header=sl_bt_cmd_sm_set_oob_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (random) { + memcpy(random,&rsp->data.rsp_sm_set_oob.random,sizeof(aes_key_128)); + } + if (confirm) { + memcpy(confirm,&rsp->data.rsp_sm_set_oob.confirm,sizeof(aes_key_128)); + } + return rsp->data.rsp_sm_set_oob.result; + +} + +sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, + aes_key_128 random, + aes_key_128 confirm) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_remote_oob.enable=enable; + memcpy(&cmd->data.cmd_sm_set_remote_oob.random,&random,sizeof(aes_key_128)); + memcpy(&cmd->data.cmd_sm_set_remote_oob.confirm,&confirm,sizeof(aes_key_128)); + + cmd->header=sl_bt_cmd_sm_set_remote_oob_id+(((33)&0xff)<<8)+(((33)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_remote_oob.result; + +} + +sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_sm_set_bonding_data.connection=connection; + cmd->data.cmd_sm_set_bonding_data.type=type; + if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_sm_set_bonding_data.data.len=data_len; + memcpy(cmd->data.cmd_sm_set_bonding_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_sm_set_bonding_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_sm_set_bonding_data.result; + +} + +sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_external_bondingdb_set_data.connection=connection; + cmd->data.cmd_external_bondingdb_set_data.type=type; + if ((3+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_external_bondingdb_set_data.data.len=data_len; + memcpy(cmd->data.cmd_external_bondingdb_set_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_external_bondingdb_set_data_id+(((3+data_len)&0xff)<<8)+(((3+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_external_bondingdb_set_data.result; + +} + +sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, + uint8_t privacy_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_resolving_list_add_device_by_bonding.bonding=bonding; + cmd->data.cmd_resolving_list_add_device_by_bonding.privacy_mode=privacy_mode; + + cmd->header=sl_bt_cmd_resolving_list_add_device_by_bonding_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resolving_list_add_device_by_bonding.result; + +} + +sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, + uint8_t address_type, + aes_key_128 key, + uint8_t privacy_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_resolving_list_add_device_by_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_resolving_list_add_device_by_address.address_type=address_type; + memcpy(&cmd->data.cmd_resolving_list_add_device_by_address.key,&key,sizeof(aes_key_128)); + cmd->data.cmd_resolving_list_add_device_by_address.privacy_mode=privacy_mode; + + cmd->header=sl_bt_cmd_resolving_list_add_device_by_address_id+(((24)&0xff)<<8)+(((24)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resolving_list_add_device_by_address.result; + +} + +sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_resolving_list_remove_device_by_bonding.bonding=bonding; + + cmd->header=sl_bt_cmd_resolving_list_remove_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resolving_list_remove_device_by_bonding.result; + +} + +sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, + uint8_t address_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_resolving_list_remove_device_by_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_resolving_list_remove_device_by_address.address_type=address_type; + + cmd->header=sl_bt_cmd_resolving_list_remove_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resolving_list_remove_device_by_address.result; + +} + +sl_status_t sl_bt_resolving_list_remove_all_devices() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_resolving_list_remove_all_devices_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_resolving_list_remove_all_devices.result; + +} + +sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_accept_list_add_device_by_bonding.bonding=bonding; + + cmd->header=sl_bt_cmd_accept_list_add_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_accept_list_add_device_by_bonding.result; + +} + +sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, + uint8_t address_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_accept_list_add_device_by_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_accept_list_add_device_by_address.address_type=address_type; + + cmd->header=sl_bt_cmd_accept_list_add_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_accept_list_add_device_by_address.result; + +} + +sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_accept_list_remove_device_by_bonding.bonding=bonding; + + cmd->header=sl_bt_cmd_accept_list_remove_device_by_bonding_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_accept_list_remove_device_by_bonding.result; + +} + +sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, + uint8_t address_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_accept_list_remove_device_by_address.address,&address,sizeof(bd_addr)); + cmd->data.cmd_accept_list_remove_device_by_address.address_type=address_type; + + cmd->header=sl_bt_cmd_accept_list_remove_device_by_address_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_accept_list_remove_device_by_address.result; + +} + +sl_status_t sl_bt_accept_list_remove_all_devices() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_accept_list_remove_all_devices_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_accept_list_remove_all_devices.result; + +} + +sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+name_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_ota_set_device_name.name.len=name_len; + memcpy(cmd->data.cmd_ota_set_device_name.name.data,name,name_len); + + cmd->header=sl_bt_cmd_ota_set_device_name_id+(((1+name_len)&0xff)<<8)+(((1+name_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_ota_set_device_name.result; + +} + +sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_ota_set_advertising_data.packet_type=packet_type; + if ((2+adv_data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_ota_set_advertising_data.adv_data.len=adv_data_len; + memcpy(cmd->data.cmd_ota_set_advertising_data.adv_data.data,adv_data,adv_data_len); + + cmd->header=sl_bt_cmd_ota_set_advertising_data_id+(((2+adv_data_len)&0xff)<<8)+(((2+adv_data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_ota_set_advertising_data.result; + +} + +sl_status_t sl_bt_ota_set_configuration(uint32_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_ota_set_configuration.flags=flags; + + cmd->header=sl_bt_cmd_ota_set_configuration_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_ota_set_configuration.result; + +} + +sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_ota_set_rf_path.enable=enable; + cmd->data.cmd_ota_set_rf_path.antenna=antenna; + + cmd->header=sl_bt_cmd_ota_set_rf_path_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_ota_set_rf_path.result; + +} + +sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_coex_set_options.mask=mask; + cmd->data.cmd_coex_set_options.options=options; + + cmd->header=sl_bt_cmd_coex_set_options_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_coex_set_options.result; + +} + +sl_status_t sl_bt_coex_set_parameters(uint8_t priority, + uint8_t request, + uint8_t pwm_period, + uint8_t pwm_dutycycle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_coex_set_parameters.priority=priority; + cmd->data.cmd_coex_set_parameters.request=request; + cmd->data.cmd_coex_set_parameters.pwm_period=pwm_period; + cmd->data.cmd_coex_set_parameters.pwm_dutycycle=pwm_dutycycle; + + cmd->header=sl_bt_cmd_coex_set_parameters_id+(((4)&0xff)<<8)+(((4)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_coex_set_parameters.result; + +} + +sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_coex_set_directional_priority_pulse.pulse=pulse; + + cmd->header=sl_bt_cmd_coex_set_directional_priority_pulse_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_coex_set_directional_priority_pulse.result; + +} + +sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, + uint8_t *request, + uint8_t *pwm_period, + uint8_t *pwm_dutycycle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_coex_get_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (priority) { + *priority = rsp->data.rsp_coex_get_parameters.priority; + } + if (request) { + *request = rsp->data.rsp_coex_get_parameters.request; + } + if (pwm_period) { + *pwm_period = rsp->data.rsp_coex_get_parameters.pwm_period; + } + if (pwm_dutycycle) { + *pwm_dutycycle = rsp->data.rsp_coex_get_parameters.pwm_dutycycle; + } + return rsp->data.rsp_coex_get_parameters.result; + +} + +sl_status_t sl_bt_coex_get_counters(uint8_t reset, + size_t max_counters_size, + size_t *counters_len, + uint8_t *counters) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_coex_get_counters.reset=reset; + + cmd->header=sl_bt_cmd_coex_get_counters_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (counters_len) { + *counters_len = rsp->data.rsp_coex_get_counters.counters.len; + } + if (counters && (rsp->data.rsp_coex_get_counters.counters.len <= max_counters_size)) { + memcpy(counters,rsp->data.rsp_coex_get_counters.counters.data,rsp->data.rsp_coex_get_counters.counters.len); + } + return rsp->data.rsp_coex_get_counters.result; + +} + +sl_status_t sl_bt_cs_security_enable(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_security_enable.connection=connection; + + cmd->header=sl_bt_cmd_cs_security_enable_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_security_enable.result; + +} + +sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, + uint8_t initiator_status, + uint8_t reflector_status, + uint8_t antenna_identifier, + int8_t max_tx_power) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_set_default_settings.connection=connection; + cmd->data.cmd_cs_set_default_settings.initiator_status=initiator_status; + cmd->data.cmd_cs_set_default_settings.reflector_status=reflector_status; + cmd->data.cmd_cs_set_default_settings.antenna_identifier=antenna_identifier; + cmd->data.cmd_cs_set_default_settings.max_tx_power=max_tx_power; + + cmd->header=sl_bt_cmd_cs_set_default_settings_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_set_default_settings.result; + +} + +sl_status_t sl_bt_cs_create_config(uint8_t connection, + uint8_t config_id, + uint8_t create_context, + uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t min_main_mode_steps, + uint8_t max_main_mode_steps, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + const sl_bt_cs_channel_map_t *channel_map, + uint8_t channel_map_repetition, + uint8_t channel_selection_type, + uint8_t ch3c_shape, + uint8_t ch3c_jump, + uint8_t companion_signal_state) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_create_config.connection=connection; + cmd->data.cmd_cs_create_config.config_id=config_id; + cmd->data.cmd_cs_create_config.create_context=create_context; + cmd->data.cmd_cs_create_config.main_mode_type=main_mode_type; + cmd->data.cmd_cs_create_config.sub_mode_type=sub_mode_type; + cmd->data.cmd_cs_create_config.min_main_mode_steps=min_main_mode_steps; + cmd->data.cmd_cs_create_config.max_main_mode_steps=max_main_mode_steps; + cmd->data.cmd_cs_create_config.main_mode_repetition=main_mode_repetition; + cmd->data.cmd_cs_create_config.mode_calibration_steps=mode_calibration_steps; + cmd->data.cmd_cs_create_config.role=role; + cmd->data.cmd_cs_create_config.rtt_type=rtt_type; + cmd->data.cmd_cs_create_config.cs_sync_phy=cs_sync_phy; + memcpy(&cmd->data.cmd_cs_create_config.channel_map,channel_map,sizeof(sl_bt_cs_channel_map_t)); + cmd->data.cmd_cs_create_config.channel_map_repetition=channel_map_repetition; + cmd->data.cmd_cs_create_config.channel_selection_type=channel_selection_type; + cmd->data.cmd_cs_create_config.ch3c_shape=ch3c_shape; + cmd->data.cmd_cs_create_config.ch3c_jump=ch3c_jump; + cmd->data.cmd_cs_create_config.companion_signal_state=companion_signal_state; + + cmd->header=sl_bt_cmd_cs_create_config_id+(((27)&0xff)<<8)+(((27)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_create_config.result; + +} + +sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_remove_config.connection=connection; + cmd->data.cmd_cs_remove_config.config_id=config_id; + + cmd->header=sl_bt_cmd_cs_remove_config_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_remove_config.result; + +} + +sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + memcpy(&cmd->data.cmd_cs_set_channel_classification.channel_map,channel_map,sizeof(sl_bt_cs_channel_map_t)); + + cmd->header=sl_bt_cmd_cs_set_channel_classification_id+(((10)&0xff)<<8)+(((10)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_set_channel_classification.result; + +} + +sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, + uint8_t config_id, + uint16_t max_procedure_len, + uint16_t min_procedure_interval, + uint16_t max_procedure_interval, + uint16_t max_procedure_count, + uint32_t min_subevent_len, + uint32_t max_subevent_len, + uint8_t tone_antenna_config_selection, + uint8_t phy, + int8_t tx_pwr_delta, + uint8_t preferred_peer_antenna) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_set_procedure_parameters.connection=connection; + cmd->data.cmd_cs_set_procedure_parameters.config_id=config_id; + cmd->data.cmd_cs_set_procedure_parameters.max_procedure_len=max_procedure_len; + cmd->data.cmd_cs_set_procedure_parameters.min_procedure_interval=min_procedure_interval; + cmd->data.cmd_cs_set_procedure_parameters.max_procedure_interval=max_procedure_interval; + cmd->data.cmd_cs_set_procedure_parameters.max_procedure_count=max_procedure_count; + cmd->data.cmd_cs_set_procedure_parameters.min_subevent_len=min_subevent_len; + cmd->data.cmd_cs_set_procedure_parameters.max_subevent_len=max_subevent_len; + cmd->data.cmd_cs_set_procedure_parameters.tone_antenna_config_selection=tone_antenna_config_selection; + cmd->data.cmd_cs_set_procedure_parameters.phy=phy; + cmd->data.cmd_cs_set_procedure_parameters.tx_pwr_delta=tx_pwr_delta; + cmd->data.cmd_cs_set_procedure_parameters.preferred_peer_antenna=preferred_peer_antenna; + + cmd->header=sl_bt_cmd_cs_set_procedure_parameters_id+(((22)&0xff)<<8)+(((22)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_set_procedure_parameters.result; + +} + +sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, + uint8_t enable, + uint8_t config_id) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_procedure_enable.connection=connection; + cmd->data.cmd_cs_procedure_enable.enable=enable; + cmd->data.cmd_cs_procedure_enable.config_id=config_id; + + cmd->header=sl_bt_cmd_cs_procedure_enable_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_procedure_enable.result; + +} + +sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, + const uint8_t* antenna_element_offset) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+antenna_element_offset_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cs_set_antenna_configuration.antenna_element_offset.len=antenna_element_offset_len; + memcpy(cmd->data.cmd_cs_set_antenna_configuration.antenna_element_offset.data,antenna_element_offset,antenna_element_offset_len); + + cmd->header=sl_bt_cmd_cs_set_antenna_configuration_id+(((1+antenna_element_offset_len)&0xff)<<8)+(((1+antenna_element_offset_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_set_antenna_configuration.result; + +} + +sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, + uint16_t *max_consecutive_procedures, + uint8_t *num_antennas, + uint8_t *max_antenna_paths, + uint8_t *roles, + uint8_t *optional_modes, + uint8_t *rtt_capability, + uint8_t *rtt_aa_only, + uint8_t *rtt_sounding, + uint8_t *rtt_random_payload, + uint8_t *optional_cs_sync_phys, + uint16_t *optional_subfeatures, + uint16_t *optional_t_ip1_times, + uint16_t *optional_t_ip2_times, + uint16_t *optional_t_fcs_times, + uint16_t *optional_t_pm_times, + uint8_t *t_sw_times) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_cs_read_local_supported_capabilities_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (num_config) { + *num_config = rsp->data.rsp_cs_read_local_supported_capabilities.num_config; + } + if (max_consecutive_procedures) { + *max_consecutive_procedures = rsp->data.rsp_cs_read_local_supported_capabilities.max_consecutive_procedures; + } + if (num_antennas) { + *num_antennas = rsp->data.rsp_cs_read_local_supported_capabilities.num_antennas; + } + if (max_antenna_paths) { + *max_antenna_paths = rsp->data.rsp_cs_read_local_supported_capabilities.max_antenna_paths; + } + if (roles) { + *roles = rsp->data.rsp_cs_read_local_supported_capabilities.roles; + } + if (optional_modes) { + *optional_modes = rsp->data.rsp_cs_read_local_supported_capabilities.optional_modes; + } + if (rtt_capability) { + *rtt_capability = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_capability; + } + if (rtt_aa_only) { + *rtt_aa_only = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_aa_only; + } + if (rtt_sounding) { + *rtt_sounding = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_sounding; + } + if (rtt_random_payload) { + *rtt_random_payload = rsp->data.rsp_cs_read_local_supported_capabilities.rtt_random_payload; + } + if (optional_cs_sync_phys) { + *optional_cs_sync_phys = rsp->data.rsp_cs_read_local_supported_capabilities.optional_cs_sync_phys; + } + if (optional_subfeatures) { + *optional_subfeatures = rsp->data.rsp_cs_read_local_supported_capabilities.optional_subfeatures; + } + if (optional_t_ip1_times) { + *optional_t_ip1_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_ip1_times; + } + if (optional_t_ip2_times) { + *optional_t_ip2_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_ip2_times; + } + if (optional_t_fcs_times) { + *optional_t_fcs_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_fcs_times; + } + if (optional_t_pm_times) { + *optional_t_pm_times = rsp->data.rsp_cs_read_local_supported_capabilities.optional_t_pm_times; + } + if (t_sw_times) { + *t_sw_times = rsp->data.rsp_cs_read_local_supported_capabilities.t_sw_times; + } + return rsp->data.rsp_cs_read_local_supported_capabilities.result; + +} + +sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + uint8_t antenna_selection, + const sl_bt_cs_subevent_length_t *subevent_len, + uint16_t subevent_interval, + int8_t tx_power, + uint8_t t_ip1_time, + uint8_t t_ip2_time, + uint8_t t_fcs_time, + uint8_t t_pm_time, + uint8_t t_sw_time, + uint8_t tone_antenna_config, + uint8_t companion_signal_state, + uint16_t drbg_nonce, + uint16_t override_config, + size_t override_parameters_len, + const uint8_t* override_parameters) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cs_test_start.main_mode_type=main_mode_type; + cmd->data.cmd_cs_test_start.sub_mode_type=sub_mode_type; + cmd->data.cmd_cs_test_start.main_mode_repetition=main_mode_repetition; + cmd->data.cmd_cs_test_start.mode_calibration_steps=mode_calibration_steps; + cmd->data.cmd_cs_test_start.role=role; + cmd->data.cmd_cs_test_start.rtt_type=rtt_type; + cmd->data.cmd_cs_test_start.cs_sync_phy=cs_sync_phy; + cmd->data.cmd_cs_test_start.antenna_selection=antenna_selection; + memcpy(&cmd->data.cmd_cs_test_start.subevent_len,subevent_len,sizeof(sl_bt_cs_subevent_length_t)); + cmd->data.cmd_cs_test_start.subevent_interval=subevent_interval; + cmd->data.cmd_cs_test_start.tx_power=tx_power; + cmd->data.cmd_cs_test_start.t_ip1_time=t_ip1_time; + cmd->data.cmd_cs_test_start.t_ip2_time=t_ip2_time; + cmd->data.cmd_cs_test_start.t_fcs_time=t_fcs_time; + cmd->data.cmd_cs_test_start.t_pm_time=t_pm_time; + cmd->data.cmd_cs_test_start.t_sw_time=t_sw_time; + cmd->data.cmd_cs_test_start.tone_antenna_config=tone_antenna_config; + cmd->data.cmd_cs_test_start.companion_signal_state=companion_signal_state; + cmd->data.cmd_cs_test_start.drbg_nonce=drbg_nonce; + cmd->data.cmd_cs_test_start.override_config=override_config; + if ((26+override_parameters_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cs_test_start.override_parameters.len=override_parameters_len; + memcpy(cmd->data.cmd_cs_test_start.override_parameters.data,override_parameters,override_parameters_len); + + cmd->header=sl_bt_cmd_cs_test_start_id+(((26+override_parameters_len)&0xff)<<8)+(((26+override_parameters_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cs_test_start.result; + +} + +sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, + uint16_t spsm, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t *cid) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_l2cap_open_le_channel.connection=connection; + cmd->data.cmd_l2cap_open_le_channel.spsm=spsm; + cmd->data.cmd_l2cap_open_le_channel.max_sdu=max_sdu; + cmd->data.cmd_l2cap_open_le_channel.max_pdu=max_pdu; + cmd->data.cmd_l2cap_open_le_channel.credit=credit; + + cmd->header=sl_bt_cmd_l2cap_open_le_channel_id+(((9)&0xff)<<8)+(((9)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (cid) { + *cid = rsp->data.rsp_l2cap_open_le_channel.cid; + } + return rsp->data.rsp_l2cap_open_le_channel.result; + +} + +sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, + uint16_t cid, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t errorcode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_l2cap_send_le_channel_open_response.connection=connection; + cmd->data.cmd_l2cap_send_le_channel_open_response.cid=cid; + cmd->data.cmd_l2cap_send_le_channel_open_response.max_sdu=max_sdu; + cmd->data.cmd_l2cap_send_le_channel_open_response.max_pdu=max_pdu; + cmd->data.cmd_l2cap_send_le_channel_open_response.credit=credit; + cmd->data.cmd_l2cap_send_le_channel_open_response.errorcode=errorcode; + + cmd->header=sl_bt_cmd_l2cap_send_le_channel_open_response_id+(((11)&0xff)<<8)+(((11)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_l2cap_send_le_channel_open_response.result; + +} + +sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, + uint16_t cid, + size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_l2cap_channel_send_data.connection=connection; + cmd->data.cmd_l2cap_channel_send_data.cid=cid; + if ((4+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_l2cap_channel_send_data.data.len=data_len; + memcpy(cmd->data.cmd_l2cap_channel_send_data.data.data,data,data_len); + + cmd->header=sl_bt_cmd_l2cap_channel_send_data_id+(((4+data_len)&0xff)<<8)+(((4+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_l2cap_channel_send_data.result; + +} + +sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, + uint16_t cid, + uint16_t credit) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_l2cap_channel_send_credit.connection=connection; + cmd->data.cmd_l2cap_channel_send_credit.cid=cid; + cmd->data.cmd_l2cap_channel_send_credit.credit=credit; + + cmd->header=sl_bt_cmd_l2cap_channel_send_credit_id+(((5)&0xff)<<8)+(((5)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_l2cap_channel_send_credit.result; + +} + +sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_l2cap_close_channel.connection=connection; + cmd->data.cmd_l2cap_close_channel.cid=cid; + + cmd->header=sl_bt_cmd_l2cap_close_channel_id+(((3)&0xff)<<8)+(((3)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_l2cap_close_channel.result; + +} + +sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_length=cte_length; + cmd->data.cmd_cte_transmitter_set_dtm_parameters.cte_type=cte_type; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_transmitter_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_transmitter_set_dtm_parameters_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_set_dtm_parameters.result; + +} + +sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_clear_dtm_parameters.result; + +} + +sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, + uint8_t cte_types, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_enable_connection_cte.connection=connection; + cmd->data.cmd_cte_transmitter_enable_connection_cte.cte_types=cte_types; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_transmitter_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_transmitter_enable_connection_cte_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_enable_connection_cte.result; + +} + +sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_disable_connection_cte.connection=connection; + + cmd->header=sl_bt_cmd_cte_transmitter_disable_connection_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_disable_connection_cte.result; + +} + +sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_enable_connectionless_cte.handle=handle; + cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_length=cte_length; + cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_type=cte_type; + cmd->data.cmd_cte_transmitter_enable_connectionless_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_transmitter_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_enable_connectionless_cte.result; + +} + +sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_disable_connectionless_cte.handle=handle; + + cmd->header=sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_disable_connectionless_cte.result; + +} + +sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_enable_silabs_cte.handle=handle; + cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_length=cte_length; + cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_type=cte_type; + cmd->data.cmd_cte_transmitter_enable_silabs_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_transmitter_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_transmitter_enable_silabs_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_enable_silabs_cte.result; + +} + +sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_transmitter_disable_silabs_cte.handle=handle; + + cmd->header=sl_bt_cmd_cte_transmitter_disable_silabs_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_transmitter_disable_silabs_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_length=cte_length; + cmd->data.cmd_cte_receiver_set_dtm_parameters.cte_type=cte_type; + cmd->data.cmd_cte_receiver_set_dtm_parameters.slot_durations=slot_durations; + if ((4+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_receiver_set_dtm_parameters.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_receiver_set_dtm_parameters_id+(((4+switching_pattern_len)&0xff)<<8)+(((4+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_set_dtm_parameters.result; + +} + +sl_status_t sl_bt_cte_receiver_clear_dtm_parameters() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_cte_receiver_clear_dtm_parameters_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_clear_dtm_parameters.result; + +} + +sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_set_sync_cte_type.sync_cte_type=sync_cte_type; + + cmd->header=sl_bt_cmd_cte_receiver_set_sync_cte_type_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_set_sync_cte_type.result; + +} + +sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.mode=mode; + cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.skip=skip; + cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.timeout=timeout; + cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.sync_cte_type=sync_cte_type; + cmd->data.cmd_cte_receiver_set_default_sync_receive_parameters.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id+(((7)&0xff)<<8)+(((7)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_set_default_sync_receive_parameters.result; + +} + +sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.connection=connection; + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.mode=mode; + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.skip=skip; + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.timeout=timeout; + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.sync_cte_type=sync_cte_type; + cmd->data.cmd_cte_receiver_set_sync_receive_parameters.reporting_mode=reporting_mode; + + cmd->header=sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id+(((8)&0xff)<<8)+(((8)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_set_sync_receive_parameters.result; + +} + +sl_status_t sl_bt_cte_receiver_configure(uint8_t flags) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_configure.flags=flags; + + cmd->header=sl_bt_cmd_cte_receiver_configure_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_configure.result; + +} + +sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, + uint16_t interval, + uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_enable_connection_cte.connection=connection; + cmd->data.cmd_cte_receiver_enable_connection_cte.interval=interval; + cmd->data.cmd_cte_receiver_enable_connection_cte.cte_length=cte_length; + cmd->data.cmd_cte_receiver_enable_connection_cte.cte_type=cte_type; + cmd->data.cmd_cte_receiver_enable_connection_cte.slot_durations=slot_durations; + if ((7+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_receiver_enable_connection_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_receiver_enable_connection_cte_id+(((7+switching_pattern_len)&0xff)<<8)+(((7+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_enable_connection_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_disable_connection_cte.connection=connection; + + cmd->header=sl_bt_cmd_cte_receiver_disable_connection_cte_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_disable_connection_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, + uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_enable_connectionless_cte.sync=sync; + cmd->data.cmd_cte_receiver_enable_connectionless_cte.slot_durations=slot_durations; + cmd->data.cmd_cte_receiver_enable_connectionless_cte.cte_count=cte_count; + if ((5+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_receiver_enable_connectionless_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_receiver_enable_connectionless_cte_id+(((5+switching_pattern_len)&0xff)<<8)+(((5+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_enable_connectionless_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_disable_connectionless_cte.sync=sync; + + cmd->header=sl_bt_cmd_cte_receiver_disable_connectionless_cte_id+(((2)&0xff)<<8)+(((2)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_disable_connectionless_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_cte_receiver_enable_silabs_cte.slot_durations=slot_durations; + cmd->data.cmd_cte_receiver_enable_silabs_cte.cte_count=cte_count; + if ((3+switching_pattern_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.len=switching_pattern_len; + memcpy(cmd->data.cmd_cte_receiver_enable_silabs_cte.switching_pattern.data,switching_pattern,switching_pattern_len); + + cmd->header=sl_bt_cmd_cte_receiver_enable_silabs_cte_id+(((3+switching_pattern_len)&0xff)<<8)+(((3+switching_pattern_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_enable_silabs_cte.result; + +} + +sl_status_t sl_bt_cte_receiver_disable_silabs_cte() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + + cmd->header=sl_bt_cmd_cte_receiver_disable_silabs_cte_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_cte_receiver_disable_silabs_cte.result; + +} + +sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, + uint32_t crc_init, + uint16_t interval, + uint16_t supervision_timeout, + uint8_t central_clock_accuracy, + uint8_t central_phy, + uint8_t peripheral_phy, + uint8_t channel_selection_algorithm, + uint8_t hop, + const sl_bt_connection_channel_map_t *channel_map, + uint8_t channel, + uint16_t event_counter, + int32_t start_time_us, + uint32_t flags, + uint8_t *analyzer) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_analyzer_start.access_address=access_address; + cmd->data.cmd_connection_analyzer_start.crc_init=crc_init; + cmd->data.cmd_connection_analyzer_start.interval=interval; + cmd->data.cmd_connection_analyzer_start.supervision_timeout=supervision_timeout; + cmd->data.cmd_connection_analyzer_start.central_clock_accuracy=central_clock_accuracy; + cmd->data.cmd_connection_analyzer_start.central_phy=central_phy; + cmd->data.cmd_connection_analyzer_start.peripheral_phy=peripheral_phy; + cmd->data.cmd_connection_analyzer_start.channel_selection_algorithm=channel_selection_algorithm; + cmd->data.cmd_connection_analyzer_start.hop=hop; + memcpy(&cmd->data.cmd_connection_analyzer_start.channel_map,channel_map,sizeof(sl_bt_connection_channel_map_t)); + cmd->data.cmd_connection_analyzer_start.channel=channel; + cmd->data.cmd_connection_analyzer_start.event_counter=event_counter; + cmd->data.cmd_connection_analyzer_start.start_time_us=start_time_us; + cmd->data.cmd_connection_analyzer_start.flags=flags; + + cmd->header=sl_bt_cmd_connection_analyzer_start_id+(((33)&0xff)<<8)+(((33)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (analyzer) { + *analyzer = rsp->data.rsp_connection_analyzer_start.analyzer; + } + return rsp->data.rsp_connection_analyzer_start.result; + +} + +sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + cmd->data.cmd_connection_analyzer_stop.analyzer=analyzer; + + cmd->header=sl_bt_cmd_connection_analyzer_stop_id+(((1)&0xff)<<8)+(((1)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_connection_analyzer_stop.result; + +} + +sl_status_t sl_bt_user_message_to_target(size_t data_len, + const uint8_t* data, + size_t max_response_size, + size_t *response_len, + uint8_t *response) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_user_message_to_target.data.len=data_len; + memcpy(cmd->data.cmd_user_message_to_target.data.data,data,data_len); + + cmd->header=sl_bt_cmd_user_message_to_target_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + if (response_len) { + *response_len = rsp->data.rsp_user_message_to_target.response.len; + } + if (response && (rsp->data.rsp_user_message_to_target.response.len <= max_response_size)) { + memcpy(response,rsp->data.rsp_user_message_to_target.response.data,rsp->data.rsp_user_message_to_target.response.len); + } + return rsp->data.rsp_user_message_to_target.result; + +} + +sl_status_t sl_bt_user_manage_event_filter(size_t data_len, + const uint8_t* data) { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + struct sl_bt_packet *rsp = (struct sl_bt_packet *)sl_bt_rsp_msg; + + if ((1+data_len) > SL_BGAPI_MAX_PAYLOAD_SIZE ) + { + return SL_STATUS_COMMAND_TOO_LONG; + } + cmd->data.cmd_user_manage_event_filter.data.len=data_len; + memcpy(cmd->data.cmd_user_manage_event_filter.data.data,data,data_len); + + cmd->header=sl_bt_cmd_user_manage_event_filter_id+(((1+data_len)&0xff)<<8)+(((1+data_len)&0x700)>>8); + + + sl_bt_host_handle_command(); + return rsp->data.rsp_user_manage_event_filter.result; + +} + +void sl_bt_user_reset_to_dfu() { + struct sl_bt_packet *cmd = (struct sl_bt_packet *)sl_bt_cmd_msg; + + + cmd->header=sl_bt_cmd_user_reset_to_dfu_id+(((0)&0xff)<<8)+(((0)&0x700)>>8); + + + sl_bt_host_handle_command_noresponse(); +} diff --git a/locator_host/gecko_sdk_4.4.1/util/silicon_labs/aox/inc/sl_rtl_clib_api.h b/locator_host/gecko_sdk_4.4.1/util/silicon_labs/aox/inc/sl_rtl_clib_api.h index 67e1ffe..14e351f 100644 --- a/locator_host/gecko_sdk_4.4.1/util/silicon_labs/aox/inc/sl_rtl_clib_api.h +++ b/locator_host/gecko_sdk_4.4.1/util/silicon_labs/aox/inc/sl_rtl_clib_api.h @@ -1,1694 +1,1694 @@ -/***************************************************************************//** - * @brief Silicon Labs Real-Time Locationing library for AoA/D and locationing - ******************************************************************************* - * # License - * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -/**************************************************************************//** -* -* Information on open-source software used with the library can be found in -* the included license.txt file. -* -******************************************************************************/ - -/**************************************************************************//** - * @file - * This is the API for the Silicon Labs Real-Time Locationing library. - * It provides an interface for estimating arrival and departure angles of - * signals and the positions of AoA/AoD signal transmitters. AoA stands for - * Angle-of-Arrival and AoD for Angle-of-Departure. AoX is used when - * referring to both techniques. - * - * Estimators can be created individually for each locator node using the API. - * Even multiple estimators with different parameters can be created for a - * single node. An instance of the estimator is created as a libitem and the - * estimator is initialized. Next, the estimation parameters such as antenna - * array type, number of antennas, estimation mode, and so on can be set - * using the function calls described below. - * - * One snapshot means a set of IQ-samples with exactly one sample per - * each antenna. - * - *****************************************************************************/ - -#ifndef SL_RTL_CLIB_API_H -#define SL_RTL_CLIB_API_H - -#include -#include - -/** - * @addtogroup sl_rtl_error Error Codes - * @{ - * - * @brief RTL library Error Codes - * - */ - -/// RTL error code -enum sl_rtl_error_code{ - SL_RTL_ERROR_SUCCESS = 0, ///< Successful execution / estimation complete - SL_RTL_ERROR_ARGUMENT, ///< Invalid argument - SL_RTL_ERROR_OUT_OF_MEMORY, ///< Memory / allocation failure - SL_RTL_ERROR_ESTIMATION_IN_PROGRESS, ///< Estimation not yet finished - SL_RTL_ERROR_NUMBER_OF_SNAPHOTS_DO_NOT_MATCH, ///< Initialized and calculated number of snapshots do not match - SL_RTL_ERROR_ESTIMATOR_NOT_CREATED, ///< Estimator not yet created - SL_RTL_ERROR_ESTIMATOR_ALREADY_CREATED, ///< Estimator already created, operation is not supported - SL_RTL_ERROR_NOT_INITIALIZED, ///< Library item not yet initialized - SL_RTL_ERROR_INTERNAL, ///< An internal error occurred - SL_RTL_ERROR_IQ_SAMPLE_QA, ///< IQ sample quality analysis failed - SL_RTL_ERROR_FEATURE_NOT_SUPPORTED, ///< The requested feature is not supported by the library - SL_RTL_ERROR_INCORRECT_MEASUREMENT, ///< The error of the last measurement for this locator was too large - - SL_RTL_ERROR_LAST ///< Number of error codes -}; -/** @} */ // end addtogroup sl_rtl_error - - -/** - * @addtogroup sl_rtl_aox Angle of Arrival / Departure - * @{ - * - * @brief Angle of Arrival / Departure - * - * These functions are related to the calculation of the Angle of Arrival - * and Angle of Departure from I/Q samples. The angles can be calculated - * following these steps: - * 1. Initialize a sl_rtl_aox_libitem instance. - * 2. Set up the antenna array and angle calculation parameters. - * 3. Create the estimator. - * 4. Set the antenna switching pattern. - * 5. Input the I/Q data into the libitem. - * 6. Process the I/Q data into an angle. - */ - -/// AoX antenna array type -enum sl_rtl_aox_array_type{ - SL_RTL_AOX_ARRAY_TYPE_4x4_URA = 0, ///< Silicon Labs Ref. 4x4 Uniform Rectangular Array - SL_RTL_AOX_ARRAY_TYPE_3x3_URA, ///< Silicon Labs Ref. 3x3 Uniform Rectangular Array - SL_RTL_AOX_ARRAY_TYPE_1x4_ULA, ///< Silicon Labs Ref. 1x4 Uniform Linear Array - SL_RTL_AOX_ARRAY_TYPE_4x4_DP_URA, ///< Silicon Labs Ref. 4x4 Uniform Dual Polarized Rectangular Array - SL_RTL_AOX_ARRAY_TYPE_COREHW_15x15_DP, ///< CoreHw Ref. 150 mm x 150 mm, 8 Element Dual Polarized Array - SL_RTL_AOX_ARRAY_TYPE_COREHW_12x12_DP, ///< CoreHw Ref. 120 mm x 120 mm, 8 Element Dual Polarized Array - SL_RTL_AOX_ARRAY_TYPE_COREHW_4x4_URA, ///< CoreHw Ref. 4x4 Uniform Rectangular Array - SL_RTL_AOX_ARRAY_TYPE_COREHW_2x2_URA, ///< CoreHw Ref. 2x2 Uniform Rectangular Array - - SL_RTL_AOX_ARRAY_TYPE_LAST ///< Placeholder -}; - -enum sl_rtl_aox_switch_pattern_array{ - SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_CP = 0, - SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_DP, - - SL_RTL_AOX_SWITCH_PATTERN_ARRAY_LAST -}; - -enum sl_rtl_aox_switch_pattern_options{ - SL_RTL_AOX_SWITCH_PATTERN_OPTIONS_DUAL_POLARIZED = 0x1, - SL_RTL_AOX_SWITCH_PATTERN_OPTIONS_EXTRA_REFERENCE = 0x2 -}; - -/// AoA, AoD (and AoX for backward compatibility) estimator modes -enum sl_rtl_aox_mode { - SL_RTL_AOA_MODE_ONE_SHOT_BASIC = 3, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOA_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOA_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. - SL_RTL_AOA_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. - - SL_RTL_AOA_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. - SL_RTL_AOA_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. - SL_RTL_AOA_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. - - SL_RTL_AOA_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOA_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOA_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. - - SL_RTL_AOA_MODE_LAST, ///< Placeholder - - /***************************************************************************/ - - SL_RTL_AOD_MODE_ONE_SHOT_BASIC = 3 | 0x20, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOD_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOD_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. - SL_RTL_AOD_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. - - SL_RTL_AOD_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. - SL_RTL_AOD_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. - SL_RTL_AOD_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. - - SL_RTL_AOD_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOD_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOD_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. - - SL_RTL_AOD_MODE_LAST, ///< Placeholder - - /***************************************************************************/ - - SL_RTL_AOX_MODE_ONE_SHOT_BASIC = 3 | 0x40, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOX_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. - SL_RTL_AOX_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. - SL_RTL_AOX_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. - - SL_RTL_AOX_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. - SL_RTL_AOX_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. - SL_RTL_AOX_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. - - SL_RTL_AOX_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOX_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. - SL_RTL_AOX_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. - - SL_RTL_AOX_MODE_LAST ///< Placeholder -}; - -// AoX constraint types -enum sl_rtl_aox_constraint_type{ - SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH = 0, ///< Azimuth constraint in degrees - SL_RTL_AOX_CONSTRAINT_TYPE_ELEVATION, ///< Elevation constraint in degrees -}; - -// AoX switch pattern modes -enum sl_rtl_aox_switch_pattern_mode{ - SL_RTL_AOX_SWITCH_PATTERN_MODE_DEFAULT = 0, ///< Internally defined switch pattern: 0, 1, 2, ..., N-1, where N is the number of antennas - SL_RTL_AOX_SWITCH_PATTERN_MODE_RANDOM, ///< Internally defined random switch pattern - SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL, ///< Switch pattern set externally by the user - SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTRA_REFERENCE, ///< Switch pattern set externally by the user with extra reference antenna as a first -}; - -/// Angle of Arrival / Departure library item -typedef void* sl_rtl_aox_libitem; - -// Structure for IQ sample quality calculation antenna-specific results -typedef struct { - float level; ///< Antenna signal level, in decibels - float snr; ///< Antenna level signal to noise ratio, in decibels - float phase_value; ///< Antenna's average unrotated phase value in the packet, in radians - float phase_jitter; ///< Phase variation of snapshots' data of an antenna in packet, in radians -} sl_rtl_clib_iq_sample_qa_antenna_data_t; - -// Structure for IQ sample quality calculation results -typedef struct { - bool data_available; ///< If false, all the antenna values are undefined - uint32_t curr_channel; ///< Radio channel for the last packet - float ref_freq; ///< Apparent supplemental tone frequency - float ref_sndr; ///< Reference period signal to noise and distortion ratio - - // available only when raw samples are used - float switching_jitter; ///< Estimated antenna switching clock jitter -} sl_rtl_clib_iq_sample_qa_dataset_t; - -// return codes from the individual IQ sample QA tests -#define SL_RTL_AOX_IQ_SAMPLE_QA_ALL_OK 0 -#define SL_RTL_AOX_IQ_SAMPLE_QA_FAILURE 0xffffffff -typedef enum { - SL_RTL_AOX_IQ_SAMPLE_QA_INVAL_REF = 0, ///< Invalid reference period data - SL_RTL_AOX_IQ_SAMPLE_QA_DCOFFSET = 2, ///< DC offset too large - SL_RTL_AOX_IQ_SAMPLE_QA_SNDR = 3, ///< Reference period SNDR too large - SL_RTL_AOX_IQ_SAMPLE_QA_ROTATING_ERROR = 4, ///< Rotation error too large - SL_RTL_AOX_IQ_SAMPLE_QA_REF_ANT_PHASE_VALUE = 5, ///< Reference antenna phase value too big - SL_RTL_AOX_IQ_SAMPLE_QA_REF_ANT_PHASE_JITTER = 6, ///< Reference antenna phase jitter too large - SL_RTL_AOX_IQ_SAMPLE_QA_ANT_X_PHASE_JITTER = 7, ///< Antenna X phase jitter too large - SL_RTL_AOX_IQ_SAMPLE_QA_ALL_SAME_PHASE = 8, ///< All the antennas seen in the same phase - SL_RTL_AOX_IQ_SAMPLE_QA_SWICHING_JITTER = 9, ///< Switching jitter too large -} sl_rtl_slib_iq_sample_qa_result_t; - -#define SL_RTL_AOX_IQ_SAMPLE_QA_CLEAR_BIT(code, bit) \ - (code &= ~(1UL << bit)) -#define SL_RTL_AOX_IQ_SAMPLE_QA_SET_BIT(code, bit) \ - (code |= (1UL << bit)) -#define SL_RTL_AOX_IQ_SAMPLE_QA_IS_SET(code, bit) \ - (code & (1UL << bit)) - -/**************************************************************************//** - * Initialize the AoX libitem instance. - * - * @param[in] item Pointer to the libitem to be initialized. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_init(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Deinitialize a libitem instance of the AoX estimator. - * - * @param[in] item Pointer to the libitem to be deinitialized. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_deinit(sl_rtl_aox_libitem* item); - -/* NARROWBAND AOA ESTIMATION */ - -/**************************************************************************//** - * Set the number of signal snapshots to be used in the angle estimation. - * - * @param[in] item Pointer to the initialized AoX libitem. - * @param[in] num_snapshots Number of snapshots as positive integer value. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_num_snapshots(sl_rtl_aox_libitem* item, uint32_t num_snapshots); - -/**************************************************************************//** - * Set the array type used with the estimator. - * - * @param[in] item Pointer to the initialized AoX libitem. - * @param[in] array_type Array type as ::sl_rtl_aox_array_type. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Set the array type used with the estimator. - * For example, the array type should be set to ::SL_RTL_AOX_ARRAY_TYPE_4x4_URA - * when using the reference 4x4 URA board. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_array_type(sl_rtl_aox_libitem* item, enum sl_rtl_aox_array_type array_type); - -/**************************************************************************//** - * Set the estimation mode. - * - * @param[in] item Pointer to the initialized AoX libitem. - * @param[in] mode Estimator mode as ::sl_rtl_aox_mode. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Set the estimation mode. For example, ::SL_RTL_AOX_MODE_BASIC sets medium filtering - * and estimates both azimuth and elevation. For further description of the modes, - * see the documentation of ::sl_rtl_aox_mode. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_mode(sl_rtl_aox_libitem* item, enum sl_rtl_aox_mode mode); - -/**************************************************************************//** - * Estimate the I/Q-sample phase rotation error in degrees. - * - * @param[in] item Pointer to the initialized AoX libitem. - * @param[in] iq_data_downsampling_factor Ratio between reference period IQ-data sampling rate. - * and actual IQ-data (i.e., antenna array data) sampling rate. - * For example, 1e6 / 500e3 = 2.0 - * @param[in] i_samples Float-array of the reference period I samples. - * @param[in] q_samples Float-array of the reference period Q samples. - * @param[in] num_samples Number of samples, or size of the I or Q sample array. - * @param[out] phase_rotation_out Returned phase rotation value as float in degrees. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Estimate the I/Q-sample phase rotation error caused by switching - * and CTE frequency error based on I/Q samples from the reference period. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_calculate_iq_sample_phase_rotation(sl_rtl_aox_libitem* item, float iq_data_downsampling_factor, float* i_samples, float* q_samples, uint32_t num_samples, float* phase_rotation_out); - -/**************************************************************************//** - * Set a constant value of I/Q sample phase rotation in degrees. - * - * @param[in] item Pointer to the initialized AoX libitem. - * @param[in] phase_rotation Float value of I/Q sample phase rotation in degrees. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Set a constant value of I/Q sample phase rotation in degrees. - * The sample rotation can be used to correct the switching and CTE frequency error. - * @note: This function should be called only after the estimator is - * created. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_iq_sample_phase_rotation(sl_rtl_aox_libitem* item, float phase_rotation); - -/**************************************************************************//** - * Add constraints for the estimator. Call before sl_rtl_aox_create_estimator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] constraint_type Select which constraints should be added. - * @param[in] min_value Starting (minimum) value of the range including the min_value. - * @param[in] max_value Ending (maximum) value of the range including the max_value. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * For example, constraint for SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH with min_value = 0 - * and max_value = 90 means that the angular range 0 to 90 degrees is excluded - * from the estimators internal processing range and angle estimated between that range - * are not considered as valid results. Setting constraints will help ruling - * out false multipath-detections when the locator is installed nearby a wall or - * a RF-reflective surface. - * @note: This function must called before the estimator is created. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_add_constraint(sl_rtl_aox_libitem* item, enum sl_rtl_aox_constraint_type constraint_type, float min_value, float max_value); - -/**************************************************************************//** - * Configure the IQ sampling sample rate for the library. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] sampleRate The new sample rate. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_sample_rate(sl_rtl_aox_libitem* item, float sampleRate); - -/**************************************************************************//** - * Configure the number of radio channels. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] channels The new number of radio channels. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_num_radio_channels(sl_rtl_aox_libitem* item, uint32_t channels); - -/**************************************************************************//** - * Configure the IQ sample quality analysis. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * This function turns the IQ sample quality analysis, - * which is not done by default. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_configure(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Get the IQ sample quality analysis overall results. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @return bitmask of found problems, zero indicates that everything is OK - *****************************************************************************/ -uint32_t sl_rtl_aox_iq_sample_qa_get_results(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Get the IQ sample quality analysis detailed results for the latest packet. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[out] results The data structure with data related to the latest data packet. - * @param[out] antenna_data The array of antenna-specific results. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Fetch the results for the latest packet. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_get_details(sl_rtl_aox_libitem* item, sl_rtl_clib_iq_sample_qa_dataset_t *results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); - -/**************************************************************************//** - * Get the IQ sample quality analysis detailed results for the requested radio channel. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] channel Radio channel to show results for. - * @param[out] results The data structure with data related to the last data packet using the requested channel. - * @param[out] antenna_data The array of antenna-specific results - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Fetch the latest results for the given radio channel, which may be other than the latest - * packet received. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_get_channel_details(sl_rtl_aox_libitem* item, uint8_t channel, sl_rtl_clib_iq_sample_qa_dataset_t *results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); - -/**************************************************************************//** - * Create the estimator after initializing the libitem and setting parameters. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_create_estimator(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Convert data in RAW IQ-data buffers to downsampled IQ-data buffers. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] start_offset The start offset in the buffer (for example, for skipping a reference period). - * @param[in] iq_data_downsampling_factor Ratio between chip IQ-data sampling rate and downsampled rate. - * For example, 4.8e6 / 500e3 = 9.6 - * @param[in] raw_i_samples_in I-part sample buffer input - * @param[in] raw_q_samples_in Q-part sample buffer input - * @param[in] num_raw_samples_in Number of IQ-sample pairs in the input buffers. - * @param[out] i_samples_out Buffer for the processed I-samples. Must be allocated by the user. - * Indexing: i_samples_out[snapshot][antenna] - * @param[out] q_samples_out Buffer for the processed Q-samples. Must be allocated by the user. - * Indexing: q_samples_out[snapshot][antenna] - * @param[in] num_snapshots_out Number of snapshots allocated in the output buffers. This function - * checks if the given number of snapshots and calculated snapshots based on the length of RAW-data match - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_convert_raw_samples(sl_rtl_aox_libitem* item, uint32_t start_offset, float iq_data_downsampling_factor, float* raw_i_samples_in, float* raw_q_samples_in, uint32_t num_raw_samples_in, float** i_samples_out, float** q_samples_out, uint32_t num_snapshots_out); - -/**************************************************************************//** - * Calculate the number of downsampled snapshots in a RAW IQ-data buffer. Use this function to get the number - * of snapshots to allocate the i_samples and q_samples buffers for the process-function. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] num_raw_samples_in Total number of RAW IQ-sample pairs. - * @param[in] start_offset The start offset in the buffer, for example, for skipping a reference period. - * @param[in] iq_data_downsampling_factor Ratio between chip IQ-data sampling rate and downsampled rate. - * For example, 4.8e6 / 500e3 = 9.6. - * @param[in] num_channels Number of channels in the RAW data - * @param[out] num_snapshots_out Calculated number of snapshots based on the input. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_calculate_number_of_snapshots(sl_rtl_aox_libitem* item, uint32_t num_raw_samples_in, uint32_t start_offset, float iq_data_downsampling_factor, uint32_t num_channels, uint32_t* num_snapshots_out); - -/**************************************************************************//** - * Set switch pattern mode. Sets internal mode used by the library. See enum sl_rtl_aox_switch_pattern_mode - * for detailed description of the modes. If this function isn't called, a default switch pattern - * of: 0, 1, 2, 3, ..., N-1 will be used, where N is the number of antennas. - * Call this function at run-time after initializing and creating the estimator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] mode Required mode. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_switch_pattern_mode(sl_rtl_aox_libitem* item, enum sl_rtl_aox_switch_pattern_mode mode); - -/**************************************************************************//** - * Update switch pattern, which is used by the estimator algorithm. - * This function must be called before calling the function sl_rtl_aox_process. - * Call this function at run-time after initializing and creating the estimator. - * - * When using a custom pattern in SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL mode, - * the pattern in switch_pattern_in must not contain duplicate elements and the - * antenna indices must be within the range 0 to (number_of_antennas - 1). - * Number_of_antennas is the amount of antennas in the set array type, for example - * for the 4x4 URA this is 16 and for the 1x4 ULA this is 4. - * The length of the switching pattern must be equal to number_of_antennas. - * - * Note: The RF switch pattern indices may be different to the indices required by - * the RTL algorithm. For example, a 1x4 ULA might use RF controls [12, 13, 14, 15] - * for switching the antennas 1-4, but the RTL algorithm requires the switch pattern - * [0, 1, 2, 3]. If the RF controls are switched as [14, 15, 13, 12], - * the RTL algorithm requires the pattern [2, 3, 1, 0]. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] switch_pattern_in Pointer to the switch pattern array. The pointer must point to a valid switch pattern when - * SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL is used. - * @param[out] switch_pattern_out Pointer to the user defined uint32_t* variable. This pointer must be non-zero when using - * internally defined switch pattern modes, otherwise can be zero. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_update_switch_pattern(sl_rtl_aox_libitem* item, uint32_t* switch_pattern_in, uint32_t** switch_pattern_out); - -/**************************************************************************//** - * Set the random seed for the switch pattern, which is used for the random pattern mode. - * Call this function at run-time after initializing and creating the estimator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] seed_value The seed value to be used. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_switch_pattern_seed(sl_rtl_aox_libitem* item, int32_t seed_value); - -/**************************************************************************//** - * Convert switching pattern from antenna indices to antenna switching pin control logic. - * Call this function at run-time after initializing and creating the estimator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] array_id Array ID, see ::sl_rtl_aox_switch_pattern_array, for example SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_DP - * @param[in] options Switch pattern options, see ::sl_rtl_aox_switch_pattern_options. - * Can be used to set for example dual polarization (default is single polarization). - * @param[in] switch_pattern_size_in The length of the input switching pattern. - * @param[in] switch_pattern_in The input switching pattern. - * @param[out] switch_pattern_size_out The outputted length of the converted switching pattern. - * @param[out] switch_pattern_out The outputted switching pattern. - * @return ::SL_RTL_ERROR_SUCCESS if successful - - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_convert_switch_pattern(sl_rtl_aox_libitem* item, uint32_t array_id, uint32_t options, uint32_t switch_pattern_size_in, uint32_t* switch_pattern_in, uint32_t* switch_pattern_size_out, uint32_t** switch_pattern_out); - -/**************************************************************************//** - * Reset estimator state. Calling this function causes the selected aox-mode to start from its initial state. - * Call this function at run-time after initializing and creating the estimator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_reset_estimator(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Calculate the angle estimate. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] i_samples Two-dimensional float-array of captured I samples - * as i_samples[snapshot][antenna]. - * @param[in] q_samples Two-dimensional float-array of captured Q samples - * as q_samples[snapshot][antenna], corresponding to the I samples array. - * @param[in] tone_frequency The frequency of the signal from which the - * I/Q data was captured from as float (e.g., 2.46e9f). - * @param[out] az_out Output azimuth angle. - * @param[out] el_out Output elevation angle. - * @return ::SL_RTL_ERROR_SUCCESS if successful and - * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final - * and more I/Q data needs to be processed. - * - * Calculate the angle estimate from the given I/Q samples captured at the - * given frequency. Call this function with new I/Q data as many times as - * indicated by the ::sl_rtl_aox_mode used by the estimator before the final - * estimate is output. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_process(sl_rtl_aox_libitem* item, float** i_samples, float** q_samples, float tone_frequency, float* az_out, float* el_out); - -/**************************************************************************//** - * Get the standard deviation for the latest AoA/AoD-estimate. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[out] az_std_dev Pointer for getting standard deviation of the - * latest azimuth estimate. - * @param[out] el_std_dev Pointer for getting standard deviation of the - * latest elevation estimate. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Call this function after sl_rtl_aox_process to fetch standard - * deviation for the latest AoA/AoD-estimate. Positive standard deviations - * indicate line-of-sight detection and negative values indicate likely - * non-line-of-sight detection. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_get_latest_aox_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev); - -/**************************************************************************//** - * Kept for backward compatibility - *****************************************************************************/ -static inline enum sl_rtl_error_code sl_rtl_aox_get_latest_aoa_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev) -{ - return sl_rtl_aox_get_latest_aox_standard_deviation(item, az_std_dev, el_std_dev); -} - -/**************************************************************************//** - * Kept for backward compatibility - *****************************************************************************/ -static inline enum sl_rtl_error_code sl_rtl_aox_get_latest_aod_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev) -{ - return sl_rtl_aox_get_latest_aox_standard_deviation(item, az_std_dev, el_std_dev); -} - -/**************************************************************************//** - * Feed the expected angles back to the locator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] expected_az Expected azimuth angle calculated by position algorithm. - * @param[in] expected_el Expected elevation angle calculated by position algorithm. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * The position algorithm has a more complete view of the asset's location. - * The direction it should be found can be calculated back and fed to the - * locator, so that it can recover faster when, - * for example, it has locked to a reflection rather than to the line of sight signal. - * See also sl_rtl_loc_get_expected_direction(). - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_expected_direction(sl_rtl_aox_libitem* item, float expected_az, float expected_el); - -/**************************************************************************//** - * Feed the expected angle deviations back to the locator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @param[in] deviation_az Deviation of the expected azimuth angle calculated by position algorithm. - * @param[in] deviation_el Deviation of the expected elevation angle calculated by position algorithm. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Report expected deviations calculated by the position algorithm back to - * the locator so that angles are calculated more accurately taking in account - * the correctness of the expected directions. If sl_rtl_aox_set_expected_direction() - * is called but this function is not called, the algorithm will use default values - * for the expected deviations. - * See also sl_rtl_loc_get_expected_deviation() and sl_rtl_aox_set_expected_direction(). - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_expected_deviation(sl_rtl_aox_libitem* item, float deviation_az, float deviation_el); - -/**************************************************************************//** - * Clear the expected directions and deviations from the locator. - * - * @param[in] item Pointer to the initialized and configured AoX libitem. - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * See also sl_rtl_aox_set_expected_direction() and sl_rtl_aox_set_expected_deviation(). - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_clear_expected_direction(sl_rtl_aox_libitem* item); - -/**************************************************************************//** - * Enable or disable outputting the pseudospectrum. This function should be called - * before creating the estimator. - * - * @param[in] item Pointer to the initialized libitem. - * @param[in] enable Set to true to enable outputting the pseudospectrum. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_enable_spectrum(sl_rtl_aox_libitem* item, bool enable); - -/**************************************************************************//** - * Get the size of the pseudospectrum. This function should be called after calling the AoX process - * function. - * - * @param[in] item Pointer to the initialized libitem. - * @param[out] rows Number of rows in the pseudospectrum data array. - * @param[out] cols Number of columns in the pseudospecutrm data array. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_get_spectrum_size(sl_rtl_aox_libitem* item, uint32_t* rows, uint32_t* cols); - -/**************************************************************************//** - * Get the size of the polarization pseudospectrum. - * This function should be called after calling the AoX process - * function. - * - * @param[in] item Pointer to the initialized libitem. - * @param[out] rows Number of rows in the polarization pseudospectrum data array. - * @param[out] cols Number of columns in the pseudospecutrm data array. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_get_polarization_spectrum_size(sl_rtl_aox_libitem* item, uint32_t* rows, uint32_t* cols); - -/**************************************************************************//** - * Get the pseudospectrum. Memory for the output spectrum must be allocated by the - * user, the size of the rows and columns are given by sl_rtl_aox_get_spectrum_size(). - * - * @param[in] item Pointer to the initialized libitem. - * @param[out] spectrum_out Outputted pseudospectrum. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_get_spectrum(sl_rtl_aox_libitem* item, float** spectrum_out); - -/**************************************************************************//** - * Get the polarization spectrum. Memory for the output spectrum must be allocated by the - * user, the size of the rows and columns are given by sl_rtl_aox_get_polarization_spectrum_size(). - * - * @param[in] item Pointer to the initialized libitem. - * @param[out] spectrum_out Outputted polarization pseudospectrum. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_get_polarization_spectrum(sl_rtl_aox_libitem* item, float** spectrum_out); - -/// Angle of Arrival / Departure antenna array radiation pattern -typedef void* sl_rtl_aox_antenna_pattern; - -/**************************************************************************//** - * Initialize the antenna radiation pattern item for the given array board. - * The antenna pattern item can be shared by multiple different estimators. - * - * @param[in] pattern Pointer to the pattern item to initialize. - * @param[in] array_type Array type of the board for which the pattern is loaded. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_antenna_pattern_init(sl_rtl_aox_antenna_pattern* pattern, enum sl_rtl_aox_array_type array_type); - -/**************************************************************************//** - * Set the given estimator to use the given antenna radiation pattern in the - * model. The same antenna pattern can be shared between multiple estimators. - * The antenna pattern can be cleared for an estimator by setting it to NULL. - * The estimator will then use the default model. - * @note: This function should be called only after the estimator is - * created. - * - * @param[in] item Pointer to the initialized libitem. - * @param[in] pattern Pointer to the initialized antenna pattern item. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_set_antenna_pattern(sl_rtl_aox_libitem* item, sl_rtl_aox_antenna_pattern* pattern); - -/**************************************************************************//** - * Deinitialize the antenna radiation pattern item. - * - * @param[in] pattern Pointer to the initialized pattern item. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_aox_antenna_pattern_deinit(sl_rtl_aox_antenna_pattern* pattern); - -/** @} */ // end addtogroup sl_rtl_aox - -/** - * @addtogroup sl_rtl_abr Accurate Bluetooth Ranging (ABR) - * @{ - * - * @brief Accurate Bluetooth Ranging - * - * These functions are related to the phase-based estimation of distance from - * I/Q-samples. - * The distances can be calculated following these steps: - * 1. Initialize a sl_rtl_abr_libitem instance - * 2. Set up the calculation parameters - * 3. Create the estimator - * 4. Process the I/Q data into a distance - * 5. Get distance estimate - */ - -/// ABR estimator mode -enum sl_rtl_abr_algo_mode{ - SL_RTL_ABR_ALGO_MODE_REAL_TIME_BASIC = 1, ///< Medium filtering, medium response, medium CPU cost. Suitable for real-time tracking. - SL_RTL_ABR_ALGO_MODE_STATIC, ///< TODO add description, - - SL_RTL_ABR_ALGO_MODE_LAST ///< Placeholder -}; - -// ABR -enum sl_rtl_abr_cs_mode{ - SL_RTL_ABR_CS_MODE_RTP = 0, ///< Round-trip phase based estimation (RTP) - SL_RTL_ABR_CS_MODE_RTT = 1, ///< Round-trip time based estimation (RTT) - // SL_RTL_ABR_CS_MODE_RTP_RTT = 2, ///< Combination of RTP and RTT - SL_RTL_ABR_CS_MODE_LAST ///< Placeholder -}; - -// ABR tone quality. Currently only entered for RTP -enum sl_rtl_abr_tone_quality{ - SL_RTL_ABR_TONE_QUALITY_GOOD = 0, - SL_RTL_ABR_TONE_QUALITY_MEDIUM = 1, - SL_RTL_ABR_TONE_QUALITY_LOW = 2, - SL_RTL_ABR_TONE_QUALITY_UNAVAILABLE = 3 -}; - -// RTT -// Note: rssi_d1, rssi_d2, time_d1 and time_d2 are required to be from the same channels and in the same channel order. -typedef struct { - uint32_t num_time_stamps; ///< Number of frequencies, 0xFFFFFFFF or 0 if invalid. In case of invalid input, the previously estimated distance shall be returned. - int32_t* rssi_d1; ///< Array of RSSI values from device 1, enter INVALID_RSSI_VALUE for any unavailable RSSI measurement - int32_t* rssi_d2; ///< Array of RSSI values from device 2, enter INVALID_RSSI_VALUE for any unavailable RSSI measurement - int32_t* time_d1; ///< Array of time measurements from device 1, enter INVALID_TIME_VALUE for any unavailable time measurement - int32_t* time_d2; ///< Array of time measurements from device 2, enter INVALID_TIME_VALUE for any unavailable time measurement -} sl_rtl_abr_rtt_data; - -// RTP -typedef struct { - uint32_t num_tones; ///< Number of tones (frequencies), including advertisement channels. Advertisement channels should be marked as blank tones, but included into total number of tones. Max value and currently the only supported value is 79. 80 num_tones is accepted as well, but internally it is converted to 79. - float tones_frequency_delta_hz; ///< Frequency delta, Hz. Accepted value is 1 MHz for 79 tones configuration. -} sl_rtl_abr_parameters; - -typedef struct { - uint32_t* blank_tone_indices; ///< Tones that shall be ignored when making a distance estimation - uint32_t num_blank_tone_indices; - enum sl_rtl_abr_tone_quality* tone_qualities_d1; ///< num_tones elements, null ptr means not used - enum sl_rtl_abr_tone_quality* tone_qualities_d2; ///< num_tones elements, null ptr means not used - float* i_samples_d1; ///< Array of device 1 I components, enter INVALID_PCT_VALUE for any unavailable PCT measurement - float* q_samples_d1; ///< Array of device 1 Q components, enter INVALID_PCT_VALUE for any unavailable PCT measurement - float* i_samples_d2; ///< Array of device 2 I components, enter INVALID_PCT_VALUE for any unavailable PCT measurement - float* q_samples_d2; ///< Array of device 2 Q components, enter INVALID_PCT_VALUE for any unavailable PCT measurement - // sl_rtl_abr_doppler_params* doppler_params; ///< Support for the Doppler parameters to be added in future -} sl_rtl_abr_rtp_data; - -/// ABR library item -typedef void* sl_rtl_abr_libitem; - -/**************************************************************************//** - * Initialize the ABR libitem instance. - * - * @param[in] item Pointer to the libitem to be initialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_init(sl_rtl_abr_libitem* item); - -/**************************************************************************//** - * Deinitialize a libitem instance of the ABR estimator. - * - * @param[in] item Pointer to the libitem to be deinitialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_deinit(sl_rtl_abr_libitem* item); - -/**************************************************************************//** - * Set the estimation mode. - * - * @param[in] item Pointer to the initialized ABR libitem - * @param[in] mode Estimator mode as ::sl_rtl_abr_algo_mode - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Set the estimation mode. For example, ::SL_RTL_ABR_ALGO_MODE_BASIC sets medium - * filtering. For further description of the modes, see the documentation - * of ::sl_rtl_abr_algo_mode. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_set_algo_mode(sl_rtl_abr_libitem* item, enum sl_rtl_abr_algo_mode mode); - -/**************************************************************************//** - * Set the estimation cs_mode. - * - * @param[in] item Pointer to the initialized ABR libitem - * @param[in] mode cs_mode as ::sl_rtl_abr_cs_mode - * @return ::SL_RTL_ERROR_SUCCESS if successful - * - * Set the desired cs_mode. For example, ::SL_RTL_ABR_CS_MODE_RTP uses round-trip - * phase based cs_mode. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_set_cs_mode(sl_rtl_abr_libitem* item, enum sl_rtl_abr_cs_mode cs_mode); - -/**************************************************************************//** - * Set parameters for estimation. Must be called before sl_rtl_abr_create_estimator. - * - * @param[in] item Pointer to the initialized ABR libitem - * @param[in] parameters Data structure with CS initialisation parameters for the estimator - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_set_parameters(sl_rtl_abr_libitem* item, sl_rtl_abr_parameters* parameters); - -/**************************************************************************//** - * Create the estimator after initializing the libitem and setting parameters. - * - * @param[in] item Pointer to the initialized and configured ABR libitem - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_create_estimator(sl_rtl_abr_libitem* item); - -/* NARROWBAND PHASE BASED DISTANCE ESTIMATION */ - -/**************************************************************************//** - * Calculate distance estimate based on RTP. - * - * @param[in] item Pointer to the initialized and configured ABR libitem - * @param[in] rtp_data Data structure with the RTP measurement data - * @return ::SL_RTL_ERROR_SUCCESS if successful and - * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final - * and more input data needs to be processed. - * - * Calculate the distance estimate from the given I/Q samples captured at the - * given frequencies. Use sl_rtl_abr_get_distance to fetch the latest distance - * estimate. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_process_rtp(sl_rtl_abr_libitem* item, sl_rtl_abr_rtp_data* rtp_data); - -/**************************************************************************//** - * Calculate distance estimate based on RTT. - * - * @param[in] item Pointer to the initialized and configured ABR libitem - * @param[in] rtt_data Data structure with the RTT measurement data - * @return ::SL_RTL_ERROR_SUCCESS if successful and - * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final - * and more input data needs to be processed. - * - * Calculate the distance estimate from the given device time samples. - * Use sl_rtl_abr_get_distance to fetch the latest distance - * estimate. - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_process_rtt(sl_rtl_abr_libitem* item, sl_rtl_abr_rtt_data* rtt_data); - -/* DISTANCE ESTIMATION COMMON*/ - -/**************************************************************************//** - * Get likeliness of the distance estimate. - * - * @param[in] item Pointer to the initialized ABR libitem - * @param[out] distance Distance out in meters. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_get_distance(sl_rtl_abr_libitem* item, float* distance); - -/**************************************************************************//** - * Get distance estimate. - * - * @param[in] item Pointer to the initialized ABR libitem - * @param[out] distance_likeliness Likeliness between 0.0 - 1.0 (unlikely - likely) of the estimated distance - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_abr_get_distance_likeliness(sl_rtl_abr_libitem* item, float* distance_likeliness); - -/** @} */ // end addtogroup sl_rtl_abr - -/** - * @addtogroup sl_rtl_loc Location Finding - * @{ - * - * @brief Location Finding - * - * These functions are related to the calculation of positions from angles - * and distances. - */ - -#define SL_RTL_LOC_ALL_LOCATORS (uint32_t)(-1) -#define SL_RTL_LOC_ALL_TAGS INT32_MAX - -/// Locator-specific measurements -enum sl_rtl_loc_locator_measurement_field{ - SL_RTL_LOC_LOCATOR_MEASUREMENT_AZIMUTH, ///< Measured azimuth from locator to tag - SL_RTL_LOC_LOCATOR_MEASUREMENT_ELEVATION, ///< Measured elevation from locator to tag - SL_RTL_LOC_LOCATOR_MEASUREMENT_DISTANCE, ///< Measured distance from locator to tag - - SL_RTL_LOC_LOCATOR_MEASUREMENT_AZIMUTH_DEVIATION, ///< Azimuth stdev - SL_RTL_LOC_LOCATOR_MEASUREMENT_ELEVATION_DEVIATION, ///< Elevation stdev - SL_RTL_LOC_LOCATOR_MEASUREMENT_DISTANCE_DEVIATION, ///< Distance stdev - - SL_RTL_LOC_LOCATOR_LAST -}; - -/// Target-specific measurements - Not yet supported -enum sl_rtl_loc_target_measurement_field{ - SL_RTL_LOC_TARGET_MEASUREMENT_LAST -}; - -/// Estimation mode -enum sl_rtl_loc_estimation_mode{ - SL_RTL_LOC_ESTIMATION_MODE_TWO_DIM_FAST_RESPONSE, ///< Two-dimensional mode - Only X and Y plane considered, less filtered mode for fast moving assests - SL_RTL_LOC_ESTIMATION_MODE_THREE_DIM_FAST_RESPONSE, ///< Three-dimensional mode - Covers X, Y and Z planes, less filtered mode for fast moving assests - - SL_RTL_LOC_ESTIMATION_MODE_TWO_DIM_HIGH_ACCURACY, ///< Two-dimensional mode - Only X and Y plane considered, more filtered mode for relatively static assets - SL_RTL_LOC_ESTIMATION_MODE_THREE_DIM_HIGH_ACCURACY, ///< Three-dimensional mode - Covers X, Y and Z planes, more filtered mode for relatively static assets - - SL_RTL_LOC_ESTIMATION_MODE_LAST -}; - -/// Measurement validation method -enum sl_rtl_loc_measurement_validation_method{ - SL_RTL_LOC_MEASUREMENT_VALIDATION_MINIMUM, ///< Only the basic validation integrated in the locationing algorithm (default) - SL_RTL_LOC_MEASUREMENT_VALIDATION_MEDIUM, ///< May discard the most inaccurate measurements with an additional calculation round - SL_RTL_LOC_MEASUREMENT_VALIDATION_FULL, ///< May discard the most inaccurate measurements with several calculation rounds -}; - -/// Locator-specific parameters related to locationing -enum sl_rtl_loc_locator_parameter { - SL_RTL_LOC_LOCATOR_PARAMETER_X_COORDINATE, ///< Set X-axis coordinate of the locator - SL_RTL_LOC_LOCATOR_PARAMETER_Y_COORDINATE, ///< Set Y-axis coordinate of the locator - SL_RTL_LOC_LOCATOR_PARAMETER_Z_COORDINATE, ///< Set Z-axis coordinate of the locator - SL_RTL_LOC_LOCATOR_PARAMETER_X_ORIENTATION, ///< Set X-axis rotation of the locator (Euler angles) in degrees - SL_RTL_LOC_LOCATOR_PARAMETER_Y_ORIENTATION, ///< Set Y-axis rotation of the locator (Euler angles) in degrees - SL_RTL_LOC_LOCATOR_PARAMETER_Z_ORIENTATION, ///< Set Z-axis rotation of the locator (Euler angles) in degrees - - SL_RTL_LOC_LOCATOR_PARAMETER_LAST -}; - -enum sl_rtl_loc_default_accuracy_parameter { - SL_RTL_LOC_DEFAULT_AZIMUTH_STDEV, ///< Set the default azimuth stdev - SL_RTL_LOC_DEFAULT_ELEVATION_STDEV, ///< Set the default elevation stdev - SL_RTL_LOC_DEFAULT_MINIMUM_DISTANCE_STDEV, ///< Set the default minimum distance stdev, will be added to the effective stdev value - SL_RTL_LOC_DEFAULT_DISTANCE_STDEV_COEFF, ///< Set the default distance stdev coeff, will be added after multiplied with the distance measurement to the effective stdev value -}; - -/// Target-specific parameters related to locationing -enum sl_rtl_loc_target_parameter{ - SL_RTL_LOC_TARGET_PARAMETER_TARGET_HEIGHT, // Z-position when the target is statically on some x-y-plane - SL_RTL_LOC_TARGET_CLEAR_TARGET_HEIGHT, // Clear the previously set Z-position - - SL_RTL_LOC_TARGET_PARAMETER_LAST -}; - -/// Locationing state results -enum sl_rtl_loc_result{ - SL_RTL_LOC_RESULT_POSITION_X = 0, ///< Estimated X-axis position of the target - SL_RTL_LOC_RESULT_POSITION_Y, ///< Estimated Y-axis position of the target - SL_RTL_LOC_RESULT_POSITION_Z, ///< Estimated Z-axis position of the target - - SL_RTL_LOC_RESULT_POSITION_RADIUS, ///< The combined radius (stdev) of the location estimate - SL_RTL_LOC_RESULT_POSITION_STDEV_X, ///< The accuracy (stdev) of the location x-coordinate estimate - SL_RTL_LOC_RESULT_POSITION_STDEV_Y, ///< The accuracy (stdev) of the location y-coordinate estimate - SL_RTL_LOC_RESULT_POSITION_STDEV_Z, ///< The accuracy (stdev) of the location z-coordinate estimate - - SL_RTL_LOC_RESULT_POSITION_VELOCITY_X, ///< Estimated X-axis velocity of the target - SL_RTL_LOC_RESULT_POSITION_VELOCITY_Y, ///< Estimated Y-axis velocity of the target - SL_RTL_LOC_RESULT_POSITION_VELOCITY_Z, ///< Estimated Z-axis velocity of the target - SL_RTL_LOC_RESULT_POSITION_ACCELERATION_X, ///< Estimated X-axis acceleration of the target - SL_RTL_LOC_RESULT_POSITION_ACCELERATION_Y, ///< Estimated Y-axis acceleration of the target - SL_RTL_LOC_RESULT_POSITION_ACCELERATION_Z, ///< Estimated Z-axis acceleration of the target - - SL_RTL_LOC_RESULT_LAST ///< Number of results -}; - -/// Locator item which contains the position and orientation of the locator array -struct sl_rtl_loc_locator_item{ - float coordinate_x; ///< X-axis coordinate of the locator - float coordinate_y; ///< Y-axis coordinate of the locator - float coordinate_z; ///< Z-axis coordinate of the locator - float orientation_x_axis_degrees; ///< X-axis rotation of the locator (Euler angles) in degrees - float orientation_y_axis_degrees; ///< Y-axis rotation of the locator (Euler angles) in degrees - float orientation_z_axis_degrees; ///< Z-axis rotation of the locator (Euler angles) in degrees -}; - -/// Locationing library item -typedef void* sl_rtl_loc_libitem; - -// Initialization functions - -/**************************************************************************//** - * Initialize the locationing libitem instance. - * - * @param[in] item Pointer to the libitem to be initialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_init(sl_rtl_loc_libitem* item); - -/**************************************************************************//** - * Deinitialize the locationing libitem instance. - * - * @param[in] item Pointer to the libitem to be initialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_deinit(sl_rtl_loc_libitem* item); - -/**************************************************************************//** - * Reinitialize the locationing libitem instance. - * - * Reset the libitem's internal values to the starting point so that it can - * start all over from the beginning. This can be used, for example, in testing - * instead of deleting and re-creating the libitem object. - * - * @param[in] item Pointer to the libitem to be initialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_reinit(sl_rtl_loc_libitem* item); - -/**************************************************************************//** - * Set the locationing dimensionality mode. Possible choices are 2D or 3D - * modes. Two-dimensional mode does not vary the z-position of the target and - * assumes it is 0 at all times. When updating, for example, the distance measure- - * ment from the locator to the target in 2D mode, it should be noted that - * even if the locator and tag are on different z-planes, the distance should - * be given as the distance as if they were on the same z-plane. - * - * @param[in] item Pointer to the libitem - * @param[in] mode Estimation mode as enum - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_mode(sl_rtl_loc_libitem* item, enum sl_rtl_loc_estimation_mode mode); - -/**************************************************************************//** - * Set the measurement validation method. If not given, the minimum method is - * used. Possible choices are minimum, medium, and full. The minimum does not - * increase the calculation CPU load because it is integrated inside the algorithm's - * normal operation. The medium and full methods use additionally one or - * multiple calculation rounds respectively and may discard the most - * inaccurate measurements from the calculation. However, they will always leave - * enough of them to calculate the estimate. - * - * @param[in] item Pointer to the libitem - * @param[in] method Validation method as enum - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_measurement_validation(sl_rtl_loc_libitem* item, enum sl_rtl_loc_measurement_validation_method method); - -/**************************************************************************//** - * Add a locator item into the locationing estimator after setting its position - * and orientation parameters. Add all locators using this - * function before calling ::sl_rtl_loc_create_position_estimator to create - * the estimator instance. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_item Locator item instance to be added - * @param[out] locator_id_out ID of the locator assigned by the library - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_add_locator(sl_rtl_loc_libitem* item, struct sl_rtl_loc_locator_item* locator_item, uint32_t* locator_id_out); - -/**************************************************************************//** - * Add an asset tag item into the locationing estimator. - * - * @param[in] item Pointer to the libitem - * @param[out] tag_id_out ID of the tag assigned by the library - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_add_tag(sl_rtl_loc_libitem* item, int32_t *tag_id_out); - -/**************************************************************************//** - * Remove an asset tag item previously added with sl_rtl_loc_add_tag. - * - * @param[in] item Pointer to the libitem - * @param[out] ID of the tag to be removed - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_remove_tag(sl_rtl_loc_libitem* item, int32_t tag_id); - -/**************************************************************************//** - * Create the position estimator instance after all locators have been added. - * - * @param[in] item Pointer to the libitem - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_create_position_estimator(sl_rtl_loc_libitem* item); - -// Processing functions - -/**************************************************************************//** - * Set locator-specific parameters, such as the azimuth and elevation - * measurement covariances. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator for which the parameter will be set - * @param[in] parameter Parameter to be set (as enum) - * @param[in] value New value for the parameter - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_locator_parameter(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_parameter parameter, float value); - -/**************************************************************************//** - * Set target-specific parameters, such as the known target height. - - * - * @param[in] item Pointer to the libitem - * @param[in] parameter Parameter to be set (as enum) - * @param[in] value New value for the parameter - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_target_parameter(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_parameter parameter, float value); - -/**************************************************************************//** - * Set target-specific parameters, such as the known target height for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] parameter Parameter to be set (as enum) - * @param[in] value New value for the parameter - * @param[in] tag_id TagID of the asset to be changed or ::SL_RTL_LOC_ALL_TAGS - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_target_parameter_tag(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_parameter parameter, float value, int32_t tag_id); - -/**************************************************************************//** - * Clear previous measurements. Call this function before setting - * new measurements if the previous measurements are not valid for the next - * iteration step. - * - * @param[in] item Pointer to the libitem - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_clear_measurements(sl_rtl_loc_libitem* item); - -/**************************************************************************//** - * Clear previous measurements for a specified tag. Call this function before setting - * new measurements if the previous measurements are not valid for the next - * iteration step. - * - * @param[in] item Pointer to the libitem - * @param[in] tag_id TagID of the asset to be changed or ::SL_RTL_LOC_ALL_TAGS - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_clear_measurements_tag(sl_rtl_loc_libitem* item, int32_t tag_id); - -/**************************************************************************//** - * Set a new measurement for a locator specified by the locator ID. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator for which the measurement will be set - * @param[in] field Measurement to be updated (as enum) - * @param[in] value New value for the measurement - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_locator_measurement(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float value); - -/**************************************************************************//** - * Set a new measurement for a locator specified by the locator ID for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator for which the measurement will be set - * @param[in] field Measurement to be updated (as enum) - * @param[in] value New value for the measurement - * @param[in] tag_id TagID of the asset to be changed - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_locator_measurement_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float value, int32_t tag_id); - -/**************************************************************************//** - * Set a new measurement for the target. Because the current version does not support this - * function, calling it has no effect. - * - * @param[in] item Pointer to the libitem - * @param[in] field Measurement to be updated (as enum) - * @param[in] value New value for the measurement - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_target_measurement(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_measurement_field field, float value); - -/**************************************************************************//** - * Set the default accuracy value for direction / distance. - * This value will be used if not given explicitly by measurement. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose parameter will be set - * @param[in] parm Parameter to be set (as enum) - * @param[in] value New value for the default accuracy - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_set_default_accuracy(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_default_accuracy_parameter param, float value); - -/**************************************************************************//** - * Process the current time step of the locationing filter. Call this function - * after old measurements are cleared and new - * measurements are set for the current time step. The process will step - * the filter forward and provide new state results and state covariance - * values, which can be retrieved with separate function calls. - * - * @param[in] item Pointer to the libitem - * @param[in] time_step Process time interval in seconds. This is the time - * separation between the previous step and this current step. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_process(sl_rtl_loc_libitem* item, float time_step); - -/**************************************************************************//** - * Process the current time step of the locationing filter for a specified tag. - * Call this function after old measurements are cleared and new - * measurements are set for the current time step. The process will step - * the filter forward and provide new state results and state covariance - * values, which can be retrieved with separate function calls. - * - * @param[in] item Pointer to the libitem - * @param[in] time_step Process time interval in seconds. This is the time - * separation between the previous step and this current step. - * @param[in] tag_id TagID of the asset to be processed or ::SL_RTL_LOC_ALL_TAGS - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_process_tag(sl_rtl_loc_libitem* item, float time_step, int32_t tag_id); - -/**************************************************************************//** - * Get result of the current state variables or state covariances. - * - * @param[in] item Pointer to the libitem - * @param[in] result The desired state variable result as enum - * @param[out] value The value output of the state variable - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_result(sl_rtl_loc_libitem* item, enum sl_rtl_loc_result result, float* value); - -/**************************************************************************//** - * Get result of the current state variables or state covariances for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] result The desired state variable result as enum - * @param[out] value The value output of the state variable - * @param[in] tag_id TagID of the asset to fetch the results for - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_result_tag(sl_rtl_loc_libitem* item, enum sl_rtl_loc_result result, float* value, int32_t tag_id); - -/**************************************************************************//** - * Get the latest measurement converted into the coordinate system of the - * multi-locator system. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[in] field Measurement to be retrieved (as enum) - * @param[out] value_out The value output of the state variable - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_measurement_in_system_coordinates(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float* value_out); - -/**************************************************************************//** - * Get the latest measurement converted into the coordinate system of the - * multi-locator system for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[in] field Measurement to be retrieved (as enum) - * @param[out] value_out The value output of the state variable - * @param[in] tag_id TagID of the asset - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_measurement_in_system_coordinates_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float* value_out, int32_t tag_id); - -/**************************************************************************//** - * Get the expected direction of the asset for the locator. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[out] azimuth The expected azimuth value - * @param[out] elevation The expected elevation value - * @param[out] distance The expected distance value - * @return ::SL_RTL_ERROR_SUCCESS if the locator does not require correction - * @return ::SL_RTL_ERROR_INCORRECT_MEASUREMENT if the locator's previous measurement was ignored because the error is too large - * @returns Another error code in case of error - * - * Position calculation has a better overall view to the asset's location than - * any individual locator. If the direction angles differ too much from - * the expected direction, the locator can be instructed to correct its - * internal state so that in can recover from this incorrectness faster. - * See also sl_rtl_aox_set_expected_direction() - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_expected_direction(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance); - -/**************************************************************************//** - * Get the expected direction of the asset for the locator for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[out] azimuth The expected azimuth value - * @param[out] elevation The expected elevation value - * @param[out] distance The expected distance value - * @param[in] tag_id TagID of the asset - * @return ::SL_RTL_ERROR_SUCCESS if the locator does not require correction - * @return ::SL_RTL_ERROR_INCORRECT_MEASUREMENT if the locator's previous measurement was ignored because of too large error - * @returns Another error code in case of error - * - * Position calculation has a better overall view to the asset's location than - * any individual locator. If the direction angles differ too much from - * the expected direction, the locator can be instructed to correct its - * internal state so that in can recover from this incorrectness faster. - * See also sl_rtl_aox_set_expected_direction(). - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_expected_direction_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance, int32_t tag_id); - -/**************************************************************************//** - * Get the deviation values for expected direction of the asset for the locator. - * - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[out] azimuth The expected azimuth value's standard deviation - * @param[out] elevation The expected elevation value's standard deviation - * @param[in] item Pointer to the libitem - * @param[out] distance The expected distance value's standard deviation - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_expected_deviation(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance); - -/**************************************************************************//** - * Get the deviation values for expected direction of the asset for the locator - * for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator whose measurement will be retrieved - * @param[out] azimuth The expected azimuth value's standard deviation - * @param[out] elevation The expected elevation value's standard deviation - * @param[out] distance The expected distance value's standard deviation - * @param[in] tag_id TagID of the asset - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_get_expected_deviation_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance, int32_t tag_id); - -/**************************************************************************//** - * Get the number of locators, which are disabled from position calculation because - * the direction error is too large. - * - * @param[in] item Pointer to the libitem - * @returns Number of locators needing correction, or -1 in case of any other error - *****************************************************************************/ -int sl_rtl_loc_get_number_disabled(sl_rtl_loc_libitem* item); - -/**************************************************************************//** - * Get the number of locators, which are disabled from position calculation because - * the direction error is too large, for a specified tag. - * - * @param[in] item Pointer to the libitem - * @param[in] tag_id TagID of the asset - * @returns Number of locators needing correction, or -1 in case of any other error - *****************************************************************************/ -int sl_rtl_loc_get_number_disabled_tag(sl_rtl_loc_libitem* item, int32_t tag_id); - -/**************************************************************************//** - * Check if the asset is in reach of a given locator according to the - * position-based filtering. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of the locator to run the test - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -bool sl_rtl_loc_filter_in_reach(sl_rtl_loc_libitem* item, uint32_t locator_id); - -/**************************************************************************//** - * Clear all the position-based filters from a locator or from all - * locators. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_clear(sl_rtl_loc_libitem* item, uint32_t locator_id); - -/**************************************************************************//** - * Add a position-based filter. This filter is based on the distance from a locator. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] radius Distance from the locator - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_sphere(sl_rtl_loc_libitem* item, uint32_t locator_id, float radius, bool exclude_region); - -/**************************************************************************//** - * Add a position-based filter. The two dimensional filter is based on - * the distance from a locator. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] radius Distance from the locator - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_circle(sl_rtl_loc_libitem* item, uint32_t locator_id, float radius, bool exclude_region); - -/**************************************************************************//** - * Add a position-based filter. This filter defines relative distances in - * coordinate axes' directions. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] xDelta Maximum distance in X-coordinate direction - * @param[in] yDelta Maximum distance in Y-coordinate direction - * @param[in] zDelta Maximum distance in Z-coordinate direction - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_box(sl_rtl_loc_libitem* item, uint32_t locator_id, float xDelta, float yDelta, float zDelta, bool exclude_region); - -/**************************************************************************//** - * Add a position-based filter. This two dimensional filter defines relative - * distances in coordinate axes' directions. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] xDelta Maximum distance in X-coordinate direction - * @param[in] yDelta Maximum distance in Y-coordinate direction - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_rect(sl_rtl_loc_libitem* item, uint32_t locator_id, float xDelta, float yDelta, bool exclude_region); - -/**************************************************************************//** - * Add a position-based filter. This filter defines an area in global - * coordinates. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] minX Minimum X-coordinate value - * @param[in] maxX Maximum X-coordinate value - * @param[in] minY Minimum Y-coordinate value - * @param[in] maxY Maximum Y-coordinate value - * @param[in] minZ Minimum Z-coordinate value - * @param[in] maxZ Maximum Z-coordinate value - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_room(sl_rtl_loc_libitem* item, uint32_t locator_id, float minX, float maxX, float minY, float maxY, float minZ, float maxZ, bool exclude_region); - -/**************************************************************************//** - * Add a position-based filter. The two dimensional filter defines an area in - * global coordinates. - * The filter can be added to one locator or all locators. A locator may - * have several filters which are combined. - * - * @param[in] item Pointer to the libitem - * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS - * @param[in] minX Minimum X-coordinate value - * @param[in] maxX Maximum X-coordinate value - * @param[in] minY Minimum Y-coordinate value - * @param[in] maxY Maximum Y-coordinate value - * @param[in] exclude_region If true, define an excluded region instead - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_filter_floor(sl_rtl_loc_libitem* item, uint32_t locator_id, float minX, float maxX, float minY, float maxY, bool exclude_region); - -/**************************************************************************//** - * Enable trilateration method in location calculation. - * - * The trilateration method calculates the position based on the distances - * from the locators rather than the direction angles. This function enables - * the method, but the location calculation may still utilize also the - * directon if available to further increase the accuracy. - * - * Trilateration method is not turned on by default. - * - * @param[in] item Pointer to the libitem - * @param[in] value Turn the trilateration on or off - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_enable_trilateration(sl_rtl_loc_libitem* item, bool value); - -/**************************************************************************//** - * Prefer the asset location below or above the locator plane. - * - * If the locators are all in the same plane (or close to it), the height of - * the asset may become ambiguous. Set the preference to be below or above - * plane so that is more likely to end up in the correct position. - * - * The default options is below the plane. - * - * @param[in] item Pointer to the libitem - * @param[in] value Turn the trilateration on or off - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_loc_trilateration_prefer_below_plane(sl_rtl_loc_libitem* item, bool value); - -/** @} */ // end addtogroup sl_rtl_loc - -/** - * @addtogroup sl_rtl_util Utility Functionality - * @{ - * - * @brief Utility Functionality - * - * These functions provide supporting functionality such as conversions, - * additional filtering, diagnostics, and setup functions. - */ - -/// Utility library item -typedef void* sl_rtl_util_libitem; - -/// Util parameter -enum sl_rtl_util_parameter{ - SL_RTL_UTIL_PARAMETER_AMOUNT_OF_FILTERING = 0 ///< Amount of filtering in range [0.0f, 1.0f] -}; - -/**************************************************************************//** - * Initialize the Util libitem instance. - * - * @param[in] item Pointer to the libitem to be initialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_init(sl_rtl_util_libitem* item); - -/**************************************************************************//** - * Deinitialize a Util libitem instance. - * - * @param[in] item Pointer to the libitem to be deinitialized - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_deinit(sl_rtl_util_libitem* item); - -/**************************************************************************//** - * Set util parameters. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] parameter Parameter to change - * @param[in] value Value of the parameter - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_set_parameter(sl_rtl_util_libitem* item, enum sl_rtl_util_parameter parameter, float value); - -/**************************************************************************//** - * Filter a value using the moving average. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] value_in Value to be fed to the filter - * @param[out] value_out Pointer to the filtered value - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_filter(sl_rtl_util_libitem* item, float value_in, float* value_out); - -/**************************************************************************//** - * Convert an RSSI-value to distance in meters. - * - * @param[in] tx_power Reference RSSI value of the TX-device at 1.0 m distance in dBm, for example -45.0f - * @param[in] rssi Measured RSSI from the receiver - * @param[out] distance_out Distance in meters - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_rssi2distance(float tx_power, float rssi, float* distance_out); - -/**************************************************************************//** - * Set up the IQ sample quality analysis. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] level Analysis level - * @param[in] num_antennas The number of antennas in the array - * @param[in] raw_samples Data contains raw samples instead of picked ones - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_setup(sl_rtl_util_libitem *item, uint32_t level, uint32_t num_antennas, bool raw_samples); - -/**************************************************************************//** - * Set up parameters for the IQ sample quality analysis. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] sample_rate The sampling rate - * @param[in] sample_offset The offset for the picked sample in the sampling slot - * @param[in] samples_in_slot Number of samples in the sampling slot - * @param[in] number_of_channels Number of radio channels - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_parameters(sl_rtl_util_libitem* item, uint32_t sample_rate, uint8_t sample_offset, uint8_t samples_in_slot, uint8_t number_of_channels); - -/**************************************************************************//** - * Set up IQ sample QA downsampling ratio. - * - * Set the downsampling factor used during the antenna samples (related to the - * sampling rate of the reference period) - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] dsf The downsampling factor - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_downsampling_factor(sl_rtl_util_libitem* item, float dsf); - -/**************************************************************************//** - * Set data samples offset. - * - * Set the offset for the data samples from the start of the reference - * period. The use of this function is optional and, if not given, - * the default values are used. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] offset The data samples' offset - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_data_offset(sl_rtl_util_libitem* item, uint32_t offset); - -/**************************************************************************//** - * Set the switch pattern for the IQ sample quality. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] size The size of the switch pattern - * @param[in] pattern Array of integers representing the switch pattern - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_switch_pattern(sl_rtl_util_libitem* item, uint32_t size, uint32_t *pattern); - -/**************************************************************************//** - * Feed the IQ sample quality analysis the reference period data. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] num_samples The size of data - * @param[in] i_samples I-part of the sample data - * @param[in] q_samples Q-part of the sample data - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_add_reference(sl_rtl_util_libitem *item, uint32_t num_samples, float *i_samples, float *q_samples); -/**************************************************************************//** - * Feed the IQ sample quality analysis the antenna data. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] num_snapshots The size of the data - * @param[in] i_samples I-part of the sample data - * @param[in] q_samples Q-part of the sample data - * @param[in] channel Radio channel the packet is using. - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_add_data(sl_rtl_util_libitem *item, uint32_t num_snapshots, float **i_samples, float **q_samples, uint8_t channel); - -/**************************************************************************//** - * Get the overall results of the IQ sample quality analysis. - * - * @param[in] item Pointer to the initialized Util libitem - - * @return Bitmask of the failing tests, zero if everything passed - *****************************************************************************/ -uint32_t sl_rtl_util_iq_sample_qa_get_results(sl_rtl_util_libitem *item); - -/**************************************************************************//** - * Get the detailed results of the IQ sample quality analysis. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[out] iq_sample_qa_results The data structure with data related to the previous data packet - * @param[out] antenna_data The array of antenna-specific results - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_get_details(sl_rtl_util_libitem *item, sl_rtl_clib_iq_sample_qa_dataset_t *iq_sample_qa_results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); - -/**************************************************************************//** - * Get the detailed results of the IQ sample quality analysis for the specified radio channel. - * - * @param[in] item Pointer to the initialized Util libitem - * @param[in] channel Radio channel to show results for. - * @param[out] iq_sample_qa_results The data structure with data related to the last data packet using the requested channel - * @param[out] antenna_data The array of antenna specific results - * @return ::SL_RTL_ERROR_SUCCESS if successful - *****************************************************************************/ -enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_get_channel_details(sl_rtl_util_libitem* item, uint8_t channel, sl_rtl_clib_iq_sample_qa_dataset_t *iq_sample_qa_results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); - -/**************************************************************************//** - * Write the IQ sample quality analysis code as human readable strings in the provided buffer. - * - * @param[in] buf Buffer for the results to be written - * @param[in] size Size of the buffer - * @param[in] code The results previously received from the sl_rtl_util_iq_sample_qa_get_results() - * @returns pointer to the buffer containing data, or to a constant string - *****************************************************************************/ -char *sl_rtl_util_iq_sample_qa_code2string(char *buf, int size, uint32_t code); - -/** @} */ // end addtogroup sl_rtl_util - +/***************************************************************************//** + * @brief Silicon Labs Real-Time Locationing library for AoA/D and locationing + ******************************************************************************* + * # License + * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +/**************************************************************************//** +* +* Information on open-source software used with the library can be found in +* the included license.txt file. +* +******************************************************************************/ + +/**************************************************************************//** + * @file + * This is the API for the Silicon Labs Real-Time Locationing library. + * It provides an interface for estimating arrival and departure angles of + * signals and the positions of AoA/AoD signal transmitters. AoA stands for + * Angle-of-Arrival and AoD for Angle-of-Departure. AoX is used when + * referring to both techniques. + * + * Estimators can be created individually for each locator node using the API. + * Even multiple estimators with different parameters can be created for a + * single node. An instance of the estimator is created as a libitem and the + * estimator is initialized. Next, the estimation parameters such as antenna + * array type, number of antennas, estimation mode, and so on can be set + * using the function calls described below. + * + * One snapshot means a set of IQ-samples with exactly one sample per + * each antenna. + * + *****************************************************************************/ + +#ifndef SL_RTL_CLIB_API_H +#define SL_RTL_CLIB_API_H + +#include +#include + +/** + * @addtogroup sl_rtl_error Error Codes + * @{ + * + * @brief RTL library Error Codes + * + */ + +/// RTL error code +enum sl_rtl_error_code{ + SL_RTL_ERROR_SUCCESS = 0, ///< Successful execution / estimation complete + SL_RTL_ERROR_ARGUMENT, ///< Invalid argument + SL_RTL_ERROR_OUT_OF_MEMORY, ///< Memory / allocation failure + SL_RTL_ERROR_ESTIMATION_IN_PROGRESS, ///< Estimation not yet finished + SL_RTL_ERROR_NUMBER_OF_SNAPHOTS_DO_NOT_MATCH, ///< Initialized and calculated number of snapshots do not match + SL_RTL_ERROR_ESTIMATOR_NOT_CREATED, ///< Estimator not yet created + SL_RTL_ERROR_ESTIMATOR_ALREADY_CREATED, ///< Estimator already created, operation is not supported + SL_RTL_ERROR_NOT_INITIALIZED, ///< Library item not yet initialized + SL_RTL_ERROR_INTERNAL, ///< An internal error occurred + SL_RTL_ERROR_IQ_SAMPLE_QA, ///< IQ sample quality analysis failed + SL_RTL_ERROR_FEATURE_NOT_SUPPORTED, ///< The requested feature is not supported by the library + SL_RTL_ERROR_INCORRECT_MEASUREMENT, ///< The error of the last measurement for this locator was too large + + SL_RTL_ERROR_LAST ///< Number of error codes +}; +/** @} */ // end addtogroup sl_rtl_error + + +/** + * @addtogroup sl_rtl_aox Angle of Arrival / Departure + * @{ + * + * @brief Angle of Arrival / Departure + * + * These functions are related to the calculation of the Angle of Arrival + * and Angle of Departure from I/Q samples. The angles can be calculated + * following these steps: + * 1. Initialize a sl_rtl_aox_libitem instance. + * 2. Set up the antenna array and angle calculation parameters. + * 3. Create the estimator. + * 4. Set the antenna switching pattern. + * 5. Input the I/Q data into the libitem. + * 6. Process the I/Q data into an angle. + */ + +/// AoX antenna array type +enum sl_rtl_aox_array_type{ + SL_RTL_AOX_ARRAY_TYPE_4x4_URA = 0, ///< Silicon Labs Ref. 4x4 Uniform Rectangular Array + SL_RTL_AOX_ARRAY_TYPE_3x3_URA, ///< Silicon Labs Ref. 3x3 Uniform Rectangular Array + SL_RTL_AOX_ARRAY_TYPE_1x4_ULA, ///< Silicon Labs Ref. 1x4 Uniform Linear Array + SL_RTL_AOX_ARRAY_TYPE_4x4_DP_URA, ///< Silicon Labs Ref. 4x4 Uniform Dual Polarized Rectangular Array + SL_RTL_AOX_ARRAY_TYPE_COREHW_15x15_DP, ///< CoreHw Ref. 150 mm x 150 mm, 8 Element Dual Polarized Array + SL_RTL_AOX_ARRAY_TYPE_COREHW_12x12_DP, ///< CoreHw Ref. 120 mm x 120 mm, 8 Element Dual Polarized Array + SL_RTL_AOX_ARRAY_TYPE_COREHW_4x4_URA, ///< CoreHw Ref. 4x4 Uniform Rectangular Array + SL_RTL_AOX_ARRAY_TYPE_COREHW_2x2_URA, ///< CoreHw Ref. 2x2 Uniform Rectangular Array + + SL_RTL_AOX_ARRAY_TYPE_LAST ///< Placeholder +}; + +enum sl_rtl_aox_switch_pattern_array{ + SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_CP = 0, + SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_DP, + + SL_RTL_AOX_SWITCH_PATTERN_ARRAY_LAST +}; + +enum sl_rtl_aox_switch_pattern_options{ + SL_RTL_AOX_SWITCH_PATTERN_OPTIONS_DUAL_POLARIZED = 0x1, + SL_RTL_AOX_SWITCH_PATTERN_OPTIONS_EXTRA_REFERENCE = 0x2 +}; + +/// AoA, AoD (and AoX for backward compatibility) estimator modes +enum sl_rtl_aox_mode { + SL_RTL_AOA_MODE_ONE_SHOT_BASIC = 3, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOA_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOA_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. + SL_RTL_AOA_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. + + SL_RTL_AOA_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. + SL_RTL_AOA_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. + SL_RTL_AOA_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. + + SL_RTL_AOA_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOA_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOA_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. + + SL_RTL_AOA_MODE_LAST, ///< Placeholder + + /***************************************************************************/ + + SL_RTL_AOD_MODE_ONE_SHOT_BASIC = 3 | 0x20, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOD_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOD_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. + SL_RTL_AOD_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. + + SL_RTL_AOD_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. + SL_RTL_AOD_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. + SL_RTL_AOD_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. + + SL_RTL_AOD_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOD_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOD_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. + + SL_RTL_AOD_MODE_LAST, ///< Placeholder + + /***************************************************************************/ + + SL_RTL_AOX_MODE_ONE_SHOT_BASIC = 3 | 0x40, ///< Medium filtering, medium response. Returns 2D angle, requires 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOX_MODE_ONE_SHOT_BASIC_LIGHTWEIGHT, ///< Medium filtering, medium response, low CPU cost & low elevation resolution. 2D angle, req. 10 rounds. Most suitable for single shot measurement. + SL_RTL_AOX_MODE_ONE_SHOT_FAST_RESPONSE, ///< Low filtering, fast response, low CPU cost & low elevation resolution. 2D angle, requires 2 rounds. Most suitable for single shot measurement. + SL_RTL_AOX_MODE_ONE_SHOT_HIGH_ACCURACY, ///< High filtering, slow response. 2D angle, requires 20 rounds. Most suitable for single shot measurement. + + SL_RTL_AOX_MODE_ONE_SHOT_BASIC_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_BASIC with low CPU cost and returns 1D angle. Most suitable for single shot measurement. + SL_RTL_AOX_MODE_ONE_SHOT_FAST_RESPONSE_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_FAST_RESPONSE with low CPU cost, 1D angle. Most suitable for single shot measurement. + SL_RTL_AOX_MODE_ONE_SHOT_HIGH_ACCURACY_AZIMUTH_ONLY, ///< Equivalent to ONE_SHOT_HIGH_ACCURACY with low CPU cost, 1D angle. Most suitable for single shot measurement. + + SL_RTL_AOX_MODE_REAL_TIME_FAST_RESPONSE, ///< Low filtering, fast response, lowest CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOX_MODE_REAL_TIME_BASIC, ///< Medium filtering, medium response, medium CPU cost, 2D angle, Most suitable for real-time tracking. + SL_RTL_AOX_MODE_REAL_TIME_HIGH_ACCURACY, ///< High filtering, slow response, highest CPU cost, 2D angle, Most suitable for real-time tracking. + + SL_RTL_AOX_MODE_LAST ///< Placeholder +}; + +// AoX constraint types +enum sl_rtl_aox_constraint_type{ + SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH = 0, ///< Azimuth constraint in degrees + SL_RTL_AOX_CONSTRAINT_TYPE_ELEVATION, ///< Elevation constraint in degrees +}; + +// AoX switch pattern modes +enum sl_rtl_aox_switch_pattern_mode{ + SL_RTL_AOX_SWITCH_PATTERN_MODE_DEFAULT = 0, ///< Internally defined switch pattern: 0, 1, 2, ..., N-1, where N is the number of antennas + SL_RTL_AOX_SWITCH_PATTERN_MODE_RANDOM, ///< Internally defined random switch pattern + SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL, ///< Switch pattern set externally by the user + SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTRA_REFERENCE, ///< Switch pattern set externally by the user with extra reference antenna as a first +}; + +/// Angle of Arrival / Departure library item +typedef void* sl_rtl_aox_libitem; + +// Structure for IQ sample quality calculation antenna-specific results +typedef struct { + float level; ///< Antenna signal level, in decibels + float snr; ///< Antenna level signal to noise ratio, in decibels + float phase_value; ///< Antenna's average unrotated phase value in the packet, in radians + float phase_jitter; ///< Phase variation of snapshots' data of an antenna in packet, in radians +} sl_rtl_clib_iq_sample_qa_antenna_data_t; + +// Structure for IQ sample quality calculation results +typedef struct { + bool data_available; ///< If false, all the antenna values are undefined + uint32_t curr_channel; ///< Radio channel for the last packet + float ref_freq; ///< Apparent supplemental tone frequency + float ref_sndr; ///< Reference period signal to noise and distortion ratio + + // available only when raw samples are used + float switching_jitter; ///< Estimated antenna switching clock jitter +} sl_rtl_clib_iq_sample_qa_dataset_t; + +// return codes from the individual IQ sample QA tests +#define SL_RTL_AOX_IQ_SAMPLE_QA_ALL_OK 0 +#define SL_RTL_AOX_IQ_SAMPLE_QA_FAILURE 0xffffffff +typedef enum { + SL_RTL_AOX_IQ_SAMPLE_QA_INVAL_REF = 0, ///< Invalid reference period data + SL_RTL_AOX_IQ_SAMPLE_QA_DCOFFSET = 2, ///< DC offset too large + SL_RTL_AOX_IQ_SAMPLE_QA_SNDR = 3, ///< Reference period SNDR too large + SL_RTL_AOX_IQ_SAMPLE_QA_ROTATING_ERROR = 4, ///< Rotation error too large + SL_RTL_AOX_IQ_SAMPLE_QA_REF_ANT_PHASE_VALUE = 5, ///< Reference antenna phase value too big + SL_RTL_AOX_IQ_SAMPLE_QA_REF_ANT_PHASE_JITTER = 6, ///< Reference antenna phase jitter too large + SL_RTL_AOX_IQ_SAMPLE_QA_ANT_X_PHASE_JITTER = 7, ///< Antenna X phase jitter too large + SL_RTL_AOX_IQ_SAMPLE_QA_ALL_SAME_PHASE = 8, ///< All the antennas seen in the same phase + SL_RTL_AOX_IQ_SAMPLE_QA_SWICHING_JITTER = 9, ///< Switching jitter too large +} sl_rtl_slib_iq_sample_qa_result_t; + +#define SL_RTL_AOX_IQ_SAMPLE_QA_CLEAR_BIT(code, bit) \ + (code &= ~(1UL << bit)) +#define SL_RTL_AOX_IQ_SAMPLE_QA_SET_BIT(code, bit) \ + (code |= (1UL << bit)) +#define SL_RTL_AOX_IQ_SAMPLE_QA_IS_SET(code, bit) \ + (code & (1UL << bit)) + +/**************************************************************************//** + * Initialize the AoX libitem instance. + * + * @param[in] item Pointer to the libitem to be initialized. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_init(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Deinitialize a libitem instance of the AoX estimator. + * + * @param[in] item Pointer to the libitem to be deinitialized. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_deinit(sl_rtl_aox_libitem* item); + +/* NARROWBAND AOA ESTIMATION */ + +/**************************************************************************//** + * Set the number of signal snapshots to be used in the angle estimation. + * + * @param[in] item Pointer to the initialized AoX libitem. + * @param[in] num_snapshots Number of snapshots as positive integer value. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_num_snapshots(sl_rtl_aox_libitem* item, uint32_t num_snapshots); + +/**************************************************************************//** + * Set the array type used with the estimator. + * + * @param[in] item Pointer to the initialized AoX libitem. + * @param[in] array_type Array type as ::sl_rtl_aox_array_type. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Set the array type used with the estimator. + * For example, the array type should be set to ::SL_RTL_AOX_ARRAY_TYPE_4x4_URA + * when using the reference 4x4 URA board. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_array_type(sl_rtl_aox_libitem* item, enum sl_rtl_aox_array_type array_type); + +/**************************************************************************//** + * Set the estimation mode. + * + * @param[in] item Pointer to the initialized AoX libitem. + * @param[in] mode Estimator mode as ::sl_rtl_aox_mode. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Set the estimation mode. For example, ::SL_RTL_AOX_MODE_BASIC sets medium filtering + * and estimates both azimuth and elevation. For further description of the modes, + * see the documentation of ::sl_rtl_aox_mode. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_mode(sl_rtl_aox_libitem* item, enum sl_rtl_aox_mode mode); + +/**************************************************************************//** + * Estimate the I/Q-sample phase rotation error in degrees. + * + * @param[in] item Pointer to the initialized AoX libitem. + * @param[in] iq_data_downsampling_factor Ratio between reference period IQ-data sampling rate. + * and actual IQ-data (i.e., antenna array data) sampling rate. + * For example, 1e6 / 500e3 = 2.0 + * @param[in] i_samples Float-array of the reference period I samples. + * @param[in] q_samples Float-array of the reference period Q samples. + * @param[in] num_samples Number of samples, or size of the I or Q sample array. + * @param[out] phase_rotation_out Returned phase rotation value as float in degrees. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Estimate the I/Q-sample phase rotation error caused by switching + * and CTE frequency error based on I/Q samples from the reference period. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_calculate_iq_sample_phase_rotation(sl_rtl_aox_libitem* item, float iq_data_downsampling_factor, float* i_samples, float* q_samples, uint32_t num_samples, float* phase_rotation_out); + +/**************************************************************************//** + * Set a constant value of I/Q sample phase rotation in degrees. + * + * @param[in] item Pointer to the initialized AoX libitem. + * @param[in] phase_rotation Float value of I/Q sample phase rotation in degrees. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Set a constant value of I/Q sample phase rotation in degrees. + * The sample rotation can be used to correct the switching and CTE frequency error. + * @note: This function should be called only after the estimator is + * created. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_iq_sample_phase_rotation(sl_rtl_aox_libitem* item, float phase_rotation); + +/**************************************************************************//** + * Add constraints for the estimator. Call before sl_rtl_aox_create_estimator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] constraint_type Select which constraints should be added. + * @param[in] min_value Starting (minimum) value of the range including the min_value. + * @param[in] max_value Ending (maximum) value of the range including the max_value. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * For example, constraint for SL_RTL_AOX_CONSTRAINT_TYPE_AZIMUTH with min_value = 0 + * and max_value = 90 means that the angular range 0 to 90 degrees is excluded + * from the estimators internal processing range and angle estimated between that range + * are not considered as valid results. Setting constraints will help ruling + * out false multipath-detections when the locator is installed nearby a wall or + * a RF-reflective surface. + * @note: This function must called before the estimator is created. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_add_constraint(sl_rtl_aox_libitem* item, enum sl_rtl_aox_constraint_type constraint_type, float min_value, float max_value); + +/**************************************************************************//** + * Configure the IQ sampling sample rate for the library. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] sampleRate The new sample rate. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_sample_rate(sl_rtl_aox_libitem* item, float sampleRate); + +/**************************************************************************//** + * Configure the number of radio channels. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] channels The new number of radio channels. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_num_radio_channels(sl_rtl_aox_libitem* item, uint32_t channels); + +/**************************************************************************//** + * Configure the IQ sample quality analysis. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * This function turns the IQ sample quality analysis, + * which is not done by default. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_configure(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Get the IQ sample quality analysis overall results. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @return bitmask of found problems, zero indicates that everything is OK + *****************************************************************************/ +uint32_t sl_rtl_aox_iq_sample_qa_get_results(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Get the IQ sample quality analysis detailed results for the latest packet. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[out] results The data structure with data related to the latest data packet. + * @param[out] antenna_data The array of antenna-specific results. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Fetch the results for the latest packet. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_get_details(sl_rtl_aox_libitem* item, sl_rtl_clib_iq_sample_qa_dataset_t *results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); + +/**************************************************************************//** + * Get the IQ sample quality analysis detailed results for the requested radio channel. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] channel Radio channel to show results for. + * @param[out] results The data structure with data related to the last data packet using the requested channel. + * @param[out] antenna_data The array of antenna-specific results + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Fetch the latest results for the given radio channel, which may be other than the latest + * packet received. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_iq_sample_qa_get_channel_details(sl_rtl_aox_libitem* item, uint8_t channel, sl_rtl_clib_iq_sample_qa_dataset_t *results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); + +/**************************************************************************//** + * Create the estimator after initializing the libitem and setting parameters. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_create_estimator(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Convert data in RAW IQ-data buffers to downsampled IQ-data buffers. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] start_offset The start offset in the buffer (for example, for skipping a reference period). + * @param[in] iq_data_downsampling_factor Ratio between chip IQ-data sampling rate and downsampled rate. + * For example, 4.8e6 / 500e3 = 9.6 + * @param[in] raw_i_samples_in I-part sample buffer input + * @param[in] raw_q_samples_in Q-part sample buffer input + * @param[in] num_raw_samples_in Number of IQ-sample pairs in the input buffers. + * @param[out] i_samples_out Buffer for the processed I-samples. Must be allocated by the user. + * Indexing: i_samples_out[snapshot][antenna] + * @param[out] q_samples_out Buffer for the processed Q-samples. Must be allocated by the user. + * Indexing: q_samples_out[snapshot][antenna] + * @param[in] num_snapshots_out Number of snapshots allocated in the output buffers. This function + * checks if the given number of snapshots and calculated snapshots based on the length of RAW-data match + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_convert_raw_samples(sl_rtl_aox_libitem* item, uint32_t start_offset, float iq_data_downsampling_factor, float* raw_i_samples_in, float* raw_q_samples_in, uint32_t num_raw_samples_in, float** i_samples_out, float** q_samples_out, uint32_t num_snapshots_out); + +/**************************************************************************//** + * Calculate the number of downsampled snapshots in a RAW IQ-data buffer. Use this function to get the number + * of snapshots to allocate the i_samples and q_samples buffers for the process-function. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] num_raw_samples_in Total number of RAW IQ-sample pairs. + * @param[in] start_offset The start offset in the buffer, for example, for skipping a reference period. + * @param[in] iq_data_downsampling_factor Ratio between chip IQ-data sampling rate and downsampled rate. + * For example, 4.8e6 / 500e3 = 9.6. + * @param[in] num_channels Number of channels in the RAW data + * @param[out] num_snapshots_out Calculated number of snapshots based on the input. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_calculate_number_of_snapshots(sl_rtl_aox_libitem* item, uint32_t num_raw_samples_in, uint32_t start_offset, float iq_data_downsampling_factor, uint32_t num_channels, uint32_t* num_snapshots_out); + +/**************************************************************************//** + * Set switch pattern mode. Sets internal mode used by the library. See enum sl_rtl_aox_switch_pattern_mode + * for detailed description of the modes. If this function isn't called, a default switch pattern + * of: 0, 1, 2, 3, ..., N-1 will be used, where N is the number of antennas. + * Call this function at run-time after initializing and creating the estimator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] mode Required mode. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_switch_pattern_mode(sl_rtl_aox_libitem* item, enum sl_rtl_aox_switch_pattern_mode mode); + +/**************************************************************************//** + * Update switch pattern, which is used by the estimator algorithm. + * This function must be called before calling the function sl_rtl_aox_process. + * Call this function at run-time after initializing and creating the estimator. + * + * When using a custom pattern in SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL mode, + * the pattern in switch_pattern_in must not contain duplicate elements and the + * antenna indices must be within the range 0 to (number_of_antennas - 1). + * Number_of_antennas is the amount of antennas in the set array type, for example + * for the 4x4 URA this is 16 and for the 1x4 ULA this is 4. + * The length of the switching pattern must be equal to number_of_antennas. + * + * Note: The RF switch pattern indices may be different to the indices required by + * the RTL algorithm. For example, a 1x4 ULA might use RF controls [12, 13, 14, 15] + * for switching the antennas 1-4, but the RTL algorithm requires the switch pattern + * [0, 1, 2, 3]. If the RF controls are switched as [14, 15, 13, 12], + * the RTL algorithm requires the pattern [2, 3, 1, 0]. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] switch_pattern_in Pointer to the switch pattern array. The pointer must point to a valid switch pattern when + * SL_RTL_AOX_SWITCH_PATTERN_MODE_EXTERNAL is used. + * @param[out] switch_pattern_out Pointer to the user defined uint32_t* variable. This pointer must be non-zero when using + * internally defined switch pattern modes, otherwise can be zero. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_update_switch_pattern(sl_rtl_aox_libitem* item, uint32_t* switch_pattern_in, uint32_t** switch_pattern_out); + +/**************************************************************************//** + * Set the random seed for the switch pattern, which is used for the random pattern mode. + * Call this function at run-time after initializing and creating the estimator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] seed_value The seed value to be used. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_switch_pattern_seed(sl_rtl_aox_libitem* item, int32_t seed_value); + +/**************************************************************************//** + * Convert switching pattern from antenna indices to antenna switching pin control logic. + * Call this function at run-time after initializing and creating the estimator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] array_id Array ID, see ::sl_rtl_aox_switch_pattern_array, for example SL_RTL_AOX_SWITCH_PATTERN_ARRAY_4x4_DP + * @param[in] options Switch pattern options, see ::sl_rtl_aox_switch_pattern_options. + * Can be used to set for example dual polarization (default is single polarization). + * @param[in] switch_pattern_size_in The length of the input switching pattern. + * @param[in] switch_pattern_in The input switching pattern. + * @param[out] switch_pattern_size_out The outputted length of the converted switching pattern. + * @param[out] switch_pattern_out The outputted switching pattern. + * @return ::SL_RTL_ERROR_SUCCESS if successful + + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_convert_switch_pattern(sl_rtl_aox_libitem* item, uint32_t array_id, uint32_t options, uint32_t switch_pattern_size_in, uint32_t* switch_pattern_in, uint32_t* switch_pattern_size_out, uint32_t** switch_pattern_out); + +/**************************************************************************//** + * Reset estimator state. Calling this function causes the selected aox-mode to start from its initial state. + * Call this function at run-time after initializing and creating the estimator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_reset_estimator(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Calculate the angle estimate. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] i_samples Two-dimensional float-array of captured I samples + * as i_samples[snapshot][antenna]. + * @param[in] q_samples Two-dimensional float-array of captured Q samples + * as q_samples[snapshot][antenna], corresponding to the I samples array. + * @param[in] tone_frequency The frequency of the signal from which the + * I/Q data was captured from as float (e.g., 2.46e9f). + * @param[out] az_out Output azimuth angle. + * @param[out] el_out Output elevation angle. + * @return ::SL_RTL_ERROR_SUCCESS if successful and + * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final + * and more I/Q data needs to be processed. + * + * Calculate the angle estimate from the given I/Q samples captured at the + * given frequency. Call this function with new I/Q data as many times as + * indicated by the ::sl_rtl_aox_mode used by the estimator before the final + * estimate is output. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_process(sl_rtl_aox_libitem* item, float** i_samples, float** q_samples, float tone_frequency, float* az_out, float* el_out); + +/**************************************************************************//** + * Get the standard deviation for the latest AoA/AoD-estimate. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[out] az_std_dev Pointer for getting standard deviation of the + * latest azimuth estimate. + * @param[out] el_std_dev Pointer for getting standard deviation of the + * latest elevation estimate. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Call this function after sl_rtl_aox_process to fetch standard + * deviation for the latest AoA/AoD-estimate. Positive standard deviations + * indicate line-of-sight detection and negative values indicate likely + * non-line-of-sight detection. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_get_latest_aox_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev); + +/**************************************************************************//** + * Kept for backward compatibility + *****************************************************************************/ +static inline enum sl_rtl_error_code sl_rtl_aox_get_latest_aoa_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev) +{ + return sl_rtl_aox_get_latest_aox_standard_deviation(item, az_std_dev, el_std_dev); +} + +/**************************************************************************//** + * Kept for backward compatibility + *****************************************************************************/ +static inline enum sl_rtl_error_code sl_rtl_aox_get_latest_aod_standard_deviation(sl_rtl_aox_libitem* item, float* az_std_dev, float* el_std_dev) +{ + return sl_rtl_aox_get_latest_aox_standard_deviation(item, az_std_dev, el_std_dev); +} + +/**************************************************************************//** + * Feed the expected angles back to the locator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] expected_az Expected azimuth angle calculated by position algorithm. + * @param[in] expected_el Expected elevation angle calculated by position algorithm. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * The position algorithm has a more complete view of the asset's location. + * The direction it should be found can be calculated back and fed to the + * locator, so that it can recover faster when, + * for example, it has locked to a reflection rather than to the line of sight signal. + * See also sl_rtl_loc_get_expected_direction(). + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_expected_direction(sl_rtl_aox_libitem* item, float expected_az, float expected_el); + +/**************************************************************************//** + * Feed the expected angle deviations back to the locator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @param[in] deviation_az Deviation of the expected azimuth angle calculated by position algorithm. + * @param[in] deviation_el Deviation of the expected elevation angle calculated by position algorithm. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Report expected deviations calculated by the position algorithm back to + * the locator so that angles are calculated more accurately taking in account + * the correctness of the expected directions. If sl_rtl_aox_set_expected_direction() + * is called but this function is not called, the algorithm will use default values + * for the expected deviations. + * See also sl_rtl_loc_get_expected_deviation() and sl_rtl_aox_set_expected_direction(). + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_expected_deviation(sl_rtl_aox_libitem* item, float deviation_az, float deviation_el); + +/**************************************************************************//** + * Clear the expected directions and deviations from the locator. + * + * @param[in] item Pointer to the initialized and configured AoX libitem. + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * See also sl_rtl_aox_set_expected_direction() and sl_rtl_aox_set_expected_deviation(). + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_clear_expected_direction(sl_rtl_aox_libitem* item); + +/**************************************************************************//** + * Enable or disable outputting the pseudospectrum. This function should be called + * before creating the estimator. + * + * @param[in] item Pointer to the initialized libitem. + * @param[in] enable Set to true to enable outputting the pseudospectrum. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_enable_spectrum(sl_rtl_aox_libitem* item, bool enable); + +/**************************************************************************//** + * Get the size of the pseudospectrum. This function should be called after calling the AoX process + * function. + * + * @param[in] item Pointer to the initialized libitem. + * @param[out] rows Number of rows in the pseudospectrum data array. + * @param[out] cols Number of columns in the pseudospecutrm data array. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_get_spectrum_size(sl_rtl_aox_libitem* item, uint32_t* rows, uint32_t* cols); + +/**************************************************************************//** + * Get the size of the polarization pseudospectrum. + * This function should be called after calling the AoX process + * function. + * + * @param[in] item Pointer to the initialized libitem. + * @param[out] rows Number of rows in the polarization pseudospectrum data array. + * @param[out] cols Number of columns in the pseudospecutrm data array. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_get_polarization_spectrum_size(sl_rtl_aox_libitem* item, uint32_t* rows, uint32_t* cols); + +/**************************************************************************//** + * Get the pseudospectrum. Memory for the output spectrum must be allocated by the + * user, the size of the rows and columns are given by sl_rtl_aox_get_spectrum_size(). + * + * @param[in] item Pointer to the initialized libitem. + * @param[out] spectrum_out Outputted pseudospectrum. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_get_spectrum(sl_rtl_aox_libitem* item, float** spectrum_out); + +/**************************************************************************//** + * Get the polarization spectrum. Memory for the output spectrum must be allocated by the + * user, the size of the rows and columns are given by sl_rtl_aox_get_polarization_spectrum_size(). + * + * @param[in] item Pointer to the initialized libitem. + * @param[out] spectrum_out Outputted polarization pseudospectrum. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_get_polarization_spectrum(sl_rtl_aox_libitem* item, float** spectrum_out); + +/// Angle of Arrival / Departure antenna array radiation pattern +typedef void* sl_rtl_aox_antenna_pattern; + +/**************************************************************************//** + * Initialize the antenna radiation pattern item for the given array board. + * The antenna pattern item can be shared by multiple different estimators. + * + * @param[in] pattern Pointer to the pattern item to initialize. + * @param[in] array_type Array type of the board for which the pattern is loaded. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_antenna_pattern_init(sl_rtl_aox_antenna_pattern* pattern, enum sl_rtl_aox_array_type array_type); + +/**************************************************************************//** + * Set the given estimator to use the given antenna radiation pattern in the + * model. The same antenna pattern can be shared between multiple estimators. + * The antenna pattern can be cleared for an estimator by setting it to NULL. + * The estimator will then use the default model. + * @note: This function should be called only after the estimator is + * created. + * + * @param[in] item Pointer to the initialized libitem. + * @param[in] pattern Pointer to the initialized antenna pattern item. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_set_antenna_pattern(sl_rtl_aox_libitem* item, sl_rtl_aox_antenna_pattern* pattern); + +/**************************************************************************//** + * Deinitialize the antenna radiation pattern item. + * + * @param[in] pattern Pointer to the initialized pattern item. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_aox_antenna_pattern_deinit(sl_rtl_aox_antenna_pattern* pattern); + +/** @} */ // end addtogroup sl_rtl_aox + +/** + * @addtogroup sl_rtl_abr Accurate Bluetooth Ranging (ABR) + * @{ + * + * @brief Accurate Bluetooth Ranging + * + * These functions are related to the phase-based estimation of distance from + * I/Q-samples. + * The distances can be calculated following these steps: + * 1. Initialize a sl_rtl_abr_libitem instance + * 2. Set up the calculation parameters + * 3. Create the estimator + * 4. Process the I/Q data into a distance + * 5. Get distance estimate + */ + +/// ABR estimator mode +enum sl_rtl_abr_algo_mode{ + SL_RTL_ABR_ALGO_MODE_REAL_TIME_BASIC = 1, ///< Medium filtering, medium response, medium CPU cost. Suitable for real-time tracking. + SL_RTL_ABR_ALGO_MODE_STATIC, ///< TODO add description, + + SL_RTL_ABR_ALGO_MODE_LAST ///< Placeholder +}; + +// ABR +enum sl_rtl_abr_cs_mode{ + SL_RTL_ABR_CS_MODE_RTP = 0, ///< Round-trip phase based estimation (RTP) + SL_RTL_ABR_CS_MODE_RTT = 1, ///< Round-trip time based estimation (RTT) + // SL_RTL_ABR_CS_MODE_RTP_RTT = 2, ///< Combination of RTP and RTT + SL_RTL_ABR_CS_MODE_LAST ///< Placeholder +}; + +// ABR tone quality. Currently only entered for RTP +enum sl_rtl_abr_tone_quality{ + SL_RTL_ABR_TONE_QUALITY_GOOD = 0, + SL_RTL_ABR_TONE_QUALITY_MEDIUM = 1, + SL_RTL_ABR_TONE_QUALITY_LOW = 2, + SL_RTL_ABR_TONE_QUALITY_UNAVAILABLE = 3 +}; + +// RTT +// Note: rssi_d1, rssi_d2, time_d1 and time_d2 are required to be from the same channels and in the same channel order. +typedef struct { + uint32_t num_time_stamps; ///< Number of frequencies, 0xFFFFFFFF or 0 if invalid. In case of invalid input, the previously estimated distance shall be returned. + int32_t* rssi_d1; ///< Array of RSSI values from device 1, enter INVALID_RSSI_VALUE for any unavailable RSSI measurement + int32_t* rssi_d2; ///< Array of RSSI values from device 2, enter INVALID_RSSI_VALUE for any unavailable RSSI measurement + int32_t* time_d1; ///< Array of time measurements from device 1, enter INVALID_TIME_VALUE for any unavailable time measurement + int32_t* time_d2; ///< Array of time measurements from device 2, enter INVALID_TIME_VALUE for any unavailable time measurement +} sl_rtl_abr_rtt_data; + +// RTP +typedef struct { + uint32_t num_tones; ///< Number of tones (frequencies), including advertisement channels. Advertisement channels should be marked as blank tones, but included into total number of tones. Max value and currently the only supported value is 79. 80 num_tones is accepted as well, but internally it is converted to 79. + float tones_frequency_delta_hz; ///< Frequency delta, Hz. Accepted value is 1 MHz for 79 tones configuration. +} sl_rtl_abr_parameters; + +typedef struct { + uint32_t* blank_tone_indices; ///< Tones that shall be ignored when making a distance estimation + uint32_t num_blank_tone_indices; + enum sl_rtl_abr_tone_quality* tone_qualities_d1; ///< num_tones elements, null ptr means not used + enum sl_rtl_abr_tone_quality* tone_qualities_d2; ///< num_tones elements, null ptr means not used + float* i_samples_d1; ///< Array of device 1 I components, enter INVALID_PCT_VALUE for any unavailable PCT measurement + float* q_samples_d1; ///< Array of device 1 Q components, enter INVALID_PCT_VALUE for any unavailable PCT measurement + float* i_samples_d2; ///< Array of device 2 I components, enter INVALID_PCT_VALUE for any unavailable PCT measurement + float* q_samples_d2; ///< Array of device 2 Q components, enter INVALID_PCT_VALUE for any unavailable PCT measurement + // sl_rtl_abr_doppler_params* doppler_params; ///< Support for the Doppler parameters to be added in future +} sl_rtl_abr_rtp_data; + +/// ABR library item +typedef void* sl_rtl_abr_libitem; + +/**************************************************************************//** + * Initialize the ABR libitem instance. + * + * @param[in] item Pointer to the libitem to be initialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_init(sl_rtl_abr_libitem* item); + +/**************************************************************************//** + * Deinitialize a libitem instance of the ABR estimator. + * + * @param[in] item Pointer to the libitem to be deinitialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_deinit(sl_rtl_abr_libitem* item); + +/**************************************************************************//** + * Set the estimation mode. + * + * @param[in] item Pointer to the initialized ABR libitem + * @param[in] mode Estimator mode as ::sl_rtl_abr_algo_mode + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Set the estimation mode. For example, ::SL_RTL_ABR_ALGO_MODE_BASIC sets medium + * filtering. For further description of the modes, see the documentation + * of ::sl_rtl_abr_algo_mode. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_set_algo_mode(sl_rtl_abr_libitem* item, enum sl_rtl_abr_algo_mode mode); + +/**************************************************************************//** + * Set the estimation cs_mode. + * + * @param[in] item Pointer to the initialized ABR libitem + * @param[in] mode cs_mode as ::sl_rtl_abr_cs_mode + * @return ::SL_RTL_ERROR_SUCCESS if successful + * + * Set the desired cs_mode. For example, ::SL_RTL_ABR_CS_MODE_RTP uses round-trip + * phase based cs_mode. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_set_cs_mode(sl_rtl_abr_libitem* item, enum sl_rtl_abr_cs_mode cs_mode); + +/**************************************************************************//** + * Set parameters for estimation. Must be called before sl_rtl_abr_create_estimator. + * + * @param[in] item Pointer to the initialized ABR libitem + * @param[in] parameters Data structure with CS initialisation parameters for the estimator + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_set_parameters(sl_rtl_abr_libitem* item, sl_rtl_abr_parameters* parameters); + +/**************************************************************************//** + * Create the estimator after initializing the libitem and setting parameters. + * + * @param[in] item Pointer to the initialized and configured ABR libitem + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_create_estimator(sl_rtl_abr_libitem* item); + +/* NARROWBAND PHASE BASED DISTANCE ESTIMATION */ + +/**************************************************************************//** + * Calculate distance estimate based on RTP. + * + * @param[in] item Pointer to the initialized and configured ABR libitem + * @param[in] rtp_data Data structure with the RTP measurement data + * @return ::SL_RTL_ERROR_SUCCESS if successful and + * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final + * and more input data needs to be processed. + * + * Calculate the distance estimate from the given I/Q samples captured at the + * given frequencies. Use sl_rtl_abr_get_distance to fetch the latest distance + * estimate. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_process_rtp(sl_rtl_abr_libitem* item, sl_rtl_abr_rtp_data* rtp_data); + +/**************************************************************************//** + * Calculate distance estimate based on RTT. + * + * @param[in] item Pointer to the initialized and configured ABR libitem + * @param[in] rtt_data Data structure with the RTT measurement data + * @return ::SL_RTL_ERROR_SUCCESS if successful and + * ::SL_RTL_ERROR_ESTIMATION_IN_PROGRESS if estimate is not yet final + * and more input data needs to be processed. + * + * Calculate the distance estimate from the given device time samples. + * Use sl_rtl_abr_get_distance to fetch the latest distance + * estimate. + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_process_rtt(sl_rtl_abr_libitem* item, sl_rtl_abr_rtt_data* rtt_data); + +/* DISTANCE ESTIMATION COMMON*/ + +/**************************************************************************//** + * Get likeliness of the distance estimate. + * + * @param[in] item Pointer to the initialized ABR libitem + * @param[out] distance Distance out in meters. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_get_distance(sl_rtl_abr_libitem* item, float* distance); + +/**************************************************************************//** + * Get distance estimate. + * + * @param[in] item Pointer to the initialized ABR libitem + * @param[out] distance_likeliness Likeliness between 0.0 - 1.0 (unlikely - likely) of the estimated distance + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_abr_get_distance_likeliness(sl_rtl_abr_libitem* item, float* distance_likeliness); + +/** @} */ // end addtogroup sl_rtl_abr + +/** + * @addtogroup sl_rtl_loc Location Finding + * @{ + * + * @brief Location Finding + * + * These functions are related to the calculation of positions from angles + * and distances. + */ + +#define SL_RTL_LOC_ALL_LOCATORS (uint32_t)(-1) +#define SL_RTL_LOC_ALL_TAGS INT32_MAX + +/// Locator-specific measurements +enum sl_rtl_loc_locator_measurement_field{ + SL_RTL_LOC_LOCATOR_MEASUREMENT_AZIMUTH, ///< Measured azimuth from locator to tag + SL_RTL_LOC_LOCATOR_MEASUREMENT_ELEVATION, ///< Measured elevation from locator to tag + SL_RTL_LOC_LOCATOR_MEASUREMENT_DISTANCE, ///< Measured distance from locator to tag + + SL_RTL_LOC_LOCATOR_MEASUREMENT_AZIMUTH_DEVIATION, ///< Azimuth stdev + SL_RTL_LOC_LOCATOR_MEASUREMENT_ELEVATION_DEVIATION, ///< Elevation stdev + SL_RTL_LOC_LOCATOR_MEASUREMENT_DISTANCE_DEVIATION, ///< Distance stdev + + SL_RTL_LOC_LOCATOR_LAST +}; + +/// Target-specific measurements - Not yet supported +enum sl_rtl_loc_target_measurement_field{ + SL_RTL_LOC_TARGET_MEASUREMENT_LAST +}; + +/// Estimation mode +enum sl_rtl_loc_estimation_mode{ + SL_RTL_LOC_ESTIMATION_MODE_TWO_DIM_FAST_RESPONSE, ///< Two-dimensional mode - Only X and Y plane considered, less filtered mode for fast moving assests + SL_RTL_LOC_ESTIMATION_MODE_THREE_DIM_FAST_RESPONSE, ///< Three-dimensional mode - Covers X, Y and Z planes, less filtered mode for fast moving assests + + SL_RTL_LOC_ESTIMATION_MODE_TWO_DIM_HIGH_ACCURACY, ///< Two-dimensional mode - Only X and Y plane considered, more filtered mode for relatively static assets + SL_RTL_LOC_ESTIMATION_MODE_THREE_DIM_HIGH_ACCURACY, ///< Three-dimensional mode - Covers X, Y and Z planes, more filtered mode for relatively static assets + + SL_RTL_LOC_ESTIMATION_MODE_LAST +}; + +/// Measurement validation method +enum sl_rtl_loc_measurement_validation_method{ + SL_RTL_LOC_MEASUREMENT_VALIDATION_MINIMUM, ///< Only the basic validation integrated in the locationing algorithm (default) + SL_RTL_LOC_MEASUREMENT_VALIDATION_MEDIUM, ///< May discard the most inaccurate measurements with an additional calculation round + SL_RTL_LOC_MEASUREMENT_VALIDATION_FULL, ///< May discard the most inaccurate measurements with several calculation rounds +}; + +/// Locator-specific parameters related to locationing +enum sl_rtl_loc_locator_parameter { + SL_RTL_LOC_LOCATOR_PARAMETER_X_COORDINATE, ///< Set X-axis coordinate of the locator + SL_RTL_LOC_LOCATOR_PARAMETER_Y_COORDINATE, ///< Set Y-axis coordinate of the locator + SL_RTL_LOC_LOCATOR_PARAMETER_Z_COORDINATE, ///< Set Z-axis coordinate of the locator + SL_RTL_LOC_LOCATOR_PARAMETER_X_ORIENTATION, ///< Set X-axis rotation of the locator (Euler angles) in degrees + SL_RTL_LOC_LOCATOR_PARAMETER_Y_ORIENTATION, ///< Set Y-axis rotation of the locator (Euler angles) in degrees + SL_RTL_LOC_LOCATOR_PARAMETER_Z_ORIENTATION, ///< Set Z-axis rotation of the locator (Euler angles) in degrees + + SL_RTL_LOC_LOCATOR_PARAMETER_LAST +}; + +enum sl_rtl_loc_default_accuracy_parameter { + SL_RTL_LOC_DEFAULT_AZIMUTH_STDEV, ///< Set the default azimuth stdev + SL_RTL_LOC_DEFAULT_ELEVATION_STDEV, ///< Set the default elevation stdev + SL_RTL_LOC_DEFAULT_MINIMUM_DISTANCE_STDEV, ///< Set the default minimum distance stdev, will be added to the effective stdev value + SL_RTL_LOC_DEFAULT_DISTANCE_STDEV_COEFF, ///< Set the default distance stdev coeff, will be added after multiplied with the distance measurement to the effective stdev value +}; + +/// Target-specific parameters related to locationing +enum sl_rtl_loc_target_parameter{ + SL_RTL_LOC_TARGET_PARAMETER_TARGET_HEIGHT, // Z-position when the target is statically on some x-y-plane + SL_RTL_LOC_TARGET_CLEAR_TARGET_HEIGHT, // Clear the previously set Z-position + + SL_RTL_LOC_TARGET_PARAMETER_LAST +}; + +/// Locationing state results +enum sl_rtl_loc_result{ + SL_RTL_LOC_RESULT_POSITION_X = 0, ///< Estimated X-axis position of the target + SL_RTL_LOC_RESULT_POSITION_Y, ///< Estimated Y-axis position of the target + SL_RTL_LOC_RESULT_POSITION_Z, ///< Estimated Z-axis position of the target + + SL_RTL_LOC_RESULT_POSITION_RADIUS, ///< The combined radius (stdev) of the location estimate + SL_RTL_LOC_RESULT_POSITION_STDEV_X, ///< The accuracy (stdev) of the location x-coordinate estimate + SL_RTL_LOC_RESULT_POSITION_STDEV_Y, ///< The accuracy (stdev) of the location y-coordinate estimate + SL_RTL_LOC_RESULT_POSITION_STDEV_Z, ///< The accuracy (stdev) of the location z-coordinate estimate + + SL_RTL_LOC_RESULT_POSITION_VELOCITY_X, ///< Estimated X-axis velocity of the target + SL_RTL_LOC_RESULT_POSITION_VELOCITY_Y, ///< Estimated Y-axis velocity of the target + SL_RTL_LOC_RESULT_POSITION_VELOCITY_Z, ///< Estimated Z-axis velocity of the target + SL_RTL_LOC_RESULT_POSITION_ACCELERATION_X, ///< Estimated X-axis acceleration of the target + SL_RTL_LOC_RESULT_POSITION_ACCELERATION_Y, ///< Estimated Y-axis acceleration of the target + SL_RTL_LOC_RESULT_POSITION_ACCELERATION_Z, ///< Estimated Z-axis acceleration of the target + + SL_RTL_LOC_RESULT_LAST ///< Number of results +}; + +/// Locator item which contains the position and orientation of the locator array +struct sl_rtl_loc_locator_item{ + float coordinate_x; ///< X-axis coordinate of the locator + float coordinate_y; ///< Y-axis coordinate of the locator + float coordinate_z; ///< Z-axis coordinate of the locator + float orientation_x_axis_degrees; ///< X-axis rotation of the locator (Euler angles) in degrees + float orientation_y_axis_degrees; ///< Y-axis rotation of the locator (Euler angles) in degrees + float orientation_z_axis_degrees; ///< Z-axis rotation of the locator (Euler angles) in degrees +}; + +/// Locationing library item +typedef void* sl_rtl_loc_libitem; + +// Initialization functions + +/**************************************************************************//** + * Initialize the locationing libitem instance. + * + * @param[in] item Pointer to the libitem to be initialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_init(sl_rtl_loc_libitem* item); + +/**************************************************************************//** + * Deinitialize the locationing libitem instance. + * + * @param[in] item Pointer to the libitem to be initialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_deinit(sl_rtl_loc_libitem* item); + +/**************************************************************************//** + * Reinitialize the locationing libitem instance. + * + * Reset the libitem's internal values to the starting point so that it can + * start all over from the beginning. This can be used, for example, in testing + * instead of deleting and re-creating the libitem object. + * + * @param[in] item Pointer to the libitem to be initialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_reinit(sl_rtl_loc_libitem* item); + +/**************************************************************************//** + * Set the locationing dimensionality mode. Possible choices are 2D or 3D + * modes. Two-dimensional mode does not vary the z-position of the target and + * assumes it is 0 at all times. When updating, for example, the distance measure- + * ment from the locator to the target in 2D mode, it should be noted that + * even if the locator and tag are on different z-planes, the distance should + * be given as the distance as if they were on the same z-plane. + * + * @param[in] item Pointer to the libitem + * @param[in] mode Estimation mode as enum + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_mode(sl_rtl_loc_libitem* item, enum sl_rtl_loc_estimation_mode mode); + +/**************************************************************************//** + * Set the measurement validation method. If not given, the minimum method is + * used. Possible choices are minimum, medium, and full. The minimum does not + * increase the calculation CPU load because it is integrated inside the algorithm's + * normal operation. The medium and full methods use additionally one or + * multiple calculation rounds respectively and may discard the most + * inaccurate measurements from the calculation. However, they will always leave + * enough of them to calculate the estimate. + * + * @param[in] item Pointer to the libitem + * @param[in] method Validation method as enum + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_measurement_validation(sl_rtl_loc_libitem* item, enum sl_rtl_loc_measurement_validation_method method); + +/**************************************************************************//** + * Add a locator item into the locationing estimator after setting its position + * and orientation parameters. Add all locators using this + * function before calling ::sl_rtl_loc_create_position_estimator to create + * the estimator instance. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_item Locator item instance to be added + * @param[out] locator_id_out ID of the locator assigned by the library + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_add_locator(sl_rtl_loc_libitem* item, struct sl_rtl_loc_locator_item* locator_item, uint32_t* locator_id_out); + +/**************************************************************************//** + * Add an asset tag item into the locationing estimator. + * + * @param[in] item Pointer to the libitem + * @param[out] tag_id_out ID of the tag assigned by the library + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_add_tag(sl_rtl_loc_libitem* item, int32_t *tag_id_out); + +/**************************************************************************//** + * Remove an asset tag item previously added with sl_rtl_loc_add_tag. + * + * @param[in] item Pointer to the libitem + * @param[out] ID of the tag to be removed + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_remove_tag(sl_rtl_loc_libitem* item, int32_t tag_id); + +/**************************************************************************//** + * Create the position estimator instance after all locators have been added. + * + * @param[in] item Pointer to the libitem + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_create_position_estimator(sl_rtl_loc_libitem* item); + +// Processing functions + +/**************************************************************************//** + * Set locator-specific parameters, such as the azimuth and elevation + * measurement covariances. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator for which the parameter will be set + * @param[in] parameter Parameter to be set (as enum) + * @param[in] value New value for the parameter + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_locator_parameter(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_parameter parameter, float value); + +/**************************************************************************//** + * Set target-specific parameters, such as the known target height. + + * + * @param[in] item Pointer to the libitem + * @param[in] parameter Parameter to be set (as enum) + * @param[in] value New value for the parameter + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_target_parameter(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_parameter parameter, float value); + +/**************************************************************************//** + * Set target-specific parameters, such as the known target height for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] parameter Parameter to be set (as enum) + * @param[in] value New value for the parameter + * @param[in] tag_id TagID of the asset to be changed or ::SL_RTL_LOC_ALL_TAGS + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_target_parameter_tag(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_parameter parameter, float value, int32_t tag_id); + +/**************************************************************************//** + * Clear previous measurements. Call this function before setting + * new measurements if the previous measurements are not valid for the next + * iteration step. + * + * @param[in] item Pointer to the libitem + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_clear_measurements(sl_rtl_loc_libitem* item); + +/**************************************************************************//** + * Clear previous measurements for a specified tag. Call this function before setting + * new measurements if the previous measurements are not valid for the next + * iteration step. + * + * @param[in] item Pointer to the libitem + * @param[in] tag_id TagID of the asset to be changed or ::SL_RTL_LOC_ALL_TAGS + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_clear_measurements_tag(sl_rtl_loc_libitem* item, int32_t tag_id); + +/**************************************************************************//** + * Set a new measurement for a locator specified by the locator ID. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator for which the measurement will be set + * @param[in] field Measurement to be updated (as enum) + * @param[in] value New value for the measurement + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_locator_measurement(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float value); + +/**************************************************************************//** + * Set a new measurement for a locator specified by the locator ID for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator for which the measurement will be set + * @param[in] field Measurement to be updated (as enum) + * @param[in] value New value for the measurement + * @param[in] tag_id TagID of the asset to be changed + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_locator_measurement_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float value, int32_t tag_id); + +/**************************************************************************//** + * Set a new measurement for the target. Because the current version does not support this + * function, calling it has no effect. + * + * @param[in] item Pointer to the libitem + * @param[in] field Measurement to be updated (as enum) + * @param[in] value New value for the measurement + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_target_measurement(sl_rtl_loc_libitem* item, enum sl_rtl_loc_target_measurement_field field, float value); + +/**************************************************************************//** + * Set the default accuracy value for direction / distance. + * This value will be used if not given explicitly by measurement. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose parameter will be set + * @param[in] parm Parameter to be set (as enum) + * @param[in] value New value for the default accuracy + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_set_default_accuracy(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_default_accuracy_parameter param, float value); + +/**************************************************************************//** + * Process the current time step of the locationing filter. Call this function + * after old measurements are cleared and new + * measurements are set for the current time step. The process will step + * the filter forward and provide new state results and state covariance + * values, which can be retrieved with separate function calls. + * + * @param[in] item Pointer to the libitem + * @param[in] time_step Process time interval in seconds. This is the time + * separation between the previous step and this current step. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_process(sl_rtl_loc_libitem* item, float time_step); + +/**************************************************************************//** + * Process the current time step of the locationing filter for a specified tag. + * Call this function after old measurements are cleared and new + * measurements are set for the current time step. The process will step + * the filter forward and provide new state results and state covariance + * values, which can be retrieved with separate function calls. + * + * @param[in] item Pointer to the libitem + * @param[in] time_step Process time interval in seconds. This is the time + * separation between the previous step and this current step. + * @param[in] tag_id TagID of the asset to be processed or ::SL_RTL_LOC_ALL_TAGS + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_process_tag(sl_rtl_loc_libitem* item, float time_step, int32_t tag_id); + +/**************************************************************************//** + * Get result of the current state variables or state covariances. + * + * @param[in] item Pointer to the libitem + * @param[in] result The desired state variable result as enum + * @param[out] value The value output of the state variable + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_result(sl_rtl_loc_libitem* item, enum sl_rtl_loc_result result, float* value); + +/**************************************************************************//** + * Get result of the current state variables or state covariances for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] result The desired state variable result as enum + * @param[out] value The value output of the state variable + * @param[in] tag_id TagID of the asset to fetch the results for + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_result_tag(sl_rtl_loc_libitem* item, enum sl_rtl_loc_result result, float* value, int32_t tag_id); + +/**************************************************************************//** + * Get the latest measurement converted into the coordinate system of the + * multi-locator system. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[in] field Measurement to be retrieved (as enum) + * @param[out] value_out The value output of the state variable + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_measurement_in_system_coordinates(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float* value_out); + +/**************************************************************************//** + * Get the latest measurement converted into the coordinate system of the + * multi-locator system for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[in] field Measurement to be retrieved (as enum) + * @param[out] value_out The value output of the state variable + * @param[in] tag_id TagID of the asset + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_measurement_in_system_coordinates_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, enum sl_rtl_loc_locator_measurement_field field, float* value_out, int32_t tag_id); + +/**************************************************************************//** + * Get the expected direction of the asset for the locator. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[out] azimuth The expected azimuth value + * @param[out] elevation The expected elevation value + * @param[out] distance The expected distance value + * @return ::SL_RTL_ERROR_SUCCESS if the locator does not require correction + * @return ::SL_RTL_ERROR_INCORRECT_MEASUREMENT if the locator's previous measurement was ignored because the error is too large + * @returns Another error code in case of error + * + * Position calculation has a better overall view to the asset's location than + * any individual locator. If the direction angles differ too much from + * the expected direction, the locator can be instructed to correct its + * internal state so that in can recover from this incorrectness faster. + * See also sl_rtl_aox_set_expected_direction() + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_expected_direction(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance); + +/**************************************************************************//** + * Get the expected direction of the asset for the locator for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[out] azimuth The expected azimuth value + * @param[out] elevation The expected elevation value + * @param[out] distance The expected distance value + * @param[in] tag_id TagID of the asset + * @return ::SL_RTL_ERROR_SUCCESS if the locator does not require correction + * @return ::SL_RTL_ERROR_INCORRECT_MEASUREMENT if the locator's previous measurement was ignored because of too large error + * @returns Another error code in case of error + * + * Position calculation has a better overall view to the asset's location than + * any individual locator. If the direction angles differ too much from + * the expected direction, the locator can be instructed to correct its + * internal state so that in can recover from this incorrectness faster. + * See also sl_rtl_aox_set_expected_direction(). + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_expected_direction_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance, int32_t tag_id); + +/**************************************************************************//** + * Get the deviation values for expected direction of the asset for the locator. + * + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[out] azimuth The expected azimuth value's standard deviation + * @param[out] elevation The expected elevation value's standard deviation + * @param[in] item Pointer to the libitem + * @param[out] distance The expected distance value's standard deviation + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_expected_deviation(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance); + +/**************************************************************************//** + * Get the deviation values for expected direction of the asset for the locator + * for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator whose measurement will be retrieved + * @param[out] azimuth The expected azimuth value's standard deviation + * @param[out] elevation The expected elevation value's standard deviation + * @param[out] distance The expected distance value's standard deviation + * @param[in] tag_id TagID of the asset + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_get_expected_deviation_tag(sl_rtl_loc_libitem* item, uint32_t locator_id, float *azimuth, float *elevation, float *distance, int32_t tag_id); + +/**************************************************************************//** + * Get the number of locators, which are disabled from position calculation because + * the direction error is too large. + * + * @param[in] item Pointer to the libitem + * @returns Number of locators needing correction, or -1 in case of any other error + *****************************************************************************/ +int sl_rtl_loc_get_number_disabled(sl_rtl_loc_libitem* item); + +/**************************************************************************//** + * Get the number of locators, which are disabled from position calculation because + * the direction error is too large, for a specified tag. + * + * @param[in] item Pointer to the libitem + * @param[in] tag_id TagID of the asset + * @returns Number of locators needing correction, or -1 in case of any other error + *****************************************************************************/ +int sl_rtl_loc_get_number_disabled_tag(sl_rtl_loc_libitem* item, int32_t tag_id); + +/**************************************************************************//** + * Check if the asset is in reach of a given locator according to the + * position-based filtering. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of the locator to run the test + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +bool sl_rtl_loc_filter_in_reach(sl_rtl_loc_libitem* item, uint32_t locator_id); + +/**************************************************************************//** + * Clear all the position-based filters from a locator or from all + * locators. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_clear(sl_rtl_loc_libitem* item, uint32_t locator_id); + +/**************************************************************************//** + * Add a position-based filter. This filter is based on the distance from a locator. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] radius Distance from the locator + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_sphere(sl_rtl_loc_libitem* item, uint32_t locator_id, float radius, bool exclude_region); + +/**************************************************************************//** + * Add a position-based filter. The two dimensional filter is based on + * the distance from a locator. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] radius Distance from the locator + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_circle(sl_rtl_loc_libitem* item, uint32_t locator_id, float radius, bool exclude_region); + +/**************************************************************************//** + * Add a position-based filter. This filter defines relative distances in + * coordinate axes' directions. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] xDelta Maximum distance in X-coordinate direction + * @param[in] yDelta Maximum distance in Y-coordinate direction + * @param[in] zDelta Maximum distance in Z-coordinate direction + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_box(sl_rtl_loc_libitem* item, uint32_t locator_id, float xDelta, float yDelta, float zDelta, bool exclude_region); + +/**************************************************************************//** + * Add a position-based filter. This two dimensional filter defines relative + * distances in coordinate axes' directions. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] xDelta Maximum distance in X-coordinate direction + * @param[in] yDelta Maximum distance in Y-coordinate direction + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_rect(sl_rtl_loc_libitem* item, uint32_t locator_id, float xDelta, float yDelta, bool exclude_region); + +/**************************************************************************//** + * Add a position-based filter. This filter defines an area in global + * coordinates. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] minX Minimum X-coordinate value + * @param[in] maxX Maximum X-coordinate value + * @param[in] minY Minimum Y-coordinate value + * @param[in] maxY Maximum Y-coordinate value + * @param[in] minZ Minimum Z-coordinate value + * @param[in] maxZ Maximum Z-coordinate value + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_room(sl_rtl_loc_libitem* item, uint32_t locator_id, float minX, float maxX, float minY, float maxY, float minZ, float maxZ, bool exclude_region); + +/**************************************************************************//** + * Add a position-based filter. The two dimensional filter defines an area in + * global coordinates. + * The filter can be added to one locator or all locators. A locator may + * have several filters which are combined. + * + * @param[in] item Pointer to the libitem + * @param[in] locator_id ID of a single locator or ::SL_RTL_LOC_ALL_LOCATORS + * @param[in] minX Minimum X-coordinate value + * @param[in] maxX Maximum X-coordinate value + * @param[in] minY Minimum Y-coordinate value + * @param[in] maxY Maximum Y-coordinate value + * @param[in] exclude_region If true, define an excluded region instead + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_filter_floor(sl_rtl_loc_libitem* item, uint32_t locator_id, float minX, float maxX, float minY, float maxY, bool exclude_region); + +/**************************************************************************//** + * Enable trilateration method in location calculation. + * + * The trilateration method calculates the position based on the distances + * from the locators rather than the direction angles. This function enables + * the method, but the location calculation may still utilize also the + * directon if available to further increase the accuracy. + * + * Trilateration method is not turned on by default. + * + * @param[in] item Pointer to the libitem + * @param[in] value Turn the trilateration on or off + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_enable_trilateration(sl_rtl_loc_libitem* item, bool value); + +/**************************************************************************//** + * Prefer the asset location below or above the locator plane. + * + * If the locators are all in the same plane (or close to it), the height of + * the asset may become ambiguous. Set the preference to be below or above + * plane so that is more likely to end up in the correct position. + * + * The default options is below the plane. + * + * @param[in] item Pointer to the libitem + * @param[in] value Turn the trilateration on or off + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_loc_trilateration_prefer_below_plane(sl_rtl_loc_libitem* item, bool value); + +/** @} */ // end addtogroup sl_rtl_loc + +/** + * @addtogroup sl_rtl_util Utility Functionality + * @{ + * + * @brief Utility Functionality + * + * These functions provide supporting functionality such as conversions, + * additional filtering, diagnostics, and setup functions. + */ + +/// Utility library item +typedef void* sl_rtl_util_libitem; + +/// Util parameter +enum sl_rtl_util_parameter{ + SL_RTL_UTIL_PARAMETER_AMOUNT_OF_FILTERING = 0 ///< Amount of filtering in range [0.0f, 1.0f] +}; + +/**************************************************************************//** + * Initialize the Util libitem instance. + * + * @param[in] item Pointer to the libitem to be initialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_init(sl_rtl_util_libitem* item); + +/**************************************************************************//** + * Deinitialize a Util libitem instance. + * + * @param[in] item Pointer to the libitem to be deinitialized + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_deinit(sl_rtl_util_libitem* item); + +/**************************************************************************//** + * Set util parameters. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] parameter Parameter to change + * @param[in] value Value of the parameter + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_set_parameter(sl_rtl_util_libitem* item, enum sl_rtl_util_parameter parameter, float value); + +/**************************************************************************//** + * Filter a value using the moving average. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] value_in Value to be fed to the filter + * @param[out] value_out Pointer to the filtered value + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_filter(sl_rtl_util_libitem* item, float value_in, float* value_out); + +/**************************************************************************//** + * Convert an RSSI-value to distance in meters. + * + * @param[in] tx_power Reference RSSI value of the TX-device at 1.0 m distance in dBm, for example -45.0f + * @param[in] rssi Measured RSSI from the receiver + * @param[out] distance_out Distance in meters + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_rssi2distance(float tx_power, float rssi, float* distance_out); + +/**************************************************************************//** + * Set up the IQ sample quality analysis. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] level Analysis level + * @param[in] num_antennas The number of antennas in the array + * @param[in] raw_samples Data contains raw samples instead of picked ones + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_setup(sl_rtl_util_libitem *item, uint32_t level, uint32_t num_antennas, bool raw_samples); + +/**************************************************************************//** + * Set up parameters for the IQ sample quality analysis. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] sample_rate The sampling rate + * @param[in] sample_offset The offset for the picked sample in the sampling slot + * @param[in] samples_in_slot Number of samples in the sampling slot + * @param[in] number_of_channels Number of radio channels + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_parameters(sl_rtl_util_libitem* item, uint32_t sample_rate, uint8_t sample_offset, uint8_t samples_in_slot, uint8_t number_of_channels); + +/**************************************************************************//** + * Set up IQ sample QA downsampling ratio. + * + * Set the downsampling factor used during the antenna samples (related to the + * sampling rate of the reference period) + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] dsf The downsampling factor + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_downsampling_factor(sl_rtl_util_libitem* item, float dsf); + +/**************************************************************************//** + * Set data samples offset. + * + * Set the offset for the data samples from the start of the reference + * period. The use of this function is optional and, if not given, + * the default values are used. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] offset The data samples' offset + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_data_offset(sl_rtl_util_libitem* item, uint32_t offset); + +/**************************************************************************//** + * Set the switch pattern for the IQ sample quality. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] size The size of the switch pattern + * @param[in] pattern Array of integers representing the switch pattern + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_set_switch_pattern(sl_rtl_util_libitem* item, uint32_t size, uint32_t *pattern); + +/**************************************************************************//** + * Feed the IQ sample quality analysis the reference period data. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] num_samples The size of data + * @param[in] i_samples I-part of the sample data + * @param[in] q_samples Q-part of the sample data + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_add_reference(sl_rtl_util_libitem *item, uint32_t num_samples, float *i_samples, float *q_samples); +/**************************************************************************//** + * Feed the IQ sample quality analysis the antenna data. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] num_snapshots The size of the data + * @param[in] i_samples I-part of the sample data + * @param[in] q_samples Q-part of the sample data + * @param[in] channel Radio channel the packet is using. + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_add_data(sl_rtl_util_libitem *item, uint32_t num_snapshots, float **i_samples, float **q_samples, uint8_t channel); + +/**************************************************************************//** + * Get the overall results of the IQ sample quality analysis. + * + * @param[in] item Pointer to the initialized Util libitem + + * @return Bitmask of the failing tests, zero if everything passed + *****************************************************************************/ +uint32_t sl_rtl_util_iq_sample_qa_get_results(sl_rtl_util_libitem *item); + +/**************************************************************************//** + * Get the detailed results of the IQ sample quality analysis. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[out] iq_sample_qa_results The data structure with data related to the previous data packet + * @param[out] antenna_data The array of antenna-specific results + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_get_details(sl_rtl_util_libitem *item, sl_rtl_clib_iq_sample_qa_dataset_t *iq_sample_qa_results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); + +/**************************************************************************//** + * Get the detailed results of the IQ sample quality analysis for the specified radio channel. + * + * @param[in] item Pointer to the initialized Util libitem + * @param[in] channel Radio channel to show results for. + * @param[out] iq_sample_qa_results The data structure with data related to the last data packet using the requested channel + * @param[out] antenna_data The array of antenna specific results + * @return ::SL_RTL_ERROR_SUCCESS if successful + *****************************************************************************/ +enum sl_rtl_error_code sl_rtl_util_iq_sample_qa_get_channel_details(sl_rtl_util_libitem* item, uint8_t channel, sl_rtl_clib_iq_sample_qa_dataset_t *iq_sample_qa_results, sl_rtl_clib_iq_sample_qa_antenna_data_t *antenna_data); + +/**************************************************************************//** + * Write the IQ sample quality analysis code as human readable strings in the provided buffer. + * + * @param[in] buf Buffer for the results to be written + * @param[in] size Size of the buffer + * @param[in] code The results previously received from the sl_rtl_util_iq_sample_qa_get_results() + * @returns pointer to the buffer containing data, or to a constant string + *****************************************************************************/ +char *sl_rtl_util_iq_sample_qa_code2string(char *buf, int size, uint32_t code); + +/** @} */ // end addtogroup sl_rtl_util + #endif /*SL_RTL_CLIB_API_H*/ \ No newline at end of file diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/inc/iostream_printf.h b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/inc/iostream_printf.h index 7f94c4f..6dbc2ca 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/inc/iostream_printf.h +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/inc/iostream_printf.h @@ -1,67 +1,67 @@ -/***************************************************************************//** - * @file - * @brief IO Stream printf implementation - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef IOSTREAM_PRINTF_H -#define IOSTREAM_PRINTF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup service - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup IOSTREAM_PRINTF - * @{ - ******************************************************************************/ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * Print a formated string on stream. - * - * @param[in] stream IO Stream to be used: - * SL_IOSTREAM_STDOUT; Default output stream will be used. - * SL_IOSTREAM_STDERR; Default error output stream will be used. - * Pointer to specific stream; Specific stream will be used. - * - * - * @param[in] format String that contains the text to be written. - * - * @param[in] ... Additional arguments. - * - * @return The number of characters that are written into the array, not counting - * the terminating null character. - ******************************************************************************/ - -int sl_iostream_printf_to_stream(sl_iostream_t *stream, - const char *format, - ...); - -/** @} (end addtogroup IOSTREAM_PRINTF) */ -/** @} (end addtogroup service) */ - -#ifdef __cplusplus -} -#endif - -#endif /* IOSTREAM_PRINTF_H */ +/***************************************************************************//** + * @file + * @brief IO Stream printf implementation + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef IOSTREAM_PRINTF_H +#define IOSTREAM_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup service + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup IOSTREAM_PRINTF + * @{ + ******************************************************************************/ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Print a formated string on stream. + * + * @param[in] stream IO Stream to be used: + * SL_IOSTREAM_STDOUT; Default output stream will be used. + * SL_IOSTREAM_STDERR; Default error output stream will be used. + * Pointer to specific stream; Specific stream will be used. + * + * + * @param[in] format String that contains the text to be written. + * + * @param[in] ... Additional arguments. + * + * @return The number of characters that are written into the array, not counting + * the terminating null character. + ******************************************************************************/ + +int sl_iostream_printf_to_stream(sl_iostream_t *stream, + const char *format, + ...); + +/** @} (end addtogroup IOSTREAM_PRINTF) */ +/** @} (end addtogroup service) */ + +#ifdef __cplusplus +} +#endif + +#endif /* IOSTREAM_PRINTF_H */ diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.c b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.c index 9538a55..b030874 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.c +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.c @@ -1,943 +1,943 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. These routines are thread -// safe and reentrant! -// Use this instead of the bloated standard/newlib printf cause these use -// malloc for printf (and may not be thread safe). -// -/////////////////////////////////////////////////////////////////////////////// - -#include -#include - -#include "printf.h" - -// __copy__ attribute was introduced in GCC9 -#if defined(__GNUC__) && __GNUC__ >= 9 -#define __copy(symbol) __attribute__((__copy__(symbol))) -#else -#define __copy(symbol) -#endif - -// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the -// printf_config.h header file -// default: undefined -#ifdef PRINTF_INCLUDE_CONFIG_H -#include "printf_config.h" -#endif - - -// 'ntoa' conversion buffer size, this must be big enough to hold one converted -// numeric number including padded zeros (dynamically created on stack) -// default: 32 byte -#ifndef PRINTF_NTOA_BUFFER_SIZE -#define PRINTF_NTOA_BUFFER_SIZE 32U -#endif - -// 'ftoa' conversion buffer size, this must be big enough to hold one converted -// float number including padded zeros (dynamically created on stack) -// default: 32 byte -#ifndef PRINTF_FTOA_BUFFER_SIZE -#define PRINTF_FTOA_BUFFER_SIZE 32U -#endif - -// support for the floating point type (%f) -// default: activated -#ifndef PRINTF_DISABLE_SUPPORT_FLOAT -#define PRINTF_SUPPORT_FLOAT -#endif - -// support for exponential floating point notation (%e/%g) -// default: activated -#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL -#define PRINTF_SUPPORT_EXPONENTIAL -#endif - -// define the default floating point precision -// default: 6 digits -#ifndef PRINTF_DEFAULT_FLOAT_PRECISION -#define PRINTF_DEFAULT_FLOAT_PRECISION 6U -#endif - -// define the largest float suitable to print with %f -// default: 1e9 -#ifndef PRINTF_MAX_FLOAT -#define PRINTF_MAX_FLOAT 1e9 -#endif - -// support for the long long types (%llu or %p) -// default: activated -#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG -#define PRINTF_SUPPORT_LONG_LONG -#endif - -// support for the ptrdiff_t type (%t) -// ptrdiff_t is normally defined in as long or long long type -// default: activated -#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T -#define PRINTF_SUPPORT_PTRDIFF_T -#endif - -/////////////////////////////////////////////////////////////////////////////// - -// internal flag definitions -#define FLAGS_ZEROPAD (1U << 0U) -#define FLAGS_LEFT (1U << 1U) -#define FLAGS_PLUS (1U << 2U) -#define FLAGS_SPACE (1U << 3U) -#define FLAGS_HASH (1U << 4U) -#define FLAGS_UPPERCASE (1U << 5U) -#define FLAGS_CHAR (1U << 6U) -#define FLAGS_SHORT (1U << 7U) -#define FLAGS_LONG (1U << 8U) -#define FLAGS_LONG_LONG (1U << 9U) -#define FLAGS_PRECISION (1U << 10U) -#define FLAGS_ADAPT_EXP (1U << 11U) - - -// import float.h for DBL_MAX -#if defined(PRINTF_SUPPORT_FLOAT) -#include -#endif - - -// output function type -typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen); - - -// wrapper (used as buffer) for output function type -typedef struct { - void (*fct)(char character, void* arg); - void* arg; -} out_fct_wrap_type; - - -// internal buffer output -static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen) -{ - if (idx < maxlen) { - ((char*)buffer)[idx] = character; - } -} - - -// internal null output -static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)character; (void)buffer; (void)idx; (void)maxlen; -} - - -// internal _putchar wrapper -static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)buffer; (void)idx; (void)maxlen; - if (character) { - _putchar(character); - } -} - - -// internal output function wrapper -static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen) -{ - (void)idx; (void)maxlen; - if (character) { - // buffer is the output fct pointer - ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg); - } -} - - -// internal secure strlen -// \return The length of the string (excluding the terminating 0) limited by 'maxsize' -static inline unsigned int _strnlen_s(const char* str, size_t maxsize) -{ - const char* s; - for (s = str; *s && maxsize--; ++s); - return (unsigned int)(s - str); -} - - -// internal test if char is a digit (0-9) -// \return true if char is a digit -static inline bool _is_digit(char ch) -{ - return (ch >= '0') && (ch <= '9'); -} - - -// internal ASCII string to unsigned int conversion -static unsigned int _atoi(const char** str) -{ - unsigned int i = 0U; - while (_is_digit(**str)) { - i = i * 10U + (unsigned int)(*((*str)++) - '0'); - } - return i; -} - - -// output the specified string in reverse, taking care of any zero-padding -static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags) -{ - const size_t start_idx = idx; - - // pad spaces up to given width - if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { - for (size_t i = len; i < width; i++) { - out(' ', buffer, idx++, maxlen); - } - } - - // reverse string - while (len) { - out(buf[--len], buffer, idx++, maxlen); - } - - // append pad spaces up to given width - if (flags & FLAGS_LEFT) { - while (idx - start_idx < width) { - out(' ', buffer, idx++, maxlen); - } - } - - return idx; -} - - -// internal itoa format -static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) -{ - // pad leading zeros - if (!(flags & FLAGS_LEFT)) { - if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { - width--; - } - while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - } - - // handle hash - if (flags & FLAGS_HASH) { - if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { - len--; - if (len && (base == 16U)) { - len--; - } - } - if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'x'; - } - else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'X'; - } - else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { - buf[len++] = 'b'; - } - if (len < PRINTF_NTOA_BUFFER_SIZE) { - buf[len++] = '0'; - } - } - - if (len < PRINTF_NTOA_BUFFER_SIZE) { - if (negative) { - buf[len++] = '-'; - } - else if (flags & FLAGS_PLUS) { - buf[len++] = '+'; // ignore the space if the '+' exists - } - else if (flags & FLAGS_SPACE) { - buf[len++] = ' '; - } - } - - return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -} - - -// internal itoa for 'long' type -static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) -{ - char buf[PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - do { - const char digit = (char)(value % base); - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - value /= base; - } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); -} - - -// internal itoa for 'long long' type -#if defined(PRINTF_SUPPORT_LONG_LONG) -static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) -{ - char buf[PRINTF_NTOA_BUFFER_SIZE]; - size_t len = 0U; - - // no hash for 0 values - if (!value) { - flags &= ~FLAGS_HASH; - } - - // write if precision != 0 and value is != 0 - if (!(flags & FLAGS_PRECISION) || value) { - do { - const char digit = (char)(value % base); - buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; - value /= base; - } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); - } - - return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); -} -#endif // PRINTF_SUPPORT_LONG_LONG - - -#if defined(PRINTF_SUPPORT_FLOAT) - -#if defined(PRINTF_SUPPORT_EXPONENTIAL) -// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT -static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags); -#endif - - -// internal ftoa for fixed decimal floating point -static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) -{ - char buf[PRINTF_FTOA_BUFFER_SIZE]; - size_t len = 0U; - double diff = 0.0; - - // powers of 10 - static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 }; - - // test for special values - if (value != value) - return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); - if (value < -DBL_MAX) - return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); - if (value > DBL_MAX) - return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags); - - // test for very large values - // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad - if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) { -#if defined(PRINTF_SUPPORT_EXPONENTIAL) - return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); -#else - return 0U; -#endif - } - - // test for negative - bool negative = false; - if (value < 0) { - negative = true; - value = 0 - value; - } - - // set default precision, if not set explicitly - if (!(flags & FLAGS_PRECISION)) { - prec = PRINTF_DEFAULT_FLOAT_PRECISION; - } - // limit precision to 9, cause a prec >= 10 can lead to overflow errors - while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { - buf[len++] = '0'; - prec--; - } - - int whole = (int)value; - double tmp = (value - whole) * pow10[prec]; - unsigned long frac = (unsigned long)tmp; - diff = tmp - frac; - - if (diff > 0.5) { - ++frac; - // handle rollover, e.g. case 0.99 with prec 1 is 1.0 - if (frac >= pow10[prec]) { - frac = 0; - ++whole; - } - } - else if (diff < 0.5) { - } - else if ((frac == 0U) || (frac & 1U)) { - // if halfway, round up if odd OR if last digit is 0 - ++frac; - } - - if (prec == 0U) { - diff = value - (double)whole; - if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { - // exactly 0.5 and ODD, then round up - // 1.5 -> 2, but 2.5 -> 2 - ++whole; - } - } - else { - unsigned int count = prec; - // now do fractional part, as an unsigned number - while (len < PRINTF_FTOA_BUFFER_SIZE) { - --count; - buf[len++] = (char)(48U + (frac % 10U)); - if (!(frac /= 10U)) { - break; - } - } - // add extra 0s - while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { - buf[len++] = '0'; - } - if (len < PRINTF_FTOA_BUFFER_SIZE) { - // add decimal - buf[len++] = '.'; - } - } - - // do whole part, number is reversed - while (len < PRINTF_FTOA_BUFFER_SIZE) { - buf[len++] = (char)(48 + (whole % 10)); - if (!(whole /= 10)) { - break; - } - } - - // pad leading zeros - if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { - if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { - width--; - } - while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) { - buf[len++] = '0'; - } - } - - if (len < PRINTF_FTOA_BUFFER_SIZE) { - if (negative) { - buf[len++] = '-'; - } - else if (flags & FLAGS_PLUS) { - buf[len++] = '+'; // ignore the space if the '+' exists - } - else if (flags & FLAGS_SPACE) { - buf[len++] = ' '; - } - } - - return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); -} - - -#if defined(PRINTF_SUPPORT_EXPONENTIAL) -// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse -static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) -{ - // check for NaN and special values - if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) { - return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); - } - - // determine the sign - const bool negative = value < 0; - if (negative) { - value = -value; - } - - // default precision - if (!(flags & FLAGS_PRECISION)) { - prec = PRINTF_DEFAULT_FLOAT_PRECISION; - } - - // determine the decimal exponent - // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) - union { - uint64_t U; - double F; - } conv; - - conv.F = value; - int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 - conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) - // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 - int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); - // now we want to compute 10^expval but we want to be sure it won't overflow - exp2 = (int)(expval * 3.321928094887362 + 0.5); - const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; - const double z2 = z * z; - conv.U = (uint64_t)(exp2 + 1023) << 52U; - // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex - conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); - // correct for rounding errors - if (value < conv.F) { - expval--; - conv.F /= 10; - } - - // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters - unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; - - // in "%g" mode, "prec" is the number of *significant figures* not decimals - if (flags & FLAGS_ADAPT_EXP) { - // do we want to fall-back to "%f" mode? - if ((value >= 1e-4) && (value < 1e6)) { - if ((int)prec > expval) { - prec = (unsigned)((int)prec - expval - 1); - } - else { - prec = 0; - } - flags |= FLAGS_PRECISION; // make sure _ftoa respects precision - // no characters in exponent - minwidth = 0U; - expval = 0; - } - else { - // we use one sigfig for the whole part - if ((prec > 0) && (flags & FLAGS_PRECISION)) { - --prec; - } - } - } - - // will everything fit? - unsigned int fwidth = width; - if (width > minwidth) { - // we didn't fall-back so subtract the characters required for the exponent - fwidth -= minwidth; - } else { - // not enough characters, so go back to default sizing - fwidth = 0U; - } - if ((flags & FLAGS_LEFT) && minwidth) { - // if we're padding on the right, DON'T pad the floating part - fwidth = 0U; - } - - // rescale the float value - if (expval) { - value /= conv.F; - } - - // output the floating part - const size_t start_idx = idx; - idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); - - // output the exponent part - if (minwidth) { - // output the exponential symbol - out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); - // output the exponent value - idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS); - // might need to right-pad spaces - if (flags & FLAGS_LEFT) { - while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); - } - } - return idx; -} -#endif // PRINTF_SUPPORT_EXPONENTIAL -#endif // PRINTF_SUPPORT_FLOAT - - -// internal vsnprintf -static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va) -{ - unsigned int flags, width, precision, n; - size_t idx = 0U; - - if (!buffer) { - // use null output function - out = _out_null; - } - - while (*format) - { - // format specifier? %[flags][width][.precision][length] - if (*format != '%') { - // no - out(*format, buffer, idx++, maxlen); - format++; - continue; - } - else { - // yes, evaluate it - format++; - } - - // evaluate flags - flags = 0U; - do { - switch (*format) { - case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; - case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; - case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; - case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; - case '#': flags |= FLAGS_HASH; format++; n = 1U; break; - default : n = 0U; break; - } - } while (n); - - // evaluate width field - width = 0U; - if (_is_digit(*format)) { - width = _atoi(&format); - } - else if (*format == '*') { - const int w = va_arg(va, int); - if (w < 0) { - flags |= FLAGS_LEFT; // reverse padding - width = (unsigned int)-w; - } - else { - width = (unsigned int)w; - } - format++; - } - - // evaluate precision field - precision = 0U; - if (*format == '.') { - flags |= FLAGS_PRECISION; - format++; - if (_is_digit(*format)) { - precision = _atoi(&format); - } - else if (*format == '*') { - const int prec = (int)va_arg(va, int); - precision = prec > 0 ? (unsigned int)prec : 0U; - format++; - } - } - - // evaluate length field - switch (*format) { - case 'l' : - flags |= FLAGS_LONG; - format++; - if (*format == 'l') { - flags |= FLAGS_LONG_LONG; - format++; - } - break; - case 'h' : - flags |= FLAGS_SHORT; - format++; - if (*format == 'h') { - flags |= FLAGS_CHAR; - format++; - } - break; -#if defined(PRINTF_SUPPORT_PTRDIFF_T) - case 't' : - flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; -#endif - case 'j' : - flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - case 'z' : - flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); - format++; - break; - default : - break; - } - - // evaluate specifier - switch (*format) { - case 'd' : - case 'i' : - case 'u' : - case 'x' : - case 'X' : - case 'o' : - case 'b' : { - // set the base - unsigned int base; - if (*format == 'x' || *format == 'X') { - base = 16U; - } - else if (*format == 'o') { - base = 8U; - } - else if (*format == 'b') { - base = 2U; - } - else { - base = 10U; - flags &= ~FLAGS_HASH; // no hash for dec format - } - // uppercase - if (*format == 'X') { - flags |= FLAGS_UPPERCASE; - } - - // no plus or space flag for u, x, X, o, b - if ((*format != 'i') && (*format != 'd')) { - flags &= ~(FLAGS_PLUS | FLAGS_SPACE); - } - - // ignore '0' flag when precision is given - if (flags & FLAGS_PRECISION) { - flags &= ~FLAGS_ZEROPAD; - } - - // convert the integer - if ((*format == 'i') || (*format == 'd')) { - // signed - if (flags & FLAGS_LONG_LONG) { -#if defined(PRINTF_SUPPORT_LONG_LONG) - const long long value = va_arg(va, long long); - idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); -#endif - } - else if (flags & FLAGS_LONG) { - const long value = va_arg(va, long); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); - } - else { - const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int); - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); - } - } - else { - // unsigned - if (flags & FLAGS_LONG_LONG) { -#if defined(PRINTF_SUPPORT_LONG_LONG) - idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); -#endif - } - else if (flags & FLAGS_LONG) { - idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); - } - else { - const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); - idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); - } - } - format++; - break; - } -#if defined(PRINTF_SUPPORT_FLOAT) - case 'f' : - case 'F' : - if (*format == 'F') flags |= FLAGS_UPPERCASE; - idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); - format++; - break; -#if defined(PRINTF_SUPPORT_EXPONENTIAL) - case 'e': - case 'E': - case 'g': - case 'G': - if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP; - if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; - idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); - format++; - break; -#endif // PRINTF_SUPPORT_EXPONENTIAL -#endif // PRINTF_SUPPORT_FLOAT - case 'c' : { - unsigned int l = 1U; - // pre padding - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // char output - out((char)va_arg(va, int), buffer, idx++, maxlen); - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 's' : { - const char* p = va_arg(va, char*); - unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1); - // pre padding - if (flags & FLAGS_PRECISION) { - l = (l < precision ? l : precision); - } - if (!(flags & FLAGS_LEFT)) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - // string output - while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { - out(*(p++), buffer, idx++, maxlen); - } - // post padding - if (flags & FLAGS_LEFT) { - while (l++ < width) { - out(' ', buffer, idx++, maxlen); - } - } - format++; - break; - } - - case 'p' : { - width = sizeof(void*) * 2U; - flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; -#if defined(PRINTF_SUPPORT_LONG_LONG) - const bool is_ll = sizeof(uintptr_t) == sizeof(long long); - if (is_ll) { - idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags); - } - else { -#endif - idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags); -#if defined(PRINTF_SUPPORT_LONG_LONG) - } -#endif - format++; - break; - } - - case '%' : - out('%', buffer, idx++, maxlen); - format++; - break; - - default : - out(*format, buffer, idx++, maxlen); - format++; - break; - } - } - - // termination - out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); - - // return written chars without terminating \0 - return (int)idx; -} - - -/////////////////////////////////////////////////////////////////////////////// - -int printf(const char* format, ...) -{ - va_list va; - va_start(va, format); - char buffer[1]; - const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); - va_end(va); - return ret; -} - - -int sprintf(char* buffer, const char* format, ...) -{ - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va); - va_end(va); - return ret; -} - - -int snprintf(char* buffer, size_t count, const char* format, ...) -{ - va_list va; - va_start(va, format); - const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); - va_end(va); - return ret; -} - - -#if (defined(__GNUC__) && !defined(__clang__)) -int sniprintf (char *, size_t, const char *, ...) __copy(snprintf) __attribute__ ((__alias__("snprintf"))); -int puts(const char* s) -{ - // handle calls to printf("..."); here - while (*s) { - _putchar(*s++); - } - // puts: Writes the C string pointed by str to the standard output(stdout) and appends a newline character('\n') - _putchar('\n'); - return 0; -} -#endif - - -int vprintf(const char* format, va_list va) -{ - char buffer[1]; - return _vsnprintf(_out_char, buffer, (size_t)-1, format, va); -} - - -int vsnprintf(char* buffer, size_t count, const char* format, va_list va) -{ - return _vsnprintf(_out_buffer, buffer, count, format, va); -} - - -int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...) -{ - va_list va; - va_start(va, format); - const out_fct_wrap_type out_fct_wrap = { out, arg }; - const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); - va_end(va); - return ret; -} - - -int vfctprintf(void (*out)(char character, void* arg), void* arg, const char* format, va_list va) -{ - const out_fct_wrap_type out_fct_wrap = { out, arg }; - const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); - return ret; -} +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on +// embedded systems with a very limited resources. These routines are thread +// safe and reentrant! +// Use this instead of the bloated standard/newlib printf cause these use +// malloc for printf (and may not be thread safe). +// +/////////////////////////////////////////////////////////////////////////////// + +#include +#include + +#include "printf.h" + +// __copy__ attribute was introduced in GCC9 +#if defined(__GNUC__) && __GNUC__ >= 9 +#define __copy(symbol) __attribute__((__copy__(symbol))) +#else +#define __copy(symbol) +#endif + +// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the +// printf_config.h header file +// default: undefined +#ifdef PRINTF_INCLUDE_CONFIG_H +#include "printf_config.h" +#endif + + +// 'ntoa' conversion buffer size, this must be big enough to hold one converted +// numeric number including padded zeros (dynamically created on stack) +// default: 32 byte +#ifndef PRINTF_NTOA_BUFFER_SIZE +#define PRINTF_NTOA_BUFFER_SIZE 32U +#endif + +// 'ftoa' conversion buffer size, this must be big enough to hold one converted +// float number including padded zeros (dynamically created on stack) +// default: 32 byte +#ifndef PRINTF_FTOA_BUFFER_SIZE +#define PRINTF_FTOA_BUFFER_SIZE 32U +#endif + +// support for the floating point type (%f) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_FLOAT +#define PRINTF_SUPPORT_FLOAT +#endif + +// support for exponential floating point notation (%e/%g) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL +#define PRINTF_SUPPORT_EXPONENTIAL +#endif + +// define the default floating point precision +// default: 6 digits +#ifndef PRINTF_DEFAULT_FLOAT_PRECISION +#define PRINTF_DEFAULT_FLOAT_PRECISION 6U +#endif + +// define the largest float suitable to print with %f +// default: 1e9 +#ifndef PRINTF_MAX_FLOAT +#define PRINTF_MAX_FLOAT 1e9 +#endif + +// support for the long long types (%llu or %p) +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG +#define PRINTF_SUPPORT_LONG_LONG +#endif + +// support for the ptrdiff_t type (%t) +// ptrdiff_t is normally defined in as long or long long type +// default: activated +#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T +#define PRINTF_SUPPORT_PTRDIFF_T +#endif + +/////////////////////////////////////////////////////////////////////////////// + +// internal flag definitions +#define FLAGS_ZEROPAD (1U << 0U) +#define FLAGS_LEFT (1U << 1U) +#define FLAGS_PLUS (1U << 2U) +#define FLAGS_SPACE (1U << 3U) +#define FLAGS_HASH (1U << 4U) +#define FLAGS_UPPERCASE (1U << 5U) +#define FLAGS_CHAR (1U << 6U) +#define FLAGS_SHORT (1U << 7U) +#define FLAGS_LONG (1U << 8U) +#define FLAGS_LONG_LONG (1U << 9U) +#define FLAGS_PRECISION (1U << 10U) +#define FLAGS_ADAPT_EXP (1U << 11U) + + +// import float.h for DBL_MAX +#if defined(PRINTF_SUPPORT_FLOAT) +#include +#endif + + +// output function type +typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen); + + +// wrapper (used as buffer) for output function type +typedef struct { + void (*fct)(char character, void* arg); + void* arg; +} out_fct_wrap_type; + + +// internal buffer output +static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen) +{ + if (idx < maxlen) { + ((char*)buffer)[idx] = character; + } +} + + +// internal null output +static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)character; (void)buffer; (void)idx; (void)maxlen; +} + + +// internal _putchar wrapper +static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)buffer; (void)idx; (void)maxlen; + if (character) { + _putchar(character); + } +} + + +// internal output function wrapper +static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)idx; (void)maxlen; + if (character) { + // buffer is the output fct pointer + ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg); + } +} + + +// internal secure strlen +// \return The length of the string (excluding the terminating 0) limited by 'maxsize' +static inline unsigned int _strnlen_s(const char* str, size_t maxsize) +{ + const char* s; + for (s = str; *s && maxsize--; ++s); + return (unsigned int)(s - str); +} + + +// internal test if char is a digit (0-9) +// \return true if char is a digit +static inline bool _is_digit(char ch) +{ + return (ch >= '0') && (ch <= '9'); +} + + +// internal ASCII string to unsigned int conversion +static unsigned int _atoi(const char** str) +{ + unsigned int i = 0U; + while (_is_digit(**str)) { + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + } + return i; +} + + +// output the specified string in reverse, taking care of any zero-padding +static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags) +{ + const size_t start_idx = idx; + + // pad spaces up to given width + if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { + for (size_t i = len; i < width; i++) { + out(' ', buffer, idx++, maxlen); + } + } + + // reverse string + while (len) { + out(buf[--len], buffer, idx++, maxlen); + } + + // append pad spaces up to given width + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) { + out(' ', buffer, idx++, maxlen); + } + } + + return idx; +} + + +// internal itoa format +static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) +{ + // pad leading zeros + if (!(flags & FLAGS_LEFT)) { + if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + // handle hash + if (flags & FLAGS_HASH) { + if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { + len--; + if (len && (base == 16U)) { + len--; + } + } + if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'x'; + } + else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'X'; + } + else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'b'; + } + if (len < PRINTF_NTOA_BUFFER_SIZE) { + buf[len++] = '0'; + } + } + + if (len < PRINTF_NTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } + else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } + else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +// internal itoa for 'long' type +static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); +} + + +// internal itoa for 'long long' type +#if defined(PRINTF_SUPPORT_LONG_LONG) +static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if (!value) { + flags &= ~FLAGS_HASH; + } + + // write if precision != 0 and value is != 0 + if (!(flags & FLAGS_PRECISION) || value) { + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + value /= base; + } while (value && (len < PRINTF_NTOA_BUFFER_SIZE)); + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); +} +#endif // PRINTF_SUPPORT_LONG_LONG + + +#if defined(PRINTF_SUPPORT_FLOAT) + +#if defined(PRINTF_SUPPORT_EXPONENTIAL) +// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT +static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags); +#endif + + +// internal ftoa for fixed decimal floating point +static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) +{ + char buf[PRINTF_FTOA_BUFFER_SIZE]; + size_t len = 0U; + double diff = 0.0; + + // powers of 10 + static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 }; + + // test for special values + if (value != value) + return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags); + if (value < -DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags); + if (value > DBL_MAX) + return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags); + + // test for very large values + // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad + if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) { +#if defined(PRINTF_SUPPORT_EXPONENTIAL) + return _etoa(out, buffer, idx, maxlen, value, prec, width, flags); +#else + return 0U; +#endif + } + + // test for negative + bool negative = false; + if (value < 0) { + negative = true; + value = 0 - value; + } + + // set default precision, if not set explicitly + if (!(flags & FLAGS_PRECISION)) { + prec = PRINTF_DEFAULT_FLOAT_PRECISION; + } + // limit precision to 9, cause a prec >= 10 can lead to overflow errors + while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) { + buf[len++] = '0'; + prec--; + } + + int whole = (int)value; + double tmp = (value - whole) * pow10[prec]; + unsigned long frac = (unsigned long)tmp; + diff = tmp - frac; + + if (diff > 0.5) { + ++frac; + // handle rollover, e.g. case 0.99 with prec 1 is 1.0 + if (frac >= pow10[prec]) { + frac = 0; + ++whole; + } + } + else if (diff < 0.5) { + } + else if ((frac == 0U) || (frac & 1U)) { + // if halfway, round up if odd OR if last digit is 0 + ++frac; + } + + if (prec == 0U) { + diff = value - (double)whole; + if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) { + // exactly 0.5 and ODD, then round up + // 1.5 -> 2, but 2.5 -> 2 + ++whole; + } + } + else { + unsigned int count = prec; + // now do fractional part, as an unsigned number + while (len < PRINTF_FTOA_BUFFER_SIZE) { + --count; + buf[len++] = (char)(48U + (frac % 10U)); + if (!(frac /= 10U)) { + break; + } + } + // add extra 0s + while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { + buf[len++] = '0'; + } + if (len < PRINTF_FTOA_BUFFER_SIZE) { + // add decimal + buf[len++] = '.'; + } + } + + // do whole part, number is reversed + while (len < PRINTF_FTOA_BUFFER_SIZE) { + buf[len++] = (char)(48 + (whole % 10)); + if (!(whole /= 10)) { + break; + } + } + + // pad leading zeros + if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) { + if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + width--; + } + while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + } + } + + if (len < PRINTF_FTOA_BUFFER_SIZE) { + if (negative) { + buf[len++] = '-'; + } + else if (flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } + else if (flags & FLAGS_SPACE) { + buf[len++] = ' '; + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + + +#if defined(PRINTF_SUPPORT_EXPONENTIAL) +// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse +static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags) +{ + // check for NaN and special values + if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) { + return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags); + } + + // determine the sign + const bool negative = value < 0; + if (negative) { + value = -value; + } + + // default precision + if (!(flags & FLAGS_PRECISION)) { + prec = PRINTF_DEFAULT_FLOAT_PRECISION; + } + + // determine the decimal exponent + // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c) + union { + uint64_t U; + double F; + } conv; + + conv.F = value; + int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023; // effectively log2 + conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U); // drop the exponent so conv.F is now in [1,2) + // now approximate log10 from the log2 integer part and an expansion of ln around 1.5 + int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168); + // now we want to compute 10^expval but we want to be sure it won't overflow + exp2 = (int)(expval * 3.321928094887362 + 0.5); + const double z = expval * 2.302585092994046 - exp2 * 0.6931471805599453; + const double z2 = z * z; + conv.U = (uint64_t)(exp2 + 1023) << 52U; + // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex + conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14))))); + // correct for rounding errors + if (value < conv.F) { + expval--; + conv.F /= 10; + } + + // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters + unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U; + + // in "%g" mode, "prec" is the number of *significant figures* not decimals + if (flags & FLAGS_ADAPT_EXP) { + // do we want to fall-back to "%f" mode? + if ((value >= 1e-4) && (value < 1e6)) { + if ((int)prec > expval) { + prec = (unsigned)((int)prec - expval - 1); + } + else { + prec = 0; + } + flags |= FLAGS_PRECISION; // make sure _ftoa respects precision + // no characters in exponent + minwidth = 0U; + expval = 0; + } + else { + // we use one sigfig for the whole part + if ((prec > 0) && (flags & FLAGS_PRECISION)) { + --prec; + } + } + } + + // will everything fit? + unsigned int fwidth = width; + if (width > minwidth) { + // we didn't fall-back so subtract the characters required for the exponent + fwidth -= minwidth; + } else { + // not enough characters, so go back to default sizing + fwidth = 0U; + } + if ((flags & FLAGS_LEFT) && minwidth) { + // if we're padding on the right, DON'T pad the floating part + fwidth = 0U; + } + + // rescale the float value + if (expval) { + value /= conv.F; + } + + // output the floating part + const size_t start_idx = idx; + idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP); + + // output the exponent part + if (minwidth) { + // output the exponential symbol + out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen); + // output the exponent value + idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS); + // might need to right-pad spaces + if (flags & FLAGS_LEFT) { + while (idx - start_idx < width) out(' ', buffer, idx++, maxlen); + } + } + return idx; +} +#endif // PRINTF_SUPPORT_EXPONENTIAL +#endif // PRINTF_SUPPORT_FLOAT + + +// internal vsnprintf +static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va) +{ + unsigned int flags, width, precision, n; + size_t idx = 0U; + + if (!buffer) { + // use null output function + out = _out_null; + } + + while (*format) + { + // format specifier? %[flags][width][.precision][length] + if (*format != '%') { + // no + out(*format, buffer, idx++, maxlen); + format++; + continue; + } + else { + // yes, evaluate it + format++; + } + + // evaluate flags + flags = 0U; + do { + switch (*format) { + case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break; + case '-': flags |= FLAGS_LEFT; format++; n = 1U; break; + case '+': flags |= FLAGS_PLUS; format++; n = 1U; break; + case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break; + case '#': flags |= FLAGS_HASH; format++; n = 1U; break; + default : n = 0U; break; + } + } while (n); + + // evaluate width field + width = 0U; + if (_is_digit(*format)) { + width = _atoi(&format); + } + else if (*format == '*') { + const int w = va_arg(va, int); + if (w < 0) { + flags |= FLAGS_LEFT; // reverse padding + width = (unsigned int)-w; + } + else { + width = (unsigned int)w; + } + format++; + } + + // evaluate precision field + precision = 0U; + if (*format == '.') { + flags |= FLAGS_PRECISION; + format++; + if (_is_digit(*format)) { + precision = _atoi(&format); + } + else if (*format == '*') { + const int prec = (int)va_arg(va, int); + precision = prec > 0 ? (unsigned int)prec : 0U; + format++; + } + } + + // evaluate length field + switch (*format) { + case 'l' : + flags |= FLAGS_LONG; + format++; + if (*format == 'l') { + flags |= FLAGS_LONG_LONG; + format++; + } + break; + case 'h' : + flags |= FLAGS_SHORT; + format++; + if (*format == 'h') { + flags |= FLAGS_CHAR; + format++; + } + break; +#if defined(PRINTF_SUPPORT_PTRDIFF_T) + case 't' : + flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; +#endif + case 'j' : + flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + case 'z' : + flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + format++; + break; + default : + break; + } + + // evaluate specifier + switch (*format) { + case 'd' : + case 'i' : + case 'u' : + case 'x' : + case 'X' : + case 'o' : + case 'b' : { + // set the base + unsigned int base; + if (*format == 'x' || *format == 'X') { + base = 16U; + } + else if (*format == 'o') { + base = 8U; + } + else if (*format == 'b') { + base = 2U; + } + else { + base = 10U; + flags &= ~FLAGS_HASH; // no hash for dec format + } + // uppercase + if (*format == 'X') { + flags |= FLAGS_UPPERCASE; + } + + // no plus or space flag for u, x, X, o, b + if ((*format != 'i') && (*format != 'd')) { + flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + } + + // ignore '0' flag when precision is given + if (flags & FLAGS_PRECISION) { + flags &= ~FLAGS_ZEROPAD; + } + + // convert the integer + if ((*format == 'i') || (*format == 'd')) { + // signed + if (flags & FLAGS_LONG_LONG) { +#if defined(PRINTF_SUPPORT_LONG_LONG) + const long long value = va_arg(va, long long); + idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); +#endif + } + else if (flags & FLAGS_LONG) { + const long value = va_arg(va, long); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); + } + else { + const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int); + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags); + } + } + else { + // unsigned + if (flags & FLAGS_LONG_LONG) { +#if defined(PRINTF_SUPPORT_LONG_LONG) + idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); +#endif + } + else if (flags & FLAGS_LONG) { + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); + } + else { + const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + } + } + format++; + break; + } +#if defined(PRINTF_SUPPORT_FLOAT) + case 'f' : + case 'F' : + if (*format == 'F') flags |= FLAGS_UPPERCASE; + idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + format++; + break; +#if defined(PRINTF_SUPPORT_EXPONENTIAL) + case 'e': + case 'E': + case 'g': + case 'G': + if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP; + if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE; + idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags); + format++; + break; +#endif // PRINTF_SUPPORT_EXPONENTIAL +#endif // PRINTF_SUPPORT_FLOAT + case 'c' : { + unsigned int l = 1U; + // pre padding + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // char output + out((char)va_arg(va, int), buffer, idx++, maxlen); + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 's' : { + const char* p = va_arg(va, char*); + unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1); + // pre padding + if (flags & FLAGS_PRECISION) { + l = (l < precision ? l : precision); + } + if (!(flags & FLAGS_LEFT)) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + // string output + while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { + out(*(p++), buffer, idx++, maxlen); + } + // post padding + if (flags & FLAGS_LEFT) { + while (l++ < width) { + out(' ', buffer, idx++, maxlen); + } + } + format++; + break; + } + + case 'p' : { + width = sizeof(void*) * 2U; + flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; +#if defined(PRINTF_SUPPORT_LONG_LONG) + const bool is_ll = sizeof(uintptr_t) == sizeof(long long); + if (is_ll) { + idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags); + } + else { +#endif + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags); +#if defined(PRINTF_SUPPORT_LONG_LONG) + } +#endif + format++; + break; + } + + case '%' : + out('%', buffer, idx++, maxlen); + format++; + break; + + default : + out(*format, buffer, idx++, maxlen); + format++; + break; + } + } + + // termination + out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); + + // return written chars without terminating \0 + return (int)idx; +} + + +/////////////////////////////////////////////////////////////////////////////// + +int printf(const char* format, ...) +{ + va_list va; + va_start(va, format); + char buffer[1]; + const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} + + +int sprintf(char* buffer, const char* format, ...) +{ + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} + + +int snprintf(char* buffer, size_t count, const char* format, ...) +{ + va_list va; + va_start(va, format); + const int ret = _vsnprintf(_out_buffer, buffer, count, format, va); + va_end(va); + return ret; +} + + +#if (defined(__GNUC__) && !defined(__clang__)) +int sniprintf (char *, size_t, const char *, ...) __copy(snprintf) __attribute__ ((__alias__("snprintf"))); +int puts(const char* s) +{ + // handle calls to printf("..."); here + while (*s) { + _putchar(*s++); + } + // puts: Writes the C string pointed by str to the standard output(stdout) and appends a newline character('\n') + _putchar('\n'); + return 0; +} +#endif + + +int vprintf(const char* format, va_list va) +{ + char buffer[1]; + return _vsnprintf(_out_char, buffer, (size_t)-1, format, va); +} + + +int vsnprintf(char* buffer, size_t count, const char* format, va_list va) +{ + return _vsnprintf(_out_buffer, buffer, count, format, va); +} + + +int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...) +{ + va_list va; + va_start(va, format); + const out_fct_wrap_type out_fct_wrap = { out, arg }; + const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); + va_end(va); + return ret; +} + + +int vfctprintf(void (*out)(char character, void* arg), void* arg, const char* format, va_list va) +{ + const out_fct_wrap_type out_fct_wrap = { out, arg }; + const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); + return ret; +} diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.h b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.h index fb0d32d..4aac823 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.h +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/printf.h @@ -1,123 +1,123 @@ -/////////////////////////////////////////////////////////////////////////////// -// \author (c) Marco Paland (info@paland.com) -// 2014-2019, PALANDesign Hannover, Germany -// -// \license The MIT License (MIT) -// -// Permission is hereby granted, free of charge, to any person obtaining a copy -// of this software and associated documentation files (the "Software"), to deal -// in the Software without restriction, including without limitation the rights -// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -// copies of the Software, and to permit persons to whom the Software is -// furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in -// all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -// THE SOFTWARE. -// -// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on -// embedded systems with a very limited resources. -// Use this instead of bloated standard/newlib printf. -// These routines are thread safe and reentrant. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _PRINTF_H_ -#define _PRINTF_H_ - -#include -#include - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * Output a character to a custom device like UART, used by the printf() function - * This function is declared here only. You have to write your custom implementation somewhere - * \param character Character to output - */ -void _putchar(char character); - - -/** - * Tiny printf implementation - * You have to implement _putchar if you use printf() - * To avoid conflicts with the regular printf() API it is overridden by macro defines - * and internal underscore-appended functions like printf_() are used - * \param format A string that specifies the format of the output - * \return The number of characters that are written into the array, not counting the terminating null character - */ -int printf(const char* format, ...); - - -/** - * Tiny sprintf implementation - * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD! - * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output! - * \param format A string that specifies the format of the output - * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character - */ -int sprintf(char* buffer, const char* format, ...); - - -/** - * Tiny snprintf/vsnprintf implementation - * \param buffer A pointer to the buffer where to store the formatted string - * \param count The maximum number of characters to store in the buffer, including a terminating null character - * \param format A string that specifies the format of the output - * \param va A value identifying a variable arguments list - * \return The number of characters that COULD have been written into the buffer, not counting the terminating - * null character. A value equal or larger than count indicates truncation. Only when the returned value - * is non-negative and less than count, the string has been completely written. - */ -int snprintf(char* buffer, size_t count, const char* format, ...); -int vsnprintf(char* buffer, size_t count, const char* format, va_list va); - - -/** - * Tiny vprintf implementation - * \param format A string that specifies the format of the output - * \param va A value identifying a variable arguments list - * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character - */ -int vprintf(const char* format, va_list va); - - -/** - * printf with output function - * You may use this as dynamic alternative to printf() with its fixed _putchar() output - * \param out An output function which takes one character and an argument pointer - * \param arg An argument pointer for user data passed to output function - * \param format A string that specifies the format of the output - * \return The number of characters that are sent to the output function, not counting the terminating null character - */ -int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...); - - -/** - * printf with output function - * You may use this as dynamic alternative to printf() with its fixed _putchar() output - * \param out An output function which takes one character and an argument pointer - * \param arg An argument pointer for user data passed to output function - * \param format A string that specifies the format of the output - * \param va A value identifying a variable arguments list - * \return The number of characters that are sent to the output function, not counting the terminating null character - */ -int vfctprintf(void (*out)(char character, void* arg), void* arg, const char* format, va_list va); - -#ifdef __cplusplus -} -#endif - - -#endif // _PRINTF_H_ +/////////////////////////////////////////////////////////////////////////////// +// \author (c) Marco Paland (info@paland.com) +// 2014-2019, PALANDesign Hannover, Germany +// +// \license The MIT License (MIT) +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in +// all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +// THE SOFTWARE. +// +// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on +// embedded systems with a very limited resources. +// Use this instead of bloated standard/newlib printf. +// These routines are thread safe and reentrant. +// +/////////////////////////////////////////////////////////////////////////////// + +#ifndef _PRINTF_H_ +#define _PRINTF_H_ + +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * Output a character to a custom device like UART, used by the printf() function + * This function is declared here only. You have to write your custom implementation somewhere + * \param character Character to output + */ +void _putchar(char character); + + +/** + * Tiny printf implementation + * You have to implement _putchar if you use printf() + * To avoid conflicts with the regular printf() API it is overridden by macro defines + * and internal underscore-appended functions like printf_() are used + * \param format A string that specifies the format of the output + * \return The number of characters that are written into the array, not counting the terminating null character + */ +int printf(const char* format, ...); + + +/** + * Tiny sprintf implementation + * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD! + * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output! + * \param format A string that specifies the format of the output + * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character + */ +int sprintf(char* buffer, const char* format, ...); + + +/** + * Tiny snprintf/vsnprintf implementation + * \param buffer A pointer to the buffer where to store the formatted string + * \param count The maximum number of characters to store in the buffer, including a terminating null character + * \param format A string that specifies the format of the output + * \param va A value identifying a variable arguments list + * \return The number of characters that COULD have been written into the buffer, not counting the terminating + * null character. A value equal or larger than count indicates truncation. Only when the returned value + * is non-negative and less than count, the string has been completely written. + */ +int snprintf(char* buffer, size_t count, const char* format, ...); +int vsnprintf(char* buffer, size_t count, const char* format, va_list va); + + +/** + * Tiny vprintf implementation + * \param format A string that specifies the format of the output + * \param va A value identifying a variable arguments list + * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character + */ +int vprintf(const char* format, va_list va); + + +/** + * printf with output function + * You may use this as dynamic alternative to printf() with its fixed _putchar() output + * \param out An output function which takes one character and an argument pointer + * \param arg An argument pointer for user data passed to output function + * \param format A string that specifies the format of the output + * \return The number of characters that are sent to the output function, not counting the terminating null character + */ +int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...); + + +/** + * printf with output function + * You may use this as dynamic alternative to printf() with its fixed _putchar() output + * \param out An output function which takes one character and an argument pointer + * \param arg An argument pointer for user data passed to output function + * \param format A string that specifies the format of the output + * \param va A value identifying a variable arguments list + * \return The number of characters that are sent to the output function, not counting the terminating null character + */ +int vfctprintf(void (*out)(char character, void* arg), void* arg, const char* format, va_list va); + +#ifdef __cplusplus +} +#endif + + +#endif // _PRINTF_H_ diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/src/iostream_printf.c b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/src/iostream_printf.c index a0ed7b8..dbc19e1 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/printf/src/iostream_printf.c +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/printf/src/iostream_printf.c @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief IO Stream printf implementation - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_iostream.h" -#include "printf.h" -#include "stdarg.h" - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -static void stream_putchar(char character, void* arg); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * printf to stream implementation - ******************************************************************************/ -int sl_iostream_printf_to_stream(sl_iostream_t *stream, - const char *format, - ...) -{ - va_list va; - int ret; - va_start(va, format); - ret = fctprintf(stream_putchar, stream, format, va); - va_end(va); - return ret; -} - -/******************************************************************************* - ************************* PRIVATE CUSTOM FUNCTIONS ************************ - ******************************************************************************/ - -/***************************************************************************//** - * Function used by the printf()function to Output a character to a custom - * implementation. - ******************************************************************************/ -void _putchar(char character) -{ - sl_iostream_putchar(SL_IOSTREAM_STDOUT, character); -} - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ -/***************************************************************************//** - * putchar implementation for sl_iostream_printf_to_stream; called by fnctprintf() - ******************************************************************************/ -static void stream_putchar(char character, - void *arg) -{ - sl_iostream_t *stream = (sl_iostream_t *)arg; - sl_iostream_putchar(stream, character); -} +/***************************************************************************//** + * @file + * @brief IO Stream printf implementation + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_iostream.h" +#include "printf.h" +#include "stdarg.h" + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static void stream_putchar(char character, void* arg); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * printf to stream implementation + ******************************************************************************/ +int sl_iostream_printf_to_stream(sl_iostream_t *stream, + const char *format, + ...) +{ + va_list va; + int ret; + va_start(va, format); + ret = fctprintf(stream_putchar, stream, format, va); + va_end(va); + return ret; +} + +/******************************************************************************* + ************************* PRIVATE CUSTOM FUNCTIONS ************************ + ******************************************************************************/ + +/***************************************************************************//** + * Function used by the printf()function to Output a character to a custom + * implementation. + ******************************************************************************/ +void _putchar(char character) +{ + sl_iostream_putchar(SL_IOSTREAM_STDOUT, character); +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ +/***************************************************************************//** + * putchar implementation for sl_iostream_printf_to_stream; called by fnctprintf() + ******************************************************************************/ +static void stream_putchar(char character, + void *arg) +{ + sl_iostream_t *stream = (sl_iostream_t *)arg; + sl_iostream_putchar(stream, character); +} diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER.h b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER.h index 2c65a00..26ec795 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER.h +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER.h @@ -1,248 +1,248 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2023 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER SystemView * Real-time application analysis * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the SystemView and RTT protocol, and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* SystemView version: 3.52 * -* * -********************************************************************** ----------------------------------------------------------------------- -File : SEGGER.h -Purpose : Global types etc & general purpose utility functions -Revision: $Rev: 18102 $ ----------------------------END-OF-HEADER------------------------------ -*/ - -#ifndef SEGGER_H // Guard against multiple inclusion -#define SEGGER_H - -#include // For va_list. -#include "Global.h" // Type definitions: U8, U16, U32, I8, I16, I32 - -#if defined(__cplusplus) -extern "C" { /* Make sure we have C-declarations in C++ programs */ -#endif - -/********************************************************************* -* -* Keywords/specifiers -* -********************************************************************** -*/ - -#ifndef INLINE - #if (defined(__ICCARM__) || defined(__RX) || defined(__ICCRX__)) - // - // Other known compilers. - // - #define INLINE inline - #else - #if (defined(_WIN32) && !defined(__clang__)) - // - // Microsoft VC6 and newer. - // Force inlining without cost checking. - // - #define INLINE __forceinline - #elif defined(__GNUC__) || defined(__clang__) - // - // Force inlining with GCC + clang - // - #define INLINE inline __attribute__((always_inline)) - #elif (defined(__CC_ARM)) - // - // Force inlining with ARMCC (Keil) - // - #define INLINE __inline - #else - // - // Unknown compilers. - // - #define INLINE - #endif - #endif -#endif - -/********************************************************************* -* -* Function-like macros -* -********************************************************************** -*/ - -#define SEGGER_COUNTOF(a) (sizeof((a))/sizeof((a)[0])) -#define SEGGER_MIN(a,b) (((a) < (b)) ? (a) : (b)) -#define SEGGER_MAX(a,b) (((a) > (b)) ? (a) : (b)) - -#ifndef SEGGER_USE_PARA // Some compiler complain about unused parameters. - #define SEGGER_USE_PARA(Para) (void)Para // This works for most compilers. -#endif - -#define SEGGER_ADDR2PTR(Type, Addr) (/*lint -e(923) -e(9078)*/((Type*)((PTR_ADDR)(Addr)))) // Allow cast from address to pointer. -#define SEGGER_PTR2ADDR(p) (/*lint -e(923) -e(9078)*/((PTR_ADDR)(p))) // Allow cast from pointer to address. -#define SEGGER_PTR2PTR(Type, p) (/*lint -e(740) -e(826) -e(9079) -e(9087)*/((Type*)(p))) // Allow cast from one pointer type to another (ignore different size). -#define SEGGER_PTR_DISTANCE(p0, p1) (SEGGER_PTR2ADDR(p0) - SEGGER_PTR2ADDR(p1)) - -/********************************************************************* -* -* Defines -* -********************************************************************** -*/ - -#define SEGGER_PRINTF_FLAG_ADJLEFT (1 << 0) -#define SEGGER_PRINTF_FLAG_SIGNFORCE (1 << 1) -#define SEGGER_PRINTF_FLAG_SIGNSPACE (1 << 2) -#define SEGGER_PRINTF_FLAG_PRECEED (1 << 3) -#define SEGGER_PRINTF_FLAG_ZEROPAD (1 << 4) -#define SEGGER_PRINTF_FLAG_NEGATIVE (1 << 5) - -/********************************************************************* -* -* Types -* -********************************************************************** -*/ - -typedef struct { - char* pBuffer; - int BufferSize; - int Cnt; -} SEGGER_BUFFER_DESC; - -typedef struct { - unsigned int CacheLineSize; // 0: No Cache. Most Systems such as ARM9 use a 32 bytes cache line size. - void (*pfDMB) (void); // Optional DMB function for Data Memory Barrier to make sure all memory operations are completed. - void (*pfClean) (void *p, unsigned long NumBytes); // Optional clean function for cached memory. - void (*pfInvalidate)(void *p, unsigned long NumBytes); // Optional invalidate function for cached memory. -} SEGGER_CACHE_CONFIG; - -typedef struct SEGGER_SNPRINTF_CONTEXT_struct SEGGER_SNPRINTF_CONTEXT; - -struct SEGGER_SNPRINTF_CONTEXT_struct { - void* pContext; // Application specific context. - SEGGER_BUFFER_DESC* pBufferDesc; // Buffer descriptor to use for output. - void (*pfFlush)(SEGGER_SNPRINTF_CONTEXT* pContext); // Callback executed once the buffer is full. Callback decides if the buffer gets cleared to store more or not. -}; - -typedef struct { - void (*pfStoreChar) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, char c); - int (*pfPrintUnsigned) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, U32 v, unsigned Base, char Flags, int Width, int Precision); - int (*pfPrintInt) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, I32 v, unsigned Base, char Flags, int Width, int Precision); -} SEGGER_PRINTF_API; - -typedef void (*SEGGER_pFormatter)(SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, const SEGGER_PRINTF_API* pApi, va_list* pParamList, char Lead, int Width, int Precision); - -typedef struct SEGGER_PRINTF_FORMATTER { - struct SEGGER_PRINTF_FORMATTER* pNext; // Pointer to next formatter. - SEGGER_pFormatter pfFormatter; // Formatter function. - char Specifier; // Format specifier. -} SEGGER_PRINTF_FORMATTER; - -typedef struct { - U32 (*pfGetHPTimestamp)(void); // Mandatory, pfGetHPTimestamp - int (*pfGetUID) (U8 abUID[16]); // Optional, pfGetUID -} SEGGER_BSP_API; - -/********************************************************************* -* -* Utility functions -* -********************************************************************** -*/ - -// -// Memory operations. -// -void SEGGER_ARM_memcpy(void* pDest, const void* pSrc, int NumBytes); -void SEGGER_memcpy (void* pDest, const void* pSrc, unsigned NumBytes); -void SEGGER_memxor (void* pDest, const void* pSrc, unsigned NumBytes); - -// -// String functions. -// -int SEGGER_atoi (const char* s); -int SEGGER_isalnum (int c); -int SEGGER_isalpha (int c); -unsigned SEGGER_strlen (const char* s); -int SEGGER_tolower (int c); -int SEGGER_strcasecmp (const char* sText1, const char* sText2); -int SEGGER_strncasecmp(const char *sText1, const char *sText2, unsigned Count); - -// -// Buffer/printf related. -// -void SEGGER_StoreChar (SEGGER_BUFFER_DESC* pBufferDesc, char c); -void SEGGER_PrintUnsigned(SEGGER_BUFFER_DESC* pBufferDesc, U32 v, unsigned Base, int Precision); -void SEGGER_PrintInt (SEGGER_BUFFER_DESC* pBufferDesc, I32 v, unsigned Base, int Precision); -int SEGGER_snprintf (char* pBuffer, int BufferSize, const char* sFormat, ...); -int SEGGER_vsnprintf (char* pBuffer, int BufferSize, const char* sFormat, va_list ParamList); -int SEGGER_vsnprintfEx (SEGGER_SNPRINTF_CONTEXT* pContext, const char* sFormat, va_list ParamList); - -int SEGGER_PRINTF_AddFormatter (SEGGER_PRINTF_FORMATTER* pFormatter, SEGGER_pFormatter pfFormatter, char c); -void SEGGER_PRINTF_AddDoubleFormatter (void); -void SEGGER_PRINTF_AddIPFormatter (void); -void SEGGER_PRINTF_AddBLUEFormatter (void); -void SEGGER_PRINTF_AddCONNECTFormatter(void); -void SEGGER_PRINTF_AddSSLFormatter (void); -void SEGGER_PRINTF_AddSSHFormatter (void); -void SEGGER_PRINTF_AddHTMLFormatter (void); - -// -// BSP abstraction API. -// -int SEGGER_BSP_GetUID (U8 abUID[16]); -int SEGGER_BSP_GetUID32(U32* pUID); -void SEGGER_BSP_SetAPI (const SEGGER_BSP_API* pAPI); -void SEGGER_BSP_SeedUID (void); - -// -// Other API. -// -void SEGGER_VERSION_GetString(char acText[8], unsigned Version); - -#if defined(__cplusplus) -} /* Make sure we have C-declarations in C++ programs */ -#endif - -#endif // Avoid multiple inclusion - -/*************************** End of file ****************************/ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2023 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.52 * +* * +********************************************************************** +---------------------------------------------------------------------- +File : SEGGER.h +Purpose : Global types etc & general purpose utility functions +Revision: $Rev: 18102 $ +---------------------------END-OF-HEADER------------------------------ +*/ + +#ifndef SEGGER_H // Guard against multiple inclusion +#define SEGGER_H + +#include // For va_list. +#include "Global.h" // Type definitions: U8, U16, U32, I8, I16, I32 + +#if defined(__cplusplus) +extern "C" { /* Make sure we have C-declarations in C++ programs */ +#endif + +/********************************************************************* +* +* Keywords/specifiers +* +********************************************************************** +*/ + +#ifndef INLINE + #if (defined(__ICCARM__) || defined(__RX) || defined(__ICCRX__)) + // + // Other known compilers. + // + #define INLINE inline + #else + #if (defined(_WIN32) && !defined(__clang__)) + // + // Microsoft VC6 and newer. + // Force inlining without cost checking. + // + #define INLINE __forceinline + #elif defined(__GNUC__) || defined(__clang__) + // + // Force inlining with GCC + clang + // + #define INLINE inline __attribute__((always_inline)) + #elif (defined(__CC_ARM)) + // + // Force inlining with ARMCC (Keil) + // + #define INLINE __inline + #else + // + // Unknown compilers. + // + #define INLINE + #endif + #endif +#endif + +/********************************************************************* +* +* Function-like macros +* +********************************************************************** +*/ + +#define SEGGER_COUNTOF(a) (sizeof((a))/sizeof((a)[0])) +#define SEGGER_MIN(a,b) (((a) < (b)) ? (a) : (b)) +#define SEGGER_MAX(a,b) (((a) > (b)) ? (a) : (b)) + +#ifndef SEGGER_USE_PARA // Some compiler complain about unused parameters. + #define SEGGER_USE_PARA(Para) (void)Para // This works for most compilers. +#endif + +#define SEGGER_ADDR2PTR(Type, Addr) (/*lint -e(923) -e(9078)*/((Type*)((PTR_ADDR)(Addr)))) // Allow cast from address to pointer. +#define SEGGER_PTR2ADDR(p) (/*lint -e(923) -e(9078)*/((PTR_ADDR)(p))) // Allow cast from pointer to address. +#define SEGGER_PTR2PTR(Type, p) (/*lint -e(740) -e(826) -e(9079) -e(9087)*/((Type*)(p))) // Allow cast from one pointer type to another (ignore different size). +#define SEGGER_PTR_DISTANCE(p0, p1) (SEGGER_PTR2ADDR(p0) - SEGGER_PTR2ADDR(p1)) + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +#define SEGGER_PRINTF_FLAG_ADJLEFT (1 << 0) +#define SEGGER_PRINTF_FLAG_SIGNFORCE (1 << 1) +#define SEGGER_PRINTF_FLAG_SIGNSPACE (1 << 2) +#define SEGGER_PRINTF_FLAG_PRECEED (1 << 3) +#define SEGGER_PRINTF_FLAG_ZEROPAD (1 << 4) +#define SEGGER_PRINTF_FLAG_NEGATIVE (1 << 5) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +typedef struct { + char* pBuffer; + int BufferSize; + int Cnt; +} SEGGER_BUFFER_DESC; + +typedef struct { + unsigned int CacheLineSize; // 0: No Cache. Most Systems such as ARM9 use a 32 bytes cache line size. + void (*pfDMB) (void); // Optional DMB function for Data Memory Barrier to make sure all memory operations are completed. + void (*pfClean) (void *p, unsigned long NumBytes); // Optional clean function for cached memory. + void (*pfInvalidate)(void *p, unsigned long NumBytes); // Optional invalidate function for cached memory. +} SEGGER_CACHE_CONFIG; + +typedef struct SEGGER_SNPRINTF_CONTEXT_struct SEGGER_SNPRINTF_CONTEXT; + +struct SEGGER_SNPRINTF_CONTEXT_struct { + void* pContext; // Application specific context. + SEGGER_BUFFER_DESC* pBufferDesc; // Buffer descriptor to use for output. + void (*pfFlush)(SEGGER_SNPRINTF_CONTEXT* pContext); // Callback executed once the buffer is full. Callback decides if the buffer gets cleared to store more or not. +}; + +typedef struct { + void (*pfStoreChar) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, char c); + int (*pfPrintUnsigned) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, U32 v, unsigned Base, char Flags, int Width, int Precision); + int (*pfPrintInt) (SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, I32 v, unsigned Base, char Flags, int Width, int Precision); +} SEGGER_PRINTF_API; + +typedef void (*SEGGER_pFormatter)(SEGGER_BUFFER_DESC* pBufferDesc, SEGGER_SNPRINTF_CONTEXT* pContext, const SEGGER_PRINTF_API* pApi, va_list* pParamList, char Lead, int Width, int Precision); + +typedef struct SEGGER_PRINTF_FORMATTER { + struct SEGGER_PRINTF_FORMATTER* pNext; // Pointer to next formatter. + SEGGER_pFormatter pfFormatter; // Formatter function. + char Specifier; // Format specifier. +} SEGGER_PRINTF_FORMATTER; + +typedef struct { + U32 (*pfGetHPTimestamp)(void); // Mandatory, pfGetHPTimestamp + int (*pfGetUID) (U8 abUID[16]); // Optional, pfGetUID +} SEGGER_BSP_API; + +/********************************************************************* +* +* Utility functions +* +********************************************************************** +*/ + +// +// Memory operations. +// +void SEGGER_ARM_memcpy(void* pDest, const void* pSrc, int NumBytes); +void SEGGER_memcpy (void* pDest, const void* pSrc, unsigned NumBytes); +void SEGGER_memxor (void* pDest, const void* pSrc, unsigned NumBytes); + +// +// String functions. +// +int SEGGER_atoi (const char* s); +int SEGGER_isalnum (int c); +int SEGGER_isalpha (int c); +unsigned SEGGER_strlen (const char* s); +int SEGGER_tolower (int c); +int SEGGER_strcasecmp (const char* sText1, const char* sText2); +int SEGGER_strncasecmp(const char *sText1, const char *sText2, unsigned Count); + +// +// Buffer/printf related. +// +void SEGGER_StoreChar (SEGGER_BUFFER_DESC* pBufferDesc, char c); +void SEGGER_PrintUnsigned(SEGGER_BUFFER_DESC* pBufferDesc, U32 v, unsigned Base, int Precision); +void SEGGER_PrintInt (SEGGER_BUFFER_DESC* pBufferDesc, I32 v, unsigned Base, int Precision); +int SEGGER_snprintf (char* pBuffer, int BufferSize, const char* sFormat, ...); +int SEGGER_vsnprintf (char* pBuffer, int BufferSize, const char* sFormat, va_list ParamList); +int SEGGER_vsnprintfEx (SEGGER_SNPRINTF_CONTEXT* pContext, const char* sFormat, va_list ParamList); + +int SEGGER_PRINTF_AddFormatter (SEGGER_PRINTF_FORMATTER* pFormatter, SEGGER_pFormatter pfFormatter, char c); +void SEGGER_PRINTF_AddDoubleFormatter (void); +void SEGGER_PRINTF_AddIPFormatter (void); +void SEGGER_PRINTF_AddBLUEFormatter (void); +void SEGGER_PRINTF_AddCONNECTFormatter(void); +void SEGGER_PRINTF_AddSSLFormatter (void); +void SEGGER_PRINTF_AddSSHFormatter (void); +void SEGGER_PRINTF_AddHTMLFormatter (void); + +// +// BSP abstraction API. +// +int SEGGER_BSP_GetUID (U8 abUID[16]); +int SEGGER_BSP_GetUID32(U32* pUID); +void SEGGER_BSP_SetAPI (const SEGGER_BSP_API* pAPI); +void SEGGER_BSP_SeedUID (void); + +// +// Other API. +// +void SEGGER_VERSION_GetString(char acText[8], unsigned Version); + +#if defined(__cplusplus) +} /* Make sure we have C-declarations in C++ programs */ +#endif + +#endif // Avoid multiple inclusion + +/*************************** End of file ****************************/ diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c index a8cc9f8..ee1cd13 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c @@ -1,2104 +1,2104 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2023 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER SystemView * Real-time application analysis * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the SystemView and RTT protocol, and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* SystemView version: 3.52 * -* * -********************************************************************** ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.c -Purpose : Implementation of SEGGER real-time transfer (RTT) which - allows real-time communication on targets which support - debugger memory accesses while the CPU is running. -Revision: $Rev: 29668 $ - -Additional information: - Type "int" is assumed to be 32-bits in size - H->T Host to target communication - T->H Target to host communication - - RTT channel 0 is always present and reserved for Terminal usage. - Name is fixed to "Terminal" - - Effective buffer size: SizeOfBuffer - 1 - - WrOff == RdOff: Buffer is empty - WrOff == (RdOff - 1): Buffer is full - WrOff > RdOff: Free space includes wrap-around - WrOff < RdOff: Used space includes wrap-around - (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): - Buffer full and wrap-around after next byte - - ----------------------------------------------------------------------- -*/ - -#include "SEGGER_RTT.h" - -#include // for memcpy - -/********************************************************************* -* -* Configuration, default values -* -********************************************************************** -*/ - -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #ifdef SEGGER_RTT_CB_ALIGN - #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGN - #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_CB_SECTION - #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_PUT_BUFFER_SECTION - #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_BUFFER_ALIGNMENT - #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif - #ifdef SEGGER_RTT_ALIGNMENT - #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif -#endif - -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host -#endif - -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) -#endif - -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target -#endif - -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target -#endif - -#ifndef SEGGER_RTT_BUFFER_SECTION - #if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION - #endif -#endif - -#ifndef SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE -#endif - -#ifndef SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE -#endif - -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP -#endif - -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() -#endif - -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() -#endif - -#ifndef STRLEN - #define STRLEN(a) strlen((a)) -#endif - -#ifndef STRCPY - #define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) -#endif - -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 -#endif - -#ifndef SEGGER_RTT_MEMCPY - #ifdef MEMCPY - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) - #else - #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) - #endif -#endif - -#ifndef MIN - #define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#ifndef MAX - #define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -// -// For some environments, NULL may not be defined until certain headers are included -// -#ifndef NULL - #define NULL 0 -#endif - -/********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ -#if (defined __ICCARM__) || (defined __ICCRX__) - #define RTT_PRAGMA(P) _Pragma(#P) -#endif - -#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT - #if ((defined __GNUC__) || (defined __clang__)) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #elif (defined __ICCARM__) || (defined __ICCRX__) - #define PRAGMA(A) _Pragma(#A) -#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) - #else - #error "Alignment not supported for this compiler." - #endif -#else - #define SEGGER_RTT_ALIGN(Var, Alignment) Var -#endif - -#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) - #if ((defined __GNUC__) || (defined __clang__)) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var - #elif (defined __ICCARM__) || (defined __ICCRX__) -#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ - Var - #elif (defined __CC_ARM) - #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var - #else - #error "Section placement not supported for this compiler." - #endif -#else - #define SEGGER_RTT_PUT_SECTION(Var, Section) Var -#endif - -#if SEGGER_RTT_ALIGNMENT - #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) -#else - #define SEGGER_RTT_CB_ALIGN(Var) Var -#endif - -#if SEGGER_RTT_BUFFER_ALIGNMENT - #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) -#else - #define SEGGER_RTT_BUFFER_ALIGN(Var) Var -#endif - - -#if defined(SEGGER_RTT_SECTION) - #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) -#else - #define SEGGER_RTT_PUT_CB_SECTION(Var) Var -#endif - -#if defined(SEGGER_RTT_BUFFER_SECTION) - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) -#else - #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var -#endif - -/********************************************************************* -* -* Static const data -* -********************************************************************** -*/ - -static const unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; - -/********************************************************************* -* -* Static data -* -********************************************************************** -*/ - -// -// RTT Control Block and allocate buffers for channel 0 -// -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #if ((defined __GNUC__) || (defined __clang__)) - SEGGER_RTT_CB _SEGGER_RTT __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); - #elif (defined __ICCARM__) - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - SEGGER_RTT_CB _SEGGER_RTT; - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]; - #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE - static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)]; - #else - #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned" - #endif -#else - SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); - SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); - SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); -#endif - -static unsigned char _ActiveTerminal; - -/********************************************************************* -* -* Static functions -* -********************************************************************** -*/ - -/********************************************************************* -* -* _DoInit() -* -* Function description -* Initializes the control block an buffers. -* -* Notes -* (1) May only be called via INIT() to avoid overriding settings. -* The only exception is SEGGER_RTT_Init(), to make an intentional override possible. -*/ - #define INIT() \ - do { \ - volatile SEGGER_RTT_CB* pRTTCBInit; \ - pRTTCBInit = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ - if (pRTTCBInit->acID[0] != 'S') { \ - _DoInit(); \ - } \ - } while (0) - -static void _DoInit(void) { - volatile SEGGER_RTT_CB* p; // Volatile to make sure that compiler cannot change the order of accesses to the control block - static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES"; // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area - unsigned i; - // - // Initialize control block - // - p = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly - memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT)); // Make sure that the RTT CB is always zero initialized. - p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; - p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; - // - // Initialize up buffer 0 - // - p->aUp[0].sName = "Terminal"; - p->aUp[0].pBuffer = _acUpBuffer; - p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; - p->aUp[0].RdOff = 0u; - p->aUp[0].WrOff = 0u; - p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Initialize down buffer 0 - // - p->aDown[0].sName = "Terminal"; - p->aDown[0].pBuffer = _acDownBuffer; - p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; - p->aDown[0].RdOff = 0u; - p->aDown[0].WrOff = 0u; - p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; - // - // Finish initialization of the control block. - // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash), - // as this would cause J-Link to "find" the control block at a wrong address. - // - RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses - for (i = 0; i < sizeof(_aInitStr) - 1; ++i) { - p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i]; // Skip terminating \0 at the end of the array - } - RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses -} - -/********************************************************************* -* -* _WriteBlocking() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* The caller is responsible for managing the write chunk sizes as -* _WriteBlocking() will block until all data has been posted successfully. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* >= 0 - Number of bytes written into buffer. -*/ -static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { - unsigned NumBytesToWrite; - unsigned NumBytesWritten; - unsigned RdOff; - unsigned WrOff; - volatile char* pDst; - // - // Write data to buffer and handle wrap-around if necessary - // - NumBytesWritten = 0u; - WrOff = pRing->WrOff; - do { - RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime - if (RdOff > WrOff) { - NumBytesToWrite = RdOff - WrOff - 1u; - } else { - NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); - } - NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around - NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesWritten += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; - while (NumBytesToWrite--) { - *pDst++ = *pBuffer++; - }; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite); - NumBytesWritten += NumBytesToWrite; - pBuffer += NumBytesToWrite; - NumBytes -= NumBytesToWrite; - WrOff += NumBytesToWrite; -#endif - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0u; - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - } while (NumBytes); - return NumBytesWritten; -} - -/********************************************************************* -* -* _WriteNoCheck() -* -* Function description -* Stores a specified number of characters in SEGGER RTT ring buffer -* and updates the associated write pointer which is periodically -* read by the host. -* It is callers responsibility to make sure data actually fits in buffer. -* -* Parameters -* pRing Ring buffer to post to. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking -*/ -static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { - unsigned NumBytesAtOnce; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - - WrOff = pRing->WrOff; - Rem = pRing->SizeOfBuffer - WrOff; - if (Rem > NumBytes) { - // - // All data fits before wrap around - // - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - WrOff += NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; -#endif - } else { - // - // We reach the end of the buffer, so need to wrap around - // -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - NumBytesAtOnce = NumBytes - Rem; - while (NumBytesAtOnce--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes - Rem; -#else - NumBytesAtOnce = Rem; - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce); - NumBytesAtOnce = NumBytes - Rem; - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytesAtOnce; -#endif - } -} - -/********************************************************************* -* -* _PostTerminalSwitch() -* -* Function description -* Switch terminal to the given terminal ID. It is the caller's -* responsibility to ensure the terminal ID is correct and there is -* enough space in the buffer for this to complete successfully. -* -* Parameters -* pRing Ring buffer to post to. -* TerminalId Terminal ID to switch to. -*/ -static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { - unsigned char ac[2]; - - ac[0] = 0xFFu; - ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit - _WriteBlocking(pRing, (const char*)ac, 2u); -} - -/********************************************************************* -* -* _GetAvailWriteSpace() -* -* Function description -* Returns the number of bytes that can be written to the ring -* buffer without blocking. -* -* Parameters -* pRing Ring buffer to check. -* -* Return value -* Number of bytes that are free in the buffer. -*/ -static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - if (RdOff <= WrOff) { - r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; - } else { - r = RdOff - WrOff - 1u; - } - return r; -} - -/********************************************************************* -* -* Public code -* -********************************************************************** -*/ - -/********************************************************************* -* -* SEGGER_RTT_ReadUpBufferNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Do not lock against interrupts and multiple access. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_UP* pRing; - volatile char* pSrc; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - // - // Handle wrap-around of buffer - // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - } - // - // Update read offset of buffer - // - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_ReadNoLock() -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* Do not lock against interrupts and multiple access. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { - unsigned NumBytesRem; - unsigned NumBytesRead; - unsigned RdOff; - unsigned WrOff; - unsigned char* pBuffer; - SEGGER_RTT_BUFFER_DOWN* pRing; - volatile char* pSrc; - // - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - pBuffer = (unsigned char*)pData; - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - NumBytesRead = 0u; - // - // Read from current read position to wrap-around of buffer, first - // - if (RdOff > WrOff) { - NumBytesRem = pRing->SizeOfBuffer - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - // - // Handle wrap-around of buffer - // - if (RdOff == pRing->SizeOfBuffer) { - RdOff = 0u; - } - } - // - // Read remaining items of buffer - // - NumBytesRem = WrOff - RdOff; - NumBytesRem = MIN(NumBytesRem, BufferSize); - if (NumBytesRem > 0u) { - pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytesRead += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; - while (NumBytesRem--) { - *pBuffer++ = *pSrc++; - }; -#else - SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); - NumBytesRead += NumBytesRem; - pBuffer += NumBytesRem; - BufferSize -= NumBytesRem; - RdOff += NumBytesRem; -#endif - } - if (NumBytesRead) { - pRing->RdOff = RdOff; - } - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_ReadUpBuffer -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data via other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of Up-buffer to be used. -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the read operation, writing is also locked. -* If only one consumer reads from the up buffer, -* call sEGGER_RTT_ReadUpBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_Read -* -* Function description -* Reads characters from SEGGER real-time-terminal control block -* which have been previously stored by the host. -* -* Parameters -* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. -* BufferSize Size of the target application buffer. -* -* Return value -* Number of bytes that have been read. -*/ -unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { - unsigned NumBytesRead; - - SEGGER_RTT_LOCK(); - // - // Call the non-locking read function - // - NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return NumBytesRead; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteWithOverwriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block. -* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application -* and overwrites data if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, data is overwritten. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link -* connection reads RTT data. -*/ -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - volatile char* pDst; - // - // Get "to-host" ring buffer and copy some elements into local variables. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Check if we will overwrite data and need to adjust the RdOff. - // - if (pRing->WrOff == pRing->RdOff) { - Avail = pRing->SizeOfBuffer - 1u; - } else if ( pRing->WrOff < pRing->RdOff) { - Avail = pRing->RdOff - pRing->WrOff - 1u; - } else { - Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; - } - if (NumBytes > Avail) { - pRing->RdOff += (NumBytes - Avail); - while (pRing->RdOff >= pRing->SizeOfBuffer) { - pRing->RdOff -= pRing->SizeOfBuffer; - } - } - // - // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds - // - Avail = pRing->SizeOfBuffer - pRing->WrOff; - do { - if (Avail > NumBytes) { - // - // Last round - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - Avail = NumBytes; - while (NumBytes--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += Avail; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff += NumBytes; -#endif - break; - } else { - // - // Wrap-around necessary, write until wrap-around and reset WrOff - // - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; -#if SEGGER_RTT_MEMCPY_USE_BYTELOOP - NumBytes -= Avail; - while (Avail--) { - *pDst++ = *pData++; - }; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; -#else - SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail); - pData += Avail; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = 0; - NumBytes -= Avail; -#endif - Avail = (pRing->SizeOfBuffer - 1); - } - } while (NumBytes); -} - -/********************************************************************* -* -* SEGGER_RTT_WriteSkipNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteSkipNoLock does not lock the application and -* skips all data, if the data does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* MUST be > 0!!! -* This is done for performance reasons, so no initial check has do be done. -* -* Return value -* 1: Data has been copied -* 0: No space, data has not been copied -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, all data is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -#if (RTT_USE_ASM == 0) -unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - unsigned RdOff; - unsigned WrOff; - unsigned Rem; - volatile char* pDst; - // - // Cases: - // 1) RdOff <= WrOff => Space until wrap-around is sufficient - // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) - // 3) RdOff < WrOff => No space in buf - // 4) RdOff > WrOff => Space is sufficient - // 5) RdOff > WrOff => No space in buf - // - // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - WrOff = pRing->WrOff; - pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; - if (RdOff <= WrOff) { // Case 1), 2) or 3) - Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) - if (Avail >= NumBytes) { // Case 1)? - memcpy((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; - return 1; - } - Avail += RdOff; // Space incl. wrap-around - if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) - Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer - memcpy((void*)pDst, pData, Rem); // Copy 1st chunk - NumBytes -= Rem; - // - // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used - // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element - // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks - // Therefore, check if 2nd memcpy is necessary at all - // - if (NumBytes) { - pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; - memcpy((void*)pDst, pData + Rem, NumBytes); - } - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = NumBytes; - return 1; - } - } else { // Potential case 4) - Avail = RdOff - WrOff - 1u; - if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) - memcpy((void*)pDst, pData, NumBytes); - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff + NumBytes; - return 1; - } - } - return 0; // No space in buffer -} -#endif - -/********************************************************************* -* -* SEGGER_RTT_WriteDownBufferNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block inside a buffer. -* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. -* Used to do the same operation that J-Link does, to transfer -* RTT data from other channels, such as TCP/IP or UART. -* -* Parameters -* BufferIndex Index of "Down"-buffer to be used. -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -*/ -unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-target" ring buffer. - // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteNoLock -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* SEGGER_RTT_WriteNoLock does not lock the application. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ -unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - unsigned Avail; - const char* pData; - SEGGER_RTT_BUFFER_UP* pRing; - // - // Get "to-host" ring buffer. - // - pData = (const char *)pBuffer; - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // How we output depends upon the mode... - // - switch (pRing->Flags) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother. - // - Avail = _GetAvailWriteSpace(pRing); - if (Avail < NumBytes) { - Status = 0u; - } else { - Status = NumBytes; - _WriteNoCheck(pRing, pData, NumBytes); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode, trim to what we can output without blocking. - // - Avail = _GetAvailWriteSpace(pRing); - Status = Avail < NumBytes ? Avail : NumBytes; - _WriteNoCheck(pRing, pData, Status); - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - Status = _WriteBlocking(pRing, pData, NumBytes); - break; - default: - Status = 0u; - break; - } - // - // Finish up. - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteDownBuffer -* -* Function description -* Stores a specified number of characters in SEGGER RTT control block in a buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Down"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* -* Additional information -* This function must not be called when J-Link might also do RTT. -* This function locks against all other RTT operations. I.e. during -* the write operation, writing from the application is also locked. -* If only one consumer writes to the down buffer, -* call SEGGER_RTT_WriteDownBufferNoLock() instead. -*/ -unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_Write -* -* Function description -* Stores a specified number of characters in SEGGER RTT -* control block which is then read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. -* NumBytes Number of bytes to be stored in the SEGGER RTT control block. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ -unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { - unsigned Status; - - INIT(); - SEGGER_RTT_LOCK(); - Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_WriteString -* -* Function description -* Stores string in SEGGER RTT control block. -* This data is read by the host. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* s Pointer to string. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -* (2) String passed to this function has to be \0 terminated -* (3) \0 termination character is *not* stored in RTT buffer -*/ -unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { - unsigned Len; - - Len = STRLEN(s); - return SEGGER_RTT_Write(BufferIndex, s, Len); -} - -/********************************************************************* -* -* SEGGER_RTT_PutCharSkipNoLock -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* SEGGER_RTT_PutCharSkipNoLock does not lock the application and -* skips the byte, if it does not fit into the buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -* (2) For performance reasons this function does not call Init() -* and may only be called after RTT has been initialized. -* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. -*/ - -unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_PutCharSkip -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) If there is not enough space in the "Up"-buffer, the character is dropped. -*/ - -unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - // - return Status; -} - - /********************************************************************* -* -* SEGGER_RTT_PutChar -* -* Function description -* Stores a single character/byte in SEGGER RTT buffer. -* -* Parameters -* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). -* c Byte to be stored. -* -* Return value -* Number of bytes which have been stored in the "Up"-buffer. -* -* Notes -* (1) Data is stored according to buffer flags. -*/ - -unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned WrOff; - unsigned Status; - volatile char* pDst; - // - // Prepare - // - INIT(); - SEGGER_RTT_LOCK(); - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Get write position and handle wrap-around if necessary - // - WrOff = pRing->WrOff + 1; - if (WrOff == pRing->SizeOfBuffer) { - WrOff = 0; - } - // - // Wait for free space if mode is set to blocking - // - if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - while (WrOff == pRing->RdOff) { - ; - } - } - // - // Output byte if free space is available - // - if (WrOff != pRing->RdOff) { - pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; - *pDst = c; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - pRing->WrOff = WrOff; - Status = 1; - } else { - Status = 0; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_GetKey -* -* Function description -* Reads one character from the SEGGER RTT buffer. -* Host has previously stored data there. -* -* Return value -* < 0 - No character available (buffer empty). -* >= 0 - Character which has been read. (Possible values: 0 - 255) -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0. -*/ -int SEGGER_RTT_GetKey(void) { - char c; - int r; - - r = (int)SEGGER_RTT_Read(0u, &c, 1u); - if (r == 1) { - r = (int)(unsigned char)c; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_WaitKey -* -* Function description -* Waits until at least one character is avaible in the SEGGER RTT buffer. -* Once a character is available, it is read and this function returns. -* -* Return value -* >=0 - Character which has been read. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -* (2) This function is blocking if no character is present in RTT buffer -*/ -int SEGGER_RTT_WaitKey(void) { - int r; - - do { - r = SEGGER_RTT_GetKey(); - } while (r < 0); - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasKey -* -* Function description -* Checks if at least one character for reading is available in the SEGGER RTT buffer. -* -* Return value -* == 0 - No characters are available to read. -* == 1 - At least one character is available. -* -* Notes -* (1) This function is only specified for accesses to RTT buffer 0 -*/ -int SEGGER_RTT_HasKey(void) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned RdOff; - int r; - - INIT(); - pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRing->RdOff; - if (RdOff != pRing->WrOff) { - r = 1; - } else { - r = 0; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_HasData -* -* Function description -* Check if there is data from the host in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_DOWN* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->WrOff; - return v - pRing->RdOff; -} - -/********************************************************************* -* -* SEGGER_RTT_HasDataUp -* -* Function description -* Check if there is data remaining to be sent in the given buffer. -* -* Return value: -* ==0: No data -* !=0: Data in buffer -* -*/ -unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - unsigned v; - - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - v = pRing->RdOff; - return pRing->WrOff - v; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocDownBuffer -* -* Function description -* Run-time configuration of the next down-buffer (H->T). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumDownBuffers); - if (BufferIndex < pRTTCB->MaxNumDownBuffers) { - pRTTCB->aDown[BufferIndex].sName = sName; - pRTTCB->aDown[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aDown[BufferIndex].RdOff = 0u; - pRTTCB->aDown[BufferIndex].WrOff = 0u; - pRTTCB->aDown[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_AllocUpBuffer -* -* Function description -* Run-time configuration of the next up-buffer (T->H). -* The next buffer, which is not used yet is configured. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. Buffer Index -* < 0 - Error -*/ -int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int BufferIndex; - volatile SEGGER_RTT_CB* pRTTCB; - - INIT(); - SEGGER_RTT_LOCK(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - BufferIndex = 0; - do { - if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) { - break; - } - BufferIndex++; - } while (BufferIndex < pRTTCB->MaxNumUpBuffers); - if (BufferIndex < pRTTCB->MaxNumUpBuffers) { - pRTTCB->aUp[BufferIndex].sName = sName; - pRTTCB->aUp[BufferIndex].pBuffer = (char*)pBuffer; - pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; - pRTTCB->aUp[BufferIndex].RdOff = 0u; - pRTTCB->aUp[BufferIndex].WrOff = 0u; - pRTTCB->aUp[BufferIndex].Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - } else { - BufferIndex = -1; - } - SEGGER_RTT_UNLOCK(); - return BufferIndex; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer (T->H). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 - O.K. -* < 0 - Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - if (BufferIndex) { - pUp->sName = sName; - pUp->pBuffer = (char*)pBuffer; - pUp->SizeOfBuffer = BufferSize; - pUp->RdOff = 0u; - pUp->WrOff = 0u; - } - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_ConfigDownBuffer -* -* Function description -* Run-time configuration of a specific down-buffer (H->T). -* Buffer to be configured is specified by index. -* This includes: Buffer address, size, name, flags, ... -* -* Parameters -* BufferIndex Index of the buffer to configure. -* sName Pointer to a constant name string. -* pBuffer Pointer to a buffer to be used. -* BufferSize Size of the buffer. -* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -* -* Additional information -* Buffer 0 is configured on compile-time. -* May only be called once per buffer. -* Buffer name and flags can be reconfigured using the appropriate functions. -*/ -int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - if (BufferIndex) { - pDown->sName = sName; - pDown->pBuffer = (char*)pBuffer; - pDown->SizeOfBuffer = BufferSize; - pDown->RdOff = 0u; - pDown->WrOff = 0u; - } - pDown->Flags = Flags; - RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameUpBuffer -* -* Function description -* Run-time configuration of a specific up-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetNameDownBuffer -* -* Function description -* Run-time configuration of a specific Down-buffer name (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* sName Pointer to a constant name string. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->sName = sName; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetFlagsUpBuffer -* -* Function description -* Run-time configuration of specific up-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer. -* Flags Flags to set for the buffer. -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_UP* pUp; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { - SEGGER_RTT_LOCK(); - pUp = &pRTTCB->aUp[BufferIndex]; - pUp->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_SetFlagsDownBuffer -* -* Function description -* Run-time configuration of specific Down-buffer flags (T->H). -* Buffer to be configured is specified by index. -* -* Parameters -* BufferIndex Index of the buffer to renamed. -* Flags Flags to set for the buffer. -* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -* -* Return value -* >= 0 O.K. -* < 0 Error -*/ -int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { - int r; - volatile SEGGER_RTT_CB* pRTTCB; - volatile SEGGER_RTT_BUFFER_DOWN* pDown; - - INIT(); - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { - SEGGER_RTT_LOCK(); - pDown = &pRTTCB->aDown[BufferIndex]; - pDown->Flags = Flags; - SEGGER_RTT_UNLOCK(); - r = 0; - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_Init -* -* Function description -* Initializes the RTT Control Block. -* Should be used in RAM targets, at start of the application. -* -*/ -void SEGGER_RTT_Init (void) { - _DoInit(); -} - -/********************************************************************* -* -* SEGGER_RTT_SetTerminal -* -* Function description -* Sets the terminal to be used for output on channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* -* Return value -* >= 0 O.K. -* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) -* -* Notes -* (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { - unsigned char ac[2]; - SEGGER_RTT_BUFFER_UP* pRing; - unsigned Avail; - int r; - - INIT(); - r = 0; - ac[0] = 0xFFu; - if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels - ac[1] = _aTerminalId[TerminalId]; - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing - if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { - _ActiveTerminal = TerminalId; - _WriteBlocking(pRing, (const char*)ac, 2u); - } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes - Avail = _GetAvailWriteSpace(pRing); - if (Avail >= 2) { - _ActiveTerminal = TerminalId; // Only change active terminal in case of success - _WriteNoCheck(pRing, (const char*)ac, 2u); - } else { - r = -1; - } - } - SEGGER_RTT_UNLOCK(); - } else { - r = -1; - } - return r; -} - -/********************************************************************* -* -* SEGGER_RTT_TerminalOut -* -* Function description -* Writes a string to the given terminal -* without changing the terminal for channel 0. -* -* Parameters -* TerminalId Index of the terminal. -* s String to be printed on the terminal. -* -* Return value -* >= 0 - Number of bytes written. -* < 0 - Error. -* -*/ -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { - int Status; - unsigned FragLen; - unsigned Avail; - SEGGER_RTT_BUFFER_UP* pRing; - // - INIT(); - // - // Validate terminal ID. - // - if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels - // - // Get "to-host" ring buffer. - // - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - // - // Need to be able to change terminal, write data, change back. - // Compute the fixed and variable sizes. - // - FragLen = STRLEN(s); - // - // How we output depends upon the mode... - // - SEGGER_RTT_LOCK(); - Avail = _GetAvailWriteSpace(pRing); - switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { - case SEGGER_RTT_MODE_NO_BLOCK_SKIP: - // - // If we are in skip mode and there is no space for the whole - // of this output, don't bother switching terminals at all. - // - if (Avail < (FragLen + 4u)) { - Status = 0; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_NO_BLOCK_TRIM: - // - // If we are in trim mode and there is not enough space for everything, - // trim the output but always include the terminal switch. If no room - // for terminal switch, skip that totally. - // - if (Avail < 4u) { - Status = -1; - } else { - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); - _PostTerminalSwitch(pRing, _ActiveTerminal); - } - break; - case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: - // - // If we are in blocking mode, output everything. - // - _PostTerminalSwitch(pRing, TerminalId); - Status = (int)_WriteBlocking(pRing, s, FragLen); - _PostTerminalSwitch(pRing, _ActiveTerminal); - break; - default: - Status = -1; - break; - } - // - // Finish up. - // - SEGGER_RTT_UNLOCK(); - } else { - Status = -1; - } - return Status; -} - -/********************************************************************* -* -* SEGGER_RTT_GetAvailWriteSpace -* -* Function description -* Returns the number of bytes available in the ring buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are free in the selected up buffer. -*/ -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) { - SEGGER_RTT_BUFFER_UP* pRing; - - pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - return _GetAvailWriteSpace(pRing); -} - - -/********************************************************************* -* -* SEGGER_RTT_GetBytesInBuffer() -* -* Function description -* Returns the number of bytes currently used in the up buffer. -* -* Parameters -* BufferIndex Index of the up buffer. -* -* Return value -* Number of bytes that are used in the buffer. -*/ -unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { - unsigned RdOff; - unsigned WrOff; - unsigned r; - volatile SEGGER_RTT_CB* pRTTCB; - // - // Avoid warnings regarding volatile access order. It's not a problem - // in this case, but dampen compiler enthusiasm. - // - pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - RdOff = pRTTCB->aUp[BufferIndex].RdOff; - WrOff = pRTTCB->aUp[BufferIndex].WrOff; - if (RdOff <= WrOff) { - r = WrOff - RdOff; - } else { - r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); - } - return r; -} - -/*************************** End of file ****************************/ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2023 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.52 * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +Revision: $Rev: 29668 $ + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + + Effective buffer size: SizeOfBuffer - 1 + + WrOff == RdOff: Buffer is empty + WrOff == (RdOff - 1): Buffer is full + WrOff > RdOff: Free space includes wrap-around + WrOff < RdOff: Used space includes wrap-around + (WrOff == (SizeOfBuffer - 1)) && (RdOff == 0): + Buffer full and wrap-around after next byte + + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #ifdef SEGGER_RTT_CB_ALIGN + #error "Custom SEGGER_RTT_CB_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_BUFFER_ALIGN + #error "Custom SEGGER_RTT_BUFFER_ALIGN() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_PUT_CB_SECTION + #error "Custom SEGGER_RTT_PUT_CB_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_PUT_BUFFER_SECTION + #error "Custom SEGGER_RTT_PUT_BUFFER_SECTION() is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_BUFFER_ALIGNMENT + #error "Custom SEGGER_RTT_BUFFER_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif + #ifdef SEGGER_RTT_ALIGNMENT + #error "Custom SEGGER_RTT_ALIGNMENT is not supported for SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif +#endif + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_BUFFER_SECTION + #if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_BUFFER_SECTION SEGGER_RTT_SECTION + #endif +#endif + +#ifndef SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#endif + +#ifndef SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGNMENT SEGGER_RTT_CPU_CACHE_LINE_SIZE +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK() +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK() +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef STRCPY + #define STRCPY(pDest, pSrc) strcpy((pDest), (pSrc)) +#endif + +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP + #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 +#endif + +#ifndef SEGGER_RTT_MEMCPY + #ifdef MEMCPY + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) MEMCPY((pDest), (pSrc), (NumBytes)) + #else + #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) + #endif +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ +#if (defined __ICCARM__) || (defined __ICCRX__) + #define RTT_PRAGMA(P) _Pragma(#P) +#endif + +#if SEGGER_RTT_ALIGNMENT || SEGGER_RTT_BUFFER_ALIGNMENT + #if ((defined __GNUC__) || (defined __clang__)) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #elif (defined __ICCARM__) || (defined __ICCRX__) + #define PRAGMA(A) _Pragma(#A) +#define SEGGER_RTT_ALIGN(Var, Alignment) RTT_PRAGMA(data_alignment=Alignment) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_ALIGN(Var, Alignment) Var __attribute__ ((aligned (Alignment))) + #else + #error "Alignment not supported for this compiler." + #endif +#else + #define SEGGER_RTT_ALIGN(Var, Alignment) Var +#endif + +#if defined(SEGGER_RTT_SECTION) || defined (SEGGER_RTT_BUFFER_SECTION) + #if ((defined __GNUC__) || (defined __clang__)) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section))) Var + #elif (defined __ICCARM__) || (defined __ICCRX__) +#define SEGGER_RTT_PUT_SECTION(Var, Section) RTT_PRAGMA(location=Section) \ + Var + #elif (defined __CC_ARM) + #define SEGGER_RTT_PUT_SECTION(Var, Section) __attribute__ ((section (Section), zero_init)) Var + #else + #error "Section placement not supported for this compiler." + #endif +#else + #define SEGGER_RTT_PUT_SECTION(Var, Section) Var +#endif + +#if SEGGER_RTT_ALIGNMENT + #define SEGGER_RTT_CB_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_ALIGNMENT) +#else + #define SEGGER_RTT_CB_ALIGN(Var) Var +#endif + +#if SEGGER_RTT_BUFFER_ALIGNMENT + #define SEGGER_RTT_BUFFER_ALIGN(Var) SEGGER_RTT_ALIGN(Var, SEGGER_RTT_BUFFER_ALIGNMENT) +#else + #define SEGGER_RTT_BUFFER_ALIGN(Var) Var +#endif + + +#if defined(SEGGER_RTT_SECTION) + #define SEGGER_RTT_PUT_CB_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_SECTION) +#else + #define SEGGER_RTT_PUT_CB_SECTION(Var) Var +#endif + +#if defined(SEGGER_RTT_BUFFER_SECTION) + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) SEGGER_RTT_PUT_SECTION(Var, SEGGER_RTT_BUFFER_SECTION) +#else + #define SEGGER_RTT_PUT_BUFFER_SECTION(Var) Var +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static const unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ + +// +// RTT Control Block and allocate buffers for channel 0 +// +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #if ((defined __GNUC__) || (defined __clang__)) + SEGGER_RTT_CB _SEGGER_RTT __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)] __attribute__ ((aligned (SEGGER_RTT_CPU_CACHE_LINE_SIZE))); + #elif (defined __ICCARM__) + #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE + SEGGER_RTT_CB _SEGGER_RTT; + #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE + static char _acUpBuffer [SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_UP)]; + #pragma data_alignment=SEGGER_RTT_CPU_CACHE_LINE_SIZE + static char _acDownBuffer[SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(BUFFER_SIZE_DOWN)]; + #else + #error "Don't know how to place _SEGGER_RTT, _acUpBuffer, _acDownBuffer cache-line aligned" + #endif +#else + SEGGER_RTT_PUT_CB_SECTION(SEGGER_RTT_CB_ALIGN(SEGGER_RTT_CB _SEGGER_RTT)); + SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acUpBuffer [BUFFER_SIZE_UP])); + SEGGER_RTT_PUT_BUFFER_SECTION(SEGGER_RTT_BUFFER_ALIGN(static char _acDownBuffer[BUFFER_SIZE_DOWN])); +#endif + +static unsigned char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* +* Notes +* (1) May only be called via INIT() to avoid overriding settings. +* The only exception is SEGGER_RTT_Init(), to make an intentional override possible. +*/ + #define INIT() \ + do { \ + volatile SEGGER_RTT_CB* pRTTCBInit; \ + pRTTCBInit = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); \ + if (pRTTCBInit->acID[0] != 'S') { \ + _DoInit(); \ + } \ + } while (0) + +static void _DoInit(void) { + volatile SEGGER_RTT_CB* p; // Volatile to make sure that compiler cannot change the order of accesses to the control block + static const char _aInitStr[] = "\0\0\0\0\0\0TTR REGGES"; // Init complete ID string to make sure that things also work if RTT is linked to a no-init memory area + unsigned i; + // + // Initialize control block + // + p = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access control block uncached so that nothing in the cache ever becomes dirty and all changes are visible in HW directly + memset((SEGGER_RTT_CB*)p, 0, sizeof(_SEGGER_RTT)); // Make sure that the RTT CB is always zero initialized. + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = BUFFER_SIZE_UP; + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = BUFFER_SIZE_DOWN; + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string backwards to make sure that "SEGGER RTT" is not found in initializer memory (usually flash), + // as this would cause J-Link to "find" the control block at a wrong address. + // + RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses + for (i = 0; i < sizeof(_aInitStr) - 1; ++i) { + p->acID[i] = _aInitStr[sizeof(_aInitStr) - 2 - i]; // Skip terminating \0 at the end of the array + } + RTT__DMB(); // Force order of memory accesses for cores that may perform out-of-order memory accesses +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; + volatile char* pDst; + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesWritten += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + while (NumBytesToWrite--) { + *pDst++ = *pBuffer++; + }; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; +#endif + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + } while (NumBytes); + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; + volatile char* pDst; + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + WrOff += NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff + NumBytes; +#endif + } else { + // + // We reach the end of the buffer, so need to wrap around + // +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + NumBytesAtOnce = NumBytes - Rem; + while (NumBytesAtOnce--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytes - Rem; +#else + NumBytesAtOnce = Rem; + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + SEGGER_RTT_MEMCPY((void*)pDst, pData + Rem, NumBytesAtOnce); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytesAtOnce; +#endif + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + unsigned char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, (const char*)ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ + +/********************************************************************* +* +* SEGGER_RTT_ReadUpBufferNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Do not lock against interrupts and multiple access. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_UP* pRing; + volatile char* pSrc; + + INIT(); + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + // + // Update read offset of buffer + // + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; + volatile char* pSrc; + // + INIT(); + pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + pSrc = (pRing->pBuffer + RdOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytesRead += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + while (NumBytesRem--) { + *pBuffer++ = *pSrc++; + }; +#else + SEGGER_RTT_MEMCPY(pBuffer, (void*)pSrc, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; +#endif + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_ReadUpBuffer +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data via other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of Up-buffer to be used. +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-up-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the read operation, writing is also locked. +* If only one consumer reads from the up buffer, +* call sEGGER_RTT_ReadUpBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadUpBufferNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + + SEGGER_RTT_LOCK(); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteWithOverwriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block. +* SEGGER_RTT_WriteWithOverwriteNoLock does not lock the application +* and overwrites data if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, data is overwritten. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* (3) Do not use SEGGER_RTT_WriteWithOverwriteNoLock if a J-Link +* connection reads RTT data. +*/ +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + volatile char* pDst; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Check if we will overwrite data and need to adjust the RdOff. + // + if (pRing->WrOff == pRing->RdOff) { + Avail = pRing->SizeOfBuffer - 1u; + } else if ( pRing->WrOff < pRing->RdOff) { + Avail = pRing->RdOff - pRing->WrOff - 1u; + } else { + Avail = pRing->RdOff - pRing->WrOff - 1u + pRing->SizeOfBuffer; + } + if (NumBytes > Avail) { + pRing->RdOff += (NumBytes - Avail); + while (pRing->RdOff >= pRing->SizeOfBuffer) { + pRing->RdOff -= pRing->SizeOfBuffer; + } + } + // + // Write all data, no need to check the RdOff, but possibly handle multiple wrap-arounds + // + Avail = pRing->SizeOfBuffer - pRing->WrOff; + do { + if (Avail > NumBytes) { + // + // Last round + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + Avail = NumBytes; + while (NumBytes--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff += Avail; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff += NumBytes; +#endif + break; + } else { + // + // Wrap-around necessary, write until wrap-around and reset WrOff + // + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; +#if SEGGER_RTT_MEMCPY_USE_BYTELOOP + NumBytes -= Avail; + while (Avail--) { + *pDst++ = *pData++; + }; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = 0; +#else + SEGGER_RTT_MEMCPY((void*)pDst, pData, Avail); + pData += Avail; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = 0; + NumBytes -= Avail; +#endif + Avail = (pRing->SizeOfBuffer - 1); + } + } while (NumBytes); +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* MUST be > 0!!! +* This is done for performance reasons, so no initial check has do be done. +* +* Return value +* 1: Data has been copied +* 0: No space, data has not been copied +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +#if (RTT_USE_ASM == 0) +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + volatile char* pDst; + // + // Cases: + // 1) RdOff <= WrOff => Space until wrap-around is sufficient + // 2) RdOff <= WrOff => Space after wrap-around needed (copy in 2 chunks) + // 3) RdOff < WrOff => No space in buf + // 4) RdOff > WrOff => Space is sufficient + // 5) RdOff > WrOff => No space in buf + // + // 1) is the most common case for large buffers and assuming that J-Link reads the data fast enough + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + pDst = (pRing->pBuffer + WrOff) + SEGGER_RTT_UNCACHED_OFF; + if (RdOff <= WrOff) { // Case 1), 2) or 3) + Avail = pRing->SizeOfBuffer - WrOff - 1u; // Space until wrap-around (assume 1 byte not usable for case that RdOff == 0) + if (Avail >= NumBytes) { // Case 1)? + memcpy((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff + NumBytes; + return 1; + } + Avail += RdOff; // Space incl. wrap-around + if (Avail >= NumBytes) { // Case 2? => If not, we have case 3) (does not fit) + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + memcpy((void*)pDst, pData, Rem); // Copy 1st chunk + NumBytes -= Rem; + // + // Special case: First check that assumed RdOff == 0 calculated that last element before wrap-around could not be used + // But 2nd check (considering space until wrap-around and until RdOff) revealed that RdOff is not 0, so we can use the last element + // In this case, we may use a copy straight until buffer end anyway without needing to copy 2 chunks + // Therefore, check if 2nd memcpy is necessary at all + // + if (NumBytes) { + pDst = pRing->pBuffer + SEGGER_RTT_UNCACHED_OFF; + memcpy((void*)pDst, pData + Rem, NumBytes); + } + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = NumBytes; + return 1; + } + } else { // Potential case 4) + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { // Case 4)? => If not, we have case 5) (does not fit) + memcpy((void*)pDst, pData, NumBytes); + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff + NumBytes; + return 1; + } + } + return 0; // No space in buffer +} +#endif + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBufferNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block inside a buffer. +* SEGGER_RTT_WriteDownBufferNoLock does not lock the application. +* Used to do the same operation that J-Link does, to transfer +* RTT data from other channels, such as TCP/IP or UART. +* +* Parameters +* BufferIndex Index of "Down"-buffer to be used. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +*/ +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + // + // Get "to-target" ring buffer. + // It is save to cast that to a "to-host" buffer. Up and Down buffer differ in volatility of offsets that might be modified by J-Link. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + // + // Get "to-host" ring buffer. + // + pData = (const char *)pBuffer; + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteDownBuffer +* +* Function description +* Stores a specified number of characters in SEGGER RTT control block in a buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Down"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* +* Additional information +* This function must not be called when J-Link might also do RTT. +* This function locks against all other RTT operations. I.e. during +* the write operation, writing from the application is also locked. +* If only one consumer writes to the down buffer, +* call SEGGER_RTT_WriteDownBufferNoLock() instead. +*/ +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteDownBufferNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + + INIT(); + SEGGER_RTT_LOCK(); + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); // Call the non-locking write function + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkipNoLock +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* SEGGER_RTT_PutCharSkipNoLock does not lock the application and +* skips the byte, if it does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ + +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_PutCharSkip +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, the character is dropped. +*/ + +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + // + return Status; +} + + /********************************************************************* +* +* SEGGER_RTT_PutChar +* +* Function description +* Stores a single character/byte in SEGGER RTT buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* c Byte to be stored. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) Data is stored according to buffer flags. +*/ + +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned WrOff; + unsigned Status; + volatile char* pDst; + // + // Prepare + // + INIT(); + SEGGER_RTT_LOCK(); + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Get write position and handle wrap-around if necessary + // + WrOff = pRing->WrOff + 1; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0; + } + // + // Wait for free space if mode is set to blocking + // + if (pRing->Flags == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + while (WrOff == pRing->RdOff) { + ; + } + } + // + // Output byte if free space is available + // + if (WrOff != pRing->RdOff) { + pDst = (pRing->pBuffer + pRing->WrOff) + SEGGER_RTT_UNCACHED_OFF; + *pDst = c; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + pRing->WrOff = WrOff; + Status = 1; + } else { + Status = 0; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned RdOff; + int r; + + INIT(); + pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRing->RdOff; + if (RdOff != pRing->WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = (SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_HasDataUp +* +* Function description +* Check if there is data remaining to be sent in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_UP* pRing; + unsigned v; + + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + v = pRing->RdOff; + return pRing->WrOff - v; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile SEGGER_RTT_CB* pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + BufferIndex = 0; + do { + if (pRTTCB->aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumDownBuffers); + if (BufferIndex < pRTTCB->MaxNumDownBuffers) { + pRTTCB->aDown[BufferIndex].sName = sName; + pRTTCB->aDown[BufferIndex].pBuffer = (char*)pBuffer; + pRTTCB->aDown[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aDown[BufferIndex].RdOff = 0u; + pRTTCB->aDown[BufferIndex].WrOff = 0u; + pRTTCB->aDown[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile SEGGER_RTT_CB* pRTTCB; + + INIT(); + SEGGER_RTT_LOCK(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + BufferIndex = 0; + do { + if (pRTTCB->aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < pRTTCB->MaxNumUpBuffers); + if (BufferIndex < pRTTCB->MaxNumUpBuffers) { + pRTTCB->aUp[BufferIndex].sName = sName; + pRTTCB->aUp[BufferIndex].pBuffer = (char*)pBuffer; + pRTTCB->aUp[BufferIndex].SizeOfBuffer = BufferSize; + pRTTCB->aUp[BufferIndex].RdOff = 0u; + pRTTCB->aUp[BufferIndex].WrOff = 0u; + pRTTCB->aUp[BufferIndex].Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 - O.K. +* < 0 - Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + if (BufferIndex) { + pUp->sName = sName; + pUp->pBuffer = (char*)pBuffer; + pUp->SizeOfBuffer = BufferSize; + pUp->RdOff = 0u; + pUp->WrOff = 0u; + } + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 O.K. +* < 0 Error +* +* Additional information +* Buffer 0 is configured on compile-time. +* May only be called once per buffer. +* Buffer name and flags can be reconfigured using the appropriate functions. +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + if (BufferIndex) { + pDown->sName = sName; + pDown->pBuffer = (char*)pBuffer; + pDown->SizeOfBuffer = BufferSize; + pDown->RdOff = 0u; + pDown->WrOff = 0u; + } + pDown->Flags = Flags; + RTT__DMB(); // Force data write to be complete before writing the , in case CPU is allowed to change the order of memory accesses + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->sName = sName; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsUpBuffer +* +* Function description +* Run-time configuration of specific up-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer. +* Flags Flags to set for the buffer. +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_UP* pUp; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_UP_BUFFERS) { + SEGGER_RTT_LOCK(); + pUp = &pRTTCB->aUp[BufferIndex]; + pUp->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetFlagsDownBuffer +* +* Function description +* Run-time configuration of specific Down-buffer flags (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* Flags Flags to set for the buffer. +* Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags) { + int r; + volatile SEGGER_RTT_CB* pRTTCB; + volatile SEGGER_RTT_BUFFER_DOWN* pDown; + + INIT(); + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + if (BufferIndex < SEGGER_RTT_MAX_NUM_DOWN_BUFFERS) { + SEGGER_RTT_LOCK(); + pDown = &pRTTCB->aDown[BufferIndex]; + pDown->Flags = Flags; + SEGGER_RTT_UNLOCK(); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + _DoInit(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +* +* Notes +* (1) Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId) { + unsigned char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + int r; + + INIT(); + r = 0; + ac[0] = 0xFFu; + if (TerminalId < sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[TerminalId]; + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + SEGGER_RTT_LOCK(); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, (const char*)ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, (const char*)ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[0] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = STRLEN(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(); + } else { + Status = -1; + } + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_GetAvailWriteSpace +* +* Function description +* Returns the number of bytes available in the ring buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are free in the selected up buffer. +*/ +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex) { + SEGGER_RTT_BUFFER_UP* pRing; + + pRing = (SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[BufferIndex] + SEGGER_RTT_UNCACHED_OFF); // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + return _GetAvailWriteSpace(pRing); +} + + +/********************************************************************* +* +* SEGGER_RTT_GetBytesInBuffer() +* +* Function description +* Returns the number of bytes currently used in the up buffer. +* +* Parameters +* BufferIndex Index of the up buffer. +* +* Return value +* Number of bytes that are used in the buffer. +*/ +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + volatile SEGGER_RTT_CB* pRTTCB; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + pRTTCB = (volatile SEGGER_RTT_CB*)((uintptr_t)&_SEGGER_RTT + SEGGER_RTT_UNCACHED_OFF); // Access RTTCB uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + RdOff = pRTTCB->aUp[BufferIndex].RdOff; + WrOff = pRTTCB->aUp[BufferIndex].WrOff; + if (RdOff <= WrOff) { + r = WrOff - RdOff; + } else { + r = pRTTCB->aUp[BufferIndex].SizeOfBuffer - (WrOff - RdOff); + } + return r; +} + +/*************************** End of file ****************************/ diff --git a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h index 2873107..6ae8f00 100644 --- a/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h +++ b/locator_host/gecko_sdk_4.4.1/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.h @@ -1,505 +1,505 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 1995 - 2023 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* SEGGER SystemView * Real-time application analysis * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* SEGGER strongly recommends to not make any changes * -* to or modify the source code of this software in order to stay * -* compatible with the SystemView and RTT protocol, and J-Link. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* o Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** -* * -* SystemView version: 3.52 * -* * -********************************************************************** ----------------------------END-OF-HEADER------------------------------ -File : SEGGER_RTT.h -Purpose : Implementation of SEGGER real-time transfer which allows - real-time communication on targets which support debugger - memory accesses while the CPU is running. -Revision: $Rev: 25842 $ ----------------------------------------------------------------------- -*/ - -#ifndef SEGGER_RTT_H -#define SEGGER_RTT_H - -#include "SEGGER_RTT_Conf.h" - -/********************************************************************* -* -* Defines, defaults -* -********************************************************************** -*/ - -#ifndef RTT_USE_ASM - // - // Some cores support out-of-order memory accesses (reordering of memory accesses in the core) - // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers. - // Needed for: - // Cortex-M7 (ARMv7-M) - // Cortex-M23 (ARM-v8M) - // Cortex-M33 (ARM-v8M) - // Cortex-A/R (ARM-v7A/R) - // - // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support. - // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio" - // - #if (defined __CROSSWORKS_ARM) // Rowley Crossworks - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined(__ARM_ARCH_8_1M_MAIN__)) // Cortex-M85 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif (defined __ARMCC_VERSION) - // - // ARM compiler - // ARM compiler V6.0 and later is clang based. - // Our ASM part is compatible to clang. - // - #if (__ARMCC_VERSION >= 6000000) - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #else - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #endif - #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture - #elif (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif ((defined __GNUC__) || (defined __clang__)) - // - // GCC / Clang - // - #define _CC_HAS_RTT_ASM_SUPPORT 1 - // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__ - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here... - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #elif ((defined __IASMARM__) || (defined __ICCARM__)) - // - // IAR assembler/compiler - // - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #if (__VER__ < 6300000) - #define VOLATILE - #else - #define VOLATILE volatile - #endif - #if (defined __ARM7M__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #endif - #endif - #if (defined __ARM7EM__) - #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_BASELINE__) - #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8M_MAINLINE__) - #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM8EM_MAINLINE__) - #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-??? - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM7A__) - #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif - #if (defined __ARM7R__) - #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm VOLATILE ("DMB"); - #endif - #endif -// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A -// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R - #else - // - // Other compilers - // - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - // - // If IDE and core support the ASM version, enable ASM version by default - // - #ifndef _CORE_HAS_RTT_ASM_SUPPORT - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores - #endif - #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) - #define RTT_USE_ASM (1) - #else - #define RTT_USE_ASM (0) - #endif -#endif - -#ifndef _CORE_NEEDS_DMB - #define _CORE_NEEDS_DMB 0 -#endif - -#ifndef RTT__DMB - #if _CORE_NEEDS_DMB - #error "Don't know how to place inline assembly for DMB" - #else - #define RTT__DMB() - #endif -#endif - -#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE - #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here -#endif - -#ifndef SEGGER_RTT_UNCACHED_OFF - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #else - #define SEGGER_RTT_UNCACHED_OFF (0) - #endif -#endif -#if RTT_USE_ASM - #if SEGGER_RTT_CPU_CACHE_LINE_SIZE - #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" - #endif -#endif - -#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file -#include -#include -#include - -/********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ - -// -// Determine how much we must pad the control block to make it a multiple of a cache line in size -// Assuming: U8 = 1B -// U16 = 2B -// U32 = 4B -// U8/U16/U32* = 4B -// -#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) -#else - #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) -#endif -#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) -#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) - -/********************************************************************* -* -* Types -* -********************************************************************** -*/ - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as up-buffer (T->H) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - unsigned WrOff; // Position of next item to be written by either target. - volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. - unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -} SEGGER_RTT_BUFFER_UP; - -// -// Description for a circular buffer (also called "ring buffer") -// which is used as down-buffer (H->T) -// -typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. - unsigned RdOff; // Position of next item to be read by target (down-buffer). - unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. -} SEGGER_RTT_BUFFER_DOWN; - -// -// RTT control block which describes the number of buffers available -// as well as the configuration for each buffer -// -// -typedef struct { - char acID[16]; // Initialized to "SEGGER RTT" - int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) - int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) - SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host - SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target -#if SEGGER_RTT__CB_PADDING - unsigned char aDummy[SEGGER_RTT__CB_PADDING]; -#endif -} SEGGER_RTT_CB; - -/********************************************************************* -* -* Global data -* -********************************************************************** -*/ -extern SEGGER_RTT_CB _SEGGER_RTT; - -/********************************************************************* -* -* RTT API functions -* -********************************************************************** -*/ -#ifdef __cplusplus - extern "C" { -#endif -int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_GetKey (void); -unsigned SEGGER_RTT_HasData (unsigned BufferIndex); -int SEGGER_RTT_HasKey (void); -unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); -void SEGGER_RTT_Init (void); -unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_WaitKey (void); -unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); -unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); -// -// Function macro for performance optimization -// -#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) - -#if RTT_USE_ASM - #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock -#endif - -/********************************************************************* -* -* RTT transfer functions to send RTT data via other channels. -* -********************************************************************** -*/ -unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); - -#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly - -/********************************************************************* -* -* RTT "Terminal" API functions -* -********************************************************************** -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId); -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); - -/********************************************************************* -* -* RTT printf functions (require SEGGER_RTT_printf.c) -* -********************************************************************** -*/ -int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); -int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); - -#ifdef __cplusplus - } -#endif - -#endif // ifndef(SEGGER_RTT_ASM) - -/********************************************************************* -* -* Defines -* -********************************************************************** -*/ - -// -// Operating modes. Define behavior if buffer is full (not enough space for entire message) -// -#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) -#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. -#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. -#define SEGGER_RTT_MODE_MASK (3) - -// -// Control sequences, based on ANSI. -// Can be used to control color, and clear the screen -// -#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors -#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left - -#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" -#define RTT_CTRL_TEXT_RED "\x1B[2;31m" -#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" -#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" -#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" -#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" -#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" -#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" - -#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" -#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" -#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" -#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" -#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" -#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" -#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" -#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" - -#define RTT_CTRL_BG_BLACK "\x1B[24;40m" -#define RTT_CTRL_BG_RED "\x1B[24;41m" -#define RTT_CTRL_BG_GREEN "\x1B[24;42m" -#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" -#define RTT_CTRL_BG_BLUE "\x1B[24;44m" -#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" -#define RTT_CTRL_BG_CYAN "\x1B[24;46m" -#define RTT_CTRL_BG_WHITE "\x1B[24;47m" - -#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" -#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" -#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" -#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" -#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" -#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" -#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" -#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" - - -#endif - -/*************************** End of file ****************************/ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 1995 - 2023 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER SystemView * Real-time application analysis * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* SEGGER strongly recommends to not make any changes * +* to or modify the source code of this software in order to stay * +* compatible with the SystemView and RTT protocol, and J-Link. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* o Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* SystemView version: 3.52 * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +Revision: $Rev: 25842 $ +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, defaults +* +********************************************************************** +*/ + +#ifndef RTT_USE_ASM + // + // Some cores support out-of-order memory accesses (reordering of memory accesses in the core) + // For such cores, we need to define a memory barrier to guarantee the order of certain accesses to the RTT ring buffers. + // Needed for: + // Cortex-M7 (ARMv7-M) + // Cortex-M23 (ARM-v8M) + // Cortex-M33 (ARM-v8M) + // Cortex-A/R (ARM-v7A/R) + // + // We do not explicitly check for "Embedded Studio" as the compiler in use determines what we support. + // You can use an external toolchain like IAR inside ES. So there is no point in checking for "Embedded Studio" + // + #if (defined __CROSSWORKS_ARM) // Rowley Crossworks + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #if (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined(__ARM_ARCH_8_1M_MAIN__)) // Cortex-M85 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif (defined __ARMCC_VERSION) + // + // ARM compiler + // ARM compiler V6.0 and later is clang based. + // Our ASM part is compatible to clang. + // + #if (__ARMCC_VERSION >= 6000000) + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #else + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #endif + #if (defined __ARM_ARCH_6M__) // Cortex-M0 / M1 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 // No ASM support for this architecture + #elif (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif ((defined __GNUC__) || (defined __clang__)) + // + // GCC / Clang + // + #define _CC_HAS_RTT_ASM_SUPPORT 1 + // ARM 7/9: __ARM_ARCH_5__ / __ARM_ARCH_5E__ / __ARM_ARCH_5T__ / __ARM_ARCH_5T__ / __ARM_ARCH_5TE__ + #if (defined __ARM_ARCH_7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 // Only Cortex-M7 needs a DMB but we cannot distinguish M4 and M7 here... + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif (defined __ARM_ARCH_8_1M_MAIN__) // Cortex-M85 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #elif ((defined __ARM_ARCH_7A__) || (defined __ARM_ARCH_7R__)) // Cortex-A/R 32-bit ARMv7-A/R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() __asm volatile ("dmb\n" : : :); + #else + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + #elif ((defined __IASMARM__) || (defined __ICCARM__)) + // + // IAR assembler/compiler + // + #define _CC_HAS_RTT_ASM_SUPPORT 1 + #if (__VER__ < 6300000) + #define VOLATILE + #else + #define VOLATILE volatile + #endif + #if (defined __ARM7M__) // Needed for old versions that do not know the define yet + #if (__CORE__ == __ARM7M__) // Cortex-M3 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #endif + #endif + #if (defined __ARM7EM__) + #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8M_BASELINE__) + #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8M_MAINLINE__) + #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM8EM_MAINLINE__) + #if (__CORE__ == __ARM8EM_MAINLINE__) // Cortex-??? + #define _CORE_HAS_RTT_ASM_SUPPORT 1 + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM7A__) + #if (__CORE__ == __ARM7A__) // Cortex-A 32-bit ARMv7-A + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif + #if (defined __ARM7R__) + #if (__CORE__ == __ARM7R__) // Cortex-R 32-bit ARMv7-R + #define _CORE_NEEDS_DMB 1 + #define RTT__DMB() asm VOLATILE ("DMB"); + #endif + #endif +// TBD: __ARM8A__ => Cortex-A 64-bit ARMv8-A +// TBD: __ARM8R__ => Cortex-R 64-bit ARMv8-R + #else + // + // Other compilers + // + #define _CC_HAS_RTT_ASM_SUPPORT 0 + #define _CORE_HAS_RTT_ASM_SUPPORT 0 + #endif + // + // If IDE and core support the ASM version, enable ASM version by default + // + #ifndef _CORE_HAS_RTT_ASM_SUPPORT + #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores + #endif + #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) + #define RTT_USE_ASM (1) + #else + #define RTT_USE_ASM (0) + #endif +#endif + +#ifndef _CORE_NEEDS_DMB + #define _CORE_NEEDS_DMB 0 +#endif + +#ifndef RTT__DMB + #if _CORE_NEEDS_DMB + #error "Don't know how to place inline assembly for DMB" + #else + #define RTT__DMB() + #endif +#endif + +#ifndef SEGGER_RTT_CPU_CACHE_LINE_SIZE + #define SEGGER_RTT_CPU_CACHE_LINE_SIZE (0) // On most target systems where RTT is used, we do not have a CPU cache, therefore 0 is a good default here +#endif + +#ifndef SEGGER_RTT_UNCACHED_OFF + #if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #error "SEGGER_RTT_UNCACHED_OFF must be defined when setting SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #else + #define SEGGER_RTT_UNCACHED_OFF (0) + #endif +#endif +#if RTT_USE_ASM + #if SEGGER_RTT_CPU_CACHE_LINE_SIZE + #error "RTT_USE_ASM is not available if SEGGER_RTT_CPU_CACHE_LINE_SIZE != 0" + #endif +#endif + +#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file +#include +#include +#include + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +// +// Determine how much we must pad the control block to make it a multiple of a cache line in size +// Assuming: U8 = 1B +// U16 = 2B +// U32 = 4B +// U8/U16/U32* = 4B +// +#if SEGGER_RTT_CPU_CACHE_LINE_SIZE // Avoid division by zero in case we do not have any cache + #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (((NumBytes + SEGGER_RTT_CPU_CACHE_LINE_SIZE - 1) / SEGGER_RTT_CPU_CACHE_LINE_SIZE) * SEGGER_RTT_CPU_CACHE_LINE_SIZE) +#else + #define SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(NumBytes) (NumBytes) +#endif +#define SEGGER_RTT__CB_SIZE (16 + 4 + 4 + (SEGGER_RTT_MAX_NUM_UP_BUFFERS * 24) + (SEGGER_RTT_MAX_NUM_DOWN_BUFFERS * 24)) +#define SEGGER_RTT__CB_PADDING (SEGGER_RTT__ROUND_UP_2_CACHE_LINE_SIZE(SEGGER_RTT__CB_SIZE) - SEGGER_RTT__CB_SIZE) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags. Flags[31:24] are used for validity check and must be zero. Flags[23:2] are reserved for future use. Flags[1:0] = RTT operating mode. +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +#if SEGGER_RTT__CB_PADDING + unsigned char aDummy[SEGGER_RTT__CB_PADDING]; +#endif +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +#ifdef __cplusplus + extern "C" { +#endif +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); +unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); +unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (((SEGGER_RTT_BUFFER_DOWN*)((uintptr_t)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_DOWN*)((char*)&_SEGGER_RTT.aDown[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) + +#if RTT_USE_ASM + #define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock +#endif + +/********************************************************************* +* +* RTT transfer functions to send RTT data via other channels. +* +********************************************************************** +*/ +unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); + +#define SEGGER_RTT_HASDATA_UP(n) (((SEGGER_RTT_BUFFER_UP*)((uintptr_t)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->WrOff - ((SEGGER_RTT_BUFFER_UP*)((char*)&_SEGGER_RTT.aUp[n] + SEGGER_RTT_UNCACHED_OFF))->RdOff) // Access uncached to make sure we see changes made by the J-Link side and all of our changes go into HW directly + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (unsigned char TerminalId); +int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +#ifdef __cplusplus + } +#endif + +#endif // ifndef(SEGGER_RTT_ASM) + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" +#define RTT_CTRL_TEXT_RED "\x1B[2;31m" +#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" +#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" +#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" +#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" + +#define RTT_CTRL_BG_BLACK "\x1B[24;40m" +#define RTT_CTRL_BG_RED "\x1B[24;41m" +#define RTT_CTRL_BG_GREEN "\x1B[24;42m" +#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" +#define RTT_CTRL_BG_BLUE "\x1B[24;44m" +#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" +#define RTT_CTRL_BG_CYAN "\x1B[24;46m" +#define RTT_CTRL_BG_WHITE "\x1B[24;47m" + +#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" + + +#endif + +/*************************** End of file ****************************/ diff --git a/locator_host/locator_host.pintool b/locator_host/locator_host.pintool index a9a49fc..a879cdf 100644 --- a/locator_host/locator_host.pintool +++ b/locator_host/locator_host.pintool @@ -1,10 +1,10 @@ - - - - - - - - - - + + + + + + + + + + diff --git a/locator_host/locator_host.slcp b/locator_host/locator_host.slcp index 2e0d00f..838fcd9 100644 --- a/locator_host/locator_host.slcp +++ b/locator_host/locator_host.slcp @@ -1,57 +1,57 @@ -# Silicon Labs Project Configuration Tools: slcp, v0, Component selection file. -project_name: locator_host -label: locator_host -description: | - Reference implementation of an NCP (Network Co-Processor) host, which typically runs on a central MCU without radio. It can connect to an NCP target running the NCP Example via UART to access the Bluetooth stack on the target and to control it using BGAPI. -category: Bluetooth Examples -filter: -- name: Device Type - value: [Host] -- name: Project Difficulty - value: [Beginner] -- name: Wireless Technology - value: [Bluetooth] -package: Bluetooth -quality: production -readme: -- {path: readme.md} -sdk: {id: gecko_sdk, version: 4.4.1} -toolchain_settings: [] -component: -- {id: iostream_rtt} -- {id: ram_interrupt_vector_init} -- instance: [exp] - id: uartdrv_usart -- {id: emlib} -- {id: driver_mvp} -- {id: ncp_host_com} -- {id: mpu} -- {id: brd4187c} -- {id: gatt_configuration} -- {id: bluetooth_api_ncp_host} -- {id: math_mvp} -- {id: rtllib} -- {id: printf} -- {id: brd4002a} -- {id: EFR32MG24B220F1536IM48} -- {id: ncp_gatt} -- {id: device_init_dpll} -other_file: -- {path: image/readme_img0.png} -- {path: image/readme_img1.png} -- {path: image/readme_img2.png} -- {path: image/readme_img3.png} -configuration: -- {name: SL_STACK_SIZE, value: '2752'} -- {name: SL_HEAP_SIZE, value: '9200'} -- {name: SL_BOARD_ENABLE_VCOM, value: '0'} -- {name: SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE, value: uartdrvFlowControlNone} -- {name: EMDRV_UARTDRV_FLOW_CONTROL_ENABLE, value: '0'} -- {name: SL_SIMPLE_COM_UARTDRV_INSTANCE, value: SL_SIMPLE_COM_UARTDRV_INSTANCE_EXP} -- condition: [psa_crypto] - name: SL_PSA_KEY_USER_SLOT_COUNT - value: '0' -ui_hints: - highlight: - - {path: readme.md, focus: true} - - {path: config/btconf/gatt_configuration.btconf} +# Silicon Labs Project Configuration Tools: slcp, v0, Component selection file. +project_name: locator_host +label: locator_host +description: | + Reference implementation of an NCP (Network Co-Processor) host, which typically runs on a central MCU without radio. It can connect to an NCP target running the NCP Example via UART to access the Bluetooth stack on the target and to control it using BGAPI. +category: Bluetooth Examples +filter: +- name: Device Type + value: [Host] +- name: Project Difficulty + value: [Beginner] +- name: Wireless Technology + value: [Bluetooth] +package: Bluetooth +quality: production +readme: +- {path: readme.md} +sdk: {id: gecko_sdk, version: 4.4.1} +toolchain_settings: [] +component: +- {id: iostream_rtt} +- {id: ram_interrupt_vector_init} +- instance: [exp] + id: uartdrv_usart +- {id: emlib} +- {id: driver_mvp} +- {id: ncp_host_com} +- {id: mpu} +- {id: brd4187c} +- {id: gatt_configuration} +- {id: bluetooth_api_ncp_host} +- {id: math_mvp} +- {id: rtllib} +- {id: printf} +- {id: brd4002a} +- {id: EFR32MG24B220F1536IM48} +- {id: ncp_gatt} +- {id: device_init_dpll} +other_file: +- {path: image/readme_img0.png} +- {path: image/readme_img1.png} +- {path: image/readme_img2.png} +- {path: image/readme_img3.png} +configuration: +- {name: SL_STACK_SIZE, value: '2752'} +- {name: SL_HEAP_SIZE, value: '9200'} +- {name: SL_BOARD_ENABLE_VCOM, value: '0'} +- {name: SL_UARTDRV_USART_EXP_FLOW_CONTROL_TYPE, value: uartdrvFlowControlNone} +- {name: EMDRV_UARTDRV_FLOW_CONTROL_ENABLE, value: '0'} +- {name: SL_SIMPLE_COM_UARTDRV_INSTANCE, value: SL_SIMPLE_COM_UARTDRV_INSTANCE_EXP} +- condition: [psa_crypto] + name: SL_PSA_KEY_USER_SLOT_COUNT + value: '0' +ui_hints: + highlight: + - {path: readme.md, focus: true} + - {path: config/btconf/gatt_configuration.btconf} diff --git a/locator_host/locator_host.slps b/locator_host/locator_host.slps index 0127c6a..ff9f3e0 100644 --- a/locator_host/locator_host.slps +++ b/locator_host/locator_host.slps @@ -1,16 +1,16 @@ - - - - - - - - - - - - - - - - \ No newline at end of file + + + + + + + + + + + + + + + + diff --git a/locator_host/locator_host_cmake/CMakeLists.txt b/locator_host/locator_host_cmake/CMakeLists.txt index 3cd6146..88b18a7 100644 --- a/locator_host/locator_host_cmake/CMakeLists.txt +++ b/locator_host/locator_host_cmake/CMakeLists.txt @@ -1,55 +1,55 @@ -# Define minimal required version of CMake. -cmake_minimum_required(VERSION "3.25") - -# Project definition -project( - locator_host - VERSION 1.0 - LANGUAGES C CXX ASM -) - -# Include the definition of the slc_locator_host target, -# which contains the content of the SLC project -include(locator_host.cmake) - -add_executable(locator_host - ../app.c - ../main.c -) - -add_subdirectory(../bt ${CMAKE_CURRENT_BINARY_DIR}/bt) -add_subdirectory(../drivers ${CMAKE_CURRENT_BINARY_DIR}/drivers) - -# Link with the content defined in the SLC project -target_link_libraries(locator_host PRIVATE - bt - drivers - slc_locator_host -) - -# Include managed project content if available -include(locator_host_project.cmake OPTIONAL RESULT_VARIABLE managed_project) -if(managed_project) - message(STATUS "Using managed project content from ${managed_project}") -endif() - -# Force the gcc linker command -set_target_properties(locator_host PROPERTIES LINKER_LANGUAGE C) - -# Create .bin, .hex and .s37 artifacts after building the project -add_custom_command(TARGET locator_host - POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -O srec "$" "$/$.s37" - COMMAND ${CMAKE_OBJCOPY} -O ihex "$" "$/$.hex" - COMMAND ${CMAKE_OBJCOPY} -O binary "$" "$/$.bin" - COMMAND ${CMAKE_SIZE_UTIL} "$" -A -) - -# Run post-build pipeline to perform additional post-processing -if(post_build_command) -add_custom_command(TARGET locator_host - POST_BUILD - WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/.. - COMMAND ${post_build_command} -) -endif() +# Define minimal required version of CMake. +cmake_minimum_required(VERSION "3.25") + +# Project definition +project( + locator_host + VERSION 1.0 + LANGUAGES C CXX ASM +) + +# Include the definition of the slc_locator_host target, +# which contains the content of the SLC project +include(locator_host.cmake) + +add_executable(locator_host + ../app.c + ../main.c +) + +add_subdirectory(../bt ${CMAKE_CURRENT_BINARY_DIR}/bt) +add_subdirectory(../drivers ${CMAKE_CURRENT_BINARY_DIR}/drivers) + +# Link with the content defined in the SLC project +target_link_libraries(locator_host PRIVATE + bt + drivers + slc_locator_host +) + +# Include managed project content if available +include(locator_host_project.cmake OPTIONAL RESULT_VARIABLE managed_project) +if(managed_project) + message(STATUS "Using managed project content from ${managed_project}") +endif() + +# Force the gcc linker command +set_target_properties(locator_host PROPERTIES LINKER_LANGUAGE C) + +# Create .bin, .hex and .s37 artifacts after building the project +add_custom_command(TARGET locator_host + POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O srec "$" "$/$.s37" + COMMAND ${CMAKE_OBJCOPY} -O ihex "$" "$/$.hex" + COMMAND ${CMAKE_OBJCOPY} -O binary "$" "$/$.bin" + COMMAND ${CMAKE_SIZE_UTIL} "$" -A +) + +# Run post-build pipeline to perform additional post-processing +if(post_build_command) +add_custom_command(TARGET locator_host + POST_BUILD + WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}/.. + COMMAND ${post_build_command} +) +endif() diff --git a/locator_host/locator_host_cmake/CMakePresets.json b/locator_host/locator_host_cmake/CMakePresets.json index 474bbdb..c7a7057 100644 --- a/locator_host/locator_host_cmake/CMakePresets.json +++ b/locator_host/locator_host_cmake/CMakePresets.json @@ -1,35 +1,35 @@ -{ - "version": 6, - "cmakeMinimumRequired": { - "major": 3, - "minor": 25, - "patch": 0 - }, - "configurePresets": [ - { - "name": "project", - "displayName": "Configure locator_host", - "generator": "Ninja Multi-Config", - "binaryDir": "${sourceDir}/../build", - "toolchainFile": "${sourceDir}/toolchain.cmake" - } - ], - "buildPresets": [ - { - "name": "default_config", - "displayName": "Build locator_host", - "configurePreset": "project", - "configuration": "Debug", - "targets": ["locator_host"] - } - ], - "workflowPresets": [ - { - "name": "project", - "steps": [ - {"type": "configure", "name": "project"}, - {"type": "build", "name": "default_config"} - ] - } - ] - } +{ + "version": 6, + "cmakeMinimumRequired": { + "major": 3, + "minor": 25, + "patch": 0 + }, + "configurePresets": [ + { + "name": "project", + "displayName": "Configure locator_host", + "generator": "Ninja Multi-Config", + "binaryDir": "${sourceDir}/../build", + "toolchainFile": "${sourceDir}/toolchain.cmake" + } + ], + "buildPresets": [ + { + "name": "default_config", + "displayName": "Build locator_host", + "configurePreset": "project", + "configuration": "Debug", + "targets": ["locator_host"] + } + ], + "workflowPresets": [ + { + "name": "project", + "steps": [ + {"type": "configure", "name": "project"}, + {"type": "build", "name": "default_config"} + ] + } + ] + } diff --git a/locator_host/locator_host_cmake/locator_host.cmake b/locator_host/locator_host_cmake/locator_host.cmake index 174dc1e..db795d5 100644 --- a/locator_host/locator_host_cmake/locator_host.cmake +++ b/locator_host/locator_host_cmake/locator_host.cmake @@ -1,233 +1,233 @@ -set(SDK_PATH "C:/Users/tilaczko/SimplicityStudio/SDKs/gecko_sdk_2") -set(COPIED_SDK_PATH "gecko_sdk_4.4.1") - -add_library(slc_locator_host OBJECT - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_robust.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_usart.c" - "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_control_gpio.c" - "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_init.c" - "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/src/sl_cos.c" - "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c" - "../${COPIED_SDK_PATH}/platform/common/src/sl_assert.c" - "../${COPIED_SDK_PATH}/platform/common/src/sl_syscalls.c" - "../${COPIED_SDK_PATH}/platform/common/toolchain/src/sl_memory.c" - "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp.c" - "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c" - "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_program_area.c" - "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_util.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_util.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c" - "../${COPIED_SDK_PATH}/platform/compute/math/src/sl_math_matrix.c" - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c" - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c" - "../${COPIED_SDK_PATH}/platform/driver/debug/src/sl_debug_swo.c" - "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/src/dmadrv.c" - "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c" - "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/src/uartdrv.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_acmp.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_burtc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_cmu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_core.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_dbg.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_emu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_eusart.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpcrc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpio.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_i2c.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_iadc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_ldma.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_letimer.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_msc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_opamp.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_pcnt.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_prs.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_rmu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_se.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_system.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_timer.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_usart.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_vdac.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_wdog.c" - "../${COPIED_SDK_PATH}/platform/peripheral/src/peripheral_sysrtc.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dcdc_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dpll_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_emu_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_hfxo_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfxo_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_nvic.c" - "../${COPIED_SDK_PATH}/platform/service/iostream/src/sl_iostream.c" - "../${COPIED_SDK_PATH}/platform/service/iostream/src/sl_iostream_rtt.c" - "../${COPIED_SDK_PATH}/platform/service/mpu/src/sl_mpu.c" - "../${COPIED_SDK_PATH}/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c" - "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_init.c" - "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_process_action.c" - "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay.c" - "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_ncp_host.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_ncp_host_api.c" - "../${COPIED_SDK_PATH}/util/third_party/printf/printf.c" - "../${COPIED_SDK_PATH}/util/third_party/printf/src/iostream_printf.c" - "../${COPIED_SDK_PATH}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c" - "../autogen/gatt_db.c" - "../autogen/sl_bluetooth.c" - "../autogen/sl_board_default_init.c" - "../autogen/sl_device_init_clocks.c" - "../autogen/sl_event_handler.c" - "../autogen/sl_iostream_handles.c" - "../autogen/sl_simple_com_isr.c" - "../autogen/sl_uartdrv_init.c" -) - -target_include_directories(slc_locator_host PUBLIC - "../config" - "../config/btconf" - "../autogen" - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Include" - "../${COPIED_SDK_PATH}/app/common/util/app_assert" - "../${COPIED_SDK_PATH}/platform/common/inc" - "../${COPIED_SDK_PATH}/protocol/bluetooth/inc" - "../${COPIED_SDK_PATH}/hardware/board/inc" - "../${COPIED_SDK_PATH}/platform/CMSIS/Core/Include" - "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/inc" - "../${COPIED_SDK_PATH}/platform/driver/debug/inc" - "../${COPIED_SDK_PATH}/platform/service/device_init/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/inc" - "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/common/inc" - "../${COPIED_SDK_PATH}/platform/emlib/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/inc" - "../${COPIED_SDK_PATH}/platform/service/iostream/inc" - "../${COPIED_SDK_PATH}/platform/compute/math/inc" - "../${COPIED_SDK_PATH}/platform/compute/math/mvp/inc" - "../${COPIED_SDK_PATH}/platform/service/mpu/inc" - "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_gatt" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_host_com" - "../${COPIED_SDK_PATH}/platform/peripheral/inc" - "../${COPIED_SDK_PATH}/util/third_party/printf" - "../${COPIED_SDK_PATH}/util/third_party/printf/inc" - "../${COPIED_SDK_PATH}/platform/service/ram_interrupt_vector_init/inc" - "../${COPIED_SDK_PATH}/util/silicon_labs/aox/inc" - "../${COPIED_SDK_PATH}/util/third_party/segger/systemview/SEGGER" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com" - "../${COPIED_SDK_PATH}/platform/common/toolchain/inc" - "../${COPIED_SDK_PATH}/platform/service/system/inc" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/inc" - "../${COPIED_SDK_PATH}/platform/service/udelay/inc" -) - -target_compile_definitions(slc_locator_host PUBLIC - "EFR32MG24B220F1536IM48=1" - "HARDWARE_BOARD_DEFAULT_RF_BAND_2400=1" - "HARDWARE_BOARD_SUPPORTS_1_RF_BAND=1" - "HARDWARE_BOARD_SUPPORTS_RF_BAND_2400=1" - "HFXO_FREQ=39000000" - "SL_BOARD_NAME=\"BRD4187C\"" - "SL_BOARD_REV=\"A01\"" - "SL_COMPONENT_CATALOG_PRESENT=1" - "RTT_USE_ASM=0" - "SEGGER_RTT_SECTION=\"SEGGER_RTT\"" -) - -target_link_libraries(slc_locator_host PUBLIC - "-Wl,--start-group" - "stdc++" - "gcc" - "c" - "m" - "nosys" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/util/silicon_labs/aox/lib/release/gcc/arm_m33/generic/libaox_static.a" - "-Wl,--end-group" -) -target_compile_options(slc_locator_host PUBLIC - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - $<$:-Wall> - $<$:-Wextra> - $<$:-Os> - $<$:-fdata-sections> - $<$:-ffunction-sections> - $<$:-fomit-frame-pointer> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - $<$:-mcmse> - $<$:-mfp16-format=ieee> - $<$:-fno-builtin-printf> - $<$:-fno-builtin-sprintf> - $<$:--specs=nano.specs> - $<$:-g> - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - $<$:-fno-rtti> - $<$:-fno-exceptions> - $<$:-Wall> - $<$:-Wextra> - $<$:-Os> - $<$:-fdata-sections> - $<$:-ffunction-sections> - $<$:-fomit-frame-pointer> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - $<$:-mcmse> - $<$:-mfp16-format=ieee> - $<$:-fno-builtin-printf> - $<$:-fno-builtin-sprintf> - $<$:--specs=nano.specs> - $<$:-g> - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - "$<$:SHELL:-x assembler-with-cpp>" -) - -set(post_build_command ) -set_property(TARGET slc_locator_host PROPERTY C_STANDARD 99) -set_property(TARGET slc_locator_host PROPERTY CXX_STANDARD 11) -set_property(TARGET slc_locator_host PROPERTY CXX_EXTENSIONS OFF) - -target_link_options(slc_locator_host INTERFACE - -mcpu=cortex-m33 - -mthumb - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard - -T${CMAKE_CURRENT_LIST_DIR}/../autogen/linkerfile.ld - --specs=nano.specs - -Xlinker -Map=$/locator_host.map - -Wl,--gc-sections - -Wl,--no-warn-rwx-segments -) - -# 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93Dn0k14vjl2Pv+i3qB33M2/i1MwYVgbI/GEfQbGpAuNzmVjbJ3kqH3Cpy2pA+PuW674PYD4F680BjzDwy/p/CHIvi6JRhmGiSisXJ7ZOdjZrEUC++lGeQyfUcCNfreua8X4AYt4smqc5GwUeZFyrQDYS5A0HIcyGqh+/SWPVzPcIMHiN1rxxi4abhE/cgKkPr9JjNl/7MP9jMUgdtAD2E3DmG7HzVhId8nRDUrR4loixuiVO4cebEMfybgV/Bw+zOXLOwYqTKIucKLjmZWFOq7NLDSDsIWvHDTv2ua41Ksk6+q/SPCFAzJwo6b5yc8yc1kaQyQmqg+eiYixfdWOtYY3RErcD2fDGQ1ktjfwDQJbxvcM9g3mMBEMC/oUbrqGertkwPO11Q5Pwl9nEGgdurukU99zNYMC5FdwuABwrgGsJ92C53vF2xtDHwD4icrYT97OdeFcn7Ag8xGCyhmQs/+JznfNqgfYFu2a+6/GeNdbiaYAmS6KA+9W5a4iHGDhN1F1ePG19IGrdNYfs8dqnaM0bga15Mwi9I8tGjkJMl6N/yhMw5UYXKwLPW+nniE3hKyfiekuq0WJVKQwtSm31FRiyxT9e5SvIYg2ruS5vZU0VGNL12UgF4YukWsfATs9Wes4zN/o8G5icspL+Q4GFIF3GKfBS0o7fXtPqEOybLL1Tck38uCiFL53h8m+CFTsCqgnq/CJLm2CV5CNzrtNoJ2jwe3b2wUwRAzG+XB/d48S/ZEcGo7kP2iHxbHi4CFLk2cGKbZmOhPuSZdGpEDC4DehDXhwNekpkaMQIGNgid3dmb9ZuV5oKAfAGWp5SLM6smHqn03xl7vJQz7PvfZ4fjB/vf/75/mF+2C2fsx6enlZt1FLgfSvRvgSy7+OZzUVVPr5qc89Ax0qh1ZFyQ9BrPDdIm5WWIlsBkPn6XGRHL3P9BM/NTrIApqk88I6lFa3QlW8PRKgdiyEIsmlonHIM8VDiBZ6dehNDQu/Rk4Mu4zBujCS0QlmeeHhMtzyOOPn4oJGAWEBVVpqBpYmzs9duIniQrVLaHmhkXwm7r6TYj+Chuv2VRpz9cbrqBl9Hcvhnt02AD+GG3i502bVGh2Stwe96i9Ka94/e0c4DsJb4BrSRF/S+KaIeb7pBfxgXTFxFECT7tbCD//eDIH8DvxIN3Wm+EsHLcHQcvhs6+Q60+M47JrK0C0+SUn6Enw6SJBxFVdb8UDHA+1kUBc7Z9i9DInCTFtgVzLmcprtjAuT4HCWfdnES/dWDJaTgtctL9ATefwPfL1EBisA2r9FyP+2A2Tng3zz2kteFFe8sXZYEXVFEodPBvnO91En8GOrx99/tu3/Vjd3TdfHtd/sKYPHXq29fPb599+GXt2/ePv2n9fj0649v31vv3v/46y/3j69ev/qvv0OrCKNnDzTg66MdpN63QPW5H2T+5f7FCXLAFPzyX//dfv0Y5YlTfgsGkTyLQJ/aw0iy5RYVaL4dfwsGR0ggjNw8AIPY64+vvqtAvn73rvjym5cwuKSvq2+///jx46tzlsWv9/vPnz/Xqis2odP9h6oBPNgC8MlvKmTFa1mSl1/6bvF37uxKvrvUy/J4Z8dA99YB2AzU3K5rzTs4dsJXYzfs0fr9R6DLQuFg6A9yuC2RAsPLMi8pme7+N/x3Xz3XNEEt3e8LrVQogfyQ7j++pdV92fad+d+CMkFlf9v82J5ms8pv+j8fMvihbKeeKe3KX7rPuqHtJs9IMsXB4fKGr+sd8hPyoVHYeeKhkkL6OZp+4Nl3vCJKarmO62A9FwdXGLbPeUXuhtnHzscXLHjBteeKyEVVowP5RAisI/ky+etUXGPqhe4hqKlnOgc8pp4IPC8uTv5PPZEDDNBSSjDeC1q++qn2t80MEbnz9Q8O9RD88HRvwdkouniXLK2aoP4x8C+fvAQ6AbvA7f0CO2u9YzgY1Hs/nUc/FV3cLef2Zk+s/4xT47GAeu0gOo3JdDuRA5rhUzom4z1DEmf74gZleqprP484NEGV8gkE/dET0zQKnP4FzOsXB/Vgp1v5KQJr3RnQ+mp/7TDYUG958kJ4At/7mvsL1RHmb2nePy97/9qpXCZ0FuC5driRlkbngCcrUixQNYdnJyhh3YRY9u7oUgLidcy974Vv1hvR869dPVew8PXOIMhk/5OcTn/fGIMO420oQo4Ue48Ijs3lqjfvHt8+7t+AOWL/9lKMqHsnTP20mM/9dpJdTgBMFcTvdo6JLX0frlecUJYJ3g3j3LKT8NkgeDf7regh3stU32pe/rHwgnrBmfufHmTp3c+S0pBrIhtN2kOWJL2pLkRK8QB62dQEQUEzm7WghTSr1HgMKcK1KmuS4PHLMWJNNbStOtgUzfbqpcTjYGoqIiXpMW+qNpkVQ6JHMC6zbqomSRRTmj57mH5kxRFzlZ6P7FUKYzuMSVbpqFhStJmPJb5jO2ePMdFP3pfUsWdn54VU6xxVjEm+HGzWo11NFkZE/AvzybSTC4slVQ69KmDfq0LbDw7RC2uqsX0+sHdRqqxgLCk+s3b26pRWLEkmrE0eUATr8dPFDlhTBg6PnTnn2HZZE/b4mGrK3O9p0zixJcrePecx7uU8Bj4enmSdOYghyTrdDzuSvY12NqTDal+ACbUqzVaDl4poGUvepxlo7DzuEJ2JqWARHQKdoVmFEau409Ww4dQ7WRT6sxbWf6fNNo7/jnfJZ+fZ/hvwwE4+O/DXQdykqwE8rVXvwIHQDoKpuN/wreYQSY3z5DhgpvL80tYw8Y6olBvAdG9biXfCiI+NiNRBxBLCvBqK2p51ULJT3XPeS7n6snW2Z8MF1wnESXQC/pxlJ97souE6peaWLzkJGNsnoFA3xnNM0BLty1CZ5ThCR6anUipKhT4wKRSFY2tdFkVj7SzxZ52qydcXNedU1Vra94vgeeC9VMI0paOZ0GxqoF/+mtclnFkSHhQiZ0k6tE8XPwNjp5X+LQd2NuuTL2bAQtFVo9kuPTyW7V/RaspCMyFWlmVmQSpL7EsaRykzbCybdMkIPVfKGp6xYEWKgYnVw0Fgz+8T4RPz2dGKYhxnB4sWy6GpInn053cucGkxMdWK1sVjMrZX1KLjMfWYYWMzBPUrwy8iVfsa16bbJf7HNZqj6ZYx4a5NMyY9nm5ZM2Ch6M50y4gUS1ilrbMilh9YkWqnW0YEWTbp4gUAikhnumVFioGJ9aZbZsR8drTgdMuIFsuhqTvdMqLFxFT70y0jatV0y4gamyGoM90uIdUjUy7NZ16vYgLFjY960m+uf8xN9b2XK97tyzOcvdBNnruxRc+J5uN05VvlRZjirfLjotcg0uo1LIzw6IR/ybwkyeOsYNr7Bo93nwiE0CeChaQ6hl5gqD7jca9fhHzrF2c5Isr54r+AFfNG1+Rd8Mbs4g5ZVhf/hfntvSt1Z/FfwwrcIytOLnqhW9AE+8WqICP28xhHwSaqFi58hUTTWIe1kEX2sF/AOGmErEWH/QLO0Zupcm3Y72AclrhSzwz7tabCGPYbOCckUIW4sJ/vFMTFf2ehzc/H3VCVp/CfxzpDMFGbaeErRGPKcntcPkjg7NBPVRnGfgdnz36q5Pf8O3C2ridfrNm6eqGcSZe8ASEteh5OP0tegLPIkue9hYC8a7eC0K+Uc8GyNyZv06BfgHPBoufhXLDkhWIuWPRCNRcseQfOBUueLwf1JW8Ug/qiF5LZOEPv+WShOc1HavqPl6PnkleWN8NyCy+GwCUvFMPZzAs45alo3sd0I3BKgl17HyxPinM/nWvO7fp3dPN5BgwmMZzrJ7ikMO5wYJLCcNgxKeGc28ckhXNYGZPU5XneO0GRagIag1wX6ezRDVxqMCMGM2owbwYzYkV2DWbUAqbUivbEJFWnB6jtov4b1x6m3reSyWvj0zQqWRoMS2UYvF9gwKQRxnmzpRdjd3f4Vh1SjGcn0PqtpMjGUMW16khmt3NOPoCLa5pDhXaaA6YMbYqV5thj8w0uyhENn45IfS6ypbFcmBGN4jwa1noBm9qy+XeWHJ2o/oActt4Lj65p/HKpu8RGkQTiJHK8NAUrugxjpTkg1Z6LbbDgagVFYIAFk1TueoH9pRar/AtXjurdCkb17jK+vXeL699aWNxdf0STmS8gtOytpnoLwWvjojpLiXQLnCx99+pRS8wiMEte9QmVhaiKgvc6uvIV6bt1pS/E+4sykmK/vzhd5hRl/AzWCyi06aOXv7SM00SCcRwKGKmFGZCpkyuzIlWi8kP75FW5PC0/PAm7+HJC/iJO/iJN/iI3v3SyhW4mfVWTjOyx+POrTWG1GYW+KfYTKxofgBr/CF52/0ex1IqtkuoBOwVvnNL/0Si1Rv95jLTNF7hzkiYjqgOremxG27lTv387Nf83MiHyhx/fwWzI3/0B6OLjx28qp/P7j69EmNAZfONdnMgFnQ589evTT3fGx1d/AGwhX8C44gseq2u3YOcThbTB67EH5utHB/y3rHJbkHvVcAAPgf+v8rG3bMpGHj038XSd0Bf5dP2OD4ykeeNKVmDwUOEa2pnnfl81GfyySCgKvykMuGwcBLYmRzkSeA/EtTxmndyxlID6PBEZlZnSTyeS/zJnMp0omSmrcSpfrpL0UzmzZjWVo5o1n2tZklnzmsj8zL6Vxpm7mfJAZjNnLQUywTVPgx4kCWfNapRFnCmDUVZ4nprqZ2dn3vCo3Oc8xTlzbPgrKflJ+UxM299VSQ4+2NkZ/FkWFkmz3PWj17VPtq99lRFN/Jf3tfPR0ujUuqi++YafDzed5ZrKi6v89kk3bjQ/ddOyg18aD7xtyHHrYk9+3cTuzIkjU8Mz5TLOds9aCGTuetZM0NnvWXMZJcjny4CDBKgM/dx58JRjXEeANatxJQKmHAYVJVijH9ZJ4EefQRPQzJfNrHCTyW4uJk414RXbA3jT3WhH4uPYS2lUSF3LbGIXBMt2RjskqyIViZBKN0AqESGVb4BURiOd6tRDKx/szuFG6eqjBzNxusFbZRa5q+9MvNnRFsbrE0SajHXYJKbQFAHthVTQYzkiZ94186nHX9Bg7fEP0uR8aOtehh+VSJCPAChOyyS4Gs/FbvwqLyOL1p/OQclWhfM5LxmYwri+A2chGj5swTfOFF/sJRum0JuSFbzBN4xYwy8vRqwAv2TEFH51YY03+IoNU+j1lQve2Gs+bMG3tUW4429ZsRVhVMiEuyQjjmwFqi7ecBej4sMUvLdOR/Y4dOQ2TQB39A0npgI0tWd4428YMYXfZE7gDb9hxBi+v4ryaz7MwTe1e9aQoGHGVIymVBBvERpGjOG/rIT+hT34KisJb+wVG7bQ7XVcuJoPW/BNSSfu8BtOTAXolI/iLUGHFVMR6oQ5vPHXfJiDr6tirSFAzYuLEN0aXGsJ0+XJVqg2rRJ3WVpWbEVYa0YOuMzIwUozcsBjRu4UpOKNv8OKrQidQm3cZejwYitEuop3UbFhC/15lWB0xYYp9DqNG2/sNR+24JNVZrCKDWvo3dp9K4jQZcdUlH6xQN6S9LmxFcRbcS7oMWMrxjrBxZRDcLFNmMgdfcOJtQAr7TC1nJgKsJorzceRzlfzpHM+rvRq0XU+wfU62Sdv9DUfpuDrJKK8wdd8WIDv1gHlhLvLgsV5HkSxUT7IUZy4HufBfhzjQZxHxtdgYb4BksNv/sVZcOhteFa4LZK6uCGnqq3ithPiqH1VSZUSSk2GHEibep9WKw0hcjBtantKMC0hcjBt6VpKMC2heTD4nXPYOdKEqnM0NXdJhR0V76XQfKeYLyWcLime2m/q8JKfyl3SgFOaa6v/kurtSkFh7AZdOB/RDPPXFdGppUyvjzoj5pDywsl6qs3YY2QBblwXmxnIMWnmBsbJg3nz7vHtI4kD8wamYSEeIMgOXA/a1AlTPy1uRfoB4Rq6EH8PZWmc2DFVKsMryXVyCbLD2CFKBTH7rcg54b2Q+U4IfH2KDPQHM10y1V1FkA4avOHuhLLMDFqXIBW0MM6LJKFkFw8Q0HoEv5bBrcx0QzK6FXkLbuv/9OrJLW7C2Qp1X5MH1KvLR6eKJk1+h+LXYs5VSmAye25u9ZNbNZumRJWYWNymi4tY0DqPqGoWvFCTXamYz1zFFTPRqf3ZlDs8IRMd1p/PqsMTMtkJ2fkUUDwxk50huo65rmzCC3NNf61Jko2/MMi4V9YdYaKi6xVhWI9TvJG3LBiPVpyBtxxYj1mcgXdYsB65OCMP+CCvK/nwgl3Tv4VnOzHE1XmGbruo6pYgIlb+tbpGtFYyrHHEHGRN+Gta/3WLV9ErBFERi2mr8QBZE95Qhw7j/MYbRGVlLmJdj4t8fU19oqpmRiV9vzDahmxrsozZbS3uanU14pagK+r2Ndns1fp3HPSHU3ZvQ1ZfHp+6rYkPiqwRN8rV0m200+1kITe2cMf0v6bONijdR6sadEFAPi3JHO6Y/pa6fZP0/cZdv1dfk7wBZgp3UpvMVNFNLogHPBiDb+qP8sPesGAMna+h9FlQQkeVQmWHGkX9q5oneqV5WegFWTiYYRuyxTmkvKGZoaz2ettZoa1WS6zyqfK3tCMSshguU5QD2l9Tt24rFNNqZFTy+Gs5L+GFbvJMdFqiKCxzw35XAiDqdIXQ+5JAYcwtra/GfCvIJLbbEx9abktrQwM79r0hXhr2nIjwCHSp4M6tkIbUhvQLU7k1EZ8b9uMeDoru3KNT9OoR5a+mc/eRk5tgXyfQEkeUN2SRVXWPG9pihYDCCisKhf11qH01lldjJre5WgPQ2jrUvhaHCF5qyDOyA6S4R6kn3g+fY9oKDct7ANIK4IbXc0x6rwzqrz5RDMg0G4glRRa3tQtiMGJ5gvsWduLZ7LGOyLMDnmd+wAFwTZYdUBhhKm6qc0Dbo32LghbLx8prfYXwqtxQQfV2M7OsWihjZo51RJ4d8OxLTJgS8jrihi7jbs0eaU2WabfmgHNhXJeoK69xZgfWfbvtoR2AAP6T+C9U4y6k04y4fZpfjT86gE5jtYU6anvt06S+0w3J0Y9UI4SLByna9tqWC1o0Egt/qVBs1/8YUmY0ttZkId/Ae6kszArzgDjXxnX8E4w4iVMdC3Kiy1/zEyy1zFUmFDe+grlRBj0ZN3c4NxeaH1/h+BvhgBFncezTxQdwPSv9Ww7cTncd2VBcGQta9WXb5SRSnz4f8Gl+4Aq+os8HPL+ewneYrqhz7+9oPpwMybEDTvPMkAMfAbLEvqRxlPIVoseFsSBVO9sH4gRd10Xo0+cEntdg2qfPB7wT2CFdMHYOfsOBlwA+b/w+T/hRTJxjDQ9+xYAPfO5e7SrebMUEPMBpKThgwAc+v0mZ72xcUb94/JZ9IxZ8RIiOx9Tj2wYtCz4icPSJhhw4CcBrddCn/5VvKlVC0UcUu3H6DlHGbUu9+zGFlfUGyLXYGRf8E4zWCtJxlQnFbb0g3RqiDfitEKRbQ6p1jHAcLltFNhRXfkE6LiL16fML0vEEX9HnGKTjiZ5TD0EEz3hKwbe790JoXE2p5sA7SMdTiB4XfkE6LiL06fML0nEFz2Uw7YXQeMJvOHAM0vHF7/OED2NoXOFXDPgH6XhKwdeb7cbQeEpRM+AYpOMJn9Ns3I+g8RSgZcE1SMdThJYFzyAdTwl4+USdIBpX+CSrg6+s9pkXBv6B5CoJRXUnL7Rsh3C/sMBbRFU7VAgLOwEK5Kk7ekAWp+cYI3FCsjx4PRwVEQoUUUIWt+/DqKiQ43APJ3oYFRFyFB6LNvFo28Qra47SA2nokGM5xU7CoL80ZGiQ+GQ1NQZA/GV1NEY4fImBPioiFChslwWMigo5jsANyS669XDUVChweOSZjfpQvMX5i8ZowpRB41REyFFEMekhnR6Ohgw5kti5MBjPaioUOBKyA2N9GMmiU2FjFAmLWSahnWUIj//1QCw73IfAUOT5Y4CjoUOOhdH4wWD0YDT9M5j9i/Lh1EBqKuQ4ikrg1DhqKvM4KPLlLzhsMbFKIstzAOUs8rq0VGhXSdRAGjIU65MzYQi4B6SmQrdao4exrHQREkWxs2yTZmDpg+nQIsQE8/Ax0U6fELmGKIqJ9/sQbS3xwvzJdr4GfWjZbUvECp+4onnfXmgLmkOnxQ6P+YXByNIhRDG7UVR37aEhqOg6EYlh0ErJsqxeSBzWybt4CWGxrhGeLjW6CBE1nIoIXYSIGsXCEnaTESJ6IA0dWizMpqUROdrYFTWihgxl7IoBEH9Z4VNk7IoaRkWEMnZFD8NeVm5zInZFjaOmQh+7oofiLU+HjIxdUSOpiFChYDak9GnRxtOo4TRkKONp1EBqKnTxNHoYCaWHm7CYkxPaOZnwpF4PxLJzeAgMLDSRUmviS+ocGThrLR3qCCMLLBUdWizsfOsxPdroJzUkBvMPI9eWgWdbxC3pF4cVFcroJzWOmgqT6CfJyZMYWGl89hI7WPn4ScuYpuxMS6WIJyOJbjSyPMZKYk0dBUCTQhIlNPIRLRrfbw7nIl+Qti9c/3HYxnZ8PdcZeUb6cWbrzMfph9NAqxApXS69ls6SpgZv1ansoRj7lsq+T5A2iR5zeCOaX0sO6kOQe1kUYeWhZF434eLE1snOKG0N6L4mtGQCgK3ZSF+3a01oPyBKa3ANrYXmhgeQh71dabJzlBaBPCbNVhNj0nQ1sT2COIsmbOixaMZJsCs2Z+rD66xMGrMltfygA1JHLcH9BHnaJu3QTKJDnnLE3NJnB5raCqfQsphix7LzQtuhv7lZd5mbGCdRFjnRdf+N7RROsfwCjXDI2pHLjv1F669K1k47VylWEESJTzF0iTFHt+GVIQR6gspbstAay1zdp2lIUbUDOzgNLVo81ZLRP/iBny270zmDbkyZCuvyhN/X8C3P9T0+HcSwQX1WLUpy8OOanujPfwwGDFbAugTp2hCuH9yD5XpHdk3Zp7m1WMzZTtzPduItnGQj8NoNJljItizvvmD2qkXcF683M1ePFoVBF3Sc6JIlUbD4+s41bEOaG55cu3iX9JyB+HWXHpKjbZ2ilRnBqmndbIMBu9gZIkB1OfqnPAETcXSxIkDFSj9Hty254kSL7qo0LVNVwkGLVPejivha4QMWNVcgZBJLva6PyoIr4rdYF06oLHyRVOsY2OnZSs955kafKQKoJPY4JBFYCEhljIVVeskxfZoegCDXZOeckmTiR+6pO2/RwbbRwBRdGtXAdWaHpQ38T5P2YZmTO7sLOHojO/tgro+BKr+QzLRx4l+y4w1nVh8shxLPhsfOIJIlA0yxmdeRf1+SKAYVBNmvZnIdYl/QJadUArshgiw3lfRPEzBrWYLGREJhoNElSiT3OlLvdKKpF1weSXv2vc+009Hj/c8/3z+wmHhKStbD0xOVSZSq2bcS7kvC+z59BpmPSoJURjMDllGKpo7kHMHW9P855uepjuMHPliiWIF9SEnmVTt6Ie+1LJZnSRbAdIqHpdHewhq60u+BKLUbNyS61pSKlyLrKonECzw7vR49xCZ2cshS+E8ZSxJaoSxTkJzCWR5FpiaMNDLQKMA0rDQDS3hnZ9OaGDwaWzXSHuh3XyllX8mwH7EjGTApjJIpAbJKEhsdQid+nPq6b0XAI3VDbxe61+0HvvR6/+b1/rG0m1+g2Zz8bO96z6n1m3dIbMuObCuIHBumDowjYDHVZ7jjsu/wGRrOd2B0C3LX+2Bn55HBxkn0V8/JgBk6nyILmK+l7JSd2B5v/dF79h2vh+v+pwdZevezpOzflpQZ8Zw+yMhaqIpLMRGxoYzceWJEfBwFZ62PN+8e3z7u30SAB9smxQ+LshapYuh6h/zEgz4wy6JjuEX/KHYjeLDxQjd53ruhDf/DgT66oD0fKdj3utHNEz7A4cYfWA57SZLHXFq5NqY6hsGzpYustLzpc7KjWk+AE4/xlSLQy3AKnDxczZtHe4Cabav1b8gwoj4RuOJLnadNJ3ZoNYNMnSKa8bQyufrlpbapWAtPU+4eHufiNgJugXO2fS5TWW0Opcq4cgg8Ly5u0PKbOXNgBZw8l1oMQCCwv0xwCG0niX70jrAfAY+zXZc1a5g/SpLwk6jK2tt3irGEwv/94eHHv/zwcG/98T34ZP14/9MPv/7yZD38ZP3xhz/9aEmKIFCQe/z1w4f3D0+PllhTZEGMGNxP//He+unh/v8VS9ZnG3Q58K1sCsX/llB6/KXC9Kcf3t33qP2vv+VR9n/++PCjIhr6m/IvIsoP939GEP5BEIlovnn/7sP7P93/6cl688PTD7+8/9n68HD/CP5eQufh6cn69fHe+uHxXQ/aMtU14Wnr8f7N09v3f0KI2T40KS1wlRM7+fJTP6Sauc7vfjf7NKNoBd68RB0yQ4taRDfxHsV+EDXVIB+8RGBgRzwM55T3cdXg8I+3MEzUfrvLnV0z7xTtHhXfX3ts58R5z0ScKMm8l7siFrsOguMAwTF+Vu/SeDX2QWRnln3weyDOxZlZIgRwkQPaM7kOoH5qFyeeX8dT0LFF+OIvfpo1jGuQYLEBDNVqKaA2JL7bt4xJxIHRtfAwK0/z2OYFKgKsM9KUz1T/eXTA2iTrmce/1K6HnWcRGGv25ZNw0NsFKxkOzDZZhMhSr/hv2kOYJTkqQMcBh2tnNnMMCxrpYl8iy7HAUHorDUShn1lHsDjzwDRWrM9uBAQowntxvPiW5gAwJFnm38AQijnfzrx3dlxMqLeR34HOxsUt5o/uvGqaK/F/eZlA8LvfieI6GD7bycW/nNKdHQQ3aoYGgveSJfatQcSea18y3+k7OuUG37oNkniWlyRRkt4KCnwi9H8rdnd6GFL/N3wIof3JK2Zb4PDvgM+wy+zk5GVDDBOPjbzeuxB88z2B70uJIzvn4WGApPpuHQBD5/suBN98X7ngd66orQYE6YYDOPD7O/D994tc8hGbdnycRdQ+OjWY34Gl8PdLRvQrPGB+JWxAcTw9vpegFg3yjGGhpv674yW6K7+9GagJn6iA1v1tXduqx2RrOEne/aX4Zn118UdEpJ/xDH73l+q7G+qIK6olepqcUO/eM7HppRrijWeJbqbXpndH+Ntd+9v6iloV3BKtXY8s3B3r32+qvZuAXNQvr0cF7o7wgbvigbvmgRt019vAXKLJ7UUUGer/KxBuMgQ8/eTXIBY6tDTx2HQsmC4ETImqCH6OQp93YPHmOen38Ndd8XEtPHUMzir/tkI77iP7j4rex2/u3tnx9//yr+9/ffrw65P149uHf9v/y79+eHj/7/dvnuDO77/tipcxcZdnAnY+sJYqNj+EXJ3CjOK+V+IdE1kKT5JykCThCHf5/RC5y79wJBhpzE+nbiFMd4W70AlRgZn5946xqN3BQxB29r3veSQ04PLokPtB5l/upk5OLSKSElPBsOdZGicWgwhMMZj6cPu5MLXUl6Wy1d0MmOvFPnkulNYtNhh3p0u+6wz3B7s60N8xiw7BwdPlQztoN7soO3tJAMT6Hwu6oQVN3qW8hj700hSYxV3gXU7Z+XvUcY41rBBGQ5bYYff5fwJL/Kdqft9Odt7nuJhypqabt/cwFvG+Dm0t1he6rciwQpzwi+rESW1Wzyo82DMEfuWFyg5t1y2OPdnBr6mX3F7ExgUo8tpx8AHWsX9+HjWR1H8Jvr27OzlXlu94JMDsAWN2d8nnF0DrFHqXjI/w06skIvlfwB8NybvPfna+K9aWt/FhKvd+ZuZYSs7xEycP7MT1Yu/iehfnC/lG7XakuoBhwB2tyZZtsZLN8Oj+R0PrK2mi9tl6kgjcY2CfCKYFroMGVVNgum1dLdxIB9/VR/Obb7757g8vYQB5lIlpARdxJxTSAJuKXP9yAl/9+vTTHVh6/6ElVK/l2/RQzi6M3ByMu6mX5fHuTXHf4kP52AfQ8/5Y6K97lHhXnOYFJACx2EuyL48O+O/3RdLyMlAwlCkGbxXt8Jh58e+BNL2/byCl6x3tPMgevSwrjnEsE2/PHyBlA6yAMHcqjJS2McpcUYb/pjpZ/6r/zklgsSd4wRl+LDhXa9tmMAVf1VE0d3qEHWYWWNEY7dh2PlmH7E0pxw3VCW88Wu5hR6HIq3TPDBuo+hrnPlOjg/2V5n317avHt+8+/PL2zdun/7Qen3798e1768PD+w/3D09v7x9fvX7194+vum3z8dXrj+C7j4Cf/eyBoSxyPv3ZTnwbOJgp/Po1/Ac+AP8HZpbYB0+5n36BNIoJovzhdf1hcEOj/vrb+gO83vc+Hr83EXGtfv1H+Q8g8+rHctT7yoD/A7RMiQGeQk1BQ/zX36s8NNBiAL3CFfy26RSFLUAZy4Fhf8jgh31hhL1kCLvyl0I3UeKffLAEbl4uvq26OvhC/Lagl4FZG/4lCbokSIIs/ePbARhovtNY4H1mL4ySL/WodSbgbiqGoCimYBIwn7pMTYPnTpJUw5Q03VgOqJPLwXId16HCYSqSqAAcBIrp4giOLxENDmAXii6Cf5ZaR5lzgkoFoqAbqiAIkryQd3VtlI65KRuyZIricv33075TgdBMTZRUQVuqAYCiVkLZJbyXmAaJLommqIFhYjmObmoAup4p6LKhqKpC0CRFHheYK4YGgSxrmgbGB4GuS3phToNCkRRZExVdXY6iU12KAoCoG4ouq7Ku0enhTDk03ZmyogqGuHSkbvNCUWlBVWTFUMylPaLINQMYJ15llHQYJFOVTUUnsIXm+j7dCKXIpqYqGr73UJ+JgANlnXsBeunLpRdMXRcNU8HuCUjWJGIbiiCopoE9EHQZF5NDtWhv6pYsH4skMDEoprpY9oene+tNFMbRBQZtyCYDoHIwGyjYrklH/M4Q5KcJkejAL5A00O01A3sA6gCop0VizRu6rpumIJIYfMscHtN3PDL9A7dAVQEGTRy3wNT6wQ/tk1el+bP88CTs4suJhLemK6KsgaGXmLVIyBqMtQJYK6hjXwiXs0TKWZTBOCNRyCyTqlvUDFVWJUMZz3JTvMlyMT5GedLkjbGa5SxRF9EERTYMQxz3Tz6YM9Ct8pgS9J2hqcCx0WV8+6LKerlHhwzIRgRDEiVRVhHTAWfslu2EMeHK0jSBXYNV7vqYiQdeQRM1URdk3r1xjPmQJ3ZI5iUqEvAUDFnl3R2RoDOH1KJ14NwbiEUGb9BOmBNCVhUDLFIR60PekGG0idSV0Azd1A3tBqDB45djRGbTpmKKwBngPsUgYIc2gJ4Wh72jhAi9Zqq6oJvi+qO1GwcBYfRFFBUduNzm+qA90g5pAuNWNEVf37a9spo7UXxHNwxTBu796qCPaeKQdcc7xRAV1dCN1X0n6xQ7CenYJ8kmWMtpNxj7ilqgRAOfIciaIIry+uYBMVtxRGjWd7og6Yqg36Azno/Edi1roqCC5fZ4sc8f9AshZlEGqwFdlRGBUd6gfYmsK8qmIYBFLiKmzR2xTeg56ZoEnD1ZHm9GcIfs2M7ZI9OzYpgSWCWu7zV98r6kjn0hdPYMRTHB+LG+QQfA2yPshcBZEoBjra5vIBD0y8Em803vZEWUNLhivBluGB33L4RrdNHUwZBtGDcIKwResZ9C5vUBzKoh3WBaD8hnR0VWFEED5nID0MSzo6LLYEABZrI66ND2g0P0QmbWGjBpWRURO/DcYcf2+UAafALzjaRIwLTXh52STewArQ48PsSuInfEz2SR1DsJLL+Av2eu71rHzoVwOQCmdEMQdXH9FWOcEEZ/TUkzFNFAbPuuANlK/ROASgjdAHOiJMo3CJelDuDknGPbJT31o5omXPOuP4KkHs2ILYMlmKDJ8vrjSEoaLxN1XQcjiYE49MYdM1geHAmPkIqCKIHF2A0M5EtKur8hwt0NVRHM9cc/cif1zlBNWdEEaX3fOqdwU+EpSk1QVWn9gZs8DHwnGoosCyZwV1dH/ezahFYtG9CzvoF9fHYj0jN0hiiBSV1bbcwLq1OQZGEn2VQU2UAcC+eDdnQehHBiEcG8AkYOBrDbMoDwRJWdRaFPGv8HDQ9cfWXBMSpMVN4lJ1su6ZpuCIImMPDTBnoqDrySHoUXASJDZBGe7aMq/yINCoLRRgArNdagYEGYnDD4JMmSJqkii3M4dTmypNt+ZOclNUEUYPSAwbDcRwW9NjsAixISXBJwJMAKEHHThhRVkxekxlfeTyJCpyuSrqq6xgNdXQ2yvD2VeCeftBMoAkDI5HDgdZCE8UEwcGiSbrCzuxG8cTbA5XYo6KBrgCUEg2lgXAl574Spn1pNohqiZoaBElETWSzfJxFWzEmnCE0E05bMwsVGIMx+K65TeS+kM5immjrwpDUG0dNJBcJkDUTrV01VNUlmcbAGhQ3eNHFCWSbUHBgCwRpEMhiEyxHowji37CR8Jjz2KoL1qGroMosdiF7F72r+aK6NkU1wwEERBd00GFjdsB55Hx1RfMrUVUFhcsByopj58MKXE0TOJ9KTt9CJUXSFxX47JlzyQ5WyqBu6ILOI7WBiJT4iB9QqGKapsNg7wMRKfLJF1AVTMUxVWM8GiPcZFd2QVBl1OZEX1Msz8TpYVwRVVRUWbiQKbDOYDq7HpxLZ7RJJN6FuGcyXmGjhjV1CsIamKoams9htxgRbXKslRCsBLxh4w5rJqYch4AYUcMH8qmmGKbDYG8KEW/QystuqoiyrwI1n4AzUWIH31Kx045zsHqmqAf9EZRHa6aKqF48x6bQExqTiqj3DaSmxQ6uoUZDkcQaWOw7MftNt58kHyBoc3pKXFY3FAbB5ESqFT4tA0gyaosiKrrNYNQ3q0rfxIxhdJtbxHTwIreuihEiQwRYioOJ4aWrZRcZRwhFAEDVNFhdcYMXFWkcuO+okCycZoiwCk2U4GiARDrRJ5GAZYGoFwwTD3tWmRGgav/mGqMUV2ZBkXWDa4FcwWmc7qPekyXqTaZqqqYmIi/X8AJd3BIk6lKmA6dREpJ7gh5bcGIB2FUHQ4WVMjnj9AWDSy16yLGqywOIQHAJqPRi0vYvMSZBhGhyVxc7tJEifFqUpwrCjwuIYUA0yd73A/lIbaPkX2fgE1qfQR+ELrQjwaWERH30kWZSYKrzCzDJQVcGs7LDSIJENqoosS6rIYgzyQjd5rvKmFRosP5INNqqga6Yqsbjp0cMFVVbhIuuzhi7pYBnEIjZWAuts3npORLgHBG95KQIMw7OCBW/LNZ540Zy9bwjXu4JuyLrK4hA4CiXUYR8lkS5V2YQ7p6wwVklzCh1WnwkXZMDuYAYZZtqrkUG91ciI5ghdNxRFNxkMxEV6sUJVwM0md63uVHjJVFRZeII9SDC5Apn3JJkwNwvQE2tEUeIRup+GCkxKY3HwtIfII9WRKqiSpukSA1+jD6g8xkg2ZGmmrppL8kXhYSpuUBMhUjTQZKLE4kpKD1FxV5Co3SQwKCm6wF5J8A4MWXY5UwJzDYvNth4eePWCsPfDVEG6yOKoXg9RGZAgC5YLCrwoKWkMYvs9TBRrTOiJylBRjCGRDwBwj14RgJ5YhHJLTIWrF1IkF4KZE0VNUXVm/a2C5Jx9witcoqKohsJkd6CPiDh3iq6p8IglM0tqARWHoWxC51ITDENSTXajd73Op1BWES6B2WBZtx7NqV1dMyRJMZg34IHwbOydDpdYpsziNGDfoigOEavAE5BljcX5oR6mxA5hkXHSw3SGpilw84UxKpojfpJgSIamyixuPw6aLyFbs9+JYMVkiILC4ozuCJJVkCM8UgEvlciCyuSSeQ8Z+TkfXRIFmKCJmQNVI6K54gT8J0OXZIMPKJp55g5mu1c1QzBYj5/EqZ/gGThDAEOowHoEJc5yIuqKDpwplbWZk97dvwMGLqgyk1vlQ0BU1mSYoqCLBvN5hvQuuyjBI39ghGI9dFLc4wUrBVk2NXhnmj0ouMgjdMwlUxNllcVxMwQoqmnmDqz1TKA1gTU2mk05Q9EluN/F2k8gn2dMU5JVYO4MbD0GbRWfwftBsTJu/6TZd4dlHDRZN1gEWzsAod7GAMmGVR0eEWZyfXMOIO0wq8FDAeT9wY7jekcpz/ygUyyk85H4TJsu6aYokXsUV9DBO4K0AAUFLM8EgSL1KATYlNaoocIKQLBiWV0NCH4miyXpArxdSbOmxQdIFjURDdOQNYrJYhJgXUNpWFOJNKBq6CLwAHiochIp0bpTUyVFNyk7zQhnW4dkUJWEJtIJXDwwRlLcI1wGNYkOeUp8J1hTdVGVKC7sLQJLljxMMgXdoDiMTqRPEqTwyLypazTBtiTKIicKOnirUzSHrO1FduyTuRiSJJmyrtLsVeIAJLvQARw0XdNoMjaOsVVnew4nqDKiJZKiqbIGFEexGpmGVTYlkanJmiYAL5vCF5uBVblg/sEP/IzwXJQkiAJwdWSBIjRwDWb2JSZMECqLoqbrAqKKIDUwn6Zd7xRJMRWaHA3X9EV1u7vIc6yCJQDFAuUauGb0INt8ERQV4ENU4mPToNAbdA8wKS1xmFo0VIHi4MrZTtzPduLti+JxzbBbVJIjvzshm7IpyhKieCALXJARLH9KfE7jTpQ1eNSNIgA7wFcbXBcfcfJKXQGzKfkYfA0a8f0NWZVg8QiVAazqvrnTrTFtReAreN+8bmknIj3OIYCJQVIMcm8EE2iTZ4j02jnQpqiZBkWWoSFSRNnq5hLfVEXriR8J+70EM0xReFs4EtUXAJdKRNJKCpg1YSthC1TW5duFLmGAU5BMXRawazLXBSCLqu3ugfDymKRqsqThV4IeciXygQ3TNAQRdeB4vtil9wyIWGf74pLmvVENQ4aZjUnqfPrAnwDtHFYAyPq/JGiiIaKSbhMAIOqsCty1FWRESG4BguLmMl3NUc2UFEExEXdtrlcafrz/+ef7B+vh6cl6A74h3Sc2Td3QNZrFxPAKSK2ceuyt/yac0BTRkBUTVYuYOUIrIQyfwix+qg5TcnEAWQ34jRqJhhtdEVWJaS6SKXyFEokwaqqowoML5CCL0H129oGrF4Op8AsAezrBG3zFjuCz732uuk2n9xCeUAXrDlmhCWEsxUp4XAbO4GB0Ie/fRDolwgrcVlMWFYpI2ghrnPiX7Fj088Y+y+9Ib5qCGVtWaQ77TGGE3WiIkUiNMuhBuqIg5nZaiFSaU4qy6jRhqxlYRG4I3B+GOaUWTr4wd0nhosPSElb5JWleZ80UVJVFXhgYXMyzdvHwHDfLn+eYLFUn8BNVWWJxdvoqOJi24AQzbIC1D9lND7jJr8gKi5Qg15FCIyS8i6JLsLg8Cx/hOkR4m75IK024HpLBsk+VGWXaHeKsl6+kFVnApGsqos4ip+NVdH2TJHOuVUmCFdYYOF3XoZKH7EVN0cGYzCLv23WIRbch1KIsSJquszgmdh0jeVIHQQSDuCmxuHpdQwztNpAPP9M0MnD/RF03WRww78GrxxwID/yT+C+kQUt4DNBUGaUzRuuvAkhmg4ppwHyOFD4VGmB35C5A0swwEtxzUIEdsklafR0lfCDwXiq1WmEeEG6WGPD8mybLrI3zGugqfRdA8df8BLiR3r8DLq0B4+3rQ3ejDM5Qbu6QqR3eWRBFk8nRzaXYyW1FVMC625BZFMNeDNo+Xfwsdz0r/VsOfAKX8LSIqimiqrK42TorQdU1bZcMq6HrogkWSAzn3TmoaU4Ww5dFAZ70ZejFzCGlsGHDkMFKQGdx/QUXLXXHM03oyOqM6pTg2YJjB2QDsw46mCDpLC7z4ILNEvuSxlFKOJMYmmCqCmoLij3iyhbsA+G+iaxKcPOIRRYabKyEI5gI14nAaWORIgwXqxPYIVmwxZAUUxIkliGMebA+GVYYypM0RWZUdgoPbBSTJWMDQ66gG4Yky2s4O4wcNF2FCdBUbcVudvQDsoWHCFwaQTUNfQ0fnnouAwOYIIApYsVB4eIRrzIk6PNKMJf0enCj4zH1CLUrKTKYec1V1kQVXHJP4U4UBJjZSaI5f7kYLqGTC2+aa4phaiwDig3YXqiENDgraoak6wrN8TNshDQhRUk0dFigkMcQMISJCpSQnZgBXpepSauCHgVKyOKPggSztbO4zL4UeXcaJrMVA16cNrjMwzPYyU0FGDhwzjQu8/Ec6FGchEQCU1LAGplJUrJZATphEiLrFuABfkNikWoDFyucQkiw6rohiSaTdJi4UImN+E4FRqxB72c9sPQdT1RhDkQWlaWxbaHwfkjQwko/OkwZvB7YNk5CpF6wgoP3xtaYATthErKNVVWQYQR1RaiEA9gdWGLoYII2WO6pz4EtwyRk460mgHWxwfJQyjxawuyDIty91jWTRX1RbLAwTkICVtNVU9BMeQ03jZl7ZmrAS1BM5lvvV0AXcRLC9ZEmq8AvY1RWGAst+QSsaWC5ISssqmrggq0CJWTrI00zDFHjEpiegFsFSkjgGroC99e4hKYn0JJ7CvBek6YaBstzQrNoCX3cO7Dw0YDXiDgvNHOxI/Avn7wE9G5vF5BdYFLAOlFXRdpT4akf+ICsFQDvY29HL00NsiyAU9GB/Ca0KAq6oqo0dajQCGE6qcQLPDv19ifH2dtJaIWyvK+ScMHfwWNWmtmZ7+xsoiCzLJm6ILEpCNLJwGw7hBs2ogn3x4G7zzorvHs4keYegUeJNSZ7y4Oc8E5CloILXrESdBFxp48OkS8R1l+QwECmSUym4D4g2yVEpIiGopo6uxSGddp8jzzfOTzxBlZbksg6BXsUk+6PqsAXEURG9W26qfOdC3GqH3iACkBi3XIJaZ0KRZQ1xZDZZcetk/kTFvIQTMNQTIVdGsUKz7Nrk1bik2UFjEkGu6T5FaTPbkQ2amsCTAYvMc/eXcxrRHEhQzQE1WA30VaA4LRGFAwWTd2QJJU1nnJSI1zWC7LAPBcunNOI3DpdMkWFfR2IYkojXOgqiiyqksg6x3M9pxHu5YgCQCbprLNil5Ma4V6kaZiSzKQybD+BMZzWyOKBAvCzVV1icSm8n7ufMMe6Kutg6jcpko9OJAomTY+vwOOmhsYiqtcHRKggUVN1HeZSZm3YxTxLqCPFVBWqlDloSMU8S6QkRdZNQ0XEMOYTPsCgRXSBWTccO7MDQgQSGH7AKI2I+cwjcD14675MOOEEkfOJNEGQCTMq6gZiibg08QhZ1TJJFjQwN4znqhn2OzBZ1zdtwUci2YFBqpouIQ7QzF/37ejfjYOA5tKvIsICoiKLw5N1NoYOvDpaNERMev1OMYHZmiyWFCiw1SGpkXpTsturYD5VBEVSVLBw/e9X//j/EgNTzQ===END_SIMPLICITY_STUDIO_METADATA +set(SDK_PATH "C:/Users/tilaczko/SimplicityStudio/SDKs/gecko_sdk_2") +set(COPIED_SDK_PATH "gecko_sdk_4.4.1") + +add_library(slc_locator_host OBJECT + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_gatt/sl_ncp_gatt.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_host_com/sl_ncp_host_com.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_robust.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_usart.c" + "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_control_gpio.c" + "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_init.c" + "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/src/sl_cos.c" + "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c" + "../${COPIED_SDK_PATH}/platform/common/src/sl_assert.c" + "../${COPIED_SDK_PATH}/platform/common/src/sl_syscalls.c" + "../${COPIED_SDK_PATH}/platform/common/toolchain/src/sl_memory.c" + "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp.c" + "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_hal_efr32.c" + "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_program_area.c" + "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/src/sl_mvp_util.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_matrix_mult.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_conjugate.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_dot_product.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_magnitude_squared.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_complex_vector_mult.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_add.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_mult.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_scale.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_sub.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_transpose.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_matrix_vector_mult.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_util.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_abs.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_add.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_clamp.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_clip.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_copy.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_dot_product.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_fill.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_mult.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_negate.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_offset.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_scale.c" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/src/sl_math_mvp_vector_sub.c" + "../${COPIED_SDK_PATH}/platform/compute/math/src/sl_math_matrix.c" + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Source/startup_efr32mg24.c" + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Source/system_efr32mg24.c" + "../${COPIED_SDK_PATH}/platform/driver/debug/src/sl_debug_swo.c" + "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/src/dmadrv.c" + "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c" + "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/src/uartdrv.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_acmp.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_burtc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_cmu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_core.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_dbg.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_emu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_eusart.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpcrc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpio.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_i2c.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_iadc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_ldma.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_letimer.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_msc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_opamp.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_pcnt.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_prs.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_rmu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_se.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_system.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_timer.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_usart.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_vdac.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_wdog.c" + "../${COPIED_SDK_PATH}/platform/peripheral/src/peripheral_sysrtc.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dcdc_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dpll_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_emu_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_hfxo_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfxo_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_nvic.c" + "../${COPIED_SDK_PATH}/platform/service/iostream/src/sl_iostream.c" + "../${COPIED_SDK_PATH}/platform/service/iostream/src/sl_iostream_rtt.c" + "../${COPIED_SDK_PATH}/platform/service/mpu/src/sl_mpu.c" + "../${COPIED_SDK_PATH}/platform/service/ram_interrupt_vector_init/src/sl_ram_interrupt_vector_init.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_sysrtc.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c" + "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_init.c" + "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_process_action.c" + "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay.c" + "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_ncp_host.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_ncp_host_api.c" + "../${COPIED_SDK_PATH}/util/third_party/printf/printf.c" + "../${COPIED_SDK_PATH}/util/third_party/printf/src/iostream_printf.c" + "../${COPIED_SDK_PATH}/util/third_party/segger/systemview/SEGGER/SEGGER_RTT.c" + "../autogen/gatt_db.c" + "../autogen/sl_bluetooth.c" + "../autogen/sl_board_default_init.c" + "../autogen/sl_device_init_clocks.c" + "../autogen/sl_event_handler.c" + "../autogen/sl_iostream_handles.c" + "../autogen/sl_simple_com_isr.c" + "../autogen/sl_uartdrv_init.c" +) + +target_include_directories(slc_locator_host PUBLIC + "../config" + "../config/btconf" + "../autogen" + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32MG24/Include" + "../${COPIED_SDK_PATH}/app/common/util/app_assert" + "../${COPIED_SDK_PATH}/platform/common/inc" + "../${COPIED_SDK_PATH}/protocol/bluetooth/inc" + "../${COPIED_SDK_PATH}/hardware/board/inc" + "../${COPIED_SDK_PATH}/platform/CMSIS/Core/Include" + "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/inc" + "../${COPIED_SDK_PATH}/platform/driver/debug/inc" + "../${COPIED_SDK_PATH}/platform/service/device_init/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/inc" + "../${COPIED_SDK_PATH}/platform/compute/driver/mvp/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/common/inc" + "../${COPIED_SDK_PATH}/platform/emlib/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/inc" + "../${COPIED_SDK_PATH}/platform/service/iostream/inc" + "../${COPIED_SDK_PATH}/platform/compute/math/inc" + "../${COPIED_SDK_PATH}/platform/compute/math/mvp/inc" + "../${COPIED_SDK_PATH}/platform/service/mpu/inc" + "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_gatt" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_host_com" + "../${COPIED_SDK_PATH}/platform/peripheral/inc" + "../${COPIED_SDK_PATH}/util/third_party/printf" + "../${COPIED_SDK_PATH}/util/third_party/printf/inc" + "../${COPIED_SDK_PATH}/platform/service/ram_interrupt_vector_init/inc" + "../${COPIED_SDK_PATH}/util/silicon_labs/aox/inc" + "../${COPIED_SDK_PATH}/util/third_party/segger/systemview/SEGGER" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com" + "../${COPIED_SDK_PATH}/platform/common/toolchain/inc" + "../${COPIED_SDK_PATH}/platform/service/system/inc" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/inc" + "../${COPIED_SDK_PATH}/platform/service/udelay/inc" +) + +target_compile_definitions(slc_locator_host PUBLIC + "EFR32MG24B220F1536IM48=1" + "HARDWARE_BOARD_DEFAULT_RF_BAND_2400=1" + "HARDWARE_BOARD_SUPPORTS_1_RF_BAND=1" + "HARDWARE_BOARD_SUPPORTS_RF_BAND_2400=1" + "HFXO_FREQ=39000000" + "SL_BOARD_NAME=\"BRD4187C\"" + "SL_BOARD_REV=\"A01\"" + "SL_COMPONENT_CATALOG_PRESENT=1" + "RTT_USE_ASM=0" + "SEGGER_RTT_SECTION=\"SEGGER_RTT\"" +) + +target_link_libraries(slc_locator_host PUBLIC + "-Wl,--start-group" + "stdc++" + "gcc" + "c" + "m" + "nosys" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/util/silicon_labs/aox/lib/release/gcc/arm_m33/generic/libaox_static.a" + "-Wl,--end-group" +) +target_compile_options(slc_locator_host PUBLIC + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + $<$:-Wall> + $<$:-Wextra> + $<$:-Os> + $<$:-fdata-sections> + $<$:-ffunction-sections> + $<$:-fomit-frame-pointer> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + $<$:-mcmse> + $<$:-mfp16-format=ieee> + $<$:-fno-builtin-printf> + $<$:-fno-builtin-sprintf> + $<$:--specs=nano.specs> + $<$:-g> + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + $<$:-fno-rtti> + $<$:-fno-exceptions> + $<$:-Wall> + $<$:-Wextra> + $<$:-Os> + $<$:-fdata-sections> + $<$:-ffunction-sections> + $<$:-fomit-frame-pointer> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + $<$:-mcmse> + $<$:-mfp16-format=ieee> + $<$:-fno-builtin-printf> + $<$:-fno-builtin-sprintf> + $<$:--specs=nano.specs> + $<$:-g> + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + "$<$:SHELL:-x assembler-with-cpp>" +) + +set(post_build_command ) +set_property(TARGET slc_locator_host PROPERTY C_STANDARD 99) +set_property(TARGET slc_locator_host PROPERTY CXX_STANDARD 11) +set_property(TARGET slc_locator_host PROPERTY CXX_EXTENSIONS OFF) + +target_link_options(slc_locator_host INTERFACE + -mcpu=cortex-m33 + -mthumb + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard + -T${CMAKE_CURRENT_LIST_DIR}/../autogen/linkerfile.ld + --specs=nano.specs + -Xlinker -Map=$/locator_host.map + -Wl,--gc-sections + -Wl,--no-warn-rwx-segments +) + +# BEGIN_SIMPLICITY_STUDIO_METADATA=eJztfQuT3LiR5l+ZUGxc7J6nq/h+6GbsGGt65rQxsnTdPfZurDYYLJJVRYss0ny0WuPwfz+A7wdYBPFgUY71bmiqq8jMLxMJIJEAMv/+6sPD+3+/f/NkPbx///Tq9au/f3z1cP/LD09v/3xvdX/6+Or1x1e73cdX/3j1bfPO4/tfH97cP4LXvvvDSxh88+wlqR9dvv/4StwJH199412cyPUvJ/DFr08/3RkfX/3h9x+Tj5fv4iT6q+dk34D/xl6SfXl0wH/BU9X3H18Vj33zzXfHKHC95JuLHcKf7TyLTt6l+Rk+4Ade/fPJzjLLPewcwDpPfPAN/PX1/s3r/aMf+E50+cU+pPuTn+1d7zm1fvMOiW3ZkW0FkWNnUWLFkbOvP5+jNNtXHPcd0vvrzM/8mJ8nmaeBdQhyL4ui7MxD/CF9HBgcFDGkfwVGZCeu5XpHOw8yy7/4GS+1IBlNAHt4urfeRGEcXbxLlvLQ0JjDtI6c+jkLELKD6MSpyZB8pmEBDr7jFaq0HEDzU8qp6dCMpoF5z1CGs31xAy/hpKsRD1w4fFQ04jENxwevJp4dVk9zse4JNgtA8VETig0GqMLy/Eua2ReHv8LG3KYhpn4YBx7suZaf8jKuMZMJQIF/+eQl8Jtd4LKHMiA/rZXcTjI3eeY5nQxZ4IDhaz9IPhOwdk7igPa8HP0T/Mgez4hBDeS7fekpov3G8o2e29j7/ZDBJzq/o3y7kkie2BlwcXf1K6wkLKnvS7L7Kww7qu/LPDaR8EVSrWNgp2crPeeZG32+WHkK2rNWIUOLqfBjcp2wn8f7n3++f7Aenp6AE3M5csCH4HDFE0l8sKKxwueYq8KQbPD8I9dxHb7YpplNIKzHC26oxgwwdRUHwXq66jObW6iAJ7Mk4gtvitP8FFP2Xu+Fbze4xm0a48WJC0KFG8ET3gSja7Z3yE9W+jnibHRjLhOY7Di27DT1eI7/SB5X/MzA8+LMD8Hwx1NJSDZ4o0ZwfOHdgJPMphGGXhglX/hO40MWE2jc0OY63I/o47WbF+arNVufF9aqiqu1o9jgae28prWfsazdCwP/AB5LvGqs4wbvCie8ZYYf2idvKjgN1uBuCCQPT8IuvpzYoS+47kfkJ9TZPifyhSFiwpD4wpAwYch8Ych9GNft6OQ5nyIrdT9Zyk7ZidPr1jiws2OUhIOVa++ZH4se13ti9ExHysGDo0fvf3qQpXc/S8rowTHVKE9GnBGr6/RLmnmh5R0TWQINprAMrQxUua81ti/V0qPbiLYvke9RwPaz0mTAfc3jLYqDQjaWZxRWmGjetxcnyF2M9m34HSRJOIqqrPmhYrAcwMnUUgmwn8Y329jNq5bthPEGRWpwLRGFbSyRmSTD0OOsIIc8scMtitIAWyZM5mxUmBLYAmGcMN+iKBWsBYLAmNgWJalxLREFcLgco01K00JbIlBogzdTJ/FjgGiTco0QLhEvDoJNClXhWiCKt83hwFs8HHhF8HKTsjTIFohzTBNnkwNCA2yBMKfYSTY5VjfAFgnjb7JhalwLRQGAttlteuAWCHU+brTnNMAWCfOyUVleloriS5scAipYSwSxt+l41riWiOLYztnbpDANsgXifPK+pI592aI8HWgLBAqAm7pFaWpcC0V5OdibXAx0sRGIBM8g+5dthm5QGJeI6BV7t5uUrIW2RKCtegcBgXcQbNQ7CJZ7B6HtB4foZYvSdKAtESi2z4eNBkG72JaIlG7S76lgLRHkeZMbBhWsBYLEzmWTa7ca1xJRkk3OnxWsZYJYqX+62MFWBerCWyBY6iR25pxj292iXH10S8TyNjz39MAtEWqbYd10cVg3BcumI9MjR8xkaZAtE2eje4ktsgXibHZxQLI0yDe7NshJFgeb3Q8h2Q55du1N9poa1wJRPrtsr/uyEqXGNS9KWJ0l3ZAUXUjz58SGh8s2IwcKGfYxMeTXiC9RXw0v7YVhdLl+cNG/OIgDi/3zzUAtob9Ovy0h7wGqfY/xUHujq9yXfJ0leh9gzXYOXnmh4xYabBjPQSzfuwHElvEcxDSzs3yd1VgfYst4P9crRx0sTTA6WNlKaxxzrQQDqPY9xrO6h/seQcD0/j8myC7r5frPoihwzrY/HAexGmrq3tCaWmgEqPXRQhg12sSMMj/kT16QSryTv+6w0Mpb9b4REsRUim6l26PGg3tyHCtOPL90H24KewwFy8iI/JM37x7fPl53T95Eyfh8PPYx+p6enTD10yKVjs84+8ykkgsB91CGxjUco5gxj/KFKi/YbVF3QMyAzn4rrkl7L+v4PAjEfQRYOgamf1v9VgDmwMLrdU4oyzcD2wUwAzaMc8tOwud1LqsgwPYA8BvKygwU18ey4kokGy+kubO+iiNSCrcvmNZOSA8BTz+kZbSGBfVErabEHgJ+JgQ88fl7hp3bv3OWhKveUQq3NfRcCbvvsG/VjUI070R131vtUgmmHNOXSebyrWxKisl7CTN5BLYkxOSVhLlb/VsSYvrc7lwmji1JMX2+6JoUl+eVYpGYUtR4yCZB3Pl+kEQqlVaZ+VEqaBwAJKTlI9zWZGkhLR7nNiZKi2j5aLcxUTqQlo95G5MlIJWlGGk2JEiNh9QnHrusVaZVNoukmtqqKquZ1vrqgphv7SbVbJKtsx0wB7sGwnOF16hozUm9Ebia0bsgFrbTFmDXQJh1xTDOGW2YxPmqlgz4NRslJWuuuyTxuosbKF29wRAjFzLELZ4UGa4zL0nyOLOePQeiwgk04NnBJPlVrWMSRW0zV2HytKRpxmva17R+Kqu7CpOZLZYHaNgYXnUYZ3VTK/l2NrG7KOanmOqFOIkcL00t2ylyWN9cgDEenp2iq7U1u0Elen38o4+CtO1uLsAYD7sO2+SHZdRpG3rrmnzDtjH7HhCMpm8T5Z7toD6OvRUZBpgWi1NmqtqUNA2kxcJsy7z6kGaF8Qevrju6DOVAoeE6L7S98kZy1yNrD8iiVrst8iESZjNB7nqB/YXNLFDSWrWLlizr7tkCmB9dymeLwwZaWJzleLwx7gEWnh2yUtSaJl1JXHXEFgC/HXovdJPnmf35Itc6A+svCa1i+oVYVZb4woBa3txMpmKxhr30xIPW0vJmNughb1qQ6MVzopUOgJZq6Zxzb1gz0wpM/dXEChj0iR69FbtGj2/RQ0ZIuHWUPqf1DKMvM7SPERJ2LkNZt4aBhVSUVrSNimNhFR3u3Oyh5rGeJdQSQhvocOc3zcLD0Xk2dxAOdeByvIvxHM9n2UfbFSLW/xyvde8Dyl+fRQRsmw2NEsH8zcjiURjvOcF4rZ149u2Rj+DgipFnfrAB+DUMXNhwPV/cAN0A9h4W8oIF6PEJ3VNWusQyFLreHMPMwYMyzZsjH8HBFSP7Eq+Uvu46/gbHoi5+e9w1jAVdfAOoJ+Jt004H8ZkAOzszOhQAKMF/Ev9l1dER8m3GxT4GrqcEOqzWtJdC3NpS+hgw7lDCF9YfUUaYJwcTvBZi6wIWSryFT1KopTurD5FgjVn1S5Bq4L1U9mCFebDa7fPr0kwAIxKuOpwABPhrfrIzb1sSotDRiOlGGfQb3NzZWFOi8dGIuj1zHQCjEs4+Xfwsdz0r/RtYbnvuNiVFoVwkdtXDbXcjAvbxkIiS5odNiVLhIRFlOz2MZiKo3t3cqIHGRWRyjh1sZF4bIiIRJ0vsSxpH6bZE6qFaJFbVwgDxNgTq4yESZSvDdR8PiShOYIfrBnTnhGkQkYnjb00an1yYKF4txxKeMBUgEmE255kz8MgrEuDnjSyDB4BIhNmOg0DjGVTvXrztLHlHkEgEio7H1NtW+7SQSATakO82REQkzlZWP308K2x2VYzXj5J29wE6IBa13uo7L1PIl22+XIsXbkKaCWBsApmbkhCFjlUgc4uCDvBRBzK3KCMLcx2HCDcpKQolaSBzEwL28ZAGMrckSoWHOJC5JVmIehYiYLglmWgGjV7YcEtCNYjoAplbEqmHijSQuQmB+nhIA5mbEoVguO6FDbckTIOIOJC5LWl8cmFg3HBTwlSAaAOZW5KJxiPvxg23JFMNiDiQuSVhiDyDftRwS+K0kCgCmVsSqIVEHsjckjxkvlsncLgpYaZWP9zrR3lh4B+uX8OZrW7jhZbtrLTPWuAt4sEdrlcL24Dn1ktp0YM3mbZiiM8J18mf1kNXMZ3FFiXr7GD0wVVc59C5h9P64Cqmc9i8W7Sqh9eqXlnZcX14Dd85hKfYSW7QZxu28/j8dSozDOD56GoMA3S+dAPdVUxnsdnuLcBVXOfQBW64zkXKHrqa6yw6b72MRn2A3mTeoiHGML1B81ZM57BF8VoHwnroGrZz+GLncoNRueY6iy5Z55BjH1yCPMk4xJbcYrZN8GbblQ679qChj7KOkBVZA2+AruE7h/BG4x32aHcjRwrbjyrKXq8Or+Y6h66oZL06uprrfm79jHVgCLkWXid3B5SpyOvTcsVbC68Or2E7u948r7Q10INXc8VZqa8PDl3OCIGtOPlgr5VDqA+xw/sqUpiX8Caa7DOe0+aK5bz7/RivmnfRpdbZqR30Y/Q97VHUaLVK4307xCs0Dl03OzzmlxuMhB3Gs3P3ihVhexivVIFFxgdv0M4JOo8dAp118i5eslJBsRHKLnecaObqICumONHM1bFNFPKbiGauD6/hi4fwZtPziD1e9HV1nA1brOjrDeD56AKxiOjr6uAqpljR1/XB2ejiqMjo6+roaq640df1AXrTSbwR0dfV8VVMMbDdbAjs88aLE68OsmGLFSdeHV7NFSdOvD64BGtlktzCj0nw/JiVzhL3oKFPCo+Q3UJrKabWvqTO8QaOc8sXM8p+C4QVXzyEt1spjfnj7QusDhR7Hr7RkgR7RVJE6NcPLFRcsfYFVkdXc53dF5g/VxcDO47PXmIHlIfrWkJrFppquRZ7JkgQHHZPxnzWsIGOsNAQkCCuGuzojTW93Dn0k14vjl2Pv+i3qB33M2/i1MwYVgbI/GEfQbGpAuNzmVjbJ3kqH3Cpy2pA+PuW674PYD4F680BjzDwy/p/CHIvi6JRhmGiSisXJ7ZOdjZrEUC++lGeQyfUcCNfreua8X4AYt4smqc5GwUeZFyrQDYS5A0HIcyGqh+/SWPVzPcIMHiN1rxxi4abhE/cgKkPr9JjNl/7MP9jMUgdtAD2E3DmG7HzVhId8nRDUrR4loixuiVO4cebEMfybgV/Bw+zOXLOwYqTKIucKLjmZWFOq7NLDSDsIWvHDTv2ua41Ksk6+q/SPCFAzJwo6b5yc8yc1kaQyQmqg+eiYixfdWOtYY3RErcD2fDGQ1ktjfwDQJbxvcM9g3mMBEMC/oUbrqGertkwPO11Q5Pwl9nEGgdurukU99zNYMC5FdwuABwrgGsJ92C53vF2xtDHwD4icrYT97OdeFcn7Ag8xGCyhmQs/+JznfNqgfYFu2a+6/GeNdbiaYAmS6KA+9W5a4iHGDhN1F1ePG19IGrdNYfs8dqnaM0bga15Mwi9I8tGjkJMl6N/yhMw5UYXKwLPW+nniE3hKyfiekuq0WJVKQwtSm31FRiyxT9e5SvIYg2ruS5vZU0VGNL12UgF4YukWsfATs9Wes4zN/o8G5icspL+Q4GFIF3GKfBS0o7fXtPqEOybLL1Tck38uCiFL53h8m+CFTsCqgnq/CJLm2CV5CNzrtNoJ2jwe3b2wUwRAzG+XB/d48S/ZEcGo7kP2iHxbHi4CFLk2cGKbZmOhPuSZdGpEDC4DehDXhwNekpkaMQIGNgid3dmb9ZuV5oKAfAGWp5SLM6smHqn03xl7vJQz7PvfZ4fjB/vf/75/mF+2C2fsx6enlZt1FLgfSvRvgSy7+OZzUVVPr5qc89Ax0qh1ZFyQ9BrPDdIm5WWIlsBkPn6XGRHL3P9BM/NTrIApqk88I6lFa3QlW8PRKgdiyEIsmlonHIM8VDiBZ6dehNDQu/Rk4Mu4zBujCS0QlmeeHhMtzyOOPn4oJGAWEBVVpqBpYmzs9duIniQrVLaHmhkXwm7r6TYj+Chuv2VRpz9cbrqBl9Hcvhnt02AD+GG3i502bVGh2Stwe96i9Ka94/e0c4DsJb4BrSRF/S+KaIeb7pBfxgXTFxFECT7tbCD//eDIH8DvxIN3Wm+EsHLcHQcvhs6+Q60+M47JrK0C0+SUn6Enw6SJBxFVdb8UDHA+1kUBc7Z9i9DInCTFtgVzLmcprtjAuT4HCWfdnES/dWDJaTgtctL9ATefwPfL1EBisA2r9FyP+2A2Tng3zz2kteFFe8sXZYEXVFEodPBvnO91En8GOrx99/tu3/Vjd3TdfHtd/sKYPHXq29fPb599+GXt2/ePv2n9fj0649v31vv3v/46y/3j69ev/qvv0OrCKNnDzTg66MdpN63QPW5H2T+5f7FCXLAFPzyX//dfv0Y5YlTfgsGkTyLQJ/aw0iy5RYVaL4dfwsGR0ggjNw8AIPY64+vvqtAvn73rvjym5cwuKSvq2+///jx46tzlsWv9/vPnz/Xqis2odP9h6oBPNgC8MlvKmTFa1mSl1/6bvF37uxKvrvUy/J4Z8dA99YB2AzU3K5rzTs4dsJXYzfs0fr9R6DLQuFg6A9yuC2RAsPLMi8pme7+N/x3Xz3XNEEt3e8LrVQogfyQ7j++pdV92fad+d+CMkFlf9v82J5ms8pv+j8fMvihbKeeKe3KX7rPuqHtJs9IMsXB4fKGr+sd8hPyoVHYeeKhkkL6OZp+4Nl3vCJKarmO62A9FwdXGLbPeUXuhtnHzscXLHjBteeKyEVVowP5RAisI/ky+etUXGPqhe4hqKlnOgc8pp4IPC8uTv5PPZEDDNBSSjDeC1q++qn2t80MEbnz9Q8O9RD88HRvwdkouniXLK2aoP4x8C+fvAQ6AbvA7f0CO2u9YzgY1Hs/nUc/FV3cLef2Zk+s/4xT47GAeu0gOo3JdDuRA5rhUzom4z1DEmf74gZleqprP484NEGV8gkE/dET0zQKnP4FzOsXB/Vgp1v5KQJr3RnQ+mp/7TDYUG958kJ4At/7mvsL1RHmb2nePy97/9qpXCZ0FuC5driRlkbngCcrUixQNYdnJyhh3YRY9u7oUgLidcy974Vv1hvR869dPVew8PXOIMhk/5OcTn/fGIMO420oQo4Ue48Ijs3lqjfvHt8+7t+AOWL/9lKMqHsnTP20mM/9dpJdTgBMFcTvdo6JLX0frlecUJYJ3g3j3LKT8NkgeDf7regh3stU32pe/rHwgnrBmfufHmTp3c+S0pBrIhtN2kOWJL2pLkRK8QB62dQEQUEzm7WghTSr1HgMKcK1KmuS4PHLMWJNNbStOtgUzfbqpcTjYGoqIiXpMW+qNpkVQ6JHMC6zbqomSRRTmj57mH5kxRFzlZ6P7FUKYzuMSVbpqFhStJmPJb5jO2ePMdFP3pfUsWdn54VU6xxVjEm+HGzWo11NFkZE/AvzybSTC4slVQ69KmDfq0LbDw7RC2uqsX0+sHdRqqxgLCk+s3b26pRWLEkmrE0eUATr8dPFDlhTBg6PnTnn2HZZE/b4mGrK3O9p0zixJcrePecx7uU8Bj4enmSdOYghyTrdDzuSvY12NqTDal+ACbUqzVaDl4poGUvepxlo7DzuEJ2JqWARHQKdoVmFEau409Ww4dQ7WRT6sxbWf6fNNo7/jnfJZ+fZ/hvwwE4+O/DXQdykqwE8rVXvwIHQDoKpuN/wreYQSY3z5DhgpvL80tYw8Y6olBvAdG9biXfCiI+NiNRBxBLCvBqK2p51ULJT3XPeS7n6snW2Z8MF1wnESXQC/pxlJ97souE6peaWLzkJGNsnoFA3xnNM0BLty1CZ5ThCR6anUipKhT4wKRSFY2tdFkVj7SzxZ52qydcXNedU1Vra94vgeeC9VMI0paOZ0GxqoF/+mtclnFkSHhQiZ0k6tE8XPwNjp5X+LQd2NuuTL2bAQtFVo9kuPTyW7V/RaspCMyFWlmVmQSpL7EsaRykzbCybdMkIPVfKGp6xYEWKgYnVw0Fgz+8T4RPz2dGKYhxnB4sWy6GpInn053cucGkxMdWK1sVjMrZX1KLjMfWYYWMzBPUrwy8iVfsa16bbJf7HNZqj6ZYx4a5NMyY9nm5ZM2Ch6M50y4gUS1ilrbMilh9YkWqnW0YEWTbp4gUAikhnumVFioGJ9aZbZsR8drTgdMuIFsuhqTvdMqLFxFT70y0jatV0y4gamyGoM90uIdUjUy7NZ16vYgLFjY960m+uf8xN9b2XK97tyzOcvdBNnruxRc+J5uN05VvlRZjirfLjotcg0uo1LIzw6IR/ybwkyeOsYNr7Bo93nwiE0CeChaQ6hl5gqD7jca9fhHzrF2c5Isr54r+AFfNG1+Rd8Mbs4g5ZVhf/hfntvSt1Z/FfwwrcIytOLnqhW9AE+8WqICP28xhHwSaqFi58hUTTWIe1kEX2sF/AOGmErEWH/QLO0Zupcm3Y72AclrhSzwz7tabCGPYbOCckUIW4sJ/vFMTFf2ehzc/H3VCVp/CfxzpDMFGbaeErRGPKcntcPkjg7NBPVRnGfgdnz36q5Pf8O3C2ridfrNm6eqGcSZe8ASEteh5OP0tegLPIkue9hYC8a7eC0K+Uc8GyNyZv06BfgHPBoufhXLDkhWIuWPRCNRcseQfOBUueLwf1JW8Ug/qiF5LZOEPv+WShOc1HavqPl6PnkleWN8NyCy+GwCUvFMPZzAs45alo3sd0I3BKgl17HyxPinM/nWvO7fp3dPN5BgwmMZzrJ7ikMO5wYJLCcNgxKeGc28ckhXNYGZPU5XneO0GRagIag1wX6ezRDVxqMCMGM2owbwYzYkV2DWbUAqbUivbEJFWnB6jtov4b1x6m3reSyWvj0zQqWRoMS2UYvF9gwKQRxnmzpRdjd3f4Vh1SjGcn0PqtpMjGUMW16khmt3NOPoCLa5pDhXaaA6YMbYqV5thj8w0uyhENn45IfS6ypbFcmBGN4jwa1noBm9qy+XeWHJ2o/oActt4Lj65p/HKpu8RGkQTiJHK8NAUrugxjpTkg1Z6LbbDgagVFYIAFk1TueoH9pRar/AtXjurdCkb17jK+vXeL699aWNxdf0STmS8gtOytpnoLwWvjojpLiXQLnCx99+pRS8wiMEte9QmVhaiKgvc6uvIV6bt1pS/E+4sykmK/vzhd5hRl/AzWCyi06aOXv7SM00SCcRwKGKmFGZCpkyuzIlWi8kP75FW5PC0/PAm7+HJC/iJO/iJN/iI3v3SyhW4mfVWTjOyx+POrTWG1GYW+KfYTKxofgBr/CF52/0ex1IqtkuoBOwVvnNL/0Si1Rv95jLTNF7hzkiYjqgOremxG27lTv387Nf83MiHyhx/fwWzI3/0B6OLjx28qp/P7j69EmNAZfONdnMgFnQ589evTT3fGx1d/AGwhX8C44gseq2u3YOcThbTB67EH5utHB/y3rHJbkHvVcAAPgf+v8rG3bMpGHj038XSd0Bf5dP2OD4ykeeNKVmDwUOEa2pnnfl81GfyySCgKvykMuGwcBLYmRzkSeA/EtTxmndyxlID6PBEZlZnSTyeS/zJnMp0omSmrcSpfrpL0UzmzZjWVo5o1n2tZklnzmsj8zL6Vxpm7mfJAZjNnLQUywTVPgx4kCWfNapRFnCmDUVZ4nprqZ2dn3vCo3Oc8xTlzbPgrKflJ+UxM299VSQ4+2NkZ/FkWFkmz3PWj17VPtq99lRFN/Jf3tfPR0ujUuqi++YafDzed5ZrKi6v89kk3bjQ/ddOyg18aD7xtyHHrYk9+3cTuzIkjU8Mz5TLOds9aCGTuetZM0NnvWXMZJcjny4CDBKgM/dx58JRjXEeANatxJQKmHAYVJVijH9ZJ4EefQRPQzJfNrHCTyW4uJk414RXbA3jT3WhH4uPYS2lUSF3LbGIXBMt2RjskqyIViZBKN0AqESGVb4BURiOd6tRDKx/szuFG6eqjBzNxusFbZRa5q+9MvNnRFsbrE0SajHXYJKbQFAHthVTQYzkiZ94186nHX9Bg7fEP0uR8aOtehh+VSJCPAChOyyS4Gs/FbvwqLyOL1p/OQclWhfM5LxmYwri+A2chGj5swTfOFF/sJRum0JuSFbzBN4xYwy8vRqwAv2TEFH51YY03+IoNU+j1lQve2Gs+bMG3tUW4429ZsRVhVMiEuyQjjmwFqi7ecBej4sMUvLdOR/Y4dOQ2TQB39A0npgI0tWd4428YMYXfZE7gDb9hxBi+v4ryaz7MwTe1e9aQoGHGVIymVBBvERpGjOG/rIT+hT34KisJb+wVG7bQ7XVcuJoPW/BNSSfu8BtOTAXolI/iLUGHFVMR6oQ5vPHXfJiDr6tirSFAzYuLEN0aXGsJ0+XJVqg2rRJ3WVpWbEVYa0YOuMzIwUozcsBjRu4UpOKNv8OKrQidQm3cZejwYitEuop3UbFhC/15lWB0xYYp9DqNG2/sNR+24JNVZrCKDWvo3dp9K4jQZcdUlH6xQN6S9LmxFcRbcS7oMWMrxjrBxZRDcLFNmMgdfcOJtQAr7TC1nJgKsJorzceRzlfzpHM+rvRq0XU+wfU62Sdv9DUfpuDrJKK8wdd8WIDv1gHlhLvLgsV5HkSxUT7IUZy4HufBfhzjQZxHxtdgYb4BksNv/sVZcOhteFa4LZK6uCGnqq3ithPiqH1VSZUSSk2GHEibep9WKw0hcjBtantKMC0hcjBt6VpKMC2heTD4nXPYOdKEqnM0NXdJhR0V76XQfKeYLyWcLime2m/q8JKfyl3SgFOaa6v/kurtSkFh7AZdOB/RDPPXFdGppUyvjzoj5pDywsl6qs3YY2QBblwXmxnIMWnmBsbJg3nz7vHtI4kD8wamYSEeIMgOXA/a1AlTPy1uRfoB4Rq6EH8PZWmc2DFVKsMryXVyCbLD2CFKBTH7rcg54b2Q+U4IfH2KDPQHM10y1V1FkA4avOHuhLLMDFqXIBW0MM6LJKFkFw8Q0HoEv5bBrcx0QzK6FXkLbuv/9OrJLW7C2Qp1X5MH1KvLR6eKJk1+h+LXYs5VSmAye25u9ZNbNZumRJWYWNymi4tY0DqPqGoWvFCTXamYz1zFFTPRqf3ZlDs8IRMd1p/PqsMTMtkJ2fkUUDwxk50huo65rmzCC3NNf61Jko2/MMi4V9YdYaKi6xVhWI9TvJG3LBiPVpyBtxxYj1mcgXdYsB65OCMP+CCvK/nwgl3Tv4VnOzHE1XmGbruo6pYgIlb+tbpGtFYyrHHEHGRN+Gta/3WLV9ErBFERi2mr8QBZE95Qhw7j/MYbRGVlLmJdj4t8fU19oqpmRiV9vzDahmxrsozZbS3uanU14pagK+r2Ndns1fp3HPSHU3ZvQ1ZfHp+6rYkPiqwRN8rV0m200+1kITe2cMf0v6bONijdR6sadEFAPi3JHO6Y/pa6fZP0/cZdv1dfk7wBZgp3UpvMVNFNLogHPBiDb+qP8sPesGAMna+h9FlQQkeVQmWHGkX9q5oneqV5WegFWTiYYRuyxTmkvKGZoaz2ettZoa1WS6zyqfK3tCMSshguU5QD2l9Tt24rFNNqZFTy+Gs5L+GFbvJMdFqiKCxzw35XAiDqdIXQ+5JAYcwtra/GfCvIJLbbEx9abktrQwM79r0hXhr2nIjwCHSp4M6tkIbUhvQLU7k1EZ8b9uMeDoru3KNT9OoR5a+mc/eRk5tgXyfQEkeUN2SRVXWPG9pihYDCCisKhf11qH01lldjJre5WgPQ2jrUvhaHCF5qyDOyA6S4R6kn3g+fY9oKDct7ANIK4IbXc0x6rwzqrz5RDMg0G4glRRa3tQtiMGJ5gvsWduLZ7LGOyLMDnmd+wAFwTZYdUBhhKm6qc0Dbo32LghbLx8prfYXwqtxQQfV2M7OsWihjZo51RJ4d8OxLTJgS8jrihi7jbs0eaU2WabfmgHNhXJeoK69xZgfWfbvtoR2AAP6T+C9U4y6k04y4fZpfjT86gE5jtYU6anvt06S+0w3J0Y9UI4SLByna9tqWC1o0Egt/qVBs1/8YUmY0ttZkId/Ae6kszArzgDjXxnX8E4w4iVMdC3Kiy1/zEyy1zFUmFDe+grlRBj0ZN3c4NxeaH1/h+BvhgBFncezTxQdwPSv9Ww7cTncd2VBcGQta9WXb5SRSnz4f8Gl+4Aq+os8HPL+ewneYrqhz7+9oPpwMybEDTvPMkAMfAbLEvqRxlPIVoseFsSBVO9sH4gRd10Xo0+cEntdg2qfPB7wT2CFdMHYOfsOBlwA+b/w+T/hRTJxjDQ9+xYAPfO5e7SrebMUEPMBpKThgwAc+v0mZ72xcUb94/JZ9IxZ8RIiOx9Tj2wYtCz4icPSJhhw4CcBrddCn/5VvKlVC0UcUu3H6DlHGbUu9+zGFlfUGyLXYGRf8E4zWCtJxlQnFbb0g3RqiDfitEKRbQ6p1jHAcLltFNhRXfkE6LiL16fML0vEEX9HnGKTjiZ5TD0EEz3hKwbe790JoXE2p5sA7SMdTiB4XfkE6LiL06fML0nEFz2Uw7YXQeMJvOHAM0vHF7/OED2NoXOFXDPgH6XhKwdeb7cbQeEpRM+AYpOMJn9Ns3I+g8RSgZcE1SMdThJYFzyAdTwl4+USdIBpX+CSrg6+s9pkXBv6B5CoJRXUnL7Rsh3C/sMBbRFU7VAgLOwEK5Kk7ekAWp+cYI3FCsjx4PRwVEQoUUUIWt+/DqKiQ43APJ3oYFRFyFB6LNvFo28Qra47SA2nokGM5xU7CoL80ZGiQ+GQ1NQZA/GV1NEY4fImBPioiFChslwWMigo5jsANyS669XDUVChweOSZjfpQvMX5i8ZowpRB41REyFFEMekhnR6Ohgw5kti5MBjPaioUOBKyA2N9GMmiU2FjFAmLWSahnWUIj//1QCw73IfAUOT5Y4CjoUOOhdH4wWD0YDT9M5j9i/Lh1EBqKuQ4ikrg1DhqKvM4KPLlLzhsMbFKIstzAOUs8rq0VGhXSdRAGjIU65MzYQi4B6SmQrdao4exrHQREkWxs2yTZmDpg+nQIsQE8/Ax0U6fELmGKIqJ9/sQbS3xwvzJdr4GfWjZbUvECp+4onnfXmgLmkOnxQ6P+YXByNIhRDG7UVR37aEhqOg6EYlh0ErJsqxeSBzWybt4CWGxrhGeLjW6CBE1nIoIXYSIGsXCEnaTESJ6IA0dWizMpqUROdrYFTWihgxl7IoBEH9Z4VNk7IoaRkWEMnZFD8NeVm5zInZFjaOmQh+7oofiLU+HjIxdUSOpiFChYDak9GnRxtOo4TRkKONp1EBqKnTxNHoYCaWHm7CYkxPaOZnwpF4PxLJzeAgMLDSRUmviS+ocGThrLR3qCCMLLBUdWizsfOsxPdroJzUkBvMPI9eWgWdbxC3pF4cVFcroJzWOmgqT6CfJyZMYWGl89hI7WPn4ScuYpuxMS6WIJyOJbjSyPMZKYk0dBUCTQhIlNPIRLRrfbw7nIl+Qti9c/3HYxnZ8PdcZeUb6cWbrzMfph9NAqxApXS69ls6SpgZv1ansoRj7lsq+T5A2iR5zeCOaX0sO6kOQe1kUYeWhZF434eLE1snOKG0N6L4mtGQCgK3ZSF+3a01oPyBKa3ANrYXmhgeQh71dabJzlBaBPCbNVhNj0nQ1sT2COIsmbOixaMZJsCs2Z+rD66xMGrMltfygA1JHLcH9BHnaJu3QTKJDnnLE3NJnB5raCqfQsphix7LzQtuhv7lZd5mbGCdRFjnRdf+N7RROsfwCjXDI2pHLjv1F669K1k47VylWEESJTzF0iTFHt+GVIQR6gspbstAay1zdp2lIUbUDOzgNLVo81ZLRP/iBny270zmDbkyZCuvyhN/X8C3P9T0+HcSwQX1WLUpy8OOanujPfwwGDFbAugTp2hCuH9yD5XpHdk3Zp7m1WMzZTtzPduItnGQj8NoNJljItizvvmD2qkXcF683M1ePFoVBF3Sc6JIlUbD4+s41bEOaG55cu3iX9JyB+HWXHpKjbZ2ilRnBqmndbIMBu9gZIkB1OfqnPAETcXSxIkDFSj9Hty254kSL7qo0LVNVwkGLVPejivha4QMWNVcgZBJLva6PyoIr4rdYF06oLHyRVOsY2OnZSs955kafKQKoJPY4JBFYCEhljIVVeskxfZoegCDXZOeckmTiR+6pO2/RwbbRwBRdGtXAdWaHpQ38T5P2YZmTO7sLOHojO/tgro+BKr+QzLRx4l+y4w1nVh8shxLPhsfOIJIlA0yxmdeRf1+SKAYVBNmvZnIdYl/QJadUArshgiw3lfRPEzBrWYLGREJhoNElSiT3OlLvdKKpF1weSXv2vc+009Hj/c8/3z+wmHhKStbD0xOVSZSq2bcS7kvC+z59BpmPSoJURjMDllGKpo7kHMHW9P855uepjuMHPliiWIF9SEnmVTt6Ie+1LJZnSRbAdIqHpdHewhq60u+BKLUbNyS61pSKlyLrKonECzw7vR49xCZ2cshS+E8ZSxJaoSxTkJzCWR5FpiaMNDLQKMA0rDQDS3hnZ9OaGDwaWzXSHuh3XyllX8mwH7EjGTApjJIpAbJKEhsdQid+nPq6b0XAI3VDbxe61+0HvvR6/+b1/rG0m1+g2Zz8bO96z6n1m3dIbMuObCuIHBumDowjYDHVZ7jjsu/wGRrOd2B0C3LX+2Bn55HBxkn0V8/JgBk6nyILmK+l7JSd2B5v/dF79h2vh+v+pwdZevezpOzflpQZ8Zw+yMhaqIpLMRGxoYzceWJEfBwFZ62PN+8e3z7u30SAB9smxQ+LshapYuh6h/zEgz4wy6JjuEX/KHYjeLDxQjd53ruhDf/DgT66oD0fKdj3utHNEz7A4cYfWA57SZLHXFq5NqY6hsGzpYustLzpc7KjWk+AE4/xlSLQy3AKnDxczZtHe4Cabav1b8gwoj4RuOJLnadNJ3ZoNYNMnSKa8bQyufrlpbapWAtPU+4eHufiNgJugXO2fS5TWW0Opcq4cgg8Ly5u0PKbOXNgBZw8l1oMQCCwv0xwCG0niX70jrAfAY+zXZc1a5g/SpLwk6jK2tt3irGEwv/94eHHv/zwcG/98T34ZP14/9MPv/7yZD38ZP3xhz/9aEmKIFCQe/z1w4f3D0+PllhTZEGMGNxP//He+unh/v8VS9ZnG3Q58K1sCsX/llB6/KXC9Kcf3t33qP2vv+VR9n/++PCjIhr6m/IvIsoP939GEP5BEIlovnn/7sP7P93/6cl688PTD7+8/9n68HD/CP5eQufh6cn69fHe+uHxXQ/aMtU14Wnr8f7N09v3f0KI2T40KS1wlRM7+fJTP6Sauc7vfjf7NKNoBd68RB0yQ4taRDfxHsV+EDXVIB+8RGBgRzwM55T3cdXg8I+3MEzUfrvLnV0z7xTtHhXfX3ts58R5z0ScKMm8l7siFrsOguMAwTF+Vu/SeDX2QWRnln3weyDOxZlZIgRwkQPaM7kOoH5qFyeeX8dT0LFF+OIvfpo1jGuQYLEBDNVqKaA2JL7bt4xJxIHRtfAwK0/z2OYFKgKsM9KUz1T/eXTA2iTrmce/1K6HnWcRGGv25ZNw0NsFKxkOzDZZhMhSr/hv2kOYJTkqQMcBh2tnNnMMCxrpYl8iy7HAUHorDUShn1lHsDjzwDRWrM9uBAQowntxvPiW5gAwJFnm38AQijnfzrx3dlxMqLeR34HOxsUt5o/uvGqaK/F/eZlA8LvfieI6GD7bycW/nNKdHQQ3aoYGgveSJfatQcSea18y3+k7OuUG37oNkniWlyRRkt4KCnwi9H8rdnd6GFL/N3wIof3JK2Zb4PDvgM+wy+zk5GVDDBOPjbzeuxB88z2B70uJIzvn4WGApPpuHQBD5/suBN98X7ngd66orQYE6YYDOPD7O/D994tc8hGbdnycRdQ+OjWY34Gl8PdLRvQrPGB+JWxAcTw9vpegFg3yjGGhpv674yW6K7+9GagJn6iA1v1tXduqx2RrOEne/aX4Zn118UdEpJ/xDH73l+q7G+qIK6olepqcUO/eM7HppRrijWeJbqbXpndH+Ntd+9v6iloV3BKtXY8s3B3r32+qvZuAXNQvr0cF7o7wgbvigbvmgRt019vAXKLJ7UUUGer/KxBuMgQ8/eTXIBY6tDTx2HQsmC4ETImqCH6OQp93YPHmOen38Ndd8XEtPHUMzir/tkI77iP7j4rex2/u3tnx9//yr+9/ffrw65P149uHf9v/y79+eHj/7/dvnuDO77/tipcxcZdnAnY+sJYqNj+EXJ3CjOK+V+IdE1kKT5JykCThCHf5/RC5y79wJBhpzE+nbiFMd4W70AlRgZn5946xqN3BQxB29r3veSQ04PLokPtB5l/upk5OLSKSElPBsOdZGicWgwhMMZj6cPu5MLXUl6Wy1d0MmOvFPnkulNYtNhh3p0u+6wz3B7s60N8xiw7BwdPlQztoN7soO3tJAMT6Hwu6oQVN3qW8hj700hSYxV3gXU7Z+XvUcY41rBBGQ5bYYff5fwJL/Kdqft9Odt7nuJhypqabt/cwFvG+Dm0t1he6rciwQpzwi+rESW1Wzyo82DMEfuWFyg5t1y2OPdnBr6mX3F7ExgUo8tpx8AHWsX9+HjWR1H8Jvr27OzlXlu94JMDsAWN2d8nnF0DrFHqXjI/w06skIvlfwB8NybvPfna+K9aWt/FhKvd+ZuZYSs7xEycP7MT1Yu/iehfnC/lG7XakuoBhwB2tyZZtsZLN8Oj+R0PrK2mi9tl6kgjcY2CfCKYFroMGVVNgum1dLdxIB9/VR/Obb7757g8vYQB5lIlpARdxJxTSAJuKXP9yAl/9+vTTHVh6/6ElVK/l2/RQzi6M3ByMu6mX5fHuTXHf4kP52AfQ8/5Y6K97lHhXnOYFJACx2EuyL48O+O/3RdLyMlAwlCkGbxXt8Jh58e+BNL2/byCl6x3tPMgevSwrjnEsE2/PHyBlA6yAMHcqjJS2McpcUYb/pjpZ/6r/zklgsSd4wRl+LDhXa9tmMAVf1VE0d3qEHWYWWNEY7dh2PlmH7E0pxw3VCW88Wu5hR6HIq3TPDBuo+hrnPlOjg/2V5n317avHt+8+/PL2zdun/7Qen3798e1768PD+w/3D09v7x9fvX7194+vum3z8dXrj+C7j4Cf/eyBoSxyPv3ZTnwbOJgp/Po1/Ac+AP8HZpbYB0+5n36BNIoJovzhdf1hcEOj/vrb+gO83vc+Hr83EXGtfv1H+Q8g8+rHctT7yoD/A7RMiQGeQk1BQ/zX36s8NNBiAL3CFfy26RSFLUAZy4Fhf8jgh31hhL1kCLvyl0I3UeKffLAEbl4uvq26OvhC/Lagl4FZG/4lCbokSIIs/ePbARhovtNY4H1mL4ySL/WodSbgbiqGoCimYBIwn7pMTYPnTpJUw5Q03VgOqJPLwXId16HCYSqSqAAcBIrp4giOLxENDmAXii6Cf5ZaR5lzgkoFoqAbqiAIkryQd3VtlI65KRuyZIricv33075TgdBMTZRUQVuqAYCiVkLZJbyXmAaJLommqIFhYjmObmoAup4p6LKhqKpC0CRFHheYK4YGgSxrmgbGB4GuS3phToNCkRRZExVdXY6iU12KAoCoG4ouq7Ku0enhTDk03ZmyogqGuHSkbvNCUWlBVWTFUMylPaLINQMYJ15llHQYJFOVTUUnsIXm+j7dCKXIpqYqGr73UJ+JgANlnXsBeunLpRdMXRcNU8HuCUjWJGIbiiCopoE9EHQZF5NDtWhv6pYsH4skMDEoprpY9oene+tNFMbRBQZtyCYDoHIwGyjYrklH/M4Q5KcJkejAL5A00O01A3sA6gCop0VizRu6rpumIJIYfMscHtN3PDL9A7dAVQEGTRy3wNT6wQ/tk1el+bP88CTs4suJhLemK6KsgaGXmLVIyBqMtQJYK6hjXwiXs0TKWZTBOCNRyCyTqlvUDFVWJUMZz3JTvMlyMT5GedLkjbGa5SxRF9EERTYMQxz3Tz6YM9Ct8pgS9J2hqcCx0WV8+6LKerlHhwzIRgRDEiVRVhHTAWfslu2EMeHK0jSBXYNV7vqYiQdeQRM1URdk3r1xjPmQJ3ZI5iUqEvAUDFnl3R2RoDOH1KJ14NwbiEUGb9BOmBNCVhUDLFIR60PekGG0idSV0Azd1A3tBqDB45djRGbTpmKKwBngPsUgYIc2gJ4Wh72jhAi9Zqq6oJvi+qO1GwcBYfRFFBUduNzm+qA90g5pAuNWNEVf37a9spo7UXxHNwxTBu796qCPaeKQdcc7xRAV1dCN1X0n6xQ7CenYJ8kmWMtpNxj7ilqgRAOfIciaIIry+uYBMVtxRGjWd7og6Yqg36Azno/Edi1roqCC5fZ4sc8f9AshZlEGqwFdlRGBUd6gfYmsK8qmIYBFLiKmzR2xTeg56ZoEnD1ZHm9GcIfs2M7ZI9OzYpgSWCWu7zV98r6kjn0hdPYMRTHB+LG+QQfA2yPshcBZEoBjra5vIBD0y8Em803vZEWUNLhivBluGB33L4RrdNHUwZBtGDcIKwResZ9C5vUBzKoh3WBaD8hnR0VWFEED5nID0MSzo6LLYEABZrI66ND2g0P0QmbWGjBpWRURO/DcYcf2+UAafALzjaRIwLTXh52STewArQ48PsSuInfEz2SR1DsJLL+Av2eu71rHzoVwOQCmdEMQdXH9FWOcEEZ/TUkzFNFAbPuuANlK/ROASgjdAHOiJMo3CJelDuDknGPbJT31o5omXPOuP4KkHs2ILYMlmKDJ8vrjSEoaLxN1XQcjiYE49MYdM1geHAmPkIqCKIHF2A0M5EtKur8hwt0NVRHM9cc/cif1zlBNWdEEaX3fOqdwU+EpSk1QVWn9gZs8DHwnGoosCyZwV1dH/ezahFYtG9CzvoF9fHYj0jN0hiiBSV1bbcwLq1OQZGEn2VQU2UAcC+eDdnQehHBiEcG8AkYOBrDbMoDwRJWdRaFPGv8HDQ9cfWXBMSpMVN4lJ1su6ZpuCIImMPDTBnoqDrySHoUXASJDZBGe7aMq/yINCoLRRgArNdagYEGYnDD4JMmSJqkii3M4dTmypNt+ZOclNUEUYPSAwbDcRwW9NjsAixISXBJwJMAKEHHThhRVkxekxlfeTyJCpyuSrqq6xgNdXQ2yvD2VeCeftBMoAkDI5HDgdZCE8UEwcGiSbrCzuxG8cTbA5XYo6KBrgCUEg2lgXAl574Spn1pNohqiZoaBElETWSzfJxFWzEmnCE0E05bMwsVGIMx+K65TeS+kM5immjrwpDUG0dNJBcJkDUTrV01VNUlmcbAGhQ3eNHFCWSbUHBgCwRpEMhiEyxHowji37CR8Jjz2KoL1qGroMosdiF7F72r+aK6NkU1wwEERBd00GFjdsB55Hx1RfMrUVUFhcsByopj58MKXE0TOJ9KTt9CJUXSFxX47JlzyQ5WyqBu6ILOI7WBiJT4iB9QqGKapsNg7wMRKfLJF1AVTMUxVWM8GiPcZFd2QVBl1OZEX1Msz8TpYVwRVVRUWbiQKbDOYDq7HpxLZ7RJJN6FuGcyXmGjhjV1CsIamKoams9htxgRbXKslRCsBLxh4w5rJqYch4AYUcMH8qmmGKbDYG8KEW/QystuqoiyrwI1n4AzUWIH31Kx045zsHqmqAf9EZRHa6aKqF48x6bQExqTiqj3DaSmxQ6uoUZDkcQaWOw7MftNt58kHyBoc3pKXFY3FAbB5ESqFT4tA0gyaosiKrrNYNQ3q0rfxIxhdJtbxHTwIreuihEiQwRYioOJ4aWrZRcZRwhFAEDVNFhdcYMXFWkcuO+okCycZoiwCk2U4GiARDrRJ5GAZYGoFwwTD3tWmRGgav/mGqMUV2ZBkXWDa4FcwWmc7qPekyXqTaZqqqYmIi/X8AJd3BIk6lKmA6dREpJ7gh5bcGIB2FUHQ4WVMjnj9AWDSy16yLGqywOIQHAJqPRi0vYvMSZBhGhyVxc7tJEifFqUpwrCjwuIYUA0yd73A/lIbaPkX2fgE1qfQR+ELrQjwaWERH30kWZSYKrzCzDJQVcGs7LDSIJENqoosS6rIYgzyQjd5rvKmFRosP5INNqqga6Yqsbjp0cMFVVbhIuuzhi7pYBnEIjZWAuts3npORLgHBG95KQIMw7OCBW/LNZ540Zy9bwjXu4JuyLrK4hA4CiXUYR8lkS5V2YQ7p6wwVklzCh1WnwkXZMDuYAYZZtqrkUG91ciI5ghdNxRFNxkMxEV6sUJVwM0md63uVHjJVFRZeII9SDC5Apn3JJkwNwvQE2tEUeIRup+GCkxKY3HwtIfII9WRKqiSpukSA1+jD6g8xkg2ZGmmrppL8kXhYSpuUBMhUjTQZKLE4kpKD1FxV5Co3SQwKCm6wF5J8A4MWXY5UwJzDYvNth4eePWCsPfDVEG6yOKoXg9RGZAgC5YLCrwoKWkMYvs9TBRrTOiJylBRjCGRDwBwj14RgJ5YhHJLTIWrF1IkF4KZE0VNUXVm/a2C5Jx9witcoqKohsJkd6CPiDh3iq6p8IglM0tqARWHoWxC51ITDENSTXajd73Op1BWES6B2WBZtx7NqV1dMyRJMZg34IHwbOydDpdYpsziNGDfoigOEavAE5BljcX5oR6mxA5hkXHSw3SGpilw84UxKpojfpJgSIamyixuPw6aLyFbs9+JYMVkiILC4ozuCJJVkCM8UgEvlciCyuSSeQ8Z+TkfXRIFmKCJmQNVI6K54gT8J0OXZIMPKJp55g5mu1c1QzBYj5/EqZ/gGThDAEOowHoEJc5yIuqKDpwplbWZk97dvwMGLqgyk1vlQ0BU1mSYoqCLBvN5hvQuuyjBI39ghGI9dFLc4wUrBVk2NXhnmj0ouMgjdMwlUxNllcVxMwQoqmnmDqz1TKA1gTU2mk05Q9EluN/F2k8gn2dMU5JVYO4MbD0GbRWfwftBsTJu/6TZd4dlHDRZN1gEWzsAod7GAMmGVR0eEWZyfXMOIO0wq8FDAeT9wY7jekcpz/ygUyyk85H4TJsu6aYokXsUV9DBO4K0AAUFLM8EgSL1KATYlNaoocIKQLBiWV0NCH4miyXpArxdSbOmxQdIFjURDdOQNYrJYhJgXUNpWFOJNKBq6CLwAHiochIp0bpTUyVFNyk7zQhnW4dkUJWEJtIJXDwwRlLcI1wGNYkOeUp8J1hTdVGVKC7sLQJLljxMMgXdoDiMTqRPEqTwyLypazTBtiTKIicKOnirUzSHrO1FduyTuRiSJJmyrtLsVeIAJLvQARw0XdNoMjaOsVVnew4nqDKiJZKiqbIGFEexGpmGVTYlkanJmiYAL5vCF5uBVblg/sEP/IzwXJQkiAJwdWSBIjRwDWb2JSZMECqLoqbrAqKKIDUwn6Zd7xRJMRWaHA3X9EV1u7vIc6yCJQDFAuUauGb0INt8ERQV4ENU4mPToNAbdA8wKS1xmFo0VIHi4MrZTtzPduLti+JxzbBbVJIjvzshm7IpyhKieCALXJARLH9KfE7jTpQ1eNSNIgA7wFcbXBcfcfJKXQGzKfkYfA0a8f0NWZVg8QiVAazqvrnTrTFtReAreN+8bmknIj3OIYCJQVIMcm8EE2iTZ4j02jnQpqiZBkWWoSFSRNnq5hLfVEXriR8J+70EM0xReFs4EtUXAJdKRNJKCpg1YSthC1TW5duFLmGAU5BMXRawazLXBSCLqu3ugfDymKRqsqThV4IeciXygQ3TNAQRdeB4vtil9wyIWGf74pLmvVENQ4aZjUnqfPrAnwDtHFYAyPq/JGiiIaKSbhMAIOqsCty1FWRESG4BguLmMl3NUc2UFEExEXdtrlcafrz/+ef7B+vh6cl6A74h3Sc2Td3QNZrFxPAKSK2ceuyt/yac0BTRkBUTVYuYOUIrIQyfwix+qg5TcnEAWQ34jRqJhhtdEVWJaS6SKXyFEokwaqqowoML5CCL0H129oGrF4Op8AsAezrBG3zFjuCz732uuk2n9xCeUAXrDlmhCWEsxUp4XAbO4GB0Ie/fRDolwgrcVlMWFYpI2ghrnPiX7Fj088Y+y+9Ib5qCGVtWaQ77TGGE3WiIkUiNMuhBuqIg5nZaiFSaU4qy6jRhqxlYRG4I3B+GOaUWTr4wd0nhosPSElb5JWleZ80UVJVFXhgYXMyzdvHwHDfLn+eYLFUn8BNVWWJxdvoqOJi24AQzbIC1D9lND7jJr8gKi5Qg15FCIyS8i6JLsLg8Cx/hOkR4m75IK024HpLBsk+VGWXaHeKsl6+kFVnApGsqos4ip+NVdH2TJHOuVUmCFdYYOF3XoZKH7EVN0cGYzCLv23WIRbch1KIsSJquszgmdh0jeVIHQQSDuCmxuHpdQwztNpAPP9M0MnD/RF03WRww78GrxxwID/yT+C+kQUt4DNBUGaUzRuuvAkhmg4ppwHyOFD4VGmB35C5A0swwEtxzUIEdsklafR0lfCDwXiq1WmEeEG6WGPD8mybLrI3zGugqfRdA8df8BLiR3r8DLq0B4+3rQ3ejDM5Qbu6QqR3eWRBFk8nRzaXYyW1FVMC625BZFMNeDNo+Xfwsdz0r/VsOfAKX8LSIqimiqrK42TorQdU1bZcMq6HrogkWSAzn3TmoaU4Ww5dFAZ70ZejFzCGlsGHDkMFKQGdx/QUXLXXHM03oyOqM6pTg2YJjB2QDsw46mCDpLC7z4ILNEvuSxlFKOJMYmmCqCmoLij3iyhbsA+G+iaxKcPOIRRYabKyEI5gI14nAaWORIgwXqxPYIVmwxZAUUxIkliGMebA+GVYYypM0RWZUdgoPbBSTJWMDQ66gG4Yky2s4O4wcNF2FCdBUbcVudvQDsoWHCFwaQTUNfQ0fnnouAwOYIIApYsVB4eIRrzIk6PNKMJf0enCj4zH1CLUrKTKYec1V1kQVXHJP4U4UBJjZSaI5f7kYLqGTC2+aa4phaiwDig3YXqiENDgraoak6wrN8TNshDQhRUk0dFigkMcQMISJCpSQnZgBXpepSauCHgVKyOKPggSztbO4zL4UeXcaJrMVA16cNrjMwzPYyU0FGDhwzjQu8/Ec6FGchEQCU1LAGplJUrJZATphEiLrFuABfkNikWoDFyucQkiw6rohiSaTdJi4UImN+E4FRqxB72c9sPQdT1RhDkQWlaWxbaHwfkjQwko/OkwZvB7YNk5CpF6wgoP3xtaYATthErKNVVWQYQR1RaiEA9gdWGLoYII2WO6pz4EtwyRk460mgHWxwfJQyjxawuyDIty91jWTRX1RbLAwTkICVtNVU9BMeQ03jZl7ZmrAS1BM5lvvV0AXcRLC9ZEmq8AvY1RWGAst+QSsaWC5ISssqmrggq0CJWTrI00zDFHjEpiegFsFSkjgGroC99e4hKYn0JJ7CvBek6YaBstzQrNoCX3cO7Dw0YDXiDgvNHOxI/Avn7wE9G5vF5BdYFLAOlFXRdpT4akf+ICsFQDvY29HL00NsiyAU9GB/Ca0KAq6oqo0dajQCGE6qcQLPDv19ifH2dtJaIWyvK+ScMHfwWNWmtmZ7+xsoiCzLJm6ILEpCNLJwGw7hBs2ogn3x4G7zzorvHs4keYegUeJNSZ7y4Oc8E5CloILXrESdBFxp48OkS8R1l+QwECmSUym4D4g2yVEpIiGopo6uxSGddp8jzzfOTzxBlZbksg6BXsUk+6PqsAXEURG9W26qfOdC3GqH3iACkBi3XIJaZ0KRZQ1xZDZZcetk/kTFvIQTMNQTIVdGsUKz7Nrk1bik2UFjEkGu6T5FaTPbkQ2amsCTAYvMc/eXcxrRHEhQzQE1WA30VaA4LRGFAwWTd2QJJU1nnJSI1zWC7LAPBcunNOI3DpdMkWFfR2IYkojXOgqiiyqksg6x3M9pxHu5YgCQCbprLNil5Ma4V6kaZiSzKQybD+BMZzWyOKBAvCzVV1icSm8n7ufMMe6Kutg6jcpko9OJAomTY+vwOOmhsYiqtcHRKggUVN1HeZSZm3YxTxLqCPFVBWqlDloSMU8S6QkRdZNQ0XEMOYTPsCgRXSBWTccO7MDQgQSGH7AKI2I+cwjcD14675MOOEEkfOJNEGQCTMq6gZiibg08QhZ1TJJFjQwN4znqhn2OzBZ1zdtwUci2YFBqpouIQ7QzF/37ejfjYOA5tKvIsICoiKLw5N1NoYOvDpaNERMev1OMYHZmiyWFCiw1SGpkXpTsturYD5VBEVSVLBw/e9X//j/EgNTzQ===END_SIMPLICITY_STUDIO_METADATA diff --git a/locator_host/locator_host_cmake/toolchain.cmake b/locator_host/locator_host_cmake/toolchain.cmake index cfa8c4e..dec1893 100644 --- a/locator_host/locator_host_cmake/toolchain.cmake +++ b/locator_host/locator_host_cmake/toolchain.cmake @@ -1,86 +1,86 @@ -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR arm) -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -if(WIN32) - set(EXE_SUFFIX ".exe") -else() - set(EXE_SUFFIX "") -endif() - -if(DEFINED ENV{ARM_GCC_DIR}) - set(TOOLCHAIN_DIR "$ENV{ARM_GCC_DIR}/bin/") -elseif(WIN32) - set(TOOLCHAIN_DIR "C:/SiliconLabs/SimplicityStudio/v5/developer/toolchains/gnu_arm/12.2.rel1_2023.7/bin/") -elseif(APPLE) - set(TOOLCHAIN_DIR "/bin/") -else() - set(TOOLCHAIN_DIR "/bin/") -endif() - -if(DEFINED ENV{POST_BUILD_EXE}) - set(POST_BUILD_EXE "$ENV{POST_BUILD_EXE}") -elseif(WIN32) - set(POST_BUILD_EXE "C:/SiliconLabs/SimplicityStudio/v5/developer/adapter_packs/commander/commander.exe") -elseif(APPLE) - set(POST_BUILD_EXE "") -else() - set(POST_BUILD_EXE "") -endif() - -if(DEFINED ENV{NINJA_EXE_PATH}) - set(CMAKE_MAKE_PROGRAM "$ENV{NINJA_EXE_PATH}" CACHE FILEPATH "" FORCE) -elseif(WIN32) - set(NINJA_RUNTIME_PATH "C:/SiliconLabs/SimplicityStudio/v5/developer/adapter_packs/ninja/ninja.exe") -elseif(APPLE) - set(NINJA_RUNTIME_PATH "") -else() - set(NINJA_RUNTIME_PATH "") -endif() -# Use default lookup mechanisms if the OS specific values are not set above -if (NINJA_RUNTIME_PATH) - set(CMAKE_MAKE_PROGRAM ${NINJA_RUNTIME_PATH} CACHE FILEPATH "" FORCE) -endif() - -set(TARGET_TRIPLET "arm-none-eabi-") -set(CMAKE_C_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}g++${EXE_SUFFIX}) -set(CMAKE_ASM_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_LINKER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_AR ${TOOLCHAIN_DIR}${TARGET_TRIPLET}ar${EXE_SUFFIX}) -set(CMAKE_SIZE_UTIL ${TOOLCHAIN_DIR}${TARGET_TRIPLET}size${EXE_SUFFIX}) -set(CMAKE_STRIP ${TOOLCHAIN_DIR}${TARGET_TRIPLET}strip${EXE_SUFFIX}) -set(CMAKE_OBJCOPY ${TOOLCHAIN_DIR}${TARGET_TRIPLET}objcopy${EXE_SUFFIX}) -set(CMAKE_OBJDUMP ${TOOLCHAIN_DIR}${TARGET_TRIPLET}objdump${EXE_SUFFIX}) -set(CMAKE_NM_UTIL ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc-nm${EXE_SUFFIX}) -set(CMAKE_RANLIB ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc-ranlib${EXE_SUFFIX}) -set(CMAKE_GCOV ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcov${EXE_SUFFIX}) - -set(CMAKE_C_STANDARD_REQUIRED OFF) -set(CMAKE_CXX_STANDARD_REQUIRED OFF) -set(CMAKE_C_EXTENSIONS OFF) - -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_C_COMPILER_FORCED TRUE) -set(CMAKE_CXX_COMPILER_FORCED TRUE) -set(CMAKE_EXPORT_COMPILE_COMMANDS ON) - -set(FLAGS_DEBUG_INIT "-Ofast -g3 -DDEBUG=1") -set(FLAGS_RELEASE_INIT "-Ofast -g0") -# Default C compiler flags -set(CMAKE_C_FLAGS_DEBUG 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+set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +set(CMAKE_C_COMPILER_FORCED TRUE) +set(CMAKE_CXX_COMPILER_FORCED TRUE) +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +set(FLAGS_DEBUG_INIT "-Ofast -g3 -DDEBUG=1") +set(FLAGS_RELEASE_INIT "-Ofast -g0") +# Default C compiler flags +set(CMAKE_C_FLAGS_DEBUG "${FLAGS_DEBUG_INIT}") +set(CMAKE_C_FLAGS_RELEASE "${FLAGS_RELEASE_INIT}") +set(CMAKE_C_FLAGS_MINSIZEREL "${FLAGS_RELEASE_INIT}") +set(CMAKE_C_FLAGS_RELWITHDEBINFO "${FLAGS_RELEASE_INIT}") +# Default C++ compiler flags +set(CMAKE_CXX_FLAGS_DEBUG "${FLAGS_DEBUG_INIT}") +set(CMAKE_CXX_FLAGS_RELEASE "${FLAGS_RELEASE_INIT}") +set(CMAKE_CXX_FLAGS_MINSIZEREL "${FLAGS_RELEASE_INIT}") +set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "${FLAGS_RELEASE_INIT}") + +set(CMAKE_EXECUTABLE_SUFFIX .out) +set(CMAKE_EXECUTABLE_SUFFIX_C .out) +set(CMAKE_EXECUTABLE_SUFFIX_CXX .out) diff --git a/locator_host/main.c b/locator_host/main.c index 939ed36..c956e18 100644 --- a/locator_host/main.c +++ b/locator_host/main.c @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief main() function. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_component_catalog.h" -#include "sl_system_init.h" -#include "app.h" -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif // SL_CATALOG_POWER_MANAGER_PRESENT -#if defined(SL_CATALOG_KERNEL_PRESENT) -#include "sl_system_kernel.h" -#else // SL_CATALOG_KERNEL_PRESENT -#include "sl_system_process_action.h" -#endif // SL_CATALOG_KERNEL_PRESENT - -int main(void) -{ - // Initialize Silicon Labs device, system, service(s) and protocol stack(s). - // Note that if the kernel is present, processing task(s) will be created by - // this call. - sl_system_init(); - - // Initialize the application. For example, create periodic timer(s) or - // task(s) if the kernel is present. - app_init(); - -#if defined(SL_CATALOG_KERNEL_PRESENT) - // Start the kernel. Task(s) created in app_init() will start running. - sl_system_kernel_start(); -#else // SL_CATALOG_KERNEL_PRESENT - while (1) { - // Do not remove this call: Silicon Labs components process action routine - // must be called from the super loop. - sl_system_process_action(); - - // Application process. - app_process_action(); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - // Let the CPU go to sleep if the system allows it. - sl_power_manager_sleep(); -#endif - } -#endif // SL_CATALOG_KERNEL_PRESENT -} +/***************************************************************************//** + * @file + * @brief main() function. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_component_catalog.h" +#include "sl_system_init.h" +#include "app.h" +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif // SL_CATALOG_POWER_MANAGER_PRESENT +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "sl_system_kernel.h" +#else // SL_CATALOG_KERNEL_PRESENT +#include "sl_system_process_action.h" +#endif // SL_CATALOG_KERNEL_PRESENT + +int main(void) +{ + // Initialize Silicon Labs device, system, service(s) and protocol stack(s). + // Note that if the kernel is present, processing task(s) will be created by + // this call. + sl_system_init(); + + // Initialize the application. For example, create periodic timer(s) or + // task(s) if the kernel is present. + app_init(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) + // Start the kernel. Task(s) created in app_init() will start running. + sl_system_kernel_start(); +#else // SL_CATALOG_KERNEL_PRESENT + while (1) { + // Do not remove this call: Silicon Labs components process action routine + // must be called from the super loop. + sl_system_process_action(); + + // Application process. + app_process_action(); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Let the CPU go to sleep if the system allows it. + sl_power_manager_sleep(); +#endif + } +#endif // SL_CATALOG_KERNEL_PRESENT +} diff --git a/locator_host/readme.md b/locator_host/readme.md index 0cc8241..81347ce 100644 --- a/locator_host/readme.md +++ b/locator_host/readme.md @@ -1,124 +1,124 @@ -# NCP - Host - -This is a reference implementation of an NCP (Network Co-Processor) host, which is typically run on a central MCU without radio. It can connect to an NCP target via UART to access the Bluetooth stack of the target and to control it using BGAPI. - -This example uses the Dynamic GATT feature, and it must be used together with the **Bluetooth - NCP** target app. - -> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. - -## Getting Started - -To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). - -In the NCP context, the application runs on a host MCU or PC, which is called the **NCP host**, while the Bluetooth stack runs on an EFR32, which is called the **NCP target**. This example application demonstrates an NCP host implementation. Although it is written for an EFR32 device, it can be ported to other MCUs. - -The NCP Host and Target communicate via a serial interface (UART), which can be tunneled either via USB or via Ethernet if you use a development kit. The communication between the NCP host and target is defined in the Silicon Labs proprietary protocol called BGAPI. BGLib is the reference implementation of the BGAPI protocol in C, to be used on the NCP Host side. - -[AN1259: Using the v3.x Silicon Labs Bluetooth Stack in Network Co-Processor Mode](https://www.silabs.com/documents/public/application-notes/an1259-bt-ncp-mode-sdk-v3x.pdf) provides a detailed description how NCP works and how to configure it for your custom hardware. - -The following figure shows the system view of NCP mode: - -![System Block Diagram](image/readme_img1.png) - -## Configuring the Host and Target - -Use this example application with an NCP target application that is run on another mainboard. - -1. Create the NCP target firmware for another mainboard on which you want to run the Bluetooth stack: - - 1. Create a new **Bluetooth - NCP** example project. - 2. In the Project Configurator, find the **UARTDRV USART** component. - 3. Add a new instance with the name 'exp'. This will root the UART pins to the EXP header of the mainboard instead of vcom. - 4. Remove the 'vcom' instance. - 5. Find the **Board Control** component. - 6. In its configuration, disable Virtual COM UART. - 7. Build and flash the project to the target mainboard. - -2. Build the NCP - Host project and flash it to the mainboard. - -3. For UART communication, the TX and RX pins of the host mainboard need to be connected to the RX and TX pins of the target mainboard, respectively. Make sure the following connections are established: - - - *TX* pin (number 12 on the expansion header of the mainboard) of the host is connected to the *RX* pin (number 14 on the expansion header of the mainboard) of the target. - - - *RX* pin (number 14 on the expansion header of the mainboard) of the host is connected to the *TX* pin (number 12 on the expansion header of the mainboard) of the target. - - - *VMCU* pin (number 2 on the expansion header of the mainboard) of the host is connected to the *VMCU* pin (number 2 on the expansion header of the mainboard) of the target. - - - *GND* pin (number 1 on the expansion header of the mainboard) of the host is connected to the *GND* pin (number 1 on the expansion header of the mainboard) of the target. - - ![Connecting the Host and Target mainboards](image/readme_img2.png) - -4. On the host, set the power supply switch into *AEM* position (the kit is powered via USB). On the target, set the power supply switch into *BAT* position. The red rectangles on the previous image show the position of the power supply switches on the host and the target. The VMCU and GND pins are used to power up the NCP target. - -5. Power the NCP host via USB. The NCP host will receive the boot event from the NCP target. The host will send an advertiser_start command to the target. As a result, you should see your NCP target device advertising itself as a Silicon Labs Example. - -## Extending the Host Code - -The Bluetooth event handler in app.c of the NCP host project works the same way as the Bluetooth event handler in app.c of any SoC project. The difference is in the background. The NCP host project sends the command to the target device, while an SoC project executes the command on the SoC device. - -## Extending the GATT Database - -The Host can build up the GATT Database on the Target in runtime with the APIs provided by the Dynamic GATT Database component. - -The Dynamic GATT Database APIs can be used for: - -- Adding / Removing services, characteristics and descriptors. -- Modifying service, characteristic and descriptor properties. -- Maintaining a polymorphic GATT, where the database can be updated at any time. - -This example demonstrates building a minimal GATT database. This can be extended by adding further services using the dynamic GATT API. - -See the Bluetooth API reference manual section "GATT Database" for more details. - -## Troubleshooting - -### Bootloader Issues - -Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either -- flash the proper bootloader or -- remove the DFU functionality from the project. - -**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. - -**If you want to add a bootloader**, then either -- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: - - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader - - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader - - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader - -- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. - - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. - - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. - -**Important Notes:** -- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - -- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. - -- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. - -For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). - - -### Programming the Radio Board - -Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. - -![Radio board power supply switch](image/readme_img0.png) - - -## Resources - -[Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) - -[UG103.14: Bluetooth LE Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-14-fundamentals-ble.pdf) - -[QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf) - -[UG434: Silicon Labs Bluetooth ® C Application Developer's Guide for SDK v3.x](https://www.silabs.com/documents/public/user-guides/ug434-bluetooth-c-soc-dev-guide-sdk-v3x.pdf) - -[Bluetooth Training](https://www.silabs.com/support/training/bluetooth) - -## Report Bugs & Get Support - -You are always encouraged and welcome to report any issues you found to us via [Silicon Labs Community](https://www.silabs.com/community). +# NCP - Host + +This is a reference implementation of an NCP (Network Co-Processor) host, which is typically run on a central MCU without radio. It can connect to an NCP target via UART to access the Bluetooth stack of the target and to control it using BGAPI. + +This example uses the Dynamic GATT feature, and it must be used together with the **Bluetooth - NCP** target app. + +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + +## Getting Started + +To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). + +In the NCP context, the application runs on a host MCU or PC, which is called the **NCP host**, while the Bluetooth stack runs on an EFR32, which is called the **NCP target**. This example application demonstrates an NCP host implementation. Although it is written for an EFR32 device, it can be ported to other MCUs. + +The NCP Host and Target communicate via a serial interface (UART), which can be tunneled either via USB or via Ethernet if you use a development kit. The communication between the NCP host and target is defined in the Silicon Labs proprietary protocol called BGAPI. BGLib is the reference implementation of the BGAPI protocol in C, to be used on the NCP Host side. + +[AN1259: Using the v3.x Silicon Labs Bluetooth Stack in Network Co-Processor Mode](https://www.silabs.com/documents/public/application-notes/an1259-bt-ncp-mode-sdk-v3x.pdf) provides a detailed description how NCP works and how to configure it for your custom hardware. + +The following figure shows the system view of NCP mode: + +![System Block Diagram](image/readme_img1.png) + +## Configuring the Host and Target + +Use this example application with an NCP target application that is run on another mainboard. + +1. Create the NCP target firmware for another mainboard on which you want to run the Bluetooth stack: + + 1. Create a new **Bluetooth - NCP** example project. + 2. In the Project Configurator, find the **UARTDRV USART** component. + 3. Add a new instance with the name 'exp'. This will root the UART pins to the EXP header of the mainboard instead of vcom. + 4. Remove the 'vcom' instance. + 5. Find the **Board Control** component. + 6. In its configuration, disable Virtual COM UART. + 7. Build and flash the project to the target mainboard. + +2. Build the NCP - Host project and flash it to the mainboard. + +3. For UART communication, the TX and RX pins of the host mainboard need to be connected to the RX and TX pins of the target mainboard, respectively. Make sure the following connections are established: + + - *TX* pin (number 12 on the expansion header of the mainboard) of the host is connected to the *RX* pin (number 14 on the expansion header of the mainboard) of the target. + + - *RX* pin (number 14 on the expansion header of the mainboard) of the host is connected to the *TX* pin (number 12 on the expansion header of the mainboard) of the target. + + - *VMCU* pin (number 2 on the expansion header of the mainboard) of the host is connected to the *VMCU* pin (number 2 on the expansion header of the mainboard) of the target. + + - *GND* pin (number 1 on the expansion header of the mainboard) of the host is connected to the *GND* pin (number 1 on the expansion header of the mainboard) of the target. + + ![Connecting the Host and Target mainboards](image/readme_img2.png) + +4. On the host, set the power supply switch into *AEM* position (the kit is powered via USB). On the target, set the power supply switch into *BAT* position. The red rectangles on the previous image show the position of the power supply switches on the host and the target. The VMCU and GND pins are used to power up the NCP target. + +5. Power the NCP host via USB. The NCP host will receive the boot event from the NCP target. The host will send an advertiser_start command to the target. As a result, you should see your NCP target device advertising itself as a Silicon Labs Example. + +## Extending the Host Code + +The Bluetooth event handler in app.c of the NCP host project works the same way as the Bluetooth event handler in app.c of any SoC project. The difference is in the background. The NCP host project sends the command to the target device, while an SoC project executes the command on the SoC device. + +## Extending the GATT Database + +The Host can build up the GATT Database on the Target in runtime with the APIs provided by the Dynamic GATT Database component. + +The Dynamic GATT Database APIs can be used for: + +- Adding / Removing services, characteristics and descriptors. +- Modifying service, characteristic and descriptor properties. +- Maintaining a polymorphic GATT, where the database can be updated at any time. + +This example demonstrates building a minimal GATT database. This can be extended by adding further services using the dynamic GATT API. + +See the Bluetooth API reference manual section "GATT Database" for more details. + +## Troubleshooting + +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. + +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. + +- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. + +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. + +![Radio board power supply switch](image/readme_img0.png) + + +## Resources + +[Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) + +[UG103.14: Bluetooth LE Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-14-fundamentals-ble.pdf) + +[QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf) + +[UG434: Silicon Labs Bluetooth ® C Application Developer's Guide for SDK v3.x](https://www.silabs.com/documents/public/user-guides/ug434-bluetooth-c-soc-dev-guide-sdk-v3x.pdf) + +[Bluetooth Training](https://www.silabs.com/support/training/bluetooth) + +## Report Bugs & Get Support + +You are always encouraged and welcome to report any issues you found to us via [Silicon Labs Community](https://www.silabs.com/community). diff --git a/locator_host/sl_system_config.h b/locator_host/sl_system_config.h index 9c38efb..dc91f95 100644 --- a/locator_host/sl_system_config.h +++ b/locator_host/sl_system_config.h @@ -1,67 +1,67 @@ -/***************************************************************************//** - * @file - * @brief - * @version 1.0.0 - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef SL_SYSTEM_CONFIG_H -#define SL_SYSTEM_CONFIG_H -#ifdef __cplusplus -extern "C" { -#endif -#include "printf.h" -#include "em_core.h" - -//macros ----------------------------------------------------------------------- -///Defines whether the angle calculations is enabled or not -#define SYSTEM_BT_AOA_ANGLE_CALCULATION_EN 1 - -///Maximum allowed tag number. If angle is not calculated then it can be higher only the UART/MQTT processing will limit. If angle calculation is enabled then heap will limit as well. -#if SYSTEM_BT_AOA_ANGLE_CALCULATION_EN - #define SYSTEM_BT_AOA_MAX_TAG_COUNT 8 -#else - #define SYSTEM_BT_AOA_MAX_TAG_COUNT 10 -#endif - -//IQ sample providing possibilities, raw bytes is the fastest. -#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_RAW_BYTES 0 -#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON 1 -///Selected IQ sample providing method -#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON - -//Utility macros for number to string transformation -#define __SYSTEM_NUM_TO_STR(x) #x -#define SYSTEM_NUM_TO_STR(x) __SYSTEM_NUM_TO_STR(x) - -///Compile time assert macro -#define SYSTEM_STATIC_ASSERT(condition) typedef char assert[(condition) ? 1 : -1] - -///Assert function which shall be used by the application -#define SYSTEM_ASSERT(condition, ...) \ - do { \ - if (!(condition)) { \ - CORE_EnterAtomic(); /*Disable interrupts*/ \ - printf("ASSERT!\r\n " __FILE__ ":" SYSTEM_NUM_TO_STR(__LINE__) "\r\n " __VA_ARGS__); \ - while (1) ; \ - } \ - } while (0) - -//type definitions ------------------------------------------------------------- -//global variables ------------------------------------------------------------- -//function prototypes ---------------------------------------------------------- - -#ifdef __cplusplus -} -#endif -#endif /* SL_SYSTEM_CONFIG_H */ +/***************************************************************************//** + * @file + * @brief + * @version 1.0.0 + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_CONFIG_H +#define SL_SYSTEM_CONFIG_H +#ifdef __cplusplus +extern "C" { +#endif +#include "printf.h" +#include "em_core.h" + +//macros ----------------------------------------------------------------------- +///Defines whether the angle calculations is enabled or not +#define SYSTEM_BT_AOA_ANGLE_CALCULATION_EN 1 + +///Maximum allowed tag number. If angle is not calculated then it can be higher only the UART/MQTT processing will limit. If angle calculation is enabled then heap will limit as well. +#if SYSTEM_BT_AOA_ANGLE_CALCULATION_EN + #define SYSTEM_BT_AOA_MAX_TAG_COUNT 8 +#else + #define SYSTEM_BT_AOA_MAX_TAG_COUNT 10 +#endif + +//IQ sample providing possibilities, raw bytes is the fastest. +#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_RAW_BYTES 0 +#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON 1 +///Selected IQ sample providing method +#define SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD SYSTEM_AOA_IQ_SAMPLE_PROVIDE_METHOD_JSON + +//Utility macros for number to string transformation +#define __SYSTEM_NUM_TO_STR(x) #x +#define SYSTEM_NUM_TO_STR(x) __SYSTEM_NUM_TO_STR(x) + +///Compile time assert macro +#define SYSTEM_STATIC_ASSERT(condition) typedef char assert[(condition) ? 1 : -1] + +///Assert function which shall be used by the application +#define SYSTEM_ASSERT(condition, ...) \ + do { \ + if (!(condition)) { \ + CORE_EnterAtomic(); /*Disable interrupts*/ \ + printf("ASSERT!\r\n " __FILE__ ":" SYSTEM_NUM_TO_STR(__LINE__) "\r\n " __VA_ARGS__); \ + while (1) ; \ + } \ + } while (0) + +//type definitions ------------------------------------------------------------- +//global variables ------------------------------------------------------------- +//function prototypes ---------------------------------------------------------- + +#ifdef __cplusplus +} +#endif +#endif /* SL_SYSTEM_CONFIG_H */ diff --git a/locator_host/tools/mqtt_forwarder/README.md b/locator_host/tools/mqtt_forwarder/README.md index 50bab43..c081302 100644 --- a/locator_host/tools/mqtt_forwarder/README.md +++ b/locator_host/tools/mqtt_forwarder/README.md @@ -1,7 +1,7 @@ -# Usage - -Steps: -1. Install the needed modules (only once if wasn't yet executed): - `pip install -r requirements.txt` -2. Run the python script `python main.py`. - With the `python main.py --help` command you can query the available arguments for customization. +# Usage + +Steps: +1. Install the needed modules (only once if wasn't yet executed): + `pip install -r requirements.txt` +2. Run the python script `python main.py`. + With the `python main.py --help` command you can query the available arguments for customization. diff --git a/locator_host/tools/mqtt_forwarder/main.py b/locator_host/tools/mqtt_forwarder/main.py index e0501cd..4621099 100644 --- a/locator_host/tools/mqtt_forwarder/main.py +++ b/locator_host/tools/mqtt_forwarder/main.py @@ -1,34 +1,34 @@ -import argparse -from mqtt import Mqtt -from rtt_viewer import RttViewer - -parser = argparse.ArgumentParser(description='Reads RTT debug strings from a JLink device and forwards it to an MQTT broker.') -parser.add_argument('--mqttBrokerAddress', type=str, default = 'localhost', help='Address of the MQTT broker (hostname or IP).') -parser.add_argument('--jlinkDir', type=str, default = 'C:/Program Files/SEGGER/JLink', help='Directory path of the SEGGER JLink.') -parser.add_argument('--device', type=str, default = 'EFR32MG24BXXXF1536', help='Silabs MCU device part number.') -parser.add_argument('--interface', type=str, default = 'SWD', help='Debug interface to use. Can be SWD or JTAG.') -parser.add_argument('--speed', type=int, default = 10000, help='Debug interface speed in kHz.') -parser.add_argument('--serialNo', type=str, default = '', help='Serial number of the JLink device to connect to.') -args = parser.parse_args() - -mqttClient = Mqtt(broker_address=args.mqttBrokerAddress) -rttClient = RttViewer(jlink_directory_path = args.jlinkDir, - device_pn = args.device, - interface = args.interface, - speed = args.speed, - serial_no = args.serialNo) - -string_buffer = '' -NEEDLE_TOPIC_START = 'Topic: ' -NEEDLE_MESSAGE_START = '{' -NEEDLE_MESSAGE_END = '}' -while True: - string_buffer += rttClient.read_line() - if NEEDLE_MESSAGE_END in string_buffer: - topic_idx = string_buffer.rfind(NEEDLE_TOPIC_START) - message_idx = string_buffer.rfind(NEEDLE_MESSAGE_START) - if(topic_idx != -1 and message_idx != -1): - topic = string_buffer[topic_idx + len(NEEDLE_TOPIC_START):message_idx].strip() - message = string_buffer[message_idx:].strip() - mqttClient.publish(topic, message) - string_buffer = '' +import argparse +from mqtt import Mqtt +from rtt_viewer import RttViewer + +parser = argparse.ArgumentParser(description='Reads RTT debug strings from a JLink device and forwards it to an MQTT broker.') +parser.add_argument('--mqttBrokerAddress', type=str, default = 'localhost', help='Address of the MQTT broker (hostname or IP).') +parser.add_argument('--jlinkDir', type=str, default = 'C:/Program Files/SEGGER/JLink', help='Directory path of the SEGGER JLink.') +parser.add_argument('--device', type=str, default = 'EFR32MG24BXXXF1536', help='Silabs MCU device part number.') +parser.add_argument('--interface', type=str, default = 'SWD', help='Debug interface to use. Can be SWD or JTAG.') +parser.add_argument('--speed', type=int, default = 10000, help='Debug interface speed in kHz.') +parser.add_argument('--serialNo', type=str, default = '', help='Serial number of the JLink device to connect to.') +args = parser.parse_args() + +mqttClient = Mqtt(broker_address=args.mqttBrokerAddress) +rttClient = RttViewer(jlink_directory_path = args.jlinkDir, + device_pn = args.device, + interface = args.interface, + speed = args.speed, + serial_no = args.serialNo) + +string_buffer = '' +NEEDLE_TOPIC_START = 'Topic: ' +NEEDLE_MESSAGE_START = '{' +NEEDLE_MESSAGE_END = '}' +while True: + string_buffer += rttClient.read_line() + if NEEDLE_MESSAGE_END in string_buffer: + topic_idx = string_buffer.rfind(NEEDLE_TOPIC_START) + message_idx = string_buffer.rfind(NEEDLE_MESSAGE_START) + if(topic_idx != -1 and message_idx != -1): + topic = string_buffer[topic_idx + len(NEEDLE_TOPIC_START):message_idx].strip() + message = string_buffer[message_idx:].strip() + mqttClient.publish(topic, message) + string_buffer = '' diff --git a/locator_host/tools/mqtt_forwarder/mqtt.py b/locator_host/tools/mqtt_forwarder/mqtt.py index 09b8b18..7e728a5 100644 --- a/locator_host/tools/mqtt_forwarder/mqtt.py +++ b/locator_host/tools/mqtt_forwarder/mqtt.py @@ -1,13 +1,13 @@ -import paho.mqtt.client as mqtt - -class Mqtt: - def __init__(self, broker_address: str): - print(f'Connecting to MQTT broker at {broker_address}') - self._client = mqtt.Client(mqtt.CallbackAPIVersion.VERSION2) - self._client.connect(broker_address) - self._client.loop_start() - - def publish(self, topic: str, message: str): - print(f'MQTT Publish!\n Topic: {topic}\n Message: {message}') - msg_info = self._client.publish(topic, message, qos=1) - msg_info.wait_for_publish() +import paho.mqtt.client as mqtt + +class Mqtt: + def __init__(self, broker_address: str): + print(f'Connecting to MQTT broker at {broker_address}') + self._client = mqtt.Client(mqtt.CallbackAPIVersion.VERSION2) + self._client.connect(broker_address) + self._client.loop_start() + + def publish(self, topic: str, message: str): + print(f'MQTT Publish!\n Topic: {topic}\n Message: {message}') + msg_info = self._client.publish(topic, message, qos=1) + msg_info.wait_for_publish() diff --git a/locator_host/tools/mqtt_forwarder/requirements.txt b/locator_host/tools/mqtt_forwarder/requirements.txt index 2ac1e6d..a151c9b 100644 --- a/locator_host/tools/mqtt_forwarder/requirements.txt +++ b/locator_host/tools/mqtt_forwarder/requirements.txt @@ -1 +1 @@ -paho-mqtt==2.0.0 +paho-mqtt==2.0.0 diff --git a/locator_host/tools/mqtt_forwarder/rtt_viewer.py b/locator_host/tools/mqtt_forwarder/rtt_viewer.py index ca5dd4d..756d4c0 100644 --- a/locator_host/tools/mqtt_forwarder/rtt_viewer.py +++ b/locator_host/tools/mqtt_forwarder/rtt_viewer.py @@ -1,27 +1,27 @@ -import os -import subprocess - -class RttViewer: - COMMAND_FILE_NAME = 'jlink_command.jlink' - - def __init__(self, jlink_directory_path: str, device_pn: str, interface: str = 'SWD', speed: int = 10000, serial_no: str = ''): - with open(self.COMMAND_FILE_NAME, 'w') as f: - f.write(f'Device {device_pn}\nSelectInterface {interface}\nSpeed {speed}\nconnect\n') - usb_serial = f'USB {serial_no}' if serial_no else '' - self._jlink_proc = subprocess.Popen(f'{jlink_directory_path}/JLink {usb_serial} -CommandFile {self.COMMAND_FILE_NAME}', stdout=subprocess.PIPE) - self._rtt_client_proc = subprocess.Popen(f'{jlink_directory_path}/JLinkRTTClient', stdout=subprocess.PIPE) - - def __del__(self): - print('Cleaning up!') - if hasattr(self, '_jlink_proc'): - self._jlink_proc.kill() - if hasattr(self, '_rtt_client_proc'): - self._rtt_client_proc.kill() - if os.path.exists(self.COMMAND_FILE_NAME): - os.remove(self.COMMAND_FILE_NAME) - - def read(self) -> str: - return self._rtt_client_proc.stdout.read().decode('utf-8').strip() - - def read_line(self) -> str: - return self._rtt_client_proc.stdout.readline().decode('utf-8').strip() +import os +import subprocess + +class RttViewer: + COMMAND_FILE_NAME = 'jlink_command.jlink' + + def __init__(self, jlink_directory_path: str, device_pn: str, interface: str = 'SWD', speed: int = 10000, serial_no: str = ''): + with open(self.COMMAND_FILE_NAME, 'w') as f: + f.write(f'Device {device_pn}\nSelectInterface {interface}\nSpeed {speed}\nconnect\n') + usb_serial = f'USB {serial_no}' if serial_no else '' + self._jlink_proc = subprocess.Popen(f'{jlink_directory_path}/JLink {usb_serial} -CommandFile {self.COMMAND_FILE_NAME}', stdout=subprocess.PIPE) + self._rtt_client_proc = subprocess.Popen(f'{jlink_directory_path}/JLinkRTTClient', stdout=subprocess.PIPE) + + def __del__(self): + print('Cleaning up!') + if hasattr(self, '_jlink_proc'): + self._jlink_proc.kill() + if hasattr(self, '_rtt_client_proc'): + self._rtt_client_proc.kill() + if os.path.exists(self.COMMAND_FILE_NAME): + os.remove(self.COMMAND_FILE_NAME) + + def read(self) -> str: + return self._rtt_client_proc.stdout.read().decode('utf-8').strip() + + def read_line(self) -> str: + return self._rtt_client_proc.stdout.readline().decode('utf-8').strip() diff --git a/locator_ncp/Makefile b/locator_ncp/Makefile index 79621e0..f88c94f 100644 --- a/locator_ncp/Makefile +++ b/locator_ncp/Makefile @@ -1,16 +1,16 @@ -.SUFFIXES: # ignore builtin rules -.PHONY: clean configure build clean_build - -TYPE ?= Debug #Release - -clean_build: clean configure build - -clean: - @echo 'Cleaning every build directory!' - rm -rf build -configure: - @echo 'CMAKE configure...!' - cmake locator_ncp_cmake -B build -G "Ninja" -DCMAKE_BUILD_TYPE:STRING=${TYPE} -DCMAKE_TOOLCHAIN_FILE:STRING=toolchain.cmake -build: - @echo 'CMAKE build...!' - cmake --build build --parallel --config ${TYPE} +.SUFFIXES: # ignore builtin rules +.PHONY: clean configure build clean_build + +TYPE ?= Debug #Release + +clean_build: clean configure build + +clean: + @echo 'Cleaning every build directory!' + rm -rf build +configure: + @echo 'CMAKE configure...!' + cmake locator_ncp_cmake -B build -G "Ninja" -DCMAKE_BUILD_TYPE:STRING=${TYPE} -DCMAKE_TOOLCHAIN_FILE:STRING=toolchain.cmake +build: + @echo 'CMAKE build...!' + cmake --build build --parallel --config ${TYPE} diff --git a/locator_ncp/app.c b/locator_ncp/app.c index 98519bc..0508e26 100644 --- a/locator_ncp/app.c +++ b/locator_ncp/app.c @@ -1,121 +1,121 @@ -/***************************************************************************//** - * @file - * @brief Core application logic. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_common.h" -#include "sl_ncp.h" -#include "app.h" - -/***************************************************************************//** - * Application Init. - ******************************************************************************/ -SL_WEAK void app_init(void) -{ - ///////////////////////////////////////////////////////////////////////////// - // Put your additional application init code here! // - // This is called once during start-up. // - ///////////////////////////////////////////////////////////////////////////// -} - -/**************************************************************************//** - * Application Process Action. - *****************************************************************************/ -SL_WEAK void app_process_action(void) -{ - ///////////////////////////////////////////////////////////////////////////// - // Put your additional application code here! // - // This is called infinitely. // - // Do not call blocking functions from here! // - ///////////////////////////////////////////////////////////////////////////// -} - -/***************************************************************************//** - * User command (message_to_target) handler callback. - * - * Handles user defined commands received from NCP host. - * The user commands handled here are defined in app.h and are solely meant for - * example purposes. - * @param[in] data Data received from NCP host. - * - * @note This overrides the dummy weak implementation. - ******************************************************************************/ -void sl_ncp_user_cmd_message_to_target_cb(void *data) -{ - uint8array *cmd = (uint8array *)data; - user_cmd_t *user_cmd = (user_cmd_t *)cmd->data; - - switch (user_cmd->hdr) { - // ------------------------------- - // Example: user command 1. - case USER_CMD_1_ID: - ////////////////////////////////////////////// - // Add your user command handler code here! // - ////////////////////////////////////////////// - - // Send response to user command 1 to NCP host. - // Example: sending back received command. - sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, cmd->len, cmd->data); - break; - - // ------------------------------- - // Example: user command 2. - case USER_CMD_2_ID: - ////////////////////////////////////////////// - // Add your user command handler code here! // - ////////////////////////////////////////////// - - // Send response to user command 2 to NCP host. - // Example: sending back received command. - sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, cmd->len, cmd->data); - // Send user event too. - // Example: sending back received command as an event. - sl_ncp_user_evt_message_to_host(cmd->len, cmd->data); - break; - - // ------------------------------- - case BOARD_CMD_ID: -#ifdef SL_BOARD_NAME - // Send board name to NCP host. - sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, - BOARD_RSP_DATA_LEN, - (uint8_t *)SL_BOARD_NAME); -#else - sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_NOT_SUPPORTED, - 0, - (uint8_t *)""); -#endif - break; - - // ------------------------------- - // Unknown user command. - default: - // Send error response to NCP host. - sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_FAIL, 0, NULL); - break; - } -} +/***************************************************************************//** + * @file + * @brief Core application logic. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_common.h" +#include "sl_ncp.h" +#include "app.h" + +/***************************************************************************//** + * Application Init. + ******************************************************************************/ +SL_WEAK void app_init(void) +{ + ///////////////////////////////////////////////////////////////////////////// + // Put your additional application init code here! // + // This is called once during start-up. // + ///////////////////////////////////////////////////////////////////////////// +} + +/**************************************************************************//** + * Application Process Action. + *****************************************************************************/ +SL_WEAK void app_process_action(void) +{ + ///////////////////////////////////////////////////////////////////////////// + // Put your additional application code here! // + // This is called infinitely. // + // Do not call blocking functions from here! // + ///////////////////////////////////////////////////////////////////////////// +} + +/***************************************************************************//** + * User command (message_to_target) handler callback. + * + * Handles user defined commands received from NCP host. + * The user commands handled here are defined in app.h and are solely meant for + * example purposes. + * @param[in] data Data received from NCP host. + * + * @note This overrides the dummy weak implementation. + ******************************************************************************/ +void sl_ncp_user_cmd_message_to_target_cb(void *data) +{ + uint8array *cmd = (uint8array *)data; + user_cmd_t *user_cmd = (user_cmd_t *)cmd->data; + + switch (user_cmd->hdr) { + // ------------------------------- + // Example: user command 1. + case USER_CMD_1_ID: + ////////////////////////////////////////////// + // Add your user command handler code here! // + ////////////////////////////////////////////// + + // Send response to user command 1 to NCP host. + // Example: sending back received command. + sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, cmd->len, cmd->data); + break; + + // ------------------------------- + // Example: user command 2. + case USER_CMD_2_ID: + ////////////////////////////////////////////// + // Add your user command handler code here! // + ////////////////////////////////////////////// + + // Send response to user command 2 to NCP host. + // Example: sending back received command. + sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, cmd->len, cmd->data); + // Send user event too. + // Example: sending back received command as an event. + sl_ncp_user_evt_message_to_host(cmd->len, cmd->data); + break; + + // ------------------------------- + case BOARD_CMD_ID: +#ifdef SL_BOARD_NAME + // Send board name to NCP host. + sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_OK, + BOARD_RSP_DATA_LEN, + (uint8_t *)SL_BOARD_NAME); +#else + sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_NOT_SUPPORTED, + 0, + (uint8_t *)""); +#endif + break; + + // ------------------------------- + // Unknown user command. + default: + // Send error response to NCP host. + sl_ncp_user_cmd_message_to_target_rsp(SL_STATUS_FAIL, 0, NULL); + break; + } +} diff --git a/locator_ncp/app.h b/locator_ncp/app.h index 6fffff0..e40ba5a 100644 --- a/locator_ncp/app.h +++ b/locator_ncp/app.h @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief Application interface provided to main(). - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_H -#define APP_H - -#include "sl_bt_api.h" - -// Example: user command 1. -#define USER_CMD_1_ID 0x01 -typedef uint8_t cmd_1_t[16]; - -// Example: user command 2. -#define USER_CMD_2_ID 0x02 -typedef uint8_t cmd_2_t[8]; - -// Get Board Name command. -#define BOARD_CMD_ID 0x03 -#define BOARD_RSP_DATA_LEN 8 - -PACKSTRUCT(struct user_cmd { - uint8_t hdr; - // Example: union of user commands. - union { - cmd_1_t cmd_1; - cmd_2_t cmd_2; - } data; -}); - -typedef struct user_cmd user_cmd_t; - -/**************************************************************************//** - * Application Init. - *****************************************************************************/ -void app_init(void); - -/**************************************************************************//** - * Application Process Action. - *****************************************************************************/ -void app_process_action(void); - -#endif // APP_H +/***************************************************************************//** + * @file + * @brief Application interface provided to main(). + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_H +#define APP_H + +#include "sl_bt_api.h" + +// Example: user command 1. +#define USER_CMD_1_ID 0x01 +typedef uint8_t cmd_1_t[16]; + +// Example: user command 2. +#define USER_CMD_2_ID 0x02 +typedef uint8_t cmd_2_t[8]; + +// Get Board Name command. +#define BOARD_CMD_ID 0x03 +#define BOARD_RSP_DATA_LEN 8 + +PACKSTRUCT(struct user_cmd { + uint8_t hdr; + // Example: union of user commands. + union { + cmd_1_t cmd_1; + cmd_2_t cmd_2; + } data; +}); + +typedef struct user_cmd user_cmd_t; + +/**************************************************************************//** + * Application Init. + *****************************************************************************/ +void app_init(void); + +/**************************************************************************//** + * Application Process Action. + *****************************************************************************/ +void app_process_action(void); + +#endif // APP_H diff --git a/locator_ncp/autogen/RTE_Components.h b/locator_ncp/autogen/RTE_Components.h index aa62dc4..9dc9cd4 100644 --- a/locator_ncp/autogen/RTE_Components.h +++ b/locator_ncp/autogen/RTE_Components.h @@ -1,22 +1,22 @@ -// This file is autogenerated by Simplicity Configuration Tools. -// The contents of this file will be replaced in their entirety upon regeneration. -// -// Source template file: RTE_Components.h.jinja - - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -/* standard device header from emlib */ -#define CMSIS_device_header "em_device.h" - -/* components are auto-generated here */ - - -#endif /* RTE_COMPONENTS_H */ - -/* This file is autogenerated by Simplicity Configuration Tools. */ -/* The contents of this file will be replaced in their entirety upon regeneration. */ -/* */ -/* Source template file: RTE_Components.h.jinja */ - +// This file is autogenerated by Simplicity Configuration Tools. +// The contents of this file will be replaced in their entirety upon regeneration. +// +// Source template file: RTE_Components.h.jinja + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +/* standard device header from emlib */ +#define CMSIS_device_header "em_device.h" + +/* components are auto-generated here */ + + +#endif /* RTE_COMPONENTS_H */ + +/* This file is autogenerated by Simplicity Configuration Tools. */ +/* The contents of this file will be replaced in their entirety upon regeneration. */ +/* */ +/* Source template file: RTE_Components.h.jinja */ + diff --git a/locator_ncp/autogen/linkerfile.ld b/locator_ncp/autogen/linkerfile.ld index cc4a611..add8a9b 100644 --- a/locator_ncp/autogen/linkerfile.ld +++ b/locator_ncp/autogen/linkerfile.ld @@ -1,250 +1,250 @@ -/***************************************************************************//** - * GCC Linker script for Silicon Labs devices - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - MEMORY - { - FLASH (rx) : ORIGIN = 0x6000, LENGTH = 0x78000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 - } - -ENTRY(Reset_Handler) - -SECTIONS -{ - - .text : - { - linker_vectors_begin = .; - KEEP(*(.vectors)) - linker_vectors_end = .; - - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - - linker_code_begin = .; - *(SORT_BY_ALIGNMENT(.text*)) - . = ALIGN(32); - linker_code_end = .; - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - __code_classification_validator_start__ = .; - . = . + 0x20; - *(code_classification_validator) - . = ALIGN(32); - __code_classification_validator_end__ = .; - - *(.rodata*) - *(.eh_frame*) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - __etext = .; - - /* Start placing output sections which are loaded into RAM */ - . = ORIGIN(RAM); - - .stack ALIGN(8) (NOLOAD): - { - __StackLimit = .; - KEEP(*(.stack*)) - . = ALIGN(4); - __StackTop = .; - PROVIDE(__stack = __StackTop); - } > RAM - - - .noinit . (NOLOAD): - { - *(.noinit*); - } > RAM - - .data . : AT (__etext) - { - . = ALIGN(4); - __data_start__ = .; - *(vtable) - *(SORT_BY_ALIGNMENT(.data*)) - . = ALIGN(4); - - PROVIDE(__ram_func_section_start = .); - *(.ram) - PROVIDE(__ram_func_section_end = .); - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss . : - { - . = ALIGN(4); - __bss_start__ = .; - *(SORT_BY_ALIGNMENT(.bss*)) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - __ramfuncs_start__ = .; - - __vma_ramfuncs_start__ = .; - __lma_ramfuncs_start__ = __etext + SIZEOF(.data); - - __text_application_ram_offset__ = . - __vma_ramfuncs_start__; - text_application_ram . : AT(__lma_ramfuncs_start__ + __text_application_ram_offset__) - { - . = ALIGN(4); - __text_application_ram_start__ = .; - *(text_application_ram) - . = ALIGN(4); - __text_application_ram_end__ = .; - } > RAM - - . = ALIGN(4); - __vma_ramfuncs_end__ = .; - __lma_ramfuncs_end__ = __lma_ramfuncs_start__ + __text_application_ram_offset__ + SIZEOF(text_application_ram); - - __ramfuncs_end__ = .; - - .heap (COPY): - { - __HeapBase = .; - __end__ = .; - end = __end__; - _end = __end__; - KEEP(*(.heap*)) - __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); - } > RAM - - __heap_size = __HeapLimit - __HeapBase; - __ram_end__ = 0x20000000 + 0x8000; - __main_flash_end__ = 0x6000 + 0x78000; - - /* This is where we handle flash storage blocks. We use dummy sections for finding the configured - * block sizes and then "place" them at the end of flash when the size is known. */ - .internal_storage (DSECT) : { - KEEP(*(.internal_storage*)) - } > FLASH - - - .nvm (DSECT) : { - KEEP(*(.simee*)) - } > FLASH - - linker_nvm_end = __main_flash_end__; - linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); - linker_nvm_size = SIZEOF(.nvm); - linker_storage_end = linker_nvm_begin; - __nvm3Base = linker_nvm_begin; - - linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); - linker_storage_size = SIZEOF(.internal_storage); - ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") - - - app_flash_end = 0x6000 + 0x78000; - ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= app_flash_end, "NVM3 is excessing the flash size !") -} +/***************************************************************************//** + * GCC Linker script for Silicon Labs devices + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + MEMORY + { + FLASH (rx) : ORIGIN = 0x6000, LENGTH = 0x78000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 + } + +ENTRY(Reset_Handler) + +SECTIONS +{ + + .text : + { + linker_vectors_begin = .; + KEEP(*(.vectors)) + linker_vectors_end = .; + + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + + linker_code_begin = .; + *(SORT_BY_ALIGNMENT(.text*)) + . = ALIGN(32); + linker_code_end = .; + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + __code_classification_validator_start__ = .; + . = . + 0x20; + *(code_classification_validator) + . = ALIGN(32); + __code_classification_validator_end__ = .; + + *(.rodata*) + *(.eh_frame*) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + __etext = .; + + /* Start placing output sections which are loaded into RAM */ + . = ORIGIN(RAM); + + .stack ALIGN(8) (NOLOAD): + { + __StackLimit = .; + KEEP(*(.stack*)) + . = ALIGN(4); + __StackTop = .; + PROVIDE(__stack = __StackTop); + } > RAM + + + .noinit . (NOLOAD): + { + *(.noinit*); + } > RAM + + .data . : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(SORT_BY_ALIGNMENT(.data*)) + . = ALIGN(4); + + PROVIDE(__ram_func_section_start = .); + *(.ram) + PROVIDE(__ram_func_section_end = .); + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss . : + { + . = ALIGN(4); + __bss_start__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + __ramfuncs_start__ = .; + + __vma_ramfuncs_start__ = .; + __lma_ramfuncs_start__ = __etext + SIZEOF(.data); + + __text_application_ram_offset__ = . - __vma_ramfuncs_start__; + text_application_ram . : AT(__lma_ramfuncs_start__ + __text_application_ram_offset__) + { + . = ALIGN(4); + __text_application_ram_start__ = .; + *(text_application_ram) + . = ALIGN(4); + __text_application_ram_end__ = .; + } > RAM + + . = ALIGN(4); + __vma_ramfuncs_end__ = .; + __lma_ramfuncs_end__ = __lma_ramfuncs_start__ + __text_application_ram_offset__ + SIZEOF(text_application_ram); + + __ramfuncs_end__ = .; + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + _end = __end__; + KEEP(*(.heap*)) + __HeapLimit = ORIGIN(RAM) + LENGTH(RAM); + } > RAM + + __heap_size = __HeapLimit - __HeapBase; + __ram_end__ = 0x20000000 + 0x8000; + __main_flash_end__ = 0x6000 + 0x78000; + + /* This is where we handle flash storage blocks. We use dummy sections for finding the configured + * block sizes and then "place" them at the end of flash when the size is known. */ + .internal_storage (DSECT) : { + KEEP(*(.internal_storage*)) + } > FLASH + + + .nvm (DSECT) : { + KEEP(*(.simee*)) + } > FLASH + + linker_nvm_end = __main_flash_end__; + linker_nvm_begin = linker_nvm_end - SIZEOF(.nvm); + linker_nvm_size = SIZEOF(.nvm); + linker_storage_end = linker_nvm_begin; + __nvm3Base = linker_nvm_begin; + + linker_storage_begin = linker_storage_end - SIZEOF(.internal_storage); + linker_storage_size = SIZEOF(.internal_storage); + ASSERT((linker_storage_begin >= (__etext + SIZEOF(.data))), "FLASH memory overflowed !") + + + app_flash_end = 0x6000 + 0x78000; + ASSERT( (linker_nvm_begin + SIZEOF(.nvm)) <= app_flash_end, "NVM3 is excessing the flash size !") +} diff --git a/locator_ncp/autogen/sl_application_type.h b/locator_ncp/autogen/sl_application_type.h index 5d4067c..ed948b9 100644 --- a/locator_ncp/autogen/sl_application_type.h +++ b/locator_ncp/autogen/sl_application_type.h @@ -1,41 +1,41 @@ -/***************************************************************************//** - * @file - * @brief Autogenerated configuration file for application properties - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_APPLICATION_TYPE_H -#define SL_APPLICATION_TYPE_H - -#include "api/application_properties.h" - -// Bitfield representing type of application -#define APPLICATION_TYPE APPLICATION_TYPE_BLUETOOTH_APP - - -#endif // SL_APPLICATION_TYPE_H - +/***************************************************************************//** + * @file + * @brief Autogenerated configuration file for application properties + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_APPLICATION_TYPE_H +#define SL_APPLICATION_TYPE_H + +#include "api/application_properties.h" + +// Bitfield representing type of application +#define APPLICATION_TYPE APPLICATION_TYPE_BLUETOOTH_APP + + +#endif // SL_APPLICATION_TYPE_H + diff --git a/locator_ncp/autogen/sl_bluetooth.c b/locator_ncp/autogen/sl_bluetooth.c index 7c775d7..05646cc 100644 --- a/locator_ncp/autogen/sl_bluetooth.c +++ b/locator_ncp/autogen/sl_bluetooth.c @@ -1,89 +1,89 @@ - - -#include -#include "sl_bluetooth.h" -#include "sl_assert.h" -#include "sl_bt_stack_init.h" -#include "sl_component_catalog.h" -#if !defined(SL_CATALOG_KERNEL_PRESENT) -/** - * Override @ref PendSV_Handler for the Link Layer task when Bluetooth runs - * in baremetal mode. The override must not exist when Bluetooth runs in an RTOS - * where the link layer task runs in a thread. - */ -#include -void PendSV_Handler() -{ - sl_bt_priority_handle(); -} -#endif - -/** - * Internal stack function to start the Bluetooth stack. - * - * @return SL_STATUS_OK if the stack was successfully started - */ -extern sl_status_t sli_bt_system_start_bluetooth(); - -void sl_bt_init(void) -{ -#if !defined(SL_CATALOG_KERNEL_PRESENT) - NVIC_ClearPendingIRQ(PendSV_IRQn); - NVIC_EnableIRQ(PendSV_IRQn); -#endif - - // Stack initialization could fail, e.g., due to out of memory. - // The failure could not be returned to user as the system initialization - // does not return an error code. Use the EFM_ASSERT to catch the failure, - // which requires either DEBUG_EFM or DEBUG_EFM_USER is defined. - sl_status_t err = sl_bt_stack_init(); - EFM_ASSERT(err == SL_STATUS_OK); - - // When neither Bluetooth on-demand start feature nor an RTOS is present, the - // Bluetooth stack is always started already at init-time. -#if !defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - err = sli_bt_system_start_bluetooth(); - EFM_ASSERT(err == SL_STATUS_OK); -#endif -} - -SL_WEAK void sl_bt_on_event(sl_bt_msg_t* evt) -{ - (void)(evt); -} - -void sl_bt_process_event(sl_bt_msg_t *evt) -{ - sl_bt_on_event(evt); -} - -#if !defined(SL_CATALOG_KERNEL_PRESENT) -// When running in an RTOS, the stack events are processed in a dedicated -// event processing task, and these functions are not used at all. - -SL_WEAK bool sl_bt_can_process_event(uint32_t len) -{ - (void)(len); - return true; -} - -void sl_bt_step(void) -{ - sl_bt_msg_t evt; - - sl_bt_run(); - uint32_t event_len = sl_bt_event_pending_len(); - // For preventing from data loss, the event will be kept in the stack's queue - // if application cannot process it at the moment. - if ((event_len == 0) || (!sl_bt_can_process_event(event_len))) { - return; - } - - // Pop (non-blocking) a Bluetooth stack event from event queue. - sl_status_t status = sl_bt_pop_event(&evt); - if(status != SL_STATUS_OK){ - return; - } - sl_bt_process_event(&evt); -} -#endif // !defined(SL_CATALOG_KERNEL_PRESENT) + + +#include +#include "sl_bluetooth.h" +#include "sl_assert.h" +#include "sl_bt_stack_init.h" +#include "sl_component_catalog.h" +#if !defined(SL_CATALOG_KERNEL_PRESENT) +/** + * Override @ref PendSV_Handler for the Link Layer task when Bluetooth runs + * in baremetal mode. The override must not exist when Bluetooth runs in an RTOS + * where the link layer task runs in a thread. + */ +#include +void PendSV_Handler() +{ + sl_bt_priority_handle(); +} +#endif + +/** + * Internal stack function to start the Bluetooth stack. + * + * @return SL_STATUS_OK if the stack was successfully started + */ +extern sl_status_t sli_bt_system_start_bluetooth(); + +void sl_bt_init(void) +{ +#if !defined(SL_CATALOG_KERNEL_PRESENT) + NVIC_ClearPendingIRQ(PendSV_IRQn); + NVIC_EnableIRQ(PendSV_IRQn); +#endif + + // Stack initialization could fail, e.g., due to out of memory. + // The failure could not be returned to user as the system initialization + // does not return an error code. Use the EFM_ASSERT to catch the failure, + // which requires either DEBUG_EFM or DEBUG_EFM_USER is defined. + sl_status_t err = sl_bt_stack_init(); + EFM_ASSERT(err == SL_STATUS_OK); + + // When neither Bluetooth on-demand start feature nor an RTOS is present, the + // Bluetooth stack is always started already at init-time. +#if !defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + err = sli_bt_system_start_bluetooth(); + EFM_ASSERT(err == SL_STATUS_OK); +#endif +} + +SL_WEAK void sl_bt_on_event(sl_bt_msg_t* evt) +{ + (void)(evt); +} + +void sl_bt_process_event(sl_bt_msg_t *evt) +{ + sl_bt_on_event(evt); +} + +#if !defined(SL_CATALOG_KERNEL_PRESENT) +// When running in an RTOS, the stack events are processed in a dedicated +// event processing task, and these functions are not used at all. + +SL_WEAK bool sl_bt_can_process_event(uint32_t len) +{ + (void)(len); + return true; +} + +void sl_bt_step(void) +{ + sl_bt_msg_t evt; + + sl_bt_run(); + uint32_t event_len = sl_bt_event_pending_len(); + // For preventing from data loss, the event will be kept in the stack's queue + // if application cannot process it at the moment. + if ((event_len == 0) || (!sl_bt_can_process_event(event_len))) { + return; + } + + // Pop (non-blocking) a Bluetooth stack event from event queue. + sl_status_t status = sl_bt_pop_event(&evt); + if(status != SL_STATUS_OK){ + return; + } + sl_bt_process_event(&evt); +} +#endif // !defined(SL_CATALOG_KERNEL_PRESENT) diff --git a/locator_ncp/autogen/sl_bluetooth.h b/locator_ncp/autogen/sl_bluetooth.h index 84d0e26..2836042 100644 --- a/locator_ncp/autogen/sl_bluetooth.h +++ b/locator_ncp/autogen/sl_bluetooth.h @@ -1,42 +1,42 @@ -#ifndef BLUETOOTH_H -#define BLUETOOTH_H - -#include -#include "sl_power_manager.h" -#include "sl_bluetooth_config.h" -#include "sl_bt_api.h" -#define SL_BT_COMPONENT_ADVERTISERS 0 - -#define SL_BT_COMPONENT_CONNECTIONS 0 - -// Initialize Bluetooth core functionality -void sl_bt_init(void); - -// Polls bluetooth stack for an event and processes it -void sl_bt_step(void); - -/** - * Tell if the application can process a new Bluetooth event in its current - * state, for example, based on resource availability status. - * If true is returned by this function, sl_bt_process_event will be called - * for event processing. Otherwise, the event will be kept in stack's event - * queue until the application can process it. - * - * @note Default implementation of this function returns true. - * Application can override it for own business logic. - * - * @param len Data length of the event - * @return ture if event can be processed; false otherwise - */ -bool sl_bt_can_process_event(uint32_t len); - -// Processes a single bluetooth event -void sl_bt_process_event(sl_bt_msg_t *evt); - -void sl_bt_on_event(sl_bt_msg_t* evt); - -// Power Manager related functions -bool sli_bt_is_ok_to_sleep(void); -sl_power_manager_on_isr_exit_t sli_bt_sleep_on_isr_exit(void); - -#endif // BLUETOOTH_H +#ifndef BLUETOOTH_H +#define BLUETOOTH_H + +#include +#include "sl_power_manager.h" +#include "sl_bluetooth_config.h" +#include "sl_bt_api.h" +#define SL_BT_COMPONENT_ADVERTISERS 0 + +#define SL_BT_COMPONENT_CONNECTIONS 0 + +// Initialize Bluetooth core functionality +void sl_bt_init(void); + +// Polls bluetooth stack for an event and processes it +void sl_bt_step(void); + +/** + * Tell if the application can process a new Bluetooth event in its current + * state, for example, based on resource availability status. + * If true is returned by this function, sl_bt_process_event will be called + * for event processing. Otherwise, the event will be kept in stack's event + * queue until the application can process it. + * + * @note Default implementation of this function returns true. + * Application can override it for own business logic. + * + * @param len Data length of the event + * @return ture if event can be processed; false otherwise + */ +bool sl_bt_can_process_event(uint32_t len); + +// Processes a single bluetooth event +void sl_bt_process_event(sl_bt_msg_t *evt); + +void sl_bt_on_event(sl_bt_msg_t* evt); + +// Power Manager related functions +bool sli_bt_is_ok_to_sleep(void); +sl_power_manager_on_isr_exit_t sli_bt_sleep_on_isr_exit(void); + +#endif // BLUETOOTH_H diff --git a/locator_ncp/autogen/sl_board_default_init.c b/locator_ncp/autogen/sl_board_default_init.c index bd43db3..ca5086b 100644 --- a/locator_ncp/autogen/sl_board_default_init.c +++ b/locator_ncp/autogen/sl_board_default_init.c @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief Board Default Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" - -void sl_board_default_init(void) -{ - sl_board_disable_vcom(); - -} +/***************************************************************************//** + * @file + * @brief Board Default Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" + +void sl_board_default_init(void) +{ + sl_board_disable_vcom(); + +} diff --git a/locator_ncp/autogen/sl_component_catalog.h b/locator_ncp/autogen/sl_component_catalog.h index ad21793..bef35ec 100644 --- a/locator_ncp/autogen/sl_component_catalog.h +++ b/locator_ncp/autogen/sl_component_catalog.h @@ -1,51 +1,51 @@ -#ifndef SL_COMPONENT_CATALOG_H -#define SL_COMPONENT_CATALOG_H - -// APIs present in project -#define SL_CATALOG_APP_ASSERT_PRESENT -#define SL_CATALOG_APP_TIMER_PRESENT -#define SL_CATALOG_BLUETOOTH_CONFIGURATION_PRESENT -#define SL_CATALOG_BLUETOOTH_CTE_SUPPORT_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_BUILTIN_BONDING_DATABASE_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_GAP_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_GATT_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_GATT_SERVER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_NVM_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_SM_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT -#define SL_CATALOG_BLUETOOTH_FEATURE_SYSTEM_PRESENT -#define SL_CATALOG_BLUETOOTH_PRESENT -#define SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT -#define SL_CATALOG_DEVICE_INIT_PRESENT -#define SL_CATALOG_DEVICE_INIT_CLOCKS_PRESENT -#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT -#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT -#define SL_CATALOG_DEVICE_INIT_EMU_PRESENT -#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT -#define SL_CATALOG_DEVICE_INIT_LFRCO_PRESENT -#define SL_CATALOG_DEVICE_INIT_LFXO_PRESENT -#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT -#define SL_CATALOG_EMLIB_CORE_PRESENT -#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT -#define SL_CATALOG_MPU_PRESENT -#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT -#define SL_CATALOG_NVM3_PRESENT -#define SL_CATALOG_POWER_MANAGER_PRESENT -#define SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT -#define SL_CATALOG_PSA_CRYPTO_PRESENT -#define SL_CATALOG_RAIL_LIB_PRESENT -#define SL_CATALOG_SE_MANAGER_PRESENT -#define SL_CATALOG_SIMPLE_COM_PRESENT -#define SL_CATALOG_SLEEPTIMER_PRESENT -#define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT -#define SL_CATALOG_UARTDRV_USART_PRESENT - -#endif // SL_COMPONENT_CATALOG_H +#ifndef SL_COMPONENT_CATALOG_H +#define SL_COMPONENT_CATALOG_H + +// APIs present in project +#define SL_CATALOG_APP_ASSERT_PRESENT +#define SL_CATALOG_APP_TIMER_PRESENT +#define SL_CATALOG_BLUETOOTH_CONFIGURATION_PRESENT +#define SL_CATALOG_BLUETOOTH_CTE_SUPPORT_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_BUILTIN_BONDING_DATABASE_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_GAP_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_GATT_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_GATT_SERVER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_NVM_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_SM_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT +#define SL_CATALOG_BLUETOOTH_FEATURE_SYSTEM_PRESENT +#define SL_CATALOG_BLUETOOTH_PRESENT +#define SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT +#define SL_CATALOG_DEVICE_INIT_PRESENT +#define SL_CATALOG_DEVICE_INIT_CLOCKS_PRESENT +#define SL_CATALOG_DEVICE_INIT_CORE_PRESENT +#define SL_CATALOG_DEVICE_INIT_DCDC_PRESENT +#define SL_CATALOG_DEVICE_INIT_EMU_PRESENT +#define SL_CATALOG_DEVICE_INIT_HFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_LFRCO_PRESENT +#define SL_CATALOG_DEVICE_INIT_LFXO_PRESENT +#define SL_CATALOG_DEVICE_INIT_NVIC_PRESENT +#define SL_CATALOG_EMLIB_CORE_PRESENT +#define SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT +#define SL_CATALOG_MPU_PRESENT +#define SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT +#define SL_CATALOG_NVM3_PRESENT +#define SL_CATALOG_POWER_MANAGER_PRESENT +#define SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT +#define SL_CATALOG_PSA_CRYPTO_PRESENT +#define SL_CATALOG_RAIL_LIB_PRESENT +#define SL_CATALOG_SE_MANAGER_PRESENT +#define SL_CATALOG_SIMPLE_COM_PRESENT +#define SL_CATALOG_SLEEPTIMER_PRESENT +#define SL_CATALOG_SLI_PROTOCOL_CRYPTO_PRESENT +#define SL_CATALOG_UARTDRV_USART_PRESENT + +#endif // SL_COMPONENT_CATALOG_H diff --git a/locator_ncp/autogen/sl_device_init_clocks.c b/locator_ncp/autogen/sl_device_init_clocks.c index dbb0964..1828ae7 100644 --- a/locator_ncp/autogen/sl_device_init_clocks.c +++ b/locator_ncp/autogen/sl_device_init_clocks.c @@ -1,60 +1,60 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for clocks. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_clocks.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_clocks(void) -{ - CMU_CLOCK_SELECT_SET(SYSCLK, HFXO); -#if defined(_CMU_EM01GRPACLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPACLK, HFXO); -#endif -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPBCLK, HFXO); -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - CMU_CLOCK_SELECT_SET(EM01GRPCCLK, HFXO); -#endif - CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFXO); - CMU_CLOCK_SELECT_SET(EM4GRPACLK, LFXO); -#if defined(RTCC_PRESENT) - CMU_CLOCK_SELECT_SET(RTCC, LFXO); -#endif -#if defined(SYSRTC_PRESENT) - CMU_CLOCK_SELECT_SET(SYSRTC, LFXO); -#endif - CMU_CLOCK_SELECT_SET(WDOG0, LFXO); -#if WDOG_COUNT > 1 - CMU_CLOCK_SELECT_SET(WDOG1, LFXO); -#endif - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_clocks.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_clocks(void) +{ + CMU_CLOCK_SELECT_SET(SYSCLK, HFXO); +#if defined(_CMU_EM01GRPACLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPACLK, HFXO); +#endif +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPBCLK, HFXO); +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + CMU_CLOCK_SELECT_SET(EM01GRPCCLK, HFXO); +#endif + CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFXO); + CMU_CLOCK_SELECT_SET(EM4GRPACLK, LFXO); +#if defined(RTCC_PRESENT) + CMU_CLOCK_SELECT_SET(RTCC, LFXO); +#endif +#if defined(SYSRTC_PRESENT) + CMU_CLOCK_SELECT_SET(SYSRTC, LFXO); +#endif + CMU_CLOCK_SELECT_SET(WDOG0, LFXO); +#if WDOG_COUNT > 1 + CMU_CLOCK_SELECT_SET(WDOG1, LFXO); +#endif + + return SL_STATUS_OK; +} diff --git a/locator_ncp/autogen/sl_event_handler.c b/locator_ncp/autogen/sl_event_handler.c index 4996eac..9decdcf 100644 --- a/locator_ncp/autogen/sl_event_handler.c +++ b/locator_ncp/autogen/sl_event_handler.c @@ -1,101 +1,101 @@ -#include "sl_event_handler.h" - -#include "em_chip.h" -#include "sl_device_init_nvic.h" -#include "sl_board_init.h" -#include "sl_device_init_dcdc.h" -#include "sl_device_init_lfxo.h" -#include "sl_device_init_hfxo.h" -#include "sl_device_init_lfrco.h" -#include "sl_device_init_clocks.h" -#include "sl_device_init_emu.h" -#include "sl_rail_util_aox.h" -#include "pa_conversions_efr32.h" -#include "btl_interface.h" -#include "sl_board_control.h" -#include "sl_sleeptimer.h" -#include "app_timer.h" -#include "sl_bluetooth.h" -#include "sl_debug_swo.h" -#include "gpiointerrupt.h" -#include "sl_mbedtls.h" -#include "sl_mpu.h" -#include "sl_ncp.h" -#include "nvm3_default.h" -#include "sl_simple_com.h" -#include "sl_uartdrv_instances.h" -#include "psa/crypto.h" -#include "sli_protocol_crypto.h" -#include "sl_power_manager.h" -#include "sl_cos.h" -#include "sl_rail_util_power_manager_init.h" - -void sl_platform_init(void) -{ - CHIP_Init(); - sl_device_init_nvic(); - sl_board_preinit(); - sl_device_init_dcdc(); - sl_device_init_lfxo(); - sl_device_init_hfxo(); - sl_device_init_lfrco(); - sl_device_init_clocks(); - sl_device_init_emu(); - sl_board_init(); - bootloader_init(); - nvm3_initDefault(); - sl_power_manager_init(); -} - -void sl_driver_init(void) -{ - sl_debug_swo_init(); - GPIOINT_Init(); - sl_uartdrv_init_instances(); - sl_cos_send_config(); -} - -void sl_service_init(void) -{ - sl_board_configure_vcom(); - sl_sleeptimer_init(); - sl_mbedtls_init(); - sl_mpu_disable_execute_from_ram(); - psa_crypto_init(); - sli_aes_seed_mask(); -} - -void sl_stack_init(void) -{ - sl_rail_util_aox_init(); - sl_rail_util_pa_init(); - sl_bt_init(); - sl_rail_util_power_manager_init(); -} - -void sl_internal_app_init(void) -{ - sl_simple_com_init(); - sl_ncp_init(); -} - -void sl_platform_process_action(void) -{ -} - -void sl_service_process_action(void) -{ - sli_app_timer_step(); - sl_simple_com_step(); -} - -void sl_stack_process_action(void) -{ - sl_bt_step(); -} - -void sl_internal_app_process_action(void) -{ - sl_ncp_step(); -} - +#include "sl_event_handler.h" + +#include "em_chip.h" +#include "sl_device_init_nvic.h" +#include "sl_board_init.h" +#include "sl_device_init_dcdc.h" +#include "sl_device_init_lfxo.h" +#include "sl_device_init_hfxo.h" +#include "sl_device_init_lfrco.h" +#include "sl_device_init_clocks.h" +#include "sl_device_init_emu.h" +#include "sl_rail_util_aox.h" +#include "pa_conversions_efr32.h" +#include "btl_interface.h" +#include "sl_board_control.h" +#include "sl_sleeptimer.h" +#include "app_timer.h" +#include "sl_bluetooth.h" +#include "sl_debug_swo.h" +#include "gpiointerrupt.h" +#include "sl_mbedtls.h" +#include "sl_mpu.h" +#include "sl_ncp.h" +#include "nvm3_default.h" +#include "sl_simple_com.h" +#include "sl_uartdrv_instances.h" +#include "psa/crypto.h" +#include "sli_protocol_crypto.h" +#include "sl_power_manager.h" +#include "sl_cos.h" +#include "sl_rail_util_power_manager_init.h" + +void sl_platform_init(void) +{ + CHIP_Init(); + sl_device_init_nvic(); + sl_board_preinit(); + sl_device_init_dcdc(); + sl_device_init_lfxo(); + sl_device_init_hfxo(); + sl_device_init_lfrco(); + sl_device_init_clocks(); + sl_device_init_emu(); + sl_board_init(); + bootloader_init(); + nvm3_initDefault(); + sl_power_manager_init(); +} + +void sl_driver_init(void) +{ + sl_debug_swo_init(); + GPIOINT_Init(); + sl_uartdrv_init_instances(); + sl_cos_send_config(); +} + +void sl_service_init(void) +{ + sl_board_configure_vcom(); + sl_sleeptimer_init(); + sl_mbedtls_init(); + sl_mpu_disable_execute_from_ram(); + psa_crypto_init(); + sli_aes_seed_mask(); +} + +void sl_stack_init(void) +{ + sl_rail_util_aox_init(); + sl_rail_util_pa_init(); + sl_bt_init(); + sl_rail_util_power_manager_init(); +} + +void sl_internal_app_init(void) +{ + sl_simple_com_init(); + sl_ncp_init(); +} + +void sl_platform_process_action(void) +{ +} + +void sl_service_process_action(void) +{ + sli_app_timer_step(); + sl_simple_com_step(); +} + +void sl_stack_process_action(void) +{ + sl_bt_step(); +} + +void sl_internal_app_process_action(void) +{ + sl_ncp_step(); +} + diff --git a/locator_ncp/autogen/sl_event_handler.h b/locator_ncp/autogen/sl_event_handler.h index 8929954..90e8ab9 100644 --- a/locator_ncp/autogen/sl_event_handler.h +++ b/locator_ncp/autogen/sl_event_handler.h @@ -1,14 +1,14 @@ -#ifndef SL_EVENT_HANDLER_H -#define SL_EVENT_HANDLER_H - -void sl_platform_init(void); -void sl_driver_init(void); -void sl_service_init(void); -void sl_stack_init(void); -void sl_internal_app_init(void); -void sl_platform_process_action(void); -void sl_service_process_action(void); -void sl_stack_process_action(void); -void sl_internal_app_process_action(void); - -#endif // SL_EVENT_HANDLER_H +#ifndef SL_EVENT_HANDLER_H +#define SL_EVENT_HANDLER_H + +void sl_platform_init(void); +void sl_driver_init(void); +void sl_service_init(void); +void sl_stack_init(void); +void sl_internal_app_init(void); +void sl_platform_process_action(void); +void sl_service_process_action(void); +void sl_stack_process_action(void); +void sl_internal_app_process_action(void); + +#endif // SL_EVENT_HANDLER_H diff --git a/locator_ncp/autogen/sl_power_manager_handler.c b/locator_ncp/autogen/sl_power_manager_handler.c index 754a5f9..3800970 100644 --- a/locator_ncp/autogen/sl_power_manager_handler.c +++ b/locator_ncp/autogen/sl_power_manager_handler.c @@ -1,133 +1,133 @@ -#include -#include "em_core.h" -#include "sl_power_manager.h" -#include "sl_sleeptimer.h" -#include "app_timer.h" -#include "sl_bluetooth.h" -#include "sl_ncp.h" -#include "uartdrv.h" - -/***************************************************************************//** - * Check if the MCU can sleep at that time. This function is called when the system - * is about to go sleeping, with the interrupts disabled. It allows the software to - * cancel going to sleep in case of a last-minute event occurred (window between the - * function call and interrupt disable). - * - * @return True, if the system can go to sleep. - * False, otherwise. - * - * @note This function is called with the interrupt disabled and it MUST NOT be - * re-enabled. - ******************************************************************************/ -__WEAK bool app_is_ok_to_sleep(void) -{ - return true; -} - -/***************************************************************************//** - * Check if the MCU can sleep after an interrupt. This function is called after an - * interrupt occured and was processed. It allows the power manger to know if it must - * go back to sleep or wakeup. - * - * @return SL_POWER_MANAGER_IGNORE, if the module did not trigger an ISR and it - * won't to contribute to the decision. - * - * SL_POWER_MANAGER_SLEEP, The module was the one that caused the system - * wakeup and the system SHOULD go back to sleep. - * - * SL_POWER_MANAGER_WAKEUP, The module was the one that caused the system - * wakeup and the system MUST NOT go back to sleep. - * - * @note This function must not have any side effects. It is not guaranteed to be - * called for every ISR. If a prior hook function requires to wakeup, such - * as a wireless stack, the application hook function won't be called. - ******************************************************************************/ -__WEAK sl_power_manager_on_isr_exit_t app_sleep_on_isr_exit(void) -{ - return SL_POWER_MANAGER_IGNORE; -} - -/***************************************************************************//** - * Mandatory callback that allows to cancel sleeping action. This function is called - * when the system is about to go sleeping, with the interrupts disabled. It allows - * the software to cancel going to sleep in case of a last-minute event occurred - * (window between the function call and interrupt disable). - ******************************************************************************/ -bool sl_power_manager_is_ok_to_sleep(void) -{ - bool ok_to_sleep = true; - if (sli_app_timer_is_ok_to_sleep() == false) { - ok_to_sleep = false; - } - if (sli_bt_is_ok_to_sleep() == false) { - ok_to_sleep = false; - } - if (sli_ncp_is_ok_to_sleep() == false) { - ok_to_sleep = false; - } - // Application hook - if (app_is_ok_to_sleep() == false) { - ok_to_sleep = false; - } - - return ok_to_sleep; -} - -/***************************************************************************//** - * Mandatory callback that must validate if the MCU can sleep after having - * processed an interrupt when the system was sleeping. - ******************************************************************************/ -bool sl_power_manager_sleep_on_isr_exit(void) -{ - sl_power_manager_on_isr_exit_t answer; - bool sleep = false; - bool force_wakeup = false; - - // This function allow the power manager to return into sleep, if the latest timer - // to expire was power manager's internal one used to restore HFXO on time or - // the HFXO interrupt. - // Most of the time we want to get back to sleep until the next event occurs. - sleep = sl_power_manager_is_latest_wakeup_internal(); - - answer = sli_app_timer_sleep_on_isr_exit(); - if (answer == SL_POWER_MANAGER_WAKEUP) { - force_wakeup = true; - } else if (answer == SL_POWER_MANAGER_SLEEP) { - sleep = true; - } - - answer = sli_bt_sleep_on_isr_exit(); - if (answer == SL_POWER_MANAGER_WAKEUP) { - force_wakeup = true; - } else if (answer == SL_POWER_MANAGER_SLEEP) { - sleep = true; - } - - answer = sli_ncp_sleep_on_isr_exit(); - if (answer == SL_POWER_MANAGER_WAKEUP) { - force_wakeup = true; - } else if (answer == SL_POWER_MANAGER_SLEEP) { - sleep = true; - } - - answer = sl_uartdrv_sleep_on_isr_exit(); - if (answer == SL_POWER_MANAGER_WAKEUP) { - force_wakeup = true; - } else if (answer == SL_POWER_MANAGER_SLEEP) { - sleep = true; - } - - // Application hook - answer = app_sleep_on_isr_exit(); - if (answer == SL_POWER_MANAGER_WAKEUP) { - force_wakeup = true; - } else if (answer == SL_POWER_MANAGER_SLEEP) { - sleep = true; - } - - if (force_wakeup) { - sleep = false; - } - - return sleep; +#include +#include "em_core.h" +#include "sl_power_manager.h" +#include "sl_sleeptimer.h" +#include "app_timer.h" +#include "sl_bluetooth.h" +#include "sl_ncp.h" +#include "uartdrv.h" + +/***************************************************************************//** + * Check if the MCU can sleep at that time. This function is called when the system + * is about to go sleeping, with the interrupts disabled. It allows the software to + * cancel going to sleep in case of a last-minute event occurred (window between the + * function call and interrupt disable). + * + * @return True, if the system can go to sleep. + * False, otherwise. + * + * @note This function is called with the interrupt disabled and it MUST NOT be + * re-enabled. + ******************************************************************************/ +__WEAK bool app_is_ok_to_sleep(void) +{ + return true; +} + +/***************************************************************************//** + * Check if the MCU can sleep after an interrupt. This function is called after an + * interrupt occured and was processed. It allows the power manger to know if it must + * go back to sleep or wakeup. + * + * @return SL_POWER_MANAGER_IGNORE, if the module did not trigger an ISR and it + * won't to contribute to the decision. + * + * SL_POWER_MANAGER_SLEEP, The module was the one that caused the system + * wakeup and the system SHOULD go back to sleep. + * + * SL_POWER_MANAGER_WAKEUP, The module was the one that caused the system + * wakeup and the system MUST NOT go back to sleep. + * + * @note This function must not have any side effects. It is not guaranteed to be + * called for every ISR. If a prior hook function requires to wakeup, such + * as a wireless stack, the application hook function won't be called. + ******************************************************************************/ +__WEAK sl_power_manager_on_isr_exit_t app_sleep_on_isr_exit(void) +{ + return SL_POWER_MANAGER_IGNORE; +} + +/***************************************************************************//** + * Mandatory callback that allows to cancel sleeping action. This function is called + * when the system is about to go sleeping, with the interrupts disabled. It allows + * the software to cancel going to sleep in case of a last-minute event occurred + * (window between the function call and interrupt disable). + ******************************************************************************/ +bool sl_power_manager_is_ok_to_sleep(void) +{ + bool ok_to_sleep = true; + if (sli_app_timer_is_ok_to_sleep() == false) { + ok_to_sleep = false; + } + if (sli_bt_is_ok_to_sleep() == false) { + ok_to_sleep = false; + } + if (sli_ncp_is_ok_to_sleep() == false) { + ok_to_sleep = false; + } + // Application hook + if (app_is_ok_to_sleep() == false) { + ok_to_sleep = false; + } + + return ok_to_sleep; +} + +/***************************************************************************//** + * Mandatory callback that must validate if the MCU can sleep after having + * processed an interrupt when the system was sleeping. + ******************************************************************************/ +bool sl_power_manager_sleep_on_isr_exit(void) +{ + sl_power_manager_on_isr_exit_t answer; + bool sleep = false; + bool force_wakeup = false; + + // This function allow the power manager to return into sleep, if the latest timer + // to expire was power manager's internal one used to restore HFXO on time or + // the HFXO interrupt. + // Most of the time we want to get back to sleep until the next event occurs. + sleep = sl_power_manager_is_latest_wakeup_internal(); + + answer = sli_app_timer_sleep_on_isr_exit(); + if (answer == SL_POWER_MANAGER_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_POWER_MANAGER_SLEEP) { + sleep = true; + } + + answer = sli_bt_sleep_on_isr_exit(); + if (answer == SL_POWER_MANAGER_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_POWER_MANAGER_SLEEP) { + sleep = true; + } + + answer = sli_ncp_sleep_on_isr_exit(); + if (answer == SL_POWER_MANAGER_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_POWER_MANAGER_SLEEP) { + sleep = true; + } + + answer = sl_uartdrv_sleep_on_isr_exit(); + if (answer == SL_POWER_MANAGER_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_POWER_MANAGER_SLEEP) { + sleep = true; + } + + // Application hook + answer = app_sleep_on_isr_exit(); + if (answer == SL_POWER_MANAGER_WAKEUP) { + force_wakeup = true; + } else if (answer == SL_POWER_MANAGER_SLEEP) { + sleep = true; + } + + if (force_wakeup) { + sleep = false; + } + + return sleep; } \ No newline at end of file diff --git a/locator_ncp/autogen/sl_simple_com_isr.c b/locator_ncp/autogen/sl_simple_com_isr.c index fb8d36e..e624fe9 100644 --- a/locator_ncp/autogen/sl_simple_com_isr.c +++ b/locator_ncp/autogen/sl_simple_com_isr.c @@ -1,76 +1,76 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) interrupt service routine - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_uartdrv_usart_vcom_config.h" - -// ISR function, declared in sl_simple_com.c -extern void sli_simple_com_isr(void); - -/******************************************************************************* - * Concatenate preprocessor tokens A and B without expanding macro unless it is - * invoked from a macro, already. - ******************************************************************************/ -#define PPCAT_NX(A, B) A ## B - -/******************************************************************************* - * Concatenate preprocessor tokens A and B after macro-expanding them. - ******************************************************************************/ -#define PPCAT(A, B) PPCAT_NX(A, B) - -/******************************************************************************* - * Actual USART instance number, generated upon project creation / modification. - ******************************************************************************/ -#define SL_UART_INST_NO SL_UARTDRV_USART_VCOM_PERIPHERAL_NO - -/******************************************************************************* - * Concatenate the actual value of SL_UARTDRV_USART_*_PERIPHERAL_NO and the - * parameter to (partially) create the interrupt service routine name. This - * will be the second part. Please note it can be created only this way: second - * part of the name, first - otherwise recursive macro expansion would mess up - * the whole effort. - ******************************************************************************/ -#define SL_SIMPLE_COM_VNAME(A) PPCAT(SL_UART_INST_NO, A) - -/******************************************************************************* - * Finally, construct the actual ISR vector name for USARTn - * Currently, this macro has limited supports only for USARTn vectors. - ******************************************************************************/ -#define SL_SIMPLE_COM_IRQ PPCAT(USART, \ - SL_SIMPLE_COM_VNAME(_RX_IRQHandler)) - -/**************************************************************************//** - * Override the default interrupt handler using the special macro in order to - * place the vector in the appropriate place no matter which USART peripheral is - * actually used. - *****************************************************************************/ -void SL_SIMPLE_COM_IRQ() -{ - sli_simple_com_isr(); -} - +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) interrupt service routine + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_uartdrv_usart_vcom_config.h" + +// ISR function, declared in sl_simple_com.c +extern void sli_simple_com_isr(void); + +/******************************************************************************* + * Concatenate preprocessor tokens A and B without expanding macro unless it is + * invoked from a macro, already. + ******************************************************************************/ +#define PPCAT_NX(A, B) A ## B + +/******************************************************************************* + * Concatenate preprocessor tokens A and B after macro-expanding them. + ******************************************************************************/ +#define PPCAT(A, B) PPCAT_NX(A, B) + +/******************************************************************************* + * Actual USART instance number, generated upon project creation / modification. + ******************************************************************************/ +#define SL_UART_INST_NO SL_UARTDRV_USART_VCOM_PERIPHERAL_NO + +/******************************************************************************* + * Concatenate the actual value of SL_UARTDRV_USART_*_PERIPHERAL_NO and the + * parameter to (partially) create the interrupt service routine name. This + * will be the second part. Please note it can be created only this way: second + * part of the name, first - otherwise recursive macro expansion would mess up + * the whole effort. + ******************************************************************************/ +#define SL_SIMPLE_COM_VNAME(A) PPCAT(SL_UART_INST_NO, A) + +/******************************************************************************* + * Finally, construct the actual ISR vector name for USARTn + * Currently, this macro has limited supports only for USARTn vectors. + ******************************************************************************/ +#define SL_SIMPLE_COM_IRQ PPCAT(USART, \ + SL_SIMPLE_COM_VNAME(_RX_IRQHandler)) + +/**************************************************************************//** + * Override the default interrupt handler using the special macro in order to + * place the vector in the appropriate place no matter which USART peripheral is + * actually used. + *****************************************************************************/ +void SL_SIMPLE_COM_IRQ() +{ + sli_simple_com_isr(); +} + diff --git a/locator_ncp/autogen/sl_uartdrv_init.c b/locator_ncp/autogen/sl_uartdrv_init.c index ab0bb51..a93664c 100644 --- a/locator_ncp/autogen/sl_uartdrv_init.c +++ b/locator_ncp/autogen/sl_uartdrv_init.c @@ -1,91 +1,91 @@ -#include "uartdrv.h" -#include "sl_uartdrv_instances.h" -#include - -#include "sl_uartdrv_usart_vcom_config.h" - -UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; -UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; - -static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; - -/* If CTS and RTS not defined, define a default value to avoid errors */ -#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 -#endif -#endif - -#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 -#if defined(_USART_ROUTELOC1_MASK) -#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 -#endif -#endif - - -/* Define RX and TX buffer queues */ -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); -DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); - - -/* Create uartdrv initialization structs */ -UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { - .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, - .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, -#if defined(_USART_ROUTELOC0_MASK) - .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, - .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, -#elif defined(_USART_ROUTE_MASK) - .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, -#elif defined(_GPIO_USART_ROUTEEN_MASK) - .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, - .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, - .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, - .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, - .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, -#endif - .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, - .parity = SL_UARTDRV_USART_VCOM_PARITY, - .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, -#if defined(USART_CTRL_MVDIS) - .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, -#endif - .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, - .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, - .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, - .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, - .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, - .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, - .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, -#if defined(_USART_ROUTELOC1_MASK) - .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, - .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, -#endif -}; - - -void sl_uartdrv_init_instances(void){ - UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); - sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); -} - -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) -{ - sl_status_t status = SL_STATUS_INVALID_HANDLE; - - if (handle != NULL) { - sli_uartdrv_default_handle = handle; - status = SL_STATUS_OK; - } - - return status; -} - -UARTDRV_Handle_t sl_uartdrv_get_default(void) -{ - return sli_uartdrv_default_handle; -} +#include "uartdrv.h" +#include "sl_uartdrv_instances.h" +#include + +#include "sl_uartdrv_usart_vcom_config.h" + +UARTDRV_HandleData_t sl_uartdrv_usart_vcom_handle_data; +UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle = &sl_uartdrv_usart_vcom_handle_data; + +static UARTDRV_Handle_t sli_uartdrv_default_handle = NULL; + +/* If CTS and RTS not defined, define a default value to avoid errors */ +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_CTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_CTS_LOC 0 +#endif +#endif + +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#define SL_UARTDRV_USART_VCOM_RTS_PIN 0 +#if defined(_USART_ROUTELOC1_MASK) +#define SL_UARTDRV_USART_VCOM_RTS_LOC 0 +#endif +#endif + + +/* Define RX and TX buffer queues */ +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE, sl_uartdrv_usart_vcom_rx_buffer); +DEFINE_BUF_QUEUE(SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE, sl_uartdrv_usart_vcom_tx_buffer); + + +/* Create uartdrv initialization structs */ +UARTDRV_InitUart_t sl_uartdrv_usart_init_vcom = { + .port = SL_UARTDRV_USART_VCOM_PERIPHERAL, + .baudRate = SL_UARTDRV_USART_VCOM_BAUDRATE, +#if defined(_USART_ROUTELOC0_MASK) + .portLocationTx = SL_UARTDRV_USART_VCOM_TX_LOC, + .portLocationRx = SL_UARTDRV_USART_VCOM_RX_LOC, +#elif defined(_USART_ROUTE_MASK) + .portLocation = SL_UARTDRV_USART_VCOM_ROUTE_LOC, +#elif defined(_GPIO_USART_ROUTEEN_MASK) + .txPort = SL_UARTDRV_USART_VCOM_TX_PORT, + .rxPort = SL_UARTDRV_USART_VCOM_RX_PORT, + .txPin = SL_UARTDRV_USART_VCOM_TX_PIN, + .rxPin = SL_UARTDRV_USART_VCOM_RX_PIN, + .uartNum = SL_UARTDRV_USART_VCOM_PERIPHERAL_NO, +#endif + .stopBits = SL_UARTDRV_USART_VCOM_STOP_BITS, + .parity = SL_UARTDRV_USART_VCOM_PARITY, + .oversampling = SL_UARTDRV_USART_VCOM_OVERSAMPLING, +#if defined(USART_CTRL_MVDIS) + .mvdis = SL_UARTDRV_USART_VCOM_MVDIS, +#endif + .fcType = SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, + .ctsPort = SL_UARTDRV_USART_VCOM_CTS_PORT, + .rtsPort = SL_UARTDRV_USART_VCOM_RTS_PORT, + .ctsPin = SL_UARTDRV_USART_VCOM_CTS_PIN, + .rtsPin = SL_UARTDRV_USART_VCOM_RTS_PIN, + .rxQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_rx_buffer, + .txQueue = (UARTDRV_Buffer_FifoQueue_t *)&sl_uartdrv_usart_vcom_tx_buffer, +#if defined(_USART_ROUTELOC1_MASK) + .portLocationCts = SL_UARTDRV_USART_VCOM_CTS_LOC, + .portLocationRts = SL_UARTDRV_USART_VCOM_RTS_LOC, +#endif +}; + + +void sl_uartdrv_init_instances(void){ + UARTDRV_InitUart(sl_uartdrv_usart_vcom_handle, &sl_uartdrv_usart_init_vcom); + sl_uartdrv_set_default(sl_uartdrv_usart_vcom_handle); +} + +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle) +{ + sl_status_t status = SL_STATUS_INVALID_HANDLE; + + if (handle != NULL) { + sli_uartdrv_default_handle = handle; + status = SL_STATUS_OK; + } + + return status; +} + +UARTDRV_Handle_t sl_uartdrv_get_default(void) +{ + return sli_uartdrv_default_handle; +} diff --git a/locator_ncp/autogen/sl_uartdrv_instances.h b/locator_ncp/autogen/sl_uartdrv_instances.h index 894c73f..ad2590d 100644 --- a/locator_ncp/autogen/sl_uartdrv_instances.h +++ b/locator_ncp/autogen/sl_uartdrv_instances.h @@ -1,35 +1,35 @@ -#ifndef SL_UARTDRV_INSTANCES_H -#define SL_UARTDRV_INSTANCES_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "sl_status.h" -#include "uartdrv.h" - -extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; - -void sl_uartdrv_init_instances(void); - -/***************************************************************************//** - * Set the handle as the default UARTDRV handle. - * - * @param[in] handle UARTDRV handle to set as default. - * - * @return Status result - ******************************************************************************/ -sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); - -/***************************************************************************//** - * Get the default UARTDRV handle configured. - * - * @return UARTDRV handle - ******************************************************************************/ -UARTDRV_Handle_t sl_uartdrv_get_default(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_UARTDRV_INSTANCES_H +#ifndef SL_UARTDRV_INSTANCES_H +#define SL_UARTDRV_INSTANCES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "sl_status.h" +#include "uartdrv.h" + +extern UARTDRV_Handle_t sl_uartdrv_usart_vcom_handle; + +void sl_uartdrv_init_instances(void); + +/***************************************************************************//** + * Set the handle as the default UARTDRV handle. + * + * @param[in] handle UARTDRV handle to set as default. + * + * @return Status result + ******************************************************************************/ +sl_status_t sl_uartdrv_set_default(UARTDRV_Handle_t handle); + +/***************************************************************************//** + * Get the default UARTDRV handle configured. + * + * @return UARTDRV handle + ******************************************************************************/ +UARTDRV_Handle_t sl_uartdrv_get_default(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_UARTDRV_INSTANCES_H diff --git a/locator_ncp/autogen/sli_mbedtls_config_autogen.h b/locator_ncp/autogen/sli_mbedtls_config_autogen.h index 6c64a38..6c767b1 100644 --- a/locator_ncp/autogen/sli_mbedtls_config_autogen.h +++ b/locator_ncp/autogen/sli_mbedtls_config_autogen.h @@ -1,24 +1,24 @@ -// This is an autogenerated config file, any changes to this file will be overwritten - -#ifndef SLI_MBEDTLS_CONFIG_AUTOGEN_H -#define SLI_MBEDTLS_CONFIG_AUTOGEN_H - - - -#define MBEDTLS_PLATFORM_C -#define MBEDTLS_PLATFORM_MEMORY -#define MBEDTLS_PLATFORM_CALLOC_MACRO sl_calloc -#define MBEDTLS_PLATFORM_FREE_MACRO sl_free -#define MBEDTLS_PSA_CRYPTO_C -#define MBEDTLS_USE_PSA_CRYPTO -#define MBEDTLS_CIPHER_C -#define MBEDTLS_PSA_CRYPTO_CONFIG -#define MBEDTLS_PSA_CRYPTO_DRIVERS -#define MBEDTLS_PSA_CRYPTO_STORAGE_C - - - - - - -#endif // SLI_MBEDTLS_CONFIG_AUTOGEN_H +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SLI_MBEDTLS_CONFIG_AUTOGEN_H +#define SLI_MBEDTLS_CONFIG_AUTOGEN_H + + + +#define MBEDTLS_PLATFORM_C +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_CALLOC_MACRO sl_calloc +#define MBEDTLS_PLATFORM_FREE_MACRO sl_free +#define MBEDTLS_PSA_CRYPTO_C +#define MBEDTLS_USE_PSA_CRYPTO +#define MBEDTLS_CIPHER_C +#define MBEDTLS_PSA_CRYPTO_CONFIG +#define MBEDTLS_PSA_CRYPTO_DRIVERS +#define MBEDTLS_PSA_CRYPTO_STORAGE_C + + + + + + +#endif // SLI_MBEDTLS_CONFIG_AUTOGEN_H diff --git a/locator_ncp/autogen/sli_mbedtls_config_transform_autogen.h b/locator_ncp/autogen/sli_mbedtls_config_transform_autogen.h index 802647a..541df65 100644 --- a/locator_ncp/autogen/sli_mbedtls_config_transform_autogen.h +++ b/locator_ncp/autogen/sli_mbedtls_config_transform_autogen.h @@ -1,54 +1,54 @@ -// This is an autogenerated config file, any changes to this file will be overwritten - -#ifndef SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H -#define SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H - -// Convert CMSIS Markup config defines to mbedTLS specific config defines - -#if SL_MBEDTLS_RSA_NO_CRT - #define MBEDTLS_RSA_NO_CRT -#endif - -// Allow undefining the specified cipher suites -#if defined(SLI_MBEDTLS_AUTODETECT_CIPHERSUITES) - #undef MBEDTLS_SSL_CIPHERSUITES -#endif - -#if SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH - #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH -#endif -#if SL_MBEDTLS_SSL_EXPORT_KEYS - #define MBEDTLS_SSL_EXPORT_KEYS -#endif -#if SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED - #define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED -#endif -#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - #define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED -#endif -#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED - #define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED -#endif -#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED - #define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED -#endif -#if SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED - #define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED -#endif -#if SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING - #define MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING -#endif - -#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) - #define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN -#endif - -#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) - #define MBEDTLS_SSL_OUT_CONTENT_LEN SL_MBEDTLS_SSL_OUT_CONTENT_LEN -#endif - - - - - -#endif // SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H +#define SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H + +// Convert CMSIS Markup config defines to mbedTLS specific config defines + +#if SL_MBEDTLS_RSA_NO_CRT + #define MBEDTLS_RSA_NO_CRT +#endif + +// Allow undefining the specified cipher suites +#if defined(SLI_MBEDTLS_AUTODETECT_CIPHERSUITES) + #undef MBEDTLS_SSL_CIPHERSUITES +#endif + +#if SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + #define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#endif +#if SL_MBEDTLS_SSL_EXPORT_KEYS + #define MBEDTLS_SSL_EXPORT_KEYS +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#endif +#if SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + #define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#endif +#if SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING + #define MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING +#endif + +#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) + #define MBEDTLS_SSL_IN_CONTENT_LEN SL_MBEDTLS_SSL_IN_CONTENT_LEN +#endif + +#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) + #define MBEDTLS_SSL_OUT_CONTENT_LEN SL_MBEDTLS_SSL_OUT_CONTENT_LEN +#endif + + + + + +#endif // SLI_MBEDTLS_CONFIG_TRANSFORM_AUTOGEN_H diff --git a/locator_ncp/autogen/sli_psa_builtin_config_autogen.h b/locator_ncp/autogen/sli_psa_builtin_config_autogen.h index 0ea73a4..3b61a95 100644 --- a/locator_ncp/autogen/sli_psa_builtin_config_autogen.h +++ b/locator_ncp/autogen/sli_psa_builtin_config_autogen.h @@ -1,8 +1,8 @@ -// This is an autogenerated config file, any changes to this file will be overwritten - -#ifndef SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H -#define SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H - - - -#endif // SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H +#define SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H + + + +#endif // SLI_PSA_BUILTIN_CONFIG_AUTOGEN_H diff --git a/locator_ncp/autogen/sli_psa_config_autogen.h b/locator_ncp/autogen/sli_psa_config_autogen.h index a608549..fbea65c 100644 --- a/locator_ncp/autogen/sli_psa_config_autogen.h +++ b/locator_ncp/autogen/sli_psa_config_autogen.h @@ -1,23 +1,23 @@ -// This is an autogenerated config file, any changes to this file will be overwritten - -#ifndef SLI_PSA_CONFIG_AUTOGEN_H -#define SLI_PSA_CONFIG_AUTOGEN_H - -#define PSA_WANT_KEY_TYPE_AES 1 -#define PSA_WANT_ALG_ECB_NO_PADDING 1 -#define PSA_WANT_ALG_CMAC 1 -#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -#define PSA_WANT_ECC_SECP_R1_256 1 -#define PSA_WANT_ALG_ECDH 1 -#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG - -#define MBEDTLS_PSA_KEY_SLOT_COUNT (2 + 1 + SL_PSA_KEY_USER_SLOT_COUNT) -#ifndef SL_PSA_ITS_MAX_FILES -#define SL_PSA_ITS_MAX_FILES (1 + SL_PSA_ITS_USER_MAX_FILES) -#endif - -#endif // SLI_PSA_CONFIG_AUTOGEN_H +// This is an autogenerated config file, any changes to this file will be overwritten + +#ifndef SLI_PSA_CONFIG_AUTOGEN_H +#define SLI_PSA_CONFIG_AUTOGEN_H + +#define PSA_WANT_KEY_TYPE_AES 1 +#define PSA_WANT_ALG_ECB_NO_PADDING 1 +#define PSA_WANT_ALG_CMAC 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define PSA_WANT_ECC_SECP_R1_256 1 +#define PSA_WANT_ALG_ECDH 1 +#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +#define MBEDTLS_PSA_KEY_SLOT_COUNT (2 + 1 + SL_PSA_KEY_USER_SLOT_COUNT) +#ifndef SL_PSA_ITS_MAX_FILES +#define SL_PSA_ITS_MAX_FILES (1 + SL_PSA_ITS_USER_MAX_FILES) +#endif + +#endif // SLI_PSA_CONFIG_AUTOGEN_H diff --git a/locator_ncp/config/app_assert_config.h b/locator_ncp/config/app_assert_config.h index 81d60f1..2256435 100644 --- a/locator_ncp/config/app_assert_config.h +++ b/locator_ncp/config/app_assert_config.h @@ -1,54 +1,54 @@ -/***************************************************************************//** - * @file - * @brief Application assert configuration - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_ASSERT_CONFIG_H -#define APP_ASSERT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Assert component -// Enables Assert. -#define APP_ASSERT_ENABLE 1 - -// Logging -// Enables logging for assert. -#define APP_ASSERT_LOG_ENABLE 1 - -// Enable trace -// Enables trace for assert. -#define APP_ASSERT_TRACE_ENABLE 1 - -// - -// - -// <<< end of configuration section >>> - -#endif // APP_ASSERT_CONFIG_H +/***************************************************************************//** + * @file + * @brief Application assert configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_ASSERT_CONFIG_H +#define APP_ASSERT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Assert component +// Enables Assert. +#define APP_ASSERT_ENABLE 1 + +// Logging +// Enables logging for assert. +#define APP_ASSERT_LOG_ENABLE 1 + +// Enable trace +// Enables trace for assert. +#define APP_ASSERT_TRACE_ENABLE 1 + +// + +// + +// <<< end of configuration section >>> + +#endif // APP_ASSERT_CONFIG_H diff --git a/locator_ncp/config/app_properties_config.h b/locator_ncp/config/app_properties_config.h index 6a6b976..0e6d78b 100644 --- a/locator_ncp/config/app_properties_config.h +++ b/locator_ncp/config/app_properties_config.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief Application Properties Header File - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_PROPERTIES_CONFIG_H -#define APP_PROPERTIES_CONFIG_H - -#include "sl_application_type.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// App Properties settings - -// Type of signature this application is signed with -// Default: APPLICATION_SIGNATURE_NONE(0) -#define SL_APPLICATION_SIGNATURE 0 - -// Location of the signature -// Default: 0xFFFFFFFF -#define SL_APPLICATION_SIGNATURE_LOCATION 0xFFFFFFFF - -// Bitfield representing type of application -#define SL_APPLICATION_TYPE APPLICATION_TYPE - -// Version number for this application -// <0-4294967295:1> -// Default: 1 [0-4294967295] -#define SL_APPLICATION_VERSION 1 - -// Capabilities of this application -// Default: 0 -#define SL_APPLICATION_CAPABILITIES 0 - -//Product ID of the device for which the application is built -#define SL_APPLICATION_PRODUCT_ID { 0 } - -// - -#endif // APP_PROPERTIES_CONFIG_H +/***************************************************************************//** + * @file + * @brief Application Properties Header File + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_PROPERTIES_CONFIG_H +#define APP_PROPERTIES_CONFIG_H + +#include "sl_application_type.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// App Properties settings + +// Type of signature this application is signed with +// Default: APPLICATION_SIGNATURE_NONE(0) +#define SL_APPLICATION_SIGNATURE 0 + +// Location of the signature +// Default: 0xFFFFFFFF +#define SL_APPLICATION_SIGNATURE_LOCATION 0xFFFFFFFF + +// Bitfield representing type of application +#define SL_APPLICATION_TYPE APPLICATION_TYPE + +// Version number for this application +// <0-4294967295:1> +// Default: 1 [0-4294967295] +#define SL_APPLICATION_VERSION 1 + +// Capabilities of this application +// Default: 0 +#define SL_APPLICATION_CAPABILITIES 0 + +//Product ID of the device for which the application is built +#define SL_APPLICATION_PRODUCT_ID { 0 } + +// + +#endif // APP_PROPERTIES_CONFIG_H diff --git a/locator_ncp/config/btl_interface_cfg.h b/locator_ncp/config/btl_interface_cfg.h index 8e246f8..053ceff 100644 --- a/locator_ncp/config/btl_interface_cfg.h +++ b/locator_ncp/config/btl_interface_cfg.h @@ -1,48 +1,48 @@ -/***************************************************************************//** - * @file - * @brief Configuration header of Bootloader Interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_INTERFACE_CFG_H -#define BTL_INTERFACE_CFG_H - -#if !defined(BOOTLOADER_APPLOADER) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#include "btl_interface_cfg_s2c1.h" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) -#include "btl_interface_cfg_s2c2.h" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) -#include "btl_interface_cfg_s2c3.h" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) -#include "btl_interface_cfg_s2c4.h" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 1 -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 1 -#endif - -#endif // !BOOTLOADER_APPLOADER - -#endif // BTL_INTERFACE_CFG_H +/***************************************************************************//** + * @file + * @brief Configuration header of Bootloader Interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_INTERFACE_CFG_H +#define BTL_INTERFACE_CFG_H + +#if !defined(BOOTLOADER_APPLOADER) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#include "btl_interface_cfg_s2c1.h" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#include "btl_interface_cfg_s2c2.h" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) +#include "btl_interface_cfg_s2c3.h" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) +#include "btl_interface_cfg_s2c4.h" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 1 +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 1 +#endif + +#endif // !BOOTLOADER_APPLOADER + +#endif // BTL_INTERFACE_CFG_H diff --git a/locator_ncp/config/btl_interface_cfg_s2c2.h b/locator_ncp/config/btl_interface_cfg_s2c2.h index 214b061..37ff1bb 100644 --- a/locator_ncp/config/btl_interface_cfg_s2c2.h +++ b/locator_ncp/config/btl_interface_cfg_s2c2.h @@ -1,287 +1,287 @@ -/***************************************************************************//** - * @file - * @brief Configuration header of Bootloader Interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_INTERFACE_CFG_S2C2_H -#define BTL_INTERFACE_CFG_S2C2_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Bootloader Interface Trust Zone Security State Configuration - -// Disable multi tiered fallback logic -// The fault handling logic as well as the USART auto-detection logic will be disabled. -// The re-configuration of SMU will be handled by querying the running bootloader -// for the peripheral list. Querying the peripheral list is supported from the bootloader -// version 2.0.0. Check for the BOOTLOADER_CAPABILITY_PERIPHERAL_LIST capability to -// see if the running bootloader supports querying the peripheral list. -#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 0 - -// Disable peripheral access fault handling -// The fault handling triggered by an erroneous access of peripherals will be disabled. -// -// This should be disabled iff all the peripherals that are in use by the bootloader -// have been properly configured by the "Manually override security state of peripherals" option. -#define BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING 0 - -// Manually override the security state of peripherals in use by the bootloader -// Default: 0. -// Manually override the security state of peripherals. Choose the peripherals touched -// by the customized code to have a valid secure access state before interacting with the bootloader -// In practice, this means that the chosen peripherals will be available at the secure address, -// which is accessible by the bootloader. Once the application is entered back the secure access state -// is changed back to the original state. -// -// The USART auto-detection logic that detects which, if any, USART is in use by the bootloader -// will be disabled. Make sure to choose the correct USART used by the bootloader. -#define BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE 0 - -// EMU -// Update secure access state of EMU before calling into bootloader -#define BOOTLOADER_PPUSATD0_EMU 0 - -// CMU -// Update secure access state of CMU before calling into bootloader -#define BOOTLOADER_PPUSATD0_CMU 0 - -// HFXO0 -// Update secure access state of HFXO0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_HFXO0 0 - -// HFRCO0 -// Update secure access state of HFRCO0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_HFRCO0 0 - -// FSRCO -// Update secure access state of FSRCO before calling into bootloader -#define BOOTLOADER_PPUSATD0_FSRCO 0 - -// DPLL0 -// Update secure access state of DPLL0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_DPLL0 0 - -// LFXO -// Update secure access state of LFXO before calling into bootloader -#define BOOTLOADER_PPUSATD0_LFXO 0 - -// LFRCO -// Update secure access state of LFRCO before calling into bootloader -#define BOOTLOADER_PPUSATD0_LFRCO 0 - -// ULFRCO -// Update secure access state of ULFRCO before calling into bootloader -#define BOOTLOADER_PPUSATD0_ULFRCO 0 - -// MSC -// Update secure access state of MSC before calling into bootloader -#define BOOTLOADER_PPUSATD0_MSC 0 - -// ICACHE0 -// Update secure access state of ICACHE0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_ICACHE0 0 - -// PRS -// Update secure access state of PRS before calling into bootloader -#define BOOTLOADER_PPUSATD0_PRS 0 - -// GPIO -// Update secure access state of GPIO before calling into bootloader -#define BOOTLOADER_PPUSATD0_GPIO 0 - -// LDMA -// Update secure access state of LDMA before calling into bootloader -#define BOOTLOADER_PPUSATD0_LDMA 0 - -// LDMAXBAR -// Update secure access state of LDMAXBAR before calling into bootloader -#define BOOTLOADER_PPUSATD0_LDMAXBAR 0 - -// TIMER0 -// Update secure access state of TIMER0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_TIMER0 0 - -// TIMER1 -// Update secure access state of TIMER1 before calling into bootloader -#define BOOTLOADER_PPUSATD0_TIMER1 0 - -// TIMER2 -// Update secure access state of TIMER2 before calling into bootloader -#define BOOTLOADER_PPUSATD0_TIMER2 0 - -// TIMER3 -// Update secure access state of TIMER3 before calling into bootloader -#define BOOTLOADER_PPUSATD0_TIMER3 0 - -// TIMER4 -// Update secure access state of TIMER4 before calling into bootloader -#define BOOTLOADER_PPUSATD0_TIMER4 0 - -// USART0 -// Update secure access state of USART0 before calling into bootloader -#define BOOTLOADER_PPUSATD0_USART0 0 - -// USART1 -// Update secure access state of USART1 before calling into bootloader -#define BOOTLOADER_PPUSATD0_USART1 0 - -// BURTC -// Update secure access state of BURTC before calling into bootloader -#define BOOTLOADER_PPUSATD0_BURTC 0 - -// I2C1 -// Update secure access state of I2C1 before calling into bootloader -#define BOOTLOADER_PPUSATD0_I2C1 0 - -// CHIPTESTCTRL -// Update secure access state of CHIPTESTCTRL before calling into bootloader -#define BOOTLOADER_PPUSATD0_CHIPTESTCTRL 0 - -// SYSCFGCFGNS -// Update secure access state of SYSCFGCFGNS before calling into bootloader -#define BOOTLOADER_PPUSATD0_SYSCFGCFGNS 0 - -// SYSCFG -// Update secure access state of SYSCFG before calling into bootloader -#define BOOTLOADER_PPUSATD0_SYSCFG 0 - -// BURAM -// Update secure access state of BURAM before calling into bootloader -#define BOOTLOADER_PPUSATD0_BURAM 0 - -// IFADCDEBUG -// Update secure access state of IFADCDEBUG before calling into bootloader -#define BOOTLOADER_PPUSATD0_IFADCDEBUG 0 - -// GPCRC -// Update secure access state of GPCRC before calling into bootloader -#define BOOTLOADER_PPUSATD0_GPCRC 0 - -// DCI -// Update secure access state of DCI before calling into bootloader -#define BOOTLOADER_PPUSATD0_DCI 0 - -// DCDC -// Update secure access state of DCDC before calling into bootloader -#define BOOTLOADER_PPUSATD1_DCDC 0 - -// PDM -// Update secure access state of PDM before calling into bootloader -#define BOOTLOADER_PPUSATD1_PDM 0 - -// RFSENSE -// Update secure access state of RFSENSE before calling into bootloader -#define BOOTLOADER_PPUSATD1_RFSENSE 0 - -// RADIOAES -// Update secure access state of RADIOAES before calling into bootloader -#define BOOTLOADER_PPUSATD1_RADIOAES 0 - -// SMU -// Update secure access state of SMU before calling into bootloader -#define BOOTLOADER_PPUSATD1_SMU 0 - -// SMUCFGNS -// Update secure access state of SMUCFGNS before calling into bootloader -#define BOOTLOADER_PPUSATD1_SMUCFGNS 0 - -// RTCC -// Update secure access state of RTCC before calling into bootloader -#define BOOTLOADER_PPUSATD1_RTCC 0 - -// LETIMER0 -// Update secure access state of LETIMER0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_LETIMER0 0 - -// IADC0 -// Update secure access state of IADC0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_IADC0 0 - -// I2C0 -// Update secure access state of I2C0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_I2C0 0 - -// WDOG0 -// Update secure access state of WDOG0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_WDOG0 0 - -// AMUXCP0 -// Update secure access state of AMUXCP0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_AMUXCP0 0 - -// EUART0 -// Update secure access state of EUART0 before calling into bootloader -#define BOOTLOADER_PPUSATD1_EUART0 0 - -// CRYPTOACC -// Update secure access state of CRYPTOACC before calling into bootloader -#define BOOTLOADER_PPUSATD1_CRYPTOACC 0 - -// AHBRADIO -// Update secure access state of AHBRADIO before calling into bootloader -#define BOOTLOADER_PPUSATD1_AHBRADIO 0 -// - -// -// <<< end of configuration section >>> - -#if BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE == 1 -#define BOOTLOADER_PPUSATD0_MASK ((BOOTLOADER_PPUSATD0_EMU << _SMU_PPUSATD0_EMU_SHIFT) \ - | (BOOTLOADER_PPUSATD0_CMU << _SMU_PPUSATD0_CMU_SHIFT) \ - | (BOOTLOADER_PPUSATD0_HFXO0 << _SMU_PPUSATD0_HFXO0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_HFRCO0 << _SMU_PPUSATD0_HFRCO0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_FSRCO << _SMU_PPUSATD0_FSRCO_SHIFT) \ - | (BOOTLOADER_PPUSATD0_DPLL0 << _SMU_PPUSATD0_DPLL0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_LFXO << _SMU_PPUSATD0_LFXO_SHIFT) \ - | (BOOTLOADER_PPUSATD0_LFRCO << _SMU_PPUSATD0_LFRCO_SHIFT) \ - | (BOOTLOADER_PPUSATD0_ULFRCO << _SMU_PPUSATD0_ULFRCO_SHIFT) \ - | (BOOTLOADER_PPUSATD0_MSC << _SMU_PPUSATD0_MSC_SHIFT) \ - | (BOOTLOADER_PPUSATD0_ICACHE0 << _SMU_PPUSATD0_ICACHE0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_PRS << _SMU_PPUSATD0_PRS_SHIFT) \ - | (BOOTLOADER_PPUSATD0_GPIO << _SMU_PPUSATD0_GPIO_SHIFT) \ - | (BOOTLOADER_PPUSATD0_LDMA << _SMU_PPUSATD0_LDMA_SHIFT) \ - | (BOOTLOADER_PPUSATD0_LDMAXBAR << _SMU_PPUSATD0_LDMAXBAR_SHIFT) \ - | (BOOTLOADER_PPUSATD0_TIMER0 << _SMU_PPUSATD0_TIMER0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_TIMER1 << _SMU_PPUSATD0_TIMER1_SHIFT) \ - | (BOOTLOADER_PPUSATD0_TIMER2 << _SMU_PPUSATD0_TIMER2_SHIFT) \ - | (BOOTLOADER_PPUSATD0_TIMER3 << _SMU_PPUSATD0_TIMER3_SHIFT) \ - | (BOOTLOADER_PPUSATD0_TIMER4 << _SMU_PPUSATD0_TIMER4_SHIFT) \ - | (BOOTLOADER_PPUSATD0_USART0 << _SMU_PPUSATD0_USART0_SHIFT) \ - | (BOOTLOADER_PPUSATD0_USART1 << _SMU_PPUSATD0_USART1_SHIFT) \ - | (BOOTLOADER_PPUSATD0_BURTC << _SMU_PPUSATD0_BURTC_SHIFT) \ - | (BOOTLOADER_PPUSATD0_I2C1 << _SMU_PPUSATD0_I2C1_SHIFT) \ - | (BOOTLOADER_PPUSATD0_CHIPTESTCTRL << _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT) \ - | (BOOTLOADER_PPUSATD0_SYSCFGCFGNS << _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT) \ - | (BOOTLOADER_PPUSATD0_SYSCFG << _SMU_PPUSATD0_SYSCFG_SHIFT) \ - | (BOOTLOADER_PPUSATD0_BURAM << _SMU_PPUSATD0_BURAM_SHIFT) \ - | (BOOTLOADER_PPUSATD0_IFADCDEBUG << _SMU_PPUSATD0_IFADCDEBUG_SHIFT) \ - | (BOOTLOADER_PPUSATD0_GPCRC << _SMU_PPUSATD0_GPCRC_SHIFT) \ - | (BOOTLOADER_PPUSATD0_DCI << _SMU_PPUSATD0_DCI_SHIFT)) -#define BOOTLOADER_PPUSATD1_MASK ((BOOTLOADER_PPUSATD1_DCDC << _SMU_PPUSATD1_DCDC_SHIFT) \ - | (BOOTLOADER_PPUSATD1_PDM << _SMU_PPUSATD1_PDM_SHIFT) \ - | (BOOTLOADER_PPUSATD1_RFSENSE << _SMU_PPUSATD1_RFSENSE_SHIFT) \ - | (BOOTLOADER_PPUSATD1_RADIOAES << _SMU_PPUSATD1_RADIOAES_SHIFT) \ - | (BOOTLOADER_PPUSATD1_SMU << _SMU_PPUSATD1_SMU_SHIFT) \ - | (BOOTLOADER_PPUSATD1_SMUCFGNS << _SMU_PPUSATD1_SMUCFGNS_SHIFT) \ - | (BOOTLOADER_PPUSATD1_RTCC << _SMU_PPUSATD1_RTCC_SHIFT) \ - | (BOOTLOADER_PPUSATD1_LETIMER0 << _SMU_PPUSATD1_LETIMER0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_IADC0 << _SMU_PPUSATD1_IADC0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_I2C0 << _SMU_PPUSATD1_I2C0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_WDOG0 << _SMU_PPUSATD1_WDOG0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_AMUXCP0 << _SMU_PPUSATD1_AMUXCP0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_EUART0 << _SMU_PPUSATD1_EUART0_SHIFT) \ - | (BOOTLOADER_PPUSATD1_CRYPTOACC << _SMU_PPUSATD1_CRYPTOACC_SHIFT) \ - | (BOOTLOADER_PPUSATD1_AHBRADIO << _SMU_PPUSATD1_AHBRADIO_SHIFT)) -#endif // BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE - -#endif // BTL_INTERFACE_CFG_S2C2_H +/***************************************************************************//** + * @file + * @brief Configuration header of Bootloader Interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_INTERFACE_CFG_S2C2_H +#define BTL_INTERFACE_CFG_S2C2_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Bootloader Interface Trust Zone Security State Configuration + +// Disable multi tiered fallback logic +// The fault handling logic as well as the USART auto-detection logic will be disabled. +// The re-configuration of SMU will be handled by querying the running bootloader +// for the peripheral list. Querying the peripheral list is supported from the bootloader +// version 2.0.0. Check for the BOOTLOADER_CAPABILITY_PERIPHERAL_LIST capability to +// see if the running bootloader supports querying the peripheral list. +#define BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION 0 + +// Disable peripheral access fault handling +// The fault handling triggered by an erroneous access of peripherals will be disabled. +// +// This should be disabled iff all the peripherals that are in use by the bootloader +// have been properly configured by the "Manually override security state of peripherals" option. +#define BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING 0 + +// Manually override the security state of peripherals in use by the bootloader +// Default: 0. +// Manually override the security state of peripherals. Choose the peripherals touched +// by the customized code to have a valid secure access state before interacting with the bootloader +// In practice, this means that the chosen peripherals will be available at the secure address, +// which is accessible by the bootloader. Once the application is entered back the secure access state +// is changed back to the original state. +// +// The USART auto-detection logic that detects which, if any, USART is in use by the bootloader +// will be disabled. Make sure to choose the correct USART used by the bootloader. +#define BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE 0 + +// EMU +// Update secure access state of EMU before calling into bootloader +#define BOOTLOADER_PPUSATD0_EMU 0 + +// CMU +// Update secure access state of CMU before calling into bootloader +#define BOOTLOADER_PPUSATD0_CMU 0 + +// HFXO0 +// Update secure access state of HFXO0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_HFXO0 0 + +// HFRCO0 +// Update secure access state of HFRCO0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_HFRCO0 0 + +// FSRCO +// Update secure access state of FSRCO before calling into bootloader +#define BOOTLOADER_PPUSATD0_FSRCO 0 + +// DPLL0 +// Update secure access state of DPLL0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_DPLL0 0 + +// LFXO +// Update secure access state of LFXO before calling into bootloader +#define BOOTLOADER_PPUSATD0_LFXO 0 + +// LFRCO +// Update secure access state of LFRCO before calling into bootloader +#define BOOTLOADER_PPUSATD0_LFRCO 0 + +// ULFRCO +// Update secure access state of ULFRCO before calling into bootloader +#define BOOTLOADER_PPUSATD0_ULFRCO 0 + +// MSC +// Update secure access state of MSC before calling into bootloader +#define BOOTLOADER_PPUSATD0_MSC 0 + +// ICACHE0 +// Update secure access state of ICACHE0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_ICACHE0 0 + +// PRS +// Update secure access state of PRS before calling into bootloader +#define BOOTLOADER_PPUSATD0_PRS 0 + +// GPIO +// Update secure access state of GPIO before calling into bootloader +#define BOOTLOADER_PPUSATD0_GPIO 0 + +// LDMA +// Update secure access state of LDMA before calling into bootloader +#define BOOTLOADER_PPUSATD0_LDMA 0 + +// LDMAXBAR +// Update secure access state of LDMAXBAR before calling into bootloader +#define BOOTLOADER_PPUSATD0_LDMAXBAR 0 + +// TIMER0 +// Update secure access state of TIMER0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_TIMER0 0 + +// TIMER1 +// Update secure access state of TIMER1 before calling into bootloader +#define BOOTLOADER_PPUSATD0_TIMER1 0 + +// TIMER2 +// Update secure access state of TIMER2 before calling into bootloader +#define BOOTLOADER_PPUSATD0_TIMER2 0 + +// TIMER3 +// Update secure access state of TIMER3 before calling into bootloader +#define BOOTLOADER_PPUSATD0_TIMER3 0 + +// TIMER4 +// Update secure access state of TIMER4 before calling into bootloader +#define BOOTLOADER_PPUSATD0_TIMER4 0 + +// USART0 +// Update secure access state of USART0 before calling into bootloader +#define BOOTLOADER_PPUSATD0_USART0 0 + +// USART1 +// Update secure access state of USART1 before calling into bootloader +#define BOOTLOADER_PPUSATD0_USART1 0 + +// BURTC +// Update secure access state of BURTC before calling into bootloader +#define BOOTLOADER_PPUSATD0_BURTC 0 + +// I2C1 +// Update secure access state of I2C1 before calling into bootloader +#define BOOTLOADER_PPUSATD0_I2C1 0 + +// CHIPTESTCTRL +// Update secure access state of CHIPTESTCTRL before calling into bootloader +#define BOOTLOADER_PPUSATD0_CHIPTESTCTRL 0 + +// SYSCFGCFGNS +// Update secure access state of SYSCFGCFGNS before calling into bootloader +#define BOOTLOADER_PPUSATD0_SYSCFGCFGNS 0 + +// SYSCFG +// Update secure access state of SYSCFG before calling into bootloader +#define BOOTLOADER_PPUSATD0_SYSCFG 0 + +// BURAM +// Update secure access state of BURAM before calling into bootloader +#define BOOTLOADER_PPUSATD0_BURAM 0 + +// IFADCDEBUG +// Update secure access state of IFADCDEBUG before calling into bootloader +#define BOOTLOADER_PPUSATD0_IFADCDEBUG 0 + +// GPCRC +// Update secure access state of GPCRC before calling into bootloader +#define BOOTLOADER_PPUSATD0_GPCRC 0 + +// DCI +// Update secure access state of DCI before calling into bootloader +#define BOOTLOADER_PPUSATD0_DCI 0 + +// DCDC +// Update secure access state of DCDC before calling into bootloader +#define BOOTLOADER_PPUSATD1_DCDC 0 + +// PDM +// Update secure access state of PDM before calling into bootloader +#define BOOTLOADER_PPUSATD1_PDM 0 + +// RFSENSE +// Update secure access state of RFSENSE before calling into bootloader +#define BOOTLOADER_PPUSATD1_RFSENSE 0 + +// RADIOAES +// Update secure access state of RADIOAES before calling into bootloader +#define BOOTLOADER_PPUSATD1_RADIOAES 0 + +// SMU +// Update secure access state of SMU before calling into bootloader +#define BOOTLOADER_PPUSATD1_SMU 0 + +// SMUCFGNS +// Update secure access state of SMUCFGNS before calling into bootloader +#define BOOTLOADER_PPUSATD1_SMUCFGNS 0 + +// RTCC +// Update secure access state of RTCC before calling into bootloader +#define BOOTLOADER_PPUSATD1_RTCC 0 + +// LETIMER0 +// Update secure access state of LETIMER0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_LETIMER0 0 + +// IADC0 +// Update secure access state of IADC0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_IADC0 0 + +// I2C0 +// Update secure access state of I2C0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_I2C0 0 + +// WDOG0 +// Update secure access state of WDOG0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_WDOG0 0 + +// AMUXCP0 +// Update secure access state of AMUXCP0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_AMUXCP0 0 + +// EUART0 +// Update secure access state of EUART0 before calling into bootloader +#define BOOTLOADER_PPUSATD1_EUART0 0 + +// CRYPTOACC +// Update secure access state of CRYPTOACC before calling into bootloader +#define BOOTLOADER_PPUSATD1_CRYPTOACC 0 + +// AHBRADIO +// Update secure access state of AHBRADIO before calling into bootloader +#define BOOTLOADER_PPUSATD1_AHBRADIO 0 +// + +// +// <<< end of configuration section >>> + +#if BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE == 1 +#define BOOTLOADER_PPUSATD0_MASK ((BOOTLOADER_PPUSATD0_EMU << _SMU_PPUSATD0_EMU_SHIFT) \ + | (BOOTLOADER_PPUSATD0_CMU << _SMU_PPUSATD0_CMU_SHIFT) \ + | (BOOTLOADER_PPUSATD0_HFXO0 << _SMU_PPUSATD0_HFXO0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_HFRCO0 << _SMU_PPUSATD0_HFRCO0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_FSRCO << _SMU_PPUSATD0_FSRCO_SHIFT) \ + | (BOOTLOADER_PPUSATD0_DPLL0 << _SMU_PPUSATD0_DPLL0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_LFXO << _SMU_PPUSATD0_LFXO_SHIFT) \ + | (BOOTLOADER_PPUSATD0_LFRCO << _SMU_PPUSATD0_LFRCO_SHIFT) \ + | (BOOTLOADER_PPUSATD0_ULFRCO << _SMU_PPUSATD0_ULFRCO_SHIFT) \ + | (BOOTLOADER_PPUSATD0_MSC << _SMU_PPUSATD0_MSC_SHIFT) \ + | (BOOTLOADER_PPUSATD0_ICACHE0 << _SMU_PPUSATD0_ICACHE0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_PRS << _SMU_PPUSATD0_PRS_SHIFT) \ + | (BOOTLOADER_PPUSATD0_GPIO << _SMU_PPUSATD0_GPIO_SHIFT) \ + | (BOOTLOADER_PPUSATD0_LDMA << _SMU_PPUSATD0_LDMA_SHIFT) \ + | (BOOTLOADER_PPUSATD0_LDMAXBAR << _SMU_PPUSATD0_LDMAXBAR_SHIFT) \ + | (BOOTLOADER_PPUSATD0_TIMER0 << _SMU_PPUSATD0_TIMER0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_TIMER1 << _SMU_PPUSATD0_TIMER1_SHIFT) \ + | (BOOTLOADER_PPUSATD0_TIMER2 << _SMU_PPUSATD0_TIMER2_SHIFT) \ + | (BOOTLOADER_PPUSATD0_TIMER3 << _SMU_PPUSATD0_TIMER3_SHIFT) \ + | (BOOTLOADER_PPUSATD0_TIMER4 << _SMU_PPUSATD0_TIMER4_SHIFT) \ + | (BOOTLOADER_PPUSATD0_USART0 << _SMU_PPUSATD0_USART0_SHIFT) \ + | (BOOTLOADER_PPUSATD0_USART1 << _SMU_PPUSATD0_USART1_SHIFT) \ + | (BOOTLOADER_PPUSATD0_BURTC << _SMU_PPUSATD0_BURTC_SHIFT) \ + | (BOOTLOADER_PPUSATD0_I2C1 << _SMU_PPUSATD0_I2C1_SHIFT) \ + | (BOOTLOADER_PPUSATD0_CHIPTESTCTRL << _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT) \ + | (BOOTLOADER_PPUSATD0_SYSCFGCFGNS << _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT) \ + | (BOOTLOADER_PPUSATD0_SYSCFG << _SMU_PPUSATD0_SYSCFG_SHIFT) \ + | (BOOTLOADER_PPUSATD0_BURAM << _SMU_PPUSATD0_BURAM_SHIFT) \ + | (BOOTLOADER_PPUSATD0_IFADCDEBUG << _SMU_PPUSATD0_IFADCDEBUG_SHIFT) \ + | (BOOTLOADER_PPUSATD0_GPCRC << _SMU_PPUSATD0_GPCRC_SHIFT) \ + | (BOOTLOADER_PPUSATD0_DCI << _SMU_PPUSATD0_DCI_SHIFT)) +#define BOOTLOADER_PPUSATD1_MASK ((BOOTLOADER_PPUSATD1_DCDC << _SMU_PPUSATD1_DCDC_SHIFT) \ + | (BOOTLOADER_PPUSATD1_PDM << _SMU_PPUSATD1_PDM_SHIFT) \ + | (BOOTLOADER_PPUSATD1_RFSENSE << _SMU_PPUSATD1_RFSENSE_SHIFT) \ + | (BOOTLOADER_PPUSATD1_RADIOAES << _SMU_PPUSATD1_RADIOAES_SHIFT) \ + | (BOOTLOADER_PPUSATD1_SMU << _SMU_PPUSATD1_SMU_SHIFT) \ + | (BOOTLOADER_PPUSATD1_SMUCFGNS << _SMU_PPUSATD1_SMUCFGNS_SHIFT) \ + | (BOOTLOADER_PPUSATD1_RTCC << _SMU_PPUSATD1_RTCC_SHIFT) \ + | (BOOTLOADER_PPUSATD1_LETIMER0 << _SMU_PPUSATD1_LETIMER0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_IADC0 << _SMU_PPUSATD1_IADC0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_I2C0 << _SMU_PPUSATD1_I2C0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_WDOG0 << _SMU_PPUSATD1_WDOG0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_AMUXCP0 << _SMU_PPUSATD1_AMUXCP0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_EUART0 << _SMU_PPUSATD1_EUART0_SHIFT) \ + | (BOOTLOADER_PPUSATD1_CRYPTOACC << _SMU_PPUSATD1_CRYPTOACC_SHIFT) \ + | (BOOTLOADER_PPUSATD1_AHBRADIO << _SMU_PPUSATD1_AHBRADIO_SHIFT)) +#endif // BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE + +#endif // BTL_INTERFACE_CFG_S2C2_H diff --git a/locator_ncp/config/dmadrv_config.h b/locator_ncp/config/dmadrv_config.h index ed105e4..f113d72 100644 --- a/locator_ncp/config/dmadrv_config.h +++ b/locator_ncp/config/dmadrv_config.h @@ -1,26 +1,26 @@ -#ifndef DMADRV_CONFIG_H -#define DMADRV_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMA interrupt priority <0-15> -// Priority of the DMA interrupt. Smaller number equals higher priority. -// Default: 8 -#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 8 - -// Number of available channels <1-8> -// Number of DMA channels supported by the driver. A lower channel count -// will reduce RAM memory footprint. The default is to support all channels -// on the device. -// Default: 8 -#define EMDRV_DMADRV_DMA_CH_COUNT 8 - -// Number of fixed priority channels -// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, -// and channels [CH_PRIORITY, CH_COUNT] as round-robin. -// Default: 0 -#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 - -// <<< end of configuration section >>> - -#endif // DMADRV_CONFIG_H +#ifndef DMADRV_CONFIG_H +#define DMADRV_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMA interrupt priority <0-15> +// Priority of the DMA interrupt. Smaller number equals higher priority. +// Default: 8 +#define EMDRV_DMADRV_DMA_IRQ_PRIORITY 8 + +// Number of available channels <1-8> +// Number of DMA channels supported by the driver. A lower channel count +// will reduce RAM memory footprint. The default is to support all channels +// on the device. +// Default: 8 +#define EMDRV_DMADRV_DMA_CH_COUNT 8 + +// Number of fixed priority channels +// This will configure channels [0, CH_PRIORITY - 1] as fixed priority, +// and channels [CH_PRIORITY, CH_COUNT] as round-robin. +// Default: 0 +#define EMDRV_DMADRV_DMA_CH_PRIORITY 0 + +// <<< end of configuration section >>> + +#endif // DMADRV_CONFIG_H diff --git a/locator_ncp/config/emlib_core_debug_config.h b/locator_ncp/config/emlib_core_debug_config.h index 07ee9b9..13e4b91 100644 --- a/locator_ncp/config/emlib_core_debug_config.h +++ b/locator_ncp/config/emlib_core_debug_config.h @@ -1,45 +1,45 @@ -/***************************************************************************//** - * @file - * @brief emlib_core Configuration - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CORE_DEBUG_CONFIG_H -#define EM_CORE_DEBUG_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Core Configuration - -// Enables measuring of interrupt disable time for debugging purposes. -// Default: 0 -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 - -// - -// <<< end of configuration section >>> -#endif // EM_CORE_CONFIG_H +/***************************************************************************//** + * @file + * @brief emlib_core Configuration + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_DEBUG_CONFIG_H +#define EM_CORE_DEBUG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Core Configuration + +// Enables measuring of interrupt disable time for debugging purposes. +// Default: 0 +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 + +// + +// <<< end of configuration section >>> +#endif // EM_CORE_CONFIG_H diff --git a/locator_ncp/config/nvm3_default_config.h b/locator_ncp/config/nvm3_default_config.h index 48eb589..52e249f 100644 --- a/locator_ncp/config/nvm3_default_config.h +++ b/locator_ncp/config/nvm3_default_config.h @@ -1,45 +1,45 @@ -#ifndef NVM3_DEFAULT_CONFIG_H -#define NVM3_DEFAULT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// NVM3 Default Instance Configuration - -#ifndef NVM3_DEFAULT_CACHE_SIZE -// NVM3 Default Instance Cache Size -// Number of NVM3 objects to cache. To reduce access times this number -// should be equal to or higher than the number of NVM3 objects in the -// default NVM3 instance. -// Default: 200 -#define NVM3_DEFAULT_CACHE_SIZE 200 -#endif - -#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE -// NVM3 Default Instance Max Object Size -// Max NVM3 object size that can be stored. -// Default: 254 -#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 -#endif - -#ifndef NVM3_DEFAULT_REPACK_HEADROOM -// NVM3 Default Instance User Repack Headroom -// Headroom determining how many bytes below the forced repack limit the user -// repack limit should be placed. The default is 0, which means the user and -// forced repack limits are equal. -// Default: 0 -#define NVM3_DEFAULT_REPACK_HEADROOM 0 -#endif - -#ifndef NVM3_DEFAULT_NVM_SIZE -// NVM3 Default Instance Size -// Size of the NVM3 storage region in flash. This size should be aligned with -// the flash page size of the device. -// Default: 40960 -#define NVM3_DEFAULT_NVM_SIZE 40960 -#endif - -// - -// <<< end of configuration section >>> - -#endif // NVM3_DEFAULT_CONFIG_H +#ifndef NVM3_DEFAULT_CONFIG_H +#define NVM3_DEFAULT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// NVM3 Default Instance Configuration + +#ifndef NVM3_DEFAULT_CACHE_SIZE +// NVM3 Default Instance Cache Size +// Number of NVM3 objects to cache. To reduce access times this number +// should be equal to or higher than the number of NVM3 objects in the +// default NVM3 instance. +// Default: 200 +#define NVM3_DEFAULT_CACHE_SIZE 200 +#endif + +#ifndef NVM3_DEFAULT_MAX_OBJECT_SIZE +// NVM3 Default Instance Max Object Size +// Max NVM3 object size that can be stored. +// Default: 254 +#define NVM3_DEFAULT_MAX_OBJECT_SIZE 254 +#endif + +#ifndef NVM3_DEFAULT_REPACK_HEADROOM +// NVM3 Default Instance User Repack Headroom +// Headroom determining how many bytes below the forced repack limit the user +// repack limit should be placed. The default is 0, which means the user and +// forced repack limits are equal. +// Default: 0 +#define NVM3_DEFAULT_REPACK_HEADROOM 0 +#endif + +#ifndef NVM3_DEFAULT_NVM_SIZE +// NVM3 Default Instance Size +// Size of the NVM3 storage region in flash. This size should be aligned with +// the flash page size of the device. +// Default: 40960 +#define NVM3_DEFAULT_NVM_SIZE 40960 +#endif + +// + +// <<< end of configuration section >>> + +#endif // NVM3_DEFAULT_CONFIG_H diff --git a/locator_ncp/config/pin_config.h b/locator_ncp/config/pin_config.h index 34e7787..2931820 100644 --- a/locator_ncp/config/pin_config.h +++ b/locator_ncp/config/pin_config.h @@ -1,172 +1,172 @@ -#ifndef PIN_CONFIG_H -#define PIN_CONFIG_H - -// $[CMU] -// [CMU]$ - -// $[LFXO] -// LFXO LFXTAL_I on PD01 -#ifndef LFXO_LFXTAL_I_PORT -#define LFXO_LFXTAL_I_PORT gpioPortD -#endif -#ifndef LFXO_LFXTAL_I_PIN -#define LFXO_LFXTAL_I_PIN 1 -#endif - -// LFXO LFXTAL_O on PD00 -#ifndef LFXO_LFXTAL_O_PORT -#define LFXO_LFXTAL_O_PORT gpioPortD -#endif -#ifndef LFXO_LFXTAL_O_PIN -#define LFXO_LFXTAL_O_PIN 0 -#endif - -// [LFXO]$ - -// $[PRS.ASYNCH0] -// [PRS.ASYNCH0]$ - -// $[PRS.ASYNCH1] -// [PRS.ASYNCH1]$ - -// $[PRS.ASYNCH2] -// [PRS.ASYNCH2]$ - -// $[PRS.ASYNCH3] -// [PRS.ASYNCH3]$ - -// $[PRS.ASYNCH4] -// [PRS.ASYNCH4]$ - -// $[PRS.ASYNCH5] -// [PRS.ASYNCH5]$ - -// $[PRS.ASYNCH6] -// [PRS.ASYNCH6]$ - -// $[PRS.ASYNCH7] -// [PRS.ASYNCH7]$ - -// $[PRS.ASYNCH8] -// [PRS.ASYNCH8]$ - -// $[PRS.ASYNCH9] -// [PRS.ASYNCH9]$ - -// $[PRS.ASYNCH10] -// [PRS.ASYNCH10]$ - -// $[PRS.ASYNCH11] -// [PRS.ASYNCH11]$ - -// $[PRS.SYNCH0] -// [PRS.SYNCH0]$ - -// $[PRS.SYNCH1] -// [PRS.SYNCH1]$ - -// $[PRS.SYNCH2] -// [PRS.SYNCH2]$ - -// $[PRS.SYNCH3] -// [PRS.SYNCH3]$ - -// $[GPIO] -// GPIO SWV on PA03 -#ifndef GPIO_SWV_PORT -#define GPIO_SWV_PORT gpioPortA -#endif -#ifndef GPIO_SWV_PIN -#define GPIO_SWV_PIN 3 -#endif - -// [GPIO]$ - -// $[TIMER0] -// [TIMER0]$ - -// $[TIMER1] -// [TIMER1]$ - -// $[TIMER2] -// [TIMER2]$ - -// $[TIMER3] -// [TIMER3]$ - -// $[TIMER4] -// [TIMER4]$ - -// $[USART0] -// [USART0]$ - -// $[USART1] -// USART1 CTS on PA08 -#ifndef USART1_CTS_PORT -#define USART1_CTS_PORT gpioPortA -#endif -#ifndef USART1_CTS_PIN -#define USART1_CTS_PIN 8 -#endif - -// USART1 RTS on PA07 -#ifndef USART1_RTS_PORT -#define USART1_RTS_PORT gpioPortA -#endif -#ifndef USART1_RTS_PIN -#define USART1_RTS_PIN 7 -#endif - -// USART1 RX on PA06 -#ifndef USART1_RX_PORT -#define USART1_RX_PORT gpioPortA -#endif -#ifndef USART1_RX_PIN -#define USART1_RX_PIN 6 -#endif - -// USART1 TX on PA05 -#ifndef USART1_TX_PORT -#define USART1_TX_PORT gpioPortA -#endif -#ifndef USART1_TX_PIN -#define USART1_TX_PIN 5 -#endif - -// [USART1]$ - -// $[I2C1] -// [I2C1]$ - -// $[PDM] -// [PDM]$ - -// $[LETIMER0] -// [LETIMER0]$ - -// $[IADC0] -// [IADC0]$ - -// $[I2C0] -// [I2C0]$ - -// $[EUART0] -// [EUART0]$ - -// $[PTI] -// [PTI]$ - -// $[MODEM] -// [MODEM]$ - -// $[CUSTOM_PIN_NAME] -#ifndef _PORT -#define _PORT gpioPortA -#endif -#ifndef _PIN -#define _PIN 0 -#endif - -// [CUSTOM_PIN_NAME]$ - -#endif // PIN_CONFIG_H +#ifndef PIN_CONFIG_H +#define PIN_CONFIG_H + +// $[CMU] +// [CMU]$ + +// $[LFXO] +// LFXO LFXTAL_I on PD01 +#ifndef LFXO_LFXTAL_I_PORT +#define LFXO_LFXTAL_I_PORT gpioPortD +#endif +#ifndef LFXO_LFXTAL_I_PIN +#define LFXO_LFXTAL_I_PIN 1 +#endif + +// LFXO LFXTAL_O on PD00 +#ifndef LFXO_LFXTAL_O_PORT +#define LFXO_LFXTAL_O_PORT gpioPortD +#endif +#ifndef LFXO_LFXTAL_O_PIN +#define LFXO_LFXTAL_O_PIN 0 +#endif + +// [LFXO]$ + +// $[PRS.ASYNCH0] +// [PRS.ASYNCH0]$ + +// $[PRS.ASYNCH1] +// [PRS.ASYNCH1]$ + +// $[PRS.ASYNCH2] +// [PRS.ASYNCH2]$ + +// $[PRS.ASYNCH3] +// [PRS.ASYNCH3]$ + +// $[PRS.ASYNCH4] +// [PRS.ASYNCH4]$ + +// $[PRS.ASYNCH5] +// [PRS.ASYNCH5]$ + +// $[PRS.ASYNCH6] +// [PRS.ASYNCH6]$ + +// $[PRS.ASYNCH7] +// [PRS.ASYNCH7]$ + +// $[PRS.ASYNCH8] +// [PRS.ASYNCH8]$ + +// $[PRS.ASYNCH9] +// [PRS.ASYNCH9]$ + +// $[PRS.ASYNCH10] +// [PRS.ASYNCH10]$ + +// $[PRS.ASYNCH11] +// [PRS.ASYNCH11]$ + +// $[PRS.SYNCH0] +// [PRS.SYNCH0]$ + +// $[PRS.SYNCH1] +// [PRS.SYNCH1]$ + +// $[PRS.SYNCH2] +// [PRS.SYNCH2]$ + +// $[PRS.SYNCH3] +// [PRS.SYNCH3]$ + +// $[GPIO] +// GPIO SWV on PA03 +#ifndef GPIO_SWV_PORT +#define GPIO_SWV_PORT gpioPortA +#endif +#ifndef GPIO_SWV_PIN +#define GPIO_SWV_PIN 3 +#endif + +// [GPIO]$ + +// $[TIMER0] +// [TIMER0]$ + +// $[TIMER1] +// [TIMER1]$ + +// $[TIMER2] +// [TIMER2]$ + +// $[TIMER3] +// [TIMER3]$ + +// $[TIMER4] +// [TIMER4]$ + +// $[USART0] +// [USART0]$ + +// $[USART1] +// USART1 CTS on PA08 +#ifndef USART1_CTS_PORT +#define USART1_CTS_PORT gpioPortA +#endif +#ifndef USART1_CTS_PIN +#define USART1_CTS_PIN 8 +#endif + +// USART1 RTS on PA07 +#ifndef USART1_RTS_PORT +#define USART1_RTS_PORT gpioPortA +#endif +#ifndef USART1_RTS_PIN +#define USART1_RTS_PIN 7 +#endif + +// USART1 RX on PA06 +#ifndef USART1_RX_PORT +#define USART1_RX_PORT gpioPortA +#endif +#ifndef USART1_RX_PIN +#define USART1_RX_PIN 6 +#endif + +// USART1 TX on PA05 +#ifndef USART1_TX_PORT +#define USART1_TX_PORT gpioPortA +#endif +#ifndef USART1_TX_PIN +#define USART1_TX_PIN 5 +#endif + +// [USART1]$ + +// $[I2C1] +// [I2C1]$ + +// $[PDM] +// [PDM]$ + +// $[LETIMER0] +// [LETIMER0]$ + +// $[IADC0] +// [IADC0]$ + +// $[I2C0] +// [I2C0]$ + +// $[EUART0] +// [EUART0]$ + +// $[PTI] +// [PTI]$ + +// $[MODEM] +// [MODEM]$ + +// $[CUSTOM_PIN_NAME] +#ifndef _PORT +#define _PORT gpioPortA +#endif +#ifndef _PIN +#define _PIN 0 +#endif + +// [CUSTOM_PIN_NAME]$ + +#endif // PIN_CONFIG_H diff --git a/locator_ncp/config/psa_crypto_config.h b/locator_ncp/config/psa_crypto_config.h index 7850924..f3c8b26 100644 --- a/locator_ncp/config/psa_crypto_config.h +++ b/locator_ncp/config/psa_crypto_config.h @@ -1,134 +1,134 @@ -#ifndef PSA_CRYPTO_CONFIG_H -#define PSA_CRYPTO_CONFIG_H - -// ----------------------------------------------------------------------------- -// User exposed config options - -// <<< Use Configuration Wizard in Context Menu >>> - -// Key management configuration - -// PSA User Maximum Open Keys Count <0-128> -// Maximum amount of keys that the user application will have open -// simultaneously. In context of PSA Crypto, an open key means any key -// either stored in RAM (lifetime set to PSA_KEY_LIFETIME_VOLATILE), or -// used as part of a cryptographic operation. -// When using a key for a multi-part (setup/update/finish) operation, a key -// is considered to be open from the moment the operation is successfully -// setup, until it finishes or aborts. -// When an application tries to open more keys than this value accounts for, -// the PSA API may return PSA_ERROR_INSUFFICIENT_MEMORY. Keep in mind that -// other software included in the application (e.g. wireless protocol stacks) -// also can have a need to have open keys in PSA Crypto. This could lead to -// a race condition when the application key slot count is set too low for -// the actual usage of the application, as a software stack may not fail -// gracefully in case an application opens more than its declared amount of -// keys, thereby precluding the stack from functioning. -// Default: 4 -#define SL_PSA_KEY_USER_SLOT_COUNT 0 - -// PSA Maximum User Persistent Keys Count <0-1024> -// Maximum amount of keys (or other files) that can be stored persistently -// by the application through the PSA interface, when persistent storage -// support for PSA Crypto is included in the project. -// Due to caching logic, this setting does have an impact on static RAM usage. -// Note that this number is added to the potential requirements from other -// software components in the project, such that the total amount of keys -// which can be stored through the ITS backend can be higher than what is -// configured here. -// -// WARNING: When changing this setting on an application that is already -// deployed, and thus will get the change through an application upgrade, -// care should be taken to ensure that the setting is only ever increased, -// and never decreased. Decreasing this setting might cause previously -// stored keys/files to become inaccessible. -// -// It is not possible to change this setting when using V3 ITS Driver. -// The file-storage indexing is dependent on the maximum number of files, -// and if SL_PSA_ITS_USER_MAX_FILES is changed, ITS should be cleared and -// all files need to be stored again. -// Default: 128 -#define SL_PSA_ITS_USER_MAX_FILES (128) - -// Enable V1 Format Support For ITS Files <0-1> -// Devices that used PSA ITS together with gecko_sdk_3.1.x or earlier -// might have keys (or other files) stored in V1 format. -// If no v1 files are used, its support can be disabled for space -// optimization. -// Default: 0 -#define SL_PSA_ITS_SUPPORT_V1_DRIVER 0 - -// Enable V2 ITS Driver Support <0-1> -// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys -// (or other files) stored using different address range. Enabling this -// config option adds upgrade code which converts V2 (and V1 if -// supported) format ITS keys/files to the latest V3 format. Update is -// fully automatic, needs to be run once and require extra flash space of -// approximately the size of the largest key. -// V1 ITS driver support can be disabled if the device has never used ITS -// driver before in GSDK 4.1.x and earlier, or the keys has been already -// migrated. -// Default: 0 -#define SL_PSA_ITS_SUPPORT_V2_DRIVER 0 - -// Enable support for V3 ITS Driver <0-1> -// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys -// (or other files) stored using different address range. In rare case -// that those devices have full nvm3 and not enough space for the -// upgrade, (that requires an extra space to store largest key in memory -// twice), this config option can disable v3 driver and use v2 one. -// To upgrade the device, make space for the upgrade, and enable v3 driver again. -// -// WARNING: When using V3 driver, it is not possible to increase or decrease -// the value of SL_PSA_ITS_USER_MAX_FILES. If the change of -// SL_PSA_ITS_USER_MAX_FILES is required, ITS should be cleared and -// all files need to be stored again. -// Default: 1 -#define SL_PSA_ITS_SUPPORT_V3_DRIVER 1 - -// Built-in AES Key Mode of Operation -// CTR Mode -// CFB Mode -// OFB Mode -// ECB Mode -// CBC Mode (no padding) -// CBC Mode (PKCS#7 padding) -// PSA Crypto only allows one specific usage algorithm per built-in key ID. -// Default: PSA_ALG_CTR -#define SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG (PSA_ALG_CTR) - -#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG -// Built-in PUF Key Algorithm -// PBKDF2 (CMAC-AES-128-PRF) -// CMAC -// PSA Crypto only allows one specific usage algorithm per built-in key ID. -// It is recommended to only use the PUF key for deriving further key -// material. -// Default: PSA_ALG_PBKDF2_AES_CMAC_PRF_128 -#define SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG (PSA_ALG_PBKDF2_AES_CMAC_PRF_128) -#endif // SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG - -// - -// <<< end of configuration section >>> - -// ----------------------------------------------------------------------------- -// Sub-files - -#if defined(SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE) - #include SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE -#else - #include "sli_psa_config_autogen.h" -#endif - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - #include "sli_psa_tfm_translation.h" -#endif - -#if SL_MBEDTLS_DRIVERS_ENABLED - #include "sli_psa_acceleration.h" -#endif - -#include "sli_psa_builtin_config_autogen.h" - -#endif // PSA_CRYPTO_CONFIG_H +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// Key management configuration + +// PSA User Maximum Open Keys Count <0-128> +// Maximum amount of keys that the user application will have open +// simultaneously. In context of PSA Crypto, an open key means any key +// either stored in RAM (lifetime set to PSA_KEY_LIFETIME_VOLATILE), or +// used as part of a cryptographic operation. +// When using a key for a multi-part (setup/update/finish) operation, a key +// is considered to be open from the moment the operation is successfully +// setup, until it finishes or aborts. +// When an application tries to open more keys than this value accounts for, +// the PSA API may return PSA_ERROR_INSUFFICIENT_MEMORY. Keep in mind that +// other software included in the application (e.g. wireless protocol stacks) +// also can have a need to have open keys in PSA Crypto. This could lead to +// a race condition when the application key slot count is set too low for +// the actual usage of the application, as a software stack may not fail +// gracefully in case an application opens more than its declared amount of +// keys, thereby precluding the stack from functioning. +// Default: 4 +#define SL_PSA_KEY_USER_SLOT_COUNT 0 + +// PSA Maximum User Persistent Keys Count <0-1024> +// Maximum amount of keys (or other files) that can be stored persistently +// by the application through the PSA interface, when persistent storage +// support for PSA Crypto is included in the project. +// Due to caching logic, this setting does have an impact on static RAM usage. +// Note that this number is added to the potential requirements from other +// software components in the project, such that the total amount of keys +// which can be stored through the ITS backend can be higher than what is +// configured here. +// +// WARNING: When changing this setting on an application that is already +// deployed, and thus will get the change through an application upgrade, +// care should be taken to ensure that the setting is only ever increased, +// and never decreased. Decreasing this setting might cause previously +// stored keys/files to become inaccessible. +// +// It is not possible to change this setting when using V3 ITS Driver. +// The file-storage indexing is dependent on the maximum number of files, +// and if SL_PSA_ITS_USER_MAX_FILES is changed, ITS should be cleared and +// all files need to be stored again. +// Default: 128 +#define SL_PSA_ITS_USER_MAX_FILES (128) + +// Enable V1 Format Support For ITS Files <0-1> +// Devices that used PSA ITS together with gecko_sdk_3.1.x or earlier +// might have keys (or other files) stored in V1 format. +// If no v1 files are used, its support can be disabled for space +// optimization. +// Default: 0 +#define SL_PSA_ITS_SUPPORT_V1_DRIVER 0 + +// Enable V2 ITS Driver Support <0-1> +// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys +// (or other files) stored using different address range. Enabling this +// config option adds upgrade code which converts V2 (and V1 if +// supported) format ITS keys/files to the latest V3 format. Update is +// fully automatic, needs to be run once and require extra flash space of +// approximately the size of the largest key. +// V1 ITS driver support can be disabled if the device has never used ITS +// driver before in GSDK 4.1.x and earlier, or the keys has been already +// migrated. +// Default: 0 +#define SL_PSA_ITS_SUPPORT_V2_DRIVER 0 + +// Enable support for V3 ITS Driver <0-1> +// Devices that have used GSDK 4.1.x and earlier, and used ITS have the keys +// (or other files) stored using different address range. In rare case +// that those devices have full nvm3 and not enough space for the +// upgrade, (that requires an extra space to store largest key in memory +// twice), this config option can disable v3 driver and use v2 one. +// To upgrade the device, make space for the upgrade, and enable v3 driver again. +// +// WARNING: When using V3 driver, it is not possible to increase or decrease +// the value of SL_PSA_ITS_USER_MAX_FILES. If the change of +// SL_PSA_ITS_USER_MAX_FILES is required, ITS should be cleared and +// all files need to be stored again. +// Default: 1 +#define SL_PSA_ITS_SUPPORT_V3_DRIVER 1 + +// Built-in AES Key Mode of Operation +// CTR Mode +// CFB Mode +// OFB Mode +// ECB Mode +// CBC Mode (no padding) +// CBC Mode (PKCS#7 padding) +// PSA Crypto only allows one specific usage algorithm per built-in key ID. +// Default: PSA_ALG_CTR +#define SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG (PSA_ALG_CTR) + +#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG +// Built-in PUF Key Algorithm +// PBKDF2 (CMAC-AES-128-PRF) +// CMAC +// PSA Crypto only allows one specific usage algorithm per built-in key ID. +// It is recommended to only use the PUF key for deriving further key +// material. +// Default: PSA_ALG_PBKDF2_AES_CMAC_PRF_128 +#define SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG (PSA_ALG_PBKDF2_AES_CMAC_PRF_128) +#endif // SL_CRYPTOACC_BUILTIN_KEY_PUF_ALG + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Sub-files + +#if defined(SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE) + #include SLI_PSA_CONFIG_AUTOGEN_OVERRIDE_FILE +#else + #include "sli_psa_config_autogen.h" +#endif + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + #include "sli_psa_tfm_translation.h" +#endif + +#if SL_MBEDTLS_DRIVERS_ENABLED + #include "sli_psa_acceleration.h" +#endif + +#include "sli_psa_builtin_config_autogen.h" + +#endif // PSA_CRYPTO_CONFIG_H diff --git a/locator_ncp/config/sl_bluetooth_advertiser_config.h b/locator_ncp/config/sl_bluetooth_advertiser_config.h index da75929..451e9d0 100644 --- a/locator_ncp/config/sl_bluetooth_advertiser_config.h +++ b/locator_ncp/config/sl_bluetooth_advertiser_config.h @@ -1,45 +1,45 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Advertiser configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_ADVERTISER_CONFIG_H -#define SL_BT_ADVERTISER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Max number of advertising sets reserved for user <0-255> -// Default: 1 -// Define the number of advertising sets that the application needs to use concurrently. Note that all types of advertising uses the same pool of advertising sets, but periodic advertising has extra configuration to define the number of advertising sets that are capable of periodic advertising. -// -// Specifically, if the component "bluetooth_feature_periodic_advertiser" is used, its configuration SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS specifies how many of the SL_BT_CONFIG_USER_ADVERTISERS advertising sets are capable of periodic advertising. Similarly, if the component bluetooth_feature_pawr_advertiser is used, its configuration SL_BT_CONFIG_MAX_PAWR_ADVERTISERS specifies how many of the periodic advertising sets are capable of Periodic Advertising with Responses. -// -// The configuration values must satisfy the condition SL_BT_CONFIG_USER_ADVERTISERS >= SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS >= SL_BT_CONFIG_MAX_PAWR_ADVERTISERS. -#define SL_BT_CONFIG_USER_ADVERTISERS 4 -// <<< end of configuration section >>> - -#endif +/***************************************************************************//** + * @file + * @brief Bluetooth Advertiser configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_ADVERTISER_CONFIG_H +#define SL_BT_ADVERTISER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Max number of advertising sets reserved for user <0-255> +// Default: 1 +// Define the number of advertising sets that the application needs to use concurrently. Note that all types of advertising uses the same pool of advertising sets, but periodic advertising has extra configuration to define the number of advertising sets that are capable of periodic advertising. +// +// Specifically, if the component "bluetooth_feature_periodic_advertiser" is used, its configuration SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS specifies how many of the SL_BT_CONFIG_USER_ADVERTISERS advertising sets are capable of periodic advertising. Similarly, if the component bluetooth_feature_pawr_advertiser is used, its configuration SL_BT_CONFIG_MAX_PAWR_ADVERTISERS specifies how many of the periodic advertising sets are capable of Periodic Advertising with Responses. +// +// The configuration values must satisfy the condition SL_BT_CONFIG_USER_ADVERTISERS >= SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS >= SL_BT_CONFIG_MAX_PAWR_ADVERTISERS. +#define SL_BT_CONFIG_USER_ADVERTISERS 4 +// <<< end of configuration section >>> + +#endif diff --git a/locator_ncp/config/sl_bluetooth_config.h b/locator_ncp/config/sl_bluetooth_config.h index 9be5570..b992508 100644 --- a/locator_ncp/config/sl_bluetooth_config.h +++ b/locator_ncp/config/sl_bluetooth_config.h @@ -1,161 +1,161 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Stack configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BLUETOOTH_CONFIG_H -#define SL_BLUETOOTH_CONFIG_H -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -// <<< Use Configuration Wizard in Context Menu >>> - -// Bluetooth Stack Configuration - -#ifdef SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT -#include "sl_bluetooth_connection_config.h" -#else -#define SL_BT_CONFIG_MAX_CONNECTIONS (0) -#endif - -// Max number of connections reserved by user application and components -#define SL_BT_CONFIG_MAX_CONNECTIONS_SUM (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS) - -#ifdef SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT -#include "sl_bluetooth_advertiser_config.h" -#else -#define SL_BT_CONFIG_USER_ADVERTISERS 4 -#endif - -#define SL_BT_CONFIG_MAX_ADVERTISERS (SL_BT_CONFIG_USER_ADVERTISERS + SL_BT_COMPONENT_ADVERTISERS) - -// Max number of software timers <0-16> -// Default: 4 -// Define the number of software timers the application needs. Each timer needs resources from the stack to be implemented. Increasing amount of soft timers may cause degraded performance in some use cases. -#define SL_BT_CONFIG_MAX_SOFTWARE_TIMERS (4) - -// Buffer memory size for Bluetooth stack -// Default: 3150 -// Define buffer memory size for running Bluetooth stack and buffering data over Bluetooth connections, -// advertising and scanning. The default value is an estimation for achieving adequate throughput -// and supporting multiple simultaneous connections. Consider increasing this value for -// higher data throughput over connections, advertising or scanning long advertisement data. -#define SL_BT_CONFIG_BUFFER_SIZE (3150) - -// End Bluetooth Stack Configuration - -// TX Power Levels - -// Minimum radiated TX power level in 0.1dBm unit -// Default: -30 (-3 dBm) -// Configure the minimum radiated TX power level for Bluetooth connections and DTM testing. -// This configuration is used for power control on Bluetooth connections -// if the LE Power Control feature is enabled. -// When this configuration is passed into stack initialization, the stack -// will select the closest value that the device supports. -// API sl_bt_system_get_tx_power_setting() can be used to query the selected value. -#define SL_BT_CONFIG_MIN_TX_POWER (-30) - -// Maximum radiated TX power level in 0.1dBm unit -// Default: 80 (8 dBm) -// Configure the maximum radiated TX power level for Bluetooth connections, -// advertising, scanning and DTM testing. -// When this configuration is passed into stack initialization, the stack -// will select the closest value that the device supports. -// API sl_bt_system_get_tx_power_setting() can be used to query the selected value. -#define SL_BT_CONFIG_MAX_TX_POWER (80) - -// End TX Power Levels - -// RF Path - -// RF TX path gain in 0.1dBm unit -// Default: 0 -// The Bluetooth stack takes TX RF path gain into account when adjusting transmitter -// output power. Power radiated from the antenna then matches the application request. -// A negative value indicates some power loss in the path. For example, -// with radiated TX power set to +10 dBm and this configuration to -10 -// (i.e., 1 dBm loss), the transmitter output power will be set to +11 dBm. -#define SL_BT_CONFIG_RF_PATH_GAIN_TX (0) - -// RF RX path gain in 0.1dBm unit -// Default: 0 -// RX RF path gain is used to compensate the RSSI reports from the Bluetooth Stack. -#define SL_BT_CONFIG_RF_PATH_GAIN_RX (0) - -// End RF Path - -// <<< end of configuration section >>> - -/** - * By default, Bluetooth requires accurate LF clock for EM2. If the component - * catalog presents, an inaccurate LF clock for EM2 can be used if the Bluetooth - * connection, periodic advertising and periodic advertising synchronization - * features are known to not present. - */ -#define BT_EM2_LFCLK_REQ_FLAG 0 - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#if !defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) - #undef BT_EM2_LFCLK_REQ_FLAG - #define BT_EM2_LFCLK_REQ_FLAG SL_BT_CONFIG_FLAG_INACCURATE_LFCLK_EM2 -#endif -#endif // SL_COMPONENT_CATALOG_PRESENT - -#ifdef SL_CATALOG_KERNEL_PRESENT -void sli_bt_rtos_ll_callback(); -void sli_bt_rtos_stack_callback(); - #define SL_BT_CONFIG_FLAGS (SL_BT_CONFIG_FLAG_RTOS | BT_EM2_LFCLK_REQ_FLAG) - #define SL_BT_CONFIG_LL_CALLBACK sli_bt_rtos_ll_callback - #define SL_BT_CONFIG_STACK_CALLBACK sli_bt_rtos_stack_callback -#else - #define SL_BT_CONFIG_FLAGS (BT_EM2_LFCLK_REQ_FLAG) - #define SL_BT_CONFIG_LL_CALLBACK 0 - #define SL_BT_CONFIG_STACK_CALLBACK 0 -#endif // SL_CATALOG_KERNEL_PRESENT - -#include "sl_bt_stack_config.h" - -#define SL_BT_CONFIG_DEFAULT \ - { \ - .config_flags = SL_BT_CONFIG_FLAGS, \ - .bluetooth.max_buffer_memory = SL_BT_CONFIG_BUFFER_SIZE, \ - .scheduler_callback = SL_BT_CONFIG_LL_CALLBACK, \ - .stack_schedule_callback = SL_BT_CONFIG_STACK_CALLBACK, \ - .gattdb = &gattdb, \ - .max_timers = SL_BT_CONFIG_MAX_SOFTWARE_TIMERS, \ - .rf.tx_gain = SL_BT_CONFIG_RF_PATH_GAIN_TX, \ - .rf.rx_gain = SL_BT_CONFIG_RF_PATH_GAIN_RX, \ - .rf.tx_min_power = SL_BT_CONFIG_MIN_TX_POWER, \ - .rf.tx_max_power = SL_BT_CONFIG_MAX_TX_POWER, \ - } - -#endif // SL_BLUETOOTH_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Stack configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BLUETOOTH_CONFIG_H +#define SL_BLUETOOTH_CONFIG_H +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +// <<< Use Configuration Wizard in Context Menu >>> + +// Bluetooth Stack Configuration + +#ifdef SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT +#include "sl_bluetooth_connection_config.h" +#else +#define SL_BT_CONFIG_MAX_CONNECTIONS (0) +#endif + +// Max number of connections reserved by user application and components +#define SL_BT_CONFIG_MAX_CONNECTIONS_SUM (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS) + +#ifdef SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT +#include "sl_bluetooth_advertiser_config.h" +#else +#define SL_BT_CONFIG_USER_ADVERTISERS 4 +#endif + +#define SL_BT_CONFIG_MAX_ADVERTISERS (SL_BT_CONFIG_USER_ADVERTISERS + SL_BT_COMPONENT_ADVERTISERS) + +// Max number of software timers <0-16> +// Default: 4 +// Define the number of software timers the application needs. Each timer needs resources from the stack to be implemented. Increasing amount of soft timers may cause degraded performance in some use cases. +#define SL_BT_CONFIG_MAX_SOFTWARE_TIMERS (4) + +// Buffer memory size for Bluetooth stack +// Default: 3150 +// Define buffer memory size for running Bluetooth stack and buffering data over Bluetooth connections, +// advertising and scanning. The default value is an estimation for achieving adequate throughput +// and supporting multiple simultaneous connections. Consider increasing this value for +// higher data throughput over connections, advertising or scanning long advertisement data. +#define SL_BT_CONFIG_BUFFER_SIZE (3150) + +// End Bluetooth Stack Configuration + +// TX Power Levels + +// Minimum radiated TX power level in 0.1dBm unit +// Default: -30 (-3 dBm) +// Configure the minimum radiated TX power level for Bluetooth connections and DTM testing. +// This configuration is used for power control on Bluetooth connections +// if the LE Power Control feature is enabled. +// When this configuration is passed into stack initialization, the stack +// will select the closest value that the device supports. +// API sl_bt_system_get_tx_power_setting() can be used to query the selected value. +#define SL_BT_CONFIG_MIN_TX_POWER (-30) + +// Maximum radiated TX power level in 0.1dBm unit +// Default: 80 (8 dBm) +// Configure the maximum radiated TX power level for Bluetooth connections, +// advertising, scanning and DTM testing. +// When this configuration is passed into stack initialization, the stack +// will select the closest value that the device supports. +// API sl_bt_system_get_tx_power_setting() can be used to query the selected value. +#define SL_BT_CONFIG_MAX_TX_POWER (80) + +// End TX Power Levels + +// RF Path + +// RF TX path gain in 0.1dBm unit +// Default: 0 +// The Bluetooth stack takes TX RF path gain into account when adjusting transmitter +// output power. Power radiated from the antenna then matches the application request. +// A negative value indicates some power loss in the path. For example, +// with radiated TX power set to +10 dBm and this configuration to -10 +// (i.e., 1 dBm loss), the transmitter output power will be set to +11 dBm. +#define SL_BT_CONFIG_RF_PATH_GAIN_TX (0) + +// RF RX path gain in 0.1dBm unit +// Default: 0 +// RX RF path gain is used to compensate the RSSI reports from the Bluetooth Stack. +#define SL_BT_CONFIG_RF_PATH_GAIN_RX (0) + +// End RF Path + +// <<< end of configuration section >>> + +/** + * By default, Bluetooth requires accurate LF clock for EM2. If the component + * catalog presents, an inaccurate LF clock for EM2 can be used if the Bluetooth + * connection, periodic advertising and periodic advertising synchronization + * features are known to not present. + */ +#define BT_EM2_LFCLK_REQ_FLAG 0 + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#if !defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) + #undef BT_EM2_LFCLK_REQ_FLAG + #define BT_EM2_LFCLK_REQ_FLAG SL_BT_CONFIG_FLAG_INACCURATE_LFCLK_EM2 +#endif +#endif // SL_COMPONENT_CATALOG_PRESENT + +#ifdef SL_CATALOG_KERNEL_PRESENT +void sli_bt_rtos_ll_callback(); +void sli_bt_rtos_stack_callback(); + #define SL_BT_CONFIG_FLAGS (SL_BT_CONFIG_FLAG_RTOS | BT_EM2_LFCLK_REQ_FLAG) + #define SL_BT_CONFIG_LL_CALLBACK sli_bt_rtos_ll_callback + #define SL_BT_CONFIG_STACK_CALLBACK sli_bt_rtos_stack_callback +#else + #define SL_BT_CONFIG_FLAGS (BT_EM2_LFCLK_REQ_FLAG) + #define SL_BT_CONFIG_LL_CALLBACK 0 + #define SL_BT_CONFIG_STACK_CALLBACK 0 +#endif // SL_CATALOG_KERNEL_PRESENT + +#include "sl_bt_stack_config.h" + +#define SL_BT_CONFIG_DEFAULT \ + { \ + .config_flags = SL_BT_CONFIG_FLAGS, \ + .bluetooth.max_buffer_memory = SL_BT_CONFIG_BUFFER_SIZE, \ + .scheduler_callback = SL_BT_CONFIG_LL_CALLBACK, \ + .stack_schedule_callback = SL_BT_CONFIG_STACK_CALLBACK, \ + .gattdb = &gattdb, \ + .max_timers = SL_BT_CONFIG_MAX_SOFTWARE_TIMERS, \ + .rf.tx_gain = SL_BT_CONFIG_RF_PATH_GAIN_TX, \ + .rf.rx_gain = SL_BT_CONFIG_RF_PATH_GAIN_RX, \ + .rf.tx_min_power = SL_BT_CONFIG_MIN_TX_POWER, \ + .rf.tx_max_power = SL_BT_CONFIG_MAX_TX_POWER, \ + } + +#endif // SL_BLUETOOTH_CONFIG_H diff --git a/locator_ncp/config/sl_bluetooth_connection_config.h b/locator_ncp/config/sl_bluetooth_connection_config.h index 73a3825..5093b88 100644 --- a/locator_ncp/config/sl_bluetooth_connection_config.h +++ b/locator_ncp/config/sl_bluetooth_connection_config.h @@ -1,48 +1,48 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Connection configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_CONNECTION_CONFIG_H -#define SL_BT_CONNECTION_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Max number of connections reserved for user <0-32> -// Default: 4 -// Define the number of connections the application needs. -#define SL_BT_CONFIG_MAX_CONNECTIONS (4) - -// Preferred maximum TX payload octets <27-251> -// Default: 251 -// Define the preferred maximum TX payload octets that will be used on connections. -// This value is set to the controller as the default suggested data length when -// Bluetooth stack is started. -#define SL_BT_CONFIG_CONNECTION_DATA_LENGTH (251) - -// <<< end of configuration section >>> -#endif +/***************************************************************************//** + * @file + * @brief Bluetooth Connection configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_CONNECTION_CONFIG_H +#define SL_BT_CONNECTION_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Max number of connections reserved for user <0-32> +// Default: 4 +// Define the number of connections the application needs. +#define SL_BT_CONFIG_MAX_CONNECTIONS (4) + +// Preferred maximum TX payload octets <27-251> +// Default: 251 +// Define the preferred maximum TX payload octets that will be used on connections. +// This value is set to the controller as the default suggested data length when +// Bluetooth stack is started. +#define SL_BT_CONFIG_CONNECTION_DATA_LENGTH (251) + +// <<< end of configuration section >>> +#endif diff --git a/locator_ncp/config/sl_bluetooth_periodic_sync_config.h b/locator_ncp/config/sl_bluetooth_periodic_sync_config.h index 6fac03a..aaf723c 100644 --- a/locator_ncp/config/sl_bluetooth_periodic_sync_config.h +++ b/locator_ncp/config/sl_bluetooth_periodic_sync_config.h @@ -1,41 +1,41 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Periodic Advertising Synchronizer configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_PERIODIC_SYNC_CONFIG_H -#define SL_BT_PERIODIC_SYNC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Max number of periodic advertising synchronizations <0-255> -// Default: 1 -// Define the number of periodic advertising synchronizations the application needs. -#define SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC 8 -// <<< end of configuration section >>> - -#endif +/***************************************************************************//** + * @file + * @brief Bluetooth Periodic Advertising Synchronizer configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_PERIODIC_SYNC_CONFIG_H +#define SL_BT_PERIODIC_SYNC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Max number of periodic advertising synchronizations <0-255> +// Default: 1 +// Define the number of periodic advertising synchronizations the application needs. +#define SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC 8 +// <<< end of configuration section >>> + +#endif diff --git a/locator_ncp/config/sl_board_control_config.h b/locator_ncp/config/sl_board_control_config.h index 12e66a4..86b65c7 100644 --- a/locator_ncp/config/sl_board_control_config.h +++ b/locator_ncp/config/sl_board_control_config.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief Board Control - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BOARD_CONTROL_CONFIG_H -#define SL_BOARD_CONTROL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable Virtual COM UART -// Default: 0 -#define SL_BOARD_ENABLE_VCOM 0 - -// Enable Display -// Default: 0 -#define SL_BOARD_ENABLE_DISPLAY 0 - -// Disable SPI Flash -// Default: 1 -#define SL_BOARD_DISABLE_MEMORY_SPI 1 - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// SL_BOARD_ENABLE_VCOM -// $[GPIO_SL_BOARD_ENABLE_VCOM] -#ifndef SL_BOARD_ENABLE_VCOM_PORT -#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB -#endif -#ifndef SL_BOARD_ENABLE_VCOM_PIN -#define SL_BOARD_ENABLE_VCOM_PIN 4 -#endif -// [GPIO_SL_BOARD_ENABLE_VCOM]$ - -// SL_BOARD_ENABLE_DISPLAY -// $[GPIO_SL_BOARD_ENABLE_DISPLAY] -#ifndef SL_BOARD_ENABLE_DISPLAY_PORT -#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortB -#endif -#ifndef SL_BOARD_ENABLE_DISPLAY_PIN -#define SL_BOARD_ENABLE_DISPLAY_PIN 4 -#endif -// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_BOARD_CONTROL_CONFIG_H +/***************************************************************************//** + * @file + * @brief Board Control + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BOARD_CONTROL_CONFIG_H +#define SL_BOARD_CONTROL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable Virtual COM UART +// Default: 0 +#define SL_BOARD_ENABLE_VCOM 0 + +// Enable Display +// Default: 0 +#define SL_BOARD_ENABLE_DISPLAY 0 + +// Disable SPI Flash +// Default: 1 +#define SL_BOARD_DISABLE_MEMORY_SPI 1 + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// SL_BOARD_ENABLE_VCOM +// $[GPIO_SL_BOARD_ENABLE_VCOM] +#ifndef SL_BOARD_ENABLE_VCOM_PORT +#define SL_BOARD_ENABLE_VCOM_PORT gpioPortB +#endif +#ifndef SL_BOARD_ENABLE_VCOM_PIN +#define SL_BOARD_ENABLE_VCOM_PIN 4 +#endif +// [GPIO_SL_BOARD_ENABLE_VCOM]$ + +// SL_BOARD_ENABLE_DISPLAY +// $[GPIO_SL_BOARD_ENABLE_DISPLAY] +#ifndef SL_BOARD_ENABLE_DISPLAY_PORT +#define SL_BOARD_ENABLE_DISPLAY_PORT gpioPortB +#endif +#ifndef SL_BOARD_ENABLE_DISPLAY_PIN +#define SL_BOARD_ENABLE_DISPLAY_PIN 4 +#endif +// [GPIO_SL_BOARD_ENABLE_DISPLAY]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_BOARD_CONTROL_CONFIG_H diff --git a/locator_ncp/config/sl_bt_dynamic_gattdb_config.h b/locator_ncp/config/sl_bt_dynamic_gattdb_config.h index 2ba4b5b..5368695 100644 --- a/locator_ncp/config/sl_bt_dynamic_gattdb_config.h +++ b/locator_ncp/config/sl_bt_dynamic_gattdb_config.h @@ -1,92 +1,92 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Dynamic GATT Database configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_DYNAMIC_GATTDB_CONFIG_H -#define SL_BT_DYNAMIC_GATTDB_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Bluetooth Dynamic GATT Configuration - -// Static GATT database configuration -// Default: 1 (Enabled) -// -// Configures whether a static GATT database, which is generated from a -// GATT XML file, should be included. When included, services and -// characteristics created dynamically are appended into the attribute -// table after the static attributes. -// -// Values: -// * 1: Include the static GATT database. -// * 0: Do not include the static GATT database. -// -#define SL_BT_GATTDB_INCLUDE_STATIC_DATABASE (1) - -// GATT Caching support configuration -// Default: 1 (Enabled) -// -// Configures whether the database should support GATT caching. When enabled, -// a Generic Attribute Profile Service will be created in the beginning of -// the database, and the GATT server will handle service-changed indications -// and robust caching with remote GATT clients automatically. -// -// Note that this configuration does not apply when a static database -// is included. GATT caching support configuration must come from the -// static database in this case. -// -// There could be cases that the database does not enable the GATT caching -// feature while one or more GATT clients are connected, or the feature is -// enabled but a connected remote GATT client does not enable GATT caching -// (by enabling service-changed indications or indicating that it supports -// robust caching). In these cases, the user application should not update -// the database. Otherwise a GATT client and local GATT server become out -// of sync, and there is no means for the GATT client to realize this -// situation. -// -// Values: -// * 1: Enable GATT Caching. -// * 0: Disable GATT Caching. -// -#define SL_BT_GATTDB_ENABLE_GATT_CACHING (1) - -// End Bluetooth Dynamic GATT Configuration - -// <<< end of configuration section >>> - -/** - * @brief Configure the Bluetooth Dynamic GATT feature. - * - * This function is automatically called by code generated by the Universal - * Configurator if the feature is included in the project. The application is - * not expected to call this function directly. - */ -sl_status_t sl_bt_dynamic_gattdb_configure(); - -#endif // SL_BT_DYNAMIC_GATTDB_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Dynamic GATT Database configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_DYNAMIC_GATTDB_CONFIG_H +#define SL_BT_DYNAMIC_GATTDB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Bluetooth Dynamic GATT Configuration + +// Static GATT database configuration +// Default: 1 (Enabled) +// +// Configures whether a static GATT database, which is generated from a +// GATT XML file, should be included. When included, services and +// characteristics created dynamically are appended into the attribute +// table after the static attributes. +// +// Values: +// * 1: Include the static GATT database. +// * 0: Do not include the static GATT database. +// +#define SL_BT_GATTDB_INCLUDE_STATIC_DATABASE (1) + +// GATT Caching support configuration +// Default: 1 (Enabled) +// +// Configures whether the database should support GATT caching. When enabled, +// a Generic Attribute Profile Service will be created in the beginning of +// the database, and the GATT server will handle service-changed indications +// and robust caching with remote GATT clients automatically. +// +// Note that this configuration does not apply when a static database +// is included. GATT caching support configuration must come from the +// static database in this case. +// +// There could be cases that the database does not enable the GATT caching +// feature while one or more GATT clients are connected, or the feature is +// enabled but a connected remote GATT client does not enable GATT caching +// (by enabling service-changed indications or indicating that it supports +// robust caching). In these cases, the user application should not update +// the database. Otherwise a GATT client and local GATT server become out +// of sync, and there is no means for the GATT client to realize this +// situation. +// +// Values: +// * 1: Enable GATT Caching. +// * 0: Disable GATT Caching. +// +#define SL_BT_GATTDB_ENABLE_GATT_CACHING (1) + +// End Bluetooth Dynamic GATT Configuration + +// <<< end of configuration section >>> + +/** + * @brief Configure the Bluetooth Dynamic GATT feature. + * + * This function is automatically called by code generated by the Universal + * Configurator if the feature is included in the project. The application is + * not expected to call this function directly. + */ +sl_status_t sl_bt_dynamic_gattdb_configure(); + +#endif // SL_BT_DYNAMIC_GATTDB_CONFIG_H diff --git a/locator_ncp/config/sl_bt_periodic_advertiser_config.h b/locator_ncp/config/sl_bt_periodic_advertiser_config.h index cb57aa2..f59be61 100644 --- a/locator_ncp/config/sl_bt_periodic_advertiser_config.h +++ b/locator_ncp/config/sl_bt_periodic_advertiser_config.h @@ -1,47 +1,47 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Periodic Advertiser configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from the - * use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in a - * product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_PERIODIC_ADVERTISER_CONFIG_H -#define SL_BT_PERIODIC_ADVERTISER_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Bluetooth Periodic Advertiser Configuration - -// Max number of advertising sets that support periodic advertising <0-255> -// Default: 1 -// Define the number of periodic advertising sets that the application needs to use concurrently. This number must not exceed the total number of advertising sets configured by SL_BT_CONFIG_USER_ADVERTISERS in the component "bluetooth_feature_advertiser". -#define SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS (1) - -// End Bluetooth Periodic Advertiser Configuration - -// <<< end of configuration section >>> - -#endif // SL_BT_PERIODIC_ADVERTISER_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Periodic Advertiser configuration + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from the + * use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in a + * product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_PERIODIC_ADVERTISER_CONFIG_H +#define SL_BT_PERIODIC_ADVERTISER_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Bluetooth Periodic Advertiser Configuration + +// Max number of advertising sets that support periodic advertising <0-255> +// Default: 1 +// Define the number of periodic advertising sets that the application needs to use concurrently. This number must not exceed the total number of advertising sets configured by SL_BT_CONFIG_USER_ADVERTISERS in the component "bluetooth_feature_advertiser". +#define SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS (1) + +// End Bluetooth Periodic Advertiser Configuration + +// <<< end of configuration section >>> + +#endif // SL_BT_PERIODIC_ADVERTISER_CONFIG_H diff --git a/locator_ncp/config/sl_debug_swo_config.h b/locator_ncp/config/sl_debug_swo_config.h index 56c90a9..5e4aa49 100644 --- a/locator_ncp/config/sl_debug_swo_config.h +++ b/locator_ncp/config/sl_debug_swo_config.h @@ -1,106 +1,106 @@ -/***************************************************************************//** - * @file - * @brief SWO configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEBUG_SWO_CONFIG_H -#define SL_DEBUG_SWO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// SWO Configuration - -// SWO Frequency -// Must be 875 kHz for communication with Silicon Labs debuggers -// Default: 875000 -#define SL_DEBUG_SWO_FREQ 875000 - -// Enable interrupt event trace -// Default: 0 -#define SL_DEBUG_SWO_SAMPLE_IRQ 0 - -// Enable Program Counter samples -// Default: 0 -#define SL_DEBUG_SWO_SAMPLE_PC 0 - -// SWO debug sample intervals -// <64=> 64 -// <128=> 128 -// <192=> 192 -// <256=> 256 -// <320=> 320 -// <384=> 384 -// <448=> 448 -// <512=> 512 -// <576=> 576 -// <640=> 640 -// <704=> 704 -// <768=> 768 -// <832=> 832 -// <896=> 896 -// <960=> 960 -// <1024=> 1024 -// <2048=> 2048 -// <3072=> 3072 -// <4096=> 4096 -// <5102=> 5102 -// <6144=> 6144 -// <7168=> 7168 -// <8192=> 8192 -// <9216=> 9216 -// <10240=> 10240 -// <11264=> 11264 -// <12288=> 12288 -// <13312=> 13312 -// <14336=> 14336 -// <15360=> 15360 -// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 -// Default: 15360 -#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 -// - -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_DEBUG -// $[GPIO_SL_DEBUG] -#ifndef SL_DEBUG_PERIPHERAL -#define SL_DEBUG_PERIPHERAL GPIO -#endif - -// GPIO SWV on PA03 -#ifndef SL_DEBUG_SWV_PORT -#define SL_DEBUG_SWV_PORT gpioPortA -#endif -#ifndef SL_DEBUG_SWV_PIN -#define SL_DEBUG_SWV_PIN 3 -#endif -// [GPIO_SL_DEBUG]$ -// <<< sl:end pin_tool >>> - -#endif // SL_DEBUG_SWO_CONFIG_H +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEBUG_SWO_CONFIG_H +#define SL_DEBUG_SWO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO Configuration + +// SWO Frequency +// Must be 875 kHz for communication with Silicon Labs debuggers +// Default: 875000 +#define SL_DEBUG_SWO_FREQ 875000 + +// Enable interrupt event trace +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_IRQ 0 + +// Enable Program Counter samples +// Default: 0 +#define SL_DEBUG_SWO_SAMPLE_PC 0 + +// SWO debug sample intervals +// <64=> 64 +// <128=> 128 +// <192=> 192 +// <256=> 256 +// <320=> 320 +// <384=> 384 +// <448=> 448 +// <512=> 512 +// <576=> 576 +// <640=> 640 +// <704=> 704 +// <768=> 768 +// <832=> 832 +// <896=> 896 +// <960=> 960 +// <1024=> 1024 +// <2048=> 2048 +// <3072=> 3072 +// <4096=> 4096 +// <5102=> 5102 +// <6144=> 6144 +// <7168=> 7168 +// <8192=> 8192 +// <9216=> 9216 +// <10240=> 10240 +// <11264=> 11264 +// <12288=> 12288 +// <13312=> 13312 +// <14336=> 14336 +// <15360=> 15360 +// Must be 64, 128, 192, [ n * 64 ], 1024, 2048, 3072, [ n * 1024 ] , 15360 +// Default: 15360 +#define SL_DEBUG_SWO_SAMPLE_INTERVAL 15360 +// + +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEBUG +// $[GPIO_SL_DEBUG] +#ifndef SL_DEBUG_PERIPHERAL +#define SL_DEBUG_PERIPHERAL GPIO +#endif + +// GPIO SWV on PA03 +#ifndef SL_DEBUG_SWV_PORT +#define SL_DEBUG_SWV_PORT gpioPortA +#endif +#ifndef SL_DEBUG_SWV_PIN +#define SL_DEBUG_SWV_PIN 3 +#endif +// [GPIO_SL_DEBUG]$ +// <<< sl:end pin_tool >>> + +#endif // SL_DEBUG_SWO_CONFIG_H diff --git a/locator_ncp/config/sl_device_init_dcdc_config.h b/locator_ncp/config/sl_device_init_dcdc_config.h index 734aed3..518e689 100644 --- a/locator_ncp/config/sl_device_init_dcdc_config.h +++ b/locator_ncp/config/sl_device_init_dcdc_config.h @@ -1,58 +1,58 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_DCDC Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H -#define SL_DEVICE_INIT_DCDC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Enable DC/DC Converter -// -// Default: 1 -#define SL_DEVICE_INIT_DCDC_ENABLE 1 - -// Set DC/DC Converter in Bypass Mode -// -// Default: 0 -#define SL_DEVICE_INIT_DCDC_BYPASS 0 - -// Override for DCDC PFMX Mode Peak Current Setting -// -// Default: 0 -#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 0 - -// DCDC PFMX Mode Peak Current Setting <0-15> -// -// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT -#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL DCDC_PFMXCTRL_IPKVAL_DEFAULT - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_DCDC_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_DCDC Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_DCDC_CONFIG_H +#define SL_DEVICE_INIT_DCDC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Enable DC/DC Converter +// +// Default: 1 +#define SL_DEVICE_INIT_DCDC_ENABLE 1 + +// Set DC/DC Converter in Bypass Mode +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_BYPASS 0 + +// Override for DCDC PFMX Mode Peak Current Setting +// +// Default: 0 +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE 0 + +// DCDC PFMX Mode Peak Current Setting <0-15> +// +// Default: DCDC_PFMXCTRL_IPKVAL_DEFAULT +#define SL_DEVICE_INIT_DCDC_PFMX_IPKVAL DCDC_PFMXCTRL_IPKVAL_DEFAULT + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_DCDC_CONFIG_H diff --git a/locator_ncp/config/sl_device_init_emu_config.h b/locator_ncp/config/sl_device_init_emu_config.h index 4ac96ba..dc9cedc 100644 --- a/locator_ncp/config/sl_device_init_emu_config.h +++ b/locator_ncp/config/sl_device_init_emu_config.h @@ -1,53 +1,53 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_EMU Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_EMU_CONFIG_H -#define SL_DEVICE_INIT_EMU_CONFIG_H - -#include "em_emu.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// Allow debugger to remain connected in EM2 -// Force PD0B to stay on on EM2 entry. This allows the debugger to remain connected in EM2 and EM3. -// Enabling debug connectivity results in an increased power consumption in EM2/EM3. -// Default: 1 -#define SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE 1 - -// EM4 pin retention mode -// No Retention: Pads enter reset state when entering EM4. -// Retention through EM4: Pads enter reset state when exiting EM4. -// Retention through EM4 and wakeup. -// Default: emuPinRetentionDisable -#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_EMU_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_EMU Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_EMU_CONFIG_H +#define SL_DEVICE_INIT_EMU_CONFIG_H + +#include "em_emu.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// Allow debugger to remain connected in EM2 +// Force PD0B to stay on on EM2 entry. This allows the debugger to remain connected in EM2 and EM3. +// Enabling debug connectivity results in an increased power consumption in EM2/EM3. +// Default: 1 +#define SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE 1 + +// EM4 pin retention mode +// No Retention: Pads enter reset state when entering EM4. +// Retention through EM4: Pads enter reset state when exiting EM4. +// Retention through EM4 and wakeup. +// Default: emuPinRetentionDisable +#define SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE emuPinRetentionDisable + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_EMU_CONFIG_H diff --git a/locator_ncp/config/sl_device_init_hfxo_config.h b/locator_ncp/config/sl_device_init_hfxo_config.h index 9d29c79..aea0d21 100644 --- a/locator_ncp/config/sl_device_init_hfxo_config.h +++ b/locator_ncp/config/sl_device_init_hfxo_config.h @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_HFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H -#define SL_DEVICE_INIT_HFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// External sine wave -// Default: cmuHfxoOscMode_Crystal -#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal - -// Frequency <38000000-40000000> -// Default: 38400000 -#define SL_DEVICE_INIT_HFXO_FREQ 38400000 - -// HFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_HFXO_PRECISION 50 - -// CTUNE <0-255> -// Default: 140 -#define SL_DEVICE_INIT_HFXO_CTUNE 120 - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_HFXO_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_HFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_HFXO_CONFIG_H +#define SL_DEVICE_INIT_HFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// External sine wave +// Default: cmuHfxoOscMode_Crystal +#define SL_DEVICE_INIT_HFXO_MODE cmuHfxoOscMode_Crystal + +// Frequency <38000000-40000000> +// Default: 38400000 +#define SL_DEVICE_INIT_HFXO_FREQ 38400000 + +// HFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_HFXO_PRECISION 50 + +// CTUNE <0-255> +// Default: 140 +#define SL_DEVICE_INIT_HFXO_CTUNE 120 + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_HFXO_CONFIG_H diff --git a/locator_ncp/config/sl_device_init_lfrco_config.h b/locator_ncp/config/sl_device_init_lfrco_config.h index 2783103..fec168e 100644 --- a/locator_ncp/config/sl_device_init_lfrco_config.h +++ b/locator_ncp/config/sl_device_init_lfrco_config.h @@ -1,53 +1,53 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFRCO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H -#define SL_DEVICE_INIT_LFRCO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Precision Mode -// Precision mode uses hardware to automatically re-calibrate the LFRCO -// against a crystal driven by the HFXO. Hardware detects temperature -// changes and initiates a re-calibration of the LFRCO as needed when -// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the -// HFXO is not active, the precision mode hardware will automatically -// enable HFXO for a short time to perform the calibration. EM4 operation is -// not allowed while precision mode is enabled. -// If high precision is selected on devices that do not support it, default -// precision will be used. -// Default precision -// High precision -// Default: cmuPrecisionHigh -#define SL_DEVICE_INIT_LFRCO_PRECISION cmuPrecisionHigh - -// <<< end of configuration section >>> - -#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFRCO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFRCO_CONFIG_H +#define SL_DEVICE_INIT_LFRCO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Precision Mode +// Precision mode uses hardware to automatically re-calibrate the LFRCO +// against a crystal driven by the HFXO. Hardware detects temperature +// changes and initiates a re-calibration of the LFRCO as needed when +// operating in EM0, EM1, or EM2. If a re-calibration is necessary and the +// HFXO is not active, the precision mode hardware will automatically +// enable HFXO for a short time to perform the calibration. EM4 operation is +// not allowed while precision mode is enabled. +// If high precision is selected on devices that do not support it, default +// precision will be used. +// Default precision +// High precision +// Default: cmuPrecisionHigh +#define SL_DEVICE_INIT_LFRCO_PRECISION cmuPrecisionHigh + +// <<< end of configuration section >>> + +#endif // SL_DEVICE_INIT_LFRCO_CONFIG_H diff --git a/locator_ncp/config/sl_device_init_lfxo_config.h b/locator_ncp/config/sl_device_init_lfxo_config.h index a3fc0aa..8f03092 100644 --- a/locator_ncp/config/sl_device_init_lfxo_config.h +++ b/locator_ncp/config/sl_device_init_lfxo_config.h @@ -1,93 +1,93 @@ -/***************************************************************************//** - * @file - * @brief DEVICE_INIT_LFXO Config - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H -#define SL_DEVICE_INIT_LFXO_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Mode -// -// Crystal oscillator -// AC-coupled buffer -// External digital clock -// Default: cmuLfxoOscMode_Crystal -#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal - -// CTUNE <0-127> -// Default: 63 -#define SL_DEVICE_INIT_LFXO_CTUNE 37 - -// LFXO precision in PPM <0-65535> -// Default: 50 -#define SL_DEVICE_INIT_LFXO_PRECISION 50 - -// Startup Timeout Delay -// -// 2 cycles -// 256 cycles -// 1K cycles -// 2K cycles -// 4K cycles -// 8K cycles -// 16K cycles -// 32K cycles -// Default: cmuLfxoStartupDelay_4KCycles -#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_DEVICE_INIT_LFXO -// $[LFXO_SL_DEVICE_INIT_LFXO] -#ifndef SL_DEVICE_INIT_LFXO_PERIPHERAL -#define SL_DEVICE_INIT_LFXO_PERIPHERAL LFXO -#endif - -// LFXO LFXTAL_O on PD00 -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT -#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT gpioPortD -#endif -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN -#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN 0 -#endif - -// LFXO LFXTAL_I on PD01 -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT -#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT gpioPortD -#endif -#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN -#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN 1 -#endif - -// [LFXO_SL_DEVICE_INIT_LFXO]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_DEVICE_INIT_LFXO_CONFIG_H +/***************************************************************************//** + * @file + * @brief DEVICE_INIT_LFXO Config + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_DEVICE_INIT_LFXO_CONFIG_H +#define SL_DEVICE_INIT_LFXO_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Mode +// +// Crystal oscillator +// AC-coupled buffer +// External digital clock +// Default: cmuLfxoOscMode_Crystal +#define SL_DEVICE_INIT_LFXO_MODE cmuLfxoOscMode_Crystal + +// CTUNE <0-127> +// Default: 63 +#define SL_DEVICE_INIT_LFXO_CTUNE 37 + +// LFXO precision in PPM <0-65535> +// Default: 50 +#define SL_DEVICE_INIT_LFXO_PRECISION 50 + +// Startup Timeout Delay +// +// 2 cycles +// 256 cycles +// 1K cycles +// 2K cycles +// 4K cycles +// 8K cycles +// 16K cycles +// 32K cycles +// Default: cmuLfxoStartupDelay_4KCycles +#define SL_DEVICE_INIT_LFXO_TIMEOUT cmuLfxoStartupDelay_4KCycles +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_DEVICE_INIT_LFXO +// $[LFXO_SL_DEVICE_INIT_LFXO] +#ifndef SL_DEVICE_INIT_LFXO_PERIPHERAL +#define SL_DEVICE_INIT_LFXO_PERIPHERAL LFXO +#endif + +// LFXO LFXTAL_O on PD00 +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT +#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PORT gpioPortD +#endif +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN +#define SL_DEVICE_INIT_LFXO_LFXTAL_O_PIN 0 +#endif + +// LFXO LFXTAL_I on PD01 +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT +#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PORT gpioPortD +#endif +#ifndef SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN +#define SL_DEVICE_INIT_LFXO_LFXTAL_I_PIN 1 +#endif + +// [LFXO_SL_DEVICE_INIT_LFXO]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_DEVICE_INIT_LFXO_CONFIG_H diff --git a/locator_ncp/config/sl_mbedtls_config.h b/locator_ncp/config/sl_mbedtls_config.h index 39b5149..851aeef 100644 --- a/locator_ncp/config/sl_mbedtls_config.h +++ b/locator_ncp/config/sl_mbedtls_config.h @@ -1,118 +1,118 @@ -#ifndef SL_MBEDTLS_CONFIG_H -#define SL_MBEDTLS_CONFIG_H - -// ----------------------------------------------------------------------------- -// User exposed config options - -// <<< Use Configuration Wizard in Context Menu >>> - -// TLS/DTLS configuration - -// Complete list of ciphersuites to use, in order of preference. -// Default: MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 -// Complete list of ciphersuites to use, in order of preference. -// The value of this configuration should be updated for the application needs. -#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 - -// Maximum TLS/DTLS fragment length in bytes (input). -// Default: 768 -// The size configured here determines the size of the internal I/O -// buffer used in mbedTLS when receiving data. -#define SL_MBEDTLS_SSL_IN_CONTENT_LEN 768 - -// Maximum TLS/DTLS fragment length in bytes (output). -// Default: 768 -// The size configured here determines the size of the internal I/O -// buffer used in mbedTLS when sending data. -#define SL_MBEDTLS_SSL_OUT_CONTENT_LEN 768 - -// Enable support for RFC 6066 max_fragment_length extension in SSL. -// Default: 1 -// Enable support for RFC 6066 max_fragment_length extension in SSL. -#define SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1 - -// Enable support for exporting key block and master secret. -// Default: 1 -// Enable support for exporting key block and master secret. -// This is required for certain users of TLS, e.g. EAP-TLS. -#define SL_MBEDTLS_SSL_EXPORT_KEYS 1 - -// Enable the PSK based ciphersuite modes in SSL / TLS. -// Default: 0 -// Enable the PSK based ciphersuite modes in SSL / TLS. -#define SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED 0 - -// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. -// Default: 0 -// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. -#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED 0 - -// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. -// Default: 0 -// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. -#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED 0 - -// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. -// Default: 0 -// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. -#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED 0 - -// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. -// Default: 0 -// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. -#define SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED 0 - -// Enable parsing of the compressed curves. -// Default: 0 -// Enable parsing of the compressed curves. -#define SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING 0 - -// - -// RSA configuration - -// Disable use of the Chinese Remainder Theorem for RSA. -// Default: 0 -// Disable use of the Chinese Remainder Theorem for RSA private key -// computations. -#define SL_MBEDTLS_RSA_NO_CRT 0 - -// - -// Miscellaneous configuration - -// Enable Silicon Labs' Mbed TLS- and PSA Crypto drivers. -// Default: 1 -// Enable drivers for hardware acceleration (Mbed TLS and PSA Crypto) and -// secure key handling (PSA Crypto). -#define SL_MBEDTLS_DRIVERS_ENABLED 1 - -// - -// <<< end of configuration section >>> - -// ----------------------------------------------------------------------------- -// Sub-files - -#if defined(SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE) - #include SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE -#else - #include "sli_mbedtls_config_autogen.h" -#endif - -#include "sli_mbedtls_omnipresent.h" - -#if SL_MBEDTLS_DRIVERS_ENABLED - #include "sli_mbedtls_acceleration.h" -#endif - -#include "sl_mbedtls_device_config.h" - -// Include transformation logic to apply CMSIS-config configuration options to -// the correct Mbed TLS / PSA Crypto options. -#include "sli_mbedtls_config_transform_autogen.h" - -// Included for backward compatibility reasons. -#include "mbedtls/build_info.h" - -#endif // SL_MBEDTLS_CONFIG_H +#ifndef SL_MBEDTLS_CONFIG_H +#define SL_MBEDTLS_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// TLS/DTLS configuration + +// Complete list of ciphersuites to use, in order of preference. +// Default: MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 +// Complete list of ciphersuites to use, in order of preference. +// The value of this configuration should be updated for the application needs. +#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + +// Maximum TLS/DTLS fragment length in bytes (input). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when receiving data. +#define SL_MBEDTLS_SSL_IN_CONTENT_LEN 768 + +// Maximum TLS/DTLS fragment length in bytes (output). +// Default: 768 +// The size configured here determines the size of the internal I/O +// buffer used in mbedTLS when sending data. +#define SL_MBEDTLS_SSL_OUT_CONTENT_LEN 768 + +// Enable support for RFC 6066 max_fragment_length extension in SSL. +// Default: 1 +// Enable support for RFC 6066 max_fragment_length extension in SSL. +#define SL_MBEDTLS_SSL_MAX_FRAGMENT_LENGTH 1 + +// Enable support for exporting key block and master secret. +// Default: 1 +// Enable support for exporting key block and master secret. +// This is required for certain users of TLS, e.g. EAP-TLS. +#define SL_MBEDTLS_SSL_EXPORT_KEYS 1 + +// Enable the PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED 0 + +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED 0 + +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED 0 + +// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED 0 + +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +// Default: 0 +// Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. +#define SL_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED 0 + +// Enable parsing of the compressed curves. +// Default: 0 +// Enable parsing of the compressed curves. +#define SL_MBEDTLS_ECP_ENABLE_COMPRESSED_CURVE_PARSING 0 + +// + +// RSA configuration + +// Disable use of the Chinese Remainder Theorem for RSA. +// Default: 0 +// Disable use of the Chinese Remainder Theorem for RSA private key +// computations. +#define SL_MBEDTLS_RSA_NO_CRT 0 + +// + +// Miscellaneous configuration + +// Enable Silicon Labs' Mbed TLS- and PSA Crypto drivers. +// Default: 1 +// Enable drivers for hardware acceleration (Mbed TLS and PSA Crypto) and +// secure key handling (PSA Crypto). +#define SL_MBEDTLS_DRIVERS_ENABLED 1 + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Sub-files + +#if defined(SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE) + #include SLI_MBEDTLS_CONFIG_AUTOGEN_OVERRIDE_FILE +#else + #include "sli_mbedtls_config_autogen.h" +#endif + +#include "sli_mbedtls_omnipresent.h" + +#if SL_MBEDTLS_DRIVERS_ENABLED + #include "sli_mbedtls_acceleration.h" +#endif + +#include "sl_mbedtls_device_config.h" + +// Include transformation logic to apply CMSIS-config configuration options to +// the correct Mbed TLS / PSA Crypto options. +#include "sli_mbedtls_config_transform_autogen.h" + +// Included for backward compatibility reasons. +#include "mbedtls/build_info.h" + +#endif // SL_MBEDTLS_CONFIG_H diff --git a/locator_ncp/config/sl_mbedtls_device_config.h b/locator_ncp/config/sl_mbedtls_device_config.h index 33c34c4..dd943a6 100644 --- a/locator_ncp/config/sl_mbedtls_device_config.h +++ b/locator_ncp/config/sl_mbedtls_device_config.h @@ -1,72 +1,72 @@ -#ifndef SL_MBEDTLS_DEVICE_CONFIG_H -#define SL_MBEDTLS_DEVICE_CONFIG_H - -// ----------------------------------------------------------------------------- -// User exposed config options - -// <<< Use Configuration Wizard in Context Menu >>> - -// Secure Engine (SE) version configuration - -// Support SE firmware versions older than 1.2.2 <0-1> -// Enable software fallback for ECDH and ECC public key validation on xG21 -// devices running SE firmware versions lower than 1.2.2. -// -// Due to other stability concerns, it is strongly recommended to upgrade -// these devices to the latest firmware revision instead of turning on -// software fallback support. -// -// Not having fallback support will make ECDH operations, as well as PSA -// Crypto public key import, return an error code on affected devices. -// -// Default: 0 -#define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 0 - -// Assume an SE firmware version newer than 1.2.2 <0-1> -// For enhanced performance: if it is guaranteed that all devices on which -// this library will run are updated to at least SE FW 1.2.2, then turning -// on this option will remove certain fallback checks, thereby reducing the -// amount of processing required for ECDH and public key verification -// operations. -// Default: 0 -#define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 0 - -// Assume an SE firmware version that is unaffected by Ed25519 errata <0-1> -// For minimal code size and performance savings: if it is guaranteed that -// none of the devices running this library has SE FWs in the range -// [1.2.2, 1.2.8], then enabling this option will disable runtime version -// checks. -// Default: 0 -#define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 0 - -// - -// <<< end of configuration section >>> - -// ----------------------------------------------------------------------------- -// Additional SE version related logic (DO NOT MODIFY) - -// SL_SE_ASSUME_FW_AT_LEAST_1_2_10 is no longer in use, however, it is kept here -// for backwards compatibility. */ -#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) - #undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 - #define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 - #undef SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA - #define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 1 -#endif - -// SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2 is no longer in use, however, it is kept -// here for backwards compatibility. */ -#if defined(SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2) - #undef SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 - #define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 1 -#endif - -// SLI_SE_ASSUME_FW_AT_LEAST_1_2_2 is no longer in use, however, it is kept -// here for backwards compatibility. */ -#if defined(SLI_SE_ASSUME_FW_AT_LEAST_1_2_2) - #undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 - #define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 -#endif - -#endif // SL_MBEDTLS_DEVICE_CONFIG_H +#ifndef SL_MBEDTLS_DEVICE_CONFIG_H +#define SL_MBEDTLS_DEVICE_CONFIG_H + +// ----------------------------------------------------------------------------- +// User exposed config options + +// <<< Use Configuration Wizard in Context Menu >>> + +// Secure Engine (SE) version configuration + +// Support SE firmware versions older than 1.2.2 <0-1> +// Enable software fallback for ECDH and ECC public key validation on xG21 +// devices running SE firmware versions lower than 1.2.2. +// +// Due to other stability concerns, it is strongly recommended to upgrade +// these devices to the latest firmware revision instead of turning on +// software fallback support. +// +// Not having fallback support will make ECDH operations, as well as PSA +// Crypto public key import, return an error code on affected devices. +// +// Default: 0 +#define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 0 + +// Assume an SE firmware version newer than 1.2.2 <0-1> +// For enhanced performance: if it is guaranteed that all devices on which +// this library will run are updated to at least SE FW 1.2.2, then turning +// on this option will remove certain fallback checks, thereby reducing the +// amount of processing required for ECDH and public key verification +// operations. +// Default: 0 +#define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 0 + +// Assume an SE firmware version that is unaffected by Ed25519 errata <0-1> +// For minimal code size and performance savings: if it is guaranteed that +// none of the devices running this library has SE FWs in the range +// [1.2.2, 1.2.8], then enabling this option will disable runtime version +// checks. +// Default: 0 +#define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 0 + +// + +// <<< end of configuration section >>> + +// ----------------------------------------------------------------------------- +// Additional SE version related logic (DO NOT MODIFY) + +// SL_SE_ASSUME_FW_AT_LEAST_1_2_10 is no longer in use, however, it is kept here +// for backwards compatibility. */ +#if defined(SL_SE_ASSUME_FW_AT_LEAST_1_2_10) + #undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 + #define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 + #undef SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA + #define SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA 1 +#endif + +// SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2 is no longer in use, however, it is kept +// here for backwards compatibility. */ +#if defined(SLI_SE_SUPPORT_FW_PRIOR_TO_1_2_2) + #undef SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 + #define SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 1 +#endif + +// SLI_SE_ASSUME_FW_AT_LEAST_1_2_2 is no longer in use, however, it is kept +// here for backwards compatibility. */ +#if defined(SLI_SE_ASSUME_FW_AT_LEAST_1_2_2) + #undef SL_SE_ASSUME_FW_AT_LEAST_1_2_2 + #define SL_SE_ASSUME_FW_AT_LEAST_1_2_2 1 +#endif + +#endif // SL_MBEDTLS_DEVICE_CONFIG_H diff --git a/locator_ncp/config/sl_memory_config.h b/locator_ncp/config/sl_memory_config.h index cef874e..ffb8705 100644 --- a/locator_ncp/config/sl_memory_config.h +++ b/locator_ncp/config/sl_memory_config.h @@ -1,28 +1,28 @@ -#ifndef SL_MEMORY_CONFIG_H -#define SL_MEMORY_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> -// Memory configuration - -// Stack size for the application. -// Default: 4096 -// The stack size configured here will be used by the stack that the -// application uses when coming out of a reset. -#ifndef SL_STACK_SIZE - #define SL_STACK_SIZE 2752 -#endif - -// Minimum heap size for the application. -// Default: 2048 -// Note that this value will configure the c heap which is normally used by -// malloc() and free() from the c library. The value defines a minimum heap -// size that is guaranteed to be available. The available heap may be larger -// to make use of any memory that would otherwise remain unused. -#ifndef SL_HEAP_SIZE - #define SL_HEAP_SIZE 12000 -#endif - -// -// <<< end of configuration section >>> - -#endif +#ifndef SL_MEMORY_CONFIG_H +#define SL_MEMORY_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> +// Memory configuration + +// Stack size for the application. +// Default: 4096 +// The stack size configured here will be used by the stack that the +// application uses when coming out of a reset. +#ifndef SL_STACK_SIZE + #define SL_STACK_SIZE 2752 +#endif + +// Minimum heap size for the application. +// Default: 2048 +// Note that this value will configure the c heap which is normally used by +// malloc() and free() from the c library. The value defines a minimum heap +// size that is guaranteed to be available. The available heap may be larger +// to make use of any memory that would otherwise remain unused. +#ifndef SL_HEAP_SIZE + #define SL_HEAP_SIZE 12000 +#endif + +// +// <<< end of configuration section >>> + +#endif diff --git a/locator_ncp/config/sl_mx25_flash_shutdown_usart_config.h b/locator_ncp/config/sl_mx25_flash_shutdown_usart_config.h index bb99d30..09f6d4d 100644 --- a/locator_ncp/config/sl_mx25_flash_shutdown_usart_config.h +++ b/locator_ncp/config/sl_mx25_flash_shutdown_usart_config.h @@ -1,67 +1,67 @@ -/***************************************************************************//** - * @file - * @brief SL_MX25_FLASH_SHUTDOWN_USART Config - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H -#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H - -// <<< sl:start pin_tool >>> -// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN -// [USART_SL_MX25_FLASH_SHUTDOWN] -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 -#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 - -// USART0 TX on PC00 -#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 - -// USART0 RX on PC01 -#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 - -// USART0 CLK on PC02 -#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC -#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 - -// [USART_SL_MX25_FLASH_SHUTDOWN] - -// SL_MX25_FLASH_SHUTDOWN_CS - -// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] -#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PORT -#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA -#endif -#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PIN -#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 -#endif -// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H +/***************************************************************************//** + * @file + * @brief SL_MX25_FLASH_SHUTDOWN_USART Config + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_CONFIG_H +#define SL_MX25_FLASH_SHUTDOWN_CONFIG_H + +// <<< sl:start pin_tool >>> +// {usart signal=TX,RX,CLK} SL_MX25_FLASH_SHUTDOWN +// [USART_SL_MX25_FLASH_SHUTDOWN] +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL USART0 +#define SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO 0 + +// USART0 TX on PC00 +#define SL_MX25_FLASH_SHUTDOWN_TX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_TX_PIN 0 + +// USART0 RX on PC01 +#define SL_MX25_FLASH_SHUTDOWN_RX_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_RX_PIN 1 + +// USART0 CLK on PC02 +#define SL_MX25_FLASH_SHUTDOWN_CLK_PORT gpioPortC +#define SL_MX25_FLASH_SHUTDOWN_CLK_PIN 2 + +// [USART_SL_MX25_FLASH_SHUTDOWN] + +// SL_MX25_FLASH_SHUTDOWN_CS + +// $[GPIO_SL_MX25_FLASH_SHUTDOWN_CS] +#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PORT +#define SL_MX25_FLASH_SHUTDOWN_CS_PORT gpioPortA +#endif +#ifndef SL_MX25_FLASH_SHUTDOWN_CS_PIN +#define SL_MX25_FLASH_SHUTDOWN_CS_PIN 4 +#endif +// [GPIO_SL_MX25_FLASH_SHUTDOWN_CS]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_MX25_FLASH_SHUTDOWN_CONFIG_H diff --git a/locator_ncp/config/sl_ncp_config.h b/locator_ncp/config/sl_ncp_config.h index 0a30d7a..52fb13f 100644 --- a/locator_ncp/config/sl_ncp_config.h +++ b/locator_ncp/config/sl_ncp_config.h @@ -1,58 +1,58 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Interface Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_CONFIG_H -#define SL_NCP_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup ncp - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Command buffer size (bytes) <260-1024> -// Default: 260 -// Define the size of Bluetooth NCP command buffer in bytes. -#define SL_NCP_CMD_BUF_SIZE (260) - -// Event buffer size (bytes) <260-4096> -// Default: 260 -// Define the size of Bluetooth NCP event buffer in bytes. -#define SL_NCP_EVT_BUF_SIZE (260) - -// Command timeout (ms) <0-10000> -// Default: 500 -// Allowed timeout in ms for command reception before triggering error. -#define SL_NCP_CMD_TIMEOUT_MS (500) -// <<< end of configuration section >>> - -/** @} (end addtogroup ncp) */ -#endif // SL_NCP_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Interface Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_CONFIG_H +#define SL_NCP_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup ncp + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Command buffer size (bytes) <260-1024> +// Default: 260 +// Define the size of Bluetooth NCP command buffer in bytes. +#define SL_NCP_CMD_BUF_SIZE (260) + +// Event buffer size (bytes) <260-4096> +// Default: 260 +// Define the size of Bluetooth NCP event buffer in bytes. +#define SL_NCP_EVT_BUF_SIZE (260) + +// Command timeout (ms) <0-10000> +// Default: 500 +// Allowed timeout in ms for command reception before triggering error. +#define SL_NCP_CMD_TIMEOUT_MS (500) +// <<< end of configuration section >>> + +/** @} (end addtogroup ncp) */ +#endif // SL_NCP_CONFIG_H diff --git a/locator_ncp/config/sl_ncp_evt_filter_config.h b/locator_ncp/config/sl_ncp_evt_filter_config.h index 925e375..769e5c6 100644 --- a/locator_ncp/config/sl_ncp_evt_filter_config.h +++ b/locator_ncp/config/sl_ncp_evt_filter_config.h @@ -1,48 +1,48 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_CONFIG_H -#define SL_NCP_EVT_FILTER_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Array length of the event filter <1-16> -// Default: 8 -// Define the length of Bluetooth NCP event filter buffer. -#define SL_NCP_EVT_FILTER_ARRAY_LENGTH 8 -// <<< end of configuration section >>> - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_CONFIG_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_CONFIG_H +#define SL_NCP_EVT_FILTER_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Array length of the event filter <1-16> +// Default: 8 +// Define the length of Bluetooth NCP event filter buffer. +#define SL_NCP_EVT_FILTER_ARRAY_LENGTH 8 +// <<< end of configuration section >>> + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_CONFIG_H diff --git a/locator_ncp/config/sl_power_manager_config.h b/locator_ncp/config/sl_power_manager_config.h index a97fb03..c83e598 100644 --- a/locator_ncp/config/sl_power_manager_config.h +++ b/locator_ncp/config/sl_power_manager_config.h @@ -1,64 +1,64 @@ -/***************************************************************************//** - * @file - * @brief Power Manager configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_POWER_MANAGER_CONFIG_H -#define SL_POWER_MANAGER_CONFIG_H - -// Power Manager Configuration - -// Enable custom IRQ handler for external HF oscillator. -// Enable if CMU_IRQHandler/HFXO0_IRQHandler is needed from your application. -// The function sl_power_manager_irq_handler() will have to be called from you custom handler if this is enabled. -// Default: 0 -#define SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER 0 - -// Enable fast wakeup (disable voltage scaling in EM2/3 mode) -// Enable or disable voltage scaling in EM2/3 modes (when available). This decreases wakeup time by about 30 us. -// Deprecated. It is replaced by the function sl_power_manager_em23_voltage_scaling_enable_fast_wakeup() -// Default: 0 -#define SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP 0 - -// Enable debugging feature -// Enable or disable debugging features (trace the different modules that have requirements). -// Default: 0 -#define SL_POWER_MANAGER_DEBUG 0 - -// Maximum numbers of requirements that can be logged -// Default: 10 -#define SL_POWER_MANAGER_DEBUG_POOL_SIZE 10 -// - -// - -#endif /* SL_POWER_MANAGER_CONFIG_H */ - -// <<< end of configuration section >>> +/***************************************************************************//** + * @file + * @brief Power Manager configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_POWER_MANAGER_CONFIG_H +#define SL_POWER_MANAGER_CONFIG_H + +// Power Manager Configuration + +// Enable custom IRQ handler for external HF oscillator. +// Enable if CMU_IRQHandler/HFXO0_IRQHandler is needed from your application. +// The function sl_power_manager_irq_handler() will have to be called from you custom handler if this is enabled. +// Default: 0 +#define SL_POWER_MANAGER_CUSTOM_HF_OSCILLATOR_IRQ_HANDLER 0 + +// Enable fast wakeup (disable voltage scaling in EM2/3 mode) +// Enable or disable voltage scaling in EM2/3 modes (when available). This decreases wakeup time by about 30 us. +// Deprecated. It is replaced by the function sl_power_manager_em23_voltage_scaling_enable_fast_wakeup() +// Default: 0 +#define SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP 0 + +// Enable debugging feature +// Enable or disable debugging features (trace the different modules that have requirements). +// Default: 0 +#define SL_POWER_MANAGER_DEBUG 0 + +// Maximum numbers of requirements that can be logged +// Default: 10 +#define SL_POWER_MANAGER_DEBUG_POOL_SIZE 10 +// + +// + +#endif /* SL_POWER_MANAGER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/locator_ncp/config/sl_rail_util_aox_config.h b/locator_ncp/config/sl_rail_util_aox_config.h index 5227eba..949b267 100644 --- a/locator_ncp/config/sl_rail_util_aox_config.h +++ b/locator_ncp/config/sl_rail_util_aox_config.h @@ -1,106 +1,106 @@ -/***************************************************************************//** - * @file - * @brief - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_AOX_CONFIG_H -#define SL_RAIL_UTIL_AOX_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> -// Number of AoX Antenna Pins -// <0-6:1> -// Default: 0 -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT 4 -#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT == 0 -#warning "The AoX component is only needed to configure multiple AoX antennas!" -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT == 0 -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> - -// CTE antenna GPIO 0 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN0 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN0] -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT gpioPortC -#endif -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN 4 -#endif -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN0]$ - -// CTE antenna GPIO 1 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN1 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN1] -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT gpioPortC -#endif -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN 5 -#endif -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN1]$ - -// CTE antenna GPIO 2 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN2 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN2] -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT gpioPortC -#endif -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN 6 -#endif -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN2]$ - -// CTE antenna GPIO 3 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN3 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN3] -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT gpioPortC -#endif -#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN -#define SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN 7 -#endif -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN3]$ - -// CTE antenna GPIO 4 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN4 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN4] - -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN4]$ - -// CTE antenna GPIO 5 -// SL_RAIL_UTIL_AOX_ANTENNA_PIN5 -// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN5] - -// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN5]$ - -// <<< sl:end pin_tool >>> - -#endif // SL_RAIL_UTIL_AOX_CONFIG_H +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_AOX_CONFIG_H +#define SL_RAIL_UTIL_AOX_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> +// Number of AoX Antenna Pins +// <0-6:1> +// Default: 0 +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT 4 +#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT == 0 +#warning "The AoX component is only needed to configure multiple AoX antennas!" +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT == 0 +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> + +// CTE antenna GPIO 0 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN0 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN0] +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT gpioPortC +#endif +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN 4 +#endif +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN0]$ + +// CTE antenna GPIO 1 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN1 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN1] +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT gpioPortC +#endif +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN 5 +#endif +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN1]$ + +// CTE antenna GPIO 2 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN2 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN2] +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT gpioPortC +#endif +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN 6 +#endif +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN2]$ + +// CTE antenna GPIO 3 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN3 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN3] +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT gpioPortC +#endif +#ifndef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN +#define SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN 7 +#endif +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN3]$ + +// CTE antenna GPIO 4 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN4 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN4] + +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN4]$ + +// CTE antenna GPIO 5 +// SL_RAIL_UTIL_AOX_ANTENNA_PIN5 +// $[GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN5] + +// [GPIO_SL_RAIL_UTIL_AOX_ANTENNA_PIN5]$ + +// <<< sl:end pin_tool >>> + +#endif // SL_RAIL_UTIL_AOX_CONFIG_H diff --git a/locator_ncp/config/sl_rail_util_pa_config.h b/locator_ncp/config/sl_rail_util_pa_config.h index a1a5fce..ce60853 100644 --- a/locator_ncp/config/sl_rail_util_pa_config.h +++ b/locator_ncp/config/sl_rail_util_pa_config.h @@ -1,81 +1,81 @@ -/***************************************************************************//** - * @file - * @brief Power Amplifier configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_PA_CONFIG_H -#define SL_RAIL_UTIL_PA_CONFIG_H - -#include "rail_types.h" - -// <<< Use Configuration Wizard in Context Menu >>> - -// PA Configuration -// Initial PA Power (deci-dBm, 100 = 10.0 dBm) -// Default: 100 -#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 - -// PA Ramp Time (microseconds) -// <0-65535:1> -// Default: 2 -#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 -// Milli-volts on PA supply pin (PA_VDD) -// <0-65535:1> -// Default: 3300 -#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 -// 2.4 GHz PA Selection -// Highest Possible -// High Power (chip-specific) -// Low Power -// Disable -// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST -// Sub-1 GHz PA Selection -// Disable -// Default: RAIL_TX_POWER_MODE_NONE -#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE -// - -// PA Curve Configuration -// Header file containing custom PA curves -// Default: "pa_curves_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" -// Header file containing PA curve types -// Default: "pa_curve_types_efr32.h" -#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" -// - -// PA Calibration Configuration -// Apply PA Calibration Factory Offset -// Default: 1 -#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 -// - -// <<< end of configuration section >>> - -#endif // SL_RAIL_UTIL_PA_CONFIG_H +/***************************************************************************//** + * @file + * @brief Power Amplifier configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_PA_CONFIG_H +#define SL_RAIL_UTIL_PA_CONFIG_H + +#include "rail_types.h" + +// <<< Use Configuration Wizard in Context Menu >>> + +// PA Configuration +// Initial PA Power (deci-dBm, 100 = 10.0 dBm) +// Default: 100 +#define SL_RAIL_UTIL_PA_POWER_DECI_DBM 100 + +// PA Ramp Time (microseconds) +// <0-65535:1> +// Default: 2 +#define SL_RAIL_UTIL_PA_RAMP_TIME_US 2 +// Milli-volts on PA supply pin (PA_VDD) +// <0-65535:1> +// Default: 3300 +#define SL_RAIL_UTIL_PA_VOLTAGE_MV 1800 +// 2.4 GHz PA Selection +// Highest Possible +// High Power (chip-specific) +// Low Power +// Disable +// Default: RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_2P4GIG_HIGHEST +// Sub-1 GHz PA Selection +// Disable +// Default: RAIL_TX_POWER_MODE_NONE +#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE +// + +// PA Curve Configuration +// Header file containing custom PA curves +// Default: "pa_curves_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_HEADER "pa_curves_efr32.h" +// Header file containing PA curve types +// Default: "pa_curve_types_efr32.h" +#define SL_RAIL_UTIL_PA_CURVE_TYPES "pa_curve_types_efr32.h" +// + +// PA Calibration Configuration +// Apply PA Calibration Factory Offset +// Default: 1 +#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE 1 +// + +// <<< end of configuration section >>> + +#endif // SL_RAIL_UTIL_PA_CONFIG_H diff --git a/locator_ncp/config/sl_rail_util_power_manager_init_config.h b/locator_ncp/config/sl_rail_util_power_manager_init_config.h index cbc69f2..8cc3085 100644 --- a/locator_ncp/config/sl_rail_util_power_manager_init_config.h +++ b/locator_ncp/config/sl_rail_util_power_manager_init_config.h @@ -1,44 +1,44 @@ -/***************************************************************************//** - * @file - * @brief RAIL power manager configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H -#define SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// RAIL power manager configuration - -// Enable RAIL power manager initialization -// Default: 1 -#define SL_RAIL_UTIL_RAIL_POWER_MANAGER_INIT 1 - -// -// <<< end of configuration section >>> -#endif // SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H +/***************************************************************************//** + * @file + * @brief RAIL power manager configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H +#define SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RAIL power manager configuration + +// Enable RAIL power manager initialization +// Default: 1 +#define SL_RAIL_UTIL_RAIL_POWER_MANAGER_INIT 1 + +// +// <<< end of configuration section >>> +#endif // SL_RAIL_UTIL_POWER_MANAGER_INIT_CONFIG_H diff --git a/locator_ncp/config/sl_simple_com_config.h b/locator_ncp/config/sl_simple_com_config.h index b742d1e..f0f413f 100644 --- a/locator_ncp/config/sl_simple_com_config.h +++ b/locator_ncp/config/sl_simple_com_config.h @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) Configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_CONFIG_H -#define SL_SIMPLE_COM_CONFIG_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -// Receive buffer size (bytes) <260-1024> -// Default: 260 -// Define the size of the receive buffer in bytes. -#define SL_SIMPLE_COM_RX_BUF_SIZE (260) - -// Transmit buffer size (bytes) <260-4096> -// Default: 260 -// Define the size of the transmit buffer in bytes. -#define SL_SIMPLE_COM_TX_BUF_SIZE (260) - -// Robust -// Message header -// Robustify the communication by adding a message header and filter out invalid messages. -// Note: This configuration should match on the sender and receiver side. -// Default: Off -#define SL_SIMPLE_COM_ROBUST 0 - -// CRC -// Add payload CRC and perform checking. -// Note: This configuration should match on the sender and receiver side. -// Default: On -#define SL_SIMPLE_COM_ROBUST_CRC 1 -// -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_CONFIG_H +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) Configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_CONFIG_H +#define SL_SIMPLE_COM_CONFIG_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +// Receive buffer size (bytes) <260-1024> +// Default: 260 +// Define the size of the receive buffer in bytes. +#define SL_SIMPLE_COM_RX_BUF_SIZE (260) + +// Transmit buffer size (bytes) <260-4096> +// Default: 260 +// Define the size of the transmit buffer in bytes. +#define SL_SIMPLE_COM_TX_BUF_SIZE (260) + +// Robust +// Message header +// Robustify the communication by adding a message header and filter out invalid messages. +// Note: This configuration should match on the sender and receiver side. +// Default: Off +#define SL_SIMPLE_COM_ROBUST 0 + +// CRC +// Add payload CRC and perform checking. +// Note: This configuration should match on the sender and receiver side. +// Default: On +#define SL_SIMPLE_COM_ROBUST_CRC 1 +// +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_CONFIG_H diff --git a/locator_ncp/config/sl_sleeptimer_config.h b/locator_ncp/config/sl_sleeptimer_config.h index 8344ef5..a315b29 100644 --- a/locator_ncp/config/sl_sleeptimer_config.h +++ b/locator_ncp/config/sl_sleeptimer_config.h @@ -1,82 +1,82 @@ -/***************************************************************************//** - * @file - * @brief Sleep Timer configuration file. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef SL_SLEEPTIMER_CONFIG_H -#define SL_SLEEPTIMER_CONFIG_H - -#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 -#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 -#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 -#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 -#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 -#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 -#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 -#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 - -// Timer Peripheral Used by Sleeptimer -// Default (auto select) -// RTCC -// Radio internal RTC (PRORTC) -// RTC -// SYSRTC -// Back-Up RTC (BURTC) -// WTIMER -// TIMER -// Selection of the Timer Peripheral Used by the Sleeptimer -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT - -// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) -// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. -// Default: 0 -#define SL_SLEEPTIMER_TIMER_INSTANCE 0 - -// Enable wallclock functionality -// Enable or disable wallclock functionalities (get_time, get_date, etc). -// Default: 0 -#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 - -// Timer frequency divider (not applicable for WTIMER/TIMER) -// WTIMER/TIMER peripherals are always prescaled to 1024. -// Default: 1 -#define SL_SLEEPTIMER_FREQ_DIVIDER 1 - -// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. -// Default: 0 -#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 - -// Enable DEBUGRUN functionality on hardware RTC. -// Default: 0 -#define SL_SLEEPTIMER_DEBUGRUN 0 - -#endif /* SLEEPTIMER_CONFIG_H */ - -// <<< end of configuration section >>> +/***************************************************************************//** + * @file + * @brief Sleep Timer configuration file. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef SL_SLEEPTIMER_CONFIG_H +#define SL_SLEEPTIMER_CONFIG_H + +#define SL_SLEEPTIMER_PERIPHERAL_DEFAULT 0 +#define SL_SLEEPTIMER_PERIPHERAL_RTCC 1 +#define SL_SLEEPTIMER_PERIPHERAL_PRORTC 2 +#define SL_SLEEPTIMER_PERIPHERAL_RTC 3 +#define SL_SLEEPTIMER_PERIPHERAL_SYSRTC 4 +#define SL_SLEEPTIMER_PERIPHERAL_BURTC 5 +#define SL_SLEEPTIMER_PERIPHERAL_WTIMER 6 +#define SL_SLEEPTIMER_PERIPHERAL_TIMER 7 + +// Timer Peripheral Used by Sleeptimer +// Default (auto select) +// RTCC +// Radio internal RTC (PRORTC) +// RTC +// SYSRTC +// Back-Up RTC (BURTC) +// WTIMER +// TIMER +// Selection of the Timer Peripheral Used by the Sleeptimer +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_DEFAULT + +// TIMER/WTIMER Instance Used by Sleeptimer (not applicable for other peripherals) +// Make sure TIMER instance size is 32bits. Check datasheet for 32bits TIMERs. +// Default: 0 +#define SL_SLEEPTIMER_TIMER_INSTANCE 0 + +// Enable wallclock functionality +// Enable or disable wallclock functionalities (get_time, get_date, etc). +// Default: 0 +#define SL_SLEEPTIMER_WALLCLOCK_CONFIG 0 + +// Timer frequency divider (not applicable for WTIMER/TIMER) +// WTIMER/TIMER peripherals are always prescaled to 1024. +// Default: 1 +#define SL_SLEEPTIMER_FREQ_DIVIDER 1 + +// If Radio internal RTC (PRORTC) HAL is used, determines if it owns the IRQ handler. Enable, if no wireless stack is used. +// Default: 0 +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 + +// Enable DEBUGRUN functionality on hardware RTC. +// Default: 0 +#define SL_SLEEPTIMER_DEBUGRUN 0 + +#endif /* SLEEPTIMER_CONFIG_H */ + +// <<< end of configuration section >>> diff --git a/locator_ncp/config/sl_uartdrv_usart_vcom_config.h b/locator_ncp/config/sl_uartdrv_usart_vcom_config.h index 3853da5..0416348 100644 --- a/locator_ncp/config/sl_uartdrv_usart_vcom_config.h +++ b/locator_ncp/config/sl_uartdrv_usart_vcom_config.h @@ -1,133 +1,133 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV_USART Config - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H -#define SL_UARTDRV_USART_VCOM_CONFIG_H - -#include "em_usart.h" -// <<< Use Configuration Wizard in Context Menu >>> - -// UART settings -// Baud rate -// Default: 115200 -#define SL_UARTDRV_USART_VCOM_BAUDRATE 460800 - -// Parity mode to use -// No Parity -// Even parity -// Odd parity -// Default: usartNoParity -#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity - -// Number of stop bits to use. -// 0.5 stop bits -// 1 stop bits -// 1.5 stop bits -// 2 stop bits -// Default: usartStopbits1 -#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 - -// Flow control method -// None -// Software XON/XOFF -// nRTS/nCTS hardware handshake -// UART peripheral controls nRTS/nCTS -// Default: uartdrvFlowControlHwUart -#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone - -// Oversampling selection -// 16x oversampling -// 8x oversampling -// 6x oversampling -// 4x oversampling -// Default: usartOVS16 -#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 - -// Majority vote disable for 16x, 8x and 6x oversampling modes -// True -// False -#define SL_UARTDRV_USART_VCOM_MVDIS false - -// Size of the receive operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 - -// Size of the transmit operation queue -// Default: 6 -#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 - -// -// <<< end of configuration section >>> - -// <<< sl:start pin_tool >>> -// SL_UARTDRV_USART_VCOM -// $[USART_SL_UARTDRV_USART_VCOM] -#ifndef SL_UARTDRV_USART_VCOM_PERIPHERAL -#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART1 -#endif -#ifndef SL_UARTDRV_USART_VCOM_PERIPHERAL_NO -#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 1 -#endif - -// USART1 TX on PA05 -#ifndef SL_UARTDRV_USART_VCOM_TX_PORT -#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_VCOM_TX_PIN -#define SL_UARTDRV_USART_VCOM_TX_PIN 5 -#endif - -// USART1 RX on PA06 -#ifndef SL_UARTDRV_USART_VCOM_RX_PORT -#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_VCOM_RX_PIN -#define SL_UARTDRV_USART_VCOM_RX_PIN 6 -#endif - -// USART1 CTS on PA08 -#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT -#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_VCOM_CTS_PIN -#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 -#endif - -// USART1 RTS on PA07 -#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT -#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA -#endif -#ifndef SL_UARTDRV_USART_VCOM_RTS_PIN -#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 -#endif -// [USART_SL_UARTDRV_USART_VCOM]$ -// <<< sl:end pin_tool >>> - -#endif // SL_UARTDRV_USART_VCOM_CONFIG_H +/***************************************************************************//** + * @file + * @brief UARTDRV_USART Config + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_UARTDRV_USART_VCOM_CONFIG_H +#define SL_UARTDRV_USART_VCOM_CONFIG_H + +#include "em_usart.h" +// <<< Use Configuration Wizard in Context Menu >>> + +// UART settings +// Baud rate +// Default: 115200 +#define SL_UARTDRV_USART_VCOM_BAUDRATE 460800 + +// Parity mode to use +// No Parity +// Even parity +// Odd parity +// Default: usartNoParity +#define SL_UARTDRV_USART_VCOM_PARITY usartNoParity + +// Number of stop bits to use. +// 0.5 stop bits +// 1 stop bits +// 1.5 stop bits +// 2 stop bits +// Default: usartStopbits1 +#define SL_UARTDRV_USART_VCOM_STOP_BITS usartStopbits1 + +// Flow control method +// None +// Software XON/XOFF +// nRTS/nCTS hardware handshake +// UART peripheral controls nRTS/nCTS +// Default: uartdrvFlowControlHwUart +#define SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE uartdrvFlowControlNone + +// Oversampling selection +// 16x oversampling +// 8x oversampling +// 6x oversampling +// 4x oversampling +// Default: usartOVS16 +#define SL_UARTDRV_USART_VCOM_OVERSAMPLING usartOVS4 + +// Majority vote disable for 16x, 8x and 6x oversampling modes +// True +// False +#define SL_UARTDRV_USART_VCOM_MVDIS false + +// Size of the receive operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_RX_BUFFER_SIZE 6 + +// Size of the transmit operation queue +// Default: 6 +#define SL_UARTDRV_USART_VCOM_TX_BUFFER_SIZE 6 + +// +// <<< end of configuration section >>> + +// <<< sl:start pin_tool >>> +// SL_UARTDRV_USART_VCOM +// $[USART_SL_UARTDRV_USART_VCOM] +#ifndef SL_UARTDRV_USART_VCOM_PERIPHERAL +#define SL_UARTDRV_USART_VCOM_PERIPHERAL USART1 +#endif +#ifndef SL_UARTDRV_USART_VCOM_PERIPHERAL_NO +#define SL_UARTDRV_USART_VCOM_PERIPHERAL_NO 1 +#endif + +// USART1 TX on PA05 +#ifndef SL_UARTDRV_USART_VCOM_TX_PORT +#define SL_UARTDRV_USART_VCOM_TX_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_VCOM_TX_PIN +#define SL_UARTDRV_USART_VCOM_TX_PIN 5 +#endif + +// USART1 RX on PA06 +#ifndef SL_UARTDRV_USART_VCOM_RX_PORT +#define SL_UARTDRV_USART_VCOM_RX_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_VCOM_RX_PIN +#define SL_UARTDRV_USART_VCOM_RX_PIN 6 +#endif + +// USART1 CTS on PA08 +#ifndef SL_UARTDRV_USART_VCOM_CTS_PORT +#define SL_UARTDRV_USART_VCOM_CTS_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_VCOM_CTS_PIN +#define SL_UARTDRV_USART_VCOM_CTS_PIN 8 +#endif + +// USART1 RTS on PA07 +#ifndef SL_UARTDRV_USART_VCOM_RTS_PORT +#define SL_UARTDRV_USART_VCOM_RTS_PORT gpioPortA +#endif +#ifndef SL_UARTDRV_USART_VCOM_RTS_PIN +#define SL_UARTDRV_USART_VCOM_RTS_PIN 7 +#endif +// [USART_SL_UARTDRV_USART_VCOM]$ +// <<< sl:end pin_tool >>> + +#endif // SL_UARTDRV_USART_VCOM_CONFIG_H diff --git a/locator_ncp/config/uartdrv_config.h b/locator_ncp/config/uartdrv_config.h index e1d0a85..3bf6f22 100644 --- a/locator_ncp/config/uartdrv_config.h +++ b/locator_ncp/config/uartdrv_config.h @@ -1,114 +1,114 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV configuration file. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ -#define __SILICON_LABS_UARTDRV_CONFIG_H__ - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ -/// Size of the receive operation queue. -/// @details -/// The maximum number of receive operations that can be queued up for one -/// driver instance before @ref UARTDRV_Receive() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 -#endif - -/// Size of the transmit operation queue. -/// @details -/// The maximum number of transmit operations that can be queued up for one -/// driver instance before @ref UARTDRV_Transmit() returns -/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. -/// @note -/// This macro is not used by the UARTDRV itself, but is intended to be used -/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate -/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. -#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) -#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 -#endif - -// <<< Use Configuration Wizard in Context Menu >>> -// UARTDRV Settings - -/// Set to 1 to include flow control support -#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -// Flow control support -// <1=> Enable -// <0=> Disable -// Default: 1 -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 -#endif - -/// Maximum number of driver instances. -#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) -// Maximum number of driver instances -// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 -// Default: 4 -#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 -#endif - -/// UART software flow control code: request peer to start TX -#if !defined(UARTDRV_FC_SW_XON) -// UART software flow control code: request peer to start TX -// Default: 0x11 -#define UARTDRV_FC_SW_XON 0x11 -#endif - -/// UART software flow control code: request peer to stop TX -#if !defined(UARTDRV_FC_SW_XOFF) -// UART software flow control code: request peer to stop TX -// Default: 0x13 -#define UARTDRV_FC_SW_XOFF 0x13 -#endif - -/// UART enable reception when sleeping. -#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) -// Enable reception when sleeping -// Enable reception when sleeping will use the power manager and add EM1 -// requirement during receive operations that use DMA. -// <1=> Enable -// <0=> Disable -// Default: 1 -#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 -#endif - -// - -// <<< end of configuration section >>> - -/** @} (end addtogroup uartdrv) */ - -#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ +/***************************************************************************//** + * @file + * @brief UARTDRV configuration file. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_UARTDRV_CONFIG_H__ +#define __SILICON_LABS_UARTDRV_CONFIG_H__ + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ +/// Size of the receive operation queue. +/// @details +/// The maximum number of receive operations that can be queued up for one +/// driver instance before @ref UARTDRV_Receive() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_RX_BUFS 6 +#endif + +/// Size of the transmit operation queue. +/// @details +/// The maximum number of transmit operations that can be queued up for one +/// driver instance before @ref UARTDRV_Transmit() returns +/// @ref ECODE_EMDRV_UARTDRV_QUEUE_FULL. +/// @note +/// This macro is not used by the UARTDRV itself, but is intended to be used +/// with the @ref DEFINE_BUF_QUEUE macro by the user of the driver to allocate +/// instances of the @ref UARTDRV_Buffer_FifoQueue_t struct. +#if !defined(EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS) +#define EMDRV_UARTDRV_MAX_CONCURRENT_TX_BUFS 6 +#endif + +// <<< Use Configuration Wizard in Context Menu >>> +// UARTDRV Settings + +/// Set to 1 to include flow control support +#if !defined(EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +// Flow control support +// <1=> Enable +// <0=> Disable +// Default: 1 +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 +#endif + +/// Maximum number of driver instances. +#if !defined(EMDRV_UARTDRV_MAX_DRIVER_INSTANCES) +// Maximum number of driver instances +// This maximum only applies when UARTDRV_FLOW_CONTROL_ENABLE = 1 +// Default: 4 +#define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 +#endif + +/// UART software flow control code: request peer to start TX +#if !defined(UARTDRV_FC_SW_XON) +// UART software flow control code: request peer to start TX +// Default: 0x11 +#define UARTDRV_FC_SW_XON 0x11 +#endif + +/// UART software flow control code: request peer to stop TX +#if !defined(UARTDRV_FC_SW_XOFF) +// UART software flow control code: request peer to stop TX +// Default: 0x13 +#define UARTDRV_FC_SW_XOFF 0x13 +#endif + +/// UART enable reception when sleeping. +#if !defined(UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION) +// Enable reception when sleeping +// Enable reception when sleeping will use the power manager and add EM1 +// requirement during receive operations that use DMA. +// <1=> Enable +// <0=> Disable +// Default: 1 +#define UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION 1 +#endif + +// + +// <<< end of configuration section >>> + +/** @} (end addtogroup uartdrv) */ + +#endif /* __SILICON_LABS_UARTDRV_CONFIG_H__ */ diff --git a/locator_ncp/create_bl_files.bat b/locator_ncp/create_bl_files.bat index 5ba02ac..068ed08 100644 --- a/locator_ncp/create_bl_files.bat +++ b/locator_ncp/create_bl_files.bat @@ -1,281 +1,281 @@ -@echo off - -:: use PATH_GCCARM env var to override default path for gcc-arm -if "%PATH_GCCARM%"=="" ( - set OBJCOPY="%ARM_GCC_DIR%\bin\arm-none-eabi-objcopy.exe" -) else ( - set OBJCOPY=%PATH_GCCARM%\bin\arm-none-eabi-objcopy.exe -) - -:: use PATH_SCMD env var to override default path for Simplicity Commander -if NOT "%PATH_SCMD%"=="" ( - set COMMANDER=%PATH_SCMD%\commander.exe -) - -:: use PATH_OUT env var to override the full path for the .out file - -:: default file extension of GCC and IAR -set FILE_EXTENSION_GCC="*.axf" -set FILE_EXTENSION_IAR="*.out" - -:: names of the OTA and UART DFU output files -set OTA_APPLO_NAME=apploader -set OTA_APPLI_NAME=application -set UARTDFU_FULL_NAME=full - -:: names of the sign and encypt key files -set GBL_SIGING_KEY_FILE=app-sign-key.pem -set GBL_ENCRYPT_KEY_FILE=app-encrypt-key.txt - -:: bootlader file name -set BOOTLOADER_FILE=bootloader-second-stage.s37 - -:: project path -set PATH_PROJ=%~dp1 - -if "%PATH_PROJ%" == "" ( - echo No project path specified. Using current directory. - echo. - set PATH_PROJ=%~dp0 -) - -:: output path of the OTA and UART DFU gbl files -set PATH_GBL="%PATH_PROJ%\output_gbl" - -for /f "delims=" %%i in ('dir %PATH_PROJ%\*.axf %PATH_PROJ%\*.out /b/s/od') do set PATH_OUT=%%i -if "%PATH_OUT%"=="" ( - echo Error: neither %FILE_EXTENSION_GCC% nor %FILE_EXTENSION_IAR% found - echo Was the project compiled and linked successfully? - pause - goto:eof -) - -if not exist "%OBJCOPY%" ( - echo Error: gcc-arm objcopy not found at '%OBJCOPY%' - echo Use PATH_GCCARM env var to override default path for gcc-arm. - echo Please refer to AN1086 sections 2.3 and 3.10 on how to set the required - echo environmental variables. - pause - goto:eof -) - -if not exist "%COMMANDER%" ( - echo Error: Simplicity Commander not found at '%COMMANDER%' - echo Use PATH_SCMD env var to override default path for Simplicity Commander. - echo Please refer to AN1086 sections 2.3 and 3.10 on how to set the required - echo environmental variables. - pause - goto:eof -) - -if exist "%BOOTLOADER_FILE%" ( - echo Bootloader file was found -) else ( - echo Bootloader file was not found - echo ---- BOOTLOADER GENERATION ------------------------------------------- - echo For adding bootloader to apploader copy a bootloader s37 image, e.g. - echo 'bootloader-storage-internal-single.s37' to the project root folder, - echo rename it to 'bootloader-second-stage.s37' and rerun the script file. - echo ---------------------------------------------------------------------- - echo. -) - -if exist "%GBL_ENCRYPT_KEY_FILE%" ( - echo Encryption key file was found -) else ( - echo Encryption key file was not found - echo ---- ENCRYPTED GBL FILE GENERATION ----------------------------------- - echo To generate an encrypted firmware upgrade file, - echo copy an encryption key file into the root folder of the project, - echo rename it to 'app-encrypt-key.txt' and rerun the script file. - echo ---------------------------------------------------------------------- - echo. -) - -if exist "%GBL_SIGING_KEY_FILE%" ( - echo Signing key file was found -) else ( - echo Signing key file was not found - echo ---- SIGNED GBL FILE GENERATION -------------------------------------- - echo To generate a signed firmware upgrade file, - echo copy a signing key file into the root folder of the project, - echo rename it to 'app-sign-key.pem' and rerun the script file. - echo ---------------------------------------------------------------------- - echo. -) - -echo ********************************************************************** -echo Converting .out to .gbl files -echo ********************************************************************** -echo. -echo .out file used: -echo %PATH_OUT% -echo. -echo output folder: -echo %PATH_GBL% - -if not exist %PATH_GBL% ( - mkdir %PATH_GBL% -) - -:: create the GBL files -echo. -echo ********************************************************************** -echo Creating %OTA_APPLO_NAME%.gbl for OTA -echo ********************************************************************** -echo. -%OBJCOPY% -O srec -j .text_apploader* "%PATH_OUT%" "%PATH_GBL%\%OTA_APPLO_NAME%.srec" -if errorlevel 1 ( - pause - goto:eof -) -if exist %BOOTLOADER_FILE% ( -echo Bootloader file was found -%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --bootloader %BOOTLOADER_FILE% -) else ( -%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" -) -echo. -echo ********************************************************************** -echo Creating %OTA_APPLI_NAME%.gbl for OTA -echo ********************************************************************** -echo. -%OBJCOPY% -O srec -R .text_apploader* -R .text_signature* "%PATH_OUT%" "%PATH_GBL%\%OTA_APPLI_NAME%.srec" -if errorlevel 1 ( - pause - goto:eof -) -%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%.srec" - -:: create the full GBL files for UART DFU -echo. -echo ********************************************************************** -echo Creating %UARTDFU_FULL_NAME%.gbl for UART DFU -echo ********************************************************************** -echo. -%OBJCOPY% -O srec -R .text_bootloader* "%PATH_OUT%" "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" -if errorlevel 1 ( - pause - goto:eof -) -%COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" - -:: create encrypted GBL file for secure boot if encrypt-key file exist -if exist %GBL_ENCRYPT_KEY_FILE% ( - echo. - echo ********************************************************************** - echo Creating encrypted .gbl files - echo ********************************************************************** - echo. - if exist %BOOTLOADER_FILE% ( - echo Bootloader file was found - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --bootloader %BOOTLOADER_FILE% - ) else ( - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% - ) - echo. - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% - echo. - %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% -) - -:: create signed GBL file for secure boot if sign-key file exists -if exist %GBL_SIGING_KEY_FILE% ( - echo. - echo ********************************************************************** - echo Creating signed .gbl files - echo ********************************************************************** - echo. - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --secureboot --keyfile %GBL_SIGING_KEY_FILE% -o "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( - if exist %BOOTLOADER_FILE% ( - echo Bootloader file was found - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-signed.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% --bootloader %BOOTLOADER_FILE% - ) else ( - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-signed.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% - ) - ) - echo. - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --secureboot --keyfile %GBL_SIGING_KEY_FILE% -o "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-signed.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% - echo. - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" -o "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" - ) else ( - copy "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" >NUL - ) - %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% - - :: create signed and encrypted GBL file for if both sign-key and encrypt-key file exist - if exist %GBL_ENCRYPT_KEY_FILE% ( - echo. - echo ********************************************************************** - echo Creating signed and encrypted .gbl files - echo ********************************************************************** - echo. - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( - if exist %BOOTLOADER_FILE% ( - echo Bootloader file was found - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% --bootloader %BOOTLOADER_FILE% - ) else ( - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% - ) - echo. - ) - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% - echo. - %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% - ) -) else ( -echo. - echo ********************************************************************** - echo Creating crc .gbl files - echo ********************************************************************** - echo. - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --crc -o "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( - if exist %BOOTLOADER_FILE% ( - echo Bootloader file was found - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-crc.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --bootloader %BOOTLOADER_FILE% - ) else ( - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-crc.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" - ) - - ) - echo. - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --crc -o "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-crc.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" - echo. - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( - %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" -o "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" - ) else ( - copy "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" >NUL - ) - %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" - - :: create crc and encrypted GBL file if encrypt-key file exist - if exist %GBL_ENCRYPT_KEY_FILE% ( - echo. - echo ********************************************************************** - echo Creating crc and encrypted .gbl files - echo ********************************************************************** - echo. - if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( - if exist %BOOTLOADER_FILE% ( - echo Bootloader file was found - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --bootloader %BOOTLOADER_FILE% - ) else ( - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% - ) - echo. - ) - %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% - echo. - %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% - ) -) - -:: clean up output dir -del "%PATH_GBL%\*.srec" - -pause +@echo off + +:: use PATH_GCCARM env var to override default path for gcc-arm +if "%PATH_GCCARM%"=="" ( + set OBJCOPY="%ARM_GCC_DIR%\bin\arm-none-eabi-objcopy.exe" +) else ( + set OBJCOPY=%PATH_GCCARM%\bin\arm-none-eabi-objcopy.exe +) + +:: use PATH_SCMD env var to override default path for Simplicity Commander +if NOT "%PATH_SCMD%"=="" ( + set COMMANDER=%PATH_SCMD%\commander.exe +) + +:: use PATH_OUT env var to override the full path for the .out file + +:: default file extension of GCC and IAR +set FILE_EXTENSION_GCC="*.axf" +set FILE_EXTENSION_IAR="*.out" + +:: names of the OTA and UART DFU output files +set OTA_APPLO_NAME=apploader +set OTA_APPLI_NAME=application +set UARTDFU_FULL_NAME=full + +:: names of the sign and encypt key files +set GBL_SIGING_KEY_FILE=app-sign-key.pem +set GBL_ENCRYPT_KEY_FILE=app-encrypt-key.txt + +:: bootlader file name +set BOOTLOADER_FILE=bootloader-second-stage.s37 + +:: project path +set PATH_PROJ=%~dp1 + +if "%PATH_PROJ%" == "" ( + echo No project path specified. Using current directory. + echo. + set PATH_PROJ=%~dp0 +) + +:: output path of the OTA and UART DFU gbl files +set PATH_GBL="%PATH_PROJ%\output_gbl" + +for /f "delims=" %%i in ('dir %PATH_PROJ%\*.axf %PATH_PROJ%\*.out /b/s/od') do set PATH_OUT=%%i +if "%PATH_OUT%"=="" ( + echo Error: neither %FILE_EXTENSION_GCC% nor %FILE_EXTENSION_IAR% found + echo Was the project compiled and linked successfully? + pause + goto:eof +) + +if not exist "%OBJCOPY%" ( + echo Error: gcc-arm objcopy not found at '%OBJCOPY%' + echo Use PATH_GCCARM env var to override default path for gcc-arm. + echo Please refer to AN1086 sections 2.3 and 3.10 on how to set the required + echo environmental variables. + pause + goto:eof +) + +if not exist "%COMMANDER%" ( + echo Error: Simplicity Commander not found at '%COMMANDER%' + echo Use PATH_SCMD env var to override default path for Simplicity Commander. + echo Please refer to AN1086 sections 2.3 and 3.10 on how to set the required + echo environmental variables. + pause + goto:eof +) + +if exist "%BOOTLOADER_FILE%" ( + echo Bootloader file was found +) else ( + echo Bootloader file was not found + echo ---- BOOTLOADER GENERATION ------------------------------------------- + echo For adding bootloader to apploader copy a bootloader s37 image, e.g. + echo 'bootloader-storage-internal-single.s37' to the project root folder, + echo rename it to 'bootloader-second-stage.s37' and rerun the script file. + echo ---------------------------------------------------------------------- + echo. +) + +if exist "%GBL_ENCRYPT_KEY_FILE%" ( + echo Encryption key file was found +) else ( + echo Encryption key file was not found + echo ---- ENCRYPTED GBL FILE GENERATION ----------------------------------- + echo To generate an encrypted firmware upgrade file, + echo copy an encryption key file into the root folder of the project, + echo rename it to 'app-encrypt-key.txt' and rerun the script file. + echo ---------------------------------------------------------------------- + echo. +) + +if exist "%GBL_SIGING_KEY_FILE%" ( + echo Signing key file was found +) else ( + echo Signing key file was not found + echo ---- SIGNED GBL FILE GENERATION -------------------------------------- + echo To generate a signed firmware upgrade file, + echo copy a signing key file into the root folder of the project, + echo rename it to 'app-sign-key.pem' and rerun the script file. + echo ---------------------------------------------------------------------- + echo. +) + +echo ********************************************************************** +echo Converting .out to .gbl files +echo ********************************************************************** +echo. +echo .out file used: +echo %PATH_OUT% +echo. +echo output folder: +echo %PATH_GBL% + +if not exist %PATH_GBL% ( + mkdir %PATH_GBL% +) + +:: create the GBL files +echo. +echo ********************************************************************** +echo Creating %OTA_APPLO_NAME%.gbl for OTA +echo ********************************************************************** +echo. +%OBJCOPY% -O srec -j .text_apploader* "%PATH_OUT%" "%PATH_GBL%\%OTA_APPLO_NAME%.srec" +if errorlevel 1 ( + pause + goto:eof +) +if exist %BOOTLOADER_FILE% ( +echo Bootloader file was found +%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --bootloader %BOOTLOADER_FILE% +) else ( +%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" +) +echo. +echo ********************************************************************** +echo Creating %OTA_APPLI_NAME%.gbl for OTA +echo ********************************************************************** +echo. +%OBJCOPY% -O srec -R .text_apploader* -R .text_signature* "%PATH_OUT%" "%PATH_GBL%\%OTA_APPLI_NAME%.srec" +if errorlevel 1 ( + pause + goto:eof +) +%COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%.srec" + +:: create the full GBL files for UART DFU +echo. +echo ********************************************************************** +echo Creating %UARTDFU_FULL_NAME%.gbl for UART DFU +echo ********************************************************************** +echo. +%OBJCOPY% -O srec -R .text_bootloader* "%PATH_OUT%" "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" +if errorlevel 1 ( + pause + goto:eof +) +%COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" + +:: create encrypted GBL file for secure boot if encrypt-key file exist +if exist %GBL_ENCRYPT_KEY_FILE% ( + echo. + echo ********************************************************************** + echo Creating encrypted .gbl files + echo ********************************************************************** + echo. + if exist %BOOTLOADER_FILE% ( + echo Bootloader file was found + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --bootloader %BOOTLOADER_FILE% + ) else ( + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% + ) + echo. + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% + echo. + %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% +) + +:: create signed GBL file for secure boot if sign-key file exists +if exist %GBL_SIGING_KEY_FILE% ( + echo. + echo ********************************************************************** + echo Creating signed .gbl files + echo ********************************************************************** + echo. + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --secureboot --keyfile %GBL_SIGING_KEY_FILE% -o "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( + if exist %BOOTLOADER_FILE% ( + echo Bootloader file was found + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-signed.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% --bootloader %BOOTLOADER_FILE% + ) else ( + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-signed.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% + ) + ) + echo. + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --secureboot --keyfile %GBL_SIGING_KEY_FILE% -o "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-signed.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% + echo. + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" -o "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" + ) else ( + copy "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" >NUL + ) + %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" --sign %GBL_SIGING_KEY_FILE% + + :: create signed and encrypted GBL file for if both sign-key and encrypt-key file exist + if exist %GBL_ENCRYPT_KEY_FILE% ( + echo. + echo ********************************************************************** + echo Creating signed and encrypted .gbl files + echo ********************************************************************** + echo. + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" ( + if exist %BOOTLOADER_FILE% ( + echo Bootloader file was found + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% --bootloader %BOOTLOADER_FILE% + ) else ( + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% + ) + echo. + ) + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% + echo. + %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-signed.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --sign %GBL_SIGING_KEY_FILE% + ) +) else ( +echo. + echo ********************************************************************** + echo Creating crc .gbl files + echo ********************************************************************** + echo. + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%.srec" --crc -o "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( + if exist %BOOTLOADER_FILE% ( + echo Bootloader file was found + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-crc.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --bootloader %BOOTLOADER_FILE% + ) else ( + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-crc.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" + ) + + ) + echo. + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLI_NAME%.srec" --crc -o "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-crc.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" + echo. + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( + %COMMANDER% convert "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" -o "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" + ) else ( + copy "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" >NUL + ) + %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" + + :: create crc and encrypted GBL file if encrypt-key file exist + if exist %GBL_ENCRYPT_KEY_FILE% ( + echo. + echo ********************************************************************** + echo Creating crc and encrypted .gbl files + echo ********************************************************************** + echo. + if exist "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" ( + if exist %BOOTLOADER_FILE% ( + echo Bootloader file was found + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-bootloader-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% --bootloader %BOOTLOADER_FILE% + ) else ( + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLO_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLO_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% + ) + echo. + ) + %COMMANDER% gbl create "%PATH_GBL%\%OTA_APPLI_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%OTA_APPLI_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% + echo. + %COMMANDER% gbl create "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc-encrypted.gbl" --app "%PATH_GBL%\%UARTDFU_FULL_NAME%-crc.srec" --encrypt %GBL_ENCRYPT_KEY_FILE% + ) +) + +:: clean up output dir +del "%PATH_GBL%\*.srec" + +pause diff --git a/locator_ncp/create_bl_files.py b/locator_ncp/create_bl_files.py index 8b835d7..f1bdf65 100644 --- a/locator_ncp/create_bl_files.py +++ b/locator_ncp/create_bl_files.py @@ -1,1248 +1,1248 @@ -#!/usr/bin/env python3 -import sys -import os -import re -import subprocess -import shutil -import time -import argparse -import builtins -import tkinter as tk -from tkinter import filedialog as fd -from pathlib import Path -from glob import glob -from datetime import datetime as dt - -LOGO = " _____ _ _____ ______ _ __ _ _ \n" -LOGO += " / __ \ | | | __ \| ___ \ | / _(_) | \n" -LOGO += " | / \/_ __ ___ __ _| |_ ___ | | \/| |_/ / | | |_ _| | ___ ___ \n" -LOGO += " | | | '__/ _ \/ _` | __/ _ \ | | __ | ___ \ | | _| | |/ _ \/ __| \n" -LOGO += " | \__/\ | | __/ (_| | || __/ | |_\ \| |_/ / |____ | | | | | __/\__ \ \n" -LOGO += " \____/_| \___|\__,_|\__\___| \____/\____/\_____/ |_| |_|_|\___||___/ \n" - -# Configuration -INTERACTIVE = True -ALWAYS_SELECT_GCC_EXT = True -COMPRESS_GBLS = True -PURGE_SRECS = True -VERBOSE = False -OUTDIR = 'output_gbl' - -# Artifacts the script will looking for -BOOT_S1_F = 'bootloader-second-stage.s37' -BOOT_S2_F = 'bootloader-apploader.s37' -SIGN_N = 'app-sign' -SIGN_F = SIGN_N + '-key.pem' -ENCRYPT_N = 'app-encrypt' -ENCRYPT_F = ENCRYPT_N + '-key.txt' -# Output filenames without extensions -APPLO_N = 'apploader' -BOOTLO_N = 'bootloader' -APPLI_N = 'application' -UARTDFU_N = 'full' - -# ANSI terminal code -class ansi: - rd = '\033[0;31m' # red - gn = '\033[0;32m' # green - yl = '\033[0;33m' # yellow - pr = '\033[0;35m' # purple - cl = '\033[0m' # clear - prev_ln = '\x1b[F' # previous line (begin) - -# tips enumerator class to show to the user e.g. if some input file is missing or special config -# used for the generator -class tip: - BOOT = 0 - ENCRYPT = 1 - SIGN = 2 - COMPRESS = 3 - INTERACTIVE = 4 - -# enumerator class for print out levels to show -class lvl: - INFO = 0 # INFO - OKAY = 1 # OK - WARN = 2 # WARNING - ERR = 3 # ERROR - -# Operation switches -BOOT_EXIST = False -ENCRYPT_KEY_EXIST = False - -# Functions -def print(level, *args, **kwargs): - """Print function - - Override built in print function to display information in the following format (with colors): - [ OK ] Operation Finished. - - :param level: INFO, OK, WARNING or ERROR levels, see definition of lvl class - :type level: lvl enumerator class - """ - if level == lvl.INFO: - builtins.print(" " * 12, end="") - else: - builtins.print("[", end="") - if level == lvl.OKAY: - builtins.print(ansi.gn + " OK ", end="") - elif level == lvl.WARN: - builtins.print(ansi.yl + "WARNING ", end="") - elif level == lvl.ERR: - builtins.print(ansi.rd + " ERROR ", end="") - builtins.print(ansi.cl + "]: ", end="") - builtins.print(*args, **kwargs, flush=True) - - -def print_question(question, delay=0.5): - """Print question - - Print out a yes-or-no question in the terminal in the same format as print. - Default selection marked in uppercase and requires only to press Enter. - - :param question: the text of the yes-or-no question - :type question: str - :param delay: delay after the answer, defaults to 0.5 sec - :type delay: float, optional - :return: True if 'Y' is the answer, else False - :rtype: bool - """ - builtins.print("[" + ansi.pr + "QUESTION" + ansi.cl + "]: ", end='') - yorno = input(question + " [Y/n]:\n" + " " * 12) - if yorno.lower() == 'n': - # overwrites the previous line content: n --> No. - builtins.print(ansi.prev_ln + "\r" + " " * 12 + ansi.yl + "No." + ansi.cl) - time.sleep(delay) - return False - else: - # overwrites the previous line content: --> Yes. - builtins.print(ansi.prev_ln + "\r" + " " * 12 + ansi.gn + "Yes." + ansi.cl) - time.sleep(delay) - return True - - -def print_tip(t, delay=1.5): - """Prints out selected tip to the standard output - - :param t: selected tip to display - :type t: Literal - """ - offset = " " * 12 - if t == tip.BOOT: - msg = "Tip: to add bootloader to the apploader you have the following options:\n" + offset - msg += "Option 1:\n" + offset - msg += "- copy a bootloader image .s37 to the current working directory\n" + offset - if SERIES_1: - boot = BOOT_S1_F - else: - boot = BOOT_S2_F - msg += "- rename it to " + ansi.yl + f"{boot}" + ansi.cl + " and rerun this script\n" + offset - msg += "Option 2:\n" + offset - msg += "- rerun this script with "+ansi.yl+"-i"+ansi.cl+" argument to activate interactive mode\n" + offset - msg += "- when prompted select the desired bootloader .s37 image with a filedialog" - msg += "Option 3:\n" + offset - msg += "- rerun this script with "+ansi.yl+"-b"+ansi.cl+" argument and specify a direct path to\n" + offset - msg += " the selected bootloader .s37 file\n" + offset - msg += "Note: Series-2 devices support merged bootloaders a.k.a. bootloader-apploader.s37\n" + offset - msg += " for applications that are utilize in-place OTA DFU.\n" + offset - - elif t == tip.ENCRYPT or t == tip.SIGN: - if t == tip.ENCRYPT: - action = "encrypt" - key = action + "ion key .txt" - arg = "-k" - filename = ENCRYPT_F - else: - action = "sign" - key = action + "ature key .pem" - arg = "-s" - filename = SIGN_F - msg = f"Tip: to generate {action}ed GBL files you have the following options:\n" + offset - msg += "Option 1:\n" + offset - msg += f"- copy the {key} file to the current working directory\n" + offset - msg += "- rename it to " + ansi.yl + f"{filename}" + ansi.cl + " and rerun this script\n" + offset - msg += "Option 2:\n" + offset - msg += "- rerun this script with "+ansi.yl+"-i"+ansi.cl+" argument to activate interactive mode\n" + offset - msg += "- when prompted select the generation option to generate the key automatically\n" + offset - msg += "Option 3:\n" + offset - msg += "- rerun this script with "+ansi.yl+f"{arg}"+ansi.cl+" argument and specify a direct path to\n" + offset - msg += " the selected key file\n" + offset - - elif t == tip.COMPRESS: - cpx = ansi.yl + "support decompressing" + ansi.cl - msg = f"Compressed GBLs require a bootloader that {cpx} the GBL!" - elif t == tip.INTERACTIVE: - msg = ansi.pr + "INTERACTIVE MODE" + ansi.cl + " selected!\n" + offset - msg += "For missing tools or files a dialog will be shown to specify the absolute path to the tool\n" + offset - msg += "in console- or filedialogs, for "+ansi.yl+"keys"+ansi.cl+" the script will offer\n" + offset - msg += "the generation option.\n" + offset - msg += "If you want to run this script without any human interaction e.g. in automated environment\n" + offset - msg += "it is suggested to not use this mode!\n" + offset - msg += "Consult with the helper (-h or --help) for more" - print(lvl.INFO,msg) - time.sleep(delay) - - -def display_menu(elems_list, title): - """Display text-based menu - - Display text based menu for the user in the terminal. - The options in the displayed menu defined by the elem_list. - - The user shall select from 1st to last or press other keys to abort the selection. - - :param elems_list: list that will be taken as the options for the menu - :type elems_list: lst - :param title: title that will be displayed above the options - :type title: str - :return: selected element from the elems_list (as string) - :rtype: str - """ - print(lvl.INFO,title) - for i in range(0, len(elems_list)): - print(lvl.INFO,f"[{i+1}] ", str(elems_list[i])) - - message = f"Select one from above [ 1 - {len(elems_list)} ] and press Enter!\n" + " " * 12 - message += "To abort press any other key and press Enter!" - print(lvl.INFO,message) - try: - s = int(input(" " * 12)) - except (TypeError, ValueError): - s = 0 - - if s in range(1, len(elems_list)+1): - print(lvl.INFO,ansi.prev_ln + " " *12 + f"{str(s)} - \'{str(elems_list[s-1])}\'.") - return str(elems_list[s-1]) - print(lvl.INFO,f"Abort selection.") - return None - - -def interactive_menu(sep): - """Realize interactive menu to configure the generator - - Shows terminal-dialogs and displays terminal-menu in order to set all possible switches in - an interactive way. - The switches: - - sign GBLs (bool) - - encrypt GBLs (bool) - - compress GBLs (bool) - - compression method as string (lz4, lzma, both) - - generate UARTDFU GBLs (bool) - - :param sep: separator string that only used for display style - :type sep: str - :return: valid values for sign, encrypt, cpress, cpress_method, uartdfu - :rtype: bool, bool, bool, str, bool - """ - offset = " " * 12 - - print_tip(tip.INTERACTIVE) - print(lvl.INFO,sep) - print(lvl.INFO,"Select generation steps below ...") - print(lvl.INFO,sep) - - question = "Would you like to "+ ansi.yl + "sign" + ansi.cl + " your GBL files?\n" + offset - question += "Note: if you don't have .pem files this script will generate them\n" + offset - question += "for you later on if you want to." - sign = print_question(question) - - question = "Would you like to "+ ansi.yl + "encrypt" + ansi.cl + " your GBL files?\n" + offset - question += "Note: if you don't have an encryption key .txt this script will generate them\n" + offset - question += "for you later on if you want to." - encrypt = print_question(question) - - question = "Would you like to "+ ansi.yl + "compress" + ansi.cl + " your GBL files?\n" + offset - question += "Note: for compressed GBLs you have to use a bootloader that is capable to\n" + offset - question += ansi.yl + "decompress" + ansi.cl + " those images!" - cpress = print_question(question) - if cpress: - cpress_method = display_menu(['lz4', 'lzma', 'both'], "Select compression method!") - else: - cpress = False - cpress_method = "" - print(lvl.WARN, "Did not selected compression method!") - print(lvl.INFO, "Compression will be skipped!") - - uartdfu = print_question("Would you like to generate "+ ansi.yl + "UARTDFU" + ansi.cl + " GBL files?") - - print(lvl.INFO, sep) - print(lvl.INFO, "Setup finished:") - print(lvl.INFO, sep) - # "Sign | Encrypt | Compress | Compress method | UART DFU GBLs" - # " yes | no | yes | lzma | yes" - print(lvl.INFO, "Sign | Encrypt | Compress | Compress method | UART DFU GBLs") - print(lvl.INFO, f"{'yes ' if sign else 'no '}| {'yes ' if encrypt else 'no '}|", end="") - if cpress_method == "lz4": - cpress_method += " " - elif cpress_method == "": - cpress_method = "none" - builtins.print(f"{' yes ' if cpress else ' no '}| {cpress_method} |", end="") - builtins.print(f"{' yes' if uartdfu else ' no'}") - - return sign, encrypt, cpress, cpress_method, uartdfu - - -def detect_platform(): - """Detects host platform and returns with it - - :return: platform in lower letters string - :rtype: str - """ - platform = os.sys.platform.lower() - if platform == 'win32': - response = run_cmd(['uname'], True, verbose=VERBOSE) - if response is None: - return 'cmd' - elif re.search(r'is not recognized', response): - return 'cmd' - else: - match_result = re.search(r'MSYS_NT', response) - if match_result: - return 'msys' - match_result = re.search(r'MINGW', response) - if match_result: - return 'mingw' - match_result = re.search(r'CYGWIN_NT', response) - if match_result: - return 'cygwin' - else: - return platform - - -def run_cmd(command_list, supp_ex_disp=False, verbose=False): - """Execute terminal command - - Execute terminal command in a subprocess and return with the content of the standard error and - standard output if its not empty. - - :param command_list: terminal command as a list - :type command_list: lst - :param supp_ex_disp: suppress exception display, defaults to False - :type supp_ex_disp: bool, optional - :param verbose: verbosity enable, defaults to False - :type verbose: bool, optional - :return: in case not empty return with stderr or stdout content as utf-8 encoded string - :rtype: str - """ - if verbose: - print(lvl.INFO,"Call:") - print(lvl.INFO,"\'" + " ".join(command_list) + "\'") - try: - cmd_proc = subprocess.run(command_list, stdout=subprocess.PIPE, stderr=subprocess.PIPE) - except FileNotFoundError: - cmd_proc = subprocess.run(command_list, stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) - except Exception as ex: - if not supp_ex_disp: - print(lvl.ERR,ansi.rd + " ".join(command_list), ansi.cl + "could not be executed!") - print(lvl.INFO,"Exception:\n" + ansi.rd + str(ex) + ansi.cl) - return None - - err = cmd_proc.stderr.decode('utf-8') - out = cmd_proc.stdout.decode('utf-8') - - if err != "": - if not supp_ex_disp: - print(lvl.ERR,"Error during execution of \'" + " ".join(command_list)+"\'!") - print(lvl.INFO,"stderr:\n"+ansi.rd+err+ansi.cl) - return err - elif out != "": - return out - else: - return None - - -def reformat_path(path): - """Reformat path to forwardslash posix format - - Reformat path to posix format with forward slashes that is universally accepted by win & posix. - Also converting cygwin and msys paths to this format. - - :param path: original path - :type path: str - :return: reformatted path - :rtype: str - """ - path = path.replace('\r', '').replace('\n', '') - if PLATFORM == 'cygwin': - m: re.Match = re.match(r"^/cygdrive/(\w)/[\w\s\\/_\-\.]+$", path) - if m is not None: - path = re.sub(r"^/cygdrive/\w/", f"{m.group(1)}:/", path) - return str(Path(path).as_posix()) - else: - return str(Path(path).as_posix()) - elif PLATFORM == 'msys' or PLATFORM == 'mingw': - m: re.Match = re.match(r"^/(\w)/[\w\s\\/_\-\.]+$", path) - if m is not None: - path = re.sub(r"^/\w/", f"{m.group(1)}:/", path) - return str(Path(path).as_posix()) - else: - return str(Path(path).as_posix()) - else: - return str(Path(path).as_posix()) - - -def check_util_exist(util_name, env): - """Check wether the selected utility exist - - Check if the selected utility exists in the system PATH. - - :param util_name: name of the utility (without extension on windows) - :type util_name: str - :param env: environment variable - :type env: str - :return: absolute path to the utility if exists - :rtype: str - """ - if PLATFORM != 'cmd': - cmd = ['which'] - result_re = r'which: no' - else: - util_name += '.exe' - cmd = ['where'] - result_re = r'Could not find files' - cmd.append(util_name) - cmd_result = run_cmd(cmd, True, verbose=VERBOSE) - match_err = re.search(result_re, cmd_result) - if match_err: - if os.environ[env] is not None: - print(lvl.WARN,f"{util_name} not found in PATH!") - p = reformat_path(os.environ[env]) - for root, files in os.walk(p): - for f in files: - if f.endswith(util_name) and os.access(os.path.join(root, f), os.X_OK): - f = os.path.join(root, f) - p = reformat_path(f) - print(lvl.OKAY,"Using " + ansi.gn + f"{env}" + ansi.cl + f" instead: {p}") - return p - print(lvl.ERR, f"Could not find {util_name}!") - return None - else: - p = reformat_path(cmd_result) - print(lvl.OKAY, f"{util_name} detected: {p}") - return p - - -def get_file_list(path, extension): - """Get all files with the selected extension - - Get files with the selected extension in the selected path. - - :param path: path in which the search shall be done - :type path: str - :param extension: extension without a '.' - :type extension: str - :return: list of absolute filepaths with the selected extension - :rtype: lst - """ - file_list = [] - try: - for root, dirs, files in os.walk(path): - for file in files: - if file.endswith(extension): - file_list.append(os.path.join(root, file)) - except TypeError: - print(lvl.ERR,"Invalid path:" + ansi.rd + path + ansi.cl + "!") - return file_list - - -def is_target_series_1(build_artifact): - """Determine the target series - - Determine the target series based on the existing build artifact. - - :param build_artifact: absolute path the the build artifact - :type build_artifact: str - :return: True if its a Series-1 project, else False - :rtype: bool - """ - with open(build_artifact, 'r', errors='ignore') as app: - lines = app.readlines() - for line in lines: - if line.find('text_apploader') != -1: - return True - return False - - -def is_file_exist(path, suppress_ex=False): - """Check if the file exist - - Check path if its a file and it does exist. - If not, or any kind of exception occurs print out the exception and return with False. - Or return with True. - - :param path: path the the file - :type path: str - :param suppress_ex: _description_, defaults to False - :type suppress_ex: bool, optional - :return: True if the file exists, or False. - :rtype: bool - """ - try: - path = reformat_path(path) - return os.path.isfile(path) - except: - if path is None and not suppress_ex: - print(lvl.ERR, ansi.rd + "File does not exist!" + ansi.cl) - elif not suppress_ex: - print(lvl.ERR, ansi.rd + f"\'{path}\' does not exist!" + ansi.cl) - return False - - -def extract_to_srec(srec_name, remove_sections, out_path, only_section=False): - """Extract binary data to srec file - - Extract binary data with arm-eabi-objcopy into an .srec file for further usage. - If the only_section flag set, only the sections in the remove_sections input parameter will remain. - With this flag the complementer action of the original will be done. - - :param srec_name: name of the srec file (without extension) - :type srec_name: str - :param remove_sections: list of the .sections that has to be removed - :type remove_sections: lst - :param out_path: output path where the .srec file will be saved - :type out_path: str - :param only_section: copy only the sections mentioned in remove_sections, defaults to False - :type only_section: bool, optional - :return: path to the .srec file - :rtype: str - """ - srec_file = reformat_path(os.path.join(OUTDIR, srec_name + '.srec')) - cmd = [OBJCOPY, '-O', 'srec'] - for sect in remove_sections: - if only_section: - cmd.extend(['-j', sect]) - else: - cmd.extend(['-R', sect]) - cmd.extend([out_path, srec_file]) - response = run_cmd(cmd, verbose=VERBOSE) - if response is None and os.path.isfile(srec_file): - print(lvl.INFO, srec_file + " extracted.") - return srec_file - else: - print(lvl.WARN, "Could not extract \'"+" ,".join(sect) + "\' sections from"+out_path+"!") - return None - - -def convert_srec(srec_list, srec_out_name, signature=None, with_crc=False): - """Converter function that converts and/or merges srec file(s) into new srec. - - Merge a list of srec files into one. - Optionally converts unprotected srec files to crc-protected srec or signed srec files. - These two types required to generate crc-protected or signed GBLs. - - :param srec_list: list of the input .srec filepaths that has to be merged - :type srec_list: str list - :param srec_out_name: the name of the output .srec file (without extension) - :type srec_out_name: str - :param signature: signature .pem filepath, defaults to None - :type signature: str, optional - :param with_crc: enable crc32 protect for output .srec, defaults to False - :type with_crc: bool, optional - :return: output .srec filepath - :rtype: str - """ - srec_out = reformat_path(os.path.join(OUTDIR, srec_out_name)) - cmd = [COMMANDER, 'convert'] - for sr in srec_list: - cmd.append(sr) - if with_crc: - srec_out += '-crc' - cmd.append('--crc') - if signature is not None: - srec_out += '-signed' - cmd.extend(['--secureboot', '--keyfile', signature]) - srec_out += '.srec' - cmd.extend(['-o', srec_out]) - response = run_cmd(cmd, verbose=VERBOSE) - match_res = re.search(r'Writing to', response) - if match_res and is_file_exist(srec_out): - print(lvl.INFO, " ".join(srec_list) + " converted to " + srec_out) - return srec_out - else: - print(lvl.WARN, "Could not convert " + " ".join(srec_list) + " to " + srec_out) - print(lvl.INFO, "command response:", response) - return None - - -def convert_srec_uartdfu(srec_list, srec_out_name): - """Merge .srec files specialized for UARTDFU GBLs - - Convert/merge .srec file(s) for specialized UARTDFU GBLs. - - :param srec_list: list of input .srec filepaths - :type srec_list: str list - :param srec_out_name: name of the output .srec file (without extension) - :type srec_out_name: str - :return: output .srec - :rtype: str - """ - if len(srec_list) == 2: - applo_srec = srec_list[0] - app_srec = srec_list[1] - if is_file_exist(applo_srec) and is_file_exist(app_srec): - out_srec = convert_srec([applo_srec, app_srec], srec_out_name) - if is_file_exist(out_srec): - print(lvl.OKAY, f"{applo_srec} and {app_srec} converted to {out_srec}.") - return out_srec - else: - print(lvl.WARN, f"Failed to convert {applo_srec} and {app_srec} to {out_srec}!") - return None - elif not is_file_exist(applo_srec) and is_file_exist(app_srec): - out_srec = reformat_path(os.path.join(OUTDIR, srec_out_name + '.srec')) - try: - shutil.copy(app_srec, out_srec) - print(lvl.OKAY, f"{app_srec} converted to {out_srec}.") - return out_srec - except shutil.SameFileError: - print(lvl.ERR, "Source and destination files are the same! Aborting.") - except PermissionError: - print(lvl.ERR, "Permission denied!") - except Exception as ex: - print(lvl.ERR, f"Exception occurred during execution of shutil.copy()!") - print(lvl.ERR, f"{ex}\n") - return None - else: - print(lvl.INFO, "Invalid .srec file list! None of the record contains actual files!") - return None - else: - print(lvl.WARN, "Failed to convert srec files! At least 2 srecs required!") - return None - - -def key_gen(key_name, encrypt_type='aes-ccm'): - """Encryption/signature key generator function - - Generate encryption or signature keys with the selected encryption methods. - To generate encrypt key, use 'ecc-p256' - To generate signature keys, use the default 'aes-ccm' - - :param key_name: name of the output key (without extension) - :type key_name: str - :param encrypt_type: encryption method, defaults to 'aes-ccm' - :type encrypt_type: str, optional - :return: True in case of successful key generation, False otherwise - :rtype: bool - """ - REGEX_GENKEY = r'Using .* generation.*DONE' - cmd = [COMMANDER, 'util', 'genkey', '--type'] - key_pf = '-key.txt' - if encrypt_type != 'aes-ccm': - REGEX_GENKEY = r'Writing private key.*DONE' - encrypt_type = 'ecc-p256' - key_pf = '-key.pem' - pkey_pf = '-pubkey.pem' - print(lvl.INFO,"Generate signature keys ...") - cmd.extend([encrypt_type, '--privkey', key_name + key_pf, '--pubkey', key_name + pkey_pf]) - else: - print(lvl.INFO,"Generate encryption key ...") - cmd.extend([encrypt_type, '--outfile', key_name + key_pf]) - - r = run_cmd(cmd, verbose=VERBOSE) - match_r = re.search(REGEX_GENKEY, r, flags=re.DOTALL) - if match_r and is_file_exist(key_name + key_pf): - print(lvl.OKAY, ansi.gn + f"{key_name+key_pf}" + ansi.cl + " generated.") - return True - elif match_r and is_file_exist(key_name + key_pf) and is_file_exist(key_name + pkey_pf): - print(lvl.OKAY,f"{key_name+key_pf}, {key_name+pkey_pf}.") - return True - else: - print(lvl.WARN,"Could not generate key!") - return False - - -def create_gbl_file(gbl_name, app_data, app_encrypt=None, app_sign=None, boot=None, cpress_a='', crc=False): - """Create GBL file function - - Builds up and initiates GBL generator command for simplicity commander based on the input parameters. - It is capable of the generation of: signed, encrypted, compressed and crc-protected GBL files. - - - :param gbl_name: Base name of the output gbl file (without extension), postfixes will be added automatically: - signed, encrypted versions will get -signed and/or -encrypted postfixes etc. - :type gbl_name: str - :param app_data: application data filepath (.srec or .gbl) - :type app_data: str - :param app_encrypt: encrypt-key filepath, defaults to None - :type app_encrypt: str, optional - :param app_sign: signature-key filepath, defaults to None - :type app_sign: str, optional - :param boot: bootloader image filepath, defaults to None - :type boot: str, optional - :param cpress_a: compression algorithm {lz4, lzma}, defaults to '' - :type cpress_a: str, optional - :param crc: generate protected GBL files with crc32 as well, defaults to False - :type crc: bool, optional - :return: filepath to the output gbl file or None in case of errors - :rtype: str - """ - if app_data is None and boot is None: - print(lvl.ERR,"Could not find " + app_data + "! Aborting GBL generation!") - return None - cmd = [COMMANDER, 'gbl', 'create'] - - if app_data is not None: - cmd.extend(['--app', app_data]) - if app_sign is not None: - gbl_name += '-signed' - cmd.extend(['--sign', app_sign]) - if app_encrypt is not None: - gbl_name += '-encrypted' - cmd.extend(['--encrypt', app_encrypt]) - if crc: - gbl_name += '-crc' - if boot is not None: - cmd.extend(['--bootloader', boot]) - if cpress_a in ('lz4', 'lzma'): - gbl_name += '-' + cpress_a - cmd.extend(['--compress', cpress_a]) - gbl_name += '.gbl' - gbl_file = reformat_path(os.path.join(OUTDIR, gbl_name)) - cmd.insert(3, gbl_file) - - if is_file_exist(gbl_file): - print(lvl.WARN, ansi.yl + f"{gbl_name}" + ansi.cl + " already exists!") - backup_text = '_bkp' + dt.now().strftime("%Y-%m-%d-%H-%M-%S") - os.rename(reformat_path(os.path.join(OUTDIR, gbl_name)), - reformat_path(os.path.join(OUTDIR, gbl_name + backup_text))) - print(lvl.INFO, f"{gbl_name} renamed to {gbl_name + backup_text}.") - gbl_name = "New " + ansi.gn + gbl_name + ansi.cl - else: - gbl_name = ansi.gn + gbl_name + ansi.cl - - response = run_cmd(cmd, verbose=VERBOSE) - match_res = re.search(r'Writing GBL file', response) - if match_res: - print(lvl.OKAY, gbl_name + " generated.\n") - return gbl_file - else: - return None - - -def generate_gbls(name, srec, s1=True, boot_img=None, encrypt_k=None, sign_k=None, - cpress=True, cpress_m='both', uartdfu=False): - """Generate multiple GBL files - - Generate all GBL files that can be generated based on the input parameters. - It also differentiate between Series-1 and Series-2 devices. - Apploader GBLs for example can only be used for Series-1 devices! - - :param name: base name for the GBL files - :type name: str - :param srec: application data .srec - :type srec: str - :param s1: Series-1 mode, defaults to True - :type s1: bool, optional - :param boot_img: path to the boot image .s37, defaults to None - :type boot_img: str, optional - :param encrypt_k: path to the encrypt key .txt, defaults to None - :type encrypt_k: str, optional - :param sign_k: path to the signature key .pem, defaults to None - :type sign_k: str, optional - :param cpress: generate compressed GBLs as well, defaults to True - :type cpress: bool, optional - :param cpress_m: compression method {'lz4', 'lzma', 'both'}, defaults to 'both' - :type cpress_m: str, optional - :param uartdfu: generate UARTDFU GBLs as well, defaults to False - :type uartdfu: bool, optional - """ - if uartdfu: - # full.gbl - create_gbl_file(name, srec) - if cpress: - if cpress_m in ('lz4', 'both'): - # full-lz4.gbl - create_gbl_file(name, srec, cpress_a='lz4') - if cpress_m in ('lzma', 'both'): - # full-lzma.gbl - create_gbl_file(name, srec, cpress_a='lzma') - - if is_file_exist(encrypt_k): - # full-encrypted.gbl - create_gbl_file(name, srec, app_encrypt=encrypt_k) - if cpress: - if cpress_m in ('lz4', 'both'): - # full-encrypted-lz4.gbl - create_gbl_file(name, srec, app_encrypt=encrypt_k, cpress_a='lz4') - if cpress_m in ('lzma', 'both'): - # full-encrypted-lzma.gbl - create_gbl_file(name, srec, app_encrypt=encrypt_k, cpress_a='lzma') - - apploader_srec = reformat_path(os.path.join(OUTDIR, APPLO_N + '-crc.srec')) - app_srec = reformat_path(os.path.join(OUTDIR, APPLI_N + '-crc.srec')) - - srec_crc = convert_srec_uartdfu([apploader_srec, app_srec], name + '-crc') - if not is_file_exist(srec_crc): - print(lvl.WARN,f"Skipping {name}-crc.gbl generation!\n") - else: - # full-crc.gbl - create_gbl_file(name, srec_crc, crc=True) - - apploader_s_srec = reformat_path(os.path.join(OUTDIR, APPLO_N + '-signed.srec')) - app_s_srec = reformat_path(os.path.join(OUTDIR, APPLI_N + '-signed.srec')) - - srec_signed = convert_srec_uartdfu([apploader_s_srec, app_s_srec], name + '-signed') - if srec_signed is None or not is_file_exist(srec_signed): - print(lvl.WARN,f"Skipping {name}-signed.gbl generation!\n") - else: - # full-signed.gbl - create_gbl_file(name, srec_signed, app_sign=sign_k) - if is_file_exist(encrypt_k): - # full-signed-encrypted.gbl - create_gbl_file(name, srec_signed, app_encrypt=encrypt_k, app_sign=sign_k) - - else: - if srec is None and not s1: - if is_file_exist(boot_img, suppress_ex=True): - # bootloader.gbl - create_gbl_file(name, None, boot=boot_img) - else: - print(lvl.WARN, f"Missing bootloader image: {boot_img}!") - else: - srec_crc = convert_srec([srec], name, with_crc=True) - if is_file_exist(boot_img, suppress_ex=True): - if is_file_exist(sign_k, suppress_ex=True): - srec_signed = convert_srec([srec], name + '-bootloader', signature=sign_k) - if is_file_exist(encrypt_k, suppress_ex=True): - # appl*-bootloader-signed-encrypted.gbl - create_gbl_file(name + '-bootloader', srec_signed, app_encrypt=encrypt_k, - app_sign=sign_k, boot=boot_img) - # appl*-bootloader-signed.gbl - create_gbl_file(name + '-bootloader', srec_signed, app_sign=sign_k, boot=boot_img) - - if is_file_exist(encrypt_k, suppress_ex=True): - # appl*-bootloader-encrypted.gbl - create_gbl_file(name + '-bootloader', srec, app_encrypt=encrypt_k, boot=boot_img) - # appl*-bootloader-encrypted-crc.gbl - create_gbl_file(name + '-bootloader', srec_crc, app_encrypt=encrypt_k, boot=boot_img, crc=True) - if cpress: - if cpress_m in ('lz4', 'both'): - # appl*-bootloader-encrypted-lz4.gbl - create_gbl_file(name + '-bootloader', srec, cpress_a='lz4', - app_encrypt=encrypt_k, boot=boot_img) - if cpress_m in ('lzma', 'both'): - # appl*-bootloader-encrypted-lzma.gbl - create_gbl_file(name + '-bootloader', srec, cpress_a='lzma', - app_encrypt=encrypt_k, boot=boot_img) - # appl*-bootloader.gbl - create_gbl_file(name + '-bootloader', srec, boot=boot_img) - # appl*-bootloader-crc.gbl - create_gbl_file(name + '-bootloader', srec_crc, boot=boot_img, crc=True) - if cpress: - if cpress_m in ('lz4', 'both'): - # appl*-bootloader-lz4.gbl - create_gbl_file(name + '-bootloader', srec, cpress_a='lz4', boot=boot_img) - if cpress_m in ('lzma', 'both'): - # appl*-bootloader-lzma.gbl - create_gbl_file(name + '-bootloader', srec, cpress_a='lzma', boot=boot_img) - - if is_file_exist(sign_k, suppress_ex=True): - srec_signed = convert_srec([srec], name, signature=sign_k) - if is_file_exist(encrypt_k, suppress_ex=True): - # appl*-signed-encrypted.gbl - create_gbl_file(name, srec_signed, app_encrypt=encrypt_k, app_sign=sign_k) - # appl*-signed.gbl - create_gbl_file(name, srec_signed, app_sign=sign_k) - - if is_file_exist(encrypt_k, suppress_ex=True): - # appl*-encrypted.gbl - create_gbl_file(name, srec, app_encrypt=encrypt_k) - # appl*-encrypted-crc.gbl - create_gbl_file(name, srec_crc, app_encrypt=encrypt_k, crc=True) - if cpress: - if cpress_m in ('lz4', 'both'): - # appl*-encrypted-lz4.gbl - create_gbl_file(name, srec, cpress_a='lz4', app_encrypt=encrypt_k) - if cpress_m in ('lzma', 'both'): - # appl*-encrypted-lzma.gbl - create_gbl_file(name, srec, cpress_a='lzma', app_encrypt=encrypt_k) - # appl*.gbl - create_gbl_file(name, srec) - # appl*-crc.gbl - create_gbl_file(name, srec_crc, crc=True) - if cpress: - if cpress_m in ('lz4', 'both'): - # appl*-lz4.gbl - create_gbl_file(name, srec, cpress_a='lz4') - if cpress_m in ('lzma', 'both'): - # appl*-lzma.gbl - create_gbl_file(name, srec, cpress_a='lzma') - -def main(): - # Platform - global PLATFORM - - # Utility paths - global COMMANDER - global OBJCOPY - - global OUTDIR - - # .axf or .out file to generate from - global PRJ_ARTIFACT - global SERIES_1 - - global BOOT_S1_F - global BOOT_S2_F - - SIGN_KEY_EXIST = False - - # file globals - global SIGN_F - global ENCRYPT_F - - # these flags define the generator phases - # it comes from either command arguments or from the interactive mode - SIGN = False - ENCRYPT = False - CPRESS = False - CPRESS_METHOD = "lzma" - UARTDFU = False - - separator = "-" * 80 - delay_display = 0.5 - - # Before any work check the Python version ... - if sys.version_info < (3, 6, 0): - sys.stderr.write("ERROR: you need at least Python v3.6.0 to run this script!\n") - sys.exit(1) - - builtins.print(LOGO) - # Workaround for cmd.exe color codes - without this the bare-codes are visible only. - os.system("") - - # Argument parse - parser = argparse.ArgumentParser( - prog="create_bl_files.py", description=f"Create Gecko Bootloader Files") - # arguments - parser.add_argument("-o", "--outdir", dest="outdir", type=str, help="output directory for the generated files", - metavar="DIRECTORY") - parser.add_argument("-w", "--overwrite", dest="overwrite_old", action="store_true", help="Overwrite existing GBLs") - parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", - help="ignore args and give choices to the user") - parser.add_argument("-k", "--key", dest="encryption_key", help="encryption key .txt", metavar="FILE", - type=argparse.FileType('r', encoding='UTF-8')) - parser.add_argument("-b", "--boot", dest="boot_img", help="bootloader.s37 file", metavar="FILE", - type=argparse.FileType('r', encoding='UTF-8')) - parser.add_argument("-s", "--signature", dest="signature_key", help="signature key .pem", metavar="FILE", - type=argparse.FileType('r', encoding='UTF-8')) - parser.add_argument("-a", "--all", dest="all", action="store_true", help="create every possible GBL files") - parser.add_argument("-u", "--uartdfu", dest="uartdfu", action="store_true", help="create GBLs for UART DFU") - parser.add_argument("-cpr", "--compress", dest="compress", choices=["lz4", "lzma", "both"], - help="Compress GBLs with the chosen method") - args = parser.parse_args() - - if args.outdir is not None and os.path.isdir(args.outdir): - OUTDIR = reformat_path(args.outdir) - print(lvl.OKAY, "Custom output directory set to " + ansi.yl + f"{OUTDIR}"+ ansi.cl + ".") - else: - if not os.path.isdir(OUTDIR): - os.makedirs(OUTDIR) - print(lvl.OKAY,f"Create {OUTDIR} directory.") - else: - print(lvl.OKAY,f"Directory {OUTDIR} already exists.") - - # reformat paths to the input files - if args.encryption_key is not None: - args.encryption_key = reformat_path(args.encryption_key) - if args.boot_img is not None: - args.boot_img = reformat_path(args.boot_img) - if args.signature_key is not None: - args.signature_key = reformat_path(args.signature_key) - - # Environment - print(lvl.INFO,separator) - print(lvl.INFO,"Check environment ...") - print(lvl.INFO,separator) - time.sleep(delay_display) - - PLATFORM = detect_platform() - print(lvl.INFO,"Detected platform: " + ansi.yl + PLATFORM + ansi.cl) - - res = check_util_exist('commander', 'PATH_SCMD') - if res is not None: - COMMANDER = res - else: - sys.exit(1) - - res = check_util_exist('arm-none-eabi-objcopy', 'PATH_GCCARM') - if res is not None: - OBJCOPY = res - else: - sys.exit(1) - - builtins.print("") - print(lvl.INFO,separator) - print(lvl.INFO,"Check input files ...") - print(lvl.INFO,separator) - time.sleep(delay_display) - - axf = get_file_list(os.getcwd(), '.axf') - out = get_file_list(os.getcwd(), '.out') - - artifacts_num = len(axf) + len(out) - if artifacts_num > 1: - print(lvl.WARN,f"Multiple build artifacts detected ({artifacts_num})!") - if ALWAYS_SELECT_GCC_EXT: - PRJ_ARTIFACT = reformat_path(axf[0]) - else: - PRJ_ARTIFACT = reformat_path(out[0]) - print(lvl.WARN,f"Build artifact selected: {PRJ_ARTIFACT}") - print(lvl.INFO,"Choose which to select automatically by changing the value of \'ALWAYS_SELECT_GCC_EXT\'!\n") - elif artifacts_num == 1: - if len(axf) != 0: - PRJ_ARTIFACT = reformat_path(axf[0]) - if len(out) != 0: - PRJ_ARTIFACT = reformat_path(out[0]) - print(lvl.OKAY,f"Build artifact selected: {PRJ_ARTIFACT}") - else: - print(lvl.ERR,"Neither *.axf or *.out build artifacts found!") - print(lvl.INFO,ansi.yl+"Project built successfully before running this script?\n"+ansi.cl) - sys.exit(1) - - if args.interactive == True: - SIGN, ENCRYPT, CPRESS, CPRESS_METHOD, UARTDFU = interactive_menu(separator) - elif args.interactive == False: - if all(v is None or v == False for v in vars(args).values()): - print(lvl.WARN, "No argument specified, using " + ansi.yl + "--all" + ansi.cl + " meaning:") - AUTO_KEYGEN = True - SIGN = True - ENCRYPT = True - CPRESS = True - CPRESS_METHOD = "both" - UARTDFU = True - msg = ansi.yl + "ALL FEATURES ENABLED" + ansi.cl + ": " - msg += "sign, encrypt, compress and generate UARTDFU GBLs too." - print(lvl.WARN, msg) - print(lvl.INFO, "Missing keys will be "+ansi.yl+"automatically "+ansi.cl+"generated!") - time.sleep(delay_display) - - if args.all: - SIGN = True - ENCRYPT = True - CPRESS = True - CPRESS_METHOD = "both" - UARTDFU = True - msg = ansi.yl + "ALL FEATURES ENABLED" + ansi.cl + ": " - msg += "sign, encrypt, compress and generate UARTDFU GBLs too." - print(lvl.WARN, msg) - print(lvl.INFO, "Missing keys will be automatically generated!") - time.sleep(delay_display) - else: - if args.signature_key: - SIGN = True - if args.encryption_key: - ENCRYPT = True - if args.compress in ("lz4", "lzma", "both"): - CPRESS = True - CPRESS_METHOD = args.compress - if args.uartdfu: - UARTDFU = True - - time.sleep(delay_display) - - builtins.print("") - print(lvl.INFO,separator) - print(lvl.INFO,"Check bootloader image ...") - print(lvl.INFO,separator) - time.sleep(delay_display) - - print(lvl.OKAY,"Target device: ", end='') - SERIES_1 = is_target_series_1(PRJ_ARTIFACT) - if SERIES_1: - builtins.print(ansi.gn + "Series-1\n" + ansi.cl) - else: - builtins.print(ansi.gn + "Series-2\n" + ansi.cl) - - if args.boot_img is not None: - BOOT_EXIST = is_file_exist(args.boot_img) - print(lvl.OKAY,f"Bootloader image added as argument: {args.boot_img}") - if SERIES_1: - BOOT_S1_F = args.boot_img - else: - BOOT_S2_F = args.boot_img - elif args.interactive: - print(lvl.INFO,"Display filedialog ...") - root = tk.Tk() - root.withdraw() - if SERIES_1: - w_title = "Select Series-1 bootloader .s37" - else: - w_title = "Select Series-2 bootloader .s37" - boot_path = fd.askopenfile(initialdir=os.getcwd(), title=w_title) - BOOT_EXIST = is_file_exist(boot_path.name, suppress_ex=True) - if BOOT_EXIST: - if SERIES_1: - BOOT_S1_F = boot_path.name - else: - BOOT_S2_F = boot_path.name - print(lvl.OKAY,"Selected a valid bootloader .s37 image.") - else: - print(lvl.ERR,"Invalid file has been selected as bootloader image!") - else: - print(lvl.INFO,"No boot image in command argument.") - print(lvl.INFO,"Check current working directory ...\n") - if SERIES_1: - BOOT_EXIST = is_file_exist(BOOT_S1_F) - else: - BOOT_EXIST = is_file_exist(BOOT_S2_F) - - # show the compression related tip only in case all features shall be used or compression selected - # according to the command-arguments, and interactive mode is not active - if (args.all or args.compress in ("lzma", "lz4", "both")) and not args.interactive: - print_tip(tip.COMPRESS) - - # if can not recognize bootloader, print out the tip on how to use it if interactive mode is not active - if not BOOT_EXIST: - BOOT_S1_F = None - BOOT_S2_F = None - print(lvl.INFO,"Bootloader addition will be skipped!\n") - if not args.interactive: - print_tip(tip.BOOT) - else: - print(lvl.OKAY,"Bootloader image detected.\n") - time.sleep(delay_display) - - if SIGN: - builtins.print("") - print(lvl.INFO,separator) - print(lvl.INFO,"Check prerequisites for signed GBL generation ...") - print(lvl.INFO,separator) - time.sleep(delay_display) - - if args.signature_key is not None: - SIGN_KEY_EXIST = is_file_exist(args.signature_key) - if SIGN_KEY_EXIST: - print(lvl.OKAY,f"Signature key added as argument: {args.signature_key}") - SIGN_F = args.signature_key - else: - print(lvl.WARN, f"Invalid signature key in command argument: {args.signature_key}!") - print(lvl.INFO, "Check current working directory ...") - SIGN_KEY_EXIST = is_file_exist(SIGN_F) - else: - print(lvl.INFO, f"No signature key in command argument.") - print(lvl.INFO, "Check current working directory ...") - SIGN_KEY_EXIST = is_file_exist(SIGN_F) - - if not SIGN_KEY_EXIST: - print(lvl.WARN,f"Could not detect {SIGN_F}!") - if args.interactive: - decision = print_question(f"Would you like to generate {SIGN_F} now?", delay=delay_display) - if not decision: - SIGN_F = None - print(lvl.WARN,f"Will not generate {SIGN_F}!") - print(lvl.INFO,"Application signing will be skipped!\n") - time.sleep(delay_display) - else: - time.sleep(delay_display) - # in this case the gbl generator function will check wether the key_gen really generated - # a valid signature key or not - SIGN_KEY_EXIST = key_gen(SIGN_N, encrypt_type='ecc-p256') - elif args.all or AUTO_KEYGEN: - # generate the signature keys automatically - SIGN_KEY_EXIST = key_gen(SIGN_N, encrypt_type='ecc-p256') - else: - print(lvl.WARN,f"Could not detect {SIGN_F}!") - print(lvl.INFO,"Application signing will be skipped!\n") - print_tip(tip.SIGN) - SIGN_F = None - else: - print(lvl.OKAY,f"Detected {SIGN_F}.") - else: - SIGN_F = None - - if ENCRYPT: - builtins.print("") - print(lvl.INFO,separator) - print(lvl.INFO,"Check prerequisites for encrypted GBL generation ...") - print(lvl.INFO,separator) - time.sleep(delay_display) - - ENCRYPT_KEY_EXIST = is_file_exist(ENCRYPT_F) - if not ENCRYPT_KEY_EXIST: - print(lvl.WARN,f"Could not detect {ENCRYPT_F}!") - if args.interactive: - decision = print_question(f"Would you like to generate {ENCRYPT_F} now?", delay=delay_display) - if not decision: - ENCRYPT_F = None - print(lvl.WARN,f"Will not generate {ENCRYPT_F}!") - print(lvl.INFO,"Application encryption will be skipped!\n") - time.sleep(delay_display) - else: - time.sleep(delay_display) - # in this case the gbl generator function will check wether the key_gen really generated - # a valid encryption key or not - ENCRYPT_KEY_EXIST = key_gen(ENCRYPT_N) - elif args.all or AUTO_KEYGEN: - # generate the encryption key automatically - ENCRYPT_KEY_EXIST = key_gen(ENCRYPT_N) - else: - print(lvl.WARN,f"Could not detect {ENCRYPT_F}! Application signing will be skipped!") - print_tip(tip.ENCRYPT) - ENCRYPT_F = None - else: - print(lvl.OKAY,f"Detected {ENCRYPT_F}.") - else: - ENCRYPT_F = None - - if SERIES_1: - builtins.print("") - print(lvl.INFO, separator) - print(lvl.INFO, "Generate apploader GBLs ...") - print(lvl.INFO, separator) - time.sleep(delay_display) - applo_srec = extract_to_srec(APPLO_N, ['.text_apploader*'], PRJ_ARTIFACT, only_section=True) - generate_gbls(APPLO_N, applo_srec, boot_img=BOOT_S1_F, encrypt_k=ENCRYPT_F, sign_k=SIGN_F) - else: - if BOOT_EXIST: - builtins.print("") - print(lvl.INFO, separator) - print(lvl.INFO, "Generate bootloader GBL ...") - print(lvl.INFO, separator) - time.sleep(delay_display) - generate_gbls(BOOTLO_N, None, s1=False, boot_img=BOOT_S2_F, cpress=False) - - builtins.print("") - print(lvl.INFO, separator) - print(lvl.INFO, "Generate application GBLs ...") - print(lvl.INFO, separator) - time.sleep(delay_display) - - # extract all sections except the .text_apploader* and .text_signature* - app_srec = extract_to_srec(APPLI_N, ['.text_apploader*', '.text_signature*'], PRJ_ARTIFACT) - if app_srec is not None: - if SERIES_1: - generate_gbls(APPLI_N, app_srec, boot_img=BOOT_S1_F, encrypt_k=ENCRYPT_F, sign_k=SIGN_F, - cpress=CPRESS, cpress_m=CPRESS_METHOD) - else: - generate_gbls(APPLI_N, app_srec, s1=False, boot_img=BOOT_S2_F, encrypt_k=ENCRYPT_F, - sign_k=SIGN_F, cpress=CPRESS, cpress_m=CPRESS_METHOD) - else: - print(lvl.ERR, f"Could not create {APPLI_N}.srec!") - print(lvl.ERR, "Exit program.") - sys.exit(1) - - if UARTDFU: - # for UART DFU compatible GBL extract every section except the .text_bootloader section into an srec - uartdfu_srec = extract_to_srec(UARTDFU_N, ['.text_bootloader*'], PRJ_ARTIFACT) - # generate UART DFU GBLs - generate_gbls(UARTDFU_N, uartdfu_srec, encrypt_k=ENCRYPT_F, sign_k=SIGN_F, cpress=CPRESS, - cpress_m=CPRESS_METHOD, uartdfu=True) - - if PURGE_SRECS: - builtins.print("") - print(lvl.INFO,separator) - print(lvl.INFO,"Erase all temporary srec files ...") - print(lvl.INFO,separator) - print(lvl.INFO,"Note: set \'PURGE_SRECS\' to False to keep these files.") - time.sleep(delay_display) - files_to_erase = glob(OUTDIR + '/*.srec') - for file in files_to_erase: - try: - os.remove(file) - except: - print(lvl.WARN,f"Could not erase {file}!") - print(lvl.INFO,"Finished.") - - -if __name__ == "__main__": - main() +#!/usr/bin/env python3 +import sys +import os +import re +import subprocess +import shutil +import time +import argparse +import builtins +import tkinter as tk +from tkinter import filedialog as fd +from pathlib import Path +from glob import glob +from datetime import datetime as dt + +LOGO = " _____ _ _____ ______ _ __ _ _ \n" +LOGO += " / __ \ | | | __ \| ___ \ | / _(_) | \n" +LOGO += " | / \/_ __ ___ __ _| |_ ___ | | \/| |_/ / | | |_ _| | ___ ___ \n" +LOGO += " | | | '__/ _ \/ _` | __/ _ \ | | __ | ___ \ | | _| | |/ _ \/ __| \n" +LOGO += " | \__/\ | | __/ (_| | || __/ | |_\ \| |_/ / |____ | | | | | __/\__ \ \n" +LOGO += " \____/_| \___|\__,_|\__\___| \____/\____/\_____/ |_| |_|_|\___||___/ \n" + +# Configuration +INTERACTIVE = True +ALWAYS_SELECT_GCC_EXT = True +COMPRESS_GBLS = True +PURGE_SRECS = True +VERBOSE = False +OUTDIR = 'output_gbl' + +# Artifacts the script will looking for +BOOT_S1_F = 'bootloader-second-stage.s37' +BOOT_S2_F = 'bootloader-apploader.s37' +SIGN_N = 'app-sign' +SIGN_F = SIGN_N + '-key.pem' +ENCRYPT_N = 'app-encrypt' +ENCRYPT_F = ENCRYPT_N + '-key.txt' +# Output filenames without extensions +APPLO_N = 'apploader' +BOOTLO_N = 'bootloader' +APPLI_N = 'application' +UARTDFU_N = 'full' + +# ANSI terminal code +class ansi: + rd = '\033[0;31m' # red + gn = '\033[0;32m' # green + yl = '\033[0;33m' # yellow + pr = '\033[0;35m' # purple + cl = '\033[0m' # clear + prev_ln = '\x1b[F' # previous line (begin) + +# tips enumerator class to show to the user e.g. if some input file is missing or special config +# used for the generator +class tip: + BOOT = 0 + ENCRYPT = 1 + SIGN = 2 + COMPRESS = 3 + INTERACTIVE = 4 + +# enumerator class for print out levels to show +class lvl: + INFO = 0 # INFO + OKAY = 1 # OK + WARN = 2 # WARNING + ERR = 3 # ERROR + +# Operation switches +BOOT_EXIST = False +ENCRYPT_KEY_EXIST = False + +# Functions +def print(level, *args, **kwargs): + """Print function + + Override built in print function to display information in the following format (with colors): + [ OK ] Operation Finished. + + :param level: INFO, OK, WARNING or ERROR levels, see definition of lvl class + :type level: lvl enumerator class + """ + if level == lvl.INFO: + builtins.print(" " * 12, end="") + else: + builtins.print("[", end="") + if level == lvl.OKAY: + builtins.print(ansi.gn + " OK ", end="") + elif level == lvl.WARN: + builtins.print(ansi.yl + "WARNING ", end="") + elif level == lvl.ERR: + builtins.print(ansi.rd + " ERROR ", end="") + builtins.print(ansi.cl + "]: ", end="") + builtins.print(*args, **kwargs, flush=True) + + +def print_question(question, delay=0.5): + """Print question + + Print out a yes-or-no question in the terminal in the same format as print. + Default selection marked in uppercase and requires only to press Enter. + + :param question: the text of the yes-or-no question + :type question: str + :param delay: delay after the answer, defaults to 0.5 sec + :type delay: float, optional + :return: True if 'Y' is the answer, else False + :rtype: bool + """ + builtins.print("[" + ansi.pr + "QUESTION" + ansi.cl + "]: ", end='') + yorno = input(question + " [Y/n]:\n" + " " * 12) + if yorno.lower() == 'n': + # overwrites the previous line content: n --> No. + builtins.print(ansi.prev_ln + "\r" + " " * 12 + ansi.yl + "No." + ansi.cl) + time.sleep(delay) + return False + else: + # overwrites the previous line content: --> Yes. + builtins.print(ansi.prev_ln + "\r" + " " * 12 + ansi.gn + "Yes." + ansi.cl) + time.sleep(delay) + return True + + +def print_tip(t, delay=1.5): + """Prints out selected tip to the standard output + + :param t: selected tip to display + :type t: Literal + """ + offset = " " * 12 + if t == tip.BOOT: + msg = "Tip: to add bootloader to the apploader you have the following options:\n" + offset + msg += "Option 1:\n" + offset + msg += "- copy a bootloader image .s37 to the current working directory\n" + offset + if SERIES_1: + boot = BOOT_S1_F + else: + boot = BOOT_S2_F + msg += "- rename it to " + ansi.yl + f"{boot}" + ansi.cl + " and rerun this script\n" + offset + msg += "Option 2:\n" + offset + msg += "- rerun this script with "+ansi.yl+"-i"+ansi.cl+" argument to activate interactive mode\n" + offset + msg += "- when prompted select the desired bootloader .s37 image with a filedialog" + msg += "Option 3:\n" + offset + msg += "- rerun this script with "+ansi.yl+"-b"+ansi.cl+" argument and specify a direct path to\n" + offset + msg += " the selected bootloader .s37 file\n" + offset + msg += "Note: Series-2 devices support merged bootloaders a.k.a. bootloader-apploader.s37\n" + offset + msg += " for applications that are utilize in-place OTA DFU.\n" + offset + + elif t == tip.ENCRYPT or t == tip.SIGN: + if t == tip.ENCRYPT: + action = "encrypt" + key = action + "ion key .txt" + arg = "-k" + filename = ENCRYPT_F + else: + action = "sign" + key = action + "ature key .pem" + arg = "-s" + filename = SIGN_F + msg = f"Tip: to generate {action}ed GBL files you have the following options:\n" + offset + msg += "Option 1:\n" + offset + msg += f"- copy the {key} file to the current working directory\n" + offset + msg += "- rename it to " + ansi.yl + f"{filename}" + ansi.cl + " and rerun this script\n" + offset + msg += "Option 2:\n" + offset + msg += "- rerun this script with "+ansi.yl+"-i"+ansi.cl+" argument to activate interactive mode\n" + offset + msg += "- when prompted select the generation option to generate the key automatically\n" + offset + msg += "Option 3:\n" + offset + msg += "- rerun this script with "+ansi.yl+f"{arg}"+ansi.cl+" argument and specify a direct path to\n" + offset + msg += " the selected key file\n" + offset + + elif t == tip.COMPRESS: + cpx = ansi.yl + "support decompressing" + ansi.cl + msg = f"Compressed GBLs require a bootloader that {cpx} the GBL!" + elif t == tip.INTERACTIVE: + msg = ansi.pr + "INTERACTIVE MODE" + ansi.cl + " selected!\n" + offset + msg += "For missing tools or files a dialog will be shown to specify the absolute path to the tool\n" + offset + msg += "in console- or filedialogs, for "+ansi.yl+"keys"+ansi.cl+" the script will offer\n" + offset + msg += "the generation option.\n" + offset + msg += "If you want to run this script without any human interaction e.g. in automated environment\n" + offset + msg += "it is suggested to not use this mode!\n" + offset + msg += "Consult with the helper (-h or --help) for more" + print(lvl.INFO,msg) + time.sleep(delay) + + +def display_menu(elems_list, title): + """Display text-based menu + + Display text based menu for the user in the terminal. + The options in the displayed menu defined by the elem_list. + + The user shall select from 1st to last or press other keys to abort the selection. + + :param elems_list: list that will be taken as the options for the menu + :type elems_list: lst + :param title: title that will be displayed above the options + :type title: str + :return: selected element from the elems_list (as string) + :rtype: str + """ + print(lvl.INFO,title) + for i in range(0, len(elems_list)): + print(lvl.INFO,f"[{i+1}] ", str(elems_list[i])) + + message = f"Select one from above [ 1 - {len(elems_list)} ] and press Enter!\n" + " " * 12 + message += "To abort press any other key and press Enter!" + print(lvl.INFO,message) + try: + s = int(input(" " * 12)) + except (TypeError, ValueError): + s = 0 + + if s in range(1, len(elems_list)+1): + print(lvl.INFO,ansi.prev_ln + " " *12 + f"{str(s)} - \'{str(elems_list[s-1])}\'.") + return str(elems_list[s-1]) + print(lvl.INFO,f"Abort selection.") + return None + + +def interactive_menu(sep): + """Realize interactive menu to configure the generator + + Shows terminal-dialogs and displays terminal-menu in order to set all possible switches in + an interactive way. + The switches: + - sign GBLs (bool) + - encrypt GBLs (bool) + - compress GBLs (bool) + - compression method as string (lz4, lzma, both) + - generate UARTDFU GBLs (bool) + + :param sep: separator string that only used for display style + :type sep: str + :return: valid values for sign, encrypt, cpress, cpress_method, uartdfu + :rtype: bool, bool, bool, str, bool + """ + offset = " " * 12 + + print_tip(tip.INTERACTIVE) + print(lvl.INFO,sep) + print(lvl.INFO,"Select generation steps below ...") + print(lvl.INFO,sep) + + question = "Would you like to "+ ansi.yl + "sign" + ansi.cl + " your GBL files?\n" + offset + question += "Note: if you don't have .pem files this script will generate them\n" + offset + question += "for you later on if you want to." + sign = print_question(question) + + question = "Would you like to "+ ansi.yl + "encrypt" + ansi.cl + " your GBL files?\n" + offset + question += "Note: if you don't have an encryption key .txt this script will generate them\n" + offset + question += "for you later on if you want to." + encrypt = print_question(question) + + question = "Would you like to "+ ansi.yl + "compress" + ansi.cl + " your GBL files?\n" + offset + question += "Note: for compressed GBLs you have to use a bootloader that is capable to\n" + offset + question += ansi.yl + "decompress" + ansi.cl + " those images!" + cpress = print_question(question) + if cpress: + cpress_method = display_menu(['lz4', 'lzma', 'both'], "Select compression method!") + else: + cpress = False + cpress_method = "" + print(lvl.WARN, "Did not selected compression method!") + print(lvl.INFO, "Compression will be skipped!") + + uartdfu = print_question("Would you like to generate "+ ansi.yl + "UARTDFU" + ansi.cl + " GBL files?") + + print(lvl.INFO, sep) + print(lvl.INFO, "Setup finished:") + print(lvl.INFO, sep) + # "Sign | Encrypt | Compress | Compress method | UART DFU GBLs" + # " yes | no | yes | lzma | yes" + print(lvl.INFO, "Sign | Encrypt | Compress | Compress method | UART DFU GBLs") + print(lvl.INFO, f"{'yes ' if sign else 'no '}| {'yes ' if encrypt else 'no '}|", end="") + if cpress_method == "lz4": + cpress_method += " " + elif cpress_method == "": + cpress_method = "none" + builtins.print(f"{' yes ' if cpress else ' no '}| {cpress_method} |", end="") + builtins.print(f"{' yes' if uartdfu else ' no'}") + + return sign, encrypt, cpress, cpress_method, uartdfu + + +def detect_platform(): + """Detects host platform and returns with it + + :return: platform in lower letters string + :rtype: str + """ + platform = os.sys.platform.lower() + if platform == 'win32': + response = run_cmd(['uname'], True, verbose=VERBOSE) + if response is None: + return 'cmd' + elif re.search(r'is not recognized', response): + return 'cmd' + else: + match_result = re.search(r'MSYS_NT', response) + if match_result: + return 'msys' + match_result = re.search(r'MINGW', response) + if match_result: + return 'mingw' + match_result = re.search(r'CYGWIN_NT', response) + if match_result: + return 'cygwin' + else: + return platform + + +def run_cmd(command_list, supp_ex_disp=False, verbose=False): + """Execute terminal command + + Execute terminal command in a subprocess and return with the content of the standard error and + standard output if its not empty. + + :param command_list: terminal command as a list + :type command_list: lst + :param supp_ex_disp: suppress exception display, defaults to False + :type supp_ex_disp: bool, optional + :param verbose: verbosity enable, defaults to False + :type verbose: bool, optional + :return: in case not empty return with stderr or stdout content as utf-8 encoded string + :rtype: str + """ + if verbose: + print(lvl.INFO,"Call:") + print(lvl.INFO,"\'" + " ".join(command_list) + "\'") + try: + cmd_proc = subprocess.run(command_list, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + except FileNotFoundError: + cmd_proc = subprocess.run(command_list, stdout=subprocess.PIPE, stderr=subprocess.PIPE, shell=True) + except Exception as ex: + if not supp_ex_disp: + print(lvl.ERR,ansi.rd + " ".join(command_list), ansi.cl + "could not be executed!") + print(lvl.INFO,"Exception:\n" + ansi.rd + str(ex) + ansi.cl) + return None + + err = cmd_proc.stderr.decode('utf-8') + out = cmd_proc.stdout.decode('utf-8') + + if err != "": + if not supp_ex_disp: + print(lvl.ERR,"Error during execution of \'" + " ".join(command_list)+"\'!") + print(lvl.INFO,"stderr:\n"+ansi.rd+err+ansi.cl) + return err + elif out != "": + return out + else: + return None + + +def reformat_path(path): + """Reformat path to forwardslash posix format + + Reformat path to posix format with forward slashes that is universally accepted by win & posix. + Also converting cygwin and msys paths to this format. + + :param path: original path + :type path: str + :return: reformatted path + :rtype: str + """ + path = path.replace('\r', '').replace('\n', '') + if PLATFORM == 'cygwin': + m: re.Match = re.match(r"^/cygdrive/(\w)/[\w\s\\/_\-\.]+$", path) + if m is not None: + path = re.sub(r"^/cygdrive/\w/", f"{m.group(1)}:/", path) + return str(Path(path).as_posix()) + else: + return str(Path(path).as_posix()) + elif PLATFORM == 'msys' or PLATFORM == 'mingw': + m: re.Match = re.match(r"^/(\w)/[\w\s\\/_\-\.]+$", path) + if m is not None: + path = re.sub(r"^/\w/", f"{m.group(1)}:/", path) + return str(Path(path).as_posix()) + else: + return str(Path(path).as_posix()) + else: + return str(Path(path).as_posix()) + + +def check_util_exist(util_name, env): + """Check whether the selected utility exist + + Check if the selected utility exists in the system PATH. + + :param util_name: name of the utility (without extension on windows) + :type util_name: str + :param env: environment variable + :type env: str + :return: absolute path to the utility if exists + :rtype: str + """ + if PLATFORM != 'cmd': + cmd = ['which'] + result_re = r'which: no' + else: + util_name += '.exe' + cmd = ['where'] + result_re = r'Could not find files' + cmd.append(util_name) + cmd_result = run_cmd(cmd, True, verbose=VERBOSE) + match_err = re.search(result_re, cmd_result) + if match_err: + if os.environ[env] is not None: + print(lvl.WARN,f"{util_name} not found in PATH!") + p = reformat_path(os.environ[env]) + for root, files in os.walk(p): + for f in files: + if f.endswith(util_name) and os.access(os.path.join(root, f), os.X_OK): + f = os.path.join(root, f) + p = reformat_path(f) + print(lvl.OKAY,"Using " + ansi.gn + f"{env}" + ansi.cl + f" instead: {p}") + return p + print(lvl.ERR, f"Could not find {util_name}!") + return None + else: + p = reformat_path(cmd_result) + print(lvl.OKAY, f"{util_name} detected: {p}") + return p + + +def get_file_list(path, extension): + """Get all files with the selected extension + + Get files with the selected extension in the selected path. + + :param path: path in which the search shall be done + :type path: str + :param extension: extension without a '.' + :type extension: str + :return: list of absolute filepaths with the selected extension + :rtype: lst + """ + file_list = [] + try: + for root, dirs, files in os.walk(path): + for file in files: + if file.endswith(extension): + file_list.append(os.path.join(root, file)) + except TypeError: + print(lvl.ERR,"Invalid path:" + ansi.rd + path + ansi.cl + "!") + return file_list + + +def is_target_series_1(build_artifact): + """Determine the target series + + Determine the target series based on the existing build artifact. + + :param build_artifact: absolute path the the build artifact + :type build_artifact: str + :return: True if its a Series-1 project, else False + :rtype: bool + """ + with open(build_artifact, 'r', errors='ignore') as app: + lines = app.readlines() + for line in lines: + if line.find('text_apploader') != -1: + return True + return False + + +def is_file_exist(path, suppress_ex=False): + """Check if the file exist + + Check path if its a file and it does exist. + If not, or any kind of exception occurs print out the exception and return with False. + Or return with True. + + :param path: path the the file + :type path: str + :param suppress_ex: _description_, defaults to False + :type suppress_ex: bool, optional + :return: True if the file exists, or False. + :rtype: bool + """ + try: + path = reformat_path(path) + return os.path.isfile(path) + except: + if path is None and not suppress_ex: + print(lvl.ERR, ansi.rd + "File does not exist!" + ansi.cl) + elif not suppress_ex: + print(lvl.ERR, ansi.rd + f"\'{path}\' does not exist!" + ansi.cl) + return False + + +def extract_to_srec(srec_name, remove_sections, out_path, only_section=False): + """Extract binary data to srec file + + Extract binary data with arm-eabi-objcopy into an .srec file for further usage. + If the only_section flag set, only the sections in the remove_sections input parameter will remain. + With this flag the complementer action of the original will be done. + + :param srec_name: name of the srec file (without extension) + :type srec_name: str + :param remove_sections: list of the .sections that has to be removed + :type remove_sections: lst + :param out_path: output path where the .srec file will be saved + :type out_path: str + :param only_section: copy only the sections mentioned in remove_sections, defaults to False + :type only_section: bool, optional + :return: path to the .srec file + :rtype: str + """ + srec_file = reformat_path(os.path.join(OUTDIR, srec_name + '.srec')) + cmd = [OBJCOPY, '-O', 'srec'] + for sect in remove_sections: + if only_section: + cmd.extend(['-j', sect]) + else: + cmd.extend(['-R', sect]) + cmd.extend([out_path, srec_file]) + response = run_cmd(cmd, verbose=VERBOSE) + if response is None and os.path.isfile(srec_file): + print(lvl.INFO, srec_file + " extracted.") + return srec_file + else: + print(lvl.WARN, "Could not extract \'"+" ,".join(sect) + "\' sections from"+out_path+"!") + return None + + +def convert_srec(srec_list, srec_out_name, signature=None, with_crc=False): + """Converter function that converts and/or merges srec file(s) into new srec. + + Merge a list of srec files into one. + Optionally converts unprotected srec files to crc-protected srec or signed srec files. + These two types required to generate crc-protected or signed GBLs. + + :param srec_list: list of the input .srec filepaths that has to be merged + :type srec_list: str list + :param srec_out_name: the name of the output .srec file (without extension) + :type srec_out_name: str + :param signature: signature .pem filepath, defaults to None + :type signature: str, optional + :param with_crc: enable crc32 protect for output .srec, defaults to False + :type with_crc: bool, optional + :return: output .srec filepath + :rtype: str + """ + srec_out = reformat_path(os.path.join(OUTDIR, srec_out_name)) + cmd = [COMMANDER, 'convert'] + for sr in srec_list: + cmd.append(sr) + if with_crc: + srec_out += '-crc' + cmd.append('--crc') + if signature is not None: + srec_out += '-signed' + cmd.extend(['--secureboot', '--keyfile', signature]) + srec_out += '.srec' + cmd.extend(['-o', srec_out]) + response = run_cmd(cmd, verbose=VERBOSE) + match_res = re.search(r'Writing to', response) + if match_res and is_file_exist(srec_out): + print(lvl.INFO, " ".join(srec_list) + " converted to " + srec_out) + return srec_out + else: + print(lvl.WARN, "Could not convert " + " ".join(srec_list) + " to " + srec_out) + print(lvl.INFO, "command response:", response) + return None + + +def convert_srec_uartdfu(srec_list, srec_out_name): + """Merge .srec files specialized for UARTDFU GBLs + + Convert/merge .srec file(s) for specialized UARTDFU GBLs. + + :param srec_list: list of input .srec filepaths + :type srec_list: str list + :param srec_out_name: name of the output .srec file (without extension) + :type srec_out_name: str + :return: output .srec + :rtype: str + """ + if len(srec_list) == 2: + applo_srec = srec_list[0] + app_srec = srec_list[1] + if is_file_exist(applo_srec) and is_file_exist(app_srec): + out_srec = convert_srec([applo_srec, app_srec], srec_out_name) + if is_file_exist(out_srec): + print(lvl.OKAY, f"{applo_srec} and {app_srec} converted to {out_srec}.") + return out_srec + else: + print(lvl.WARN, f"Failed to convert {applo_srec} and {app_srec} to {out_srec}!") + return None + elif not is_file_exist(applo_srec) and is_file_exist(app_srec): + out_srec = reformat_path(os.path.join(OUTDIR, srec_out_name + '.srec')) + try: + shutil.copy(app_srec, out_srec) + print(lvl.OKAY, f"{app_srec} converted to {out_srec}.") + return out_srec + except shutil.SameFileError: + print(lvl.ERR, "Source and destination files are the same! Aborting.") + except PermissionError: + print(lvl.ERR, "Permission denied!") + except Exception as ex: + print(lvl.ERR, f"Exception occurred during execution of shutil.copy()!") + print(lvl.ERR, f"{ex}\n") + return None + else: + print(lvl.INFO, "Invalid .srec file list! None of the record contains actual files!") + return None + else: + print(lvl.WARN, "Failed to convert srec files! At least 2 srecs required!") + return None + + +def key_gen(key_name, encrypt_type='aes-ccm'): + """Encryption/signature key generator function + + Generate encryption or signature keys with the selected encryption methods. + To generate encrypt key, use 'ecc-p256' + To generate signature keys, use the default 'aes-ccm' + + :param key_name: name of the output key (without extension) + :type key_name: str + :param encrypt_type: encryption method, defaults to 'aes-ccm' + :type encrypt_type: str, optional + :return: True in case of successful key generation, False otherwise + :rtype: bool + """ + REGEX_GENKEY = r'Using .* generation.*DONE' + cmd = [COMMANDER, 'util', 'genkey', '--type'] + key_pf = '-key.txt' + if encrypt_type != 'aes-ccm': + REGEX_GENKEY = r'Writing private key.*DONE' + encrypt_type = 'ecc-p256' + key_pf = '-key.pem' + pkey_pf = '-pubkey.pem' + print(lvl.INFO,"Generate signature keys ...") + cmd.extend([encrypt_type, '--privkey', key_name + key_pf, '--pubkey', key_name + pkey_pf]) + else: + print(lvl.INFO,"Generate encryption key ...") + cmd.extend([encrypt_type, '--outfile', key_name + key_pf]) + + r = run_cmd(cmd, verbose=VERBOSE) + match_r = re.search(REGEX_GENKEY, r, flags=re.DOTALL) + if match_r and is_file_exist(key_name + key_pf): + print(lvl.OKAY, ansi.gn + f"{key_name+key_pf}" + ansi.cl + " generated.") + return True + elif match_r and is_file_exist(key_name + key_pf) and is_file_exist(key_name + pkey_pf): + print(lvl.OKAY,f"{key_name+key_pf}, {key_name+pkey_pf}.") + return True + else: + print(lvl.WARN,"Could not generate key!") + return False + + +def create_gbl_file(gbl_name, app_data, app_encrypt=None, app_sign=None, boot=None, cpress_a='', crc=False): + """Create GBL file function + + Builds up and initiates GBL generator command for simplicity commander based on the input parameters. + It is capable of the generation of: signed, encrypted, compressed and crc-protected GBL files. + + + :param gbl_name: Base name of the output gbl file (without extension), postfixes will be added automatically: + signed, encrypted versions will get -signed and/or -encrypted postfixes etc. + :type gbl_name: str + :param app_data: application data filepath (.srec or .gbl) + :type app_data: str + :param app_encrypt: encrypt-key filepath, defaults to None + :type app_encrypt: str, optional + :param app_sign: signature-key filepath, defaults to None + :type app_sign: str, optional + :param boot: bootloader image filepath, defaults to None + :type boot: str, optional + :param cpress_a: compression algorithm {lz4, lzma}, defaults to '' + :type cpress_a: str, optional + :param crc: generate protected GBL files with crc32 as well, defaults to False + :type crc: bool, optional + :return: filepath to the output gbl file or None in case of errors + :rtype: str + """ + if app_data is None and boot is None: + print(lvl.ERR,"Could not find " + app_data + "! Aborting GBL generation!") + return None + cmd = [COMMANDER, 'gbl', 'create'] + + if app_data is not None: + cmd.extend(['--app', app_data]) + if app_sign is not None: + gbl_name += '-signed' + cmd.extend(['--sign', app_sign]) + if app_encrypt is not None: + gbl_name += '-encrypted' + cmd.extend(['--encrypt', app_encrypt]) + if crc: + gbl_name += '-crc' + if boot is not None: + cmd.extend(['--bootloader', boot]) + if cpress_a in ('lz4', 'lzma'): + gbl_name += '-' + cpress_a + cmd.extend(['--compress', cpress_a]) + gbl_name += '.gbl' + gbl_file = reformat_path(os.path.join(OUTDIR, gbl_name)) + cmd.insert(3, gbl_file) + + if is_file_exist(gbl_file): + print(lvl.WARN, ansi.yl + f"{gbl_name}" + ansi.cl + " already exists!") + backup_text = '_bkp' + dt.now().strftime("%Y-%m-%d-%H-%M-%S") + os.rename(reformat_path(os.path.join(OUTDIR, gbl_name)), + reformat_path(os.path.join(OUTDIR, gbl_name + backup_text))) + print(lvl.INFO, f"{gbl_name} renamed to {gbl_name + backup_text}.") + gbl_name = "New " + ansi.gn + gbl_name + ansi.cl + else: + gbl_name = ansi.gn + gbl_name + ansi.cl + + response = run_cmd(cmd, verbose=VERBOSE) + match_res = re.search(r'Writing GBL file', response) + if match_res: + print(lvl.OKAY, gbl_name + " generated.\n") + return gbl_file + else: + return None + + +def generate_gbls(name, srec, s1=True, boot_img=None, encrypt_k=None, sign_k=None, + cpress=True, cpress_m='both', uartdfu=False): + """Generate multiple GBL files + + Generate all GBL files that can be generated based on the input parameters. + It also differentiate between Series-1 and Series-2 devices. + Apploader GBLs for example can only be used for Series-1 devices! + + :param name: base name for the GBL files + :type name: str + :param srec: application data .srec + :type srec: str + :param s1: Series-1 mode, defaults to True + :type s1: bool, optional + :param boot_img: path to the boot image .s37, defaults to None + :type boot_img: str, optional + :param encrypt_k: path to the encrypt key .txt, defaults to None + :type encrypt_k: str, optional + :param sign_k: path to the signature key .pem, defaults to None + :type sign_k: str, optional + :param cpress: generate compressed GBLs as well, defaults to True + :type cpress: bool, optional + :param cpress_m: compression method {'lz4', 'lzma', 'both'}, defaults to 'both' + :type cpress_m: str, optional + :param uartdfu: generate UARTDFU GBLs as well, defaults to False + :type uartdfu: bool, optional + """ + if uartdfu: + # full.gbl + create_gbl_file(name, srec) + if cpress: + if cpress_m in ('lz4', 'both'): + # full-lz4.gbl + create_gbl_file(name, srec, cpress_a='lz4') + if cpress_m in ('lzma', 'both'): + # full-lzma.gbl + create_gbl_file(name, srec, cpress_a='lzma') + + if is_file_exist(encrypt_k): + # full-encrypted.gbl + create_gbl_file(name, srec, app_encrypt=encrypt_k) + if cpress: + if cpress_m in ('lz4', 'both'): + # full-encrypted-lz4.gbl + create_gbl_file(name, srec, app_encrypt=encrypt_k, cpress_a='lz4') + if cpress_m in ('lzma', 'both'): + # full-encrypted-lzma.gbl + create_gbl_file(name, srec, app_encrypt=encrypt_k, cpress_a='lzma') + + apploader_srec = reformat_path(os.path.join(OUTDIR, APPLO_N + '-crc.srec')) + app_srec = reformat_path(os.path.join(OUTDIR, APPLI_N + '-crc.srec')) + + srec_crc = convert_srec_uartdfu([apploader_srec, app_srec], name + '-crc') + if not is_file_exist(srec_crc): + print(lvl.WARN,f"Skipping {name}-crc.gbl generation!\n") + else: + # full-crc.gbl + create_gbl_file(name, srec_crc, crc=True) + + apploader_s_srec = reformat_path(os.path.join(OUTDIR, APPLO_N + '-signed.srec')) + app_s_srec = reformat_path(os.path.join(OUTDIR, APPLI_N + '-signed.srec')) + + srec_signed = convert_srec_uartdfu([apploader_s_srec, app_s_srec], name + '-signed') + if srec_signed is None or not is_file_exist(srec_signed): + print(lvl.WARN,f"Skipping {name}-signed.gbl generation!\n") + else: + # full-signed.gbl + create_gbl_file(name, srec_signed, app_sign=sign_k) + if is_file_exist(encrypt_k): + # full-signed-encrypted.gbl + create_gbl_file(name, srec_signed, app_encrypt=encrypt_k, app_sign=sign_k) + + else: + if srec is None and not s1: + if is_file_exist(boot_img, suppress_ex=True): + # bootloader.gbl + create_gbl_file(name, None, boot=boot_img) + else: + print(lvl.WARN, f"Missing bootloader image: {boot_img}!") + else: + srec_crc = convert_srec([srec], name, with_crc=True) + if is_file_exist(boot_img, suppress_ex=True): + if is_file_exist(sign_k, suppress_ex=True): + srec_signed = convert_srec([srec], name + '-bootloader', signature=sign_k) + if is_file_exist(encrypt_k, suppress_ex=True): + # appl*-bootloader-signed-encrypted.gbl + create_gbl_file(name + '-bootloader', srec_signed, app_encrypt=encrypt_k, + app_sign=sign_k, boot=boot_img) + # appl*-bootloader-signed.gbl + create_gbl_file(name + '-bootloader', srec_signed, app_sign=sign_k, boot=boot_img) + + if is_file_exist(encrypt_k, suppress_ex=True): + # appl*-bootloader-encrypted.gbl + create_gbl_file(name + '-bootloader', srec, app_encrypt=encrypt_k, boot=boot_img) + # appl*-bootloader-encrypted-crc.gbl + create_gbl_file(name + '-bootloader', srec_crc, app_encrypt=encrypt_k, boot=boot_img, crc=True) + if cpress: + if cpress_m in ('lz4', 'both'): + # appl*-bootloader-encrypted-lz4.gbl + create_gbl_file(name + '-bootloader', srec, cpress_a='lz4', + app_encrypt=encrypt_k, boot=boot_img) + if cpress_m in ('lzma', 'both'): + # appl*-bootloader-encrypted-lzma.gbl + create_gbl_file(name + '-bootloader', srec, cpress_a='lzma', + app_encrypt=encrypt_k, boot=boot_img) + # appl*-bootloader.gbl + create_gbl_file(name + '-bootloader', srec, boot=boot_img) + # appl*-bootloader-crc.gbl + create_gbl_file(name + '-bootloader', srec_crc, boot=boot_img, crc=True) + if cpress: + if cpress_m in ('lz4', 'both'): + # appl*-bootloader-lz4.gbl + create_gbl_file(name + '-bootloader', srec, cpress_a='lz4', boot=boot_img) + if cpress_m in ('lzma', 'both'): + # appl*-bootloader-lzma.gbl + create_gbl_file(name + '-bootloader', srec, cpress_a='lzma', boot=boot_img) + + if is_file_exist(sign_k, suppress_ex=True): + srec_signed = convert_srec([srec], name, signature=sign_k) + if is_file_exist(encrypt_k, suppress_ex=True): + # appl*-signed-encrypted.gbl + create_gbl_file(name, srec_signed, app_encrypt=encrypt_k, app_sign=sign_k) + # appl*-signed.gbl + create_gbl_file(name, srec_signed, app_sign=sign_k) + + if is_file_exist(encrypt_k, suppress_ex=True): + # appl*-encrypted.gbl + create_gbl_file(name, srec, app_encrypt=encrypt_k) + # appl*-encrypted-crc.gbl + create_gbl_file(name, srec_crc, app_encrypt=encrypt_k, crc=True) + if cpress: + if cpress_m in ('lz4', 'both'): + # appl*-encrypted-lz4.gbl + create_gbl_file(name, srec, cpress_a='lz4', app_encrypt=encrypt_k) + if cpress_m in ('lzma', 'both'): + # appl*-encrypted-lzma.gbl + create_gbl_file(name, srec, cpress_a='lzma', app_encrypt=encrypt_k) + # appl*.gbl + create_gbl_file(name, srec) + # appl*-crc.gbl + create_gbl_file(name, srec_crc, crc=True) + if cpress: + if cpress_m in ('lz4', 'both'): + # appl*-lz4.gbl + create_gbl_file(name, srec, cpress_a='lz4') + if cpress_m in ('lzma', 'both'): + # appl*-lzma.gbl + create_gbl_file(name, srec, cpress_a='lzma') + +def main(): + # Platform + global PLATFORM + + # Utility paths + global COMMANDER + global OBJCOPY + + global OUTDIR + + # .axf or .out file to generate from + global PRJ_ARTIFACT + global SERIES_1 + + global BOOT_S1_F + global BOOT_S2_F + + SIGN_KEY_EXIST = False + + # file globals + global SIGN_F + global ENCRYPT_F + + # these flags define the generator phases + # it comes from either command arguments or from the interactive mode + SIGN = False + ENCRYPT = False + CPRESS = False + CPRESS_METHOD = "lzma" + UARTDFU = False + + separator = "-" * 80 + delay_display = 0.5 + + # Before any work check the Python version ... + if sys.version_info < (3, 6, 0): + sys.stderr.write("ERROR: you need at least Python v3.6.0 to run this script!\n") + sys.exit(1) + + builtins.print(LOGO) + # Workaround for cmd.exe color codes - without this the bare-codes are visible only. + os.system("") + + # Argument parse + parser = argparse.ArgumentParser( + prog="create_bl_files.py", description=f"Create Gecko Bootloader Files") + # arguments + parser.add_argument("-o", "--outdir", dest="outdir", type=str, help="output directory for the generated files", + metavar="DIRECTORY") + parser.add_argument("-w", "--overwrite", dest="overwrite_old", action="store_true", help="Overwrite existing GBLs") + parser.add_argument("-i", "--interactive", dest="interactive", action="store_true", + help="ignore args and give choices to the user") + parser.add_argument("-k", "--key", dest="encryption_key", help="encryption key .txt", metavar="FILE", + type=argparse.FileType('r', encoding='UTF-8')) + parser.add_argument("-b", "--boot", dest="boot_img", help="bootloader.s37 file", metavar="FILE", + type=argparse.FileType('r', encoding='UTF-8')) + parser.add_argument("-s", "--signature", dest="signature_key", help="signature key .pem", metavar="FILE", + type=argparse.FileType('r', encoding='UTF-8')) + parser.add_argument("-a", "--all", dest="all", action="store_true", help="create every possible GBL files") + parser.add_argument("-u", "--uartdfu", dest="uartdfu", action="store_true", help="create GBLs for UART DFU") + parser.add_argument("-cpr", "--compress", dest="compress", choices=["lz4", "lzma", "both"], + help="Compress GBLs with the chosen method") + args = parser.parse_args() + + if args.outdir is not None and os.path.isdir(args.outdir): + OUTDIR = reformat_path(args.outdir) + print(lvl.OKAY, "Custom output directory set to " + ansi.yl + f"{OUTDIR}"+ ansi.cl + ".") + else: + if not os.path.isdir(OUTDIR): + os.makedirs(OUTDIR) + print(lvl.OKAY,f"Create {OUTDIR} directory.") + else: + print(lvl.OKAY,f"Directory {OUTDIR} already exists.") + + # reformat paths to the input files + if args.encryption_key is not None: + args.encryption_key = reformat_path(args.encryption_key) + if args.boot_img is not None: + args.boot_img = reformat_path(args.boot_img) + if args.signature_key is not None: + args.signature_key = reformat_path(args.signature_key) + + # Environment + print(lvl.INFO,separator) + print(lvl.INFO,"Check environment ...") + print(lvl.INFO,separator) + time.sleep(delay_display) + + PLATFORM = detect_platform() + print(lvl.INFO,"Detected platform: " + ansi.yl + PLATFORM + ansi.cl) + + res = check_util_exist('commander', 'PATH_SCMD') + if res is not None: + COMMANDER = res + else: + sys.exit(1) + + res = check_util_exist('arm-none-eabi-objcopy', 'PATH_GCCARM') + if res is not None: + OBJCOPY = res + else: + sys.exit(1) + + builtins.print("") + print(lvl.INFO,separator) + print(lvl.INFO,"Check input files ...") + print(lvl.INFO,separator) + time.sleep(delay_display) + + axf = get_file_list(os.getcwd(), '.axf') + out = get_file_list(os.getcwd(), '.out') + + artifacts_num = len(axf) + len(out) + if artifacts_num > 1: + print(lvl.WARN,f"Multiple build artifacts detected ({artifacts_num})!") + if ALWAYS_SELECT_GCC_EXT: + PRJ_ARTIFACT = reformat_path(axf[0]) + else: + PRJ_ARTIFACT = reformat_path(out[0]) + print(lvl.WARN,f"Build artifact selected: {PRJ_ARTIFACT}") + print(lvl.INFO,"Choose which to select automatically by changing the value of \'ALWAYS_SELECT_GCC_EXT\'!\n") + elif artifacts_num == 1: + if len(axf) != 0: + PRJ_ARTIFACT = reformat_path(axf[0]) + if len(out) != 0: + PRJ_ARTIFACT = reformat_path(out[0]) + print(lvl.OKAY,f"Build artifact selected: {PRJ_ARTIFACT}") + else: + print(lvl.ERR,"Neither *.axf or *.out build artifacts found!") + print(lvl.INFO,ansi.yl+"Project built successfully before running this script?\n"+ansi.cl) + sys.exit(1) + + if args.interactive == True: + SIGN, ENCRYPT, CPRESS, CPRESS_METHOD, UARTDFU = interactive_menu(separator) + elif args.interactive == False: + if all(v is None or v == False for v in vars(args).values()): + print(lvl.WARN, "No argument specified, using " + ansi.yl + "--all" + ansi.cl + " meaning:") + AUTO_KEYGEN = True + SIGN = True + ENCRYPT = True + CPRESS = True + CPRESS_METHOD = "both" + UARTDFU = True + msg = ansi.yl + "ALL FEATURES ENABLED" + ansi.cl + ": " + msg += "sign, encrypt, compress and generate UARTDFU GBLs too." + print(lvl.WARN, msg) + print(lvl.INFO, "Missing keys will be "+ansi.yl+"automatically "+ansi.cl+"generated!") + time.sleep(delay_display) + + if args.all: + SIGN = True + ENCRYPT = True + CPRESS = True + CPRESS_METHOD = "both" + UARTDFU = True + msg = ansi.yl + "ALL FEATURES ENABLED" + ansi.cl + ": " + msg += "sign, encrypt, compress and generate UARTDFU GBLs too." + print(lvl.WARN, msg) + print(lvl.INFO, "Missing keys will be automatically generated!") + time.sleep(delay_display) + else: + if args.signature_key: + SIGN = True + if args.encryption_key: + ENCRYPT = True + if args.compress in ("lz4", "lzma", "both"): + CPRESS = True + CPRESS_METHOD = args.compress + if args.uartdfu: + UARTDFU = True + + time.sleep(delay_display) + + builtins.print("") + print(lvl.INFO,separator) + print(lvl.INFO,"Check bootloader image ...") + print(lvl.INFO,separator) + time.sleep(delay_display) + + print(lvl.OKAY,"Target device: ", end='') + SERIES_1 = is_target_series_1(PRJ_ARTIFACT) + if SERIES_1: + builtins.print(ansi.gn + "Series-1\n" + ansi.cl) + else: + builtins.print(ansi.gn + "Series-2\n" + ansi.cl) + + if args.boot_img is not None: + BOOT_EXIST = is_file_exist(args.boot_img) + print(lvl.OKAY,f"Bootloader image added as argument: {args.boot_img}") + if SERIES_1: + BOOT_S1_F = args.boot_img + else: + BOOT_S2_F = args.boot_img + elif args.interactive: + print(lvl.INFO,"Display filedialog ...") + root = tk.Tk() + root.withdraw() + if SERIES_1: + w_title = "Select Series-1 bootloader .s37" + else: + w_title = "Select Series-2 bootloader .s37" + boot_path = fd.askopenfile(initialdir=os.getcwd(), title=w_title) + BOOT_EXIST = is_file_exist(boot_path.name, suppress_ex=True) + if BOOT_EXIST: + if SERIES_1: + BOOT_S1_F = boot_path.name + else: + BOOT_S2_F = boot_path.name + print(lvl.OKAY,"Selected a valid bootloader .s37 image.") + else: + print(lvl.ERR,"Invalid file has been selected as bootloader image!") + else: + print(lvl.INFO,"No boot image in command argument.") + print(lvl.INFO,"Check current working directory ...\n") + if SERIES_1: + BOOT_EXIST = is_file_exist(BOOT_S1_F) + else: + BOOT_EXIST = is_file_exist(BOOT_S2_F) + + # show the compression related tip only in case all features shall be used or compression selected + # according to the command-arguments, and interactive mode is not active + if (args.all or args.compress in ("lzma", "lz4", "both")) and not args.interactive: + print_tip(tip.COMPRESS) + + # if can not recognize bootloader, print out the tip on how to use it if interactive mode is not active + if not BOOT_EXIST: + BOOT_S1_F = None + BOOT_S2_F = None + print(lvl.INFO,"Bootloader addition will be skipped!\n") + if not args.interactive: + print_tip(tip.BOOT) + else: + print(lvl.OKAY,"Bootloader image detected.\n") + time.sleep(delay_display) + + if SIGN: + builtins.print("") + print(lvl.INFO,separator) + print(lvl.INFO,"Check prerequisites for signed GBL generation ...") + print(lvl.INFO,separator) + time.sleep(delay_display) + + if args.signature_key is not None: + SIGN_KEY_EXIST = is_file_exist(args.signature_key) + if SIGN_KEY_EXIST: + print(lvl.OKAY,f"Signature key added as argument: {args.signature_key}") + SIGN_F = args.signature_key + else: + print(lvl.WARN, f"Invalid signature key in command argument: {args.signature_key}!") + print(lvl.INFO, "Check current working directory ...") + SIGN_KEY_EXIST = is_file_exist(SIGN_F) + else: + print(lvl.INFO, f"No signature key in command argument.") + print(lvl.INFO, "Check current working directory ...") + SIGN_KEY_EXIST = is_file_exist(SIGN_F) + + if not SIGN_KEY_EXIST: + print(lvl.WARN,f"Could not detect {SIGN_F}!") + if args.interactive: + decision = print_question(f"Would you like to generate {SIGN_F} now?", delay=delay_display) + if not decision: + SIGN_F = None + print(lvl.WARN,f"Will not generate {SIGN_F}!") + print(lvl.INFO,"Application signing will be skipped!\n") + time.sleep(delay_display) + else: + time.sleep(delay_display) + # in this case the gbl generator function will check whether the key_gen really generated + # a valid signature key or not + SIGN_KEY_EXIST = key_gen(SIGN_N, encrypt_type='ecc-p256') + elif args.all or AUTO_KEYGEN: + # generate the signature keys automatically + SIGN_KEY_EXIST = key_gen(SIGN_N, encrypt_type='ecc-p256') + else: + print(lvl.WARN,f"Could not detect {SIGN_F}!") + print(lvl.INFO,"Application signing will be skipped!\n") + print_tip(tip.SIGN) + SIGN_F = None + else: + print(lvl.OKAY,f"Detected {SIGN_F}.") + else: + SIGN_F = None + + if ENCRYPT: + builtins.print("") + print(lvl.INFO,separator) + print(lvl.INFO,"Check prerequisites for encrypted GBL generation ...") + print(lvl.INFO,separator) + time.sleep(delay_display) + + ENCRYPT_KEY_EXIST = is_file_exist(ENCRYPT_F) + if not ENCRYPT_KEY_EXIST: + print(lvl.WARN,f"Could not detect {ENCRYPT_F}!") + if args.interactive: + decision = print_question(f"Would you like to generate {ENCRYPT_F} now?", delay=delay_display) + if not decision: + ENCRYPT_F = None + print(lvl.WARN,f"Will not generate {ENCRYPT_F}!") + print(lvl.INFO,"Application encryption will be skipped!\n") + time.sleep(delay_display) + else: + time.sleep(delay_display) + # in this case the gbl generator function will check whether the key_gen really generated + # a valid encryption key or not + ENCRYPT_KEY_EXIST = key_gen(ENCRYPT_N) + elif args.all or AUTO_KEYGEN: + # generate the encryption key automatically + ENCRYPT_KEY_EXIST = key_gen(ENCRYPT_N) + else: + print(lvl.WARN,f"Could not detect {ENCRYPT_F}! Application signing will be skipped!") + print_tip(tip.ENCRYPT) + ENCRYPT_F = None + else: + print(lvl.OKAY,f"Detected {ENCRYPT_F}.") + else: + ENCRYPT_F = None + + if SERIES_1: + builtins.print("") + print(lvl.INFO, separator) + print(lvl.INFO, "Generate apploader GBLs ...") + print(lvl.INFO, separator) + time.sleep(delay_display) + applo_srec = extract_to_srec(APPLO_N, ['.text_apploader*'], PRJ_ARTIFACT, only_section=True) + generate_gbls(APPLO_N, applo_srec, boot_img=BOOT_S1_F, encrypt_k=ENCRYPT_F, sign_k=SIGN_F) + else: + if BOOT_EXIST: + builtins.print("") + print(lvl.INFO, separator) + print(lvl.INFO, "Generate bootloader GBL ...") + print(lvl.INFO, separator) + time.sleep(delay_display) + generate_gbls(BOOTLO_N, None, s1=False, boot_img=BOOT_S2_F, cpress=False) + + builtins.print("") + print(lvl.INFO, separator) + print(lvl.INFO, "Generate application GBLs ...") + print(lvl.INFO, separator) + time.sleep(delay_display) + + # extract all sections except the .text_apploader* and .text_signature* + app_srec = extract_to_srec(APPLI_N, ['.text_apploader*', '.text_signature*'], PRJ_ARTIFACT) + if app_srec is not None: + if SERIES_1: + generate_gbls(APPLI_N, app_srec, boot_img=BOOT_S1_F, encrypt_k=ENCRYPT_F, sign_k=SIGN_F, + cpress=CPRESS, cpress_m=CPRESS_METHOD) + else: + generate_gbls(APPLI_N, app_srec, s1=False, boot_img=BOOT_S2_F, encrypt_k=ENCRYPT_F, + sign_k=SIGN_F, cpress=CPRESS, cpress_m=CPRESS_METHOD) + else: + print(lvl.ERR, f"Could not create {APPLI_N}.srec!") + print(lvl.ERR, "Exit program.") + sys.exit(1) + + if UARTDFU: + # for UART DFU compatible GBL extract every section except the .text_bootloader section into an srec + uartdfu_srec = extract_to_srec(UARTDFU_N, ['.text_bootloader*'], PRJ_ARTIFACT) + # generate UART DFU GBLs + generate_gbls(UARTDFU_N, uartdfu_srec, encrypt_k=ENCRYPT_F, sign_k=SIGN_F, cpress=CPRESS, + cpress_m=CPRESS_METHOD, uartdfu=True) + + if PURGE_SRECS: + builtins.print("") + print(lvl.INFO,separator) + print(lvl.INFO,"Erase all temporary srec files ...") + print(lvl.INFO,separator) + print(lvl.INFO,"Note: set \'PURGE_SRECS\' to False to keep these files.") + time.sleep(delay_display) + files_to_erase = glob(OUTDIR + '/*.srec') + for file in files_to_erase: + try: + os.remove(file) + except: + print(lvl.WARN,f"Could not erase {file}!") + print(lvl.INFO,"Finished.") + + +if __name__ == "__main__": + main() diff --git a/locator_ncp/create_bl_files.sh b/locator_ncp/create_bl_files.sh index c4b5f81..5f7c589 100644 --- a/locator_ncp/create_bl_files.sh +++ b/locator_ncp/create_bl_files.sh @@ -1,290 +1,290 @@ -#!/bin/bash - -if [ -z "$BASH_VERSION" ] -then - exec bash "$0" "$@" -fi - -# use PATH_GCCARM env var to override default path for gcc-arm -if [[ -z ${PATH_GCCARM} ]]; then - OBJCOPY="${ARM_GCC_DIR}/bin/arm-none-eabi-objcopy" - if [[ `uname` == CYGWIN* ]]; then OBJCOPY="`cygpath ${OBJCOPY}`"; fi -else - OBJCOPY="${PATH_GCCARM}/bin/arm-none-eabi-objcopy" -fi - -# use PATH_SCMD env var to set path for Simplicity Commander -if [[ -n ${PATH_SCMD} ]]; then - COMMANDER="${PATH_SCMD}/commander" -fi - -# use PATH_OUT env var to override the full path for the .out file - -# default file extension of GCC and IAR -FILE_EXTENSION_GCC="*.axf" -FILE_EXTENSION_IAR="*.out" - -# names of the OTA and UART DFU output files -OTA_APPLO_NAME="apploader" -OTA_APPLI_NAME="application" -UARTDFU_FULL_NAME="full" - -# names of the sign and encypt key files -GBL_SIGING_KEY_FILE="app-sign-key.pem" -GBL_ENCRYPT_KEY_FILE="app-encrypt-key.txt" - -# bootlader file name -BOOTLOADER_FILE="bootloader-second-stage.s37" - -# project path -PATH_PROJ="$1" - -if [ -z "$PATH_PROJ" ]; then - echo "No project path specified. Using script directory as root." - echo - PATH_PROJ="$(dirname $0)" -fi - -# output path of the OTA and UART DFU gbl files -PATH_GBL="${PATH_PROJ}/output_gbl" - -# out file path -PATH_OUT=`find ${PATH_PROJ} -type f \( -iname ${FILE_EXTENSION_GCC} \) -exec echo {} \;` -if [[ -z ${PATH_OUT} ]]; then - PATH_OUT=`find ${PATH_PROJ} -type f \( -iname ${FILE_EXTENSION_IAR} \) -exec echo {} \;` -fi - -if [[ -z ${PATH_OUT} ]]; then - echo "Error: neither ${FILE_EXTENSION_GCC} nor ${FILE_EXTENSION_IAR} found" - echo "Was the project compiled and linked successfully?" - read -rsp $'Press enter to continue...\n' - exit -fi - -if [[ ! -f "${OBJCOPY}" ]]; then - echo "Error: gcc-arm objcopy not found at '${OBJCOPY}'" - echo "Use PATH_GCCARM env var to override default path for gcc-arm." - echo "Please refer to AN1086 sections 2.3 and 3.10 on how to set the required" - echo "environmental variables." - read -rsp $'Press enter to continue...\n' - exit -fi - -if [[ ! -f "${COMMANDER}" ]]; then - echo "Error: Simplicity Commander not found at '${COMMANDER}'" - echo "Use PATH_SCMD env var to override default path for Simplicity Commander." - echo "Please refer to AN1086 sections 2.3 and 3.10 on how to set the required" - echo "environmental variables." - read -rsp $'Press enter to continue...\n' - exit -fi - -if [[ -f "$BOOTLOADER_FILE" ]]; then - echo "Bootloader file was found" -else - echo "Bootloader file was not found" - echo "---- BOOTLOADER GENERATION -------------------------------------------" - echo "For adding bootloader to apploader copy a bootloader s37 image, e.g." - echo "'bootloader-storage-internal-single.s37' to the project root folder," - echo "rename it to 'bootloader-second-stage.s37' and rerun the script file." - echo "----------------------------------------------------------------------" - echo -fi - -if [[ -f "$GBL_ENCRYPT_KEY_FILE" ]]; then - echo "Encryption key file was found" -else - echo "Encryption key file was not found" - echo "---- ENCRYPTED GBL FILE GENERATION -----------------------------------" - echo "To generate an encrypted firmware upgrade file," - echo "copy an encryption key file into the root folder of the project," - echo "rename it to 'app-encrypt-key.txt' and rerun the script file." - echo "----------------------------------------------------------------------" - echo -fi - -if [[ -f "$GBL_SIGING_KEY_FILE" ]]; then - echo "Signing key file was found" -else - echo "Signing key file was not found" - echo "---- SIGNED GBL FILE GENERATION --------------------------------------" - echo "To generate a signed firmware upgrade file," - echo "copy a signing key file into the root folder of the project," - echo "rename it to 'app-sign-key.pem' and rerun the script file." - echo "----------------------------------------------------------------------" - echo -fi - -echo "**********************************************************************" -echo "Converting .out to .gbl files" -echo "**********************************************************************" -echo -echo ".out file used:" -echo "${PATH_OUT}" -echo -echo "output folder:" -echo "${PATH_GBL}" - -mkdir -p ${PATH_GBL} - -# create the GBL files -echo -echo "**********************************************************************" -echo "Creating ${OTA_APPLO_NAME}.gbl for OTA" -echo "**********************************************************************" -echo -"${OBJCOPY}" -O srec -j .text_apploader* "${PATH_OUT}" "${PATH_GBL}/${OTA_APPLO_NAME}.srec" -if [ $? -ne 0 ]; then - read -rsp $'Press enter to continue...\n' - exit -fi -if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --bootloader ${BOOTLOADER_FILE} -else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" -fi - -echo -echo "**********************************************************************" -echo "Creating ${OTA_APPLI_NAME}.gbl for OTA" -echo "**********************************************************************" -echo -"${OBJCOPY}" -O srec -R .text_apploader* -R .text_signature* "${PATH_OUT}" "${PATH_GBL}/${OTA_APPLI_NAME}.srec" -if [ $? -ne 0 ]; then - read -rsp $'Press enter to continue...\n' - exit -fi -"${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}.srec" - -# create the full GBL files for UART DFU -echo -echo "**********************************************************************" -echo "Creating ${UARTDFU_FULL_NAME}.gbl for UART DFU" -echo "**********************************************************************" -echo -"${OBJCOPY}" -O srec -R .text_bootloader* "${PATH_OUT}" "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" -if [ $? -ne 0 ]; then - read -rsp $'Press enter to continue...\n' - exit -fi -"${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" - -# create encrypted GBL file for secure boot if encrypt-key file exist -if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then - echo - echo "**********************************************************************" - echo "Creating encrypted .gbl files" - echo "**********************************************************************" - echo - if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --bootloader ${BOOTLOADER_FILE} - else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} - fi - echo - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} - echo - "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} -fi - -# create signed GBL file for secure boot if sign-key file exists -if [[ -f $GBL_SIGING_KEY_FILE ]]; then - echo - echo "**********************************************************************" - echo "Creating signed .gbl files" - echo "**********************************************************************" - echo - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --secureboot --keyfile ${GBL_SIGING_KEY_FILE} -o "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then - if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-signed.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} --bootloader ${BOOTLOADER_FILE} - else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-signed.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} - fi - fi - echo - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --secureboot --keyfile ${GBL_SIGING_KEY_FILE} -o "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-signed.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} - echo - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" -o "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" - else - cp "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" - fi - "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} - - # create signed and encrypted GBL file for if both sign-key and encrypt-key file exist - if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then - echo - echo "**********************************************************************" - echo "Creating signed and encrypted .gbl files" - echo "**********************************************************************" - echo - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then - if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} --bootloader ${BOOTLOADER_FILE} - else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} - fi - echo - fi - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} - echo - "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} - fi -else - echo - echo "**********************************************************************" - echo "Creating crc .gbl files" - echo "**********************************************************************" - echo - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --crc -o "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then - if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-crc.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --bootloader ${BOOTLOADER_FILE} - else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-crc.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" - fi - fi - echo - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --crc -o "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-crc.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" - echo - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then - "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" -o "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" - else - cp "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" - fi - "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" - - # create crc and encrypted GBL file if encrypt-key file exist - if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then - echo - echo "**********************************************************************" - echo "Creating crc and encrypted .gbl files" - echo "**********************************************************************" - echo - if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then - if [[ -f $BOOTLOADER_FILE ]]; then - echo "Bootloader file was found" - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --bootloader ${BOOTLOADER_FILE} - else - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} - fi - echo - fi - "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} - echo - "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} - fi -fi - -# clean up output dir -rm "${PATH_GBL}"/*.srec - -read -rsp $'Press enter to continue...\n' +#!/bin/bash + +if [ -z "$BASH_VERSION" ] +then + exec bash "$0" "$@" +fi + +# use PATH_GCCARM env var to override default path for gcc-arm +if [[ -z ${PATH_GCCARM} ]]; then + OBJCOPY="${ARM_GCC_DIR}/bin/arm-none-eabi-objcopy" + if [[ `uname` == CYGWIN* ]]; then OBJCOPY="`cygpath ${OBJCOPY}`"; fi +else + OBJCOPY="${PATH_GCCARM}/bin/arm-none-eabi-objcopy" +fi + +# use PATH_SCMD env var to set path for Simplicity Commander +if [[ -n ${PATH_SCMD} ]]; then + COMMANDER="${PATH_SCMD}/commander" +fi + +# use PATH_OUT env var to override the full path for the .out file + +# default file extension of GCC and IAR +FILE_EXTENSION_GCC="*.axf" +FILE_EXTENSION_IAR="*.out" + +# names of the OTA and UART DFU output files +OTA_APPLO_NAME="apploader" +OTA_APPLI_NAME="application" +UARTDFU_FULL_NAME="full" + +# names of the sign and encypt key files +GBL_SIGING_KEY_FILE="app-sign-key.pem" +GBL_ENCRYPT_KEY_FILE="app-encrypt-key.txt" + +# bootlader file name +BOOTLOADER_FILE="bootloader-second-stage.s37" + +# project path +PATH_PROJ="$1" + +if [ -z "$PATH_PROJ" ]; then + echo "No project path specified. Using script directory as root." + echo + PATH_PROJ="$(dirname $0)" +fi + +# output path of the OTA and UART DFU gbl files +PATH_GBL="${PATH_PROJ}/output_gbl" + +# out file path +PATH_OUT=`find ${PATH_PROJ} -type f \( -iname ${FILE_EXTENSION_GCC} \) -exec echo {} \;` +if [[ -z ${PATH_OUT} ]]; then + PATH_OUT=`find ${PATH_PROJ} -type f \( -iname ${FILE_EXTENSION_IAR} \) -exec echo {} \;` +fi + +if [[ -z ${PATH_OUT} ]]; then + echo "Error: neither ${FILE_EXTENSION_GCC} nor ${FILE_EXTENSION_IAR} found" + echo "Was the project compiled and linked successfully?" + read -rsp $'Press enter to continue...\n' + exit +fi + +if [[ ! -f "${OBJCOPY}" ]]; then + echo "Error: gcc-arm objcopy not found at '${OBJCOPY}'" + echo "Use PATH_GCCARM env var to override default path for gcc-arm." + echo "Please refer to AN1086 sections 2.3 and 3.10 on how to set the required" + echo "environmental variables." + read -rsp $'Press enter to continue...\n' + exit +fi + +if [[ ! -f "${COMMANDER}" ]]; then + echo "Error: Simplicity Commander not found at '${COMMANDER}'" + echo "Use PATH_SCMD env var to override default path for Simplicity Commander." + echo "Please refer to AN1086 sections 2.3 and 3.10 on how to set the required" + echo "environmental variables." + read -rsp $'Press enter to continue...\n' + exit +fi + +if [[ -f "$BOOTLOADER_FILE" ]]; then + echo "Bootloader file was found" +else + echo "Bootloader file was not found" + echo "---- BOOTLOADER GENERATION -------------------------------------------" + echo "For adding bootloader to apploader copy a bootloader s37 image, e.g." + echo "'bootloader-storage-internal-single.s37' to the project root folder," + echo "rename it to 'bootloader-second-stage.s37' and rerun the script file." + echo "----------------------------------------------------------------------" + echo +fi + +if [[ -f "$GBL_ENCRYPT_KEY_FILE" ]]; then + echo "Encryption key file was found" +else + echo "Encryption key file was not found" + echo "---- ENCRYPTED GBL FILE GENERATION -----------------------------------" + echo "To generate an encrypted firmware upgrade file," + echo "copy an encryption key file into the root folder of the project," + echo "rename it to 'app-encrypt-key.txt' and rerun the script file." + echo "----------------------------------------------------------------------" + echo +fi + +if [[ -f "$GBL_SIGING_KEY_FILE" ]]; then + echo "Signing key file was found" +else + echo "Signing key file was not found" + echo "---- SIGNED GBL FILE GENERATION --------------------------------------" + echo "To generate a signed firmware upgrade file," + echo "copy a signing key file into the root folder of the project," + echo "rename it to 'app-sign-key.pem' and rerun the script file." + echo "----------------------------------------------------------------------" + echo +fi + +echo "**********************************************************************" +echo "Converting .out to .gbl files" +echo "**********************************************************************" +echo +echo ".out file used:" +echo "${PATH_OUT}" +echo +echo "output folder:" +echo "${PATH_GBL}" + +mkdir -p ${PATH_GBL} + +# create the GBL files +echo +echo "**********************************************************************" +echo "Creating ${OTA_APPLO_NAME}.gbl for OTA" +echo "**********************************************************************" +echo +"${OBJCOPY}" -O srec -j .text_apploader* "${PATH_OUT}" "${PATH_GBL}/${OTA_APPLO_NAME}.srec" +if [ $? -ne 0 ]; then + read -rsp $'Press enter to continue...\n' + exit +fi +if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --bootloader ${BOOTLOADER_FILE} +else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" +fi + +echo +echo "**********************************************************************" +echo "Creating ${OTA_APPLI_NAME}.gbl for OTA" +echo "**********************************************************************" +echo +"${OBJCOPY}" -O srec -R .text_apploader* -R .text_signature* "${PATH_OUT}" "${PATH_GBL}/${OTA_APPLI_NAME}.srec" +if [ $? -ne 0 ]; then + read -rsp $'Press enter to continue...\n' + exit +fi +"${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}.srec" + +# create the full GBL files for UART DFU +echo +echo "**********************************************************************" +echo "Creating ${UARTDFU_FULL_NAME}.gbl for UART DFU" +echo "**********************************************************************" +echo +"${OBJCOPY}" -O srec -R .text_bootloader* "${PATH_OUT}" "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" +if [ $? -ne 0 ]; then + read -rsp $'Press enter to continue...\n' + exit +fi +"${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" + +# create encrypted GBL file for secure boot if encrypt-key file exist +if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then + echo + echo "**********************************************************************" + echo "Creating encrypted .gbl files" + echo "**********************************************************************" + echo + if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --bootloader ${BOOTLOADER_FILE} + else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} + fi + echo + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} + echo + "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} +fi + +# create signed GBL file for secure boot if sign-key file exists +if [[ -f $GBL_SIGING_KEY_FILE ]]; then + echo + echo "**********************************************************************" + echo "Creating signed .gbl files" + echo "**********************************************************************" + echo + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --secureboot --keyfile ${GBL_SIGING_KEY_FILE} -o "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then + if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-signed.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} --bootloader ${BOOTLOADER_FILE} + else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-signed.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} + fi + fi + echo + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --secureboot --keyfile ${GBL_SIGING_KEY_FILE} -o "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-signed.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} + echo + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" -o "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" + else + cp "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" + fi + "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" --sign ${GBL_SIGING_KEY_FILE} + + # create signed and encrypted GBL file for if both sign-key and encrypt-key file exist + if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then + echo + echo "**********************************************************************" + echo "Creating signed and encrypted .gbl files" + echo "**********************************************************************" + echo + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" ]]; then + if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} --bootloader ${BOOTLOADER_FILE} + else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} + fi + echo + fi + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} + echo + "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-signed.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --sign ${GBL_SIGING_KEY_FILE} + fi +else + echo + echo "**********************************************************************" + echo "Creating crc .gbl files" + echo "**********************************************************************" + echo + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}.srec" --crc -o "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then + if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-crc.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --bootloader ${BOOTLOADER_FILE} + else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-crc.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" + fi + fi + echo + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLI_NAME}.srec" --crc -o "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-crc.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" + echo + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then + "${COMMANDER}" convert "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" -o "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" + else + cp "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" + fi + "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" + + # create crc and encrypted GBL file if encrypt-key file exist + if [[ -f $GBL_ENCRYPT_KEY_FILE ]]; then + echo + echo "**********************************************************************" + echo "Creating crc and encrypted .gbl files" + echo "**********************************************************************" + echo + if [[ -f "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" ]]; then + if [[ -f $BOOTLOADER_FILE ]]; then + echo "Bootloader file was found" + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-bootloader-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} --bootloader ${BOOTLOADER_FILE} + else + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLO_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLO_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} + fi + echo + fi + "${COMMANDER}" gbl create "${PATH_GBL}/${OTA_APPLI_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${OTA_APPLI_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} + echo + "${COMMANDER}" gbl create "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc-encrypted.gbl" --app "${PATH_GBL}/${UARTDFU_FULL_NAME}-crc.srec" --encrypt ${GBL_ENCRYPT_KEY_FILE} + fi +fi + +# clean up output dir +rm "${PATH_GBL}"/*.srec + +read -rsp $'Press enter to continue...\n' diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.c b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.c index 10f3fcd..04f7c5f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.c +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.c @@ -1,751 +1,751 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Interface - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "em_common.h" -#include "em_core.h" -#include "sl_bluetooth.h" -#include "sl_status.h" -#include "app_assert.h" -#include "sl_simple_com.h" -#include "sl_ncp.h" -#include "sl_ncp_evt_filter.h" -#ifdef SL_COMPONENT_CATALOG_PRESENT -#include "sl_component_catalog.h" -#endif // SL_COMPONENT_CATALOG_PRESENT -#include "app_timer.h" -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -#include "sl_wake_lock.h" -#endif // SL_CATALOG_WAKE_LOCK_PRESENT -#if defined(SL_CATALOG_NCP_SEC_PRESENT) -#include "sl_ncp_sec.h" -#endif // SL_CATALOG_NCP_SEC_PRESENT -#if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) -#include "btl_interface.h" -#endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT - -// Command buffer -typedef struct { - uint16_t len; - uint8_t buf[SL_NCP_CMD_BUF_SIZE]; - bool available; -} cmd_t; - -// Event buffer -typedef struct { - uint16_t len; - uint8_t buf[SL_NCP_EVT_BUF_SIZE]; - bool available; -} evt_t; - -// Timer states -typedef enum { - CMD_IDLE = 0, - CMD_WAITING, - CMD_RECEIVED -} timer_state_t; - -static cmd_t cmd = { 0 }; -static evt_t evt = { 0 }; -static bool busy = false; -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -// semaphore to disable sleep prematurely -static uint8_t sleep_semaphore = 0; -// upper bits are flags to store signal value and wait until first cmd is received -#define SLEEP_SIGNAL_PRESENT 0x80 -#define SLEEP_WAITING_FIRST_RX 0x40 -#define SLEEP_SIGNAL_MASK SLEEP_WAITING_FIRST_RX | SLEEP_SIGNAL_PRESENT -#endif // SL_CATALOG_WAKE_LOCK_PRESENT - -#define MSG_GET_LEN(x) ((uint16_t)(SL_BT_MSG_LEN((x)->header) \ - + SL_BT_MSG_HEADER_LEN)) - -static bool handle_user_command(uint32_t hdr, void *data); - -// Command and event buffer helper functions -static void cmd_enqueue(uint16_t len, uint8_t *data); -static void cmd_dequeue(void); -static void evt_enqueue(uint16_t len, uint8_t *data); -static void evt_dequeue(void); - -// Command and event helper functions -static inline bool cmd_is_available(void); -static inline void cmd_set_available(void); -static inline void cmd_clr_available(void); -static inline bool evt_is_available(void); -static inline void evt_set_available(void); -static inline void evt_clr_available(void); - -// Timer handle and callback for command timeout. -static app_timer_t cmd_timer; -static void cmd_timer_cb(app_timer_t *timer, void *data); - -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -static inline bool sleep_signal_mask_is_set(void); -static inline void sleep_signal_mask_set(void); -static inline void sleep_signal_flag_clr(void); -static inline void sleep_signal_wait_clr(void); -#endif // SL_CATALOG_WAKE_LOCK_PRESENT - -// ----------------------------------------------------------------------------- -// Public functions (API implementation) - -/**************************************************************************//** - * Ncp Initialization function. - *****************************************************************************/ -void sl_ncp_init(void) -{ - // Clear all buffers - cmd_dequeue(); - evt_dequeue(); - - // Start reception - sl_simple_com_receive(); - busy = false; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - sleep_semaphore = 0; - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - - sl_ncp_os_task_init(); -} - -/**************************************************************************//** - * Ncp process action function. - * - * @note Called through sl_system_process_action - *****************************************************************************/ -void sl_ncp_step(void) -{ - // ------------------------------- - // Command available and NCP not busy - if (cmd_is_available() && !busy) { - sl_bt_msg_t *command = (sl_bt_msg_t *)cmd.buf; - sl_bt_msg_t *response; - - #if defined(SL_CATALOG_NCP_SEC_PRESENT) - uint32_t result = 0; - // store if cmd was encrypted during reception for further processing - bool cmd_is_encrypted = sl_ncp_sec_is_encrypted(&cmd.buf); - result = sl_ncp_sec_command_handler((uint8_t*)&cmd.buf); - if ((result & SL_NCP_SEC_CMD_PROCESS) == SL_NCP_SEC_CMD_PROCESS) - #endif // SL_CATALOG_NCP_SEC_PRESENT - { - cmd_clr_available(); - // Check for user command - if (!handle_user_command(command->header, command->data.payload)) { - // Call Bluetooth API binary command handler - sl_bt_handle_command(command->header, command->data.payload); - } - } - #if defined(SL_CATALOG_NCP_SEC_PRESENT) - if ((result & SL_NCP_SEC_EVT_PROCESS) == SL_NCP_SEC_EVT_PROCESS) { - // Clear command buffer - cmd_dequeue(); - } else if ((result & SL_NCP_SEC_RSP_PROCESS) - == SL_NCP_SEC_RSP_PROCESS) { - response = sl_ncp_sec_process_response( - sl_bt_get_command_response(), cmd_is_encrypted); - #else - { - response = sl_bt_get_command_response(); - #endif // SL_CATALOG_NCP_SEC_PRESENT - // Clear command buffer - cmd_dequeue(); - busy = true; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Wake up other controller - sl_wake_lock_set_remote_req(); - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - // Transmit command response - sl_simple_com_transmit((uint32_t)(MSG_GET_LEN(response)), - (uint8_t *)response); - } - } - - // ------------------------------- - // Event available and NCP not busy - if (evt_is_available() && !busy) { - evt_clr_available(); - busy = true; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Wake up other controller - sl_wake_lock_set_remote_req(); - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - - uint8_t *data_ptr = evt.buf; - uint16_t len = evt.len; - - #if defined(SL_CATALOG_NCP_SEC_PRESENT) - // encrypt the outgoing event - data_ptr = (uint8_t*)sl_ncp_sec_process_event((sl_bt_msg_t*)evt.buf); - app_assert(data_ptr, "Error during event encryption.\n"); - // refresh original len as encrypted msg will be longer than original - len = MSG_GET_LEN((sl_bt_msg_t*)data_ptr); - #endif // SL_CATALOG_NCP_SEC_PRESENT - - // Transmit events - sl_simple_com_transmit((uint32_t)len, data_ptr); - // Clear event buffer - evt_dequeue(); - } -} - -/**************************************************************************//** - * Local event processor. - * - * Use this function to process Bluetooth stack events locally on NCP. - * Set the return value to true, if the event should be forwarded to the - * NCP-host. Otherwise, the event is discarded locally. - * Implement your own function to override this default weak implementation. - * - * @param[in] evt The event. - * - * @return true, if we shall send the event to the host. This is the default. - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK bool sl_ncp_local_evt_process(sl_bt_msg_t *evt) -{ - (void)evt; - return true; -} - -#if defined(SL_CATALOG_BTMESH_PRESENT) - -/**************************************************************************//** - * Local event processor. - * - * Use this function to process Bluetooth Mesh stack events locally on NCP. - * Set the return value to true, if the event should be forwarded to the - * NCP-host. Otherwise, the event is discarded locally. - * Implement your own function to override this default weak implementation. - * - * @param[in] evt The event. - * - * @return true, if we shall send the event to the host. This is the default. - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK bool sl_ncp_local_btmesh_evt_process(sl_btmesh_msg_t *evt) -{ - (void)evt; - return true; -} - -#endif - -/**************************************************************************//** - * User command (message_to_target) handler callback. - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK void sl_ncp_user_cmd_message_to_target_cb(void *data) -{ - (void)data; -} - -/**************************************************************************//** - * Send user command (message_to_target) response. - *****************************************************************************/ -void sl_ncp_user_cmd_message_to_target_rsp(sl_status_t result, - uint8_t len, - uint8_t *data) -{ - sl_bt_send_rsp_user_message_to_target(result, len, data); -} - -/**************************************************************************//** - * Send user event (message_to_host). - *****************************************************************************/ -void sl_ncp_user_evt_message_to_host(uint8_t len, uint8_t *data) -{ - sl_bt_send_evt_user_message_to_host(len, data); -} - -/**************************************************************************//** - * Handle a user API command in binary format. - * - * @param[in] hdr the command header. - * @param[in] data the command payload in a byte array - * - * @retval true User command handled. - * @retval false No user command found. - *****************************************************************************/ -static bool handle_user_command(uint32_t hdr, void *data) -{ - bool cmd_handled = true; - - switch (SL_BT_MSG_ID(hdr)) { - // ------------------------------- - case sl_bt_cmd_user_message_to_target_id: - if (((uint8array *)data)->len > 0) { - sl_ncp_user_cmd_message_to_target_cb(data); - } else { - sl_bt_send_rsp_user_message_to_target(SL_STATUS_FAIL, 0, NULL); - } - break; - // ------------------------------- - case sl_bt_cmd_user_manage_event_filter_id: - if (((uint8array *)data)->len > 0) { - sl_ncp_evt_filter_handler((user_cmd_manage_event_filter_t *)data); - } else { - sl_bt_send_rsp_user_manage_event_filter(SL_STATUS_FAIL); - } - break; - // ------------------------------- - case sl_bt_cmd_user_reset_to_dfu_id: - #if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) - bootloader_rebootAndInstall(); - #endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT - break; - // ------------------------------- - default: - cmd_handled = false; - break; - } - return cmd_handled; -} - -// ----------------------------------------------------------------------------- -// Functions used for communication between stack and Uart - -/**************************************************************************//** - * Bluetooth stack event handler. - * - * This overrides the dummy weak implementation. - * - * @param[in] evt Event coming from the Bluetooth stack. - *****************************************************************************/ -void sl_bt_on_event(sl_bt_msg_t *evt) -{ - if (!sl_ncp_evt_filter_is_filtered((uint32_t)SL_BT_MSG_ID(evt->header))) { - if (sl_ncp_local_evt_process(evt)) { - // Enqueue event - evt_enqueue(MSG_GET_LEN(evt), - (uint8_t *)evt); - sl_ncp_os_task_proceed(); - } - } -} - -#if defined(SL_CATALOG_BTMESH_PRESENT) - -/**************************************************************************//** - * Bluetooth mesh stack event handler. - * - * This overrides the dummy weak implementation. - * - * @param[in] evt Event coming from the Bluetooth Mesh stack. - *****************************************************************************/ -void sl_btmesh_on_event(sl_btmesh_msg_t *evt) -{ - if (!sl_ncp_evt_filter_is_filtered((uint32_t)SL_BT_MSG_ID(evt->header))) { - if (sl_ncp_local_btmesh_evt_process(evt)) { - // Enqueue event - evt_enqueue(MSG_GET_LEN(evt), - (uint8_t *)evt); - sl_ncp_os_task_proceed(); - } - } -} -#endif - -/**************************************************************************//** - * Signal if ncp application can process a new received event. - * - * Called before putting event into event buffer. - * - * @param[in] len Message length - * - * @return True if message fits into buffer, otherwise false. - *****************************************************************************/ -static inline bool sl_ncp_can_process_event(uint32_t len) -{ - bool ret = false; - // event fits into event buffer; otherwise don't pop it from queue - if ((len <= (uint32_t)(sizeof(evt.buf) - evt.len)) && !evt_is_available() - && !cmd_is_available()) { - ret = true; - } - return ret; -} - -/**************************************************************************//** - * Signal if bluetooth stack can process a new received event. - * - * @param[in] len Message length - * - * @return True if message fits into buffer, otherwise false. - *****************************************************************************/ -bool sl_bt_can_process_event(uint32_t len) -{ - return sl_ncp_can_process_event(len); -} - -#if defined(SL_CATALOG_BTMESH_PRESENT) -/**************************************************************************//** - * Signal if bluetooth mesh stack can process a new received event. - * - * @param[in] len Message length - * - * @return True if message fits into buffer, otherwise false. - *****************************************************************************/ -bool sl_btmesh_can_process_event(uint32_t len) -{ - return sl_ncp_can_process_event(len); -} -#endif - -/**************************************************************************//** - * Uart transmit completed callback - * - * Called after Uart transmit is finished. - * - * @param[in] status Status of the transmission - *****************************************************************************/ -void sl_simple_com_transmit_cb(sl_status_t status) -{ - (void)status; - - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Signal other controller that it can go to sleep - sl_wake_lock_clear_remote_req(); - - // Command response completed, go to sleep if possible - if (sleep_signal_mask_is_set()) { - // Only decrease semaphore if a command was received before - // i.e. not an event was sent out - sleep_semaphore--; - if (!sleep_semaphore) { - // Go to sleep if signal is down and command answered - sl_wake_lock_set_local(); - } - } - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - busy = false; - sl_ncp_os_task_proceed(); -} - -/**************************************************************************//** - * Uart receive completed callback - * - * Called after Uart receive is finished. - * - * @param[in] status Status of the reception - * @param[in] len Received message length - * @param[in] data Data received - *****************************************************************************/ -void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data) -{ - (void)status; - // Stop on communication error - app_assert_status_f(status, - "Receive error. Received %d bytes.\n", - (int)len); - // Copy command into buffer - cmd_enqueue((uint16_t)len, data); - sl_ncp_os_task_proceed(); -} - -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -/**************************************************************************//** - * Wake-up signal arrived from host. - * This overrides the dummy weak implementation. - *****************************************************************************/ -void sl_wake_lock_set_req_rx_cb(void) -{ - // Other end set wake-up pin, so set signaling flag. Also signal that at least - // one command needs to be received and processed before sleep. - sleep_signal_mask_set(); - sl_bt_send_system_awake(); -} - -/**************************************************************************//** - * Go to sleep signal arrived from host. - * This overrides the dummy weak implementation. - *****************************************************************************/ -void sl_wake_lock_clear_req_rx_cb(void) -{ - // Other end released pin, remove signaling flag - sleep_signal_flag_clr(); - - if (!sleep_semaphore) { - // Go to sleep if signal is down and command answered - sl_wake_lock_set_local(); - } -} -#endif // SL_CATALOG_WAKE_LOCK_PRESENT - -// ----------------------------------------------------------------------------- -// Power manager related functions - -/**************************************************************************//** - * Check if NCP allows go to sleep - *****************************************************************************/ -bool sli_ncp_is_ok_to_sleep(void) -{ - bool result; - - result = !cmd_is_available() && !evt_is_available() && !busy; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - result = result && !sleep_semaphore; - #endif - return result; -} -/**************************************************************************//** - * Routine for power manager handler - *****************************************************************************/ -sl_power_manager_on_isr_exit_t sli_ncp_sleep_on_isr_exit(void) -{ - if (sli_ncp_is_ok_to_sleep() == false) { - return SL_POWER_MANAGER_WAKEUP; - } - return SL_POWER_MANAGER_IGNORE; -} - -// ----------------------------------------------------------------------------- -// Command and event buffer handling functions - -/**************************************************************************//** - * Put command to command buffer - * - * @param[in] len Command length - * @param[in] data Command data - *****************************************************************************/ -static void cmd_enqueue(uint16_t len, uint8_t *data) -{ - sl_status_t sc; - timer_state_t state = CMD_IDLE; - - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - // Command fits into command buffer; otherwise discard it. - if (len <= (sizeof(cmd.buf) - cmd.len)) { - memcpy((void *)&cmd.buf[cmd.len], (void *)data, (size_t)len); - cmd.len += len; - // Part of the command received, start timer to not get stuck. - state = CMD_WAITING; - // Command header has been received. - if (cmd.len >= SL_BT_MSG_HEADER_LEN) { - // 4-byte header + len bytes payload - uint32_t len = SL_BT_MSG_LEN(*(uint32_t *)cmd.buf) + SL_BT_MSG_HEADER_LEN; - if (cmd.len >= len) { - // Command has been received entirely. - cmd_set_available(); - state = CMD_RECEIVED; - #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) - // Command received fully, increase semaphore. - sleep_semaphore++; - // Also signal that a command was received, system can go to sleep after - sleep_signal_wait_clr(); - #endif // SL_CATALOG_WAKE_LOCK_PRESENT - } - } - } - CORE_EXIT_ATOMIC(); - - if (state == CMD_RECEIVED) { - // Stop timer as the whole command was received. No problem if timer was - // not started before, app_timer is prepared for that. - sc = app_timer_stop(&cmd_timer); - - app_assert_status(sc); - } else if (state == CMD_WAITING) { - // Start timer used for max waiting time of fragmented packets. - sc = app_timer_start(&cmd_timer, - SL_NCP_CMD_TIMEOUT_MS, - cmd_timer_cb, - NULL, - false); - app_assert_status(sc); - } -} - -/**************************************************************************//** - * Clear command buffer - *****************************************************************************/ -static void cmd_dequeue(void) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - cmd.len = 0; - cmd_clr_available(); - CORE_EXIT_ATOMIC(); -} - -/**************************************************************************//** - * Put event to event buffer - * - * @param[in] len Event length - * @param[in] data Event data - *****************************************************************************/ -static void evt_enqueue(uint16_t len, uint8_t *data) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - // event fits into event buffer; otherwise discard it - if (len <= (sizeof(evt.buf) - evt.len)) { - memcpy((void *)&evt.buf[evt.len], (void *)data, len); - evt.len += len; - evt_set_available(); - } - CORE_EXIT_ATOMIC(); -} - -/**************************************************************************//** - * Clear event buffer - *****************************************************************************/ -static void evt_dequeue(void) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - evt.len = 0; - evt_clr_available(); - CORE_EXIT_ATOMIC(); -} - -// ----------------------------------------------------------------------------- -// Timer callback function - -static void cmd_timer_cb(app_timer_t *timer, void *data) -{ - (void)data; - (void)timer; - - // Signal the other end that the command was received only partially - // then clean buffer. The timer is already stopped. - sl_bt_send_system_error(SL_STATUS_COMMAND_INCOMPLETE, 0, NULL); - cmd_dequeue(); -} - -// ----------------------------------------------------------------------------- -// Helper functions - -/**************************************************************************//** - * Get command availability in command buffer - *****************************************************************************/ -static inline bool cmd_is_available(void) -{ - return cmd.available; -} - -/**************************************************************************//** - * Set command available in command buffer - *****************************************************************************/ -static inline void cmd_set_available(void) -{ - cmd.available = true; -} - -/**************************************************************************//** - * Clear command available in command buffer - *****************************************************************************/ -static inline void cmd_clr_available(void) -{ - cmd.available = false; -} - -/**************************************************************************//** - * Get event availability in command buffer - *****************************************************************************/ -static inline bool evt_is_available(void) -{ - return evt.available; -} - -/**************************************************************************//** - * Set event available in command buffer - *****************************************************************************/ -static inline void evt_set_available(void) -{ - evt.available = true; -} - -/**************************************************************************//** - * Clear event available in command buffer - *****************************************************************************/ -static inline void evt_clr_available(void) -{ - evt.available = false; -} - -/**************************************************************************//** - * OS initialization function - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK void sl_ncp_os_task_init(void) -{ - // No action on bare metal implementation -} - -/**************************************************************************//** - * Function to trigger the OS task to proceed - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK void sl_ncp_os_task_proceed(void) -{ - // No action on bare metal implementation -} - -#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) -/**************************************************************************//** - * Get sleep signal flag and wait for rx cmd flag state - *****************************************************************************/ -static inline bool sleep_signal_mask_is_set(void) -{ - return (sleep_semaphore & ~(SLEEP_SIGNAL_MASK)); -} - -/**************************************************************************//** - * Set sleep signal flag and wait for rx cmd flag state - *****************************************************************************/ -static inline void sleep_signal_mask_set(void) -{ - sleep_semaphore |= (SLEEP_SIGNAL_PRESENT | SLEEP_WAITING_FIRST_RX); -} - -/**************************************************************************//** - * Clear sleep signal flag state - *****************************************************************************/ -static inline void sleep_signal_flag_clr(void) -{ - sleep_semaphore &= ~(SLEEP_SIGNAL_PRESENT); -} - -/**************************************************************************//** - * Clear wait for rx cmd flag state - *****************************************************************************/ -static inline void sleep_signal_wait_clr(void) -{ - sleep_semaphore &= ~(SLEEP_WAITING_FIRST_RX); -} -#endif // SL_CATALOG_WAKE_LOCK_PRESENT +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Interface + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "em_common.h" +#include "em_core.h" +#include "sl_bluetooth.h" +#include "sl_status.h" +#include "app_assert.h" +#include "sl_simple_com.h" +#include "sl_ncp.h" +#include "sl_ncp_evt_filter.h" +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#endif // SL_COMPONENT_CATALOG_PRESENT +#include "app_timer.h" +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +#include "sl_wake_lock.h" +#endif // SL_CATALOG_WAKE_LOCK_PRESENT +#if defined(SL_CATALOG_NCP_SEC_PRESENT) +#include "sl_ncp_sec.h" +#endif // SL_CATALOG_NCP_SEC_PRESENT +#if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) +#include "btl_interface.h" +#endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT + +// Command buffer +typedef struct { + uint16_t len; + uint8_t buf[SL_NCP_CMD_BUF_SIZE]; + bool available; +} cmd_t; + +// Event buffer +typedef struct { + uint16_t len; + uint8_t buf[SL_NCP_EVT_BUF_SIZE]; + bool available; +} evt_t; + +// Timer states +typedef enum { + CMD_IDLE = 0, + CMD_WAITING, + CMD_RECEIVED +} timer_state_t; + +static cmd_t cmd = { 0 }; +static evt_t evt = { 0 }; +static bool busy = false; +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +// semaphore to disable sleep prematurely +static uint8_t sleep_semaphore = 0; +// upper bits are flags to store signal value and wait until first cmd is received +#define SLEEP_SIGNAL_PRESENT 0x80 +#define SLEEP_WAITING_FIRST_RX 0x40 +#define SLEEP_SIGNAL_MASK SLEEP_WAITING_FIRST_RX | SLEEP_SIGNAL_PRESENT +#endif // SL_CATALOG_WAKE_LOCK_PRESENT + +#define MSG_GET_LEN(x) ((uint16_t)(SL_BT_MSG_LEN((x)->header) \ + + SL_BT_MSG_HEADER_LEN)) + +static bool handle_user_command(uint32_t hdr, void *data); + +// Command and event buffer helper functions +static void cmd_enqueue(uint16_t len, uint8_t *data); +static void cmd_dequeue(void); +static void evt_enqueue(uint16_t len, uint8_t *data); +static void evt_dequeue(void); + +// Command and event helper functions +static inline bool cmd_is_available(void); +static inline void cmd_set_available(void); +static inline void cmd_clr_available(void); +static inline bool evt_is_available(void); +static inline void evt_set_available(void); +static inline void evt_clr_available(void); + +// Timer handle and callback for command timeout. +static app_timer_t cmd_timer; +static void cmd_timer_cb(app_timer_t *timer, void *data); + +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +static inline bool sleep_signal_mask_is_set(void); +static inline void sleep_signal_mask_set(void); +static inline void sleep_signal_flag_clr(void); +static inline void sleep_signal_wait_clr(void); +#endif // SL_CATALOG_WAKE_LOCK_PRESENT + +// ----------------------------------------------------------------------------- +// Public functions (API implementation) + +/**************************************************************************//** + * Ncp Initialization function. + *****************************************************************************/ +void sl_ncp_init(void) +{ + // Clear all buffers + cmd_dequeue(); + evt_dequeue(); + + // Start reception + sl_simple_com_receive(); + busy = false; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + sleep_semaphore = 0; + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + + sl_ncp_os_task_init(); +} + +/**************************************************************************//** + * Ncp process action function. + * + * @note Called through sl_system_process_action + *****************************************************************************/ +void sl_ncp_step(void) +{ + // ------------------------------- + // Command available and NCP not busy + if (cmd_is_available() && !busy) { + sl_bt_msg_t *command = (sl_bt_msg_t *)cmd.buf; + sl_bt_msg_t *response; + + #if defined(SL_CATALOG_NCP_SEC_PRESENT) + uint32_t result = 0; + // store if cmd was encrypted during reception for further processing + bool cmd_is_encrypted = sl_ncp_sec_is_encrypted(&cmd.buf); + result = sl_ncp_sec_command_handler((uint8_t*)&cmd.buf); + if ((result & SL_NCP_SEC_CMD_PROCESS) == SL_NCP_SEC_CMD_PROCESS) + #endif // SL_CATALOG_NCP_SEC_PRESENT + { + cmd_clr_available(); + // Check for user command + if (!handle_user_command(command->header, command->data.payload)) { + // Call Bluetooth API binary command handler + sl_bt_handle_command(command->header, command->data.payload); + } + } + #if defined(SL_CATALOG_NCP_SEC_PRESENT) + if ((result & SL_NCP_SEC_EVT_PROCESS) == SL_NCP_SEC_EVT_PROCESS) { + // Clear command buffer + cmd_dequeue(); + } else if ((result & SL_NCP_SEC_RSP_PROCESS) + == SL_NCP_SEC_RSP_PROCESS) { + response = sl_ncp_sec_process_response( + sl_bt_get_command_response(), cmd_is_encrypted); + #else + { + response = sl_bt_get_command_response(); + #endif // SL_CATALOG_NCP_SEC_PRESENT + // Clear command buffer + cmd_dequeue(); + busy = true; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Wake up other controller + sl_wake_lock_set_remote_req(); + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + // Transmit command response + sl_simple_com_transmit((uint32_t)(MSG_GET_LEN(response)), + (uint8_t *)response); + } + } + + // ------------------------------- + // Event available and NCP not busy + if (evt_is_available() && !busy) { + evt_clr_available(); + busy = true; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Wake up other controller + sl_wake_lock_set_remote_req(); + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + + uint8_t *data_ptr = evt.buf; + uint16_t len = evt.len; + + #if defined(SL_CATALOG_NCP_SEC_PRESENT) + // encrypt the outgoing event + data_ptr = (uint8_t*)sl_ncp_sec_process_event((sl_bt_msg_t*)evt.buf); + app_assert(data_ptr, "Error during event encryption.\n"); + // refresh original len as encrypted msg will be longer than original + len = MSG_GET_LEN((sl_bt_msg_t*)data_ptr); + #endif // SL_CATALOG_NCP_SEC_PRESENT + + // Transmit events + sl_simple_com_transmit((uint32_t)len, data_ptr); + // Clear event buffer + evt_dequeue(); + } +} + +/**************************************************************************//** + * Local event processor. + * + * Use this function to process Bluetooth stack events locally on NCP. + * Set the return value to true, if the event should be forwarded to the + * NCP-host. Otherwise, the event is discarded locally. + * Implement your own function to override this default weak implementation. + * + * @param[in] evt The event. + * + * @return true, if we shall send the event to the host. This is the default. + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK bool sl_ncp_local_evt_process(sl_bt_msg_t *evt) +{ + (void)evt; + return true; +} + +#if defined(SL_CATALOG_BTMESH_PRESENT) + +/**************************************************************************//** + * Local event processor. + * + * Use this function to process Bluetooth Mesh stack events locally on NCP. + * Set the return value to true, if the event should be forwarded to the + * NCP-host. Otherwise, the event is discarded locally. + * Implement your own function to override this default weak implementation. + * + * @param[in] evt The event. + * + * @return true, if we shall send the event to the host. This is the default. + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK bool sl_ncp_local_btmesh_evt_process(sl_btmesh_msg_t *evt) +{ + (void)evt; + return true; +} + +#endif + +/**************************************************************************//** + * User command (message_to_target) handler callback. + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK void sl_ncp_user_cmd_message_to_target_cb(void *data) +{ + (void)data; +} + +/**************************************************************************//** + * Send user command (message_to_target) response. + *****************************************************************************/ +void sl_ncp_user_cmd_message_to_target_rsp(sl_status_t result, + uint8_t len, + uint8_t *data) +{ + sl_bt_send_rsp_user_message_to_target(result, len, data); +} + +/**************************************************************************//** + * Send user event (message_to_host). + *****************************************************************************/ +void sl_ncp_user_evt_message_to_host(uint8_t len, uint8_t *data) +{ + sl_bt_send_evt_user_message_to_host(len, data); +} + +/**************************************************************************//** + * Handle a user API command in binary format. + * + * @param[in] hdr the command header. + * @param[in] data the command payload in a byte array + * + * @retval true User command handled. + * @retval false No user command found. + *****************************************************************************/ +static bool handle_user_command(uint32_t hdr, void *data) +{ + bool cmd_handled = true; + + switch (SL_BT_MSG_ID(hdr)) { + // ------------------------------- + case sl_bt_cmd_user_message_to_target_id: + if (((uint8array *)data)->len > 0) { + sl_ncp_user_cmd_message_to_target_cb(data); + } else { + sl_bt_send_rsp_user_message_to_target(SL_STATUS_FAIL, 0, NULL); + } + break; + // ------------------------------- + case sl_bt_cmd_user_manage_event_filter_id: + if (((uint8array *)data)->len > 0) { + sl_ncp_evt_filter_handler((user_cmd_manage_event_filter_t *)data); + } else { + sl_bt_send_rsp_user_manage_event_filter(SL_STATUS_FAIL); + } + break; + // ------------------------------- + case sl_bt_cmd_user_reset_to_dfu_id: + #if defined(SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT) + bootloader_rebootAndInstall(); + #endif // SL_CATALOG_GECKO_BOOTLOADER_INTERFACE_PRESENT + break; + // ------------------------------- + default: + cmd_handled = false; + break; + } + return cmd_handled; +} + +// ----------------------------------------------------------------------------- +// Functions used for communication between stack and Uart + +/**************************************************************************//** + * Bluetooth stack event handler. + * + * This overrides the dummy weak implementation. + * + * @param[in] evt Event coming from the Bluetooth stack. + *****************************************************************************/ +void sl_bt_on_event(sl_bt_msg_t *evt) +{ + if (!sl_ncp_evt_filter_is_filtered((uint32_t)SL_BT_MSG_ID(evt->header))) { + if (sl_ncp_local_evt_process(evt)) { + // Enqueue event + evt_enqueue(MSG_GET_LEN(evt), + (uint8_t *)evt); + sl_ncp_os_task_proceed(); + } + } +} + +#if defined(SL_CATALOG_BTMESH_PRESENT) + +/**************************************************************************//** + * Bluetooth mesh stack event handler. + * + * This overrides the dummy weak implementation. + * + * @param[in] evt Event coming from the Bluetooth Mesh stack. + *****************************************************************************/ +void sl_btmesh_on_event(sl_btmesh_msg_t *evt) +{ + if (!sl_ncp_evt_filter_is_filtered((uint32_t)SL_BT_MSG_ID(evt->header))) { + if (sl_ncp_local_btmesh_evt_process(evt)) { + // Enqueue event + evt_enqueue(MSG_GET_LEN(evt), + (uint8_t *)evt); + sl_ncp_os_task_proceed(); + } + } +} +#endif + +/**************************************************************************//** + * Signal if ncp application can process a new received event. + * + * Called before putting event into event buffer. + * + * @param[in] len Message length + * + * @return True if message fits into buffer, otherwise false. + *****************************************************************************/ +static inline bool sl_ncp_can_process_event(uint32_t len) +{ + bool ret = false; + // event fits into event buffer; otherwise don't pop it from queue + if ((len <= (uint32_t)(sizeof(evt.buf) - evt.len)) && !evt_is_available() + && !cmd_is_available()) { + ret = true; + } + return ret; +} + +/**************************************************************************//** + * Signal if bluetooth stack can process a new received event. + * + * @param[in] len Message length + * + * @return True if message fits into buffer, otherwise false. + *****************************************************************************/ +bool sl_bt_can_process_event(uint32_t len) +{ + return sl_ncp_can_process_event(len); +} + +#if defined(SL_CATALOG_BTMESH_PRESENT) +/**************************************************************************//** + * Signal if bluetooth mesh stack can process a new received event. + * + * @param[in] len Message length + * + * @return True if message fits into buffer, otherwise false. + *****************************************************************************/ +bool sl_btmesh_can_process_event(uint32_t len) +{ + return sl_ncp_can_process_event(len); +} +#endif + +/**************************************************************************//** + * Uart transmit completed callback + * + * Called after Uart transmit is finished. + * + * @param[in] status Status of the transmission + *****************************************************************************/ +void sl_simple_com_transmit_cb(sl_status_t status) +{ + (void)status; + + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Signal other controller that it can go to sleep + sl_wake_lock_clear_remote_req(); + + // Command response completed, go to sleep if possible + if (sleep_signal_mask_is_set()) { + // Only decrease semaphore if a command was received before + // i.e. not an event was sent out + sleep_semaphore--; + if (!sleep_semaphore) { + // Go to sleep if signal is down and command answered + sl_wake_lock_set_local(); + } + } + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + busy = false; + sl_ncp_os_task_proceed(); +} + +/**************************************************************************//** + * Uart receive completed callback + * + * Called after Uart receive is finished. + * + * @param[in] status Status of the reception + * @param[in] len Received message length + * @param[in] data Data received + *****************************************************************************/ +void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data) +{ + (void)status; + // Stop on communication error + app_assert_status_f(status, + "Receive error. Received %d bytes.\n", + (int)len); + // Copy command into buffer + cmd_enqueue((uint16_t)len, data); + sl_ncp_os_task_proceed(); +} + +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +/**************************************************************************//** + * Wake-up signal arrived from host. + * This overrides the dummy weak implementation. + *****************************************************************************/ +void sl_wake_lock_set_req_rx_cb(void) +{ + // Other end set wake-up pin, so set signaling flag. Also signal that at least + // one command needs to be received and processed before sleep. + sleep_signal_mask_set(); + sl_bt_send_system_awake(); +} + +/**************************************************************************//** + * Go to sleep signal arrived from host. + * This overrides the dummy weak implementation. + *****************************************************************************/ +void sl_wake_lock_clear_req_rx_cb(void) +{ + // Other end released pin, remove signaling flag + sleep_signal_flag_clr(); + + if (!sleep_semaphore) { + // Go to sleep if signal is down and command answered + sl_wake_lock_set_local(); + } +} +#endif // SL_CATALOG_WAKE_LOCK_PRESENT + +// ----------------------------------------------------------------------------- +// Power manager related functions + +/**************************************************************************//** + * Check if NCP allows go to sleep + *****************************************************************************/ +bool sli_ncp_is_ok_to_sleep(void) +{ + bool result; + + result = !cmd_is_available() && !evt_is_available() && !busy; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + result = result && !sleep_semaphore; + #endif + return result; +} +/**************************************************************************//** + * Routine for power manager handler + *****************************************************************************/ +sl_power_manager_on_isr_exit_t sli_ncp_sleep_on_isr_exit(void) +{ + if (sli_ncp_is_ok_to_sleep() == false) { + return SL_POWER_MANAGER_WAKEUP; + } + return SL_POWER_MANAGER_IGNORE; +} + +// ----------------------------------------------------------------------------- +// Command and event buffer handling functions + +/**************************************************************************//** + * Put command to command buffer + * + * @param[in] len Command length + * @param[in] data Command data + *****************************************************************************/ +static void cmd_enqueue(uint16_t len, uint8_t *data) +{ + sl_status_t sc; + timer_state_t state = CMD_IDLE; + + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + // Command fits into command buffer; otherwise discard it. + if (len <= (sizeof(cmd.buf) - cmd.len)) { + memcpy((void *)&cmd.buf[cmd.len], (void *)data, (size_t)len); + cmd.len += len; + // Part of the command received, start timer to not get stuck. + state = CMD_WAITING; + // Command header has been received. + if (cmd.len >= SL_BT_MSG_HEADER_LEN) { + // 4-byte header + len bytes payload + uint32_t len = SL_BT_MSG_LEN(*(uint32_t *)cmd.buf) + SL_BT_MSG_HEADER_LEN; + if (cmd.len >= len) { + // Command has been received entirely. + cmd_set_available(); + state = CMD_RECEIVED; + #if defined(SL_CATALOG_WAKE_LOCK_PRESENT) + // Command received fully, increase semaphore. + sleep_semaphore++; + // Also signal that a command was received, system can go to sleep after + sleep_signal_wait_clr(); + #endif // SL_CATALOG_WAKE_LOCK_PRESENT + } + } + } + CORE_EXIT_ATOMIC(); + + if (state == CMD_RECEIVED) { + // Stop timer as the whole command was received. No problem if timer was + // not started before, app_timer is prepared for that. + sc = app_timer_stop(&cmd_timer); + + app_assert_status(sc); + } else if (state == CMD_WAITING) { + // Start timer used for max waiting time of fragmented packets. + sc = app_timer_start(&cmd_timer, + SL_NCP_CMD_TIMEOUT_MS, + cmd_timer_cb, + NULL, + false); + app_assert_status(sc); + } +} + +/**************************************************************************//** + * Clear command buffer + *****************************************************************************/ +static void cmd_dequeue(void) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + cmd.len = 0; + cmd_clr_available(); + CORE_EXIT_ATOMIC(); +} + +/**************************************************************************//** + * Put event to event buffer + * + * @param[in] len Event length + * @param[in] data Event data + *****************************************************************************/ +static void evt_enqueue(uint16_t len, uint8_t *data) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + // event fits into event buffer; otherwise discard it + if (len <= (sizeof(evt.buf) - evt.len)) { + memcpy((void *)&evt.buf[evt.len], (void *)data, len); + evt.len += len; + evt_set_available(); + } + CORE_EXIT_ATOMIC(); +} + +/**************************************************************************//** + * Clear event buffer + *****************************************************************************/ +static void evt_dequeue(void) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + evt.len = 0; + evt_clr_available(); + CORE_EXIT_ATOMIC(); +} + +// ----------------------------------------------------------------------------- +// Timer callback function + +static void cmd_timer_cb(app_timer_t *timer, void *data) +{ + (void)data; + (void)timer; + + // Signal the other end that the command was received only partially + // then clean buffer. The timer is already stopped. + sl_bt_send_system_error(SL_STATUS_COMMAND_INCOMPLETE, 0, NULL); + cmd_dequeue(); +} + +// ----------------------------------------------------------------------------- +// Helper functions + +/**************************************************************************//** + * Get command availability in command buffer + *****************************************************************************/ +static inline bool cmd_is_available(void) +{ + return cmd.available; +} + +/**************************************************************************//** + * Set command available in command buffer + *****************************************************************************/ +static inline void cmd_set_available(void) +{ + cmd.available = true; +} + +/**************************************************************************//** + * Clear command available in command buffer + *****************************************************************************/ +static inline void cmd_clr_available(void) +{ + cmd.available = false; +} + +/**************************************************************************//** + * Get event availability in command buffer + *****************************************************************************/ +static inline bool evt_is_available(void) +{ + return evt.available; +} + +/**************************************************************************//** + * Set event available in command buffer + *****************************************************************************/ +static inline void evt_set_available(void) +{ + evt.available = true; +} + +/**************************************************************************//** + * Clear event available in command buffer + *****************************************************************************/ +static inline void evt_clr_available(void) +{ + evt.available = false; +} + +/**************************************************************************//** + * OS initialization function + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK void sl_ncp_os_task_init(void) +{ + // No action on bare metal implementation +} + +/**************************************************************************//** + * Function to trigger the OS task to proceed + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK void sl_ncp_os_task_proceed(void) +{ + // No action on bare metal implementation +} + +#if defined(SL_CATALOG_WAKE_LOCK_PRESENT) +/**************************************************************************//** + * Get sleep signal flag and wait for rx cmd flag state + *****************************************************************************/ +static inline bool sleep_signal_mask_is_set(void) +{ + return (sleep_semaphore & ~(SLEEP_SIGNAL_MASK)); +} + +/**************************************************************************//** + * Set sleep signal flag and wait for rx cmd flag state + *****************************************************************************/ +static inline void sleep_signal_mask_set(void) +{ + sleep_semaphore |= (SLEEP_SIGNAL_PRESENT | SLEEP_WAITING_FIRST_RX); +} + +/**************************************************************************//** + * Clear sleep signal flag state + *****************************************************************************/ +static inline void sleep_signal_flag_clr(void) +{ + sleep_semaphore &= ~(SLEEP_SIGNAL_PRESENT); +} + +/**************************************************************************//** + * Clear wait for rx cmd flag state + *****************************************************************************/ +static inline void sleep_signal_wait_clr(void) +{ + sleep_semaphore &= ~(SLEEP_WAITING_FIRST_RX); +} +#endif // SL_CATALOG_WAKE_LOCK_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.h b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.h index ea96d88..ced5032 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp/sl_ncp.h @@ -1,114 +1,114 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_H -#define SL_NCP_H - -/***********************************************************************************************//** - * @addtogroup ncp - * @{ - **************************************************************************************************/ - -#include -#include -#include "sl_status.h" -#include "sl_ncp_config.h" -#include "sl_bt_api.h" -#include "sl_power_manager.h" - -/**************************************************************************//** - * NCP initialization function. - *****************************************************************************/ -void sl_ncp_init(void); - -/**************************************************************************//** - * NCP process action function. - *****************************************************************************/ -void sl_ncp_step(void); - -/**************************************************************************//** - * Local event processor - *****************************************************************************/ -bool sl_ncp_local_evt_process(sl_bt_msg_t *evt); - -/**************************************************************************//** - * User command (message_to_target) handler callback. - * - * Handle user defined commands received from NCP-host. - * - * @param[in] data Data received from NCP through UART. - *****************************************************************************/ -void sl_ncp_user_cmd_message_to_target_cb(void *data); - -/**************************************************************************//** - * Send user command (message_to_target) response. - * - * Send response to user defined (message_to_target) command to NCP-host. - * - * @param[out] result Result of the response to the command received. - * @param[out] len Message length. - * @param[out] data Data to send to NCP. - *****************************************************************************/ -void sl_ncp_user_cmd_message_to_target_rsp(sl_status_t result, - uint8_t len, - uint8_t *data); - -/**************************************************************************//** - * Send user event (message_to_host). - * - * Send user defined (message_to_host) event to NCP-host. - * - * @param[out] len Message length. - * @param[out] data Data to send to NCP. - *****************************************************************************/ -void sl_ncp_user_evt_message_to_host(uint8_t len, uint8_t *data); - -/**************************************************************************//** - * Check if NCP allows go to sleep - *****************************************************************************/ -bool sli_ncp_is_ok_to_sleep(void); - -/**************************************************************************//** - * Routine for power manager handler - *****************************************************************************/ -sl_power_manager_on_isr_exit_t sli_ncp_sleep_on_isr_exit(void); - -/**************************************************************************//** - * OS initialization function - if the OS is present - *****************************************************************************/ -void sl_ncp_os_task_init(void); - -/**************************************************************************//** - * Function to trigger the OS task to proceed - if the OS is present - *****************************************************************************/ -void sl_ncp_os_task_proceed(void); - -/** @} (end addtogroup ncp) */ -#endif // SL_NCP_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_H +#define SL_NCP_H + +/***********************************************************************************************//** + * @addtogroup ncp + * @{ + **************************************************************************************************/ + +#include +#include +#include "sl_status.h" +#include "sl_ncp_config.h" +#include "sl_bt_api.h" +#include "sl_power_manager.h" + +/**************************************************************************//** + * NCP initialization function. + *****************************************************************************/ +void sl_ncp_init(void); + +/**************************************************************************//** + * NCP process action function. + *****************************************************************************/ +void sl_ncp_step(void); + +/**************************************************************************//** + * Local event processor + *****************************************************************************/ +bool sl_ncp_local_evt_process(sl_bt_msg_t *evt); + +/**************************************************************************//** + * User command (message_to_target) handler callback. + * + * Handle user defined commands received from NCP-host. + * + * @param[in] data Data received from NCP through UART. + *****************************************************************************/ +void sl_ncp_user_cmd_message_to_target_cb(void *data); + +/**************************************************************************//** + * Send user command (message_to_target) response. + * + * Send response to user defined (message_to_target) command to NCP-host. + * + * @param[out] result Result of the response to the command received. + * @param[out] len Message length. + * @param[out] data Data to send to NCP. + *****************************************************************************/ +void sl_ncp_user_cmd_message_to_target_rsp(sl_status_t result, + uint8_t len, + uint8_t *data); + +/**************************************************************************//** + * Send user event (message_to_host). + * + * Send user defined (message_to_host) event to NCP-host. + * + * @param[out] len Message length. + * @param[out] data Data to send to NCP. + *****************************************************************************/ +void sl_ncp_user_evt_message_to_host(uint8_t len, uint8_t *data); + +/**************************************************************************//** + * Check if NCP allows go to sleep + *****************************************************************************/ +bool sli_ncp_is_ok_to_sleep(void); + +/**************************************************************************//** + * Routine for power manager handler + *****************************************************************************/ +sl_power_manager_on_isr_exit_t sli_ncp_sleep_on_isr_exit(void); + +/**************************************************************************//** + * OS initialization function - if the OS is present + *****************************************************************************/ +void sl_ncp_os_task_init(void); + +/**************************************************************************//** + * Function to trigger the OS task to proceed - if the OS is present + *****************************************************************************/ +void sl_ncp_os_task_proceed(void); + +/** @} (end addtogroup ncp) */ +#endif // SL_NCP_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c index d955ba2..a0c3922 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c @@ -1,220 +1,220 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "sl_status.h" -#include "sl_ncp_evt_filter.h" -#include "sl_ncp_evt_filter_config.h" -#include "sl_ncp_evt_filter_common.h" - -static evt_filter_t evt_filter_array[SL_NCP_EVT_FILTER_ARRAY_LENGTH]; -static uint8_t evt_pos = 0; - -static sl_status_t evt_filter_add_to_array(evt_filter_t event); -static bool evt_filter_search_in_array(evt_filter_t event); -static sl_status_t evt_filter_remove_from_array(evt_filter_t event); -static sl_status_t evt_filter_reset_array(void); -static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd); - -// ----------------------------------------------------------------------------- -// Public functions (API implementation) - -/**************************************************************************//** - * User command (manage_event_filter) handler. - *****************************************************************************/ -void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd) -{ - sl_status_t status = SL_STATUS_FAIL; - - //check length of commands - if (false == evt_filter_check_is_valid_user_command(cmd)) { - sl_bt_send_rsp_user_manage_event_filter(status); - return; - } - - switch (cmd->hdr.id) { - // ------------------------------- - // Add event filter - case SL_NCP_EVT_FILTER_CMD_ADD_ID: - status = evt_filter_add_to_array(cmd->evt); - break; - - // ------------------------------- - // Remove event filter - case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: - status = evt_filter_remove_from_array(cmd->evt); - break; - - // ------------------------------- - // Reset event filter - case SL_NCP_EVT_FILTER_CMD_RESET_ID: - status = evt_filter_reset_array(); - break; - - // ------------------------------- - default: - // Unknown subcommand, send response with failure. - break; - } - - sl_bt_send_rsp_user_manage_event_filter(status); -} - -/***************************************************************************//** - * Checks if the given event is filtered or not. - ******************************************************************************/ -bool sl_ncp_evt_filter_is_filtered(uint32_t header) -{ - return evt_filter_search_in_array(header); -} - -/***************************************************************************//** - * Checks the payload length and header length. - * - * @param[in] cmd: Contains the len, cmd id and event. - * @return Returns false if lengths are not valid true otherwise. - ******************************************************************************/ -static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd) -{ - bool valid = false; - - switch (cmd->hdr.id) { - case SL_NCP_EVT_FILTER_CMD_ADD_ID: - if (SL_NCP_EVT_FILTER_CMD_ADD_LEN == cmd->hdr.len) { - valid = true; - } - break; - - case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: - if (SL_NCP_EVT_FILTER_CMD_REMOVE_LEN == cmd->hdr.len) { - valid = true; - } - break; - - case SL_NCP_EVT_FILTER_CMD_RESET_ID: - if (SL_NCP_EVT_FILTER_CMD_RESET_LEN == cmd->hdr.len) { - valid = true; - } - break; - - default: - break; - } - - return valid; -} - -/***************************************************************************//** - * Clears the content of the event filter array. - * - * @return Returns ok - ******************************************************************************/ -static sl_status_t evt_filter_reset_array(void) -{ - sl_status_t status = SL_STATUS_OK; - memset(evt_filter_array, 0, sizeof(evt_filter_array)); - evt_pos = 0; - return status; -} - -/***************************************************************************//** - * Deletes the given event in the event filter array. - * - * @param[in] event - * @return Returns ok or not_found or empty - ******************************************************************************/ -static sl_status_t evt_filter_remove_from_array(evt_filter_t event) -{ - uint8_t i, j; - sl_status_t status = SL_STATUS_NOT_FOUND; - uint8_t evt_pos_tmp = evt_pos; - - if (evt_pos > 0) { - for (i = 0; i < evt_pos; i++) { - if (event == evt_filter_array[i]) { - evt_filter_array[i] = 0; - status = SL_STATUS_OK; - evt_pos -= 1; - - //move element one space ahead from the removed element - for (j = i; j < evt_pos_tmp - 1; j++) { - evt_filter_array[j] = evt_filter_array[j + 1]; - evt_filter_array[j + 1] = 0; - } - break; - } - } - } else { - status = SL_STATUS_EMPTY; - } - - return status; -} - -/***************************************************************************//** - * Stores the given event in the event filter array. - * - * @param[in] event - * @return Returns ok or full or already exists - ******************************************************************************/ -static sl_status_t evt_filter_add_to_array(evt_filter_t event) -{ - sl_status_t status = SL_STATUS_OK; - - if (evt_pos == SL_NCP_EVT_FILTER_ARRAY_LENGTH) { - status = SL_STATUS_FULL; - } else if (false == evt_filter_search_in_array(event)) { - evt_filter_array[evt_pos] = event; - evt_pos++; - } else { - status = SL_STATUS_ALREADY_EXISTS; - } - return status; -} - -/***************************************************************************//** - * Searches the given event in the event filter array. - * - * @param[in] event - * @return Returns true if finds, false otherwise. - ******************************************************************************/ -static bool evt_filter_search_in_array(evt_filter_t event) -{ - uint8_t i; - bool catch = false; - - for (i = 0; i < evt_pos; i++) { - if (event == evt_filter_array[i]) { - catch = true; - break; - } - } - return catch; -} +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_status.h" +#include "sl_ncp_evt_filter.h" +#include "sl_ncp_evt_filter_config.h" +#include "sl_ncp_evt_filter_common.h" + +static evt_filter_t evt_filter_array[SL_NCP_EVT_FILTER_ARRAY_LENGTH]; +static uint8_t evt_pos = 0; + +static sl_status_t evt_filter_add_to_array(evt_filter_t event); +static bool evt_filter_search_in_array(evt_filter_t event); +static sl_status_t evt_filter_remove_from_array(evt_filter_t event); +static sl_status_t evt_filter_reset_array(void); +static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd); + +// ----------------------------------------------------------------------------- +// Public functions (API implementation) + +/**************************************************************************//** + * User command (manage_event_filter) handler. + *****************************************************************************/ +void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd) +{ + sl_status_t status = SL_STATUS_FAIL; + + //check length of commands + if (false == evt_filter_check_is_valid_user_command(cmd)) { + sl_bt_send_rsp_user_manage_event_filter(status); + return; + } + + switch (cmd->hdr.id) { + // ------------------------------- + // Add event filter + case SL_NCP_EVT_FILTER_CMD_ADD_ID: + status = evt_filter_add_to_array(cmd->evt); + break; + + // ------------------------------- + // Remove event filter + case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: + status = evt_filter_remove_from_array(cmd->evt); + break; + + // ------------------------------- + // Reset event filter + case SL_NCP_EVT_FILTER_CMD_RESET_ID: + status = evt_filter_reset_array(); + break; + + // ------------------------------- + default: + // Unknown subcommand, send response with failure. + break; + } + + sl_bt_send_rsp_user_manage_event_filter(status); +} + +/***************************************************************************//** + * Checks if the given event is filtered or not. + ******************************************************************************/ +bool sl_ncp_evt_filter_is_filtered(uint32_t header) +{ + return evt_filter_search_in_array(header); +} + +/***************************************************************************//** + * Checks the payload length and header length. + * + * @param[in] cmd: Contains the len, cmd id and event. + * @return Returns false if lengths are not valid true otherwise. + ******************************************************************************/ +static bool evt_filter_check_is_valid_user_command(user_cmd_manage_event_filter_t *cmd) +{ + bool valid = false; + + switch (cmd->hdr.id) { + case SL_NCP_EVT_FILTER_CMD_ADD_ID: + if (SL_NCP_EVT_FILTER_CMD_ADD_LEN == cmd->hdr.len) { + valid = true; + } + break; + + case SL_NCP_EVT_FILTER_CMD_REMOVE_ID: + if (SL_NCP_EVT_FILTER_CMD_REMOVE_LEN == cmd->hdr.len) { + valid = true; + } + break; + + case SL_NCP_EVT_FILTER_CMD_RESET_ID: + if (SL_NCP_EVT_FILTER_CMD_RESET_LEN == cmd->hdr.len) { + valid = true; + } + break; + + default: + break; + } + + return valid; +} + +/***************************************************************************//** + * Clears the content of the event filter array. + * + * @return Returns ok + ******************************************************************************/ +static sl_status_t evt_filter_reset_array(void) +{ + sl_status_t status = SL_STATUS_OK; + memset(evt_filter_array, 0, sizeof(evt_filter_array)); + evt_pos = 0; + return status; +} + +/***************************************************************************//** + * Deletes the given event in the event filter array. + * + * @param[in] event + * @return Returns ok or not_found or empty + ******************************************************************************/ +static sl_status_t evt_filter_remove_from_array(evt_filter_t event) +{ + uint8_t i, j; + sl_status_t status = SL_STATUS_NOT_FOUND; + uint8_t evt_pos_tmp = evt_pos; + + if (evt_pos > 0) { + for (i = 0; i < evt_pos; i++) { + if (event == evt_filter_array[i]) { + evt_filter_array[i] = 0; + status = SL_STATUS_OK; + evt_pos -= 1; + + //move element one space ahead from the removed element + for (j = i; j < evt_pos_tmp - 1; j++) { + evt_filter_array[j] = evt_filter_array[j + 1]; + evt_filter_array[j + 1] = 0; + } + break; + } + } + } else { + status = SL_STATUS_EMPTY; + } + + return status; +} + +/***************************************************************************//** + * Stores the given event in the event filter array. + * + * @param[in] event + * @return Returns ok or full or already exists + ******************************************************************************/ +static sl_status_t evt_filter_add_to_array(evt_filter_t event) +{ + sl_status_t status = SL_STATUS_OK; + + if (evt_pos == SL_NCP_EVT_FILTER_ARRAY_LENGTH) { + status = SL_STATUS_FULL; + } else if (false == evt_filter_search_in_array(event)) { + evt_filter_array[evt_pos] = event; + evt_pos++; + } else { + status = SL_STATUS_ALREADY_EXISTS; + } + return status; +} + +/***************************************************************************//** + * Searches the given event in the event filter array. + * + * @param[in] event + * @return Returns true if finds, false otherwise. + ******************************************************************************/ +static bool evt_filter_search_in_array(evt_filter_t event) +{ + uint8_t i; + bool catch = false; + + for (i = 0; i < evt_pos; i++) { + if (event == evt_filter_array[i]) { + catch = true; + break; + } + } + return catch; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.h b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.h index c5fa99c..66226bb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.h @@ -1,74 +1,74 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_H -#define SL_NCP_EVT_FILTER_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -#include -#include -#include "sl_bt_api.h" - -typedef uint32_t evt_filter_t; - -PACKSTRUCT(struct user_cmd_manage_event_filter { - struct { - uint8_t len; - uint8_t id; - } hdr; - evt_filter_t evt; -}); - -typedef struct user_cmd_manage_event_filter user_cmd_manage_event_filter_t; - -/**************************************************************************//** - * User command (manage_event_filter) handler. - * This function processes the event filter command which is in the cmd - * parameter and according to it adds/removes/resets the events in the - * event filter array. - * - * @param[in] cmd payload of manage event filter - *****************************************************************************/ -void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd); - -/***************************************************************************//** - * Checks if the given event is filtered or not. - * - * @param[in] header incoming Bluetooth stack event header - * @return Returns true if filtered, false otherwise. - ******************************************************************************/ -bool sl_ncp_evt_filter_is_filtered(uint32_t header); - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_H +#define SL_NCP_EVT_FILTER_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +#include +#include +#include "sl_bt_api.h" + +typedef uint32_t evt_filter_t; + +PACKSTRUCT(struct user_cmd_manage_event_filter { + struct { + uint8_t len; + uint8_t id; + } hdr; + evt_filter_t evt; +}); + +typedef struct user_cmd_manage_event_filter user_cmd_manage_event_filter_t; + +/**************************************************************************//** + * User command (manage_event_filter) handler. + * This function processes the event filter command which is in the cmd + * parameter and according to it adds/removes/resets the events in the + * event filter array. + * + * @param[in] cmd payload of manage event filter + *****************************************************************************/ +void sl_ncp_evt_filter_handler(user_cmd_manage_event_filter_t *cmd); + +/***************************************************************************//** + * Checks if the given event is filtered or not. + * + * @param[in] header incoming Bluetooth stack event header + * @return Returns true if filtered, false otherwise. + ******************************************************************************/ +bool sl_ncp_evt_filter_is_filtered(uint32_t header); + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter_common.h b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter_common.h index 4bb98f5..6376de6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter_common.h @@ -1,50 +1,50 @@ -/***************************************************************************//** - * @file - * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_NCP_EVT_FILTER_COMMON_H -#define SL_NCP_EVT_FILTER_COMMON_H - -/***********************************************************************************************//** - * @addtogroup ncp_evt_filter - * @{ - **************************************************************************************************/ - -// Manage event filter user command -#define SL_NCP_EVT_FILTER_CMD_ADD_ID 0 -#define SL_NCP_EVT_FILTER_CMD_REMOVE_ID 1 -#define SL_NCP_EVT_FILTER_CMD_RESET_ID 2 - -// Manage event filter command payload length -#define SL_NCP_EVT_FILTER_CMD_ADD_LEN 5 -#define SL_NCP_EVT_FILTER_CMD_REMOVE_LEN 5 -#define SL_NCP_EVT_FILTER_CMD_RESET_LEN 1 - -/** @} (end addtogroup ncp_evt_filter) */ -#endif // SL_NCP_EVT_FILTER_COMMON_H +/***************************************************************************//** + * @file + * @brief Bluetooth Network Co-Processor (NCP) Event Filter Interface + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_NCP_EVT_FILTER_COMMON_H +#define SL_NCP_EVT_FILTER_COMMON_H + +/***********************************************************************************************//** + * @addtogroup ncp_evt_filter + * @{ + **************************************************************************************************/ + +// Manage event filter user command +#define SL_NCP_EVT_FILTER_CMD_ADD_ID 0 +#define SL_NCP_EVT_FILTER_CMD_REMOVE_ID 1 +#define SL_NCP_EVT_FILTER_CMD_RESET_ID 2 + +// Manage event filter command payload length +#define SL_NCP_EVT_FILTER_CMD_ADD_LEN 5 +#define SL_NCP_EVT_FILTER_CMD_REMOVE_LEN 5 +#define SL_NCP_EVT_FILTER_CMD_RESET_LEN 1 + +/** @} (end addtogroup ncp_evt_filter) */ +#endif // SL_NCP_EVT_FILTER_COMMON_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h index 666d39a..9010f65 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com.h @@ -1,83 +1,83 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_H -#define SL_SIMPLE_COM_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -#include -#include "sl_status.h" - -/**************************************************************************//** - * Simple Comm Init. - *****************************************************************************/ -void sl_simple_com_init(void); - -/**************************************************************************//** - * Step function (used in CPC mode) - *****************************************************************************/ -void sl_simple_com_step(void); - -/**************************************************************************//** - * Transmit function - *****************************************************************************/ -void sl_simple_com_transmit(uint32_t len, const uint8_t *data); - -/**************************************************************************//** - * Transmit completed callback - *****************************************************************************/ -void sl_simple_com_transmit_cb(sl_status_t status); - -/**************************************************************************//** - * Receive function (used in UART mode) - *****************************************************************************/ -void sl_simple_com_receive(void); - -/**************************************************************************//** - * Receive completed callback - *****************************************************************************/ -void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data); - -/**************************************************************************//** - * OS initialization function - if the OS is present - *****************************************************************************/ -void sl_simple_com_os_task_init(void); - -/**************************************************************************//** - * Function to trigger the OS task to proceed - if the OS is present - *****************************************************************************/ -void sl_simple_com_os_task_proceed(void); - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_H +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_H +#define SL_SIMPLE_COM_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +#include +#include "sl_status.h" + +/**************************************************************************//** + * Simple Comm Init. + *****************************************************************************/ +void sl_simple_com_init(void); + +/**************************************************************************//** + * Step function (used in CPC mode) + *****************************************************************************/ +void sl_simple_com_step(void); + +/**************************************************************************//** + * Transmit function + *****************************************************************************/ +void sl_simple_com_transmit(uint32_t len, const uint8_t *data); + +/**************************************************************************//** + * Transmit completed callback + *****************************************************************************/ +void sl_simple_com_transmit_cb(sl_status_t status); + +/**************************************************************************//** + * Receive function (used in UART mode) + *****************************************************************************/ +void sl_simple_com_receive(void); + +/**************************************************************************//** + * Receive completed callback + *****************************************************************************/ +void sl_simple_com_receive_cb(sl_status_t status, uint32_t len, uint8_t *data); + +/**************************************************************************//** + * OS initialization function - if the OS is present + *****************************************************************************/ +void sl_simple_com_os_task_init(void); + +/**************************************************************************//** + * Function to trigger the OS task to proceed - if the OS is present + *****************************************************************************/ +void sl_simple_com_os_task_proceed(void); + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c index ae93a2d..9fd7180 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.c @@ -1,211 +1,211 @@ -/***************************************************************************//** - * @file - * @brief Robust Communication - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -// ----------------------------------------------------------------------------- -// Includes -#include -#include -#include "sl_simple_com_robust.h" -#ifndef HOST_TOOLCHAIN -#include "sl_simple_com_config.h" -#else // HOST_TOOLCHAIN -#include "host_comm_config.h" -#endif // HOST_TOOLCHAIN - -#define PREAMBLE_BYTE 0b01011010 // 0x5A -#define MAX_PAYLOAD_LENGTH 2047 -#define PAYLOAD_LENGTH_MASK 0b11100000 -#define CRC_PRESENT_FLAG 0b00010000 - -// ----------------------------------------------------------------------------- -// Private function declarations - -/**************************************************************************//** - * Calculate CRC-4 checksum using the x^4 + x + 1 polynomial - * - * @param[in] data pointer to the input data - * @param[in] len length of the input data in nibbles - * @return CRC-4 checksum - *****************************************************************************/ -static uint8_t crc4(const uint8_t *data, size_t len); - -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -/**************************************************************************//** - * Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial - * - * @param[in] data pointer to the input data - * @param[in] len size of the input data in bytes - * @return CRC-8 checksum - *****************************************************************************/ -static uint8_t crc8(const uint8_t *data, size_t len); -#endif - -// ----------------------------------------------------------------------------- -// Private function definitions - -// Calculate CRC-4 checksum using the x^4 + x + 1 polynomial -uint8_t crc4(const uint8_t *data, size_t len) -{ - static const uint8_t table[] = { - 0x0, 0x7, 0xe, 0x9, 0x5, 0x2, 0xb, 0xc, 0xa, 0xd, 0x4, 0x3, 0xf, 0x8, 0x1, 0x6 - }; - - uint8_t crc = 0xa; // CRC value of the preamble 0x5A - for (size_t i = 0; i < len; i++) { - uint8_t shift = i % 2 == 0 ? 4 : 0; // high nibbles have even index - uint8_t nibble = (data[i / 2] >> shift) & 0x0F; - crc = table[crc ^ nibble]; - } - return crc; -} - -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -// Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial -static uint8_t crc8(const uint8_t *data, size_t len) -{ - uint32_t crc = 0; // initial value - for (size_t i = 0; i < len; i++) { - crc ^= data[i] << 8; - for (size_t j = 8; j > 0; j--) { - if (crc & 0x8000) { - crc ^= (0x1070 << 3); - } - crc <<= 1; - } - } - return (uint8_t)(crc >> 8); -} -#endif - -// ----------------------------------------------------------------------------- -// Public function definitions - -// Pack data between preamble byte and (if turned on) CRC checksum -size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, - const uint8_t *data, - uint16_t len) -{ - if (packed_data_ptr == NULL || data == NULL || len > MAX_PAYLOAD_LENGTH) { - return 0; - } - size_t packed_data_size = sl_simple_com_robust_get_pack_buffer_size(len); - - // Building the 3 header bytes: preamble (1 byte), - // Payload length (11 bits), CRC present flag (1 bit), header CRC-4 (4 bits) - packed_data_ptr[0] = PREAMBLE_BYTE; - // 2nd byte of the header contains the lower 8 bits of payload length - packed_data_ptr[1] = (uint8_t)len; - // Upper 3 bits of the 3rd byte of the header contains the higher 3 bits of payload length - packed_data_ptr[2] = (uint8_t)((len >> 3) & PAYLOAD_LENGTH_MASK); -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - packed_data_ptr[2] |= CRC_PRESENT_FLAG; -#endif - // Calculate CRC value for header, exclude preamble - packed_data_ptr[2] |= crc4(packed_data_ptr + 1, 3); - - // Payload - memcpy(&packed_data_ptr[SL_SIMPLE_COM_ROBUST_HEADER_SIZE], data, len); - - // CRC-8 -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - packed_data_ptr[packed_data_size - 1] = crc8(data, len); -#endif - return packed_data_size; -} - -// Unpack packets from byte stream looking for valid headers -sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, - size_t len) -{ - sl_simple_com_robust_result_t result = { - .status = SL_STATUS_FAIL, - .payload = NULL, - .payload_size = 0, - .processed = 0 - }; - - if (data == NULL) { - result.status = SL_STATUS_NULL_POINTER; - return result; - } - if (len <= SL_SIMPLE_COM_ROBUST_HEADER_SIZE) { - result.status = SL_STATUS_EMPTY; - return result; - } - - // Find and validate the message header - size_t margin = len - SL_SIMPLE_COM_ROBUST_HEADER_SIZE; - while ((data[result.processed] != PREAMBLE_BYTE - || crc4(data + result.processed + 1, 4) != 0) - && result.processed < margin) { - result.processed++; - } - // No valid frame found - if (result.processed >= margin) { - result.status = SL_STATUS_NOT_FOUND; - return result; - } - - // Shift input data to the beginning of the frame - data += result.processed; - len -= result.processed; - - // Check payload CRC flag - bool crc_present = (data[2] & CRC_PRESENT_FLAG) != 0; - - // Get payload length from header (11 bits) - result.payload_size = data[1] | ((data[2] & PAYLOAD_LENGTH_MASK) << 3); - - // Check if the incoming data contains the whole payload - size_t message_size = SL_SIMPLE_COM_ROBUST_HEADER_SIZE + result.payload_size; - if (crc_present) { - message_size++; - } - - if (len < message_size) { - result.status = SL_STATUS_FAIL; - return result; - } - - result.processed += message_size; - result.payload = data + SL_SIMPLE_COM_ROBUST_HEADER_SIZE; - - // If payload CRC is present, validate -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 - if (crc_present) { - if (crc8(result.payload, result.payload_size + 1) != 0) { - result.status = SL_STATUS_FAIL; - return result; - } - } -#endif // SL_SIMPLE_COM_ROBUST_CRC - - result.status = SL_STATUS_OK; - return result; -} +/***************************************************************************//** + * @file + * @brief Robust Communication + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +// ----------------------------------------------------------------------------- +// Includes +#include +#include +#include "sl_simple_com_robust.h" +#ifndef HOST_TOOLCHAIN +#include "sl_simple_com_config.h" +#else // HOST_TOOLCHAIN +#include "host_comm_config.h" +#endif // HOST_TOOLCHAIN + +#define PREAMBLE_BYTE 0b01011010 // 0x5A +#define MAX_PAYLOAD_LENGTH 2047 +#define PAYLOAD_LENGTH_MASK 0b11100000 +#define CRC_PRESENT_FLAG 0b00010000 + +// ----------------------------------------------------------------------------- +// Private function declarations + +/**************************************************************************//** + * Calculate CRC-4 checksum using the x^4 + x + 1 polynomial + * + * @param[in] data pointer to the input data + * @param[in] len length of the input data in nibbles + * @return CRC-4 checksum + *****************************************************************************/ +static uint8_t crc4(const uint8_t *data, size_t len); + +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +/**************************************************************************//** + * Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial + * + * @param[in] data pointer to the input data + * @param[in] len size of the input data in bytes + * @return CRC-8 checksum + *****************************************************************************/ +static uint8_t crc8(const uint8_t *data, size_t len); +#endif + +// ----------------------------------------------------------------------------- +// Private function definitions + +// Calculate CRC-4 checksum using the x^4 + x + 1 polynomial +uint8_t crc4(const uint8_t *data, size_t len) +{ + static const uint8_t table[] = { + 0x0, 0x7, 0xe, 0x9, 0x5, 0x2, 0xb, 0xc, 0xa, 0xd, 0x4, 0x3, 0xf, 0x8, 0x1, 0x6 + }; + + uint8_t crc = 0xa; // CRC value of the preamble 0x5A + for (size_t i = 0; i < len; i++) { + uint8_t shift = i % 2 == 0 ? 4 : 0; // high nibbles have even index + uint8_t nibble = (data[i / 2] >> shift) & 0x0F; + crc = table[crc ^ nibble]; + } + return crc; +} + +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +// Calculate CRC-8 checksum using the x^8 + x^2 + x + 1 polynomial +static uint8_t crc8(const uint8_t *data, size_t len) +{ + uint32_t crc = 0; // initial value + for (size_t i = 0; i < len; i++) { + crc ^= data[i] << 8; + for (size_t j = 8; j > 0; j--) { + if (crc & 0x8000) { + crc ^= (0x1070 << 3); + } + crc <<= 1; + } + } + return (uint8_t)(crc >> 8); +} +#endif + +// ----------------------------------------------------------------------------- +// Public function definitions + +// Pack data between preamble byte and (if turned on) CRC checksum +size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, + const uint8_t *data, + uint16_t len) +{ + if (packed_data_ptr == NULL || data == NULL || len > MAX_PAYLOAD_LENGTH) { + return 0; + } + size_t packed_data_size = sl_simple_com_robust_get_pack_buffer_size(len); + + // Building the 3 header bytes: preamble (1 byte), + // Payload length (11 bits), CRC present flag (1 bit), header CRC-4 (4 bits) + packed_data_ptr[0] = PREAMBLE_BYTE; + // 2nd byte of the header contains the lower 8 bits of payload length + packed_data_ptr[1] = (uint8_t)len; + // Upper 3 bits of the 3rd byte of the header contains the higher 3 bits of payload length + packed_data_ptr[2] = (uint8_t)((len >> 3) & PAYLOAD_LENGTH_MASK); +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + packed_data_ptr[2] |= CRC_PRESENT_FLAG; +#endif + // Calculate CRC value for header, exclude preamble + packed_data_ptr[2] |= crc4(packed_data_ptr + 1, 3); + + // Payload + memcpy(&packed_data_ptr[SL_SIMPLE_COM_ROBUST_HEADER_SIZE], data, len); + + // CRC-8 +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + packed_data_ptr[packed_data_size - 1] = crc8(data, len); +#endif + return packed_data_size; +} + +// Unpack packets from byte stream looking for valid headers +sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, + size_t len) +{ + sl_simple_com_robust_result_t result = { + .status = SL_STATUS_FAIL, + .payload = NULL, + .payload_size = 0, + .processed = 0 + }; + + if (data == NULL) { + result.status = SL_STATUS_NULL_POINTER; + return result; + } + if (len <= SL_SIMPLE_COM_ROBUST_HEADER_SIZE) { + result.status = SL_STATUS_EMPTY; + return result; + } + + // Find and validate the message header + size_t margin = len - SL_SIMPLE_COM_ROBUST_HEADER_SIZE; + while ((data[result.processed] != PREAMBLE_BYTE + || crc4(data + result.processed + 1, 4) != 0) + && result.processed < margin) { + result.processed++; + } + // No valid frame found + if (result.processed >= margin) { + result.status = SL_STATUS_NOT_FOUND; + return result; + } + + // Shift input data to the beginning of the frame + data += result.processed; + len -= result.processed; + + // Check payload CRC flag + bool crc_present = (data[2] & CRC_PRESENT_FLAG) != 0; + + // Get payload length from header (11 bits) + result.payload_size = data[1] | ((data[2] & PAYLOAD_LENGTH_MASK) << 3); + + // Check if the incoming data contains the whole payload + size_t message_size = SL_SIMPLE_COM_ROBUST_HEADER_SIZE + result.payload_size; + if (crc_present) { + message_size++; + } + + if (len < message_size) { + result.status = SL_STATUS_FAIL; + return result; + } + + result.processed += message_size; + result.payload = data + SL_SIMPLE_COM_ROBUST_HEADER_SIZE; + + // If payload CRC is present, validate +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 + if (crc_present) { + if (crc8(result.payload, result.payload_size + 1) != 0) { + result.status = SL_STATUS_FAIL; + return result; + } + } +#endif // SL_SIMPLE_COM_ROBUST_CRC + + result.status = SL_STATUS_OK; + return result; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h index c3e74f7..d41ea47 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_robust.h @@ -1,96 +1,96 @@ -/***************************************************************************//** - * @file - * @brief Robust Communication Interface - * Packeting layer providing reliable communication with guaranteeing data - * integrity. This module can be used to pack bytes between a header and a CRC - * value and unpack and validate packets from a data stream. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SIMPLE_COM_ROBUST_H -#define SL_SIMPLE_COM_ROBUST_H - -/***********************************************************************************************//** - * @addtogroup simple_com - * @{ - **************************************************************************************************/ - -#include -#include -#include "sl_status.h" -#ifndef HOST_TOOLCHAIN -#include "sl_simple_com_config.h" -#else // HOST_TOOLCHAIN -#include "host_comm_config.h" -#endif // HOST_TOOLCHAIN - -#define SL_SIMPLE_COM_ROBUST_HEADER_SIZE 3 - -// Get required buffer size for packed data -#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 -#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE + 1) -#else // SL_SIMPLE_COM_ROBUST_CRC -#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE) -#endif // SL_SIMPLE_COM_ROBUST_CRC - -typedef struct { - sl_status_t status; // SL_STATUS_OK if a packet was found and validated with success - uint8_t *payload; // Pointer to the beginning of the payload - size_t payload_size; // Payload length in bytes - size_t processed; // Number of bytes processed from the input buffer -} sl_simple_com_robust_result_t; - -/**************************************************************************//** - * Pack data between preamble byte and (if turned on) CRC checksum - * This function adds a 3 byte header containing preamble byte, payload - * length, CRC flag and CRC value to the header. If CRC is required an 8 bit - * CRC value will be calculated for the payload and added to the end of packet. - * - * @param[out] packed_data_ptr pointer where the packed data should be loaded - * @param[in] data pointer to the data to be packed - * @param[in] len size of the data to be packed - * @return the size of packed data - *****************************************************************************/ -size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, - const uint8_t *data, - uint16_t len); - -/**************************************************************************//** - * Unpack packets from byte stream looking for valid headers. - * This function searches valid headers and extracts payload after the header - * into destination buffer. Header is validated by 4 bit header CRC and payload - * can be also validated by optional CRC check. - * - * @param[in] data pointer to the data to be unpacked - * @param[in] len size of the data to be unpacked - * @return the result of the action - *****************************************************************************/ -sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, - size_t len); - -/** @} (end addtogroup simple_com) */ -#endif // SL_SIMPLE_COM_ROBUST_H +/***************************************************************************//** + * @file + * @brief Robust Communication Interface + * Packeting layer providing reliable communication with guaranteeing data + * integrity. This module can be used to pack bytes between a header and a CRC + * value and unpack and validate packets from a data stream. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SIMPLE_COM_ROBUST_H +#define SL_SIMPLE_COM_ROBUST_H + +/***********************************************************************************************//** + * @addtogroup simple_com + * @{ + **************************************************************************************************/ + +#include +#include +#include "sl_status.h" +#ifndef HOST_TOOLCHAIN +#include "sl_simple_com_config.h" +#else // HOST_TOOLCHAIN +#include "host_comm_config.h" +#endif // HOST_TOOLCHAIN + +#define SL_SIMPLE_COM_ROBUST_HEADER_SIZE 3 + +// Get required buffer size for packed data +#if defined(SL_SIMPLE_COM_ROBUST_CRC) && SL_SIMPLE_COM_ROBUST_CRC == 1 +#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE + 1) +#else // SL_SIMPLE_COM_ROBUST_CRC +#define sl_simple_com_robust_get_pack_buffer_size(len) (len + SL_SIMPLE_COM_ROBUST_HEADER_SIZE) +#endif // SL_SIMPLE_COM_ROBUST_CRC + +typedef struct { + sl_status_t status; // SL_STATUS_OK if a packet was found and validated with success + uint8_t *payload; // Pointer to the beginning of the payload + size_t payload_size; // Payload length in bytes + size_t processed; // Number of bytes processed from the input buffer +} sl_simple_com_robust_result_t; + +/**************************************************************************//** + * Pack data between preamble byte and (if turned on) CRC checksum + * This function adds a 3 byte header containing preamble byte, payload + * length, CRC flag and CRC value to the header. If CRC is required an 8 bit + * CRC value will be calculated for the payload and added to the end of packet. + * + * @param[out] packed_data_ptr pointer where the packed data should be loaded + * @param[in] data pointer to the data to be packed + * @param[in] len size of the data to be packed + * @return the size of packed data + *****************************************************************************/ +size_t sl_simple_com_robust_pack_data(uint8_t *packed_data_ptr, + const uint8_t *data, + uint16_t len); + +/**************************************************************************//** + * Unpack packets from byte stream looking for valid headers. + * This function searches valid headers and extracts payload after the header + * into destination buffer. Header is validated by 4 bit header CRC and payload + * can be also validated by optional CRC check. + * + * @param[in] data pointer to the data to be unpacked + * @param[in] len size of the data to be unpacked + * @return the result of the action + *****************************************************************************/ +sl_simple_com_robust_result_t sl_simple_com_robust_unpack_data(uint8_t *data, + size_t len); + +/** @} (end addtogroup simple_com) */ +#endif // SL_SIMPLE_COM_ROBUST_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c index 5a0588f..46d3c85 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c +++ b/locator_ncp/gecko_sdk_4.4.1/app/bluetooth/common/simple_com/sl_simple_com_usart.c @@ -1,584 +1,584 @@ -/***************************************************************************//** - * @file - * @brief Simple Communication Interface (UART) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include -#include "sl_status.h" -#include "em_common.h" -#include "em_core.h" -#include "sl_uartdrv_instances.h" -#include "app_assert.h" -#include "sl_simple_com.h" -#include "sl_simple_com_config.h" -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 -#include "sl_simple_com_robust.h" -#endif // SL_SIMPLE_COM_ROBUST -#ifdef EFR32BG1_USART_E202_WORKAROUND -#include "sl_sleeptimer.h" -#endif // EFR32BG1_USART_E202_WORKAROUND - -// Store UARTDRV handle to use with Simple COM -static UARTDRV_Handle_t uartdrv_handle = NULL; -static IRQn_Type irq_number; - -// store the maximum waiting time for a callback -static uint32_t time_to_wait_tx_callback = 0; - -// store the returned values of TX callback -typedef struct { - UARTDRV_Handle_t handle; - uint32_t timeout; - sl_status_t status; - bool finished; -} tx_cb_sig; - -static tx_cb_sig tx_cb_signal = { 0 }; - -// UART receive and transmit buffers -static uint8_t rx_buf[SL_SIMPLE_COM_RX_BUF_SIZE] = { 0 }; -static uint8_t tx_buf[SL_SIMPLE_COM_TX_BUF_SIZE] = { 0 }; - -#ifdef EFR32BG1_USART_E202_WORKAROUND -// Internal timer and counter for receive -// EFR32BG1 - USART_E202 workaround -static sl_sleeptimer_timer_handle_t receive_timer; -static uint32_t received_count = 0; -#endif // EFR32BG1_USART_E202_WORKAROUND - -// Internal UART receive and transmit callback -static void transmit_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); -static void receive_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); -// Helper functions to ensure reception -static Ecode_t cancel_receive(UARTDRV_Handle_t handle); -static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer); -static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer); - -static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle); - -static Ecode_t uart_receive_start(UARTDRV_Handle_t handle); - -void sli_simple_com_isr(void); - -// ----------------------------------------------------------------------------- -// Public functions (API implementation) - -/**************************************************************************//** - * Simple COM initialization function - *****************************************************************************/ -void sl_simple_com_init(void) -{ - // clear RX and TX buffers - memset(rx_buf, 0, sizeof(rx_buf)); - memset(tx_buf, 0, sizeof(tx_buf)); - - // Get the default UARTDRV handle to use for Simple COM - uartdrv_handle = sl_uartdrv_get_default(); - irq_number = irq_number_from_handle(uartdrv_handle); - app_assert(irq_number >= (IRQn_Type)(0), "Unknown UARTDRV handle\n"); - - // calculate the maximum amount of time to wait for UART TX buffer to empty - time_to_wait_tx_callback = CMU_ClockFreqGet(cmuClock_CORE) - / USART_BaudrateGet(uartdrv_handle->peripheral.uart) - * 4; -} - -/**************************************************************************//** - * Simple COM step function - *****************************************************************************/ -void sl_simple_com_step(void) -{ - if (tx_cb_signal.finished) { - // Wait until UART finished transfer - if ((!(UARTDRV_GetPeripheralStatus(tx_cb_signal.handle) & UARTDRV_STATUS_TXC)) - && (tx_cb_signal.timeout < time_to_wait_tx_callback)) { - tx_cb_signal.timeout++; - sl_simple_com_os_task_proceed(); - } else { - // Clear TX buffer - tx_cb_signal.timeout = 0; - tx_cb_signal.finished = false; - // Call public callback API - sl_simple_com_transmit_cb(ECODE_EMDRV_UARTDRV_OK == tx_cb_signal.status - ? SL_STATUS_OK : SL_STATUS_FAIL); - } - } -} - -/**************************************************************************//** - * UART transmit function - * - * Transmits len bytes of data through the UART interface using DMA. - * - * @param[out] len Message length - * @param[out] data Message data - *****************************************************************************/ -void sl_simple_com_transmit(uint32_t len, const uint8_t *data) -{ - Ecode_t ec; - // Make a copy of the data to be sent to guarantee its integrity until - // transmission completes -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 - app_assert(sl_simple_com_robust_get_pack_buffer_size(len) <= SL_SIMPLE_COM_TX_BUF_SIZE, - "TX length is bigger than allocated buffer\n"); - len = sl_simple_com_robust_pack_data(tx_buf, data, (size_t)len); -#else // SL_SIMPLE_COM_ROBUST - app_assert(len <= SL_SIMPLE_COM_TX_BUF_SIZE, - "TX length is bigger than allocated buffer\n"); - memcpy((void *)tx_buf, (void *)data, (size_t)len); -#endif // SL_SIMPLE_COM_ROBUST - - // Transmit data using a non-blocking transmit function - ec = UARTDRV_Transmit(uartdrv_handle, - tx_buf, - len, - transmit_cb); - app_assert(ECODE_EMDRV_UARTDRV_OK == ec, - "[E: 0x%04x] Failed to start transmitting\n", - (int)ec); - (void)ec; - sl_simple_com_os_task_proceed(); -} - -/**************************************************************************//** - * UART receive function - * - * Starts reception on UART interface using DMA. - * - * @note The problem with standard UART reception is that it needs the exact - * amount of bytes to read. This implementation starts a timer to measure idle - * time on the bus and based on that puts the received message into the buffer. - *****************************************************************************/ -void sl_simple_com_receive(void) -{ - Ecode_t ec; - // Clear pending RX interrupt flag in NVIC - NVIC_ClearPendingIRQ(irq_number); - NVIC_EnableIRQ(irq_number); - // Setup RX timeout to 255 bit-time - uartdrv_handle->peripheral.uart->TIMECMP1 = \ - (USART_TIMECMP1_TSTOP_RXACT - | USART_TIMECMP1_TSTART_RXEOF - | (0xff << _USART_TIMECMP1_TCMPVAL_SHIFT)); - // Clear any USART interrupt flags - USART_IntClear(uartdrv_handle->peripheral.uart, _USART_IF_MASK); - USART_IntEnable(uartdrv_handle->peripheral.uart, USART_IF_TXIDLE | USART_IF_TCMP1); - ec = uart_receive_start(uartdrv_handle); - app_assert(ECODE_EMDRV_UARTDRV_OK == ec, - "[E: 0x%04x] Failed to start receiving\n", - (int)ec); - (void)ec; -} - -/**************************************************************************//** - * UART transmit completed callback - * - * Called after UART transmit is finished. - * - * @param[in] status Status of the transmission - * - * @note Weak implementation - * Called after DMA is complete, the UART transmission might be still ongoing - *****************************************************************************/ -SL_WEAK void sl_simple_com_transmit_cb(sl_status_t status) -{ - (void)status; -} - -/**************************************************************************//** - * UART receive completed callback - * - * Called after UART receive is finished. - * - * @param[in] status Status of the reception - * @param[in] len Received message length - * @param[in] data Data received - * - * @note Weak implementation - *****************************************************************************/ -SL_WEAK void sl_simple_com_receive_cb(sl_status_t status, - uint32_t len, - uint8_t *data) -{ - (void)status; - (void)data; - (void)len; -} - -// ----------------------------------------------------------------------------- -// Private functions - -#ifdef EFR32BG1_USART_E202_WORKAROUND -// EFR32BG1 - USART_E202 workaround -static void timer_callback(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - (void)handle; - (void)data; - - // Assert nRTS - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); - } - - // Get received bytes - uint8_t* buffer = NULL; - uint32_t received = 0; - uint32_t remaining = 0; - UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); - - // if no change in that time callback is needed - if (received_count == received) { - sl_sleeptimer_stop_timer(&receive_timer); - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - - // cancel previous block receive operation - (void)cancel_receive(uartdrv_handle); - uart_receive_start(uartdrv_handle); - CORE_EXIT_ATOMIC(); - received_count = 0; - } else { - // otherwise register received bytes for the next run - received_count = received; - } -} - -#endif // EFR32BG1_USART_E202_WORKAROUND - -/****************************************************************************** - * UART interrupt handler - * - * Called when the set timer for tx idle states finished. - * - * @note automatically restarts the timer and starts a new reception. - * @note TODO: this should be provided by UARTDRV - *****************************************************************************/ -void sli_simple_com_isr(void) -{ - // RX timeout, stop transfer and handle what we got in buffer - if (uartdrv_handle->peripheral.uart->IF & USART_IF_TCMP1) { - CORE_DECLARE_IRQ_STATE; - - // Assert nRTS - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); - } - - CORE_ENTER_ATOMIC(); - // stop the timer - uartdrv_handle->peripheral.uart->TIMECMP1 &= \ - ~_USART_TIMECMP1_TSTART_MASK; - uartdrv_handle->peripheral.uart->TIMECMP1 |= \ - USART_TIMECMP1_TSTART_RXEOF; - // clear timer interrupt - USART_IntClear(uartdrv_handle->peripheral.uart, - USART_IF_TCMP1); -#ifdef EFR32BG1_USART_E202_WORKAROUND - // EFR32BG1 - USART_E202 workaround - sl_sleeptimer_stop_timer(&receive_timer); - sl_sleeptimer_start_periodic_timer( - &receive_timer, - sl_sleeptimer_ms_to_tick(1), - timer_callback, - NULL, - 0, - 0); - uint8_t* buffer = NULL; - uint32_t received = 0; - uint32_t remaining = 0; - UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); - received_count = received; -#else - // cancel previous block receive operation - (void)cancel_receive(uartdrv_handle); - uart_receive_start(uartdrv_handle); -#endif // EFR32BG1_USART_E202_WORKAROUND - CORE_EXIT_ATOMIC(); - } -} - -/****************************************************************************** - * Internal UART transmit completed callback - * - * Called after UART transmit is finished. - * - * @param[in] handle UART driver handle - * @param[in] transferStatus Status of the transfer - * @param[in] data Transmitted data - * @param[in] transferCount Number of sent bytes - * - * @note Calls public sl_simple_com_transmit_cb - * Called after DMA is complete, the UART transmission might be still ongoing - *****************************************************************************/ -static void transmit_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount) -{ - (void)data; - (void)transferCount; - - CORE_ATOMIC_SECTION( - tx_cb_signal.status = transferStatus; - tx_cb_signal.handle = handle; - tx_cb_signal.timeout = 0; - tx_cb_signal.finished = true; - ) - sl_simple_com_os_task_proceed(); -} - -/****************************************************************************** - * Internal UART receive completed callback - * - * Called after UART receive is finished. - * - * @param[in] handle UART driver handle - * @param[in] transferStatus Status of the transfer - * @param[in] data Received data - * @param[in] transferCount Number of received bytes - * - * @note Calls public sl_simple_com_receive_cb - *****************************************************************************/ -static void receive_cb(UARTDRV_Handle_t handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount) -{ - (void)handle; - -#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 - if (transferCount > 0) { - sl_simple_com_robust_result_t result = sl_simple_com_robust_unpack_data(data, - transferCount); - - // Call public callback API - sl_simple_com_receive_cb((ECODE_EMDRV_UARTDRV_OK == transferStatus - ? SL_STATUS_OK : SL_STATUS_FAIL | result.status), - result.payload_size, - result.payload); - } else { -#else // SL_SIMPLE_COM_ROBUST - { -#endif // SL_SIMPLE_COM_ROBUST - // Call public callback API - sl_simple_com_receive_cb(ECODE_EMDRV_UARTDRV_OK == transferStatus - ? SL_STATUS_OK : SL_STATUS_FAIL, - transferCount, - data); - } - - sl_simple_com_os_task_proceed(); -} - -/****************************************************************************** - * Cancel previous block receive operation. - * - * @param[in] handle UART driver handle - *****************************************************************************/ -static Ecode_t cancel_receive(UARTDRV_Handle_t handle) -{ - UARTDRV_Buffer_t *rxBuffer; - Ecode_t status; - CORE_DECLARE_IRQ_STATE; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - CORE_ENTER_ATOMIC(); - if (handle->rxQueue->used == 0) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } - - // ------------------------------- - // Stop the current DMA transfer - (void)DMADRV_StopTransfer(handle->rxDmaCh); - handle->rxDmaActive = false; - // Update the transfer status of the active transfer - status = get_tail_buffer(handle->rxQueue, &rxBuffer); - // If aborting was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - EFM_ASSERT(rxBuffer != NULL); - (void)DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int *)&rxBuffer->itemsRemaining); - rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // ------------------------------- - // Dequeue all transfers and call callback - while (handle->rxQueue->used > 0) { - (void)dequeue_buffer(handle->rxQueue, &rxBuffer); - // Call the callback - if (rxBuffer->callback != NULL) { - if (rxBuffer->callback != NULL) { - rxBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_OK, - rxBuffer->data, - rxBuffer->transferCount - rxBuffer->itemsRemaining); - } - } - } - - // ------------------------------- - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Gets the buffer tail. - * - * @param[in] queue Input buffer - * @param[out] buffer Output buffer - *****************************************************************************/ -static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Dequeues buffer - * - * Moves through the buffer. - * - * @param[in] queue Input buffer - * @param[out] buffer Output buffer - *****************************************************************************/ -static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - queue->tail = (queue->tail + 1) % queue->size; - queue->used--; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/****************************************************************************** - * Get NVIC IRQ number from UARTDRV handle - * - * @param[in] handle UART driver handle - * @return Interrupt number - *****************************************************************************/ -static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle) -{ - IRQn_Type irq_number = (IRQn_Type)(-1); - - switch ((uint32_t)handle->peripheral.uart) { -#if defined(USART0_BASE) - case USART0_BASE: - irq_number = USART0_RX_IRQn; - break; -#endif -#if defined(USART1_BASE) - case USART1_BASE: - irq_number = USART1_RX_IRQn; - break; -#endif -#if defined(USART2_BASE) - case USART2_BASE: - irq_number = USART2_RX_IRQn; - break; -#endif -#if defined(USART3_BASE) - case USART3_BASE: - irq_number = USART3_RX_IRQn; - break; -#endif - default: - app_assert(false, "Unknown UARTDRV handle\n"); - break; - } - - return irq_number; -} - -/****************************************************************************** - * Start / resume UARTDRV receiving - * - * @param[in] handle UART driver handle - * @return UARTDRV reported result of the operation - *****************************************************************************/ -static Ecode_t uart_receive_start(UARTDRV_Handle_t handle) -{ - Ecode_t ec = UARTDRV_Receive(handle, rx_buf, sizeof(rx_buf), receive_cb); - - if (ec == ECODE_EMDRV_UARTDRV_OK) { - // De-assert nRTS or send XON - if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { - UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlAuto); - } - } - - return ec; -} -/****************************************************************************** - * Function to trigger the OS task to proceed - * - * @note Weak implementation. - *****************************************************************************/ -SL_WEAK void sl_simple_com_os_task_proceed(void) -{ - // No action on bare metal implementation -} +/***************************************************************************//** + * @file + * @brief Simple Communication Interface (UART) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include +#include "sl_status.h" +#include "em_common.h" +#include "em_core.h" +#include "sl_uartdrv_instances.h" +#include "app_assert.h" +#include "sl_simple_com.h" +#include "sl_simple_com_config.h" +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 +#include "sl_simple_com_robust.h" +#endif // SL_SIMPLE_COM_ROBUST +#ifdef EFR32BG1_USART_E202_WORKAROUND +#include "sl_sleeptimer.h" +#endif // EFR32BG1_USART_E202_WORKAROUND + +// Store UARTDRV handle to use with Simple COM +static UARTDRV_Handle_t uartdrv_handle = NULL; +static IRQn_Type irq_number; + +// store the maximum waiting time for a callback +static uint32_t time_to_wait_tx_callback = 0; + +// store the returned values of TX callback +typedef struct { + UARTDRV_Handle_t handle; + uint32_t timeout; + sl_status_t status; + bool finished; +} tx_cb_sig; + +static tx_cb_sig tx_cb_signal = { 0 }; + +// UART receive and transmit buffers +static uint8_t rx_buf[SL_SIMPLE_COM_RX_BUF_SIZE] = { 0 }; +static uint8_t tx_buf[SL_SIMPLE_COM_TX_BUF_SIZE] = { 0 }; + +#ifdef EFR32BG1_USART_E202_WORKAROUND +// Internal timer and counter for receive +// EFR32BG1 - USART_E202 workaround +static sl_sleeptimer_timer_handle_t receive_timer; +static uint32_t received_count = 0; +#endif // EFR32BG1_USART_E202_WORKAROUND + +// Internal UART receive and transmit callback +static void transmit_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); +static void receive_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); +// Helper functions to ensure reception +static Ecode_t cancel_receive(UARTDRV_Handle_t handle); +static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer); +static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer); + +static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle); + +static Ecode_t uart_receive_start(UARTDRV_Handle_t handle); + +void sli_simple_com_isr(void); + +// ----------------------------------------------------------------------------- +// Public functions (API implementation) + +/**************************************************************************//** + * Simple COM initialization function + *****************************************************************************/ +void sl_simple_com_init(void) +{ + // clear RX and TX buffers + memset(rx_buf, 0, sizeof(rx_buf)); + memset(tx_buf, 0, sizeof(tx_buf)); + + // Get the default UARTDRV handle to use for Simple COM + uartdrv_handle = sl_uartdrv_get_default(); + irq_number = irq_number_from_handle(uartdrv_handle); + app_assert(irq_number >= (IRQn_Type)(0), "Unknown UARTDRV handle\n"); + + // calculate the maximum amount of time to wait for UART TX buffer to empty + time_to_wait_tx_callback = CMU_ClockFreqGet(cmuClock_CORE) + / USART_BaudrateGet(uartdrv_handle->peripheral.uart) + * 4; +} + +/**************************************************************************//** + * Simple COM step function + *****************************************************************************/ +void sl_simple_com_step(void) +{ + if (tx_cb_signal.finished) { + // Wait until UART finished transfer + if ((!(UARTDRV_GetPeripheralStatus(tx_cb_signal.handle) & UARTDRV_STATUS_TXC)) + && (tx_cb_signal.timeout < time_to_wait_tx_callback)) { + tx_cb_signal.timeout++; + sl_simple_com_os_task_proceed(); + } else { + // Clear TX buffer + tx_cb_signal.timeout = 0; + tx_cb_signal.finished = false; + // Call public callback API + sl_simple_com_transmit_cb(ECODE_EMDRV_UARTDRV_OK == tx_cb_signal.status + ? SL_STATUS_OK : SL_STATUS_FAIL); + } + } +} + +/**************************************************************************//** + * UART transmit function + * + * Transmits len bytes of data through the UART interface using DMA. + * + * @param[out] len Message length + * @param[out] data Message data + *****************************************************************************/ +void sl_simple_com_transmit(uint32_t len, const uint8_t *data) +{ + Ecode_t ec; + // Make a copy of the data to be sent to guarantee its integrity until + // transmission completes +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 + app_assert(sl_simple_com_robust_get_pack_buffer_size(len) <= SL_SIMPLE_COM_TX_BUF_SIZE, + "TX length is bigger than allocated buffer\n"); + len = sl_simple_com_robust_pack_data(tx_buf, data, (size_t)len); +#else // SL_SIMPLE_COM_ROBUST + app_assert(len <= SL_SIMPLE_COM_TX_BUF_SIZE, + "TX length is bigger than allocated buffer\n"); + memcpy((void *)tx_buf, (void *)data, (size_t)len); +#endif // SL_SIMPLE_COM_ROBUST + + // Transmit data using a non-blocking transmit function + ec = UARTDRV_Transmit(uartdrv_handle, + tx_buf, + len, + transmit_cb); + app_assert(ECODE_EMDRV_UARTDRV_OK == ec, + "[E: 0x%04x] Failed to start transmitting\n", + (int)ec); + (void)ec; + sl_simple_com_os_task_proceed(); +} + +/**************************************************************************//** + * UART receive function + * + * Starts reception on UART interface using DMA. + * + * @note The problem with standard UART reception is that it needs the exact + * amount of bytes to read. This implementation starts a timer to measure idle + * time on the bus and based on that puts the received message into the buffer. + *****************************************************************************/ +void sl_simple_com_receive(void) +{ + Ecode_t ec; + // Clear pending RX interrupt flag in NVIC + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); + // Setup RX timeout to 255 bit-time + uartdrv_handle->peripheral.uart->TIMECMP1 = \ + (USART_TIMECMP1_TSTOP_RXACT + | USART_TIMECMP1_TSTART_RXEOF + | (0xff << _USART_TIMECMP1_TCMPVAL_SHIFT)); + // Clear any USART interrupt flags + USART_IntClear(uartdrv_handle->peripheral.uart, _USART_IF_MASK); + USART_IntEnable(uartdrv_handle->peripheral.uart, USART_IF_TXIDLE | USART_IF_TCMP1); + ec = uart_receive_start(uartdrv_handle); + app_assert(ECODE_EMDRV_UARTDRV_OK == ec, + "[E: 0x%04x] Failed to start receiving\n", + (int)ec); + (void)ec; +} + +/**************************************************************************//** + * UART transmit completed callback + * + * Called after UART transmit is finished. + * + * @param[in] status Status of the transmission + * + * @note Weak implementation + * Called after DMA is complete, the UART transmission might be still ongoing + *****************************************************************************/ +SL_WEAK void sl_simple_com_transmit_cb(sl_status_t status) +{ + (void)status; +} + +/**************************************************************************//** + * UART receive completed callback + * + * Called after UART receive is finished. + * + * @param[in] status Status of the reception + * @param[in] len Received message length + * @param[in] data Data received + * + * @note Weak implementation + *****************************************************************************/ +SL_WEAK void sl_simple_com_receive_cb(sl_status_t status, + uint32_t len, + uint8_t *data) +{ + (void)status; + (void)data; + (void)len; +} + +// ----------------------------------------------------------------------------- +// Private functions + +#ifdef EFR32BG1_USART_E202_WORKAROUND +// EFR32BG1 - USART_E202 workaround +static void timer_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + (void)handle; + (void)data; + + // Assert nRTS + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); + } + + // Get received bytes + uint8_t* buffer = NULL; + uint32_t received = 0; + uint32_t remaining = 0; + UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); + + // if no change in that time callback is needed + if (received_count == received) { + sl_sleeptimer_stop_timer(&receive_timer); + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // cancel previous block receive operation + (void)cancel_receive(uartdrv_handle); + uart_receive_start(uartdrv_handle); + CORE_EXIT_ATOMIC(); + received_count = 0; + } else { + // otherwise register received bytes for the next run + received_count = received; + } +} + +#endif // EFR32BG1_USART_E202_WORKAROUND + +/****************************************************************************** + * UART interrupt handler + * + * Called when the set timer for tx idle states finished. + * + * @note automatically restarts the timer and starts a new reception. + * @note TODO: this should be provided by UARTDRV + *****************************************************************************/ +void sli_simple_com_isr(void) +{ + // RX timeout, stop transfer and handle what we got in buffer + if (uartdrv_handle->peripheral.uart->IF & USART_IF_TCMP1) { + CORE_DECLARE_IRQ_STATE; + + // Assert nRTS + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlOff); + } + + CORE_ENTER_ATOMIC(); + // stop the timer + uartdrv_handle->peripheral.uart->TIMECMP1 &= \ + ~_USART_TIMECMP1_TSTART_MASK; + uartdrv_handle->peripheral.uart->TIMECMP1 |= \ + USART_TIMECMP1_TSTART_RXEOF; + // clear timer interrupt + USART_IntClear(uartdrv_handle->peripheral.uart, + USART_IF_TCMP1); +#ifdef EFR32BG1_USART_E202_WORKAROUND + // EFR32BG1 - USART_E202 workaround + sl_sleeptimer_stop_timer(&receive_timer); + sl_sleeptimer_start_periodic_timer( + &receive_timer, + sl_sleeptimer_ms_to_tick(1), + timer_callback, + NULL, + 0, + 0); + uint8_t* buffer = NULL; + uint32_t received = 0; + uint32_t remaining = 0; + UARTDRV_GetReceiveStatus(uartdrv_handle, &buffer, &received, &remaining); + received_count = received; +#else + // cancel previous block receive operation + (void)cancel_receive(uartdrv_handle); + uart_receive_start(uartdrv_handle); +#endif // EFR32BG1_USART_E202_WORKAROUND + CORE_EXIT_ATOMIC(); + } +} + +/****************************************************************************** + * Internal UART transmit completed callback + * + * Called after UART transmit is finished. + * + * @param[in] handle UART driver handle + * @param[in] transferStatus Status of the transfer + * @param[in] data Transmitted data + * @param[in] transferCount Number of sent bytes + * + * @note Calls public sl_simple_com_transmit_cb + * Called after DMA is complete, the UART transmission might be still ongoing + *****************************************************************************/ +static void transmit_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount) +{ + (void)data; + (void)transferCount; + + CORE_ATOMIC_SECTION( + tx_cb_signal.status = transferStatus; + tx_cb_signal.handle = handle; + tx_cb_signal.timeout = 0; + tx_cb_signal.finished = true; + ) + sl_simple_com_os_task_proceed(); +} + +/****************************************************************************** + * Internal UART receive completed callback + * + * Called after UART receive is finished. + * + * @param[in] handle UART driver handle + * @param[in] transferStatus Status of the transfer + * @param[in] data Received data + * @param[in] transferCount Number of received bytes + * + * @note Calls public sl_simple_com_receive_cb + *****************************************************************************/ +static void receive_cb(UARTDRV_Handle_t handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount) +{ + (void)handle; + +#if defined(SL_SIMPLE_COM_ROBUST) && SL_SIMPLE_COM_ROBUST == 1 + if (transferCount > 0) { + sl_simple_com_robust_result_t result = sl_simple_com_robust_unpack_data(data, + transferCount); + + // Call public callback API + sl_simple_com_receive_cb((ECODE_EMDRV_UARTDRV_OK == transferStatus + ? SL_STATUS_OK : SL_STATUS_FAIL | result.status), + result.payload_size, + result.payload); + } else { +#else // SL_SIMPLE_COM_ROBUST + { +#endif // SL_SIMPLE_COM_ROBUST + // Call public callback API + sl_simple_com_receive_cb(ECODE_EMDRV_UARTDRV_OK == transferStatus + ? SL_STATUS_OK : SL_STATUS_FAIL, + transferCount, + data); + } + + sl_simple_com_os_task_proceed(); +} + +/****************************************************************************** + * Cancel previous block receive operation. + * + * @param[in] handle UART driver handle + *****************************************************************************/ +static Ecode_t cancel_receive(UARTDRV_Handle_t handle) +{ + UARTDRV_Buffer_t *rxBuffer; + Ecode_t status; + CORE_DECLARE_IRQ_STATE; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + CORE_ENTER_ATOMIC(); + if (handle->rxQueue->used == 0) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } + + // ------------------------------- + // Stop the current DMA transfer + (void)DMADRV_StopTransfer(handle->rxDmaCh); + handle->rxDmaActive = false; + // Update the transfer status of the active transfer + status = get_tail_buffer(handle->rxQueue, &rxBuffer); + // If aborting was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + EFM_ASSERT(rxBuffer != NULL); + (void)DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int *)&rxBuffer->itemsRemaining); + rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // ------------------------------- + // Dequeue all transfers and call callback + while (handle->rxQueue->used > 0) { + (void)dequeue_buffer(handle->rxQueue, &rxBuffer); + // Call the callback + if (rxBuffer->callback != NULL) { + if (rxBuffer->callback != NULL) { + rxBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_OK, + rxBuffer->data, + rxBuffer->transferCount - rxBuffer->itemsRemaining); + } + } + } + + // ------------------------------- + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Gets the buffer tail. + * + * @param[in] queue Input buffer + * @param[out] buffer Output buffer + *****************************************************************************/ +static Ecode_t get_tail_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Dequeues buffer + * + * Moves through the buffer. + * + * @param[in] queue Input buffer + * @param[out] buffer Output buffer + *****************************************************************************/ +static Ecode_t dequeue_buffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + queue->tail = (queue->tail + 1) % queue->size; + queue->used--; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/****************************************************************************** + * Get NVIC IRQ number from UARTDRV handle + * + * @param[in] handle UART driver handle + * @return Interrupt number + *****************************************************************************/ +static IRQn_Type irq_number_from_handle(UARTDRV_Handle_t handle) +{ + IRQn_Type irq_number = (IRQn_Type)(-1); + + switch ((uint32_t)handle->peripheral.uart) { +#if defined(USART0_BASE) + case USART0_BASE: + irq_number = USART0_RX_IRQn; + break; +#endif +#if defined(USART1_BASE) + case USART1_BASE: + irq_number = USART1_RX_IRQn; + break; +#endif +#if defined(USART2_BASE) + case USART2_BASE: + irq_number = USART2_RX_IRQn; + break; +#endif +#if defined(USART3_BASE) + case USART3_BASE: + irq_number = USART3_RX_IRQn; + break; +#endif + default: + app_assert(false, "Unknown UARTDRV handle\n"); + break; + } + + return irq_number; +} + +/****************************************************************************** + * Start / resume UARTDRV receiving + * + * @param[in] handle UART driver handle + * @return UARTDRV reported result of the operation + *****************************************************************************/ +static Ecode_t uart_receive_start(UARTDRV_Handle_t handle) +{ + Ecode_t ec = UARTDRV_Receive(handle, rx_buf, sizeof(rx_buf), receive_cb); + + if (ec == ECODE_EMDRV_UARTDRV_OK) { + // De-assert nRTS or send XON + if (uartdrv_handle->fcType != uartdrvFlowControlHwUart) { + UARTDRV_FlowControlSet(uartdrv_handle, uartdrvFlowControlAuto); + } + } + + return ec; +} +/****************************************************************************** + * Function to trigger the OS task to proceed + * + * @note Weak implementation. + *****************************************************************************/ +SL_WEAK void sl_simple_com_os_task_proceed(void) +{ + // No action on bare metal implementation +} diff --git a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h index 9fee028..64b8e43 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/app_assert.h @@ -1,165 +1,165 @@ -/***************************************************************************//** - * @file - * @brief Application assert interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef APP_ASSERT_H -#define APP_ASSERT_H - -#ifdef SL_COMPONENT_CATALOG_PRESENT -#include "sl_component_catalog.h" -#endif // SL_COMPONENT_CATALOG_PRESENT -#include "app_assert_config.h" -#include "sl_status.h" -#ifdef SL_CATALOG_APP_LOG_PRESENT -#include "app_log.h" -#endif - -#define APP_ASSERT_SEPARATOR ": " -#define APP_ASSERT_FORMAT "Assertion '%s' failed" -#define APP_ASSERT_TEXT "Assertion failed" - -#if defined(APP_ASSERT_ENABLE) && APP_ASSERT_ENABLE - -#ifdef HOST_TOOLCHAIN -#include -#define _app_assert_abort() abort() -#else -#define _app_assert_abort() while (1) -#endif // HOST_TOOLCHAIN - -#if defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE -#define _app_assert_trace() app_log_print_trace() -#else // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE -#define _app_assert_trace() -#endif // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE - -#if defined(SL_CATALOG_APP_LOG_PRESENT) \ - && APP_ASSERT_LOG_ENABLE \ - && defined(APP_LOG_ENABLE) \ - && APP_LOG_ENABLE - -#define _app_assert_log_status(sc, ...) \ - do { \ - app_log_nl(); \ - _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ - _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ - _app_log_time(); \ - _app_log_counter(); \ - _app_assert_trace(); \ - _app_log_print_status(sc); \ - app_log_append(__VA_ARGS__); \ - } while (0) - -#define _app_assert_log(...) \ - do { \ - app_log_nl(); \ - _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ - _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ - _app_log_time(); \ - _app_log_counter(); \ - _app_assert_trace(); \ - app_log_append(__VA_ARGS__); \ - } while (0) - -#define app_assert_s(expr) \ - do { \ - if (!(expr)) { \ - _app_assert_log(APP_ASSERT_FORMAT, \ - #expr); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert_status(sc) \ - do { \ - if (!(sc == SL_STATUS_OK)) { \ - _app_assert_log_status(sc, \ - APP_ASSERT_TEXT); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert_status_f(sc, ...) \ - do { \ - if (!(sc == SL_STATUS_OK)) { \ - _app_assert_log_status(sc, \ - APP_ASSERT_TEXT \ - APP_ASSERT_SEPARATOR \ - __VA_ARGS__); \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert(expr, ...) \ - do { \ - if (!(expr)) { \ - _app_assert_log(APP_ASSERT_FORMAT \ - APP_ASSERT_SEPARATOR, \ - #expr); \ - app_log_append(__VA_ARGS__); \ - _app_assert_abort(); \ - } \ - } while (0) - -#else // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE - -#define _app_assert_printless(expr) \ - do { \ - if (!(expr)) { \ - _app_assert_abort(); \ - } \ - } while (0) - -#define app_assert(expr, ...) \ - _app_assert_printless(expr) - -#define app_assert_s(expr) \ - _app_assert_printless(expr) - -#define app_assert_status(sc) \ - _app_assert_printless(sc == SL_STATUS_OK) - -#define app_assert_status_f(sc, ...) \ - _app_assert_printless(sc == SL_STATUS_OK) - -#endif // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE - -#else // APP_ASSERT_ENABLE - -#define app_assert(expr, ...) - -#define app_assert_s(expr) - -#define app_assert_status(sc) (void)sc - -#define app_assert_status_f(sc, ...) (void)sc - -#endif // APP_ASSERT_ENABLE - -#endif // APP_ASSERT_H +/***************************************************************************//** + * @file + * @brief Application assert interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef APP_ASSERT_H +#define APP_ASSERT_H + +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#endif // SL_COMPONENT_CATALOG_PRESENT +#include "app_assert_config.h" +#include "sl_status.h" +#ifdef SL_CATALOG_APP_LOG_PRESENT +#include "app_log.h" +#endif + +#define APP_ASSERT_SEPARATOR ": " +#define APP_ASSERT_FORMAT "Assertion '%s' failed" +#define APP_ASSERT_TEXT "Assertion failed" + +#if defined(APP_ASSERT_ENABLE) && APP_ASSERT_ENABLE + +#ifdef HOST_TOOLCHAIN +#include +#define _app_assert_abort() abort() +#else +#define _app_assert_abort() while (1) +#endif // HOST_TOOLCHAIN + +#if defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE +#define _app_assert_trace() app_log_print_trace() +#else // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE +#define _app_assert_trace() +#endif // defined(APP_ASSERT_TRACE_ENABLE) && APP_ASSERT_TRACE_ENABLE + +#if defined(SL_CATALOG_APP_LOG_PRESENT) \ + && APP_ASSERT_LOG_ENABLE \ + && defined(APP_LOG_ENABLE) \ + && APP_LOG_ENABLE + +#define _app_assert_log_status(sc, ...) \ + do { \ + app_log_nl(); \ + _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ + _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ + _app_log_time(); \ + _app_log_counter(); \ + _app_assert_trace(); \ + _app_log_print_status(sc); \ + app_log_append(__VA_ARGS__); \ + } while (0) + +#define _app_assert_log(...) \ + do { \ + app_log_nl(); \ + _app_log_print_color(APP_LOG_LEVEL_CRITICAL); \ + _app_log_print_prefix(APP_LOG_LEVEL_CRITICAL); \ + _app_log_time(); \ + _app_log_counter(); \ + _app_assert_trace(); \ + app_log_append(__VA_ARGS__); \ + } while (0) + +#define app_assert_s(expr) \ + do { \ + if (!(expr)) { \ + _app_assert_log(APP_ASSERT_FORMAT, \ + #expr); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert_status(sc) \ + do { \ + if (!(sc == SL_STATUS_OK)) { \ + _app_assert_log_status(sc, \ + APP_ASSERT_TEXT); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert_status_f(sc, ...) \ + do { \ + if (!(sc == SL_STATUS_OK)) { \ + _app_assert_log_status(sc, \ + APP_ASSERT_TEXT \ + APP_ASSERT_SEPARATOR \ + __VA_ARGS__); \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert(expr, ...) \ + do { \ + if (!(expr)) { \ + _app_assert_log(APP_ASSERT_FORMAT \ + APP_ASSERT_SEPARATOR, \ + #expr); \ + app_log_append(__VA_ARGS__); \ + _app_assert_abort(); \ + } \ + } while (0) + +#else // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE + +#define _app_assert_printless(expr) \ + do { \ + if (!(expr)) { \ + _app_assert_abort(); \ + } \ + } while (0) + +#define app_assert(expr, ...) \ + _app_assert_printless(expr) + +#define app_assert_s(expr) \ + _app_assert_printless(expr) + +#define app_assert_status(sc) \ + _app_assert_printless(sc == SL_STATUS_OK) + +#define app_assert_status_f(sc, ...) \ + _app_assert_printless(sc == SL_STATUS_OK) + +#endif // defined(SL_CATALOG_APP_LOG_PRESENT) && APP_ASSERT_LOG_ENABLE && defined(APP_LOG_ENABLE) && APP_LOG_ENABLE + +#else // APP_ASSERT_ENABLE + +#define app_assert(expr, ...) + +#define app_assert_s(expr) + +#define app_assert_status(sc) (void)sc + +#define app_assert_status_f(sc, ...) (void)sc + +#endif // APP_ASSERT_ENABLE + +#endif // APP_ASSERT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h index 01f97c3..c625ead 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_assert/sl_app_assert.h @@ -1,40 +1,40 @@ -/***************************************************************************//** - * @file - * @brief Application assert interface - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_APP_ASSERT_H -#define SL_APP_ASSERT_H - -#include "app_assert.h" - -#warning "sl_app_assert is deprecated and marked for removal in a later release. Please use app_assert instead." - -#define sl_app_assert(expr, ...) app_assert(expr, __VA_ARGS__) - -#endif // SL_APP_ASSERT_H +/***************************************************************************//** + * @file + * @brief Application assert interface + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_APP_ASSERT_H +#define SL_APP_ASSERT_H + +#include "app_assert.h" + +#warning "sl_app_assert is deprecated and marked for removal in a later release. Please use app_assert instead." + +#define sl_app_assert(expr, ...) app_assert(expr, __VA_ARGS__) + +#endif // SL_APP_ASSERT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.c b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.c index 72bfe92..c506cbd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.c +++ b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.c @@ -1,354 +1,354 @@ -/***************************************************************************//** - * @file - * @brief Timer service - * - * Timer service for applications with less strict timing requirements. - * This module is based on the sleeptimer, but runs the timer callbacks in - * non-interrupt context. This behavior gives more flexibility for the callback - * implementation but causes a less precise timing. - * - * @note If your application requires precise timing, please use the sleeptimer - * directly. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "app_timer.h" -#include "em_core.h" - -// ----------------------------------------------------------------------------- -// Definitions - -#define LONG_TIMER_CHECK(timer) (0 != timer->overflow_max) - -// ----------------------------------------------------------------------------- -// Private variables - -/// Number of the triggered timers. -static uint32_t trigger_count = 0; - -/// Start of the linked list which contains the active timers. -static app_timer_t *app_timer_head = NULL; - -// ----------------------------------------------------------------------------- -// Private function declarations - -/******************************************************************************* - * Common callback for the sleeptimers. - * - * @param[in] handle Pointer to the sleeptimer handle. - * @param[in] data Pointer to the sleeptimer's parent app timer. - * - * @note This function runs in interrupt context. - ******************************************************************************/ -static void app_timer_callback(sl_sleeptimer_timer_handle_t *handle, - void *data); - -/******************************************************************************* - * Append a timer to the end of the linked list. - * - * @param[in] timer Pointer to the timer handle. - * - * @pre Assumes that the timer is not present in the list. - ******************************************************************************/ -static void append_app_timer(app_timer_t *timer); - -/******************************************************************************* - * Remove a timer from the linked list. - * - * @param[in] timer Pointer to the timer handle. - * - * @return Presence of the timer in the linked list. - * @retval true Timer was in the list. - * @retval false Timer was not found in the list. - ******************************************************************************/ -static bool remove_app_timer(app_timer_t *timer); - -/******************************************************************************* - * Find and return the first triggered timer from the linked list. - * - * @return The first triggered timer from the linked list. - * - * @note The trigger state is also reset, and it is removed from the list if - * the timer is non-periodic. - ******************************************************************************/ -static app_timer_t *get_triggered_app_timer(void); - -// ----------------------------------------------------------------------------- -// Public function definitions - -sl_status_t app_timer_start(app_timer_t *timer, - uint32_t timeout_ms, - app_timer_callback_t callback, - void *callback_data, - bool is_periodic) -{ - sl_status_t sc; - uint32_t timeout_initial_tick; - uint32_t timer_freq; - uint64_t required_tick; - - // Check input parameters. - if ((timeout_ms == 0) && is_periodic) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Make sure that timer is stopped, also check for NULL. - sc = app_timer_stop(timer); - if (SL_STATUS_OK != sc) { - return sc; - } - - timer->triggered = false; - timer->overflow_counter = 0; - timer->overflow_max = 0; - - // Check if the timer has to be a long one - if (timeout_ms > sl_sleeptimer_get_max_ms32_conversion()) { - // Calculate the required ticks - timer_freq = sl_sleeptimer_get_timer_frequency(); - required_tick = ((uint64_t)timeout_ms * (uint64_t)timer_freq + 999) - / 1000; - - // Calculate the initial time in ticks for the first run and the number of - // maximum-time runs - timeout_initial_tick = (uint32_t)(required_tick % UINT32_MAX); - timer->overflow_max = (uint16_t)(required_tick / UINT32_MAX); - - // Start the timer with the initial time - sc = sl_sleeptimer_start_periodic_timer(&timer->sleeptimer_handle, - timeout_initial_tick, - app_timer_callback, - (void*)timer, - 0, - 0); - } else { - // Start sleeptimer with the given timeout/period. - if (is_periodic) { - sc = sl_sleeptimer_start_periodic_timer_ms( - &timer->sleeptimer_handle, - timeout_ms, - app_timer_callback, - (void*)timer, - 0, - 0); - } else { - sc = sl_sleeptimer_start_timer_ms( - &timer->sleeptimer_handle, - timeout_ms, - app_timer_callback, - (void*)timer, - 0, - 0); - } - } - - if (SL_STATUS_OK == sc) { - timer->callback = callback; - timer->callback_data = callback_data; - timer->periodic = is_periodic; - timer->timeout_ms = timeout_ms; - append_app_timer(timer); - } - return sc; -} - -sl_status_t app_timer_stop(app_timer_t *timer) -{ - bool timer_present; - - if (timer == NULL) { - return SL_STATUS_NULL_POINTER; - } - - // Stop sleeptimer, ignore error code if was not running. - (void)sl_sleeptimer_stop_timer(&timer->sleeptimer_handle); - - timer_present = remove_app_timer(timer); - if (timer_present && timer->triggered) { - // Timer has been triggered but not served yet. - CORE_ATOMIC_SECTION(--trigger_count; ) - } - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Execute timer callback functions. - ******************************************************************************/ -void sli_app_timer_step(void) -{ - if (trigger_count > 0) { - // Find triggered timers in list and call their callbacks. - app_timer_t *timer; - do { - timer = get_triggered_app_timer(); - if (timer != NULL) { - timer->callback(timer, timer->callback_data); - } - } while (timer != NULL); - } -} - -/***************************************************************************//** - * Routine for power manager handler - ******************************************************************************/ -sl_power_manager_on_isr_exit_t sli_app_timer_sleep_on_isr_exit(void) -{ - sl_power_manager_on_isr_exit_t ret = SL_POWER_MANAGER_IGNORE; - // if there is a triggered event, wake up to handle it - if (trigger_count > 0) { - ret = SL_POWER_MANAGER_WAKEUP; - } - return ret; -} - -/***************************************************************************//** - * Checks if it is ok to sleep now - ******************************************************************************/ -bool sli_app_timer_is_ok_to_sleep(void) -{ - bool ret = true; - // if there is a triggered event, do not go to sleep - if (trigger_count > 0) { - ret = false; - } - return ret; -} - -// ----------------------------------------------------------------------------- -// Private function definitions - -static void app_timer_callback(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - (void)handle; - app_timer_t *timer = (app_timer_t*)data; - if (timer->triggered == false) { - if (timer->overflow_counter < timer->overflow_max) { - // Timer has to run - if (timer->overflow_counter == 0) { - // For the first round, restart periodic timer with maximum value - sl_sleeptimer_restart_periodic_timer(&timer->sleeptimer_handle, - UINT32_MAX, - app_timer_callback, - (void*)timer, - 0, - 0); - } - timer->overflow_counter++; - } else { - if (LONG_TIMER_CHECK(timer)) { - if (timer->periodic) { - // Restart long timer - app_timer_start(timer, - timer->timeout_ms, - timer->callback, - timer->callback_data, - true); - } else { - // Stop periodic timer - sl_sleeptimer_stop_timer(&timer->sleeptimer_handle); - } - } - timer->triggered = true; - ++trigger_count; - } - } -} - -static void append_app_timer(app_timer_t *timer) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - - if (app_timer_head != NULL) { - app_timer_t *current = app_timer_head; - // Find end of list. - while (current->next != NULL) { - current = current->next; - } - current->next = timer; - } else { - app_timer_head = timer; - } - timer->next = NULL; - - CORE_EXIT_ATOMIC(); -} - -static bool remove_app_timer(app_timer_t *timer) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - - app_timer_t *prev = NULL; - app_timer_t *current = app_timer_head; - - // Find timer in list. - while (current != NULL && current != timer) { - prev = current; - current = current->next; - } - - if (current != timer) { - // Not found. - CORE_EXIT_ATOMIC(); - return false; - } - - if (prev != NULL) { - prev->next = timer->next; - } else { - app_timer_head = timer->next; - } - CORE_EXIT_ATOMIC(); - return true; -} - -static app_timer_t *get_triggered_app_timer(void) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_ATOMIC(); - - // Find the first triggered timer in list - app_timer_t *timer = app_timer_head; - while (timer != NULL) { - if (timer->triggered) { - // Timer found - timer->triggered = false; - --trigger_count; - if (!timer->periodic) { - (void)remove_app_timer(timer); - } - - CORE_EXIT_ATOMIC(); - return timer; - } - timer = timer->next; - } - - CORE_EXIT_ATOMIC(); - return NULL; -} +/***************************************************************************//** + * @file + * @brief Timer service + * + * Timer service for applications with less strict timing requirements. + * This module is based on the sleeptimer, but runs the timer callbacks in + * non-interrupt context. This behavior gives more flexibility for the callback + * implementation but causes a less precise timing. + * + * @note If your application requires precise timing, please use the sleeptimer + * directly. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "app_timer.h" +#include "em_core.h" + +// ----------------------------------------------------------------------------- +// Definitions + +#define LONG_TIMER_CHECK(timer) (0 != timer->overflow_max) + +// ----------------------------------------------------------------------------- +// Private variables + +/// Number of the triggered timers. +static uint32_t trigger_count = 0; + +/// Start of the linked list which contains the active timers. +static app_timer_t *app_timer_head = NULL; + +// ----------------------------------------------------------------------------- +// Private function declarations + +/******************************************************************************* + * Common callback for the sleeptimers. + * + * @param[in] handle Pointer to the sleeptimer handle. + * @param[in] data Pointer to the sleeptimer's parent app timer. + * + * @note This function runs in interrupt context. + ******************************************************************************/ +static void app_timer_callback(sl_sleeptimer_timer_handle_t *handle, + void *data); + +/******************************************************************************* + * Append a timer to the end of the linked list. + * + * @param[in] timer Pointer to the timer handle. + * + * @pre Assumes that the timer is not present in the list. + ******************************************************************************/ +static void append_app_timer(app_timer_t *timer); + +/******************************************************************************* + * Remove a timer from the linked list. + * + * @param[in] timer Pointer to the timer handle. + * + * @return Presence of the timer in the linked list. + * @retval true Timer was in the list. + * @retval false Timer was not found in the list. + ******************************************************************************/ +static bool remove_app_timer(app_timer_t *timer); + +/******************************************************************************* + * Find and return the first triggered timer from the linked list. + * + * @return The first triggered timer from the linked list. + * + * @note The trigger state is also reset, and it is removed from the list if + * the timer is non-periodic. + ******************************************************************************/ +static app_timer_t *get_triggered_app_timer(void); + +// ----------------------------------------------------------------------------- +// Public function definitions + +sl_status_t app_timer_start(app_timer_t *timer, + uint32_t timeout_ms, + app_timer_callback_t callback, + void *callback_data, + bool is_periodic) +{ + sl_status_t sc; + uint32_t timeout_initial_tick; + uint32_t timer_freq; + uint64_t required_tick; + + // Check input parameters. + if ((timeout_ms == 0) && is_periodic) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Make sure that timer is stopped, also check for NULL. + sc = app_timer_stop(timer); + if (SL_STATUS_OK != sc) { + return sc; + } + + timer->triggered = false; + timer->overflow_counter = 0; + timer->overflow_max = 0; + + // Check if the timer has to be a long one + if (timeout_ms > sl_sleeptimer_get_max_ms32_conversion()) { + // Calculate the required ticks + timer_freq = sl_sleeptimer_get_timer_frequency(); + required_tick = ((uint64_t)timeout_ms * (uint64_t)timer_freq + 999) + / 1000; + + // Calculate the initial time in ticks for the first run and the number of + // maximum-time runs + timeout_initial_tick = (uint32_t)(required_tick % UINT32_MAX); + timer->overflow_max = (uint16_t)(required_tick / UINT32_MAX); + + // Start the timer with the initial time + sc = sl_sleeptimer_start_periodic_timer(&timer->sleeptimer_handle, + timeout_initial_tick, + app_timer_callback, + (void*)timer, + 0, + 0); + } else { + // Start sleeptimer with the given timeout/period. + if (is_periodic) { + sc = sl_sleeptimer_start_periodic_timer_ms( + &timer->sleeptimer_handle, + timeout_ms, + app_timer_callback, + (void*)timer, + 0, + 0); + } else { + sc = sl_sleeptimer_start_timer_ms( + &timer->sleeptimer_handle, + timeout_ms, + app_timer_callback, + (void*)timer, + 0, + 0); + } + } + + if (SL_STATUS_OK == sc) { + timer->callback = callback; + timer->callback_data = callback_data; + timer->periodic = is_periodic; + timer->timeout_ms = timeout_ms; + append_app_timer(timer); + } + return sc; +} + +sl_status_t app_timer_stop(app_timer_t *timer) +{ + bool timer_present; + + if (timer == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Stop sleeptimer, ignore error code if was not running. + (void)sl_sleeptimer_stop_timer(&timer->sleeptimer_handle); + + timer_present = remove_app_timer(timer); + if (timer_present && timer->triggered) { + // Timer has been triggered but not served yet. + CORE_ATOMIC_SECTION(--trigger_count; ) + } + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Execute timer callback functions. + ******************************************************************************/ +void sli_app_timer_step(void) +{ + if (trigger_count > 0) { + // Find triggered timers in list and call their callbacks. + app_timer_t *timer; + do { + timer = get_triggered_app_timer(); + if (timer != NULL) { + timer->callback(timer, timer->callback_data); + } + } while (timer != NULL); + } +} + +/***************************************************************************//** + * Routine for power manager handler + ******************************************************************************/ +sl_power_manager_on_isr_exit_t sli_app_timer_sleep_on_isr_exit(void) +{ + sl_power_manager_on_isr_exit_t ret = SL_POWER_MANAGER_IGNORE; + // if there is a triggered event, wake up to handle it + if (trigger_count > 0) { + ret = SL_POWER_MANAGER_WAKEUP; + } + return ret; +} + +/***************************************************************************//** + * Checks if it is ok to sleep now + ******************************************************************************/ +bool sli_app_timer_is_ok_to_sleep(void) +{ + bool ret = true; + // if there is a triggered event, do not go to sleep + if (trigger_count > 0) { + ret = false; + } + return ret; +} + +// ----------------------------------------------------------------------------- +// Private function definitions + +static void app_timer_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + (void)handle; + app_timer_t *timer = (app_timer_t*)data; + if (timer->triggered == false) { + if (timer->overflow_counter < timer->overflow_max) { + // Timer has to run + if (timer->overflow_counter == 0) { + // For the first round, restart periodic timer with maximum value + sl_sleeptimer_restart_periodic_timer(&timer->sleeptimer_handle, + UINT32_MAX, + app_timer_callback, + (void*)timer, + 0, + 0); + } + timer->overflow_counter++; + } else { + if (LONG_TIMER_CHECK(timer)) { + if (timer->periodic) { + // Restart long timer + app_timer_start(timer, + timer->timeout_ms, + timer->callback, + timer->callback_data, + true); + } else { + // Stop periodic timer + sl_sleeptimer_stop_timer(&timer->sleeptimer_handle); + } + } + timer->triggered = true; + ++trigger_count; + } + } +} + +static void append_app_timer(app_timer_t *timer) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + if (app_timer_head != NULL) { + app_timer_t *current = app_timer_head; + // Find end of list. + while (current->next != NULL) { + current = current->next; + } + current->next = timer; + } else { + app_timer_head = timer; + } + timer->next = NULL; + + CORE_EXIT_ATOMIC(); +} + +static bool remove_app_timer(app_timer_t *timer) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + app_timer_t *prev = NULL; + app_timer_t *current = app_timer_head; + + // Find timer in list. + while (current != NULL && current != timer) { + prev = current; + current = current->next; + } + + if (current != timer) { + // Not found. + CORE_EXIT_ATOMIC(); + return false; + } + + if (prev != NULL) { + prev->next = timer->next; + } else { + app_timer_head = timer->next; + } + CORE_EXIT_ATOMIC(); + return true; +} + +static app_timer_t *get_triggered_app_timer(void) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_ATOMIC(); + + // Find the first triggered timer in list + app_timer_t *timer = app_timer_head; + while (timer != NULL) { + if (timer->triggered) { + // Timer found + timer->triggered = false; + --trigger_count; + if (!timer->periodic) { + (void)remove_app_timer(timer); + } + + CORE_EXIT_ATOMIC(); + return timer; + } + timer = timer->next; + } + + CORE_EXIT_ATOMIC(); + return NULL; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.h b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.h index 58758d7..158c83b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/app_timer.h @@ -1,117 +1,117 @@ -/***************************************************************************//** - * @file - * @brief Timer service header - * - * Timer service for applications with less strict timing requirements. - * This module is based on the sleeptimer, but runs the timer callbacks in - * non-interrupt context. This behavior gives more flexibility for the callback - * implementation but causes a less precise timing. - * - * @note If your application requires precise timing, please use the sleeptimer - * directly. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef APP_TIMER_H -#define APP_TIMER_H - -#include -#include -#include "sl_sleeptimer.h" -#include "sl_power_manager.h" - -// Forward declaration -typedef struct app_timer app_timer_t; - -/***************************************************************************//** - * Expected prototype of the user's callback function which is called when a - * timer expires. - * - * @param timer Pointer to the timer handle. - * @param data An extra parameter for the user application. - ******************************************************************************/ -typedef void (*app_timer_callback_t)(app_timer_t *timer, void *data); - -/// Timer structure -struct app_timer { - sl_sleeptimer_timer_handle_t sleeptimer_handle; - app_timer_callback_t callback; - void *callback_data; - app_timer_t *next; - bool triggered; - bool periodic; - uint32_t timeout_ms; - uint16_t overflow_counter; - uint16_t overflow_max; -}; - -/***************************************************************************//** - * Start timer or restart if it is running already. - * - * @param[in] timer Pointer to the timer. - * @param[in] timeout_ms Timer timeout, in milliseconds. - * @param[in] callback Callback function that is called when timeout expires. - * @param[in] callback_data Pointer to user data that will be passed to callback. - * @param[in] is_periodic Reload timer when it expires if true. - * - * @return Status of the operation. - ******************************************************************************/ -sl_status_t app_timer_start(app_timer_t *timer, - uint32_t timeout_ms, - app_timer_callback_t callback, - void *callback_data, - bool is_periodic); - -/***************************************************************************//** - * Stop running timer. - * - * @param[in] timer Pointer to the timer. - * - * @return Status of the operation. - ******************************************************************************/ -sl_status_t app_timer_stop(app_timer_t *timer); - -/***************************************************************************//** - * Execute timer callback functions. - * - ******************************************************************************/ -void sli_app_timer_step(void); - -/***************************************************************************//** - * Routine for power manager handler - * - * @return SL_POWER_MANAGER_WAKEUP if there is an unhandled timer event - ******************************************************************************/ -sl_power_manager_on_isr_exit_t sli_app_timer_sleep_on_isr_exit(void); - -/***************************************************************************//** - * Checks if it is ok to sleep now - * - * @return false if there is an unhandled timer event - ******************************************************************************/ -bool sli_app_timer_is_ok_to_sleep(void); - -#endif // APP_TIMER_H +/***************************************************************************//** + * @file + * @brief Timer service header + * + * Timer service for applications with less strict timing requirements. + * This module is based on the sleeptimer, but runs the timer callbacks in + * non-interrupt context. This behavior gives more flexibility for the callback + * implementation but causes a less precise timing. + * + * @note If your application requires precise timing, please use the sleeptimer + * directly. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef APP_TIMER_H +#define APP_TIMER_H + +#include +#include +#include "sl_sleeptimer.h" +#include "sl_power_manager.h" + +// Forward declaration +typedef struct app_timer app_timer_t; + +/***************************************************************************//** + * Expected prototype of the user's callback function which is called when a + * timer expires. + * + * @param timer Pointer to the timer handle. + * @param data An extra parameter for the user application. + ******************************************************************************/ +typedef void (*app_timer_callback_t)(app_timer_t *timer, void *data); + +/// Timer structure +struct app_timer { + sl_sleeptimer_timer_handle_t sleeptimer_handle; + app_timer_callback_t callback; + void *callback_data; + app_timer_t *next; + bool triggered; + bool periodic; + uint32_t timeout_ms; + uint16_t overflow_counter; + uint16_t overflow_max; +}; + +/***************************************************************************//** + * Start timer or restart if it is running already. + * + * @param[in] timer Pointer to the timer. + * @param[in] timeout_ms Timer timeout, in milliseconds. + * @param[in] callback Callback function that is called when timeout expires. + * @param[in] callback_data Pointer to user data that will be passed to callback. + * @param[in] is_periodic Reload timer when it expires if true. + * + * @return Status of the operation. + ******************************************************************************/ +sl_status_t app_timer_start(app_timer_t *timer, + uint32_t timeout_ms, + app_timer_callback_t callback, + void *callback_data, + bool is_periodic); + +/***************************************************************************//** + * Stop running timer. + * + * @param[in] timer Pointer to the timer. + * + * @return Status of the operation. + ******************************************************************************/ +sl_status_t app_timer_stop(app_timer_t *timer); + +/***************************************************************************//** + * Execute timer callback functions. + * + ******************************************************************************/ +void sli_app_timer_step(void); + +/***************************************************************************//** + * Routine for power manager handler + * + * @return SL_POWER_MANAGER_WAKEUP if there is an unhandled timer event + ******************************************************************************/ +sl_power_manager_on_isr_exit_t sli_app_timer_sleep_on_isr_exit(void); + +/***************************************************************************//** + * Checks if it is ok to sleep now + * + * @return false if there is an unhandled timer event + ******************************************************************************/ +bool sli_app_timer_is_ok_to_sleep(void); + +#endif // APP_TIMER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/sl_simple_timer.h b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/sl_simple_timer.h index 3467907..559d051 100644 --- a/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/sl_simple_timer.h +++ b/locator_ncp/gecko_sdk_4.4.1/app/common/util/app_timer/sl_simple_timer.h @@ -1,43 +1,43 @@ -/***************************************************************************//** - * @file - * @brief Timer service compatibility header - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SIMPLE_TIMER_H -#define SL_SIMPLE_TIMER_H - -#include "app_timer.h" - -#warning "sl_simple_timer is deprecated and marked for removal in a later release. Please use app_timer instead." - -// Timer structure -typedef app_timer_t sl_simple_timer_t; - -#define sl_simple_timer_start(...) app_timer_start(__VA_ARGS__) -#define sl_simple_timer_stop(...) app_timer_stop(__VA_ARGS__) - -#endif // SL_SIMPLE_TIMER_H +/***************************************************************************//** + * @file + * @brief Timer service compatibility header + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SIMPLE_TIMER_H +#define SL_SIMPLE_TIMER_H + +#include "app_timer.h" + +#warning "sl_simple_timer is deprecated and marked for removal in a later release. Please use app_timer instead." + +// Timer structure +typedef app_timer_t sl_simple_timer_t; + +#define sl_simple_timer_start(...) app_timer_start(__VA_ARGS__) +#define sl_simple_timer_stop(...) app_timer_stop(__VA_ARGS__) + +#endif // SL_SIMPLE_TIMER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h b/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h index a629332..0000f6a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_control.h @@ -1,219 +1,219 @@ -/***************************************************************************//** - * @file - * @brief Board Control API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_BOARD_CONTROL_H -#define SL_BOARD_CONTROL_H - -#include "sl_status.h" -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup board_control Board Control - * @brief Functions to control Silicon Labs board features - * @{ - ******************************************************************************/ - -/// Board Sensor Type -SL_ENUM_GENERIC(sl_board_sensor_t, int) { - SL_BOARD_SENSOR_RHT = (1UL << 0UL), ///< Relative Humidity and Temperature Sensor - SL_BOARD_SENSOR_LIGHT = (1UL << 1UL), ///< UV Index and Ambient Light Sensor - SL_BOARD_SENSOR_PRESSURE = (1UL << 2UL), ///< Barometric Pressure Sensor - SL_BOARD_SENSOR_HALL = (1UL << 3UL), ///< Hall Effect Sensor - SL_BOARD_SENSOR_GAS = (1UL << 4UL), ///< Gas Sensor - SL_BOARD_SENSOR_IMU = (1UL << 5UL), ///< Inertial Measurement Unit (Accelerometer/Gyroscope) - SL_BOARD_SENSOR_MICROPHONE = (1UL << 6UL), ///< Microphone -}; - -/// Board Memory Type -SL_ENUM_GENERIC(sl_board_memory_t, int) { - SL_BOARD_MEMORY_SDCARD = (1UL << 0UL), ///< SD Card - SL_BOARD_MEMORY_QSPI = (1UL << 1UL), ///< Quad SPI Flash -}; - -/// Board Oscillator Type -SL_ENUM_GENERIC(sl_board_oscillator_t, int) { - SL_BOARD_OSCILLATOR_TCXO = (1UL << 0UL), ///< TCXO -}; - -/***************************************************************************//** - * @brief Configure Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully enabled - * @retval SL_STATUS_FAIL Enabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - * @retval SL_STATUS_NOT_SUPPORTED VCOM enabled was not configured - ******************************************************************************/ -sl_status_t sl_board_configure_vcom(void); - -/***************************************************************************//** - * @brief Enable Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully enabled - * @retval SL_STATUS_FAIL Enabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_vcom(void); - -/***************************************************************************//** - * @brief Disable Virtual COM UART. - * - * @return Status code - * @retval SL_STATUS_OK VCOM was successfully disabled - * @retval SL_STATUS_FAIL Disabling VCOM failed - * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_vcom(void); - -/***************************************************************************//** - * @brief Enable a sensor. - * - * @warning - * On boards 4166A, 4184A, and 4184B sensors - * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; - * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; - * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor - * respectively, are tied to the same enable pin. Calling the enable function - * for only one of these sensors has the side-effect of enabling all three; - * and calling the disable function for only one of them has the - * side-effect of disabling all three. - * The latter scenario seems less than desirable. - * - * @param[in] sensor Sensor to enable - * - * @return Status code - * @retval SL_STATUS_OK Sensor was successfully enabled - * @retval SL_STATUS_FAIL Enabling sensor failed - * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor); - -/***************************************************************************//** - * @brief Disable a sensor. - * - * @warning - * On boards 4166A, 4184A, and 4184B sensors - * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; - * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; - * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor - * respectively, are tied to the same enable pin. Calling the enable function - * for only one of these sensors has the side-effect of enabling all three; - * and calling the disable function for only one of them has the - * side-effect of disabling all three. - * The latter scenario seems less than desirable. - * - * @param[in] sensor Sensors to disable - * - * @return Status code - * @retval SL_STATUS_OK Sensor was successfully disabled - * @retval SL_STATUS_FAIL Disabling sensor failed - * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor); - -/***************************************************************************//** - * @brief Enable display. - * - * @return Status code - * @retval SL_STATUS_OK Display was successfully enabled - * @retval SL_STATUS_FAIL Enabling display failed - * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_display(void); - -/***************************************************************************//** - * @brief Disable display. - * - * @return Status code - * @retval SL_STATUS_OK Display was successfully disabled - * @retval SL_STATUS_FAIL Disabling display failed - * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_display(void); - -/***************************************************************************//** - * @brief Enable memory. - * - * @param[in] memory Memory to enable - * - * @return Status code - * @retval SL_STATUS_OK Memory was successfully enabled - * @retval SL_STATUS_FAIL Enabling memory failed - * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_memory(sl_board_memory_t memory); - -/***************************************************************************//** - * @brief Disable memory. - * - * @param[in] memory Memory to disable - * - * @return Status code - * @retval SL_STATUS_OK Memory was successfully disabled - * @retval SL_STATUS_FAIL Disabling memory failed - * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_memory(sl_board_memory_t memory); - -/***************************************************************************//** - * @brief Enable an oscillator. - * - * @param[in] oscillator Oscillator to enable - * - * @return Status code - * @retval SL_STATUS_OK Oscillator was successfully enabled - * @retval SL_STATUS_FAIL Enabling oscillator failed - * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator); - -/***************************************************************************//** - * @brief Disable a oscillator. - * - * @param[in] oscillator Oscillator to disable - * - * @return Status code - * @retval SL_STATUS_OK Oscillator was successfully disabled - * @retval SL_STATUS_FAIL Disabling oscillator failed - * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board - ******************************************************************************/ -sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator); - -/** @} */ - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // SL_BOARD_CONTROL_H +/***************************************************************************//** + * @file + * @brief Board Control API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_BOARD_CONTROL_H +#define SL_BOARD_CONTROL_H + +#include "sl_status.h" +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup board_control Board Control + * @brief Functions to control Silicon Labs board features + * @{ + ******************************************************************************/ + +/// Board Sensor Type +SL_ENUM_GENERIC(sl_board_sensor_t, int) { + SL_BOARD_SENSOR_RHT = (1UL << 0UL), ///< Relative Humidity and Temperature Sensor + SL_BOARD_SENSOR_LIGHT = (1UL << 1UL), ///< UV Index and Ambient Light Sensor + SL_BOARD_SENSOR_PRESSURE = (1UL << 2UL), ///< Barometric Pressure Sensor + SL_BOARD_SENSOR_HALL = (1UL << 3UL), ///< Hall Effect Sensor + SL_BOARD_SENSOR_GAS = (1UL << 4UL), ///< Gas Sensor + SL_BOARD_SENSOR_IMU = (1UL << 5UL), ///< Inertial Measurement Unit (Accelerometer/Gyroscope) + SL_BOARD_SENSOR_MICROPHONE = (1UL << 6UL), ///< Microphone +}; + +/// Board Memory Type +SL_ENUM_GENERIC(sl_board_memory_t, int) { + SL_BOARD_MEMORY_SDCARD = (1UL << 0UL), ///< SD Card + SL_BOARD_MEMORY_QSPI = (1UL << 1UL), ///< Quad SPI Flash +}; + +/// Board Oscillator Type +SL_ENUM_GENERIC(sl_board_oscillator_t, int) { + SL_BOARD_OSCILLATOR_TCXO = (1UL << 0UL), ///< TCXO +}; + +/***************************************************************************//** + * @brief Configure Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully enabled + * @retval SL_STATUS_FAIL Enabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + * @retval SL_STATUS_NOT_SUPPORTED VCOM enabled was not configured + ******************************************************************************/ +sl_status_t sl_board_configure_vcom(void); + +/***************************************************************************//** + * @brief Enable Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully enabled + * @retval SL_STATUS_FAIL Enabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_vcom(void); + +/***************************************************************************//** + * @brief Disable Virtual COM UART. + * + * @return Status code + * @retval SL_STATUS_OK VCOM was successfully disabled + * @retval SL_STATUS_FAIL Disabling VCOM failed + * @retval SL_STATUS_NOT_AVAILABLE VCOM control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_vcom(void); + +/***************************************************************************//** + * @brief Enable a sensor. + * + * @warning + * On boards 4166A, 4184A, and 4184B sensors + * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; + * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; + * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor + * respectively, are tied to the same enable pin. Calling the enable function + * for only one of these sensors has the side-effect of enabling all three; + * and calling the disable function for only one of them has the + * side-effect of disabling all three. + * The latter scenario seems less than desirable. + * + * @param[in] sensor Sensor to enable + * + * @return Status code + * @retval SL_STATUS_OK Sensor was successfully enabled + * @retval SL_STATUS_FAIL Enabling sensor failed + * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor); + +/***************************************************************************//** + * @brief Disable a sensor. + * + * @warning + * On boards 4166A, 4184A, and 4184B sensors + * - Pressure Sensor, RH/Temp Sensor, and UV/Ambient Light Sensor; + * - UV/Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor; + * - Ambient Light Sensor, Hall-effect Sensor, and RH/Temp Sensor + * respectively, are tied to the same enable pin. Calling the enable function + * for only one of these sensors has the side-effect of enabling all three; + * and calling the disable function for only one of them has the + * side-effect of disabling all three. + * The latter scenario seems less than desirable. + * + * @param[in] sensor Sensors to disable + * + * @return Status code + * @retval SL_STATUS_OK Sensor was successfully disabled + * @retval SL_STATUS_FAIL Disabling sensor failed + * @retval SL_STATUS_NOT_AVAILABLE Sensor control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor); + +/***************************************************************************//** + * @brief Enable display. + * + * @return Status code + * @retval SL_STATUS_OK Display was successfully enabled + * @retval SL_STATUS_FAIL Enabling display failed + * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_display(void); + +/***************************************************************************//** + * @brief Disable display. + * + * @return Status code + * @retval SL_STATUS_OK Display was successfully disabled + * @retval SL_STATUS_FAIL Disabling display failed + * @retval SL_STATUS_NOT_AVAILABLE Display control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_display(void); + +/***************************************************************************//** + * @brief Enable memory. + * + * @param[in] memory Memory to enable + * + * @return Status code + * @retval SL_STATUS_OK Memory was successfully enabled + * @retval SL_STATUS_FAIL Enabling memory failed + * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_memory(sl_board_memory_t memory); + +/***************************************************************************//** + * @brief Disable memory. + * + * @param[in] memory Memory to disable + * + * @return Status code + * @retval SL_STATUS_OK Memory was successfully disabled + * @retval SL_STATUS_FAIL Disabling memory failed + * @retval SL_STATUS_NOT_AVAILABLE Memory control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_memory(sl_board_memory_t memory); + +/***************************************************************************//** + * @brief Enable an oscillator. + * + * @param[in] oscillator Oscillator to enable + * + * @return Status code + * @retval SL_STATUS_OK Oscillator was successfully enabled + * @retval SL_STATUS_FAIL Enabling oscillator failed + * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator); + +/***************************************************************************//** + * @brief Disable a oscillator. + * + * @param[in] oscillator Oscillator to disable + * + * @return Status code + * @retval SL_STATUS_OK Oscillator was successfully disabled + * @retval SL_STATUS_FAIL Disabling oscillator failed + * @retval SL_STATUS_NOT_AVAILABLE Oscillator control is not available on this board + ******************************************************************************/ +sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator); + +/** @} */ + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // SL_BOARD_CONTROL_H diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h b/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h index 8bd5f4b..036ff64 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/board/inc/sl_board_init.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief Board Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_BOARD_INIT_H -#define SL_BOARD_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup board_init Board Init - * @brief Initialization of Silicon Labs board features - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Initialize board. - * @details - * Initialize a Silicon Labs board by enabling available and configured board - * features, in addition to performing necessary board errata fixes and setting - * default pin states. - ******************************************************************************/ -void sl_board_init(void); - -/***************************************************************************//** - * @brief Initialize board features that are required at early boot. - * @details - * Certain board features such as external oscillators may need to be powered - * before core device features, such as the clock tree, are configured. - ******************************************************************************/ -void sl_board_preinit(void); -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_BOARD_INIT_H +/***************************************************************************//** + * @file + * @brief Board Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_BOARD_INIT_H +#define SL_BOARD_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup board_init Board Init + * @brief Initialization of Silicon Labs board features + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Initialize board. + * @details + * Initialize a Silicon Labs board by enabling available and configured board + * features, in addition to performing necessary board errata fixes and setting + * default pin states. + ******************************************************************************/ +void sl_board_init(void); + +/***************************************************************************//** + * @brief Initialize board features that are required at early boot. + * @details + * Certain board features such as external oscillators may need to be powered + * before core device features, such as the clock tree, are configured. + ******************************************************************************/ +void sl_board_preinit(void); +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_BOARD_INIT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c b/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c index 0d02db2..5e318e5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_control_gpio.c @@ -1,455 +1,455 @@ -/***************************************************************************//** - * @file - * @brief Board Control API - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" -#include "sl_board_control_config.h" -#include "em_device.h" - -#if defined(_SILICON_LABS_32B_SERIES_3) -#include "sl_peripheral_gpio.h" -#else -#include "em_gpio.h" -#endif - -sl_status_t sl_board_configure_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM) && SL_BOARD_ENABLE_VCOM - return sl_board_enable_vcom(); -#else - return SL_STATUS_NOT_SUPPORTED; -#endif -} - -sl_status_t sl_board_enable_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 1); -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_disable_vcom(void) -{ -#if defined(SL_BOARD_ENABLE_VCOM_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 0); -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_enable_display(void) -{ -#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 1); -#endif -#if defined(SL_BOARD_SELECT_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#else - GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 1); -#endif -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_disable_display(void) -{ -#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 0); -#endif -#if defined(SL_BOARD_SELECT_DISPLAY_PORT) -#if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); -#else - GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 0); -#endif -#endif - return SL_STATUS_OK; -#else - return SL_STATUS_NOT_AVAILABLE; -#endif -} - -sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (sensor) { - case SL_BOARD_SENSOR_RHT: - #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_LIGHT: - #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_PRESSURE: - #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_HALL: - #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_GAS: - #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_IMU: - #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_MICROPHONE: - #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (sensor) { - case SL_BOARD_SENSOR_RHT: - #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_LIGHT: - #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_PRESSURE: - #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_HALL: - #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_GAS: - #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_IMU: - #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_SENSOR_MICROPHONE: - #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_enable_memory(sl_board_memory_t memory) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (memory) { - case SL_BOARD_MEMORY_SDCARD: - #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_MEMORY_QSPI: - #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_memory(sl_board_memory_t memory) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (memory) { - case SL_BOARD_MEMORY_SDCARD: - #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - case SL_BOARD_MEMORY_QSPI: - #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (oscillator) { - case SL_BOARD_OSCILLATOR_TCXO: - #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 1); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 1); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} - -sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator) -{ - sl_status_t status = SL_STATUS_NOT_AVAILABLE; - - switch (oscillator) { - case SL_BOARD_OSCILLATOR_TCXO: - #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) - #if defined(_SILICON_LABS_32B_SERIES_3) - sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 0); - #else - GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 0); - #endif - status = SL_STATUS_OK; - #else - EFM_ASSERT(false); - #endif - break; - - default: - EFM_ASSERT(false); // Should not happen - break; - } - - return status; -} +/***************************************************************************//** + * @file + * @brief Board Control API + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" +#include "sl_board_control_config.h" +#include "em_device.h" + +#if defined(_SILICON_LABS_32B_SERIES_3) +#include "sl_peripheral_gpio.h" +#else +#include "em_gpio.h" +#endif + +sl_status_t sl_board_configure_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM) && SL_BOARD_ENABLE_VCOM + return sl_board_enable_vcom(); +#else + return SL_STATUS_NOT_SUPPORTED; +#endif +} + +sl_status_t sl_board_enable_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 1); +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_disable_vcom(void) +{ +#if defined(SL_BOARD_ENABLE_VCOM_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_VCOM_PORT, SL_BOARD_ENABLE_VCOM_PIN, gpioModePushPull, 0); +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_enable_display(void) +{ +#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 1); +#endif +#if defined(SL_BOARD_SELECT_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#else + GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 1); +#endif +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_disable_display(void) +{ +#if defined(SL_BOARD_ENABLE_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_ENABLE_DISPLAY_PORT, SL_BOARD_ENABLE_DISPLAY_PIN, gpioModePushPull, 0); +#endif +#if defined(SL_BOARD_SELECT_DISPLAY_PORT) +#if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, SL_GPIO_MODE_PUSH_PULL, 0); +#else + GPIO_PinModeSet(SL_BOARD_SELECT_DISPLAY_PORT, SL_BOARD_SELECT_DISPLAY_PIN, gpioModePushPull, 0); +#endif +#endif + return SL_STATUS_OK; +#else + return SL_STATUS_NOT_AVAILABLE; +#endif +} + +sl_status_t sl_board_enable_sensor(sl_board_sensor_t sensor) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (sensor) { + case SL_BOARD_SENSOR_RHT: + #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_LIGHT: + #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_PRESSURE: + #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_HALL: + #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_GAS: + #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_IMU: + #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_MICROPHONE: + #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_sensor(sl_board_sensor_t sensor) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (sensor) { + case SL_BOARD_SENSOR_RHT: + #if defined(SL_BOARD_ENABLE_SENSOR_RHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_RHT_PORT, SL_BOARD_ENABLE_SENSOR_RHT_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_LIGHT: + #if defined(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_LIGHT_PORT, SL_BOARD_ENABLE_SENSOR_LIGHT_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_PRESSURE: + #if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_PRESSURE_PORT, SL_BOARD_ENABLE_SENSOR_PRESSURE_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_HALL: + #if defined(SL_BOARD_ENABLE_SENSOR_HALL_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_HALL_PORT, SL_BOARD_ENABLE_SENSOR_HALL_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_GAS: + #if defined(SL_BOARD_ENABLE_SENSOR_GAS_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_GAS_PORT, SL_BOARD_ENABLE_SENSOR_GAS_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_IMU: + #if defined(SL_BOARD_ENABLE_SENSOR_IMU_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_IMU_PORT, SL_BOARD_ENABLE_SENSOR_IMU_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_SENSOR_MICROPHONE: + #if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_SENSOR_MICROPHONE_PORT, SL_BOARD_ENABLE_SENSOR_MICROPHONE_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_enable_memory(sl_board_memory_t memory) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (memory) { + case SL_BOARD_MEMORY_SDCARD: + #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_MEMORY_QSPI: + #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_memory(sl_board_memory_t memory) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (memory) { + case SL_BOARD_MEMORY_SDCARD: + #if defined(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_SDCARD_PORT, SL_BOARD_ENABLE_MEMORY_SDCARD_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + case SL_BOARD_MEMORY_QSPI: + #if defined(SL_BOARD_ENABLE_MEMORY_QSPI_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_MEMORY_QSPI_PORT, SL_BOARD_ENABLE_MEMORY_QSPI_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_enable_oscillator(sl_board_oscillator_t oscillator) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (oscillator) { + case SL_BOARD_OSCILLATOR_TCXO: + #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 1); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 1); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} + +sl_status_t sl_board_disable_oscillator(sl_board_oscillator_t oscillator) +{ + sl_status_t status = SL_STATUS_NOT_AVAILABLE; + + switch (oscillator) { + case SL_BOARD_OSCILLATOR_TCXO: + #if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT) + #if defined(_SILICON_LABS_32B_SERIES_3) + sl_gpio_set_pin_mode(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, SL_GPIO_MODE_PUSH_PULL, 0); + #else + GPIO_PinModeSet(SL_BOARD_ENABLE_OSCILLATOR_TCXO_PORT, SL_BOARD_ENABLE_OSCILLATOR_TCXO_PIN, gpioModePushPull, 0); + #endif + status = SL_STATUS_OK; + #else + EFM_ASSERT(false); + #endif + break; + + default: + EFM_ASSERT(false); // Should not happen + break; + } + + return status; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c b/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c index bbe57b0..bdcb8a5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/board/src/sl_board_init.c @@ -1,98 +1,98 @@ -/***************************************************************************//** - * @file - * @brief Board Init - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_board_control.h" -#include "sl_board_control_config.h" - -#include "em_cmu.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT) -#include "sl_mx25_flash_shutdown.h" -#endif - -void sl_board_default_init(void); - -void sl_board_init(void) -{ - CMU_ClockEnable(cmuClock_GPIO, true); - - // Errata fixes and default pin states - sl_board_default_init(); - -#if defined(SL_BOARD_ENABLE_SENSOR_RHT) && SL_BOARD_ENABLE_SENSOR_RHT - sl_board_enable_sensor(SL_BOARD_SENSOR_RHT); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT) && SL_BOARD_ENABLE_SENSOR_LIGHT - sl_board_enable_sensor(SL_BOARD_SENSOR_LIGHT); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE) && SL_BOARD_ENABLE_SENSOR_PRESSURE - sl_board_enable_sensor(SL_BOARD_SENSOR_PRESSURE); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_HALL) && SL_BOARD_ENABLE_SENSOR_HALL - sl_board_enable_sensor(SL_BOARD_SENSOR_HALL); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_GAS) && SL_BOARD_ENABLE_SENSOR_GAS - sl_board_enable_sensor(SL_BOARD_SENSOR_GAS); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_IMU) && SL_BOARD_ENABLE_SENSOR_IMU - sl_board_enable_sensor(SL_BOARD_SENSOR_IMU); -#endif -#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE) && SL_BOARD_ENABLE_SENSOR_MICROPHONE - sl_board_enable_sensor(SL_BOARD_SENSOR_MICROPHONE); -#endif - -#if defined(SL_BOARD_ENABLE_DISPLAY) && SL_BOARD_ENABLE_DISPLAY - sl_board_enable_display(); -#endif - -#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD) && SL_BOARD_ENABLE_MEMORY_SDCARD - sl_board_enable_memory(SL_BOARD_MEMORY_SDCARD); -#endif -#if defined(SL_BOARD_ENABLE_MEMORY_QSPI) && SL_BOARD_ENABLE_MEMORY_QSPI - sl_board_enable_memory(SL_BOARD_MEMORY_QSPI); -#endif - -#if (defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)) && \ - defined(SL_BOARD_DISABLE_MEMORY_SPI) && SL_BOARD_DISABLE_MEMORY_SPI - sl_mx25_flash_shutdown(); -#endif -} - -void sl_board_preinit(void) -{ - CMU_ClockEnable(cmuClock_GPIO, true); - -#if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO) && SL_BOARD_ENABLE_OSCILLATOR_TCXO - sl_board_enable_oscillator(SL_BOARD_OSCILLATOR_TCXO); -#endif -} +/***************************************************************************//** + * @file + * @brief Board Init + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_board_control.h" +#include "sl_board_control_config.h" + +#include "em_cmu.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT) +#include "sl_mx25_flash_shutdown.h" +#endif + +void sl_board_default_init(void); + +void sl_board_init(void) +{ + CMU_ClockEnable(cmuClock_GPIO, true); + + // Errata fixes and default pin states + sl_board_default_init(); + +#if defined(SL_BOARD_ENABLE_SENSOR_RHT) && SL_BOARD_ENABLE_SENSOR_RHT + sl_board_enable_sensor(SL_BOARD_SENSOR_RHT); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_LIGHT) && SL_BOARD_ENABLE_SENSOR_LIGHT + sl_board_enable_sensor(SL_BOARD_SENSOR_LIGHT); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_PRESSURE) && SL_BOARD_ENABLE_SENSOR_PRESSURE + sl_board_enable_sensor(SL_BOARD_SENSOR_PRESSURE); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_HALL) && SL_BOARD_ENABLE_SENSOR_HALL + sl_board_enable_sensor(SL_BOARD_SENSOR_HALL); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_GAS) && SL_BOARD_ENABLE_SENSOR_GAS + sl_board_enable_sensor(SL_BOARD_SENSOR_GAS); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_IMU) && SL_BOARD_ENABLE_SENSOR_IMU + sl_board_enable_sensor(SL_BOARD_SENSOR_IMU); +#endif +#if defined(SL_BOARD_ENABLE_SENSOR_MICROPHONE) && SL_BOARD_ENABLE_SENSOR_MICROPHONE + sl_board_enable_sensor(SL_BOARD_SENSOR_MICROPHONE); +#endif + +#if defined(SL_BOARD_ENABLE_DISPLAY) && SL_BOARD_ENABLE_DISPLAY + sl_board_enable_display(); +#endif + +#if defined(SL_BOARD_ENABLE_MEMORY_SDCARD) && SL_BOARD_ENABLE_MEMORY_SDCARD + sl_board_enable_memory(SL_BOARD_MEMORY_SDCARD); +#endif +#if defined(SL_BOARD_ENABLE_MEMORY_QSPI) && SL_BOARD_ENABLE_MEMORY_QSPI + sl_board_enable_memory(SL_BOARD_MEMORY_QSPI); +#endif + +#if (defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_USART_PRESENT) || defined(SL_CATALOG_MX25_FLASH_SHUTDOWN_EUSART_PRESENT)) && \ + defined(SL_BOARD_DISABLE_MEMORY_SPI) && SL_BOARD_DISABLE_MEMORY_SPI + sl_mx25_flash_shutdown(); +#endif +} + +void sl_board_preinit(void) +{ + CMU_ClockEnable(cmuClock_GPIO, true); + +#if defined(SL_BOARD_ENABLE_OSCILLATOR_TCXO) && SL_BOARD_ENABLE_OSCILLATOR_TCXO + sl_board_enable_oscillator(SL_BOARD_OSCILLATOR_TCXO); +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h index 0818ff1..06f9d9c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/inc/sl_cos.h @@ -1,147 +1,147 @@ -/***************************************************************************//** - * @file - * @brief Configuration Over SWO Component. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_COS_H -#define SL_COS_H - -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup cos Configuration Over SWO - * @brief Configuration Over SWO - * @details - * ## Overview - * - * When working with VCOM and/or PTI with a Silicon Labs kit (WSTK or WPK), - * it's important that the configuration of the kit's board controller - * matches that of the target application. - * The Configuration Over SWO component provides a way to automatically - * configure the board controller to use the same settings for VCOM and - * PTI configuration is sent to the board controller over SWO at startup, - * ensuring that the configuration is synchronized. - * @{ - ******************************************************************************/ - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ -#if defined (SL_CATALOG_UARTDRV_USART_PRESENT) || defined (SL_CATALOG_UARTDRV_EUSART_PRESENT) -#define SLI_COS_UARTDRV_VCOM_PRESENT -#endif // SL_CATALOG_UARTDRV_USART_PRESENT || SL_CATALOG_UARTDRV_EUSART_PRESENT - -#define COS_CONFIG_FLOWCONTROL_NONE 0 -#define COS_CONFIG_FLOWCONTROL_CTS 1 -#define COS_CONFIG_FLOWCONTROL_RTS 2 -#define COS_CONFIG_FLOWCONTROL_CTS_RTS 3 -/// @endcond - -// ----------------------------------------------------------------------------- -// Data Types - -/// @brief Enumeration representing the PTI Modes -SL_ENUM(COS_PtiMode_t) { - /** ONEWIRE mode. */ - COS_CONFIG_PTI_MODE_ONEWIRE, - /** TWOWIRE mode. */ - COS_CONFIG_PTI_MODE_TWOWIRE, - /** UART mode. */ - COS_CONFIG_PTI_MODE_EFRUART, - /** SPI mode. */ - COS_CONFIG_PTI_MODE_EFRSPI, - /** Mode count. */ - COS_CONFIG_PTI_MODE_COUNT -}; - -/// @brief Enumeration representing the PTI Interfaces -SL_ENUM(COS_PtiInterface_t) { - /** PTI INTERFACE 0. */ - COS_CONFIG_PTI_INTERFACE_0, - /** PTI INTERFACE 1. */ - COS_CONFIG_PTI_INTERFACE_1, - /** Interface count. */ - COS_CONFIG_PTI_INTERFACE_COUNT -}; - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. - ******************************************************************************/ -void sl_cos_send_config(void); - - /***************************************************************************//** - * Custom API, to be used by other software component to write the - * structured VCOM data on SWO ITM channel 8 - * The following Custom API take Baud rate, Flow Control as an input that should be - * configured at the bit(0 to 23) and bit(30(CTS), 31(RTS)) of the structured VCOM - * data respectively so that WSTK identifies the baud rate and flow_control values - * and configure accordingly - * - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * - * @param[in] flow_control Flow Control value that has to be set over bit_30 and bit_31. - ******************************************************************************/ -void sl_cos_config_vcom(uint32_t baudrate, - uint8_t flow_control); - -/***************************************************************************//** - * Custom API, to be used by other software component to write the - * structured PTI data on SWO ITM channel 8 - * - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] mode COS_PtiMode_t to be used. - * ONEWIRE mode. - * TWOWIRE mode. - * UART mode. - * SPI mode. - * PTI Modes that has to be set over bit_27 to bit_29. - * @param[in] interface COS_PtiInterface_t to be used. - * PTI INTERFACE 0. - * PTI INTERFACE 1. - * Interface value that has to be set over bit_30 and bit_31. - * @return config - ******************************************************************************/ -void sl_cos_config_pti(uint32_t baudrate, - COS_PtiMode_t mode, - COS_PtiInterface_t interface); - -/** @} (end addtogroup cos) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_COS_H */ +/***************************************************************************//** + * @file + * @brief Configuration Over SWO Component. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COS_H +#define SL_COS_H + +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup cos Configuration Over SWO + * @brief Configuration Over SWO + * @details + * ## Overview + * + * When working with VCOM and/or PTI with a Silicon Labs kit (WSTK or WPK), + * it's important that the configuration of the kit's board controller + * matches that of the target application. + * The Configuration Over SWO component provides a way to automatically + * configure the board controller to use the same settings for VCOM and + * PTI configuration is sent to the board controller over SWO at startup, + * ensuring that the configuration is synchronized. + * @{ + ******************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#if defined (SL_CATALOG_UARTDRV_USART_PRESENT) || defined (SL_CATALOG_UARTDRV_EUSART_PRESENT) +#define SLI_COS_UARTDRV_VCOM_PRESENT +#endif // SL_CATALOG_UARTDRV_USART_PRESENT || SL_CATALOG_UARTDRV_EUSART_PRESENT + +#define COS_CONFIG_FLOWCONTROL_NONE 0 +#define COS_CONFIG_FLOWCONTROL_CTS 1 +#define COS_CONFIG_FLOWCONTROL_RTS 2 +#define COS_CONFIG_FLOWCONTROL_CTS_RTS 3 +/// @endcond + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Enumeration representing the PTI Modes +SL_ENUM(COS_PtiMode_t) { + /** ONEWIRE mode. */ + COS_CONFIG_PTI_MODE_ONEWIRE, + /** TWOWIRE mode. */ + COS_CONFIG_PTI_MODE_TWOWIRE, + /** UART mode. */ + COS_CONFIG_PTI_MODE_EFRUART, + /** SPI mode. */ + COS_CONFIG_PTI_MODE_EFRSPI, + /** Mode count. */ + COS_CONFIG_PTI_MODE_COUNT +}; + +/// @brief Enumeration representing the PTI Interfaces +SL_ENUM(COS_PtiInterface_t) { + /** PTI INTERFACE 0. */ + COS_CONFIG_PTI_INTERFACE_0, + /** PTI INTERFACE 1. */ + COS_CONFIG_PTI_INTERFACE_1, + /** Interface count. */ + COS_CONFIG_PTI_INTERFACE_COUNT +}; + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. + ******************************************************************************/ +void sl_cos_send_config(void); + + /***************************************************************************//** + * Custom API, to be used by other software component to write the + * structured VCOM data on SWO ITM channel 8 + * The following Custom API take Baud rate, Flow Control as an input that should be + * configured at the bit(0 to 23) and bit(30(CTS), 31(RTS)) of the structured VCOM + * data respectively so that WSTK identifies the baud rate and flow_control values + * and configure accordingly + * + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * + * @param[in] flow_control Flow Control value that has to be set over bit_30 and bit_31. + ******************************************************************************/ +void sl_cos_config_vcom(uint32_t baudrate, + uint8_t flow_control); + +/***************************************************************************//** + * Custom API, to be used by other software component to write the + * structured PTI data on SWO ITM channel 8 + * + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] mode COS_PtiMode_t to be used. + * ONEWIRE mode. + * TWOWIRE mode. + * UART mode. + * SPI mode. + * PTI Modes that has to be set over bit_27 to bit_29. + * @param[in] interface COS_PtiInterface_t to be used. + * PTI INTERFACE 0. + * PTI INTERFACE 1. + * Interface value that has to be set over bit_30 and bit_31. + * @return config + ******************************************************************************/ +void sl_cos_config_pti(uint32_t baudrate, + COS_PtiMode_t mode, + COS_PtiInterface_t interface); + +/** @} (end addtogroup cos) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_COS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c index 049a030..d301cf0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/configuration_over_swo/src/sl_cos.c @@ -1,370 +1,370 @@ -/***************************************************************************//** - * @file - * @brief Configuration Over SWO Component - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#include -#include -#include -#include "sl_cos.h" -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -#include "sl_uartdrv_instances.h" -#endif // SLI_COS_UARTDRV_VCOM_PRESENT -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -#include "sl_rail_util_pti_config.h" -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -#include "sl_status.h" -#include "sl_debug_swo.h" - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ -#if defined (__ICCARM__) -#define DCH_PACKED_STRUCT __packed struct -#elif defined (__clang__) || defined (__ARM_ARCH) -#define DCH_PACKED_STRUCT struct __attribute__ ((__packed__)) -#elif defined (__GNUC__) -#define DCH_PACKED_STRUCT struct __attribute__ ((gcc_struct, __packed__)) -#endif - -#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) -#define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) - -#define COS_CONFIG_OPTION_TYPE_NULL 0 -#define COS_CONFIG_OPTION_TYPE_UART 1 -#define COS_CONFIG_OPTION_TYPE_PTI 2 - -#define COS_CONFIG_BAUDRATE_POS 0 -#define COS_CONFIG_BAUDRATE_MASK 0x00FFFFFFLU - -#define COS_CONFIG_UART_STOPBITS_1 0 -#define COS_CONFIG_UART_STOPBITS_1_5 1 -#define COS_CONFIG_UART_STOPBITS_2 2 -#define COS_CONFIG_UART_STOPBITS_LAST COS_CONFIG_UART_STOPBITS_2 -#define COS_CONFIG_UART_STOPBITS_POS 24 -#define COS_CONFIG_UART_STOPBITS_MASK 0x03LU - -#define COS_CONFIG_UART_PARITY_NONE 0 -#define COS_CONFIG_UART_PARITY_EVEN 1 -#define COS_CONFIG_UART_PARITY_ODD 2 -#define COS_CONFIG_UART_PARITY_LAST COS_CONFIG_UART_PARITY_ODD -#define COS_CONFIG_UART_PARITY_POS 26 -#define COS_CONFIG_UART_PARITY_MASK 0x03LU - -#define COS_CONFIG_UART_MODE_UART 0 -#define COS_CONFIG_UART_MODE_SPISLAVE 1 -#define COS_CONFIG_UART_MODE_SPIMASTER 2 -#define COS_CONFIG_UART_MODE_LAST COS_CONFIG_UART_MODE_ENABLED -#define COS_CONFIG_UART_MODE_POS 28 -#define COS_CONFIG_UART_MODE_MASK 0x03LU - -#define COS_CONFIG_UART_CTS_DISABLED 0 -#define COS_CONFIG_UART_CTS_ENABLED 1 -#define COS_CONFIG_UART_CTS_LAST COS_CONFIG_UART_CTS_ENABLED -#define COS_CONFIG_UART_CTS_POS 30 -#define COS_CONFIG_UART_CTS_MASK 0x01LU - -#define COS_CONFIG_UART_RTS_DISABLED 0 -#define COS_CONFIG_UART_RTS_ENABLED 1 -#define COS_CONFIG_UART_RTS_LAST COS_CONFIG_UART_RTS_ENABLED -#define COS_CONFIG_UART_RTS_POS 31 -#define COS_CONFIG_UART_RTS_MASK 0x01LU -#define COS_CONFIG_UART_FC_POS 30 -#define COS_CONFIG_UART_FC_MASK 0x03LU - -#define COS_CONFIG_PTI_MODE_POS 27 -#define COS_CONFIG_PTI_MODE_MASK 0x07LU - -#define COS_CONFIG_PTI_INTERFACE_POS 30 -#define COS_CONFIG_PTI_INTERFACE_MASK 0x03LU - -// SWO message type for COS -#define EM_COS_PACKET 0X0080LU - -// MACRO for SWO channel 8 -#define SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL 8U - -/******************************************************************************* - ****************************** VARIABLES ********************************** - ******************************************************************************/ - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static UARTDRV_Handle_t uartdrv_handle = NULL; -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -/***************************************************************************//** - * Structure to store the COS Config Options - ******************************************************************************/ -typedef DCH_PACKED_STRUCT __COS_ConfigOption { - uint8_t optionType; ///< option type - uint8_t reserved1; ///< reserved one - uint16_t reserved2; ///< reserved two - uint32_t optionValue; ///< option value -} COS_ConfigOption_t; - -/******************************************************************************* - ********************* LOCAL FUNCTION PROTOTYPES *************************** - ******************************************************************************/ - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static uint32_t sli_cos_vcom_config(uint32_t baudrate, uint8_t flow_control); -static void sli_cos_vcom_write(void); -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -static uint32_t sli_cos_pti_config(uint32_t baudrate, RAIL_PtiMode_t mode, uint8_t interface); -static void sli_cos_pti_write(void); -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, - size_t buffer_length); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. - ******************************************************************************/ -void sl_cos_send_config(void) -{ - // Configure SWO stimulus 8 - sl_debug_swo_enable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); - -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) - sli_cos_vcom_write(); -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) - // If RAIL PTI MODE is RAIL_PTI_MODE_DISABLED, then don't initiate sli_cos_pti_write(). - if (SL_RAIL_UTIL_PTI_MODE != RAIL_PTI_MODE_DISABLED) { - sli_cos_pti_write(); - } -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - - // Disable SWO stimulus 8 - sl_debug_swo_disable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); - - return; -} - -/***************************************************************************//** - * Pack the BaudRate, flow control value of VCOM into a 32 bit integer - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] flow_control Flow control that has to be set over bit_30 and bit_31. - * return uint32_t result - ******************************************************************************/ -static uint32_t sli_cos_vcom_config(uint32_t baudrate, - uint8_t flow_control) -{ - uint32_t config = 0; - - // Packing baudrate, and flow control info to config. - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((flow_control) & (COS_CONFIG_UART_FC_MASK)) << COS_CONFIG_UART_FC_POS); - - return config; -} - -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -/***************************************************************************//** - * Pack the BaudRate and mode value of PTI into a 32 bit integer - * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. - * @param[in] mode RAIL_PtiMode_t to be used. - * RAIL_PTI_MODE_DISABLED; Turn PTI off entirely. - * RAIL_PTI_MODE_SPI; SPI mode. - * RAIL_PTI_MODE_UART; UART mode. - * RAIL_PTI_MODE_UART_ONEWIRE; 9-bit UART mode. - * PTI Modes that has to be set over bit_27 to bit_29. - * @param[in] interface Interface value that has to be set over bit_30 and bit_31. - * return uint32_t config - ******************************************************************************/ -static uint32_t sli_cos_pti_config(uint32_t baudrate, - RAIL_PtiMode_t mode, uint8_t interface) -{ - uint32_t config = 0; - COS_PtiMode_t mode_Val = COS_CONFIG_PTI_MODE_EFRUART; - - // Mapping received Rail PTI Mode to COS PTI Mode - if (RAIL_PTI_MODE_SPI == mode) { - mode_Val = COS_CONFIG_PTI_MODE_EFRSPI; - } - - // Packing baudrate, mode and interface info to config. - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((mode_Val) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); - config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); - - return config; -} -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -/***************************************************************************//** - * Write the structured VCOM data on SWO ITM channel 8. - ******************************************************************************/ -#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) -static void sli_cos_vcom_write(void) -{ - COS_ConfigOption_t Cos_Uart_Config; - uartdrv_handle = sl_uartdrv_get_default(); - uint32_t baudrate = 0; - - Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; - -#ifdef SL_CATALOG_UARTDRV_EUSART_PRESENT - if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeEuart) { - baudrate = EUSART_BaudrateGet(uartdrv_handle->peripheral.euart); - } -#endif // SL_CATALOG_UARTDRV_EUSART_PRESENT - -#ifdef SL_CATALOG_UARTDRV_USART_PRESENT - if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeUart) { - baudrate = USART_BaudrateGet(uartdrv_handle->peripheral.uart); - } -#endif // SL_CATALOG_UARTDRV_USART_PRESENT - - Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, uartdrv_handle->fcType); - - sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); -} -#endif // SLI_COS_UARTDRV_VCOM_PRESENT - -/***************************************************************************//** - * Write the structured PTI data on SWO ITM channel 8. - ******************************************************************************/ -#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) -static void sli_cos_pti_write(void) -{ - COS_ConfigOption_t Cos_Pti_Config; - - Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; - Cos_Pti_Config.optionValue = sli_cos_pti_config(SL_RAIL_UTIL_PTI_BAUD_RATE_HZ, SL_RAIL_UTIL_PTI_MODE, COS_CONFIG_PTI_INTERFACE_0); - - sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); -} -#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT - -/***************************************************************************//** - * Custom API which can be used by other software component, to write the - * structured PTI data on SWO ITM channel 8. - ******************************************************************************/ -void sl_cos_config_pti(uint32_t baudrate, - COS_PtiMode_t mode, - COS_PtiInterface_t interface) -{ - COS_ConfigOption_t Cos_Pti_Config; - uint32_t config = 0; - - Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; - - // Packing baudrate, mode and interface info to config - config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); - config |= (((mode) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); - config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); - - Cos_Pti_Config.optionValue = config; - - sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); -} - -/***************************************************************************//** - * Custom API which can be used by other software component, to write the - * structured VCOM data on SWO ITM channel 8. - ******************************************************************************/ -void sl_cos_config_vcom(uint32_t baudrate, - uint8_t flow_control) -{ - COS_ConfigOption_t Cos_Uart_Config; - - Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; - Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, flow_control); - - sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); -} - -/***************************************************************************//** - * Write data on SWO interface (WSTK-port 4900) - ******************************************************************************/ -static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, - size_t buffer_length) -{ - uint8_t *buf = (uint8_t *)buffer; - uint32_t packet_length; - uint32_t i; - uint8_t output_byte; - uint8_t seq_nbr = 0; - - // Full length is 2 square braces, 1 byte length and 2 byte CRC - packet_length = ( (uint32_t)buffer_length) + 9; - - // The write feature is built upon the existing Ember Debug Message (EDM) protocol, which today is transmitted over SWO UART on ITM Channel 8. - // The Protocol have the Start-byte, Length, Version, Message type, Sequence number, Message, CRC CCITT-16, and End-byte for correct communication. - for ( i = 0; i < packet_length; ++i ) { - if ( i == 0 ) { - // Frame start - output_byte = '['; - } else if ( i == 1 ) { - // Including special byte, type and sequence number - output_byte = buffer_length + 4; - } else if ( i == 2 ) { - // Special EDM byte - output_byte = 0xD1; - } else if ( i == 3 ) { - // COS Type byte 1 - output_byte = LOW_BYTE((uint16_t)(EM_COS_PACKET)); - } else if ( i == 4 ) { - // COS Type byte 2 - output_byte = HIGH_BYTE((uint16_t)(EM_COS_PACKET)); - } else if ( i == 5 ) { - // Sequence number - output_byte = seq_nbr++; - } else if ( i == (packet_length - 3) ) { - // CRC first byte - // Ignored by FW - so we also skip it - output_byte = 0x5A; - } else if ( i == (packet_length - 2) ) { - // CRC second byte - // Ignored by FW - so we also skip it - output_byte = 0x5A; - } else if ( i == (packet_length - 1) ) { - // Frame end - output_byte = ']'; - } else { - // Data - output_byte = buf[i - 6]; - } - - sl_debug_swo_write(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL, output_byte); - } - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Configuration Over SWO Component + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include +#include +#include +#include "sl_cos.h" +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +#include "sl_uartdrv_instances.h" +#endif // SLI_COS_UARTDRV_VCOM_PRESENT +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +#include "sl_rail_util_pti_config.h" +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +#include "sl_status.h" +#include "sl_debug_swo.h" + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ +#if defined (__ICCARM__) +#define DCH_PACKED_STRUCT __packed struct +#elif defined (__clang__) || defined (__ARM_ARCH) +#define DCH_PACKED_STRUCT struct __attribute__ ((__packed__)) +#elif defined (__GNUC__) +#define DCH_PACKED_STRUCT struct __attribute__ ((gcc_struct, __packed__)) +#endif + +#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) +#define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) + +#define COS_CONFIG_OPTION_TYPE_NULL 0 +#define COS_CONFIG_OPTION_TYPE_UART 1 +#define COS_CONFIG_OPTION_TYPE_PTI 2 + +#define COS_CONFIG_BAUDRATE_POS 0 +#define COS_CONFIG_BAUDRATE_MASK 0x00FFFFFFLU + +#define COS_CONFIG_UART_STOPBITS_1 0 +#define COS_CONFIG_UART_STOPBITS_1_5 1 +#define COS_CONFIG_UART_STOPBITS_2 2 +#define COS_CONFIG_UART_STOPBITS_LAST COS_CONFIG_UART_STOPBITS_2 +#define COS_CONFIG_UART_STOPBITS_POS 24 +#define COS_CONFIG_UART_STOPBITS_MASK 0x03LU + +#define COS_CONFIG_UART_PARITY_NONE 0 +#define COS_CONFIG_UART_PARITY_EVEN 1 +#define COS_CONFIG_UART_PARITY_ODD 2 +#define COS_CONFIG_UART_PARITY_LAST COS_CONFIG_UART_PARITY_ODD +#define COS_CONFIG_UART_PARITY_POS 26 +#define COS_CONFIG_UART_PARITY_MASK 0x03LU + +#define COS_CONFIG_UART_MODE_UART 0 +#define COS_CONFIG_UART_MODE_SPISLAVE 1 +#define COS_CONFIG_UART_MODE_SPIMASTER 2 +#define COS_CONFIG_UART_MODE_LAST COS_CONFIG_UART_MODE_ENABLED +#define COS_CONFIG_UART_MODE_POS 28 +#define COS_CONFIG_UART_MODE_MASK 0x03LU + +#define COS_CONFIG_UART_CTS_DISABLED 0 +#define COS_CONFIG_UART_CTS_ENABLED 1 +#define COS_CONFIG_UART_CTS_LAST COS_CONFIG_UART_CTS_ENABLED +#define COS_CONFIG_UART_CTS_POS 30 +#define COS_CONFIG_UART_CTS_MASK 0x01LU + +#define COS_CONFIG_UART_RTS_DISABLED 0 +#define COS_CONFIG_UART_RTS_ENABLED 1 +#define COS_CONFIG_UART_RTS_LAST COS_CONFIG_UART_RTS_ENABLED +#define COS_CONFIG_UART_RTS_POS 31 +#define COS_CONFIG_UART_RTS_MASK 0x01LU +#define COS_CONFIG_UART_FC_POS 30 +#define COS_CONFIG_UART_FC_MASK 0x03LU + +#define COS_CONFIG_PTI_MODE_POS 27 +#define COS_CONFIG_PTI_MODE_MASK 0x07LU + +#define COS_CONFIG_PTI_INTERFACE_POS 30 +#define COS_CONFIG_PTI_INTERFACE_MASK 0x03LU + +// SWO message type for COS +#define EM_COS_PACKET 0X0080LU + +// MACRO for SWO channel 8 +#define SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL 8U + +/******************************************************************************* + ****************************** VARIABLES ********************************** + ******************************************************************************/ + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static UARTDRV_Handle_t uartdrv_handle = NULL; +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +/***************************************************************************//** + * Structure to store the COS Config Options + ******************************************************************************/ +typedef DCH_PACKED_STRUCT __COS_ConfigOption { + uint8_t optionType; ///< option type + uint8_t reserved1; ///< reserved one + uint16_t reserved2; ///< reserved two + uint32_t optionValue; ///< option value +} COS_ConfigOption_t; + +/******************************************************************************* + ********************* LOCAL FUNCTION PROTOTYPES *************************** + ******************************************************************************/ + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static uint32_t sli_cos_vcom_config(uint32_t baudrate, uint8_t flow_control); +static void sli_cos_vcom_write(void); +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +static uint32_t sli_cos_pti_config(uint32_t baudrate, RAIL_PtiMode_t mode, uint8_t interface); +static void sli_cos_pti_write(void); +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, + size_t buffer_length); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initialize the SWO ITM 8 and initiates VCOM/PTI SWO writes. + ******************************************************************************/ +void sl_cos_send_config(void) +{ + // Configure SWO stimulus 8 + sl_debug_swo_enable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); + +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) + sli_cos_vcom_write(); +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) + // If RAIL PTI MODE is RAIL_PTI_MODE_DISABLED, then don't initiate sli_cos_pti_write(). + if (SL_RAIL_UTIL_PTI_MODE != RAIL_PTI_MODE_DISABLED) { + sli_cos_pti_write(); + } +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + + // Disable SWO stimulus 8 + sl_debug_swo_disable_itm(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL); + + return; +} + +/***************************************************************************//** + * Pack the BaudRate, flow control value of VCOM into a 32 bit integer + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] flow_control Flow control that has to be set over bit_30 and bit_31. + * return uint32_t result + ******************************************************************************/ +static uint32_t sli_cos_vcom_config(uint32_t baudrate, + uint8_t flow_control) +{ + uint32_t config = 0; + + // Packing baudrate, and flow control info to config. + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((flow_control) & (COS_CONFIG_UART_FC_MASK)) << COS_CONFIG_UART_FC_POS); + + return config; +} + +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +/***************************************************************************//** + * Pack the BaudRate and mode value of PTI into a 32 bit integer + * @param[in] BaudRate Baud rate that has to be set over bit_0 to bit_23. + * @param[in] mode RAIL_PtiMode_t to be used. + * RAIL_PTI_MODE_DISABLED; Turn PTI off entirely. + * RAIL_PTI_MODE_SPI; SPI mode. + * RAIL_PTI_MODE_UART; UART mode. + * RAIL_PTI_MODE_UART_ONEWIRE; 9-bit UART mode. + * PTI Modes that has to be set over bit_27 to bit_29. + * @param[in] interface Interface value that has to be set over bit_30 and bit_31. + * return uint32_t config + ******************************************************************************/ +static uint32_t sli_cos_pti_config(uint32_t baudrate, + RAIL_PtiMode_t mode, uint8_t interface) +{ + uint32_t config = 0; + COS_PtiMode_t mode_Val = COS_CONFIG_PTI_MODE_EFRUART; + + // Mapping received Rail PTI Mode to COS PTI Mode + if (RAIL_PTI_MODE_SPI == mode) { + mode_Val = COS_CONFIG_PTI_MODE_EFRSPI; + } + + // Packing baudrate, mode and interface info to config. + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((mode_Val) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); + config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); + + return config; +} +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +/***************************************************************************//** + * Write the structured VCOM data on SWO ITM channel 8. + ******************************************************************************/ +#if defined (SLI_COS_UARTDRV_VCOM_PRESENT) +static void sli_cos_vcom_write(void) +{ + COS_ConfigOption_t Cos_Uart_Config; + uartdrv_handle = sl_uartdrv_get_default(); + uint32_t baudrate = 0; + + Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; + +#ifdef SL_CATALOG_UARTDRV_EUSART_PRESENT + if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeEuart) { + baudrate = EUSART_BaudrateGet(uartdrv_handle->peripheral.euart); + } +#endif // SL_CATALOG_UARTDRV_EUSART_PRESENT + +#ifdef SL_CATALOG_UARTDRV_USART_PRESENT + if (uartdrv_handle->type == (UARTDRV_UartType_t)uartdrvUartTypeUart) { + baudrate = USART_BaudrateGet(uartdrv_handle->peripheral.uart); + } +#endif // SL_CATALOG_UARTDRV_USART_PRESENT + + Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, uartdrv_handle->fcType); + + sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); +} +#endif // SLI_COS_UARTDRV_VCOM_PRESENT + +/***************************************************************************//** + * Write the structured PTI data on SWO ITM channel 8. + ******************************************************************************/ +#if defined (SL_CATALOG_RAIL_UTIL_PTI_PRESENT) +static void sli_cos_pti_write(void) +{ + COS_ConfigOption_t Cos_Pti_Config; + + Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; + Cos_Pti_Config.optionValue = sli_cos_pti_config(SL_RAIL_UTIL_PTI_BAUD_RATE_HZ, SL_RAIL_UTIL_PTI_MODE, COS_CONFIG_PTI_INTERFACE_0); + + sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); +} +#endif // SL_CATALOG_RAIL_UTIL_PTI_PRESENT + +/***************************************************************************//** + * Custom API which can be used by other software component, to write the + * structured PTI data on SWO ITM channel 8. + ******************************************************************************/ +void sl_cos_config_pti(uint32_t baudrate, + COS_PtiMode_t mode, + COS_PtiInterface_t interface) +{ + COS_ConfigOption_t Cos_Pti_Config; + uint32_t config = 0; + + Cos_Pti_Config.optionType = COS_CONFIG_OPTION_TYPE_PTI; + + // Packing baudrate, mode and interface info to config + config |= (((baudrate) & (COS_CONFIG_BAUDRATE_MASK)) << COS_CONFIG_BAUDRATE_POS); + config |= (((mode) & (COS_CONFIG_PTI_MODE_MASK)) << COS_CONFIG_PTI_MODE_POS); + config |= (((interface) & (COS_CONFIG_PTI_INTERFACE_MASK)) << COS_CONFIG_PTI_INTERFACE_POS); + + Cos_Pti_Config.optionValue = config; + + sli_cos_swo_itm_8_write(&Cos_Pti_Config, sizeof(Cos_Pti_Config)); +} + +/***************************************************************************//** + * Custom API which can be used by other software component, to write the + * structured VCOM data on SWO ITM channel 8. + ******************************************************************************/ +void sl_cos_config_vcom(uint32_t baudrate, + uint8_t flow_control) +{ + COS_ConfigOption_t Cos_Uart_Config; + + Cos_Uart_Config.optionType = COS_CONFIG_OPTION_TYPE_UART; + Cos_Uart_Config.optionValue = sli_cos_vcom_config(baudrate, flow_control); + + sli_cos_swo_itm_8_write(&Cos_Uart_Config, sizeof(Cos_Uart_Config)); +} + +/***************************************************************************//** + * Write data on SWO interface (WSTK-port 4900) + ******************************************************************************/ +static sl_status_t sli_cos_swo_itm_8_write(const void *buffer, + size_t buffer_length) +{ + uint8_t *buf = (uint8_t *)buffer; + uint32_t packet_length; + uint32_t i; + uint8_t output_byte; + uint8_t seq_nbr = 0; + + // Full length is 2 square braces, 1 byte length and 2 byte CRC + packet_length = ( (uint32_t)buffer_length) + 9; + + // The write feature is built upon the existing Ember Debug Message (EDM) protocol, which today is transmitted over SWO UART on ITM Channel 8. + // The Protocol have the Start-byte, Length, Version, Message type, Sequence number, Message, CRC CCITT-16, and End-byte for correct communication. + for ( i = 0; i < packet_length; ++i ) { + if ( i == 0 ) { + // Frame start + output_byte = '['; + } else if ( i == 1 ) { + // Including special byte, type and sequence number + output_byte = buffer_length + 4; + } else if ( i == 2 ) { + // Special EDM byte + output_byte = 0xD1; + } else if ( i == 3 ) { + // COS Type byte 1 + output_byte = LOW_BYTE((uint16_t)(EM_COS_PACKET)); + } else if ( i == 4 ) { + // COS Type byte 2 + output_byte = HIGH_BYTE((uint16_t)(EM_COS_PACKET)); + } else if ( i == 5 ) { + // Sequence number + output_byte = seq_nbr++; + } else if ( i == (packet_length - 3) ) { + // CRC first byte + // Ignored by FW - so we also skip it + output_byte = 0x5A; + } else if ( i == (packet_length - 2) ) { + // CRC second byte + // Ignored by FW - so we also skip it + output_byte = 0x5A; + } else if ( i == (packet_length - 1) ) { + // Frame end + output_byte = ']'; + } else { + // Data + output_byte = buf[i - 6]; + } + + sl_debug_swo_write(SWO_VCOM_PTI_DATA_STRUCTURED_CHANNEL, output_byte); + } + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h index 7dd0da5..c471eff 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.h @@ -1,65 +1,65 @@ -/***************************************************************************//** - * @file - * @brief MX25 flash shutdown - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_MX25_FLASH_SHUTDOWN_H -#define SL_MX25_FLASH_SHUTDOWN_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "em_device.h" -#include "sl_mx25_flash_shutdown_usart_config.h" - -/***************************************************************************//** - * @addtogroup mx25_flash_shutdown MX25 SPI Flash Shutdown - * @brief Provide a function to put the MX25 SPI flash into deep power down - * mode to reduce power consumption. - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Put the MX25 SPI flash into deep power down mode. - * - * This function initializes SPI communication with the MX25 flash and sends - * the deep power-down instruction, which sets the device to minimal - * power consumption. The SPI communication is disabled to free the USART. - ******************************************************************************/ -void sl_mx25_flash_shutdown(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif // SL_MX25_FLASH_SHUTDOWN_H +/***************************************************************************//** + * @file + * @brief MX25 flash shutdown + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_MX25_FLASH_SHUTDOWN_H +#define SL_MX25_FLASH_SHUTDOWN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "em_device.h" +#include "sl_mx25_flash_shutdown_usart_config.h" + +/***************************************************************************//** + * @addtogroup mx25_flash_shutdown MX25 SPI Flash Shutdown + * @brief Provide a function to put the MX25 SPI flash into deep power down + * mode to reduce power consumption. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Put the MX25 SPI flash into deep power down mode. + * + * This function initializes SPI communication with the MX25 flash and sends + * the deep power-down instruction, which sets the device to minimal + * power consumption. The SPI communication is disabled to free the USART. + ******************************************************************************/ +void sl_mx25_flash_shutdown(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif // SL_MX25_FLASH_SHUTDOWN_H diff --git a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c index 6eec5a9..42ad519 100644 --- a/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c +++ b/locator_ncp/gecko_sdk_4.4.1/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c @@ -1,141 +1,141 @@ -/***************************************************************************//** - * @file - * @brief MX25 flash shutdown - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_cmu.h" -#include "em_usart.h" -#include "em_gpio.h" -#include "sl_udelay.h" -#include "sl_mx25_flash_shutdown.h" - -// Fallback to baudrate of 8 MHz if not defined for backwards compatibility -#ifndef SL_MX25_FLASH_SHUTDOWN_BAUDRATE -#define SL_MX25_FLASH_SHUTDOWN_BAUDRATE 8000000 -#endif - -// Define usart clock -#ifndef SL_MX25_FLASH_SHUTDOWN_CLK -#define MERGE(x, y) x##y -#define USART_CLOCK(n) MERGE(cmuClock_USART, n) -#define SL_MX25_FLASH_SHUTDOWN_CLK USART_CLOCK(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO) -#endif - -#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL -static void cs_low(void) -{ - GPIO_PinOutClear(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); -} - -static void cs_high(void) -{ - GPIO_PinOutSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); -} -#endif - -/***************************************************************************//** - * Puts the MX25 into deep power down mode. - ******************************************************************************/ -void sl_mx25_flash_shutdown(void) -{ -#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL - // Init flash - USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; - - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, true); - - init.msbf = true; - init.baudrate = SL_MX25_FLASH_SHUTDOWN_BAUDRATE; - - USART_InitSync(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init); - - // IO config - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeInput, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModePushPull, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModePushPull, 1); - -#ifdef _GPIO_USART_ROUTEEN_MASK - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = ((SL_MX25_FLASH_SHUTDOWN_CLK_PORT << _GPIO_USART_CLKROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_CLK_PIN << _GPIO_USART_CLKROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = ((SL_MX25_FLASH_SHUTDOWN_RX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = ((SL_MX25_FLASH_SHUTDOWN_TX_PORT << _GPIO_USART_TXROUTE_PORT_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_TX_PIN << _GPIO_USART_TXROUTE_PIN_SHIFT)); - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = (GPIO_USART_ROUTEEN_RXPEN - | GPIO_USART_ROUTEEN_TXPEN - | GPIO_USART_ROUTEEN_CLKPEN); -#else - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = ((SL_MX25_FLASH_SHUTDOWN_RX_LOC << _USART_ROUTELOC0_RXLOC_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_TX_LOC << _USART_ROUTELOC0_TXLOC_SHIFT) - | (SL_MX25_FLASH_SHUTDOWN_CLK_LOC << _USART_ROUTELOC0_CLKLOC_SHIFT)); - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = (USART_ROUTEPEN_RXPEN - | USART_ROUTEPEN_TXPEN - | USART_ROUTEPEN_CLKPEN); -#endif - - // Wait for flash warm-up - sl_udelay_wait(800); // wait for tVSL=800us - - // Wake up flash in case the device is in deep power down mode already. - cs_low(); - sl_udelay_wait(20); // wait for tCRDP=20us - cs_high(); - sl_udelay_wait(35); // wait for tRDP=35us - - // Chip select go low to start a flash command - cs_low(); - - // Deep Power Down Mode command (0xB9) - USART_SpiTransfer(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9); - - // Chip select go high to end a flash command - cs_high(); - - // Deinit flash - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModeDisabled, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeDisabled, 0); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModeDisabled, 1); - GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModeDisabled, 1); - - USART_Reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL); - -#ifdef _GPIO_USART_ROUTEEN_MASK - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; - GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; -#else - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; - SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; -#endif - - CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, false); -#endif -} +/***************************************************************************//** + * @file + * @brief MX25 flash shutdown + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_cmu.h" +#include "em_usart.h" +#include "em_gpio.h" +#include "sl_udelay.h" +#include "sl_mx25_flash_shutdown.h" + +// Fallback to baudrate of 8 MHz if not defined for backwards compatibility +#ifndef SL_MX25_FLASH_SHUTDOWN_BAUDRATE +#define SL_MX25_FLASH_SHUTDOWN_BAUDRATE 8000000 +#endif + +// Define usart clock +#ifndef SL_MX25_FLASH_SHUTDOWN_CLK +#define MERGE(x, y) x##y +#define USART_CLOCK(n) MERGE(cmuClock_USART, n) +#define SL_MX25_FLASH_SHUTDOWN_CLK USART_CLOCK(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO) +#endif + +#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL +static void cs_low(void) +{ + GPIO_PinOutClear(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); +} + +static void cs_high(void) +{ + GPIO_PinOutSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN); +} +#endif + +/***************************************************************************//** + * Puts the MX25 into deep power down mode. + ******************************************************************************/ +void sl_mx25_flash_shutdown(void) +{ +#ifdef SL_MX25_FLASH_SHUTDOWN_PERIPHERAL + // Init flash + USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT; + + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, true); + + init.msbf = true; + init.baudrate = SL_MX25_FLASH_SHUTDOWN_BAUDRATE; + + USART_InitSync(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, &init); + + // IO config + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModePushPull, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeInput, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModePushPull, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModePushPull, 1); + +#ifdef _GPIO_USART_ROUTEEN_MASK + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = ((SL_MX25_FLASH_SHUTDOWN_CLK_PORT << _GPIO_USART_CLKROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_CLK_PIN << _GPIO_USART_CLKROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = ((SL_MX25_FLASH_SHUTDOWN_RX_PORT << _GPIO_USART_RXROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_RX_PIN << _GPIO_USART_RXROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = ((SL_MX25_FLASH_SHUTDOWN_TX_PORT << _GPIO_USART_TXROUTE_PORT_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_TX_PIN << _GPIO_USART_TXROUTE_PIN_SHIFT)); + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = (GPIO_USART_ROUTEEN_RXPEN + | GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_CLKPEN); +#else + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = ((SL_MX25_FLASH_SHUTDOWN_RX_LOC << _USART_ROUTELOC0_RXLOC_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_TX_LOC << _USART_ROUTELOC0_TXLOC_SHIFT) + | (SL_MX25_FLASH_SHUTDOWN_CLK_LOC << _USART_ROUTELOC0_CLKLOC_SHIFT)); + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = (USART_ROUTEPEN_RXPEN + | USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_CLKPEN); +#endif + + // Wait for flash warm-up + sl_udelay_wait(800); // wait for tVSL=800us + + // Wake up flash in case the device is in deep power down mode already. + cs_low(); + sl_udelay_wait(20); // wait for tCRDP=20us + cs_high(); + sl_udelay_wait(35); // wait for tRDP=35us + + // Chip select go low to start a flash command + cs_low(); + + // Deep Power Down Mode command (0xB9) + USART_SpiTransfer(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL, 0xB9); + + // Chip select go high to end a flash command + cs_high(); + + // Deinit flash + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_TX_PORT, SL_MX25_FLASH_SHUTDOWN_TX_PIN, gpioModeDisabled, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_RX_PORT, SL_MX25_FLASH_SHUTDOWN_RX_PIN, gpioModeDisabled, 0); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CLK_PORT, SL_MX25_FLASH_SHUTDOWN_CLK_PIN, gpioModeDisabled, 1); + GPIO_PinModeSet(SL_MX25_FLASH_SHUTDOWN_CS_PORT, SL_MX25_FLASH_SHUTDOWN_CS_PIN, gpioModeDisabled, 1); + + USART_Reset(SL_MX25_FLASH_SHUTDOWN_PERIPHERAL); + +#ifdef _GPIO_USART_ROUTEEN_MASK + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].CLKROUTE = _GPIO_USART_CLKROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].RXROUTE = _GPIO_USART_RXROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].TXROUTE = _GPIO_USART_TXROUTE_RESETVALUE; + GPIO->USARTROUTE[SL_MX25_FLASH_SHUTDOWN_PERIPHERAL_NO].ROUTEEN = _GPIO_USART_ROUTEEN_RESETVALUE; +#else + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + SL_MX25_FLASH_SHUTDOWN_PERIPHERAL->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; +#endif + + CMU_ClockEnable(SL_MX25_FLASH_SHUTDOWN_CLK, false); +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h index adbf296..21a2c71 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_compiler.h @@ -1,283 +1,283 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h index 67bda4e..045aaf1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_gcc.h @@ -1,2211 +1,2211 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h index 2f048e4..a196dfd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/cmsis_version.h @@ -1,39 +1,39 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.4 - * @date 23. July 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h index f9cf6ab..4dbde81 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/core_cm33.h @@ -1,3265 +1,3265 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h index 3de16ef..b6ff9a9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/mpu_armv8.h @@ -1,352 +1,352 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h index 0d09749..d4c1474 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/CMSIS/Core/Include/tz_context.h @@ -1,70 +1,70 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h index 9fc611f..ae625fc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_aes.h @@ -1,453 +1,453 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 AES register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_AES_H -#define EFR32BG22_AES_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_AES AES - * @{ - * @brief EFR32BG22 AES Register Declaration. - *****************************************************************************/ - -/** AES Register Declaration. */ -typedef struct { - __IOM uint32_t FETCHADDR; /**< Fetcher Address */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t FETCHLEN; /**< Fetcher Length */ - __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ - __IOM uint32_t PUSHADDR; /**< Pusher Address */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t PUSHLEN; /**< Pusher Length */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IM uint32_t IF; /**< Interrupt Flags */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt status clear */ - __IOM uint32_t CTRL; /**< Control register */ - __IOM uint32_t CMD; /**< Command register */ - __IM uint32_t STATUS; /**< Status register */ - uint32_t RESERVED4[240U]; /**< Reserved for future use */ - __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ - __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ - __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ - __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ - __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ - __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ -} AES_TypeDef; -/** @} End of group EFR32BG22_AES */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_AES - * @{ - * @defgroup EFR32BG22_AES_BitFields AES Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for AES FETCHADDR */ -#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ -#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ -#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ -#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ - -/* Bit fields for AES FETCHLEN */ -#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ -#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ -#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ -#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ -#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ - -/* Bit fields for AES FETCHTAG */ -#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ -#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ -#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ -#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ -#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ -#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ - -/* Bit fields for AES PUSHADDR */ -#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ -#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ -#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ -#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ -#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ - -/* Bit fields for AES PUSHLEN */ -#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ -#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ -#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ -#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ -#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ -#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ -#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ -#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ -#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ - -/* Bit fields for AES IEN */ -#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ -#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ -#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ -#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ -#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ -#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ -#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ -#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ -#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ - -/* Bit fields for AES IF */ -#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ -#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ -#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ -#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ -#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ -#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ -#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ -#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ -#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ - -/* Bit fields for AES IF_CLR */ -#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ -#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ -#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ -#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ -#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ -#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ -#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ -#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ -#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ -#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ -#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ -#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ -#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ - -/* Bit fields for AES CTRL */ -#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ -#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ -#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ -#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ -#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ -#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ -#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ -#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ -#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ -#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ -#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ -#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ -#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ -#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ - -/* Bit fields for AES CMD */ -#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ -#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ -#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ -#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ -#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ -#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ -#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ -#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ - -/* Bit fields for AES STATUS */ -#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ -#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ -#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ -#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ -#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ -#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ -#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ -#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ -#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ -#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ -#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ -#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ -#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ -#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ -#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ -#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ -#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ - -/* Bit fields for AES INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ -#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ -#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ -#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ -#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ - -/* Bit fields for AES BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ -#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ -#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ -#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ -#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ -#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ -#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ -#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ - -/* Bit fields for AES BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ -#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ -#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ - -/* Bit fields for AES BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ -#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ -#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ -#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ -#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ -#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ -#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ - -/* Bit fields for AES BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ -#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ -#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ -#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ - -/* Bit fields for AES BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ -#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ -#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ - -/** @} End of group EFR32BG22_AES_BitFields */ -/** @} End of group EFR32BG22_AES */ -/** @} End of group Parts */ - -#endif // EFR32BG22_AES_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 AES register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_AES_H +#define EFR32BG22_AES_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_AES AES + * @{ + * @brief EFR32BG22 AES Register Declaration. + *****************************************************************************/ + +/** AES Register Declaration. */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< INCL_IPS_HW_CFG */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E_HW_CFG_1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E_HW_CFG_2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413_HW_CFG */ + __IM uint32_t BA418_HW_CFG; /**< BA418_HW_CFG */ + __IM uint32_t BA419_HW_CFG; /**< BA419_HW_CFG */ +} AES_TypeDef; +/** @} End of group EFR32BG22_AES */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_AES + * @{ + * @defgroup EFR32BG22_AES_BitFields AES Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for AES FETCHADDR */ +#define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ +#define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ +#define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ +#define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ + +/* Bit fields for AES FETCHLEN */ +#define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ +#define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ +#define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ +#define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ +#define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ + +/* Bit fields for AES FETCHTAG */ +#define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ +#define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ +#define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ +#define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ +#define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ +#define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ + +/* Bit fields for AES PUSHADDR */ +#define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ +#define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ +#define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ +#define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ +#define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ + +/* Bit fields for AES PUSHLEN */ +#define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ +#define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ +#define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ +#define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ +#define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ +#define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ +#define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ +#define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ + +/* Bit fields for AES IEN */ +#define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ +#define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ +#define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ + +/* Bit fields for AES IF */ +#define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ +#define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ +#define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ + +/* Bit fields for AES IF_CLR */ +#define _AES_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for AES_IF_CLR */ +#define _AES_IF_CLR_MASK 0x0000003FUL /**< Mask for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ +#define _AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _AES_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ +#define _AES_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERSTOPPED_DEFAULT (_AES_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _AES_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ +#define _AES_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_FETCHERERROR_DEFAULT (_AES_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< FETCHERENDOFBLOCKIFC */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ +#define _AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< FETCHERSTOPPEDIFC */ +#define _AES_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ +#define _AES_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERSTOPPED_DEFAULT (_AES_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR (0x1UL << 5) /**< FETCHERERRORIFC */ +#define _AES_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ +#define _AES_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF_CLR */ +#define AES_IF_CLR_PUSHERERROR_DEFAULT (_AES_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF_CLR */ + +/* Bit fields for AES CTRL */ +#define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ +#define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ +#define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ +#define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ +#define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ +#define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ +#define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ +#define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ +#define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ + +/* Bit fields for AES CMD */ +#define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ +#define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ +#define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ +#define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ +#define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ +#define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ + +/* Bit fields for AES STATUS */ +#define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ +#define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ +#define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ +#define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ +#define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ +#define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ +#define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ +#define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ +#define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ +#define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ +#define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ +#define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ + +/* Bit fields for AES INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_INCL_IPS_HW_CFG */ +#define _AES_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for AES_g_IncludeAES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for AES_g_IncludeAESGCM */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for AES_g_IncludeAESXTS */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for AES_g_IncludeDES */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for AES_g_IncludeHASH */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for AES_g_IncludeChachaPoly */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for AES_g_IncludeSHA3 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for AES_g_IncludeZUC */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for AES_g_IncludeSM4 */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for AES_g_IncludePKE */ +#define _AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for AES_g_IncludeNDRNG */ +#define _AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_INCL_IPS_HW_CFG */ +#define AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_AES_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for AES_INCL_IPS_HW_CFG*/ + +/* Bit fields for AES BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_RESETVALUE 0x05010127UL /**< Default value for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for AES_BA411E_HW_CFG_1 */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for AES_g_AesModesPoss */ +#define _AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x00000127UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_AES_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _AES_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for AES_g_CS */ +#define _AES_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_CS_DEFAULT (_AES_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define AES_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for AES_g_UseMasking */ +#define _AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_AES_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ +#define _AES_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for AES_g_Keysize */ +#define _AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000005UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_1 */ +#define AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_AES_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_1*/ + +/* Bit fields for AES BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for AES_BA411E_HW_CFG_2 */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for AES_g_CtrSize */ +#define _AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for AES_BA411E_HW_CFG_2 */ +#define AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_AES_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA411E_HW_CFG_2*/ + +/* Bit fields for AES BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for AES_BA413_HW_CFG */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for AES_g_HashMaskFunc */ +#define _AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_AES_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _AES_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for AES_g_HashPadding */ +#define _AES_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashPadding_DEFAULT (_AES_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for AES_g_HMAC_enabled */ +#define _AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_AES_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for AES_g_HashVerifyDigest */ +#define _AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA413_HW_CFG */ +#define AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_AES_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for AES_BA413_HW_CFG */ + +/* Bit fields for AES BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for AES_BA418_HW_CFG */ +#define _AES_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for AES_g_Sha3CtxtEn */ +#define _AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for AES_BA418_HW_CFG */ +#define AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_AES_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA418_HW_CFG */ + +/* Bit fields for AES BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_RESETVALUE 0x00000000UL /**< Default value for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for AES_BA419_HW_CFG */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for AES_g_SM4ModesPoss */ +#define _AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_BA419_HW_CFG */ +#define AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_AES_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_BA419_HW_CFG */ + +/** @} End of group EFR32BG22_AES_BitFields */ +/** @} End of group EFR32BG22_AES */ +/** @} End of group Parts */ + +#endif // EFR32BG22_AES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h index 1194ecf..6fe467a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_buram.h @@ -1,80 +1,80 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 BURAM register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_BURAM_H -#define EFR32BG22_BURAM_H -#define BURAM_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_BURAM BURAM - * @{ - * @brief EFR32BG22 BURAM Register Declaration. - *****************************************************************************/ - -/** BURAM RET Register Group Declaration. */ -typedef struct { - __IOM uint32_t REG; /**< Retention Register */ -} BURAM_RET_TypeDef; - -/** BURAM Register Declaration. */ -typedef struct { - BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ - uint32_t RESERVED0[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ - uint32_t RESERVED1[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ - uint32_t RESERVED2[992U]; /**< Reserved for future use */ - BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ -} BURAM_TypeDef; -/** @} End of group EFR32BG22_BURAM */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_BURAM - * @{ - * @defgroup EFR32BG22_BURAM_BitFields BURAM Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for BURAM RET_REG */ -#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ -#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ -#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ -#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ -#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ - -/** @} End of group EFR32BG22_BURAM_BitFields */ -/** @} End of group EFR32BG22_BURAM */ -/** @} End of group Parts */ - -#endif // EFR32BG22_BURAM_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 BURAM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_BURAM_H +#define EFR32BG22_BURAM_H +#define BURAM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_BURAM BURAM + * @{ + * @brief EFR32BG22 BURAM Register Declaration. + *****************************************************************************/ + +/** BURAM RET Register Group Declaration. */ +typedef struct { + __IOM uint32_t REG; /**< Retention Register */ +} BURAM_RET_TypeDef; + +/** BURAM Register Declaration. */ +typedef struct { + BURAM_RET_TypeDef RET[32U]; /**< RetentionReg */ + uint32_t RESERVED0[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_SET[32U]; /**< RetentionReg */ + uint32_t RESERVED1[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_CLR[32U]; /**< RetentionReg */ + uint32_t RESERVED2[992U]; /**< Reserved for future use */ + BURAM_RET_TypeDef RET_TGL[32U]; /**< RetentionReg */ +} BURAM_TypeDef; +/** @} End of group EFR32BG22_BURAM */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_BURAM + * @{ + * @defgroup EFR32BG22_BURAM_BitFields BURAM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURAM RET_REG */ +#define _BURAM_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURAM_RET_REG */ +#define _BURAM_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURAM_RET_REG */ +#define _BURAM_RET_REG_RETREG_SHIFT 0 /**< Shift value for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_MASK 0xFFFFFFFFUL /**< Bit mask for BURAM_RETREG */ +#define _BURAM_RET_REG_RETREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURAM_RET_REG */ +#define BURAM_RET_REG_RETREG_DEFAULT (_BURAM_RET_REG_RETREG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURAM_RET_REG */ + +/** @} End of group EFR32BG22_BURAM_BitFields */ +/** @} End of group EFR32BG22_BURAM */ +/** @} End of group Parts */ + +#endif // EFR32BG22_BURAM_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h index 418263a..29e378c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_burtc.h @@ -1,332 +1,332 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 BURTC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_BURTC_H -#define EFR32BG22_BURTC_H -#define BURTC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_BURTC BURTC - * @{ - * @brief EFR32BG22 BURTC Register Declaration. - *****************************************************************************/ - -/** BURTC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t COMP; /**< Compare Value Register */ - uint32_t RESERVED0[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t COMP_SET; /**< Compare Value Register */ - uint32_t RESERVED1[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t COMP_CLR; /**< Compare Value Register */ - uint32_t RESERVED2[1011U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t COMP_TGL; /**< Compare Value Register */ -} BURTC_TypeDef; -/** @} End of group EFR32BG22_BURTC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_BURTC - * @{ - * @defgroup EFR32BG22_BURTC_BitFields BURTC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for BURTC IPVERSION */ -#define _BURTC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ -#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IPVERSION */ -#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ - -/* Bit fields for BURTC EN */ -#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ -#define _BURTC_EN_MASK 0x00000001UL /**< Mask for BURTC_EN */ -#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ -#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ -#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ -#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ -#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ - -/* Bit fields for BURTC CFG */ -#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ -#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ -#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ -#define _BURTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_DISABLE (_BURTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CFG */ -#define BURTC_CFG_DEBUGRUN_ENABLE (_BURTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ -#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ -#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ -#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ -#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ -#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ -#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ -#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ - -/* Bit fields for BURTC CMD */ -#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ -#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ -#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ -#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ -#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ -#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ - -/* Bit fields for BURTC STATUS */ -#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ -#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ -#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ -#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ -#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ -#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ -#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ -#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ - -/* Bit fields for BURTC IF */ -#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ -#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ -#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ -#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ - -/* Bit fields for BURTC IEN */ -#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ -#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ -#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ -#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ -#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ -#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ -#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ -#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ - -/* Bit fields for BURTC PRECNT */ -#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ -#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ -#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ - -/* Bit fields for BURTC CNT */ -#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ -#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ -#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ -#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ -#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ - -/* Bit fields for BURTC EM4WUEN */ -#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ -#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ -#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ -#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ -#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ - -/* Bit fields for BURTC SYNCBUSY */ -#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ -#define _BURTC_SYNCBUSY_MASK 0x0000003FUL /**< Mask for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ -#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ -#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ -#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ -#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ -#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ -#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ -#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ -#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ -#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ -#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_EN (0x1UL << 5) /**< Sync busy for EN */ -#define _BURTC_SYNCBUSY_EN_SHIFT 5 /**< Shift value for BURTC_EN */ -#define _BURTC_SYNCBUSY_EN_MASK 0x20UL /**< Bit mask for BURTC_EN */ -#define _BURTC_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_EN_DEFAULT (_BURTC_SYNCBUSY_EN_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ - -/* Bit fields for BURTC LOCK */ -#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ -#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ -#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ -#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ - -/* Bit fields for BURTC COMP */ -#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ -#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ -#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ -#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ -#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ - -/** @} End of group EFR32BG22_BURTC_BitFields */ -/** @} End of group EFR32BG22_BURTC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_BURTC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 BURTC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_BURTC_H +#define EFR32BG22_BURTC_H +#define BURTC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_BURTC BURTC + * @{ + * @brief EFR32BG22 BURTC Register Declaration. + *****************************************************************************/ + +/** BURTC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t COMP; /**< Compare Value Register */ + uint32_t RESERVED0[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t COMP_SET; /**< Compare Value Register */ + uint32_t RESERVED1[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t COMP_CLR; /**< Compare Value Register */ + uint32_t RESERVED2[1011U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t COMP_TGL; /**< Compare Value Register */ +} BURTC_TypeDef; +/** @} End of group EFR32BG22_BURTC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_BURTC + * @{ + * @defgroup EFR32BG22_BURTC_BitFields BURTC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for BURTC IPVERSION */ +#define _BURTC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ +#define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IPVERSION */ +#define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ + +/* Bit fields for BURTC EN */ +#define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ +#define _BURTC_EN_MASK 0x00000001UL /**< Mask for BURTC_EN */ +#define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ +#define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ +#define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ +#define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ +#define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ + +/* Bit fields for BURTC CFG */ +#define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ +#define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ +#define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_DISABLE (_BURTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_DEBUGRUN_ENABLE (_BURTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ +#define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ +#define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ +#define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ +#define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ +#define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ +#define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ +#define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ + +/* Bit fields for BURTC CMD */ +#define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ +#define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ +#define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ +#define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ +#define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ +#define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ + +/* Bit fields for BURTC STATUS */ +#define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ +#define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ +#define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ +#define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ +#define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ +#define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ +#define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ +#define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ + +/* Bit fields for BURTC IF */ +#define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ +#define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ +#define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ +#define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ + +/* Bit fields for BURTC IEN */ +#define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ +#define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ +#define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ +#define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ +#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ +#define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ +#define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ +#define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ + +/* Bit fields for BURTC PRECNT */ +#define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ +#define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ +#define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ + +/* Bit fields for BURTC CNT */ +#define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ +#define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ +#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ +#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ +#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ + +/* Bit fields for BURTC EM4WUEN */ +#define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ +#define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ +#define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ +#define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ +#define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ + +/* Bit fields for BURTC SYNCBUSY */ +#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ +#define _BURTC_SYNCBUSY_MASK 0x0000003FUL /**< Mask for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ +#define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ +#define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ +#define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ +#define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ +#define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ +#define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ +#define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN (0x1UL << 5) /**< Sync busy for EN */ +#define _BURTC_SYNCBUSY_EN_SHIFT 5 /**< Shift value for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_MASK 0x20UL /**< Bit mask for BURTC_EN */ +#define _BURTC_SYNCBUSY_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_EN_DEFAULT (_BURTC_SYNCBUSY_EN_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ + +/* Bit fields for BURTC LOCK */ +#define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ +#define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ +#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ +#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ + +/* Bit fields for BURTC COMP */ +#define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ +#define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ +#define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ +#define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ +#define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ + +/** @} End of group EFR32BG22_BURTC_BitFields */ +/** @} End of group EFR32BG22_BURTC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_BURTC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h index d318dc1..870cc3c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cmu.h @@ -1,978 +1,978 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 CMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_CMU_H -#define EFR32BG22_CMU_H -#define CMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_CMU CMU - * @{ - * @brief EFR32BG22 CMU Register Declaration. - *****************************************************************************/ - -/** CMU Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED3[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL; /**< Calibration Control Register */ - __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ - uint32_t RESERVED7[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ - uint32_t RESERVED8[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ - __IOM uint32_t EM01GRPBCLKCTRL; /**< EM01 Peripheral Group B Clock Control */ - uint32_t RESERVED10[6U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED11[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ - uint32_t RESERVED13[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED14[7U]; /**< Reserved for future use */ - __IOM uint32_t EUART0CLKCTRL; /**< UART Clock Control */ - uint32_t RESERVED15[7U]; /**< Reserved for future use */ - __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ - uint32_t RESERVED17[5U]; /**< Reserved for future use */ - __IOM uint32_t CRYPTOACCCLKCTRL; /**< CRYPTOACC Clock Control */ - uint32_t RESERVED18[7U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ - uint32_t RESERVED19[863U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED22[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED23[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ - __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ - uint32_t RESERVED24[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ - uint32_t RESERVED28[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED29[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ - __IOM uint32_t EM01GRPBCLKCTRL_SET; /**< EM01 Peripheral Group B Clock Control */ - uint32_t RESERVED30[6U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED31[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED32[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ - uint32_t RESERVED33[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t EUART0CLKCTRL_SET; /**< UART Clock Control */ - uint32_t RESERVED35[7U]; /**< Reserved for future use */ - __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ - uint32_t RESERVED36[1U]; /**< Reserved for future use */ - __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ - uint32_t RESERVED37[5U]; /**< Reserved for future use */ - __IOM uint32_t CRYPTOACCCLKCTRL_SET; /**< CRYPTOACC Clock Control */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ - uint32_t RESERVED39[863U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED42[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED43[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ - __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ - uint32_t RESERVED44[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ - uint32_t RESERVED45[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ - uint32_t RESERVED46[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ - uint32_t RESERVED47[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ - uint32_t RESERVED48[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED49[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ - __IOM uint32_t EM01GRPBCLKCTRL_CLR; /**< EM01 Peripheral Group B Clock Control */ - uint32_t RESERVED50[6U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED51[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED52[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ - uint32_t RESERVED53[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ - uint32_t RESERVED54[7U]; /**< Reserved for future use */ - __IOM uint32_t EUART0CLKCTRL_CLR; /**< UART Clock Control */ - uint32_t RESERVED55[7U]; /**< Reserved for future use */ - __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ - uint32_t RESERVED56[1U]; /**< Reserved for future use */ - __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ - uint32_t RESERVED57[5U]; /**< Reserved for future use */ - __IOM uint32_t CRYPTOACCCLKCTRL_CLR; /**< CRYPTOACC Clock Control */ - uint32_t RESERVED58[7U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ - uint32_t RESERVED59[863U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED60[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED61[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ - uint32_t RESERVED62[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED63[10U]; /**< Reserved for future use */ - __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ - __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ - __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ - uint32_t RESERVED64[2U]; /**< Reserved for future use */ - __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ - __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ - uint32_t RESERVED65[1U]; /**< Reserved for future use */ - __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ - uint32_t RESERVED66[3U]; /**< Reserved for future use */ - __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ - uint32_t RESERVED67[3U]; /**< Reserved for future use */ - __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ - uint32_t RESERVED68[27U]; /**< Reserved for future use */ - __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ - uint32_t RESERVED69[7U]; /**< Reserved for future use */ - __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ - __IOM uint32_t EM01GRPBCLKCTRL_TGL; /**< EM01 Peripheral Group B Clock Control */ - uint32_t RESERVED70[6U]; /**< Reserved for future use */ - __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ - uint32_t RESERVED71[7U]; /**< Reserved for future use */ - __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ - uint32_t RESERVED72[7U]; /**< Reserved for future use */ - __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ - uint32_t RESERVED73[31U]; /**< Reserved for future use */ - __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ - uint32_t RESERVED74[7U]; /**< Reserved for future use */ - __IOM uint32_t EUART0CLKCTRL_TGL; /**< UART Clock Control */ - uint32_t RESERVED75[7U]; /**< Reserved for future use */ - __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ - uint32_t RESERVED76[1U]; /**< Reserved for future use */ - __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ - uint32_t RESERVED77[5U]; /**< Reserved for future use */ - __IOM uint32_t CRYPTOACCCLKCTRL_TGL; /**< CRYPTOACC Clock Control */ - uint32_t RESERVED78[7U]; /**< Reserved for future use */ - __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ -} CMU_TypeDef; -/** @} End of group EFR32BG22_CMU */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_CMU - * @{ - * @defgroup EFR32BG22_CMU_BitFields CMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for CMU IPVERSION */ -#define _CMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for CMU_IPVERSION */ -#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ -#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IPVERSION */ -#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ - -/* Bit fields for CMU STATUS */ -#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ -#define _CMU_STATUS_MASK 0xC0030001UL /**< Mask for CMU_STATUS */ -#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ -#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ -#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ -#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ -#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ -#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ -#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ -#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ -#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ -#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ - -/* Bit fields for CMU LOCK */ -#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ -#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ -#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ - -/* Bit fields for CMU WDOGLOCK */ -#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ -#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ -#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ -#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ - -/* Bit fields for CMU IF */ -#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ -#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ -#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ -#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ -#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ -#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ - -/* Bit fields for CMU IEN */ -#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ -#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ -#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ -#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ -#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ -#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ -#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ -#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ -#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ - -/* Bit fields for CMU CALCMD */ -#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ -#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ -#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ -#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ -#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ -#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ -#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ - -/* Bit fields for CMU CALCTRL */ -#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ -#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ -#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ -#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ -#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ -#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ -#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ -#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ -#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ -#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ -#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ - -/* Bit fields for CMU CALCNT */ -#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ -#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ -#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ - -/* Bit fields for CMU CLKEN0 */ -#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ -#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ -#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ -#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ -#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ -#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ -#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ -#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ -#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ -#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0 (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_USART0_SHIFT 8 /**< Shift value for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_MASK 0x100UL /**< Bit mask for CMU_USART0 */ -#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART1 (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_USART1_SHIFT 9 /**< Shift value for CMU_USART1 */ -#define _CMU_CLKEN0_USART1_MASK 0x200UL /**< Bit mask for CMU_USART1 */ -#define _CMU_CLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_USART1_DEFAULT (_CMU_CLKEN0_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ -#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ -#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ -#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ -#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ -#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ -#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ -#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ -#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ -#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0 (0x1UL << 19) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_HFXO0_SHIFT 19 /**< Shift value for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_MASK 0x80000UL /**< Bit mask for CMU_HFXO0 */ -#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO (0x1UL << 20) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_FSRCO_SHIFT 20 /**< Shift value for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_MASK 0x100000UL /**< Bit mask for CMU_FSRCO */ -#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO (0x1UL << 21) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFRCO_SHIFT 21 /**< Shift value for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_MASK 0x200000UL /**< Bit mask for CMU_LFRCO */ -#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO (0x1UL << 22) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_LFXO_SHIFT 22 /**< Shift value for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_MASK 0x400000UL /**< Bit mask for CMU_LFXO */ -#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO (0x1UL << 23) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_ULFRCO_SHIFT 23 /**< Shift value for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_MASK 0x800000UL /**< Bit mask for CMU_ULFRCO */ -#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_EUART0 (0x1UL << 24) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_EUART0_SHIFT 24 /**< Shift value for CMU_EUART0 */ -#define _CMU_CLKEN0_EUART0_MASK 0x1000000UL /**< Bit mask for CMU_EUART0 */ -#define _CMU_CLKEN0_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_EUART0_DEFAULT (_CMU_CLKEN0_EUART0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PDM (0x1UL << 25) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_PDM_SHIFT 25 /**< Shift value for CMU_PDM */ -#define _CMU_CLKEN0_PDM_MASK 0x2000000UL /**< Bit mask for CMU_PDM */ -#define _CMU_CLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PDM_DEFAULT (_CMU_CLKEN0_PDM_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ -#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ -#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ -#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ -#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ -#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RTCC (0x1UL << 30) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_RTCC_SHIFT 30 /**< Shift value for CMU_RTCC */ -#define _CMU_CLKEN0_RTCC_MASK 0x40000000UL /**< Bit mask for CMU_RTCC */ -#define _CMU_CLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_RTCC_DEFAULT (_CMU_CLKEN0_RTCC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ -#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ -#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ -#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ - -/* Bit fields for CMU CLKEN1 */ -#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ -#define _CMU_CLKEN1_MASK 0x0007FFFFUL /**< Mask for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ -#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ -#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ -#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ -#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ -#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ -#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ -#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ -#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ -#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ -#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RDSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RDSCRATCHPAD */ -#define _CMU_CLKEN1_RDSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RDSCRATCHPAD */ -#define _CMU_CLKEN1_RDSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RDSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDMAILBOX0 (0x1UL << 8) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RDMAILBOX0_SHIFT 8 /**< Shift value for CMU_RDMAILBOX0 */ -#define _CMU_CLKEN1_RDMAILBOX0_MASK 0x100UL /**< Bit mask for CMU_RDMAILBOX0 */ -#define _CMU_CLKEN1_RDMAILBOX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDMAILBOX0_DEFAULT (_CMU_CLKEN1_RDMAILBOX0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDMAILBOX1 (0x1UL << 9) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RDMAILBOX1_SHIFT 9 /**< Shift value for CMU_RDMAILBOX1 */ -#define _CMU_CLKEN1_RDMAILBOX1_MASK 0x200UL /**< Bit mask for CMU_RDMAILBOX1 */ -#define _CMU_CLKEN1_RDMAILBOX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RDMAILBOX1_DEFAULT (_CMU_CLKEN1_RDMAILBOX1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PRORTC (0x1UL << 10) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_PRORTC_SHIFT 10 /**< Shift value for CMU_PRORTC */ -#define _CMU_CLKEN1_PRORTC_MASK 0x400UL /**< Bit mask for CMU_PRORTC */ -#define _CMU_CLKEN1_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_PRORTC_DEFAULT (_CMU_CLKEN1_PRORTC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ -#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_IFADCDEBUG (0x1UL << 12) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_IFADCDEBUG_SHIFT 12 /**< Shift value for CMU_IFADCDEBUG */ -#define _CMU_CLKEN1_IFADCDEBUG_MASK 0x1000UL /**< Bit mask for CMU_IFADCDEBUG */ -#define _CMU_CLKEN1_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_IFADCDEBUG_DEFAULT (_CMU_CLKEN1_IFADCDEBUG_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_CRYPTOACC (0x1UL << 13) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_CRYPTOACC_SHIFT 13 /**< Shift value for CMU_CRYPTOACC */ -#define _CMU_CLKEN1_CRYPTOACC_MASK 0x2000UL /**< Bit mask for CMU_CRYPTOACC */ -#define _CMU_CLKEN1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_CRYPTOACC_DEFAULT (_CMU_CLKEN1_CRYPTOACC_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSENSE (0x1UL << 14) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_RFSENSE_SHIFT 14 /**< Shift value for CMU_RFSENSE */ -#define _CMU_CLKEN1_RFSENSE_MASK 0x4000UL /**< Bit mask for CMU_RFSENSE */ -#define _CMU_CLKEN1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_RFSENSE_DEFAULT (_CMU_CLKEN1_RFSENSE_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU (0x1UL << 15) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_SMU_SHIFT 15 /**< Shift value for CMU_SMU */ -#define _CMU_CLKEN1_SMU_MASK 0x8000UL /**< Bit mask for CMU_SMU */ -#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0 (0x1UL << 16) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_ICACHE0_SHIFT 16 /**< Shift value for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_MASK 0x10000UL /**< Bit mask for CMU_ICACHE0 */ -#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC (0x1UL << 17) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_MSC_SHIFT 17 /**< Shift value for CMU_MSC */ -#define _CMU_CLKEN1_MSC_MASK 0x20000UL /**< Bit mask for CMU_MSC */ -#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_TIMER4 (0x1UL << 18) /**< Enable Bus Clock */ -#define _CMU_CLKEN1_TIMER4_SHIFT 18 /**< Shift value for CMU_TIMER4 */ -#define _CMU_CLKEN1_TIMER4_MASK 0x40000UL /**< Bit mask for CMU_TIMER4 */ -#define _CMU_CLKEN1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ -#define CMU_CLKEN1_TIMER4_DEFAULT (_CMU_CLKEN1_TIMER4_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ - -/* Bit fields for CMU SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ -#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ -#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ - -/* Bit fields for CMU TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ -#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ -#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ -#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ - -/* Bit fields for CMU EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ -#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ -#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ -#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ - -/* Bit fields for CMU DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ -#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ -#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ -#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ - -/* Bit fields for CMU EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ -#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ -#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ - -/* Bit fields for CMU EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL */ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPBCLKCTRL*/ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPBCLKCTRL*/ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 (_CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL*/ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPBCLKCTRL */ - -/* Bit fields for CMU EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ - -/* Bit fields for CMU EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ - -/* Bit fields for CMU IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ -#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ -#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ -#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ - -/* Bit fields for CMU WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ - -/* Bit fields for CMU EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_EUART0CLKCTRL */ -#define _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_EUART0CLKCTRL */ -#define CMU_EUART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUART0CLKCTRL */ -#define CMU_EUART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUART0CLKCTRL */ -#define CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_EUART0CLKCTRL*/ -#define CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_EUART0CLKCTRL*/ - -/* Bit fields for CMU RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ -#define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ -#define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ -#define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ -#define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ -#define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ - -/* Bit fields for CMU PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ -#define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ -#define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ -#define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ -#define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ -#define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ - -/* Bit fields for CMU CRYPTOACCCLKCTRL */ -#define _CMU_CRYPTOACCCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CRYPTOACCCLKCTRL */ -#define _CMU_CRYPTOACCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_CRYPTOACCCLKCTRL */ -#define CMU_CRYPTOACCCLKCTRL_PKEN (0x1UL << 0) /**< PK Enable */ -#define _CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT 0 /**< Shift value for CMU_PKEN */ -#define _CMU_CRYPTOACCCLKCTRL_PKEN_MASK 0x1UL /**< Bit mask for CMU_PKEN */ -#define _CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ -#define CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ -#define CMU_CRYPTOACCCLKCTRL_AESEN (0x1UL << 1) /**< AES Enable */ -#define _CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT 1 /**< Shift value for CMU_AESEN */ -#define _CMU_CRYPTOACCCLKCTRL_AESEN_MASK 0x2UL /**< Bit mask for CMU_AESEN */ -#define _CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ -#define CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ - -/* Bit fields for CMU RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ -#define _CMU_RADIOCLKCTRL_MASK 0x80000001UL /**< Mask for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ -#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ -#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ -#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ -#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ -#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ - -/** @} End of group EFR32BG22_CMU_BitFields */ -/** @} End of group EFR32BG22_CMU */ -/** @} End of group Parts */ - -#endif // EFR32BG22_CMU_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 CMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_CMU_H +#define EFR32BG22_CMU_H +#define CMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_CMU CMU + * @{ + * @brief EFR32BG22 CMU Register Declaration. + *****************************************************************************/ + +/** CMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED3[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL; /**< Calibration Control Register */ + __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ + uint32_t RESERVED7[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ + uint32_t RESERVED8[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL; /**< EM01 Peripheral Group B Clock Control */ + uint32_t RESERVED10[6U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED11[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ + uint32_t RESERVED13[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED14[7U]; /**< Reserved for future use */ + __IOM uint32_t EUART0CLKCTRL; /**< UART Clock Control */ + uint32_t RESERVED15[7U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED17[5U]; /**< Reserved for future use */ + __IOM uint32_t CRYPTOACCCLKCTRL; /**< CRYPTOACC Clock Control */ + uint32_t RESERVED18[7U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ + uint32_t RESERVED19[863U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED23[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ + __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ + uint32_t RESERVED24[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ + uint32_t RESERVED28[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_SET; /**< EM01 Peripheral Group B Clock Control */ + uint32_t RESERVED30[6U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED31[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED32[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ + uint32_t RESERVED33[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t EUART0CLKCTRL_SET; /**< UART Clock Control */ + uint32_t RESERVED35[7U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ + uint32_t RESERVED36[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ + uint32_t RESERVED37[5U]; /**< Reserved for future use */ + __IOM uint32_t CRYPTOACCCLKCTRL_SET; /**< CRYPTOACC Clock Control */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ + uint32_t RESERVED39[863U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED43[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ + __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ + uint32_t RESERVED44[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ + uint32_t RESERVED46[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ + uint32_t RESERVED47[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ + uint32_t RESERVED48[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED49[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_CLR; /**< EM01 Peripheral Group B Clock Control */ + uint32_t RESERVED50[6U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED51[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED52[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ + uint32_t RESERVED53[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ + uint32_t RESERVED54[7U]; /**< Reserved for future use */ + __IOM uint32_t EUART0CLKCTRL_CLR; /**< UART Clock Control */ + uint32_t RESERVED55[7U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ + uint32_t RESERVED56[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ + uint32_t RESERVED57[5U]; /**< Reserved for future use */ + __IOM uint32_t CRYPTOACCCLKCTRL_CLR; /**< CRYPTOACC Clock Control */ + uint32_t RESERVED58[7U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ + uint32_t RESERVED59[863U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED60[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED61[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ + uint32_t RESERVED62[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED63[10U]; /**< Reserved for future use */ + __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ + __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ + __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ + uint32_t RESERVED64[2U]; /**< Reserved for future use */ + __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ + __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ + uint32_t RESERVED65[1U]; /**< Reserved for future use */ + __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ + uint32_t RESERVED66[3U]; /**< Reserved for future use */ + __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ + uint32_t RESERVED67[3U]; /**< Reserved for future use */ + __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ + uint32_t RESERVED68[27U]; /**< Reserved for future use */ + __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ + uint32_t RESERVED69[7U]; /**< Reserved for future use */ + __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ + __IOM uint32_t EM01GRPBCLKCTRL_TGL; /**< EM01 Peripheral Group B Clock Control */ + uint32_t RESERVED70[6U]; /**< Reserved for future use */ + __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ + uint32_t RESERVED71[7U]; /**< Reserved for future use */ + __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ + uint32_t RESERVED72[7U]; /**< Reserved for future use */ + __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ + uint32_t RESERVED73[31U]; /**< Reserved for future use */ + __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ + uint32_t RESERVED74[7U]; /**< Reserved for future use */ + __IOM uint32_t EUART0CLKCTRL_TGL; /**< UART Clock Control */ + uint32_t RESERVED75[7U]; /**< Reserved for future use */ + __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ + uint32_t RESERVED76[1U]; /**< Reserved for future use */ + __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ + uint32_t RESERVED77[5U]; /**< Reserved for future use */ + __IOM uint32_t CRYPTOACCCLKCTRL_TGL; /**< CRYPTOACC Clock Control */ + uint32_t RESERVED78[7U]; /**< Reserved for future use */ + __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ +} CMU_TypeDef; +/** @} End of group EFR32BG22_CMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_CMU + * @{ + * @defgroup EFR32BG22_CMU_BitFields CMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CMU IPVERSION */ +#define _CMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for CMU_IPVERSION */ +#define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ +#define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IPVERSION */ +#define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ + +/* Bit fields for CMU STATUS */ +#define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ +#define _CMU_STATUS_MASK 0xC0030001UL /**< Mask for CMU_STATUS */ +#define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ +#define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ +#define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ +#define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ +#define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ +#define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ +#define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ +#define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ +#define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ +#define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ + +/* Bit fields for CMU LOCK */ +#define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ +#define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ +#define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ + +/* Bit fields for CMU WDOGLOCK */ +#define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ +#define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ +#define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ +#define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ + +/* Bit fields for CMU IF */ +#define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ +#define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ +#define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ +#define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ +#define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ +#define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ + +/* Bit fields for CMU IEN */ +#define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ +#define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ +#define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ +#define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ +#define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ +#define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ +#define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ +#define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ +#define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ + +/* Bit fields for CMU CALCMD */ +#define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ +#define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ +#define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ +#define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ +#define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ +#define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ +#define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ + +/* Bit fields for CMU CALCTRL */ +#define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ +#define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ +#define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ +#define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ +#define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ +#define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ +#define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ +#define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ +#define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ +#define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ +#define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ + +/* Bit fields for CMU CALCNT */ +#define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ +#define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ +#define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ + +/* Bit fields for CMU CLKEN0 */ +#define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ +#define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ +#define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ +#define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ +#define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ +#define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ +#define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ +#define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ +#define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ +#define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART0_SHIFT 8 /**< Shift value for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_MASK 0x100UL /**< Bit mask for CMU_USART0 */ +#define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_USART1_SHIFT 9 /**< Shift value for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_MASK 0x200UL /**< Bit mask for CMU_USART1 */ +#define _CMU_CLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_USART1_DEFAULT (_CMU_CLKEN0_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ +#define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ +#define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ +#define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ +#define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ +#define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ +#define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ +#define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ +#define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ +#define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0 (0x1UL << 19) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_HFXO0_SHIFT 19 /**< Shift value for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_MASK 0x80000UL /**< Bit mask for CMU_HFXO0 */ +#define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO (0x1UL << 20) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_FSRCO_SHIFT 20 /**< Shift value for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_MASK 0x100000UL /**< Bit mask for CMU_FSRCO */ +#define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO (0x1UL << 21) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFRCO_SHIFT 21 /**< Shift value for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_MASK 0x200000UL /**< Bit mask for CMU_LFRCO */ +#define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO (0x1UL << 22) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_LFXO_SHIFT 22 /**< Shift value for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_MASK 0x400000UL /**< Bit mask for CMU_LFXO */ +#define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO (0x1UL << 23) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_ULFRCO_SHIFT 23 /**< Shift value for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_MASK 0x800000UL /**< Bit mask for CMU_ULFRCO */ +#define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_EUART0 (0x1UL << 24) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_EUART0_SHIFT 24 /**< Shift value for CMU_EUART0 */ +#define _CMU_CLKEN0_EUART0_MASK 0x1000000UL /**< Bit mask for CMU_EUART0 */ +#define _CMU_CLKEN0_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_EUART0_DEFAULT (_CMU_CLKEN0_EUART0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM (0x1UL << 25) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PDM_SHIFT 25 /**< Shift value for CMU_PDM */ +#define _CMU_CLKEN0_PDM_MASK 0x2000000UL /**< Bit mask for CMU_PDM */ +#define _CMU_CLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PDM_DEFAULT (_CMU_CLKEN0_PDM_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ +#define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ +#define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ +#define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ +#define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ +#define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC (0x1UL << 30) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_RTCC_SHIFT 30 /**< Shift value for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_MASK 0x40000000UL /**< Bit mask for CMU_RTCC */ +#define _CMU_CLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_RTCC_DEFAULT (_CMU_CLKEN0_RTCC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ +#define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ +#define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ +#define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ + +/* Bit fields for CMU CLKEN1 */ +#define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ +#define _CMU_CLKEN1_MASK 0x0007FFFFUL /**< Mask for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ +#define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ +#define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ +#define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ +#define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ +#define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ +#define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ +#define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ +#define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ +#define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ +#define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RDSCRATCHPAD */ +#define _CMU_CLKEN1_RDSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RDSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0 (0x1UL << 8) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX0_SHIFT 8 /**< Shift value for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_MASK 0x100UL /**< Bit mask for CMU_RDMAILBOX0 */ +#define _CMU_CLKEN1_RDMAILBOX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX0_DEFAULT (_CMU_CLKEN1_RDMAILBOX0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1 (0x1UL << 9) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RDMAILBOX1_SHIFT 9 /**< Shift value for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_MASK 0x200UL /**< Bit mask for CMU_RDMAILBOX1 */ +#define _CMU_CLKEN1_RDMAILBOX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RDMAILBOX1_DEFAULT (_CMU_CLKEN1_RDMAILBOX1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC (0x1UL << 10) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_PRORTC_SHIFT 10 /**< Shift value for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_MASK 0x400UL /**< Bit mask for CMU_PRORTC */ +#define _CMU_CLKEN1_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_PRORTC_DEFAULT (_CMU_CLKEN1_PRORTC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ +#define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG (0x1UL << 12) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_IFADCDEBUG_SHIFT 12 /**< Shift value for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_MASK 0x1000UL /**< Bit mask for CMU_IFADCDEBUG */ +#define _CMU_CLKEN1_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_IFADCDEBUG_DEFAULT (_CMU_CLKEN1_IFADCDEBUG_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_CRYPTOACC (0x1UL << 13) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_CRYPTOACC_SHIFT 13 /**< Shift value for CMU_CRYPTOACC */ +#define _CMU_CLKEN1_CRYPTOACC_MASK 0x2000UL /**< Bit mask for CMU_CRYPTOACC */ +#define _CMU_CLKEN1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_CRYPTOACC_DEFAULT (_CMU_CLKEN1_CRYPTOACC_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE (0x1UL << 14) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_RFSENSE_SHIFT 14 /**< Shift value for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_MASK 0x4000UL /**< Bit mask for CMU_RFSENSE */ +#define _CMU_CLKEN1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_RFSENSE_DEFAULT (_CMU_CLKEN1_RFSENSE_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU (0x1UL << 15) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_SMU_SHIFT 15 /**< Shift value for CMU_SMU */ +#define _CMU_CLKEN1_SMU_MASK 0x8000UL /**< Bit mask for CMU_SMU */ +#define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0 (0x1UL << 16) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_ICACHE0_SHIFT 16 /**< Shift value for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_MASK 0x10000UL /**< Bit mask for CMU_ICACHE0 */ +#define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC (0x1UL << 17) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_MSC_SHIFT 17 /**< Shift value for CMU_MSC */ +#define _CMU_CLKEN1_MSC_MASK 0x20000UL /**< Bit mask for CMU_MSC */ +#define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4 (0x1UL << 18) /**< Enable Bus Clock */ +#define _CMU_CLKEN1_TIMER4_SHIFT 18 /**< Shift value for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_MASK 0x40000UL /**< Bit mask for CMU_TIMER4 */ +#define _CMU_CLKEN1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ +#define CMU_CLKEN1_TIMER4_DEFAULT (_CMU_CLKEN1_TIMER4_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ + +/* Bit fields for CMU SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ +#define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ +#define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ + +/* Bit fields for CMU TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ +#define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ +#define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ +#define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ + +/* Bit fields for CMU EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ +#define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ +#define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ +#define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ + +/* Bit fields for CMU DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ +#define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ +#define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ +#define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ + +/* Bit fields for CMU EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ +#define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ +#define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ + +/* Bit fields for CMU EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL */ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 (_CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL*/ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPBCLKCTRL */ + +/* Bit fields for CMU EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ + +/* Bit fields for CMU EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ + +/* Bit fields for CMU IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ +#define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ +#define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ +#define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ + +/* Bit fields for CMU WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ + +/* Bit fields for CMU EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_EUART0CLKCTRL */ +#define _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_EUART0CLKCTRL */ +#define CMU_EUART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUART0CLKCTRL */ +#define CMU_EUART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUART0CLKCTRL */ +#define CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_EUART0CLKCTRL*/ +#define CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_EUART0CLKCTRL*/ + +/* Bit fields for CMU RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ +#define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ +#define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ + +/* Bit fields for CMU PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ +#define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ +#define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ + +/* Bit fields for CMU CRYPTOACCCLKCTRL */ +#define _CMU_CRYPTOACCCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CRYPTOACCCLKCTRL */ +#define _CMU_CRYPTOACCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_CRYPTOACCCLKCTRL */ +#define CMU_CRYPTOACCCLKCTRL_PKEN (0x1UL << 0) /**< PK Enable */ +#define _CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT 0 /**< Shift value for CMU_PKEN */ +#define _CMU_CRYPTOACCCLKCTRL_PKEN_MASK 0x1UL /**< Bit mask for CMU_PKEN */ +#define _CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ +#define CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ +#define CMU_CRYPTOACCCLKCTRL_AESEN (0x1UL << 1) /**< AES Enable */ +#define _CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT 1 /**< Shift value for CMU_AESEN */ +#define _CMU_CRYPTOACCCLKCTRL_AESEN_MASK 0x2UL /**< Bit mask for CMU_AESEN */ +#define _CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ +#define CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ + +/* Bit fields for CMU RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ +#define _CMU_RADIOCLKCTRL_MASK 0x80000001UL /**< Mask for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ +#define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ +#define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ +#define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ +#define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ +#define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ + +/** @} End of group EFR32BG22_CMU_BitFields */ +/** @} End of group EFR32BG22_CMU */ +/** @} End of group Parts */ + +#endif // EFR32BG22_CMU_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h index e08c701..ceb5c8d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_cryptoacc.h @@ -1,1022 +1,1022 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 CRYPTOACC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_CRYPTOACC_H -#define EFR32BG22_CRYPTOACC_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_CRYPTOACC CRYPTOACC - * @{ - * @brief EFR32BG22 CRYPTOACC Register Declaration. - *****************************************************************************/ - -/** CRYPTOACC Register Declaration. */ -typedef struct { - __IOM uint32_t FETCHADDR; /**< Fetcher Address */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t FETCHLEN; /**< Fetcher Length */ - __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ - __IOM uint32_t PUSHADDR; /**< Pusher Address */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t PUSHLEN; /**< Pusher Length */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IM uint32_t IF; /**< Interrupt Flags */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt status clear */ - __IOM uint32_t CTRL; /**< Control register */ - __IOM uint32_t CMD; /**< Command register */ - __IM uint32_t STATUS; /**< Status register */ - uint32_t RESERVED4[240U]; /**< Reserved for future use */ - __IM uint32_t INCL_IPS_HW_CFG; /**< General CRYPTOACC Hardware Configuration */ - __IM uint32_t BA411E_HW_CFG_1; /**< BA411E Hardware Configuration 1 */ - __IM uint32_t BA411E_HW_CFG_2; /**< BA411E Hardware Configuration 2 */ - __IM uint32_t BA413_HW_CFG; /**< BA413 Hardware Configuration */ - __IM uint32_t BA418_HW_CFG; /**< BA418 Hardware Configuration */ - __IM uint32_t BA419_HW_CFG; /**< BA419 Hardware Configuration */ -} CRYPTOACC_TypeDef; -/** @} End of group EFR32BG22_CRYPTOACC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_CRYPTOACC - * @{ - * @defgroup EFR32BG22_CRYPTOACC_BitFields CRYPTOACC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for CRYPTOACC FETCHADDR */ -#define _CRYPTOACC_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHADDR */ -#define _CRYPTOACC_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHADDR */ -#define _CRYPTOACC_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ -#define _CRYPTOACC_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ -#define _CRYPTOACC_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHADDR */ -#define CRYPTOACC_FETCHADDR_ADDR_DEFAULT (_CRYPTOACC_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHADDR*/ - -/* Bit fields for CRYPTOACC FETCHLEN */ -#define _CRYPTOACC_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHLEN */ -#define _CRYPTOACC_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for CRYPTOACC_FETCHLEN */ -#define _CRYPTOACC_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ -#define _CRYPTOACC_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ -#define _CRYPTOACC_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ -#define CRYPTOACC_FETCHLEN_LENGTH_DEFAULT (_CRYPTOACC_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ -#define CRYPTOACC_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _CRYPTOACC_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ -#define _CRYPTOACC_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ -#define _CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ -#define CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ -#define CRYPTOACC_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _CRYPTOACC_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ -#define _CRYPTOACC_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ -#define _CRYPTOACC_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ -#define CRYPTOACC_FETCHLEN_REALIGN_DEFAULT (_CRYPTOACC_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ - -/* Bit fields for CRYPTOACC FETCHTAG */ -#define _CRYPTOACC_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHTAG */ -#define _CRYPTOACC_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHTAG */ -#define _CRYPTOACC_FETCHTAG_TAG_SHIFT 0 /**< Shift value for CRYPTOACC_TAG */ -#define _CRYPTOACC_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TAG */ -#define _CRYPTOACC_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHTAG */ -#define CRYPTOACC_FETCHTAG_TAG_DEFAULT (_CRYPTOACC_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHTAG */ - -/* Bit fields for CRYPTOACC PUSHADDR */ -#define _CRYPTOACC_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHADDR */ -#define _CRYPTOACC_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_PUSHADDR */ -#define _CRYPTOACC_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ -#define _CRYPTOACC_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ -#define _CRYPTOACC_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHADDR */ -#define CRYPTOACC_PUSHADDR_ADDR_DEFAULT (_CRYPTOACC_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHADDR */ - -/* Bit fields for CRYPTOACC PUSHLEN */ -#define _CRYPTOACC_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHLEN */ -#define _CRYPTOACC_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for CRYPTOACC_PUSHLEN */ -#define _CRYPTOACC_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ -#define _CRYPTOACC_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ -#define _CRYPTOACC_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_LENGTH_DEFAULT (_CRYPTOACC_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ -#define _CRYPTOACC_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ -#define _CRYPTOACC_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ -#define _CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ -#define _CRYPTOACC_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ -#define _CRYPTOACC_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ -#define _CRYPTOACC_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_REALIGN_DEFAULT (_CRYPTOACC_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ -#define _CRYPTOACC_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for CRYPTOACC_DISCARD */ -#define _CRYPTOACC_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_DISCARD */ -#define _CRYPTOACC_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ -#define CRYPTOACC_PUSHLEN_DISCARD_DEFAULT (_CRYPTOACC_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ - -/* Bit fields for CRYPTOACC IEN */ -#define _CRYPTOACC_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IEN */ -#define _CRYPTOACC_IEN_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ -#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ -#define _CRYPTOACC_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ -#define _CRYPTOACC_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_FETCHERERROR_DEFAULT (_CRYPTOACC_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ -#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ -#define _CRYPTOACC_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ -#define _CRYPTOACC_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ -#define CRYPTOACC_IEN_PUSHERERROR_DEFAULT (_CRYPTOACC_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ - -/* Bit fields for CRYPTOACC IF */ -#define _CRYPTOACC_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF */ -#define _CRYPTOACC_IF_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ -#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ -#define _CRYPTOACC_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ -#define _CRYPTOACC_IF_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ -#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ -#define _CRYPTOACC_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ -#define _CRYPTOACC_IF_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ -#define CRYPTOACC_IF_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ - -/* Bit fields for CRYPTOACC IF_CLR */ -#define _CRYPTOACC_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF_CLR */ -#define _CRYPTOACC_IF_CLR_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ -#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ -#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ -#define _CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ -#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ -#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag clear */ -#define _CRYPTOACC_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ -#define _CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ -#define CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ - -/* Bit fields for CRYPTOACC CTRL */ -#define _CRYPTOACC_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CTRL */ -#define _CRYPTOACC_CTRL_MASK 0x0000001FUL /**< Mask for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ -#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERSCATTERGATHER*/ -#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERSCATTERGATHER */ -#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ -#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERSCATTERGATHER*/ -#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERSCATTERGATHER */ -#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ -#define _CRYPTOACC_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for CRYPTOACC_STOPFETCHER */ -#define _CRYPTOACC_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for CRYPTOACC_STOPFETCHER */ -#define _CRYPTOACC_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_STOPFETCHER_DEFAULT (_CRYPTOACC_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ -#define _CRYPTOACC_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for CRYPTOACC_STOPPUSHER */ -#define _CRYPTOACC_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for CRYPTOACC_STOPPUSHER */ -#define _CRYPTOACC_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_STOPPUSHER_DEFAULT (_CRYPTOACC_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ -#define _CRYPTOACC_CTRL_SWRESET_SHIFT 4 /**< Shift value for CRYPTOACC_SWRESET */ -#define _CRYPTOACC_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for CRYPTOACC_SWRESET */ -#define _CRYPTOACC_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ -#define CRYPTOACC_CTRL_SWRESET_DEFAULT (_CRYPTOACC_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ - -/* Bit fields for CRYPTOACC CMD */ -#define _CRYPTOACC_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CMD */ -#define _CRYPTOACC_CMD_MASK 0x00000003UL /**< Mask for CRYPTOACC_CMD */ -#define CRYPTOACC_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ -#define _CRYPTOACC_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for CRYPTOACC_STARTFETCHER */ -#define _CRYPTOACC_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_STARTFETCHER */ -#define _CRYPTOACC_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ -#define CRYPTOACC_CMD_STARTFETCHER_DEFAULT (_CRYPTOACC_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ -#define CRYPTOACC_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ -#define _CRYPTOACC_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for CRYPTOACC_STARTPUSHER */ -#define _CRYPTOACC_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_STARTPUSHER */ -#define _CRYPTOACC_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ -#define CRYPTOACC_CMD_STARTPUSHER_DEFAULT (_CRYPTOACC_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ - -/* Bit fields for CRYPTOACC STATUS */ -#define _CRYPTOACC_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_STATUS */ -#define _CRYPTOACC_STATUS_MASK 0xFFFF0073UL /**< Mask for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ -#define _CRYPTOACC_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERBSY */ -#define _CRYPTOACC_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERBSY */ -#define _CRYPTOACC_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_FETCHERBSY_DEFAULT (_CRYPTOACC_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ -#define _CRYPTOACC_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERBSY */ -#define _CRYPTOACC_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERBSY */ -#define _CRYPTOACC_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_PUSHERBSY_DEFAULT (_CRYPTOACC_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ -#define _CRYPTOACC_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for CRYPTOACC_NOTEMPTY */ -#define _CRYPTOACC_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTEMPTY */ -#define _CRYPTOACC_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_NOTEMPTY_DEFAULT (_CRYPTOACC_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ -#define _CRYPTOACC_STATUS_WAITING_SHIFT 5 /**< Shift value for CRYPTOACC_WAITING */ -#define _CRYPTOACC_STATUS_WAITING_MASK 0x20UL /**< Bit mask for CRYPTOACC_WAITING */ -#define _CRYPTOACC_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_WAITING_DEFAULT (_CRYPTOACC_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ -#define _CRYPTOACC_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for CRYPTOACC_SOFTRSTBSY */ -#define _CRYPTOACC_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for CRYPTOACC_SOFTRSTBSY */ -#define _CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT (_CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ -#define _CRYPTOACC_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for CRYPTOACC_FIFODATANUM */ -#define _CRYPTOACC_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for CRYPTOACC_FIFODATANUM */ -#define _CRYPTOACC_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ -#define CRYPTOACC_STATUS_FIFODATANUM_DEFAULT (_CRYPTOACC_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ - -/* Bit fields for CRYPTOACC INCL_IPS_HW_CFG */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_RESETVALUE 0x00000611UL /**< Default value for CRYPTOACC_INCL_IPS_HW_CFG */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for CRYPTOACC_g_IncludeAES */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_IncludeAES */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for CRYPTOACC_g_IncludeAESGCM */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for CRYPTOACC_g_IncludeAESGCM */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for CRYPTOACC_g_IncludeAESXTS */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for CRYPTOACC_g_IncludeAESXTS */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for CRYPTOACC_g_IncludeDES */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for CRYPTOACC_g_IncludeDES */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for CRYPTOACC_g_IncludeHASH */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for CRYPTOACC_g_IncludeHASH */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for CRYPTOACC_g_IncludeChachaPoly*/ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for CRYPTOACC_g_IncludeChachaPoly */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for CRYPTOACC_g_IncludeSHA3 */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for CRYPTOACC_g_IncludeSHA3 */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for CRYPTOACC_g_IncludeZUC */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for CRYPTOACC_g_IncludeZUC */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for CRYPTOACC_g_IncludeSM4 */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for CRYPTOACC_g_IncludeSM4 */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for CRYPTOACC_g_IncludePKE */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for CRYPTOACC_g_IncludePKE */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for CRYPTOACC_g_IncludeNDRNG */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for CRYPTOACC_g_IncludeNDRNG */ -#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ -#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ - -/* Bit fields for CRYPTOACC BA411E_HW_CFG_1 */ -#define _CRYPTOACC_BA411E_HW_CFG_1_RESETVALUE 0x0700017FUL /**< Default value for CRYPTOACC_BA411E_HW_CFG_1 */ -#define _CRYPTOACC_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_1 */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_AesModesPoss */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for CRYPTOACC_g_AesModesPoss */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x0000017FUL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ -#define CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ -#define CRYPTOACC_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for CRYPTOACC_g_CS */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_CS */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ -#define CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ -#define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for CRYPTOACC_g_UseMasking */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_UseMasking */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ -#define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for CRYPTOACC_g_Keysize */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for CRYPTOACC_g_Keysize */ -#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000007UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ -#define CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ - -/* Bit fields for CRYPTOACC BA411E_HW_CFG_2 */ -#define _CRYPTOACC_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for CRYPTOACC_BA411E_HW_CFG_2 */ -#define _CRYPTOACC_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_2 */ -#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for CRYPTOACC_g_CtrSize */ -#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_g_CtrSize */ -#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2 */ -#define CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2*/ - -/* Bit fields for CRYPTOACC BA413_HW_CFG */ -#define _CRYPTOACC_BA413_HW_CFG_RESETVALUE 0x0003007FUL /**< Default value for CRYPTOACC_BA413_HW_CFG */ -#define _CRYPTOACC_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for CRYPTOACC_BA413_HW_CFG */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for CRYPTOACC_g_HashMaskFunc */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_HashMaskFunc */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ -#define CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ -#define CRYPTOACC_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for CRYPTOACC_g_HashPadding */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_HashPadding */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ -#define CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ -#define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ -#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for CRYPTOACC_g_HMAC_enabled */ -#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_HMAC_enabled */ -#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ -#define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ -#define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for CRYPTOACC_g_HashVerifyDigest*/ -#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for CRYPTOACC_g_HashVerifyDigest */ -#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ -#define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ - -/* Bit fields for CRYPTOACC BA418_HW_CFG */ -#define _CRYPTOACC_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for CRYPTOACC_BA418_HW_CFG */ -#define _CRYPTOACC_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for CRYPTOACC_BA418_HW_CFG */ -#define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ -#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for CRYPTOACC_g_Sha3CtxtEn */ -#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_Sha3CtxtEn */ -#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA418_HW_CFG */ -#define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA418_HW_CFG*/ - -/* Bit fields for CRYPTOACC BA419_HW_CFG */ -#define _CRYPTOACC_BA419_HW_CFG_RESETVALUE 0x0000005FUL /**< Default value for CRYPTOACC_BA419_HW_CFG */ -#define _CRYPTOACC_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for CRYPTOACC_BA419_HW_CFG */ -#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_SM4ModesPoss */ -#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_SM4ModesPoss */ -#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x0000005FUL /**< Mode DEFAULT for CRYPTOACC_BA419_HW_CFG */ -#define CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA419_HW_CFG*/ - -/** @} End of group EFR32BG22_CRYPTOACC_BitFields */ -/** @} End of group EFR32BG22_CRYPTOACC */ -/**************************************************************************//** - * @defgroup EFR32BG22_CRYPTOACC_PKCTRL CRYPTOACC_PKCTRL - * @{ - * @brief EFR32BG22 CRYPTOACC_PKCTRL Register Declaration. - *****************************************************************************/ - -/** CRYPTOACC_PKCTRL Register Declaration. */ -typedef struct { - __IOM uint32_t POINTER; /**< Pointers */ - __IOM uint32_t COMMAND; /**< Command */ - __IOM uint32_t PKCTRL; /**< Control */ - __IM uint32_t PKSTATUS; /**< Status */ - __IM uint32_t VERSION; /**< Version */ - __IM uint32_t TIMER; /**< Timer */ -} CRYPTOACC_PKCTRL_TypeDef; -/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_CRYPTOACC_PKCTRL - * @{ - * @defgroup EFR32BG22_CRYPTOACC_PKCTRL_BitFields CRYPTOACC_PKCTRL Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for CRYPTOACC POINTER */ -#define _CRYPTOACC_POINTER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_POINTER */ -#define _CRYPTOACC_POINTER_MASK 0x0F0F0F0FUL /**< Mask for CRYPTOACC_POINTER */ -#define _CRYPTOACC_POINTER_OPPTRA_SHIFT 0 /**< Shift value for CRYPTOACC_OPPTRA */ -#define _CRYPTOACC_POINTER_OPPTRA_MASK 0xFUL /**< Bit mask for CRYPTOACC_OPPTRA */ -#define _CRYPTOACC_POINTER_OPPTRA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ -#define CRYPTOACC_POINTER_OPPTRA_DEFAULT (_CRYPTOACC_POINTER_OPPTRA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ -#define _CRYPTOACC_POINTER_OPPTRB_SHIFT 8 /**< Shift value for CRYPTOACC_OPPTRB */ -#define _CRYPTOACC_POINTER_OPPTRB_MASK 0xF00UL /**< Bit mask for CRYPTOACC_OPPTRB */ -#define _CRYPTOACC_POINTER_OPPTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ -#define CRYPTOACC_POINTER_OPPTRB_DEFAULT (_CRYPTOACC_POINTER_OPPTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ -#define _CRYPTOACC_POINTER_OPPTRC_SHIFT 16 /**< Shift value for CRYPTOACC_OPPTRC */ -#define _CRYPTOACC_POINTER_OPPTRC_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_OPPTRC */ -#define _CRYPTOACC_POINTER_OPPTRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ -#define CRYPTOACC_POINTER_OPPTRC_DEFAULT (_CRYPTOACC_POINTER_OPPTRC_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ -#define _CRYPTOACC_POINTER_OPPTRN_SHIFT 24 /**< Shift value for CRYPTOACC_OPPTRN */ -#define _CRYPTOACC_POINTER_OPPTRN_MASK 0xF000000UL /**< Bit mask for CRYPTOACC_OPPTRN */ -#define _CRYPTOACC_POINTER_OPPTRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ -#define CRYPTOACC_POINTER_OPPTRN_DEFAULT (_CRYPTOACC_POINTER_OPPTRN_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ - -/* Bit fields for CRYPTOACC COMMAND */ -#define _CRYPTOACC_COMMAND_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_MASK 0xFC77FFFFUL /**< Mask for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_OPERATION_SHIFT 0 /**< Shift value for CRYPTOACC_OPERATION */ -#define _CRYPTOACC_COMMAND_OPERATION_MASK 0x7FUL /**< Bit mask for CRYPTOACC_OPERATION */ -#define _CRYPTOACC_COMMAND_OPERATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_OPERATION_DEFAULT (_CRYPTOACC_COMMAND_OPERATION_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FIELD (0x1UL << 7) /**< Field */ -#define _CRYPTOACC_COMMAND_FIELD_SHIFT 7 /**< Shift value for CRYPTOACC_FIELD */ -#define _CRYPTOACC_COMMAND_FIELD_MASK 0x80UL /**< Bit mask for CRYPTOACC_FIELD */ -#define _CRYPTOACC_COMMAND_FIELD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_FIELD_GFP 0x00000000UL /**< Mode GFP for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_FIELD_GF2M 0x00000001UL /**< Mode GF2M for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FIELD_DEFAULT (_CRYPTOACC_COMMAND_FIELD_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FIELD_GFP (_CRYPTOACC_COMMAND_FIELD_GFP << 7) /**< Shifted mode GFP for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FIELD_GF2M (_CRYPTOACC_COMMAND_FIELD_GF2M << 7) /**< Shifted mode GF2M for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SIZE_SHIFT 8 /**< Shift value for CRYPTOACC_SIZE */ -#define _CRYPTOACC_COMMAND_SIZE_MASK 0x7FF00UL /**< Bit mask for CRYPTOACC_SIZE */ -#define _CRYPTOACC_COMMAND_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SIZE_DEFAULT (_CRYPTOACC_COMMAND_SIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SELCURVE_SHIFT 20 /**< Shift value for CRYPTOACC_SELCURVE */ -#define _CRYPTOACC_COMMAND_SELCURVE_MASK 0x700000UL /**< Bit mask for CRYPTOACC_SELCURVE */ -#define _CRYPTOACC_COMMAND_SELCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SELCURVE_NONE 0x00000000UL /**< Mode NONE for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SELCURVE_P256 0x00000001UL /**< Mode P256 for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SELCURVE_P192 0x00000004UL /**< Mode P192 for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SELCURVE_DEFAULT (_CRYPTOACC_COMMAND_SELCURVE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SELCURVE_NONE (_CRYPTOACC_COMMAND_SELCURVE_NONE << 20) /**< Shifted mode NONE for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SELCURVE_P256 (_CRYPTOACC_COMMAND_SELCURVE_P256 << 20) /**< Shifted mode P256 for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SELCURVE_P192 (_CRYPTOACC_COMMAND_SELCURVE_P192 << 20) /**< Shifted mode P192 for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_EDWARDS (0x1UL << 26) /**< Edwards Curve Enable */ -#define _CRYPTOACC_COMMAND_EDWARDS_SHIFT 26 /**< Shift value for CRYPTOACC_EDWARDS */ -#define _CRYPTOACC_COMMAND_EDWARDS_MASK 0x4000000UL /**< Bit mask for CRYPTOACC_EDWARDS */ -#define _CRYPTOACC_COMMAND_EDWARDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_EDWARDS_DEFAULT (_CRYPTOACC_COMMAND_EDWARDS_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_BUFSEL (0x1UL << 27) /**< Buffer Select */ -#define _CRYPTOACC_COMMAND_BUFSEL_SHIFT 27 /**< Shift value for CRYPTOACC_BUFSEL */ -#define _CRYPTOACC_COMMAND_BUFSEL_MASK 0x8000000UL /**< Bit mask for CRYPTOACC_BUFSEL */ -#define _CRYPTOACC_COMMAND_BUFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_BUFSEL_MEM0 0x00000000UL /**< Mode MEM0 for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_BUFSEL_DEFAULT (_CRYPTOACC_COMMAND_BUFSEL_DEFAULT << 27) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_BUFSEL_MEM0 (_CRYPTOACC_COMMAND_BUFSEL_MEM0 << 27) /**< Shifted mode MEM0 for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SWAPBYTES (0x1UL << 28) /**< Swap bytes */ -#define _CRYPTOACC_COMMAND_SWAPBYTES_SHIFT 28 /**< Shift value for CRYPTOACC_SWAPBYTES */ -#define _CRYPTOACC_COMMAND_SWAPBYTES_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_SWAPBYTES */ -#define _CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SWAPBYTES_NATIVE 0x00000000UL /**< Mode NATIVE for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED 0x00000001UL /**< Mode SWAPPED for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT (_CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SWAPBYTES_NATIVE (_CRYPTOACC_COMMAND_SWAPBYTES_NATIVE << 28) /**< Shifted mode NATIVE for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED (_CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED << 28) /**< Shifted mode SWAPPED for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FLAGA (0x1UL << 29) /**< Flag A */ -#define _CRYPTOACC_COMMAND_FLAGA_SHIFT 29 /**< Shift value for CRYPTOACC_FLAGA */ -#define _CRYPTOACC_COMMAND_FLAGA_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_FLAGA */ -#define _CRYPTOACC_COMMAND_FLAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FLAGA_DEFAULT (_CRYPTOACC_COMMAND_FLAGA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FLAGB (0x1UL << 30) /**< Flag B */ -#define _CRYPTOACC_COMMAND_FLAGB_SHIFT 30 /**< Shift value for CRYPTOACC_FLAGB */ -#define _CRYPTOACC_COMMAND_FLAGB_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_FLAGB */ -#define _CRYPTOACC_COMMAND_FLAGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_FLAGB_DEFAULT (_CRYPTOACC_COMMAND_FLAGB_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_CALCR2 (0x1UL << 31) /**< Calculate R2 */ -#define _CRYPTOACC_COMMAND_CALCR2_SHIFT 31 /**< Shift value for CRYPTOACC_CALCR2 */ -#define _CRYPTOACC_COMMAND_CALCR2_MASK 0x80000000UL /**< Bit mask for CRYPTOACC_CALCR2 */ -#define _CRYPTOACC_COMMAND_CALCR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_CALCR2_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_COMMAND */ -#define _CRYPTOACC_COMMAND_CALCR2_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_CALCR2_DEFAULT (_CRYPTOACC_COMMAND_CALCR2_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_CALCR2_FALSE (_CRYPTOACC_COMMAND_CALCR2_FALSE << 31) /**< Shifted mode FALSE for CRYPTOACC_COMMAND */ -#define CRYPTOACC_COMMAND_CALCR2_TRUE (_CRYPTOACC_COMMAND_CALCR2_TRUE << 31) /**< Shifted mode TRUE for CRYPTOACC_COMMAND */ - -/* Bit fields for CRYPTOACC PKCTRL */ -#define _CRYPTOACC_PKCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKCTRL */ -#define _CRYPTOACC_PKCTRL_MASK 0x00000003UL /**< Mask for CRYPTOACC_PKCTRL */ -#define CRYPTOACC_PKCTRL_PKSTART (0x1UL << 0) /**< PK Start */ -#define _CRYPTOACC_PKCTRL_PKSTART_SHIFT 0 /**< Shift value for CRYPTOACC_PKSTART */ -#define _CRYPTOACC_PKCTRL_PKSTART_MASK 0x1UL /**< Bit mask for CRYPTOACC_PKSTART */ -#define _CRYPTOACC_PKCTRL_PKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ -#define CRYPTOACC_PKCTRL_PKSTART_DEFAULT (_CRYPTOACC_PKCTRL_PKSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ -#define CRYPTOACC_PKCTRL_IFC (0x1UL << 1) /**< ClearIRQ */ -#define _CRYPTOACC_PKCTRL_IFC_SHIFT 1 /**< Shift value for CRYPTOACC_IFC */ -#define _CRYPTOACC_PKCTRL_IFC_MASK 0x2UL /**< Bit mask for CRYPTOACC_IFC */ -#define _CRYPTOACC_PKCTRL_IFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ -#define CRYPTOACC_PKCTRL_IFC_DEFAULT (_CRYPTOACC_PKCTRL_IFC_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ - -/* Bit fields for CRYPTOACC PKSTATUS */ -#define _CRYPTOACC_PKSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKSTATUS */ -#define _CRYPTOACC_PKSTATUS_MASK 0x00033FFFUL /**< Mask for CRYPTOACC_PKSTATUS */ -#define _CRYPTOACC_PKSTATUS_FAILADDR_SHIFT 0 /**< Shift value for CRYPTOACC_FAILADDR */ -#define _CRYPTOACC_PKSTATUS_FAILADDR_MASK 0xFUL /**< Bit mask for CRYPTOACC_FAILADDR */ -#define _CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT (_CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTONCURVE (0x1UL << 4) /**< Point Px not on curve */ -#define _CRYPTOACC_PKSTATUS_NOTONCURVE_SHIFT 4 /**< Shift value for CRYPTOACC_NOTONCURVE */ -#define _CRYPTOACC_PKSTATUS_NOTONCURVE_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTONCURVE */ -#define _CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_ATINFINITY (0x1UL << 5) /**< Point Px at infinity */ -#define _CRYPTOACC_PKSTATUS_ATINFINITY_SHIFT 5 /**< Shift value for CRYPTOACC_ATINFINITY */ -#define _CRYPTOACC_PKSTATUS_ATINFINITY_MASK 0x20UL /**< Bit mask for CRYPTOACC_ATINFINITY */ -#define _CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT (_CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COUPLENOTVALID (0x1UL << 6) /**< Couple not valid */ -#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_SHIFT 6 /**< Shift value for CRYPTOACC_COUPLENOTVALID */ -#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_MASK 0x40UL /**< Bit mask for CRYPTOACC_COUPLENOTVALID */ -#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PARAMNNOTVALID (0x1UL << 7) /**< Param n not valid */ -#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_SHIFT 7 /**< Shift value for CRYPTOACC_PARAMNNOTVALID */ -#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_MASK 0x80UL /**< Bit mask for CRYPTOACC_PARAMNNOTVALID */ -#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED (0x1UL << 8) /**< Not implemented */ -#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_SHIFT 8 /**< Shift value for CRYPTOACC_NOTIMPLEMENTED */ -#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_MASK 0x100UL /**< Bit mask for CRYPTOACC_NOTIMPLEMENTED */ -#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT (_CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_SIGNOTVALID (0x1UL << 9) /**< Signature not valid */ -#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_SHIFT 9 /**< Shift value for CRYPTOACC_SIGNOTVALID */ -#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_MASK 0x200UL /**< Bit mask for CRYPTOACC_SIGNOTVALID */ -#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PARAMABNOTVALID (0x1UL << 10) /**< Param AB not valid */ -#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_SHIFT 10 /**< Shift value for CRYPTOACC_PARAMABNOTVALID */ -#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_MASK 0x400UL /**< Bit mask for CRYPTOACC_PARAMABNOTVALID */ -#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTINVERTIBLE (0x1UL << 11) /**< Not invertible */ -#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_SHIFT 11 /**< Shift value for CRYPTOACC_NOTINVERTIBLE */ -#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_MASK 0x800UL /**< Bit mask for CRYPTOACC_NOTINVERTIBLE */ -#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COMPOSITE (0x1UL << 12) /**< Composite */ -#define _CRYPTOACC_PKSTATUS_COMPOSITE_SHIFT 12 /**< Shift value for CRYPTOACC_COMPOSITE */ -#define _CRYPTOACC_PKSTATUS_COMPOSITE_MASK 0x1000UL /**< Bit mask for CRYPTOACC_COMPOSITE */ -#define _CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define _CRYPTOACC_PKSTATUS_COMPOSITE_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_PKSTATUS */ -#define _CRYPTOACC_PKSTATUS_COMPOSITE_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT (_CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COMPOSITE_FALSE (_CRYPTOACC_PKSTATUS_COMPOSITE_FALSE << 12) /**< Shifted mode FALSE for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_COMPOSITE_TRUE (_CRYPTOACC_PKSTATUS_COMPOSITE_TRUE << 12) /**< Shifted mode TRUE for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTQUAD (0x1UL << 13) /**< Not quadratic residue */ -#define _CRYPTOACC_PKSTATUS_NOTQUAD_SHIFT 13 /**< Shift value for CRYPTOACC_NOTQUAD */ -#define _CRYPTOACC_PKSTATUS_NOTQUAD_MASK 0x2000UL /**< Bit mask for CRYPTOACC_NOTQUAD */ -#define _CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT (_CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PKBUSY (0x1UL << 16) /**< PK busy */ -#define _CRYPTOACC_PKSTATUS_PKBUSY_SHIFT 16 /**< Shift value for CRYPTOACC_PKBUSY */ -#define _CRYPTOACC_PKSTATUS_PKBUSY_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PKBUSY */ -#define _CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT (_CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PKIF (0x1UL << 17) /**< Interrupt status */ -#define _CRYPTOACC_PKSTATUS_PKIF_SHIFT 17 /**< Shift value for CRYPTOACC_PKIF */ -#define _CRYPTOACC_PKSTATUS_PKIF_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PKIF */ -#define _CRYPTOACC_PKSTATUS_PKIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ -#define CRYPTOACC_PKSTATUS_PKIF_DEFAULT (_CRYPTOACC_PKSTATUS_PKIF_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ - -/* Bit fields for CRYPTOACC VERSION */ -#define _CRYPTOACC_VERSION_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_VERSION */ -#define _CRYPTOACC_VERSION_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_VERSION */ -#define _CRYPTOACC_VERSION_SW_SHIFT 0 /**< Shift value for CRYPTOACC_SW */ -#define _CRYPTOACC_VERSION_SW_MASK 0xFFUL /**< Bit mask for CRYPTOACC_SW */ -#define _CRYPTOACC_VERSION_SW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ -#define CRYPTOACC_VERSION_SW_DEFAULT (_CRYPTOACC_VERSION_SW_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ -#define _CRYPTOACC_VERSION_HW_SHIFT 8 /**< Shift value for CRYPTOACC_HW */ -#define _CRYPTOACC_VERSION_HW_MASK 0xFF00UL /**< Bit mask for CRYPTOACC_HW */ -#define _CRYPTOACC_VERSION_HW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ -#define CRYPTOACC_VERSION_HW_DEFAULT (_CRYPTOACC_VERSION_HW_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ - -/* Bit fields for CRYPTOACC TIMER */ -#define _CRYPTOACC_TIMER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TIMER */ -#define _CRYPTOACC_TIMER_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TIMER */ -#define _CRYPTOACC_TIMER_TIMER_SHIFT 0 /**< Shift value for CRYPTOACC_TIMER */ -#define _CRYPTOACC_TIMER_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TIMER */ -#define _CRYPTOACC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TIMER */ -#define CRYPTOACC_TIMER_TIMER_DEFAULT (_CRYPTOACC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TIMER */ - -/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL_BitFields */ -/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ -/**************************************************************************//** - * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL CRYPTOACC_RNGCTRL - * @{ - * @brief EFR32BG22 CRYPTOACC_RNGCTRL Register Declaration. - *****************************************************************************/ - -/** CRYPTOACC_RNGCTRL KEYS Register Group Declaration. */ -typedef struct { - __IOM uint32_t KEY; /**< Key Register */ -} CRYPTOACC_KEYS_TypeDef; - -/** CRYPTOACC_RNGCTRL Register Declaration. */ -typedef struct { - __IOM uint32_t RNGCTRL; /**< RNG Control Register */ - __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ - __IM uint32_t FIFOTHRESH; /**< FIFO Threshold Register */ - __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ - CRYPTOACC_KEYS_TypeDef KEYS[4U]; /**< */ - __IOM uint32_t TESTDATA; /**< Test Data Register */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t RNGSTATUS; /**< RNG Status Register */ - __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t SWOFFTMRVAL; /**< Switch off timer value */ - __IOM uint32_t CLKDIV; /**< Sample clock divider */ - __IOM uint32_t AIS31CONF0; /**< AIS31 configuration 0 register */ - __IOM uint32_t AIS31CONF1; /**< AIS31 configuration 1 register */ - __IOM uint32_t AIS31CONF2; /**< AIS31 configuration 2 register */ - __IOM uint32_t AIS31STATUS; /**< AIS31 status register */ -} CRYPTOACC_RNGCTRL_TypeDef; -/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_CRYPTOACC_RNGCTRL - * @{ - * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL_BitFields CRYPTOACC_RNGCTRL Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for CRYPTOACC RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_RESETVALUE 0x00040000UL /**< Default value for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_MASK 0x001FFFFFUL /**< Mask for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ -#define _CRYPTOACC_RNGCTRL_ENABLE_SHIFT 0 /**< Shift value for CRYPTOACC_ENABLE */ -#define _CRYPTOACC_RNGCTRL_ENABLE_MASK 0x1UL /**< Bit mask for CRYPTOACC_ENABLE */ -#define _CRYPTOACC_RNGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ENABLE_DEFAULT (_CRYPTOACC_RNGCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ENABLE_DISABLED (_CRYPTOACC_RNGCTRL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ENABLE_ENABLED (_CRYPTOACC_RNGCTRL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_TESTEN (0x1UL << 2) /**< Test Enable */ -#define _CRYPTOACC_RNGCTRL_TESTEN_SHIFT 2 /**< Shift value for CRYPTOACC_TESTEN */ -#define _CRYPTOACC_RNGCTRL_TESTEN_MASK 0x4UL /**< Bit mask for CRYPTOACC_TESTEN */ -#define _CRYPTOACC_RNGCTRL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_TESTEN_DEFAULT (_CRYPTOACC_RNGCTRL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_TESTEN_NOISE (_CRYPTOACC_RNGCTRL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_TESTEN_TESTDATA (_CRYPTOACC_RNGCTRL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ -#define _CRYPTOACC_RNGCTRL_CONDBYPASS_SHIFT 3 /**< Shift value for CRYPTOACC_CONDBYPASS */ -#define _CRYPTOACC_RNGCTRL_CONDBYPASS_MASK 0x8UL /**< Bit mask for CRYPTOACC_CONDBYPASS */ -#define _CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT (_CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL (_CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS (_CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_REPCOUNTIEN (0x1UL << 4) /**< IRQ enable for Repetition Count Test */ -#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIEN */ -#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIEN */ -#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT (_CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_APT64IEN (0x1UL << 5) /**< IRQ enable for APT64IF */ -#define _CRYPTOACC_RNGCTRL_APT64IEN_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IEN */ -#define _CRYPTOACC_RNGCTRL_APT64IEN_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IEN */ -#define _CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_APT4096IEN (0x1UL << 6) /**< IRQ enable for APT4096IF */ -#define _CRYPTOACC_RNGCTRL_APT4096IEN_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IEN */ -#define _CRYPTOACC_RNGCTRL_APT4096IEN_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IEN */ -#define _CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FULLIEN (0x1UL << 7) /**< IRQ enable for FIFO full */ -#define _CRYPTOACC_RNGCTRL_FULLIEN_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIEN */ -#define _CRYPTOACC_RNGCTRL_FULLIEN_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIEN */ -#define _CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT (_CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_SOFTRESET (0x1UL << 8) /**< Software Reset */ -#define _CRYPTOACC_RNGCTRL_SOFTRESET_SHIFT 8 /**< Shift value for CRYPTOACC_SOFTRESET */ -#define _CRYPTOACC_RNGCTRL_SOFTRESET_MASK 0x100UL /**< Bit mask for CRYPTOACC_SOFTRESET */ -#define _CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT (_CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL (_CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_SOFTRESET_RESET (_CRYPTOACC_RNGCTRL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_PREIEN (0x1UL << 9) /**< IRQ enable for AIS31 prelim. noise alarm */ -#define _CRYPTOACC_RNGCTRL_PREIEN_SHIFT 9 /**< Shift value for CRYPTOACC_PREIEN */ -#define _CRYPTOACC_RNGCTRL_PREIEN_MASK 0x200UL /**< Bit mask for CRYPTOACC_PREIEN */ -#define _CRYPTOACC_RNGCTRL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_PREIEN_DEFAULT (_CRYPTOACC_RNGCTRL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ALMIEN (0x1UL << 10) /**< IRQ enable for AIS31 noise alarm */ -#define _CRYPTOACC_RNGCTRL_ALMIEN_SHIFT 10 /**< Shift value for CRYPTOACC_ALMIEN */ -#define _CRYPTOACC_RNGCTRL_ALMIEN_MASK 0x400UL /**< Bit mask for CRYPTOACC_ALMIEN */ -#define _CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT (_CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ -#define _CRYPTOACC_RNGCTRL_FORCERUN_SHIFT 11 /**< Shift value for CRYPTOACC_FORCERUN */ -#define _CRYPTOACC_RNGCTRL_FORCERUN_MASK 0x800UL /**< Bit mask for CRYPTOACC_FORCERUN */ -#define _CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT (_CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FORCERUN_NORMAL (_CRYPTOACC_RNGCTRL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FORCERUN_RUN (_CRYPTOACC_RNGCTRL_FORCERUN_RUN << 11) /**< Shifted mode RUN for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ -#define _CRYPTOACC_RNGCTRL_BYPNIST_SHIFT 12 /**< Shift value for CRYPTOACC_BYPNIST */ -#define _CRYPTOACC_RNGCTRL_BYPNIST_MASK 0x1000UL /**< Bit mask for CRYPTOACC_BYPNIST */ -#define _CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT (_CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPNIST_NORMAL (_CRYPTOACC_RNGCTRL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPNIST_BYPASS (_CRYPTOACC_RNGCTRL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ -#define _CRYPTOACC_RNGCTRL_BYPAIS31_SHIFT 13 /**< Shift value for CRYPTOACC_BYPAIS31 */ -#define _CRYPTOACC_RNGCTRL_BYPAIS31_MASK 0x2000UL /**< Bit mask for CRYPTOACC_BYPAIS31 */ -#define _CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT (_CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL (_CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS (_CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL (0x1UL << 14) /**< Health test input select */ -#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_SHIFT 14 /**< Shift value for CRYPTOACC_HEALTHTESTSEL */ -#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_MASK 0x4000UL /**< Bit mask for CRYPTOACC_HEALTHTESTSEL */ -#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE << 14) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER << 14) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_AIS31TESTSEL (0x1UL << 15) /**< AIS31 test input select */ -#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_SHIFT 15 /**< Shift value for CRYPTOACC_AIS31TESTSEL */ -#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_MASK 0x8000UL /**< Bit mask for CRYPTOACC_AIS31TESTSEL */ -#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE << 15) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER << 15) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ -#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_SHIFT 16 /**< Shift value for CRYPTOACC_NB128BITBLOCKS */ -#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_NB128BITBLOCKS */ -#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT 0x00000004UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT (_CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP (0x1UL << 20) /**< Fifo Write Start Up */ -#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_SHIFT 20 /**< Shift value for CRYPTOACC_FIFOWRSTARTUP */ -#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_MASK 0x100000UL /**< Bit mask for CRYPTOACC_FIFOWRSTARTUP */ -#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ -#define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT (_CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ - -/* Bit fields for CRYPTOACC FIFOLEVEL */ -#define _CRYPTOACC_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FIFOLEVEL */ -#define _CRYPTOACC_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOLEVEL */ -#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOLEVEL */ -#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOLEVEL */ -#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FIFOLEVEL */ -#define CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT (_CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOLEVEL*/ - -/* Bit fields for CRYPTOACC FIFOTHRESH */ -#define _CRYPTOACC_FIFOTHRESH_RESETVALUE 0x0000003FUL /**< Default value for CRYPTOACC_FIFOTHRESH */ -#define _CRYPTOACC_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOTHRESH */ -#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOTHRESH */ -#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOTHRESH */ -#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT 0x0000003FUL /**< Mode DEFAULT for CRYPTOACC_FIFOTHRESH */ -#define CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT (_CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOTHRESH*/ - -/* Bit fields for CRYPTOACC FIFODEPTH */ -#define _CRYPTOACC_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for CRYPTOACC_FIFODEPTH */ -#define _CRYPTOACC_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFODEPTH */ -#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFODEPTH */ -#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFODEPTH */ -#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT 0x00000040UL /**< Mode DEFAULT for CRYPTOACC_FIFODEPTH */ -#define CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT (_CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFODEPTH*/ - -/* Bit fields for CRYPTOACC KEY */ -#define _CRYPTOACC_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_KEY */ -#define _CRYPTOACC_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_KEY */ -#define _CRYPTOACC_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTOACC_KEY */ -#define _CRYPTOACC_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY */ -#define _CRYPTOACC_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_KEY */ -#define CRYPTOACC_KEY_KEY_DEFAULT (_CRYPTOACC_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_KEY */ - -/* Bit fields for CRYPTOACC TESTDATA */ -#define _CRYPTOACC_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TESTDATA */ -#define _CRYPTOACC_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TESTDATA */ -#define _CRYPTOACC_TESTDATA_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ -#define _CRYPTOACC_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_VALUE */ -#define _CRYPTOACC_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TESTDATA */ -#define CRYPTOACC_TESTDATA_VALUE_DEFAULT (_CRYPTOACC_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TESTDATA */ - -/* Bit fields for CRYPTOACC RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_MASK 0x000007FFUL /**< Mask for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ -#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for CRYPTOACC_TESTDATABUSY */ -#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_TESTDATABUSY */ -#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_SHIFT 1 /**< Shift value for CRYPTOACC_STATE */ -#define _CRYPTOACC_RNGSTATUS_STATE_MASK 0xEUL /**< Bit mask for CRYPTOACC_STATE */ -#define _CRYPTOACC_RNGSTATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_RESET 0x00000000UL /**< Mode RESET for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_STARTUP 0x00000001UL /**< Mode STARTUP for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON 0x00000002UL /**< Mode FIFOFULLON for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF 0x00000003UL /**< Mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_RUNNING 0x00000004UL /**< Mode RUNNING for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_ERROR 0x00000005UL /**< Mode ERROR for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 0x00000006UL /**< Mode UNUSED_6 for CRYPTOACC_RNGSTATUS */ -#define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 0x00000007UL /**< Mode UNUSED_7 for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_STATE_DEFAULT (_CRYPTOACC_RNGSTATUS_STATE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_RESET (_CRYPTOACC_RNGSTATUS_STATE_RESET << 1) /**< Shifted mode RESET for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_STATE_STARTUP (_CRYPTOACC_RNGSTATUS_STATE_STARTUP << 1) /**< Shifted mode STARTUP for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON << 1) /**< Shifted mode FIFOFULLON for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF << 1) /**< Shifted mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_RUNNING (_CRYPTOACC_RNGSTATUS_STATE_RUNNING << 1) /**< Shifted mode RUNNING for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_ERROR (_CRYPTOACC_RNGSTATUS_STATE_ERROR << 1) /**< Shifted mode ERROR for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 << 1) /**< Shifted mode UNUSED_6 for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 << 1) /**< Shifted mode UNUSED_7 for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ -#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIF */ -#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIF */ -#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT (_CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_APT64IF (0x1UL << 5) /**< 64-sample window Adaptive Proportion IF */ -#define _CRYPTOACC_RNGSTATUS_APT64IF_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IF */ -#define _CRYPTOACC_RNGSTATUS_APT64IF_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IF */ -#define _CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_APT4096IF (0x1UL << 6) /**< 4096-sample window Adaptive Prop. IF */ -#define _CRYPTOACC_RNGSTATUS_APT4096IF_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IF */ -#define _CRYPTOACC_RNGSTATUS_APT4096IF_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IF */ -#define _CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ -#define _CRYPTOACC_RNGSTATUS_FULLIF_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIF */ -#define _CRYPTOACC_RNGSTATUS_FULLIF_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIF */ -#define _CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT (_CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm IF */ -#define _CRYPTOACC_RNGSTATUS_PREIF_SHIFT 8 /**< Shift value for CRYPTOACC_PREIF */ -#define _CRYPTOACC_RNGSTATUS_PREIF_MASK 0x100UL /**< Bit mask for CRYPTOACC_PREIF */ -#define _CRYPTOACC_RNGSTATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_PREIF_DEFAULT (_CRYPTOACC_RNGSTATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ -#define CRYPTOACC_RNGSTATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ -#define _CRYPTOACC_RNGSTATUS_ALMIF_SHIFT 9 /**< Shift value for CRYPTOACC_ALMIF */ -#define _CRYPTOACC_RNGSTATUS_ALMIF_MASK 0x200UL /**< Bit mask for CRYPTOACC_ALMIF */ -#define _CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ -#define CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT (_CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ - -/* Bit fields for CRYPTOACC INITWAITVAL */ -#define _CRYPTOACC_INITWAITVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_INITWAITVAL */ -#define _CRYPTOACC_INITWAITVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_INITWAITVAL */ -#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_SHIFT 0 /**< Shift value for CRYPTOACC_INITWAITVAL */ -#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_INITWAITVAL */ -#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_INITWAITVAL */ -#define CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT (_CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INITWAITVAL*/ - -/* Bit fields for CRYPTOACC SWOFFTMRVAL */ -#define _CRYPTOACC_SWOFFTMRVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_SWOFFTMRVAL */ -#define _CRYPTOACC_SWOFFTMRVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_SWOFFTMRVAL */ -#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_SHIFT 0 /**< Shift value for CRYPTOACC_SWOFFTMRVAL */ -#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_SWOFFTMRVAL */ -#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_SWOFFTMRVAL */ -#define CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT (_CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_SWOFFTMRVAL*/ - -/* Bit fields for CRYPTOACC CLKDIV */ -#define _CRYPTOACC_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CLKDIV */ -#define _CRYPTOACC_CLKDIV_MASK 0x000000FFUL /**< Mask for CRYPTOACC_CLKDIV */ -#define _CRYPTOACC_CLKDIV_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ -#define _CRYPTOACC_CLKDIV_VALUE_MASK 0xFFUL /**< Bit mask for CRYPTOACC_VALUE */ -#define _CRYPTOACC_CLKDIV_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CLKDIV */ -#define CRYPTOACC_CLKDIV_VALUE_DEFAULT (_CRYPTOACC_CLKDIV_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CLKDIV */ - -/* Bit fields for CRYPTOACC AIS31CONF0 */ -#define _CRYPTOACC_AIS31CONF0_RESETVALUE 0x43401040UL /**< Default value for CRYPTOACC_AIS31CONF0 */ -#define _CRYPTOACC_AIS31CONF0_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF0 */ -#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_SHIFT 0 /**< Shift value for CRYPTOACC_STARTUPTHRES */ -#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_STARTUPTHRES */ -#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT 0x00001040UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ -#define CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT (_CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ -#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINETHRESH */ -#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINETHRESH */ -#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT 0x00004340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ -#define CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT (_CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ - -/* Bit fields for CRYPTOACC AIS31CONF1 */ -#define _CRYPTOACC_AIS31CONF1_RESETVALUE 0x03C00680UL /**< Default value for CRYPTOACC_AIS31CONF1 */ -#define _CRYPTOACC_AIS31CONF1_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF1 */ -#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_SHIFT 0 /**< Shift value for CRYPTOACC_HEXPECTEDVALUE */ -#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HEXPECTEDVALUE */ -#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT 0x00000680UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ -#define CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT (_CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ -#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINEREPTHRESH */ -#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINEREPTHRESH */ -#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT 0x000003C0UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ -#define CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT (_CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ - -/* Bit fields for CRYPTOACC AIS31CONF2 */ -#define _CRYPTOACC_AIS31CONF2_RESETVALUE 0x04400340UL /**< Default value for CRYPTOACC_AIS31CONF2 */ -#define _CRYPTOACC_AIS31CONF2_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF2 */ -#define _CRYPTOACC_AIS31CONF2_HMIN_SHIFT 0 /**< Shift value for CRYPTOACC_HMIN */ -#define _CRYPTOACC_AIS31CONF2_HMIN_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HMIN */ -#define _CRYPTOACC_AIS31CONF2_HMIN_DEFAULT 0x00000340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ -#define CRYPTOACC_AIS31CONF2_HMIN_DEFAULT (_CRYPTOACC_AIS31CONF2_HMIN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ -#define _CRYPTOACC_AIS31CONF2_HMAX_SHIFT 16 /**< Shift value for CRYPTOACC_HMAX */ -#define _CRYPTOACC_AIS31CONF2_HMAX_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_HMAX */ -#define _CRYPTOACC_AIS31CONF2_HMAX_DEFAULT 0x00000440UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ -#define CRYPTOACC_AIS31CONF2_HMAX_DEFAULT (_CRYPTOACC_AIS31CONF2_HMAX_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ - -/* Bit fields for CRYPTOACC AIS31STATUS */ -#define _CRYPTOACC_AIS31STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_AIS31STATUS */ -#define _CRYPTOACC_AIS31STATUS_MASK 0x0003FFFFUL /**< Mask for CRYPTOACC_AIS31STATUS */ -#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_SHIFT 0 /**< Shift value for CRYPTOACC_NUMPRELIMALARMS */ -#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_NUMPRELIMALARMS */ -#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ -#define CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT (_CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ -#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG (0x1UL << 16) /**< Preliminary noise alarm RNG */ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_SHIFT 16 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMRNG*/ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMRNG */ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ -#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ -#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP (0x1UL << 17) /**< Preliminary noise alarm Rep */ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_SHIFT 17 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMREP*/ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMREP */ -#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ -#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ - -/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL_BitFields */ -/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ -/** @} End of group Parts */ - -#endif // EFR32BG22_CRYPTOACC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 CRYPTOACC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_CRYPTOACC_H +#define EFR32BG22_CRYPTOACC_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_CRYPTOACC CRYPTOACC + * @{ + * @brief EFR32BG22 CRYPTOACC Register Declaration. + *****************************************************************************/ + +/** CRYPTOACC Register Declaration. */ +typedef struct { + __IOM uint32_t FETCHADDR; /**< Fetcher Address */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t FETCHLEN; /**< Fetcher Length */ + __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ + __IOM uint32_t PUSHADDR; /**< Pusher Address */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t PUSHLEN; /**< Pusher Length */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IM uint32_t IF; /**< Interrupt Flags */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt status clear */ + __IOM uint32_t CTRL; /**< Control register */ + __IOM uint32_t CMD; /**< Command register */ + __IM uint32_t STATUS; /**< Status register */ + uint32_t RESERVED4[240U]; /**< Reserved for future use */ + __IM uint32_t INCL_IPS_HW_CFG; /**< General CRYPTOACC Hardware Configuration */ + __IM uint32_t BA411E_HW_CFG_1; /**< BA411E Hardware Configuration 1 */ + __IM uint32_t BA411E_HW_CFG_2; /**< BA411E Hardware Configuration 2 */ + __IM uint32_t BA413_HW_CFG; /**< BA413 Hardware Configuration */ + __IM uint32_t BA418_HW_CFG; /**< BA418 Hardware Configuration */ + __IM uint32_t BA419_HW_CFG; /**< BA419 Hardware Configuration */ +} CRYPTOACC_TypeDef; +/** @} End of group EFR32BG22_CRYPTOACC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_CRYPTOACC + * @{ + * @defgroup EFR32BG22_CRYPTOACC_BitFields CRYPTOACC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTOACC FETCHADDR */ +#define _CRYPTOACC_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHADDR */ +#define _CRYPTOACC_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHADDR */ +#define _CRYPTOACC_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ +#define _CRYPTOACC_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ +#define _CRYPTOACC_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHADDR */ +#define CRYPTOACC_FETCHADDR_ADDR_DEFAULT (_CRYPTOACC_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHADDR*/ + +/* Bit fields for CRYPTOACC FETCHLEN */ +#define _CRYPTOACC_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHLEN */ +#define _CRYPTOACC_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for CRYPTOACC_FETCHLEN */ +#define _CRYPTOACC_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ +#define _CRYPTOACC_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ +#define _CRYPTOACC_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ +#define CRYPTOACC_FETCHLEN_LENGTH_DEFAULT (_CRYPTOACC_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ +#define CRYPTOACC_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _CRYPTOACC_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ +#define _CRYPTOACC_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ +#define _CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ +#define CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ +#define CRYPTOACC_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _CRYPTOACC_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ +#define _CRYPTOACC_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ +#define _CRYPTOACC_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHLEN */ +#define CRYPTOACC_FETCHLEN_REALIGN_DEFAULT (_CRYPTOACC_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHLEN */ + +/* Bit fields for CRYPTOACC FETCHTAG */ +#define _CRYPTOACC_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FETCHTAG */ +#define _CRYPTOACC_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FETCHTAG */ +#define _CRYPTOACC_FETCHTAG_TAG_SHIFT 0 /**< Shift value for CRYPTOACC_TAG */ +#define _CRYPTOACC_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TAG */ +#define _CRYPTOACC_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FETCHTAG */ +#define CRYPTOACC_FETCHTAG_TAG_DEFAULT (_CRYPTOACC_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FETCHTAG */ + +/* Bit fields for CRYPTOACC PUSHADDR */ +#define _CRYPTOACC_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHADDR */ +#define _CRYPTOACC_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_PUSHADDR */ +#define _CRYPTOACC_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for CRYPTOACC_ADDR */ +#define _CRYPTOACC_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_ADDR */ +#define _CRYPTOACC_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHADDR */ +#define CRYPTOACC_PUSHADDR_ADDR_DEFAULT (_CRYPTOACC_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHADDR */ + +/* Bit fields for CRYPTOACC PUSHLEN */ +#define _CRYPTOACC_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PUSHLEN */ +#define _CRYPTOACC_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for CRYPTOACC_PUSHLEN */ +#define _CRYPTOACC_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for CRYPTOACC_LENGTH */ +#define _CRYPTOACC_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for CRYPTOACC_LENGTH */ +#define _CRYPTOACC_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_LENGTH_DEFAULT (_CRYPTOACC_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ +#define _CRYPTOACC_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for CRYPTOACC_CONSTADDR */ +#define _CRYPTOACC_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_CONSTADDR */ +#define _CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT (_CRYPTOACC_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ +#define _CRYPTOACC_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for CRYPTOACC_REALIGN */ +#define _CRYPTOACC_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_REALIGN */ +#define _CRYPTOACC_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_REALIGN_DEFAULT (_CRYPTOACC_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ +#define _CRYPTOACC_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for CRYPTOACC_DISCARD */ +#define _CRYPTOACC_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_DISCARD */ +#define _CRYPTOACC_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PUSHLEN */ +#define CRYPTOACC_PUSHLEN_DISCARD_DEFAULT (_CRYPTOACC_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_PUSHLEN */ + +/* Bit fields for CRYPTOACC IEN */ +#define _CRYPTOACC_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IEN */ +#define _CRYPTOACC_IEN_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ +#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ +#define _CRYPTOACC_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ +#define _CRYPTOACC_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_FETCHERERROR_DEFAULT (_CRYPTOACC_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ +#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ +#define _CRYPTOACC_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ +#define _CRYPTOACC_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IEN */ +#define CRYPTOACC_IEN_PUSHERERROR_DEFAULT (_CRYPTOACC_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IEN */ + +/* Bit fields for CRYPTOACC IF */ +#define _CRYPTOACC_IF_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF */ +#define _CRYPTOACC_IF_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ +#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ +#define _CRYPTOACC_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ +#define _CRYPTOACC_IF_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ +#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ +#define _CRYPTOACC_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ +#define _CRYPTOACC_IF_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF */ +#define CRYPTOACC_IF_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF */ + +/* Bit fields for CRYPTOACC IF_CLR */ +#define _CRYPTOACC_IF_CLR_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_IF_CLR */ +#define _CRYPTOACC_IF_CLR_MASK 0x0000003FUL /**< Mask for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERENDOFBLOCK */ +#define _CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_SHIFT 1 /**< Shift value for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for CRYPTOACC_FETCHERSTOPPED */ +#define _CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_FETCHERERROR_SHIFT 2 /**< Shift value for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IF_CLR_FETCHERERROR_MASK 0x4UL /**< Bit mask for CRYPTOACC_FETCHERERROR */ +#define _CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for CRYPTOACC_PUSHERENDOFBLOCK */ +#define _CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_SHIFT 4 /**< Shift value for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for CRYPTOACC_PUSHERSTOPPED */ +#define _CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag clear */ +#define _CRYPTOACC_IF_CLR_PUSHERERROR_SHIFT 5 /**< Shift value for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IF_CLR_PUSHERERROR_MASK 0x20UL /**< Bit mask for CRYPTOACC_PUSHERERROR */ +#define _CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_IF_CLR */ +#define CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT (_CRYPTOACC_IF_CLR_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_IF_CLR */ + +/* Bit fields for CRYPTOACC CTRL */ +#define _CRYPTOACC_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CTRL */ +#define _CRYPTOACC_CTRL_MASK 0x0000001FUL /**< Mask for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ +#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERSCATTERGATHER*/ +#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERSCATTERGATHER */ +#define _CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ +#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERSCATTERGATHER*/ +#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERSCATTERGATHER */ +#define _CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT (_CRYPTOACC_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ +#define _CRYPTOACC_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for CRYPTOACC_STOPFETCHER */ +#define _CRYPTOACC_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for CRYPTOACC_STOPFETCHER */ +#define _CRYPTOACC_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_STOPFETCHER_DEFAULT (_CRYPTOACC_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ +#define _CRYPTOACC_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for CRYPTOACC_STOPPUSHER */ +#define _CRYPTOACC_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for CRYPTOACC_STOPPUSHER */ +#define _CRYPTOACC_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_STOPPUSHER_DEFAULT (_CRYPTOACC_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ +#define _CRYPTOACC_CTRL_SWRESET_SHIFT 4 /**< Shift value for CRYPTOACC_SWRESET */ +#define _CRYPTOACC_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for CRYPTOACC_SWRESET */ +#define _CRYPTOACC_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CTRL */ +#define CRYPTOACC_CTRL_SWRESET_DEFAULT (_CRYPTOACC_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_CTRL */ + +/* Bit fields for CRYPTOACC CMD */ +#define _CRYPTOACC_CMD_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CMD */ +#define _CRYPTOACC_CMD_MASK 0x00000003UL /**< Mask for CRYPTOACC_CMD */ +#define CRYPTOACC_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ +#define _CRYPTOACC_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for CRYPTOACC_STARTFETCHER */ +#define _CRYPTOACC_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for CRYPTOACC_STARTFETCHER */ +#define _CRYPTOACC_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ +#define CRYPTOACC_CMD_STARTFETCHER_DEFAULT (_CRYPTOACC_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ +#define CRYPTOACC_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ +#define _CRYPTOACC_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for CRYPTOACC_STARTPUSHER */ +#define _CRYPTOACC_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for CRYPTOACC_STARTPUSHER */ +#define _CRYPTOACC_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CMD */ +#define CRYPTOACC_CMD_STARTPUSHER_DEFAULT (_CRYPTOACC_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_CMD */ + +/* Bit fields for CRYPTOACC STATUS */ +#define _CRYPTOACC_STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_STATUS */ +#define _CRYPTOACC_STATUS_MASK 0xFFFF0073UL /**< Mask for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ +#define _CRYPTOACC_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for CRYPTOACC_FETCHERBSY */ +#define _CRYPTOACC_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_FETCHERBSY */ +#define _CRYPTOACC_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_FETCHERBSY_DEFAULT (_CRYPTOACC_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ +#define _CRYPTOACC_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for CRYPTOACC_PUSHERBSY */ +#define _CRYPTOACC_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for CRYPTOACC_PUSHERBSY */ +#define _CRYPTOACC_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_PUSHERBSY_DEFAULT (_CRYPTOACC_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ +#define _CRYPTOACC_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for CRYPTOACC_NOTEMPTY */ +#define _CRYPTOACC_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTEMPTY */ +#define _CRYPTOACC_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_NOTEMPTY_DEFAULT (_CRYPTOACC_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ +#define _CRYPTOACC_STATUS_WAITING_SHIFT 5 /**< Shift value for CRYPTOACC_WAITING */ +#define _CRYPTOACC_STATUS_WAITING_MASK 0x20UL /**< Bit mask for CRYPTOACC_WAITING */ +#define _CRYPTOACC_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_WAITING_DEFAULT (_CRYPTOACC_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ +#define _CRYPTOACC_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for CRYPTOACC_SOFTRSTBSY */ +#define _CRYPTOACC_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for CRYPTOACC_SOFTRSTBSY */ +#define _CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT (_CRYPTOACC_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ +#define _CRYPTOACC_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for CRYPTOACC_FIFODATANUM */ +#define _CRYPTOACC_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for CRYPTOACC_FIFODATANUM */ +#define _CRYPTOACC_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_STATUS */ +#define CRYPTOACC_STATUS_FIFODATANUM_DEFAULT (_CRYPTOACC_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_STATUS */ + +/* Bit fields for CRYPTOACC INCL_IPS_HW_CFG */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_RESETVALUE 0x00000611UL /**< Default value for CRYPTOACC_INCL_IPS_HW_CFG */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_MASK 0x000007FFUL /**< Mask for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES (0x1UL << 0) /**< Generic g_IncludeAES value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_SHIFT 0 /**< Shift value for CRYPTOACC_g_IncludeAES */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_IncludeAES */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM (0x1UL << 1) /**< Generic g_IncludeAESGCM value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_SHIFT 1 /**< Shift value for CRYPTOACC_g_IncludeAESGCM */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_MASK 0x2UL /**< Bit mask for CRYPTOACC_g_IncludeAESGCM */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESGCM_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS (0x1UL << 2) /**< Generic g_IncludeAESXTS value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_SHIFT 2 /**< Shift value for CRYPTOACC_g_IncludeAESXTS */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_MASK 0x4UL /**< Bit mask for CRYPTOACC_g_IncludeAESXTS */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeAESXTS_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES (0x1UL << 3) /**< Generic g_IncludeDES value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_SHIFT 3 /**< Shift value for CRYPTOACC_g_IncludeDES */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_MASK 0x8UL /**< Bit mask for CRYPTOACC_g_IncludeDES */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeDES_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH (0x1UL << 4) /**< Generic g_IncludeHASH value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_SHIFT 4 /**< Shift value for CRYPTOACC_g_IncludeHASH */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_MASK 0x10UL /**< Bit mask for CRYPTOACC_g_IncludeHASH */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeHASH_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly (0x1UL << 5) /**< Generic g_IncludeChachaPoly value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_SHIFT 5 /**< Shift value for CRYPTOACC_g_IncludeChachaPoly*/ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_MASK 0x20UL /**< Bit mask for CRYPTOACC_g_IncludeChachaPoly */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeChachaPoly_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3 (0x1UL << 6) /**< Generic g_IncludeSHA3 value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_SHIFT 6 /**< Shift value for CRYPTOACC_g_IncludeSHA3 */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_MASK 0x40UL /**< Bit mask for CRYPTOACC_g_IncludeSHA3 */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSHA3_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC (0x1UL << 7) /**< Generic g_IncludeZUC value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_SHIFT 7 /**< Shift value for CRYPTOACC_g_IncludeZUC */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_MASK 0x80UL /**< Bit mask for CRYPTOACC_g_IncludeZUC */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeZUC_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4 (0x1UL << 8) /**< Generic g_IncludeSM4 value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_SHIFT 8 /**< Shift value for CRYPTOACC_g_IncludeSM4 */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_MASK 0x100UL /**< Bit mask for CRYPTOACC_g_IncludeSM4 */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeSM4_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE (0x1UL << 9) /**< Generic g_IncludePKE value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_SHIFT 9 /**< Shift value for CRYPTOACC_g_IncludePKE */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_MASK 0x200UL /**< Bit mask for CRYPTOACC_g_IncludePKE */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludePKE_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG (0x1UL << 10) /**< Generic g_IncludeNDRNG value */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_SHIFT 10 /**< Shift value for CRYPTOACC_g_IncludeNDRNG */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_MASK 0x400UL /**< Bit mask for CRYPTOACC_g_IncludeNDRNG */ +#define _CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG */ +#define CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT (_CRYPTOACC_INCL_IPS_HW_CFG_g_IncludeNDRNG_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_INCL_IPS_HW_CFG*/ + +/* Bit fields for CRYPTOACC BA411E_HW_CFG_1 */ +#define _CRYPTOACC_BA411E_HW_CFG_1_RESETVALUE 0x0700017FUL /**< Default value for CRYPTOACC_BA411E_HW_CFG_1 */ +#define _CRYPTOACC_BA411E_HW_CFG_1_MASK 0x070301FFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_1 */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_AesModesPoss */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_MASK 0x1FFUL /**< Bit mask for CRYPTOACC_g_AesModesPoss */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT 0x0000017FUL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ +#define CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_AesModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ +#define CRYPTOACC_BA411E_HW_CFG_1_g_CS (0x1UL << 16) /**< Generic g_CS value */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_SHIFT 16 /**< Shift value for CRYPTOACC_g_CS */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_CS */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ +#define CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_CS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ +#define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking (0x1UL << 17) /**< Generic g_UseMasking value */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_SHIFT 17 /**< Shift value for CRYPTOACC_g_UseMasking */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_UseMasking */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ +#define CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_UseMasking_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_SHIFT 24 /**< Shift value for CRYPTOACC_g_Keysize */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_MASK 0x7000000UL /**< Bit mask for CRYPTOACC_g_Keysize */ +#define _CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT 0x00000007UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1 */ +#define CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_1_g_Keysize_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_1*/ + +/* Bit fields for CRYPTOACC BA411E_HW_CFG_2 */ +#define _CRYPTOACC_BA411E_HW_CFG_2_RESETVALUE 0x00000080UL /**< Default value for CRYPTOACC_BA411E_HW_CFG_2 */ +#define _CRYPTOACC_BA411E_HW_CFG_2_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_BA411E_HW_CFG_2 */ +#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_SHIFT 0 /**< Shift value for CRYPTOACC_g_CtrSize */ +#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_g_CtrSize */ +#define _CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT 0x00000080UL /**< Mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2 */ +#define CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT (_CRYPTOACC_BA411E_HW_CFG_2_g_CtrSize_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA411E_HW_CFG_2*/ + +/* Bit fields for CRYPTOACC BA413_HW_CFG */ +#define _CRYPTOACC_BA413_HW_CFG_RESETVALUE 0x0003007FUL /**< Default value for CRYPTOACC_BA413_HW_CFG */ +#define _CRYPTOACC_BA413_HW_CFG_MASK 0x0007007FUL /**< Mask for CRYPTOACC_BA413_HW_CFG */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_SHIFT 0 /**< Shift value for CRYPTOACC_g_HashMaskFunc */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_HashMaskFunc */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT 0x0000007FUL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ +#define CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashMaskFunc_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ +#define CRYPTOACC_BA413_HW_CFG_g_HashPadding (0x1UL << 16) /**< Generic g_HashPadding value */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_SHIFT 16 /**< Shift value for CRYPTOACC_g_HashPadding */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_MASK 0x10000UL /**< Bit mask for CRYPTOACC_g_HashPadding */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ +#define CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashPadding_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ +#define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled (0x1UL << 17) /**< Generic g_HMAC_enabled value */ +#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_SHIFT 17 /**< Shift value for CRYPTOACC_g_HMAC_enabled */ +#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_MASK 0x20000UL /**< Bit mask for CRYPTOACC_g_HMAC_enabled */ +#define _CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ +#define CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HMAC_enabled_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ +#define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest (0x1UL << 18) /**< Generic g_HashVerifyDigest value */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_SHIFT 18 /**< Shift value for CRYPTOACC_g_HashVerifyDigest*/ +#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_MASK 0x40000UL /**< Bit mask for CRYPTOACC_g_HashVerifyDigest */ +#define _CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_BA413_HW_CFG */ +#define CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT (_CRYPTOACC_BA413_HW_CFG_g_HashVerifyDigest_DEFAULT << 18) /**< Shifted mode DEFAULT for CRYPTOACC_BA413_HW_CFG*/ + +/* Bit fields for CRYPTOACC BA418_HW_CFG */ +#define _CRYPTOACC_BA418_HW_CFG_RESETVALUE 0x00000001UL /**< Default value for CRYPTOACC_BA418_HW_CFG */ +#define _CRYPTOACC_BA418_HW_CFG_MASK 0x00000001UL /**< Mask for CRYPTOACC_BA418_HW_CFG */ +#define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn (0x1UL << 0) /**< Generic g_Sha3CtxtEn value */ +#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_SHIFT 0 /**< Shift value for CRYPTOACC_g_Sha3CtxtEn */ +#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_MASK 0x1UL /**< Bit mask for CRYPTOACC_g_Sha3CtxtEn */ +#define _CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT 0x00000001UL /**< Mode DEFAULT for CRYPTOACC_BA418_HW_CFG */ +#define CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT (_CRYPTOACC_BA418_HW_CFG_g_Sha3CtxtEn_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA418_HW_CFG*/ + +/* Bit fields for CRYPTOACC BA419_HW_CFG */ +#define _CRYPTOACC_BA419_HW_CFG_RESETVALUE 0x0000005FUL /**< Default value for CRYPTOACC_BA419_HW_CFG */ +#define _CRYPTOACC_BA419_HW_CFG_MASK 0x0000007FUL /**< Mask for CRYPTOACC_BA419_HW_CFG */ +#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_SHIFT 0 /**< Shift value for CRYPTOACC_g_SM4ModesPoss */ +#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_MASK 0x7FUL /**< Bit mask for CRYPTOACC_g_SM4ModesPoss */ +#define _CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT 0x0000005FUL /**< Mode DEFAULT for CRYPTOACC_BA419_HW_CFG */ +#define CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT (_CRYPTOACC_BA419_HW_CFG_g_SM4ModesPoss_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_BA419_HW_CFG*/ + +/** @} End of group EFR32BG22_CRYPTOACC_BitFields */ +/** @} End of group EFR32BG22_CRYPTOACC */ +/**************************************************************************//** + * @defgroup EFR32BG22_CRYPTOACC_PKCTRL CRYPTOACC_PKCTRL + * @{ + * @brief EFR32BG22 CRYPTOACC_PKCTRL Register Declaration. + *****************************************************************************/ + +/** CRYPTOACC_PKCTRL Register Declaration. */ +typedef struct { + __IOM uint32_t POINTER; /**< Pointers */ + __IOM uint32_t COMMAND; /**< Command */ + __IOM uint32_t PKCTRL; /**< Control */ + __IM uint32_t PKSTATUS; /**< Status */ + __IM uint32_t VERSION; /**< Version */ + __IM uint32_t TIMER; /**< Timer */ +} CRYPTOACC_PKCTRL_TypeDef; +/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_CRYPTOACC_PKCTRL + * @{ + * @defgroup EFR32BG22_CRYPTOACC_PKCTRL_BitFields CRYPTOACC_PKCTRL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTOACC POINTER */ +#define _CRYPTOACC_POINTER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_POINTER */ +#define _CRYPTOACC_POINTER_MASK 0x0F0F0F0FUL /**< Mask for CRYPTOACC_POINTER */ +#define _CRYPTOACC_POINTER_OPPTRA_SHIFT 0 /**< Shift value for CRYPTOACC_OPPTRA */ +#define _CRYPTOACC_POINTER_OPPTRA_MASK 0xFUL /**< Bit mask for CRYPTOACC_OPPTRA */ +#define _CRYPTOACC_POINTER_OPPTRA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ +#define CRYPTOACC_POINTER_OPPTRA_DEFAULT (_CRYPTOACC_POINTER_OPPTRA_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ +#define _CRYPTOACC_POINTER_OPPTRB_SHIFT 8 /**< Shift value for CRYPTOACC_OPPTRB */ +#define _CRYPTOACC_POINTER_OPPTRB_MASK 0xF00UL /**< Bit mask for CRYPTOACC_OPPTRB */ +#define _CRYPTOACC_POINTER_OPPTRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ +#define CRYPTOACC_POINTER_OPPTRB_DEFAULT (_CRYPTOACC_POINTER_OPPTRB_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ +#define _CRYPTOACC_POINTER_OPPTRC_SHIFT 16 /**< Shift value for CRYPTOACC_OPPTRC */ +#define _CRYPTOACC_POINTER_OPPTRC_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_OPPTRC */ +#define _CRYPTOACC_POINTER_OPPTRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ +#define CRYPTOACC_POINTER_OPPTRC_DEFAULT (_CRYPTOACC_POINTER_OPPTRC_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ +#define _CRYPTOACC_POINTER_OPPTRN_SHIFT 24 /**< Shift value for CRYPTOACC_OPPTRN */ +#define _CRYPTOACC_POINTER_OPPTRN_MASK 0xF000000UL /**< Bit mask for CRYPTOACC_OPPTRN */ +#define _CRYPTOACC_POINTER_OPPTRN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_POINTER */ +#define CRYPTOACC_POINTER_OPPTRN_DEFAULT (_CRYPTOACC_POINTER_OPPTRN_DEFAULT << 24) /**< Shifted mode DEFAULT for CRYPTOACC_POINTER */ + +/* Bit fields for CRYPTOACC COMMAND */ +#define _CRYPTOACC_COMMAND_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_MASK 0xFC77FFFFUL /**< Mask for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_OPERATION_SHIFT 0 /**< Shift value for CRYPTOACC_OPERATION */ +#define _CRYPTOACC_COMMAND_OPERATION_MASK 0x7FUL /**< Bit mask for CRYPTOACC_OPERATION */ +#define _CRYPTOACC_COMMAND_OPERATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_OPERATION_DEFAULT (_CRYPTOACC_COMMAND_OPERATION_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FIELD (0x1UL << 7) /**< Field */ +#define _CRYPTOACC_COMMAND_FIELD_SHIFT 7 /**< Shift value for CRYPTOACC_FIELD */ +#define _CRYPTOACC_COMMAND_FIELD_MASK 0x80UL /**< Bit mask for CRYPTOACC_FIELD */ +#define _CRYPTOACC_COMMAND_FIELD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_FIELD_GFP 0x00000000UL /**< Mode GFP for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_FIELD_GF2M 0x00000001UL /**< Mode GF2M for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FIELD_DEFAULT (_CRYPTOACC_COMMAND_FIELD_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FIELD_GFP (_CRYPTOACC_COMMAND_FIELD_GFP << 7) /**< Shifted mode GFP for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FIELD_GF2M (_CRYPTOACC_COMMAND_FIELD_GF2M << 7) /**< Shifted mode GF2M for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SIZE_SHIFT 8 /**< Shift value for CRYPTOACC_SIZE */ +#define _CRYPTOACC_COMMAND_SIZE_MASK 0x7FF00UL /**< Bit mask for CRYPTOACC_SIZE */ +#define _CRYPTOACC_COMMAND_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SIZE_DEFAULT (_CRYPTOACC_COMMAND_SIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SELCURVE_SHIFT 20 /**< Shift value for CRYPTOACC_SELCURVE */ +#define _CRYPTOACC_COMMAND_SELCURVE_MASK 0x700000UL /**< Bit mask for CRYPTOACC_SELCURVE */ +#define _CRYPTOACC_COMMAND_SELCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SELCURVE_NONE 0x00000000UL /**< Mode NONE for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SELCURVE_P256 0x00000001UL /**< Mode P256 for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SELCURVE_P192 0x00000004UL /**< Mode P192 for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SELCURVE_DEFAULT (_CRYPTOACC_COMMAND_SELCURVE_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SELCURVE_NONE (_CRYPTOACC_COMMAND_SELCURVE_NONE << 20) /**< Shifted mode NONE for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SELCURVE_P256 (_CRYPTOACC_COMMAND_SELCURVE_P256 << 20) /**< Shifted mode P256 for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SELCURVE_P192 (_CRYPTOACC_COMMAND_SELCURVE_P192 << 20) /**< Shifted mode P192 for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_EDWARDS (0x1UL << 26) /**< Edwards Curve Enable */ +#define _CRYPTOACC_COMMAND_EDWARDS_SHIFT 26 /**< Shift value for CRYPTOACC_EDWARDS */ +#define _CRYPTOACC_COMMAND_EDWARDS_MASK 0x4000000UL /**< Bit mask for CRYPTOACC_EDWARDS */ +#define _CRYPTOACC_COMMAND_EDWARDS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_EDWARDS_DEFAULT (_CRYPTOACC_COMMAND_EDWARDS_DEFAULT << 26) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_BUFSEL (0x1UL << 27) /**< Buffer Select */ +#define _CRYPTOACC_COMMAND_BUFSEL_SHIFT 27 /**< Shift value for CRYPTOACC_BUFSEL */ +#define _CRYPTOACC_COMMAND_BUFSEL_MASK 0x8000000UL /**< Bit mask for CRYPTOACC_BUFSEL */ +#define _CRYPTOACC_COMMAND_BUFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_BUFSEL_MEM0 0x00000000UL /**< Mode MEM0 for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_BUFSEL_DEFAULT (_CRYPTOACC_COMMAND_BUFSEL_DEFAULT << 27) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_BUFSEL_MEM0 (_CRYPTOACC_COMMAND_BUFSEL_MEM0 << 27) /**< Shifted mode MEM0 for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SWAPBYTES (0x1UL << 28) /**< Swap bytes */ +#define _CRYPTOACC_COMMAND_SWAPBYTES_SHIFT 28 /**< Shift value for CRYPTOACC_SWAPBYTES */ +#define _CRYPTOACC_COMMAND_SWAPBYTES_MASK 0x10000000UL /**< Bit mask for CRYPTOACC_SWAPBYTES */ +#define _CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SWAPBYTES_NATIVE 0x00000000UL /**< Mode NATIVE for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED 0x00000001UL /**< Mode SWAPPED for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT (_CRYPTOACC_COMMAND_SWAPBYTES_DEFAULT << 28) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SWAPBYTES_NATIVE (_CRYPTOACC_COMMAND_SWAPBYTES_NATIVE << 28) /**< Shifted mode NATIVE for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED (_CRYPTOACC_COMMAND_SWAPBYTES_SWAPPED << 28) /**< Shifted mode SWAPPED for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FLAGA (0x1UL << 29) /**< Flag A */ +#define _CRYPTOACC_COMMAND_FLAGA_SHIFT 29 /**< Shift value for CRYPTOACC_FLAGA */ +#define _CRYPTOACC_COMMAND_FLAGA_MASK 0x20000000UL /**< Bit mask for CRYPTOACC_FLAGA */ +#define _CRYPTOACC_COMMAND_FLAGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FLAGA_DEFAULT (_CRYPTOACC_COMMAND_FLAGA_DEFAULT << 29) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FLAGB (0x1UL << 30) /**< Flag B */ +#define _CRYPTOACC_COMMAND_FLAGB_SHIFT 30 /**< Shift value for CRYPTOACC_FLAGB */ +#define _CRYPTOACC_COMMAND_FLAGB_MASK 0x40000000UL /**< Bit mask for CRYPTOACC_FLAGB */ +#define _CRYPTOACC_COMMAND_FLAGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_FLAGB_DEFAULT (_CRYPTOACC_COMMAND_FLAGB_DEFAULT << 30) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_CALCR2 (0x1UL << 31) /**< Calculate R2 */ +#define _CRYPTOACC_COMMAND_CALCR2_SHIFT 31 /**< Shift value for CRYPTOACC_CALCR2 */ +#define _CRYPTOACC_COMMAND_CALCR2_MASK 0x80000000UL /**< Bit mask for CRYPTOACC_CALCR2 */ +#define _CRYPTOACC_COMMAND_CALCR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_CALCR2_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_COMMAND */ +#define _CRYPTOACC_COMMAND_CALCR2_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_CALCR2_DEFAULT (_CRYPTOACC_COMMAND_CALCR2_DEFAULT << 31) /**< Shifted mode DEFAULT for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_CALCR2_FALSE (_CRYPTOACC_COMMAND_CALCR2_FALSE << 31) /**< Shifted mode FALSE for CRYPTOACC_COMMAND */ +#define CRYPTOACC_COMMAND_CALCR2_TRUE (_CRYPTOACC_COMMAND_CALCR2_TRUE << 31) /**< Shifted mode TRUE for CRYPTOACC_COMMAND */ + +/* Bit fields for CRYPTOACC PKCTRL */ +#define _CRYPTOACC_PKCTRL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKCTRL */ +#define _CRYPTOACC_PKCTRL_MASK 0x00000003UL /**< Mask for CRYPTOACC_PKCTRL */ +#define CRYPTOACC_PKCTRL_PKSTART (0x1UL << 0) /**< PK Start */ +#define _CRYPTOACC_PKCTRL_PKSTART_SHIFT 0 /**< Shift value for CRYPTOACC_PKSTART */ +#define _CRYPTOACC_PKCTRL_PKSTART_MASK 0x1UL /**< Bit mask for CRYPTOACC_PKSTART */ +#define _CRYPTOACC_PKCTRL_PKSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ +#define CRYPTOACC_PKCTRL_PKSTART_DEFAULT (_CRYPTOACC_PKCTRL_PKSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ +#define CRYPTOACC_PKCTRL_IFC (0x1UL << 1) /**< ClearIRQ */ +#define _CRYPTOACC_PKCTRL_IFC_SHIFT 1 /**< Shift value for CRYPTOACC_IFC */ +#define _CRYPTOACC_PKCTRL_IFC_MASK 0x2UL /**< Bit mask for CRYPTOACC_IFC */ +#define _CRYPTOACC_PKCTRL_IFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKCTRL */ +#define CRYPTOACC_PKCTRL_IFC_DEFAULT (_CRYPTOACC_PKCTRL_IFC_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_PKCTRL */ + +/* Bit fields for CRYPTOACC PKSTATUS */ +#define _CRYPTOACC_PKSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_PKSTATUS */ +#define _CRYPTOACC_PKSTATUS_MASK 0x00033FFFUL /**< Mask for CRYPTOACC_PKSTATUS */ +#define _CRYPTOACC_PKSTATUS_FAILADDR_SHIFT 0 /**< Shift value for CRYPTOACC_FAILADDR */ +#define _CRYPTOACC_PKSTATUS_FAILADDR_MASK 0xFUL /**< Bit mask for CRYPTOACC_FAILADDR */ +#define _CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT (_CRYPTOACC_PKSTATUS_FAILADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTONCURVE (0x1UL << 4) /**< Point Px not on curve */ +#define _CRYPTOACC_PKSTATUS_NOTONCURVE_SHIFT 4 /**< Shift value for CRYPTOACC_NOTONCURVE */ +#define _CRYPTOACC_PKSTATUS_NOTONCURVE_MASK 0x10UL /**< Bit mask for CRYPTOACC_NOTONCURVE */ +#define _CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTONCURVE_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_ATINFINITY (0x1UL << 5) /**< Point Px at infinity */ +#define _CRYPTOACC_PKSTATUS_ATINFINITY_SHIFT 5 /**< Shift value for CRYPTOACC_ATINFINITY */ +#define _CRYPTOACC_PKSTATUS_ATINFINITY_MASK 0x20UL /**< Bit mask for CRYPTOACC_ATINFINITY */ +#define _CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT (_CRYPTOACC_PKSTATUS_ATINFINITY_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COUPLENOTVALID (0x1UL << 6) /**< Couple not valid */ +#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_SHIFT 6 /**< Shift value for CRYPTOACC_COUPLENOTVALID */ +#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_MASK 0x40UL /**< Bit mask for CRYPTOACC_COUPLENOTVALID */ +#define _CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_COUPLENOTVALID_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PARAMNNOTVALID (0x1UL << 7) /**< Param n not valid */ +#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_SHIFT 7 /**< Shift value for CRYPTOACC_PARAMNNOTVALID */ +#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_MASK 0x80UL /**< Bit mask for CRYPTOACC_PARAMNNOTVALID */ +#define _CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMNNOTVALID_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED (0x1UL << 8) /**< Not implemented */ +#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_SHIFT 8 /**< Shift value for CRYPTOACC_NOTIMPLEMENTED */ +#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_MASK 0x100UL /**< Bit mask for CRYPTOACC_NOTIMPLEMENTED */ +#define _CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT (_CRYPTOACC_PKSTATUS_NOTIMPLEMENTED_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_SIGNOTVALID (0x1UL << 9) /**< Signature not valid */ +#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_SHIFT 9 /**< Shift value for CRYPTOACC_SIGNOTVALID */ +#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_MASK 0x200UL /**< Bit mask for CRYPTOACC_SIGNOTVALID */ +#define _CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_SIGNOTVALID_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PARAMABNOTVALID (0x1UL << 10) /**< Param AB not valid */ +#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_SHIFT 10 /**< Shift value for CRYPTOACC_PARAMABNOTVALID */ +#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_MASK 0x400UL /**< Bit mask for CRYPTOACC_PARAMABNOTVALID */ +#define _CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT (_CRYPTOACC_PKSTATUS_PARAMABNOTVALID_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTINVERTIBLE (0x1UL << 11) /**< Not invertible */ +#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_SHIFT 11 /**< Shift value for CRYPTOACC_NOTINVERTIBLE */ +#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_MASK 0x800UL /**< Bit mask for CRYPTOACC_NOTINVERTIBLE */ +#define _CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT (_CRYPTOACC_PKSTATUS_NOTINVERTIBLE_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COMPOSITE (0x1UL << 12) /**< Composite */ +#define _CRYPTOACC_PKSTATUS_COMPOSITE_SHIFT 12 /**< Shift value for CRYPTOACC_COMPOSITE */ +#define _CRYPTOACC_PKSTATUS_COMPOSITE_MASK 0x1000UL /**< Bit mask for CRYPTOACC_COMPOSITE */ +#define _CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define _CRYPTOACC_PKSTATUS_COMPOSITE_FALSE 0x00000000UL /**< Mode FALSE for CRYPTOACC_PKSTATUS */ +#define _CRYPTOACC_PKSTATUS_COMPOSITE_TRUE 0x00000001UL /**< Mode TRUE for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT (_CRYPTOACC_PKSTATUS_COMPOSITE_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COMPOSITE_FALSE (_CRYPTOACC_PKSTATUS_COMPOSITE_FALSE << 12) /**< Shifted mode FALSE for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_COMPOSITE_TRUE (_CRYPTOACC_PKSTATUS_COMPOSITE_TRUE << 12) /**< Shifted mode TRUE for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTQUAD (0x1UL << 13) /**< Not quadratic residue */ +#define _CRYPTOACC_PKSTATUS_NOTQUAD_SHIFT 13 /**< Shift value for CRYPTOACC_NOTQUAD */ +#define _CRYPTOACC_PKSTATUS_NOTQUAD_MASK 0x2000UL /**< Bit mask for CRYPTOACC_NOTQUAD */ +#define _CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT (_CRYPTOACC_PKSTATUS_NOTQUAD_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PKBUSY (0x1UL << 16) /**< PK busy */ +#define _CRYPTOACC_PKSTATUS_PKBUSY_SHIFT 16 /**< Shift value for CRYPTOACC_PKBUSY */ +#define _CRYPTOACC_PKSTATUS_PKBUSY_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PKBUSY */ +#define _CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT (_CRYPTOACC_PKSTATUS_PKBUSY_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PKIF (0x1UL << 17) /**< Interrupt status */ +#define _CRYPTOACC_PKSTATUS_PKIF_SHIFT 17 /**< Shift value for CRYPTOACC_PKIF */ +#define _CRYPTOACC_PKSTATUS_PKIF_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PKIF */ +#define _CRYPTOACC_PKSTATUS_PKIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_PKSTATUS */ +#define CRYPTOACC_PKSTATUS_PKIF_DEFAULT (_CRYPTOACC_PKSTATUS_PKIF_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_PKSTATUS */ + +/* Bit fields for CRYPTOACC VERSION */ +#define _CRYPTOACC_VERSION_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_VERSION */ +#define _CRYPTOACC_VERSION_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_VERSION */ +#define _CRYPTOACC_VERSION_SW_SHIFT 0 /**< Shift value for CRYPTOACC_SW */ +#define _CRYPTOACC_VERSION_SW_MASK 0xFFUL /**< Bit mask for CRYPTOACC_SW */ +#define _CRYPTOACC_VERSION_SW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ +#define CRYPTOACC_VERSION_SW_DEFAULT (_CRYPTOACC_VERSION_SW_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ +#define _CRYPTOACC_VERSION_HW_SHIFT 8 /**< Shift value for CRYPTOACC_HW */ +#define _CRYPTOACC_VERSION_HW_MASK 0xFF00UL /**< Bit mask for CRYPTOACC_HW */ +#define _CRYPTOACC_VERSION_HW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_VERSION */ +#define CRYPTOACC_VERSION_HW_DEFAULT (_CRYPTOACC_VERSION_HW_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_VERSION */ + +/* Bit fields for CRYPTOACC TIMER */ +#define _CRYPTOACC_TIMER_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TIMER */ +#define _CRYPTOACC_TIMER_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TIMER */ +#define _CRYPTOACC_TIMER_TIMER_SHIFT 0 /**< Shift value for CRYPTOACC_TIMER */ +#define _CRYPTOACC_TIMER_TIMER_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_TIMER */ +#define _CRYPTOACC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TIMER */ +#define CRYPTOACC_TIMER_TIMER_DEFAULT (_CRYPTOACC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TIMER */ + +/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL_BitFields */ +/** @} End of group EFR32BG22_CRYPTOACC_PKCTRL */ +/**************************************************************************//** + * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL CRYPTOACC_RNGCTRL + * @{ + * @brief EFR32BG22 CRYPTOACC_RNGCTRL Register Declaration. + *****************************************************************************/ + +/** CRYPTOACC_RNGCTRL KEYS Register Group Declaration. */ +typedef struct { + __IOM uint32_t KEY; /**< Key Register */ +} CRYPTOACC_KEYS_TypeDef; + +/** CRYPTOACC_RNGCTRL Register Declaration. */ +typedef struct { + __IOM uint32_t RNGCTRL; /**< RNG Control Register */ + __IM uint32_t FIFOLEVEL; /**< FIFO Level Register */ + __IM uint32_t FIFOTHRESH; /**< FIFO Threshold Register */ + __IM uint32_t FIFODEPTH; /**< FIFO Depth Register */ + CRYPTOACC_KEYS_TypeDef KEYS[4U]; /**< */ + __IOM uint32_t TESTDATA; /**< Test Data Register */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t RNGSTATUS; /**< RNG Status Register */ + __IOM uint32_t INITWAITVAL; /**< Initial Wait Counter */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t SWOFFTMRVAL; /**< Switch off timer value */ + __IOM uint32_t CLKDIV; /**< Sample clock divider */ + __IOM uint32_t AIS31CONF0; /**< AIS31 configuration 0 register */ + __IOM uint32_t AIS31CONF1; /**< AIS31 configuration 1 register */ + __IOM uint32_t AIS31CONF2; /**< AIS31 configuration 2 register */ + __IOM uint32_t AIS31STATUS; /**< AIS31 status register */ +} CRYPTOACC_RNGCTRL_TypeDef; +/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_CRYPTOACC_RNGCTRL + * @{ + * @defgroup EFR32BG22_CRYPTOACC_RNGCTRL_BitFields CRYPTOACC_RNGCTRL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for CRYPTOACC RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_RESETVALUE 0x00040000UL /**< Default value for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_MASK 0x001FFFFFUL /**< Mask for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ENABLE (0x1UL << 0) /**< TRNG Module Enable */ +#define _CRYPTOACC_RNGCTRL_ENABLE_SHIFT 0 /**< Shift value for CRYPTOACC_ENABLE */ +#define _CRYPTOACC_RNGCTRL_ENABLE_MASK 0x1UL /**< Bit mask for CRYPTOACC_ENABLE */ +#define _CRYPTOACC_RNGCTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_ENABLE_DISABLED 0x00000000UL /**< Mode DISABLED for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_ENABLE_ENABLED 0x00000001UL /**< Mode ENABLED for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ENABLE_DEFAULT (_CRYPTOACC_RNGCTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ENABLE_DISABLED (_CRYPTOACC_RNGCTRL_ENABLE_DISABLED << 0) /**< Shifted mode DISABLED for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ENABLE_ENABLED (_CRYPTOACC_RNGCTRL_ENABLE_ENABLED << 0) /**< Shifted mode ENABLED for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_TESTEN (0x1UL << 2) /**< Test Enable */ +#define _CRYPTOACC_RNGCTRL_TESTEN_SHIFT 2 /**< Shift value for CRYPTOACC_TESTEN */ +#define _CRYPTOACC_RNGCTRL_TESTEN_MASK 0x4UL /**< Bit mask for CRYPTOACC_TESTEN */ +#define _CRYPTOACC_RNGCTRL_TESTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_TESTEN_NOISE 0x00000000UL /**< Mode NOISE for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_TESTEN_TESTDATA 0x00000001UL /**< Mode TESTDATA for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_TESTEN_DEFAULT (_CRYPTOACC_RNGCTRL_TESTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_TESTEN_NOISE (_CRYPTOACC_RNGCTRL_TESTEN_NOISE << 2) /**< Shifted mode NOISE for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_TESTEN_TESTDATA (_CRYPTOACC_RNGCTRL_TESTEN_TESTDATA << 2) /**< Shifted mode TESTDATA for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_CONDBYPASS (0x1UL << 3) /**< Conditioning Bypass */ +#define _CRYPTOACC_RNGCTRL_CONDBYPASS_SHIFT 3 /**< Shift value for CRYPTOACC_CONDBYPASS */ +#define _CRYPTOACC_RNGCTRL_CONDBYPASS_MASK 0x8UL /**< Bit mask for CRYPTOACC_CONDBYPASS */ +#define _CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT (_CRYPTOACC_RNGCTRL_CONDBYPASS_DEFAULT << 3) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL (_CRYPTOACC_RNGCTRL_CONDBYPASS_NORMAL << 3) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS (_CRYPTOACC_RNGCTRL_CONDBYPASS_BYPASS << 3) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_REPCOUNTIEN (0x1UL << 4) /**< IRQ enable for Repetition Count Test */ +#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIEN */ +#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIEN */ +#define _CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT (_CRYPTOACC_RNGCTRL_REPCOUNTIEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_APT64IEN (0x1UL << 5) /**< IRQ enable for APT64IF */ +#define _CRYPTOACC_RNGCTRL_APT64IEN_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IEN */ +#define _CRYPTOACC_RNGCTRL_APT64IEN_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IEN */ +#define _CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT64IEN_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_APT4096IEN (0x1UL << 6) /**< IRQ enable for APT4096IF */ +#define _CRYPTOACC_RNGCTRL_APT4096IEN_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IEN */ +#define _CRYPTOACC_RNGCTRL_APT4096IEN_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IEN */ +#define _CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT (_CRYPTOACC_RNGCTRL_APT4096IEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FULLIEN (0x1UL << 7) /**< IRQ enable for FIFO full */ +#define _CRYPTOACC_RNGCTRL_FULLIEN_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIEN */ +#define _CRYPTOACC_RNGCTRL_FULLIEN_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIEN */ +#define _CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT (_CRYPTOACC_RNGCTRL_FULLIEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_SOFTRESET (0x1UL << 8) /**< Software Reset */ +#define _CRYPTOACC_RNGCTRL_SOFTRESET_SHIFT 8 /**< Shift value for CRYPTOACC_SOFTRESET */ +#define _CRYPTOACC_RNGCTRL_SOFTRESET_MASK 0x100UL /**< Bit mask for CRYPTOACC_SOFTRESET */ +#define _CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_SOFTRESET_RESET 0x00000001UL /**< Mode RESET for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT (_CRYPTOACC_RNGCTRL_SOFTRESET_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL (_CRYPTOACC_RNGCTRL_SOFTRESET_NORMAL << 8) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_SOFTRESET_RESET (_CRYPTOACC_RNGCTRL_SOFTRESET_RESET << 8) /**< Shifted mode RESET for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_PREIEN (0x1UL << 9) /**< IRQ enable for AIS31 prelim. noise alarm */ +#define _CRYPTOACC_RNGCTRL_PREIEN_SHIFT 9 /**< Shift value for CRYPTOACC_PREIEN */ +#define _CRYPTOACC_RNGCTRL_PREIEN_MASK 0x200UL /**< Bit mask for CRYPTOACC_PREIEN */ +#define _CRYPTOACC_RNGCTRL_PREIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_PREIEN_DEFAULT (_CRYPTOACC_RNGCTRL_PREIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ALMIEN (0x1UL << 10) /**< IRQ enable for AIS31 noise alarm */ +#define _CRYPTOACC_RNGCTRL_ALMIEN_SHIFT 10 /**< Shift value for CRYPTOACC_ALMIEN */ +#define _CRYPTOACC_RNGCTRL_ALMIEN_MASK 0x400UL /**< Bit mask for CRYPTOACC_ALMIEN */ +#define _CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT (_CRYPTOACC_RNGCTRL_ALMIEN_DEFAULT << 10) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FORCERUN (0x1UL << 11) /**< Oscillator Force Run */ +#define _CRYPTOACC_RNGCTRL_FORCERUN_SHIFT 11 /**< Shift value for CRYPTOACC_FORCERUN */ +#define _CRYPTOACC_RNGCTRL_FORCERUN_MASK 0x800UL /**< Bit mask for CRYPTOACC_FORCERUN */ +#define _CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_FORCERUN_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_FORCERUN_RUN 0x00000001UL /**< Mode RUN for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT (_CRYPTOACC_RNGCTRL_FORCERUN_DEFAULT << 11) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FORCERUN_NORMAL (_CRYPTOACC_RNGCTRL_FORCERUN_NORMAL << 11) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FORCERUN_RUN (_CRYPTOACC_RNGCTRL_FORCERUN_RUN << 11) /**< Shifted mode RUN for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPNIST (0x1UL << 12) /**< NIST Start-up Test Bypass. */ +#define _CRYPTOACC_RNGCTRL_BYPNIST_SHIFT 12 /**< Shift value for CRYPTOACC_BYPNIST */ +#define _CRYPTOACC_RNGCTRL_BYPNIST_MASK 0x1000UL /**< Bit mask for CRYPTOACC_BYPNIST */ +#define _CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_BYPNIST_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_BYPNIST_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT (_CRYPTOACC_RNGCTRL_BYPNIST_DEFAULT << 12) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPNIST_NORMAL (_CRYPTOACC_RNGCTRL_BYPNIST_NORMAL << 12) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPNIST_BYPASS (_CRYPTOACC_RNGCTRL_BYPNIST_BYPASS << 12) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPAIS31 (0x1UL << 13) /**< AIS31 Start-up Test Bypass. */ +#define _CRYPTOACC_RNGCTRL_BYPAIS31_SHIFT 13 /**< Shift value for CRYPTOACC_BYPAIS31 */ +#define _CRYPTOACC_RNGCTRL_BYPAIS31_MASK 0x2000UL /**< Bit mask for CRYPTOACC_BYPAIS31 */ +#define _CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL 0x00000000UL /**< Mode NORMAL for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS 0x00000001UL /**< Mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT (_CRYPTOACC_RNGCTRL_BYPAIS31_DEFAULT << 13) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL (_CRYPTOACC_RNGCTRL_BYPAIS31_NORMAL << 13) /**< Shifted mode NORMAL for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS (_CRYPTOACC_RNGCTRL_BYPAIS31_BYPASS << 13) /**< Shifted mode BYPASS for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL (0x1UL << 14) /**< Health test input select */ +#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_SHIFT 14 /**< Shift value for CRYPTOACC_HEALTHTESTSEL */ +#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_MASK 0x4000UL /**< Bit mask for CRYPTOACC_HEALTHTESTSEL */ +#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_DEFAULT << 14) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_BEFORE << 14) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER (_CRYPTOACC_RNGCTRL_HEALTHTESTSEL_AFTER << 14) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_AIS31TESTSEL (0x1UL << 15) /**< AIS31 test input select */ +#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_SHIFT 15 /**< Shift value for CRYPTOACC_AIS31TESTSEL */ +#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_MASK 0x8000UL /**< Bit mask for CRYPTOACC_AIS31TESTSEL */ +#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE 0x00000000UL /**< Mode BEFORE for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER 0x00000001UL /**< Mode AFTER for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_DEFAULT << 15) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_BEFORE << 15) /**< Shifted mode BEFORE for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER (_CRYPTOACC_RNGCTRL_AIS31TESTSEL_AFTER << 15) /**< Shifted mode AFTER for CRYPTOACC_RNGCTRL */ +#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_SHIFT 16 /**< Shift value for CRYPTOACC_NB128BITBLOCKS */ +#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_MASK 0xF0000UL /**< Bit mask for CRYPTOACC_NB128BITBLOCKS */ +#define _CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT 0x00000004UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT (_CRYPTOACC_RNGCTRL_NB128BITBLOCKS_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP (0x1UL << 20) /**< Fifo Write Start Up */ +#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_SHIFT 20 /**< Shift value for CRYPTOACC_FIFOWRSTARTUP */ +#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_MASK 0x100000UL /**< Bit mask for CRYPTOACC_FIFOWRSTARTUP */ +#define _CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGCTRL */ +#define CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT (_CRYPTOACC_RNGCTRL_FIFOWRSTARTUP_DEFAULT << 20) /**< Shifted mode DEFAULT for CRYPTOACC_RNGCTRL */ + +/* Bit fields for CRYPTOACC FIFOLEVEL */ +#define _CRYPTOACC_FIFOLEVEL_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_FIFOLEVEL */ +#define _CRYPTOACC_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOLEVEL */ +#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOLEVEL */ +#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOLEVEL */ +#define _CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_FIFOLEVEL */ +#define CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT (_CRYPTOACC_FIFOLEVEL_FIFOLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOLEVEL*/ + +/* Bit fields for CRYPTOACC FIFOTHRESH */ +#define _CRYPTOACC_FIFOTHRESH_RESETVALUE 0x0000003FUL /**< Default value for CRYPTOACC_FIFOTHRESH */ +#define _CRYPTOACC_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFOTHRESH */ +#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFOTHRESH */ +#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFOTHRESH */ +#define _CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT 0x0000003FUL /**< Mode DEFAULT for CRYPTOACC_FIFOTHRESH */ +#define CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT (_CRYPTOACC_FIFOTHRESH_FIFOTHRESH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFOTHRESH*/ + +/* Bit fields for CRYPTOACC FIFODEPTH */ +#define _CRYPTOACC_FIFODEPTH_RESETVALUE 0x00000040UL /**< Default value for CRYPTOACC_FIFODEPTH */ +#define _CRYPTOACC_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_FIFODEPTH */ +#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_SHIFT 0 /**< Shift value for CRYPTOACC_FIFODEPTH */ +#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_FIFODEPTH */ +#define _CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT 0x00000040UL /**< Mode DEFAULT for CRYPTOACC_FIFODEPTH */ +#define CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT (_CRYPTOACC_FIFODEPTH_FIFODEPTH_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_FIFODEPTH*/ + +/* Bit fields for CRYPTOACC KEY */ +#define _CRYPTOACC_KEY_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_KEY */ +#define _CRYPTOACC_KEY_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_KEY */ +#define _CRYPTOACC_KEY_KEY_SHIFT 0 /**< Shift value for CRYPTOACC_KEY */ +#define _CRYPTOACC_KEY_KEY_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_KEY */ +#define _CRYPTOACC_KEY_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_KEY */ +#define CRYPTOACC_KEY_KEY_DEFAULT (_CRYPTOACC_KEY_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_KEY */ + +/* Bit fields for CRYPTOACC TESTDATA */ +#define _CRYPTOACC_TESTDATA_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_TESTDATA */ +#define _CRYPTOACC_TESTDATA_MASK 0xFFFFFFFFUL /**< Mask for CRYPTOACC_TESTDATA */ +#define _CRYPTOACC_TESTDATA_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ +#define _CRYPTOACC_TESTDATA_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for CRYPTOACC_VALUE */ +#define _CRYPTOACC_TESTDATA_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_TESTDATA */ +#define CRYPTOACC_TESTDATA_VALUE_DEFAULT (_CRYPTOACC_TESTDATA_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_TESTDATA */ + +/* Bit fields for CRYPTOACC RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_MASK 0x000007FFUL /**< Mask for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_TESTDATABUSY (0x1UL << 0) /**< Test Data Busy */ +#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_SHIFT 0 /**< Shift value for CRYPTOACC_TESTDATABUSY */ +#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_MASK 0x1UL /**< Bit mask for CRYPTOACC_TESTDATABUSY */ +#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE 0x00000000UL /**< Mode IDLE for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY 0x00000001UL /**< Mode BUSY for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_IDLE << 0) /**< Shifted mode IDLE for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY (_CRYPTOACC_RNGSTATUS_TESTDATABUSY_BUSY << 0) /**< Shifted mode BUSY for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_SHIFT 1 /**< Shift value for CRYPTOACC_STATE */ +#define _CRYPTOACC_RNGSTATUS_STATE_MASK 0xEUL /**< Bit mask for CRYPTOACC_STATE */ +#define _CRYPTOACC_RNGSTATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_RESET 0x00000000UL /**< Mode RESET for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_STARTUP 0x00000001UL /**< Mode STARTUP for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON 0x00000002UL /**< Mode FIFOFULLON for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF 0x00000003UL /**< Mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_RUNNING 0x00000004UL /**< Mode RUNNING for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_ERROR 0x00000005UL /**< Mode ERROR for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 0x00000006UL /**< Mode UNUSED_6 for CRYPTOACC_RNGSTATUS */ +#define _CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 0x00000007UL /**< Mode UNUSED_7 for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_STATE_DEFAULT (_CRYPTOACC_RNGSTATUS_STATE_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_RESET (_CRYPTOACC_RNGSTATUS_STATE_RESET << 1) /**< Shifted mode RESET for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_STATE_STARTUP (_CRYPTOACC_RNGSTATUS_STATE_STARTUP << 1) /**< Shifted mode STARTUP for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLON << 1) /**< Shifted mode FIFOFULLON for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF (_CRYPTOACC_RNGSTATUS_STATE_FIFOFULLOFF << 1) /**< Shifted mode FIFOFULLOFF for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_RUNNING (_CRYPTOACC_RNGSTATUS_STATE_RUNNING << 1) /**< Shifted mode RUNNING for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_ERROR (_CRYPTOACC_RNGSTATUS_STATE_ERROR << 1) /**< Shifted mode ERROR for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_6 << 1) /**< Shifted mode UNUSED_6 for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 (_CRYPTOACC_RNGSTATUS_STATE_UNUSED_7 << 1) /**< Shifted mode UNUSED_7 for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_REPCOUNTIF (0x1UL << 4) /**< Repetition Count Test interrupt status */ +#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_SHIFT 4 /**< Shift value for CRYPTOACC_REPCOUNTIF */ +#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_MASK 0x10UL /**< Bit mask for CRYPTOACC_REPCOUNTIF */ +#define _CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT (_CRYPTOACC_RNGSTATUS_REPCOUNTIF_DEFAULT << 4) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_APT64IF (0x1UL << 5) /**< 64-sample window Adaptive Proportion IF */ +#define _CRYPTOACC_RNGSTATUS_APT64IF_SHIFT 5 /**< Shift value for CRYPTOACC_APT64IF */ +#define _CRYPTOACC_RNGSTATUS_APT64IF_MASK 0x20UL /**< Bit mask for CRYPTOACC_APT64IF */ +#define _CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT64IF_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_APT4096IF (0x1UL << 6) /**< 4096-sample window Adaptive Prop. IF */ +#define _CRYPTOACC_RNGSTATUS_APT4096IF_SHIFT 6 /**< Shift value for CRYPTOACC_APT4096IF */ +#define _CRYPTOACC_RNGSTATUS_APT4096IF_MASK 0x40UL /**< Bit mask for CRYPTOACC_APT4096IF */ +#define _CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT (_CRYPTOACC_RNGSTATUS_APT4096IF_DEFAULT << 6) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_FULLIF (0x1UL << 7) /**< FIFO full interrupt status */ +#define _CRYPTOACC_RNGSTATUS_FULLIF_SHIFT 7 /**< Shift value for CRYPTOACC_FULLIF */ +#define _CRYPTOACC_RNGSTATUS_FULLIF_MASK 0x80UL /**< Bit mask for CRYPTOACC_FULLIF */ +#define _CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT (_CRYPTOACC_RNGSTATUS_FULLIF_DEFAULT << 7) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_PREIF (0x1UL << 8) /**< AIS31 Preliminary Noise Alarm IF */ +#define _CRYPTOACC_RNGSTATUS_PREIF_SHIFT 8 /**< Shift value for CRYPTOACC_PREIF */ +#define _CRYPTOACC_RNGSTATUS_PREIF_MASK 0x100UL /**< Bit mask for CRYPTOACC_PREIF */ +#define _CRYPTOACC_RNGSTATUS_PREIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_PREIF_DEFAULT (_CRYPTOACC_RNGSTATUS_PREIF_DEFAULT << 8) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ +#define CRYPTOACC_RNGSTATUS_ALMIF (0x1UL << 9) /**< AIS31 Noise Alarm interrupt status */ +#define _CRYPTOACC_RNGSTATUS_ALMIF_SHIFT 9 /**< Shift value for CRYPTOACC_ALMIF */ +#define _CRYPTOACC_RNGSTATUS_ALMIF_MASK 0x200UL /**< Bit mask for CRYPTOACC_ALMIF */ +#define _CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_RNGSTATUS */ +#define CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT (_CRYPTOACC_RNGSTATUS_ALMIF_DEFAULT << 9) /**< Shifted mode DEFAULT for CRYPTOACC_RNGSTATUS*/ + +/* Bit fields for CRYPTOACC INITWAITVAL */ +#define _CRYPTOACC_INITWAITVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_INITWAITVAL */ +#define _CRYPTOACC_INITWAITVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_INITWAITVAL */ +#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_SHIFT 0 /**< Shift value for CRYPTOACC_INITWAITVAL */ +#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_INITWAITVAL */ +#define _CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_INITWAITVAL */ +#define CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT (_CRYPTOACC_INITWAITVAL_INITWAITVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_INITWAITVAL*/ + +/* Bit fields for CRYPTOACC SWOFFTMRVAL */ +#define _CRYPTOACC_SWOFFTMRVAL_RESETVALUE 0x0000FFFFUL /**< Default value for CRYPTOACC_SWOFFTMRVAL */ +#define _CRYPTOACC_SWOFFTMRVAL_MASK 0x0000FFFFUL /**< Mask for CRYPTOACC_SWOFFTMRVAL */ +#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_SHIFT 0 /**< Shift value for CRYPTOACC_SWOFFTMRVAL */ +#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_SWOFFTMRVAL */ +#define _CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for CRYPTOACC_SWOFFTMRVAL */ +#define CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT (_CRYPTOACC_SWOFFTMRVAL_SWOFFTMRVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_SWOFFTMRVAL*/ + +/* Bit fields for CRYPTOACC CLKDIV */ +#define _CRYPTOACC_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_CLKDIV */ +#define _CRYPTOACC_CLKDIV_MASK 0x000000FFUL /**< Mask for CRYPTOACC_CLKDIV */ +#define _CRYPTOACC_CLKDIV_VALUE_SHIFT 0 /**< Shift value for CRYPTOACC_VALUE */ +#define _CRYPTOACC_CLKDIV_VALUE_MASK 0xFFUL /**< Bit mask for CRYPTOACC_VALUE */ +#define _CRYPTOACC_CLKDIV_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_CLKDIV */ +#define CRYPTOACC_CLKDIV_VALUE_DEFAULT (_CRYPTOACC_CLKDIV_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_CLKDIV */ + +/* Bit fields for CRYPTOACC AIS31CONF0 */ +#define _CRYPTOACC_AIS31CONF0_RESETVALUE 0x43401040UL /**< Default value for CRYPTOACC_AIS31CONF0 */ +#define _CRYPTOACC_AIS31CONF0_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF0 */ +#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_SHIFT 0 /**< Shift value for CRYPTOACC_STARTUPTHRES */ +#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_STARTUPTHRES */ +#define _CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT 0x00001040UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ +#define CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT (_CRYPTOACC_AIS31CONF0_STARTUPTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ +#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINETHRESH */ +#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINETHRESH */ +#define _CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT 0x00004340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF0 */ +#define CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT (_CRYPTOACC_AIS31CONF0_ONLINETHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF0*/ + +/* Bit fields for CRYPTOACC AIS31CONF1 */ +#define _CRYPTOACC_AIS31CONF1_RESETVALUE 0x03C00680UL /**< Default value for CRYPTOACC_AIS31CONF1 */ +#define _CRYPTOACC_AIS31CONF1_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF1 */ +#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_SHIFT 0 /**< Shift value for CRYPTOACC_HEXPECTEDVALUE */ +#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HEXPECTEDVALUE */ +#define _CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT 0x00000680UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ +#define CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT (_CRYPTOACC_AIS31CONF1_HEXPECTEDVALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ +#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_SHIFT 16 /**< Shift value for CRYPTOACC_ONLINEREPTHRESH */ +#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_ONLINEREPTHRESH */ +#define _CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT 0x000003C0UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF1 */ +#define CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT (_CRYPTOACC_AIS31CONF1_ONLINEREPTHRESH_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF1*/ + +/* Bit fields for CRYPTOACC AIS31CONF2 */ +#define _CRYPTOACC_AIS31CONF2_RESETVALUE 0x04400340UL /**< Default value for CRYPTOACC_AIS31CONF2 */ +#define _CRYPTOACC_AIS31CONF2_MASK 0x7FFF7FFFUL /**< Mask for CRYPTOACC_AIS31CONF2 */ +#define _CRYPTOACC_AIS31CONF2_HMIN_SHIFT 0 /**< Shift value for CRYPTOACC_HMIN */ +#define _CRYPTOACC_AIS31CONF2_HMIN_MASK 0x7FFFUL /**< Bit mask for CRYPTOACC_HMIN */ +#define _CRYPTOACC_AIS31CONF2_HMIN_DEFAULT 0x00000340UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ +#define CRYPTOACC_AIS31CONF2_HMIN_DEFAULT (_CRYPTOACC_AIS31CONF2_HMIN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ +#define _CRYPTOACC_AIS31CONF2_HMAX_SHIFT 16 /**< Shift value for CRYPTOACC_HMAX */ +#define _CRYPTOACC_AIS31CONF2_HMAX_MASK 0x7FFF0000UL /**< Bit mask for CRYPTOACC_HMAX */ +#define _CRYPTOACC_AIS31CONF2_HMAX_DEFAULT 0x00000440UL /**< Mode DEFAULT for CRYPTOACC_AIS31CONF2 */ +#define CRYPTOACC_AIS31CONF2_HMAX_DEFAULT (_CRYPTOACC_AIS31CONF2_HMAX_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31CONF2*/ + +/* Bit fields for CRYPTOACC AIS31STATUS */ +#define _CRYPTOACC_AIS31STATUS_RESETVALUE 0x00000000UL /**< Default value for CRYPTOACC_AIS31STATUS */ +#define _CRYPTOACC_AIS31STATUS_MASK 0x0003FFFFUL /**< Mask for CRYPTOACC_AIS31STATUS */ +#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_SHIFT 0 /**< Shift value for CRYPTOACC_NUMPRELIMALARMS */ +#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_MASK 0xFFFFUL /**< Bit mask for CRYPTOACC_NUMPRELIMALARMS */ +#define _CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ +#define CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT (_CRYPTOACC_AIS31STATUS_NUMPRELIMALARMS_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ +#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG (0x1UL << 16) /**< Preliminary noise alarm RNG */ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_SHIFT 16 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMRNG*/ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_MASK 0x10000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMRNG */ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ +#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMRNG_DEFAULT << 16) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ +#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP (0x1UL << 17) /**< Preliminary noise alarm Rep */ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_SHIFT 17 /**< Shift value for CRYPTOACC_PRELIMNOISEALARMREP*/ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_MASK 0x20000UL /**< Bit mask for CRYPTOACC_PRELIMNOISEALARMREP */ +#define _CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYPTOACC_AIS31STATUS */ +#define CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT (_CRYPTOACC_AIS31STATUS_PRELIMNOISEALARMREP_DEFAULT << 17) /**< Shifted mode DEFAULT for CRYPTOACC_AIS31STATUS*/ + +/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL_BitFields */ +/** @} End of group EFR32BG22_CRYPTOACC_RNGCTRL */ +/** @} End of group Parts */ + +#endif // EFR32BG22_CRYPTOACC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h index ee12df2..3fae71b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dcdc.h @@ -1,392 +1,392 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 DCDC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_DCDC_H -#define EFR32BG22_DCDC_H -#define DCDC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_DCDC DCDC - * @{ - * @brief EFR32BG22 DCDC Register Declaration. - *****************************************************************************/ - -/** DCDC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CTRL; /**< Control */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01CTRL0; /**< EM01 Control */ - __IOM uint32_t EM23CTRL0; /**< EM23 Control */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED2[4U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ - uint32_t RESERVED3[2U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - uint32_t RESERVED7[995U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CTRL_SET; /**< Control */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ - __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED10[4U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ - uint32_t RESERVED11[2U]; /**< Reserved for future use */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - uint32_t RESERVED15[995U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CTRL_CLR; /**< Control */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ - __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ - uint32_t RESERVED17[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED18[4U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - uint32_t RESERVED21[7U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - uint32_t RESERVED23[995U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CTRL_TGL; /**< Control */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ - __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED26[4U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ - uint32_t RESERVED27[2U]; /**< Reserved for future use */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - uint32_t RESERVED29[7U]; /**< Reserved for future use */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ -} DCDC_TypeDef; -/** @} End of group EFR32BG22_DCDC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_DCDC - * @{ - * @defgroup EFR32BG22_DCDC_BitFields DCDC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DCDC IPVERSION */ -#define _DCDC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ -#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IPVERSION */ -#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ - -/* Bit fields for DCDC EN */ -#define _DCDC_EN_RESETVALUE 0x00000000UL /**< Default value for DCDC_EN */ -#define _DCDC_EN_MASK 0x00000001UL /**< Mask for DCDC_EN */ -#define DCDC_EN_EN (0x1UL << 0) /**< Enable */ -#define _DCDC_EN_EN_SHIFT 0 /**< Shift value for DCDC_EN */ -#define _DCDC_EN_EN_MASK 0x1UL /**< Bit mask for DCDC_EN */ -#define _DCDC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_EN */ -#define _DCDC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for DCDC_EN */ -#define _DCDC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for DCDC_EN */ -#define DCDC_EN_EN_DEFAULT (_DCDC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EN */ -#define DCDC_EN_EN_DISABLE (_DCDC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for DCDC_EN */ -#define DCDC_EN_EN_ENABLE (_DCDC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for DCDC_EN */ - -/* Bit fields for DCDC CTRL */ -#define _DCDC_CTRL_RESETVALUE 0x00000044UL /**< Default value for DCDC_CTRL */ -#define _DCDC_CTRL_MASK 0x00000077UL /**< Mask for DCDC_CTRL */ -#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ -#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ -#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ -#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ -#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ -#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ -#define DCDC_CTRL_DCMONLYEN (0x1UL << 2) /**< DCDC DCM Only Enable */ -#define _DCDC_CTRL_DCMONLYEN_SHIFT 2 /**< Shift value for DCDC_DCMONLYEN */ -#define _DCDC_CTRL_DCMONLYEN_MASK 0x4UL /**< Bit mask for DCDC_DCMONLYEN */ -#define _DCDC_CTRL_DCMONLYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_DCMONLYEN_DUALMODE 0x00000000UL /**< Mode DUALMODE for DCDC_CTRL */ -#define _DCDC_CTRL_DCMONLYEN_DCMONLYEN 0x00000001UL /**< Mode DCMONLYEN for DCDC_CTRL */ -#define DCDC_CTRL_DCMONLYEN_DEFAULT (_DCDC_CTRL_DCMONLYEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_DCMONLYEN_DUALMODE (_DCDC_CTRL_DCMONLYEN_DUALMODE << 2) /**< Shifted mode DUALMODE for DCDC_CTRL */ -#define DCDC_CTRL_DCMONLYEN_DCMONLYEN (_DCDC_CTRL_DCMONLYEN_DCMONLYEN << 2) /**< Shifted mode DCMONLYEN for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ -#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ -#define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ - -/* Bit fields for DCDC EM01CTRL0 */ -#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ -#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ -#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ -#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ -#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ -#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ -#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ -#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ -#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ - -/* Bit fields for DCDC EM23CTRL0 */ -#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ -#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ -#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_LOAD5MA 0x00000003UL /**< Mode LOAD5MA for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_IPKVAL_LOAD10MA 0x00000009UL /**< Mode LOAD10MA for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_LOAD5MA (_DCDC_EM23CTRL0_IPKVAL_LOAD5MA << 0) /**< Shifted mode LOAD5MA for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_IPKVAL_LOAD10MA (_DCDC_EM23CTRL0_IPKVAL_LOAD10MA << 0) /**< Shifted mode LOAD10MA for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ -#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ -#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ -#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ -#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ -#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ -#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ - -/* Bit fields for DCDC IF */ -#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ -#define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ -#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ -#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ -#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ -#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ -#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ -#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ -#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ -#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ -#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ -#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ -#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ -#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ -#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ -#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ -#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ -#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ -#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ -#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ -#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ -#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ -#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ - -/* Bit fields for DCDC IEN */ -#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ -#define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ -#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ -#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ -#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ -#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ -#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ -#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ -#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ -#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ -#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ -#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ -#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ -#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ -#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ -#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ -#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ -#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ -#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ -#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ -#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ -#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ - -/* Bit fields for DCDC STATUS */ -#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ -#define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ -#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ -#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ -#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ -#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ -#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ -#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ -#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ -#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ -#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ -#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ -#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ -#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ -#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ -#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ -#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ -#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ -#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ - -/* Bit fields for DCDC LOCK */ -#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ -#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ -#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ -#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ -#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ -#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ -#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ -#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ - -/* Bit fields for DCDC LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ -#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ -#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ -#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ -#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ -#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ - -/** @} End of group EFR32BG22_DCDC_BitFields */ -/** @} End of group EFR32BG22_DCDC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_DCDC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 DCDC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_DCDC_H +#define EFR32BG22_DCDC_H +#define DCDC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_DCDC DCDC + * @{ + * @brief EFR32BG22 DCDC Register Declaration. + *****************************************************************************/ + +/** DCDC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0; /**< EM23 Control */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED2[4U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ + uint32_t RESERVED3[2U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + uint32_t RESERVED7[995U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED10[4U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + uint32_t RESERVED15[995U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ + uint32_t RESERVED17[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED18[4U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + uint32_t RESERVED21[7U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + uint32_t RESERVED23[995U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ + __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED26[4U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ + uint32_t RESERVED27[2U]; /**< Reserved for future use */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + uint32_t RESERVED29[7U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ +} DCDC_TypeDef; +/** @} End of group EFR32BG22_DCDC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_DCDC + * @{ + * @defgroup EFR32BG22_DCDC_BitFields DCDC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DCDC IPVERSION */ +#define _DCDC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ +#define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IPVERSION */ +#define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ + +/* Bit fields for DCDC EN */ +#define _DCDC_EN_RESETVALUE 0x00000000UL /**< Default value for DCDC_EN */ +#define _DCDC_EN_MASK 0x00000001UL /**< Mask for DCDC_EN */ +#define DCDC_EN_EN (0x1UL << 0) /**< Enable */ +#define _DCDC_EN_EN_SHIFT 0 /**< Shift value for DCDC_EN */ +#define _DCDC_EN_EN_MASK 0x1UL /**< Bit mask for DCDC_EN */ +#define _DCDC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_EN */ +#define _DCDC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for DCDC_EN */ +#define _DCDC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for DCDC_EN */ +#define DCDC_EN_EN_DEFAULT (_DCDC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EN */ +#define DCDC_EN_EN_DISABLE (_DCDC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for DCDC_EN */ +#define DCDC_EN_EN_ENABLE (_DCDC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for DCDC_EN */ + +/* Bit fields for DCDC CTRL */ +#define _DCDC_CTRL_RESETVALUE 0x00000044UL /**< Default value for DCDC_CTRL */ +#define _DCDC_CTRL_MASK 0x00000077UL /**< Mask for DCDC_CTRL */ +#define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ +#define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ +#define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ +#define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ +#define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ +#define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ +#define DCDC_CTRL_DCMONLYEN (0x1UL << 2) /**< DCDC DCM Only Enable */ +#define _DCDC_CTRL_DCMONLYEN_SHIFT 2 /**< Shift value for DCDC_DCMONLYEN */ +#define _DCDC_CTRL_DCMONLYEN_MASK 0x4UL /**< Bit mask for DCDC_DCMONLYEN */ +#define _DCDC_CTRL_DCMONLYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_DCMONLYEN_DUALMODE 0x00000000UL /**< Mode DUALMODE for DCDC_CTRL */ +#define _DCDC_CTRL_DCMONLYEN_DCMONLYEN 0x00000001UL /**< Mode DCMONLYEN for DCDC_CTRL */ +#define DCDC_CTRL_DCMONLYEN_DEFAULT (_DCDC_CTRL_DCMONLYEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_DCMONLYEN_DUALMODE (_DCDC_CTRL_DCMONLYEN_DUALMODE << 2) /**< Shifted mode DUALMODE for DCDC_CTRL */ +#define DCDC_CTRL_DCMONLYEN_DCMONLYEN (_DCDC_CTRL_DCMONLYEN_DCMONLYEN << 2) /**< Shifted mode DCMONLYEN for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ +#define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ +#define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ + +/* Bit fields for DCDC EM01CTRL0 */ +#define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ +#define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ +#define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ +#define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ + +/* Bit fields for DCDC EM23CTRL0 */ +#define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ +#define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_LOAD5MA 0x00000003UL /**< Mode LOAD5MA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_IPKVAL_LOAD10MA 0x00000009UL /**< Mode LOAD10MA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_LOAD5MA (_DCDC_EM23CTRL0_IPKVAL_LOAD5MA << 0) /**< Shifted mode LOAD5MA for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_IPKVAL_LOAD10MA (_DCDC_EM23CTRL0_IPKVAL_LOAD10MA << 0) /**< Shifted mode LOAD10MA for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ +#define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ +#define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ +#define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ + +/* Bit fields for DCDC IF */ +#define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ +#define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ +#define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ +#define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ +#define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ +#define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ +#define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ +#define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ +#define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX (0x1UL << 6) /**< Ton_max Timeout Reached */ +#define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ +#define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ +#define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ + +/* Bit fields for DCDC IEN */ +#define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ +#define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ +#define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ +#define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ +#define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ +#define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ +#define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ +#define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ +#define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ +#define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ +#define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ +#define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ +#define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ +#define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ +#define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ +#define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ + +/* Bit fields for DCDC STATUS */ +#define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ +#define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ +#define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ +#define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ +#define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ +#define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ +#define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ +#define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ +#define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ +#define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ +#define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ +#define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ +#define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ +#define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ + +/* Bit fields for DCDC LOCK */ +#define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ +#define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ +#define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ +#define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ +#define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ + +/* Bit fields for DCDC LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ +#define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ +#define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ +#define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ +#define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ + +/** @} End of group EFR32BG22_DCDC_BitFields */ +/** @} End of group EFR32BG22_DCDC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_DCDC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h index 6789781..b994deb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_devinfo.h @@ -1,903 +1,903 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 DEVINFO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_DEVINFO_H -#define EFR32BG22_DEVINFO_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_DEVINFO DEVINFO - * @{ - * @brief EFR32BG22 DEVINFO Register Declaration. - *****************************************************************************/ - -/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ -typedef struct { - __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ -} DEVINFO_HFRCODPLLCAL_TypeDef; - -/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} DEVINFO_HFRCOEM23CAL_TypeDef; - -/** DEVINFO HFRCOSECAL Register Group Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} DEVINFO_HFRCOSECAL_TypeDef; - -/** DEVINFO Register Declaration. */ -typedef struct { - __IM uint32_t INFO; /**< DI Information */ - __IM uint32_t PART; /**< Part Info */ - __IM uint32_t MEMINFO; /**< Memory Info */ - __IM uint32_t MSIZE; /**< Memory Size */ - __IM uint32_t PKGINFO; /**< Misc Device Info */ - __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ - __IM uint32_t SWFIX; /**< SW Fix Register */ - __IM uint32_t SWCAPA0; /**< Software Restriction */ - __IM uint32_t SWCAPA1; /**< Software Restriction */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t EXTINFO; /**< External Component Info */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IM uint32_t EUI48L; /**< EUI 48 Low */ - __IM uint32_t EUI48H; /**< EUI 48 High */ - __IM uint32_t EUI64L; /**< EUI64 Low */ - __IM uint32_t EUI64H; /**< EUI64 High */ - __IM uint32_t CALTEMP; /**< Calibration temperature Information */ - __IM uint32_t EMUTEMP; /**< EMU Temperature Sensor Calibration Information */ - DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ - DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ - DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ - __IM uint32_t MODULENAME0; /**< Module Name Information */ - __IM uint32_t MODULENAME1; /**< Module Name Information */ - __IM uint32_t MODULENAME2; /**< Module Name Information */ - __IM uint32_t MODULENAME3; /**< Module Name Information */ - __IM uint32_t MODULENAME4; /**< Module Name Information */ - __IM uint32_t MODULENAME5; /**< Module Name Information */ - __IM uint32_t MODULENAME6; /**< Module Name Information */ - __IM uint32_t MODULEINFO; /**< Module Information */ - __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ - uint32_t RESERVED3[11U]; /**< Reserved for future use */ - __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ - __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ - __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ - __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ - __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ - uint32_t RESERVED4[24U]; /**< Reserved for future use */ - __IM uint32_t LEGACY; /**< Legacy Device Info */ - uint32_t RESERVED5[23U]; /**< Reserved for future use */ - __IM uint32_t RTHERM; /**< Thermistor Calibration */ - uint32_t RESERVED6[80U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ -} DEVINFO_TypeDef; -/** @} End of group EFR32BG22_DEVINFO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_DEVINFO - * @{ - * @defgroup EFR32BG22_DEVINFO_BitFields DEVINFO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DEVINFO INFO */ -#define _DEVINFO_INFO_RESETVALUE 0x07000000UL /**< Default value for DEVINFO_INFO */ -#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ -#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ -#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ -#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ -#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ -#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ -#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ -#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ -#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ -#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_INFO */ -#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ - -/* Bit fields for DEVINFO PART */ -#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ -#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ -#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ -#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ -#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ -#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ -#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ -#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ -#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ -#define _DEVINFO_PART_FAMILY_PG 0x00000005UL /**< Mode PG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ -#define DEVINFO_PART_FAMILY_PG (_DEVINFO_PART_FAMILY_PG << 24) /**< Shifted mode PG for DEVINFO_PART */ - -/* Bit fields for DEVINFO MEMINFO */ -#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ -#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ -#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ -#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ -#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ -#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ -#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ - -/* Bit fields for DEVINFO MSIZE */ -#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ -#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ -#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ -#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ -#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ -#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ -#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ -#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ - -/* Bit fields for DEVINFO PKGINFO */ -#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ -#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ -#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ -#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ -#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ -#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ -#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ -#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ -#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ - -/* Bit fields for DEVINFO CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ -#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ -#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ - -/* Bit fields for DEVINFO SWFIX */ -#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ -#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ -#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ -#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ -#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ -#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ - -/* Bit fields for DEVINFO SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_MASK 0x00333333UL /**< Mask for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ -#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ -#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ -#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ -#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ -#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ -#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ -#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ -#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ -#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ -#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ -#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ -#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ -#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ - -/* Bit fields for DEVINFO SWCAPA1 */ -#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ -#define _DEVINFO_SWCAPA1_MASK 0x00000007UL /**< Mask for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ -#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ -#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ -#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ -#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ -#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ -#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ -#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ -#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ -#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ -#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ - -/* Bit fields for DEVINFO EXTINFO */ -#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ -#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ -#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ -#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ -#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ -#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ -#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ -#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ -#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ - -/* Bit fields for DEVINFO EUI48L */ -#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ -#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ -#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ -#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ -#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ -#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ -#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ -#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ - -/* Bit fields for DEVINFO EUI48H */ -#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ -#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ -#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ -#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ -#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ -#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ -#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ -#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ - -/* Bit fields for DEVINFO EUI64L */ -#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ -#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ -#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ -#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ -#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ -#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ - -/* Bit fields for DEVINFO EUI64H */ -#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ -#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ -#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ -#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ -#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ -#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ -#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ -#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ - -/* Bit fields for DEVINFO CALTEMP */ -#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ -#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ -#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ -#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ -#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ -#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ - -/* Bit fields for DEVINFO EMUTEMP */ -#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ -#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ -#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ -#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ - -/* Bit fields for DEVINFO HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ -#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ -#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ -#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ -#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ -#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ -#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ -#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ -#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ -#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ - -/* Bit fields for DEVINFO MODULENAME0 */ -#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ -#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ -#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ -#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ -#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ -#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ -#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ -#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ -#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ -#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ -#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ - -/* Bit fields for DEVINFO MODULENAME1 */ -#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ -#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ -#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ -#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ -#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ -#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ -#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ -#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ -#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ -#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ -#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ - -/* Bit fields for DEVINFO MODULENAME2 */ -#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ -#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ -#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ -#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ -#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ -#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ -#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ -#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ -#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ -#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ -#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ - -/* Bit fields for DEVINFO MODULENAME3 */ -#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ -#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ -#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ -#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ -#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ -#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ -#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ -#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ -#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ -#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ -#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ - -/* Bit fields for DEVINFO MODULENAME4 */ -#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ -#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ -#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ -#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ -#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ -#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ -#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ -#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ -#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ -#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ -#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ - -/* Bit fields for DEVINFO MODULENAME5 */ -#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ -#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ -#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ -#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ -#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ -#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ -#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ -#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ -#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ -#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ -#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ - -/* Bit fields for DEVINFO MODULENAME6 */ -#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ -#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ -#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ -#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ -#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ -#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ -#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ -#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ -#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ -#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ - -/* Bit fields for DEVINFO MODULEINFO */ -#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ -#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ -#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ -#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ -#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ -#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ -#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ -#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ -#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ -#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ -#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ -#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ -#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ -#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ -#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ -#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ -#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ -#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ -#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ -#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ -#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ -#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ -#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ -#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ -#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ -#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ -#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ - -/* Bit fields for DEVINFO MODXOCAL */ -#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ -#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ -#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ -#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ - -/* Bit fields for DEVINFO IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ -#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ -#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ - -/* Bit fields for DEVINFO IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ -#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ -#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ - -/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ -#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ -#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ -#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ -#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ -#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ -#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ - -/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ -#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ - -/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ -#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ -#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ - -/* Bit fields for DEVINFO LEGACY */ -#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ -#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ -#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ - -/* Bit fields for DEVINFO RTHERM */ -#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ -#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ -#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ - -/** @} End of group EFR32BG22_DEVINFO_BitFields */ -/** @} End of group EFR32BG22_DEVINFO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_DEVINFO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 DEVINFO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_DEVINFO_H +#define EFR32BG22_DEVINFO_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_DEVINFO DEVINFO + * @{ + * @brief EFR32BG22 DEVINFO Register Declaration. + *****************************************************************************/ + +/** DEVINFO HFRCODPLLCAL Register Group Declaration. */ +typedef struct { + __IM uint32_t HFRCODPLLCAL; /**< HFRCODPLL Calibration */ +} DEVINFO_HFRCODPLLCAL_TypeDef; + +/** DEVINFO HFRCOEM23CAL Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOEM23CAL_TypeDef; + +/** DEVINFO HFRCOSECAL Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} DEVINFO_HFRCOSECAL_TypeDef; + +/** DEVINFO Register Declaration. */ +typedef struct { + __IM uint32_t INFO; /**< DI Information */ + __IM uint32_t PART; /**< Part Info */ + __IM uint32_t MEMINFO; /**< Memory Info */ + __IM uint32_t MSIZE; /**< Memory Size */ + __IM uint32_t PKGINFO; /**< Misc Device Info */ + __IM uint32_t CUSTOMINFO; /**< Custom Part Info */ + __IM uint32_t SWFIX; /**< SW Fix Register */ + __IM uint32_t SWCAPA0; /**< Software Restriction */ + __IM uint32_t SWCAPA1; /**< Software Restriction */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t EXTINFO; /**< External Component Info */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IM uint32_t EUI48L; /**< EUI 48 Low */ + __IM uint32_t EUI48H; /**< EUI 48 High */ + __IM uint32_t EUI64L; /**< EUI64 Low */ + __IM uint32_t EUI64H; /**< EUI64 High */ + __IM uint32_t CALTEMP; /**< Calibration temperature Information */ + __IM uint32_t EMUTEMP; /**< EMU Temperature Sensor Calibration Information */ + DEVINFO_HFRCODPLLCAL_TypeDef HFRCODPLLCAL[18U]; /**< */ + DEVINFO_HFRCOEM23CAL_TypeDef HFRCOEM23CAL[18U]; /**< */ + DEVINFO_HFRCOSECAL_TypeDef HFRCOSECAL[18U]; /**< */ + __IM uint32_t MODULENAME0; /**< Module Name Information */ + __IM uint32_t MODULENAME1; /**< Module Name Information */ + __IM uint32_t MODULENAME2; /**< Module Name Information */ + __IM uint32_t MODULENAME3; /**< Module Name Information */ + __IM uint32_t MODULENAME4; /**< Module Name Information */ + __IM uint32_t MODULENAME5; /**< Module Name Information */ + __IM uint32_t MODULENAME6; /**< Module Name Information */ + __IM uint32_t MODULEINFO; /**< Module Information */ + __IM uint32_t MODXOCAL; /**< Module External Oscillator Calibration Information */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IM uint32_t IADC0GAIN0; /**< IADC Gain Calibration */ + __IM uint32_t IADC0GAIN1; /**< IADC Gain Calibration */ + __IM uint32_t IADC0OFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0NORMALOFFSETCAL1; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL0; /**< IADC Offset Calibration */ + __IM uint32_t IADC0HISPDOFFSETCAL1; /**< IADC Offset Calibration */ + uint32_t RESERVED4[24U]; /**< Reserved for future use */ + __IM uint32_t LEGACY; /**< Legacy Device Info */ + uint32_t RESERVED5[23U]; /**< Reserved for future use */ + __IM uint32_t RTHERM; /**< Thermistor Calibration */ + uint32_t RESERVED6[80U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ +} DEVINFO_TypeDef; +/** @} End of group EFR32BG22_DEVINFO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_DEVINFO + * @{ + * @defgroup EFR32BG22_DEVINFO_BitFields DEVINFO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DEVINFO INFO */ +#define _DEVINFO_INFO_RESETVALUE 0x07000000UL /**< Default value for DEVINFO_INFO */ +#define _DEVINFO_INFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_INFO */ +#define _DEVINFO_INFO_CRC_SHIFT 0 /**< Shift value for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_MASK 0xFFFFUL /**< Bit mask for DEVINFO_CRC */ +#define _DEVINFO_INFO_CRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_CRC_DEFAULT (_DEVINFO_INFO_CRC_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_PRODREV_SHIFT 16 /**< Shift value for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PRODREV */ +#define _DEVINFO_INFO_PRODREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_PRODREV_DEFAULT (_DEVINFO_INFO_PRODREV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_INFO */ +#define _DEVINFO_INFO_DEVINFOREV_SHIFT 24 /**< Shift value for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_MASK 0xFF000000UL /**< Bit mask for DEVINFO_DEVINFOREV */ +#define _DEVINFO_INFO_DEVINFOREV_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_INFO */ +#define DEVINFO_INFO_DEVINFOREV_DEFAULT (_DEVINFO_INFO_DEVINFOREV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_INFO */ + +/* Bit fields for DEVINFO PART */ +#define _DEVINFO_PART_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PART */ +#define _DEVINFO_PART_MASK 0x3F3FFFFFUL /**< Mask for DEVINFO_PART */ +#define _DEVINFO_PART_DEVICENUM_SHIFT 0 /**< Shift value for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_DEVICENUM */ +#define _DEVINFO_PART_DEVICENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_DEVICENUM_DEFAULT (_DEVINFO_PART_DEVICENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILYNUM_SHIFT 16 /**< Shift value for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_MASK 0x3F0000UL /**< Bit mask for DEVINFO_FAMILYNUM */ +#define _DEVINFO_PART_FAMILYNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILYNUM_DEFAULT (_DEVINFO_PART_FAMILYNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_SHIFT 24 /**< Shift value for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_MASK 0x3F000000UL /**< Bit mask for DEVINFO_FAMILY */ +#define _DEVINFO_PART_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_FG 0x00000000UL /**< Mode FG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_MG 0x00000001UL /**< Mode MG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_BG 0x00000002UL /**< Mode BG for DEVINFO_PART */ +#define _DEVINFO_PART_FAMILY_PG 0x00000005UL /**< Mode PG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_DEFAULT (_DEVINFO_PART_FAMILY_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_FG (_DEVINFO_PART_FAMILY_FG << 24) /**< Shifted mode FG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_MG (_DEVINFO_PART_FAMILY_MG << 24) /**< Shifted mode MG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_BG (_DEVINFO_PART_FAMILY_BG << 24) /**< Shifted mode BG for DEVINFO_PART */ +#define DEVINFO_PART_FAMILY_PG (_DEVINFO_PART_FAMILY_PG << 24) /**< Shifted mode PG for DEVINFO_PART */ + +/* Bit fields for DEVINFO MEMINFO */ +#define _DEVINFO_MEMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT 0 /**< Shift value for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK 0xFFUL /**< Bit mask for DEVINFO_FLASHPAGESIZE */ +#define _DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_FLASHPAGESIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_SHIFT 8 /**< Shift value for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_MASK 0xFF00UL /**< Bit mask for DEVINFO_UDPAGESIZE */ +#define _DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT (_DEVINFO_MEMINFO_UDPAGESIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ +#define _DEVINFO_MEMINFO_DILEN_SHIFT 16 /**< Shift value for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_DILEN */ +#define _DEVINFO_MEMINFO_DILEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MEMINFO */ +#define DEVINFO_MEMINFO_DILEN_DEFAULT (_DEVINFO_MEMINFO_DILEN_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MEMINFO */ + +/* Bit fields for DEVINFO MSIZE */ +#define _DEVINFO_MSIZE_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_MASK 0x07FFFFFFUL /**< Mask for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for DEVINFO_FLASH */ +#define _DEVINFO_MSIZE_FLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_FLASH_DEFAULT (_DEVINFO_MSIZE_FLASH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ +#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_MASK 0x7FF0000UL /**< Bit mask for DEVINFO_SRAM */ +#define _DEVINFO_MSIZE_SRAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_MSIZE */ +#define DEVINFO_MSIZE_SRAM_DEFAULT (_DEVINFO_MSIZE_SRAM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MSIZE */ + +/* Bit fields for DEVINFO PKGINFO */ +#define _DEVINFO_PKGINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_SHIFT 0 /**< Shift value for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMPGRADE */ +#define _DEVINFO_PKGINFO_TEMPGRADE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_DEFAULT (_DEVINFO_PKGINFO_TEMPGRADE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO85 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO125 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N40TO105 (_DEVINFO_PKGINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_TEMPGRADE_N0TO70 (_DEVINFO_PKGINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_SHIFT 8 /**< Shift value for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for DEVINFO_PKGTYPE */ +#define _DEVINFO_PKGINFO_PKGTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_DEFAULT (_DEVINFO_PKGINFO_PKGTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_WLCSP (_DEVINFO_PKGINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_BGA (_DEVINFO_PKGINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFN (_DEVINFO_PKGINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PKGTYPE_QFP (_DEVINFO_PKGINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_PKGINFO */ +#define _DEVINFO_PKGINFO_PINCOUNT_SHIFT 16 /**< Shift value for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for DEVINFO_PINCOUNT */ +#define _DEVINFO_PKGINFO_PINCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_PKGINFO */ +#define DEVINFO_PKGINFO_PINCOUNT_DEFAULT (_DEVINFO_PKGINFO_PINCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_PKGINFO */ + +/* Bit fields for DEVINFO CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_PARTNO */ +#define _DEVINFO_CUSTOMINFO_PARTNO_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CUSTOMINFO */ +#define DEVINFO_CUSTOMINFO_PARTNO_DEFAULT (_DEVINFO_CUSTOMINFO_PARTNO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_CUSTOMINFO */ + +/* Bit fields for DEVINFO SWFIX */ +#define _DEVINFO_SWFIX_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_SWFIX */ +#define _DEVINFO_SWFIX_RSV_SHIFT 0 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_SWFIX_RSV_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for DEVINFO_SWFIX */ +#define DEVINFO_SWFIX_RSV_DEFAULT (_DEVINFO_SWFIX_RSV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWFIX */ + +/* Bit fields for DEVINFO SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_MASK 0x00333333UL /**< Mask for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_SHIFT 0 /**< Shift value for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_MASK 0x3UL /**< Bit mask for DEVINFO_ZIGBEE */ +#define _DEVINFO_SWCAPA0_ZIGBEE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_DEFAULT (_DEVINFO_SWCAPA0_ZIGBEE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL0 << 0) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL1 << 0) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL2 << 0) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 (_DEVINFO_SWCAPA0_ZIGBEE_LEVEL3 << 0) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_SHIFT 4 /**< Shift value for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_MASK 0x30UL /**< Bit mask for DEVINFO_THREAD */ +#define _DEVINFO_SWCAPA0_THREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_THREAD_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_DEFAULT (_DEVINFO_SWCAPA0_THREAD_DEFAULT << 4) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL0 (_DEVINFO_SWCAPA0_THREAD_LEVEL0 << 4) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL1 (_DEVINFO_SWCAPA0_THREAD_LEVEL1 << 4) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL2 (_DEVINFO_SWCAPA0_THREAD_LEVEL2 << 4) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_THREAD_LEVEL3 (_DEVINFO_SWCAPA0_THREAD_LEVEL3 << 4) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_SHIFT 8 /**< Shift value for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_MASK 0x300UL /**< Bit mask for DEVINFO_RF4CE */ +#define _DEVINFO_SWCAPA0_RF4CE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_RF4CE_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_DEFAULT (_DEVINFO_SWCAPA0_RF4CE_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL0 (_DEVINFO_SWCAPA0_RF4CE_LEVEL0 << 8) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL1 (_DEVINFO_SWCAPA0_RF4CE_LEVEL1 << 8) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL2 (_DEVINFO_SWCAPA0_RF4CE_LEVEL2 << 8) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_RF4CE_LEVEL3 (_DEVINFO_SWCAPA0_RF4CE_LEVEL3 << 8) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_SHIFT 12 /**< Shift value for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_MASK 0x3000UL /**< Bit mask for DEVINFO_BTSMART */ +#define _DEVINFO_SWCAPA0_BTSMART_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_BTSMART_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_DEFAULT (_DEVINFO_SWCAPA0_BTSMART_DEFAULT << 12) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL0 (_DEVINFO_SWCAPA0_BTSMART_LEVEL0 << 12) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL1 (_DEVINFO_SWCAPA0_BTSMART_LEVEL1 << 12) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL2 (_DEVINFO_SWCAPA0_BTSMART_LEVEL2 << 12) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_BTSMART_LEVEL3 (_DEVINFO_SWCAPA0_BTSMART_LEVEL3 << 12) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_SHIFT 16 /**< Shift value for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_MASK 0x30000UL /**< Bit mask for DEVINFO_CONNECT */ +#define _DEVINFO_SWCAPA0_CONNECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_CONNECT_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_DEFAULT (_DEVINFO_SWCAPA0_CONNECT_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL0 (_DEVINFO_SWCAPA0_CONNECT_LEVEL0 << 16) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL1 (_DEVINFO_SWCAPA0_CONNECT_LEVEL1 << 16) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL2 (_DEVINFO_SWCAPA0_CONNECT_LEVEL2 << 16) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_CONNECT_LEVEL3 (_DEVINFO_SWCAPA0_CONNECT_LEVEL3 << 16) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_SHIFT 20 /**< Shift value for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_MASK 0x300000UL /**< Bit mask for DEVINFO_SRI */ +#define _DEVINFO_SWCAPA0_SRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL0 0x00000000UL /**< Mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL1 0x00000001UL /**< Mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL2 0x00000002UL /**< Mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define _DEVINFO_SWCAPA0_SRI_LEVEL3 0x00000003UL /**< Mode LEVEL3 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_DEFAULT (_DEVINFO_SWCAPA0_SRI_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL0 (_DEVINFO_SWCAPA0_SRI_LEVEL0 << 20) /**< Shifted mode LEVEL0 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL1 (_DEVINFO_SWCAPA0_SRI_LEVEL1 << 20) /**< Shifted mode LEVEL1 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL2 (_DEVINFO_SWCAPA0_SRI_LEVEL2 << 20) /**< Shifted mode LEVEL2 for DEVINFO_SWCAPA0 */ +#define DEVINFO_SWCAPA0_SRI_LEVEL3 (_DEVINFO_SWCAPA0_SRI_LEVEL3 << 20) /**< Shifted mode LEVEL3 for DEVINFO_SWCAPA0 */ + +/* Bit fields for DEVINFO SWCAPA1 */ +#define _DEVINFO_SWCAPA1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_SWCAPA1 */ +#define _DEVINFO_SWCAPA1_MASK 0x00000007UL /**< Mask for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN (0x1UL << 0) /**< RF-MCU */ +#define _DEVINFO_SWCAPA1_RFMCUEN_SHIFT 0 /**< Shift value for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_MASK 0x1UL /**< Bit mask for DEVINFO_RFMCUEN */ +#define _DEVINFO_SWCAPA1_RFMCUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_RFMCUEN_DEFAULT (_DEVINFO_SWCAPA1_RFMCUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN (0x1UL << 1) /**< NCP */ +#define _DEVINFO_SWCAPA1_NCPEN_SHIFT 1 /**< Shift value for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_MASK 0x2UL /**< Bit mask for DEVINFO_NCPEN */ +#define _DEVINFO_SWCAPA1_NCPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_NCPEN_DEFAULT (_DEVINFO_SWCAPA1_NCPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN (0x1UL << 2) /**< Gateway */ +#define _DEVINFO_SWCAPA1_GWEN_SHIFT 2 /**< Shift value for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_MASK 0x4UL /**< Bit mask for DEVINFO_GWEN */ +#define _DEVINFO_SWCAPA1_GWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_SWCAPA1 */ +#define DEVINFO_SWCAPA1_GWEN_DEFAULT (_DEVINFO_SWCAPA1_GWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_SWCAPA1 */ + +/* Bit fields for DEVINFO EXTINFO */ +#define _DEVINFO_EXTINFO_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_EXTINFO_TYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_DEFAULT (_DEVINFO_EXTINFO_TYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for DEVINFO_CONNECTION */ +#define _DEVINFO_EXTINFO_CONNECTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000000UL /**< Mode SPI for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_DEFAULT (_DEVINFO_EXTINFO_CONNECTION_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ +#define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for DEVINFO_REV */ +#define _DEVINFO_EXTINFO_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EXTINFO */ +#define DEVINFO_EXTINFO_REV_DEFAULT (_DEVINFO_EXTINFO_REV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EXTINFO */ + +/* Bit fields for DEVINFO EUI48L */ +#define _DEVINFO_EUI48L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEID */ +#define _DEVINFO_EUI48L_UNIQUEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_UNIQUEID_DEFAULT (_DEVINFO_EUI48L_UNIQUEID_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ +#define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for DEVINFO_OUI48L */ +#define _DEVINFO_EUI48L_OUI48L_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48L */ +#define DEVINFO_EUI48L_OUI48L_DEFAULT (_DEVINFO_EUI48L_OUI48L_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_EUI48L */ + +/* Bit fields for DEVINFO EUI48H */ +#define _DEVINFO_EUI48H_RESETVALUE 0xFFFF0000UL /**< Default value for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OUI48H */ +#define _DEVINFO_EUI48H_OUI48H_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_OUI48H_DEFAULT (_DEVINFO_EUI48H_OUI48H_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ +#define _DEVINFO_EUI48H_RESERVED_SHIFT 16 /**< Shift value for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RESERVED */ +#define _DEVINFO_EUI48H_RESERVED_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_EUI48H */ +#define DEVINFO_EUI48H_RESERVED_DEFAULT (_DEVINFO_EUI48H_RESERVED_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_EUI48H */ + +/* Bit fields for DEVINFO EUI64L */ +#define _DEVINFO_EUI64L_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64L */ +#define _DEVINFO_EUI64L_UNIQUEL_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for DEVINFO_UNIQUEL */ +#define _DEVINFO_EUI64L_UNIQUEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64L */ +#define DEVINFO_EUI64L_UNIQUEL_DEFAULT (_DEVINFO_EUI64L_UNIQUEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64L */ + +/* Bit fields for DEVINFO EUI64H */ +#define _DEVINFO_EUI64H_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_UNIQUEH_SHIFT 0 /**< Shift value for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_MASK 0xFFUL /**< Bit mask for DEVINFO_UNIQUEH */ +#define _DEVINFO_EUI64H_UNIQUEH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_UNIQUEH_DEFAULT (_DEVINFO_EUI64H_UNIQUEH_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ +#define _DEVINFO_EUI64H_OUI64_SHIFT 8 /**< Shift value for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_MASK 0xFFFFFF00UL /**< Bit mask for DEVINFO_OUI64 */ +#define _DEVINFO_EUI64H_OUI64_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EUI64H */ +#define DEVINFO_EUI64H_OUI64_DEFAULT (_DEVINFO_EUI64H_OUI64_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_EUI64H */ + +/* Bit fields for DEVINFO CALTEMP */ +#define _DEVINFO_CALTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_CALTEMP */ +#define _DEVINFO_CALTEMP_TEMP_SHIFT 0 /**< Shift value for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_MASK 0xFFUL /**< Bit mask for DEVINFO_TEMP */ +#define _DEVINFO_CALTEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_CALTEMP */ +#define DEVINFO_CALTEMP_TEMP_DEFAULT (_DEVINFO_CALTEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_CALTEMP */ + +/* Bit fields for DEVINFO EMUTEMP */ +#define _DEVINFO_EMUTEMP_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_MASK 0x1FFF07FCUL /**< Mask for DEVINFO_EMUTEMP */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 2 /**< Shift value for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0x7FCUL /**< Bit mask for DEVINFO_EMUTEMPROOM */ +#define _DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_EMUTEMP */ +#define DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT (_DEVINFO_EMUTEMP_EMUTEMPROOM_DEFAULT << 2) /**< Shifted mode DEFAULT for DEVINFO_EMUTEMP */ + +/* Bit fields for DEVINFO HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_MASK 0xFFFFBF7FUL /**< Mask for DEVINFO_HFRCODPLLCAL */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_SHIFT 0 /**< Shift value for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_MASK 0x7FUL /**< Bit mask for DEVINFO_TUNING */ +#define _DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_SHIFT 8 /**< Shift value for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for DEVINFO_FINETUNING */ +#define _DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT (_DEVINFO_HFRCODPLLCAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define DEVINFO_HFRCODPLLCAL_LDOHP (0x1UL << 15) /**< */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_SHIFT 15 /**< Shift value for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_MASK 0x8000UL /**< Bit mask for DEVINFO_LDOHP */ +#define _DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT (_DEVINFO_HFRCODPLLCAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_SHIFT 16 /**< Shift value for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for DEVINFO_FREQRANGE */ +#define _DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT (_DEVINFO_HFRCODPLLCAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_SHIFT 21 /**< Shift value for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for DEVINFO_CMPBIAS */ +#define _DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_SHIFT 24 /**< Shift value for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for DEVINFO_CLKDIV */ +#define _DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT (_DEVINFO_HFRCODPLLCAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_SHIFT 26 /**< Shift value for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for DEVINFO_CMPSEL */ +#define _DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT (_DEVINFO_HFRCODPLLCAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_SHIFT 28 /**< Shift value for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for DEVINFO_IREFTC */ +#define _DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_HFRCODPLLCAL */ +#define DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT (_DEVINFO_HFRCODPLLCAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for DEVINFO_HFRCODPLLCAL*/ + +/* Bit fields for DEVINFO MODULENAME0 */ +#define _DEVINFO_MODULENAME0_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME0 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR1 */ +#define _DEVINFO_MODULENAME0_MODCHAR1_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR1_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR2_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR2 */ +#define _DEVINFO_MODULENAME0_MODCHAR2_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR2_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR2_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR3_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR3 */ +#define _DEVINFO_MODULENAME0_MODCHAR3_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR3_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR3_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ +#define _DEVINFO_MODULENAME0_MODCHAR4_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR4 */ +#define _DEVINFO_MODULENAME0_MODCHAR4_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME0 */ +#define DEVINFO_MODULENAME0_MODCHAR4_DEFAULT (_DEVINFO_MODULENAME0_MODCHAR4_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME0*/ + +/* Bit fields for DEVINFO MODULENAME1 */ +#define _DEVINFO_MODULENAME1_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME1 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR5 */ +#define _DEVINFO_MODULENAME1_MODCHAR5_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR5_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR5_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR6_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR6 */ +#define _DEVINFO_MODULENAME1_MODCHAR6_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR6_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR6_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR7_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR7 */ +#define _DEVINFO_MODULENAME1_MODCHAR7_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR7_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR7_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ +#define _DEVINFO_MODULENAME1_MODCHAR8_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR8 */ +#define _DEVINFO_MODULENAME1_MODCHAR8_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME1 */ +#define DEVINFO_MODULENAME1_MODCHAR8_DEFAULT (_DEVINFO_MODULENAME1_MODCHAR8_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME1*/ + +/* Bit fields for DEVINFO MODULENAME2 */ +#define _DEVINFO_MODULENAME2_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME2 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR9 */ +#define _DEVINFO_MODULENAME2_MODCHAR9_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR9_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR9_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR10_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR10 */ +#define _DEVINFO_MODULENAME2_MODCHAR10_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR10_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR10_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR11_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR11 */ +#define _DEVINFO_MODULENAME2_MODCHAR11_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR11_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR11_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ +#define _DEVINFO_MODULENAME2_MODCHAR12_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR12 */ +#define _DEVINFO_MODULENAME2_MODCHAR12_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME2 */ +#define DEVINFO_MODULENAME2_MODCHAR12_DEFAULT (_DEVINFO_MODULENAME2_MODCHAR12_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME2*/ + +/* Bit fields for DEVINFO MODULENAME3 */ +#define _DEVINFO_MODULENAME3_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME3 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR13 */ +#define _DEVINFO_MODULENAME3_MODCHAR13_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR13_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR13_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR14_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR14 */ +#define _DEVINFO_MODULENAME3_MODCHAR14_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR14_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR14_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR15_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR15 */ +#define _DEVINFO_MODULENAME3_MODCHAR15_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR15_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR15_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ +#define _DEVINFO_MODULENAME3_MODCHAR16_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR16 */ +#define _DEVINFO_MODULENAME3_MODCHAR16_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME3 */ +#define DEVINFO_MODULENAME3_MODCHAR16_DEFAULT (_DEVINFO_MODULENAME3_MODCHAR16_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME3*/ + +/* Bit fields for DEVINFO MODULENAME4 */ +#define _DEVINFO_MODULENAME4_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME4 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR17 */ +#define _DEVINFO_MODULENAME4_MODCHAR17_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR17_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR17_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR18_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR18 */ +#define _DEVINFO_MODULENAME4_MODCHAR18_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR18_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR18_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR19_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR19 */ +#define _DEVINFO_MODULENAME4_MODCHAR19_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR19_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR19_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ +#define _DEVINFO_MODULENAME4_MODCHAR20_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR20 */ +#define _DEVINFO_MODULENAME4_MODCHAR20_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME4 */ +#define DEVINFO_MODULENAME4_MODCHAR20_DEFAULT (_DEVINFO_MODULENAME4_MODCHAR20_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME4*/ + +/* Bit fields for DEVINFO MODULENAME5 */ +#define _DEVINFO_MODULENAME5_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME5 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR21 */ +#define _DEVINFO_MODULENAME5_MODCHAR21_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR21_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR21_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR22_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR22 */ +#define _DEVINFO_MODULENAME5_MODCHAR22_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR22_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR22_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR23_SHIFT 16 /**< Shift value for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_MASK 0xFF0000UL /**< Bit mask for DEVINFO_MODCHAR23 */ +#define _DEVINFO_MODULENAME5_MODCHAR23_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR23_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR23_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ +#define _DEVINFO_MODULENAME5_MODCHAR24_SHIFT 24 /**< Shift value for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_MASK 0xFF000000UL /**< Bit mask for DEVINFO_MODCHAR24 */ +#define _DEVINFO_MODULENAME5_MODCHAR24_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME5 */ +#define DEVINFO_MODULENAME5_MODCHAR24_DEFAULT (_DEVINFO_MODULENAME5_MODCHAR24_DEFAULT << 24) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME5*/ + +/* Bit fields for DEVINFO MODULENAME6 */ +#define _DEVINFO_MODULENAME6_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULENAME6 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_SHIFT 0 /**< Shift value for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_MASK 0xFFUL /**< Bit mask for DEVINFO_MODCHAR25 */ +#define _DEVINFO_MODULENAME6_MODCHAR25_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR25_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR25_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_MODCHAR26_SHIFT 8 /**< Shift value for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_MASK 0xFF00UL /**< Bit mask for DEVINFO_MODCHAR26 */ +#define _DEVINFO_MODULENAME6_MODCHAR26_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_MODCHAR26_DEFAULT (_DEVINFO_MODULENAME6_MODCHAR26_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ +#define _DEVINFO_MODULENAME6_RSV_SHIFT 16 /**< Shift value for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_RSV */ +#define _DEVINFO_MODULENAME6_RSV_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for DEVINFO_MODULENAME6 */ +#define DEVINFO_MODULENAME6_RSV_DEFAULT (_DEVINFO_MODULENAME6_RSV_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULENAME6*/ + +/* Bit fields for DEVINFO MODULEINFO */ +#define _DEVINFO_MODULEINFO_RESETVALUE 0xFFFFFFFFUL /**< Default value for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HWREV_SHIFT 0 /**< Shift value for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_MASK 0x1FUL /**< Bit mask for DEVINFO_HWREV */ +#define _DEVINFO_MODULEINFO_HWREV_DEFAULT 0x0000001FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HWREV_DEFAULT (_DEVINFO_MODULEINFO_HWREV_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_SHIFT 5 /**< Shift value for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_MASK 0xE0UL /**< Bit mask for DEVINFO_ANTENNA */ +#define _DEVINFO_MODULEINFO_ANTENNA_DEFAULT 0x00000007UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_BUILTIN 0x00000000UL /**< Mode BUILTIN for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_CONNECTOR 0x00000001UL /**< Mode CONNECTOR for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_RFPAD 0x00000002UL /**< Mode RFPAD for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_ANTENNA_INVERTEDF 0x00000003UL /**< Mode INVERTEDF for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_DEFAULT (_DEVINFO_MODULEINFO_ANTENNA_DEFAULT << 5) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_BUILTIN (_DEVINFO_MODULEINFO_ANTENNA_BUILTIN << 5) /**< Shifted mode BUILTIN for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_CONNECTOR (_DEVINFO_MODULEINFO_ANTENNA_CONNECTOR << 5) /**< Shifted mode CONNECTOR for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_ANTENNA_RFPAD (_DEVINFO_MODULEINFO_ANTENNA_RFPAD << 5) /**< Shifted mode RFPAD for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_ANTENNA_INVERTEDF (_DEVINFO_MODULEINFO_ANTENNA_INVERTEDF << 5) /**< Shifted mode INVERTEDF for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBER_SHIFT 8 /**< Shift value for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_MASK 0x7F00UL /**< Bit mask for DEVINFO_MODNUMBER */ +#define _DEVINFO_MODULEINFO_MODNUMBER_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBER_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBER_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE (0x1UL << 15) /**< */ +#define _DEVINFO_MODULEINFO_TYPE_SHIFT 15 /**< Shift value for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_MASK 0x8000UL /**< Bit mask for DEVINFO_TYPE */ +#define _DEVINFO_MODULEINFO_TYPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_PCB 0x00000000UL /**< Mode PCB for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_TYPE_SIP 0x00000001UL /**< Mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_DEFAULT (_DEVINFO_MODULEINFO_TYPE_DEFAULT << 15) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_PCB (_DEVINFO_MODULEINFO_TYPE_PCB << 15) /**< Shifted mode PCB for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_TYPE_SIP (_DEVINFO_MODULEINFO_TYPE_SIP << 15) /**< Shifted mode SIP for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO (0x1UL << 16) /**< */ +#define _DEVINFO_MODULEINFO_LFXO_SHIFT 16 /**< Shift value for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_MASK 0x10000UL /**< Bit mask for DEVINFO_LFXO */ +#define _DEVINFO_MODULEINFO_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_NONE 0x00000000UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXO_PRESENT 0x00000001UL /**< Mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_DEFAULT (_DEVINFO_MODULEINFO_LFXO_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_NONE (_DEVINFO_MODULEINFO_LFXO_NONE << 16) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXO_PRESENT (_DEVINFO_MODULEINFO_LFXO_PRESENT << 16) /**< Shifted mode PRESENT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS (0x1UL << 17) /**< */ +#define _DEVINFO_MODULEINFO_EXPRESS_SHIFT 17 /**< Shift value for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_MASK 0x20000UL /**< Bit mask for DEVINFO_EXPRESS */ +#define _DEVINFO_MODULEINFO_EXPRESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_SUPPORTED 0x00000000UL /**< Mode SUPPORTED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXPRESS_NONE 0x00000001UL /**< Mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_DEFAULT (_DEVINFO_MODULEINFO_EXPRESS_DEFAULT << 17) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXPRESS_SUPPORTED (_DEVINFO_MODULEINFO_EXPRESS_SUPPORTED << 17) /**< Shifted mode SUPPORTED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXPRESS_NONE (_DEVINFO_MODULEINFO_EXPRESS_NONE << 17) /**< Shifted mode NONE for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL (0x1UL << 18) /**< */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_SHIFT 18 /**< Shift value for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_MASK 0x40000UL /**< Bit mask for DEVINFO_LFXOCALVAL */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_LFXOCALVAL_DEFAULT << 18) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_VALID (_DEVINFO_MODULEINFO_LFXOCALVAL_VALID << 18) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_LFXOCALVAL_NOTVALID << 18) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_HFXOCALVAL (0x1UL << 19) /**< */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_SHIFT 19 /**< Shift value for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_MASK 0x80000UL /**< Bit mask for DEVINFO_HFXOCALVAL */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_VALID 0x00000000UL /**< Mode VALID for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID 0x00000001UL /**< Mode NOTVALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT (_DEVINFO_MODULEINFO_HFXOCALVAL_DEFAULT << 19) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_VALID (_DEVINFO_MODULEINFO_HFXOCALVAL_VALID << 19) /**< Shifted mode VALID for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID (_DEVINFO_MODULEINFO_HFXOCALVAL_NOTVALID << 19) /**< Shifted mode NOTVALID for DEVINFO_MODULEINFO*/ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_SHIFT 20 /**< Shift value for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_MASK 0x1FF00000UL /**< Bit mask for DEVINFO_MODNUMBERMSB */ +#define _DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT 0x000001FFUL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT (_DEVINFO_MODULEINFO_MODNUMBERMSB_DEFAULT << 20) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC (0x1UL << 29) /**< */ +#define _DEVINFO_MODULEINFO_PADCDC_SHIFT 29 /**< Shift value for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_MASK 0x20000000UL /**< Bit mask for DEVINFO_PADCDC */ +#define _DEVINFO_MODULEINFO_PADCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_VDCDC 0x00000000UL /**< Mode VDCDC for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PADCDC_OTHER 0x00000001UL /**< Mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_DEFAULT (_DEVINFO_MODULEINFO_PADCDC_DEFAULT << 29) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_VDCDC (_DEVINFO_MODULEINFO_PADCDC_VDCDC << 29) /**< Shifted mode VDCDC for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PADCDC_OTHER (_DEVINFO_MODULEINFO_PADCDC_OTHER << 29) /**< Shifted mode OTHER for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED (0x1UL << 30) /**< */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_SHIFT 30 /**< Shift value for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_MASK 0x40000000UL /**< Bit mask for DEVINFO_PHYLIMITED */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_LIMITED 0x00000000UL /**< Mode LIMITED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED 0x00000001UL /**< Mode UNLIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT (_DEVINFO_MODULEINFO_PHYLIMITED_DEFAULT << 30) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_LIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_LIMITED << 30) /**< Shifted mode LIMITED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED (_DEVINFO_MODULEINFO_PHYLIMITED_UNLIMITED << 30) /**< Shifted mode UNLIMITED for DEVINFO_MODULEINFO*/ +#define DEVINFO_MODULEINFO_EXTVALID (0x1UL << 31) /**< */ +#define _DEVINFO_MODULEINFO_EXTVALID_SHIFT 31 /**< Shift value for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_MASK 0x80000000UL /**< Bit mask for DEVINFO_EXTVALID */ +#define _DEVINFO_MODULEINFO_EXTVALID_DEFAULT 0x00000001UL /**< Mode DEFAULT for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUSED 0x00000000UL /**< Mode EXTUSED for DEVINFO_MODULEINFO */ +#define _DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED 0x00000001UL /**< Mode EXTUNUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_DEFAULT (_DEVINFO_MODULEINFO_EXTVALID_DEFAULT << 31) /**< Shifted mode DEFAULT for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUSED << 31) /**< Shifted mode EXTUSED for DEVINFO_MODULEINFO */ +#define DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED (_DEVINFO_MODULEINFO_EXTVALID_EXTUNUSED << 31) /**< Shifted mode EXTUNUSED for DEVINFO_MODULEINFO*/ + +/* Bit fields for DEVINFO MODXOCAL */ +#define _DEVINFO_MODXOCAL_RESETVALUE 0x007FFFFFUL /**< Default value for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_MASK 0x007FFFFFUL /**< Mask for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT 0 /**< Shift value for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK 0xFFUL /**< Bit mask for DEVINFO_HFXOCTUNEXIANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT 8 /**< Shift value for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK 0xFF00UL /**< Bit mask for DEVINFO_HFXOCTUNEXOANA */ +#define _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT 0x000000FFUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT (_DEVINFO_MODXOCAL_HFXOCTUNEXOANA_DEFAULT << 8) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT 16 /**< Shift value for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK 0x7F0000UL /**< Bit mask for DEVINFO_LFXOCAPTUNE */ +#define _DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT 0x0000007FUL /**< Mode DEFAULT for DEVINFO_MODXOCAL */ +#define DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT (_DEVINFO_MODXOCAL_LFXOCAPTUNE_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_MODXOCAL */ + +/* Bit fields for DEVINFO IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA1 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA1_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA2 */ +#define _DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN0 */ +#define DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT (_DEVINFO_IADC0GAIN0_GAINCANA2_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN0 */ + +/* Bit fields for DEVINFO IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT 0 /**< Shift value for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_MASK 0xFFFFUL /**< Bit mask for DEVINFO_GAINCANA3 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA3_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT 16 /**< Shift value for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_GAINCANA4 */ +#define _DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0GAIN1 */ +#define DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT (_DEVINFO_IADC0GAIN1_GAINCANA4_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0GAIN1 */ + +/* Bit fields for DEVINFO IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0OFFSETCAL0 */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANABASE */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA1HIACC */ +#define _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0OFFSETCAL0 */ +#define DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT (_DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0OFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL0 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ +#define DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0NORMALOFFSETCAL1 */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3NORM */ +#define _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ +#define DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT (_DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0NORMALOFFSETCAL1*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL0 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA1HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT 16 /**< Shift value for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_MASK 0xFFFF0000UL /**< Bit mask for DEVINFO_OFFSETANA2HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ +#define DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL0*/ + +/* Bit fields for DEVINFO IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_MASK 0x0000FFFFUL /**< Mask for DEVINFO_IADC0HISPDOFFSETCAL1 */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_SHIFT 0 /**< Shift value for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK 0xFFFFUL /**< Bit mask for DEVINFO_OFFSETANA3HISPD */ +#define _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ +#define DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT (_DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_IADC0HISPDOFFSETCAL1*/ + +/* Bit fields for DEVINFO LEGACY */ +#define _DEVINFO_LEGACY_RESETVALUE 0x00800000UL /**< Default value for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_MASK 0x00FF0000UL /**< Mask for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SHIFT 16 /**< Shift value for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_MASK 0xFF0000UL /**< Bit mask for DEVINFO_DEVICEFAMILY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT 0x00000080UL /**< Mode DEFAULT for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P 0x00000034UL /**< Mode EFR32MG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B 0x00000035UL /**< Mode EFR32MG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V 0x00000036UL /**< Mode EFR32MG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P 0x00000037UL /**< Mode EFR32BG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B 0x00000038UL /**< Mode EFR32BG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V 0x00000039UL /**< Mode EFR32BG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P 0x0000003DUL /**< Mode EFR32FG14P for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B 0x0000003EUL /**< Mode EFR32FG14B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V 0x0000003FUL /**< Mode EFR32FG14V for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B 0x00000064UL /**< Mode EFM32GG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B 0x00000067UL /**< Mode EFM32TG11B for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_LEGACY */ +#define _DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 0x00000080UL /**< Mode SERIES2V0 for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT (_DEVINFO_LEGACY_DEVICEFAMILY_DEFAULT << 16) /**< Shifted mode DEFAULT for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14P << 16) /**< Shifted mode EFR32MG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14B << 16) /**< Shifted mode EFR32MG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32MG14V << 16) /**< Shifted mode EFR32MG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14P << 16) /**< Shifted mode EFR32BG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14B << 16) /**< Shifted mode EFR32BG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32BG14V << 16) /**< Shifted mode EFR32BG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14P << 16) /**< Shifted mode EFR32FG14P for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14B << 16) /**< Shifted mode EFR32FG14B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V (_DEVINFO_LEGACY_DEVICEFAMILY_EFR32FG14V << 16) /**< Shifted mode EFR32FG14V for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32G (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32GG11B << 16) /**< Shifted mode EFM32GG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B (_DEVINFO_LEGACY_DEVICEFAMILY_EFM32TG11B << 16) /**< Shifted mode EFM32TG11B for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG (_DEVINFO_LEGACY_DEVICEFAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_LEGACY */ +#define DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 (_DEVINFO_LEGACY_DEVICEFAMILY_SERIES2V0 << 16) /**< Shifted mode SERIES2V0 for DEVINFO_LEGACY */ + +/* Bit fields for DEVINFO RTHERM */ +#define _DEVINFO_RTHERM_RESETVALUE 0x00000000UL /**< Default value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_MASK 0x0000FFFFUL /**< Mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_SHIFT 0 /**< Shift value for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_MASK 0xFFFFUL /**< Bit mask for DEVINFO_RTHERM */ +#define _DEVINFO_RTHERM_RTHERM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DEVINFO_RTHERM */ +#define DEVINFO_RTHERM_RTHERM_DEFAULT (_DEVINFO_RTHERM_RTHERM_DEFAULT << 0) /**< Shifted mode DEFAULT for DEVINFO_RTHERM */ + +/** @} End of group EFR32BG22_DEVINFO_BitFields */ +/** @} End of group EFR32BG22_DEVINFO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_DEVINFO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h index 4fab470..8405f74 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dma_descriptor.h @@ -1,59 +1,59 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 DMA descriptor bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_DMA_DESCRIPTOR_H -#define EFR32BG22_DMA_DESCRIPTOR_H - -#if defined(__ICCARM__) -#pragma system_include /* Treat file as system include file. */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#pragma clang system_header /* Treat file as system include file. */ -#endif - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup DMA_DESCRIPTOR DMA Descriptor - * @{ - *****************************************************************************/ -/** DMA_DESCRIPTOR Register Declaration */ -typedef struct { - /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ - /* pointer and referenced memory are declared volatile. */ - __IOM uint32_t CTRL; /**< DMA control register */ - __IOM void * __IOM SRC; /**< DMA source address */ - __IOM void * __IOM DST; /**< DMA destination address */ - __IOM void * __IOM LINK; /**< DMA link address */ -} DMA_DESCRIPTOR_TypeDef; /**< @} */ - -/** @} End of group Parts */ - -#endif // EFR32BG22_DMA_DESCRIPTOR_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 DMA descriptor bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_DMA_DESCRIPTOR_H +#define EFR32BG22_DMA_DESCRIPTOR_H + +#if defined(__ICCARM__) +#pragma system_include /* Treat file as system include file. */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang system_header /* Treat file as system include file. */ +#endif + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup DMA_DESCRIPTOR DMA Descriptor + * @{ + *****************************************************************************/ +/** DMA_DESCRIPTOR Register Declaration */ +typedef struct { + /* Note! Use of double __IOM (volatile) qualifier to ensure that both */ + /* pointer and referenced memory are declared volatile. */ + __IOM uint32_t CTRL; /**< DMA control register */ + __IOM void * __IOM SRC; /**< DMA source address */ + __IOM void * __IOM DST; /**< DMA destination address */ + __IOM void * __IOM LINK; /**< DMA link address */ +} DMA_DESCRIPTOR_TypeDef; /**< @} */ + +/** @} End of group Parts */ + +#endif // EFR32BG22_DMA_DESCRIPTOR_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h index 710cc24..10384f6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_dpll.h @@ -1,227 +1,227 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 DPLL register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_DPLL_H -#define EFR32BG22_DPLL_H -#define DPLL_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_DPLL DPLL - * @{ - * @brief EFR32BG22 DPLL Register Declaration. - *****************************************************************************/ - -/** DPLL Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CFG; /**< Config */ - __IOM uint32_t CFG1; /**< Config1 */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IM uint32_t STATUS; /**< Status */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CFG_SET; /**< Config */ - __IOM uint32_t CFG1_SET; /**< Config1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IM uint32_t STATUS_SET; /**< Status */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CFG_CLR; /**< Config */ - __IOM uint32_t CFG1_CLR; /**< Config1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IM uint32_t STATUS_CLR; /**< Status */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CFG_TGL; /**< Config */ - __IOM uint32_t CFG1_TGL; /**< Config1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IM uint32_t STATUS_TGL; /**< Status */ - uint32_t RESERVED6[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock */ -} DPLL_TypeDef; -/** @} End of group EFR32BG22_DPLL */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_DPLL - * @{ - * @defgroup EFR32BG22_DPLL_BitFields DPLL Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for DPLL IPVERSION */ -#define _DPLL_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ -#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IPVERSION */ -#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ - -/* Bit fields for DPLL EN */ -#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ -#define _DPLL_EN_MASK 0x00000001UL /**< Mask for DPLL_EN */ -#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ -#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ -#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ -#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ - -/* Bit fields for DPLL CFG */ -#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ -#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ -#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ -#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ -#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ -#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ -#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ -#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ -#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ -#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ -#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ -#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ -#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ -#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ -#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ -#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ -#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ - -/* Bit fields for DPLL CFG1 */ -#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ -#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ -#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ -#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ -#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ -#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ -#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ -#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ -#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ - -/* Bit fields for DPLL IF */ -#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ -#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ -#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ -#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ -#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ -#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ -#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ - -/* Bit fields for DPLL IEN */ -#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ -#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ -#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ -#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ -#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ -#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ -#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ -#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ -#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ - -/* Bit fields for DPLL STATUS */ -#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ -#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ -#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ -#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ -#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ -#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ -#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ -#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ -#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ -#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ -#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ - -/* Bit fields for DPLL LOCK */ -#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ -#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ -#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ -#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ -#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ - -/** @} End of group EFR32BG22_DPLL_BitFields */ -/** @} End of group EFR32BG22_DPLL */ -/** @} End of group Parts */ - -#endif // EFR32BG22_DPLL_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 DPLL register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_DPLL_H +#define EFR32BG22_DPLL_H +#define DPLL_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_DPLL DPLL + * @{ + * @brief EFR32BG22 DPLL Register Declaration. + *****************************************************************************/ + +/** DPLL Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CFG; /**< Config */ + __IOM uint32_t CFG1; /**< Config1 */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IM uint32_t STATUS; /**< Status */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CFG_SET; /**< Config */ + __IOM uint32_t CFG1_SET; /**< Config1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IM uint32_t STATUS_SET; /**< Status */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CFG_CLR; /**< Config */ + __IOM uint32_t CFG1_CLR; /**< Config1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IM uint32_t STATUS_CLR; /**< Status */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CFG_TGL; /**< Config */ + __IOM uint32_t CFG1_TGL; /**< Config1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IM uint32_t STATUS_TGL; /**< Status */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock */ +} DPLL_TypeDef; +/** @} End of group EFR32BG22_DPLL */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_DPLL + * @{ + * @defgroup EFR32BG22_DPLL_BitFields DPLL Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for DPLL IPVERSION */ +#define _DPLL_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DPLL_IPVERSION */ +#define _DPLL_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IPVERSION */ +#define DPLL_IPVERSION_IPVERSION_DEFAULT (_DPLL_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IPVERSION */ + +/* Bit fields for DPLL EN */ +#define _DPLL_EN_RESETVALUE 0x00000000UL /**< Default value for DPLL_EN */ +#define _DPLL_EN_MASK 0x00000001UL /**< Mask for DPLL_EN */ +#define DPLL_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _DPLL_EN_EN_SHIFT 0 /**< Shift value for DPLL_EN */ +#define _DPLL_EN_EN_MASK 0x1UL /**< Bit mask for DPLL_EN */ +#define _DPLL_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_EN */ +#define DPLL_EN_EN_DEFAULT (_DPLL_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_EN */ + +/* Bit fields for DPLL CFG */ +#define _DPLL_CFG_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG */ +#define _DPLL_CFG_MASK 0x00000047UL /**< Mask for DPLL_CFG */ +#define DPLL_CFG_MODE (0x1UL << 0) /**< Operating Mode Control */ +#define _DPLL_CFG_MODE_SHIFT 0 /**< Shift value for DPLL_MODE */ +#define _DPLL_CFG_MODE_MASK 0x1UL /**< Bit mask for DPLL_MODE */ +#define _DPLL_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define _DPLL_CFG_MODE_FLL 0x00000000UL /**< Mode FLL for DPLL_CFG */ +#define _DPLL_CFG_MODE_PLL 0x00000001UL /**< Mode PLL for DPLL_CFG */ +#define DPLL_CFG_MODE_DEFAULT (_DPLL_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_MODE_FLL (_DPLL_CFG_MODE_FLL << 0) /**< Shifted mode FLL for DPLL_CFG */ +#define DPLL_CFG_MODE_PLL (_DPLL_CFG_MODE_PLL << 0) /**< Shifted mode PLL for DPLL_CFG */ +#define DPLL_CFG_EDGESEL (0x1UL << 1) /**< Reference Edge Select */ +#define _DPLL_CFG_EDGESEL_SHIFT 1 /**< Shift value for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_MASK 0x2UL /**< Bit mask for DPLL_EDGESEL */ +#define _DPLL_CFG_EDGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_EDGESEL_DEFAULT (_DPLL_CFG_EDGESEL_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER (0x1UL << 2) /**< Automatic Recovery Control */ +#define _DPLL_CFG_AUTORECOVER_SHIFT 2 /**< Shift value for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_MASK 0x4UL /**< Bit mask for DPLL_AUTORECOVER */ +#define _DPLL_CFG_AUTORECOVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_AUTORECOVER_DEFAULT (_DPLL_CFG_AUTORECOVER_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN (0x1UL << 6) /**< Dither Enable Control */ +#define _DPLL_CFG_DITHEN_SHIFT 6 /**< Shift value for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_MASK 0x40UL /**< Bit mask for DPLL_DITHEN */ +#define _DPLL_CFG_DITHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG */ +#define DPLL_CFG_DITHEN_DEFAULT (_DPLL_CFG_DITHEN_DEFAULT << 6) /**< Shifted mode DEFAULT for DPLL_CFG */ + +/* Bit fields for DPLL CFG1 */ +#define _DPLL_CFG1_RESETVALUE 0x00000000UL /**< Default value for DPLL_CFG1 */ +#define _DPLL_CFG1_MASK 0x0FFF0FFFUL /**< Mask for DPLL_CFG1 */ +#define _DPLL_CFG1_M_SHIFT 0 /**< Shift value for DPLL_M */ +#define _DPLL_CFG1_M_MASK 0xFFFUL /**< Bit mask for DPLL_M */ +#define _DPLL_CFG1_M_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_M_DEFAULT (_DPLL_CFG1_M_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_CFG1 */ +#define _DPLL_CFG1_N_SHIFT 16 /**< Shift value for DPLL_N */ +#define _DPLL_CFG1_N_MASK 0xFFF0000UL /**< Bit mask for DPLL_N */ +#define _DPLL_CFG1_N_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_CFG1 */ +#define DPLL_CFG1_N_DEFAULT (_DPLL_CFG1_N_DEFAULT << 16) /**< Shifted mode DEFAULT for DPLL_CFG1 */ + +/* Bit fields for DPLL IF */ +#define _DPLL_IF_RESETVALUE 0x00000000UL /**< Default value for DPLL_IF */ +#define _DPLL_IF_MASK 0x00000007UL /**< Mask for DPLL_IF */ +#define DPLL_IF_LOCK (0x1UL << 0) /**< Lock Interrupt Flag */ +#define _DPLL_IF_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IF_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IF_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCK_DEFAULT (_DPLL_IF_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW (0x1UL << 1) /**< Lock Failure Low Interrupt Flag */ +#define _DPLL_IF_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IF_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILLOW_DEFAULT (_DPLL_IF_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH (0x1UL << 2) /**< Lock Failure High Interrupt Flag */ +#define _DPLL_IF_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IF_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IF */ +#define DPLL_IF_LOCKFAILHIGH_DEFAULT (_DPLL_IF_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IF */ + +/* Bit fields for DPLL IEN */ +#define _DPLL_IEN_RESETVALUE 0x00000000UL /**< Default value for DPLL_IEN */ +#define _DPLL_IEN_MASK 0x00000007UL /**< Mask for DPLL_IEN */ +#define DPLL_IEN_LOCK (0x1UL << 0) /**< LOCK interrupt Enable */ +#define _DPLL_IEN_LOCK_SHIFT 0 /**< Shift value for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_MASK 0x1UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_IEN_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCK_DEFAULT (_DPLL_IEN_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW (0x1UL << 1) /**< LOCKFAILLOW Interrupe Enable */ +#define _DPLL_IEN_LOCKFAILLOW_SHIFT 1 /**< Shift value for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_MASK 0x2UL /**< Bit mask for DPLL_LOCKFAILLOW */ +#define _DPLL_IEN_LOCKFAILLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILLOW_DEFAULT (_DPLL_IEN_LOCKFAILLOW_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH (0x1UL << 2) /**< LOCKFAILHIGH Interrupt Enable */ +#define _DPLL_IEN_LOCKFAILHIGH_SHIFT 2 /**< Shift value for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_MASK 0x4UL /**< Bit mask for DPLL_LOCKFAILHIGH */ +#define _DPLL_IEN_LOCKFAILHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_IEN */ +#define DPLL_IEN_LOCKFAILHIGH_DEFAULT (_DPLL_IEN_LOCKFAILHIGH_DEFAULT << 2) /**< Shifted mode DEFAULT for DPLL_IEN */ + +/* Bit fields for DPLL STATUS */ +#define _DPLL_STATUS_RESETVALUE 0x00000000UL /**< Default value for DPLL_STATUS */ +#define _DPLL_STATUS_MASK 0x80000003UL /**< Mask for DPLL_STATUS */ +#define DPLL_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _DPLL_STATUS_RDY_SHIFT 0 /**< Shift value for DPLL_RDY */ +#define _DPLL_STATUS_RDY_MASK 0x1UL /**< Bit mask for DPLL_RDY */ +#define _DPLL_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_RDY_DEFAULT (_DPLL_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS (0x1UL << 1) /**< Enable Status */ +#define _DPLL_STATUS_ENS_SHIFT 1 /**< Shift value for DPLL_ENS */ +#define _DPLL_STATUS_ENS_MASK 0x2UL /**< Bit mask for DPLL_ENS */ +#define _DPLL_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_ENS_DEFAULT (_DPLL_STATUS_ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _DPLL_STATUS_LOCK_SHIFT 31 /**< Shift value for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for DPLL_LOCK */ +#define _DPLL_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DPLL_STATUS */ +#define _DPLL_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_DEFAULT (_DPLL_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_UNLOCKED (_DPLL_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for DPLL_STATUS */ +#define DPLL_STATUS_LOCK_LOCKED (_DPLL_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for DPLL_STATUS */ + +/* Bit fields for DPLL LOCK */ +#define _DPLL_LOCK_RESETVALUE 0x00007102UL /**< Default value for DPLL_LOCK */ +#define _DPLL_LOCK_MASK 0x0000FFFFUL /**< Mask for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DPLL_LOCKKEY */ +#define _DPLL_LOCK_LOCKKEY_DEFAULT 0x00007102UL /**< Mode DEFAULT for DPLL_LOCK */ +#define _DPLL_LOCK_LOCKKEY_UNLOCK 0x00007102UL /**< Mode UNLOCK for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_DEFAULT (_DPLL_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DPLL_LOCK */ +#define DPLL_LOCK_LOCKKEY_UNLOCK (_DPLL_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for DPLL_LOCK */ + +/** @} End of group EFR32BG22_DPLL_BitFields */ +/** @} End of group EFR32BG22_DPLL */ +/** @} End of group Parts */ + +#endif // EFR32BG22_DPLL_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h index 18bbb8b..4c1fa23 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_emu.h @@ -1,738 +1,738 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 EMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_EMU_H -#define EFR32BG22_EMU_H -#define EMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_EMU EMU - * @{ - * @brief EFR32BG22 EMU Register Declaration. - *****************************************************************************/ - -/** EMU Register Declaration. */ -typedef struct { - uint32_t RESERVED0[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED3[7U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< EMU Configuration lock register */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL; /**< EM4 Control */ - __IOM uint32_t CMD; /**< EMU Command register */ - __IOM uint32_t CTRL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< EMU Status register */ - __IM uint32_t TEMP; /**< Temperature */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE; /**< Reset cause */ - uint32_t RESERVED6[2U]; /**< Reserved for future use */ - __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ - uint32_t RESERVED7[6U]; /**< Reserved for future use */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - uint32_t RESERVED9[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED10[958U]; /**< Reserved for future use */ - uint32_t RESERVED11[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED12[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ - uint32_t RESERVED13[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ - uint32_t RESERVED14[7U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ - __IOM uint32_t CMD_SET; /**< EMU Command register */ - __IOM uint32_t CTRL_SET; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ - uint32_t RESERVED15[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< EMU Status register */ - __IM uint32_t TEMP_SET; /**< Temperature */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ - uint32_t RESERVED17[2U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ - uint32_t RESERVED18[6U]; /**< Reserved for future use */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - uint32_t RESERVED20[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED21[958U]; /**< Reserved for future use */ - uint32_t RESERVED22[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED23[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ - uint32_t RESERVED24[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ - uint32_t RESERVED25[7U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ - __IOM uint32_t CMD_CLR; /**< EMU Command register */ - __IOM uint32_t CTRL_CLR; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ - uint32_t RESERVED26[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< EMU Status register */ - __IM uint32_t TEMP_CLR; /**< Temperature */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ - uint32_t RESERVED28[2U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ - uint32_t RESERVED29[6U]; /**< Reserved for future use */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - uint32_t RESERVED31[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ - uint32_t RESERVED32[958U]; /**< Reserved for future use */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ - uint32_t RESERVED34[3U]; /**< Reserved for future use */ - __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ - uint32_t RESERVED35[6U]; /**< Reserved for future use */ - __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ - __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ - uint32_t RESERVED36[7U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ - __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ - __IOM uint32_t CMD_TGL; /**< EMU Command register */ - __IOM uint32_t CTRL_TGL; /**< EMU Control register */ - __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ - uint32_t RESERVED37[2U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< EMU Status register */ - __IM uint32_t TEMP_TGL; /**< Temperature */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ - __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ - uint32_t RESERVED39[2U]; /**< Reserved for future use */ - __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ - __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ - uint32_t RESERVED40[6U]; /**< Reserved for future use */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - uint32_t RESERVED42[15U]; /**< Reserved for future use */ - __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ - __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ -} EMU_TypeDef; -/** @} End of group EFR32BG22_EMU */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_EMU - * @{ - * @defgroup EFR32BG22_EMU_BitFields EMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for EMU DECBOD */ -#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ -#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ -#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ -#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ -#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ -#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ -#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ -#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ -#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ -#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ -#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ - -/* Bit fields for EMU BOD3SENSE */ -#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ -#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ -#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ -#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ -#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ -#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ -#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ - -/* Bit fields for EMU VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ -#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ -#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ -#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ - -/* Bit fields for EMU PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN 0x00000000UL /**< Mode RETAIN for EMU_PD1PARETCTRL */ -#define _EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN 0x00000001UL /**< Mode NORETAIN for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN << 0) /**< Shifted mode RETAIN for EMU_PD1PARETCTRL */ -#define EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN << 0) /**< Shifted mode NORETAIN for EMU_PD1PARETCTRL */ - -/* Bit fields for EMU LOCK */ -#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ -#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ -#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ -#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ - -/* Bit fields for EMU IF */ -#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ -#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ -#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ -#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ -#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ -#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ -#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ -#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ - -/* Bit fields for EMU IEN */ -#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ -#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ -#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ -#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ -#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ -#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ -#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ -#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ -#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ -#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ -#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ - -/* Bit fields for EMU EM4CTRL */ -#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ -#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ -#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ -#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ -#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ -#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ - -/* Bit fields for EMU CMD */ -#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ -#define _EMU_CMD_MASK 0x00020E12UL /**< Mask for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ -#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ -#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ -#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ -#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ -#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ -#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ -#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ -#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ -#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ -#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ -#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ - -/* Bit fields for EMU CTRL */ -#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ -#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ -#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ -#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ -#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ -#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ -#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ -#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ -#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ -#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ -#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ -#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ -#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ -#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ -#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ -#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ -#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ -#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ - -/* Bit fields for EMU TEMPLIMITS */ -#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ -#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ -#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ -#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ -#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ - -/* Bit fields for EMU STATUS */ -#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ -#define _EMU_STATUS_MASK 0xFF0054FFUL /**< Mask for EMU_STATUS */ -#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ -#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ -#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ -#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ -#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ -#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ -#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ -#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ -#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ -#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ -#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ -#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ -#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ -#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ -#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ -#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ -#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ -#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ -#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ -#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ -#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ -#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ -#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ -#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ -#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ -#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ - -/* Bit fields for EMU TEMP */ -#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ -#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ -#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ -#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ -#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ -#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ -#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ -#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ -#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ - -/* Bit fields for EMU RSTCTRL */ -#define _EMU_RSTCTRL_RESETVALUE 0x40010407UL /**< Default value for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_MASK 0xC001C5CFUL /**< Mask for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ -#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ -#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ -#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ -#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ -#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ -#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ -#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ -#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DCIRMODE (0x1UL << 16) /**< DCI System reset */ -#define _EMU_RSTCTRL_DCIRMODE_SHIFT 16 /**< Shift value for EMU_DCIRMODE */ -#define _EMU_RSTCTRL_DCIRMODE_MASK 0x10000UL /**< Bit mask for EMU_DCIRMODE */ -#define _EMU_RSTCTRL_DCIRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DCIRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ -#define _EMU_RSTCTRL_DCIRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DCIRMODE_DEFAULT (_EMU_RSTCTRL_DCIRMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DCIRMODE_DISABLED (_EMU_RSTCTRL_DCIRMODE_DISABLED << 16) /**< Shifted mode DISABLED for EMU_RSTCTRL */ -#define EMU_RSTCTRL_DCIRMODE_ENABLED (_EMU_RSTCTRL_DCIRMODE_ENABLED << 16) /**< Shifted mode ENABLED for EMU_RSTCTRL */ - -/* Bit fields for EMU RSTCAUSE */ -#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ -#define _EMU_RSTCAUSE_MASK 0x8001FFFFUL /**< Mask for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ -#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ -#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ -#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ -#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ -#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ -#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ -#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ -#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ -#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ -#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ -#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ -#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ -#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ -#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ -#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ -#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ -#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ -#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ -#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ -#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ -#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ -#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ -#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DCI (0x1UL << 16) /**< DCI reset */ -#define _EMU_RSTCAUSE_DCI_SHIFT 16 /**< Shift value for EMU_DCI */ -#define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ -#define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ -#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ -#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ -#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ - -/* Bit fields for EMU DGIF */ -#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ -#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ -#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ -#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ -#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ -#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ -#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ -#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ -#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ -#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ -#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ - -/* Bit fields for EMU DGIEN */ -#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ -#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ -#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ -#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ -#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ -#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ -#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ -#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ -#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ - -/* Bit fields for EMU EFPIF */ -#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ -#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ -#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ -#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ -#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ - -/* Bit fields for EMU EFPIEN */ -#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ -#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ -#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ -#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ -#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ - -/** @} End of group EFR32BG22_EMU_BitFields */ -/** @} End of group EFR32BG22_EMU */ -/** @} End of group Parts */ - -#endif // EFR32BG22_EMU_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 EMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_EMU_H +#define EFR32BG22_EMU_H +#define EMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_EMU EMU + * @{ + * @brief EFR32BG22 EMU Register Declaration. + *****************************************************************************/ + +/** EMU Register Declaration. */ +typedef struct { + uint32_t RESERVED0[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE; /**< BOD3SENSE Control register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED3[7U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< EMU Configuration lock register */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL; /**< EM4 Control */ + __IOM uint32_t CMD; /**< EMU Command register */ + __IOM uint32_t CTRL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS; /**< EMU Temperature thresholds */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< EMU Status register */ + __IM uint32_t TEMP; /**< Temperature */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE; /**< Reset cause */ + uint32_t RESERVED6[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN; /**< Interrupt Enables Debug */ + uint32_t RESERVED7[6U]; /**< Reserved for future use */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + uint32_t RESERVED9[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED10[958U]; /**< Reserved for future use */ + uint32_t RESERVED11[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_SET; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED12[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_SET; /**< BOD3SENSE Control register */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_SET; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_SET; /**< PD1 Partial Retention Control */ + uint32_t RESERVED14[7U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< EMU Configuration lock register */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_SET; /**< EM4 Control */ + __IOM uint32_t CMD_SET; /**< EMU Command register */ + __IOM uint32_t CTRL_SET; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_SET; /**< EMU Temperature thresholds */ + uint32_t RESERVED15[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< EMU Status register */ + __IM uint32_t TEMP_SET; /**< Temperature */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_SET; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_SET; /**< Reset cause */ + uint32_t RESERVED17[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_SET; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_SET; /**< Interrupt Enables Debug */ + uint32_t RESERVED18[6U]; /**< Reserved for future use */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + uint32_t RESERVED20[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_SET; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_SET; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED21[958U]; /**< Reserved for future use */ + uint32_t RESERVED22[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_CLR; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED23[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_CLR; /**< BOD3SENSE Control register */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_CLR; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_CLR; /**< PD1 Partial Retention Control */ + uint32_t RESERVED25[7U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< EMU Configuration lock register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_CLR; /**< EM4 Control */ + __IOM uint32_t CMD_CLR; /**< EMU Command register */ + __IOM uint32_t CTRL_CLR; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_CLR; /**< EMU Temperature thresholds */ + uint32_t RESERVED26[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< EMU Status register */ + __IM uint32_t TEMP_CLR; /**< Temperature */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_CLR; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_CLR; /**< Reset cause */ + uint32_t RESERVED28[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_CLR; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_CLR; /**< Interrupt Enables Debug */ + uint32_t RESERVED29[6U]; /**< Reserved for future use */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_CLR; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_CLR; /**< EFP Interrupt Enable Register */ + uint32_t RESERVED32[958U]; /**< Reserved for future use */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + __IOM uint32_t DECBOD_TGL; /**< DECOUPLE LVBOD Control register */ + uint32_t RESERVED34[3U]; /**< Reserved for future use */ + __IOM uint32_t BOD3SENSE_TGL; /**< BOD3SENSE Control register */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t VREGVDDCMPCTRL_TGL; /**< DC-DC VREGVDD Comparator Control Register */ + __IOM uint32_t PD1PARETCTRL_TGL; /**< PD1 Partial Retention Control */ + uint32_t RESERVED36[7U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< EMU Configuration lock register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enables */ + __IOM uint32_t EM4CTRL_TGL; /**< EM4 Control */ + __IOM uint32_t CMD_TGL; /**< EMU Command register */ + __IOM uint32_t CTRL_TGL; /**< EMU Control register */ + __IOM uint32_t TEMPLIMITS_TGL; /**< EMU Temperature thresholds */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< EMU Status register */ + __IM uint32_t TEMP_TGL; /**< Temperature */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + __IOM uint32_t RSTCTRL_TGL; /**< Reset Management Control register */ + __IM uint32_t RSTCAUSE_TGL; /**< Reset cause */ + uint32_t RESERVED39[2U]; /**< Reserved for future use */ + __IOM uint32_t DGIF_TGL; /**< Interrupt Flags Debug */ + __IOM uint32_t DGIEN_TGL; /**< Interrupt Enables Debug */ + uint32_t RESERVED40[6U]; /**< Reserved for future use */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + uint32_t RESERVED42[15U]; /**< Reserved for future use */ + __IOM uint32_t EFPIF_TGL; /**< EFP Interrupt Register */ + __IOM uint32_t EFPIEN_TGL; /**< EFP Interrupt Enable Register */ +} EMU_TypeDef; +/** @} End of group EFR32BG22_EMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_EMU + * @{ + * @defgroup EFR32BG22_EMU_BitFields EMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EMU DECBOD */ +#define _EMU_DECBOD_RESETVALUE 0x00000022UL /**< Default value for EMU_DECBOD */ +#define _EMU_DECBOD_MASK 0x00000033UL /**< Mask for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN (0x1UL << 0) /**< DECBOD enable */ +#define _EMU_DECBOD_DECBODEN_SHIFT 0 /**< Shift value for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_MASK 0x1UL /**< Bit mask for EMU_DECBODEN */ +#define _EMU_DECBOD_DECBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODEN_DEFAULT (_EMU_DECBOD_DECBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK (0x1UL << 1) /**< DECBOD Mask */ +#define _EMU_DECBOD_DECBODMASK_SHIFT 1 /**< Shift value for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_MASK 0x2UL /**< Bit mask for EMU_DECBODMASK */ +#define _EMU_DECBOD_DECBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECBODMASK_DEFAULT (_EMU_DECBOD_DECBODMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN (0x1UL << 4) /**< Over Voltage Monitor enable */ +#define _EMU_DECBOD_DECOVMBODEN_SHIFT 4 /**< Shift value for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_MASK 0x10UL /**< Bit mask for EMU_DECOVMBODEN */ +#define _EMU_DECBOD_DECOVMBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODEN_DEFAULT (_EMU_DECBOD_DECOVMBODEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK (0x1UL << 5) /**< Over Voltage Monitor Mask */ +#define _EMU_DECBOD_DECOVMBODMASK_SHIFT 5 /**< Shift value for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_MASK 0x20UL /**< Bit mask for EMU_DECOVMBODMASK */ +#define _EMU_DECBOD_DECOVMBODMASK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DECBOD */ +#define EMU_DECBOD_DECOVMBODMASK_DEFAULT (_EMU_DECBOD_DECOVMBODMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DECBOD */ + +/* Bit fields for EMU BOD3SENSE */ +#define _EMU_BOD3SENSE_RESETVALUE 0x00000000UL /**< Default value for EMU_BOD3SENSE */ +#define _EMU_BOD3SENSE_MASK 0x00000077UL /**< Mask for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN (0x1UL << 0) /**< AVDD BOD enable */ +#define _EMU_BOD3SENSE_AVDDBODEN_SHIFT 0 /**< Shift value for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_MASK 0x1UL /**< Bit mask for EMU_AVDDBODEN */ +#define _EMU_BOD3SENSE_AVDDBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_AVDDBODEN_DEFAULT (_EMU_BOD3SENSE_AVDDBODEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN (0x1UL << 1) /**< VDDIO0 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_SHIFT 1 /**< Shift value for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_MASK 0x2UL /**< Bit mask for EMU_VDDIO0BODEN */ +#define _EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO0BODEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN (0x1UL << 2) /**< VDDIO1 BOD enable */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_SHIFT 2 /**< Shift value for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_MASK 0x4UL /**< Bit mask for EMU_VDDIO1BODEN */ +#define _EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BOD3SENSE */ +#define EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT (_EMU_BOD3SENSE_VDDIO1BODEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BOD3SENSE */ + +/* Bit fields for EMU VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_RESETVALUE 0x00000006UL /**< Default value for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_MASK 0x00000007UL /**< Mask for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN (0x1UL << 0) /**< VREGVDD comparator enable */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_SHIFT 0 /**< Shift value for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_MASK 0x1UL /**< Bit mask for EMU_VREGINCMPEN */ +#define _EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT (_EMU_VREGVDDCMPCTRL_VREGINCMPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT 1 /**< Shift value for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_MASK 0x6UL /**< Bit mask for EMU_THRESSEL */ +#define _EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_VREGVDDCMPCTRL */ +#define EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT (_EMU_VREGVDDCMPCTRL_THRESSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_VREGVDDCMPCTRL */ + +/* Bit fields for EMU PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_SHIFT 0 /**< Shift value for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_MASK 0xFFFFUL /**< Bit mask for EMU_PD1PARETDIS */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN 0x00000000UL /**< Mode RETAIN for EMU_PD1PARETCTRL */ +#define _EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN 0x00000001UL /**< Mode NORETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT (_EMU_PD1PARETCTRL_PD1PARETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_RETAIN << 0) /**< Shifted mode RETAIN for EMU_PD1PARETCTRL */ +#define EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN (_EMU_PD1PARETCTRL_PD1PARETDIS_NORETAIN << 0) /**< Shifted mode NORETAIN for EMU_PD1PARETCTRL */ + +/* Bit fields for EMU LOCK */ +#define _EMU_LOCK_RESETVALUE 0x0000ADE8UL /**< Default value for EMU_LOCK */ +#define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ +#define _EMU_LOCK_LOCKKEY_DEFAULT 0x0000ADE8UL /**< Mode DEFAULT for EMU_LOCK */ +#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ + +/* Bit fields for EMU IF */ +#define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ +#define _EMU_IF_MASK 0xEB070000UL /**< Mask for EMU_IF */ +#define EMU_IF_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt flag */ +#define _EMU_IF_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IF_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_AVDDBOD_DEFAULT (_EMU_IF_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt flag */ +#define _EMU_IF_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IF_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_IOVDD0BOD_DEFAULT (_EMU_IF_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt flag */ +#define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG (0x1UL << 27) /**< Temperature Average Interrupt flag */ +#define _EMU_IF_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IF_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPAVG_DEFAULT (_EMU_IF_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ +#define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ + +/* Bit fields for EMU IEN */ +#define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ +#define _EMU_IEN_MASK 0xEB070000UL /**< Mask for EMU_IEN */ +#define EMU_IEN_AVDDBOD (0x1UL << 16) /**< AVDD BOD Interrupt enable */ +#define _EMU_IEN_AVDDBOD_SHIFT 16 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_MASK 0x10000UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_IEN_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_AVDDBOD_DEFAULT (_EMU_IEN_AVDDBOD_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD (0x1UL << 17) /**< VDDIO0 BOD Interrupt enable */ +#define _EMU_IEN_IOVDD0BOD_SHIFT 17 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_MASK 0x20000UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_IEN_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_IOVDD0BOD_DEFAULT (_EMU_IEN_IOVDD0BOD_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ +#define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< Vscale done Interrupt enable */ +#define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ +#define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG (0x1UL << 27) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMPAVG_SHIFT 27 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_MASK 0x8000000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_IEN_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPAVG_DEFAULT (_EMU_IEN_TEMPAVG_DEFAULT << 27) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ +#define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ +#define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ +#define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ + +/* Bit fields for EMU EM4CTRL */ +#define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_MASK 0x00000133UL /**< Mask for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4ENTRY_SHIFT 0 /**< Shift value for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_MASK 0x3UL /**< Bit mask for EMU_EM4ENTRY */ +#define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ +#define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ +#define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU (0x1UL << 8) /**< Set BOD3SENSE as EM4 wakeup */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_SHIFT 8 /**< Shift value for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_MASK 0x100UL /**< Bit mask for EMU_BOD3SENSEEM4WU */ +#define _EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ +#define EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT (_EMU_EM4CTRL_BOD3SENSEEM4WU_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ + +/* Bit fields for EMU CMD */ +#define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ +#define _EMU_CMD_MASK 0x00020E12UL /**< Mask for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH (0x1UL << 1) /**< EM4 unlatch */ +#define _EMU_CMD_EM4UNLATCH_SHIFT 1 /**< Shift value for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_MASK 0x2UL /**< Bit mask for EMU_EM4UNLATCH */ +#define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ (0x1UL << 4) /**< Temperature Average Request */ +#define _EMU_CMD_TEMPAVGREQ_SHIFT 4 /**< Shift value for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_MASK 0x10UL /**< Bit mask for EMU_TEMPAVGREQ */ +#define _EMU_CMD_TEMPAVGREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_TEMPAVGREQ_DEFAULT (_EMU_CMD_TEMPAVGREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1 (0x1UL << 10) /**< Scale voltage to Vscale1 */ +#define _EMU_CMD_EM01VSCALE1_SHIFT 10 /**< Shift value for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_MASK 0x400UL /**< Bit mask for EMU_EM01VSCALE1 */ +#define _EMU_CMD_EM01VSCALE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE1_DEFAULT (_EMU_CMD_EM01VSCALE1_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2 (0x1UL << 11) /**< Scale voltage to Vscale2 */ +#define _EMU_CMD_EM01VSCALE2_SHIFT 11 /**< Shift value for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_MASK 0x800UL /**< Bit mask for EMU_EM01VSCALE2 */ +#define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR (0x1UL << 17) /**< Reset Cause Clear */ +#define _EMU_CMD_RSTCAUSECLR_SHIFT 17 /**< Shift value for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_MASK 0x20000UL /**< Bit mask for EMU_RSTCAUSECLR */ +#define _EMU_CMD_RSTCAUSECLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ +#define EMU_CMD_RSTCAUSECLR_DEFAULT (_EMU_CMD_RSTCAUSECLR_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_CMD */ + +/* Bit fields for EMU CTRL */ +#define _EMU_CTRL_RESETVALUE 0x00000200UL /**< Default value for EMU_CTRL */ +#define _EMU_CTRL_MASK 0xE0010309UL /**< Mask for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN (0x1UL << 0) /**< Enable debugging in EM2 */ +#define _EMU_CTRL_EM2DBGEN_SHIFT 0 /**< Shift value for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_MASK 0x1UL /**< Bit mask for EMU_EM2DBGEN */ +#define _EMU_CTRL_EM2DBGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM2DBGEN_DEFAULT (_EMU_CTRL_EM2DBGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM (0x1UL << 3) /**< Averaged Temperature samples num */ +#define _EMU_CTRL_TEMPAVGNUM_SHIFT 3 /**< Shift value for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGNUM */ +#define _EMU_CTRL_TEMPAVGNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N16 0x00000000UL /**< Mode N16 for EMU_CTRL */ +#define _EMU_CTRL_TEMPAVGNUM_N64 0x00000001UL /**< Mode N64 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_DEFAULT (_EMU_CTRL_TEMPAVGNUM_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N16 (_EMU_CTRL_TEMPAVGNUM_N16 << 3) /**< Shifted mode N16 for EMU_CTRL */ +#define EMU_CTRL_TEMPAVGNUM_N64 (_EMU_CTRL_TEMPAVGNUM_N64 << 3) /**< Shifted mode N64 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ +#define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_CTRL */ +#define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE1 (_EMU_CTRL_EM23VSCALE_VSCALE1 << 8) /**< Shifted mode VSCALE1 for EMU_CTRL */ +#define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND (0x1UL << 16) /**< Enable flash on demand wakeup */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_SHIFT 16 /**< Shift value for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_MASK 0x10000UL /**< Bit mask for EMU_FLASHPWRUPONDEMAND */ +#define _EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT (_EMU_CTRL_FLASHPWRUPONDEMAND_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN (0x1UL << 29) /**< EFP Direct Mode Enable */ +#define _EMU_CTRL_EFPDIRECTMODEEN_SHIFT 29 /**< Shift value for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_MASK 0x20000000UL /**< Bit mask for EMU_EFPDIRECTMODEEN */ +#define _EMU_CTRL_EFPDIRECTMODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDIRECTMODEEN_DEFAULT (_EMU_CTRL_EFPDIRECTMODEEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE (0x1UL << 30) /**< EFP drives DECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_SHIFT 30 /**< Shift value for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_MASK 0x40000000UL /**< Bit mask for EMU_EFPDRVDECOUPLE */ +#define _EMU_CTRL_EFPDRVDECOUPLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDECOUPLE_DEFAULT (_EMU_CTRL_EFPDRVDECOUPLE_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD (0x1UL << 31) /**< EFP drives DVDD */ +#define _EMU_CTRL_EFPDRVDVDD_SHIFT 31 /**< Shift value for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_MASK 0x80000000UL /**< Bit mask for EMU_EFPDRVDVDD */ +#define _EMU_CTRL_EFPDRVDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ +#define EMU_CTRL_EFPDRVDVDD_DEFAULT (_EMU_CTRL_EFPDRVDVDD_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_CTRL */ + +/* Bit fields for EMU TEMPLIMITS */ +#define _EMU_TEMPLIMITS_RESETVALUE 0x01FF0000UL /**< Default value for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_MASK 0x01FF01FFUL /**< Mask for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_MASK 0x1FFUL /**< Bit mask for EMU_TEMPLOW */ +#define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ +#define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 16 /**< Shift value for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0x1FF0000UL /**< Bit mask for EMU_TEMPHIGH */ +#define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000001FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ +#define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ + +/* Bit fields for EMU STATUS */ +#define _EMU_STATUS_RESETVALUE 0x00000080UL /**< Default value for EMU_STATUS */ +#define _EMU_STATUS_MASK 0xFF0054FFUL /**< Mask for EMU_STATUS */ +#define EMU_STATUS_LOCK (0x1UL << 0) /**< Lock status */ +#define _EMU_STATUS_LOCK_SHIFT 0 /**< Shift value for EMU_LOCK */ +#define _EMU_STATUS_LOCK_MASK 0x1UL /**< Bit mask for EMU_LOCK */ +#define _EMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_STATUS */ +#define _EMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_DEFAULT (_EMU_STATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_LOCK_UNLOCKED (_EMU_STATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_STATUS */ +#define EMU_STATUS_LOCK_LOCKED (_EMU_STATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE (0x1UL << 1) /**< First Temp done */ +#define _EMU_STATUS_FIRSTTEMPDONE_SHIFT 1 /**< Shift value for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_MASK 0x2UL /**< Bit mask for EMU_FIRSTTEMPDONE */ +#define _EMU_STATUS_FIRSTTEMPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_FIRSTTEMPDONE_DEFAULT (_EMU_STATUS_FIRSTTEMPDONE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE (0x1UL << 2) /**< Temp active */ +#define _EMU_STATUS_TEMPACTIVE_SHIFT 2 /**< Shift value for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_MASK 0x4UL /**< Bit mask for EMU_TEMPACTIVE */ +#define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE (0x1UL << 3) /**< Temp Average active */ +#define _EMU_STATUS_TEMPAVGACTIVE_SHIFT 3 /**< Shift value for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_MASK 0x8UL /**< Bit mask for EMU_TEMPAVGACTIVE */ +#define _EMU_STATUS_TEMPAVGACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_TEMPAVGACTIVE_DEFAULT (_EMU_STATUS_TEMPAVGACTIVE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY (0x1UL << 4) /**< Vscale busy */ +#define _EMU_STATUS_VSCALEBUSY_SHIFT 4 /**< Shift value for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_MASK 0x10UL /**< Bit mask for EMU_VSCALEBUSY */ +#define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED (0x1UL << 5) /**< Vscale failed */ +#define _EMU_STATUS_VSCALEFAILED_SHIFT 5 /**< Shift value for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_MASK 0x20UL /**< Bit mask for EMU_VSCALEFAILED */ +#define _EMU_STATUS_VSCALEFAILED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALEFAILED_DEFAULT (_EMU_STATUS_VSCALEFAILED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_SHIFT 6 /**< Shift value for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_MASK 0xC0UL /**< Bit mask for EMU_VSCALE */ +#define _EMU_STATUS_VSCALE_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE0 0x00000000UL /**< Mode VSCALE0 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE1 0x00000001UL /**< Mode VSCALE1 for EMU_STATUS */ +#define _EMU_STATUS_VSCALE_VSCALE2 0x00000002UL /**< Mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 6) /**< Shifted mode VSCALE0 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE1 (_EMU_STATUS_VSCALE_VSCALE1 << 6) /**< Shifted mode VSCALE1 for EMU_STATUS */ +#define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 6) /**< Shifted mode VSCALE2 for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE (0x1UL << 10) /**< RAC active */ +#define _EMU_STATUS_RACACTIVE_SHIFT 10 /**< Shift value for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_MASK 0x400UL /**< Bit mask for EMU_RACACTIVE */ +#define _EMU_STATUS_RACACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_RACACTIVE_DEFAULT (_EMU_STATUS_RACACTIVE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET (0x1UL << 12) /**< EM4 IO retention status */ +#define _EMU_STATUS_EM4IORET_SHIFT 12 /**< Shift value for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_MASK 0x1000UL /**< Bit mask for EMU_EM4IORET */ +#define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED (0x1UL << 14) /**< EM2 entered */ +#define _EMU_STATUS_EM2ENTERED_SHIFT 14 /**< Shift value for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_MASK 0x4000UL /**< Bit mask for EMU_EM2ENTERED */ +#define _EMU_STATUS_EM2ENTERED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ +#define EMU_STATUS_EM2ENTERED_DEFAULT (_EMU_STATUS_EM2ENTERED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_STATUS */ + +/* Bit fields for EMU TEMP */ +#define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ +#define _EMU_TEMP_MASK 0x07FF07FFUL /**< Mask for EMU_TEMP */ +#define _EMU_TEMP_TEMPLSB_SHIFT 0 /**< Shift value for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_MASK 0x3UL /**< Bit mask for EMU_TEMPLSB */ +#define _EMU_TEMP_TEMPLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPLSB_DEFAULT (_EMU_TEMP_TEMPLSB_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMP_SHIFT 2 /**< Shift value for EMU_TEMP */ +#define _EMU_TEMP_TEMP_MASK 0x7FCUL /**< Bit mask for EMU_TEMP */ +#define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_TEMP */ +#define _EMU_TEMP_TEMPAVG_SHIFT 16 /**< Shift value for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_MASK 0x7FF0000UL /**< Bit mask for EMU_TEMPAVG */ +#define _EMU_TEMP_TEMPAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ +#define EMU_TEMP_TEMPAVG_DEFAULT (_EMU_TEMP_TEMPAVG_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMP */ + +/* Bit fields for EMU RSTCTRL */ +#define _EMU_RSTCTRL_RESETVALUE 0x40010407UL /**< Default value for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_MASK 0xC001C5CFUL /**< Mask for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE (0x1UL << 0) /**< Enable WDOG0 reset */ +#define _EMU_RSTCTRL_WDOG0RMODE_SHIFT 0 /**< Shift value for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_MASK 0x1UL /**< Bit mask for EMU_WDOG0RMODE */ +#define _EMU_RSTCTRL_WDOG0RMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_WDOG0RMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DEFAULT (_EMU_RSTCTRL_WDOG0RMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_DISABLED (_EMU_RSTCTRL_WDOG0RMODE_DISABLED << 0) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_WDOG0RMODE_ENABLED (_EMU_RSTCTRL_WDOG0RMODE_ENABLED << 0) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE (0x1UL << 2) /**< Enable M33 System reset */ +#define _EMU_RSTCTRL_SYSRMODE_SHIFT 2 /**< Shift value for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_MASK 0x4UL /**< Bit mask for EMU_SYSRMODE */ +#define _EMU_RSTCTRL_SYSRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_SYSRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DEFAULT (_EMU_RSTCTRL_SYSRMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_DISABLED (_EMU_RSTCTRL_SYSRMODE_DISABLED << 2) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_SYSRMODE_ENABLED (_EMU_RSTCTRL_SYSRMODE_ENABLED << 2) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE (0x1UL << 3) /**< Enable M33 Lockup reset */ +#define _EMU_RSTCTRL_LOCKUPRMODE_SHIFT 3 /**< Shift value for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_MASK 0x8UL /**< Bit mask for EMU_LOCKUPRMODE */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_LOCKUPRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DEFAULT (_EMU_RSTCTRL_LOCKUPRMODE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_DISABLED (_EMU_RSTCTRL_LOCKUPRMODE_DISABLED << 3) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_LOCKUPRMODE_ENABLED (_EMU_RSTCTRL_LOCKUPRMODE_ENABLED << 3) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE (0x1UL << 6) /**< Enable AVDD BOD reset */ +#define _EMU_RSTCTRL_AVDDBODRMODE_SHIFT 6 /**< Shift value for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_MASK 0x40UL /**< Bit mask for EMU_AVDDBODRMODE */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_AVDDBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DEFAULT (_EMU_RSTCTRL_AVDDBODRMODE_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_DISABLED (_EMU_RSTCTRL_AVDDBODRMODE_DISABLED << 6) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_AVDDBODRMODE_ENABLED (_EMU_RSTCTRL_AVDDBODRMODE_ENABLED << 6) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE (0x1UL << 7) /**< Enable VDDIO0 BOD reset */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_SHIFT 7 /**< Shift value for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_MASK 0x80UL /**< Bit mask for EMU_IOVDD0BODRMODE */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT (_EMU_RSTCTRL_IOVDD0BODRMODE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_DISABLED << 7) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED (_EMU_RSTCTRL_IOVDD0BODRMODE_ENABLED << 7) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE (0x1UL << 10) /**< Enable DECBOD reset */ +#define _EMU_RSTCTRL_DECBODRMODE_SHIFT 10 /**< Shift value for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_MASK 0x400UL /**< Bit mask for EMU_DECBODRMODE */ +#define _EMU_RSTCTRL_DECBODRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DECBODRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DEFAULT (_EMU_RSTCTRL_DECBODRMODE_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_DISABLED (_EMU_RSTCTRL_DECBODRMODE_DISABLED << 10) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DECBODRMODE_ENABLED (_EMU_RSTCTRL_DECBODRMODE_ENABLED << 10) /**< Shifted mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE (0x1UL << 16) /**< DCI System reset */ +#define _EMU_RSTCTRL_DCIRMODE_SHIFT 16 /**< Shift value for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_MASK 0x10000UL /**< Bit mask for EMU_DCIRMODE */ +#define _EMU_RSTCTRL_DCIRMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_RSTCTRL */ +#define _EMU_RSTCTRL_DCIRMODE_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DEFAULT (_EMU_RSTCTRL_DCIRMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_DISABLED (_EMU_RSTCTRL_DCIRMODE_DISABLED << 16) /**< Shifted mode DISABLED for EMU_RSTCTRL */ +#define EMU_RSTCTRL_DCIRMODE_ENABLED (_EMU_RSTCTRL_DCIRMODE_ENABLED << 16) /**< Shifted mode ENABLED for EMU_RSTCTRL */ + +/* Bit fields for EMU RSTCAUSE */ +#define _EMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for EMU_RSTCAUSE */ +#define _EMU_RSTCAUSE_MASK 0x8001FFFFUL /**< Mask for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR (0x1UL << 0) /**< Power On Reset */ +#define _EMU_RSTCAUSE_POR_SHIFT 0 /**< Shift value for EMU_POR */ +#define _EMU_RSTCAUSE_POR_MASK 0x1UL /**< Bit mask for EMU_POR */ +#define _EMU_RSTCAUSE_POR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_POR_DEFAULT (_EMU_RSTCAUSE_POR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN (0x1UL << 1) /**< Pin Reset */ +#define _EMU_RSTCAUSE_PIN_SHIFT 1 /**< Shift value for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_MASK 0x2UL /**< Bit mask for EMU_PIN */ +#define _EMU_RSTCAUSE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_PIN_DEFAULT (_EMU_RSTCAUSE_PIN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4 (0x1UL << 2) /**< EM4 Wakeup Reset */ +#define _EMU_RSTCAUSE_EM4_SHIFT 2 /**< Shift value for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_MASK 0x4UL /**< Bit mask for EMU_EM4 */ +#define _EMU_RSTCAUSE_EM4_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_EM4_DEFAULT (_EMU_RSTCAUSE_EM4_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0 (0x1UL << 3) /**< Watchdog 0 Reset */ +#define _EMU_RSTCAUSE_WDOG0_SHIFT 3 /**< Shift value for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_MASK 0x8UL /**< Bit mask for EMU_WDOG0 */ +#define _EMU_RSTCAUSE_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_WDOG0_DEFAULT (_EMU_RSTCAUSE_WDOG0_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP (0x1UL << 5) /**< M33 Core Lockup Reset */ +#define _EMU_RSTCAUSE_LOCKUP_SHIFT 5 /**< Shift value for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_MASK 0x20UL /**< Bit mask for EMU_LOCKUP */ +#define _EMU_RSTCAUSE_LOCKUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_LOCKUP_DEFAULT (_EMU_RSTCAUSE_LOCKUP_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ (0x1UL << 6) /**< M33 Core Sys Reset */ +#define _EMU_RSTCAUSE_SYSREQ_SHIFT 6 /**< Shift value for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_MASK 0x40UL /**< Bit mask for EMU_SYSREQ */ +#define _EMU_RSTCAUSE_SYSREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_SYSREQ_DEFAULT (_EMU_RSTCAUSE_SYSREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD (0x1UL << 7) /**< HVBOD Reset */ +#define _EMU_RSTCAUSE_DVDDBOD_SHIFT 7 /**< Shift value for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_MASK 0x80UL /**< Bit mask for EMU_DVDDBOD */ +#define _EMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDBOD_DEFAULT (_EMU_RSTCAUSE_DVDDBOD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD (0x1UL << 8) /**< LEBOD Reset */ +#define _EMU_RSTCAUSE_DVDDLEBOD_SHIFT 8 /**< Shift value for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_MASK 0x100UL /**< Bit mask for EMU_DVDDLEBOD */ +#define _EMU_RSTCAUSE_DVDDLEBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DVDDLEBOD_DEFAULT (_EMU_RSTCAUSE_DVDDLEBOD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD (0x1UL << 9) /**< LVBOD Reset */ +#define _EMU_RSTCAUSE_DECBOD_SHIFT 9 /**< Shift value for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_MASK 0x200UL /**< Bit mask for EMU_DECBOD */ +#define _EMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DECBOD_DEFAULT (_EMU_RSTCAUSE_DECBOD_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD (0x1UL << 10) /**< LEBOD1 Reset */ +#define _EMU_RSTCAUSE_AVDDBOD_SHIFT 10 /**< Shift value for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_MASK 0x400UL /**< Bit mask for EMU_AVDDBOD */ +#define _EMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_AVDDBOD_DEFAULT (_EMU_RSTCAUSE_AVDDBOD_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD (0x1UL << 11) /**< LEBOD2 Reset */ +#define _EMU_RSTCAUSE_IOVDD0BOD_SHIFT 11 /**< Shift value for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_MASK 0x800UL /**< Bit mask for EMU_IOVDD0BOD */ +#define _EMU_RSTCAUSE_IOVDD0BOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_IOVDD0BOD_DEFAULT (_EMU_RSTCAUSE_IOVDD0BOD_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI (0x1UL << 16) /**< DCI reset */ +#define _EMU_RSTCAUSE_DCI_SHIFT 16 /**< Shift value for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_MASK 0x10000UL /**< Bit mask for EMU_DCI */ +#define _EMU_RSTCAUSE_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_DCI_DEFAULT (_EMU_RSTCAUSE_DCI_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN (0x1UL << 31) /**< DCDC VREGIN comparator */ +#define _EMU_RSTCAUSE_VREGIN_SHIFT 31 /**< Shift value for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_MASK 0x80000000UL /**< Bit mask for EMU_VREGIN */ +#define _EMU_RSTCAUSE_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RSTCAUSE */ +#define EMU_RSTCAUSE_VREGIN_DEFAULT (_EMU_RSTCAUSE_VREGIN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_RSTCAUSE */ + +/* Bit fields for EMU DGIF */ +#define _EMU_DGIF_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIF */ +#define _EMU_DGIF_MASK 0xE1000000UL /**< Mask for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF (0x1UL << 24) /**< EM23 Wake up Interrupt flag */ +#define _EMU_DGIF_EM23WAKEUPDGIF_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIF */ +#define _EMU_DGIF_EM23WAKEUPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_EM23WAKEUPDGIF_DEFAULT (_EMU_DGIF_EM23WAKEUPDGIF_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF (0x1UL << 29) /**< Temperature Interrupt flag */ +#define _EMU_DGIF_TEMPDGIF_SHIFT 29 /**< Shift value for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIF */ +#define _EMU_DGIF_TEMPDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPDGIF_DEFAULT (_EMU_DGIF_TEMPDGIF_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF (0x1UL << 30) /**< Temperature low Interrupt flag */ +#define _EMU_DGIF_TEMPLOWDGIF_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIF */ +#define _EMU_DGIF_TEMPLOWDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPLOWDGIF_DEFAULT (_EMU_DGIF_TEMPLOWDGIF_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF (0x1UL << 31) /**< Temperature high Interrupt flag */ +#define _EMU_DGIF_TEMPHIGHDGIF_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIF */ +#define _EMU_DGIF_TEMPHIGHDGIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIF */ +#define EMU_DGIF_TEMPHIGHDGIF_DEFAULT (_EMU_DGIF_TEMPHIGHDGIF_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIF */ + +/* Bit fields for EMU DGIEN */ +#define _EMU_DGIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_DGIEN */ +#define _EMU_DGIEN_MASK 0xE1000000UL /**< Mask for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN (0x1UL << 24) /**< EM23 Wake up Interrupt enable */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_SHIFT 24 /**< Shift value for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUPDGIEN */ +#define _EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT (_EMU_DGIEN_EM23WAKEUPDGIEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN (0x1UL << 29) /**< Temperature Interrupt enable */ +#define _EMU_DGIEN_TEMPDGIEN_SHIFT 29 /**< Shift value for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_MASK 0x20000000UL /**< Bit mask for EMU_TEMPDGIEN */ +#define _EMU_DGIEN_TEMPDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPDGIEN_DEFAULT (_EMU_DGIEN_TEMPDGIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN (0x1UL << 30) /**< Temperature low Interrupt enable */ +#define _EMU_DGIEN_TEMPLOWDGIEN_SHIFT 30 /**< Shift value for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOWDGIEN */ +#define _EMU_DGIEN_TEMPLOWDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPLOWDGIEN_DEFAULT (_EMU_DGIEN_TEMPLOWDGIEN_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN (0x1UL << 31) /**< Temperature high Interrupt enable */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_SHIFT 31 /**< Shift value for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGHDGIEN */ +#define _EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DGIEN */ +#define EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT (_EMU_DGIEN_TEMPHIGHDGIEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_DGIEN */ + +/* Bit fields for EMU EFPIF */ +#define _EMU_EFPIF_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIF */ +#define _EMU_EFPIF_MASK 0x00000001UL /**< Mask for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF (0x1UL << 0) /**< EFP Interrupt Flag */ +#define _EMU_EFPIF_EFPIF_SHIFT 0 /**< Shift value for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_MASK 0x1UL /**< Bit mask for EMU_EFPIF */ +#define _EMU_EFPIF_EFPIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIF */ +#define EMU_EFPIF_EFPIF_DEFAULT (_EMU_EFPIF_EFPIF_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIF */ + +/* Bit fields for EMU EFPIEN */ +#define _EMU_EFPIEN_RESETVALUE 0x00000000UL /**< Default value for EMU_EFPIEN */ +#define _EMU_EFPIEN_MASK 0x00000001UL /**< Mask for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN (0x1UL << 0) /**< EFP Interrupt enable */ +#define _EMU_EFPIEN_EFPIEN_SHIFT 0 /**< Shift value for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_MASK 0x1UL /**< Bit mask for EMU_EFPIEN */ +#define _EMU_EFPIEN_EFPIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EFPIEN */ +#define EMU_EFPIEN_EFPIEN_DEFAULT (_EMU_EFPIEN_EFPIEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EFPIEN */ + +/** @} End of group EFR32BG22_EMU_BitFields */ +/** @} End of group EFR32BG22_EMU */ +/** @} End of group Parts */ + +#endif // EFR32BG22_EMU_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h index 40469cf..de0a4f6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_eusart.h @@ -1,916 +1,916 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 EUSART register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_EUSART_H -#define EFR32BG22_EUSART_H -#define EUSART_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_EUSART EUSART - * @{ - * @brief EFR32BG22 EUSART Register Declaration. - *****************************************************************************/ - -/** EUSART Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG0; /**< Configuration 0 Register */ - __IOM uint32_t CFG1; /**< Configuration 1 Register */ - __IOM uint32_t FRAMECFG; /**< Frame Format Register */ - __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t RXDATA; /**< RX Data Register */ - __IM uint32_t RXDATAP; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA; /**< TX Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED0[1004U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ - __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ - __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t RXDATA_SET; /**< RX Data Register */ - __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< TX Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED1[1004U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ - __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ - __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t RXDATA_CLR; /**< RX Data Register */ - __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED2[1004U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ - __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ - __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ - __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ - __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ - __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ - __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ - __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t RXDATA_TGL; /**< RX Data Register */ - __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ -} EUSART_TypeDef; -/** @} End of group EFR32BG22_EUSART */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_EUSART - * @{ - * @defgroup EFR32BG22_EUSART_BitFields EUSART Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for EUSART IPVERSION */ -#define _EUSART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ -#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IPVERSION */ -#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ - -/* Bit fields for EUSART EN */ -#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ -#define _EUSART_EN_MASK 0x00000001UL /**< Mask for EUSART_EN */ -#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ -#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ -#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ -#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ -#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ - -/* Bit fields for EUSART CFG0 */ -#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ -#define _EUSART_CFG0_MASK 0xC1D264FEUL /**< Mask for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ -#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ -#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ -#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ -#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ -#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ -#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ -#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ -#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ -#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ -#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ -#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ -#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ -#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ -#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ -#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ -#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ -#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ -#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ -#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ -#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ -#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ -#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ -#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ - -/* Bit fields for EUSART CFG1 */ -#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ -#define _EUSART_CFG1_MASK 0x00DB8E0FUL /**< Mask for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ -#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ -#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ -#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ -#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ -#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ -#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ -#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ -#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ -#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ -#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ -#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ -#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ -#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ -#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ -#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ -#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_MASK 0x30000UL /**< Bit mask for EUSART_TXFIW */ -#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_SHIFT 19 /**< Shift value for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_MASK 0x180000UL /**< Bit mask for EUSART_RXFIW */ -#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 19) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 19) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 19) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 19) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_MASK 0xC00000UL /**< Bit mask for EUSART_RTSRXFW */ -#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ -#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ -#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ - -/* Bit fields for EUSART FRAMECFG */ -#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_MASK 0x00003303UL /**< Mask for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_MASK 0x3UL /**< Bit mask for EUSART_DATABITS */ -#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ -#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ -#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ -#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ -#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ -#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ - -/* Bit fields for EUSART IRHFCFG */ -#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ -#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ -#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ -#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ -#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ -#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ -#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ - -/* Bit fields for EUSART IRLFCFG */ -#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ -#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ -#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ -#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ -#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ - -/* Bit fields for EUSART TIMINGCFG */ -#define _EUSART_TIMINGCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_MASK 0x00000003UL /**< Mask for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ -#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ -#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ -#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ - -/* Bit fields for EUSART STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ -#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ -#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ - -/* Bit fields for EUSART SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ -#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ -#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ - -/* Bit fields for EUSART CLKDIV */ -#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ -#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ -#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ - -/* Bit fields for EUSART TRIGCTRL */ -#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ -#define _EUSART_TRIGCTRL_MASK 0x00000003UL /**< Mask for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ -#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ -#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ -#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ - -/* Bit fields for EUSART CMD */ -#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ -#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ -#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ -#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ -#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ -#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ -#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ -#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ -#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ -#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ - -/* Bit fields for EUSART RXDATA */ -#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ -#define _EUSART_RXDATA_MASK 0x000007FFUL /**< Mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATA */ -#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_PERR (0x1UL << 9) /**< Parity Error */ -#define _EUSART_RXDATA_PERR_SHIFT 9 /**< Shift value for EUSART_PERR */ -#define _EUSART_RXDATA_PERR_MASK 0x200UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_RXDATA_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_PERR_DEFAULT (_EUSART_RXDATA_PERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_FERR (0x1UL << 10) /**< Framing Error */ -#define _EUSART_RXDATA_FERR_SHIFT 10 /**< Shift value for EUSART_FERR */ -#define _EUSART_RXDATA_FERR_MASK 0x400UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_RXDATA_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ -#define EUSART_RXDATA_FERR_DEFAULT (_EUSART_RXDATA_FERR_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATA */ - -/* Bit fields for EUSART RXDATAP */ -#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_MASK 0x000007FFUL /**< Mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATAP */ -#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_PERRP (0x1UL << 9) /**< Parity Error Peek */ -#define _EUSART_RXDATAP_PERRP_SHIFT 9 /**< Shift value for EUSART_PERRP */ -#define _EUSART_RXDATAP_PERRP_MASK 0x200UL /**< Bit mask for EUSART_PERRP */ -#define _EUSART_RXDATAP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_PERRP_DEFAULT (_EUSART_RXDATAP_PERRP_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_FERRP (0x1UL << 10) /**< Framing Error Peek */ -#define _EUSART_RXDATAP_FERRP_SHIFT 10 /**< Shift value for EUSART_FERRP */ -#define _EUSART_RXDATAP_FERRP_MASK 0x400UL /**< Bit mask for EUSART_FERRP */ -#define _EUSART_RXDATAP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ -#define EUSART_RXDATAP_FERRP_DEFAULT (_EUSART_RXDATAP_FERRP_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ - -/* Bit fields for EUSART TXDATA */ -#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ -#define _EUSART_TXDATA_MASK 0x00003FFFUL /**< Mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_TXDATA */ -#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_UBRXAT (0x1UL << 9) /**< Unblock RX After Transmission */ -#define _EUSART_TXDATA_UBRXAT_SHIFT 9 /**< Shift value for EUSART_UBRXAT */ -#define _EUSART_TXDATA_UBRXAT_MASK 0x200UL /**< Bit mask for EUSART_UBRXAT */ -#define _EUSART_TXDATA_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_UBRXAT_DEFAULT (_EUSART_TXDATA_UBRXAT_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXTRIAT (0x1UL << 10) /**< Set TXTRI After Transmisssion */ -#define _EUSART_TXDATA_TXTRIAT_SHIFT 10 /**< Shift value for EUSART_TXTRIAT */ -#define _EUSART_TXDATA_TXTRIAT_MASK 0x400UL /**< Bit mask for EUSART_TXTRIAT */ -#define _EUSART_TXDATA_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXTRIAT_DEFAULT (_EUSART_TXDATA_TXTRIAT_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXBREAK (0x1UL << 11) /**< Transit Data as Break */ -#define _EUSART_TXDATA_TXBREAK_SHIFT 11 /**< Shift value for EUSART_TXBREAK */ -#define _EUSART_TXDATA_TXBREAK_MASK 0x800UL /**< Bit mask for EUSART_TXBREAK */ -#define _EUSART_TXDATA_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXBREAK_DEFAULT (_EUSART_TXDATA_TXBREAK_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDISAT (0x1UL << 12) /**< Clear TXEN After Transmission */ -#define _EUSART_TXDATA_TXDISAT_SHIFT 12 /**< Shift value for EUSART_TXDISAT */ -#define _EUSART_TXDATA_TXDISAT_MASK 0x1000UL /**< Bit mask for EUSART_TXDISAT */ -#define _EUSART_TXDATA_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_TXDISAT_DEFAULT (_EUSART_TXDATA_TXDISAT_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_RXENAT (0x1UL << 13) /**< Enable RXEN After Transmission */ -#define _EUSART_TXDATA_RXENAT_SHIFT 13 /**< Shift value for EUSART_RXENAT */ -#define _EUSART_TXDATA_RXENAT_MASK 0x2000UL /**< Bit mask for EUSART_RXENAT */ -#define _EUSART_TXDATA_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ -#define EUSART_TXDATA_RXENAT_DEFAULT (_EUSART_TXDATA_RXENAT_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_TXDATA */ - -/* Bit fields for EUSART STATUS */ -#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ -#define _EUSART_STATUS_MASK 0x010F31FBUL /**< Mask for EUSART_STATUS */ -#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ -#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ -#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ -#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ -#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ -#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ -#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ -#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ -#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ -#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_MASK 0x70000UL /**< Bit mask for EUSART_TXFCNT */ -#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 19) /**< TX FIFO Clear Busy */ -#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 19 /**< Shift value for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x80000UL /**< Bit mask for EUSART_CLEARTXBUSY */ -#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ -#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ -#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ - -/* Bit fields for EUSART IF */ -#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ -#define _EUSART_IF_MASK 0x010C377FUL /**< Mask for EUSART_IF */ -#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ -#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ -#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ -#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ -#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ -#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ -#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ -#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ -#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ -#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ - -/* Bit fields for EUSART IEN */ -#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ -#define _EUSART_IEN_MASK 0x010C377FUL /**< Mask for EUSART_IEN */ -#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ -#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ -#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ -#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ -#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ -#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ -#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ -#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ -#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ -#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ -#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ -#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ -#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ -#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ -#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ -#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ -#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ -#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ -#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ -#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ -#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ -#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ -#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ -#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ -#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ -#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ -#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ -#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ -#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ -#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ -#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ -#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ -#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ -#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ -#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ -#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ - -/* Bit fields for EUSART SYNCBUSY */ -#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ -#define _EUSART_SYNCBUSY_MASK 0x000007FFUL /**< Mask for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ -#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ -#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ -#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ -#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ -#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ -#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ -#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ -#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ -#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ -#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ -#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ -#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ -#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ -#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ -#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ -#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ -#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ -#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ -#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ -#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ - -/** @} End of group EFR32BG22_EUSART_BitFields */ -/** @} End of group EFR32BG22_EUSART */ -/** @} End of group Parts */ - -#endif // EFR32BG22_EUSART_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 EUSART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_EUSART_H +#define EFR32BG22_EUSART_H +#define EUSART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_EUSART EUSART + * @{ + * @brief EFR32BG22 EUSART Register Declaration. + *****************************************************************************/ + +/** EUSART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG0; /**< Configuration 0 Register */ + __IOM uint32_t CFG1; /**< Configuration 1 Register */ + __IOM uint32_t FRAMECFG; /**< Frame Format Register */ + __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t RXDATA; /**< RX Data Register */ + __IM uint32_t RXDATAP; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA; /**< TX Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED0[1004U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ + __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ + __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t RXDATA_SET; /**< RX Data Register */ + __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< TX Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1004U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ + __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ + __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t RXDATA_CLR; /**< RX Data Register */ + __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED2[1004U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ + __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ + __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ + __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ + __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ + __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ + __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ + __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t RXDATA_TGL; /**< RX Data Register */ + __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} EUSART_TypeDef; +/** @} End of group EFR32BG22_EUSART */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_EUSART + * @{ + * @defgroup EFR32BG22_EUSART_BitFields EUSART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for EUSART IPVERSION */ +#define _EUSART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ +#define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IPVERSION */ +#define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ + +/* Bit fields for EUSART EN */ +#define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ +#define _EUSART_EN_MASK 0x00000001UL /**< Mask for EUSART_EN */ +#define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ +#define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ +#define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ +#define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ +#define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ + +/* Bit fields for EUSART CFG0 */ +#define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ +#define _EUSART_CFG0_MASK 0xC1D264FEUL /**< Mask for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ +#define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ +#define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ +#define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ +#define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ +#define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ +#define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ +#define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ +#define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ +#define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ +#define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ +#define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ +#define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ +#define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ +#define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ +#define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ +#define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ +#define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ +#define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ +#define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ +#define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ +#define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ +#define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ +#define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ + +/* Bit fields for EUSART CFG1 */ +#define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ +#define _EUSART_CFG1_MASK 0x00DB8E0FUL /**< Mask for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ +#define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ +#define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ +#define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ +#define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ +#define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ +#define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ +#define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ +#define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ +#define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ +#define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ +#define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ +#define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ +#define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ +#define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ +#define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ +#define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_MASK 0x30000UL /**< Bit mask for EUSART_TXFIW */ +#define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_SHIFT 19 /**< Shift value for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_MASK 0x180000UL /**< Bit mask for EUSART_RXFIW */ +#define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 19) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 19) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 19) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 19) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_MASK 0xC00000UL /**< Bit mask for EUSART_RTSRXFW */ +#define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ +#define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ +#define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ + +/* Bit fields for EUSART FRAMECFG */ +#define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_MASK 0x00003303UL /**< Mask for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_MASK 0x3UL /**< Bit mask for EUSART_DATABITS */ +#define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ +#define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ +#define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ +#define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ +#define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ +#define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ + +/* Bit fields for EUSART IRHFCFG */ +#define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ +#define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ +#define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ +#define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ +#define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ +#define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ +#define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ + +/* Bit fields for EUSART IRLFCFG */ +#define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ +#define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ +#define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ +#define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ +#define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ + +/* Bit fields for EUSART TIMINGCFG */ +#define _EUSART_TIMINGCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_MASK 0x00000003UL /**< Mask for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ +#define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ +#define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ +#define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ + +/* Bit fields for EUSART STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ +#define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ +#define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ + +/* Bit fields for EUSART SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ +#define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ +#define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ + +/* Bit fields for EUSART CLKDIV */ +#define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ +#define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ +#define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ + +/* Bit fields for EUSART TRIGCTRL */ +#define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ +#define _EUSART_TRIGCTRL_MASK 0x00000003UL /**< Mask for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ +#define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ +#define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ +#define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ + +/* Bit fields for EUSART CMD */ +#define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ +#define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ +#define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ +#define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ +#define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ +#define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ +#define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ +#define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ +#define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ +#define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ + +/* Bit fields for EUSART RXDATA */ +#define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ +#define _EUSART_RXDATA_MASK 0x000007FFUL /**< Mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATA */ +#define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_PERR (0x1UL << 9) /**< Parity Error */ +#define _EUSART_RXDATA_PERR_SHIFT 9 /**< Shift value for EUSART_PERR */ +#define _EUSART_RXDATA_PERR_MASK 0x200UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_RXDATA_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_PERR_DEFAULT (_EUSART_RXDATA_PERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_FERR (0x1UL << 10) /**< Framing Error */ +#define _EUSART_RXDATA_FERR_SHIFT 10 /**< Shift value for EUSART_FERR */ +#define _EUSART_RXDATA_FERR_MASK 0x400UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_RXDATA_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ +#define EUSART_RXDATA_FERR_DEFAULT (_EUSART_RXDATA_FERR_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATA */ + +/* Bit fields for EUSART RXDATAP */ +#define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_MASK 0x000007FFUL /**< Mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATAP */ +#define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_PERRP (0x1UL << 9) /**< Parity Error Peek */ +#define _EUSART_RXDATAP_PERRP_SHIFT 9 /**< Shift value for EUSART_PERRP */ +#define _EUSART_RXDATAP_PERRP_MASK 0x200UL /**< Bit mask for EUSART_PERRP */ +#define _EUSART_RXDATAP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_PERRP_DEFAULT (_EUSART_RXDATAP_PERRP_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_FERRP (0x1UL << 10) /**< Framing Error Peek */ +#define _EUSART_RXDATAP_FERRP_SHIFT 10 /**< Shift value for EUSART_FERRP */ +#define _EUSART_RXDATAP_FERRP_MASK 0x400UL /**< Bit mask for EUSART_FERRP */ +#define _EUSART_RXDATAP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ +#define EUSART_RXDATAP_FERRP_DEFAULT (_EUSART_RXDATAP_FERRP_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ + +/* Bit fields for EUSART TXDATA */ +#define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ +#define _EUSART_TXDATA_MASK 0x00003FFFUL /**< Mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_TXDATA */ +#define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_UBRXAT (0x1UL << 9) /**< Unblock RX After Transmission */ +#define _EUSART_TXDATA_UBRXAT_SHIFT 9 /**< Shift value for EUSART_UBRXAT */ +#define _EUSART_TXDATA_UBRXAT_MASK 0x200UL /**< Bit mask for EUSART_UBRXAT */ +#define _EUSART_TXDATA_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_UBRXAT_DEFAULT (_EUSART_TXDATA_UBRXAT_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXTRIAT (0x1UL << 10) /**< Set TXTRI After Transmisssion */ +#define _EUSART_TXDATA_TXTRIAT_SHIFT 10 /**< Shift value for EUSART_TXTRIAT */ +#define _EUSART_TXDATA_TXTRIAT_MASK 0x400UL /**< Bit mask for EUSART_TXTRIAT */ +#define _EUSART_TXDATA_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXTRIAT_DEFAULT (_EUSART_TXDATA_TXTRIAT_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXBREAK (0x1UL << 11) /**< Transit Data as Break */ +#define _EUSART_TXDATA_TXBREAK_SHIFT 11 /**< Shift value for EUSART_TXBREAK */ +#define _EUSART_TXDATA_TXBREAK_MASK 0x800UL /**< Bit mask for EUSART_TXBREAK */ +#define _EUSART_TXDATA_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXBREAK_DEFAULT (_EUSART_TXDATA_TXBREAK_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDISAT (0x1UL << 12) /**< Clear TXEN After Transmission */ +#define _EUSART_TXDATA_TXDISAT_SHIFT 12 /**< Shift value for EUSART_TXDISAT */ +#define _EUSART_TXDATA_TXDISAT_MASK 0x1000UL /**< Bit mask for EUSART_TXDISAT */ +#define _EUSART_TXDATA_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_TXDISAT_DEFAULT (_EUSART_TXDATA_TXDISAT_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_RXENAT (0x1UL << 13) /**< Enable RXEN After Transmission */ +#define _EUSART_TXDATA_RXENAT_SHIFT 13 /**< Shift value for EUSART_RXENAT */ +#define _EUSART_TXDATA_RXENAT_MASK 0x2000UL /**< Bit mask for EUSART_RXENAT */ +#define _EUSART_TXDATA_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ +#define EUSART_TXDATA_RXENAT_DEFAULT (_EUSART_TXDATA_RXENAT_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_TXDATA */ + +/* Bit fields for EUSART STATUS */ +#define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ +#define _EUSART_STATUS_MASK 0x010F31FBUL /**< Mask for EUSART_STATUS */ +#define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ +#define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ +#define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ +#define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ +#define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ +#define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ +#define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ +#define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ +#define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ +#define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_MASK 0x70000UL /**< Bit mask for EUSART_TXFCNT */ +#define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY (0x1UL << 19) /**< TX FIFO Clear Busy */ +#define _EUSART_STATUS_CLEARTXBUSY_SHIFT 19 /**< Shift value for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_MASK 0x80000UL /**< Bit mask for EUSART_CLEARTXBUSY */ +#define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ +#define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ +#define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ + +/* Bit fields for EUSART IF */ +#define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ +#define _EUSART_IF_MASK 0x010C377FUL /**< Mask for EUSART_IF */ +#define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ +#define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ +#define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ +#define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ +#define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ +#define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ +#define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ +#define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ +#define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ +#define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ + +/* Bit fields for EUSART IEN */ +#define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ +#define _EUSART_IEN_MASK 0x010C377FUL /**< Mask for EUSART_IEN */ +#define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ +#define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ +#define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ +#define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ +#define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ +#define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ +#define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ +#define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ +#define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ +#define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ +#define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ +#define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ +#define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ +#define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ +#define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ +#define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ +#define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ +#define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ +#define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ +#define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ +#define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ +#define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ +#define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ +#define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ +#define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ +#define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ +#define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ +#define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ +#define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ +#define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ +#define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ +#define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ +#define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ +#define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ +#define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ +#define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ + +/* Bit fields for EUSART SYNCBUSY */ +#define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ +#define _EUSART_SYNCBUSY_MASK 0x000007FFUL /**< Mask for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ +#define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ +#define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ +#define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ +#define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ +#define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ +#define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ +#define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ +#define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ +#define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ +#define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ +#define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ +#define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ +#define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ +#define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ +#define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ +#define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ +#define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ +#define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ +#define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ +#define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ + +/** @} End of group EFR32BG22_EUSART_BitFields */ +/** @} End of group EFR32BG22_EUSART */ +/** @} End of group Parts */ + +#endif // EFR32BG22_EUSART_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h index 3a6aefe..44b8254 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_fsrco.h @@ -1,75 +1,75 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 FSRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_FSRCO_H -#define EFR32BG22_FSRCO_H -#define FSRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_FSRCO FSRCO - * @{ - * @brief EFR32BG22 FSRCO Register Declaration. - *****************************************************************************/ - -/** FSRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - uint32_t RESERVED0[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - uint32_t RESERVED1[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - uint32_t RESERVED2[1023U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ -} FSRCO_TypeDef; -/** @} End of group EFR32BG22_FSRCO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_FSRCO - * @{ - * @defgroup EFR32BG22_FSRCO_BitFields FSRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for FSRCO IPVERSION */ -#define _FSRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ -#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for FSRCO_IPVERSION */ -#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ - -/** @} End of group EFR32BG22_FSRCO_BitFields */ -/** @} End of group EFR32BG22_FSRCO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_FSRCO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 FSRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_FSRCO_H +#define EFR32BG22_FSRCO_H +#define FSRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_FSRCO FSRCO + * @{ + * @brief EFR32BG22 FSRCO Register Declaration. + *****************************************************************************/ + +/** FSRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + uint32_t RESERVED0[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + uint32_t RESERVED1[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + uint32_t RESERVED2[1023U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ +} FSRCO_TypeDef; +/** @} End of group EFR32BG22_FSRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_FSRCO + * @{ + * @defgroup EFR32BG22_FSRCO_BitFields FSRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for FSRCO IPVERSION */ +#define _FSRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for FSRCO_IPVERSION */ +#define _FSRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for FSRCO_IPVERSION */ +#define FSRCO_IPVERSION_IPVERSION_DEFAULT (_FSRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for FSRCO_IPVERSION */ + +/** @} End of group EFR32BG22_FSRCO_BitFields */ +/** @} End of group EFR32BG22_FSRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_FSRCO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h index a9a4058..f21beea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpcrc.h @@ -1,246 +1,246 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 GPCRC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_GPCRC_H -#define EFR32BG22_GPCRC_H -#define GPCRC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_GPCRC GPCRC - * @{ - * @brief EFR32BG22 GPCRC Register Declaration. - *****************************************************************************/ - -/** GPCRC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t EN; /**< CRC Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t INIT; /**< CRC Init Value */ - __IOM uint32_t POLY; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ - __IM uint32_t DATA; /**< CRC Data Register */ - __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED0[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t EN_SET; /**< CRC Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t INIT_SET; /**< CRC Init Value */ - __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_SET; /**< CRC Data Register */ - __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED1[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t EN_CLR; /**< CRC Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t INIT_CLR; /**< CRC Init Value */ - __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_CLR; /**< CRC Data Register */ - __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ - uint32_t RESERVED2[1012U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t EN_TGL; /**< CRC Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t INIT_TGL; /**< CRC Init Value */ - __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ - __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ - __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ - __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ - __IM uint32_t DATA_TGL; /**< CRC Data Register */ - __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ - __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ -} GPCRC_TypeDef; -/** @} End of group EFR32BG22_GPCRC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_GPCRC - * @{ - * @defgroup EFR32BG22_GPCRC_BitFields GPCRC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for GPCRC IPVERSION */ -#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ -#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ -#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ - -/* Bit fields for GPCRC EN */ -#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ -#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ -#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ -#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ -#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ -#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ -#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ -#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ -#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ -#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ -#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ - -/* Bit fields for GPCRC CTRL */ -#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ -#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ -#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ -#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ -#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ -#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ -#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ -#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ -#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ -#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ -#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ -#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ -#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ -#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ -#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ -#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ -#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ - -/* Bit fields for GPCRC CMD */ -#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ -#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ -#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ -#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ -#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ - -/* Bit fields for GPCRC INIT */ -#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ -#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ -#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ -#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ - -/* Bit fields for GPCRC POLY */ -#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ -#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ -#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ -#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ - -/* Bit fields for GPCRC INPUTDATA */ -#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ -#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ -#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ - -/* Bit fields for GPCRC INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ -#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ -#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ - -/* Bit fields for GPCRC INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ -#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ -#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ - -/* Bit fields for GPCRC DATA */ -#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ -#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ -#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ -#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ - -/* Bit fields for GPCRC DATAREV */ -#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ -#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ -#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ - -/* Bit fields for GPCRC DATABYTEREV */ -#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ -#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ -#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ - -/** @} End of group EFR32BG22_GPCRC_BitFields */ -/** @} End of group EFR32BG22_GPCRC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_GPCRC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 GPCRC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_GPCRC_H +#define EFR32BG22_GPCRC_H +#define GPCRC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_GPCRC GPCRC + * @{ + * @brief EFR32BG22 GPCRC Register Declaration. + *****************************************************************************/ + +/** GPCRC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< CRC Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t INIT; /**< CRC Init Value */ + __IOM uint32_t POLY; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ + __IM uint32_t DATA; /**< CRC Data Register */ + __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED0[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< CRC Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t INIT_SET; /**< CRC Init Value */ + __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_SET; /**< CRC Data Register */ + __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED1[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< CRC Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t INIT_CLR; /**< CRC Init Value */ + __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_CLR; /**< CRC Data Register */ + __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ + uint32_t RESERVED2[1012U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< CRC Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t INIT_TGL; /**< CRC Init Value */ + __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ + __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ + __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ + __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ + __IM uint32_t DATA_TGL; /**< CRC Data Register */ + __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ + __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ +} GPCRC_TypeDef; +/** @} End of group EFR32BG22_GPCRC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_GPCRC + * @{ + * @defgroup EFR32BG22_GPCRC_BitFields GPCRC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for GPCRC IPVERSION */ +#define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ +#define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ +#define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ + +/* Bit fields for GPCRC EN */ +#define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ +#define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ +#define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ +#define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ +#define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ +#define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ +#define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ +#define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ +#define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ +#define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ +#define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ + +/* Bit fields for GPCRC CTRL */ +#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ +#define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ +#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ +#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ +#define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ +#define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ +#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ +#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ +#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ +#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ +#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ +#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ +#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ +#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ +#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ +#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ +#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ + +/* Bit fields for GPCRC CMD */ +#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ +#define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ +#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ +#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ +#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ + +/* Bit fields for GPCRC INIT */ +#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ +#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ +#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ +#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ + +/* Bit fields for GPCRC POLY */ +#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ +#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ +#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ +#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ + +/* Bit fields for GPCRC INPUTDATA */ +#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ +#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ +#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ + +/* Bit fields for GPCRC INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ +#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ +#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ + +/* Bit fields for GPCRC INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ +#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ +#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ + +/* Bit fields for GPCRC DATA */ +#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ +#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ +#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ +#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ + +/* Bit fields for GPCRC DATAREV */ +#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ +#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ +#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ + +/* Bit fields for GPCRC DATABYTEREV */ +#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ +#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ +#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ + +/** @} End of group EFR32BG22_GPCRC_BitFields */ +/** @} End of group EFR32BG22_GPCRC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_GPCRC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h index 2495ae6..4ae8aa7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio.h @@ -1,2088 +1,2088 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 GPIO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_GPIO_H -#define EFR32BG22_GPIO_H -#define GPIO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ - -#include "efr32bg22_gpio_port.h" - -typedef struct { - __IOM uint32_t ROUTEEN; /**< CMU pin enable */ - __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ - __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ - __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ - __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ -} GPIO_CMUROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< DCDC pin enable */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ -} GPIO_DCDCROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< FRC pin enable */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_FRCROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ - __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ - __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_I2CROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ - __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ - __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_LETIMERROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< EUART pin enable */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_EUARTROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ - __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ - __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ - __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ - __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ - __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ - __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ - __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ - __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ - __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ - __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ - __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ - __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ - __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ - __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ - __IOM uint32_t DINROUTE; /**< DIN port/pin select */ - __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_MODEMROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< PDM pin enable */ - __IOM uint32_t CLKROUTE; /**< CLK port/pin select */ - __IOM uint32_t DAT0ROUTE; /**< DAT0 port/pin select */ - __IOM uint32_t DAT1ROUTE; /**< DAT1 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_PDMROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ - __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ - __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ - __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ - __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ - __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ - __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ - __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ - __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ - __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ - __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ - __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ - __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ - __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ - __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ - __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ - __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_PRSROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ - __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ - __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ - __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ - __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ - __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ - __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_TIMERROUTE_TypeDef; - -typedef struct { - __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ - __IOM uint32_t CSROUTE; /**< CS port/pin select */ - __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ - __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ - __IOM uint32_t RXROUTE; /**< RX port/pin select */ - __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ - __IOM uint32_t TXROUTE; /**< TX port/pin select */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ -} GPIO_USARTROUTE_TypeDef; - -typedef struct { - GPIO_PORT_TypeDef P[4U]; /**< */ - uint32_t RESERVED0[144U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ - uint32_t RESERVED3[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ - GPIO_DCDCROUTE_TypeDef DCDCROUTE; /**< dcdc DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE[1U]; /**< letimer DBUS config registers */ - GPIO_EUARTROUTE_TypeDef EUARTROUTE[1U]; /**< leuart DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ - GPIO_PDMROUTE_TypeDef PDMROUTE; /**< pdm DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE[2U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED8[617U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_SET[4U]; /**< */ - uint32_t RESERVED9[144U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ - uint32_t RESERVED12[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ - GPIO_DCDCROUTE_TypeDef DCDCROUTE_SET; /**< dcdc DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET[1U]; /**< letimer DBUS config registers */ - GPIO_EUARTROUTE_TypeDef EUARTROUTE_SET[1U]; /**< leuart DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ - GPIO_PDMROUTE_TypeDef PDMROUTE_SET; /**< pdm DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_SET[2U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED17[617U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_CLR[4U]; /**< */ - uint32_t RESERVED18[144U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED19[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ - uint32_t RESERVED20[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ - uint32_t RESERVED21[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED22[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ - uint32_t RESERVED24[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ - GPIO_DCDCROUTE_TypeDef DCDCROUTE_CLR; /**< dcdc DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR[1U]; /**< letimer DBUS config registers */ - GPIO_EUARTROUTE_TypeDef EUARTROUTE_CLR[1U]; /**< leuart DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ - GPIO_PDMROUTE_TypeDef PDMROUTE_CLR; /**< pdm DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[2U]; /**< usart0 DBUS config registers */ - uint32_t RESERVED26[617U]; /**< Reserved for future use */ - GPIO_PORT_TypeDef P_TGL[4U]; /**< */ - uint32_t RESERVED27[144U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - uint32_t RESERVED28[3U]; /**< Reserved for future use */ - __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ - uint32_t RESERVED29[3U]; /**< Reserved for future use */ - __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ - __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ - __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ - uint32_t RESERVED30[53U]; /**< Reserved for future use */ - __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ - __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ - __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ - __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ - __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ - __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ - __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ - __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ - GPIO_DCDCROUTE_TypeDef DCDCROUTE_TGL; /**< dcdc DBUS config registers */ - GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ - GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ - GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL[1U]; /**< letimer DBUS config registers */ - GPIO_EUARTROUTE_TypeDef EUARTROUTE_TGL[1U]; /**< leuart DBUS config registers */ - GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ - GPIO_PDMROUTE_TypeDef PDMROUTE_TGL; /**< pdm DBUS config registers */ - GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ - GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ - GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[2U]; /**< usart0 DBUS config registers */ -} GPIO_TypeDef; - -#define GPIO_PORTA 0x00000000UL /**< PORTA index */ -#define GPIO_PORTB 0x00000001UL /**< PORTB index */ -#define GPIO_PORTC 0x00000002UL /**< PORTC index */ -#define GPIO_PORTD 0x00000003UL /**< PORTD index */ - -/* Bit fields for GPIO LOCK */ -#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ -#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ -#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ -#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ -#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ - -/* Bit fields for GPIO GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ -#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ -#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ -#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ - -/* Bit fields for GPIO ABUSALLOC */ -#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ -#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ -#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ -#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ -#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ -#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ -#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ - -/* Bit fields for GPIO BBUSALLOC */ -#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ -#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ -#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ -#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ -#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ -#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ -#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ - -/* Bit fields for GPIO CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ -#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ -#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ -#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ -#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ -#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ -#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ - -/* Bit fields for GPIO EXTIPSELL */ -#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ -#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ -#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ - -/* Bit fields for GPIO EXTIPSELH */ -#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ -#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ -#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ - -/* Bit fields for GPIO EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 << 0) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 << 0) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 << 0) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 << 0) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 << 4) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 << 4) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 << 4) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 << 4) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 << 8) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 << 8) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 << 8) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 << 8) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 << 12) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 << 12) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 << 12) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 << 12) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 << 16) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 << 16) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 << 16) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 << 16) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 << 20) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 << 20) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 << 20) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 << 20) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 << 24) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 << 24) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 << 24) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 << 24) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ -#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 << 28) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 << 28) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 << 28) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ -#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 << 28) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ - -/* Bit fields for GPIO EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 << 0) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 << 0) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 << 0) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 << 0) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 << 4) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 << 4) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 << 4) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 << 4) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 << 8) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 << 8) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 << 8) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 << 8) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ -#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 << 12) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 << 12) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 << 12) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ -#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 << 12) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ - -/* Bit fields for GPIO EXTIRISE */ -#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ -#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ -#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ - -/* Bit fields for GPIO EXTIFALL */ -#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ -#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ -#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ - -/* Bit fields for GPIO IF */ -#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ -#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ -#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ -#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ -#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ -#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ -#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ -#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ -#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ -#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ -#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ -#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ -#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ -#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ -#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ -#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ -#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ -#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ -#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ - -/* Bit fields for GPIO IEN */ -#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ -#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ -#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ -#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ -#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ -#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ -#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ -#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ -#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ -#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ -#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ -#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ -#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ -#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ -#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ -#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ -#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ -#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ -#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ -#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ -#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ -#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ -#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ -#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ -#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ -#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ -#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ -#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ -#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ - -/* Bit fields for GPIO EM4WUEN */ -#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ -#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ -#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ - -/* Bit fields for GPIO EM4WUPOL */ -#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ -#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ -#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ - -/* Bit fields for GPIO DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ -#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ -#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ -#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ -#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ -#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ -#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ -#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ - -/* Bit fields for GPIO TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ -#define _GPIO_TRACEROUTEPEN_MASK 0x00000007UL /**< Mask for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ -#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ -#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ -#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ -#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ - -/* Bit fields for GPIO_CMU ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ -#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ -#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ -#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ - -/* Bit fields for GPIO_CMU CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ -#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ -#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ -#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ - -/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ -#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ - -/* Bit fields for GPIO_DCDC ROUTEEN */ -#define _GPIO_DCDC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_DCDC_ROUTEEN */ -#define _GPIO_DCDC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_DCDC_ROUTEEN */ -#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN (0x1UL << 0) /**< DCDCCOREHIDDEN pin enable control bit */ -#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_SHIFT 0 /**< Shift value for GPIO_DCDCCOREHIDDENPEN */ -#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_MASK 0x1UL /**< Bit mask for GPIO_DCDCCOREHIDDENPEN */ -#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_DCDC_ROUTEEN */ -#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT (_GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DCDC_ROUTEEN */ - -/* Bit fields for GPIO_FRC ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ -#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ -#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ -#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ - -/* Bit fields for GPIO_FRC DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ -#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ - -/* Bit fields for GPIO_FRC DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ -#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ -#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ - -/* Bit fields for GPIO_FRC DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ -#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ - -/* Bit fields for GPIO_I2C ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ -#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ -#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ -#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ -#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ - -/* Bit fields for GPIO_I2C SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ -#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ - -/* Bit fields for GPIO_I2C SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ -#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ - -/* Bit fields for GPIO_LETIMER ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ -#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ -#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ -#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ - -/* Bit fields for GPIO_LETIMER OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ -#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ - -/* Bit fields for GPIO_LETIMER OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ -#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ - -/* Bit fields for GPIO_EUART ROUTEEN */ -#define _GPIO_EUART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_ROUTEEN */ -#define _GPIO_EUART_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_EUART_ROUTEEN */ -#define GPIO_EUART_ROUTEEN_RTSPEN (0x1UL << 0) /**< RTS pin enable control bit */ -#define _GPIO_EUART_ROUTEEN_RTSPEN_SHIFT 0 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_EUART_ROUTEEN_RTSPEN_MASK 0x1UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_ROUTEEN */ -#define GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_ROUTEEN */ -#define GPIO_EUART_ROUTEEN_TXPEN (0x1UL << 1) /**< TX pin enable control bit */ -#define _GPIO_EUART_ROUTEEN_TXPEN_SHIFT 1 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_EUART_ROUTEEN_TXPEN_MASK 0x2UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_EUART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_ROUTEEN */ -#define GPIO_EUART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUART_ROUTEEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUART_ROUTEEN */ - -/* Bit fields for GPIO_EUART CTSROUTE */ -#define _GPIO_EUART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_CTSROUTE */ -#define _GPIO_EUART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_CTSROUTE */ -#define _GPIO_EUART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_CTSROUTE */ -#define GPIO_EUART_CTSROUTE_PORT_DEFAULT (_GPIO_EUART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_CTSROUTE*/ -#define _GPIO_EUART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_CTSROUTE */ -#define GPIO_EUART_CTSROUTE_PIN_DEFAULT (_GPIO_EUART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_CTSROUTE*/ - -/* Bit fields for GPIO_EUART RTSROUTE */ -#define _GPIO_EUART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_RTSROUTE */ -#define _GPIO_EUART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_RTSROUTE */ -#define _GPIO_EUART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RTSROUTE */ -#define GPIO_EUART_RTSROUTE_PORT_DEFAULT (_GPIO_EUART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_RTSROUTE*/ -#define _GPIO_EUART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RTSROUTE */ -#define GPIO_EUART_RTSROUTE_PIN_DEFAULT (_GPIO_EUART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_RTSROUTE*/ - -/* Bit fields for GPIO_EUART RXROUTE */ -#define _GPIO_EUART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_RXROUTE */ -#define _GPIO_EUART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_RXROUTE */ -#define _GPIO_EUART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RXROUTE */ -#define GPIO_EUART_RXROUTE_PORT_DEFAULT (_GPIO_EUART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_RXROUTE */ -#define _GPIO_EUART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RXROUTE */ -#define GPIO_EUART_RXROUTE_PIN_DEFAULT (_GPIO_EUART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_RXROUTE */ - -/* Bit fields for GPIO_EUART TXROUTE */ -#define _GPIO_EUART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_TXROUTE */ -#define _GPIO_EUART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_TXROUTE */ -#define _GPIO_EUART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_EUART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_EUART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_TXROUTE */ -#define GPIO_EUART_TXROUTE_PORT_DEFAULT (_GPIO_EUART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_TXROUTE */ -#define _GPIO_EUART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_EUART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_EUART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_TXROUTE */ -#define GPIO_EUART_TXROUTE_PIN_DEFAULT (_GPIO_EUART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_TXROUTE */ - -/* Bit fields for GPIO_MODEM ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ -#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ -#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ -#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ -#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ -#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ -#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ - -/* Bit fields for GPIO_MODEM ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ -#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ -#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ - -/* Bit fields for GPIO_MODEM ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ -#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ -#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ -#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ -#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ -#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ -#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ -#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ -#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ -#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ - -/* Bit fields for GPIO_MODEM ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ -#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ - -/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ -#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ - -/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ -#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ - -/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ -#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ - -/* Bit fields for GPIO_MODEM DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ -#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ -#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ -#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ - -/* Bit fields for GPIO_MODEM DINROUTE */ -#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ -#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ -#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ -#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ - -/* Bit fields for GPIO_MODEM DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ -#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ -#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ -#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ - -/* Bit fields for GPIO_PDM ROUTEEN */ -#define _GPIO_PDM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_ROUTEEN */ -#define _GPIO_PDM_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_PDM_ROUTEEN */ -#define GPIO_PDM_ROUTEEN_CLKPEN (0x1UL << 0) /**< CLK pin enable control bit */ -#define _GPIO_PDM_ROUTEEN_CLKPEN_SHIFT 0 /**< Shift value for GPIO_CLKPEN */ -#define _GPIO_PDM_ROUTEEN_CLKPEN_MASK 0x1UL /**< Bit mask for GPIO_CLKPEN */ -#define _GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_ROUTEEN */ -#define GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT (_GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_ROUTEEN */ - -/* Bit fields for GPIO_PDM CLKROUTE */ -#define _GPIO_PDM_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_CLKROUTE */ -#define _GPIO_PDM_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_CLKROUTE */ -#define _GPIO_PDM_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PDM_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PDM_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ -#define GPIO_PDM_CLKROUTE_PORT_DEFAULT (_GPIO_PDM_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ -#define _GPIO_PDM_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PDM_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PDM_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ -#define GPIO_PDM_CLKROUTE_PIN_DEFAULT (_GPIO_PDM_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ - -/* Bit fields for GPIO_PDM DAT0ROUTE */ -#define _GPIO_PDM_DAT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT0ROUTE */ -#define _GPIO_PDM_DAT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT0ROUTE */ -#define _GPIO_PDM_DAT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PDM_DAT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PDM_DAT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ -#define GPIO_PDM_DAT0ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ -#define _GPIO_PDM_DAT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PDM_DAT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PDM_DAT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ -#define GPIO_PDM_DAT0ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ - -/* Bit fields for GPIO_PDM DAT1ROUTE */ -#define _GPIO_PDM_DAT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT1ROUTE */ -#define _GPIO_PDM_DAT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT1ROUTE */ -#define _GPIO_PDM_DAT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PDM_DAT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PDM_DAT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ -#define GPIO_PDM_DAT1ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ -#define _GPIO_PDM_DAT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PDM_DAT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PDM_DAT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ -#define GPIO_PDM_DAT1ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ - -/* Bit fields for GPIO_PRS ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ -#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ -#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ -#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ -#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ - -/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ -#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ -#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ -#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ -#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ -#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ -#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ -#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ -#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ -#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ -#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ -#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ - -/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ -#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ -#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ -#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ -#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ - -/* Bit fields for GPIO_PRS SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ -#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ - -/* Bit fields for GPIO_TIMER ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ -#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ -#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ -#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ - -/* Bit fields for GPIO_TIMER CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ -#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ -#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ -#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ - -/* Bit fields for GPIO_TIMER CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ -#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ -#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ -#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ - -/* Bit fields for GPIO_TIMER CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ -#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ -#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ -#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ -#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ -#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ - -/* Bit fields for GPIO_TIMER CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ -#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ - -/* Bit fields for GPIO_USART ROUTEEN */ -#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ -#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ -#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ -#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ -#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ -#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ -#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ -#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ -#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ -#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ - -/* Bit fields for GPIO_USART CSROUTE */ -#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ -#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ -#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ - -/* Bit fields for GPIO_USART CTSROUTE */ -#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ -#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ -#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ -#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ - -/* Bit fields for GPIO_USART RTSROUTE */ -#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ -#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ -#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ -#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ - -/* Bit fields for GPIO_USART RXROUTE */ -#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ -#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ -#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ - -/* Bit fields for GPIO_USART CLKROUTE */ -#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ -#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ -#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ -#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ - -/* Bit fields for GPIO_USART TXROUTE */ -#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ -#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ -#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ -#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ -/** @} End of group Parts */ - -#endif // EFR32BG22_GPIO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 GPIO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_GPIO_H +#define EFR32BG22_GPIO_H +#define GPIO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ + +#include "efr32bg22_gpio_port.h" + +typedef struct { + __IOM uint32_t ROUTEEN; /**< CMU pin enable */ + __IOM uint32_t CLKIN0ROUTE; /**< CLKIN0 port/pin select */ + __IOM uint32_t CLKOUT0ROUTE; /**< CLKOUT0 port/pin select */ + __IOM uint32_t CLKOUT1ROUTE; /**< CLKOUT1 port/pin select */ + __IOM uint32_t CLKOUT2ROUTE; /**< CLKOUT2 port/pin select */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ +} GPIO_CMUROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< DCDC pin enable */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ +} GPIO_DCDCROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< FRC pin enable */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DFRAMEROUTE; /**< DFRAME port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_FRCROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< I2C0 pin enable */ + __IOM uint32_t SCLROUTE; /**< SCL port/pin select */ + __IOM uint32_t SDAROUTE; /**< SDA port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_I2CROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< LETIMER pin enable */ + __IOM uint32_t OUT0ROUTE; /**< OUT0 port/pin select */ + __IOM uint32_t OUT1ROUTE; /**< OUT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_LETIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< EUART pin enable */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_EUARTROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< MODEM pin enable */ + __IOM uint32_t ANT0ROUTE; /**< ANT0 port/pin select */ + __IOM uint32_t ANT1ROUTE; /**< ANT1 port/pin select */ + __IOM uint32_t ANTROLLOVERROUTE; /**< ANTROLLOVER port/pin select */ + __IOM uint32_t ANTRR0ROUTE; /**< ANTRR0 port/pin select */ + __IOM uint32_t ANTRR1ROUTE; /**< ANTRR1 port/pin select */ + __IOM uint32_t ANTRR2ROUTE; /**< ANTRR2 port/pin select */ + __IOM uint32_t ANTRR3ROUTE; /**< ANTRR3 port/pin select */ + __IOM uint32_t ANTRR4ROUTE; /**< ANTRR4 port/pin select */ + __IOM uint32_t ANTRR5ROUTE; /**< ANTRR5 port/pin select */ + __IOM uint32_t ANTSWENROUTE; /**< ANTSWEN port/pin select */ + __IOM uint32_t ANTSWUSROUTE; /**< ANTSWUS port/pin select */ + __IOM uint32_t ANTTRIGROUTE; /**< ANTTRIG port/pin select */ + __IOM uint32_t ANTTRIGSTOPROUTE; /**< ANTTRIGSTOP port/pin select */ + __IOM uint32_t DCLKROUTE; /**< DCLK port/pin select */ + __IOM uint32_t DINROUTE; /**< DIN port/pin select */ + __IOM uint32_t DOUTROUTE; /**< DOUT port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_MODEMROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< PDM pin enable */ + __IOM uint32_t CLKROUTE; /**< CLK port/pin select */ + __IOM uint32_t DAT0ROUTE; /**< DAT0 port/pin select */ + __IOM uint32_t DAT1ROUTE; /**< DAT1 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PDMROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< PRS0 pin enable */ + __IOM uint32_t ASYNCH0ROUTE; /**< ASYNCH0 port/pin select */ + __IOM uint32_t ASYNCH1ROUTE; /**< ASYNCH1 port/pin select */ + __IOM uint32_t ASYNCH2ROUTE; /**< ASYNCH2 port/pin select */ + __IOM uint32_t ASYNCH3ROUTE; /**< ASYNCH3 port/pin select */ + __IOM uint32_t ASYNCH4ROUTE; /**< ASYNCH4 port/pin select */ + __IOM uint32_t ASYNCH5ROUTE; /**< ASYNCH5 port/pin select */ + __IOM uint32_t ASYNCH6ROUTE; /**< ASYNCH6 port/pin select */ + __IOM uint32_t ASYNCH7ROUTE; /**< ASYNCH7 port/pin select */ + __IOM uint32_t ASYNCH8ROUTE; /**< ASYNCH8 port/pin select */ + __IOM uint32_t ASYNCH9ROUTE; /**< ASYNCH9 port/pin select */ + __IOM uint32_t ASYNCH10ROUTE; /**< ASYNCH10 port/pin select */ + __IOM uint32_t ASYNCH11ROUTE; /**< ASYNCH11 port/pin select */ + __IOM uint32_t SYNCH0ROUTE; /**< SYNCH0 port/pin select */ + __IOM uint32_t SYNCH1ROUTE; /**< SYNCH1 port/pin select */ + __IOM uint32_t SYNCH2ROUTE; /**< SYNCH2 port/pin select */ + __IOM uint32_t SYNCH3ROUTE; /**< SYNCH3 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_PRSROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< TIMER0 pin enable */ + __IOM uint32_t CC0ROUTE; /**< CC0 port/pin select */ + __IOM uint32_t CC1ROUTE; /**< CC1 port/pin select */ + __IOM uint32_t CC2ROUTE; /**< CC2 port/pin select */ + __IOM uint32_t CDTI0ROUTE; /**< CDTI0 port/pin select */ + __IOM uint32_t CDTI1ROUTE; /**< CDTI1 port/pin select */ + __IOM uint32_t CDTI2ROUTE; /**< CDTI2 port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_TIMERROUTE_TypeDef; + +typedef struct { + __IOM uint32_t ROUTEEN; /**< USART0 pin enable */ + __IOM uint32_t CSROUTE; /**< CS port/pin select */ + __IOM uint32_t CTSROUTE; /**< CTS port/pin select */ + __IOM uint32_t RTSROUTE; /**< RTS port/pin select */ + __IOM uint32_t RXROUTE; /**< RX port/pin select */ + __IOM uint32_t CLKROUTE; /**< SCLK port/pin select */ + __IOM uint32_t TXROUTE; /**< TX port/pin select */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ +} GPIO_USARTROUTE_TypeDef; + +typedef struct { + GPIO_PORT_TypeDef P[4U]; /**< */ + uint32_t RESERVED0[144U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC; /**< CD Bus allocation */ + uint32_t RESERVED3[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL; /**< EM4 wakeup polarity */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN; /**< Trace Route Pin Enable */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + GPIO_CMUROUTE_TypeDef CMUROUTE; /**< cmu DBUS config registers */ + GPIO_DCDCROUTE_TypeDef DCDCROUTE; /**< dcdc DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE[1U]; /**< letimer DBUS config registers */ + GPIO_EUARTROUTE_TypeDef EUARTROUTE[1U]; /**< leuart DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED8[617U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_SET[4U]; /**< */ + uint32_t RESERVED9[144U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_SET; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_SET; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_SET; /**< CD Bus allocation */ + uint32_t RESERVED12[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_SET; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_SET; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_SET; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_SET; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_SET; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_SET; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_SET; /**< EM4 wakeup polarity */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_SET; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_SET; /**< Trace Route Pin Enable */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + GPIO_CMUROUTE_TypeDef CMUROUTE_SET; /**< cmu DBUS config registers */ + GPIO_DCDCROUTE_TypeDef DCDCROUTE_SET; /**< dcdc DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_SET; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_SET[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_SET[1U]; /**< letimer DBUS config registers */ + GPIO_EUARTROUTE_TypeDef EUARTROUTE_SET[1U]; /**< leuart DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_SET; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_SET; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_SET[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_SET[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_SET[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED17[617U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_CLR[4U]; /**< */ + uint32_t RESERVED18[144U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED19[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED20[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_CLR; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_CLR; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_CLR; /**< CD Bus allocation */ + uint32_t RESERVED21[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_CLR; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_CLR; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_CLR; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_CLR; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_CLR; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_CLR; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED22[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_CLR; /**< EM4 wakeup polarity */ + uint32_t RESERVED24[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_CLR; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_CLR; /**< Trace Route Pin Enable */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + GPIO_CMUROUTE_TypeDef CMUROUTE_CLR; /**< cmu DBUS config registers */ + GPIO_DCDCROUTE_TypeDef DCDCROUTE_CLR; /**< dcdc DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_CLR; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_CLR[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_CLR[1U]; /**< letimer DBUS config registers */ + GPIO_EUARTROUTE_TypeDef EUARTROUTE_CLR[1U]; /**< leuart DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_CLR; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_CLR; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_CLR[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_CLR[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_CLR[2U]; /**< usart0 DBUS config registers */ + uint32_t RESERVED26[617U]; /**< Reserved for future use */ + GPIO_PORT_TypeDef P_TGL[4U]; /**< */ + uint32_t RESERVED27[144U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + uint32_t RESERVED28[3U]; /**< Reserved for future use */ + __IM uint32_t GPIOLOCKSTATUS_TGL; /**< Lock Status */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IOM uint32_t ABUSALLOC_TGL; /**< A Bus allocation */ + __IOM uint32_t BBUSALLOC_TGL; /**< B Bus allocation */ + __IOM uint32_t CDBUSALLOC_TGL; /**< CD Bus allocation */ + uint32_t RESERVED30[53U]; /**< Reserved for future use */ + __IOM uint32_t EXTIPSELL_TGL; /**< External Interrupt Port Select Low */ + __IOM uint32_t EXTIPSELH_TGL; /**< External interrupt Port Select High */ + __IOM uint32_t EXTIPINSELL_TGL; /**< External Interrupt Pin Select Low */ + __IOM uint32_t EXTIPINSELH_TGL; /**< External Interrupt Pin Select High */ + __IOM uint32_t EXTIRISE_TGL; /**< External Interrupt Rising Edge Trigger */ + __IOM uint32_t EXTIFALL_TGL; /**< External Interrupt Falling Edge Trigger */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup enable */ + __IOM uint32_t EM4WUPOL_TGL; /**< EM4 wakeup polarity */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t DBGROUTEPEN_TGL; /**< Debugger Route Pin enable */ + __IOM uint32_t TRACEROUTEPEN_TGL; /**< Trace Route Pin Enable */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + GPIO_CMUROUTE_TypeDef CMUROUTE_TGL; /**< cmu DBUS config registers */ + GPIO_DCDCROUTE_TypeDef DCDCROUTE_TGL; /**< dcdc DBUS config registers */ + GPIO_FRCROUTE_TypeDef FRCROUTE_TGL; /**< frc DBUS config registers */ + GPIO_I2CROUTE_TypeDef I2CROUTE_TGL[2U]; /**< i2c0 DBUS config registers */ + GPIO_LETIMERROUTE_TypeDef LETIMERROUTE_TGL[1U]; /**< letimer DBUS config registers */ + GPIO_EUARTROUTE_TypeDef EUARTROUTE_TGL[1U]; /**< leuart DBUS config registers */ + GPIO_MODEMROUTE_TypeDef MODEMROUTE_TGL; /**< modem DBUS config registers */ + GPIO_PDMROUTE_TypeDef PDMROUTE_TGL; /**< pdm DBUS config registers */ + GPIO_PRSROUTE_TypeDef PRSROUTE_TGL[1U]; /**< prs0 DBUS config registers */ + GPIO_TIMERROUTE_TypeDef TIMERROUTE_TGL[5U]; /**< timer0 DBUS config registers */ + GPIO_USARTROUTE_TypeDef USARTROUTE_TGL[2U]; /**< usart0 DBUS config registers */ +} GPIO_TypeDef; + +#define GPIO_PORTA 0x00000000UL /**< PORTA index */ +#define GPIO_PORTB 0x00000001UL /**< PORTB index */ +#define GPIO_PORTC 0x00000002UL /**< PORTC index */ +#define GPIO_PORTD 0x00000003UL /**< PORTD index */ + +/* Bit fields for GPIO LOCK */ +#define _GPIO_LOCK_RESETVALUE 0x0000A534UL /**< Default value for GPIO_LOCK */ +#define _GPIO_LOCK_MASK 0x0000FFFFUL /**< Mask for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for GPIO_LOCKKEY */ +#define _GPIO_LOCK_LOCKKEY_DEFAULT 0x0000A534UL /**< Mode DEFAULT for GPIO_LOCK */ +#define _GPIO_LOCK_LOCKKEY_UNLOCK 0x0000A534UL /**< Mode UNLOCK for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_DEFAULT (_GPIO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LOCK */ +#define GPIO_LOCK_LOCKKEY_UNLOCK (_GPIO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for GPIO_LOCK */ + +/* Bit fields for GPIO GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_MASK 0x00000001UL /**< Mask for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK (0x1UL << 0) /**< GPIO LOCK status */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for GPIO_LOCK */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for GPIO_GPIOLOCKSTATUS */ +#define _GPIO_GPIOLOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for GPIO_GPIOLOCKSTATUS */ +#define GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT (_GPIO_GPIOLOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for GPIO_GPIOLOCKSTATUS*/ +#define GPIO_GPIOLOCKSTATUS_LOCK_LOCKED (_GPIO_GPIOLOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for GPIO_GPIOLOCKSTATUS */ + +/* Bit fields for GPIO ABUSALLOC */ +#define _GPIO_ABUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_SHIFT 0 /**< Shift value for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_MASK 0xFUL /**< Bit mask for GPIO_AEVEN0 */ +#define _GPIO_ABUSALLOC_AEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_DEFAULT (_GPIO_ABUSALLOC_AEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_TRISTATE (_GPIO_ABUSALLOC_AEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN0_ADC0 (_GPIO_ABUSALLOC_AEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_SHIFT 8 /**< Shift value for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_AEVEN1 */ +#define _GPIO_ABUSALLOC_AEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_DEFAULT (_GPIO_ABUSALLOC_AEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_TRISTATE (_GPIO_ABUSALLOC_AEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AEVEN1_ADC0 (_GPIO_ABUSALLOC_AEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_SHIFT 16 /**< Shift value for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_MASK 0xF0000UL /**< Bit mask for GPIO_AODD0 */ +#define _GPIO_ABUSALLOC_AODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_DEFAULT (_GPIO_ABUSALLOC_AODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_TRISTATE (_GPIO_ABUSALLOC_AODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD0_ADC0 (_GPIO_ABUSALLOC_AODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_SHIFT 24 /**< Shift value for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_MASK 0xF000000UL /**< Bit mask for GPIO_AODD1 */ +#define _GPIO_ABUSALLOC_AODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_ABUSALLOC */ +#define _GPIO_ABUSALLOC_AODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_DEFAULT (_GPIO_ABUSALLOC_AODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_TRISTATE (_GPIO_ABUSALLOC_AODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_ABUSALLOC */ +#define GPIO_ABUSALLOC_AODD1_ADC0 (_GPIO_ABUSALLOC_AODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_ABUSALLOC */ + +/* Bit fields for GPIO BBUSALLOC */ +#define _GPIO_BBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_SHIFT 0 /**< Shift value for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_MASK 0xFUL /**< Bit mask for GPIO_BEVEN0 */ +#define _GPIO_BBUSALLOC_BEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_DEFAULT (_GPIO_BBUSALLOC_BEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_TRISTATE (_GPIO_BBUSALLOC_BEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN0_ADC0 (_GPIO_BBUSALLOC_BEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_SHIFT 8 /**< Shift value for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_BEVEN1 */ +#define _GPIO_BBUSALLOC_BEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_DEFAULT (_GPIO_BBUSALLOC_BEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_TRISTATE (_GPIO_BBUSALLOC_BEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BEVEN1_ADC0 (_GPIO_BBUSALLOC_BEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_SHIFT 16 /**< Shift value for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_MASK 0xF0000UL /**< Bit mask for GPIO_BODD0 */ +#define _GPIO_BBUSALLOC_BODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_DEFAULT (_GPIO_BBUSALLOC_BODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_TRISTATE (_GPIO_BBUSALLOC_BODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD0_ADC0 (_GPIO_BBUSALLOC_BODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_SHIFT 24 /**< Shift value for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_MASK 0xF000000UL /**< Bit mask for GPIO_BODD1 */ +#define _GPIO_BBUSALLOC_BODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_BBUSALLOC */ +#define _GPIO_BBUSALLOC_BODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_DEFAULT (_GPIO_BBUSALLOC_BODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_TRISTATE (_GPIO_BBUSALLOC_BODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_BBUSALLOC */ +#define GPIO_BBUSALLOC_BODD1_ADC0 (_GPIO_BBUSALLOC_BODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_BBUSALLOC */ + +/* Bit fields for GPIO CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_RESETVALUE 0x00000000UL /**< Default value for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_MASK 0x0F0F0F0FUL /**< Mask for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_SHIFT 0 /**< Shift value for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_MASK 0xFUL /**< Bit mask for GPIO_CDEVEN0 */ +#define _GPIO_CDBUSALLOC_CDEVEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN0_TRISTATE << 0) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN0_ADC0 (_GPIO_CDBUSALLOC_CDEVEN0_ADC0 << 0) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_SHIFT 8 /**< Shift value for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_MASK 0xF00UL /**< Bit mask for GPIO_CDEVEN1 */ +#define _GPIO_CDBUSALLOC_CDEVEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDEVEN1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_DEFAULT (_GPIO_CDBUSALLOC_CDEVEN1_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_TRISTATE (_GPIO_CDBUSALLOC_CDEVEN1_TRISTATE << 8) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDEVEN1_ADC0 (_GPIO_CDBUSALLOC_CDEVEN1_ADC0 << 8) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_SHIFT 16 /**< Shift value for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_MASK 0xF0000UL /**< Bit mask for GPIO_CDODD0 */ +#define _GPIO_CDBUSALLOC_CDODD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD0_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_DEFAULT (_GPIO_CDBUSALLOC_CDODD0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_TRISTATE (_GPIO_CDBUSALLOC_CDODD0_TRISTATE << 16) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD0_ADC0 (_GPIO_CDBUSALLOC_CDODD0_ADC0 << 16) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_SHIFT 24 /**< Shift value for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_MASK 0xF000000UL /**< Bit mask for GPIO_CDODD1 */ +#define _GPIO_CDBUSALLOC_CDODD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_TRISTATE 0x00000000UL /**< Mode TRISTATE for GPIO_CDBUSALLOC */ +#define _GPIO_CDBUSALLOC_CDODD1_ADC0 0x00000001UL /**< Mode ADC0 for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_DEFAULT (_GPIO_CDBUSALLOC_CDODD1_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_TRISTATE (_GPIO_CDBUSALLOC_CDODD1_TRISTATE << 24) /**< Shifted mode TRISTATE for GPIO_CDBUSALLOC */ +#define GPIO_CDBUSALLOC_CDODD1_ADC0 (_GPIO_CDBUSALLOC_CDODD1_ADC0 << 24) /**< Shifted mode ADC0 for GPIO_CDBUSALLOC */ + +/* Bit fields for GPIO EXTIPSELL */ +#define _GPIO_EXTIPSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTA (_GPIO_EXTIPSELL_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTB (_GPIO_EXTIPSELL_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTC (_GPIO_EXTIPSELL_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL0_PORTD (_GPIO_EXTIPSELL_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTA (_GPIO_EXTIPSELL_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTB (_GPIO_EXTIPSELL_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTC (_GPIO_EXTIPSELL_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL1_PORTD (_GPIO_EXTIPSELL_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTA (_GPIO_EXTIPSELL_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTB (_GPIO_EXTIPSELL_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTC (_GPIO_EXTIPSELL_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL2_PORTD (_GPIO_EXTIPSELL_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTA (_GPIO_EXTIPSELL_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTB (_GPIO_EXTIPSELL_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTC (_GPIO_EXTIPSELL_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL3_PORTD (_GPIO_EXTIPSELL_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPSEL4 */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL4_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTA (_GPIO_EXTIPSELL_EXTIPSEL4_PORTA << 16) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTB (_GPIO_EXTIPSELL_EXTIPSEL4_PORTB << 16) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTC (_GPIO_EXTIPSELL_EXTIPSEL4_PORTC << 16) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL4_PORTD (_GPIO_EXTIPSELL_EXTIPSEL4_PORTD << 16) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPSEL5 */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL5_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTA (_GPIO_EXTIPSELL_EXTIPSEL5_PORTA << 20) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTB (_GPIO_EXTIPSELL_EXTIPSEL5_PORTB << 20) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTC (_GPIO_EXTIPSELL_EXTIPSEL5_PORTC << 20) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL5_PORTD (_GPIO_EXTIPSELL_EXTIPSEL5_PORTD << 20) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPSEL6 */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL6_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTA (_GPIO_EXTIPSELL_EXTIPSEL6_PORTA << 24) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTB (_GPIO_EXTIPSELL_EXTIPSEL6_PORTB << 24) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTC (_GPIO_EXTIPSELL_EXTIPSEL6_PORTC << 24) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL6_PORTD (_GPIO_EXTIPSELL_EXTIPSEL6_PORTD << 24) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPSEL7 */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELL */ +#define _GPIO_EXTIPSELL_EXTIPSEL7_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT (_GPIO_EXTIPSELL_EXTIPSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTA (_GPIO_EXTIPSELL_EXTIPSEL7_PORTA << 28) /**< Shifted mode PORTA for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTB (_GPIO_EXTIPSELL_EXTIPSEL7_PORTB << 28) /**< Shifted mode PORTB for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTC (_GPIO_EXTIPSELL_EXTIPSEL7_PORTC << 28) /**< Shifted mode PORTC for GPIO_EXTIPSELL */ +#define GPIO_EXTIPSELL_EXTIPSEL7_PORTD (_GPIO_EXTIPSELL_EXTIPSEL7_PORTD << 28) /**< Shifted mode PORTD for GPIO_EXTIPSELL */ + +/* Bit fields for GPIO EXTIPSELH */ +#define _GPIO_EXTIPSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPSEL0 */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL0_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTA (_GPIO_EXTIPSELH_EXTIPSEL0_PORTA << 0) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTB (_GPIO_EXTIPSELH_EXTIPSEL0_PORTB << 0) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTC (_GPIO_EXTIPSELH_EXTIPSEL0_PORTC << 0) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL0_PORTD (_GPIO_EXTIPSELH_EXTIPSEL0_PORTD << 0) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPSEL1 */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL1_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTA (_GPIO_EXTIPSELH_EXTIPSEL1_PORTA << 4) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTB (_GPIO_EXTIPSELH_EXTIPSEL1_PORTB << 4) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTC (_GPIO_EXTIPSELH_EXTIPSEL1_PORTC << 4) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL1_PORTD (_GPIO_EXTIPSELH_EXTIPSEL1_PORTD << 4) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPSEL2 */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL2_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTA (_GPIO_EXTIPSELH_EXTIPSEL2_PORTA << 8) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTB (_GPIO_EXTIPSELH_EXTIPSEL2_PORTB << 8) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTC (_GPIO_EXTIPSELH_EXTIPSEL2_PORTC << 8) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL2_PORTD (_GPIO_EXTIPSELH_EXTIPSEL2_PORTD << 8) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPSEL3 */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTA 0x00000000UL /**< Mode PORTA for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTB 0x00000001UL /**< Mode PORTB for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTC 0x00000002UL /**< Mode PORTC for GPIO_EXTIPSELH */ +#define _GPIO_EXTIPSELH_EXTIPSEL3_PORTD 0x00000003UL /**< Mode PORTD for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT (_GPIO_EXTIPSELH_EXTIPSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTA (_GPIO_EXTIPSELH_EXTIPSEL3_PORTA << 12) /**< Shifted mode PORTA for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTB (_GPIO_EXTIPSELH_EXTIPSEL3_PORTB << 12) /**< Shifted mode PORTB for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTC (_GPIO_EXTIPSELH_EXTIPSEL3_PORTC << 12) /**< Shifted mode PORTC for GPIO_EXTIPSELH */ +#define GPIO_EXTIPSELH_EXTIPSEL3_PORTD (_GPIO_EXTIPSELH_EXTIPSEL3_PORTD << 12) /**< Shifted mode PORTD for GPIO_EXTIPSELH */ + +/* Bit fields for GPIO EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_MASK 0x33333333UL /**< Mask for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET0 << 0) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET1 << 0) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET2 << 0) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL0_OFFSET3 << 0) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET0 << 4) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET1 << 4) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET2 << 4) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL1_OFFSET3 << 4) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET0 << 8) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET1 << 8) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET2 << 8) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL2_OFFSET3 << 8) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET0 << 12) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET1 << 12) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET2 << 12) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL3_OFFSET3 << 12) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_SHIFT 16 /**< Shift value for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_MASK 0x30000UL /**< Bit mask for GPIO_EXTIPINSEL4 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET0 << 16) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET1 << 16) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET2 << 16) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL4_OFFSET3 << 16) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_SHIFT 20 /**< Shift value for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_MASK 0x300000UL /**< Bit mask for GPIO_EXTIPINSEL5 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET0 << 20) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET1 << 20) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET2 << 20) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL5_OFFSET3 << 20) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_SHIFT 24 /**< Shift value for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_MASK 0x3000000UL /**< Bit mask for GPIO_EXTIPINSEL6 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET0 << 24) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET1 << 24) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET2 << 24) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL6_OFFSET3 << 24) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_SHIFT 28 /**< Shift value for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_MASK 0x30000000UL /**< Bit mask for GPIO_EXTIPINSEL7 */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 0x00000000UL /**< Mode OFFSET0 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 0x00000001UL /**< Mode OFFSET1 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 0x00000002UL /**< Mode OFFSET2 for GPIO_EXTIPINSELL */ +#define _GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 0x00000003UL /**< Mode OFFSET3 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT (_GPIO_EXTIPINSELL_EXTIPINSEL7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET0 << 28) /**< Shifted mode OFFSET0 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET1 << 28) /**< Shifted mode OFFSET1 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET2 << 28) /**< Shifted mode OFFSET2 for GPIO_EXTIPINSELL */ +#define GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 (_GPIO_EXTIPINSELL_EXTIPINSEL7_OFFSET3 << 28) /**< Shifted mode OFFSET3 for GPIO_EXTIPINSELL */ + +/* Bit fields for GPIO EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_MASK 0x00003333UL /**< Mask for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_SHIFT 0 /**< Shift value for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK 0x3UL /**< Bit mask for GPIO_EXTIPINSEL0 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET8 << 0) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET9 << 0) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET10 << 0) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL0_OFFSET11 << 0) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT 4 /**< Shift value for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_MASK 0x30UL /**< Bit mask for GPIO_EXTIPINSEL1 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET8 << 4) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET9 << 4) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET10 << 4) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL1_OFFSET11 << 4) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_SHIFT 8 /**< Shift value for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_MASK 0x300UL /**< Bit mask for GPIO_EXTIPINSEL2 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET8 << 8) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET9 << 8) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET10 << 8) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL2_OFFSET11 << 8) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_SHIFT 12 /**< Shift value for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_MASK 0x3000UL /**< Bit mask for GPIO_EXTIPINSEL3 */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 0x00000000UL /**< Mode OFFSET8 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 0x00000001UL /**< Mode OFFSET9 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 0x00000002UL /**< Mode OFFSET10 for GPIO_EXTIPINSELH */ +#define _GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 0x00000003UL /**< Mode OFFSET11 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT (_GPIO_EXTIPINSELH_EXTIPINSEL3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET8 << 12) /**< Shifted mode OFFSET8 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET9 << 12) /**< Shifted mode OFFSET9 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET10 << 12) /**< Shifted mode OFFSET10 for GPIO_EXTIPINSELH */ +#define GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 (_GPIO_EXTIPINSELH_EXTIPINSEL3_OFFSET11 << 12) /**< Shifted mode OFFSET11 for GPIO_EXTIPINSELH */ + +/* Bit fields for GPIO EXTIRISE */ +#define _GPIO_EXTIRISE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_SHIFT 0 /**< Shift value for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIRISE */ +#define _GPIO_EXTIRISE_EXTIRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIRISE */ +#define GPIO_EXTIRISE_EXTIRISE_DEFAULT (_GPIO_EXTIRISE_EXTIRISE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIRISE */ + +/* Bit fields for GPIO EXTIFALL */ +#define _GPIO_EXTIFALL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_MASK 0x00000FFFUL /**< Mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_SHIFT 0 /**< Shift value for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_MASK 0xFFFUL /**< Bit mask for GPIO_EXTIFALL */ +#define _GPIO_EXTIFALL_EXTIFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EXTIFALL */ +#define GPIO_EXTIFALL_EXTIFALL_DEFAULT (_GPIO_EXTIFALL_EXTIFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EXTIFALL */ + +/* Bit fields for GPIO IF */ +#define _GPIO_IF_RESETVALUE 0x00000000UL /**< Default value for GPIO_IF */ +#define _GPIO_IF_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IF */ +#define GPIO_IF_EXTIF0 (0x1UL << 0) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF0_SHIFT 0 /**< Shift value for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_MASK 0x1UL /**< Bit mask for GPIO_EXTIF0 */ +#define _GPIO_IF_EXTIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF0_DEFAULT (_GPIO_IF_EXTIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1 (0x1UL << 1) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF1_SHIFT 1 /**< Shift value for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_MASK 0x2UL /**< Bit mask for GPIO_EXTIF1 */ +#define _GPIO_IF_EXTIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF1_DEFAULT (_GPIO_IF_EXTIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2 (0x1UL << 2) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF2_SHIFT 2 /**< Shift value for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_MASK 0x4UL /**< Bit mask for GPIO_EXTIF2 */ +#define _GPIO_IF_EXTIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF2_DEFAULT (_GPIO_IF_EXTIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3 (0x1UL << 3) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF3_SHIFT 3 /**< Shift value for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_MASK 0x8UL /**< Bit mask for GPIO_EXTIF3 */ +#define _GPIO_IF_EXTIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF3_DEFAULT (_GPIO_IF_EXTIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4 (0x1UL << 4) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF4_SHIFT 4 /**< Shift value for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_MASK 0x10UL /**< Bit mask for GPIO_EXTIF4 */ +#define _GPIO_IF_EXTIF4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF4_DEFAULT (_GPIO_IF_EXTIF4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5 (0x1UL << 5) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF5_SHIFT 5 /**< Shift value for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_MASK 0x20UL /**< Bit mask for GPIO_EXTIF5 */ +#define _GPIO_IF_EXTIF5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF5_DEFAULT (_GPIO_IF_EXTIF5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6 (0x1UL << 6) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF6_SHIFT 6 /**< Shift value for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_MASK 0x40UL /**< Bit mask for GPIO_EXTIF6 */ +#define _GPIO_IF_EXTIF6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF6_DEFAULT (_GPIO_IF_EXTIF6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7 (0x1UL << 7) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF7_SHIFT 7 /**< Shift value for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_MASK 0x80UL /**< Bit mask for GPIO_EXTIF7 */ +#define _GPIO_IF_EXTIF7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF7_DEFAULT (_GPIO_IF_EXTIF7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8 (0x1UL << 8) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF8_SHIFT 8 /**< Shift value for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_MASK 0x100UL /**< Bit mask for GPIO_EXTIF8 */ +#define _GPIO_IF_EXTIF8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF8_DEFAULT (_GPIO_IF_EXTIF8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9 (0x1UL << 9) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF9_SHIFT 9 /**< Shift value for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_MASK 0x200UL /**< Bit mask for GPIO_EXTIF9 */ +#define _GPIO_IF_EXTIF9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF9_DEFAULT (_GPIO_IF_EXTIF9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10 (0x1UL << 10) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF10_SHIFT 10 /**< Shift value for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_MASK 0x400UL /**< Bit mask for GPIO_EXTIF10 */ +#define _GPIO_IF_EXTIF10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF10_DEFAULT (_GPIO_IF_EXTIF10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11 (0x1UL << 11) /**< External Pin Flag */ +#define _GPIO_IF_EXTIF11_SHIFT 11 /**< Shift value for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_MASK 0x800UL /**< Bit mask for GPIO_EXTIF11 */ +#define _GPIO_IF_EXTIF11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EXTIF11_DEFAULT (_GPIO_IF_EXTIF11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IF */ +#define _GPIO_IF_EM4WU_SHIFT 16 /**< Shift value for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WU */ +#define _GPIO_IF_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IF */ +#define GPIO_IF_EM4WU_DEFAULT (_GPIO_IF_EM4WU_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IF */ + +/* Bit fields for GPIO IEN */ +#define _GPIO_IEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_IEN */ +#define _GPIO_IEN_MASK 0x0FFF0FFFUL /**< Mask for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0 (0x1UL << 0) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN0_SHIFT 0 /**< Shift value for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_MASK 0x1UL /**< Bit mask for GPIO_EXTIEN0 */ +#define _GPIO_IEN_EXTIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN0_DEFAULT (_GPIO_IEN_EXTIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1 (0x1UL << 1) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN1_SHIFT 1 /**< Shift value for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_MASK 0x2UL /**< Bit mask for GPIO_EXTIEN1 */ +#define _GPIO_IEN_EXTIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN1_DEFAULT (_GPIO_IEN_EXTIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2 (0x1UL << 2) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN2_SHIFT 2 /**< Shift value for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_MASK 0x4UL /**< Bit mask for GPIO_EXTIEN2 */ +#define _GPIO_IEN_EXTIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN2_DEFAULT (_GPIO_IEN_EXTIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3 (0x1UL << 3) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN3_SHIFT 3 /**< Shift value for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_MASK 0x8UL /**< Bit mask for GPIO_EXTIEN3 */ +#define _GPIO_IEN_EXTIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN3_DEFAULT (_GPIO_IEN_EXTIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4 (0x1UL << 4) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN4_SHIFT 4 /**< Shift value for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_MASK 0x10UL /**< Bit mask for GPIO_EXTIEN4 */ +#define _GPIO_IEN_EXTIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN4_DEFAULT (_GPIO_IEN_EXTIEN4_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5 (0x1UL << 5) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN5_SHIFT 5 /**< Shift value for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_MASK 0x20UL /**< Bit mask for GPIO_EXTIEN5 */ +#define _GPIO_IEN_EXTIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN5_DEFAULT (_GPIO_IEN_EXTIEN5_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6 (0x1UL << 6) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN6_SHIFT 6 /**< Shift value for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_MASK 0x40UL /**< Bit mask for GPIO_EXTIEN6 */ +#define _GPIO_IEN_EXTIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN6_DEFAULT (_GPIO_IEN_EXTIEN6_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7 (0x1UL << 7) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN7_SHIFT 7 /**< Shift value for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_MASK 0x80UL /**< Bit mask for GPIO_EXTIEN7 */ +#define _GPIO_IEN_EXTIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN7_DEFAULT (_GPIO_IEN_EXTIEN7_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8 (0x1UL << 8) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN8_SHIFT 8 /**< Shift value for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_MASK 0x100UL /**< Bit mask for GPIO_EXTIEN8 */ +#define _GPIO_IEN_EXTIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN8_DEFAULT (_GPIO_IEN_EXTIEN8_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9 (0x1UL << 9) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN9_SHIFT 9 /**< Shift value for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_MASK 0x200UL /**< Bit mask for GPIO_EXTIEN9 */ +#define _GPIO_IEN_EXTIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN9_DEFAULT (_GPIO_IEN_EXTIEN9_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10 (0x1UL << 10) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN10_SHIFT 10 /**< Shift value for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_MASK 0x400UL /**< Bit mask for GPIO_EXTIEN10 */ +#define _GPIO_IEN_EXTIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN10_DEFAULT (_GPIO_IEN_EXTIEN10_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11 (0x1UL << 11) /**< External Pin Enable */ +#define _GPIO_IEN_EXTIEN11_SHIFT 11 /**< Shift value for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_MASK 0x800UL /**< Bit mask for GPIO_EXTIEN11 */ +#define _GPIO_IEN_EXTIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EXTIEN11_DEFAULT (_GPIO_IEN_EXTIEN11_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0 (0x1UL << 16) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN0_SHIFT 16 /**< Shift value for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_MASK 0x10000UL /**< Bit mask for GPIO_EM4WUIEN0 */ +#define _GPIO_IEN_EM4WUIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN0_DEFAULT (_GPIO_IEN_EM4WUIEN0_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1 (0x1UL << 17) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN1_SHIFT 17 /**< Shift value for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_MASK 0x20000UL /**< Bit mask for GPIO_EM4WUIEN1 */ +#define _GPIO_IEN_EM4WUIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN1_DEFAULT (_GPIO_IEN_EM4WUIEN1_DEFAULT << 17) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2 (0x1UL << 18) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN2_SHIFT 18 /**< Shift value for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_MASK 0x40000UL /**< Bit mask for GPIO_EM4WUIEN2 */ +#define _GPIO_IEN_EM4WUIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN2_DEFAULT (_GPIO_IEN_EM4WUIEN2_DEFAULT << 18) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3 (0x1UL << 19) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN3_SHIFT 19 /**< Shift value for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_MASK 0x80000UL /**< Bit mask for GPIO_EM4WUIEN3 */ +#define _GPIO_IEN_EM4WUIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN3_DEFAULT (_GPIO_IEN_EM4WUIEN3_DEFAULT << 19) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4 (0x1UL << 20) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN4_SHIFT 20 /**< Shift value for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_MASK 0x100000UL /**< Bit mask for GPIO_EM4WUIEN4 */ +#define _GPIO_IEN_EM4WUIEN4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN4_DEFAULT (_GPIO_IEN_EM4WUIEN4_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5 (0x1UL << 21) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN5_SHIFT 21 /**< Shift value for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_MASK 0x200000UL /**< Bit mask for GPIO_EM4WUIEN5 */ +#define _GPIO_IEN_EM4WUIEN5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN5_DEFAULT (_GPIO_IEN_EM4WUIEN5_DEFAULT << 21) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6 (0x1UL << 22) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN6_SHIFT 22 /**< Shift value for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_MASK 0x400000UL /**< Bit mask for GPIO_EM4WUIEN6 */ +#define _GPIO_IEN_EM4WUIEN6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN6_DEFAULT (_GPIO_IEN_EM4WUIEN6_DEFAULT << 22) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7 (0x1UL << 23) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN7_SHIFT 23 /**< Shift value for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_MASK 0x800000UL /**< Bit mask for GPIO_EM4WUIEN7 */ +#define _GPIO_IEN_EM4WUIEN7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN7_DEFAULT (_GPIO_IEN_EM4WUIEN7_DEFAULT << 23) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8 (0x1UL << 24) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN8_SHIFT 24 /**< Shift value for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_MASK 0x1000000UL /**< Bit mask for GPIO_EM4WUIEN8 */ +#define _GPIO_IEN_EM4WUIEN8_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN8_DEFAULT (_GPIO_IEN_EM4WUIEN8_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9 (0x1UL << 25) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN9_SHIFT 25 /**< Shift value for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_MASK 0x2000000UL /**< Bit mask for GPIO_EM4WUIEN9 */ +#define _GPIO_IEN_EM4WUIEN9_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN9_DEFAULT (_GPIO_IEN_EM4WUIEN9_DEFAULT << 25) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10 (0x1UL << 26) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN10_SHIFT 26 /**< Shift value for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_MASK 0x4000000UL /**< Bit mask for GPIO_EM4WUIEN10 */ +#define _GPIO_IEN_EM4WUIEN10_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN10_DEFAULT (_GPIO_IEN_EM4WUIEN10_DEFAULT << 26) /**< Shifted mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11 (0x1UL << 27) /**< EM4 Wake Up Interrupt En */ +#define _GPIO_IEN_EM4WUIEN11_SHIFT 27 /**< Shift value for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_MASK 0x8000000UL /**< Bit mask for GPIO_EM4WUIEN11 */ +#define _GPIO_IEN_EM4WUIEN11_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_IEN */ +#define GPIO_IEN_EM4WUIEN11_DEFAULT (_GPIO_IEN_EM4WUIEN11_DEFAULT << 27) /**< Shifted mode DEFAULT for GPIO_IEN */ + +/* Bit fields for GPIO EM4WUEN */ +#define _GPIO_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_SHIFT 16 /**< Shift value for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUEN */ +#define _GPIO_EM4WUEN_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUEN */ +#define GPIO_EM4WUEN_EM4WUEN_DEFAULT (_GPIO_EM4WUEN_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUEN */ + +/* Bit fields for GPIO EM4WUPOL */ +#define _GPIO_EM4WUPOL_RESETVALUE 0x00000000UL /**< Default value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_MASK 0x0FFF0000UL /**< Mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_SHIFT 16 /**< Shift value for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_MASK 0xFFF0000UL /**< Bit mask for GPIO_EM4WUPOL */ +#define _GPIO_EM4WUPOL_EM4WUPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EM4WUPOL */ +#define GPIO_EM4WUPOL_EM4WUPOL_DEFAULT (_GPIO_EM4WUPOL_EM4WUPOL_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EM4WUPOL */ + +/* Bit fields for GPIO DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_RESETVALUE 0x0000000FUL /**< Default value for GPIO_DBGROUTEPEN */ +#define _GPIO_DBGROUTEPEN_MASK 0x0000000FUL /**< Mask for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN (0x1UL << 0) /**< Route Pin Enable */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT 0 /**< Shift value for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK 0x1UL /**< Bit mask for GPIO_SWCLKTCKPEN */ +#define _GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWCLKTCKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN (0x1UL << 1) /**< Route Location 0 */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT 1 /**< Shift value for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK 0x2UL /**< Bit mask for GPIO_SWDIOTMSPEN */ +#define _GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT (_GPIO_DBGROUTEPEN_SWDIOTMSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN (0x1UL << 2) /**< JTAG Test Debug Output Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDOPEN_SHIFT 2 /**< Shift value for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_MASK 0x4UL /**< Bit mask for GPIO_TDOPEN */ +#define _GPIO_DBGROUTEPEN_TDOPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDOPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDOPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN (0x1UL << 3) /**< JTAG Test Debug Input Pin Enable */ +#define _GPIO_DBGROUTEPEN_TDIPEN_SHIFT 3 /**< Shift value for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_MASK 0x8UL /**< Bit mask for GPIO_TDIPEN */ +#define _GPIO_DBGROUTEPEN_TDIPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for GPIO_DBGROUTEPEN */ +#define GPIO_DBGROUTEPEN_TDIPEN_DEFAULT (_GPIO_DBGROUTEPEN_TDIPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_DBGROUTEPEN */ + +/* Bit fields for GPIO TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TRACEROUTEPEN */ +#define _GPIO_TRACEROUTEPEN_MASK 0x00000007UL /**< Mask for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN (0x1UL << 0) /**< Serial Wire Viewer Output Pin Enable */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT 0 /**< Shift value for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_MASK 0x1UL /**< Bit mask for GPIO_SWVPEN */ +#define _GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT (_GPIO_TRACEROUTEPEN_SWVPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN (0x1UL << 1) /**< Trace Clk Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_SHIFT 1 /**< Shift value for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_MASK 0x2UL /**< Bit mask for GPIO_TRACECLKPEN */ +#define _GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACECLKPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN (0x1UL << 2) /**< Trace Data0 Pin Enable */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_SHIFT 2 /**< Shift value for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_MASK 0x4UL /**< Bit mask for GPIO_TRACEDATA0PEN */ +#define _GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TRACEROUTEPEN */ +#define GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT (_GPIO_TRACEROUTEPEN_TRACEDATA0PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TRACEROUTEPEN */ + +/* Bit fields for GPIO_CMU ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_ROUTEEN */ +#define _GPIO_CMU_ROUTEEN_MASK 0x0000000FUL /**< Mask for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_SHIFT 0 /**< Shift value for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_CLKOUT0PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_SHIFT 1 /**< Shift value for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_CLKOUT1PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN (0x1UL << 2) /**< CLKOUT2 pin enable control bit */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_SHIFT 2 /**< Shift value for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_MASK 0x4UL /**< Bit mask for GPIO_CLKOUT2PEN */ +#define _GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_ROUTEEN */ +#define GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT (_GPIO_CMU_ROUTEEN_CLKOUT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_CMU_ROUTEEN */ + +/* Bit fields for GPIO_CMU CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKIN0ROUTE */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKIN0ROUTE */ +#define GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKIN0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKIN0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT0ROUTE */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE */ +#define GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT0ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT1ROUTE */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE */ +#define GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT1ROUTE*/ + +/* Bit fields for GPIO_CMU CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_CMU_CLKOUT2ROUTE */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE */ +#define GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT (_GPIO_CMU_CLKOUT2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_CMU_CLKOUT2ROUTE*/ + +/* Bit fields for GPIO_DCDC ROUTEEN */ +#define _GPIO_DCDC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_DCDC_ROUTEEN */ +#define _GPIO_DCDC_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_DCDC_ROUTEEN */ +#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN (0x1UL << 0) /**< DCDCCOREHIDDEN pin enable control bit */ +#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_SHIFT 0 /**< Shift value for GPIO_DCDCCOREHIDDENPEN */ +#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_MASK 0x1UL /**< Bit mask for GPIO_DCDCCOREHIDDENPEN */ +#define _GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_DCDC_ROUTEEN */ +#define GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT (_GPIO_DCDC_ROUTEEN_DCDCCOREHIDDENPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_DCDC_ROUTEEN */ + +/* Bit fields for GPIO_FRC ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_ROUTEEN */ +#define _GPIO_FRC_ROUTEEN_MASK 0x00000007UL /**< Mask for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN (0x1UL << 0) /**< DCLK pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_SHIFT 0 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_MASK 0x1UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN (0x1UL << 1) /**< DFRAME pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_SHIFT 1 /**< Shift value for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_MASK 0x2UL /**< Bit mask for GPIO_DFRAMEPEN */ +#define _GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DFRAMEPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN (0x1UL << 2) /**< DOUT pin enable control bit */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_SHIFT 2 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_MASK 0x4UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_ROUTEEN */ +#define GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_FRC_ROUTEEN_DOUTPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_FRC_ROUTEEN */ + +/* Bit fields for GPIO_FRC DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PORT_DEFAULT (_GPIO_FRC_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define _GPIO_FRC_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DCLKROUTE */ +#define GPIO_FRC_DCLKROUTE_PIN_DEFAULT (_GPIO_FRC_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DCLKROUTE */ + +/* Bit fields for GPIO_FRC DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DFRAMEROUTE */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ +#define _GPIO_FRC_DFRAMEROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DFRAMEROUTE */ +#define GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT (_GPIO_FRC_DFRAMEROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DFRAMEROUTE*/ + +/* Bit fields for GPIO_FRC DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_FRC_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PORT_DEFAULT (_GPIO_FRC_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define _GPIO_FRC_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_FRC_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_FRC_DOUTROUTE */ +#define GPIO_FRC_DOUTROUTE_PIN_DEFAULT (_GPIO_FRC_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_FRC_DOUTROUTE */ + +/* Bit fields for GPIO_I2C ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_ROUTEEN */ +#define _GPIO_I2C_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN (0x1UL << 0) /**< SCL pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_SHIFT 0 /**< Shift value for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_MASK 0x1UL /**< Bit mask for GPIO_SCLPEN */ +#define _GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SCLPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN (0x1UL << 1) /**< SDA pin enable control bit */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_SHIFT 1 /**< Shift value for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_MASK 0x2UL /**< Bit mask for GPIO_SDAPEN */ +#define _GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_ROUTEEN */ +#define GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT (_GPIO_I2C_ROUTEEN_SDAPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_I2C_ROUTEEN */ + +/* Bit fields for GPIO_I2C SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SCLROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PORT_DEFAULT (_GPIO_I2C_SCLROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define _GPIO_I2C_SCLROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SCLROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SCLROUTE */ +#define GPIO_I2C_SCLROUTE_PIN_DEFAULT (_GPIO_I2C_SCLROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SCLROUTE */ + +/* Bit fields for GPIO_I2C SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_MASK 0x000F0003UL /**< Mask for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_I2C_SDAROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PORT_DEFAULT (_GPIO_I2C_SDAROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define _GPIO_I2C_SDAROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_I2C_SDAROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_I2C_SDAROUTE */ +#define GPIO_I2C_SDAROUTE_PIN_DEFAULT (_GPIO_I2C_SDAROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_I2C_SDAROUTE */ + +/* Bit fields for GPIO_LETIMER ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_ROUTEEN */ +#define _GPIO_LETIMER_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN (0x1UL << 0) /**< OUT0 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_SHIFT 0 /**< Shift value for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_MASK 0x1UL /**< Bit mask for GPIO_OUT0PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN (0x1UL << 1) /**< OUT1 pin enable control bit */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_SHIFT 1 /**< Shift value for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_MASK 0x2UL /**< Bit mask for GPIO_OUT1PEN */ +#define _GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_ROUTEEN */ +#define GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT (_GPIO_LETIMER_ROUTEEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_LETIMER_ROUTEEN*/ + +/* Bit fields for GPIO_LETIMER OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT0ROUTE */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT0ROUTE */ +#define GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT0ROUTE*/ + +/* Bit fields for GPIO_LETIMER OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_LETIMER_OUT1ROUTE */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_LETIMER_OUT1ROUTE */ +#define GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT (_GPIO_LETIMER_OUT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_LETIMER_OUT1ROUTE*/ + +/* Bit fields for GPIO_EUART ROUTEEN */ +#define _GPIO_EUART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_ROUTEEN */ +#define _GPIO_EUART_ROUTEEN_MASK 0x00000003UL /**< Mask for GPIO_EUART_ROUTEEN */ +#define GPIO_EUART_ROUTEEN_RTSPEN (0x1UL << 0) /**< RTS pin enable control bit */ +#define _GPIO_EUART_ROUTEEN_RTSPEN_SHIFT 0 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_EUART_ROUTEEN_RTSPEN_MASK 0x1UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_ROUTEEN */ +#define GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_EUART_ROUTEEN_RTSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_ROUTEEN */ +#define GPIO_EUART_ROUTEEN_TXPEN (0x1UL << 1) /**< TX pin enable control bit */ +#define _GPIO_EUART_ROUTEEN_TXPEN_SHIFT 1 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_EUART_ROUTEEN_TXPEN_MASK 0x2UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_EUART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_ROUTEEN */ +#define GPIO_EUART_ROUTEEN_TXPEN_DEFAULT (_GPIO_EUART_ROUTEEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_EUART_ROUTEEN */ + +/* Bit fields for GPIO_EUART CTSROUTE */ +#define _GPIO_EUART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_CTSROUTE */ +#define _GPIO_EUART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_CTSROUTE */ +#define _GPIO_EUART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_CTSROUTE */ +#define GPIO_EUART_CTSROUTE_PORT_DEFAULT (_GPIO_EUART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_CTSROUTE*/ +#define _GPIO_EUART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_CTSROUTE */ +#define GPIO_EUART_CTSROUTE_PIN_DEFAULT (_GPIO_EUART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_CTSROUTE*/ + +/* Bit fields for GPIO_EUART RTSROUTE */ +#define _GPIO_EUART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_RTSROUTE */ +#define _GPIO_EUART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_RTSROUTE */ +#define _GPIO_EUART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RTSROUTE */ +#define GPIO_EUART_RTSROUTE_PORT_DEFAULT (_GPIO_EUART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_RTSROUTE*/ +#define _GPIO_EUART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RTSROUTE */ +#define GPIO_EUART_RTSROUTE_PIN_DEFAULT (_GPIO_EUART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_RTSROUTE*/ + +/* Bit fields for GPIO_EUART RXROUTE */ +#define _GPIO_EUART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_RXROUTE */ +#define _GPIO_EUART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_RXROUTE */ +#define _GPIO_EUART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RXROUTE */ +#define GPIO_EUART_RXROUTE_PORT_DEFAULT (_GPIO_EUART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_RXROUTE */ +#define _GPIO_EUART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_RXROUTE */ +#define GPIO_EUART_RXROUTE_PIN_DEFAULT (_GPIO_EUART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_RXROUTE */ + +/* Bit fields for GPIO_EUART TXROUTE */ +#define _GPIO_EUART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_EUART_TXROUTE */ +#define _GPIO_EUART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_EUART_TXROUTE */ +#define _GPIO_EUART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_EUART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_EUART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_TXROUTE */ +#define GPIO_EUART_TXROUTE_PORT_DEFAULT (_GPIO_EUART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_EUART_TXROUTE */ +#define _GPIO_EUART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_EUART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_EUART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_EUART_TXROUTE */ +#define GPIO_EUART_TXROUTE_PIN_DEFAULT (_GPIO_EUART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_EUART_TXROUTE */ + +/* Bit fields for GPIO_MODEM ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ROUTEEN */ +#define _GPIO_MODEM_ROUTEEN_MASK 0x00007FFFUL /**< Mask for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN (0x1UL << 0) /**< ANT0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_SHIFT 0 /**< Shift value for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_MASK 0x1UL /**< Bit mask for GPIO_ANT0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN (0x1UL << 1) /**< ANT1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_SHIFT 1 /**< Shift value for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_MASK 0x2UL /**< Bit mask for GPIO_ANT1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN (0x1UL << 2) /**< ANTROLLOVER pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_SHIFT 2 /**< Shift value for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_MASK 0x4UL /**< Bit mask for GPIO_ANTROLLOVERPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTROLLOVERPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN (0x1UL << 3) /**< ANTRR0 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_SHIFT 3 /**< Shift value for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_MASK 0x8UL /**< Bit mask for GPIO_ANTRR0PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN (0x1UL << 4) /**< ANTRR1 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_SHIFT 4 /**< Shift value for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_MASK 0x10UL /**< Bit mask for GPIO_ANTRR1PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN (0x1UL << 5) /**< ANTRR2 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_SHIFT 5 /**< Shift value for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_MASK 0x20UL /**< Bit mask for GPIO_ANTRR2PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN (0x1UL << 6) /**< ANTRR3 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_SHIFT 6 /**< Shift value for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_MASK 0x40UL /**< Bit mask for GPIO_ANTRR3PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR3PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN (0x1UL << 7) /**< ANTRR4 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_SHIFT 7 /**< Shift value for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_MASK 0x80UL /**< Bit mask for GPIO_ANTRR4PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR4PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN (0x1UL << 8) /**< ANTRR5 pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_SHIFT 8 /**< Shift value for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_MASK 0x100UL /**< Bit mask for GPIO_ANTRR5PEN */ +#define _GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTRR5PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN (0x1UL << 9) /**< ANTSWEN pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_SHIFT 9 /**< Shift value for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_MASK 0x200UL /**< Bit mask for GPIO_ANTSWENPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWENPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN (0x1UL << 10) /**< ANTSWUS pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_SHIFT 10 /**< Shift value for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_MASK 0x400UL /**< Bit mask for GPIO_ANTSWUSPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTSWUSPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN (0x1UL << 11) /**< ANTTRIG pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_SHIFT 11 /**< Shift value for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_MASK 0x800UL /**< Bit mask for GPIO_ANTTRIGPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN (0x1UL << 12) /**< ANTTRIGSTOP pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_SHIFT 12 /**< Shift value for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_MASK 0x1000UL /**< Bit mask for GPIO_ANTTRIGSTOPPEN */ +#define _GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_ANTTRIGSTOPPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN (0x1UL << 13) /**< DCLK pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_SHIFT 13 /**< Shift value for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_MASK 0x2000UL /**< Bit mask for GPIO_DCLKPEN */ +#define _GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DCLKPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN (0x1UL << 14) /**< DOUT pin enable control bit */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_SHIFT 14 /**< Shift value for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_MASK 0x4000UL /**< Bit mask for GPIO_DOUTPEN */ +#define _GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ROUTEEN */ +#define GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT (_GPIO_MODEM_ROUTEEN_DOUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_MODEM_ROUTEEN */ + +/* Bit fields for GPIO_MODEM ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT0ROUTE */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ +#define _GPIO_MODEM_ANT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT0ROUTE */ +#define GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANT1ROUTE */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ +#define _GPIO_MODEM_ANT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANT1ROUTE */ +#define GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANT1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTROLLOVERROUTE */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ +#define GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTROLLOVERROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTROLLOVERROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR0ROUTE */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE */ +#define GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR0ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR1ROUTE */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE */ +#define GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR1ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR2ROUTE */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE */ +#define GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR2ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR3ROUTE */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE */ +#define GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR3ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR4ROUTE */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE */ +#define GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR4ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTRR5ROUTE */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE */ +#define GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTRR5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTRR5ROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWENROUTE */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWENROUTE */ +#define GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWENROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWENROUTE*/ + +/* Bit fields for GPIO_MODEM ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTSWUSROUTE */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE */ +#define GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTSWUSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTSWUSROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGROUTE */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE */ +#define GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGROUTE*/ + +/* Bit fields for GPIO_MODEM ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_ANTTRIGSTOPROUTE */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ +#define GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT (_GPIO_MODEM_ANTTRIGSTOPROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_ANTTRIGSTOPROUTE*/ + +/* Bit fields for GPIO_MODEM DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DCLKROUTE */ +#define _GPIO_MODEM_DCLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DCLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PORT_DEFAULT (_GPIO_MODEM_DCLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ +#define _GPIO_MODEM_DCLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DCLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DCLKROUTE */ +#define GPIO_MODEM_DCLKROUTE_PIN_DEFAULT (_GPIO_MODEM_DCLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DCLKROUTE*/ + +/* Bit fields for GPIO_MODEM DINROUTE */ +#define _GPIO_MODEM_DINROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DINROUTE */ +#define _GPIO_MODEM_DINROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DINROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PORT_DEFAULT (_GPIO_MODEM_DINROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ +#define _GPIO_MODEM_DINROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DINROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DINROUTE */ +#define GPIO_MODEM_DINROUTE_PIN_DEFAULT (_GPIO_MODEM_DINROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DINROUTE*/ + +/* Bit fields for GPIO_MODEM DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_MASK 0x000F0003UL /**< Mask for GPIO_MODEM_DOUTROUTE */ +#define _GPIO_MODEM_DOUTROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_MODEM_DOUTROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PORT_DEFAULT (_GPIO_MODEM_DOUTROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ +#define _GPIO_MODEM_DOUTROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_MODEM_DOUTROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_MODEM_DOUTROUTE */ +#define GPIO_MODEM_DOUTROUTE_PIN_DEFAULT (_GPIO_MODEM_DOUTROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_MODEM_DOUTROUTE*/ + +/* Bit fields for GPIO_PDM ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_ROUTEEN */ +#define _GPIO_PDM_ROUTEEN_MASK 0x00000001UL /**< Mask for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN (0x1UL << 0) /**< CLK pin enable control bit */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_SHIFT 0 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_MASK 0x1UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_ROUTEEN */ +#define GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT (_GPIO_PDM_ROUTEEN_CLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_ROUTEEN */ + +/* Bit fields for GPIO_PDM CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PORT_DEFAULT (_GPIO_PDM_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define _GPIO_PDM_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_CLKROUTE */ +#define GPIO_PDM_CLKROUTE_PIN_DEFAULT (_GPIO_PDM_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_CLKROUTE */ + +/* Bit fields for GPIO_PDM DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define _GPIO_PDM_DAT0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT0ROUTE */ +#define GPIO_PDM_DAT0ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT0ROUTE */ + +/* Bit fields for GPIO_PDM DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PDM_DAT1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PORT_DEFAULT (_GPIO_PDM_DAT1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define _GPIO_PDM_DAT1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PDM_DAT1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PDM_DAT1ROUTE */ +#define GPIO_PDM_DAT1ROUTE_PIN_DEFAULT (_GPIO_PDM_DAT1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PDM_DAT1ROUTE */ + +/* Bit fields for GPIO_PRS ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ROUTEEN */ +#define _GPIO_PRS_ROUTEEN_MASK 0x0000FFFFUL /**< Mask for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN (0x1UL << 0) /**< ASYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT 0 /**< Shift value for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_MASK 0x1UL /**< Bit mask for GPIO_ASYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN (0x1UL << 1) /**< ASYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_SHIFT 1 /**< Shift value for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_MASK 0x2UL /**< Bit mask for GPIO_ASYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN (0x1UL << 2) /**< ASYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_SHIFT 2 /**< Shift value for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_MASK 0x4UL /**< Bit mask for GPIO_ASYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN (0x1UL << 3) /**< ASYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_SHIFT 3 /**< Shift value for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_MASK 0x8UL /**< Bit mask for GPIO_ASYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN (0x1UL << 4) /**< ASYNCH4 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_SHIFT 4 /**< Shift value for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_MASK 0x10UL /**< Bit mask for GPIO_ASYNCH4PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH4PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN (0x1UL << 5) /**< ASYNCH5 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_SHIFT 5 /**< Shift value for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_MASK 0x20UL /**< Bit mask for GPIO_ASYNCH5PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH5PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN (0x1UL << 6) /**< ASYNCH6 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_SHIFT 6 /**< Shift value for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_MASK 0x40UL /**< Bit mask for GPIO_ASYNCH6PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH6PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN (0x1UL << 7) /**< ASYNCH7 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_SHIFT 7 /**< Shift value for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_MASK 0x80UL /**< Bit mask for GPIO_ASYNCH7PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH7PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN (0x1UL << 8) /**< ASYNCH8 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_SHIFT 8 /**< Shift value for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_MASK 0x100UL /**< Bit mask for GPIO_ASYNCH8PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH8PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN (0x1UL << 9) /**< ASYNCH9 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_SHIFT 9 /**< Shift value for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_MASK 0x200UL /**< Bit mask for GPIO_ASYNCH9PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH9PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN (0x1UL << 10) /**< ASYNCH10 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_SHIFT 10 /**< Shift value for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_MASK 0x400UL /**< Bit mask for GPIO_ASYNCH10PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH10PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN (0x1UL << 11) /**< ASYNCH11 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_SHIFT 11 /**< Shift value for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_MASK 0x800UL /**< Bit mask for GPIO_ASYNCH11PEN */ +#define _GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT (_GPIO_PRS_ROUTEEN_ASYNCH11PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN (0x1UL << 12) /**< SYNCH0 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT 12 /**< Shift value for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_MASK 0x1000UL /**< Bit mask for GPIO_SYNCH0PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH0PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN (0x1UL << 13) /**< SYNCH1 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_SHIFT 13 /**< Shift value for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_MASK 0x2000UL /**< Bit mask for GPIO_SYNCH1PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH1PEN_DEFAULT << 13) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN (0x1UL << 14) /**< SYNCH2 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_SHIFT 14 /**< Shift value for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_MASK 0x4000UL /**< Bit mask for GPIO_SYNCH2PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH2PEN_DEFAULT << 14) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN (0x1UL << 15) /**< SYNCH3 pin enable control bit */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_SHIFT 15 /**< Shift value for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_MASK 0x8000UL /**< Bit mask for GPIO_SYNCH3PEN */ +#define _GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ROUTEEN */ +#define GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT (_GPIO_PRS_ROUTEEN_SYNCH3PEN_DEFAULT << 15) /**< Shifted mode DEFAULT for GPIO_PRS_ROUTEEN */ + +/* Bit fields for GPIO_PRS ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH0ROUTE */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE */ +#define GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH1ROUTE */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE */ +#define GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH2ROUTE */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE */ +#define GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH3ROUTE */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE */ +#define GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH3ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH4ROUTE */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE */ +#define GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH4ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH4ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH5ROUTE */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE */ +#define GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH5ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH5ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH6ROUTE */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE */ +#define GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH6ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH6ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH7ROUTE */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE */ +#define GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH7ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH7ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH8ROUTE */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE */ +#define GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH8ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH8ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH9ROUTE */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE */ +#define GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH9ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH9ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH10ROUTE */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE */ +#define GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH10ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH10ROUTE*/ + +/* Bit fields for GPIO_PRS ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_ASYNCH11ROUTE */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE */ +#define GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT (_GPIO_PRS_ASYNCH11ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_ASYNCH11ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH0ROUTE */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH0ROUTE */ +#define GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH0ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH1ROUTE */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH1ROUTE */ +#define GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH1ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH2ROUTE */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH2ROUTE */ +#define GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH2ROUTE*/ + +/* Bit fields for GPIO_PRS SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_PRS_SYNCH3ROUTE */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_PRS_SYNCH3ROUTE */ +#define GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT (_GPIO_PRS_SYNCH3ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_PRS_SYNCH3ROUTE*/ + +/* Bit fields for GPIO_TIMER ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_ROUTEEN */ +#define _GPIO_TIMER_ROUTEEN_MASK 0x0000003FUL /**< Mask for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN (0x1UL << 0) /**< CC0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_SHIFT 0 /**< Shift value for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_MASK 0x1UL /**< Bit mask for GPIO_CC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN (0x1UL << 1) /**< CC1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_SHIFT 1 /**< Shift value for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_MASK 0x2UL /**< Bit mask for GPIO_CC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN (0x1UL << 2) /**< CC2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_SHIFT 2 /**< Shift value for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_MASK 0x4UL /**< Bit mask for GPIO_CC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CC2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN (0x1UL << 3) /**< CDTI0 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_SHIFT 3 /**< Shift value for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_MASK 0x8UL /**< Bit mask for GPIO_CCC0PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC0PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN (0x1UL << 4) /**< CDTI1 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_SHIFT 4 /**< Shift value for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_MASK 0x10UL /**< Bit mask for GPIO_CCC1PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC1PEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN (0x1UL << 5) /**< CDTI2 pin enable control bit */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_SHIFT 5 /**< Shift value for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_MASK 0x20UL /**< Bit mask for GPIO_CCC2PEN */ +#define _GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_ROUTEEN */ +#define GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT (_GPIO_TIMER_ROUTEEN_CCC2PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for GPIO_TIMER_ROUTEEN */ + +/* Bit fields for GPIO_TIMER CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC0ROUTE */ +#define _GPIO_TIMER_CC0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ +#define _GPIO_TIMER_CC0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC0ROUTE */ +#define GPIO_TIMER_CC0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC0ROUTE*/ + +/* Bit fields for GPIO_TIMER CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC1ROUTE */ +#define _GPIO_TIMER_CC1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ +#define _GPIO_TIMER_CC1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC1ROUTE */ +#define GPIO_TIMER_CC1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC1ROUTE*/ + +/* Bit fields for GPIO_TIMER CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CC2ROUTE */ +#define _GPIO_TIMER_CC2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CC2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CC2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ +#define _GPIO_TIMER_CC2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CC2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CC2ROUTE */ +#define GPIO_TIMER_CC2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CC2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CC2ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI0ROUTE */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI0ROUTE */ +#define GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI0ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI0ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI1ROUTE */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI1ROUTE */ +#define GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI1ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI1ROUTE*/ + +/* Bit fields for GPIO_TIMER CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_MASK 0x000F0003UL /**< Mask for GPIO_TIMER_CDTI2ROUTE */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_TIMER_CDTI2ROUTE */ +#define GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT (_GPIO_TIMER_CDTI2ROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_TIMER_CDTI2ROUTE*/ + +/* Bit fields for GPIO_USART ROUTEEN */ +#define _GPIO_USART_ROUTEEN_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_ROUTEEN */ +#define _GPIO_USART_ROUTEEN_MASK 0x0000001FUL /**< Mask for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN (0x1UL << 0) /**< CS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CSPEN_SHIFT 0 /**< Shift value for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_MASK 0x1UL /**< Bit mask for GPIO_CSPEN */ +#define _GPIO_USART_ROUTEEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CSPEN_DEFAULT (_GPIO_USART_ROUTEEN_CSPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN (0x1UL << 1) /**< RTS pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RTSPEN_SHIFT 1 /**< Shift value for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_MASK 0x2UL /**< Bit mask for GPIO_RTSPEN */ +#define _GPIO_USART_ROUTEEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RTSPEN_DEFAULT (_GPIO_USART_ROUTEEN_RTSPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN (0x1UL << 2) /**< RX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_RXPEN_SHIFT 2 /**< Shift value for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_MASK 0x4UL /**< Bit mask for GPIO_RXPEN */ +#define _GPIO_USART_ROUTEEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_RXPEN_DEFAULT (_GPIO_USART_ROUTEEN_RXPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN (0x1UL << 3) /**< SCLK pin enable control bit */ +#define _GPIO_USART_ROUTEEN_CLKPEN_SHIFT 3 /**< Shift value for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_MASK 0x8UL /**< Bit mask for GPIO_CLKPEN */ +#define _GPIO_USART_ROUTEEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_CLKPEN_DEFAULT (_GPIO_USART_ROUTEEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN (0x1UL << 4) /**< TX pin enable control bit */ +#define _GPIO_USART_ROUTEEN_TXPEN_SHIFT 4 /**< Shift value for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_MASK 0x10UL /**< Bit mask for GPIO_TXPEN */ +#define _GPIO_USART_ROUTEEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_ROUTEEN */ +#define GPIO_USART_ROUTEEN_TXPEN_DEFAULT (_GPIO_USART_ROUTEEN_TXPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_USART_ROUTEEN */ + +/* Bit fields for GPIO_USART CSROUTE */ +#define _GPIO_USART_CSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PORT_DEFAULT (_GPIO_USART_CSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ +#define _GPIO_USART_CSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CSROUTE */ +#define GPIO_USART_CSROUTE_PIN_DEFAULT (_GPIO_USART_CSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CSROUTE */ + +/* Bit fields for GPIO_USART CTSROUTE */ +#define _GPIO_USART_CTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CTSROUTE */ +#define _GPIO_USART_CTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PORT_DEFAULT (_GPIO_USART_CTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ +#define _GPIO_USART_CTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CTSROUTE */ +#define GPIO_USART_CTSROUTE_PIN_DEFAULT (_GPIO_USART_CTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CTSROUTE*/ + +/* Bit fields for GPIO_USART RTSROUTE */ +#define _GPIO_USART_RTSROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RTSROUTE */ +#define _GPIO_USART_RTSROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RTSROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PORT_DEFAULT (_GPIO_USART_RTSROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ +#define _GPIO_USART_RTSROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RTSROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RTSROUTE */ +#define GPIO_USART_RTSROUTE_PIN_DEFAULT (_GPIO_USART_RTSROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RTSROUTE*/ + +/* Bit fields for GPIO_USART RXROUTE */ +#define _GPIO_USART_RXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_RXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PORT_DEFAULT (_GPIO_USART_RXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ +#define _GPIO_USART_RXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_RXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_RXROUTE */ +#define GPIO_USART_RXROUTE_PIN_DEFAULT (_GPIO_USART_RXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_RXROUTE */ + +/* Bit fields for GPIO_USART CLKROUTE */ +#define _GPIO_USART_CLKROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_CLKROUTE */ +#define _GPIO_USART_CLKROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_CLKROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PORT_DEFAULT (_GPIO_USART_CLKROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ +#define _GPIO_USART_CLKROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_CLKROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_CLKROUTE */ +#define GPIO_USART_CLKROUTE_PIN_DEFAULT (_GPIO_USART_CLKROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_CLKROUTE*/ + +/* Bit fields for GPIO_USART TXROUTE */ +#define _GPIO_USART_TXROUTE_RESETVALUE 0x00000000UL /**< Default value for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_MASK 0x000F0003UL /**< Mask for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PORT_SHIFT 0 /**< Shift value for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_MASK 0x3UL /**< Bit mask for GPIO_PORT */ +#define _GPIO_USART_TXROUTE_PORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PORT_DEFAULT (_GPIO_USART_TXROUTE_PORT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +#define _GPIO_USART_TXROUTE_PIN_SHIFT 16 /**< Shift value for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_MASK 0xF0000UL /**< Bit mask for GPIO_PIN */ +#define _GPIO_USART_TXROUTE_PIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_USART_TXROUTE */ +#define GPIO_USART_TXROUTE_PIN_DEFAULT (_GPIO_USART_TXROUTE_PIN_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_USART_TXROUTE */ +/** @} End of group Parts */ + +#endif // EFR32BG22_GPIO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h index 25080fa..dcf401b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_gpio_port.h @@ -1,421 +1,421 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 GPIO Port register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef GPIO_PORT_H -#define GPIO_PORT_H - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @brief EFR32BG22 GPIO PORT - *****************************************************************************/ -typedef struct { - __IOM uint32_t CTRL; /**< Port control */ - __IOM uint32_t MODEL; /**< mode low */ - uint32_t RESERVED0[1]; /**< Reserved for future use */ - __IOM uint32_t MODEH; /**< mode high */ - __IOM uint32_t DOUT; /**< data out */ - __IM uint32_t DIN; /**< data in */ - uint32_t RESERVED1[6]; /**< Reserved for future use */ -} GPIO_PORT_TypeDef; - -/* Bit fields for GPIO_P CTRL */ -#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ -#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ -#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ -#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ -#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ -#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ -#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ -#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ - -/* Bit fields for GPIO_P MODEL */ -#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ -#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ -#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ -#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ -#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ -#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ -#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ -#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ -#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ -#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ -#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ - -/* Bit fields for GPIO_P MODEH */ -#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MASK 0x0000000FUL /**< Mask for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ -#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ -#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ -#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ -#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ - -/* Bit fields for GPIO_P DOUT */ -#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_MASK 0x000001FFUL /**< Mask for GPIO_P_DOUT */ -#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_MASK 0x1FFUL /**< Bit mask for GPIO_DOUT */ -#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ -#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ - -/* Bit fields for GPIO_P DIN */ -#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ -#define _GPIO_P_DIN_MASK 0x000001FFUL /**< Mask for GPIO_P_DIN */ -#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_MASK 0x1FFUL /**< Bit mask for GPIO_DIN */ -#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ -#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ -/** @} End of group Parts */ - -#endif // GPIO_PORT_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 GPIO Port register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef GPIO_PORT_H +#define GPIO_PORT_H + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @brief EFR32BG22 GPIO PORT + *****************************************************************************/ +typedef struct { + __IOM uint32_t CTRL; /**< Port control */ + __IOM uint32_t MODEL; /**< mode low */ + uint32_t RESERVED0[1]; /**< Reserved for future use */ + __IOM uint32_t MODEH; /**< mode high */ + __IOM uint32_t DOUT; /**< data out */ + __IM uint32_t DIN; /**< data in */ + uint32_t RESERVED1[6]; /**< Reserved for future use */ +} GPIO_PORT_TypeDef; + +/* Bit fields for GPIO_P CTRL */ +#define _GPIO_P_CTRL_RESETVALUE 0x00400040UL /**< Default value for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_MASK 0x10701070UL /**< Mask for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATE_SHIFT 4 /**< Shift value for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_MASK 0x70UL /**< Bit mask for GPIO_SLEWRATE */ +#define _GPIO_P_CTRL_SLEWRATE_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATE_DEFAULT (_GPIO_P_CTRL_SLEWRATE_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS (0x1UL << 12) /**< Data In Disable */ +#define _GPIO_P_CTRL_DINDIS_SHIFT 12 /**< Shift value for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_MASK 0x1000UL /**< Bit mask for GPIO_DINDIS */ +#define _GPIO_P_CTRL_DINDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDIS_DEFAULT (_GPIO_P_CTRL_DINDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define _GPIO_P_CTRL_SLEWRATEALT_SHIFT 20 /**< Shift value for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_MASK 0x700000UL /**< Bit mask for GPIO_SLEWRATEALT */ +#define _GPIO_P_CTRL_SLEWRATEALT_DEFAULT 0x00000004UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_SLEWRATEALT_DEFAULT (_GPIO_P_CTRL_SLEWRATEALT_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT (0x1UL << 28) /**< Data In Disable Alt */ +#define _GPIO_P_CTRL_DINDISALT_SHIFT 28 /**< Shift value for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_MASK 0x10000000UL /**< Bit mask for GPIO_DINDISALT */ +#define _GPIO_P_CTRL_DINDISALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_CTRL */ +#define GPIO_P_CTRL_DINDISALT_DEFAULT (_GPIO_P_CTRL_DINDISALT_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_CTRL */ + +/* Bit fields for GPIO_P MODEL */ +#define _GPIO_P_MODEL_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MASK 0xFFFFFFFFUL /**< Mask for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEL_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_DEFAULT (_GPIO_P_MODEL_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_DISABLED (_GPIO_P_MODEL_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUT (_GPIO_P_MODEL_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULL (_GPIO_P_MODEL_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_INPUTPULLFILTER (_GPIO_P_MODEL_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_PUSHPULL (_GPIO_P_MODEL_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_PUSHPULLALT (_GPIO_P_MODEL_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDOR (_GPIO_P_MODEL_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDAND (_GPIO_P_MODEL_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDFILTER (_GPIO_P_MODEL_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALT (_GPIO_P_MODEL_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE1_SHIFT 4 /**< Shift value for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_MASK 0xF0UL /**< Bit mask for GPIO_MODE1 */ +#define _GPIO_P_MODEL_MODE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_DEFAULT (_GPIO_P_MODEL_MODE1_DEFAULT << 4) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_DISABLED (_GPIO_P_MODEL_MODE1_DISABLED << 4) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUT (_GPIO_P_MODEL_MODE1_INPUT << 4) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULL (_GPIO_P_MODEL_MODE1_INPUTPULL << 4) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_INPUTPULLFILTER (_GPIO_P_MODEL_MODE1_INPUTPULLFILTER << 4) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_PUSHPULL (_GPIO_P_MODEL_MODE1_PUSHPULL << 4) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_PUSHPULLALT (_GPIO_P_MODEL_MODE1_PUSHPULLALT << 4) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDOR (_GPIO_P_MODEL_MODE1_WIREDOR << 4) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE1_WIREDORPULLDOWN << 4) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDAND (_GPIO_P_MODEL_MODE1_WIREDAND << 4) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDFILTER (_GPIO_P_MODEL_MODE1_WIREDANDFILTER << 4) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDPULLUP << 4) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDPULLUPFILTER << 4) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALT (_GPIO_P_MODEL_MODE1_WIREDANDALT << 4) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE1_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTFILTER << 4) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUP << 4) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE1_WIREDANDALTPULLUPFILTER << 4) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE2_SHIFT 8 /**< Shift value for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_MASK 0xF00UL /**< Bit mask for GPIO_MODE2 */ +#define _GPIO_P_MODEL_MODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_DEFAULT (_GPIO_P_MODEL_MODE2_DEFAULT << 8) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_DISABLED (_GPIO_P_MODEL_MODE2_DISABLED << 8) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUT (_GPIO_P_MODEL_MODE2_INPUT << 8) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULL (_GPIO_P_MODEL_MODE2_INPUTPULL << 8) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_INPUTPULLFILTER (_GPIO_P_MODEL_MODE2_INPUTPULLFILTER << 8) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_PUSHPULL (_GPIO_P_MODEL_MODE2_PUSHPULL << 8) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_PUSHPULLALT (_GPIO_P_MODEL_MODE2_PUSHPULLALT << 8) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDOR (_GPIO_P_MODEL_MODE2_WIREDOR << 8) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE2_WIREDORPULLDOWN << 8) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDAND (_GPIO_P_MODEL_MODE2_WIREDAND << 8) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDFILTER (_GPIO_P_MODEL_MODE2_WIREDANDFILTER << 8) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDPULLUP << 8) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDPULLUPFILTER << 8) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALT (_GPIO_P_MODEL_MODE2_WIREDANDALT << 8) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE2_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTFILTER << 8) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUP << 8) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE2_WIREDANDALTPULLUPFILTER << 8) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE3_SHIFT 12 /**< Shift value for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_MASK 0xF000UL /**< Bit mask for GPIO_MODE3 */ +#define _GPIO_P_MODEL_MODE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_DEFAULT (_GPIO_P_MODEL_MODE3_DEFAULT << 12) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_DISABLED (_GPIO_P_MODEL_MODE3_DISABLED << 12) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUT (_GPIO_P_MODEL_MODE3_INPUT << 12) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULL (_GPIO_P_MODEL_MODE3_INPUTPULL << 12) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_INPUTPULLFILTER (_GPIO_P_MODEL_MODE3_INPUTPULLFILTER << 12) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_PUSHPULL (_GPIO_P_MODEL_MODE3_PUSHPULL << 12) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_PUSHPULLALT (_GPIO_P_MODEL_MODE3_PUSHPULLALT << 12) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDOR (_GPIO_P_MODEL_MODE3_WIREDOR << 12) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE3_WIREDORPULLDOWN << 12) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDAND (_GPIO_P_MODEL_MODE3_WIREDAND << 12) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDFILTER (_GPIO_P_MODEL_MODE3_WIREDANDFILTER << 12) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDPULLUP << 12) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDPULLUPFILTER << 12) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALT (_GPIO_P_MODEL_MODE3_WIREDANDALT << 12) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE3_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTFILTER << 12) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUP << 12) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE3_WIREDANDALTPULLUPFILTER << 12) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE4_SHIFT 16 /**< Shift value for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_MASK 0xF0000UL /**< Bit mask for GPIO_MODE4 */ +#define _GPIO_P_MODEL_MODE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_DEFAULT (_GPIO_P_MODEL_MODE4_DEFAULT << 16) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_DISABLED (_GPIO_P_MODEL_MODE4_DISABLED << 16) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUT (_GPIO_P_MODEL_MODE4_INPUT << 16) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULL (_GPIO_P_MODEL_MODE4_INPUTPULL << 16) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_INPUTPULLFILTER (_GPIO_P_MODEL_MODE4_INPUTPULLFILTER << 16) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_PUSHPULL (_GPIO_P_MODEL_MODE4_PUSHPULL << 16) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_PUSHPULLALT (_GPIO_P_MODEL_MODE4_PUSHPULLALT << 16) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDOR (_GPIO_P_MODEL_MODE4_WIREDOR << 16) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE4_WIREDORPULLDOWN << 16) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDAND (_GPIO_P_MODEL_MODE4_WIREDAND << 16) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDFILTER (_GPIO_P_MODEL_MODE4_WIREDANDFILTER << 16) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDPULLUP << 16) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDPULLUPFILTER << 16) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALT (_GPIO_P_MODEL_MODE4_WIREDANDALT << 16) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE4_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTFILTER << 16) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUP << 16) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE4_WIREDANDALTPULLUPFILTER << 16) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE5_SHIFT 20 /**< Shift value for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_MASK 0xF00000UL /**< Bit mask for GPIO_MODE5 */ +#define _GPIO_P_MODEL_MODE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_DEFAULT (_GPIO_P_MODEL_MODE5_DEFAULT << 20) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_DISABLED (_GPIO_P_MODEL_MODE5_DISABLED << 20) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUT (_GPIO_P_MODEL_MODE5_INPUT << 20) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULL (_GPIO_P_MODEL_MODE5_INPUTPULL << 20) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_INPUTPULLFILTER (_GPIO_P_MODEL_MODE5_INPUTPULLFILTER << 20) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_PUSHPULL (_GPIO_P_MODEL_MODE5_PUSHPULL << 20) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_PUSHPULLALT (_GPIO_P_MODEL_MODE5_PUSHPULLALT << 20) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDOR (_GPIO_P_MODEL_MODE5_WIREDOR << 20) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE5_WIREDORPULLDOWN << 20) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDAND (_GPIO_P_MODEL_MODE5_WIREDAND << 20) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDFILTER (_GPIO_P_MODEL_MODE5_WIREDANDFILTER << 20) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDPULLUP << 20) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDPULLUPFILTER << 20) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALT (_GPIO_P_MODEL_MODE5_WIREDANDALT << 20) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE5_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTFILTER << 20) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUP << 20) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE5_WIREDANDALTPULLUPFILTER << 20) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE6_SHIFT 24 /**< Shift value for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_MASK 0xF000000UL /**< Bit mask for GPIO_MODE6 */ +#define _GPIO_P_MODEL_MODE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_DEFAULT (_GPIO_P_MODEL_MODE6_DEFAULT << 24) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_DISABLED (_GPIO_P_MODEL_MODE6_DISABLED << 24) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUT (_GPIO_P_MODEL_MODE6_INPUT << 24) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULL (_GPIO_P_MODEL_MODE6_INPUTPULL << 24) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_INPUTPULLFILTER (_GPIO_P_MODEL_MODE6_INPUTPULLFILTER << 24) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_PUSHPULL (_GPIO_P_MODEL_MODE6_PUSHPULL << 24) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_PUSHPULLALT (_GPIO_P_MODEL_MODE6_PUSHPULLALT << 24) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDOR (_GPIO_P_MODEL_MODE6_WIREDOR << 24) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE6_WIREDORPULLDOWN << 24) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDAND (_GPIO_P_MODEL_MODE6_WIREDAND << 24) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDFILTER (_GPIO_P_MODEL_MODE6_WIREDANDFILTER << 24) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDPULLUP << 24) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDPULLUPFILTER << 24) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALT (_GPIO_P_MODEL_MODE6_WIREDANDALT << 24) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE6_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTFILTER << 24) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUP << 24) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE6_WIREDANDALTPULLUPFILTER << 24) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define _GPIO_P_MODEL_MODE7_SHIFT 28 /**< Shift value for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_MASK 0xF0000000UL /**< Bit mask for GPIO_MODE7 */ +#define _GPIO_P_MODEL_MODE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEL */ +#define _GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_DEFAULT (_GPIO_P_MODEL_MODE7_DEFAULT << 28) /**< Shifted mode DEFAULT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_DISABLED (_GPIO_P_MODEL_MODE7_DISABLED << 28) /**< Shifted mode DISABLED for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUT (_GPIO_P_MODEL_MODE7_INPUT << 28) /**< Shifted mode INPUT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULL (_GPIO_P_MODEL_MODE7_INPUTPULL << 28) /**< Shifted mode INPUTPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_INPUTPULLFILTER (_GPIO_P_MODEL_MODE7_INPUTPULLFILTER << 28) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_PUSHPULL (_GPIO_P_MODEL_MODE7_PUSHPULL << 28) /**< Shifted mode PUSHPULL for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_PUSHPULLALT (_GPIO_P_MODEL_MODE7_PUSHPULLALT << 28) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDOR (_GPIO_P_MODEL_MODE7_WIREDOR << 28) /**< Shifted mode WIREDOR for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDORPULLDOWN (_GPIO_P_MODEL_MODE7_WIREDORPULLDOWN << 28) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDAND (_GPIO_P_MODEL_MODE7_WIREDAND << 28) /**< Shifted mode WIREDAND for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDFILTER (_GPIO_P_MODEL_MODE7_WIREDANDFILTER << 28) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDPULLUP << 28) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDPULLUPFILTER << 28) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALT (_GPIO_P_MODEL_MODE7_WIREDANDALT << 28) /**< Shifted mode WIREDANDALT for GPIO_P_MODEL */ +#define GPIO_P_MODEL_MODE7_WIREDANDALTFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTFILTER << 28) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUP << 28) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEL*/ +#define GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEL_MODE7_WIREDANDALTPULLUPFILTER << 28) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEL*/ + +/* Bit fields for GPIO_P MODEH */ +#define _GPIO_P_MODEH_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MASK 0x0000000FUL /**< Mask for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_SHIFT 0 /**< Shift value for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_MASK 0xFUL /**< Bit mask for GPIO_MODE0 */ +#define _GPIO_P_MODEH_MODE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_DISABLED 0x00000000UL /**< Mode DISABLED for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUT 0x00000001UL /**< Mode INPUT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULL 0x00000002UL /**< Mode INPUTPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_INPUTPULLFILTER 0x00000003UL /**< Mode INPUTPULLFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULL 0x00000004UL /**< Mode PUSHPULL for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_PUSHPULLALT 0x00000005UL /**< Mode PUSHPULLALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDOR 0x00000006UL /**< Mode WIREDOR for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDORPULLDOWN 0x00000007UL /**< Mode WIREDORPULLDOWN for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDAND 0x00000008UL /**< Mode WIREDAND for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDFILTER 0x00000009UL /**< Mode WIREDANDFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUP 0x0000000AUL /**< Mode WIREDANDPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER 0x0000000BUL /**< Mode WIREDANDPULLUPFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALT 0x0000000CUL /**< Mode WIREDANDALT for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTFILTER 0x0000000DUL /**< Mode WIREDANDALTFILTER for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP 0x0000000EUL /**< Mode WIREDANDALTPULLUP for GPIO_P_MODEH */ +#define _GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER 0x0000000FUL /**< Mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_DEFAULT (_GPIO_P_MODEH_MODE0_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_DISABLED (_GPIO_P_MODEH_MODE0_DISABLED << 0) /**< Shifted mode DISABLED for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUT (_GPIO_P_MODEH_MODE0_INPUT << 0) /**< Shifted mode INPUT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULL (_GPIO_P_MODEH_MODE0_INPUTPULL << 0) /**< Shifted mode INPUTPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_INPUTPULLFILTER (_GPIO_P_MODEH_MODE0_INPUTPULLFILTER << 0) /**< Shifted mode INPUTPULLFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_PUSHPULL (_GPIO_P_MODEH_MODE0_PUSHPULL << 0) /**< Shifted mode PUSHPULL for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_PUSHPULLALT (_GPIO_P_MODEH_MODE0_PUSHPULLALT << 0) /**< Shifted mode PUSHPULLALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDOR (_GPIO_P_MODEH_MODE0_WIREDOR << 0) /**< Shifted mode WIREDOR for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDORPULLDOWN (_GPIO_P_MODEH_MODE0_WIREDORPULLDOWN << 0) /**< Shifted mode WIREDORPULLDOWN for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDAND (_GPIO_P_MODEH_MODE0_WIREDAND << 0) /**< Shifted mode WIREDAND for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDFILTER (_GPIO_P_MODEH_MODE0_WIREDANDFILTER << 0) /**< Shifted mode WIREDANDFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDPULLUP << 0) /**< Shifted mode WIREDANDPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDPULLUPFILTER << 0) /**< Shifted mode WIREDANDPULLUPFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALT (_GPIO_P_MODEH_MODE0_WIREDANDALT << 0) /**< Shifted mode WIREDANDALT for GPIO_P_MODEH */ +#define GPIO_P_MODEH_MODE0_WIREDANDALTFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTFILTER << 0) /**< Shifted mode WIREDANDALTFILTER for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUP << 0) /**< Shifted mode WIREDANDALTPULLUP for GPIO_P_MODEH*/ +#define GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER (_GPIO_P_MODEH_MODE0_WIREDANDALTPULLUPFILTER << 0) /**< Shifted mode WIREDANDALTPULLUPFILTER for GPIO_P_MODEH*/ + +/* Bit fields for GPIO_P DOUT */ +#define _GPIO_P_DOUT_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_MASK 0x000001FFUL /**< Mask for GPIO_P_DOUT */ +#define _GPIO_P_DOUT_DOUT_SHIFT 0 /**< Shift value for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_MASK 0x1FFUL /**< Bit mask for GPIO_DOUT */ +#define _GPIO_P_DOUT_DOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DOUT */ +#define GPIO_P_DOUT_DOUT_DEFAULT (_GPIO_P_DOUT_DOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DOUT */ + +/* Bit fields for GPIO_P DIN */ +#define _GPIO_P_DIN_RESETVALUE 0x00000000UL /**< Default value for GPIO_P_DIN */ +#define _GPIO_P_DIN_MASK 0x000001FFUL /**< Mask for GPIO_P_DIN */ +#define _GPIO_P_DIN_DIN_SHIFT 0 /**< Shift value for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_MASK 0x1FFUL /**< Bit mask for GPIO_DIN */ +#define _GPIO_P_DIN_DIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPIO_P_DIN */ +#define GPIO_P_DIN_DIN_DEFAULT (_GPIO_P_DIN_DIN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPIO_P_DIN */ +/** @} End of group Parts */ + +#endif // GPIO_PORT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h index b077d9f..37b4ccb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfrco.h @@ -1,221 +1,221 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 HFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_HFRCO_H -#define EFR32BG22_HFRCO_H -#define HFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_HFRCO HFRCO - * @{ - * @brief EFR32BG22 HFRCO Register Declaration. - *****************************************************************************/ - -/** HFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t CTRL; /**< Ctrl Register */ - __IOM uint32_t CAL; /**< Calibration Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Lock Register */ - uint32_t RESERVED1[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t CTRL_SET; /**< Ctrl Register */ - __IOM uint32_t CAL_SET; /**< Calibration Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - uint32_t RESERVED3[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ - __IOM uint32_t CAL_CLR; /**< Calibration Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - uint32_t RESERVED5[1016U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ - __IOM uint32_t CAL_TGL; /**< Calibration Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ -} HFRCO_TypeDef; -/** @} End of group EFR32BG22_HFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_HFRCO - * @{ - * @defgroup EFR32BG22_HFRCO_BitFields HFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for HFRCO IPVERSION */ -#define _HFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ -#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_IPVERSION */ -#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ - -/* Bit fields for HFRCO CTRL */ -#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ -#define _HFRCO_CTRL_MASK 0x00000003UL /**< Mask for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ -#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ -#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ -#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ -#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ - -/* Bit fields for HFRCO CAL */ -#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ -#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ -#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ -#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ -#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ -#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ -#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ -#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ -#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ -#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ -#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ -#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ -#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ -#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ -#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ -#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ -#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ - -/* Bit fields for HFRCO STATUS */ -#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ -#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ -#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ -#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ -#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ -#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ -#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ -#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ -#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ -#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ -#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ - -/* Bit fields for HFRCO IF */ -#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ -#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ -#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ -#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ - -/* Bit fields for HFRCO IEN */ -#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ -#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ -#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ -#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ -#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ -#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ - -/* Bit fields for HFRCO LOCK */ -#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ -#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ -#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ -#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ -#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ - -/** @} End of group EFR32BG22_HFRCO_BitFields */ -/** @} End of group EFR32BG22_HFRCO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_HFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 HFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_HFRCO_H +#define EFR32BG22_HFRCO_H +#define HFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_HFRCO HFRCO + * @{ + * @brief EFR32BG22 HFRCO Register Declaration. + *****************************************************************************/ + +/** HFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t CTRL; /**< Ctrl Register */ + __IOM uint32_t CAL; /**< Calibration Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Lock Register */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t CTRL_SET; /**< Ctrl Register */ + __IOM uint32_t CAL_SET; /**< Calibration Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + uint32_t RESERVED3[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t CTRL_CLR; /**< Ctrl Register */ + __IOM uint32_t CAL_CLR; /**< Calibration Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + uint32_t RESERVED5[1016U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t CTRL_TGL; /**< Ctrl Register */ + __IOM uint32_t CAL_TGL; /**< Calibration Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ +} HFRCO_TypeDef; +/** @} End of group EFR32BG22_HFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_HFRCO + * @{ + * @defgroup EFR32BG22_HFRCO_BitFields HFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFRCO IPVERSION */ +#define _HFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFRCO_IPVERSION */ +#define _HFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_IPVERSION */ +#define HFRCO_IPVERSION_IPVERSION_DEFAULT (_HFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IPVERSION */ + +/* Bit fields for HFRCO CTRL */ +#define _HFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for HFRCO_CTRL */ +#define _HFRCO_CTRL_MASK 0x00000003UL /**< Mask for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFRCO_FORCEEN */ +#define _HFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_FORCEEN_DEFAULT (_HFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand */ +#define _HFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFRCO_DISONDEMAND */ +#define _HFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CTRL */ +#define HFRCO_CTRL_DISONDEMAND_DEFAULT (_HFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_CTRL */ + +/* Bit fields for HFRCO CAL */ +#define _HFRCO_CAL_RESETVALUE 0xA8689F7FUL /**< Default value for HFRCO_CAL */ +#define _HFRCO_CAL_MASK 0xFFFFBF7FUL /**< Mask for HFRCO_CAL */ +#define _HFRCO_CAL_TUNING_SHIFT 0 /**< Shift value for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_MASK 0x7FUL /**< Bit mask for HFRCO_TUNING */ +#define _HFRCO_CAL_TUNING_DEFAULT 0x0000007FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_TUNING_DEFAULT (_HFRCO_CAL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FINETUNING_SHIFT 8 /**< Shift value for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_MASK 0x3F00UL /**< Bit mask for HFRCO_FINETUNING */ +#define _HFRCO_CAL_FINETUNING_DEFAULT 0x0000001FUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FINETUNING_DEFAULT (_HFRCO_CAL_FINETUNING_DEFAULT << 8) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP (0x1UL << 15) /**< LDO High Power Mode */ +#define _HFRCO_CAL_LDOHP_SHIFT 15 /**< Shift value for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_MASK 0x8000UL /**< Bit mask for HFRCO_LDOHP */ +#define _HFRCO_CAL_LDOHP_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_LDOHP_DEFAULT (_HFRCO_CAL_LDOHP_DEFAULT << 15) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_FREQRANGE_SHIFT 16 /**< Shift value for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for HFRCO_FREQRANGE */ +#define _HFRCO_CAL_FREQRANGE_DEFAULT 0x00000008UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_FREQRANGE_DEFAULT (_HFRCO_CAL_FREQRANGE_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CMPBIAS_SHIFT 21 /**< Shift value for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_MASK 0xE00000UL /**< Bit mask for HFRCO_CMPBIAS */ +#define _HFRCO_CAL_CMPBIAS_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPBIAS_DEFAULT (_HFRCO_CAL_CMPBIAS_DEFAULT << 21) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_SHIFT 24 /**< Shift value for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_MASK 0x3000000UL /**< Bit mask for HFRCO_CLKDIV */ +#define _HFRCO_CAL_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV1 0x00000000UL /**< Mode DIV1 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV2 0x00000001UL /**< Mode DIV2 for HFRCO_CAL */ +#define _HFRCO_CAL_CLKDIV_DIV4 0x00000002UL /**< Mode DIV4 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DEFAULT (_HFRCO_CAL_CLKDIV_DEFAULT << 24) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV1 (_HFRCO_CAL_CLKDIV_DIV1 << 24) /**< Shifted mode DIV1 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV2 (_HFRCO_CAL_CLKDIV_DIV2 << 24) /**< Shifted mode DIV2 for HFRCO_CAL */ +#define HFRCO_CAL_CLKDIV_DIV4 (_HFRCO_CAL_CLKDIV_DIV4 << 24) /**< Shifted mode DIV4 for HFRCO_CAL */ +#define _HFRCO_CAL_CMPSEL_SHIFT 26 /**< Shift value for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_MASK 0xC000000UL /**< Bit mask for HFRCO_CMPSEL */ +#define _HFRCO_CAL_CMPSEL_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_CMPSEL_DEFAULT (_HFRCO_CAL_CMPSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for HFRCO_CAL */ +#define _HFRCO_CAL_IREFTC_SHIFT 28 /**< Shift value for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_MASK 0xF0000000UL /**< Bit mask for HFRCO_IREFTC */ +#define _HFRCO_CAL_IREFTC_DEFAULT 0x0000000AUL /**< Mode DEFAULT for HFRCO_CAL */ +#define HFRCO_CAL_IREFTC_DEFAULT (_HFRCO_CAL_IREFTC_DEFAULT << 28) /**< Shifted mode DEFAULT for HFRCO_CAL */ + +/* Bit fields for HFRCO STATUS */ +#define _HFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFRCO_STATUS */ +#define _HFRCO_STATUS_MASK 0x80010007UL /**< Mask for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY (0x1UL << 0) /**< Ready */ +#define _HFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_RDY_DEFAULT (_HFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY (0x1UL << 1) /**< Frequency Updating Busy */ +#define _HFRCO_STATUS_FREQBSY_SHIFT 1 /**< Shift value for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_MASK 0x2UL /**< Bit mask for HFRCO_FREQBSY */ +#define _HFRCO_STATUS_FREQBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_FREQBSY_DEFAULT (_HFRCO_STATUS_FREQBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY (0x1UL << 2) /**< Synchronization Busy */ +#define _HFRCO_STATUS_SYNCBUSY_SHIFT 2 /**< Shift value for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_MASK 0x4UL /**< Bit mask for HFRCO_SYNCBUSY */ +#define _HFRCO_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_SYNCBUSY_DEFAULT (_HFRCO_STATUS_SYNCBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _HFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFRCO_ENS */ +#define _HFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_ENS_DEFAULT (_HFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _HFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFRCO_LOCK */ +#define _HFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFRCO_STATUS */ +#define _HFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_DEFAULT (_HFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_UNLOCKED (_HFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFRCO_STATUS */ +#define HFRCO_STATUS_LOCK_LOCKED (_HFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFRCO_STATUS */ + +/* Bit fields for HFRCO IF */ +#define _HFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IF */ +#define _HFRCO_IF_MASK 0x00000001UL /**< Mask for HFRCO_IF */ +#define HFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _HFRCO_IF_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IF */ +#define HFRCO_IF_RDY_DEFAULT (_HFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IF */ + +/* Bit fields for HFRCO IEN */ +#define _HFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFRCO_IEN */ +#define _HFRCO_IEN_MASK 0x00000001UL /**< Mask for HFRCO_IEN */ +#define HFRCO_IEN_RDY (0x1UL << 0) /**< RDY Interrupt Enable */ +#define _HFRCO_IEN_RDY_SHIFT 0 /**< Shift value for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFRCO_RDY */ +#define _HFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFRCO_IEN */ +#define HFRCO_IEN_RDY_DEFAULT (_HFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_IEN */ + +/* Bit fields for HFRCO LOCK */ +#define _HFRCO_LOCK_RESETVALUE 0x00008195UL /**< Default value for HFRCO_LOCK */ +#define _HFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFRCO_LOCKKEY */ +#define _HFRCO_LOCK_LOCKKEY_DEFAULT 0x00008195UL /**< Mode DEFAULT for HFRCO_LOCK */ +#define _HFRCO_LOCK_LOCKKEY_UNLOCK 0x00008195UL /**< Mode UNLOCK for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_DEFAULT (_HFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFRCO_LOCK */ +#define HFRCO_LOCK_LOCKKEY_UNLOCK (_HFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFRCO_LOCK */ + +/** @} End of group EFR32BG22_HFRCO_BitFields */ +/** @} End of group EFR32BG22_HFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_HFRCO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h index 140d70d..b994a34 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_hfxo.h @@ -1,463 +1,463 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 HFXO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_HFXO_H -#define EFR32BG22_HFXO_H -#define HFXO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_HFXO HFXO - * @{ - * @brief EFR32BG22 HFXO Register Declaration. - *****************************************************************************/ - -/** HFXO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Control Register */ - uint32_t RESERVED4[9U]; /**< Reserved for future use */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED6[5U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED8[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED9[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ - uint32_t RESERVED11[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - uint32_t RESERVED13[9U]; /**< Reserved for future use */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED15[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED16[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED17[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - uint32_t RESERVED22[9U]; /**< Reserved for future use */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED24[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED26[991U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED27[3U]; /**< Reserved for future use */ - __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - uint32_t RESERVED31[9U]; /**< Reserved for future use */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED33[5U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED34[2U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ -} HFXO_TypeDef; -/** @} End of group EFR32BG22_HFXO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_HFXO - * @{ - * @defgroup EFR32BG22_HFXO_BitFields HFXO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for HFXO IPVERSION */ -#define _HFXO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ -#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFXO_IPVERSION */ -#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ - -/* Bit fields for HFXO XTALCFG */ -#define _HFXO_XTALCFG_RESETVALUE 0x044334CBUL /**< Default value for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ -#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ -#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000013UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ -#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ -#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000000UL /**< Mode T16US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000001UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000002UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000003UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000004UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000005UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000006UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000007UL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000008UL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x00000009UL /**< Mode T500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000AUL /**< Mode T666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000BUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000CUL /**< Mode T1666US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000DUL /**< Mode T2500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000EUL /**< Mode T4166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US 0x0000000FUL /**< Mode T7500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTSTEADY_T7500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US << 20) /**< Shifted mode T7500US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ -#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ -#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ - -/* Bit fields for HFXO XTALCTRL */ -#define _HFXO_XTALCTRL_RESETVALUE 0x0F8C8C10UL /**< Default value for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ -#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x00000010UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ -#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ -#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ -#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ -#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ -#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ -#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ - -/* Bit fields for HFXO CFG */ -#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ -#define _HFXO_CFG_MASK 0xF000000DUL /**< Mask for HFXO_CFG */ -#define HFXO_CFG_MODE (0x1UL << 0) /**< Crystal Oscillator Mode */ -#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ -#define _HFXO_CFG_MODE_MASK 0x1UL /**< Bit mask for HFXO_MODE */ -#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ -#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ -#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ -#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ -#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ -#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ -#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ -#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ -#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ - -/* Bit fields for HFXO CTRL */ -#define _HFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for HFXO_CTRL */ -#define _HFXO_CTRL_MASK 0x80000037UL /**< Mask for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _HFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFXO_FORCEEN */ -#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand Mode */ -#define _HFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFXO_DISONDEMAND */ -#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ -#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ -#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ -#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ -#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ -#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ -#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ - -/* Bit fields for HFXO CMD */ -#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ -#define _HFXO_CMD_MASK 0x00000003UL /**< Mask for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ -#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ -#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_MANUALOVERRIDE (0x1UL << 1) /**< Manual Override */ -#define _HFXO_CMD_MANUALOVERRIDE_SHIFT 1 /**< Shift value for HFXO_MANUALOVERRIDE */ -#define _HFXO_CMD_MANUALOVERRIDE_MASK 0x2UL /**< Bit mask for HFXO_MANUALOVERRIDE */ -#define _HFXO_CMD_MANUALOVERRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ -#define HFXO_CMD_MANUALOVERRIDE_DEFAULT (_HFXO_CMD_MANUALOVERRIDE_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CMD */ - -/* Bit fields for HFXO STATUS */ -#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ -#define _HFXO_STATUS_MASK 0xC00F0003UL /**< Mask for HFXO_STATUS */ -#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ -#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ -#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ -#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Hardware */ -#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ -#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ -#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ -#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_FSMLOCK (0x1UL << 30) /**< FSM Lock Status */ -#define _HFXO_STATUS_FSMLOCK_SHIFT 30 /**< Shift value for HFXO_FSMLOCK */ -#define _HFXO_STATUS_FSMLOCK_MASK 0x40000000UL /**< Bit mask for HFXO_FSMLOCK */ -#define _HFXO_STATUS_FSMLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define _HFXO_STATUS_FSMLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ -#define _HFXO_STATUS_FSMLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_FSMLOCK_DEFAULT (_HFXO_STATUS_FSMLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_FSMLOCK_UNLOCKED (_HFXO_STATUS_FSMLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for HFXO_STATUS */ -#define HFXO_STATUS_FSMLOCK_LOCKED (_HFXO_STATUS_FSMLOCK_LOCKED << 30) /**< Shifted mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ -#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ -#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ -#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ -#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ - -/* Bit fields for HFXO IF */ -#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ -#define _HFXO_IF_MASK 0xE0000003UL /**< Mask for HFXO_IF */ -#define HFXO_IF_RDY (0x1UL << 0) /**< Ready Interrupt */ -#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ -#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ - -/* Bit fields for HFXO IEN */ -#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ -#define _HFXO_IEN_MASK 0xE0000003UL /**< Mask for HFXO_IEN */ -#define HFXO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt */ -#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ -#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ -#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ -#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ -#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ -#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ -#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ -#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ -#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ -#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ - -/* Bit fields for HFXO LOCK */ -#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ -#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ -#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ -#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ -#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ - -/** @} End of group EFR32BG22_HFXO_BitFields */ -/** @} End of group EFR32BG22_HFXO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_HFXO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 HFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_HFXO_H +#define EFR32BG22_HFXO_H +#define HFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_HFXO HFXO + * @{ + * @brief EFR32BG22 HFXO Register Declaration. + *****************************************************************************/ + +/** HFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG; /**< Crystal Configuration Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL; /**< Crystal Control Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Control Register */ + uint32_t RESERVED4[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED6[5U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED8[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED9[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_SET; /**< Crystal Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_SET; /**< Crystal Control Register */ + uint32_t RESERVED11[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + uint32_t RESERVED13[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED15[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED16[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED17[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_CLR; /**< Crystal Configuration Register */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_CLR; /**< Crystal Control Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + uint32_t RESERVED22[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED24[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED26[991U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED27[3U]; /**< Reserved for future use */ + __IOM uint32_t XTALCFG_TGL; /**< Crystal Configuration Register */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t XTALCTRL_TGL; /**< Crystal Control Register */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + uint32_t RESERVED31[9U]; /**< Reserved for future use */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED33[5U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED34[2U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} HFXO_TypeDef; +/** @} End of group EFR32BG22_HFXO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_HFXO + * @{ + * @defgroup EFR32BG22_HFXO_BitFields HFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for HFXO IPVERSION */ +#define _HFXO_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for HFXO_IPVERSION */ +#define _HFXO_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for HFXO_IPVERSION */ +#define HFXO_IPVERSION_IPVERSION_DEFAULT (_HFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IPVERSION */ + +/* Bit fields for HFXO XTALCFG */ +#define _HFXO_XTALCFG_RESETVALUE 0x044334CBUL /**< Default value for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_MASK 0x0FFFFFFFUL /**< Mask for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT 0 /**< Shift value for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_MASK 0x3FUL /**< Bit mask for HFXO_COREBIASSTARTUPI */ +#define _HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT 0x0000000BUL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUPI_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT 6 /**< Shift value for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_MASK 0xFC0UL /**< Bit mask for HFXO_COREBIASSTARTUP */ +#define _HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT 0x00000013UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT (_HFXO_XTALCFG_COREBIASSTARTUP_DEFAULT << 6) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT 12 /**< Shift value for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_MASK 0xF000UL /**< Bit mask for HFXO_CTUNEXISTARTUP */ +#define _HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXISTARTUP_DEFAULT << 12) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT 16 /**< Shift value for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_MASK 0xF0000UL /**< Bit mask for HFXO_CTUNEXOSTARTUP */ +#define _HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT (_HFXO_XTALCFG_CTUNEXOSTARTUP_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT 20 /**< Shift value for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_MASK 0xF00000UL /**< Bit mask for HFXO_TIMEOUTSTEADY */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T16US 0x00000000UL /**< Mode T16US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T41US 0x00000001UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T83US 0x00000002UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T125US 0x00000003UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T166US 0x00000004UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T208US 0x00000005UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T250US 0x00000006UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T333US 0x00000007UL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T416US 0x00000008UL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T500US 0x00000009UL /**< Mode T500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T666US 0x0000000AUL /**< Mode T666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T833US 0x0000000BUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US 0x0000000CUL /**< Mode T1666US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US 0x0000000DUL /**< Mode T2500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US 0x0000000EUL /**< Mode T4166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US 0x0000000FUL /**< Mode T7500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT (_HFXO_XTALCFG_TIMEOUTSTEADY_DEFAULT << 20) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T16US (_HFXO_XTALCFG_TIMEOUTSTEADY_T16US << 20) /**< Shifted mode T16US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T41US (_HFXO_XTALCFG_TIMEOUTSTEADY_T41US << 20) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T83US (_HFXO_XTALCFG_TIMEOUTSTEADY_T83US << 20) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T125US (_HFXO_XTALCFG_TIMEOUTSTEADY_T125US << 20) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T166US << 20) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T208US (_HFXO_XTALCFG_TIMEOUTSTEADY_T208US << 20) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T250US (_HFXO_XTALCFG_TIMEOUTSTEADY_T250US << 20) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T333US (_HFXO_XTALCFG_TIMEOUTSTEADY_T333US << 20) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T416US (_HFXO_XTALCFG_TIMEOUTSTEADY_T416US << 20) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T500US << 20) /**< Shifted mode T500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T666US << 20) /**< Shifted mode T666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T833US (_HFXO_XTALCFG_TIMEOUTSTEADY_T833US << 20) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T1666US (_HFXO_XTALCFG_TIMEOUTSTEADY_T1666US << 20) /**< Shifted mode T1666US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T2500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T2500US << 20) /**< Shifted mode T2500US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T4166US (_HFXO_XTALCFG_TIMEOUTSTEADY_T4166US << 20) /**< Shifted mode T4166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTSTEADY_T7500US (_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US << 20) /**< Shifted mode T7500US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT 24 /**< Shift value for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_MASK 0xF000000UL /**< Bit mask for HFXO_TIMEOUTCBLSB */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT 0x00000004UL /**< Mode DEFAULT for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T8US 0x00000000UL /**< Mode T8US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T20US 0x00000001UL /**< Mode T20US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T41US 0x00000002UL /**< Mode T41US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T62US 0x00000003UL /**< Mode T62US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T83US 0x00000004UL /**< Mode T83US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T104US 0x00000005UL /**< Mode T104US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T125US 0x00000006UL /**< Mode T125US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T166US 0x00000007UL /**< Mode T166US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T208US 0x00000008UL /**< Mode T208US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T250US 0x00000009UL /**< Mode T250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T333US 0x0000000AUL /**< Mode T333US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T416US 0x0000000BUL /**< Mode T416US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T833US 0x0000000CUL /**< Mode T833US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US 0x0000000DUL /**< Mode T1250US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US 0x0000000EUL /**< Mode T2083US for HFXO_XTALCFG */ +#define _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US 0x0000000FUL /**< Mode T3750US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT (_HFXO_XTALCFG_TIMEOUTCBLSB_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T8US (_HFXO_XTALCFG_TIMEOUTCBLSB_T8US << 24) /**< Shifted mode T8US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T20US (_HFXO_XTALCFG_TIMEOUTCBLSB_T20US << 24) /**< Shifted mode T20US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T41US (_HFXO_XTALCFG_TIMEOUTCBLSB_T41US << 24) /**< Shifted mode T41US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T62US (_HFXO_XTALCFG_TIMEOUTCBLSB_T62US << 24) /**< Shifted mode T62US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T83US (_HFXO_XTALCFG_TIMEOUTCBLSB_T83US << 24) /**< Shifted mode T83US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T104US (_HFXO_XTALCFG_TIMEOUTCBLSB_T104US << 24) /**< Shifted mode T104US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T125US (_HFXO_XTALCFG_TIMEOUTCBLSB_T125US << 24) /**< Shifted mode T125US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T166US (_HFXO_XTALCFG_TIMEOUTCBLSB_T166US << 24) /**< Shifted mode T166US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T208US (_HFXO_XTALCFG_TIMEOUTCBLSB_T208US << 24) /**< Shifted mode T208US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T250US << 24) /**< Shifted mode T250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T333US (_HFXO_XTALCFG_TIMEOUTCBLSB_T333US << 24) /**< Shifted mode T333US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T416US (_HFXO_XTALCFG_TIMEOUTCBLSB_T416US << 24) /**< Shifted mode T416US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T833US (_HFXO_XTALCFG_TIMEOUTCBLSB_T833US << 24) /**< Shifted mode T833US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T1250US (_HFXO_XTALCFG_TIMEOUTCBLSB_T1250US << 24) /**< Shifted mode T1250US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T2083US (_HFXO_XTALCFG_TIMEOUTCBLSB_T2083US << 24) /**< Shifted mode T2083US for HFXO_XTALCFG */ +#define HFXO_XTALCFG_TIMEOUTCBLSB_T3750US (_HFXO_XTALCFG_TIMEOUTCBLSB_T3750US << 24) /**< Shifted mode T3750US for HFXO_XTALCFG */ + +/* Bit fields for HFXO XTALCTRL */ +#define _HFXO_XTALCTRL_RESETVALUE 0x0F8C8C10UL /**< Default value for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_MASK 0x8FFFFFFFUL /**< Mask for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREBIASANA_SHIFT 0 /**< Shift value for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_MASK 0xFFUL /**< Bit mask for HFXO_COREBIASANA */ +#define _HFXO_XTALCTRL_COREBIASANA_DEFAULT 0x00000010UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREBIASANA_DEFAULT (_HFXO_XTALCTRL_COREBIASANA_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXIANA_SHIFT 8 /**< Shift value for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_MASK 0xFF00UL /**< Bit mask for HFXO_CTUNEXIANA */ +#define _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXIANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT << 8) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEXOANA_SHIFT 16 /**< Shift value for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_MASK 0xFF0000UL /**< Bit mask for HFXO_CTUNEXOANA */ +#define _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT 0x0000008CUL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEXOANA_DEFAULT (_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT 24 /**< Shift value for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_MASK 0x3000000UL /**< Bit mask for HFXO_CTUNEFIXANA */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XI 0x00000001UL /**< Mode XI for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_XO 0x00000002UL /**< Mode XO for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_CTUNEFIXANA_BOTH 0x00000003UL /**< Mode BOTH for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT (_HFXO_XTALCTRL_CTUNEFIXANA_DEFAULT << 24) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_NONE (_HFXO_XTALCTRL_CTUNEFIXANA_NONE << 24) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XI (_HFXO_XTALCTRL_CTUNEFIXANA_XI << 24) /**< Shifted mode XI for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_XO (_HFXO_XTALCTRL_CTUNEFIXANA_XO << 24) /**< Shifted mode XO for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_CTUNEFIXANA_BOTH (_HFXO_XTALCTRL_CTUNEFIXANA_BOTH << 24) /**< Shifted mode BOTH for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_SHIFT 26 /**< Shift value for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_MASK 0xC000000UL /**< Bit mask for HFXO_COREDGENANA */ +#define _HFXO_XTALCTRL_COREDGENANA_DEFAULT 0x00000003UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_NONE 0x00000000UL /**< Mode NONE for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN33 0x00000001UL /**< Mode DGEN33 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN50 0x00000002UL /**< Mode DGEN50 for HFXO_XTALCTRL */ +#define _HFXO_XTALCTRL_COREDGENANA_DGEN100 0x00000003UL /**< Mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DEFAULT (_HFXO_XTALCTRL_COREDGENANA_DEFAULT << 26) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_NONE (_HFXO_XTALCTRL_COREDGENANA_NONE << 26) /**< Shifted mode NONE for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN33 (_HFXO_XTALCTRL_COREDGENANA_DGEN33 << 26) /**< Shifted mode DGEN33 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN50 (_HFXO_XTALCTRL_COREDGENANA_DGEN50 << 26) /**< Shifted mode DGEN50 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_COREDGENANA_DGEN100 (_HFXO_XTALCTRL_COREDGENANA_DGEN100 << 26) /**< Shifted mode DGEN100 for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT (0x1UL << 31) /**< Skip Core Bias Optimization */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_SHIFT 31 /**< Shift value for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK 0x80000000UL /**< Bit mask for HFXO_SKIPCOREBIASOPT */ +#define _HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_XTALCTRL */ +#define HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT (_HFXO_XTALCTRL_SKIPCOREBIASOPT_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_XTALCTRL */ + +/* Bit fields for HFXO CFG */ +#define _HFXO_CFG_RESETVALUE 0x10000000UL /**< Default value for HFXO_CFG */ +#define _HFXO_CFG_MASK 0xF000000DUL /**< Mask for HFXO_CFG */ +#define HFXO_CFG_MODE (0x1UL << 0) /**< Crystal Oscillator Mode */ +#define _HFXO_CFG_MODE_SHIFT 0 /**< Shift value for HFXO_MODE */ +#define _HFXO_CFG_MODE_MASK 0x1UL /**< Bit mask for HFXO_MODE */ +#define _HFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for HFXO_CFG */ +#define _HFXO_CFG_MODE_EXTCLK 0x00000001UL /**< Mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_MODE_DEFAULT (_HFXO_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_MODE_XTAL (_HFXO_CFG_MODE_XTAL << 0) /**< Shifted mode XTAL for HFXO_CFG */ +#define HFXO_CFG_MODE_EXTCLK (_HFXO_CFG_MODE_EXTCLK << 0) /**< Shifted mode EXTCLK for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA (0x1UL << 2) /**< Enable XI Internal DC Bias */ +#define _HFXO_CFG_ENXIDCBIASANA_SHIFT 2 /**< Shift value for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_MASK 0x4UL /**< Bit mask for HFXO_ENXIDCBIASANA */ +#define _HFXO_CFG_ENXIDCBIASANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_ENXIDCBIASANA_DEFAULT (_HFXO_CFG_ENXIDCBIASANA_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA (0x1UL << 3) /**< Squaring Buffer Schmitt Trigger */ +#define _HFXO_CFG_SQBUFSCHTRGANA_SHIFT 3 /**< Shift value for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_MASK 0x8UL /**< Bit mask for HFXO_SQBUFSCHTRGANA */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CFG */ +#define _HFXO_CFG_SQBUFSCHTRGANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DEFAULT (_HFXO_CFG_SQBUFSCHTRGANA_DEFAULT << 3) /**< Shifted mode DEFAULT for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_DISABLE (_HFXO_CFG_SQBUFSCHTRGANA_DISABLE << 3) /**< Shifted mode DISABLE for HFXO_CFG */ +#define HFXO_CFG_SQBUFSCHTRGANA_ENABLE (_HFXO_CFG_SQBUFSCHTRGANA_ENABLE << 3) /**< Shifted mode ENABLE for HFXO_CFG */ + +/* Bit fields for HFXO CTRL */ +#define _HFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for HFXO_CTRL */ +#define _HFXO_CTRL_MASK 0x80000037UL /**< Mask for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _HFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for HFXO_FORCEEN */ +#define _HFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEEN_DEFAULT (_HFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-demand Mode */ +#define _HFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for HFXO_DISONDEMAND */ +#define _HFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_DISONDEMAND_DEFAULT (_HFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM (0x1UL << 2) /**< Keep Warm */ +#define _HFXO_CTRL_KEEPWARM_SHIFT 2 /**< Shift value for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_MASK 0x4UL /**< Bit mask for HFXO_KEEPWARM */ +#define _HFXO_CTRL_KEEPWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_KEEPWARM_DEFAULT (_HFXO_CTRL_KEEPWARM_DEFAULT << 2) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA (0x1UL << 4) /**< Force XI Pin to Ground */ +#define _HFXO_CTRL_FORCEXI2GNDANA_SHIFT 4 /**< Shift value for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_MASK 0x10UL /**< Bit mask for HFXO_FORCEXI2GNDANA */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXI2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXI2GNDANA_DEFAULT << 4) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_DISABLE (_HFXO_CTRL_FORCEXI2GNDANA_DISABLE << 4) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXI2GNDANA_ENABLE (_HFXO_CTRL_FORCEXI2GNDANA_ENABLE << 4) /**< Shifted mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA (0x1UL << 5) /**< Force XO Pin to Ground */ +#define _HFXO_CTRL_FORCEXO2GNDANA_SHIFT 5 /**< Shift value for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_MASK 0x20UL /**< Bit mask for HFXO_FORCEXO2GNDANA */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_DISABLE 0x00000000UL /**< Mode DISABLE for HFXO_CTRL */ +#define _HFXO_CTRL_FORCEXO2GNDANA_ENABLE 0x00000001UL /**< Mode ENABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DEFAULT (_HFXO_CTRL_FORCEXO2GNDANA_DEFAULT << 5) /**< Shifted mode DEFAULT for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_DISABLE (_HFXO_CTRL_FORCEXO2GNDANA_DISABLE << 5) /**< Shifted mode DISABLE for HFXO_CTRL */ +#define HFXO_CTRL_FORCEXO2GNDANA_ENABLE (_HFXO_CTRL_FORCEXO2GNDANA_ENABLE << 5) /**< Shifted mode ENABLE for HFXO_CTRL */ + +/* Bit fields for HFXO CMD */ +#define _HFXO_CMD_RESETVALUE 0x00000000UL /**< Default value for HFXO_CMD */ +#define _HFXO_CMD_MASK 0x00000003UL /**< Mask for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT (0x1UL << 0) /**< Core Bias Optimizaton */ +#define _HFXO_CMD_COREBIASOPT_SHIFT 0 /**< Shift value for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_MASK 0x1UL /**< Bit mask for HFXO_COREBIASOPT */ +#define _HFXO_CMD_COREBIASOPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_COREBIASOPT_DEFAULT (_HFXO_CMD_COREBIASOPT_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE (0x1UL << 1) /**< Manual Override */ +#define _HFXO_CMD_MANUALOVERRIDE_SHIFT 1 /**< Shift value for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_MASK 0x2UL /**< Bit mask for HFXO_MANUALOVERRIDE */ +#define _HFXO_CMD_MANUALOVERRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_CMD */ +#define HFXO_CMD_MANUALOVERRIDE_DEFAULT (_HFXO_CMD_MANUALOVERRIDE_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_CMD */ + +/* Bit fields for HFXO STATUS */ +#define _HFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for HFXO_STATUS */ +#define _HFXO_STATUS_MASK 0xC00F0003UL /**< Mask for HFXO_STATUS */ +#define HFXO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _HFXO_STATUS_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_RDY_DEFAULT (_HFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready */ +#define _HFXO_STATUS_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_STATUS_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_COREBIASOPTRDY_DEFAULT (_HFXO_STATUS_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _HFXO_STATUS_ENS_SHIFT 16 /**< Shift value for HFXO_ENS */ +#define _HFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for HFXO_ENS */ +#define _HFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ENS_DEFAULT (_HFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ (0x1UL << 17) /**< Oscillator Requested by Hardware */ +#define _HFXO_STATUS_HWREQ_SHIFT 17 /**< Shift value for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_MASK 0x20000UL /**< Bit mask for HFXO_HWREQ */ +#define _HFXO_STATUS_HWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_HWREQ_DEFAULT (_HFXO_STATUS_HWREQ_DEFAULT << 17) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM (0x1UL << 19) /**< Oscillator Is Kept Warm */ +#define _HFXO_STATUS_ISWARM_SHIFT 19 /**< Shift value for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_MASK 0x80000UL /**< Bit mask for HFXO_ISWARM */ +#define _HFXO_STATUS_ISWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_ISWARM_DEFAULT (_HFXO_STATUS_ISWARM_DEFAULT << 19) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK (0x1UL << 30) /**< FSM Lock Status */ +#define _HFXO_STATUS_FSMLOCK_SHIFT 30 /**< Shift value for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_MASK 0x40000000UL /**< Bit mask for HFXO_FSMLOCK */ +#define _HFXO_STATUS_FSMLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_FSMLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_DEFAULT (_HFXO_STATUS_FSMLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_UNLOCKED (_HFXO_STATUS_FSMLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_FSMLOCK_LOCKED (_HFXO_STATUS_FSMLOCK_LOCKED << 30) /**< Shifted mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ +#define _HFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for HFXO_LOCK */ +#define _HFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for HFXO_STATUS */ +#define _HFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_DEFAULT (_HFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_UNLOCKED (_HFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for HFXO_STATUS */ +#define HFXO_STATUS_LOCK_LOCKED (_HFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for HFXO_STATUS */ + +/* Bit fields for HFXO IF */ +#define _HFXO_IF_RESETVALUE 0x00000000UL /**< Default value for HFXO_IF */ +#define _HFXO_IF_MASK 0xE0000003UL /**< Mask for HFXO_IF */ +#define HFXO_IF_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IF_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IF_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_RDY_DEFAULT (_HFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IF_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IF_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTRDY_DEFAULT (_HFXO_IF_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IF_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IF_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_DNSERR_DEFAULT (_HFXO_IF_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IF_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IF_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IF */ +#define HFXO_IF_COREBIASOPTERR_DEFAULT (_HFXO_IF_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IF */ + +/* Bit fields for HFXO IEN */ +#define _HFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for HFXO_IEN */ +#define _HFXO_IEN_MASK 0xE0000003UL /**< Mask for HFXO_IEN */ +#define HFXO_IEN_RDY (0x1UL << 0) /**< Ready Interrupt */ +#define _HFXO_IEN_RDY_SHIFT 0 /**< Shift value for HFXO_RDY */ +#define _HFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for HFXO_RDY */ +#define _HFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_RDY_DEFAULT (_HFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY (0x1UL << 1) /**< Core Bias Optimization Ready Interrupt */ +#define _HFXO_IEN_COREBIASOPTRDY_SHIFT 1 /**< Shift value for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_MASK 0x2UL /**< Bit mask for HFXO_COREBIASOPTRDY */ +#define _HFXO_IEN_COREBIASOPTRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTRDY_DEFAULT (_HFXO_IEN_COREBIASOPTRDY_DEFAULT << 1) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR (0x1UL << 29) /**< Did Not Start Error Interrupt */ +#define _HFXO_IEN_DNSERR_SHIFT 29 /**< Shift value for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_MASK 0x20000000UL /**< Bit mask for HFXO_DNSERR */ +#define _HFXO_IEN_DNSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_DNSERR_DEFAULT (_HFXO_IEN_DNSERR_DEFAULT << 29) /**< Shifted mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR (0x1UL << 31) /**< Core Bias Optimization Error Interrupt */ +#define _HFXO_IEN_COREBIASOPTERR_SHIFT 31 /**< Shift value for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_MASK 0x80000000UL /**< Bit mask for HFXO_COREBIASOPTERR */ +#define _HFXO_IEN_COREBIASOPTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for HFXO_IEN */ +#define HFXO_IEN_COREBIASOPTERR_DEFAULT (_HFXO_IEN_COREBIASOPTERR_DEFAULT << 31) /**< Shifted mode DEFAULT for HFXO_IEN */ + +/* Bit fields for HFXO LOCK */ +#define _HFXO_LOCK_RESETVALUE 0x0000580EUL /**< Default value for HFXO_LOCK */ +#define _HFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for HFXO_LOCKKEY */ +#define _HFXO_LOCK_LOCKKEY_DEFAULT 0x0000580EUL /**< Mode DEFAULT for HFXO_LOCK */ +#define _HFXO_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_DEFAULT (_HFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for HFXO_LOCK */ +#define HFXO_LOCK_LOCKKEY_UNLOCK (_HFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for HFXO_LOCK */ + +/** @} End of group EFR32BG22_HFXO_BitFields */ +/** @} End of group EFR32BG22_HFXO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_HFXO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h index 7ce18e7..61ec5e1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_i2c.h @@ -1,744 +1,744 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 I2C register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_I2C_H -#define EFR32BG22_I2C_H -#define I2C_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_I2C I2C - * @{ - * @brief EFR32BG22 I2C Register Declaration. - *****************************************************************************/ - -/** I2C Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP VERSION Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATE; /**< State Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Division Register */ - __IOM uint32_t SADDR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED0[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATE_SET; /**< State Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ - __IOM uint32_t SADDR_SET; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATE_CLR; /**< State Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ - __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1007U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATE_TGL; /**< State Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ - __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ - __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ - __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ - __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ - __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ - __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ - __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ -} I2C_TypeDef; -/** @} End of group EFR32BG22_I2C */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_I2C - * @{ - * @defgroup EFR32BG22_I2C_BitFields I2C Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for I2C IPVERSION */ -#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ -#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ -#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ -#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ - -/* Bit fields for I2C EN */ -#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ -#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ -#define I2C_EN_EN (0x1UL << 0) /**< module enable */ -#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ -#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ -#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ -#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ -#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ -#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ -#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ -#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ - -/* Bit fields for I2C CTRL */ -#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ -#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ -#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ -#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ -#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ -#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ -#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ -#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ -#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ -#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ -#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ -#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ -#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ -#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ -#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ -#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ -#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ -#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ -#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ -#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ -#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ -#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ -#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ -#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ -#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ -#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ -#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ -#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ -#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ -#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ -#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ -#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ -#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ -#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ -#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ -#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ -#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ -#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ -#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ -#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ -#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ -#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ -#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ -#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ -#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ -#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ - -/* Bit fields for I2C CMD */ -#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ -#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ -#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ -#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ -#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ -#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ -#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ -#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ -#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ -#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ -#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ -#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ -#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ -#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ -#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ -#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ -#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ -#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ -#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ -#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ -#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ -#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ -#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ -#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ - -/* Bit fields for I2C STATE */ -#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ -#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ -#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ -#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ -#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ -#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ -#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ -#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ -#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ -#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ -#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ -#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ -#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ -#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ -#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ -#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ -#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ -#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ -#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ -#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ -#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ -#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ -#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ -#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ -#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ -#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ -#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ -#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ -#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ -#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ -#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ -#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ - -/* Bit fields for I2C STATUS */ -#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ -#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ -#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ -#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ -#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ -#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ -#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ -#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ -#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ -#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ -#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ -#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ -#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ -#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ -#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ -#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ -#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ -#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ -#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ -#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ -#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ -#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ -#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ -#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ -#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ -#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ -#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ -#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ -#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ -#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ -#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ - -/* Bit fields for I2C CLKDIV */ -#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ -#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ -#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ -#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ -#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ - -/* Bit fields for I2C SADDR */ -#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ -#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ -#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ -#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ -#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ -#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ - -/* Bit fields for I2C SADDRMASK */ -#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ -#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ -#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ - -/* Bit fields for I2C RXDATA */ -#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ -#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ -#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ -#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ - -/* Bit fields for I2C RXDOUBLE */ -#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ -#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ -#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ -#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ -#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ - -/* Bit fields for I2C RXDATAP */ -#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ -#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ -#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ -#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ - -/* Bit fields for I2C RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ -#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ -#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ -#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ -#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ - -/* Bit fields for I2C TXDATA */ -#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ -#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ -#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ -#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ - -/* Bit fields for I2C TXDOUBLE */ -#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ -#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ -#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ -#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ -#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ - -/* Bit fields for I2C IF */ -#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ -#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ -#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ -#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ - -/* Bit fields for I2C IEN */ -#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ -#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ -#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ -#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ -#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ -#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ -#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ -#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ -#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ -#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ -#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ -#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ -#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ -#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ -#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ -#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ -#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ -#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ -#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ -#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ -#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ -#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ -#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ -#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ -#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ -#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ -#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ -#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ -#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ -#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ -#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ -#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ -#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ -#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ -#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ -#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ -#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ -#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ -#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ -#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ -#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ -#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ -#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ -#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ -#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ -#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ -#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ -#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ -#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ -#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ -#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ -#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ -#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ -#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ -#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ -#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ -#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ - -/** @} End of group EFR32BG22_I2C_BitFields */ -/** @} End of group EFR32BG22_I2C */ -/** @} End of group Parts */ - -#endif // EFR32BG22_I2C_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 I2C register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_I2C_H +#define EFR32BG22_I2C_H +#define I2C_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_I2C I2C + * @{ + * @brief EFR32BG22 I2C Register Declaration. + *****************************************************************************/ + +/** I2C Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATE; /**< State Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Division Register */ + __IOM uint32_t SADDR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED0[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATE_SET; /**< State Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Division Register */ + __IOM uint32_t SADDR_SET; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_SET; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_SET; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_SET; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_SET; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_SET; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_SET; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_SET; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATE_CLR; /**< State Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Division Register */ + __IOM uint32_t SADDR_CLR; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_CLR; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_CLR; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_CLR; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_CLR; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_CLR; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_CLR; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1007U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATE_TGL; /**< State Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Division Register */ + __IOM uint32_t SADDR_TGL; /**< Follower Address Register */ + __IOM uint32_t SADDRMASK_TGL; /**< Follower Address Mask Register */ + __IM uint32_t RXDATA_TGL; /**< Receive Buffer Data Register */ + __IM uint32_t RXDOUBLE_TGL; /**< Receive Buffer Double Data Register */ + __IM uint32_t RXDATAP_TGL; /**< Receive Buffer Data Peek Register */ + __IM uint32_t RXDOUBLEP_TGL; /**< Receive Buffer Double Data Peek Register */ + __IOM uint32_t TXDATA_TGL; /**< Transmit Buffer Data Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< Transmit Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} I2C_TypeDef; +/** @} End of group EFR32BG22_I2C */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_I2C + * @{ + * @defgroup EFR32BG22_I2C_BitFields I2C Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for I2C IPVERSION */ +#define _I2C_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for I2C_IPVERSION */ +#define _I2C_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for I2C_IPVERSION */ +#define _I2C_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IPVERSION */ +#define I2C_IPVERSION_IPVERSION_DEFAULT (_I2C_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IPVERSION */ + +/* Bit fields for I2C EN */ +#define _I2C_EN_RESETVALUE 0x00000000UL /**< Default value for I2C_EN */ +#define _I2C_EN_MASK 0x00000001UL /**< Mask for I2C_EN */ +#define I2C_EN_EN (0x1UL << 0) /**< module enable */ +#define _I2C_EN_EN_SHIFT 0 /**< Shift value for I2C_EN */ +#define _I2C_EN_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ +#define _I2C_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_EN */ +#define _I2C_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_EN */ +#define _I2C_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_EN */ +#define I2C_EN_EN_DEFAULT (_I2C_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_EN */ +#define I2C_EN_EN_DISABLE (_I2C_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for I2C_EN */ +#define I2C_EN_EN_ENABLE (_I2C_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for I2C_EN */ + +/* Bit fields for I2C CTRL */ +#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ +#define _I2C_CTRL_MASK 0x0037B3FFUL /**< Mask for I2C_CTRL */ +#define I2C_CTRL_CORERST (0x1UL << 0) /**< Soft Reset the internal state registers */ +#define _I2C_CTRL_CORERST_SHIFT 0 /**< Shift value for I2C_CORERST */ +#define _I2C_CTRL_CORERST_MASK 0x1UL /**< Bit mask for I2C_CORERST */ +#define _I2C_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CORERST_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_CORERST_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_DEFAULT (_I2C_CTRL_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CORERST_DISABLE (_I2C_CTRL_CORERST_DISABLE << 0) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_CORERST_ENABLE (_I2C_CTRL_CORERST_ENABLE << 0) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Follower */ +#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ +#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SLAVE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SLAVE_DISABLE (_I2C_CTRL_SLAVE_DISABLE << 1) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SLAVE_ENABLE (_I2C_CTRL_SLAVE_ENABLE << 1) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ +#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ +#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOACK_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_DISABLE (_I2C_CTRL_AUTOACK_DISABLE << 2) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOACK_ENABLE (_I2C_CTRL_AUTOACK_ENABLE << 2) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ +#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ +#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSE_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_DISABLE (_I2C_CTRL_AUTOSE_DISABLE << 3) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSE_ENABLE (_I2C_CTRL_AUTOSE_ENABLE << 3) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ +#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ +#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_AUTOSN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_DISABLE (_I2C_CTRL_AUTOSN_DISABLE << 4) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_AUTOSN_ENABLE (_I2C_CTRL_AUTOSN_ENABLE << 4) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ +#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ +#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_ARBDIS_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_DISABLE (_I2C_CTRL_ARBDIS_DISABLE << 5) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_ARBDIS_ENABLE (_I2C_CTRL_ARBDIS_ENABLE << 5) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ +#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ +#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GCAMEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_DISABLE (_I2C_CTRL_GCAMEN_DISABLE << 6) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GCAMEN_ENABLE (_I2C_CTRL_GCAMEN_ENABLE << 6) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */ +#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */ +#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */ +#define _I2C_CTRL_TXBIL_HALF_FULL 0x00000001UL /**< Mode HALF_FULL for I2C_CTRL */ +#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */ +#define I2C_CTRL_TXBIL_HALF_FULL (_I2C_CTRL_TXBIL_HALF_FULL << 7) /**< Shifted mode HALF_FULL for I2C_CTRL */ +#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ +#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ +#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ +#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ +#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ +#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ +#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ +#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ +#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ +#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ +#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_BITO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C40PCC (_I2C_CTRL_BITO_I2C40PCC << 12) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C80PCC (_I2C_CTRL_BITO_I2C80PCC << 12) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_BITO_I2C160PCC (_I2C_CTRL_BITO_I2C160PCC << 12) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ +#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ +#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_GIBITO_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_GIBITO_DISABLE (_I2C_CTRL_GIBITO_DISABLE << 15) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_GIBITO_ENABLE (_I2C_CTRL_GIBITO_ENABLE << 15) /**< Shifted mode ENABLE for I2C_CTRL */ +#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ +#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C40PCC 0x00000001UL /**< Mode I2C40PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C80PCC 0x00000002UL /**< Mode I2C80PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C160PCC 0x00000003UL /**< Mode I2C160PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C320PCC 0x00000004UL /**< Mode I2C320PCC for I2C_CTRL */ +#define _I2C_CTRL_CLTO_I2C1024PCC 0x00000005UL /**< Mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C40PCC (_I2C_CTRL_CLTO_I2C40PCC << 16) /**< Shifted mode I2C40PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C80PCC (_I2C_CTRL_CLTO_I2C80PCC << 16) /**< Shifted mode I2C80PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C160PCC (_I2C_CTRL_CLTO_I2C160PCC << 16) /**< Shifted mode I2C160PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C320PCC (_I2C_CTRL_CLTO_I2C320PCC << 16) /**< Shifted mode I2C320PCC for I2C_CTRL */ +#define I2C_CTRL_CLTO_I2C1024PCC (_I2C_CTRL_CLTO_I2C1024PCC << 16) /**< Shifted mode I2C1024PCC for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN (0x1UL << 20) /**< SCL Monitor Enable */ +#define _I2C_CTRL_SCLMONEN_SHIFT 20 /**< Shift value for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_MASK 0x100000UL /**< Bit mask for I2C_SCLMONEN */ +#define _I2C_CTRL_SCLMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SCLMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DEFAULT (_I2C_CTRL_SCLMONEN_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_DISABLE (_I2C_CTRL_SCLMONEN_DISABLE << 20) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SCLMONEN_ENABLE (_I2C_CTRL_SCLMONEN_ENABLE << 20) /**< Shifted mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN (0x1UL << 21) /**< SDA Monitor Enable */ +#define _I2C_CTRL_SDAMONEN_SHIFT 21 /**< Shift value for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_MASK 0x200000UL /**< Bit mask for I2C_SDAMONEN */ +#define _I2C_CTRL_SDAMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_DISABLE 0x00000000UL /**< Mode DISABLE for I2C_CTRL */ +#define _I2C_CTRL_SDAMONEN_ENABLE 0x00000001UL /**< Mode ENABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DEFAULT (_I2C_CTRL_SDAMONEN_DEFAULT << 21) /**< Shifted mode DEFAULT for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_DISABLE (_I2C_CTRL_SDAMONEN_DISABLE << 21) /**< Shifted mode DISABLE for I2C_CTRL */ +#define I2C_CTRL_SDAMONEN_ENABLE (_I2C_CTRL_SDAMONEN_ENABLE << 21) /**< Shifted mode ENABLE for I2C_CTRL */ + +/* Bit fields for I2C CMD */ +#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ +#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ +#define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ +#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ +#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ +#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ +#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ +#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ +#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ +#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ +#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ +#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ +#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ +#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ +#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ +#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ +#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ +#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ +#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ +#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ +#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ +#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ +#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ +#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ + +/* Bit fields for I2C STATE */ +#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ +#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ +#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ +#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ +#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ +#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER (0x1UL << 1) /**< Leader */ +#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ +#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ +#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ +#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ +#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ +#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ +#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ +#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ +#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ +#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ +#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ +#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ +#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ +#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ +#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ +#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ +#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ +#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ +#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ +#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ +#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ +#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ +#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ +#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ +#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ +#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ + +/* Bit fields for I2C STATUS */ +#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ +#define _I2C_STATUS_MASK 0x00000FFFUL /**< Mask for I2C_STATUS */ +#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ +#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ +#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ +#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ +#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ +#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ +#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ +#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ +#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ +#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ +#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ +#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ +#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ +#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ +#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ +#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ +#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ +#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ +#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ +#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ +#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ +#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ +#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ +#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ +#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */ +#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */ +#define _I2C_STATUS_TXBUFCNT_SHIFT 10 /**< Shift value for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_MASK 0xC00UL /**< Bit mask for I2C_TXBUFCNT */ +#define _I2C_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ +#define I2C_STATUS_TXBUFCNT_DEFAULT (_I2C_STATUS_TXBUFCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_STATUS */ + +/* Bit fields for I2C CLKDIV */ +#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ +#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ +#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ +#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ +#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ + +/* Bit fields for I2C SADDR */ +#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ +#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ +#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ +#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ +#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ +#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ + +/* Bit fields for I2C SADDRMASK */ +#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_SHIFT 1 /**< Shift value for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_MASK 0xFEUL /**< Bit mask for I2C_SADDRMASK */ +#define _I2C_SADDRMASK_SADDRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ +#define I2C_SADDRMASK_SADDRMASK_DEFAULT (_I2C_SADDRMASK_SADDRMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ + +/* Bit fields for I2C RXDATA */ +#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ +#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ +#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ +#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ + +/* Bit fields for I2C RXDOUBLE */ +#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */ +#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ +#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */ +#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */ +#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */ + +/* Bit fields for I2C RXDATAP */ +#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ +#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ +#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ +#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ + +/* Bit fields for I2C RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */ +#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ +#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */ +#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */ +#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */ + +/* Bit fields for I2C TXDATA */ +#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ +#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ +#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ +#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ + +/* Bit fields for I2C TXDOUBLE */ +#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */ +#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ +#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */ +#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */ +#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */ + +/* Bit fields for I2C IF */ +#define _I2C_IF_RESETVALUE 0x00000000UL /**< Default value for I2C_IF */ +#define _I2C_IF_MASK 0x001FFFFFUL /**< Mask for I2C_IF */ +#define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IF_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IF_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IF_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SCLERR_DEFAULT (_I2C_IF_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IF_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IF_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IF_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ +#define I2C_IF_SDAERR_DEFAULT (_I2C_IF_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IF */ + +/* Bit fields for I2C IEN */ +#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ +#define _I2C_IEN_MASK 0x001FFFFFUL /**< Mask for I2C_IEN */ +#define I2C_IEN_START (0x1UL << 0) /**< START condition Interrupt Flag */ +#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ +#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ +#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ +#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ +#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ +#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ +#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ +#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ +#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ +#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ +#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ +#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ +#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ +#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ +#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ +#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ +#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ +#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ +#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ +#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ +#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ +#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP (0x1UL << 8) /**< Leader STOP Condition Interrupt Flag */ +#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ +#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ +#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ +#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ +#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ +#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ +#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ +#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ +#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ +#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ +#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ +#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ +#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ +#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ +#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ +#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ +#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ +#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ +#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ +#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP (0x1UL << 16) /**< Follower STOP condition Interrupt Flag */ +#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ +#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */ +#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */ +#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */ +#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */ +#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */ +#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR (0x1UL << 19) /**< SCL Error Interrupt Flag */ +#define _I2C_IEN_SCLERR_SHIFT 19 /**< Shift value for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_MASK 0x80000UL /**< Bit mask for I2C_SCLERR */ +#define _I2C_IEN_SCLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SCLERR_DEFAULT (_I2C_IEN_SCLERR_DEFAULT << 19) /**< Shifted mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR (0x1UL << 20) /**< SDA Error Interrupt Flag */ +#define _I2C_IEN_SDAERR_SHIFT 20 /**< Shift value for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_MASK 0x100000UL /**< Bit mask for I2C_SDAERR */ +#define _I2C_IEN_SDAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ +#define I2C_IEN_SDAERR_DEFAULT (_I2C_IEN_SDAERR_DEFAULT << 20) /**< Shifted mode DEFAULT for I2C_IEN */ + +/** @} End of group EFR32BG22_I2C_BitFields */ +/** @} End of group EFR32BG22_I2C */ +/** @} End of group Parts */ + +#endif // EFR32BG22_I2C_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h index 27ff1b3..96a6363 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_iadc.h @@ -1,1005 +1,1005 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 IADC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_IADC_H -#define EFR32BG22_IADC_H -#define IADC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_IADC IADC - * @{ - * @brief EFR32BG22 IADC Register Declaration. - *****************************************************************************/ - -/** IADC CFG Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG; /**< Configuration */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t SCALE; /**< Scaling */ - __IOM uint32_t SCHED; /**< Scheduling */ -} IADC_CFG_TypeDef; - -/** IADC SCANTABLE Register Group Declaration. */ -typedef struct { - __IOM uint32_t SCAN; /**< SCAN Entry */ -} IADC_SCANTABLE_TypeDef; - -/** IADC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< Enable */ - __IOM uint32_t CTRL; /**< Control */ - __IOM uint32_t CMD; /**< Command */ - __IOM uint32_t TIMER; /**< Timer */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t MASKREQ; /**< Mask Request */ - __IM uint32_t STMASK; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF; /**< Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER; /**< Trigger */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG[2U]; /**< CFG */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA; /**< Single FIFO Read Data */ - __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA; /**< Scan Data */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - uint32_t RESERVED8[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< Enable */ - __IOM uint32_t CTRL_SET; /**< Control */ - __IOM uint32_t CMD_SET; /**< Command */ - __IOM uint32_t TIMER_SET; /**< Timer */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t MASKREQ_SET; /**< Mask Request */ - __IM uint32_t STMASK_SET; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_SET; /**< Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_SET; /**< Trigger */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - uint32_t RESERVED10[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ - uint32_t RESERVED11[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO Read Data */ - __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_SET; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_SET; /**< Scan Data */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ - uint32_t RESERVED15[4U]; /**< Reserved for future use */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - uint32_t RESERVED17[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< Enable */ - __IOM uint32_t CTRL_CLR; /**< Control */ - __IOM uint32_t CMD_CLR; /**< Command */ - __IOM uint32_t TIMER_CLR; /**< Timer */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ - __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_CLR; /**< Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_CLR; /**< Trigger */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - uint32_t RESERVED19[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO Read Data */ - __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_CLR; /**< Scan Data */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ - uint32_t RESERVED23[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ - uint32_t RESERVED24[4U]; /**< Reserved for future use */ - uint32_t RESERVED25[1U]; /**< Reserved for future use */ - uint32_t RESERVED26[963U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< Enable */ - __IOM uint32_t CTRL_TGL; /**< Control */ - __IOM uint32_t CMD_TGL; /**< Command */ - __IOM uint32_t TIMER_TGL; /**< Timer */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ - __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ - __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ - __IOM uint32_t IF_TGL; /**< Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - __IOM uint32_t TRIGGER_TGL; /**< Trigger */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[5U]; /**< Reserved for future use */ - IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ - __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO Read Data */ - __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ - __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ - __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ - __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ - __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ - __IM uint32_t SCANDATA_TGL; /**< Scan Data */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - uint32_t RESERVED31[1U]; /**< Reserved for future use */ - __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - uint32_t RESERVED34[1U]; /**< Reserved for future use */ -} IADC_TypeDef; -/** @} End of group EFR32BG22_IADC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_IADC - * @{ - * @defgroup EFR32BG22_IADC_BitFields IADC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for IADC IPVERSION */ -#define _IADC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for IADC_IPVERSION */ -#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ -#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_IPVERSION */ -#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ - -/* Bit fields for IADC EN */ -#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ -#define _IADC_EN_MASK 0x00000001UL /**< Mask for IADC_EN */ -#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ -#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ -#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ -#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ -#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ -#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ -#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ -#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ -#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ - -/* Bit fields for IADC CTRL */ -#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ -#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ -#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ -#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ -#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ -#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ -#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ -#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ -#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ -#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ -#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ -#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ -#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ -#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ -#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ -#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ -#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ -#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ -#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ -#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ -#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ - -/* Bit fields for IADC CMD */ -#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ -#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ -#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ -#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ -#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ -#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ -#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ -#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ -#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ -#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ -#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ -#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ -#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ -#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ -#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ -#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ -#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ -#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ -#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ -#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ - -/* Bit fields for IADC TIMER */ -#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ -#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ -#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ -#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ -#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ - -/* Bit fields for IADC STATUS */ -#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ -#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ -#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ -#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ -#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ -#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ -#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ -#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ -#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ -#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ -#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ -#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ -#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ -#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ -#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ -#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ -#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ -#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ -#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ -#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ -#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ -#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ -#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ -#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ -#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ -#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ -#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ -#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ - -/* Bit fields for IADC MASKREQ */ -#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ -#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ -#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ - -/* Bit fields for IADC STMASK */ -#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ -#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ -#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ -#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ -#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ - -/* Bit fields for IADC CMPTHR */ -#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ -#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ -#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ -#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ -#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ -#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ - -/* Bit fields for IADC IF */ -#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ -#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ -#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ -#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ -#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ -#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ -#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ -#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ -#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ -#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ -#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ -#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ -#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ -#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ -#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ -#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ -#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ - -/* Bit fields for IADC IEN */ -#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ -#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ -#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ -#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ -#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ -#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ -#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ -#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ -#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ -#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ -#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ -#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ -#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ -#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ -#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ -#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ -#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ -#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ -#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ -#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ -#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ -#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ -#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ -#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ -#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ -#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ -#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ -#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ -#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ -#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ -#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ - -/* Bit fields for IADC TRIGGER */ -#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ -#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ -#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ -#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ -#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ -#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ -#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ -#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ -#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ -#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ -#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ -#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ - -/* Bit fields for IADC CFG */ -#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ -#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ -#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ -#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ -#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ -#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ -#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ -#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ -#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ -#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ -#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ -#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ -#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ -#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ -#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ -#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ -#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ -#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ -#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ -#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ -#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ -#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ -#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ -#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ -#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ -#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ -#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ -#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ - -/* Bit fields for IADC SCALE */ -#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ -#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ -#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ -#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ -#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ -#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ -#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ -#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ -#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ - -/* Bit fields for IADC SCHED */ -#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ -#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ -#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ -#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ -#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ - -/* Bit fields for IADC SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ -#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ -#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ -#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ - -/* Bit fields for IADC SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ -#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ -#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ - -/* Bit fields for IADC SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SINGLEFIFOSTAT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ -#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ - -/* Bit fields for IADC SINGLEDATA */ -#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ -#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ -#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ - -/* Bit fields for IADC SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ -#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ -#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ -#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ -#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ -#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ - -/* Bit fields for IADC SCANFIFODATA */ -#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ -#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ -#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ - -/* Bit fields for IADC SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SCANFIFOSTAT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ -#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ -#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ - -/* Bit fields for IADC SCANDATA */ -#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ -#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ -#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ -#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ -#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ -#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ - -/* Bit fields for IADC SINGLE */ -#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ -#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ -#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ -#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ -#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ -#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ -#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ -#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ -#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ -#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ -#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ - -/* Bit fields for IADC SCAN */ -#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ -#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ -#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ -#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ -#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ -#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ -#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ -#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ -#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ -#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ -#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ -#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ -#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ -#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ -#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ -#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ -#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ -#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ -#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ -#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ -#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ - -/** @} End of group EFR32BG22_IADC_BitFields */ -/** @} End of group EFR32BG22_IADC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_IADC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 IADC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_IADC_H +#define EFR32BG22_IADC_H +#define IADC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_IADC IADC + * @{ + * @brief EFR32BG22 IADC Register Declaration. + *****************************************************************************/ + +/** IADC CFG Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< Configuration */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t SCALE; /**< Scaling */ + __IOM uint32_t SCHED; /**< Scheduling */ +} IADC_CFG_TypeDef; + +/** IADC SCANTABLE Register Group Declaration. */ +typedef struct { + __IOM uint32_t SCAN; /**< SCAN Entry */ +} IADC_SCANTABLE_TypeDef; + +/** IADC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< Enable */ + __IOM uint32_t CTRL; /**< Control */ + __IOM uint32_t CMD; /**< Command */ + __IOM uint32_t TIMER; /**< Timer */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t MASKREQ; /**< Mask Request */ + __IM uint32_t STMASK; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF; /**< Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER; /**< Trigger */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG[2U]; /**< CFG */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA; /**< Single FIFO Read Data */ + __IM uint32_t SINGLEFIFOSTAT; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA; /**< Scan Data */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE; /**< Single Queue Port Selection */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE[16U]; /**< SCANTABLE */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + uint32_t RESERVED8[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< Enable */ + __IOM uint32_t CTRL_SET; /**< Control */ + __IOM uint32_t CMD_SET; /**< Command */ + __IOM uint32_t TIMER_SET; /**< Timer */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t MASKREQ_SET; /**< Mask Request */ + __IM uint32_t STMASK_SET; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_SET; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_SET; /**< Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_SET; /**< Trigger */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + uint32_t RESERVED10[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_SET[2U]; /**< CFG */ + uint32_t RESERVED11[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_SET; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_SET; /**< Single FIFO Read Data */ + __IM uint32_t SINGLEFIFOSTAT_SET; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_SET; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_SET; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_SET; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_SET; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_SET; /**< Scan Data */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_SET; /**< Single Queue Port Selection */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_SET[16U]; /**< SCANTABLE */ + uint32_t RESERVED15[4U]; /**< Reserved for future use */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + uint32_t RESERVED17[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< Enable */ + __IOM uint32_t CTRL_CLR; /**< Control */ + __IOM uint32_t CMD_CLR; /**< Command */ + __IOM uint32_t TIMER_CLR; /**< Timer */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t MASKREQ_CLR; /**< Mask Request */ + __IM uint32_t STMASK_CLR; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_CLR; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_CLR; /**< Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_CLR; /**< Trigger */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + uint32_t RESERVED19[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_CLR[2U]; /**< CFG */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_CLR; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_CLR; /**< Single FIFO Read Data */ + __IM uint32_t SINGLEFIFOSTAT_CLR; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_CLR; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_CLR; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_CLR; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_CLR; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_CLR; /**< Scan Data */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_CLR; /**< Single Queue Port Selection */ + uint32_t RESERVED23[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_CLR[16U]; /**< SCANTABLE */ + uint32_t RESERVED24[4U]; /**< Reserved for future use */ + uint32_t RESERVED25[1U]; /**< Reserved for future use */ + uint32_t RESERVED26[963U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< Enable */ + __IOM uint32_t CTRL_TGL; /**< Control */ + __IOM uint32_t CMD_TGL; /**< Command */ + __IOM uint32_t TIMER_TGL; /**< Timer */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t MASKREQ_TGL; /**< Mask Request */ + __IM uint32_t STMASK_TGL; /**< Scan Table Mask */ + __IOM uint32_t CMPTHR_TGL; /**< Digital Window Comparator Threshold */ + __IOM uint32_t IF_TGL; /**< Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + __IOM uint32_t TRIGGER_TGL; /**< Trigger */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[5U]; /**< Reserved for future use */ + IADC_CFG_TypeDef CFG_TGL[2U]; /**< CFG */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t SINGLEFIFOCFG_TGL; /**< Single FIFO Configuration */ + __IM uint32_t SINGLEFIFODATA_TGL; /**< Single FIFO Read Data */ + __IM uint32_t SINGLEFIFOSTAT_TGL; /**< Single FIFO Status */ + __IM uint32_t SINGLEDATA_TGL; /**< Single Data */ + __IOM uint32_t SCANFIFOCFG_TGL; /**< Scan FIFO Configuration */ + __IM uint32_t SCANFIFODATA_TGL; /**< Scan FIFO Read Data */ + __IM uint32_t SCANFIFOSTAT_TGL; /**< Scan FIFO Status */ + __IM uint32_t SCANDATA_TGL; /**< Scan Data */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + uint32_t RESERVED31[1U]; /**< Reserved for future use */ + __IOM uint32_t SINGLE_TGL; /**< Single Queue Port Selection */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + IADC_SCANTABLE_TypeDef SCANTABLE_TGL[16U]; /**< SCANTABLE */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[1U]; /**< Reserved for future use */ +} IADC_TypeDef; +/** @} End of group EFR32BG22_IADC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_IADC + * @{ + * @defgroup EFR32BG22_IADC_BitFields IADC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for IADC IPVERSION */ +#define _IADC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for IADC_IPVERSION */ +#define _IADC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_IPVERSION */ +#define _IADC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_IPVERSION */ +#define IADC_IPVERSION_IPVERSION_DEFAULT (_IADC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IPVERSION */ + +/* Bit fields for IADC EN */ +#define _IADC_EN_RESETVALUE 0x00000000UL /**< Default value for IADC_EN */ +#define _IADC_EN_MASK 0x00000001UL /**< Mask for IADC_EN */ +#define IADC_EN_EN (0x1UL << 0) /**< Enable IADC Module */ +#define _IADC_EN_EN_SHIFT 0 /**< Shift value for IADC_EN */ +#define _IADC_EN_EN_MASK 0x1UL /**< Bit mask for IADC_EN */ +#define _IADC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_EN */ +#define _IADC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for IADC_EN */ +#define _IADC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for IADC_EN */ +#define IADC_EN_EN_DEFAULT (_IADC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_EN */ +#define IADC_EN_EN_DISABLE (_IADC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for IADC_EN */ +#define IADC_EN_EN_ENABLE (_IADC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for IADC_EN */ + +/* Bit fields for IADC CTRL */ +#define _IADC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IADC_CTRL */ +#define _IADC_CTRL_MASK 0x707F003FUL /**< Mask for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT (0x1UL << 0) /**< EM23 Wakeup on Conversion */ +#define _IADC_CTRL_EM23WUCONVERT_SHIFT 0 /**< Shift value for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_MASK 0x1UL /**< Bit mask for IADC_EM23WUCONVERT */ +#define _IADC_CTRL_EM23WUCONVERT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUDVL 0x00000000UL /**< Mode WUDVL for IADC_CTRL */ +#define _IADC_CTRL_EM23WUCONVERT_WUCONVERT 0x00000001UL /**< Mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_DEFAULT (_IADC_CTRL_EM23WUCONVERT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUDVL (_IADC_CTRL_EM23WUCONVERT_WUDVL << 0) /**< Shifted mode WUDVL for IADC_CTRL */ +#define IADC_CTRL_EM23WUCONVERT_WUCONVERT (_IADC_CTRL_EM23WUCONVERT_WUCONVERT << 0) /**< Shifted mode WUCONVERT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0 (0x1UL << 1) /**< ADC_CLK Suspend - PRS0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_SHIFT 1 /**< Shift value for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_MASK 0x2UL /**< Bit mask for IADC_ADCCLKSUSPEND0 */ +#define _IADC_CTRL_ADCCLKSUSPEND0_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND0_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUDIS << 1) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND0_PRSWUEN << 1) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1 (0x1UL << 2) /**< ADC_CLK Suspend - PRS1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_SHIFT 2 /**< Shift value for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_MASK 0x4UL /**< Bit mask for IADC_ADCCLKSUSPEND1 */ +#define _IADC_CTRL_ADCCLKSUSPEND1_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS 0x00000000UL /**< Mode PRSWUDIS for IADC_CTRL */ +#define _IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN 0x00000001UL /**< Mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_DEFAULT (_IADC_CTRL_ADCCLKSUSPEND1_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUDIS << 2) /**< Shifted mode PRSWUDIS for IADC_CTRL */ +#define IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN (_IADC_CTRL_ADCCLKSUSPEND1_PRSWUEN << 2) /**< Shifted mode PRSWUEN for IADC_CTRL */ +#define IADC_CTRL_DBGHALT (0x1UL << 3) /**< Debug Halt */ +#define _IADC_CTRL_DBGHALT_SHIFT 3 /**< Shift value for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_MASK 0x8UL /**< Bit mask for IADC_DBGHALT */ +#define _IADC_CTRL_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_DBGHALT_HALT 0x00000001UL /**< Mode HALT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_DEFAULT (_IADC_CTRL_DBGHALT_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_NORMAL (_IADC_CTRL_DBGHALT_NORMAL << 3) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_DBGHALT_HALT (_IADC_CTRL_DBGHALT_HALT << 3) /**< Shifted mode HALT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_SHIFT 4 /**< Shift value for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_MASK 0x30UL /**< Bit mask for IADC_WARMUPMODE */ +#define _IADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY 0x00000001UL /**< Mode KEEPINSTANDBY for IADC_CTRL */ +#define _IADC_CTRL_WARMUPMODE_KEEPWARM 0x00000002UL /**< Mode KEEPWARM for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_DEFAULT (_IADC_CTRL_WARMUPMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_NORMAL (_IADC_CTRL_WARMUPMODE_NORMAL << 4) /**< Shifted mode NORMAL for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPINSTANDBY (_IADC_CTRL_WARMUPMODE_KEEPINSTANDBY << 4) /**< Shifted mode KEEPINSTANDBY for IADC_CTRL */ +#define IADC_CTRL_WARMUPMODE_KEEPWARM (_IADC_CTRL_WARMUPMODE_KEEPWARM << 4) /**< Shifted mode KEEPWARM for IADC_CTRL */ +#define _IADC_CTRL_TIMEBASE_SHIFT 16 /**< Shift value for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_MASK 0x7F0000UL /**< Bit mask for IADC_TIMEBASE */ +#define _IADC_CTRL_TIMEBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_TIMEBASE_DEFAULT (_IADC_CTRL_TIMEBASE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_SHIFT 28 /**< Shift value for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_MASK 0x70000000UL /**< Bit mask for IADC_HSCLKRATE */ +#define _IADC_CTRL_HSCLKRATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV1 0x00000000UL /**< Mode DIV1 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV2 0x00000001UL /**< Mode DIV2 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV3 0x00000002UL /**< Mode DIV3 for IADC_CTRL */ +#define _IADC_CTRL_HSCLKRATE_DIV4 0x00000003UL /**< Mode DIV4 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DEFAULT (_IADC_CTRL_HSCLKRATE_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV1 (_IADC_CTRL_HSCLKRATE_DIV1 << 28) /**< Shifted mode DIV1 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV2 (_IADC_CTRL_HSCLKRATE_DIV2 << 28) /**< Shifted mode DIV2 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV3 (_IADC_CTRL_HSCLKRATE_DIV3 << 28) /**< Shifted mode DIV3 for IADC_CTRL */ +#define IADC_CTRL_HSCLKRATE_DIV4 (_IADC_CTRL_HSCLKRATE_DIV4 << 28) /**< Shifted mode DIV4 for IADC_CTRL */ + +/* Bit fields for IADC CMD */ +#define _IADC_CMD_RESETVALUE 0x00000000UL /**< Default value for IADC_CMD */ +#define _IADC_CMD_MASK 0x0303001BUL /**< Mask for IADC_CMD */ +#define IADC_CMD_SINGLESTART (0x1UL << 0) /**< Single Queue Start */ +#define _IADC_CMD_SINGLESTART_SHIFT 0 /**< Shift value for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_MASK 0x1UL /**< Bit mask for IADC_SINGLESTART */ +#define _IADC_CMD_SINGLESTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTART_DEFAULT (_IADC_CMD_SINGLESTART_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP (0x1UL << 1) /**< Single Queue Stop */ +#define _IADC_CMD_SINGLESTOP_SHIFT 1 /**< Shift value for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_MASK 0x2UL /**< Bit mask for IADC_SINGLESTOP */ +#define _IADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLESTOP_DEFAULT (_IADC_CMD_SINGLESTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART (0x1UL << 3) /**< Scan Queue Start */ +#define _IADC_CMD_SCANSTART_SHIFT 3 /**< Shift value for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_MASK 0x8UL /**< Bit mask for IADC_SCANSTART */ +#define _IADC_CMD_SCANSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTART_DEFAULT (_IADC_CMD_SCANSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP (0x1UL << 4) /**< Scan Queue Stop */ +#define _IADC_CMD_SCANSTOP_SHIFT 4 /**< Shift value for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_MASK 0x10UL /**< Bit mask for IADC_SCANSTOP */ +#define _IADC_CMD_SCANSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANSTOP_DEFAULT (_IADC_CMD_SCANSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN (0x1UL << 16) /**< Timer Enable */ +#define _IADC_CMD_TIMEREN_SHIFT 16 /**< Shift value for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_MASK 0x10000UL /**< Bit mask for IADC_TIMEREN */ +#define _IADC_CMD_TIMEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMEREN_DEFAULT (_IADC_CMD_TIMEREN_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS (0x1UL << 17) /**< Timer Disable */ +#define _IADC_CMD_TIMERDIS_SHIFT 17 /**< Shift value for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_MASK 0x20000UL /**< Bit mask for IADC_TIMERDIS */ +#define _IADC_CMD_TIMERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_TIMERDIS_DEFAULT (_IADC_CMD_TIMERDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH (0x1UL << 24) /**< Flush the Single FIFO */ +#define _IADC_CMD_SINGLEFIFOFLUSH_SHIFT 24 /**< Shift value for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_MASK 0x1000000UL /**< Bit mask for IADC_SINGLEFIFOFLUSH */ +#define _IADC_CMD_SINGLEFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SINGLEFIFOFLUSH_DEFAULT (_IADC_CMD_SINGLEFIFOFLUSH_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH (0x1UL << 25) /**< Flush the Scan FIFO */ +#define _IADC_CMD_SCANFIFOFLUSH_SHIFT 25 /**< Shift value for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_MASK 0x2000000UL /**< Bit mask for IADC_SCANFIFOFLUSH */ +#define _IADC_CMD_SCANFIFOFLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMD */ +#define IADC_CMD_SCANFIFOFLUSH_DEFAULT (_IADC_CMD_SCANFIFOFLUSH_DEFAULT << 25) /**< Shifted mode DEFAULT for IADC_CMD */ + +/* Bit fields for IADC TIMER */ +#define _IADC_TIMER_RESETVALUE 0x00000000UL /**< Default value for IADC_TIMER */ +#define _IADC_TIMER_MASK 0x0000FFFFUL /**< Mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_SHIFT 0 /**< Shift value for IADC_TIMER */ +#define _IADC_TIMER_TIMER_MASK 0xFFFFUL /**< Bit mask for IADC_TIMER */ +#define _IADC_TIMER_TIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TIMER */ +#define IADC_TIMER_TIMER_DEFAULT (_IADC_TIMER_TIMER_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TIMER */ + +/* Bit fields for IADC STATUS */ +#define _IADC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IADC_STATUS */ +#define _IADC_STATUS_MASK 0x4131CF5BUL /**< Mask for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN (0x1UL << 0) /**< Single Queue Enabled */ +#define _IADC_STATUS_SINGLEQEN_SHIFT 0 /**< Shift value for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_MASK 0x1UL /**< Bit mask for IADC_SINGLEQEN */ +#define _IADC_STATUS_SINGLEQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQEN_DEFAULT (_IADC_STATUS_SINGLEQEN_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING (0x1UL << 1) /**< Single Queue Pending */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_SHIFT 1 /**< Shift value for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_MASK 0x2UL /**< Bit mask for IADC_SINGLEQUEUEPENDING */ +#define _IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT (_IADC_STATUS_SINGLEQUEUEPENDING_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN (0x1UL << 3) /**< Scan Queued Enabled */ +#define _IADC_STATUS_SCANQEN_SHIFT 3 /**< Shift value for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_MASK 0x8UL /**< Bit mask for IADC_SCANQEN */ +#define _IADC_STATUS_SCANQEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQEN_DEFAULT (_IADC_STATUS_SCANQEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING (0x1UL << 4) /**< Scan Queue Pending */ +#define _IADC_STATUS_SCANQUEUEPENDING_SHIFT 4 /**< Shift value for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_MASK 0x10UL /**< Bit mask for IADC_SCANQUEUEPENDING */ +#define _IADC_STATUS_SCANQUEUEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANQUEUEPENDING_DEFAULT (_IADC_STATUS_SCANQUEUEPENDING_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING (0x1UL << 6) /**< Converting */ +#define _IADC_STATUS_CONVERTING_SHIFT 6 /**< Shift value for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_MASK 0x40UL /**< Bit mask for IADC_CONVERTING */ +#define _IADC_STATUS_CONVERTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_CONVERTING_DEFAULT (_IADC_STATUS_CONVERTING_DEFAULT << 6) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV (0x1UL << 8) /**< SINGLEFIFO Data Valid */ +#define _IADC_STATUS_SINGLEFIFODV_SHIFT 8 /**< Shift value for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_MASK 0x100UL /**< Bit mask for IADC_SINGLEFIFODV */ +#define _IADC_STATUS_SINGLEFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFODV_DEFAULT (_IADC_STATUS_SINGLEFIFODV_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV (0x1UL << 9) /**< SCANFIFO Data Valid */ +#define _IADC_STATUS_SCANFIFODV_SHIFT 9 /**< Shift value for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_MASK 0x200UL /**< Bit mask for IADC_SCANFIFODV */ +#define _IADC_STATUS_SCANFIFODV_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFODV_DEFAULT (_IADC_STATUS_SCANFIFODV_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING (0x1UL << 14) /**< The Single FIFO is flushing */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_SHIFT 14 /**< Shift value for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_MASK 0x4000UL /**< Bit mask for IADC_SINGLEFIFOFLUSHING */ +#define _IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT (_IADC_STATUS_SINGLEFIFOFLUSHING_DEFAULT << 14) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING (0x1UL << 15) /**< The Scan FIFO is flushing */ +#define _IADC_STATUS_SCANFIFOFLUSHING_SHIFT 15 /**< Shift value for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_MASK 0x8000UL /**< Bit mask for IADC_SCANFIFOFLUSHING */ +#define _IADC_STATUS_SCANFIFOFLUSHING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SCANFIFOFLUSHING_DEFAULT (_IADC_STATUS_SCANFIFOFLUSHING_DEFAULT << 15) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE (0x1UL << 16) /**< Timer Active */ +#define _IADC_STATUS_TIMERACTIVE_SHIFT 16 /**< Shift value for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_MASK 0x10000UL /**< Bit mask for IADC_TIMERACTIVE */ +#define _IADC_STATUS_TIMERACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_TIMERACTIVE_DEFAULT (_IADC_STATUS_TIMERACTIVE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING (0x1UL << 20) /**< SINGLE write pending */ +#define _IADC_STATUS_SINGLEWRITEPENDING_SHIFT 20 /**< Shift value for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_MASK 0x100000UL /**< Bit mask for IADC_SINGLEWRITEPENDING */ +#define _IADC_STATUS_SINGLEWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SINGLEWRITEPENDING_DEFAULT (_IADC_STATUS_SINGLEWRITEPENDING_DEFAULT << 20) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING (0x1UL << 21) /**< MASKREQ write pending */ +#define _IADC_STATUS_MASKREQWRITEPENDING_SHIFT 21 /**< Shift value for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_MASK 0x200000UL /**< Bit mask for IADC_MASKREQWRITEPENDING */ +#define _IADC_STATUS_MASKREQWRITEPENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_MASKREQWRITEPENDING_DEFAULT (_IADC_STATUS_MASKREQWRITEPENDING_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY (0x1UL << 24) /**< SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_SHIFT 24 /**< Shift value for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_MASK 0x1000000UL /**< Bit mask for IADC_SYNCBUSY */ +#define _IADC_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_SYNCBUSY_DEFAULT (_IADC_STATUS_SYNCBUSY_DEFAULT << 24) /**< Shifted mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM (0x1UL << 30) /**< ADCWARM */ +#define _IADC_STATUS_ADCWARM_SHIFT 30 /**< Shift value for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_MASK 0x40000000UL /**< Bit mask for IADC_ADCWARM */ +#define _IADC_STATUS_ADCWARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STATUS */ +#define IADC_STATUS_ADCWARM_DEFAULT (_IADC_STATUS_ADCWARM_DEFAULT << 30) /**< Shifted mode DEFAULT for IADC_STATUS */ + +/* Bit fields for IADC MASKREQ */ +#define _IADC_MASKREQ_RESETVALUE 0x00000000UL /**< Default value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASK 0x0000FFFFUL /**< Mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_SHIFT 0 /**< Shift value for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_MASK 0xFFFFUL /**< Bit mask for IADC_MASKREQ */ +#define _IADC_MASKREQ_MASKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_MASKREQ */ +#define IADC_MASKREQ_MASKREQ_DEFAULT (_IADC_MASKREQ_MASKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_MASKREQ */ + +/* Bit fields for IADC STMASK */ +#define _IADC_STMASK_RESETVALUE 0x00000000UL /**< Default value for IADC_STMASK */ +#define _IADC_STMASK_MASK 0x0000FFFFUL /**< Mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_SHIFT 0 /**< Shift value for IADC_STMASK */ +#define _IADC_STMASK_STMASK_MASK 0xFFFFUL /**< Bit mask for IADC_STMASK */ +#define _IADC_STMASK_STMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_STMASK */ +#define IADC_STMASK_STMASK_DEFAULT (_IADC_STMASK_STMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_STMASK */ + +/* Bit fields for IADC CMPTHR */ +#define _IADC_CMPTHR_RESETVALUE 0x00000000UL /**< Default value for IADC_CMPTHR */ +#define _IADC_CMPTHR_MASK 0xFFFFFFFFUL /**< Mask for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADLT_SHIFT 0 /**< Shift value for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_MASK 0xFFFFUL /**< Bit mask for IADC_ADLT */ +#define _IADC_CMPTHR_ADLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADLT_DEFAULT (_IADC_CMPTHR_ADLT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CMPTHR */ +#define _IADC_CMPTHR_ADGT_SHIFT 16 /**< Shift value for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_MASK 0xFFFF0000UL /**< Bit mask for IADC_ADGT */ +#define _IADC_CMPTHR_ADGT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CMPTHR */ +#define IADC_CMPTHR_ADGT_DEFAULT (_IADC_CMPTHR_ADGT_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CMPTHR */ + +/* Bit fields for IADC IF */ +#define _IADC_IF_RESETVALUE 0x00000000UL /**< Default value for IADC_IF */ +#define _IADC_IF_MASK 0x800F338FUL /**< Mask for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level */ +#define _IADC_IF_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IF_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFODVL_DEFAULT (_IADC_IF_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level */ +#define _IADC_IF_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IF_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFODVL_DEFAULT (_IADC_IF_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare */ +#define _IADC_IF_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IF_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLECMP_DEFAULT (_IADC_IF_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare */ +#define _IADC_IF_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IF_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANCMP_DEFAULT (_IADC_IF_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done */ +#define _IADC_IF_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IF_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANENTRYDONE_DEFAULT (_IADC_IF_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done */ +#define _IADC_IF_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IF_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANTABLEDONE_DEFAULT (_IADC_IF_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done */ +#define _IADC_IF_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IF_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEDONE_DEFAULT (_IADC_IF_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR (0x1UL << 12) /**< Polarity Error */ +#define _IADC_IF_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IF_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_POLARITYERR_DEFAULT (_IADC_IF_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error */ +#define _IADC_IF_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IF_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_PORTALLOCERR_DEFAULT (_IADC_IF_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow */ +#define _IADC_IF_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IF_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOOF_DEFAULT (_IADC_IF_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow */ +#define _IADC_IF_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IF_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOOF_DEFAULT (_IADC_IF_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow */ +#define _IADC_IF_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IF_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SINGLEFIFOUF_DEFAULT (_IADC_IF_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow */ +#define _IADC_IF_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IF_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_SCANFIFOUF_DEFAULT (_IADC_IF_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error */ +#define _IADC_IF_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IF_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IF */ +#define IADC_IF_EM23ABORTERROR_DEFAULT (_IADC_IF_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IF */ + +/* Bit fields for IADC IEN */ +#define _IADC_IEN_RESETVALUE 0x00000000UL /**< Default value for IADC_IEN */ +#define _IADC_IEN_MASK 0x800F338FUL /**< Mask for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL (0x1UL << 0) /**< Single FIFO Data Valid Level Enable */ +#define _IADC_IEN_SINGLEFIFODVL_SHIFT 0 /**< Shift value for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_MASK 0x1UL /**< Bit mask for IADC_SINGLEFIFODVL */ +#define _IADC_IEN_SINGLEFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFODVL_DEFAULT (_IADC_IEN_SINGLEFIFODVL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL (0x1UL << 1) /**< Scan FIFO Data Valid Level Enable */ +#define _IADC_IEN_SCANFIFODVL_SHIFT 1 /**< Shift value for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_MASK 0x2UL /**< Bit mask for IADC_SCANFIFODVL */ +#define _IADC_IEN_SCANFIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFODVL_DEFAULT (_IADC_IEN_SCANFIFODVL_DEFAULT << 1) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP (0x1UL << 2) /**< Single Result Window Compare Enable */ +#define _IADC_IEN_SINGLECMP_SHIFT 2 /**< Shift value for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_MASK 0x4UL /**< Bit mask for IADC_SINGLECMP */ +#define _IADC_IEN_SINGLECMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLECMP_DEFAULT (_IADC_IEN_SINGLECMP_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP (0x1UL << 3) /**< Scan Result Window Compare Enable */ +#define _IADC_IEN_SCANCMP_SHIFT 3 /**< Shift value for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_MASK 0x8UL /**< Bit mask for IADC_SCANCMP */ +#define _IADC_IEN_SCANCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANCMP_DEFAULT (_IADC_IEN_SCANCMP_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE (0x1UL << 7) /**< Scan Entry Done Enable */ +#define _IADC_IEN_SCANENTRYDONE_SHIFT 7 /**< Shift value for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_MASK 0x80UL /**< Bit mask for IADC_SCANENTRYDONE */ +#define _IADC_IEN_SCANENTRYDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANENTRYDONE_DEFAULT (_IADC_IEN_SCANENTRYDONE_DEFAULT << 7) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE (0x1UL << 8) /**< Scan Table Done Enable */ +#define _IADC_IEN_SCANTABLEDONE_SHIFT 8 /**< Shift value for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_MASK 0x100UL /**< Bit mask for IADC_SCANTABLEDONE */ +#define _IADC_IEN_SCANTABLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANTABLEDONE_DEFAULT (_IADC_IEN_SCANTABLEDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE (0x1UL << 9) /**< Single Conversion Done Enable */ +#define _IADC_IEN_SINGLEDONE_SHIFT 9 /**< Shift value for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_MASK 0x200UL /**< Bit mask for IADC_SINGLEDONE */ +#define _IADC_IEN_SINGLEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEDONE_DEFAULT (_IADC_IEN_SINGLEDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR (0x1UL << 12) /**< Polarity Error Enable */ +#define _IADC_IEN_POLARITYERR_SHIFT 12 /**< Shift value for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_MASK 0x1000UL /**< Bit mask for IADC_POLARITYERR */ +#define _IADC_IEN_POLARITYERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_POLARITYERR_DEFAULT (_IADC_IEN_POLARITYERR_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR (0x1UL << 13) /**< Port Allocation Error Enable */ +#define _IADC_IEN_PORTALLOCERR_SHIFT 13 /**< Shift value for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_MASK 0x2000UL /**< Bit mask for IADC_PORTALLOCERR */ +#define _IADC_IEN_PORTALLOCERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_PORTALLOCERR_DEFAULT (_IADC_IEN_PORTALLOCERR_DEFAULT << 13) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF (0x1UL << 16) /**< Single FIFO Overflow Enable */ +#define _IADC_IEN_SINGLEFIFOOF_SHIFT 16 /**< Shift value for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_MASK 0x10000UL /**< Bit mask for IADC_SINGLEFIFOOF */ +#define _IADC_IEN_SINGLEFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOOF_DEFAULT (_IADC_IEN_SINGLEFIFOOF_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF (0x1UL << 17) /**< Scan FIFO Overflow Enable */ +#define _IADC_IEN_SCANFIFOOF_SHIFT 17 /**< Shift value for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_MASK 0x20000UL /**< Bit mask for IADC_SCANFIFOOF */ +#define _IADC_IEN_SCANFIFOOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOOF_DEFAULT (_IADC_IEN_SCANFIFOOF_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF (0x1UL << 18) /**< Single FIFO Underflow Enable */ +#define _IADC_IEN_SINGLEFIFOUF_SHIFT 18 /**< Shift value for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_MASK 0x40000UL /**< Bit mask for IADC_SINGLEFIFOUF */ +#define _IADC_IEN_SINGLEFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SINGLEFIFOUF_DEFAULT (_IADC_IEN_SINGLEFIFOUF_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF (0x1UL << 19) /**< Scan FIFO Underflow Enable */ +#define _IADC_IEN_SCANFIFOUF_SHIFT 19 /**< Shift value for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_MASK 0x80000UL /**< Bit mask for IADC_SCANFIFOUF */ +#define _IADC_IEN_SCANFIFOUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_SCANFIFOUF_DEFAULT (_IADC_IEN_SCANFIFOUF_DEFAULT << 19) /**< Shifted mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR (0x1UL << 31) /**< EM2/3 Abort Error Enable */ +#define _IADC_IEN_EM23ABORTERROR_SHIFT 31 /**< Shift value for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_MASK 0x80000000UL /**< Bit mask for IADC_EM23ABORTERROR */ +#define _IADC_IEN_EM23ABORTERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_IEN */ +#define IADC_IEN_EM23ABORTERROR_DEFAULT (_IADC_IEN_EM23ABORTERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_IEN */ + +/* Bit fields for IADC TRIGGER */ +#define _IADC_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for IADC_TRIGGER */ +#define _IADC_TRIGGER_MASK 0x00011717UL /**< Mask for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_SHIFT 0 /**< Shift value for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_MASK 0x7UL /**< Bit mask for IADC_SCANTRIGSEL */ +#define _IADC_TRIGGER_SCANTRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_DEFAULT (_IADC_TRIGGER_SCANTRIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE (_IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE << 0) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_TIMER (_IADC_TRIGGER_SCANTRIGSEL_TIMER << 0) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP << 0) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSPOS (_IADC_TRIGGER_SCANTRIGSEL_PRSPOS << 0) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGSEL_PRSNEG (_IADC_TRIGGER_SCANTRIGSEL_PRSNEG << 0) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION (0x1UL << 4) /**< Scan Trigger Action */ +#define _IADC_TRIGGER_SCANTRIGACTION_SHIFT 4 /**< Shift value for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_MASK 0x10UL /**< Bit mask for IADC_SCANTRIGACTION */ +#define _IADC_TRIGGER_SCANTRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_DEFAULT (_IADC_TRIGGER_SCANTRIGACTION_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_ONCE (_IADC_TRIGGER_SCANTRIGACTION_ONCE << 4) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS (_IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS << 4) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_SHIFT 8 /**< Shift value for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_MASK 0x700UL /**< Bit mask for IADC_SINGLETRIGSEL */ +#define _IADC_TRIGGER_SINGLETRIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE 0x00000000UL /**< Mode IMMEDIATE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_TIMER 0x00000001UL /**< Mode TIMER for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP 0x00000002UL /**< Mode PRSCLKGRP for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSPOS 0x00000003UL /**< Mode PRSPOS for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGSEL_PRSNEG 0x00000004UL /**< Mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_DEFAULT (_IADC_TRIGGER_SINGLETRIGSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE (_IADC_TRIGGER_SINGLETRIGSEL_IMMEDIATE << 8) /**< Shifted mode IMMEDIATE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_TIMER (_IADC_TRIGGER_SINGLETRIGSEL_TIMER << 8) /**< Shifted mode TIMER for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP (_IADC_TRIGGER_SINGLETRIGSEL_PRSCLKGRP << 8) /**< Shifted mode PRSCLKGRP for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSPOS (_IADC_TRIGGER_SINGLETRIGSEL_PRSPOS << 8) /**< Shifted mode PRSPOS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGSEL_PRSNEG (_IADC_TRIGGER_SINGLETRIGSEL_PRSNEG << 8) /**< Shifted mode PRSNEG for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION (0x1UL << 12) /**< Single Trigger Action */ +#define _IADC_TRIGGER_SINGLETRIGACTION_SHIFT 12 /**< Shift value for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_MASK 0x1000UL /**< Bit mask for IADC_SINGLETRIGACTION */ +#define _IADC_TRIGGER_SINGLETRIGACTION_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_ONCE 0x00000000UL /**< Mode ONCE for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS 0x00000001UL /**< Mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_DEFAULT (_IADC_TRIGGER_SINGLETRIGACTION_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_ONCE (_IADC_TRIGGER_SINGLETRIGACTION_ONCE << 12) /**< Shifted mode ONCE for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS (_IADC_TRIGGER_SINGLETRIGACTION_CONTINUOUS << 12) /**< Shifted mode CONTINUOUS for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE (0x1UL << 16) /**< Single Tailgate Enable */ +#define _IADC_TRIGGER_SINGLETAILGATE_SHIFT 16 /**< Shift value for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_MASK 0x10000UL /**< Bit mask for IADC_SINGLETAILGATE */ +#define _IADC_TRIGGER_SINGLETAILGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF 0x00000000UL /**< Mode TAILGATEOFF for IADC_TRIGGER */ +#define _IADC_TRIGGER_SINGLETAILGATE_TAILGATEON 0x00000001UL /**< Mode TAILGATEON for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_DEFAULT (_IADC_TRIGGER_SINGLETAILGATE_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEOFF << 16) /**< Shifted mode TAILGATEOFF for IADC_TRIGGER */ +#define IADC_TRIGGER_SINGLETAILGATE_TAILGATEON (_IADC_TRIGGER_SINGLETAILGATE_TAILGATEON << 16) /**< Shifted mode TAILGATEON for IADC_TRIGGER */ + +/* Bit fields for IADC CFG */ +#define _IADC_CFG_RESETVALUE 0x00002060UL /**< Default value for IADC_CFG */ +#define _IADC_CFG_MASK 0x30E770FFUL /**< Mask for IADC_CFG */ +#define _IADC_CFG_ADCMODE_SHIFT 0 /**< Shift value for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_MASK 0x3UL /**< Bit mask for IADC_ADCMODE */ +#define _IADC_CFG_ADCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ADCMODE_NORMAL 0x00000000UL /**< Mode NORMAL for IADC_CFG */ +#define IADC_CFG_ADCMODE_DEFAULT (_IADC_CFG_ADCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ADCMODE_NORMAL (_IADC_CFG_ADCMODE_NORMAL << 0) /**< Shifted mode NORMAL for IADC_CFG */ +#define _IADC_CFG_OSRHS_SHIFT 2 /**< Shift value for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_MASK 0x1CUL /**< Bit mask for IADC_OSRHS */ +#define _IADC_CFG_OSRHS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD2 0x00000000UL /**< Mode HISPD2 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD4 0x00000001UL /**< Mode HISPD4 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD8 0x00000002UL /**< Mode HISPD8 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD16 0x00000003UL /**< Mode HISPD16 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD32 0x00000004UL /**< Mode HISPD32 for IADC_CFG */ +#define _IADC_CFG_OSRHS_HISPD64 0x00000005UL /**< Mode HISPD64 for IADC_CFG */ +#define IADC_CFG_OSRHS_DEFAULT (_IADC_CFG_OSRHS_DEFAULT << 2) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD2 (_IADC_CFG_OSRHS_HISPD2 << 2) /**< Shifted mode HISPD2 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD4 (_IADC_CFG_OSRHS_HISPD4 << 2) /**< Shifted mode HISPD4 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD8 (_IADC_CFG_OSRHS_HISPD8 << 2) /**< Shifted mode HISPD8 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD16 (_IADC_CFG_OSRHS_HISPD16 << 2) /**< Shifted mode HISPD16 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD32 (_IADC_CFG_OSRHS_HISPD32 << 2) /**< Shifted mode HISPD32 for IADC_CFG */ +#define IADC_CFG_OSRHS_HISPD64 (_IADC_CFG_OSRHS_HISPD64 << 2) /**< Shifted mode HISPD64 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_SHIFT 12 /**< Shift value for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_MASK 0x7000UL /**< Bit mask for IADC_ANALOGGAIN */ +#define _IADC_CFG_ANALOGGAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN0P5 0x00000001UL /**< Mode ANAGAIN0P5 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN1 0x00000002UL /**< Mode ANAGAIN1 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN2 0x00000003UL /**< Mode ANAGAIN2 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN3 0x00000004UL /**< Mode ANAGAIN3 for IADC_CFG */ +#define _IADC_CFG_ANALOGGAIN_ANAGAIN4 0x00000005UL /**< Mode ANAGAIN4 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_DEFAULT (_IADC_CFG_ANALOGGAIN_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN0P5 (_IADC_CFG_ANALOGGAIN_ANAGAIN0P5 << 12) /**< Shifted mode ANAGAIN0P5 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN1 (_IADC_CFG_ANALOGGAIN_ANAGAIN1 << 12) /**< Shifted mode ANAGAIN1 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN2 (_IADC_CFG_ANALOGGAIN_ANAGAIN2 << 12) /**< Shifted mode ANAGAIN2 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN3 (_IADC_CFG_ANALOGGAIN_ANAGAIN3 << 12) /**< Shifted mode ANAGAIN3 for IADC_CFG */ +#define IADC_CFG_ANALOGGAIN_ANAGAIN4 (_IADC_CFG_ANALOGGAIN_ANAGAIN4 << 12) /**< Shifted mode ANAGAIN4 for IADC_CFG */ +#define _IADC_CFG_REFSEL_SHIFT 16 /**< Shift value for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_MASK 0x70000UL /**< Bit mask for IADC_REFSEL */ +#define _IADC_CFG_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_REFSEL_VBGR 0x00000000UL /**< Mode VBGR for IADC_CFG */ +#define _IADC_CFG_REFSEL_VREF 0x00000001UL /**< Mode VREF for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX 0x00000003UL /**< Mode VDDX for IADC_CFG */ +#define _IADC_CFG_REFSEL_VDDX0P8BUF 0x00000004UL /**< Mode VDDX0P8BUF for IADC_CFG */ +#define IADC_CFG_REFSEL_DEFAULT (_IADC_CFG_REFSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_REFSEL_VBGR (_IADC_CFG_REFSEL_VBGR << 16) /**< Shifted mode VBGR for IADC_CFG */ +#define IADC_CFG_REFSEL_VREF (_IADC_CFG_REFSEL_VREF << 16) /**< Shifted mode VREF for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX (_IADC_CFG_REFSEL_VDDX << 16) /**< Shifted mode VDDX for IADC_CFG */ +#define IADC_CFG_REFSEL_VDDX0P8BUF (_IADC_CFG_REFSEL_VDDX0P8BUF << 16) /**< Shifted mode VDDX0P8BUF for IADC_CFG */ +#define _IADC_CFG_DIGAVG_SHIFT 21 /**< Shift value for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_MASK 0xE00000UL /**< Bit mask for IADC_DIGAVG */ +#define _IADC_CFG_DIGAVG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG1 0x00000000UL /**< Mode AVG1 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG2 0x00000001UL /**< Mode AVG2 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG4 0x00000002UL /**< Mode AVG4 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG8 0x00000003UL /**< Mode AVG8 for IADC_CFG */ +#define _IADC_CFG_DIGAVG_AVG16 0x00000004UL /**< Mode AVG16 for IADC_CFG */ +#define IADC_CFG_DIGAVG_DEFAULT (_IADC_CFG_DIGAVG_DEFAULT << 21) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG1 (_IADC_CFG_DIGAVG_AVG1 << 21) /**< Shifted mode AVG1 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG2 (_IADC_CFG_DIGAVG_AVG2 << 21) /**< Shifted mode AVG2 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG4 (_IADC_CFG_DIGAVG_AVG4 << 21) /**< Shifted mode AVG4 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG8 (_IADC_CFG_DIGAVG_AVG8 << 21) /**< Shifted mode AVG8 for IADC_CFG */ +#define IADC_CFG_DIGAVG_AVG16 (_IADC_CFG_DIGAVG_AVG16 << 21) /**< Shifted mode AVG16 for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_SHIFT 28 /**< Shift value for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_MASK 0x30000000UL /**< Bit mask for IADC_TWOSCOMPL */ +#define _IADC_CFG_TWOSCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_AUTO 0x00000000UL /**< Mode AUTO for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR 0x00000001UL /**< Mode FORCEUNIPOLAR for IADC_CFG */ +#define _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR 0x00000002UL /**< Mode FORCEBIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_DEFAULT (_IADC_CFG_TWOSCOMPL_DEFAULT << 28) /**< Shifted mode DEFAULT for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_AUTO (_IADC_CFG_TWOSCOMPL_AUTO << 28) /**< Shifted mode AUTO for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR << 28) /**< Shifted mode FORCEUNIPOLAR for IADC_CFG */ +#define IADC_CFG_TWOSCOMPL_FORCEBIPOLAR (_IADC_CFG_TWOSCOMPL_FORCEBIPOLAR << 28) /**< Shifted mode FORCEBIPOLAR for IADC_CFG */ + +/* Bit fields for IADC SCALE */ +#define _IADC_SCALE_RESETVALUE 0x8002C000UL /**< Default value for IADC_SCALE */ +#define _IADC_SCALE_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCALE */ +#define _IADC_SCALE_OFFSET_SHIFT 0 /**< Shift value for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_MASK 0x3FFFFUL /**< Bit mask for IADC_OFFSET */ +#define _IADC_SCALE_OFFSET_DEFAULT 0x0002C000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_OFFSET_DEFAULT (_IADC_SCALE_OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN13LSB_SHIFT 18 /**< Shift value for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_MASK 0x7FFC0000UL /**< Bit mask for IADC_GAIN13LSB */ +#define _IADC_SCALE_GAIN13LSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN13LSB_DEFAULT (_IADC_SCALE_GAIN13LSB_DEFAULT << 18) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB (0x1UL << 31) /**< Gain 3 MSBs */ +#define _IADC_SCALE_GAIN3MSB_SHIFT 31 /**< Shift value for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_MASK 0x80000000UL /**< Bit mask for IADC_GAIN3MSB */ +#define _IADC_SCALE_GAIN3MSB_DEFAULT 0x00000001UL /**< Mode DEFAULT for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN011 0x00000000UL /**< Mode GAIN011 for IADC_SCALE */ +#define _IADC_SCALE_GAIN3MSB_GAIN100 0x00000001UL /**< Mode GAIN100 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_DEFAULT (_IADC_SCALE_GAIN3MSB_DEFAULT << 31) /**< Shifted mode DEFAULT for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN011 (_IADC_SCALE_GAIN3MSB_GAIN011 << 31) /**< Shifted mode GAIN011 for IADC_SCALE */ +#define IADC_SCALE_GAIN3MSB_GAIN100 (_IADC_SCALE_GAIN3MSB_GAIN100 << 31) /**< Shifted mode GAIN100 for IADC_SCALE */ + +/* Bit fields for IADC SCHED */ +#define _IADC_SCHED_RESETVALUE 0x00000000UL /**< Default value for IADC_SCHED */ +#define _IADC_SCHED_MASK 0x000003FFUL /**< Mask for IADC_SCHED */ +#define _IADC_SCHED_PRESCALE_SHIFT 0 /**< Shift value for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_MASK 0x3FFUL /**< Bit mask for IADC_PRESCALE */ +#define _IADC_SCHED_PRESCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCHED */ +#define IADC_SCHED_PRESCALE_DEFAULT (_IADC_SCHED_PRESCALE_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCHED */ + +/* Bit fields for IADC SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SINGLEFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SINGLEFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SINGLEFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_SHOWID_DEFAULT (_IADC_SINGLEFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SINGLEFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_DEFAULT (_IADC_SINGLEFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID1 (_IADC_SINGLEFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID2 (_IADC_SINGLEFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID3 (_IADC_SINGLEFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DVL_VALID4 (_IADC_SINGLEFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE (0x1UL << 8) /**< Single FIFO DMA wakeup. */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSINGLE */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SINGLEFIFOCFG */ +#define _IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOCFG */ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SINGLEFIFOCFG*/ +#define IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED (_IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SINGLEFIFOCFG */ + +/* Bit fields for IADC SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEFIFODATA */ +#define _IADC_SINGLEFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFODATA */ +#define IADC_SINGLEFIFODATA_DATA_DEFAULT (_IADC_SINGLEFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFODATA*/ + +/* Bit fields for IADC SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SINGLEFIFOSTAT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEFIFOSTAT */ +#define IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SINGLEFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEFIFOSTAT*/ + +/* Bit fields for IADC SINGLEDATA */ +#define _IADC_SINGLEDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SINGLEDATA */ +#define _IADC_SINGLEDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLEDATA */ +#define IADC_SINGLEDATA_DATA_DEFAULT (_IADC_SINGLEDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLEDATA */ + +/* Bit fields for IADC SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_RESETVALUE 0x00000030UL /**< Default value for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_MASK 0x0000013FUL /**< Mask for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT 0 /**< Shift value for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_MASK 0x7UL /**< Bit mask for IADC_ALIGNMENT */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 0x00000000UL /**< Mode RIGHT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 0x00000001UL /**< Mode RIGHT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 0x00000002UL /**< Mode RIGHT20 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 0x00000003UL /**< Mode LEFT12 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 0x00000004UL /**< Mode LEFT16 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 0x00000005UL /**< Mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT (_IADC_SCANFIFOCFG_ALIGNMENT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12 << 0) /**< Shifted mode RIGHT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16 << 0) /**< Shifted mode RIGHT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 (_IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20 << 0) /**< Shifted mode RIGHT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT12 << 0) /**< Shifted mode LEFT12 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT16 << 0) /**< Shifted mode LEFT16 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 (_IADC_SCANFIFOCFG_ALIGNMENT_LEFT20 << 0) /**< Shifted mode LEFT20 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID (0x1UL << 3) /**< Show ID */ +#define _IADC_SCANFIFOCFG_SHOWID_SHIFT 3 /**< Shift value for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_MASK 0x8UL /**< Bit mask for IADC_SHOWID */ +#define _IADC_SCANFIFOCFG_SHOWID_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_SHOWID_DEFAULT (_IADC_SCANFIFOCFG_SHOWID_DEFAULT << 3) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_SHIFT 4 /**< Shift value for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_MASK 0x30UL /**< Bit mask for IADC_DVL */ +#define _IADC_SCANFIFOCFG_DVL_DEFAULT 0x00000003UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID1 0x00000000UL /**< Mode VALID1 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID2 0x00000001UL /**< Mode VALID2 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID3 0x00000002UL /**< Mode VALID3 for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DVL_VALID4 0x00000003UL /**< Mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_DEFAULT (_IADC_SCANFIFOCFG_DVL_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID1 (_IADC_SCANFIFOCFG_DVL_VALID1 << 4) /**< Shifted mode VALID1 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID2 (_IADC_SCANFIFOCFG_DVL_VALID2 << 4) /**< Shifted mode VALID2 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID3 (_IADC_SCANFIFOCFG_DVL_VALID3 << 4) /**< Shifted mode VALID3 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DVL_VALID4 (_IADC_SCANFIFOCFG_DVL_VALID4 << 4) /**< Shifted mode VALID4 for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN (0x1UL << 8) /**< Scan FIFO DMA Wakeup */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_SHIFT 8 /**< Shift value for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_MASK 0x100UL /**< Bit mask for IADC_DMAWUFIFOSCAN */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED 0x00000000UL /**< Mode DISABLED for IADC_SCANFIFOCFG */ +#define _IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED 0x00000001UL /**< Mode ENABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_DISABLED << 8) /**< Shifted mode DISABLED for IADC_SCANFIFOCFG */ +#define IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED (_IADC_SCANFIFOCFG_DMAWUFIFOSCAN_ENABLED << 8) /**< Shifted mode ENABLED for IADC_SCANFIFOCFG */ + +/* Bit fields for IADC SCANFIFODATA */ +#define _IADC_SCANFIFODATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANFIFODATA */ +#define _IADC_SCANFIFODATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANFIFODATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFODATA */ +#define IADC_SCANFIFODATA_DATA_DEFAULT (_IADC_SCANFIFODATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFODATA */ + +/* Bit fields for IADC SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_MASK 0x00000007UL /**< Mask for IADC_SCANFIFOSTAT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT 0 /**< Shift value for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK 0x7UL /**< Bit mask for IADC_FIFOREADCNT */ +#define _IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANFIFOSTAT */ +#define IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT (_IADC_SCANFIFOSTAT_FIFOREADCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANFIFOSTAT */ + +/* Bit fields for IADC SCANDATA */ +#define _IADC_SCANDATA_RESETVALUE 0x00000000UL /**< Default value for IADC_SCANDATA */ +#define _IADC_SCANDATA_MASK 0xFFFFFFFFUL /**< Mask for IADC_SCANDATA */ +#define _IADC_SCANDATA_DATA_SHIFT 0 /**< Shift value for IADC_DATA */ +#define _IADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for IADC_DATA */ +#define _IADC_SCANDATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCANDATA */ +#define IADC_SCANDATA_DATA_DEFAULT (_IADC_SCANDATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCANDATA */ + +/* Bit fields for IADC SINGLE */ +#define _IADC_SINGLE_RESETVALUE 0x00000000UL /**< Default value for IADC_SINGLE */ +#define _IADC_SINGLE_MASK 0x0003FFFFUL /**< Mask for IADC_SINGLE */ +#define _IADC_SINGLE_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SINGLE_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINNEG_DEFAULT (_IADC_SINGLE_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SINGLE_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_DEFAULT (_IADC_SINGLE_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_GND (_IADC_SINGLE_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTA (_IADC_SINGLE_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTB (_IADC_SINGLE_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTC (_IADC_SINGLE_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTNEG_PORTD (_IADC_SINGLE_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SINGLE */ +#define _IADC_SINGLE_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SINGLE_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PINPOS_DEFAULT (_IADC_SINGLE_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SINGLE_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SINGLE */ +#define _IADC_SINGLE_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_DEFAULT (_IADC_SINGLE_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_GND (_IADC_SINGLE_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_SUPPLY (_IADC_SINGLE_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTA (_IADC_SINGLE_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTB (_IADC_SINGLE_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTC (_IADC_SINGLE_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SINGLE */ +#define IADC_SINGLE_PORTPOS_PORTD (_IADC_SINGLE_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SINGLE */ +#define IADC_SINGLE_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SINGLE_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SINGLE_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SINGLE_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SINGLE */ +#define _IADC_SINGLE_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_DEFAULT (_IADC_SINGLE_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG0 (_IADC_SINGLE_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SINGLE */ +#define IADC_SINGLE_CFG_CONFIG1 (_IADC_SINGLE_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SINGLE */ +#define IADC_SINGLE_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SINGLE_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SINGLE_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SINGLE_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SINGLE */ +#define IADC_SINGLE_CMP_DEFAULT (_IADC_SINGLE_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SINGLE */ + +/* Bit fields for IADC SCAN */ +#define _IADC_SCAN_RESETVALUE 0x00000000UL /**< Default value for IADC_SCAN */ +#define _IADC_SCAN_MASK 0x0003FFFFUL /**< Mask for IADC_SCAN */ +#define _IADC_SCAN_PINNEG_SHIFT 0 /**< Shift value for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_MASK 0xFUL /**< Bit mask for IADC_PINNEG */ +#define _IADC_SCAN_PINNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINNEG_DEFAULT (_IADC_SCAN_PINNEG_DEFAULT << 0) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_SHIFT 4 /**< Shift value for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_MASK 0xF0UL /**< Bit mask for IADC_PORTNEG */ +#define _IADC_SCAN_PORTNEG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTNEG_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_DEFAULT (_IADC_SCAN_PORTNEG_DEFAULT << 4) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_GND (_IADC_SCAN_PORTNEG_GND << 4) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTA (_IADC_SCAN_PORTNEG_PORTA << 4) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTB (_IADC_SCAN_PORTNEG_PORTB << 4) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTC (_IADC_SCAN_PORTNEG_PORTC << 4) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTNEG_PORTD (_IADC_SCAN_PORTNEG_PORTD << 4) /**< Shifted mode PORTD for IADC_SCAN */ +#define _IADC_SCAN_PINPOS_SHIFT 8 /**< Shift value for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_MASK 0xF00UL /**< Bit mask for IADC_PINPOS */ +#define _IADC_SCAN_PINPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PINPOS_DEFAULT (_IADC_SCAN_PINPOS_DEFAULT << 8) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SHIFT 12 /**< Shift value for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_MASK 0xF000UL /**< Bit mask for IADC_PORTPOS */ +#define _IADC_SCAN_PORTPOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_GND 0x00000000UL /**< Mode GND for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_SUPPLY 0x00000001UL /**< Mode SUPPLY for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTA 0x00000008UL /**< Mode PORTA for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTB 0x00000009UL /**< Mode PORTB for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTC 0x0000000AUL /**< Mode PORTC for IADC_SCAN */ +#define _IADC_SCAN_PORTPOS_PORTD 0x0000000BUL /**< Mode PORTD for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_DEFAULT (_IADC_SCAN_PORTPOS_DEFAULT << 12) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_GND (_IADC_SCAN_PORTPOS_GND << 12) /**< Shifted mode GND for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_SUPPLY (_IADC_SCAN_PORTPOS_SUPPLY << 12) /**< Shifted mode SUPPLY for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTA (_IADC_SCAN_PORTPOS_PORTA << 12) /**< Shifted mode PORTA for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTB (_IADC_SCAN_PORTPOS_PORTB << 12) /**< Shifted mode PORTB for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTC (_IADC_SCAN_PORTPOS_PORTC << 12) /**< Shifted mode PORTC for IADC_SCAN */ +#define IADC_SCAN_PORTPOS_PORTD (_IADC_SCAN_PORTPOS_PORTD << 12) /**< Shifted mode PORTD for IADC_SCAN */ +#define IADC_SCAN_CFG (0x1UL << 16) /**< Configuration Group Select */ +#define _IADC_SCAN_CFG_SHIFT 16 /**< Shift value for IADC_CFG */ +#define _IADC_SCAN_CFG_MASK 0x10000UL /**< Bit mask for IADC_CFG */ +#define _IADC_SCAN_CFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG0 0x00000000UL /**< Mode CONFIG0 for IADC_SCAN */ +#define _IADC_SCAN_CFG_CONFIG1 0x00000001UL /**< Mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CFG_DEFAULT (_IADC_SCAN_CFG_DEFAULT << 16) /**< Shifted mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG0 (_IADC_SCAN_CFG_CONFIG0 << 16) /**< Shifted mode CONFIG0 for IADC_SCAN */ +#define IADC_SCAN_CFG_CONFIG1 (_IADC_SCAN_CFG_CONFIG1 << 16) /**< Shifted mode CONFIG1 for IADC_SCAN */ +#define IADC_SCAN_CMP (0x1UL << 17) /**< Comparison Enable */ +#define _IADC_SCAN_CMP_SHIFT 17 /**< Shift value for IADC_CMP */ +#define _IADC_SCAN_CMP_MASK 0x20000UL /**< Bit mask for IADC_CMP */ +#define _IADC_SCAN_CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for IADC_SCAN */ +#define IADC_SCAN_CMP_DEFAULT (_IADC_SCAN_CMP_DEFAULT << 17) /**< Shifted mode DEFAULT for IADC_SCAN */ + +/** @} End of group EFR32BG22_IADC_BitFields */ +/** @} End of group EFR32BG22_IADC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_IADC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h index d8a31d8..adb4dfe 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_icache.h @@ -1,248 +1,248 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 ICACHE register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_ICACHE_H -#define EFR32BG22_ICACHE_H -#define ICACHE_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_ICACHE ICACHE - * @{ - * @brief EFR32BG22 ICACHE Register Declaration. - *****************************************************************************/ - -/** ICACHE Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t PCHITS; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LPMODE; /**< Low Power Mode */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED2[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ - __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ - __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ -} ICACHE_TypeDef; -/** @} End of group EFR32BG22_ICACHE */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_ICACHE - * @{ - * @defgroup EFR32BG22_ICACHE_BitFields ICACHE Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for ICACHE IPVERSION */ -#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ -#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ -#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ - -/* Bit fields for ICACHE CTRL */ -#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ -#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ -#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ -#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ -#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ -#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ -#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ -#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ - -/* Bit fields for ICACHE PCHITS */ -#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ -#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ -#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ - -/* Bit fields for ICACHE PCMISSES */ -#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ -#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ -#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ - -/* Bit fields for ICACHE PCAHITS */ -#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ -#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ -#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ - -/* Bit fields for ICACHE STATUS */ -#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ -#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ -#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ -#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ -#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ - -/* Bit fields for ICACHE CMD */ -#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ -#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ -#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ -#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ -#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ -#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ -#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ -#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ -#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ - -/* Bit fields for ICACHE LPMODE */ -#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ -#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ -#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ -#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ -#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ -#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ - -/* Bit fields for ICACHE IF */ -#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ -#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ -#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ -#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ -#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ -#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ -#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ - -/* Bit fields for ICACHE IEN */ -#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ -#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ -#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ -#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ -#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ -#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ -#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ -#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ -#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ -#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ -#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ - -/** @} End of group EFR32BG22_ICACHE_BitFields */ -/** @} End of group EFR32BG22_ICACHE */ -/** @} End of group Parts */ - -#endif // EFR32BG22_ICACHE_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 ICACHE register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_ICACHE_H +#define EFR32BG22_ICACHE_H +#define ICACHE_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_ICACHE ICACHE + * @{ + * @brief EFR32BG22 ICACHE Register Declaration. + *****************************************************************************/ + +/** ICACHE Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t PCHITS; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LPMODE; /**< Low Power Mode */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t PCHITS_SET; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_SET; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_SET; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LPMODE_SET; /**< Low Power Mode */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t PCHITS_CLR; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_CLR; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_CLR; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LPMODE_CLR; /**< Low Power Mode */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED2[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t PCHITS_TGL; /**< Performance Counter Hits */ + __IM uint32_t PCMISSES_TGL; /**< Performance Counter Misses */ + __IM uint32_t PCAHITS_TGL; /**< Performance Counter Advanced Hits */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LPMODE_TGL; /**< Low Power Mode */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ +} ICACHE_TypeDef; +/** @} End of group EFR32BG22_ICACHE */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_ICACHE + * @{ + * @defgroup EFR32BG22_ICACHE_BitFields ICACHE Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ICACHE IPVERSION */ +#define _ICACHE_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_IPVERSION */ +#define _ICACHE_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IPVERSION */ +#define ICACHE_IPVERSION_IPVERSION_DEFAULT (_ICACHE_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IPVERSION */ + +/* Bit fields for ICACHE CTRL */ +#define _ICACHE_CTRL_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CTRL */ +#define _ICACHE_CTRL_MASK 0x00000007UL /**< Mask for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS (0x1UL << 0) /**< Cache Disable */ +#define _ICACHE_CTRL_CACHEDIS_SHIFT 0 /**< Shift value for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_MASK 0x1UL /**< Bit mask for ICACHE_CACHEDIS */ +#define _ICACHE_CTRL_CACHEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_CACHEDIS_DEFAULT (_ICACHE_CTRL_CACHEDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU (0x1UL << 1) /**< Use MPU */ +#define _ICACHE_CTRL_USEMPU_SHIFT 1 /**< Shift value for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_MASK 0x2UL /**< Bit mask for ICACHE_USEMPU */ +#define _ICACHE_CTRL_USEMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_USEMPU_DEFAULT (_ICACHE_CTRL_USEMPU_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS (0x1UL << 2) /**< Automatic Flushing Disable */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_SHIFT 2 /**< Shift value for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_MASK 0x4UL /**< Bit mask for ICACHE_AUTOFLUSHDIS */ +#define _ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CTRL */ +#define ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT (_ICACHE_CTRL_AUTOFLUSHDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CTRL */ + +/* Bit fields for ICACHE PCHITS */ +#define _ICACHE_PCHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_SHIFT 0 /**< Shift value for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCHITS */ +#define _ICACHE_PCHITS_PCHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCHITS */ +#define ICACHE_PCHITS_PCHITS_DEFAULT (_ICACHE_PCHITS_PCHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCHITS */ + +/* Bit fields for ICACHE PCMISSES */ +#define _ICACHE_PCMISSES_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_SHIFT 0 /**< Shift value for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCMISSES */ +#define _ICACHE_PCMISSES_PCMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCMISSES */ +#define ICACHE_PCMISSES_PCMISSES_DEFAULT (_ICACHE_PCMISSES_PCMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCMISSES */ + +/* Bit fields for ICACHE PCAHITS */ +#define _ICACHE_PCAHITS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_MASK 0xFFFFFFFFUL /**< Mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_SHIFT 0 /**< Shift value for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_MASK 0xFFFFFFFFUL /**< Bit mask for ICACHE_PCAHITS */ +#define _ICACHE_PCAHITS_PCAHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_PCAHITS */ +#define ICACHE_PCAHITS_PCAHITS_DEFAULT (_ICACHE_PCAHITS_PCAHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_PCAHITS */ + +/* Bit fields for ICACHE STATUS */ +#define _ICACHE_STATUS_RESETVALUE 0x00000000UL /**< Default value for ICACHE_STATUS */ +#define _ICACHE_STATUS_MASK 0x00000001UL /**< Mask for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING (0x1UL << 0) /**< PC Running */ +#define _ICACHE_STATUS_PCRUNNING_SHIFT 0 /**< Shift value for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_MASK 0x1UL /**< Bit mask for ICACHE_PCRUNNING */ +#define _ICACHE_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_STATUS */ +#define ICACHE_STATUS_PCRUNNING_DEFAULT (_ICACHE_STATUS_PCRUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_STATUS */ + +/* Bit fields for ICACHE CMD */ +#define _ICACHE_CMD_RESETVALUE 0x00000000UL /**< Default value for ICACHE_CMD */ +#define _ICACHE_CMD_MASK 0x00000007UL /**< Mask for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH (0x1UL << 0) /**< Flush */ +#define _ICACHE_CMD_FLUSH_SHIFT 0 /**< Shift value for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_MASK 0x1UL /**< Bit mask for ICACHE_FLUSH */ +#define _ICACHE_CMD_FLUSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_FLUSH_DEFAULT (_ICACHE_CMD_FLUSH_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */ +#define _ICACHE_CMD_STARTPC_SHIFT 1 /**< Shift value for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_MASK 0x2UL /**< Bit mask for ICACHE_STARTPC */ +#define _ICACHE_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STARTPC_DEFAULT (_ICACHE_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */ +#define _ICACHE_CMD_STOPPC_SHIFT 2 /**< Shift value for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_MASK 0x4UL /**< Bit mask for ICACHE_STOPPC */ +#define _ICACHE_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_CMD */ +#define ICACHE_CMD_STOPPC_DEFAULT (_ICACHE_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_CMD */ + +/* Bit fields for ICACHE LPMODE */ +#define _ICACHE_LPMODE_RESETVALUE 0x00000023UL /**< Default value for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_MASK 0x000000F3UL /**< Mask for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_SHIFT 0 /**< Shift value for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_MASK 0x3UL /**< Bit mask for ICACHE_LPLEVEL */ +#define _ICACHE_LPMODE_LPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_BASIC 0x00000000UL /**< Mode BASIC for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_LPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_DEFAULT (_ICACHE_LPMODE_LPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_BASIC (_ICACHE_LPMODE_LPLEVEL_BASIC << 0) /**< Shifted mode BASIC for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_ADVANCED (_ICACHE_LPMODE_LPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for ICACHE_LPMODE */ +#define ICACHE_LPMODE_LPLEVEL_MINACTIVITY (_ICACHE_LPMODE_LPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for ICACHE_LPMODE */ +#define _ICACHE_LPMODE_NESTFACTOR_SHIFT 4 /**< Shift value for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_MASK 0xF0UL /**< Bit mask for ICACHE_NESTFACTOR */ +#define _ICACHE_LPMODE_NESTFACTOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for ICACHE_LPMODE */ +#define ICACHE_LPMODE_NESTFACTOR_DEFAULT (_ICACHE_LPMODE_NESTFACTOR_DEFAULT << 4) /**< Shifted mode DEFAULT for ICACHE_LPMODE */ + +/* Bit fields for ICACHE IF */ +#define _ICACHE_IF_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IF */ +#define _ICACHE_IF_MASK 0x00000107UL /**< Mask for ICACHE_IF */ +#define ICACHE_IF_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IF_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_HITOF_DEFAULT (_ICACHE_IF_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Flag */ +#define _ICACHE_IF_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IF_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_MISSOF_DEFAULT (_ICACHE_IF_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Flag */ +#define _ICACHE_IF_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IF_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_AHITOF_DEFAULT (_ICACHE_IF_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Flag */ +#define _ICACHE_IF_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IF_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IF */ +#define ICACHE_IF_RAMERROR_DEFAULT (_ICACHE_IF_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IF */ + +/* Bit fields for ICACHE IEN */ +#define _ICACHE_IEN_RESETVALUE 0x00000000UL /**< Default value for ICACHE_IEN */ +#define _ICACHE_IEN_MASK 0x00000107UL /**< Mask for ICACHE_IEN */ +#define ICACHE_IEN_HITOF (0x1UL << 0) /**< Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_HITOF_SHIFT 0 /**< Shift value for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_MASK 0x1UL /**< Bit mask for ICACHE_HITOF */ +#define _ICACHE_IEN_HITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_HITOF_DEFAULT (_ICACHE_IEN_HITOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF (0x1UL << 1) /**< Miss Overflow Interrupt Enable */ +#define _ICACHE_IEN_MISSOF_SHIFT 1 /**< Shift value for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_MASK 0x2UL /**< Bit mask for ICACHE_MISSOF */ +#define _ICACHE_IEN_MISSOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_MISSOF_DEFAULT (_ICACHE_IEN_MISSOF_DEFAULT << 1) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF (0x1UL << 2) /**< Advanced Hit Overflow Interrupt Enable */ +#define _ICACHE_IEN_AHITOF_SHIFT 2 /**< Shift value for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_MASK 0x4UL /**< Bit mask for ICACHE_AHITOF */ +#define _ICACHE_IEN_AHITOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_AHITOF_DEFAULT (_ICACHE_IEN_AHITOF_DEFAULT << 2) /**< Shifted mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR (0x1UL << 8) /**< RAM error Interrupt Enable */ +#define _ICACHE_IEN_RAMERROR_SHIFT 8 /**< Shift value for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_MASK 0x100UL /**< Bit mask for ICACHE_RAMERROR */ +#define _ICACHE_IEN_RAMERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ICACHE_IEN */ +#define ICACHE_IEN_RAMERROR_DEFAULT (_ICACHE_IEN_RAMERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for ICACHE_IEN */ + +/** @} End of group EFR32BG22_ICACHE_BitFields */ +/** @} End of group EFR32BG22_ICACHE */ +/** @} End of group Parts */ + +#endif // EFR32BG22_ICACHE_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h index 2a45b78..13a6bb0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldma.h @@ -1,685 +1,685 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LDMA register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LDMA_H -#define EFR32BG22_LDMA_H -#define LDMA_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_LDMA LDMA - * @{ - * @brief EFR32BG22 LDMA Register Declaration. - *****************************************************************************/ - -/** LDMA CH Register Group Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t CFG; /**< Channel Configuration Register */ - __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ - __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ - __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ - __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ - __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ - uint32_t RESERVED1[5U]; /**< Reserved for future use */ -} LDMA_CH_TypeDef; - -/** LDMA Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL; /**< DMA Control Register */ - __IM uint32_t STATUS; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_SET; /**< DMA Control Register */ - __IM uint32_t STATUS_SET; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ - __IM uint32_t STATUS_CLR; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[906U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ - __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ - __IM uint32_t STATUS_TGL; /**< DMA Status Register */ - __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ - __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ - __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ - __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ - __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ - __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ - __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ - __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ - __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ - __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ - __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ - __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ - __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ - __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ - __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ - __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ -} LDMA_TypeDef; -/** @} End of group EFR32BG22_LDMA */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_LDMA - * @{ - * @defgroup EFR32BG22_LDMA_BitFields LDMA Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LDMA IPVERSION */ -#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ -#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ -#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ - -/* Bit fields for LDMA EN */ -#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ -#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ -#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ -#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ -#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ -#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ -#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ - -/* Bit fields for LDMA CTRL */ -#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ -#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ -#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ -#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ -#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ -#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ -#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ -#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ -#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ - -/* Bit fields for LDMA STATUS */ -#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ -#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ -#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ -#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ -#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ -#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ -#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ -#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ -#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ -#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ -#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ -#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ -#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ -#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ -#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ -#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ -#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ -#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ -#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ - -/* Bit fields for LDMA SYNCSWSET */ -#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ -#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ -#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ - -/* Bit fields for LDMA SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ -#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ -#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ - -/* Bit fields for LDMA SYNCHWEN */ -#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ -#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ -#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ -#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ - -/* Bit fields for LDMA SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ -#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ -#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ - -/* Bit fields for LDMA SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ -#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ -#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ - -/* Bit fields for LDMA CHEN */ -#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ -#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ -#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ -#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ - -/* Bit fields for LDMA CHDIS */ -#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ -#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ -#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ -#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ - -/* Bit fields for LDMA CHSTATUS */ -#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ -#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ -#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ - -/* Bit fields for LDMA CHBUSY */ -#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ -#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ -#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ -#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ -#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ -#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ - -/* Bit fields for LDMA CHDONE */ -#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ -#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ -#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ -#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ -#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ -#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ -#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ -#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ -#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ -#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ -#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ -#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ -#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ -#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ -#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ -#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ -#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ -#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ -#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ -#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ - -/* Bit fields for LDMA DBGHALT */ -#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ -#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ -#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ - -/* Bit fields for LDMA SWREQ */ -#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ -#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ -#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ -#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ - -/* Bit fields for LDMA REQDIS */ -#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ -#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ -#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ -#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ - -/* Bit fields for LDMA REQPEND */ -#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ -#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ -#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ -#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ - -/* Bit fields for LDMA LINKLOAD */ -#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ -#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ -#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ - -/* Bit fields for LDMA REQCLEAR */ -#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ -#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ -#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ - -/* Bit fields for LDMA IF */ -#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ -#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ -#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ -#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ -#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ -#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ -#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ -#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ -#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ -#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ -#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ -#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ -#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ -#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ -#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ -#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ -#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ -#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ -#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ -#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ -#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ -#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ -#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ -#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ -#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ - -/* Bit fields for LDMA IEN */ -#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ -#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ -#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ -#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ -#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ -#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ -#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ -#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ -#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ - -/* Bit fields for LDMA CH_CFG */ -#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ -#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ -#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ -#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ -#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ -#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ -#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ -#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ -#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ - -/* Bit fields for LDMA CH_LOOP */ -#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ -#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ -#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ -#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ -#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ -#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ - -/* Bit fields for LDMA CH_CTRL */ -#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ -#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ -#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ -#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ -#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ -#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ -#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ -#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ -#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ -#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ -#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ -#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ -#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ -#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ -#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ -#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ -#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ -#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ -#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ -#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ -#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ -#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ -#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ -#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ -#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ - -/* Bit fields for LDMA CH_SRC */ -#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ -#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ -#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ -#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ -#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ -#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ - -/* Bit fields for LDMA CH_DST */ -#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ -#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ -#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ -#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ -#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ -#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ - -/* Bit fields for LDMA CH_LINK */ -#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ -#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ -#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ -#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ -#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ -#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ -#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ -#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ -#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ -#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ -#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ - -/** @} End of group EFR32BG22_LDMA_BitFields */ -/** @} End of group EFR32BG22_LDMA */ -/** @} End of group Parts */ - -#endif // EFR32BG22_LDMA_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LDMA register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LDMA_H +#define EFR32BG22_LDMA_H +#define LDMA_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_LDMA LDMA + * @{ + * @brief EFR32BG22 LDMA Register Declaration. + *****************************************************************************/ + +/** LDMA CH Register Group Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CFG; /**< Channel Configuration Register */ + __IOM uint32_t LOOP; /**< Channel Loop Counter Register */ + __IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */ + __IOM uint32_t SRC; /**< Channel Descriptor Source Address */ + __IOM uint32_t DST; /**< Channel Descriptor Destination Address */ + __IOM uint32_t LINK; /**< Channel Descriptor Link Address */ + uint32_t RESERVED1[5U]; /**< Reserved for future use */ +} LDMA_CH_TypeDef; + +/** LDMA Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL; /**< DMA Control Register */ + __IM uint32_t STATUS; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_SET; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_SET; /**< DMA Control Register */ + __IM uint32_t STATUS_SET; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_SET; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_SET; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_SET; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_SET; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_SET; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_SET; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_SET; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_SET; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_SET; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_SET; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_SET; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_SET; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_SET; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_SET; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_SET; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_SET; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_CLR; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_CLR; /**< DMA Control Register */ + __IM uint32_t STATUS_CLR; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_CLR; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_CLR; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_CLR; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_CLR; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_CLR; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_CLR; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_CLR; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_CLR; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_CLR; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_CLR; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_CLR; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_CLR; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_CLR; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_CLR; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_CLR; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_CLR; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[906U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t EN_TGL; /**< DMA module enable disable Register */ + __IOM uint32_t CTRL_TGL; /**< DMA Control Register */ + __IM uint32_t STATUS_TGL; /**< DMA Status Register */ + __IOM uint32_t SYNCSWSET_TGL; /**< DMA Sync Trig Sw Set Register */ + __IOM uint32_t SYNCSWCLR_TGL; /**< DMA Sync Trig Sw Clear register */ + __IOM uint32_t SYNCHWEN_TGL; /**< DMA Sync HW trigger enable register */ + __IOM uint32_t SYNCHWSEL_TGL; /**< DMA Sync HW trigger selection register */ + __IM uint32_t SYNCSTATUS_TGL; /**< DMA Sync Trigger Status Register */ + __IOM uint32_t CHEN_TGL; /**< DMA Channel Enable Register */ + __IOM uint32_t CHDIS_TGL; /**< DMA Channel Disable Register */ + __IM uint32_t CHSTATUS_TGL; /**< DMA Channel Status Register */ + __IM uint32_t CHBUSY_TGL; /**< DMA Channel Busy Register */ + __IOM uint32_t CHDONE_TGL; /**< DMA Channel Linking Done Register */ + __IOM uint32_t DBGHALT_TGL; /**< DMA Channel Debug Halt Register */ + __IOM uint32_t SWREQ_TGL; /**< DMA Channel Software Transfer Request */ + __IOM uint32_t REQDIS_TGL; /**< DMA Channel Request Disable Register */ + __IM uint32_t REQPEND_TGL; /**< DMA Channel Requests Pending Register */ + __IOM uint32_t LINKLOAD_TGL; /**< DMA Channel Link Load Register */ + __IOM uint32_t REQCLEAR_TGL; /**< DMA Channel Request Clear Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + LDMA_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMA_TypeDef; +/** @} End of group EFR32BG22_LDMA */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_LDMA + * @{ + * @defgroup EFR32BG22_LDMA_BitFields LDMA Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMA IPVERSION */ +#define _LDMA_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_MASK 0x000000FFUL /**< Mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_MASK 0xFFUL /**< Bit mask for LDMA_IPVERSION */ +#define _LDMA_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IPVERSION */ +#define LDMA_IPVERSION_IPVERSION_DEFAULT (_LDMA_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IPVERSION */ + +/* Bit fields for LDMA EN */ +#define _LDMA_EN_RESETVALUE 0x00000000UL /**< Default value for LDMA_EN */ +#define _LDMA_EN_MASK 0x00000001UL /**< Mask for LDMA_EN */ +#define LDMA_EN_EN (0x1UL << 0) /**< LDMA module enable and disable register */ +#define _LDMA_EN_EN_SHIFT 0 /**< Shift value for LDMA_EN */ +#define _LDMA_EN_EN_MASK 0x1UL /**< Bit mask for LDMA_EN */ +#define _LDMA_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_EN */ +#define LDMA_EN_EN_DEFAULT (_LDMA_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_EN */ + +/* Bit fields for LDMA CTRL */ +#define _LDMA_CTRL_RESETVALUE 0x1E000000UL /**< Default value for LDMA_CTRL */ +#define _LDMA_CTRL_MASK 0x9F000000UL /**< Mask for LDMA_CTRL */ +#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */ +#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x0000001EUL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST (0x1UL << 31) /**< Reset DMA controller */ +#define _LDMA_CTRL_CORERST_SHIFT 31 /**< Shift value for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_MASK 0x80000000UL /**< Bit mask for LDMA_CORERST */ +#define _LDMA_CTRL_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */ +#define LDMA_CTRL_CORERST_DEFAULT (_LDMA_CTRL_CORERST_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CTRL */ + +/* Bit fields for LDMA STATUS */ +#define _LDMA_STATUS_RESETVALUE 0x08100000UL /**< Default value for LDMA_STATUS */ +#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */ +#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */ +#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */ +#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */ +#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */ +#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */ +#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */ +#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */ +#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */ +#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000008UL /**< Mode DEFAULT for LDMA_STATUS */ +#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */ + +/* Bit fields for LDMA SYNCSWSET */ +#define _LDMA_SYNCSWSET_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_SHIFT 0 /**< Shift value for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWSET */ +#define _LDMA_SYNCSWSET_SYNCSWSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWSET */ +#define LDMA_SYNCSWSET_SYNCSWSET_DEFAULT (_LDMA_SYNCSWSET_SYNCSWSET_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWSET */ + +/* Bit fields for LDMA SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_SHIFT 0 /**< Shift value for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSWCLR */ +#define _LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSWCLR */ +#define LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT (_LDMA_SYNCSWCLR_SYNCSWCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSWCLR */ + +/* Bit fields for LDMA SYNCHWEN */ +#define _LDMA_SYNCHWEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEN */ +#define _LDMA_SYNCHWEN_SYNCSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCSETEN_DEFAULT (_LDMA_SYNCHWEN_SYNCSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_SHIFT 16 /**< Shift value for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREN */ +#define _LDMA_SYNCHWEN_SYNCCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWEN */ +#define LDMA_SYNCHWEN_SYNCCLREN_DEFAULT (_LDMA_SYNCHWEN_SYNCCLREN_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWEN */ + +/* Bit fields for LDMA SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_MASK 0x00FF00FFUL /**< Mask for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_SHIFT 0 /**< Shift value for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_MASK 0xFFUL /**< Bit mask for LDMA_SYNCSETEDGE */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCSETEDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCSETEDGE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_RISE (_LDMA_SYNCHWSEL_SYNCSETEDGE_RISE << 0) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCSETEDGE_FALL (_LDMA_SYNCHWSEL_SYNCSETEDGE_FALL << 0) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_SHIFT 16 /**< Shift value for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_MASK 0xFF0000UL /**< Bit mask for LDMA_SYNCCLREDGE */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_RISE 0x00000000UL /**< Mode RISE for LDMA_SYNCHWSEL */ +#define _LDMA_SYNCHWSEL_SYNCCLREDGE_FALL 0x00000001UL /**< Mode FALL for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT (_LDMA_SYNCHWSEL_SYNCCLREDGE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_RISE (_LDMA_SYNCHWSEL_SYNCCLREDGE_RISE << 16) /**< Shifted mode RISE for LDMA_SYNCHWSEL */ +#define LDMA_SYNCHWSEL_SYNCCLREDGE_FALL (_LDMA_SYNCHWSEL_SYNCCLREDGE_FALL << 16) /**< Shifted mode FALL for LDMA_SYNCHWSEL */ + +/* Bit fields for LDMA SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_SYNCSTATUS */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */ +#define _LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNCSTATUS */ +#define LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT (_LDMA_SYNCSTATUS_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNCSTATUS */ + +/* Bit fields for LDMA CHEN */ +#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */ +#define _LDMA_CHEN_MASK 0x000000FFUL /**< Mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_MASK 0xFFUL /**< Bit mask for LDMA_CHEN */ +#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */ +#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */ + +/* Bit fields for LDMA CHDIS */ +#define _LDMA_CHDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDIS */ +#define _LDMA_CHDIS_MASK 0x000000FFUL /**< Mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_SHIFT 0 /**< Shift value for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_MASK 0xFFUL /**< Bit mask for LDMA_CHDIS */ +#define _LDMA_CHDIS_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDIS */ +#define LDMA_CHDIS_CHDIS_DEFAULT (_LDMA_CHDIS_CHDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDIS */ + +/* Bit fields for LDMA CHSTATUS */ +#define _LDMA_CHSTATUS_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_MASK 0x000000FFUL /**< Mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_SHIFT 0 /**< Shift value for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_MASK 0xFFUL /**< Bit mask for LDMA_CHSTATUS */ +#define _LDMA_CHSTATUS_CHSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHSTATUS */ +#define LDMA_CHSTATUS_CHSTATUS_DEFAULT (_LDMA_CHSTATUS_CHSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHSTATUS */ + +/* Bit fields for LDMA CHBUSY */ +#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_MASK 0x000000FFUL /**< Mask for LDMA_CHBUSY */ +#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_MASK 0xFFUL /**< Bit mask for LDMA_BUSY */ +#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */ +#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */ + +/* Bit fields for LDMA CHDONE */ +#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */ +#define _LDMA_CHDONE_MASK 0x000000FFUL /**< Mask for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0 (0x1UL << 0) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE0_SHIFT 0 /**< Shift value for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_MASK 0x1UL /**< Bit mask for LDMA_CHDONE0 */ +#define _LDMA_CHDONE_CHDONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE0_DEFAULT (_LDMA_CHDONE_CHDONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1 (0x1UL << 1) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE1_SHIFT 1 /**< Shift value for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_MASK 0x2UL /**< Bit mask for LDMA_CHDONE1 */ +#define _LDMA_CHDONE_CHDONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE1_DEFAULT (_LDMA_CHDONE_CHDONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2 (0x1UL << 2) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE2_SHIFT 2 /**< Shift value for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_MASK 0x4UL /**< Bit mask for LDMA_CHDONE2 */ +#define _LDMA_CHDONE_CHDONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE2_DEFAULT (_LDMA_CHDONE_CHDONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3 (0x1UL << 3) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE3_SHIFT 3 /**< Shift value for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_MASK 0x8UL /**< Bit mask for LDMA_CHDONE3 */ +#define _LDMA_CHDONE_CHDONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE3_DEFAULT (_LDMA_CHDONE_CHDONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4 (0x1UL << 4) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE4_SHIFT 4 /**< Shift value for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_MASK 0x10UL /**< Bit mask for LDMA_CHDONE4 */ +#define _LDMA_CHDONE_CHDONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE4_DEFAULT (_LDMA_CHDONE_CHDONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5 (0x1UL << 5) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE5_SHIFT 5 /**< Shift value for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_MASK 0x20UL /**< Bit mask for LDMA_CHDONE5 */ +#define _LDMA_CHDONE_CHDONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE5_DEFAULT (_LDMA_CHDONE_CHDONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6 (0x1UL << 6) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE6_SHIFT 6 /**< Shift value for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_MASK 0x40UL /**< Bit mask for LDMA_CHDONE6 */ +#define _LDMA_CHDONE_CHDONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE6_DEFAULT (_LDMA_CHDONE_CHDONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7 (0x1UL << 7) /**< DMA Channel Link done intr flag */ +#define _LDMA_CHDONE_CHDONE7_SHIFT 7 /**< Shift value for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_MASK 0x80UL /**< Bit mask for LDMA_CHDONE7 */ +#define _LDMA_CHDONE_CHDONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */ +#define LDMA_CHDONE_CHDONE7_DEFAULT (_LDMA_CHDONE_CHDONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_CHDONE */ + +/* Bit fields for LDMA DBGHALT */ +#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_MASK 0x000000FFUL /**< Mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFUL /**< Bit mask for LDMA_DBGHALT */ +#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */ +#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */ + +/* Bit fields for LDMA SWREQ */ +#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */ +#define _LDMA_SWREQ_MASK 0x000000FFUL /**< Mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_MASK 0xFFUL /**< Bit mask for LDMA_SWREQ */ +#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */ +#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */ + +/* Bit fields for LDMA REQDIS */ +#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */ +#define _LDMA_REQDIS_MASK 0x000000FFUL /**< Mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_MASK 0xFFUL /**< Bit mask for LDMA_REQDIS */ +#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */ +#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */ + +/* Bit fields for LDMA REQPEND */ +#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */ +#define _LDMA_REQPEND_MASK 0x000000FFUL /**< Mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_MASK 0xFFUL /**< Bit mask for LDMA_REQPEND */ +#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */ +#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */ + +/* Bit fields for LDMA LINKLOAD */ +#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_MASK 0x000000FFUL /**< Mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFUL /**< Bit mask for LDMA_LINKLOAD */ +#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */ +#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */ + +/* Bit fields for LDMA REQCLEAR */ +#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_MASK 0x000000FFUL /**< Mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFUL /**< Bit mask for LDMA_REQCLEAR */ +#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */ +#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */ + +/* Bit fields for LDMA IF */ +#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */ +#define _LDMA_IF_MASK 0x800000FFUL /**< Mask for LDMA_IF */ +#define LDMA_IF_DONE0 (0x1UL << 0) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE0_SHIFT 0 /**< Shift value for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_MASK 0x1UL /**< Bit mask for LDMA_DONE0 */ +#define _LDMA_IF_DONE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE0_DEFAULT (_LDMA_IF_DONE0_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1 (0x1UL << 1) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE1_SHIFT 1 /**< Shift value for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_MASK 0x2UL /**< Bit mask for LDMA_DONE1 */ +#define _LDMA_IF_DONE1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE1_DEFAULT (_LDMA_IF_DONE1_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2 (0x1UL << 2) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE2_SHIFT 2 /**< Shift value for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_MASK 0x4UL /**< Bit mask for LDMA_DONE2 */ +#define _LDMA_IF_DONE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE2_DEFAULT (_LDMA_IF_DONE2_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3 (0x1UL << 3) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE3_SHIFT 3 /**< Shift value for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_MASK 0x8UL /**< Bit mask for LDMA_DONE3 */ +#define _LDMA_IF_DONE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE3_DEFAULT (_LDMA_IF_DONE3_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4 (0x1UL << 4) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE4_SHIFT 4 /**< Shift value for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_MASK 0x10UL /**< Bit mask for LDMA_DONE4 */ +#define _LDMA_IF_DONE4_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE4_DEFAULT (_LDMA_IF_DONE4_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5 (0x1UL << 5) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE5_SHIFT 5 /**< Shift value for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_MASK 0x20UL /**< Bit mask for LDMA_DONE5 */ +#define _LDMA_IF_DONE5_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE5_DEFAULT (_LDMA_IF_DONE5_DEFAULT << 5) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6 (0x1UL << 6) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE6_SHIFT 6 /**< Shift value for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_MASK 0x40UL /**< Bit mask for LDMA_DONE6 */ +#define _LDMA_IF_DONE6_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE6_DEFAULT (_LDMA_IF_DONE6_DEFAULT << 6) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7 (0x1UL << 7) /**< DMA Structure Operation Done */ +#define _LDMA_IF_DONE7_SHIFT 7 /**< Shift value for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_MASK 0x80UL /**< Bit mask for LDMA_DONE7 */ +#define _LDMA_IF_DONE7_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_DONE7_DEFAULT (_LDMA_IF_DONE7_DEFAULT << 7) /**< Shifted mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR (0x1UL << 31) /**< Error Flag */ +#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */ +#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */ + +/* Bit fields for LDMA IEN */ +#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */ +#define _LDMA_IEN_MASK 0x800000FFUL /**< Mask for LDMA_IEN */ +#define _LDMA_IEN_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_MASK 0xFFUL /**< Bit mask for LDMA_CHDONE */ +#define _LDMA_IEN_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_CHDONE_DEFAULT (_LDMA_IEN_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR (0x1UL << 31) /**< Enable or disable the error interrupt */ +#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */ +#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */ +#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */ + +/* Bit fields for LDMA CH_CFG */ +#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */ +#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */ +#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */ +#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */ +#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */ +#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */ +#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */ +#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */ +#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */ + +/* Bit fields for LDMA CH_LOOP */ +#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */ +#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */ +#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */ +#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */ + +/* Bit fields for LDMA CH_CTRL */ +#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */ +#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */ +#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */ +#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */ +#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */ +#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */ +#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */ +#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set En */ +#define _LDMA_CH_CTRL_DONEIEN_SHIFT 20 /**< Shift value for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIEN */ +#define _LDMA_CH_CTRL_DONEIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DONEIEN_DEFAULT (_LDMA_CH_CTRL_DONEIEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */ +#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */ +#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */ +#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */ +#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */ +#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */ +#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */ +#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */ +#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */ +#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */ +#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */ +#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */ +#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */ +#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */ +#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */ +#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */ + +/* Bit fields for LDMA CH_SRC */ +#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */ +#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */ +#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */ +#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */ + +/* Bit fields for LDMA CH_DST */ +#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */ +#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */ +#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */ +#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */ +#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */ + +/* Bit fields for LDMA CH_LINK */ +#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */ +#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */ +#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */ +#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */ +#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ +#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */ +#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */ +#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */ + +/** @} End of group EFR32BG22_LDMA_BitFields */ +/** @} End of group EFR32BG22_LDMA */ +/** @} End of group Parts */ + +#endif // EFR32BG22_LDMA_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h index c9a1a24..4e5c4f2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar.h @@ -1,84 +1,84 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LDMAXBAR register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LDMAXBAR_H -#define EFR32BG22_LDMAXBAR_H -#define LDMAXBAR_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_LDMAXBAR LDMAXBAR - * @{ - * @brief EFR32BG22 LDMAXBAR Register Declaration. - *****************************************************************************/ - -/** LDMAXBAR CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ -} LDMAXBAR_CH_TypeDef; - -/** LDMAXBAR Register Declaration. */ -typedef struct { - LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED0[1016U]; /**< Reserved for future use */ - LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED1[1016U]; /**< Reserved for future use */ - LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ - uint32_t RESERVED2[1016U]; /**< Reserved for future use */ - LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ -} LDMAXBAR_TypeDef; -/** @} End of group EFR32BG22_LDMAXBAR */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_LDMAXBAR - * @{ - * @defgroup EFR32BG22_LDMAXBAR_BitFields LDMAXBAR Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LDMAXBAR CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ - -/** @} End of group EFR32BG22_LDMAXBAR_BitFields */ -/** @} End of group EFR32BG22_LDMAXBAR */ -/** @} End of group Parts */ - -#endif // EFR32BG22_LDMAXBAR_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LDMAXBAR register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LDMAXBAR_H +#define EFR32BG22_LDMAXBAR_H +#define LDMAXBAR_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_LDMAXBAR LDMAXBAR + * @{ + * @brief EFR32BG22 LDMAXBAR Register Declaration. + *****************************************************************************/ + +/** LDMAXBAR CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Reg... */ +} LDMAXBAR_CH_TypeDef; + +/** LDMAXBAR Register Declaration. */ +typedef struct { + LDMAXBAR_CH_TypeDef CH[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED0[1016U]; /**< Reserved for future use */ + LDMAXBAR_CH_TypeDef CH_SET[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED1[1016U]; /**< Reserved for future use */ + LDMAXBAR_CH_TypeDef CH_CLR[8U]; /**< DMA Channel Registers */ + uint32_t RESERVED2[1016U]; /**< Reserved for future use */ + LDMAXBAR_CH_TypeDef CH_TGL[8U]; /**< DMA Channel Registers */ +} LDMAXBAR_TypeDef; +/** @} End of group EFR32BG22_LDMAXBAR */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_LDMAXBAR + * @{ + * @defgroup EFR32BG22_LDMAXBAR_BitFields LDMAXBAR Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LDMAXBAR CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMAXBAR_SIGSEL */ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMAXBAR_SOURCESEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT (_LDMAXBAR_CH_REQSEL_SOURCESEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMAXBAR_CH_REQSEL */ + +/** @} End of group EFR32BG22_LDMAXBAR_BitFields */ +/** @} End of group EFR32BG22_LDMAXBAR */ +/** @} End of group Parts */ + +#endif // EFR32BG22_LDMAXBAR_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h index fe35ebc..2e6809f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ldmaxbar_defines.h @@ -1,155 +1,155 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LDMA XBAR channel request soruce definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LDMAXBAR_DEFINES_H -#define EFR32BG22_LDMAXBAR_DEFINES_H - -// Module source selection indices -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 0x00000005UL /**< Mode USART1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000006UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000007UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000bUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000cUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000dUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000eUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_PDM 0x0000000fUL /**< Mode PDM for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 0x00000010UL /**< Mode EUART0 for LDMAXBAR_CH_REQSEL */ -#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x00000011UL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ - -// Shifted source selection indices -#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) -#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted Mode USART1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_PDM (_LDMAXBAR_CH_REQSEL_SOURCESEL_PDM << 16) /**< Shifted Mode PDM for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 << 16) /**< Shifted Mode EUART0 for LDMAXBAR_CH_REQSEL */ -#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ - -// Module signal selection indices -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /** Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000001UL /** Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL 0x00000002UL /** Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000003UL /** Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000004UL /** Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV 0x00000000UL /** Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL 0x00000000UL /** Mode EUART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL 0x00000001UL /** Mode EUART0TXFL for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ - -// Shifted Module signal selection indices -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /** Shifted Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /** Shifted Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL << 0) /** Shifted Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /** Shifted Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /** Shifted Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV << 0) /** Shifted Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL << 0) /** Shifted Mode EUART0RXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL << 0) /** Shifted Mode EUART0TXFL for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ -#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ - -#endif // EFR32BG22_LDMAXBAR_DEFINES_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LDMA XBAR channel request soruce definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LDMAXBAR_DEFINES_H +#define EFR32BG22_LDMAXBAR_DEFINES_H + +// Module source selection indices +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR 0x00000001UL /**< Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 0x00000002UL /**< Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 0x00000003UL /**< Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 0x00000004UL /**< Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 0x00000005UL /**< Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 0x00000006UL /**< Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 0x00000007UL /**< Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 0x0000000bUL /**< Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_MSC 0x0000000cUL /**< Mode MSC for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 0x0000000dUL /**< Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 0x0000000eUL /**< Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_PDM 0x0000000fUL /**< Mode PDM for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 0x00000010UL /**< Mode EUART0 for LDMAXBAR_CH_REQSEL */ +#define _LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 0x00000011UL /**< Mode TIMER4 for LDMAXBAR_CH_REQSEL */ + +// Shifted source selection indices +#define LDMAXBAR_CH_REQSEL_SOURCESEL_NONE (_LDMAXBAR_CH_REQSEL_SOURCESEL_NONE << 16) +#define LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR (_LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR << 16) /**< Shifted Mode LDMAXBAR for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted Mode TIMER0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted Mode TIMER1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted Mode USART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted Mode USART1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted Mode I2C0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 (_LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted Mode I2C1 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0 << 16) /**< Shifted Mode IADC0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_MSC (_LDMAXBAR_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted Mode MSC for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted Mode TIMER2 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted Mode TIMER3 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_PDM (_LDMAXBAR_CH_REQSEL_SOURCESEL_PDM << 16) /**< Shifted Mode PDM for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 (_LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0 << 16) /**< Shifted Mode EUART0 for LDMAXBAR_CH_REQSEL */ +#define LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 (_LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted Mode TIMER4 for LDMAXBAR_CH_REQSEL */ + +// Module signal selection indices +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 0x00000000UL /** Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 0x00000001UL /** Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000000UL /** Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000001UL /** Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000002UL /** Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000003UL /** Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000000UL /** Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000001UL /** Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000002UL /** Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000003UL /** Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /** Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT 0x00000001UL /** Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL 0x00000002UL /** Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT 0x00000003UL /** Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000004UL /** Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /** Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000001UL /** Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL 0x00000002UL /** Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000003UL /** Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000004UL /** Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /** Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /** Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /** Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /** Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN 0x00000000UL /** Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE 0x00000001UL /** Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /** Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000000UL /** Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000001UL /** Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000002UL /** Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000003UL /** Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000000UL /** Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000001UL /** Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000002UL /** Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000003UL /** Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV 0x00000000UL /** Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL 0x00000000UL /** Mode EUART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL 0x00000001UL /** Mode EUART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000000UL /** Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000001UL /** Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000002UL /** Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define _LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000003UL /** Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +// Shifted Module signal selection indices +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 << 0) /** Shifted Mode LDMAXBARPRSREQ0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 (_LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 << 0) /** Shifted Mode LDMAXBARPRSREQ1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /** Shifted Mode TIMER0CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /** Shifted Mode TIMER0CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /** Shifted Mode TIMER0CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /** Shifted Mode TIMER0UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /** Shifted Mode TIMER1CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /** Shifted Mode TIMER1CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /** Shifted Mode TIMER1CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /** Shifted Mode TIMER1UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /** Shifted Mode USART0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT << 0) /** Shifted Mode USART0RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL << 0) /** Shifted Mode USART0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT << 0) /** Shifted Mode USART0TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /** Shifted Mode USART0TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /** Shifted Mode USART1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /** Shifted Mode USART1RXDATAVRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL << 0) /** Shifted Mode USART1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /** Shifted Mode USART1TXBLRIGHT for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /** Shifted Mode USART1TXEMPTY for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /** Shifted Mode I2C0RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /** Shifted Mode I2C0TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /** Shifted Mode I2C1RXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /** Shifted Mode I2C1TXBL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN << 0) /** Shifted Mode IADC0IADC_SCAN for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE (_LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE << 0) /** Shifted Mode IADC0IADC_SINGLE for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA (_LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA << 0) /** Shifted Mode MSCWDATA for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /** Shifted Mode TIMER2CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /** Shifted Mode TIMER2CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /** Shifted Mode TIMER2CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /** Shifted Mode TIMER2UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /** Shifted Mode TIMER3CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /** Shifted Mode TIMER3CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /** Shifted Mode TIMER3CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /** Shifted Mode TIMER3UFOF for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV (_LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV << 0) /** Shifted Mode PDMRXDATAV for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL << 0) /** Shifted Mode EUART0RXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL (_LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL << 0) /** Shifted Mode EUART0TXFL for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /** Shifted Mode TIMER4CC0 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /** Shifted Mode TIMER4CC1 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /** Shifted Mode TIMER4CC2 for LDMAXBAR_CH_REQSEL**/ +#define LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /** Shifted Mode TIMER4UFOF for LDMAXBAR_CH_REQSEL**/ + +#endif // EFR32BG22_LDMAXBAR_DEFINES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h index b1e0cf0..8f74ba7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_letimer.h @@ -1,496 +1,496 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LETIMER register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LETIMER_H -#define EFR32BG22_LETIMER_H -#define LETIMER_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_LETIMER LETIMER - * @{ - * @brief EFR32BG22 LETIMER Register Declaration. - *****************************************************************************/ - -/** LETIMER Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t EN; /**< module en */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IOM uint32_t COMP0; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1; /**< Compare Value Register 1 */ - __IOM uint32_t TOP; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ - uint32_t RESERVED3[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t EN_SET; /**< module en */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED6[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ - uint32_t RESERVED7[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t EN_CLR; /**< module en */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED10[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ - uint32_t RESERVED11[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t EN_TGL; /**< module en */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ - __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ - __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ - __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ - __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ - __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - uint32_t RESERVED14[3U]; /**< Reserved for future use */ - __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ -} LETIMER_TypeDef; -/** @} End of group EFR32BG22_LETIMER */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_LETIMER - * @{ - * @defgroup EFR32BG22_LETIMER_BitFields LETIMER Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LETIMER IPVERSION */ -#define _LETIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ -#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IPVERSION */ -#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ - -/* Bit fields for LETIMER EN */ -#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ -#define _LETIMER_EN_MASK 0x00000001UL /**< Mask for LETIMER_EN */ -#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ -#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ -#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ -#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ -#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ - -/* Bit fields for LETIMER CTRL */ -#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ -#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ -#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ -#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ -#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ -#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ -#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ -#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ -#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ -#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ -#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ -#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ -#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ -#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ -#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ -#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ -#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ -#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ -#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ -#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ -#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ -#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ - -/* Bit fields for LETIMER CMD */ -#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ -#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ -#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ -#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ -#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ -#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ -#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ -#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ -#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ -#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ - -/* Bit fields for LETIMER STATUS */ -#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ -#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ -#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ -#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ - -/* Bit fields for LETIMER CNT */ -#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ -#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ -#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ - -/* Bit fields for LETIMER COMP0 */ -#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ -#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ - -/* Bit fields for LETIMER COMP1 */ -#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ -#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ - -/* Bit fields for LETIMER TOP */ -#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ -#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ -#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ - -/* Bit fields for LETIMER TOPBUFF */ -#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ -#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ -#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ - -/* Bit fields for LETIMER REP0 */ -#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ -#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ -#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ - -/* Bit fields for LETIMER REP1 */ -#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ -#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ -#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ - -/* Bit fields for LETIMER IF */ -#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ -#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ -#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ -#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ -#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ -#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ -#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ -#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ -#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ - -/* Bit fields for LETIMER IEN */ -#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ -#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ -#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ -#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ -#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ -#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ -#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ -#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ -#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ -#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ -#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ -#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ -#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ - -/* Bit fields for LETIMER SYNCBUSY */ -#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ -#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ -#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ -#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ -#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ -#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ -#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ -#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ -#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ -#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ -#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ -#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ -#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ -#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ -#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ -#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ -#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ - -/* Bit fields for LETIMER PRSMODE */ -#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ -#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ -#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ - -/** @} End of group EFR32BG22_LETIMER_BitFields */ -/** @} End of group EFR32BG22_LETIMER */ -/** @} End of group Parts */ - -#endif // EFR32BG22_LETIMER_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LETIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LETIMER_H +#define EFR32BG22_LETIMER_H +#define LETIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_LETIMER LETIMER + * @{ + * @brief EFR32BG22 LETIMER Register Declaration. + *****************************************************************************/ + +/** LETIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t EN; /**< module en */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IOM uint32_t COMP0; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1; /**< Compare Value Register 1 */ + __IOM uint32_t TOP; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE; /**< PRS Input mode select Register */ + uint32_t RESERVED3[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t EN_SET; /**< module en */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IOM uint32_t COMP0_SET; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_SET; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_SET; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_SET; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_SET; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_SET; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED6[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_SET; /**< PRS Input mode select Register */ + uint32_t RESERVED7[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t EN_CLR; /**< module en */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IOM uint32_t COMP0_CLR; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_CLR; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_CLR; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_CLR; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_CLR; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_CLR; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED10[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_CLR; /**< PRS Input mode select Register */ + uint32_t RESERVED11[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t EN_TGL; /**< module en */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IOM uint32_t COMP0_TGL; /**< Compare Value Register 0 */ + __IOM uint32_t COMP1_TGL; /**< Compare Value Register 1 */ + __IOM uint32_t TOP_TGL; /**< Counter TOP Value Register */ + __IOM uint32_t TOPBUFF_TGL; /**< Buffered Counter TOP Value */ + __IOM uint32_t REP0_TGL; /**< Repeat Counter Register 0 */ + __IOM uint32_t REP1_TGL; /**< Repeat Counter Register 1 */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + uint32_t RESERVED14[3U]; /**< Reserved for future use */ + __IOM uint32_t PRSMODE_TGL; /**< PRS Input mode select Register */ +} LETIMER_TypeDef; +/** @} End of group EFR32BG22_LETIMER */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_LETIMER + * @{ + * @defgroup EFR32BG22_LETIMER_BitFields LETIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LETIMER IPVERSION */ +#define _LETIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LETIMER_IPVERSION */ +#define _LETIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IPVERSION */ +#define LETIMER_IPVERSION_IPVERSION_DEFAULT (_LETIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IPVERSION */ + +/* Bit fields for LETIMER EN */ +#define _LETIMER_EN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_EN */ +#define _LETIMER_EN_MASK 0x00000001UL /**< Mask for LETIMER_EN */ +#define LETIMER_EN_EN (0x1UL << 0) /**< module en */ +#define _LETIMER_EN_EN_SHIFT 0 /**< Shift value for LETIMER_EN */ +#define _LETIMER_EN_EN_MASK 0x1UL /**< Bit mask for LETIMER_EN */ +#define _LETIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_EN */ +#define LETIMER_EN_EN_DEFAULT (_LETIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_EN */ + +/* Bit fields for LETIMER CTRL */ +#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */ +#define _LETIMER_CTRL_MASK 0x000F13FFUL /**< Mask for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */ +#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */ +#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */ +#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */ +#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */ +#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */ +#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */ +#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */ +#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */ +#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */ +#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */ +#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */ +#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */ +#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_BUFTOP_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_DISABLE (_LETIMER_CTRL_BUFTOP_DISABLE << 8) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_BUFTOP_ENABLE (_LETIMER_CTRL_BUFTOP_ENABLE << 8) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN (0x1UL << 9) /**< Compare Value 0 Is Top Value */ +#define _LETIMER_CTRL_CNTTOPEN_SHIFT 9 /**< Shift value for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_MASK 0x200UL /**< Bit mask for LETIMER_CNTTOPEN */ +#define _LETIMER_CTRL_CNTTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTTOPEN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DEFAULT (_LETIMER_CTRL_CNTTOPEN_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_DISABLE (_LETIMER_CTRL_CNTTOPEN_DISABLE << 9) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTTOPEN_ENABLE (_LETIMER_CTRL_CNTTOPEN_ENABLE << 9) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */ +#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */ +#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_DISABLE (_LETIMER_CTRL_DEBUGRUN_DISABLE << 12) /**< Shifted mode DISABLE for LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUGRUN_ENABLE (_LETIMER_CTRL_DEBUGRUN_ENABLE << 12) /**< Shifted mode ENABLE for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_SHIFT 16 /**< Shift value for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_MASK 0xF0000UL /**< Bit mask for LETIMER_CNTPRESC */ +#define _LETIMER_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for LETIMER_CTRL */ +#define _LETIMER_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DEFAULT (_LETIMER_CTRL_CNTPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV1 (_LETIMER_CTRL_CNTPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV2 (_LETIMER_CTRL_CNTPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV4 (_LETIMER_CTRL_CNTPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV8 (_LETIMER_CTRL_CNTPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV16 (_LETIMER_CTRL_CNTPRESC_DIV16 << 16) /**< Shifted mode DIV16 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV32 (_LETIMER_CTRL_CNTPRESC_DIV32 << 16) /**< Shifted mode DIV32 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV64 (_LETIMER_CTRL_CNTPRESC_DIV64 << 16) /**< Shifted mode DIV64 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV128 (_LETIMER_CTRL_CNTPRESC_DIV128 << 16) /**< Shifted mode DIV128 for LETIMER_CTRL */ +#define LETIMER_CTRL_CNTPRESC_DIV256 (_LETIMER_CTRL_CNTPRESC_DIV256 << 16) /**< Shifted mode DIV256 for LETIMER_CTRL */ + +/* Bit fields for LETIMER CMD */ +#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */ +#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */ +#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */ +#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */ +#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */ +#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */ +#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */ +#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */ +#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */ +#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */ + +/* Bit fields for LETIMER STATUS */ +#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */ +#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */ +#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */ +#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */ + +/* Bit fields for LETIMER CNT */ +#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */ +#define _LETIMER_CNT_MASK 0x00FFFFFFUL /**< Mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */ +#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */ + +/* Bit fields for LETIMER COMP0 */ +#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */ +#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */ + +/* Bit fields for LETIMER COMP1 */ +#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_MASK 0x00FFFFFFUL /**< Mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */ +#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */ + +/* Bit fields for LETIMER TOP */ +#define _LETIMER_TOP_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOP */ +#define _LETIMER_TOP_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_SHIFT 0 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_TOP_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOP */ +#define LETIMER_TOP_TOP_DEFAULT (_LETIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOP */ + +/* Bit fields for LETIMER TOPBUFF */ +#define _LETIMER_TOPBUFF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_MASK 0x00FFFFFFUL /**< Mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_SHIFT 0 /**< Shift value for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_MASK 0xFFFFFFUL /**< Bit mask for LETIMER_TOPBUFF */ +#define _LETIMER_TOPBUFF_TOPBUFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_TOPBUFF */ +#define LETIMER_TOPBUFF_TOPBUFF_DEFAULT (_LETIMER_TOPBUFF_TOPBUFF_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_TOPBUFF */ + +/* Bit fields for LETIMER REP0 */ +#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */ +#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */ +#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */ + +/* Bit fields for LETIMER REP1 */ +#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */ +#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */ +#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */ + +/* Bit fields for LETIMER IF */ +#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */ +#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */ +#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */ +#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */ +#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */ +#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */ +#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */ +#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */ +#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */ + +/* Bit fields for LETIMER IEN */ +#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */ +#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */ +#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Enable */ +#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */ +#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Enable */ +#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */ +#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF (0x1UL << 2) /**< Underflow Interrupt Enable */ +#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */ +#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */ +#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Enable */ +#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Enable */ +#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */ +#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */ + +/* Bit fields for LETIMER SYNCBUSY */ +#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */ +#define _LETIMER_SYNCBUSY_MASK 0x000003FDUL /**< Mask for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT (0x1UL << 0) /**< Sync busy for CNT */ +#define _LETIMER_SYNCBUSY_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_MASK 0x1UL /**< Bit mask for LETIMER_CNT */ +#define _LETIMER_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CNT_DEFAULT (_LETIMER_SYNCBUSY_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP (0x1UL << 2) /**< Sync busy for TOP */ +#define _LETIMER_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for LETIMER_TOP */ +#define _LETIMER_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_TOP_DEFAULT (_LETIMER_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0 (0x1UL << 3) /**< Sync busy for REP0 */ +#define _LETIMER_SYNCBUSY_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */ +#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (0x1UL << 4) /**< Sync busy for REP1 */ +#define _LETIMER_SYNCBUSY_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */ +#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START (0x1UL << 5) /**< Sync busy for START */ +#define _LETIMER_SYNCBUSY_START_SHIFT 5 /**< Shift value for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_MASK 0x20UL /**< Bit mask for LETIMER_START */ +#define _LETIMER_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_START_DEFAULT (_LETIMER_SYNCBUSY_START_DEFAULT << 5) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP (0x1UL << 6) /**< Sync busy for STOP */ +#define _LETIMER_SYNCBUSY_STOP_SHIFT 6 /**< Shift value for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_MASK 0x40UL /**< Bit mask for LETIMER_STOP */ +#define _LETIMER_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_STOP_DEFAULT (_LETIMER_SYNCBUSY_STOP_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR (0x1UL << 7) /**< Sync busy for CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_SHIFT 7 /**< Shift value for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_MASK 0x80UL /**< Bit mask for LETIMER_CLEAR */ +#define _LETIMER_SYNCBUSY_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CLEAR_DEFAULT (_LETIMER_SYNCBUSY_CLEAR_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0 (0x1UL << 8) /**< Sync busy for CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_SHIFT 8 /**< Shift value for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_MASK 0x100UL /**< Bit mask for LETIMER_CTO0 */ +#define _LETIMER_SYNCBUSY_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO0_DEFAULT (_LETIMER_SYNCBUSY_CTO0_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1 (0x1UL << 9) /**< Sync busy for CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_SHIFT 9 /**< Shift value for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_MASK 0x200UL /**< Bit mask for LETIMER_CTO1 */ +#define _LETIMER_SYNCBUSY_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_CTO1_DEFAULT (_LETIMER_SYNCBUSY_CTO1_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */ + +/* Bit fields for LETIMER PRSMODE */ +#define _LETIMER_PRSMODE_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_MASK 0x0CCC0000UL /**< Mask for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_NONE (_LETIMER_PRSMODE_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_RISING (_LETIMER_PRSMODE_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_FALLING (_LETIMER_PRSMODE_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTARTMODE_BOTH (_LETIMER_PRSMODE_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT (_LETIMER_PRSMODE_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_NONE (_LETIMER_PRSMODE_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_RISING (_LETIMER_PRSMODE_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_FALLING (_LETIMER_PRSMODE_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSSTOPMODE_BOTH (_LETIMER_PRSMODE_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSMODE */ +#define _LETIMER_PRSMODE_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT (_LETIMER_PRSMODE_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_NONE (_LETIMER_PRSMODE_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_RISING (_LETIMER_PRSMODE_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_FALLING (_LETIMER_PRSMODE_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSMODE */ +#define LETIMER_PRSMODE_PRSCLEARMODE_BOTH (_LETIMER_PRSMODE_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSMODE */ + +/** @} End of group EFR32BG22_LETIMER_BitFields */ +/** @} End of group EFR32BG22_LETIMER */ +/** @} End of group Parts */ + +#endif // EFR32BG22_LETIMER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h index 6da2e7f..cad5310 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfrco.h @@ -1,304 +1,304 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LFRCO_H -#define EFR32BG22_LFRCO_H -#define LFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_LFRCO LFRCO - * @{ - * @brief EFR32BG22 LFRCO Register Declaration. - *****************************************************************************/ - -/** LFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - __IOM uint32_t CTRL; /**< Control Register */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED3[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED7[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED11[1010U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED12[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ - __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ -} LFRCO_TypeDef; -/** @} End of group EFR32BG22_LFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_LFRCO - * @{ - * @defgroup EFR32BG22_LFRCO_BitFields LFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LFRCO IPVERSION */ -#define _LFRCO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ -#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LFRCO_IPVERSION */ -#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ - -/* Bit fields for LFRCO CTRL */ -#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ -#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ -#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ -#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ -#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ -#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ -#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ -#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ -#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ -#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ - -/* Bit fields for LFRCO STATUS */ -#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ -#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ -#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ -#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ -#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ -#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ -#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ -#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ - -/* Bit fields for LFRCO IF */ -#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ -#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ -#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ -#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ -#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ -#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ -#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ -#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ -#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ -#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ -#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ -#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ -#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ -#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ -#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ -#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ -#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ -#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ -#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ -#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ -#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ -#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ -#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ -#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ -#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ - -/* Bit fields for LFRCO IEN */ -#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ -#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ -#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ -#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ -#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ -#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ -#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ -#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ -#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ -#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ -#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ -#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ -#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ -#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ -#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ -#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ -#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ -#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ -#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ -#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ -#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ -#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ -#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ -#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ -#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ -#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ -#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ -#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ - -/* Bit fields for LFRCO LOCK */ -#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ -#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ -#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ -#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ -#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ - -/* Bit fields for LFRCO CFG */ -#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ -#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ -#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ -#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ -#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ -#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ -#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ - -/* Bit fields for LFRCO NOMCAL */ -#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ -#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ -#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ -#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ -#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ -#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ - -/* Bit fields for LFRCO NOMCALINV */ -#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ -#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ -#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ -#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ - -/* Bit fields for LFRCO CMD */ -#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ -#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ -#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ -#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ -#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ -#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ -#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ - -/** @} End of group EFR32BG22_LFRCO_BitFields */ -/** @} End of group EFR32BG22_LFRCO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_LFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LFRCO_H +#define EFR32BG22_LFRCO_H +#define LFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_LFRCO LFRCO + * @{ + * @brief EFR32BG22 LFRCO Register Declaration. + *****************************************************************************/ + +/** LFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + __IOM uint32_t CTRL; /**< Control Register */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED3[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED7[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED11[1010U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */ + __IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ +} LFRCO_TypeDef; +/** @} End of group EFR32BG22_LFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_LFRCO + * @{ + * @defgroup EFR32BG22_LFRCO_BitFields LFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFRCO IPVERSION */ +#define _LFRCO_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */ +#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for LFRCO_IPVERSION */ +#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */ + +/* Bit fields for LFRCO CTRL */ +#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */ +#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */ +#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */ +#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */ +#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */ +#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */ +#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */ + +/* Bit fields for LFRCO STATUS */ +#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */ +#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */ +#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */ +#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */ +#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */ +#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */ +#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */ +#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */ + +/* Bit fields for LFRCO IF */ +#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */ +#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */ +#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */ +#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */ +#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */ +#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */ +#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */ +#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */ +#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */ +#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */ +#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */ +#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */ +#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */ + +/* Bit fields for LFRCO IEN */ +#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */ +#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */ +#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */ +#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */ +#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */ +#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */ +#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */ +#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */ +#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */ +#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */ +#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */ +#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */ +#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */ +#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */ +#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */ +#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */ +#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */ +#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */ +#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */ +#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */ +#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */ +#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */ + +/* Bit fields for LFRCO LOCK */ +#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */ +#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */ +#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */ +#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */ +#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */ + +/* Bit fields for LFRCO CFG */ +#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */ +#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */ +#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */ +#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */ +#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */ + +/* Bit fields for LFRCO NOMCAL */ +#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */ +#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */ +#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */ +#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */ + +/* Bit fields for LFRCO NOMCALINV */ +#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */ +#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */ +#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */ + +/* Bit fields for LFRCO CMD */ +#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */ +#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */ +#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */ +#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */ +#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */ + +/** @} End of group EFR32BG22_LFRCO_BitFields */ +/** @} End of group EFR32BG22_LFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_LFRCO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h index 74f92db..4381a53 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_lfxo.h @@ -1,281 +1,281 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 LFXO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_LFXO_H -#define EFR32BG22_LFXO_H -#define LFXO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_LFXO LFXO - * @{ - * @brief EFR32BG22 LFXO Register Declaration. - *****************************************************************************/ - -/** LFXO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< LFXO IP version */ - __IOM uint32_t CTRL; /**< LFXO Control Register */ - __IOM uint32_t CFG; /**< LFXO Configuration Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< LFXO Status Register */ - __IOM uint32_t CAL; /**< LFXO Calibration Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ - __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ - __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< LFXO Status Register */ - __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ - __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ - __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ - __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ - __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ - __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ - __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ -} LFXO_TypeDef; -/** @} End of group EFR32BG22_LFXO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_LFXO - * @{ - * @defgroup EFR32BG22_LFXO_BitFields LFXO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for LFXO IPVERSION */ -#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ -#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */ -#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ - -/* Bit fields for LFXO CTRL */ -#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ -#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ -#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ -#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ -#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ -#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ -#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ -#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ -#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ -#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ -#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ - -/* Bit fields for LFXO CFG */ -#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ -#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ -#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ -#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ -#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ -#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ -#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ -#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ -#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ -#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ -#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ -#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ -#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ -#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ -#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ -#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ - -/* Bit fields for LFXO STATUS */ -#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ -#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ -#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ -#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ -#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ -#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ -#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ -#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ -#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ -#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ -#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ - -/* Bit fields for LFXO CAL */ -#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */ -#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ -#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ -#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ -#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ -#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */ -#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ - -/* Bit fields for LFXO IF */ -#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ -#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ -#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ -#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ -#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ -#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ -#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ -#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ - -/* Bit fields for LFXO IEN */ -#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ -#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ -#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ -#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ -#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ -#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ -#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ -#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ -#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ -#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ -#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ -#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ -#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ - -/* Bit fields for LFXO SYNCBUSY */ -#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ -#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ -#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ -#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ -#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ - -/* Bit fields for LFXO LOCK */ -#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ -#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ -#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ -#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ -#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ - -/** @} End of group EFR32BG22_LFXO_BitFields */ -/** @} End of group EFR32BG22_LFXO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_LFXO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 LFXO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_LFXO_H +#define EFR32BG22_LFXO_H +#define LFXO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_LFXO LFXO + * @{ + * @brief EFR32BG22 LFXO Register Declaration. + *****************************************************************************/ + +/** LFXO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< LFXO IP version */ + __IOM uint32_t CTRL; /**< LFXO Control Register */ + __IOM uint32_t CFG; /**< LFXO Configuration Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< LFXO Status Register */ + __IOM uint32_t CAL; /**< LFXO Calibration Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ + __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ + __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< LFXO Status Register */ + __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ + __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ + __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ + __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ + __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ + __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ + __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ +} LFXO_TypeDef; +/** @} End of group EFR32BG22_LFXO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_LFXO + * @{ + * @defgroup EFR32BG22_LFXO_BitFields LFXO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for LFXO IPVERSION */ +#define _LFXO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ +#define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IPVERSION */ +#define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ + +/* Bit fields for LFXO CTRL */ +#define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ +#define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ +#define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ +#define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ +#define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ +#define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ +#define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ +#define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ +#define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ +#define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ +#define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ + +/* Bit fields for LFXO CFG */ +#define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ +#define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ +#define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ +#define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ +#define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ +#define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ +#define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ +#define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ +#define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ +#define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ +#define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ +#define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ +#define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ +#define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ +#define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ +#define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ + +/* Bit fields for LFXO STATUS */ +#define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ +#define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ +#define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ +#define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ +#define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ +#define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ +#define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ +#define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ +#define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ +#define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ +#define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ + +/* Bit fields for LFXO CAL */ +#define _LFXO_CAL_RESETVALUE 0x00000200UL /**< Default value for LFXO_CAL */ +#define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ +#define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ +#define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ +#define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ +#define _LFXO_CAL_GAIN_DEFAULT 0x00000002UL /**< Mode DEFAULT for LFXO_CAL */ +#define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ + +/* Bit fields for LFXO IF */ +#define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ +#define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ +#define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ +#define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ +#define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ +#define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ +#define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ +#define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ + +/* Bit fields for LFXO IEN */ +#define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ +#define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ +#define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ +#define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ +#define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ +#define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ +#define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ +#define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ +#define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ +#define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ +#define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ +#define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ +#define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ + +/* Bit fields for LFXO SYNCBUSY */ +#define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ +#define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ +#define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ +#define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ +#define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ + +/* Bit fields for LFXO LOCK */ +#define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ +#define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ +#define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ +#define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ +#define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ + +/** @} End of group EFR32BG22_LFXO_BitFields */ +/** @} End of group EFR32BG22_LFXO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_LFXO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h index a85b8c2..de603c6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_msc.h @@ -1,479 +1,479 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 MSC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_MSC_H -#define EFR32BG22_MSC_H -#define MSC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_MSC MSC - * @{ - * @brief EFR32BG22 MSC Register Declaration. - *****************************************************************************/ - -/** MSC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t READCTRL; /**< Read Control Register */ - __IOM uint32_t WRITECTRL; /**< Write Control Register */ - __IOM uint32_t WRITECMD; /**< Write Command Register */ - __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA; /**< Write Data Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ - uint32_t RESERVED2[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL; /**< Power control register */ - uint32_t RESERVED3[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - uint32_t RESERVED5[4U]; /**< Reserved for future use */ - uint32_t RESERVED6[4U]; /**< Reserved for future use */ - uint32_t RESERVED7[4U]; /**< Reserved for future use */ - uint32_t RESERVED8[4U]; /**< Reserved for future use */ - uint32_t RESERVED9[12U]; /**< Reserved for future use */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - uint32_t RESERVED11[11U]; /**< Reserved for future use */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - uint32_t RESERVED13[907U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IOM uint32_t READCTRL_SET; /**< Read Control Register */ - __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ - __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ - __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_SET; /**< Write Data Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ - uint32_t RESERVED16[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_SET; /**< Power control register */ - uint32_t RESERVED17[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ - uint32_t RESERVED18[2U]; /**< Reserved for future use */ - uint32_t RESERVED19[4U]; /**< Reserved for future use */ - uint32_t RESERVED20[4U]; /**< Reserved for future use */ - uint32_t RESERVED21[4U]; /**< Reserved for future use */ - uint32_t RESERVED22[4U]; /**< Reserved for future use */ - uint32_t RESERVED23[12U]; /**< Reserved for future use */ - uint32_t RESERVED24[1U]; /**< Reserved for future use */ - uint32_t RESERVED25[11U]; /**< Reserved for future use */ - uint32_t RESERVED26[1U]; /**< Reserved for future use */ - uint32_t RESERVED27[907U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED28[1U]; /**< Reserved for future use */ - __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ - __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ - __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ - __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_CLR; /**< Write Data Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED29[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ - uint32_t RESERVED30[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ - uint32_t RESERVED31[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ - uint32_t RESERVED32[2U]; /**< Reserved for future use */ - uint32_t RESERVED33[4U]; /**< Reserved for future use */ - uint32_t RESERVED34[4U]; /**< Reserved for future use */ - uint32_t RESERVED35[4U]; /**< Reserved for future use */ - uint32_t RESERVED36[4U]; /**< Reserved for future use */ - uint32_t RESERVED37[12U]; /**< Reserved for future use */ - uint32_t RESERVED38[1U]; /**< Reserved for future use */ - uint32_t RESERVED39[11U]; /**< Reserved for future use */ - uint32_t RESERVED40[1U]; /**< Reserved for future use */ - uint32_t RESERVED41[907U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED42[1U]; /**< Reserved for future use */ - __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ - __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ - __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ - __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ - __IOM uint32_t WDATA_TGL; /**< Write Data Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - uint32_t RESERVED43[3U]; /**< Reserved for future use */ - __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ - uint32_t RESERVED44[3U]; /**< Reserved for future use */ - __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ - uint32_t RESERVED45[51U]; /**< Reserved for future use */ - __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ - __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ - uint32_t RESERVED46[2U]; /**< Reserved for future use */ - uint32_t RESERVED47[4U]; /**< Reserved for future use */ - uint32_t RESERVED48[4U]; /**< Reserved for future use */ - uint32_t RESERVED49[4U]; /**< Reserved for future use */ - uint32_t RESERVED50[4U]; /**< Reserved for future use */ - uint32_t RESERVED51[12U]; /**< Reserved for future use */ - uint32_t RESERVED52[1U]; /**< Reserved for future use */ - uint32_t RESERVED53[11U]; /**< Reserved for future use */ - uint32_t RESERVED54[1U]; /**< Reserved for future use */ -} MSC_TypeDef; -/** @} End of group EFR32BG22_MSC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_MSC - * @{ - * @defgroup EFR32BG22_MSC_BitFields MSC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for MSC IPVERSION */ -#define _MSC_IPVERSION_RESETVALUE 0x00000008UL /**< Default value for MSC_IPVERSION */ -#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ -#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000008UL /**< Mode DEFAULT for MSC_IPVERSION */ -#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ - -/* Bit fields for MSC READCTRL */ -#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ -#define _MSC_READCTRL_MASK 0x00301002UL /**< Mask for MSC_READCTRL */ -#define MSC_READCTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ -#define _MSC_READCTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ -#define _MSC_READCTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ -#define _MSC_READCTRL_DOUTBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ -#define MSC_READCTRL_DOUTBUFEN_DEFAULT (_MSC_READCTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ -#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ -#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ -#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ -#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ - -/* Bit fields for MSC WRITECTRL */ -#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ -#define _MSC_WRITECTRL_MASK 0x0000000BUL /**< Mask for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ -#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ -#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ -#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ -#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ -#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ -#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ -#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ - -/* Bit fields for MSC WRITECMD */ -#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ -#define _MSC_WRITECMD_MASK 0x00001126UL /**< Mask for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ -#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ -#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ -#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ -#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ -#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ -#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ -#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ -#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ -#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ -#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ - -/* Bit fields for MSC ADDRB */ -#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ -#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ -#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ -#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ - -/* Bit fields for MSC WDATA */ -#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ -#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ -#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ -#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ -#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ -#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ - -/* Bit fields for MSC STATUS */ -#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ -#define _MSC_STATUS_MASK 0xF901007FUL /**< Mask for MSC_STATUS */ -#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ -#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ -#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ -#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ -#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ -#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ -#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ -#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ -#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ -#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ -#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ -#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ -#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ -#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ -#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ -#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ -#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ -#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ -#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ -#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ -#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ -#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ -#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ -#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ -#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ -#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ -#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ -#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ -#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ -#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ - -/* Bit fields for MSC IF */ -#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ -#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ -#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ -#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ -#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ -#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ -#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ -#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ -#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ - -/* Bit fields for MSC IEN */ -#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ -#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ -#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ -#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ -#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ -#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ -#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ -#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ -#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ -#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ -#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ -#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ -#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ -#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ -#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ - -/* Bit fields for MSC USERDATASIZE */ -#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ -#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ -#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ - -/* Bit fields for MSC CMD */ -#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ -#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ -#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ -#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ -#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ -#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ -#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ -#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ - -/* Bit fields for MSC LOCK */ -#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ -#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ -#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ -#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ - -/* Bit fields for MSC MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ -#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ -#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ -#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ -#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ - -/* Bit fields for MSC PWRCTRL */ -#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ -#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ -#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ -#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ -#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ -#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ - -/* Bit fields for MSC PAGELOCK0 */ -#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ -#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ -#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ - -/* Bit fields for MSC PAGELOCK1 */ -#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ -#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ -#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ -#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ - -/** @} End of group EFR32BG22_MSC_BitFields */ -/** @} End of group EFR32BG22_MSC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_MSC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 MSC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_MSC_H +#define EFR32BG22_MSC_H +#define MSC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_MSC MSC + * @{ + * @brief EFR32BG22 MSC Register Declaration. + *****************************************************************************/ + +/** MSC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t READCTRL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL; /**< Write Control Register */ + __IOM uint32_t WRITECMD; /**< Write Command Register */ + __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA; /**< Write Data Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE; /**< User Data Region Size Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD; /**< Mass erase and User data page lock word */ + uint32_t RESERVED2[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL; /**< Power control register */ + uint32_t RESERVED3[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1; /**< Main space page 32-63 lock word */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + uint32_t RESERVED5[4U]; /**< Reserved for future use */ + uint32_t RESERVED6[4U]; /**< Reserved for future use */ + uint32_t RESERVED7[4U]; /**< Reserved for future use */ + uint32_t RESERVED8[4U]; /**< Reserved for future use */ + uint32_t RESERVED9[12U]; /**< Reserved for future use */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + uint32_t RESERVED11[11U]; /**< Reserved for future use */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + uint32_t RESERVED13[907U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IOM uint32_t READCTRL_SET; /**< Read Control Register */ + __IOM uint32_t WRITECTRL_SET; /**< Write Control Register */ + __IOM uint32_t WRITECMD_SET; /**< Write Command Register */ + __IOM uint32_t ADDRB_SET; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_SET; /**< Write Data Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_SET; /**< User Data Region Size Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_SET; /**< Mass erase and User data page lock word */ + uint32_t RESERVED16[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_SET; /**< Power control register */ + uint32_t RESERVED17[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_SET; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_SET; /**< Main space page 32-63 lock word */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + uint32_t RESERVED19[4U]; /**< Reserved for future use */ + uint32_t RESERVED20[4U]; /**< Reserved for future use */ + uint32_t RESERVED21[4U]; /**< Reserved for future use */ + uint32_t RESERVED22[4U]; /**< Reserved for future use */ + uint32_t RESERVED23[12U]; /**< Reserved for future use */ + uint32_t RESERVED24[1U]; /**< Reserved for future use */ + uint32_t RESERVED25[11U]; /**< Reserved for future use */ + uint32_t RESERVED26[1U]; /**< Reserved for future use */ + uint32_t RESERVED27[907U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED28[1U]; /**< Reserved for future use */ + __IOM uint32_t READCTRL_CLR; /**< Read Control Register */ + __IOM uint32_t WRITECTRL_CLR; /**< Write Control Register */ + __IOM uint32_t WRITECMD_CLR; /**< Write Command Register */ + __IOM uint32_t ADDRB_CLR; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_CLR; /**< Write Data Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED29[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_CLR; /**< User Data Region Size Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_CLR; /**< Mass erase and User data page lock word */ + uint32_t RESERVED30[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_CLR; /**< Power control register */ + uint32_t RESERVED31[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_CLR; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_CLR; /**< Main space page 32-63 lock word */ + uint32_t RESERVED32[2U]; /**< Reserved for future use */ + uint32_t RESERVED33[4U]; /**< Reserved for future use */ + uint32_t RESERVED34[4U]; /**< Reserved for future use */ + uint32_t RESERVED35[4U]; /**< Reserved for future use */ + uint32_t RESERVED36[4U]; /**< Reserved for future use */ + uint32_t RESERVED37[12U]; /**< Reserved for future use */ + uint32_t RESERVED38[1U]; /**< Reserved for future use */ + uint32_t RESERVED39[11U]; /**< Reserved for future use */ + uint32_t RESERVED40[1U]; /**< Reserved for future use */ + uint32_t RESERVED41[907U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IOM uint32_t READCTRL_TGL; /**< Read Control Register */ + __IOM uint32_t WRITECTRL_TGL; /**< Write Control Register */ + __IOM uint32_t WRITECMD_TGL; /**< Write Command Register */ + __IOM uint32_t ADDRB_TGL; /**< Page Erase/Write Address Buffer */ + __IOM uint32_t WDATA_TGL; /**< Write Data Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + uint32_t RESERVED43[3U]; /**< Reserved for future use */ + __IM uint32_t USERDATASIZE_TGL; /**< User Data Region Size Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + __IOM uint32_t MISCLOCKWORD_TGL; /**< Mass erase and User data page lock word */ + uint32_t RESERVED44[3U]; /**< Reserved for future use */ + __IOM uint32_t PWRCTRL_TGL; /**< Power control register */ + uint32_t RESERVED45[51U]; /**< Reserved for future use */ + __IOM uint32_t PAGELOCK0_TGL; /**< Main space page 0-31 lock word */ + __IOM uint32_t PAGELOCK1_TGL; /**< Main space page 32-63 lock word */ + uint32_t RESERVED46[2U]; /**< Reserved for future use */ + uint32_t RESERVED47[4U]; /**< Reserved for future use */ + uint32_t RESERVED48[4U]; /**< Reserved for future use */ + uint32_t RESERVED49[4U]; /**< Reserved for future use */ + uint32_t RESERVED50[4U]; /**< Reserved for future use */ + uint32_t RESERVED51[12U]; /**< Reserved for future use */ + uint32_t RESERVED52[1U]; /**< Reserved for future use */ + uint32_t RESERVED53[11U]; /**< Reserved for future use */ + uint32_t RESERVED54[1U]; /**< Reserved for future use */ +} MSC_TypeDef; +/** @} End of group EFR32BG22_MSC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_MSC + * @{ + * @defgroup EFR32BG22_MSC_BitFields MSC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for MSC IPVERSION */ +#define _MSC_IPVERSION_RESETVALUE 0x00000008UL /**< Default value for MSC_IPVERSION */ +#define _MSC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_IPVERSION */ +#define _MSC_IPVERSION_IPVERSION_DEFAULT 0x00000008UL /**< Mode DEFAULT for MSC_IPVERSION */ +#define MSC_IPVERSION_IPVERSION_DEFAULT (_MSC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IPVERSION */ + +/* Bit fields for MSC READCTRL */ +#define _MSC_READCTRL_RESETVALUE 0x00200000UL /**< Default value for MSC_READCTRL */ +#define _MSC_READCTRL_MASK 0x00301002UL /**< Mask for MSC_READCTRL */ +#define MSC_READCTRL_DOUTBUFEN (0x1UL << 12) /**< Flash dout pipeline buffer enable */ +#define _MSC_READCTRL_DOUTBUFEN_SHIFT 12 /**< Shift value for MSC_DOUTBUFEN */ +#define _MSC_READCTRL_DOUTBUFEN_MASK 0x1000UL /**< Bit mask for MSC_DOUTBUFEN */ +#define _MSC_READCTRL_DOUTBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_DOUTBUFEN_DEFAULT (_MSC_READCTRL_DOUTBUFEN_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_SHIFT 20 /**< Shift value for MSC_MODE */ +#define _MSC_READCTRL_MODE_MASK 0x300000UL /**< Bit mask for MSC_MODE */ +#define _MSC_READCTRL_MODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */ +#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 20) /**< Shifted mode DEFAULT for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 20) /**< Shifted mode WS0 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 20) /**< Shifted mode WS1 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 20) /**< Shifted mode WS2 for MSC_READCTRL */ +#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 20) /**< Shifted mode WS3 for MSC_READCTRL */ + +/* Bit fields for MSC WRITECTRL */ +#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */ +#define _MSC_WRITECTRL_MASK 0x0000000BUL /**< Mask for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */ +#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */ +#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */ +#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */ +#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE (0x1UL << 3) /**< Low-Power Write */ +#define _MSC_WRITECTRL_LPWRITE_SHIFT 3 /**< Shift value for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_MASK 0x8UL /**< Bit mask for MSC_LPWRITE */ +#define _MSC_WRITECTRL_LPWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */ +#define MSC_WRITECTRL_LPWRITE_DEFAULT (_MSC_WRITECTRL_LPWRITE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECTRL */ + +/* Bit fields for MSC WRITECMD */ +#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */ +#define _MSC_WRITECMD_MASK 0x00001126UL /**< Mask for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */ +#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */ +#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */ +#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */ +#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */ +#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */ +#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */ +#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */ +#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */ +#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */ +#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */ + +/* Bit fields for MSC ADDRB */ +#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */ +#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */ +#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */ +#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */ + +/* Bit fields for MSC WDATA */ +#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */ +#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */ +#define _MSC_WDATA_DATAW_SHIFT 0 /**< Shift value for MSC_DATAW */ +#define _MSC_WDATA_DATAW_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_DATAW */ +#define _MSC_WDATA_DATAW_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */ +#define MSC_WDATA_DATAW_DEFAULT (_MSC_WDATA_DATAW_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */ + +/* Bit fields for MSC STATUS */ +#define _MSC_STATUS_RESETVALUE 0x08000008UL /**< Default value for MSC_STATUS */ +#define _MSC_STATUS_MASK 0xF901007FUL /**< Mask for MSC_STATUS */ +#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */ +#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */ +#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */ +#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */ +#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */ +#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */ +#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */ +#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */ +#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */ +#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED (0x1UL << 4) /**< Erase Operation Aborted */ +#define _MSC_STATUS_ERASEABORTED_SHIFT 4 /**< Shift value for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_MASK 0x10UL /**< Bit mask for MSC_ERASEABORTED */ +#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING (0x1UL << 5) /**< Write Command In Queue */ +#define _MSC_STATUS_PENDING_SHIFT 5 /**< Shift value for MSC_PENDING */ +#define _MSC_STATUS_PENDING_MASK 0x20UL /**< Bit mask for MSC_PENDING */ +#define _MSC_STATUS_PENDING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PENDING_DEFAULT (_MSC_STATUS_PENDING_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT (0x1UL << 6) /**< Write Command Timeout */ +#define _MSC_STATUS_TIMEOUT_SHIFT 6 /**< Shift value for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_MASK 0x40UL /**< Bit mask for MSC_TIMEOUT */ +#define _MSC_STATUS_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_TIMEOUT_DEFAULT (_MSC_STATUS_TIMEOUT_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK (0x1UL << 16) /**< Register Lock Status */ +#define _MSC_STATUS_REGLOCK_SHIFT 16 /**< Shift value for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_MASK 0x10000UL /**< Bit mask for MSC_REGLOCK */ +#define _MSC_STATUS_REGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_STATUS */ +#define _MSC_STATUS_REGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_DEFAULT (_MSC_STATUS_REGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_UNLOCKED (_MSC_STATUS_REGLOCK_UNLOCKED << 16) /**< Shifted mode UNLOCKED for MSC_STATUS */ +#define MSC_STATUS_REGLOCK_LOCKED (_MSC_STATUS_REGLOCK_LOCKED << 16) /**< Shifted mode LOCKED for MSC_STATUS */ +#define MSC_STATUS_PWRON (0x1UL << 24) /**< Flash Power On Status */ +#define _MSC_STATUS_PWRON_SHIFT 24 /**< Shift value for MSC_PWRON */ +#define _MSC_STATUS_PWRON_MASK 0x1000000UL /**< Bit mask for MSC_PWRON */ +#define _MSC_STATUS_PWRON_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRON_DEFAULT (_MSC_STATUS_PWRON_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY (0x1UL << 27) /**< Flash Write Ready */ +#define _MSC_STATUS_WREADY_SHIFT 27 /**< Shift value for MSC_WREADY */ +#define _MSC_STATUS_WREADY_MASK 0x8000000UL /**< Bit mask for MSC_WREADY */ +#define _MSC_STATUS_WREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_WREADY_DEFAULT (_MSC_STATUS_WREADY_DEFAULT << 27) /**< Shifted mode DEFAULT for MSC_STATUS */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */ +#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */ +#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */ + +/* Bit fields for MSC IF */ +#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */ +#define _MSC_IF_MASK 0x00000307UL /**< Mask for MSC_IF */ +#define MSC_IF_ERASE (0x1UL << 0) /**< Host Erase Done Interrupt Read Flag */ +#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE (0x1UL << 1) /**< Host Write Done Interrupt Read Flag */ +#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV (0x1UL << 2) /**< Host write buffer overflow */ +#define _MSC_IF_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF (0x1UL << 8) /**< Flash Power Up Sequence Complete Flag */ +#define _MSC_IF_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF (0x1UL << 9) /**< Flash Power Off Sequence Complete Flag */ +#define _MSC_IF_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IF_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IF_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */ +#define MSC_IF_PWROFF_DEFAULT (_MSC_IF_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IF */ + +/* Bit fields for MSC IEN */ +#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */ +#define _MSC_IEN_MASK 0x00000307UL /**< Mask for MSC_IEN */ +#define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt enable */ +#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */ +#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */ +#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt enable */ +#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */ +#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */ +#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV (0x1UL << 2) /**< write data buffer overflow irq enable */ +#define _MSC_IEN_WDATAOV_SHIFT 2 /**< Shift value for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_MASK 0x4UL /**< Bit mask for MSC_WDATAOV */ +#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF (0x1UL << 8) /**< Flash Power Up Seq done irq enable */ +#define _MSC_IEN_PWRUPF_SHIFT 8 /**< Shift value for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_MASK 0x100UL /**< Bit mask for MSC_PWRUPF */ +#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF (0x1UL << 9) /**< Flash Power Off Seq done irq enable */ +#define _MSC_IEN_PWROFF_SHIFT 9 /**< Shift value for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_MASK 0x200UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_IEN_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */ +#define MSC_IEN_PWROFF_DEFAULT (_MSC_IEN_PWROFF_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_IEN */ + +/* Bit fields for MSC USERDATASIZE */ +#define _MSC_USERDATASIZE_RESETVALUE 0x00000004UL /**< Default value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_MASK 0x0000003FUL /**< Mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_SHIFT 0 /**< Shift value for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_MASK 0x3FUL /**< Bit mask for MSC_USERDATASIZE */ +#define _MSC_USERDATASIZE_USERDATASIZE_DEFAULT 0x00000004UL /**< Mode DEFAULT for MSC_USERDATASIZE */ +#define MSC_USERDATASIZE_USERDATASIZE_DEFAULT (_MSC_USERDATASIZE_USERDATASIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_USERDATASIZE */ + +/* Bit fields for MSC CMD */ +#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */ +#define _MSC_CMD_MASK 0x00000011UL /**< Mask for MSC_CMD */ +#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */ +#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */ +#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF (0x1UL << 4) /**< Flash power off/sleep command */ +#define _MSC_CMD_PWROFF_SHIFT 4 /**< Shift value for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_MASK 0x10UL /**< Bit mask for MSC_PWROFF */ +#define _MSC_CMD_PWROFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */ +#define MSC_CMD_PWROFF_DEFAULT (_MSC_CMD_PWROFF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CMD */ + +/* Bit fields for MSC LOCK */ +#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */ +#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */ +#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */ +#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */ + +/* Bit fields for MSC MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_RESETVALUE 0x00000011UL /**< Default value for MSC_MISCLOCKWORD */ +#define _MSC_MISCLOCKWORD_MASK 0x00000011UL /**< Mask for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT (0x1UL << 0) /**< Mass Erase Lock */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_SHIFT 0 /**< Shift value for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_MASK 0x1UL /**< Bit mask for MSC_MELOCKBIT */ +#define _MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_MELOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT (0x1UL << 4) /**< User Data Lock */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_SHIFT 4 /**< Shift value for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_MASK 0x10UL /**< Bit mask for MSC_UDLOCKBIT */ +#define _MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MISCLOCKWORD */ +#define MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT (_MSC_MISCLOCKWORD_UDLOCKBIT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_MISCLOCKWORD */ + +/* Bit fields for MSC PWRCTRL */ +#define _MSC_PWRCTRL_RESETVALUE 0x00100002UL /**< Default value for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_MASK 0x00FF0013UL /**< Mask for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY (0x1UL << 0) /**< Power down Flash macro when enter EM1 */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_SHIFT 0 /**< Shift value for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_MASK 0x1UL /**< Bit mask for MSC_PWROFFONEM1ENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1ENTRY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY (0x1UL << 1) /**< Power down Flash macro when enter EM1P */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_SHIFT 1 /**< Shift value for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_MASK 0x2UL /**< Bit mask for MSC_PWROFFONEM1PENTRY */ +#define _MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT (_MSC_PWRCTRL_PWROFFONEM1PENTRY_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN (0x1UL << 4) /**< POWER down flash again in EM1/EM1p */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_SHIFT 4 /**< Shift value for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_MASK 0x10UL /**< Bit mask for MSC_PWROFFENTRYAGAIN */ +#define _MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT (_MSC_PWRCTRL_PWROFFENTRYAGAIN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ +#define _MSC_PWRCTRL_PWROFFDLY_SHIFT 16 /**< Shift value for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_MASK 0xFF0000UL /**< Bit mask for MSC_PWROFFDLY */ +#define _MSC_PWRCTRL_PWROFFDLY_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_PWRCTRL */ +#define MSC_PWRCTRL_PWROFFDLY_DEFAULT (_MSC_PWRCTRL_PWROFFDLY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_PWRCTRL */ + +/* Bit fields for MSC PAGELOCK0 */ +#define _MSC_PAGELOCK0_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK0 */ +#define _MSC_PAGELOCK0_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK0_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK0 */ +#define MSC_PAGELOCK0_LOCKBIT_DEFAULT (_MSC_PAGELOCK0_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK0 */ + +/* Bit fields for MSC PAGELOCK1 */ +#define _MSC_PAGELOCK1_RESETVALUE 0x00000000UL /**< Default value for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_MASK 0xFFFFFFFFUL /**< Mask for MSC_PAGELOCK1 */ +#define _MSC_PAGELOCK1_LOCKBIT_SHIFT 0 /**< Shift value for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_LOCKBIT */ +#define _MSC_PAGELOCK1_LOCKBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_PAGELOCK1 */ +#define MSC_PAGELOCK1_LOCKBIT_DEFAULT (_MSC_PAGELOCK1_LOCKBIT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_PAGELOCK1 */ + +/** @} End of group EFR32BG22_MSC_BitFields */ +/** @} End of group EFR32BG22_MSC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_MSC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h index fa1cb9b..fb71d08 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_pdm.h @@ -1,363 +1,363 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 PDM register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_PDM_H -#define EFR32BG22_PDM_H -#define PDM_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_PDM PDM - * @{ - * @brief EFR32BG22 PDM Register Declaration. - *****************************************************************************/ - -/** PDM Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version ID */ - __IOM uint32_t EN; /**< PDM Module enable Register */ - __IOM uint32_t CTRL; /**< PDM Core Control Register */ - __IOM uint32_t CMD; /**< PDM Core Command Register */ - __IM uint32_t STATUS; /**< PDM Status register */ - __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ - __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t RXDATA; /**< PDM Received Data Register */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Flag Register */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED3[999U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version ID */ - __IOM uint32_t EN_SET; /**< PDM Module enable Register */ - __IOM uint32_t CTRL_SET; /**< PDM Core Control Register */ - __IOM uint32_t CMD_SET; /**< PDM Core Command Register */ - __IM uint32_t STATUS_SET; /**< PDM Status register */ - __IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */ - __IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t RXDATA_SET; /**< PDM Received Data Register */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Flag Register */ - uint32_t RESERVED6[6U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED7[999U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ - __IOM uint32_t EN_CLR; /**< PDM Module enable Register */ - __IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */ - __IOM uint32_t CMD_CLR; /**< PDM Core Command Register */ - __IM uint32_t STATUS_CLR; /**< PDM Status register */ - __IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */ - __IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */ - uint32_t RESERVED10[6U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED11[999U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ - __IOM uint32_t EN_TGL; /**< PDM Module enable Register */ - __IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */ - __IOM uint32_t CMD_TGL; /**< PDM Core Command Register */ - __IM uint32_t STATUS_TGL; /**< PDM Status register */ - __IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */ - __IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */ - uint32_t RESERVED13[7U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */ - uint32_t RESERVED14[6U]; /**< Reserved for future use */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ -} PDM_TypeDef; -/** @} End of group EFR32BG22_PDM */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_PDM - * @{ - * @defgroup EFR32BG22_PDM_BitFields PDM Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for PDM IPVERSION */ -#define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ -#define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ -#define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ -#define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ -#define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ -#define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ - -/* Bit fields for PDM EN */ -#define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ -#define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ -#define PDM_EN_EN (0x1UL << 0) /**< PDM enable */ -#define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ -#define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ -#define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ -#define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ -#define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ -#define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ -#define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ -#define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ - -/* Bit fields for PDM CTRL */ -#define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ -#define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */ -#define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ -#define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ -#define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ -#define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ -#define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ -#define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ -#define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ -#define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ - -/* Bit fields for PDM CMD */ -#define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ -#define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ -#define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ -#define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ -#define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ -#define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ -#define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ -#define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ -#define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ -#define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ -#define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ -#define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ -#define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ -#define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ -#define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ -#define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ -#define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ -#define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ -#define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ -#define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ -#define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ -#define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ - -/* Bit fields for PDM STATUS */ -#define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ -#define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ -#define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ -#define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ -#define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ -#define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ -#define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ -#define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ -#define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ -#define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ -#define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ -#define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ -#define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ -#define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ -#define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ -#define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ - -/* Bit fields for PDM CFG0 */ -#define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ -#define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */ -#define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ -#define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ -#define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ -#define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ -#define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ -#define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ -#define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ -#define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ -#define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ -#define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ -#define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */ -#define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ -#define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */ -#define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ -#define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ -#define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ -#define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ -#define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ -#define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ -#define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ -#define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ -#define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ -#define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ -#define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ -#define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ -#define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ -#define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ -#define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ -#define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ -#define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ -#define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ -#define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ -#define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ -#define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ -#define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ -#define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ -#define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ -#define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ -#define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ -#define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ -#define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ -#define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ -#define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ -#define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ -#define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ -#define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ -#define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ -#define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ -#define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ -#define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ -#define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ -#define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ -#define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ -#define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ - -/* Bit fields for PDM CFG1 */ -#define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ -#define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */ -#define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ -#define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ -#define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ -#define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ -#define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */ -#define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */ -#define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ -#define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */ - -/* Bit fields for PDM RXDATA */ -#define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ -#define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ -#define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ -#define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ -#define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ -#define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ - -/* Bit fields for PDM IF */ -#define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ -#define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ -#define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ -#define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ -#define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ -#define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ -#define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ -#define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ -#define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ -#define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ -#define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ -#define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ -#define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ -#define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ -#define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ -#define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ -#define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ -#define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ -#define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ -#define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ -#define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ -#define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ - -/* Bit fields for PDM IEN */ -#define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ -#define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ -#define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */ -#define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ -#define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ -#define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ -#define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ -#define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */ -#define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ -#define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ -#define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ -#define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ -#define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */ -#define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ -#define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ -#define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ -#define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ -#define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */ -#define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ -#define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ -#define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ -#define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ - -/* Bit fields for PDM SYNCBUSY */ -#define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ -#define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */ -#define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */ -#define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */ -#define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */ -#define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ -#define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ -#define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ -#define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ -#define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ -#define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ -#define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ - -/** @} End of group EFR32BG22_PDM_BitFields */ -/** @} End of group EFR32BG22_PDM */ -/** @} End of group Parts */ - -#endif // EFR32BG22_PDM_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 PDM register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_PDM_H +#define EFR32BG22_PDM_H +#define PDM_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_PDM PDM + * @{ + * @brief EFR32BG22 PDM Register Declaration. + *****************************************************************************/ + +/** PDM Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version ID */ + __IOM uint32_t EN; /**< PDM Module enable Register */ + __IOM uint32_t CTRL; /**< PDM Core Control Register */ + __IOM uint32_t CMD; /**< PDM Core Command Register */ + __IM uint32_t STATUS; /**< PDM Status register */ + __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA; /**< PDM Received Data Register */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Flag Register */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED3[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version ID */ + __IOM uint32_t EN_SET; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_SET; /**< PDM Core Control Register */ + __IOM uint32_t CMD_SET; /**< PDM Core Command Register */ + __IM uint32_t STATUS_SET; /**< PDM Status register */ + __IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_SET; /**< PDM Received Data Register */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Flag Register */ + uint32_t RESERVED6[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED7[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ + __IOM uint32_t EN_CLR; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */ + __IOM uint32_t CMD_CLR; /**< PDM Core Command Register */ + __IM uint32_t STATUS_CLR; /**< PDM Status register */ + __IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */ + uint32_t RESERVED10[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED11[999U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ + __IOM uint32_t EN_TGL; /**< PDM Module enable Register */ + __IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */ + __IOM uint32_t CMD_TGL; /**< PDM Core Command Register */ + __IM uint32_t STATUS_TGL; /**< PDM Status register */ + __IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */ + __IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */ + uint32_t RESERVED13[7U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */ + uint32_t RESERVED14[6U]; /**< Reserved for future use */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} PDM_TypeDef; +/** @} End of group EFR32BG22_PDM */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_PDM + * @{ + * @defgroup EFR32BG22_PDM_BitFields PDM Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PDM IPVERSION */ +#define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ +#define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ +#define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ +#define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ + +/* Bit fields for PDM EN */ +#define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ +#define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ +#define PDM_EN_EN (0x1UL << 0) /**< PDM enable */ +#define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ +#define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ +#define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ +#define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ +#define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ +#define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ +#define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ +#define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ + +/* Bit fields for PDM CTRL */ +#define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ +#define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */ +#define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ +#define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ +#define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ +#define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ +#define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ +#define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ +#define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ + +/* Bit fields for PDM CMD */ +#define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ +#define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ +#define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ +#define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ +#define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ +#define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ +#define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ +#define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ +#define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ +#define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ +#define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ +#define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ +#define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ +#define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ + +/* Bit fields for PDM STATUS */ +#define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ +#define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ +#define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ +#define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ +#define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ +#define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ +#define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ +#define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ +#define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ +#define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ +#define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ +#define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ +#define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ +#define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ + +/* Bit fields for PDM CFG0 */ +#define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ +#define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ +#define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ +#define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ +#define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ +#define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ +#define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ +#define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */ +#define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */ +#define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ +#define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ +#define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ +#define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ +#define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ +#define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ +#define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ +#define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ +#define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ +#define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ +#define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ +#define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ +#define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ +#define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ +#define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ +#define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ +#define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ + +/* Bit fields for PDM CFG1 */ +#define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ +#define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */ +#define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ +#define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ +#define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ +#define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */ +#define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ +#define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */ + +/* Bit fields for PDM RXDATA */ +#define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ +#define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ +#define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ +#define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ + +/* Bit fields for PDM IF */ +#define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ +#define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ +#define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ +#define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ +#define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ +#define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ +#define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ +#define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ +#define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ + +/* Bit fields for PDM IEN */ +#define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ +#define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ +#define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */ +#define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ +#define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ +#define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */ +#define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ +#define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ +#define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */ +#define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ +#define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ +#define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */ +#define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ +#define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ +#define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ +#define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ + +/* Bit fields for PDM SYNCBUSY */ +#define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */ +#define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */ +#define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ +#define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ +#define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ + +/** @} End of group EFR32BG22_PDM_BitFields */ +/** @} End of group EFR32BG22_PDM */ +/** @} End of group Parts */ + +#endif // EFR32BG22_PDM_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h index 42e0ddc..6de88ee 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs.h @@ -1,1319 +1,1319 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 PRS register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_PRS_H -#define EFR32BG22_PRS_H -#define PRS_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_PRS PRS - * @{ - * @brief EFR32BG22 PRS Register Declaration. - *****************************************************************************/ - -/** PRS ASYNC_CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t CTRL; /**< Async Channel Control Register */ -} PRS_ASYNC_CH_TypeDef; - -/** PRS SYNC_CH Register Group Declaration. */ -typedef struct { - __IOM uint32_t CTRL; /**< Sync Channel Control Register */ -} PRS_SYNC_CH_TypeDef; - -/** PRS Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN; /**< CMU CALDN Consumer Selection */ - __IOM uint32_t CONSUMER_CMU_CALUP; /**< CMU CALUP Consumer Selection */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< IADC0 SCANTRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< IADC0 SINGLETRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< LETIMER CLEAR Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_START; /**< LETIMER START Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< LETIMER STOP Consumer Selection */ - __IOM uint32_t CONSUMER_EUART0_RX; /**< EUART0 RX consumer register */ - __IOM uint32_t CONSUMER_EUART0_TRIGGER; /**< EUART0 TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN Consumer Selection */ - uint32_t RESERVED2[2U]; /**< Reserved for future use */ - uint32_t RESERVED3[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR; /**< RAC CLR Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< RAC CTIIN0 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< RAC CTIIN1 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< RAC CTIIN2 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< RAC CTIIN3 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_FORCETX; /**< RAC FORCETX Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RAC RXDIS Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXEN; /**< RAC RXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_SEQ; /**< RAC SEQ Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_TXEN; /**< RAC TXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC0; /**< RTCC CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC1; /**< RTCC CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC2; /**< RTCC CC2 Consumer Selection */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0; /**< TIMER0 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC1; /**< TIMER0 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC2; /**< TIMER0 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTI; /**< TIMER0 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< TIMER0 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< TIMER0 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC0; /**< TIMER1 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC1; /**< TIMER1 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC2; /**< TIMER1 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTI; /**< TIMER1 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< TIMER1 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< TIMER1 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC0; /**< TIMER2 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC1; /**< TIMER2 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC2; /**< TIMER2 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTI; /**< TIMER2 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< TIMER2 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< TIMER2 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC0; /**< TIMER3 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC1; /**< TIMER3 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC2; /**< TIMER3 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTI; /**< TIMER3 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< TIMER3 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< TIMER3 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC0; /**< TIMER4 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC1; /**< TIMER4 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC2; /**< TIMER4 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTI; /**< TIMER4 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< TIMER4 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< TIMER4 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_CLK; /**< USART0 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_IR; /**< USART0 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_RX; /**< USART0 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< USART0 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_CLK; /**< USART1 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_IR; /**< USART1 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_RX; /**< USART1 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< USART1 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< WDOG0 SRC0 Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< WDOG0 SRC1 Consumer Selection */ - uint32_t RESERVED5[917U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CMU CALDN Consumer Selection */ - __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CMU CALUP Consumer Selection */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< IADC0 SCANTRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< IADC0 SINGLETRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< LETIMER CLEAR Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< LETIMER START Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< LETIMER STOP Consumer Selection */ - __IOM uint32_t CONSUMER_EUART0_RX_SET; /**< EUART0 RX consumer register */ - __IOM uint32_t CONSUMER_EUART0_TRIGGER_SET; /**< EUART0 TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN Consumer Selection */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< RAC CLR Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< RAC CTIIN0 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< RAC CTIIN1 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< RAC CTIIN2 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< RAC CTIIN3 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< RAC FORCETX Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RAC RXDIS Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RAC RXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< RAC SEQ Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< RAC TXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< RTCC CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< RTCC CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< RTCC CC2 Consumer Selection */ - uint32_t RESERVED10[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< TIMER0 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< TIMER0 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< TIMER0 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< TIMER0 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< TIMER0 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< TIMER0 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< TIMER1 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< TIMER1 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< TIMER1 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< TIMER1 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< TIMER1 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< TIMER1 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< TIMER2 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< TIMER2 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< TIMER2 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< TIMER2 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< TIMER2 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< TIMER2 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< TIMER3 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< TIMER3 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< TIMER3 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< TIMER3 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< TIMER3 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< TIMER3 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< TIMER4 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< TIMER4 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< TIMER4 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< TIMER4 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< TIMER4 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< TIMER4 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< USART0 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_IR_SET; /**< USART0 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_RX_SET; /**< USART0 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< USART0 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< USART1 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_IR_SET; /**< USART1 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_RX_SET; /**< USART1 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< USART1 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< WDOG0 SRC0 Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< WDOG0 SRC1 Consumer Selection */ - uint32_t RESERVED11[917U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CMU CALDN Consumer Selection */ - __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CMU CALUP Consumer Selection */ - uint32_t RESERVED13[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< IADC0 SCANTRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< IADC0 SINGLETRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< LETIMER CLEAR Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< LETIMER START Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< LETIMER STOP Consumer Selection */ - __IOM uint32_t CONSUMER_EUART0_RX_CLR; /**< EUART0 RX consumer register */ - __IOM uint32_t CONSUMER_EUART0_TRIGGER_CLR; /**< EUART0 TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN Consumer Selection */ - uint32_t RESERVED14[2U]; /**< Reserved for future use */ - uint32_t RESERVED15[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< RAC CLR Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< RAC CTIIN0 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< RAC CTIIN1 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< RAC CTIIN2 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< RAC CTIIN3 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< RAC FORCETX Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RAC RXDIS Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RAC RXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< RAC SEQ Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< RAC TXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< RTCC CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< RTCC CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< RTCC CC2 Consumer Selection */ - uint32_t RESERVED16[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< TIMER0 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< TIMER0 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< TIMER0 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< TIMER0 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< TIMER0 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< TIMER0 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< TIMER1 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< TIMER1 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< TIMER1 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< TIMER1 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< TIMER1 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< TIMER1 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< TIMER2 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< TIMER2 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< TIMER2 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< TIMER2 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< TIMER2 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< TIMER2 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< TIMER3 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< TIMER3 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< TIMER3 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< TIMER3 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< TIMER3 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< TIMER3 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< TIMER4 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< TIMER4 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< TIMER4 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< TIMER4 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< TIMER4 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< TIMER4 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< USART0 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< USART0 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< USART0 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< USART0 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< USART1 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< USART1 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< USART1 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< USART1 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< WDOG0 SRC0 Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< WDOG0 SRC1 Consumer Selection */ - uint32_t RESERVED17[917U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ - __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ - __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ - __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ - PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ - PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ - __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CMU CALDN Consumer Selection */ - __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CMU CALUP Consumer Selection */ - uint32_t RESERVED19[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< IADC0 SCANTRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< IADC0 SINGLETRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 Consumer Selection */ - __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< LETIMER CLEAR Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< LETIMER START Consumer Selection */ - __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< LETIMER STOP Consumer Selection */ - __IOM uint32_t CONSUMER_EUART0_RX_TGL; /**< EUART0 RX consumer register */ - __IOM uint32_t CONSUMER_EUART0_TRIGGER_TGL; /**< EUART0 TRIGGER Consumer register */ - __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN Consumer Selection */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - uint32_t RESERVED21[11U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< RAC CLR Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< RAC CTIIN0 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< RAC CTIIN1 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< RAC CTIIN2 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< RAC CTIIN3 Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< RAC FORCETX Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RAC RXDIS Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RAC RXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< RAC SEQ Consumer Selection */ - __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< RAC TXEN Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< RTCC CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< RTCC CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< RTCC CC2 Consumer Selection */ - uint32_t RESERVED22[1U]; /**< Reserved for future use */ - __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ - __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< TIMER0 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< TIMER0 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< TIMER0 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< TIMER0 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< TIMER0 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< TIMER0 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< TIMER1 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< TIMER1 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< TIMER1 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< TIMER1 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< TIMER1 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< TIMER1 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< TIMER2 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< TIMER2 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< TIMER2 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< TIMER2 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< TIMER2 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< TIMER2 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< TIMER3 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< TIMER3 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< TIMER3 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< TIMER3 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< TIMER3 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< TIMER3 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< TIMER4 CC0 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< TIMER4 CC1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< TIMER4 CC2 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< TIMER4 DTI Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< TIMER4 DTIFS1 Consumer Selection */ - __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< TIMER4 DTIFS2 Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< USART0 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< USART0 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< USART0 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< USART0 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< USART1 CLK Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< USART1 IR Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< USART1 RX Consumer Selection */ - __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< USART1 TRIGGER Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< WDOG0 SRC0 Consumer Selection */ - __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< WDOG0 SRC1 Consumer Selection */ -} PRS_TypeDef; -/** @} End of group EFR32BG22_PRS */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_PRS - * @{ - * @defgroup EFR32BG22_PRS_BitFields PRS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for PRS IPVERSION */ -#define _PRS_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PRS_IPVERSION */ -#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ -#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PRS_IPVERSION */ -#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ - -/* Bit fields for PRS ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ -#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ -#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ -#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ -#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ -#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ -#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ -#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ -#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ -#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ -#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ -#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ -#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ -#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ -#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ - -/* Bit fields for PRS ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ -#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ -#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ -#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ - -/* Bit fields for PRS ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ -#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ -#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ -#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ -#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ -#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ -#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ -#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ -#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ -#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ -#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ -#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ -#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ -#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ -#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ -#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ -#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ -#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ -#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ -#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ -#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ -#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ -#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ - -/* Bit fields for PRS SYNC_PEEK */ -#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ -#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ -#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ -#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ -#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ -#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ -#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ -#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ - -/* Bit fields for PRS ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ -#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ -#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ -#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ - -/* Bit fields for PRS SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ - -/* Bit fields for PRS CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ -#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ - -/* Bit fields for PRS CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ -#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ - -/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ -#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ - -/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ -#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ - -/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ - -/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ -#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ -#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ -#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ -#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ - -/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ -#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ -#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ - -/* Bit fields for PRS CONSUMER_EUART0_RX */ -#define _PRS_CONSUMER_EUART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_RX */ -#define _PRS_CONSUMER_EUART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_RX */ -#define _PRS_CONSUMER_EUART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_RX */ -#define PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_RX*/ - -/* Bit fields for PRS CONSUMER_EUART0_TRIGGER */ -#define _PRS_CONSUMER_EUART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_TRIGGER*/ -#define _PRS_CONSUMER_EUART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_TRIGGER */ -#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ -#define PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ -#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ - -/* Bit fields for PRS CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ -#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ -#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ -#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ -#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ - -/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ -#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ - -/* Bit fields for PRS CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ -#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ - -/* Bit fields for PRS CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ -#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ - -/* Bit fields for PRS CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ -#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ - -/* Bit fields for PRS CONSUMER_RAC_SEQ */ -#define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ -#define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ -#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ -#define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ - -/* Bit fields for PRS CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ -#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ - -/* Bit fields for PRS CONSUMER_RTCC_CC0 */ -#define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ -#define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ -#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ -#define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ - -/* Bit fields for PRS CONSUMER_RTCC_CC1 */ -#define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ -#define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ -#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ -#define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ - -/* Bit fields for PRS CONSUMER_RTCC_CC2 */ -#define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ -#define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ -#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ -#define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ -#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ -#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ -#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ - -/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ -#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ - -/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ -#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ -#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ -#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ -#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ -#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ -#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ -#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ -#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ -#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ -#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ -#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ -#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ -#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ -#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ -#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ -#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ -#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ -#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ -#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ -#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ -#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ -#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ -#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ -#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ -#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ -#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ -#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ -#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ -#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ -#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ -#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ -#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ -#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ -#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ -#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ - -/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ -#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ -#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ -#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ -#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ -#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ - -/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ -#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ -#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ - -/* Bit fields for PRS CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ -#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ - -/* Bit fields for PRS CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ -#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ - -/* Bit fields for PRS CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ -#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ - -/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ -#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ -#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_USART1_CLK */ -#define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ -#define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ -#define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ -#define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ - -/* Bit fields for PRS CONSUMER_USART1_IR */ -#define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ -#define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ -#define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ -#define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ - -/* Bit fields for PRS CONSUMER_USART1_RX */ -#define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ -#define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ -#define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ -#define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ - -/* Bit fields for PRS CONSUMER_USART1_TRIGGER */ -#define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ -#define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ -#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ -#define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ - -/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ -#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ - -/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ -#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ -#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ - -/** @} End of group EFR32BG22_PRS_BitFields */ -/** @} End of group EFR32BG22_PRS */ -/** @} End of group Parts */ - -#endif // EFR32BG22_PRS_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 PRS register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_PRS_H +#define EFR32BG22_PRS_H +#define PRS_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_PRS PRS + * @{ + * @brief EFR32BG22 PRS Register Declaration. + *****************************************************************************/ + +/** PRS ASYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Async Channel Control Register */ +} PRS_ASYNC_CH_TypeDef; + +/** PRS SYNC_CH Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< Sync Channel Control Register */ +} PRS_SYNC_CH_TypeDef; + +/** PRS Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN; /**< CMU CALDN Consumer Selection */ + __IOM uint32_t CONSUMER_CMU_CALUP; /**< CMU CALUP Consumer Selection */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER; /**< IADC0 SCANTRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER; /**< IADC0 SINGLETRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0; /**< DMAREQ0 Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1; /**< DMAREQ1 Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR; /**< LETIMER CLEAR Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_START; /**< LETIMER START Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_STOP; /**< LETIMER STOP Consumer Selection */ + __IOM uint32_t CONSUMER_EUART0_RX; /**< EUART0 RX consumer register */ + __IOM uint32_t CONSUMER_EUART0_TRIGGER; /**< EUART0 TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN; /**< MODEM DIN Consumer Selection */ + uint32_t RESERVED2[2U]; /**< Reserved for future use */ + uint32_t RESERVED3[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR; /**< RAC CLR Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN0; /**< RAC CTIIN0 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN1; /**< RAC CTIIN1 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN2; /**< RAC CTIIN2 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN3; /**< RAC CTIIN3 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_FORCETX; /**< RAC FORCETX Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXDIS; /**< RAC RXDIS Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXEN; /**< RAC RXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_SEQ; /**< RAC SEQ Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_TXEN; /**< RAC TXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC0; /**< RTCC CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC1; /**< RTCC CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC2; /**< RTCC CC2 Consumer Selection */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_CORE_CTIIN0; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0; /**< TIMER0 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC1; /**< TIMER0 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC2; /**< TIMER0 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTI; /**< TIMER0 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1; /**< TIMER0 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2; /**< TIMER0 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC0; /**< TIMER1 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC1; /**< TIMER1 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC2; /**< TIMER1 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTI; /**< TIMER1 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1; /**< TIMER1 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2; /**< TIMER1 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC0; /**< TIMER2 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC1; /**< TIMER2 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC2; /**< TIMER2 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTI; /**< TIMER2 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1; /**< TIMER2 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2; /**< TIMER2 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC0; /**< TIMER3 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC1; /**< TIMER3 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC2; /**< TIMER3 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTI; /**< TIMER3 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1; /**< TIMER3 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2; /**< TIMER3 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC0; /**< TIMER4 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC1; /**< TIMER4 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC2; /**< TIMER4 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTI; /**< TIMER4 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1; /**< TIMER4 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2; /**< TIMER4 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_CLK; /**< USART0 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_IR; /**< USART0 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_RX; /**< USART0 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_TRIGGER; /**< USART0 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_CLK; /**< USART1 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_IR; /**< USART1 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_RX; /**< USART1 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_TRIGGER; /**< USART1 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC0; /**< WDOG0 SRC0 Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC1; /**< WDOG0 SRC1 Consumer Selection */ + uint32_t RESERVED5[917U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_SET; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_SET; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_SET; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_SET; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_SET[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_SET[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_SET; /**< CMU CALDN Consumer Selection */ + __IOM uint32_t CONSUMER_CMU_CALUP_SET; /**< CMU CALUP Consumer Selection */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_SET; /**< IADC0 SCANTRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_SET; /**< IADC0 SINGLETRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_SET; /**< DMAREQ0 Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_SET; /**< DMAREQ1 Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_SET; /**< LETIMER CLEAR Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_START_SET; /**< LETIMER START Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_SET; /**< LETIMER STOP Consumer Selection */ + __IOM uint32_t CONSUMER_EUART0_RX_SET; /**< EUART0 RX consumer register */ + __IOM uint32_t CONSUMER_EUART0_TRIGGER_SET; /**< EUART0 TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_SET; /**< MODEM DIN Consumer Selection */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_SET; /**< RAC CLR Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_SET; /**< RAC CTIIN0 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_SET; /**< RAC CTIIN1 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_SET; /**< RAC CTIIN2 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_SET; /**< RAC CTIIN3 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_FORCETX_SET; /**< RAC FORCETX Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXDIS_SET; /**< RAC RXDIS Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXEN_SET; /**< RAC RXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_SEQ_SET; /**< RAC SEQ Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_TXEN_SET; /**< RAC TXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC0_SET; /**< RTCC CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC1_SET; /**< RTCC CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC2_SET; /**< RTCC CC2 Consumer Selection */ + uint32_t RESERVED10[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_SET; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_SET; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_SET; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_SET; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_SET; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_SET; /**< TIMER0 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC1_SET; /**< TIMER0 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC2_SET; /**< TIMER0 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTI_SET; /**< TIMER0 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_SET; /**< TIMER0 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_SET; /**< TIMER0 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC0_SET; /**< TIMER1 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC1_SET; /**< TIMER1 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC2_SET; /**< TIMER1 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTI_SET; /**< TIMER1 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_SET; /**< TIMER1 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_SET; /**< TIMER1 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC0_SET; /**< TIMER2 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC1_SET; /**< TIMER2 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC2_SET; /**< TIMER2 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTI_SET; /**< TIMER2 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_SET; /**< TIMER2 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_SET; /**< TIMER2 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC0_SET; /**< TIMER3 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC1_SET; /**< TIMER3 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC2_SET; /**< TIMER3 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTI_SET; /**< TIMER3 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_SET; /**< TIMER3 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_SET; /**< TIMER3 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC0_SET; /**< TIMER4 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC1_SET; /**< TIMER4 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC2_SET; /**< TIMER4 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTI_SET; /**< TIMER4 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_SET; /**< TIMER4 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_SET; /**< TIMER4 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_CLK_SET; /**< USART0 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_IR_SET; /**< USART0 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_RX_SET; /**< USART0 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_SET; /**< USART0 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_CLK_SET; /**< USART1 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_IR_SET; /**< USART1 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_RX_SET; /**< USART1 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_SET; /**< USART1 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_SET; /**< WDOG0 SRC0 Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_SET; /**< WDOG0 SRC1 Consumer Selection */ + uint32_t RESERVED11[917U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_CLR; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_CLR; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_CLR; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_CLR; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_CLR[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_CLR[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_CLR; /**< CMU CALDN Consumer Selection */ + __IOM uint32_t CONSUMER_CMU_CALUP_CLR; /**< CMU CALUP Consumer Selection */ + uint32_t RESERVED13[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_CLR; /**< IADC0 SCANTRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_CLR; /**< IADC0 SINGLETRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_CLR; /**< DMAREQ0 Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_CLR; /**< DMAREQ1 Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_CLR; /**< LETIMER CLEAR Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_START_CLR; /**< LETIMER START Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_CLR; /**< LETIMER STOP Consumer Selection */ + __IOM uint32_t CONSUMER_EUART0_RX_CLR; /**< EUART0 RX consumer register */ + __IOM uint32_t CONSUMER_EUART0_TRIGGER_CLR; /**< EUART0 TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_CLR; /**< MODEM DIN Consumer Selection */ + uint32_t RESERVED14[2U]; /**< Reserved for future use */ + uint32_t RESERVED15[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_CLR; /**< RAC CLR Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_CLR; /**< RAC CTIIN0 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_CLR; /**< RAC CTIIN1 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_CLR; /**< RAC CTIIN2 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_CLR; /**< RAC CTIIN3 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_FORCETX_CLR; /**< RAC FORCETX Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXDIS_CLR; /**< RAC RXDIS Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXEN_CLR; /**< RAC RXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_SEQ_CLR; /**< RAC SEQ Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_TXEN_CLR; /**< RAC TXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC0_CLR; /**< RTCC CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC1_CLR; /**< RTCC CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC2_CLR; /**< RTCC CC2 Consumer Selection */ + uint32_t RESERVED16[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_CLR; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_CLR; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_CLR; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_CLR; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_CLR; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_CLR; /**< TIMER0 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC1_CLR; /**< TIMER0 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC2_CLR; /**< TIMER0 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTI_CLR; /**< TIMER0 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_CLR; /**< TIMER0 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_CLR; /**< TIMER0 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC0_CLR; /**< TIMER1 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC1_CLR; /**< TIMER1 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC2_CLR; /**< TIMER1 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTI_CLR; /**< TIMER1 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_CLR; /**< TIMER1 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_CLR; /**< TIMER1 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC0_CLR; /**< TIMER2 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC1_CLR; /**< TIMER2 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC2_CLR; /**< TIMER2 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTI_CLR; /**< TIMER2 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_CLR; /**< TIMER2 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_CLR; /**< TIMER2 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC0_CLR; /**< TIMER3 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC1_CLR; /**< TIMER3 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC2_CLR; /**< TIMER3 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTI_CLR; /**< TIMER3 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_CLR; /**< TIMER3 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_CLR; /**< TIMER3 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC0_CLR; /**< TIMER4 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC1_CLR; /**< TIMER4 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC2_CLR; /**< TIMER4 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTI_CLR; /**< TIMER4 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_CLR; /**< TIMER4 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_CLR; /**< TIMER4 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_CLK_CLR; /**< USART0 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_IR_CLR; /**< USART0 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_RX_CLR; /**< USART0 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_CLR; /**< USART0 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_CLK_CLR; /**< USART1 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_IR_CLR; /**< USART1 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_RX_CLR; /**< USART1 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_CLR; /**< USART1 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_CLR; /**< WDOG0 SRC0 Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_CLR; /**< WDOG0 SRC1 Consumer Selection */ + uint32_t RESERVED17[917U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IOM uint32_t ASYNC_SWPULSE_TGL; /**< Software Pulse Register */ + __IOM uint32_t ASYNC_SWLEVEL_TGL; /**< Software Level Register */ + __IM uint32_t ASYNC_PEEK_TGL; /**< Async Channel Values */ + __IM uint32_t SYNC_PEEK_TGL; /**< Sync Channel Values */ + PRS_ASYNC_CH_TypeDef ASYNC_CH_TGL[12U]; /**< Async Channel registers */ + PRS_SYNC_CH_TypeDef SYNC_CH_TGL[4U]; /**< Sync Channel registers */ + __IOM uint32_t CONSUMER_CMU_CALDN_TGL; /**< CMU CALDN Consumer Selection */ + __IOM uint32_t CONSUMER_CMU_CALUP_TGL; /**< CMU CALUP Consumer Selection */ + uint32_t RESERVED19[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_IADC0_SCANTRIGGER_TGL; /**< IADC0 SCANTRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_IADC0_SINGLETRIGGER_TGL; /**< IADC0 SINGLETRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ0_TGL; /**< DMAREQ0 Consumer Selection */ + __IOM uint32_t CONSUMER_LDMAXBAR_DMAREQ1_TGL; /**< DMAREQ1 Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_CLEAR_TGL; /**< LETIMER CLEAR Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_START_TGL; /**< LETIMER START Consumer Selection */ + __IOM uint32_t CONSUMER_LETIMER0_STOP_TGL; /**< LETIMER STOP Consumer Selection */ + __IOM uint32_t CONSUMER_EUART0_RX_TGL; /**< EUART0 RX consumer register */ + __IOM uint32_t CONSUMER_EUART0_TRIGGER_TGL; /**< EUART0 TRIGGER Consumer register */ + __IOM uint32_t CONSUMER_MODEM_DIN_TGL; /**< MODEM DIN Consumer Selection */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + uint32_t RESERVED21[11U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_RAC_CLR_TGL; /**< RAC CLR Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN0_TGL; /**< RAC CTIIN0 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN1_TGL; /**< RAC CTIIN1 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN2_TGL; /**< RAC CTIIN2 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_CTIIN3_TGL; /**< RAC CTIIN3 Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_FORCETX_TGL; /**< RAC FORCETX Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXDIS_TGL; /**< RAC RXDIS Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_RXEN_TGL; /**< RAC RXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_SEQ_TGL; /**< RAC SEQ Consumer Selection */ + __IOM uint32_t CONSUMER_RAC_TXEN_TGL; /**< RAC TXEN Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC0_TGL; /**< RTCC CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC1_TGL; /**< RTCC CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_RTCC_CC2_TGL; /**< RTCC CC2 Consumer Selection */ + uint32_t RESERVED22[1U]; /**< Reserved for future use */ + __IOM uint32_t CONSUMER_CORE_CTIIN0_TGL; /**< CTI0 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN1_TGL; /**< CTI1 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN2_TGL; /**< CTI2 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_CTIIN3_TGL; /**< CTI3 Consumer Selection */ + __IOM uint32_t CONSUMER_CORE_M33RXEV_TGL; /**< M33 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC0_TGL; /**< TIMER0 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC1_TGL; /**< TIMER0 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_CC2_TGL; /**< TIMER0 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTI_TGL; /**< TIMER0 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS1_TGL; /**< TIMER0 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER0_DTIFS2_TGL; /**< TIMER0 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC0_TGL; /**< TIMER1 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC1_TGL; /**< TIMER1 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_CC2_TGL; /**< TIMER1 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTI_TGL; /**< TIMER1 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS1_TGL; /**< TIMER1 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER1_DTIFS2_TGL; /**< TIMER1 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC0_TGL; /**< TIMER2 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC1_TGL; /**< TIMER2 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_CC2_TGL; /**< TIMER2 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTI_TGL; /**< TIMER2 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS1_TGL; /**< TIMER2 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER2_DTIFS2_TGL; /**< TIMER2 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC0_TGL; /**< TIMER3 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC1_TGL; /**< TIMER3 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_CC2_TGL; /**< TIMER3 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTI_TGL; /**< TIMER3 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS1_TGL; /**< TIMER3 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER3_DTIFS2_TGL; /**< TIMER3 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC0_TGL; /**< TIMER4 CC0 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC1_TGL; /**< TIMER4 CC1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_CC2_TGL; /**< TIMER4 CC2 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTI_TGL; /**< TIMER4 DTI Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS1_TGL; /**< TIMER4 DTIFS1 Consumer Selection */ + __IOM uint32_t CONSUMER_TIMER4_DTIFS2_TGL; /**< TIMER4 DTIFS2 Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_CLK_TGL; /**< USART0 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_IR_TGL; /**< USART0 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_RX_TGL; /**< USART0 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART0_TRIGGER_TGL; /**< USART0 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_CLK_TGL; /**< USART1 CLK Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_IR_TGL; /**< USART1 IR Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_RX_TGL; /**< USART1 RX Consumer Selection */ + __IOM uint32_t CONSUMER_USART1_TRIGGER_TGL; /**< USART1 TRIGGER Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC0_TGL; /**< WDOG0 SRC0 Consumer Selection */ + __IOM uint32_t CONSUMER_WDOG0_SRC1_TGL; /**< WDOG0 SRC1 Consumer Selection */ +} PRS_TypeDef; +/** @} End of group EFR32BG22_PRS */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_PRS + * @{ + * @defgroup EFR32BG22_PRS_BitFields PRS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for PRS IPVERSION */ +#define _PRS_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PRS_IPVERSION */ +#define _PRS_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PRS_IPVERSION */ +#define _PRS_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PRS_IPVERSION */ +#define PRS_IPVERSION_IPVERSION_DEFAULT (_PRS_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_IPVERSION */ + +/* Bit fields for PRS ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWPULSE */ +#define _PRS_ASYNC_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */ +#define _PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */ +#define _PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */ +#define _PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */ +#define _PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */ +#define _PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */ +#define _PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */ +#define _PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */ +#define _PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */ +#define _PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */ +#define _PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */ +#define _PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel pulse */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */ +#define _PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWPULSE */ +#define PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT (_PRS_ASYNC_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWPULSE */ + +/* Bit fields for PRS ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_SWLEVEL */ +#define _PRS_ASYNC_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel Level */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */ +#define _PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_SWLEVEL */ +#define PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_ASYNC_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_SWLEVEL */ + +/* Bit fields for PRS ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_ASYNC_PEEK */ +#define _PRS_ASYNC_PEEK_MASK 0x00000FFFUL /**< Mask for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel 0 Current Value */ +#define _PRS_ASYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_ASYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH0VAL_DEFAULT (_PRS_ASYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel 1 Current Value */ +#define _PRS_ASYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_ASYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH1VAL_DEFAULT (_PRS_ASYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel 2 Current Value */ +#define _PRS_ASYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_ASYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH2VAL_DEFAULT (_PRS_ASYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel 3 Current Value */ +#define _PRS_ASYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_ASYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH3VAL_DEFAULT (_PRS_ASYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL (0x1UL << 4) /**< Channel 4 Current Value */ +#define _PRS_ASYNC_PEEK_CH4VAL_SHIFT 4 /**< Shift value for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_MASK 0x10UL /**< Bit mask for PRS_CH4VAL */ +#define _PRS_ASYNC_PEEK_CH4VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH4VAL_DEFAULT (_PRS_ASYNC_PEEK_CH4VAL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL (0x1UL << 5) /**< Channel 5 Current Value */ +#define _PRS_ASYNC_PEEK_CH5VAL_SHIFT 5 /**< Shift value for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_MASK 0x20UL /**< Bit mask for PRS_CH5VAL */ +#define _PRS_ASYNC_PEEK_CH5VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH5VAL_DEFAULT (_PRS_ASYNC_PEEK_CH5VAL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL (0x1UL << 6) /**< Channel 6 Current Value */ +#define _PRS_ASYNC_PEEK_CH6VAL_SHIFT 6 /**< Shift value for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_MASK 0x40UL /**< Bit mask for PRS_CH6VAL */ +#define _PRS_ASYNC_PEEK_CH6VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH6VAL_DEFAULT (_PRS_ASYNC_PEEK_CH6VAL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL (0x1UL << 7) /**< Channel 7 Current Value */ +#define _PRS_ASYNC_PEEK_CH7VAL_SHIFT 7 /**< Shift value for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_MASK 0x80UL /**< Bit mask for PRS_CH7VAL */ +#define _PRS_ASYNC_PEEK_CH7VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH7VAL_DEFAULT (_PRS_ASYNC_PEEK_CH7VAL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL (0x1UL << 8) /**< Channel 8 Current Value */ +#define _PRS_ASYNC_PEEK_CH8VAL_SHIFT 8 /**< Shift value for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_MASK 0x100UL /**< Bit mask for PRS_CH8VAL */ +#define _PRS_ASYNC_PEEK_CH8VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH8VAL_DEFAULT (_PRS_ASYNC_PEEK_CH8VAL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL (0x1UL << 9) /**< Channel 9 Current Value */ +#define _PRS_ASYNC_PEEK_CH9VAL_SHIFT 9 /**< Shift value for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_MASK 0x200UL /**< Bit mask for PRS_CH9VAL */ +#define _PRS_ASYNC_PEEK_CH9VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH9VAL_DEFAULT (_PRS_ASYNC_PEEK_CH9VAL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL (0x1UL << 10) /**< Channel 10 Current Value */ +#define _PRS_ASYNC_PEEK_CH10VAL_SHIFT 10 /**< Shift value for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_MASK 0x400UL /**< Bit mask for PRS_CH10VAL */ +#define _PRS_ASYNC_PEEK_CH10VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH10VAL_DEFAULT (_PRS_ASYNC_PEEK_CH10VAL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL (0x1UL << 11) /**< Channel 11 Current Value */ +#define _PRS_ASYNC_PEEK_CH11VAL_SHIFT 11 /**< Shift value for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_MASK 0x800UL /**< Bit mask for PRS_CH11VAL */ +#define _PRS_ASYNC_PEEK_CH11VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_PEEK */ +#define PRS_ASYNC_PEEK_CH11VAL_DEFAULT (_PRS_ASYNC_PEEK_CH11VAL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_ASYNC_PEEK */ + +/* Bit fields for PRS SYNC_PEEK */ +#define _PRS_SYNC_PEEK_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_PEEK */ +#define _PRS_SYNC_PEEK_MASK 0x0000000FUL /**< Mask for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL (0x1UL << 0) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH0VAL_SHIFT 0 /**< Shift value for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_MASK 0x1UL /**< Bit mask for PRS_CH0VAL */ +#define _PRS_SYNC_PEEK_CH0VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH0VAL_DEFAULT (_PRS_SYNC_PEEK_CH0VAL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL (0x1UL << 1) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH1VAL_SHIFT 1 /**< Shift value for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_MASK 0x2UL /**< Bit mask for PRS_CH1VAL */ +#define _PRS_SYNC_PEEK_CH1VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH1VAL_DEFAULT (_PRS_SYNC_PEEK_CH1VAL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL (0x1UL << 2) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH2VAL_SHIFT 2 /**< Shift value for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_MASK 0x4UL /**< Bit mask for PRS_CH2VAL */ +#define _PRS_SYNC_PEEK_CH2VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH2VAL_DEFAULT (_PRS_SYNC_PEEK_CH2VAL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL (0x1UL << 3) /**< Channel Value */ +#define _PRS_SYNC_PEEK_CH3VAL_SHIFT 3 /**< Shift value for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_MASK 0x8UL /**< Bit mask for PRS_CH3VAL */ +#define _PRS_SYNC_PEEK_CH3VAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_PEEK */ +#define PRS_SYNC_PEEK_CH3VAL_DEFAULT (_PRS_SYNC_PEEK_CH3VAL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SYNC_PEEK */ + +/* Bit fields for PRS ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_RESETVALUE 0x000C0000UL /**< Default value for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_MASK 0x0F0F7F07UL /**< Mask for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_NONE 0x00000000UL /**< Mode NONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_NONE (_PRS_ASYNC_CH_CTRL_SIGSEL_NONE << 0) /**< Shifted mode NONE for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_ASYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT 16 /**< Shift value for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_MASK 0xF0000UL /**< Bit mask for PRS_FNSEL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO 0x00000000UL /**< Mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B 0x00000001UL /**< Mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B 0x00000002UL /**< Mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A 0x00000003UL /**< Mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B 0x00000004UL /**< Mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B 0x00000005UL /**< Mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B 0x00000006UL /**< Mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B 0x00000007UL /**< Mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B 0x00000008UL /**< Mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B 0x00000009UL /**< Mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_B 0x0000000AUL /**< Mode B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B 0x0000000BUL /**< Mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A 0x0000000CUL /**< Mode A for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B 0x0000000DUL /**< Mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B 0x0000000EUL /**< Mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE 0x0000000FUL /**< Mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_FNSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO << 16) /**< Shifted mode LOGICAL_ZERO for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B << 16) /**< Shifted mode A_NOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B << 16) /**< Shifted mode NOT_A_AND_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A << 16) /**< Shifted mode NOT_A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B << 16) /**< Shifted mode A_AND_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_B << 16) /**< Shifted mode NOT_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B << 16) /**< Shifted mode A_XOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B << 16) /**< Shifted mode A_NAND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B << 16) /**< Shifted mode A_AND_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B << 16) /**< Shifted mode A_XNOR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_B (_PRS_ASYNC_CH_CTRL_FNSEL_B << 16) /**< Shifted mode B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B << 16) /**< Shifted mode NOT_A_OR_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A (_PRS_ASYNC_CH_CTRL_FNSEL_A << 16) /**< Shifted mode A for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B << 16) /**< Shifted mode A_OR_NOT_B for PRS_ASYNC_CH_CTRL*/ +#define PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B (_PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B << 16) /**< Shifted mode A_OR_B for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE (_PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE << 16) /**< Shifted mode LOGICAL_ONE for PRS_ASYNC_CH_CTRL*/ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT 24 /**< Shift value for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_MASK 0xF000000UL /**< Bit mask for PRS_AUXSEL */ +#define _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ASYNC_CH_CTRL */ +#define PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT (_PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_ASYNC_CH_CTRL */ + +/* Bit fields for PRS SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_MASK 0x00007F07UL /**< Mask for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT (_PRS_SYNC_CH_CTRL_SIGSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT 8 /**< Shift value for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_MASK 0x7F00UL /**< Bit mask for PRS_SOURCESEL */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SYNC_CH_CTRL */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT (_PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SYNC_CH_CTRL */ + +/* Bit fields for PRS CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALDN */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALDN */ +#define PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALDN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALDN*/ + +/* Bit fields for PRS CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CMU_CALUP */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CMU_CALUP */ +#define PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT (_PRS_CONSUMER_CMU_CALUP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CMU_CALUP*/ + +/* Bit fields for PRS CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SCANTRIGGER */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ +#define PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SCANTRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SCANTRIGGER*/ + +/* Bit fields for PRS CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_IADC0_SINGLETRIGGER */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ +#define PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT (_PRS_CONSUMER_IADC0_SINGLETRIGGER_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_IADC0_SINGLETRIGGER*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ0 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ0*/ + +/* Bit fields for PRS CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LDMAXBAR_DMAREQ1 */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ +#define PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT (_PRS_CONSUMER_LDMAXBAR_DMAREQ1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LDMAXBAR_DMAREQ1*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define _PRS_CONSUMER_LETIMER0_CLEAR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_CLEAR */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ +#define PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_CLEAR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_CLEAR*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_START*/ +#define _PRS_CONSUMER_LETIMER0_START_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_START */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ +#define PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_START_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_START*/ + +/* Bit fields for PRS CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_LETIMER0_STOP*/ +#define _PRS_CONSUMER_LETIMER0_STOP_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_LETIMER0_STOP */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP */ +#define PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT (_PRS_CONSUMER_LETIMER0_STOP_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_LETIMER0_STOP*/ + +/* Bit fields for PRS CONSUMER_EUART0_RX */ +#define _PRS_CONSUMER_EUART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_RX */ +#define _PRS_CONSUMER_EUART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_RX */ +#define _PRS_CONSUMER_EUART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_RX */ +#define PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_RX*/ + +/* Bit fields for PRS CONSUMER_EUART0_TRIGGER */ +#define _PRS_CONSUMER_EUART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_EUART0_TRIGGER*/ +#define _PRS_CONSUMER_EUART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_EUART0_TRIGGER */ +#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ +#define PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_EUART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_EUART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_MODEM_DIN */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_MODEM_DIN */ +#define PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT (_PRS_CONSUMER_MODEM_DIN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_MODEM_DIN*/ + +/* Bit fields for PRS CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CLR */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CLR */ +#define PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CLR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CLR*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN0 */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0 */ +#define PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN1 */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1 */ +#define PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN2 */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2 */ +#define PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_CTIIN3 */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3 */ +#define PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_FORCETX */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_FORCETX */ +#define PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_FORCETX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_FORCETX*/ + +/* Bit fields for PRS CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXDIS */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXDIS */ +#define PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXDIS_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXDIS*/ + +/* Bit fields for PRS CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_RXEN */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_RXEN */ +#define PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_RXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_RXEN*/ + +/* Bit fields for PRS CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_SEQ */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_SEQ */ +#define PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_SEQ_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_SEQ*/ + +/* Bit fields for PRS CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RAC_TXEN */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RAC_TXEN */ +#define PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT (_PRS_CONSUMER_RAC_TXEN_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RAC_TXEN*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC0 */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC0 */ +#define PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC0*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC1 */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC1 */ +#define PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC1*/ + +/* Bit fields for PRS CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_RTCC_CC2 */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_RTCC_CC2 */ +#define PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_RTCC_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_RTCC_CC2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN0 */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0 */ +#define PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN0*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN1 */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1 */ +#define PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN1*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN2 */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2 */ +#define PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN2*/ + +/* Bit fields for PRS CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_CTIIN3 */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3 */ +#define PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_CTIIN3_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_CTIIN3*/ + +/* Bit fields for PRS CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_CORE_M33RXEV */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV */ +#define PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT (_PRS_CONSUMER_CORE_M33RXEV_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_CORE_M33RXEV*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC0 */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC0 */ +#define PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC1 */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC1 */ +#define PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER0_CC2 */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_CC2 */ +#define PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTI */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTI */ +#define PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS1*/ +#define _PRS_CONSUMER_TIMER0_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1 */ +#define PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER0_DTIFS2*/ +#define _PRS_CONSUMER_TIMER0_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2 */ +#define PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER0_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER0_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC0 */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC0 */ +#define PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC1 */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC1 */ +#define PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER1_CC2 */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_CC2 */ +#define PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTI */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTI */ +#define PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS1*/ +#define _PRS_CONSUMER_TIMER1_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1 */ +#define PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER1_DTIFS2*/ +#define _PRS_CONSUMER_TIMER1_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2 */ +#define PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER1_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER1_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC0 */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC0 */ +#define PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC1 */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC1 */ +#define PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER2_CC2 */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_CC2 */ +#define PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTI */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTI */ +#define PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS1*/ +#define _PRS_CONSUMER_TIMER2_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1 */ +#define PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER2_DTIFS2*/ +#define _PRS_CONSUMER_TIMER2_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2 */ +#define PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER2_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER2_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC0 */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC0 */ +#define PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC1 */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC1 */ +#define PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER3_CC2 */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_CC2 */ +#define PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTI */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTI */ +#define PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS1*/ +#define _PRS_CONSUMER_TIMER3_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1 */ +#define PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER3_DTIFS2*/ +#define _PRS_CONSUMER_TIMER3_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2 */ +#define PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER3_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER3_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC0 */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC0 */ +#define PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC0_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC0*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC1 */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC1 */ +#define PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC1_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_MASK 0x0000030FUL /**< Mask for PRS_CONSUMER_TIMER4_CC2 */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_SHIFT 8 /**< Shift value for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_MASK 0x300UL /**< Bit mask for PRS_SPRSSEL */ +#define _PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_CC2 */ +#define PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_CC2_SPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_CC2*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTI */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTI */ +#define PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTI_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTI*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS1*/ +#define _PRS_CONSUMER_TIMER4_DTIFS1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1 */ +#define PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS1*/ + +/* Bit fields for PRS CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_TIMER4_DTIFS2*/ +#define _PRS_CONSUMER_TIMER4_DTIFS2_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2 */ +#define PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT (_PRS_CONSUMER_TIMER4_DTIFS2_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_TIMER4_DTIFS2*/ + +/* Bit fields for PRS CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_CLK */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_CLK */ +#define PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_CLK*/ + +/* Bit fields for PRS CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_IR */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_IR */ +#define PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_IR*/ + +/* Bit fields for PRS CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_RX */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_RX */ +#define PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_RX*/ + +/* Bit fields for PRS CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART0_TRIGGER*/ +#define _PRS_CONSUMER_USART0_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART0_TRIGGER */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ +#define PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART0_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART0_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_CLK */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_CLK */ +#define PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_CLK_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_CLK*/ + +/* Bit fields for PRS CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_IR */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_IR */ +#define PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_IR_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_IR*/ + +/* Bit fields for PRS CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_RX */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_RX */ +#define PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_RX_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_RX*/ + +/* Bit fields for PRS CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_USART1_TRIGGER*/ +#define _PRS_CONSUMER_USART1_TRIGGER_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_USART1_TRIGGER */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ +#define PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT (_PRS_CONSUMER_USART1_TRIGGER_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_USART1_TRIGGER*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC0 */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0 */ +#define PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC0_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC0*/ + +/* Bit fields for PRS CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_RESETVALUE 0x00000000UL /**< Default value for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_MASK 0x0000000FUL /**< Mask for PRS_CONSUMER_WDOG0_SRC1 */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_SHIFT 0 /**< Shift value for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_MASK 0xFUL /**< Bit mask for PRS_PRSSEL */ +#define _PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1 */ +#define PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT (_PRS_CONSUMER_WDOG0_SRC1_PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_CONSUMER_WDOG0_SRC1*/ + +/** @} End of group EFR32BG22_PRS_BitFields */ +/** @} End of group EFR32BG22_PRS */ +/** @} End of group Parts */ + +#endif // EFR32BG22_PRS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h index 86f5689..a286739 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_prs_signals.h @@ -1,850 +1,850 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 PRS register signal bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_PRS_SIGNALS_H -#define EFR32BG22_PRS_SIGNALS_H - -/** Synchronous signal sources enumeration: */ -#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) -#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) - -/** Synchronous signal sources enumeration aligned with register bit field: */ -#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) -#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) - -/** Synchronous signals enumeration: */ -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) - -/** Synchronous signals enumeration aligned with register bit field: */ -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) -#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) - -/** Synchronous signals and sources combined and aligned with register bit fields: */ -#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) -#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) -#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) -#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) -#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) -#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) -#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) -#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) -#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) -#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) -#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) -#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) -#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) -#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) -#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) -#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) -#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) -#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) -#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) -#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) -#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) -#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) -#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) -#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) -#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) -#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) -#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) -#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) - -/** Asynchronous signal sources enumeration: */ -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000008UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (0x00000009UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x0000000aUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x0000000bUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 (0x0000000cUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x0000000dUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x0000000eUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x0000000fUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (0x00000010UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (0x00000021UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000022UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000023UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000024UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000025UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000026UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000027UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000028UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000029UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x0000002aUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002bUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002cUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002dUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002eUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002fUL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x00000030UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (0x00000031UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (0x00000032UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000033UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000034UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000035UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x00000036UL) -#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000037UL) - -/** Asynchronous signal sources enumeration aligned with register bit field: */ -#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDML << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDM << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) -#define PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE << 8) - -/** Asynchronous signals enumeration: */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) -#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) - -/** Asynchronous signals enumeration aligned with register bit field: */ -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (_PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) -#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) - -/** Asynchronous signals and sources combined and aligned with register bit fields: */ -#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) -#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) -#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) -#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) -#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) -#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) -#define PRS_ASYNC_USART1_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS) -#define PRS_ASYNC_USART1_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX) -#define PRS_ASYNC_USART1_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS) -#define PRS_ASYNC_USART1_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA) -#define PRS_ASYNC_USART1_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX) -#define PRS_ASYNC_USART1_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC) -#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) -#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) -#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) -#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) -#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) -#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) -#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) -#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) -#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) -#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) -#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) -#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) -#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) -#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) -#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) -#define PRS_ASYNC_RTCC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0) -#define PRS_ASYNC_RTCC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1) -#define PRS_ASYNC_RTCC_CCV2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2) -#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) -#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) -#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) -#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) -#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) -#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) -#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) -#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) -#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) -#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) -#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) -#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) -#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) -#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) -#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) -#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) -#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) -#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) -#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) -#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) -#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) -#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) -#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) -#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) -#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) -#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) -#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) -#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) -#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) -#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) -#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) -#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) -#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) -#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) -#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) -#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) -#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) -#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) -#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) -#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) -#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) -#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) -#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) -#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) -#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) -#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) -#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) -#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) -#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) -#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) -#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) -#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) -#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) -#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) -#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) -#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) -#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) -#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) -#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) -#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) -#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) -#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) -#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) -#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) -#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) -#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) -#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) -#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) -#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) -#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) -#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) -#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) -#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) -#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) -#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) -#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) -#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) -#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) -#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) -#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) -#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) -#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) -#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) -#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) -#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) -#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) -#define PRS_ASYNC_PRORTC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0) -#define PRS_ASYNC_PRORTC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1) -#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) -#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) -#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) -#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) -#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) -#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) -#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) -#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) -#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) -#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) -#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) -#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) -#define PRS_ASYNC_PDML_PDMDSRPULSE (PRS_ASYNC_CH_CTRL_SOURCESEL_PDML | PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE) -#define PRS_ASYNC_EUART0_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX) -#define PRS_ASYNC_EUART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS) -#define PRS_ASYNC_EUART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX) -#define PRS_ASYNC_EUART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC) -#define PRS_ASYNC_EUART0_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL) -#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) -#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) -#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) -#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) -#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) -#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) -#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) -#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) -#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) -#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) -#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) -#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) -#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) -#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) -#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) -#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) -#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) - -/** - * Asynchronous signals and sources combined and aligned with register bit fields - * without the '_ASYNCH_' infix in order for backward compatibility: - */ -#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) -#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) -#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) -#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) -#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) -#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) -#define PRS_USART1_CS (PRS_ASYNC_USART1_CS) -#define PRS_USART1_IRTX (PRS_ASYNC_USART1_IRTX) -#define PRS_USART1_RTS (PRS_ASYNC_USART1_RTS) -#define PRS_USART1_RXDATA (PRS_ASYNC_USART1_RXDATA) -#define PRS_USART1_TX (PRS_ASYNC_USART1_TX) -#define PRS_USART1_TXC (PRS_ASYNC_USART1_TXC) -#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) -#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) -#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) -#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) -#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) -#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) -#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) -#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) -#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) -#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) -#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) -#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) -#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) -#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) -#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) -#define PRS_RTCC_CCV0 (PRS_ASYNC_RTCC_CCV0) -#define PRS_RTCC_CCV1 (PRS_ASYNC_RTCC_CCV1) -#define PRS_RTCC_CCV2 (PRS_ASYNC_RTCC_CCV2) -#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) -#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) -#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) -#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) -#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) -#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) -#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) -#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) -#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) -#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) -#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) -#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) -#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) -#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) -#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) -#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) -#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) -#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) -#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) -#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) -#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) -#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) -#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) -#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) -#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) -#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) -#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) -#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) -#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) -#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) -#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) -#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) -#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) -#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) -#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) -#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) -#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) -#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) -#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) -#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) -#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) -#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) -#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) -#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) -#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) -#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) -#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) -#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) -#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) -#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) -#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) -#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) -#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) -#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) -#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) -#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) -#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) -#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) -#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) -#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) -#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) -#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) -#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) -#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) -#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) -#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) -#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) -#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) -#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) -#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) -#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) -#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) -#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) -#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) -#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) -#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) -#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) -#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) -#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) -#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) -#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) -#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) -#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) -#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) -#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) -#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) -#define PRS_PRORTC_CCV0 (PRS_ASYNC_PRORTC_CCV0) -#define PRS_PRORTC_CCV1 (PRS_ASYNC_PRORTC_CCV1) -#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) -#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) -#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) -#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) -#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) -#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) -#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) -#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) -#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) -#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) -#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) -#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) -#define PRS_PDML_PDMDSRPULSE (PRS_ASYNC_PDML_PDMDSRPULSE) -#define PRS_EUART0_IRDATX (PRS_ASYNC_EUART0_IRDATX) -#define PRS_EUART0_RTS (PRS_ASYNC_EUART0_RTS) -#define PRS_EUART0_TX (PRS_ASYNC_EUART0_TX) -#define PRS_EUART0_TXC (PRS_ASYNC_EUART0_TXC) -#define PRS_EUART0_RXFL (PRS_ASYNC_EUART0_RXFL) -#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) -#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) -#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) -#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) -#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) -#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) -#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) -#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) -#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) -#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) -#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) -#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) -#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) -#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) -#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) -#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) -#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) - -#endif // EFR32BG22_PRS_SIGNALS_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 PRS register signal bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_PRS_SIGNALS_H +#define EFR32BG22_PRS_SIGNALS_H + +/** Synchronous signal sources enumeration: */ +#define _PRS_SYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000005UL) +#define _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000006UL) + +/** Synchronous signal sources enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SOURCESEL_NONE (_PRS_SYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) + +/** Synchronous signals enumeration: */ +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) + +/** Synchronous signals enumeration aligned with register bit field: */ +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) + +/** Synchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_SYNC_TIMER0_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_SYNC_TIMER0_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_SYNC_TIMER0_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_SYNC_TIMER0_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_SYNC_TIMER0_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_SYNC_TIMER1_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_SYNC_TIMER1_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_SYNC_TIMER1_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_SYNC_TIMER1_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_SYNC_TIMER1_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_SYNC_IADC0_SCAN_ENTRY_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_SYNC_IADC0_SCAN_TABLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_SYNC_IADC0_SINGLE_DONE (PRS_SYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_SYNC_TIMER2_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_SYNC_TIMER2_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_SYNC_TIMER2_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_SYNC_TIMER2_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_SYNC_TIMER2_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_SYNC_TIMER3_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_SYNC_TIMER3_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_SYNC_TIMER3_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_SYNC_TIMER3_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_SYNC_TIMER3_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_SYNC_TIMER4_UF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_SYNC_TIMER4_OF (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_SYNC_TIMER4_CC0 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_SYNC_TIMER4_CC1 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_SYNC_TIMER4_CC2 (PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_SYNC_CH_CTRL_SIGSEL_TIMER4CC2) + +/** Asynchronous signal sources enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (0x00000008UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (0x00000009UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (0x0000000aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (0x0000000bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 (0x0000000cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (0x0000000dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (0x0000000eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (0x0000000fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (0x00000010UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (0x00000020UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (0x00000021UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (0x00000022UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (0x00000023UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (0x00000024UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (0x00000025UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (0x00000026UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (0x00000027UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (0x00000028UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (0x00000029UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (0x0000002aUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (0x0000002bUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (0x0000002cUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (0x0000002dUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (0x0000002eUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (0x0000002fUL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (0x00000030UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (0x00000031UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (0x00000032UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (0x00000033UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (0x00000034UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (0x00000035UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (0x00000036UL) +#define _PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (0x00000037UL) + +/** Asynchronous signal sources enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SOURCESEL_NONE (_PRS_ASYNC_CH_CTRL_SOURCESEL_NONE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO (_PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CORE (_PRS_ASYNC_CH_CTRL_SOURCESEL_CORE << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH (_PRS_ASYNC_CH_CTRL_SOURCESEL_CMUH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_AGC (_PRS_ASYNC_CH_CTRL_SOURCESEL_AGC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC (_PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH (_PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_FRC (_PRS_ASYNC_CH_CTRL_SOURCESEL_FRC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER (_PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH (_PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PRS (_PRS_ASYNC_CH_CTRL_SOURCESEL_PRS << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDML (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDML << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_PDM (_PRS_ASYNC_CH_CTRL_SOURCESEL_PDM << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RACL (_PRS_ASYNC_CH_CTRL_SOURCESEL_RACL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RAC (_PRS_ASYNC_CH_CTRL_SOURCESEL_RAC << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 (_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 (_PRS_ASYNC_CH_CTRL_SOURCESEL_HFRCO0 << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMUL << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_EMU (_PRS_ASYNC_CH_CTRL_SOURCESEL_EMU << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO (_PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO << 8) +#define PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE (_PRS_ASYNC_CH_CTRL_SOURCESEL_RFSENSE << 8) + +/** Asynchronous signals enumeration: */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (0x00000005UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (0x00000006UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (0x00000007UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (0x00000002UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (0x00000003UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (0x00000004UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (0x00000000UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (0x00000001UL) +#define _PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (0x00000002UL) + +/** Asynchronous signals enumeration aligned with register bit field: */ +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW (_PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE (_PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL (_PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF (_PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT (_PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF (_PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 (_PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 (_PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE (_PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL (_PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 (_PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 (_PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2 << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM << 0) +#define PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS (_PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS << 0) + +/** Asynchronous signals and sources combined and aligned with register bit fields: */ +#define PRS_ASYNC_USART0_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0CS) +#define PRS_ASYNC_USART0_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0IRTX) +#define PRS_ASYNC_USART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RTS) +#define PRS_ASYNC_USART0_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0RXDATA) +#define PRS_ASYNC_USART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TX) +#define PRS_ASYNC_USART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART0 | PRS_ASYNC_CH_CTRL_SIGSEL_USART0TXC) +#define PRS_ASYNC_USART1_CS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1CS) +#define PRS_ASYNC_USART1_IRTX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1IRTX) +#define PRS_ASYNC_USART1_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RTS) +#define PRS_ASYNC_USART1_RXDATA (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1RXDATA) +#define PRS_ASYNC_USART1_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TX) +#define PRS_ASYNC_USART1_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_USART1 | PRS_ASYNC_CH_CTRL_SIGSEL_USART1TXC) +#define PRS_ASYNC_TIMER0_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0UF) +#define PRS_ASYNC_TIMER0_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0OF) +#define PRS_ASYNC_TIMER0_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC0) +#define PRS_ASYNC_TIMER0_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC1) +#define PRS_ASYNC_TIMER0_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER0CC2) +#define PRS_ASYNC_TIMER1_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1UF) +#define PRS_ASYNC_TIMER1_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1OF) +#define PRS_ASYNC_TIMER1_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC0) +#define PRS_ASYNC_TIMER1_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC1) +#define PRS_ASYNC_TIMER1_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER1CC2) +#define PRS_ASYNC_IADC0_SCANENTRYDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE) +#define PRS_ASYNC_IADC0_SCANTABLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE) +#define PRS_ASYNC_IADC0_SINGLEDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0 | PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE) +#define PRS_ASYNC_LETIMER0_CH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH0) +#define PRS_ASYNC_LETIMER0_CH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_LETIMER0 | PRS_ASYNC_CH_CTRL_SIGSEL_LETIMER0CH1) +#define PRS_ASYNC_RTCC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV0) +#define PRS_ASYNC_RTCC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV1) +#define PRS_ASYNC_RTCC_CCV2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RTCC | PRS_ASYNC_CH_CTRL_SIGSEL_RTCCCCV2) +#define PRS_ASYNC_BURTC_COMP (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCCOMP) +#define PRS_ASYNC_BURTC_OVERFLOW (PRS_ASYNC_CH_CTRL_SOURCESEL_BURTC | PRS_ASYNC_CH_CTRL_SIGSEL_BURTCOVERFLOW) +#define PRS_ASYNC_GPIO_PIN0 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN0) +#define PRS_ASYNC_GPIO_PIN1 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN1) +#define PRS_ASYNC_GPIO_PIN2 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN2) +#define PRS_ASYNC_GPIO_PIN3 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN3) +#define PRS_ASYNC_GPIO_PIN4 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN4) +#define PRS_ASYNC_GPIO_PIN5 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN5) +#define PRS_ASYNC_GPIO_PIN6 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN6) +#define PRS_ASYNC_GPIO_PIN7 (PRS_ASYNC_CH_CTRL_SOURCESEL_GPIO | PRS_ASYNC_CH_CTRL_SIGSEL_GPIOPIN7) +#define PRS_ASYNC_TIMER2_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF) +#define PRS_ASYNC_TIMER2_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF) +#define PRS_ASYNC_TIMER2_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0) +#define PRS_ASYNC_TIMER2_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1) +#define PRS_ASYNC_TIMER2_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2) +#define PRS_ASYNC_TIMER3_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3UF) +#define PRS_ASYNC_TIMER3_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3OF) +#define PRS_ASYNC_TIMER3_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC0) +#define PRS_ASYNC_TIMER3_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC1) +#define PRS_ASYNC_TIMER3_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER3CC2) +#define PRS_ASYNC_CORE_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT0) +#define PRS_ASYNC_CORE_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT1) +#define PRS_ASYNC_CORE_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT2) +#define PRS_ASYNC_CORE_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_CORE | PRS_ASYNC_CH_CTRL_SIGSEL_CORECTIOUT3) +#define PRS_ASYNC_CMUL_CLKOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT0) +#define PRS_ASYNC_CMUL_CLKOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT1) +#define PRS_ASYNC_CMUL_CLKOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_CMUL | PRS_ASYNC_CH_CTRL_SIGSEL_CMULCLKOUT2) +#define PRS_ASYNC_AGCL_CCA (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCA) +#define PRS_ASYNC_AGCL_CCAREQ (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLCCAREQ) +#define PRS_ASYNC_AGCL_GAINADJUST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINADJUST) +#define PRS_ASYNC_AGCL_GAINOK (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINOK) +#define PRS_ASYNC_AGCL_GAINREDUCED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLGAINREDUCED) +#define PRS_ASYNC_AGCL_IFPKI1 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKI1) +#define PRS_ASYNC_AGCL_IFPKQ2 (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKQ2) +#define PRS_ASYNC_AGCL_IFPKRST (PRS_ASYNC_CH_CTRL_SOURCESEL_AGCL | PRS_ASYNC_CH_CTRL_SIGSEL_AGCLIFPKRST) +#define PRS_ASYNC_AGC_PEAKDET (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPEAKDET) +#define PRS_ASYNC_AGC_PROPAGATED (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCPROPAGATED) +#define PRS_ASYNC_AGC_RSSIDONE (PRS_ASYNC_CH_CTRL_SOURCESEL_AGC | PRS_ASYNC_CH_CTRL_SIGSEL_AGCRSSIDONE) +#define PRS_ASYNC_BUFC_THR0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR0) +#define PRS_ASYNC_BUFC_THR1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR1) +#define PRS_ASYNC_BUFC_THR2 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR2) +#define PRS_ASYNC_BUFC_THR3 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCTHR3) +#define PRS_ASYNC_BUFC_CNT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT0) +#define PRS_ASYNC_BUFC_CNT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCCNT1) +#define PRS_ASYNC_BUFC_FULL (PRS_ASYNC_CH_CTRL_SOURCESEL_BUFC | PRS_ASYNC_CH_CTRL_SIGSEL_BUFCFULL) +#define PRS_ASYNC_MODEML_ADVANCE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLADVANCE) +#define PRS_ASYNC_MODEML_ANT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT0) +#define PRS_ASYNC_MODEML_ANT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLANT1) +#define PRS_ASYNC_MODEML_COHDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSADET) +#define PRS_ASYNC_MODEML_COHDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLCOHDSALIVE) +#define PRS_ASYNC_MODEML_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDCLK) +#define PRS_ASYNC_MODEML_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLDOUT) +#define PRS_ASYNC_MODEML_FRAMEDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEML | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLFRAMEDET) +#define PRS_ASYNC_MODEM_FRAMESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMFRAMESENT) +#define PRS_ASYNC_MODEM_LOWCORR (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLOWCORR) +#define PRS_ASYNC_MODEM_LRDSADET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSADET) +#define PRS_ASYNC_MODEM_LRDSALIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMLRDSALIVE) +#define PRS_ASYNC_MODEM_NEWSYMBOL (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWSYMBOL) +#define PRS_ASYNC_MODEM_NEWWND (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMNEWWND) +#define PRS_ASYNC_MODEM_POSTPONE (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPOSTPONE) +#define PRS_ASYNC_MODEM_PREDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEM | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMPREDET) +#define PRS_ASYNC_MODEMH_PRESENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHPRESENT) +#define PRS_ASYNC_MODEMH_RSSIJUMP (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHRSSIJUMP) +#define PRS_ASYNC_MODEMH_SYNCSENT (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHSYNCSENT) +#define PRS_ASYNC_MODEMH_TIMDET (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHTIMDET) +#define PRS_ASYNC_MODEMH_WEAK (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHWEAK) +#define PRS_ASYNC_MODEMH_EOF (PRS_ASYNC_CH_CTRL_SOURCESEL_MODEMH | PRS_ASYNC_CH_CTRL_SIGSEL_MODEMHEOF) +#define PRS_ASYNC_FRC_DCLK (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDCLK) +#define PRS_ASYNC_FRC_DOUT (PRS_ASYNC_CH_CTRL_SOURCESEL_FRC | PRS_ASYNC_CH_CTRL_SIGSEL_FRCDOUT) +#define PRS_ASYNC_PROTIMERL_BOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBOF) +#define PRS_ASYNC_PROTIMERL_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC0) +#define PRS_ASYNC_PROTIMERL_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC1) +#define PRS_ASYNC_PROTIMERL_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC2) +#define PRS_ASYNC_PROTIMERL_CC3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC3) +#define PRS_ASYNC_PROTIMERL_CC4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLCC4) +#define PRS_ASYNC_PROTIMERL_LBTF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTF) +#define PRS_ASYNC_PROTIMERL_LBTR (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMERL | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLLBTR) +#define PRS_ASYNC_PROTIMER_LBTS (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERLBTS) +#define PRS_ASYNC_PROTIMER_POF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERPOF) +#define PRS_ASYNC_PROTIMER_T0MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0MATCH) +#define PRS_ASYNC_PROTIMER_T0UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT0UF) +#define PRS_ASYNC_PROTIMER_T1MATCH (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1MATCH) +#define PRS_ASYNC_PROTIMER_T1UF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERT1UF) +#define PRS_ASYNC_PROTIMER_WOF (PRS_ASYNC_CH_CTRL_SOURCESEL_PROTIMER | PRS_ASYNC_CH_CTRL_SIGSEL_PROTIMERWOF) +#define PRS_ASYNC_SYNTH_MUX0 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX0) +#define PRS_ASYNC_SYNTH_MUX1 (PRS_ASYNC_CH_CTRL_SOURCESEL_SYNTH | PRS_ASYNC_CH_CTRL_SIGSEL_SYNTHMUX1) +#define PRS_ASYNC_PRORTC_CCV0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV0) +#define PRS_ASYNC_PRORTC_CCV1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRORTC | PRS_ASYNC_CH_CTRL_SIGSEL_PRORTCCCV1) +#define PRS_ASYNC_PRSL_ASYNCH0 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH0) +#define PRS_ASYNC_PRSL_ASYNCH1 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH1) +#define PRS_ASYNC_PRSL_ASYNCH2 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH2) +#define PRS_ASYNC_PRSL_ASYNCH3 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH3) +#define PRS_ASYNC_PRSL_ASYNCH4 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH4) +#define PRS_ASYNC_PRSL_ASYNCH5 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH5) +#define PRS_ASYNC_PRSL_ASYNCH6 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH6) +#define PRS_ASYNC_PRSL_ASYNCH7 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRSL | PRS_ASYNC_CH_CTRL_SIGSEL_PRSLASYNCH7) +#define PRS_ASYNC_PRS_ASYNCH8 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH8) +#define PRS_ASYNC_PRS_ASYNCH9 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH9) +#define PRS_ASYNC_PRS_ASYNCH10 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH10) +#define PRS_ASYNC_PRS_ASYNCH11 (PRS_ASYNC_CH_CTRL_SOURCESEL_PRS | PRS_ASYNC_CH_CTRL_SIGSEL_PRSASYNCH11) +#define PRS_ASYNC_PDML_PDMDSRPULSE (PRS_ASYNC_CH_CTRL_SOURCESEL_PDML | PRS_ASYNC_CH_CTRL_SIGSEL_PDMLPDMDSRPULSE) +#define PRS_ASYNC_EUART0_IRDATX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0IRDATX) +#define PRS_ASYNC_EUART0_RTS (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RTS) +#define PRS_ASYNC_EUART0_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TX) +#define PRS_ASYNC_EUART0_TXC (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0TXC) +#define PRS_ASYNC_EUART0_RXFL (PRS_ASYNC_CH_CTRL_SOURCESEL_EUART0 | PRS_ASYNC_CH_CTRL_SIGSEL_EUART0RXFL) +#define PRS_ASYNC_RACL_ACTIVE (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLACTIVE) +#define PRS_ASYNC_RACL_LNAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLLNAEN) +#define PRS_ASYNC_RACL_PAEN (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLPAEN) +#define PRS_ASYNC_RACL_RX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLRX) +#define PRS_ASYNC_RACL_TX (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLTX) +#define PRS_ASYNC_RACL_CTIOUT0 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT0) +#define PRS_ASYNC_RACL_CTIOUT1 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT1) +#define PRS_ASYNC_RACL_CTIOUT2 (PRS_ASYNC_CH_CTRL_SOURCESEL_RACL | PRS_ASYNC_CH_CTRL_SIGSEL_RACLCTIOUT2) +#define PRS_ASYNC_RAC_CTIOUT3 (PRS_ASYNC_CH_CTRL_SOURCESEL_RAC | PRS_ASYNC_CH_CTRL_SIGSEL_RACCTIOUT3) +#define PRS_ASYNC_TIMER4_UF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4UF) +#define PRS_ASYNC_TIMER4_OF (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4OF) +#define PRS_ASYNC_TIMER4_CC0 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC0) +#define PRS_ASYNC_TIMER4_CC1 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC1) +#define PRS_ASYNC_TIMER4_CC2 (PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4 | PRS_ASYNC_CH_CTRL_SIGSEL_TIMER4CC2) +#define PRS_ASYNC_LFRCO_CALMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOCALMEAS) +#define PRS_ASYNC_LFRCO_SDM (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOSDM) +#define PRS_ASYNC_LFRCO_TCMEAS (PRS_ASYNC_CH_CTRL_SOURCESEL_LFRCO | PRS_ASYNC_CH_CTRL_SIGSEL_LFRCOTCMEAS) + +/** + * Asynchronous signals and sources combined and aligned with register bit fields + * without the '_ASYNCH_' infix in order for backward compatibility: + */ +#define PRS_USART0_CS (PRS_ASYNC_USART0_CS) +#define PRS_USART0_IRTX (PRS_ASYNC_USART0_IRTX) +#define PRS_USART0_RTS (PRS_ASYNC_USART0_RTS) +#define PRS_USART0_RXDATA (PRS_ASYNC_USART0_RXDATA) +#define PRS_USART0_TX (PRS_ASYNC_USART0_TX) +#define PRS_USART0_TXC (PRS_ASYNC_USART0_TXC) +#define PRS_USART1_CS (PRS_ASYNC_USART1_CS) +#define PRS_USART1_IRTX (PRS_ASYNC_USART1_IRTX) +#define PRS_USART1_RTS (PRS_ASYNC_USART1_RTS) +#define PRS_USART1_RXDATA (PRS_ASYNC_USART1_RXDATA) +#define PRS_USART1_TX (PRS_ASYNC_USART1_TX) +#define PRS_USART1_TXC (PRS_ASYNC_USART1_TXC) +#define PRS_TIMER0_UF (PRS_ASYNC_TIMER0_UF) +#define PRS_TIMER0_OF (PRS_ASYNC_TIMER0_OF) +#define PRS_TIMER0_CC0 (PRS_ASYNC_TIMER0_CC0) +#define PRS_TIMER0_CC1 (PRS_ASYNC_TIMER0_CC1) +#define PRS_TIMER0_CC2 (PRS_ASYNC_TIMER0_CC2) +#define PRS_TIMER1_UF (PRS_ASYNC_TIMER1_UF) +#define PRS_TIMER1_OF (PRS_ASYNC_TIMER1_OF) +#define PRS_TIMER1_CC0 (PRS_ASYNC_TIMER1_CC0) +#define PRS_TIMER1_CC1 (PRS_ASYNC_TIMER1_CC1) +#define PRS_TIMER1_CC2 (PRS_ASYNC_TIMER1_CC2) +#define PRS_IADC0_SCANENTRYDONE (PRS_ASYNC_IADC0_SCANENTRYDONE) +#define PRS_IADC0_SCANTABLEDONE (PRS_ASYNC_IADC0_SCANTABLEDONE) +#define PRS_IADC0_SINGLEDONE (PRS_ASYNC_IADC0_SINGLEDONE) +#define PRS_LETIMER0_CH0 (PRS_ASYNC_LETIMER0_CH0) +#define PRS_LETIMER0_CH1 (PRS_ASYNC_LETIMER0_CH1) +#define PRS_RTCC_CCV0 (PRS_ASYNC_RTCC_CCV0) +#define PRS_RTCC_CCV1 (PRS_ASYNC_RTCC_CCV1) +#define PRS_RTCC_CCV2 (PRS_ASYNC_RTCC_CCV2) +#define PRS_BURTC_COMP (PRS_ASYNC_BURTC_COMP) +#define PRS_BURTC_OVERFLOW (PRS_ASYNC_BURTC_OVERFLOW) +#define PRS_GPIO_PIN0 (PRS_ASYNC_GPIO_PIN0) +#define PRS_GPIO_PIN1 (PRS_ASYNC_GPIO_PIN1) +#define PRS_GPIO_PIN2 (PRS_ASYNC_GPIO_PIN2) +#define PRS_GPIO_PIN3 (PRS_ASYNC_GPIO_PIN3) +#define PRS_GPIO_PIN4 (PRS_ASYNC_GPIO_PIN4) +#define PRS_GPIO_PIN5 (PRS_ASYNC_GPIO_PIN5) +#define PRS_GPIO_PIN6 (PRS_ASYNC_GPIO_PIN6) +#define PRS_GPIO_PIN7 (PRS_ASYNC_GPIO_PIN7) +#define PRS_TIMER2_UF (PRS_ASYNC_TIMER2_UF) +#define PRS_TIMER2_OF (PRS_ASYNC_TIMER2_OF) +#define PRS_TIMER2_CC0 (PRS_ASYNC_TIMER2_CC0) +#define PRS_TIMER2_CC1 (PRS_ASYNC_TIMER2_CC1) +#define PRS_TIMER2_CC2 (PRS_ASYNC_TIMER2_CC2) +#define PRS_TIMER3_UF (PRS_ASYNC_TIMER3_UF) +#define PRS_TIMER3_OF (PRS_ASYNC_TIMER3_OF) +#define PRS_TIMER3_CC0 (PRS_ASYNC_TIMER3_CC0) +#define PRS_TIMER3_CC1 (PRS_ASYNC_TIMER3_CC1) +#define PRS_TIMER3_CC2 (PRS_ASYNC_TIMER3_CC2) +#define PRS_CORE_CTIOUT0 (PRS_ASYNC_CORE_CTIOUT0) +#define PRS_CORE_CTIOUT1 (PRS_ASYNC_CORE_CTIOUT1) +#define PRS_CORE_CTIOUT2 (PRS_ASYNC_CORE_CTIOUT2) +#define PRS_CORE_CTIOUT3 (PRS_ASYNC_CORE_CTIOUT3) +#define PRS_CMUL_CLKOUT0 (PRS_ASYNC_CMUL_CLKOUT0) +#define PRS_CMUL_CLKOUT1 (PRS_ASYNC_CMUL_CLKOUT1) +#define PRS_CMUL_CLKOUT2 (PRS_ASYNC_CMUL_CLKOUT2) +#define PRS_AGCL_CCA (PRS_ASYNC_AGCL_CCA) +#define PRS_AGCL_CCAREQ (PRS_ASYNC_AGCL_CCAREQ) +#define PRS_AGCL_GAINADJUST (PRS_ASYNC_AGCL_GAINADJUST) +#define PRS_AGCL_GAINOK (PRS_ASYNC_AGCL_GAINOK) +#define PRS_AGCL_GAINREDUCED (PRS_ASYNC_AGCL_GAINREDUCED) +#define PRS_AGCL_IFPKI1 (PRS_ASYNC_AGCL_IFPKI1) +#define PRS_AGCL_IFPKQ2 (PRS_ASYNC_AGCL_IFPKQ2) +#define PRS_AGCL_IFPKRST (PRS_ASYNC_AGCL_IFPKRST) +#define PRS_AGC_PEAKDET (PRS_ASYNC_AGC_PEAKDET) +#define PRS_AGC_PROPAGATED (PRS_ASYNC_AGC_PROPAGATED) +#define PRS_AGC_RSSIDONE (PRS_ASYNC_AGC_RSSIDONE) +#define PRS_BUFC_THR0 (PRS_ASYNC_BUFC_THR0) +#define PRS_BUFC_THR1 (PRS_ASYNC_BUFC_THR1) +#define PRS_BUFC_THR2 (PRS_ASYNC_BUFC_THR2) +#define PRS_BUFC_THR3 (PRS_ASYNC_BUFC_THR3) +#define PRS_BUFC_CNT0 (PRS_ASYNC_BUFC_CNT0) +#define PRS_BUFC_CNT1 (PRS_ASYNC_BUFC_CNT1) +#define PRS_BUFC_FULL (PRS_ASYNC_BUFC_FULL) +#define PRS_MODEML_ADVANCE (PRS_ASYNC_MODEML_ADVANCE) +#define PRS_MODEML_ANT0 (PRS_ASYNC_MODEML_ANT0) +#define PRS_MODEML_ANT1 (PRS_ASYNC_MODEML_ANT1) +#define PRS_MODEML_COHDSADET (PRS_ASYNC_MODEML_COHDSADET) +#define PRS_MODEML_COHDSALIVE (PRS_ASYNC_MODEML_COHDSALIVE) +#define PRS_MODEML_DCLK (PRS_ASYNC_MODEML_DCLK) +#define PRS_MODEML_DOUT (PRS_ASYNC_MODEML_DOUT) +#define PRS_MODEML_FRAMEDET (PRS_ASYNC_MODEML_FRAMEDET) +#define PRS_MODEM_FRAMESENT (PRS_ASYNC_MODEM_FRAMESENT) +#define PRS_MODEM_LOWCORR (PRS_ASYNC_MODEM_LOWCORR) +#define PRS_MODEM_LRDSADET (PRS_ASYNC_MODEM_LRDSADET) +#define PRS_MODEM_LRDSALIVE (PRS_ASYNC_MODEM_LRDSALIVE) +#define PRS_MODEM_NEWSYMBOL (PRS_ASYNC_MODEM_NEWSYMBOL) +#define PRS_MODEM_NEWWND (PRS_ASYNC_MODEM_NEWWND) +#define PRS_MODEM_POSTPONE (PRS_ASYNC_MODEM_POSTPONE) +#define PRS_MODEM_PREDET (PRS_ASYNC_MODEM_PREDET) +#define PRS_MODEMH_PRESENT (PRS_ASYNC_MODEMH_PRESENT) +#define PRS_MODEMH_RSSIJUMP (PRS_ASYNC_MODEMH_RSSIJUMP) +#define PRS_MODEMH_SYNCSENT (PRS_ASYNC_MODEMH_SYNCSENT) +#define PRS_MODEMH_TIMDET (PRS_ASYNC_MODEMH_TIMDET) +#define PRS_MODEMH_WEAK (PRS_ASYNC_MODEMH_WEAK) +#define PRS_MODEMH_EOF (PRS_ASYNC_MODEMH_EOF) +#define PRS_FRC_DCLK (PRS_ASYNC_FRC_DCLK) +#define PRS_FRC_DOUT (PRS_ASYNC_FRC_DOUT) +#define PRS_PROTIMERL_BOF (PRS_ASYNC_PROTIMERL_BOF) +#define PRS_PROTIMERL_CC0 (PRS_ASYNC_PROTIMERL_CC0) +#define PRS_PROTIMERL_CC1 (PRS_ASYNC_PROTIMERL_CC1) +#define PRS_PROTIMERL_CC2 (PRS_ASYNC_PROTIMERL_CC2) +#define PRS_PROTIMERL_CC3 (PRS_ASYNC_PROTIMERL_CC3) +#define PRS_PROTIMERL_CC4 (PRS_ASYNC_PROTIMERL_CC4) +#define PRS_PROTIMERL_LBTF (PRS_ASYNC_PROTIMERL_LBTF) +#define PRS_PROTIMERL_LBTR (PRS_ASYNC_PROTIMERL_LBTR) +#define PRS_PROTIMER_LBTS (PRS_ASYNC_PROTIMER_LBTS) +#define PRS_PROTIMER_POF (PRS_ASYNC_PROTIMER_POF) +#define PRS_PROTIMER_T0MATCH (PRS_ASYNC_PROTIMER_T0MATCH) +#define PRS_PROTIMER_T0UF (PRS_ASYNC_PROTIMER_T0UF) +#define PRS_PROTIMER_T1MATCH (PRS_ASYNC_PROTIMER_T1MATCH) +#define PRS_PROTIMER_T1UF (PRS_ASYNC_PROTIMER_T1UF) +#define PRS_PROTIMER_WOF (PRS_ASYNC_PROTIMER_WOF) +#define PRS_SYNTH_MUX0 (PRS_ASYNC_SYNTH_MUX0) +#define PRS_SYNTH_MUX1 (PRS_ASYNC_SYNTH_MUX1) +#define PRS_PRORTC_CCV0 (PRS_ASYNC_PRORTC_CCV0) +#define PRS_PRORTC_CCV1 (PRS_ASYNC_PRORTC_CCV1) +#define PRS_PRSL_ASYNCH0 (PRS_ASYNC_PRSL_ASYNCH0) +#define PRS_PRSL_ASYNCH1 (PRS_ASYNC_PRSL_ASYNCH1) +#define PRS_PRSL_ASYNCH2 (PRS_ASYNC_PRSL_ASYNCH2) +#define PRS_PRSL_ASYNCH3 (PRS_ASYNC_PRSL_ASYNCH3) +#define PRS_PRSL_ASYNCH4 (PRS_ASYNC_PRSL_ASYNCH4) +#define PRS_PRSL_ASYNCH5 (PRS_ASYNC_PRSL_ASYNCH5) +#define PRS_PRSL_ASYNCH6 (PRS_ASYNC_PRSL_ASYNCH6) +#define PRS_PRSL_ASYNCH7 (PRS_ASYNC_PRSL_ASYNCH7) +#define PRS_PRS_ASYNCH8 (PRS_ASYNC_PRS_ASYNCH8) +#define PRS_PRS_ASYNCH9 (PRS_ASYNC_PRS_ASYNCH9) +#define PRS_PRS_ASYNCH10 (PRS_ASYNC_PRS_ASYNCH10) +#define PRS_PRS_ASYNCH11 (PRS_ASYNC_PRS_ASYNCH11) +#define PRS_PDML_PDMDSRPULSE (PRS_ASYNC_PDML_PDMDSRPULSE) +#define PRS_EUART0_IRDATX (PRS_ASYNC_EUART0_IRDATX) +#define PRS_EUART0_RTS (PRS_ASYNC_EUART0_RTS) +#define PRS_EUART0_TX (PRS_ASYNC_EUART0_TX) +#define PRS_EUART0_TXC (PRS_ASYNC_EUART0_TXC) +#define PRS_EUART0_RXFL (PRS_ASYNC_EUART0_RXFL) +#define PRS_RACL_ACTIVE (PRS_ASYNC_RACL_ACTIVE) +#define PRS_RACL_LNAEN (PRS_ASYNC_RACL_LNAEN) +#define PRS_RACL_PAEN (PRS_ASYNC_RACL_PAEN) +#define PRS_RACL_RX (PRS_ASYNC_RACL_RX) +#define PRS_RACL_TX (PRS_ASYNC_RACL_TX) +#define PRS_RACL_CTIOUT0 (PRS_ASYNC_RACL_CTIOUT0) +#define PRS_RACL_CTIOUT1 (PRS_ASYNC_RACL_CTIOUT1) +#define PRS_RACL_CTIOUT2 (PRS_ASYNC_RACL_CTIOUT2) +#define PRS_RAC_CTIOUT3 (PRS_ASYNC_RAC_CTIOUT3) +#define PRS_TIMER4_UF (PRS_ASYNC_TIMER4_UF) +#define PRS_TIMER4_OF (PRS_ASYNC_TIMER4_OF) +#define PRS_TIMER4_CC0 (PRS_ASYNC_TIMER4_CC0) +#define PRS_TIMER4_CC1 (PRS_ASYNC_TIMER4_CC1) +#define PRS_TIMER4_CC2 (PRS_ASYNC_TIMER4_CC2) +#define PRS_LFRCO_CALMEAS (PRS_ASYNC_LFRCO_CALMEAS) +#define PRS_LFRCO_SDM (PRS_ASYNC_LFRCO_SDM) +#define PRS_LFRCO_TCMEAS (PRS_ASYNC_LFRCO_TCMEAS) + +#endif // EFR32BG22_PRS_SIGNALS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h index 4f4b967..8f6d44c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_rtcc.h @@ -1,422 +1,422 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 RTCC register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_RTCC_H -#define EFR32BG22_RTCC_H -#define RTCC_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_RTCC RTCC - * @{ - * @brief EFR32BG22 RTCC Register Declaration. - *****************************************************************************/ - -/** RTCC CC Register Group Declaration. */ -typedef struct { - __IOM uint32_t CTRL; /**< CC Channel Control Register */ - __IOM uint32_t OCVALUE; /**< Output Compare Value Register */ - __IM uint32_t ICVALUE; /**< Input Capture Value Register */ -} RTCC_CC_TypeDef; - -/** RTCC Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP VERSION */ - __IOM uint32_t EN; /**< Module Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status register */ - __IOM uint32_t IF; /**< RTCC Interrupt Flags */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Valu... */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK; /**< Configuration Lock Register */ - RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ - uint32_t RESERVED0[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP VERSION */ - __IOM uint32_t EN_SET; /**< Module Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status register */ - __IOM uint32_t IF_SET; /**< RTCC Interrupt Flags */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - __IM uint32_t COMBCNT_SET; /**< Combined Pre-Counter and Counter Valu... */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ - RTCC_CC_TypeDef CC_SET[3U]; /**< Capture/Compare Channel */ - uint32_t RESERVED1[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ - __IOM uint32_t EN_CLR; /**< Module Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status register */ - __IOM uint32_t IF_CLR; /**< RTCC Interrupt Flags */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - __IM uint32_t COMBCNT_CLR; /**< Combined Pre-Counter and Counter Valu... */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ - RTCC_CC_TypeDef CC_CLR[3U]; /**< Capture/Compare Channel */ - uint32_t RESERVED2[1003U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ - __IOM uint32_t EN_TGL; /**< Module Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status register */ - __IOM uint32_t IF_TGL; /**< RTCC Interrupt Flags */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - __IM uint32_t COMBCNT_TGL; /**< Combined Pre-Counter and Counter Valu... */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ - __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ - RTCC_CC_TypeDef CC_TGL[3U]; /**< Capture/Compare Channel */ -} RTCC_TypeDef; -/** @} End of group EFR32BG22_RTCC */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_RTCC - * @{ - * @defgroup EFR32BG22_RTCC_BitFields RTCC Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for RTCC IPVERSION */ -#define _RTCC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for RTCC_IPVERSION */ -#define _RTCC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RTCC_IPVERSION */ -#define _RTCC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RTCC_IPVERSION */ -#define _RTCC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IPVERSION */ -#define _RTCC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for RTCC_IPVERSION */ -#define RTCC_IPVERSION_IPVERSION_DEFAULT (_RTCC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IPVERSION */ - -/* Bit fields for RTCC EN */ -#define _RTCC_EN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EN */ -#define _RTCC_EN_MASK 0x00000001UL /**< Mask for RTCC_EN */ -#define RTCC_EN_EN (0x1UL << 0) /**< RTCC Enable */ -#define _RTCC_EN_EN_SHIFT 0 /**< Shift value for RTCC_EN */ -#define _RTCC_EN_EN_MASK 0x1UL /**< Bit mask for RTCC_EN */ -#define _RTCC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EN */ -#define RTCC_EN_EN_DEFAULT (_RTCC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EN */ - -/* Bit fields for RTCC CFG */ -#define _RTCC_CFG_RESETVALUE 0x00000000UL /**< Default value for RTCC_CFG */ -#define _RTCC_CFG_MASK 0x000000FFUL /**< Mask for RTCC_CFG */ -#define RTCC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ -#define _RTCC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for RTCC_DEBUGRUN */ -#define _RTCC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for RTCC_DEBUGRUN */ -#define _RTCC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ -#define _RTCC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for RTCC_CFG */ -#define _RTCC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for RTCC_CFG */ -#define RTCC_CFG_DEBUGRUN_DEFAULT (_RTCC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_DEBUGRUN_X0 (_RTCC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for RTCC_CFG */ -#define RTCC_CFG_DEBUGRUN_X1 (_RTCC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for RTCC_CFG */ -#define RTCC_CFG_PRECNTCCV0TOP (0x1UL << 1) /**< Pre-counter CCV0 top value enable. */ -#define _RTCC_CFG_PRECNTCCV0TOP_SHIFT 1 /**< Shift value for RTCC_PRECNTCCV0TOP */ -#define _RTCC_CFG_PRECNTCCV0TOP_MASK 0x2UL /**< Bit mask for RTCC_PRECNTCCV0TOP */ -#define _RTCC_CFG_PRECNTCCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_PRECNTCCV0TOP_DEFAULT (_RTCC_CFG_PRECNTCCV0TOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_CNTCCV1TOP (0x1UL << 2) /**< CCV1 top value enable */ -#define _RTCC_CFG_CNTCCV1TOP_SHIFT 2 /**< Shift value for RTCC_CNTCCV1TOP */ -#define _RTCC_CFG_CNTCCV1TOP_MASK 0x4UL /**< Bit mask for RTCC_CNTCCV1TOP */ -#define _RTCC_CFG_CNTCCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_CNTCCV1TOP_DEFAULT (_RTCC_CFG_CNTCCV1TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_CNTTICK (0x1UL << 3) /**< Counter prescaler mode. */ -#define _RTCC_CFG_CNTTICK_SHIFT 3 /**< Shift value for RTCC_CNTTICK */ -#define _RTCC_CFG_CNTTICK_MASK 0x8UL /**< Bit mask for RTCC_CNTTICK */ -#define _RTCC_CFG_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ -#define _RTCC_CFG_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CFG */ -#define _RTCC_CFG_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CFG */ -#define RTCC_CFG_CNTTICK_DEFAULT (_RTCC_CFG_CNTTICK_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_CNTTICK_PRESC (_RTCC_CFG_CNTTICK_PRESC << 3) /**< Shifted mode PRESC for RTCC_CFG */ -#define RTCC_CFG_CNTTICK_CCV0MATCH (_RTCC_CFG_CNTTICK_CCV0MATCH << 3) /**< Shifted mode CCV0MATCH for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for RTCC_CNTPRESC */ -#define _RTCC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for RTCC_CNTPRESC */ -#define _RTCC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CFG */ -#define _RTCC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DEFAULT (_RTCC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV1 (_RTCC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV2 (_RTCC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV4 (_RTCC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV8 (_RTCC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV16 (_RTCC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV32 (_RTCC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV64 (_RTCC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV128 (_RTCC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV256 (_RTCC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV512 (_RTCC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV1024 (_RTCC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV2048 (_RTCC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV4096 (_RTCC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV8192 (_RTCC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV16384 (_RTCC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for RTCC_CFG */ -#define RTCC_CFG_CNTPRESC_DIV32768 (_RTCC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for RTCC_CFG */ - -/* Bit fields for RTCC CMD */ -#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ -#define _RTCC_CMD_MASK 0x00000003UL /**< Mask for RTCC_CMD */ -#define RTCC_CMD_START (0x1UL << 0) /**< Start RTCC main counter */ -#define _RTCC_CMD_START_SHIFT 0 /**< Shift value for RTCC_START */ -#define _RTCC_CMD_START_MASK 0x1UL /**< Bit mask for RTCC_START */ -#define _RTCC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ -#define RTCC_CMD_START_DEFAULT (_RTCC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ -#define RTCC_CMD_STOP (0x1UL << 1) /**< Stop RTCC main counter */ -#define _RTCC_CMD_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ -#define _RTCC_CMD_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ -#define _RTCC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ -#define RTCC_CMD_STOP_DEFAULT (_RTCC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CMD */ - -/* Bit fields for RTCC STATUS */ -#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ -#define _RTCC_STATUS_MASK 0x00000003UL /**< Mask for RTCC_STATUS */ -#define RTCC_STATUS_RUNNING (0x1UL << 0) /**< RTCC running status */ -#define _RTCC_STATUS_RUNNING_SHIFT 0 /**< Shift value for RTCC_RUNNING */ -#define _RTCC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for RTCC_RUNNING */ -#define _RTCC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ -#define RTCC_STATUS_RUNNING_DEFAULT (_RTCC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ -#define RTCC_STATUS_RTCCLOCKSTATUS (0x1UL << 1) /**< Lock Status */ -#define _RTCC_STATUS_RTCCLOCKSTATUS_SHIFT 1 /**< Shift value for RTCC_RTCCLOCKSTATUS */ -#define _RTCC_STATUS_RTCCLOCKSTATUS_MASK 0x2UL /**< Bit mask for RTCC_RTCCLOCKSTATUS */ -#define _RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ -#define _RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_STATUS */ -#define _RTCC_STATUS_RTCCLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_STATUS */ -#define RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT (_RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_STATUS */ -#define RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for RTCC_STATUS */ -#define RTCC_STATUS_RTCCLOCKSTATUS_LOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for RTCC_STATUS */ - -/* Bit fields for RTCC IF */ -#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ -#define _RTCC_IF_MASK 0x000003FFUL /**< Mask for RTCC_IF */ -#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ -#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ -#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ -#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CNTTICK (0x1UL << 1) /**< Main counter tick */ -#define _RTCC_IF_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ -#define _RTCC_IF_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ -#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Flag */ -#define _RTCC_IF_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ -#define _RTCC_IF_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ -#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Flag */ -#define _RTCC_IF_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ -#define _RTCC_IF_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ -#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Flag */ -#define _RTCC_IF_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ -#define _RTCC_IF_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ -#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ -#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ - -/* Bit fields for RTCC IEN */ -#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ -#define _RTCC_IEN_MASK 0x000003FFUL /**< Mask for RTCC_IEN */ -#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ -#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ -#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ -#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CNTTICK (0x1UL << 1) /**< CNTTICK Interrupt Enable */ -#define _RTCC_IEN_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ -#define _RTCC_IEN_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ -#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Enable */ -#define _RTCC_IEN_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ -#define _RTCC_IEN_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ -#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Enable */ -#define _RTCC_IEN_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ -#define _RTCC_IEN_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ -#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Enable */ -#define _RTCC_IEN_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ -#define _RTCC_IEN_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ -#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ -#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ - -/* Bit fields for RTCC PRECNT */ -#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ -#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ -#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ -#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ -#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ -#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ - -/* Bit fields for RTCC CNT */ -#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ -#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ -#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ -#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ -#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ -#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ - -/* Bit fields for RTCC COMBCNT */ -#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ -#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ -#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ -#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ -#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ -#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ -#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ -#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ -#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ -#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ - -/* Bit fields for RTCC SYNCBUSY */ -#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ -#define _RTCC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ -#define _RTCC_SYNCBUSY_START_SHIFT 0 /**< Shift value for RTCC_START */ -#define _RTCC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for RTCC_START */ -#define _RTCC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_START_DEFAULT (_RTCC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ -#define _RTCC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ -#define _RTCC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ -#define _RTCC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_STOP_DEFAULT (_RTCC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ -#define _RTCC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for RTCC_PRECNT */ -#define _RTCC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for RTCC_PRECNT */ -#define _RTCC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_PRECNT_DEFAULT (_RTCC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ -#define _RTCC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for RTCC_CNT */ -#define _RTCC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for RTCC_CNT */ -#define _RTCC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ -#define RTCC_SYNCBUSY_CNT_DEFAULT (_RTCC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ - -/* Bit fields for RTCC LOCK */ -#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ -#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ -#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ -#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ -#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ -#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ -#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ -#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ - -/* Bit fields for RTCC CC_CTRL */ -#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_MASK 0x000000FFUL /**< Mask for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for RTCC_MODE */ -#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for RTCC_MODE */ -#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for RTCC_CMOA */ -#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for RTCC_CMOA */ -#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_COMPBASE (0x1UL << 4) /**< Capture compare channel comparison base. */ -#define _RTCC_CC_CTRL_COMPBASE_SHIFT 4 /**< Shift value for RTCC_COMPBASE */ -#define _RTCC_CC_CTRL_COMPBASE_MASK 0x10UL /**< Bit mask for RTCC_COMPBASE */ -#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 4) /**< Shifted mode CNT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 4) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_ICEDGE_SHIFT 5 /**< Shift value for RTCC_ICEDGE */ -#define _RTCC_CC_CTRL_ICEDGE_MASK 0x60UL /**< Bit mask for RTCC_ICEDGE */ -#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ -#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 5) /**< Shifted mode RISING for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 5) /**< Shifted mode FALLING for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 5) /**< Shifted mode BOTH for RTCC_CC_CTRL */ -#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 5) /**< Shifted mode NONE for RTCC_CC_CTRL */ - -/* Bit fields for RTCC CC_OCVALUE */ -#define _RTCC_CC_OCVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_OCVALUE */ -#define _RTCC_CC_OCVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_OCVALUE */ -#define _RTCC_CC_OCVALUE_OC_SHIFT 0 /**< Shift value for RTCC_OC */ -#define _RTCC_CC_OCVALUE_OC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_OC */ -#define _RTCC_CC_OCVALUE_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_OCVALUE */ -#define RTCC_CC_OCVALUE_OC_DEFAULT (_RTCC_CC_OCVALUE_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_OCVALUE */ - -/* Bit fields for RTCC CC_ICVALUE */ -#define _RTCC_CC_ICVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_ICVALUE */ -#define _RTCC_CC_ICVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_ICVALUE */ -#define _RTCC_CC_ICVALUE_IC_SHIFT 0 /**< Shift value for RTCC_IC */ -#define _RTCC_CC_ICVALUE_IC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IC */ -#define _RTCC_CC_ICVALUE_IC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_ICVALUE */ -#define RTCC_CC_ICVALUE_IC_DEFAULT (_RTCC_CC_ICVALUE_IC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_ICVALUE */ - -/** @} End of group EFR32BG22_RTCC_BitFields */ -/** @} End of group EFR32BG22_RTCC */ -/** @} End of group Parts */ - -#endif // EFR32BG22_RTCC_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 RTCC register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_RTCC_H +#define EFR32BG22_RTCC_H +#define RTCC_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_RTCC RTCC + * @{ + * @brief EFR32BG22 RTCC Register Declaration. + *****************************************************************************/ + +/** RTCC CC Register Group Declaration. */ +typedef struct { + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OCVALUE; /**< Output Compare Value Register */ + __IM uint32_t ICVALUE; /**< Input Capture Value Register */ +} RTCC_CC_TypeDef; + +/** RTCC Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP VERSION */ + __IOM uint32_t EN; /**< Module Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status register */ + __IOM uint32_t IF; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED0[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP VERSION */ + __IOM uint32_t EN_SET; /**< Module Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status register */ + __IOM uint32_t IF_SET; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + __IM uint32_t COMBCNT_SET; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_SET[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED1[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ + __IOM uint32_t EN_CLR; /**< Module Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status register */ + __IOM uint32_t IF_CLR; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + __IM uint32_t COMBCNT_CLR; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_CLR[3U]; /**< Capture/Compare Channel */ + uint32_t RESERVED2[1003U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ + __IOM uint32_t EN_TGL; /**< Module Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status register */ + __IOM uint32_t IF_TGL; /**< RTCC Interrupt Flags */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + __IM uint32_t COMBCNT_TGL; /**< Combined Pre-Counter and Counter Valu... */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ + __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ + RTCC_CC_TypeDef CC_TGL[3U]; /**< Capture/Compare Channel */ +} RTCC_TypeDef; +/** @} End of group EFR32BG22_RTCC */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_RTCC + * @{ + * @defgroup EFR32BG22_RTCC_BitFields RTCC Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for RTCC IPVERSION */ +#define _RTCC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IPVERSION */ +#define _RTCC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for RTCC_IPVERSION */ +#define RTCC_IPVERSION_IPVERSION_DEFAULT (_RTCC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IPVERSION */ + +/* Bit fields for RTCC EN */ +#define _RTCC_EN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EN */ +#define _RTCC_EN_MASK 0x00000001UL /**< Mask for RTCC_EN */ +#define RTCC_EN_EN (0x1UL << 0) /**< RTCC Enable */ +#define _RTCC_EN_EN_SHIFT 0 /**< Shift value for RTCC_EN */ +#define _RTCC_EN_EN_MASK 0x1UL /**< Bit mask for RTCC_EN */ +#define _RTCC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EN */ +#define RTCC_EN_EN_DEFAULT (_RTCC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EN */ + +/* Bit fields for RTCC CFG */ +#define _RTCC_CFG_RESETVALUE 0x00000000UL /**< Default value for RTCC_CFG */ +#define _RTCC_CFG_MASK 0x000000FFUL /**< Mask for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ +#define _RTCC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for RTCC_DEBUGRUN */ +#define _RTCC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for RTCC_CFG */ +#define _RTCC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_DEFAULT (_RTCC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X0 (_RTCC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for RTCC_CFG */ +#define RTCC_CFG_DEBUGRUN_X1 (_RTCC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP (0x1UL << 1) /**< Pre-counter CCV0 top value enable. */ +#define _RTCC_CFG_PRECNTCCV0TOP_SHIFT 1 /**< Shift value for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_MASK 0x2UL /**< Bit mask for RTCC_PRECNTCCV0TOP */ +#define _RTCC_CFG_PRECNTCCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_PRECNTCCV0TOP_DEFAULT (_RTCC_CFG_PRECNTCCV0TOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP (0x1UL << 2) /**< CCV1 top value enable */ +#define _RTCC_CFG_CNTCCV1TOP_SHIFT 2 /**< Shift value for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_MASK 0x4UL /**< Bit mask for RTCC_CNTCCV1TOP */ +#define _RTCC_CFG_CNTCCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTCCV1TOP_DEFAULT (_RTCC_CFG_CNTCCV1TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK (0x1UL << 3) /**< Counter prescaler mode. */ +#define _RTCC_CFG_CNTTICK_SHIFT 3 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_MASK 0x8UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_CFG_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CFG */ +#define _RTCC_CFG_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_DEFAULT (_RTCC_CFG_CNTTICK_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_PRESC (_RTCC_CFG_CNTTICK_PRESC << 3) /**< Shifted mode PRESC for RTCC_CFG */ +#define RTCC_CFG_CNTTICK_CCV0MATCH (_RTCC_CFG_CNTTICK_CCV0MATCH << 3) /**< Shifted mode CCV0MATCH for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for RTCC_CNTPRESC */ +#define _RTCC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CFG */ +#define _RTCC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DEFAULT (_RTCC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1 (_RTCC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2 (_RTCC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4 (_RTCC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8 (_RTCC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16 (_RTCC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32 (_RTCC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV64 (_RTCC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV128 (_RTCC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV256 (_RTCC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV512 (_RTCC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV1024 (_RTCC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV2048 (_RTCC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV4096 (_RTCC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV8192 (_RTCC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV16384 (_RTCC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for RTCC_CFG */ +#define RTCC_CFG_CNTPRESC_DIV32768 (_RTCC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for RTCC_CFG */ + +/* Bit fields for RTCC CMD */ +#define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ +#define _RTCC_CMD_MASK 0x00000003UL /**< Mask for RTCC_CMD */ +#define RTCC_CMD_START (0x1UL << 0) /**< Start RTCC main counter */ +#define _RTCC_CMD_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_CMD_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_START_DEFAULT (_RTCC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP (0x1UL << 1) /**< Stop RTCC main counter */ +#define _RTCC_CMD_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_CMD_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ +#define RTCC_CMD_STOP_DEFAULT (_RTCC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_CMD */ + +/* Bit fields for RTCC STATUS */ +#define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ +#define _RTCC_STATUS_MASK 0x00000003UL /**< Mask for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING (0x1UL << 0) /**< RTCC running status */ +#define _RTCC_STATUS_RUNNING_SHIFT 0 /**< Shift value for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for RTCC_RUNNING */ +#define _RTCC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RUNNING_DEFAULT (_RTCC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS (0x1UL << 1) /**< Lock Status */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_SHIFT 1 /**< Shift value for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_MASK 0x2UL /**< Bit mask for RTCC_RTCCLOCKSTATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_STATUS */ +#define _RTCC_STATUS_RTCCLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT (_RTCC_STATUS_RTCCLOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for RTCC_STATUS */ +#define RTCC_STATUS_RTCCLOCKSTATUS_LOCKED (_RTCC_STATUS_RTCCLOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for RTCC_STATUS */ + +/* Bit fields for RTCC IF */ +#define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ +#define _RTCC_IF_MASK 0x000003FFUL /**< Mask for RTCC_IF */ +#define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK (0x1UL << 1) /**< Main counter tick */ +#define _RTCC_IF_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IF_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IF_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Flag */ +#define _RTCC_IF_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IF_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ +#define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ + +/* Bit fields for RTCC IEN */ +#define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ +#define _RTCC_IEN_MASK 0x000003FFUL /**< Mask for RTCC_IEN */ +#define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ +#define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ +#define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ +#define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK (0x1UL << 1) /**< CNTTICK Interrupt Enable */ +#define _RTCC_IEN_CNTTICK_SHIFT 1 /**< Shift value for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_MASK 0x2UL /**< Bit mask for RTCC_CNTTICK */ +#define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0 (0x1UL << 4) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC0_SHIFT 4 /**< Shift value for RTCC_CC0 */ +#define _RTCC_IEN_CC0_MASK 0x10UL /**< Bit mask for RTCC_CC0 */ +#define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1 (0x1UL << 6) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC1_SHIFT 6 /**< Shift value for RTCC_CC1 */ +#define _RTCC_IEN_CC1_MASK 0x40UL /**< Bit mask for RTCC_CC1 */ +#define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2 (0x1UL << 8) /**< CC Channel n Interrupt Enable */ +#define _RTCC_IEN_CC2_SHIFT 8 /**< Shift value for RTCC_CC2 */ +#define _RTCC_IEN_CC2_MASK 0x100UL /**< Bit mask for RTCC_CC2 */ +#define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ +#define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ + +/* Bit fields for RTCC PRECNT */ +#define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ +#define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ +#define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ + +/* Bit fields for RTCC CNT */ +#define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ +#define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ +#define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ +#define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ +#define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ + +/* Bit fields for RTCC COMBCNT */ +#define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ +#define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ +#define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ +#define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ + +/* Bit fields for RTCC SYNCBUSY */ +#define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ +#define _RTCC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ +#define _RTCC_SYNCBUSY_START_SHIFT 0 /**< Shift value for RTCC_START */ +#define _RTCC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for RTCC_START */ +#define _RTCC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_START_DEFAULT (_RTCC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ +#define _RTCC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for RTCC_STOP */ +#define _RTCC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_STOP_DEFAULT (_RTCC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for RTCC_PRECNT */ +#define _RTCC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_PRECNT_DEFAULT (_RTCC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ +#define _RTCC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for RTCC_CNT */ +#define _RTCC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ +#define RTCC_SYNCBUSY_CNT_DEFAULT (_RTCC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ + +/* Bit fields for RTCC LOCK */ +#define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ +#define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ +#define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ +#define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ +#define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ + +/* Bit fields for RTCC CC_CTRL */ +#define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MASK 0x000000FFUL /**< Mask for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for RTCC_MODE */ +#define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for RTCC_CMOA */ +#define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE (0x1UL << 4) /**< Capture compare channel comparison base. */ +#define _RTCC_CC_CTRL_COMPBASE_SHIFT 4 /**< Shift value for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_MASK 0x10UL /**< Bit mask for RTCC_COMPBASE */ +#define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 4) /**< Shifted mode CNT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 4) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_SHIFT 5 /**< Shift value for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_MASK 0x60UL /**< Bit mask for RTCC_ICEDGE */ +#define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ +#define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 5) /**< Shifted mode RISING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 5) /**< Shifted mode FALLING for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 5) /**< Shifted mode BOTH for RTCC_CC_CTRL */ +#define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 5) /**< Shifted mode NONE for RTCC_CC_CTRL */ + +/* Bit fields for RTCC CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_OCVALUE */ +#define _RTCC_CC_OCVALUE_OC_SHIFT 0 /**< Shift value for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_OC */ +#define _RTCC_CC_OCVALUE_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_OCVALUE */ +#define RTCC_CC_OCVALUE_OC_DEFAULT (_RTCC_CC_OCVALUE_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_OCVALUE */ + +/* Bit fields for RTCC CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_ICVALUE */ +#define _RTCC_CC_ICVALUE_IC_SHIFT 0 /**< Shift value for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_IC */ +#define _RTCC_CC_ICVALUE_IC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_ICVALUE */ +#define RTCC_CC_ICVALUE_IC_DEFAULT (_RTCC_CC_ICVALUE_IC_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_ICVALUE */ + +/** @} End of group EFR32BG22_RTCC_BitFields */ +/** @} End of group EFR32BG22_RTCC */ +/** @} End of group Parts */ + +#endif // EFR32BG22_RTCC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h index f12bab3..253ace8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_smu.h @@ -1,1313 +1,1313 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 SMU register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_SMU_H -#define EFR32BG22_SMU_H -#define SMU_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_SMU SMU - * @{ - * @brief EFR32BG22 SMU Register Declaration. - *****************************************************************************/ - -/** SMU Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version */ - __IM uint32_t STATUS; /**< Status */ - __IOM uint32_t LOCK; /**< Lock */ - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL; /**< M33 Control */ - uint32_t RESERVED1[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0; /**< PPU PATD Register 0 */ - __IOM uint32_t PPUPATD1; /**< PPU PATD Register 1 */ - uint32_t RESERVED2[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0; /**< PPU SATD Register 0 */ - __IOM uint32_t PPUSATD1; /**< PPU SATD Register 1 */ - uint32_t RESERVED3[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS; /**< PPU Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0; /**< BMPU PATD Register 0 */ - uint32_t RESERVED5[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0; /**< BMPU SATD Register 0 */ - uint32_t RESERVED6[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS; /**< BMPU Fault Status */ - __IM uint32_t BMPUFSADDR; /**< BMPU Fault Status Address */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0; /**< ESAU Region Types Register 0 */ - __IOM uint32_t ESAURTYPES1; /**< ESAU Region Types Register 1 */ - uint32_t RESERVED8[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01; /**< ESAU Movable Region Boundary 0-1 */ - __IOM uint32_t ESAUMRB12; /**< ESAU Movable Region Boundary 1-2 */ - uint32_t RESERVED9[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45; /**< ESAU Movable Region Boundary 4-5 */ - __IOM uint32_t ESAUMRB56; /**< ESAU Movable Region Boundary 5-6 */ - uint32_t RESERVED10[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version */ - __IM uint32_t STATUS_SET; /**< Status */ - __IOM uint32_t LOCK_SET; /**< Lock */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_SET; /**< M33 Control */ - uint32_t RESERVED12[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_SET; /**< PPU PATD Register 0 */ - __IOM uint32_t PPUPATD1_SET; /**< PPU PATD Register 1 */ - uint32_t RESERVED13[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_SET; /**< PPU SATD Register 0 */ - __IOM uint32_t PPUSATD1_SET; /**< PPU SATD Register 1 */ - uint32_t RESERVED14[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_SET; /**< PPU Fault Status */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_SET; /**< BMPU PATD Register 0 */ - uint32_t RESERVED16[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_SET; /**< BMPU SATD Register 0 */ - uint32_t RESERVED17[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_SET; /**< BMPU Fault Status */ - __IM uint32_t BMPUFSADDR_SET; /**< BMPU Fault Status Address */ - uint32_t RESERVED18[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_SET; /**< ESAU Region Types Register 0 */ - __IOM uint32_t ESAURTYPES1_SET; /**< ESAU Region Types Register 1 */ - uint32_t RESERVED19[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_SET; /**< ESAU Movable Region Boundary 0-1 */ - __IOM uint32_t ESAUMRB12_SET; /**< ESAU Movable Region Boundary 1-2 */ - uint32_t RESERVED20[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_SET; /**< ESAU Movable Region Boundary 4-5 */ - __IOM uint32_t ESAUMRB56_SET; /**< ESAU Movable Region Boundary 5-6 */ - uint32_t RESERVED21[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version */ - __IM uint32_t STATUS_CLR; /**< Status */ - __IOM uint32_t LOCK_CLR; /**< Lock */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_CLR; /**< M33 Control */ - uint32_t RESERVED23[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_CLR; /**< PPU PATD Register 0 */ - __IOM uint32_t PPUPATD1_CLR; /**< PPU PATD Register 1 */ - uint32_t RESERVED24[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_CLR; /**< PPU SATD Register 0 */ - __IOM uint32_t PPUSATD1_CLR; /**< PPU SATD Register 1 */ - uint32_t RESERVED25[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_CLR; /**< PPU Fault Status */ - uint32_t RESERVED26[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_CLR; /**< BMPU PATD Register 0 */ - uint32_t RESERVED27[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_CLR; /**< BMPU SATD Register 0 */ - uint32_t RESERVED28[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_CLR; /**< BMPU Fault Status */ - __IM uint32_t BMPUFSADDR_CLR; /**< BMPU Fault Status Address */ - uint32_t RESERVED29[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_CLR; /**< ESAU Region Types Register 0 */ - __IOM uint32_t ESAURTYPES1_CLR; /**< ESAU Region Types Register 1 */ - uint32_t RESERVED30[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_CLR; /**< ESAU Movable Region Boundary 0-1 */ - __IOM uint32_t ESAUMRB12_CLR; /**< ESAU Movable Region Boundary 1-2 */ - uint32_t RESERVED31[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_CLR; /**< ESAU Movable Region Boundary 4-5 */ - __IOM uint32_t ESAUMRB56_CLR; /**< ESAU Movable Region Boundary 5-6 */ - uint32_t RESERVED32[862U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version */ - __IM uint32_t STATUS_TGL; /**< Status */ - __IOM uint32_t LOCK_TGL; /**< Lock */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED33[3U]; /**< Reserved for future use */ - __IOM uint32_t M33CTRL_TGL; /**< M33 Control */ - uint32_t RESERVED34[7U]; /**< Reserved for future use */ - __IOM uint32_t PPUPATD0_TGL; /**< PPU PATD Register 0 */ - __IOM uint32_t PPUPATD1_TGL; /**< PPU PATD Register 1 */ - uint32_t RESERVED35[6U]; /**< Reserved for future use */ - __IOM uint32_t PPUSATD0_TGL; /**< PPU SATD Register 0 */ - __IOM uint32_t PPUSATD1_TGL; /**< PPU SATD Register 1 */ - uint32_t RESERVED36[54U]; /**< Reserved for future use */ - __IM uint32_t PPUFS_TGL; /**< PPU Fault Status */ - uint32_t RESERVED37[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUPATD0_TGL; /**< BMPU PATD Register 0 */ - uint32_t RESERVED38[7U]; /**< Reserved for future use */ - __IOM uint32_t BMPUSATD0_TGL; /**< BMPU SATD Register 0 */ - uint32_t RESERVED39[55U]; /**< Reserved for future use */ - __IM uint32_t BMPUFS_TGL; /**< BMPU Fault Status */ - __IM uint32_t BMPUFSADDR_TGL; /**< BMPU Fault Status Address */ - uint32_t RESERVED40[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAURTYPES0_TGL; /**< ESAU Region Types Register 0 */ - __IOM uint32_t ESAURTYPES1_TGL; /**< ESAU Region Types Register 1 */ - uint32_t RESERVED41[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB01_TGL; /**< ESAU Movable Region Boundary 0-1 */ - __IOM uint32_t ESAUMRB12_TGL; /**< ESAU Movable Region Boundary 1-2 */ - uint32_t RESERVED42[2U]; /**< Reserved for future use */ - __IOM uint32_t ESAUMRB45_TGL; /**< ESAU Movable Region Boundary 4-5 */ - __IOM uint32_t ESAUMRB56_TGL; /**< ESAU Movable Region Boundary 5-6 */ -} SMU_TypeDef; -/** @} End of group EFR32BG22_SMU */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_SMU - * @{ - * @defgroup EFR32BG22_SMU_BitFields SMU Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SMU IPVERSION */ -#define _SMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SMU_IPVERSION */ -#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ -#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_IPVERSION */ -#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ - -/* Bit fields for SMU STATUS */ -#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ -#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ -#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ -#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ -#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ -#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ -#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ -#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ -#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ -#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ - -/* Bit fields for SMU LOCK */ -#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ -#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ -#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ -#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ -#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ - -/* Bit fields for SMU IF */ -#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ -#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ -#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ -#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ -#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ -#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ -#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ -#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ - -/* Bit fields for SMU IEN */ -#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ -#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ -#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ -#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ -#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ -#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ -#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ -#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ -#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ -#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ -#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ -#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ - -/* Bit fields for SMU M33CTRL */ -#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ -#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< LOCKSVTAIRCR control of M33 CPU */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ -#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< LOCKNSVTOR control of M33 CPU */ -#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ -#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< LOCKSMPU control of M33 CPU */ -#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ -#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< LOCKNSMPU control of M33 CPU */ -#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ -#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< LOCKSAU control of M33 CPU */ -#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ -#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ -#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ - -/* Bit fields for SMU PPUPATD0 */ -#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ -#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ -#define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ -#define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ -#define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ -#define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ -#define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ -#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ -#define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ -#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ -#define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ -#define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ -#define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ -#define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ -#define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ -#define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ -#define _SMU_PPUPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ -#define _SMU_PPUPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ -#define _SMU_PPUPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ -#define _SMU_PPUPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ -#define _SMU_PPUPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ -#define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ -#define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ -#define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ -#define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ -#define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ -#define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ -#define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ -#define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ -#define _SMU_PPUPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ -#define _SMU_PPUPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ -#define _SMU_PPUPATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_DCI_DEFAULT (_SMU_PPUPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ - -/* Bit fields for SMU PPUPATD1 */ -#define _SMU_PPUPATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUPATD1 */ -#define _SMU_PPUPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ -#define _SMU_PPUPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUPATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_DCDC_DEFAULT (_SMU_PPUPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ -#define _SMU_PPUPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ -#define _SMU_PPUPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ -#define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ -#define _SMU_PPUPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ -#define _SMU_PPUPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ -#define _SMU_PPUPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RFSENSE_DEFAULT (_SMU_PPUPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ -#define _SMU_PPUPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ -#define _SMU_PPUPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ -#define _SMU_PPUPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ -#define _SMU_PPUPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ -#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ -#define _SMU_PPUPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ -#define _SMU_PPUPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ -#define _SMU_PPUPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ -#define _SMU_PPUPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ -#define _SMU_PPUPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ -#define _SMU_PPUPATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_EUART0_DEFAULT (_SMU_PPUPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ -#define _SMU_PPUPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_PPUPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_PPUPATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_CRYPTOACC_DEFAULT (_SMU_PPUPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ -#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ - -/* Bit fields for SMU PPUSATD0 */ -#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ -#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ -#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ -#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ -#define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ -#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ -#define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ -#define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ -#define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ -#define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ -#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ -#define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ -#define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ -#define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ -#define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ -#define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ -#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ -#define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ -#define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ -#define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ -#define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Secure Access */ -#define _SMU_PPUSATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0 (0x1UL << 21) /**< USART0 Secure Access */ -#define _SMU_PPUSATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART1 (0x1UL << 22) /**< USART1 Secure Access */ -#define _SMU_PPUSATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ -#define _SMU_PPUSATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ -#define _SMU_PPUSATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ -#define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ -#define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Secure Access */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ -#define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ -#define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ -#define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ -#define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ -#define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ -#define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCI (0x1UL << 31) /**< DCI Secure Access */ -#define _SMU_PPUSATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ -#define _SMU_PPUSATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ -#define _SMU_PPUSATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ -#define SMU_PPUSATD0_DCI_DEFAULT (_SMU_PPUSATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ - -/* Bit fields for SMU PPUSATD1 */ -#define _SMU_PPUSATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUSATD1 */ -#define _SMU_PPUSATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DCDC (0x1UL << 1) /**< DCDC Secure Access */ -#define _SMU_PPUSATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUSATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUSATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_DCDC_DEFAULT (_SMU_PPUSATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PDM (0x1UL << 2) /**< PDM Secure Access */ -#define _SMU_PPUSATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ -#define _SMU_PPUSATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ -#define _SMU_PPUSATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_PDM_DEFAULT (_SMU_PPUSATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Secure Access */ -#define _SMU_PPUSATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ -#define _SMU_PPUSATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ -#define _SMU_PPUSATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RFSENSE_DEFAULT (_SMU_PPUSATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Secure Access */ -#define _SMU_PPUSATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU (0x1UL << 5) /**< SMU Secure Access */ -#define _SMU_PPUSATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Secure Access */ -#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RTCC (0x1UL << 7) /**< RTCC Secure Access */ -#define _SMU_PPUSATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ -#define _SMU_PPUSATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ -#define _SMU_PPUSATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_RTCC_DEFAULT (_SMU_PPUSATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Secure Access */ -#define _SMU_PPUSATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0 (0x1UL << 9) /**< IADC0 Secure Access */ -#define _SMU_PPUSATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0 (0x1UL << 10) /**< I2C0 Secure Access */ -#define _SMU_PPUSATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Secure Access */ -#define _SMU_PPUSATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Secure Access */ -#define _SMU_PPUSATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUART0 (0x1UL << 13) /**< EUART0 Secure Access */ -#define _SMU_PPUSATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ -#define _SMU_PPUSATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ -#define _SMU_PPUSATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_EUART0_DEFAULT (_SMU_PPUSATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Secure Access */ -#define _SMU_PPUSATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_PPUSATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_PPUSATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_CRYPTOACC_DEFAULT (_SMU_PPUSATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Secure Access */ -#define _SMU_PPUSATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ -#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ - -/* Bit fields for SMU PPUFS */ -#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ -#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ -#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ -#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ - -/* Bit fields for SMU BMPUPATD0 */ -#define _SMU_BMPUPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUPATD0 */ -#define _SMU_BMPUPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ -#define _SMU_BMPUPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_BMPUPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_BMPUPATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ -#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ -#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ - -/* Bit fields for SMU BMPUSATD0 */ -#define _SMU_BMPUSATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUSATD0 */ -#define _SMU_BMPUSATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ -#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA secure mode */ -#define _SMU_BMPUSATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_BMPUSATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_BMPUSATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_CRYPTOACC_DEFAULT (_SMU_BMPUSATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager secure mode */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug secure mode */ -#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA (0x1UL << 4) /**< MCU LDMA secure mode */ -#define _SMU_BMPUSATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ -#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ - -/* Bit fields for SMU BMPUFS */ -#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ -#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ -#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ -#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ -#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ - -/* Bit fields for SMU BMPUFSADDR */ -#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ -#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ -#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ - -/* Bit fields for SMU ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ -#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure Type */ -#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ -#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ -#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ - -/* Bit fields for SMU ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ -#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure Type */ -#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ -#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ -#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ - -/* Bit fields for SMU ESAUMRB01 */ -#define _SMU_ESAUMRB01_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ -#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ -#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ - -/* Bit fields for SMU ESAUMRB12 */ -#define _SMU_ESAUMRB12_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ -#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ -#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ - -/* Bit fields for SMU ESAUMRB45 */ -#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ -#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ -#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ - -/* Bit fields for SMU ESAUMRB56 */ -#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ -#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ -#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ - -/** @} End of group EFR32BG22_SMU_BitFields */ -/** @} End of group EFR32BG22_SMU */ -/**************************************************************************//** - * @defgroup EFR32BG22_SMU_CFGNS SMU_CFGNS - * @{ - * @brief EFR32BG22 SMU_CFGNS Register Declaration. - *****************************************************************************/ - -/** SMU_CFGNS Register Declaration. */ -typedef struct { - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS; /**< Non-Secure Status */ - __IOM uint32_t NSLOCK; /**< Non-Secure Lock */ - __IOM uint32_t NSIF; /**< Non-Secure Interrupt Flag */ - __IOM uint32_t NSIEN; /**< Non-Secure Interrupt Enable */ - uint32_t RESERVED1[3U]; /**< Reserved for future use */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0; /**< PPU Non-secure PATD Register 0 */ - __IOM uint32_t PPUNSPATD1; /**< PPU Non-secure PATD Register 1 */ - uint32_t RESERVED3[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS; /**< PPU Non-secure Fault Status */ - uint32_t RESERVED4[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0; /**< BMPU Non-Secure PATD Register 0 */ - uint32_t RESERVED5[63U]; /**< Reserved for future use */ - uint32_t RESERVED6[876U]; /**< Reserved for future use */ - uint32_t RESERVED7[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_SET; /**< Non-Secure Status */ - __IOM uint32_t NSLOCK_SET; /**< Non-Secure Lock */ - __IOM uint32_t NSIF_SET; /**< Non-Secure Interrupt Flag */ - __IOM uint32_t NSIEN_SET; /**< Non-Secure Interrupt Enable */ - uint32_t RESERVED8[3U]; /**< Reserved for future use */ - uint32_t RESERVED9[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_SET; /**< PPU Non-secure PATD Register 0 */ - __IOM uint32_t PPUNSPATD1_SET; /**< PPU Non-secure PATD Register 1 */ - uint32_t RESERVED10[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_SET; /**< PPU Non-secure Fault Status */ - uint32_t RESERVED11[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_SET; /**< BMPU Non-Secure PATD Register 0 */ - uint32_t RESERVED12[63U]; /**< Reserved for future use */ - uint32_t RESERVED13[876U]; /**< Reserved for future use */ - uint32_t RESERVED14[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_CLR; /**< Non-Secure Status */ - __IOM uint32_t NSLOCK_CLR; /**< Non-Secure Lock */ - __IOM uint32_t NSIF_CLR; /**< Non-Secure Interrupt Flag */ - __IOM uint32_t NSIEN_CLR; /**< Non-Secure Interrupt Enable */ - uint32_t RESERVED15[3U]; /**< Reserved for future use */ - uint32_t RESERVED16[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_CLR; /**< PPU Non-secure PATD Register 0 */ - __IOM uint32_t PPUNSPATD1_CLR; /**< PPU Non-secure PATD Register 1 */ - uint32_t RESERVED17[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_CLR; /**< PPU Non-secure Fault Status */ - uint32_t RESERVED18[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_CLR; /**< BMPU Non-Secure PATD Register 0 */ - uint32_t RESERVED19[63U]; /**< Reserved for future use */ - uint32_t RESERVED20[876U]; /**< Reserved for future use */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IM uint32_t NSSTATUS_TGL; /**< Non-Secure Status */ - __IOM uint32_t NSLOCK_TGL; /**< Non-Secure Lock */ - __IOM uint32_t NSIF_TGL; /**< Non-Secure Interrupt Flag */ - __IOM uint32_t NSIEN_TGL; /**< Non-Secure Interrupt Enable */ - uint32_t RESERVED22[3U]; /**< Reserved for future use */ - uint32_t RESERVED23[8U]; /**< Reserved for future use */ - __IOM uint32_t PPUNSPATD0_TGL; /**< PPU Non-secure PATD Register 0 */ - __IOM uint32_t PPUNSPATD1_TGL; /**< PPU Non-secure PATD Register 1 */ - uint32_t RESERVED24[62U]; /**< Reserved for future use */ - __IM uint32_t PPUNSFS_TGL; /**< PPU Non-secure Fault Status */ - uint32_t RESERVED25[3U]; /**< Reserved for future use */ - __IOM uint32_t BMPUNSPATD0_TGL; /**< BMPU Non-Secure PATD Register 0 */ - uint32_t RESERVED26[63U]; /**< Reserved for future use */ -} SMU_CFGNS_TypeDef; -/** @} End of group EFR32BG22_SMU_CFGNS */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_SMU_CFGNS - * @{ - * @defgroup EFR32BG22_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SMU NSSTATUS */ -#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock Status */ -#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ -#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ -#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ -#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ - -/* Bit fields for SMU NSLOCK */ -#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ -#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ -#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ -#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ - -/* Bit fields for SMU NSIF */ -#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ -#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ -#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ -#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ -#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ - -/* Bit fields for SMU NSIEN */ -#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ -#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ -#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ -#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ -#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ -#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ -#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ - -/* Bit fields for SMU PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ -#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ -#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ -#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ -#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ -#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ -#define _SMU_PPUNSPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ -#define _SMU_PPUNSPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ -#define _SMU_PPUNSPATD0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFXO0_DEFAULT (_SMU_PPUNSPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ -#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ -#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ -#define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ -#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ -#define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ -#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ -#define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ -#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ -#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ -#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ -#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ -#define _SMU_PPUNSPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ -#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ -#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ -#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ -#define _SMU_PPUNSPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ -#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ -#define _SMU_PPUNSPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ -#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ -#define _SMU_PPUNSPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ -#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ -#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ -#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ -#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ -#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ -#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ -#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ -#define _SMU_PPUNSPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ -#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ -#define _SMU_PPUNSPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ -#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ -#define _SMU_PPUNSPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ -#define _SMU_PPUNSPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ -#define _SMU_PPUNSPATD0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_USART1_DEFAULT (_SMU_PPUNSPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ -#define _SMU_PPUNSPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ -#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ -#define _SMU_PPUNSPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ -#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ -#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ -#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ -#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ -#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ -#define _SMU_PPUNSPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ -#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ -#define _SMU_PPUNSPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ -#define _SMU_PPUNSPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ -#define _SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ -#define _SMU_PPUNSPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ -#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ -#define _SMU_PPUNSPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ -#define _SMU_PPUNSPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ -#define _SMU_PPUNSPATD0_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ -#define SMU_PPUNSPATD0_DCI_DEFAULT (_SMU_PPUNSPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ - -/* Bit fields for SMU PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ -#define _SMU_PPUNSPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ -#define _SMU_PPUNSPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ -#define _SMU_PPUNSPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ -#define _SMU_PPUNSPATD1_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_DCDC_DEFAULT (_SMU_PPUNSPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ -#define _SMU_PPUNSPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ -#define _SMU_PPUNSPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ -#define _SMU_PPUNSPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_PDM_DEFAULT (_SMU_PPUNSPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ -#define _SMU_PPUNSPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ -#define _SMU_PPUNSPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ -#define _SMU_PPUNSPATD1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RFSENSE_DEFAULT (_SMU_PPUNSPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ -#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ -#define _SMU_PPUNSPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ -#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ -#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ -#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ -#define _SMU_PPUNSPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ -#define _SMU_PPUNSPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ -#define _SMU_PPUNSPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_RTCC_DEFAULT (_SMU_PPUNSPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ -#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ -#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ -#define _SMU_PPUNSPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ -#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ -#define _SMU_PPUNSPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ -#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ -#define _SMU_PPUNSPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ -#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ -#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ -#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ -#define _SMU_PPUNSPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ -#define _SMU_PPUNSPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ -#define _SMU_PPUNSPATD1_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_EUART0_DEFAULT (_SMU_PPUNSPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ -#define _SMU_PPUNSPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_PPUNSPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_PPUNSPATD1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_CRYPTOACC_DEFAULT (_SMU_PPUNSPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ -#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ -#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ -#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ - -/* Bit fields for SMU PPUNSFS */ -#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ -#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ -#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ - -/* Bit fields for SMU BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ -#define _SMU_BMPUNSPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ -#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ -#define _SMU_BMPUNSPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ -#define _SMU_BMPUNSPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ -#define _SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ -#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ -#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ -#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ -#define _SMU_BMPUNSPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ -#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ -#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ - -/** @} End of group EFR32BG22_SMU_CFGNS_BitFields */ -/** @} End of group EFR32BG22_SMU_CFGNS */ -/** @} End of group Parts */ - -#endif // EFR32BG22_SMU_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 SMU register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_SMU_H +#define EFR32BG22_SMU_H +#define SMU_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_SMU SMU + * @{ + * @brief EFR32BG22 SMU Register Declaration. + *****************************************************************************/ + +/** SMU Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version */ + __IM uint32_t STATUS; /**< Status */ + __IOM uint32_t LOCK; /**< Lock */ + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL; /**< M33 Control */ + uint32_t RESERVED1[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0; /**< PPU PATD Register 0 */ + __IOM uint32_t PPUPATD1; /**< PPU PATD Register 1 */ + uint32_t RESERVED2[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0; /**< PPU SATD Register 0 */ + __IOM uint32_t PPUSATD1; /**< PPU SATD Register 1 */ + uint32_t RESERVED3[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS; /**< PPU Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0; /**< BMPU PATD Register 0 */ + uint32_t RESERVED5[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0; /**< BMPU SATD Register 0 */ + uint32_t RESERVED6[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR; /**< BMPU Fault Status Address */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0; /**< ESAU Region Types Register 0 */ + __IOM uint32_t ESAURTYPES1; /**< ESAU Region Types Register 1 */ + uint32_t RESERVED8[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED9[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED10[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version */ + __IM uint32_t STATUS_SET; /**< Status */ + __IOM uint32_t LOCK_SET; /**< Lock */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_SET; /**< M33 Control */ + uint32_t RESERVED12[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_SET; /**< PPU PATD Register 0 */ + __IOM uint32_t PPUPATD1_SET; /**< PPU PATD Register 1 */ + uint32_t RESERVED13[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_SET; /**< PPU SATD Register 0 */ + __IOM uint32_t PPUSATD1_SET; /**< PPU SATD Register 1 */ + uint32_t RESERVED14[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_SET; /**< PPU Fault Status */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_SET; /**< BMPU PATD Register 0 */ + uint32_t RESERVED16[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_SET; /**< BMPU SATD Register 0 */ + uint32_t RESERVED17[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_SET; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_SET; /**< BMPU Fault Status Address */ + uint32_t RESERVED18[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_SET; /**< ESAU Region Types Register 0 */ + __IOM uint32_t ESAURTYPES1_SET; /**< ESAU Region Types Register 1 */ + uint32_t RESERVED19[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_SET; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_SET; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED20[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_SET; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_SET; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED21[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version */ + __IM uint32_t STATUS_CLR; /**< Status */ + __IOM uint32_t LOCK_CLR; /**< Lock */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_CLR; /**< M33 Control */ + uint32_t RESERVED23[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_CLR; /**< PPU PATD Register 0 */ + __IOM uint32_t PPUPATD1_CLR; /**< PPU PATD Register 1 */ + uint32_t RESERVED24[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_CLR; /**< PPU SATD Register 0 */ + __IOM uint32_t PPUSATD1_CLR; /**< PPU SATD Register 1 */ + uint32_t RESERVED25[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_CLR; /**< PPU Fault Status */ + uint32_t RESERVED26[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_CLR; /**< BMPU PATD Register 0 */ + uint32_t RESERVED27[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_CLR; /**< BMPU SATD Register 0 */ + uint32_t RESERVED28[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_CLR; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_CLR; /**< BMPU Fault Status Address */ + uint32_t RESERVED29[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_CLR; /**< ESAU Region Types Register 0 */ + __IOM uint32_t ESAURTYPES1_CLR; /**< ESAU Region Types Register 1 */ + uint32_t RESERVED30[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_CLR; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_CLR; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED31[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_CLR; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_CLR; /**< ESAU Movable Region Boundary 5-6 */ + uint32_t RESERVED32[862U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version */ + __IM uint32_t STATUS_TGL; /**< Status */ + __IOM uint32_t LOCK_TGL; /**< Lock */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED33[3U]; /**< Reserved for future use */ + __IOM uint32_t M33CTRL_TGL; /**< M33 Control */ + uint32_t RESERVED34[7U]; /**< Reserved for future use */ + __IOM uint32_t PPUPATD0_TGL; /**< PPU PATD Register 0 */ + __IOM uint32_t PPUPATD1_TGL; /**< PPU PATD Register 1 */ + uint32_t RESERVED35[6U]; /**< Reserved for future use */ + __IOM uint32_t PPUSATD0_TGL; /**< PPU SATD Register 0 */ + __IOM uint32_t PPUSATD1_TGL; /**< PPU SATD Register 1 */ + uint32_t RESERVED36[54U]; /**< Reserved for future use */ + __IM uint32_t PPUFS_TGL; /**< PPU Fault Status */ + uint32_t RESERVED37[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUPATD0_TGL; /**< BMPU PATD Register 0 */ + uint32_t RESERVED38[7U]; /**< Reserved for future use */ + __IOM uint32_t BMPUSATD0_TGL; /**< BMPU SATD Register 0 */ + uint32_t RESERVED39[55U]; /**< Reserved for future use */ + __IM uint32_t BMPUFS_TGL; /**< BMPU Fault Status */ + __IM uint32_t BMPUFSADDR_TGL; /**< BMPU Fault Status Address */ + uint32_t RESERVED40[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAURTYPES0_TGL; /**< ESAU Region Types Register 0 */ + __IOM uint32_t ESAURTYPES1_TGL; /**< ESAU Region Types Register 1 */ + uint32_t RESERVED41[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB01_TGL; /**< ESAU Movable Region Boundary 0-1 */ + __IOM uint32_t ESAUMRB12_TGL; /**< ESAU Movable Region Boundary 1-2 */ + uint32_t RESERVED42[2U]; /**< Reserved for future use */ + __IOM uint32_t ESAUMRB45_TGL; /**< ESAU Movable Region Boundary 4-5 */ + __IOM uint32_t ESAUMRB56_TGL; /**< ESAU Movable Region Boundary 5-6 */ +} SMU_TypeDef; +/** @} End of group EFR32BG22_SMU */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_SMU + * @{ + * @defgroup EFR32BG22_SMU_BitFields SMU Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU IPVERSION */ +#define _SMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SMU_IPVERSION */ +#define _SMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_IPVERSION */ +#define _SMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_IPVERSION */ +#define SMU_IPVERSION_IPVERSION_DEFAULT (_SMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IPVERSION */ + +/* Bit fields for SMU STATUS */ +#define _SMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_STATUS */ +#define _SMU_STATUS_MASK 0x00000003UL /**< Mask for SMU_STATUS */ +#define SMU_STATUS_SMULOCK (0x1UL << 0) /**< SMU Lock */ +#define _SMU_STATUS_SMULOCK_SHIFT 0 /**< Shift value for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_MASK 0x1UL /**< Bit mask for SMU_SMULOCK */ +#define _SMU_STATUS_SMULOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_STATUS */ +#define _SMU_STATUS_SMULOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_DEFAULT (_SMU_STATUS_SMULOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_UNLOCKED (_SMU_STATUS_SMULOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_STATUS */ +#define SMU_STATUS_SMULOCK_LOCKED (_SMU_STATUS_SMULOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR (0x1UL << 1) /**< SMU Programming Error */ +#define _SMU_STATUS_SMUPRGERR_SHIFT 1 /**< Shift value for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_MASK 0x2UL /**< Bit mask for SMU_SMUPRGERR */ +#define _SMU_STATUS_SMUPRGERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_STATUS */ +#define SMU_STATUS_SMUPRGERR_DEFAULT (_SMU_STATUS_SMUPRGERR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_STATUS */ + +/* Bit fields for SMU LOCK */ +#define _SMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_LOCK */ +#define _SMU_LOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_SHIFT 0 /**< Shift value for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMULOCKKEY */ +#define _SMU_LOCK_SMULOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_LOCK */ +#define _SMU_LOCK_SMULOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_DEFAULT (_SMU_LOCK_SMULOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_LOCK */ +#define SMU_LOCK_SMULOCKKEY_UNLOCK (_SMU_LOCK_SMULOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_LOCK */ + +/* Bit fields for SMU IF */ +#define _SMU_IF_RESETVALUE 0x00000000UL /**< Default value for SMU_IF */ +#define _SMU_IF_MASK 0x00030005UL /**< Mask for SMU_IF */ +#define SMU_IF_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Flag */ +#define _SMU_IF_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IF_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUPRIV_DEFAULT (_SMU_IF_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Flag */ +#define _SMU_IF_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IF_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IF_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUINST_DEFAULT (_SMU_IF_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Flag */ +#define _SMU_IF_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IF_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_PPUSEC_DEFAULT (_SMU_IF_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Flag */ +#define _SMU_IF_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IF_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IF */ +#define SMU_IF_BMPUSEC_DEFAULT (_SMU_IF_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IF */ + +/* Bit fields for SMU IEN */ +#define _SMU_IEN_RESETVALUE 0x00000000UL /**< Default value for SMU_IEN */ +#define _SMU_IEN_MASK 0x00030005UL /**< Mask for SMU_IEN */ +#define SMU_IEN_PPUPRIV (0x1UL << 0) /**< PPU Privilege Interrupt Enable */ +#define _SMU_IEN_PPUPRIV_SHIFT 0 /**< Shift value for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUPRIV */ +#define _SMU_IEN_PPUPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUPRIV_DEFAULT (_SMU_IEN_PPUPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST (0x1UL << 2) /**< PPU Instruction Interrupt Enable */ +#define _SMU_IEN_PPUINST_SHIFT 2 /**< Shift value for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_MASK 0x4UL /**< Bit mask for SMU_PPUINST */ +#define _SMU_IEN_PPUINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUINST_DEFAULT (_SMU_IEN_PPUINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC (0x1UL << 16) /**< PPU Security Interrupt Enable */ +#define _SMU_IEN_PPUSEC_SHIFT 16 /**< Shift value for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_MASK 0x10000UL /**< Bit mask for SMU_PPUSEC */ +#define _SMU_IEN_PPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_PPUSEC_DEFAULT (_SMU_IEN_PPUSEC_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC (0x1UL << 17) /**< BMPU Security Interrupt Enable */ +#define _SMU_IEN_BMPUSEC_SHIFT 17 /**< Shift value for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_MASK 0x20000UL /**< Bit mask for SMU_BMPUSEC */ +#define _SMU_IEN_BMPUSEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_IEN */ +#define SMU_IEN_BMPUSEC_DEFAULT (_SMU_IEN_BMPUSEC_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_IEN */ + +/* Bit fields for SMU M33CTRL */ +#define _SMU_M33CTRL_RESETVALUE 0x00000000UL /**< Default value for SMU_M33CTRL */ +#define _SMU_M33CTRL_MASK 0x0000001FUL /**< Mask for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR (0x1UL << 0) /**< LOCKSVTAIRCR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_SHIFT 0 /**< Shift value for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_MASK 0x1UL /**< Bit mask for SMU_LOCKSVTAIRCR */ +#define _SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT (_SMU_M33CTRL_LOCKSVTAIRCR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR (0x1UL << 1) /**< LOCKNSVTOR control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSVTOR_SHIFT 1 /**< Shift value for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_MASK 0x2UL /**< Bit mask for SMU_LOCKNSVTOR */ +#define _SMU_M33CTRL_LOCKNSVTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSVTOR_DEFAULT (_SMU_M33CTRL_LOCKNSVTOR_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU (0x1UL << 2) /**< LOCKSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSMPU_SHIFT 2 /**< Shift value for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_MASK 0x4UL /**< Bit mask for SMU_LOCKSMPU */ +#define _SMU_M33CTRL_LOCKSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSMPU_DEFAULT (_SMU_M33CTRL_LOCKSMPU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU (0x1UL << 3) /**< LOCKNSMPU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKNSMPU_SHIFT 3 /**< Shift value for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_MASK 0x8UL /**< Bit mask for SMU_LOCKNSMPU */ +#define _SMU_M33CTRL_LOCKNSMPU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKNSMPU_DEFAULT (_SMU_M33CTRL_LOCKNSMPU_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU (0x1UL << 4) /**< LOCKSAU control of M33 CPU */ +#define _SMU_M33CTRL_LOCKSAU_SHIFT 4 /**< Shift value for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_MASK 0x10UL /**< Bit mask for SMU_LOCKSAU */ +#define _SMU_M33CTRL_LOCKSAU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_M33CTRL */ +#define SMU_M33CTRL_LOCKSAU_DEFAULT (_SMU_M33CTRL_LOCKSAU_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_M33CTRL */ + +/* Bit fields for SMU PPUPATD0 */ +#define _SMU_PPUPATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUPATD0 */ +#define _SMU_PPUPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUPATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUPATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFXO0_DEFAULT (_SMU_PPUPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUPATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_HFRCO0_DEFAULT (_SMU_PPUPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUPATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_FSRCO_DEFAULT (_SMU_PPUPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUPATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DPLL0_DEFAULT (_SMU_PPUPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUPATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFXO_DEFAULT (_SMU_PPUPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUPATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LFRCO_DEFAULT (_SMU_PPUPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUPATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ULFRCO_DEFAULT (_SMU_PPUPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUPATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_MSC_DEFAULT (_SMU_PPUPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUPATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_ICACHE0_DEFAULT (_SMU_PPUPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUPATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_PRS_DEFAULT (_SMU_PPUPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUPATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPIO_DEFAULT (_SMU_PPUPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMA_DEFAULT (_SMU_PPUPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUPATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_LDMAXBAR_DEFAULT (_SMU_PPUPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUPATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER0_DEFAULT (_SMU_PPUPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUPATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER1_DEFAULT (_SMU_PPUPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUPATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER2_DEFAULT (_SMU_PPUPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUPATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER3_DEFAULT (_SMU_PPUPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUPATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_TIMER4_DEFAULT (_SMU_PPUPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUPATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART0_DEFAULT (_SMU_PPUPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUPATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_USART1_DEFAULT (_SMU_PPUPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUPATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURTC_DEFAULT (_SMU_PPUPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUPATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_I2C1_DEFAULT (_SMU_PPUPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUPATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_SYSCFG_DEFAULT (_SMU_PPUPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUPATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_BURAM_DEFAULT (_SMU_PPUPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUPATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUPATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_GPCRC_DEFAULT (_SMU_PPUPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ +#define _SMU_PPUPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ +#define _SMU_PPUPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ +#define _SMU_PPUPATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD0 */ +#define SMU_PPUPATD0_DCI_DEFAULT (_SMU_PPUPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ + +/* Bit fields for SMU PPUPATD1 */ +#define _SMU_PPUPATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUPATD1 */ +#define _SMU_PPUPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ +#define _SMU_PPUPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUPATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_DCDC_DEFAULT (_SMU_PPUPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ +#define _SMU_PPUPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUPATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_PDM_DEFAULT (_SMU_PPUPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ +#define _SMU_PPUPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUPATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RFSENSE_DEFAULT (_SMU_PPUPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ +#define _SMU_PPUPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUPATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RADIOAES_DEFAULT (_SMU_PPUPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ +#define _SMU_PPUPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUPATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMU_DEFAULT (_SMU_PPUPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUPATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_SMUCFGNS_DEFAULT (_SMU_PPUPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ +#define _SMU_PPUPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUPATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_RTCC_DEFAULT (_SMU_PPUPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUPATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_LETIMER0_DEFAULT (_SMU_PPUPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ +#define _SMU_PPUPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUPATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_IADC0_DEFAULT (_SMU_PPUPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ +#define _SMU_PPUPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUPATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_I2C0_DEFAULT (_SMU_PPUPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ +#define _SMU_PPUPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUPATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_WDOG0_DEFAULT (_SMU_PPUPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUPATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AMUXCP0_DEFAULT (_SMU_PPUPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ +#define _SMU_PPUPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ +#define _SMU_PPUPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ +#define _SMU_PPUPATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_EUART0_DEFAULT (_SMU_PPUPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ +#define _SMU_PPUPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_PPUPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_PPUPATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_CRYPTOACC_DEFAULT (_SMU_PPUPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUPATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUPATD1 */ +#define SMU_PPUPATD1_AHBRADIO_DEFAULT (_SMU_PPUPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUPATD1 */ + +/* Bit fields for SMU PPUSATD0 */ +#define _SMU_PPUSATD0_RESETVALUE 0xFFFFFFFFUL /**< Default value for SMU_PPUSATD0 */ +#define _SMU_PPUSATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU (0x1UL << 1) /**< EMU Secure Access */ +#define _SMU_PPUSATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUSATD0_EMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_EMU_DEFAULT (_SMU_PPUSATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU (0x1UL << 2) /**< CMU Secure Access */ +#define _SMU_PPUSATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUSATD0_CMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CMU_DEFAULT (_SMU_PPUSATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Secure Access */ +#define _SMU_PPUSATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUSATD0_HFXO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFXO0_DEFAULT (_SMU_PPUSATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Secure Access */ +#define _SMU_PPUSATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUSATD0_HFRCO0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_HFRCO0_DEFAULT (_SMU_PPUSATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO (0x1UL << 5) /**< FSRCO Secure Access */ +#define _SMU_PPUSATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUSATD0_FSRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_FSRCO_DEFAULT (_SMU_PPUSATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Secure Access */ +#define _SMU_PPUSATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUSATD0_DPLL0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DPLL0_DEFAULT (_SMU_PPUSATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO (0x1UL << 7) /**< LFXO Secure Access */ +#define _SMU_PPUSATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUSATD0_LFXO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFXO_DEFAULT (_SMU_PPUSATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO (0x1UL << 8) /**< LFRCO Secure Access */ +#define _SMU_PPUSATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUSATD0_LFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LFRCO_DEFAULT (_SMU_PPUSATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Secure Access */ +#define _SMU_PPUSATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUSATD0_ULFRCO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ULFRCO_DEFAULT (_SMU_PPUSATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC (0x1UL << 10) /**< MSC Secure Access */ +#define _SMU_PPUSATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUSATD0_MSC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_MSC_DEFAULT (_SMU_PPUSATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Secure Access */ +#define _SMU_PPUSATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUSATD0_ICACHE0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_ICACHE0_DEFAULT (_SMU_PPUSATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS (0x1UL << 12) /**< PRS Secure Access */ +#define _SMU_PPUSATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUSATD0_PRS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_PRS_DEFAULT (_SMU_PPUSATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO (0x1UL << 13) /**< GPIO Secure Access */ +#define _SMU_PPUSATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUSATD0_GPIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPIO_DEFAULT (_SMU_PPUSATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA (0x1UL << 14) /**< LDMA Secure Access */ +#define _SMU_PPUSATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMA_DEFAULT (_SMU_PPUSATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Secure Access */ +#define _SMU_PPUSATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUSATD0_LDMAXBAR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_LDMAXBAR_DEFAULT (_SMU_PPUSATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Secure Access */ +#define _SMU_PPUSATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUSATD0_TIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER0_DEFAULT (_SMU_PPUSATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Secure Access */ +#define _SMU_PPUSATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUSATD0_TIMER1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER1_DEFAULT (_SMU_PPUSATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Secure Access */ +#define _SMU_PPUSATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUSATD0_TIMER2_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER2_DEFAULT (_SMU_PPUSATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Secure Access */ +#define _SMU_PPUSATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUSATD0_TIMER3_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER3_DEFAULT (_SMU_PPUSATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Secure Access */ +#define _SMU_PPUSATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUSATD0_TIMER4_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_TIMER4_DEFAULT (_SMU_PPUSATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0 (0x1UL << 21) /**< USART0 Secure Access */ +#define _SMU_PPUSATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUSATD0_USART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART0_DEFAULT (_SMU_PPUSATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1 (0x1UL << 22) /**< USART1 Secure Access */ +#define _SMU_PPUSATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUSATD0_USART1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_USART1_DEFAULT (_SMU_PPUSATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC (0x1UL << 23) /**< BURTC Secure Access */ +#define _SMU_PPUSATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUSATD0_BURTC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURTC_DEFAULT (_SMU_PPUSATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1 (0x1UL << 24) /**< I2C1 Secure Access */ +#define _SMU_PPUSATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUSATD0_I2C1_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_I2C1_DEFAULT (_SMU_PPUSATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Secure Access */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUSATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Secure Access */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUSATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Secure Access */ +#define _SMU_PPUSATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUSATD0_SYSCFG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_SYSCFG_DEFAULT (_SMU_PPUSATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM (0x1UL << 28) /**< BURAM Secure Access */ +#define _SMU_PPUSATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUSATD0_BURAM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_BURAM_DEFAULT (_SMU_PPUSATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Secure Access */ +#define _SMU_PPUSATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUSATD0_IFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_IFADCDEBUG_DEFAULT (_SMU_PPUSATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC (0x1UL << 30) /**< GPCRC Secure Access */ +#define _SMU_PPUSATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUSATD0_GPCRC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_GPCRC_DEFAULT (_SMU_PPUSATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCI (0x1UL << 31) /**< DCI Secure Access */ +#define _SMU_PPUSATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ +#define _SMU_PPUSATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ +#define _SMU_PPUSATD0_DCI_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD0 */ +#define SMU_PPUSATD0_DCI_DEFAULT (_SMU_PPUSATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUSATD0 */ + +/* Bit fields for SMU PPUSATD1 */ +#define _SMU_PPUSATD1_RESETVALUE 0x0000FFFFUL /**< Default value for SMU_PPUSATD1 */ +#define _SMU_PPUSATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DCDC (0x1UL << 1) /**< DCDC Secure Access */ +#define _SMU_PPUSATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUSATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUSATD1_DCDC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_DCDC_DEFAULT (_SMU_PPUSATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM (0x1UL << 2) /**< PDM Secure Access */ +#define _SMU_PPUSATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUSATD1_PDM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_PDM_DEFAULT (_SMU_PPUSATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Secure Access */ +#define _SMU_PPUSATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUSATD1_RFSENSE_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RFSENSE_DEFAULT (_SMU_PPUSATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Secure Access */ +#define _SMU_PPUSATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUSATD1_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RADIOAES_DEFAULT (_SMU_PPUSATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU (0x1UL << 5) /**< SMU Secure Access */ +#define _SMU_PPUSATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUSATD1_SMU_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMU_DEFAULT (_SMU_PPUSATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Secure Access */ +#define _SMU_PPUSATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUSATD1_SMUCFGNS_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_SMUCFGNS_DEFAULT (_SMU_PPUSATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC (0x1UL << 7) /**< RTCC Secure Access */ +#define _SMU_PPUSATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUSATD1_RTCC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_RTCC_DEFAULT (_SMU_PPUSATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Secure Access */ +#define _SMU_PPUSATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUSATD1_LETIMER0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_LETIMER0_DEFAULT (_SMU_PPUSATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0 (0x1UL << 9) /**< IADC0 Secure Access */ +#define _SMU_PPUSATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUSATD1_IADC0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_IADC0_DEFAULT (_SMU_PPUSATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0 (0x1UL << 10) /**< I2C0 Secure Access */ +#define _SMU_PPUSATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUSATD1_I2C0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_I2C0_DEFAULT (_SMU_PPUSATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Secure Access */ +#define _SMU_PPUSATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUSATD1_WDOG0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_WDOG0_DEFAULT (_SMU_PPUSATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Secure Access */ +#define _SMU_PPUSATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUSATD1_AMUXCP0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AMUXCP0_DEFAULT (_SMU_PPUSATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUART0 (0x1UL << 13) /**< EUART0 Secure Access */ +#define _SMU_PPUSATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ +#define _SMU_PPUSATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ +#define _SMU_PPUSATD1_EUART0_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_EUART0_DEFAULT (_SMU_PPUSATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Secure Access */ +#define _SMU_PPUSATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_PPUSATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_PPUSATD1_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_CRYPTOACC_DEFAULT (_SMU_PPUSATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Secure Access */ +#define _SMU_PPUSATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUSATD1_AHBRADIO_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_PPUSATD1 */ +#define SMU_PPUSATD1_AHBRADIO_DEFAULT (_SMU_PPUSATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUSATD1 */ + +/* Bit fields for SMU PPUFS */ +#define _SMU_PPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUFS */ +#define _SMU_PPUFS_MASK 0x000000FFUL /**< Mask for SMU_PPUFS */ +#define _SMU_PPUFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUFS */ +#define SMU_PPUFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUFS */ + +/* Bit fields for SMU BMPUPATD0 */ +#define _SMU_BMPUPATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUPATD0 */ +#define _SMU_BMPUPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUPATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOAES_DEFAULT (_SMU_BMPUPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ +#define _SMU_BMPUPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_BMPUPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_BMPUPATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUPATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUPATD0 */ +#define SMU_BMPUPATD0_LDMA_DEFAULT (_SMU_BMPUPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUPATD0 */ + +/* Bit fields for SMU BMPUSATD0 */ +#define _SMU_BMPUSATD0_RESETVALUE 0x0000001FUL /**< Default value for SMU_BMPUSATD0 */ +#define _SMU_BMPUSATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES (0x1UL << 0) /**< RADIOAES DMA secure mode */ +#define _SMU_BMPUSATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUSATD0_RADIOAES_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOAES_DEFAULT (_SMU_BMPUSATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA secure mode */ +#define _SMU_BMPUSATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_BMPUSATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_BMPUSATD0_CRYPTOACC_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_CRYPTOACC_DEFAULT (_SMU_BMPUSATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager secure mode */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUSATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug secure mode */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUSATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA (0x1UL << 4) /**< MCU LDMA secure mode */ +#define _SMU_BMPUSATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUSATD0_LDMA_DEFAULT 0x00000001UL /**< Mode DEFAULT for SMU_BMPUSATD0 */ +#define SMU_BMPUSATD0_LDMA_DEFAULT (_SMU_BMPUSATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUSATD0 */ + +/* Bit fields for SMU BMPUFS */ +#define _SMU_BMPUFS_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFS */ +#define _SMU_BMPUFS_MASK 0x000000FFUL /**< Mask for SMU_BMPUFS */ +#define _SMU_BMPUFS_BMPUFSMASTERID_SHIFT 0 /**< Shift value for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_MASK 0xFFUL /**< Bit mask for SMU_BMPUFSMASTERID */ +#define _SMU_BMPUFS_BMPUFSMASTERID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFS */ +#define SMU_BMPUFS_BMPUFSMASTERID_DEFAULT (_SMU_BMPUFS_BMPUFSMASTERID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFS */ + +/* Bit fields for SMU BMPUFSADDR */ +#define _SMU_BMPUFSADDR_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_SHIFT 0 /**< Shift value for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SMU_BMPUFSADDR */ +#define _SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUFSADDR */ +#define SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT (_SMU_BMPUFSADDR_BMPUFSADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUFSADDR */ + +/* Bit fields for SMU ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES0 */ +#define _SMU_ESAURTYPES0_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS (0x1UL << 12) /**< Region 3 Non-Secure Type */ +#define _SMU_ESAURTYPES0_ESAUR3NS_SHIFT 12 /**< Shift value for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR3NS */ +#define _SMU_ESAURTYPES0_ESAUR3NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES0 */ +#define SMU_ESAURTYPES0_ESAUR3NS_DEFAULT (_SMU_ESAURTYPES0_ESAUR3NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES0 */ + +/* Bit fields for SMU ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_RESETVALUE 0x00000000UL /**< Default value for SMU_ESAURTYPES1 */ +#define _SMU_ESAURTYPES1_MASK 0x00001000UL /**< Mask for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS (0x1UL << 12) /**< Region 11 Non-Secure Type */ +#define _SMU_ESAURTYPES1_ESAUR11NS_SHIFT 12 /**< Shift value for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_MASK 0x1000UL /**< Bit mask for SMU_ESAUR11NS */ +#define _SMU_ESAURTYPES1_ESAUR11NS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_ESAURTYPES1 */ +#define SMU_ESAURTYPES1_ESAUR11NS_DEFAULT (_SMU_ESAURTYPES1_ESAUR11NS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAURTYPES1 */ + +/* Bit fields for SMU ESAUMRB01 */ +#define _SMU_ESAUMRB01_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_SHIFT 12 /**< Shift value for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB01 */ +#define _SMU_ESAUMRB01_ESAUMRB01_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB01 */ +#define SMU_ESAUMRB01_ESAUMRB01_DEFAULT (_SMU_ESAUMRB01_ESAUMRB01_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB01 */ + +/* Bit fields for SMU ESAUMRB12 */ +#define _SMU_ESAUMRB12_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_SHIFT 12 /**< Shift value for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB12 */ +#define _SMU_ESAUMRB12_ESAUMRB12_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB12 */ +#define SMU_ESAUMRB12_ESAUMRB12_DEFAULT (_SMU_ESAUMRB12_ESAUMRB12_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB12 */ + +/* Bit fields for SMU ESAUMRB45 */ +#define _SMU_ESAUMRB45_RESETVALUE 0x02000000UL /**< Default value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_SHIFT 12 /**< Shift value for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB45 */ +#define _SMU_ESAUMRB45_ESAUMRB45_DEFAULT 0x00002000UL /**< Mode DEFAULT for SMU_ESAUMRB45 */ +#define SMU_ESAUMRB45_ESAUMRB45_DEFAULT (_SMU_ESAUMRB45_ESAUMRB45_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB45 */ + +/* Bit fields for SMU ESAUMRB56 */ +#define _SMU_ESAUMRB56_RESETVALUE 0x04000000UL /**< Default value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_MASK 0x0FFFF000UL /**< Mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_SHIFT 12 /**< Shift value for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_MASK 0xFFFF000UL /**< Bit mask for SMU_ESAUMRB56 */ +#define _SMU_ESAUMRB56_ESAUMRB56_DEFAULT 0x00004000UL /**< Mode DEFAULT for SMU_ESAUMRB56 */ +#define SMU_ESAUMRB56_ESAUMRB56_DEFAULT (_SMU_ESAUMRB56_ESAUMRB56_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_ESAUMRB56 */ + +/** @} End of group EFR32BG22_SMU_BitFields */ +/** @} End of group EFR32BG22_SMU */ +/**************************************************************************//** + * @defgroup EFR32BG22_SMU_CFGNS SMU_CFGNS + * @{ + * @brief EFR32BG22 SMU_CFGNS Register Declaration. + *****************************************************************************/ + +/** SMU_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK; /**< Non-Secure Lock */ + __IOM uint32_t NSIF; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED1[3U]; /**< Reserved for future use */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0; /**< PPU Non-secure PATD Register 0 */ + __IOM uint32_t PPUNSPATD1; /**< PPU Non-secure PATD Register 1 */ + uint32_t RESERVED3[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS; /**< PPU Non-secure Fault Status */ + uint32_t RESERVED4[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0; /**< BMPU Non-Secure PATD Register 0 */ + uint32_t RESERVED5[63U]; /**< Reserved for future use */ + uint32_t RESERVED6[876U]; /**< Reserved for future use */ + uint32_t RESERVED7[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_SET; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_SET; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_SET; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_SET; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED8[3U]; /**< Reserved for future use */ + uint32_t RESERVED9[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_SET; /**< PPU Non-secure PATD Register 0 */ + __IOM uint32_t PPUNSPATD1_SET; /**< PPU Non-secure PATD Register 1 */ + uint32_t RESERVED10[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_SET; /**< PPU Non-secure Fault Status */ + uint32_t RESERVED11[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_SET; /**< BMPU Non-Secure PATD Register 0 */ + uint32_t RESERVED12[63U]; /**< Reserved for future use */ + uint32_t RESERVED13[876U]; /**< Reserved for future use */ + uint32_t RESERVED14[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_CLR; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_CLR; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_CLR; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_CLR; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED15[3U]; /**< Reserved for future use */ + uint32_t RESERVED16[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_CLR; /**< PPU Non-secure PATD Register 0 */ + __IOM uint32_t PPUNSPATD1_CLR; /**< PPU Non-secure PATD Register 1 */ + uint32_t RESERVED17[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_CLR; /**< PPU Non-secure Fault Status */ + uint32_t RESERVED18[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_CLR; /**< BMPU Non-Secure PATD Register 0 */ + uint32_t RESERVED19[63U]; /**< Reserved for future use */ + uint32_t RESERVED20[876U]; /**< Reserved for future use */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t NSSTATUS_TGL; /**< Non-Secure Status */ + __IOM uint32_t NSLOCK_TGL; /**< Non-Secure Lock */ + __IOM uint32_t NSIF_TGL; /**< Non-Secure Interrupt Flag */ + __IOM uint32_t NSIEN_TGL; /**< Non-Secure Interrupt Enable */ + uint32_t RESERVED22[3U]; /**< Reserved for future use */ + uint32_t RESERVED23[8U]; /**< Reserved for future use */ + __IOM uint32_t PPUNSPATD0_TGL; /**< PPU Non-secure PATD Register 0 */ + __IOM uint32_t PPUNSPATD1_TGL; /**< PPU Non-secure PATD Register 1 */ + uint32_t RESERVED24[62U]; /**< Reserved for future use */ + __IM uint32_t PPUNSFS_TGL; /**< PPU Non-secure Fault Status */ + uint32_t RESERVED25[3U]; /**< Reserved for future use */ + __IOM uint32_t BMPUNSPATD0_TGL; /**< BMPU Non-Secure PATD Register 0 */ + uint32_t RESERVED26[63U]; /**< Reserved for future use */ +} SMU_CFGNS_TypeDef; +/** @} End of group EFR32BG22_SMU_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_SMU_CFGNS + * @{ + * @defgroup EFR32BG22_SMU_CFGNS_BitFields SMU_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SMU NSSTATUS */ +#define _SMU_NSSTATUS_RESETVALUE 0x00000000UL /**< Default value for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_MASK 0x00000001UL /**< Mask for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK (0x1UL << 0) /**< SMUNS Lock Status */ +#define _SMU_NSSTATUS_SMUNSLOCK_SHIFT 0 /**< Shift value for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_MASK 0x1UL /**< Bit mask for SMU_SMUNSLOCK */ +#define _SMU_NSSTATUS_SMUNSLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SMU_NSSTATUS */ +#define _SMU_NSSTATUS_SMUNSLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_DEFAULT (_SMU_NSSTATUS_SMUNSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_UNLOCKED (_SMU_NSSTATUS_SMUNSLOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for SMU_NSSTATUS */ +#define SMU_NSSTATUS_SMUNSLOCK_LOCKED (_SMU_NSSTATUS_SMUNSLOCK_LOCKED << 0) /**< Shifted mode LOCKED for SMU_NSSTATUS */ + +/* Bit fields for SMU NSLOCK */ +#define _SMU_NSLOCK_RESETVALUE 0x00000000UL /**< Default value for SMU_NSLOCK */ +#define _SMU_NSLOCK_MASK 0x00FFFFFFUL /**< Mask for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_SHIFT 0 /**< Shift value for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_MASK 0xFFFFFFUL /**< Bit mask for SMU_SMUNSLOCKKEY */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSLOCK */ +#define _SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK 0x00ACCE55UL /**< Mode UNLOCK for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT (_SMU_NSLOCK_SMUNSLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSLOCK */ +#define SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK (_SMU_NSLOCK_SMUNSLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SMU_NSLOCK */ + +/* Bit fields for SMU NSIF */ +#define _SMU_NSIF_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIF */ +#define _SMU_NSIF_MASK 0x00000005UL /**< Mask for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Flag */ +#define _SMU_NSIF_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIF_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSPRIV_DEFAULT (_SMU_NSIF_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Flag */ +#define _SMU_NSIF_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIF_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIF */ +#define SMU_NSIF_PPUNSINST_DEFAULT (_SMU_NSIF_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIF */ + +/* Bit fields for SMU NSIEN */ +#define _SMU_NSIEN_RESETVALUE 0x00000000UL /**< Default value for SMU_NSIEN */ +#define _SMU_NSIEN_MASK 0x00000005UL /**< Mask for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV (0x1UL << 0) /**< PPUNS Privilege Interrupt Enable */ +#define _SMU_NSIEN_PPUNSPRIV_SHIFT 0 /**< Shift value for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_MASK 0x1UL /**< Bit mask for SMU_PPUNSPRIV */ +#define _SMU_NSIEN_PPUNSPRIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSPRIV_DEFAULT (_SMU_NSIEN_PPUNSPRIV_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST (0x1UL << 2) /**< PPUNS Instruction Interrupt Enable */ +#define _SMU_NSIEN_PPUNSINST_SHIFT 2 /**< Shift value for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_MASK 0x4UL /**< Bit mask for SMU_PPUNSINST */ +#define _SMU_NSIEN_PPUNSINST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_NSIEN */ +#define SMU_NSIEN_PPUNSINST_DEFAULT (_SMU_NSIEN_PPUNSINST_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_NSIEN */ + +/* Bit fields for SMU PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD0 */ +#define _SMU_PPUNSPATD0_MASK 0xFFFFFFFFUL /**< Mask for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU (0x1UL << 1) /**< EMU Privileged Access */ +#define _SMU_PPUNSPATD0_EMU_SHIFT 1 /**< Shift value for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_MASK 0x2UL /**< Bit mask for SMU_EMU */ +#define _SMU_PPUNSPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_EMU_DEFAULT (_SMU_PPUNSPATD0_EMU_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU (0x1UL << 2) /**< CMU Privileged Access */ +#define _SMU_PPUNSPATD0_CMU_SHIFT 2 /**< Shift value for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_MASK 0x4UL /**< Bit mask for SMU_CMU */ +#define _SMU_PPUNSPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CMU_DEFAULT (_SMU_PPUNSPATD0_CMU_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0 (0x1UL << 3) /**< HFXO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFXO0_SHIFT 3 /**< Shift value for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_MASK 0x8UL /**< Bit mask for SMU_HFXO0 */ +#define _SMU_PPUNSPATD0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFXO0_DEFAULT (_SMU_PPUNSPATD0_HFXO0_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0 (0x1UL << 4) /**< HFRCO0 Privileged Access */ +#define _SMU_PPUNSPATD0_HFRCO0_SHIFT 4 /**< Shift value for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_MASK 0x10UL /**< Bit mask for SMU_HFRCO0 */ +#define _SMU_PPUNSPATD0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_HFRCO0_DEFAULT (_SMU_PPUNSPATD0_HFRCO0_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO (0x1UL << 5) /**< FSRCO Privileged Access */ +#define _SMU_PPUNSPATD0_FSRCO_SHIFT 5 /**< Shift value for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_MASK 0x20UL /**< Bit mask for SMU_FSRCO */ +#define _SMU_PPUNSPATD0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_FSRCO_DEFAULT (_SMU_PPUNSPATD0_FSRCO_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0 (0x1UL << 6) /**< DPLL0 Privileged Access */ +#define _SMU_PPUNSPATD0_DPLL0_SHIFT 6 /**< Shift value for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_MASK 0x40UL /**< Bit mask for SMU_DPLL0 */ +#define _SMU_PPUNSPATD0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DPLL0_DEFAULT (_SMU_PPUNSPATD0_DPLL0_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO (0x1UL << 7) /**< LFXO Privileged Access */ +#define _SMU_PPUNSPATD0_LFXO_SHIFT 7 /**< Shift value for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_MASK 0x80UL /**< Bit mask for SMU_LFXO */ +#define _SMU_PPUNSPATD0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFXO_DEFAULT (_SMU_PPUNSPATD0_LFXO_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO (0x1UL << 8) /**< LFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_LFRCO_SHIFT 8 /**< Shift value for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_MASK 0x100UL /**< Bit mask for SMU_LFRCO */ +#define _SMU_PPUNSPATD0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LFRCO_DEFAULT (_SMU_PPUNSPATD0_LFRCO_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO (0x1UL << 9) /**< ULFRCO Privileged Access */ +#define _SMU_PPUNSPATD0_ULFRCO_SHIFT 9 /**< Shift value for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_MASK 0x200UL /**< Bit mask for SMU_ULFRCO */ +#define _SMU_PPUNSPATD0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ULFRCO_DEFAULT (_SMU_PPUNSPATD0_ULFRCO_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC (0x1UL << 10) /**< MSC Privileged Access */ +#define _SMU_PPUNSPATD0_MSC_SHIFT 10 /**< Shift value for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_MASK 0x400UL /**< Bit mask for SMU_MSC */ +#define _SMU_PPUNSPATD0_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_MSC_DEFAULT (_SMU_PPUNSPATD0_MSC_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0 (0x1UL << 11) /**< ICACHE0 Privileged Access */ +#define _SMU_PPUNSPATD0_ICACHE0_SHIFT 11 /**< Shift value for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_MASK 0x800UL /**< Bit mask for SMU_ICACHE0 */ +#define _SMU_PPUNSPATD0_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_ICACHE0_DEFAULT (_SMU_PPUNSPATD0_ICACHE0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS (0x1UL << 12) /**< PRS Privileged Access */ +#define _SMU_PPUNSPATD0_PRS_SHIFT 12 /**< Shift value for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_MASK 0x1000UL /**< Bit mask for SMU_PRS */ +#define _SMU_PPUNSPATD0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_PRS_DEFAULT (_SMU_PPUNSPATD0_PRS_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO (0x1UL << 13) /**< GPIO Privileged Access */ +#define _SMU_PPUNSPATD0_GPIO_SHIFT 13 /**< Shift value for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_MASK 0x2000UL /**< Bit mask for SMU_GPIO */ +#define _SMU_PPUNSPATD0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPIO_DEFAULT (_SMU_PPUNSPATD0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA (0x1UL << 14) /**< LDMA Privileged Access */ +#define _SMU_PPUNSPATD0_LDMA_SHIFT 14 /**< Shift value for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_MASK 0x4000UL /**< Bit mask for SMU_LDMA */ +#define _SMU_PPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMA_DEFAULT (_SMU_PPUNSPATD0_LDMA_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR (0x1UL << 15) /**< LDMAXBAR Privileged Access */ +#define _SMU_PPUNSPATD0_LDMAXBAR_SHIFT 15 /**< Shift value for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_MASK 0x8000UL /**< Bit mask for SMU_LDMAXBAR */ +#define _SMU_PPUNSPATD0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_LDMAXBAR_DEFAULT (_SMU_PPUNSPATD0_LDMAXBAR_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0 (0x1UL << 16) /**< TIMER0 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER0_SHIFT 16 /**< Shift value for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_MASK 0x10000UL /**< Bit mask for SMU_TIMER0 */ +#define _SMU_PPUNSPATD0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER0_DEFAULT (_SMU_PPUNSPATD0_TIMER0_DEFAULT << 16) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1 (0x1UL << 17) /**< TIMER1 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER1_SHIFT 17 /**< Shift value for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_MASK 0x20000UL /**< Bit mask for SMU_TIMER1 */ +#define _SMU_PPUNSPATD0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER1_DEFAULT (_SMU_PPUNSPATD0_TIMER1_DEFAULT << 17) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2 (0x1UL << 18) /**< TIMER2 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER2_SHIFT 18 /**< Shift value for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_MASK 0x40000UL /**< Bit mask for SMU_TIMER2 */ +#define _SMU_PPUNSPATD0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER2_DEFAULT (_SMU_PPUNSPATD0_TIMER2_DEFAULT << 18) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3 (0x1UL << 19) /**< TIMER3 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER3_SHIFT 19 /**< Shift value for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_MASK 0x80000UL /**< Bit mask for SMU_TIMER3 */ +#define _SMU_PPUNSPATD0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER3_DEFAULT (_SMU_PPUNSPATD0_TIMER3_DEFAULT << 19) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4 (0x1UL << 20) /**< TIMER4 Privileged Access */ +#define _SMU_PPUNSPATD0_TIMER4_SHIFT 20 /**< Shift value for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_MASK 0x100000UL /**< Bit mask for SMU_TIMER4 */ +#define _SMU_PPUNSPATD0_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_TIMER4_DEFAULT (_SMU_PPUNSPATD0_TIMER4_DEFAULT << 20) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0 (0x1UL << 21) /**< USART0 Privileged Access */ +#define _SMU_PPUNSPATD0_USART0_SHIFT 21 /**< Shift value for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_MASK 0x200000UL /**< Bit mask for SMU_USART0 */ +#define _SMU_PPUNSPATD0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART0_DEFAULT (_SMU_PPUNSPATD0_USART0_DEFAULT << 21) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1 (0x1UL << 22) /**< USART1 Privileged Access */ +#define _SMU_PPUNSPATD0_USART1_SHIFT 22 /**< Shift value for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_MASK 0x400000UL /**< Bit mask for SMU_USART1 */ +#define _SMU_PPUNSPATD0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_USART1_DEFAULT (_SMU_PPUNSPATD0_USART1_DEFAULT << 22) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC (0x1UL << 23) /**< BURTC Privileged Access */ +#define _SMU_PPUNSPATD0_BURTC_SHIFT 23 /**< Shift value for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_MASK 0x800000UL /**< Bit mask for SMU_BURTC */ +#define _SMU_PPUNSPATD0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURTC_DEFAULT (_SMU_PPUNSPATD0_BURTC_DEFAULT << 23) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1 (0x1UL << 24) /**< I2C1 Privileged Access */ +#define _SMU_PPUNSPATD0_I2C1_SHIFT 24 /**< Shift value for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_MASK 0x1000000UL /**< Bit mask for SMU_I2C1 */ +#define _SMU_PPUNSPATD0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_I2C1_DEFAULT (_SMU_PPUNSPATD0_I2C1_DEFAULT << 24) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL (0x1UL << 25) /**< CHIPTESTCTRL Privileged Access */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_SHIFT 25 /**< Shift value for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_MASK 0x2000000UL /**< Bit mask for SMU_CHIPTESTCTRL */ +#define _SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT (_SMU_PPUNSPATD0_CHIPTESTCTRL_DEFAULT << 25) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS (0x1UL << 26) /**< SYSCFGCFGNS Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_SHIFT 26 /**< Shift value for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_MASK 0x4000000UL /**< Bit mask for SMU_SYSCFGCFGNS */ +#define _SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT (_SMU_PPUNSPATD0_SYSCFGCFGNS_DEFAULT << 26) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG (0x1UL << 27) /**< SYSCFG Privileged Access */ +#define _SMU_PPUNSPATD0_SYSCFG_SHIFT 27 /**< Shift value for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_MASK 0x8000000UL /**< Bit mask for SMU_SYSCFG */ +#define _SMU_PPUNSPATD0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_SYSCFG_DEFAULT (_SMU_PPUNSPATD0_SYSCFG_DEFAULT << 27) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM (0x1UL << 28) /**< BURAM Privileged Access */ +#define _SMU_PPUNSPATD0_BURAM_SHIFT 28 /**< Shift value for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_MASK 0x10000000UL /**< Bit mask for SMU_BURAM */ +#define _SMU_PPUNSPATD0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_BURAM_DEFAULT (_SMU_PPUNSPATD0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG (0x1UL << 29) /**< IFADCDEBUG Privileged Access */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_SHIFT 29 /**< Shift value for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_MASK 0x20000000UL /**< Bit mask for SMU_IFADCDEBUG */ +#define _SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT (_SMU_PPUNSPATD0_IFADCDEBUG_DEFAULT << 29) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC (0x1UL << 30) /**< GPCRC Privileged Access */ +#define _SMU_PPUNSPATD0_GPCRC_SHIFT 30 /**< Shift value for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_MASK 0x40000000UL /**< Bit mask for SMU_GPCRC */ +#define _SMU_PPUNSPATD0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_GPCRC_DEFAULT (_SMU_PPUNSPATD0_GPCRC_DEFAULT << 30) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCI (0x1UL << 31) /**< DCI Privileged Access */ +#define _SMU_PPUNSPATD0_DCI_SHIFT 31 /**< Shift value for SMU_DCI */ +#define _SMU_PPUNSPATD0_DCI_MASK 0x80000000UL /**< Bit mask for SMU_DCI */ +#define _SMU_PPUNSPATD0_DCI_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD0 */ +#define SMU_PPUNSPATD0_DCI_DEFAULT (_SMU_PPUNSPATD0_DCI_DEFAULT << 31) /**< Shifted mode DEFAULT for SMU_PPUNSPATD0 */ + +/* Bit fields for SMU PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSPATD1 */ +#define _SMU_PPUNSPATD1_MASK 0x0000FFFFUL /**< Mask for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DCDC (0x1UL << 1) /**< DCDC Privileged Access */ +#define _SMU_PPUNSPATD1_DCDC_SHIFT 1 /**< Shift value for SMU_DCDC */ +#define _SMU_PPUNSPATD1_DCDC_MASK 0x2UL /**< Bit mask for SMU_DCDC */ +#define _SMU_PPUNSPATD1_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_DCDC_DEFAULT (_SMU_PPUNSPATD1_DCDC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM (0x1UL << 2) /**< PDM Privileged Access */ +#define _SMU_PPUNSPATD1_PDM_SHIFT 2 /**< Shift value for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_MASK 0x4UL /**< Bit mask for SMU_PDM */ +#define _SMU_PPUNSPATD1_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_PDM_DEFAULT (_SMU_PPUNSPATD1_PDM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE (0x1UL << 3) /**< RFSENSE Privileged Access */ +#define _SMU_PPUNSPATD1_RFSENSE_SHIFT 3 /**< Shift value for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_MASK 0x8UL /**< Bit mask for SMU_RFSENSE */ +#define _SMU_PPUNSPATD1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RFSENSE_DEFAULT (_SMU_PPUNSPATD1_RFSENSE_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES (0x1UL << 4) /**< RADIOAES Privileged Access */ +#define _SMU_PPUNSPATD1_RADIOAES_SHIFT 4 /**< Shift value for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_MASK 0x10UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_PPUNSPATD1_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RADIOAES_DEFAULT (_SMU_PPUNSPATD1_RADIOAES_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU (0x1UL << 5) /**< SMU Privileged Access */ +#define _SMU_PPUNSPATD1_SMU_SHIFT 5 /**< Shift value for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_MASK 0x20UL /**< Bit mask for SMU_SMU */ +#define _SMU_PPUNSPATD1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMU_DEFAULT (_SMU_PPUNSPATD1_SMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS (0x1UL << 6) /**< SMUCFGNS Privileged Access */ +#define _SMU_PPUNSPATD1_SMUCFGNS_SHIFT 6 /**< Shift value for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_MASK 0x40UL /**< Bit mask for SMU_SMUCFGNS */ +#define _SMU_PPUNSPATD1_SMUCFGNS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_SMUCFGNS_DEFAULT (_SMU_PPUNSPATD1_SMUCFGNS_DEFAULT << 6) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC (0x1UL << 7) /**< RTCC Privileged Access */ +#define _SMU_PPUNSPATD1_RTCC_SHIFT 7 /**< Shift value for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_MASK 0x80UL /**< Bit mask for SMU_RTCC */ +#define _SMU_PPUNSPATD1_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_RTCC_DEFAULT (_SMU_PPUNSPATD1_RTCC_DEFAULT << 7) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0 (0x1UL << 8) /**< LETIMER0 Privileged Access */ +#define _SMU_PPUNSPATD1_LETIMER0_SHIFT 8 /**< Shift value for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_MASK 0x100UL /**< Bit mask for SMU_LETIMER0 */ +#define _SMU_PPUNSPATD1_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_LETIMER0_DEFAULT (_SMU_PPUNSPATD1_LETIMER0_DEFAULT << 8) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0 (0x1UL << 9) /**< IADC0 Privileged Access */ +#define _SMU_PPUNSPATD1_IADC0_SHIFT 9 /**< Shift value for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_MASK 0x200UL /**< Bit mask for SMU_IADC0 */ +#define _SMU_PPUNSPATD1_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_IADC0_DEFAULT (_SMU_PPUNSPATD1_IADC0_DEFAULT << 9) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0 (0x1UL << 10) /**< I2C0 Privileged Access */ +#define _SMU_PPUNSPATD1_I2C0_SHIFT 10 /**< Shift value for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_MASK 0x400UL /**< Bit mask for SMU_I2C0 */ +#define _SMU_PPUNSPATD1_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_I2C0_DEFAULT (_SMU_PPUNSPATD1_I2C0_DEFAULT << 10) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0 (0x1UL << 11) /**< WDOG0 Privileged Access */ +#define _SMU_PPUNSPATD1_WDOG0_SHIFT 11 /**< Shift value for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_MASK 0x800UL /**< Bit mask for SMU_WDOG0 */ +#define _SMU_PPUNSPATD1_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_WDOG0_DEFAULT (_SMU_PPUNSPATD1_WDOG0_DEFAULT << 11) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0 (0x1UL << 12) /**< AMUXCP0 Privileged Access */ +#define _SMU_PPUNSPATD1_AMUXCP0_SHIFT 12 /**< Shift value for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_MASK 0x1000UL /**< Bit mask for SMU_AMUXCP0 */ +#define _SMU_PPUNSPATD1_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AMUXCP0_DEFAULT (_SMU_PPUNSPATD1_AMUXCP0_DEFAULT << 12) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUART0 (0x1UL << 13) /**< EUART0 Privileged Access */ +#define _SMU_PPUNSPATD1_EUART0_SHIFT 13 /**< Shift value for SMU_EUART0 */ +#define _SMU_PPUNSPATD1_EUART0_MASK 0x2000UL /**< Bit mask for SMU_EUART0 */ +#define _SMU_PPUNSPATD1_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_EUART0_DEFAULT (_SMU_PPUNSPATD1_EUART0_DEFAULT << 13) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_CRYPTOACC (0x1UL << 14) /**< CRYPTOACC Privileged Access */ +#define _SMU_PPUNSPATD1_CRYPTOACC_SHIFT 14 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_PPUNSPATD1_CRYPTOACC_MASK 0x4000UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_PPUNSPATD1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_CRYPTOACC_DEFAULT (_SMU_PPUNSPATD1_CRYPTOACC_DEFAULT << 14) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO (0x1UL << 15) /**< AHBRADIO Privileged Access */ +#define _SMU_PPUNSPATD1_AHBRADIO_SHIFT 15 /**< Shift value for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_MASK 0x8000UL /**< Bit mask for SMU_AHBRADIO */ +#define _SMU_PPUNSPATD1_AHBRADIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSPATD1 */ +#define SMU_PPUNSPATD1_AHBRADIO_DEFAULT (_SMU_PPUNSPATD1_AHBRADIO_DEFAULT << 15) /**< Shifted mode DEFAULT for SMU_PPUNSPATD1 */ + +/* Bit fields for SMU PPUNSFS */ +#define _SMU_PPUNSFS_RESETVALUE 0x00000000UL /**< Default value for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_MASK 0x000000FFUL /**< Mask for SMU_PPUNSFS */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_SHIFT 0 /**< Shift value for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_MASK 0xFFUL /**< Bit mask for SMU_PPUFSPERIPHID */ +#define _SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUNSFS */ +#define SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT (_SMU_PPUNSFS_PPUFSPERIPHID_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_PPUNSFS */ + +/* Bit fields for SMU BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_RESETVALUE 0x00000000UL /**< Default value for SMU_BMPUNSPATD0 */ +#define _SMU_BMPUNSPATD0_MASK 0x0000001FUL /**< Mask for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES (0x1UL << 0) /**< RADIO AES DMA privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOAES_SHIFT 0 /**< Shift value for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_MASK 0x1UL /**< Bit mask for SMU_RADIOAES */ +#define _SMU_BMPUNSPATD0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOAES_DEFAULT (_SMU_BMPUNSPATD0_RADIOAES_DEFAULT << 0) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_CRYPTOACC (0x1UL << 1) /**< CRYPTOACC DMA privileged mode */ +#define _SMU_BMPUNSPATD0_CRYPTOACC_SHIFT 1 /**< Shift value for SMU_CRYPTOACC */ +#define _SMU_BMPUNSPATD0_CRYPTOACC_MASK 0x2UL /**< Bit mask for SMU_CRYPTOACC */ +#define _SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT (_SMU_BMPUNSPATD0_CRYPTOACC_DEFAULT << 1) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM (0x1UL << 2) /**< RADIO subsystem manager privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_SHIFT 2 /**< Shift value for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_MASK 0x4UL /**< Bit mask for SMU_RADIOSUBSYSTEM */ +#define _SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT (_SMU_BMPUNSPATD0_RADIOSUBSYSTEM_DEFAULT << 2) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG (0x1UL << 3) /**< RADIO IFADC debug privileged mode */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_SHIFT 3 /**< Shift value for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_MASK 0x8UL /**< Bit mask for SMU_RADIOIFADCDEBUG */ +#define _SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT (_SMU_BMPUNSPATD0_RADIOIFADCDEBUG_DEFAULT << 3) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA (0x1UL << 4) /**< MCU LDMA privileged mode */ +#define _SMU_BMPUNSPATD0_LDMA_SHIFT 4 /**< Shift value for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_MASK 0x10UL /**< Bit mask for SMU_LDMA */ +#define _SMU_BMPUNSPATD0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_BMPUNSPATD0 */ +#define SMU_BMPUNSPATD0_LDMA_DEFAULT (_SMU_BMPUNSPATD0_LDMA_DEFAULT << 4) /**< Shifted mode DEFAULT for SMU_BMPUNSPATD0 */ + +/** @} End of group EFR32BG22_SMU_CFGNS_BitFields */ +/** @} End of group EFR32BG22_SMU_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32BG22_SMU_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h index 2d3b0f3..8bf8c05 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_syscfg.h @@ -1,599 +1,599 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 SYSCFG register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_SYSCFG_H -#define EFR32BG22_SYSCFG_H -#define SYSCFG_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_SYSCFG SYSCFG - * @{ - * @brief EFR32BG22 SYSCFG Register Declaration. - *****************************************************************************/ - -/** SYSCFG Register Declaration. */ -typedef struct { - __IOM uint32_t IF; /**< Interrupt Flag */ - __IOM uint32_t IEN; /**< Interrupt Enable */ - uint32_t RESERVED0[2U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ - uint32_t RESERVED2[55U]; /**< Reserved for future use */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - uint32_t RESERVED4[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL; /**< Memory System Control */ - uint32_t RESERVED5[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t DMEM0ECCADDR; /**< DMEM0 ECC Address */ - __IOM uint32_t DMEM0ECCCTRL; /**< DMEM0 ECC Control */ - uint32_t RESERVED7[122U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ - uint32_t RESERVED10[122U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0; /**< Root Data Register 0 */ - __IOM uint32_t ROOTDATA1; /**< Root Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ - uint32_t RESERVED11[637U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable */ - uint32_t RESERVED12[2U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ - uint32_t RESERVED13[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ - uint32_t RESERVED14[55U]; /**< Reserved for future use */ - uint32_t RESERVED15[1U]; /**< Reserved for future use */ - uint32_t RESERVED16[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_SET; /**< Memory System Control */ - uint32_t RESERVED17[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ - uint32_t RESERVED18[1U]; /**< Reserved for future use */ - __IM uint32_t DMEM0ECCADDR_SET; /**< DMEM0 ECC Address */ - __IOM uint32_t DMEM0ECCCTRL_SET; /**< DMEM0 ECC Control */ - uint32_t RESERVED19[122U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */ - uint32_t RESERVED20[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED21[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ - uint32_t RESERVED22[122U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_SET; /**< Root Data Register 0 */ - __IOM uint32_t ROOTDATA1_SET; /**< Root Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ - uint32_t RESERVED23[637U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ - uint32_t RESERVED24[2U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ - uint32_t RESERVED25[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ - uint32_t RESERVED26[55U]; /**< Reserved for future use */ - uint32_t RESERVED27[1U]; /**< Reserved for future use */ - uint32_t RESERVED28[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_CLR; /**< Memory System Control */ - uint32_t RESERVED29[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ - uint32_t RESERVED30[1U]; /**< Reserved for future use */ - __IM uint32_t DMEM0ECCADDR_CLR; /**< DMEM0 ECC Address */ - __IOM uint32_t DMEM0ECCCTRL_CLR; /**< DMEM0 ECC Control */ - uint32_t RESERVED31[122U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */ - uint32_t RESERVED32[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED33[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ - uint32_t RESERVED34[122U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_CLR; /**< Root Data Register 0 */ - __IOM uint32_t ROOTDATA1_CLR; /**< Root Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ - uint32_t RESERVED35[637U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ - uint32_t RESERVED36[2U]; /**< Reserved for future use */ - __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ - __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ - uint32_t RESERVED37[2U]; /**< Reserved for future use */ - __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ - uint32_t RESERVED38[55U]; /**< Reserved for future use */ - uint32_t RESERVED39[1U]; /**< Reserved for future use */ - uint32_t RESERVED40[63U]; /**< Reserved for future use */ - __IOM uint32_t CTRL_TGL; /**< Memory System Control */ - uint32_t RESERVED41[1U]; /**< Reserved for future use */ - __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ - uint32_t RESERVED42[1U]; /**< Reserved for future use */ - __IM uint32_t DMEM0ECCADDR_TGL; /**< DMEM0 ECC Address */ - __IOM uint32_t DMEM0ECCCTRL_TGL; /**< DMEM0 ECC Control */ - uint32_t RESERVED43[122U]; /**< Reserved for future use */ - __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */ - uint32_t RESERVED44[1U]; /**< Reserved for future use */ - __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ - uint32_t RESERVED45[1U]; /**< Reserved for future use */ - __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ - __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ - uint32_t RESERVED46[122U]; /**< Reserved for future use */ - __IOM uint32_t ROOTDATA0_TGL; /**< Root Data Register 0 */ - __IOM uint32_t ROOTDATA1_TGL; /**< Root Data Register 1 */ - __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ -} SYSCFG_TypeDef; -/** @} End of group EFR32BG22_SYSCFG */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_SYSCFG - * @{ - * @defgroup EFR32BG22_SYSCFG_BitFields SYSCFG Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SYSCFG IF */ -#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ -#define _SYSCFG_IF_MASK 0x3303000FUL /**< Mask for SYSCFG_IF */ -#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt 0 */ -#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt 1 */ -#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt 2 */ -#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt 3 */ -#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ -#define _SYSCFG_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ -#define _SYSCFG_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_RAMERR1B_DEFAULT (_SYSCFG_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ -#define _SYSCFG_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ -#define _SYSCFG_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_RAMERR2B_DEFAULT (_SYSCFG_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-Bit Error Interrupt Flag */ -#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ -#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ - -/* Bit fields for SYSCFG IEN */ -#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ -#define _SYSCFG_IEN_MASK 0x3303000FUL /**< Mask for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software interrupt 0 */ -#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ -#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software interrupt 1 */ -#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ -#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software interrupt 2 */ -#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ -#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software interrupt 3 */ -#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ -#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_RAMERR1B (0x1UL << 16) /**< RAM 1-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ -#define _SYSCFG_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ -#define _SYSCFG_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_RAMERR1B_DEFAULT (_SYSCFG_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_RAMERR2B (0x1UL << 17) /**< RAM 2-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ -#define _SYSCFG_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ -#define _SYSCFG_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_RAMERR2B_DEFAULT (_SYSCFG_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ -#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ -#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ -#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-bit Error Interrupt Enable */ -#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ -#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ -#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ - -/* Bit fields for SYSCFG CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000D02UL /**< Default value for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000034UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ -#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ -#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ - -/* Bit fields for SYSCFG CHIPREV */ -#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ -#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ -#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_PG22 0x00000018UL /**< Mode PG22 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_MG22 0x00000034UL /**< Mode MG22 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_BG22 0x00000035UL /**< Mode BG22 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_FAMILY_FG22 0x00000037UL /**< Mode FG22 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_PG22 (_SYSCFG_CHIPREV_FAMILY_PG22 << 6) /**< Shifted mode PG22 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_MG22 (_SYSCFG_CHIPREV_FAMILY_MG22 << 6) /**< Shifted mode MG22 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_BG22 (_SYSCFG_CHIPREV_FAMILY_BG22 << 6) /**< Shifted mode BG22 for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_FAMILY_FG22 (_SYSCFG_CHIPREV_FAMILY_FG22 << 6) /**< Shifted mode FG22 for SYSCFG_CHIPREV */ -#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ -#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ -#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ - -/* Bit fields for SYSCFG CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ -#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ -#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ -#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ - -/* Bit fields for SYSCFG CTRL */ -#define _SYSCFG_CTRL_RESETVALUE 0x00000021UL /**< Default value for SYSCFG_CTRL */ -#define _SYSCFG_CTRL_MASK 0x00000021UL /**< Mask for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ -#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ -#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC Error Bus Fault Response Enable */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ -#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ -#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ - -/* Bit fields for SYSCFG DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_DMEM0RETNCTRL */ -#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_DMEM0RETNCTRL */ -#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_DMEM0RETNCTRL */ - -/* Bit fields for SYSCFG DMEM0ECCADDR */ -#define _SYSCFG_DMEM0ECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCADDR */ -#define _SYSCFG_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0ECCADDR */ -#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_SHIFT 0 /**< Shift value for SYSCFG_DMEM0ECCADDR */ -#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DMEM0ECCADDR */ -#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCADDR */ -#define SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT (_SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCADDR*/ - -/* Bit fields for SYSCFG DMEM0ECCCTRL */ -#define _SYSCFG_DMEM0ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCCTRL */ -#define _SYSCFG_DMEM0ECCCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0ECCCTRL */ -#define SYSCFG_DMEM0ECCCTRL_RAMECCEN (0x1UL << 0) /**< RAM ECC Enable */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_RAMECCEN */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMECCEN */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ -#define SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ -#define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN (0x1UL << 1) /**< RAM ECC Error Writeback Enable */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_RAMECCEWEN */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMECCEWEN */ -#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ -#define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ - -/* Bit fields for SYSCFG RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ -#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ -#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ - -/* Bit fields for SYSCFG RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ -#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ -#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ -#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ - -/* Bit fields for SYSCFG SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ -#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ -#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ - -/* Bit fields for SYSCFG FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ -#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ -#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ - -/* Bit fields for SYSCFG ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ -#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ -#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ - -/* Bit fields for SYSCFG ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ -#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ -#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ - -/* Bit fields for SYSCFG ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x011F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ -#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x011F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ -#define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK (0x1UL << 24) /**< Radio Debug Lock */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_SHIFT 24 /**< Shift value for SYSCFG_RADIODBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_MASK 0x1000000UL /**< Bit mask for SYSCFG_RADIODBGLOCK */ -#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ -#define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ - -/** @} End of group EFR32BG22_SYSCFG_BitFields */ -/** @} End of group EFR32BG22_SYSCFG */ -/**************************************************************************//** - * @defgroup EFR32BG22_SYSCFG_CFGNS SYSCFG_CFGNS - * @{ - * @brief EFR32BG22 SYSCFG_CFGNS Register Declaration. - *****************************************************************************/ - -/** SYSCFG_CFGNS Register Declaration. */ -typedef struct { - uint32_t RESERVED0[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ - uint32_t RESERVED1[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ - uint32_t RESERVED2[638U]; /**< Reserved for future use */ - uint32_t RESERVED3[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ - uint32_t RESERVED4[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ - uint32_t RESERVED5[638U]; /**< Reserved for future use */ - uint32_t RESERVED6[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ - uint32_t RESERVED7[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ - uint32_t RESERVED8[638U]; /**< Reserved for future use */ - uint32_t RESERVED9[7U]; /**< Reserved for future use */ - __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ - uint32_t RESERVED10[376U]; /**< Reserved for future use */ - __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ - __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ -} SYSCFG_CFGNS_TypeDef; -/** @} End of group EFR32BG22_SYSCFG_CFGNS */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_SYSCFG_CFGNS - * @{ - * @defgroup EFR32BG22_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for SYSCFG CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ -#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ -#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ -#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ -#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ -#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ -#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ -#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ -#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ -#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ -#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ - -/* Bit fields for SYSCFG ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ -#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ -#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ - -/* Bit fields for SYSCFG ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ -#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ -#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ -#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ - -/** @} End of group EFR32BG22_SYSCFG_CFGNS_BitFields */ -/** @} End of group EFR32BG22_SYSCFG_CFGNS */ -/** @} End of group Parts */ - -#endif // EFR32BG22_SYSCFG_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 SYSCFG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_SYSCFG_H +#define EFR32BG22_SYSCFG_H +#define SYSCFG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_SYSCFG SYSCFG + * @{ + * @brief EFR32BG22 SYSCFG Register Declaration. + *****************************************************************************/ + +/** SYSCFG Register Declaration. */ +typedef struct { + __IOM uint32_t IF; /**< Interrupt Flag */ + __IOM uint32_t IEN; /**< Interrupt Enable */ + uint32_t RESERVED0[2U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV; /**< Part Family and Revision Values */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ + uint32_t RESERVED2[55U]; /**< Reserved for future use */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + uint32_t RESERVED4[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL; /**< Memory System Control */ + uint32_t RESERVED5[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL; /**< DMEM0 Retention Control */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t DMEM0ECCADDR; /**< DMEM0 ECC Address */ + __IOM uint32_t DMEM0ECCCTRL; /**< DMEM0 ECC Control */ + uint32_t RESERVED7[122U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Address */ + uint32_t RESERVED10[122U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0; /**< Root Data Register 0 */ + __IOM uint32_t ROOTDATA1; /**< Root Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS; /**< Lock Status */ + uint32_t RESERVED11[637U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable */ + uint32_t RESERVED12[2U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_SET; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision Values */ + uint32_t RESERVED13[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ + uint32_t RESERVED14[55U]; /**< Reserved for future use */ + uint32_t RESERVED15[1U]; /**< Reserved for future use */ + uint32_t RESERVED16[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_SET; /**< Memory System Control */ + uint32_t RESERVED17[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM0 Retention Control */ + uint32_t RESERVED18[1U]; /**< Reserved for future use */ + __IM uint32_t DMEM0ECCADDR_SET; /**< DMEM0 ECC Address */ + __IOM uint32_t DMEM0ECCCTRL_SET; /**< DMEM0 ECC Control */ + uint32_t RESERVED19[122U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED20[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED21[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Address */ + uint32_t RESERVED22[122U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_SET; /**< Root Data Register 0 */ + __IOM uint32_t ROOTDATA1_SET; /**< Root Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_SET; /**< Lock Status */ + uint32_t RESERVED23[637U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ + uint32_t RESERVED24[2U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_CLR; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision Values */ + uint32_t RESERVED25[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ + uint32_t RESERVED26[55U]; /**< Reserved for future use */ + uint32_t RESERVED27[1U]; /**< Reserved for future use */ + uint32_t RESERVED28[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_CLR; /**< Memory System Control */ + uint32_t RESERVED29[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM0 Retention Control */ + uint32_t RESERVED30[1U]; /**< Reserved for future use */ + __IM uint32_t DMEM0ECCADDR_CLR; /**< DMEM0 ECC Address */ + __IOM uint32_t DMEM0ECCCTRL_CLR; /**< DMEM0 ECC Control */ + uint32_t RESERVED31[122U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED32[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED33[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Address */ + uint32_t RESERVED34[122U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_CLR; /**< Root Data Register 0 */ + __IOM uint32_t ROOTDATA1_CLR; /**< Root Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_CLR; /**< Lock Status */ + uint32_t RESERVED35[637U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ + uint32_t RESERVED36[2U]; /**< Reserved for future use */ + __IOM uint32_t CHIPREVHW_TGL; /**< Chip Revision, Hard-wired */ + __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision Values */ + uint32_t RESERVED37[2U]; /**< Reserved for future use */ + __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ + uint32_t RESERVED38[55U]; /**< Reserved for future use */ + uint32_t RESERVED39[1U]; /**< Reserved for future use */ + uint32_t RESERVED40[63U]; /**< Reserved for future use */ + __IOM uint32_t CTRL_TGL; /**< Memory System Control */ + uint32_t RESERVED41[1U]; /**< Reserved for future use */ + __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM0 Retention Control */ + uint32_t RESERVED42[1U]; /**< Reserved for future use */ + __IM uint32_t DMEM0ECCADDR_TGL; /**< DMEM0 ECC Address */ + __IOM uint32_t DMEM0ECCCTRL_TGL; /**< DMEM0 ECC Control */ + uint32_t RESERVED43[122U]; /**< Reserved for future use */ + __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */ + uint32_t RESERVED44[1U]; /**< Reserved for future use */ + __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ + uint32_t RESERVED45[1U]; /**< Reserved for future use */ + __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Address */ + __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Address */ + uint32_t RESERVED46[122U]; /**< Reserved for future use */ + __IOM uint32_t ROOTDATA0_TGL; /**< Root Data Register 0 */ + __IOM uint32_t ROOTDATA1_TGL; /**< Root Data Register 1 */ + __IM uint32_t ROOTLOCKSTATUS_TGL; /**< Lock Status */ +} SYSCFG_TypeDef; +/** @} End of group EFR32BG22_SYSCFG */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_SYSCFG + * @{ + * @defgroup EFR32BG22_SYSCFG_BitFields SYSCFG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG IF */ +#define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ +#define _SYSCFG_IF_MASK 0x3303000FUL /**< Mask for SYSCFG_IF */ +#define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt 0 */ +#define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt 1 */ +#define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt 2 */ +#define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt 3 */ +#define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ +#define _SYSCFG_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ +#define _SYSCFG_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_RAMERR1B_DEFAULT (_SYSCFG_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ +#define _SYSCFG_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ +#define _SYSCFG_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_RAMERR2B_DEFAULT (_SYSCFG_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IF_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR1B_DEFAULT (_SYSCFG_IF_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-Bit Error Interrupt Flag */ +#define _SYSCFG_IF_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IF_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ +#define SYSCFG_IF_FRCRAMERR2B_DEFAULT (_SYSCFG_IF_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ + +/* Bit fields for SYSCFG IEN */ +#define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ +#define _SYSCFG_IEN_MASK 0x3303000FUL /**< Mask for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software interrupt 0 */ +#define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ +#define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software interrupt 1 */ +#define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ +#define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software interrupt 2 */ +#define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ +#define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software interrupt 3 */ +#define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ +#define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_RAMERR1B (0x1UL << 16) /**< RAM 1-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ +#define _SYSCFG_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ +#define _SYSCFG_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_RAMERR1B_DEFAULT (_SYSCFG_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_RAMERR2B (0x1UL << 17) /**< RAM 2-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ +#define _SYSCFG_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ +#define _SYSCFG_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_RAMERR2B_DEFAULT (_SYSCFG_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ +#define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ +#define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B (0x1UL << 28) /**< FRCRAM 1-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR1B_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1B */ +#define _SYSCFG_IEN_FRCRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR1B_DEFAULT (_SYSCFG_IEN_FRCRAMERR1B_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B (0x1UL << 29) /**< FRCRAM 2-bit Error Interrupt Enable */ +#define _SYSCFG_IEN_FRCRAMERR2B_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2B */ +#define _SYSCFG_IEN_FRCRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ +#define SYSCFG_IEN_FRCRAMERR2B_DEFAULT (_SYSCFG_IEN_FRCRAMERR2B_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ + +/* Bit fields for SYSCFG CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000D02UL /**< Default value for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000002UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000034UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ +#define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ +#define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ + +/* Bit fields for SYSCFG CHIPREV */ +#define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ +#define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ +#define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_PG22 0x00000018UL /**< Mode PG22 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_MG22 0x00000034UL /**< Mode MG22 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_BG22 0x00000035UL /**< Mode BG22 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_FAMILY_FG22 0x00000037UL /**< Mode FG22 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_PG22 (_SYSCFG_CHIPREV_FAMILY_PG22 << 6) /**< Shifted mode PG22 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_MG22 (_SYSCFG_CHIPREV_FAMILY_MG22 << 6) /**< Shifted mode MG22 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_BG22 (_SYSCFG_CHIPREV_FAMILY_BG22 << 6) /**< Shifted mode BG22 for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_FAMILY_FG22 (_SYSCFG_CHIPREV_FAMILY_FG22 << 6) /**< Shifted mode FG22 for SYSCFG_CHIPREV */ +#define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ +#define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ +#define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ + +/* Bit fields for SYSCFG CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ +#define _SYSCFG_CFGSYSTIC_MASK 0x00000001UL /**< Mask for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ +#define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ +#define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ + +/* Bit fields for SYSCFG CTRL */ +#define _SYSCFG_CTRL_RESETVALUE 0x00000021UL /**< Default value for SYSCFG_CTRL */ +#define _SYSCFG_CTRL_MASK 0x00000021UL /**< Mask for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ +#define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ +#define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC Error Bus Fault Response Enable */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ +#define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ +#define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ + +/* Bit fields for SYSCFG DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_RAMRETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_DMEM0RETNCTRL */ +#define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_DMEM0RETNCTRL */ +#define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_DMEM0RETNCTRL */ + +/* Bit fields for SYSCFG DMEM0ECCADDR */ +#define _SYSCFG_DMEM0ECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCADDR */ +#define _SYSCFG_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0ECCADDR */ +#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_SHIFT 0 /**< Shift value for SYSCFG_DMEM0ECCADDR */ +#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DMEM0ECCADDR */ +#define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCADDR */ +#define SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT (_SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCADDR*/ + +/* Bit fields for SYSCFG DMEM0ECCCTRL */ +#define _SYSCFG_DMEM0ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCCTRL */ +#define _SYSCFG_DMEM0ECCCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0ECCCTRL */ +#define SYSCFG_DMEM0ECCCTRL_RAMECCEN (0x1UL << 0) /**< RAM ECC Enable */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_RAMECCEN */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMECCEN */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ +#define SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ +#define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN (0x1UL << 1) /**< RAM ECC Error Writeback Enable */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_RAMECCEWEN */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMECCEWEN */ +#define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ +#define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ + +/* Bit fields for SYSCFG RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000103UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x3UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 0x00000001UL /**< Mode BLK0 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 0x00000002UL /**< Mode BLK1 for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF 0x00000003UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK0 << 0) /**< Shifted mode BLK0 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_BLK1 << 0) /**< Shifted mode BLK1 for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLOFF << 0) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Retention Control */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ +#define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF 0x00000001UL /**< Mode ALLOFF for SYSCFG_RADIORAMRETNCTRL */ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ +#define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLOFF << 8) /**< Shifted mode ALLOFF for SYSCFG_RADIORAMRETNCTRL*/ + +/* Bit fields for SYSCFG RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ +#define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN (0x1UL << 0) /**< SEQRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 1) /**< SEQRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN (0x1UL << 8) /**< FRCRAM ECC Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 9) /**< FRCRAM ECC Error Writeback Enable */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ +#define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ +#define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ + +/* Bit fields for SYSCFG SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ +#define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ +#define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ + +/* Bit fields for SYSCFG FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ +#define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ +#define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ + +/* Bit fields for SYSCFG ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA0 */ +#define _SYSCFG_ROOTDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA0 */ +#define SYSCFG_ROOTDATA0_DATA_DEFAULT (_SYSCFG_ROOTDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA0 */ + +/* Bit fields for SYSCFG ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTDATA1 */ +#define _SYSCFG_ROOTDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTDATA1 */ +#define SYSCFG_ROOTDATA1_DATA_DEFAULT (_SYSCFG_ROOTDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTDATA1 */ + +/* Bit fields for SYSCFG ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_RESETVALUE 0x011F0107UL /**< Default value for SYSCFG_ROOTLOCKSTATUS */ +#define _SYSCFG_ROOTLOCKSTATUS_MASK 0x011F0117UL /**< Mask for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK (0x1UL << 0) /**< Bus Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_SHIFT 0 /**< Shift value for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_MASK 0x1UL /**< Bit mask for SYSCFG_BUSLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_BUSLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK (0x1UL << 1) /**< Register Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_SHIFT 1 /**< Shift value for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_MASK 0x2UL /**< Bit mask for SYSCFG_REGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_REGLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK (0x1UL << 2) /**< Manufacture Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_SHIFT 2 /**< Shift value for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_MASK 0x4UL /**< Bit mask for SYSCFG_MFRLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_MFRLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK (0x1UL << 4) /**< Root Mode Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_SHIFT 4 /**< Shift value for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_MASK 0x10UL /**< Bit mask for SYSCFG_ROOTMODELOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTMODELOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK (0x1UL << 8) /**< Root Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_SHIFT 8 /**< Shift value for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_MASK 0x100UL /**< Bit mask for SYSCFG_ROOTDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_ROOTDBGLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK (0x1UL << 16) /**< User Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_SHIFT 16 /**< Shift value for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_MASK 0x10000UL /**< Bit mask for SYSCFG_USERDBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK (0x1UL << 17) /**< User Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_SHIFT 17 /**< Shift value for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_MASK 0x20000UL /**< Bit mask for SYSCFG_USERNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERNIDLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK (0x1UL << 18) /**< User Secure Invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_SHIFT 18 /**< Shift value for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_MASK 0x40000UL /**< Bit mask for SYSCFG_USERSPIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPIDLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK (0x1UL << 19) /**< User Secure Non-invasive Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_SHIFT 19 /**< Shift value for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_MASK 0x80000UL /**< Bit mask for SYSCFG_USERSPNIDLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERSPNIDLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK (0x1UL << 20) /**< User Debug Access Port Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_SHIFT 20 /**< Shift value for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_MASK 0x100000UL /**< Bit mask for SYSCFG_USERDBGAPLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_USERDBGAPLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ +#define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK (0x1UL << 24) /**< Radio Debug Lock */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_SHIFT 24 /**< Shift value for SYSCFG_RADIODBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_MASK 0x1000000UL /**< Bit mask for SYSCFG_RADIODBGLOCK */ +#define _SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_ROOTLOCKSTATUS */ +#define SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT (_SYSCFG_ROOTLOCKSTATUS_RADIODBGLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_ROOTLOCKSTATUS*/ + +/** @} End of group EFR32BG22_SYSCFG_BitFields */ +/** @} End of group EFR32BG22_SYSCFG */ +/**************************************************************************//** + * @defgroup EFR32BG22_SYSCFG_CFGNS SYSCFG_CFGNS + * @{ + * @brief EFR32BG22 SYSCFG_CFGNS Register Declaration. + *****************************************************************************/ + +/** SYSCFG_CFGNS Register Declaration. */ +typedef struct { + uint32_t RESERVED0[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED1[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1; /**< Data Register 1 */ + uint32_t RESERVED2[638U]; /**< Reserved for future use */ + uint32_t RESERVED3[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_SET; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED4[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_SET; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_SET; /**< Data Register 1 */ + uint32_t RESERVED5[638U]; /**< Reserved for future use */ + uint32_t RESERVED6[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_CLR; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED7[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_CLR; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_CLR; /**< Data Register 1 */ + uint32_t RESERVED8[638U]; /**< Reserved for future use */ + uint32_t RESERVED9[7U]; /**< Reserved for future use */ + __IOM uint32_t CFGNSTCALIB_TGL; /**< Configure Non-secure Sys-Tick Cal. */ + uint32_t RESERVED10[376U]; /**< Reserved for future use */ + __IOM uint32_t ROOTNSDATA0_TGL; /**< Data Register 0 */ + __IOM uint32_t ROOTNSDATA1_TGL; /**< Data Register 1 */ +} SYSCFG_CFGNS_TypeDef; +/** @} End of group EFR32BG22_SYSCFG_CFGNS */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_SYSCFG_CFGNS + * @{ + * @defgroup EFR32BG22_SYSCFG_CFGNS_BitFields SYSCFG_CFGNS Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for SYSCFG CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_RESETVALUE 0x01004A37UL /**< Default value for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_MASK 0x03FFFFFFUL /**< Mask for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_TENMS_SHIFT 0 /**< Shift value for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_MASK 0xFFFFFFUL /**< Bit mask for SYSCFG_TENMS */ +#define _SYSCFG_CFGNSTCALIB_TENMS_DEFAULT 0x00004A37UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_TENMS_DEFAULT (_SYSCFG_CFGNSTCALIB_TENMS_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW (0x1UL << 24) /**< Skew */ +#define _SYSCFG_CFGNSTCALIB_SKEW_SHIFT 24 /**< Shift value for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_MASK 0x1000000UL /**< Bit mask for SYSCFG_SKEW */ +#define _SYSCFG_CFGNSTCALIB_SKEW_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_SKEW_DEFAULT (_SYSCFG_CFGNSTCALIB_SKEW_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF (0x1UL << 25) /**< No Reference */ +#define _SYSCFG_CFGNSTCALIB_NOREF_SHIFT 25 /**< Shift value for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_MASK 0x2000000UL /**< Bit mask for SYSCFG_NOREF */ +#define _SYSCFG_CFGNSTCALIB_NOREF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_REF 0x00000000UL /**< Mode REF for SYSCFG_CFGNSTCALIB */ +#define _SYSCFG_CFGNSTCALIB_NOREF_NOREF 0x00000001UL /**< Mode NOREF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_DEFAULT (_SYSCFG_CFGNSTCALIB_NOREF_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_REF (_SYSCFG_CFGNSTCALIB_NOREF_REF << 25) /**< Shifted mode REF for SYSCFG_CFGNSTCALIB */ +#define SYSCFG_CFGNSTCALIB_NOREF_NOREF (_SYSCFG_CFGNSTCALIB_NOREF_NOREF << 25) /**< Shifted mode NOREF for SYSCFG_CFGNSTCALIB */ + +/* Bit fields for SYSCFG ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA0 */ +#define _SYSCFG_ROOTNSDATA0_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA0_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA0 */ +#define SYSCFG_ROOTNSDATA0_DATA_DEFAULT (_SYSCFG_ROOTNSDATA0_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA0 */ + +/* Bit fields for SYSCFG ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_ROOTNSDATA1 */ +#define _SYSCFG_ROOTNSDATA1_DATA_SHIFT 0 /**< Shift value for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DATA */ +#define _SYSCFG_ROOTNSDATA1_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_ROOTNSDATA1 */ +#define SYSCFG_ROOTNSDATA1_DATA_DEFAULT (_SYSCFG_ROOTNSDATA1_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_ROOTNSDATA1 */ + +/** @} End of group EFR32BG22_SYSCFG_CFGNS_BitFields */ +/** @} End of group EFR32BG22_SYSCFG_CFGNS */ +/** @} End of group Parts */ + +#endif // EFR32BG22_SYSCFG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h index 82631a7..905c801 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_timer.h @@ -1,1015 +1,1015 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 TIMER register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_TIMER_H -#define EFR32BG22_TIMER_H -#define TIMER_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_TIMER TIMER - * @{ - * @brief EFR32BG22 TIMER Register Declaration. - *****************************************************************************/ - -/** TIMER CC Register Group Declaration. */ -typedef struct { - __IOM uint32_t CFG; /**< CC Channel Configuration Register */ - __IOM uint32_t CTRL; /**< CC Channel Control Register */ - __IOM uint32_t OC; /**< OC Channel Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ - __IM uint32_t ICF; /**< IC Channel Value Register */ - __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ - uint32_t RESERVED1[1U]; /**< Reserved for future use */ -} TIMER_CC_TypeDef; - -/** TIMER Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version ID */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t TOP; /**< Counter Top Value Register */ - __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT; /**< Counter Value Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN; /**< module en */ - uint32_t RESERVED1[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED2[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ - uint32_t RESERVED3[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version ID */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_SET; /**< Counter Value Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_SET; /**< module en */ - uint32_t RESERVED5[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED6[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ - uint32_t RESERVED7[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version ID */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_CLR; /**< Counter Value Register */ - uint32_t RESERVED8[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_CLR; /**< module en */ - uint32_t RESERVED9[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED10[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ - uint32_t RESERVED11[960U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version ID */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ - __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ - __IOM uint32_t CNT_TGL; /**< Counter Value Register */ - uint32_t RESERVED12[1U]; /**< Reserved for future use */ - __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ - __IOM uint32_t EN_TGL; /**< module en */ - uint32_t RESERVED13[11U]; /**< Reserved for future use */ - TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ - uint32_t RESERVED14[8U]; /**< Reserved for future use */ - __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ - __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ - __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ - __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ - __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ - __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ - __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ - __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ -} TIMER_TypeDef; -/** @} End of group EFR32BG22_TIMER */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_TIMER - * @{ - * @defgroup EFR32BG22_TIMER_BitFields TIMER Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for TIMER IPVERSION */ -#define _TIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ -#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IPVERSION */ -#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ - -/* Bit fields for TIMER CFG */ -#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ -#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ -#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ -#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ -#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ -#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ -#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ -#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ -#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ -#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ -#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ -#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ -#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ -#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ -#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ -#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ -#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ -#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ -#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ -#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ -#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ -#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ -#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ -#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ -#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ -#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ -#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ -#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ -#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ -#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ -#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ -#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ -#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ -#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ -#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ -#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ -#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ -#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ -#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ -#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ -#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ -#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ -#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ -#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ -#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ -#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ - -/* Bit fields for TIMER CTRL */ -#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ -#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ -#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ -#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ -#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ -#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ -#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ -#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ -#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ - -/* Bit fields for TIMER CMD */ -#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ -#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ -#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ -#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ -#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ -#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ -#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ -#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ -#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ -#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ - -/* Bit fields for TIMER STATUS */ -#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ -#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ -#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ -#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ -#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ -#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ -#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ -#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ -#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ -#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ -#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ -#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ -#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ -#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ -#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ -#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ -#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ -#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ -#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ -#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ -#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ -#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ -#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ -#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ -#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ -#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ -#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ -#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ -#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ -#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ - -/* Bit fields for TIMER IF */ -#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ -#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ -#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ -#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ -#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ -#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ -#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ -#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ -#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ -#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ -#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ -#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ -#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ - -/* Bit fields for TIMER IEN */ -#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ -#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ -#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ -#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ -#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ -#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ -#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ -#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ -#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ -#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ -#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ -#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ -#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ -#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ -#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ -#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ -#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ -#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ -#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ -#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ -#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ -#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ -#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ -#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ -#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ -#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ -#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ -#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ -#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ -#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ -#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ -#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ -#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ -#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ -#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ -#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ -#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ - -/* Bit fields for TIMER TOP */ -#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ -#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ -#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ -#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ -#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ - -/* Bit fields for TIMER TOPB */ -#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ -#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ -#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ -#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ - -/* Bit fields for TIMER CNT */ -#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ -#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ -#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ -#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ -#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ - -/* Bit fields for TIMER LOCK */ -#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ -#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ -#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ -#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ -#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ - -/* Bit fields for TIMER EN */ -#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ -#define _TIMER_EN_MASK 0x00000001UL /**< Mask for TIMER_EN */ -#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ -#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ -#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ -#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ -#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ - -/* Bit fields for TIMER CC_CFG */ -#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ -#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ -#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ -#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ -#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ -#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ -#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ -#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ -#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ -#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ -#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ -#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ -#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ - -/* Bit fields for TIMER CC_CTRL */ -#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ -#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ -#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ -#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ -#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ -#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ -#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ -#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ -#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ -#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ - -/* Bit fields for TIMER CC_OC */ -#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ -#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ -#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ -#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ -#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ -#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ - -/* Bit fields for TIMER CC_OCB */ -#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ -#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ -#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ -#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ - -/* Bit fields for TIMER CC_ICF */ -#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ -#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ -#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ -#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ - -/* Bit fields for TIMER CC_ICOF */ -#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ -#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ -#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ -#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ - -/* Bit fields for TIMER DTCFG */ -#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ -#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ -#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ -#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ -#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ -#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ -#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ -#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ -#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ -#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ -#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ -#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ -#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ -#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ - -/* Bit fields for TIMER DTTIMECFG */ -#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ -#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ -#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ -#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ -#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ -#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ - -/* Bit fields for TIMER DTFCFG */ -#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ -#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ -#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ -#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ -#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ -#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ -#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ -#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ -#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ -#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ -#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ -#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ - -/* Bit fields for TIMER DTCTRL */ -#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ -#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ -#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ -#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ -#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ -#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ - -/* Bit fields for TIMER DTOGEN */ -#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ -#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ -#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ -#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ -#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ -#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ -#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ -#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ -#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ - -/* Bit fields for TIMER DTFAULT */ -#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ -#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ -#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ -#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ -#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ -#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ -#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ -#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ -#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ -#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ -#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ -#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ -#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ - -/* Bit fields for TIMER DTFAULTC */ -#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ -#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ -#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ -#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ -#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ -#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ -#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ -#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ -#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ -#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ -#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ - -/* Bit fields for TIMER DTLOCK */ -#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ -#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ -#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ -#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ - -/** @} End of group EFR32BG22_TIMER_BitFields */ -/** @} End of group EFR32BG22_TIMER */ -/** @} End of group Parts */ - -#endif // EFR32BG22_TIMER_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 TIMER register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_TIMER_H +#define EFR32BG22_TIMER_H +#define TIMER_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_TIMER TIMER + * @{ + * @brief EFR32BG22 TIMER Register Declaration. + *****************************************************************************/ + +/** TIMER CC Register Group Declaration. */ +typedef struct { + __IOM uint32_t CFG; /**< CC Channel Configuration Register */ + __IOM uint32_t CTRL; /**< CC Channel Control Register */ + __IOM uint32_t OC; /**< OC Channel Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t OCB; /**< OC Channel Value Buffer Register */ + __IM uint32_t ICF; /**< IC Channel Value Register */ + __IM uint32_t ICOF; /**< IC Channel Value Overflow Register */ + uint32_t RESERVED1[1U]; /**< Reserved for future use */ +} TIMER_CC_TypeDef; + +/** TIMER Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version ID */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t TOP; /**< Counter Top Value Register */ + __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT; /**< Counter Value Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN; /**< module en */ + uint32_t RESERVED1[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED2[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK; /**< DTI Configuration Lock Register */ + uint32_t RESERVED3[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version ID */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_SET; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_SET; /**< Counter Value Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_SET; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_SET; /**< module en */ + uint32_t RESERVED5[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_SET[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED6[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_SET; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_SET; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_SET; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_SET; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_SET; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_SET; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_SET; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_SET; /**< DTI Configuration Lock Register */ + uint32_t RESERVED7[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version ID */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_CLR; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_CLR; /**< Counter Value Register */ + uint32_t RESERVED8[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_CLR; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_CLR; /**< module en */ + uint32_t RESERVED9[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_CLR[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED10[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_CLR; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_CLR; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_CLR; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_CLR; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_CLR; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_CLR; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_CLR; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_CLR; /**< DTI Configuration Lock Register */ + uint32_t RESERVED11[960U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version ID */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t TOP_TGL; /**< Counter Top Value Register */ + __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ + __IOM uint32_t CNT_TGL; /**< Counter Value Register */ + uint32_t RESERVED12[1U]; /**< Reserved for future use */ + __IOM uint32_t LOCK_TGL; /**< TIMER Configuration Lock Register */ + __IOM uint32_t EN_TGL; /**< module en */ + uint32_t RESERVED13[11U]; /**< Reserved for future use */ + TIMER_CC_TypeDef CC_TGL[3U]; /**< Compare/Capture Channel */ + uint32_t RESERVED14[8U]; /**< Reserved for future use */ + __IOM uint32_t DTCFG_TGL; /**< DTI Configuration Register */ + __IOM uint32_t DTTIMECFG_TGL; /**< DTI Time Configuration Register */ + __IOM uint32_t DTFCFG_TGL; /**< DTI Fault Configuration Register */ + __IOM uint32_t DTCTRL_TGL; /**< DTI Control Register */ + __IOM uint32_t DTOGEN_TGL; /**< DTI Output Generation Enable Register */ + __IM uint32_t DTFAULT_TGL; /**< DTI Fault Register */ + __IOM uint32_t DTFAULTC_TGL; /**< DTI Fault Clear Register */ + __IOM uint32_t DTLOCK_TGL; /**< DTI Configuration Lock Register */ +} TIMER_TypeDef; +/** @} End of group EFR32BG22_TIMER */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_TIMER + * @{ + * @defgroup EFR32BG22_TIMER_BitFields TIMER Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for TIMER IPVERSION */ +#define _TIMER_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_IPVERSION */ +#define _TIMER_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IPVERSION */ +#define TIMER_IPVERSION_IPVERSION_DEFAULT (_TIMER_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IPVERSION */ + +/* Bit fields for TIMER CFG */ +#define _TIMER_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CFG */ +#define _TIMER_CFG_MASK 0x0FFF1FFBUL /**< Mask for TIMER_CFG */ +#define _TIMER_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_MODE_UP 0x00000000UL /**< Mode UP for TIMER_CFG */ +#define _TIMER_CFG_MODE_DOWN 0x00000001UL /**< Mode DOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_UPDOWN 0x00000002UL /**< Mode UPDOWN for TIMER_CFG */ +#define _TIMER_CFG_MODE_QDEC 0x00000003UL /**< Mode QDEC for TIMER_CFG */ +#define TIMER_CFG_MODE_DEFAULT (_TIMER_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_MODE_UP (_TIMER_CFG_MODE_UP << 0) /**< Shifted mode UP for TIMER_CFG */ +#define TIMER_CFG_MODE_DOWN (_TIMER_CFG_MODE_DOWN << 0) /**< Shifted mode DOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_UPDOWN (_TIMER_CFG_MODE_UPDOWN << 0) /**< Shifted mode UPDOWN for TIMER_CFG */ +#define TIMER_CFG_MODE_QDEC (_TIMER_CFG_MODE_QDEC << 0) /**< Shifted mode QDEC for TIMER_CFG */ +#define TIMER_CFG_SYNC (0x1UL << 3) /**< Timer Start/Stop/Reload Synchronization */ +#define _TIMER_CFG_SYNC_SHIFT 3 /**< Shift value for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_MASK 0x8UL /**< Bit mask for TIMER_SYNC */ +#define _TIMER_CFG_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_DEFAULT (_TIMER_CFG_SYNC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_SYNC_DISABLE (_TIMER_CFG_SYNC_DISABLE << 3) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_SYNC_ENABLE (_TIMER_CFG_SYNC_ENABLE << 3) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_OSMEN (0x1UL << 4) /**< One-shot Mode Enable */ +#define _TIMER_CFG_OSMEN_SHIFT 4 /**< Shift value for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_MASK 0x10UL /**< Bit mask for TIMER_OSMEN */ +#define _TIMER_CFG_OSMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_OSMEN_DEFAULT (_TIMER_CFG_OSMEN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM (0x1UL << 5) /**< Quadrature Decoder Mode Selection */ +#define _TIMER_CFG_QDM_SHIFT 5 /**< Shift value for TIMER_QDM */ +#define _TIMER_CFG_QDM_MASK 0x20UL /**< Bit mask for TIMER_QDM */ +#define _TIMER_CFG_QDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_QDM_X2 0x00000000UL /**< Mode X2 for TIMER_CFG */ +#define _TIMER_CFG_QDM_X4 0x00000001UL /**< Mode X4 for TIMER_CFG */ +#define TIMER_CFG_QDM_DEFAULT (_TIMER_CFG_QDM_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_QDM_X2 (_TIMER_CFG_QDM_X2 << 5) /**< Shifted mode X2 for TIMER_CFG */ +#define TIMER_CFG_QDM_X4 (_TIMER_CFG_QDM_X4 << 5) /**< Shifted mode X4 for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN (0x1UL << 6) /**< Debug Mode Run Enable */ +#define _TIMER_CFG_DEBUGRUN_SHIFT 6 /**< Shift value for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_MASK 0x40UL /**< Bit mask for TIMER_DEBUGRUN */ +#define _TIMER_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_HALT 0x00000000UL /**< Mode HALT for TIMER_CFG */ +#define _TIMER_CFG_DEBUGRUN_RUN 0x00000001UL /**< Mode RUN for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_DEFAULT (_TIMER_CFG_DEBUGRUN_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_HALT (_TIMER_CFG_DEBUGRUN_HALT << 6) /**< Shifted mode HALT for TIMER_CFG */ +#define TIMER_CFG_DEBUGRUN_RUN (_TIMER_CFG_DEBUGRUN_RUN << 6) /**< Shifted mode RUN for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT (0x1UL << 7) /**< DMA Request Clear on Active */ +#define _TIMER_CFG_DMACLRACT_SHIFT 7 /**< Shift value for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_MASK 0x80UL /**< Bit mask for TIMER_DMACLRACT */ +#define _TIMER_CFG_DMACLRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DMACLRACT_DEFAULT (_TIMER_CFG_DMACLRACT_DEFAULT << 7) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_SHIFT 8 /**< Shift value for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_MASK 0x300UL /**< Bit mask for TIMER_CLKSEL */ +#define _TIMER_CFG_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK 0x00000000UL /**< Mode PRESCEM01GRPACLK for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_CC1 0x00000001UL /**< Mode CC1 for TIMER_CFG */ +#define _TIMER_CFG_CLKSEL_TIMEROUF 0x00000002UL /**< Mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_DEFAULT (_TIMER_CFG_CLKSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_PRESCEM01GRPACLK (_TIMER_CFG_CLKSEL_PRESCEM01GRPACLK << 8) /**< Shifted mode PRESCEM01GRPACLK for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_CC1 (_TIMER_CFG_CLKSEL_CC1 << 8) /**< Shifted mode CC1 for TIMER_CFG */ +#define TIMER_CFG_CLKSEL_TIMEROUF (_TIMER_CFG_CLKSEL_TIMEROUF << 8) /**< Shifted mode TIMEROUF for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN (0x1UL << 10) /**< PWM output retimed enable */ +#define _TIMER_CFG_RETIMEEN_SHIFT 10 /**< Shift value for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_MASK 0x400UL /**< Bit mask for TIMER_RETIMEEN */ +#define _TIMER_CFG_RETIMEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CFG */ +#define _TIMER_CFG_RETIMEEN_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DEFAULT (_TIMER_CFG_RETIMEEN_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_DISABLE (_TIMER_CFG_RETIMEEN_DISABLE << 10) /**< Shifted mode DISABLE for TIMER_CFG */ +#define TIMER_CFG_RETIMEEN_ENABLE (_TIMER_CFG_RETIMEEN_ENABLE << 10) /**< Shifted mode ENABLE for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT (0x1UL << 11) /**< Disable Timer Start/Stop/Reload output */ +#define _TIMER_CFG_DISSYNCOUT_SHIFT 11 /**< Shift value for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_MASK 0x800UL /**< Bit mask for TIMER_DISSYNCOUT */ +#define _TIMER_CFG_DISSYNCOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_EN 0x00000000UL /**< Mode EN for TIMER_CFG */ +#define _TIMER_CFG_DISSYNCOUT_DIS 0x00000001UL /**< Mode DIS for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DEFAULT (_TIMER_CFG_DISSYNCOUT_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_EN (_TIMER_CFG_DISSYNCOUT_EN << 11) /**< Shifted mode EN for TIMER_CFG */ +#define TIMER_CFG_DISSYNCOUT_DIS (_TIMER_CFG_DISSYNCOUT_DIS << 11) /**< Shifted mode DIS for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL (0x1UL << 12) /**< PWM output retime select */ +#define _TIMER_CFG_RETIMESEL_SHIFT 12 /**< Shift value for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_MASK 0x1000UL /**< Bit mask for TIMER_RETIMESEL */ +#define _TIMER_CFG_RETIMESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RETIMESEL_DEFAULT (_TIMER_CFG_RETIMESEL_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI (0x1UL << 16) /**< Always Track Inputs */ +#define _TIMER_CFG_ATI_SHIFT 16 /**< Shift value for TIMER_ATI */ +#define _TIMER_CFG_ATI_MASK 0x10000UL /**< Bit mask for TIMER_ATI */ +#define _TIMER_CFG_ATI_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_ATI_DEFAULT (_TIMER_CFG_ATI_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST (0x1UL << 17) /**< Reload-Start Sets COIST */ +#define _TIMER_CFG_RSSCOIST_SHIFT 17 /**< Shift value for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_MASK 0x20000UL /**< Bit mask for TIMER_RSSCOIST */ +#define _TIMER_CFG_RSSCOIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_RSSCOIST_DEFAULT (_TIMER_CFG_RSSCOIST_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_SHIFT 18 /**< Shift value for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_MASK 0xFFC0000UL /**< Bit mask for TIMER_PRESC */ +#define _TIMER_CFG_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV8 0x00000007UL /**< Mode DIV8 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV16 0x0000000FUL /**< Mode DIV16 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV32 0x0000001FUL /**< Mode DIV32 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV64 0x0000003FUL /**< Mode DIV64 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV128 0x0000007FUL /**< Mode DIV128 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV256 0x000000FFUL /**< Mode DIV256 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV512 0x000001FFUL /**< Mode DIV512 for TIMER_CFG */ +#define _TIMER_CFG_PRESC_DIV1024 0x000003FFUL /**< Mode DIV1024 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DEFAULT (_TIMER_CFG_PRESC_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1 (_TIMER_CFG_PRESC_DIV1 << 18) /**< Shifted mode DIV1 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV2 (_TIMER_CFG_PRESC_DIV2 << 18) /**< Shifted mode DIV2 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV4 (_TIMER_CFG_PRESC_DIV4 << 18) /**< Shifted mode DIV4 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV8 (_TIMER_CFG_PRESC_DIV8 << 18) /**< Shifted mode DIV8 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV16 (_TIMER_CFG_PRESC_DIV16 << 18) /**< Shifted mode DIV16 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV32 (_TIMER_CFG_PRESC_DIV32 << 18) /**< Shifted mode DIV32 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV64 (_TIMER_CFG_PRESC_DIV64 << 18) /**< Shifted mode DIV64 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV128 (_TIMER_CFG_PRESC_DIV128 << 18) /**< Shifted mode DIV128 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV256 (_TIMER_CFG_PRESC_DIV256 << 18) /**< Shifted mode DIV256 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV512 (_TIMER_CFG_PRESC_DIV512 << 18) /**< Shifted mode DIV512 for TIMER_CFG */ +#define TIMER_CFG_PRESC_DIV1024 (_TIMER_CFG_PRESC_DIV1024 << 18) /**< Shifted mode DIV1024 for TIMER_CFG */ + +/* Bit fields for TIMER CTRL */ +#define _TIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CTRL */ +#define _TIMER_CTRL_MASK 0x0000001FUL /**< Mask for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_SHIFT 0 /**< Shift value for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_MASK 0x3UL /**< Bit mask for TIMER_RISEA */ +#define _TIMER_CTRL_RISEA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_RISEA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_DEFAULT (_TIMER_CTRL_RISEA_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_NONE (_TIMER_CTRL_RISEA_NONE << 0) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_START (_TIMER_CTRL_RISEA_START << 0) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_STOP (_TIMER_CTRL_RISEA_STOP << 0) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_RISEA_RELOADSTART (_TIMER_CTRL_RISEA_RELOADSTART << 0) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_SHIFT 2 /**< Shift value for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_MASK 0xCUL /**< Bit mask for TIMER_FALLA */ +#define _TIMER_CTRL_FALLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_NONE 0x00000000UL /**< Mode NONE for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_START 0x00000001UL /**< Mode START for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_STOP 0x00000002UL /**< Mode STOP for TIMER_CTRL */ +#define _TIMER_CTRL_FALLA_RELOADSTART 0x00000003UL /**< Mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_DEFAULT (_TIMER_CTRL_FALLA_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_NONE (_TIMER_CTRL_FALLA_NONE << 2) /**< Shifted mode NONE for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_START (_TIMER_CTRL_FALLA_START << 2) /**< Shifted mode START for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_STOP (_TIMER_CTRL_FALLA_STOP << 2) /**< Shifted mode STOP for TIMER_CTRL */ +#define TIMER_CTRL_FALLA_RELOADSTART (_TIMER_CTRL_FALLA_RELOADSTART << 2) /**< Shifted mode RELOADSTART for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT (0x1UL << 4) /**< 2x Count Mode */ +#define _TIMER_CTRL_X2CNT_SHIFT 4 /**< Shift value for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_MASK 0x10UL /**< Bit mask for TIMER_X2CNT */ +#define _TIMER_CTRL_X2CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CTRL */ +#define TIMER_CTRL_X2CNT_DEFAULT (_TIMER_CTRL_X2CNT_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CTRL */ + +/* Bit fields for TIMER CMD */ +#define _TIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for TIMER_CMD */ +#define _TIMER_CMD_MASK 0x00000003UL /**< Mask for TIMER_CMD */ +#define TIMER_CMD_START (0x1UL << 0) /**< Start Timer */ +#define _TIMER_CMD_START_SHIFT 0 /**< Shift value for TIMER_START */ +#define _TIMER_CMD_START_MASK 0x1UL /**< Bit mask for TIMER_START */ +#define _TIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_START_DEFAULT (_TIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP (0x1UL << 1) /**< Stop Timer */ +#define _TIMER_CMD_STOP_SHIFT 1 /**< Shift value for TIMER_STOP */ +#define _TIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for TIMER_STOP */ +#define _TIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CMD */ +#define TIMER_CMD_STOP_DEFAULT (_TIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_CMD */ + +/* Bit fields for TIMER STATUS */ +#define _TIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for TIMER_STATUS */ +#define _TIMER_STATUS_MASK 0x07070777UL /**< Mask for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING (0x1UL << 0) /**< Running */ +#define _TIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for TIMER_RUNNING */ +#define _TIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_RUNNING_DEFAULT (_TIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR (0x1UL << 1) /**< Direction */ +#define _TIMER_STATUS_DIR_SHIFT 1 /**< Shift value for TIMER_DIR */ +#define _TIMER_STATUS_DIR_MASK 0x2UL /**< Bit mask for TIMER_DIR */ +#define _TIMER_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_UP 0x00000000UL /**< Mode UP for TIMER_STATUS */ +#define _TIMER_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DEFAULT (_TIMER_STATUS_DIR_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DIR_UP (_TIMER_STATUS_DIR_UP << 1) /**< Shifted mode UP for TIMER_STATUS */ +#define TIMER_STATUS_DIR_DOWN (_TIMER_STATUS_DIR_DOWN << 1) /**< Shifted mode DOWN for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV (0x1UL << 2) /**< TOP Buffer Valid */ +#define _TIMER_STATUS_TOPBV_SHIFT 2 /**< Shift value for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_MASK 0x4UL /**< Bit mask for TIMER_TOPBV */ +#define _TIMER_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TOPBV_DEFAULT (_TIMER_STATUS_TOPBV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS (0x1UL << 4) /**< Timer lock status */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_SHIFT 4 /**< Shift value for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_MASK 0x10UL /**< Bit mask for TIMER_TIMERLOCKSTATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_TIMERLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT (_TIMER_STATUS_TIMERLOCKSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_UNLOCKED << 4) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_TIMERLOCKSTATUS_LOCKED (_TIMER_STATUS_TIMERLOCKSTATUS_LOCKED << 4) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS (0x1UL << 5) /**< DTI lock status */ +#define _TIMER_STATUS_DTILOCKSTATUS_SHIFT 5 /**< Shift value for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_MASK 0x20UL /**< Bit mask for TIMER_DTILOCKSTATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for TIMER_STATUS */ +#define _TIMER_STATUS_DTILOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_DEFAULT (_TIMER_STATUS_DTILOCKSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_UNLOCKED (_TIMER_STATUS_DTILOCKSTATUS_UNLOCKED << 5) /**< Shifted mode UNLOCKED for TIMER_STATUS */ +#define TIMER_STATUS_DTILOCKSTATUS_LOCKED (_TIMER_STATUS_DTILOCKSTATUS_LOCKED << 5) /**< Shifted mode LOCKED for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY (0x1UL << 6) /**< Sync Busy */ +#define _TIMER_STATUS_SYNCBUSY_SHIFT 6 /**< Shift value for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_MASK 0x40UL /**< Bit mask for TIMER_SYNCBUSY */ +#define _TIMER_STATUS_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_SYNCBUSY_DEFAULT (_TIMER_STATUS_SYNCBUSY_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0 (0x1UL << 8) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV0_SHIFT 8 /**< Shift value for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_MASK 0x100UL /**< Bit mask for TIMER_OCBV0 */ +#define _TIMER_STATUS_OCBV0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV0_DEFAULT (_TIMER_STATUS_OCBV0_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1 (0x1UL << 9) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV1_SHIFT 9 /**< Shift value for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_MASK 0x200UL /**< Bit mask for TIMER_OCBV1 */ +#define _TIMER_STATUS_OCBV1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV1_DEFAULT (_TIMER_STATUS_OCBV1_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2 (0x1UL << 10) /**< Output Compare Buffer Valid */ +#define _TIMER_STATUS_OCBV2_SHIFT 10 /**< Shift value for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_MASK 0x400UL /**< Bit mask for TIMER_OCBV2 */ +#define _TIMER_STATUS_OCBV2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_OCBV2_DEFAULT (_TIMER_STATUS_OCBV2_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0 (0x1UL << 16) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY0_SHIFT 16 /**< Shift value for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_MASK 0x10000UL /**< Bit mask for TIMER_ICFEMPTY0 */ +#define _TIMER_STATUS_ICFEMPTY0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY0_DEFAULT (_TIMER_STATUS_ICFEMPTY0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1 (0x1UL << 17) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY1_SHIFT 17 /**< Shift value for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_MASK 0x20000UL /**< Bit mask for TIMER_ICFEMPTY1 */ +#define _TIMER_STATUS_ICFEMPTY1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY1_DEFAULT (_TIMER_STATUS_ICFEMPTY1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2 (0x1UL << 18) /**< Input capture fifo empty */ +#define _TIMER_STATUS_ICFEMPTY2_SHIFT 18 /**< Shift value for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_MASK 0x40000UL /**< Bit mask for TIMER_ICFEMPTY2 */ +#define _TIMER_STATUS_ICFEMPTY2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_ICFEMPTY2_DEFAULT (_TIMER_STATUS_ICFEMPTY2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0 (0x1UL << 24) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL0_SHIFT 24 /**< Shift value for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_MASK 0x1000000UL /**< Bit mask for TIMER_CCPOL0 */ +#define _TIMER_STATUS_CCPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL0_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_DEFAULT (_TIMER_STATUS_CCPOL0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_LOWRISE (_TIMER_STATUS_CCPOL0_LOWRISE << 24) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL0_HIGHFALL (_TIMER_STATUS_CCPOL0_HIGHFALL << 24) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1 (0x1UL << 25) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL1_SHIFT 25 /**< Shift value for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_MASK 0x2000000UL /**< Bit mask for TIMER_CCPOL1 */ +#define _TIMER_STATUS_CCPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL1_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_DEFAULT (_TIMER_STATUS_CCPOL1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_LOWRISE (_TIMER_STATUS_CCPOL1_LOWRISE << 25) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL1_HIGHFALL (_TIMER_STATUS_CCPOL1_HIGHFALL << 25) /**< Shifted mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2 (0x1UL << 26) /**< Compare/Capture Polarity */ +#define _TIMER_STATUS_CCPOL2_SHIFT 26 /**< Shift value for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_MASK 0x4000000UL /**< Bit mask for TIMER_CCPOL2 */ +#define _TIMER_STATUS_CCPOL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_LOWRISE 0x00000000UL /**< Mode LOWRISE for TIMER_STATUS */ +#define _TIMER_STATUS_CCPOL2_HIGHFALL 0x00000001UL /**< Mode HIGHFALL for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_DEFAULT (_TIMER_STATUS_CCPOL2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_LOWRISE (_TIMER_STATUS_CCPOL2_LOWRISE << 26) /**< Shifted mode LOWRISE for TIMER_STATUS */ +#define TIMER_STATUS_CCPOL2_HIGHFALL (_TIMER_STATUS_CCPOL2_HIGHFALL << 26) /**< Shifted mode HIGHFALL for TIMER_STATUS */ + +/* Bit fields for TIMER IF */ +#define _TIMER_IF_RESETVALUE 0x00000000UL /**< Default value for TIMER_IF */ +#define _TIMER_IF_MASK 0x07770077UL /**< Mask for TIMER_IF */ +#define TIMER_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ +#define _TIMER_IF_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IF_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_OF_DEFAULT (_TIMER_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF (0x1UL << 1) /**< Underflow Interrupt Flag */ +#define _TIMER_IF_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IF_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_UF_DEFAULT (_TIMER_IF_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ +#define _TIMER_IF_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IF_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_DIRCHG_DEFAULT (_TIMER_IF_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0 (0x1UL << 4) /**< Capture Compare Channel 0 Interrupt Flag */ +#define _TIMER_IF_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IF_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC0_DEFAULT (_TIMER_IF_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1 (0x1UL << 5) /**< Capture Compare Channel 1 Interrupt Flag */ +#define _TIMER_IF_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IF_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC1_DEFAULT (_TIMER_IF_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2 (0x1UL << 6) /**< Capture Compare Channel 2 Interrupt Flag */ +#define _TIMER_IF_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IF_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_CC2_DEFAULT (_TIMER_IF_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0 (0x1UL << 16) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IF_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL0_DEFAULT (_TIMER_IF_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1 (0x1UL << 17) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IF_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL1_DEFAULT (_TIMER_IF_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2 (0x1UL << 18) /**< Input Capture Watermark Level Full */ +#define _TIMER_IF_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IF_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFWLFULL2_DEFAULT (_TIMER_IF_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0 (0x1UL << 20) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IF_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF0_DEFAULT (_TIMER_IF_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1 (0x1UL << 21) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IF_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF1_DEFAULT (_TIMER_IF_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2 (0x1UL << 22) /**< Input Capture FIFO overflow */ +#define _TIMER_IF_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IF_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFOF2_DEFAULT (_TIMER_IF_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0 (0x1UL << 24) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IF_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF0_DEFAULT (_TIMER_IF_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1 (0x1UL << 25) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IF_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF1_DEFAULT (_TIMER_IF_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2 (0x1UL << 26) /**< Input capture FIFO underflow */ +#define _TIMER_IF_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IF_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IF */ +#define TIMER_IF_ICFUF2_DEFAULT (_TIMER_IF_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IF */ + +/* Bit fields for TIMER IEN */ +#define _TIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_IEN */ +#define _TIMER_IEN_MASK 0x07770077UL /**< Mask for TIMER_IEN */ +#define TIMER_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ +#define _TIMER_IEN_OF_SHIFT 0 /**< Shift value for TIMER_OF */ +#define _TIMER_IEN_OF_MASK 0x1UL /**< Bit mask for TIMER_OF */ +#define _TIMER_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_OF_DEFAULT (_TIMER_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF (0x1UL << 1) /**< Underflow Interrupt Enable */ +#define _TIMER_IEN_UF_SHIFT 1 /**< Shift value for TIMER_UF */ +#define _TIMER_IEN_UF_MASK 0x2UL /**< Bit mask for TIMER_UF */ +#define _TIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_UF_DEFAULT (_TIMER_IEN_UF_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ +#define _TIMER_IEN_DIRCHG_SHIFT 2 /**< Shift value for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_MASK 0x4UL /**< Bit mask for TIMER_DIRCHG */ +#define _TIMER_IEN_DIRCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_DIRCHG_DEFAULT (_TIMER_IEN_DIRCHG_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0 (0x1UL << 4) /**< CC0 Interrupt Enable */ +#define _TIMER_IEN_CC0_SHIFT 4 /**< Shift value for TIMER_CC0 */ +#define _TIMER_IEN_CC0_MASK 0x10UL /**< Bit mask for TIMER_CC0 */ +#define _TIMER_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC0_DEFAULT (_TIMER_IEN_CC0_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1 (0x1UL << 5) /**< CC1 Interrupt Enable */ +#define _TIMER_IEN_CC1_SHIFT 5 /**< Shift value for TIMER_CC1 */ +#define _TIMER_IEN_CC1_MASK 0x20UL /**< Bit mask for TIMER_CC1 */ +#define _TIMER_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC1_DEFAULT (_TIMER_IEN_CC1_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2 (0x1UL << 6) /**< CC2 Interrupt Enable */ +#define _TIMER_IEN_CC2_SHIFT 6 /**< Shift value for TIMER_CC2 */ +#define _TIMER_IEN_CC2_MASK 0x40UL /**< Bit mask for TIMER_CC2 */ +#define _TIMER_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_CC2_DEFAULT (_TIMER_IEN_CC2_DEFAULT << 6) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0 (0x1UL << 16) /**< ICFWLFULL0 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL0_SHIFT 16 /**< Shift value for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_MASK 0x10000UL /**< Bit mask for TIMER_ICFWLFULL0 */ +#define _TIMER_IEN_ICFWLFULL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL0_DEFAULT (_TIMER_IEN_ICFWLFULL0_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1 (0x1UL << 17) /**< ICFWLFULL1 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL1_SHIFT 17 /**< Shift value for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_MASK 0x20000UL /**< Bit mask for TIMER_ICFWLFULL1 */ +#define _TIMER_IEN_ICFWLFULL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL1_DEFAULT (_TIMER_IEN_ICFWLFULL1_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2 (0x1UL << 18) /**< ICFWLFULL2 Interrupt Enable */ +#define _TIMER_IEN_ICFWLFULL2_SHIFT 18 /**< Shift value for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_MASK 0x40000UL /**< Bit mask for TIMER_ICFWLFULL2 */ +#define _TIMER_IEN_ICFWLFULL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFWLFULL2_DEFAULT (_TIMER_IEN_ICFWLFULL2_DEFAULT << 18) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0 (0x1UL << 20) /**< ICFOF0 Interrupt Enable */ +#define _TIMER_IEN_ICFOF0_SHIFT 20 /**< Shift value for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_MASK 0x100000UL /**< Bit mask for TIMER_ICFOF0 */ +#define _TIMER_IEN_ICFOF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF0_DEFAULT (_TIMER_IEN_ICFOF0_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1 (0x1UL << 21) /**< ICFOF1 Interrupt Enable */ +#define _TIMER_IEN_ICFOF1_SHIFT 21 /**< Shift value for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_MASK 0x200000UL /**< Bit mask for TIMER_ICFOF1 */ +#define _TIMER_IEN_ICFOF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF1_DEFAULT (_TIMER_IEN_ICFOF1_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2 (0x1UL << 22) /**< ICFOF2 Interrupt Enable */ +#define _TIMER_IEN_ICFOF2_SHIFT 22 /**< Shift value for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_MASK 0x400000UL /**< Bit mask for TIMER_ICFOF2 */ +#define _TIMER_IEN_ICFOF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFOF2_DEFAULT (_TIMER_IEN_ICFOF2_DEFAULT << 22) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0 (0x1UL << 24) /**< ICFUF0 Interrupt Enable */ +#define _TIMER_IEN_ICFUF0_SHIFT 24 /**< Shift value for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_MASK 0x1000000UL /**< Bit mask for TIMER_ICFUF0 */ +#define _TIMER_IEN_ICFUF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF0_DEFAULT (_TIMER_IEN_ICFUF0_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1 (0x1UL << 25) /**< ICFUF1 Interrupt Enable */ +#define _TIMER_IEN_ICFUF1_SHIFT 25 /**< Shift value for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_MASK 0x2000000UL /**< Bit mask for TIMER_ICFUF1 */ +#define _TIMER_IEN_ICFUF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF1_DEFAULT (_TIMER_IEN_ICFUF1_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2 (0x1UL << 26) /**< ICFUF2 Interrupt Enable */ +#define _TIMER_IEN_ICFUF2_SHIFT 26 /**< Shift value for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_MASK 0x4000000UL /**< Bit mask for TIMER_ICFUF2 */ +#define _TIMER_IEN_ICFUF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_IEN */ +#define TIMER_IEN_ICFUF2_DEFAULT (_TIMER_IEN_ICFUF2_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_IEN */ + +/* Bit fields for TIMER TOP */ +#define _TIMER_TOP_RESETVALUE 0x0000FFFFUL /**< Default value for TIMER_TOP */ +#define _TIMER_TOP_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_SHIFT 0 /**< Shift value for TIMER_TOP */ +#define _TIMER_TOP_TOP_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOP */ +#define _TIMER_TOP_TOP_DEFAULT 0x0000FFFFUL /**< Mode DEFAULT for TIMER_TOP */ +#define TIMER_TOP_TOP_DEFAULT (_TIMER_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOP */ + +/* Bit fields for TIMER TOPB */ +#define _TIMER_TOPB_RESETVALUE 0x00000000UL /**< Default value for TIMER_TOPB */ +#define _TIMER_TOPB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_SHIFT 0 /**< Shift value for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_TOPB */ +#define _TIMER_TOPB_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_TOPB */ +#define TIMER_TOPB_TOPB_DEFAULT (_TIMER_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_TOPB */ + +/* Bit fields for TIMER CNT */ +#define _TIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for TIMER_CNT */ +#define _TIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_SHIFT 0 /**< Shift value for TIMER_CNT */ +#define _TIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_CNT */ +#define _TIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CNT */ +#define TIMER_CNT_CNT_DEFAULT (_TIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CNT */ + +/* Bit fields for TIMER LOCK */ +#define _TIMER_LOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_LOCK */ +#define _TIMER_LOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_LOCKKEY */ +#define _TIMER_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_LOCK */ +#define _TIMER_LOCK_LOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_DEFAULT (_TIMER_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_LOCK */ +#define TIMER_LOCK_LOCKKEY_UNLOCK (_TIMER_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_LOCK */ + +/* Bit fields for TIMER EN */ +#define _TIMER_EN_RESETVALUE 0x00000000UL /**< Default value for TIMER_EN */ +#define _TIMER_EN_MASK 0x00000001UL /**< Mask for TIMER_EN */ +#define TIMER_EN_EN (0x1UL << 0) /**< Timer Module Enable */ +#define _TIMER_EN_EN_SHIFT 0 /**< Shift value for TIMER_EN */ +#define _TIMER_EN_EN_MASK 0x1UL /**< Bit mask for TIMER_EN */ +#define _TIMER_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_EN */ +#define TIMER_EN_EN_DEFAULT (_TIMER_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_EN */ + +/* Bit fields for TIMER CC_CFG */ +#define _TIMER_CC_CFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MASK 0x003E0013UL /**< Mask for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_SHIFT 0 /**< Shift value for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_MASK 0x3UL /**< Bit mask for TIMER_MODE */ +#define _TIMER_CC_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OFF 0x00000000UL /**< Mode OFF for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_MODE_PWM 0x00000003UL /**< Mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_DEFAULT (_TIMER_CC_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OFF (_TIMER_CC_CFG_MODE_OFF << 0) /**< Shifted mode OFF for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_INPUTCAPTURE (_TIMER_CC_CFG_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_OUTPUTCOMPARE (_TIMER_CC_CFG_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_MODE_PWM (_TIMER_CC_CFG_MODE_PWM << 0) /**< Shifted mode PWM for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST (0x1UL << 4) /**< Compare Output Initial State */ +#define _TIMER_CC_CFG_COIST_SHIFT 4 /**< Shift value for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_MASK 0x10UL /**< Bit mask for TIMER_COIST */ +#define _TIMER_CC_CFG_COIST_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_COIST_DEFAULT (_TIMER_CC_CFG_COIST_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_SHIFT 17 /**< Shift value for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_MASK 0x60000UL /**< Bit mask for TIMER_INSEL */ +#define _TIMER_CC_CFG_INSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PIN 0x00000000UL /**< Mode PIN for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSSYNC 0x00000001UL /**< Mode PRSSYNC for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL 0x00000002UL /**< Mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_INSEL_PRSASYNCPULSE 0x00000003UL /**< Mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_DEFAULT (_TIMER_CC_CFG_INSEL_DEFAULT << 17) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PIN (_TIMER_CC_CFG_INSEL_PIN << 17) /**< Shifted mode PIN for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSSYNC (_TIMER_CC_CFG_INSEL_PRSSYNC << 17) /**< Shifted mode PRSSYNC for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCLEVEL (_TIMER_CC_CFG_INSEL_PRSASYNCLEVEL << 17) /**< Shifted mode PRSASYNCLEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_INSEL_PRSASYNCPULSE (_TIMER_CC_CFG_INSEL_PRSASYNCPULSE << 17) /**< Shifted mode PRSASYNCPULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF (0x1UL << 19) /**< PRS Configuration */ +#define _TIMER_CC_CFG_PRSCONF_SHIFT 19 /**< Shift value for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_MASK 0x80000UL /**< Bit mask for TIMER_PRSCONF */ +#define _TIMER_CC_CFG_PRSCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_PULSE 0x00000000UL /**< Mode PULSE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_PRSCONF_LEVEL 0x00000001UL /**< Mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_DEFAULT (_TIMER_CC_CFG_PRSCONF_DEFAULT << 19) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_PULSE (_TIMER_CC_CFG_PRSCONF_PULSE << 19) /**< Shifted mode PULSE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_PRSCONF_LEVEL (_TIMER_CC_CFG_PRSCONF_LEVEL << 19) /**< Shifted mode LEVEL for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT (0x1UL << 20) /**< Digital Filter */ +#define _TIMER_CC_CFG_FILT_SHIFT 20 /**< Shift value for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_MASK 0x100000UL /**< Bit mask for TIMER_FILT */ +#define _TIMER_CC_CFG_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_DISABLE 0x00000000UL /**< Mode DISABLE for TIMER_CC_CFG */ +#define _TIMER_CC_CFG_FILT_ENABLE 0x00000001UL /**< Mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DEFAULT (_TIMER_CC_CFG_FILT_DEFAULT << 20) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_DISABLE (_TIMER_CC_CFG_FILT_DISABLE << 20) /**< Shifted mode DISABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_FILT_ENABLE (_TIMER_CC_CFG_FILT_ENABLE << 20) /**< Shifted mode ENABLE for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL (0x1UL << 21) /**< Input Capture FIFO watermark level */ +#define _TIMER_CC_CFG_ICFWL_SHIFT 21 /**< Shift value for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_MASK 0x200000UL /**< Bit mask for TIMER_ICFWL */ +#define _TIMER_CC_CFG_ICFWL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CFG */ +#define TIMER_CC_CFG_ICFWL_DEFAULT (_TIMER_CC_CFG_ICFWL_DEFAULT << 21) /**< Shifted mode DEFAULT for TIMER_CC_CFG */ + +/* Bit fields for TIMER CC_CTRL */ +#define _TIMER_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_MASK 0x0F003F04UL /**< Mask for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV (0x1UL << 2) /**< Output Invert */ +#define _TIMER_CC_CTRL_OUTINV_SHIFT 2 /**< Shift value for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_MASK 0x4UL /**< Bit mask for TIMER_OUTINV */ +#define _TIMER_CC_CTRL_OUTINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_OUTINV_DEFAULT (_TIMER_CC_CTRL_OUTINV_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SHIFT 8 /**< Shift value for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_MASK 0x300UL /**< Bit mask for TIMER_CMOA */ +#define _TIMER_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_DEFAULT (_TIMER_CC_CTRL_CMOA_DEFAULT << 8) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_NONE (_TIMER_CC_CTRL_CMOA_NONE << 8) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_TOGGLE (_TIMER_CC_CTRL_CMOA_TOGGLE << 8) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_CLEAR (_TIMER_CC_CTRL_CMOA_CLEAR << 8) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CMOA_SET (_TIMER_CC_CTRL_CMOA_SET << 8) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SHIFT 10 /**< Shift value for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_MASK 0xC00UL /**< Bit mask for TIMER_COFOA */ +#define _TIMER_CC_CTRL_COFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_COFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_DEFAULT (_TIMER_CC_CTRL_COFOA_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_NONE (_TIMER_CC_CTRL_COFOA_NONE << 10) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_TOGGLE (_TIMER_CC_CTRL_COFOA_TOGGLE << 10) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_CLEAR (_TIMER_CC_CTRL_COFOA_CLEAR << 10) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_COFOA_SET (_TIMER_CC_CTRL_COFOA_SET << 10) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SHIFT 12 /**< Shift value for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_MASK 0x3000UL /**< Bit mask for TIMER_CUFOA */ +#define _TIMER_CC_CTRL_CUFOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_NONE 0x00000000UL /**< Mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_CUFOA_SET 0x00000003UL /**< Mode SET for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_DEFAULT (_TIMER_CC_CTRL_CUFOA_DEFAULT << 12) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_NONE (_TIMER_CC_CTRL_CUFOA_NONE << 12) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_TOGGLE (_TIMER_CC_CTRL_CUFOA_TOGGLE << 12) /**< Shifted mode TOGGLE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_CLEAR (_TIMER_CC_CTRL_CUFOA_CLEAR << 12) /**< Shifted mode CLEAR for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_CUFOA_SET (_TIMER_CC_CTRL_CUFOA_SET << 12) /**< Shifted mode SET for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_SHIFT 24 /**< Shift value for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_MASK 0x3000000UL /**< Bit mask for TIMER_ICEDGE */ +#define _TIMER_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_DEFAULT (_TIMER_CC_CTRL_ICEDGE_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_RISING (_TIMER_CC_CTRL_ICEDGE_RISING << 24) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_FALLING (_TIMER_CC_CTRL_ICEDGE_FALLING << 24) /**< Shifted mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_BOTH (_TIMER_CC_CTRL_ICEDGE_BOTH << 24) /**< Shifted mode BOTH for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEDGE_NONE (_TIMER_CC_CTRL_ICEDGE_NONE << 24) /**< Shifted mode NONE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_SHIFT 26 /**< Shift value for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_MASK 0xC000000UL /**< Bit mask for TIMER_ICEVCTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0x00000000UL /**< Mode EVERYEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 0x00000001UL /**< Mode EVERYSECONDEDGE for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_RISING 0x00000002UL /**< Mode RISING for TIMER_CC_CTRL */ +#define _TIMER_CC_CTRL_ICEVCTRL_FALLING 0x00000003UL /**< Mode FALLING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_DEFAULT (_TIMER_CC_CTRL_ICEVCTRL_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE << 26) /**< Shifted mode EVERYEDGE for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE (_TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE << 26) /**< Shifted mode EVERYSECONDEDGE for TIMER_CC_CTRL*/ +#define TIMER_CC_CTRL_ICEVCTRL_RISING (_TIMER_CC_CTRL_ICEVCTRL_RISING << 26) /**< Shifted mode RISING for TIMER_CC_CTRL */ +#define TIMER_CC_CTRL_ICEVCTRL_FALLING (_TIMER_CC_CTRL_ICEVCTRL_FALLING << 26) /**< Shifted mode FALLING for TIMER_CC_CTRL */ + +/* Bit fields for TIMER CC_OC */ +#define _TIMER_CC_OC_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OC */ +#define _TIMER_CC_OC_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OC */ +#define _TIMER_CC_OC_OC_SHIFT 0 /**< Shift value for TIMER_OC */ +#define _TIMER_CC_OC_OC_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OC */ +#define _TIMER_CC_OC_OC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OC */ +#define TIMER_CC_OC_OC_DEFAULT (_TIMER_CC_OC_OC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OC */ + +/* Bit fields for TIMER CC_OCB */ +#define _TIMER_CC_OCB_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_OCB */ +#define _TIMER_CC_OCB_OCB_SHIFT 0 /**< Shift value for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_OCB */ +#define _TIMER_CC_OCB_OCB_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_OCB */ +#define TIMER_CC_OCB_OCB_DEFAULT (_TIMER_CC_OCB_OCB_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_OCB */ + +/* Bit fields for TIMER CC_ICF */ +#define _TIMER_CC_ICF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICF */ +#define _TIMER_CC_ICF_ICF_SHIFT 0 /**< Shift value for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICF */ +#define _TIMER_CC_ICF_ICF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICF */ +#define TIMER_CC_ICF_ICF_DEFAULT (_TIMER_CC_ICF_ICF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICF */ + +/* Bit fields for TIMER CC_ICOF */ +#define _TIMER_CC_ICOF_RESETVALUE 0x00000000UL /**< Default value for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_MASK 0xFFFFFFFFUL /**< Mask for TIMER_CC_ICOF */ +#define _TIMER_CC_ICOF_ICOF_SHIFT 0 /**< Shift value for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_MASK 0xFFFFFFFFUL /**< Bit mask for TIMER_ICOF */ +#define _TIMER_CC_ICOF_ICOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_CC_ICOF */ +#define TIMER_CC_ICOF_ICOF_DEFAULT (_TIMER_CC_ICOF_ICOF_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_CC_ICOF */ + +/* Bit fields for TIMER DTCFG */ +#define _TIMER_DTCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCFG */ +#define _TIMER_DTCFG_MASK 0x00000E03UL /**< Mask for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN (0x1UL << 0) /**< DTI Enable */ +#define _TIMER_DTCFG_DTEN_SHIFT 0 /**< Shift value for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_MASK 0x1UL /**< Bit mask for TIMER_DTEN */ +#define _TIMER_DTCFG_DTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTEN_DEFAULT (_TIMER_DTCFG_DTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS (0x1UL << 1) /**< DTI Automatic Start-up Functionality */ +#define _TIMER_DTCFG_DTDAS_SHIFT 1 /**< Shift value for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_MASK 0x2UL /**< Bit mask for TIMER_DTDAS */ +#define _TIMER_DTCFG_DTDAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_NORESTART 0x00000000UL /**< Mode NORESTART for TIMER_DTCFG */ +#define _TIMER_DTCFG_DTDAS_RESTART 0x00000001UL /**< Mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_DEFAULT (_TIMER_DTCFG_DTDAS_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_NORESTART (_TIMER_DTCFG_DTDAS_NORESTART << 1) /**< Shifted mode NORESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTDAS_RESTART (_TIMER_DTCFG_DTDAS_RESTART << 1) /**< Shifted mode RESTART for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR (0x1UL << 9) /**< DTI Always Run */ +#define _TIMER_DTCFG_DTAR_SHIFT 9 /**< Shift value for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_MASK 0x200UL /**< Bit mask for TIMER_DTAR */ +#define _TIMER_DTCFG_DTAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTAR_DEFAULT (_TIMER_DTCFG_DTAR_DEFAULT << 9) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS (0x1UL << 10) /**< DTI Fault Action on Timer Stop */ +#define _TIMER_DTCFG_DTFATS_SHIFT 10 /**< Shift value for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_MASK 0x400UL /**< Bit mask for TIMER_DTFATS */ +#define _TIMER_DTCFG_DTFATS_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTFATS_DEFAULT (_TIMER_DTCFG_DTFATS_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN (0x1UL << 11) /**< DTI PRS Source Enable */ +#define _TIMER_DTCFG_DTPRSEN_SHIFT 11 /**< Shift value for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_MASK 0x800UL /**< Bit mask for TIMER_DTPRSEN */ +#define _TIMER_DTCFG_DTPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCFG */ +#define TIMER_DTCFG_DTPRSEN_DEFAULT (_TIMER_DTCFG_DTPRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for TIMER_DTCFG */ + +/* Bit fields for TIMER DTTIMECFG */ +#define _TIMER_DTTIMECFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_MASK 0x003FFFFFUL /**< Mask for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTPRESC_SHIFT 0 /**< Shift value for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_MASK 0x3FFUL /**< Bit mask for TIMER_DTPRESC */ +#define _TIMER_DTTIMECFG_DTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTPRESC_DEFAULT (_TIMER_DTTIMECFG_DTPRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTRISET_SHIFT 10 /**< Shift value for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_MASK 0xFC00UL /**< Bit mask for TIMER_DTRISET */ +#define _TIMER_DTTIMECFG_DTRISET_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTRISET_DEFAULT (_TIMER_DTTIMECFG_DTRISET_DEFAULT << 10) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ +#define _TIMER_DTTIMECFG_DTFALLT_SHIFT 16 /**< Shift value for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_MASK 0x3F0000UL /**< Bit mask for TIMER_DTFALLT */ +#define _TIMER_DTTIMECFG_DTFALLT_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTTIMECFG */ +#define TIMER_DTTIMECFG_DTFALLT_DEFAULT (_TIMER_DTTIMECFG_DTFALLT_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTTIMECFG */ + +/* Bit fields for TIMER DTFCFG */ +#define _TIMER_DTFCFG_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_MASK 0x1F030000UL /**< Mask for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_SHIFT 16 /**< Shift value for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_MASK 0x30000UL /**< Bit mask for TIMER_DTFA */ +#define _TIMER_DTFCFG_DTFA_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_NONE 0x00000000UL /**< Mode NONE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_INACTIVE 0x00000001UL /**< Mode INACTIVE for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_CLEAR 0x00000002UL /**< Mode CLEAR for TIMER_DTFCFG */ +#define _TIMER_DTFCFG_DTFA_TRISTATE 0x00000003UL /**< Mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_DEFAULT (_TIMER_DTFCFG_DTFA_DEFAULT << 16) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_NONE (_TIMER_DTFCFG_DTFA_NONE << 16) /**< Shifted mode NONE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_INACTIVE (_TIMER_DTFCFG_DTFA_INACTIVE << 16) /**< Shifted mode INACTIVE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_CLEAR (_TIMER_DTFCFG_DTFA_CLEAR << 16) /**< Shifted mode CLEAR for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTFA_TRISTATE (_TIMER_DTFCFG_DTFA_TRISTATE << 16) /**< Shifted mode TRISTATE for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN (0x1UL << 24) /**< DTI PRS 0 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS0FEN_SHIFT 24 /**< Shift value for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_MASK 0x1000000UL /**< Bit mask for TIMER_DTPRS0FEN */ +#define _TIMER_DTFCFG_DTPRS0FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS0FEN_DEFAULT (_TIMER_DTFCFG_DTPRS0FEN_DEFAULT << 24) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN (0x1UL << 25) /**< DTI PRS 1 Fault Enable */ +#define _TIMER_DTFCFG_DTPRS1FEN_SHIFT 25 /**< Shift value for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_MASK 0x2000000UL /**< Bit mask for TIMER_DTPRS1FEN */ +#define _TIMER_DTFCFG_DTPRS1FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTPRS1FEN_DEFAULT (_TIMER_DTFCFG_DTPRS1FEN_DEFAULT << 25) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN (0x1UL << 26) /**< DTI Debugger Fault Enable */ +#define _TIMER_DTFCFG_DTDBGFEN_SHIFT 26 /**< Shift value for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_MASK 0x4000000UL /**< Bit mask for TIMER_DTDBGFEN */ +#define _TIMER_DTFCFG_DTDBGFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTDBGFEN_DEFAULT (_TIMER_DTFCFG_DTDBGFEN_DEFAULT << 26) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN (0x1UL << 27) /**< DTI Lockup Fault Enable */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_SHIFT 27 /**< Shift value for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_MASK 0x8000000UL /**< Bit mask for TIMER_DTLOCKUPFEN */ +#define _TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT (_TIMER_DTFCFG_DTLOCKUPFEN_DEFAULT << 27) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN (0x1UL << 28) /**< DTI EM23 Fault Enable */ +#define _TIMER_DTFCFG_DTEM23FEN_SHIFT 28 /**< Shift value for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_MASK 0x10000000UL /**< Bit mask for TIMER_DTEM23FEN */ +#define _TIMER_DTFCFG_DTEM23FEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFCFG */ +#define TIMER_DTFCFG_DTEM23FEN_DEFAULT (_TIMER_DTFCFG_DTEM23FEN_DEFAULT << 28) /**< Shifted mode DEFAULT for TIMER_DTFCFG */ + +/* Bit fields for TIMER DTCTRL */ +#define _TIMER_DTCTRL_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTCTRL */ +#define _TIMER_DTCTRL_MASK 0x00000003UL /**< Mask for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV (0x1UL << 0) /**< DTI Complementary Output Invert. */ +#define _TIMER_DTCTRL_DTCINV_SHIFT 0 /**< Shift value for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_MASK 0x1UL /**< Bit mask for TIMER_DTCINV */ +#define _TIMER_DTCTRL_DTCINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTCINV_DEFAULT (_TIMER_DTCTRL_DTCINV_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL (0x1UL << 1) /**< DTI Inactive Polarity */ +#define _TIMER_DTCTRL_DTIPOL_SHIFT 1 /**< Shift value for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_MASK 0x2UL /**< Bit mask for TIMER_DTIPOL */ +#define _TIMER_DTCTRL_DTIPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTCTRL */ +#define TIMER_DTCTRL_DTIPOL_DEFAULT (_TIMER_DTCTRL_DTIPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTCTRL */ + +/* Bit fields for TIMER DTOGEN */ +#define _TIMER_DTOGEN_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTOGEN */ +#define _TIMER_DTOGEN_MASK 0x0000003FUL /**< Mask for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN (0x1UL << 0) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC0EN_SHIFT 0 /**< Shift value for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_MASK 0x1UL /**< Bit mask for TIMER_DTOGCC0EN */ +#define _TIMER_DTOGEN_DTOGCC0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC0EN_DEFAULT (_TIMER_DTOGEN_DTOGCC0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN (0x1UL << 1) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC1EN_SHIFT 1 /**< Shift value for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_MASK 0x2UL /**< Bit mask for TIMER_DTOGCC1EN */ +#define _TIMER_DTOGEN_DTOGCC1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC1EN_DEFAULT (_TIMER_DTOGEN_DTOGCC1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN (0x1UL << 2) /**< DTI CCn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCC2EN_SHIFT 2 /**< Shift value for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_MASK 0x4UL /**< Bit mask for TIMER_DTOGCC2EN */ +#define _TIMER_DTOGEN_DTOGCC2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCC2EN_DEFAULT (_TIMER_DTOGEN_DTOGCC2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN (0x1UL << 3) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_SHIFT 3 /**< Shift value for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_MASK 0x8UL /**< Bit mask for TIMER_DTOGCDTI0EN */ +#define _TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI0EN_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN (0x1UL << 4) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_SHIFT 4 /**< Shift value for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_MASK 0x10UL /**< Bit mask for TIMER_DTOGCDTI1EN */ +#define _TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI1EN_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN (0x1UL << 5) /**< DTI CDTIn Output Generation Enable */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_SHIFT 5 /**< Shift value for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_MASK 0x20UL /**< Bit mask for TIMER_DTOGCDTI2EN */ +#define _TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTOGEN */ +#define TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT (_TIMER_DTOGEN_DTOGCDTI2EN_DEFAULT << 5) /**< Shifted mode DEFAULT for TIMER_DTOGEN */ + +/* Bit fields for TIMER DTFAULT */ +#define _TIMER_DTFAULT_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULT */ +#define _TIMER_DTFAULT_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F (0x1UL << 0) /**< DTI PRS 0 Fault */ +#define _TIMER_DTFAULT_DTPRS0F_SHIFT 0 /**< Shift value for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0F */ +#define _TIMER_DTFAULT_DTPRS0F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS0F_DEFAULT (_TIMER_DTFAULT_DTPRS0F_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F (0x1UL << 1) /**< DTI PRS 1 Fault */ +#define _TIMER_DTFAULT_DTPRS1F_SHIFT 1 /**< Shift value for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1F */ +#define _TIMER_DTFAULT_DTPRS1F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTPRS1F_DEFAULT (_TIMER_DTFAULT_DTPRS1F_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF (0x1UL << 2) /**< DTI Debugger Fault */ +#define _TIMER_DTFAULT_DTDBGF_SHIFT 2 /**< Shift value for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_MASK 0x4UL /**< Bit mask for TIMER_DTDBGF */ +#define _TIMER_DTFAULT_DTDBGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTDBGF_DEFAULT (_TIMER_DTFAULT_DTDBGF_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF (0x1UL << 3) /**< DTI Lockup Fault */ +#define _TIMER_DTFAULT_DTLOCKUPF_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPF */ +#define _TIMER_DTFAULT_DTLOCKUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTLOCKUPF_DEFAULT (_TIMER_DTFAULT_DTLOCKUPF_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F (0x1UL << 4) /**< DTI EM23 Entry Fault */ +#define _TIMER_DTFAULT_DTEM23F_SHIFT 4 /**< Shift value for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_MASK 0x10UL /**< Bit mask for TIMER_DTEM23F */ +#define _TIMER_DTFAULT_DTEM23F_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULT */ +#define TIMER_DTFAULT_DTEM23F_DEFAULT (_TIMER_DTFAULT_DTEM23F_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULT */ + +/* Bit fields for TIMER DTFAULTC */ +#define _TIMER_DTFAULTC_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTFAULTC */ +#define _TIMER_DTFAULTC_MASK 0x0000001FUL /**< Mask for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC (0x1UL << 0) /**< DTI PRS0 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS0FC_SHIFT 0 /**< Shift value for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_MASK 0x1UL /**< Bit mask for TIMER_DTPRS0FC */ +#define _TIMER_DTFAULTC_DTPRS0FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS0FC_DEFAULT (_TIMER_DTFAULTC_DTPRS0FC_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC (0x1UL << 1) /**< DTI PRS1 Fault Clear */ +#define _TIMER_DTFAULTC_DTPRS1FC_SHIFT 1 /**< Shift value for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_MASK 0x2UL /**< Bit mask for TIMER_DTPRS1FC */ +#define _TIMER_DTFAULTC_DTPRS1FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTPRS1FC_DEFAULT (_TIMER_DTFAULTC_DTPRS1FC_DEFAULT << 1) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC (0x1UL << 2) /**< DTI Debugger Fault Clear */ +#define _TIMER_DTFAULTC_DTDBGFC_SHIFT 2 /**< Shift value for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_MASK 0x4UL /**< Bit mask for TIMER_DTDBGFC */ +#define _TIMER_DTFAULTC_DTDBGFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTDBGFC_DEFAULT (_TIMER_DTFAULTC_DTDBGFC_DEFAULT << 2) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC (0x1UL << 3) /**< DTI Lockup Fault Clear */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_SHIFT 3 /**< Shift value for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_MASK 0x8UL /**< Bit mask for TIMER_DTLOCKUPFC */ +#define _TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT (_TIMER_DTFAULTC_DTLOCKUPFC_DEFAULT << 3) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC (0x1UL << 4) /**< DTI EM23 Fault Clear */ +#define _TIMER_DTFAULTC_DTEM23FC_SHIFT 4 /**< Shift value for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_MASK 0x10UL /**< Bit mask for TIMER_DTEM23FC */ +#define _TIMER_DTFAULTC_DTEM23FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTFAULTC */ +#define TIMER_DTFAULTC_DTEM23FC_DEFAULT (_TIMER_DTFAULTC_DTEM23FC_DEFAULT << 4) /**< Shifted mode DEFAULT for TIMER_DTFAULTC */ + +/* Bit fields for TIMER DTLOCK */ +#define _TIMER_DTLOCK_RESETVALUE 0x00000000UL /**< Default value for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_MASK 0x0000FFFFUL /**< Mask for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_SHIFT 0 /**< Shift value for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_MASK 0xFFFFUL /**< Bit mask for TIMER_DTILOCKKEY */ +#define _TIMER_DTLOCK_DTILOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for TIMER_DTLOCK */ +#define _TIMER_DTLOCK_DTILOCKKEY_UNLOCK 0x0000CE80UL /**< Mode UNLOCK for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_DEFAULT (_TIMER_DTLOCK_DTILOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for TIMER_DTLOCK */ +#define TIMER_DTLOCK_DTILOCKKEY_UNLOCK (_TIMER_DTLOCK_DTILOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for TIMER_DTLOCK */ + +/** @} End of group EFR32BG22_TIMER_BitFields */ +/** @} End of group EFR32BG22_TIMER */ +/** @} End of group Parts */ + +#endif // EFR32BG22_TIMER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h index a6781bf..6e220a5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_ulfrco.h @@ -1,147 +1,147 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 ULFRCO register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_ULFRCO_H -#define EFR32BG22_ULFRCO_H -#define ULFRCO_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_ULFRCO ULFRCO - * @{ - * @brief EFR32BG22 ULFRCO Register Declaration. - *****************************************************************************/ - -/** ULFRCO Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP version */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - uint32_t RESERVED1[2U]; /**< Reserved for future use */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - uint32_t RESERVED2[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP version */ - uint32_t RESERVED3[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - uint32_t RESERVED4[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - uint32_t RESERVED5[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP version */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - uint32_t RESERVED7[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - uint32_t RESERVED8[1017U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP version */ - uint32_t RESERVED9[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - uint32_t RESERVED10[2U]; /**< Reserved for future use */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ -} ULFRCO_TypeDef; -/** @} End of group EFR32BG22_ULFRCO */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_ULFRCO - * @{ - * @defgroup EFR32BG22_ULFRCO_BitFields ULFRCO Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for ULFRCO IPVERSION */ -#define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ -#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ -#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ - -/* Bit fields for ULFRCO STATUS */ -#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ -#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ -#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ -#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ -#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ -#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ - -/* Bit fields for ULFRCO IF */ -#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ -#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ -#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ -#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ -#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ -#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ -#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ - -/* Bit fields for ULFRCO IEN */ -#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ -#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ -#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ -#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ -#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ -#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ -#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ -#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ -#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ - -/** @} End of group EFR32BG22_ULFRCO_BitFields */ -/** @} End of group EFR32BG22_ULFRCO */ -/** @} End of group Parts */ - -#endif // EFR32BG22_ULFRCO_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 ULFRCO register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_ULFRCO_H +#define EFR32BG22_ULFRCO_H +#define ULFRCO_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_ULFRCO ULFRCO + * @{ + * @brief EFR32BG22 ULFRCO Register Declaration. + *****************************************************************************/ + +/** ULFRCO Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP version */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + uint32_t RESERVED1[2U]; /**< Reserved for future use */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + uint32_t RESERVED2[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP version */ + uint32_t RESERVED3[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + uint32_t RESERVED4[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + uint32_t RESERVED5[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP version */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + uint32_t RESERVED7[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + uint32_t RESERVED8[1017U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP version */ + uint32_t RESERVED9[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + uint32_t RESERVED10[2U]; /**< Reserved for future use */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ +} ULFRCO_TypeDef; +/** @} End of group EFR32BG22_ULFRCO */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_ULFRCO + * @{ + * @defgroup EFR32BG22_ULFRCO_BitFields ULFRCO Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for ULFRCO IPVERSION */ +#define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */ +#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */ +#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */ + +/* Bit fields for ULFRCO STATUS */ +#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */ +#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */ +#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */ +#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */ +#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */ +#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */ + +/* Bit fields for ULFRCO IF */ +#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */ +#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */ +#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */ +#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */ +#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */ +#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */ +#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */ + +/* Bit fields for ULFRCO IEN */ +#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */ +#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */ +#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */ +#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */ +#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */ +#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */ +#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */ +#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */ +#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */ + +/** @} End of group EFR32BG22_ULFRCO_BitFields */ +/** @} End of group EFR32BG22_ULFRCO */ +/** @} End of group Parts */ + +#endif // EFR32BG22_ULFRCO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h index 54061cc..7451447 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_usart.h @@ -1,1431 +1,1431 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 USART register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_USART_H -#define EFR32BG22_USART_H -#define USART_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_USART USART - * @{ - * @brief EFR32BG22 USART Register Declaration. - *****************************************************************************/ - -/** USART Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IPVERSION */ - __IOM uint32_t EN; /**< USART Enable */ - __IOM uint32_t CTRL; /**< Control Register */ - __IOM uint32_t FRAME; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ - __IOM uint32_t CMD; /**< Command Register */ - __IM uint32_t STATUS; /**< USART Status Register */ - __IOM uint32_t CLKDIV; /**< Clock Control Register */ - __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL; /**< I2S Control Register */ - __IOM uint32_t TIMING; /**< Timing Register */ - __IOM uint32_t CTRLX; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ - uint32_t RESERVED0[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IPVERSION */ - __IOM uint32_t EN_SET; /**< USART Enable */ - __IOM uint32_t CTRL_SET; /**< Control Register */ - __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - __IM uint32_t STATUS_SET; /**< USART Status Register */ - __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ - __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ - __IOM uint32_t TIMING_SET; /**< Timing Register */ - __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ - uint32_t RESERVED1[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ - __IOM uint32_t EN_CLR; /**< USART Enable */ - __IOM uint32_t CTRL_CLR; /**< Control Register */ - __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - __IM uint32_t STATUS_CLR; /**< USART Status Register */ - __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ - __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ - __IOM uint32_t TIMING_CLR; /**< Timing Register */ - __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ - uint32_t RESERVED2[997U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ - __IOM uint32_t EN_TGL; /**< USART Enable */ - __IOM uint32_t CTRL_TGL; /**< Control Register */ - __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ - __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - __IM uint32_t STATUS_TGL; /**< USART Status Register */ - __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ - __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ - __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ - __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ - __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ - __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ - __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ - __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ - __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ - __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ - __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ - __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ - __IOM uint32_t TIMING_TGL; /**< Timing Register */ - __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ - __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ - __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ - __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ -} USART_TypeDef; -/** @} End of group EFR32BG22_USART */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_USART - * @{ - * @defgroup EFR32BG22_USART_BitFields USART Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for USART IPVERSION */ -#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ -#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ -#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ -#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ - -/* Bit fields for USART EN */ -#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ -#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ -#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ -#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ -#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ -#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ -#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ - -/* Bit fields for USART CTRL */ -#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ -#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ -#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ -#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ -#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ -#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ -#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ -#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ -#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ -#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ -#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ -#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ -#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ -#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ -#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ -#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ -#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ -#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ -#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ -#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ -#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ -#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ -#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ -#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ -#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ -#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ -#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ -#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ -#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ -#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ -#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ -#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ -#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ -#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ -#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ -#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ -#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ -#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ -#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ -#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ -#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ -#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ -#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ -#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ -#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ -#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ -#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ -#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ -#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ -#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ -#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ -#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ -#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ -#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ -#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ -#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ -#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ -#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ -#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ -#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ -#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ -#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ -#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ -#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ -#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ -#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ -#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ -#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ -#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ -#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ -#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ -#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ -#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ -#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ -#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ -#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ -#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ -#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ -#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ -#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ -#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ -#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ -#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ -#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ -#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ -#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ -#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ -#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ -#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ -#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ -#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ -#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ -#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ -#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ -#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ -#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ - -/* Bit fields for USART FRAME */ -#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ -#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ -#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ -#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ -#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ -#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ -#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ -#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ -#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ -#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ -#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ -#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ -#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ -#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ -#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ -#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ -#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ -#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ -#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ -#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ -#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ -#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ -#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ -#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ -#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ -#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ -#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ -#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ -#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ -#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ -#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ -#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ -#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ -#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ -#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ -#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ - -/* Bit fields for USART TRIGCTRL */ -#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ -#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ -#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ -#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ -#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ -#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ -#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ -#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ -#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ -#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ -#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ -#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ -#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ -#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ -#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ -#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ -#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ - -/* Bit fields for USART CMD */ -#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ -#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ -#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ -#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ -#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ -#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ -#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ -#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ -#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ -#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ -#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ -#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ -#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ -#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ -#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ -#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ -#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ -#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ -#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ -#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ -#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ -#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ -#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ -#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ -#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ -#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ -#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ -#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ -#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ -#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ -#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ -#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ -#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ -#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ -#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ -#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ -#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ -#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ -#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ -#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ - -/* Bit fields for USART STATUS */ -#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ -#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ -#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ -#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ -#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ -#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ -#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ -#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ -#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ -#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ -#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ -#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ -#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ -#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ -#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ -#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ -#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ -#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ -#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ -#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ -#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ -#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ -#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ -#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ -#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ -#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ -#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ -#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ -#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ -#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ -#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ -#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ -#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ -#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ -#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ -#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ -#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ -#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ -#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ -#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ -#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ -#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ - -/* Bit fields for USART CLKDIV */ -#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ -#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ -#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ -#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ -#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ -#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ -#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ -#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ - -/* Bit fields for USART RXDATAX */ -#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ -#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ -#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ -#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ -#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ -#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ -#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ -#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ -#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ -#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ -#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ -#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ - -/* Bit fields for USART RXDATA */ -#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ -#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ -#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ -#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ - -/* Bit fields for USART RXDOUBLEX */ -#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ -#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ -#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ -#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ -#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ -#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ -#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ -#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ -#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ - -/* Bit fields for USART RXDOUBLE */ -#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ -#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ -#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ -#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ -#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ -#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ - -/* Bit fields for USART RXDATAXP */ -#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ -#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ -#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ -#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ -#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ -#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ -#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ -#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ -#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ -#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ -#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ - -/* Bit fields for USART RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ -#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ -#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ -#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ -#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ -#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ -#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ -#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ -#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ -#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ -#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ - -/* Bit fields for USART TXDATAX */ -#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ -#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ -#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ -#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ -#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ -#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ -#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ -#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ -#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ -#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ -#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ -#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ -#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ -#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ - -/* Bit fields for USART TXDATA */ -#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ -#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ -#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ -#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ - -/* Bit fields for USART TXDOUBLEX */ -#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ -#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ -#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ -#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ -#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ -#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ -#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ -#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ -#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ -#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ -#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ -#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ -#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ -#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ -#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ -#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ - -/* Bit fields for USART TXDOUBLE */ -#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ -#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ -#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ -#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ -#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ -#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ - -/* Bit fields for USART IF */ -#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ -#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ -#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ -#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ -#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ -#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ -#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ -#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ -#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ -#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ -#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ -#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ -#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ -#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ -#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ -#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ -#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ -#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ -#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ -#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ -#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ -#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ -#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ -#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ -#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ -#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ -#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ -#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ -#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ -#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ -#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ -#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ -#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ -#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ -#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ -#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ -#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ -#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ -#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ -#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ -#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ -#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ -#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ -#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ -#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ -#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ -#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ -#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ -#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ -#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ -#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ -#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ -#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ - -/* Bit fields for USART IEN */ -#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ -#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ -#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ -#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ -#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ -#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ -#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ -#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ -#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ -#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ -#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ -#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ -#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ -#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ -#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ -#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ -#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ -#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ -#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ -#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ -#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ -#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ -#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ -#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ -#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ -#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ -#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ -#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ -#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ -#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ -#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ -#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ -#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ -#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ -#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ -#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ -#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ -#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ -#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ -#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ -#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ -#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ -#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ -#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ -#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ -#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ -#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ -#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ -#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ -#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ -#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ -#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ -#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ -#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ -#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ - -/* Bit fields for USART IRCTRL */ -#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ -#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ -#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ -#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ -#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ -#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ -#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ -#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ -#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ -#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ -#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ -#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ -#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ -#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ -#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ -#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ - -/* Bit fields for USART I2SCTRL */ -#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ -#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ -#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ -#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ -#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ -#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ -#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ -#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ -#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ -#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ -#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ -#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ -#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ -#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ -#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ -#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ -#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ -#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ -#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ -#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ -#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ -#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ -#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ -#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ - -/* Bit fields for USART TIMING */ -#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ -#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ -#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ -#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ -#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ -#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ -#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ -#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ -#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ -#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ -#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ -#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ -#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ -#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ -#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ -#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ -#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ -#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ -#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ -#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ -#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ -#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ -#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ -#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ - -/* Bit fields for USART CTRLX */ -#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ -#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ -#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ -#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ -#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ -#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ -#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ -#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ -#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ -#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ -#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ -#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ -#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ -#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ -#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ -#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ -#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ -#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ -#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ -#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ -#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ -#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ -#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ -#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ -#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ - -/* Bit fields for USART TIMECMP0 */ -#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ -#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ -#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ -#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ -#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ -#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ - -/* Bit fields for USART TIMECMP1 */ -#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ -#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ -#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ -#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ -#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ -#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ - -/* Bit fields for USART TIMECMP2 */ -#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ -#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ -#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ -#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ -#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ -#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ -#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ -#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ -#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ -#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ - -/** @} End of group EFR32BG22_USART_BitFields */ -/** @} End of group EFR32BG22_USART */ -/** @} End of group Parts */ - -#endif // EFR32BG22_USART_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 USART register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_USART_H +#define EFR32BG22_USART_H +#define USART_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_USART USART + * @{ + * @brief EFR32BG22 USART Register Declaration. + *****************************************************************************/ + +/** USART Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IPVERSION */ + __IOM uint32_t EN; /**< USART Enable */ + __IOM uint32_t CTRL; /**< Control Register */ + __IOM uint32_t FRAME; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */ + __IOM uint32_t CMD; /**< Command Register */ + __IM uint32_t STATUS; /**< USART Status Register */ + __IOM uint32_t CLKDIV; /**< Clock Control Register */ + __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL; /**< I2S Control Register */ + __IOM uint32_t TIMING; /**< Timing Register */ + __IOM uint32_t CTRLX; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2; /**< Timer Compare 2 */ + uint32_t RESERVED0[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IPVERSION */ + __IOM uint32_t EN_SET; /**< USART Enable */ + __IOM uint32_t CTRL_SET; /**< Control Register */ + __IOM uint32_t FRAME_SET; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_SET; /**< USART Trigger Control register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + __IM uint32_t STATUS_SET; /**< USART Status Register */ + __IOM uint32_t CLKDIV_SET; /**< Clock Control Register */ + __IM uint32_t RXDATAX_SET; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_SET; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_SET; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_SET; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_SET; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_SET; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_SET; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_SET; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_SET; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_SET; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_SET; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_SET; /**< I2S Control Register */ + __IOM uint32_t TIMING_SET; /**< Timing Register */ + __IOM uint32_t CTRLX_SET; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_SET; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_SET; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_SET; /**< Timer Compare 2 */ + uint32_t RESERVED1[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ + __IOM uint32_t EN_CLR; /**< USART Enable */ + __IOM uint32_t CTRL_CLR; /**< Control Register */ + __IOM uint32_t FRAME_CLR; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_CLR; /**< USART Trigger Control register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + __IM uint32_t STATUS_CLR; /**< USART Status Register */ + __IOM uint32_t CLKDIV_CLR; /**< Clock Control Register */ + __IM uint32_t RXDATAX_CLR; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_CLR; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_CLR; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_CLR; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_CLR; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_CLR; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_CLR; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_CLR; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_CLR; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_CLR; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_CLR; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_CLR; /**< I2S Control Register */ + __IOM uint32_t TIMING_CLR; /**< Timing Register */ + __IOM uint32_t CTRLX_CLR; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_CLR; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_CLR; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_CLR; /**< Timer Compare 2 */ + uint32_t RESERVED2[997U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ + __IOM uint32_t EN_TGL; /**< USART Enable */ + __IOM uint32_t CTRL_TGL; /**< Control Register */ + __IOM uint32_t FRAME_TGL; /**< USART Frame Format Register */ + __IOM uint32_t TRIGCTRL_TGL; /**< USART Trigger Control register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + __IM uint32_t STATUS_TGL; /**< USART Status Register */ + __IOM uint32_t CLKDIV_TGL; /**< Clock Control Register */ + __IM uint32_t RXDATAX_TGL; /**< RX Buffer Data Extended Register */ + __IM uint32_t RXDATA_TGL; /**< RX Buffer Data Register */ + __IM uint32_t RXDOUBLEX_TGL; /**< RX Buffer Double Data Extended Register */ + __IM uint32_t RXDOUBLE_TGL; /**< RX FIFO Double Data Register */ + __IM uint32_t RXDATAXP_TGL; /**< RX Buffer Data Extended Peek Register */ + __IM uint32_t RXDOUBLEXP_TGL; /**< RX Buffer Double Data Extended Peek R... */ + __IOM uint32_t TXDATAX_TGL; /**< TX Buffer Data Extended Register */ + __IOM uint32_t TXDATA_TGL; /**< TX Buffer Data Register */ + __IOM uint32_t TXDOUBLEX_TGL; /**< TX Buffer Double Data Extended Register */ + __IOM uint32_t TXDOUBLE_TGL; /**< TX Buffer Double Data Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t IRCTRL_TGL; /**< IrDA Control Register */ + __IOM uint32_t I2SCTRL_TGL; /**< I2S Control Register */ + __IOM uint32_t TIMING_TGL; /**< Timing Register */ + __IOM uint32_t CTRLX_TGL; /**< Control Register Extended */ + __IOM uint32_t TIMECMP0_TGL; /**< Timer Compare 0 */ + __IOM uint32_t TIMECMP1_TGL; /**< Timer Compare 1 */ + __IOM uint32_t TIMECMP2_TGL; /**< Timer Compare 2 */ +} USART_TypeDef; +/** @} End of group EFR32BG22_USART */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_USART + * @{ + * @defgroup EFR32BG22_USART_BitFields USART Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for USART IPVERSION */ +#define _USART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for USART_IPVERSION */ +#define _USART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for USART_IPVERSION */ +#define _USART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IPVERSION */ +#define USART_IPVERSION_IPVERSION_DEFAULT (_USART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IPVERSION */ + +/* Bit fields for USART EN */ +#define _USART_EN_RESETVALUE 0x00000000UL /**< Default value for USART_EN */ +#define _USART_EN_MASK 0x00000001UL /**< Mask for USART_EN */ +#define USART_EN_EN (0x1UL << 0) /**< USART Enable */ +#define _USART_EN_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_EN_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_EN */ +#define USART_EN_EN_DEFAULT (_USART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_EN */ + +/* Bit fields for USART CTRL */ +#define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */ +#define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */ +#define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */ +#define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */ +#define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */ +#define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_SYNC_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_SYNC_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SYNC_DISABLE (_USART_CTRL_SYNC_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_SYNC_ENABLE (_USART_CTRL_SYNC_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */ +#define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */ +#define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_LOOPBK_DISABLE (_USART_CTRL_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_LOOPBK_ENABLE (_USART_CTRL_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */ +#define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */ +#define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */ +#define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CCEN_DISABLE (_USART_CTRL_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CCEN_ENABLE (_USART_CTRL_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */ +#define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */ +#define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */ +#define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPM_DISABLE (_USART_CTRL_MPM_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MPM_ENABLE (_USART_CTRL_MPM_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ +#define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */ +#define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */ +#define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */ +#define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */ +#define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */ +#define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */ +#define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */ +#define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */ +#define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */ +#define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */ +#define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */ +#define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */ +#define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */ +#define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */ +#define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */ +#define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */ +#define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */ +#define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */ +#define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */ +#define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */ +#define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */ +#define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */ +#define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */ +#define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */ +#define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */ +#define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MSBF_DISABLE (_USART_CTRL_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_MSBF_ENABLE (_USART_CTRL_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Chip Select In Main Mode */ +#define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */ +#define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */ +#define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */ +#define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */ +#define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */ +#define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */ +#define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */ +#define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */ +#define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */ +#define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */ +#define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */ +#define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */ +#define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */ +#define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */ +#define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */ +#define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_RXINV_DISABLE (_USART_CTRL_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_RXINV_ENABLE (_USART_CTRL_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */ +#define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */ +#define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */ +#define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_TXINV_DISABLE (_USART_CTRL_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_TXINV_ENABLE (_USART_CTRL_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */ +#define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */ +#define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */ +#define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_CSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_CSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_CSINV_DISABLE (_USART_CTRL_CSINV_DISABLE << 15) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_CSINV_ENABLE (_USART_CTRL_CSINV_ENABLE << 15) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */ +#define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */ +#define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ +#define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */ +#define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTRI_DISABLE (_USART_CTRL_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_AUTOTRI_ENABLE (_USART_CTRL_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */ +#define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */ +#define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */ +#define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */ +#define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */ +#define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ +#define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */ +#define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */ +#define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */ +#define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */ +#define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */ +#define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSDMA_DISABLE (_USART_CTRL_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSDMA_ENABLE (_USART_CTRL_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ +#define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */ +#define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSRX_DISABLE (_USART_CTRL_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSRX_ENABLE (_USART_CTRL_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ +#define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */ +#define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_ERRSTX_DISABLE (_USART_CTRL_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_ERRSTX_ENABLE (_USART_CTRL_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Secondary Setup Early */ +#define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */ +#define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */ +#define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */ +#define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRL */ +#define _USART_CTRL_BYTESWAP_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_BYTESWAP_DISABLE (_USART_CTRL_BYTESWAP_DISABLE << 28) /**< Shifted mode DISABLE for USART_CTRL */ +#define USART_CTRL_BYTESWAP_ENABLE (_USART_CTRL_BYTESWAP_ENABLE << 28) /**< Shifted mode ENABLE for USART_CTRL */ +#define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */ +#define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */ +#define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ +#define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */ +#define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */ +#define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Main Sample Delay */ +#define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */ +#define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */ +#define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */ + +/* Bit fields for USART FRAME */ +#define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */ +#define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */ +#define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */ +#define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */ +#define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */ +#define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */ +#define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */ +#define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */ +#define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */ +#define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */ +#define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */ +#define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */ +#define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */ +#define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */ +#define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */ +#define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */ +#define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */ +#define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */ +#define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */ +#define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */ +#define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */ +#define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */ +#define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */ +#define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */ +#define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */ +#define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */ +#define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */ +#define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */ +#define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */ +#define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */ +#define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */ +#define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */ +#define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */ +#define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */ +#define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */ +#define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */ + +/* Bit fields for USART TRIGCTRL */ +#define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */ +#define _USART_TRIGCTRL_MASK 0x00001FF0UL /**< Mask for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */ +#define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */ +#define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */ +#define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */ +#define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */ +#define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */ +#define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */ +#define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */ +#define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of */ +#define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */ +#define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */ +#define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */ +#define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of f */ +#define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */ +#define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */ +#define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */ + +/* Bit fields for USART CMD */ +#define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */ +#define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */ +#define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ +#define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */ +#define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */ +#define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ +#define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */ +#define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */ +#define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ +#define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */ +#define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */ +#define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ +#define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */ +#define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */ +#define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN (0x1UL << 4) /**< Main Mode Enable */ +#define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */ +#define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS (0x1UL << 5) /**< Main Mode Disable */ +#define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */ +#define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */ +#define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */ +#define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */ +#define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */ +#define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */ +#define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */ +#define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */ +#define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */ +#define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */ +#define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */ +#define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */ +#define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */ +#define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */ +#define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */ + +/* Bit fields for USART STATUS */ +#define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */ +#define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */ +#define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ +#define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */ +#define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */ +#define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ +#define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */ +#define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */ +#define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Main Mode */ +#define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */ +#define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */ +#define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ +#define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */ +#define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ +#define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */ +#define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */ +#define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ +#define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */ +#define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */ +#define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */ +#define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */ +#define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */ +#define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */ +#define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */ +#define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ +#define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */ +#define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */ +#define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */ +#define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */ +#define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */ +#define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */ +#define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */ +#define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */ +#define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */ +#define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */ +#define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ +#define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */ +#define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */ +#define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */ +#define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */ +#define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */ +#define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */ + +/* Bit fields for USART CLKDIV */ +#define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */ +#define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */ +#define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */ +#define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */ +#define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ +#define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */ +#define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */ +#define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */ + +/* Bit fields for USART RXDATAX */ +#define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */ +#define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */ +#define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */ +#define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */ +#define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */ +#define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */ +#define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */ +#define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */ +#define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */ +#define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */ + +/* Bit fields for USART RXDATA */ +#define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */ +#define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */ +#define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */ +#define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */ + +/* Bit fields for USART RXDOUBLEX */ +#define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */ +#define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */ +#define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */ +#define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */ +#define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */ +#define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */ +#define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */ +#define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */ +#define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */ + +/* Bit fields for USART RXDOUBLE */ +#define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */ +#define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ +#define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */ +#define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */ + +/* Bit fields for USART RXDATAXP */ +#define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */ +#define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */ +#define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */ +#define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */ +#define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */ +#define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */ +#define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */ +#define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */ + +/* Bit fields for USART RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */ +#define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */ +#define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */ +#define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */ +#define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */ +#define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */ +#define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */ +#define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */ +#define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */ +#define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */ +#define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */ + +/* Bit fields for USART TXDATAX */ +#define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */ +#define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */ +#define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */ +#define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */ +#define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */ +#define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */ +#define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */ +#define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */ +#define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */ + +/* Bit fields for USART TXDATA */ +#define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */ +#define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */ +#define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */ +#define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */ + +/* Bit fields for USART TXDOUBLEX */ +#define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */ +#define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */ +#define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */ +#define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */ +#define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */ +#define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */ +#define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */ +#define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */ +#define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */ +#define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */ +#define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */ +#define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */ +#define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */ +#define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */ +#define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */ +#define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */ + +/* Bit fields for USART TXDOUBLE */ +#define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */ +#define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ +#define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */ +#define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */ + +/* Bit fields for USART IF */ +#define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */ +#define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */ +#define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ +#define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */ +#define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */ +#define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */ +#define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */ +#define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */ +#define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */ +#define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */ +#define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ +#define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ +#define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ +#define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ +#define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */ +#define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */ +#define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */ +#define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */ +#define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */ + +/* Bit fields for USART IEN */ +#define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */ +#define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */ +#define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */ +#define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */ +#define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */ +#define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */ +#define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */ +#define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */ +#define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */ +#define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */ +#define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */ +#define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */ +#define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */ +#define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */ +#define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */ +#define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */ +#define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */ +#define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */ +#define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */ +#define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */ +#define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */ +#define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */ +#define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */ +#define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */ +#define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */ +#define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */ +#define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */ +#define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */ +#define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */ +#define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */ +#define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */ +#define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ +#define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */ +#define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */ +#define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM (0x1UL << 11) /**< Chip-Select In Main Mode Interrupt Flag */ +#define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */ +#define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */ +#define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */ +#define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */ +#define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */ +#define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Enable */ +#define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */ +#define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Enable */ +#define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */ +#define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */ +#define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Enable */ +#define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */ +#define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */ +#define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Enable */ +#define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */ +#define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */ +#define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */ +#define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */ + +/* Bit fields for USART IRCTRL */ +#define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */ +#define _USART_IRCTRL_MASK 0x0000008FUL /**< Mask for USART_IRCTRL */ +#define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */ +#define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */ +#define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */ +#define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */ +#define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */ +#define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */ +#define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */ +#define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */ +#define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */ +#define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_IRCTRL */ +#define _USART_IRCTRL_IRFILT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_DISABLE (_USART_IRCTRL_IRFILT_DISABLE << 3) /**< Shifted mode DISABLE for USART_IRCTRL */ +#define USART_IRCTRL_IRFILT_ENABLE (_USART_IRCTRL_IRFILT_ENABLE << 3) /**< Shifted mode ENABLE for USART_IRCTRL */ + +/* Bit fields for USART I2SCTRL */ +#define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */ +#define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */ +#define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */ +#define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */ +#define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */ +#define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */ +#define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */ +#define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */ +#define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */ +#define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */ +#define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */ +#define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */ +#define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */ +#define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */ +#define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */ +#define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */ +#define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */ +#define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */ +#define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */ + +/* Bit fields for USART TIMING */ +#define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */ +#define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */ +#define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */ +#define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */ +#define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */ +#define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */ +#define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */ +#define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */ +#define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */ +#define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */ +#define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */ +#define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */ +#define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */ +#define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */ +#define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */ +#define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */ +#define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */ +#define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */ + +/* Bit fields for USART CTRLX */ +#define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */ +#define _USART_CTRLX_MASK 0x8000808FUL /**< Mask for USART_CTRLX */ +#define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */ +#define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */ +#define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_DISABLE (_USART_CTRLX_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_DBGHALT_ENABLE (_USART_CTRLX_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */ +#define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */ +#define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSINV_DISABLE (_USART_CTRLX_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSINV_ENABLE (_USART_CTRLX_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */ +#define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */ +#define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CTSEN_DISABLE (_USART_CTRLX_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_CTSEN_ENABLE (_USART_CTRLX_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */ +#define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */ +#define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for USART_CTRLX */ +#define _USART_CTRLX_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RTSINV_DISABLE (_USART_CTRLX_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for USART_CTRLX */ +#define USART_CTRLX_RTSINV_ENABLE (_USART_CTRLX_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN (0x1UL << 7) /**< PRS RX Enable */ +#define _USART_CTRLX_RXPRSEN_SHIFT 7 /**< Shift value for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_MASK 0x80UL /**< Bit mask for USART_RXPRSEN */ +#define _USART_CTRLX_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_RXPRSEN_DEFAULT (_USART_CTRLX_RXPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN (0x1UL << 15) /**< PRS CLK Enable */ +#define _USART_CTRLX_CLKPRSEN_SHIFT 15 /**< Shift value for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_MASK 0x8000UL /**< Bit mask for USART_CLKPRSEN */ +#define _USART_CTRLX_CLKPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */ +#define USART_CTRLX_CLKPRSEN_DEFAULT (_USART_CTRLX_CLKPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRLX */ + +/* Bit fields for USART TIMECMP0 */ +#define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */ +#define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */ +#define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */ +#define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */ +#define _USART_TIMECMP0_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_DISABLE (_USART_TIMECMP0_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP0 */ +#define USART_TIMECMP0_RESTARTEN_ENABLE (_USART_TIMECMP0_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP0 */ + +/* Bit fields for USART TIMECMP1 */ +#define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */ +#define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */ +#define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */ +#define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */ +#define _USART_TIMECMP1_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_DISABLE (_USART_TIMECMP1_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP1 */ +#define USART_TIMECMP1_RESTARTEN_ENABLE (_USART_TIMECMP1_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP1 */ + +/* Bit fields for USART TIMECMP2 */ +#define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */ +#define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */ +#define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */ +#define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */ +#define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */ +#define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */ +#define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */ +#define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */ +#define _USART_TIMECMP2_RESTARTEN_ENABLE 0x00000001UL /**< Mode ENABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_DISABLE (_USART_TIMECMP2_RESTARTEN_DISABLE << 24) /**< Shifted mode DISABLE for USART_TIMECMP2 */ +#define USART_TIMECMP2_RESTARTEN_ENABLE (_USART_TIMECMP2_RESTARTEN_ENABLE << 24) /**< Shifted mode ENABLE for USART_TIMECMP2 */ + +/** @} End of group EFR32BG22_USART_BitFields */ +/** @} End of group EFR32BG22_USART */ +/** @} End of group Parts */ + +#endif // EFR32BG22_USART_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h index 5beb6d3..b0fd700 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22_wdog.h @@ -1,361 +1,361 @@ -/**************************************************************************//** - * @file - * @brief EFR32BG22 WDOG register and bit field definitions - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22_WDOG_H -#define EFR32BG22_WDOG_H -#define WDOG_HAS_SET_CLEAR - -/**************************************************************************//** -* @addtogroup Parts -* @{ -******************************************************************************/ -/**************************************************************************//** - * @defgroup EFR32BG22_WDOG WDOG - * @{ - * @brief EFR32BG22 WDOG Register Declaration. - *****************************************************************************/ - -/** WDOG Register Declaration. */ -typedef struct { - __IM uint32_t IPVERSION; /**< IP Version Register */ - __IOM uint32_t EN; /**< Enable Register */ - __IOM uint32_t CFG; /**< Configuration Register */ - __IOM uint32_t CMD; /**< Command Register */ - uint32_t RESERVED0[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS; /**< Status Register */ - __IOM uint32_t IF; /**< Interrupt Flag Register */ - __IOM uint32_t IEN; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK; /**< Lock Register */ - __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ - uint32_t RESERVED1[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_SET; /**< IP Version Register */ - __IOM uint32_t EN_SET; /**< Enable Register */ - __IOM uint32_t CFG_SET; /**< Configuration Register */ - __IOM uint32_t CMD_SET; /**< Command Register */ - uint32_t RESERVED2[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_SET; /**< Status Register */ - __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_SET; /**< Lock Register */ - __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ - uint32_t RESERVED3[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ - __IOM uint32_t EN_CLR; /**< Enable Register */ - __IOM uint32_t CFG_CLR; /**< Configuration Register */ - __IOM uint32_t CMD_CLR; /**< Command Register */ - uint32_t RESERVED4[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_CLR; /**< Status Register */ - __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_CLR; /**< Lock Register */ - __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ - uint32_t RESERVED5[1014U]; /**< Reserved for future use */ - __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ - __IOM uint32_t EN_TGL; /**< Enable Register */ - __IOM uint32_t CFG_TGL; /**< Configuration Register */ - __IOM uint32_t CMD_TGL; /**< Command Register */ - uint32_t RESERVED6[1U]; /**< Reserved for future use */ - __IM uint32_t STATUS_TGL; /**< Status Register */ - __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ - __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ - __IOM uint32_t LOCK_TGL; /**< Lock Register */ - __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ -} WDOG_TypeDef; -/** @} End of group EFR32BG22_WDOG */ - -/**************************************************************************//** - * @addtogroup EFR32BG22_WDOG - * @{ - * @defgroup EFR32BG22_WDOG_BitFields WDOG Bit Fields - * @{ - *****************************************************************************/ - -/* Bit fields for WDOG IPVERSION */ -#define _WDOG_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ -#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IPVERSION */ -#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ - -/* Bit fields for WDOG EN */ -#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ -#define _WDOG_EN_MASK 0x00000001UL /**< Mask for WDOG_EN */ -#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ -#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ -#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ -#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ -#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ - -/* Bit fields for WDOG CFG */ -#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ -#define _WDOG_CFG_MASK 0x730F071FUL /**< Mask for WDOG_CFG */ -#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ -#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ -#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ -#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ -#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ -#define WDOG_CFG_EM2RUN (0x1UL << 1) /**< EM2 Run */ -#define _WDOG_CFG_EM2RUN_SHIFT 1 /**< Shift value for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_MASK 0x2UL /**< Bit mask for WDOG_EM2RUN */ -#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN (0x1UL << 2) /**< EM3 Run */ -#define _WDOG_CFG_EM3RUN_SHIFT 2 /**< Shift value for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_MASK 0x4UL /**< Bit mask for WDOG_EM3RUN */ -#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK (0x1UL << 3) /**< EM4 Block */ -#define _WDOG_CFG_EM4BLOCK_SHIFT 3 /**< Shift value for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_MASK 0x8UL /**< Bit mask for WDOG_EM4BLOCK */ -#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN (0x1UL << 4) /**< Debug Mode Run */ -#define _WDOG_CFG_DEBUGRUN_SHIFT 4 /**< Shift value for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_MASK 0x10UL /**< Bit mask for WDOG_DEBUGRUN */ -#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ -#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ -#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ -#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ -#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ -#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ -#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ -#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ -#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ -#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ -#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ -#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ -#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ -#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ -#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ -#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ -#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ -#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ - -/* Bit fields for WDOG CMD */ -#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ -#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ -#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ -#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ -#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ -#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ -#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ -#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ - -/* Bit fields for WDOG STATUS */ -#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ -#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ -#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ -#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ -#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ -#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ -#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ - -/* Bit fields for WDOG IF */ -#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ -#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ -#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ -#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ -#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ -#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ -#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ -#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ - -/* Bit fields for WDOG IEN */ -#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ -#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ -#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ -#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ -#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ -#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ -#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ -#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ -#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ -#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ -#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ -#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ -#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ -#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ -#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ - -/* Bit fields for WDOG LOCK */ -#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ -#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ -#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ -#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ -#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ - -/* Bit fields for WDOG SYNCBUSY */ -#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ -#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ -#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ -#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ -#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ - -/** @} End of group EFR32BG22_WDOG_BitFields */ -/** @} End of group EFR32BG22_WDOG */ -/** @} End of group Parts */ - -#endif // EFR32BG22_WDOG_H +/**************************************************************************//** + * @file + * @brief EFR32BG22 WDOG register and bit field definitions + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22_WDOG_H +#define EFR32BG22_WDOG_H +#define WDOG_HAS_SET_CLEAR + +/**************************************************************************//** +* @addtogroup Parts +* @{ +******************************************************************************/ +/**************************************************************************//** + * @defgroup EFR32BG22_WDOG WDOG + * @{ + * @brief EFR32BG22 WDOG Register Declaration. + *****************************************************************************/ + +/** WDOG Register Declaration. */ +typedef struct { + __IM uint32_t IPVERSION; /**< IP Version Register */ + __IOM uint32_t EN; /**< Enable Register */ + __IOM uint32_t CFG; /**< Configuration Register */ + __IOM uint32_t CMD; /**< Command Register */ + uint32_t RESERVED0[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS; /**< Status Register */ + __IOM uint32_t IF; /**< Interrupt Flag Register */ + __IOM uint32_t IEN; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK; /**< Lock Register */ + __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ + uint32_t RESERVED1[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_SET; /**< IP Version Register */ + __IOM uint32_t EN_SET; /**< Enable Register */ + __IOM uint32_t CFG_SET; /**< Configuration Register */ + __IOM uint32_t CMD_SET; /**< Command Register */ + uint32_t RESERVED2[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_SET; /**< Status Register */ + __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_SET; /**< Lock Register */ + __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ + uint32_t RESERVED3[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_CLR; /**< IP Version Register */ + __IOM uint32_t EN_CLR; /**< Enable Register */ + __IOM uint32_t CFG_CLR; /**< Configuration Register */ + __IOM uint32_t CMD_CLR; /**< Command Register */ + uint32_t RESERVED4[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_CLR; /**< Status Register */ + __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_CLR; /**< Lock Register */ + __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ + uint32_t RESERVED5[1014U]; /**< Reserved for future use */ + __IM uint32_t IPVERSION_TGL; /**< IP Version Register */ + __IOM uint32_t EN_TGL; /**< Enable Register */ + __IOM uint32_t CFG_TGL; /**< Configuration Register */ + __IOM uint32_t CMD_TGL; /**< Command Register */ + uint32_t RESERVED6[1U]; /**< Reserved for future use */ + __IM uint32_t STATUS_TGL; /**< Status Register */ + __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ + __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ + __IOM uint32_t LOCK_TGL; /**< Lock Register */ + __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ +} WDOG_TypeDef; +/** @} End of group EFR32BG22_WDOG */ + +/**************************************************************************//** + * @addtogroup EFR32BG22_WDOG + * @{ + * @defgroup EFR32BG22_WDOG_BitFields WDOG Bit Fields + * @{ + *****************************************************************************/ + +/* Bit fields for WDOG IPVERSION */ +#define _WDOG_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for WDOG_IPVERSION */ +#define _WDOG_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IPVERSION */ +#define WDOG_IPVERSION_IPVERSION_DEFAULT (_WDOG_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IPVERSION */ + +/* Bit fields for WDOG EN */ +#define _WDOG_EN_RESETVALUE 0x00000000UL /**< Default value for WDOG_EN */ +#define _WDOG_EN_MASK 0x00000001UL /**< Mask for WDOG_EN */ +#define WDOG_EN_EN (0x1UL << 0) /**< Module Enable */ +#define _WDOG_EN_EN_SHIFT 0 /**< Shift value for WDOG_EN */ +#define _WDOG_EN_EN_MASK 0x1UL /**< Bit mask for WDOG_EN */ +#define _WDOG_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_EN */ +#define WDOG_EN_EN_DEFAULT (_WDOG_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_EN */ + +/* Bit fields for WDOG CFG */ +#define _WDOG_CFG_RESETVALUE 0x000F0000UL /**< Default value for WDOG_CFG */ +#define _WDOG_CFG_MASK 0x730F071FUL /**< Mask for WDOG_CFG */ +#define WDOG_CFG_CLRSRC (0x1UL << 0) /**< WDOG Clear Source */ +#define _WDOG_CFG_CLRSRC_SHIFT 0 /**< Shift value for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_MASK 0x1UL /**< Bit mask for WDOG_CLRSRC */ +#define _WDOG_CFG_CLRSRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_SW 0x00000000UL /**< Mode SW for WDOG_CFG */ +#define _WDOG_CFG_CLRSRC_PRSSRC0 0x00000001UL /**< Mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_DEFAULT (_WDOG_CFG_CLRSRC_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_SW (_WDOG_CFG_CLRSRC_SW << 0) /**< Shifted mode SW for WDOG_CFG */ +#define WDOG_CFG_CLRSRC_PRSSRC0 (_WDOG_CFG_CLRSRC_PRSSRC0 << 0) /**< Shifted mode PRSSRC0 for WDOG_CFG */ +#define WDOG_CFG_EM2RUN (0x1UL << 1) /**< EM2 Run */ +#define _WDOG_CFG_EM2RUN_SHIFT 1 /**< Shift value for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_MASK 0x2UL /**< Bit mask for WDOG_EM2RUN */ +#define _WDOG_CFG_EM2RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM2RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DEFAULT (_WDOG_CFG_EM2RUN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_DISABLE (_WDOG_CFG_EM2RUN_DISABLE << 1) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM2RUN_ENABLE (_WDOG_CFG_EM2RUN_ENABLE << 1) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN (0x1UL << 2) /**< EM3 Run */ +#define _WDOG_CFG_EM3RUN_SHIFT 2 /**< Shift value for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_MASK 0x4UL /**< Bit mask for WDOG_EM3RUN */ +#define _WDOG_CFG_EM3RUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM3RUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DEFAULT (_WDOG_CFG_EM3RUN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_DISABLE (_WDOG_CFG_EM3RUN_DISABLE << 2) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM3RUN_ENABLE (_WDOG_CFG_EM3RUN_ENABLE << 2) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK (0x1UL << 3) /**< EM4 Block */ +#define _WDOG_CFG_EM4BLOCK_SHIFT 3 /**< Shift value for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_MASK 0x8UL /**< Bit mask for WDOG_EM4BLOCK */ +#define _WDOG_CFG_EM4BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_EM4BLOCK_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DEFAULT (_WDOG_CFG_EM4BLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_DISABLE (_WDOG_CFG_EM4BLOCK_DISABLE << 3) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_EM4BLOCK_ENABLE (_WDOG_CFG_EM4BLOCK_ENABLE << 3) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN (0x1UL << 4) /**< Debug Mode Run */ +#define _WDOG_CFG_DEBUGRUN_SHIFT 4 /**< Shift value for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_MASK 0x10UL /**< Bit mask for WDOG_DEBUGRUN */ +#define _WDOG_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for WDOG_CFG */ +#define _WDOG_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DEFAULT (_WDOG_CFG_DEBUGRUN_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_DISABLE (_WDOG_CFG_DEBUGRUN_DISABLE << 4) /**< Shifted mode DISABLE for WDOG_CFG */ +#define WDOG_CFG_DEBUGRUN_ENABLE (_WDOG_CFG_DEBUGRUN_ENABLE << 4) /**< Shifted mode ENABLE for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS (0x1UL << 8) /**< WDOG Reset Disable */ +#define _WDOG_CFG_WDOGRSTDIS_SHIFT 8 /**< Shift value for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_MASK 0x100UL /**< Bit mask for WDOG_WDOGRSTDIS */ +#define _WDOG_CFG_WDOGRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_EN 0x00000000UL /**< Mode EN for WDOG_CFG */ +#define _WDOG_CFG_WDOGRSTDIS_DIS 0x00000001UL /**< Mode DIS for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DEFAULT (_WDOG_CFG_WDOGRSTDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_EN (_WDOG_CFG_WDOGRSTDIS_EN << 8) /**< Shifted mode EN for WDOG_CFG */ +#define WDOG_CFG_WDOGRSTDIS_DIS (_WDOG_CFG_WDOGRSTDIS_DIS << 8) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN (0x1UL << 9) /**< PRS Src0 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS0MISSRSTEN_SHIFT 9 /**< Shift value for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_MASK 0x200UL /**< Bit mask for WDOG_PRS0MISSRSTEN */ +#define _WDOG_CFG_PRS0MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS0MISSRSTEN_DEFAULT (_WDOG_CFG_PRS0MISSRSTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN (0x1UL << 10) /**< PRS Src1 Missing Event WDOG Reset */ +#define _WDOG_CFG_PRS1MISSRSTEN_SHIFT 10 /**< Shift value for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_MASK 0x400UL /**< Bit mask for WDOG_PRS1MISSRSTEN */ +#define _WDOG_CFG_PRS1MISSRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PRS1MISSRSTEN_DEFAULT (_WDOG_CFG_PRS1MISSRSTEN_DEFAULT << 10) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SHIFT 16 /**< Shift value for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_MASK 0xF0000UL /**< Bit mask for WDOG_PERSEL */ +#define _WDOG_CFG_PERSEL_DEFAULT 0x0000000FUL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL0 0x00000000UL /**< Mode SEL0 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL8 0x00000008UL /**< Mode SEL8 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL9 0x00000009UL /**< Mode SEL9 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL10 0x0000000AUL /**< Mode SEL10 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL11 0x0000000BUL /**< Mode SEL11 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL12 0x0000000CUL /**< Mode SEL12 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL13 0x0000000DUL /**< Mode SEL13 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL14 0x0000000EUL /**< Mode SEL14 for WDOG_CFG */ +#define _WDOG_CFG_PERSEL_SEL15 0x0000000FUL /**< Mode SEL15 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_DEFAULT (_WDOG_CFG_PERSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL0 (_WDOG_CFG_PERSEL_SEL0 << 16) /**< Shifted mode SEL0 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL1 (_WDOG_CFG_PERSEL_SEL1 << 16) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL2 (_WDOG_CFG_PERSEL_SEL2 << 16) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL3 (_WDOG_CFG_PERSEL_SEL3 << 16) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL4 (_WDOG_CFG_PERSEL_SEL4 << 16) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL5 (_WDOG_CFG_PERSEL_SEL5 << 16) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL6 (_WDOG_CFG_PERSEL_SEL6 << 16) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL7 (_WDOG_CFG_PERSEL_SEL7 << 16) /**< Shifted mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL8 (_WDOG_CFG_PERSEL_SEL8 << 16) /**< Shifted mode SEL8 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL9 (_WDOG_CFG_PERSEL_SEL9 << 16) /**< Shifted mode SEL9 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL10 (_WDOG_CFG_PERSEL_SEL10 << 16) /**< Shifted mode SEL10 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL11 (_WDOG_CFG_PERSEL_SEL11 << 16) /**< Shifted mode SEL11 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL12 (_WDOG_CFG_PERSEL_SEL12 << 16) /**< Shifted mode SEL12 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL13 (_WDOG_CFG_PERSEL_SEL13 << 16) /**< Shifted mode SEL13 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL14 (_WDOG_CFG_PERSEL_SEL14 << 16) /**< Shifted mode SEL14 for WDOG_CFG */ +#define WDOG_CFG_PERSEL_SEL15 (_WDOG_CFG_PERSEL_SEL15 << 16) /**< Shifted mode SEL15 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SHIFT 24 /**< Shift value for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_MASK 0x3000000UL /**< Bit mask for WDOG_WARNSEL */ +#define _WDOG_CFG_WARNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WARNSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DEFAULT (_WDOG_CFG_WARNSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_DIS (_WDOG_CFG_WARNSEL_DIS << 24) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL1 (_WDOG_CFG_WARNSEL_SEL1 << 24) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL2 (_WDOG_CFG_WARNSEL_SEL2 << 24) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WARNSEL_SEL3 (_WDOG_CFG_WARNSEL_SEL3 << 24) /**< Shifted mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SHIFT 28 /**< Shift value for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_MASK 0x70000000UL /**< Bit mask for WDOG_WINSEL */ +#define _WDOG_CFG_WINSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_DIS 0x00000000UL /**< Mode DIS for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL1 0x00000001UL /**< Mode SEL1 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL2 0x00000002UL /**< Mode SEL2 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL3 0x00000003UL /**< Mode SEL3 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL4 0x00000004UL /**< Mode SEL4 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL5 0x00000005UL /**< Mode SEL5 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL6 0x00000006UL /**< Mode SEL6 for WDOG_CFG */ +#define _WDOG_CFG_WINSEL_SEL7 0x00000007UL /**< Mode SEL7 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DEFAULT (_WDOG_CFG_WINSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for WDOG_CFG */ +#define WDOG_CFG_WINSEL_DIS (_WDOG_CFG_WINSEL_DIS << 28) /**< Shifted mode DIS for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL1 (_WDOG_CFG_WINSEL_SEL1 << 28) /**< Shifted mode SEL1 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL2 (_WDOG_CFG_WINSEL_SEL2 << 28) /**< Shifted mode SEL2 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL3 (_WDOG_CFG_WINSEL_SEL3 << 28) /**< Shifted mode SEL3 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL4 (_WDOG_CFG_WINSEL_SEL4 << 28) /**< Shifted mode SEL4 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL5 (_WDOG_CFG_WINSEL_SEL5 << 28) /**< Shifted mode SEL5 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL6 (_WDOG_CFG_WINSEL_SEL6 << 28) /**< Shifted mode SEL6 for WDOG_CFG */ +#define WDOG_CFG_WINSEL_SEL7 (_WDOG_CFG_WINSEL_SEL7 << 28) /**< Shifted mode SEL7 for WDOG_CFG */ + +/* Bit fields for WDOG CMD */ +#define _WDOG_CMD_RESETVALUE 0x00000000UL /**< Default value for WDOG_CMD */ +#define _WDOG_CMD_MASK 0x00000001UL /**< Mask for WDOG_CMD */ +#define WDOG_CMD_CLEAR (0x1UL << 0) /**< WDOG Timer Clear */ +#define _WDOG_CMD_CLEAR_SHIFT 0 /**< Shift value for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_MASK 0x1UL /**< Bit mask for WDOG_CLEAR */ +#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /**< Mode UNCHANGED for WDOG_CMD */ +#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /**< Mode CLEARED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_CMD */ +#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /**< Shifted mode UNCHANGED for WDOG_CMD */ +#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /**< Shifted mode CLEARED for WDOG_CMD */ + +/* Bit fields for WDOG STATUS */ +#define _WDOG_STATUS_RESETVALUE 0x00000000UL /**< Default value for WDOG_STATUS */ +#define _WDOG_STATUS_MASK 0x80000000UL /**< Mask for WDOG_STATUS */ +#define WDOG_STATUS_LOCK (0x1UL << 31) /**< WDOG Configuration Lock Status */ +#define _WDOG_STATUS_LOCK_SHIFT 31 /**< Shift value for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for WDOG_LOCK */ +#define _WDOG_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for WDOG_STATUS */ +#define _WDOG_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_DEFAULT (_WDOG_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_UNLOCKED (_WDOG_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for WDOG_STATUS */ +#define WDOG_STATUS_LOCK_LOCKED (_WDOG_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for WDOG_STATUS */ + +/* Bit fields for WDOG IF */ +#define _WDOG_IF_RESETVALUE 0x00000000UL /**< Default value for WDOG_IF */ +#define _WDOG_IF_MASK 0x0000001FUL /**< Mask for WDOG_IF */ +#define WDOG_IF_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Flag */ +#define _WDOG_IF_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IF_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IF_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_TOUT_DEFAULT (_WDOG_IF_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Flag */ +#define _WDOG_IF_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IF_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IF_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WARN_DEFAULT (_WDOG_IF_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN (0x1UL << 2) /**< WDOG Window Interrupt Flag */ +#define _WDOG_IF_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IF_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IF_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_WIN_DEFAULT (_WDOG_IF_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IF_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM0_DEFAULT (_WDOG_IF_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Flag */ +#define _WDOG_IF_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IF_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IF */ +#define WDOG_IF_PEM1_DEFAULT (_WDOG_IF_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IF */ + +/* Bit fields for WDOG IEN */ +#define _WDOG_IEN_RESETVALUE 0x00000000UL /**< Default value for WDOG_IEN */ +#define _WDOG_IEN_MASK 0x0000001FUL /**< Mask for WDOG_IEN */ +#define WDOG_IEN_TOUT (0x1UL << 0) /**< WDOG Timeout Interrupt Enable */ +#define _WDOG_IEN_TOUT_SHIFT 0 /**< Shift value for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_MASK 0x1UL /**< Bit mask for WDOG_TOUT */ +#define _WDOG_IEN_TOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_TOUT_DEFAULT (_WDOG_IEN_TOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN (0x1UL << 1) /**< WDOG Warning Timeout Interrupt Enable */ +#define _WDOG_IEN_WARN_SHIFT 1 /**< Shift value for WDOG_WARN */ +#define _WDOG_IEN_WARN_MASK 0x2UL /**< Bit mask for WDOG_WARN */ +#define _WDOG_IEN_WARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WARN_DEFAULT (_WDOG_IEN_WARN_DEFAULT << 1) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN (0x1UL << 2) /**< WDOG Window Interrupt Enable */ +#define _WDOG_IEN_WIN_SHIFT 2 /**< Shift value for WDOG_WIN */ +#define _WDOG_IEN_WIN_MASK 0x4UL /**< Bit mask for WDOG_WIN */ +#define _WDOG_IEN_WIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_WIN_DEFAULT (_WDOG_IEN_WIN_DEFAULT << 2) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0 (0x1UL << 3) /**< PRS Src0 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM0_SHIFT 3 /**< Shift value for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_MASK 0x8UL /**< Bit mask for WDOG_PEM0 */ +#define _WDOG_IEN_PEM0_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM0_DEFAULT (_WDOG_IEN_PEM0_DEFAULT << 3) /**< Shifted mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1 (0x1UL << 4) /**< PRS Src1 Event Missing Interrupt Enable */ +#define _WDOG_IEN_PEM1_SHIFT 4 /**< Shift value for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_MASK 0x10UL /**< Bit mask for WDOG_PEM1 */ +#define _WDOG_IEN_PEM1_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_IEN */ +#define WDOG_IEN_PEM1_DEFAULT (_WDOG_IEN_PEM1_DEFAULT << 4) /**< Shifted mode DEFAULT for WDOG_IEN */ + +/* Bit fields for WDOG LOCK */ +#define _WDOG_LOCK_RESETVALUE 0x0000ABE8UL /**< Default value for WDOG_LOCK */ +#define _WDOG_LOCK_MASK 0x0000FFFFUL /**< Mask for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for WDOG_LOCKKEY */ +#define _WDOG_LOCK_LOCKKEY_DEFAULT 0x0000ABE8UL /**< Mode DEFAULT for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for WDOG_LOCK */ +#define _WDOG_LOCK_LOCKKEY_UNLOCK 0x0000ABE8UL /**< Mode UNLOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_DEFAULT (_WDOG_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_LOCK (_WDOG_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for WDOG_LOCK */ +#define WDOG_LOCK_LOCKKEY_UNLOCK (_WDOG_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for WDOG_LOCK */ + +/* Bit fields for WDOG SYNCBUSY */ +#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for WDOG_SYNCBUSY */ +#define _WDOG_SYNCBUSY_MASK 0x00000001UL /**< Mask for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (0x1UL << 0) /**< Sync Busy for Cmd Register */ +#define _WDOG_SYNCBUSY_CMD_SHIFT 0 /**< Shift value for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_MASK 0x1UL /**< Bit mask for WDOG_CMD */ +#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 0) /**< Shifted mode DEFAULT for WDOG_SYNCBUSY */ + +/** @} End of group EFR32BG22_WDOG_BitFields */ +/** @} End of group EFR32BG22_WDOG */ +/** @} End of group Parts */ + +#endif // EFR32BG22_WDOG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h index c155f31..ef9c3b4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/efr32bg22c224f512im40.h @@ -1,1340 +1,1340 @@ -/**************************************************************************//** - * @file - * @brief CMSIS Cortex-M Peripheral Access Layer Header File - * for EFR32BG22C224F512IM40 - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ -#ifndef EFR32BG22C224F512IM40_H -#define EFR32BG22C224F512IM40_H - -#ifdef __cplusplus -extern "C" { -#endif - -/**************************************************************************//** - * @addtogroup Parts - * @{ - *****************************************************************************/ - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40 EFR32BG22C224F512IM40 - * @{ - *****************************************************************************/ - -/** Interrupt Number Definition */ -typedef enum IRQn{ - /****** Cortex-M Processor Exceptions Numbers ******************************************/ - NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ - - /****** EFR32BG22 Peripheral Interrupt Numbers ******************************************/ - - CRYPTOACC_IRQn = 0, /*!< 0 EFR32 CRYPTOACC Interrupt */ - TRNG_IRQn = 1, /*!< 1 EFR32 TRNG Interrupt */ - PKE_IRQn = 2, /*!< 2 EFR32 PKE Interrupt */ - SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ - SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ - SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ - EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ - TIMER0_IRQn = 7, /*!< 7 EFR32 TIMER0 Interrupt */ - TIMER1_IRQn = 8, /*!< 8 EFR32 TIMER1 Interrupt */ - TIMER2_IRQn = 9, /*!< 9 EFR32 TIMER2 Interrupt */ - TIMER3_IRQn = 10, /*!< 10 EFR32 TIMER3 Interrupt */ - TIMER4_IRQn = 11, /*!< 11 EFR32 TIMER4 Interrupt */ - RTCC_IRQn = 12, /*!< 12 EFR32 RTCC Interrupt */ - USART0_RX_IRQn = 13, /*!< 13 EFR32 USART0_RX Interrupt */ - USART0_TX_IRQn = 14, /*!< 14 EFR32 USART0_TX Interrupt */ - USART1_RX_IRQn = 15, /*!< 15 EFR32 USART1_RX Interrupt */ - USART1_TX_IRQn = 16, /*!< 16 EFR32 USART1_TX Interrupt */ - ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ - BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ - LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ - SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ - LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ - LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ - LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ - ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ - GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ - GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ - I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ - I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ - EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ - EMUSE_IRQn = 30, /*!< 30 EFR32 EMUSE Interrupt */ - AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ - BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ - FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ - FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ - MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ - PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ - RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ - RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ - RDMAILBOX_IRQn = 39, /*!< 39 EFR32 RDMAILBOX Interrupt */ - RFSENSE_IRQn = 40, /*!< 40 EFR32 RFSENSE Interrupt */ - PRORTC_IRQn = 41, /*!< 41 EFR32 PRORTC Interrupt */ - SYNTH_IRQn = 42, /*!< 42 EFR32 SYNTH Interrupt */ - WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ - HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ - HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ - CMU_IRQn = 46, /*!< 46 EFR32 CMU Interrupt */ - AES_IRQn = 47, /*!< 47 EFR32 AES Interrupt */ - IADC_IRQn = 48, /*!< 48 EFR32 IADC Interrupt */ - MSC_IRQn = 49, /*!< 49 EFR32 MSC Interrupt */ - DPLL0_IRQn = 50, /*!< 50 EFR32 DPLL0 Interrupt */ - PDM_IRQn = 51, /*!< 51 EFR32 PDM Interrupt */ - SW0_IRQn = 52, /*!< 52 EFR32 SW0 Interrupt */ - SW1_IRQn = 53, /*!< 53 EFR32 SW1 Interrupt */ - SW2_IRQn = 54, /*!< 54 EFR32 SW2 Interrupt */ - SW3_IRQn = 55, /*!< 55 EFR32 SW3 Interrupt */ - KERNEL0_IRQn = 56, /*!< 56 EFR32 KERNEL0 Interrupt */ - KERNEL1_IRQn = 57, /*!< 57 EFR32 KERNEL1 Interrupt */ - M33CTI0_IRQn = 58, /*!< 58 EFR32 M33CTI0 Interrupt */ - M33CTI1_IRQn = 59, /*!< 59 EFR32 M33CTI1 Interrupt */ - EMUEFP_IRQn = 60, /*!< 60 EFR32 EMUEFP Interrupt */ - DCDC_IRQn = 61, /*!< 61 EFR32 DCDC Interrupt */ - EUART0_RX_IRQn = 62, /*!< 62 EFR32 EUART0_RX Interrupt */ - EUART0_TX_IRQn = 63, /*!< 63 EFR32 EUART0_TX Interrupt */ -} IRQn_Type; - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40_Core EFR32BG22C224F512IM40 Core - * @{ - * @brief Processor and Core Peripheral Section - *****************************************************************************/ - -#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ -#define __DSP_PRESENT 1U /**< Presence of DSP */ -#define __FPU_PRESENT 1U /**< Presence of FPU */ -#define __MPU_PRESENT 1U /**< Presence of MPU */ -#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ -#define __TZ_PRESENT 1U /**< Presence of TrustZone */ -#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ -#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ -#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ - -/** @} End of group EFR32BG22C224F512IM40_Core */ - -/**************************************************************************//** -* @defgroup EFR32BG22C224F512IM40_Part EFR32BG22C224F512IM40 Part -* @{ -******************************************************************************/ - -/** Part number */ - -/* If part number is not defined as compiler option, define it */ -#if !defined(EFR32BG22C224F512IM40) -#define EFR32BG22C224F512IM40 1 /**< FULL Part */ -#endif - -/** Configure part number */ -#define PART_NUMBER "EFR32BG22C224F512IM40" /**< Part Number */ - -/** Family / Line / Series / Config */ -#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ -#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ -#define _EFR_DEVICE 1 /** Product Line Identifier */ -#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ -#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ -#define _SILICON_LABS_32B_SERIES_2_CONFIG_2 /** Product Config Identifier */ -#define _SILICON_LABS_32B_SERIES_2_CONFIG 2 /** Product Config Identifier */ -#define _SILICON_LABS_GECKO_INTERNAL_SDID 205 /** Silicon Labs internal use only */ -#define _SILICON_LABS_GECKO_INTERNAL_SDID_205 /** Silicon Labs internal use only */ -#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ -#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ -#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ -#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_ROT /** Security feature set */ -#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ -#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ -#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ -#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ -#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ -#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ -#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ -#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ -#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 6 /** Radio 2G4HZ HP PA output power */ -#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ -#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ -#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ -#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ - -/** Memory Base addresses and limits */ -#define FLASH_MEM_BASE (0x00000000UL) /** FLASH_MEM base address */ -#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ -#define FLASH_MEM_END (0x0007FFFFUL) /** FLASH_MEM end address */ -#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ -#define MSC_FLASH_MEM_BASE (0x00000000UL) /** MSC_FLASH_MEM base address */ -#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ -#define MSC_FLASH_MEM_END (0x0007FFFFUL) /** MSC_FLASH_MEM end address */ -#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ -#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ -#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ -#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ -#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ -#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ -#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ -#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ -#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ -#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ -#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ -#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ -#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ -#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE0E000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ -#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ -#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE0E5FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ -#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ -#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ -#define DMEM_RAM0_RAM_MEM_SIZE (0x00008000UL) /** DMEM_RAM0_RAM_MEM available address space */ -#define DMEM_RAM0_RAM_MEM_END (0x20007FFFUL) /** DMEM_RAM0_RAM_MEM end address */ -#define DMEM_RAM0_RAM_MEM_BITS (0x10UL) /** DMEM_RAM0_RAM_MEM used bits */ -#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ -#define RAM_MEM_SIZE (0x00008000UL) /** RAM_MEM available address space */ -#define RAM_MEM_END (0x20007FFFUL) /** RAM_MEM end address */ -#define RAM_MEM_BITS (0x10UL) /** RAM_MEM used bits */ -#define CRYPTOACC_RNGOUT_FIFO_S_MEM_BASE (0x4C024000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM base address */ -#define CRYPTOACC_RNGOUT_FIFO_S_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM available address space */ -#define CRYPTOACC_RNGOUT_FIFO_S_MEM_END (0x4C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM end address */ -#define CRYPTOACC_RNGOUT_FIFO_S_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM used bits */ -#define CRYPTOACC_PKRAM_MAIN_S_MEM_BASE (0x4C028000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM base address */ -#define CRYPTOACC_PKRAM_MAIN_S_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM available address space */ -#define CRYPTOACC_PKRAM_MAIN_S_MEM_END (0x4C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM end address */ -#define CRYPTOACC_PKRAM_MAIN_S_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM used bits */ -#define CRYPTOACC_RNGOUT_FIFO_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM base address */ -#define CRYPTOACC_RNGOUT_FIFO_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM available address space */ -#define CRYPTOACC_RNGOUT_FIFO_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM end address */ -#define CRYPTOACC_RNGOUT_FIFO_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM used bits */ -#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM base address */ -#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM available address space */ -#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM end address */ -#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM used bits */ -#define CRYPTOACC_PKRAM_MAIN_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_MEM base address */ -#define CRYPTOACC_PKRAM_MAIN_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_MEM available address space */ -#define CRYPTOACC_PKRAM_MAIN_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_MEM end address */ -#define CRYPTOACC_PKRAM_MAIN_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_MEM used bits */ -#define CRYPTOACC_PKRAM_MAIN_NS_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM base address */ -#define CRYPTOACC_PKRAM_MAIN_NS_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM available address space */ -#define CRYPTOACC_PKRAM_MAIN_NS_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM end address */ -#define CRYPTOACC_PKRAM_MAIN_NS_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM used bits */ -#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ -#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ -#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ -#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ -#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ -#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ -#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ -#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ -#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ -#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ -#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ -#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ -#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ -#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ -#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ -#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ -#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ -#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ -#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ -#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ -#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ -#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ -#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ -#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ - -/** Flash and SRAM limits for EFR32BG22C224F512IM40 */ -#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ -#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ -#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ -#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ -#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */ -#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ -#define EXT_IRQ_COUNT 64 /**< Number of External (NVIC) interrupts */ - -/* GPIO Avalibility Info */ -#define GPIO_PA_INDEX 0U /**< Index of port PA */ -#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ -#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ -#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ -#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ -#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ -#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ -#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ -#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ -#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ -#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ -#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ -#define GPIO_PB_INDEX 1U /**< Index of port PB */ -#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ -#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ -#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ -#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ -#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ -#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ -#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ -#define GPIO_PC_INDEX 2U /**< Index of port PC */ -#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ -#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ -#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ -#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ -#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ -#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ -#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ -#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ -#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ -#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ -#define GPIO_PD_INDEX 3U /**< Index of port PD */ -#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ -#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ -#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ -#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ -#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ -#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ - -/* Fixed Resource Locations */ -#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ -#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ -#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ -#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ -#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ -#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ -#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ -#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ -#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ -#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ -#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ -#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ -#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ -#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ -#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ -#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ -#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ -#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ -#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ -#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ -#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ -#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ -#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ -#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ -#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ -#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ -#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ -#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ -#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ -#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ -#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ -#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ -#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ -#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ -#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ -#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ -#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ -#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ - -/* Part number capabilities */ -#define BURAM_PRESENT /** BURAM is available in this part */ -#define BURAM_COUNT 1 /** 1 BURAMs available */ -#define BURTC_PRESENT /** BURTC is available in this part */ -#define BURTC_COUNT 1 /** 1 BURTCs available */ -#define CMU_PRESENT /** CMU is available in this part */ -#define CMU_COUNT 1 /** 1 CMUs available */ -#define CRYPTOACC_PRESENT /** CRYPTOACC is available in this part */ -#define CRYPTOACC_COUNT 1 /** 1 CRYPTOACCs available */ -#define DCDC_PRESENT /** DCDC is available in this part */ -#define DCDC_COUNT 1 /** 1 DCDCs available */ -#define DPLL_PRESENT /** DPLL is available in this part */ -#define DPLL_COUNT 1 /** 1 DPLLs available */ -#define EMU_PRESENT /** EMU is available in this part */ -#define EMU_COUNT 1 /** 1 EMUs available */ -#define EUART_PRESENT /** EUART is available in this part */ -#define EUART_COUNT 1 /** 1 EUARTs available */ -#define FSRCO_PRESENT /** FSRCO is available in this part */ -#define FSRCO_COUNT 1 /** 1 FSRCOs available */ -#define GPCRC_PRESENT /** GPCRC is available in this part */ -#define GPCRC_COUNT 1 /** 1 GPCRCs available */ -#define GPIO_PRESENT /** GPIO is available in this part */ -#define GPIO_COUNT 1 /** 1 GPIOs available */ -#define HFRCO_PRESENT /** HFRCO is available in this part */ -#define HFRCO_COUNT 1 /** 1 HFRCOs available */ -#define HFXO_PRESENT /** HFXO is available in this part */ -#define HFXO_COUNT 1 /** 1 HFXOs available */ -#define I2C_PRESENT /** I2C is available in this part */ -#define I2C_COUNT 2 /** 2 I2Cs available */ -#define IADC_PRESENT /** IADC is available in this part */ -#define IADC_COUNT 1 /** 1 IADCs available */ -#define ICACHE_PRESENT /** ICACHE is available in this part */ -#define ICACHE_COUNT 1 /** 1 ICACHEs available */ -#define LDMA_PRESENT /** LDMA is available in this part */ -#define LDMA_COUNT 1 /** 1 LDMAs available */ -#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ -#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ -#define LETIMER_PRESENT /** LETIMER is available in this part */ -#define LETIMER_COUNT 1 /** 1 LETIMERs available */ -#define LFRCO_PRESENT /** LFRCO is available in this part */ -#define LFRCO_COUNT 1 /** 1 LFRCOs available */ -#define LFXO_PRESENT /** LFXO is available in this part */ -#define LFXO_COUNT 1 /** 1 LFXOs available */ -#define MSC_PRESENT /** MSC is available in this part */ -#define MSC_COUNT 1 /** 1 MSCs available */ -#define PDM_PRESENT /** PDM is available in this part */ -#define PDM_COUNT 1 /** 1 PDMs available */ -#define PRORTC_PRESENT /** PRORTC is available in this part */ -#define PRORTC_COUNT 1 /** 1 PRORTCs available */ -#define PRS_PRESENT /** PRS is available in this part */ -#define PRS_COUNT 1 /** 1 PRSs available */ -#define RADIOAES_PRESENT /** RADIOAES is available in this part */ -#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ -#define RTCC_PRESENT /** RTCC is available in this part */ -#define RTCC_COUNT 1 /** 1 RTCCs available */ -#define SMU_PRESENT /** SMU is available in this part */ -#define SMU_COUNT 1 /** 1 SMUs available */ -#define SYSCFG_PRESENT /** SYSCFG is available in this part */ -#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ -#define TIMER_PRESENT /** TIMER is available in this part */ -#define TIMER_COUNT 5 /** 5 TIMERs available */ -#define ULFRCO_PRESENT /** ULFRCO is available in this part */ -#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ -#define USART_PRESENT /** USART is available in this part */ -#define USART_COUNT 2 /** 2 USARTs available */ -#define WDOG_PRESENT /** WDOG is available in this part */ -#define WDOG_COUNT 1 /** 1 WDOGs available */ -#define DEVINFO_PRESENT /** DEVINFO is available in this part */ -#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ - -/* Include standard ARM headers for the core */ -#include "core_cm33.h" /* Core Header File */ -#include "system_efr32bg22.h" /* System Header File */ - -/** @} End of group EFR32BG22C224F512IM40_Part */ - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40_Peripheral_TypeDefs EFR32BG22C224F512IM40 Peripheral TypeDefs - * @{ - * @brief Device Specific Peripheral Register Structures - *****************************************************************************/ -#include "efr32bg22_emu.h" -#include "efr32bg22_cmu.h" -#include "efr32bg22_hfxo.h" -#include "efr32bg22_hfrco.h" -#include "efr32bg22_fsrco.h" -#include "efr32bg22_dpll.h" -#include "efr32bg22_lfxo.h" -#include "efr32bg22_lfrco.h" -#include "efr32bg22_ulfrco.h" -#include "efr32bg22_msc.h" -#include "efr32bg22_icache.h" -#include "efr32bg22_prs.h" -#include "efr32bg22_gpio.h" -#include "efr32bg22_ldma.h" -#include "efr32bg22_ldmaxbar.h" -#include "efr32bg22_timer.h" -#include "efr32bg22_usart.h" -#include "efr32bg22_burtc.h" -#include "efr32bg22_i2c.h" -#include "efr32bg22_syscfg.h" -#include "efr32bg22_buram.h" -#include "efr32bg22_gpcrc.h" -#include "efr32bg22_dcdc.h" -#include "efr32bg22_pdm.h" -#include "efr32bg22_aes.h" -#include "efr32bg22_smu.h" -#include "efr32bg22_rtcc.h" -#include "efr32bg22_letimer.h" -#include "efr32bg22_iadc.h" -#include "efr32bg22_wdog.h" -#include "efr32bg22_eusart.h" -#include "efr32bg22_cryptoacc.h" -#include "efr32bg22_devinfo.h" - -/* Custom headers for LDMAXBAR and PRS mappings */ -#include "efr32bg22_prs_signals.h" -#include "efr32bg22_dma_descriptor.h" -#include "efr32bg22_ldmaxbar_defines.h" - -/** @} End of group EFR32BG22C224F512IM40_Peripheral_TypeDefs */ - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40_Peripheral_Base EFR32BG22C224F512IM40 Peripheral Memory Map - * @{ - *****************************************************************************/ - -#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ -#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ -#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ -#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ -#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ -#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ -#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ -#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ -#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ -#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ -#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ -#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ -#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ -#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ -#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ -#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ -#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ -#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ -#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ -#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ -#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ -#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ -#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ -#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ -#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ -#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ -#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ -#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ -#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ -#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ -#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ -#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ -#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ -#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ -#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ -#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ -#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ -#define WDOG0_S_BASE (0x4A018000UL) /* WDOG0_S base address */ -#define EUART0_S_BASE (0x4A030000UL) /* EUART0_S base address */ -#define CRYPTOACC_S_BASE (0x4C020000UL) /* CRYPTOACC_S base address */ -#define CRYPTOACC_S_RNGCTRL_BASE (0x4C021000UL) /* CRYPTOACC_S_RNGCTRL base address */ -#define CRYPTOACC_S_PKCTRL_BASE (0x4C022000UL) /* CRYPTOACC_S_PKCTRL base address */ -#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ -#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ -#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ -#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ -#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ -#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ -#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ -#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ -#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ -#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ -#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ -#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ -#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ -#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ -#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ -#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ -#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ -#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ -#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ -#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ -#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ -#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ -#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ -#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ -#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ -#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ -#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ -#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ -#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ -#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ -#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ -#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ -#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ -#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ -#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ -#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ -#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ -#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ -#define WDOG0_NS_BASE (0x5A018000UL) /* WDOG0_NS base address */ -#define EUART0_NS_BASE (0x5A030000UL) /* EUART0_NS base address */ -#define CRYPTOACC_NS_BASE (0x5C020000UL) /* CRYPTOACC_NS base address */ -#define CRYPTOACC_NS_RNGCTRL_BASE (0x5C021000UL) /* CRYPTOACC_NS_RNGCTRL base address */ -#define CRYPTOACC_NS_PKCTRL_BASE (0x5C022000UL) /* CRYPTOACC_NS_PKCTRL base address */ -#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" - -#endif -#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) -#include "sl_trustzone_secure_config.h" - -#endif - -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) -#define EMU_BASE (EMU_S_BASE) /* EMU base address */ -#else -#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) -#define CMU_BASE (CMU_S_BASE) /* CMU base address */ -#else -#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) -#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ -#else -#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) -#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ -#else -#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) -#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ -#else -#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) -#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ -#else -#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) -#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ -#else -#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) -#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ -#else -#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) -#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ -#else -#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) -#define MSC_BASE (MSC_S_BASE) /* MSC base address */ -#else -#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) -#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ -#else -#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) -#define PRS_BASE (PRS_S_BASE) /* PRS base address */ -#else -#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) -#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ -#else -#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) -#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ -#else -#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) -#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ -#else -#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) -#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ -#else -#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) -#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ -#else -#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) -#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ -#else -#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) -#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ -#else -#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) -#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ -#else -#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) -#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ -#else -#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) -#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ -#else -#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) -#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ -#else -#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) -#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ -#else -#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) -#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ -#else -#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) -#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ -#else -#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) -#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ -#else -#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) -#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ -#else -#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) -#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ -#else -#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) -#define PDM_BASE (PDM_S_BASE) /* PDM base address */ -#else -#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) -#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ -#else -#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) -#define SMU_BASE (SMU_S_BASE) /* SMU base address */ -#else -#define SMU_BASE (SMU_S_BASE) /* SMU base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) -#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ -#else -#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) -#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ -#else -#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) -#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ -#else -#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) -#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ -#else -#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) -#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ -#else -#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) -#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ -#else -#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) -#define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ -#else -#define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_EUART0_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) -#define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ -#else -#define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) -#define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ -#else -#define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) -#define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ -#else -#define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) -#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ -#else -#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ -#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S - -#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ -/** @} End of group EFR32BG22C224F512IM40_Peripheral_Base */ - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40_Peripheral_Declaration EFR32BG22C224F512IM40 Peripheral Declarations Map - * @{ - *****************************************************************************/ - -#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ -#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ -#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ -#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ -#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ -#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ -#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ -#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ -#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ -#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ -#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ -#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ -#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ -#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ -#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ -#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ -#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ -#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ -#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ -#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ -#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ -#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ -#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ -#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ -#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ -#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ -#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ -#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ -#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ -#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ -#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ -#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ -#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ -#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ -#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ -#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ -#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ -#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ -#define EUART0_S ((EUSART_TypeDef *) EUART0_S_BASE) /**< EUART0_S base pointer */ -#define CRYPTOACC_S ((CRYPTOACC_TypeDef *) CRYPTOACC_S_BASE) /**< CRYPTOACC_S base pointer */ -#define CRYPTOACC_S_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_S_RNGCTRL_BASE) /**< CRYPTOACC_S_RNGCTRL base pointer */ -#define CRYPTOACC_S_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_S_PKCTRL_BASE) /**< CRYPTOACC_S_PKCTRL base pointer */ -#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ -#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ -#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ -#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ -#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ -#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ -#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ -#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ -#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ -#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ -#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ -#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ -#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ -#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ -#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ -#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ -#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ -#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ -#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ -#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ -#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ -#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ -#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ -#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ -#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ -#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ -#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ -#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ -#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ -#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ -#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ -#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ -#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ -#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ -#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ -#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ -#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ -#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ -#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ -#define EUART0_NS ((EUSART_TypeDef *) EUART0_NS_BASE) /**< EUART0_NS base pointer */ -#define CRYPTOACC_NS ((CRYPTOACC_TypeDef *) CRYPTOACC_NS_BASE) /**< CRYPTOACC_NS base pointer */ -#define CRYPTOACC_NS_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_NS_RNGCTRL_BASE) /**< CRYPTOACC_NS_RNGCTRL base pointer */ -#define CRYPTOACC_NS_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_NS_PKCTRL_BASE) /**< CRYPTOACC_NS_PKCTRL base pointer */ -#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ -#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ -#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ -#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ -#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ -#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ -#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ -#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ -#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ -#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ -#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ -#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ -#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ -#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ -#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ -#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ -#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ -#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ -#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ -#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ -#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ -#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ -#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ -#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ -#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ -#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ -#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ -#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ -#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ -#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ -#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ -#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ -#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ -#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ -#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ -#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ -#define EUART0 ((EUSART_TypeDef *) EUART0_BASE) /**< EUART0 base pointer */ -#define CRYPTOACC ((CRYPTOACC_TypeDef *) CRYPTOACC_BASE) /**< CRYPTOACC base pointer */ -#define CRYPTOACC_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_RNGCTRL_BASE) /**< CRYPTOACC_RNGCTRL base pointer */ -#define CRYPTOACC_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_PKCTRL_BASE) /**< CRYPTOACC_PKCTRL base pointer */ -#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ -#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ -/** @} End of group EFR32BG22C224F512IM40_Peripheral_Declaration */ - -/**************************************************************************//** - * @defgroup EFR32BG22C224F512IM40_Peripheral_Parameters EFR32BG22C224F512IM40 Peripheral Parameters - * @{ - * @brief Device peripheral parameter values - *****************************************************************************/ - -/* Common peripheral register block offsets. */ -#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ -#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ -#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ -#define MSC_CDA_PRESENT 0x1UL /**> */ -#define MSC_FDIO_WIDTH 0x40UL /**> None */ -#define MSC_FLASHADDRBITS 0x13UL /**> None */ -#define MSC_FLASHBLOCKADDRBITS 0x13UL /**> None */ -#define MSC_FLASH_BLOCK_INFO_PCOUNT 0xCUL /**> None */ -#define MSC_INFOADDRBITS 0x10UL /**> None */ -#define MSC_INFOBLOCKADDRBITS 0x10UL /**> None */ -#define MSC_INFO_PSIZE_BITS 0xCUL /**> None */ -#define MSC_MAIN_PSIZE_BITS 0xCUL /**> None */ -#define MSC_MTP_PRESENT 0x1UL /**> */ -#define MSC_REDUNDANCY 0x2UL /**> None */ -#define MSC_UD_IN_MTP_PAGE 0x0UL /**> */ -#define MSC_YADDRBITS 0x6UL /**> */ -#define SYSROM_WORDS 0x700UL /**> Number of words in ROM */ -#define SYSROM_ROM_SIZE_BYTES 0x1C00UL /**> Number of bytes in ROM */ -#define DMEM_BANK0_SIZE 0x6000UL /**> Bank0 Size */ -#define DMEM_BANK1_SIZE 0x2000UL /**> Bank1 Size */ -#define DMEM_BANK2_SIZE 0x0UL /**> Bank2 Size */ -#define DMEM_BANK3_SIZE 0x0UL /**> Bank3 Size */ -#define DMEM_BANK4_SIZE 0x0UL /**> Bank4 Size */ -#define DMEM_BANK5_SIZE 0x0UL /**> Bank5 Size */ -#define DMEM_BANK6_SIZE 0x0UL /**> Bank6 Size */ -#define DMEM_BANK7_SIZE 0x0UL /**> Bank7 Size */ -#define DMEM_NUM_BANKS 0x2UL /**> Number of Banks */ -#define DMEM_SIZE 0x8000UL /**> Total size */ -#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ -#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ -#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ -#define ICACHE0_CACHEABLE_SIZE 0x200UL /**> Cache Size */ -#define ICACHE0_CACHEABLE_START 0x12UL /**> Cache Start */ -#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ -#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ -#define ICACHE0_FLASH_START 0x0UL /**> Flash start */ -#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ -#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ -#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ -#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ -#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ -#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ -#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ -#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ -#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ -#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ -#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ -#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ -#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ -#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ -#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ -#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ -#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ -#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ -#define PRS_SYNC_CH_NUM 0x4UL /**> None */ -#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ -#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ -#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ -#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ -#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ -#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ -#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ -#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ -#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ -#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ -#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ -#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ -#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ -#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ -#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ -#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ -#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ -#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ -#define GPIO_PORT_A_WL 0x8UL /**> New Param */ -#define GPIO_PORT_A_WU 0x1UL /**> New Param */ -#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ -#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ -#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ -#define GPIO_PORT_B_WL 0x5UL /**> New Param */ -#define GPIO_PORT_B_WU 0x0UL /**> New Param */ -#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ -#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ -#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ -#define GPIO_PORT_C_WL 0x8UL /**> New Param */ -#define GPIO_PORT_C_WU 0x0UL /**> New Param */ -#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ -#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ -#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ -#define GPIO_PORT_D_WL 0x4UL /**> New Param */ -#define GPIO_PORT_D_WU 0x0UL /**> New Param */ -#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ -#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ -#define LDMA_CH_BITS 0x5UL /**> New Param */ -#define LDMA_CH_NUM 0x8UL /**> New Param */ -#define LDMA_FIFO_BITS 0x5UL /**> New Param */ -#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ -#define LDMAXBAR_CH_BITS 0x5UL /**> None */ -#define LDMAXBAR_CH_NUM 0x8UL /**> None */ -#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ -#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ -#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ -#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER0_NO_DTI 0x0UL /**> */ -#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER1_NO_DTI 0x0UL /**> */ -#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER2_NO_DTI 0x0UL /**> */ -#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER3_NO_DTI 0x0UL /**> */ -#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ -#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ -#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ -#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ -#define TIMER4_NO_DTI 0x0UL /**> */ -#define USART0_AUTOTX_REG 0x1UL /**> None */ -#define USART0_AUTOTX_REG_B 0x0UL /**> None */ -#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ -#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ -#define USART0_CLK_PRS 0x1UL /**> None */ -#define USART0_CLK_PRS_B 0x0UL /**> New Param */ -#define USART0_FLOW_CONTROL 0x1UL /**> None */ -#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ -#define USART0_I2S 0x1UL /**> None */ -#define USART0_I2S_B 0x0UL /**> New Param */ -#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ -#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_MVDIS_FUNC 0x1UL /**> None */ -#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ -#define USART0_RX_PRS 0x1UL /**> None */ -#define USART0_RX_PRS_B 0x0UL /**> New Param */ -#define USART0_SC_AVAILABLE 0x1UL /**> None */ -#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ -#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ -#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ -#define USART0_TIMER 0x1UL /**> New Param */ -#define USART0_TIMER_B 0x0UL /**> New Param */ -#define USART1_AUTOTX_REG 0x1UL /**> None */ -#define USART1_AUTOTX_REG_B 0x0UL /**> None */ -#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ -#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ -#define USART1_CLK_PRS 0x1UL /**> None */ -#define USART1_CLK_PRS_B 0x0UL /**> New Param */ -#define USART1_FLOW_CONTROL 0x1UL /**> None */ -#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ -#define USART1_I2S 0x1UL /**> None */ -#define USART1_I2S_B 0x0UL /**> New Param */ -#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ -#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ -#define USART1_MVDIS_FUNC 0x1UL /**> None */ -#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ -#define USART1_RX_PRS 0x1UL /**> None */ -#define USART1_RX_PRS_B 0x0UL /**> New Param */ -#define USART1_SC_AVAILABLE 0x1UL /**> None */ -#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ -#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ -#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ -#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ -#define USART1_TIMER 0x1UL /**> New Param */ -#define USART1_TIMER_B 0x0UL /**> New Param */ -#define BURTC_CNTWIDTH 0x20UL /**> None */ -#define BURTC_PRECNT_WIDTH 0xFUL /**> */ -#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ -#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ -#define SYSCFG_CHIP_FAMILY 0x34UL /**> CHIP Family */ -#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ -#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ -#define SYSCFG_RAM0_INST_COUNT 0x2UL /**> None */ -#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ -#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ -#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ -#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ -#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ -#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ -#define PDM_FIFO_LEN 0x4UL /**> New Param */ -#define PDM_NUM_CH 0x2UL /**> None */ -#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ -#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ -#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ -#define PDM_PIPELINE 0x0UL /**> None */ -#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ -#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x0UL /**> Enable sidechannel counter measures */ -#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ -#define SMU_NUM_PPU_PERIPHS 0x30UL /**> Number of PPU Peripherals */ -#define SMU_NUM_PPU_PERIPHS_MOD_32 0x10UL /**> Number of PPU Peripherals (mod 32) */ -#define SMU_NUM_PPU_PERIPHS_SUB_32 0x10UL /**> Number of PPU peripherals minus 32 */ -#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ -#define RTCC_CC_NUM 0x3UL /**> None */ -#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ -#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ -#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ -#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ -#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ -#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ -#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ -#define WDOG0_PCNUM 0x2UL /**> None */ -#define EUART0_USE_AS_LEUART 0x1UL /**> LEUART instace */ -#define EUART0_USE_AS_UART 0x0UL /**> UART instance */ -#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ -#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ -#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ -#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ -#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ -#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ -#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ -#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ -#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ -#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ -#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ -#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ -#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ -#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ -#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ -#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ -#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ -#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ -#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ -#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ -#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ -#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ -#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ -#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ -#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ -#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ -#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ -#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ -#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ -#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ -#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ -#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ -#define PRORTC_CC_NUM 0x2UL /**> None */ - -/* Instance macros for I2C */ -#define I2C(n) (((n) == 0) ? I2C0 \ - : ((n) == 1) ? I2C1 \ - : 0x0UL) -#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ - : ((ref) == I2C1) ? 1 \ - : -1) -#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ - : ((n) == 1) ? I2C1_DELAY \ - : 0x0UL) -#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ - : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ - : 0x0UL) - -/* Instance macros for TIMER */ -#define TIMER(n) (((n) == 0) ? TIMER0 \ - : ((n) == 1) ? TIMER1 \ - : ((n) == 2) ? TIMER2 \ - : ((n) == 3) ? TIMER3 \ - : ((n) == 4) ? TIMER4 \ - : 0x0UL) -#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ - : ((ref) == TIMER1) ? 1 \ - : ((ref) == TIMER2) ? 2 \ - : ((ref) == TIMER3) ? 3 \ - : ((ref) == TIMER4) ? 4 \ - : -1) -#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ - : ((n) == 1) ? TIMER1_CC_NUM \ - : ((n) == 2) ? TIMER2_CC_NUM \ - : ((n) == 3) ? TIMER3_CC_NUM \ - : ((n) == 4) ? TIMER4_CC_NUM \ - : 0x0UL) -#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ - : ((n) == 1) ? TIMER1_CNTWIDTH \ - : ((n) == 2) ? TIMER2_CNTWIDTH \ - : ((n) == 3) ? TIMER3_CNTWIDTH \ - : ((n) == 4) ? TIMER4_CNTWIDTH \ - : 0x0UL) -#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ - : ((n) == 1) ? TIMER1_DTI \ - : ((n) == 2) ? TIMER2_DTI \ - : ((n) == 3) ? TIMER3_DTI \ - : ((n) == 4) ? TIMER4_DTI \ - : 0x0UL) -#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ - : ((n) == 1) ? TIMER1_DTI_CC_NUM \ - : ((n) == 2) ? TIMER2_DTI_CC_NUM \ - : ((n) == 3) ? TIMER3_DTI_CC_NUM \ - : ((n) == 4) ? TIMER4_DTI_CC_NUM \ - : 0x0UL) -#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ - : ((n) == 1) ? TIMER1_NO_DTI \ - : ((n) == 2) ? TIMER2_NO_DTI \ - : ((n) == 3) ? TIMER3_NO_DTI \ - : ((n) == 4) ? TIMER4_NO_DTI \ - : 0x0UL) - -/* Instance macros for USART */ -#define USART(n) (((n) == 0) ? USART0 \ - : ((n) == 1) ? USART1 \ - : 0x0UL) -#define USART_NUM(ref) (((ref) == USART0) ? 0 \ - : ((ref) == USART1) ? 1 \ - : -1) -#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ - : ((n) == 1) ? USART1_AUTOTX_REG \ - : 0x0UL) -#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ - : ((n) == 1) ? USART1_AUTOTX_REG_B \ - : 0x0UL) -#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ - : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ - : 0x0UL) -#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ - : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ - : 0x0UL) -#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ - : ((n) == 1) ? USART1_CLK_PRS \ - : 0x0UL) -#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ - : ((n) == 1) ? USART1_CLK_PRS_B \ - : 0x0UL) -#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ - : ((n) == 1) ? USART1_FLOW_CONTROL \ - : 0x0UL) -#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ - : ((n) == 1) ? USART1_FLOW_CONTROL_B \ - : 0x0UL) -#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ - : ((n) == 1) ? USART1_I2S \ - : 0x0UL) -#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ - : ((n) == 1) ? USART1_I2S_B \ - : 0x0UL) -#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ - : ((n) == 1) ? USART1_IRDA_AVAILABLE \ - : 0x0UL) -#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ - : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ - : 0x0UL) -#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ - : ((n) == 1) ? USART1_MVDIS_FUNC \ - : 0x0UL) -#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ - : ((n) == 1) ? USART1_MVDIS_FUNC_B \ - : 0x0UL) -#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ - : ((n) == 1) ? USART1_RX_PRS \ - : 0x0UL) -#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ - : ((n) == 1) ? USART1_RX_PRS_B \ - : 0x0UL) -#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ - : ((n) == 1) ? USART1_SC_AVAILABLE \ - : 0x0UL) -#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ - : ((n) == 1) ? USART1_SC_AVAILABLE_B \ - : 0x0UL) -#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ - : ((n) == 1) ? USART1_SYNC_AVAILABLE \ - : 0x0UL) -#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ - : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ - : 0x0UL) -#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ - : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ - : 0x0UL) -#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ - : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ - : 0x0UL) -#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ - : ((n) == 1) ? USART1_TIMER \ - : 0x0UL) -#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ - : ((n) == 1) ? USART1_TIMER_B \ - : 0x0UL) - -/** @} End of group EFR32BG22C224F512IM40_Peripheral_Parameters */ - -/** @} End of group EFR32BG22C224F512IM40 */ -/** @}} End of group Parts */ - -#ifdef __cplusplus -} -#endif -#endif +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer Header File + * for EFR32BG22C224F512IM40 + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ +#ifndef EFR32BG22C224F512IM40_H +#define EFR32BG22C224F512IM40_H + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************************************************************//** + * @addtogroup Parts + * @{ + *****************************************************************************/ + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40 EFR32BG22C224F512IM40 + * @{ + *****************************************************************************/ + +/** Interrupt Number Definition */ +typedef enum IRQn{ + /****** Cortex-M Processor Exceptions Numbers ******************************************/ + NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< -13 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< -12 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< -11 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< -10 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< -5 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< -4 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< -2 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< -1 Cortex-M System Tick Interrupt */ + + /****** EFR32BG22 Peripheral Interrupt Numbers ******************************************/ + + CRYPTOACC_IRQn = 0, /*!< 0 EFR32 CRYPTOACC Interrupt */ + TRNG_IRQn = 1, /*!< 1 EFR32 TRNG Interrupt */ + PKE_IRQn = 2, /*!< 2 EFR32 PKE Interrupt */ + SMU_SECURE_IRQn = 3, /*!< 3 EFR32 SMU_SECURE Interrupt */ + SMU_S_PRIVILEGED_IRQn = 4, /*!< 4 EFR32 SMU_S_PRIVILEGED Interrupt */ + SMU_NS_PRIVILEGED_IRQn = 5, /*!< 5 EFR32 SMU_NS_PRIVILEGED Interrupt */ + EMU_IRQn = 6, /*!< 6 EFR32 EMU Interrupt */ + TIMER0_IRQn = 7, /*!< 7 EFR32 TIMER0 Interrupt */ + TIMER1_IRQn = 8, /*!< 8 EFR32 TIMER1 Interrupt */ + TIMER2_IRQn = 9, /*!< 9 EFR32 TIMER2 Interrupt */ + TIMER3_IRQn = 10, /*!< 10 EFR32 TIMER3 Interrupt */ + TIMER4_IRQn = 11, /*!< 11 EFR32 TIMER4 Interrupt */ + RTCC_IRQn = 12, /*!< 12 EFR32 RTCC Interrupt */ + USART0_RX_IRQn = 13, /*!< 13 EFR32 USART0_RX Interrupt */ + USART0_TX_IRQn = 14, /*!< 14 EFR32 USART0_TX Interrupt */ + USART1_RX_IRQn = 15, /*!< 15 EFR32 USART1_RX Interrupt */ + USART1_TX_IRQn = 16, /*!< 16 EFR32 USART1_TX Interrupt */ + ICACHE0_IRQn = 17, /*!< 17 EFR32 ICACHE0 Interrupt */ + BURTC_IRQn = 18, /*!< 18 EFR32 BURTC Interrupt */ + LETIMER0_IRQn = 19, /*!< 19 EFR32 LETIMER0 Interrupt */ + SYSCFG_IRQn = 20, /*!< 20 EFR32 SYSCFG Interrupt */ + LDMA_IRQn = 21, /*!< 21 EFR32 LDMA Interrupt */ + LFXO_IRQn = 22, /*!< 22 EFR32 LFXO Interrupt */ + LFRCO_IRQn = 23, /*!< 23 EFR32 LFRCO Interrupt */ + ULFRCO_IRQn = 24, /*!< 24 EFR32 ULFRCO Interrupt */ + GPIO_ODD_IRQn = 25, /*!< 25 EFR32 GPIO_ODD Interrupt */ + GPIO_EVEN_IRQn = 26, /*!< 26 EFR32 GPIO_EVEN Interrupt */ + I2C0_IRQn = 27, /*!< 27 EFR32 I2C0 Interrupt */ + I2C1_IRQn = 28, /*!< 28 EFR32 I2C1 Interrupt */ + EMUDG_IRQn = 29, /*!< 29 EFR32 EMUDG Interrupt */ + EMUSE_IRQn = 30, /*!< 30 EFR32 EMUSE Interrupt */ + AGC_IRQn = 31, /*!< 31 EFR32 AGC Interrupt */ + BUFC_IRQn = 32, /*!< 32 EFR32 BUFC Interrupt */ + FRC_PRI_IRQn = 33, /*!< 33 EFR32 FRC_PRI Interrupt */ + FRC_IRQn = 34, /*!< 34 EFR32 FRC Interrupt */ + MODEM_IRQn = 35, /*!< 35 EFR32 MODEM Interrupt */ + PROTIMER_IRQn = 36, /*!< 36 EFR32 PROTIMER Interrupt */ + RAC_RSM_IRQn = 37, /*!< 37 EFR32 RAC_RSM Interrupt */ + RAC_SEQ_IRQn = 38, /*!< 38 EFR32 RAC_SEQ Interrupt */ + RDMAILBOX_IRQn = 39, /*!< 39 EFR32 RDMAILBOX Interrupt */ + RFSENSE_IRQn = 40, /*!< 40 EFR32 RFSENSE Interrupt */ + PRORTC_IRQn = 41, /*!< 41 EFR32 PRORTC Interrupt */ + SYNTH_IRQn = 42, /*!< 42 EFR32 SYNTH Interrupt */ + WDOG0_IRQn = 43, /*!< 43 EFR32 WDOG0 Interrupt */ + HFXO0_IRQn = 44, /*!< 44 EFR32 HFXO0 Interrupt */ + HFRCO0_IRQn = 45, /*!< 45 EFR32 HFRCO0 Interrupt */ + CMU_IRQn = 46, /*!< 46 EFR32 CMU Interrupt */ + AES_IRQn = 47, /*!< 47 EFR32 AES Interrupt */ + IADC_IRQn = 48, /*!< 48 EFR32 IADC Interrupt */ + MSC_IRQn = 49, /*!< 49 EFR32 MSC Interrupt */ + DPLL0_IRQn = 50, /*!< 50 EFR32 DPLL0 Interrupt */ + PDM_IRQn = 51, /*!< 51 EFR32 PDM Interrupt */ + SW0_IRQn = 52, /*!< 52 EFR32 SW0 Interrupt */ + SW1_IRQn = 53, /*!< 53 EFR32 SW1 Interrupt */ + SW2_IRQn = 54, /*!< 54 EFR32 SW2 Interrupt */ + SW3_IRQn = 55, /*!< 55 EFR32 SW3 Interrupt */ + KERNEL0_IRQn = 56, /*!< 56 EFR32 KERNEL0 Interrupt */ + KERNEL1_IRQn = 57, /*!< 57 EFR32 KERNEL1 Interrupt */ + M33CTI0_IRQn = 58, /*!< 58 EFR32 M33CTI0 Interrupt */ + M33CTI1_IRQn = 59, /*!< 59 EFR32 M33CTI1 Interrupt */ + EMUEFP_IRQn = 60, /*!< 60 EFR32 EMUEFP Interrupt */ + DCDC_IRQn = 61, /*!< 61 EFR32 DCDC Interrupt */ + EUART0_RX_IRQn = 62, /*!< 62 EFR32 EUART0_RX Interrupt */ + EUART0_TX_IRQn = 63, /*!< 63 EFR32 EUART0_TX Interrupt */ +} IRQn_Type; + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40_Core EFR32BG22C224F512IM40 Core + * @{ + * @brief Processor and Core Peripheral Section + *****************************************************************************/ + +#define __CM33_REV 0x0004U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/** @} End of group EFR32BG22C224F512IM40_Core */ + +/**************************************************************************//** +* @defgroup EFR32BG22C224F512IM40_Part EFR32BG22C224F512IM40 Part +* @{ +******************************************************************************/ + +/** Part number */ + +/* If part number is not defined as compiler option, define it */ +#if !defined(EFR32BG22C224F512IM40) +#define EFR32BG22C224F512IM40 1 /**< FULL Part */ +#endif + +/** Configure part number */ +#define PART_NUMBER "EFR32BG22C224F512IM40" /**< Part Number */ + +/** Family / Line / Series / Config */ +#define _EFR32_BLUE_FAMILY 1 /** Device Family Name Identifier */ +#define _EFR32_BG_FAMILY 1 /** Device Family Identifier */ +#define _EFR_DEVICE 1 /** Product Line Identifier */ +#define _SILICON_LABS_32B_SERIES_2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES 2 /** Product Series Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG_2 /** Product Config Identifier */ +#define _SILICON_LABS_32B_SERIES_2_CONFIG 2 /** Product Config Identifier */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID 205 /** Silicon Labs internal use only */ +#define _SILICON_LABS_GECKO_INTERNAL_SDID_205 /** Silicon Labs internal use only */ +#define _SILICON_LABS_SECURITY_FEATURE_SE 0 /** Mid */ +#define _SILICON_LABS_SECURITY_FEATURE_VAULT 1 /** High */ +#define _SILICON_LABS_SECURITY_FEATURE_ROT 2 /** Root Of Trust */ +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_ROT /** Security feature set */ +#define _SILICON_LABS_DCDC_FEATURE_NOTUSED 0 /** Not Used */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK 1 /** Includes Buck DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST 2 /** Includes Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE_DCDC_BOB 3 /** Includes Buck or Boost DCDC */ +#define _SILICON_LABS_DCDC_FEATURE _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK /** DCDC feature set */ +#define _SILICON_LABS_EFR32_RADIO_NONE 0 /** No radio present */ +#define _SILICON_LABS_EFR32_RADIO_SUBGHZ 1 /** Radio supports Sub-GHz */ +#define _SILICON_LABS_EFR32_RADIO_2G4HZ 2 /** Radio supports 2.4 GHz */ +#define _SILICON_LABS_EFR32_RADIO_DUALBAND 3 /** Radio supports dual band */ +#define _SILICON_LABS_EFR32_RADIO_TYPE _SILICON_LABS_EFR32_RADIO_2G4HZ /** Radio type */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM 6 /** Radio 2G4HZ HP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_MAX_OUTPUT_DBM 0 /** Radio 2G4HZ LP PA output power */ +#define _SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT /** Radio 2G4HZ HP PA is present */ +#define _SILICON_LABS_EFR32_2G4HZ_LP_PA_PRESENT /** Radio 2G4HZ LP PA is present */ +#define LFRCO_PRECISION_MODE 1 /** Precision mode of LFRCO enabled or disabled */ + +/** Memory Base addresses and limits */ +#define FLASH_MEM_BASE (0x00000000UL) /** FLASH_MEM base address */ +#define FLASH_MEM_SIZE (0x00080000UL) /** FLASH_MEM available address space */ +#define FLASH_MEM_END (0x0007FFFFUL) /** FLASH_MEM end address */ +#define FLASH_MEM_BITS (0x14UL) /** FLASH_MEM used bits */ +#define MSC_FLASH_MEM_BASE (0x00000000UL) /** MSC_FLASH_MEM base address */ +#define MSC_FLASH_MEM_SIZE (0x00080000UL) /** MSC_FLASH_MEM available address space */ +#define MSC_FLASH_MEM_END (0x0007FFFFUL) /** MSC_FLASH_MEM end address */ +#define MSC_FLASH_MEM_BITS (0x14UL) /** MSC_FLASH_MEM used bits */ +#define MSC_FLASH_USERDATA_MEM_BASE (0x0FE00000UL) /** MSC_FLASH_USERDATA_MEM base address */ +#define MSC_FLASH_USERDATA_MEM_SIZE (0x00000400UL) /** MSC_FLASH_USERDATA_MEM available address space */ +#define MSC_FLASH_USERDATA_MEM_END (0x0FE003FFUL) /** MSC_FLASH_USERDATA_MEM end address */ +#define MSC_FLASH_USERDATA_MEM_BITS (0xBUL) /** MSC_FLASH_USERDATA_MEM used bits */ +#define USERDATA_BASE (0x0FE00000UL) /** USERDATA base address */ +#define USERDATA_SIZE (0x00000400UL) /** USERDATA available address space */ +#define USERDATA_END (0x0FE003FFUL) /** USERDATA end address */ +#define USERDATA_BITS (0xBUL) /** USERDATA used bits */ +#define MSC_FLASH_DEVINFO_MEM_BASE (0x0FE08000UL) /** MSC_FLASH_DEVINFO_MEM base address */ +#define MSC_FLASH_DEVINFO_MEM_SIZE (0x00000400UL) /** MSC_FLASH_DEVINFO_MEM available address space */ +#define MSC_FLASH_DEVINFO_MEM_END (0x0FE083FFUL) /** MSC_FLASH_DEVINFO_MEM end address */ +#define MSC_FLASH_DEVINFO_MEM_BITS (0xBUL) /** MSC_FLASH_DEVINFO_MEM used bits */ +#define MSC_FLASH_CHIPCONFIG_MEM_BASE (0x0FE0E000UL) /** MSC_FLASH_CHIPCONFIG_MEM base address */ +#define MSC_FLASH_CHIPCONFIG_MEM_SIZE (0x00000600UL) /** MSC_FLASH_CHIPCONFIG_MEM available address space */ +#define MSC_FLASH_CHIPCONFIG_MEM_END (0x0FE0E5FFUL) /** MSC_FLASH_CHIPCONFIG_MEM end address */ +#define MSC_FLASH_CHIPCONFIG_MEM_BITS (0xBUL) /** MSC_FLASH_CHIPCONFIG_MEM used bits */ +#define DMEM_RAM0_RAM_MEM_BASE (0x20000000UL) /** DMEM_RAM0_RAM_MEM base address */ +#define DMEM_RAM0_RAM_MEM_SIZE (0x00008000UL) /** DMEM_RAM0_RAM_MEM available address space */ +#define DMEM_RAM0_RAM_MEM_END (0x20007FFFUL) /** DMEM_RAM0_RAM_MEM end address */ +#define DMEM_RAM0_RAM_MEM_BITS (0x10UL) /** DMEM_RAM0_RAM_MEM used bits */ +#define RAM_MEM_BASE (0x20000000UL) /** RAM_MEM base address */ +#define RAM_MEM_SIZE (0x00008000UL) /** RAM_MEM available address space */ +#define RAM_MEM_END (0x20007FFFUL) /** RAM_MEM end address */ +#define RAM_MEM_BITS (0x10UL) /** RAM_MEM used bits */ +#define CRYPTOACC_RNGOUT_FIFO_S_MEM_BASE (0x4C024000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM base address */ +#define CRYPTOACC_RNGOUT_FIFO_S_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM available address space */ +#define CRYPTOACC_RNGOUT_FIFO_S_MEM_END (0x4C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM end address */ +#define CRYPTOACC_RNGOUT_FIFO_S_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_S_MEM used bits */ +#define CRYPTOACC_PKRAM_MAIN_S_MEM_BASE (0x4C028000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM base address */ +#define CRYPTOACC_PKRAM_MAIN_S_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_S_MEM available address space */ +#define CRYPTOACC_PKRAM_MAIN_S_MEM_END (0x4C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM end address */ +#define CRYPTOACC_PKRAM_MAIN_S_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_S_MEM used bits */ +#define CRYPTOACC_RNGOUT_FIFO_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM base address */ +#define CRYPTOACC_RNGOUT_FIFO_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_MEM available address space */ +#define CRYPTOACC_RNGOUT_FIFO_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM end address */ +#define CRYPTOACC_RNGOUT_FIFO_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_MEM used bits */ +#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BASE (0x5C024000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM base address */ +#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_SIZE (0x00004000UL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM available address space */ +#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_END (0x5C027FFFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM end address */ +#define CRYPTOACC_RNGOUT_FIFO_NS_MEM_BITS (0xFUL) /** CRYPTOACC_RNGOUT_FIFO_NS_MEM used bits */ +#define CRYPTOACC_PKRAM_MAIN_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_MEM base address */ +#define CRYPTOACC_PKRAM_MAIN_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_MEM available address space */ +#define CRYPTOACC_PKRAM_MAIN_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_MEM end address */ +#define CRYPTOACC_PKRAM_MAIN_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_MEM used bits */ +#define CRYPTOACC_PKRAM_MAIN_NS_MEM_BASE (0x5C028000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM base address */ +#define CRYPTOACC_PKRAM_MAIN_NS_MEM_SIZE (0x00001000UL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM available address space */ +#define CRYPTOACC_PKRAM_MAIN_NS_MEM_END (0x5C028FFFUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM end address */ +#define CRYPTOACC_PKRAM_MAIN_NS_MEM_BITS (0xDUL) /** CRYPTOACC_PKRAM_MAIN_NS_MEM used bits */ +#define RDMEM_SEQRAM_S_MEM_BASE (0xA0000000UL) /** RDMEM_SEQRAM_S_MEM base address */ +#define RDMEM_SEQRAM_S_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_S_MEM available address space */ +#define RDMEM_SEQRAM_S_MEM_END (0xA0003FFFUL) /** RDMEM_SEQRAM_S_MEM end address */ +#define RDMEM_SEQRAM_S_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_S_MEM used bits */ +#define RDMEM_FRCRAM_S_MEM_BASE (0xA0004000UL) /** RDMEM_FRCRAM_S_MEM base address */ +#define RDMEM_FRCRAM_S_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_S_MEM available address space */ +#define RDMEM_FRCRAM_S_MEM_END (0xA0004FFFUL) /** RDMEM_FRCRAM_S_MEM end address */ +#define RDMEM_FRCRAM_S_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_S_MEM used bits */ +#define RDMEM_SEQRAM_NS_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_NS_MEM base address */ +#define RDMEM_SEQRAM_NS_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_NS_MEM available address space */ +#define RDMEM_SEQRAM_NS_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_NS_MEM end address */ +#define RDMEM_SEQRAM_NS_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_NS_MEM used bits */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BASE (0xB0000000UL) /** RDMEM_SEQRAM_SEQRAM_MEM base address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_SIZE (0x00004000UL) /** RDMEM_SEQRAM_SEQRAM_MEM available address space */ +#define RDMEM_SEQRAM_SEQRAM_MEM_END (0xB0003FFFUL) /** RDMEM_SEQRAM_SEQRAM_MEM end address */ +#define RDMEM_SEQRAM_SEQRAM_MEM_BITS (0xFUL) /** RDMEM_SEQRAM_SEQRAM_MEM used bits */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_FRCRAM_MEM base address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_FRCRAM_MEM available address space */ +#define RDMEM_FRCRAM_FRCRAM_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_FRCRAM_MEM end address */ +#define RDMEM_FRCRAM_FRCRAM_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_FRCRAM_MEM used bits */ +#define RDMEM_FRCRAM_NS_MEM_BASE (0xB0004000UL) /** RDMEM_FRCRAM_NS_MEM base address */ +#define RDMEM_FRCRAM_NS_MEM_SIZE (0x00001000UL) /** RDMEM_FRCRAM_NS_MEM available address space */ +#define RDMEM_FRCRAM_NS_MEM_END (0xB0004FFFUL) /** RDMEM_FRCRAM_NS_MEM end address */ +#define RDMEM_FRCRAM_NS_MEM_BITS (0xDUL) /** RDMEM_FRCRAM_NS_MEM used bits */ + +/** Flash and SRAM limits for EFR32BG22C224F512IM40 */ +#define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ +#define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */ +#define FLASH_PAGE_SIZE (0x00002000UL) /**< Flash Memory page size */ +#define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */ +#define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */ +#define DMA_CHAN_COUNT LDMA_CH_NUM /**< Number of DMA channels */ +#define EXT_IRQ_COUNT 64 /**< Number of External (NVIC) interrupts */ + +/* GPIO Avalibility Info */ +#define GPIO_PA_INDEX 0U /**< Index of port PA */ +#define GPIO_PA_COUNT 9U /**< Number of pins on port PA */ +#define GPIO_PA_MASK (0x01FFUL) /**< Port PA pin mask */ +#define GPIO_PA_PIN0 1U /**< GPIO pin PA0 is present. */ +#define GPIO_PA_PIN1 1U /**< GPIO pin PA1 is present. */ +#define GPIO_PA_PIN2 1U /**< GPIO pin PA2 is present. */ +#define GPIO_PA_PIN3 1U /**< GPIO pin PA3 is present. */ +#define GPIO_PA_PIN4 1U /**< GPIO pin PA4 is present. */ +#define GPIO_PA_PIN5 1U /**< GPIO pin PA5 is present. */ +#define GPIO_PA_PIN6 1U /**< GPIO pin PA6 is present. */ +#define GPIO_PA_PIN7 1U /**< GPIO pin PA7 is present. */ +#define GPIO_PA_PIN8 1U /**< GPIO pin PA8 is present. */ +#define GPIO_PB_INDEX 1U /**< Index of port PB */ +#define GPIO_PB_COUNT 5U /**< Number of pins on port PB */ +#define GPIO_PB_MASK (0x001FUL) /**< Port PB pin mask */ +#define GPIO_PB_PIN0 1U /**< GPIO pin PB0 is present. */ +#define GPIO_PB_PIN1 1U /**< GPIO pin PB1 is present. */ +#define GPIO_PB_PIN2 1U /**< GPIO pin PB2 is present. */ +#define GPIO_PB_PIN3 1U /**< GPIO pin PB3 is present. */ +#define GPIO_PB_PIN4 1U /**< GPIO pin PB4 is present. */ +#define GPIO_PC_INDEX 2U /**< Index of port PC */ +#define GPIO_PC_COUNT 8U /**< Number of pins on port PC */ +#define GPIO_PC_MASK (0x00FFUL) /**< Port PC pin mask */ +#define GPIO_PC_PIN0 1U /**< GPIO pin PC0 is present. */ +#define GPIO_PC_PIN1 1U /**< GPIO pin PC1 is present. */ +#define GPIO_PC_PIN2 1U /**< GPIO pin PC2 is present. */ +#define GPIO_PC_PIN3 1U /**< GPIO pin PC3 is present. */ +#define GPIO_PC_PIN4 1U /**< GPIO pin PC4 is present. */ +#define GPIO_PC_PIN5 1U /**< GPIO pin PC5 is present. */ +#define GPIO_PC_PIN6 1U /**< GPIO pin PC6 is present. */ +#define GPIO_PC_PIN7 1U /**< GPIO pin PC7 is present. */ +#define GPIO_PD_INDEX 3U /**< Index of port PD */ +#define GPIO_PD_COUNT 4U /**< Number of pins on port PD */ +#define GPIO_PD_MASK (0x000FUL) /**< Port PD pin mask */ +#define GPIO_PD_PIN0 1U /**< GPIO pin PD0 is present. */ +#define GPIO_PD_PIN1 1U /**< GPIO pin PD1 is present. */ +#define GPIO_PD_PIN2 1U /**< GPIO pin PD2 is present. */ +#define GPIO_PD_PIN3 1U /**< GPIO pin PD3 is present. */ + +/* Fixed Resource Locations */ +#define GPIO_SWCLK_PORT GPIO_PA_INDEX /**< Port of SWCLK.*/ +#define GPIO_SWCLK_PIN 1U /**< Pin of SWCLK.*/ +#define GPIO_SWDIO_PORT GPIO_PA_INDEX /**< Port of SWDIO.*/ +#define GPIO_SWDIO_PIN 2U /**< Pin of SWDIO.*/ +#define GPIO_SWV_PORT GPIO_PA_INDEX /**< Port of SWV.*/ +#define GPIO_SWV_PIN 3U /**< Pin of SWV.*/ +#define GPIO_TDI_PORT GPIO_PA_INDEX /**< Port of TDI.*/ +#define GPIO_TDI_PIN 4U /**< Pin of TDI.*/ +#define GPIO_TDO_PORT GPIO_PA_INDEX /**< Port of TDO.*/ +#define GPIO_TDO_PIN 3U /**< Pin of TDO.*/ +#define GPIO_TRACECLK_PORT GPIO_PA_INDEX /**< Port of TRACECLK.*/ +#define GPIO_TRACECLK_PIN 4U /**< Pin of TRACECLK.*/ +#define GPIO_TRACEDATA0_PORT GPIO_PA_INDEX /**< Port of TRACEDATA0.*/ +#define GPIO_TRACEDATA0_PIN 3U /**< Pin of TRACEDATA0.*/ +#define GPIO_EM4WU0_PORT GPIO_PA_INDEX /**< Port of EM4WU0.*/ +#define GPIO_EM4WU0_PIN 5U /**< Pin of EM4WU0.*/ +#define GPIO_EM4WU3_PORT GPIO_PB_INDEX /**< Port of EM4WU3.*/ +#define GPIO_EM4WU3_PIN 1U /**< Pin of EM4WU3.*/ +#define GPIO_EM4WU4_PORT GPIO_PB_INDEX /**< Port of EM4WU4.*/ +#define GPIO_EM4WU4_PIN 3U /**< Pin of EM4WU4.*/ +#define GPIO_EM4WU6_PORT GPIO_PC_INDEX /**< Port of EM4WU6.*/ +#define GPIO_EM4WU6_PIN 0U /**< Pin of EM4WU6.*/ +#define GPIO_EM4WU7_PORT GPIO_PC_INDEX /**< Port of EM4WU7.*/ +#define GPIO_EM4WU7_PIN 5U /**< Pin of EM4WU7.*/ +#define GPIO_EM4WU8_PORT GPIO_PC_INDEX /**< Port of EM4WU8.*/ +#define GPIO_EM4WU8_PIN 7U /**< Pin of EM4WU8.*/ +#define GPIO_EM4WU9_PORT GPIO_PD_INDEX /**< Port of EM4WU9.*/ +#define GPIO_EM4WU9_PIN 2U /**< Pin of EM4WU9.*/ +#define GPIO_THMSW_EN_PORT GPIO_PC_INDEX /**< Port of THMSW_EN.*/ +#define GPIO_THMSW_EN_PIN 0U /**< Pin of THMSW_EN.*/ +#define IADC0_VREFP_PORT GPIO_PA_INDEX /**< Port of VREFP.*/ +#define IADC0_VREFP_PIN 0U /**< Pin of VREFP.*/ +#define LFXO_LFXTAL_I_PORT GPIO_PD_INDEX /**< Port of LFXTAL_I.*/ +#define LFXO_LFXTAL_I_PIN 1U /**< Pin of LFXTAL_I.*/ +#define LFXO_LFXTAL_O_PORT GPIO_PD_INDEX /**< Port of LFXTAL_O.*/ +#define LFXO_LFXTAL_O_PIN 0U /**< Pin of LFXTAL_O.*/ +#define LFXO_LF_EXTCLK_PORT GPIO_PD_INDEX /**< Port of LF_EXTCLK.*/ +#define LFXO_LF_EXTCLK_PIN 1U /**< Pin of LF_EXTCLK.*/ + +/* Part number capabilities */ +#define BURAM_PRESENT /** BURAM is available in this part */ +#define BURAM_COUNT 1 /** 1 BURAMs available */ +#define BURTC_PRESENT /** BURTC is available in this part */ +#define BURTC_COUNT 1 /** 1 BURTCs available */ +#define CMU_PRESENT /** CMU is available in this part */ +#define CMU_COUNT 1 /** 1 CMUs available */ +#define CRYPTOACC_PRESENT /** CRYPTOACC is available in this part */ +#define CRYPTOACC_COUNT 1 /** 1 CRYPTOACCs available */ +#define DCDC_PRESENT /** DCDC is available in this part */ +#define DCDC_COUNT 1 /** 1 DCDCs available */ +#define DPLL_PRESENT /** DPLL is available in this part */ +#define DPLL_COUNT 1 /** 1 DPLLs available */ +#define EMU_PRESENT /** EMU is available in this part */ +#define EMU_COUNT 1 /** 1 EMUs available */ +#define EUART_PRESENT /** EUART is available in this part */ +#define EUART_COUNT 1 /** 1 EUARTs available */ +#define FSRCO_PRESENT /** FSRCO is available in this part */ +#define FSRCO_COUNT 1 /** 1 FSRCOs available */ +#define GPCRC_PRESENT /** GPCRC is available in this part */ +#define GPCRC_COUNT 1 /** 1 GPCRCs available */ +#define GPIO_PRESENT /** GPIO is available in this part */ +#define GPIO_COUNT 1 /** 1 GPIOs available */ +#define HFRCO_PRESENT /** HFRCO is available in this part */ +#define HFRCO_COUNT 1 /** 1 HFRCOs available */ +#define HFXO_PRESENT /** HFXO is available in this part */ +#define HFXO_COUNT 1 /** 1 HFXOs available */ +#define I2C_PRESENT /** I2C is available in this part */ +#define I2C_COUNT 2 /** 2 I2Cs available */ +#define IADC_PRESENT /** IADC is available in this part */ +#define IADC_COUNT 1 /** 1 IADCs available */ +#define ICACHE_PRESENT /** ICACHE is available in this part */ +#define ICACHE_COUNT 1 /** 1 ICACHEs available */ +#define LDMA_PRESENT /** LDMA is available in this part */ +#define LDMA_COUNT 1 /** 1 LDMAs available */ +#define LDMAXBAR_PRESENT /** LDMAXBAR is available in this part */ +#define LDMAXBAR_COUNT 1 /** 1 LDMAXBARs available */ +#define LETIMER_PRESENT /** LETIMER is available in this part */ +#define LETIMER_COUNT 1 /** 1 LETIMERs available */ +#define LFRCO_PRESENT /** LFRCO is available in this part */ +#define LFRCO_COUNT 1 /** 1 LFRCOs available */ +#define LFXO_PRESENT /** LFXO is available in this part */ +#define LFXO_COUNT 1 /** 1 LFXOs available */ +#define MSC_PRESENT /** MSC is available in this part */ +#define MSC_COUNT 1 /** 1 MSCs available */ +#define PDM_PRESENT /** PDM is available in this part */ +#define PDM_COUNT 1 /** 1 PDMs available */ +#define PRORTC_PRESENT /** PRORTC is available in this part */ +#define PRORTC_COUNT 1 /** 1 PRORTCs available */ +#define PRS_PRESENT /** PRS is available in this part */ +#define PRS_COUNT 1 /** 1 PRSs available */ +#define RADIOAES_PRESENT /** RADIOAES is available in this part */ +#define RADIOAES_COUNT 1 /** 1 RADIOAESs available */ +#define RTCC_PRESENT /** RTCC is available in this part */ +#define RTCC_COUNT 1 /** 1 RTCCs available */ +#define SMU_PRESENT /** SMU is available in this part */ +#define SMU_COUNT 1 /** 1 SMUs available */ +#define SYSCFG_PRESENT /** SYSCFG is available in this part */ +#define SYSCFG_COUNT 1 /** 1 SYSCFGs available */ +#define TIMER_PRESENT /** TIMER is available in this part */ +#define TIMER_COUNT 5 /** 5 TIMERs available */ +#define ULFRCO_PRESENT /** ULFRCO is available in this part */ +#define ULFRCO_COUNT 1 /** 1 ULFRCOs available */ +#define USART_PRESENT /** USART is available in this part */ +#define USART_COUNT 2 /** 2 USARTs available */ +#define WDOG_PRESENT /** WDOG is available in this part */ +#define WDOG_COUNT 1 /** 1 WDOGs available */ +#define DEVINFO_PRESENT /** DEVINFO is available in this part */ +#define DEVINFO_COUNT 1 /** 1 DEVINFOs available */ + +/* Include standard ARM headers for the core */ +#include "core_cm33.h" /* Core Header File */ +#include "system_efr32bg22.h" /* System Header File */ + +/** @} End of group EFR32BG22C224F512IM40_Part */ + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40_Peripheral_TypeDefs EFR32BG22C224F512IM40 Peripheral TypeDefs + * @{ + * @brief Device Specific Peripheral Register Structures + *****************************************************************************/ +#include "efr32bg22_emu.h" +#include "efr32bg22_cmu.h" +#include "efr32bg22_hfxo.h" +#include "efr32bg22_hfrco.h" +#include "efr32bg22_fsrco.h" +#include "efr32bg22_dpll.h" +#include "efr32bg22_lfxo.h" +#include "efr32bg22_lfrco.h" +#include "efr32bg22_ulfrco.h" +#include "efr32bg22_msc.h" +#include "efr32bg22_icache.h" +#include "efr32bg22_prs.h" +#include "efr32bg22_gpio.h" +#include "efr32bg22_ldma.h" +#include "efr32bg22_ldmaxbar.h" +#include "efr32bg22_timer.h" +#include "efr32bg22_usart.h" +#include "efr32bg22_burtc.h" +#include "efr32bg22_i2c.h" +#include "efr32bg22_syscfg.h" +#include "efr32bg22_buram.h" +#include "efr32bg22_gpcrc.h" +#include "efr32bg22_dcdc.h" +#include "efr32bg22_pdm.h" +#include "efr32bg22_aes.h" +#include "efr32bg22_smu.h" +#include "efr32bg22_rtcc.h" +#include "efr32bg22_letimer.h" +#include "efr32bg22_iadc.h" +#include "efr32bg22_wdog.h" +#include "efr32bg22_eusart.h" +#include "efr32bg22_cryptoacc.h" +#include "efr32bg22_devinfo.h" + +/* Custom headers for LDMAXBAR and PRS mappings */ +#include "efr32bg22_prs_signals.h" +#include "efr32bg22_dma_descriptor.h" +#include "efr32bg22_ldmaxbar_defines.h" + +/** @} End of group EFR32BG22C224F512IM40_Peripheral_TypeDefs */ + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40_Peripheral_Base EFR32BG22C224F512IM40 Peripheral Memory Map + * @{ + *****************************************************************************/ + +#define EMU_S_BASE (0x40004000UL) /* EMU_S base address */ +#define CMU_S_BASE (0x40008000UL) /* CMU_S base address */ +#define HFXO0_S_BASE (0x4000C000UL) /* HFXO0_S base address */ +#define HFRCO0_S_BASE (0x40010000UL) /* HFRCO0_S base address */ +#define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ +#define DPLL0_S_BASE (0x4001C000UL) /* DPLL0_S base address */ +#define LFXO_S_BASE (0x40020000UL) /* LFXO_S base address */ +#define LFRCO_S_BASE (0x40024000UL) /* LFRCO_S base address */ +#define ULFRCO_S_BASE (0x40028000UL) /* ULFRCO_S base address */ +#define MSC_S_BASE (0x40030000UL) /* MSC_S base address */ +#define ICACHE0_S_BASE (0x40034000UL) /* ICACHE0_S base address */ +#define PRS_S_BASE (0x40038000UL) /* PRS_S base address */ +#define GPIO_S_BASE (0x4003C000UL) /* GPIO_S base address */ +#define LDMA_S_BASE (0x40040000UL) /* LDMA_S base address */ +#define LDMAXBAR_S_BASE (0x40044000UL) /* LDMAXBAR_S base address */ +#define TIMER0_S_BASE (0x40048000UL) /* TIMER0_S base address */ +#define TIMER1_S_BASE (0x4004C000UL) /* TIMER1_S base address */ +#define TIMER2_S_BASE (0x40050000UL) /* TIMER2_S base address */ +#define TIMER3_S_BASE (0x40054000UL) /* TIMER3_S base address */ +#define TIMER4_S_BASE (0x40058000UL) /* TIMER4_S base address */ +#define USART0_S_BASE (0x4005C000UL) /* USART0_S base address */ +#define USART1_S_BASE (0x40060000UL) /* USART1_S base address */ +#define BURTC_S_BASE (0x40064000UL) /* BURTC_S base address */ +#define I2C1_S_BASE (0x40068000UL) /* I2C1_S base address */ +#define SYSCFG_S_CFGNS_BASE (0x40078000UL) /* SYSCFG_S_CFGNS base address */ +#define SYSCFG_S_BASE (0x4007C000UL) /* SYSCFG_S base address */ +#define BURAM_S_BASE (0x40080000UL) /* BURAM_S base address */ +#define GPCRC_S_BASE (0x40088000UL) /* GPCRC_S base address */ +#define DCDC_S_BASE (0x40094000UL) /* DCDC_S base address */ +#define PDM_S_BASE (0x40098000UL) /* PDM_S base address */ +#define RADIOAES_S_BASE (0x44000000UL) /* RADIOAES_S base address */ +#define SMU_S_BASE (0x44008000UL) /* SMU_S base address */ +#define SMU_S_CFGNS_BASE (0x4400C000UL) /* SMU_S_CFGNS base address */ +#define RTCC_S_BASE (0x48000000UL) /* RTCC_S base address */ +#define LETIMER0_S_BASE (0x4A000000UL) /* LETIMER0_S base address */ +#define IADC0_S_BASE (0x4A004000UL) /* IADC0_S base address */ +#define I2C0_S_BASE (0x4A010000UL) /* I2C0_S base address */ +#define WDOG0_S_BASE (0x4A018000UL) /* WDOG0_S base address */ +#define EUART0_S_BASE (0x4A030000UL) /* EUART0_S base address */ +#define CRYPTOACC_S_BASE (0x4C020000UL) /* CRYPTOACC_S base address */ +#define CRYPTOACC_S_RNGCTRL_BASE (0x4C021000UL) /* CRYPTOACC_S_RNGCTRL base address */ +#define CRYPTOACC_S_PKCTRL_BASE (0x4C022000UL) /* CRYPTOACC_S_PKCTRL base address */ +#define PRORTC_S_BASE (0xA8000000UL) /* PRORTC_S base address */ +#define EMU_NS_BASE (0x50004000UL) /* EMU_NS base address */ +#define CMU_NS_BASE (0x50008000UL) /* CMU_NS base address */ +#define HFXO0_NS_BASE (0x5000C000UL) /* HFXO0_NS base address */ +#define HFRCO0_NS_BASE (0x50010000UL) /* HFRCO0_NS base address */ +#define FSRCO_NS_BASE (0x50018000UL) /* FSRCO_NS base address */ +#define DPLL0_NS_BASE (0x5001C000UL) /* DPLL0_NS base address */ +#define LFXO_NS_BASE (0x50020000UL) /* LFXO_NS base address */ +#define LFRCO_NS_BASE (0x50024000UL) /* LFRCO_NS base address */ +#define ULFRCO_NS_BASE (0x50028000UL) /* ULFRCO_NS base address */ +#define MSC_NS_BASE (0x50030000UL) /* MSC_NS base address */ +#define ICACHE0_NS_BASE (0x50034000UL) /* ICACHE0_NS base address */ +#define PRS_NS_BASE (0x50038000UL) /* PRS_NS base address */ +#define GPIO_NS_BASE (0x5003C000UL) /* GPIO_NS base address */ +#define LDMA_NS_BASE (0x50040000UL) /* LDMA_NS base address */ +#define LDMAXBAR_NS_BASE (0x50044000UL) /* LDMAXBAR_NS base address */ +#define TIMER0_NS_BASE (0x50048000UL) /* TIMER0_NS base address */ +#define TIMER1_NS_BASE (0x5004C000UL) /* TIMER1_NS base address */ +#define TIMER2_NS_BASE (0x50050000UL) /* TIMER2_NS base address */ +#define TIMER3_NS_BASE (0x50054000UL) /* TIMER3_NS base address */ +#define TIMER4_NS_BASE (0x50058000UL) /* TIMER4_NS base address */ +#define USART0_NS_BASE (0x5005C000UL) /* USART0_NS base address */ +#define USART1_NS_BASE (0x50060000UL) /* USART1_NS base address */ +#define BURTC_NS_BASE (0x50064000UL) /* BURTC_NS base address */ +#define I2C1_NS_BASE (0x50068000UL) /* I2C1_NS base address */ +#define SYSCFG_NS_CFGNS_BASE (0x50078000UL) /* SYSCFG_NS_CFGNS base address */ +#define SYSCFG_NS_BASE (0x5007C000UL) /* SYSCFG_NS base address */ +#define BURAM_NS_BASE (0x50080000UL) /* BURAM_NS base address */ +#define GPCRC_NS_BASE (0x50088000UL) /* GPCRC_NS base address */ +#define DCDC_NS_BASE (0x50094000UL) /* DCDC_NS base address */ +#define PDM_NS_BASE (0x50098000UL) /* PDM_NS base address */ +#define RADIOAES_NS_BASE (0x54000000UL) /* RADIOAES_NS base address */ +#define SMU_NS_BASE (0x54008000UL) /* SMU_NS base address */ +#define SMU_NS_CFGNS_BASE (0x5400C000UL) /* SMU_NS_CFGNS base address */ +#define RTCC_NS_BASE (0x58000000UL) /* RTCC_NS base address */ +#define LETIMER0_NS_BASE (0x5A000000UL) /* LETIMER0_NS base address */ +#define IADC0_NS_BASE (0x5A004000UL) /* IADC0_NS base address */ +#define I2C0_NS_BASE (0x5A010000UL) /* I2C0_NS base address */ +#define WDOG0_NS_BASE (0x5A018000UL) /* WDOG0_NS base address */ +#define EUART0_NS_BASE (0x5A030000UL) /* EUART0_NS base address */ +#define CRYPTOACC_NS_BASE (0x5C020000UL) /* CRYPTOACC_NS base address */ +#define CRYPTOACC_NS_RNGCTRL_BASE (0x5C021000UL) /* CRYPTOACC_NS_RNGCTRL base address */ +#define CRYPTOACC_NS_PKCTRL_BASE (0x5C022000UL) /* CRYPTOACC_NS_PKCTRL base address */ +#define PRORTC_NS_BASE (0xB8000000UL) /* PRORTC_NS base address */ + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" + +#endif +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) +#include "sl_trustzone_secure_config.h" + +#endif + +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EMU_S) && (SL_TRUSTZONE_PERIPHERAL_EMU_S != 0))) +#define EMU_BASE (EMU_S_BASE) /* EMU base address */ +#else +#define EMU_BASE (EMU_NS_BASE) /* EMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CMU_S) && (SL_TRUSTZONE_PERIPHERAL_CMU_S != 0))) +#define CMU_BASE (CMU_S_BASE) /* CMU base address */ +#else +#define CMU_BASE (CMU_NS_BASE) /* CMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFXO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFXO0_S != 0))) +#define HFXO0_BASE (HFXO0_S_BASE) /* HFXO0 base address */ +#else +#define HFXO0_BASE (HFXO0_NS_BASE) /* HFXO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFXO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_HFRCO0_S) && (SL_TRUSTZONE_PERIPHERAL_HFRCO0_S != 0))) +#define HFRCO0_BASE (HFRCO0_S_BASE) /* HFRCO0 base address */ +#else +#define HFRCO0_BASE (HFRCO0_NS_BASE) /* HFRCO0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_HFRCO0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_FSRCO_S) && (SL_TRUSTZONE_PERIPHERAL_FSRCO_S != 0))) +#define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */ +#else +#define FSRCO_BASE (FSRCO_NS_BASE) /* FSRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_FSRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DPLL0_S) && (SL_TRUSTZONE_PERIPHERAL_DPLL0_S != 0))) +#define DPLL0_BASE (DPLL0_S_BASE) /* DPLL0 base address */ +#else +#define DPLL0_BASE (DPLL0_NS_BASE) /* DPLL0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DPLL0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFXO_S) && (SL_TRUSTZONE_PERIPHERAL_LFXO_S != 0))) +#define LFXO_BASE (LFXO_S_BASE) /* LFXO base address */ +#else +#define LFXO_BASE (LFXO_NS_BASE) /* LFXO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFXO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_LFRCO_S != 0))) +#define LFRCO_BASE (LFRCO_S_BASE) /* LFRCO base address */ +#else +#define LFRCO_BASE (LFRCO_NS_BASE) /* LFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ULFRCO_S) && (SL_TRUSTZONE_PERIPHERAL_ULFRCO_S != 0))) +#define ULFRCO_BASE (ULFRCO_S_BASE) /* ULFRCO base address */ +#else +#define ULFRCO_BASE (ULFRCO_NS_BASE) /* ULFRCO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ULFRCO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_MSC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_MSC_S) && (SL_TRUSTZONE_PERIPHERAL_MSC_S != 0))) +#define MSC_BASE (MSC_S_BASE) /* MSC base address */ +#else +#define MSC_BASE (MSC_NS_BASE) /* MSC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_MSC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_ICACHE0_S) && (SL_TRUSTZONE_PERIPHERAL_ICACHE0_S != 0))) +#define ICACHE0_BASE (ICACHE0_S_BASE) /* ICACHE0 base address */ +#else +#define ICACHE0_BASE (ICACHE0_NS_BASE) /* ICACHE0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_ICACHE0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRS_S) && (SL_TRUSTZONE_PERIPHERAL_PRS_S != 0))) +#define PRS_BASE (PRS_S_BASE) /* PRS base address */ +#else +#define PRS_BASE (PRS_NS_BASE) /* PRS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPIO_S) && (SL_TRUSTZONE_PERIPHERAL_GPIO_S != 0))) +#define GPIO_BASE (GPIO_S_BASE) /* GPIO base address */ +#else +#define GPIO_BASE (GPIO_NS_BASE) /* GPIO base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPIO_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMA_S) && (SL_TRUSTZONE_PERIPHERAL_LDMA_S != 0))) +#define LDMA_BASE (LDMA_S_BASE) /* LDMA base address */ +#else +#define LDMA_BASE (LDMA_NS_BASE) /* LDMA base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMA_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S) && (SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S != 0))) +#define LDMAXBAR_BASE (LDMAXBAR_S_BASE) /* LDMAXBAR base address */ +#else +#define LDMAXBAR_BASE (LDMAXBAR_NS_BASE) /* LDMAXBAR base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LDMAXBAR_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER0_S != 0))) +#define TIMER0_BASE (TIMER0_S_BASE) /* TIMER0 base address */ +#else +#define TIMER0_BASE (TIMER0_NS_BASE) /* TIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER1_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER1_S != 0))) +#define TIMER1_BASE (TIMER1_S_BASE) /* TIMER1 base address */ +#else +#define TIMER1_BASE (TIMER1_NS_BASE) /* TIMER1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER2_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER2_S != 0))) +#define TIMER2_BASE (TIMER2_S_BASE) /* TIMER2 base address */ +#else +#define TIMER2_BASE (TIMER2_NS_BASE) /* TIMER2 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER2_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER3_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER3_S != 0))) +#define TIMER3_BASE (TIMER3_S_BASE) /* TIMER3 base address */ +#else +#define TIMER3_BASE (TIMER3_NS_BASE) /* TIMER3 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER3_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_TIMER4_S) && (SL_TRUSTZONE_PERIPHERAL_TIMER4_S != 0))) +#define TIMER4_BASE (TIMER4_S_BASE) /* TIMER4 base address */ +#else +#define TIMER4_BASE (TIMER4_NS_BASE) /* TIMER4 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_TIMER4_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART0_S) && (SL_TRUSTZONE_PERIPHERAL_USART0_S != 0))) +#define USART0_BASE (USART0_S_BASE) /* USART0 base address */ +#else +#define USART0_BASE (USART0_NS_BASE) /* USART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_USART1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_USART1_S) && (SL_TRUSTZONE_PERIPHERAL_USART1_S != 0))) +#define USART1_BASE (USART1_S_BASE) /* USART1 base address */ +#else +#define USART1_BASE (USART1_NS_BASE) /* USART1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_USART1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURTC_S) && (SL_TRUSTZONE_PERIPHERAL_BURTC_S != 0))) +#define BURTC_BASE (BURTC_S_BASE) /* BURTC base address */ +#else +#define BURTC_BASE (BURTC_NS_BASE) /* BURTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURTC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C1_S) && (SL_TRUSTZONE_PERIPHERAL_I2C1_S != 0))) +#define I2C1_BASE (I2C1_S_BASE) /* I2C1 base address */ +#else +#define I2C1_BASE (I2C1_NS_BASE) /* I2C1 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C1_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S != 0))) +#define SYSCFG_CFGNS_BASE (SYSCFG_S_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#else +#define SYSCFG_CFGNS_BASE (SYSCFG_NS_CFGNS_BASE) /* SYSCFG_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SYSCFG_S) && (SL_TRUSTZONE_PERIPHERAL_SYSCFG_S != 0))) +#define SYSCFG_BASE (SYSCFG_S_BASE) /* SYSCFG base address */ +#else +#define SYSCFG_BASE (SYSCFG_NS_BASE) /* SYSCFG base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SYSCFG_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_BURAM_S) && (SL_TRUSTZONE_PERIPHERAL_BURAM_S != 0))) +#define BURAM_BASE (BURAM_S_BASE) /* BURAM base address */ +#else +#define BURAM_BASE (BURAM_NS_BASE) /* BURAM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_BURAM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_GPCRC_S) && (SL_TRUSTZONE_PERIPHERAL_GPCRC_S != 0))) +#define GPCRC_BASE (GPCRC_S_BASE) /* GPCRC base address */ +#else +#define GPCRC_BASE (GPCRC_NS_BASE) /* GPCRC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_GPCRC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_DCDC_S) && (SL_TRUSTZONE_PERIPHERAL_DCDC_S != 0))) +#define DCDC_BASE (DCDC_S_BASE) /* DCDC base address */ +#else +#define DCDC_BASE (DCDC_NS_BASE) /* DCDC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_DCDC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PDM_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PDM_S) && (SL_TRUSTZONE_PERIPHERAL_PDM_S != 0))) +#define PDM_BASE (PDM_S_BASE) /* PDM base address */ +#else +#define PDM_BASE (PDM_NS_BASE) /* PDM base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PDM_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RADIOAES_S) && (SL_TRUSTZONE_PERIPHERAL_RADIOAES_S != 0))) +#define RADIOAES_BASE (RADIOAES_S_BASE) /* RADIOAES base address */ +#else +#define RADIOAES_BASE (RADIOAES_NS_BASE) /* RADIOAES base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RADIOAES_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_S != 0))) +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#else +#define SMU_BASE (SMU_S_BASE) /* SMU base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S) && (SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S != 0))) +#define SMU_CFGNS_BASE (SMU_S_CFGNS_BASE) /* SMU_CFGNS base address */ +#else +#define SMU_CFGNS_BASE (SMU_NS_CFGNS_BASE) /* SMU_CFGNS base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_SMU_CFGNS_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_RTCC_S) && (SL_TRUSTZONE_PERIPHERAL_RTCC_S != 0))) +#define RTCC_BASE (RTCC_S_BASE) /* RTCC base address */ +#else +#define RTCC_BASE (RTCC_NS_BASE) /* RTCC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_RTCC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_LETIMER0_S) && (SL_TRUSTZONE_PERIPHERAL_LETIMER0_S != 0))) +#define LETIMER0_BASE (LETIMER0_S_BASE) /* LETIMER0 base address */ +#else +#define LETIMER0_BASE (LETIMER0_NS_BASE) /* LETIMER0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_LETIMER0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_IADC0_S) && (SL_TRUSTZONE_PERIPHERAL_IADC0_S != 0))) +#define IADC0_BASE (IADC0_S_BASE) /* IADC0 base address */ +#else +#define IADC0_BASE (IADC0_NS_BASE) /* IADC0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_IADC0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_I2C0_S) && (SL_TRUSTZONE_PERIPHERAL_I2C0_S != 0))) +#define I2C0_BASE (I2C0_S_BASE) /* I2C0 base address */ +#else +#define I2C0_BASE (I2C0_NS_BASE) /* I2C0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_I2C0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_WDOG0_S) && (SL_TRUSTZONE_PERIPHERAL_WDOG0_S != 0))) +#define WDOG0_BASE (WDOG0_S_BASE) /* WDOG0 base address */ +#else +#define WDOG0_BASE (WDOG0_NS_BASE) /* WDOG0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_WDOG0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_EUART0_S) && (SL_TRUSTZONE_PERIPHERAL_EUART0_S != 0))) +#define EUART0_BASE (EUART0_S_BASE) /* EUART0 base address */ +#else +#define EUART0_BASE (EUART0_NS_BASE) /* EUART0 base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_EUART0_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S != 0))) +#define CRYPTOACC_BASE (CRYPTOACC_S_BASE) /* CRYPTOACC base address */ +#else +#define CRYPTOACC_BASE (CRYPTOACC_NS_BASE) /* CRYPTOACC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S != 0))) +#define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_S_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ +#else +#define CRYPTOACC_RNGCTRL_BASE (CRYPTOACC_NS_RNGCTRL_BASE) /* CRYPTOACC_RNGCTRL base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_RNGCTRL_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S) && (SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S != 0))) +#define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_S_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ +#else +#define CRYPTOACC_PKCTRL_BASE (CRYPTOACC_NS_PKCTRL_BASE) /* CRYPTOACC_PKCTRL base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_CRYPTOACC_PKCTRL_S +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S)) || (defined(SL_TRUSTZONE_PERIPHERAL_PRORTC_S) && (SL_TRUSTZONE_PERIPHERAL_PRORTC_S != 0))) +#define PRORTC_BASE (PRORTC_S_BASE) /* PRORTC base address */ +#else +#define PRORTC_BASE (PRORTC_NS_BASE) /* PRORTC base address */ +#endif // SL_TRUSTZONE_PERIPHERAL_PRORTC_S + +#define DEVINFO_BASE (0x0FE08000UL) /* DEVINFO base address */ +/** @} End of group EFR32BG22C224F512IM40_Peripheral_Base */ + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40_Peripheral_Declaration EFR32BG22C224F512IM40 Peripheral Declarations Map + * @{ + *****************************************************************************/ + +#define EMU_S ((EMU_TypeDef *) EMU_S_BASE) /**< EMU_S base pointer */ +#define CMU_S ((CMU_TypeDef *) CMU_S_BASE) /**< CMU_S base pointer */ +#define HFXO0_S ((HFXO_TypeDef *) HFXO0_S_BASE) /**< HFXO0_S base pointer */ +#define HFRCO0_S ((HFRCO_TypeDef *) HFRCO0_S_BASE) /**< HFRCO0_S base pointer */ +#define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base pointer */ +#define DPLL0_S ((DPLL_TypeDef *) DPLL0_S_BASE) /**< DPLL0_S base pointer */ +#define LFXO_S ((LFXO_TypeDef *) LFXO_S_BASE) /**< LFXO_S base pointer */ +#define LFRCO_S ((LFRCO_TypeDef *) LFRCO_S_BASE) /**< LFRCO_S base pointer */ +#define ULFRCO_S ((ULFRCO_TypeDef *) ULFRCO_S_BASE) /**< ULFRCO_S base pointer */ +#define MSC_S ((MSC_TypeDef *) MSC_S_BASE) /**< MSC_S base pointer */ +#define ICACHE0_S ((ICACHE_TypeDef *) ICACHE0_S_BASE) /**< ICACHE0_S base pointer */ +#define PRS_S ((PRS_TypeDef *) PRS_S_BASE) /**< PRS_S base pointer */ +#define GPIO_S ((GPIO_TypeDef *) GPIO_S_BASE) /**< GPIO_S base pointer */ +#define LDMA_S ((LDMA_TypeDef *) LDMA_S_BASE) /**< LDMA_S base pointer */ +#define LDMAXBAR_S ((LDMAXBAR_TypeDef *) LDMAXBAR_S_BASE) /**< LDMAXBAR_S base pointer */ +#define TIMER0_S ((TIMER_TypeDef *) TIMER0_S_BASE) /**< TIMER0_S base pointer */ +#define TIMER1_S ((TIMER_TypeDef *) TIMER1_S_BASE) /**< TIMER1_S base pointer */ +#define TIMER2_S ((TIMER_TypeDef *) TIMER2_S_BASE) /**< TIMER2_S base pointer */ +#define TIMER3_S ((TIMER_TypeDef *) TIMER3_S_BASE) /**< TIMER3_S base pointer */ +#define TIMER4_S ((TIMER_TypeDef *) TIMER4_S_BASE) /**< TIMER4_S base pointer */ +#define USART0_S ((USART_TypeDef *) USART0_S_BASE) /**< USART0_S base pointer */ +#define USART1_S ((USART_TypeDef *) USART1_S_BASE) /**< USART1_S base pointer */ +#define BURTC_S ((BURTC_TypeDef *) BURTC_S_BASE) /**< BURTC_S base pointer */ +#define I2C1_S ((I2C_TypeDef *) I2C1_S_BASE) /**< I2C1_S base pointer */ +#define SYSCFG_S_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_S_CFGNS_BASE) /**< SYSCFG_S_CFGNS base pointer */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_S_BASE) /**< SYSCFG_S base pointer */ +#define BURAM_S ((BURAM_TypeDef *) BURAM_S_BASE) /**< BURAM_S base pointer */ +#define GPCRC_S ((GPCRC_TypeDef *) GPCRC_S_BASE) /**< GPCRC_S base pointer */ +#define DCDC_S ((DCDC_TypeDef *) DCDC_S_BASE) /**< DCDC_S base pointer */ +#define PDM_S ((PDM_TypeDef *) PDM_S_BASE) /**< PDM_S base pointer */ +#define RADIOAES_S ((AES_TypeDef *) RADIOAES_S_BASE) /**< RADIOAES_S base pointer */ +#define SMU_S ((SMU_TypeDef *) SMU_S_BASE) /**< SMU_S base pointer */ +#define SMU_S_CFGNS ((SMU_CFGNS_TypeDef *) SMU_S_CFGNS_BASE) /**< SMU_S_CFGNS base pointer */ +#define RTCC_S ((RTCC_TypeDef *) RTCC_S_BASE) /**< RTCC_S base pointer */ +#define LETIMER0_S ((LETIMER_TypeDef *) LETIMER0_S_BASE) /**< LETIMER0_S base pointer */ +#define IADC0_S ((IADC_TypeDef *) IADC0_S_BASE) /**< IADC0_S base pointer */ +#define I2C0_S ((I2C_TypeDef *) I2C0_S_BASE) /**< I2C0_S base pointer */ +#define WDOG0_S ((WDOG_TypeDef *) WDOG0_S_BASE) /**< WDOG0_S base pointer */ +#define EUART0_S ((EUSART_TypeDef *) EUART0_S_BASE) /**< EUART0_S base pointer */ +#define CRYPTOACC_S ((CRYPTOACC_TypeDef *) CRYPTOACC_S_BASE) /**< CRYPTOACC_S base pointer */ +#define CRYPTOACC_S_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_S_RNGCTRL_BASE) /**< CRYPTOACC_S_RNGCTRL base pointer */ +#define CRYPTOACC_S_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_S_PKCTRL_BASE) /**< CRYPTOACC_S_PKCTRL base pointer */ +#define PRORTC_S ((RTCC_TypeDef *) PRORTC_S_BASE) /**< PRORTC_S base pointer */ +#define EMU_NS ((EMU_TypeDef *) EMU_NS_BASE) /**< EMU_NS base pointer */ +#define CMU_NS ((CMU_TypeDef *) CMU_NS_BASE) /**< CMU_NS base pointer */ +#define HFXO0_NS ((HFXO_TypeDef *) HFXO0_NS_BASE) /**< HFXO0_NS base pointer */ +#define HFRCO0_NS ((HFRCO_TypeDef *) HFRCO0_NS_BASE) /**< HFRCO0_NS base pointer */ +#define FSRCO_NS ((FSRCO_TypeDef *) FSRCO_NS_BASE) /**< FSRCO_NS base pointer */ +#define DPLL0_NS ((DPLL_TypeDef *) DPLL0_NS_BASE) /**< DPLL0_NS base pointer */ +#define LFXO_NS ((LFXO_TypeDef *) LFXO_NS_BASE) /**< LFXO_NS base pointer */ +#define LFRCO_NS ((LFRCO_TypeDef *) LFRCO_NS_BASE) /**< LFRCO_NS base pointer */ +#define ULFRCO_NS ((ULFRCO_TypeDef *) ULFRCO_NS_BASE) /**< ULFRCO_NS base pointer */ +#define MSC_NS ((MSC_TypeDef *) MSC_NS_BASE) /**< MSC_NS base pointer */ +#define ICACHE0_NS ((ICACHE_TypeDef *) ICACHE0_NS_BASE) /**< ICACHE0_NS base pointer */ +#define PRS_NS ((PRS_TypeDef *) PRS_NS_BASE) /**< PRS_NS base pointer */ +#define GPIO_NS ((GPIO_TypeDef *) GPIO_NS_BASE) /**< GPIO_NS base pointer */ +#define LDMA_NS ((LDMA_TypeDef *) LDMA_NS_BASE) /**< LDMA_NS base pointer */ +#define LDMAXBAR_NS ((LDMAXBAR_TypeDef *) LDMAXBAR_NS_BASE) /**< LDMAXBAR_NS base pointer */ +#define TIMER0_NS ((TIMER_TypeDef *) TIMER0_NS_BASE) /**< TIMER0_NS base pointer */ +#define TIMER1_NS ((TIMER_TypeDef *) TIMER1_NS_BASE) /**< TIMER1_NS base pointer */ +#define TIMER2_NS ((TIMER_TypeDef *) TIMER2_NS_BASE) /**< TIMER2_NS base pointer */ +#define TIMER3_NS ((TIMER_TypeDef *) TIMER3_NS_BASE) /**< TIMER3_NS base pointer */ +#define TIMER4_NS ((TIMER_TypeDef *) TIMER4_NS_BASE) /**< TIMER4_NS base pointer */ +#define USART0_NS ((USART_TypeDef *) USART0_NS_BASE) /**< USART0_NS base pointer */ +#define USART1_NS ((USART_TypeDef *) USART1_NS_BASE) /**< USART1_NS base pointer */ +#define BURTC_NS ((BURTC_TypeDef *) BURTC_NS_BASE) /**< BURTC_NS base pointer */ +#define I2C1_NS ((I2C_TypeDef *) I2C1_NS_BASE) /**< I2C1_NS base pointer */ +#define SYSCFG_NS_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_NS_CFGNS_BASE) /**< SYSCFG_NS_CFGNS base pointer */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_NS_BASE) /**< SYSCFG_NS base pointer */ +#define BURAM_NS ((BURAM_TypeDef *) BURAM_NS_BASE) /**< BURAM_NS base pointer */ +#define GPCRC_NS ((GPCRC_TypeDef *) GPCRC_NS_BASE) /**< GPCRC_NS base pointer */ +#define DCDC_NS ((DCDC_TypeDef *) DCDC_NS_BASE) /**< DCDC_NS base pointer */ +#define PDM_NS ((PDM_TypeDef *) PDM_NS_BASE) /**< PDM_NS base pointer */ +#define RADIOAES_NS ((AES_TypeDef *) RADIOAES_NS_BASE) /**< RADIOAES_NS base pointer */ +#define SMU_NS ((SMU_TypeDef *) SMU_NS_BASE) /**< SMU_NS base pointer */ +#define SMU_NS_CFGNS ((SMU_CFGNS_TypeDef *) SMU_NS_CFGNS_BASE) /**< SMU_NS_CFGNS base pointer */ +#define RTCC_NS ((RTCC_TypeDef *) RTCC_NS_BASE) /**< RTCC_NS base pointer */ +#define LETIMER0_NS ((LETIMER_TypeDef *) LETIMER0_NS_BASE) /**< LETIMER0_NS base pointer */ +#define IADC0_NS ((IADC_TypeDef *) IADC0_NS_BASE) /**< IADC0_NS base pointer */ +#define I2C0_NS ((I2C_TypeDef *) I2C0_NS_BASE) /**< I2C0_NS base pointer */ +#define WDOG0_NS ((WDOG_TypeDef *) WDOG0_NS_BASE) /**< WDOG0_NS base pointer */ +#define EUART0_NS ((EUSART_TypeDef *) EUART0_NS_BASE) /**< EUART0_NS base pointer */ +#define CRYPTOACC_NS ((CRYPTOACC_TypeDef *) CRYPTOACC_NS_BASE) /**< CRYPTOACC_NS base pointer */ +#define CRYPTOACC_NS_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_NS_RNGCTRL_BASE) /**< CRYPTOACC_NS_RNGCTRL base pointer */ +#define CRYPTOACC_NS_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_NS_PKCTRL_BASE) /**< CRYPTOACC_NS_PKCTRL base pointer */ +#define PRORTC_NS ((RTCC_TypeDef *) PRORTC_NS_BASE) /**< PRORTC_NS base pointer */ +#define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */ +#define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */ +#define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base pointer */ +#define HFRCO0 ((HFRCO_TypeDef *) HFRCO0_BASE) /**< HFRCO0 base pointer */ +#define FSRCO ((FSRCO_TypeDef *) FSRCO_BASE) /**< FSRCO base pointer */ +#define DPLL0 ((DPLL_TypeDef *) DPLL0_BASE) /**< DPLL0 base pointer */ +#define LFXO ((LFXO_TypeDef *) LFXO_BASE) /**< LFXO base pointer */ +#define LFRCO ((LFRCO_TypeDef *) LFRCO_BASE) /**< LFRCO base pointer */ +#define ULFRCO ((ULFRCO_TypeDef *) ULFRCO_BASE) /**< ULFRCO base pointer */ +#define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */ +#define ICACHE0 ((ICACHE_TypeDef *) ICACHE0_BASE) /**< ICACHE0 base pointer */ +#define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */ +#define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */ +#define LDMA ((LDMA_TypeDef *) LDMA_BASE) /**< LDMA base pointer */ +#define LDMAXBAR ((LDMAXBAR_TypeDef *) LDMAXBAR_BASE) /**< LDMAXBAR base pointer */ +#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */ +#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */ +#define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */ +#define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */ +#define TIMER4 ((TIMER_TypeDef *) TIMER4_BASE) /**< TIMER4 base pointer */ +#define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */ +#define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */ +#define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */ +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */ +#define SYSCFG_CFGNS ((SYSCFG_CFGNS_TypeDef *) SYSCFG_CFGNS_BASE) /**< SYSCFG_CFGNS base pointer */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) /**< SYSCFG base pointer */ +#define BURAM ((BURAM_TypeDef *) BURAM_BASE) /**< BURAM base pointer */ +#define GPCRC ((GPCRC_TypeDef *) GPCRC_BASE) /**< GPCRC base pointer */ +#define DCDC ((DCDC_TypeDef *) DCDC_BASE) /**< DCDC base pointer */ +#define PDM ((PDM_TypeDef *) PDM_BASE) /**< PDM base pointer */ +#define RADIOAES ((AES_TypeDef *) RADIOAES_BASE) /**< RADIOAES base pointer */ +#define SMU ((SMU_TypeDef *) SMU_BASE) /**< SMU base pointer */ +#define SMU_CFGNS ((SMU_CFGNS_TypeDef *) SMU_CFGNS_BASE) /**< SMU_CFGNS base pointer */ +#define RTCC ((RTCC_TypeDef *) RTCC_BASE) /**< RTCC base pointer */ +#define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */ +#define IADC0 ((IADC_TypeDef *) IADC0_BASE) /**< IADC0 base pointer */ +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */ +#define WDOG0 ((WDOG_TypeDef *) WDOG0_BASE) /**< WDOG0 base pointer */ +#define EUART0 ((EUSART_TypeDef *) EUART0_BASE) /**< EUART0 base pointer */ +#define CRYPTOACC ((CRYPTOACC_TypeDef *) CRYPTOACC_BASE) /**< CRYPTOACC base pointer */ +#define CRYPTOACC_RNGCTRL ((CRYPTOACC_RNGCTRL_TypeDef *) CRYPTOACC_RNGCTRL_BASE) /**< CRYPTOACC_RNGCTRL base pointer */ +#define CRYPTOACC_PKCTRL ((CRYPTOACC_PKCTRL_TypeDef *) CRYPTOACC_PKCTRL_BASE) /**< CRYPTOACC_PKCTRL base pointer */ +#define PRORTC ((RTCC_TypeDef *) PRORTC_BASE) /**< PRORTC base pointer */ +#define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */ +/** @} End of group EFR32BG22C224F512IM40_Peripheral_Declaration */ + +/**************************************************************************//** + * @defgroup EFR32BG22C224F512IM40_Peripheral_Parameters EFR32BG22C224F512IM40 Peripheral Parameters + * @{ + * @brief Device peripheral parameter values + *****************************************************************************/ + +/* Common peripheral register block offsets. */ +#define PER_REG_BLOCK_SET_OFFSET 0x1000UL /**< Offset to SET register block */ +#define PER_REG_BLOCK_CLR_OFFSET 0x2000UL /**< Offset to CLEAR register block */ +#define PER_REG_BLOCK_TGL_OFFSET 0x3000UL /**< Offset to TOGGLE register block */ +#define MSC_CDA_PRESENT 0x1UL /**> */ +#define MSC_FDIO_WIDTH 0x40UL /**> None */ +#define MSC_FLASHADDRBITS 0x13UL /**> None */ +#define MSC_FLASHBLOCKADDRBITS 0x13UL /**> None */ +#define MSC_FLASH_BLOCK_INFO_PCOUNT 0xCUL /**> None */ +#define MSC_INFOADDRBITS 0x10UL /**> None */ +#define MSC_INFOBLOCKADDRBITS 0x10UL /**> None */ +#define MSC_INFO_PSIZE_BITS 0xCUL /**> None */ +#define MSC_MAIN_PSIZE_BITS 0xCUL /**> None */ +#define MSC_MTP_PRESENT 0x1UL /**> */ +#define MSC_REDUNDANCY 0x2UL /**> None */ +#define MSC_UD_IN_MTP_PAGE 0x0UL /**> */ +#define MSC_YADDRBITS 0x6UL /**> */ +#define SYSROM_WORDS 0x700UL /**> Number of words in ROM */ +#define SYSROM_ROM_SIZE_BYTES 0x1C00UL /**> Number of bytes in ROM */ +#define DMEM_BANK0_SIZE 0x6000UL /**> Bank0 Size */ +#define DMEM_BANK1_SIZE 0x2000UL /**> Bank1 Size */ +#define DMEM_BANK2_SIZE 0x0UL /**> Bank2 Size */ +#define DMEM_BANK3_SIZE 0x0UL /**> Bank3 Size */ +#define DMEM_BANK4_SIZE 0x0UL /**> Bank4 Size */ +#define DMEM_BANK5_SIZE 0x0UL /**> Bank5 Size */ +#define DMEM_BANK6_SIZE 0x0UL /**> Bank6 Size */ +#define DMEM_BANK7_SIZE 0x0UL /**> Bank7 Size */ +#define DMEM_NUM_BANKS 0x2UL /**> Number of Banks */ +#define DMEM_SIZE 0x8000UL /**> Total size */ +#define LFXO_NO_CTUNE 0x0UL /**> CTUNE Not Present */ +#define LFXO_CTUNE 0x1UL /**> CTUNE Present */ +#define ICACHE0_AHB_LITE 0x0UL /**> AHB Lite */ +#define ICACHE0_CACHEABLE_SIZE 0x200UL /**> Cache Size */ +#define ICACHE0_CACHEABLE_START 0x12UL /**> Cache Start */ +#define ICACHE0_DEFAULT_OFF 0x1UL /**> Default off */ +#define ICACHE0_FLASH_SIZE 0x80000UL /**> Flash size */ +#define ICACHE0_FLASH_START 0x0UL /**> Flash start */ +#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS 0x3UL /**> Loopcache Memory Address bits */ +#define ICACHE0_LOOPCACHE_STICKINESS_BITS 0x4UL /**> Loopcache Stickiness bits */ +#define ICACHE0_PARITY_BITS 0x1UL /**> Use Parity */ +#define ICACHE0_PC_BITS 0x20UL /**> Performance Counter bits */ +#define ICACHE0_PIPE_STAGE 0x1UL /**> Pipeline Stage */ +#define ICACHE0_RAM_ADDR_BITS 0x0UL /**> RAM Address bits */ +#define ICACHE0_RAM_DATA_BITS 0x0UL /**> RAM Data bits */ +#define ICACHE0_SET_BITS 0x5UL /**> Set bits */ +#define ICACHE0_USE_HREADY_GATING 0x1UL /**> Use HREADY gating */ +#define ICACHE0_USE_IDLE_GATING 0x1UL /**> Use IDLE gating */ +#define ICACHE0_USE_LOOPCACHE 0x1UL /**> Use Loopcache */ +#define ICACHE0_WAY_BITS 0x1UL /**> Way bits */ +#define ICACHE0_WORDS_PER_BLOCK 0x0UL /**> Words Per Block */ +#define ICACHE0_WPB_BITS 0x1UL /**> Words Per Block bits */ +#define ICACHE0_WPL_BITS 0x3UL /**> Words Per Line bits */ +#define PRS_ASYNC_CH_NUM 0xCUL /**> None */ +#define PRS_PRSSEL_WIDTH 0x4UL /**> New Param */ +#define PRS_SPRSSEL_WIDTH 0x2UL /**> New Param */ +#define PRS_SYNC_CH_NUM 0x4UL /**> None */ +#define GPIO_MODE_WIDTH 0x4UL /**> Mode Width */ +#define GPIO_NUM_EM4_WU 0xCUL /**> New Param */ +#define GPIO_NUM_EVEN_PA 0x5UL /**> Num of even pins port A */ +#define GPIO_NUM_EVEN_PB 0x3UL /**> Num of even pins port B */ +#define GPIO_NUM_EVEN_PC 0x4UL /**> Num of even pins port C */ +#define GPIO_NUM_EVEN_PD 0x2UL /**> Num of even pins port D */ +#define GPIO_NUM_EXT_INT 0xCUL /**> New Param */ +#define GPIO_NUM_EXT_INT_L 0x8UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U 0x4UL /**> New Param */ +#define GPIO_NUM_EXT_INT_U_ZERO 0x0UL /**> New Param */ +#define GPIO_NUM_ODD_PA 0x4UL /**> Num of odd pins port A */ +#define GPIO_NUM_ODD_PB 0x2UL /**> Num of odd pins port B */ +#define GPIO_NUM_ODD_PC 0x4UL /**> Num of odd pins port C */ +#define GPIO_NUM_ODD_PD 0x2UL /**> Num of odd pins port D */ +#define GPIO_PINSEL_WIDTH 0x4UL /**> Route config pin select width */ +#define GPIO_PORTSEL_WIDTH 0x2UL /**> Route config port select width */ +#define GPIO_PORT_A_WIDTH 0x9UL /**> Port A Width */ +#define GPIO_PORT_A_WIDTH_ZERO 0x0UL /**> Port A Width is Zero */ +#define GPIO_PORT_A_WL 0x8UL /**> New Param */ +#define GPIO_PORT_A_WU 0x1UL /**> New Param */ +#define GPIO_PORT_A_WU_ZERO 0x0UL /**> New Param */ +#define GPIO_PORT_B_WIDTH 0x5UL /**> Port B Width */ +#define GPIO_PORT_B_WIDTH_ZERO 0x0UL /**> Port B Width is Zero */ +#define GPIO_PORT_B_WL 0x5UL /**> New Param */ +#define GPIO_PORT_B_WU 0x0UL /**> New Param */ +#define GPIO_PORT_B_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_C_WIDTH 0x8UL /**> Port C Width */ +#define GPIO_PORT_C_WIDTH_ZERO 0x0UL /**> Port C Width is Zero */ +#define GPIO_PORT_C_WL 0x8UL /**> New Param */ +#define GPIO_PORT_C_WU 0x0UL /**> New Param */ +#define GPIO_PORT_C_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_PORT_D_WIDTH 0x4UL /**> Port D Width */ +#define GPIO_PORT_D_WIDTH_ZERO 0x0UL /**> Port D Width is Zero */ +#define GPIO_PORT_D_WL 0x4UL /**> New Param */ +#define GPIO_PORT_D_WU 0x0UL /**> New Param */ +#define GPIO_PORT_D_WU_ZERO 0x1UL /**> New Param */ +#define GPIO_SLEWRATE_WIDTH 0x3UL /**> Slew Rate Width Param */ +#define LDMA_CH_BITS 0x5UL /**> New Param */ +#define LDMA_CH_NUM 0x8UL /**> New Param */ +#define LDMA_FIFO_BITS 0x5UL /**> New Param */ +#define LDMA_FIFO_DEPTH 0x10UL /**> New Param */ +#define LDMAXBAR_CH_BITS 0x5UL /**> None */ +#define LDMAXBAR_CH_NUM 0x8UL /**> None */ +#define LDMAXBAR_SIGSEL_W 0x4UL /**> New Param */ +#define LDMAXBAR_SOURCESEL_W 0x6UL /**> New Param */ +#define TIMER0_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER0_CNTWIDTH 0x20UL /**> Counter Width */ +#define TIMER0_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER0_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER0_NO_DTI 0x0UL /**> */ +#define TIMER1_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER1_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER1_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER1_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER1_NO_DTI 0x0UL /**> */ +#define TIMER2_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER2_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER2_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER2_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER2_NO_DTI 0x0UL /**> */ +#define TIMER3_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER3_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER3_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER3_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER3_NO_DTI 0x0UL /**> */ +#define TIMER4_CC_NUM 0x3UL /**> Number of Compare/Capture Channels */ +#define TIMER4_CNTWIDTH 0x10UL /**> Counter Width */ +#define TIMER4_DTI 0x1UL /**> Dead-time insertion enabled */ +#define TIMER4_DTI_CC_NUM 0x3UL /**> Number of DTI Channels */ +#define TIMER4_NO_DTI 0x0UL /**> */ +#define USART0_AUTOTX_REG 0x1UL /**> None */ +#define USART0_AUTOTX_REG_B 0x0UL /**> None */ +#define USART0_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART0_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART0_CLK_PRS 0x1UL /**> None */ +#define USART0_CLK_PRS_B 0x0UL /**> New Param */ +#define USART0_FLOW_CONTROL 0x1UL /**> None */ +#define USART0_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART0_I2S 0x1UL /**> None */ +#define USART0_I2S_B 0x0UL /**> New Param */ +#define USART0_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART0_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_MVDIS_FUNC 0x1UL /**> None */ +#define USART0_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART0_RX_PRS 0x1UL /**> None */ +#define USART0_RX_PRS_B 0x0UL /**> New Param */ +#define USART0_SC_AVAILABLE 0x1UL /**> None */ +#define USART0_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART0_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART0_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART0_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART0_TIMER 0x1UL /**> New Param */ +#define USART0_TIMER_B 0x0UL /**> New Param */ +#define USART1_AUTOTX_REG 0x1UL /**> None */ +#define USART1_AUTOTX_REG_B 0x0UL /**> None */ +#define USART1_AUTOTX_TRIGGER 0x1UL /**> None */ +#define USART1_AUTOTX_TRIGGER_B 0x0UL /**> New Param */ +#define USART1_CLK_PRS 0x1UL /**> None */ +#define USART1_CLK_PRS_B 0x0UL /**> New Param */ +#define USART1_FLOW_CONTROL 0x1UL /**> None */ +#define USART1_FLOW_CONTROL_B 0x0UL /**> New Param */ +#define USART1_I2S 0x1UL /**> None */ +#define USART1_I2S_B 0x0UL /**> New Param */ +#define USART1_IRDA_AVAILABLE 0x1UL /**> None */ +#define USART1_IRDA_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_MVDIS_FUNC 0x1UL /**> None */ +#define USART1_MVDIS_FUNC_B 0x0UL /**> New Param */ +#define USART1_RX_PRS 0x1UL /**> None */ +#define USART1_RX_PRS_B 0x0UL /**> New Param */ +#define USART1_SC_AVAILABLE 0x1UL /**> None */ +#define USART1_SC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_AVAILABLE 0x1UL /**> None */ +#define USART1_SYNC_AVAILABLE_B 0x0UL /**> New Param */ +#define USART1_SYNC_LATE_SAMPLE 0x1UL /**> None */ +#define USART1_SYNC_LATE_SAMPLE_B 0x0UL /**> New Param */ +#define USART1_TIMER 0x1UL /**> New Param */ +#define USART1_TIMER_B 0x0UL /**> New Param */ +#define BURTC_CNTWIDTH 0x20UL /**> None */ +#define BURTC_PRECNT_WIDTH 0xFUL /**> */ +#define I2C1_DELAY 0x7D0UL /**> Delay cell selection */ +#define I2C1_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define SYSCFG_CHIP_FAMILY 0x34UL /**> CHIP Family */ +#define SYSCFG_DEMODRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_FRCRAM_INST_COUNT 0x1UL /**> */ +#define SYSCFG_RAM0_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SEQRAM_INST_COUNT 0x2UL /**> None */ +#define SYSCFG_SWINT_NUM 0x4UL /**> Software interupts */ +#define DCDC_DCDCMODE_WIDTH 0x1UL /**> Mode register width */ +#define DCDC_DRVSPEED_WIDTH 0x2UL /**> Drive Speed bitfield width */ +#define DCDC_IPKVAL_WIDTH 0x4UL /**> Peak Current Setting bitfield Width */ +#define DCDC_VCMPIBIAS_WIDTH 0x2UL /**> VCMP ibias bitfield width */ +#define PDM_FIFO_LEN 0x4UL /**> New Param */ +#define PDM_NUM_CH 0x2UL /**> None */ +#define PDM_CH2_PRESENT_B 0x1UL /**> New Param */ +#define PDM_CH3_PRESENT_B 0x1UL /**> New Param */ +#define PDM_NUM_CH_WIDTH 0x1UL /**> New Param */ +#define PDM_PIPELINE 0x0UL /**> None */ +#define PDM_STEREO23_PRESENT_B 0x1UL /**> New Param */ +#define RADIOAES_SIDECHANNEL_COUNTERMEASURES 0x0UL /**> Enable sidechannel counter measures */ +#define SMU_NUM_BMPUS 0x5UL /**> Number of BMPUs */ +#define SMU_NUM_PPU_PERIPHS 0x30UL /**> Number of PPU Peripherals */ +#define SMU_NUM_PPU_PERIPHS_MOD_32 0x10UL /**> Number of PPU Peripherals (mod 32) */ +#define SMU_NUM_PPU_PERIPHS_SUB_32 0x10UL /**> Number of PPU peripherals minus 32 */ +#define SMU_PERIPHID_BITS 0x8UL /**> Bits used for Peripheral ID */ +#define RTCC_CC_NUM 0x3UL /**> None */ +#define LETIMER0_CNT_WIDTH 0x18UL /**> Count Width */ +#define IADC0_CONFIGNUM 0x2UL /**> CONFIG */ +#define IADC0_FULLRANGEUNIPOLAR 0x0UL /**> FULLRANGEUNIPOLAR */ +#define IADC0_SCANBYTES 0x1UL /**> SCANBYTES */ +#define IADC0_ENTRIES 0x10UL /**> ENTRIES */ +#define I2C0_DELAY 0x3E8UL /**> Delay cell selection */ +#define I2C0_DELAY_CHAIN_NUM 0x2UL /**> Number of delay chain */ +#define WDOG0_PCNUM 0x2UL /**> None */ +#define EUART0_USE_AS_LEUART 0x1UL /**> LEUART instace */ +#define EUART0_USE_AS_UART 0x0UL /**> UART instance */ +#define RDMEM_FRC_BANK0_SIZE 0x1000UL /**> FRC_RAM_BANK0_SIZE */ +#define RDMEM_FRC_BANK1_SIZE 0x0UL /**> FRC_RAM_BANK1_SIZE */ +#define RDMEM_FRC_BANK2_SIZE 0x0UL /**> FRC_RAM_BANK2_SIZE */ +#define RDMEM_FRC_BANK3_SIZE 0x0UL /**> FRC_RAM_BANK3_SIZE */ +#define RDMEM_FRC_BANK4_SIZE 0x0UL /**> FRC_RAM_BANK4_SIZE */ +#define RDMEM_FRC_BANK5_SIZE 0x0UL /**> FRC_RAM_BANK5_SIZE */ +#define RDMEM_FRC_BANK6_SIZE 0x0UL /**> FRC_RAM_BANK6_SIZE */ +#define RDMEM_FRC_BANK7_SIZE 0x0UL /**> FRC_RAM_BANK7_SIZE */ +#define RDMEM_FRC_NUM_BANK 0x1UL /**> FRC_NUM_BANK */ +#define RDMEM_FRC_RAMADDRBITS 0xCUL /**> FRC RAM ADDRBITS */ +#define RDMEM_FRC_RAMADDRMINBITS 0xCUL /**> FRC RAM address bits for one bank */ +#define RDMEM_FRC_RAMECCADDR_WIDTH 0x20UL /**> FRC RAM ECC Address width */ +#define RDMEM_FRC_RAM_BWE_WIDTH 0x27UL /**> FRCRAM BWE width */ +#define RDMEM_FRC_RAM_DATA_WIDTH 0x27UL /**> FRC_RAM_DATA_WIDTH */ +#define RDMEM_FRC_RAM_ECC_EN 0x1UL /**> FRC RAM ECCEN */ +#define RDMEM_FRC_RAM_TOTAL_SIZE 0x1000UL /**> FRC_RAM_TOTAL_SIZE */ +#define RDMEM_SEQ_BANK0_SIZE 0x2000UL /**> SEQ_RAM_BANK0_SIZE */ +#define RDMEM_SEQ_BANK1_SIZE 0x2000UL /**> SEQ_RAM_BANK1_SIZE */ +#define RDMEM_SEQ_BANK2_SIZE 0x0UL /**> SEQ_RAM_BANK2_SIZE */ +#define RDMEM_SEQ_BANK3_SIZE 0x0UL /**> SEQ_RAM_BANK3_SIZE */ +#define RDMEM_SEQ_BANK4_SIZE 0x0UL /**> SEQ_RAM_BANK4_SIZE */ +#define RDMEM_SEQ_BANK5_SIZE 0x0UL /**> SEQ_RAM_BANK5_SIZE */ +#define RDMEM_SEQ_BANK6_SIZE 0x0UL /**> SEQ_RAM_BANK6_SIZE */ +#define RDMEM_SEQ_BANK7_SIZE 0x0UL /**> SEQ_RAM_BANK7_SIZE */ +#define RDMEM_SEQ_NUM_BANK 0x2UL /**> SEQ_NUM_BANK */ +#define RDMEM_SEQ_RAMADDRBITS 0xEUL /**> SEQ RAM ADDRBITS */ +#define RDMEM_SEQ_RAMADDRMINBITS 0xDUL /**> SEQ RAM address bits for one bank */ +#define RDMEM_SEQ_RAMECCADDR_WIDTH 0x20UL /**> SEQ RAM ECC Address width */ +#define RDMEM_SEQ_RAM_BWE_WIDTH 0x27UL /**> SEQRAM BWE width */ +#define RDMEM_SEQ_RAM_DATA_WIDTH 0x27UL /**> SEQ_RAM_DATA_WIDTH */ +#define RDMEM_SEQ_RAM_ECC_EN 0x1UL /**> SEQ RAM ECCEN */ +#define RDMEM_SEQ_RAM_TOTAL_SIZE 0x4000UL /**> SEQ_RAM_TOTAL_SIZE */ +#define PRORTC_CC_NUM 0x2UL /**> None */ + +/* Instance macros for I2C */ +#define I2C(n) (((n) == 0) ? I2C0 \ + : ((n) == 1) ? I2C1 \ + : 0x0UL) +#define I2C_NUM(ref) (((ref) == I2C0) ? 0 \ + : ((ref) == I2C1) ? 1 \ + : -1) +#define I2C_DELAY(n) (((n) == 0) ? I2C0_DELAY \ + : ((n) == 1) ? I2C1_DELAY \ + : 0x0UL) +#define I2C_DELAY_CHAIN_NUM(n) (((n) == 0) ? I2C0_DELAY_CHAIN_NUM \ + : ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \ + : 0x0UL) + +/* Instance macros for TIMER */ +#define TIMER(n) (((n) == 0) ? TIMER0 \ + : ((n) == 1) ? TIMER1 \ + : ((n) == 2) ? TIMER2 \ + : ((n) == 3) ? TIMER3 \ + : ((n) == 4) ? TIMER4 \ + : 0x0UL) +#define TIMER_NUM(ref) (((ref) == TIMER0) ? 0 \ + : ((ref) == TIMER1) ? 1 \ + : ((ref) == TIMER2) ? 2 \ + : ((ref) == TIMER3) ? 3 \ + : ((ref) == TIMER4) ? 4 \ + : -1) +#define TIMER_CC_NUM(n) (((n) == 0) ? TIMER0_CC_NUM \ + : ((n) == 1) ? TIMER1_CC_NUM \ + : ((n) == 2) ? TIMER2_CC_NUM \ + : ((n) == 3) ? TIMER3_CC_NUM \ + : ((n) == 4) ? TIMER4_CC_NUM \ + : 0x0UL) +#define TIMER_CNTWIDTH(n) (((n) == 0) ? TIMER0_CNTWIDTH \ + : ((n) == 1) ? TIMER1_CNTWIDTH \ + : ((n) == 2) ? TIMER2_CNTWIDTH \ + : ((n) == 3) ? TIMER3_CNTWIDTH \ + : ((n) == 4) ? TIMER4_CNTWIDTH \ + : 0x0UL) +#define TIMER_DTI(n) (((n) == 0) ? TIMER0_DTI \ + : ((n) == 1) ? TIMER1_DTI \ + : ((n) == 2) ? TIMER2_DTI \ + : ((n) == 3) ? TIMER3_DTI \ + : ((n) == 4) ? TIMER4_DTI \ + : 0x0UL) +#define TIMER_DTI_CC_NUM(n) (((n) == 0) ? TIMER0_DTI_CC_NUM \ + : ((n) == 1) ? TIMER1_DTI_CC_NUM \ + : ((n) == 2) ? TIMER2_DTI_CC_NUM \ + : ((n) == 3) ? TIMER3_DTI_CC_NUM \ + : ((n) == 4) ? TIMER4_DTI_CC_NUM \ + : 0x0UL) +#define TIMER_NO_DTI(n) (((n) == 0) ? TIMER0_NO_DTI \ + : ((n) == 1) ? TIMER1_NO_DTI \ + : ((n) == 2) ? TIMER2_NO_DTI \ + : ((n) == 3) ? TIMER3_NO_DTI \ + : ((n) == 4) ? TIMER4_NO_DTI \ + : 0x0UL) + +/* Instance macros for USART */ +#define USART(n) (((n) == 0) ? USART0 \ + : ((n) == 1) ? USART1 \ + : 0x0UL) +#define USART_NUM(ref) (((ref) == USART0) ? 0 \ + : ((ref) == USART1) ? 1 \ + : -1) +#define USART_AUTOTX_REG(n) (((n) == 0) ? USART0_AUTOTX_REG \ + : ((n) == 1) ? USART1_AUTOTX_REG \ + : 0x0UL) +#define USART_AUTOTX_REG_B(n) (((n) == 0) ? USART0_AUTOTX_REG_B \ + : ((n) == 1) ? USART1_AUTOTX_REG_B \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER \ + : 0x0UL) +#define USART_AUTOTX_TRIGGER_B(n) (((n) == 0) ? USART0_AUTOTX_TRIGGER_B \ + : ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \ + : 0x0UL) +#define USART_CLK_PRS(n) (((n) == 0) ? USART0_CLK_PRS \ + : ((n) == 1) ? USART1_CLK_PRS \ + : 0x0UL) +#define USART_CLK_PRS_B(n) (((n) == 0) ? USART0_CLK_PRS_B \ + : ((n) == 1) ? USART1_CLK_PRS_B \ + : 0x0UL) +#define USART_FLOW_CONTROL(n) (((n) == 0) ? USART0_FLOW_CONTROL \ + : ((n) == 1) ? USART1_FLOW_CONTROL \ + : 0x0UL) +#define USART_FLOW_CONTROL_B(n) (((n) == 0) ? USART0_FLOW_CONTROL_B \ + : ((n) == 1) ? USART1_FLOW_CONTROL_B \ + : 0x0UL) +#define USART_I2S(n) (((n) == 0) ? USART0_I2S \ + : ((n) == 1) ? USART1_I2S \ + : 0x0UL) +#define USART_I2S_B(n) (((n) == 0) ? USART0_I2S_B \ + : ((n) == 1) ? USART1_I2S_B \ + : 0x0UL) +#define USART_IRDA_AVAILABLE(n) (((n) == 0) ? USART0_IRDA_AVAILABLE \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE \ + : 0x0UL) +#define USART_IRDA_AVAILABLE_B(n) (((n) == 0) ? USART0_IRDA_AVAILABLE_B \ + : ((n) == 1) ? USART1_IRDA_AVAILABLE_B \ + : 0x0UL) +#define USART_MVDIS_FUNC(n) (((n) == 0) ? USART0_MVDIS_FUNC \ + : ((n) == 1) ? USART1_MVDIS_FUNC \ + : 0x0UL) +#define USART_MVDIS_FUNC_B(n) (((n) == 0) ? USART0_MVDIS_FUNC_B \ + : ((n) == 1) ? USART1_MVDIS_FUNC_B \ + : 0x0UL) +#define USART_RX_PRS(n) (((n) == 0) ? USART0_RX_PRS \ + : ((n) == 1) ? USART1_RX_PRS \ + : 0x0UL) +#define USART_RX_PRS_B(n) (((n) == 0) ? USART0_RX_PRS_B \ + : ((n) == 1) ? USART1_RX_PRS_B \ + : 0x0UL) +#define USART_SC_AVAILABLE(n) (((n) == 0) ? USART0_SC_AVAILABLE \ + : ((n) == 1) ? USART1_SC_AVAILABLE \ + : 0x0UL) +#define USART_SC_AVAILABLE_B(n) (((n) == 0) ? USART0_SC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_AVAILABLE(n) (((n) == 0) ? USART0_SYNC_AVAILABLE \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE \ + : 0x0UL) +#define USART_SYNC_AVAILABLE_B(n) (((n) == 0) ? USART0_SYNC_AVAILABLE_B \ + : ((n) == 1) ? USART1_SYNC_AVAILABLE_B \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \ + : 0x0UL) +#define USART_SYNC_LATE_SAMPLE_B(n) (((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \ + : ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \ + : 0x0UL) +#define USART_TIMER(n) (((n) == 0) ? USART0_TIMER \ + : ((n) == 1) ? USART1_TIMER \ + : 0x0UL) +#define USART_TIMER_B(n) (((n) == 0) ? USART0_TIMER_B \ + : ((n) == 1) ? USART1_TIMER_B \ + : 0x0UL) + +/** @} End of group EFR32BG22C224F512IM40_Peripheral_Parameters */ + +/** @} End of group EFR32BG22C224F512IM40 */ +/** @}} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h index b8ca91e..d9de59c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/em_device.h @@ -1,85 +1,85 @@ -/**************************************************************************//** - * @file - * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories - * microcontroller devices - * - * This is a convenience header file for defining the part number on the - * build command line, instead of specifying the part specific header file. - * - * @verbatim - * Example: Add "-DEFM32G890F128" to your build options, to define part - * Add "#include "em_device.h" to your source files - - * - * @endverbatim - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#ifndef EM_DEVICE_H -#define EM_DEVICE_H -#if defined(EFR32BG22C112F352GM32) -#include "efr32bg22c112f352gm32.h" - -#elif defined(EFR32BG22C112F352GM40) -#include "efr32bg22c112f352gm40.h" - -#elif defined(EFR32BG22C222F352GM32) -#include "efr32bg22c222f352gm32.h" - -#elif defined(EFR32BG22C222F352GM40) -#include "efr32bg22c222f352gm40.h" - -#elif defined(EFR32BG22C222F352GN32) -#include "efr32bg22c222f352gn32.h" - -#elif defined(EFR32BG22C224F512GM32) -#include "efr32bg22c224f512gm32.h" - -#elif defined(EFR32BG22C224F512GM40) -#include "efr32bg22c224f512gm40.h" - -#elif defined(EFR32BG22C224F512GN32) -#include "efr32bg22c224f512gn32.h" - -#elif defined(EFR32BG22C224F512IM32) -#include "efr32bg22c224f512im32.h" - -#elif defined(EFR32BG22C224F512IM40) -#include "efr32bg22c224f512im40.h" - -#else -#error "em_device.h: PART NUMBER undefined" -#endif - -#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) -#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." -#endif - -#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) -#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." -#endif -#endif /* EM_DEVICE_H */ +/**************************************************************************//** + * @file + * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories + * microcontroller devices + * + * This is a convenience header file for defining the part number on the + * build command line, instead of specifying the part specific header file. + * + * @verbatim + * Example: Add "-DEFM32G890F128" to your build options, to define part + * Add "#include "em_device.h" to your source files + + * + * @endverbatim + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef EM_DEVICE_H +#define EM_DEVICE_H +#if defined(EFR32BG22C112F352GM32) +#include "efr32bg22c112f352gm32.h" + +#elif defined(EFR32BG22C112F352GM40) +#include "efr32bg22c112f352gm40.h" + +#elif defined(EFR32BG22C222F352GM32) +#include "efr32bg22c222f352gm32.h" + +#elif defined(EFR32BG22C222F352GM40) +#include "efr32bg22c222f352gm40.h" + +#elif defined(EFR32BG22C222F352GN32) +#include "efr32bg22c222f352gn32.h" + +#elif defined(EFR32BG22C224F512GM32) +#include "efr32bg22c224f512gm32.h" + +#elif defined(EFR32BG22C224F512GM40) +#include "efr32bg22c224f512gm40.h" + +#elif defined(EFR32BG22C224F512GN32) +#include "efr32bg22c224f512gn32.h" + +#elif defined(EFR32BG22C224F512IM32) +#include "efr32bg22c224f512im32.h" + +#elif defined(EFR32BG22C224F512IM40) +#include "efr32bg22c224f512im40.h" + +#else +#error "em_device.h: PART NUMBER undefined" +#endif + +#if defined(SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_CATALOG_TRUSTZONE_SECURE_CONFIG_PRESENT and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif + +#if defined(SL_TRUSTZONE_SECURE) && defined(SL_TRUSTZONE_NONSECURE) +#error "Can't define SL_TRUSTZONE_SECURE and SL_TRUSTZONE_NONSECURE MACRO at the same time." +#endif +#endif /* EM_DEVICE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h index 969bd8c..84390e1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Include/system_efr32bg22.h @@ -1,233 +1,233 @@ -/**************************************************************************//** - * @file - * @brief CMSIS system header file for EFR32BG22 - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#ifndef SYSTEM_EFR32BG22_H -#define SYSTEM_EFR32BG22_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/***************************************************************************//** - * @addtogroup Parts - * @{ - ******************************************************************************/ -/***************************************************************************//** - * @addtogroup EFR32BG22 EFR32BG22 - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/* Interrupt vectortable entry */ -typedef union { - void (*VECTOR_TABLE_Type)(void); - void *topOfStack; -} tVectorEntry; - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -#if !defined(SYSTEM_NO_STATIC_MEMORY) -extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ -extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ -#endif - -/*Re-direction of IRQn.*/ -#if defined (SL_TRUSTZONE_SECURE) -#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn -#else -#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn -#endif /* SL_TRUSTZONE_SECURE */ - -/*Re-direction of IRQHandler.*/ -#if defined (SL_TRUSTZONE_SECURE) -#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler -#else -#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler -#endif /* SL_TRUSTZONE_SECURE */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void Reset_Handler(void); /**< Reset Handler */ -void NMI_Handler(void); /**< NMI Handler */ -void HardFault_Handler(void); /**< Hard Fault Handler */ -void MemManage_Handler(void); /**< MPU Fault Handler */ -void BusFault_Handler(void); /**< Bus Fault Handler */ -void UsageFault_Handler(void); /**< Usage Fault Handler */ -void SecureFault_Handler(void); /**< Secure Fault Handler */ -void SVC_Handler(void); /**< SVCall Handler */ -void DebugMon_Handler(void); /**< Debug Monitor Handler */ -void PendSV_Handler(void); /**< PendSV Handler */ -void SysTick_Handler(void); /**< SysTick Handler */ - -/* Part Specific Interrupts */ -void CRYPTOACC_IRQHandler(void); /**< CRYPTOACC IRQ Handler */ -void TRNG_IRQHandler(void); /**< TRNG IRQ Handler */ -void PKE_IRQHandler(void); /**< PKE IRQ Handler */ -void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ -void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ -void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ -void EMU_IRQHandler(void); /**< EMU IRQ Handler */ -void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ -void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ -void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ -void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ -void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ -void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ -void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ -void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ -void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ -void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ -void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ -void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ -void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ -void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ -void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ -void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ -void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ -void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ -void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ -void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ -void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ -void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ -void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ -void EMUSE_IRQHandler(void); /**< EMUSE IRQ Handler */ -void AGC_IRQHandler(void); /**< AGC IRQ Handler */ -void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ -void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ -void FRC_IRQHandler(void); /**< FRC IRQ Handler */ -void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ -void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ -void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ -void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ -void RDMAILBOX_IRQHandler(void); /**< RDMAILBOX IRQ Handler */ -void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ -void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */ -void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ -void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ -void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ -void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ -void CMU_IRQHandler(void); /**< CMU IRQ Handler */ -void AES_IRQHandler(void); /**< AES IRQ Handler */ -void IADC_IRQHandler(void); /**< IADC IRQ Handler */ -void MSC_IRQHandler(void); /**< MSC IRQ Handler */ -void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ -void PDM_IRQHandler(void); /**< PDM IRQ Handler */ -void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ -void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ -void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ -void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ -void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ -void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ -void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ -void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ -void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ -void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ -void EUART0_RX_IRQHandler(void); /**< EUART0_RX IRQ Handler */ -void EUART0_TX_IRQHandler(void); /**< EUART0_TX IRQ Handler */ - -#if (__FPU_PRESENT == 1) -void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ -#endif - -uint32_t SystemHCLKGet(void); - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that only if changing the core clock frequency through the EMLIB - * CMU API, this variable will be kept updated. This function is only - * provided for CMSIS compliance and if a user modifies the the core clock - * outside the EMLIB CMU API. - *****************************************************************************/ -static __INLINE uint32_t SystemCoreClockGet(void) -{ - return SystemHCLKGet(); -} - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that only if changing the core clock frequency through the EMLIB - * CMU API, this variable will be kept updated. This function is only - * provided for CMSIS compliance and if a user modifies the the core clock - * outside the EMLIB CMU API. - *****************************************************************************/ -static __INLINE void SystemCoreClockUpdate(void) -{ - SystemHCLKGet(); -} - -void SystemInit(void); -#if !defined(SL_LEGACY_LINKER) -void FlashToRamCopy(uint32_t *from, - uint32_t *to, - uint32_t size); -#endif -uint32_t SystemHFRCODPLLClockGet(void); -void SystemHFRCODPLLClockSet(uint32_t freq); -uint32_t SystemSYSCLKGet(void); -uint32_t SystemMaxCoreClockGet(void); -uint32_t SystemFSRCOClockGet(void); -uint32_t SystemHFXOClockGet(void); -void SystemHFXOClockSet(uint32_t freq); -uint32_t SystemCLKIN0Get(void); -uint32_t SystemLFXOClockGet(void); -void SystemLFXOClockSet(uint32_t freq); -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemULFRCOClockGet(void); - -/** @} End of group */ -/** @} End of group Parts */ - -#ifdef __cplusplus -} -#endif -#endif /* SYSTEM_EFR32BG22_H */ +/**************************************************************************//** + * @file + * @brief CMSIS system header file for EFR32BG22 + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#ifndef SYSTEM_EFR32BG22_H +#define SYSTEM_EFR32BG22_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/***************************************************************************//** + * @addtogroup Parts + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup EFR32BG22 EFR32BG22 + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/* Interrupt vectortable entry */ +typedef union { + void (*VECTOR_TABLE_Type)(void); + void *topOfStack; +} tVectorEntry; + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ +extern uint32_t SystemHfrcoFreq; /**< System HFRCO frequency */ +#endif + +/*Re-direction of IRQn.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQn SMU_S_PRIVILEGED_IRQn +#else +#define SMU_PRIVILEGED_IRQn SMU_NS_PRIVILEGED_IRQn +#endif /* SL_TRUSTZONE_SECURE */ + +/*Re-direction of IRQHandler.*/ +#if defined (SL_TRUSTZONE_SECURE) +#define SMU_PRIVILEGED_IRQHandler SMU_S_PRIVILEGED_IRQHandler +#else +#define SMU_PRIVILEGED_IRQHandler SMU_NS_PRIVILEGED_IRQHandler +#endif /* SL_TRUSTZONE_SECURE */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void Reset_Handler(void); /**< Reset Handler */ +void NMI_Handler(void); /**< NMI Handler */ +void HardFault_Handler(void); /**< Hard Fault Handler */ +void MemManage_Handler(void); /**< MPU Fault Handler */ +void BusFault_Handler(void); /**< Bus Fault Handler */ +void UsageFault_Handler(void); /**< Usage Fault Handler */ +void SecureFault_Handler(void); /**< Secure Fault Handler */ +void SVC_Handler(void); /**< SVCall Handler */ +void DebugMon_Handler(void); /**< Debug Monitor Handler */ +void PendSV_Handler(void); /**< PendSV Handler */ +void SysTick_Handler(void); /**< SysTick Handler */ + +/* Part Specific Interrupts */ +void CRYPTOACC_IRQHandler(void); /**< CRYPTOACC IRQ Handler */ +void TRNG_IRQHandler(void); /**< TRNG IRQ Handler */ +void PKE_IRQHandler(void); /**< PKE IRQ Handler */ +void SMU_SECURE_IRQHandler(void); /**< SMU_SECURE IRQ Handler */ +void SMU_S_PRIVILEGED_IRQHandler(void); /**< SMU_S_PRIVILEGED IRQ Handler */ +void SMU_NS_PRIVILEGED_IRQHandler(void); /**< SMU_NS_PRIVILEGED IRQ Handler */ +void EMU_IRQHandler(void); /**< EMU IRQ Handler */ +void TIMER0_IRQHandler(void); /**< TIMER0 IRQ Handler */ +void TIMER1_IRQHandler(void); /**< TIMER1 IRQ Handler */ +void TIMER2_IRQHandler(void); /**< TIMER2 IRQ Handler */ +void TIMER3_IRQHandler(void); /**< TIMER3 IRQ Handler */ +void TIMER4_IRQHandler(void); /**< TIMER4 IRQ Handler */ +void RTCC_IRQHandler(void); /**< RTCC IRQ Handler */ +void USART0_RX_IRQHandler(void); /**< USART0_RX IRQ Handler */ +void USART0_TX_IRQHandler(void); /**< USART0_TX IRQ Handler */ +void USART1_RX_IRQHandler(void); /**< USART1_RX IRQ Handler */ +void USART1_TX_IRQHandler(void); /**< USART1_TX IRQ Handler */ +void ICACHE0_IRQHandler(void); /**< ICACHE0 IRQ Handler */ +void BURTC_IRQHandler(void); /**< BURTC IRQ Handler */ +void LETIMER0_IRQHandler(void); /**< LETIMER0 IRQ Handler */ +void SYSCFG_IRQHandler(void); /**< SYSCFG IRQ Handler */ +void LDMA_IRQHandler(void); /**< LDMA IRQ Handler */ +void LFXO_IRQHandler(void); /**< LFXO IRQ Handler */ +void LFRCO_IRQHandler(void); /**< LFRCO IRQ Handler */ +void ULFRCO_IRQHandler(void); /**< ULFRCO IRQ Handler */ +void GPIO_ODD_IRQHandler(void); /**< GPIO_ODD IRQ Handler */ +void GPIO_EVEN_IRQHandler(void); /**< GPIO_EVEN IRQ Handler */ +void I2C0_IRQHandler(void); /**< I2C0 IRQ Handler */ +void I2C1_IRQHandler(void); /**< I2C1 IRQ Handler */ +void EMUDG_IRQHandler(void); /**< EMUDG IRQ Handler */ +void EMUSE_IRQHandler(void); /**< EMUSE IRQ Handler */ +void AGC_IRQHandler(void); /**< AGC IRQ Handler */ +void BUFC_IRQHandler(void); /**< BUFC IRQ Handler */ +void FRC_PRI_IRQHandler(void); /**< FRC_PRI IRQ Handler */ +void FRC_IRQHandler(void); /**< FRC IRQ Handler */ +void MODEM_IRQHandler(void); /**< MODEM IRQ Handler */ +void PROTIMER_IRQHandler(void); /**< PROTIMER IRQ Handler */ +void RAC_RSM_IRQHandler(void); /**< RAC_RSM IRQ Handler */ +void RAC_SEQ_IRQHandler(void); /**< RAC_SEQ IRQ Handler */ +void RDMAILBOX_IRQHandler(void); /**< RDMAILBOX IRQ Handler */ +void RFSENSE_IRQHandler(void); /**< RFSENSE IRQ Handler */ +void PRORTC_IRQHandler(void); /**< PRORTC IRQ Handler */ +void SYNTH_IRQHandler(void); /**< SYNTH IRQ Handler */ +void WDOG0_IRQHandler(void); /**< WDOG0 IRQ Handler */ +void HFXO0_IRQHandler(void); /**< HFXO0 IRQ Handler */ +void HFRCO0_IRQHandler(void); /**< HFRCO0 IRQ Handler */ +void CMU_IRQHandler(void); /**< CMU IRQ Handler */ +void AES_IRQHandler(void); /**< AES IRQ Handler */ +void IADC_IRQHandler(void); /**< IADC IRQ Handler */ +void MSC_IRQHandler(void); /**< MSC IRQ Handler */ +void DPLL0_IRQHandler(void); /**< DPLL0 IRQ Handler */ +void PDM_IRQHandler(void); /**< PDM IRQ Handler */ +void SW0_IRQHandler(void); /**< SW0 IRQ Handler */ +void SW1_IRQHandler(void); /**< SW1 IRQ Handler */ +void SW2_IRQHandler(void); /**< SW2 IRQ Handler */ +void SW3_IRQHandler(void); /**< SW3 IRQ Handler */ +void KERNEL0_IRQHandler(void); /**< KERNEL0 IRQ Handler */ +void KERNEL1_IRQHandler(void); /**< KERNEL1 IRQ Handler */ +void M33CTI0_IRQHandler(void); /**< M33CTI0 IRQ Handler */ +void M33CTI1_IRQHandler(void); /**< M33CTI1 IRQ Handler */ +void EMUEFP_IRQHandler(void); /**< EMUEFP IRQ Handler */ +void DCDC_IRQHandler(void); /**< DCDC IRQ Handler */ +void EUART0_RX_IRQHandler(void); /**< EUART0_RX IRQ Handler */ +void EUART0_TX_IRQHandler(void); /**< EUART0_TX IRQ Handler */ + +#if (__FPU_PRESENT == 1) +void FPUEH_IRQHandler(void); /**< FPU IRQ Handler */ +#endif + +uint32_t SystemHCLKGet(void); + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE uint32_t SystemCoreClockGet(void) +{ + return SystemHCLKGet(); +} + +/**************************************************************************//** + * @brief + * Update CMSIS SystemCoreClock variable. + * + * @details + * CMSIS defines a global variable SystemCoreClock that shall hold the + * core frequency in Hz. If the core frequency is dynamically changed, the + * variable must be kept updated in order to be CMSIS compliant. + * + * Notice that only if changing the core clock frequency through the EMLIB + * CMU API, this variable will be kept updated. This function is only + * provided for CMSIS compliance and if a user modifies the the core clock + * outside the EMLIB CMU API. + *****************************************************************************/ +static __INLINE void SystemCoreClockUpdate(void) +{ + SystemHCLKGet(); +} + +void SystemInit(void); +#if !defined(SL_LEGACY_LINKER) +void FlashToRamCopy(uint32_t *from, + uint32_t *to, + uint32_t size); +#endif +uint32_t SystemHFRCODPLLClockGet(void); +void SystemHFRCODPLLClockSet(uint32_t freq); +uint32_t SystemSYSCLKGet(void); +uint32_t SystemMaxCoreClockGet(void); +uint32_t SystemFSRCOClockGet(void); +uint32_t SystemHFXOClockGet(void); +void SystemHFXOClockSet(uint32_t freq); +uint32_t SystemCLKIN0Get(void); +uint32_t SystemLFXOClockGet(void); +void SystemLFXOClockSet(uint32_t freq); +uint32_t SystemLFRCOClockGet(void); +uint32_t SystemULFRCOClockGet(void); + +/** @} End of group */ +/** @} End of group Parts */ + +#ifdef __cplusplus +} +#endif +#endif /* SYSTEM_EFR32BG22_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c index 2c22f9f..99a4a61 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c @@ -1,406 +1,406 @@ -/****************************************************************************** -* @file startup_efr32bg22.c -* @brief CMSIS-Core(M) Device Startup File for -* Device EFR32BG22 -* @version V2.1.0 -* @date 16. December 2020 -******************************************************************************* -* # License -* -* The licensor of this software is Silicon Laboratories Inc. Your use of this -* software is governed by the terms of Silicon Labs Master Software License -* Agreement (MSLA) available at -* www.silabs.com/about-us/legal/master-software-license-agreement. This -* software is Third Party Software licensed by Silicon Labs from a third party -* and is governed by the sections of the MSLA applicable to Third Party -* Software and the additional terms set forth below. -* -******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "em_device.h" - -#ifdef BOOTLOADER_ENABLE -#include "api/btl_interface.h" - -#endif // BOOTLOADER_ENABLE -#ifdef SL_APP_PROPERTIES -#include "api/application_properties.h" - -#endif // SL_APP_PROPERTIES - -#define TOTAL_INTERRUPTS (16 + EXT_IRQ_COUNT) - -#ifdef BOOTLOADER_ENABLE -extern MainBootloaderTable_t mainStageTable; -extern void SystemInit2(void); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void (*VECTOR_TABLE_Type)(void); -#endif - -#ifdef SL_APP_PROPERTIES -extern ApplicationProperties_t sl_app_properties; - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void (*VECTOR_TABLE_Type)(void); -#endif - -/*--------------------------------------------------------------------------- - * External References - *---------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -#if defined (SL_TRUSTZONE_SECURE) -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint64_t __STACK_SEAL; -#endif // __ARM_FEATURE_CMSE -#endif // SL_TRUSTZONE_SECURE - -extern __NO_RETURN void __PROGRAM_START(void); - -#if defined (__START) && defined (__GNUC__) -extern int __START(void) __attribute__((noreturn)); /* main entry point */ -void Copy_Table(); -void Zero_Table(); -#endif // __START -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) -// Function to copy RAM functions from Flash to RAM at startup time -void CopyRamFuncs(); -#endif -#endif - -/*--------------------------------------------------------------------------- - * Internal References - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void); -void Default_Handler(void); - -#if defined (__GNUC__) -#ifndef __STACK_SIZE -#define __STACK_SIZE 0x00000400 -#endif // __STACK_SIZE - -#ifndef __HEAP_SIZE -#define __HEAP_SIZE 0x00000C00 -#endif // __HEAP_SIZE -#endif // __GNUC__ - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Cortex-M Processor Exceptions */ -void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); -#ifndef SL_APP_PROPERTIES -/* Provide a dummy value for the sl_app_properties symbol. */ -void sl_app_properties(void); /* Prototype to please MISRA checkers. */ -void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - -/* Part Specific Interrupts */ -void CRYPTOACC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TRNG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PKE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_S_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMUSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RDMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void RFSENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PRORTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); -void EUART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); - -/*---------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined (__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif // __GNUC__ - -#if defined (__ICCARM__) -#pragma data_alignment=512 -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { -#elif defined(__GNUC__) -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __attribute__((aligned(512))) -__VECTOR_TABLE_ATTRIBUTE = { -#else -extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; -const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { -#endif - { .topOfStack = &__INITIAL_SP }, /* Initial Stack Pointer */ - { Reset_Handler }, /* Reset Handler */ - { NMI_Handler }, /* -14 NMI Handler */ - { HardFault_Handler }, /* -13 Hard Fault Handler */ - { MemManage_Handler }, /* -12 MPU Fault Handler */ - { BusFault_Handler }, /* -11 Bus Fault Handler */ - { UsageFault_Handler }, /* -10 Usage Fault Handler */ - { SecureFault_Handler }, /* -9 Secure Fault Handler */ - { Default_Handler }, /* Reserved */ - { Default_Handler }, /* Reserved */ -#ifdef BOOTLOADER_ENABLE - { (VECTOR_TABLE_Type) & mainStageTable }, -#else - { Default_Handler }, /* Reserved */ -#endif - { SVC_Handler }, /* -5 SVCall Handler */ - { DebugMon_Handler }, /* -4 Debug Monitor Handler */ -#ifdef SL_APP_PROPERTIES - { (VECTOR_TABLE_Type) & sl_app_properties }, /* Application properties */ -#else - { sl_app_properties }, /* Application properties */ -#endif - { PendSV_Handler }, /* -2 PendSV Handler */ - { SysTick_Handler }, /* -1 SysTick Handler */ - - /* External interrupts */ - { CRYPTOACC_IRQHandler }, /* -16 = CRYPTOACC */ - { TRNG_IRQHandler }, /* -15 = TRNG */ - { PKE_IRQHandler }, /* -14 = PKE */ - { SMU_SECURE_IRQHandler }, /* -13 = SMU_SECURE */ - { SMU_S_PRIVILEGED_IRQHandler }, /* -12 = SMU_S_PRIVILEGED */ - { SMU_NS_PRIVILEGED_IRQHandler }, /* -11 = SMU_NS_PRIVILEGED */ - { EMU_IRQHandler }, /* -10 = EMU */ - { TIMER0_IRQHandler }, /* -9 = TIMER0 */ - { TIMER1_IRQHandler }, /* -8 = TIMER1 */ - { TIMER2_IRQHandler }, /* -7 = TIMER2 */ - { TIMER3_IRQHandler }, /* -6 = TIMER3 */ - { TIMER4_IRQHandler }, /* -5 = TIMER4 */ - { RTCC_IRQHandler }, /* -4 = RTCC */ - { USART0_RX_IRQHandler }, /* -3 = USART0_RX */ - { USART0_TX_IRQHandler }, /* -2 = USART0_TX */ - { USART1_RX_IRQHandler }, /* -1 = USART1_RX */ - { USART1_TX_IRQHandler }, /* 00 = USART1_TX */ - { ICACHE0_IRQHandler }, /* 01 = ICACHE0 */ - { BURTC_IRQHandler }, /* 02 = BURTC */ - { LETIMER0_IRQHandler }, /* 03 = LETIMER0 */ - { SYSCFG_IRQHandler }, /* 04 = SYSCFG */ - { LDMA_IRQHandler }, /* 05 = LDMA */ - { LFXO_IRQHandler }, /* 06 = LFXO */ - { LFRCO_IRQHandler }, /* 07 = LFRCO */ - { ULFRCO_IRQHandler }, /* 08 = ULFRCO */ - { GPIO_ODD_IRQHandler }, /* 09 = GPIO_ODD */ - { GPIO_EVEN_IRQHandler }, /* 10 = GPIO_EVEN */ - { I2C0_IRQHandler }, /* 11 = I2C0 */ - { I2C1_IRQHandler }, /* 12 = I2C1 */ - { EMUDG_IRQHandler }, /* 13 = EMUDG */ - { EMUSE_IRQHandler }, /* 14 = EMUSE */ - { AGC_IRQHandler }, /* 15 = AGC */ - { BUFC_IRQHandler }, /* 16 = BUFC */ - { FRC_PRI_IRQHandler }, /* 17 = FRC_PRI */ - { FRC_IRQHandler }, /* 18 = FRC */ - { MODEM_IRQHandler }, /* 19 = MODEM */ - { PROTIMER_IRQHandler }, /* 20 = PROTIMER */ - { RAC_RSM_IRQHandler }, /* 21 = RAC_RSM */ - { RAC_SEQ_IRQHandler }, /* 22 = RAC_SEQ */ - { RDMAILBOX_IRQHandler }, /* 23 = RDMAILBOX */ - { RFSENSE_IRQHandler }, /* 24 = RFSENSE */ - { PRORTC_IRQHandler }, /* 25 = PRORTC */ - { SYNTH_IRQHandler }, /* 26 = SYNTH */ - { WDOG0_IRQHandler }, /* 27 = WDOG0 */ - { HFXO0_IRQHandler }, /* 28 = HFXO0 */ - { HFRCO0_IRQHandler }, /* 29 = HFRCO0 */ - { CMU_IRQHandler }, /* 30 = CMU */ - { AES_IRQHandler }, /* 31 = AES */ - { IADC_IRQHandler }, /* 32 = IADC */ - { MSC_IRQHandler }, /* 33 = MSC */ - { DPLL0_IRQHandler }, /* 34 = DPLL0 */ - { PDM_IRQHandler }, /* 35 = PDM */ - { SW0_IRQHandler }, /* 36 = SW0 */ - { SW1_IRQHandler }, /* 37 = SW1 */ - { SW2_IRQHandler }, /* 38 = SW2 */ - { SW3_IRQHandler }, /* 39 = SW3 */ - { KERNEL0_IRQHandler }, /* 40 = KERNEL0 */ - { KERNEL1_IRQHandler }, /* 41 = KERNEL1 */ - { M33CTI0_IRQHandler }, /* 42 = M33CTI0 */ - { M33CTI1_IRQHandler }, /* 43 = M33CTI1 */ - { EMUEFP_IRQHandler }, /* 44 = EMUEFP */ - { DCDC_IRQHandler }, /* 45 = DCDC */ - { EUART0_RX_IRQHandler }, /* 46 = EUART0_RX */ - { EUART0_TX_IRQHandler }, /* 47 = EUART0_TX */ -}; - -#if defined (__GNUC__) -#pragma GCC diagnostic pop -#endif // __GNUC__ - -#if defined (__START) && defined (__GNUC__) -void Copy_Table() -{ - uint32_t *pSrc, *pDest; - extern uint32_t __etext; - extern uint32_t __data_start__; - extern uint32_t __data_end__; - pSrc = &__etext; - pDest = &__data_start__; - - for (; pDest < &__data_end__; ) { - *pDest++ = *pSrc++; - } -} - -void Zero_Table() -{ - uint32_t *pDest; - extern uint32_t __bss_start__; - extern uint32_t __bss_end__; - pDest = &__bss_start__; - - for (; pDest < &__bss_end__; ) { - *pDest++ = 0UL; - } -} -#endif // __START - -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) -void CopyRamFuncs() -{ - extern uint32_t __lma_ramfuncs_start__; - extern uint32_t __lma_ramfuncs_end__; - extern uint32_t __ramfuncs_start__; - uint32_t size = &__lma_ramfuncs_end__ - &__lma_ramfuncs_start__; - - FlashToRamCopy(&__lma_ramfuncs_start__, &__ramfuncs_start__, size); -} -#endif -#endif - -/*--------------------------------------------------------------------------- - * Reset Handler called on controller reset - *---------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ -#if defined (SL_TRUSTZONE_SECURE) - __set_MSPLIM((uint32_t) (&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *) (&__STACK_SEAL)); -#endif // __ARM_FEATURE_CMSE -#endif // SL_TRUSTZONE_SECURE - - #ifndef __NO_SYSTEM_INIT - SystemInit(); /* CMSIS System Initialization */ - #endif - -#ifdef BOOTLOADER_ENABLE - SystemInit2(); -#endif // BOOTLOADER_ENABLE -#if !defined(SL_LEGACY_LINKER) -#if defined (__GNUC__) - CopyRamFuncs(); -#endif -#endif -#if defined (__GNUC__) && defined (__START) - Copy_Table(); - Zero_Table(); - __START(); -#else - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -#endif // __GNUC__ -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif // __ARMCC_VERSION - -/*---------------------------------------------------------------------------- - * Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while (true) { - } -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif // __ARMCC_VERSION +/****************************************************************************** +* @file startup_efr32bg22.c +* @brief CMSIS-Core(M) Device Startup File for +* Device EFR32BG22 +* @version V2.1.0 +* @date 16. December 2020 +******************************************************************************* +* # License +* +* The licensor of this software is Silicon Laboratories Inc. Your use of this +* software is governed by the terms of Silicon Labs Master Software License +* Agreement (MSLA) available at +* www.silabs.com/about-us/legal/master-software-license-agreement. This +* software is Third Party Software licensed by Silicon Labs from a third party +* and is governed by the sections of the MSLA applicable to Third Party +* Software and the additional terms set forth below. +* +******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "em_device.h" + +#ifdef BOOTLOADER_ENABLE +#include "api/btl_interface.h" + +#endif // BOOTLOADER_ENABLE +#ifdef SL_APP_PROPERTIES +#include "api/application_properties.h" + +#endif // SL_APP_PROPERTIES + +#define TOTAL_INTERRUPTS (16 + EXT_IRQ_COUNT) + +#ifdef BOOTLOADER_ENABLE +extern MainBootloaderTable_t mainStageTable; +extern void SystemInit2(void); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +#ifdef SL_APP_PROPERTIES +extern ApplicationProperties_t sl_app_properties; + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void (*VECTOR_TABLE_Type)(void); +#endif + +/*--------------------------------------------------------------------------- + * External References + *---------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +#if defined (SL_TRUSTZONE_SECURE) +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + +extern __NO_RETURN void __PROGRAM_START(void); + +#if defined (__START) && defined (__GNUC__) +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +void Copy_Table(); +void Zero_Table(); +#endif // __START +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) +// Function to copy RAM functions from Flash to RAM at startup time +void CopyRamFuncs(); +#endif +#endif + +/*--------------------------------------------------------------------------- + * Internal References + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void); +void Default_Handler(void); + +#if defined (__GNUC__) +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x00000400 +#endif // __STACK_SIZE + +#ifndef __HEAP_SIZE +#define __HEAP_SIZE 0x00000C00 +#endif // __HEAP_SIZE +#endif // __GNUC__ + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M Processor Exceptions */ +void NMI_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler(void) __attribute__ ((weak, alias("Default_Handler"))); +#ifndef SL_APP_PROPERTIES +/* Provide a dummy value for the sl_app_properties symbol. */ +void sl_app_properties(void); /* Prototype to please MISRA checkers. */ +void sl_app_properties(void) __attribute__ ((weak, alias("Default_Handler"))); +#endif + +/* Part Specific Interrupts */ +void CRYPTOACC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TRNG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PKE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_SECURE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_S_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SMU_NS_PRIVILEGED_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void TIMER4_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RTCC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void USART1_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ICACHE0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BURTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LETIMER0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYSCFG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LDMA_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFXO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void LFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void ULFRCO_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_ODD_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void GPIO_EVEN_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUDG_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AGC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void BUFC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_PRI_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void FRC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MODEM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PROTIMER_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_RSM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RAC_SEQ_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RDMAILBOX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void RFSENSE_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PRORTC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SYNTH_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void WDOG0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFXO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void HFRCO0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void CMU_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void AES_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void IADC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void MSC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DPLL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void PDM_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW2_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void SW3_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void KERNEL1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI0_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void M33CTI1_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EMUEFP_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void DCDC_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUART0_RX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); +void EUART0_TX_IRQHandler(void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined (__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif // __GNUC__ + +#if defined (__ICCARM__) +#pragma data_alignment=512 +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#elif defined(__GNUC__) +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __attribute__((aligned(512))) +__VECTOR_TABLE_ATTRIBUTE = { +#else +extern const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS]; +const tVectorEntry __VECTOR_TABLE[TOTAL_INTERRUPTS] __VECTOR_TABLE_ATTRIBUTE = { +#endif + { .topOfStack = &__INITIAL_SP }, /* Initial Stack Pointer */ + { Reset_Handler }, /* Reset Handler */ + { NMI_Handler }, /* -14 NMI Handler */ + { HardFault_Handler }, /* -13 Hard Fault Handler */ + { MemManage_Handler }, /* -12 MPU Fault Handler */ + { BusFault_Handler }, /* -11 Bus Fault Handler */ + { UsageFault_Handler }, /* -10 Usage Fault Handler */ + { SecureFault_Handler }, /* -9 Secure Fault Handler */ + { Default_Handler }, /* Reserved */ + { Default_Handler }, /* Reserved */ +#ifdef BOOTLOADER_ENABLE + { (VECTOR_TABLE_Type) & mainStageTable }, +#else + { Default_Handler }, /* Reserved */ +#endif + { SVC_Handler }, /* -5 SVCall Handler */ + { DebugMon_Handler }, /* -4 Debug Monitor Handler */ +#ifdef SL_APP_PROPERTIES + { (VECTOR_TABLE_Type) & sl_app_properties }, /* Application properties */ +#else + { sl_app_properties }, /* Application properties */ +#endif + { PendSV_Handler }, /* -2 PendSV Handler */ + { SysTick_Handler }, /* -1 SysTick Handler */ + + /* External interrupts */ + { CRYPTOACC_IRQHandler }, /* -16 = CRYPTOACC */ + { TRNG_IRQHandler }, /* -15 = TRNG */ + { PKE_IRQHandler }, /* -14 = PKE */ + { SMU_SECURE_IRQHandler }, /* -13 = SMU_SECURE */ + { SMU_S_PRIVILEGED_IRQHandler }, /* -12 = SMU_S_PRIVILEGED */ + { SMU_NS_PRIVILEGED_IRQHandler }, /* -11 = SMU_NS_PRIVILEGED */ + { EMU_IRQHandler }, /* -10 = EMU */ + { TIMER0_IRQHandler }, /* -9 = TIMER0 */ + { TIMER1_IRQHandler }, /* -8 = TIMER1 */ + { TIMER2_IRQHandler }, /* -7 = TIMER2 */ + { TIMER3_IRQHandler }, /* -6 = TIMER3 */ + { TIMER4_IRQHandler }, /* -5 = TIMER4 */ + { RTCC_IRQHandler }, /* -4 = RTCC */ + { USART0_RX_IRQHandler }, /* -3 = USART0_RX */ + { USART0_TX_IRQHandler }, /* -2 = USART0_TX */ + { USART1_RX_IRQHandler }, /* -1 = USART1_RX */ + { USART1_TX_IRQHandler }, /* 00 = USART1_TX */ + { ICACHE0_IRQHandler }, /* 01 = ICACHE0 */ + { BURTC_IRQHandler }, /* 02 = BURTC */ + { LETIMER0_IRQHandler }, /* 03 = LETIMER0 */ + { SYSCFG_IRQHandler }, /* 04 = SYSCFG */ + { LDMA_IRQHandler }, /* 05 = LDMA */ + { LFXO_IRQHandler }, /* 06 = LFXO */ + { LFRCO_IRQHandler }, /* 07 = LFRCO */ + { ULFRCO_IRQHandler }, /* 08 = ULFRCO */ + { GPIO_ODD_IRQHandler }, /* 09 = GPIO_ODD */ + { GPIO_EVEN_IRQHandler }, /* 10 = GPIO_EVEN */ + { I2C0_IRQHandler }, /* 11 = I2C0 */ + { I2C1_IRQHandler }, /* 12 = I2C1 */ + { EMUDG_IRQHandler }, /* 13 = EMUDG */ + { EMUSE_IRQHandler }, /* 14 = EMUSE */ + { AGC_IRQHandler }, /* 15 = AGC */ + { BUFC_IRQHandler }, /* 16 = BUFC */ + { FRC_PRI_IRQHandler }, /* 17 = FRC_PRI */ + { FRC_IRQHandler }, /* 18 = FRC */ + { MODEM_IRQHandler }, /* 19 = MODEM */ + { PROTIMER_IRQHandler }, /* 20 = PROTIMER */ + { RAC_RSM_IRQHandler }, /* 21 = RAC_RSM */ + { RAC_SEQ_IRQHandler }, /* 22 = RAC_SEQ */ + { RDMAILBOX_IRQHandler }, /* 23 = RDMAILBOX */ + { RFSENSE_IRQHandler }, /* 24 = RFSENSE */ + { PRORTC_IRQHandler }, /* 25 = PRORTC */ + { SYNTH_IRQHandler }, /* 26 = SYNTH */ + { WDOG0_IRQHandler }, /* 27 = WDOG0 */ + { HFXO0_IRQHandler }, /* 28 = HFXO0 */ + { HFRCO0_IRQHandler }, /* 29 = HFRCO0 */ + { CMU_IRQHandler }, /* 30 = CMU */ + { AES_IRQHandler }, /* 31 = AES */ + { IADC_IRQHandler }, /* 32 = IADC */ + { MSC_IRQHandler }, /* 33 = MSC */ + { DPLL0_IRQHandler }, /* 34 = DPLL0 */ + { PDM_IRQHandler }, /* 35 = PDM */ + { SW0_IRQHandler }, /* 36 = SW0 */ + { SW1_IRQHandler }, /* 37 = SW1 */ + { SW2_IRQHandler }, /* 38 = SW2 */ + { SW3_IRQHandler }, /* 39 = SW3 */ + { KERNEL0_IRQHandler }, /* 40 = KERNEL0 */ + { KERNEL1_IRQHandler }, /* 41 = KERNEL1 */ + { M33CTI0_IRQHandler }, /* 42 = M33CTI0 */ + { M33CTI1_IRQHandler }, /* 43 = M33CTI1 */ + { EMUEFP_IRQHandler }, /* 44 = EMUEFP */ + { DCDC_IRQHandler }, /* 45 = DCDC */ + { EUART0_RX_IRQHandler }, /* 46 = EUART0_RX */ + { EUART0_TX_IRQHandler }, /* 47 = EUART0_TX */ +}; + +#if defined (__GNUC__) +#pragma GCC diagnostic pop +#endif // __GNUC__ + +#if defined (__START) && defined (__GNUC__) +void Copy_Table() +{ + uint32_t *pSrc, *pDest; + extern uint32_t __etext; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + pSrc = &__etext; + pDest = &__data_start__; + + for (; pDest < &__data_end__; ) { + *pDest++ = *pSrc++; + } +} + +void Zero_Table() +{ + uint32_t *pDest; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + pDest = &__bss_start__; + + for (; pDest < &__bss_end__; ) { + *pDest++ = 0UL; + } +} +#endif // __START + +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) +void CopyRamFuncs() +{ + extern uint32_t __lma_ramfuncs_start__; + extern uint32_t __lma_ramfuncs_end__; + extern uint32_t __ramfuncs_start__; + uint32_t size = &__lma_ramfuncs_end__ - &__lma_ramfuncs_start__; + + FlashToRamCopy(&__lma_ramfuncs_start__, &__ramfuncs_start__, size); +} +#endif +#endif + +/*--------------------------------------------------------------------------- + * Reset Handler called on controller reset + *---------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ +#if defined (SL_TRUSTZONE_SECURE) + __set_MSPLIM((uint32_t) (&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *) (&__STACK_SEAL)); +#endif // __ARM_FEATURE_CMSE +#endif // SL_TRUSTZONE_SECURE + + #ifndef __NO_SYSTEM_INIT + SystemInit(); /* CMSIS System Initialization */ + #endif + +#ifdef BOOTLOADER_ENABLE + SystemInit2(); +#endif // BOOTLOADER_ENABLE +#if !defined(SL_LEGACY_LINKER) +#if defined (__GNUC__) + CopyRamFuncs(); +#endif +#endif +#if defined (__GNUC__) && defined (__START) + Copy_Table(); + Zero_Table(); + __START(); +#else + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +#endif // __GNUC__ +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif // __ARMCC_VERSION + +/*---------------------------------------------------------------------------- + * Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while (true) { + } +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif // __ARMCC_VERSION diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c index 318271f..ce41aff 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c @@ -1,614 +1,614 @@ -/***************************************************************************//** - * @file - * @brief CMSIS Cortex-M33 system support for EFR32BG22 devices. - ****************************************************************************** - * # License - * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com - ****************************************************************************** - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - *****************************************************************************/ - -#include -#include "em_device.h" - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -// System oscillator frequencies. These frequencies are normally constant -// for a target, but they are made configurable in order to allow run-time -// handling of different boards. The crystal oscillator clocks can be set -// compile time to a non-default value by defining respective nFXO_FREQ -// values according to board design. By defining the nFXO_FREQ to 0, -// one indicates that the oscillator is not present, in order to save some -// SW footprint. - -#if !defined(FSRCO_FREQ) -// FSRCO frequency -#define FSRCO_FREQ (20000000UL) -#endif - -#if !defined(HFXO_FREQ) -// HFXO frequency -#define HFXO_FREQ (38400000UL) -#endif - -#if !defined(HFRCODPLL_STARTUP_FREQ) -// HFRCODPLL startup frequency -#define HFRCODPLL_STARTUP_FREQ (19000000UL) -#endif - -#if !defined(HFRCODPLL_MAX_FREQ) -// Maximum HFRCODPLL frequency -#define HFRCODPLL_MAX_FREQ (80000000UL) -#endif - -// CLKIN0 input -#if !defined(CLKIN0_FREQ) -#define CLKIN0_FREQ (0UL) -#endif - -#if !defined(LFRCO_MAX_FREQ) -// LFRCO frequency, tuned to below frequency during manufacturing. -#define LFRCO_FREQ (32768UL) -#endif - -#if !defined(ULFRCO_FREQ) -// ULFRCO frequency -#define ULFRCO_FREQ (1000UL) -#endif - -#if !defined(LFXO_FREQ) -// LFXO frequency -#define LFXO_FREQ (LFRCO_FREQ) -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) -// NOTE: Gecko bootloaders can't have static variable allocation. -// System HFXO clock frequency -static uint32_t SystemHFXOClock = HFXO_FREQ; -#endif - -#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) -// System LFXO clock frequency -static uint32_t SystemLFXOClock = LFXO_FREQ; -#endif - -#if !defined(SYSTEM_NO_STATIC_MEMORY) -// System HFRCODPLL clock frequency -static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; -#endif - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -#if !defined(SYSTEM_NO_STATIC_MEMORY) - -/** - * @brief - * System System Clock Frequency (Core Clock). - * - * @details - * Required CMSIS global variable that must be kept up-to-date. - */ -uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; - -#endif - -/*--------------------------------------------------------------------------- - * Exception / Interrupt Vector table - *---------------------------------------------------------------------------*/ -extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/**************************************************************************//** - * @brief - * Initialize the system. - * - * @details - * Do required generic HW system init. - * - * @note - * This function is invoked during system init, before the main() routine - * and any data has been initialized. For this reason, it cannot do any - * initialization of variables etc. - *****************************************************************************/ -void SystemInit(void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); -#endif - -#if defined(UNALIGNED_SUPPORT_DISABLE) - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if (__FPU_PRESENT == 1) - SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ - | (3U << 11U * 2U)); /* set CP11 Full Access */ -#endif - -/* Secure app takes care of moving between the security states. - * SL_TRUSTZONE_SECURE MACRO is for secure access. - * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. - * When both the MACROS are not defined, during start-up below code makes sure - * that all the peripherals are accessed from non-secure address except SMU, - * as SMU is used to configure the trustzone state of the system. */ -#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ - && defined(__TZ_PRESENT) - CMU->CLKEN1_SET = CMU_CLKEN1_SMU; - - // config SMU to Secure and other peripherals to Non-Secure. - SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; -#if defined (SEMAILBOX_PRESENT) - SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); -#else - SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); -#endif - - // SAU treats all accesses as non-secure -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SAU->CTRL = SAU_CTRL_ALLNS_Msk; - __DSB(); - __ISB(); -#else - #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." -#endif // __ARM_FEATURE_CMSE - -// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. - NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); - SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; - NVIC_EnableIRQ(SMU_SECURE_IRQn); - SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; -#endif //SL_TRUSTZONE_SECURE -} - -#if !defined(SL_LEGACY_LINKER) -/**************************************************************************//** - * @brief - * Copy data. - * - * @details - * Used to copy data from Flash to Ram at startup and runtime. - * - * @param[in] from - * Pointer to the source address in Flash. - * - * @param[in] to - * Pointer to the destination address in Ram. - * - * @param[in] size - * Size of data to copy. - *****************************************************************************/ -void FlashToRamCopy(uint32_t *from, - uint32_t *to, - uint32_t size) -{ - if (size != 0) { - while (size--) { - *to++ = *from++; - } - } -} -#endif - -/**************************************************************************//** - * @brief - * Get current HFRCODPLL frequency. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * HFRCODPLL frequency in Hz. - *****************************************************************************/ -uint32_t SystemHFRCODPLLClockGet(void) -{ -#if !defined(SYSTEM_NO_STATIC_MEMORY) - return SystemHFRCODPLLClock; -#else - uint32_t ret = 0UL; - - // Get oscillator frequency band - switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) - >> _HFRCO_CAL_FREQRANGE_SHIFT) { - case 0: - switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { - case HFRCO_CAL_CLKDIV_DIV1: - ret = 4000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV2: - ret = 2000000UL; - break; - - case HFRCO_CAL_CLKDIV_DIV4: - ret = 1000000UL; - break; - - default: - ret = 0UL; - break; - } - break; - - case 3: - ret = 7000000UL; - break; - - case 6: - ret = 13000000UL; - break; - - case 7: - ret = 16000000UL; - break; - - case 8: - ret = 19000000UL; - break; - - case 10: - ret = 26000000UL; - break; - - case 11: - ret = 32000000UL; - break; - - case 12: - ret = 38000000UL; - break; - - case 13: - ret = 48000000UL; - break; - - case 14: - ret = 56000000UL; - break; - - case 15: - ret = 64000000UL; - break; - - case 16: - ret = 80000000UL; - break; - - default: - break; - } - return ret; -#endif -} - -/**************************************************************************//** - * @brief - * Set HFRCODPLL frequency value. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * HFRCODPLL frequency in Hz. - *****************************************************************************/ -void SystemHFRCODPLLClockSet(uint32_t freq) -{ -#if !defined(SYSTEM_NO_STATIC_MEMORY) - SystemHFRCODPLLClock = freq; -#else - (void) freq; // Unused parameter -#endif -} - -/***************************************************************************//** - * @brief - * Get the current system clock frequency (SYSCLK). - * - * @details - * Calculate and get the current core clock frequency based on the current - * hardware configuration. - * - * @note - * This is an EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * Current system clock (SYSCLK) frequency in Hz. - ******************************************************************************/ -uint32_t SystemSYSCLKGet(void) -{ - uint32_t ret = 0U; - - // Find clock source - switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { - case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: - ret = SystemHFRCODPLLClockGet(); - break; - -#if (HFXO_FREQ > 0U) - case _CMU_SYSCLKCTRL_CLKSEL_HFXO: -#if defined(SYSTEM_NO_STATIC_MEMORY) - ret = HFXO_FREQ; -#else - ret = SystemHFXOClock; -#endif - break; -#endif - -#if (CLKIN0_FREQ > 0U) - case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: - ret = CLKIN0_FREQ; - break; -#endif - - case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: - ret = FSRCO_FREQ; - break; - - default: - // Unknown clock source. - while (1) { - } - } - return ret; -} - -/***************************************************************************//** - * @brief - * Get the current system core clock frequency (HCLK). - * - * @details - * Calculate and get the current core clock frequency based on the current - * configuration. Assuming that the SystemCoreClock global variable is - * maintained, the core clock frequency is stored in that variable as well. - * This function will however calculate the core clock based on actual HW - * configuration. It will also update the SystemCoreClock global variable. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * The current core clock (HCLK) frequency in Hz. - ******************************************************************************/ -uint32_t SystemHCLKGet(void) -{ - uint32_t presc, ret; - - ret = SystemSYSCLKGet(); - - presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; - - ret /= presc + 1U; - -#if !defined(SYSTEM_NO_STATIC_MEMORY) - // Keep CMSIS system clock variable up-to-date - SystemCoreClock = ret; -#endif - - return ret; -} - -/***************************************************************************//** - * @brief - * Get the maximum core clock frequency. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * The maximum core clock frequency in Hz. - ******************************************************************************/ -uint32_t SystemMaxCoreClockGet(void) -{ - return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ - ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); -} - -/**************************************************************************//** - * @brief - * Get high frequency crystal oscillator clock frequency for target system. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. - *****************************************************************************/ -uint32_t SystemHFXOClockGet(void) -{ - // The external crystal oscillator is not present if HFXO_FREQ==0 -#if (HFXO_FREQ > 0U) -#if defined(SYSTEM_NO_STATIC_MEMORY) - return HFXO_FREQ; -#else - return SystemHFXOClock; -#endif -#else - return 0U; -#endif -} - -/**************************************************************************//** - * @brief - * Set high frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * HFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemHFXOClockSet(uint32_t freq) -{ - // External crystal oscillator present? -#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) - SystemHFXOClock = freq; - - // Update core clock frequency if HFXO is used to clock core - if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) - == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { - // This function will update the global variable - SystemHCLKGet(); - } -#else - (void) freq; // Unused parameter -#endif -} - -/**************************************************************************//** - * @brief - * Get current CLKIN0 frequency. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * CLKIN0 frequency in Hz. - *****************************************************************************/ -uint32_t SystemCLKIN0Get(void) -{ - return CLKIN0_FREQ; -} - -/**************************************************************************//** - * @brief - * Get FSRCO frequency. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * FSRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemFSRCOClockGet(void) -{ - return FSRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get low frequency RC oscillator clock frequency for target system. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * LFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFRCOClockGet(void) -{ - return LFRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get ultra low frequency RC oscillator clock frequency for target system. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * ULFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemULFRCOClockGet(void) -{ - // The ULFRCO frequency is not tuned, and can be very inaccurate - return ULFRCO_FREQ; -} - -/**************************************************************************//** - * @brief - * Get low frequency crystal oscillator clock frequency for target system. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @return - * LFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFXOClockGet(void) -{ - // External crystal present? -#if (LFXO_FREQ > 0U) -#if defined(SYSTEM_NO_STATIC_MEMORY) - return LFXO_FREQ; -#else - return SystemLFXOClock; -#endif -#else - return 0U; -#endif -} - -/**************************************************************************//** - * @brief - * Set low frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is a EFR32BG22 specific function, not part of the - * CMSIS definition. - * - * @param[in] freq - * LFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemLFXOClockSet(uint32_t freq) -{ - // External crystal oscillator present? -#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) - SystemLFXOClock = freq; -#else - (void) freq; // Unused parameter -#endif -} +/***************************************************************************//** + * @file + * @brief CMSIS Cortex-M33 system support for EFR32BG22 devices. + ****************************************************************************** + * # License + * Copyright 2023 Silicon Laboratories, Inc. www.silabs.com + ****************************************************************************** + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + *****************************************************************************/ + +#include +#include "em_device.h" + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +// System oscillator frequencies. These frequencies are normally constant +// for a target, but they are made configurable in order to allow run-time +// handling of different boards. The crystal oscillator clocks can be set +// compile time to a non-default value by defining respective nFXO_FREQ +// values according to board design. By defining the nFXO_FREQ to 0, +// one indicates that the oscillator is not present, in order to save some +// SW footprint. + +#if !defined(FSRCO_FREQ) +// FSRCO frequency +#define FSRCO_FREQ (20000000UL) +#endif + +#if !defined(HFXO_FREQ) +// HFXO frequency +#define HFXO_FREQ (38400000UL) +#endif + +#if !defined(HFRCODPLL_STARTUP_FREQ) +// HFRCODPLL startup frequency +#define HFRCODPLL_STARTUP_FREQ (19000000UL) +#endif + +#if !defined(HFRCODPLL_MAX_FREQ) +// Maximum HFRCODPLL frequency +#define HFRCODPLL_MAX_FREQ (80000000UL) +#endif + +// CLKIN0 input +#if !defined(CLKIN0_FREQ) +#define CLKIN0_FREQ (0UL) +#endif + +#if !defined(LFRCO_MAX_FREQ) +// LFRCO frequency, tuned to below frequency during manufacturing. +#define LFRCO_FREQ (32768UL) +#endif + +#if !defined(ULFRCO_FREQ) +// ULFRCO frequency +#define ULFRCO_FREQ (1000UL) +#endif + +#if !defined(LFXO_FREQ) +// LFXO frequency +#define LFXO_FREQ (LFRCO_FREQ) +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// NOTE: Gecko bootloaders can't have static variable allocation. +// System HFXO clock frequency +static uint32_t SystemHFXOClock = HFXO_FREQ; +#endif + +#if (LFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) +// System LFXO clock frequency +static uint32_t SystemLFXOClock = LFXO_FREQ; +#endif + +#if !defined(SYSTEM_NO_STATIC_MEMORY) +// System HFRCODPLL clock frequency +static uint32_t SystemHFRCODPLLClock = HFRCODPLL_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** GLOBAL VARIABLES ******************************* + ******************************************************************************/ + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + +/** + * @brief + * System System Clock Frequency (Core Clock). + * + * @details + * Required CMSIS global variable that must be kept up-to-date. + */ +uint32_t SystemCoreClock = HFRCODPLL_STARTUP_FREQ; + +#endif + +/*--------------------------------------------------------------------------- + * Exception / Interrupt Vector table + *---------------------------------------------------------------------------*/ +extern const tVectorEntry __VECTOR_TABLE[16 + EXT_IRQ_COUNT]; + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Initialize the system. + * + * @details + * Do required generic HW system init. + * + * @note + * This function is invoked during system init, before the main() routine + * and any data has been initialized. For this reason, it cannot do any + * initialization of variables etc. + *****************************************************************************/ +void SystemInit(void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) (&__VECTOR_TABLE[0]); +#endif + +#if defined(UNALIGNED_SUPPORT_DISABLE) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if (__FPU_PRESENT == 1) + SCB->CPACR |= ((3U << 10U * 2U) /* set CP10 Full Access */ + | (3U << 11U * 2U)); /* set CP11 Full Access */ +#endif + +/* Secure app takes care of moving between the security states. + * SL_TRUSTZONE_SECURE MACRO is for secure access. + * SL_TRUSTZONE_NONSECURE MACRO is for non-secure access. + * When both the MACROS are not defined, during start-up below code makes sure + * that all the peripherals are accessed from non-secure address except SMU, + * as SMU is used to configure the trustzone state of the system. */ +#if !defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_NONSECURE) \ + && defined(__TZ_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; + + // config SMU to Secure and other peripherals to Non-Secure. + SMU->PPUSATD0_CLR = _SMU_PPUSATD0_MASK; +#if defined (SEMAILBOX_PRESENT) + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & (~SMU_PPUSATD1_SMU & ~SMU_PPUSATD1_SEMAILBOX)); +#else + SMU->PPUSATD1_CLR = (_SMU_PPUSATD1_MASK & ~SMU_PPUSATD1_SMU); +#endif + + // SAU treats all accesses as non-secure +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SAU->CTRL = SAU_CTRL_ALLNS_Msk; + __DSB(); + __ISB(); +#else + #error "The startup code requires access to the CMSE toolchain extension to set proper SAU settings." +#endif // __ARM_FEATURE_CMSE + +// Clear and Enable the SMU PPUSEC and BMPUSEC interrupt. + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IF_PPUSEC | SMU_IF_BMPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN = SMU_IEN_PPUSEC | SMU_IEN_BMPUSEC; +#endif //SL_TRUSTZONE_SECURE +} + +#if !defined(SL_LEGACY_LINKER) +/**************************************************************************//** + * @brief + * Copy data. + * + * @details + * Used to copy data from Flash to Ram at startup and runtime. + * + * @param[in] from + * Pointer to the source address in Flash. + * + * @param[in] to + * Pointer to the destination address in Ram. + * + * @param[in] size + * Size of data to copy. + *****************************************************************************/ +void FlashToRamCopy(uint32_t *from, + uint32_t *to, + uint32_t size) +{ + if (size != 0) { + while (size--) { + *to++ = *from++; + } + } +} +#endif + +/**************************************************************************//** + * @brief + * Get current HFRCODPLL frequency. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +uint32_t SystemHFRCODPLLClockGet(void) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + return SystemHFRCODPLLClock; +#else + uint32_t ret = 0UL; + + // Get oscillator frequency band + switch ((HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK) + >> _HFRCO_CAL_FREQRANGE_SHIFT) { + case 0: + switch (HFRCO0->CAL & _HFRCO_CAL_CLKDIV_MASK) { + case HFRCO_CAL_CLKDIV_DIV1: + ret = 4000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV2: + ret = 2000000UL; + break; + + case HFRCO_CAL_CLKDIV_DIV4: + ret = 1000000UL; + break; + + default: + ret = 0UL; + break; + } + break; + + case 3: + ret = 7000000UL; + break; + + case 6: + ret = 13000000UL; + break; + + case 7: + ret = 16000000UL; + break; + + case 8: + ret = 19000000UL; + break; + + case 10: + ret = 26000000UL; + break; + + case 11: + ret = 32000000UL; + break; + + case 12: + ret = 38000000UL; + break; + + case 13: + ret = 48000000UL; + break; + + case 14: + ret = 56000000UL; + break; + + case 15: + ret = 64000000UL; + break; + + case 16: + ret = 80000000UL; + break; + + default: + break; + } + return ret; +#endif +} + +/**************************************************************************//** + * @brief + * Set HFRCODPLL frequency value. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFRCODPLL frequency in Hz. + *****************************************************************************/ +void SystemHFRCODPLLClockSet(uint32_t freq) +{ +#if !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFRCODPLLClock = freq; +#else + (void) freq; // Unused parameter +#endif +} + +/***************************************************************************//** + * @brief + * Get the current system clock frequency (SYSCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * hardware configuration. + * + * @note + * This is an EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * Current system clock (SYSCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemSYSCLKGet(void) +{ + uint32_t ret = 0U; + + // Find clock source + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = SystemHFRCODPLLClockGet(); + break; + +#if (HFXO_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_HFXO: +#if defined(SYSTEM_NO_STATIC_MEMORY) + ret = HFXO_FREQ; +#else + ret = SystemHFXOClock; +#endif + break; +#endif + +#if (CLKIN0_FREQ > 0U) + case _CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = CLKIN0_FREQ; + break; +#endif + + case _CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = FSRCO_FREQ; + break; + + default: + // Unknown clock source. + while (1) { + } + } + return ret; +} + +/***************************************************************************//** + * @brief + * Get the current system core clock frequency (HCLK). + * + * @details + * Calculate and get the current core clock frequency based on the current + * configuration. Assuming that the SystemCoreClock global variable is + * maintained, the core clock frequency is stored in that variable as well. + * This function will however calculate the core clock based on actual HW + * configuration. It will also update the SystemCoreClock global variable. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * The current core clock (HCLK) frequency in Hz. + ******************************************************************************/ +uint32_t SystemHCLKGet(void) +{ + uint32_t presc, ret; + + ret = SystemSYSCLKGet(); + + presc = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; + + ret /= presc + 1U; + +#if !defined(SYSTEM_NO_STATIC_MEMORY) + // Keep CMSIS system clock variable up-to-date + SystemCoreClock = ret; +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Get the maximum core clock frequency. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * The maximum core clock frequency in Hz. + ******************************************************************************/ +uint32_t SystemMaxCoreClockGet(void) +{ + return(HFRCODPLL_MAX_FREQ > HFXO_FREQ \ + ? HFRCODPLL_MAX_FREQ : HFXO_FREQ); +} + +/**************************************************************************//** + * @brief + * Get high frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * HFXO frequency in Hz. 0 if the external crystal oscillator is not present. + *****************************************************************************/ +uint32_t SystemHFXOClockGet(void) +{ + // The external crystal oscillator is not present if HFXO_FREQ==0 +#if (HFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return HFXO_FREQ; +#else + return SystemHFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set high frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * HFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemHFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (HFXO_FREQ > 0) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemHFXOClock = freq; + + // Update core clock frequency if HFXO is used to clock core + if ((CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) + == _CMU_SYSCLKCTRL_CLKSEL_HFXO) { + // This function will update the global variable + SystemHCLKGet(); + } +#else + (void) freq; // Unused parameter +#endif +} + +/**************************************************************************//** + * @brief + * Get current CLKIN0 frequency. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * CLKIN0 frequency in Hz. + *****************************************************************************/ +uint32_t SystemCLKIN0Get(void) +{ + return CLKIN0_FREQ; +} + +/**************************************************************************//** + * @brief + * Get FSRCO frequency. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * FSRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemFSRCOClockGet(void) +{ + return FSRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * LFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFRCOClockGet(void) +{ + return LFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get ultra low frequency RC oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * ULFRCO frequency in Hz. + *****************************************************************************/ +uint32_t SystemULFRCOClockGet(void) +{ + // The ULFRCO frequency is not tuned, and can be very inaccurate + return ULFRCO_FREQ; +} + +/**************************************************************************//** + * @brief + * Get low frequency crystal oscillator clock frequency for target system. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @return + * LFXO frequency in Hz. + *****************************************************************************/ +uint32_t SystemLFXOClockGet(void) +{ + // External crystal present? +#if (LFXO_FREQ > 0U) +#if defined(SYSTEM_NO_STATIC_MEMORY) + return LFXO_FREQ; +#else + return SystemLFXOClock; +#endif +#else + return 0U; +#endif +} + +/**************************************************************************//** + * @brief + * Set low frequency crystal oscillator clock frequency for target system. + * + * @note + * This function is mainly provided for being able to handle target systems + * with different HF crystal oscillator frequencies run-time. If used, it + * should probably only be used once during system startup. + * + * @note + * This is a EFR32BG22 specific function, not part of the + * CMSIS definition. + * + * @param[in] freq + * LFXO frequency in Hz used for target. + *****************************************************************************/ +void SystemLFXOClockSet(uint32_t freq) +{ + // External crystal oscillator present? +#if (LFXO_FREQ > 0U) && !defined(SYSTEM_NO_STATIC_MEMORY) + SystemLFXOClock = freq; +#else + (void) freq; // Unused parameter +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/application_properties.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/application_properties.h index 3e53456..21dc5a1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/application_properties.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/application_properties.h @@ -1,168 +1,168 @@ -/***************************************************************************//** - * @file - * @brief Representation of Application Properties - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef APPLICATION_PROPERTIES_H -#define APPLICATION_PROPERTIES_H - -#include - -/***************************************************************************//** - * @addtogroup Interface - * @{ - * @addtogroup ApplicationProperties Application Properties - * @brief Properties of the application that can be accessed by the bootloader - * @details - * Applications must contain an @ref ApplicationProperties_t struct declaring - * the application version and capabilities, and so on. The metadata contained - * in this struct will be extracted from the application by the Simplicity - * Commander tool and placed in the GBL upgrade file. If this struct is not - * in the application image, it will be added to the GBL file by the - * Simplicity Commander. - * - * The struct is also used to declare whether the application image is signed - * and what type of signature is used. If no @ref ApplicationProperties_t - * struct is present, the bootloader will assume that the application image - * is signed using @ref APPLICATION_SIGNATURE_ECDSA_P256. - * - * To ensure that the bootloader can easily locate the ApplicationProperties_t - * struct, if not already done by the linker, Simplicity Commander will modify - * word 13 of the application to insert a pointer to the - * ApplicationProperties_t struct. - * @{ - ******************************************************************************/ - -/// Magic value declaring the existence of an ApplicationProperties_t struct -#define APPLICATION_PROPERTIES_MAGIC { \ - 0x13, 0xb7, 0x79, 0xfa, \ - 0xc9, 0x25, 0xdd, 0xb7, \ - 0xad, 0xf3, 0xcf, 0xe0, \ - 0xf1, 0xb6, 0x14, 0xb8 \ -} - -/// Byte-reversed version of ::APPLICATION_PROPERTIES_MAGIC -#define APPLICATION_PROPERTIES_REVERSED { \ - 0xb8, 0x14, 0xb6, 0xf1, \ - 0xe0, 0xcf, 0xf3, 0xad, \ - 0xb7, 0xdd, 0x25, 0xc9, \ - 0xfa, 0x79, 0xb7, 0x13 \ -} - -/// Major version number of the AppliationProperties_t struct -#define APPLICATION_PROPERTIES_VERSION_MAJOR (1UL) -/// Minor version number of the AppliationProperties_t struct -#define APPLICATION_PROPERTIES_VERSION_MINOR (2UL) -/// Version number of the ApplicationCertificate_t struct -#define APPLICATION_CERTIFICATE_VERSION (1UL) -/// The application is not signed -#define APPLICATION_SIGNATURE_NONE (0UL) -/// @brief The SHA-256 digest of the application is signed using ECDSA with the -/// NIST P-256 curve. -#define APPLICATION_SIGNATURE_ECDSA_P256 (1UL << 0UL) -/// @brief The application is not signed, but has a CRC-32 checksum -#define APPLICATION_SIGNATURE_CRC32 (1UL << 1UL) - -/// The application contains a Zigbee wireless stack -#define APPLICATION_TYPE_ZIGBEE (1UL << 0UL) -/// The application contains a Thread wireless stack -#define APPLICATION_TYPE_THREAD (1UL << 1UL) -/// The application contains a Flex wireless stack -#define APPLICATION_TYPE_FLEX (1UL << 2UL) -/// The application contains a Bluetooth wireless stack -#define APPLICATION_TYPE_BLUETOOTH (1UL << 3UL) -/// The application is an MCU application -#define APPLICATION_TYPE_MCU (1UL << 4UL) -/// The application contains a Bluetooth application -#define APPLICATION_TYPE_BLUETOOTH_APP (1UL << 5UL) -/// The application contains a bootloader -#define APPLICATION_TYPE_BOOTLOADER (1UL << 6UL) -/// The application contains a Zwave wireless stack -#define APPLICATION_TYPE_ZWAVE (1UL << 7UL) - -/// Application Data -typedef struct ApplicationData { - /// @brief Bitfield representing type of application, e.g., - /// @ref APPLICATION_TYPE_ZIGBEE - uint32_t type; - /// Version number for this application - uint32_t version; - /// Capabilities of this application - uint32_t capabilities; - /// Unique ID (UUID or GUID) for the product this application is built for - uint8_t productId[16]; -} ApplicationData_t; - -/// Application Certificate -typedef struct ApplicationCertificate { - /// Version of the certificate structure - uint8_t structVersion; - /// Reserved flags - uint8_t flags[3]; - /// Public key - uint8_t key[64]; - /// The version number of this certificate - uint32_t version; - /// Signature of the certificate - uint8_t signature[64]; -} ApplicationCertificate_t; - -/// Application Properties struct -typedef struct { - /// @brief Magic value indicating this is an ApplicationProperties_t struct. - /// Must equal @ref APPLICATION_PROPERTIES_MAGIC - uint8_t magic[16]; - /// Version number of this struct - uint32_t structVersion; - /// Type of signature this application is signed with - uint32_t signatureType; - /// Location of the signature. Typically points to the end of the application - uint32_t signatureLocation; - /// Information about the application - ApplicationData_t app; - /// Pointer to information about the certificate - ApplicationCertificate_t *cert; - /// Pointer to Long Token Data Section - uint8_t *longTokenSectionAddress; - /// Parser Decryption Key - const uint8_t decryptKey[16]; -} ApplicationProperties_t; - -/** @} (end addtogroup ApplicationProperties) */ -/** @} (end addtogroup Interface) */ - -/// Application Properties major version shift value -#define APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT (0U) -/// Application Properties minor version shift value -#define APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT (8U) - -/// Application Properties major version mask -#define APPLICATION_PROPERTIES_VERSION_MAJOR_MASK (0x000000FFU) -/// Application Properties minor version mask -#define APPLICATION_PROPERTIES_VERSION_MINOR_MASK (0xFFFFFF00U) - -/// Version number of the AppliationProperties_t struct -#define APPLICATION_PROPERTIES_VERSION ((APPLICATION_PROPERTIES_VERSION_MINOR \ - << APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) \ - | (APPLICATION_PROPERTIES_VERSION_MAJOR \ - << APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT)) - -#if (APPLICATION_PROPERTIES_VERSION_MAJOR \ - > (APPLICATION_PROPERTIES_VERSION_MAJOR_MASK >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT)) -|| (APPLICATION_PROPERTIES_VERSION_MINOR \ - > (APPLICATION_PROPERTIES_VERSION_MINOR_MASK >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT)) -#error "Invalid application properties version" -#endif - -#endif // APPLICATION_PROPERTIES_H +/***************************************************************************//** + * @file + * @brief Representation of Application Properties + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef APPLICATION_PROPERTIES_H +#define APPLICATION_PROPERTIES_H + +#include + +/***************************************************************************//** + * @addtogroup Interface + * @{ + * @addtogroup ApplicationProperties Application Properties + * @brief Properties of the application that can be accessed by the bootloader + * @details + * Applications must contain an @ref ApplicationProperties_t struct declaring + * the application version and capabilities, and so on. The metadata contained + * in this struct will be extracted from the application by the Simplicity + * Commander tool and placed in the GBL upgrade file. If this struct is not + * in the application image, it will be added to the GBL file by the + * Simplicity Commander. + * + * The struct is also used to declare whether the application image is signed + * and what type of signature is used. If no @ref ApplicationProperties_t + * struct is present, the bootloader will assume that the application image + * is signed using @ref APPLICATION_SIGNATURE_ECDSA_P256. + * + * To ensure that the bootloader can easily locate the ApplicationProperties_t + * struct, if not already done by the linker, Simplicity Commander will modify + * word 13 of the application to insert a pointer to the + * ApplicationProperties_t struct. + * @{ + ******************************************************************************/ + +/// Magic value declaring the existence of an ApplicationProperties_t struct +#define APPLICATION_PROPERTIES_MAGIC { \ + 0x13, 0xb7, 0x79, 0xfa, \ + 0xc9, 0x25, 0xdd, 0xb7, \ + 0xad, 0xf3, 0xcf, 0xe0, \ + 0xf1, 0xb6, 0x14, 0xb8 \ +} + +/// Byte-reversed version of ::APPLICATION_PROPERTIES_MAGIC +#define APPLICATION_PROPERTIES_REVERSED { \ + 0xb8, 0x14, 0xb6, 0xf1, \ + 0xe0, 0xcf, 0xf3, 0xad, \ + 0xb7, 0xdd, 0x25, 0xc9, \ + 0xfa, 0x79, 0xb7, 0x13 \ +} + +/// Major version number of the AppliationProperties_t struct +#define APPLICATION_PROPERTIES_VERSION_MAJOR (1UL) +/// Minor version number of the AppliationProperties_t struct +#define APPLICATION_PROPERTIES_VERSION_MINOR (2UL) +/// Version number of the ApplicationCertificate_t struct +#define APPLICATION_CERTIFICATE_VERSION (1UL) +/// The application is not signed +#define APPLICATION_SIGNATURE_NONE (0UL) +/// @brief The SHA-256 digest of the application is signed using ECDSA with the +/// NIST P-256 curve. +#define APPLICATION_SIGNATURE_ECDSA_P256 (1UL << 0UL) +/// @brief The application is not signed, but has a CRC-32 checksum +#define APPLICATION_SIGNATURE_CRC32 (1UL << 1UL) + +/// The application contains a Zigbee wireless stack +#define APPLICATION_TYPE_ZIGBEE (1UL << 0UL) +/// The application contains a Thread wireless stack +#define APPLICATION_TYPE_THREAD (1UL << 1UL) +/// The application contains a Flex wireless stack +#define APPLICATION_TYPE_FLEX (1UL << 2UL) +/// The application contains a Bluetooth wireless stack +#define APPLICATION_TYPE_BLUETOOTH (1UL << 3UL) +/// The application is an MCU application +#define APPLICATION_TYPE_MCU (1UL << 4UL) +/// The application contains a Bluetooth application +#define APPLICATION_TYPE_BLUETOOTH_APP (1UL << 5UL) +/// The application contains a bootloader +#define APPLICATION_TYPE_BOOTLOADER (1UL << 6UL) +/// The application contains a Zwave wireless stack +#define APPLICATION_TYPE_ZWAVE (1UL << 7UL) + +/// Application Data +typedef struct ApplicationData { + /// @brief Bitfield representing type of application, e.g., + /// @ref APPLICATION_TYPE_ZIGBEE + uint32_t type; + /// Version number for this application + uint32_t version; + /// Capabilities of this application + uint32_t capabilities; + /// Unique ID (UUID or GUID) for the product this application is built for + uint8_t productId[16]; +} ApplicationData_t; + +/// Application Certificate +typedef struct ApplicationCertificate { + /// Version of the certificate structure + uint8_t structVersion; + /// Reserved flags + uint8_t flags[3]; + /// Public key + uint8_t key[64]; + /// The version number of this certificate + uint32_t version; + /// Signature of the certificate + uint8_t signature[64]; +} ApplicationCertificate_t; + +/// Application Properties struct +typedef struct { + /// @brief Magic value indicating this is an ApplicationProperties_t struct. + /// Must equal @ref APPLICATION_PROPERTIES_MAGIC + uint8_t magic[16]; + /// Version number of this struct + uint32_t structVersion; + /// Type of signature this application is signed with + uint32_t signatureType; + /// Location of the signature. Typically points to the end of the application + uint32_t signatureLocation; + /// Information about the application + ApplicationData_t app; + /// Pointer to information about the certificate + ApplicationCertificate_t *cert; + /// Pointer to Long Token Data Section + uint8_t *longTokenSectionAddress; + /// Parser Decryption Key + const uint8_t decryptKey[16]; +} ApplicationProperties_t; + +/** @} (end addtogroup ApplicationProperties) */ +/** @} (end addtogroup Interface) */ + +/// Application Properties major version shift value +#define APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT (0U) +/// Application Properties minor version shift value +#define APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT (8U) + +/// Application Properties major version mask +#define APPLICATION_PROPERTIES_VERSION_MAJOR_MASK (0x000000FFU) +/// Application Properties minor version mask +#define APPLICATION_PROPERTIES_VERSION_MINOR_MASK (0xFFFFFF00U) + +/// Version number of the AppliationProperties_t struct +#define APPLICATION_PROPERTIES_VERSION ((APPLICATION_PROPERTIES_VERSION_MINOR \ + << APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) \ + | (APPLICATION_PROPERTIES_VERSION_MAJOR \ + << APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT)) + +#if (APPLICATION_PROPERTIES_VERSION_MAJOR \ + > (APPLICATION_PROPERTIES_VERSION_MAJOR_MASK >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT)) +|| (APPLICATION_PROPERTIES_VERSION_MINOR \ + > (APPLICATION_PROPERTIES_VERSION_MINOR_MASK >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT)) +#error "Invalid application properties version" +#endif + +#endif // APPLICATION_PROPERTIES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_errorcode.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_errorcode.h index 4f53920..8d554c1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_errorcode.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_errorcode.h @@ -1,379 +1,379 @@ -/***************************************************************************//** - * @file - * @brief Error codes used and exposed by the bootloader. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_ERRORCODE_H -#define BTL_ERRORCODE_H - -/** - * @addtogroup ErrorCodes Error Codes - * @brief Bootloader error codes - * @details - * @{ - */ - -/// No error, operation OK -#define BOOTLOADER_OK 0L - -/** - * @addtogroup ErrorBases Error Code Base Values - * @brief Bootloader error code base values, per logical function - * @details - * @{ - */ -/// Initialization errors -#define BOOTLOADER_ERROR_INIT_BASE 0x0100L -/// Image verification errors -#define BOOTLOADER_ERROR_PARSE_BASE 0x0200L -/// Storage errors -#define BOOTLOADER_ERROR_STORAGE_BASE 0x0400L -/// Bootload errors -#define BOOTLOADER_ERROR_BOOTLOAD_BASE 0x0500L -/// Security errors -#define BOOTLOADER_ERROR_SECURITY_BASE 0x0600L -/// Communication component errors -#define BOOTLOADER_ERROR_COMMUNICATION_BASE 0x0700L -/// XMODEM parser errors -#define BOOTLOADER_ERROR_XMODEM_BASE 0x0900L -/// Image file parser errors -#define BOOTLOADER_ERROR_PARSER_BASE 0x1000L -/// SPI Peripheral driver errors -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE 0x1100L -/// UART driver errors -#define BOOTLOADER_ERROR_UART_BASE 0x1200L -/// Compression errors -#define BOOTLOADER_ERROR_COMPRESSION_BASE 0x1300L - -/** @} addtogroup ErrorBases */ - -/** - * @addtogroup InitError Initialization Error Codes - * @brief Bootloader error codes returned by initialization code. - * @details - * Offset from @ref BOOTLOADER_ERROR_INIT_BASE - * @{ - */ -/// Storage initialization error -#define BOOTLOADER_ERROR_INIT_STORAGE \ - (BOOTLOADER_ERROR_INIT_BASE | 0x01L) -/// Bootloader table invalid -#define BOOTLOADER_ERROR_INIT_TABLE \ - (BOOTLOADER_ERROR_INIT_BASE | 0x02L) -/// Bootloader SFDP not supported -#define BOOTLOADER_ERROR_INIT_SFDP \ - (BOOTLOADER_ERROR_INIT_BASE | 0x03L) - -/** @} addtogroup InitError */ - -/** - * @addtogroup ParseErrpr Parse Error Codes - * @brief Bootloader error codes returned by image parsing. - * @details - * Offset from @ref BOOTLOADER_ERROR_PARSE_BASE - * @{ - */ -/// Parse not complete, continue calling the -/// parsing function -#define BOOTLOADER_ERROR_PARSE_CONTINUE (BOOTLOADER_ERROR_PARSE_BASE | 0x01L) -/// Verification failed -#define BOOTLOADER_ERROR_PARSE_FAILED (BOOTLOADER_ERROR_PARSE_BASE | 0x02L) -/// Verification successfully completed. Image is valid. -#define BOOTLOADER_ERROR_PARSE_SUCCESS (BOOTLOADER_ERROR_PARSE_BASE | 0x03L) -/// Bootloader has no storage, and cannot parse images. -#define BOOTLOADER_ERROR_PARSE_STORAGE (BOOTLOADER_ERROR_PARSE_BASE | 0x04L) -/// Parse context incompatible with parse function -#define BOOTLOADER_ERROR_PARSE_CONTEXT (BOOTLOADER_ERROR_PARSE_BASE | 0x05L) - -/** @} addtogroup VerificationError */ - -/** - * @addtogroup StorageError Storage Driver Error Codes - * @brief Bootloader error codes returned by a storage driver. - * @details - * Offset from @ref BOOTLOADER_ERROR_STORAGE_BASE - * @{ - */ -/// Invalid slot -#define BOOTLOADER_ERROR_STORAGE_INVALID_SLOT \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x01L) -/// Invalid address. Address not aligned/out of range -#define BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x02L) -/// The storage area needs to be erased before it can be used -#define BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x03L) -/// The address or length needs to be aligned -#define BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x04L) -/// An error occured during bootload from storage -#define BOOTLOADER_ERROR_STORAGE_BOOTLOAD \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x05L) -/// There is no image in this storage slot -#define BOOTLOADER_ERROR_STORAGE_NO_IMAGE \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x06L) -/// Continue calling function -#define BOOTLOADER_ERROR_STORAGE_CONTINUE \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x07L) -/// Generic storage error -#define BOOTLOADER_ERROR_STORAGE_GENERIC \ - (BOOTLOADER_ERROR_STORAGE_BASE | 0x08L) - -/** @} addtogroup StorageError */ - -/** - * @addtogroup BootloadError Bootloading Error Codes - * @brief Bootloader error codes returned by the bootloading process. - * @details - * Offset from @ref BOOTLOADER_ERROR_BOOTLOAD_BASE - * @{ - */ -/// No images marked for bootload -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_EMPTY \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x01L) -/// List of images marked for bootload is full -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_FULL \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x02L) -/// Image already marked for bootload -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_ENTRY_EXISTS \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x03L) -/// Bootload list overflowed, requested length too large -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_OVERFLOW \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x04L) -/// No bootload list found at the base of storage -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_NO_LIST \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x05L) -/// Bootload list found but with invalid CRC -#define BOOTLOADER_ERROR_BOOTLOAD_LIST_INVALID \ - (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x06L) - -/** @} addtogroup BootloadError */ - -/** - * @addtogroup SecurityError Security Error Codes - * @brief Bootloader error codes returned by security algorithms. - * @details - * Offset from @ref BOOTLOADER_ERROR_SECURITY_BASE - * @{ - */ -/// Invalid input parameter to security algorithm -#define BOOTLOADER_ERROR_SECURITY_INVALID_PARAM \ - (BOOTLOADER_ERROR_SECURITY_BASE | 0x01L) -/// Input parameter to security algorithm is out of range -#define BOOTLOADER_ERROR_SECURITY_PARAM_OUT_RANGE \ - (BOOTLOADER_ERROR_SECURITY_BASE | 0x02L) -/// Invalid option for security algorithm -#define BOOTLOADER_ERROR_SECURITY_INVALID_OPTION \ - (BOOTLOADER_ERROR_SECURITY_BASE | 0x03L) -/// Authentication did not check out -#define BOOTLOADER_ERROR_SECURITY_REJECTED \ - (BOOTLOADER_ERROR_SECURITY_BASE | 0x04L) - -/** @} addtogroup SecurityError */ - -/** - * @addtogroup CommunicationError Communication Component Error Codes - * @brief Bootloader error codes returned by communication components. - * @details - * Offset from @ref BOOTLOADER_ERROR_COMMUNICATION_BASE - * @{ - */ -/// Invalid input parameter to security algorithm -/// Could not initialize hardware resources for communication protocol -#define BOOTLOADER_ERROR_COMMUNICATION_INIT \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x01L) -/// @brief Could not start communication with host (timeout, sync error, -/// version mismatch, ...) -#define BOOTLOADER_ERROR_COMMUNICATION_START \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x02L) -/// Host closed communication, no image received -#define BOOTLOADER_ERROR_COMMUNICATION_DONE \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x03L) -/// Unrecoverable error in host-bootloader communication -#define BOOTLOADER_ERROR_COMMUNICATION_ERROR \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x04L) -/// Host closed communication, no valid image received -#define BOOTLOADER_ERROR_COMMUNICATION_IMAGE_ERROR \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x05L) -/// Communication aborted, no response from host -#define BOOTLOADER_ERROR_COMMUNICATION_TIMEOUT \ - (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x06L) - -/** @} addtogroup CommunicationError */ - -/** - * @addtogroup XmodemError XMODEM Error Codes - * @brief Bootloader error codes returned by the XMODEM parser. - * @details - * Offset from @ref BOOTLOADER_ERROR_XMODEM_BASE - * @{ - */ -/// Could not verify lower CRC byte -#define BOOTLOADER_ERROR_XMODEM_CRCL \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x01L) -/// Could not verify upper CRC byte -#define BOOTLOADER_ERROR_XMODEM_CRCH \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x02L) -/// No start of header found -#define BOOTLOADER_ERROR_XMODEM_NO_SOH \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x03L) -/// Packet number doesn't match its inverse -#define BOOTLOADER_ERROR_XMODEM_PKTNUM \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x04L) -/// Packet number error (unexpected sequence) -#define BOOTLOADER_ERROR_XMODEM_PKTSEQ \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x05L) -/// Packet number error (duplicate) -#define BOOTLOADER_ERROR_XMODEM_PKTDUP \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x06L) -/// Transfer is done (Technically not an error) -#define BOOTLOADER_ERROR_XMODEM_DONE \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x07L) -/// Transfer is canceled -#define BOOTLOADER_ERROR_XMODEM_CANCEL \ - (BOOTLOADER_ERROR_XMODEM_BASE | 0x08L) - -/** @} addtogroup XmodemError */ - -/** - * @addtogroup ParserError Image Parser Error Codes - * @brief Bootloader error codes returned by the image file parser. - * @details - * Offset from @ref BOOTLOADER_ERROR_PARSER_BASE - * @{ - */ -/// Encountered unexpected data/option -#define BOOTLOADER_ERROR_PARSER_UNEXPECTED \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x01L) -/// Ran out of internal buffer space. -/// Please increase internal buffer size to match biggest header -#define BOOTLOADER_ERROR_PARSER_BUFFER \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x02L) -/// Internal state: done parsing the current input buffer -#define BOOTLOADER_ERROR_PARSER_PARSED \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x03L) -/// Invalid encryption key or no key not present -#define BOOTLOADER_ERROR_PARSER_KEYERROR \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x04L) -/// Invalid checksum -#define BOOTLOADER_ERROR_PARSER_CRC \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x05L) -/// Invalid signature -#define BOOTLOADER_ERROR_PARSER_SIGNATURE \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x06L) -/// Image parsing is already done (or has previously errored out) -#define BOOTLOADER_ERROR_PARSER_EOF \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x07L) -/// Unknown data type in image file -#define BOOTLOADER_ERROR_PARSER_UNKNOWN_TAG \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x08L) -/// Image file version doesn't match with parser -#define BOOTLOADER_ERROR_PARSER_VERSION \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x09L) -/// Image file type doesn't match with parser -#define BOOTLOADER_ERROR_PARSER_FILETYPE \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x0AL) -/// Initialization failed -#define BOOTLOADER_ERROR_PARSER_INIT \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x0BL) -/// Upgrade file was rejected -#define BOOTLOADER_ERROR_PARSER_REJECTED \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x0CL) -/// Upgrade file overlaps with the upgrade location -#define BOOTLOADER_ERROR_PARSER_OVERLAP \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x0DL) -/// A GBL tag occurred in an order forbidden by the GBL format spec -#define BOOTLOADER_ERROR_PARSER_INVALID_TAG_ORDER \ - (BOOTLOADER_ERROR_PARSER_BASE | 0x0EL) - -/** @} addtogroup ParserError */ - -/** - * @addtogroup SpiPeripheralError SPI Peripheral Driver Error Codes - * @brief Bootloader error codes returned by the SPI Peripheral driver. - * @details - * Offset from @ref BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE - * @{ - */ -/// Operation not allowed because hardware has not been initialized -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_UNINIT \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x01) -/// Hardware fail during initialization -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_INIT \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x02) -/// Invalid argument -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_ARGUMENT \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x03) -/// Timeout -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_TIMEOUT \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x04) -/// Buffer overflow condition -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_OVERFLOW \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x05) -/// Busy condition -#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BUSY \ - (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x06) - -/** @} addtogroup SpiPeripheralError */ - -/** - * @addtogroup UartError UART Driver Error Codes - * @brief Bootloader error codes returned by the UART driver. - * @details - * Offset from @ref BOOTLOADER_ERROR_UART_BASE - * @{ - */ -/// Operation not allowed because hardware has not been initialized -#define BOOTLOADER_ERROR_UART_UNINIT (BOOTLOADER_ERROR_UART_BASE | 0x01) -/// Hardware fail during initialization -#define BOOTLOADER_ERROR_UART_INIT (BOOTLOADER_ERROR_UART_BASE | 0x02) -/// Invalid argument -#define BOOTLOADER_ERROR_UART_ARGUMENT (BOOTLOADER_ERROR_UART_BASE | 0x03) -/// Operation timed out -#define BOOTLOADER_ERROR_UART_TIMEOUT (BOOTLOADER_ERROR_UART_BASE | 0x04) -/// Buffer overflow condition -#define BOOTLOADER_ERROR_UART_OVERFLOW (BOOTLOADER_ERROR_UART_BASE | 0x05) -/// Busy condition -#define BOOTLOADER_ERROR_UART_BUSY (BOOTLOADER_ERROR_UART_BASE | 0x06) - -/** @} addtogroup UartError */ - -/** - * @addtogroup CompressionError Compression Error Codes - * @brief Bootloader error codes returned by the decompressor - * @details - * Offset from @ref BOOTLOADER_ERROR_COMPRESSION_BASE - * @{ - */ -/// Could not initialize decompressor -#define BOOTLOADER_ERROR_COMPRESSION_INIT \ - (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x01) -/// Invalid decompressor state -- possible invalid input -#define BOOTLOADER_ERROR_COMPRESSION_STATE \ - (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x02) -/// Data error -#define BOOTLOADER_ERROR_COMPRESSION_DATA \ - (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x03) -/// Data length error -#define BOOTLOADER_ERROR_COMPRESSION_DATALEN \ - (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x04) -/// Memory error -#define BOOTLOADER_ERROR_COMPRESSION_MEM \ - (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x05) - -/** @} addtogroup CompressionError */ - -/** @} addtogroup ErrorCodes */ - -#endif // BTL_ERRORCODE_H +/***************************************************************************//** + * @file + * @brief Error codes used and exposed by the bootloader. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_ERRORCODE_H +#define BTL_ERRORCODE_H + +/** + * @addtogroup ErrorCodes Error Codes + * @brief Bootloader error codes + * @details + * @{ + */ + +/// No error, operation OK +#define BOOTLOADER_OK 0L + +/** + * @addtogroup ErrorBases Error Code Base Values + * @brief Bootloader error code base values, per logical function + * @details + * @{ + */ +/// Initialization errors +#define BOOTLOADER_ERROR_INIT_BASE 0x0100L +/// Image verification errors +#define BOOTLOADER_ERROR_PARSE_BASE 0x0200L +/// Storage errors +#define BOOTLOADER_ERROR_STORAGE_BASE 0x0400L +/// Bootload errors +#define BOOTLOADER_ERROR_BOOTLOAD_BASE 0x0500L +/// Security errors +#define BOOTLOADER_ERROR_SECURITY_BASE 0x0600L +/// Communication component errors +#define BOOTLOADER_ERROR_COMMUNICATION_BASE 0x0700L +/// XMODEM parser errors +#define BOOTLOADER_ERROR_XMODEM_BASE 0x0900L +/// Image file parser errors +#define BOOTLOADER_ERROR_PARSER_BASE 0x1000L +/// SPI Peripheral driver errors +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE 0x1100L +/// UART driver errors +#define BOOTLOADER_ERROR_UART_BASE 0x1200L +/// Compression errors +#define BOOTLOADER_ERROR_COMPRESSION_BASE 0x1300L + +/** @} addtogroup ErrorBases */ + +/** + * @addtogroup InitError Initialization Error Codes + * @brief Bootloader error codes returned by initialization code. + * @details + * Offset from @ref BOOTLOADER_ERROR_INIT_BASE + * @{ + */ +/// Storage initialization error +#define BOOTLOADER_ERROR_INIT_STORAGE \ + (BOOTLOADER_ERROR_INIT_BASE | 0x01L) +/// Bootloader table invalid +#define BOOTLOADER_ERROR_INIT_TABLE \ + (BOOTLOADER_ERROR_INIT_BASE | 0x02L) +/// Bootloader SFDP not supported +#define BOOTLOADER_ERROR_INIT_SFDP \ + (BOOTLOADER_ERROR_INIT_BASE | 0x03L) + +/** @} addtogroup InitError */ + +/** + * @addtogroup ParseErrpr Parse Error Codes + * @brief Bootloader error codes returned by image parsing. + * @details + * Offset from @ref BOOTLOADER_ERROR_PARSE_BASE + * @{ + */ +/// Parse not complete, continue calling the +/// parsing function +#define BOOTLOADER_ERROR_PARSE_CONTINUE (BOOTLOADER_ERROR_PARSE_BASE | 0x01L) +/// Verification failed +#define BOOTLOADER_ERROR_PARSE_FAILED (BOOTLOADER_ERROR_PARSE_BASE | 0x02L) +/// Verification successfully completed. Image is valid. +#define BOOTLOADER_ERROR_PARSE_SUCCESS (BOOTLOADER_ERROR_PARSE_BASE | 0x03L) +/// Bootloader has no storage, and cannot parse images. +#define BOOTLOADER_ERROR_PARSE_STORAGE (BOOTLOADER_ERROR_PARSE_BASE | 0x04L) +/// Parse context incompatible with parse function +#define BOOTLOADER_ERROR_PARSE_CONTEXT (BOOTLOADER_ERROR_PARSE_BASE | 0x05L) + +/** @} addtogroup VerificationError */ + +/** + * @addtogroup StorageError Storage Driver Error Codes + * @brief Bootloader error codes returned by a storage driver. + * @details + * Offset from @ref BOOTLOADER_ERROR_STORAGE_BASE + * @{ + */ +/// Invalid slot +#define BOOTLOADER_ERROR_STORAGE_INVALID_SLOT \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x01L) +/// Invalid address. Address not aligned/out of range +#define BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x02L) +/// The storage area needs to be erased before it can be used +#define BOOTLOADER_ERROR_STORAGE_NEEDS_ERASE \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x03L) +/// The address or length needs to be aligned +#define BOOTLOADER_ERROR_STORAGE_NEEDS_ALIGN \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x04L) +/// An error occured during bootload from storage +#define BOOTLOADER_ERROR_STORAGE_BOOTLOAD \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x05L) +/// There is no image in this storage slot +#define BOOTLOADER_ERROR_STORAGE_NO_IMAGE \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x06L) +/// Continue calling function +#define BOOTLOADER_ERROR_STORAGE_CONTINUE \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x07L) +/// Generic storage error +#define BOOTLOADER_ERROR_STORAGE_GENERIC \ + (BOOTLOADER_ERROR_STORAGE_BASE | 0x08L) + +/** @} addtogroup StorageError */ + +/** + * @addtogroup BootloadError Bootloading Error Codes + * @brief Bootloader error codes returned by the bootloading process. + * @details + * Offset from @ref BOOTLOADER_ERROR_BOOTLOAD_BASE + * @{ + */ +/// No images marked for bootload +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_EMPTY \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x01L) +/// List of images marked for bootload is full +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_FULL \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x02L) +/// Image already marked for bootload +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_ENTRY_EXISTS \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x03L) +/// Bootload list overflowed, requested length too large +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_OVERFLOW \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x04L) +/// No bootload list found at the base of storage +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_NO_LIST \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x05L) +/// Bootload list found but with invalid CRC +#define BOOTLOADER_ERROR_BOOTLOAD_LIST_INVALID \ + (BOOTLOADER_ERROR_BOOTLOAD_BASE | 0x06L) + +/** @} addtogroup BootloadError */ + +/** + * @addtogroup SecurityError Security Error Codes + * @brief Bootloader error codes returned by security algorithms. + * @details + * Offset from @ref BOOTLOADER_ERROR_SECURITY_BASE + * @{ + */ +/// Invalid input parameter to security algorithm +#define BOOTLOADER_ERROR_SECURITY_INVALID_PARAM \ + (BOOTLOADER_ERROR_SECURITY_BASE | 0x01L) +/// Input parameter to security algorithm is out of range +#define BOOTLOADER_ERROR_SECURITY_PARAM_OUT_RANGE \ + (BOOTLOADER_ERROR_SECURITY_BASE | 0x02L) +/// Invalid option for security algorithm +#define BOOTLOADER_ERROR_SECURITY_INVALID_OPTION \ + (BOOTLOADER_ERROR_SECURITY_BASE | 0x03L) +/// Authentication did not check out +#define BOOTLOADER_ERROR_SECURITY_REJECTED \ + (BOOTLOADER_ERROR_SECURITY_BASE | 0x04L) + +/** @} addtogroup SecurityError */ + +/** + * @addtogroup CommunicationError Communication Component Error Codes + * @brief Bootloader error codes returned by communication components. + * @details + * Offset from @ref BOOTLOADER_ERROR_COMMUNICATION_BASE + * @{ + */ +/// Invalid input parameter to security algorithm +/// Could not initialize hardware resources for communication protocol +#define BOOTLOADER_ERROR_COMMUNICATION_INIT \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x01L) +/// @brief Could not start communication with host (timeout, sync error, +/// version mismatch, ...) +#define BOOTLOADER_ERROR_COMMUNICATION_START \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x02L) +/// Host closed communication, no image received +#define BOOTLOADER_ERROR_COMMUNICATION_DONE \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x03L) +/// Unrecoverable error in host-bootloader communication +#define BOOTLOADER_ERROR_COMMUNICATION_ERROR \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x04L) +/// Host closed communication, no valid image received +#define BOOTLOADER_ERROR_COMMUNICATION_IMAGE_ERROR \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x05L) +/// Communication aborted, no response from host +#define BOOTLOADER_ERROR_COMMUNICATION_TIMEOUT \ + (BOOTLOADER_ERROR_COMMUNICATION_BASE | 0x06L) + +/** @} addtogroup CommunicationError */ + +/** + * @addtogroup XmodemError XMODEM Error Codes + * @brief Bootloader error codes returned by the XMODEM parser. + * @details + * Offset from @ref BOOTLOADER_ERROR_XMODEM_BASE + * @{ + */ +/// Could not verify lower CRC byte +#define BOOTLOADER_ERROR_XMODEM_CRCL \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x01L) +/// Could not verify upper CRC byte +#define BOOTLOADER_ERROR_XMODEM_CRCH \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x02L) +/// No start of header found +#define BOOTLOADER_ERROR_XMODEM_NO_SOH \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x03L) +/// Packet number doesn't match its inverse +#define BOOTLOADER_ERROR_XMODEM_PKTNUM \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x04L) +/// Packet number error (unexpected sequence) +#define BOOTLOADER_ERROR_XMODEM_PKTSEQ \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x05L) +/// Packet number error (duplicate) +#define BOOTLOADER_ERROR_XMODEM_PKTDUP \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x06L) +/// Transfer is done (Technically not an error) +#define BOOTLOADER_ERROR_XMODEM_DONE \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x07L) +/// Transfer is canceled +#define BOOTLOADER_ERROR_XMODEM_CANCEL \ + (BOOTLOADER_ERROR_XMODEM_BASE | 0x08L) + +/** @} addtogroup XmodemError */ + +/** + * @addtogroup ParserError Image Parser Error Codes + * @brief Bootloader error codes returned by the image file parser. + * @details + * Offset from @ref BOOTLOADER_ERROR_PARSER_BASE + * @{ + */ +/// Encountered unexpected data/option +#define BOOTLOADER_ERROR_PARSER_UNEXPECTED \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x01L) +/// Ran out of internal buffer space. +/// Please increase internal buffer size to match biggest header +#define BOOTLOADER_ERROR_PARSER_BUFFER \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x02L) +/// Internal state: done parsing the current input buffer +#define BOOTLOADER_ERROR_PARSER_PARSED \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x03L) +/// Invalid encryption key or no key not present +#define BOOTLOADER_ERROR_PARSER_KEYERROR \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x04L) +/// Invalid checksum +#define BOOTLOADER_ERROR_PARSER_CRC \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x05L) +/// Invalid signature +#define BOOTLOADER_ERROR_PARSER_SIGNATURE \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x06L) +/// Image parsing is already done (or has previously errored out) +#define BOOTLOADER_ERROR_PARSER_EOF \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x07L) +/// Unknown data type in image file +#define BOOTLOADER_ERROR_PARSER_UNKNOWN_TAG \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x08L) +/// Image file version doesn't match with parser +#define BOOTLOADER_ERROR_PARSER_VERSION \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x09L) +/// Image file type doesn't match with parser +#define BOOTLOADER_ERROR_PARSER_FILETYPE \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x0AL) +/// Initialization failed +#define BOOTLOADER_ERROR_PARSER_INIT \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x0BL) +/// Upgrade file was rejected +#define BOOTLOADER_ERROR_PARSER_REJECTED \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x0CL) +/// Upgrade file overlaps with the upgrade location +#define BOOTLOADER_ERROR_PARSER_OVERLAP \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x0DL) +/// A GBL tag occurred in an order forbidden by the GBL format spec +#define BOOTLOADER_ERROR_PARSER_INVALID_TAG_ORDER \ + (BOOTLOADER_ERROR_PARSER_BASE | 0x0EL) + +/** @} addtogroup ParserError */ + +/** + * @addtogroup SpiPeripheralError SPI Peripheral Driver Error Codes + * @brief Bootloader error codes returned by the SPI Peripheral driver. + * @details + * Offset from @ref BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE + * @{ + */ +/// Operation not allowed because hardware has not been initialized +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_UNINIT \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x01) +/// Hardware fail during initialization +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_INIT \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x02) +/// Invalid argument +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_ARGUMENT \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x03) +/// Timeout +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_TIMEOUT \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x04) +/// Buffer overflow condition +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_OVERFLOW \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x05) +/// Busy condition +#define BOOTLOADER_ERROR_SPI_PERIPHERAL_BUSY \ + (BOOTLOADER_ERROR_SPI_PERIPHERAL_BASE | 0x06) + +/** @} addtogroup SpiPeripheralError */ + +/** + * @addtogroup UartError UART Driver Error Codes + * @brief Bootloader error codes returned by the UART driver. + * @details + * Offset from @ref BOOTLOADER_ERROR_UART_BASE + * @{ + */ +/// Operation not allowed because hardware has not been initialized +#define BOOTLOADER_ERROR_UART_UNINIT (BOOTLOADER_ERROR_UART_BASE | 0x01) +/// Hardware fail during initialization +#define BOOTLOADER_ERROR_UART_INIT (BOOTLOADER_ERROR_UART_BASE | 0x02) +/// Invalid argument +#define BOOTLOADER_ERROR_UART_ARGUMENT (BOOTLOADER_ERROR_UART_BASE | 0x03) +/// Operation timed out +#define BOOTLOADER_ERROR_UART_TIMEOUT (BOOTLOADER_ERROR_UART_BASE | 0x04) +/// Buffer overflow condition +#define BOOTLOADER_ERROR_UART_OVERFLOW (BOOTLOADER_ERROR_UART_BASE | 0x05) +/// Busy condition +#define BOOTLOADER_ERROR_UART_BUSY (BOOTLOADER_ERROR_UART_BASE | 0x06) + +/** @} addtogroup UartError */ + +/** + * @addtogroup CompressionError Compression Error Codes + * @brief Bootloader error codes returned by the decompressor + * @details + * Offset from @ref BOOTLOADER_ERROR_COMPRESSION_BASE + * @{ + */ +/// Could not initialize decompressor +#define BOOTLOADER_ERROR_COMPRESSION_INIT \ + (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x01) +/// Invalid decompressor state -- possible invalid input +#define BOOTLOADER_ERROR_COMPRESSION_STATE \ + (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x02) +/// Data error +#define BOOTLOADER_ERROR_COMPRESSION_DATA \ + (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x03) +/// Data length error +#define BOOTLOADER_ERROR_COMPRESSION_DATALEN \ + (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x04) +/// Memory error +#define BOOTLOADER_ERROR_COMPRESSION_MEM \ + (BOOTLOADER_ERROR_COMPRESSION_BASE | 0x05) + +/** @} addtogroup CompressionError */ + +/** @} addtogroup ErrorCodes */ + +#endif // BTL_ERRORCODE_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.c b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.c index 4b98918..691bda3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.c @@ -1,851 +1,851 @@ -/***************************************************************************//** - * @file - * @brief Application interface to the bootloader. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "btl_interface.h" -#include "em_core.h" -#include "btl_interface_cfg.h" -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - -// ----------------------------------------------------------------------------- -// Configurations - -#if ((!defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING) \ - || (defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING) \ - && (BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING == 0))) && defined(SL_CATALOG_NVM3_PRESENT)) -#define BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING -#endif // BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING && SL_CATALOG_NVM3_PRESENT - -#if !defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE) \ - || (defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE) \ - && (BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE == 0)) -#define BOOTLOADER_ENABLE_USART_AUTO_DETECTION -#endif // BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE - -#if (defined(BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION) \ - && (BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION == 1)) -#define BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK -#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING -#undef BOOTLOADER_ENABLE_USART_AUTO_DETECTION -#endif // BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION - -#if defined(SL_TRUSTZONE_SECURE) -#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING -#endif // SL_TRUSTZONE_SECURE - -// ----------------------------------------------------------------------------- -// Configuration spesifics - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) -// Allocated range of NVM3 IDs for bootloader usage */ -#define BL_NVM3_RESERVED_ID (0x87100UL) - -#include -#include "nvm3_default.h" - -static bool blPPUSATDnStateCacheSet = false; -static uint32_t blPPUSATDnStateCache[2] = { 0 }; -#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING - -#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) -static void preConfigureUsartPPUSATD(void); -static void storeUsartInUse(void); -static int32_t usartNumberSpi = -1; -#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION - -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - -// ----------------------------------------------------------------------------- -// Static variables - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) -#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) -static CORE_DECLARE_IRQ_STATE; -#endif -static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 }; - -typedef enum { - IDLE, SAVE, TIERED -} ppusatdConfigurationState_t; - -static ppusatdConfigurationState_t bootloader_ppusatdConfigstate = IDLE; -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - -// ----------------------------------------------------------------------------- -// Enums - -typedef enum { - RESET, INITIALIZED, DEINITIALIZED -} initState_t; - -static initState_t bootloader_InitState = RESET; - -// ----------------------------------------------------------------------------- -// Test helpers - -#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) -extern bool enabled; -extern void enterUnprivilegedMode(bool); -extern void exitUnprivilegedMode(void); -#endif // BOOTLOADER_TEST_UNPRIVILEGED_ACCESS - -// ----------------------------------------------------------------------------- -// Functions - -void bootloader_getInfo(BootloaderInformation_t *info) -{ -#if defined(BOOTLOADER_HAS_FIRST_STAGE) - if (!bootloader_pointerToFirstStageValid(firstBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable)) { - // No bootloader is present (first stage or main stage invalid) - info->type = NO_BOOTLOADER; - info->capabilities = 0; - } else if ((firstBootloaderTable->header.type == BOOTLOADER_MAGIC_FIRST_STAGE) - && (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN)) { - info->type = SL_BOOTLOADER; - info->version = mainBootloaderTable->header.version; - info->capabilities = mainBootloaderTable->capabilities; - } else { - info->type = NO_BOOTLOADER; - info->capabilities = 0; - } -#else - if (!bootloader_pointerValid(mainBootloaderTable)) { - // No bootloader is present (first stage or main stage invalid) - info->type = NO_BOOTLOADER; - info->capabilities = 0; - } else if (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN) { - info->type = SL_BOOTLOADER; - info->version = mainBootloaderTable->header.version; - info->capabilities = mainBootloaderTable->capabilities; - } else { - info->type = NO_BOOTLOADER; - info->capabilities = 0; - } -#endif -} - -int32_t bootloader_init(void) -{ - int32_t retVal; - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - - if (bootloader_InitState == RESET || bootloader_InitState == DEINITIALIZED) { -#if defined(SL_TRUSTZONE_SECURE) - if (bootloader_InitState == RESET) { - // Enable SMU bus clock at the start-up of the TZ secure application - // to make it possible to configure the SMU peripheral. Since the CMU address - // is known. Otherwise, delegate the SMU bus clock enablement to the NS application. -#if defined(_CMU_CLKEN1_SMU_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_SMU; -#endif // _CMU_CLKEN1_SMU_MASK - } -#endif // SL_TRUSTZONE_SECURE - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) - NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); - SMU->IF_CLR = SMU_IEN_PPUSEC; - NVIC_EnableIRQ(SMU_SECURE_IRQn); - SMU->IEN_SET = SMU_IEN_PPUSEC; -#endif - retVal = mainBootloaderTable->init(); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif - - if (retVal == BOOTLOADER_OK) { - bootloader_InitState = INITIALIZED; - } - } else { - retVal = BOOTLOADER_OK; - } - return retVal; -} - -int32_t bootloader_deinit(void) -{ - int32_t retVal; - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - - if (bootloader_InitState == INITIALIZED) { -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) - SMU->IF_CLR = SMU_IEN_PPUSEC; - SMU->IEN_CLR = SMU_IEN_PPUSEC; - NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); - NVIC_DisableIRQ(SMU_SECURE_IRQn); -#endif - - retVal = mainBootloaderTable->deinit(); - if (retVal == BOOTLOADER_OK) { - bootloader_InitState = DEINITIALIZED; - } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - } else { - retVal = BOOTLOADER_OK; - } - return retVal; -} - -BootloaderResetCause_t bootloader_getResetReason(void) -{ - volatile BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); - return *resetCause; -} - -void bootloader_rebootAndInstall(void) -{ - // Set reset reason to bootloader entry - BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); - resetCause->reason = BOOTLOADER_RESET_REASON_BOOTLOAD; - resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID; -#if defined(RMU_PRESENT) - // Clear resetcause - RMU->CMD = RMU_CMD_RCCLR; - // Trigger a software system reset - RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_FULL; -#endif - NVIC_SystemReset(); -} - -int32_t bootloader_initParser(BootloaderParserContext_t *context, - size_t contextSize) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_PARSE_FAILED; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->initParser(context, contextSize); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_parseBuffer(BootloaderParserContext_t *context, - BootloaderParserCallbacks_t *callbacks, - uint8_t data[], - size_t numBytes) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_PARSE_FAILED; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->parseBuffer(context, callbacks, data, numBytes); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context, - uint8_t data[], - size_t numBytes, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_PARSE_FAILED; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) - >> BOOTLOADER_VERSION_MAJOR_SHIFT); - uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) - >> BOOTLOADER_VERSION_MINOR_SHIFT); - - if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { - return BOOTLOADER_ERROR_PARSE_FAILED; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->parseImageInfo(context, data, numBytes, appInfo, bootloaderVersion); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -uint32_t bootloader_parserContextSize(void) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return 0UL; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) - >> BOOTLOADER_VERSION_MAJOR_SHIFT); - uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) - >> BOOTLOADER_VERSION_MINOR_SHIFT); - - if (blMajorVersion < 1UL) { - return 384UL; - } - - if (blMajorVersion == 1UL && blMinorVersion < 11UL) { -#if defined(_SILICON_LABS_32B_SERIES_2) - if (blMinorVersion == 10UL) { - return 524UL; - } else { - return 384UL; - } -#else - return 384UL; -#endif - } - - return mainBootloaderTable->parserContextSize(); -} - -bool bootloader_verifyApplication(uint32_t startAddress) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return false; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - bool retVal = mainBootloaderTable->verifyApplication(startAddress); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -bool bootloader_secureBootEnforced(void) -{ - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - if (info.capabilities & BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT) { - return true; - } - return false; -} - -bool bootloader_getUpgradeLocation(uint32_t *location) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return false; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) - >> BOOTLOADER_VERSION_MAJOR_SHIFT); - uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) - >> BOOTLOADER_VERSION_MINOR_SHIFT); - - if (blMajorVersion == 2UL && blMinorVersion >= 1UL) { - *location = mainBootloaderTable->getUpgradeLocation(); - return true; - } - - return false; -} - -#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -uint32_t bootloader_remainingApplicationUpgrades(void) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return 0UL; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) - >> BOOTLOADER_VERSION_MAJOR_SHIFT); - uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) - >> BOOTLOADER_VERSION_MINOR_SHIFT); - - if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { - return 0UL; - } - - return mainBootloaderTable->remainingApplicationUpgrades(); -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) -bool bootloader_getCertificateVersion(uint32_t *version) -{ - // Access word 13 to read sl_app_properties of the bootloader. - ApplicationProperties_t *blProperties = - (ApplicationProperties_t *)(*(uint32_t *)(BTL_MAIN_STAGE_BASE + 52UL)); - - if (!bootloader_pointerValid(blProperties)) { - return false; - } - - // Compatibility check of the application properties struct. - if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MAJOR_MASK) - >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT) < 1UL) { - return false; - } - if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MINOR_MASK) - >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) < 1UL) { - return false; - } - - if (blProperties->cert == NULL) { - return false; - } - - *version = blProperties->cert->version; - return true; -} -#endif // _SILICON_LABS_32B_SERIES_2 - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) -void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1) -{ - if (!bootloader_pointerValid(mainBootloaderTable)) { - return; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - if (info.capabilities & BOOTLOADER_CAPABILITY_PERIPHERAL_LIST) { - mainBootloaderTable->getPeripheralList(ppusatd0, ppusatd1); - } -} - -void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx) -{ - if (bootloader_ppusatdConfigstate != IDLE) { - // This function is called from a bootloader callback function - bootloader_ppusatdConfigstate = TIERED; - return; - } - uint32_t ppusatd0 = 0u; - uint32_t ppusatd1 = 0u; - - if (ctx == NULL) { - return; - } - - bootloader_ppusatdConfigstate = SAVE; - - // Enter ATOMIC section. The ATOMIC section is exited when - // the restore function is called. -#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) - CORE_ENTER_ATOMIC(); -#endif - - sli_bootloader_preHook(); - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) - // Read the stored PPUSATD state from NVM3 - if (!blPPUSATDnStateCacheSet) { - Ecode_t status; - status = nvm3_initDefault(); - if (status == ECODE_NVM3_OK) { - nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID; - status = nvm3_readData(nvm3_defaultHandle, - object_id, - blPPUSATDnStateCache, - sizeof(blPPUSATDnStateCache)); - if (status == ECODE_NVM3_OK) { - blPPUSATDnStateCacheSet = true; - } - } - } -#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING - - // Store the CLKENn states -#if defined(_CMU_CLKEN0_MASK) - ctx->CLKEN0 = CMU->CLKEN0; - ctx->CLKEN1 = CMU->CLKEN1; -#endif - -#if defined(_CMU_CLKEN1_SMU_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_SMU; -#endif // _CMU_CLKEN1_SMU_MASK - ctx->SMU_STATUS = SMU->STATUS; - - // Unlock SMU before re-configuration - SMU->LOCK = SMU_LOCK_SMULOCKKEY_UNLOCK; - - // Store the PPUSATDn states - ctx->PPUSATD0 = SMU->PPUSATD0; - ctx->PPUSATD1 = SMU->PPUSATD1; - ctx->BMPUSATD0 = SMU->BMPUSATD0; - -#if defined(SMU_NS_CFGNS_BASE) - // Store the PPUPATDn states - ctx->PPUPATD0 = SMU->PPUPATD0; - ctx->PPUPATD1 = SMU->PPUPATD1; - - SMU->PPUPATD0 = SMU_NS_CFGNS->PPUNSPATD0; - SMU->PPUPATD1 = SMU_NS_CFGNS->PPUNSPATD1; -#endif // SMU_NS_CFGNS_BASE - -#if defined(CMU_CLKEN0_LDMA) - CMU->CLKEN0_SET = CMU_CLKEN0_LDMA; -#endif // CMU_CLKEN0_LDMA -#if defined(CRYPTOACC_PRESENT) - CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; -#endif - - // Wait for any active transition of other busmasters to finish - if (SMU->PPUSATD0 & SMU_PPUSATD0_LDMA) { - while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ; - } else { - while (LDMA_NS->STATUS & LDMA_STATUS_ANYBUSY) ; - } -#if defined(CRYPTOACC_PRESENT) - if (SMU->PPUSATD1 & SMU_PPUSATD1_CRYPTOACC) { - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) - while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; - #else - while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; - #endif - } else { - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) - while (CRYPTOACC_NS->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; - #else - while (CRYPTOACC_NS->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; - #endif - } -#endif // CRYPTOACC_PRESENT - - // Configure the peripheral secure access state before calling into the bootloader. -#if !defined(BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK) -#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) - // If we do not know which USART is used by the bootloader, - // and the bootloader is not initialized, - // Configure PPUSATDn bits for all the USART not in use. - preConfigureUsartPPUSATD(); -#else - SMU->PPUSATD0_SET = BOOTLOADER_PPUSATD0_MASK; - SMU->PPUSATD1_SET = BOOTLOADER_PPUSATD1_MASK; -#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION - - SMU->PPUSATD0_SET = SMU_PPUSATD0_CMU; - SMU->PPUSATD0_SET = SMU_PPUSATD0_MSC; - if (bootloader_getAllocatedDMAChannel() != -1 - && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) { - SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMA; - SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMAXBAR; - SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA; - } - - SMU->PPUSATD0_SET = SMU_PPUSATD0_HFRCO0; -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - SMU->PPUSATD0_SET = SMU_PPUSATD0_GPIO; -#endif - SMU->PPUSATD0_SET = SMU_PPUSATD0_GPCRC; -#if defined(SMU_PPUSATD1_CRYPTOACC) - SMU->PPUSATD1_SET = SMU_PPUSATD1_CRYPTOACC; -#endif // SMU_PPUSATD1_CRYPTOACC -#if defined(SMU_PPUSATD1_SEMAILBOX) - SMU->PPUSATD1_SET = SMU_PPUSATD1_SEMAILBOX; -#endif // SMU_PPUSATD1_SEMAILBOX -#elif defined(SL_TRUSTZONE_SECURE) - #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA0; - SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA1; - #else - SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA; - #endif -#endif // BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK - - bootloader_getPeripheralList(&ppusatd0, &ppusatd1); - SMU->PPUSATD0_SET = ppusatd0; - SMU->PPUSATD1_SET = ppusatd1; - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) - // Update the peripheral secure access state of - // the "unknown" peripheral that triggered a fault earlier - if (blPPUSATDnStateCacheSet == true) { - SMU->PPUSATD0_SET = blPPUSATDnStateCache[0]; - SMU->PPUSATD1_SET = blPPUSATDnStateCache[1]; - } -#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING -#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) - enterUnprivilegedMode(enabled); -#endif -} - -void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx) -{ -#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) - exitUnprivilegedMode(); -#endif - - if (bootloader_ppusatdConfigstate != SAVE) { - // This function is called from a bootloader callback function - bootloader_ppusatdConfigstate = SAVE; - return; - } - - if (ctx == NULL) { - return; - } - - // Wait for any active transition of other busmasters to finish - if (bootloader_getAllocatedDMAChannel() != -1 - && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) { -#if defined(CMU_CLKEN0_LDMA) - CMU_S->CLKEN0_SET = CMU_CLKEN0_LDMA; -#endif // CMU_CLKEN0_LDMA - while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ; - } -#if defined(CRYPTOACC_PRESENT) - CMU_S->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) - while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; - #else - while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; - #endif -#endif // CRYPTOACC_PRESENT - - SMU->PPUSATD0 = ctx->PPUSATD0; - SMU->PPUSATD1 = ctx->PPUSATD1; - SMU->BMPUSATD0 = ctx->BMPUSATD0; -#if defined(SMU_NS_CFGNS_BASE) - SMU->PPUPATD0 = ctx->PPUPATD0; - SMU->PPUPATD1 = ctx->PPUPATD1; -#endif // SMU_NS_CFGNS_BASE - if (ctx->SMU_STATUS & SMU_STATUS_SMULOCK) { - SMU->LOCK = 0u; - } - -#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) - storeUsartInUse(); -#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION - - // Restore the CLKENn states -#if defined(_CMU_CLKEN0_MASK) - CMU->CLKEN0 = ctx->CLKEN0; - CMU->CLKEN1 = ctx->CLKEN1; -#endif - - sli_bootloader_postHook(); - -#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) - CORE_EXIT_ATOMIC(); -#endif - - // Update the state after the critical section has been - // exited to ensure that the SMU interrupt gets fired, - // before the state change happens. - bootloader_ppusatdConfigstate = IDLE; -} - -__attribute__ ((weak)) void sli_bootloader_preHook(void) -{ -} - -__attribute__ ((weak)) void sli_bootloader_postHook(void) -{ -} - -#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) -static void preConfigureUsartPPUSATD(void) -{ - if (usartNumberSpi != -1) { - SMU->PPUSATD0_SET = (SMU_PPUSATD0_USART0 << usartNumberSpi); - return; - } - - if (bootloader_InitState != RESET) { - // The USART taken by the bootloader - // is still unknown, do nothing. - return; - } -#if defined(USART0_BASE) -#if defined(CMU_CLKEN0_USART0) - CMU->CLKEN0_SET = CMU_CLKEN0_USART0; -#endif // CMU_CLKEN0_USART0 -#if defined(SL_TRUSTZONE_SECURE) - if (USART0_NS->EN == _USART_EN_RESETVALUE) { -#else - if (USART0->EN == _USART_EN_RESETVALUE) { -#endif // SL_TRUSTZONE_SECURE - SMU->PPUSATD0_SET = SMU_PPUSATD0_USART0; - } -#endif // USART0_BASE - -#if defined(USART1_BASE) -#if defined(CMU_CLKEN0_USART1) - CMU->CLKEN0_SET = CMU_CLKEN0_USART1; -#endif // CMU_CLKEN0_USART1 -#if defined(SL_TRUSTZONE_SECURE) - if (USART1_NS->EN == _USART_EN_RESETVALUE) { -#else - if (USART1->EN == _USART_EN_RESETVALUE) { -#endif // SL_TRUSTZONE_SECURE - SMU->PPUSATD0_SET = SMU_PPUSATD0_USART1; - } -#endif // USART1_BASE - -#if defined(USART2_BASE) -#if defined(CMU_CLKEN0_USART2) - CMU->CLKEN0_SET = CMU_CLKEN0_USART2; -#endif // CMU_CLKEN0_USART2 -#if defined(SL_TRUSTZONE_SECURE) - if (USART2_NS->EN == _USART_EN_RESETVALUE) { -#else - if (USART2->EN == _USART_EN_RESETVALUE) { -#endif // SL_TRUSTZONE_SECURE - SMU->PPUSATD0_SET = SMU_PPUSATD0_USART2; - } -#endif // USART2_BASE -} - -static void storeUsartInUse(void) -{ - if ((usartNumberSpi != -1) || (bootloader_InitState != RESET)) { - return; - } -#if defined(USART0_BASE) -#if defined(SL_TRUSTZONE_SECURE) - if (USART0_NS->EN & USART_EN_EN) { -#else - if (USART0->EN & USART_EN_EN) { -#endif // SL_TRUSTZONE_SECURE - usartNumberSpi = 0; - } -#endif // USART0_BASE - -#if defined(USART1_BASE) -#if defined(SL_TRUSTZONE_SECURE) - if (USART1_NS->EN & USART_EN_EN) { -#else - if (USART1->EN & USART_EN_EN) { -#endif // SL_TRUSTZONE_SECURE - usartNumberSpi = 1; - } -#endif // USART1_BASE - -#if defined(USART2_BASE) -#if defined(SL_TRUSTZONE_SECURE) - if (USART2_NS->EN & USART_EN_EN) { -#else - if (USART2->EN & USART_EN_EN) { -#endif // SL_TRUSTZONE_SECURE - usartNumberSpi = 2; - } -#endif // USART2_BASE -} -#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION - -#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) -void SMU_SECURE_IRQHandler(void) -{ -#if !defined(BOOTLOADER_TEST_FAULT_HANDLING) - if (bootloader_ppusatdConfigstate == IDLE) { - // If none of the bootloader interface operations are active, - // the fault is not caused by the bootloader. Just park in the while loop. - while (true) ; - } -#endif // BOOTLOADER_TEST_FAULT_HANDLING - - Ecode_t status; - uint32_t PPUSATDn_state[2] = { 0 }; - nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID; - - // First read the pre-existing configuration - status = nvm3_readData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); - if (status == ECODE_NVM3_OK) { - if (SMU->PPUFS > 31) { - PPUSATDn_state[1] |= 1 << (SMU->PPUFS - 32); - } else { - PPUSATDn_state[0] |= 1 << SMU->PPUFS; - } - // Nothing to do to recover if this fails, just continue and perform a reset. - (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); - } else if (status == ECODE_NVM3_ERR_KEY_NOT_FOUND) { - if (SMU->PPUFS > 31) { - PPUSATDn_state[1] = 1 << (SMU->PPUFS - 32); - } else { - PPUSATDn_state[0] = 1 << SMU->PPUFS; - } - (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); - } else { - // Do nothing. If NVM3 read fails for an unknown reason, - // perform a reset to recover from the failure state. - } - - BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); - resetCause->reason = BOOTLOADER_RESET_REASON_FAULT; - resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID; - NVIC_SystemReset(); -} -#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING - -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif +/***************************************************************************//** + * @file + * @brief Application interface to the bootloader. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "btl_interface.h" +#include "em_core.h" +#include "btl_interface_cfg.h" +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + +// ----------------------------------------------------------------------------- +// Configurations + +#if ((!defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING) \ + || (defined(BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING) \ + && (BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING == 0))) && defined(SL_CATALOG_NVM3_PRESENT)) +#define BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING +#endif // BOOTLOADER_DISABLE_NVM3_FAULT_HANDLING && SL_CATALOG_NVM3_PRESENT + +#if !defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE) \ + || (defined(BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE) \ + && (BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE == 0)) +#define BOOTLOADER_ENABLE_USART_AUTO_DETECTION +#endif // BOOTLOADER_MANUAL_OVERRIDE_SECURITY_STATE + +#if (defined(BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION) \ + && (BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION == 1)) +#define BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK +#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING +#undef BOOTLOADER_ENABLE_USART_AUTO_DETECTION +#endif // BOOTLOADER_DISABLE_OLD_BOOTLOADER_MITIGATION + +#if defined(SL_TRUSTZONE_SECURE) +#undef BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING +#endif // SL_TRUSTZONE_SECURE + +// ----------------------------------------------------------------------------- +// Configuration spesifics + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) +// Allocated range of NVM3 IDs for bootloader usage */ +#define BL_NVM3_RESERVED_ID (0x87100UL) + +#include +#include "nvm3_default.h" + +static bool blPPUSATDnStateCacheSet = false; +static uint32_t blPPUSATDnStateCache[2] = { 0 }; +#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING + +#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) +static void preConfigureUsartPPUSATD(void); +static void storeUsartInUse(void); +static int32_t usartNumberSpi = -1; +#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION + +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + +// ----------------------------------------------------------------------------- +// Static variables + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) +#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) +static CORE_DECLARE_IRQ_STATE; +#endif +static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 }; + +typedef enum { + IDLE, SAVE, TIERED +} ppusatdConfigurationState_t; + +static ppusatdConfigurationState_t bootloader_ppusatdConfigstate = IDLE; +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + +// ----------------------------------------------------------------------------- +// Enums + +typedef enum { + RESET, INITIALIZED, DEINITIALIZED +} initState_t; + +static initState_t bootloader_InitState = RESET; + +// ----------------------------------------------------------------------------- +// Test helpers + +#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) +extern bool enabled; +extern void enterUnprivilegedMode(bool); +extern void exitUnprivilegedMode(void); +#endif // BOOTLOADER_TEST_UNPRIVILEGED_ACCESS + +// ----------------------------------------------------------------------------- +// Functions + +void bootloader_getInfo(BootloaderInformation_t *info) +{ +#if defined(BOOTLOADER_HAS_FIRST_STAGE) + if (!bootloader_pointerToFirstStageValid(firstBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable)) { + // No bootloader is present (first stage or main stage invalid) + info->type = NO_BOOTLOADER; + info->capabilities = 0; + } else if ((firstBootloaderTable->header.type == BOOTLOADER_MAGIC_FIRST_STAGE) + && (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN)) { + info->type = SL_BOOTLOADER; + info->version = mainBootloaderTable->header.version; + info->capabilities = mainBootloaderTable->capabilities; + } else { + info->type = NO_BOOTLOADER; + info->capabilities = 0; + } +#else + if (!bootloader_pointerValid(mainBootloaderTable)) { + // No bootloader is present (first stage or main stage invalid) + info->type = NO_BOOTLOADER; + info->capabilities = 0; + } else if (mainBootloaderTable->header.type == BOOTLOADER_MAGIC_MAIN) { + info->type = SL_BOOTLOADER; + info->version = mainBootloaderTable->header.version; + info->capabilities = mainBootloaderTable->capabilities; + } else { + info->type = NO_BOOTLOADER; + info->capabilities = 0; + } +#endif +} + +int32_t bootloader_init(void) +{ + int32_t retVal; + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + + if (bootloader_InitState == RESET || bootloader_InitState == DEINITIALIZED) { +#if defined(SL_TRUSTZONE_SECURE) + if (bootloader_InitState == RESET) { + // Enable SMU bus clock at the start-up of the TZ secure application + // to make it possible to configure the SMU peripheral. Since the CMU address + // is known. Otherwise, delegate the SMU bus clock enablement to the NS application. +#if defined(_CMU_CLKEN1_SMU_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; +#endif // _CMU_CLKEN1_SMU_MASK + } +#endif // SL_TRUSTZONE_SECURE + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + SMU->IF_CLR = SMU_IEN_PPUSEC; + NVIC_EnableIRQ(SMU_SECURE_IRQn); + SMU->IEN_SET = SMU_IEN_PPUSEC; +#endif + retVal = mainBootloaderTable->init(); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif + + if (retVal == BOOTLOADER_OK) { + bootloader_InitState = INITIALIZED; + } + } else { + retVal = BOOTLOADER_OK; + } + return retVal; +} + +int32_t bootloader_deinit(void) +{ + int32_t retVal; + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + if (mainBootloaderTable->header.type != BOOTLOADER_MAGIC_MAIN) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + + if (bootloader_InitState == INITIALIZED) { +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) + SMU->IF_CLR = SMU_IEN_PPUSEC; + SMU->IEN_CLR = SMU_IEN_PPUSEC; + NVIC_ClearPendingIRQ(SMU_SECURE_IRQn); + NVIC_DisableIRQ(SMU_SECURE_IRQn); +#endif + + retVal = mainBootloaderTable->deinit(); + if (retVal == BOOTLOADER_OK) { + bootloader_InitState = DEINITIALIZED; + } +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + } else { + retVal = BOOTLOADER_OK; + } + return retVal; +} + +BootloaderResetCause_t bootloader_getResetReason(void) +{ + volatile BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); + return *resetCause; +} + +void bootloader_rebootAndInstall(void) +{ + // Set reset reason to bootloader entry + BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); + resetCause->reason = BOOTLOADER_RESET_REASON_BOOTLOAD; + resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID; +#if defined(RMU_PRESENT) + // Clear resetcause + RMU->CMD = RMU_CMD_RCCLR; + // Trigger a software system reset + RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_SYSRMODE_MASK) | RMU_CTRL_SYSRMODE_FULL; +#endif + NVIC_SystemReset(); +} + +int32_t bootloader_initParser(BootloaderParserContext_t *context, + size_t contextSize) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_PARSE_FAILED; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->initParser(context, contextSize); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_parseBuffer(BootloaderParserContext_t *context, + BootloaderParserCallbacks_t *callbacks, + uint8_t data[], + size_t numBytes) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_PARSE_FAILED; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->parseBuffer(context, callbacks, data, numBytes); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context, + uint8_t data[], + size_t numBytes, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_PARSE_FAILED; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) + >> BOOTLOADER_VERSION_MAJOR_SHIFT); + uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) + >> BOOTLOADER_VERSION_MINOR_SHIFT); + + if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { + return BOOTLOADER_ERROR_PARSE_FAILED; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->parseImageInfo(context, data, numBytes, appInfo, bootloaderVersion); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +uint32_t bootloader_parserContextSize(void) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return 0UL; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) + >> BOOTLOADER_VERSION_MAJOR_SHIFT); + uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) + >> BOOTLOADER_VERSION_MINOR_SHIFT); + + if (blMajorVersion < 1UL) { + return 384UL; + } + + if (blMajorVersion == 1UL && blMinorVersion < 11UL) { +#if defined(_SILICON_LABS_32B_SERIES_2) + if (blMinorVersion == 10UL) { + return 524UL; + } else { + return 384UL; + } +#else + return 384UL; +#endif + } + + return mainBootloaderTable->parserContextSize(); +} + +bool bootloader_verifyApplication(uint32_t startAddress) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return false; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + bool retVal = mainBootloaderTable->verifyApplication(startAddress); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +bool bootloader_secureBootEnforced(void) +{ + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + if (info.capabilities & BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT) { + return true; + } + return false; +} + +bool bootloader_getUpgradeLocation(uint32_t *location) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return false; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) + >> BOOTLOADER_VERSION_MAJOR_SHIFT); + uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) + >> BOOTLOADER_VERSION_MINOR_SHIFT); + + if (blMajorVersion == 2UL && blMinorVersion >= 1UL) { + *location = mainBootloaderTable->getUpgradeLocation(); + return true; + } + + return false; +} + +#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +uint32_t bootloader_remainingApplicationUpgrades(void) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return 0UL; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) + >> BOOTLOADER_VERSION_MAJOR_SHIFT); + uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) + >> BOOTLOADER_VERSION_MINOR_SHIFT); + + if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { + return 0UL; + } + + return mainBootloaderTable->remainingApplicationUpgrades(); +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) +bool bootloader_getCertificateVersion(uint32_t *version) +{ + // Access word 13 to read sl_app_properties of the bootloader. + ApplicationProperties_t *blProperties = + (ApplicationProperties_t *)(*(uint32_t *)(BTL_MAIN_STAGE_BASE + 52UL)); + + if (!bootloader_pointerValid(blProperties)) { + return false; + } + + // Compatibility check of the application properties struct. + if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MAJOR_MASK) + >> APPLICATION_PROPERTIES_VERSION_MAJOR_SHIFT) < 1UL) { + return false; + } + if (((blProperties->structVersion & APPLICATION_PROPERTIES_VERSION_MINOR_MASK) + >> APPLICATION_PROPERTIES_VERSION_MINOR_SHIFT) < 1UL) { + return false; + } + + if (blProperties->cert == NULL) { + return false; + } + + *version = blProperties->cert->version; + return true; +} +#endif // _SILICON_LABS_32B_SERIES_2 + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) +void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1) +{ + if (!bootloader_pointerValid(mainBootloaderTable)) { + return; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + if (info.capabilities & BOOTLOADER_CAPABILITY_PERIPHERAL_LIST) { + mainBootloaderTable->getPeripheralList(ppusatd0, ppusatd1); + } +} + +void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx) +{ + if (bootloader_ppusatdConfigstate != IDLE) { + // This function is called from a bootloader callback function + bootloader_ppusatdConfigstate = TIERED; + return; + } + uint32_t ppusatd0 = 0u; + uint32_t ppusatd1 = 0u; + + if (ctx == NULL) { + return; + } + + bootloader_ppusatdConfigstate = SAVE; + + // Enter ATOMIC section. The ATOMIC section is exited when + // the restore function is called. +#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) + CORE_ENTER_ATOMIC(); +#endif + + sli_bootloader_preHook(); + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) + // Read the stored PPUSATD state from NVM3 + if (!blPPUSATDnStateCacheSet) { + Ecode_t status; + status = nvm3_initDefault(); + if (status == ECODE_NVM3_OK) { + nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID; + status = nvm3_readData(nvm3_defaultHandle, + object_id, + blPPUSATDnStateCache, + sizeof(blPPUSATDnStateCache)); + if (status == ECODE_NVM3_OK) { + blPPUSATDnStateCacheSet = true; + } + } + } +#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING + + // Store the CLKENn states +#if defined(_CMU_CLKEN0_MASK) + ctx->CLKEN0 = CMU->CLKEN0; + ctx->CLKEN1 = CMU->CLKEN1; +#endif + +#if defined(_CMU_CLKEN1_SMU_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_SMU; +#endif // _CMU_CLKEN1_SMU_MASK + ctx->SMU_STATUS = SMU->STATUS; + + // Unlock SMU before re-configuration + SMU->LOCK = SMU_LOCK_SMULOCKKEY_UNLOCK; + + // Store the PPUSATDn states + ctx->PPUSATD0 = SMU->PPUSATD0; + ctx->PPUSATD1 = SMU->PPUSATD1; + ctx->BMPUSATD0 = SMU->BMPUSATD0; + +#if defined(SMU_NS_CFGNS_BASE) + // Store the PPUPATDn states + ctx->PPUPATD0 = SMU->PPUPATD0; + ctx->PPUPATD1 = SMU->PPUPATD1; + + SMU->PPUPATD0 = SMU_NS_CFGNS->PPUNSPATD0; + SMU->PPUPATD1 = SMU_NS_CFGNS->PPUNSPATD1; +#endif // SMU_NS_CFGNS_BASE + +#if defined(CMU_CLKEN0_LDMA) + CMU->CLKEN0_SET = CMU_CLKEN0_LDMA; +#endif // CMU_CLKEN0_LDMA +#if defined(CRYPTOACC_PRESENT) + CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; +#endif + + // Wait for any active transition of other busmasters to finish + if (SMU->PPUSATD0 & SMU_PPUSATD0_LDMA) { + while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ; + } else { + while (LDMA_NS->STATUS & LDMA_STATUS_ANYBUSY) ; + } +#if defined(CRYPTOACC_PRESENT) + if (SMU->PPUSATD1 & SMU_PPUSATD1_CRYPTOACC) { + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) + while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; + #else + while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; + #endif + } else { + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) + while (CRYPTOACC_NS->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; + #else + while (CRYPTOACC_NS->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; + #endif + } +#endif // CRYPTOACC_PRESENT + + // Configure the peripheral secure access state before calling into the bootloader. +#if !defined(BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK) +#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) + // If we do not know which USART is used by the bootloader, + // and the bootloader is not initialized, + // Configure PPUSATDn bits for all the USART not in use. + preConfigureUsartPPUSATD(); +#else + SMU->PPUSATD0_SET = BOOTLOADER_PPUSATD0_MASK; + SMU->PPUSATD1_SET = BOOTLOADER_PPUSATD1_MASK; +#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION + + SMU->PPUSATD0_SET = SMU_PPUSATD0_CMU; + SMU->PPUSATD0_SET = SMU_PPUSATD0_MSC; + if (bootloader_getAllocatedDMAChannel() != -1 + && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) { + SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMA; + SMU->PPUSATD0_SET = SMU_PPUSATD0_LDMAXBAR; + SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA; + } + + SMU->PPUSATD0_SET = SMU_PPUSATD0_HFRCO0; +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) && !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + SMU->PPUSATD0_SET = SMU_PPUSATD0_GPIO; +#endif + SMU->PPUSATD0_SET = SMU_PPUSATD0_GPCRC; +#if defined(SMU_PPUSATD1_CRYPTOACC) + SMU->PPUSATD1_SET = SMU_PPUSATD1_CRYPTOACC; +#endif // SMU_PPUSATD1_CRYPTOACC +#if defined(SMU_PPUSATD1_SEMAILBOX) + SMU->PPUSATD1_SET = SMU_PPUSATD1_SEMAILBOX; +#endif // SMU_PPUSATD1_SEMAILBOX +#elif defined(SL_TRUSTZONE_SECURE) + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA0; + SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA1; + #else + SMU->BMPUSATD0_SET = SMU_BMPUSATD0_LDMA; + #endif +#endif // BOOTLOADER_DISABLE_MULTI_TIERED_FALLBACK + + bootloader_getPeripheralList(&ppusatd0, &ppusatd1); + SMU->PPUSATD0_SET = ppusatd0; + SMU->PPUSATD1_SET = ppusatd1; + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) + // Update the peripheral secure access state of + // the "unknown" peripheral that triggered a fault earlier + if (blPPUSATDnStateCacheSet == true) { + SMU->PPUSATD0_SET = blPPUSATDnStateCache[0]; + SMU->PPUSATD1_SET = blPPUSATDnStateCache[1]; + } +#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING +#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) + enterUnprivilegedMode(enabled); +#endif +} + +void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx) +{ +#if defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) + exitUnprivilegedMode(); +#endif + + if (bootloader_ppusatdConfigstate != SAVE) { + // This function is called from a bootloader callback function + bootloader_ppusatdConfigstate = SAVE; + return; + } + + if (ctx == NULL) { + return; + } + + // Wait for any active transition of other busmasters to finish + if (bootloader_getAllocatedDMAChannel() != -1 + && bootloader_getAllocatedDMAChannel() != BOOTLOADER_ERROR_INIT_STORAGE) { +#if defined(CMU_CLKEN0_LDMA) + CMU_S->CLKEN0_SET = CMU_CLKEN0_LDMA; +#endif // CMU_CLKEN0_LDMA + while (LDMA_S->STATUS & LDMA_STATUS_ANYBUSY) ; + } +#if defined(CRYPTOACC_PRESENT) + CMU_S->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) + while (CRYPTOACC_S->DMACTRL_STATUS & (CRYPTOACC_DMACTRL_STATUS_FETCH_BUSY | CRYPTOACC_DMACTRL_STATUS_PUSH_BUSY | CRYPTOACC_DMACTRL_STATUS_SOFT_RST_BUSY)) ; + #else + while (CRYPTOACC_S->STATUS & (CRYPTOACC_STATUS_FETCHERBSY | CRYPTOACC_STATUS_PUSHERBSY | CRYPTOACC_STATUS_SOFTRSTBSY)) ; + #endif +#endif // CRYPTOACC_PRESENT + + SMU->PPUSATD0 = ctx->PPUSATD0; + SMU->PPUSATD1 = ctx->PPUSATD1; + SMU->BMPUSATD0 = ctx->BMPUSATD0; +#if defined(SMU_NS_CFGNS_BASE) + SMU->PPUPATD0 = ctx->PPUPATD0; + SMU->PPUPATD1 = ctx->PPUPATD1; +#endif // SMU_NS_CFGNS_BASE + if (ctx->SMU_STATUS & SMU_STATUS_SMULOCK) { + SMU->LOCK = 0u; + } + +#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) + storeUsartInUse(); +#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION + + // Restore the CLKENn states +#if defined(_CMU_CLKEN0_MASK) + CMU->CLKEN0 = ctx->CLKEN0; + CMU->CLKEN1 = ctx->CLKEN1; +#endif + + sli_bootloader_postHook(); + +#if !defined(BOOTLOADER_TEST_UNPRIVILEGED_ACCESS) + CORE_EXIT_ATOMIC(); +#endif + + // Update the state after the critical section has been + // exited to ensure that the SMU interrupt gets fired, + // before the state change happens. + bootloader_ppusatdConfigstate = IDLE; +} + +__attribute__ ((weak)) void sli_bootloader_preHook(void) +{ +} + +__attribute__ ((weak)) void sli_bootloader_postHook(void) +{ +} + +#if defined(BOOTLOADER_ENABLE_USART_AUTO_DETECTION) +static void preConfigureUsartPPUSATD(void) +{ + if (usartNumberSpi != -1) { + SMU->PPUSATD0_SET = (SMU_PPUSATD0_USART0 << usartNumberSpi); + return; + } + + if (bootloader_InitState != RESET) { + // The USART taken by the bootloader + // is still unknown, do nothing. + return; + } +#if defined(USART0_BASE) +#if defined(CMU_CLKEN0_USART0) + CMU->CLKEN0_SET = CMU_CLKEN0_USART0; +#endif // CMU_CLKEN0_USART0 +#if defined(SL_TRUSTZONE_SECURE) + if (USART0_NS->EN == _USART_EN_RESETVALUE) { +#else + if (USART0->EN == _USART_EN_RESETVALUE) { +#endif // SL_TRUSTZONE_SECURE + SMU->PPUSATD0_SET = SMU_PPUSATD0_USART0; + } +#endif // USART0_BASE + +#if defined(USART1_BASE) +#if defined(CMU_CLKEN0_USART1) + CMU->CLKEN0_SET = CMU_CLKEN0_USART1; +#endif // CMU_CLKEN0_USART1 +#if defined(SL_TRUSTZONE_SECURE) + if (USART1_NS->EN == _USART_EN_RESETVALUE) { +#else + if (USART1->EN == _USART_EN_RESETVALUE) { +#endif // SL_TRUSTZONE_SECURE + SMU->PPUSATD0_SET = SMU_PPUSATD0_USART1; + } +#endif // USART1_BASE + +#if defined(USART2_BASE) +#if defined(CMU_CLKEN0_USART2) + CMU->CLKEN0_SET = CMU_CLKEN0_USART2; +#endif // CMU_CLKEN0_USART2 +#if defined(SL_TRUSTZONE_SECURE) + if (USART2_NS->EN == _USART_EN_RESETVALUE) { +#else + if (USART2->EN == _USART_EN_RESETVALUE) { +#endif // SL_TRUSTZONE_SECURE + SMU->PPUSATD0_SET = SMU_PPUSATD0_USART2; + } +#endif // USART2_BASE +} + +static void storeUsartInUse(void) +{ + if ((usartNumberSpi != -1) || (bootloader_InitState != RESET)) { + return; + } +#if defined(USART0_BASE) +#if defined(SL_TRUSTZONE_SECURE) + if (USART0_NS->EN & USART_EN_EN) { +#else + if (USART0->EN & USART_EN_EN) { +#endif // SL_TRUSTZONE_SECURE + usartNumberSpi = 0; + } +#endif // USART0_BASE + +#if defined(USART1_BASE) +#if defined(SL_TRUSTZONE_SECURE) + if (USART1_NS->EN & USART_EN_EN) { +#else + if (USART1->EN & USART_EN_EN) { +#endif // SL_TRUSTZONE_SECURE + usartNumberSpi = 1; + } +#endif // USART1_BASE + +#if defined(USART2_BASE) +#if defined(SL_TRUSTZONE_SECURE) + if (USART2_NS->EN & USART_EN_EN) { +#else + if (USART2->EN & USART_EN_EN) { +#endif // SL_TRUSTZONE_SECURE + usartNumberSpi = 2; + } +#endif // USART2_BASE +} +#endif // BOOTLOADER_ENABLE_USART_AUTO_DETECTION + +#if defined(BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING) +void SMU_SECURE_IRQHandler(void) +{ +#if !defined(BOOTLOADER_TEST_FAULT_HANDLING) + if (bootloader_ppusatdConfigstate == IDLE) { + // If none of the bootloader interface operations are active, + // the fault is not caused by the bootloader. Just park in the while loop. + while (true) ; + } +#endif // BOOTLOADER_TEST_FAULT_HANDLING + + Ecode_t status; + uint32_t PPUSATDn_state[2] = { 0 }; + nvm3_ObjectKey_t object_id = BL_NVM3_RESERVED_ID; + + // First read the pre-existing configuration + status = nvm3_readData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); + if (status == ECODE_NVM3_OK) { + if (SMU->PPUFS > 31) { + PPUSATDn_state[1] |= 1 << (SMU->PPUFS - 32); + } else { + PPUSATDn_state[0] |= 1 << SMU->PPUFS; + } + // Nothing to do to recover if this fails, just continue and perform a reset. + (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); + } else if (status == ECODE_NVM3_ERR_KEY_NOT_FOUND) { + if (SMU->PPUFS > 31) { + PPUSATDn_state[1] = 1 << (SMU->PPUFS - 32); + } else { + PPUSATDn_state[0] = 1 << SMU->PPUFS; + } + (void)nvm3_writeData(nvm3_defaultHandle, object_id, PPUSATDn_state, sizeof(PPUSATDn_state)); + } else { + // Do nothing. If NVM3 read fails for an unknown reason, + // perform a reset to recover from the failure state. + } + + BootloaderResetCause_t* resetCause = (BootloaderResetCause_t*) (SRAM_BASE); + resetCause->reason = BOOTLOADER_RESET_REASON_FAULT; + resetCause->signature = BOOTLOADER_RESET_SIGNATURE_VALID; + NVIC_SystemReset(); +} +#endif // BOOTLOADER_ENABLE_NVM3_FAULT_HANDLING + +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.h index 6fa7666..eac0b68 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface.h @@ -1,729 +1,729 @@ -/***************************************************************************//** - * @file - * @brief Application interface to the bootloader. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_INTERFACE_H -#define BTL_INTERFACE_H - -#include - -#include "btl_errorcode.h" -#include "btl_reset_info.h" -#include "application_properties.h" - -// Include component-specific interfaces -#include "btl_interface_parser.h" -#include "btl_interface_storage.h" - -// Get flash page size -#include "em_device.h" - -#if defined(SL_TRUSTZONE_NONSECURE) -#include "sli_tz_ns_interface.h" -#endif - -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif -/***************************************************************************//** - * @addtogroup Interface Application Interface - * @brief Application interface to the bootloader - * @details - * The application interface consists of functions that can be included - * in the customer application that and will communicate with the - * bootloader through the @ref MainBootloaderTable_t. This table - * contains function pointers to the bootloader. The 10th word of the - * bootloader contains a pointer to this struct, allowing any application to - * easily locate it. - * To access the bootloader table, use wrapper functions. Avoid - * accessing the bootloader table directly. - * - * @{ - * @addtogroup CommonInterface Common Application Interface - * @brief Generic application interface available on all versions of the - * bootloader, regardless of the available components. - * @note These Bootloader APIs are not reentrant and should be wrapped in critical section - * where needed. - * @details - * @{ - ******************************************************************************/ - -/// Bare boot table. Can be mapped on top of vector table to access contents. -typedef struct { - /// Pointer to top of stack - uint32_t *stackTop; - /// Pointer to reset vector - void (*resetVector)(void); - /// Reserved pointers to fault handlers - uint32_t reserved0[5]; - /// Reserved pointers to RESERVED fields - uint32_t reserved1[3]; - /// Pointer to bootloader table - void *table; - /// Reserved pointers to SVC and DebugMon interrupts - uint32_t reserved2[2]; - /// Pointer to application signature - void *signature; -} BareBootTable_t; - -// -------------------------------- -// Bootloader defines - -/// Bootloader version major version shift value -#define BOOTLOADER_VERSION_MAJOR_SHIFT (24U) -/// Bootloader version minor version shift value -#define BOOTLOADER_VERSION_MINOR_SHIFT (16U) -/// Bootloader version major version mask -#define BOOTLOADER_VERSION_MAJOR_MASK (0xFF000000U) -/// Bootloader version minor version mask -#define BOOTLOADER_VERSION_MINOR_MASK (0x00FF0000U) - -/// Bootloader interface APIs are trust zone aware -#if defined(BOOTLOADER_SECURE) -#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE -#elif defined(_SILICON_LABS_32B_SERIES_2) && !defined(BOOTLOADER_APPLOADER) -// The bootloader with AppLoader as the communication interface will not -// re-configure the SMU since it is using the NS peripherals by default. -#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE -#endif - -// -------------------------------- -// Bootloader information typedefs - -/// Type of bootloader -typedef enum { - /// No bootloader present. - NO_BOOTLOADER = 0, - /// Bootloader is a Silicon Labs bootloader. - SL_BOOTLOADER = 1 -} BootloaderType_t; - -/// Information about the current bootloader -typedef struct { - /// The type of bootloader. - BootloaderType_t type; - /// Version number of the bootloader - uint32_t version; - /// Capability mask for the bootloader. - uint32_t capabilities; -} BootloaderInformation_t; - -/// Common header for bootloader tables -typedef struct { - /// Type of image - uint32_t type; - /// Version number of the bootloader/application table - uint32_t layout; - /// Version number of the image - uint32_t version; -} BootloaderHeader_t; - -/// Address table for the First Stage Bootloader -typedef struct { - /// Header of the First Stage Bootloader table - BootloaderHeader_t header; - /// Start address of the Main Bootloader - BareBootTable_t *mainBootloader; - /// Location of the Main Bootloader upgrade image - BareBootTable_t *upgradeLocation; -} FirstBootloaderTable_t; - -/// Address table for the Main Bootloader -typedef struct { - /// Header of the Main Bootloader table - BootloaderHeader_t header; - /// Size of the Main Bootloader - uint32_t size; - /// Start address of the application - BareBootTable_t *startOfAppSpace; - /// End address of the allocated application space - uint32_t *endOfAppSpace; - /// Capabilities of the bootloader - uint32_t capabilities; - // ------------------------------ - /// Initialize bootloader for use from application - int32_t (*init)(void); - /// Deinitialize bootloader after use from application - int32_t (*deinit)(void); - // ------------------------------ - /// Verify application - bool (*verifyApplication)(uint32_t startAddress); - // ------------------------------ - /// Initialize parser - int32_t (*initParser)(BootloaderParserContext_t *context, size_t contextSize); - /// Parse a buffer - int32_t (*parseBuffer)(BootloaderParserContext_t *context, - const BootloaderParserCallbacks_t *callbacks, - uint8_t data[], - size_t numBytes); - // ------------------------------ - /// Function table for storage component - const BootloaderStorageFunctions_t *storage; - // ------------------------------ - /// Parse a buffer and get application and bootloader upgrade metadata from the buffer. - int32_t (*parseImageInfo)(BootloaderParserContext_t *context, - uint8_t data[], - size_t numBytes, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion); - // ------------------------------ - /// Size of context buffer used by bootloader image parser to store parser state - uint32_t (*parserContextSize)(void); - // ------------------------------ - /// Remaining number of application upgrades - uint32_t (*remainingApplicationUpgrades)(void); - // ------------------------------ - /// Get the list of the peripheral that is used by the bootloader - void (*getPeripheralList)(uint32_t *ppusatd0, uint32_t *ppusatd1); - // ------------------------------ - /// Get base address of bootloader upgrade image - uint32_t (*getUpgradeLocation)(void); -} MainBootloaderTable_t; - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) -/// Struct that represents the state of the PPUSATDn, PPUPATDn and CLKENn registers -typedef struct { - uint32_t PPUSATD0; - uint32_t PPUSATD1; - uint32_t BMPUSATD0; -#if defined(SMU_NS_CFGNS_BASE) - uint32_t PPUPATD0; - uint32_t PPUPATD1; -#endif -#if defined(_CMU_CLKEN0_MASK) - uint32_t CLKEN0; - uint32_t CLKEN1; -#endif - uint32_t SMU_STATUS; -} Bootloader_PPUSATDnCLKENnState_t; - -/// Struct containing function arguments -typedef struct Bootloader_inOutVec { - void *base; /// the start address of the memory buffer - size_t len; /// the size in bytes -} Bootloader_inOutVec_t; - -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - -// -------------------------------- -// Bootloader capabilities - -/// Bootloader enforces signed application upgrade images -#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_SIGNATURE (1 << 0) -/// Bootloader enforces encrypted application upgrade images -#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_ENCRYPTION (1 << 1) -/// @brief Bootloader enforces signature verification of the application image -/// before every boot -#define BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT (1 << 2) - -/// Bootloader has the capability of being upgraded -#define BOOTLOADER_CAPABILITY_BOOTLOADER_UPGRADE (1 << 4) - -/// Bootloader has the capability of parsing GBL files -#define BOOTLOADER_CAPABILITY_GBL (1 << 5) -/// Bootloader has the capability of parsing signed GBL files -#define BOOTLOADER_CAPABILITY_GBL_SIGNATURE (1 << 6) -/// Bootloader has the capability of parsing encrypted GBL files -#define BOOTLOADER_CAPABILITY_GBL_ENCRYPTION (1 << 7) -/// @brief Bootloader enforces signature verification of the application image -/// before every boot using certificate -#define BOOTLOADER_CAPABILITY_ENFORCE_CERTIFICATE_SECURE_BOOT (1 << 8) -/// Bootloader has the capability of application rollback protection -#define BOOTLOADER_CAPABILITY_ROLLBACK_PROTECTION (1 << 9) -/// Bootloader has the capability to check the peripherals in use -#define BOOTLOADER_CAPABILITY_PERIPHERAL_LIST (1 << 10) - -/// @brief Bootloader has the capability of storing data in an internal or -/// external storage medium -#define BOOTLOADER_CAPABILITY_STORAGE (1 << 16) -/// @brief Bootloader has the capability of communicating with host processors -/// using a communication interface -#define BOOTLOADER_CAPABILITY_COMMUNICATION (1 << 20) - -// -------------------------------- -// Magic constants for bootloader tables - -/// Magic word indicating first stage bootloader table -#define BOOTLOADER_MAGIC_FIRST_STAGE (0xB00710ADUL) -/// Magic word indicating main bootloader table -#define BOOTLOADER_MAGIC_MAIN (0x5ECDB007UL) - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -#define BOOTLOADER_HEADER_VERSION_FIRST_STAGE (0x00000001UL) -#define BOOTLOADER_HEADER_VERSION_MAIN (0x00000002UL) -/// @endcond - -// -------------------------------- -// Bootloader table access - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) || defined(MAIN_BOOTLOADER_TEST) -// No first stage on devices with SE -#define BTL_FIRST_STAGE_SIZE (0UL) -#else -// First stage takes a single flash page -#define BTL_FIRST_STAGE_SIZE (FLASH_PAGE_SIZE) -#define BOOTLOADER_HAS_FIRST_STAGE -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -// No writeable bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE 0x00000000UL -#define BTL_APPLICATION_BASE 0x00004000UL -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) -// Dedicated bootloader area of 38k -// Place the bootloader in the dedicated bootloader area of the -// information block -#define BTL_FIRST_STAGE_BASE 0x0FE10000UL -#define BTL_APPLICATION_BASE 0x00000000UL -#define BTL_MAIN_STAGE_MAX_SIZE (0x00009800UL - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) -#define BTL_FIRST_STAGE_BASE 0x0FE10000UL -#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) -#define BTL_APPLICATION_BASE 0x00004800UL -#define BTL_MAIN_STAGE_MAX_SIZE BTL_APPLICATION_BASE -#else -// Dedicated bootloader area of 16k -// Place the bootloader in the dedicated bootloader area of the -// information block -#define BTL_APPLICATION_BASE 0x00000000UL -#define BTL_MAIN_STAGE_MAX_SIZE (0x00004000UL - BTL_FIRST_STAGE_SIZE) -#endif -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#define BTL_FIRST_STAGE_BASE 0x0FE10000UL -#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) -#define BTL_APPLICATION_BASE 0x00004800UL -#define BTL_MAIN_STAGE_MAX_SIZE BTL_APPLICATION_BASE -#else -// Dedicated bootloader area of 18k -// Place the bootloader in the dedicated bootloader area of the -// information block -#define BTL_APPLICATION_BASE 0x00000000UL -#define BTL_MAIN_STAGE_MAX_SIZE (0x00004800UL - BTL_FIRST_STAGE_SIZE) -#endif -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -// Dedicated bootloader area of 32k -// Place the bootloader in the dedicated bootloader area of the -// information block -#define BTL_FIRST_STAGE_BASE 0x0FE10000UL -#define BTL_APPLICATION_BASE 0x00000000UL -#define BTL_MAIN_STAGE_MAX_SIZE (0x00008000UL - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -// Dedicated bootloader area of 18k -// Place the bootloader in the dedicated bootloader area of the -// information block -#define BTL_FIRST_STAGE_BASE 0x0FE10000UL -#define BTL_APPLICATION_BASE 0x00000000UL -#define BTL_MAIN_STAGE_MAX_SIZE (0x00004800UL - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#elif defined(BOOTLOADER_SECURE) && defined(BOOTLOADER_SUPPORT_COMMUNICATION) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00004000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - BTL_FIRST_STAGE_SIZE) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#elif defined(BOOTLOADER_CUSTOM_SIZE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00004000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE)) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE)) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_220) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE)) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE)) -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_235) -// No bootloader area: Place the bootloader in main flash -#define BTL_FIRST_STAGE_BASE FLASH_BASE -#if defined(BOOTLOADER_APPLOADER) -#if defined(BOOTLOADER_SECURE) -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) -#endif // BOOTLOADER_SECURE -#else -#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) -#endif // BOOTLOADER_APPLOADER -#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ - - (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE)) -#else -#error "This part is not supported in this bootloader version." -#endif - -#if defined(MAIN_BOOTLOADER_TEST) || defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) -#define BTL_MAIN_STAGE_BASE (FLASH_BASE) -#else -#define BTL_MAIN_STAGE_BASE (BTL_FIRST_STAGE_BASE \ - + BTL_FIRST_STAGE_SIZE) -#endif - -#if defined(BOOTLOADER_HAS_FIRST_STAGE) -#define BTL_FIRST_BOOTLOADER_TABLE_BASE (BTL_FIRST_STAGE_BASE \ - + offsetof(BareBootTable_t, table)) -#endif -#define BTL_MAIN_BOOTLOADER_TABLE_BASE (BTL_MAIN_STAGE_BASE \ - + offsetof(BareBootTable_t, table)) - -/// @endcond // DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(MAIN_BOOTLOADER_TEST) -#if defined(BOOTLOADER_HAS_FIRST_STAGE) -extern FirstBootloaderTable_t *firstBootloaderTable; -#endif -extern MainBootloaderTable_t *mainBootloaderTable; -#else -#if defined(BOOTLOADER_HAS_FIRST_STAGE) -/// Pointer to first stage bootloader table -#define firstBootloaderTable (*(FirstBootloaderTable_t **) \ - (BTL_FIRST_BOOTLOADER_TABLE_BASE)) -#endif // BOOTLOADER_HAS_FIRST_STAGE -/// Pointer to main bootloader table -#define mainBootloaderTable (*(MainBootloaderTable_t **) \ - (BTL_MAIN_BOOTLOADER_TABLE_BASE)) -#endif // MAIN_BOOTLOADER_TEST -// -------------------------------- -// Functions - -/***************************************************************************//** - * Get information about the bootloader on this device. - * - * The returned information is fetched from the main bootloader - * information table. - * - * @param[out] info Pointer to the bootloader information struct. - ******************************************************************************/ -void bootloader_getInfo(BootloaderInformation_t *info); - -/***************************************************************************//** - * Initialize components of the bootloader - * so the app can use the interface. This typically includes initializing - * serial peripherals for communication with external SPI flashes, and so on. - * - * @return Error code. @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_INIT_BASE range. - ******************************************************************************/ -int32_t bootloader_init(void); - -/***************************************************************************//** - * De-initialize components of the bootloader that were previously initialized. - * This typically includes powering down external SPI flashes and - * de-initializing the serial peripheral used for communication with the - * external flash. - * - * @return Error code. @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_INIT_BASE range. - ******************************************************************************/ -int32_t bootloader_deinit(void); - -/***************************************************************************//** - * Reboot into the bootloader to perform an install. - * - * If there is a storage component and a slot is marked for bootload, install - * the image in that slot after verifying it. - * - * If a communication component is present, open the communication channel and - * receive an image to be installed. - ******************************************************************************/ -void bootloader_rebootAndInstall(void); - -/***************************************************************************//** - * Verify the application image stored in the Flash memory starting at - * the address startAddress. - * - * If the secure boot is enforced, the function will only return true if the - * cryptographic signature of the application is valid. Otherwise, the - * application is verified according to the signature type defined in the - * ApplicationProperties_t structure embedded in the application. Silicon Labs - * wireless stacks include a declaration of this structure. However, - * applications not using a full wireless stack may need to instantiate - * the structure. - * - * Examples of results when the secure boot is not enforced: - * - App has no signature: Valid if initial stack pointer and program counter - * have reasonable values. - * - App has CRC checksum: Valid if checksum is valid. - * - App has ECDSA signature: Valid if ECDSA signature is valid. - * - * When secure boot is enforced, only ECDSA signed applications with - * a valid signature are considered valid. - * - * - * @param[in] startAddress Starting address of the application. - * - * @return True if the application is valid, else false. - ******************************************************************************/ -bool bootloader_verifyApplication(uint32_t startAddress); - -/***************************************************************************//** - * Check whether signature verification on the application image in internal flash - * is enforced before every boot. - * - * @return True if signature verification is enforced, else false. - ******************************************************************************/ -bool bootloader_secureBootEnforced(void); - -/***************************************************************************//** - * Get base address of the bootloader upgrade image. - * - * @param[out] location the base address of bootloader upgrade image. - * - * @return Returns true if the location was found. - ******************************************************************************/ -bool bootloader_getUpgradeLocation(uint32_t *location); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) -/***************************************************************************//** - * Get the list of the peripheral that is used by the bootloader. - * - * @param[out] ppusatd0 Word containing all the peripherals used by the - * bootloader. Each bit represents a peripheral, - * which is ordered after the PPUSATD0 register bit - * fields. - * - * @param[out] ppusatd1 Word containing all the peripherals used by the - * bootloader. Each bit represents a peripheral, - * which is ordered after the PPUSATD1 register bit - * fields. - ******************************************************************************/ -void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1); - -/***************************************************************************//** - * Save PPUSATDn state in RAM. - * Configure the peripheral attributes before calling into the bootloader. - * - * @note Enters ATOMIC section. - * - * @param[out] ctx Context struct to save register state into - * - * @return True if a valid certificate version is found. - ******************************************************************************/ -void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx); - -/***************************************************************************//** - * Restore PPUSATDn state from RAM. - * Store the USART used by the bootloader if this is unknown. - * - * @note Exits ATOMIC section. - * - * @param[in] ctx Context struct to restore register state from - * - * @return True if a valid certificate version is found. - ******************************************************************************/ -void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx); - -/***************************************************************************//** - * Called before the bootloader is initialized. - * - * This function implementation does not perform anything, but it is __weak - * so that it can be implemented by another application. - ******************************************************************************/ -void sli_bootloader_preHook(void); - -/***************************************************************************//** - * Called after the bootloader is de-initialized. - * - * This function implementation does not perform anything, but it is __weak - * so that it can be implemented by another application. - ******************************************************************************/ -void sli_bootloader_postHook(void); -#endif - -#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/***************************************************************************//** - * Count the total remaining number of application upgrades. - * - * @return remaining number of application upgrades. - ******************************************************************************/ -uint32_t bootloader_remainingApplicationUpgrades(void); -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * Get bootloader certificate version. - * - * @param[out] version Bootloader certificate version - * - * @return True if a valid certificate version is found. - ******************************************************************************/ -bool bootloader_getCertificateVersion(uint32_t *version); -#endif // _SILICON_LABS_32B_SERIES_2 - -/***************************************************************************//** - * Get reset cause of the bootloader. - * - * @return Reset cause of the bootloader. - ******************************************************************************/ -BootloaderResetCause_t bootloader_getResetReason(void); - -#if defined(BOOTLOADER_HAS_FIRST_STAGE) -/***************************************************************************//** - * Check if a pointer is valid and if it points to the bootloader first stage. - * - * This function checks pointers to bootloader - * jump tables. - * - * - * @param[in] ptr The pointer to check - * - * @return True if the pointer points to the bootloader first stage, - * false if not. - ******************************************************************************/ -__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr); -__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr) -{ -#if defined(MAIN_BOOTLOADER_TEST) - // In main bootloader tests, no first stage is present - (void) ptr; - return false; -#elif BTL_FIRST_STAGE_BASE > 0U - if (((size_t)(ptr) >= BTL_FIRST_STAGE_BASE) - && ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE))) { - return true; - } else { - return false; - } -#else - // First stage starts at address 0, don't need to check lower bound - if ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE)) { - return true; - } else { - return false; - } -#endif -} -#endif // BOOTLOADER_HAS_FIRST_STAGE - -/***************************************************************************//** - * Check if a pointer is valid and if it points to the bootloader main stage. - * - * This function checks pointers to bootloader - * jump tables. - * - * - * @param[in] ptr The pointer to check - * - * @return True if the pointer points into the bootloader main stage, - * false if not. - ******************************************************************************/ -__STATIC_INLINE bool bootloader_pointerValid(const void *ptr); -__STATIC_INLINE bool bootloader_pointerValid(const void *ptr) -{ -#if defined(MAIN_BOOTLOADER_TEST) - // In main bootloader tests, all of memory is considered part of the bootloader - (void) ptr; - return true; -#elif BTL_MAIN_STAGE_BASE > 0U - if (((size_t)ptr >= BTL_MAIN_STAGE_BASE) - && ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE))) { - return true; - } else { - return false; - } -#else - if ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE)) { - return true; - } else { - return false; - } -#endif -} - -/** @} (end addtogroup CommonInterface) */ -/** @} (end addtogroup Interface) */ -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - -#endif // BTL_INTERFACE_H +/***************************************************************************//** + * @file + * @brief Application interface to the bootloader. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_INTERFACE_H +#define BTL_INTERFACE_H + +#include + +#include "btl_errorcode.h" +#include "btl_reset_info.h" +#include "application_properties.h" + +// Include component-specific interfaces +#include "btl_interface_parser.h" +#include "btl_interface_storage.h" + +// Get flash page size +#include "em_device.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_ns_interface.h" +#endif + +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif +/***************************************************************************//** + * @addtogroup Interface Application Interface + * @brief Application interface to the bootloader + * @details + * The application interface consists of functions that can be included + * in the customer application that and will communicate with the + * bootloader through the @ref MainBootloaderTable_t. This table + * contains function pointers to the bootloader. The 10th word of the + * bootloader contains a pointer to this struct, allowing any application to + * easily locate it. + * To access the bootloader table, use wrapper functions. Avoid + * accessing the bootloader table directly. + * + * @{ + * @addtogroup CommonInterface Common Application Interface + * @brief Generic application interface available on all versions of the + * bootloader, regardless of the available components. + * @note These Bootloader APIs are not reentrant and should be wrapped in critical section + * where needed. + * @details + * @{ + ******************************************************************************/ + +/// Bare boot table. Can be mapped on top of vector table to access contents. +typedef struct { + /// Pointer to top of stack + uint32_t *stackTop; + /// Pointer to reset vector + void (*resetVector)(void); + /// Reserved pointers to fault handlers + uint32_t reserved0[5]; + /// Reserved pointers to RESERVED fields + uint32_t reserved1[3]; + /// Pointer to bootloader table + void *table; + /// Reserved pointers to SVC and DebugMon interrupts + uint32_t reserved2[2]; + /// Pointer to application signature + void *signature; +} BareBootTable_t; + +// -------------------------------- +// Bootloader defines + +/// Bootloader version major version shift value +#define BOOTLOADER_VERSION_MAJOR_SHIFT (24U) +/// Bootloader version minor version shift value +#define BOOTLOADER_VERSION_MINOR_SHIFT (16U) +/// Bootloader version major version mask +#define BOOTLOADER_VERSION_MAJOR_MASK (0xFF000000U) +/// Bootloader version minor version mask +#define BOOTLOADER_VERSION_MINOR_MASK (0x00FF0000U) + +/// Bootloader interface APIs are trust zone aware +#if defined(BOOTLOADER_SECURE) +#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE +#elif defined(_SILICON_LABS_32B_SERIES_2) && !defined(BOOTLOADER_APPLOADER) +// The bootloader with AppLoader as the communication interface will not +// re-configure the SMU since it is using the NS peripherals by default. +#define BOOTLOADER_INTERFACE_TRUSTZONE_AWARE +#endif + +// -------------------------------- +// Bootloader information typedefs + +/// Type of bootloader +typedef enum { + /// No bootloader present. + NO_BOOTLOADER = 0, + /// Bootloader is a Silicon Labs bootloader. + SL_BOOTLOADER = 1 +} BootloaderType_t; + +/// Information about the current bootloader +typedef struct { + /// The type of bootloader. + BootloaderType_t type; + /// Version number of the bootloader + uint32_t version; + /// Capability mask for the bootloader. + uint32_t capabilities; +} BootloaderInformation_t; + +/// Common header for bootloader tables +typedef struct { + /// Type of image + uint32_t type; + /// Version number of the bootloader/application table + uint32_t layout; + /// Version number of the image + uint32_t version; +} BootloaderHeader_t; + +/// Address table for the First Stage Bootloader +typedef struct { + /// Header of the First Stage Bootloader table + BootloaderHeader_t header; + /// Start address of the Main Bootloader + BareBootTable_t *mainBootloader; + /// Location of the Main Bootloader upgrade image + BareBootTable_t *upgradeLocation; +} FirstBootloaderTable_t; + +/// Address table for the Main Bootloader +typedef struct { + /// Header of the Main Bootloader table + BootloaderHeader_t header; + /// Size of the Main Bootloader + uint32_t size; + /// Start address of the application + BareBootTable_t *startOfAppSpace; + /// End address of the allocated application space + uint32_t *endOfAppSpace; + /// Capabilities of the bootloader + uint32_t capabilities; + // ------------------------------ + /// Initialize bootloader for use from application + int32_t (*init)(void); + /// Deinitialize bootloader after use from application + int32_t (*deinit)(void); + // ------------------------------ + /// Verify application + bool (*verifyApplication)(uint32_t startAddress); + // ------------------------------ + /// Initialize parser + int32_t (*initParser)(BootloaderParserContext_t *context, size_t contextSize); + /// Parse a buffer + int32_t (*parseBuffer)(BootloaderParserContext_t *context, + const BootloaderParserCallbacks_t *callbacks, + uint8_t data[], + size_t numBytes); + // ------------------------------ + /// Function table for storage component + const BootloaderStorageFunctions_t *storage; + // ------------------------------ + /// Parse a buffer and get application and bootloader upgrade metadata from the buffer. + int32_t (*parseImageInfo)(BootloaderParserContext_t *context, + uint8_t data[], + size_t numBytes, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion); + // ------------------------------ + /// Size of context buffer used by bootloader image parser to store parser state + uint32_t (*parserContextSize)(void); + // ------------------------------ + /// Remaining number of application upgrades + uint32_t (*remainingApplicationUpgrades)(void); + // ------------------------------ + /// Get the list of the peripheral that is used by the bootloader + void (*getPeripheralList)(uint32_t *ppusatd0, uint32_t *ppusatd1); + // ------------------------------ + /// Get base address of bootloader upgrade image + uint32_t (*getUpgradeLocation)(void); +} MainBootloaderTable_t; + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) +/// Struct that represents the state of the PPUSATDn, PPUPATDn and CLKENn registers +typedef struct { + uint32_t PPUSATD0; + uint32_t PPUSATD1; + uint32_t BMPUSATD0; +#if defined(SMU_NS_CFGNS_BASE) + uint32_t PPUPATD0; + uint32_t PPUPATD1; +#endif +#if defined(_CMU_CLKEN0_MASK) + uint32_t CLKEN0; + uint32_t CLKEN1; +#endif + uint32_t SMU_STATUS; +} Bootloader_PPUSATDnCLKENnState_t; + +/// Struct containing function arguments +typedef struct Bootloader_inOutVec { + void *base; /// the start address of the memory buffer + size_t len; /// the size in bytes +} Bootloader_inOutVec_t; + +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + +// -------------------------------- +// Bootloader capabilities + +/// Bootloader enforces signed application upgrade images +#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_SIGNATURE (1 << 0) +/// Bootloader enforces encrypted application upgrade images +#define BOOTLOADER_CAPABILITY_ENFORCE_UPGRADE_ENCRYPTION (1 << 1) +/// @brief Bootloader enforces signature verification of the application image +/// before every boot +#define BOOTLOADER_CAPABILITY_ENFORCE_SECURE_BOOT (1 << 2) + +/// Bootloader has the capability of being upgraded +#define BOOTLOADER_CAPABILITY_BOOTLOADER_UPGRADE (1 << 4) + +/// Bootloader has the capability of parsing GBL files +#define BOOTLOADER_CAPABILITY_GBL (1 << 5) +/// Bootloader has the capability of parsing signed GBL files +#define BOOTLOADER_CAPABILITY_GBL_SIGNATURE (1 << 6) +/// Bootloader has the capability of parsing encrypted GBL files +#define BOOTLOADER_CAPABILITY_GBL_ENCRYPTION (1 << 7) +/// @brief Bootloader enforces signature verification of the application image +/// before every boot using certificate +#define BOOTLOADER_CAPABILITY_ENFORCE_CERTIFICATE_SECURE_BOOT (1 << 8) +/// Bootloader has the capability of application rollback protection +#define BOOTLOADER_CAPABILITY_ROLLBACK_PROTECTION (1 << 9) +/// Bootloader has the capability to check the peripherals in use +#define BOOTLOADER_CAPABILITY_PERIPHERAL_LIST (1 << 10) + +/// @brief Bootloader has the capability of storing data in an internal or +/// external storage medium +#define BOOTLOADER_CAPABILITY_STORAGE (1 << 16) +/// @brief Bootloader has the capability of communicating with host processors +/// using a communication interface +#define BOOTLOADER_CAPABILITY_COMMUNICATION (1 << 20) + +// -------------------------------- +// Magic constants for bootloader tables + +/// Magic word indicating first stage bootloader table +#define BOOTLOADER_MAGIC_FIRST_STAGE (0xB00710ADUL) +/// Magic word indicating main bootloader table +#define BOOTLOADER_MAGIC_MAIN (0x5ECDB007UL) + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define BOOTLOADER_HEADER_VERSION_FIRST_STAGE (0x00000001UL) +#define BOOTLOADER_HEADER_VERSION_MAIN (0x00000002UL) +/// @endcond + +// -------------------------------- +// Bootloader table access + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) || defined(MAIN_BOOTLOADER_TEST) +// No first stage on devices with SE +#define BTL_FIRST_STAGE_SIZE (0UL) +#else +// First stage takes a single flash page +#define BTL_FIRST_STAGE_SIZE (FLASH_PAGE_SIZE) +#define BOOTLOADER_HAS_FIRST_STAGE +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +// No writeable bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE 0x00000000UL +#define BTL_APPLICATION_BASE 0x00004000UL +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +// Dedicated bootloader area of 38k +// Place the bootloader in the dedicated bootloader area of the +// information block +#define BTL_FIRST_STAGE_BASE 0x0FE10000UL +#define BTL_APPLICATION_BASE 0x00000000UL +#define BTL_MAIN_STAGE_MAX_SIZE (0x00009800UL - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define BTL_FIRST_STAGE_BASE 0x0FE10000UL +#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) +#define BTL_APPLICATION_BASE 0x00004800UL +#define BTL_MAIN_STAGE_MAX_SIZE BTL_APPLICATION_BASE +#else +// Dedicated bootloader area of 16k +// Place the bootloader in the dedicated bootloader area of the +// information block +#define BTL_APPLICATION_BASE 0x00000000UL +#define BTL_MAIN_STAGE_MAX_SIZE (0x00004000UL - BTL_FIRST_STAGE_SIZE) +#endif +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#define BTL_FIRST_STAGE_BASE 0x0FE10000UL +#if defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) +#define BTL_APPLICATION_BASE 0x00004800UL +#define BTL_MAIN_STAGE_MAX_SIZE BTL_APPLICATION_BASE +#else +// Dedicated bootloader area of 18k +// Place the bootloader in the dedicated bootloader area of the +// information block +#define BTL_APPLICATION_BASE 0x00000000UL +#define BTL_MAIN_STAGE_MAX_SIZE (0x00004800UL - BTL_FIRST_STAGE_SIZE) +#endif +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +// Dedicated bootloader area of 32k +// Place the bootloader in the dedicated bootloader area of the +// information block +#define BTL_FIRST_STAGE_BASE 0x0FE10000UL +#define BTL_APPLICATION_BASE 0x00000000UL +#define BTL_MAIN_STAGE_MAX_SIZE (0x00008000UL - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +// Dedicated bootloader area of 18k +// Place the bootloader in the dedicated bootloader area of the +// information block +#define BTL_FIRST_STAGE_BASE 0x0FE10000UL +#define BTL_APPLICATION_BASE 0x00000000UL +#define BTL_MAIN_STAGE_MAX_SIZE (0x00004800UL - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#elif defined(BOOTLOADER_SECURE) && defined(BOOTLOADER_SUPPORT_COMMUNICATION) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00004000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - BTL_FIRST_STAGE_SIZE) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#elif defined(BOOTLOADER_CUSTOM_SIZE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00004000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE)) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE)) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_220) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE)) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_230) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE)) +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_235) +// No bootloader area: Place the bootloader in main flash +#define BTL_FIRST_STAGE_BASE FLASH_BASE +#if defined(BOOTLOADER_APPLOADER) +#if defined(BOOTLOADER_SECURE) +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00014000UL) +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00012000UL) +#endif // BOOTLOADER_SECURE +#else +#define BTL_APPLICATION_BASE (FLASH_BASE + 0x00006000UL) +#endif // BOOTLOADER_APPLOADER +#define BTL_MAIN_STAGE_MAX_SIZE (BTL_APPLICATION_BASE \ + - (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE)) +#else +#error "This part is not supported in this bootloader version." +#endif + +#if defined(MAIN_BOOTLOADER_TEST) || defined(MAIN_BOOTLOADER_IN_MAIN_FLASH) +#define BTL_MAIN_STAGE_BASE (FLASH_BASE) +#else +#define BTL_MAIN_STAGE_BASE (BTL_FIRST_STAGE_BASE \ + + BTL_FIRST_STAGE_SIZE) +#endif + +#if defined(BOOTLOADER_HAS_FIRST_STAGE) +#define BTL_FIRST_BOOTLOADER_TABLE_BASE (BTL_FIRST_STAGE_BASE \ + + offsetof(BareBootTable_t, table)) +#endif +#define BTL_MAIN_BOOTLOADER_TABLE_BASE (BTL_MAIN_STAGE_BASE \ + + offsetof(BareBootTable_t, table)) + +/// @endcond // DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(MAIN_BOOTLOADER_TEST) +#if defined(BOOTLOADER_HAS_FIRST_STAGE) +extern FirstBootloaderTable_t *firstBootloaderTable; +#endif +extern MainBootloaderTable_t *mainBootloaderTable; +#else +#if defined(BOOTLOADER_HAS_FIRST_STAGE) +/// Pointer to first stage bootloader table +#define firstBootloaderTable (*(FirstBootloaderTable_t **) \ + (BTL_FIRST_BOOTLOADER_TABLE_BASE)) +#endif // BOOTLOADER_HAS_FIRST_STAGE +/// Pointer to main bootloader table +#define mainBootloaderTable (*(MainBootloaderTable_t **) \ + (BTL_MAIN_BOOTLOADER_TABLE_BASE)) +#endif // MAIN_BOOTLOADER_TEST +// -------------------------------- +// Functions + +/***************************************************************************//** + * Get information about the bootloader on this device. + * + * The returned information is fetched from the main bootloader + * information table. + * + * @param[out] info Pointer to the bootloader information struct. + ******************************************************************************/ +void bootloader_getInfo(BootloaderInformation_t *info); + +/***************************************************************************//** + * Initialize components of the bootloader + * so the app can use the interface. This typically includes initializing + * serial peripherals for communication with external SPI flashes, and so on. + * + * @return Error code. @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_INIT_BASE range. + ******************************************************************************/ +int32_t bootloader_init(void); + +/***************************************************************************//** + * De-initialize components of the bootloader that were previously initialized. + * This typically includes powering down external SPI flashes and + * de-initializing the serial peripheral used for communication with the + * external flash. + * + * @return Error code. @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_INIT_BASE range. + ******************************************************************************/ +int32_t bootloader_deinit(void); + +/***************************************************************************//** + * Reboot into the bootloader to perform an install. + * + * If there is a storage component and a slot is marked for bootload, install + * the image in that slot after verifying it. + * + * If a communication component is present, open the communication channel and + * receive an image to be installed. + ******************************************************************************/ +void bootloader_rebootAndInstall(void); + +/***************************************************************************//** + * Verify the application image stored in the Flash memory starting at + * the address startAddress. + * + * If the secure boot is enforced, the function will only return true if the + * cryptographic signature of the application is valid. Otherwise, the + * application is verified according to the signature type defined in the + * ApplicationProperties_t structure embedded in the application. Silicon Labs + * wireless stacks include a declaration of this structure. However, + * applications not using a full wireless stack may need to instantiate + * the structure. + * + * Examples of results when the secure boot is not enforced: + * - App has no signature: Valid if initial stack pointer and program counter + * have reasonable values. + * - App has CRC checksum: Valid if checksum is valid. + * - App has ECDSA signature: Valid if ECDSA signature is valid. + * + * When secure boot is enforced, only ECDSA signed applications with + * a valid signature are considered valid. + * + * + * @param[in] startAddress Starting address of the application. + * + * @return True if the application is valid, else false. + ******************************************************************************/ +bool bootloader_verifyApplication(uint32_t startAddress); + +/***************************************************************************//** + * Check whether signature verification on the application image in internal flash + * is enforced before every boot. + * + * @return True if signature verification is enforced, else false. + ******************************************************************************/ +bool bootloader_secureBootEnforced(void); + +/***************************************************************************//** + * Get base address of the bootloader upgrade image. + * + * @param[out] location the base address of bootloader upgrade image. + * + * @return Returns true if the location was found. + ******************************************************************************/ +bool bootloader_getUpgradeLocation(uint32_t *location); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) +/***************************************************************************//** + * Get the list of the peripheral that is used by the bootloader. + * + * @param[out] ppusatd0 Word containing all the peripherals used by the + * bootloader. Each bit represents a peripheral, + * which is ordered after the PPUSATD0 register bit + * fields. + * + * @param[out] ppusatd1 Word containing all the peripherals used by the + * bootloader. Each bit represents a peripheral, + * which is ordered after the PPUSATD1 register bit + * fields. + ******************************************************************************/ +void bootloader_getPeripheralList(uint32_t *ppusatd0, uint32_t *ppusatd1); + +/***************************************************************************//** + * Save PPUSATDn state in RAM. + * Configure the peripheral attributes before calling into the bootloader. + * + * @note Enters ATOMIC section. + * + * @param[out] ctx Context struct to save register state into + * + * @return True if a valid certificate version is found. + ******************************************************************************/ +void bootloader_ppusatdnSaveReconfigureState(Bootloader_PPUSATDnCLKENnState_t *ctx); + +/***************************************************************************//** + * Restore PPUSATDn state from RAM. + * Store the USART used by the bootloader if this is unknown. + * + * @note Exits ATOMIC section. + * + * @param[in] ctx Context struct to restore register state from + * + * @return True if a valid certificate version is found. + ******************************************************************************/ +void bootloader_ppusatdnRestoreState(Bootloader_PPUSATDnCLKENnState_t *ctx); + +/***************************************************************************//** + * Called before the bootloader is initialized. + * + * This function implementation does not perform anything, but it is __weak + * so that it can be implemented by another application. + ******************************************************************************/ +void sli_bootloader_preHook(void); + +/***************************************************************************//** + * Called after the bootloader is de-initialized. + * + * This function implementation does not perform anything, but it is __weak + * so that it can be implemented by another application. + ******************************************************************************/ +void sli_bootloader_postHook(void); +#endif + +#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/***************************************************************************//** + * Count the total remaining number of application upgrades. + * + * @return remaining number of application upgrades. + ******************************************************************************/ +uint32_t bootloader_remainingApplicationUpgrades(void); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * Get bootloader certificate version. + * + * @param[out] version Bootloader certificate version + * + * @return True if a valid certificate version is found. + ******************************************************************************/ +bool bootloader_getCertificateVersion(uint32_t *version); +#endif // _SILICON_LABS_32B_SERIES_2 + +/***************************************************************************//** + * Get reset cause of the bootloader. + * + * @return Reset cause of the bootloader. + ******************************************************************************/ +BootloaderResetCause_t bootloader_getResetReason(void); + +#if defined(BOOTLOADER_HAS_FIRST_STAGE) +/***************************************************************************//** + * Check if a pointer is valid and if it points to the bootloader first stage. + * + * This function checks pointers to bootloader + * jump tables. + * + * + * @param[in] ptr The pointer to check + * + * @return True if the pointer points to the bootloader first stage, + * false if not. + ******************************************************************************/ +__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr); +__STATIC_INLINE bool bootloader_pointerToFirstStageValid(const void *ptr) +{ +#if defined(MAIN_BOOTLOADER_TEST) + // In main bootloader tests, no first stage is present + (void) ptr; + return false; +#elif BTL_FIRST_STAGE_BASE > 0U + if (((size_t)(ptr) >= BTL_FIRST_STAGE_BASE) + && ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE))) { + return true; + } else { + return false; + } +#else + // First stage starts at address 0, don't need to check lower bound + if ((size_t)(ptr) < (BTL_FIRST_STAGE_BASE + BTL_FIRST_STAGE_SIZE)) { + return true; + } else { + return false; + } +#endif +} +#endif // BOOTLOADER_HAS_FIRST_STAGE + +/***************************************************************************//** + * Check if a pointer is valid and if it points to the bootloader main stage. + * + * This function checks pointers to bootloader + * jump tables. + * + * + * @param[in] ptr The pointer to check + * + * @return True if the pointer points into the bootloader main stage, + * false if not. + ******************************************************************************/ +__STATIC_INLINE bool bootloader_pointerValid(const void *ptr); +__STATIC_INLINE bool bootloader_pointerValid(const void *ptr) +{ +#if defined(MAIN_BOOTLOADER_TEST) + // In main bootloader tests, all of memory is considered part of the bootloader + (void) ptr; + return true; +#elif BTL_MAIN_STAGE_BASE > 0U + if (((size_t)ptr >= BTL_MAIN_STAGE_BASE) + && ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE))) { + return true; + } else { + return false; + } +#else + if ((size_t)ptr < (BTL_MAIN_STAGE_BASE + BTL_MAIN_STAGE_MAX_SIZE)) { + return true; + } else { + return false; + } +#endif +} + +/** @} (end addtogroup CommonInterface) */ +/** @} (end addtogroup Interface) */ +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif + +#endif // BTL_INTERFACE_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_parser.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_parser.h index 3e0f347..6310ad3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_parser.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_parser.h @@ -1,138 +1,138 @@ -/***************************************************************************//** - * @file - * @brief Application interface to the bootloader parser. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef BTL_INTERFACE_PARSER_H -#define BTL_INTERFACE_PARSER_H - -#include -#include -#include - -/***************************************************************************//** - * @addtogroup Interface - * @{ - * @addtogroup ParserInterface Application Parser Interface - * @brief Application interface for the bootloader image - * parser. - * @details The Parser Interface can be used to parse upgrade images from the - * context of the application. - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Typedefs - -/***************************************************************************//** - * Bootloader parser callback - * - * @param address Address of the data - * @param data Raw data - * @param length Size in bytes of raw data. - * @param context A context variable defined by the implementation that - * is implementing this callback. - ******************************************************************************/ -typedef void (*BootloaderParserCallback_t)(uint32_t address, - uint8_t *data, - size_t length, - void *context); - -/// Context for the bootloader image parser routine. -typedef struct BootloaderParserContext BootloaderParserContext_t; - -/// Function pointers to parser callbacks -typedef struct { - /// Opaque pointer passed to the callback functions - void *context; - /// Callback function pointer for application image data - BootloaderParserCallback_t applicationCallback; - /// Callback function pointer for image metadata - BootloaderParserCallback_t metadataCallback; - /// Callback function pointer for bootloader upgrade image data - BootloaderParserCallback_t bootloaderCallback; -} BootloaderParserCallbacks_t; - -/***************************************************************************//** - * Initialize the image parser. - * - * @param[in] context Pointer to the parser context struct. - * @param[in] contextSize Size of the context struct. - * - * @return BOOTLOADER_OK if success, BOOTLOADER_ERROR_PARSE_CONTEXT if context - * struct is too small. - ******************************************************************************/ -int32_t bootloader_initParser(BootloaderParserContext_t *context, - size_t contextSize); - -#if !defined(SL_TRUSTZONE_NONSECURE) -/***************************************************************************//** - * Parse a buffer. - * @param[in] context Pointer to the parser context struct. - * @param[in] callbacks Callbacks to be called by the parser. - * @param[in] data Data to be parsed. - * @param[in] numBytes Size of the data buffer. - * - * @return BOOTLOADER_ERROR_PARSE_CONTINUE if the chunk was parsed correctly, - * and a new chunk is expected. BOOTLOADER_ERROR_PARSE_ERROR if - * something went wrong while parsing. BOOTLOADER_ERROR_PARSE_SUCCESS - * if the entire file was successfully parsed. - ******************************************************************************/ -int32_t bootloader_parseBuffer(BootloaderParserContext_t *context, - BootloaderParserCallbacks_t *callbacks, - uint8_t data[], - size_t numBytes); -#endif // SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Parse a buffer and get application and bootloader upgrade metadata - * from the buffer. - * - * @note \p appInfo and \p bootloaderVersion will default to zeros. - * - * @param[in] context Pointer to the parser context struct. - * @param[in] data Data to be parsed. - * @param[in] numBytes Size of the data buffer. - * @param[out] appInfo Pointer to @ref ApplicationData_t struct. - * @param[out] bootloaderVersion Pointer to an integer representing bootloader - * version. - * - * @return @ref BOOTLOADER_OK if metadata was filled successfully. - ******************************************************************************/ -#if !defined(SL_TRUSTZONE_NONSECURE) -int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context, - uint8_t data[], - size_t numBytes, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion); -#else -int32_t bootloader_parseImageInfo(uint8_t data[], - size_t numBytes, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion); -#endif // SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Find the size of the context struct BootloaderParserContext used by the bootloader - * image parser to store parser state. - * - * @return size of BootloaderParserContext, returns 0 if something went wrong. - ******************************************************************************/ -uint32_t bootloader_parserContextSize(void); - -/** @} (end addtogroup ParserInterface) */ -/** @} (end addtogroup Interface) */ - -#endif // BTL_INTERFACE_PARSER_H +/***************************************************************************//** + * @file + * @brief Application interface to the bootloader parser. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef BTL_INTERFACE_PARSER_H +#define BTL_INTERFACE_PARSER_H + +#include +#include +#include + +/***************************************************************************//** + * @addtogroup Interface + * @{ + * @addtogroup ParserInterface Application Parser Interface + * @brief Application interface for the bootloader image + * parser. + * @details The Parser Interface can be used to parse upgrade images from the + * context of the application. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Typedefs + +/***************************************************************************//** + * Bootloader parser callback + * + * @param address Address of the data + * @param data Raw data + * @param length Size in bytes of raw data. + * @param context A context variable defined by the implementation that + * is implementing this callback. + ******************************************************************************/ +typedef void (*BootloaderParserCallback_t)(uint32_t address, + uint8_t *data, + size_t length, + void *context); + +/// Context for the bootloader image parser routine. +typedef struct BootloaderParserContext BootloaderParserContext_t; + +/// Function pointers to parser callbacks +typedef struct { + /// Opaque pointer passed to the callback functions + void *context; + /// Callback function pointer for application image data + BootloaderParserCallback_t applicationCallback; + /// Callback function pointer for image metadata + BootloaderParserCallback_t metadataCallback; + /// Callback function pointer for bootloader upgrade image data + BootloaderParserCallback_t bootloaderCallback; +} BootloaderParserCallbacks_t; + +/***************************************************************************//** + * Initialize the image parser. + * + * @param[in] context Pointer to the parser context struct. + * @param[in] contextSize Size of the context struct. + * + * @return BOOTLOADER_OK if success, BOOTLOADER_ERROR_PARSE_CONTEXT if context + * struct is too small. + ******************************************************************************/ +int32_t bootloader_initParser(BootloaderParserContext_t *context, + size_t contextSize); + +#if !defined(SL_TRUSTZONE_NONSECURE) +/***************************************************************************//** + * Parse a buffer. + * @param[in] context Pointer to the parser context struct. + * @param[in] callbacks Callbacks to be called by the parser. + * @param[in] data Data to be parsed. + * @param[in] numBytes Size of the data buffer. + * + * @return BOOTLOADER_ERROR_PARSE_CONTINUE if the chunk was parsed correctly, + * and a new chunk is expected. BOOTLOADER_ERROR_PARSE_ERROR if + * something went wrong while parsing. BOOTLOADER_ERROR_PARSE_SUCCESS + * if the entire file was successfully parsed. + ******************************************************************************/ +int32_t bootloader_parseBuffer(BootloaderParserContext_t *context, + BootloaderParserCallbacks_t *callbacks, + uint8_t data[], + size_t numBytes); +#endif // SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Parse a buffer and get application and bootloader upgrade metadata + * from the buffer. + * + * @note \p appInfo and \p bootloaderVersion will default to zeros. + * + * @param[in] context Pointer to the parser context struct. + * @param[in] data Data to be parsed. + * @param[in] numBytes Size of the data buffer. + * @param[out] appInfo Pointer to @ref ApplicationData_t struct. + * @param[out] bootloaderVersion Pointer to an integer representing bootloader + * version. + * + * @return @ref BOOTLOADER_OK if metadata was filled successfully. + ******************************************************************************/ +#if !defined(SL_TRUSTZONE_NONSECURE) +int32_t bootloader_parseImageInfo(BootloaderParserContext_t *context, + uint8_t data[], + size_t numBytes, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion); +#else +int32_t bootloader_parseImageInfo(uint8_t data[], + size_t numBytes, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion); +#endif // SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Find the size of the context struct BootloaderParserContext used by the bootloader + * image parser to store parser state. + * + * @return size of BootloaderParserContext, returns 0 if something went wrong. + ******************************************************************************/ +uint32_t bootloader_parserContextSize(void); + +/** @} (end addtogroup ParserInterface) */ +/** @} (end addtogroup Interface) */ + +#endif // BTL_INTERFACE_PARSER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.c b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.c index 259ca09..52b80fc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.c @@ -1,576 +1,576 @@ -/***************************************************************************//** - * @file - * @brief Application interface to the storage component of the bootloader. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "btl_interface.h" - -// ----------------------------------------------------------------------------- -// Defines - -// Make assert no-op if not configured -#ifndef BTL_ASSERT -#define BTL_ASSERT(x) -#endif -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif -// ----------------------------------------------------------------------------- -// Static variables - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) -static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 }; -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - -// ----------------------------------------------------------------------------- -// Functions - -void bootloader_getStorageInfo(BootloaderStorageInformation_t *info) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return; - } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - mainBootloaderTable->storage->getInfo(info); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE -} - -int32_t bootloader_getStorageSlotInfo(uint32_t slotId, - BootloaderStorageSlot_t *slot) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - return mainBootloaderTable->storage->getSlotInfo(slotId, slot); -} - -int32_t bootloader_readStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->read(slotId, offset, buffer, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif - - return retVal; -} - -int32_t bootloader_writeStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->write(slotId, offset, buffer, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_eraseWriteStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length) -{ - int32_t retVal; - uint16_t flashPageSize; - uint32_t storageStartAddr; - uint32_t eraseOffset; - uint32_t eraseLength; - BootloaderStorageSlot_t storageSlot; - BootloaderStorageInformation_t storageInfo; - - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - - bootloader_getStorageInfo(&storageInfo); - flashPageSize = storageInfo.info->pageSize; - if (flashPageSize == 0) { - return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT; - } - - retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - storageStartAddr = storageSlot.address; - - if (offset + length > storageSlot.length) { - return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; - } - - if (offset % flashPageSize) { - // Erase from next page: - eraseOffset = (offset & ~(flashPageSize - 1)) + flashPageSize; - - if ((offset + length) % flashPageSize) { - // Example case for this if/else section: - // 0 1 2 3 - // |----|----|----| - // ^ ^ - // O L - eraseLength = ((offset + length) & ~(flashPageSize - 1)) + flashPageSize - eraseOffset; - } else { - // Example case for this if/else section: - // 0 1 2 3 - // |----|----|----| - // ^ ^ - // O L - eraseLength = length - (flashPageSize - (offset % flashPageSize)); - } - eraseOffset = storageStartAddr + eraseOffset; - } else { - eraseOffset = storageStartAddr + offset; - if (length % flashPageSize) { - // Example case for this if/else section: - // 0 1 2 3 - // |----|----|----| - // ^ ^ - // O L - eraseLength = (length & ~(flashPageSize - 1)) + flashPageSize; - } else { - // Example case for this if/else section: - // 0 1 2 3 - // |----|----|----| - // ^ ^ - // O L - eraseLength = length; - } - } - if (eraseLength != 0) { - retVal = bootloader_eraseRawStorage(eraseOffset, eraseLength); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - } - - retVal = bootloader_writeRawStorage(storageStartAddr + offset, buffer, length); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - - return BOOTLOADER_OK; -} - -int32_t bootloader_eraseStorageSlot(uint32_t slotId) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->erase(slotId); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_initChunkedEraseStorageSlot(uint32_t slotId, - BootloaderEraseStatus_t *eraseStat) -{ - int32_t retVal; - BootloaderStorageInformation_t storageInfo; - bootloader_getStorageInfo(&storageInfo); - - retVal = bootloader_getStorageSlotInfo(slotId, &eraseStat->storageSlotInfo); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - - eraseStat->currentPageAddr = eraseStat->storageSlotInfo.address; - eraseStat->pageSize = storageInfo.info->pageSize; - - return BOOTLOADER_OK; -} - -int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat) -{ - int32_t retVal; - if (eraseStat->currentPageAddr - == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) { - return BOOTLOADER_OK; - } - - retVal = bootloader_eraseRawStorage(eraseStat->currentPageAddr, eraseStat->pageSize); - if (retVal != BOOTLOADER_OK) { - return retVal; - } - - eraseStat->currentPageAddr += eraseStat->pageSize; - if (eraseStat->currentPageAddr - == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) { - return BOOTLOADER_OK; - } - - return BOOTLOADER_ERROR_STORAGE_CONTINUE; -} - -int32_t bootloader_setImageToBootload(int32_t slotId) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(&slotId, 1); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(slotIds, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->getImagesToBootload(slotIds, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_appendImageToBootloadList(int32_t slotId) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_TABLE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->appendImageToBootloadList(slotId); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_initVerifyImage(uint32_t slotId, - void *context, - size_t contextSize) -{ - int32_t retVal; - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_PARSE_STORAGE; - } - - // Check that the bootloader has image verification capability - if (mainBootloaderTable->storage == NULL) { - return BOOTLOADER_ERROR_PARSE_STORAGE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - retVal = mainBootloaderTable->storage->initParseImage( - slotId, - (BootloaderParserContext_t*)context, - contextSize); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_continueVerifyImage(void *context, - BootloaderParserCallback_t metadataCallback) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_PARSE_STORAGE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->verifyImage( - (BootloaderParserContext_t *)context, - metadataCallback); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_verifyImage(uint32_t slotId, - BootloaderParserCallback_t metadataCallback) -{ - int32_t retval; - uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE]; - - if (!bootloader_pointerValid(mainBootloaderTable)) { - return BOOTLOADER_ERROR_PARSE_STORAGE; - } - - retval = bootloader_initVerifyImage(slotId, - context, - BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE); - - if (retval != BOOTLOADER_OK) { - return retval; - } - - do { - retval = bootloader_continueVerifyImage(context, metadataCallback); - } while (retval == BOOTLOADER_ERROR_PARSE_CONTINUE); - - if (retval == BOOTLOADER_ERROR_PARSE_SUCCESS) { - return BOOTLOADER_OK; - } else { - return retval; - } -} - -int32_t bootloader_getImageInfo(uint32_t slotId, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion) -{ - int32_t retval; - uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE]; - - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_PARSE_STORAGE; - } - - // Check that the bootloader has image verification capability - BTL_ASSERT(mainBootloaderTable->storage != NULL); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - retval = mainBootloaderTable->storage->initParseImage( - slotId, - (BootloaderParserContext_t *)context, - BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE); - if (retval != BOOTLOADER_OK) { -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - return retval; - } - retval = mainBootloaderTable->storage->getImageInfo( - (BootloaderParserContext_t *)context, - appInfo, - bootloaderVersion); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retval; -} - -bool bootloader_storageIsBusy(void) -{ - bool isBusy = false; - - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return true; - } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - isBusy = mainBootloaderTable->storage->isBusy(); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return isBusy; -} - -int32_t bootloader_readRawStorage(uint32_t address, - uint8_t *buffer, - size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->readRaw(address, buffer, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_writeRawStorage(uint32_t address, - uint8_t *buffer, - size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->writeRaw(address, buffer, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} - -int32_t bootloader_getAllocatedDMAChannel(void) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } - - BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; - bootloader_getInfo(&info); - - if ((info.capabilities & BOOTLOADER_CAPABILITY_STORAGE) == 0u) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } - - uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) - >> BOOTLOADER_VERSION_MAJOR_SHIFT); - uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) - >> BOOTLOADER_VERSION_MINOR_SHIFT); - - if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } - - return mainBootloaderTable->storage->getDMAchannel(); -} - -int32_t bootloader_eraseRawStorage(uint32_t address, - size_t length) -{ - if (!bootloader_pointerValid(mainBootloaderTable) - || !bootloader_pointerValid(mainBootloaderTable->storage)) { - return BOOTLOADER_ERROR_INIT_STORAGE; - } - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - int32_t retVal = mainBootloaderTable->storage->eraseRaw(address, length); - -#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) - bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); -#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE - - return retVal; -} -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif +/***************************************************************************//** + * @file + * @brief Application interface to the storage component of the bootloader. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "btl_interface.h" + +// ----------------------------------------------------------------------------- +// Defines + +// Make assert no-op if not configured +#ifndef BTL_ASSERT +#define BTL_ASSERT(x) +#endif +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif +// ----------------------------------------------------------------------------- +// Static variables + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) +static Bootloader_PPUSATDnCLKENnState_t blPPUSATDnCLKENnState = { 0 }; +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + +// ----------------------------------------------------------------------------- +// Functions + +void bootloader_getStorageInfo(BootloaderStorageInformation_t *info) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return; + } +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + mainBootloaderTable->storage->getInfo(info); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE +} + +int32_t bootloader_getStorageSlotInfo(uint32_t slotId, + BootloaderStorageSlot_t *slot) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + return mainBootloaderTable->storage->getSlotInfo(slotId, slot); +} + +int32_t bootloader_readStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->read(slotId, offset, buffer, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif + + return retVal; +} + +int32_t bootloader_writeStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->write(slotId, offset, buffer, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_eraseWriteStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length) +{ + int32_t retVal; + uint16_t flashPageSize; + uint32_t storageStartAddr; + uint32_t eraseOffset; + uint32_t eraseLength; + BootloaderStorageSlot_t storageSlot; + BootloaderStorageInformation_t storageInfo; + + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + + bootloader_getStorageInfo(&storageInfo); + flashPageSize = storageInfo.info->pageSize; + if (flashPageSize == 0) { + return BOOTLOADER_ERROR_STORAGE_INVALID_SLOT; + } + + retVal = bootloader_getStorageSlotInfo(slotId, &storageSlot); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + storageStartAddr = storageSlot.address; + + if (offset + length > storageSlot.length) { + return BOOTLOADER_ERROR_STORAGE_INVALID_ADDRESS; + } + + if (offset % flashPageSize) { + // Erase from next page: + eraseOffset = (offset & ~(flashPageSize - 1)) + flashPageSize; + + if ((offset + length) % flashPageSize) { + // Example case for this if/else section: + // 0 1 2 3 + // |----|----|----| + // ^ ^ + // O L + eraseLength = ((offset + length) & ~(flashPageSize - 1)) + flashPageSize - eraseOffset; + } else { + // Example case for this if/else section: + // 0 1 2 3 + // |----|----|----| + // ^ ^ + // O L + eraseLength = length - (flashPageSize - (offset % flashPageSize)); + } + eraseOffset = storageStartAddr + eraseOffset; + } else { + eraseOffset = storageStartAddr + offset; + if (length % flashPageSize) { + // Example case for this if/else section: + // 0 1 2 3 + // |----|----|----| + // ^ ^ + // O L + eraseLength = (length & ~(flashPageSize - 1)) + flashPageSize; + } else { + // Example case for this if/else section: + // 0 1 2 3 + // |----|----|----| + // ^ ^ + // O L + eraseLength = length; + } + } + if (eraseLength != 0) { + retVal = bootloader_eraseRawStorage(eraseOffset, eraseLength); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + } + + retVal = bootloader_writeRawStorage(storageStartAddr + offset, buffer, length); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + return BOOTLOADER_OK; +} + +int32_t bootloader_eraseStorageSlot(uint32_t slotId) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->erase(slotId); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_initChunkedEraseStorageSlot(uint32_t slotId, + BootloaderEraseStatus_t *eraseStat) +{ + int32_t retVal; + BootloaderStorageInformation_t storageInfo; + bootloader_getStorageInfo(&storageInfo); + + retVal = bootloader_getStorageSlotInfo(slotId, &eraseStat->storageSlotInfo); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + eraseStat->currentPageAddr = eraseStat->storageSlotInfo.address; + eraseStat->pageSize = storageInfo.info->pageSize; + + return BOOTLOADER_OK; +} + +int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat) +{ + int32_t retVal; + if (eraseStat->currentPageAddr + == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) { + return BOOTLOADER_OK; + } + + retVal = bootloader_eraseRawStorage(eraseStat->currentPageAddr, eraseStat->pageSize); + if (retVal != BOOTLOADER_OK) { + return retVal; + } + + eraseStat->currentPageAddr += eraseStat->pageSize; + if (eraseStat->currentPageAddr + == (eraseStat->storageSlotInfo.address + eraseStat->storageSlotInfo.length)) { + return BOOTLOADER_OK; + } + + return BOOTLOADER_ERROR_STORAGE_CONTINUE; +} + +int32_t bootloader_setImageToBootload(int32_t slotId) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(&slotId, 1); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->setImagesToBootload(slotIds, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->getImagesToBootload(slotIds, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_appendImageToBootloadList(int32_t slotId) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_TABLE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->appendImageToBootloadList(slotId); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_initVerifyImage(uint32_t slotId, + void *context, + size_t contextSize) +{ + int32_t retVal; + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_PARSE_STORAGE; + } + + // Check that the bootloader has image verification capability + if (mainBootloaderTable->storage == NULL) { + return BOOTLOADER_ERROR_PARSE_STORAGE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retVal = mainBootloaderTable->storage->initParseImage( + slotId, + (BootloaderParserContext_t*)context, + contextSize); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_continueVerifyImage(void *context, + BootloaderParserCallback_t metadataCallback) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_PARSE_STORAGE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->verifyImage( + (BootloaderParserContext_t *)context, + metadataCallback); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_verifyImage(uint32_t slotId, + BootloaderParserCallback_t metadataCallback) +{ + int32_t retval; + uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE]; + + if (!bootloader_pointerValid(mainBootloaderTable)) { + return BOOTLOADER_ERROR_PARSE_STORAGE; + } + + retval = bootloader_initVerifyImage(slotId, + context, + BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE); + + if (retval != BOOTLOADER_OK) { + return retval; + } + + do { + retval = bootloader_continueVerifyImage(context, metadataCallback); + } while (retval == BOOTLOADER_ERROR_PARSE_CONTINUE); + + if (retval == BOOTLOADER_ERROR_PARSE_SUCCESS) { + return BOOTLOADER_OK; + } else { + return retval; + } +} + +int32_t bootloader_getImageInfo(uint32_t slotId, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion) +{ + int32_t retval; + uint8_t context[BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE]; + + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_PARSE_STORAGE; + } + + // Check that the bootloader has image verification capability + BTL_ASSERT(mainBootloaderTable->storage != NULL); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + retval = mainBootloaderTable->storage->initParseImage( + slotId, + (BootloaderParserContext_t *)context, + BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE); + if (retval != BOOTLOADER_OK) { +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + return retval; + } + retval = mainBootloaderTable->storage->getImageInfo( + (BootloaderParserContext_t *)context, + appInfo, + bootloaderVersion); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retval; +} + +bool bootloader_storageIsBusy(void) +{ + bool isBusy = false; + + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return true; + } +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + isBusy = mainBootloaderTable->storage->isBusy(); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return isBusy; +} + +int32_t bootloader_readRawStorage(uint32_t address, + uint8_t *buffer, + size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->readRaw(address, buffer, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_writeRawStorage(uint32_t address, + uint8_t *buffer, + size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->writeRaw(address, buffer, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} + +int32_t bootloader_getAllocatedDMAChannel(void) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + + BootloaderInformation_t info = { .type = SL_BOOTLOADER, .version = 0U, .capabilities = 0U }; + bootloader_getInfo(&info); + + if ((info.capabilities & BOOTLOADER_CAPABILITY_STORAGE) == 0u) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + + uint32_t blMajorVersion = ((info.version & BOOTLOADER_VERSION_MAJOR_MASK) + >> BOOTLOADER_VERSION_MAJOR_SHIFT); + uint32_t blMinorVersion = ((info.version & BOOTLOADER_VERSION_MINOR_MASK) + >> BOOTLOADER_VERSION_MINOR_SHIFT); + + if ((blMajorVersion < 1UL) || (blMajorVersion == 1UL && blMinorVersion < 11UL)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + + return mainBootloaderTable->storage->getDMAchannel(); +} + +int32_t bootloader_eraseRawStorage(uint32_t address, + size_t length) +{ + if (!bootloader_pointerValid(mainBootloaderTable) + || !bootloader_pointerValid(mainBootloaderTable->storage)) { + return BOOTLOADER_ERROR_INIT_STORAGE; + } + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnSaveReconfigureState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + int32_t retVal = mainBootloaderTable->storage->eraseRaw(address, length); + +#if defined(BOOTLOADER_INTERFACE_TRUSTZONE_AWARE) + bootloader_ppusatdnRestoreState(&blPPUSATDnCLKENnState); +#endif // BOOTLOADER_INTERFACE_TRUSTZONE_AWARE + + return retVal; +} +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.h index a1a704c..3ec89a1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_interface_storage.h @@ -1,653 +1,653 @@ -/***************************************************************************//** - * @file - * @brief Application interface to the storage component of the bootloader. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef BTL_INTERFACE_STORAGE_H -#define BTL_INTERFACE_STORAGE_H - -#include -#include -#include - -// Get part series version. -#include "em_device.h" - -/***************************************************************************//** - * @addtogroup Interface - * @{ - * @addtogroup StorageInterface Application Storage Interface - * @brief Application interface for interfacing with the bootloader storage. - * @note These Bootloader APIs are not reentrant and should be wrapped in critical section - * where needed. - * @details The Storage Interface is only available on bootloaders that declare - * they support @ref BOOTLOADER_CAPABILITY_STORAGE. - * - * @li @ref bootloader_interface_example - * - * @n @section bootloader_interface_example Example - * - * @brief Snippet for the OTA use case: - * @verbatim - * ///OTA Example - * /// Assuming the user has an upgrade image downloaded which will be used to upgrade the application - * - * //Initialize the bootloader interface - * bootloader_init(); - * - * //Erase the storage slot in internal/SPI flash memory - * bootloader_eraseStorageSlot(0); - * - * //Write the upgrade image (GBL file data) to the slot. blinkGbl  uint8 array holding the GBL data in memory - * bootloader_writeStorage(0, 0, blinkGbl, sizeof(blinkGbl)); - * - * //Reboot into the bootloader to install the new image - * bootloader_rebootAndInstall(); - * - * The general flow for bootloader interface APIs from the application is: - * - * ///General flow - * - * //Initialize the bootloader interface - * bootloader_init(); - * - * //Interface API accesses - * …………… - * …………… - * …………… - * - * //De-initialize the bootloader interface - * bootloader_deinit(); - * @endverbatim - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Typedefs - -/// Possible storage types -typedef enum { - /// Storage backend is a SPI flash - SPIFLASH, - /// Storage backend is internal flash - INTERNAL_FLASH, - /// Storage backend is custom - CUSTOM_STORAGE -} BootloaderStorageType_t; - -/// Information about a storage slot -typedef struct { - /// Address of the slot. - uint32_t address; - /// Size of the slot. - uint32_t length; -} BootloaderStorageSlot_t; - -/// Information about the bootloader storage implementation -/// Note: From Gecko Bootloader version >= 2.1, -/// the pointer partType will only contain a zero value. -/// The partType variable can be used to find information -/// about the attached storage. -typedef struct { - /// The version of this data structure - uint16_t version; - /// A bitmask describing the capabilities of this particular storage - uint16_t capabilitiesMask; - /// Maximum time it takes to erase a page. (in milliseconds) - uint32_t pageEraseMs; - /// Maximum time it takes to erase the entire part. (in milliseconds) - uint32_t partEraseMs; - /// The size of a single erasable page in bytes - uint32_t pageSize; - /// The total size of the storage in bytes - uint32_t partSize; - /// Pointer to a string describing the attached storage - char *partDescription; - /// The number of bytes in a word for the storage - uint8_t wordSizeBytes; - /// Value representing the attached storage - uint32_t partType; -} BootloaderStorageImplementationInformation_t; - -/// Information about the bootloader storage \n -/// Note: The flashInfo variable is only usable with -/// Gecko Bootloader version >= 2.0. All previous versions of the -/// Gecko Bootloader do not support the flashInfo data field. -typedef struct { - /// The version of this data structure - uint32_t version; - /// The capabilities of the storage component - uint32_t capabilities; - /// Type of storage - BootloaderStorageType_t storageType; - /// Number of storage slots - uint32_t numStorageSlots; - /// A pointer to detailed information about the attached storage - BootloaderStorageImplementationInformation_t *info; - /// Detailed information about the attached storage(available for use only with Gecko Bootloader version >= 2.0) - BootloaderStorageImplementationInformation_t flashInfo; -} BootloaderStorageInformation_t; - -/// Erase status struct -typedef struct { - /// Address of the current page to be erased - uint32_t currentPageAddr; - /// The size of a single erasable page in bytes - uint32_t pageSize; - /// Information about a storage slot - BootloaderStorageSlot_t storageSlotInfo; -} BootloaderEraseStatus_t; - -/// Storage API accessible from the application -typedef struct BootloaderStorageFunctions { - /// Version of this struct - uint32_t version; - /// Get information about the storage -- capabilities, layout, configuration - void (*getInfo)(BootloaderStorageInformation_t *info); - /// Get information about storage slot -- size, location - int32_t (*getSlotInfo)(uint32_t slotId, BootloaderStorageSlot_t *slot); - /// Read bytes from slot into buffer - int32_t (*read)(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length); - /// Write bytes from buffer into slot - int32_t (*write)(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length); - /// Erase an entire slot - int32_t (*erase)(uint32_t slotId); - // ------------------------------ - /// Mark a list of slots for bootload - int32_t (*setImagesToBootload)(int32_t *slotIds, size_t length); - /// Mark a list of slots for bootload - int32_t (*getImagesToBootload)(int32_t *slotIds, size_t length); - /// Append a slot to bootload list - int32_t (*appendImageToBootloadList)(int32_t slotId); - // ------------------------------ - /// Start image parsing - int32_t (*initParseImage)(uint32_t slotId, - BootloaderParserContext_t *context, - size_t contextSize); - /// Continue image verification - int32_t (*verifyImage)(BootloaderParserContext_t *context, - BootloaderParserCallback_t metadataCallback); - /// Get app and bootloader upgrade information from storage slot - int32_t (*getImageInfo)(BootloaderParserContext_t *context, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion); - /// Check whether the bootloader storage is busy - bool (*isBusy)(void); - /// Read raw bytes from storage - int32_t (*readRaw)(uint32_t address, uint8_t *buffer, size_t length); - /// Write bytes to raw storage - int32_t (*writeRaw)(uint32_t address, uint8_t *buffer, size_t length); - /// Erase storage - int32_t (*eraseRaw)(uint32_t address, size_t length); - /// Get configured DMA channel - int32_t (*getDMAchannel)(void); -} BootloaderStorageFunctions_t; - -// ----------------------------------------------------------------------------- -// Defines - -/// Context size for bootloader verification context -#if defined(_SILICON_LABS_32B_SERIES_2) -#if defined(SEMAILBOX_PRESENT) -/// Context size(680) includes counter(16) plus stream_block(16 (block size) * 8 (Maximum blocks)) -#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (680) -#else -#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (568) -#endif -#else -#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (384) -#endif - -/// Current version of the BootloaderStorageInformation_t struct -#define BOOTLOADER_STORAGE_INFO_VERSION (0x30000U) -/// Current version of the BootloaderStorageImplementationInformation_t struct -#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION (0x0210U) -/// Major version of the BootloaderStorageImplementationInformation_t struct -#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR (0x0200U) -/// Major version mask for @ref BOOTLOADER_STORAGE_IMPL_INFO_VERSION -#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR_MASK (0xFF00U) - -/// Spiflash capability indicating that it supports erase -#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_ERASE_SUPPORTED (1 << 0) -/// @brief Spiflash capability indicating it requires full page erases before -/// new data can be written -#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_PAGE_ERASE_REQUIRED (1 << 1) -/// Spiflash capability indicating that the write function is blocking -#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_WRITE (1 << 2) -/// Spiflash capability indicating that the erase function is blocking -#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_ERASE (1 << 3) - -/// ISSI IS25LQ040B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ040B (1U << 0) -/// ISSI IS25LQ020B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ020B (1U << 1) -/// ISSI IS25LQ010B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ010B (1U << 2) -/// ISSI IS25LQ512B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ512B (1U << 3) -/// ISSI IS25LQ025B SPI Flash -#define BOOTLOADER_STORAGE_ISSI_IS25LQ025B (1U << 4) -/// Numonyx M25P16 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P16 (1U << 5) -/// Numonyx M25P80 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P80 (1U << 6) -/// Numonyx M25P40 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P40 (1U << 7) -/// Numonyx M25P20 SPI Flash -#define BOOTLOADER_STORAGE_NUMONYX_M25P20 (1U << 8) -/// Adesto AT25SF041 SPI Flash -#define BOOTLOADER_STORAGE_ADESTO_AT25SF041 (1U << 9) -/// Atmel AT25DF081A SPI Flash -#define BOOTLOADER_STORAGE_ATMEL_AT25DF081A (1U << 10) -/// Atmel AT25DF041A SPI Flash -#define BOOTLOADER_STORAGE_ATMEL_AT25DF041A (1U << 11) -/// Macronix MX25R6435F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R6435F (1U << 12) -/// Macronix MX25R6435F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R3235F (1U << 13) -/// Macronix MX25U1635E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25U1635E (1U << 14) -/// Macronix MX25L1606E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L1606E (1U << 15) -/// Macronix MX25R8035F SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25R8035F (1U << 16) -/// Macronix MX25L8006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L8006E (1U << 17) -/// Macronix MX25L4006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L4006E (1U << 18) -/// Macronix MX25L2006E SPI Flash -#define BOOTLOADER_STORAGE_MACRONIX_MX25L2006E (1U << 19) -/// Winbond W25Q80BV SPI Flash -#define BOOTLOADER_STORAGE_WINBOND_W25Q80BV (1U << 20) -/// Winbond W25X20BV SPI Flash -#define BOOTLOADER_STORAGE_WINBOND_W25X20BV (1U << 21) -/// Spansion S25L208K SPI Flash -#define BOOTLOADER_STORAGE_SPANSION_S25FL208K (1U << 22) -/// Internal storage -#define BOOTLOADER_STORAGE_INTERNAL_STORAGE (1U << 30) -/// JEDEC Supported SPI Flash -#define BOOTLOADER_STORAGE_JEDEC (1U << 31) - -// ----------------------------------------------------------------------------- -// Functions - -/***************************************************************************//** - * Get information about the storage component. - * - * @param[out] info Information about the storage component. - ******************************************************************************/ -void bootloader_getStorageInfo(BootloaderStorageInformation_t *info); - -/***************************************************************************//** - * Get information about a storage slot. - * - * @param[in] slotId ID of the slot to get information about - * @param[out] slot Information about the storage slot - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_getStorageSlotInfo(uint32_t slotId, - BootloaderStorageSlot_t *slot); - -/***************************************************************************//** - * Read data from a storage slot. - * - * @param[in] slotId ID of the slot - * @param[in] offset Offset into the slot to start reading from - * @param[out] buffer Buffer to store the data - * @param[in] length Amount of data to read - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_readStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length); - -/***************************************************************************//** - * Write data to a storage slot. - * - * @note - * If DMA-based MSC write is enabled on the bootloader, writing data from - * flash to flash is not supported on Series-1 devices. DMA-based MSC write is - * enabled, both offset and buffer should be word aligned. In case the buffer - * is not aligned, the normal write procedure is used instead of DMA. - * - * @param[in] slotId ID of the slot - * @param[in] offset Offset into the slot to start writing to - * @param[in] buffer Buffer to read data to write from - * @param[in] length Amount of data to write. Must be a multiple of 4. - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_writeStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length); - -/***************************************************************************//** - * Erase and write data to a storage slot. - * - * @note This function automatically erases the following Flash page whenever - * the written data crosses a page boundary. In other words, the function - * can't be used to perform multiple sequential writes to the same - * address range unless the range starts at a page boundary. - * For a sequential write, the first call to this function should have - * a start address at a page boundary. Otherwise, the corresponding page - * of the starting address needs to be erased explicitly. If DMA-based - * MSC write is enabled on the bootloader, writing data from flash to - * flash is not supported on Series-1 devices. - * - * @param[in] slotId ID of the slot - * @param[in] offset Offset into the slot to start writing to - * @param[in] buffer Buffer to read data to write from - * @param[in] length Amount of data to write. Must be a multiple of 4. - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_eraseWriteStorage(uint32_t slotId, - uint32_t offset, - uint8_t *buffer, - size_t length); - -/***************************************************************************//** - * Erase all contents of a storage slot. - * - * @param[in] slotId ID of the slot - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_eraseStorageSlot(uint32_t slotId); - -/***************************************************************************//** - * Initialize chunked erase of a storage slot. - * - * @note This function must be called before calling - * @ref bootloader_chunkedEraseStorageSlot in a loop. - * - * @param[in] slotId ID of the slot - * @param[in] eraseStat Erase status struct - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_initChunkedEraseStorageSlot(uint32_t slotId, - BootloaderEraseStatus_t *eraseStat); - -/***************************************************************************//** - * Erase one page from a storage slot according to - * the struct BootloaderEraseStatus_t. - * - * @note @ref bootloader_initChunkedEraseStorageSlot must be called - * before calling this function, in order to prepare - * BootloaderEraseStatus_t. - * - * @note This can be called sequentially to, for example, erase all contents - * of a storage slot. - * - * @param[in] eraseStat Erase status struct - * - * @return @ref BOOTLOADER_ERROR_STORAGE_CONTINUE if erasing a page was - * successful. Erase can be continued by calling this function again. - * @ref BOOTLOADER_OK if the entire slot has been erased, - * else error code in @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat); - -/***************************************************************************//** - * Set a prioritized list of images to attempt to bootload. The last call to - * this function determines which slot will be installed when - * @ref bootloader_rebootAndInstall is called. - * - * @param[in] slotIds Prioritized list of slot IDs to attempt to bootload. The - * first image to pass verification will be bootloaded. - * @param[in] length Length of the slotIds array - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range - ******************************************************************************/ -int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length); - -/***************************************************************************//** - * Get the prioritized list of images the bootloader will attempt to bootload. - * - * @param[out] slotIds Prioritized list of slot IDs to attempt to bootload. The - * first image to pass verification will be bootloaded. - * @param[in] length Length of the slotIds array - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range - ******************************************************************************/ -int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length); - -/***************************************************************************//** - * Append a single image to the list of images to attempt to bootload. - * - * @param[in] slotId ID of the slot to append - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range - ******************************************************************************/ -int32_t bootloader_appendImageToBootloadList(int32_t slotId); - -/***************************************************************************//** - * Set a single image to attempt to bootload. - * - * @param[in] slotId ID of the slot - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range - ******************************************************************************/ -int32_t bootloader_setImageToBootload(int32_t slotId); - -/***************************************************************************//** - * Initialize image verification. - * - * Initialize verification of an upgrade image stored in a bootloader storage - * slot. - * - * @note This function must be called before calling - * @ref bootloader_continueVerifyImage in a loop. - * - * @note The context pointer must point to memory allocated by the caller. - * The caller must ensure that the context pointer is 32 bit aligned. - * The required size of this context may depend on the version - * of the bootloader. The required size for the bootloader associated with - * this version of the application interface is given by the define - * @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE. - * - * @note Instead of calling @ref bootloader_initVerifyImage followed by - * @ref bootloader_continueVerifyImage, call - * @ref bootloader_verifyImage if no - * time-critical tasks are needed and sufficient stack space is - * available for the automatically allocated context. The purpose of the - * init-and-continue functions is to allow the caller to service system - * needs during verification. - * - * - * @param[in] slotId ID of the slot to check. - * @param context Pointer to memory used to hold the parser context. - * @param[in] contextSize Size of the context. An error is returned if the - * supplied context is too small. - * - * @return @ref BOOTLOADER_OK if the image parser was initialized, else error - * code. - ******************************************************************************/ -#if !defined(SL_TRUSTZONE_NONSECURE) -int32_t bootloader_initVerifyImage(uint32_t slotId, - void *context, - size_t contextSize); -#else -int32_t bootloader_initVerifyImage(uint32_t slotId); -#endif // SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Continue image verification. - * - * Continue verification of an upgrade image stored in a bootloader storage - * slot. - * - * @note This function must be called in a loop until anything other than - * @ref BOOTLOADER_ERROR_PARSE_CONTINUE is returned. - * - * @note @ref bootloader_initVerifyImage must be called before calling this - * function to reset the parser. - * - * @note Instead of calling @ref bootloader_initVerifyImage followed by - * @ref bootloader_continueVerifyImage, call - * @ref bootloader_verifyImage if no - * time-critical tasks are needed. The purpose of the - * init-and-continue functions is to allow the caller to service system - * needs during verification. - * - * - * @param context Pointer to a context structure that has - * been initialized by calling - * @ref bootloader_initVerifyImage() - * @param[in] metadataCallback Function pointer, which is called when - * the binary metadata in the image is currently - * verified. Set to NULL if not required. - * - * @return @ref BOOTLOADER_ERROR_PARSE_CONTINUE if parsing was successful, and - * the parser expects more data. @ref BOOTLOADER_ERROR_PARSE_SUCCESS if - * the parser has successfully parsed the image and it passes - * verification. Else error code. - ******************************************************************************/ -#if !defined(SL_TRUSTZONE_NONSECURE) -int32_t bootloader_continueVerifyImage(void *context, - BootloaderParserCallback_t metadataCallback); -#else -int32_t bootloader_continueVerifyImage(void); -#endif // SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Verify that the image in the given storage slot is valid. - * - * @param[in] slotId ID of the slot to check - * @param[in] metadataCallback Function pointer, which is called when - * binary metadata is present in the storage slot. - * Set to NULL if not required. - * - * @note This function allocates a context structure of the size given by - * @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE on the caller's - * stack. To manage memory and allocate the - * context elsewhere (on the heap, as a global variable, and so on), use - * @ref bootloader_initVerifyImage and @ref bootloader_continueVerifyImage - * functions instead. - * - * @return @ref BOOTLOADER_OK if the image is valid, else error code. - ******************************************************************************/ -#if !defined(SL_TRUSTZONE_NONSECURE) -int32_t bootloader_verifyImage(uint32_t slotId, - BootloaderParserCallback_t metadataCallback); -#else -int32_t bootloader_verifyImage(uint32_t slotId); -#endif // SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Get application and bootloader upgrade metadata from the storage slot. - * - * @param[in] slotId ID of the slot to check - * @param[out] appInfo Pointer to @ref ApplicationData_t struct - * @param[out] bootloaderVersion Pointer to an integer representing bootloader - * version - * - * @return @ref BOOTLOADER_OK if metadata was filled successfully - ******************************************************************************/ -int32_t bootloader_getImageInfo(uint32_t slotId, - ApplicationData_t *appInfo, - uint32_t *bootloaderVersion); - -/***************************************************************************//** - * Check whether the bootloader storage is busy. - * - * @return True if the storage is busy - ******************************************************************************/ -bool bootloader_storageIsBusy(void); - -#if !defined(SL_TRUSTZONE_NONSECURE) -/***************************************************************************//** - * Read raw data from storage. - * - * @param[in] address Address to start reading from - * @param[out] buffer Buffer to store the data - * @param[in] length Amount of data to read - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_readRawStorage(uint32_t address, - uint8_t *buffer, - size_t length); - -/***************************************************************************//** - * Write data to storage. - * - * @note - * If DMA-based MSC write is enabled on the bootloader, writing data from - * flash to flash is not supported on Series-1 devices. - * - * @param[in] address Address to start writing to - * @param[in] buffer Buffer to read data to write from - * @param[in] length Amount of data to write. Must be a multiple of 4. - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_writeRawStorage(uint32_t address, - uint8_t *buffer, - size_t length); - -/***************************************************************************//** - * Erase data from storage. - * - * @note Erasing storage must adhere to the limitations of the underlying - * storage medium, such as requiring full page erases. Use - * @ref bootloader_getStorageInfo to learn about the limitations of the - * configured storage medium. - * - * @param[in] address Address to start erasing from - * @param[in] length Length of data to erase - * - * @return @ref BOOTLOADER_OK on success, else error code in - * @ref BOOTLOADER_ERROR_STORAGE_BASE range - ******************************************************************************/ -int32_t bootloader_eraseRawStorage(uint32_t address, size_t length); -#endif // !SL_TRUSTZONE_NONSECURE - -/***************************************************************************//** - * Get allocated DMA channel for MSC write. - * - * @return A positive number channel. -1 if DMA-based MSC write - * is not enabled. Otherwise, the error code - * BOOTLOADER_ERROR_INIT_STORAGE. - ******************************************************************************/ -int32_t bootloader_getAllocatedDMAChannel(void); - -/** @} (end addtogroup StorageInterface) */ -/** @} (end addtogroup Interface) */ - -#endif // BTL_INTERFACE_STORAGE_H +/***************************************************************************//** + * @file + * @brief Application interface to the storage component of the bootloader. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef BTL_INTERFACE_STORAGE_H +#define BTL_INTERFACE_STORAGE_H + +#include +#include +#include + +// Get part series version. +#include "em_device.h" + +/***************************************************************************//** + * @addtogroup Interface + * @{ + * @addtogroup StorageInterface Application Storage Interface + * @brief Application interface for interfacing with the bootloader storage. + * @note These Bootloader APIs are not reentrant and should be wrapped in critical section + * where needed. + * @details The Storage Interface is only available on bootloaders that declare + * they support @ref BOOTLOADER_CAPABILITY_STORAGE. + * + * @li @ref bootloader_interface_example + * + * @n @section bootloader_interface_example Example + * + * @brief Snippet for the OTA use case: + * @verbatim + * ///OTA Example + * /// Assuming the user has an upgrade image downloaded which will be used to upgrade the application + * + * //Initialize the bootloader interface + * bootloader_init(); + * + * //Erase the storage slot in internal/SPI flash memory + * bootloader_eraseStorageSlot(0); + * + * //Write the upgrade image (GBL file data) to the slot. blinkGbl  uint8 array holding the GBL data in memory + * bootloader_writeStorage(0, 0, blinkGbl, sizeof(blinkGbl)); + * + * //Reboot into the bootloader to install the new image + * bootloader_rebootAndInstall(); + * + * The general flow for bootloader interface APIs from the application is: + * + * ///General flow + * + * //Initialize the bootloader interface + * bootloader_init(); + * + * //Interface API accesses + * …………… + * …………… + * …………… + * + * //De-initialize the bootloader interface + * bootloader_deinit(); + * @endverbatim + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Typedefs + +/// Possible storage types +typedef enum { + /// Storage backend is a SPI flash + SPIFLASH, + /// Storage backend is internal flash + INTERNAL_FLASH, + /// Storage backend is custom + CUSTOM_STORAGE +} BootloaderStorageType_t; + +/// Information about a storage slot +typedef struct { + /// Address of the slot. + uint32_t address; + /// Size of the slot. + uint32_t length; +} BootloaderStorageSlot_t; + +/// Information about the bootloader storage implementation +/// Note: From Gecko Bootloader version >= 2.1, +/// the pointer partType will only contain a zero value. +/// The partType variable can be used to find information +/// about the attached storage. +typedef struct { + /// The version of this data structure + uint16_t version; + /// A bitmask describing the capabilities of this particular storage + uint16_t capabilitiesMask; + /// Maximum time it takes to erase a page. (in milliseconds) + uint32_t pageEraseMs; + /// Maximum time it takes to erase the entire part. (in milliseconds) + uint32_t partEraseMs; + /// The size of a single erasable page in bytes + uint32_t pageSize; + /// The total size of the storage in bytes + uint32_t partSize; + /// Pointer to a string describing the attached storage + char *partDescription; + /// The number of bytes in a word for the storage + uint8_t wordSizeBytes; + /// Value representing the attached storage + uint32_t partType; +} BootloaderStorageImplementationInformation_t; + +/// Information about the bootloader storage \n +/// Note: The flashInfo variable is only usable with +/// Gecko Bootloader version >= 2.0. All previous versions of the +/// Gecko Bootloader do not support the flashInfo data field. +typedef struct { + /// The version of this data structure + uint32_t version; + /// The capabilities of the storage component + uint32_t capabilities; + /// Type of storage + BootloaderStorageType_t storageType; + /// Number of storage slots + uint32_t numStorageSlots; + /// A pointer to detailed information about the attached storage + BootloaderStorageImplementationInformation_t *info; + /// Detailed information about the attached storage(available for use only with Gecko Bootloader version >= 2.0) + BootloaderStorageImplementationInformation_t flashInfo; +} BootloaderStorageInformation_t; + +/// Erase status struct +typedef struct { + /// Address of the current page to be erased + uint32_t currentPageAddr; + /// The size of a single erasable page in bytes + uint32_t pageSize; + /// Information about a storage slot + BootloaderStorageSlot_t storageSlotInfo; +} BootloaderEraseStatus_t; + +/// Storage API accessible from the application +typedef struct BootloaderStorageFunctions { + /// Version of this struct + uint32_t version; + /// Get information about the storage -- capabilities, layout, configuration + void (*getInfo)(BootloaderStorageInformation_t *info); + /// Get information about storage slot -- size, location + int32_t (*getSlotInfo)(uint32_t slotId, BootloaderStorageSlot_t *slot); + /// Read bytes from slot into buffer + int32_t (*read)(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length); + /// Write bytes from buffer into slot + int32_t (*write)(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length); + /// Erase an entire slot + int32_t (*erase)(uint32_t slotId); + // ------------------------------ + /// Mark a list of slots for bootload + int32_t (*setImagesToBootload)(int32_t *slotIds, size_t length); + /// Mark a list of slots for bootload + int32_t (*getImagesToBootload)(int32_t *slotIds, size_t length); + /// Append a slot to bootload list + int32_t (*appendImageToBootloadList)(int32_t slotId); + // ------------------------------ + /// Start image parsing + int32_t (*initParseImage)(uint32_t slotId, + BootloaderParserContext_t *context, + size_t contextSize); + /// Continue image verification + int32_t (*verifyImage)(BootloaderParserContext_t *context, + BootloaderParserCallback_t metadataCallback); + /// Get app and bootloader upgrade information from storage slot + int32_t (*getImageInfo)(BootloaderParserContext_t *context, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion); + /// Check whether the bootloader storage is busy + bool (*isBusy)(void); + /// Read raw bytes from storage + int32_t (*readRaw)(uint32_t address, uint8_t *buffer, size_t length); + /// Write bytes to raw storage + int32_t (*writeRaw)(uint32_t address, uint8_t *buffer, size_t length); + /// Erase storage + int32_t (*eraseRaw)(uint32_t address, size_t length); + /// Get configured DMA channel + int32_t (*getDMAchannel)(void); +} BootloaderStorageFunctions_t; + +// ----------------------------------------------------------------------------- +// Defines + +/// Context size for bootloader verification context +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SEMAILBOX_PRESENT) +/// Context size(680) includes counter(16) plus stream_block(16 (block size) * 8 (Maximum blocks)) +#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (680) +#else +#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (568) +#endif +#else +#define BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE (384) +#endif + +/// Current version of the BootloaderStorageInformation_t struct +#define BOOTLOADER_STORAGE_INFO_VERSION (0x30000U) +/// Current version of the BootloaderStorageImplementationInformation_t struct +#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION (0x0210U) +/// Major version of the BootloaderStorageImplementationInformation_t struct +#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR (0x0200U) +/// Major version mask for @ref BOOTLOADER_STORAGE_IMPL_INFO_VERSION +#define BOOTLOADER_STORAGE_IMPL_INFO_VERSION_MAJOR_MASK (0xFF00U) + +/// Spiflash capability indicating that it supports erase +#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_ERASE_SUPPORTED (1 << 0) +/// @brief Spiflash capability indicating it requires full page erases before +/// new data can be written +#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_PAGE_ERASE_REQUIRED (1 << 1) +/// Spiflash capability indicating that the write function is blocking +#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_WRITE (1 << 2) +/// Spiflash capability indicating that the erase function is blocking +#define BOOTLOADER_STORAGE_IMPL_CAPABILITY_BLOCKING_ERASE (1 << 3) + +/// ISSI IS25LQ040B SPI Flash +#define BOOTLOADER_STORAGE_ISSI_IS25LQ040B (1U << 0) +/// ISSI IS25LQ020B SPI Flash +#define BOOTLOADER_STORAGE_ISSI_IS25LQ020B (1U << 1) +/// ISSI IS25LQ010B SPI Flash +#define BOOTLOADER_STORAGE_ISSI_IS25LQ010B (1U << 2) +/// ISSI IS25LQ512B SPI Flash +#define BOOTLOADER_STORAGE_ISSI_IS25LQ512B (1U << 3) +/// ISSI IS25LQ025B SPI Flash +#define BOOTLOADER_STORAGE_ISSI_IS25LQ025B (1U << 4) +/// Numonyx M25P16 SPI Flash +#define BOOTLOADER_STORAGE_NUMONYX_M25P16 (1U << 5) +/// Numonyx M25P80 SPI Flash +#define BOOTLOADER_STORAGE_NUMONYX_M25P80 (1U << 6) +/// Numonyx M25P40 SPI Flash +#define BOOTLOADER_STORAGE_NUMONYX_M25P40 (1U << 7) +/// Numonyx M25P20 SPI Flash +#define BOOTLOADER_STORAGE_NUMONYX_M25P20 (1U << 8) +/// Adesto AT25SF041 SPI Flash +#define BOOTLOADER_STORAGE_ADESTO_AT25SF041 (1U << 9) +/// Atmel AT25DF081A SPI Flash +#define BOOTLOADER_STORAGE_ATMEL_AT25DF081A (1U << 10) +/// Atmel AT25DF041A SPI Flash +#define BOOTLOADER_STORAGE_ATMEL_AT25DF041A (1U << 11) +/// Macronix MX25R6435F SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25R6435F (1U << 12) +/// Macronix MX25R6435F SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25R3235F (1U << 13) +/// Macronix MX25U1635E SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25U1635E (1U << 14) +/// Macronix MX25L1606E SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25L1606E (1U << 15) +/// Macronix MX25R8035F SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25R8035F (1U << 16) +/// Macronix MX25L8006E SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25L8006E (1U << 17) +/// Macronix MX25L4006E SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25L4006E (1U << 18) +/// Macronix MX25L2006E SPI Flash +#define BOOTLOADER_STORAGE_MACRONIX_MX25L2006E (1U << 19) +/// Winbond W25Q80BV SPI Flash +#define BOOTLOADER_STORAGE_WINBOND_W25Q80BV (1U << 20) +/// Winbond W25X20BV SPI Flash +#define BOOTLOADER_STORAGE_WINBOND_W25X20BV (1U << 21) +/// Spansion S25L208K SPI Flash +#define BOOTLOADER_STORAGE_SPANSION_S25FL208K (1U << 22) +/// Internal storage +#define BOOTLOADER_STORAGE_INTERNAL_STORAGE (1U << 30) +/// JEDEC Supported SPI Flash +#define BOOTLOADER_STORAGE_JEDEC (1U << 31) + +// ----------------------------------------------------------------------------- +// Functions + +/***************************************************************************//** + * Get information about the storage component. + * + * @param[out] info Information about the storage component. + ******************************************************************************/ +void bootloader_getStorageInfo(BootloaderStorageInformation_t *info); + +/***************************************************************************//** + * Get information about a storage slot. + * + * @param[in] slotId ID of the slot to get information about + * @param[out] slot Information about the storage slot + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_getStorageSlotInfo(uint32_t slotId, + BootloaderStorageSlot_t *slot); + +/***************************************************************************//** + * Read data from a storage slot. + * + * @param[in] slotId ID of the slot + * @param[in] offset Offset into the slot to start reading from + * @param[out] buffer Buffer to store the data + * @param[in] length Amount of data to read + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_readStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length); + +/***************************************************************************//** + * Write data to a storage slot. + * + * @note + * If DMA-based MSC write is enabled on the bootloader, writing data from + * flash to flash is not supported on Series-1 devices. DMA-based MSC write is + * enabled, both offset and buffer should be word aligned. In case the buffer + * is not aligned, the normal write procedure is used instead of DMA. + * + * @param[in] slotId ID of the slot + * @param[in] offset Offset into the slot to start writing to + * @param[in] buffer Buffer to read data to write from + * @param[in] length Amount of data to write. Must be a multiple of 4. + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_writeStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length); + +/***************************************************************************//** + * Erase and write data to a storage slot. + * + * @note This function automatically erases the following Flash page whenever + * the written data crosses a page boundary. In other words, the function + * can't be used to perform multiple sequential writes to the same + * address range unless the range starts at a page boundary. + * For a sequential write, the first call to this function should have + * a start address at a page boundary. Otherwise, the corresponding page + * of the starting address needs to be erased explicitly. If DMA-based + * MSC write is enabled on the bootloader, writing data from flash to + * flash is not supported on Series-1 devices. + * + * @param[in] slotId ID of the slot + * @param[in] offset Offset into the slot to start writing to + * @param[in] buffer Buffer to read data to write from + * @param[in] length Amount of data to write. Must be a multiple of 4. + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_eraseWriteStorage(uint32_t slotId, + uint32_t offset, + uint8_t *buffer, + size_t length); + +/***************************************************************************//** + * Erase all contents of a storage slot. + * + * @param[in] slotId ID of the slot + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_eraseStorageSlot(uint32_t slotId); + +/***************************************************************************//** + * Initialize chunked erase of a storage slot. + * + * @note This function must be called before calling + * @ref bootloader_chunkedEraseStorageSlot in a loop. + * + * @param[in] slotId ID of the slot + * @param[in] eraseStat Erase status struct + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_initChunkedEraseStorageSlot(uint32_t slotId, + BootloaderEraseStatus_t *eraseStat); + +/***************************************************************************//** + * Erase one page from a storage slot according to + * the struct BootloaderEraseStatus_t. + * + * @note @ref bootloader_initChunkedEraseStorageSlot must be called + * before calling this function, in order to prepare + * BootloaderEraseStatus_t. + * + * @note This can be called sequentially to, for example, erase all contents + * of a storage slot. + * + * @param[in] eraseStat Erase status struct + * + * @return @ref BOOTLOADER_ERROR_STORAGE_CONTINUE if erasing a page was + * successful. Erase can be continued by calling this function again. + * @ref BOOTLOADER_OK if the entire slot has been erased, + * else error code in @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_chunkedEraseStorageSlot(BootloaderEraseStatus_t *eraseStat); + +/***************************************************************************//** + * Set a prioritized list of images to attempt to bootload. The last call to + * this function determines which slot will be installed when + * @ref bootloader_rebootAndInstall is called. + * + * @param[in] slotIds Prioritized list of slot IDs to attempt to bootload. The + * first image to pass verification will be bootloaded. + * @param[in] length Length of the slotIds array + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range + ******************************************************************************/ +int32_t bootloader_setImagesToBootload(int32_t *slotIds, size_t length); + +/***************************************************************************//** + * Get the prioritized list of images the bootloader will attempt to bootload. + * + * @param[out] slotIds Prioritized list of slot IDs to attempt to bootload. The + * first image to pass verification will be bootloaded. + * @param[in] length Length of the slotIds array + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range + ******************************************************************************/ +int32_t bootloader_getImagesToBootload(int32_t *slotIds, size_t length); + +/***************************************************************************//** + * Append a single image to the list of images to attempt to bootload. + * + * @param[in] slotId ID of the slot to append + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range + ******************************************************************************/ +int32_t bootloader_appendImageToBootloadList(int32_t slotId); + +/***************************************************************************//** + * Set a single image to attempt to bootload. + * + * @param[in] slotId ID of the slot + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_BOOTLOAD_BASE range + ******************************************************************************/ +int32_t bootloader_setImageToBootload(int32_t slotId); + +/***************************************************************************//** + * Initialize image verification. + * + * Initialize verification of an upgrade image stored in a bootloader storage + * slot. + * + * @note This function must be called before calling + * @ref bootloader_continueVerifyImage in a loop. + * + * @note The context pointer must point to memory allocated by the caller. + * The caller must ensure that the context pointer is 32 bit aligned. + * The required size of this context may depend on the version + * of the bootloader. The required size for the bootloader associated with + * this version of the application interface is given by the define + * @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE. + * + * @note Instead of calling @ref bootloader_initVerifyImage followed by + * @ref bootloader_continueVerifyImage, call + * @ref bootloader_verifyImage if no + * time-critical tasks are needed and sufficient stack space is + * available for the automatically allocated context. The purpose of the + * init-and-continue functions is to allow the caller to service system + * needs during verification. + * + * + * @param[in] slotId ID of the slot to check. + * @param context Pointer to memory used to hold the parser context. + * @param[in] contextSize Size of the context. An error is returned if the + * supplied context is too small. + * + * @return @ref BOOTLOADER_OK if the image parser was initialized, else error + * code. + ******************************************************************************/ +#if !defined(SL_TRUSTZONE_NONSECURE) +int32_t bootloader_initVerifyImage(uint32_t slotId, + void *context, + size_t contextSize); +#else +int32_t bootloader_initVerifyImage(uint32_t slotId); +#endif // SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Continue image verification. + * + * Continue verification of an upgrade image stored in a bootloader storage + * slot. + * + * @note This function must be called in a loop until anything other than + * @ref BOOTLOADER_ERROR_PARSE_CONTINUE is returned. + * + * @note @ref bootloader_initVerifyImage must be called before calling this + * function to reset the parser. + * + * @note Instead of calling @ref bootloader_initVerifyImage followed by + * @ref bootloader_continueVerifyImage, call + * @ref bootloader_verifyImage if no + * time-critical tasks are needed. The purpose of the + * init-and-continue functions is to allow the caller to service system + * needs during verification. + * + * + * @param context Pointer to a context structure that has + * been initialized by calling + * @ref bootloader_initVerifyImage() + * @param[in] metadataCallback Function pointer, which is called when + * the binary metadata in the image is currently + * verified. Set to NULL if not required. + * + * @return @ref BOOTLOADER_ERROR_PARSE_CONTINUE if parsing was successful, and + * the parser expects more data. @ref BOOTLOADER_ERROR_PARSE_SUCCESS if + * the parser has successfully parsed the image and it passes + * verification. Else error code. + ******************************************************************************/ +#if !defined(SL_TRUSTZONE_NONSECURE) +int32_t bootloader_continueVerifyImage(void *context, + BootloaderParserCallback_t metadataCallback); +#else +int32_t bootloader_continueVerifyImage(void); +#endif // SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Verify that the image in the given storage slot is valid. + * + * @param[in] slotId ID of the slot to check + * @param[in] metadataCallback Function pointer, which is called when + * binary metadata is present in the storage slot. + * Set to NULL if not required. + * + * @note This function allocates a context structure of the size given by + * @ref BOOTLOADER_STORAGE_VERIFICATION_CONTEXT_SIZE on the caller's + * stack. To manage memory and allocate the + * context elsewhere (on the heap, as a global variable, and so on), use + * @ref bootloader_initVerifyImage and @ref bootloader_continueVerifyImage + * functions instead. + * + * @return @ref BOOTLOADER_OK if the image is valid, else error code. + ******************************************************************************/ +#if !defined(SL_TRUSTZONE_NONSECURE) +int32_t bootloader_verifyImage(uint32_t slotId, + BootloaderParserCallback_t metadataCallback); +#else +int32_t bootloader_verifyImage(uint32_t slotId); +#endif // SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Get application and bootloader upgrade metadata from the storage slot. + * + * @param[in] slotId ID of the slot to check + * @param[out] appInfo Pointer to @ref ApplicationData_t struct + * @param[out] bootloaderVersion Pointer to an integer representing bootloader + * version + * + * @return @ref BOOTLOADER_OK if metadata was filled successfully + ******************************************************************************/ +int32_t bootloader_getImageInfo(uint32_t slotId, + ApplicationData_t *appInfo, + uint32_t *bootloaderVersion); + +/***************************************************************************//** + * Check whether the bootloader storage is busy. + * + * @return True if the storage is busy + ******************************************************************************/ +bool bootloader_storageIsBusy(void); + +#if !defined(SL_TRUSTZONE_NONSECURE) +/***************************************************************************//** + * Read raw data from storage. + * + * @param[in] address Address to start reading from + * @param[out] buffer Buffer to store the data + * @param[in] length Amount of data to read + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_readRawStorage(uint32_t address, + uint8_t *buffer, + size_t length); + +/***************************************************************************//** + * Write data to storage. + * + * @note + * If DMA-based MSC write is enabled on the bootloader, writing data from + * flash to flash is not supported on Series-1 devices. + * + * @param[in] address Address to start writing to + * @param[in] buffer Buffer to read data to write from + * @param[in] length Amount of data to write. Must be a multiple of 4. + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_writeRawStorage(uint32_t address, + uint8_t *buffer, + size_t length); + +/***************************************************************************//** + * Erase data from storage. + * + * @note Erasing storage must adhere to the limitations of the underlying + * storage medium, such as requiring full page erases. Use + * @ref bootloader_getStorageInfo to learn about the limitations of the + * configured storage medium. + * + * @param[in] address Address to start erasing from + * @param[in] length Length of data to erase + * + * @return @ref BOOTLOADER_OK on success, else error code in + * @ref BOOTLOADER_ERROR_STORAGE_BASE range + ******************************************************************************/ +int32_t bootloader_eraseRawStorage(uint32_t address, size_t length); +#endif // !SL_TRUSTZONE_NONSECURE + +/***************************************************************************//** + * Get allocated DMA channel for MSC write. + * + * @return A positive number channel. -1 if DMA-based MSC write + * is not enabled. Otherwise, the error code + * BOOTLOADER_ERROR_INIT_STORAGE. + ******************************************************************************/ +int32_t bootloader_getAllocatedDMAChannel(void); + +/** @} (end addtogroup StorageInterface) */ +/** @} (end addtogroup Interface) */ + +#endif // BTL_INTERFACE_STORAGE_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_reset_info.h b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_reset_info.h index 3d7f868..6f30015 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_reset_info.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/api/btl_reset_info.h @@ -1,97 +1,97 @@ -/***************************************************************************//** - * @file - * @brief Reset information for the Silicon Labs Gecko bootloader - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ -#ifndef BTL_RESET_INFO_H -#define BTL_RESET_INFO_H - -#include - -/***************************************************************************//** - * @addtogroup Interface - * @{ - * @addtogroup CommonInterface - * @{ - * @addtogroup ResetInterface Reset Information - * @brief Passing information when resetting into and out of the bootloader - * @details - * To signal the bootloader to run, the - * application needs to write the @ref BootloaderResetCause_t structure - * to the first address of RAM, setting @ref BootloaderResetCause_t.reason - * to @ref BOOTLOADER_RESET_REASON_BOOTLOAD. - * - * The reset cause is only valid if @ref BootloaderResetCause_t.signature - * is set to @ref BOOTLOADER_RESET_SIGNATURE_VALID. - * @code BootloaderResetCause_t resetCause = { - * .reason = BOOTLOADER_RESET_REASON_BOOTLOAD, - * .signature = BOOTLOADER_RESET_SIGNATURE_VALID - * } @endcode - * - * When the bootloader reboots back into the app, it sets the reset - * reason to @ref BOOTLOADER_RESET_REASON_GO if the bootload succeeded, - * or @ref BOOTLOADER_RESET_REASON_BADIMAGE if the bootload failed due - * to errors when parsing the upgrade image. - * - * @note - * The reset information is automatically filled out before reset if the - * @ref bootloader_rebootAndInstall function is called. - * @{ - ******************************************************************************/ - -/// Reset cause of the bootloader -typedef struct { - /// Reset reason as defined in the [reset information](@ref ResetInterface) - uint16_t reason; - /// Signature indicating whether the reset reason is valid - uint16_t signature; -} BootloaderResetCause_t; - -/// Unknown bootloader cause (should never occur) -#define BOOTLOADER_RESET_REASON_UNKNOWN 0x0200u -/// Bootloader caused reset telling app to run -#define BOOTLOADER_RESET_REASON_GO 0x0201u -/// Application requested that bootloader runs -#define BOOTLOADER_RESET_REASON_BOOTLOAD 0x0202u -/// Bootloader detected bad external upgrade image -#define BOOTLOADER_RESET_REASON_BADIMAGE 0x0203u -/// Fatal Error or assert in bootloader -#define BOOTLOADER_RESET_REASON_FATAL 0x0204u -/// Forced bootloader activation -#define BOOTLOADER_RESET_REASON_FORCE 0x0205u -/// OTA Bootloader mode activation -#define BOOTLOADER_RESET_REASON_OTAVALID 0x0206u -/// Bootloader initiated deep sleep -#define BOOTLOADER_RESET_REASON_DEEPSLEEP 0x0207u -/// Application verification failed -#define BOOTLOADER_RESET_REASON_BADAPP 0x0208u -/// Bootloader requested that first stage upgrades main bootloader -#define BOOTLOADER_RESET_REASON_UPGRADE 0x0209u -/// Bootloader timed out waiting for upgrade image -#define BOOTLOADER_RESET_REASON_TIMEOUT 0x020Au -/// Soft-reset was forced to handle a fault -#define BOOTLOADER_RESET_REASON_FAULT 0x020Bu -/// Soft-reset was forced to handle a security fault -#define BOOTLOADER_RESET_REASON_TZ_FAULT 0x020Cu - -/// Reset signature is valid -#define BOOTLOADER_RESET_SIGNATURE_VALID 0xF00Fu -/// Reset signature is invalid -#define BOOTLOADER_RESET_SIGNATURE_INVALID 0xC33Cu - -/** @} (end addtogroup ResetInterface) */ -/** @} (end addtogroup CommonInterface) */ -/** @} (end addtogroup Interface) */ - -#endif // BTL_RESET_INFO_H +/***************************************************************************//** + * @file + * @brief Reset information for the Silicon Labs Gecko bootloader + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ +#ifndef BTL_RESET_INFO_H +#define BTL_RESET_INFO_H + +#include + +/***************************************************************************//** + * @addtogroup Interface + * @{ + * @addtogroup CommonInterface + * @{ + * @addtogroup ResetInterface Reset Information + * @brief Passing information when resetting into and out of the bootloader + * @details + * To signal the bootloader to run, the + * application needs to write the @ref BootloaderResetCause_t structure + * to the first address of RAM, setting @ref BootloaderResetCause_t.reason + * to @ref BOOTLOADER_RESET_REASON_BOOTLOAD. + * + * The reset cause is only valid if @ref BootloaderResetCause_t.signature + * is set to @ref BOOTLOADER_RESET_SIGNATURE_VALID. + * @code BootloaderResetCause_t resetCause = { + * .reason = BOOTLOADER_RESET_REASON_BOOTLOAD, + * .signature = BOOTLOADER_RESET_SIGNATURE_VALID + * } @endcode + * + * When the bootloader reboots back into the app, it sets the reset + * reason to @ref BOOTLOADER_RESET_REASON_GO if the bootload succeeded, + * or @ref BOOTLOADER_RESET_REASON_BADIMAGE if the bootload failed due + * to errors when parsing the upgrade image. + * + * @note + * The reset information is automatically filled out before reset if the + * @ref bootloader_rebootAndInstall function is called. + * @{ + ******************************************************************************/ + +/// Reset cause of the bootloader +typedef struct { + /// Reset reason as defined in the [reset information](@ref ResetInterface) + uint16_t reason; + /// Signature indicating whether the reset reason is valid + uint16_t signature; +} BootloaderResetCause_t; + +/// Unknown bootloader cause (should never occur) +#define BOOTLOADER_RESET_REASON_UNKNOWN 0x0200u +/// Bootloader caused reset telling app to run +#define BOOTLOADER_RESET_REASON_GO 0x0201u +/// Application requested that bootloader runs +#define BOOTLOADER_RESET_REASON_BOOTLOAD 0x0202u +/// Bootloader detected bad external upgrade image +#define BOOTLOADER_RESET_REASON_BADIMAGE 0x0203u +/// Fatal Error or assert in bootloader +#define BOOTLOADER_RESET_REASON_FATAL 0x0204u +/// Forced bootloader activation +#define BOOTLOADER_RESET_REASON_FORCE 0x0205u +/// OTA Bootloader mode activation +#define BOOTLOADER_RESET_REASON_OTAVALID 0x0206u +/// Bootloader initiated deep sleep +#define BOOTLOADER_RESET_REASON_DEEPSLEEP 0x0207u +/// Application verification failed +#define BOOTLOADER_RESET_REASON_BADAPP 0x0208u +/// Bootloader requested that first stage upgrades main bootloader +#define BOOTLOADER_RESET_REASON_UPGRADE 0x0209u +/// Bootloader timed out waiting for upgrade image +#define BOOTLOADER_RESET_REASON_TIMEOUT 0x020Au +/// Soft-reset was forced to handle a fault +#define BOOTLOADER_RESET_REASON_FAULT 0x020Bu +/// Soft-reset was forced to handle a security fault +#define BOOTLOADER_RESET_REASON_TZ_FAULT 0x020Cu + +/// Reset signature is valid +#define BOOTLOADER_RESET_SIGNATURE_VALID 0xF00Fu +/// Reset signature is invalid +#define BOOTLOADER_RESET_SIGNATURE_INVALID 0xC33Cu + +/** @} (end addtogroup ResetInterface) */ +/** @} (end addtogroup CommonInterface) */ +/** @} (end addtogroup Interface) */ + +#endif // BTL_RESET_INFO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/app_properties/app_properties.c b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/app_properties/app_properties.c index fb1b909..9a971b7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/app_properties/app_properties.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/bootloader/app_properties/app_properties.c @@ -1,49 +1,49 @@ -/***************************************************************************//** - * @file - * @brief Application Properties Source File - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifdef APP_PROPERTIES_CONFIG_FILE -#include APP_PROPERTIES_CONFIG_FILE -#else -#include "app_properties_config.h" -#endif - -const ApplicationProperties_t sl_app_properties = { - .magic = APPLICATION_PROPERTIES_MAGIC, - .structVersion = APPLICATION_PROPERTIES_VERSION, - .signatureType = SL_APPLICATION_SIGNATURE, - .signatureLocation = SL_APPLICATION_SIGNATURE_LOCATION, - .app = { - .type = SL_APPLICATION_TYPE, - .version = SL_APPLICATION_VERSION, - .capabilities = SL_APPLICATION_CAPABILITIES, - .productId = SL_APPLICATION_PRODUCT_ID - }, - .cert = 0, - .longTokenSectionAddress = 0 -}; +/***************************************************************************//** + * @file + * @brief Application Properties Source File + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifdef APP_PROPERTIES_CONFIG_FILE +#include APP_PROPERTIES_CONFIG_FILE +#else +#include "app_properties_config.h" +#endif + +const ApplicationProperties_t sl_app_properties = { + .magic = APPLICATION_PROPERTIES_MAGIC, + .structVersion = APPLICATION_PROPERTIES_VERSION, + .signatureType = SL_APPLICATION_SIGNATURE, + .signatureLocation = SL_APPLICATION_SIGNATURE_LOCATION, + .app = { + .type = SL_APPLICATION_TYPE, + .version = SL_APPLICATION_VERSION, + .capabilities = SL_APPLICATION_CAPABILITIES, + .productId = SL_APPLICATION_PRODUCT_ID + }, + .cert = 0, + .longTokenSectionAddress = 0 +}; diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h index 6747fc7..ae493ef 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_assert.h @@ -1,99 +1,99 @@ -/***************************************************************************//** - * @file - * @brief API "assert" implementation. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_ASSERT_H -#define SL_ASSERT_H - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(DOXY_DOC_ONLY) -/** Included for documentation purposes only. This define is not present by default. - * DEBUG_EFM should be defined from the compiler to enable the default internal - * assert handler. */ -#define DEBUG_EFM -#endif - -#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) -/***************************************************************************//** - * @addtogroup assert ASSERT - Assert - * @brief Assert/error checking module - * @details - * By default, library assert usage is not included to reduce - * footprint and processing overhead. Further, assert usage is decoupled - * from ISO C assert handling (NDEBUG usage) to allow using ISO C - * assert without including assert statements. - * - * Below are available defines for controlling assert inclusion. The defines - * are typically for a project to be used by the preprocessor. - * - * @li If DEBUG_EFM is defined, the internal library assert handling will - * be used. This is implemented as a simple while(true) loop. DEBUG_EFM is not - * defined by default. - * - * @li If DEBUG_EFM_USER is defined, the user must provide custom - * implementation of the assertEFM() function. - * - * @li If both DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() - * statements are not operational. - * - * @note - * The internal assert is documented because DEBUG_EFM is defined in - * the doxygen configuration. - * @{ - ******************************************************************************/ -/* Due to footprint considerations, we only pass file name and line number, */ -/* not the assert expression (nor function name (C99)) */ -/***************************************************************************//** - * @brief - * Assert function for EFM. - * @param[in] file - path and file name of the assert. - * - * @param[in] line - line number, in the file. - ******************************************************************************/ -void assertEFM(const char *file, int line); -/** Default assertion is not operational */ -#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) - -#else - -/** Default assertion is not operational */ -#define EFM_ASSERT(expr) ((void)(expr)) - -#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ - -/** @} (end addtogroup assert) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_ASSERT_H */ +/***************************************************************************//** + * @file + * @brief API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_ASSERT_H +#define SL_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(DOXY_DOC_ONLY) +/** Included for documentation purposes only. This define is not present by default. + * DEBUG_EFM should be defined from the compiler to enable the default internal + * assert handler. */ +#define DEBUG_EFM +#endif + +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) +/***************************************************************************//** + * @addtogroup assert ASSERT - Assert + * @brief Assert/error checking module + * @details + * By default, library assert usage is not included to reduce + * footprint and processing overhead. Further, assert usage is decoupled + * from ISO C assert handling (NDEBUG usage) to allow using ISO C + * assert without including assert statements. + * + * Below are available defines for controlling assert inclusion. The defines + * are typically for a project to be used by the preprocessor. + * + * @li If DEBUG_EFM is defined, the internal library assert handling will + * be used. This is implemented as a simple while(true) loop. DEBUG_EFM is not + * defined by default. + * + * @li If DEBUG_EFM_USER is defined, the user must provide custom + * implementation of the assertEFM() function. + * + * @li If both DEBUG_EFM and DEBUG_EFM_USER are undefined, all EFM_ASSERT() + * statements are not operational. + * + * @note + * The internal assert is documented because DEBUG_EFM is defined in + * the doxygen configuration. + * @{ + ******************************************************************************/ +/* Due to footprint considerations, we only pass file name and line number, */ +/* not the assert expression (nor function name (C99)) */ +/***************************************************************************//** + * @brief + * Assert function for EFM. + * @param[in] file - path and file name of the assert. + * + * @param[in] line - line number, in the file. + ******************************************************************************/ +void assertEFM(const char *file, int line); +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((expr) ? ((void)0) : assertEFM(__FILE__, __LINE__)) + +#else + +/** Default assertion is not operational */ +#define EFM_ASSERT(expr) ((void)(expr)) + +#endif /* defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) */ + +/** @} (end addtogroup assert) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_ASSERT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h index d3a51ec..8a12995 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_atomic.h @@ -1,80 +1,80 @@ -/******************************************************************************* - * @file - * @brief Implementation of atomic operations. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_ATOMIC_H -#define SL_ATOMIC_H - -/******************************************************************************* - * @addtogroup atomic Atomic Operations - * @brief Atomic operations provide RAM store and read functionalities. - * @n @section atomic_usage Atomic Operations Usage - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Perform an atomic load. Use when a variable must be read from - * RAM. - * - * @param dest Variable where to copy the loaded value. - * - * @param source Variable from where to load the value. - * - * @note Does only support native types <= 32 bits. - * - * @note Load operation on 32 bit value is atomic on ARM architecture. - * - * @note Only the load operation from 'source' is guaranteed to be - * performed atomically. If writing to 'dest' implies a store, - * the load and store operations are not guaranteed to be - * performed atomically. - ******************************************************************************/ -#define sl_atomic_load(dest, source) ((dest) = (source)) - -/******************************************************************************* - * @brief Perform an atomic store. Use when a value must be stored in - * RAM. - * - * @param dest Variable where to store the value. - * - * @param source Variable that contains the value to store in 'dest'. - * - * @note Does only support native types <= 32 bits. - * - * @note Store operation on 32 bit value is atomic on ARM architecture. - * - * @note Only the store operation to 'dest' is guaranteed to be - * performed atomically. If reading from 'source' implies a load, - * the store and load operations are not guaranteed to be - * performed atomically. - ******************************************************************************/ -#define sl_atomic_store(dest, source) ((dest) = (source)) - -/** @} (end addtogroup atomic) */ - -#endif /* SL_ATOMIC_H */ +/******************************************************************************* + * @file + * @brief Implementation of atomic operations. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ATOMIC_H +#define SL_ATOMIC_H + +/******************************************************************************* + * @addtogroup atomic Atomic Operations + * @brief Atomic operations provide RAM store and read functionalities. + * @n @section atomic_usage Atomic Operations Usage + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Perform an atomic load. Use when a variable must be read from + * RAM. + * + * @param dest Variable where to copy the loaded value. + * + * @param source Variable from where to load the value. + * + * @note Does only support native types <= 32 bits. + * + * @note Load operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the load operation from 'source' is guaranteed to be + * performed atomically. If writing to 'dest' implies a store, + * the load and store operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_load(dest, source) ((dest) = (source)) + +/******************************************************************************* + * @brief Perform an atomic store. Use when a value must be stored in + * RAM. + * + * @param dest Variable where to store the value. + * + * @param source Variable that contains the value to store in 'dest'. + * + * @note Does only support native types <= 32 bits. + * + * @note Store operation on 32 bit value is atomic on ARM architecture. + * + * @note Only the store operation to 'dest' is guaranteed to be + * performed atomically. If reading from 'source' implies a load, + * the store and load operations are not guaranteed to be + * performed atomically. + ******************************************************************************/ +#define sl_atomic_store(dest, source) ((dest) = (source)) + +/** @} (end addtogroup atomic) */ + +#endif /* SL_ATOMIC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_common.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_common.h index f5621a7..33d2671 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_common.h @@ -1,385 +1,385 @@ -/***************************************************************************//** - * @file - * @brief General purpose utilities. - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_COMMON_H -#define SL_COMMON_H - -#include -#include -#include "sl_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__STATIC_INLINE) -#if !defined(__unix__) && defined(__arm__) -/* Compiler agnostic definitions */ -#include "cmsis_compiler.h" -#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) -#define __STATIC_INLINE static inline -#else -#warning Please provide a macro for your compiler and architecture -#define __STATIC_INLINE static -#endif -#endif - -/***************************************************************************//** - * @addtogroup common COMMON - Common Utilities - * @brief General purpose utilities and cross-compiler support - * @details - * This SDK supports the following compilers/IDEs: - * @li Simplicity Studio - * @li IAR Embedded Workbench - * @li Keil uVision IDE - * @li Plain armgcc - * - * Certain compiler features such as alignment is implemented differently in the tools. - * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent - * code. - * - * @note RAM code macros are implemented in [RAMFUNC](/gecko-platform//emlib-efm32g/). - * Cross-compiler RAM code support needs extended documentation and it is therefore - * implemented as a separate module. - * - * @{ - ******************************************************************************/ - -/** @brief Macros to concatenate. */ -#define SL_CONCAT_PASTER_2(first, second) first ## second ///< sl concat paster 2. -#define SL_CONCAT_PASTER_3(first, second, third) first ## second ## third ///< sl concat paster 3. -#define SL_CONCAT_PASTER_4(first, second, third, fourth) first ## second ## third ## fourth ///< sl concat paster 4. - -/** @brief Round n up to closest interval of i. */ -#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) - -/** @brief Round n down to closest interval of i. */ -#define SL_FLOOR(n, i) ((n / i) * i) - -/** @brief Stringify X */ -#define STRINGIZE(X) #X - -#if !defined(__GNUC__) -/* Not GCC compilers */ - -/** @brief Macro for getting minimum value. */ -#define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) - -/** @brief Macro for getting maximum value. */ -#define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) - -/** @brief Macros for handling packed structures. */ -#define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) -#define SL_PACK_END() _Pragma("pack()") -#define SL_ATTRIBUTE_PACKED - -#if defined(__CC_ARM) -/** @brief MDK-ARM compiler: Macros for handling aligned structures. */ -#define SL_ALIGN(X) __align(X) - -/** MDK-ARM compiler: Macro for handling weak symbols. */ -#define SL_WEAK __attribute__ ((weak)) - -/** MDK-ARM compiler: Macro for handling non-returning functions. */ -#define SL_NORETURN __attribute__ ((noreturn)) - -/** MDK-ARM compiler: Macro for handling section placement */ -#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) -#endif - -#if defined(__ICCARM__) - -#if (__VER__ >= 8000000) -/** @brief Obsoleted macro from version 8.00 and on . */ -#define _STD_BEGIN -/** @brief Obsoleted macro from version 8.00 and on . */ -#define _STD_END -#endif - -/** @brief IAR Embedded Workbench: Macros for handling aligned structures. */ -#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) - -/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ -#define SL_WEAK __weak - -/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ -#define SL_NORETURN __noreturn - -/* *INDENT-OFF* */ -/** IAR Embedded Workbench: Macro for handling section placement */ -#define SL_ATTRIBUTE_SECTION(X) @ X -#endif -/* *INDENT-ON* */ - -#define SL_ATTRIBUTE_ALIGN(X) - -/** @brief Macro for notifying the compiler of an intended - * switch case fallthrough. */ -#define SL_FALLTHROUGH - -/** @brief A macro for notifying the compiler to ignore type limit check. */ -#define SL_IGNORE_TYPE_LIMIT_BEGIN -#define SL_IGNORE_TYPE_LIMIT_END - -#else // !defined(__GNUC__) -/* GCC compilers */ - -/** @brief A macro for getting the minimum value. No side-effects, a and b are evaluated one time only. */ -#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) - -/** @brief A macro for getting the maximum value. No side-effects, a and b are evaluated one time only. */ -#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) - -/** @brief A GCC style macro for handling packed structures. */ -#define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) - -/** @brief A macro for handling packed structures. - * @n Use this macro before the structure definition. - * @n X denotes the maximum alignment of structure members. X is not supported with - * GCC. GCC always uses 1 byte maximum alignment. - */ -#define SL_PACK_START(x) - -/** @brief A macro for handling packed structures. - * @n Use this macro after the structure definition. - * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure - * definition. - */ -#define SL_PACK_END() - -/** @brief GCC style macro for aligning a variable. */ -#define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) - -/** @brief A macro for aligning a variable. - * @n Use this macro before the variable definition. - * @n X denotes the storage alignment value in bytes. - * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal - * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. - */ -#define SL_ALIGN(X) - -/** @brief A macro for defining a weak symbol. */ -#define SL_WEAK __attribute__ ((weak)) - -/** @brief A macro for handling non-returning functions. */ -#define SL_NORETURN __attribute__ ((noreturn)) - -/** A macro for placing a variable in a section. - * @n Use this macro after the variable definition, before the equal sign or a semicolon. - * @n X denotes the section to place the variable in. - */ -#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) - -/** @brief A macro for notifying the compiler of an intended - * switch case fallthrough. */ -#if __GNUC__ >= 7 - #define SL_FALLTHROUGH __attribute__ ((fallthrough)); -#else - #define SL_FALLTHROUGH -#endif - -/** @brief A macro for notifying the compiler to ignore type limit check. */ -#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) - #define SL_IGNORE_TYPE_LIMIT_BEGIN \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wtype-limits\"") - #define SL_IGNORE_TYPE_LIMIT_END \ - _Pragma("GCC diagnostic pop") -#else - #define SL_IGNORE_TYPE_LIMIT_BEGIN - #define SL_IGNORE_TYPE_LIMIT_END ///< A MACRO to notify the compiler, limit END. -#endif - -#endif // !defined(__GNUC__) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** @brief - * Macro for marking deprecated functions - * - * @details - * SL_DEPRECATED_API_SDK_ is used to mark functions that are - * deprecated and should not be used from a given version of the SDK. - * The accompanying SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_ - * define can be set to suppress warnings generated when using - * deprecated APIs. - */ -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_0 -#define SL_DEPRECATED_API_SDK_3_0 -#else -#define SL_DEPRECATED_API_SDK_3_0 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_2 -#define SL_DEPRECATED_API_SDK_3_2 -#else -#define SL_DEPRECATED_API_SDK_3_2 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_3 -#define SL_DEPRECATED_API_SDK_3_3 -#else -#define SL_DEPRECATED_API_SDK_3_3 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_1 -#define SL_DEPRECATED_API_SDK_4_1 -#else -#define SL_DEPRECATED_API_SDK_4_1 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_2 -#define SL_DEPRECATED_API_SDK_4_2 -#else -#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated)) -#endif - -#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4 -#define SL_DEPRECATED_API_SDK_4_4 -#else -#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated)) -#endif -/** @endcond */ - -/***************************************************************************//** - * @brief - * Count trailing number of zeros. Use CLZ instruction if available. - * - * @param[in] value - * Data value to check for number of trailing zero bits. - * - * @return - * A number of trailing zeros in value. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_CTZ(uint32_t value) -{ -#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) - return __CLZ(__RBIT(value)); - -#else - uint32_t zeros; - for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { - ; - } - return zeros; -#endif -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated function. New code should use @ref SL_CTZ. */ -__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) -{ - return SL_CTZ(value); -} -/** @endcond */ - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * Data value to reverse. - * - * @return - * A reversed value. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_RBIT(uint32_t value) -{ - uint32_t result; - -#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) - result = __RBIT(value); -#else - int32_t s = 4 * 8 - 1; - - result = value; - for (value >>= 1U; value != 0U; value >>= 1U) { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; -#endif - return result; -} - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * 16-bit data value to reverse. - * - * @return - * A 16-bit reversed value. - ******************************************************************************/ -__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) -{ - return (uint16_t)(SL_RBIT(value) >> 16); -} - -/***************************************************************************//** - * @brief - * Reverse the bits. Use the RBIT instruction if available, else process. - * - * @param[in] value - * 8-bit data value to reverse. - * - * @return - * A 8-bit reversed value. - ******************************************************************************/ -__STATIC_INLINE uint8_t SL_RBIT8(uint8_t value) -{ - return (uint8_t)(SL_RBIT(value) >> 24); -} - -/***************************************************************************//** - * @brief - * Convert logarithm of 2 to division factor. - * - * @param[in] log2 - * Logarithm of 2. - * - * @return - * Dividend. - ******************************************************************************/ -__STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) -{ - EFM_ASSERT(log2 < 32U); - return 1UL << log2; -} - -/** @} (end addtogroup common) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_COMMON_H */ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_COMMON_H +#define SL_COMMON_H + +#include +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__STATIC_INLINE) +#if !defined(__unix__) && defined(__arm__) +/* Compiler agnostic definitions */ +#include "cmsis_compiler.h" +#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) +#define __STATIC_INLINE static inline +#else +#warning Please provide a macro for your compiler and architecture +#define __STATIC_INLINE static +#endif +#endif + +/***************************************************************************//** + * @addtogroup common COMMON - Common Utilities + * @brief General purpose utilities and cross-compiler support + * @details + * This SDK supports the following compilers/IDEs: + * @li Simplicity Studio + * @li IAR Embedded Workbench + * @li Keil uVision IDE + * @li Plain armgcc + * + * Certain compiler features such as alignment is implemented differently in the tools. + * Therefore, macros such as @ref SL_ALIGN are provided to enable compiler independent + * code. + * + * @note RAM code macros are implemented in [RAMFUNC](/gecko-platform//emlib-efm32g/). + * Cross-compiler RAM code support needs extended documentation and it is therefore + * implemented as a separate module. + * + * @{ + ******************************************************************************/ + +/** @brief Macros to concatenate. */ +#define SL_CONCAT_PASTER_2(first, second) first ## second ///< sl concat paster 2. +#define SL_CONCAT_PASTER_3(first, second, third) first ## second ## third ///< sl concat paster 3. +#define SL_CONCAT_PASTER_4(first, second, third, fourth) first ## second ## third ## fourth ///< sl concat paster 4. + +/** @brief Round n up to closest interval of i. */ +#define SL_CEILING(n, i) ((((n) + (i) - 1U) / (i)) * (i)) + +/** @brief Round n down to closest interval of i. */ +#define SL_FLOOR(n, i) ((n / i) * i) + +/** @brief Stringify X */ +#define STRINGIZE(X) #X + +#if !defined(__GNUC__) +/* Not GCC compilers */ + +/** @brief Macro for getting minimum value. */ +#define SL_MIN(a, b) ((a) < (b) ? (a) : (b)) + +/** @brief Macro for getting maximum value. */ +#define SL_MAX(a, b) ((a) > (b) ? (a) : (b)) + +/** @brief Macros for handling packed structures. */ +#define SL_PACK_START(X) _Pragma(STRINGIZE(pack(X))) +#define SL_PACK_END() _Pragma("pack()") +#define SL_ATTRIBUTE_PACKED + +#if defined(__CC_ARM) +/** @brief MDK-ARM compiler: Macros for handling aligned structures. */ +#define SL_ALIGN(X) __align(X) + +/** MDK-ARM compiler: Macro for handling weak symbols. */ +#define SL_WEAK __attribute__ ((weak)) + +/** MDK-ARM compiler: Macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** MDK-ARM compiler: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) +#endif + +#if defined(__ICCARM__) + +#if (__VER__ >= 8000000) +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_BEGIN +/** @brief Obsoleted macro from version 8.00 and on . */ +#define _STD_END +#endif + +/** @brief IAR Embedded Workbench: Macros for handling aligned structures. */ +#define SL_ALIGN(X) _Pragma(STRINGIZE(data_alignment = X)) + +/** @brief IAR Embedded Workbench: Macros for handling weak symbols. */ +#define SL_WEAK __weak + +/** @brief IAR Embedded Workbench: Macro for handling non-returning functions. */ +#define SL_NORETURN __noreturn + +/* *INDENT-OFF* */ +/** IAR Embedded Workbench: Macro for handling section placement */ +#define SL_ATTRIBUTE_SECTION(X) @ X +#endif +/* *INDENT-ON* */ + +#define SL_ATTRIBUTE_ALIGN(X) + +/** @brief Macro for notifying the compiler of an intended + * switch case fallthrough. */ +#define SL_FALLTHROUGH + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#define SL_IGNORE_TYPE_LIMIT_BEGIN +#define SL_IGNORE_TYPE_LIMIT_END + +#else // !defined(__GNUC__) +/* GCC compilers */ + +/** @brief A macro for getting the minimum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MIN(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a < _b ? _a : _b; }) + +/** @brief A macro for getting the maximum value. No side-effects, a and b are evaluated one time only. */ +#define SL_MAX(a, b) __extension__({ __typeof__(a)_a = (a); __typeof__(b)_b = (b); _a > _b ? _a : _b; }) + +/** @brief A GCC style macro for handling packed structures. */ +#define SL_ATTRIBUTE_PACKED __attribute__ ((packed)) + +/** @brief A macro for handling packed structures. + * @n Use this macro before the structure definition. + * @n X denotes the maximum alignment of structure members. X is not supported with + * GCC. GCC always uses 1 byte maximum alignment. + */ +#define SL_PACK_START(x) + +/** @brief A macro for handling packed structures. + * @n Use this macro after the structure definition. + * @n With GCC, add SL_ATTRIBUTE_PACKED after the closing curly braces of the structure + * definition. + */ +#define SL_PACK_END() + +/** @brief GCC style macro for aligning a variable. */ +#define SL_ATTRIBUTE_ALIGN(X) __attribute__ ((aligned(X))) + +/** @brief A macro for aligning a variable. + * @n Use this macro before the variable definition. + * @n X denotes the storage alignment value in bytes. + * @n To be GCC-compatible, use SL_ATTRIBUTE_ALIGN(X) before the semicolon on normal + * variables. Use SL_ATTRIBUTE_ALIGN(X) before the opening curly brace on structure variables. + */ +#define SL_ALIGN(X) + +/** @brief A macro for defining a weak symbol. */ +#define SL_WEAK __attribute__ ((weak)) + +/** @brief A macro for handling non-returning functions. */ +#define SL_NORETURN __attribute__ ((noreturn)) + +/** A macro for placing a variable in a section. + * @n Use this macro after the variable definition, before the equal sign or a semicolon. + * @n X denotes the section to place the variable in. + */ +#define SL_ATTRIBUTE_SECTION(X) __attribute__ ((section(X))) + +/** @brief A macro for notifying the compiler of an intended + * switch case fallthrough. */ +#if __GNUC__ >= 7 + #define SL_FALLTHROUGH __attribute__ ((fallthrough)); +#else + #define SL_FALLTHROUGH +#endif + +/** @brief A macro for notifying the compiler to ignore type limit check. */ +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6) + #define SL_IGNORE_TYPE_LIMIT_BEGIN \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wtype-limits\"") + #define SL_IGNORE_TYPE_LIMIT_END \ + _Pragma("GCC diagnostic pop") +#else + #define SL_IGNORE_TYPE_LIMIT_BEGIN + #define SL_IGNORE_TYPE_LIMIT_END ///< A MACRO to notify the compiler, limit END. +#endif + +#endif // !defined(__GNUC__) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** @brief + * Macro for marking deprecated functions + * + * @details + * SL_DEPRECATED_API_SDK_ is used to mark functions that are + * deprecated and should not be used from a given version of the SDK. + * The accompanying SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_ + * define can be set to suppress warnings generated when using + * deprecated APIs. + */ +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_0 +#define SL_DEPRECATED_API_SDK_3_0 +#else +#define SL_DEPRECATED_API_SDK_3_0 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_2 +#define SL_DEPRECATED_API_SDK_3_2 +#else +#define SL_DEPRECATED_API_SDK_3_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_3_3 +#define SL_DEPRECATED_API_SDK_3_3 +#else +#define SL_DEPRECATED_API_SDK_3_3 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_1 +#define SL_DEPRECATED_API_SDK_4_1 +#else +#define SL_DEPRECATED_API_SDK_4_1 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_2 +#define SL_DEPRECATED_API_SDK_4_2 +#else +#define SL_DEPRECATED_API_SDK_4_2 __attribute__ ((deprecated)) +#endif + +#ifdef SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_4_4 +#define SL_DEPRECATED_API_SDK_4_4 +#else +#define SL_DEPRECATED_API_SDK_4_4 __attribute__ ((deprecated)) +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Count trailing number of zeros. Use CLZ instruction if available. + * + * @param[in] value + * Data value to check for number of trailing zero bits. + * + * @return + * A number of trailing zeros in value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_CTZ(uint32_t value) +{ +#if defined(__CORTEX_M) && (__CORTEX_M >= 3U) + return __CLZ(__RBIT(value)); + +#else + uint32_t zeros; + for (zeros = 0; (zeros < 32) && ((value & 0x1) == 0); zeros++, value >>= 1) { + ; + } + return zeros; +#endif +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated function. New code should use @ref SL_CTZ. */ +__STATIC_INLINE uint32_t EFM32_CTZ(uint32_t value) +{ + return SL_CTZ(value); +} +/** @endcond */ + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * Data value to reverse. + * + * @return + * A reversed value. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_RBIT(uint32_t value) +{ + uint32_t result; + +#if defined(__CORTEX_M) && (__CORTEX_M >= 0x03U) + result = __RBIT(value); +#else + int32_t s = 4 * 8 - 1; + + result = value; + for (value >>= 1U; value != 0U; value >>= 1U) { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; +#endif + return result; +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 16-bit data value to reverse. + * + * @return + * A 16-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint16_t SL_RBIT16(uint16_t value) +{ + return (uint16_t)(SL_RBIT(value) >> 16); +} + +/***************************************************************************//** + * @brief + * Reverse the bits. Use the RBIT instruction if available, else process. + * + * @param[in] value + * 8-bit data value to reverse. + * + * @return + * A 8-bit reversed value. + ******************************************************************************/ +__STATIC_INLINE uint8_t SL_RBIT8(uint8_t value) +{ + return (uint8_t)(SL_RBIT(value) >> 24); +} + +/***************************************************************************//** + * @brief + * Convert logarithm of 2 to division factor. + * + * @param[in] log2 + * Logarithm of 2. + * + * @return + * Dividend. + ******************************************************************************/ +__STATIC_INLINE uint32_t SL_Log2ToDiv(uint32_t log2) +{ + EFM_ASSERT(log2 < 32U); + return 1UL << log2; +} + +/** @} (end addtogroup common) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h index e7e33bb..4240564 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_enum.h @@ -1,66 +1,66 @@ -/******************************************************************************* - * @file - * @brief SL_ENUM Implementation - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_ENUM_H -#define SL_ENUM_H - -/******************************************************************************* - * @addtogroup enum Enumerations - * @brief Enumerations with stable binary representation - * @details - * Silicon Labs libraries do not use enumerations because the ARM EABI leaves - * their size ambiguous, which causes problems if the application is built - * with different flags than the library. Instead, uint8_t typedefs - * are used in compiled code for all enumerations. For documentation purposes, - * this is converted to an actual enumeration in documentation. - * @{ - ******************************************************************************/ - -#ifdef DOXYGEN -/// Enumeration mapped to uint8_t -#define SL_ENUM(name) enum name -/// Enumeration mapped to arbitrary type -#define SL_ENUM_GENERIC(name, type) enum name -#else -// NOTE: The following macros might cause MISRA warnings because -// Macro parameters need to be enclosed in parentheses. -// However, it is not possible in C to enclose declaration -// identifiers in parentheses. For example: -// typedef uint8_t (some_identifier); -// is not syntactically correct in the C language (C99). -#define SL_ENUM(name) typedef uint8_t name; enum name##_enum -#define SL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum - -// For debugging, use the following define to turn this back into a proper enumeration -// #define SL_ENUM(name) typedef enum name##_enum name; enum name##_enum -#endif - -/** @} end enum */ - -#endif // SL_ENUM_H +/******************************************************************************* + * @file + * @brief SL_ENUM Implementation + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_ENUM_H +#define SL_ENUM_H + +/******************************************************************************* + * @addtogroup enum Enumerations + * @brief Enumerations with stable binary representation + * @details + * Silicon Labs libraries do not use enumerations because the ARM EABI leaves + * their size ambiguous, which causes problems if the application is built + * with different flags than the library. Instead, uint8_t typedefs + * are used in compiled code for all enumerations. For documentation purposes, + * this is converted to an actual enumeration in documentation. + * @{ + ******************************************************************************/ + +#ifdef DOXYGEN +/// Enumeration mapped to uint8_t +#define SL_ENUM(name) enum name +/// Enumeration mapped to arbitrary type +#define SL_ENUM_GENERIC(name, type) enum name +#else +// NOTE: The following macros might cause MISRA warnings because +// Macro parameters need to be enclosed in parentheses. +// However, it is not possible in C to enclose declaration +// identifiers in parentheses. For example: +// typedef uint8_t (some_identifier); +// is not syntactically correct in the C language (C99). +#define SL_ENUM(name) typedef uint8_t name; enum name##_enum +#define SL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum + +// For debugging, use the following define to turn this back into a proper enumeration +// #define SL_ENUM(name) typedef enum name##_enum name; enum name##_enum +#endif + +/** @} end enum */ + +#endif // SL_ENUM_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_slist.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_slist.h index 7a5d4c4..f54704e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_slist.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_slist.h @@ -1,153 +1,153 @@ -/******************************************************************************* - * @file - * @brief Single Link List. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SLIST_H -#define SL_SLIST_H - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * @addtogroup slist Singly-Linked List - * @brief Singly-linked List module provides APIs to handle singly-linked list - * operations such as insert, push, pop, push back, sort and remove. - * - * @note The pop operation follows FIFO method. - * @n @section slist_usage Singly-Linked List module Usage - * @{ - ******************************************************************************/ - -/// List node type -typedef struct sl_slist_node sl_slist_node_t; - -/// List node -struct sl_slist_node { - sl_slist_node_t *node; ///< List node -}; - -#ifndef DOXYGEN -#define container_of(ptr, type, member) (type *)((uintptr_t)(ptr) - ((uintptr_t)(&((type *)0)->member))) - -#define SL_SLIST_ENTRY container_of - -#define SL_SLIST_FOR_EACH(list_head, iterator) for ((iterator) = (list_head); (iterator) != NULL; (iterator) = (iterator)->node) - -#define SL_SLIST_FOR_EACH_ENTRY(list_head, entry, type, member) for ( (entry) = SL_SLIST_ENTRY(list_head, type, member); \ - (type *)(entry) != SL_SLIST_ENTRY(NULL, type, member); \ - (entry) = SL_SLIST_ENTRY((entry)->member.node, type, member)) -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/******************************************************************************* - * Initialize a singly-linked list. - * - * @param head Pointer to pointer of head element of list. - ******************************************************************************/ -void sl_slist_init(sl_slist_node_t **head); - -/******************************************************************************* - * Add given item at beginning of the list. - * - * @param head Pointer to pointer of head element of the list. - * - * @param item Pointer to an item to add. - ******************************************************************************/ -void sl_slist_push(sl_slist_node_t **head, - sl_slist_node_t *item); - -/******************************************************************************* - * Add item at the end of the list. - * - * @param head Pointer to the pointer of a head element of the list. - * - * @param item Pointer to the item to add. - ******************************************************************************/ -void sl_slist_push_back(sl_slist_node_t **head, - sl_slist_node_t *item); - -/******************************************************************************* - * Remove and return the first element of the list. - * - * @param head Pointer to he pointer of the head element of the list. - * - * @return Pointer to item that was at top of the list. - ******************************************************************************/ -sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head); - -/******************************************************************************* - * Insert an item after the given item. - * - * @param item Pointer to an item to add. - * - * @param pos Pointer to an item after which the item to add will be inserted. - ******************************************************************************/ -void sl_slist_insert(sl_slist_node_t *item, - sl_slist_node_t *pos); - -/******************************************************************************* - * Remove an item from the list. - * - * @param head Pointer to pointer of the head element of list. - * - * @param item Pointer to the item to remove. - * - * @note (1) An EFM_ASSERT is thrown if the item is not found within the list. - ******************************************************************************/ -void sl_slist_remove(sl_slist_node_t **head, - sl_slist_node_t *item); - -/******************************************************************************* - * Sort list items. - * - * @param head Pointer to the pointer of the head element of the list. - * - * @param cmp_fnct Pointer to function to use for sorting the list. - * item_l Pointer to left item. - * item_r Pointer to right item. - * Returns whether the two items are ordered (true) or not (false). - ******************************************************************************/ -void sl_slist_sort(sl_slist_node_t **head, - bool (*cmp_fnct)(sl_slist_node_t *item_l, - sl_slist_node_t *item_r)); - -/** @} (end addtogroup slist) */ - -#ifdef __cplusplus -} -#endif - -#endif /* SL_SLIST_H */ +/******************************************************************************* + * @file + * @brief Single Link List. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SLIST_H +#define SL_SLIST_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * @addtogroup slist Singly-Linked List + * @brief Singly-linked List module provides APIs to handle singly-linked list + * operations such as insert, push, pop, push back, sort and remove. + * + * @note The pop operation follows FIFO method. + * @n @section slist_usage Singly-Linked List module Usage + * @{ + ******************************************************************************/ + +/// List node type +typedef struct sl_slist_node sl_slist_node_t; + +/// List node +struct sl_slist_node { + sl_slist_node_t *node; ///< List node +}; + +#ifndef DOXYGEN +#define container_of(ptr, type, member) (type *)((uintptr_t)(ptr) - ((uintptr_t)(&((type *)0)->member))) + +#define SL_SLIST_ENTRY container_of + +#define SL_SLIST_FOR_EACH(list_head, iterator) for ((iterator) = (list_head); (iterator) != NULL; (iterator) = (iterator)->node) + +#define SL_SLIST_FOR_EACH_ENTRY(list_head, entry, type, member) for ( (entry) = SL_SLIST_ENTRY(list_head, type, member); \ + (type *)(entry) != SL_SLIST_ENTRY(NULL, type, member); \ + (entry) = SL_SLIST_ENTRY((entry)->member.node, type, member)) +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/******************************************************************************* + * Initialize a singly-linked list. + * + * @param head Pointer to pointer of head element of list. + ******************************************************************************/ +void sl_slist_init(sl_slist_node_t **head); + +/******************************************************************************* + * Add given item at beginning of the list. + * + * @param head Pointer to pointer of head element of the list. + * + * @param item Pointer to an item to add. + ******************************************************************************/ +void sl_slist_push(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Add item at the end of the list. + * + * @param head Pointer to the pointer of a head element of the list. + * + * @param item Pointer to the item to add. + ******************************************************************************/ +void sl_slist_push_back(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Remove and return the first element of the list. + * + * @param head Pointer to he pointer of the head element of the list. + * + * @return Pointer to item that was at top of the list. + ******************************************************************************/ +sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head); + +/******************************************************************************* + * Insert an item after the given item. + * + * @param item Pointer to an item to add. + * + * @param pos Pointer to an item after which the item to add will be inserted. + ******************************************************************************/ +void sl_slist_insert(sl_slist_node_t *item, + sl_slist_node_t *pos); + +/******************************************************************************* + * Remove an item from the list. + * + * @param head Pointer to pointer of the head element of list. + * + * @param item Pointer to the item to remove. + * + * @note (1) An EFM_ASSERT is thrown if the item is not found within the list. + ******************************************************************************/ +void sl_slist_remove(sl_slist_node_t **head, + sl_slist_node_t *item); + +/******************************************************************************* + * Sort list items. + * + * @param head Pointer to the pointer of the head element of the list. + * + * @param cmp_fnct Pointer to function to use for sorting the list. + * item_l Pointer to left item. + * item_r Pointer to right item. + * Returns whether the two items are ordered (true) or not (false). + ******************************************************************************/ +void sl_slist_sort(sl_slist_node_t **head, + bool (*cmp_fnct)(sl_slist_node_t *item_l, + sl_slist_node_t *item_r)); + +/** @} (end addtogroup slist) */ + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SLIST_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_status.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_status.h index 83a4338..f81a8d3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_status.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/inc/sl_status.h @@ -1,452 +1,452 @@ -/******************************************************************************* - * @file - * @brief SL Status Codes. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_STATUS_H -#define SL_STATUS_H - -#include - -/******************************************************************************* - * @addtogroup status Status Codes - * @details Status Codes contains error and status code definitions used by GSDK - * software components and stacks. This module also provides routines to - * read the string linked with the error and status codes. - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Space Defines - -#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask. - -#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space. - -#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space. -#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space. -#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space. - -#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space. -#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space. -#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space. -#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space. -#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space. -#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space. -#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space. -#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space. -#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space. -#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space. - -#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space. -#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space. - -#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space. -#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space. -#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space. -#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space. - -#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space. - -#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space. - -// ----------------------------------------------------------------------------- -// Status Defines - -// ----------------------------------------------------------------------------- -// Generic Errors - -#define SL_STATUS_OK ((sl_status_t)0x0000) ///< No error. -#define SL_STATUS_FAIL ((sl_status_t)0x0001) ///< Generic error. - -// State Errors -#define SL_STATUS_INVALID_STATE ((sl_status_t)0x0002) ///< Generic invalid state error. -#define SL_STATUS_NOT_READY ((sl_status_t)0x0003) ///< Module is not ready for requested operation. -#define SL_STATUS_BUSY ((sl_status_t)0x0004) ///< Module is busy and cannot carry out requested operation. -#define SL_STATUS_IN_PROGRESS ((sl_status_t)0x0005) ///< Operation is in progress and not yet complete (pass or fail). -#define SL_STATUS_ABORT ((sl_status_t)0x0006) ///< Operation aborted. -#define SL_STATUS_TIMEOUT ((sl_status_t)0x0007) ///< Operation timed out. -#define SL_STATUS_PERMISSION ((sl_status_t)0x0008) ///< Operation not allowed per permissions. -#define SL_STATUS_WOULD_BLOCK ((sl_status_t)0x0009) ///< Non-blocking operation would block. -#define SL_STATUS_IDLE ((sl_status_t)0x000A) ///< Operation/module is Idle, cannot carry requested operation. -#define SL_STATUS_IS_WAITING ((sl_status_t)0x000B) ///< Operation cannot be done while construct is waiting. -#define SL_STATUS_NONE_WAITING ((sl_status_t)0x000C) ///< No task/construct waiting/pending for that action/event. -#define SL_STATUS_SUSPENDED ((sl_status_t)0x000D) ///< Operation cannot be done while construct is suspended. -#define SL_STATUS_NOT_AVAILABLE ((sl_status_t)0x000E) ///< Feature not available due to software configuration. -#define SL_STATUS_NOT_SUPPORTED ((sl_status_t)0x000F) ///< Feature not supported. -#define SL_STATUS_INITIALIZATION ((sl_status_t)0x0010) ///< Initialization failed. -#define SL_STATUS_NOT_INITIALIZED ((sl_status_t)0x0011) ///< Module has not been initialized. -#define SL_STATUS_ALREADY_INITIALIZED ((sl_status_t)0x0012) ///< Module has already been initialized. -#define SL_STATUS_DELETED ((sl_status_t)0x0013) ///< Object/construct has been deleted. -#define SL_STATUS_ISR ((sl_status_t)0x0014) ///< Illegal call from ISR. -#define SL_STATUS_NETWORK_UP ((sl_status_t)0x0015) ///< Illegal call because network is up. -#define SL_STATUS_NETWORK_DOWN ((sl_status_t)0x0016) ///< Illegal call because network is down. -#define SL_STATUS_NOT_JOINED ((sl_status_t)0x0017) ///< Failure due to not being joined in a network. -#define SL_STATUS_NO_BEACONS ((sl_status_t)0x0018) ///< Invalid operation as there are no beacons. - -// Allocation/ownership Errors -#define SL_STATUS_ALLOCATION_FAILED ((sl_status_t)0x0019) ///< Generic allocation error. -#define SL_STATUS_NO_MORE_RESOURCE ((sl_status_t)0x001A) ///< No more resource available to perform the operation. -#define SL_STATUS_EMPTY ((sl_status_t)0x001B) ///< Item/list/queue is empty. -#define SL_STATUS_FULL ((sl_status_t)0x001C) ///< Item/list/queue is full. -#define SL_STATUS_WOULD_OVERFLOW ((sl_status_t)0x001D) ///< Item would overflow. -#define SL_STATUS_HAS_OVERFLOWED ((sl_status_t)0x001E) ///< Item/list/queue has been overflowed. -#define SL_STATUS_OWNERSHIP ((sl_status_t)0x001F) ///< Generic ownership error. -#define SL_STATUS_IS_OWNER ((sl_status_t)0x0020) ///< Already/still owning resource. - -// Invalid Parameters Errors -#define SL_STATUS_INVALID_PARAMETER ((sl_status_t)0x0021) ///< Generic invalid argument or consequence of invalid argument. -#define SL_STATUS_NULL_POINTER ((sl_status_t)0x0022) ///< Invalid null pointer received as argument. -#define SL_STATUS_INVALID_CONFIGURATION ((sl_status_t)0x0023) ///< Invalid configuration provided. -#define SL_STATUS_INVALID_MODE ((sl_status_t)0x0024) ///< Invalid mode. -#define SL_STATUS_INVALID_HANDLE ((sl_status_t)0x0025) ///< Invalid handle. -#define SL_STATUS_INVALID_TYPE ((sl_status_t)0x0026) ///< Invalid type for operation. -#define SL_STATUS_INVALID_INDEX ((sl_status_t)0x0027) ///< Invalid index. -#define SL_STATUS_INVALID_RANGE ((sl_status_t)0x0028) ///< Invalid range. -#define SL_STATUS_INVALID_KEY ((sl_status_t)0x0029) ///< Invalid key. -#define SL_STATUS_INVALID_CREDENTIALS ((sl_status_t)0x002A) ///< Invalid credentials. -#define SL_STATUS_INVALID_COUNT ((sl_status_t)0x002B) ///< Invalid count. -#define SL_STATUS_INVALID_SIGNATURE ((sl_status_t)0x002C) ///< Invalid signature / verification failed. -#define SL_STATUS_NOT_FOUND ((sl_status_t)0x002D) ///< Item could not be found. -#define SL_STATUS_ALREADY_EXISTS ((sl_status_t)0x002E) ///< Item already exists. - -// IO/Communication Errors -#define SL_STATUS_IO ((sl_status_t)0x002F) ///< Generic I/O failure. -#define SL_STATUS_IO_TIMEOUT ((sl_status_t)0x0030) ///< I/O failure due to timeout. -#define SL_STATUS_TRANSMIT ((sl_status_t)0x0031) ///< Generic transmission error. -#define SL_STATUS_TRANSMIT_UNDERFLOW ((sl_status_t)0x0032) ///< Transmit underflowed. -#define SL_STATUS_TRANSMIT_INCOMPLETE ((sl_status_t)0x0033) ///< Transmit is incomplete. -#define SL_STATUS_TRANSMIT_BUSY ((sl_status_t)0x0034) ///< Transmit is busy. -#define SL_STATUS_RECEIVE ((sl_status_t)0x0035) ///< Generic reception error. -#define SL_STATUS_OBJECT_READ ((sl_status_t)0x0036) ///< Failed to read on/via given object. -#define SL_STATUS_OBJECT_WRITE ((sl_status_t)0x0037) ///< Failed to write on/via given object. -#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long. - -// EEPROM/Flash Errors -#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch. -#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch. -#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited. -#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed. -#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed. -#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed. - -// MAC Errors -#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data. -#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received. -#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout. -#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type. -#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type. -#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure. - -// CLI_STORAGE Errors -#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM - -// Security status codes -#define SL_STATUS_SECURITY_IMAGE_CHECKSUM_ERROR ((sl_status_t)0x0046) ///< Image checksum is not valid. -#define SL_STATUS_SECURITY_DECRYPT_ERROR ((sl_status_t)0x0047) ///< Decryption failed - -// Command status codes -#define SL_STATUS_COMMAND_IS_INVALID ((sl_status_t)0x0048) ///< Command was not recognized -#define SL_STATUS_COMMAND_TOO_LONG ((sl_status_t)0x0049) ///< Command or parameter maximum length exceeded -#define SL_STATUS_COMMAND_INCOMPLETE ((sl_status_t)0x004A) ///< Data received does not form a complete command - -// Misc Errors -#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address - -// Unified MAC Errors -#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure. - -// Scan errors -#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning. -#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type. -#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask. -#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration. - -// Bluetooth status codes -#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. -#define SL_STATUS_BT_UNSPECIFIED ((sl_status_t)0x0403) ///< Unspecified error -#define SL_STATUS_BT_HARDWARE ((sl_status_t)0x0404) ///< Hardware failure -#define SL_STATUS_BT_NO_BONDING ((sl_status_t)0x0406) ///< The bonding does not exist. -#define SL_STATUS_BT_CRYPTO ((sl_status_t)0x0407) ///< Error using crypto functions -#define SL_STATUS_BT_DATA_CORRUPTED ((sl_status_t)0x0408) ///< Data was corrupted. -#define SL_STATUS_BT_INVALID_SYNC_HANDLE ((sl_status_t)0x040A) ///< Invalid periodic advertising sync handle -#define SL_STATUS_BT_INVALID_MODULE_ACTION ((sl_status_t)0x040B) ///< Bluetooth cannot be used on this hardware -#define SL_STATUS_BT_RADIO ((sl_status_t)0x040C) ///< Error received from radio -#define SL_STATUS_BT_L2CAP_REMOTE_DISCONNECTED ((sl_status_t)0x040D) ///< Returned when remote disconnects the connection-oriented channel by sending disconnection request. -#define SL_STATUS_BT_L2CAP_LOCAL_DISCONNECTED ((sl_status_t)0x040E) ///< Returned when local host disconnect the connection-oriented channel by sending disconnection request. -#define SL_STATUS_BT_L2CAP_CID_NOT_EXIST ((sl_status_t)0x040F) ///< Returned when local host did not find a connection-oriented channel with given destination CID. -#define SL_STATUS_BT_L2CAP_LE_DISCONNECTED ((sl_status_t)0x0410) ///< Returned when connection-oriented channel disconnected due to LE connection is dropped. -#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_VIOLATED ((sl_status_t)0x0412) ///< Returned when connection-oriented channel disconnected due to remote end send data even without credit. -#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_CREDIT_OVERFLOWED ((sl_status_t)0x0413) ///< Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. -#define SL_STATUS_BT_L2CAP_NO_FLOW_CONTROL_CREDIT ((sl_status_t)0x0414) ///< Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. -#define SL_STATUS_BT_L2CAP_CONNECTION_REQUEST_TIMEOUT ((sl_status_t)0x0415) ///< Returned when connection-oriented channel has not received connection response message within maximum timeout. -#define SL_STATUS_BT_L2CAP_INVALID_CID ((sl_status_t)0x0416) ///< Returned when local host received a connection-oriented channel connection response with an invalid destination CID. -#define SL_STATUS_BT_L2CAP_WRONG_STATE ((sl_status_t)0x0417) ///< Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. -#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full -#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found -#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level -#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed. - -// Bluetooth controller status codes -#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled. -#define SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE ((sl_status_t)0x1005) ///< Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key -#define SL_STATUS_BT_CTRL_PIN_OR_KEY_MISSING ((sl_status_t)0x1006) ///< Pairing failed because of missing PIN, or authentication failed because of missing Key -#define SL_STATUS_BT_CTRL_MEMORY_CAPACITY_EXCEEDED ((sl_status_t)0x1007) ///< Controller is out of memory. -#define SL_STATUS_BT_CTRL_CONNECTION_TIMEOUT ((sl_status_t)0x1008) ///< Link supervision timeout has expired. -#define SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x1009) ///< Controller is at limit of connections it can support. -#define SL_STATUS_BT_CTRL_SYNCHRONOUS_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x100A) ///< The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. -#define SL_STATUS_BT_CTRL_ACL_CONNECTION_ALREADY_EXISTS ((sl_status_t)0x100B) ///< The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. -#define SL_STATUS_BT_CTRL_COMMAND_DISALLOWED ((sl_status_t)0x100C) ///< Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES ((sl_status_t)0x100D) ///< The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS ((sl_status_t)0x100E) ///< The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR ((sl_status_t)0x100F) ///< The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. -#define SL_STATUS_BT_CTRL_CONNECTION_ACCEPT_TIMEOUT_EXCEEDED ((sl_status_t)0x1010) ///< The Connection Accept Timeout has been exceeded for this connection attempt. -#define SL_STATUS_BT_CTRL_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE ((sl_status_t)0x1011) ///< A feature or parameter value in the HCI command is not supported. -#define SL_STATUS_BT_CTRL_INVALID_COMMAND_PARAMETERS ((sl_status_t)0x1012) ///< Command contained invalid parameters. -#define SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED ((sl_status_t)0x1013) ///< User on the remote device terminated the connection. -#define SL_STATUS_BT_CTRL_REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES ((sl_status_t)0x1014) ///< The remote device terminated the connection because of low resources -#define SL_STATUS_BT_CTRL_REMOTE_POWERING_OFF ((sl_status_t)0x1015) ///< Remote Device Terminated Connection due to Power Off -#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST ((sl_status_t)0x1016) ///< Local device terminated the connection. -#define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. -#define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing -#define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. -#define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. -#define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. -#define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. -#define SL_STATUS_BT_CTRL_ENCRYPTION_MODE_NOT_ACCEPTABLE ((sl_status_t)0x1025) ///< The requested encryption mode is not acceptable at this time. -#define SL_STATUS_BT_CTRL_LINK_KEY_CANNOT_BE_CHANGED ((sl_status_t)0x1026) ///< Link key cannot be changed because a fixed unit key is being used. -#define SL_STATUS_BT_CTRL_INSTANT_PASSED ((sl_status_t)0x1028) ///< LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. -#define SL_STATUS_BT_CTRL_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED ((sl_status_t)0x1029) ///< It was not possible to pair as a unit key was requested and it is not supported. -#define SL_STATUS_BT_CTRL_DIFFERENT_TRANSACTION_COLLISION ((sl_status_t)0x102A) ///< LMP transaction was started that collides with an ongoing transaction. -#define SL_STATUS_BT_CTRL_CHANNEL_ASSESSMENT_NOT_SUPPORTED ((sl_status_t)0x102E) ///< The Controller cannot perform channel assessment because it is not supported. -#define SL_STATUS_BT_CTRL_INSUFFICIENT_SECURITY ((sl_status_t)0x102F) ///< The HCI command or LMP PDU sent is only possible on an encrypted link. -#define SL_STATUS_BT_CTRL_PARAMETER_OUT_OF_MANDATORY_RANGE ((sl_status_t)0x1030) ///< A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. -#define SL_STATUS_BT_CTRL_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST ((sl_status_t)0x1037) ///< The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. -#define SL_STATUS_BT_CTRL_HOST_BUSY_PAIRING ((sl_status_t)0x1038) ///< The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. -#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation. -#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request. -#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval. -#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. -#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. -#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. -#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. -#define SL_STATUS_BT_CTRL_COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING ((sl_status_t)0x1040) ///< The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. -#define SL_STATUS_BT_CTRL_UNKNOWN_ADVERTISING_IDENTIFIER ((sl_status_t)0x1042) ///< A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. -#define SL_STATUS_BT_CTRL_LIMIT_REACHED ((sl_status_t)0x1043) ///< Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). -#define SL_STATUS_BT_CTRL_OPERATION_CANCELLED_BY_HOST ((sl_status_t)0x1044) ///< A request to the Controller issued by the Host and still pending was successfully canceled. -#define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. -#define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. -#define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. - -// Bluetooth attribute status codes -#define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server -#define SL_STATUS_BT_ATT_READ_NOT_PERMITTED ((sl_status_t)0x1102) ///< The attribute cannot be read -#define SL_STATUS_BT_ATT_WRITE_NOT_PERMITTED ((sl_status_t)0x1103) ///< The attribute cannot be written -#define SL_STATUS_BT_ATT_INVALID_PDU ((sl_status_t)0x1104) ///< The attribute PDU was invalid -#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHENTICATION ((sl_status_t)0x1105) ///< The attribute requires authentication before it can be read or written. -#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client. -#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute -#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written. -#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued -#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range. -#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request -#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient. -#define SL_STATUS_BT_ATT_INVALID_ATT_LENGTH ((sl_status_t)0x110D) ///< The attribute value length is invalid for the operation -#define SL_STATUS_BT_ATT_UNLIKELY_ERROR ((sl_status_t)0x110E) ///< The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. -#define SL_STATUS_BT_ATT_INSUFFICIENT_ENCRYPTION ((sl_status_t)0x110F) ///< The attribute requires encryption before it can be read or written. -#define SL_STATUS_BT_ATT_UNSUPPORTED_GROUP_TYPE ((sl_status_t)0x1110) ///< The attribute type is not a supported grouping attribute as defined by a higher layer specification. -#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request -#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database. -#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed. -#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. -#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions. -#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service. -#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress. -#define SL_STATUS_BT_ATT_OUT_OF_RANGE ((sl_status_t)0x11FF) ///< The attribute value is out of range as defined by a profile or service specification. - -// Bluetooth Security Manager Protocol status codes -#define SL_STATUS_BT_SMP_PASSKEY_ENTRY_FAILED ((sl_status_t)0x1201) ///< The user input of passkey failed, for example, the user cancelled the operation -#define SL_STATUS_BT_SMP_OOB_NOT_AVAILABLE ((sl_status_t)0x1202) ///< Out of Band data is not available for authentication -#define SL_STATUS_BT_SMP_AUTHENTICATION_REQUIREMENTS ((sl_status_t)0x1203) ///< The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices -#define SL_STATUS_BT_SMP_CONFIRM_VALUE_FAILED ((sl_status_t)0x1204) ///< The confirm value does not match the calculated compare value -#define SL_STATUS_BT_SMP_PAIRING_NOT_SUPPORTED ((sl_status_t)0x1205) ///< Pairing is not supported by the device -#define SL_STATUS_BT_SMP_ENCRYPTION_KEY_SIZE ((sl_status_t)0x1206) ///< The resultant encryption key size is insufficient for the security requirements of this device -#define SL_STATUS_BT_SMP_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1207) ///< The SMP command received is not supported on this device -#define SL_STATUS_BT_SMP_UNSPECIFIED_REASON ((sl_status_t)0x1208) ///< Pairing failed due to an unspecified reason -#define SL_STATUS_BT_SMP_REPEATED_ATTEMPTS ((sl_status_t)0x1209) ///< Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request -#define SL_STATUS_BT_SMP_INVALID_PARAMETERS ((sl_status_t)0x120A) ///< The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. -#define SL_STATUS_BT_SMP_DHKEY_CHECK_FAILED ((sl_status_t)0x120B) ///< Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. -#define SL_STATUS_BT_SMP_NUMERIC_COMPARISON_FAILED ((sl_status_t)0x120C) ///< Indicates that the confirm values in the numeric comparison protocol do not match. -#define SL_STATUS_BT_SMP_BREDR_PAIRING_IN_PROGRESS ((sl_status_t)0x120D) ///< Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. -#define SL_STATUS_BT_SMP_CROSS_TRANSPORT_KEY_DERIVATION_GENERATION_NOT_ALLOWED ((sl_status_t)0x120E) ///< Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. -#define SL_STATUS_BT_SMP_KEY_REJECTED ((sl_status_t)0x120F) ///< Indicates that the device chose not to accept a distributed key. - -// Bluetooth Mesh status codes -#define SL_STATUS_BT_MESH_ALREADY_EXISTS ((sl_status_t)0x0501) ///< Returned when trying to add a key or some other unique resource with an ID which already exists -#define SL_STATUS_BT_MESH_DOES_NOT_EXIST ((sl_status_t)0x0502) ///< Returned when trying to manipulate a key or some other resource with an ID which does not exist -#define SL_STATUS_BT_MESH_LIMIT_REACHED ((sl_status_t)0x0503) ///< Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached -#define SL_STATUS_BT_MESH_INVALID_ADDRESS ((sl_status_t)0x0504) ///< Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device -#define SL_STATUS_BT_MESH_MALFORMED_DATA ((sl_status_t)0x0505) ///< In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data -#define SL_STATUS_BT_MESH_ALREADY_INITIALIZED ((sl_status_t)0x0506) ///< An attempt was made to initialize a subsystem that was already initialized. -#define SL_STATUS_BT_MESH_NOT_INITIALIZED ((sl_status_t)0x0507) ///< An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. -#define SL_STATUS_BT_MESH_NO_FRIEND_OFFER ((sl_status_t)0x0508) ///< Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. -#define SL_STATUS_BT_MESH_PROV_LINK_CLOSED ((sl_status_t)0x0509) ///< Provisioning link was unexpectedly closed before provisioning was complete. -#define SL_STATUS_BT_MESH_PROV_INVALID_PDU ((sl_status_t)0x050A) ///< An unrecognized provisioning PDU was received. -#define SL_STATUS_BT_MESH_PROV_INVALID_PDU_FORMAT ((sl_status_t)0x050B) ///< A provisioning PDU with wrong length or containing field values that are out of bounds was received. -#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_PDU ((sl_status_t)0x050C) ///< An unexpected (out of sequence) provisioning PDU was received. -#define SL_STATUS_BT_MESH_PROV_CONFIRMATION_FAILED ((sl_status_t)0x050D) ///< The computed confirmation value did not match the expected value. -#define SL_STATUS_BT_MESH_PROV_OUT_OF_RESOURCES ((sl_status_t)0x050E) ///< Provisioning could not be continued due to insufficient resources. -#define SL_STATUS_BT_MESH_PROV_DECRYPTION_FAILED ((sl_status_t)0x050F) ///< The provisioning data block could not be decrypted. -#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_ERROR ((sl_status_t)0x0510) ///< An unexpected error happened during provisioning. -#define SL_STATUS_BT_MESH_PROV_CANNOT_ASSIGN_ADDR ((sl_status_t)0x0511) ///< Device could not assign unicast addresses to all of its elements. -#define SL_STATUS_BT_MESH_ADDRESS_TEMPORARILY_UNAVAILABLE ((sl_status_t)0x0512) ///< Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. -#define SL_STATUS_BT_MESH_ADDRESS_ALREADY_USED ((sl_status_t)0x0513) ///< Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. -#define SL_STATUS_BT_MESH_PUBLISH_NOT_CONFIGURED ((sl_status_t)0x0514) ///< Application key or publish address are not set -#define SL_STATUS_BT_MESH_APP_KEY_NOT_BOUND ((sl_status_t)0x0515) ///< Application key is not bound to a model - -// Bluetooth Mesh foundation status codes -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_ADDRESS ((sl_status_t)0x1301) ///< Returned when address in request was not valid -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_MODEL ((sl_status_t)0x1302) ///< Returned when model identified is not found for a given element -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_APP_KEY ((sl_status_t)0x1303) ///< Returned when the key identified by AppKeyIndex is not stored in the node -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_NET_KEY ((sl_status_t)0x1304) ///< Returned when the key identified by NetKeyIndex is not stored in the node -#define SL_STATUS_BT_MESH_FOUNDATION_INSUFFICIENT_RESOURCES ((sl_status_t)0x1305) ///< Returned when The node cannot serve the request due to insufficient resources -#define SL_STATUS_BT_MESH_FOUNDATION_KEY_INDEX_EXISTS ((sl_status_t)0x1306) ///< Returned when the key identified is already stored in the node and the new NetKey value is different -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_PUBLISH_PARAMS ((sl_status_t)0x1307) ///< Returned when the model does not support the publish mechanism -#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUBSCRIBE_MODEL ((sl_status_t)0x1308) ///< Returned when the model does not support the subscribe mechanism -#define SL_STATUS_BT_MESH_FOUNDATION_STORAGE_FAILURE ((sl_status_t)0x1309) ///< Returned when storing of the requested parameters failed -#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUPPORTED ((sl_status_t)0x130A) ///< Returned when requested setting is not supported -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_UPDATE ((sl_status_t)0x130B) ///< Returned when the requested update operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_REMOVE ((sl_status_t)0x130C) ///< Returned when the requested delete operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_BIND ((sl_status_t)0x130D) ///< Returned when the requested bind operation cannot be performed due to general constraints -#define SL_STATUS_BT_MESH_FOUNDATION_TEMPORARILY_UNABLE ((sl_status_t)0x130E) ///< Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached -#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_SET ((sl_status_t)0x130F) ///< Returned when the requested state cannot be set -#define SL_STATUS_BT_MESH_FOUNDATION_UNSPECIFIED ((sl_status_t)0x1310) ///< Returned when an unspecified error took place -#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_BINDING ((sl_status_t)0x1311) ///< Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update - -// ----------------------------------------------------------------------------- -// Wi-Fi Errors - -#define SL_STATUS_WIFI_INVALID_KEY ((sl_status_t)0x0B01) ///< Invalid firmware keyset -#define SL_STATUS_WIFI_FIRMWARE_DOWNLOAD_TIMEOUT ((sl_status_t)0x0B02) ///< The firmware download took too long -#define SL_STATUS_WIFI_UNSUPPORTED_MESSAGE_ID ((sl_status_t)0x0B03) ///< Unknown request ID or wrong interface ID used -#define SL_STATUS_WIFI_WARNING ((sl_status_t)0x0B04) ///< The request is successful but some parameters have been ignored -#define SL_STATUS_WIFI_NO_PACKET_TO_RECEIVE ((sl_status_t)0x0B05) ///< No Packets waiting to be received -#define SL_STATUS_WIFI_SLEEP_GRANTED ((sl_status_t)0x0B08) ///< The sleep mode is granted -#define SL_STATUS_WIFI_SLEEP_NOT_GRANTED ((sl_status_t)0x0B09) ///< The WFx does not go back to sleep -#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ERROR ((sl_status_t)0x0B10) ///< The SecureLink MAC key was not found -#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ALREADY_BURNED ((sl_status_t)0x0B11) ///< The SecureLink MAC key is already installed in OTP -#define SL_STATUS_WIFI_SECURE_LINK_RAM_MODE_NOT_ALLOWED ((sl_status_t)0x0B12) ///< The SecureLink MAC key cannot be installed in RAM -#define SL_STATUS_WIFI_SECURE_LINK_FAILED_UNKNOWN_MODE ((sl_status_t)0x0B13) ///< The SecureLink MAC key installation failed -#define SL_STATUS_WIFI_SECURE_LINK_EXCHANGE_FAILED ((sl_status_t)0x0B14) ///< SecureLink key (re)negotiation failed -#define SL_STATUS_WIFI_WRONG_STATE ((sl_status_t)0x0B18) ///< The device is in an inappropriate state to perform the request -#define SL_STATUS_WIFI_CHANNEL_NOT_ALLOWED ((sl_status_t)0x0B19) ///< The request failed due to regulatory limitations -#define SL_STATUS_WIFI_NO_MATCHING_AP ((sl_status_t)0x0B1A) ///< The connection request failed because no suitable AP was found -#define SL_STATUS_WIFI_CONNECTION_ABORTED ((sl_status_t)0x0B1B) ///< The connection request was aborted by host -#define SL_STATUS_WIFI_CONNECTION_TIMEOUT ((sl_status_t)0x0B1C) ///< The connection request failed because of a timeout -#define SL_STATUS_WIFI_CONNECTION_REJECTED_BY_AP ((sl_status_t)0x0B1D) ///< The connection request failed because the AP rejected the device -#define SL_STATUS_WIFI_CONNECTION_AUTH_FAILURE ((sl_status_t)0x0B1E) ///< The connection request failed because the WPA handshake did not complete successfully -#define SL_STATUS_WIFI_RETRY_EXCEEDED ((sl_status_t)0x0B1F) ///< The request failed because the retry limit was exceeded -#define SL_STATUS_WIFI_TX_LIFETIME_EXCEEDED ((sl_status_t)0x0B20) ///< The request failed because the MSDU life time was exceeded - -// ----------------------------------------------------------------------------- -// MVP Driver and MVP Math status codes -#define SL_STATUS_COMPUTE_DRIVER_FAULT ((sl_status_t)0x1501) ///< Critical fault -#define SL_STATUS_COMPUTE_DRIVER_ALU_NAN ((sl_status_t)0x1502) ///< ALU operation output NaN -#define SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW ((sl_status_t)0x1503) ///< ALU numeric overflow -#define SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW ((sl_status_t)0x1504) ///< ALU numeric underflow -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW ((sl_status_t)0x1505) ///< Overflow during array store -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW ((sl_status_t)0x1506) ///< Underflow during array store conversion -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion -#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion - -#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered -#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered -#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow -#define SL_STATUS_COMPUTE_MATH_UNDERFLOW ((sl_status_t)0x1515) ///< MATH numeric underflow - -// ----------------------------------------------------------------------------- -// Data Types -/** @brief define global status variable. */ -typedef uint32_t sl_status_t; - -// ----------------------------------------------------------------------------- -// Functions - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************************************** - * sl_status_get_string_n() - * - * @brief Get a copy of the status string associated to the status code passed, up to - * 'buffer_length' length, if the string associated to the status code is enabled. If not, - * the error code number, in hex, prefixed by "SL_STATUS_" will be copied in the buffer - * instead. - * For example, the buffer would either contain "SL_STATUS_FAIL" if that status string is - * enabled, or "SL_STATUS_0x0001" if the string is disabled, as SL_STATUS_FAIL's - * value is 0x0001. - * - * @param status The status code from which to obtain the status string. - * - * @param buffer Pointer to a buffer in which the status string will be copied. A terminating - * null-character will be appended after the copied status string. - * - * @param buffer_length Maximum number of characters that can be written in the buffer, including the - * terminating null-character. If the status string would be longer than the - * available length, it will be truncated and a null-terminating character will - * be the last character contained in the buffer. - * - * @return The number of characters that would have been written if the buffer_length had been - * sufficiently large, not counting the terminating null character. - * If the status code is invalid, 0 or a negative number is returned. - * Notice that only when this returned value is strictly positive and less than - * buffer_length, the status string has been completely written in the buffer. - *******************************************************************************************************/ -int32_t sl_status_get_string_n(sl_status_t status, char *buffer, uint32_t buffer_length); - -/******************************************************************************************************** - * sl_status_print() - * - * @brief Print, through printf, the string associated to the passed status code. If the string - * associated to the status code is enabled, the status string will be printed, for example - * "SL_STATUS_OK". If the string associated to the status code is disabled, the status number, - * in hex, prefixed by "SL_STATUS_" will be printed instead, for example "SL_STATUS_0x0000", - * as SL_STATUS_OK's value is 0x0000. - * - * @param status The status code of which to print the status string. - *******************************************************************************************************/ -void sl_status_print(sl_status_t status); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup status) */ - -#endif /* SL_STATUS_H */ +/******************************************************************************* + * @file + * @brief SL Status Codes. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_STATUS_H +#define SL_STATUS_H + +#include + +/******************************************************************************* + * @addtogroup status Status Codes + * @details Status Codes contains error and status code definitions used by GSDK + * software components and stacks. This module also provides routines to + * read the string linked with the error and status codes. + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Space Defines + +#define SL_STATUS_SPACE_MASK ((sl_status_t)0xFF00) ///< sl status space mask. + +#define SL_STATUS_GENERIC_SPACE ((sl_status_t)0x0000) ///< sl status generic space. + +#define SL_STATUS_PLATFORM_1_SPACE ((sl_status_t)0x0100) ///< sl status platform 1 space. +#define SL_STATUS_PLATFORM_2_SPACE ((sl_status_t)0x0200) ///< sl status platform 2 space. +#define SL_STATUS_HARDWARE_SPACE ((sl_status_t)0x0300) ///< sl status hardware space. + +#define SL_STATUS_BLUETOOTH_SPACE ((sl_status_t)0x0400) ///< sl status bluetooth space. +#define SL_STATUS_BLUETOOTH_MESH_SPACE ((sl_status_t)0x0500) ///< sl status bluetooth mesh space. +#define SL_STATUS_CAN_CANOPEN_SPACE ((sl_status_t)0x0600) ///< sl status can canopen space. +#define SL_STATUS_CONNECT_SPACE ((sl_status_t)0x0700) ///< sl status connect space. +#define SL_STATUS_NET_SUITE_SPACE ((sl_status_t)0x0800) ///< sl status net suite space. +#define SL_STATUS_THREAD_SPACE ((sl_status_t)0x0900) ///< sl status thread space. +#define SL_STATUS_USB_SPACE ((sl_status_t)0x0A00) ///< sl status usb space. +#define SL_STATUS_WIFI_SPACE ((sl_status_t)0x0B00) ///< sl status wifi space. +#define SL_STATUS_ZIGBEE_SPACE ((sl_status_t)0x0C00) ///< sl status zigbee space. +#define SL_STATUS_Z_WAVE_SPACE ((sl_status_t)0x0D00) ///< sl status z wave space. + +#define SL_STATUS_GECKO_OS_1_SPACE ((sl_status_t)0x0E00) ///< sl status gecko os 1 space. +#define SL_STATUS_GECKO_OS_2_SPACE ((sl_status_t)0x0F00) ///< sl status gecko os 2 space. + +#define SL_STATUS_BLUETOOTH_CTRL_SPACE ((sl_status_t)0x1000) ///< sl status bluetooth ctrl space. +#define SL_STATUS_BLUETOOTH_ATT_SPACE ((sl_status_t)0x1100) ///< sl status bluetooth att space. +#define SL_STATUS_BLUETOOTH_SMP_SPACE ((sl_status_t)0x1200) ///< sl status bluetooth mesh foundation space. +#define SL_STATUS_BLUETOOTH_MESH_FOUNDATION_SPACE ((sl_status_t)0x1300) ///< sl status bluetooth mesh foundation space. + +#define SL_STATUS_WISUN_SPACE ((sl_status_t)0x1400) ///< sl status wisun space. + +#define SL_STATUS_COMPUTE_SPACE ((sl_status_t)0x1500) ///< sl status compute space. + +// ----------------------------------------------------------------------------- +// Status Defines + +// ----------------------------------------------------------------------------- +// Generic Errors + +#define SL_STATUS_OK ((sl_status_t)0x0000) ///< No error. +#define SL_STATUS_FAIL ((sl_status_t)0x0001) ///< Generic error. + +// State Errors +#define SL_STATUS_INVALID_STATE ((sl_status_t)0x0002) ///< Generic invalid state error. +#define SL_STATUS_NOT_READY ((sl_status_t)0x0003) ///< Module is not ready for requested operation. +#define SL_STATUS_BUSY ((sl_status_t)0x0004) ///< Module is busy and cannot carry out requested operation. +#define SL_STATUS_IN_PROGRESS ((sl_status_t)0x0005) ///< Operation is in progress and not yet complete (pass or fail). +#define SL_STATUS_ABORT ((sl_status_t)0x0006) ///< Operation aborted. +#define SL_STATUS_TIMEOUT ((sl_status_t)0x0007) ///< Operation timed out. +#define SL_STATUS_PERMISSION ((sl_status_t)0x0008) ///< Operation not allowed per permissions. +#define SL_STATUS_WOULD_BLOCK ((sl_status_t)0x0009) ///< Non-blocking operation would block. +#define SL_STATUS_IDLE ((sl_status_t)0x000A) ///< Operation/module is Idle, cannot carry requested operation. +#define SL_STATUS_IS_WAITING ((sl_status_t)0x000B) ///< Operation cannot be done while construct is waiting. +#define SL_STATUS_NONE_WAITING ((sl_status_t)0x000C) ///< No task/construct waiting/pending for that action/event. +#define SL_STATUS_SUSPENDED ((sl_status_t)0x000D) ///< Operation cannot be done while construct is suspended. +#define SL_STATUS_NOT_AVAILABLE ((sl_status_t)0x000E) ///< Feature not available due to software configuration. +#define SL_STATUS_NOT_SUPPORTED ((sl_status_t)0x000F) ///< Feature not supported. +#define SL_STATUS_INITIALIZATION ((sl_status_t)0x0010) ///< Initialization failed. +#define SL_STATUS_NOT_INITIALIZED ((sl_status_t)0x0011) ///< Module has not been initialized. +#define SL_STATUS_ALREADY_INITIALIZED ((sl_status_t)0x0012) ///< Module has already been initialized. +#define SL_STATUS_DELETED ((sl_status_t)0x0013) ///< Object/construct has been deleted. +#define SL_STATUS_ISR ((sl_status_t)0x0014) ///< Illegal call from ISR. +#define SL_STATUS_NETWORK_UP ((sl_status_t)0x0015) ///< Illegal call because network is up. +#define SL_STATUS_NETWORK_DOWN ((sl_status_t)0x0016) ///< Illegal call because network is down. +#define SL_STATUS_NOT_JOINED ((sl_status_t)0x0017) ///< Failure due to not being joined in a network. +#define SL_STATUS_NO_BEACONS ((sl_status_t)0x0018) ///< Invalid operation as there are no beacons. + +// Allocation/ownership Errors +#define SL_STATUS_ALLOCATION_FAILED ((sl_status_t)0x0019) ///< Generic allocation error. +#define SL_STATUS_NO_MORE_RESOURCE ((sl_status_t)0x001A) ///< No more resource available to perform the operation. +#define SL_STATUS_EMPTY ((sl_status_t)0x001B) ///< Item/list/queue is empty. +#define SL_STATUS_FULL ((sl_status_t)0x001C) ///< Item/list/queue is full. +#define SL_STATUS_WOULD_OVERFLOW ((sl_status_t)0x001D) ///< Item would overflow. +#define SL_STATUS_HAS_OVERFLOWED ((sl_status_t)0x001E) ///< Item/list/queue has been overflowed. +#define SL_STATUS_OWNERSHIP ((sl_status_t)0x001F) ///< Generic ownership error. +#define SL_STATUS_IS_OWNER ((sl_status_t)0x0020) ///< Already/still owning resource. + +// Invalid Parameters Errors +#define SL_STATUS_INVALID_PARAMETER ((sl_status_t)0x0021) ///< Generic invalid argument or consequence of invalid argument. +#define SL_STATUS_NULL_POINTER ((sl_status_t)0x0022) ///< Invalid null pointer received as argument. +#define SL_STATUS_INVALID_CONFIGURATION ((sl_status_t)0x0023) ///< Invalid configuration provided. +#define SL_STATUS_INVALID_MODE ((sl_status_t)0x0024) ///< Invalid mode. +#define SL_STATUS_INVALID_HANDLE ((sl_status_t)0x0025) ///< Invalid handle. +#define SL_STATUS_INVALID_TYPE ((sl_status_t)0x0026) ///< Invalid type for operation. +#define SL_STATUS_INVALID_INDEX ((sl_status_t)0x0027) ///< Invalid index. +#define SL_STATUS_INVALID_RANGE ((sl_status_t)0x0028) ///< Invalid range. +#define SL_STATUS_INVALID_KEY ((sl_status_t)0x0029) ///< Invalid key. +#define SL_STATUS_INVALID_CREDENTIALS ((sl_status_t)0x002A) ///< Invalid credentials. +#define SL_STATUS_INVALID_COUNT ((sl_status_t)0x002B) ///< Invalid count. +#define SL_STATUS_INVALID_SIGNATURE ((sl_status_t)0x002C) ///< Invalid signature / verification failed. +#define SL_STATUS_NOT_FOUND ((sl_status_t)0x002D) ///< Item could not be found. +#define SL_STATUS_ALREADY_EXISTS ((sl_status_t)0x002E) ///< Item already exists. + +// IO/Communication Errors +#define SL_STATUS_IO ((sl_status_t)0x002F) ///< Generic I/O failure. +#define SL_STATUS_IO_TIMEOUT ((sl_status_t)0x0030) ///< I/O failure due to timeout. +#define SL_STATUS_TRANSMIT ((sl_status_t)0x0031) ///< Generic transmission error. +#define SL_STATUS_TRANSMIT_UNDERFLOW ((sl_status_t)0x0032) ///< Transmit underflowed. +#define SL_STATUS_TRANSMIT_INCOMPLETE ((sl_status_t)0x0033) ///< Transmit is incomplete. +#define SL_STATUS_TRANSMIT_BUSY ((sl_status_t)0x0034) ///< Transmit is busy. +#define SL_STATUS_RECEIVE ((sl_status_t)0x0035) ///< Generic reception error. +#define SL_STATUS_OBJECT_READ ((sl_status_t)0x0036) ///< Failed to read on/via given object. +#define SL_STATUS_OBJECT_WRITE ((sl_status_t)0x0037) ///< Failed to write on/via given object. +#define SL_STATUS_MESSAGE_TOO_LONG ((sl_status_t)0x0038) ///< Message is too long. + +// EEPROM/Flash Errors +#define SL_STATUS_EEPROM_MFG_VERSION_MISMATCH ((sl_status_t)0x0039) ///< EEPROM MFG version mismatch. +#define SL_STATUS_EEPROM_STACK_VERSION_MISMATCH ((sl_status_t)0x003A) ///< EEPROM Stack version mismatch. +#define SL_STATUS_FLASH_WRITE_INHIBITED ((sl_status_t)0x003B) ///< Flash write is inhibited. +#define SL_STATUS_FLASH_VERIFY_FAILED ((sl_status_t)0x003C) ///< Flash verification failed. +#define SL_STATUS_FLASH_PROGRAM_FAILED ((sl_status_t)0x003D) ///< Flash programming failed. +#define SL_STATUS_FLASH_ERASE_FAILED ((sl_status_t)0x003E) ///< Flash erase failed. + +// MAC Errors +#define SL_STATUS_MAC_NO_DATA ((sl_status_t)0x003F) ///< MAC no data. +#define SL_STATUS_MAC_NO_ACK_RECEIVED ((sl_status_t)0x0040) ///< MAC no ACK received. +#define SL_STATUS_MAC_INDIRECT_TIMEOUT ((sl_status_t)0x0041) ///< MAC indirect timeout. +#define SL_STATUS_MAC_UNKNOWN_HEADER_TYPE ((sl_status_t)0x0042) ///< MAC unknown header type. +#define SL_STATUS_MAC_ACK_HEADER_TYPE ((sl_status_t)0x0043) ///< MAC ACK unknown header type. +#define SL_STATUS_MAC_COMMAND_TRANSMIT_FAILURE ((sl_status_t)0x0044) ///< MAC command transmit failure. + +// CLI_STORAGE Errors +#define SL_STATUS_CLI_STORAGE_NVM_OPEN_ERROR ((sl_status_t)0x0045) ///< Error in open NVM + +// Security status codes +#define SL_STATUS_SECURITY_IMAGE_CHECKSUM_ERROR ((sl_status_t)0x0046) ///< Image checksum is not valid. +#define SL_STATUS_SECURITY_DECRYPT_ERROR ((sl_status_t)0x0047) ///< Decryption failed + +// Command status codes +#define SL_STATUS_COMMAND_IS_INVALID ((sl_status_t)0x0048) ///< Command was not recognized +#define SL_STATUS_COMMAND_TOO_LONG ((sl_status_t)0x0049) ///< Command or parameter maximum length exceeded +#define SL_STATUS_COMMAND_INCOMPLETE ((sl_status_t)0x004A) ///< Data received does not form a complete command + +// Misc Errors +#define SL_STATUS_BUS_ERROR ((sl_status_t)0x004B) ///< Bus error, e.g. invalid DMA address + +// Unified MAC Errors +#define SL_STATUS_CCA_FAILURE ((sl_status_t)0x004C) ///< CCA failure. + +// Scan errors +#define SL_STATUS_MAC_SCANNING ((sl_status_t)0x004D) ///< MAC scanning. +#define SL_STATUS_MAC_INCORRECT_SCAN_TYPE ((sl_status_t)0x004E) ///< MAC incorrect scan type. +#define SL_STATUS_INVALID_CHANNEL_MASK ((sl_status_t)0x004F) ///< Invalid channel mask. +#define SL_STATUS_BAD_SCAN_DURATION ((sl_status_t)0x0050) ///< Bad scan duration. + +// Bluetooth status codes +#define SL_STATUS_BT_OUT_OF_BONDS ((sl_status_t)0x0402) ///< Bonding procedure can't be started because device has no space left for bond. +#define SL_STATUS_BT_UNSPECIFIED ((sl_status_t)0x0403) ///< Unspecified error +#define SL_STATUS_BT_HARDWARE ((sl_status_t)0x0404) ///< Hardware failure +#define SL_STATUS_BT_NO_BONDING ((sl_status_t)0x0406) ///< The bonding does not exist. +#define SL_STATUS_BT_CRYPTO ((sl_status_t)0x0407) ///< Error using crypto functions +#define SL_STATUS_BT_DATA_CORRUPTED ((sl_status_t)0x0408) ///< Data was corrupted. +#define SL_STATUS_BT_INVALID_SYNC_HANDLE ((sl_status_t)0x040A) ///< Invalid periodic advertising sync handle +#define SL_STATUS_BT_INVALID_MODULE_ACTION ((sl_status_t)0x040B) ///< Bluetooth cannot be used on this hardware +#define SL_STATUS_BT_RADIO ((sl_status_t)0x040C) ///< Error received from radio +#define SL_STATUS_BT_L2CAP_REMOTE_DISCONNECTED ((sl_status_t)0x040D) ///< Returned when remote disconnects the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_LOCAL_DISCONNECTED ((sl_status_t)0x040E) ///< Returned when local host disconnect the connection-oriented channel by sending disconnection request. +#define SL_STATUS_BT_L2CAP_CID_NOT_EXIST ((sl_status_t)0x040F) ///< Returned when local host did not find a connection-oriented channel with given destination CID. +#define SL_STATUS_BT_L2CAP_LE_DISCONNECTED ((sl_status_t)0x0410) ///< Returned when connection-oriented channel disconnected due to LE connection is dropped. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_VIOLATED ((sl_status_t)0x0412) ///< Returned when connection-oriented channel disconnected due to remote end send data even without credit. +#define SL_STATUS_BT_L2CAP_FLOW_CONTROL_CREDIT_OVERFLOWED ((sl_status_t)0x0413) ///< Returned when connection-oriented channel disconnected due to remote end send flow control credits exceed 65535. +#define SL_STATUS_BT_L2CAP_NO_FLOW_CONTROL_CREDIT ((sl_status_t)0x0414) ///< Returned when connection-oriented channel has run out of flow control credit and local application still trying to send data. +#define SL_STATUS_BT_L2CAP_CONNECTION_REQUEST_TIMEOUT ((sl_status_t)0x0415) ///< Returned when connection-oriented channel has not received connection response message within maximum timeout. +#define SL_STATUS_BT_L2CAP_INVALID_CID ((sl_status_t)0x0416) ///< Returned when local host received a connection-oriented channel connection response with an invalid destination CID. +#define SL_STATUS_BT_L2CAP_WRONG_STATE ((sl_status_t)0x0417) ///< Returned when local host application tries to send a command which is not suitable for L2CAP channel's current state. +#define SL_STATUS_BT_PS_STORE_FULL ((sl_status_t)0x041B) ///< Flash reserved for PS store is full +#define SL_STATUS_BT_PS_KEY_NOT_FOUND ((sl_status_t)0x041C) ///< PS key not found +#define SL_STATUS_BT_APPLICATION_MISMATCHED_OR_INSUFFICIENT_SECURITY ((sl_status_t)0x041D) ///< Mismatched or insufficient security level +#define SL_STATUS_BT_APPLICATION_ENCRYPTION_DECRYPTION_ERROR ((sl_status_t)0x041E) ///< Encryption/decryption operation failed. + +// Bluetooth controller status codes +#define SL_STATUS_BT_CTRL_UNKNOWN_CONNECTION_IDENTIFIER ((sl_status_t)0x1002) ///< Connection does not exist, or connection open request was cancelled. +#define SL_STATUS_BT_CTRL_AUTHENTICATION_FAILURE ((sl_status_t)0x1005) ///< Pairing or authentication failed due to incorrect results in the pairing or authentication procedure. This could be due to an incorrect PIN or Link Key +#define SL_STATUS_BT_CTRL_PIN_OR_KEY_MISSING ((sl_status_t)0x1006) ///< Pairing failed because of missing PIN, or authentication failed because of missing Key +#define SL_STATUS_BT_CTRL_MEMORY_CAPACITY_EXCEEDED ((sl_status_t)0x1007) ///< Controller is out of memory. +#define SL_STATUS_BT_CTRL_CONNECTION_TIMEOUT ((sl_status_t)0x1008) ///< Link supervision timeout has expired. +#define SL_STATUS_BT_CTRL_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x1009) ///< Controller is at limit of connections it can support. +#define SL_STATUS_BT_CTRL_SYNCHRONOUS_CONNECTION_LIMIT_EXCEEDED ((sl_status_t)0x100A) ///< The Synchronous Connection Limit to a Device Exceeded error code indicates that the Controller has reached the limit to the number of synchronous connections that can be achieved to a device. +#define SL_STATUS_BT_CTRL_ACL_CONNECTION_ALREADY_EXISTS ((sl_status_t)0x100B) ///< The ACL Connection Already Exists error code indicates that an attempt to create a new ACL Connection to a device when there is already a connection to this device. +#define SL_STATUS_BT_CTRL_COMMAND_DISALLOWED ((sl_status_t)0x100C) ///< Command requested cannot be executed because the Controller is in a state where it cannot process this command at this time. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES ((sl_status_t)0x100D) ///< The Connection Rejected Due To Limited Resources error code indicates that an incoming connection was rejected due to limited resources. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS ((sl_status_t)0x100E) ///< The Connection Rejected Due To Security Reasons error code indicates that a connection was rejected due to security requirements not being fulfilled, like authentication or pairing. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR ((sl_status_t)0x100F) ///< The Connection was rejected because this device does not accept the BD_ADDR. This may be because the device will only accept connections from specific BD_ADDRs. +#define SL_STATUS_BT_CTRL_CONNECTION_ACCEPT_TIMEOUT_EXCEEDED ((sl_status_t)0x1010) ///< The Connection Accept Timeout has been exceeded for this connection attempt. +#define SL_STATUS_BT_CTRL_UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE ((sl_status_t)0x1011) ///< A feature or parameter value in the HCI command is not supported. +#define SL_STATUS_BT_CTRL_INVALID_COMMAND_PARAMETERS ((sl_status_t)0x1012) ///< Command contained invalid parameters. +#define SL_STATUS_BT_CTRL_REMOTE_USER_TERMINATED ((sl_status_t)0x1013) ///< User on the remote device terminated the connection. +#define SL_STATUS_BT_CTRL_REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES ((sl_status_t)0x1014) ///< The remote device terminated the connection because of low resources +#define SL_STATUS_BT_CTRL_REMOTE_POWERING_OFF ((sl_status_t)0x1015) ///< Remote Device Terminated Connection due to Power Off +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_BY_LOCAL_HOST ((sl_status_t)0x1016) ///< Local device terminated the connection. +#define SL_STATUS_BT_CTRL_REPEATED_ATTEMPTS ((sl_status_t)0x1017) ///< The Controller is disallowing an authentication or pairing procedure because too little time has elapsed since the last authentication or pairing attempt failed. +#define SL_STATUS_BT_CTRL_PAIRING_NOT_ALLOWED ((sl_status_t)0x1018) ///< The device does not allow pairing. This can be for example, when a device only allows pairing during a certain time window after some user input allows pairing +#define SL_STATUS_BT_CTRL_UNSUPPORTED_REMOTE_FEATURE ((sl_status_t)0x101A) ///< The remote device does not support the feature associated with the issued command. +#define SL_STATUS_BT_CTRL_UNSPECIFIED_ERROR ((sl_status_t)0x101F) ///< No other error code specified is appropriate to use. +#define SL_STATUS_BT_CTRL_LL_RESPONSE_TIMEOUT ((sl_status_t)0x1022) ///< Connection terminated due to link-layer procedure timeout. +#define SL_STATUS_BT_CTRL_LL_PROCEDURE_COLLISION ((sl_status_t)0x1023) ///< LL procedure has collided with the same transaction or procedure that is already in progress. +#define SL_STATUS_BT_CTRL_ENCRYPTION_MODE_NOT_ACCEPTABLE ((sl_status_t)0x1025) ///< The requested encryption mode is not acceptable at this time. +#define SL_STATUS_BT_CTRL_LINK_KEY_CANNOT_BE_CHANGED ((sl_status_t)0x1026) ///< Link key cannot be changed because a fixed unit key is being used. +#define SL_STATUS_BT_CTRL_INSTANT_PASSED ((sl_status_t)0x1028) ///< LMP PDU or LL PDU that includes an instant cannot be performed because the instant when this would have occurred has passed. +#define SL_STATUS_BT_CTRL_PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED ((sl_status_t)0x1029) ///< It was not possible to pair as a unit key was requested and it is not supported. +#define SL_STATUS_BT_CTRL_DIFFERENT_TRANSACTION_COLLISION ((sl_status_t)0x102A) ///< LMP transaction was started that collides with an ongoing transaction. +#define SL_STATUS_BT_CTRL_CHANNEL_ASSESSMENT_NOT_SUPPORTED ((sl_status_t)0x102E) ///< The Controller cannot perform channel assessment because it is not supported. +#define SL_STATUS_BT_CTRL_INSUFFICIENT_SECURITY ((sl_status_t)0x102F) ///< The HCI command or LMP PDU sent is only possible on an encrypted link. +#define SL_STATUS_BT_CTRL_PARAMETER_OUT_OF_MANDATORY_RANGE ((sl_status_t)0x1030) ///< A parameter value requested is outside the mandatory range of parameters for the given HCI command or LMP PDU. +#define SL_STATUS_BT_CTRL_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST ((sl_status_t)0x1037) ///< The IO capabilities request or response was rejected because the sending Host does not support Secure Simple Pairing even though the receiving Link Manager does. +#define SL_STATUS_BT_CTRL_HOST_BUSY_PAIRING ((sl_status_t)0x1038) ///< The Host is busy with another pairing operation and unable to support the requested pairing. The receiving device should retry pairing again later. +#define SL_STATUS_BT_CTRL_CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND ((sl_status_t)0x1039) ///< The Controller could not calculate an appropriate value for the Channel selection operation. +#define SL_STATUS_BT_CTRL_CONTROLLER_BUSY ((sl_status_t)0x103A) ///< Operation was rejected because the controller is busy and unable to process the request. +#define SL_STATUS_BT_CTRL_UNACCEPTABLE_CONNECTION_INTERVAL ((sl_status_t)0x103B) ///< Remote device terminated the connection because of an unacceptable connection interval. +#define SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT ((sl_status_t)0x103C) ///< Advertising for a fixed duration completed or, for directed advertising, that advertising completed without a connection being created. +#define SL_STATUS_BT_CTRL_CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE ((sl_status_t)0x103D) ///< Connection was terminated because the Message Integrity Check (MIC) failed on a received packet. +#define SL_STATUS_BT_CTRL_CONNECTION_FAILED_TO_BE_ESTABLISHED ((sl_status_t)0x103E) ///< LL initiated a connection but the connection has failed to be established. Controller did not receive any packets from remote end. +#define SL_STATUS_BT_CTRL_MAC_CONNECTION_FAILED ((sl_status_t)0x103F) ///< The MAC of the 802.11 AMP was requested to connect to a peer, but the connection failed. +#define SL_STATUS_BT_CTRL_COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING ((sl_status_t)0x1040) ///< The master, at this time, is unable to make a coarse adjustment to the piconet clock, using the supplied parameters. Instead the master will attempt to move the clock using clock dragging. +#define SL_STATUS_BT_CTRL_UNKNOWN_ADVERTISING_IDENTIFIER ((sl_status_t)0x1042) ///< A command was sent from the Host that should identify an Advertising or Sync handle, but the Advertising or Sync handle does not exist. +#define SL_STATUS_BT_CTRL_LIMIT_REACHED ((sl_status_t)0x1043) ///< Number of operations requested has been reached and has indicated the completion of the activity (e.g., advertising or scanning). +#define SL_STATUS_BT_CTRL_OPERATION_CANCELLED_BY_HOST ((sl_status_t)0x1044) ///< A request to the Controller issued by the Host and still pending was successfully canceled. +#define SL_STATUS_BT_CTRL_PACKET_TOO_LONG ((sl_status_t)0x1045) ///< An attempt was made to send or receive a packet that exceeds the maximum allowed packet length. +#define SL_STATUS_BT_CTRL_TOO_LATE ((sl_status_t)0x1046) ///< Information was provided too late to the controller. +#define SL_STATUS_BT_CTRL_TOO_EARLY ((sl_status_t)0x1047) ///< Information was provided too early to the controller. + +// Bluetooth attribute status codes +#define SL_STATUS_BT_ATT_INVALID_HANDLE ((sl_status_t)0x1101) ///< The attribute handle given was not valid on this server +#define SL_STATUS_BT_ATT_READ_NOT_PERMITTED ((sl_status_t)0x1102) ///< The attribute cannot be read +#define SL_STATUS_BT_ATT_WRITE_NOT_PERMITTED ((sl_status_t)0x1103) ///< The attribute cannot be written +#define SL_STATUS_BT_ATT_INVALID_PDU ((sl_status_t)0x1104) ///< The attribute PDU was invalid +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHENTICATION ((sl_status_t)0x1105) ///< The attribute requires authentication before it can be read or written. +#define SL_STATUS_BT_ATT_REQUEST_NOT_SUPPORTED ((sl_status_t)0x1106) ///< Attribute Server does not support the request received from the client. +#define SL_STATUS_BT_ATT_INVALID_OFFSET ((sl_status_t)0x1107) ///< Offset specified was past the end of the attribute +#define SL_STATUS_BT_ATT_INSUFFICIENT_AUTHORIZATION ((sl_status_t)0x1108) ///< The attribute requires authorization before it can be read or written. +#define SL_STATUS_BT_ATT_PREPARE_QUEUE_FULL ((sl_status_t)0x1109) ///< Too many prepare writes have been queued +#define SL_STATUS_BT_ATT_ATT_NOT_FOUND ((sl_status_t)0x110A) ///< No attribute found within the given attribute handle range. +#define SL_STATUS_BT_ATT_ATT_NOT_LONG ((sl_status_t)0x110B) ///< The attribute cannot be read or written using the Read Blob Request +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENC_KEY_SIZE ((sl_status_t)0x110C) ///< The Encryption Key Size used for encrypting this link is insufficient. +#define SL_STATUS_BT_ATT_INVALID_ATT_LENGTH ((sl_status_t)0x110D) ///< The attribute value length is invalid for the operation +#define SL_STATUS_BT_ATT_UNLIKELY_ERROR ((sl_status_t)0x110E) ///< The attribute request that was requested has encountered an error that was unlikely, and therefore could not be completed as requested. +#define SL_STATUS_BT_ATT_INSUFFICIENT_ENCRYPTION ((sl_status_t)0x110F) ///< The attribute requires encryption before it can be read or written. +#define SL_STATUS_BT_ATT_UNSUPPORTED_GROUP_TYPE ((sl_status_t)0x1110) ///< The attribute type is not a supported grouping attribute as defined by a higher layer specification. +#define SL_STATUS_BT_ATT_INSUFFICIENT_RESOURCES ((sl_status_t)0x1111) ///< Insufficient Resources to complete the request +#define SL_STATUS_BT_ATT_OUT_OF_SYNC ((sl_status_t)0x1112) ///< The server requests the client to rediscover the database. +#define SL_STATUS_BT_ATT_VALUE_NOT_ALLOWED ((sl_status_t)0x1113) ///< The attribute parameter value was not allowed. +#define SL_STATUS_BT_ATT_APPLICATION ((sl_status_t)0x1180) ///< When this is returned in a BGAPI response, the application tried to read or write the value of a user attribute from the GATT database. +#define SL_STATUS_BT_ATT_WRITE_REQUEST_REJECTED ((sl_status_t)0x11FC) ///< The requested write operation cannot be fulfilled for reasons other than permissions. +#define SL_STATUS_BT_ATT_CLIENT_CHARACTERISTIC_CONFIGURATION_DESCRIPTOR_IMPROPERLY_CONFIGURED ((sl_status_t)0x11FD) ///< The Client Characteristic Configuration descriptor is not configured according to the requirements of the profile or service. +#define SL_STATUS_BT_ATT_PROCEDURE_ALREADY_IN_PROGRESS ((sl_status_t)0x11FE) ///< The profile or service request cannot be serviced because an operation that has been previously triggered is still in progress. +#define SL_STATUS_BT_ATT_OUT_OF_RANGE ((sl_status_t)0x11FF) ///< The attribute value is out of range as defined by a profile or service specification. + +// Bluetooth Security Manager Protocol status codes +#define SL_STATUS_BT_SMP_PASSKEY_ENTRY_FAILED ((sl_status_t)0x1201) ///< The user input of passkey failed, for example, the user cancelled the operation +#define SL_STATUS_BT_SMP_OOB_NOT_AVAILABLE ((sl_status_t)0x1202) ///< Out of Band data is not available for authentication +#define SL_STATUS_BT_SMP_AUTHENTICATION_REQUIREMENTS ((sl_status_t)0x1203) ///< The pairing procedure cannot be performed as authentication requirements cannot be met due to IO capabilities of one or both devices +#define SL_STATUS_BT_SMP_CONFIRM_VALUE_FAILED ((sl_status_t)0x1204) ///< The confirm value does not match the calculated compare value +#define SL_STATUS_BT_SMP_PAIRING_NOT_SUPPORTED ((sl_status_t)0x1205) ///< Pairing is not supported by the device +#define SL_STATUS_BT_SMP_ENCRYPTION_KEY_SIZE ((sl_status_t)0x1206) ///< The resultant encryption key size is insufficient for the security requirements of this device +#define SL_STATUS_BT_SMP_COMMAND_NOT_SUPPORTED ((sl_status_t)0x1207) ///< The SMP command received is not supported on this device +#define SL_STATUS_BT_SMP_UNSPECIFIED_REASON ((sl_status_t)0x1208) ///< Pairing failed due to an unspecified reason +#define SL_STATUS_BT_SMP_REPEATED_ATTEMPTS ((sl_status_t)0x1209) ///< Pairing or authentication procedure is disallowed because too little time has elapsed since last pairing request or security request +#define SL_STATUS_BT_SMP_INVALID_PARAMETERS ((sl_status_t)0x120A) ///< The Invalid Parameters error code indicates: the command length is invalid or a parameter is outside of the specified range. +#define SL_STATUS_BT_SMP_DHKEY_CHECK_FAILED ((sl_status_t)0x120B) ///< Indicates to the remote device that the DHKey Check value received doesn't match the one calculated by the local device. +#define SL_STATUS_BT_SMP_NUMERIC_COMPARISON_FAILED ((sl_status_t)0x120C) ///< Indicates that the confirm values in the numeric comparison protocol do not match. +#define SL_STATUS_BT_SMP_BREDR_PAIRING_IN_PROGRESS ((sl_status_t)0x120D) ///< Indicates that the pairing over the LE transport failed due to a Pairing Request sent over the BR/EDR transport in process. +#define SL_STATUS_BT_SMP_CROSS_TRANSPORT_KEY_DERIVATION_GENERATION_NOT_ALLOWED ((sl_status_t)0x120E) ///< Indicates that the BR/EDR Link Key generated on the BR/EDR transport cannot be used to derive and distribute keys for the LE transport. +#define SL_STATUS_BT_SMP_KEY_REJECTED ((sl_status_t)0x120F) ///< Indicates that the device chose not to accept a distributed key. + +// Bluetooth Mesh status codes +#define SL_STATUS_BT_MESH_ALREADY_EXISTS ((sl_status_t)0x0501) ///< Returned when trying to add a key or some other unique resource with an ID which already exists +#define SL_STATUS_BT_MESH_DOES_NOT_EXIST ((sl_status_t)0x0502) ///< Returned when trying to manipulate a key or some other resource with an ID which does not exist +#define SL_STATUS_BT_MESH_LIMIT_REACHED ((sl_status_t)0x0503) ///< Returned when an operation cannot be executed because a pre-configured limit for keys, key bindings, elements, models, virtual addresses, provisioned devices, or provisioning sessions is reached +#define SL_STATUS_BT_MESH_INVALID_ADDRESS ((sl_status_t)0x0504) ///< Returned when trying to use a reserved address or add a "pre-provisioned" device using an address already used by some other device +#define SL_STATUS_BT_MESH_MALFORMED_DATA ((sl_status_t)0x0505) ///< In a BGAPI response, the user supplied malformed data; in a BGAPI event, the remote end responded with malformed or unrecognized data +#define SL_STATUS_BT_MESH_ALREADY_INITIALIZED ((sl_status_t)0x0506) ///< An attempt was made to initialize a subsystem that was already initialized. +#define SL_STATUS_BT_MESH_NOT_INITIALIZED ((sl_status_t)0x0507) ///< An attempt was made to use a subsystem that wasn't initialized yet. Call the subsystem's init function first. +#define SL_STATUS_BT_MESH_NO_FRIEND_OFFER ((sl_status_t)0x0508) ///< Returned when trying to establish a friendship as a Low Power Node, but no acceptable friend offer message was received. +#define SL_STATUS_BT_MESH_PROV_LINK_CLOSED ((sl_status_t)0x0509) ///< Provisioning link was unexpectedly closed before provisioning was complete. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU ((sl_status_t)0x050A) ///< An unrecognized provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_INVALID_PDU_FORMAT ((sl_status_t)0x050B) ///< A provisioning PDU with wrong length or containing field values that are out of bounds was received. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_PDU ((sl_status_t)0x050C) ///< An unexpected (out of sequence) provisioning PDU was received. +#define SL_STATUS_BT_MESH_PROV_CONFIRMATION_FAILED ((sl_status_t)0x050D) ///< The computed confirmation value did not match the expected value. +#define SL_STATUS_BT_MESH_PROV_OUT_OF_RESOURCES ((sl_status_t)0x050E) ///< Provisioning could not be continued due to insufficient resources. +#define SL_STATUS_BT_MESH_PROV_DECRYPTION_FAILED ((sl_status_t)0x050F) ///< The provisioning data block could not be decrypted. +#define SL_STATUS_BT_MESH_PROV_UNEXPECTED_ERROR ((sl_status_t)0x0510) ///< An unexpected error happened during provisioning. +#define SL_STATUS_BT_MESH_PROV_CANNOT_ASSIGN_ADDR ((sl_status_t)0x0511) ///< Device could not assign unicast addresses to all of its elements. +#define SL_STATUS_BT_MESH_ADDRESS_TEMPORARILY_UNAVAILABLE ((sl_status_t)0x0512) ///< Returned when trying to reuse an address of a previously deleted device before an IV Index Update has been executed. +#define SL_STATUS_BT_MESH_ADDRESS_ALREADY_USED ((sl_status_t)0x0513) ///< Returned when trying to assign an address that is used by one of the devices in the Device Database, or by the Provisioner itself. +#define SL_STATUS_BT_MESH_PUBLISH_NOT_CONFIGURED ((sl_status_t)0x0514) ///< Application key or publish address are not set +#define SL_STATUS_BT_MESH_APP_KEY_NOT_BOUND ((sl_status_t)0x0515) ///< Application key is not bound to a model + +// Bluetooth Mesh foundation status codes +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_ADDRESS ((sl_status_t)0x1301) ///< Returned when address in request was not valid +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_MODEL ((sl_status_t)0x1302) ///< Returned when model identified is not found for a given element +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_APP_KEY ((sl_status_t)0x1303) ///< Returned when the key identified by AppKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_NET_KEY ((sl_status_t)0x1304) ///< Returned when the key identified by NetKeyIndex is not stored in the node +#define SL_STATUS_BT_MESH_FOUNDATION_INSUFFICIENT_RESOURCES ((sl_status_t)0x1305) ///< Returned when The node cannot serve the request due to insufficient resources +#define SL_STATUS_BT_MESH_FOUNDATION_KEY_INDEX_EXISTS ((sl_status_t)0x1306) ///< Returned when the key identified is already stored in the node and the new NetKey value is different +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_PUBLISH_PARAMS ((sl_status_t)0x1307) ///< Returned when the model does not support the publish mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUBSCRIBE_MODEL ((sl_status_t)0x1308) ///< Returned when the model does not support the subscribe mechanism +#define SL_STATUS_BT_MESH_FOUNDATION_STORAGE_FAILURE ((sl_status_t)0x1309) ///< Returned when storing of the requested parameters failed +#define SL_STATUS_BT_MESH_FOUNDATION_NOT_SUPPORTED ((sl_status_t)0x130A) ///< Returned when requested setting is not supported +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_UPDATE ((sl_status_t)0x130B) ///< Returned when the requested update operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_REMOVE ((sl_status_t)0x130C) ///< Returned when the requested delete operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_BIND ((sl_status_t)0x130D) ///< Returned when the requested bind operation cannot be performed due to general constraints +#define SL_STATUS_BT_MESH_FOUNDATION_TEMPORARILY_UNABLE ((sl_status_t)0x130E) ///< Returned when The node cannot start advertising with Node Identity or Proxy since the maximum number of parallel advertising is reached +#define SL_STATUS_BT_MESH_FOUNDATION_CANNOT_SET ((sl_status_t)0x130F) ///< Returned when the requested state cannot be set +#define SL_STATUS_BT_MESH_FOUNDATION_UNSPECIFIED ((sl_status_t)0x1310) ///< Returned when an unspecified error took place +#define SL_STATUS_BT_MESH_FOUNDATION_INVALID_BINDING ((sl_status_t)0x1311) ///< Returned when the NetKeyIndex and AppKeyIndex combination is not valid for a Config AppKey Update + +// ----------------------------------------------------------------------------- +// Wi-Fi Errors + +#define SL_STATUS_WIFI_INVALID_KEY ((sl_status_t)0x0B01) ///< Invalid firmware keyset +#define SL_STATUS_WIFI_FIRMWARE_DOWNLOAD_TIMEOUT ((sl_status_t)0x0B02) ///< The firmware download took too long +#define SL_STATUS_WIFI_UNSUPPORTED_MESSAGE_ID ((sl_status_t)0x0B03) ///< Unknown request ID or wrong interface ID used +#define SL_STATUS_WIFI_WARNING ((sl_status_t)0x0B04) ///< The request is successful but some parameters have been ignored +#define SL_STATUS_WIFI_NO_PACKET_TO_RECEIVE ((sl_status_t)0x0B05) ///< No Packets waiting to be received +#define SL_STATUS_WIFI_SLEEP_GRANTED ((sl_status_t)0x0B08) ///< The sleep mode is granted +#define SL_STATUS_WIFI_SLEEP_NOT_GRANTED ((sl_status_t)0x0B09) ///< The WFx does not go back to sleep +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ERROR ((sl_status_t)0x0B10) ///< The SecureLink MAC key was not found +#define SL_STATUS_WIFI_SECURE_LINK_MAC_KEY_ALREADY_BURNED ((sl_status_t)0x0B11) ///< The SecureLink MAC key is already installed in OTP +#define SL_STATUS_WIFI_SECURE_LINK_RAM_MODE_NOT_ALLOWED ((sl_status_t)0x0B12) ///< The SecureLink MAC key cannot be installed in RAM +#define SL_STATUS_WIFI_SECURE_LINK_FAILED_UNKNOWN_MODE ((sl_status_t)0x0B13) ///< The SecureLink MAC key installation failed +#define SL_STATUS_WIFI_SECURE_LINK_EXCHANGE_FAILED ((sl_status_t)0x0B14) ///< SecureLink key (re)negotiation failed +#define SL_STATUS_WIFI_WRONG_STATE ((sl_status_t)0x0B18) ///< The device is in an inappropriate state to perform the request +#define SL_STATUS_WIFI_CHANNEL_NOT_ALLOWED ((sl_status_t)0x0B19) ///< The request failed due to regulatory limitations +#define SL_STATUS_WIFI_NO_MATCHING_AP ((sl_status_t)0x0B1A) ///< The connection request failed because no suitable AP was found +#define SL_STATUS_WIFI_CONNECTION_ABORTED ((sl_status_t)0x0B1B) ///< The connection request was aborted by host +#define SL_STATUS_WIFI_CONNECTION_TIMEOUT ((sl_status_t)0x0B1C) ///< The connection request failed because of a timeout +#define SL_STATUS_WIFI_CONNECTION_REJECTED_BY_AP ((sl_status_t)0x0B1D) ///< The connection request failed because the AP rejected the device +#define SL_STATUS_WIFI_CONNECTION_AUTH_FAILURE ((sl_status_t)0x0B1E) ///< The connection request failed because the WPA handshake did not complete successfully +#define SL_STATUS_WIFI_RETRY_EXCEEDED ((sl_status_t)0x0B1F) ///< The request failed because the retry limit was exceeded +#define SL_STATUS_WIFI_TX_LIFETIME_EXCEEDED ((sl_status_t)0x0B20) ///< The request failed because the MSDU life time was exceeded + +// ----------------------------------------------------------------------------- +// MVP Driver and MVP Math status codes +#define SL_STATUS_COMPUTE_DRIVER_FAULT ((sl_status_t)0x1501) ///< Critical fault +#define SL_STATUS_COMPUTE_DRIVER_ALU_NAN ((sl_status_t)0x1502) ///< ALU operation output NaN +#define SL_STATUS_COMPUTE_DRIVER_ALU_OVERFLOW ((sl_status_t)0x1503) ///< ALU numeric overflow +#define SL_STATUS_COMPUTE_DRIVER_ALU_UNDERFLOW ((sl_status_t)0x1504) ///< ALU numeric underflow +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_OVERFLOW ((sl_status_t)0x1505) ///< Overflow during array store +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_UNDERFLOW ((sl_status_t)0x1506) ///< Underflow during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_INFINITY ((sl_status_t)0x1507) ///< Infinity encountered during array store conversion +#define SL_STATUS_COMPUTE_DRIVER_STORE_CONVERSION_NAN ((sl_status_t)0x1508) ///< NaN encountered during array store conversion + +#define SL_STATUS_COMPUTE_MATH_NAN ((sl_status_t)0x1512) ///< MATH NaN encountered +#define SL_STATUS_COMPUTE_MATH_INFINITY ((sl_status_t)0x1513) ///< MATH Infinity encountered +#define SL_STATUS_COMPUTE_MATH_OVERFLOW ((sl_status_t)0x1514) ///< MATH numeric overflow +#define SL_STATUS_COMPUTE_MATH_UNDERFLOW ((sl_status_t)0x1515) ///< MATH numeric underflow + +// ----------------------------------------------------------------------------- +// Data Types +/** @brief define global status variable. */ +typedef uint32_t sl_status_t; + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************************************** + * sl_status_get_string_n() + * + * @brief Get a copy of the status string associated to the status code passed, up to + * 'buffer_length' length, if the string associated to the status code is enabled. If not, + * the error code number, in hex, prefixed by "SL_STATUS_" will be copied in the buffer + * instead. + * For example, the buffer would either contain "SL_STATUS_FAIL" if that status string is + * enabled, or "SL_STATUS_0x0001" if the string is disabled, as SL_STATUS_FAIL's + * value is 0x0001. + * + * @param status The status code from which to obtain the status string. + * + * @param buffer Pointer to a buffer in which the status string will be copied. A terminating + * null-character will be appended after the copied status string. + * + * @param buffer_length Maximum number of characters that can be written in the buffer, including the + * terminating null-character. If the status string would be longer than the + * available length, it will be truncated and a null-terminating character will + * be the last character contained in the buffer. + * + * @return The number of characters that would have been written if the buffer_length had been + * sufficiently large, not counting the terminating null character. + * If the status code is invalid, 0 or a negative number is returned. + * Notice that only when this returned value is strictly positive and less than + * buffer_length, the status string has been completely written in the buffer. + *******************************************************************************************************/ +int32_t sl_status_get_string_n(sl_status_t status, char *buffer, uint32_t buffer_length); + +/******************************************************************************************************** + * sl_status_print() + * + * @brief Print, through printf, the string associated to the passed status code. If the string + * associated to the status code is enabled, the status string will be printed, for example + * "SL_STATUS_OK". If the string associated to the status code is disabled, the status number, + * in hex, prefixed by "SL_STATUS_" will be printed instead, for example "SL_STATUS_0x0000", + * as SL_STATUS_OK's value is 0x0000. + * + * @param status The status code of which to print the status string. + *******************************************************************************************************/ +void sl_status_print(sl_status_t status); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup status) */ + +#endif /* SL_STATUS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_assert.c b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_assert.c index 5b22c4f..12c843a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_assert.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_assert.c @@ -1,76 +1,76 @@ -/***************************************************************************//** - * @file - * @brief Assert API - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_assert.h" -#include - -/***************************************************************************//** - * @addtogroup assert - * @details - * This module contains functions to control the ASSERT peripheral of Silicon - * Labs 32-bit MCUs and SoCs. - * @{ - ******************************************************************************/ - -#if defined(DEBUG_EFM) -/***************************************************************************//** - * @brief - * EFM internal assert handling. - * - * This function is invoked through EFM_ASSERT() macro usage only and should - * not be used explicitly. - * - * This implementation enters an indefinite loop, allowing - * the use of a debugger to determine a cause of failure. By defining - * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version - * of this function must be defined and will be invoked instead, possibly - * providing output of assertion location. - * - * @note - * This function is not used unless DEBUG_EFM is defined - * during preprocessing of EFM_ASSERT() usage. - * - * @param[in] file - * Name of the source file where assertion failed. - * - * @param[in] line - * A line number in the source file where assertion failed. - ******************************************************************************/ -void assertEFM(const char *file, int line) -{ - (void)file; /* Unused parameter */ - (void)line; /* Unused parameter */ - - while (true) { - } -} -#endif /* DEBUG_EFM */ - -/** @} (end addtogroup assert) */ +/***************************************************************************//** + * @file + * @brief Assert API + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include + +/***************************************************************************//** + * @addtogroup assert + * @details + * This module contains functions to control the ASSERT peripheral of Silicon + * Labs 32-bit MCUs and SoCs. + * @{ + ******************************************************************************/ + +#if defined(DEBUG_EFM) +/***************************************************************************//** + * @brief + * EFM internal assert handling. + * + * This function is invoked through EFM_ASSERT() macro usage only and should + * not be used explicitly. + * + * This implementation enters an indefinite loop, allowing + * the use of a debugger to determine a cause of failure. By defining + * DEBUG_EFM_USER to the preprocessor for all files, a user-defined version + * of this function must be defined and will be invoked instead, possibly + * providing output of assertion location. + * + * @note + * This function is not used unless DEBUG_EFM is defined + * during preprocessing of EFM_ASSERT() usage. + * + * @param[in] file + * Name of the source file where assertion failed. + * + * @param[in] line + * A line number in the source file where assertion failed. + ******************************************************************************/ +void assertEFM(const char *file, int line) +{ + (void)file; /* Unused parameter */ + (void)line; /* Unused parameter */ + + while (true) { + } +} +#endif /* DEBUG_EFM */ + +/** @} (end addtogroup assert) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_slist.c b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_slist.c index 0e8d609..dbe7ac2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_slist.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_slist.c @@ -1,172 +1,172 @@ -/***************************************************************************//** - * @file - * @brief Single Link List - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_assert.h" -#include "sl_slist.h" -#include -#include -#include - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initializes a singly-linked list. - ******************************************************************************/ -void sl_slist_init(sl_slist_node_t **head) -{ - *head = 0; -} - -/***************************************************************************//** - * Add given item at beginning of list. - ******************************************************************************/ -void sl_slist_push(sl_slist_node_t **head, - sl_slist_node_t *item) -{ - EFM_ASSERT((item != NULL) && (head != NULL)); - - item->node = *head; - *head = item; -} - -/***************************************************************************//** - * Add item at end of list. - ******************************************************************************/ -void sl_slist_push_back(sl_slist_node_t **head, - sl_slist_node_t *item) -{ - sl_slist_node_t **node_ptr = head; - - EFM_ASSERT((item != NULL) && (head != NULL)); - - while (*node_ptr != NULL) { - node_ptr = &((*node_ptr)->node); - } - - item->node = NULL; - *node_ptr = item; -} - -/***************************************************************************//** - * Removes and returns first element of list. - ******************************************************************************/ -sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head) -{ - sl_slist_node_t *item; - - EFM_ASSERT(head != NULL); - - item = *head; - if (item == NULL) { - return (NULL); - } - - *head = item->node; - - item->node = NULL; - - return (item); -} - -/***************************************************************************//** - * Insert item after given item. - ******************************************************************************/ -void sl_slist_insert(sl_slist_node_t *item, - sl_slist_node_t *pos) -{ - EFM_ASSERT((item != NULL) && (pos != NULL)); - - item->node = pos->node; - pos->node = item; -} - -/***************************************************************************//** - * Remove item from list. - ******************************************************************************/ -void sl_slist_remove(sl_slist_node_t **head, - sl_slist_node_t *item) -{ - sl_slist_node_t **node_ptr; - - EFM_ASSERT((item != NULL) && (head != NULL)); - - for (node_ptr = head; *node_ptr != NULL; node_ptr = &((*node_ptr)->node)) { - if (*node_ptr == item) { - *node_ptr = item->node; - return; - } - } - - EFM_ASSERT(node_ptr != NULL); -} - -/***************************************************************************//** - * Sorts list items. - ******************************************************************************/ -void sl_slist_sort(sl_slist_node_t **head, - bool (*cmp_fnct)(sl_slist_node_t *item_l, - sl_slist_node_t *item_r)) -{ - bool swapped; - sl_slist_node_t **pp_item_l; - - EFM_ASSERT((head != NULL) && (cmp_fnct != NULL)); - - do { - swapped = false; - - pp_item_l = head; - // Loop until end of list is found. - while ((*pp_item_l != NULL) && ((*pp_item_l)->node != NULL)) { - sl_slist_node_t *p_item_r = (*pp_item_l)->node; - bool ordered; - - // Call provided compare fnct. - ordered = cmp_fnct(*pp_item_l, p_item_r); - if (ordered == false) { - // If order is not correct, swap items. - sl_slist_node_t *p_tmp = p_item_r->node; - - // Swap the two items. - p_item_r->node = *pp_item_l; - (*pp_item_l)->node = p_tmp; - *pp_item_l = p_item_r; - pp_item_l = &(p_item_r->node); - // Indicate a swap has been done. - swapped = true; - } else { - pp_item_l = &((*pp_item_l)->node); - } - } - // Re-loop until no items have been swapped. - } while (swapped == true); -} +/***************************************************************************//** + * @file + * @brief Single Link List + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_assert.h" +#include "sl_slist.h" +#include +#include +#include + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes a singly-linked list. + ******************************************************************************/ +void sl_slist_init(sl_slist_node_t **head) +{ + *head = 0; +} + +/***************************************************************************//** + * Add given item at beginning of list. + ******************************************************************************/ +void sl_slist_push(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + EFM_ASSERT((item != NULL) && (head != NULL)); + + item->node = *head; + *head = item; +} + +/***************************************************************************//** + * Add item at end of list. + ******************************************************************************/ +void sl_slist_push_back(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + sl_slist_node_t **node_ptr = head; + + EFM_ASSERT((item != NULL) && (head != NULL)); + + while (*node_ptr != NULL) { + node_ptr = &((*node_ptr)->node); + } + + item->node = NULL; + *node_ptr = item; +} + +/***************************************************************************//** + * Removes and returns first element of list. + ******************************************************************************/ +sl_slist_node_t *sl_slist_pop(sl_slist_node_t **head) +{ + sl_slist_node_t *item; + + EFM_ASSERT(head != NULL); + + item = *head; + if (item == NULL) { + return (NULL); + } + + *head = item->node; + + item->node = NULL; + + return (item); +} + +/***************************************************************************//** + * Insert item after given item. + ******************************************************************************/ +void sl_slist_insert(sl_slist_node_t *item, + sl_slist_node_t *pos) +{ + EFM_ASSERT((item != NULL) && (pos != NULL)); + + item->node = pos->node; + pos->node = item; +} + +/***************************************************************************//** + * Remove item from list. + ******************************************************************************/ +void sl_slist_remove(sl_slist_node_t **head, + sl_slist_node_t *item) +{ + sl_slist_node_t **node_ptr; + + EFM_ASSERT((item != NULL) && (head != NULL)); + + for (node_ptr = head; *node_ptr != NULL; node_ptr = &((*node_ptr)->node)) { + if (*node_ptr == item) { + *node_ptr = item->node; + return; + } + } + + EFM_ASSERT(node_ptr != NULL); +} + +/***************************************************************************//** + * Sorts list items. + ******************************************************************************/ +void sl_slist_sort(sl_slist_node_t **head, + bool (*cmp_fnct)(sl_slist_node_t *item_l, + sl_slist_node_t *item_r)) +{ + bool swapped; + sl_slist_node_t **pp_item_l; + + EFM_ASSERT((head != NULL) && (cmp_fnct != NULL)); + + do { + swapped = false; + + pp_item_l = head; + // Loop until end of list is found. + while ((*pp_item_l != NULL) && ((*pp_item_l)->node != NULL)) { + sl_slist_node_t *p_item_r = (*pp_item_l)->node; + bool ordered; + + // Call provided compare fnct. + ordered = cmp_fnct(*pp_item_l, p_item_r); + if (ordered == false) { + // If order is not correct, swap items. + sl_slist_node_t *p_tmp = p_item_r->node; + + // Swap the two items. + p_item_r->node = *pp_item_l; + (*pp_item_l)->node = p_tmp; + *pp_item_l = p_item_r; + pp_item_l = &(p_item_r->node); + // Indicate a swap has been done. + swapped = true; + } else { + pp_item_l = &((*pp_item_l)->node); + } + } + // Re-loop until no items have been swapped. + } while (swapped == true); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c index 84949f0..7ab761a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/src/sl_syscalls.c @@ -1,115 +1,115 @@ -/***************************************************************************//** - * @file - * @brief SystemCall API - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup systemcalls - * @details - * This module reimplements the syscalls that don't have the definition in the - * bare metal project. - * This prevents linker warnings. - * @{ - ******************************************************************************/ -#include "cmsis_compiler.h" - -struct stat; -struct timeval; -struct timezone; - -__WEAK int _close(int file) -{ - (void)file; - return -1; -} - -__WEAK void _exit(int status) -{ - (void)status; - - /* Convince GCC that this function never returns. */ - for (;; ) { - ; - } -} - -__WEAK int _fstat(int file, struct stat *st) -{ - (void)file; - (void)(void *)st; - return 0; -} - -__WEAK int _getpid(void) -{ - return 1; -} - -__WEAK int _isatty(int file) -{ - (void)file; - return 1; -} - -__WEAK int _kill(int pid, int sig) -{ - (void)pid; - (void)sig; - return -1; -} - -__WEAK int _lseek(int file, int ptr, int dir) -{ - (void)file; - (void)ptr; - (void)dir; - return 0; -} - -__WEAK int _read(int file, char *ptr, int len) -{ - (void)file; - (void)(void *)ptr; - (void)len; - return 0; -} - -__WEAK int _write(int file, const char *ptr, int len) -{ - (void)file; - (void)(const void *)ptr; - (void)len; - return 0; -} - -__WEAK int _gettimeofday(struct timeval *tv, struct timezone *tz) -{ - (void)(void *)tv; - (void)(void *)tz; - return 0; -} +/***************************************************************************//** + * @file + * @brief SystemCall API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup systemcalls + * @details + * This module reimplements the syscalls that don't have the definition in the + * bare metal project. + * This prevents linker warnings. + * @{ + ******************************************************************************/ +#include "cmsis_compiler.h" + +struct stat; +struct timeval; +struct timezone; + +__WEAK int _close(int file) +{ + (void)file; + return -1; +} + +__WEAK void _exit(int status) +{ + (void)status; + + /* Convince GCC that this function never returns. */ + for (;; ) { + ; + } +} + +__WEAK int _fstat(int file, struct stat *st) +{ + (void)file; + (void)(void *)st; + return 0; +} + +__WEAK int _getpid(void) +{ + return 1; +} + +__WEAK int _isatty(int file) +{ + (void)file; + return 1; +} + +__WEAK int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + return -1; +} + +__WEAK int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +__WEAK int _read(int file, char *ptr, int len) +{ + (void)file; + (void)(void *)ptr; + (void)len; + return 0; +} + +__WEAK int _write(int file, const char *ptr, int len) +{ + (void)file; + (void)(const void *)ptr; + (void)len; + return 0; +} + +__WEAK int _gettimeofday(struct timeval *tv, struct timezone *tz) +{ + (void)(void *)tv; + (void)(void *)tz; + return 0; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h index 55543c5..f032404 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_gcc_preinclude.h @@ -1,40 +1,40 @@ -/***************************************************************************//** - * @file - * @brief GCC startup file - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/* The startup files contain a stack and heap symbol in addition - * to the vector table. The size of these internal stack and heap - * objects depend on the build system providing two macros on the - * commandline called __STACK_SIZE and __HEAP_SIZE. - * - * We provide alternative stack and heap symbols in the sl_memory.c - * file which can be configured in a separate config file. Go to - * sl_memory_config.h to configure the stack and heap size. */ -#define __STACK_SIZE 0x0 -#define __HEAP_SIZE 0x0 +/***************************************************************************//** + * @file + * @brief GCC startup file + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/* The startup files contain a stack and heap symbol in addition + * to the vector table. The size of these internal stack and heap + * objects depend on the build system providing two macros on the + * commandline called __STACK_SIZE and __HEAP_SIZE. + * + * We provide alternative stack and heap symbols in the sl_memory.c + * file which can be configured in a separate config file. Go to + * sl_memory_config.h to configure the stack and heap size. */ +#define __STACK_SIZE 0x0 +#define __HEAP_SIZE 0x0 diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h index 64152d8..9f39e35 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief Heap and stack memory - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MEMORY_H -#define SL_MEMORY_H - -#include "sl_memory_region.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup linker - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get size and location of the stack. - * - * @return - * description of the region reserved for the c stack. - ******************************************************************************/ -sl_memory_region_t sl_memory_get_stack_region(void); - -/***************************************************************************//** - * @brief - * Get size and location of the heap. - * - * @return - * description of the region reserved for the c heap. - ******************************************************************************/ -sl_memory_region_t sl_memory_get_heap_region(void); - -/** @} end linker */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_MEMORY_H +/***************************************************************************//** + * @file + * @brief Heap and stack memory + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MEMORY_H +#define SL_MEMORY_H + +#include "sl_memory_region.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup linker + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get size and location of the stack. + * + * @return + * description of the region reserved for the c stack. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_stack_region(void); + +/***************************************************************************//** + * @brief + * Get size and location of the heap. + * + * @return + * description of the region reserved for the c heap. + ******************************************************************************/ +sl_memory_region_t sl_memory_get_heap_region(void); + +/** @} end linker */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_MEMORY_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h index 186f1db..4c73a0f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/inc/sl_memory_region.h @@ -1,49 +1,49 @@ -/***************************************************************************//** - * @file - * @brief Memory region types - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_REGION_H -#define SL_REGION_H - -#include - -/***************************************************************************//** - * @addtogroup linker Linker - * @brief Functions to extract locations of linker sections. - * @{ - ******************************************************************************/ - -/** Memory region structure. */ -typedef struct sl_memory_region_t { - void * addr; ///< Pointer to the beginning of the memory region. Can be NULL. - size_t size; ///< Size of this memory region. -} sl_memory_region_t; - -/** @} end linker */ - -#endif +/***************************************************************************//** + * @file + * @brief Memory region types + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_REGION_H +#define SL_REGION_H + +#include + +/***************************************************************************//** + * @addtogroup linker Linker + * @brief Functions to extract locations of linker sections. + * @{ + ******************************************************************************/ + +/** Memory region structure. */ +typedef struct sl_memory_region_t { + void * addr; ///< Pointer to the beginning of the memory region. Can be NULL. + size_t size; ///< Size of this memory region. +} sl_memory_region_t; + +/** @} end linker */ + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c index e26cb7d..a6c719f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/common/toolchain/src/sl_memory.c @@ -1,110 +1,110 @@ -/***************************************************************************//** - * @file - * @brief Heap and stack allocation - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include "em_device.h" -#include "sl_memory.h" -#include "sl_memory_config.h" - -#if defined(__GNUC__) -/* Declare stack object used with gcc */ -static char sl_stack[SL_STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); - -/* Declare the minimum heap object used with gcc */ - #if SL_HEAP_SIZE > 0 -static char sl_heap[SL_HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); - #endif - -/* - * Declare the base and limit of the full heap region used with gcc. To make - * use of otherwise unused memory, the total heap region be larger than the - * minimum heap allocation above. - */ -extern char __HeapBase[]; -extern char __HeapLimit[]; - -#elif defined(__ICCARM__) -/* Declare stack object used with iar */ -__root char sl_stack[SL_STACK_SIZE] @ ".stack"; - -/* Declare the minimum heap object used with iar */ - #if SL_HEAP_SIZE > 0 -__root char sl_heap[SL_HEAP_SIZE] @ ".heap"; - #endif - #pragma section="HEAP" - -#endif - -sl_memory_region_t sl_memory_get_stack_region(void) -{ - sl_memory_region_t region; - - region.addr = &sl_stack; - region.size = SL_STACK_SIZE; - return region; -} - -sl_memory_region_t sl_memory_get_heap_region(void) -{ - sl_memory_region_t region; - - /* - * Report the actual heap region which may be larger then the minimum - * allocation of SL_HEAP_SIZE bytes - */ -#if defined(__GNUC__) - region.addr = __HeapBase; - region.size = (size_t) ((uintptr_t) __HeapLimit - (uintptr_t) __HeapBase); - -#elif defined(__ICCARM__) - region.addr = __section_begin("HEAP"); - region.size = __section_size("HEAP"); - -#endif - - return region; -} - -#if defined(__GNUC__) -__USED void * _sbrk(int incr) -{ - static char *heap_end = __HeapBase; - char *prev_heap_end; - - if ((heap_end + incr) > __HeapLimit) { - // Not enough heap - return (void *) -1; - } - - prev_heap_end = heap_end; - heap_end += incr; - - return prev_heap_end; -} -#endif +/***************************************************************************//** + * @file + * @brief Heap and stack allocation + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include "em_device.h" +#include "sl_memory.h" +#include "sl_memory_config.h" + +#if defined(__GNUC__) +/* Declare stack object used with gcc */ +static char sl_stack[SL_STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +/* Declare the minimum heap object used with gcc */ + #if SL_HEAP_SIZE > 0 +static char sl_heap[SL_HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); + #endif + +/* + * Declare the base and limit of the full heap region used with gcc. To make + * use of otherwise unused memory, the total heap region be larger than the + * minimum heap allocation above. + */ +extern char __HeapBase[]; +extern char __HeapLimit[]; + +#elif defined(__ICCARM__) +/* Declare stack object used with iar */ +__root char sl_stack[SL_STACK_SIZE] @ ".stack"; + +/* Declare the minimum heap object used with iar */ + #if SL_HEAP_SIZE > 0 +__root char sl_heap[SL_HEAP_SIZE] @ ".heap"; + #endif + #pragma section="HEAP" + +#endif + +sl_memory_region_t sl_memory_get_stack_region(void) +{ + sl_memory_region_t region; + + region.addr = &sl_stack; + region.size = SL_STACK_SIZE; + return region; +} + +sl_memory_region_t sl_memory_get_heap_region(void) +{ + sl_memory_region_t region; + + /* + * Report the actual heap region which may be larger then the minimum + * allocation of SL_HEAP_SIZE bytes + */ +#if defined(__GNUC__) + region.addr = __HeapBase; + region.size = (size_t) ((uintptr_t) __HeapLimit - (uintptr_t) __HeapBase); + +#elif defined(__ICCARM__) + region.addr = __section_begin("HEAP"); + region.size = __section_size("HEAP"); + +#endif + + return region; +} + +#if defined(__GNUC__) +__USED void * _sbrk(int incr) +{ + static char *heap_end = __HeapBase; + char *prev_heap_end; + + if ((heap_end + incr) > __HeapLimit) { + // Not enough heap + return (void *) -1; + } + + prev_heap_end = heap_end; + heap_end += incr; + + return prev_heap_end; +} +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h b/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h index 5529b4c..21b86b8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/inc/sl_debug_swo.h @@ -1,167 +1,167 @@ -/***************************************************************************//** - * @file - * @brief SWO configuration - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEBUG_SWO_H -#define SL_DEBUG_SWO_H - -#include "sl_status.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup debug Debug - * @{ - * @addtogroup debug_swo SWO Debug - * @brief Serial Wire Output Debug Configuration - * @details - * Initializes Serial Wire Output using the DWT and ITM peripherals of - * Cortex-M processors. Configures output of Program Counter samples, - * interrupt events, and data over any ITM channel. - * @{ - */ -/** - * Initialize SWO Debug - * - * @details - * Initializes SWO debug using configuration parameters for frequency, as well - * as whether PC sample events and interrupt events should be emitted. - * - * @note - * This function does not enable any software stimulus ports in the ITM. This - * can be done by calling @ref sl_debug_swo_enable_itm or by using - * @ref sl_debug_swo_write which enables the necessary ports automatically. - * - * @return Status code - * @retval SL_STATUS_OK SWO initialized successfully - */ -sl_status_t sl_debug_swo_init(void); - -/** - * Enable an ITM channel - * - * @details - * Enables the given ITM channel in the Trace Enable Register. - * - * @param[in] channel ITM channel number - * - * @return Status code - * @retval SL_STATUS_OK ITM channel enabled successfully - */ -sl_status_t sl_debug_swo_enable_itm(uint32_t channel); - -/** - * Disable an ITM channel - * - * @details - * Disables the given ITM channel in the Trace Enable Register. - * - * @param[in] channel ITM channel number - * - * @return Status code - * @retval SL_STATUS_OK ITM channel disabled successfully - */ -sl_status_t sl_debug_swo_disable_itm(uint32_t channel); - -/** - * Write a byte to an ITM channel - * - * @details - * Writes the given byte to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. Note that even if the debug port is locked, the byte - * will still be written on the SWO. - * - * @param[in] channel ITM channel number - * @param[in] byte Byte to send - * - * @return Status code - * @retval SL_STATUS_OK Byte sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte); - -/** - * Write a half-word to an ITM channel - * - * @details - * Writes the given half-word to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. - * - * @param[in] channel ITM channel number - * @param[in] half_word Half-word to send - * - * @return Status code - * @retval SL_STATUS_OK half-word sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word); - -/** - * Write a word to an ITM channel - * - * @details - * Writes the given word to the given ITM channel - * - * @note - * This function ensures that the ITM channel is enabled, and enables it if - * it wasn't already. - * - * @param[in] channel ITM channel number - * @param[in] word Word to send - * - * @return Status code - * @retval SL_STATUS_OK half-word sent successfully - * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call - * @ref sl_debug_swo_init first. - */ -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word); - -/** - * alias for backward compatibility - */ -#define sl_debug_swo_write sl_debug_swo_write_u8 - -/** @} end debug_swo */ -/** @} end debug */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEBUG_SWO_H +/***************************************************************************//** + * @file + * @brief SWO configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEBUG_SWO_H +#define SL_DEBUG_SWO_H + +#include "sl_status.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup debug Debug + * @{ + * @addtogroup debug_swo SWO Debug + * @brief Serial Wire Output Debug Configuration + * @details + * Initializes Serial Wire Output using the DWT and ITM peripherals of + * Cortex-M processors. Configures output of Program Counter samples, + * interrupt events, and data over any ITM channel. + * @{ + */ +/** + * Initialize SWO Debug + * + * @details + * Initializes SWO debug using configuration parameters for frequency, as well + * as whether PC sample events and interrupt events should be emitted. + * + * @note + * This function does not enable any software stimulus ports in the ITM. This + * can be done by calling @ref sl_debug_swo_enable_itm or by using + * @ref sl_debug_swo_write which enables the necessary ports automatically. + * + * @return Status code + * @retval SL_STATUS_OK SWO initialized successfully + */ +sl_status_t sl_debug_swo_init(void); + +/** + * Enable an ITM channel + * + * @details + * Enables the given ITM channel in the Trace Enable Register. + * + * @param[in] channel ITM channel number + * + * @return Status code + * @retval SL_STATUS_OK ITM channel enabled successfully + */ +sl_status_t sl_debug_swo_enable_itm(uint32_t channel); + +/** + * Disable an ITM channel + * + * @details + * Disables the given ITM channel in the Trace Enable Register. + * + * @param[in] channel ITM channel number + * + * @return Status code + * @retval SL_STATUS_OK ITM channel disabled successfully + */ +sl_status_t sl_debug_swo_disable_itm(uint32_t channel); + +/** + * Write a byte to an ITM channel + * + * @details + * Writes the given byte to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. Note that even if the debug port is locked, the byte + * will still be written on the SWO. + * + * @param[in] channel ITM channel number + * @param[in] byte Byte to send + * + * @return Status code + * @retval SL_STATUS_OK Byte sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte); + +/** + * Write a half-word to an ITM channel + * + * @details + * Writes the given half-word to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. + * + * @param[in] channel ITM channel number + * @param[in] half_word Half-word to send + * + * @return Status code + * @retval SL_STATUS_OK half-word sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word); + +/** + * Write a word to an ITM channel + * + * @details + * Writes the given word to the given ITM channel + * + * @note + * This function ensures that the ITM channel is enabled, and enables it if + * it wasn't already. + * + * @param[in] channel ITM channel number + * @param[in] word Word to send + * + * @return Status code + * @retval SL_STATUS_OK half-word sent successfully + * @retval SL_STATUS_NOT_INITIALIZED ITM has not been enabled, call + * @ref sl_debug_swo_init first. + */ +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word); + +/** + * alias for backward compatibility + */ +#define sl_debug_swo_write sl_debug_swo_write_u8 + +/** @} end debug_swo */ +/** @} end debug */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEBUG_SWO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c b/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c index 8151608..3b02ab2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/driver/debug/src/sl_debug_swo.c @@ -1,269 +1,269 @@ -/***************************************************************************//** - * @file - * @brief SWO debug - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_debug_swo.h" - -#include "em_device.h" - -#if defined(__CORTEX_M) && (__CORTEX_M >= 3) - -#if _SILICON_LABS_32B_SERIES <= 2 -#include "em_gpio.h" -#else -#include "sl_peripheral_gpio.h" -#endif - -#include "em_cmu.h" -#include "sl_debug_swo_config.h" - -sl_status_t sl_debug_swo_init(void) -{ - uint32_t freq = 0.0f; - uint16_t cyctap = 0U; - uint16_t postpreset = 0U; - -#if _SILICON_LABS_32B_SERIES <= 2 - unsigned int location = 0U; - CMU_ClockEnable(cmuClock_GPIO, true); - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) - // Series 0 - location = SL_DEBUG_ROUTE_LOC; - GPIO_PinModeSet(SL_DEBUG_SWO_PORT, SL_DEBUG_SWO_PIN, gpioModePushPull, 1); -#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) - // Series 1 - location = SL_DEBUG_SWV_LOC; - GPIO_PinModeSet(SL_DEBUG_SWV_PORT, SL_DEBUG_SWV_PIN, gpioModePushPull, 1); -#elif defined(GPIO_SWV_PORT) - // Series 2 - // SWO location is not configurable - GPIO_PinModeSet((GPIO_Port_TypeDef)GPIO_SWV_PORT, GPIO_SWV_PIN, gpioModePushPull, 1); -#endif - - // Set SWO location - GPIO_DbgLocationSet(location); - - // Enable SWO pin - GPIO_DbgSWOEnable(true); - -#else -#if defined(GPIO_SWV_PORT) - sl_gpio_set_pin_mode((sl_gpio_port_t)GPIO_SWV_PORT, GPIO_SWV_PIN, SL_GPIO_MODE_PUSH_PULL, 1); -#endif - - sl_gpio_enable_debug_swo(true); -#endif - -#if _SILICON_LABS_32B_SERIES < 2 - // Enable debug clock - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - - // Get debug clock frequency - freq = CMU_ClockFreqGet(cmuClock_DBG); -#else - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) -#if defined(_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) -#if defined(CMU_CLKEN0_HFRCOEM23) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; -#endif - // Select HFRCOEM23 as source for TRACECLK - CMU_CLOCK_SELECT_SET(TRACECLK, HFRCOEM23); -#elif defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) - // Select SYSCLK as source for TRACECLK - CMU_CLOCK_SELECT_SET(TRACECLK, SYSCLK); -#endif -#endif - - freq = CMU_ClockFreqGet(cmuClock_TRACECLK); -#endif - - // Enable trace in core debug - CoreDebug->DHCSR |= CoreDebug_DHCSR_C_DEBUGEN_Msk; - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - //Tap the cyctap and postpreset based on the selected interval -#ifdef SL_DEBUG_SWO_SAMPLE_INTERVAL - if (SL_DEBUG_SWO_SAMPLE_INTERVAL <= 960) { - cyctap = 0; - postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 64); - } else { - cyctap = 1; - postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 1024); - } -#else - cyctap = 1; - postpreset = 0xF; -#endif - // Enable PC and IRQ sampling output - DWT->CTRL = ((4UL << DWT_CTRL_NUMCOMP_Pos) // Number of comparators. Hardwired to 4. - | (SL_DEBUG_SWO_SAMPLE_IRQ << DWT_CTRL_EXCTRCENA_Pos) // Interrupt events - | (SL_DEBUG_SWO_SAMPLE_PC << DWT_CTRL_PCSAMPLENA_Pos) // PC sample events - | (cyctap << DWT_CTRL_CYCTAP_Pos) // Tap cycle counter at bit 10 (vs bit 6 if 0) - | (0xFUL << DWT_CTRL_POSTINIT_Pos) // Post-tap counter - | (postpreset << DWT_CTRL_POSTPRESET_Pos) // Post-tap counter reload value - | (1UL << DWT_CTRL_CYCCNTENA_Pos)); // Enable cycle counter - // Set TPIU prescaler for the current debug clock frequency. ACPR value is div - 1. - TPI->ACPR = ((freq + (SL_DEBUG_SWO_FREQ / 2)) / SL_DEBUG_SWO_FREQ) - 1UL; - - // Set protocol to NRZ - TPI->SPPR = 2UL; - - // Disable continuous formatting - TPI->FFCR = TPI_FFCR_TrigIn_Msk; - - // Unlock ITM and output data - ITM->LAR = 0xC5ACCE55UL; - // CMSIS bitfield naming is inconsistent - 16U maps to - // ITM_TCR_TraceBusID_Pos (v7M) or ITM_TCR_TRACEBUSID_Pos (v8M) - ITM->TCR = ((1UL << 16U) - | (1UL << ITM_TCR_DWTENA_Pos) - | (1UL << ITM_TCR_ITMENA_Pos)); - - // Send data on the SWO channel. This avoids corrupting data - // sent on the SWO channel shortly after initialization. - ITM->TER |= (1UL << 8); - ITM->PORT[8].u8 = 0xFF; - ITM->TER &= ~(1UL << 8); - - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_enable_itm(uint32_t channel) -{ - ITM->TER |= (1UL << channel); - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_disable_itm(uint32_t channel) -{ - ITM->TER &= ~(1UL << channel); - return SL_STATUS_OK; -} - -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u8 = byte; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u16 = half_word; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) -{ - if (ITM->TCR & ITM_TCR_ITMENA_Msk) { - do { - // Some versions of JLink (erroneously) disable SWO when debug connections - // are closed. Re-enabling trace works around this. - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - - // Ensure ITM channel is enabled - ITM->TER |= (1UL << channel); - } while (ITM->PORT[channel].u32 == 0); - - ITM->PORT[channel].u32 = word; - - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_INITIALIZED; -} - -#else // __CORTEX_M - -sl_status_t sl_debug_swo_init(void) -{ - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_enable_itm(uint32_t channel) -{ - (void) channel; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_disable_itm(uint32_t channel) -{ - (void) channel; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) -{ - (void) channel; - (void) byte; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) -{ - (void) channel; - (void) half_word; - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) -{ - (void) channel; - (void) word; - return SL_STATUS_NOT_SUPPORTED; -} - -#endif // __CORTEX_M +/***************************************************************************//** + * @file + * @brief SWO debug + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_debug_swo.h" + +#include "em_device.h" + +#if defined(__CORTEX_M) && (__CORTEX_M >= 3) + +#if _SILICON_LABS_32B_SERIES <= 2 +#include "em_gpio.h" +#else +#include "sl_peripheral_gpio.h" +#endif + +#include "em_cmu.h" +#include "sl_debug_swo_config.h" + +sl_status_t sl_debug_swo_init(void) +{ + uint32_t freq = 0.0f; + uint16_t cyctap = 0U; + uint16_t postpreset = 0U; + +#if _SILICON_LABS_32B_SERIES <= 2 + unsigned int location = 0U; + CMU_ClockEnable(cmuClock_GPIO, true); + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) + // Series 0 + location = SL_DEBUG_ROUTE_LOC; + GPIO_PinModeSet(SL_DEBUG_SWO_PORT, SL_DEBUG_SWO_PIN, gpioModePushPull, 1); +#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) + // Series 1 + location = SL_DEBUG_SWV_LOC; + GPIO_PinModeSet(SL_DEBUG_SWV_PORT, SL_DEBUG_SWV_PIN, gpioModePushPull, 1); +#elif defined(GPIO_SWV_PORT) + // Series 2 + // SWO location is not configurable + GPIO_PinModeSet((GPIO_Port_TypeDef)GPIO_SWV_PORT, GPIO_SWV_PIN, gpioModePushPull, 1); +#endif + + // Set SWO location + GPIO_DbgLocationSet(location); + + // Enable SWO pin + GPIO_DbgSWOEnable(true); + +#else +#if defined(GPIO_SWV_PORT) + sl_gpio_set_pin_mode((sl_gpio_port_t)GPIO_SWV_PORT, GPIO_SWV_PIN, SL_GPIO_MODE_PUSH_PULL, 1); +#endif + + sl_gpio_enable_debug_swo(true); +#endif + +#if _SILICON_LABS_32B_SERIES < 2 + // Enable debug clock + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + + // Get debug clock frequency + freq = CMU_ClockFreqGet(cmuClock_DBG); +#else + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) +#if defined(_CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) +#if defined(CMU_CLKEN0_HFRCOEM23) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; +#endif + // Select HFRCOEM23 as source for TRACECLK + CMU_CLOCK_SELECT_SET(TRACECLK, HFRCOEM23); +#elif defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) + // Select SYSCLK as source for TRACECLK + CMU_CLOCK_SELECT_SET(TRACECLK, SYSCLK); +#endif +#endif + + freq = CMU_ClockFreqGet(cmuClock_TRACECLK); +#endif + + // Enable trace in core debug + CoreDebug->DHCSR |= CoreDebug_DHCSR_C_DEBUGEN_Msk; + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + //Tap the cyctap and postpreset based on the selected interval +#ifdef SL_DEBUG_SWO_SAMPLE_INTERVAL + if (SL_DEBUG_SWO_SAMPLE_INTERVAL <= 960) { + cyctap = 0; + postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 64); + } else { + cyctap = 1; + postpreset = (SL_DEBUG_SWO_SAMPLE_INTERVAL / 1024); + } +#else + cyctap = 1; + postpreset = 0xF; +#endif + // Enable PC and IRQ sampling output + DWT->CTRL = ((4UL << DWT_CTRL_NUMCOMP_Pos) // Number of comparators. Hardwired to 4. + | (SL_DEBUG_SWO_SAMPLE_IRQ << DWT_CTRL_EXCTRCENA_Pos) // Interrupt events + | (SL_DEBUG_SWO_SAMPLE_PC << DWT_CTRL_PCSAMPLENA_Pos) // PC sample events + | (cyctap << DWT_CTRL_CYCTAP_Pos) // Tap cycle counter at bit 10 (vs bit 6 if 0) + | (0xFUL << DWT_CTRL_POSTINIT_Pos) // Post-tap counter + | (postpreset << DWT_CTRL_POSTPRESET_Pos) // Post-tap counter reload value + | (1UL << DWT_CTRL_CYCCNTENA_Pos)); // Enable cycle counter + // Set TPIU prescaler for the current debug clock frequency. ACPR value is div - 1. + TPI->ACPR = ((freq + (SL_DEBUG_SWO_FREQ / 2)) / SL_DEBUG_SWO_FREQ) - 1UL; + + // Set protocol to NRZ + TPI->SPPR = 2UL; + + // Disable continuous formatting + TPI->FFCR = TPI_FFCR_TrigIn_Msk; + + // Unlock ITM and output data + ITM->LAR = 0xC5ACCE55UL; + // CMSIS bitfield naming is inconsistent - 16U maps to + // ITM_TCR_TraceBusID_Pos (v7M) or ITM_TCR_TRACEBUSID_Pos (v8M) + ITM->TCR = ((1UL << 16U) + | (1UL << ITM_TCR_DWTENA_Pos) + | (1UL << ITM_TCR_ITMENA_Pos)); + + // Send data on the SWO channel. This avoids corrupting data + // sent on the SWO channel shortly after initialization. + ITM->TER |= (1UL << 8); + ITM->PORT[8].u8 = 0xFF; + ITM->TER &= ~(1UL << 8); + + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_enable_itm(uint32_t channel) +{ + ITM->TER |= (1UL << channel); + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_disable_itm(uint32_t channel) +{ + ITM->TER &= ~(1UL << channel); + return SL_STATUS_OK; +} + +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u8 = byte; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u16 = half_word; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) +{ + if (ITM->TCR & ITM_TCR_ITMENA_Msk) { + do { + // Some versions of JLink (erroneously) disable SWO when debug connections + // are closed. Re-enabling trace works around this. + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Ensure ITM channel is enabled + ITM->TER |= (1UL << channel); + } while (ITM->PORT[channel].u32 == 0); + + ITM->PORT[channel].u32 = word; + + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_INITIALIZED; +} + +#else // __CORTEX_M + +sl_status_t sl_debug_swo_init(void) +{ + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_enable_itm(uint32_t channel) +{ + (void) channel; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_disable_itm(uint32_t channel) +{ + (void) channel; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u8(uint32_t channel, uint8_t byte) +{ + (void) channel; + (void) byte; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u16(uint32_t channel, uint16_t half_word) +{ + (void) channel; + (void) half_word; + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_debug_swo_write_u32(uint32_t channel, uint32_t word) +{ + (void) channel; + (void) word; + return SL_STATUS_NOT_SUPPORTED; +} + +#endif // __CORTEX_M diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h index 033400b..ac23ead 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/common/inc/ecode.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief Energy Aware drivers error code definitions. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef __SILICON_LABS_ECODE_H__ -#define __SILICON_LABS_ECODE_H__ - -#include - -/***************************************************************************//** - * @addtogroup ecode ECODE - Error Codes - * @details ECODE is set of error and status codes related to DMA, RTC, SPI, - * NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and - * status codes are used by the above listed drivers to update the layer - * (using the driver) about an error or status. - * - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief Typedef for API function error code return values. - * - * @details - * Bit 24-31: Component, for example emdrv @n - * Bit 16-23: Module, for example @ref uartdrv or @ref spidrv @n - * Bit 0-15: Error code - ******************************************************************************/ -typedef uint32_t Ecode_t; - -#define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. - -#define ECODE_OK (0U) ///< Generic success return value. - -#define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. -#define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. -#define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. -#define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. -#define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. -#define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. -#define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. -#define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. - -/** @} (end addtogroup ecode) */ - -#endif // __SILICON_LABS_ECODE_H__ +/***************************************************************************//** + * @file + * @brief Energy Aware drivers error code definitions. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef __SILICON_LABS_ECODE_H__ +#define __SILICON_LABS_ECODE_H__ + +#include + +/***************************************************************************//** + * @addtogroup ecode ECODE - Error Codes + * @details ECODE is set of error and status codes related to DMA, RTC, SPI, + * NVM, USTIMER, UARTDRV, EZRADIO, TEMP, and NVM3 drivers. These error and + * status codes are used by the above listed drivers to update the layer + * (using the driver) about an error or status. + * + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief Typedef for API function error code return values. + * + * @details + * Bit 24-31: Component, for example emdrv @n + * Bit 16-23: Module, for example @ref uartdrv or @ref spidrv @n + * Bit 0-15: Error code + ******************************************************************************/ +typedef uint32_t Ecode_t; + +#define ECODE_EMDRV_BASE (0xF0000000U) ///< Base value for all EMDRV errorcodes. + +#define ECODE_OK (0U) ///< Generic success return value. + +#define ECODE_EMDRV_SPIDRV_BASE (ECODE_EMDRV_BASE | 0x00002000U) ///< Base value for SPIDRV error codes. +#define ECODE_EMDRV_NVM_BASE (ECODE_EMDRV_BASE | 0x00003000U) ///< Base value for NVM error codes. +#define ECODE_EMDRV_USTIMER_BASE (ECODE_EMDRV_BASE | 0x00004000U) ///< Base value for USTIMER error codes. +#define ECODE_EMDRV_UARTDRV_BASE (ECODE_EMDRV_BASE | 0x00007000U) ///< Base value for UARTDRV error codes. +#define ECODE_EMDRV_DMADRV_BASE (ECODE_EMDRV_BASE | 0x00008000U) ///< Base value for DMADRV error codes. +#define ECODE_EMDRV_EZRADIODRV_BASE (ECODE_EMDRV_BASE | 0x00009000U) ///< Base value for EZRADIODRV error codes. +#define ECODE_EMDRV_TEMPDRV_BASE (ECODE_EMDRV_BASE | 0x0000D000U) ///< Base value for TEMPDRV error codes. +#define ECODE_EMDRV_NVM3_BASE (ECODE_EMDRV_BASE | 0x0000E000U) ///< Base value for NVM3 error codes. + +/** @} (end addtogroup ecode) */ + +#endif // __SILICON_LABS_ECODE_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h index e03d466..99d9b07 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/inc/dmadrv.h @@ -1,1047 +1,1047 @@ -/***************************************************************************//** - * @file - * @brief DMADRV API definition. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __SILICON_LABS_DMADRV_H__ -#define __SILICON_LABS_DMADRV_H__ - -#include "em_device.h" -#include "ecode.h" -#include "sl_enum.h" - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define EMDRV_DMADRV_UDMA -#define EMDRV_DMADRV_DMA_PRESENT -#include "em_dma.h" -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#if (_SILICON_LABS_32B_SERIES > 2) -#define EMDRV_DMADRV_LDMA_S3 -#include "sl_peripheral_ldma.h" -#else -#define EMDRV_DMADRV_DMA_PRESENT -#define EMDRV_DMADRV_LDMA -#include "em_ldma.h" -#endif - -#else -#error "No valid DMA engine defined." -#endif - -#include "dmadrv_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup dmadrv - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup dmadrv_error_codes Error Codes - * @{ - ******************************************************************************/ - -#define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. -#define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. -#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. -#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. -#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. -#define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. -#define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. -#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. - -/** @} (end addtogroup error codes) */ -/***************************************************************************//** - * @brief - * DMADRV transfer completion callback function. - * - * @details - * The callback function is called when a transfer is complete. - * - * @param[in] channel - * The DMA channel number. - * - * @param[in] sequenceNo - * The number of times the callback was called. Useful on long chains of - * linked transfers or on endless ping-pong type transfers. - * - * @param[in] userParam - * Optional user parameter supplied on DMA invocation. - * - * @return - * When doing ping-pong transfers, return true to continue or false to - * stop transfers. - ******************************************************************************/ -typedef bool (*DMADRV_Callback_t)(unsigned int channel, - unsigned int sequenceNo, - void *userParam); - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) - -/// Maximum length of one DMA transfer. -#define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1)) - -/// Peripherals that can trigger UDMA transfers. -#ifdef DOXY_DOC_ONLY -SL_ENUM_GENERIC(DMADRV_Peripheralsignal_t, uint32_t) { -#else -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { -#endif - dmadrvPeripheralSignal_NONE = 0, ///< No peripheral selected for DMA triggering. - #if defined(DMAREQ_ADC0_SCAN) - dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN, ///< Trig on ADC0_SCAN. - #endif - #if defined(DMAREQ_ADC0_SINGLE) - dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE, ///< Trig on ADC0_SINGLE. - #endif - #if defined(DMAREQ_AES_DATARD) - dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD, ///< Trig on AES_DATARD. - #endif - #if defined(DMAREQ_AES_DATAWR) - dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR, ///< Trig on AES_DATAWR. - #endif - #if defined(DMAREQ_AES_KEYWR) - dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR, ///< Trig on AES_KEYWR. - #endif - #if defined(DMAREQ_AES_XORDATAWR) - dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR, ///< Trig on AES_XORDATAWR. - #endif - #if defined(DMAREQ_DAC0_CH0) - dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0, ///< Trig on DAC0_CH0. - #endif - #if defined(DMAREQ_DAC0_CH1) - dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1, ///< Trig on DAC0_CH1. - #endif - #if defined(DMAREQ_EBI_DDEMPTY) - dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY, ///< Trig on EBI_DDEMPTY. - #endif - #if defined(DMAREQ_EBI_PXL0EMPTY) - dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY, ///< Trig on EBI_PXL0EMPTY. - #endif - #if defined(DMAREQ_EBI_PXL1EMPTY) - dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY, ///< Trig on EBI_PXL1EMPTY. - #endif - #if defined(DMAREQ_EBI_PXLFULL) - dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL, ///< Trig on EBI_PXLFULL. - #endif - #if defined(DMAREQ_I2C0_RXDATAV) - dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV, ///< Trig on I2C0_RXDATAV. - #endif - #if defined(DMAREQ_I2C0_TXBL) - dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL, ///< Trig on I2C0_TXBL. - #endif - #if defined(DMAREQ_I2C1_RXDATAV) - dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV, ///< Trig on I2C1_RXDATAV. - #endif - #if defined(DMAREQ_I2C1_TXBL) - dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL, ///< Trig on I2C1_TXBL. - #endif - #if defined(DMAREQ_LESENSE_BUFDATAV) - dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV, ///< Trig on LESENSE_BUFDATAV. - #endif - #if defined(DMAREQ_LEUART0_RXDATAV) - dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV, ///< Trig on LEUART0_RXDATAV. - #endif - #if defined(DMAREQ_LEUART0_TXBL) - dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL, ///< Trig on LEUART0_TXBL. - #endif - #if defined(DMAREQ_LEUART0_TXEMPTY) - dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY, ///< Trig on LEUART0_TXEMPTY. - #endif - #if defined(DMAREQ_LEUART1_RXDATAV) - dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV, ///< Trig on LEUART1_RXDATAV. - #endif - #if defined(DMAREQ_LEUART1_TXBL) - dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL, ///< Trig on LEUART1_TXBL. - #endif - #if defined(DMAREQ_LEUART1_TXEMPTY) - dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY, ///< Trig on LEUART1_TXEMPTY. - #endif - #if defined(DMAREQ_MSC_WDATA) - dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA, ///< Trig on MSC_WDATA. - #endif - #if defined(DMAREQ_TIMER0_CC0) - dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0, ///< Trig on TIMER0_CC0. - #endif - #if defined(DMAREQ_TIMER0_CC1) - dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1, ///< Trig on TIMER0_CC1. - #endif - #if defined(DMAREQ_TIMER0_CC2) - dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2, ///< Trig on TIMER0_CC2. - #endif - #if defined(DMAREQ_TIMER0_UFOF) - dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF, ///< Trig on TIMER0_UFOF. - #endif - #if defined(DMAREQ_TIMER1_CC0) - dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0, ///< Trig on TIMER1_CC0. - #endif - #if defined(DMAREQ_TIMER1_CC1) - dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1, ///< Trig on TIMER1_CC1. - #endif - #if defined(DMAREQ_TIMER1_CC2) - dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2, ///< Trig on TIMER1_CC2. - #endif - #if defined(DMAREQ_TIMER1_UFOF) - dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF, ///< Trig on TIMER1_UFOF. - #endif - #if defined(DMAREQ_TIMER2_CC0) - dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0, ///< Trig on TIMER2_CC0. - #endif - #if defined(DMAREQ_TIMER2_CC1) - dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1, ///< Trig on TIMER2_CC1. - #endif - #if defined(DMAREQ_TIMER2_CC2) - dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2, ///< Trig on TIMER2_CC2. - #endif - #if defined(DMAREQ_TIMER2_UFOF) - dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF, ///< Trig on TIMER2_UFOF. - #endif - #if defined(DMAREQ_TIMER3_CC0) - dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0, ///< Trig on TIMER3_CC0. - #endif - #if defined(DMAREQ_TIMER3_CC1) - dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1, ///< Trig on TIMER3_CC1. - #endif - #if defined(DMAREQ_TIMER3_CC2) - dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2, ///< Trig on TIMER3_CC2. - #endif - #if defined(DMAREQ_TIMER3_UFOF) - dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF, ///< Trig on TIMER3_UFOF. - #endif - #if defined(DMAREQ_UART0_RXDATAV) - dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV, ///< Trig on UART0_RXDATAV. - #endif - #if defined(DMAREQ_UART0_TXBL) - dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL, ///< Trig on UART0_TXBL. - #endif - #if defined(DMAREQ_UART0_TXEMPTY) - dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY, ///< Trig on UART0_TXEMPTY. - #endif - #if defined(DMAREQ_UART1_RXDATAV) - dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV, ///< Trig on UART1_RXDATAV. - #endif - #if defined(DMAREQ_UART1_TXBL) - dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL, ///< Trig on UART1_TXBL. - #endif - #if defined(DMAREQ_UART1_TXEMPTY) - dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY, ///< Trig on UART1_TXEMPTY. - #endif - #if defined(DMAREQ_USART0_RXDATAV) - dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV, ///< Trig on USART0_RXDATAV. - #endif - #if defined(DMAREQ_USART0_TXBL) - dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL, ///< Trig on USART0_TXBL. - #endif - #if defined(DMAREQ_USART0_TXEMPTY) - dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY, ///< Trig on USART0_TXEMPTY. - #endif - #if defined(DMAREQ_USARTRF0_RXDATAV) - dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV, ///< Trig on USARTRF0_RXDATAV. - #endif - #if defined(DMAREQ_USARTRF0_TXBL) - dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL, ///< Trig on USARTRF0_TXBL. - #endif - #if defined(DMAREQ_USARTRF0_TXEMPTY) - dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY, ///< Trig on USARTRF0_TXEMPTY. - #endif - #if defined(DMAREQ_USARTRF1_RXDATAV) - dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV, ///< Trig on USARTRF1_RXDATAV. - #endif - #if defined(DMAREQ_USARTRF1_TXBL) - dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL, ///< Trig on USARTRF1_TXBL. - #endif - #if defined(DMAREQ_USARTRF1_TXEMPTY) - dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY, ///< Trig on USARTRF1_TXEMPTY. - #endif - #if defined(DMAREQ_USART1_RXDATAV) - dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV, ///< Trig on USART1_RXDATAV. - #endif - #if defined(DMAREQ_USART1_RXDATAVRIGHT) - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,///< Trig on USART1_RXDATAVRIGHT. - #endif - #if defined(DMAREQ_USART1_TXBL) - dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL, ///< Trig on USART1_TXBL. - #endif - #if defined(DMAREQ_USART1_TXBLRIGHT) - dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT, ///< Trig on USART1_TXBLRIGHT. - #endif - #if defined(DMAREQ_USART1_TXEMPTY) - dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY, ///< Trig on USART1_TXEMPTY. - #endif - #if defined(DMAREQ_USART2_RXDATAV) - dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV, ///< Trig on USART2_RXDATAV. - #endif - #if defined(DMAREQ_USART2_RXDATAVRIGHT) - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,///< Trig on USART2_RXDATAVRIGHT. - #endif - #if defined(DMAREQ_USART2_TXBL) - dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL, ///< Trig on USART2_TXBL. - #endif - #if defined(DMAREQ_USART2_TXBLRIGHT) - dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT, ///< Trig on USART2_TXBLRIGHT. - #endif - #if defined(DMAREQ_USART2_TXEMPTY) - dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY, ///< Trig on USART2_TXEMPTY. - #endif -}; - -/// Data size of one UDMA transfer item. -#ifdef DOXY_DOC_ONLY -SL_ENUM(DMADRV_Datasize_t) { -#else -SL_ENUM(DMADRV_DataSize_t) { -#endif - dmadrvDataSize1 = dmaDataSize1, ///< Byte - dmadrvDataSize2 = dmaDataSize2, ///< Halfword - dmadrvDataSize4 = dmaDataSize4 ///< Word -}; - -#endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 ) - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -/// Maximum length of one DMA transfer. -#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) - -#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) -/// Peripherals that can trigger LDMA transfers. -// TODO CM see if need to add stuff for Rainier XBAR -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { - dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 - dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 - dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 - dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF - dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 - dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 - dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 - dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF - dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV - dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT - dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL - dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT - dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY - dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV - dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL - dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT - dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY - dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV - dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL - dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT - dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY - dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV - dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL - dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV - dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL - dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI - dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF - dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 - dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 - dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 - dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 - dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 - dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF - dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF - dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG - dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN - dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE - dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA - dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 - dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 - dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 - dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF - dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 - dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 - dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 - dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF - dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL - dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL - dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL - dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL - dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL - dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL - dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL - dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL - dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL - dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL - dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART3_RXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL - dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL - dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_RXBL. - #endif -}; - -#else -/// Peripherals that can trigger LDMA transfers. -SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { - dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) - dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) - dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) - dmadrvPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) - dmadrvPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) - dmadrvPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0 - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) - dmadrvPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1 - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_AGCRSSI) - dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) - dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) - dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) - dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) - dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) - dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) - dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) - dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) - dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) - dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) - dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) - dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) - dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) - dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) - dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) - dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) - dmadrvPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) - dmadrvPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) - dmadrvPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) - dmadrvPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) - dmadrvPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) - dmadrvPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) - dmadrvPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) - dmadrvPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV) - dmadrvPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) - dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) - dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) - dmadrvPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) - dmadrvPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) - dmadrvPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) - dmadrvPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) - dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) - dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) - dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) - dmadrvPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) - dmadrvPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) - dmadrvPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG) - dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) - dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF) - dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0) - dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1) - dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2) - dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3) - dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4) - dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF) - dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF) - dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) - dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) - dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) - dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) - dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) - dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC3) - dmadrvPeripheralSignal_TIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) - dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) - dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) - dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) - dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) - dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) - dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) - dmadrvPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) - dmadrvPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) - dmadrvPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC3) - dmadrvPeripheralSignal_TIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) - dmadrvPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) - dmadrvPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) - dmadrvPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) - dmadrvPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC3) - dmadrvPeripheralSignal_TIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) - dmadrvPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) - dmadrvPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) - dmadrvPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) - dmadrvPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC3) - dmadrvPeripheralSignal_TIMER4_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) - dmadrvPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) - dmadrvPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) - dmadrvPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) - dmadrvPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC3) - dmadrvPeripheralSignal_TIMER5_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) - dmadrvPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) - dmadrvPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) - dmadrvPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) - dmadrvPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC3) - dmadrvPeripheralSignal_TIMER6_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) - dmadrvPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) - dmadrvPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) - dmadrvPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) - dmadrvPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3) - dmadrvPeripheralSignal_WTIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) - dmadrvPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) - dmadrvPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) - dmadrvPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) - dmadrvPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) - dmadrvPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) - dmadrvPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) - dmadrvPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) - dmadrvPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) - dmadrvPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3) - dmadrvPeripheralSignal_WTIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) - dmadrvPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) - dmadrvPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) - dmadrvPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) - dmadrvPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3) - dmadrvPeripheralSignal_WTIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) - dmadrvPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) - dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) - dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) - dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) - dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) - dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) - dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) - dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) - dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) - dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT) - dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) - dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT) - dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) - dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) - dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) - dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) - dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) - dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) - dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) - dmadrvPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) - dmadrvPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) - dmadrvPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) - dmadrvPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) - dmadrvPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) - dmadrvPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT) - dmadrvPeripheralSignal_USART5_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) - dmadrvPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT) - dmadrvPeripheralSignal_USART5_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) - dmadrvPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) - dmadrvPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) - dmadrvPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) - dmadrvPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) - dmadrvPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) - dmadrvPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) - dmadrvPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1 ///< Trig on UART1_TXEMPTY. - #endif -}; -#endif - -/// Data size of one LDMA transfer item. -SL_ENUM(DMADRV_DataSize_t) { -#if defined(EMDRV_DMADRV_LDMA_S3) - dmadrvDataSize1 = SL_HAL_LDMA_CTRL_SIZE_BYTE, ///< Byte - dmadrvDataSize2 = SL_HAL_LDMA_CTRL_SIZE_HALF, ///< Halfword - dmadrvDataSize4 = SL_HAL_LDMA_CTRL_SIZE_WORD ///< Word -#else - dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte - dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword - dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word -#endif -}; - -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ - -Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, - void *capabilities); -Ecode_t DMADRV_DeInit(void); -Ecode_t DMADRV_FreeChannel(unsigned int channelId); -Ecode_t DMADRV_Init(void); - -Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst, - void *src0, - void *src1, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); -Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *dst0, - void *dst1, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); - -#if defined(EMDRV_DMADRV_LDMA) -Ecode_t DMADRV_LdmaStartTransfer(int channelId, - LDMA_TransferCfg_t *transfer, - LDMA_Descriptor_t *descriptor, - DMADRV_Callback_t callback, - void *cbUserParam); -#endif - -Ecode_t DMADRV_PauseTransfer(unsigned int channelId); -Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); -Ecode_t DMADRV_StopTransfer(unsigned int channelId); -Ecode_t DMADRV_TransferActive(unsigned int channelId, - bool *active); -Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, - bool *pending); -Ecode_t DMADRV_TransferDone(unsigned int channelId, - bool *done); -Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, - int *remaining); - -/** @} (end addtogroup dmadrv) */ - -#ifdef __cplusplus -} -#endif - -#endif /* __SILICON_LABS_DMADRV_H__ */ +/***************************************************************************//** + * @file + * @brief DMADRV API definition. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __SILICON_LABS_DMADRV_H__ +#define __SILICON_LABS_DMADRV_H__ + +#include "em_device.h" +#include "ecode.h" +#include "sl_enum.h" + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define EMDRV_DMADRV_UDMA +#define EMDRV_DMADRV_DMA_PRESENT +#include "em_dma.h" +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#if (_SILICON_LABS_32B_SERIES > 2) +#define EMDRV_DMADRV_LDMA_S3 +#include "sl_peripheral_ldma.h" +#else +#define EMDRV_DMADRV_DMA_PRESENT +#define EMDRV_DMADRV_LDMA +#include "em_ldma.h" +#endif + +#else +#error "No valid DMA engine defined." +#endif + +#include "dmadrv_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dmadrv + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup dmadrv_error_codes Error Codes + * @{ + ******************************************************************************/ + +#define ECODE_EMDRV_DMADRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_DMADRV_PARAM_ERROR (ECODE_EMDRV_DMADRV_BASE | 0x00000001) ///< An illegal input parameter. +#define ECODE_EMDRV_DMADRV_NOT_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000002) ///< DMA is not initialized. +#define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED (ECODE_EMDRV_DMADRV_BASE | 0x00000003) ///< DMA has already been initialized. +#define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED (ECODE_EMDRV_DMADRV_BASE | 0x00000004) ///< No DMA channels available. +#define ECODE_EMDRV_DMADRV_IN_USE (ECODE_EMDRV_DMADRV_BASE | 0x00000005) ///< DMA is in use. +#define ECODE_EMDRV_DMADRV_ALREADY_FREED (ECODE_EMDRV_DMADRV_BASE | 0x00000006) ///< A DMA channel was free. +#define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED (ECODE_EMDRV_DMADRV_BASE | 0x00000007) ///< A channel is not reserved. + +/** @} (end addtogroup error codes) */ +/***************************************************************************//** + * @brief + * DMADRV transfer completion callback function. + * + * @details + * The callback function is called when a transfer is complete. + * + * @param[in] channel + * The DMA channel number. + * + * @param[in] sequenceNo + * The number of times the callback was called. Useful on long chains of + * linked transfers or on endless ping-pong type transfers. + * + * @param[in] userParam + * Optional user parameter supplied on DMA invocation. + * + * @return + * When doing ping-pong transfers, return true to continue or false to + * stop transfers. + ******************************************************************************/ +typedef bool (*DMADRV_Callback_t)(unsigned int channel, + unsigned int sequenceNo, + void *userParam); + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) + +/// Maximum length of one DMA transfer. +#define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1)) + +/// Peripherals that can trigger UDMA transfers. +#ifdef DOXY_DOC_ONLY +SL_ENUM_GENERIC(DMADRV_Peripheralsignal_t, uint32_t) { +#else +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { +#endif + dmadrvPeripheralSignal_NONE = 0, ///< No peripheral selected for DMA triggering. + #if defined(DMAREQ_ADC0_SCAN) + dmadrvPeripheralSignal_ADC0_SCAN = DMAREQ_ADC0_SCAN, ///< Trig on ADC0_SCAN. + #endif + #if defined(DMAREQ_ADC0_SINGLE) + dmadrvPeripheralSignal_ADC0_SINGLE = DMAREQ_ADC0_SINGLE, ///< Trig on ADC0_SINGLE. + #endif + #if defined(DMAREQ_AES_DATARD) + dmadrvPeripheralSignal_AES_DATARD = DMAREQ_AES_DATARD, ///< Trig on AES_DATARD. + #endif + #if defined(DMAREQ_AES_DATAWR) + dmadrvPeripheralSignal_AES_DATAWR = DMAREQ_AES_DATAWR, ///< Trig on AES_DATAWR. + #endif + #if defined(DMAREQ_AES_KEYWR) + dmadrvPeripheralSignal_AES_KEYWR = DMAREQ_AES_KEYWR, ///< Trig on AES_KEYWR. + #endif + #if defined(DMAREQ_AES_XORDATAWR) + dmadrvPeripheralSignal_AES_XORDATAWR = DMAREQ_AES_XORDATAWR, ///< Trig on AES_XORDATAWR. + #endif + #if defined(DMAREQ_DAC0_CH0) + dmadrvPeripheralSignal_DAC0_CH0 = DMAREQ_DAC0_CH0, ///< Trig on DAC0_CH0. + #endif + #if defined(DMAREQ_DAC0_CH1) + dmadrvPeripheralSignal_DAC0_CH1 = DMAREQ_DAC0_CH1, ///< Trig on DAC0_CH1. + #endif + #if defined(DMAREQ_EBI_DDEMPTY) + dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY, ///< Trig on EBI_DDEMPTY. + #endif + #if defined(DMAREQ_EBI_PXL0EMPTY) + dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY, ///< Trig on EBI_PXL0EMPTY. + #endif + #if defined(DMAREQ_EBI_PXL1EMPTY) + dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY, ///< Trig on EBI_PXL1EMPTY. + #endif + #if defined(DMAREQ_EBI_PXLFULL) + dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL, ///< Trig on EBI_PXLFULL. + #endif + #if defined(DMAREQ_I2C0_RXDATAV) + dmadrvPeripheralSignal_I2C0_RXDATAV = DMAREQ_I2C0_RXDATAV, ///< Trig on I2C0_RXDATAV. + #endif + #if defined(DMAREQ_I2C0_TXBL) + dmadrvPeripheralSignal_I2C0_TXBL = DMAREQ_I2C0_TXBL, ///< Trig on I2C0_TXBL. + #endif + #if defined(DMAREQ_I2C1_RXDATAV) + dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(DMAREQ_I2C1_TXBL) + dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL, ///< Trig on I2C1_TXBL. + #endif + #if defined(DMAREQ_LESENSE_BUFDATAV) + dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(DMAREQ_LEUART0_RXDATAV) + dmadrvPeripheralSignal_LEUART0_RXDATAV = DMAREQ_LEUART0_RXDATAV, ///< Trig on LEUART0_RXDATAV. + #endif + #if defined(DMAREQ_LEUART0_TXBL) + dmadrvPeripheralSignal_LEUART0_TXBL = DMAREQ_LEUART0_TXBL, ///< Trig on LEUART0_TXBL. + #endif + #if defined(DMAREQ_LEUART0_TXEMPTY) + dmadrvPeripheralSignal_LEUART0_TXEMPTY = DMAREQ_LEUART0_TXEMPTY, ///< Trig on LEUART0_TXEMPTY. + #endif + #if defined(DMAREQ_LEUART1_RXDATAV) + dmadrvPeripheralSignal_LEUART1_RXDATAV = DMAREQ_LEUART1_RXDATAV, ///< Trig on LEUART1_RXDATAV. + #endif + #if defined(DMAREQ_LEUART1_TXBL) + dmadrvPeripheralSignal_LEUART1_TXBL = DMAREQ_LEUART1_TXBL, ///< Trig on LEUART1_TXBL. + #endif + #if defined(DMAREQ_LEUART1_TXEMPTY) + dmadrvPeripheralSignal_LEUART1_TXEMPTY = DMAREQ_LEUART1_TXEMPTY, ///< Trig on LEUART1_TXEMPTY. + #endif + #if defined(DMAREQ_MSC_WDATA) + dmadrvPeripheralSignal_MSC_WDATA = DMAREQ_MSC_WDATA, ///< Trig on MSC_WDATA. + #endif + #if defined(DMAREQ_TIMER0_CC0) + dmadrvPeripheralSignal_TIMER0_CC0 = DMAREQ_TIMER0_CC0, ///< Trig on TIMER0_CC0. + #endif + #if defined(DMAREQ_TIMER0_CC1) + dmadrvPeripheralSignal_TIMER0_CC1 = DMAREQ_TIMER0_CC1, ///< Trig on TIMER0_CC1. + #endif + #if defined(DMAREQ_TIMER0_CC2) + dmadrvPeripheralSignal_TIMER0_CC2 = DMAREQ_TIMER0_CC2, ///< Trig on TIMER0_CC2. + #endif + #if defined(DMAREQ_TIMER0_UFOF) + dmadrvPeripheralSignal_TIMER0_UFOF = DMAREQ_TIMER0_UFOF, ///< Trig on TIMER0_UFOF. + #endif + #if defined(DMAREQ_TIMER1_CC0) + dmadrvPeripheralSignal_TIMER1_CC0 = DMAREQ_TIMER1_CC0, ///< Trig on TIMER1_CC0. + #endif + #if defined(DMAREQ_TIMER1_CC1) + dmadrvPeripheralSignal_TIMER1_CC1 = DMAREQ_TIMER1_CC1, ///< Trig on TIMER1_CC1. + #endif + #if defined(DMAREQ_TIMER1_CC2) + dmadrvPeripheralSignal_TIMER1_CC2 = DMAREQ_TIMER1_CC2, ///< Trig on TIMER1_CC2. + #endif + #if defined(DMAREQ_TIMER1_UFOF) + dmadrvPeripheralSignal_TIMER1_UFOF = DMAREQ_TIMER1_UFOF, ///< Trig on TIMER1_UFOF. + #endif + #if defined(DMAREQ_TIMER2_CC0) + dmadrvPeripheralSignal_TIMER2_CC0 = DMAREQ_TIMER2_CC0, ///< Trig on TIMER2_CC0. + #endif + #if defined(DMAREQ_TIMER2_CC1) + dmadrvPeripheralSignal_TIMER2_CC1 = DMAREQ_TIMER2_CC1, ///< Trig on TIMER2_CC1. + #endif + #if defined(DMAREQ_TIMER2_CC2) + dmadrvPeripheralSignal_TIMER2_CC2 = DMAREQ_TIMER2_CC2, ///< Trig on TIMER2_CC2. + #endif + #if defined(DMAREQ_TIMER2_UFOF) + dmadrvPeripheralSignal_TIMER2_UFOF = DMAREQ_TIMER2_UFOF, ///< Trig on TIMER2_UFOF. + #endif + #if defined(DMAREQ_TIMER3_CC0) + dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0, ///< Trig on TIMER3_CC0. + #endif + #if defined(DMAREQ_TIMER3_CC1) + dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1, ///< Trig on TIMER3_CC1. + #endif + #if defined(DMAREQ_TIMER3_CC2) + dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2, ///< Trig on TIMER3_CC2. + #endif + #if defined(DMAREQ_TIMER3_UFOF) + dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF, ///< Trig on TIMER3_UFOF. + #endif + #if defined(DMAREQ_UART0_RXDATAV) + dmadrvPeripheralSignal_UART0_RXDATAV = DMAREQ_UART0_RXDATAV, ///< Trig on UART0_RXDATAV. + #endif + #if defined(DMAREQ_UART0_TXBL) + dmadrvPeripheralSignal_UART0_TXBL = DMAREQ_UART0_TXBL, ///< Trig on UART0_TXBL. + #endif + #if defined(DMAREQ_UART0_TXEMPTY) + dmadrvPeripheralSignal_UART0_TXEMPTY = DMAREQ_UART0_TXEMPTY, ///< Trig on UART0_TXEMPTY. + #endif + #if defined(DMAREQ_UART1_RXDATAV) + dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV, ///< Trig on UART1_RXDATAV. + #endif + #if defined(DMAREQ_UART1_TXBL) + dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL, ///< Trig on UART1_TXBL. + #endif + #if defined(DMAREQ_UART1_TXEMPTY) + dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY, ///< Trig on UART1_TXEMPTY. + #endif + #if defined(DMAREQ_USART0_RXDATAV) + dmadrvPeripheralSignal_USART0_RXDATAV = DMAREQ_USART0_RXDATAV, ///< Trig on USART0_RXDATAV. + #endif + #if defined(DMAREQ_USART0_TXBL) + dmadrvPeripheralSignal_USART0_TXBL = DMAREQ_USART0_TXBL, ///< Trig on USART0_TXBL. + #endif + #if defined(DMAREQ_USART0_TXEMPTY) + dmadrvPeripheralSignal_USART0_TXEMPTY = DMAREQ_USART0_TXEMPTY, ///< Trig on USART0_TXEMPTY. + #endif + #if defined(DMAREQ_USARTRF0_RXDATAV) + dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV, ///< Trig on USARTRF0_RXDATAV. + #endif + #if defined(DMAREQ_USARTRF0_TXBL) + dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL, ///< Trig on USARTRF0_TXBL. + #endif + #if defined(DMAREQ_USARTRF0_TXEMPTY) + dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY, ///< Trig on USARTRF0_TXEMPTY. + #endif + #if defined(DMAREQ_USARTRF1_RXDATAV) + dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV, ///< Trig on USARTRF1_RXDATAV. + #endif + #if defined(DMAREQ_USARTRF1_TXBL) + dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL, ///< Trig on USARTRF1_TXBL. + #endif + #if defined(DMAREQ_USARTRF1_TXEMPTY) + dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY, ///< Trig on USARTRF1_TXEMPTY. + #endif + #if defined(DMAREQ_USART1_RXDATAV) + dmadrvPeripheralSignal_USART1_RXDATAV = DMAREQ_USART1_RXDATAV, ///< Trig on USART1_RXDATAV. + #endif + #if defined(DMAREQ_USART1_RXDATAVRIGHT) + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,///< Trig on USART1_RXDATAVRIGHT. + #endif + #if defined(DMAREQ_USART1_TXBL) + dmadrvPeripheralSignal_USART1_TXBL = DMAREQ_USART1_TXBL, ///< Trig on USART1_TXBL. + #endif + #if defined(DMAREQ_USART1_TXBLRIGHT) + dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT, ///< Trig on USART1_TXBLRIGHT. + #endif + #if defined(DMAREQ_USART1_TXEMPTY) + dmadrvPeripheralSignal_USART1_TXEMPTY = DMAREQ_USART1_TXEMPTY, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(DMAREQ_USART2_RXDATAV) + dmadrvPeripheralSignal_USART2_RXDATAV = DMAREQ_USART2_RXDATAV, ///< Trig on USART2_RXDATAV. + #endif + #if defined(DMAREQ_USART2_RXDATAVRIGHT) + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,///< Trig on USART2_RXDATAVRIGHT. + #endif + #if defined(DMAREQ_USART2_TXBL) + dmadrvPeripheralSignal_USART2_TXBL = DMAREQ_USART2_TXBL, ///< Trig on USART2_TXBL. + #endif + #if defined(DMAREQ_USART2_TXBLRIGHT) + dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT, ///< Trig on USART2_TXBLRIGHT. + #endif + #if defined(DMAREQ_USART2_TXEMPTY) + dmadrvPeripheralSignal_USART2_TXEMPTY = DMAREQ_USART2_TXEMPTY, ///< Trig on USART2_TXEMPTY. + #endif +}; + +/// Data size of one UDMA transfer item. +#ifdef DOXY_DOC_ONLY +SL_ENUM(DMADRV_Datasize_t) { +#else +SL_ENUM(DMADRV_DataSize_t) { +#endif + dmadrvDataSize1 = dmaDataSize1, ///< Byte + dmadrvDataSize2 = dmaDataSize2, ///< Halfword + dmadrvDataSize4 = dmaDataSize4 ///< Word +}; + +#endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 ) + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +/// Maximum length of one DMA transfer. +#define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) +/// Peripherals that can trigger LDMA transfers. +// TODO CM see if need to add stuff for Rainier XBAR +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { + dmadrvPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + dmadrvPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + dmadrvPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + dmadrvPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + dmadrvPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + dmadrvPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + dmadrvPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + dmadrvPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + dmadrvPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + dmadrvPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + dmadrvPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + dmadrvPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + dmadrvPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + dmadrvPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + dmadrvPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + dmadrvPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + dmadrvPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + dmadrvPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + dmadrvPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + dmadrvPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + dmadrvPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + dmadrvPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + dmadrvPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + dmadrvPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + dmadrvPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + dmadrvPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + dmadrvPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + dmadrvPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + dmadrvPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + dmadrvPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + dmadrvPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + dmadrvPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + dmadrvPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + dmadrvPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + dmadrvPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + dmadrvPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA + dmadrvPeripheralSignal_IMEM_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_IMEMWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_IMEM, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + dmadrvPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + dmadrvPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + dmadrvPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + dmadrvPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + dmadrvPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + dmadrvPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + dmadrvPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + dmadrvPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + dmadrvPeripheralSignal_EUART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + dmadrvPeripheralSignal_EUART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + dmadrvPeripheralSignal_EUSART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + dmadrvPeripheralSignal_EUSART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trig on EUART0_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + dmadrvPeripheralSignal_EUSART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + dmadrvPeripheralSignal_EUSART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trig on EUART1_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + dmadrvPeripheralSignal_EUSART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + dmadrvPeripheralSignal_EUSART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trig on EUART2_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + dmadrvPeripheralSignal_EUSART3_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + dmadrvPeripheralSignal_EUSART3_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trig on EUART3_RXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + dmadrvPeripheralSignal_EUSART4_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + dmadrvPeripheralSignal_EUSART4_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trig on EUART4_RXBL. + #endif +}; + +#else +/// Peripherals that can trigger LDMA transfers. +SL_ENUM_GENERIC(DMADRV_PeripheralSignal_t, uint32_t) { + dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) + dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) + dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trig on ADC0_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) + dmadrvPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) + dmadrvPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trig on ADC1_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + dmadrvPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH0 + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + dmadrvPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trig on VDAC0_CH1 + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_AGCRSSI) + dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC, ///< Trig on AGC_RSSI. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) + dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) + dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) + dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) + dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) + dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trig on CRYPTO_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + dmadrvPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + dmadrvPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + dmadrvPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + dmadrvPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + dmadrvPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trig on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + dmadrvPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + dmadrvPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + dmadrvPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + dmadrvPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + dmadrvPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trig on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) + dmadrvPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL0EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) + dmadrvPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXL1EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) + dmadrvPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_PXLFULL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) + dmadrvPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_DDEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) + dmadrvPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_VSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) + dmadrvPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trig on EBI_HSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + dmadrvPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + dmadrvPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trig on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV) + dmadrvPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LSENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trig on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trig on I2C0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + dmadrvPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + dmadrvPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trig on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) + dmadrvPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) + dmadrvPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trig on I2C2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trig on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) + dmadrvPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) + dmadrvPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) + dmadrvPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trig on LEUART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG) + dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM, ///< Trig on MODEM_DEBUG. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trig on MSC_WDATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF) + dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_BOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0) + dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1) + dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2) + dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3) + dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4) + dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_CC4. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF) + dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_POF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF) + dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trig on PROTIMER_WOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) + dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) + dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trig on PRS_REQ1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) + dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) + dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) + dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC3) + dmadrvPeripheralSignal_TIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) + dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trig on TIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) + dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) + dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) + dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) + dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) + dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trig on TIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) + dmadrvPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) + dmadrvPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) + dmadrvPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC3) + dmadrvPeripheralSignal_TIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) + dmadrvPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trig on TIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) + dmadrvPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) + dmadrvPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) + dmadrvPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC3) + dmadrvPeripheralSignal_TIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) + dmadrvPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trig on TIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) + dmadrvPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) + dmadrvPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) + dmadrvPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC3) + dmadrvPeripheralSignal_TIMER4_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) + dmadrvPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trig on TIMER4_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) + dmadrvPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) + dmadrvPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) + dmadrvPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC3) + dmadrvPeripheralSignal_TIMER5_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) + dmadrvPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trig on TIMER5_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) + dmadrvPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) + dmadrvPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) + dmadrvPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC3) + dmadrvPeripheralSignal_TIMER6_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) + dmadrvPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trig on TIMER6_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + dmadrvPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + dmadrvPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + dmadrvPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3) + dmadrvPeripheralSignal_WTIMER0_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + dmadrvPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trig on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + dmadrvPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + dmadrvPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + dmadrvPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + dmadrvPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + dmadrvPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trig on WTIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) + dmadrvPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) + dmadrvPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) + dmadrvPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3) + dmadrvPeripheralSignal_WTIMER2_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) + dmadrvPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trig on WTIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) + dmadrvPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) + dmadrvPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) + dmadrvPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3) + dmadrvPeripheralSignal_WTIMER3_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) + dmadrvPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trig on WTIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) + dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) + dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) + dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trig on USART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) + dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) + dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) + dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) + dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trig on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + dmadrvPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT) + dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + dmadrvPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT) + dmadrvPeripheralSignal_USART2_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + dmadrvPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trig on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + dmadrvPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + dmadrvPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + dmadrvPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + dmadrvPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + dmadrvPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trig on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) + dmadrvPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) + dmadrvPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) + dmadrvPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) + dmadrvPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) + dmadrvPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trig on USART4_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) + dmadrvPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT) + dmadrvPeripheralSignal_USART5_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) + dmadrvPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT) + dmadrvPeripheralSignal_USART5_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART5TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) + dmadrvPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trig on USART5_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) + dmadrvPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) + dmadrvPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) + dmadrvPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trig on UART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) + dmadrvPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) + dmadrvPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trig on UART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) + dmadrvPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1 ///< Trig on UART1_TXEMPTY. + #endif +}; +#endif + +/// Data size of one LDMA transfer item. +SL_ENUM(DMADRV_DataSize_t) { +#if defined(EMDRV_DMADRV_LDMA_S3) + dmadrvDataSize1 = SL_HAL_LDMA_CTRL_SIZE_BYTE, ///< Byte + dmadrvDataSize2 = SL_HAL_LDMA_CTRL_SIZE_HALF, ///< Halfword + dmadrvDataSize4 = SL_HAL_LDMA_CTRL_SIZE_WORD ///< Word +#else + dmadrvDataSize1 = ldmaCtrlSizeByte, ///< Byte + dmadrvDataSize2 = ldmaCtrlSizeHalf, ///< Halfword + dmadrvDataSize4 = ldmaCtrlSizeWord ///< Word +#endif +}; + +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ + +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, + void *capabilities); +Ecode_t DMADRV_DeInit(void); +Ecode_t DMADRV_FreeChannel(unsigned int channelId); +Ecode_t DMADRV_Init(void); + +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); +Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA) +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam); +#endif + +Ecode_t DMADRV_PauseTransfer(unsigned int channelId); +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId); +Ecode_t DMADRV_StopTransfer(unsigned int channelId); +Ecode_t DMADRV_TransferActive(unsigned int channelId, + bool *active); +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, + bool *pending); +Ecode_t DMADRV_TransferDone(unsigned int channelId, + bool *done); +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining); + +/** @} (end addtogroup dmadrv) */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SILICON_LABS_DMADRV_H__ */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c index b801b42..2b1ad03 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/dmadrv/src/dmadrv.c @@ -1,1664 +1,1664 @@ -/***************************************************************************//** - * @file - * @brief DMADRV API implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include - -#include "em_device.h" -#include "em_core.h" - -#include "dmadrv.h" - -#if defined(EMDRV_DMADRV_UDMA) -#include "em_cmu.h" -#include "dmactrl.h" -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ - || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) -#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT -#endif - -typedef enum { - dmaDirectionMemToPeripheral, - dmaDirectionPeripheralToMem -} DmaDirection_t; - -typedef enum { - dmaModeBasic, - dmaModePingPong -} DmaMode_t; - -typedef struct { - DMADRV_Callback_t callback; - void *userParam; - unsigned int callbackCount; -#if defined(EMDRV_DMADRV_UDMA) - int length; -#endif - bool allocated; -#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) - DmaMode_t mode; -#endif -} ChTable_t; - -static bool initialized = false; -static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; - -#if defined(EMDRV_DMADRV_UDMA) -static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; -#endif - -#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) -#if defined(EMDRV_DMADRV_LDMA) -const LDMA_TransferCfg_t xferCfgPeripheral = LDMA_TRANSFER_CFG_PERIPHERAL(0); -const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); -const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); - -typedef struct { - LDMA_Descriptor_t desc[2]; -} DmaXfer_t; -#else -const sl_hal_ldma_transfer_config_t xferCfgPeripheral = SL_HAL_LDMA_TRANSFER_CFG_PERIPHERAL(0); -const sl_hal_ldma_descriptor_t m2p = SL_HAL_LDMA_DESCRIPTOR_SINGLE_M2P(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); -const sl_hal_ldma_descriptor_t p2m = SL_HAL_LDMA_DESCRIPTOR_SINGLE_P2M(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); - -typedef struct { - sl_hal_ldma_descriptor_t desc[2]; -} DmaXfer_t; -#endif - -static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; -#endif - -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam); - -#if defined(EMDRV_DMADRV_LDMA_S3) -static void LDMA_IRQHandlerDefault(uint8_t chnum); -#endif - -/// @endcond - -/***************************************************************************//** - * @brief - * Allocate (reserve) a DMA channel. - * - * @param[out] channelId - * The channel ID assigned by DMADRV. - * - * @param[in] capabilities - * Not used. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) -{ - unsigned int i; - (void)capabilities; - CORE_DECLARE_IRQ_STATE; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId == NULL ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - CORE_ENTER_ATOMIC(); - for ( i = 0U; i < (unsigned int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - if ( !chTable[i].allocated ) { - *channelId = i; - chTable[i].allocated = true; - chTable[i].callback = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - } - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; -} - -/***************************************************************************//** - * @brief - * Deinitialize DMADRV. - * - * @details - * If DMA channels are not currently allocated, it will disable DMA hardware - * and mask associated interrupts. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_DeInit(void) -{ - int i; - bool inUse; - CORE_DECLARE_IRQ_STATE; - - inUse = false; - - CORE_ENTER_ATOMIC(); - for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - if ( chTable[i].allocated ) { - inUse = true; - break; - } - } - - if ( !inUse ) { -#if defined(EMDRV_DMADRV_UDMA) - NVIC_DisableIRQ(DMA_IRQn); - DMA->IEN = _DMA_IEN_RESETVALUE; - DMA->CONFIG = _DMA_CONFIG_RESETVALUE; - CMU_ClockEnable(cmuClock_DMA, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_DeInit(); -#elif defined(EMDRV_DMADRV_LDMA_S3) - NVIC_DisableIRQ(LDMA_CHNL0_IRQn); - NVIC_DisableIRQ(LDMA_CHNL1_IRQn); - NVIC_DisableIRQ(LDMA_CHNL2_IRQn); - NVIC_DisableIRQ(LDMA_CHNL3_IRQn); - NVIC_DisableIRQ(LDMA_CHNL4_IRQn); - NVIC_DisableIRQ(LDMA_CHNL5_IRQn); - NVIC_DisableIRQ(LDMA_CHNL6_IRQn); - NVIC_DisableIRQ(LDMA_CHNL7_IRQn); - - sl_hal_ldma_reset(); - - // TODO CM add call to the equivalent of CMU_ClockEnable() to disable cmuClock_LDMA. It will require to include the proper S3 CMU header file. -#endif - initialized = false; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_DMADRV_IN_USE; -} - -/***************************************************************************//** - * @brief - * Free an allocated (reserved) DMA channel. - * - * @param[in] channelId - * The channel ID to free. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_FreeChannel(unsigned int channelId) -{ - CORE_DECLARE_IRQ_STATE; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - CORE_ENTER_ATOMIC(); - if ( chTable[channelId].allocated ) { - chTable[channelId].allocated = false; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_OK; - } - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_DMADRV_ALREADY_FREED; -} - -/***************************************************************************//** - * @brief - * Initialize DMADRV. - * - * @details - * The DMA hardware is initialized. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_Init(void) -{ - int i; - CORE_DECLARE_IRQ_STATE; -#if defined(EMDRV_DMADRV_UDMA) - DMA_Init_TypeDef dmaInit; -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; - dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_config_t dmaInit = SL_HAL_LDMA_INIT_DEFAULT; - dmaInit.num_fixed_priority = EMDRV_DMADRV_DMA_CH_PRIORITY; -#endif - - CORE_ENTER_ATOMIC(); - if ( initialized ) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; - } - initialized = true; - CORE_EXIT_ATOMIC(); - - if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY >= (1 << __NVIC_PRIO_BITS) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { - chTable[i].allocated = false; - } - -#if defined(EMDRV_DMADRV_UDMA) - NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - dmaInit.hprot = 0; - dmaInit.controlBlock = dmaControlBlock; - DMA_Init(&dmaInit); -#elif defined(EMDRV_DMADRV_LDMA) - dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; - LDMA_Init(&dmaInit); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_init(&dmaInit); - - NVIC_ClearPendingIRQ(LDMA_CHNL0_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL1_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL2_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL3_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL4_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL5_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL6_IRQn); - NVIC_ClearPendingIRQ(LDMA_CHNL7_IRQn); - - NVIC_SetPriority(LDMA_CHNL0_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL1_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL2_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL3_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL4_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL5_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL6_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - NVIC_SetPriority(LDMA_CHNL7_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); - - NVIC_EnableIRQ(LDMA_CHNL0_IRQn); - NVIC_EnableIRQ(LDMA_CHNL1_IRQn); - NVIC_EnableIRQ(LDMA_CHNL2_IRQn); - NVIC_EnableIRQ(LDMA_CHNL3_IRQn); - NVIC_EnableIRQ(LDMA_CHNL4_IRQn); - NVIC_EnableIRQ(LDMA_CHNL5_IRQn); - NVIC_EnableIRQ(LDMA_CHNL6_IRQn); - NVIC_EnableIRQ(LDMA_CHNL7_IRQn); - - sl_hal_ldma_enable(); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -#if defined(EMDRV_DMADRV_LDMA) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - * - * @details - * This function is similar to the emlib LDMA function. - * - * @param[in] channelId - * The channel ID to use. - * - * @param[in] transfer - * A DMA transfer configuration data structure. - * - * @param[in] descriptor - * A DMA transfer descriptor, can be an array of descriptors linked together. - * - * @param[in] callback - * An optional callback function for signalling completion. May be NULL if not - * needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. May be NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_LdmaStartTransfer(int channelId, - LDMA_TransferCfg_t *transfer, - LDMA_Descriptor_t *descriptor, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - LDMA_StartTransfer(channelId, transfer, descriptor); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif - -/***************************************************************************//** - * @brief - * Start a memory to a peripheral DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination (peripheral register) memory address. - * - * @param[in] src - * A source memory address. - * - * @param[in] srcInc - * Set to true to enable source address increment (increments according to - * @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModeBasic, - dmaDirectionMemToPeripheral, - channelId, - peripheralSignal, - dst, - src, - NULL, - srcInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a memory to a peripheral ping-pong DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination (peripheral register) memory address. - * - * @param[in] src0 - * A source memory address of the first (ping) buffer. - * - * @param[in] src1 - * A source memory address of the second (pong) buffer. - * - * @param[in] srcInc - * Set to true to enable source address increment (increments according to - * @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_MemoryPeripheralPingPong( - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src0, - void *src1, - bool srcInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModePingPong, - dmaDirectionMemToPeripheral, - channelId, - peripheralSignal, - dst, - src0, - src1, - srcInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a peripheral to memory DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst - * A destination memory address. - * - * @param[in] src - * A source memory (peripheral register) address. - * - * @param[in] dstInc - * Set to true to enable destination address increment (increments according - * to @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModeBasic, - dmaDirectionPeripheralToMem, - channelId, - peripheralSignal, - dst, - src, - NULL, - dstInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Start a peripheral to memory ping-pong DMA transfer. - * - * @param[in] channelId - * The channel ID to use for the transfer. - * - * @param[in] peripheralSignal - * Selects which peripheral/peripheralsignal to use. - * - * @param[in] dst0 - * A destination memory address of the first (ping) buffer. - * - * @param[in] dst1 - * A destination memory address of the second (pong) buffer. - * - * @param[in] src - * A source memory (peripheral register) address. - * - * @param[in] dstInc - * Set to true to enable destination address increment (increments according - * to @a size parameter). - * - * @param[in] len - * A number of items (of @a size size) to transfer. - * - * @param[in] size - * An item size, byte, halfword or word. - * - * @param[in] callback - * A function to call on DMA completion, use NULL if not needed. - * - * @param[in] cbUserParam - * An optional user parameter to feed to the callback function. Use NULL if - * not needed. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PeripheralMemoryPingPong( - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *dst0, - void *dst1, - void *src, - bool dstInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - return StartTransfer(dmaModePingPong, - dmaDirectionPeripheralToMem, - channelId, - peripheralSignal, - dst0, - dst1, - src, - dstInc, - len, - size, - callback, - cbUserParam); -} - -/***************************************************************************//** - * @brief - * Pause an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to pause. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_PauseTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelRequestEnable(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_EnableChannelRequest(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_disable_channel_request(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Resume an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to resume. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelRequestEnable(channelId, true); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_EnableChannelRequest(channelId, true); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_enable_channel_request(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Stop an ongoing DMA transfer. - * - * @param[in] channelId - * The channel ID of the transfer to stop. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_StopTransfer(unsigned int channelId) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - DMA_ChannelEnable(channelId, false); -#elif defined(EMDRV_DMADRV_LDMA) - LDMA_StopTransfer(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - sl_hal_ldma_stop_transfer(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer is running. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] active - * True if transfer is running, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (active == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - if ( DMA_ChannelEnabled(channelId) ) -#elif defined(EMDRV_DMADRV_LDMA) - if ( LDMA_ChannelEnabled(channelId) ) -#elif defined(EMDRV_DMADRV_LDMA_S3) - if ( sl_hal_ldma_channel_is_enabled(channelId) ) -#endif - { - *active = true; - } else { - *active = false; - } - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer complete is pending. - * - * @details - * Will check the channel interrupt flag. This assumes that the DMA is configured - * to give a completion interrupt. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] pending - * True if a transfer complete is pending, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) -{ - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (pending == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - if ( DMA->IF & (1 << channelId) ) -#elif defined(EMDRV_DMADRV_LDMA) - if ( LDMA->IF & (1 << channelId) ) -#elif defined(EMDRV_DMADRV_LDMA_S3) - if ( sl_hal_ldma_get_interrupts() & (1 << channelId) ) -#endif - { - *pending = true; - } else { - *pending = false; - } - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Check if a transfer has completed. - * - * @note - * This function should be used in a polled environment. - * Will only work reliably for transfers NOT using the completion interrupt. - * On UDMA, it will only work on basic transfers on the primary channel. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] done - * True if a transfer has completed, false otherwise. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) -{ -#if defined(EMDRV_DMADRV_UDMA) - uint32_t remaining, iflag; -#endif - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (done == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - CORE_ATOMIC_SECTION( - /* This works for primary channel only ! */ - remaining = (dmaControlBlock[channelId].CTRL - & _DMA_CTRL_N_MINUS_1_MASK) - >> _DMA_CTRL_N_MINUS_1_SHIFT; - iflag = DMA->IF; - ) - - if ( (remaining == 0) && (iflag & (1 << channelId)) ) { - *done = true; - } else { - *done = false; - } -#elif defined(EMDRV_DMADRV_LDMA) - *done = LDMA_TransferDone(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - *done = sl_hal_ldma_transfer_is_done(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/***************************************************************************//** - * @brief - * Get number of items remaining in a transfer. - * - * @note - * This function does not take into account that a DMA transfer with - * a chain of linked transfers might be ongoing. It will only check the - * count for the current transfer. - * On UDMA, it will only work on the primary channel. - * - * @param[in] channelId - * The channel ID of the transfer to check. - * - * @param[out] remaining - * A number of items remaining in the transfer. - * - * @return - * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate - * DMADRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, - int *remaining) -{ -#if defined(EMDRV_DMADRV_UDMA) - uint32_t remain, iflag; -#endif - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (remaining == NULL) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - if ( chTable[channelId].allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - -#if defined(EMDRV_DMADRV_UDMA) - CORE_ATOMIC_SECTION( - /* This works for the primary channel only ! */ - remain = (dmaControlBlock[channelId].CTRL - & _DMA_CTRL_N_MINUS_1_MASK) - >> _DMA_CTRL_N_MINUS_1_SHIFT; - iflag = DMA->IF; - ) - - if ( (remain == 0) && (iflag & (1 << channelId)) ) { - *remaining = 0; - } else { - *remaining = 1 + remain; - } -#elif defined(EMDRV_DMADRV_LDMA) - *remaining = LDMA_TransferRemainingCount(channelId); -#elif defined(EMDRV_DMADRV_LDMA_S3) - *remaining = sl_hal_ldma_transfer_remaining_count(channelId); -#endif - - return ECODE_EMDRV_DMADRV_OK; -} - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(EMDRV_DMADRV_LDMA) -/***************************************************************************//** - * @brief - * An interrupt handler for LDMA. - ******************************************************************************/ -void LDMA_IRQHandler(void) -{ - bool stop; - ChTable_t *ch; - uint32_t pending, chnum, chmask; - - /* Get all pending and enabled interrupts. */ - pending = LDMA->IF; - pending &= LDMA->IEN; - - /* Check for LDMA error. */ - if ( pending & LDMA_IF_ERROR ) { - /* Loop to enable debugger to see what has happened. */ - while (true) { - /* Wait forever. */ - } - } - - /* Iterate over all LDMA channels. */ - for ( chnum = 0, chmask = 1; - chnum < EMDRV_DMADRV_DMA_CH_COUNT; - chnum++, chmask <<= 1 ) { - if ( pending & chmask ) { - /* Clear the interrupt flag. */ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chmask; -#else - LDMA->IFC = chmask; -#endif - - ch = &chTable[chnum]; - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); - - if ( (ch->mode == dmaModePingPong) && stop ) { - dmaXfer[chnum].desc[0].xfer.link = 0; - dmaXfer[chnum].desc[1].xfer.link = 0; - } - } - } - } -} -#endif /* defined( EMDRV_DMADRV_LDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA_S3) -/***************************************************************************//** - * @brief - * Default interrupt handler for LDMA common to all interrupt channel lines. - * - * @param[in] chnum - * The channel ID responsible for the interrupt signal trigger. - ******************************************************************************/ -static void LDMA_IRQHandlerDefault(uint8_t chnum) -{ - bool stop; - ChTable_t *ch; - uint32_t pending; - uint32_t chmask; - - /* Get all pending and enabled interrupts. */ - pending = sl_hal_ldma_get_enabled_interrupts(); - - /* Check for LDMA error. */ - if ( pending & (LDMA_IF_ERROR0 << chnum) ) { - /* Loop to enable debugger to see what has happened. */ - while (true) { - /* Wait forever. */ - } - } - - chmask = 1 << chnum; - if ( pending & chmask ) { - /* Clear the interrupt flag. */ - sl_hal_ldma_clear_interrupts(chmask); - - /* Callback called if it was provided for the given channel. */ - ch = &chTable[chnum]; - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); - - /* Continue or not a ping-pong transfer. */ - if ( (ch->mode == dmaModePingPong) && stop ) { - dmaXfer[chnum].desc[0].xfer.link = 0; - dmaXfer[chnum].desc[1].xfer.link = 0; - } - } - } -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 0. - ******************************************************************************/ -void LDMA_CHNL0_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(0); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 1. - ******************************************************************************/ -void LDMA_CHNL1_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(1); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 2. - ******************************************************************************/ -void LDMA_CHNL2_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(2); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 3. - ******************************************************************************/ -void LDMA_CHNL3_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(3); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 4. - ******************************************************************************/ -void LDMA_CHNL4_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(4); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 5. - ******************************************************************************/ -void LDMA_CHNL5_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(5); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 6. - ******************************************************************************/ -void LDMA_CHNL6_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(6); -} - -/***************************************************************************//** - * @brief - * Root interrupt handler for LDMA channel 7. - ******************************************************************************/ -void LDMA_CHNL7_IRQHandler(void) -{ - LDMA_IRQHandlerDefault(7); -} - -#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * A callback function for UDMA basic transfers. - ******************************************************************************/ -static void DmaBasicCallback(unsigned int channel, bool primary, void *user) -{ - ChTable_t *ch = &chTable[channel]; - (void)user; - (void)primary; - - if ( ch->callback != NULL ) { - ch->callbackCount++; - ch->callback(channel, ch->callbackCount, ch->userParam); - } -} -#endif - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * A callback function for UDMA ping-pong transfers. - ******************************************************************************/ -static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) -{ - bool stop = true; - ChTable_t *ch = &chTable[channel]; - - (void)user; - - if ( ch->callback != NULL ) { - ch->callbackCount++; - stop = !ch->callback(channel, ch->callbackCount, ch->userParam); - } - - DMA_RefreshPingPong(channel, - primary, - false, - NULL, - NULL, - ch->length - 1, - stop); -} -#endif - -#if defined(EMDRV_DMADRV_UDMA) -/***************************************************************************//** - * @brief - * Start a UDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - DMA_CfgChannel_TypeDef chCfg; - DMA_CfgDescr_TypeDef descrCfg; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - /* Se tup the interrupt callback routine. */ - if ( mode == dmaModeBasic ) { - dmaCallBack[channelId].cbFunc = DmaBasicCallback; - } else { - dmaCallBack[channelId].cbFunc = DmaPingPongCallback; - } - dmaCallBack[channelId].userPtr = NULL; - - /* Set up the channel */ - chCfg.highPri = false; /* Can't use hi pri with peripherals. */ - - /* Whether the interrupt is needed. */ - if ( (callback != NULL) || (mode == dmaModePingPong) ) { - chCfg.enableInt = true; - } else { - chCfg.enableInt = false; - } - chCfg.select = peripheralSignal; - chCfg.cb = &dmaCallBack[channelId]; - DMA_CfgChannel(channelId, &chCfg); - - /* Set up the channel descriptor. */ - if ( direction == dmaDirectionMemToPeripheral ) { - if ( bufInc ) { - if ( size == dmadrvDataSize1 ) { - descrCfg.srcInc = dmaDataInc1; - } else if ( size == dmadrvDataSize2 ) { - descrCfg.srcInc = dmaDataInc2; - } else { /* dmadrvDataSize4 */ - descrCfg.srcInc = dmaDataInc4; - } - } else { - descrCfg.srcInc = dmaDataIncNone; - } - descrCfg.dstInc = dmaDataIncNone; - } else { - if ( bufInc ) { - if ( size == dmadrvDataSize1 ) { - descrCfg.dstInc = dmaDataInc1; - } else if ( size == dmadrvDataSize2 ) { - descrCfg.dstInc = dmaDataInc2; - } else { /* dmadrvDataSize4 */ - descrCfg.dstInc = dmaDataInc4; - } - } else { - descrCfg.dstInc = dmaDataIncNone; - } - descrCfg.srcInc = dmaDataIncNone; - } - descrCfg.size = (DMA_DataSize_TypeDef)size; - descrCfg.arbRate = dmaArbitrate1; - descrCfg.hprot = 0; - DMA_CfgDescr(channelId, true, &descrCfg); - if ( mode == dmaModePingPong ) { - DMA_CfgDescr(channelId, false, &descrCfg); - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->length = len; - - DMA->IFC = 1 << channelId; - - /* Start the DMA cycle. */ - if ( mode == dmaModeBasic ) { - DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); - } else { - if ( direction == dmaDirectionMemToPeripheral ) { - DMA_ActivatePingPong(channelId, - false, - buf0, /* dest */ - buf1, /* src */ - len - 1, - buf0, /* dest */ - buf2, /* src */ - len - 1); - } else { - DMA_ActivatePingPong(channelId, - false, - buf0, /* dest */ - buf2, /* src */ - len - 1, - buf1, /* dest */ - buf2, /* src */ - len - 1); - } - } - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_UDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - LDMA_TransferCfg_t xfer; - LDMA_Descriptor_t *desc; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - xfer = xferCfgPeripheral; - desc = &dmaXfer[channelId].desc[0]; - - if ( direction == dmaDirectionMemToPeripheral ) { - *desc = m2p; - if ( !bufInc ) { - desc->xfer.srcInc = ldmaCtrlSrcIncNone; - } - } else { - *desc = p2m; - if ( !bufInc ) { - desc->xfer.dstInc = ldmaCtrlDstIncNone; - } - } - - xfer.ldmaReqSel = peripheralSignal; - desc->xfer.xferCnt = len - 1; - desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; - desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; - desc->xfer.size = size; - - if ( mode == dmaModePingPong ) { - desc->xfer.linkMode = ldmaLinkModeRel; - desc->xfer.link = 1; - desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ - - /* Set the "pong" descriptor equal to the "ping" descriptor. */ - dmaXfer[channelId].desc[1] = *desc; - /* Refer to the "ping" descriptor. */ - dmaXfer[channelId].desc[1].xfer.linkAddr = -4; - dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; - - if ( direction == dmaDirectionPeripheralToMem ) { - dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; - desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; - } - } - - /* Whether an interrupt is needed. */ - if ( (callback == NULL) && (mode == dmaModeBasic) ) { - desc->xfer.doneIfs = 0; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->mode = mode; - - LDMA_StartTransfer(channelId, &xfer, desc); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_LDMA ) */ - -#if defined(EMDRV_DMADRV_LDMA_S3) -/***************************************************************************//** - * @brief - * Start an LDMA transfer. - ******************************************************************************/ -static Ecode_t StartTransfer(DmaMode_t mode, - DmaDirection_t direction, - unsigned int channelId, - DMADRV_PeripheralSignal_t - peripheralSignal, - void *buf0, - void *buf1, - void *buf2, - bool bufInc, - int len, - DMADRV_DataSize_t size, - DMADRV_Callback_t callback, - void *cbUserParam) -{ - ChTable_t *ch; - sl_hal_ldma_transfer_config_t xfer; - sl_hal_ldma_descriptor_t *desc; - - if ( !initialized ) { - return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; - } - - if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) - || (buf0 == NULL) - || (buf1 == NULL) - || (len > DMADRV_MAX_XFER_COUNT) - || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { - return ECODE_EMDRV_DMADRV_PARAM_ERROR; - } - - ch = &chTable[channelId]; - if ( ch->allocated == false ) { - return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; - } - - xfer = xferCfgPeripheral; - desc = &dmaXfer[channelId].desc[0]; - - if ( direction == dmaDirectionMemToPeripheral ) { - *desc = m2p; - if ( !bufInc ) { - desc->xfer.src_inc = SL_HAL_LDMA_CTRL_SRC_INC_NONE; - } - } else { - *desc = p2m; - if ( !bufInc ) { - desc->xfer.dst_inc = SL_HAL_LDMA_CTRL_DST_INC_NONE; - } - } - - xfer.request_sel = peripheralSignal; - desc->xfer.xfer_count = len - 1; - desc->xfer.dst_addr = (uint32_t)(uint8_t *)buf0; - desc->xfer.src_addr = (uint32_t)(uint8_t *)buf1; - desc->xfer.size = size; - - if ( mode == dmaModePingPong ) { - desc->xfer.link_mode = SL_HAL_LDMA_LINK_MODE_REL; - desc->xfer.link = 1; - desc->xfer.link_addr = 4; /* Refer to the "pong" descriptor. */ - - /* Set the "pong" descriptor equal to the "ping" descriptor. */ - dmaXfer[channelId].desc[1] = *desc; - /* Refer to the "ping" descriptor. */ - dmaXfer[channelId].desc[1].xfer.link_addr = -4; - dmaXfer[channelId].desc[1].xfer.src_addr = (uint32_t)(uint8_t *)buf2; - - if ( direction == dmaDirectionPeripheralToMem ) { - dmaXfer[channelId].desc[1].xfer.dst_addr = (uint32_t)(uint8_t *)buf1; - desc->xfer.src_addr = (uint32_t)(uint8_t *)buf2; - } - } - - /* Whether an interrupt is needed. */ - if ( (callback == NULL) && (mode == dmaModeBasic) ) { - desc->xfer.done_ifs = 0; - } - - ch->callback = callback; - ch->userParam = cbUserParam; - ch->callbackCount = 0; - ch->mode = mode; - - sl_hal_ldma_init_transfer(channelId, &xfer, desc); - sl_hal_ldma_start_transfer(channelId); - sl_hal_ldma_enable_interrupts((0x1UL << channelId)); - - return ECODE_EMDRV_DMADRV_OK; -} -#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ - -/// @endcond - -// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** -/// @addtogroup dmadrv DMADRV - DMA Driver -/// @brief Direct Memory Access Driver -/// @{ -/// -/// @details -/// -/// -/// @n @section dmadrv_intro Introduction -/// -/// The DMADRV driver supports writing code using DMA which will work -/// regardless of the type of the DMA controller on the underlying microcontroller. -/// Additionally, DMA can be used in several modules that are -/// completely unaware of each other. -/// The driver does not preclude use of the native emlib API of the underlying -/// DMA controller. On the contrary, it will often result in more efficient -/// code and is necessary for complex DMA operations. The housekeeping -/// functions of this driver are valuable even in this use-case. -/// -/// The dmadrv.c and dmadrv.h source files are in the -/// emdrv/dmadrv folder. -/// -/// @note DMA transfer completion callback functions are called from within the -/// DMA interrupt handler. -/// -/// @n @section dmadrv_conf Configuration Options -/// -/// Some properties of the DMADRV driver are compile-time configurable. These -/// properties are stored in a file named dmadrv_config.h. A template for this -/// file, containing default values, is in the emdrv/config folder. -/// Currently the configuration options are as follows: -/// @li The interrupt priority of the DMA peripheral. -/// @li A number of DMA channels to support. -/// @li Use the native emlib API belonging to the underlying DMA hardware in -/// combination with the DMADRV API. -/// -/// Both configuration options will help reduce the driver's RAM footprint. -/// -/// To configure DMADRV, provide a custom configuration file. This is an -/// example dmadrv_config.h file: -/// @code{.c} -/// #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ -/// #define __SILICON_LABS_DMADRV_CONFIG_H__ -/// -/// // DMADRV DMA interrupt priority configuration option. -/// // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. -/// #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 -/// -/// // DMADRV channel count configuration option. -/// // A number of DMA channels to support. A lower DMA channel count will reduce -/// // RAM footprint. -/// #define EMDRV_DMADRV_DMA_CH_COUNT 4 -/// -/// #endif -/// @endcode -/// -/// @n @section dmadrv_api The API -/// -/// This section contains brief descriptions of the API functions. -/// For more information about input and output parameters and return values, -/// click on the hyperlinked function names. Most functions return an error -/// code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, -/// see @ref ecode and @ref dmadrv_error_codes for other error codes. -/// -/// The application code must include @em dmadrv.h header file. -/// -/// @ref DMADRV_Init(), @ref DMADRV_DeInit() @n -/// These functions initialize or deinitialize the DMADRV driver. Typically, -/// DMADRV_Init() is called once in the startup code. -/// -/// @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n -/// DMA channel reserve and release functions. It is recommended that -/// application code check that DMADRV_AllocateChannel() -/// returns ECODE_EMDRV_DMADRV_OK before starting a DMA -/// transfer. -/// -/// @ref DMADRV_MemoryPeripheral() @n -/// Start a DMA transfer from memory to a peripheral. -/// -/// @ref DMADRV_PeripheralMemory() @n -/// Start a DMA transfer from a peripheral to memory. -/// -/// @ref DMADRV_MemoryPeripheralPingPong() @n -/// Start a DMA ping-pong transfer from memory to a peripheral. -/// -/// @ref DMADRV_PeripheralMemoryPingPong() @n -/// Start a DMA ping-pong transfer from a peripheral to memory. -/// -/// @ref DMADRV_LdmaStartTransfer() @n -/// Start a DMA transfer on an LDMA controller. -/// -/// @ref DMADRV_StopTransfer() @n -/// Stop an ongoing DMA transfer. -/// -/// @ref DMADRV_TransferActive() @n -/// Check if a transfer is ongoing. -/// -/// @ref DMADRV_TransferCompletePending() @n -/// Check if a transfer completion is pending. -/// -/// @ref DMADRV_TransferDone() @n -/// Check if a transfer has completed. -/// -/// @ref DMADRV_TransferRemainingCount() @n -/// Get number of items remaining in a transfer. -/// -/// @n @section dmadrv_example Example -/// Transfer a text string to USART1. -/// @code{.c} -/// #include "dmadrv.h" -/// -/// char str[] = "Hello DMA !"; -/// unsigned int channel; -/// -/// int main( void ) -/// { -/// // Initialize DMA. -/// DMADRV_Init(); -/// -/// // Request a DMA channel. -/// DMADRV_AllocateChannel( &channel, NULL ); -/// -/// // Start the DMA transfer. -/// DMADRV_MemoryPeripheral( channel, -/// dmadrvPeripheralSignal_USART1_TXBL, -/// (void*)&(USART1->TXDATA), -/// str, -/// true, -/// sizeof( str ), -/// dmadrvDataSize1, -/// NULL, -/// NULL ); -/// -/// return 0; -/// } -/// @endcode -/// -/// @} end group dmadrv ******************************************************** +/***************************************************************************//** + * @file + * @brief DMADRV API implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include + +#include "em_device.h" +#include "em_core.h" + +#include "dmadrv.h" + +#if defined(EMDRV_DMADRV_UDMA) +#include "em_cmu.h" +#include "dmactrl.h" +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if !defined(EMDRV_DMADRV_DMA_CH_COUNT) \ + || (EMDRV_DMADRV_DMA_CH_COUNT > DMA_CHAN_COUNT) +#define EMDRV_DMADRV_DMA_CH_COUNT DMA_CHAN_COUNT +#endif + +typedef enum { + dmaDirectionMemToPeripheral, + dmaDirectionPeripheralToMem +} DmaDirection_t; + +typedef enum { + dmaModeBasic, + dmaModePingPong +} DmaMode_t; + +typedef struct { + DMADRV_Callback_t callback; + void *userParam; + unsigned int callbackCount; +#if defined(EMDRV_DMADRV_UDMA) + int length; +#endif + bool allocated; +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) + DmaMode_t mode; +#endif +} ChTable_t; + +static bool initialized = false; +static ChTable_t chTable[EMDRV_DMADRV_DMA_CH_COUNT]; + +#if defined(EMDRV_DMADRV_UDMA) +static DMA_CB_TypeDef dmaCallBack[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +#if defined(EMDRV_DMADRV_LDMA) || defined(EMDRV_DMADRV_LDMA_S3) +#if defined(EMDRV_DMADRV_LDMA) +const LDMA_TransferCfg_t xferCfgPeripheral = LDMA_TRANSFER_CFG_PERIPHERAL(0); +const LDMA_Descriptor_t m2p = LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(NULL, NULL, 1UL); +const LDMA_Descriptor_t p2m = LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(NULL, NULL, 1UL); + +typedef struct { + LDMA_Descriptor_t desc[2]; +} DmaXfer_t; +#else +const sl_hal_ldma_transfer_config_t xferCfgPeripheral = SL_HAL_LDMA_TRANSFER_CFG_PERIPHERAL(0); +const sl_hal_ldma_descriptor_t m2p = SL_HAL_LDMA_DESCRIPTOR_SINGLE_M2P(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); +const sl_hal_ldma_descriptor_t p2m = SL_HAL_LDMA_DESCRIPTOR_SINGLE_P2M(SL_HAL_LDMA_CTRL_SIZE_BYTE, NULL, NULL, 1UL); + +typedef struct { + sl_hal_ldma_descriptor_t desc[2]; +} DmaXfer_t; +#endif + +static DmaXfer_t dmaXfer[EMDRV_DMADRV_DMA_CH_COUNT]; +#endif + +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam); + +#if defined(EMDRV_DMADRV_LDMA_S3) +static void LDMA_IRQHandlerDefault(uint8_t chnum); +#endif + +/// @endcond + +/***************************************************************************//** + * @brief + * Allocate (reserve) a DMA channel. + * + * @param[out] channelId + * The channel ID assigned by DMADRV. + * + * @param[in] capabilities + * Not used. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities) +{ + unsigned int i; + (void)capabilities; + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId == NULL ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + for ( i = 0U; i < (unsigned int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( !chTable[i].allocated ) { + *channelId = i; + chTable[i].allocated = true; + chTable[i].callback = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + } + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED; +} + +/***************************************************************************//** + * @brief + * Deinitialize DMADRV. + * + * @details + * If DMA channels are not currently allocated, it will disable DMA hardware + * and mask associated interrupts. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_DeInit(void) +{ + int i; + bool inUse; + CORE_DECLARE_IRQ_STATE; + + inUse = false; + + CORE_ENTER_ATOMIC(); + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + if ( chTable[i].allocated ) { + inUse = true; + break; + } + } + + if ( !inUse ) { +#if defined(EMDRV_DMADRV_UDMA) + NVIC_DisableIRQ(DMA_IRQn); + DMA->IEN = _DMA_IEN_RESETVALUE; + DMA->CONFIG = _DMA_CONFIG_RESETVALUE; + CMU_ClockEnable(cmuClock_DMA, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_DeInit(); +#elif defined(EMDRV_DMADRV_LDMA_S3) + NVIC_DisableIRQ(LDMA_CHNL0_IRQn); + NVIC_DisableIRQ(LDMA_CHNL1_IRQn); + NVIC_DisableIRQ(LDMA_CHNL2_IRQn); + NVIC_DisableIRQ(LDMA_CHNL3_IRQn); + NVIC_DisableIRQ(LDMA_CHNL4_IRQn); + NVIC_DisableIRQ(LDMA_CHNL5_IRQn); + NVIC_DisableIRQ(LDMA_CHNL6_IRQn); + NVIC_DisableIRQ(LDMA_CHNL7_IRQn); + + sl_hal_ldma_reset(); + + // TODO CM add call to the equivalent of CMU_ClockEnable() to disable cmuClock_LDMA. It will require to include the proper S3 CMU header file. +#endif + initialized = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_IN_USE; +} + +/***************************************************************************//** + * @brief + * Free an allocated (reserved) DMA channel. + * + * @param[in] channelId + * The channel ID to free. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_FreeChannel(unsigned int channelId) +{ + CORE_DECLARE_IRQ_STATE; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + CORE_ENTER_ATOMIC(); + if ( chTable[channelId].allocated ) { + chTable[channelId].allocated = false; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_OK; + } + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_DMADRV_ALREADY_FREED; +} + +/***************************************************************************//** + * @brief + * Initialize DMADRV. + * + * @details + * The DMA hardware is initialized. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_Init(void) +{ + int i; + CORE_DECLARE_IRQ_STATE; +#if defined(EMDRV_DMADRV_UDMA) + DMA_Init_TypeDef dmaInit; +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_Init_t dmaInit = LDMA_INIT_DEFAULT; + dmaInit.ldmaInitCtrlNumFixed = EMDRV_DMADRV_DMA_CH_PRIORITY; +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_config_t dmaInit = SL_HAL_LDMA_INIT_DEFAULT; + dmaInit.num_fixed_priority = EMDRV_DMADRV_DMA_CH_PRIORITY; +#endif + + CORE_ENTER_ATOMIC(); + if ( initialized ) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED; + } + initialized = true; + CORE_EXIT_ATOMIC(); + + if ( EMDRV_DMADRV_DMA_IRQ_PRIORITY >= (1 << __NVIC_PRIO_BITS) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + for ( i = 0; i < (int)EMDRV_DMADRV_DMA_CH_COUNT; i++ ) { + chTable[i].allocated = false; + } + +#if defined(EMDRV_DMADRV_UDMA) + NVIC_SetPriority(DMA_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + dmaInit.hprot = 0; + dmaInit.controlBlock = dmaControlBlock; + DMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA) + dmaInit.ldmaInitIrqPriority = EMDRV_DMADRV_DMA_IRQ_PRIORITY; + LDMA_Init(&dmaInit); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_init(&dmaInit); + + NVIC_ClearPendingIRQ(LDMA_CHNL0_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL1_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL2_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL3_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL4_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL5_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL6_IRQn); + NVIC_ClearPendingIRQ(LDMA_CHNL7_IRQn); + + NVIC_SetPriority(LDMA_CHNL0_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL1_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL2_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL3_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL4_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL5_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL6_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + NVIC_SetPriority(LDMA_CHNL7_IRQn, EMDRV_DMADRV_DMA_IRQ_PRIORITY); + + NVIC_EnableIRQ(LDMA_CHNL0_IRQn); + NVIC_EnableIRQ(LDMA_CHNL1_IRQn); + NVIC_EnableIRQ(LDMA_CHNL2_IRQn); + NVIC_EnableIRQ(LDMA_CHNL3_IRQn); + NVIC_EnableIRQ(LDMA_CHNL4_IRQn); + NVIC_EnableIRQ(LDMA_CHNL5_IRQn); + NVIC_EnableIRQ(LDMA_CHNL6_IRQn); + NVIC_EnableIRQ(LDMA_CHNL7_IRQn); + + sl_hal_ldma_enable(); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +#if defined(EMDRV_DMADRV_LDMA) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + * + * @details + * This function is similar to the emlib LDMA function. + * + * @param[in] channelId + * The channel ID to use. + * + * @param[in] transfer + * A DMA transfer configuration data structure. + * + * @param[in] descriptor + * A DMA transfer descriptor, can be an array of descriptors linked together. + * + * @param[in] callback + * An optional callback function for signalling completion. May be NULL if not + * needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. May be NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_LdmaStartTransfer(int channelId, + LDMA_TransferCfg_t *transfer, + LDMA_Descriptor_t *descriptor, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= (int)EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + LDMA_StartTransfer(channelId, transfer, descriptor); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src + * A source memory address. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src, + NULL, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a memory to a peripheral ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination (peripheral register) memory address. + * + * @param[in] src0 + * A source memory address of the first (ping) buffer. + * + * @param[in] src1 + * A source memory address of the second (pong) buffer. + * + * @param[in] srcInc + * Set to true to enable source address increment (increments according to + * @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_MemoryPeripheralPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src0, + void *src1, + bool srcInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionMemToPeripheral, + channelId, + peripheralSignal, + dst, + src0, + src1, + srcInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst + * A destination memory address. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModeBasic, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst, + src, + NULL, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Start a peripheral to memory ping-pong DMA transfer. + * + * @param[in] channelId + * The channel ID to use for the transfer. + * + * @param[in] peripheralSignal + * Selects which peripheral/peripheralsignal to use. + * + * @param[in] dst0 + * A destination memory address of the first (ping) buffer. + * + * @param[in] dst1 + * A destination memory address of the second (pong) buffer. + * + * @param[in] src + * A source memory (peripheral register) address. + * + * @param[in] dstInc + * Set to true to enable destination address increment (increments according + * to @a size parameter). + * + * @param[in] len + * A number of items (of @a size size) to transfer. + * + * @param[in] size + * An item size, byte, halfword or word. + * + * @param[in] callback + * A function to call on DMA completion, use NULL if not needed. + * + * @param[in] cbUserParam + * An optional user parameter to feed to the callback function. Use NULL if + * not needed. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PeripheralMemoryPingPong( + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *dst0, + void *dst1, + void *src, + bool dstInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + return StartTransfer(dmaModePingPong, + dmaDirectionPeripheralToMem, + channelId, + peripheralSignal, + dst0, + dst1, + src, + dstInc, + len, + size, + callback, + cbUserParam); +} + +/***************************************************************************//** + * @brief + * Pause an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to pause. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_PauseTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_disable_channel_request(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Resume an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to resume. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_ResumeTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelRequestEnable(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_EnableChannelRequest(channelId, true); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_enable_channel_request(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Stop an ongoing DMA transfer. + * + * @param[in] channelId + * The channel ID of the transfer to stop. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_StopTransfer(unsigned int channelId) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( channelId >= EMDRV_DMADRV_DMA_CH_COUNT ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + DMA_ChannelEnable(channelId, false); +#elif defined(EMDRV_DMADRV_LDMA) + LDMA_StopTransfer(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + sl_hal_ldma_stop_transfer(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer is running. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] active + * True if transfer is running, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (active == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA_ChannelEnabled(channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_channel_is_enabled(channelId) ) +#endif + { + *active = true; + } else { + *active = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer complete is pending. + * + * @details + * Will check the channel interrupt flag. This assumes that the DMA is configured + * to give a completion interrupt. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] pending + * True if a transfer complete is pending, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending) +{ + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (pending == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + if ( DMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA) + if ( LDMA->IF & (1 << channelId) ) +#elif defined(EMDRV_DMADRV_LDMA_S3) + if ( sl_hal_ldma_get_interrupts() & (1 << channelId) ) +#endif + { + *pending = true; + } else { + *pending = false; + } + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Check if a transfer has completed. + * + * @note + * This function should be used in a polled environment. + * Will only work reliably for transfers NOT using the completion interrupt. + * On UDMA, it will only work on basic transfers on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] done + * True if a transfer has completed, false otherwise. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remaining, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (done == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for primary channel only ! */ + remaining = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remaining == 0) && (iflag & (1 << channelId)) ) { + *done = true; + } else { + *done = false; + } +#elif defined(EMDRV_DMADRV_LDMA) + *done = LDMA_TransferDone(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *done = sl_hal_ldma_transfer_is_done(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/***************************************************************************//** + * @brief + * Get number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * On UDMA, it will only work on the primary channel. + * + * @param[in] channelId + * The channel ID of the transfer to check. + * + * @param[out] remaining + * A number of items remaining in the transfer. + * + * @return + * @ref ECODE_EMDRV_DMADRV_OK on success. On failure, an appropriate + * DMADRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, + int *remaining) +{ +#if defined(EMDRV_DMADRV_UDMA) + uint32_t remain, iflag; +#endif + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (remaining == NULL) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + if ( chTable[channelId].allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + +#if defined(EMDRV_DMADRV_UDMA) + CORE_ATOMIC_SECTION( + /* This works for the primary channel only ! */ + remain = (dmaControlBlock[channelId].CTRL + & _DMA_CTRL_N_MINUS_1_MASK) + >> _DMA_CTRL_N_MINUS_1_SHIFT; + iflag = DMA->IF; + ) + + if ( (remain == 0) && (iflag & (1 << channelId)) ) { + *remaining = 0; + } else { + *remaining = 1 + remain; + } +#elif defined(EMDRV_DMADRV_LDMA) + *remaining = LDMA_TransferRemainingCount(channelId); +#elif defined(EMDRV_DMADRV_LDMA_S3) + *remaining = sl_hal_ldma_transfer_remaining_count(channelId); +#endif + + return ECODE_EMDRV_DMADRV_OK; +} + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * An interrupt handler for LDMA. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + bool stop; + ChTable_t *ch; + uint32_t pending, chnum, chmask; + + /* Get all pending and enabled interrupts. */ + pending = LDMA->IF; + pending &= LDMA->IEN; + + /* Check for LDMA error. */ + if ( pending & LDMA_IF_ERROR ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + /* Iterate over all LDMA channels. */ + for ( chnum = 0, chmask = 1; + chnum < EMDRV_DMADRV_DMA_CH_COUNT; + chnum++, chmask <<= 1 ) { + if ( pending & chmask ) { + /* Clear the interrupt flag. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chmask; +#else + LDMA->IFC = chmask; +#endif + + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } + } +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Default interrupt handler for LDMA common to all interrupt channel lines. + * + * @param[in] chnum + * The channel ID responsible for the interrupt signal trigger. + ******************************************************************************/ +static void LDMA_IRQHandlerDefault(uint8_t chnum) +{ + bool stop; + ChTable_t *ch; + uint32_t pending; + uint32_t chmask; + + /* Get all pending and enabled interrupts. */ + pending = sl_hal_ldma_get_enabled_interrupts(); + + /* Check for LDMA error. */ + if ( pending & (LDMA_IF_ERROR0 << chnum) ) { + /* Loop to enable debugger to see what has happened. */ + while (true) { + /* Wait forever. */ + } + } + + chmask = 1 << chnum; + if ( pending & chmask ) { + /* Clear the interrupt flag. */ + sl_hal_ldma_clear_interrupts(chmask); + + /* Callback called if it was provided for the given channel. */ + ch = &chTable[chnum]; + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(chnum, ch->callbackCount, ch->userParam); + + /* Continue or not a ping-pong transfer. */ + if ( (ch->mode == dmaModePingPong) && stop ) { + dmaXfer[chnum].desc[0].xfer.link = 0; + dmaXfer[chnum].desc[1].xfer.link = 0; + } + } + } +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 0. + ******************************************************************************/ +void LDMA_CHNL0_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(0); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 1. + ******************************************************************************/ +void LDMA_CHNL1_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(1); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 2. + ******************************************************************************/ +void LDMA_CHNL2_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(2); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 3. + ******************************************************************************/ +void LDMA_CHNL3_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(3); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 4. + ******************************************************************************/ +void LDMA_CHNL4_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(4); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 5. + ******************************************************************************/ +void LDMA_CHNL5_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(5); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 6. + ******************************************************************************/ +void LDMA_CHNL6_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(6); +} + +/***************************************************************************//** + * @brief + * Root interrupt handler for LDMA channel 7. + ******************************************************************************/ +void LDMA_CHNL7_IRQHandler(void) +{ + LDMA_IRQHandlerDefault(7); +} + +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA basic transfers. + ******************************************************************************/ +static void DmaBasicCallback(unsigned int channel, bool primary, void *user) +{ + ChTable_t *ch = &chTable[channel]; + (void)user; + (void)primary; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + ch->callback(channel, ch->callbackCount, ch->userParam); + } +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * A callback function for UDMA ping-pong transfers. + ******************************************************************************/ +static void DmaPingPongCallback(unsigned int channel, bool primary, void *user) +{ + bool stop = true; + ChTable_t *ch = &chTable[channel]; + + (void)user; + + if ( ch->callback != NULL ) { + ch->callbackCount++; + stop = !ch->callback(channel, ch->callbackCount, ch->userParam); + } + + DMA_RefreshPingPong(channel, + primary, + false, + NULL, + NULL, + ch->length - 1, + stop); +} +#endif + +#if defined(EMDRV_DMADRV_UDMA) +/***************************************************************************//** + * @brief + * Start a UDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + DMA_CfgChannel_TypeDef chCfg; + DMA_CfgDescr_TypeDef descrCfg; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + /* Se tup the interrupt callback routine. */ + if ( mode == dmaModeBasic ) { + dmaCallBack[channelId].cbFunc = DmaBasicCallback; + } else { + dmaCallBack[channelId].cbFunc = DmaPingPongCallback; + } + dmaCallBack[channelId].userPtr = NULL; + + /* Set up the channel */ + chCfg.highPri = false; /* Can't use hi pri with peripherals. */ + + /* Whether the interrupt is needed. */ + if ( (callback != NULL) || (mode == dmaModePingPong) ) { + chCfg.enableInt = true; + } else { + chCfg.enableInt = false; + } + chCfg.select = peripheralSignal; + chCfg.cb = &dmaCallBack[channelId]; + DMA_CfgChannel(channelId, &chCfg); + + /* Set up the channel descriptor. */ + if ( direction == dmaDirectionMemToPeripheral ) { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.srcInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.srcInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.srcInc = dmaDataInc4; + } + } else { + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.dstInc = dmaDataIncNone; + } else { + if ( bufInc ) { + if ( size == dmadrvDataSize1 ) { + descrCfg.dstInc = dmaDataInc1; + } else if ( size == dmadrvDataSize2 ) { + descrCfg.dstInc = dmaDataInc2; + } else { /* dmadrvDataSize4 */ + descrCfg.dstInc = dmaDataInc4; + } + } else { + descrCfg.dstInc = dmaDataIncNone; + } + descrCfg.srcInc = dmaDataIncNone; + } + descrCfg.size = (DMA_DataSize_TypeDef)size; + descrCfg.arbRate = dmaArbitrate1; + descrCfg.hprot = 0; + DMA_CfgDescr(channelId, true, &descrCfg); + if ( mode == dmaModePingPong ) { + DMA_CfgDescr(channelId, false, &descrCfg); + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->length = len; + + DMA->IFC = 1 << channelId; + + /* Start the DMA cycle. */ + if ( mode == dmaModeBasic ) { + DMA_ActivateBasic(channelId, true, false, buf0, buf1, len - 1); + } else { + if ( direction == dmaDirectionMemToPeripheral ) { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf1, /* src */ + len - 1, + buf0, /* dest */ + buf2, /* src */ + len - 1); + } else { + DMA_ActivatePingPong(channelId, + false, + buf0, /* dest */ + buf2, /* src */ + len - 1, + buf1, /* dest */ + buf2, /* src */ + len - 1); + } + } + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_UDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + LDMA_TransferCfg_t xfer; + LDMA_Descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.srcInc = ldmaCtrlSrcIncNone; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dstInc = ldmaCtrlDstIncNone; + } + } + + xfer.ldmaReqSel = peripheralSignal; + desc->xfer.xferCnt = len - 1; + desc->xfer.dstAddr = (uint32_t)(uint8_t *)buf0; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.linkMode = ldmaLinkModeRel; + desc->xfer.link = 1; + desc->xfer.linkAddr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.linkAddr = -4; + dmaXfer[channelId].desc[1].xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dstAddr = (uint32_t)(uint8_t *)buf1; + desc->xfer.srcAddr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.doneIfs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + LDMA_StartTransfer(channelId, &xfer, desc); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA ) */ + +#if defined(EMDRV_DMADRV_LDMA_S3) +/***************************************************************************//** + * @brief + * Start an LDMA transfer. + ******************************************************************************/ +static Ecode_t StartTransfer(DmaMode_t mode, + DmaDirection_t direction, + unsigned int channelId, + DMADRV_PeripheralSignal_t + peripheralSignal, + void *buf0, + void *buf1, + void *buf2, + bool bufInc, + int len, + DMADRV_DataSize_t size, + DMADRV_Callback_t callback, + void *cbUserParam) +{ + ChTable_t *ch; + sl_hal_ldma_transfer_config_t xfer; + sl_hal_ldma_descriptor_t *desc; + + if ( !initialized ) { + return ECODE_EMDRV_DMADRV_NOT_INITIALIZED; + } + + if ( (channelId >= EMDRV_DMADRV_DMA_CH_COUNT) + || (buf0 == NULL) + || (buf1 == NULL) + || (len > DMADRV_MAX_XFER_COUNT) + || ((mode == dmaModePingPong) && (buf2 == NULL)) ) { + return ECODE_EMDRV_DMADRV_PARAM_ERROR; + } + + ch = &chTable[channelId]; + if ( ch->allocated == false ) { + return ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED; + } + + xfer = xferCfgPeripheral; + desc = &dmaXfer[channelId].desc[0]; + + if ( direction == dmaDirectionMemToPeripheral ) { + *desc = m2p; + if ( !bufInc ) { + desc->xfer.src_inc = SL_HAL_LDMA_CTRL_SRC_INC_NONE; + } + } else { + *desc = p2m; + if ( !bufInc ) { + desc->xfer.dst_inc = SL_HAL_LDMA_CTRL_DST_INC_NONE; + } + } + + xfer.request_sel = peripheralSignal; + desc->xfer.xfer_count = len - 1; + desc->xfer.dst_addr = (uint32_t)(uint8_t *)buf0; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.size = size; + + if ( mode == dmaModePingPong ) { + desc->xfer.link_mode = SL_HAL_LDMA_LINK_MODE_REL; + desc->xfer.link = 1; + desc->xfer.link_addr = 4; /* Refer to the "pong" descriptor. */ + + /* Set the "pong" descriptor equal to the "ping" descriptor. */ + dmaXfer[channelId].desc[1] = *desc; + /* Refer to the "ping" descriptor. */ + dmaXfer[channelId].desc[1].xfer.link_addr = -4; + dmaXfer[channelId].desc[1].xfer.src_addr = (uint32_t)(uint8_t *)buf2; + + if ( direction == dmaDirectionPeripheralToMem ) { + dmaXfer[channelId].desc[1].xfer.dst_addr = (uint32_t)(uint8_t *)buf1; + desc->xfer.src_addr = (uint32_t)(uint8_t *)buf2; + } + } + + /* Whether an interrupt is needed. */ + if ( (callback == NULL) && (mode == dmaModeBasic) ) { + desc->xfer.done_ifs = 0; + } + + ch->callback = callback; + ch->userParam = cbUserParam; + ch->callbackCount = 0; + ch->mode = mode; + + sl_hal_ldma_init_transfer(channelId, &xfer, desc); + sl_hal_ldma_start_transfer(channelId); + sl_hal_ldma_enable_interrupts((0x1UL << channelId)); + + return ECODE_EMDRV_DMADRV_OK; +} +#endif /* defined( EMDRV_DMADRV_LDMA_S3 ) */ + +/// @endcond + +// ******** THE REST OF THE FILE IS DOCUMENTATION ONLY !*********************** +/// @addtogroup dmadrv DMADRV - DMA Driver +/// @brief Direct Memory Access Driver +/// @{ +/// +/// @details +/// +/// +/// @n @section dmadrv_intro Introduction +/// +/// The DMADRV driver supports writing code using DMA which will work +/// regardless of the type of the DMA controller on the underlying microcontroller. +/// Additionally, DMA can be used in several modules that are +/// completely unaware of each other. +/// The driver does not preclude use of the native emlib API of the underlying +/// DMA controller. On the contrary, it will often result in more efficient +/// code and is necessary for complex DMA operations. The housekeeping +/// functions of this driver are valuable even in this use-case. +/// +/// The dmadrv.c and dmadrv.h source files are in the +/// emdrv/dmadrv folder. +/// +/// @note DMA transfer completion callback functions are called from within the +/// DMA interrupt handler. +/// +/// @n @section dmadrv_conf Configuration Options +/// +/// Some properties of the DMADRV driver are compile-time configurable. These +/// properties are stored in a file named dmadrv_config.h. A template for this +/// file, containing default values, is in the emdrv/config folder. +/// Currently the configuration options are as follows: +/// @li The interrupt priority of the DMA peripheral. +/// @li A number of DMA channels to support. +/// @li Use the native emlib API belonging to the underlying DMA hardware in +/// combination with the DMADRV API. +/// +/// Both configuration options will help reduce the driver's RAM footprint. +/// +/// To configure DMADRV, provide a custom configuration file. This is an +/// example dmadrv_config.h file: +/// @code{.c} +/// #ifndef __SILICON_LABS_DMADRV_CONFIG_H__ +/// #define __SILICON_LABS_DMADRV_CONFIG_H__ +/// +/// // DMADRV DMA interrupt priority configuration option. +/// // Set DMA interrupt priority. Range is 0..7, 0 is the highest priority. +/// #define EMDRV_DMADRV_DMA_IRQ_PRIORITY 4 +/// +/// // DMADRV channel count configuration option. +/// // A number of DMA channels to support. A lower DMA channel count will reduce +/// // RAM footprint. +/// #define EMDRV_DMADRV_DMA_CH_COUNT 4 +/// +/// #endif +/// @endcode +/// +/// @n @section dmadrv_api The API +/// +/// This section contains brief descriptions of the API functions. +/// For more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, @ref ECODE_EMDRV_DMADRV_OK is returned on success, +/// see @ref ecode and @ref dmadrv_error_codes for other error codes. +/// +/// The application code must include @em dmadrv.h header file. +/// +/// @ref DMADRV_Init(), @ref DMADRV_DeInit() @n +/// These functions initialize or deinitialize the DMADRV driver. Typically, +/// DMADRV_Init() is called once in the startup code. +/// +/// @ref DMADRV_AllocateChannel(), @ref DMADRV_FreeChannel() @n +/// DMA channel reserve and release functions. It is recommended that +/// application code check that DMADRV_AllocateChannel() +/// returns ECODE_EMDRV_DMADRV_OK before starting a DMA +/// transfer. +/// +/// @ref DMADRV_MemoryPeripheral() @n +/// Start a DMA transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemory() @n +/// Start a DMA transfer from a peripheral to memory. +/// +/// @ref DMADRV_MemoryPeripheralPingPong() @n +/// Start a DMA ping-pong transfer from memory to a peripheral. +/// +/// @ref DMADRV_PeripheralMemoryPingPong() @n +/// Start a DMA ping-pong transfer from a peripheral to memory. +/// +/// @ref DMADRV_LdmaStartTransfer() @n +/// Start a DMA transfer on an LDMA controller. +/// +/// @ref DMADRV_StopTransfer() @n +/// Stop an ongoing DMA transfer. +/// +/// @ref DMADRV_TransferActive() @n +/// Check if a transfer is ongoing. +/// +/// @ref DMADRV_TransferCompletePending() @n +/// Check if a transfer completion is pending. +/// +/// @ref DMADRV_TransferDone() @n +/// Check if a transfer has completed. +/// +/// @ref DMADRV_TransferRemainingCount() @n +/// Get number of items remaining in a transfer. +/// +/// @n @section dmadrv_example Example +/// Transfer a text string to USART1. +/// @code{.c} +/// #include "dmadrv.h" +/// +/// char str[] = "Hello DMA !"; +/// unsigned int channel; +/// +/// int main( void ) +/// { +/// // Initialize DMA. +/// DMADRV_Init(); +/// +/// // Request a DMA channel. +/// DMADRV_AllocateChannel( &channel, NULL ); +/// +/// // Start the DMA transfer. +/// DMADRV_MemoryPeripheral( channel, +/// dmadrvPeripheralSignal_USART1_TXBL, +/// (void*)&(USART1->TXDATA), +/// str, +/// true, +/// sizeof( str ), +/// dmadrvDataSize1, +/// NULL, +/// NULL ); +/// +/// return 0; +/// } +/// @endcode +/// +/// @} end group dmadrv ******************************************************** diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h index 2ab8065..74349b6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/inc/gpiointerrupt.h @@ -1,102 +1,102 @@ -/***************************************************************************//** - * @file - * @brief GPIOINT API definition - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef GPIOINTERRUPT_H -#define GPIOINTERRUPT_H - -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup gpioint - * @{ - ******************************************************************************/ -/******************************************************************************* - ***************************** DEFINITIONS ********************************* - ******************************************************************************/ - -#define INTERRUPT_UNAVAILABLE (0xFF) ///< A MACRO for Interrupt Un-available. - -/******************************************************************************* - ******************************* TYPEDEFS ********************************** - ******************************************************************************/ - -/** - * @brief - * GPIO interrupt callback function pointer. - * @details - * Parameters: - * @li intNo - The pin interrupt number the callback function is invoked for. - */ -typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo); - -/** - * @brief - * Extended GPIO interrupt callback function pointer. - * @details - * Parameters: - * @li intNo - The pin interrupt number the callback function is invoked for. - * @li ctx - Pointer to callback context. - */ -typedef void (*GPIOINT_IrqCallbackPtrExt_t)(uint8_t intNo, void *ctx); - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ -void GPIOINT_Init(void); -void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr); -unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx); -__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); - -/***************************************************************************//** - * @brief - * Unregister user callback for a given pin interrupt number. - * - * @details - * Use this function to unregister a callback. - * - * @param[in] intNo - * Pin interrupt number for the callback. - * - ******************************************************************************/ -__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) -{ - GPIOINT_CallbackRegister(intNo, 0); -} - -/** @} (end addtogroup gpioint) */ -#ifdef __cplusplus -} -#endif - -#endif /* GPIOINTERRUPT_H */ +/***************************************************************************//** + * @file + * @brief GPIOINT API definition + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef GPIOINTERRUPT_H +#define GPIOINTERRUPT_H + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup gpioint + * @{ + ******************************************************************************/ +/******************************************************************************* + ***************************** DEFINITIONS ********************************* + ******************************************************************************/ + +#define INTERRUPT_UNAVAILABLE (0xFF) ///< A MACRO for Interrupt Un-available. + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +/** + * @brief + * GPIO interrupt callback function pointer. + * @details + * Parameters: + * @li intNo - The pin interrupt number the callback function is invoked for. + */ +typedef void (*GPIOINT_IrqCallbackPtr_t)(uint8_t intNo); + +/** + * @brief + * Extended GPIO interrupt callback function pointer. + * @details + * Parameters: + * @li intNo - The pin interrupt number the callback function is invoked for. + * @li ctx - Pointer to callback context. + */ +typedef void (*GPIOINT_IrqCallbackPtrExt_t)(uint8_t intNo, void *ctx); + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ +void GPIOINT_Init(void); +void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr); +unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx); +__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo); + +/***************************************************************************//** + * @brief + * Unregister user callback for a given pin interrupt number. + * + * @details + * Use this function to unregister a callback. + * + * @param[in] intNo + * Pin interrupt number for the callback. + * + ******************************************************************************/ +__STATIC_INLINE void GPIOINT_CallbackUnRegister(uint8_t intNo) +{ + GPIOINT_CallbackRegister(intNo, 0); +} + +/** @} (end addtogroup gpioint) */ +#ifdef __cplusplus +} +#endif + +#endif /* GPIOINTERRUPT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c index 049a970..6358fa7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c @@ -1,366 +1,366 @@ -/***************************************************************************//** - * @file - * @brief GPIOINT API implementation - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_gpio.h" -#include "em_core.h" -#include "gpiointerrupt.h" -#include "sl_assert.h" -#include "sl_common.h" - -/***************************************************************************//** - * @addtogroup gpioint - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#define _GPIOINT_IF_EVEN_MASK ((_GPIO_IF_MASK) & 0x55555555UL) -#define _GPIOINT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) - -/******************************************************************************* - ******************************** MACROS *********************************** - ******************************************************************************/ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -typedef struct { - /* Pin interrupt number in range of 0 to 31 */ - uint32_t intNo; - /* Pointer to the callback function */ - void *callback; - /* Pointer to the callback context */ - void *context; - /* True if callback takes a context */ - bool context_flag; -} GPIOINT_CallbackDesc_t; - -/******************************************************************************* - ******************************** GLOBALS ********************************** - ******************************************************************************/ - -/* Array of user callbacks. One for each pin interrupt number. */ -static GPIOINT_CallbackDesc_t gpioCallbacks[32] = { 0 }; - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ -static void GPIOINT_IRQDispatcher(uint32_t iflags); - -/** @endcond */ - -/******************************************************************************* - *************************** GLOBAL FUNCTIONS ****************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialization of GPIOINT module. - * - ******************************************************************************/ -void GPIOINT_Init(void) -{ - if (CORE_NvicIRQDisabled(GPIO_ODD_IRQn)) { - NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); - NVIC_EnableIRQ(GPIO_ODD_IRQn); - } - if (CORE_NvicIRQDisabled(GPIO_EVEN_IRQn)) { - NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - } -} - -/***************************************************************************//** - * @brief - * Registers user callback for given pin interrupt number. - * - * @details - * Use this function to register a callback which shall be called upon - * interrupt generated for a given pin interrupt number. - * Interrupt itself must be configured externally. Function overwrites previously - * registered callback. - * - * @param[in] intNo - * Pin interrupt number for the callback. - * @param[in] callbackPtr - * A pointer to callback function. - ******************************************************************************/ -void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr) -{ - CORE_ATOMIC_SECTION( - /* Dispatcher is used */ - gpioCallbacks[intNo].callback = (void *)callbackPtr; - gpioCallbacks[intNo].context_flag = false; - ) -} - -/***************************************************************************//** - * @brief - * Registers user callback for given pin interrupt number. - * - * @details - * Use this function to register a callback with context which shall be called upon - * interrupt generated for a given pin number. - * The function will return an interrupt number if one is available. - * Interrupt itself must be configured externally. - * - * @param[in] pin - * Pin number for the callback. - * @param[in] callbackPtr - * A pointer to callback function. - * @param[in] callbackCtx - * A pointer to the callback context. - * - * @return - * Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use - ******************************************************************************/ -unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx) -{ - CORE_DECLARE_IRQ_STATE; - unsigned int intNo = INTERRUPT_UNAVAILABLE; - - CORE_ENTER_ATOMIC(); - -#if defined(_GPIO_EXTIPINSELL_MASK) - uint32_t intToCheck; - uint32_t intGroupStart = (pin & 0xFFC); - uint32_t intsEnabled = GPIO_EnabledIntGet(); - - // loop through the interrupt group, starting - // from the pin number, and take - // the first available - for (uint8_t i = 0; i < 4; i++) { - intToCheck = intGroupStart + ((pin + i) & 0x3); // modulo 4 - if (((intsEnabled >> intToCheck) & 0x1) == 0) { - intNo = (unsigned int)intToCheck; - break; - } - } -#else - if (gpioCallbacks[pin].callback == 0) { - intNo = (unsigned int)pin; - } -#endif - - if (intNo != INTERRUPT_UNAVAILABLE) { - gpioCallbacks[intNo].callback = (void *)callbackPtr; - gpioCallbacks[intNo].context = callbackCtx; - gpioCallbacks[intNo].context_flag = true; - } - - CORE_EXIT_ATOMIC(); - - return intNo; -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Function calls users callback for registered pin interrupts. - * - * @details - * This function is called when GPIO interrupts are handled by the IRQHandlers. - * Function gets even or odd interrupt flags and calls user callback - * registered for that pin. Function iterates on flags starting from MSB. - * - * @param iflags - * Interrupt flags which shall be handled by the dispatcher. - * - ******************************************************************************/ -static void GPIOINT_IRQDispatcher(uint32_t iflags) -{ - uint32_t irqIdx; - GPIOINT_CallbackDesc_t *callback; - - /* check for all flags set in IF register */ - while (iflags != 0U) { - irqIdx = SL_CTZ(iflags); - - /* clear flag*/ - iflags &= ~(1UL << irqIdx); - - callback = &gpioCallbacks[irqIdx]; - if (callback->callback) { - /* call user callback */ - if (callback->context_flag) { - GPIOINT_IrqCallbackPtrExt_t func = (GPIOINT_IrqCallbackPtrExt_t)(callback->callback); - func((uint8_t)irqIdx, callback->context); - } else { - GPIOINT_IrqCallbackPtr_t func = (GPIOINT_IrqCallbackPtr_t)(callback->callback); - func((uint8_t)irqIdx); - } - } - } -} - -/***************************************************************************//** - * @brief - * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and - * call the dispatcher passing the flags which triggered the interrupt. - * - ******************************************************************************/ -void GPIO_EVEN_IRQHandler(void) -{ - uint32_t iflags; - - /* Get all even interrupts. */ - iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_EVEN_MASK; - - /* Clean only even interrupts. */ - GPIO_IntClear(iflags); - - GPIOINT_IRQDispatcher(iflags); -} - -/***************************************************************************//** - * @brief - * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and - * call the dispatcher passing the flags which triggered the interrupt. - * - ******************************************************************************/ -void GPIO_ODD_IRQHandler(void) -{ - uint32_t iflags; - - /* Get all odd interrupts. */ - iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_ODD_MASK; - - /* Clean only odd interrupts. */ - GPIO_IntClear(iflags); - - GPIOINT_IRQDispatcher(iflags); -} - -/** @endcond */ - -/** @} (end addtogroup gpioint) */ - -/* *INDENT-OFF* */ -// ******* THE REST OF THE FILE IS DOCUMENTATION ONLY !************************ -/// @addtogroup gpioint GPIOINT - GPIO Interrupt -/// @brief GPIOINT General Purpose Input/Output Interrupt dispatcher -/// @{ -/// -/// @details -/// The source files for the GPIO interrupt dispatcher library resides in the -/// emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h. -/// -/// -/// @n @section gpioint_intro Introduction -/// EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more -/// than two interrupts are used then interrupt routine must dispatch from a callback -/// register. This module provides small dispatcher for both GPIO interrupts enabling -/// handling of up to 32 GPIO pin interrupts. -/// -/// It is up to the user to configure and enable interrupt on given pin. This can be done -/// using the GPIO library (emlib). This module handles the dispatch register and clearing of -/// interrupt flags. -/// -/// In order to use this dispatcher, it has to be initialized first by -/// calling GPIOINT_Init(). Then each pin interrupt number must be configured by first -/// registering the callback function for given interrupt number and then configure and -/// enabling the interrupt number in the GPIO module. -/// -/// The extended function GPIOINT_CallbackRegisterExt() may also be used to register a callback -/// with context for a given pin number. The first available interrupt number will be returned. -/// -/// @n @section gpioint_api The API -/// This section contain brief descriptions of the functions in the API. You will -/// find detailed information on parameters by clicking on the hyperlinked function names. -/// -/// Your application code must include one header file: @em gpiointerrupt.h. -/// -/// @ref GPIOINT_Init() @n -/// This functions initializes the dispatcher register. Typically -/// GPIOINT_Init() is called once in your startup code. -/// -/// @ref GPIOINT_CallbackRegister() @n -/// Register a callback function on a pin interrupt number. -/// -/// @ref GPIOINT_CallbackUnRegister() @n -/// Un-register a callback function on a pin interrupt number. -/// -/// @ref GPIOINT_CallbackRegisterExt() @n -/// Register a callback function with context on a pin number. -/// -/// @n @section gpioint_example Example -/// @code{.c} -/// -///#include "gpiointerrupt.h" -/// -///#include "em_chip.h" -///#include "em_cmu.h" -///#include "em_gpio.h" -/// -///// An array to track if given pin callback was called -///volatile uint8_t pinInt[32]; -/// -///// Gpio callbacks called when pin interrupt was triggered. -///void gpioCallback1(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///void gpioCallback3(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///void gpioCallback8(uint8_t intNo) -///{ -/// pinInt[intNo]++; -///} -/// -///int main(void) -///{ -/// CHIP_Init(); -/// -/// // Enable clock for GPIO module, initialize GPIOINT -/// CMU_ClockEnable(cmuClock_GPIO, true); -/// GPIOINT_Init(); -/// -/// // Register callback functions and enable interrupts -/// GPIOINT_CallbackRegister(1, gpioCallback1); -/// GPIOINT_CallbackRegister(3, gpioCallback3); -/// unsigned int intPin8 = GPIOINT_CallbackRegisterExt(8, gpioCallback8, (void *)callback8context); -/// GPIO_IntEnable(1<<1 | 1<<3 | 1<Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_gpio.h" +#include "em_core.h" +#include "gpiointerrupt.h" +#include "sl_assert.h" +#include "sl_common.h" + +/***************************************************************************//** + * @addtogroup gpioint + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#define _GPIOINT_IF_EVEN_MASK ((_GPIO_IF_MASK) & 0x55555555UL) +#define _GPIOINT_IF_ODD_MASK ((_GPIO_IF_MASK) & 0xAAAAAAAAUL) + +/******************************************************************************* + ******************************** MACROS *********************************** + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +typedef struct { + /* Pin interrupt number in range of 0 to 31 */ + uint32_t intNo; + /* Pointer to the callback function */ + void *callback; + /* Pointer to the callback context */ + void *context; + /* True if callback takes a context */ + bool context_flag; +} GPIOINT_CallbackDesc_t; + +/******************************************************************************* + ******************************** GLOBALS ********************************** + ******************************************************************************/ + +/* Array of user callbacks. One for each pin interrupt number. */ +static GPIOINT_CallbackDesc_t gpioCallbacks[32] = { 0 }; + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ +static void GPIOINT_IRQDispatcher(uint32_t iflags); + +/** @endcond */ + +/******************************************************************************* + *************************** GLOBAL FUNCTIONS ****************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialization of GPIOINT module. + * + ******************************************************************************/ +void GPIOINT_Init(void) +{ + if (CORE_NvicIRQDisabled(GPIO_ODD_IRQn)) { + NVIC_ClearPendingIRQ(GPIO_ODD_IRQn); + NVIC_EnableIRQ(GPIO_ODD_IRQn); + } + if (CORE_NvicIRQDisabled(GPIO_EVEN_IRQn)) { + NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); + NVIC_EnableIRQ(GPIO_EVEN_IRQn); + } +} + +/***************************************************************************//** + * @brief + * Registers user callback for given pin interrupt number. + * + * @details + * Use this function to register a callback which shall be called upon + * interrupt generated for a given pin interrupt number. + * Interrupt itself must be configured externally. Function overwrites previously + * registered callback. + * + * @param[in] intNo + * Pin interrupt number for the callback. + * @param[in] callbackPtr + * A pointer to callback function. + ******************************************************************************/ +void GPIOINT_CallbackRegister(uint8_t intNo, GPIOINT_IrqCallbackPtr_t callbackPtr) +{ + CORE_ATOMIC_SECTION( + /* Dispatcher is used */ + gpioCallbacks[intNo].callback = (void *)callbackPtr; + gpioCallbacks[intNo].context_flag = false; + ) +} + +/***************************************************************************//** + * @brief + * Registers user callback for given pin interrupt number. + * + * @details + * Use this function to register a callback with context which shall be called upon + * interrupt generated for a given pin number. + * The function will return an interrupt number if one is available. + * Interrupt itself must be configured externally. + * + * @param[in] pin + * Pin number for the callback. + * @param[in] callbackPtr + * A pointer to callback function. + * @param[in] callbackCtx + * A pointer to the callback context. + * + * @return + * Interrupt number, or INTERRUPT_UNAVAILABLE if all are in use + ******************************************************************************/ +unsigned int GPIOINT_CallbackRegisterExt(uint8_t pin, GPIOINT_IrqCallbackPtrExt_t callbackPtr, void *callbackCtx) +{ + CORE_DECLARE_IRQ_STATE; + unsigned int intNo = INTERRUPT_UNAVAILABLE; + + CORE_ENTER_ATOMIC(); + +#if defined(_GPIO_EXTIPINSELL_MASK) + uint32_t intToCheck; + uint32_t intGroupStart = (pin & 0xFFC); + uint32_t intsEnabled = GPIO_EnabledIntGet(); + + // loop through the interrupt group, starting + // from the pin number, and take + // the first available + for (uint8_t i = 0; i < 4; i++) { + intToCheck = intGroupStart + ((pin + i) & 0x3); // modulo 4 + if (((intsEnabled >> intToCheck) & 0x1) == 0) { + intNo = (unsigned int)intToCheck; + break; + } + } +#else + if (gpioCallbacks[pin].callback == 0) { + intNo = (unsigned int)pin; + } +#endif + + if (intNo != INTERRUPT_UNAVAILABLE) { + gpioCallbacks[intNo].callback = (void *)callbackPtr; + gpioCallbacks[intNo].context = callbackCtx; + gpioCallbacks[intNo].context_flag = true; + } + + CORE_EXIT_ATOMIC(); + + return intNo; +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Function calls users callback for registered pin interrupts. + * + * @details + * This function is called when GPIO interrupts are handled by the IRQHandlers. + * Function gets even or odd interrupt flags and calls user callback + * registered for that pin. Function iterates on flags starting from MSB. + * + * @param iflags + * Interrupt flags which shall be handled by the dispatcher. + * + ******************************************************************************/ +static void GPIOINT_IRQDispatcher(uint32_t iflags) +{ + uint32_t irqIdx; + GPIOINT_CallbackDesc_t *callback; + + /* check for all flags set in IF register */ + while (iflags != 0U) { + irqIdx = SL_CTZ(iflags); + + /* clear flag*/ + iflags &= ~(1UL << irqIdx); + + callback = &gpioCallbacks[irqIdx]; + if (callback->callback) { + /* call user callback */ + if (callback->context_flag) { + GPIOINT_IrqCallbackPtrExt_t func = (GPIOINT_IrqCallbackPtrExt_t)(callback->callback); + func((uint8_t)irqIdx, callback->context); + } else { + GPIOINT_IrqCallbackPtr_t func = (GPIOINT_IrqCallbackPtr_t)(callback->callback); + func((uint8_t)irqIdx); + } + } + } +} + +/***************************************************************************//** + * @brief + * GPIO EVEN interrupt handler. Interrupt handler clears all IF even flags and + * call the dispatcher passing the flags which triggered the interrupt. + * + ******************************************************************************/ +void GPIO_EVEN_IRQHandler(void) +{ + uint32_t iflags; + + /* Get all even interrupts. */ + iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_EVEN_MASK; + + /* Clean only even interrupts. */ + GPIO_IntClear(iflags); + + GPIOINT_IRQDispatcher(iflags); +} + +/***************************************************************************//** + * @brief + * GPIO ODD interrupt handler. Interrupt handler clears all IF odd flags and + * call the dispatcher passing the flags which triggered the interrupt. + * + ******************************************************************************/ +void GPIO_ODD_IRQHandler(void) +{ + uint32_t iflags; + + /* Get all odd interrupts. */ + iflags = GPIO_IntGetEnabled() & _GPIOINT_IF_ODD_MASK; + + /* Clean only odd interrupts. */ + GPIO_IntClear(iflags); + + GPIOINT_IRQDispatcher(iflags); +} + +/** @endcond */ + +/** @} (end addtogroup gpioint) */ + +/* *INDENT-OFF* */ +// ******* THE REST OF THE FILE IS DOCUMENTATION ONLY !************************ +/// @addtogroup gpioint GPIOINT - GPIO Interrupt +/// @brief GPIOINT General Purpose Input/Output Interrupt dispatcher +/// @{ +/// +/// @details +/// The source files for the GPIO interrupt dispatcher library resides in the +/// emdrv/gpiointerrupt folder, and are named gpiointerrupt.c and gpiointerrupt.h. +/// +/// +/// @n @section gpioint_intro Introduction +/// EFM32/EZR32/EFR32 has two GPIO interrupts lines, Odd and Even. If more +/// than two interrupts are used then interrupt routine must dispatch from a callback +/// register. This module provides small dispatcher for both GPIO interrupts enabling +/// handling of up to 32 GPIO pin interrupts. +/// +/// It is up to the user to configure and enable interrupt on given pin. This can be done +/// using the GPIO library (emlib). This module handles the dispatch register and clearing of +/// interrupt flags. +/// +/// In order to use this dispatcher, it has to be initialized first by +/// calling GPIOINT_Init(). Then each pin interrupt number must be configured by first +/// registering the callback function for given interrupt number and then configure and +/// enabling the interrupt number in the GPIO module. +/// +/// The extended function GPIOINT_CallbackRegisterExt() may also be used to register a callback +/// with context for a given pin number. The first available interrupt number will be returned. +/// +/// @n @section gpioint_api The API +/// This section contain brief descriptions of the functions in the API. You will +/// find detailed information on parameters by clicking on the hyperlinked function names. +/// +/// Your application code must include one header file: @em gpiointerrupt.h. +/// +/// @ref GPIOINT_Init() @n +/// This functions initializes the dispatcher register. Typically +/// GPIOINT_Init() is called once in your startup code. +/// +/// @ref GPIOINT_CallbackRegister() @n +/// Register a callback function on a pin interrupt number. +/// +/// @ref GPIOINT_CallbackUnRegister() @n +/// Un-register a callback function on a pin interrupt number. +/// +/// @ref GPIOINT_CallbackRegisterExt() @n +/// Register a callback function with context on a pin number. +/// +/// @n @section gpioint_example Example +/// @code{.c} +/// +///#include "gpiointerrupt.h" +/// +///#include "em_chip.h" +///#include "em_cmu.h" +///#include "em_gpio.h" +/// +///// An array to track if given pin callback was called +///volatile uint8_t pinInt[32]; +/// +///// Gpio callbacks called when pin interrupt was triggered. +///void gpioCallback1(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///void gpioCallback3(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///void gpioCallback8(uint8_t intNo) +///{ +/// pinInt[intNo]++; +///} +/// +///int main(void) +///{ +/// CHIP_Init(); +/// +/// // Enable clock for GPIO module, initialize GPIOINT +/// CMU_ClockEnable(cmuClock_GPIO, true); +/// GPIOINT_Init(); +/// +/// // Register callback functions and enable interrupts +/// GPIOINT_CallbackRegister(1, gpioCallback1); +/// GPIOINT_CallbackRegister(3, gpioCallback3); +/// unsigned int intPin8 = GPIOINT_CallbackRegisterExt(8, gpioCallback8, (void *)callback8context); +/// GPIO_IntEnable(1<<1 | 1<<3 | 1<Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_H -#define NVM3_H - -#ifndef NVM3_HOST_BUILD -#include "em_device.h" -#endif - -#include "nvm3_generic.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -#define NVM3_MIN_FRAGMENT_COUNT (2U) ///< The minimum number of fragments -#if defined(FLASH_PAGE_SIZE) -#define NVM3_MAX_OBJECT_SIZE_X (NVM3_MAX_OBJECT_SIZE + 8) // Adjust for an object header -#define FLASH_PAGE_SIZE_X (FLASH_PAGE_SIZE - 20) // Adjust for a page header -#define NVM3_FRAGMENT_COUNT (((NVM3_MAX_OBJECT_SIZE_X - 1) / FLASH_PAGE_SIZE_X) + NVM3_MIN_FRAGMENT_COUNT) -#endif - -typedef struct nvm3_ObjFrag { - uint8_t idx; // Fragment index - bool isFirstFragFound; // The object first fragment found - bool isLastFragFound; // The object last fragment found -#if defined(FLASH_PAGE_SIZE) - nvm3_ObjFragDetail_t detail[NVM3_FRAGMENT_COUNT]; -#else - nvm3_ObjFragDetail_t detail[NVM3_MIN_FRAGMENT_COUNT]; -#endif -} nvm3_ObjFrag_t; - -typedef struct nvm3_Obj { - nvm3_ObjectKey_t key; // The object key - struct nvm3_Obj *objAdr; // The object pointer - struct nvm3_Obj *nextObjAdr; // The next object pointer - const void *srcPtr; // May be used to carry the source address of the data - size_t totalLen; // The object total length - uint8_t objType; // The object type - bool isHdrValid; // The object header is valid - bool isValid; // The object is valid - bool isFragmented; // The object is fragmented - nvm3_ObjFrag_t frag; // The object fragment information -} nvm3_Obj_t; - -// Definition of NVM3 variables -/// @brief A variable used by the NVM3 functions. -extern nvm3_Obj_t nvm3_internalObjectHandleA; -/// @brief A variable used by the NVM3 functions. -extern nvm3_Obj_t nvm3_internalObjectHandleB; -/// @brief A variable used by the NVM3 functions. -extern nvm3_Obj_t nvm3_internalObjectHandleC; -/// @brief A variable used by the NVM3 functions. -extern nvm3_Obj_t nvm3_internalObjectHandleD; -/// @brief A variable that must contain the maximum number of object fragments. -extern const uint8_t nvm3_maxFragmentCount; -/// @brief A variable containing the object handle size in bytes. -extern const size_t nvm3_objHandleSize; - -#ifdef __cplusplus -} -#endif - -/// @} end group nvm3 ****************************************************/ - -#endif /* NVM3_H */ +/***************************************************************************//** + * @file + * @brief NVM3 API definition (Device Specific). + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_H +#define NVM3_H + +#ifndef NVM3_HOST_BUILD +#include "em_device.h" +#endif + +#include "nvm3_generic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +#define NVM3_MIN_FRAGMENT_COUNT (2U) ///< The minimum number of fragments +#if defined(FLASH_PAGE_SIZE) +#define NVM3_MAX_OBJECT_SIZE_X (NVM3_MAX_OBJECT_SIZE + 8) // Adjust for an object header +#define FLASH_PAGE_SIZE_X (FLASH_PAGE_SIZE - 20) // Adjust for a page header +#define NVM3_FRAGMENT_COUNT (((NVM3_MAX_OBJECT_SIZE_X - 1) / FLASH_PAGE_SIZE_X) + NVM3_MIN_FRAGMENT_COUNT) +#endif + +typedef struct nvm3_ObjFrag { + uint8_t idx; // Fragment index + bool isFirstFragFound; // The object first fragment found + bool isLastFragFound; // The object last fragment found +#if defined(FLASH_PAGE_SIZE) + nvm3_ObjFragDetail_t detail[NVM3_FRAGMENT_COUNT]; +#else + nvm3_ObjFragDetail_t detail[NVM3_MIN_FRAGMENT_COUNT]; +#endif +} nvm3_ObjFrag_t; + +typedef struct nvm3_Obj { + nvm3_ObjectKey_t key; // The object key + struct nvm3_Obj *objAdr; // The object pointer + struct nvm3_Obj *nextObjAdr; // The next object pointer + const void *srcPtr; // May be used to carry the source address of the data + size_t totalLen; // The object total length + uint8_t objType; // The object type + bool isHdrValid; // The object header is valid + bool isValid; // The object is valid + bool isFragmented; // The object is fragmented + nvm3_ObjFrag_t frag; // The object fragment information +} nvm3_Obj_t; + +// Definition of NVM3 variables +/// @brief A variable used by the NVM3 functions. +extern nvm3_Obj_t nvm3_internalObjectHandleA; +/// @brief A variable used by the NVM3 functions. +extern nvm3_Obj_t nvm3_internalObjectHandleB; +/// @brief A variable used by the NVM3 functions. +extern nvm3_Obj_t nvm3_internalObjectHandleC; +/// @brief A variable used by the NVM3 functions. +extern nvm3_Obj_t nvm3_internalObjectHandleD; +/// @brief A variable that must contain the maximum number of object fragments. +extern const uint8_t nvm3_maxFragmentCount; +/// @brief A variable containing the object handle size in bytes. +extern const size_t nvm3_objHandleSize; + +#ifdef __cplusplus +} +#endif + +/// @} end group nvm3 ****************************************************/ + +#endif /* NVM3_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_default.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_default.h index d1a462b..093cfee 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_default.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_default.h @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief NVM3 definition of the default data structures. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_DEFAULT_H -#define NVM3_DEFAULT_H -#include "nvm3_generic.h" - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ -/***************************************************************************//** - * @addtogroup nvm3default NVM3 Default Instance - * @brief NVM3 default instance functions and handles - * @{ - ******************************************************************************/ - -extern nvm3_Handle_t *nvm3_defaultHandle; ///< The default handle. -extern nvm3_Init_t *nvm3_defaultInit; ///< Default initialization data. - -/***************************************************************************//** - * @brief - * Initialize the default NVM3 instance. - * Once initialized the instance can be accessed through the NVM3 API using - * nvm3_defaultHandle as the nvm3_Handle_t handle. - * - * @return - * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_initDefault(void); - -/***************************************************************************//** - * @brief - * Deinit the default NVM3 instance. - * - * @return - * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_deinitDefault(void); - -/** @} (end addtogroup nvm3default) */ -/** @} (end addtogroup nvm3) */ - -#endif /* NVM3_DEFAULT_H */ +/***************************************************************************//** + * @file + * @brief NVM3 definition of the default data structures. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_DEFAULT_H +#define NVM3_DEFAULT_H +#include "nvm3_generic.h" + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ +/***************************************************************************//** + * @addtogroup nvm3default NVM3 Default Instance + * @brief NVM3 default instance functions and handles + * @{ + ******************************************************************************/ + +extern nvm3_Handle_t *nvm3_defaultHandle; ///< The default handle. +extern nvm3_Init_t *nvm3_defaultInit; ///< Default initialization data. + +/***************************************************************************//** + * @brief + * Initialize the default NVM3 instance. + * Once initialized the instance can be accessed through the NVM3 API using + * nvm3_defaultHandle as the nvm3_Handle_t handle. + * + * @return + * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_initDefault(void); + +/***************************************************************************//** + * @brief + * Deinit the default NVM3 instance. + * + * @return + * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_deinitDefault(void); + +/** @} (end addtogroup nvm3default) */ +/** @} (end addtogroup nvm3) */ + +#endif /* NVM3_DEFAULT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_generic.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_generic.h index f744801..76f1b57 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_generic.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_generic.h @@ -1,1007 +1,1007 @@ -/***************************************************************************//** - * @file - * @brief NVM3 API definition (Generic). - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_GENERIC_H -#define NVM3_GENERIC_H - -#include -#include -#include - -#include "nvm3_hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -#define ECODE_NVM3_OK (ECODE_OK) ///< Success return value -#define ECODE_NVM3_ERR_ALIGNMENT_INVALID (ECODE_EMDRV_NVM3_BASE | 0x00000001U) ///< Invalid data alignment -#define ECODE_NVM3_ERR_SIZE_TOO_SMALL (ECODE_EMDRV_NVM3_BASE | 0x00000002U) ///< Not enough NVM memory specified -#define ECODE_NVM3_ERR_NO_VALID_PAGES (ECODE_EMDRV_NVM3_BASE | 0x00000003U) ///< Initialization aborted, no valid page found -#define ECODE_NVM3_ERR_PAGE_SIZE_NOT_SUPPORTED (ECODE_EMDRV_NVM3_BASE | 0x00000004U) ///< The page size is not supported -#define ECODE_NVM3_ERR_OBJECT_SIZE_NOT_SUPPORTED (ECODE_EMDRV_NVM3_BASE | 0x00000005U) ///< The object size is not supported -#define ECODE_NVM3_ERR_STORAGE_FULL (ECODE_EMDRV_NVM3_BASE | 0x00000006U) ///< No more NVM space available -#define ECODE_NVM3_ERR_NOT_OPENED (ECODE_EMDRV_NVM3_BASE | 0x00000007U) ///< The module has not been successfully opened -#define ECODE_NVM3_ERR_OPENED_WITH_OTHER_PARAMETERS (ECODE_EMDRV_NVM3_BASE | 0x00000008U) ///< The module has already been opened with other parameters -#define ECODE_NVM3_ERR_PARAMETER (ECODE_EMDRV_NVM3_BASE | 0x00000009U) ///< Illegal parameter -#define ECODE_NVM3_ERR_KEY_INVALID (ECODE_EMDRV_NVM3_BASE | 0x0000000AU) ///< Invalid key value -#define ECODE_NVM3_ERR_KEY_NOT_FOUND (ECODE_EMDRV_NVM3_BASE | 0x0000000BU) ///< Key not found -#define ECODE_NVM3_ERR_OBJECT_IS_NOT_DATA (ECODE_EMDRV_NVM3_BASE | 0x0000000CU) ///< Trying to access a data object which is currently a counter object -#define ECODE_NVM3_ERR_OBJECT_IS_NOT_A_COUNTER (ECODE_EMDRV_NVM3_BASE | 0x0000000DU) ///< Trying to access a counter object which is currently a data object -#define ECODE_NVM3_ERR_ERASE_FAILED (ECODE_EMDRV_NVM3_BASE | 0x0000000EU) ///< Erase failed -#define ECODE_NVM3_ERR_WRITE_DATA_SIZE (ECODE_EMDRV_NVM3_BASE | 0x0000000FU) ///< The object is too large -#define ECODE_NVM3_ERR_WRITE_FAILED (ECODE_EMDRV_NVM3_BASE | 0x00000010U) ///< Error in the write operation -#define ECODE_NVM3_ERR_READ_DATA_SIZE (ECODE_EMDRV_NVM3_BASE | 0x00000011U) ///< Trying to read with a length different from actual object size -#define ECODE_NVM3_ERR_READ_FAILED (ECODE_EMDRV_NVM3_BASE | 0x00000012U) ///< Error in the read operation -#define ECODE_NVM3_ERR_INIT_WITH_FULL_NVM (ECODE_EMDRV_NVM3_BASE | 0x00000013U) ///< The module was opened with a full NVM -#define ECODE_NVM3_ERR_RESIZE_PARAMETER (ECODE_EMDRV_NVM3_BASE | 0x00000014U) ///< Illegal parameter -#define ECODE_NVM3_ERR_RESIZE_NOT_ENOUGH_SPACE (ECODE_EMDRV_NVM3_BASE | 0x00000015U) ///< Not enough NVM to complete resize -#define ECODE_NVM3_ERR_ERASE_COUNT_ERROR (ECODE_EMDRV_NVM3_BASE | 0x00000016U) ///< Erase counts are not valid -#define ECODE_NVM3_ERR_ADDRESS_RANGE (ECODE_EMDRV_NVM3_BASE | 0x00000017U) ///< Address and size is out of range of available NVM -#define ECODE_NVM3_ERR_NVM_ACCESS (ECODE_EMDRV_NVM3_BASE | 0x00000019U) ///< A NVM function call was failing -#define ECODE_NVM3_ERR_INT_WRITE_TO_NOT_ERASED (ECODE_EMDRV_NVM3_BASE | 0x00000020U) ///< Write to memory that is not erased -#define ECODE_NVM3_ERR_INT_ADDR_INVALID (ECODE_EMDRV_NVM3_BASE | 0x00000021U) ///< Internal error trying to access invalid memory -#define ECODE_NVM3_ERR_INT_KEY_MISMATCH (ECODE_EMDRV_NVM3_BASE | 0x00000022U) ///< Key validation failure -#define ECODE_NVM3_ERR_INT_SIZE_ERROR (ECODE_EMDRV_NVM3_BASE | 0x00000023U) ///< Internal size mismatch error -#define ECODE_NVM3_ERR_INT_EMULATOR (ECODE_EMDRV_NVM3_BASE | 0x00000024U) ///< Internal Emulator error -#define ECODE_NVM3_ERR_INT_TEST (ECODE_EMDRV_NVM3_BASE | 0x00000030U) ///< Internal Test error - -/***************************************************************************//** - * @brief Definitions of NVM3 constraints. - ******************************************************************************/ -#define NVM3_MIN_PAGE_SIZE 512U ///< The minimum page size supported -#define NVM3_MAX_OBJECT_SIZE_LOW_LIMIT 204U ///< The minimum value for the maximum object size -#define NVM3_MAX_OBJECT_SIZE_HIGH_LIMIT 4096U ///< The maximum value for the maximum object size -#define NVM3_MAX_OBJECT_SIZE_DEFAULT 1900U ///< The default value for the maximum object size - -#if !defined(NVM3_MAX_OBJECT_SIZE) -#define NVM3_MAX_OBJECT_SIZE NVM3_MAX_OBJECT_SIZE_DEFAULT ///< The maximum object size -#endif - -/***************************************************************************//** - * @brief NVM3 static data definition helper macro for applications using linker - * script placement of the NVM memory area. This macro exports the section 'name'_section - * to the linker. The user must place the section name in a linker script - * at an address aligned with the page size of the underlying memory system. The size of - * the NVM area must be a multiple of the page size. - * @n This macro also allocates the static NVM3 cache. - * @n Use this macro with @ref NVM3_DEFINE_SECTION_INIT_DATA() to create initialization - * data for @ref nvm3_open(). See @ref nvm3_example section for usage examples. - ******************************************************************************/ -#define NVM3_DEFINE_SECTION_STATIC_DATA(name, nvmSize, cacheSize) \ - static nvm3_CacheEntry_t name##_cache[cacheSize]; \ - static const uint8_t name##_nvm[nvmSize] \ - SL_ATTRIBUTE_SECTION(STRINGIZE(name##_section)) - -/***************************************************************************//** - * @brief NVM3 initialization data helper macro to be used with @ref - * NVM3_DEFINE_SECTION_STATIC_DATA(). The @p name parameter in both macros must - * match. - * @n Call @ref nvm3_open() after this macro to initialize NVM3. See @ref - * nvm3_example section for code examples. - ******************************************************************************/ -#define NVM3_DEFINE_SECTION_INIT_DATA(name, flashHandle) \ - nvm3_Init_t name = \ - { \ - (nvm3_HalPtr_t)name##_nvm, \ - sizeof(name##_nvm), \ - name##_cache, \ - sizeof(name##_cache) / sizeof(nvm3_CacheEntry_t), \ - NVM3_MAX_OBJECT_SIZE, \ - 0, \ - flashHandle, \ - } - -#define NVM3_KEY_INVALID 0xFFFFFFFFU ///< Invalid key identifier -#define NVM3_KEY_SIZE 20U ///< Unique object key identifier size in number of bits -#define NVM3_KEY_MASK ((1U << NVM3_KEY_SIZE) - 1U) ///< Unique object key identifier mask -#define NVM3_KEY_MIN 0U ///< Minimum object key value -#define NVM3_KEY_MAX NVM3_KEY_MASK ///< Maximum object key value - -#define NVM3_OBJECTTYPE_DATA 0U ///< The object is data -#define NVM3_OBJECTTYPE_COUNTER 1U ///< The object is a counter - -/// @brief The data type for object keys. Only the 20 least significant bits are used. -typedef uint32_t nvm3_ObjectKey_t; - -/// @brief The datatype for each cache entry. The cache must be an array of these. -typedef struct nvm3_CacheEntry { - nvm3_ObjectKey_t key; ///< key - void *ptr; ///< pointer -} nvm3_CacheEntry_t; - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -typedef struct nvm3_Cache { - nvm3_CacheEntry_t *entryPtr; - size_t entryCount; - bool overflow; -} nvm3_Cache_t; - -typedef struct nvm3_ObjFragDetail { - void *adr; - uint16_t len; - uint8_t typ; -} nvm3_ObjFragDetail_t; - -typedef struct { - nvm3_HalPtr_t nvmAdr; // NVM address - size_t nvmSize; // NVM size - nvm3_Cache_t cache; // Cache management data - size_t maxObjectSize; // The maximum object size in bytes - size_t repackHeadroom; // The size difference between the user and forced repacks - size_t totalNvmPageCnt; // The total number of NVM pages - size_t validNvmPageCnt; // The number of valid NVM pages - size_t fifoFirstIdx; // FIFO bottom page - void *fifoFirstObj; // The first object location - void *fifoNextObj; // The next free object location - size_t unusedNvmSize; // The size of the unused NVM - bool hasBeenOpened; // Open status - size_t minUnused; // The minimum value of the unusedNvmSize - const nvm3_HalHandle_t *halHandle; // HAL handle - nvm3_HalInfo_t halInfo; // HAL information -} nvm3_Handle_t; - -/// @endcond - -/// @brief NVM3 initialization data. -typedef struct { - nvm3_HalPtr_t nvmAdr; ///< NVM memory area base address - size_t nvmSize; ///< NVM memory area size in bytes - nvm3_CacheEntry_t *cachePtr; ///< A pointer to cache - size_t cacheEntryCount; ///< The size of the cache in number of elements - size_t maxObjectSize; ///< The maximum object size in bytes - size_t repackHeadroom; ///< The size difference between the user and forced repacks - const nvm3_HalHandle_t *halHandle; ///< HAL handle -} nvm3_Init_t; - -/***************************************************************************//** - * @brief - * Open an NVM3 driver instance, which is represented by a handle - * keeping information about the state. A successful open will initialize - * the handle and the cache with information about the objects already in the - * NVM-memory. - * Several NVM3 instances using different handles must NOT overlap NVM-memory. - * To change some of the parameters, - * first call @ref nvm3_close and then @ref nvm3_open. - * @note The driver handle must be initialized to zero before it is used the - * first time. The @ref nvm3_open can be called repeatedly with the same handle - * and initialization data. In that case, the next calls will be regarded as a - * "no operation" and the function will return the same status as the previous - * call. - * - * @param[out] h - * A pointer to an NVM3 driver handle. - * - * @param[in] i - * A pointer to NVM3 driver initialization data. - * - * @return - * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_open(nvm3_Handle_t *h, const nvm3_Init_t *i); - -/***************************************************************************//** - * @brief - * Close the NVM3 driver instance. - * - * @param[in] h - * A pointer to the NVM3 driver handle. - * - * @return - * @ref ECODE_NVM3_OK is always returned. - ******************************************************************************/ -Ecode_t nvm3_close(nvm3_Handle_t *h); - -/***************************************************************************//** - * @brief - * Write the object value identified with the key to NVM. - * If the data object exists with the same length, its old content is compared - * with the new and only if the new content is different from the old it will - * be written. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[in] value - * A pointer to the object data to write. - * - * @param[in] len - * The size of the object data in number of bytes. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_writeData(nvm3_Handle_t *h, nvm3_ObjectKey_t key, const void *value, size_t len); - -/***************************************************************************//** - * @brief - * Read the object data identified with a given key from NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[out] value - * A pointer to the application data buffer. The read function will copy - * data to this location. For best performance, the buffer should be word-aligned. - * - * @param[in] len - * The maximum object size in number of bytes. The @ref nvm3_getObjectInfo() function - * can be used to find the actual size. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_readData(nvm3_Handle_t *h, nvm3_ObjectKey_t key, void *value, size_t len); - -/***************************************************************************//** - * @brief - * Read parts of the object data identified with a given key from NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[out] value - * A pointer to the application data buffer. The read function will copy - * data to this location. For best performance, the buffer should be word-aligned. - * - * @param[in] ofs - * The offset where data shall be read from. - * - * @param[in] len - * The number of bytes to read. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_readPartialData(nvm3_Handle_t* h, nvm3_ObjectKey_t key, void* value, size_t ofs, size_t len); - -/***************************************************************************//** - * @brief - * Find the type and size of an object in NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[out] type - * A pointer to the location where NVM3 shall write the object type. The type can - * be either @ref NVM3_OBJECTTYPE_DATA or @ref NVM3_OBJECTTYPE_COUNTER. - * - * @param[out] len - * A pointer to the location where NVM3 writes the object size. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_getObjectInfo(nvm3_Handle_t *h, nvm3_ObjectKey_t key, - uint32_t *type, size_t *len); - -/***************************************************************************//** - * @brief - * Create a list of object keys for valid objects in NVM. - * - * @note - * The function @ref nvm3_countObjects() is also provided to count the - * number of valid objects. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[out] keyListPtr - * A pointer to a buffer for the key list. - * - * @param[in] keyListSize - * The number of elements in the key list buffer. If the keyListSize = 0, - * the @p keyListPtr can be NULL and the function will return the total - * number of objects. - * - * @param[in] keyMin - * The lower search key. Set to @ref NVM3_KEY_MIN to match all keys. - * - * @param[in] keyMax - * The upper search key. Set to @ref NVM3_KEY_MAX to match all keys. - * - * @return - * The number of keys written to the key list. This value is less than or equal - * to @p keyListSize. If the @p keyListSize = 0, the function will return the - * total number of objects matching the key Min - Max pattern. - ******************************************************************************/ -size_t nvm3_enumObjects(nvm3_Handle_t *h, - nvm3_ObjectKey_t *keyListPtr, size_t keyListSize, - nvm3_ObjectKey_t keyMin, nvm3_ObjectKey_t keyMax); - -/***************************************************************************//** - * @brief - * Create a list of object keys for deleted objects in NVM. - * - * @note - * The function @ref nvm3_countDeletedObjects() is also provided to count the - * number of deleted objects. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[out] keyListPtr - * A pointer to a buffer for the key list. - * - * @param[in] keyListSize - * The number of elements in the key list buffer. If the keyListSize = 0, - * the @p keyListPtr can be NULL and the function will return the total - * number of objects. - * - * @param[in] keyMin - * The lower search key. Set to @ref NVM3_KEY_MIN to match all keys. - * - * @param[in] keyMax - * The upper search key. Set to @ref NVM3_KEY_MAX to match all keys. - * - * @return - * The number of keys written to the key list. This value is less than or equal - * to @p keyListSize. If the @p keyListSize = 0, the function will return the - * total number of objects matching the key Min - Max pattern. - ******************************************************************************/ -size_t nvm3_enumDeletedObjects(nvm3_Handle_t *h, - nvm3_ObjectKey_t *keyListPtr, size_t keyListSize, - nvm3_ObjectKey_t keyMin, nvm3_ObjectKey_t keyMax); - -/***************************************************************************//** - * @brief - * Delete an object from NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_deleteObject(nvm3_Handle_t *h, nvm3_ObjectKey_t key); - -/***************************************************************************//** - * @brief - * Store a counter in NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[in] value - * The counter value to write. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_writeCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t value); - -/***************************************************************************//** - * @brief - * Read a counter value from NVM. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[out] value - * A pointer to the counter location. The read function will copy - * the counter value to this location. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_readCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t *value); - -/***************************************************************************//** - * @brief - * Increment a counter object value by 1 and read out optionally. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] key - * A 20-bit object identifier. - * - * @param[out] newValue - * A pointer to the counter readout location. The counter is incremented before the value - * is written to this location. Set this value to NULL to ignore readout. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_incrementCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t *newValue); - -/***************************************************************************//** - * @brief - * Delete all objects in NVM. - * - * @note - * Users don't need to call this function to get NVM3 into an - * initial valid state. - * - * @warning - * The execution time depends on the configured NVM size and may therefore be - * significant. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_eraseAll(nvm3_Handle_t *h); - -/***************************************************************************//** - * @brief - * Get the number of page erases of the most erased page in the NVM area since - * the first initialization. - * - * @note - * Except for pages marked as bad, pages will have an erase count equal to the - * most erased or one less because of the wear leveling algorithm. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] eraseCnt - * A pointer to the location where the NVM3 shall place the page - * erasure counter value. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_getEraseCount(nvm3_Handle_t *h, uint32_t *eraseCnt); - -/***************************************************************************//** - * @brief - * Set the page erase count. - * Normally, the application should not be concerned with the erase count value. - * If NVM3 is substituting a previous solution, it is possible to transfer - * the erase count to NVM3 when initializing the NVM for the first time. - * The erase count must be set before the @ref nvm3_open is called and will - * only take effect if the NVM is completely erased or contains unknown - * data to NVM3. In that case, all pages will be initialized with the supplied - * erase count. After @ref nvm3_open is called, the value will be consumed - * and will have no effect on further calls to @ref nvm3_open. - * - * @param[in] eraseCnt - * The erase count. - ******************************************************************************/ -void nvm3_setEraseCount(uint32_t eraseCnt); - -/***************************************************************************//** - * @brief - * Execute a repack operation. NVM3 will copy data or erase pages when repacking - * is needed. Calling @ref nvm3_repack() may block access to the non-volatile - * memory for up to one page erasure time plus an small execution overhead. - * The exact worst-case timing characteristics can be found in the data sheet for the - * part. - * - * @note - * Calling @ref nvm3_repack() is not mandatory because the functions that - * write data to NVM will trigger a repack if needed. Because a - * repack operation may be time consuming, the application may want to be - * in control of when repacking occurs by calling this function. - * - * More information about the repack operation can be found in the - * @ref nvm3_repack section. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_repack(nvm3_Handle_t *h); - -/***************************************************************************//** - * @brief - * Check the internal status of NVM3 and return true if a repack - * operation is required. The application must call @ref nvm3_repack() to - * perform the actual repack operation. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @return - * true if repacking is needed, false if repacking is not needed. - ******************************************************************************/ -bool nvm3_repackNeeded(nvm3_Handle_t *h); - -/***************************************************************************//** - * @brief - * Resize the NVM area used by an open NVM3 instance. - * The area can be resized by changing the start or end address either up - * or down in memory. Because the input parameters to NVM3 are start address - * and size, users should be cautious. Either move the start address up or - * down in memory and adjust the size accordingly to keep the end address, - * or keep the address and change the size only. - * It is not possible to resize the area by doing changes in both ends of the - * NVM address range at the same time. - * If the resize operation returns @ref ECODE_NVM3_OK, the instance is still - * open and can be used to access objects in the resized NVM. - * If the resize operation fails, the instance will still be open but with - * unchanged size. - * - * @note - * It is possible to decrease the NVM area to a new size that is not capable - * of keeping the already stored objects. The result is loss of data. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @param[in] newAddr - * The start address of the NVM after resize. - * - * @param[in] newSize - * The size of the NVM after resize. - * - * @return - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -Ecode_t nvm3_resize(nvm3_Handle_t *h, nvm3_HalPtr_t newAddr, size_t newSize); - -/***************************************************************************//** - * @brief - * Count valid objects. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @return - * The number of valid objects. - ******************************************************************************/ -__STATIC_INLINE size_t nvm3_countObjects(nvm3_Handle_t *h) -{ - return nvm3_enumObjects(h, NULL, 0, NVM3_KEY_MIN, NVM3_KEY_MAX); -} - -/***************************************************************************//** - * @brief - * Count deleted objects. - * - * @param[in] h - * A pointer to an NVM3 driver handle. - * - * @return - * The number of deleted objects. - ******************************************************************************/ -__STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) -{ - return nvm3_enumDeletedObjects(h, NULL, 0, NVM3_KEY_MIN, NVM3_KEY_MAX); -} - -/** @} (end addtogroup nvm3) */ - -#ifdef __cplusplus -} -#endif - -#include "nvm3_default.h" - -/* *INDENT-OFF* */ -/************ THIS SECTION IS FOR DOCUMENTATION ONLY !**********************//** - * @addtogroup nvm3 NVM3 - NVM Data Manager - * @brief NVM3 Non-Volatile Memory Data Management driver - * @{ - - # Introduction {#nvm3_intro} - The NVM3 driver provides a way for an application to safely store and - retrieve variable-size objects in a page-based non-volatile memory (NVM). - Objects are identified with 20-bit object identifiers denoted as keys. - - The driver is designed to use pages in a sequential order to provide equal - usage and wear. The driver is resilient to power loss or reset events, - ensuring that objects retrieved from the driver are in a valid state. A - valid object will always be the last successfully stored object. NVM3 can - detect NVM defects and mark pages as unusable. NVM3 will continue to operate - on good pages after defect pages are detected. - - # Objects {#nvm3_objects} - An NVM3 object is data that can be stored in NVM. The object - is handled as an array of bytes up to @ref NVM3_MAX_OBJECT_SIZE in size. - NVM3 can handle two types of objects. - -# Regular data objects. Data objects can store information of - any size up to maximum @ref NVM3_MAX_OBJECT_SIZE bytes. - -# 32-bit counter objects. Counter objects can store 32-bit counters that are - accessed with a separate set of API functions. The counter object is designed - to be compact while minimizing memory wear in applications that require - frequent persistent counter increments. - - See @ref nvm3_api for more details on the API. - - # Repacking {#nvm3_repack} - As the NVM fills up, it reaches a point where it can no longer store - additional objects, and a repacking operation is required to release - out-of-date objects to free up NVM. Because both writing data and erasing - pages take a long time, - the NVM3 driver does not trigger the process by itself unless free memory - reaches a critical low level. As an alternative, the application can trigger - the repacking process by calling the @ref nvm3_repack() function. - During the call, NVM3 will either move data to a new page or erase pages - that can be reused. At most, the call will block for a period equal to a page - erasure time or the time to write the largest size object (whatever is largest) - plus a small execution overhead. Page erasure and flash write timing for the - EFM32 or EFR32 parts can be found in the datasheet. - - NVM3 uses two thresholds for repacking: - -# Forced threshold. This is the threshold used to force automatic repacking - when free memory reaches a critical low level. - -# User threshold. This is the threshold used by @ref nvm3_repackNeeded(). - @ref nvm3_repack() will not perform repacking unless free memory is below - this threshold. - - The user can define the user threshold by entering a value in the repackHeadroom - member of the @ref nvm3_Init_t structure used by the @ref nvm3_open() function. - The repackHeadroom value defines the difference between the user and forced - threshold. The forced threshold is the minimum low memory threshold defined - by the page size and maximum object size and can't be changed by the user. - The default value for the repack headroom is 0, meaning that the forced and - user thresholds are equal. - - An NVM3 function that deletes or modifies data or counter object will trigger - an automatic repack operation when free memory is below the forced threshold. - The check is done before the object is modified, not after. - - The application can use @ref nvm3_repackNeeded() to determine if repacking - is needed. To initiate repacks, call @ref nvm3_repack(). Note that - this function will perform repacks only if they are needed. - - @note The repack threshold can be changed to prevent multiple modifications - of objects between user called repacks from causing forced repacks. Note - that "high" values of the repack headroom may cause - increased NVM wear from increased number of repacks. - - See @ref nvm3_timing section for more details on repack timing. - - # Caching {#nvm3_cache} - NVM3 includes an object location lookup cache to speed up object access, as - searching through the entire NVM3 contents for an object could otherwise - be slow. It is important to note that this cache only stores the location - of the object and not the object data itself. To ensure that cache can hold all necessary - information, it must be configured to a size equivalent to or larger than the - number of objects stored in NVM, including those deleted, as long as they are - not discarded by the repack function. If the cache is available, - the driver will first look in the cache to find the position of the object in NVM. - If the object position is not found in the cache, the object position will be - found by searching the NVM. The search will start at the last stored object - and search all the way to the oldest object. If the object is found, the cache - is updated accordingly. - - The application must allocate and support data for the cache. - See the @ref nvm3_open function for more details. The size of each cache - element is one uint32_t and one pointer giving a total of 8 bytes (2 words) - pr. entry for EFM32 and EFR32 devices. - - @note The cache is fully initialized by @ref nvm3_open() and automatically - updated by any subsequent write, read, or delete function call. - - # Global Data (variables) {#nvm3_data} - The NVM3 library uses global variables to store intermediate data - during open, read, write, increment, and delete calls. Because the actual - memory configuration is not defined at the time the NVM3 library is built - but rather at the time the user application is built, the size of data - structures must be determined by the application configuration. - Also, the application must set the value of the @ref nvm3_maxFragmentCount - at run-time before any NVM3 functions are called. - - NVM3 does not support overlapped calls. If there is any chance that the - application can issue overlapped calls, the NVM3 locking mechanism must be - present and protected from that. - - @note If the application uses more than one NVM3 instance, the variables - will be shared between the instances. Be sure to allocate data that have a - size that is large enough for the largest usage. - - # Stack Usage {#nvm3_stack} - NVM3 library function calls are nested several levels deep. The stack - usage has been measured on some EFM32, and EFR32 targets with library builds - for IAR and ARM GCC. The maximum stack usage measured was 420 bytes for - IAR, and 472 bytes for ARM GCC builds. The unit test used to validate the - stack usage has a 10% margin and uses a stack limit of 462 bytes for IAR - and 520 for ARM GCC. - Note that the actual stack usage is a little different on the Cortex - M0 Plus, M3, M4, and M33 versions of the library. - - # The API {#nvm3_api} - The NVM3 API is defined in the nvm3.h file. The application code - must include the nvm3.h header file to get access to all definitions, - datatypes, and function prototypes defined by NVM3. - - This section contains brief descriptions of NVM3 functions. For - more information about parameters and return values, see the Function - documentation section. Most functions return an @ref Ecode_t that has the - value @ref ECODE_NVM3_OK on success, or see nvm3.h for other values. - - @ref nvm3_open() and @ref nvm3_close(). - @n These functions open and close an NVM3 instance. @ref nvm3_open() takes a handle - of type nvm3_Handle_t and initialization data of type @ref nvm3_Init_t. - The helper macro pair @ref NVM3_DEFINE_SECTION_STATIC_DATA() and - @ref NVM3_DEFINE_SECTION_INIT_DATA() are provided to simplify initialization - data definition. For usage examples, see the @ref nvm3_example section. - - @ref nvm3_getObjectInfo(), @ref nvm3_enumObjects(), @ref nvm3_deleteObject() - and nvm3_countObjects() - @n These functions work on all objects. @ref nvm3_enumObjects() - gets a list of keys to valid objects in the NVM. The search can also - be constrained by the function parameters. - @ref nvm3_countObjects() can be useful at startup to distinguish between a - first startup without any valid objects present and later reboots with valid - objects persistently stored in NVM. - - @ref nvm3_writeData() and @ref nvm3_readData() - @n Write and read data objects. - - @ref nvm3_writeCounter(), @ref nvm3_readCounter() and @ref nvm3_incrementCounter() - @n Write, read, and increment 32-bit counter objects. - - @ref nvm3_eraseAll() - @n Erase all objects in NVM. - - @ref nvm3_getEraseCount() - @n Return the erasure count for the most erased page in NVM. - - @ref nvm3_repack() and @ref nvm3_repackNeeded() - @n Manage NVM3 repacking operations. - - @ref nvm3_resize() - @n Resize the NVM area used by an open NVM3 instance. - - # API Locking and Interrupt handling {#nvm3_locking} - Common for all NVM3 API calls is that they are not re-entrant. By default, - all functions are protected with protection functions that disable interrupts. - - @note The default NVM3 protection functions can be substituted by the - application if other synchronization functions are available and disabling - interrupts for extended periods is not desired. - - If the application does all the nvm3-calls from the same thread and guarantees - no overlapping calls, the lock functions don't have to do anything. - - # Memory Placement {#nvm3_memory_placement} - The application is responsible for placing the NVM area correctly. The minimum - requirements for memory placement are as follows: - -# NVM area start address must be aligned with a page of the underlying - memory system. - -# NVM area size must be a multiple of the page size. - - The minimum required NVM size is dependent on both the NVM page size and the - NVM3_MAX_OBJECT_SIZE value. For a device with 2 kB page size and typical - values for NVM3_MAX_OBJECT_SIZE, the following is the minimum required - number of pages: - - For NVM3_MAX_OBJECT_SIZE=208: 3 pages - - For NVM3_MAX_OBJECT_SIZE=1900: 4 pages - - For NVM3_MAX_OBJECT_SIZE=4096: 5 pages - - @ref NVM3_DEFINE_SECTION_STATIC_DATA() and @ref NVM3_DEFINE_SECTION_INIT_DATA() - macros are provided to support the creation of the NVM area and initialization - data. - A linker section called 'name'_section is defined by @ref NVM3_DEFINE_SECTION_STATIC_DATA(). - The NVM area is placed within the linker section. The application linker script - must place the section according to the requirements above. An error is returned - by @ref nvm3_open() on alignment or size violation. - - @note When the start address and size of the data area are defined and - used by an application, make sure you use the same values at - every program startup and also reuse by new versions of the software after - an upgrade. If an application tries to open an instance with a start address - or size that does not match the previous use, it can result in permanent data loss - and failure. - - # Configuration Options {#nvm3_configuration} - There are no compile-time configuration options for NVM3. All configuration - parameters are contained in @ref nvm3_Init_t. - - @note The @ref nvm3_data must however be configured for correct - size and have correct values for NVM3 to behave correctly. - - # Bad NVM Page Handling {#nvm3_bad_page_handling} - NVM3 has been designed to detect page erase and write errors during - normal operation and mark failing pages as BAD. If a write operation - fails, all objects that have been written to the page prior to the write - error are copied to the next free page before the page is marked as BAD and - the write operation resumes. If the recovery operation is successful, the - operation is regarded as complete, and the function will return @ref - ECODE_NVM3_OK status. - - @note Erase and write errors may not be detected by NVM3 if the device is - used until End-of-Life (EOL), where the failure mode can be that the NVM content is - changing during a power cycle. - - # Error Handling {#nvm3_error_handling} - The NVM3 error handling involves most functions - returning an error code. The @ref nvm3_countObjects is - different because it returns the actual number of objects - found. - - The behavior and return values for most functions, such as @ref - nvm3_readData, @ref nvm3_writeData, and so on should be self explanatory, - while the @ref nvm3_open is slightly different. @ref nvm3_open will always try - to recover from the previous state and continue without an error, if possible. - In other words, if a valid NVM3 instance is - established, @ref nvm3_open will recover from brownouts and power cycles at - any time in any operation and bring the system to a valid state where all - pages and objects are in a known state and return success whenever possible. - From this state, normal operation can resume. If @ref nvm3_open returns an - error, it's an indication of either a design or coding error - or that many of the NVM pages have been marked as BAD, leaving insufficient - space in the NVM to progress. Operation may not resume if @ref nvm3_open - returns an error. - - @note Because the @ref nvm3_open may need to do recovery operations, - the execution time will occasionally vary. - - # Storing Objects in Internal Flash {#nvm3_support_internal_flash} - NVM3 has support for writing and reading objects in internal, i.e., memory-mapped - Flash memory through the nvm3_hal_flash.c "driver". nvm3_hal_flash.c - is using EMLIB functions to write and erase data while using regular - memory functions to read data from Flash. - - @n The "driver" for internal Flash is selected by setting the halHandle in - the nvm3_open initialization structure to point to nvm3_halFlashHandle. - - # NVM3 Libraries {#nvm3_libraries} - The NVM3 comes with pre-compiled libraries for Cortex M0, M3, M4, and M33 - compiled with either Arm GCC or IAR toolchains. - - # Storage Capacity {#nvm3_capacity} - Basic storage is defined as the size of on instance of all objects, including - any overhead stored with the data. For NVM3 the maximum amount of data you - can store is dependent on the number of flash pages used for storage and the - max object size used for NVM3. The following table shows the maximum allowed - basic storage for a varying number of 2 kB or 8 kB flash pages and the minimum - (208 bytes), default (254 bytes), high (1900 bytes) and maximum (4096 bytes) - max object size. Note that this is a theoretical limit, and if the basic storage - is at this limit, no space is left for wear-levelling, and page erases will be - forced for every object written. The NVM3 instance should therefore be configured - with enough flash pages to put the maximum allowed basic storage significantly - higher than the actual basic storage. - - ## Max Allowed Basic Storage with 2 kB page size - - | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | - |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| - | | | Max object size = 208 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | - | 3 | 6144 | 1596 | 1504 | 0 | 0 | - | 4 | 8192 | 3624 | 3532 | 240 | 0 | - | 5 | 10240 | 5652 | 5560 | 2268 | 0 | - | 6 | 12288 | 7680 | 7588 | 4296 | 0 | - | 7 | 14336 | 9708 | 9616 | 6324 | 0 | - | 8 | 16384 | 11736 | 11644 | 8352 | 0 | - | 9 | 18432 | 13764 | 13672 | 10380 | 1900 | - | 10 | 20480 | 15792 | 15700 | 12408 | 3928 | - | 11 | 22528 | 17820 | 17728 | 14436 | 5956 | - | 12 | 24576 | 19848 | 19756 | 16464 | 7984 | - | 13 | 26624 | 21876 | 21784 | 18492 | 10012 | - | 14 | 28672 | 23904 | 23812 | 20520 | 12040 | - | 15 | 30720 | 25932 | 25840 | 22548 | 14068 | - | 16 | 32768 | 27960 | 27868 | 24576 | 16096 | - | 17 | 34816 | 29988 | 29896 | 26604 | 18124 | - | 18 | 36864 | 32016 | 31924 | 28632 | 20152 | - - ## Max Allowed Basic Storage with 8 kB page size - | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | - |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| - | | | Max object size = 208 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | - | 3 | 24516 | 7740 | 7648 | 4356 | 0 | - | 4 | 32688 | 15912 | 15820 | 12528 | 8136 | - | 5 | 40860 | 24084 | 23992 | 20700 | 16308 | - | 6 | 49032 | 32256 | 32164 | 28872 | 24480 | - - # Default Instance {#nvm3_default} - Several NVM3 instances can be created on a device and live independently of each other, - but to save memory, it is usually desirable to use only one NVM3 instance as each - instance adds some overhead. For this reason, a default instance exists that is used - by all Silicon Labs wireless stacks. The API to initialize the default instance and - the handles to use with the regular NVM3 API are described in @ref nvm3default. - - # NVM3 in Simplicity Commander {#nvm3_commander} - Simplicity Commander is a single, all-purpose tool to be used in a production environment. - It is invoked using a simple Command Line Interface (CLI) that can also be scripted. - Simplicity Commander supports reading out the NVM3 data area from a device and parsing - the NVM3 data to extract stored values. This can be useful in a debugging scenario - where you may need to find out the stored state of an application that has been running - for some time. - - For more information about using the Simplicity Commander with NVM3, see - UG162: Simplicity Commander Reference Guide. - - # Execution Timing {#nvm3_timing} - There are several factors that affect the execution time for NVM3 calls that - can update the NVM, described below. - - The primary factor when doing updates is that data must be written to flash. - Writing to flash is relatively slow, and timing information for the particular - device is available in the datasheet and can be used to calculate the - approximately minimum execution time. Note that NVM3 will, in addition to the - user data, write object headers, and the software will add some - overhead. The relative overhead will be larger for smaller compared to larger - objects. - - When updating the flash store, repacking must be done from time to - time. See the @ref nvm3_repack section for more details about why - repacking is needed and how it works. - - To minimize the time when repacks are executed, there are a few configurations - that affect how NVM3 works. The most important configurations are listed below: - -# The repackHeadroom parameter in the @ref nvm3_Init_t structure can be used - to set the number of bytes that can be written before a forced repack is - triggered. To make this work, the @ref nvm3_repack() function must be called - until the @ref nvm3_repackNeeded() returns false before the actual write. - -# Use as small objects as possible and define the NVM3_MAX_OBJECT_SIZE - accordingly. Writing and repacking large objects is time-consuming. Limiting - the maximum object size will limit the time spent in both write and repack - functions. - - When triggered, the repack function will either copy data or erase a page. - To limit the time spent when copying, the repack function will return when - the NVM3_MAX_OBJECT_SIZE number of bytes have been copied. The copy operation - will resume on the next call to repack, and the application may have to call - the repack function several times to complete a full repack operation. - - @note Performing the @ref nvm3_repack()/@ref nvm3_repackNeeded() loop is - highly recommended before any timing-sensitive procedure. - - # Examples {#nvm3_example} - - Example 1 shows initialization, usage of data objects, and repacking. - - @include nvm3_example_1.c - - Example 2 shows initialization and usage of counter objects. The - counter object uses a compact way of storing a 32-bit counter value while minimizing - NVM wear. - - @include nvm3_example_2.c - - * @} end group nvm3 ****************************************************/ - -#endif /* NVM3_GENERIC_H */ +/***************************************************************************//** + * @file + * @brief NVM3 API definition (Generic). + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_GENERIC_H +#define NVM3_GENERIC_H + +#include +#include +#include + +#include "nvm3_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +#define ECODE_NVM3_OK (ECODE_OK) ///< Success return value +#define ECODE_NVM3_ERR_ALIGNMENT_INVALID (ECODE_EMDRV_NVM3_BASE | 0x00000001U) ///< Invalid data alignment +#define ECODE_NVM3_ERR_SIZE_TOO_SMALL (ECODE_EMDRV_NVM3_BASE | 0x00000002U) ///< Not enough NVM memory specified +#define ECODE_NVM3_ERR_NO_VALID_PAGES (ECODE_EMDRV_NVM3_BASE | 0x00000003U) ///< Initialization aborted, no valid page found +#define ECODE_NVM3_ERR_PAGE_SIZE_NOT_SUPPORTED (ECODE_EMDRV_NVM3_BASE | 0x00000004U) ///< The page size is not supported +#define ECODE_NVM3_ERR_OBJECT_SIZE_NOT_SUPPORTED (ECODE_EMDRV_NVM3_BASE | 0x00000005U) ///< The object size is not supported +#define ECODE_NVM3_ERR_STORAGE_FULL (ECODE_EMDRV_NVM3_BASE | 0x00000006U) ///< No more NVM space available +#define ECODE_NVM3_ERR_NOT_OPENED (ECODE_EMDRV_NVM3_BASE | 0x00000007U) ///< The module has not been successfully opened +#define ECODE_NVM3_ERR_OPENED_WITH_OTHER_PARAMETERS (ECODE_EMDRV_NVM3_BASE | 0x00000008U) ///< The module has already been opened with other parameters +#define ECODE_NVM3_ERR_PARAMETER (ECODE_EMDRV_NVM3_BASE | 0x00000009U) ///< Illegal parameter +#define ECODE_NVM3_ERR_KEY_INVALID (ECODE_EMDRV_NVM3_BASE | 0x0000000AU) ///< Invalid key value +#define ECODE_NVM3_ERR_KEY_NOT_FOUND (ECODE_EMDRV_NVM3_BASE | 0x0000000BU) ///< Key not found +#define ECODE_NVM3_ERR_OBJECT_IS_NOT_DATA (ECODE_EMDRV_NVM3_BASE | 0x0000000CU) ///< Trying to access a data object which is currently a counter object +#define ECODE_NVM3_ERR_OBJECT_IS_NOT_A_COUNTER (ECODE_EMDRV_NVM3_BASE | 0x0000000DU) ///< Trying to access a counter object which is currently a data object +#define ECODE_NVM3_ERR_ERASE_FAILED (ECODE_EMDRV_NVM3_BASE | 0x0000000EU) ///< Erase failed +#define ECODE_NVM3_ERR_WRITE_DATA_SIZE (ECODE_EMDRV_NVM3_BASE | 0x0000000FU) ///< The object is too large +#define ECODE_NVM3_ERR_WRITE_FAILED (ECODE_EMDRV_NVM3_BASE | 0x00000010U) ///< Error in the write operation +#define ECODE_NVM3_ERR_READ_DATA_SIZE (ECODE_EMDRV_NVM3_BASE | 0x00000011U) ///< Trying to read with a length different from actual object size +#define ECODE_NVM3_ERR_READ_FAILED (ECODE_EMDRV_NVM3_BASE | 0x00000012U) ///< Error in the read operation +#define ECODE_NVM3_ERR_INIT_WITH_FULL_NVM (ECODE_EMDRV_NVM3_BASE | 0x00000013U) ///< The module was opened with a full NVM +#define ECODE_NVM3_ERR_RESIZE_PARAMETER (ECODE_EMDRV_NVM3_BASE | 0x00000014U) ///< Illegal parameter +#define ECODE_NVM3_ERR_RESIZE_NOT_ENOUGH_SPACE (ECODE_EMDRV_NVM3_BASE | 0x00000015U) ///< Not enough NVM to complete resize +#define ECODE_NVM3_ERR_ERASE_COUNT_ERROR (ECODE_EMDRV_NVM3_BASE | 0x00000016U) ///< Erase counts are not valid +#define ECODE_NVM3_ERR_ADDRESS_RANGE (ECODE_EMDRV_NVM3_BASE | 0x00000017U) ///< Address and size is out of range of available NVM +#define ECODE_NVM3_ERR_NVM_ACCESS (ECODE_EMDRV_NVM3_BASE | 0x00000019U) ///< A NVM function call was failing +#define ECODE_NVM3_ERR_INT_WRITE_TO_NOT_ERASED (ECODE_EMDRV_NVM3_BASE | 0x00000020U) ///< Write to memory that is not erased +#define ECODE_NVM3_ERR_INT_ADDR_INVALID (ECODE_EMDRV_NVM3_BASE | 0x00000021U) ///< Internal error trying to access invalid memory +#define ECODE_NVM3_ERR_INT_KEY_MISMATCH (ECODE_EMDRV_NVM3_BASE | 0x00000022U) ///< Key validation failure +#define ECODE_NVM3_ERR_INT_SIZE_ERROR (ECODE_EMDRV_NVM3_BASE | 0x00000023U) ///< Internal size mismatch error +#define ECODE_NVM3_ERR_INT_EMULATOR (ECODE_EMDRV_NVM3_BASE | 0x00000024U) ///< Internal Emulator error +#define ECODE_NVM3_ERR_INT_TEST (ECODE_EMDRV_NVM3_BASE | 0x00000030U) ///< Internal Test error + +/***************************************************************************//** + * @brief Definitions of NVM3 constraints. + ******************************************************************************/ +#define NVM3_MIN_PAGE_SIZE 512U ///< The minimum page size supported +#define NVM3_MAX_OBJECT_SIZE_LOW_LIMIT 204U ///< The minimum value for the maximum object size +#define NVM3_MAX_OBJECT_SIZE_HIGH_LIMIT 4096U ///< The maximum value for the maximum object size +#define NVM3_MAX_OBJECT_SIZE_DEFAULT 1900U ///< The default value for the maximum object size + +#if !defined(NVM3_MAX_OBJECT_SIZE) +#define NVM3_MAX_OBJECT_SIZE NVM3_MAX_OBJECT_SIZE_DEFAULT ///< The maximum object size +#endif + +/***************************************************************************//** + * @brief NVM3 static data definition helper macro for applications using linker + * script placement of the NVM memory area. This macro exports the section 'name'_section + * to the linker. The user must place the section name in a linker script + * at an address aligned with the page size of the underlying memory system. The size of + * the NVM area must be a multiple of the page size. + * @n This macro also allocates the static NVM3 cache. + * @n Use this macro with @ref NVM3_DEFINE_SECTION_INIT_DATA() to create initialization + * data for @ref nvm3_open(). See @ref nvm3_example section for usage examples. + ******************************************************************************/ +#define NVM3_DEFINE_SECTION_STATIC_DATA(name, nvmSize, cacheSize) \ + static nvm3_CacheEntry_t name##_cache[cacheSize]; \ + static const uint8_t name##_nvm[nvmSize] \ + SL_ATTRIBUTE_SECTION(STRINGIZE(name##_section)) + +/***************************************************************************//** + * @brief NVM3 initialization data helper macro to be used with @ref + * NVM3_DEFINE_SECTION_STATIC_DATA(). The @p name parameter in both macros must + * match. + * @n Call @ref nvm3_open() after this macro to initialize NVM3. See @ref + * nvm3_example section for code examples. + ******************************************************************************/ +#define NVM3_DEFINE_SECTION_INIT_DATA(name, flashHandle) \ + nvm3_Init_t name = \ + { \ + (nvm3_HalPtr_t)name##_nvm, \ + sizeof(name##_nvm), \ + name##_cache, \ + sizeof(name##_cache) / sizeof(nvm3_CacheEntry_t), \ + NVM3_MAX_OBJECT_SIZE, \ + 0, \ + flashHandle, \ + } + +#define NVM3_KEY_INVALID 0xFFFFFFFFU ///< Invalid key identifier +#define NVM3_KEY_SIZE 20U ///< Unique object key identifier size in number of bits +#define NVM3_KEY_MASK ((1U << NVM3_KEY_SIZE) - 1U) ///< Unique object key identifier mask +#define NVM3_KEY_MIN 0U ///< Minimum object key value +#define NVM3_KEY_MAX NVM3_KEY_MASK ///< Maximum object key value + +#define NVM3_OBJECTTYPE_DATA 0U ///< The object is data +#define NVM3_OBJECTTYPE_COUNTER 1U ///< The object is a counter + +/// @brief The data type for object keys. Only the 20 least significant bits are used. +typedef uint32_t nvm3_ObjectKey_t; + +/// @brief The datatype for each cache entry. The cache must be an array of these. +typedef struct nvm3_CacheEntry { + nvm3_ObjectKey_t key; ///< key + void *ptr; ///< pointer +} nvm3_CacheEntry_t; + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +typedef struct nvm3_Cache { + nvm3_CacheEntry_t *entryPtr; + size_t entryCount; + bool overflow; +} nvm3_Cache_t; + +typedef struct nvm3_ObjFragDetail { + void *adr; + uint16_t len; + uint8_t typ; +} nvm3_ObjFragDetail_t; + +typedef struct { + nvm3_HalPtr_t nvmAdr; // NVM address + size_t nvmSize; // NVM size + nvm3_Cache_t cache; // Cache management data + size_t maxObjectSize; // The maximum object size in bytes + size_t repackHeadroom; // The size difference between the user and forced repacks + size_t totalNvmPageCnt; // The total number of NVM pages + size_t validNvmPageCnt; // The number of valid NVM pages + size_t fifoFirstIdx; // FIFO bottom page + void *fifoFirstObj; // The first object location + void *fifoNextObj; // The next free object location + size_t unusedNvmSize; // The size of the unused NVM + bool hasBeenOpened; // Open status + size_t minUnused; // The minimum value of the unusedNvmSize + const nvm3_HalHandle_t *halHandle; // HAL handle + nvm3_HalInfo_t halInfo; // HAL information +} nvm3_Handle_t; + +/// @endcond + +/// @brief NVM3 initialization data. +typedef struct { + nvm3_HalPtr_t nvmAdr; ///< NVM memory area base address + size_t nvmSize; ///< NVM memory area size in bytes + nvm3_CacheEntry_t *cachePtr; ///< A pointer to cache + size_t cacheEntryCount; ///< The size of the cache in number of elements + size_t maxObjectSize; ///< The maximum object size in bytes + size_t repackHeadroom; ///< The size difference between the user and forced repacks + const nvm3_HalHandle_t *halHandle; ///< HAL handle +} nvm3_Init_t; + +/***************************************************************************//** + * @brief + * Open an NVM3 driver instance, which is represented by a handle + * keeping information about the state. A successful open will initialize + * the handle and the cache with information about the objects already in the + * NVM-memory. + * Several NVM3 instances using different handles must NOT overlap NVM-memory. + * To change some of the parameters, + * first call @ref nvm3_close and then @ref nvm3_open. + * @note The driver handle must be initialized to zero before it is used the + * first time. The @ref nvm3_open can be called repeatedly with the same handle + * and initialization data. In that case, the next calls will be regarded as a + * "no operation" and the function will return the same status as the previous + * call. + * + * @param[out] h + * A pointer to an NVM3 driver handle. + * + * @param[in] i + * A pointer to NVM3 driver initialization data. + * + * @return + * @ref ECODE_NVM3_OK on success and a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_open(nvm3_Handle_t *h, const nvm3_Init_t *i); + +/***************************************************************************//** + * @brief + * Close the NVM3 driver instance. + * + * @param[in] h + * A pointer to the NVM3 driver handle. + * + * @return + * @ref ECODE_NVM3_OK is always returned. + ******************************************************************************/ +Ecode_t nvm3_close(nvm3_Handle_t *h); + +/***************************************************************************//** + * @brief + * Write the object value identified with the key to NVM. + * If the data object exists with the same length, its old content is compared + * with the new and only if the new content is different from the old it will + * be written. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[in] value + * A pointer to the object data to write. + * + * @param[in] len + * The size of the object data in number of bytes. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_writeData(nvm3_Handle_t *h, nvm3_ObjectKey_t key, const void *value, size_t len); + +/***************************************************************************//** + * @brief + * Read the object data identified with a given key from NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[out] value + * A pointer to the application data buffer. The read function will copy + * data to this location. For best performance, the buffer should be word-aligned. + * + * @param[in] len + * The maximum object size in number of bytes. The @ref nvm3_getObjectInfo() function + * can be used to find the actual size. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_readData(nvm3_Handle_t *h, nvm3_ObjectKey_t key, void *value, size_t len); + +/***************************************************************************//** + * @brief + * Read parts of the object data identified with a given key from NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[out] value + * A pointer to the application data buffer. The read function will copy + * data to this location. For best performance, the buffer should be word-aligned. + * + * @param[in] ofs + * The offset where data shall be read from. + * + * @param[in] len + * The number of bytes to read. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_readPartialData(nvm3_Handle_t* h, nvm3_ObjectKey_t key, void* value, size_t ofs, size_t len); + +/***************************************************************************//** + * @brief + * Find the type and size of an object in NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[out] type + * A pointer to the location where NVM3 shall write the object type. The type can + * be either @ref NVM3_OBJECTTYPE_DATA or @ref NVM3_OBJECTTYPE_COUNTER. + * + * @param[out] len + * A pointer to the location where NVM3 writes the object size. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_getObjectInfo(nvm3_Handle_t *h, nvm3_ObjectKey_t key, + uint32_t *type, size_t *len); + +/***************************************************************************//** + * @brief + * Create a list of object keys for valid objects in NVM. + * + * @note + * The function @ref nvm3_countObjects() is also provided to count the + * number of valid objects. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[out] keyListPtr + * A pointer to a buffer for the key list. + * + * @param[in] keyListSize + * The number of elements in the key list buffer. If the keyListSize = 0, + * the @p keyListPtr can be NULL and the function will return the total + * number of objects. + * + * @param[in] keyMin + * The lower search key. Set to @ref NVM3_KEY_MIN to match all keys. + * + * @param[in] keyMax + * The upper search key. Set to @ref NVM3_KEY_MAX to match all keys. + * + * @return + * The number of keys written to the key list. This value is less than or equal + * to @p keyListSize. If the @p keyListSize = 0, the function will return the + * total number of objects matching the key Min - Max pattern. + ******************************************************************************/ +size_t nvm3_enumObjects(nvm3_Handle_t *h, + nvm3_ObjectKey_t *keyListPtr, size_t keyListSize, + nvm3_ObjectKey_t keyMin, nvm3_ObjectKey_t keyMax); + +/***************************************************************************//** + * @brief + * Create a list of object keys for deleted objects in NVM. + * + * @note + * The function @ref nvm3_countDeletedObjects() is also provided to count the + * number of deleted objects. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[out] keyListPtr + * A pointer to a buffer for the key list. + * + * @param[in] keyListSize + * The number of elements in the key list buffer. If the keyListSize = 0, + * the @p keyListPtr can be NULL and the function will return the total + * number of objects. + * + * @param[in] keyMin + * The lower search key. Set to @ref NVM3_KEY_MIN to match all keys. + * + * @param[in] keyMax + * The upper search key. Set to @ref NVM3_KEY_MAX to match all keys. + * + * @return + * The number of keys written to the key list. This value is less than or equal + * to @p keyListSize. If the @p keyListSize = 0, the function will return the + * total number of objects matching the key Min - Max pattern. + ******************************************************************************/ +size_t nvm3_enumDeletedObjects(nvm3_Handle_t *h, + nvm3_ObjectKey_t *keyListPtr, size_t keyListSize, + nvm3_ObjectKey_t keyMin, nvm3_ObjectKey_t keyMax); + +/***************************************************************************//** + * @brief + * Delete an object from NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_deleteObject(nvm3_Handle_t *h, nvm3_ObjectKey_t key); + +/***************************************************************************//** + * @brief + * Store a counter in NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[in] value + * The counter value to write. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_writeCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t value); + +/***************************************************************************//** + * @brief + * Read a counter value from NVM. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[out] value + * A pointer to the counter location. The read function will copy + * the counter value to this location. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_readCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t *value); + +/***************************************************************************//** + * @brief + * Increment a counter object value by 1 and read out optionally. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] key + * A 20-bit object identifier. + * + * @param[out] newValue + * A pointer to the counter readout location. The counter is incremented before the value + * is written to this location. Set this value to NULL to ignore readout. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_incrementCounter(nvm3_Handle_t *h, nvm3_ObjectKey_t key, uint32_t *newValue); + +/***************************************************************************//** + * @brief + * Delete all objects in NVM. + * + * @note + * Users don't need to call this function to get NVM3 into an + * initial valid state. + * + * @warning + * The execution time depends on the configured NVM size and may therefore be + * significant. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_eraseAll(nvm3_Handle_t *h); + +/***************************************************************************//** + * @brief + * Get the number of page erases of the most erased page in the NVM area since + * the first initialization. + * + * @note + * Except for pages marked as bad, pages will have an erase count equal to the + * most erased or one less because of the wear leveling algorithm. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] eraseCnt + * A pointer to the location where the NVM3 shall place the page + * erasure counter value. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_getEraseCount(nvm3_Handle_t *h, uint32_t *eraseCnt); + +/***************************************************************************//** + * @brief + * Set the page erase count. + * Normally, the application should not be concerned with the erase count value. + * If NVM3 is substituting a previous solution, it is possible to transfer + * the erase count to NVM3 when initializing the NVM for the first time. + * The erase count must be set before the @ref nvm3_open is called and will + * only take effect if the NVM is completely erased or contains unknown + * data to NVM3. In that case, all pages will be initialized with the supplied + * erase count. After @ref nvm3_open is called, the value will be consumed + * and will have no effect on further calls to @ref nvm3_open. + * + * @param[in] eraseCnt + * The erase count. + ******************************************************************************/ +void nvm3_setEraseCount(uint32_t eraseCnt); + +/***************************************************************************//** + * @brief + * Execute a repack operation. NVM3 will copy data or erase pages when repacking + * is needed. Calling @ref nvm3_repack() may block access to the non-volatile + * memory for up to one page erasure time plus an small execution overhead. + * The exact worst-case timing characteristics can be found in the data sheet for the + * part. + * + * @note + * Calling @ref nvm3_repack() is not mandatory because the functions that + * write data to NVM will trigger a repack if needed. Because a + * repack operation may be time consuming, the application may want to be + * in control of when repacking occurs by calling this function. + * + * More information about the repack operation can be found in the + * @ref nvm3_repack section. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_repack(nvm3_Handle_t *h); + +/***************************************************************************//** + * @brief + * Check the internal status of NVM3 and return true if a repack + * operation is required. The application must call @ref nvm3_repack() to + * perform the actual repack operation. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @return + * true if repacking is needed, false if repacking is not needed. + ******************************************************************************/ +bool nvm3_repackNeeded(nvm3_Handle_t *h); + +/***************************************************************************//** + * @brief + * Resize the NVM area used by an open NVM3 instance. + * The area can be resized by changing the start or end address either up + * or down in memory. Because the input parameters to NVM3 are start address + * and size, users should be cautious. Either move the start address up or + * down in memory and adjust the size accordingly to keep the end address, + * or keep the address and change the size only. + * It is not possible to resize the area by doing changes in both ends of the + * NVM address range at the same time. + * If the resize operation returns @ref ECODE_NVM3_OK, the instance is still + * open and can be used to access objects in the resized NVM. + * If the resize operation fails, the instance will still be open but with + * unchanged size. + * + * @note + * It is possible to decrease the NVM area to a new size that is not capable + * of keeping the already stored objects. The result is loss of data. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @param[in] newAddr + * The start address of the NVM after resize. + * + * @param[in] newSize + * The size of the NVM after resize. + * + * @return + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +Ecode_t nvm3_resize(nvm3_Handle_t *h, nvm3_HalPtr_t newAddr, size_t newSize); + +/***************************************************************************//** + * @brief + * Count valid objects. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @return + * The number of valid objects. + ******************************************************************************/ +__STATIC_INLINE size_t nvm3_countObjects(nvm3_Handle_t *h) +{ + return nvm3_enumObjects(h, NULL, 0, NVM3_KEY_MIN, NVM3_KEY_MAX); +} + +/***************************************************************************//** + * @brief + * Count deleted objects. + * + * @param[in] h + * A pointer to an NVM3 driver handle. + * + * @return + * The number of deleted objects. + ******************************************************************************/ +__STATIC_INLINE size_t nvm3_countDeletedObjects(nvm3_Handle_t *h) +{ + return nvm3_enumDeletedObjects(h, NULL, 0, NVM3_KEY_MIN, NVM3_KEY_MAX); +} + +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#include "nvm3_default.h" + +/* *INDENT-OFF* */ +/************ THIS SECTION IS FOR DOCUMENTATION ONLY !**********************//** + * @addtogroup nvm3 NVM3 - NVM Data Manager + * @brief NVM3 Non-Volatile Memory Data Management driver + * @{ + + # Introduction {#nvm3_intro} + The NVM3 driver provides a way for an application to safely store and + retrieve variable-size objects in a page-based non-volatile memory (NVM). + Objects are identified with 20-bit object identifiers denoted as keys. + + The driver is designed to use pages in a sequential order to provide equal + usage and wear. The driver is resilient to power loss or reset events, + ensuring that objects retrieved from the driver are in a valid state. A + valid object will always be the last successfully stored object. NVM3 can + detect NVM defects and mark pages as unusable. NVM3 will continue to operate + on good pages after defect pages are detected. + + # Objects {#nvm3_objects} + An NVM3 object is data that can be stored in NVM. The object + is handled as an array of bytes up to @ref NVM3_MAX_OBJECT_SIZE in size. + NVM3 can handle two types of objects. + -# Regular data objects. Data objects can store information of + any size up to maximum @ref NVM3_MAX_OBJECT_SIZE bytes. + -# 32-bit counter objects. Counter objects can store 32-bit counters that are + accessed with a separate set of API functions. The counter object is designed + to be compact while minimizing memory wear in applications that require + frequent persistent counter increments. + + See @ref nvm3_api for more details on the API. + + # Repacking {#nvm3_repack} + As the NVM fills up, it reaches a point where it can no longer store + additional objects, and a repacking operation is required to release + out-of-date objects to free up NVM. Because both writing data and erasing + pages take a long time, + the NVM3 driver does not trigger the process by itself unless free memory + reaches a critical low level. As an alternative, the application can trigger + the repacking process by calling the @ref nvm3_repack() function. + During the call, NVM3 will either move data to a new page or erase pages + that can be reused. At most, the call will block for a period equal to a page + erasure time or the time to write the largest size object (whatever is largest) + plus a small execution overhead. Page erasure and flash write timing for the + EFM32 or EFR32 parts can be found in the datasheet. + + NVM3 uses two thresholds for repacking: + -# Forced threshold. This is the threshold used to force automatic repacking + when free memory reaches a critical low level. + -# User threshold. This is the threshold used by @ref nvm3_repackNeeded(). + @ref nvm3_repack() will not perform repacking unless free memory is below + this threshold. + + The user can define the user threshold by entering a value in the repackHeadroom + member of the @ref nvm3_Init_t structure used by the @ref nvm3_open() function. + The repackHeadroom value defines the difference between the user and forced + threshold. The forced threshold is the minimum low memory threshold defined + by the page size and maximum object size and can't be changed by the user. + The default value for the repack headroom is 0, meaning that the forced and + user thresholds are equal. + + An NVM3 function that deletes or modifies data or counter object will trigger + an automatic repack operation when free memory is below the forced threshold. + The check is done before the object is modified, not after. + + The application can use @ref nvm3_repackNeeded() to determine if repacking + is needed. To initiate repacks, call @ref nvm3_repack(). Note that + this function will perform repacks only if they are needed. + + @note The repack threshold can be changed to prevent multiple modifications + of objects between user called repacks from causing forced repacks. Note + that "high" values of the repack headroom may cause + increased NVM wear from increased number of repacks. + + See @ref nvm3_timing section for more details on repack timing. + + # Caching {#nvm3_cache} + NVM3 includes an object location lookup cache to speed up object access, as + searching through the entire NVM3 contents for an object could otherwise + be slow. It is important to note that this cache only stores the location + of the object and not the object data itself. To ensure that cache can hold all necessary + information, it must be configured to a size equivalent to or larger than the + number of objects stored in NVM, including those deleted, as long as they are + not discarded by the repack function. If the cache is available, + the driver will first look in the cache to find the position of the object in NVM. + If the object position is not found in the cache, the object position will be + found by searching the NVM. The search will start at the last stored object + and search all the way to the oldest object. If the object is found, the cache + is updated accordingly. + + The application must allocate and support data for the cache. + See the @ref nvm3_open function for more details. The size of each cache + element is one uint32_t and one pointer giving a total of 8 bytes (2 words) + pr. entry for EFM32 and EFR32 devices. + + @note The cache is fully initialized by @ref nvm3_open() and automatically + updated by any subsequent write, read, or delete function call. + + # Global Data (variables) {#nvm3_data} + The NVM3 library uses global variables to store intermediate data + during open, read, write, increment, and delete calls. Because the actual + memory configuration is not defined at the time the NVM3 library is built + but rather at the time the user application is built, the size of data + structures must be determined by the application configuration. + Also, the application must set the value of the @ref nvm3_maxFragmentCount + at run-time before any NVM3 functions are called. + + NVM3 does not support overlapped calls. If there is any chance that the + application can issue overlapped calls, the NVM3 locking mechanism must be + present and protected from that. + + @note If the application uses more than one NVM3 instance, the variables + will be shared between the instances. Be sure to allocate data that have a + size that is large enough for the largest usage. + + # Stack Usage {#nvm3_stack} + NVM3 library function calls are nested several levels deep. The stack + usage has been measured on some EFM32, and EFR32 targets with library builds + for IAR and ARM GCC. The maximum stack usage measured was 420 bytes for + IAR, and 472 bytes for ARM GCC builds. The unit test used to validate the + stack usage has a 10% margin and uses a stack limit of 462 bytes for IAR + and 520 for ARM GCC. + Note that the actual stack usage is a little different on the Cortex + M0 Plus, M3, M4, and M33 versions of the library. + + # The API {#nvm3_api} + The NVM3 API is defined in the nvm3.h file. The application code + must include the nvm3.h header file to get access to all definitions, + datatypes, and function prototypes defined by NVM3. + + This section contains brief descriptions of NVM3 functions. For + more information about parameters and return values, see the Function + documentation section. Most functions return an @ref Ecode_t that has the + value @ref ECODE_NVM3_OK on success, or see nvm3.h for other values. + + @ref nvm3_open() and @ref nvm3_close(). + @n These functions open and close an NVM3 instance. @ref nvm3_open() takes a handle + of type nvm3_Handle_t and initialization data of type @ref nvm3_Init_t. + The helper macro pair @ref NVM3_DEFINE_SECTION_STATIC_DATA() and + @ref NVM3_DEFINE_SECTION_INIT_DATA() are provided to simplify initialization + data definition. For usage examples, see the @ref nvm3_example section. + + @ref nvm3_getObjectInfo(), @ref nvm3_enumObjects(), @ref nvm3_deleteObject() + and nvm3_countObjects() + @n These functions work on all objects. @ref nvm3_enumObjects() + gets a list of keys to valid objects in the NVM. The search can also + be constrained by the function parameters. + @ref nvm3_countObjects() can be useful at startup to distinguish between a + first startup without any valid objects present and later reboots with valid + objects persistently stored in NVM. + + @ref nvm3_writeData() and @ref nvm3_readData() + @n Write and read data objects. + + @ref nvm3_writeCounter(), @ref nvm3_readCounter() and @ref nvm3_incrementCounter() + @n Write, read, and increment 32-bit counter objects. + + @ref nvm3_eraseAll() + @n Erase all objects in NVM. + + @ref nvm3_getEraseCount() + @n Return the erasure count for the most erased page in NVM. + + @ref nvm3_repack() and @ref nvm3_repackNeeded() + @n Manage NVM3 repacking operations. + + @ref nvm3_resize() + @n Resize the NVM area used by an open NVM3 instance. + + # API Locking and Interrupt handling {#nvm3_locking} + Common for all NVM3 API calls is that they are not re-entrant. By default, + all functions are protected with protection functions that disable interrupts. + + @note The default NVM3 protection functions can be substituted by the + application if other synchronization functions are available and disabling + interrupts for extended periods is not desired. + + If the application does all the nvm3-calls from the same thread and guarantees + no overlapping calls, the lock functions don't have to do anything. + + # Memory Placement {#nvm3_memory_placement} + The application is responsible for placing the NVM area correctly. The minimum + requirements for memory placement are as follows: + -# NVM area start address must be aligned with a page of the underlying + memory system. + -# NVM area size must be a multiple of the page size. + + The minimum required NVM size is dependent on both the NVM page size and the + NVM3_MAX_OBJECT_SIZE value. For a device with 2 kB page size and typical + values for NVM3_MAX_OBJECT_SIZE, the following is the minimum required + number of pages: + - For NVM3_MAX_OBJECT_SIZE=208: 3 pages + - For NVM3_MAX_OBJECT_SIZE=1900: 4 pages + - For NVM3_MAX_OBJECT_SIZE=4096: 5 pages + + @ref NVM3_DEFINE_SECTION_STATIC_DATA() and @ref NVM3_DEFINE_SECTION_INIT_DATA() + macros are provided to support the creation of the NVM area and initialization + data. + A linker section called 'name'_section is defined by @ref NVM3_DEFINE_SECTION_STATIC_DATA(). + The NVM area is placed within the linker section. The application linker script + must place the section according to the requirements above. An error is returned + by @ref nvm3_open() on alignment or size violation. + + @note When the start address and size of the data area are defined and + used by an application, make sure you use the same values at + every program startup and also reuse by new versions of the software after + an upgrade. If an application tries to open an instance with a start address + or size that does not match the previous use, it can result in permanent data loss + and failure. + + # Configuration Options {#nvm3_configuration} + There are no compile-time configuration options for NVM3. All configuration + parameters are contained in @ref nvm3_Init_t. + + @note The @ref nvm3_data must however be configured for correct + size and have correct values for NVM3 to behave correctly. + + # Bad NVM Page Handling {#nvm3_bad_page_handling} + NVM3 has been designed to detect page erase and write errors during + normal operation and mark failing pages as BAD. If a write operation + fails, all objects that have been written to the page prior to the write + error are copied to the next free page before the page is marked as BAD and + the write operation resumes. If the recovery operation is successful, the + operation is regarded as complete, and the function will return @ref + ECODE_NVM3_OK status. + + @note Erase and write errors may not be detected by NVM3 if the device is + used until End-of-Life (EOL), where the failure mode can be that the NVM content is + changing during a power cycle. + + # Error Handling {#nvm3_error_handling} + The NVM3 error handling involves most functions + returning an error code. The @ref nvm3_countObjects is + different because it returns the actual number of objects + found. + + The behavior and return values for most functions, such as @ref + nvm3_readData, @ref nvm3_writeData, and so on should be self explanatory, + while the @ref nvm3_open is slightly different. @ref nvm3_open will always try + to recover from the previous state and continue without an error, if possible. + In other words, if a valid NVM3 instance is + established, @ref nvm3_open will recover from brownouts and power cycles at + any time in any operation and bring the system to a valid state where all + pages and objects are in a known state and return success whenever possible. + From this state, normal operation can resume. If @ref nvm3_open returns an + error, it's an indication of either a design or coding error + or that many of the NVM pages have been marked as BAD, leaving insufficient + space in the NVM to progress. Operation may not resume if @ref nvm3_open + returns an error. + + @note Because the @ref nvm3_open may need to do recovery operations, + the execution time will occasionally vary. + + # Storing Objects in Internal Flash {#nvm3_support_internal_flash} + NVM3 has support for writing and reading objects in internal, i.e., memory-mapped + Flash memory through the nvm3_hal_flash.c "driver". nvm3_hal_flash.c + is using EMLIB functions to write and erase data while using regular + memory functions to read data from Flash. + + @n The "driver" for internal Flash is selected by setting the halHandle in + the nvm3_open initialization structure to point to nvm3_halFlashHandle. + + # NVM3 Libraries {#nvm3_libraries} + The NVM3 comes with pre-compiled libraries for Cortex M0, M3, M4, and M33 + compiled with either Arm GCC or IAR toolchains. + + # Storage Capacity {#nvm3_capacity} + Basic storage is defined as the size of on instance of all objects, including + any overhead stored with the data. For NVM3 the maximum amount of data you + can store is dependent on the number of flash pages used for storage and the + max object size used for NVM3. The following table shows the maximum allowed + basic storage for a varying number of 2 kB or 8 kB flash pages and the minimum + (208 bytes), default (254 bytes), high (1900 bytes) and maximum (4096 bytes) + max object size. Note that this is a theoretical limit, and if the basic storage + is at this limit, no space is left for wear-levelling, and page erases will be + forced for every object written. The NVM3 instance should therefore be configured + with enough flash pages to put the maximum allowed basic storage significantly + higher than the actual basic storage. + + ## Max Allowed Basic Storage with 2 kB page size + + | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | + |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| + | | | Max object size = 208 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | + | 3 | 6144 | 1596 | 1504 | 0 | 0 | + | 4 | 8192 | 3624 | 3532 | 240 | 0 | + | 5 | 10240 | 5652 | 5560 | 2268 | 0 | + | 6 | 12288 | 7680 | 7588 | 4296 | 0 | + | 7 | 14336 | 9708 | 9616 | 6324 | 0 | + | 8 | 16384 | 11736 | 11644 | 8352 | 0 | + | 9 | 18432 | 13764 | 13672 | 10380 | 1900 | + | 10 | 20480 | 15792 | 15700 | 12408 | 3928 | + | 11 | 22528 | 17820 | 17728 | 14436 | 5956 | + | 12 | 24576 | 19848 | 19756 | 16464 | 7984 | + | 13 | 26624 | 21876 | 21784 | 18492 | 10012 | + | 14 | 28672 | 23904 | 23812 | 20520 | 12040 | + | 15 | 30720 | 25932 | 25840 | 22548 | 14068 | + | 16 | 32768 | 27960 | 27868 | 24576 | 16096 | + | 17 | 34816 | 29988 | 29896 | 26604 | 18124 | + | 18 | 36864 | 32016 | 31924 | 28632 | 20152 | + + ## Max Allowed Basic Storage with 8 kB page size + | Flash pages | Total size (bytes) | Max allowed basic storage (bytes) | | | | + |-------------------------------|--------------------------------------|-----------------------------------------|-------------------------------------|--------------------------------------|--------------------------------------| + | | | Max object size = 208 bytes | Max object size = 254 bytes | Max object size = 1900 bytes | Max object size = 4096 bytes | + | 3 | 24516 | 7740 | 7648 | 4356 | 0 | + | 4 | 32688 | 15912 | 15820 | 12528 | 8136 | + | 5 | 40860 | 24084 | 23992 | 20700 | 16308 | + | 6 | 49032 | 32256 | 32164 | 28872 | 24480 | + + # Default Instance {#nvm3_default} + Several NVM3 instances can be created on a device and live independently of each other, + but to save memory, it is usually desirable to use only one NVM3 instance as each + instance adds some overhead. For this reason, a default instance exists that is used + by all Silicon Labs wireless stacks. The API to initialize the default instance and + the handles to use with the regular NVM3 API are described in @ref nvm3default. + + # NVM3 in Simplicity Commander {#nvm3_commander} + Simplicity Commander is a single, all-purpose tool to be used in a production environment. + It is invoked using a simple Command Line Interface (CLI) that can also be scripted. + Simplicity Commander supports reading out the NVM3 data area from a device and parsing + the NVM3 data to extract stored values. This can be useful in a debugging scenario + where you may need to find out the stored state of an application that has been running + for some time. + + For more information about using the Simplicity Commander with NVM3, see + UG162: Simplicity Commander Reference Guide. + + # Execution Timing {#nvm3_timing} + There are several factors that affect the execution time for NVM3 calls that + can update the NVM, described below. + + The primary factor when doing updates is that data must be written to flash. + Writing to flash is relatively slow, and timing information for the particular + device is available in the datasheet and can be used to calculate the + approximately minimum execution time. Note that NVM3 will, in addition to the + user data, write object headers, and the software will add some + overhead. The relative overhead will be larger for smaller compared to larger + objects. + + When updating the flash store, repacking must be done from time to + time. See the @ref nvm3_repack section for more details about why + repacking is needed and how it works. + + To minimize the time when repacks are executed, there are a few configurations + that affect how NVM3 works. The most important configurations are listed below: + -# The repackHeadroom parameter in the @ref nvm3_Init_t structure can be used + to set the number of bytes that can be written before a forced repack is + triggered. To make this work, the @ref nvm3_repack() function must be called + until the @ref nvm3_repackNeeded() returns false before the actual write. + -# Use as small objects as possible and define the NVM3_MAX_OBJECT_SIZE + accordingly. Writing and repacking large objects is time-consuming. Limiting + the maximum object size will limit the time spent in both write and repack + functions. + + When triggered, the repack function will either copy data or erase a page. + To limit the time spent when copying, the repack function will return when + the NVM3_MAX_OBJECT_SIZE number of bytes have been copied. The copy operation + will resume on the next call to repack, and the application may have to call + the repack function several times to complete a full repack operation. + + @note Performing the @ref nvm3_repack()/@ref nvm3_repackNeeded() loop is + highly recommended before any timing-sensitive procedure. + + # Examples {#nvm3_example} + + Example 1 shows initialization, usage of data objects, and repacking. + + @include nvm3_example_1.c + + Example 2 shows initialization and usage of counter objects. The + counter object uses a compact way of storing a 32-bit counter value while minimizing + NVM wear. + + @include nvm3_example_2.c + + * @} end group nvm3 ****************************************************/ + +#endif /* NVM3_GENERIC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal.h index a6d0beb..ac85c23 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal.h @@ -1,249 +1,249 @@ -/***************************************************************************//** - * @file - * @brief NVM3 driver HAL - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_HAL_H -#define NVM3_HAL_H - -#include "ecode.h" -#include -#include -#include - -#ifdef NVM3_HOST_BUILD -#include "nvm3_hal_host.h" -#else -#include "sl_assert.h" -#include "sl_common.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup nvm3hal NVM3 HAL - * @brief NVM3 Hardware Abstraction Layer - * @{ - * @details - * This module provides the interface to the NVM. By having all NVM access - * functions in a separate file, it is possible to support different hardware - * by substituting the functions in this module. - * - * @note These functions are used by the NVM3 and should not be used by - * any applications. - ******************************************************************************/ - -/****************************************************************************** - ****************************** MACROS ********************************** - *****************************************************************************/ - -#define NVM3_HAL_WRITE_SIZE_32 0 ///< Only single writes are allowed -#define NVM3_HAL_WRITE_SIZE_16 1 ///< Two writes are allowed - -#define NVM3_HAL_NVM_ACCESS_NONE 0 ///< No access -#define NVM3_HAL_NVM_ACCESS_RD 1 ///< Read access -#define NVM3_HAL_NVM_ACCESS_RDWR 2 ///< Read and write access -#define NVM3_HAL_NVM_ACCESS_NOP 3 ///< Ignore - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#define nvm3_halOpen(hal, a, b) ((hal)->open((a), (b))) -#define nvm3_halClose(hal) ((hal)->close()) -#define nvm3_halGetInfo(hal, a) ((hal)->getInfo(a)) -#define nvm3_halNvmAccess(hal, a) ((hal)->access(a)) -#define nvm3_halReadWords(hal, a, b, c) ((hal)->readWords((a), (b), (c))) -#define nvm3_halWriteWords(hal, a, b, c) ((hal)->writeWords((a), (b), (c))) -#define nvm3_halPageErase(hal, a) ((hal)->pageErase(a)) - -/// @endcond - -/****************************************************************************** - ****************************** TYPEDEFS ********************************** - *****************************************************************************/ - -/// @brief Pointer to NVM -typedef void *nvm3_HalPtr_t; - -/// @brief Device NVM capabilities - -typedef struct nvm3_HalInfo { - uint16_t deviceFamilyPartNumber; ///< Device family or part number. - uint8_t writeSize; ///< Write-size: 0=32-bit, 1=16-bit. - uint8_t memoryMapped; ///< Memory-mapped: 0=not memory mapped, 1=memory mapped. - size_t pageSize; ///< The data storage page size. - uint64_t systemUnique; ///< Obsolete. Was used to support external flash. -} nvm3_HalInfo_t; - -typedef uint8_t nvm3_HalNvmAccessCode_t; ///< Definition of the access data type. - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Open the NVM3 HAL for usage. - * - * @details - * This function must be run at initialization, before any other functions - * are called. It is used to call necessary startup routines before the - * hardware can be accessed. - * - * @param[in] nvmAdr - * A pointer to the destination in NVM. - * - * @param[in] nvmSize - * The total size of the NVM. - * - * @return - * The result of the open call. - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -typedef Ecode_t (*nvm3_HalOpen_t)(nvm3_HalPtr_t nvmAdr, size_t nvmSize); - -/***************************************************************************//** - * @brief - * Close the NVM3 HAL for usage. - * - * @details - * This function should be called at program termination. - * Should be done before any graceful halts. - ******************************************************************************/ -typedef void(*nvm3_HalClose_t)(void); - -/***************************************************************************//** - * @brief - * Retrieve device information. - * - * @details - * This function is used to retrieve information about the device properties, - * such as the device family, write size, whether the NVM is memory mapped or - * not, and finally the NVM page size. - * - * @param[in] info - * A pointer to a structure that will receive the device information. - ******************************************************************************/ -typedef Ecode_t (*nvm3_HalGetInfo_t)(nvm3_HalInfo_t *info); - -/***************************************************************************//** - * @brief - * Control read and write access to the NVM. - * - * @details - * This function is used to control the access to the NVM. It can be either - * read, write, or none. - * - * @param[in] access - * The requested access. - ******************************************************************************/ -typedef void (*nvm3_HalNvmAccess_t)(nvm3_HalNvmAccessCode_t access); - -/***************************************************************************//** - * @brief - * Erase a page in the NVM. - * - * @details - * This function is used to erase an NVM page. - * - * @param[in] nvmAdr - * A memory address pointing to the start of the page to erase. - * - * @return - * The result of the erase operation. - ******************************************************************************/ -typedef Ecode_t (*nvm3_HalPageErase_t)(nvm3_HalPtr_t nvmAdr); - -/***************************************************************************//** - * @brief - * Read data from NVM. - * - * @details - * This function is used to read data from the NVM. It will be a - * blocking call, since the thread asking for data to be read cannot continue - * without the data. - * - * @param[in] nvmAdr - * A memory address in NVM where data will be read. - * - * @param[in] *dst - * A pointer to the destination buffer. - * - * @param[in] wordCnt - * The number of words to read. - ******************************************************************************/ -typedef Ecode_t (*nvm3_HalReadWords_t)(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt); - -/***************************************************************************//** - * @brief - * Write data to the NVM. - * - * @details - * This function is used to write data to the NVM. This is a blocking - * function. - * - * @param[in] nvmAdr - * A memory address in NVM where data will be written. - * - * @param[in] *pSrc - * A pointer to the source data. - * - * @param[in] cnt - * The number of words to write. - * - * @return - * The result of the write operation. - * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. - ******************************************************************************/ -typedef Ecode_t (*nvm3_HalWriteWords_t)(nvm3_HalPtr_t nvmAdr, void const *pSrc, size_t cnt); - -/// @brief The HAL handle definition. -typedef struct { - nvm3_HalOpen_t open; ///< Pointer to the open function - nvm3_HalClose_t close; ///< Pointer to the close function - nvm3_HalGetInfo_t getInfo; ///< Pointer to the get-info function - nvm3_HalNvmAccess_t access; ///< Pointer to the access function - nvm3_HalPageErase_t pageErase; ///< Pointer to the page-erase function - nvm3_HalReadWords_t readWords; ///< Pointer to the read-words function - nvm3_HalWriteWords_t writeWords; ///< Pointer to the write-words function -} nvm3_HalHandle_t; - -/** @} (end addtogroup nvm3hal) */ -/** @} (end addtogroup nvm3) */ - -#ifdef __cplusplus -} -#endif - -#endif /* NVM3_HAL_H */ +/***************************************************************************//** + * @file + * @brief NVM3 driver HAL + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_HAL_H +#define NVM3_HAL_H + +#include "ecode.h" +#include +#include +#include + +#ifdef NVM3_HOST_BUILD +#include "nvm3_hal_host.h" +#else +#include "sl_assert.h" +#include "sl_common.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3hal NVM3 HAL + * @brief NVM3 Hardware Abstraction Layer + * @{ + * @details + * This module provides the interface to the NVM. By having all NVM access + * functions in a separate file, it is possible to support different hardware + * by substituting the functions in this module. + * + * @note These functions are used by the NVM3 and should not be used by + * any applications. + ******************************************************************************/ + +/****************************************************************************** + ****************************** MACROS ********************************** + *****************************************************************************/ + +#define NVM3_HAL_WRITE_SIZE_32 0 ///< Only single writes are allowed +#define NVM3_HAL_WRITE_SIZE_16 1 ///< Two writes are allowed + +#define NVM3_HAL_NVM_ACCESS_NONE 0 ///< No access +#define NVM3_HAL_NVM_ACCESS_RD 1 ///< Read access +#define NVM3_HAL_NVM_ACCESS_RDWR 2 ///< Read and write access +#define NVM3_HAL_NVM_ACCESS_NOP 3 ///< Ignore + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#define nvm3_halOpen(hal, a, b) ((hal)->open((a), (b))) +#define nvm3_halClose(hal) ((hal)->close()) +#define nvm3_halGetInfo(hal, a) ((hal)->getInfo(a)) +#define nvm3_halNvmAccess(hal, a) ((hal)->access(a)) +#define nvm3_halReadWords(hal, a, b, c) ((hal)->readWords((a), (b), (c))) +#define nvm3_halWriteWords(hal, a, b, c) ((hal)->writeWords((a), (b), (c))) +#define nvm3_halPageErase(hal, a) ((hal)->pageErase(a)) + +/// @endcond + +/****************************************************************************** + ****************************** TYPEDEFS ********************************** + *****************************************************************************/ + +/// @brief Pointer to NVM +typedef void *nvm3_HalPtr_t; + +/// @brief Device NVM capabilities + +typedef struct nvm3_HalInfo { + uint16_t deviceFamilyPartNumber; ///< Device family or part number. + uint8_t writeSize; ///< Write-size: 0=32-bit, 1=16-bit. + uint8_t memoryMapped; ///< Memory-mapped: 0=not memory mapped, 1=memory mapped. + size_t pageSize; ///< The data storage page size. + uint64_t systemUnique; ///< Obsolete. Was used to support external flash. +} nvm3_HalInfo_t; + +typedef uint8_t nvm3_HalNvmAccessCode_t; ///< Definition of the access data type. + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Open the NVM3 HAL for usage. + * + * @details + * This function must be run at initialization, before any other functions + * are called. It is used to call necessary startup routines before the + * hardware can be accessed. + * + * @param[in] nvmAdr + * A pointer to the destination in NVM. + * + * @param[in] nvmSize + * The total size of the NVM. + * + * @return + * The result of the open call. + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +typedef Ecode_t (*nvm3_HalOpen_t)(nvm3_HalPtr_t nvmAdr, size_t nvmSize); + +/***************************************************************************//** + * @brief + * Close the NVM3 HAL for usage. + * + * @details + * This function should be called at program termination. + * Should be done before any graceful halts. + ******************************************************************************/ +typedef void(*nvm3_HalClose_t)(void); + +/***************************************************************************//** + * @brief + * Retrieve device information. + * + * @details + * This function is used to retrieve information about the device properties, + * such as the device family, write size, whether the NVM is memory mapped or + * not, and finally the NVM page size. + * + * @param[in] info + * A pointer to a structure that will receive the device information. + ******************************************************************************/ +typedef Ecode_t (*nvm3_HalGetInfo_t)(nvm3_HalInfo_t *info); + +/***************************************************************************//** + * @brief + * Control read and write access to the NVM. + * + * @details + * This function is used to control the access to the NVM. It can be either + * read, write, or none. + * + * @param[in] access + * The requested access. + ******************************************************************************/ +typedef void (*nvm3_HalNvmAccess_t)(nvm3_HalNvmAccessCode_t access); + +/***************************************************************************//** + * @brief + * Erase a page in the NVM. + * + * @details + * This function is used to erase an NVM page. + * + * @param[in] nvmAdr + * A memory address pointing to the start of the page to erase. + * + * @return + * The result of the erase operation. + ******************************************************************************/ +typedef Ecode_t (*nvm3_HalPageErase_t)(nvm3_HalPtr_t nvmAdr); + +/***************************************************************************//** + * @brief + * Read data from NVM. + * + * @details + * This function is used to read data from the NVM. It will be a + * blocking call, since the thread asking for data to be read cannot continue + * without the data. + * + * @param[in] nvmAdr + * A memory address in NVM where data will be read. + * + * @param[in] *dst + * A pointer to the destination buffer. + * + * @param[in] wordCnt + * The number of words to read. + ******************************************************************************/ +typedef Ecode_t (*nvm3_HalReadWords_t)(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt); + +/***************************************************************************//** + * @brief + * Write data to the NVM. + * + * @details + * This function is used to write data to the NVM. This is a blocking + * function. + * + * @param[in] nvmAdr + * A memory address in NVM where data will be written. + * + * @param[in] *pSrc + * A pointer to the source data. + * + * @param[in] cnt + * The number of words to write. + * + * @return + * The result of the write operation. + * @ref ECODE_NVM3_OK on success or a NVM3 @ref Ecode_t on failure. + ******************************************************************************/ +typedef Ecode_t (*nvm3_HalWriteWords_t)(nvm3_HalPtr_t nvmAdr, void const *pSrc, size_t cnt); + +/// @brief The HAL handle definition. +typedef struct { + nvm3_HalOpen_t open; ///< Pointer to the open function + nvm3_HalClose_t close; ///< Pointer to the close function + nvm3_HalGetInfo_t getInfo; ///< Pointer to the get-info function + nvm3_HalNvmAccess_t access; ///< Pointer to the access function + nvm3_HalPageErase_t pageErase; ///< Pointer to the page-erase function + nvm3_HalReadWords_t readWords; ///< Pointer to the read-words function + nvm3_HalWriteWords_t writeWords; ///< Pointer to the write-words function +} nvm3_HalHandle_t; + +/** @} (end addtogroup nvm3hal) */ +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#endif /* NVM3_HAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal_flash.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal_flash.h index e158877..2624f96 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal_flash.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_hal_flash.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief NVM3 driver HAL for memory mapped FLASH - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_HAL_FLASH_H -#define NVM3_HAL_FLASH_H - -#include "nvm3_hal.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup nvm3hal - * @{ - * @details - * This module provides the NVM3 interface to the EFM and EFR Flash NVM. - * - * @note The features available through the handle are used by the NVM3 and - * should not be used directly by any applications. - ******************************************************************************/ - -/******************************************************************************* - *************************** GLOBAL VARIABLES ****************************** - ******************************************************************************/ - -extern const nvm3_HalHandle_t nvm3_halFlashHandle; ///< The HAL flash handle. - -/** @} (end addtogroup nvm3hal) */ -/** @} (end addtogroup nvm3) */ - -#ifdef __cplusplus -} -#endif - -#endif /* NVM3_HAL_FLASH_H */ +/***************************************************************************//** + * @file + * @brief NVM3 driver HAL for memory mapped FLASH + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_HAL_FLASH_H +#define NVM3_HAL_FLASH_H + +#include "nvm3_hal.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3hal + * @{ + * @details + * This module provides the NVM3 interface to the EFM and EFR Flash NVM. + * + * @note The features available through the handle are used by the NVM3 and + * should not be used directly by any applications. + ******************************************************************************/ + +/******************************************************************************* + *************************** GLOBAL VARIABLES ****************************** + ******************************************************************************/ + +extern const nvm3_HalHandle_t nvm3_halFlashHandle; ///< The HAL flash handle. + +/** @} (end addtogroup nvm3hal) */ +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#endif /* NVM3_HAL_FLASH_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_lock.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_lock.h index 087b4af..6406efe 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_lock.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/inc/nvm3_lock.h @@ -1,87 +1,87 @@ -/***************************************************************************//** - * @file - * @brief NVM3 data access lock API definition - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef NVM3_LOCK_H -#define NVM3_LOCK_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup nvm3lock NVM3 Lock - * @brief NVM3 lock functions - * @{ - * @details - * This module provides data protection tools for NVM3. - * - * The functions in this module are the default protection tools for NVM3. - * The application can substitute the nvm3_lockBegin and nvm3_lockEnd - * functions as long as the NVM3 functions are protected from - * being called re-entrant. - * - * @note These functions are used by the NVM3 and should not be used by - * any applications. - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Begin a lock section. - ******************************************************************************/ -void nvm3_lockBegin(void); - -/***************************************************************************//** - * @brief - * End a lock section. - ******************************************************************************/ -void nvm3_lockEnd(void); - -/***************************************************************************//** - * @brief - * Disable execution from data area. - ******************************************************************************/ -void nvm3_lockDisableExecute(void* address, size_t size); - -/** @} (end addtogroup nvm3lock) */ -/** @} (end addtogroup nvm3) */ - -#ifdef __cplusplus -} -#endif - -#endif //NVM3_LOCK_H +/***************************************************************************//** + * @file + * @brief NVM3 data access lock API definition + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef NVM3_LOCK_H +#define NVM3_LOCK_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3lock NVM3 Lock + * @brief NVM3 lock functions + * @{ + * @details + * This module provides data protection tools for NVM3. + * + * The functions in this module are the default protection tools for NVM3. + * The application can substitute the nvm3_lockBegin and nvm3_lockEnd + * functions as long as the NVM3 functions are protected from + * being called re-entrant. + * + * @note These functions are used by the NVM3 and should not be used by + * any applications. + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Begin a lock section. + ******************************************************************************/ +void nvm3_lockBegin(void); + +/***************************************************************************//** + * @brief + * End a lock section. + ******************************************************************************/ +void nvm3_lockEnd(void); + +/***************************************************************************//** + * @brief + * Disable execution from data area. + ******************************************************************************/ +void nvm3_lockDisableExecute(void* address, size_t size); + +/** @} (end addtogroup nvm3lock) */ +/** @} (end addtogroup nvm3) */ + +#ifdef __cplusplus +} +#endif + +#endif //NVM3_LOCK_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_default_common_linker.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_default_common_linker.c index c975124..5506d9b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_default_common_linker.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_default_common_linker.c @@ -1,86 +1,86 @@ -/***************************************************************************//** - * @file - * @brief NVM3 definition of the default data structures. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "nvm3.h" -#include "nvm3_hal_flash.h" -#include "nvm3_default_config.h" - -#if defined(NVM3_BASE) -/* Manually control the NVM3 address and size */ - -#elif defined (__ICCARM__) - -__root uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] @ "SIMEE"; -#define NVM3_BASE (nvm3_default_storage) - -#elif defined (__GNUC__) - -extern char linker_nvm_begin; - -__attribute__((used)) uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] __attribute__ ((section(".simee"))); -#define NVM3_BASE (&linker_nvm_begin) - -#else -#error "Unsupported toolchain" -#endif - -nvm3_Handle_t nvm3_defaultHandleData; -nvm3_Handle_t *nvm3_defaultHandle = &nvm3_defaultHandleData; - -#if (NVM3_DEFAULT_CACHE_SIZE != 0) -static nvm3_CacheEntry_t defaultCache[NVM3_DEFAULT_CACHE_SIZE]; -#endif - -nvm3_Init_t nvm3_defaultInitData = -{ - (nvm3_HalPtr_t)NVM3_BASE, - NVM3_DEFAULT_NVM_SIZE, -#if (NVM3_DEFAULT_CACHE_SIZE != 0) - defaultCache, -#else - NULL, -#endif - NVM3_DEFAULT_CACHE_SIZE, - NVM3_DEFAULT_MAX_OBJECT_SIZE, - NVM3_DEFAULT_REPACK_HEADROOM, - &nvm3_halFlashHandle, -}; - -nvm3_Init_t *nvm3_defaultInit = &nvm3_defaultInitData; - -Ecode_t nvm3_initDefault(void) -{ - return nvm3_open(nvm3_defaultHandle, nvm3_defaultInit); -} - -Ecode_t nvm3_deinitDefault(void) -{ - return nvm3_close(nvm3_defaultHandle); -} +/***************************************************************************//** + * @file + * @brief NVM3 definition of the default data structures. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "nvm3.h" +#include "nvm3_hal_flash.h" +#include "nvm3_default_config.h" + +#if defined(NVM3_BASE) +/* Manually control the NVM3 address and size */ + +#elif defined (__ICCARM__) + +__root uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] @ "SIMEE"; +#define NVM3_BASE (nvm3_default_storage) + +#elif defined (__GNUC__) + +extern char linker_nvm_begin; + +__attribute__((used)) uint8_t nvm3_default_storage[NVM3_DEFAULT_NVM_SIZE] __attribute__ ((section(".simee"))); +#define NVM3_BASE (&linker_nvm_begin) + +#else +#error "Unsupported toolchain" +#endif + +nvm3_Handle_t nvm3_defaultHandleData; +nvm3_Handle_t *nvm3_defaultHandle = &nvm3_defaultHandleData; + +#if (NVM3_DEFAULT_CACHE_SIZE != 0) +static nvm3_CacheEntry_t defaultCache[NVM3_DEFAULT_CACHE_SIZE]; +#endif + +nvm3_Init_t nvm3_defaultInitData = +{ + (nvm3_HalPtr_t)NVM3_BASE, + NVM3_DEFAULT_NVM_SIZE, +#if (NVM3_DEFAULT_CACHE_SIZE != 0) + defaultCache, +#else + NULL, +#endif + NVM3_DEFAULT_CACHE_SIZE, + NVM3_DEFAULT_MAX_OBJECT_SIZE, + NVM3_DEFAULT_REPACK_HEADROOM, + &nvm3_halFlashHandle, +}; + +nvm3_Init_t *nvm3_defaultInit = &nvm3_defaultInitData; + +Ecode_t nvm3_initDefault(void) +{ + return nvm3_open(nvm3_defaultHandle, nvm3_defaultInit); +} + +Ecode_t nvm3_deinitDefault(void) +{ + return nvm3_close(nvm3_defaultHandle); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_hal_flash.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_hal_flash.c index f65aeff..016f2da 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_hal_flash.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_hal_flash.c @@ -1,231 +1,231 @@ -/***************************************************************************//** - * @file - * @brief Non-Volatile Memory Wear-Leveling driver HAL implementation - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include -#include "nvm3.h" -#include "nvm3_hal_flash.h" -#include "em_system.h" -#include "em_msc.h" - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup nvm3hal - * @{ - ******************************************************************************/ - -/****************************************************************************** - ****************************** MACROS ********************************** - *****************************************************************************/ - -#define CHECK_DATA 1 ///< Macro defining if data should be checked - -/****************************************************************************** - *************************** LOCAL VARIABLES ****************************** - *****************************************************************************/ - -/****************************************************************************** - *************************** LOCAL FUNCTIONS ****************************** - *****************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Convert return type. - * - * @details - * This function converts between the return type of the emlib and the - * NVM3 API. - * - * @param[in] result - * Operation result. - * - * @return - * Returns remapped status code. - ******************************************************************************/ -static Ecode_t convertMscStatusToNvm3Status(MSC_Status_TypeDef result) -{ - Ecode_t ret; - - switch (result) { - case mscReturnOk: - ret = ECODE_NVM3_OK; - break; - case mscReturnInvalidAddr: - ret = ECODE_NVM3_ERR_INT_ADDR_INVALID; - break; - default: - ret = ECODE_NVM3_ERR_INT_EMULATOR; - break; - } - - return ret; -} - -// Check if the page is erased. -static bool isErased(void *adr, size_t len) -{ - size_t i; - size_t cnt; - uint32_t *dat = adr; - - cnt = len / sizeof(uint32_t); - for (i = 0U; i < cnt; i++) { - if (*dat != 0xFFFFFFFFUL) { - return false; - } - dat++; - } - - return true; -} - -/** @endcond */ - -static Ecode_t nvm3_halFlashOpen(nvm3_HalPtr_t nvmAdr, size_t flashSize) -{ - (void)nvmAdr; - (void)flashSize; - MSC_Init(); - - return ECODE_NVM3_OK; -} - -static void nvm3_halFlashClose(void) -{ - MSC_Deinit(); -} - -static Ecode_t nvm3_halFlashGetInfo(nvm3_HalInfo_t *halInfo) -{ - SYSTEM_ChipRevision_TypeDef chipRev; - - SYSTEM_ChipRevisionGet(&chipRev); -#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - halInfo->deviceFamilyPartNumber = chipRev.partNumber; -#else - halInfo->deviceFamilyPartNumber = chipRev.family; -#endif - halInfo->memoryMapped = 1; -#if defined(_SILICON_LABS_32B_SERIES_2) - halInfo->writeSize = NVM3_HAL_WRITE_SIZE_32; -#else - halInfo->writeSize = NVM3_HAL_WRITE_SIZE_16; -#endif - halInfo->pageSize = SYSTEM_GetFlashPageSize(); - - return ECODE_NVM3_OK; -} - -static void nvm3_halFlashAccess(nvm3_HalNvmAccessCode_t access) -{ - (void)access; -} - -static Ecode_t nvm3_halFlashReadWords(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt) -{ - uint32_t *pSrc = (uint32_t *)nvmAdr; - uint32_t *pDst = dst; - - if ((((size_t)pSrc % 4) == 0) && (((size_t)pDst % 4) == 0)) { - while (wordCnt > 0U) { - *pDst++ = *pSrc++; - wordCnt--; - } - } else { - (void)memcpy(dst, nvmAdr, wordCnt * sizeof(uint32_t)); - } - - return ECODE_NVM3_OK; -} - -static Ecode_t nvm3_halFlashWriteWords(nvm3_HalPtr_t nvmAdr, void const *src, size_t wordCnt) -{ - const uint32_t *pSrc = src; - uint32_t *pDst = (uint32_t *)nvmAdr; - MSC_Status_TypeDef mscSta; - Ecode_t halSta; - size_t byteCnt; - - byteCnt = wordCnt * sizeof(uint32_t); - mscSta = MSC_WriteWord(pDst, pSrc, byteCnt); - halSta = convertMscStatusToNvm3Status(mscSta); - -#if CHECK_DATA - if (halSta == ECODE_NVM3_OK) { - if (memcmp(pDst, pSrc, byteCnt) != 0) { - halSta = ECODE_NVM3_ERR_WRITE_FAILED; - } - } -#endif - - return halSta; -} - -static Ecode_t nvm3_halFlashPageErase(nvm3_HalPtr_t nvmAdr) -{ - MSC_Status_TypeDef mscSta; - Ecode_t halSta; - - mscSta = MSC_ErasePage((uint32_t *)nvmAdr); - halSta = convertMscStatusToNvm3Status(mscSta); - -#if CHECK_DATA - if (halSta == ECODE_NVM3_OK) { - if (!isErased(nvmAdr, SYSTEM_GetFlashPageSize())) { - halSta = ECODE_NVM3_ERR_ERASE_FAILED; - } - } -#endif - - return halSta; -} - -/******************************************************************************* - *************************** GLOBAL VARIABLES ****************************** - ******************************************************************************/ - -const nvm3_HalHandle_t nvm3_halFlashHandle = { - .open = nvm3_halFlashOpen, ///< Set the open function - .close = nvm3_halFlashClose, ///< Set the close function - .getInfo = nvm3_halFlashGetInfo, ///< Set the get-info function - .access = nvm3_halFlashAccess, ///< Set the access function - .pageErase = nvm3_halFlashPageErase, ///< Set the page-erase function - .readWords = nvm3_halFlashReadWords, ///< Set the read-words function - .writeWords = nvm3_halFlashWriteWords, ///< Set the write-words function -}; - -/** @} (end addtogroup nvm3hal) */ -/** @} (end addtogroup nvm3) */ +/***************************************************************************//** + * @file + * @brief Non-Volatile Memory Wear-Leveling driver HAL implementation + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include +#include "nvm3.h" +#include "nvm3_hal_flash.h" +#include "em_system.h" +#include "em_msc.h" + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup nvm3hal + * @{ + ******************************************************************************/ + +/****************************************************************************** + ****************************** MACROS ********************************** + *****************************************************************************/ + +#define CHECK_DATA 1 ///< Macro defining if data should be checked + +/****************************************************************************** + *************************** LOCAL VARIABLES ****************************** + *****************************************************************************/ + +/****************************************************************************** + *************************** LOCAL FUNCTIONS ****************************** + *****************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Convert return type. + * + * @details + * This function converts between the return type of the emlib and the + * NVM3 API. + * + * @param[in] result + * Operation result. + * + * @return + * Returns remapped status code. + ******************************************************************************/ +static Ecode_t convertMscStatusToNvm3Status(MSC_Status_TypeDef result) +{ + Ecode_t ret; + + switch (result) { + case mscReturnOk: + ret = ECODE_NVM3_OK; + break; + case mscReturnInvalidAddr: + ret = ECODE_NVM3_ERR_INT_ADDR_INVALID; + break; + default: + ret = ECODE_NVM3_ERR_INT_EMULATOR; + break; + } + + return ret; +} + +// Check if the page is erased. +static bool isErased(void *adr, size_t len) +{ + size_t i; + size_t cnt; + uint32_t *dat = adr; + + cnt = len / sizeof(uint32_t); + for (i = 0U; i < cnt; i++) { + if (*dat != 0xFFFFFFFFUL) { + return false; + } + dat++; + } + + return true; +} + +/** @endcond */ + +static Ecode_t nvm3_halFlashOpen(nvm3_HalPtr_t nvmAdr, size_t flashSize) +{ + (void)nvmAdr; + (void)flashSize; + MSC_Init(); + + return ECODE_NVM3_OK; +} + +static void nvm3_halFlashClose(void) +{ + MSC_Deinit(); +} + +static Ecode_t nvm3_halFlashGetInfo(nvm3_HalInfo_t *halInfo) +{ + SYSTEM_ChipRevision_TypeDef chipRev; + + SYSTEM_ChipRevisionGet(&chipRev); +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + halInfo->deviceFamilyPartNumber = chipRev.partNumber; +#else + halInfo->deviceFamilyPartNumber = chipRev.family; +#endif + halInfo->memoryMapped = 1; +#if defined(_SILICON_LABS_32B_SERIES_2) + halInfo->writeSize = NVM3_HAL_WRITE_SIZE_32; +#else + halInfo->writeSize = NVM3_HAL_WRITE_SIZE_16; +#endif + halInfo->pageSize = SYSTEM_GetFlashPageSize(); + + return ECODE_NVM3_OK; +} + +static void nvm3_halFlashAccess(nvm3_HalNvmAccessCode_t access) +{ + (void)access; +} + +static Ecode_t nvm3_halFlashReadWords(nvm3_HalPtr_t nvmAdr, void *dst, size_t wordCnt) +{ + uint32_t *pSrc = (uint32_t *)nvmAdr; + uint32_t *pDst = dst; + + if ((((size_t)pSrc % 4) == 0) && (((size_t)pDst % 4) == 0)) { + while (wordCnt > 0U) { + *pDst++ = *pSrc++; + wordCnt--; + } + } else { + (void)memcpy(dst, nvmAdr, wordCnt * sizeof(uint32_t)); + } + + return ECODE_NVM3_OK; +} + +static Ecode_t nvm3_halFlashWriteWords(nvm3_HalPtr_t nvmAdr, void const *src, size_t wordCnt) +{ + const uint32_t *pSrc = src; + uint32_t *pDst = (uint32_t *)nvmAdr; + MSC_Status_TypeDef mscSta; + Ecode_t halSta; + size_t byteCnt; + + byteCnt = wordCnt * sizeof(uint32_t); + mscSta = MSC_WriteWord(pDst, pSrc, byteCnt); + halSta = convertMscStatusToNvm3Status(mscSta); + +#if CHECK_DATA + if (halSta == ECODE_NVM3_OK) { + if (memcmp(pDst, pSrc, byteCnt) != 0) { + halSta = ECODE_NVM3_ERR_WRITE_FAILED; + } + } +#endif + + return halSta; +} + +static Ecode_t nvm3_halFlashPageErase(nvm3_HalPtr_t nvmAdr) +{ + MSC_Status_TypeDef mscSta; + Ecode_t halSta; + + mscSta = MSC_ErasePage((uint32_t *)nvmAdr); + halSta = convertMscStatusToNvm3Status(mscSta); + +#if CHECK_DATA + if (halSta == ECODE_NVM3_OK) { + if (!isErased(nvmAdr, SYSTEM_GetFlashPageSize())) { + halSta = ECODE_NVM3_ERR_ERASE_FAILED; + } + } +#endif + + return halSta; +} + +/******************************************************************************* + *************************** GLOBAL VARIABLES ****************************** + ******************************************************************************/ + +const nvm3_HalHandle_t nvm3_halFlashHandle = { + .open = nvm3_halFlashOpen, ///< Set the open function + .close = nvm3_halFlashClose, ///< Set the close function + .getInfo = nvm3_halFlashGetInfo, ///< Set the get-info function + .access = nvm3_halFlashAccess, ///< Set the access function + .pageErase = nvm3_halFlashPageErase, ///< Set the page-erase function + .readWords = nvm3_halFlashReadWords, ///< Set the read-words function + .writeWords = nvm3_halFlashWriteWords, ///< Set the write-words function +}; + +/** @} (end addtogroup nvm3hal) */ +/** @} (end addtogroup nvm3) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_lock.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_lock.c index c3bfdb4..3c463ca 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_lock.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/nvm3/src/nvm3_lock.c @@ -1,138 +1,138 @@ -/***************************************************************************//** - * @file - * @brief NVM3 data access lock API implementation - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "nvm3_lock.h" -#include "nvm3.h" - -#ifdef NVM3_HOST_BUILD -#include "nvm3_config.h" -#include "nvm3_trace.h" -#include "nvm3_hal.h" -#else -#include "em_core.h" -#endif - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_MPU_PRESENT) -#include "sl_mpu.h" -#endif - -//**************************************************************************** - -#ifdef NVM3_HOST_BUILD -#define SL_WEAK -#endif - -#ifdef NVM3_HOST_BUILD -static int lockCount = 0; -#else -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -CORE_DECLARE_IRQ_STATE; -/// @endcond -#endif - -/***************************************************************************//** - * @addtogroup nvm3 - * @{ - ******************************************************************************/ - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -nvm3_Obj_t nvm3_internalObjectHandleA; -nvm3_Obj_t nvm3_internalObjectHandleB; -nvm3_Obj_t nvm3_internalObjectHandleC; -nvm3_Obj_t nvm3_internalObjectHandleD; -const uint8_t nvm3_maxFragmentCount = NVM3_FRAGMENT_COUNT; -const size_t nvm3_objHandleSize = sizeof(nvm3_Obj_t); - -/// @endcond - -/***************************************************************************//** - * @addtogroup nvm3lock - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @details - * The default lock-begin implementation. - ******************************************************************************/ -SL_WEAK void nvm3_lockBegin(void) -{ -#ifdef NVM3_HOST_BUILD - lockCount++; -#else -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - CORE_ENTER_CRITICAL(); -/// @endcond -#endif -} - -/***************************************************************************//** - * @details - * The default lock-end implementation. - ******************************************************************************/ -SL_WEAK void nvm3_lockEnd(void) -{ -#ifdef NVM3_HOST_BUILD - if (lockCount == 0) { - nvm3_tracePrint(NVM3_TRACE_LEVEL_ERROR, "NVM3 ERROR - lockEnd: invalid lock count.\n"); - } - lockCount--; -#else - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @details - * Disable execution from data area. - * - * @param[in] address Start of memory range - * - * @param[in] size Size of memory range. - ******************************************************************************/ -void nvm3_lockDisableExecute(void *address, size_t size) -{ -#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) \ - && defined(SL_CATALOG_MPU_PRESENT) \ - && !defined(SL_TRUSTZONE_SECURE) - // The memory range used by nvm3 may not be compatible with the mpu. - // Just ignore errors. - sl_mpu_disable_execute((uint32_t)address, (uint32_t)address + size - 1, size); -#else - (void)address; - (void)size; -#endif -} - -/** @} (end addtogroup nvm3lock) */ -/** @} (end addtogroup nvm3) */ +/***************************************************************************//** + * @file + * @brief NVM3 data access lock API implementation + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "nvm3_lock.h" +#include "nvm3.h" + +#ifdef NVM3_HOST_BUILD +#include "nvm3_config.h" +#include "nvm3_trace.h" +#include "nvm3_hal.h" +#else +#include "em_core.h" +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MPU_PRESENT) +#include "sl_mpu.h" +#endif + +//**************************************************************************** + +#ifdef NVM3_HOST_BUILD +#define SL_WEAK +#endif + +#ifdef NVM3_HOST_BUILD +static int lockCount = 0; +#else +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +CORE_DECLARE_IRQ_STATE; +/// @endcond +#endif + +/***************************************************************************//** + * @addtogroup nvm3 + * @{ + ******************************************************************************/ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +nvm3_Obj_t nvm3_internalObjectHandleA; +nvm3_Obj_t nvm3_internalObjectHandleB; +nvm3_Obj_t nvm3_internalObjectHandleC; +nvm3_Obj_t nvm3_internalObjectHandleD; +const uint8_t nvm3_maxFragmentCount = NVM3_FRAGMENT_COUNT; +const size_t nvm3_objHandleSize = sizeof(nvm3_Obj_t); + +/// @endcond + +/***************************************************************************//** + * @addtogroup nvm3lock + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @details + * The default lock-begin implementation. + ******************************************************************************/ +SL_WEAK void nvm3_lockBegin(void) +{ +#ifdef NVM3_HOST_BUILD + lockCount++; +#else +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + CORE_ENTER_CRITICAL(); +/// @endcond +#endif +} + +/***************************************************************************//** + * @details + * The default lock-end implementation. + ******************************************************************************/ +SL_WEAK void nvm3_lockEnd(void) +{ +#ifdef NVM3_HOST_BUILD + if (lockCount == 0) { + nvm3_tracePrint(NVM3_TRACE_LEVEL_ERROR, "NVM3 ERROR - lockEnd: invalid lock count.\n"); + } + lockCount--; +#else + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @details + * Disable execution from data area. + * + * @param[in] address Start of memory range + * + * @param[in] size Size of memory range. + ******************************************************************************/ +void nvm3_lockDisableExecute(void *address, size_t size) +{ +#if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1U) \ + && defined(SL_CATALOG_MPU_PRESENT) \ + && !defined(SL_TRUSTZONE_SECURE) + // The memory range used by nvm3 may not be compatible with the mpu. + // Just ignore errors. + sl_mpu_disable_execute((uint32_t)address, (uint32_t)address + size - 1, size); +#else + (void)address; + (void)size; +#endif +} + +/** @} (end addtogroup nvm3lock) */ +/** @} (end addtogroup nvm3) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/inc/uartdrv.h b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/inc/uartdrv.h index b983a57..31ce466 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/inc/uartdrv.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/inc/uartdrv.h @@ -1,492 +1,492 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV API definition. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef UARTDRV_H -#define UARTDRV_H - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#include "em_device.h" -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#include "em_usart.h" -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) -#include "em_leuart.h" -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - -#if (_SILICON_LABS_32B_SERIES > 2) -#define UARTDRV_USE_PERIPHERAL -#include "sl_peripheral_eusart.h" -#else -#include "em_eusart.h" -#endif -#endif - -#if defined(UARTDRV_USE_PERIPHERAL) -#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 // TODO (PLATFORM_MTL-8363): Remove when sl_gpio will be used. -#include "sl_peripheral_gpio.h" -#else -#include "em_gpio.h" -#endif - -#include "em_cmu.h" -#include "ecode.h" -#include "uartdrv_config.h" -#include "dmadrv.h" -#include "sl_enum.h" -#include "sl_sleeptimer.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup uartdrv - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup uartdrv_error_codes Error Codes - * @{ - ******************************************************************************/ -#define ECODE_EMDRV_UARTDRV_OK (ECODE_OK) ///< A successful return value. -#define ECODE_EMDRV_UARTDRV_WAITING (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue. -#define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle. -#define ECODE_EMDRV_UARTDRV_PARAM_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter. -#define ECODE_EMDRV_UARTDRV_BUSY (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy. -#define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port. -#define ECODE_EMDRV_UARTDRV_IDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress. -#define ECODE_EMDRV_UARTDRV_ABORTED (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted. -#define ECODE_EMDRV_UARTDRV_QUEUE_FULL (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full. -#define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty. -#define ECODE_EMDRV_UARTDRV_PARITY_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored. -#define ECODE_EMDRV_UARTDRV_FRAME_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored. -#define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels. -#define ECODE_EMDRV_UARTDRV_CLOCK_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate. -/** @} (end addtogroup error codes) */ - -/***************************************************************************//** - * @addtogroup uartdrv_status_codes Status Codes - * @{ - ******************************************************************************/ -#define UARTDRV_STATUS_RXEN (1 << 0) ///< The receiver is enabled. -#define UARTDRV_STATUS_TXEN (1 << 1) ///< The transmitter is enabled. -#define UARTDRV_STATUS_RXBLOCK (1 << 3) ///< The receiver is blocked; incoming frames will be discarded. -#define UARTDRV_STATUS_TXTRI (1 << 4) ///< The transmitter is tristated. -#define UARTDRV_STATUS_TXC (1 << 5) ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register. -#define UARTDRV_STATUS_TXBL (1 << 6) ///< The transmit buffer is empty. -#define UARTDRV_STATUS_RXDATAV (1 << 7) ///< Data is available in the receive buffer. -#define UARTDRV_STATUS_RXFULL (1 << 8) ///< The receive buffer is full. -#if defined(EUSART_STATUS_TXCANDTXIDLE) -#define UARTDRV_STATUS_TXCANDTXIDLE (1 << 9) ///< Set when both TXC and TXIDLE are set. -#endif -#define UARTDRV_STATUS_TXIDLE (1 << 13) ///< The transmitter is idle. -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -#define UARTDRV_STATUS_RXIDLE (1 << 12) ///< The Receiver is idle. -#endif -/** @} (end addtogroup status codes) */ - -typedef uint32_t UARTDRV_Count_t; ///< A UART transfer count -typedef uint32_t UARTDRV_Status_t; ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values. - -/** - * @enum UARTDRV_FlowControlType_t - * @brief UARTDRV Flow Control method. - */ -SL_ENUM(UARTDRV_FlowControlType_t) { - uartdrvFlowControlNone = 0, ///< None - uartdrvFlowControlSw = 1, ///< Software XON/XOFF - uartdrvFlowControlHw = 2, ///< nRTS/nCTS hardware handshake - uartdrvFlowControlHwUart = 3 ///< UART peripheral controls nRTS/nCTS -}; - -/// Flow Control state -SL_ENUM(UARTDRV_FlowControlState_t) { - uartdrvFlowControlOn = 0, ///< XON or nRTS/nCTS low - uartdrvFlowControlOff = 1, ///< XOFF or nRTS/nCTS high - uartdrvFlowControlAuto = 2 ///< This driver controls the state. -}; - -/// Transfer abort type -SL_ENUM(UARTDRV_AbortType_t) { - uartdrvAbortTransmit = 1, ///< Abort current and queued transmit operations - uartdrvAbortReceive = 2, ///< Abort current and queued receive operations - uartdrvAbortAll = 3 ///< Abort all current and queued operations -}; - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -/// Type of a UART peripheral -SL_ENUM(UARTDRV_UartType_t) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - uartdrvUartTypeUart = 0, ///< USART/UART peripheral -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - uartdrvUartTypeLeuart = 1 ///< LEUART peripheral -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - uartdrvUartTypeEuart = 2 ///< EUART peripheral -#endif -}; -/// @endcond - -struct UARTDRV_HandleData; - -/***************************************************************************//** - * @brief - * UARTDRV transfer completion callback function. - * - * @details - * Called when a transfer is complete. An - * application should check the transferStatus and itemsTransferred values. - * - * @param[in] handle - * The UARTDRV device handle used to start the transfer. - * - * @param[in] transferStatus - * Completion status of the transfer operation. - * - * @param[in] data - * A pointer to the transfer data buffer. - * - * @param[in] transferCount - * A number of bytes transferred. - ******************************************************************************/ -typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle, - Ecode_t transferStatus, - uint8_t *data, - UARTDRV_Count_t transferCount); - -/// UART transfer buffer -typedef struct { - uint8_t *data; ///< Transfer data buffer - UARTDRV_Count_t transferCount; ///< Transfer item count - volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining - UARTDRV_Callback_t callback; ///< Completion callback - Ecode_t transferStatus; ///< Completion status of the transfer operation -} UARTDRV_Buffer_t; - -/// Transfer operation FIFO queue typedef -typedef struct { - volatile uint16_t head; ///< An index of the next byte to send. - volatile uint16_t tail; ///< An index of the location to enqueue the next message. - volatile uint16_t used; ///< A number of bytes queued. - const uint16_t size; ///< FIFO size. - UARTDRV_Buffer_t fifo[1]; ///< FIFO of queued data. Actual size varies. -} UARTDRV_Buffer_FifoQueue_t; - -/// Macros to define FIFO and buffer queues. typedef can't be used because the size -/// of the FIFO array in the queues can change. -#define DEFINE_BUF_QUEUE(qSize, qName) \ - typedef struct { \ - uint16_t head; \ - uint16_t tail; \ - volatile uint16_t used; \ - const uint16_t size; \ - UARTDRV_Buffer_t fifo[qSize]; \ - } _##qName; \ - static volatile _##qName qName = \ - { \ - .head = 0, \ - .tail = 0, \ - .used = 0, \ - .size = qSize, \ - } - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/** - * @struct UARTDRV_InitUart_t - * @brief A UART driver instance initialization structure. - * LEUART driver instance initialization structure. - * Contains a number of UARTDRV configuration options. - * It is required for driver instance initialization. - * This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV - * instance. - */ -typedef struct { - USART_TypeDef *port; ///< The peripheral used for UART - uint32_t baudRate; ///< UART baud rate -#if defined(_USART_ROUTELOC0_MASK) - uint8_t portLocationTx; ///< A location number for UART Tx pin. - uint8_t portLocationRx; ///< A location number for UART Rx pin. -#elif defined(_USART_ROUTE_MASK) - uint8_t portLocation; ///< A location number for UART pins. -#elif defined(_GPIO_USART_ROUTEEN_MASK) - GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. - GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. - uint8_t txPin; ///< Pin number for UART Tx. - uint8_t rxPin; ///< Pin number for UART Rx. - uint8_t uartNum; ///< UART instance number. -#endif - USART_Stopbits_TypeDef stopBits; ///< A number of stop bits. - USART_Parity_TypeDef parity; ///< Parity configuration. - USART_OVS_TypeDef oversampling; ///< Oversampling mode. -#if defined(USART_CTRL_MVDIS) - bool mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#endif - UARTDRV_FlowControlType_t fcType; ///< Flow control mode. - GPIO_Port_TypeDef ctsPort; ///< A CTS pin port number. - uint8_t ctsPin; ///< A CTS pin number. - GPIO_Port_TypeDef rtsPort; ///< An RTS pin port number. - uint8_t rtsPin; ///< An RTS pin number. - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< A receive operation queue. - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< T transmit operation queue. -#if defined(_USART_ROUTELOC1_MASK) - uint8_t portLocationCts; ///< A location number for the UART CTS pin. - uint8_t portLocationRts; ///< A location number for the UART RTS pin. -#endif -} UARTDRV_InitUart_t; -#endif - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -/** - * @struct UARTDRV_InitLeuart_t - * @brief LEUART driver instance initialization structure. - * LEUART driver instance initialization structure. - * Contains a number of UARTDRV configuration options. - * It is required to initialize a driver instance. - * This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV - * instance. - */ -typedef struct { - LEUART_TypeDef *port; ///< The peripheral used for LEUART - uint32_t baudRate; ///< UART baud rate -#if defined(_LEUART_ROUTELOC0_MASK) - uint8_t portLocationTx; ///< Location number for LEUART Tx pin. - uint8_t portLocationRx; ///< Location number for LEUART Rx pin. -#else - uint8_t portLocation; ///< Location number for LEUART pins -#endif - LEUART_Stopbits_TypeDef stopBits; ///< Number of stop bits - LEUART_Parity_TypeDef parity; ///< Parity configuration - UARTDRV_FlowControlType_t fcType; ///< Flow control mode - GPIO_Port_TypeDef ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - GPIO_Port_TypeDef rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue -} UARTDRV_InitLeuart_t; -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -/// UART driver instance initialization structure. -/// Contains a number of UARTDRV configuration options. -/// It is required to initialize a driver instance. -/// This structure is passed to @ref UARTDRV_InitEuart() when initializing a UARTDRV -typedef struct { - EUSART_TypeDef *port; ///< The peripheral used for EUART - bool useLowFrequencyMode; ///< Clock configuration of the EUART - uint32_t baudRate; ///< EUART baud rate -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t txPort; ///< Port for UART Tx pin. - sl_gpio_port_t rxPort; ///< Port for UART Rx pin. -#else - GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. - GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. -#endif - uint8_t txPin; ///< Pin number for UART Tx. - uint8_t rxPin; ///< Pin number for UART Rx. - uint8_t uartNum; ///< EUART instance number. -#if defined(UARTDRV_USE_PERIPHERAL) - sl_hal_eusart_stop_bits_t stopBits; ///< Number of stop bits - sl_hal_eusart_parity_t parity; ///< Parity configuration - sl_hal_eusart_ovs_t oversampling; ///< Oversampling mode. - sl_hal_eusart_majority_vote_t mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#else - EUSART_Stopbits_TypeDef stopBits; ///< Number of stop bits - EUSART_Parity_TypeDef parity; ///< Parity configuration - EUSART_OVS_TypeDef oversampling; ///< Oversampling mode. - EUSART_MajorityVote_TypeDef mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. -#endif - UARTDRV_FlowControlType_t fcType; ///< Flow control mode -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - sl_gpio_port_t rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number -#else - GPIO_Port_TypeDef ctsPort; ///< CTS pin port number - uint8_t ctsPin; ///< CTS pin number - GPIO_Port_TypeDef rtsPort; ///< RTS pin port number - uint8_t rtsPin; ///< RTS pin number -#endif - UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue -} UARTDRV_InitEuart_t; -#endif - -/// A UART driver instance handle data structure. -/// Allocated by the application using UARTDRV. -/// Several concurrent driver instances may exist in an application. The application must -/// not modify the contents of this handle and should not depend on its values. -typedef struct UARTDRV_HandleData{ - /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - union { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - USART_TypeDef * uart; -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - LEUART_TypeDef * leuart; -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - EUSART_TypeDef * euart; -#endif - void * __reserved_space; - } peripheral; - uint8_t uartNum; // UART instance number - unsigned int txDmaCh; // A DMA ch assigned to Tx - unsigned int rxDmaCh; // A DMA ch assigned to Rx - DMADRV_PeripheralSignal_t txDmaSignal; // A DMA Tx trigger source signal - DMADRV_PeripheralSignal_t rxDmaSignal; // A DMA Rx trigger source signal - UARTDRV_FlowControlState_t fcSelfState; // A current self flow control state - UARTDRV_FlowControlState_t fcSelfCfg; // A self flow control override configuration - UARTDRV_FlowControlState_t fcPeerState; // A current peer flow control state -#if defined(UARTDRV_USE_PERIPHERAL) - sl_gpio_port_t txPort; // A Tx pin port number - sl_gpio_port_t rxPort; // An Rx pin port number - sl_gpio_port_t ctsPort; // A CTS pin port number - sl_gpio_port_t rtsPort; // An RTS pin port number -#else - GPIO_Port_TypeDef txPort; // A Tx pin port number - GPIO_Port_TypeDef rxPort; // An Rx pin port number - GPIO_Port_TypeDef ctsPort; // A CTS pin port number - GPIO_Port_TypeDef rtsPort; // An RTS pin port number -#endif - uint8_t txPin; // A Tx pin number - uint8_t rxPin; // An Tx pin number - uint8_t ctsPin; // A CTS pin number - uint8_t rtsPin; // An RTS pin number - CMU_Clock_TypeDef uartClock; // A clock source select - UARTDRV_Buffer_FifoQueue_t *rxQueue; // A receive operation queue - UARTDRV_Buffer_FifoQueue_t *txQueue; // A transmit operation queue - volatile bool rxDmaActive; // A receive DMA is currently active - volatile bool txDmaActive; // A transmit DMA is currently active - volatile uint8_t txDmaPaused; // A transmit DMA pause counter - bool IgnoreRestrain; // A transmit does not respect uartdrvFlowControlOff - bool hasTransmitted; // Indicates whether the handle has transmitted data - UARTDRV_FlowControlType_t fcType; // A flow control mode - UARTDRV_UartType_t type; // A type of UART - volatile int em1RequestCount; // A EM1 request count for the handle - sl_sleeptimer_timer_handle_t delayedTxTimer; // A timer to wait for the last byte out - size_t sleep; // Sleep state on isr return - /// @endcond -} UARTDRV_HandleData_t; - -/// Handle pointer -typedef UARTDRV_HandleData_t * UARTDRV_Handle_t; - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t * initData); -#endif - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t * initData); -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t * initData); -#endif -Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle); - -UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle); - -UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *bytesReceived, - UARTDRV_Count_t *bytesRemaining); - -UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *bytesSent, - UARTDRV_Count_t *bytesRemaining); - -uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle); - -uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback); - -Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback); - -Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count); - -UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t maxLength); - -Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type); - -Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle); - -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle); - -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle); - -Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); - -Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); - -Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void); -#endif - -/** @} (end addtogroup uartdrv) */ - -#ifdef __cplusplus -} -#endif -#endif // UARTDRV_H +/***************************************************************************//** + * @file + * @brief UARTDRV API definition. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef UARTDRV_H +#define UARTDRV_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#include "em_device.h" +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#include "em_usart.h" +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) +#include "em_leuart.h" +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + +#if (_SILICON_LABS_32B_SERIES > 2) +#define UARTDRV_USE_PERIPHERAL +#include "sl_peripheral_eusart.h" +#else +#include "em_eusart.h" +#endif +#endif + +#if defined(UARTDRV_USE_PERIPHERAL) +#define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 0 // TODO (PLATFORM_MTL-8363): Remove when sl_gpio will be used. +#include "sl_peripheral_gpio.h" +#else +#include "em_gpio.h" +#endif + +#include "em_cmu.h" +#include "ecode.h" +#include "uartdrv_config.h" +#include "dmadrv.h" +#include "sl_enum.h" +#include "sl_sleeptimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup uartdrv + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup uartdrv_error_codes Error Codes + * @{ + ******************************************************************************/ +#define ECODE_EMDRV_UARTDRV_OK (ECODE_OK) ///< A successful return value. +#define ECODE_EMDRV_UARTDRV_WAITING (ECODE_EMDRV_UARTDRV_BASE | 0x00000001) ///< An operation is waiting in queue. +#define ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000002) ///< An illegal UART handle. +#define ECODE_EMDRV_UARTDRV_PARAM_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x00000003) ///< An illegal input parameter. +#define ECODE_EMDRV_UARTDRV_BUSY (ECODE_EMDRV_UARTDRV_BASE | 0x00000004) ///< The UART port is busy. +#define ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION (ECODE_EMDRV_UARTDRV_BASE | 0x00000005) ///< An illegal operation on the UART port. +#define ECODE_EMDRV_UARTDRV_IDLE (ECODE_EMDRV_UARTDRV_BASE | 0x00000008) ///< No UART transfer is in progress. +#define ECODE_EMDRV_UARTDRV_ABORTED (ECODE_EMDRV_UARTDRV_BASE | 0x00000009) ///< A UART transfer has been aborted. +#define ECODE_EMDRV_UARTDRV_QUEUE_FULL (ECODE_EMDRV_UARTDRV_BASE | 0x0000000A) ///< A UART operation queue is full. +#define ECODE_EMDRV_UARTDRV_QUEUE_EMPTY (ECODE_EMDRV_UARTDRV_BASE | 0x0000000B) ///< A UART operation queue is empty. +#define ECODE_EMDRV_UARTDRV_PARITY_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000C) ///< A UART parity error frame. Data is ignored. +#define ECODE_EMDRV_UARTDRV_FRAME_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000D) ///< A UART frame error. Data is ignored. +#define ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000E) ///< Unable to allocate DMA channels. +#define ECODE_EMDRV_UARTDRV_CLOCK_ERROR (ECODE_EMDRV_UARTDRV_BASE | 0x0000000F) ///< Unable to set a desired baudrate. +/** @} (end addtogroup error codes) */ + +/***************************************************************************//** + * @addtogroup uartdrv_status_codes Status Codes + * @{ + ******************************************************************************/ +#define UARTDRV_STATUS_RXEN (1 << 0) ///< The receiver is enabled. +#define UARTDRV_STATUS_TXEN (1 << 1) ///< The transmitter is enabled. +#define UARTDRV_STATUS_RXBLOCK (1 << 3) ///< The receiver is blocked; incoming frames will be discarded. +#define UARTDRV_STATUS_TXTRI (1 << 4) ///< The transmitter is tristated. +#define UARTDRV_STATUS_TXC (1 << 5) ///< A transmit operation is complete. No more data is available in the transmit buffer and shift register. +#define UARTDRV_STATUS_TXBL (1 << 6) ///< The transmit buffer is empty. +#define UARTDRV_STATUS_RXDATAV (1 << 7) ///< Data is available in the receive buffer. +#define UARTDRV_STATUS_RXFULL (1 << 8) ///< The receive buffer is full. +#if defined(EUSART_STATUS_TXCANDTXIDLE) +#define UARTDRV_STATUS_TXCANDTXIDLE (1 << 9) ///< Set when both TXC and TXIDLE are set. +#endif +#define UARTDRV_STATUS_TXIDLE (1 << 13) ///< The transmitter is idle. +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +#define UARTDRV_STATUS_RXIDLE (1 << 12) ///< The Receiver is idle. +#endif +/** @} (end addtogroup status codes) */ + +typedef uint32_t UARTDRV_Count_t; ///< A UART transfer count +typedef uint32_t UARTDRV_Status_t; ///< A UART status return type. Bitfield of UARTDRV_STATUS_* values. + +/** + * @enum UARTDRV_FlowControlType_t + * @brief UARTDRV Flow Control method. + */ +SL_ENUM(UARTDRV_FlowControlType_t) { + uartdrvFlowControlNone = 0, ///< None + uartdrvFlowControlSw = 1, ///< Software XON/XOFF + uartdrvFlowControlHw = 2, ///< nRTS/nCTS hardware handshake + uartdrvFlowControlHwUart = 3 ///< UART peripheral controls nRTS/nCTS +}; + +/// Flow Control state +SL_ENUM(UARTDRV_FlowControlState_t) { + uartdrvFlowControlOn = 0, ///< XON or nRTS/nCTS low + uartdrvFlowControlOff = 1, ///< XOFF or nRTS/nCTS high + uartdrvFlowControlAuto = 2 ///< This driver controls the state. +}; + +/// Transfer abort type +SL_ENUM(UARTDRV_AbortType_t) { + uartdrvAbortTransmit = 1, ///< Abort current and queued transmit operations + uartdrvAbortReceive = 2, ///< Abort current and queued receive operations + uartdrvAbortAll = 3 ///< Abort all current and queued operations +}; + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +/// Type of a UART peripheral +SL_ENUM(UARTDRV_UartType_t) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + uartdrvUartTypeUart = 0, ///< USART/UART peripheral +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + uartdrvUartTypeLeuart = 1 ///< LEUART peripheral +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + uartdrvUartTypeEuart = 2 ///< EUART peripheral +#endif +}; +/// @endcond + +struct UARTDRV_HandleData; + +/***************************************************************************//** + * @brief + * UARTDRV transfer completion callback function. + * + * @details + * Called when a transfer is complete. An + * application should check the transferStatus and itemsTransferred values. + * + * @param[in] handle + * The UARTDRV device handle used to start the transfer. + * + * @param[in] transferStatus + * Completion status of the transfer operation. + * + * @param[in] data + * A pointer to the transfer data buffer. + * + * @param[in] transferCount + * A number of bytes transferred. + ******************************************************************************/ +typedef void (*UARTDRV_Callback_t)(struct UARTDRV_HandleData *handle, + Ecode_t transferStatus, + uint8_t *data, + UARTDRV_Count_t transferCount); + +/// UART transfer buffer +typedef struct { + uint8_t *data; ///< Transfer data buffer + UARTDRV_Count_t transferCount; ///< Transfer item count + volatile UARTDRV_Count_t itemsRemaining; ///< Transfer items remaining + UARTDRV_Callback_t callback; ///< Completion callback + Ecode_t transferStatus; ///< Completion status of the transfer operation +} UARTDRV_Buffer_t; + +/// Transfer operation FIFO queue typedef +typedef struct { + volatile uint16_t head; ///< An index of the next byte to send. + volatile uint16_t tail; ///< An index of the location to enqueue the next message. + volatile uint16_t used; ///< A number of bytes queued. + const uint16_t size; ///< FIFO size. + UARTDRV_Buffer_t fifo[1]; ///< FIFO of queued data. Actual size varies. +} UARTDRV_Buffer_FifoQueue_t; + +/// Macros to define FIFO and buffer queues. typedef can't be used because the size +/// of the FIFO array in the queues can change. +#define DEFINE_BUF_QUEUE(qSize, qName) \ + typedef struct { \ + uint16_t head; \ + uint16_t tail; \ + volatile uint16_t used; \ + const uint16_t size; \ + UARTDRV_Buffer_t fifo[qSize]; \ + } _##qName; \ + static volatile _##qName qName = \ + { \ + .head = 0, \ + .tail = 0, \ + .used = 0, \ + .size = qSize, \ + } + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/** + * @struct UARTDRV_InitUart_t + * @brief A UART driver instance initialization structure. + * LEUART driver instance initialization structure. + * Contains a number of UARTDRV configuration options. + * It is required for driver instance initialization. + * This structure is passed to @ref UARTDRV_Init() when initializing a UARTDRV + * instance. + */ +typedef struct { + USART_TypeDef *port; ///< The peripheral used for UART + uint32_t baudRate; ///< UART baud rate +#if defined(_USART_ROUTELOC0_MASK) + uint8_t portLocationTx; ///< A location number for UART Tx pin. + uint8_t portLocationRx; ///< A location number for UART Rx pin. +#elif defined(_USART_ROUTE_MASK) + uint8_t portLocation; ///< A location number for UART pins. +#elif defined(_GPIO_USART_ROUTEEN_MASK) + GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. + GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. + uint8_t txPin; ///< Pin number for UART Tx. + uint8_t rxPin; ///< Pin number for UART Rx. + uint8_t uartNum; ///< UART instance number. +#endif + USART_Stopbits_TypeDef stopBits; ///< A number of stop bits. + USART_Parity_TypeDef parity; ///< Parity configuration. + USART_OVS_TypeDef oversampling; ///< Oversampling mode. +#if defined(USART_CTRL_MVDIS) + bool mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#endif + UARTDRV_FlowControlType_t fcType; ///< Flow control mode. + GPIO_Port_TypeDef ctsPort; ///< A CTS pin port number. + uint8_t ctsPin; ///< A CTS pin number. + GPIO_Port_TypeDef rtsPort; ///< An RTS pin port number. + uint8_t rtsPin; ///< An RTS pin number. + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< A receive operation queue. + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< T transmit operation queue. +#if defined(_USART_ROUTELOC1_MASK) + uint8_t portLocationCts; ///< A location number for the UART CTS pin. + uint8_t portLocationRts; ///< A location number for the UART RTS pin. +#endif +} UARTDRV_InitUart_t; +#endif + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +/** + * @struct UARTDRV_InitLeuart_t + * @brief LEUART driver instance initialization structure. + * LEUART driver instance initialization structure. + * Contains a number of UARTDRV configuration options. + * It is required to initialize a driver instance. + * This structure is passed to @ref UARTDRV_InitLeuart() when initializing a UARTDRV + * instance. + */ +typedef struct { + LEUART_TypeDef *port; ///< The peripheral used for LEUART + uint32_t baudRate; ///< UART baud rate +#if defined(_LEUART_ROUTELOC0_MASK) + uint8_t portLocationTx; ///< Location number for LEUART Tx pin. + uint8_t portLocationRx; ///< Location number for LEUART Rx pin. +#else + uint8_t portLocation; ///< Location number for LEUART pins +#endif + LEUART_Stopbits_TypeDef stopBits; ///< Number of stop bits + LEUART_Parity_TypeDef parity; ///< Parity configuration + UARTDRV_FlowControlType_t fcType; ///< Flow control mode + GPIO_Port_TypeDef ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + GPIO_Port_TypeDef rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue +} UARTDRV_InitLeuart_t; +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +/// UART driver instance initialization structure. +/// Contains a number of UARTDRV configuration options. +/// It is required to initialize a driver instance. +/// This structure is passed to @ref UARTDRV_InitEuart() when initializing a UARTDRV +typedef struct { + EUSART_TypeDef *port; ///< The peripheral used for EUART + bool useLowFrequencyMode; ///< Clock configuration of the EUART + uint32_t baudRate; ///< EUART baud rate +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t txPort; ///< Port for UART Tx pin. + sl_gpio_port_t rxPort; ///< Port for UART Rx pin. +#else + GPIO_Port_TypeDef txPort; ///< Port for UART Tx pin. + GPIO_Port_TypeDef rxPort; ///< Port for UART Rx pin. +#endif + uint8_t txPin; ///< Pin number for UART Tx. + uint8_t rxPin; ///< Pin number for UART Rx. + uint8_t uartNum; ///< EUART instance number. +#if defined(UARTDRV_USE_PERIPHERAL) + sl_hal_eusart_stop_bits_t stopBits; ///< Number of stop bits + sl_hal_eusart_parity_t parity; ///< Parity configuration + sl_hal_eusart_ovs_t oversampling; ///< Oversampling mode. + sl_hal_eusart_majority_vote_t mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#else + EUSART_Stopbits_TypeDef stopBits; ///< Number of stop bits + EUSART_Parity_TypeDef parity; ///< Parity configuration + EUSART_OVS_TypeDef oversampling; ///< Oversampling mode. + EUSART_MajorityVote_TypeDef mvdis; ///< Majority Vote Disable for 16x, 8x and 6x oversampling modes. +#endif + UARTDRV_FlowControlType_t fcType; ///< Flow control mode +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + sl_gpio_port_t rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number +#else + GPIO_Port_TypeDef ctsPort; ///< CTS pin port number + uint8_t ctsPin; ///< CTS pin number + GPIO_Port_TypeDef rtsPort; ///< RTS pin port number + uint8_t rtsPin; ///< RTS pin number +#endif + UARTDRV_Buffer_FifoQueue_t *rxQueue; ///< Receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; ///< Transmit operation queue +} UARTDRV_InitEuart_t; +#endif + +/// A UART driver instance handle data structure. +/// Allocated by the application using UARTDRV. +/// Several concurrent driver instances may exist in an application. The application must +/// not modify the contents of this handle and should not depend on its values. +typedef struct UARTDRV_HandleData{ + /// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + union { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + USART_TypeDef * uart; +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + LEUART_TypeDef * leuart; +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + EUSART_TypeDef * euart; +#endif + void * __reserved_space; + } peripheral; + uint8_t uartNum; // UART instance number + unsigned int txDmaCh; // A DMA ch assigned to Tx + unsigned int rxDmaCh; // A DMA ch assigned to Rx + DMADRV_PeripheralSignal_t txDmaSignal; // A DMA Tx trigger source signal + DMADRV_PeripheralSignal_t rxDmaSignal; // A DMA Rx trigger source signal + UARTDRV_FlowControlState_t fcSelfState; // A current self flow control state + UARTDRV_FlowControlState_t fcSelfCfg; // A self flow control override configuration + UARTDRV_FlowControlState_t fcPeerState; // A current peer flow control state +#if defined(UARTDRV_USE_PERIPHERAL) + sl_gpio_port_t txPort; // A Tx pin port number + sl_gpio_port_t rxPort; // An Rx pin port number + sl_gpio_port_t ctsPort; // A CTS pin port number + sl_gpio_port_t rtsPort; // An RTS pin port number +#else + GPIO_Port_TypeDef txPort; // A Tx pin port number + GPIO_Port_TypeDef rxPort; // An Rx pin port number + GPIO_Port_TypeDef ctsPort; // A CTS pin port number + GPIO_Port_TypeDef rtsPort; // An RTS pin port number +#endif + uint8_t txPin; // A Tx pin number + uint8_t rxPin; // An Tx pin number + uint8_t ctsPin; // A CTS pin number + uint8_t rtsPin; // An RTS pin number + CMU_Clock_TypeDef uartClock; // A clock source select + UARTDRV_Buffer_FifoQueue_t *rxQueue; // A receive operation queue + UARTDRV_Buffer_FifoQueue_t *txQueue; // A transmit operation queue + volatile bool rxDmaActive; // A receive DMA is currently active + volatile bool txDmaActive; // A transmit DMA is currently active + volatile uint8_t txDmaPaused; // A transmit DMA pause counter + bool IgnoreRestrain; // A transmit does not respect uartdrvFlowControlOff + bool hasTransmitted; // Indicates whether the handle has transmitted data + UARTDRV_FlowControlType_t fcType; // A flow control mode + UARTDRV_UartType_t type; // A type of UART + volatile int em1RequestCount; // A EM1 request count for the handle + sl_sleeptimer_timer_handle_t delayedTxTimer; // A timer to wait for the last byte out + size_t sleep; // Sleep state on isr return + /// @endcond +} UARTDRV_HandleData_t; + +/// Handle pointer +typedef UARTDRV_HandleData_t * UARTDRV_Handle_t; + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t * initData); +#endif + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t * initData); +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t * initData); +#endif +Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle); + +UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle); + +UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *bytesReceived, + UARTDRV_Count_t *bytesRemaining); + +UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *bytesSent, + UARTDRV_Count_t *bytesRemaining); + +uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle); + +uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback); + +Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback); + +Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count); + +UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t maxLength); + +Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type); + +Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle); + +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle); + +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle); + +Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); + +Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state); + +Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void); +#endif + +/** @} (end addtogroup uartdrv) */ + +#ifdef __cplusplus +} +#endif +#endif // UARTDRV_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c index f2142db..68021a7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emdrv/uartdrv/src/uartdrv.c @@ -1,3328 +1,3328 @@ -/***************************************************************************//** - * @file - * @brief UARTDRV API implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#define CURRENT_MODULE_NAME "UARTDRV" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#include "uartdrv.h" -#include "em_device.h" -#include "em_core.h" -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -#include "gpiointerrupt.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#include "sl_sleeptimer.h" -#endif - -#include - -//**************************************************************************** - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(_USART_ROUTEPEN_CTSPEN_MASK) -#define UART_HW_FLOW_CONTROL_SUPPORT -#elif (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(USART_CTRLX_CTSEN) -#define UART_HW_FLOW_CONTROL_SUPPORT -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -#define HANDLES_ARE_AVAILABLE 1 -#elif defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -#define HANDLES_ARE_AVAILABLE 1 -#else -#define HANDLES_ARE_AVAILABLE 0 -#endif - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#if defined(DMA_PRESENT) && (DMA_COUNT == 1) -#define UART_DMA_IRQ DMA_IRQn -#define UART_DMA_IRQHANDLER() DMA_IRQHandler() -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES <= 2) -#define UART_DMA_IRQ LDMA_IRQn -#define UART_DMA_IRQHANDLER() LDMA_IRQHandler() -#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES > 2) -#define UART_DMA_IRQ LDMA_CHNL0_IRQn -#define UART_DMA_IRQHANDLER() LDMA_CHNL0_IRQHandler() -#else -#error "No valid UARTDRV DMA engine defined." -#endif - -// UARTDRV use low-level drivers from platform/peripheral. -#if defined(UARTDRV_USE_PERIPHERAL) - -#define uartdrv_gpio_port_t sl_gpio_port_t -#define UARTDRV_GPIO_MODE_DISABLED SL_GPIO_MODE_DISABLED -#define UARTDRV_GPIO_MODE_INPUT SL_GPIO_MODE_INPUT -#define UARTDRV_GPIO_MODE_INPUT_PULL SL_GPIO_MODE_INPUT_PULL -#define UARTDRV_GPIO_MODE_PUSH_PULL SL_GPIO_MODE_PUSH_PULL - -#define uartdrv_gpio_get_pin_input(port, pin) sl_gpio_get_pin_input(port, pin) -#define uartdrv_gpio_set_pin_output(port, pin) sl_gpio_set_pin_output(port, pin) -#define uartdrv_gpio_clear_pin_output(port, pin) sl_gpio_clear_pin_output(port, pin) -#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) sl_gpio_set_pin_mode(port, pin, mode, output) -#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ - sl_gpio_configure_external_interrupt(port, \ - pin, \ - intNo, \ - (risingEdge * SL_GPIO_INTERRUPT_RISING_EDGE \ - & fallingEdge * SL_GPIO_INTERRUPT_FALLING_EDGE \ - & enable * SL_GPIO_INTERRUPT_ENABLE)) - -#define uartdrv_eusart_data_bits_t sl_hal_eusart_data_bits_t -#define uartdrv_eusart_stop_bits_t sl_hal_eusart_stop_bits_t -#define uartdrv_eusart_parity_t sl_hal_eusart_parity_t -#define uartdrv_eusart_ovs_t sl_hal_eusart_ovs_t -#define uartdrv_eusart_majority_vote_t sl_hal_eusart_majority_vote_t - -#define UARTDRV_EUSART_DISABLE 0x0 -#define UARTDRV_EUSART_ENABLE_RX (EUSART_CMD_RXEN | EUSART_CMD_TXDIS) -#define UARTDRV_EUSART_ENABLE_TX (EUSART_CMD_TXEN | EUSART_CMD_RXDIS) -#define UARTDRV_EUSART_ENABLE (EUSART_CMD_RXEN | EUSART_CMD_TXEN) - -#define uartdrv_eusart_get_status(eusart) sl_hal_eusart_get_status(eusart) -#define uartdrv_eusart_tx(eusart, data) sl_hal_eusart_tx(eusart, data) -#define uartdrv_eusart_reset(eusart) sl_hal_eusart_reset(eusart) -#define uartdrv_eusart_enable(eusart, enable) do { if (enable == UARTDRV_EUSART_DISABLE) \ - { sl_hal_eusart_disable(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE_RX) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_disable_tx(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE_TX) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_tx(eusart); sl_hal_eusart_disable_rx(eusart); } \ - else if (enable == UARTDRV_EUSART_ENABLE) \ - { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_enable_tx(eusart); } } while (0) - -// UARTDRV use low-level drivers from platform/emlib. -#else -#define uartdrv_gpio_port_t GPIO_Port_TypeDef - -#define UARTDRV_GPIO_MODE_DISABLED gpioModeDisabled -#define UARTDRV_GPIO_MODE_INPUT gpioModeInput -#define UARTDRV_GPIO_MODE_INPUT_PULL gpioModeInputPull -#define UARTDRV_GPIO_MODE_PUSH_PULL gpioModePushPull - -#define uartdrv_gpio_get_pin_input(port, pin) GPIO_PinInGet(port, pin) -#define uartdrv_gpio_set_pin_output(port, pin) GPIO_PinOutSet(port, pin) -#define uartdrv_gpio_clear_pin_output(port, pin) GPIO_PinOutClear(port, pin) -#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) GPIO_PinModeSet(port, pin, mode, output) -#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ - GPIO_ExtIntConfig(port, pin, intNo, risingEdge, fallingEdge, enable) - -#define uartdrv_eusart_data_bits_t EUSART_Databits_TypeDef -#define uartdrv_eusart_stop_bits_t EUSART_Stopbits_TypeDef -#define uartdrv_eusart_parity_t EUSART_Parity_TypeDef -#define uartdrv_eusart_ovs_t EUSART_OVS_TypeDef -#define uartdrv_eusart_majority_vote_t EUSART_MajorityVote_TypeDef - -#define UARTDRV_EUSART_DISABLE eusartDisable -#define UARTDRV_EUSART_ENABLE_RX eusartEnableRx -#define UARTDRV_EUSART_ENABLE_TX eusartEnableTx -#define UARTDRV_EUSART_ENABLE eusartEnable - -#define uartdrv_eusart_get_status(eusart) EUSART_StatusGet(eusart) -#define uartdrv_eusart_tx(eusart, data) EUSART_Tx(eusart, data) -#define uartdrv_eusart_reset(eusart) EUSART_Reset(eusart) -#define uartdrv_eusart_enable(eusart, enable) EUSART_Enable(eusart, enable) -#endif - -//**************************************************************************** - -#if (HANDLES_ARE_AVAILABLE) -static bool uartdrvHandleIsInitialized = false; -static UARTDRV_Handle_t uartdrvHandle[EMDRV_UARTDRV_MAX_DRIVER_INSTANCES]; -#endif -static bool enableRxWhenSleeping = UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION; - -//**************************************************************************** - -static bool ReceiveDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam); -static bool TransmitDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam); - -/***************************************************************************//** - * @brief Power management functions for the uartdrv. - ******************************************************************************/ -static void em1RequestAdd(UARTDRV_Handle_t handle) -{ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (handle->em1RequestCount == 0) { - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); - } - handle->em1RequestCount++; - CORE_EXIT_ATOMIC(); -#else - handle->em1RequestCount++; -#endif -} - -static void em1RequestRemove(UARTDRV_Handle_t handle) -{ - EFM_ASSERT(handle->em1RequestCount > 0); -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - handle->em1RequestCount--; - if (handle->em1RequestCount == 0) { - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); - } - CORE_EXIT_ATOMIC(); -#else - handle->em1RequestCount--; -#endif -} - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -static void emRequestInit(UARTDRV_Handle_t handle) -{ - handle->em1RequestCount = 0; -} -#endif - -static void emRequestDeinit(UARTDRV_Handle_t handle) -{ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - sl_status_t status; - bool running; - - CORE_ENTER_ATOMIC(); - status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); - if ((status == SL_STATUS_OK) && (running)) { - sl_sleeptimer_stop_timer(&handle->delayedTxTimer); - } - CORE_EXIT_ATOMIC(); -#endif - if (handle->em1RequestCount > 0) { - handle->em1RequestCount = 1; - em1RequestRemove(handle); - } -} - -/***************************************************************************//** - * @brief Get UARTDRV_Handle_t from GPIO pin number (HW FC CTS pin interrupt). - ******************************************************************************/ -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -static UARTDRV_Handle_t HwFcCtsIrqGetDrvHandle(uint32_t gpioPinNo) -{ - uint32_t i; - - for (i = 0; i < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; i++) { - if (uartdrvHandle[i]->ctsPin == gpioPinNo) { - return uartdrvHandle[i]; - } - } - return NULL; -} - -/***************************************************************************//** - * @brief Get CTS pin state. - ******************************************************************************/ -static UARTDRV_FlowControlState_t HwFcGetClearToSendPin(UARTDRV_Handle_t handle) -{ - if (handle->fcType == uartdrvFlowControlHw) { - return (UARTDRV_FlowControlState_t)uartdrv_gpio_get_pin_input(handle->ctsPort, handle->ctsPin); - } else { - return uartdrvFlowControlOn; - } -} - -/***************************************************************************//** - * @brief Manage CTS pin change. - ******************************************************************************/ -static void HwFcManageClearToSend(uint8_t gpioPinNo) -{ - UARTDRV_Handle_t handle = HwFcCtsIrqGetDrvHandle(gpioPinNo); - - if (handle && handle->fcType == uartdrvFlowControlHw) { - // If not auto mode, assign the CTS pin state to the self state - // If auto mode, also control UART Tx enable - handle->fcSelfState = HwFcGetClearToSendPin(handle); - // Only manage DMA if not already paused by SW - if (handle->fcSelfCfg == uartdrvFlowControlAuto && (handle->txDmaPaused == 0)) { - bool active = false; - Ecode_t status = DMADRV_TransferActive(handle->txDmaCh, &active); - if ((handle->fcSelfState == uartdrvFlowControlOn) || handle->IgnoreRestrain) { - handle->IgnoreRestrain = false; - DMADRV_ResumeTransfer(handle->txDmaCh); - } - // Only pause DMA if currently active - else if ((status == ECODE_EMDRV_DMADRV_OK) && active) { - DMADRV_PauseTransfer(handle->txDmaCh); - } - } - } -} - -static Ecode_t FcApplyState(UARTDRV_Handle_t handle) -{ - uint8_t fcSwCode; - - if (handle->fcType == uartdrvFlowControlHw) { - if (handle->fcSelfCfg == uartdrvFlowControlOn) { - // Assert nRTS (application control) - uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); - } else if (handle->fcSelfCfg == uartdrvFlowControlOff) { - // Deassert nRTS (application control) - uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); - } else { // Auto mode - if (handle->fcSelfState == uartdrvFlowControlOn) { - // Assert nRTS - uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); - } else { // Off - // Deassert nRTS - uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); - } - } - } else if (handle->fcType == uartdrvFlowControlSw) { - if (handle->fcSelfState == uartdrvFlowControlOn) { - fcSwCode = UARTDRV_FC_SW_XON; - // Pause transmit to ensure XON transmits immediately - UARTDRV_PauseTransmit(handle); - UARTDRV_ForceTransmit(handle, &fcSwCode, 1); - UARTDRV_ResumeTransmit(handle); - } else { - fcSwCode = UARTDRV_FC_SW_XOFF; - // Pause transmit to ensure XOFF transmits immediately - UARTDRV_PauseTransmit(handle); - UARTDRV_ForceTransmit(handle, &fcSwCode, 1); - UARTDRV_ResumeTransmit(handle); - } - } - return ECODE_EMDRV_UARTDRV_OK; -} -#else -// CTS pin should always read as uartdrvFlowControlOn when HW FC is disabled -#define HwFcGetClearToSendPin(x) uartdrvFlowControlOn -#endif /* EMDRV_UARTDRV_FLOW_CONTROL_ENABLE */ - -/***************************************************************************//** - * @brief Enqueue UART transfer buffer. - ******************************************************************************/ -static Ecode_t EnqueueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t *inputBuffer, - UARTDRV_Buffer_t **queueBuffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used >= queue->size) { - *queueBuffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_FULL; - } - memcpy((void *)&queue->fifo[queue->head], - (const void *)inputBuffer, - sizeof(UARTDRV_Buffer_t)); - *queueBuffer = &queue->fifo[queue->head]; - queue->head = (queue->head + 1) % queue->size; - queue->used++; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Dequeue UART transfer buffer. - ******************************************************************************/ -static Ecode_t DequeueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - queue->tail = (queue->tail + 1) % queue->size; - queue->used--; - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Get tail UART transfer buffer. - ******************************************************************************/ -static Ecode_t GetTailBuffer(UARTDRV_Buffer_FifoQueue_t *queue, - UARTDRV_Buffer_t **buffer) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (queue->used == 0) { - *buffer = NULL; - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; - } - *buffer = &queue->fifo[queue->tail]; - - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Enable UART transmitter. - ******************************************************************************/ -static void EnableTransmitter(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif // LEUART || EUART || EUSART - { - // Enable Tx - handle->peripheral.uart->CMD = USART_CMD_TXEN; - // Wait for Tx to be enabled - while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXENS)) { - } - - // Enable Tx route -#if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_TXPEN; -#elif defined(USART_ROUTE_TXPEN) - handle->peripheral.uart->ROUTE |= USART_ROUTE_TXPEN; -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; -#endif - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Enable Tx - handle->peripheral.leuart->CMD = LEUART_CMD_TXEN; - // Wait for Tx to be enabled - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS)) { - } - - // Enable Tx route -#if defined(LEUART_ROUTEPEN_TXPEN) - handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN; -#else - handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_TXPEN; -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); - } -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; -#endif - } -#endif -} - -/***************************************************************************//** - * @brief Disable UART transmitter. - ******************************************************************************/ -static void DisableTransmitter(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Disable Tx route -#if defined(USART_ROUTEPEN_TXPEN) - handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_TXPEN; -#elif defined(USART_ROUTE_TXPEN) - handle->peripheral.uart->ROUTE &= ~USART_ROUTE_TXPEN; -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; -#endif - // Disable Tx - handle->peripheral.uart->CMD = USART_CMD_TXDIS; - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Disable Tx route -#if defined(LEUART_ROUTEPEN_TXPEN) - handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_TXPEN; -#else - handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_TXPEN; -#endif - // Disable Tx - handle->peripheral.leuart->CMD = LEUART_CMD_TXDIS; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); - } -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; -#endif - } -#endif -} - -/***************************************************************************//** - * @brief Enable UART receiver. - ******************************************************************************/ -static void EnableReceiver(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Enable Rx - handle->peripheral.uart->CMD = USART_CMD_RXEN; - // Wait for Rx to be enabled - while (!(handle->peripheral.uart->STATUS & USART_STATUS_RXENS)) { - } - - // Enable Rx route -#if defined(USART_ROUTEPEN_RXPEN) - handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_RXPEN) - handle->peripheral.uart->ROUTE |= USART_ROUTE_RXPEN; -#elif defined(GPIO_USART_ROUTEEN_RXPEN) - GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; -#endif - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for previous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Enable Rx - handle->peripheral.leuart->CMD = LEUART_CMD_RXEN; - // Wait for Rx to be enabled - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS)) { - } - - // Enable Rx route -#if defined(LEUART_ROUTEPEN_RXPEN) - handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN; -#else - handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_RXPEN; -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); - } - } -#endif -} - -/***************************************************************************//** - * @brief Disable UART receiver. - ******************************************************************************/ -static void DisableReceiver(UARTDRV_Handle_t handle) -{ - if (false) { - } -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ - || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ - || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeUart) -#endif - { - // Disable Rx route -#if defined(USART_ROUTEPEN_RXPEN) - handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_RXPEN) - handle->peripheral.uart->ROUTE &= ~USART_ROUTE_RXPEN; -#elif defined(GPIO_USART_ROUTEEN_RXPEN) - GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; -#endif - // Disable Rx - handle->peripheral.uart->CMD = USART_CMD_RXDIS; - } -#endif // UART || USART -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - else if (handle->type == uartdrvUartTypeLeuart) { - // Wait for prevous register writes to sync - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Disable Rx route -#if defined(LEUART_ROUTEPEN_RXPEN) - handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_RXPEN; -#else - handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_RXPEN; -#endif - // Disable Rx - handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - else if (handle->type == uartdrvUartTypeEuart) { - if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); - } else { - uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); - } - } -#endif -} - -/***************************************************************************//** - * @brief Start a UART DMA receive operation. - ******************************************************************************/ -static void StartReceiveDma(UARTDRV_Handle_t handle, - UARTDRV_Buffer_t *buffer) -{ - void *rxPort = NULL; - - handle->rxDmaActive = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - rxPort = (void *)&(handle->peripheral.uart->RXDATA); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - rxPort = (void *)&(handle->peripheral.leuart->RXDATA); -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - rxPort = (void *)&(handle->peripheral.euart->RXDATA); -#endif - } else { - handle->rxDmaActive = false; - return; - } - - if (enableRxWhenSleeping) { - em1RequestAdd(handle); - } - DMADRV_PeripheralMemory(handle->rxDmaCh, - handle->rxDmaSignal, - buffer->data, - rxPort, - true, - buffer->transferCount, - dmadrvDataSize1, - ReceiveDmaComplete, - handle); -} - -/***************************************************************************//** - * @brief Start a UART DMA transmit operation. - ******************************************************************************/ -static void StartTransmitDma(UARTDRV_Handle_t handle, - UARTDRV_Buffer_t *buffer) -{ - void *txPort = NULL; - - handle->txDmaActive = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txPort = (void *)&(handle->peripheral.uart->TXDATA); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - // Set TX DMA wakeup request. Needed for transmit while in EM2. - handle->peripheral.leuart->CTRL |= LEUART_CTRL_TXDMAWU; - txPort = (void *)&(handle->peripheral.leuart->TXDATA); -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - txPort = (void *)&(handle->peripheral.euart->TXDATA); -#endif - } else { - handle->txDmaActive = false; - return; - } - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - CORE_DECLARE_IRQ_STATE; - sl_status_t status; - bool running; - - CORE_ENTER_ATOMIC(); - status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); - if ((status == 0) && (running)) { - sl_sleeptimer_stop_timer(&handle->delayedTxTimer); - em1RequestRemove(handle); - } - CORE_EXIT_ATOMIC(); -#if !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif -#endif - - em1RequestAdd(handle); - DMADRV_MemoryPeripheral(handle->txDmaCh, - handle->txDmaSignal, - txPort, - buffer->data, - true, - buffer->transferCount, - dmadrvDataSize1, - TransmitDmaComplete, - handle); -} - -/***************************************************************************//** - * @brief DMA transfer completion callback. Called by the DMA interrupt handler. - ******************************************************************************/ -static bool ReceiveDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam) -{ - CORE_DECLARE_IRQ_STATE; - UARTDRV_Handle_t handle; - UARTDRV_Buffer_t *buffer; - Ecode_t status; - (void)channel; - (void)sequenceNo; - handle = (UARTDRV_Handle_t)userParam; - status = GetTailBuffer(handle->rxQueue, &buffer); - - if (enableRxWhenSleeping) { - em1RequestRemove(handle); - } - - // If an abort was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return true; - } - - EFM_ASSERT(buffer != NULL); - -#if defined(USART_IF_FERR) - if (handle->type == uartdrvUartTypeUart - && (handle->peripheral.uart->IF & USART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; -#if defined(USART_HAS_SET_CLEAR) - handle->peripheral.uart->IF_CLR = USART_IF_FERR; -#else - handle->peripheral.uart->IFC = USART_IFC_FERR; -#endif - } else -#endif -#if defined(USART_IF_PERR) - if (handle->type == uartdrvUartTypeUart - && (handle->peripheral.uart->IF & USART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; -#if defined(USART_HAS_SET_CLEAR) - handle->peripheral.uart->IF_CLR = USART_IF_PERR; -#else - handle->peripheral.uart->IFC = USART_IFC_PERR; -#endif - } else -#endif -#if defined(LEUART_IF_FERR) - if (handle->type == uartdrvUartTypeLeuart - && (handle->peripheral.leuart->IF & LEUART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.leuart->IFC = LEUART_IFC_FERR; - } else -#endif -#if defined(LEUART_IF_PERR) - if (handle->type == uartdrvUartTypeLeuart - && (handle->peripheral.leuart->IF & LEUART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.leuart->IFC = LEUART_IFC_PERR; - } else -#endif -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) - if (handle->type == uartdrvUartTypeEuart - && (handle->peripheral.euart->IF & EUSART_IF_FERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.euart->IF_CLR = EUSART_IF_FERR; - } else if (handle->type == uartdrvUartTypeEuart - && (handle->peripheral.euart->IF & EUSART_IF_PERR)) { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; - buffer->itemsRemaining = 0; - handle->peripheral.euart->IF_CLR = EUSART_IF_PERR; - } else -#endif - { - buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; - buffer->itemsRemaining = 0; - } - - CORE_ENTER_ATOMIC(); - - if (buffer->callback != NULL) { - buffer->callback(handle, buffer->transferStatus, buffer->data, buffer->transferCount - buffer->itemsRemaining); - } - // Dequeue the current tail Rx operation, check if more in queue - DequeueBuffer(handle->rxQueue, &buffer); - - if (handle->rxQueue->used > 0) { - GetTailBuffer(handle->rxQueue, &buffer); - StartReceiveDma(handle, buffer); - } else { -#if EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcSelfState = uartdrvFlowControlOff; - FcApplyState(handle); -#endif - handle->rxDmaActive = false; - - if (handle->fcType != uartdrvFlowControlHwUart) { - DisableReceiver(handle); - } - } - CORE_EXIT_ATOMIC(); - return true; -} - -/***************************************************************************//** - * @brief Calculate the number of sleeptimer ticks to flush the uart tx buffers. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -static uint32_t calculateSleeptimerTicksToFlushTxBuffers(UARTDRV_Handle_t handle) -{ - uint32_t baud = 0; - uint32_t ticks = 0; - - switch (handle->type) { -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - case uartdrvUartTypeLeuart: - baud = LEUART_BaudrateGet(handle->peripheral.leuart); - break; -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - case uartdrvUartTypeEuart: - baud = EUSART_BaudrateGet(handle->peripheral.euart); - break; -#endif -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - case uartdrvUartTypeUart: - default: - baud = USART_BaudrateGet(handle->peripheral.uart); - break; -#endif - } - - if (baud != 0) { // Avoid division by 0 - // Calculate the number of sleeptimer ticks for: - // 3 bytes: two in FIFO and one in shift register. - // 12 bits pr byte: one start bit, 8 data bits, parity and 2 stop bits. - ticks = (sl_sleeptimer_get_timer_frequency() * 3 * 12) / baud; - // Round up. - ticks++; - } - - return ticks; -} -#endif - -/***************************************************************************//** - * @brief Delayed transmit complete timer callback. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -static void TransmitDmaCompleteDelayed(sl_sleeptimer_timer_handle_t *timer_handle, void *userParam) -{ - (void)timer_handle; - UARTDRV_Handle_t uartdrv_handle = (UARTDRV_Handle_t)userParam; - uint32_t reg; - bool txComplete = false; - - // Check if transmit is completed by checking the uart registers. - switch (uartdrv_handle->type) { -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - case uartdrvUartTypeLeuart: - reg = uartdrv_handle->peripheral.leuart->STATUS; - txComplete = reg & LEUART_STATUS_TXC; - break; -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - case uartdrvUartTypeEuart: - reg = uartdrv_handle->peripheral.euart->STATUS; - txComplete = reg & EUSART_STATUS_TXC; - break; -#endif -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - case uartdrvUartTypeUart: - default: - reg = uartdrv_handle->peripheral.uart->STATUS; - txComplete = reg & USART_STATUS_TXC; - break; -#endif - } - - if (txComplete) { - // Remove the power manager request if completed. - em1RequestRemove(uartdrv_handle); -#if !defined(SL_CATALOG_KERNEL_PRESENT) - uartdrv_handle->sleep = SL_POWER_MANAGER_SLEEP; -#endif - } else { - // Restart the timer if not completed. - // May be the case if flow control is used. - uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(uartdrv_handle); - sl_sleeptimer_start_timer(&uartdrv_handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); - } -} -#endif - -/***************************************************************************//** - * @brief DMA transfer completion callback. Called by the DMA interrupt handler. - ******************************************************************************/ -static bool TransmitDmaComplete(unsigned int channel, - unsigned int sequenceNo, - void *userParam) -{ - CORE_DECLARE_IRQ_STATE; - UARTDRV_Handle_t handle; - UARTDRV_Buffer_t *buffer; - Ecode_t status; - (void)channel; - (void)sequenceNo; - - handle = (UARTDRV_Handle_t)userParam; - status = GetTailBuffer(handle->txQueue, &buffer); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(handle); - sl_sleeptimer_start_timer(&handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); -#else - em1RequestRemove(handle); -#endif - - // If an abort was in progress when DMA completed, the ISR could be deferred - // until after the critical section. In this case, the buffers no longer - // exist, even though the DMA complete callback was called. - if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { - return true; - } - - EFM_ASSERT(buffer != NULL); - - buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; - buffer->itemsRemaining = 0; - - CORE_ENTER_ATOMIC(); - - if (buffer->callback != NULL) { - buffer->callback(handle, ECODE_EMDRV_UARTDRV_OK, buffer->data, buffer->transferCount); - } - // Dequeue the current tail Tx operation, check if more in queue - DequeueBuffer(handle->txQueue, &buffer); - - if (handle->txQueue->used > 0) { - GetTailBuffer(handle->txQueue, &buffer); - StartTransmitDma(handle, buffer); - } else { - handle->txDmaActive = false; -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) - if (handle->type == uartdrvUartTypeLeuart) { - // Clear TX DMA Wakeup request - handle->peripheral.leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; - } -#endif - } - CORE_EXIT_ATOMIC(); - return true; -} - -/***************************************************************************//** - * @brief Parameter checking function for blocking transfer API functions. - ******************************************************************************/ -static Ecode_t CheckParams(UARTDRV_Handle_t handle, void *data, uint32_t count) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if ((data == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - return ECODE_EMDRV_UARTDRV_OK; -} - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/***************************************************************************//** - * @brief Store U(S)ART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t * initData) -{ -#if defined(_USART_ROUTELOC0_MASK) - if (false) { -#if defined(USARTRF0) - } else if (handle->peripheral.uart == USARTRF0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocationRx); -#endif -#if defined(USARTRF1) - } else if (handle->peripheral.uart == USARTRF1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART0) - } else if (handle->peripheral.uart == USART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART1) - } else if (handle->peripheral.uart == USART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART1_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART2) - } else if (handle->peripheral.uart == USART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART2_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART2_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART3) - } else if (handle->peripheral.uart == USART3) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART3_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART3_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART3_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART3_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART4) - } else if (handle->peripheral.uart == USART4) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART4_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART4_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART4_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART4_RX_PIN(initData->portLocationRx); -#endif -#if defined(USART5) - } else if (handle->peripheral.uart == USART5) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART5_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART5_RX_PORT(initData->portLocationRx); - handle->txPin = AF_USART5_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_USART5_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART0) - } else if (handle->peripheral.uart == UART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART1) - } else if (handle->peripheral.uart == UART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART1_RX_PIN(initData->portLocationRx); -#endif -#if defined(UART2) - } else if (handle->peripheral.uart == UART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART2_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART2_RX_PORT(initData->portLocationRx); - handle->txPin = AF_UART2_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_UART2_RX_PIN(initData->portLocationRx); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_USART_ROUTE_MASK) - if (false) { -#if defined(USARTRF0) - } else if (handle->peripheral.uart == USARTRF0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocation); - handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocation); - handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocation); -#endif -#if defined(USARTRF1) - } else if (handle->peripheral.uart == USARTRF1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocation); - handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocation); - handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocation); -#endif -#if defined(USART0) - } else if (handle->peripheral.uart == USART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocation); - handle->txPin = AF_USART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART0_RX_PIN(initData->portLocation); -#endif -#if defined(USART1) - } else if (handle->peripheral.uart == USART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocation); - handle->txPin = AF_USART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART1_RX_PIN(initData->portLocation); -#endif -#if defined(USART2) - } else if (handle->peripheral.uart == USART2) { - handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocation); - handle->txPin = AF_USART2_TX_PIN(initData->portLocation); - handle->rxPin = AF_USART2_RX_PIN(initData->portLocation); -#endif -#if defined(UART0) - } else if (handle->peripheral.uart == UART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocation); - handle->txPin = AF_UART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_UART0_RX_PIN(initData->portLocation); -#endif -#if defined(UART1) - } else if (handle->peripheral.uart == UART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocation); - handle->txPin = AF_UART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_UART1_RX_PIN(initData->portLocation); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_GPIO_USART_ROUTEEN_MASK) - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; -#endif - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif // UART || USART - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief Store LEUART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t * initData) -{ -#if defined(_LEUART_ROUTELOC0_MASK) - if (false) { -#if defined(LEUART0) - } else if (handle->peripheral.leuart == LEUART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocationRx); - handle->txPin = AF_LEUART0_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocationRx); -#endif -#if defined(LEUART1) - } else if (handle->peripheral.leuart == LEUART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocationTx); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocationRx); - handle->txPin = AF_LEUART1_TX_PIN(initData->portLocationTx); - handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocationRx); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_USART_ROUTE_MASK) - if (false) { -#if defined(LEUART0) - } else if (handle->peripheral.leuart == LEUART0) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocation); - handle->txPin = AF_LEUART0_TX_PIN(initData->portLocation); - handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocation); -#endif -#if defined(LEUART1) - } else if (handle->peripheral.leuart == LEUART1) { - handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocation); - handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocation); - handle->txPin = AF_LEUART1_TX_PIN(initData->portLocation); - handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocation); -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - -#elif defined(_GPIO_USART_ROUTEEN_MASK) - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; -#endif - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) -/***************************************************************************//** - * @brief Store EUART GPIO pins into handle. - ******************************************************************************/ -static Ecode_t SetupGpioEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t * initData) -{ - handle->txPort = initData->txPort; - handle->txPin = initData->txPin; - handle->rxPort = initData->rxPort; - handle->rxPin = initData->rxPin; - - handle->ctsPort = initData->ctsPort; - handle->ctsPin = initData->ctsPin; - handle->rtsPort = initData->rtsPort; - handle->rtsPin = initData->rtsPin; - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief Configure/deconfigure U(S)ART GPIO pins. - ******************************************************************************/ -static Ecode_t ConfigGpio(UARTDRV_Handle_t handle, bool enable) -{ - if (enable) { - uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_PUSH_PULL, 1); - uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_INPUT_PULL, 1); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); - uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, true); - } else if (handle->fcType == uartdrvFlowControlHwUart) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); - } -#endif - } else { - uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_DISABLED, 0); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, false); - } else if (handle->fcType == uartdrvFlowControlHwUart) { - uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); - } -#endif - } - return ECODE_EMDRV_UARTDRV_OK; -} - -#if (HANDLES_ARE_AVAILABLE) -/***************************************************************************//** - * @brief Add handle to handle array. - ******************************************************************************/ -static Ecode_t addHandle(UARTDRV_Handle_t handle) -{ - bool handleIsSet; - uint32_t handleIdx; - - // Set handler pointer in handler array - if (!uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - uartdrvHandle[handleIdx] = NULL; - } - uartdrvHandleIsInitialized = true; - } - - // Check if its already in the array - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == handle) { - return ECODE_EMDRV_UARTDRV_OK; - } - } - - // Insert handle - handleIsSet = false; - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == NULL) { - uartdrvHandle[handleIdx] = handle; - handleIsSet = true; - break; - } - } - - if (!handleIsSet) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief Remove handle from handle array. - ******************************************************************************/ -static Ecode_t removeHandle(UARTDRV_Handle_t handle) -{ - uint32_t handleIdx; - - if (uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - if (uartdrvHandle[handleIdx] == handle) { - uartdrvHandle[handleIdx] = NULL; - break; - } - } - } - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief Initialize FIFO queues for a handle. - ******************************************************************************/ -static void InitializeQueues(UARTDRV_Handle_t handle, - UARTDRV_Buffer_FifoQueue_t * rxQueue, - UARTDRV_Buffer_FifoQueue_t * txQueue) -{ - handle->rxQueue = rxQueue; - handle->rxQueue->head = 0; - handle->rxQueue->tail = 0; - handle->rxQueue->used = 0; - handle->rxDmaActive = false; - - handle->txQueue = txQueue; - handle->txQueue->head = 0; - handle->txQueue->tail = 0; - handle->txQueue->used = 0; - handle->txDmaActive = false; - - handle->IgnoreRestrain = false; -} - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) -/***************************************************************************//** - * @brief Initialize GPIO-driven flow control. - ******************************************************************************/ -static void InitializeGpioFlowControl(UARTDRV_Handle_t handle) -{ - GPIOINT_CallbackRegister(handle->ctsPin, HwFcManageClearToSend); - GPIOINT_Init(); - handle->fcPeerState = uartdrvFlowControlOn; - handle->fcSelfState = uartdrvFlowControlOn; - handle->fcSelfCfg = uartdrvFlowControlAuto; - FcApplyState(handle); -} -#endif - -/***************************************************************************//** - * @brief Initialize DMA channels for a handle. - ******************************************************************************/ -static Ecode_t InitializeDma(UARTDRV_Handle_t handle) -{ - // Initialize DMA. - DMADRV_Init(); - - if (DMADRV_AllocateChannel(&handle->txDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { - return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; - } - - if (DMADRV_AllocateChannel(&handle->rxDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { - return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -/// @endcond - -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) -/***************************************************************************//** - * @brief - * Initialize a U(S)ART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitUart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, - const UARTDRV_InitUart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - emRequestInit(handle); - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - - handle->peripheral.uart = initData->port; - handle->type = uartdrvUartTypeUart; -#if defined(_GPIO_USART_ROUTEEN_MASK) - handle->uartNum = initData->uartNum; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(USART0) - } else if (initData->port == USART0) { - handle->uartClock = cmuClock_USART0; - handle->txDmaSignal = dmadrvPeripheralSignal_USART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART0_RXDATAV; -#endif -#if defined(USART1) - } else if (initData->port == USART1) { - handle->uartClock = cmuClock_USART1; - handle->txDmaSignal = dmadrvPeripheralSignal_USART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART1_RXDATAV; -#endif -#if defined(USART2) - } else if (initData->port == USART2) { - handle->uartClock = cmuClock_USART2; - handle->txDmaSignal = dmadrvPeripheralSignal_USART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART2_RXDATAV; -#endif -#if defined(USART3) - } else if (initData->port == USART3) { - handle->uartClock = cmuClock_USART3; - handle->txDmaSignal = dmadrvPeripheralSignal_USART3_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART3_RXDATAV; -#endif -#if defined(USART4) - } else if (initData->port == USART4) { - handle->uartClock = cmuClock_USART4; - handle->txDmaSignal = dmadrvPeripheralSignal_USART4_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART4_RXDATAV; -#endif -#if defined(USART5) - } else if (initData->port == USART5) { - handle->uartClock = cmuClock_USART5; - handle->txDmaSignal = dmadrvPeripheralSignal_USART5_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_USART5_RXDATAV; -#endif -#if defined(UART0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (initData->port == UART0) { - handle->uartClock = cmuClock_UART0; - handle->txDmaSignal = dmadrvPeripheralSignal_UART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART0_RXDATAV; -#endif -#if defined(UART1) - } else if (initData->port == UART1) { - handle->uartClock = cmuClock_UART1; - handle->txDmaSignal = dmadrvPeripheralSignal_UART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART1_RXDATAV; -#endif -#if defined(UART2) - } else if (initData->port == UART2) { - handle->uartClock = cmuClock_UART2; - handle->txDmaSignal = dmadrvPeripheralSignal_UART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_UART2_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - usartInit.baudrate = initData->baudRate; - usartInit.stopbits = initData->stopBits; - usartInit.parity = initData->parity; - usartInit.oversampling = initData->oversampling; -#if defined(USART_CTRL_MVDIS) - usartInit.mvdis = initData->mvdis; -#endif - - // UARTDRV is fixed at 8 bit frames. - usartInit.databits = (USART_Databits_TypeDef)USART_FRAME_DATABITS_EIGHT; - - // Enable clocks -#if defined(_CMU_HFPERCLKEN0_MASK) - CMU_ClockEnable(cmuClock_HFPER, true); -#endif - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(handle->uartClock, true); - - // Init U(S)ART to default async config. - // Rx/Tx enable is done on demand - usartInit.enable = usartDisable; - USART_InitAsync(initData->port, &usartInit); - -#if defined(USART_ROUTEPEN_TXPEN) - initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 - & ~(_USART_ROUTELOC0_TXLOC_MASK - | _USART_ROUTELOC0_RXLOC_MASK)) - | (initData->portLocationTx - << _USART_ROUTELOC0_TXLOC_SHIFT) - | (initData->portLocationRx - << _USART_ROUTELOC0_RXLOC_SHIFT); - - initData->port->ROUTEPEN = USART_ROUTEPEN_TXPEN - | USART_ROUTEPEN_RXPEN; -#elif defined(USART_ROUTE_TXPEN) - initData->port->ROUTE = USART_ROUTE_TXPEN - | USART_ROUTE_RXPEN - | (initData->portLocation - << _USART_ROUTE_LOCATION_SHIFT); -#elif defined(GPIO_USART_ROUTEEN_TXPEN) - GPIO->USARTROUTE[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN - | GPIO_USART_ROUTEEN_RXPEN; - GPIO->USARTROUTE[initData->uartNum].TXROUTE = - (initData->txPort << _GPIO_USART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_USART_TXROUTE_PIN_SHIFT); - GPIO->USARTROUTE[initData->uartNum].RXROUTE = - (initData->rxPort << _GPIO_USART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_USART_RXROUTE_PIN_SHIFT); -#endif - - if ((retVal = SetupGpioUart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - CORE_ENTER_ATOMIC(); - - // Configure hardware flow control pins and interrupt vectors -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHwUart) { -#if defined(UART_HW_FLOW_CONTROL_SUPPORT) -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) - initData->port->ROUTELOC1 = (initData->portLocationCts << _USART_ROUTELOC1_CTSLOC_SHIFT) - | (initData->portLocationRts << _USART_ROUTELOC1_RTSLOC_SHIFT); - initData->port->CTRLX |= USART_CTRLX_CTSEN; - initData->port->ROUTEPEN |= USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN; -#elif defined(USART_CTRLX_CTSEN) - GPIO->USARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; - initData->port->CTRLX_SET = USART_CTRLX_CTSEN; - GPIO->USARTROUTE_SET[initData->uartNum].RTSROUTE = - (initData->rtsPort << _GPIO_USART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_USART_RTSROUTE_PIN_SHIFT); - GPIO->USARTROUTE_SET[initData->uartNum].CTSROUTE = - (initData->ctsPort << _GPIO_USART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_USART_CTSROUTE_PIN_SHIFT); -#endif -#else - // Attempting to use USART hardware flow control on a device that does not - // support it. - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; -#endif - } else if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - - // Clear any false IRQ/DMA request - USART_IntClear(initData->port, ~0x0); - - // Enable Tx permanently as the Tx circuit consumes very little energy. - // Rx is enabled on demand as the Rx circuit consumes some energy due to - // continuous (over)sampling. - if (initData->fcType == uartdrvFlowControlHwUart) { - // Rx must be enabled permanently when using USART hw flow control - USART_Enable(initData->port, usartEnable); - } else { - USART_Enable(initData->port, usartEnableTx); - } - - // Discard false frames and/or IRQs - initData->port->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; - - // Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif // UART || USART - -#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Initialize a LEUART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitLeuart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, - const UARTDRV_InitLeuart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - LEUART_Init_TypeDef leuartInit = LEUART_INIT_DEFAULT; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - if (initData->fcType == uartdrvFlowControlHwUart) { - // LEUART doesn't support peripheral hw flow control - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - - handle->peripheral.leuart = initData->port; - handle->type = uartdrvUartTypeLeuart; -#if defined(_GPIO_USART_ROUTEEN_MASK) - handle->uartNum = initData->uartNum; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(LEUART0) - } else if (initData->port == LEUART0) { - handle->uartClock = cmuClock_LEUART0; - handle->txDmaSignal = dmadrvPeripheralSignal_LEUART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART0_RXDATAV; -#endif -#if defined(LEUART1) - } else if (initData->port == LEUART1) { - handle->uartClock = cmuClock_LEUART1; - handle->txDmaSignal = dmadrvPeripheralSignal_LEUART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART1_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - leuartInit.baudrate = initData->baudRate; - leuartInit.stopbits = initData->stopBits; - leuartInit.parity = initData->parity; - - // UARTDRV is fixed at 8 bit frames. - leuartInit.databits = (LEUART_Databits_TypeDef)LEUART_CTRL_DATABITS_EIGHT; - - // Enable clocks -#if defined(_CMU_HFPERCLKEN0_MASK) - CMU_ClockEnable(cmuClock_HFPER, true); -#endif - CMU_ClockEnable(cmuClock_GPIO, true); -#if defined(_CMU_HFBUSCLKEN0_MASK) || defined(CMU_HFCORECLKEN0_LE) - CMU_ClockEnable(cmuClock_HFLE, true); -#endif - - // Only try to use LF clock if LFXO or LFRCO is enabled and requested baudrate is low - if (CMU->STATUS & CMU_STATUS_LFXOENS - && (leuartInit.baudrate <= SystemLFXOClockGet())) { - CMU_CLOCK_SELECT_SET(LFB, LFXO); - } else if (CMU->STATUS & CMU_STATUS_LFRCOENS - && (leuartInit.baudrate <= SystemLFRCOClockGet())) { - CMU_CLOCK_SELECT_SET(LFB, LFRCO); - } else { - // Try to figure out the prescaler that will give us the best stability - CMU_CLOCK_SELECT_SET(LFB, HFCLKLE); - -#if defined(_SILICON_LABS_32B_SERIES_0) - // Attainable baudrate lies between refclk and refclk/128. For maximum - // accuracy, we want the reference clock to be as high as possible. - uint32_t refclk = CMU_ClockFreqGet(cmuClock_LFB); - uint8_t divisor = 0; - - while (leuartInit.baudrate <= (refclk >> (divisor + 7))) { - divisor++; - } - - // If we ran out of stretch on the clock division, error out. - if (divisor > (_CMU_LFBPRESC0_LEUART0_MASK >> _CMU_LFBPRESC0_LEUART0_SHIFT)) { - return ECODE_EMDRV_UARTDRV_CLOCK_ERROR; - } - CMU_ClockDivSet(handle->uartClock, (CMU_ClkDiv_TypeDef) (1 << divisor)); -#elif defined(_SILICON_LABS_32B_SERIES_1) - // Clock divider in LEUARTn is large enough for any baudrate. -#endif - } - - CMU_ClockEnable(handle->uartClock, true); - - // Init LEUART to default async config. - // Rx/Tx enable is done on demand - leuartInit.enable = leuartDisable; - LEUART_Init(initData->port, &leuartInit); - -#if defined(LEUART_ROUTEPEN_TXPEN) - initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 - & ~(_LEUART_ROUTELOC0_TXLOC_MASK - | _LEUART_ROUTELOC0_RXLOC_MASK)) - | (initData->portLocationTx - << _LEUART_ROUTELOC0_TXLOC_SHIFT) - | (initData->portLocationRx - << _LEUART_ROUTELOC0_RXLOC_SHIFT); - - initData->port->ROUTEPEN = LEUART_ROUTEPEN_TXPEN - | LEUART_ROUTEPEN_RXPEN; -#else - initData->port->ROUTE = LEUART_ROUTE_TXPEN - | LEUART_ROUTE_RXPEN - | (initData->portLocation - << _LEUART_ROUTE_LOCATION_SHIFT); -#endif - - if ((retVal = SetupGpioLeuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - CORE_ENTER_ATOMIC(); - - // Configure hardware flow control pins and interrupt vectors -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - - // Clear any false IRQ/DMA request - LEUART_IntClear(initData->port, ~0x0); - - // Enable Tx permanently as the Tx circuit consumes very little energy. - // Rx is enabled on demand as the Rx circuit consumes some energy due to - // continuous (over)sampling. - LEUART_Enable(initData->port, leuartEnableTx); - - // Wait for previous write (TXEN) to sync before clearing FIFOs - while ((initData->port->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - - // Discard false frames and/or IRQs - initData->port->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; - initData->port->CTRL |= LEUART_CTRL_RXDMAWU; - - // Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - // Wait for everything to be synchronized - while (initData->port->SYNCBUSY != 0U) { - } - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) || defined(DOXYGEN) - -/***************************************************************************//** - * @brief - * Initialize a EUART driver instance. - * - * @param[out] handle Pointer to a UARTDRV handle, refer to @ref - * UARTDRV_Handle_t. - * - * @param[in] initData Pointer to an initialization data structure, - * refer to @ref UARTDRV_InitEuart_t. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, - const UARTDRV_InitEuart_t *initData) -{ - Ecode_t retVal; - CORE_DECLARE_IRQ_STATE; - #if defined(UARTDRV_USE_PERIPHERAL) - sl_hal_eusart_uart_config_t uartInit = SL_HAL_EUSART_UART_INIT_DEFAULT_HF; - sl_hal_eusart_uart_advanced_config_t uartAdvancedInit = SL_HAL_EUSART_UART_ADVANCED_INIT_DEFAULT; - #else - EUSART_UartInit_TypeDef uartInit = EUSART_UART_INIT_DEFAULT_HF; - EUSART_AdvancedInit_TypeDef uartAdvancedInit = EUSART_ADVANCED_INIT_DEFAULT; - #endif - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - if (initData == NULL) { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - memset(handle, 0, sizeof(UARTDRV_HandleData_t)); - - handle->peripheral.euart = initData->port; - handle->type = uartdrvUartTypeEuart; - handle->uartNum = initData->uartNum; - -#if (HANDLES_ARE_AVAILABLE) - retVal = addHandle(handle); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } -#endif - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - handle->fcType = initData->fcType; -#else - // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE - handle->fcType = uartdrvFlowControlNone; -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) - handle->sleep = SL_POWER_MANAGER_IGNORE; -#endif - - // Set clocks and DMA requests according to available peripherals - if (false) { -#if defined(EUART0) - } else if (initData->port == EUART0) { - handle->uartClock = cmuClock_EUART0; - handle->txDmaSignal = dmadrvPeripheralSignal_EUART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUART0_RXDATAV; -#endif -#if defined(EUSART0) - } else if (initData->port == EUSART0) { - handle->uartClock = cmuClock_EUSART0; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART0_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART0_RXDATAV; -#endif -#if defined(EUSART1) - } else if (initData->port == EUSART1) { - handle->uartClock = cmuClock_EUSART1; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART1_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART1_RXDATAV; -#endif -#if defined(EUSART2) - } else if (initData->port == EUSART2) { - handle->uartClock = cmuClock_EUSART2; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART2_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART2_RXDATAV; -#endif -#if defined(EUSART3) - } else if (initData->port == EUSART3) { - handle->uartClock = cmuClock_EUSART3; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART3_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART3_RXDATAV; -#endif -#if defined(EUSART4) - } else if (initData->port == EUSART4) { - handle->uartClock = cmuClock_EUSART4; - handle->txDmaSignal = dmadrvPeripheralSignal_EUSART4_TXBL; - handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART4_RXDATAV; -#endif - } else { - return ECODE_EMDRV_UARTDRV_PARAM_ERROR; - } - - // Common configurations to all EUART/EUSART instances. - handle->txDmaActive = false; - handle->rxDmaActive = false; - - InitializeQueues(handle, initData->rxQueue, initData->txQueue); - - // Enable clocks. - CMU_ClockEnable(cmuClock_GPIO, true); - CMU_ClockEnable(handle->uartClock, true); - if (initData->useLowFrequencyMode) { - CMU_ClockEnable(cmuClock_LFRCO, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - CMU_ClockEnable(cmuClock_EM23GRPACLK, true); - CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFRCO); -#if defined(EUART_PRESENT) - CMU_CLOCK_SELECT_SET(EUART0, EM23GRPACLK); -#elif defined (EUSART_PRESENT) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM23GRPACLK); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ - || defined(_SILICON_LABS_32B_SERIES_3) - CMU_CLOCK_SELECT_SET(EUSART0CLK, LFRCO); -#else - #error "Please assign a LF clock to EUSART instance" -#endif - } else { -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - CMU_ClockEnable(cmuClock_EM01GRPACLK, true); -#if defined(EUART_PRESENT) - CMU_CLOCK_SELECT_SET(EUART0CLK, EM01GRPACLK); -#elif defined (EUSART_PRESENT) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPACLK); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ - || defined(_SILICON_LABS_32B_SERIES_3) - CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPCCLK); -#else - #error "Please assign a HF clock to EUSART instance" -#endif - } - -#if defined(EUART_COUNT) && (EUART_COUNT > 0) - GPIO->EUARTROUTE->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; - GPIO->EUARTROUTE->TXROUTE = (initData->txPort - << _GPIO_EUART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_EUART_TXROUTE_PIN_SHIFT); - GPIO->EUARTROUTE->RXROUTE = (initData->rxPort - << _GPIO_EUART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_EUART_RXROUTE_PIN_SHIFT); -#elif defined(EUSART_COUNT) && (EUSART_COUNT > 0) - GPIO->EUSARTROUTE[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; - GPIO->EUSARTROUTE[initData->uartNum].TXROUTE = (initData->txPort - << _GPIO_EUSART_TXROUTE_PORT_SHIFT) - | (initData->txPin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); - GPIO->EUSARTROUTE[initData->uartNum].RXROUTE = (initData->rxPort - << _GPIO_EUSART_RXROUTE_PORT_SHIFT) - | (initData->rxPin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); - #endif - - if ((retVal = SetupGpioEuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - -#if defined(UARTDRV_USE_PERIPHERAL) - // UARTDRV is fixed at 8 bit frames. - uartInit.data_bits = SL_HAL_EUSART_DATA_BITS_8; - - uartInit.clock_div = sl_hal_eusart_uart_calculate_clock_div(CMU_ClockFreqGet(cmuClock_EUSART0), initData->baudRate, initData->oversampling); - uartInit.stop_bits = initData->stopBits; - uartInit.parity = initData->parity; - uartInit.oversampling = initData->oversampling; - uartInit.majority_vote = initData->mvdis; - - uartAdvancedInit.dma_wakeup_on_rx = true; - uartAdvancedInit.dma_wakeup_on_tx = false; - uartInit.advanced_config = &uartAdvancedInit; -#else - // UARTDRV is fixed at 8 bit frames. - uartInit.databits = eusartDataBits8; - - uartInit.baudrate = initData->baudRate; - uartInit.stopbits = initData->stopBits; - uartInit.parity = initData->parity; - uartInit.oversampling = initData->oversampling; - uartInit.majorityVote = initData->mvdis; - - uartAdvancedInit.dmaWakeUpOnRx = true; - uartAdvancedInit.dmaWakeUpOnTx = false; - uartInit.advancedSettings = &uartAdvancedInit; -#endif - - CORE_ENTER_ATOMIC(); - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (initData->fcType == uartdrvFlowControlHwUart) { -#if defined(EUART_PRESENT) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; - GPIO->EUARTROUTE_SET[0].RTSROUTE = - (initData->rtsPort << _GPIO_EUART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_EUART_RTSROUTE_PIN_SHIFT); - GPIO->EUARTROUTE_SET[0].CTSROUTE = - (initData->ctsPort << _GPIO_EUART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_EUART_CTSROUTE_PIN_SHIFT); -#elif defined(EUSART_PRESENT) - GPIO->EUSARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; - GPIO->EUSARTROUTE_SET[initData->uartNum].RTSROUTE = - (initData->rtsPort << _GPIO_EUSART_RTSROUTE_PORT_SHIFT) - | (initData->rtsPin << _GPIO_EUSART_RTSROUTE_PIN_SHIFT); - GPIO->EUSARTROUTE_SET[initData->uartNum].CTSROUTE = - (initData->ctsPort << _GPIO_EUSART_CTSROUTE_PORT_SHIFT) - | (initData->ctsPin << _GPIO_EUSART_CTSROUTE_PIN_SHIFT); -#endif - uartAdvancedInit.hwFlowControl = eusartHwFlowControlCtsAndRts; - } else if (initData->fcType == uartdrvFlowControlHw) { - InitializeGpioFlowControl(handle); - } -#endif - -#if defined(UARTDRV_USE_PERIPHERAL) - if (initData->useLowFrequencyMode) { - sl_hal_eusart_init_uart_lf(initData->port, &uartInit); - } else { - sl_hal_eusart_init_uart_hf(initData->port, &uartInit); - } - - // Set Tx enable to follow USART implementation. - uartdrv_eusart_enable(initData->port, UARTDRV_EUSART_ENABLE_TX); -#else - // Set Tx enable to follow USART implementation. - uartInit.enable = UARTDRV_EUSART_ENABLE_TX; - - if (initData->useLowFrequencyMode) { - EUSART_UartInitLf(initData->port, &uartInit); - } else { - EUSART_UartInitHf(initData->port, &uartInit); - } -#endif - -// Initialize DMA. - retVal = InitializeDma(handle); - - CORE_EXIT_ATOMIC(); - - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - return ECODE_EMDRV_UARTDRV_OK; -} -#endif - -/***************************************************************************//** - * @brief - * Deinitialize a UART driver instance. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - // Stop DMA transfers. - UARTDRV_Abort(handle, uartdrvAbortAll); - - // Do not leave any peer restrained on DeInit - UARTDRV_FlowControlSet(handle, uartdrvFlowControlOn); - - ConfigGpio(handle, false); - -#if (HANDLES_ARE_AVAILABLE) - removeHandle(handle); -#endif - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - handle->peripheral.uart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS; -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - LEUART_Reset(handle->peripheral.leuart); - while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { - } - handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS; - -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - uartdrv_eusart_reset(handle->peripheral.euart); -#endif - } - - CMU_ClockEnable(handle->uartClock, false); - -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHw) { - GPIOINT_CallbackRegister(handle->ctsPin, NULL); - } -#endif - - DMADRV_FreeChannel(handle->txDmaCh); - DMADRV_FreeChannel(handle->rxDmaCh); - DMADRV_DeInit(); - - handle->rxQueue->head = 0; - handle->rxQueue->tail = 0; - handle->rxQueue->used = 0; - - handle->txQueue->head = 0; - handle->txQueue->tail = 0; - handle->txQueue->used = 0; - - emRequestDeinit(handle); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Abort ongoing UART transfers. - * - * @details - * All ongoing or queued operations of the given abort type will be aborted. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] type Abort type -- whether to abort only Tx, only Rx, or both. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success, @ref ECODE_EMDRV_UARTDRV_IDLE if - * the UART is idle. On failure, an appropriate UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type) -{ - UARTDRV_Buffer_t *rxBuffer, *txBuffer; - CORE_DECLARE_IRQ_STATE; - - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - CORE_ENTER_ATOMIC(); - if ((type == uartdrvAbortTransmit) && (handle->txQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } else if ((type == uartdrvAbortReceive) && (handle->rxQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } else if ((type == uartdrvAbortAll) - && (handle->txQueue->used == 0) - && (handle->rxQueue->used == 0)) { - CORE_EXIT_ATOMIC(); - return ECODE_EMDRV_UARTDRV_IDLE; - } - - // Stop DMA transfers. - if ((type == uartdrvAbortTransmit) || (type == uartdrvAbortAll)) { - // Stop the current transfer - DMADRV_StopTransfer(handle->txDmaCh); - handle->txDmaActive = false; - - if (handle->txQueue->used > 0) { - // Update the transfer status of the active transfer - GetTailBuffer(handle->txQueue, &txBuffer); - DMADRV_TransferRemainingCount(handle->txDmaCh, - (int*)&txBuffer->itemsRemaining); - txBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // Dequeue all transfers and call callback - while (handle->txQueue->used > 0) { - DequeueBuffer(handle->txQueue, &txBuffer); - - // Call the callback with ABORTED error code - if (txBuffer->callback != NULL) { - txBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_ABORTED, - NULL, - txBuffer->itemsRemaining); - } - } - } - - // Wait for peripheral to finish cleaning up, to prevent framing errors - // on subsequent transfers - while (!(UARTDRV_GetPeripheralStatus(handle) & UARTDRV_STATUS_TXIDLE)) { - } - } - if ((type == uartdrvAbortReceive) || (type == uartdrvAbortAll)) { - // Stop the current transfer - DMADRV_StopTransfer(handle->rxDmaCh); - handle->rxDmaActive = false; - - if (handle->rxQueue->used > 0) { - // Update the transfer status of the active transfer - GetTailBuffer(handle->rxQueue, &rxBuffer); - DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int*)&rxBuffer->itemsRemaining); - rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; - - // Dequeue all transfers and call callback - while (handle->rxQueue->used > 0) { - DequeueBuffer(handle->rxQueue, &rxBuffer); - - // Call the callback with ABORTED error code - if (rxBuffer->callback != NULL) { - rxBuffer->callback(handle, - ECODE_EMDRV_UARTDRV_ABORTED, - NULL, - rxBuffer->itemsRemaining); - } - } - } - - // Disable the receiver - if (handle->fcType != uartdrvFlowControlHwUart) { - DisableReceiver(handle); - } - } - - if (handle->em1RequestCount > 0) { - em1RequestRemove(handle); - } - - CORE_EXIT_ATOMIC(); - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Return the status of the UART peripheral associated with a given handle. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * UART status value - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle) -{ - UARTDRV_Status_t status = 0; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (handle->type == uartdrvUartTypeUart) { - status = handle->peripheral.uart->STATUS; - } else if (handle->type == uartdrvUartTypeLeuart) { - uint32_t reg = handle->peripheral.leuart->STATUS; - if (reg & LEUART_STATUS_TXENS) { - status |= UARTDRV_STATUS_TXEN; - } - if (reg & LEUART_STATUS_RXENS) { - status |= UARTDRV_STATUS_RXEN; - } - if (reg & LEUART_STATUS_RXBLOCK) { - status |= UARTDRV_STATUS_RXBLOCK; - } - if (reg & LEUART_STATUS_TXC) { - status |= UARTDRV_STATUS_TXC; - } - if (reg & LEUART_STATUS_TXBL) { - status |= UARTDRV_STATUS_TXBL; - } - if (reg & LEUART_STATUS_RXDATAV) { - status |= UARTDRV_STATUS_RXDATAV; - } -#if defined(LEUART_STATUS_TXIDLE) - if (reg & LEUART_STATUS_TXIDLE) { - status |= UARTDRV_STATUS_TXIDLE; - } -#endif - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - status = handle->peripheral.uart->STATUS; -#endif - } else if ((handle->type == uartdrvUartTypeEuart)) { - status = uartdrv_eusart_get_status(handle->peripheral.euart); - } -#else - status = handle->peripheral.uart->STATUS; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) - // Series 0 devices does not have the TXIDLE flag, so we emulate it - if ((status & UARTDRV_STATUS_TXC) || !(handle->hasTransmitted)) { - status |= UARTDRV_STATUS_TXIDLE; - } -#endif - - return status; -} - -/***************************************************************************//** - * @brief - * Return the number of queued receive operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * The number of queued operations. - ******************************************************************************/ -uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle) -{ - return (uint8_t)handle->rxQueue->used; -} - -/***************************************************************************//** - * @brief - * Check the status of the UART and gather information about any ongoing - * receive operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[out] buffer Pointer to the current data buffer. - * - * @param[out] itemsReceived Current bytes received count. - * - * @param[out] itemsRemaining Current bytes remaining count. - * - * @return - * UART status. - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *itemsReceived, - UARTDRV_Count_t *itemsRemaining) -{ - UARTDRV_Buffer_t *rxBuffer = NULL; - Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; - uint32_t remaining = 0; - - if (handle->rxQueue->used > 0) { - retVal = GetTailBuffer(handle->rxQueue, &rxBuffer); - DMADRV_TransferRemainingCount(handle->rxDmaCh, - (int*)&remaining); - } - - if (rxBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { - *itemsReceived = rxBuffer->transferCount - remaining; - *itemsRemaining = remaining; - *buffer = rxBuffer->data; - } else { - *itemsRemaining = 0; - *itemsReceived = 0; - *buffer = NULL; - } - - return UARTDRV_GetPeripheralStatus(handle); -} - -/***************************************************************************//** - * @brief - * Returns the number of queued transmit operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * The number of queued operations. - ******************************************************************************/ -uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle) -{ - return (uint8_t)handle->txQueue->used; -} - -/***************************************************************************//** - * @brief - * Check the status of the UART and gather information about any ongoing - * transmit operations. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[out] buffer Pointer to the current data buffer. - * - * @param[out] itemsSent Current bytes sent count. - * - * @param[out] itemsRemaining Current bytes remaining count. - * - * @return - * UART status. - ******************************************************************************/ -UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, - uint8_t **buffer, - UARTDRV_Count_t *itemsSent, - UARTDRV_Count_t *itemsRemaining) -{ - UARTDRV_Buffer_t *txBuffer = NULL; - Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; - uint32_t remaining = 0; - - if (handle->txQueue->used > 0) { - retVal = GetTailBuffer(handle->txQueue, &txBuffer); - DMADRV_TransferRemainingCount(handle->txDmaCh, - (int*)&remaining); - } - - if (txBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { - *itemsSent = txBuffer->transferCount - remaining; - *itemsRemaining = remaining; - *buffer = txBuffer->data; - } else { - *itemsRemaining = 0; - *itemsSent = 0; - *buffer = NULL; - } - - return UARTDRV_GetPeripheralStatus(handle); -} - -/***************************************************************************//** - * @brief - * Set UART flow control state. Set nRTS pin if hardware flow control - * is enabled. Send XON/XOFF if software flow control is enabled. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] state Flow control state. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) -{ -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType == uartdrvFlowControlHwUart) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - handle->fcSelfCfg = state; - if (state != uartdrvFlowControlAuto) { - handle->fcSelfState = state; - } - return FcApplyState(handle); -#else - (void) handle; - (void) state; - return ECODE_EMDRV_UARTDRV_OK; -#endif -} - -/***************************************************************************//** - * @brief - * Set peer UART flow control state. Pause/resume transmit accordingly. - * Only for manual software flow control. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] state Flow control state. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) -{ - if ( (handle->fcType != uartdrvFlowControlSw) - || (state == uartdrvFlowControlAuto) ) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - - if (handle->fcPeerState != state) { - handle->fcPeerState = state; - if (state == uartdrvFlowControlOn) { - UARTDRV_ResumeTransmit(handle); - } else if (state == uartdrvFlowControlOff) { - UARTDRV_PauseTransmit(handle); - } - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Check the peer's flow control status. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * Returns uartdrvFlowControlOn if clear to send. - ******************************************************************************/ -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle) -{ - return handle->fcPeerState; -} - -/***************************************************************************//** - * @brief - * Check the self flow control status. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * Returns uartdrvFlowControlOn if requesting to send. - ******************************************************************************/ -UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle) -{ - return handle->fcSelfState; -} - -/***************************************************************************//** - * @brief - * Enable transmission when restrained by flow control. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle) -{ - handle->IgnoreRestrain = true; - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Direct receive without interrupts or callback. This is a blocking function. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data pointer to buffer. - * - * @param[in] maxCount Maximum number of bytes to receive. - * - * @return - * Number of bytes received. - ******************************************************************************/ -UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t maxCount) -{ - Ecode_t retVal; - uint32_t rxState; - UARTDRV_Count_t i = 0; - - retVal = CheckParams(handle, data, maxCount); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return 0; - } - - // Wait for DMA receive to complete and clear - while (handle->rxQueue->used > 0) { - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - rxState = (handle->peripheral.uart->STATUS & USART_STATUS_RXENS); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - rxState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS); -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - rxState = (handle->peripheral.euart->STATUS & EUSART_STATUS_RXENS); -#endif - } else { - EFM_ASSERT(false); - rxState = 0; - } - - if (!rxState) { - EnableReceiver(handle); - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - while ((handle->peripheral.uart->STATUS & USART_STATUS_RXDATAV) != 0U) { - *data = (uint8_t)handle->peripheral.uart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - while ((handle->peripheral.leuart->STATUS & LEUART_STATUS_RXDATAV) != 0U) { - *data = (uint8_t)handle->peripheral.leuart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - while ((handle->peripheral.euart->STATUS & EUSART_STATUS_RXFL) != 0U) { - *data = (uint8_t)handle->peripheral.euart->RXDATA; - data++; - i++; - if (i >= maxCount) { - break; - } - } -#endif - } - - data -= i; - - if (!rxState) { - DisableReceiver(handle); - } - return i; -} - -/***************************************************************************//** - * @brief - * Direct transmit without interrupts or callback. This is a blocking function. - * that ignores flow control if enabled. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data Pointer to the buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - uint32_t txState; - bool callDmaIrqHandler; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - - // Wait for DMA transmit to complete and clear - callDmaIrqHandler = CORE_IrqIsBlocked(UART_DMA_IRQ); // Loop invariant - while ((handle->txQueue->used > 0) && (!handle->txDmaPaused)) { - if (callDmaIrqHandler) { - UART_DMA_IRQHANDLER(); - } - } - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); -#endif -#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; -#endif - } else { - EFM_ASSERT(false); - txState = 0; - } - - if (!txState) { - EnableTransmitter(handle); - } - - handle->hasTransmitted = true; - - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - while (count-- != 0U) { - USART_Tx(handle->peripheral.uart, *data++); - } - // Wait for Tx completion - while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXC)) { - } -#endif -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - } else if (handle->type == uartdrvUartTypeLeuart) { - while (count-- != 0U) { - LEUART_Tx(handle->peripheral.leuart, *data++); - } - // Wait for Tx completion - while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXC)) { - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeEuart) { - while (count-- != 0U) { - uartdrv_eusart_tx(handle->peripheral.euart, *data++); - } - while (~uartdrv_eusart_get_status(handle->peripheral.euart) & (EUSART_STATUS_TXC | EUSART_STATUS_TXIDLE)) { - } -#endif - } - - if (!txState) { - DisableTransmitter(handle); - } - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Pause an ongoing transmit operation. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - // Pause the transfer if 1) pause counter is 0 - // 2) HW flow control hasn't already paused the DMA - if ( (handle->txDmaPaused == 0) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { - DMADRV_PauseTransfer(handle->txDmaCh); - } - // Increment counter to allow nested calls - handle->txDmaPaused++; - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a non-blocking receive. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A receive data buffer. - * - * @param[in] count A number of bytes received. - * - * @param[in] callback A transfer completion callback. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback) -{ - Ecode_t retVal; - UARTDRV_Buffer_t outputBuffer; - UARTDRV_Buffer_t *queueBuffer; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - outputBuffer.data = data; - outputBuffer.transferCount = count; - outputBuffer.itemsRemaining = count; - outputBuffer.callback = callback; - outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - - retVal = EnqueueBuffer(handle->rxQueue, &outputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if (!(handle->rxDmaActive)) { - EnableReceiver(handle); - StartReceiveDma(handle, queueBuffer); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType != uartdrvFlowControlHwUart) { - handle->fcSelfState = uartdrvFlowControlOn; - FcApplyState(handle); - } -#endif - } // else: started by ReceiveDmaComplete - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a blocking receive. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A receive data buffer. - * - * @param[in] count A number of bytes received. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - UARTDRV_Buffer_t inputBuffer; - UARTDRV_Buffer_t *queueBuffer; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - inputBuffer.data = data; - inputBuffer.transferCount = count; - inputBuffer.itemsRemaining = count; - inputBuffer.callback = NULL; - inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - - retVal = EnqueueBuffer(handle->rxQueue, &inputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->rxQueue->used > 1) { - } - EnableReceiver(handle); -#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) - if (handle->fcType != uartdrvFlowControlHwUart) { - handle->fcSelfState = uartdrvFlowControlOn; - FcApplyState(handle); - } -#endif - StartReceiveDma(handle, queueBuffer); - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->rxDmaActive) { - } - return queueBuffer->transferStatus; -} - -/***************************************************************************//** - * @brief - * Resume a paused transmit operation. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate - * UARTDRV @ref Ecode_t is returned. - ******************************************************************************/ -Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle) -{ - if (handle == NULL) { - return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; - } - - if (handle->txDmaPaused > 0) { - // Resume the transfer if 1) pause counter is 1 - // 2) HW flow control doesn't need to pause the DMA - if ( (handle->txDmaPaused == 1) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { - DMADRV_ResumeTransfer(handle->txDmaCh); - } - handle->txDmaPaused--; - } else { - return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; - } - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a non-blocking transmit. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A transmit data buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @param[in] callback A transfer completion callback. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count, - UARTDRV_Callback_t callback) -{ - Ecode_t retVal; - UARTDRV_Buffer_t inputBuffer; - UARTDRV_Buffer_t *queueBuffer; - uint32_t txState; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - inputBuffer.data = data; - inputBuffer.transferCount = count; - inputBuffer.itemsRemaining = count; - inputBuffer.callback = callback; - inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); - } else { - EFM_ASSERT(false); - txState = 0; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; - } else { - EFM_ASSERT(false); - txState = 0; - } -#else - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - - if (!txState) { - EnableTransmitter(handle); - } - - retVal = EnqueueBuffer(handle->txQueue, &inputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - if (!(handle->txDmaActive)) { - CORE_ATOMIC_SECTION( - if (handle->txQueue->used > 0) { - StartTransmitDma(handle, queueBuffer); - handle->hasTransmitted = true; - } - ) - } // else: started by TransmitDmaComplete - - return ECODE_EMDRV_UARTDRV_OK; -} - -/***************************************************************************//** - * @brief - * Start a blocking transmit. - * - * @param[in] handle Pointer to a UART driver handle. - * - * @param[in] data A transmit data buffer. - * - * @param[in] count A number of bytes to transmit. - * - * @return - * @ref ECODE_EMDRV_UARTDRV_OK on success. - ******************************************************************************/ -Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, - uint8_t *data, - UARTDRV_Count_t count) -{ - Ecode_t retVal; - UARTDRV_Buffer_t outputBuffer; - UARTDRV_Buffer_t *queueBuffer; - uint32_t txState; - - retVal = CheckParams(handle, data, count); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - outputBuffer.data = data; - outputBuffer.transferCount = count; - outputBuffer.itemsRemaining = count; - outputBuffer.callback = NULL; - outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; - -#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeLeuart) { - txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); - } else { - EFM_ASSERT(false); - txState = 0; - } -#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) - if (false) { -#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) - } else if (handle->type == uartdrvUartTypeUart) { - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - } else if (handle->type == uartdrvUartTypeEuart) { - txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; - } else { - EFM_ASSERT(false); - txState = 0; - } -#else - txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); -#endif - - if (!txState) { - EnableTransmitter(handle); - } - - retVal = EnqueueBuffer(handle->txQueue, &outputBuffer, &queueBuffer); - if (retVal != ECODE_EMDRV_UARTDRV_OK) { - return retVal; - } - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->txQueue->used > 1) { - } - StartTransmitDma(handle, queueBuffer); - handle->hasTransmitted = true; - // Active wait, the system must be in EM0 or EM1 anyway - while (handle->txDmaActive) { - } - - return queueBuffer->transferStatus; -} - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) -sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void) -{ - sl_power_manager_on_isr_exit_t result = SL_POWER_MANAGER_IGNORE; - uint32_t handleIdx; - UARTDRV_Handle_t handle; - - if (uartdrvHandleIsInitialized) { - for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { - handle = uartdrvHandle[handleIdx]; - if (handle != NULL) { - if ((sl_power_manager_on_isr_exit_t)handle->sleep == SL_POWER_MANAGER_SLEEP) { - handle->sleep = SL_POWER_MANAGER_IGNORE; - result = SL_POWER_MANAGER_SLEEP; - } - } - } - } - - return result; -} -#endif - -/******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** - * @addtogroup uartdrv UARTDRV - UART Driver - * @brief Universal Asynchronous Receiver/Transmitter Driver - * @{ - - @details - The source files for the UART driver library, uartdrv.c and uartdrv.h, are in the - emdrv/uartdrv folder. - - @n @section uartdrv_intro Introduction - The UART driver supports the UART capabilities of the USART, UART, and LEUART - peripherals. The driver is fully reentrant and supports multiple driver instances. - The driver does not buffer or queue data. However, it queues UART transmit - and receive operations. Both blocking and non-blocking transfer functions are - available. Non-blocking transfer functions report transfer completion with - callback functions. Transfers are done using DMA. Simple direct/forced - transmit and receive functions are also available. Note that these functions - are blocking and not suitable for low energy applications because they use CPU - polling. - - UART hardware flow control (CTS/RTS) is fully supported by the driver. UART - software flow control (XON/XOFF) is partially supported by the driver. For - more information about flow control support, see @ref uartdrv_fc. - - @note Transfer completion callback functions are called from within the DMA - interrupt handler with interrupts disabled. - - @n @section uartdrv_conf Configuration Options - - Some properties of the UARTDRV driver are compile-time configurable. These - properties are set in a uartdrv_config.h file. A template for this - file, containing default values, is in the emdrv/config folder. - To configure UARTDRV for your application, provide a custom configuration file, - or override the defines on the compiler command line. - These are the available configuration parameters with default values defined. - @code - - // Set to 1 to enable hardware flow control. - #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 - - // Maximum number of driver instances. - #define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 - - // UART software flow control code: request peer to start Tx. - #define UARTDRV_FC_SW_XON 0x11 - - // UART software flow control code: request peer to stop Tx. - #define UARTDRV_FC_SW_XOFF 0x13 - @endcode - - The properties of each UART driver instance are set at run-time via the - @ref UARTDRV_InitUart_t data structure input parameter to the @ref UARTDRV_InitUart() - function for UART and USART peripherals, and the @ref UARTDRV_InitLeuart_t - data structure input parameter to the @ref UARTDRV_InitLeuart() function for - LEUART peripherals. - - @n @section uartdrv_api The API - - This section contains brief descriptions of the functions in the API. For more - information on input and output parameters and return values, - click on the hyperlinked function names. Most functions return an error - code, @ref ECODE_EMDRV_UARTDRV_OK is returned on success, - see ecode.h and uartdrv.h for other error codes. - - The application code must include @em uartdrv.h header file. - - @ref UARTDRV_InitUart(), @ref UARTDRV_InitLeuart() and @ref UARTDRV_DeInit() @n - These functions initialize and deinitialize the UARTDRV driver. Typically, - UARTDRV_InitUart() (for UART/USART) or - UARTDRV_InitLeuart() (for LEUART) are called once in - the startup code. - - @ref UARTDRV_GetReceiveStatus() and @ref UARTDRV_GetTransmitStatus() @n - Query the status of a current transmit or receive operations. Reports number - of items (frames) transmitted and remaining. - - @ref UARTDRV_GetReceiveDepth() and @ref UARTDRV_GetTransmitDepth() @n - Get the number of queued receive or transmit operations. - - @ref UARTDRV_Transmit(), UARTDRV_Receive() @n - UARTDRV_TransmitB(), UARTDRV_ReceiveB() @n - UARTDRV_ForceTransmit() and UARTDRV_ForceReceive() @n - Blocking and non-blocking transfer functions are included. - The blocking versions have an uppercase B (for Blocking) at the end of - their function name. Blocking functions do not return before the transfer - is complete. The non-blocking functions signal a transfer completion with a - callback function. @ref UARTDRV_ForceTransmit() and - @ref UARTDRV_ForceReceive() are also blocking. These two functions access - the UART peripheral directly without using DMA or interrupts. - @ref UARTDRV_ForceTransmit() does not respect flow control. - @ref UARTDRV_ForceReceive() forces RTS low. - - @ref UARTDRV_Abort() @n - Abort current transmit or receive operations and remove all queued - operations. - - @ref UARTDRV_FlowControlSet(), @ref UARTDRV_FlowControlGetSelfStatus(), @ref UARTDRV_FlowControlSetPeerStatus() and @ref UARTDRV_FlowControlGetPeerStatus() @n - Set and get flow control status of self or peer device. Note that the return - value from these two functions depends on the flow control mode set by - @ref UARTDRV_FlowControlSet(), @ref UARTDRV_InitUart(), or - @ref UARTDRV_InitLeuart(). - - @ref UARTDRV_FlowControlIgnoreRestrain() @n - Enables transmission when restrained by flow control. - - @ref UARTDRV_PauseTransmit() and @ref UARTDRV_ResumeTransmit() @n - Pause a currently active transmit operation by preventing the DMA from loading - the UART FIFO. Will not override HW flow control state (if applicable), but - can be used in conjunction. - - @n @section uartdrv_fc Flow Control Support - - If UART flow control is not required, make sure that - EMDRV_UARTDRV_FLOW_CONTROL_ENABLE is set to 0. This reduces the code size - and complexity of the driver. - - Both hardware and software flow control are supported. To - enable either of these, set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1 in - uartdrv_config.h. - - @n @subsection uartdrv_fc_hw Hardware Flow Control - - UART hardware flow control uses two additional pins for flow control - handshaking, the clear-to-send (CTS) and ready-to-send (RTS) pins. - RTS is an output and CTS is an input. These are active-low signals. - When CTS is high, the UART transmitter should stop sending frames. - A receiver should set RTS high when it is no longer capable of - receiving data. - - @par Peripheral Hardware Flow Control - - Newer devices natively support CTS/RTS in - the USART peripheral hardware. To enable hardware flow control, perform the - following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - In the @ref UARTDRV_InitUart_t struct passed to @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHwUart. - - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort - and rtsPin in the init struct. - - Also define the CTS and RTS locations by setting portLocationCts and - portLocationRts in the init struct. - - @par GPIO Hardware Flow Control - - To support hardware flow control on devices that don't have UART CTS/RTS - hardware support, the driver includes the GPIOINT driver to emulate a - hardware implementation of UART CTS/RTS flow control on these devices. - - To enable hardware flow control, perform the following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - UART/USART: In the @ref UARTDRV_InitUart_t struct passed to - @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHw. - - LEUART: In the @ref UARTDRV_InitLeuart_t struct passed to - @ref UARTDRV_InitLeuart(), set - @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlHw. - - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort and - rtsPin in the same init struct. - - @note Because of the limitations in GPIO interrupt hardware, you cannot select - CTS pins in multiple driver instances with the same pin number. For example, pin A0 and - B0 cannot serve as CTS pins in two concurrent driver instances. - - RTS is set high whenever there are no Rx operations queued. The UART - transmitter is halted when the CTS pin goes high. The transmitter completes - the current frame before halting. DMA transfers are also halted. - - @n @subsection uartdrv_fc_sw Software Flow Control - - UART software flow control uses in-band signaling, meaning the receiver sends - special flow control characters to the transmitter and thereby removes - the need for dedicated wires for flow control. The two symbols - UARTDRV_FC_SW_XON and UARTDRV_FC_SW_XOFF are defined in uartdrv_config.h. - - To enable support for software flow control, perform the following steps: - - - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. - - UART/USART: In the @ref UARTDRV_InitUart_t structure passed to - @ref UARTDRV_InitUart(), set - @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlSw. - - LEUART: In the @ref UARTDRV_InitLeuart_t structure passed to - @ref UARTDRV_InitLeuart(), set - @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlSw. - - @note Software flow control is partial only. - - The application must monitor buffers and make decisions on when to send XON/ - XOFF. XON/XOFF can be sent to the peer using @ref UARTDRV_FlowControlSet(). - Though @ref UARTDRV_FlowControlSet() will pause the active transmit operation - to send a flow control character, there is no way to guarantee the order. - If the application implements a specific packet format where the flow control - codes may appear only in fixed positions, the application should not - use @ref UARTDRV_FlowControlSet() but implement read and write of XON/XOFF - into packet buffers. If the application code fully implements all the flow - control logic, EMDRV_UARTDRV_FLOW_CONTROL_ENABLE should be set to 0 - to reduce code space. - - @n @section uartdrv_example Example - @if DOXYDOC_P1_DEVICE - @if DOXYDOC_EFM32G - @include uartdrv_example_p1_nomvdis.c - @endif - @if DOXYDOC_EZR32HG - @include uartdrv_example_p1_usart0.c - @endif - @ifnot (DOXYDOC_EFM32G || DOXYDOC_EZR32HG) - @include uartdrv_example_p1.c - @endif - @endif - @if DOXYDOC_P2_DEVICE - @include uartdrv_example_p2.c - @endif - @if DOXYDOC_S2_DEVICE - @include uartdrv_example_s2.c - @endif - - * @} end group uartdrv *********************************************************/ +/***************************************************************************//** + * @file + * @brief UARTDRV API implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#define CURRENT_MODULE_NAME "UARTDRV" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#include "uartdrv.h" +#include "em_device.h" +#include "em_core.h" +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +#include "gpiointerrupt.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#include "sl_sleeptimer.h" +#endif + +#include + +//**************************************************************************** + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(_USART_ROUTEPEN_CTSPEN_MASK) +#define UART_HW_FLOW_CONTROL_SUPPORT +#elif (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) && defined(USART_CTRLX_CTSEN) +#define UART_HW_FLOW_CONTROL_SUPPORT +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +#define HANDLES_ARE_AVAILABLE 1 +#elif defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +#define HANDLES_ARE_AVAILABLE 1 +#else +#define HANDLES_ARE_AVAILABLE 0 +#endif + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#if defined(DMA_PRESENT) && (DMA_COUNT == 1) +#define UART_DMA_IRQ DMA_IRQn +#define UART_DMA_IRQHANDLER() DMA_IRQHandler() +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES <= 2) +#define UART_DMA_IRQ LDMA_IRQn +#define UART_DMA_IRQHANDLER() LDMA_IRQHandler() +#elif defined(LDMA_PRESENT) && (LDMA_COUNT == 1) && (_SILICON_LABS_32B_SERIES > 2) +#define UART_DMA_IRQ LDMA_CHNL0_IRQn +#define UART_DMA_IRQHANDLER() LDMA_CHNL0_IRQHandler() +#else +#error "No valid UARTDRV DMA engine defined." +#endif + +// UARTDRV use low-level drivers from platform/peripheral. +#if defined(UARTDRV_USE_PERIPHERAL) + +#define uartdrv_gpio_port_t sl_gpio_port_t +#define UARTDRV_GPIO_MODE_DISABLED SL_GPIO_MODE_DISABLED +#define UARTDRV_GPIO_MODE_INPUT SL_GPIO_MODE_INPUT +#define UARTDRV_GPIO_MODE_INPUT_PULL SL_GPIO_MODE_INPUT_PULL +#define UARTDRV_GPIO_MODE_PUSH_PULL SL_GPIO_MODE_PUSH_PULL + +#define uartdrv_gpio_get_pin_input(port, pin) sl_gpio_get_pin_input(port, pin) +#define uartdrv_gpio_set_pin_output(port, pin) sl_gpio_set_pin_output(port, pin) +#define uartdrv_gpio_clear_pin_output(port, pin) sl_gpio_clear_pin_output(port, pin) +#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) sl_gpio_set_pin_mode(port, pin, mode, output) +#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ + sl_gpio_configure_external_interrupt(port, \ + pin, \ + intNo, \ + (risingEdge * SL_GPIO_INTERRUPT_RISING_EDGE \ + & fallingEdge * SL_GPIO_INTERRUPT_FALLING_EDGE \ + & enable * SL_GPIO_INTERRUPT_ENABLE)) + +#define uartdrv_eusart_data_bits_t sl_hal_eusart_data_bits_t +#define uartdrv_eusart_stop_bits_t sl_hal_eusart_stop_bits_t +#define uartdrv_eusart_parity_t sl_hal_eusart_parity_t +#define uartdrv_eusart_ovs_t sl_hal_eusart_ovs_t +#define uartdrv_eusart_majority_vote_t sl_hal_eusart_majority_vote_t + +#define UARTDRV_EUSART_DISABLE 0x0 +#define UARTDRV_EUSART_ENABLE_RX (EUSART_CMD_RXEN | EUSART_CMD_TXDIS) +#define UARTDRV_EUSART_ENABLE_TX (EUSART_CMD_TXEN | EUSART_CMD_RXDIS) +#define UARTDRV_EUSART_ENABLE (EUSART_CMD_RXEN | EUSART_CMD_TXEN) + +#define uartdrv_eusart_get_status(eusart) sl_hal_eusart_get_status(eusart) +#define uartdrv_eusart_tx(eusart, data) sl_hal_eusart_tx(eusart, data) +#define uartdrv_eusart_reset(eusart) sl_hal_eusart_reset(eusart) +#define uartdrv_eusart_enable(eusart, enable) do { if (enable == UARTDRV_EUSART_DISABLE) \ + { sl_hal_eusart_disable(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE_RX) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_disable_tx(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE_TX) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_tx(eusart); sl_hal_eusart_disable_rx(eusart); } \ + else if (enable == UARTDRV_EUSART_ENABLE) \ + { sl_hal_eusart_enable(eusart); sl_hal_eusart_enable_rx(eusart); sl_hal_eusart_enable_tx(eusart); } } while (0) + +// UARTDRV use low-level drivers from platform/emlib. +#else +#define uartdrv_gpio_port_t GPIO_Port_TypeDef + +#define UARTDRV_GPIO_MODE_DISABLED gpioModeDisabled +#define UARTDRV_GPIO_MODE_INPUT gpioModeInput +#define UARTDRV_GPIO_MODE_INPUT_PULL gpioModeInputPull +#define UARTDRV_GPIO_MODE_PUSH_PULL gpioModePushPull + +#define uartdrv_gpio_get_pin_input(port, pin) GPIO_PinInGet(port, pin) +#define uartdrv_gpio_set_pin_output(port, pin) GPIO_PinOutSet(port, pin) +#define uartdrv_gpio_clear_pin_output(port, pin) GPIO_PinOutClear(port, pin) +#define uartdrv_gpio_set_pin_mode(port, pin, mode, output) GPIO_PinModeSet(port, pin, mode, output) +#define uartdrv_gpio_config_ext_int(port, pin, intNo, risingEdge, fallingEdge, enable) \ + GPIO_ExtIntConfig(port, pin, intNo, risingEdge, fallingEdge, enable) + +#define uartdrv_eusart_data_bits_t EUSART_Databits_TypeDef +#define uartdrv_eusart_stop_bits_t EUSART_Stopbits_TypeDef +#define uartdrv_eusart_parity_t EUSART_Parity_TypeDef +#define uartdrv_eusart_ovs_t EUSART_OVS_TypeDef +#define uartdrv_eusart_majority_vote_t EUSART_MajorityVote_TypeDef + +#define UARTDRV_EUSART_DISABLE eusartDisable +#define UARTDRV_EUSART_ENABLE_RX eusartEnableRx +#define UARTDRV_EUSART_ENABLE_TX eusartEnableTx +#define UARTDRV_EUSART_ENABLE eusartEnable + +#define uartdrv_eusart_get_status(eusart) EUSART_StatusGet(eusart) +#define uartdrv_eusart_tx(eusart, data) EUSART_Tx(eusart, data) +#define uartdrv_eusart_reset(eusart) EUSART_Reset(eusart) +#define uartdrv_eusart_enable(eusart, enable) EUSART_Enable(eusart, enable) +#endif + +//**************************************************************************** + +#if (HANDLES_ARE_AVAILABLE) +static bool uartdrvHandleIsInitialized = false; +static UARTDRV_Handle_t uartdrvHandle[EMDRV_UARTDRV_MAX_DRIVER_INSTANCES]; +#endif +static bool enableRxWhenSleeping = UARTDRV_RESTRICT_ENERGY_MODE_TO_ALLOW_RECEPTION; + +//**************************************************************************** + +static bool ReceiveDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam); +static bool TransmitDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam); + +/***************************************************************************//** + * @brief Power management functions for the uartdrv. + ******************************************************************************/ +static void em1RequestAdd(UARTDRV_Handle_t handle) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (handle->em1RequestCount == 0) { + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + } + handle->em1RequestCount++; + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount++; +#endif +} + +static void em1RequestRemove(UARTDRV_Handle_t handle) +{ + EFM_ASSERT(handle->em1RequestCount > 0); +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + handle->em1RequestCount--; + if (handle->em1RequestCount == 0) { + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + } + CORE_EXIT_ATOMIC(); +#else + handle->em1RequestCount--; +#endif +} + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +static void emRequestInit(UARTDRV_Handle_t handle) +{ + handle->em1RequestCount = 0; +} +#endif + +static void emRequestDeinit(UARTDRV_Handle_t handle) +{ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + sl_status_t status; + bool running; + + CORE_ENTER_ATOMIC(); + status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); + if ((status == SL_STATUS_OK) && (running)) { + sl_sleeptimer_stop_timer(&handle->delayedTxTimer); + } + CORE_EXIT_ATOMIC(); +#endif + if (handle->em1RequestCount > 0) { + handle->em1RequestCount = 1; + em1RequestRemove(handle); + } +} + +/***************************************************************************//** + * @brief Get UARTDRV_Handle_t from GPIO pin number (HW FC CTS pin interrupt). + ******************************************************************************/ +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +static UARTDRV_Handle_t HwFcCtsIrqGetDrvHandle(uint32_t gpioPinNo) +{ + uint32_t i; + + for (i = 0; i < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; i++) { + if (uartdrvHandle[i]->ctsPin == gpioPinNo) { + return uartdrvHandle[i]; + } + } + return NULL; +} + +/***************************************************************************//** + * @brief Get CTS pin state. + ******************************************************************************/ +static UARTDRV_FlowControlState_t HwFcGetClearToSendPin(UARTDRV_Handle_t handle) +{ + if (handle->fcType == uartdrvFlowControlHw) { + return (UARTDRV_FlowControlState_t)uartdrv_gpio_get_pin_input(handle->ctsPort, handle->ctsPin); + } else { + return uartdrvFlowControlOn; + } +} + +/***************************************************************************//** + * @brief Manage CTS pin change. + ******************************************************************************/ +static void HwFcManageClearToSend(uint8_t gpioPinNo) +{ + UARTDRV_Handle_t handle = HwFcCtsIrqGetDrvHandle(gpioPinNo); + + if (handle && handle->fcType == uartdrvFlowControlHw) { + // If not auto mode, assign the CTS pin state to the self state + // If auto mode, also control UART Tx enable + handle->fcSelfState = HwFcGetClearToSendPin(handle); + // Only manage DMA if not already paused by SW + if (handle->fcSelfCfg == uartdrvFlowControlAuto && (handle->txDmaPaused == 0)) { + bool active = false; + Ecode_t status = DMADRV_TransferActive(handle->txDmaCh, &active); + if ((handle->fcSelfState == uartdrvFlowControlOn) || handle->IgnoreRestrain) { + handle->IgnoreRestrain = false; + DMADRV_ResumeTransfer(handle->txDmaCh); + } + // Only pause DMA if currently active + else if ((status == ECODE_EMDRV_DMADRV_OK) && active) { + DMADRV_PauseTransfer(handle->txDmaCh); + } + } + } +} + +static Ecode_t FcApplyState(UARTDRV_Handle_t handle) +{ + uint8_t fcSwCode; + + if (handle->fcType == uartdrvFlowControlHw) { + if (handle->fcSelfCfg == uartdrvFlowControlOn) { + // Assert nRTS (application control) + uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); + } else if (handle->fcSelfCfg == uartdrvFlowControlOff) { + // Deassert nRTS (application control) + uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); + } else { // Auto mode + if (handle->fcSelfState == uartdrvFlowControlOn) { + // Assert nRTS + uartdrv_gpio_clear_pin_output(handle->rtsPort, handle->rtsPin); + } else { // Off + // Deassert nRTS + uartdrv_gpio_set_pin_output(handle->rtsPort, handle->rtsPin); + } + } + } else if (handle->fcType == uartdrvFlowControlSw) { + if (handle->fcSelfState == uartdrvFlowControlOn) { + fcSwCode = UARTDRV_FC_SW_XON; + // Pause transmit to ensure XON transmits immediately + UARTDRV_PauseTransmit(handle); + UARTDRV_ForceTransmit(handle, &fcSwCode, 1); + UARTDRV_ResumeTransmit(handle); + } else { + fcSwCode = UARTDRV_FC_SW_XOFF; + // Pause transmit to ensure XOFF transmits immediately + UARTDRV_PauseTransmit(handle); + UARTDRV_ForceTransmit(handle, &fcSwCode, 1); + UARTDRV_ResumeTransmit(handle); + } + } + return ECODE_EMDRV_UARTDRV_OK; +} +#else +// CTS pin should always read as uartdrvFlowControlOn when HW FC is disabled +#define HwFcGetClearToSendPin(x) uartdrvFlowControlOn +#endif /* EMDRV_UARTDRV_FLOW_CONTROL_ENABLE */ + +/***************************************************************************//** + * @brief Enqueue UART transfer buffer. + ******************************************************************************/ +static Ecode_t EnqueueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t *inputBuffer, + UARTDRV_Buffer_t **queueBuffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used >= queue->size) { + *queueBuffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_FULL; + } + memcpy((void *)&queue->fifo[queue->head], + (const void *)inputBuffer, + sizeof(UARTDRV_Buffer_t)); + *queueBuffer = &queue->fifo[queue->head]; + queue->head = (queue->head + 1) % queue->size; + queue->used++; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Dequeue UART transfer buffer. + ******************************************************************************/ +static Ecode_t DequeueBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + queue->tail = (queue->tail + 1) % queue->size; + queue->used--; + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Get tail UART transfer buffer. + ******************************************************************************/ +static Ecode_t GetTailBuffer(UARTDRV_Buffer_FifoQueue_t *queue, + UARTDRV_Buffer_t **buffer) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (queue->used == 0) { + *buffer = NULL; + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_QUEUE_EMPTY; + } + *buffer = &queue->fifo[queue->tail]; + + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Enable UART transmitter. + ******************************************************************************/ +static void EnableTransmitter(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif // LEUART || EUART || EUSART + { + // Enable Tx + handle->peripheral.uart->CMD = USART_CMD_TXEN; + // Wait for Tx to be enabled + while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXENS)) { + } + + // Enable Tx route +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_TXPEN; +#elif defined(USART_ROUTE_TXPEN) + handle->peripheral.uart->ROUTE |= USART_ROUTE_TXPEN; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; +#endif + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Enable Tx + handle->peripheral.leuart->CMD = LEUART_CMD_TXEN; + // Wait for Tx to be enabled + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS)) { + } + + // Enable Tx route +#if defined(LEUART_ROUTEPEN_TXPEN) + handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN; +#else + handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_TXPEN; +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); + } +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; +#endif + } +#endif +} + +/***************************************************************************//** + * @brief Disable UART transmitter. + ******************************************************************************/ +static void DisableTransmitter(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Disable Tx route +#if defined(USART_ROUTEPEN_TXPEN) + handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_TXPEN; +#elif defined(USART_ROUTE_TXPEN) + handle->peripheral.uart->ROUTE &= ~USART_ROUTE_TXPEN; +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN; +#endif + // Disable Tx + handle->peripheral.uart->CMD = USART_CMD_TXDIS; + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Disable Tx route +#if defined(LEUART_ROUTEPEN_TXPEN) + handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_TXPEN; +#else + handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_TXPEN; +#endif + // Disable Tx + handle->peripheral.leuart->CMD = LEUART_CMD_TXDIS; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_RXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); + } +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; +#endif + } +#endif +} + +/***************************************************************************//** + * @brief Enable UART receiver. + ******************************************************************************/ +static void EnableReceiver(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Enable Rx + handle->peripheral.uart->CMD = USART_CMD_RXEN; + // Wait for Rx to be enabled + while (!(handle->peripheral.uart->STATUS & USART_STATUS_RXENS)) { + } + + // Enable Rx route +#if defined(USART_ROUTEPEN_RXPEN) + handle->peripheral.uart->ROUTEPEN |= USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_RXPEN) + handle->peripheral.uart->ROUTE |= USART_ROUTE_RXPEN; +#elif defined(GPIO_USART_ROUTEEN_RXPEN) + GPIO->USARTROUTE_SET[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; +#endif + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for previous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Enable Rx + handle->peripheral.leuart->CMD = LEUART_CMD_RXEN; + // Wait for Rx to be enabled + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS)) { + } + + // Enable Rx route +#if defined(LEUART_ROUTEPEN_RXPEN) + handle->peripheral.leuart->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN; +#else + handle->peripheral.leuart->ROUTE |= LEUART_ROUTE_RXPEN; +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_RX); + } + } +#endif +} + +/***************************************************************************//** + * @brief Disable UART receiver. + ******************************************************************************/ +static void DisableReceiver(UARTDRV_Handle_t handle) +{ + if (false) { + } +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) \ + || (defined(EUART_COUNT) && (EUART_COUNT > 0)) \ + || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeUart) +#endif + { + // Disable Rx route +#if defined(USART_ROUTEPEN_RXPEN) + handle->peripheral.uart->ROUTEPEN &= ~USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_RXPEN) + handle->peripheral.uart->ROUTE &= ~USART_ROUTE_RXPEN; +#elif defined(GPIO_USART_ROUTEEN_RXPEN) + GPIO->USARTROUTE_CLR[handle->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RXPEN; +#endif + // Disable Rx + handle->peripheral.uart->CMD = USART_CMD_RXDIS; + } +#endif // UART || USART +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + else if (handle->type == uartdrvUartTypeLeuart) { + // Wait for prevous register writes to sync + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Disable Rx route +#if defined(LEUART_ROUTEPEN_RXPEN) + handle->peripheral.leuart->ROUTEPEN &= ~LEUART_ROUTEPEN_RXPEN; +#else + handle->peripheral.leuart->ROUTE &= ~LEUART_ROUTE_RXPEN; +#endif + // Disable Rx + handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + else if (handle->type == uartdrvUartTypeEuart) { + if (uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS) { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_ENABLE_TX); + } else { + uartdrv_eusart_enable(handle->peripheral.euart, UARTDRV_EUSART_DISABLE); + } + } +#endif +} + +/***************************************************************************//** + * @brief Start a UART DMA receive operation. + ******************************************************************************/ +static void StartReceiveDma(UARTDRV_Handle_t handle, + UARTDRV_Buffer_t *buffer) +{ + void *rxPort = NULL; + + handle->rxDmaActive = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + rxPort = (void *)&(handle->peripheral.uart->RXDATA); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + rxPort = (void *)&(handle->peripheral.leuart->RXDATA); +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + rxPort = (void *)&(handle->peripheral.euart->RXDATA); +#endif + } else { + handle->rxDmaActive = false; + return; + } + + if (enableRxWhenSleeping) { + em1RequestAdd(handle); + } + DMADRV_PeripheralMemory(handle->rxDmaCh, + handle->rxDmaSignal, + buffer->data, + rxPort, + true, + buffer->transferCount, + dmadrvDataSize1, + ReceiveDmaComplete, + handle); +} + +/***************************************************************************//** + * @brief Start a UART DMA transmit operation. + ******************************************************************************/ +static void StartTransmitDma(UARTDRV_Handle_t handle, + UARTDRV_Buffer_t *buffer) +{ + void *txPort = NULL; + + handle->txDmaActive = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txPort = (void *)&(handle->peripheral.uart->TXDATA); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + // Set TX DMA wakeup request. Needed for transmit while in EM2. + handle->peripheral.leuart->CTRL |= LEUART_CTRL_TXDMAWU; + txPort = (void *)&(handle->peripheral.leuart->TXDATA); +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + txPort = (void *)&(handle->peripheral.euart->TXDATA); +#endif + } else { + handle->txDmaActive = false; + return; + } + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + CORE_DECLARE_IRQ_STATE; + sl_status_t status; + bool running; + + CORE_ENTER_ATOMIC(); + status = sl_sleeptimer_is_timer_running(&handle->delayedTxTimer, &running); + if ((status == 0) && (running)) { + sl_sleeptimer_stop_timer(&handle->delayedTxTimer); + em1RequestRemove(handle); + } + CORE_EXIT_ATOMIC(); +#if !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif +#endif + + em1RequestAdd(handle); + DMADRV_MemoryPeripheral(handle->txDmaCh, + handle->txDmaSignal, + txPort, + buffer->data, + true, + buffer->transferCount, + dmadrvDataSize1, + TransmitDmaComplete, + handle); +} + +/***************************************************************************//** + * @brief DMA transfer completion callback. Called by the DMA interrupt handler. + ******************************************************************************/ +static bool ReceiveDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam) +{ + CORE_DECLARE_IRQ_STATE; + UARTDRV_Handle_t handle; + UARTDRV_Buffer_t *buffer; + Ecode_t status; + (void)channel; + (void)sequenceNo; + handle = (UARTDRV_Handle_t)userParam; + status = GetTailBuffer(handle->rxQueue, &buffer); + + if (enableRxWhenSleeping) { + em1RequestRemove(handle); + } + + // If an abort was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return true; + } + + EFM_ASSERT(buffer != NULL); + +#if defined(USART_IF_FERR) + if (handle->type == uartdrvUartTypeUart + && (handle->peripheral.uart->IF & USART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; +#if defined(USART_HAS_SET_CLEAR) + handle->peripheral.uart->IF_CLR = USART_IF_FERR; +#else + handle->peripheral.uart->IFC = USART_IFC_FERR; +#endif + } else +#endif +#if defined(USART_IF_PERR) + if (handle->type == uartdrvUartTypeUart + && (handle->peripheral.uart->IF & USART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; +#if defined(USART_HAS_SET_CLEAR) + handle->peripheral.uart->IF_CLR = USART_IF_PERR; +#else + handle->peripheral.uart->IFC = USART_IFC_PERR; +#endif + } else +#endif +#if defined(LEUART_IF_FERR) + if (handle->type == uartdrvUartTypeLeuart + && (handle->peripheral.leuart->IF & LEUART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.leuart->IFC = LEUART_IFC_FERR; + } else +#endif +#if defined(LEUART_IF_PERR) + if (handle->type == uartdrvUartTypeLeuart + && (handle->peripheral.leuart->IF & LEUART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.leuart->IFC = LEUART_IFC_PERR; + } else +#endif +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) + if (handle->type == uartdrvUartTypeEuart + && (handle->peripheral.euart->IF & EUSART_IF_FERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_FRAME_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.euart->IF_CLR = EUSART_IF_FERR; + } else if (handle->type == uartdrvUartTypeEuart + && (handle->peripheral.euart->IF & EUSART_IF_PERR)) { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_PARITY_ERROR; + buffer->itemsRemaining = 0; + handle->peripheral.euart->IF_CLR = EUSART_IF_PERR; + } else +#endif + { + buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; + buffer->itemsRemaining = 0; + } + + CORE_ENTER_ATOMIC(); + + if (buffer->callback != NULL) { + buffer->callback(handle, buffer->transferStatus, buffer->data, buffer->transferCount - buffer->itemsRemaining); + } + // Dequeue the current tail Rx operation, check if more in queue + DequeueBuffer(handle->rxQueue, &buffer); + + if (handle->rxQueue->used > 0) { + GetTailBuffer(handle->rxQueue, &buffer); + StartReceiveDma(handle, buffer); + } else { +#if EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcSelfState = uartdrvFlowControlOff; + FcApplyState(handle); +#endif + handle->rxDmaActive = false; + + if (handle->fcType != uartdrvFlowControlHwUart) { + DisableReceiver(handle); + } + } + CORE_EXIT_ATOMIC(); + return true; +} + +/***************************************************************************//** + * @brief Calculate the number of sleeptimer ticks to flush the uart tx buffers. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +static uint32_t calculateSleeptimerTicksToFlushTxBuffers(UARTDRV_Handle_t handle) +{ + uint32_t baud = 0; + uint32_t ticks = 0; + + switch (handle->type) { +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + case uartdrvUartTypeLeuart: + baud = LEUART_BaudrateGet(handle->peripheral.leuart); + break; +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + case uartdrvUartTypeEuart: + baud = EUSART_BaudrateGet(handle->peripheral.euart); + break; +#endif +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + case uartdrvUartTypeUart: + default: + baud = USART_BaudrateGet(handle->peripheral.uart); + break; +#endif + } + + if (baud != 0) { // Avoid division by 0 + // Calculate the number of sleeptimer ticks for: + // 3 bytes: two in FIFO and one in shift register. + // 12 bits pr byte: one start bit, 8 data bits, parity and 2 stop bits. + ticks = (sl_sleeptimer_get_timer_frequency() * 3 * 12) / baud; + // Round up. + ticks++; + } + + return ticks; +} +#endif + +/***************************************************************************//** + * @brief Delayed transmit complete timer callback. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +static void TransmitDmaCompleteDelayed(sl_sleeptimer_timer_handle_t *timer_handle, void *userParam) +{ + (void)timer_handle; + UARTDRV_Handle_t uartdrv_handle = (UARTDRV_Handle_t)userParam; + uint32_t reg; + bool txComplete = false; + + // Check if transmit is completed by checking the uart registers. + switch (uartdrv_handle->type) { +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + case uartdrvUartTypeLeuart: + reg = uartdrv_handle->peripheral.leuart->STATUS; + txComplete = reg & LEUART_STATUS_TXC; + break; +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + case uartdrvUartTypeEuart: + reg = uartdrv_handle->peripheral.euart->STATUS; + txComplete = reg & EUSART_STATUS_TXC; + break; +#endif +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + case uartdrvUartTypeUart: + default: + reg = uartdrv_handle->peripheral.uart->STATUS; + txComplete = reg & USART_STATUS_TXC; + break; +#endif + } + + if (txComplete) { + // Remove the power manager request if completed. + em1RequestRemove(uartdrv_handle); +#if !defined(SL_CATALOG_KERNEL_PRESENT) + uartdrv_handle->sleep = SL_POWER_MANAGER_SLEEP; +#endif + } else { + // Restart the timer if not completed. + // May be the case if flow control is used. + uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(uartdrv_handle); + sl_sleeptimer_start_timer(&uartdrv_handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); + } +} +#endif + +/***************************************************************************//** + * @brief DMA transfer completion callback. Called by the DMA interrupt handler. + ******************************************************************************/ +static bool TransmitDmaComplete(unsigned int channel, + unsigned int sequenceNo, + void *userParam) +{ + CORE_DECLARE_IRQ_STATE; + UARTDRV_Handle_t handle; + UARTDRV_Buffer_t *buffer; + Ecode_t status; + (void)channel; + (void)sequenceNo; + + handle = (UARTDRV_Handle_t)userParam; + status = GetTailBuffer(handle->txQueue, &buffer); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + uint32_t ticks = calculateSleeptimerTicksToFlushTxBuffers(handle); + sl_sleeptimer_start_timer(&handle->delayedTxTimer, ticks, TransmitDmaCompleteDelayed, userParam, 0, 0); +#else + em1RequestRemove(handle); +#endif + + // If an abort was in progress when DMA completed, the ISR could be deferred + // until after the critical section. In this case, the buffers no longer + // exist, even though the DMA complete callback was called. + if (status == ECODE_EMDRV_UARTDRV_QUEUE_EMPTY) { + return true; + } + + EFM_ASSERT(buffer != NULL); + + buffer->transferStatus = ECODE_EMDRV_UARTDRV_OK; + buffer->itemsRemaining = 0; + + CORE_ENTER_ATOMIC(); + + if (buffer->callback != NULL) { + buffer->callback(handle, ECODE_EMDRV_UARTDRV_OK, buffer->data, buffer->transferCount); + } + // Dequeue the current tail Tx operation, check if more in queue + DequeueBuffer(handle->txQueue, &buffer); + + if (handle->txQueue->used > 0) { + GetTailBuffer(handle->txQueue, &buffer); + StartTransmitDma(handle, buffer); + } else { + handle->txDmaActive = false; +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) + if (handle->type == uartdrvUartTypeLeuart) { + // Clear TX DMA Wakeup request + handle->peripheral.leuart->CTRL &= ~LEUART_CTRL_TXDMAWU; + } +#endif + } + CORE_EXIT_ATOMIC(); + return true; +} + +/***************************************************************************//** + * @brief Parameter checking function for blocking transfer API functions. + ******************************************************************************/ +static Ecode_t CheckParams(UARTDRV_Handle_t handle, void *data, uint32_t count) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if ((data == NULL) || (count == 0) || (count > DMADRV_MAX_XFER_COUNT)) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + return ECODE_EMDRV_UARTDRV_OK; +} + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/***************************************************************************//** + * @brief Store U(S)ART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t * initData) +{ +#if defined(_USART_ROUTELOC0_MASK) + if (false) { +#if defined(USARTRF0) + } else if (handle->peripheral.uart == USARTRF0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocationRx); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.uart == USARTRF1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART0) + } else if (handle->peripheral.uart == USART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART1) + } else if (handle->peripheral.uart == USART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART1_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART2) + } else if (handle->peripheral.uart == USART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART2_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART2_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART3) + } else if (handle->peripheral.uart == USART3) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART3_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART3_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART3_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART3_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART4) + } else if (handle->peripheral.uart == USART4) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART4_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART4_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART4_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART4_RX_PIN(initData->portLocationRx); +#endif +#if defined(USART5) + } else if (handle->peripheral.uart == USART5) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART5_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART5_RX_PORT(initData->portLocationRx); + handle->txPin = AF_USART5_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_USART5_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART0) + } else if (handle->peripheral.uart == UART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART1) + } else if (handle->peripheral.uart == UART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART1_RX_PIN(initData->portLocationRx); +#endif +#if defined(UART2) + } else if (handle->peripheral.uart == UART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART2_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART2_RX_PORT(initData->portLocationRx); + handle->txPin = AF_UART2_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_UART2_RX_PIN(initData->portLocationRx); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_USART_ROUTE_MASK) + if (false) { +#if defined(USARTRF0) + } else if (handle->peripheral.uart == USARTRF0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF0_RX_PORT(initData->portLocation); + handle->txPin = AF_USARTRF0_TX_PIN(initData->portLocation); + handle->rxPin = AF_USARTRF0_RX_PIN(initData->portLocation); +#endif +#if defined(USARTRF1) + } else if (handle->peripheral.uart == USARTRF1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USARTRF1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USARTRF1_RX_PORT(initData->portLocation); + handle->txPin = AF_USARTRF1_TX_PIN(initData->portLocation); + handle->rxPin = AF_USARTRF1_RX_PIN(initData->portLocation); +#endif +#if defined(USART0) + } else if (handle->peripheral.uart == USART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART0_RX_PORT(initData->portLocation); + handle->txPin = AF_USART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART0_RX_PIN(initData->portLocation); +#endif +#if defined(USART1) + } else if (handle->peripheral.uart == USART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART1_RX_PORT(initData->portLocation); + handle->txPin = AF_USART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART1_RX_PIN(initData->portLocation); +#endif +#if defined(USART2) + } else if (handle->peripheral.uart == USART2) { + handle->txPort = (uartdrv_gpio_port_t)AF_USART2_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_USART2_RX_PORT(initData->portLocation); + handle->txPin = AF_USART2_TX_PIN(initData->portLocation); + handle->rxPin = AF_USART2_RX_PIN(initData->portLocation); +#endif +#if defined(UART0) + } else if (handle->peripheral.uart == UART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART0_RX_PORT(initData->portLocation); + handle->txPin = AF_UART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_UART0_RX_PIN(initData->portLocation); +#endif +#if defined(UART1) + } else if (handle->peripheral.uart == UART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_UART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_UART1_RX_PORT(initData->portLocation); + handle->txPin = AF_UART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_UART1_RX_PIN(initData->portLocation); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_GPIO_USART_ROUTEEN_MASK) + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; +#endif + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif // UART || USART + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief Store LEUART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t * initData) +{ +#if defined(_LEUART_ROUTELOC0_MASK) + if (false) { +#if defined(LEUART0) + } else if (handle->peripheral.leuart == LEUART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocationRx); + handle->txPin = AF_LEUART0_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocationRx); +#endif +#if defined(LEUART1) + } else if (handle->peripheral.leuart == LEUART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocationTx); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocationRx); + handle->txPin = AF_LEUART1_TX_PIN(initData->portLocationTx); + handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocationRx); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_USART_ROUTE_MASK) + if (false) { +#if defined(LEUART0) + } else if (handle->peripheral.leuart == LEUART0) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART0_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART0_RX_PORT(initData->portLocation); + handle->txPin = AF_LEUART0_TX_PIN(initData->portLocation); + handle->rxPin = AF_LEUART0_RX_PIN(initData->portLocation); +#endif +#if defined(LEUART1) + } else if (handle->peripheral.leuart == LEUART1) { + handle->txPort = (uartdrv_gpio_port_t)AF_LEUART1_TX_PORT(initData->portLocation); + handle->rxPort = (uartdrv_gpio_port_t)AF_LEUART1_RX_PORT(initData->portLocation); + handle->txPin = AF_LEUART1_TX_PIN(initData->portLocation); + handle->rxPin = AF_LEUART1_RX_PIN(initData->portLocation); +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + +#elif defined(_GPIO_USART_ROUTEEN_MASK) + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; +#endif + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) +/***************************************************************************//** + * @brief Store EUART GPIO pins into handle. + ******************************************************************************/ +static Ecode_t SetupGpioEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t * initData) +{ + handle->txPort = initData->txPort; + handle->txPin = initData->txPin; + handle->rxPort = initData->rxPort; + handle->rxPin = initData->rxPin; + + handle->ctsPort = initData->ctsPort; + handle->ctsPin = initData->ctsPin; + handle->rtsPort = initData->rtsPort; + handle->rtsPin = initData->rtsPin; + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief Configure/deconfigure U(S)ART GPIO pins. + ******************************************************************************/ +static Ecode_t ConfigGpio(UARTDRV_Handle_t handle, bool enable) +{ + if (enable) { + uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_PUSH_PULL, 1); + uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_INPUT_PULL, 1); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); + uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, true); + } else if (handle->fcType == uartdrvFlowControlHwUart) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_INPUT, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_PUSH_PULL, 0); + } +#endif + } else { + uartdrv_gpio_set_pin_mode(handle->txPort, handle->txPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rxPort, handle->rxPin, UARTDRV_GPIO_MODE_DISABLED, 0); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_config_ext_int(handle->ctsPort, handle->ctsPin, handle->ctsPin, true, true, false); + } else if (handle->fcType == uartdrvFlowControlHwUart) { + uartdrv_gpio_set_pin_mode(handle->ctsPort, handle->ctsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + uartdrv_gpio_set_pin_mode(handle->rtsPort, handle->rtsPin, UARTDRV_GPIO_MODE_DISABLED, 0); + } +#endif + } + return ECODE_EMDRV_UARTDRV_OK; +} + +#if (HANDLES_ARE_AVAILABLE) +/***************************************************************************//** + * @brief Add handle to handle array. + ******************************************************************************/ +static Ecode_t addHandle(UARTDRV_Handle_t handle) +{ + bool handleIsSet; + uint32_t handleIdx; + + // Set handler pointer in handler array + if (!uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + uartdrvHandle[handleIdx] = NULL; + } + uartdrvHandleIsInitialized = true; + } + + // Check if its already in the array + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == handle) { + return ECODE_EMDRV_UARTDRV_OK; + } + } + + // Insert handle + handleIsSet = false; + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == NULL) { + uartdrvHandle[handleIdx] = handle; + handleIsSet = true; + break; + } + } + + if (!handleIsSet) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief Remove handle from handle array. + ******************************************************************************/ +static Ecode_t removeHandle(UARTDRV_Handle_t handle) +{ + uint32_t handleIdx; + + if (uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + if (uartdrvHandle[handleIdx] == handle) { + uartdrvHandle[handleIdx] = NULL; + break; + } + } + } + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief Initialize FIFO queues for a handle. + ******************************************************************************/ +static void InitializeQueues(UARTDRV_Handle_t handle, + UARTDRV_Buffer_FifoQueue_t * rxQueue, + UARTDRV_Buffer_FifoQueue_t * txQueue) +{ + handle->rxQueue = rxQueue; + handle->rxQueue->head = 0; + handle->rxQueue->tail = 0; + handle->rxQueue->used = 0; + handle->rxDmaActive = false; + + handle->txQueue = txQueue; + handle->txQueue->head = 0; + handle->txQueue->tail = 0; + handle->txQueue->used = 0; + handle->txDmaActive = false; + + handle->IgnoreRestrain = false; +} + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) +/***************************************************************************//** + * @brief Initialize GPIO-driven flow control. + ******************************************************************************/ +static void InitializeGpioFlowControl(UARTDRV_Handle_t handle) +{ + GPIOINT_CallbackRegister(handle->ctsPin, HwFcManageClearToSend); + GPIOINT_Init(); + handle->fcPeerState = uartdrvFlowControlOn; + handle->fcSelfState = uartdrvFlowControlOn; + handle->fcSelfCfg = uartdrvFlowControlAuto; + FcApplyState(handle); +} +#endif + +/***************************************************************************//** + * @brief Initialize DMA channels for a handle. + ******************************************************************************/ +static Ecode_t InitializeDma(UARTDRV_Handle_t handle) +{ + // Initialize DMA. + DMADRV_Init(); + + if (DMADRV_AllocateChannel(&handle->txDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; + } + + if (DMADRV_AllocateChannel(&handle->rxDmaCh, NULL) != ECODE_EMDRV_DMADRV_OK) { + return ECODE_EMDRV_UARTDRV_DMA_ALLOC_ERROR; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +/// @endcond + +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) +/***************************************************************************//** + * @brief + * Initialize a U(S)ART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitUart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitUart(UARTDRV_Handle_t handle, + const UARTDRV_InitUart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + emRequestInit(handle); + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + + handle->peripheral.uart = initData->port; + handle->type = uartdrvUartTypeUart; +#if defined(_GPIO_USART_ROUTEEN_MASK) + handle->uartNum = initData->uartNum; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(USART0) + } else if (initData->port == USART0) { + handle->uartClock = cmuClock_USART0; + handle->txDmaSignal = dmadrvPeripheralSignal_USART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART0_RXDATAV; +#endif +#if defined(USART1) + } else if (initData->port == USART1) { + handle->uartClock = cmuClock_USART1; + handle->txDmaSignal = dmadrvPeripheralSignal_USART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART1_RXDATAV; +#endif +#if defined(USART2) + } else if (initData->port == USART2) { + handle->uartClock = cmuClock_USART2; + handle->txDmaSignal = dmadrvPeripheralSignal_USART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART2_RXDATAV; +#endif +#if defined(USART3) + } else if (initData->port == USART3) { + handle->uartClock = cmuClock_USART3; + handle->txDmaSignal = dmadrvPeripheralSignal_USART3_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART3_RXDATAV; +#endif +#if defined(USART4) + } else if (initData->port == USART4) { + handle->uartClock = cmuClock_USART4; + handle->txDmaSignal = dmadrvPeripheralSignal_USART4_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART4_RXDATAV; +#endif +#if defined(USART5) + } else if (initData->port == USART5) { + handle->uartClock = cmuClock_USART5; + handle->txDmaSignal = dmadrvPeripheralSignal_USART5_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_USART5_RXDATAV; +#endif +#if defined(UART0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (initData->port == UART0) { + handle->uartClock = cmuClock_UART0; + handle->txDmaSignal = dmadrvPeripheralSignal_UART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART0_RXDATAV; +#endif +#if defined(UART1) + } else if (initData->port == UART1) { + handle->uartClock = cmuClock_UART1; + handle->txDmaSignal = dmadrvPeripheralSignal_UART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART1_RXDATAV; +#endif +#if defined(UART2) + } else if (initData->port == UART2) { + handle->uartClock = cmuClock_UART2; + handle->txDmaSignal = dmadrvPeripheralSignal_UART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_UART2_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + usartInit.baudrate = initData->baudRate; + usartInit.stopbits = initData->stopBits; + usartInit.parity = initData->parity; + usartInit.oversampling = initData->oversampling; +#if defined(USART_CTRL_MVDIS) + usartInit.mvdis = initData->mvdis; +#endif + + // UARTDRV is fixed at 8 bit frames. + usartInit.databits = (USART_Databits_TypeDef)USART_FRAME_DATABITS_EIGHT; + + // Enable clocks +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->uartClock, true); + + // Init U(S)ART to default async config. + // Rx/Tx enable is done on demand + usartInit.enable = usartDisable; + USART_InitAsync(initData->port, &usartInit); + +#if defined(USART_ROUTEPEN_TXPEN) + initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 + & ~(_USART_ROUTELOC0_TXLOC_MASK + | _USART_ROUTELOC0_RXLOC_MASK)) + | (initData->portLocationTx + << _USART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx + << _USART_ROUTELOC0_RXLOC_SHIFT); + + initData->port->ROUTEPEN = USART_ROUTEPEN_TXPEN + | USART_ROUTEPEN_RXPEN; +#elif defined(USART_ROUTE_TXPEN) + initData->port->ROUTE = USART_ROUTE_TXPEN + | USART_ROUTE_RXPEN + | (initData->portLocation + << _USART_ROUTE_LOCATION_SHIFT); +#elif defined(GPIO_USART_ROUTEEN_TXPEN) + GPIO->USARTROUTE[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_TXPEN + | GPIO_USART_ROUTEEN_RXPEN; + GPIO->USARTROUTE[initData->uartNum].TXROUTE = + (initData->txPort << _GPIO_USART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_USART_TXROUTE_PIN_SHIFT); + GPIO->USARTROUTE[initData->uartNum].RXROUTE = + (initData->rxPort << _GPIO_USART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_USART_RXROUTE_PIN_SHIFT); +#endif + + if ((retVal = SetupGpioUart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + CORE_ENTER_ATOMIC(); + + // Configure hardware flow control pins and interrupt vectors +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHwUart) { +#if defined(UART_HW_FLOW_CONTROL_SUPPORT) +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) + initData->port->ROUTELOC1 = (initData->portLocationCts << _USART_ROUTELOC1_CTSLOC_SHIFT) + | (initData->portLocationRts << _USART_ROUTELOC1_RTSLOC_SHIFT); + initData->port->CTRLX |= USART_CTRLX_CTSEN; + initData->port->ROUTEPEN |= USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN; +#elif defined(USART_CTRLX_CTSEN) + GPIO->USARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; + initData->port->CTRLX_SET = USART_CTRLX_CTSEN; + GPIO->USARTROUTE_SET[initData->uartNum].RTSROUTE = + (initData->rtsPort << _GPIO_USART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_USART_RTSROUTE_PIN_SHIFT); + GPIO->USARTROUTE_SET[initData->uartNum].CTSROUTE = + (initData->ctsPort << _GPIO_USART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_USART_CTSROUTE_PIN_SHIFT); +#endif +#else + // Attempting to use USART hardware flow control on a device that does not + // support it. + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; +#endif + } else if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + + // Clear any false IRQ/DMA request + USART_IntClear(initData->port, ~0x0); + + // Enable Tx permanently as the Tx circuit consumes very little energy. + // Rx is enabled on demand as the Rx circuit consumes some energy due to + // continuous (over)sampling. + if (initData->fcType == uartdrvFlowControlHwUart) { + // Rx must be enabled permanently when using USART hw flow control + USART_Enable(initData->port, usartEnable); + } else { + USART_Enable(initData->port, usartEnableTx); + } + + // Discard false frames and/or IRQs + initData->port->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX; + + // Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif // UART || USART + +#if (defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2)) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Initialize a LEUART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitLeuart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitLeuart(UARTDRV_Handle_t handle, + const UARTDRV_InitLeuart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + LEUART_Init_TypeDef leuartInit = LEUART_INIT_DEFAULT; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + if (initData->fcType == uartdrvFlowControlHwUart) { + // LEUART doesn't support peripheral hw flow control + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + + handle->peripheral.leuart = initData->port; + handle->type = uartdrvUartTypeLeuart; +#if defined(_GPIO_USART_ROUTEEN_MASK) + handle->uartNum = initData->uartNum; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(LEUART0) + } else if (initData->port == LEUART0) { + handle->uartClock = cmuClock_LEUART0; + handle->txDmaSignal = dmadrvPeripheralSignal_LEUART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART0_RXDATAV; +#endif +#if defined(LEUART1) + } else if (initData->port == LEUART1) { + handle->uartClock = cmuClock_LEUART1; + handle->txDmaSignal = dmadrvPeripheralSignal_LEUART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_LEUART1_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + leuartInit.baudrate = initData->baudRate; + leuartInit.stopbits = initData->stopBits; + leuartInit.parity = initData->parity; + + // UARTDRV is fixed at 8 bit frames. + leuartInit.databits = (LEUART_Databits_TypeDef)LEUART_CTRL_DATABITS_EIGHT; + + // Enable clocks +#if defined(_CMU_HFPERCLKEN0_MASK) + CMU_ClockEnable(cmuClock_HFPER, true); +#endif + CMU_ClockEnable(cmuClock_GPIO, true); +#if defined(_CMU_HFBUSCLKEN0_MASK) || defined(CMU_HFCORECLKEN0_LE) + CMU_ClockEnable(cmuClock_HFLE, true); +#endif + + // Only try to use LF clock if LFXO or LFRCO is enabled and requested baudrate is low + if (CMU->STATUS & CMU_STATUS_LFXOENS + && (leuartInit.baudrate <= SystemLFXOClockGet())) { + CMU_CLOCK_SELECT_SET(LFB, LFXO); + } else if (CMU->STATUS & CMU_STATUS_LFRCOENS + && (leuartInit.baudrate <= SystemLFRCOClockGet())) { + CMU_CLOCK_SELECT_SET(LFB, LFRCO); + } else { + // Try to figure out the prescaler that will give us the best stability + CMU_CLOCK_SELECT_SET(LFB, HFCLKLE); + +#if defined(_SILICON_LABS_32B_SERIES_0) + // Attainable baudrate lies between refclk and refclk/128. For maximum + // accuracy, we want the reference clock to be as high as possible. + uint32_t refclk = CMU_ClockFreqGet(cmuClock_LFB); + uint8_t divisor = 0; + + while (leuartInit.baudrate <= (refclk >> (divisor + 7))) { + divisor++; + } + + // If we ran out of stretch on the clock division, error out. + if (divisor > (_CMU_LFBPRESC0_LEUART0_MASK >> _CMU_LFBPRESC0_LEUART0_SHIFT)) { + return ECODE_EMDRV_UARTDRV_CLOCK_ERROR; + } + CMU_ClockDivSet(handle->uartClock, (CMU_ClkDiv_TypeDef) (1 << divisor)); +#elif defined(_SILICON_LABS_32B_SERIES_1) + // Clock divider in LEUARTn is large enough for any baudrate. +#endif + } + + CMU_ClockEnable(handle->uartClock, true); + + // Init LEUART to default async config. + // Rx/Tx enable is done on demand + leuartInit.enable = leuartDisable; + LEUART_Init(initData->port, &leuartInit); + +#if defined(LEUART_ROUTEPEN_TXPEN) + initData->port->ROUTELOC0 = (initData->port->ROUTELOC0 + & ~(_LEUART_ROUTELOC0_TXLOC_MASK + | _LEUART_ROUTELOC0_RXLOC_MASK)) + | (initData->portLocationTx + << _LEUART_ROUTELOC0_TXLOC_SHIFT) + | (initData->portLocationRx + << _LEUART_ROUTELOC0_RXLOC_SHIFT); + + initData->port->ROUTEPEN = LEUART_ROUTEPEN_TXPEN + | LEUART_ROUTEPEN_RXPEN; +#else + initData->port->ROUTE = LEUART_ROUTE_TXPEN + | LEUART_ROUTE_RXPEN + | (initData->portLocation + << _LEUART_ROUTE_LOCATION_SHIFT); +#endif + + if ((retVal = SetupGpioLeuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + CORE_ENTER_ATOMIC(); + + // Configure hardware flow control pins and interrupt vectors +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + + // Clear any false IRQ/DMA request + LEUART_IntClear(initData->port, ~0x0); + + // Enable Tx permanently as the Tx circuit consumes very little energy. + // Rx is enabled on demand as the Rx circuit consumes some energy due to + // continuous (over)sampling. + LEUART_Enable(initData->port, leuartEnableTx); + + // Wait for previous write (TXEN) to sync before clearing FIFOs + while ((initData->port->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + + // Discard false frames and/or IRQs + initData->port->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX; + initData->port->CTRL |= LEUART_CTRL_RXDMAWU; + + // Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + // Wait for everything to be synchronized + while (initData->port->SYNCBUSY != 0U) { + } + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) || defined(DOXYGEN) + +/***************************************************************************//** + * @brief + * Initialize a EUART driver instance. + * + * @param[out] handle Pointer to a UARTDRV handle, refer to @ref + * UARTDRV_Handle_t. + * + * @param[in] initData Pointer to an initialization data structure, + * refer to @ref UARTDRV_InitEuart_t. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_InitEuart(UARTDRV_Handle_t handle, + const UARTDRV_InitEuart_t *initData) +{ + Ecode_t retVal; + CORE_DECLARE_IRQ_STATE; + #if defined(UARTDRV_USE_PERIPHERAL) + sl_hal_eusart_uart_config_t uartInit = SL_HAL_EUSART_UART_INIT_DEFAULT_HF; + sl_hal_eusart_uart_advanced_config_t uartAdvancedInit = SL_HAL_EUSART_UART_ADVANCED_INIT_DEFAULT; + #else + EUSART_UartInit_TypeDef uartInit = EUSART_UART_INIT_DEFAULT_HF; + EUSART_AdvancedInit_TypeDef uartAdvancedInit = EUSART_ADVANCED_INIT_DEFAULT; + #endif + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + if (initData == NULL) { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + memset(handle, 0, sizeof(UARTDRV_HandleData_t)); + + handle->peripheral.euart = initData->port; + handle->type = uartdrvUartTypeEuart; + handle->uartNum = initData->uartNum; + +#if (HANDLES_ARE_AVAILABLE) + retVal = addHandle(handle); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } +#endif + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + handle->fcType = initData->fcType; +#else + // Force init data to uartdrvFlowControlNone if flow control is excluded by EMDRV_UARTDRV_FLOW_CONTROL_ENABLE + handle->fcType = uartdrvFlowControlNone; +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) + handle->sleep = SL_POWER_MANAGER_IGNORE; +#endif + + // Set clocks and DMA requests according to available peripherals + if (false) { +#if defined(EUART0) + } else if (initData->port == EUART0) { + handle->uartClock = cmuClock_EUART0; + handle->txDmaSignal = dmadrvPeripheralSignal_EUART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUART0_RXDATAV; +#endif +#if defined(EUSART0) + } else if (initData->port == EUSART0) { + handle->uartClock = cmuClock_EUSART0; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART0_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART0_RXDATAV; +#endif +#if defined(EUSART1) + } else if (initData->port == EUSART1) { + handle->uartClock = cmuClock_EUSART1; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART1_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART1_RXDATAV; +#endif +#if defined(EUSART2) + } else if (initData->port == EUSART2) { + handle->uartClock = cmuClock_EUSART2; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART2_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART2_RXDATAV; +#endif +#if defined(EUSART3) + } else if (initData->port == EUSART3) { + handle->uartClock = cmuClock_EUSART3; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART3_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART3_RXDATAV; +#endif +#if defined(EUSART4) + } else if (initData->port == EUSART4) { + handle->uartClock = cmuClock_EUSART4; + handle->txDmaSignal = dmadrvPeripheralSignal_EUSART4_TXBL; + handle->rxDmaSignal = dmadrvPeripheralSignal_EUSART4_RXDATAV; +#endif + } else { + return ECODE_EMDRV_UARTDRV_PARAM_ERROR; + } + + // Common configurations to all EUART/EUSART instances. + handle->txDmaActive = false; + handle->rxDmaActive = false; + + InitializeQueues(handle, initData->rxQueue, initData->txQueue); + + // Enable clocks. + CMU_ClockEnable(cmuClock_GPIO, true); + CMU_ClockEnable(handle->uartClock, true); + if (initData->useLowFrequencyMode) { + CMU_ClockEnable(cmuClock_LFRCO, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + CMU_ClockEnable(cmuClock_EM23GRPACLK, true); + CMU_CLOCK_SELECT_SET(EM23GRPACLK, LFRCO); +#if defined(EUART_PRESENT) + CMU_CLOCK_SELECT_SET(EUART0, EM23GRPACLK); +#elif defined (EUSART_PRESENT) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM23GRPACLK); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_3) + CMU_CLOCK_SELECT_SET(EUSART0CLK, LFRCO); +#else + #error "Please assign a LF clock to EUSART instance" +#endif + } else { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + CMU_ClockEnable(cmuClock_EM01GRPACLK, true); +#if defined(EUART_PRESENT) + CMU_CLOCK_SELECT_SET(EUART0CLK, EM01GRPACLK); +#elif defined (EUSART_PRESENT) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPACLK); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) \ + || defined(_SILICON_LABS_32B_SERIES_3) + CMU_CLOCK_SELECT_SET(EUSART0CLK, EM01GRPCCLK); +#else + #error "Please assign a HF clock to EUSART instance" +#endif + } + +#if defined(EUART_COUNT) && (EUART_COUNT > 0) + GPIO->EUARTROUTE->ROUTEEN = GPIO_EUART_ROUTEEN_TXPEN; + GPIO->EUARTROUTE->TXROUTE = (initData->txPort + << _GPIO_EUART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_EUART_TXROUTE_PIN_SHIFT); + GPIO->EUARTROUTE->RXROUTE = (initData->rxPort + << _GPIO_EUART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_EUART_RXROUTE_PIN_SHIFT); +#elif defined(EUSART_COUNT) && (EUSART_COUNT > 0) + GPIO->EUSARTROUTE[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN; + GPIO->EUSARTROUTE[initData->uartNum].TXROUTE = (initData->txPort + << _GPIO_EUSART_TXROUTE_PORT_SHIFT) + | (initData->txPin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE[initData->uartNum].RXROUTE = (initData->rxPort + << _GPIO_EUSART_RXROUTE_PORT_SHIFT) + | (initData->rxPin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); + #endif + + if ((retVal = SetupGpioEuart(handle, initData)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if ((retVal = ConfigGpio(handle, true)) != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + +#if defined(UARTDRV_USE_PERIPHERAL) + // UARTDRV is fixed at 8 bit frames. + uartInit.data_bits = SL_HAL_EUSART_DATA_BITS_8; + + uartInit.clock_div = sl_hal_eusart_uart_calculate_clock_div(CMU_ClockFreqGet(cmuClock_EUSART0), initData->baudRate, initData->oversampling); + uartInit.stop_bits = initData->stopBits; + uartInit.parity = initData->parity; + uartInit.oversampling = initData->oversampling; + uartInit.majority_vote = initData->mvdis; + + uartAdvancedInit.dma_wakeup_on_rx = true; + uartAdvancedInit.dma_wakeup_on_tx = false; + uartInit.advanced_config = &uartAdvancedInit; +#else + // UARTDRV is fixed at 8 bit frames. + uartInit.databits = eusartDataBits8; + + uartInit.baudrate = initData->baudRate; + uartInit.stopbits = initData->stopBits; + uartInit.parity = initData->parity; + uartInit.oversampling = initData->oversampling; + uartInit.majorityVote = initData->mvdis; + + uartAdvancedInit.dmaWakeUpOnRx = true; + uartAdvancedInit.dmaWakeUpOnTx = false; + uartInit.advancedSettings = &uartAdvancedInit; +#endif + + CORE_ENTER_ATOMIC(); + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (initData->fcType == uartdrvFlowControlHwUart) { +#if defined(EUART_PRESENT) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; + GPIO->EUARTROUTE_SET[0].RTSROUTE = + (initData->rtsPort << _GPIO_EUART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_EUART_RTSROUTE_PIN_SHIFT); + GPIO->EUARTROUTE_SET[0].CTSROUTE = + (initData->ctsPort << _GPIO_EUART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_EUART_CTSROUTE_PIN_SHIFT); +#elif defined(EUSART_PRESENT) + GPIO->EUSARTROUTE_SET[initData->uartNum].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; + GPIO->EUSARTROUTE_SET[initData->uartNum].RTSROUTE = + (initData->rtsPort << _GPIO_EUSART_RTSROUTE_PORT_SHIFT) + | (initData->rtsPin << _GPIO_EUSART_RTSROUTE_PIN_SHIFT); + GPIO->EUSARTROUTE_SET[initData->uartNum].CTSROUTE = + (initData->ctsPort << _GPIO_EUSART_CTSROUTE_PORT_SHIFT) + | (initData->ctsPin << _GPIO_EUSART_CTSROUTE_PIN_SHIFT); +#endif + uartAdvancedInit.hwFlowControl = eusartHwFlowControlCtsAndRts; + } else if (initData->fcType == uartdrvFlowControlHw) { + InitializeGpioFlowControl(handle); + } +#endif + +#if defined(UARTDRV_USE_PERIPHERAL) + if (initData->useLowFrequencyMode) { + sl_hal_eusart_init_uart_lf(initData->port, &uartInit); + } else { + sl_hal_eusart_init_uart_hf(initData->port, &uartInit); + } + + // Set Tx enable to follow USART implementation. + uartdrv_eusart_enable(initData->port, UARTDRV_EUSART_ENABLE_TX); +#else + // Set Tx enable to follow USART implementation. + uartInit.enable = UARTDRV_EUSART_ENABLE_TX; + + if (initData->useLowFrequencyMode) { + EUSART_UartInitLf(initData->port, &uartInit); + } else { + EUSART_UartInitHf(initData->port, &uartInit); + } +#endif + +// Initialize DMA. + retVal = InitializeDma(handle); + + CORE_EXIT_ATOMIC(); + + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + return ECODE_EMDRV_UARTDRV_OK; +} +#endif + +/***************************************************************************//** + * @brief + * Deinitialize a UART driver instance. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_DeInit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + // Stop DMA transfers. + UARTDRV_Abort(handle, uartdrvAbortAll); + + // Do not leave any peer restrained on DeInit + UARTDRV_FlowControlSet(handle, uartdrvFlowControlOn); + + ConfigGpio(handle, false); + +#if (HANDLES_ARE_AVAILABLE) + removeHandle(handle); +#endif + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + handle->peripheral.uart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS; +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + LEUART_Reset(handle->peripheral.leuart); + while ((handle->peripheral.leuart->SYNCBUSY & LEUART_SYNCBUSY_CMD) != 0U) { + } + handle->peripheral.leuart->CMD = LEUART_CMD_RXDIS | LEUART_CMD_TXDIS; + +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + uartdrv_eusart_reset(handle->peripheral.euart); +#endif + } + + CMU_ClockEnable(handle->uartClock, false); + +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHw) { + GPIOINT_CallbackRegister(handle->ctsPin, NULL); + } +#endif + + DMADRV_FreeChannel(handle->txDmaCh); + DMADRV_FreeChannel(handle->rxDmaCh); + DMADRV_DeInit(); + + handle->rxQueue->head = 0; + handle->rxQueue->tail = 0; + handle->rxQueue->used = 0; + + handle->txQueue->head = 0; + handle->txQueue->tail = 0; + handle->txQueue->used = 0; + + emRequestDeinit(handle); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Abort ongoing UART transfers. + * + * @details + * All ongoing or queued operations of the given abort type will be aborted. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] type Abort type -- whether to abort only Tx, only Rx, or both. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success, @ref ECODE_EMDRV_UARTDRV_IDLE if + * the UART is idle. On failure, an appropriate UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_Abort(UARTDRV_Handle_t handle, UARTDRV_AbortType_t type) +{ + UARTDRV_Buffer_t *rxBuffer, *txBuffer; + CORE_DECLARE_IRQ_STATE; + + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + CORE_ENTER_ATOMIC(); + if ((type == uartdrvAbortTransmit) && (handle->txQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } else if ((type == uartdrvAbortReceive) && (handle->rxQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } else if ((type == uartdrvAbortAll) + && (handle->txQueue->used == 0) + && (handle->rxQueue->used == 0)) { + CORE_EXIT_ATOMIC(); + return ECODE_EMDRV_UARTDRV_IDLE; + } + + // Stop DMA transfers. + if ((type == uartdrvAbortTransmit) || (type == uartdrvAbortAll)) { + // Stop the current transfer + DMADRV_StopTransfer(handle->txDmaCh); + handle->txDmaActive = false; + + if (handle->txQueue->used > 0) { + // Update the transfer status of the active transfer + GetTailBuffer(handle->txQueue, &txBuffer); + DMADRV_TransferRemainingCount(handle->txDmaCh, + (int*)&txBuffer->itemsRemaining); + txBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // Dequeue all transfers and call callback + while (handle->txQueue->used > 0) { + DequeueBuffer(handle->txQueue, &txBuffer); + + // Call the callback with ABORTED error code + if (txBuffer->callback != NULL) { + txBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_ABORTED, + NULL, + txBuffer->itemsRemaining); + } + } + } + + // Wait for peripheral to finish cleaning up, to prevent framing errors + // on subsequent transfers + while (!(UARTDRV_GetPeripheralStatus(handle) & UARTDRV_STATUS_TXIDLE)) { + } + } + if ((type == uartdrvAbortReceive) || (type == uartdrvAbortAll)) { + // Stop the current transfer + DMADRV_StopTransfer(handle->rxDmaCh); + handle->rxDmaActive = false; + + if (handle->rxQueue->used > 0) { + // Update the transfer status of the active transfer + GetTailBuffer(handle->rxQueue, &rxBuffer); + DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int*)&rxBuffer->itemsRemaining); + rxBuffer->transferStatus = ECODE_EMDRV_UARTDRV_ABORTED; + + // Dequeue all transfers and call callback + while (handle->rxQueue->used > 0) { + DequeueBuffer(handle->rxQueue, &rxBuffer); + + // Call the callback with ABORTED error code + if (rxBuffer->callback != NULL) { + rxBuffer->callback(handle, + ECODE_EMDRV_UARTDRV_ABORTED, + NULL, + rxBuffer->itemsRemaining); + } + } + } + + // Disable the receiver + if (handle->fcType != uartdrvFlowControlHwUart) { + DisableReceiver(handle); + } + } + + if (handle->em1RequestCount > 0) { + em1RequestRemove(handle); + } + + CORE_EXIT_ATOMIC(); + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Return the status of the UART peripheral associated with a given handle. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * UART status value + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetPeripheralStatus(UARTDRV_Handle_t handle) +{ + UARTDRV_Status_t status = 0; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (handle->type == uartdrvUartTypeUart) { + status = handle->peripheral.uart->STATUS; + } else if (handle->type == uartdrvUartTypeLeuart) { + uint32_t reg = handle->peripheral.leuart->STATUS; + if (reg & LEUART_STATUS_TXENS) { + status |= UARTDRV_STATUS_TXEN; + } + if (reg & LEUART_STATUS_RXENS) { + status |= UARTDRV_STATUS_RXEN; + } + if (reg & LEUART_STATUS_RXBLOCK) { + status |= UARTDRV_STATUS_RXBLOCK; + } + if (reg & LEUART_STATUS_TXC) { + status |= UARTDRV_STATUS_TXC; + } + if (reg & LEUART_STATUS_TXBL) { + status |= UARTDRV_STATUS_TXBL; + } + if (reg & LEUART_STATUS_RXDATAV) { + status |= UARTDRV_STATUS_RXDATAV; + } +#if defined(LEUART_STATUS_TXIDLE) + if (reg & LEUART_STATUS_TXIDLE) { + status |= UARTDRV_STATUS_TXIDLE; + } +#endif + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + status = handle->peripheral.uart->STATUS; +#endif + } else if ((handle->type == uartdrvUartTypeEuart)) { + status = uartdrv_eusart_get_status(handle->peripheral.euart); + } +#else + status = handle->peripheral.uart->STATUS; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) + // Series 0 devices does not have the TXIDLE flag, so we emulate it + if ((status & UARTDRV_STATUS_TXC) || !(handle->hasTransmitted)) { + status |= UARTDRV_STATUS_TXIDLE; + } +#endif + + return status; +} + +/***************************************************************************//** + * @brief + * Return the number of queued receive operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * The number of queued operations. + ******************************************************************************/ +uint8_t UARTDRV_GetReceiveDepth(UARTDRV_Handle_t handle) +{ + return (uint8_t)handle->rxQueue->used; +} + +/***************************************************************************//** + * @brief + * Check the status of the UART and gather information about any ongoing + * receive operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[out] buffer Pointer to the current data buffer. + * + * @param[out] itemsReceived Current bytes received count. + * + * @param[out] itemsRemaining Current bytes remaining count. + * + * @return + * UART status. + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetReceiveStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *itemsReceived, + UARTDRV_Count_t *itemsRemaining) +{ + UARTDRV_Buffer_t *rxBuffer = NULL; + Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; + uint32_t remaining = 0; + + if (handle->rxQueue->used > 0) { + retVal = GetTailBuffer(handle->rxQueue, &rxBuffer); + DMADRV_TransferRemainingCount(handle->rxDmaCh, + (int*)&remaining); + } + + if (rxBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { + *itemsReceived = rxBuffer->transferCount - remaining; + *itemsRemaining = remaining; + *buffer = rxBuffer->data; + } else { + *itemsRemaining = 0; + *itemsReceived = 0; + *buffer = NULL; + } + + return UARTDRV_GetPeripheralStatus(handle); +} + +/***************************************************************************//** + * @brief + * Returns the number of queued transmit operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * The number of queued operations. + ******************************************************************************/ +uint8_t UARTDRV_GetTransmitDepth(UARTDRV_Handle_t handle) +{ + return (uint8_t)handle->txQueue->used; +} + +/***************************************************************************//** + * @brief + * Check the status of the UART and gather information about any ongoing + * transmit operations. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[out] buffer Pointer to the current data buffer. + * + * @param[out] itemsSent Current bytes sent count. + * + * @param[out] itemsRemaining Current bytes remaining count. + * + * @return + * UART status. + ******************************************************************************/ +UARTDRV_Status_t UARTDRV_GetTransmitStatus(UARTDRV_Handle_t handle, + uint8_t **buffer, + UARTDRV_Count_t *itemsSent, + UARTDRV_Count_t *itemsRemaining) +{ + UARTDRV_Buffer_t *txBuffer = NULL; + Ecode_t retVal = ECODE_EMDRV_UARTDRV_OK; + uint32_t remaining = 0; + + if (handle->txQueue->used > 0) { + retVal = GetTailBuffer(handle->txQueue, &txBuffer); + DMADRV_TransferRemainingCount(handle->txDmaCh, + (int*)&remaining); + } + + if (txBuffer && (retVal == ECODE_EMDRV_UARTDRV_OK)) { + *itemsSent = txBuffer->transferCount - remaining; + *itemsRemaining = remaining; + *buffer = txBuffer->data; + } else { + *itemsRemaining = 0; + *itemsSent = 0; + *buffer = NULL; + } + + return UARTDRV_GetPeripheralStatus(handle); +} + +/***************************************************************************//** + * @brief + * Set UART flow control state. Set nRTS pin if hardware flow control + * is enabled. Send XON/XOFF if software flow control is enabled. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] state Flow control state. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlSet(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) +{ +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType == uartdrvFlowControlHwUart) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + handle->fcSelfCfg = state; + if (state != uartdrvFlowControlAuto) { + handle->fcSelfState = state; + } + return FcApplyState(handle); +#else + (void) handle; + (void) state; + return ECODE_EMDRV_UARTDRV_OK; +#endif +} + +/***************************************************************************//** + * @brief + * Set peer UART flow control state. Pause/resume transmit accordingly. + * Only for manual software flow control. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] state Flow control state. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlSetPeerStatus(UARTDRV_Handle_t handle, UARTDRV_FlowControlState_t state) +{ + if ( (handle->fcType != uartdrvFlowControlSw) + || (state == uartdrvFlowControlAuto) ) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + + if (handle->fcPeerState != state) { + handle->fcPeerState = state; + if (state == uartdrvFlowControlOn) { + UARTDRV_ResumeTransmit(handle); + } else if (state == uartdrvFlowControlOff) { + UARTDRV_PauseTransmit(handle); + } + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Check the peer's flow control status. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * Returns uartdrvFlowControlOn if clear to send. + ******************************************************************************/ +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetPeerStatus(UARTDRV_Handle_t handle) +{ + return handle->fcPeerState; +} + +/***************************************************************************//** + * @brief + * Check the self flow control status. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * Returns uartdrvFlowControlOn if requesting to send. + ******************************************************************************/ +UARTDRV_FlowControlState_t UARTDRV_FlowControlGetSelfStatus(UARTDRV_Handle_t handle) +{ + return handle->fcSelfState; +} + +/***************************************************************************//** + * @brief + * Enable transmission when restrained by flow control. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_FlowControlIgnoreRestrain(UARTDRV_Handle_t handle) +{ + handle->IgnoreRestrain = true; + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Direct receive without interrupts or callback. This is a blocking function. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data pointer to buffer. + * + * @param[in] maxCount Maximum number of bytes to receive. + * + * @return + * Number of bytes received. + ******************************************************************************/ +UARTDRV_Count_t UARTDRV_ForceReceive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t maxCount) +{ + Ecode_t retVal; + uint32_t rxState; + UARTDRV_Count_t i = 0; + + retVal = CheckParams(handle, data, maxCount); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return 0; + } + + // Wait for DMA receive to complete and clear + while (handle->rxQueue->used > 0) { + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + rxState = (handle->peripheral.uart->STATUS & USART_STATUS_RXENS); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + rxState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_RXENS); +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + rxState = (handle->peripheral.euart->STATUS & EUSART_STATUS_RXENS); +#endif + } else { + EFM_ASSERT(false); + rxState = 0; + } + + if (!rxState) { + EnableReceiver(handle); + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + while ((handle->peripheral.uart->STATUS & USART_STATUS_RXDATAV) != 0U) { + *data = (uint8_t)handle->peripheral.uart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + while ((handle->peripheral.leuart->STATUS & LEUART_STATUS_RXDATAV) != 0U) { + *data = (uint8_t)handle->peripheral.leuart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + while ((handle->peripheral.euart->STATUS & EUSART_STATUS_RXFL) != 0U) { + *data = (uint8_t)handle->peripheral.euart->RXDATA; + data++; + i++; + if (i >= maxCount) { + break; + } + } +#endif + } + + data -= i; + + if (!rxState) { + DisableReceiver(handle); + } + return i; +} + +/***************************************************************************//** + * @brief + * Direct transmit without interrupts or callback. This is a blocking function. + * that ignores flow control if enabled. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data Pointer to the buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_ForceTransmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + uint32_t txState; + bool callDmaIrqHandler; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + + // Wait for DMA transmit to complete and clear + callDmaIrqHandler = CORE_IrqIsBlocked(UART_DMA_IRQ); // Loop invariant + while ((handle->txQueue->used > 0) && (!handle->txDmaPaused)) { + if (callDmaIrqHandler) { + UART_DMA_IRQHANDLER(); + } + } + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); +#endif +#if (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; +#endif + } else { + EFM_ASSERT(false); + txState = 0; + } + + if (!txState) { + EnableTransmitter(handle); + } + + handle->hasTransmitted = true; + + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + while (count-- != 0U) { + USART_Tx(handle->peripheral.uart, *data++); + } + // Wait for Tx completion + while (!(handle->peripheral.uart->STATUS & USART_STATUS_TXC)) { + } +#endif +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + } else if (handle->type == uartdrvUartTypeLeuart) { + while (count-- != 0U) { + LEUART_Tx(handle->peripheral.leuart, *data++); + } + // Wait for Tx completion + while (!(handle->peripheral.leuart->STATUS & LEUART_STATUS_TXC)) { + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeEuart) { + while (count-- != 0U) { + uartdrv_eusart_tx(handle->peripheral.euart, *data++); + } + while (~uartdrv_eusart_get_status(handle->peripheral.euart) & (EUSART_STATUS_TXC | EUSART_STATUS_TXIDLE)) { + } +#endif + } + + if (!txState) { + DisableTransmitter(handle); + } + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Pause an ongoing transmit operation. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_PauseTransmit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + // Pause the transfer if 1) pause counter is 0 + // 2) HW flow control hasn't already paused the DMA + if ( (handle->txDmaPaused == 0) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { + DMADRV_PauseTransfer(handle->txDmaCh); + } + // Increment counter to allow nested calls + handle->txDmaPaused++; + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a non-blocking receive. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A receive data buffer. + * + * @param[in] count A number of bytes received. + * + * @param[in] callback A transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_Receive(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback) +{ + Ecode_t retVal; + UARTDRV_Buffer_t outputBuffer; + UARTDRV_Buffer_t *queueBuffer; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + outputBuffer.data = data; + outputBuffer.transferCount = count; + outputBuffer.itemsRemaining = count; + outputBuffer.callback = callback; + outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + + retVal = EnqueueBuffer(handle->rxQueue, &outputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if (!(handle->rxDmaActive)) { + EnableReceiver(handle); + StartReceiveDma(handle, queueBuffer); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType != uartdrvFlowControlHwUart) { + handle->fcSelfState = uartdrvFlowControlOn; + FcApplyState(handle); + } +#endif + } // else: started by ReceiveDmaComplete + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a blocking receive. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A receive data buffer. + * + * @param[in] count A number of bytes received. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_ReceiveB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + UARTDRV_Buffer_t inputBuffer; + UARTDRV_Buffer_t *queueBuffer; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + inputBuffer.data = data; + inputBuffer.transferCount = count; + inputBuffer.itemsRemaining = count; + inputBuffer.callback = NULL; + inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + + retVal = EnqueueBuffer(handle->rxQueue, &inputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->rxQueue->used > 1) { + } + EnableReceiver(handle); +#if (EMDRV_UARTDRV_FLOW_CONTROL_ENABLE) + if (handle->fcType != uartdrvFlowControlHwUart) { + handle->fcSelfState = uartdrvFlowControlOn; + FcApplyState(handle); + } +#endif + StartReceiveDma(handle, queueBuffer); + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->rxDmaActive) { + } + return queueBuffer->transferStatus; +} + +/***************************************************************************//** + * @brief + * Resume a paused transmit operation. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. On failure, an appropriate + * UARTDRV @ref Ecode_t is returned. + ******************************************************************************/ +Ecode_t UARTDRV_ResumeTransmit(UARTDRV_Handle_t handle) +{ + if (handle == NULL) { + return ECODE_EMDRV_UARTDRV_ILLEGAL_HANDLE; + } + + if (handle->txDmaPaused > 0) { + // Resume the transfer if 1) pause counter is 1 + // 2) HW flow control doesn't need to pause the DMA + if ( (handle->txDmaPaused == 1) && (HwFcGetClearToSendPin(handle) == uartdrvFlowControlOn) ) { + DMADRV_ResumeTransfer(handle->txDmaCh); + } + handle->txDmaPaused--; + } else { + return ECODE_EMDRV_UARTDRV_ILLEGAL_OPERATION; + } + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a non-blocking transmit. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A transmit data buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @param[in] callback A transfer completion callback. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_Transmit(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count, + UARTDRV_Callback_t callback) +{ + Ecode_t retVal; + UARTDRV_Buffer_t inputBuffer; + UARTDRV_Buffer_t *queueBuffer; + uint32_t txState; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + inputBuffer.data = data; + inputBuffer.transferCount = count; + inputBuffer.itemsRemaining = count; + inputBuffer.callback = callback; + inputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); + } else { + EFM_ASSERT(false); + txState = 0; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; + } else { + EFM_ASSERT(false); + txState = 0; + } +#else + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + + if (!txState) { + EnableTransmitter(handle); + } + + retVal = EnqueueBuffer(handle->txQueue, &inputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + if (!(handle->txDmaActive)) { + CORE_ATOMIC_SECTION( + if (handle->txQueue->used > 0) { + StartTransmitDma(handle, queueBuffer); + handle->hasTransmitted = true; + } + ) + } // else: started by TransmitDmaComplete + + return ECODE_EMDRV_UARTDRV_OK; +} + +/***************************************************************************//** + * @brief + * Start a blocking transmit. + * + * @param[in] handle Pointer to a UART driver handle. + * + * @param[in] data A transmit data buffer. + * + * @param[in] count A number of bytes to transmit. + * + * @return + * @ref ECODE_EMDRV_UARTDRV_OK on success. + ******************************************************************************/ +Ecode_t UARTDRV_TransmitB(UARTDRV_Handle_t handle, + uint8_t *data, + UARTDRV_Count_t count) +{ + Ecode_t retVal; + UARTDRV_Buffer_t outputBuffer; + UARTDRV_Buffer_t *queueBuffer; + uint32_t txState; + + retVal = CheckParams(handle, data, count); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + outputBuffer.data = data; + outputBuffer.transferCount = count; + outputBuffer.itemsRemaining = count; + outputBuffer.callback = NULL; + outputBuffer.transferStatus = ECODE_EMDRV_UARTDRV_WAITING; + +#if defined(LEUART_COUNT) && (LEUART_COUNT > 0) && !defined(_SILICON_LABS_32B_SERIES_2) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeLeuart) { + txState = (handle->peripheral.leuart->STATUS & LEUART_STATUS_TXENS); + } else { + EFM_ASSERT(false); + txState = 0; + } +#elif (defined(EUART_COUNT) && (EUART_COUNT > 0)) || (defined(EUSART_COUNT) && (EUSART_COUNT > 0)) + if (false) { +#if (defined(UART_COUNT) && (UART_COUNT > 0)) || (defined(USART_COUNT) && (USART_COUNT > 0)) + } else if (handle->type == uartdrvUartTypeUart) { + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + } else if (handle->type == uartdrvUartTypeEuart) { + txState = uartdrv_eusart_get_status(handle->peripheral.euart) & EUSART_STATUS_TXENS; + } else { + EFM_ASSERT(false); + txState = 0; + } +#else + txState = (handle->peripheral.uart->STATUS & USART_STATUS_TXENS); +#endif + + if (!txState) { + EnableTransmitter(handle); + } + + retVal = EnqueueBuffer(handle->txQueue, &outputBuffer, &queueBuffer); + if (retVal != ECODE_EMDRV_UARTDRV_OK) { + return retVal; + } + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->txQueue->used > 1) { + } + StartTransmitDma(handle, queueBuffer); + handle->hasTransmitted = true; + // Active wait, the system must be in EM0 or EM1 anyway + while (handle->txDmaActive) { + } + + return queueBuffer->transferStatus; +} + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && !defined(SL_CATALOG_KERNEL_PRESENT) +sl_power_manager_on_isr_exit_t sl_uartdrv_sleep_on_isr_exit(void) +{ + sl_power_manager_on_isr_exit_t result = SL_POWER_MANAGER_IGNORE; + uint32_t handleIdx; + UARTDRV_Handle_t handle; + + if (uartdrvHandleIsInitialized) { + for (handleIdx = 0; handleIdx < EMDRV_UARTDRV_MAX_DRIVER_INSTANCES; handleIdx++) { + handle = uartdrvHandle[handleIdx]; + if (handle != NULL) { + if ((sl_power_manager_on_isr_exit_t)handle->sleep == SL_POWER_MANAGER_SLEEP) { + handle->sleep = SL_POWER_MANAGER_IGNORE; + result = SL_POWER_MANAGER_SLEEP; + } + } + } + } + + return result; +} +#endif + +/******** THE REST OF THE FILE IS DOCUMENTATION ONLY !**********************//** + * @addtogroup uartdrv UARTDRV - UART Driver + * @brief Universal Asynchronous Receiver/Transmitter Driver + * @{ + + @details + The source files for the UART driver library, uartdrv.c and uartdrv.h, are in the + emdrv/uartdrv folder. + + @n @section uartdrv_intro Introduction + The UART driver supports the UART capabilities of the USART, UART, and LEUART + peripherals. The driver is fully reentrant and supports multiple driver instances. + The driver does not buffer or queue data. However, it queues UART transmit + and receive operations. Both blocking and non-blocking transfer functions are + available. Non-blocking transfer functions report transfer completion with + callback functions. Transfers are done using DMA. Simple direct/forced + transmit and receive functions are also available. Note that these functions + are blocking and not suitable for low energy applications because they use CPU + polling. + + UART hardware flow control (CTS/RTS) is fully supported by the driver. UART + software flow control (XON/XOFF) is partially supported by the driver. For + more information about flow control support, see @ref uartdrv_fc. + + @note Transfer completion callback functions are called from within the DMA + interrupt handler with interrupts disabled. + + @n @section uartdrv_conf Configuration Options + + Some properties of the UARTDRV driver are compile-time configurable. These + properties are set in a uartdrv_config.h file. A template for this + file, containing default values, is in the emdrv/config folder. + To configure UARTDRV for your application, provide a custom configuration file, + or override the defines on the compiler command line. + These are the available configuration parameters with default values defined. + @code + + // Set to 1 to enable hardware flow control. + #define EMDRV_UARTDRV_FLOW_CONTROL_ENABLE 1 + + // Maximum number of driver instances. + #define EMDRV_UARTDRV_MAX_DRIVER_INSTANCES 4 + + // UART software flow control code: request peer to start Tx. + #define UARTDRV_FC_SW_XON 0x11 + + // UART software flow control code: request peer to stop Tx. + #define UARTDRV_FC_SW_XOFF 0x13 + @endcode + + The properties of each UART driver instance are set at run-time via the + @ref UARTDRV_InitUart_t data structure input parameter to the @ref UARTDRV_InitUart() + function for UART and USART peripherals, and the @ref UARTDRV_InitLeuart_t + data structure input parameter to the @ref UARTDRV_InitLeuart() function for + LEUART peripherals. + + @n @section uartdrv_api The API + + This section contains brief descriptions of the functions in the API. For more + information on input and output parameters and return values, + click on the hyperlinked function names. Most functions return an error + code, @ref ECODE_EMDRV_UARTDRV_OK is returned on success, + see ecode.h and uartdrv.h for other error codes. + + The application code must include @em uartdrv.h header file. + + @ref UARTDRV_InitUart(), @ref UARTDRV_InitLeuart() and @ref UARTDRV_DeInit() @n + These functions initialize and deinitialize the UARTDRV driver. Typically, + UARTDRV_InitUart() (for UART/USART) or + UARTDRV_InitLeuart() (for LEUART) are called once in + the startup code. + + @ref UARTDRV_GetReceiveStatus() and @ref UARTDRV_GetTransmitStatus() @n + Query the status of a current transmit or receive operations. Reports number + of items (frames) transmitted and remaining. + + @ref UARTDRV_GetReceiveDepth() and @ref UARTDRV_GetTransmitDepth() @n + Get the number of queued receive or transmit operations. + + @ref UARTDRV_Transmit(), UARTDRV_Receive() @n + UARTDRV_TransmitB(), UARTDRV_ReceiveB() @n + UARTDRV_ForceTransmit() and UARTDRV_ForceReceive() @n + Blocking and non-blocking transfer functions are included. + The blocking versions have an uppercase B (for Blocking) at the end of + their function name. Blocking functions do not return before the transfer + is complete. The non-blocking functions signal a transfer completion with a + callback function. @ref UARTDRV_ForceTransmit() and + @ref UARTDRV_ForceReceive() are also blocking. These two functions access + the UART peripheral directly without using DMA or interrupts. + @ref UARTDRV_ForceTransmit() does not respect flow control. + @ref UARTDRV_ForceReceive() forces RTS low. + + @ref UARTDRV_Abort() @n + Abort current transmit or receive operations and remove all queued + operations. + + @ref UARTDRV_FlowControlSet(), @ref UARTDRV_FlowControlGetSelfStatus(), @ref UARTDRV_FlowControlSetPeerStatus() and @ref UARTDRV_FlowControlGetPeerStatus() @n + Set and get flow control status of self or peer device. Note that the return + value from these two functions depends on the flow control mode set by + @ref UARTDRV_FlowControlSet(), @ref UARTDRV_InitUart(), or + @ref UARTDRV_InitLeuart(). + + @ref UARTDRV_FlowControlIgnoreRestrain() @n + Enables transmission when restrained by flow control. + + @ref UARTDRV_PauseTransmit() and @ref UARTDRV_ResumeTransmit() @n + Pause a currently active transmit operation by preventing the DMA from loading + the UART FIFO. Will not override HW flow control state (if applicable), but + can be used in conjunction. + + @n @section uartdrv_fc Flow Control Support + + If UART flow control is not required, make sure that + EMDRV_UARTDRV_FLOW_CONTROL_ENABLE is set to 0. This reduces the code size + and complexity of the driver. + + Both hardware and software flow control are supported. To + enable either of these, set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1 in + uartdrv_config.h. + + @n @subsection uartdrv_fc_hw Hardware Flow Control + + UART hardware flow control uses two additional pins for flow control + handshaking, the clear-to-send (CTS) and ready-to-send (RTS) pins. + RTS is an output and CTS is an input. These are active-low signals. + When CTS is high, the UART transmitter should stop sending frames. + A receiver should set RTS high when it is no longer capable of + receiving data. + + @par Peripheral Hardware Flow Control + + Newer devices natively support CTS/RTS in + the USART peripheral hardware. To enable hardware flow control, perform the + following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - In the @ref UARTDRV_InitUart_t struct passed to @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHwUart. + - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort + and rtsPin in the init struct. + - Also define the CTS and RTS locations by setting portLocationCts and + portLocationRts in the init struct. + + @par GPIO Hardware Flow Control + + To support hardware flow control on devices that don't have UART CTS/RTS + hardware support, the driver includes the GPIOINT driver to emulate a + hardware implementation of UART CTS/RTS flow control on these devices. + + To enable hardware flow control, perform the following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - UART/USART: In the @ref UARTDRV_InitUart_t struct passed to + @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlHw. + - LEUART: In the @ref UARTDRV_InitLeuart_t struct passed to + @ref UARTDRV_InitLeuart(), set + @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlHw. + - Define the pins for CTS and RTS by setting ctsPort, ctsPin, rtsPort and + rtsPin in the same init struct. + + @note Because of the limitations in GPIO interrupt hardware, you cannot select + CTS pins in multiple driver instances with the same pin number. For example, pin A0 and + B0 cannot serve as CTS pins in two concurrent driver instances. + + RTS is set high whenever there are no Rx operations queued. The UART + transmitter is halted when the CTS pin goes high. The transmitter completes + the current frame before halting. DMA transfers are also halted. + + @n @subsection uartdrv_fc_sw Software Flow Control + + UART software flow control uses in-band signaling, meaning the receiver sends + special flow control characters to the transmitter and thereby removes + the need for dedicated wires for flow control. The two symbols + UARTDRV_FC_SW_XON and UARTDRV_FC_SW_XOFF are defined in uartdrv_config.h. + + To enable support for software flow control, perform the following steps: + + - Set EMDRV_UARTDRV_FLOW_CONTROL_ENABLE to 1. + - UART/USART: In the @ref UARTDRV_InitUart_t structure passed to + @ref UARTDRV_InitUart(), set + @ref UARTDRV_InitUart_t.fcType = uartdrvFlowControlSw. + - LEUART: In the @ref UARTDRV_InitLeuart_t structure passed to + @ref UARTDRV_InitLeuart(), set + @ref UARTDRV_InitLeuart_t.fcType = uartdrvFlowControlSw. + + @note Software flow control is partial only. + + The application must monitor buffers and make decisions on when to send XON/ + XOFF. XON/XOFF can be sent to the peer using @ref UARTDRV_FlowControlSet(). + Though @ref UARTDRV_FlowControlSet() will pause the active transmit operation + to send a flow control character, there is no way to guarantee the order. + If the application implements a specific packet format where the flow control + codes may appear only in fixed positions, the application should not + use @ref UARTDRV_FlowControlSet() but implement read and write of XON/XOFF + into packet buffers. If the application code fully implements all the flow + control logic, EMDRV_UARTDRV_FLOW_CONTROL_ENABLE should be set to 0 + to reduce code space. + + @n @section uartdrv_example Example + @if DOXYDOC_P1_DEVICE + @if DOXYDOC_EFM32G + @include uartdrv_example_p1_nomvdis.c + @endif + @if DOXYDOC_EZR32HG + @include uartdrv_example_p1_usart0.c + @endif + @ifnot (DOXYDOC_EFM32G || DOXYDOC_EZR32HG) + @include uartdrv_example_p1.c + @endif + @endif + @if DOXYDOC_P2_DEVICE + @include uartdrv_example_p2.c + @endif + @if DOXYDOC_S2_DEVICE + @include uartdrv_example_s2.c + @endif + + * @} end group uartdrv *********************************************************/ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h index f3c14ac..bffa5c2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_assert.h @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief Emlib peripheral API "assert" implementation. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_ASSERT_H -#define EM_ASSERT_H - -#include "sl_assert.h" - -#endif /* EM_ASSERT_H */ +/***************************************************************************//** + * @file + * @brief Emlib peripheral API "assert" implementation. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_ASSERT_H +#define EM_ASSERT_H + +#include "sl_assert.h" + +#endif /* EM_ASSERT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h index bd2583b..756e362 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_burtc.h @@ -1,473 +1,473 @@ -/***************************************************************************//** - * @file - * @brief Backup Real Time Counter (BURTC) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_BURTC_H -#define EM_BURTC_H - -#include "em_device.h" -#if defined(BURTC_PRESENT) - -#include -#include "sl_assert.h" -#include "em_bus.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup burtc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** BURTC clock divisors. These values are valid for the BURTC prescaler. */ -#define burtcClkDiv_1 1 /**< Divide clock by 1. */ -#define burtcClkDiv_2 2 /**< Divide clock by 2. */ -#define burtcClkDiv_4 4 /**< Divide clock by 4. */ -#define burtcClkDiv_8 8 /**< Divide clock by 8. */ -#define burtcClkDiv_16 16 /**< Divide clock by 16. */ -#define burtcClkDiv_32 32 /**< Divide clock by 32. */ -#define burtcClkDiv_64 64 /**< Divide clock by 64. */ -#define burtcClkDiv_128 128 /**< Divide clock by 128. */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** BURTC clock selection. */ -typedef enum { - /** Ultra low frequency (1 kHz) clock. */ - burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, - /** Low frequency RC oscillator. */ - burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, - /** Low frequency crystal oscillator. */ - burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO -} BURTC_ClkSel_TypeDef; - -/** BURTC mode of operation. */ -typedef enum { - /** Disable BURTC */ - burtcModeDisable = BURTC_CTRL_MODE_DISABLE, - /** Enable and start BURTC counter in EM0 to EM2. */ - burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, - /** Enable and start BURTC counter in EM0 to EM3. */ - burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, - /** Enable and start BURTC counter in EM0 to EM4. */ - burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, -} BURTC_Mode_TypeDef; - -/** BURTC low power mode. */ -typedef enum { - /** Low Power Mode is disabled. */ - burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, - /** Low Power Mode is always enabled. */ - burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, - /** Low Power Mode when system enters backup mode. */ - burtcLPBU = BURTC_LPMODE_LPMODE_BUEN -} BURTC_LP_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** BURTC initialization structure for Series 0 devices. */ -typedef struct { - bool enable; /**< Enable BURTC after initialization (starts counter). */ - - BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ - bool debugRun; /**< If true, counter will keep running under debug halt. */ - BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ - uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ - - uint32_t lowPowerComp; /**< Number of least significant clock bits to ignore in low power mode. */ - bool timeStamp; /**< Enable time stamp on entering backup power domain. */ - - bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ - - BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ -} BURTC_Init_TypeDef; - -/** Default configuration for BURTC initialization structure. */ -#define BURTC_INIT_DEFAULT \ - { \ - true, \ - burtcModeEM2, \ - false, \ - burtcClkSelULFRCO, \ - burtcClkDiv_1, \ - 0, \ - true, \ - false, \ - burtcLPDisable, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) -/** BURTC initialization structure for Series 2 devices. */ -typedef struct { - bool start; /**< Start BURTC after initialization */ - bool debugRun; /**< If true, counter will keep running under debug halt */ - uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ - bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ - bool em4comp; /**< Enable EM4 wakeup on compare match. */ - bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ -} BURTC_Init_TypeDef; - -/** Default configuration for BURTC init structure */ -#define BURTC_INIT_DEFAULT \ - { \ - true, \ - false, \ - 1, \ - 0, \ - false, \ - false, \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Clear one or more pending BURTC interrupts. - * - * @param[in] flags - * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed - * together to clear multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntClear(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IF_CLR = flags; -#else - BURTC->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more BURTC interrupts. - * - * @param[in] flags - * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed - * together to disable multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntDisable(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IEN_CLR = flags; -#else - BURTC->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more BURTC interrupts. - * - * @note - * Depending on use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling - * if a pending interrupt should be ignored. - * - * @param[in] flags - * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed - * together to set multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntEnable(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IEN_SET = flags; -#else - BURTC->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending BURTC interrupt flags. - * - * @note - * This function does not clear the event bits. - * - * @return - * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed - * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_IntGet(void) -{ - return BURTC->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending BURTC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * Pending BURTC interrupt sources that is also enabled. Returns a set of - * interrupt flags OR-ed together for multiple interrupt sources in the - * BURTC module (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) -{ - uint32_t tmp; - - /* Get enabled interrupts */ - tmp = BURTC->IEN; - - /* Return set interrupts */ - return BURTC->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending BURTC interrupts from SW. - * - * @param[in] flags - * BURTC interrupt sources to set to pending. Use a set of interrupt flags - * OR-ed together to set multiple interrupt sources for the BURTC module - * (BURTC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void BURTC_IntSet(uint32_t flags) -{ -#if defined(BURTC_HAS_SET_CLEAR) - BURTC->IF_SET = flags; -#else - BURTC->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Status of BURTC RAM, timestamp and LP Mode - * - * @return A mask logically OR-ed status bits - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_Status(void) -{ - return BURTC->STATUS; -} - -#if defined(BURTC_CMD_CLRSTATUS) -/***************************************************************************//** - * @brief - * Clear and reset BURTC status register - ******************************************************************************/ -__STATIC_INLINE void BURTC_StatusClear(void) -{ - BURTC->CMD = BURTC_CMD_CLRSTATUS; -} -#endif - -/***************************************************************************//** - * @brief - * Wait for the BURTC to complete all synchronization of register changes - * and commands. - ******************************************************************************/ -__STATIC_INLINE void BURTC_SyncWait(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { - /* Wait for previous synchronization to finish */ - } -#else - while (BURTC->SYNCBUSY != 0U) { - /* Wait for previous synchronization to finish */ - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Start BURTC counter. - * - * This function will send a start command to the BURTC peripheral. The BURTC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref BURTC_SyncWait() function can be used to wait for the start command - * to be executed. - * - * @note - * This function requires the BURTC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Start(void) -{ - BURTC_SyncWait(); - BURTC->CMD = BURTC_CMD_START; -} - -/***************************************************************************//** - * @brief - * Stop the BURTC counter. - * - * This function will send a stop command to the BURTC peripheral. The BURTC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref BURTC_SyncWait() function can be used to wait for the stop command - * to be executed. - * - * @note - * This function requires the BURTC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Stop(void) -{ - BURTC_SyncWait(); - BURTC->CMD = BURTC_CMD_STOP; -} -#endif - -/***************************************************************************//** - * @brief Get BURTC counter. - * - * @return - * BURTC counter value - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_CounterGet(void) -{ - return BURTC->CNT; -} - -#if defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief Get BURTC timestamp for entering BU. - * - * @return - * BURTC Time Stamp value - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_TimestampGet(void) -{ - return BURTC->TIMESTAMP; -} - -/***************************************************************************//** - * @brief Freeze register updates until enabled. - * @param[in] enable If true, registers are not updated until enabled again. - ******************************************************************************/ -__STATIC_INLINE void BURTC_FreezeEnable(bool enable) -{ - BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); -} - -/***************************************************************************//** - * @brief Shut down power to retention register bank. - * @param[in] enable - * If true, shuts off power to retention registers. - * @note - * When power retention is disabled, it can't be enabled again (until - * reset). - ******************************************************************************/ -__STATIC_INLINE void BURTC_Powerdown(bool enable) -{ - BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); -} - -/***************************************************************************//** - * @brief - * Set a value in one of the retention registers. - * - * @param[in] num - * Register to set - * @param[in] data - * Value to put into register - ******************************************************************************/ -__STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) -{ - EFM_ASSERT(num <= 127); - - BURTC->RET[num].REG = data; -} - -/***************************************************************************//** - * @brief - * Read a value from one of the retention registers. - * - * @param[in] num - * Retention Register to read - * - * @return - * Value of the retention register - ******************************************************************************/ -__STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) -{ - EFM_ASSERT(num <= 127); - - return BURTC->RET[num].REG; -} -#endif - -/***************************************************************************//** - * @brief - * Lock BURTC registers, which will protect from writing new config settings. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Lock(void) -{ - BURTC->LOCK = 0x0; -} - -/***************************************************************************//** - * @brief - * Unlock BURTC registers, which will enable write access to change configuration. - ******************************************************************************/ -__STATIC_INLINE void BURTC_Unlock(void) -{ - BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; -} - -void BURTC_Reset(void); -void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); -void BURTC_Enable(bool enable); -void BURTC_CounterReset(void); -void BURTC_CompareSet(unsigned int comp, uint32_t value); -uint32_t BURTC_CompareGet(unsigned int comp); -#if defined(_BURTC_CTRL_MASK) -uint32_t BURTC_ClockFreqGet(void); -#endif - -/** @} (end addtogroup burtc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* BURTC_PRESENT */ -#endif /* EM_BURTC_H */ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BURTC_H +#define EM_BURTC_H + +#include "em_device.h" +#if defined(BURTC_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup burtc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** BURTC clock divisors. These values are valid for the BURTC prescaler. */ +#define burtcClkDiv_1 1 /**< Divide clock by 1. */ +#define burtcClkDiv_2 2 /**< Divide clock by 2. */ +#define burtcClkDiv_4 4 /**< Divide clock by 4. */ +#define burtcClkDiv_8 8 /**< Divide clock by 8. */ +#define burtcClkDiv_16 16 /**< Divide clock by 16. */ +#define burtcClkDiv_32 32 /**< Divide clock by 32. */ +#define burtcClkDiv_64 64 /**< Divide clock by 64. */ +#define burtcClkDiv_128 128 /**< Divide clock by 128. */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC clock selection. */ +typedef enum { + /** Ultra low frequency (1 kHz) clock. */ + burtcClkSelULFRCO = BURTC_CTRL_CLKSEL_ULFRCO, + /** Low frequency RC oscillator. */ + burtcClkSelLFRCO = BURTC_CTRL_CLKSEL_LFRCO, + /** Low frequency crystal oscillator. */ + burtcClkSelLFXO = BURTC_CTRL_CLKSEL_LFXO +} BURTC_ClkSel_TypeDef; + +/** BURTC mode of operation. */ +typedef enum { + /** Disable BURTC */ + burtcModeDisable = BURTC_CTRL_MODE_DISABLE, + /** Enable and start BURTC counter in EM0 to EM2. */ + burtcModeEM2 = BURTC_CTRL_MODE_EM2EN, + /** Enable and start BURTC counter in EM0 to EM3. */ + burtcModeEM3 = BURTC_CTRL_MODE_EM3EN, + /** Enable and start BURTC counter in EM0 to EM4. */ + burtcModeEM4 = BURTC_CTRL_MODE_EM4EN, +} BURTC_Mode_TypeDef; + +/** BURTC low power mode. */ +typedef enum { + /** Low Power Mode is disabled. */ + burtcLPDisable = BURTC_LPMODE_LPMODE_DISABLE, + /** Low Power Mode is always enabled. */ + burtcLPEnable = BURTC_LPMODE_LPMODE_ENABLE, + /** Low Power Mode when system enters backup mode. */ + burtcLPBU = BURTC_LPMODE_LPMODE_BUEN +} BURTC_LP_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** BURTC initialization structure for Series 0 devices. */ +typedef struct { + bool enable; /**< Enable BURTC after initialization (starts counter). */ + + BURTC_Mode_TypeDef mode; /**< Configure energy mode operation. */ + bool debugRun; /**< If true, counter will keep running under debug halt. */ + BURTC_ClkSel_TypeDef clkSel; /**< Select clock source. */ + uint32_t clkDiv; /**< Clock divider; for ULFRCO 1Khz or 2kHz operation. */ + + uint32_t lowPowerComp; /**< Number of least significant clock bits to ignore in low power mode. */ + bool timeStamp; /**< Enable time stamp on entering backup power domain. */ + + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart). */ + + BURTC_LP_TypeDef lowPowerMode; /**< Low power operation mode, requires LFXO or LFRCO. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC initialization structure. */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + burtcModeEM2, \ + false, \ + burtcClkSelULFRCO, \ + burtcClkDiv_1, \ + 0, \ + true, \ + false, \ + burtcLPDisable, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) +/** BURTC initialization structure for Series 2 devices. */ +typedef struct { + bool start; /**< Start BURTC after initialization */ + bool debugRun; /**< If true, counter will keep running under debug halt */ + uint32_t clkDiv; /**< Clock divider. Supported range is 1-32768 */ + bool compare0Top; /**< Set if Compare Value 0 is also top value (counter restart) */ + bool em4comp; /**< Enable EM4 wakeup on compare match. */ + bool em4overflow; /**< Enable EM4 wakeup on counter overflow. */ +} BURTC_Init_TypeDef; + +/** Default configuration for BURTC init structure */ +#define BURTC_INIT_DEFAULT \ + { \ + true, \ + false, \ + 1, \ + 0, \ + false, \ + false, \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Clear one or more pending BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntClear(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_CLR = flags; +#else + BURTC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more BURTC interrupts. + * + * @param[in] flags + * BURTC interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntDisable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_CLR = flags; +#else + BURTC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more BURTC interrupts. + * + * @note + * Depending on use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using BURTC_IntClear() prior to enabling + * if a pending interrupt should be ignored. + * + * @param[in] flags + * BURTC interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntEnable(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IEN_SET = flags; +#else + BURTC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending BURTC interrupt flags. + * + * @note + * This function does not clear the event bits. + * + * @return + * Pending BURTC interrupt sources. Returns a set of interrupt flags OR-ed + * together for multiple interrupt sources in the BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGet(void) +{ + return BURTC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending BURTC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending BURTC interrupt sources that is also enabled. Returns a set of + * interrupt flags OR-ed together for multiple interrupt sources in the + * BURTC module (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Get enabled interrupts */ + tmp = BURTC->IEN; + + /* Return set interrupts */ + return BURTC->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending BURTC interrupts from SW. + * + * @param[in] flags + * BURTC interrupt sources to set to pending. Use a set of interrupt flags + * OR-ed together to set multiple interrupt sources for the BURTC module + * (BURTC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void BURTC_IntSet(uint32_t flags) +{ +#if defined(BURTC_HAS_SET_CLEAR) + BURTC->IF_SET = flags; +#else + BURTC->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Status of BURTC RAM, timestamp and LP Mode + * + * @return A mask logically OR-ed status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_Status(void) +{ + return BURTC->STATUS; +} + +#if defined(BURTC_CMD_CLRSTATUS) +/***************************************************************************//** + * @brief + * Clear and reset BURTC status register + ******************************************************************************/ +__STATIC_INLINE void BURTC_StatusClear(void) +{ + BURTC->CMD = BURTC_CMD_CLRSTATUS; +} +#endif + +/***************************************************************************//** + * @brief + * Wait for the BURTC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +__STATIC_INLINE void BURTC_SyncWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((BURTC->EN != 0U) && (BURTC->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (BURTC->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Start BURTC counter. + * + * This function will send a start command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the start command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Start(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_START; +} + +/***************************************************************************//** + * @brief + * Stop the BURTC counter. + * + * This function will send a stop command to the BURTC peripheral. The BURTC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref BURTC_SyncWait() function can be used to wait for the stop command + * to be executed. + * + * @note + * This function requires the BURTC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Stop(void) +{ + BURTC_SyncWait(); + BURTC->CMD = BURTC_CMD_STOP; +} +#endif + +/***************************************************************************//** + * @brief Get BURTC counter. + * + * @return + * BURTC counter value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_CounterGet(void) +{ + return BURTC->CNT; +} + +#if defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief Get BURTC timestamp for entering BU. + * + * @return + * BURTC Time Stamp value + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_TimestampGet(void) +{ + return BURTC->TIMESTAMP; +} + +/***************************************************************************//** + * @brief Freeze register updates until enabled. + * @param[in] enable If true, registers are not updated until enabled again. + ******************************************************************************/ +__STATIC_INLINE void BURTC_FreezeEnable(bool enable) +{ + BUS_RegBitWrite(&BURTC->FREEZE, _BURTC_FREEZE_REGFREEZE_SHIFT, enable); +} + +/***************************************************************************//** + * @brief Shut down power to retention register bank. + * @param[in] enable + * If true, shuts off power to retention registers. + * @note + * When power retention is disabled, it can't be enabled again (until + * reset). + ******************************************************************************/ +__STATIC_INLINE void BURTC_Powerdown(bool enable) +{ + BUS_RegBitWrite(&BURTC->POWERDOWN, _BURTC_POWERDOWN_RAM_SHIFT, enable); +} + +/***************************************************************************//** + * @brief + * Set a value in one of the retention registers. + * + * @param[in] num + * Register to set + * @param[in] data + * Value to put into register + ******************************************************************************/ +__STATIC_INLINE void BURTC_RetRegSet(uint32_t num, uint32_t data) +{ + EFM_ASSERT(num <= 127); + + BURTC->RET[num].REG = data; +} + +/***************************************************************************//** + * @brief + * Read a value from one of the retention registers. + * + * @param[in] num + * Retention Register to read + * + * @return + * Value of the retention register + ******************************************************************************/ +__STATIC_INLINE uint32_t BURTC_RetRegGet(uint32_t num) +{ + EFM_ASSERT(num <= 127); + + return BURTC->RET[num].REG; +} +#endif + +/***************************************************************************//** + * @brief + * Lock BURTC registers, which will protect from writing new config settings. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Lock(void) +{ + BURTC->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock BURTC registers, which will enable write access to change configuration. + ******************************************************************************/ +__STATIC_INLINE void BURTC_Unlock(void) +{ + BURTC->LOCK = BURTC_LOCK_LOCKKEY_UNLOCK; +} + +void BURTC_Reset(void); +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit); +void BURTC_Enable(bool enable); +void BURTC_CounterReset(void); +void BURTC_CompareSet(unsigned int comp, uint32_t value); +uint32_t BURTC_CompareGet(unsigned int comp); +#if defined(_BURTC_CTRL_MASK) +uint32_t BURTC_ClockFreqGet(void); +#endif + +/** @} (end addtogroup burtc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* BURTC_PRESENT */ +#endif /* EM_BURTC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h index 6b2e977..9ae27b4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_bus.h @@ -1,341 +1,341 @@ -/***************************************************************************//** - * @file - * @brief RAM and peripheral bit-field set and clear API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_BUS_H -#define EM_BUS_H - -#include "sl_assert.h" -#include "em_core.h" -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup bus BUS - Bitfield Read/Write - * @brief BUS register and RAM bit/field read/write API - * @details - * API to perform bit-band and field set/clear access to RAM and peripherals. - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Perform a single-bit write operation on a 32-bit word in RAM. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read-modify-write operation on a single bit write on a 32-bit word in RAM. - * See the reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. Bit- - * banding is a multi cycle read-modify-write bus operation. RAM bit-banding is - * performed using the memory alias region at BITBAND_RAM_BASE. - * - * @param[in] addr An ddress of a 32-bit word in RAM. - * - * @param[in] bit A bit position to write, 0-31. - * - * @param[in] val A value to set bit to, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, - unsigned int bit, - unsigned int val) -{ -#if defined(BITBAND_RAM_BASE) - uint32_t aliasAddr = - BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - *(volatile uint32_t *)aliasAddr = (uint32_t)val; -#else - uint32_t tmp = *addr; - - /* Make sure val is not more than 1 because only one bit needs to be set. */ - *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit read operation on a 32-bit word in RAM. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. - * RAM bit-banding is performed using the memory alias region - * at BITBAND_RAM_BASE. - * - * @param[in] addr RAM address. - * - * @param[in] bit A bit position to read, 0-31. - * - * @return - * The requested bit shifted to bit position 0 in the return value. - ******************************************************************************/ -__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, - unsigned int bit) -{ -#if defined(BITBAND_RAM_BASE) - uint32_t aliasAddr = - BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - return *(volatile uint32_t *)aliasAddr; -#else - return ((*addr) >> bit) & 1UL; -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit write operation on a peripheral register. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read-modify-write operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. Bit- - * banding is a multi cycle read-modify-write bus operation. Peripheral register - * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] bit A bit position to write, 0-31. - * - * @param[in] val A value to set bit to, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, - unsigned int bit, - unsigned int val) -{ - EFM_ASSERT(bit < 32U); -#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) - uint32_t aliasAddr; - if (val != 0U) { - aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; - } else { - aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; - } - *(volatile uint32_t *)aliasAddr = 1UL << bit; -#elif defined(BITBAND_PER_BASE) - uint32_t aliasAddr = - BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); - - *(volatile uint32_t *)aliasAddr = (uint32_t)val; -#else - uint32_t tmp = *addr; - - /* Make sure val is not more than 1 because only one bit needs to be set. */ - *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a single-bit read operation on a peripheral register. - * - * @details - * This function uses Cortex-M bit-banding hardware to perform an atomic - * read operation on a single register bit. See the - * reference manual for more details about bit-banding. - * - * @note - * This function is atomic on Cortex-M cores with bit-banding support. - * Peripheral register bit-banding is performed using the memory alias - * region at BITBAND_PER_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] bit A bit position to read, 0-31. - * - * @return - * The requested bit shifted to bit position 0 in the return value. - ******************************************************************************/ -__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, - unsigned int bit) -{ -#if defined(BITBAND_PER_BASE) - uint32_t aliasAddr = - BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); - - return *(volatile uint32_t *)aliasAddr; -#else - return ((*addr) >> bit) & 1UL; -#endif -} - -/***************************************************************************//** - * @brief - * Perform a masked set operation on a peripheral register address. - * - * @details - * A peripheral register masked set provides a single-cycle and atomic set - * operation of a bit-mask in a peripheral register. All 1s in the mask are - * set to 1 in the register. All 0s in the mask are not changed in the - * register. - * RAMs and special peripherals are not supported. See the - * reference manual for more details about the peripheral register field set. - * - * @note - * This function is single-cycle and atomic on cores with peripheral bit set - * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A mask to set. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, - uint32_t mask) -{ -#if defined(PER_REG_BLOCK_SET_OFFSET) - uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; - *(volatile uint32_t *)aliasAddr = mask; -#elif defined(PER_BITSET_MEM_BASE) - uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); - *(volatile uint32_t *)aliasAddr = mask; -#else - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr |= mask; - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Perform a masked clear operation on the peripheral register address. - * - * @details - * A peripheral register masked clear provides a single-cycle and atomic clear - * operation of a bit-mask in a peripheral register. All 1s in the mask are - * set to 0 in the register. - * All 0s in the mask are not changed in the register. - * RAMs and special peripherals are not supported. See the - * reference manual for more details about the peripheral register field clear. - * - * @note - * This function is single-cycle and atomic on cores with peripheral bit set - * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A mask to clear. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, - uint32_t mask) -{ -#if defined(PER_REG_BLOCK_CLR_OFFSET) - uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; - *(volatile uint32_t *)aliasAddr = mask; -#elif defined(PER_BITCLR_MEM_BASE) - uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); - *(volatile uint32_t *)aliasAddr = mask; -#else - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr &= ~mask; - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Perform peripheral register masked write. - * - * @details - * This function first reads the peripheral register and updates only bits - * that are set in the mask with content of val. Typically, the mask is a - * bit-field in the register and the value val is within the mask. - * - * @note - * The read-modify-write operation is executed in a critical section to - * guarantee atomicity. Note that atomicity can only be guaranteed if register - * is modified only by the core, and not by other peripherals (like DMA). - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A peripheral register mask. - * - * @param[in] val A peripheral register value. The value must be shifted to the - correct bit position in the register corresponding to the field - defined by the mask parameter. The register value must be - contained in the field defined by the mask parameter. The - register value is masked to prevent involuntary spillage. - ******************************************************************************/ -__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, - uint32_t mask, - uint32_t val) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - *addr = (*addr & ~mask) | (val & mask); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * @brief - * Perform a peripheral register masked read. - * - * @details - * Read an unshifted and masked value from a peripheral register. - * - * @note - * This operation is not hardware accelerated. - * - * @param[in] addr A peripheral register address. - * - * @param[in] mask A peripheral register mask. - * - * @return - * An unshifted and masked register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, - uint32_t mask) -{ - return *addr & mask; -} - -/** @} (end addtogroup bus) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_BUS_H */ +/***************************************************************************//** + * @file + * @brief RAM and peripheral bit-field set and clear API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_BUS_H +#define EM_BUS_H + +#include "sl_assert.h" +#include "em_core.h" +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup bus BUS - Bitfield Read/Write + * @brief BUS register and RAM bit/field read/write API + * @details + * API to perform bit-band and field set/clear access to RAM and peripherals. + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single bit write on a 32-bit word in RAM. + * See the reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. RAM bit-banding is + * performed using the memory alias region at BITBAND_RAM_BASE. + * + * @param[in] addr An ddress of a 32-bit word in RAM. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RamBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1UL << bit)) | ((val & 1UL) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a 32-bit word in RAM. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * RAM bit-banding is performed using the memory alias region + * at BITBAND_RAM_BASE. + * + * @param[in] addr RAM address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RamBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_RAM_BASE) + uint32_t aliasAddr = + BITBAND_RAM_BASE + (((uint32_t)addr - SRAM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit write operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read-modify-write operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. Bit- + * banding is a multi cycle read-modify-write bus operation. Peripheral register + * bit-banding is performed using the memory alias region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to write, 0-31. + * + * @param[in] val A value to set bit to, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, + unsigned int bit, + unsigned int val) +{ + EFM_ASSERT(bit < 32U); +#if defined(PER_REG_BLOCK_SET_OFFSET) && defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr; + if (val != 0U) { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + } else { + aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + } + *(volatile uint32_t *)aliasAddr = 1UL << bit; +#elif defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t) 32) + (bit * (uint32_t) 4); + + *(volatile uint32_t *)aliasAddr = (uint32_t)val; +#else + uint32_t tmp = *addr; + + /* Make sure val is not more than 1 because only one bit needs to be set. */ + *addr = (tmp & ~(1 << bit)) | ((val & 1) << bit); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a single-bit read operation on a peripheral register. + * + * @details + * This function uses Cortex-M bit-banding hardware to perform an atomic + * read operation on a single register bit. See the + * reference manual for more details about bit-banding. + * + * @note + * This function is atomic on Cortex-M cores with bit-banding support. + * Peripheral register bit-banding is performed using the memory alias + * region at BITBAND_PER_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] bit A bit position to read, 0-31. + * + * @return + * The requested bit shifted to bit position 0 in the return value. + ******************************************************************************/ +__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, + unsigned int bit) +{ +#if defined(BITBAND_PER_BASE) + uint32_t aliasAddr = + BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) * (uint32_t)32) + (bit * (uint32_t) 4); + + return *(volatile uint32_t *)aliasAddr; +#else + return ((*addr) >> bit) & 1UL; +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked set operation on a peripheral register address. + * + * @details + * A peripheral register masked set provides a single-cycle and atomic set + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 1 in the register. All 0s in the mask are not changed in the + * register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field set. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITSET_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to set. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_SET_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_SET_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITSET_MEM_BASE) + uint32_t aliasAddr = PER_BITSET_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr |= mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform a masked clear operation on the peripheral register address. + * + * @details + * A peripheral register masked clear provides a single-cycle and atomic clear + * operation of a bit-mask in a peripheral register. All 1s in the mask are + * set to 0 in the register. + * All 0s in the mask are not changed in the register. + * RAMs and special peripherals are not supported. See the + * reference manual for more details about the peripheral register field clear. + * + * @note + * This function is single-cycle and atomic on cores with peripheral bit set + * and clear support. It uses the memory alias region at PER_BITCLR_MEM_BASE. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A mask to clear. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, + uint32_t mask) +{ +#if defined(PER_REG_BLOCK_CLR_OFFSET) + uint32_t aliasAddr = (uint32_t)addr + PER_REG_BLOCK_CLR_OFFSET; + *(volatile uint32_t *)aliasAddr = mask; +#elif defined(PER_BITCLR_MEM_BASE) + uint32_t aliasAddr = PER_BITCLR_MEM_BASE + ((uint32_t)addr - PER_MEM_BASE); + *(volatile uint32_t *)aliasAddr = mask; +#else + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr &= ~mask; + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Perform peripheral register masked write. + * + * @details + * This function first reads the peripheral register and updates only bits + * that are set in the mask with content of val. Typically, the mask is a + * bit-field in the register and the value val is within the mask. + * + * @note + * The read-modify-write operation is executed in a critical section to + * guarantee atomicity. Note that atomicity can only be guaranteed if register + * is modified only by the core, and not by other peripherals (like DMA). + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @param[in] val A peripheral register value. The value must be shifted to the + correct bit position in the register corresponding to the field + defined by the mask parameter. The register value must be + contained in the field defined by the mask parameter. The + register value is masked to prevent involuntary spillage. + ******************************************************************************/ +__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, + uint32_t mask, + uint32_t val) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + *addr = (*addr & ~mask) | (val & mask); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Perform a peripheral register masked read. + * + * @details + * Read an unshifted and masked value from a peripheral register. + * + * @note + * This operation is not hardware accelerated. + * + * @param[in] addr A peripheral register address. + * + * @param[in] mask A peripheral register mask. + * + * @return + * An unshifted and masked register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, + uint32_t mask) +{ + return *addr & mask; +} + +/** @} (end addtogroup bus) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_BUS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h index 1de476a..27b559d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_chip.h @@ -1,462 +1,462 @@ -/***************************************************************************//** - * @file - * @brief Chip Errata Workarounds - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CHIP_H -#define EM_CHIP_H - -#include "em_device.h" -#include "sl_common.h" -#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2) -#include "em_system.h" -#endif -#include "em_bus.h" - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#include "em_gpio.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup chip CHIP - Chip Errata Workarounds - * @brief Chip errata workaround APIs - * @details - * API to apply chip errata workarounds at initialization and reset. - * @{ - ******************************************************************************/ - -/**************************************************************************//** - * @brief - * Chip initialization routine for revision errata workarounds. - * - * @note - * This function must be called immediately in main(). - * - * This initialization function configures the device to a state - * as similar to later revisions as possible to improve software compatibility - * with newer parts. See the device-specific errata for details. - *****************************************************************************/ -__STATIC_INLINE void CHIP_Init(void) -{ -#if defined(MSC_CACHECMD_INVCACHE) - MSC->CACHECMD = MSC_CACHECMD_INVCACHE; -#elif defined(MSC_CMD_INVCACHE) - MSC->CMD = MSC_CMD_INVCACHE; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) - uint32_t rev; - SYSTEM_ChipRevision_TypeDef chipRev; - volatile uint32_t *reg; - - rev = *(volatile uint32_t *)(0x0FE081FC); - /* Engineering Sample calibration setup. */ - if ((rev >> 24) == 0) { - reg = (volatile uint32_t *)0x400CA00C; - *reg &= ~(0x70UL); - /* DREG */ - reg = (volatile uint32_t *)0x400C6020; - *reg &= ~(0xE0000000UL); - *reg |= ~(7UL << 25); - } - if ((rev >> 24) <= 3) { - /* DREG */ - reg = (volatile uint32_t *)0x400C6020; - *reg &= ~(0x00001F80UL); - /* Update CMU reset values. */ - reg = (volatile uint32_t *)0x400C8040; - *reg = 0; - reg = (volatile uint32_t *)0x400C8044; - *reg = 0; - reg = (volatile uint32_t *)0x400C8058; - *reg = 0; - reg = (volatile uint32_t *)0x400C8060; - *reg = 0; - reg = (volatile uint32_t *)0x400C8078; - *reg = 0; - } - - SYSTEM_ChipRevisionGet(&chipRev); - if (chipRev.major == 0x01) { - /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ - /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ - if (chipRev.minor == 00) { - reg = (volatile uint32_t *)0x400C8040; - *reg |= 0x2; - } - - /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ - /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ - /* later chip revisions and is only needed for rev A+B. */ - if (chipRev.minor <= 0x01) { - reg = (volatile uint32_t *)0x400C8044; - *reg |= 0x1; - } - } - /* Ensure correct ADC/DAC calibration value. */ - rev = *(volatile uint32_t *)0x0FE081F0; - if (rev < 0x4C8ABA00) { - uint32_t cal; - - /* Enable ADC/DAC clocks. */ - reg = (volatile uint32_t *)0x400C8044UL; - *reg |= (1 << 14 | 1 << 11); - - /* Retrive calibration values. */ - cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) - >> 8) << 24; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) - >> 0) << 16; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) - >> 8) << 8; - - cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) - >> 0) << 0; - - /* ADC0->CAL = 1.25 reference. */ - reg = (volatile uint32_t *)0x40002034UL; - *reg = cal; - - /* DAC0->CAL = 1.25 reference. */ - reg = (volatile uint32_t *)(0x4000402CUL); - cal = *(volatile uint32_t *)0x0FE081C8UL; - *reg = cal; - - /* Turn off ADC/DAC clocks. */ - reg = (volatile uint32_t *)0x400C8044UL; - *reg &= ~(1 << 14 | 1 << 11); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) - - /****************************/ - /* Fix for errata CMU_E113. */ - - uint8_t prodRev; - SYSTEM_ChipRevision_TypeDef chipRev; - - prodRev = SYSTEM_GetProdRev(); - SYSTEM_ChipRevisionGet(&chipRev); - - // All Giant and Leopard parts except Leopard Rev E - if ((prodRev >= 16) && (chipRev.minor >= 3) - && !((chipRev.major == 2) && (chipRev.minor == 4))) { - /* This fixes an issue with the LFXO on high temperatures. */ - *(volatile uint32_t*)0x400C80C0 = - (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - - uint8_t prodRev; - prodRev = SYSTEM_GetProdRev(); - - if (prodRev <= 129) { - /* This fixes a mistaken internal connection between PC0 and PC4. */ - /* This disables an internal pull-down on PC4. */ - *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); - /* This disables an internal LDO test signal driving PC4. */ - *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); - } -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - - /**************************** - * Fixes for errata GPIO_E201 (slewrate) and - * HFXO high-temperature oscillator startup robustness fix. */ - - uint32_t port; - uint32_t clkEn; - uint8_t prodRev; - const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) - | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); - const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE - & ~(_GPIO_P_CTRL_SLEWRATE_MASK - | _GPIO_P_CTRL_SLEWRATEALT_MASK); - - prodRev = SYSTEM_GetProdRev(); - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - /* This errata is fixed in hardware from PRODREV 0x8F. */ - if (prodRev < 0x8F) { - /* Fixes for errata GPIO_E201 (slewrate). */ - - /* Save HFBUSCLK enable state and enable GPIO clock. */ - clkEn = CMU->HFBUSCLKEN0; - CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; - - /* Update slewrate. */ - for (port = 0; port <= GPIO_PORT_MAX; port++) { - GPIO->P[port].CTRL = setVal | resetVal; - } - - /* Restore HFBUSCLK enable state. */ - CMU->HFBUSCLKEN0 = clkEn; - } - - /* This errata is fixed in hardware from PRODREV 0x90. */ - if (prodRev < 0x90) { - /* HFXO high-temperature oscillator startup robustness fix. */ - CMU->HFXOSTARTUPCTRL = - (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) - | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - } - - if (chipRev.major == 0x01) { - /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ - *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; - } - - /**************************** - * Fix for errata DCDC_E206. - * Disable bypass limit enabled temporarily in SystemInit() errata - * workaround. */ - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - uint8_t prodRev = SYSTEM_GetProdRev(); - - /* EM2 current fixes for early samples. */ - if (prodRev == 0U) { - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; - *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; - } - if (prodRev < 2U) { - *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); - } - - /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ - CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) - | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES - | CMU_LFRCOCTRL_ENVREF; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) - MSC->CTRL |= 0x1UL << 8; -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if ((chipRev.major > 1) || (chipRev.minor >= 3)) { - /* PLFRCO trim values */ - *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608; - *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250; - *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118; - *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400; - } -#endif - -/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ -#if defined(_LCD_DISPCTRL_CHGRDST_MASK) -#if defined(_SILICON_LABS_32B_SERIES_1) - CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; - CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; - *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); - CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; - CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ - && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) - /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur - * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */ - *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { - /* Change HFXO default peak detector settings. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) - | 0x00178500U; - /* Change HFXO low power control settings. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) - | 0x0000C000U; - /* Change default SQBUF bias current. */ - *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; - } - - if (chipRev.major == 0x01 && chipRev.minor == 0x0) { - /* Trigger RAM read for each RAM instance */ - volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; - for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { - // Force memory read - *dmem; - dmem += (DMEM_BANK0_SIZE / 4U); - } - } - - /* Set TRACE clock to intended reset value. */ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) - | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) -#if defined(SL_TRUSTZONE_SECURE) -#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL) -#else -#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL) -#endif -#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL) - if (SYSTEM_GetProdRev() == 1) { - bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0; - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; - /* Enable HFRCO CLKOUT0. */ - *(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0; - if (hfrcoClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; - } - } -#endif - -/* PM-3503 */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) - { - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - - bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); - DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; - - while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { - /* Wait for previous synchronization to finish */ - } - - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { - /* Wait for BYPASS switch enable. */ - } - - if (dcdcIsLock) { - DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; - } - - if (dcdcClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - } -#endif - -/* PM-5163 */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \ - && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - - if (chipRev.major == 0x01 && chipRev.minor == 0x00) { - bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0; - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; - - *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = - (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) - | 0x0C000000UL; - - if (hfxo0ClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; - } - } -#endif -} - -/**************************************************************************//** - * @brief - * Chip reset routine with errata workarounds. - * - * @note - * This function should be called to reset the chip. It does not return. - * - * This function applies any errata workarounds needed to cleanly reset the - * device and then performs a system reset. See the device-specific errata for - * details. - *****************************************************************************/ -__STATIC_INLINE void CHIP_Reset(void) -{ -#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - /**************************** - * Workaround for errata DCDC_E206. - * Disable radio interference minimization features when resetting */ - - // Ensure access to EMU registers - EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; - - // No need to do anything if the DCDC is not powering DVDD - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { - // Make sure radio cannot accidentally re-enable features - *(volatile uint32_t *)(0x40084040UL) = 0x1UL; - - // If DCDC is in use, disable features - uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; - if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) - || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) { - BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); - BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); - } - } -#endif - - NVIC_SystemReset(); -} - -/** @} (end addtogroup chip) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_CHIP_H */ +/***************************************************************************//** + * @file + * @brief Chip Errata Workarounds + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CHIP_H +#define EM_CHIP_H + +#include "em_device.h" +#include "sl_common.h" +#if defined(_SILICON_LABS_32B_SERIES) && (_SILICON_LABS_32B_SERIES <= 2) +#include "em_system.h" +#endif +#include "em_bus.h" + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#include "em_gpio.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup chip CHIP - Chip Errata Workarounds + * @brief Chip errata workaround APIs + * @details + * API to apply chip errata workarounds at initialization and reset. + * @{ + ******************************************************************************/ + +/**************************************************************************//** + * @brief + * Chip initialization routine for revision errata workarounds. + * + * @note + * This function must be called immediately in main(). + * + * This initialization function configures the device to a state + * as similar to later revisions as possible to improve software compatibility + * with newer parts. See the device-specific errata for details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Init(void) +{ +#if defined(MSC_CACHECMD_INVCACHE) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#elif defined(MSC_CMD_INVCACHE) + MSC->CMD = MSC_CMD_INVCACHE; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) + uint32_t rev; + SYSTEM_ChipRevision_TypeDef chipRev; + volatile uint32_t *reg; + + rev = *(volatile uint32_t *)(0x0FE081FC); + /* Engineering Sample calibration setup. */ + if ((rev >> 24) == 0) { + reg = (volatile uint32_t *)0x400CA00C; + *reg &= ~(0x70UL); + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0xE0000000UL); + *reg |= ~(7UL << 25); + } + if ((rev >> 24) <= 3) { + /* DREG */ + reg = (volatile uint32_t *)0x400C6020; + *reg &= ~(0x00001F80UL); + /* Update CMU reset values. */ + reg = (volatile uint32_t *)0x400C8040; + *reg = 0; + reg = (volatile uint32_t *)0x400C8044; + *reg = 0; + reg = (volatile uint32_t *)0x400C8058; + *reg = 0; + reg = (volatile uint32_t *)0x400C8060; + *reg = 0; + reg = (volatile uint32_t *)0x400C8078; + *reg = 0; + } + + SYSTEM_ChipRevisionGet(&chipRev); + if (chipRev.major == 0x01) { + /* Rev A errata handling for EM2/3. Must enable DMA clock to get EM2/3 */ + /* to work. This will be fixed in later chip revisions and is only needed for rev A. */ + if (chipRev.minor == 00) { + reg = (volatile uint32_t *)0x400C8040; + *reg |= 0x2; + } + + /* Rev A+B errata handling for I2C when using EM2/3. USART0 clock must be enabled */ + /* after waking up from EM2/EM3 to get I2C to work. This will be fixed in */ + /* later chip revisions and is only needed for rev A+B. */ + if (chipRev.minor <= 0x01) { + reg = (volatile uint32_t *)0x400C8044; + *reg |= 0x1; + } + } + /* Ensure correct ADC/DAC calibration value. */ + rev = *(volatile uint32_t *)0x0FE081F0; + if (rev < 0x4C8ABA00) { + uint32_t cal; + + /* Enable ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg |= (1 << 14 | 1 << 11); + + /* Retrive calibration values. */ + cal = ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 24; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 16; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x00007F00UL) + >> 8) << 8; + + cal |= ((*(volatile uint32_t *)(0x0FE081B4UL) & 0x0000007FUL) + >> 0) << 0; + + /* ADC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)0x40002034UL; + *reg = cal; + + /* DAC0->CAL = 1.25 reference. */ + reg = (volatile uint32_t *)(0x4000402CUL); + cal = *(volatile uint32_t *)0x0FE081C8UL; + *reg = cal; + + /* Turn off ADC/DAC clocks. */ + reg = (volatile uint32_t *)0x400C8044UL; + *reg &= ~(1 << 14 | 1 << 11); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + + /****************************/ + /* Fix for errata CMU_E113. */ + + uint8_t prodRev; + SYSTEM_ChipRevision_TypeDef chipRev; + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevisionGet(&chipRev); + + // All Giant and Leopard parts except Leopard Rev E + if ((prodRev >= 16) && (chipRev.minor >= 3) + && !((chipRev.major == 2) && (chipRev.minor == 4))) { + /* This fixes an issue with the LFXO on high temperatures. */ + *(volatile uint32_t*)0x400C80C0 = + (*(volatile uint32_t*)0x400C80C0 & ~(1 << 6) ) | (1 << 4); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + + uint8_t prodRev; + prodRev = SYSTEM_GetProdRev(); + + if (prodRev <= 129) { + /* This fixes a mistaken internal connection between PC0 and PC4. */ + /* This disables an internal pull-down on PC4. */ + *(volatile uint32_t*)(0x400C6018) = (1 << 26) | (5 << 0); + /* This disables an internal LDO test signal driving PC4. */ + *(volatile uint32_t*)(0x400C80E4) &= ~(1 << 24); + } +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /**************************** + * Fixes for errata GPIO_E201 (slewrate) and + * HFXO high-temperature oscillator startup robustness fix. */ + + uint32_t port; + uint32_t clkEn; + uint8_t prodRev; + const uint32_t setVal = (0x5 << _GPIO_P_CTRL_SLEWRATEALT_SHIFT) + | (0x5 << _GPIO_P_CTRL_SLEWRATE_SHIFT); + const uint32_t resetVal = _GPIO_P_CTRL_RESETVALUE + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK); + + prodRev = SYSTEM_GetProdRev(); + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + /* This errata is fixed in hardware from PRODREV 0x8F. */ + if (prodRev < 0x8F) { + /* Fixes for errata GPIO_E201 (slewrate). */ + + /* Save HFBUSCLK enable state and enable GPIO clock. */ + clkEn = CMU->HFBUSCLKEN0; + CMU->HFBUSCLKEN0 = clkEn | CMU_HFBUSCLKEN0_GPIO; + + /* Update slewrate. */ + for (port = 0; port <= GPIO_PORT_MAX; port++) { + GPIO->P[port].CTRL = setVal | resetVal; + } + + /* Restore HFBUSCLK enable state. */ + CMU->HFBUSCLKEN0 = clkEn; + } + + /* This errata is fixed in hardware from PRODREV 0x90. */ + if (prodRev < 0x90) { + /* HFXO high-temperature oscillator startup robustness fix. */ + CMU->HFXOSTARTUPCTRL = + (CMU->HFXOSTARTUPCTRL & ~_CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK) + | (0x20 << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + } + + if (chipRev.major == 0x01) { + /* Fix for errata EMU_E210 - Potential Power-Down When Entering EM2 */ + *(volatile uint32_t *)(EMU_BASE + 0x164) |= 0x4; + } + + /**************************** + * Fix for errata DCDC_E206. + * Disable bypass limit enabled temporarily in SystemInit() errata + * workaround. */ + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + uint8_t prodRev = SYSTEM_GetProdRev(); + + /* EM2 current fixes for early samples. */ + if (prodRev == 0U) { + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 2); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0; + } + if (prodRev < 2U) { + *(volatile uint32_t *)(EMU_BASE + 0x164UL) |= (0x1UL << 13); + } + + /* Set optimal LFRCOCTRL VREFUPDATE and enable duty cycling of VREF. */ + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~_CMU_LFRCOCTRL_VREFUPDATE_MASK) + | CMU_LFRCOCTRL_VREFUPDATE_64CYCLES + | CMU_LFRCOCTRL_ENVREF; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && defined(_EFR_DEVICE) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 84) + MSC->CTRL |= 0x1UL << 8; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if ((chipRev.major > 1) || (chipRev.minor >= 3)) { + /* PLFRCO trim values */ + *(volatile uint32_t *)(CMU_BASE + 0x28CUL) = 608; + *(volatile uint32_t *)(CMU_BASE + 0x290UL) = 356250; + *(volatile uint32_t *)(CMU_BASE + 0x2F0UL) = 0x04000118; + *(volatile uint32_t *)(CMU_BASE + 0x2F8UL) = 0x08328400; + } +#endif + +/* Charge redist setup (fixed value): LCD->DBGCTRL.CHGRDSTSTR = 1 (reset: 0). */ +#if defined(_LCD_DISPCTRL_CHGRDST_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LE; + CMU->LFACLKEN0 |= CMU_LFACLKEN0_LCD; + *(volatile uint32_t *)(LCD_BASE + 0x034) |= (0x1UL << 12); + CMU->LFACLKEN0 &= ~CMU_LFACLKEN0_LCD; + CMU->HFBUSCLKEN0 &= ~CMU_HFBUSCLKEN0_LE; +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) + /* First part of the EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. Second part is in em_emu.c */ + *(volatile uint32_t *)(EMU_BASE + 0x1A4) |= 0x1f << 10; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { + /* Change HFXO default peak detector settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x34U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x34U) & 0xFF8000FFU) + | 0x00178500U; + /* Change HFXO low power control settings. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x30U) & 0xFFFF0FFFU) + | 0x0000C000U; + /* Change default SQBUF bias current. */ + *(volatile uint32_t*)(HFXO0_BASE + 0x30U) |= 0x700; + } + + if (chipRev.major == 0x01 && chipRev.minor == 0x0) { + /* Trigger RAM read for each RAM instance */ + volatile uint32_t *dmem = (volatile uint32_t *) DMEM_RAM0_RAM_MEM_BASE; + for (uint32_t i = 0U; i < DMEM_NUM_BANK; i++) { + // Force memory read + *dmem; + dmem += (DMEM_BANK0_SIZE / 4U); + } + } + + /* Set TRACE clock to intended reset value. */ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) +#if defined(SL_TRUSTZONE_SECURE) +#define HFRCO_CLK_CFG_CLR_ADDR (0x40012020UL) +#else +#define HFRCO_CLK_CFG_CLR_ADDR (0x50012020UL) +#endif +#define HFRCO_CLK_CFG_CLKOUTDIS0 (0x4UL) + if (SYSTEM_GetProdRev() == 1) { + bool hfrcoClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFRCO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; + /* Enable HFRCO CLKOUT0. */ + *(volatile uint32_t*)(HFRCO_CLK_CFG_CLR_ADDR) = HFRCO_CLK_CFG_CLKOUTDIS0; + if (hfrcoClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFRCO0; + } + } +#endif + +/* PM-3503 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_210) + { + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + bool dcdcClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + bool dcdcIsLock = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK_LOCKED) != 0); + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; + + while (DCDC->SYNCBUSY & DCDC_SYNCBUSY_CTRL) { + /* Wait for previous synchronization to finish */ + } + + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while ((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) { + /* Wait for BYPASS switch enable. */ + } + + if (dcdcIsLock) { + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; + } + + if (dcdcClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + } +#endif + +/* PM-5163 */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_215) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + + if (chipRev.major == 0x01 && chipRev.minor == 0x00) { + bool hfxo0ClkIsOff = (CMU->CLKEN0 & CMU_CLKEN0_HFXO0) == 0; + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + + *(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) = + (*(volatile uint32_t*)(HFXO0_BASE + 0x0034UL) & 0xE3FFFFFFUL) + | 0x0C000000UL; + + if (hfxo0ClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_HFXO0; + } + } +#endif +} + +/**************************************************************************//** + * @brief + * Chip reset routine with errata workarounds. + * + * @note + * This function should be called to reset the chip. It does not return. + * + * This function applies any errata workarounds needed to cleanly reset the + * device and then performs a system reset. See the device-specific errata for + * details. + *****************************************************************************/ +__STATIC_INLINE void CHIP_Reset(void) +{ +#if defined(_EFR_DEVICE) && defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /**************************** + * Workaround for errata DCDC_E206. + * Disable radio interference minimization features when resetting */ + + // Ensure access to EMU registers + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; + + // No need to do anything if the DCDC is not powering DVDD + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + // Make sure radio cannot accidentally re-enable features + *(volatile uint32_t *)(0x40084040UL) = 0x1UL; + + // If DCDC is in use, disable features + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if ((dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) + || (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER)) { + BUS_RegBitWrite((volatile uint32_t *)(0x400E3060UL), 28UL, 0); + BUS_RegBitWrite((volatile uint32_t *)(0x400E3074UL), 0, 0); + } + } +#endif + + NVIC_SystemReset(); +} + +/** @} (end addtogroup chip) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_CHIP_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h index 3ac9d07..66b9ecc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu.h @@ -1,3654 +1,3654 @@ -/***************************************************************************//** - * @file - * @brief Clock management unit (CMU) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_CMU_H -#define EM_CMU_H - -#include "em_device.h" -#if defined(CMU_PRESENT) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "em_cmu_compat.h" -#include "em_gpio.h" -#include "sl_common.h" -#include "sl_enum.h" -#include "sl_status.h" -#include "sli_em_cmu.h" -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup cmu - * @{ - ******************************************************************************/ - -/** Macro to set clock sources in the clock tree. */ -#define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel - -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/* Enable register bit positions, for internal use. */ -#define CMU_EN_BIT_POS 0U -#define CMU_EN_BIT_MASK 0x1FU - -/* Enable register ID's for internal use. */ -#define CMU_NO_EN_REG 0 -#define CMU_CLKEN0_EN_REG 1 -#define CMU_CLKEN1_EN_REG 2 -#if defined(_CMU_CLKEN2_MASK) -#define CMU_CLKEN2_EN_REG 3 -#endif -#define CMU_CRYPTOACCCLKCTRL_EN_REG 3 -#define CMU_EN_REG_POS 5U -#define CMU_EN_REG_MASK 0x3U - -/* Clock branch ID's internal use. */ -#define CMU_CORE_BRANCH 0 -#define CMU_SYSCLK_BRANCH 1 -#define CMU_SYSTICK_BRANCH 2 -#define CMU_HCLK_BRANCH 3 -#define CMU_EXPCLK_BRANCH 4 -#define CMU_PCLK_BRANCH 5 -#define CMU_LSPCLK_BRANCH 6 -#define CMU_TRACECLK_BRANCH 7 -#define CMU_EM01GRPACLK_BRANCH 8 -#if defined(_CMU_EM01GRPBCLKCTRL_MASK) -#define CMU_EM01GRPBCLK_BRANCH 9 -#endif -#define CMU_EUART0CLK_BRANCH 10 -#define CMU_IADCCLK_BRANCH 11 -#define CMU_EM23GRPACLK_BRANCH 12 -#define CMU_WDOG0CLK_BRANCH 13 -#if defined(RTCC_PRESENT) -#define CMU_RTCCCLK_BRANCH 14 -#elif defined(SYSRTC_PRESENT) -#define CMU_SYSRTCCLK_BRANCH 14 -#endif -#define CMU_EM4GRPACLK_BRANCH 15 -#if defined(PDM_PRESENT) -#define CMU_PDMREF_BRANCH 16 -#endif -#define CMU_DPLLREFCLK_BRANCH 17 -#if WDOG_COUNT > 1 -#define CMU_WDOG1CLK_BRANCH 18 -#endif -#if defined(LCD_PRESENT) -#define CMU_LCD_BRANCH 19 -#endif -#if defined(VDAC_PRESENT) -#define CMU_VDAC0_BRANCH 20 -#endif -#if defined(PCNT_PRESENT) -#define CMU_PCNT_BRANCH 21 -#endif -#if defined(LESENSE_PRESENT) -#define CMU_LESENSEHF_BRANCH 22 -#define CMU_LESENSE_BRANCH 23 -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -#define CMU_EM01GRPCCLK_BRANCH 24 -#endif -#if defined(VDAC_PRESENT) && (VDAC_COUNT > 1) -#define CMU_VDAC1_BRANCH 25 -#endif -#define CMU_CLK_BRANCH_POS 7U -#define CMU_CLK_BRANCH_MASK 0x1FU -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(_EMU_CMD_EM01VSCALE1_MASK) -/* Maximum clock frequency for VSCALE voltages. */ -#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL -#endif - -/* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API. - * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for - * Series1 parts (highest VSCALE voltage = lowest numerical value). */ -#define VSCALE_EM01_LOW_POWER 1 -#define VSCALE_EM01_HIGH_PERFORMANCE 0 - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define PLFRCO_PRESENT -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Disable clocks configuration */ -#if defined(_SILICON_LABS_32B_SERIES_2) -#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */ -#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/ -#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */ -#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/ -#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */ -#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/ -#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */ -#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */ -#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */ -#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */ -#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */ -#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */ -#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ -#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ -#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */ -#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */ -#endif // (_SILICON_LABS_32B_SERIES_2) - -/** Clock divider configuration */ -typedef uint32_t CMU_ClkDiv_TypeDef; - -/** HFRCODPLL frequency bands */ -SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) { - cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ - cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ - cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ - cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ - cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ - cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ - cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ - cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ - cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ - cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ - cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ - cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ - cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ - cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */ -#endif - cmuHFRCODPLLFreq_UserDefined = 0, -}; - -#if defined(USBPLL_PRESENT) -/** HFXO reference frequency */ -SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) { - cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (24UL << _USBPLL_CTRL_DIVX_SHIFT) - | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */ - cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (25UL << _USBPLL_CTRL_DIVX_SHIFT) - | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */ - cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (16UL << _USBPLL_CTRL_DIVX_SHIFT) - | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */ - cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) - | (24UL << _USBPLL_CTRL_DIVX_SHIFT) - | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */ -}; -#endif - -/** HFRCODPLL maximum frequency */ -#define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz -/** HFRCODPLL minimum frequency */ -#define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz - -#if defined(HFRCOEM23_PRESENT) -/** HFRCOEM23 frequency bands */ -SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) { - cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ - cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ - cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ - cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ - cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ - cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ - cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ - cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ - cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ - cmuHFRCOEM23Freq_UserDefined = 0, -}; - -/** HFRCOEM23 maximum frequency */ -#define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz -/** HFRCOEM23 minimum frequency */ -#define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz -#endif // defined(HFRCOEM23_PRESENT) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/** Clock points in CMU clock-tree. */ -SL_ENUM(CMU_Clock_TypeDef) { - /*******************/ - /* Clock branches */ - /*******************/ - - cmuClock_SYSCLK, /**< System clock. */ - cmuClock_HCLK, /**< Core and AHB bus interface clock. */ - cmuClock_EXPCLK, /**< Export clock. */ - cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ - cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ - cmuClock_IADCCLK, /**< IADC clock. */ - cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ - cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ - cmuClock_WDOG0CLK, /**< WDOG0 clock. */ - cmuClock_WDOG1CLK, /**< WDOG1 clock. */ - cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ - cmuClock_TRACECLK, /**< Debug trace clock. */ - cmuClock_RTCCCLK, /**< RTCC clock. */ - cmuClock_HFRCOEM23, - - /*********************/ - /* Peripheral clocks */ - /*********************/ - - cmuClock_CORE, /**< Cortex-M33 core clock. */ - cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ - cmuClock_ACMP0, /**< ACMP0 clock. */ - cmuClock_ACMP1, /**< ACMP1 clock. */ - cmuClock_BURTC, /**< BURTC clock. */ - cmuClock_GPCRC, /**< GPCRC clock. */ - cmuClock_GPIO, /**< GPIO clock. */ - cmuClock_I2C0, /**< I2C0 clock. */ - cmuClock_I2C1, /**< I2C1 clock. */ - cmuClock_IADC0, /**< IADC clock. */ - cmuClock_LDMA, /**< LDMA clock. */ - cmuClock_LETIMER0, /**< LETIMER clock. */ - cmuClock_PRS, /**< PRS clock. */ - cmuClock_RTCC, /**< RTCC clock. */ - cmuClock_TIMER0, /**< TIMER0 clock. */ - cmuClock_TIMER1, /**< TIMER1 clock. */ - cmuClock_TIMER2, /**< TIMER2 clock. */ - cmuClock_TIMER3, /**< TIMER3 clock. */ - cmuClock_USART0, /**< USART0 clock. */ - cmuClock_USART1, /**< USART1 clock. */ - cmuClock_USART2, /**< USART2 clock. */ - cmuClock_WDOG0, /**< WDOG0 clock. */ - cmuClock_WDOG1, /**< WDOG1 clock. */ - cmuClock_PDM /**< PDM clock. */ -}; -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -/** Clock points in CMU clock-tree. */ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { - /*******************/ - /* Clock branches */ - /*******************/ - - cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */ - cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */ - cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */ - cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */ - cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */ - cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */ - cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */ - cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */ -#if defined(PDM_PRESENT) - cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */ -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */ -#endif -#if defined(EUART_PRESENT) - cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */ -#elif defined(EUSART_PRESENT) - cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */ -#endif - cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */ - cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */ - cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */ -#if WDOG_COUNT > 1 - cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */ -#endif -#if defined(RTCC_PRESENT) - cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */ -#elif defined(SYSRTC_PRESENT) - cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */ -#endif - cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */ - cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */ -#if defined(CRYPTOACC_PRESENT) - cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */ - cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */ -#endif -#if defined(LCD_PRESENT) - cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */ -#endif -#if defined(VDAC_PRESENT) - cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */ -#if (VDAC_COUNT > 1) - cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */ -#endif -#endif -#if defined(PCNT_PRESENT) - cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */ -#endif -#if defined(LESENSE_PRESENT) - cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */ - cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */ -#endif - - cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */ -#if defined(PDM_PRESENT) - cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */ -#endif - /*********************/ - /* Peripheral clocks */ - /*********************/ - - cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */ - cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */ -#if defined(RADIOAES_PRESENT) - cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */ -#endif - cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */ - cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */ - cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */ - cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */ - cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */ -#if defined(_CMU_CLKEN2_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#elif defined(_CMU_CLKEN1_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#elif defined(_CMU_CLKEN0_TIMER4_SHIFT) - cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#elif defined(_CMU_CLKEN1_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#elif defined(_CMU_CLKEN0_TIMER5_SHIFT) - cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#elif defined(_CMU_CLKEN1_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#elif defined(_CMU_CLKEN0_TIMER6_SHIFT) - cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#elif defined(_CMU_CLKEN1_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#elif defined(_CMU_CLKEN0_TIMER7_SHIFT) - cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER8_SHIFT) - cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */ -#endif -#if defined(_CMU_CLKEN2_TIMER9_SHIFT) - cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */ -#endif -#if defined(USART_PRESENT) && USART_COUNT > 0 - cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */ -#endif -#if defined(USART_PRESENT) && USART_COUNT > 1 -#if defined(_CMU_CLKEN0_USART1_SHIFT) - cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ -#elif defined(_CMU_CLKEN2_USART1_SHIFT) - cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ -#endif -#endif /* defined(USART_PRESENT) && USART_COUNT > 1 */ -#if defined(USART_PRESENT) && USART_COUNT > 2 - cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */ -#endif /* defined(USART_PRESENT) && USART_COUNT > 2 */ -#if defined(IADC_PRESENT) - cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */ -#endif - cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */ -#if defined(LETIMER_PRESENT) - cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */ -#endif - cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */ -#if WDOG_COUNT > 1 - cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */ -#endif -#if defined(I2C_PRESENT) - cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */ -#if I2C_COUNT > 1 - cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */ -#endif /* I2C_COUNT > 1 */ -#if I2C_COUNT > 2 - cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */ -#endif /* I2C_COUNT > 2 */ -#if I2C_COUNT > 3 - cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */ -#endif /* I2C_COUNT > 3 */ -#endif /* defined(I2C_PRESENT) */ - cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */ - cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */ - cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */ -#if defined(HFRCOEM23_PRESENT) - cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */ -#endif -#if defined(HFXO_PRESENT) - cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */ -#endif - cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */ - cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */ - cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */ - cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */ -#if defined(EUART_PRESENT) - cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */ -#endif -#if defined(PDM_PRESENT) - cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */ -#endif - cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */ - cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */ - cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */ - cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */ -#if defined(RTCC_PRESENT) - cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */ -#endif - cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */ -#if defined(SYSRTC_PRESENT) - cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 - cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */ -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#if defined(_CMU_CLKEN1_EUSART2_SHIFT) - cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ -#elif defined(_CMU_CLKEN2_EUSART2_SHIFT) - cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#if defined(_CMU_CLKEN1_EUSART3_SHIFT) - cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ -#elif defined(_CMU_CLKEN2_EUSART3_SHIFT) - cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#if defined(_CMU_CLKEN1_EUSART4_SHIFT) - cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ -#elif defined(_CMU_CLKEN2_EUSART4_SHIFT) - cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ -#endif -#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */ -#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) - cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */ -#endif -#if defined(CRYPTOACC_PRESENT) - cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */ -#endif -#if defined(SEMAILBOX_PRESENT) - cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */ -#endif - cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */ -#if defined(ICACHE_PRESENT) - cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */ -#endif -#if defined(LESENSE_PRESENT) - cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */ -#endif -#if defined(ACMP_PRESENT) - cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */ -#if ACMP_COUNT > 1 - cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */ -#endif -#endif -#if defined(VDAC_PRESENT) - cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */ -#if (VDAC_COUNT > 1) - cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */ -#endif -#endif -#if defined(PCNT_PRESENT) - cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */ -#endif -#if defined(DMEM_PRESENT) - cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */ -#endif -#if defined(KEYSCAN_PRESENT) - cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */ -#endif -#if defined(LCD_PRESENT) - cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */ -#endif -#if defined(MVP_PRESENT) - cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */ -#endif - cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */ -#if defined(USB_PRESENT) - cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */ -#endif -#if defined(ETAMPDET_PRESENT) - cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */ -#endif -#if defined(RFFPLL_PRESENT) - cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */ -#endif -}; -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/** Oscillator types. */ -SL_ENUM(CMU_Osc_TypeDef) { - cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ - cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ - cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuOsc_HFXO, /**< High frequency crystal oscillator. */ - cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ -#if defined(HFRCOEM23_PRESENT) - cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ -#endif - cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ -}; - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/** Selectable clock sources. */ -SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ - cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ - cmuSelect_CLKIN0, /**< External clock input. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ - cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ - cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ - cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ - cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ - cmuSelect_EXPCLK, /**< Pin export clock. */ - cmuSelect_PRS /**< PRS input as clock. */ -}; -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/** Selectable clock sources. */ -SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ - cmuSelect_HFXO, /**< High frequency crystal oscillator. */ - cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */ - cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ - cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */ -#if defined(HFRCOEM23_PRESENT) - cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ -#endif - cmuSelect_CLKIN0, /**< External clock input. */ - cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ -#if defined(PLFRCO_PRESENT) - cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */ -#endif - cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ - cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ - cmuSelect_SYSCLK, /**< System clock. */ - cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ - cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ - cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */ -#endif - cmuSelect_EXPCLK, /**< Pin export clock. */ - cmuSelect_PRS, /**< PRS input as clock. */ -#if defined(PCNT_PRESENT) - cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */ -#endif - cmuSelect_TEMPOSC, /**< Temperature oscillator. */ - cmuSelect_PFMOSC, /**< PFM oscillator. */ - cmuSelect_BIASOSC, /**< BIAS oscillator. */ -#if defined(USBPLL_PRESENT) - cmuSelect_USBPLL0, /**< PLL clock for USB. */ -#endif -#if defined(RFFPLL_PRESENT) - cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */ -#endif -}; -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/** DPLL reference clock edge detect selector. */ -SL_ENUM(CMU_DPLLEdgeSel_TypeDef) { - cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ - cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ -}; - -/** DPLL lock mode selector. */ -SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { - cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ - cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ -}; - -/** LFXO oscillator modes. */ -SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) { - cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ - cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ - cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ -}; - -/** LFXO start-up timeout delay. */ -SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) { - cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ - cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ - cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ - cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ - cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ - cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ - cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ - cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ -}; - -/** HFXO oscillator modes. */ -SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) { - cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ - cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ -#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) - cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */ -#endif -}; - -/** HFXO core bias LSB change timeout. */ -SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) { - cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ - cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ - cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ - cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ - cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ - cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ - cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ - cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ - cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ - cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ - cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ - cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ - cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ - cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ - cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ - cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ -}; - -/** HFXO steady state timeout. */ -SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) { - cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ - cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ - cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ - cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ - cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ - cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ - cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ - cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ - cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ - cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ - cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ - cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ - cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ - cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ - cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ -#if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US) - cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ -#endif -}; - -/** HFXO core degeneration control. */ -SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) { - cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ - cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ - cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ - cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ -}; - -/** HFXO XI and XO pin fixed capacitor control. */ -SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) { - cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ - cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ - cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ - cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ -}; - -/** Oscillator precision modes. */ -SL_ENUM(CMU_Precision_TypeDef) { - cmuPrecisionDefault, /**< Default precision mode. */ - cmuPrecisionHigh, /**< High precision mode. */ -}; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { - uint8_t gain; /**< Startup gain. */ - uint8_t capTune; /**< Internal capacitance tuning. */ - CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ - CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ - bool highAmplitudeEn; /**< High amplitude enable. */ - bool agcEn; /**< AGC enable. */ - bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ - bool failDetEn; /**< Oscillator failure detection enable. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Lock register access. */ -} CMU_LFXOInit_TypeDef; - -/** Default LFXO initialization values for XTAL mode. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - 1, \ - 38, \ - cmuLfxoStartupDelay_4KCycles, \ - cmuLfxoOscMode_Crystal, \ - false, /* highAmplitudeEn */ \ - true, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default LFXO initialization values for external clock mode. */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - 0U, \ - 0U, \ - cmuLfxoStartupDelay_2Cycles, \ - cmuLfxoOscMode_External, \ - false, /* highAmplitudeEn */ \ - false, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default LFXO initialization values for external sine mode. */ -#define CMU_LFXOINIT_EXTERNAL_SINE \ - { \ - 0U, \ - 0U, \ - cmuLfxoStartupDelay_2Cycles, \ - cmuLfxoOscMode_AcCoupledSine, \ - false, /* highAmplitudeEn */ \ - false, /* agcEn */ \ - false, /* failDetEM4WUEn */ \ - false, /* failDetEn */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** HFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { - CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ - CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ - CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ - uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ - uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ - uint8_t coreBiasStartup; /**< Core bias startup current. */ - uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ - CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ - CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ - uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ - uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ - uint8_t coreBiasAna; /**< Core bias current. */ - bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ - CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ - bool forceXo2GndAna; /**< Force XO pin to ground. */ - bool forceXi2GndAna; /**< Force XI pin to ground. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ -#if defined(HFXO_CTRL_EM23ONDEMAND) - bool em23OnDemand; /**< Enable deep sleep. */ -#endif - bool regLock; /**< Lock register access. */ -} CMU_HFXOInit_TypeDef; - -#if defined(HFXO_CTRL_EM23ONDEMAND) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -// See [PM-2871] for details. -/** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \ - && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) -// See [PM-5131] for details. -/** - * Default configuration of fixed tuning capacitance on XO for EFR32XG24 - * when high power PA is present and output dBm equal 20 dBm. - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -// See [PM-5638] for details. -/** - * Default configuration of fixed tuning capacitance on XO for EFR32XG25 - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo -#else -/** - * Default configuration of fixed tuning capacitance on XO and XI. - */ -#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both -#endif - -/** Default HFXO initialization values for XTAL mode. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - cmuHfxoCbLsbTimeout_416us, \ - cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ - cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 32U, /* coreBiasStartup */ \ - 32U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \ - _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ - _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ - 60U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna */ \ - cmuHfxoOscMode_Crystal, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode. */ -#define CMU_HFXOINIT_EXTERNAL_SINE \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSine, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode with peak detector. */ -#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSinePkDet, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false, /* em23OnDemand */ \ - false /* Lock registers */ \ - } -#else -/** Default HFXO initialization values for XTAL mode. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - cmuHfxoCbLsbTimeout_416us, \ - cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ - cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 32U, /* coreBiasStartup */ \ - 32U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_Both, \ - _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ - _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ - 60U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna */ \ - cmuHfxoOscMode_Crystal, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode. */ -#define CMU_HFXOINIT_EXTERNAL_SINE \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSine, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } - -/** Default HFXO initialization values for external sine mode with peak detector. */ -#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ - { \ - (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ - (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ - 0U, /* ctuneXoStartup */ \ - 0U, /* ctuneXiStartup */ \ - 0U, /* coreBiasStartup */ \ - 0U, /* imCoreBiasStartup */ \ - cmuHfxoCoreDegen_None, \ - cmuHfxoCtuneFixCap_None, \ - 0U, /* ctuneXoAna */ \ - 0U, /* ctuneXiAna */ \ - 0U, /* coreBiasAna */ \ - false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ - cmuHfxoOscMode_ExternalSinePkDet, \ - false, /* forceXo2GndAna */ \ - false, /* forceXi2GndAna (Never enable in sine mode) */ \ - false, /* DisOndemand */ \ - false, /* ForceEn */ \ - false /* Lock registers */ \ - } -#endif - -#if defined(_HFXO_BUFOUTCTRL_MASK) - -/** Crystal sharing timeout start up timeout. */ -SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) { - startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */ - startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */ - startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */ - startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */ - startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */ - startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */ - startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */ - startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */ - startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */ - startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */ - startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */ - startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */ - startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */ - startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */ - startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */ - startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */ -}; - -/** Crystal sharing leader initialization structure. */ -typedef struct { - bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */ - CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */ -} CMU_BUFOUTLeaderInit_TypeDef; - -/** Default crystal sharing master initialization values. */ -#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \ - { \ - true, /* minimalStartupDelay */ \ - startupTimeout208Us, /* timeoutStartup */ \ - } -#endif - -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -/** PRS status select output signal. */ -SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) { - PRS_Status_select_0, /**< PRS status 0 output signal. */ - PRS_Status_select_1 /**< PRS status 1 output signal. */ -}; - -/** Crystal sharing follower initialization structure. */ -typedef struct { - CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */ - bool em23OnDemand; /**< Enable em23 on demand. */ - bool regLock; /**< Lock registers. */ -} CMU_CrystalSharingFollowerInit_TypeDef; - -/** Default crystal sharing follower initialization values. */ -#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \ - { \ - PRS_Status_select_0, /* prsStatusSelectOutput */ \ - true, /* em23OnDemand */ \ - false /* regLock */ \ - } -#endif - -/** DPLL initialization structure. - * Frequency will be Fref*(N+1)/(M+1). */ -typedef struct { - uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ - uint16_t n; /**< Factor N. 300 <= N <= 4095 */ - uint16_t m; /**< Factor M. M <= 4095 */ - CMU_Select_TypeDef refClk; /**< Reference clock selector. */ - CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ - CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ - bool autoRecover; /**< Enable automatic lock recovery. */ - bool ditherEn; /**< Enable dither functionality. */ -} CMU_DPLLInit_TypeDef; - -/** - * DPLL initialization values for 39,998,805 Hz using LFXO as reference - * clock, M=2 and N=3661. - */ -#define CMU_DPLL_LFXO_TO_40MHZ \ - { \ - 39998805, /* Target frequency. */ \ - 3661, /* Factor N. */ \ - 2, /* Factor M. */ \ - cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * DPLL initialization values for 76,800,000 Hz using HFXO as reference - * clock, M = 1919, N = 3839 - */ -#define CMU_DPLL_HFXO_TO_76_8MHZ \ - { \ - 76800000, /* Target frequency. */ \ - 3839, /* Factor N. */ \ - 1919, /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * DPLL initialization values for 80,000,000 Hz using HFXO as reference - * clock, M = 1919, N = 3999. - */ -#define CMU_DPLL_HFXO_TO_80MHZ \ - { \ - 80000000, /* Target frequency. */ \ - (4000 - 1), /* Factor N. */ \ - (1920 - 1), /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -/** - * Default configurations for DPLL initialization. When using this macro - * you need to modify the N and M factor and the desired frequency to match - * the components placed on the board. - */ -#define CMU_DPLLINIT_DEFAULT \ - { \ - 80000000, /* Target frequency. */ \ - (4000 - 1), /* Factor N. */ \ - (1920 - 1), /* Factor M. */ \ - cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true, /* Enable automatic lock recovery. */ \ - false /* Don't enable dither function. */ \ - } - -#if defined(USBPLL_PRESENT) -/** USB PLL initialization structure. */ -typedef struct { - CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */ - bool shuntRegEn; /**< Shunt regulator enable. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Enable register lock. */ -} CMU_USBPLL_Init_TypeDef; - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 38 MHz. - */ -#define CMU_USBPLL_REFFREQ_38MHZ \ - { \ - cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 38.4 MHz. - */ -#define CMU_USBPLL_REFFREQ_38_4MHZ \ - { \ - cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 39 MHz. - */ -#define CMU_USBPLL_REFFREQ_39MHZ \ - { \ - cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } - -/** - * Default configurations for USB PLL initialization if the HFXO frequency is - * 40 MHz. - */ -#define CMU_USBPLL_REFFREQ_40MHZ \ - { \ - cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \ - false, /* Disable shunt regulator. */ \ - false, /* Disable PLL always on. */ \ - false, /* Force enable. */ \ - true /* Enable register lock. */ \ - } -#endif - -#if defined(RFFPLL_PRESENT) -/** - * RFF PLL initialization structure. - * When using this structure you need to modify the X, Y and N factor - * and the desired host target frequency to match the components placed - * on the board (namely the RFFPLL reference clock). - * X, Y, N values for a 39MHz HFXO: - * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY - * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2) - */ -typedef struct { - uint32_t frequency; /**< Host target frequency. */ - bool disOnDemand; /**< Disable on-demand requests. */ - bool forceEn; /**< Force oscillator enable. */ - bool regLock; /**< Enable register lock. */ - uint8_t dividerY; /**< Divider Y for digital. */ - uint8_t dividerX; /**< Divider X for Radio. */ - uint8_t dividerN; /**< Feedback divider N. */ -} CMU_RFFPLL_Init_TypeDef; - -/** Radio frequency locked loop default initialization values. */ -#define CMU_RFFPLL_DEFAULT \ - { \ - 100000000UL, /* Host target frequency. */ \ - false, /* Disable on-demand requests. */ \ - false, /* Force enable. */ \ - true, /* Enable register lock. */ \ - _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \ - _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \ - _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \ - } - -/** Radio frequency locked loop initialization values for 97.5MHz. */ -#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \ - { \ - 97500000UL, /* Host target frequency. */ \ - false, /* Disable on-demand requests. */ \ - false, /* Force enable. */ \ - true, /* Enable register lock. */ \ - 20U, /* Divider Y for digital. */ \ - 6U, /* Divider X for Radio. */ \ - 100U /* Feedback divider N. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t cycles, - CMU_Select_TypeDef reference); -void CMU_CalibrateConfig(uint32_t downCycles, - CMU_Select_TypeDef downSel, - CMU_Select_TypeDef upSel); -uint32_t CMU_CalibrateCountGet(void); -void CMU_ClkOutPinConfig(uint32_t clkno, - CMU_Select_TypeDef sel, - CMU_ClkDiv_TypeDef clkdiv, - GPIO_Port_TypeDef port, - unsigned int pin); -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, - CMU_ClkDiv_TypeDef div); -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); -#endif -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, - CMU_Select_TypeDef ref); -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); -void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); -#if defined(USBPLL_PRESENT) -void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit); -__STATIC_INLINE void CMU_WaitUSBPLLLock(void); -#endif -#if defined(RFFPLL_PRESENT) -void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); -__STATIC_INLINE void CMU_WaitRFFPLLLock(void); -#endif -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); -#if defined(HFXO0_BUFOUT) -void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, - GPIO_Port_TypeDef port, - unsigned int pin); -#endif -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, - unsigned int prsAsyncCh, - GPIO_Port_TypeDef port, - unsigned int pin); -#endif -sl_status_t CMU_HFXOCTuneSet(uint32_t ctune); -uint32_t CMU_HFXOCTuneGet(void); -void CMU_HFXOCTuneDeltaSet(int32_t delta); -int32_t CMU_HFXOCTuneDeltaGet(void); -void CMU_HFXOCoreBiasCurrentCalibrate(void); -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); -void CMU_LFXOPrecisionSet(uint16_t precision); -uint16_t CMU_LFXOPrecisionGet(void); -void CMU_HFXOPrecisionSet(uint16_t precision); -uint16_t CMU_HFXOPrecisionGet(void); -#if defined(PLFRCO_PRESENT) -void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision); -#endif -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, - uint32_t val); -void CMU_UpdateWaitStates(uint32_t freq, int vscale); -void CMU_PCNTClockExternalSet(unsigned int instance, bool external); - -#if defined(HFRCOEM23_PRESENT) -CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); -void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @note - * This is a dummy function to solve backward compatibility issues. - * - * @param[in] clock - * The clock to enable/disable. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -__STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - (void)clock; - (void)enable; -} -#endif - -/***************************************************************************//** - * @brief - * Configure continuous calibration mode. - * @param[in] enable - * If true, enables continuous calibration, if false disables continuous - * calibration. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateCont(bool enable) -{ - BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Start calibration. - * @note - * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly - * @ref CMU_CalibrateCont(). - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStart(void) -{ - CMU->CALCMD = CMU_CALCMD_CALSTART; -} - -/***************************************************************************//** - * @brief - * Stop calibration counters. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStop(void) -{ - CMU->CALCMD = CMU_CALCMD_CALSTOP; -} - -/***************************************************************************//** - * @brief - * Unlock the DPLL. - * @note - * The HFRCODPLL oscillator is not turned off. - ******************************************************************************/ -__STATIC_INLINE void CMU_DPLLUnlock(void) -{ - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { - } -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending CMU interrupt flags. - * - * @param[in] flags - * CMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntClear(uint32_t flags) -{ - CMU->IF_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more CMU interrupt sources. - * - * @param[in] flags - * CMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntDisable(uint32_t flags) -{ - CMU->IEN_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more CMU interrupt sources. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using @ref CMU_IntClear() prior to - * enabling if such a pending interrupt should be ignored. - * - * @param[in] flags - * CMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntEnable(uint32_t flags) -{ - CMU->IEN_SET = flags; -} - -/***************************************************************************//** - * @brief - * Get pending CMU interrupt sources. - * - * @return - * CMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGet(void) -{ - return CMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending CMU interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * Pending and enabled CMU interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in CMU_IEN and - * - the pending interrupt flags CMU_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = CMU->IEN; - return CMU->IF & ien; -} - -/**************************************************************************//** - * @brief - * Set one or more pending CMU interrupt sources. - * - * @param[in] flags - * CMU interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void CMU_IntSet(uint32_t flags) -{ - CMU->IF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Lock CMU register access in order to protect registers contents against - * unintended modification. - * - * @details - * See the reference manual for CMU registers that will be - * locked. - * - * @note - * If locking the CMU registers, they must be unlocked prior to using any - * CMU API functions modifying CMU registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_Lock(void) -{ - CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Enable/disable oscillator. - * - * @note - * This is a dummy function to solve backward compatibility issues. - * - * @param[in] osc - * The oscillator to enable/disable. - * - * @param[in] enable - * @li true - enable specified oscillator. - * @li false - disable specified oscillator. - * - * @param[in] wait - * Only used if @p enable is true. - * @li true - wait for oscillator start-up time to timeout before returning. - * @li false - do not wait for oscillator start-up time to timeout before - * returning. - ******************************************************************************/ -__STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, - bool enable, - bool wait) -{ - (void)osc; - (void)enable; - (void)wait; -} - -/***************************************************************************//** - * @brief - * Unlock CMU register access so that writing to registers is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_Unlock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Lock WDOG register access in order to protect registers contents against - * unintended modification. - * - * @note - * If locking the WDOG registers, they must be unlocked prior to using any - * emlib API functions modifying registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_WdogLock(void) -{ - CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Unlock WDOG register access so that writing to registers is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_WdogUnlock(void) -{ - CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; -} - -#if defined(USBPLL_PRESENT) -/***************************************************************************//** - * @brief - * Wait for USB PLL lock and ready. - ******************************************************************************/ -__STATIC_INLINE void CMU_WaitUSBPLLLock() -{ - while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) - != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { - /* Wait for USB PLL lock and ready */ - } -} -#endif - -#if defined(RFFPLL_PRESENT) -/***************************************************************************//** - * @brief - * Wait for RFF PLL lock and ready. - ******************************************************************************/ -__STATIC_INLINE void CMU_WaitRFFPLLLock() -{ - while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) - != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { - /* Wait for RFF PLL lock and ready. */ - } -} -#endif - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/* Select register IDs for internal use. */ -#define CMU_NOSEL_REG 0 -#define CMU_HFCLKSEL_REG 1 -#define CMU_LFACLKSEL_REG 2 -#define CMU_LFBCLKSEL_REG 3 -#define CMU_LFCCLKSEL_REG 4 -#define CMU_LFECLKSEL_REG 5 -#define CMU_DBGCLKSEL_REG 6 -#define CMU_USBCCLKSEL_REG 7 -#define CMU_ADC0ASYNCSEL_REG 8 -#define CMU_ADC1ASYNCSEL_REG 9 -#define CMU_SDIOREFSEL_REG 10 -#define CMU_QSPI0REFSEL_REG 11 -#define CMU_USBRCLKSEL_REG 12 -#define CMU_PDMREFSEL_REG 13 - -#define CMU_SEL_REG_POS 0U -#define CMU_SEL_REG_MASK 0xfU - -/* Divisor/prescaler register IDs for internal use. */ -#define CMU_NODIV_REG 0 -#define CMU_NOPRESC_REG 0 -#define CMU_HFPRESC_REG 1 -#define CMU_HFCLKDIV_REG 1 -#define CMU_HFEXPPRESC_REG 2 -#define CMU_HFCLKLEPRESC_REG 3 -#define CMU_HFPERPRESC_REG 4 -#define CMU_HFPERCLKDIV_REG 4 -#define CMU_HFPERPRESCB_REG 5 -#define CMU_HFPERPRESCC_REG 6 -#define CMU_HFCOREPRESC_REG 7 -#define CMU_HFCORECLKDIV_REG 7 -#define CMU_LFAPRESC0_REG 8 -#define CMU_LFBPRESC0_REG 9 -#define CMU_LFEPRESC0_REG 10 -#define CMU_ADCASYNCDIV_REG 11 -#define CMU_HFBUSPRESC_REG 12 -#define CMU_HFCORECLKLEDIV_REG 13 - -#define CMU_PRESC_REG_POS 4U -#define CMU_DIV_REG_POS CMU_PRESC_REG_POS -#define CMU_PRESC_REG_MASK 0xfU -#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK - -/* Enable register IDs for internal use. */ -#define CMU_NO_EN_REG 0 -#define CMU_CTRL_EN_REG 1 -#define CMU_HFPERCLKDIV_EN_REG 1 -#define CMU_HFPERCLKEN0_EN_REG 2 -#define CMU_HFCORECLKEN0_EN_REG 3 -#define CMU_PDMREF_EN_REG 4 -#define CMU_HFBUSCLKEN0_EN_REG 5 -#define CMU_LFACLKEN0_EN_REG 6 -#define CMU_LFBCLKEN0_EN_REG 7 -#define CMU_LFCCLKEN0_EN_REG 8 -#define CMU_LFECLKEN0_EN_REG 9 -#define CMU_PCNT_EN_REG 10 -#define CMU_SDIOREF_EN_REG 11 -#define CMU_QSPI0REF_EN_REG 12 -#define CMU_QSPI1REF_EN_REG 13 -#define CMU_HFPERCLKEN1_EN_REG 14 -#define CMU_USBRCLK_EN_REG 15 - -#define CMU_EN_REG_POS 8U -#define CMU_EN_REG_MASK 0xfU - -/* Enable register bit positions, for internal use. */ -#define CMU_EN_BIT_POS 12U -#define CMU_EN_BIT_MASK 0x1fU - -/* Clock branch bitfield positions, for internal use. */ -#define CMU_HF_CLK_BRANCH 0 -#define CMU_HFCORE_CLK_BRANCH 1 -#define CMU_HFPER_CLK_BRANCH 2 -#define CMU_HFPERB_CLK_BRANCH 3 -#define CMU_HFPERC_CLK_BRANCH 4 -#define CMU_HFBUS_CLK_BRANCH 5 -#define CMU_HFEXP_CLK_BRANCH 6 -#define CMU_DBG_CLK_BRANCH 7 -#define CMU_AUX_CLK_BRANCH 8 -#define CMU_RTC_CLK_BRANCH 9 -#define CMU_RTCC_CLK_BRANCH 10 -#define CMU_LETIMER0_CLK_BRANCH 11 -#define CMU_LETIMER1_CLK_BRANCH 12 -#define CMU_LEUART0_CLK_BRANCH 13 -#define CMU_LEUART1_CLK_BRANCH 14 -#define CMU_LFA_CLK_BRANCH 15 -#define CMU_LFB_CLK_BRANCH 16 -#define CMU_LFC_CLK_BRANCH 17 -#define CMU_LFE_CLK_BRANCH 18 -#define CMU_USBC_CLK_BRANCH 19 -#define CMU_USBLE_CLK_BRANCH 20 -#define CMU_LCDPRE_CLK_BRANCH 21 -#define CMU_LCD_CLK_BRANCH 22 -#define CMU_LESENSE_CLK_BRANCH 23 -#define CMU_CSEN_LF_CLK_BRANCH 24 -#define CMU_ADC0ASYNC_CLK_BRANCH 25 -#define CMU_ADC1ASYNC_CLK_BRANCH 26 -#define CMU_SDIOREF_CLK_BRANCH 27 -#define CMU_QSPI0REF_CLK_BRANCH 28 -#define CMU_USBR_CLK_BRANCH 29 -#define CMU_PDMREF_CLK_BRANCH 30 -#define CMU_HFLE_CLK_BRANCH 31 - -#define CMU_CLK_BRANCH_POS 17U -#define CMU_CLK_BRANCH_MASK 0x1fU - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) -/* Maximum clock frequency for VSCALE voltages. */ -#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL -#endif - -/* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API. - * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for - * Series1 parts (highest VSCALE voltage = lowest numerical value). */ -#define VSCALE_EM01_LOW_POWER 2 -#define VSCALE_EM01_HIGH_PERFORMANCE 0 - -#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) -#define USBC_CLOCK_PRESENT -#endif -#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) -#define USBR_CLOCK_PRESENT -#endif -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define PLFRCO_PRESENT -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Clock divisors. These values are valid for prescalers. */ -#define cmuClkDiv_1 1 /**< Divide clock by 1. */ -#define cmuClkDiv_2 2 /**< Divide clock by 2. */ -#define cmuClkDiv_4 4 /**< Divide clock by 4. */ -#define cmuClkDiv_8 8 /**< Divide clock by 8. */ -#define cmuClkDiv_16 16 /**< Divide clock by 16. */ -#define cmuClkDiv_32 32 /**< Divide clock by 32. */ -#define cmuClkDiv_64 64 /**< Divide clock by 64. */ -#define cmuClkDiv_128 128 /**< Divide clock by 128. */ -#define cmuClkDiv_256 256 /**< Divide clock by 256. */ -#define cmuClkDiv_512 512 /**< Divide clock by 512. */ -#define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ -#define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ -#define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ -#define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ -#define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ -#define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ - -/** Clock divider configuration */ -typedef uint32_t CMU_ClkDiv_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_1) -/** Clockprescaler configuration */ -typedef uint32_t CMU_ClkPresc_TypeDef; -#endif - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/** High-frequency system RCO bands */ -SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) { - cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ - cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ - cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ - cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ - cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ -#if defined(CMU_HFRCOCTRL_BAND_28MHZ) - cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ -#endif -}; -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/** AUX high-frequency RCO bands */ -SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) { - cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ - cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ - cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ - cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ - cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ -#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) - cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ -#endif -}; -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/** Universal serial high-frequency RC bands */ -SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) { - /** 24 MHz RC band. */ - cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, - /** 48 MHz RC band. */ - cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, -}; -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -/** High-USHFRCO bands */ -SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) { - cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ - cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ - cmuUSHFRCOFreq_UserDefined = 0, -}; -/** USHFRCO minimum frequency */ -#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz -/** USHFRCO maximum frequency */ -#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz -#endif - -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -/** High-frequency system RCO bands */ -SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) { - cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ - cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ - cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ - cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ - cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ - cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ - cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ - cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ -#if defined(_DEVINFO_HFRCOCAL13_MASK) - cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL14_MASK) - cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL15_MASK) - cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ -#endif -#if defined(_DEVINFO_HFRCOCAL16_MASK) - cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ -#endif - cmuHFRCOFreq_UserDefined = 0, -}; - -/** HFRCO minimum frequency. */ -#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz -#if defined(_DEVINFO_HFRCOCAL16_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz -#elif defined(_DEVINFO_HFRCOCAL15_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz -#elif defined(_DEVINFO_HFRCOCAL14_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz -#elif defined(_DEVINFO_HFRCOCAL13_MASK) -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz -#else -/** HFRCO maximum frequency. */ -#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz -#endif -#endif - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/** AUX high-frequency RCO bands */ -SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) { - cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ - cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ - cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ - cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ - cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ - cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ - cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ - cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ - cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ - cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ -#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) - cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ -#endif -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) - cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ -#endif - cmuAUXHFRCOFreq_UserDefined = 0, -}; -/** AUXHFRCO minimum frequency. */ -#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz -#elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz -#else -/** AUXHFRCO maximum frequency. */ -#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz -#endif -#endif - -/** Clock points in CMU. See CMU overview in the reference manual. */ -SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { - /*******************/ - /* HF clock branch */ - /*******************/ - - /** High-frequency clock */ -#if defined(_CMU_CTRL_HFCLKDIV_MASK) \ - || defined(_CMU_HFPRESC_MASK) - cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /** Debug clock */ - cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** AUX clock */ - cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(_CMU_HFEXPPRESC_MASK) - /**********************/ - /* HF export sub-branch */ - /**********************/ - - /** Export clock */ - cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_MASK) -/**********************************/ -/* HF bus clock sub-branch */ -/**********************************/ - - /** High-frequency bus clock */ -#if defined(_CMU_HFBUSPRESC_MASK) - cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO) - /** Cryptography accelerator clock */ - cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO0) - /** Cryptography accelerator 0 clock */ - cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_CRYPTO1) - /** Cryptography accelerator 1 clock */ - cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_LDMA) - /** Direct-memory access controller clock */ - cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_QSPI0) - /** Quad SPI clock */ - cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_GPCRC) - /** General-purpose cyclic redundancy checksum clock */ - cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFBUSCLKEN0_GPIO) - /** General-purpose input/output clock */ - cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /** Low-energy clock divided down from HFCLK */ - cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_HFBUSCLKEN0_PRS) - /** Peripheral reflex system clock */ - cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) - | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - - /**********************************/ - /* HF peripheral clock sub-branch */ - /**********************************/ - - /** High-frequency peripheral clock */ -#if defined(_CMU_HFPRESC_MASK) - cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#else - cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERPRESCB_MASK) - /** Branch B figh-frequency peripheral clock */ - cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - /** Branch C figh-frequency peripheral clock */ - cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) - | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_PDM) - /** PDM clock */ - cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART0) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USARTRF0) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USARTRF1) - /** Universal sync/async receiver/transmitter 0 clock */ - cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART1) - /** Universal sync/async receiver/transmitter 1 clock */ - cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART2) - /** Universal sync/async receiver/transmitter 2 clock */ - cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCB_MASK) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_USART3) - /** Universal sync/async receiver/transmitter 3 clock */ - cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART4) - /** Universal sync/async receiver/transmitter 4 clock */ - cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_USART5) - /** Universal sync/async receiver/transmitter 5 clock */ - cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_UART0) - /** Universal async receiver/transmitter 0 clock */ - cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFPERCLKEN1_UART0_MASK) - /** Universal async receiver/transmitter 0 clock */ - cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_UART1) - /** Universal async receiver/transmitter 1 clock */ - cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFPERCLKEN1_UART1_MASK) - /** Universal async receiver/transmitter 1 clock */ - cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER0) - /** Timer 0 clock */ - cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCB_MASK) - | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER1) - /** Timer 1 clock */ - cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER2) - /** Timer 2 clock */ - cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER3) - /** Timer 3 clock */ - cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER4) - /** Timer 4 clock */ - cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER5) - /** Timer 5 clock */ - cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TIMER6) - /** Timer 6 clock */ - cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_WTIMER0) - /** Wide-timer 0 clock */ - cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_WTIMER0) - /** Wide-timer 0 clock */ - cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_WTIMER1) - /** Wide-timer 1 clock */ - cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_WTIMER1) - /** Wide-timer 1 clock */ - cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN1_WTIMER2) - /** Wide-timer 2 clock */ - cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN1_WTIMER3) - /** Wide-timer 3 clock */ - cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_CRYOTIMER) - /** CRYOtimer clock */ - cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP0) - /** Analog comparator 0 clock */ - cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP1) - /** Analog comparator 1 clock */ - cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP2) - /** Analog comparator 2 clock */ - cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_ACMP3) - /** Analog comparator 3 clock */ - cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_PRS) - /** Peripheral-reflex system clock */ - cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_DAC0) - /** Digital-to-analog converter 0 clock */ - cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_VDAC0) - /** Voltage digital-to-analog converter 0 clock */ - cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_VDAC0) - /** Voltage digital-to-analog converter 0 clock */ - cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_IDAC0) - /** Current digital-to-analog converter 0 clock */ - cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_GPIO) - /** General-purpose input/output clock */ - cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_VCMP) - /** Voltage comparator clock */ - cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_ADC0) - /** Analog-to-digital converter 0 clock */ - cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_ADC1) - /** Analog-to-digital converter 1 clock */ - cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_I2C0) - /** I2C 0 clock */ - cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_I2C1) - /** I2C 1 clock */ - cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) - #if defined(_CMU_HFPERPRESCC_MASK) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #else - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), - #endif -#endif - -#if defined(CMU_HFPERCLKEN0_I2C2) - /** I2C 2 clock */ - cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_CSEN) - /** Capacitive Sense HF clock */ - cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFPERCLKEN1_CSEN) - /** Capacitive Sense HF clock */ - cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFPERCLKEN0_TRNG0) - /** True random number generator clock */ - cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERCLKEN1_CAN0_MASK) - /** Controller Area Network 0 clock */ - cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFPERCLKEN1_CAN1_MASK) - /** Controller Area Network 1 clock. */ - cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /**********************/ - /* HF core sub-branch */ - /**********************/ - - /** Core clock */ - cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_HFCORECLKEN0_AES) - /** Advanced encryption standard accelerator clock */ - cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_DMA) - /** Direct memory access controller clock */ - cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_LE) - /** Low-energy clock divided down from HFCORECLK */ - cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_EBI) - /** External bus interface clock */ - cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) - /** External bus interface clock */ - cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_ETH_MASK) - /** Ethernet clock */ - cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) - /** SDIO clock */ - cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(USBC_CLOCK_PRESENT) - /** USB Core clock */ - cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#if defined (USBR_CLOCK_PRESENT) - /** USB Rate clock */ - cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) - | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_HFCORECLKEN0_USB) - /** USB clock */ - cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_HFBUSCLKEN0_USB) - /** USB clock */ - cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /***************/ - /* LF A branch */ - /***************/ - - /** Low-frequency A clock */ - cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFACLKEN0_RTC) - /** Real time counter clock */ - cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) - | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LETIMER0) - /** Low-energy timer 0 clock */ - cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) - | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LETIMER1) - /** Low-energy timer 1 clock */ - cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) - | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFACLKEN0_LCD) - /** Liquid crystal display, pre FDIV clock */ - cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** Liquid crystal display clock. Note that FDIV prescaler - * must be set by special API. */ - cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) - | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT0CLKEN) - /** Pulse counter 0 clock */ - cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT1CLKEN) - /** Pulse counter 1 clock */ - cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_PCNTCTRL_PCNT2CLKEN) - /** Pulse counter 2 clock */ - cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) - | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#if defined(CMU_LFACLKEN0_LESENSE) - /** LESENSE clock */ - cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) - | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - - /***************/ - /* LF B branch */ - /***************/ - - /** Low-frequency B clock */ - cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFBCLKEN0_LEUART0) - /** Low-energy universal asynchronous receiver/transmitter 0 clock */ - cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_CSEN) - /** Capacitive Sense LF clock */ - cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_LEUART1) - /** Low-energy universal asynchronous receiver/transmitter 1 clock */ - cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(CMU_LFBCLKEN0_SYSTICK) - /** Cortex SYSTICK LF clock */ - cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) - | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_LFCCLKEN0_MASK) - /***************/ - /* LF C branch */ - /***************/ - - /** Low-frequency C clock */ - cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), - -#if defined(CMU_LFCCLKEN0_USBLE) - /** USB LE clock */ - cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#elif defined(CMU_LFCCLKEN0_USB) - /** USB LE clock */ - cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) - | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - -#if defined(_CMU_LFECLKEN0_MASK) - /***************/ - /* LF E branch */ - /***************/ - - /** Low-frequency E clock */ - cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) - | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), - - /** Real-time counter and calendar clock */ -#if defined (CMU_LFECLKEN0_RTCC) - cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) - | (CMU_NOSEL_REG << CMU_SEL_REG_POS) - | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) - | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) - | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -#endif - - /**********************************/ - /* Asynchronous peripheral clocks */ - /**********************************/ - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - /** ADC0 asynchronous clock */ - cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) - | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - /** ADC1 asynchronous clock */ - cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) - | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) - | (CMU_NO_EN_REG << CMU_EN_REG_POS) - | (0 << CMU_EN_BIT_POS) - | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) - /** SDIO reference clock */ - cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) - | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) - | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) - | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) - /** QSPI0 reference clock */ - cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) - | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) - | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) - | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) - /** PDM reference clock */ - cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) - | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) - | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) - | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) - | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), -#endif -}; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated CMU_Clock_TypeDef member */ -#define cmuClock_CORELE cmuClock_HFLE -/** @endcond */ - -/** Oscillator types. */ -SL_ENUM(CMU_Osc_TypeDef) { - cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ - cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ - cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ - cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ - cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - cmuOsc_CLKIN0, /**< External oscillator. */ -#endif -#if defined(PLFRCO_PRESENT) - cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ -#endif -}; - -/** Oscillator modes. */ -SL_ENUM(CMU_OscMode_TypeDef) { - cmuOscMode_Crystal, /**< Crystal oscillator. */ - cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ - cmuOscMode_External, /**< External digital clock. */ -}; - -/** Selectable clock sources. */ -SL_ENUM(CMU_Select_TypeDef) { - cmuSelect_Error, /**< Usage error. */ - cmuSelect_Disabled, /**< Clock selector disabled. */ - cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ - cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ - cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ - cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ - cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ - cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */ - cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ - cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on - Tiny Gecko and for USBC (not used on Gecko). */ -#if defined(CMU_STATUS_USHFRCOENS) - cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ -#endif -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ -#endif -#if defined(CMU_HFXOCTRL_HFXOX2EN) - cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - cmuSelect_CLKIN0, /**< External clock input. */ -#endif -#if defined(PLFRCO_PRESENT) - cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ -#endif -}; - -#if defined(CMU_HFCORECLKEN0_LE) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated CMU_Select_TypeDef member */ -#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE -/** @endcond */ -#endif - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -/** HFXO tuning modes */ -SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) { - cmuHFXOTuningMode_Auto = 0, - cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ - cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ - | CMU_CMD_HFXOSHUNTOPTSTART, -#endif -}; -#endif - -#if defined(_CMU_CTRL_LFXOBOOST_MASK) -/** LFXO Boost values. */ -SL_ENUM(CMU_LFXOBoost_TypeDef) { - cmuLfxoBoost70 = 0x0, - cmuLfxoBoost100 = 0x2, -#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) - cmuLfxoBoost70Reduced = 0x1, - cmuLfxoBoost100Reduced = 0x3, -#endif -}; -#endif - -#if defined(CMU_OSCENCMD_DPLLEN) -/** DPLL reference clock selector. */ -SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) { - cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ - cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ - cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ -}; - -/** DPLL reference clock edge detect selector. */ -SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) { - cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ - cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ -}; - -/** DPLL lock mode selector. */ -SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { - cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ - cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ -}; -#endif // CMU_OSCENCMD_DPLLEN - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { -#if defined(_CMU_LFXOCTRL_MASK) - uint8_t ctune; /**< CTUNE (load capacitance) value */ - uint8_t gain; /**< Gain/max startup margin */ -#else - CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ -#endif - uint8_t timeout; /**< Startup delay */ - CMU_OscMode_TypeDef mode; /**< Oscillator mode */ -} CMU_LFXOInit_TypeDef; - -#if defined(_CMU_LFXOCTRL_MASK) -/** Default LFXO initialization values. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ - _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ - _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ - cmuOscMode_Crystal, /* Crystal oscillator */ \ - } -/** Default LFXO initialization for external clock */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - 0, /* No CTUNE value needed */ \ - 0, /* No LFXO startup gain */ \ - _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ - cmuOscMode_External, /* External digital clock */ \ - } -#else -/** Default LFXO initialization values. */ -#define CMU_LFXOINIT_DEFAULT \ - { \ - cmuLfxoBoost70, \ - _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -/** Default LFXO initialization for external clock */ -#define CMU_LFXOINIT_EXTERNAL_CLOCK \ - { \ - cmuLfxoBoost70, \ - _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ - cmuOscMode_External, \ - } -#endif - -/** HFXO initialization structure. - * Initialization values should be obtained from a configuration tool, - * application note or crystal data sheet. */ -typedef struct { -#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) - uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ - uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ - uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ - uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ - uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ - uint8_t timeoutSteady; /**< Timeout - steady-state */ - uint8_t timeoutStartup; /**< Timeout - startup */ -#elif defined(_CMU_HFXOCTRL_MASK) - bool lowPowerMode; /**< Enable low-power mode */ - bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ - uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ - uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ - uint8_t regIshSteadyState; /**< Shunt steady-state current */ - uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ - uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ - uint8_t thresholdPeakDetect; /**< Peak detection threshold */ - uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ - uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ - uint8_t timeoutSteady; /**< Timeout - steady-state */ - uint8_t timeoutStartup; /**< Timeout - startup */ -#else - uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ - uint8_t timeout; /**< Startup delay */ - bool glitchDetector; /**< Enable/disable glitch detector */ -#endif - CMU_OscMode_TypeDef mode; /**< Oscillator mode */ -} CMU_HFXOInit_TypeDef; - -#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) -/** Default HFXO init. */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -/** Init of HFXO with external clock. */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_External, \ - } -#elif defined(_CMU_HFXOCTRL_MASK) -/** - * Default HFXO initialization values for Platform 2 devices, which contain a - * separate HFXOCTRL register. - */ -#if defined(_EFR_DEVICE) -#define CMU_HFXOINIT_DEFAULT \ - { \ - false, /* Low-noise mode for EFR32 */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - 0xA, /* Default Shunt steady-state current */ \ - 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ - 0x7, /* Recommended steady-state XO core bias current */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0xA, /* Recommended peak detection timeout */ \ - 0x4, /* Recommended steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -#else /* EFM32 device */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - true, /* Low-power mode for EFM32 */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ - _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ - 0xA, /* Default shunt steady-state current */ \ - 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ - 0x7, /* Recommended steady-state osc core bias current */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0xA, /* Recommended peak detection timeout */ \ - 0x4, /* Recommended steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ - cmuOscMode_Crystal, \ - } -#endif /* _EFR_DEVICE */ -/** Init of HFXO with external clock. */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - true, /* Low-power mode */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - false, /* @deprecated no longer in use */ \ - 0, /* Startup CTUNE=0 recommended for external clock */ \ - 0, /* Steady CTUNE=0 recommended for external clock */ \ - 0xA, /* Default shunt steady-state current */ \ - 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ - 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ - 0x6, /* Recommended peak detection threshold */ \ - 0x2, /* Recommended shunt optimization timeout */ \ - 0x0, /* Peak-detect not recommended for external clock usage */ \ - _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ - _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ - cmuOscMode_External, \ - } -#else /* _CMU_HFXOCTRL_MASK */ -/** - * Default HFXO initialization values for Platform 1 devices. - */ -#define CMU_HFXOINIT_DEFAULT \ - { \ - _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ - _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ - false, /* Disable glitch detector */ \ - cmuOscMode_Crystal, /* Crystal oscillator */ \ - } -/** Default HFXO initialization for external clock */ -#define CMU_HFXOINIT_EXTERNAL_CLOCK \ - { \ - 0, /* Minimal HFXO boost, 50% */ \ - _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ - false, /* Disable glitch detector */ \ - cmuOscMode_External, /* External digital clock */ \ - } -#endif /* _CMU_HFXOCTRL_MASK */ - -#if defined(CMU_OSCENCMD_DPLLEN) -/** DPLL initialization structure. - * Frequency will be Fref*(N+1)/(M+1). */ -typedef struct { - uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ - uint16_t n; /**< Factor N. 300 <= N <= 4095 */ - uint16_t m; /**< Factor M. M <= 4095 */ - uint8_t ssInterval; /**< Spread spectrum update interval. */ - uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ - CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ - CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ - CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ - bool autoRecover; /**< Enable automatic lock recovery. */ -} CMU_DPLLInit_TypeDef; - -/** - * DPLL initialization values for 39,998,805 Hz using LFXO as reference - * clock, M=2 and N=3661. - */ -#define CMU_DPLL_LFXO_TO_40MHZ \ - { \ - 39998805, /* Target frequency. */ \ - 3661, /* Factor N. */ \ - 2, /* Factor M. */ \ - 0, /* No spread spectrum clocking. */ \ - 0, /* No spread spectrum clocking. */ \ - cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ - cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ - cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ - true /* Enable automatic lock recovery. */ \ - } -#endif // CMU_OSCENCMD_DPLLEN - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); - -#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); -#endif - -uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); - -#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, - CMU_Osc_TypeDef upSel); -#endif - -uint32_t CMU_CalibrateCountGet(void); -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); - -#if defined(_SILICON_LABS_32B_SERIES_1) -void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); -uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); -#endif - -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); - -#if defined(CMU_OSCENCMD_DPLLEN) -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); -#endif -void CMU_FreezeEnable(bool enable); - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); -void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); - -#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); -void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); -#endif - -#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) -uint32_t CMU_HFRCOStartupDelayGet(void); -void CMU_HFRCOStartupDelaySet(uint32_t delay); -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); -void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); -uint32_t CMU_USHFRCOFreqGet(void); -#endif - -#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) -void CMU_HFXOAutostartEnable(uint32_t userSel, - bool enEM0EM1Start, - bool enEM0EM1StartSel); -#endif - -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); - -uint32_t CMU_LCDClkFDIVGet(void); -void CMU_LCDClkFDIVSet(uint32_t div); -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); -void CMU_LFXOPrecisionSet(uint16_t precision); -uint16_t CMU_LFXOPrecisionGet(void); -void CMU_HFXOPrecisionSet(uint16_t precision); -uint16_t CMU_HFXOPrecisionGet(void); - -void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); -bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode, - bool wait); -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) -void CMU_PCNTClockExternalSet(unsigned int instance, bool external); -bool CMU_PCNTClockExternalGet(unsigned int instance); -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); -void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); -uint32_t CMU_USHFRCOFreqGet(void); -#endif -void CMU_UpdateWaitStates(uint32_t freq, int vscale); - -#if defined(CMU_CALCTRL_CONT) -/***************************************************************************//** - * @brief - * Configure continuous calibration mode. - * @param[in] enable - * If true, enables continuous calibration, if false disables continuous - * calibration. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateCont(bool enable) -{ - BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); -} -#endif - -/***************************************************************************//** - * @brief - * Start calibration. - * @note - * This call is usually invoked after CMU_CalibrateConfig() and possibly - * CMU_CalibrateCont(). - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStart(void) -{ - CMU->CMD = CMU_CMD_CALSTART; -} - -#if defined(CMU_CMD_CALSTOP) -/***************************************************************************//** - * @brief - * Stop the calibration counters. - ******************************************************************************/ -__STATIC_INLINE void CMU_CalibrateStop(void) -{ - CMU->CMD = CMU_CMD_CALSTOP; -} -#endif - -/***************************************************************************//** - * @brief - * Convert divider to logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param[in] div - * An unscaled divider. - * - * @return - * Logarithm base 2 (binary) value, i.e. exponent as used by fixed - * 2^n prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) -{ - uint32_t log2; - - /* Fixed 2^n prescalers take argument of 32768 or less. */ - EFM_ASSERT((div > 0U) && (div <= 32768U)); - - /* Count leading zeroes and "reverse" result */ - log2 = 31UL - __CLZ(div); - - return log2; -} - -#if defined(CMU_OSCENCMD_DPLLEN) -/***************************************************************************//** - * @brief - * Unlock DPLL. - * @note - * HFRCO is not turned off. - ******************************************************************************/ -__STATIC_INLINE void CMU_DPLLUnlock(void) -{ - CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; -} -#endif - -/***************************************************************************//** - * @brief - * Clear one or more pending CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntClear(uint32_t flags) -{ - CMU->IFC = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntDisable(uint32_t flags) -{ - CMU->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more CMU interrupts. - * - * @note - * Depending on use case, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling - * if the pending interrupt should be ignored. - * - * @param[in] flags - * CMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void CMU_IntEnable(uint32_t flags) -{ - CMU->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending CMU interrupts. - * - * @return - * CMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGet(void) -{ - return CMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending CMU interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * This function does not clear event bits. - * - * @return - * Pending and enabled CMU interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in CMU_IEN and - * - the pending interrupt flags CMU_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = CMU->IEN; - return CMU->IF & ien; -} - -/**************************************************************************//** - * @brief - * Set one or more pending CMU interrupts. - * - * @param[in] flags - * CMU interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void CMU_IntSet(uint32_t flags) -{ - CMU->IFS = flags; -} - -/***************************************************************************//** - * @brief - * Lock the CMU to protect some of its registers against unintended - * modification. - * - * @details - * See the reference manual for CMU registers that will be - * locked. - * - * @note - * If locking the CMU registers, they must be unlocked prior to using any - * CMU API functions modifying CMU registers protected by the lock. - ******************************************************************************/ -__STATIC_INLINE void CMU_Lock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; -} - -/***************************************************************************//** - * @brief - * Unlock the CMU so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void CMU_Unlock(void) -{ - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; -} - -#endif // defined(_SILICON_LABS_32B_SERIES_2) - -#if !defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Convert prescaler divider to a logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param[in] presc - * Prescaler value used to set the frequency divider. The divider is equal to - * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be - * equal to (divider - 1). - * - * @return - * Logarithm base 2 (binary) value, i.e. exponent as used by fixed - * 2^n prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) -{ - uint32_t log2; - - /* Integer prescalers take argument less than 32768. */ - EFM_ASSERT(presc < 32768U); - - /* Count leading zeroes and "reverse" result. Consider divider value to get - * exponent n from 2^n, so ('presc' +1). */ - log2 = 31UL - __CLZ(presc + (uint32_t) 1); - - /* Check that prescaler is a 2^n number. */ - EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); - - return log2; -} -#endif // !defined(_SILICON_LABS_32B_SERIES_0) - -/** @} (end addtogroup cmu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(CMU_PRESENT) */ -#endif /* EM_CMU_H */ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CMU_H +#define EM_CMU_H + +#include "em_device.h" +#if defined(CMU_PRESENT) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu_compat.h" +#include "em_gpio.h" +#include "sl_common.h" +#include "sl_enum.h" +#include "sl_status.h" +#include "sli_em_cmu.h" +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup cmu + * @{ + ******************************************************************************/ + +/** Macro to set clock sources in the clock tree. */ +#define CMU_CLOCK_SELECT_SET(clock, sel) CMU_##clock##_SELECT_##sel + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 0U +#define CMU_EN_BIT_MASK 0x1FU + +/* Enable register ID's for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CLKEN0_EN_REG 1 +#define CMU_CLKEN1_EN_REG 2 +#if defined(_CMU_CLKEN2_MASK) +#define CMU_CLKEN2_EN_REG 3 +#endif +#define CMU_CRYPTOACCCLKCTRL_EN_REG 3 +#define CMU_EN_REG_POS 5U +#define CMU_EN_REG_MASK 0x3U + +/* Clock branch ID's internal use. */ +#define CMU_CORE_BRANCH 0 +#define CMU_SYSCLK_BRANCH 1 +#define CMU_SYSTICK_BRANCH 2 +#define CMU_HCLK_BRANCH 3 +#define CMU_EXPCLK_BRANCH 4 +#define CMU_PCLK_BRANCH 5 +#define CMU_LSPCLK_BRANCH 6 +#define CMU_TRACECLK_BRANCH 7 +#define CMU_EM01GRPACLK_BRANCH 8 +#if defined(_CMU_EM01GRPBCLKCTRL_MASK) +#define CMU_EM01GRPBCLK_BRANCH 9 +#endif +#define CMU_EUART0CLK_BRANCH 10 +#define CMU_IADCCLK_BRANCH 11 +#define CMU_EM23GRPACLK_BRANCH 12 +#define CMU_WDOG0CLK_BRANCH 13 +#if defined(RTCC_PRESENT) +#define CMU_RTCCCLK_BRANCH 14 +#elif defined(SYSRTC_PRESENT) +#define CMU_SYSRTCCLK_BRANCH 14 +#endif +#define CMU_EM4GRPACLK_BRANCH 15 +#if defined(PDM_PRESENT) +#define CMU_PDMREF_BRANCH 16 +#endif +#define CMU_DPLLREFCLK_BRANCH 17 +#if WDOG_COUNT > 1 +#define CMU_WDOG1CLK_BRANCH 18 +#endif +#if defined(LCD_PRESENT) +#define CMU_LCD_BRANCH 19 +#endif +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_BRANCH 20 +#endif +#if defined(PCNT_PRESENT) +#define CMU_PCNT_BRANCH 21 +#endif +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHF_BRANCH 22 +#define CMU_LESENSE_BRANCH 23 +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_BRANCH 24 +#endif +#if defined(VDAC_PRESENT) && (VDAC_COUNT > 1) +#define CMU_VDAC1_BRANCH 25 +#endif +#define CMU_CLK_BRANCH_POS 7U +#define CMU_CLK_BRANCH_MASK 0x1FU +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_EMU_CMD_EM01VSCALE1_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL +#endif + +/* Macros for VSCALE for use with the @ref CMU_UpdateWaitStates() API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 1 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Disable clocks configuration */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPACLKCTRL */ +#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPACLKCTRL*/ +#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM01GRPBCLKCTRL */ +#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL*/ +#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM23GRPACLKCTRL */ +#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM23GRPACLKCTRL*/ +#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EM4GRPACLKCTRL */ +#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG0CLKCTRL */ +#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG0CLKCTRL */ +#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_WDOG1CLKCTRL */ +#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_WDOG1CLKCTRL */ +#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUSART0CLKCTRL */ +#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUSART0CLKCTRL*/ +#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL */ +#endif // (_SILICON_LABS_32B_SERIES_2) + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +/** HFRCODPLL frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCODPLLFreq_TypeDef, uint32_t) { + cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */ + cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */ + cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */ + cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */ + cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */ + cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + cmuHFRCODPLLFreq_100M0Hz = 100000000U, /**< 100MHz RC band. */ +#endif + cmuHFRCODPLLFreq_UserDefined = 0, +}; + +#if defined(USBPLL_PRESENT) +/** HFXO reference frequency */ +SL_ENUM_GENERIC(CMU_HFXORefFreq_TypeDef, uint32_t) { + cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (19UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38MHz input frequency. */ + cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (25UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 38.4MHz input frequency. */ + cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (16UL << _USBPLL_CTRL_DIVX_SHIFT) + | (13UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 39MHz input frequency. */ + cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) + | (24UL << _USBPLL_CTRL_DIVX_SHIFT) + | (20UL << _USBPLL_CTRL_DIVN_SHIFT), /**< 40MHz input frequency. */ +}; +#endif + +/** HFRCODPLL maximum frequency */ +#define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz +/** HFRCODPLL minimum frequency */ +#define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz + +#if defined(HFRCOEM23_PRESENT) +/** HFRCOEM23 frequency bands */ +SL_ENUM_GENERIC(CMU_HFRCOEM23Freq_TypeDef, uint32_t) { + cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */ + cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */ + cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */ + cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */ + cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */ + cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */ + cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */ + cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */ + cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */ + cmuHFRCOEM23Freq_UserDefined = 0, +}; + +/** HFRCOEM23 maximum frequency */ +#define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz +/** HFRCOEM23 minimum frequency */ +#define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz +#endif // defined(HFRCOEM23_PRESENT) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Clock points in CMU clock-tree. */ +SL_ENUM(CMU_Clock_TypeDef) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK, /**< System clock. */ + cmuClock_HCLK, /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK, /**< Export clock. */ + cmuClock_PCLK, /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */ + cmuClock_IADCCLK, /**< IADC clock. */ + cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */ + cmuClock_WDOG0CLK, /**< WDOG0 clock. */ + cmuClock_WDOG1CLK, /**< WDOG1 clock. */ + cmuClock_DPLLREFCLK, /**< DPLL reference clock. */ + cmuClock_TRACECLK, /**< Debug trace clock. */ + cmuClock_RTCCCLK, /**< RTCC clock. */ + cmuClock_HFRCOEM23, + + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_CORE, /**< Cortex-M33 core clock. */ + cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */ + cmuClock_ACMP0, /**< ACMP0 clock. */ + cmuClock_ACMP1, /**< ACMP1 clock. */ + cmuClock_BURTC, /**< BURTC clock. */ + cmuClock_GPCRC, /**< GPCRC clock. */ + cmuClock_GPIO, /**< GPIO clock. */ + cmuClock_I2C0, /**< I2C0 clock. */ + cmuClock_I2C1, /**< I2C1 clock. */ + cmuClock_IADC0, /**< IADC clock. */ + cmuClock_LDMA, /**< LDMA clock. */ + cmuClock_LETIMER0, /**< LETIMER clock. */ + cmuClock_PRS, /**< PRS clock. */ + cmuClock_RTCC, /**< RTCC clock. */ + cmuClock_TIMER0, /**< TIMER0 clock. */ + cmuClock_TIMER1, /**< TIMER1 clock. */ + cmuClock_TIMER2, /**< TIMER2 clock. */ + cmuClock_TIMER3, /**< TIMER3 clock. */ + cmuClock_USART0, /**< USART0 clock. */ + cmuClock_USART1, /**< USART1 clock. */ + cmuClock_USART2, /**< USART2 clock. */ + cmuClock_WDOG0, /**< WDOG0 clock. */ + cmuClock_WDOG1, /**< WDOG1 clock. */ + cmuClock_PDM /**< PDM clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/** Clock points in CMU clock-tree. */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* Clock branches */ + /*******************/ + + cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTEM clock. */ + cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSTICK clock. */ + cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Core and AHB bus interface clock. */ + cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Export clock. */ + cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Peripheral APB bus interface clock. */ + cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Low speed peripheral APB bus interface clock. */ + cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS), /**< Debug trace. */ + cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPA clock. */ +#if defined(PDM_PRESENT) + cmuClock_EM01GRPBCLK = (CMU_EM01GRPBCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPB clock. */ +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM01GRPC clock. */ +#endif +#if defined(EUART_PRESENT) + cmuClock_EUART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUART0 clock. */ +#elif defined(EUSART_PRESENT) + cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EUSART0 clock. */ +#endif + cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< IADC clock. */ + cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM23GRPA clock. */ + cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS), /**< WDOG1 clock. */ +#endif +#if defined(RTCC_PRESENT) + cmuClock_RTCCCLK = (CMU_RTCCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< RTCC clock. */ +#elif defined(SYSRTC_PRESENT) + cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< SYSRTC clock. */ +#endif + cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS), /**< EM4GRPA clock. */ + cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS), /**< DPLLREF clock. */ +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOAES = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOAES clock. */ + cmuClock_CRYPTOPK = (CMU_CRYPTOACCCLKCTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOPK clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCDCLK = (CMU_LCD_BRANCH << CMU_CLK_BRANCH_POS), /**< LCD clock. */ +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1CLK = (CMU_VDAC1_BRANCH << CMU_CLK_BRANCH_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS), /**< PCNT0 clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE high frequency clock. */ + cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS), /**< LESENSE low frequency clock. */ +#endif + + cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS), /**< Cortex-M33 core clock. */ +#if defined(PDM_PRESENT) + cmuClock_PDMREF = (CMU_PDMREF_BRANCH << CMU_CLK_BRANCH_POS), /**< PDMREF clock. */ +#endif + /*********************/ + /* Peripheral clocks */ + /*********************/ + + cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS), /**< LDMA clock. */ + cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS), /**< LDMAXBAR clock. */ +#if defined(RADIOAES_PRESENT) + cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS), /**< RADIOAES clock. */ +#endif + cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS), /**< GPCRC clock. */ + cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS), /**< TIMER0 clock. */ + cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS), /**< TIMER1 clock. */ + cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS), /**< TIMER2 clock. */ + cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS), /**< TIMER3 clock. */ +#if defined(_CMU_CLKEN2_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN1_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#elif defined(_CMU_CLKEN0_TIMER4_SHIFT) + cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS), /**< TIMER4 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN1_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#elif defined(_CMU_CLKEN0_TIMER5_SHIFT) + cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS), /**< TIMER5 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN1_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#elif defined(_CMU_CLKEN0_TIMER6_SHIFT) + cmuClock_TIMER6 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS), /**< TIMER6 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN1_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#elif defined(_CMU_CLKEN0_TIMER7_SHIFT) + cmuClock_TIMER7 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_TIMER7_SHIFT << CMU_EN_BIT_POS), /**< TIMER7 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER8_SHIFT) + cmuClock_TIMER8 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER8_SHIFT << CMU_EN_BIT_POS), /**< TIMER8 clock. */ +#endif +#if defined(_CMU_CLKEN2_TIMER9_SHIFT) + cmuClock_TIMER9 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_TIMER9_SHIFT << CMU_EN_BIT_POS), /**< TIMER9 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 0 + cmuClock_USART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART0_SHIFT << CMU_EN_BIT_POS), /**< USART0 clock. */ +#endif +#if defined(USART_PRESENT) && USART_COUNT > 1 +#if defined(_CMU_CLKEN0_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#elif defined(_CMU_CLKEN2_USART1_SHIFT) + cmuClock_USART1 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART1_SHIFT << CMU_EN_BIT_POS), /**< USART1 clock. */ +#endif +#endif /* defined(USART_PRESENT) && USART_COUNT > 1 */ +#if defined(USART_PRESENT) && USART_COUNT > 2 + cmuClock_USART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_USART2_SHIFT << CMU_EN_BIT_POS), /**< USART2 clock. */ +#endif /* defined(USART_PRESENT) && USART_COUNT > 2 */ +#if defined(IADC_PRESENT) + cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS), /**< IADC0 clock. */ +#endif + cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS), /**< AMUXCP0 clock. */ +#if defined(LETIMER_PRESENT) + cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS), /**< LETIMER0 clock. */ +#endif + cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS), /**< WDOG0 clock. */ +#if WDOG_COUNT > 1 + cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS), /**< WDOG1 clock. */ +#endif +#if defined(I2C_PRESENT) + cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS), /**< I2C0 clock. */ +#if I2C_COUNT > 1 + cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS), /**< I2C1 clock. */ +#endif /* I2C_COUNT > 1 */ +#if I2C_COUNT > 2 + cmuClock_I2C2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C2_SHIFT << CMU_EN_BIT_POS), /**< I2C2 clock. */ +#endif /* I2C_COUNT > 2 */ +#if I2C_COUNT > 3 + cmuClock_I2C3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_I2C3_SHIFT << CMU_EN_BIT_POS), /**< I2C3 clock. */ +#endif /* I2C_COUNT > 3 */ +#endif /* defined(I2C_PRESENT) */ + cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS), /**< SYSCFG clock. */ + cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS), /**< DPLL0 clock. */ + cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS), /**< HFRCO0 clock. */ +#if defined(HFRCOEM23_PRESENT) + cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS), /**< HFRCOEM23 clock. */ +#endif +#if defined(HFXO_PRESENT) + cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS), /**< HFXO clock. */ +#endif + cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS), /**< FSRCO clock. */ + cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS), /**< LFRCO clock. */ + cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS), /**< LFXO clock. */ + cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS), /**< ULFRCO clock. */ +#if defined(EUART_PRESENT) + cmuClock_EUART0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_EUART0_SHIFT << CMU_EN_BIT_POS), /**< EUART0 clock. */ +#endif +#if defined(PDM_PRESENT) + cmuClock_PDM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PDM_SHIFT << CMU_EN_BIT_POS), /**< PDM clock. */ +#endif + cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS), /**< GPIO clock. */ + cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS), /**< PRS clock. */ + cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS), /**< BURAM clock. */ + cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS), /**< BURTC clock. */ +#if defined(RTCC_PRESENT) + cmuClock_RTCC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS), /**< RTCC clock. */ +#endif + cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS), /**< DCDC clock. */ +#if defined(SYSRTC_PRESENT) + cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS), /**< SYSRTC clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS), /**< EUSART0 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS), /**< EUSART1 clock. */ +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#if defined(_CMU_CLKEN1_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#elif defined(_CMU_CLKEN2_EUSART2_SHIFT) + cmuClock_EUSART2 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART2_SHIFT << CMU_EN_BIT_POS), /**< EUSART2 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#if defined(_CMU_CLKEN1_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#elif defined(_CMU_CLKEN2_EUSART3_SHIFT) + cmuClock_EUSART3 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART3_SHIFT << CMU_EN_BIT_POS), /**< EUSART3 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#if defined(_CMU_CLKEN1_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#elif defined(_CMU_CLKEN2_EUSART4_SHIFT) + cmuClock_EUSART4 = (CMU_CLKEN2_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN2_EUSART4_SHIFT << CMU_EN_BIT_POS), /**< EUSART4 clock. */ +#endif +#endif /* defined(EUSART_PRESENT) && EUSART_COUNT > 4 */ +#if defined(_CMU_CLKEN1_IFADCDEBUG_SHIFT) + cmuClock_IFADCDEBUG = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_IFADCDEBUG_SHIFT << CMU_EN_BIT_POS), /**< IFADCDEBUG clock. */ +#endif +#if defined(CRYPTOACC_PRESENT) + cmuClock_CRYPTOACC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_CRYPTOACC_SHIFT << CMU_EN_BIT_POS), /**< CRYPTOACC clock. */ +#endif +#if defined(SEMAILBOX_PRESENT) + cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS), /**< SEMAILBOX clock. */ +#endif + cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS), /**< SMU clock. */ +#if defined(ICACHE_PRESENT) + cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS), /**< ICACHE clock. */ +#endif +#if defined(LESENSE_PRESENT) + cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS), /**< LESENSE clock. */ +#endif +#if defined(ACMP_PRESENT) + cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS), /**< ACMP0 clock. */ +#if ACMP_COUNT > 1 + cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS), /**< ACMP1 clock. */ +#endif +#endif +#if defined(VDAC_PRESENT) + cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS), /**< VDAC0 clock. */ +#if (VDAC_COUNT > 1) + cmuClock_VDAC1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_VDAC1_SHIFT << CMU_EN_BIT_POS), /**< VDAC1 clock. */ +#endif +#endif +#if defined(PCNT_PRESENT) + cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS), /**< PCNT0 clock. */ +#endif +#if defined(DMEM_PRESENT) + cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS), /**< DMEM clock. */ +#endif +#if defined(KEYSCAN_PRESENT) + cmuClock_KEYSCAN = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_KEYSCAN_SHIFT << CMU_EN_BIT_POS), /**< KEYSCAN clock. */ +#endif +#if defined(LCD_PRESENT) + cmuClock_LCD = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_LCD_SHIFT << CMU_EN_BIT_POS), /**< LCD clock. */ +#endif +#if defined(MVP_PRESENT) + cmuClock_MVP = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MVP_SHIFT << CMU_EN_BIT_POS), /**< MVP clock. */ +#endif + cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS), /**< MSC clock. */ +#if defined(USB_PRESENT) + cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS), /**< USB clock. */ +#endif +#if defined(ETAMPDET_PRESENT) + cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS), /**< ETAMPDET clock. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS) /**< RFFPLL clock. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low frequency RC oscillator. */ + cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuOsc_HFXO, /**< High frequency crystal oscillator. */ + cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */ +}; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS /**< PRS input as clock. */ +}; +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/** Selectable clock sources. */ +SL_ENUM_GENERIC(CMU_Select_TypeDef, uint32_t) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */ + cmuSelect_HFXO, /**< High frequency crystal oscillator. */ + cmuSelect_HFXORT, /**< Re-timed high frequency crystal oscillator. */ + cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */ + cmuSelect_HFRCODPLLRT, /**< Re-timed high frequency RC and DPLL oscillator. */ +#if defined(HFRCOEM23_PRESENT) + cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */ +#endif + cmuSelect_CLKIN0, /**< External clock input. */ + cmuSelect_LFXO, /**< Low frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low frequency RC oscillator. */ +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */ +#endif + cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */ + cmuSelect_HCLK, /**< Core and AHB bus interface clock. */ + cmuSelect_SYSCLK, /**< System clock. */ + cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */ + cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */ + cmuSelect_EM23GRPACLK, /**< EM23GRPA clock. */ +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */ +#endif + cmuSelect_EXPCLK, /**< Pin export clock. */ + cmuSelect_PRS, /**< PRS input as clock. */ +#if defined(PCNT_PRESENT) + cmuSelect_PCNTEXTCLK, /**< Pulse counter external source or PRS as clock. */ +#endif + cmuSelect_TEMPOSC, /**< Temperature oscillator. */ + cmuSelect_PFMOSC, /**< PFM oscillator. */ + cmuSelect_BIASOSC, /**< BIAS oscillator. */ +#if defined(USBPLL_PRESENT) + cmuSelect_USBPLL0, /**< PLL clock for USB. */ +#endif +#if defined(RFFPLL_PRESENT) + cmuSelect_RFFPLLSYS /**< Radio frequency friendly PLL system clock source. */ +#endif +}; +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/** DPLL reference clock edge detect selector. */ +SL_ENUM(CMU_DPLLEdgeSel_TypeDef) { + cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */ +}; + +/** LFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_LfxoOscMode_TypeDef, uint32_t) { + cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */ + cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */ +}; + +/** LFXO start-up timeout delay. */ +SL_ENUM_GENERIC(CMU_LfxoStartupDelay_TypeDef, uint32_t) { + cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */ + cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */ + cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */ + cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */ + cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */ + cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */ + cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */ + cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */ +}; + +/** HFXO oscillator modes. */ +SL_ENUM_GENERIC(CMU_HfxoOscMode_TypeDef, uint32_t) { + cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */ + cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */ +#if defined(_HFXO_CFG_MODE_EXTCLKPKDET) + cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */ +#endif +}; + +/** HFXO core bias LSB change timeout. */ +SL_ENUM_GENERIC(CMU_HfxoCbLsbTimeout_TypeDef, uint32_t) { + cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */ + cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */ + cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */ + cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */ + cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */ + cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */ + cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */ + cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */ + cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */ + cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */ + cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */ + cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */ + cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */ + cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */ + cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */ + cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */ +}; + +/** HFXO steady state timeout. */ +SL_ENUM_GENERIC(CMU_HfxoSteadyStateTimeout_TypeDef, uint32_t) { + cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */ + cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */ + cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */ + cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */ + cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */ + cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */ + cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */ + cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */ + cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */ + cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */ + cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */ + cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */ + cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */ + cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */ + cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */ +#if defined(_HFXO_XTALCFG_TIMEOUTSTEADY_T7500US) + cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */ +#endif +}; + +/** HFXO core degeneration control. */ +SL_ENUM_GENERIC(CMU_HfxoCoreDegen_TypeDef, uint32_t) { + cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */ + cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */ + cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */ + cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */ +}; + +/** HFXO XI and XO pin fixed capacitor control. */ +SL_ENUM_GENERIC(CMU_HfxoCtuneFixCap_TypeDef, uint32_t) { + cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */ + cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */ + cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */ + cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */ +}; + +/** Oscillator precision modes. */ +SL_ENUM(CMU_Precision_TypeDef) { + cmuPrecisionDefault, /**< Default precision mode. */ + cmuPrecisionHigh, /**< High precision mode. */ +}; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + uint8_t gain; /**< Startup gain. */ + uint8_t capTune; /**< Internal capacitance tuning. */ + CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */ + CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool highAmplitudeEn; /**< High amplitude enable. */ + bool agcEn; /**< AGC enable. */ + bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */ + bool failDetEn; /**< Oscillator failure detection enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Lock register access. */ +} CMU_LFXOInit_TypeDef; + +/** Default LFXO initialization values for XTAL mode. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + 1, \ + 38, \ + cmuLfxoStartupDelay_4KCycles, \ + cmuLfxoOscMode_Crystal, \ + false, /* highAmplitudeEn */ \ + true, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external clock mode. */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_External, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default LFXO initialization values for external sine mode. */ +#define CMU_LFXOINIT_EXTERNAL_SINE \ + { \ + 0U, \ + 0U, \ + cmuLfxoStartupDelay_2Cycles, \ + cmuLfxoOscMode_AcCoupledSine, \ + false, /* highAmplitudeEn */ \ + false, /* agcEn */ \ + false, /* failDetEM4WUEn */ \ + false, /* failDetEn */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { + CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */ + CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */ + uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */ + uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */ + uint8_t coreBiasStartup; /**< Core bias startup current. */ + uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */ + CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */ + CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */ + uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */ + uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */ + uint8_t coreBiasAna; /**< Core bias current. */ + bool enXiDcBiasAna; /**< Enable XI internal DC bias. */ + CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */ + bool forceXo2GndAna; /**< Force XO pin to ground. */ + bool forceXi2GndAna; /**< Force XI pin to ground. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ +#if defined(HFXO_CTRL_EM23ONDEMAND) + bool em23OnDemand; /**< Enable deep sleep. */ +#endif + bool regLock; /**< Lock register access. */ +} CMU_HFXOInit_TypeDef; + +#if defined(HFXO_CTRL_EM23ONDEMAND) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// See [PM-2871] for details. +/** Default configuration of fixed tuning capacitance on XI or XO for EFR32XG23 and EFR32XG28. */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)) \ + && defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM == 20) +// See [PM-5131] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG24 + * when high power PA is present and output dBm equal 20 dBm. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +// See [PM-5638] for details. +/** + * Default configuration of fixed tuning capacitance on XO for EFR32XG25 + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo +#else +/** + * Default configuration of fixed tuning capacitance on XO and XI. + */ +#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Both +#endif + +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false, /* em23OnDemand */ \ + false /* Lock registers */ \ + } +#else +/** Default HFXO initialization values for XTAL mode. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + cmuHfxoCbLsbTimeout_416us, \ + cmuHfxoSteadyStateTimeout_833us, /* First lock */ \ + cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 32U, /* coreBiasStartup */ \ + 32U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_Both, \ + _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \ + _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \ + 60U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna */ \ + cmuHfxoOscMode_Crystal, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode. */ +#define CMU_HFXOINIT_EXTERNAL_SINE \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSine, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } + +/** Default HFXO initialization values for external sine mode with peak detector. */ +#define CMU_HFXOINIT_EXTERNAL_SINEPKDET \ + { \ + (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \ + (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \ + 0U, /* ctuneXoStartup */ \ + 0U, /* ctuneXiStartup */ \ + 0U, /* coreBiasStartup */ \ + 0U, /* imCoreBiasStartup */ \ + cmuHfxoCoreDegen_None, \ + cmuHfxoCtuneFixCap_None, \ + 0U, /* ctuneXoAna */ \ + 0U, /* ctuneXiAna */ \ + 0U, /* coreBiasAna */ \ + false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \ + cmuHfxoOscMode_ExternalSinePkDet, \ + false, /* forceXo2GndAna */ \ + false, /* forceXi2GndAna (Never enable in sine mode) */ \ + false, /* DisOndemand */ \ + false, /* ForceEn */ \ + false /* Lock registers */ \ + } +#endif + +#if defined(_HFXO_BUFOUTCTRL_MASK) + +/** Crystal sharing timeout start up timeout. */ +SL_ENUM_GENERIC(CMU_BufoutTimeoutStartup_TypeDef, uint32_t) { + startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US, /**< Timeout set to 42 us. */ + startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US, /**< Timeout set to 83 us. */ + startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US, /**< Timeout set to 108 us. */ + startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US, /**< Timeout set to 133 us. */ + startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US, /**< Timeout set to 158 us. */ + startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US, /**< Timeout set to 183 us. */ + startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US, /**< Timeout set to 208 us. */ + startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US, /**< Timeout set to 233 us. */ + startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US, /**< Timeout set to 258 us. */ + startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US, /**< Timeout set to 283 us. */ + startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US, /**< Timeout set to 333 us. */ + startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US, /**< Timeout set to 375 us. */ + startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US, /**< Timeout set to 417 us. */ + startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US, /**< Timeout set to 458 us. */ + startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US, /**< Timeout set to 500 us. */ + startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US, /**< Timeout set to 667 us. */ +}; + +/** Crystal sharing leader initialization structure. */ +typedef struct { + bool minimalStartupDelay; /**< If enabled, bufout won't start until timeout expires. */ + CMU_BufoutTimeoutStartup_TypeDef timeoutStartup; /**< Wait duration of the oscillator startup sequence to prevent bufout starting too early. */ +} CMU_BUFOUTLeaderInit_TypeDef; + +/** Default crystal sharing master initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT \ + { \ + true, /* minimalStartupDelay */ \ + startupTimeout208Us, /* timeoutStartup */ \ + } +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/** PRS status select output signal. */ +SL_ENUM(CMU_PRS_Status_Output_Select_TypeDef) { + PRS_Status_select_0, /**< PRS status 0 output signal. */ + PRS_Status_select_1 /**< PRS status 1 output signal. */ +}; + +/** Crystal sharing follower initialization structure. */ +typedef struct { + CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput; /**< PRS status output select. */ + bool em23OnDemand; /**< Enable em23 on demand. */ + bool regLock; /**< Lock registers. */ +} CMU_CrystalSharingFollowerInit_TypeDef; + +/** Default crystal sharing follower initialization values. */ +#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT \ + { \ + PRS_Status_select_0, /* prsStatusSelectOutput */ \ + true, /* em23OnDemand */ \ + false /* regLock */ \ + } +#endif + +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 80 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + CMU_Select_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ + bool ditherEn; /**< Enable dither functionality. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + cmuSelect_LFXO, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 76,800,000 Hz using HFXO as reference + * clock, M = 1919, N = 3839 + */ +#define CMU_DPLL_HFXO_TO_76_8MHZ \ + { \ + 76800000, /* Target frequency. */ \ + 3839, /* Factor N. */ \ + 1919, /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * DPLL initialization values for 80,000,000 Hz using HFXO as reference + * clock, M = 1919, N = 3999. + */ +#define CMU_DPLL_HFXO_TO_80MHZ \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +/** + * Default configurations for DPLL initialization. When using this macro + * you need to modify the N and M factor and the desired frequency to match + * the components placed on the board. + */ +#define CMU_DPLLINIT_DEFAULT \ + { \ + 80000000, /* Target frequency. */ \ + (4000 - 1), /* Factor N. */ \ + (1920 - 1), /* Factor M. */ \ + cmuSelect_HFXO, /* Select HFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true, /* Enable automatic lock recovery. */ \ + false /* Don't enable dither function. */ \ + } + +#if defined(USBPLL_PRESENT) +/** USB PLL initialization structure. */ +typedef struct { + CMU_HFXORefFreq_TypeDef hfxoRefFreq; /**< HFXO reference frequency. */ + bool shuntRegEn; /**< Shunt regulator enable. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ +} CMU_USBPLL_Init_TypeDef; + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38 MHz. + */ +#define CMU_USBPLL_REFFREQ_38MHZ \ + { \ + cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 38.4 MHz. + */ +#define CMU_USBPLL_REFFREQ_38_4MHZ \ + { \ + cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 39 MHz. + */ +#define CMU_USBPLL_REFFREQ_39MHZ \ + { \ + cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } + +/** + * Default configurations for USB PLL initialization if the HFXO frequency is + * 40 MHz. + */ +#define CMU_USBPLL_REFFREQ_40MHZ \ + { \ + cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \ + false, /* Disable shunt regulator. */ \ + false, /* Disable PLL always on. */ \ + false, /* Force enable. */ \ + true /* Enable register lock. */ \ + } +#endif + +#if defined(RFFPLL_PRESENT) +/** + * RFF PLL initialization structure. + * When using this structure you need to modify the X, Y and N factor + * and the desired host target frequency to match the components placed + * on the board (namely the RFFPLL reference clock). + * X, Y, N values for a 39MHz HFXO: + * - Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY + * - Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2) + */ +typedef struct { + uint32_t frequency; /**< Host target frequency. */ + bool disOnDemand; /**< Disable on-demand requests. */ + bool forceEn; /**< Force oscillator enable. */ + bool regLock; /**< Enable register lock. */ + uint8_t dividerY; /**< Divider Y for digital. */ + uint8_t dividerX; /**< Divider X for Radio. */ + uint8_t dividerN; /**< Feedback divider N. */ +} CMU_RFFPLL_Init_TypeDef; + +/** Radio frequency locked loop default initialization values. */ +#define CMU_RFFPLL_DEFAULT \ + { \ + 100000000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + _RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \ + _RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \ + _RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \ + } + +/** Radio frequency locked loop initialization values for 97.5MHz. */ +#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ \ + { \ + 97500000UL, /* Host target frequency. */ \ + false, /* Disable on-demand requests. */ \ + false, /* Force enable. */ \ + true, /* Enable register lock. */ \ + 20U, /* Divider Y for digital. */ \ + 6U, /* Divider X for Radio. */ \ + 100U /* Feedback divider N. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, + CMU_Select_TypeDef reference); +void CMU_CalibrateConfig(uint32_t downCycles, + CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel); +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClkOutPinConfig(uint32_t clkno, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkdiv, + GPIO_Port_TypeDef port, + unsigned int pin); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, + CMU_ClkDiv_TypeDef div); +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +#endif +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, + CMU_Select_TypeDef ref); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void); +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq); +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#if defined(USBPLL_PRESENT) +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitUSBPLLLock(void); +#endif +#if defined(RFFPLL_PRESENT) +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit); +__STATIC_INLINE void CMU_WaitRFFPLLLock(void); +#endif +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); +#if defined(HFXO0_BUFOUT) +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin); +#endif +sl_status_t CMU_HFXOCTuneSet(uint32_t ctune); +uint32_t CMU_HFXOCTuneGet(void); +void CMU_HFXOCTuneDeltaSet(int32_t delta); +int32_t CMU_HFXOCTuneDeltaGet(void); +void CMU_HFXOCoreBiasCurrentCalibrate(void); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); +#if defined(PLFRCO_PRESENT) +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision); +#endif +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, + uint32_t val); +void CMU_UpdateWaitStates(uint32_t freq, int vscale); +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); + +#if defined(HFRCOEM23_PRESENT) +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void); +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +__STATIC_INLINE void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + (void)clock; + (void)enable; +} +#endif + +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after @ref CMU_CalibrateConfig() and possibly + * @ref CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTART; +} + +/***************************************************************************//** + * @brief + * Stop calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CALCMD = CMU_CALCMD_CALSTOP; +} + +/***************************************************************************//** + * @brief + * Unlock the DPLL. + * @note + * The HFRCODPLL oscillator is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while ((DPLL0->EN & DPLL_EN_DISABLING) != 0U) { + } +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupt flags. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupt sources. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to + * enabling if such a pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupt sources. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupt sources. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Lock CMU register access in order to protect registers contents against + * unintended modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = ~CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * This is a dummy function to solve backward compatibility issues. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +__STATIC_INLINE void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, + bool enable, + bool wait) +{ + (void)osc; + (void)enable; + (void)wait; +} + +/***************************************************************************//** + * @brief + * Unlock CMU register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Lock WDOG register access in order to protect registers contents against + * unintended modification. + * + * @note + * If locking the WDOG registers, they must be unlocked prior to using any + * emlib API functions modifying registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogLock(void) +{ + CMU->WDOGLOCK = ~CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Unlock WDOG register access so that writing to registers is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_WdogUnlock(void) +{ + CMU->WDOGLOCK = CMU_WDOGLOCK_LOCKKEY_UNLOCK; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for USB PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitUSBPLLLock() +{ + while ((USBPLL0->STATUS & (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) + != (USBPLL_STATUS_PLLRDY | USBPLL_STATUS_PLLLOCK)) { + /* Wait for USB PLL lock and ready */ + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Wait for RFF PLL lock and ready. + ******************************************************************************/ +__STATIC_INLINE void CMU_WaitRFFPLLLock() +{ + while ((RFFPLL0->STATUS & (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) + != (RFFPLL_STATUS_RFFPLLRADIORDY | RFFPLL_STATUS_RFFPLLSYSRDY)) { + /* Wait for RFF PLL lock and ready. */ + } +} +#endif + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Select register IDs for internal use. */ +#define CMU_NOSEL_REG 0 +#define CMU_HFCLKSEL_REG 1 +#define CMU_LFACLKSEL_REG 2 +#define CMU_LFBCLKSEL_REG 3 +#define CMU_LFCCLKSEL_REG 4 +#define CMU_LFECLKSEL_REG 5 +#define CMU_DBGCLKSEL_REG 6 +#define CMU_USBCCLKSEL_REG 7 +#define CMU_ADC0ASYNCSEL_REG 8 +#define CMU_ADC1ASYNCSEL_REG 9 +#define CMU_SDIOREFSEL_REG 10 +#define CMU_QSPI0REFSEL_REG 11 +#define CMU_USBRCLKSEL_REG 12 +#define CMU_PDMREFSEL_REG 13 + +#define CMU_SEL_REG_POS 0U +#define CMU_SEL_REG_MASK 0xfU + +/* Divisor/prescaler register IDs for internal use. */ +#define CMU_NODIV_REG 0 +#define CMU_NOPRESC_REG 0 +#define CMU_HFPRESC_REG 1 +#define CMU_HFCLKDIV_REG 1 +#define CMU_HFEXPPRESC_REG 2 +#define CMU_HFCLKLEPRESC_REG 3 +#define CMU_HFPERPRESC_REG 4 +#define CMU_HFPERCLKDIV_REG 4 +#define CMU_HFPERPRESCB_REG 5 +#define CMU_HFPERPRESCC_REG 6 +#define CMU_HFCOREPRESC_REG 7 +#define CMU_HFCORECLKDIV_REG 7 +#define CMU_LFAPRESC0_REG 8 +#define CMU_LFBPRESC0_REG 9 +#define CMU_LFEPRESC0_REG 10 +#define CMU_ADCASYNCDIV_REG 11 +#define CMU_HFBUSPRESC_REG 12 +#define CMU_HFCORECLKLEDIV_REG 13 + +#define CMU_PRESC_REG_POS 4U +#define CMU_DIV_REG_POS CMU_PRESC_REG_POS +#define CMU_PRESC_REG_MASK 0xfU +#define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK + +/* Enable register IDs for internal use. */ +#define CMU_NO_EN_REG 0 +#define CMU_CTRL_EN_REG 1 +#define CMU_HFPERCLKDIV_EN_REG 1 +#define CMU_HFPERCLKEN0_EN_REG 2 +#define CMU_HFCORECLKEN0_EN_REG 3 +#define CMU_PDMREF_EN_REG 4 +#define CMU_HFBUSCLKEN0_EN_REG 5 +#define CMU_LFACLKEN0_EN_REG 6 +#define CMU_LFBCLKEN0_EN_REG 7 +#define CMU_LFCCLKEN0_EN_REG 8 +#define CMU_LFECLKEN0_EN_REG 9 +#define CMU_PCNT_EN_REG 10 +#define CMU_SDIOREF_EN_REG 11 +#define CMU_QSPI0REF_EN_REG 12 +#define CMU_QSPI1REF_EN_REG 13 +#define CMU_HFPERCLKEN1_EN_REG 14 +#define CMU_USBRCLK_EN_REG 15 + +#define CMU_EN_REG_POS 8U +#define CMU_EN_REG_MASK 0xfU + +/* Enable register bit positions, for internal use. */ +#define CMU_EN_BIT_POS 12U +#define CMU_EN_BIT_MASK 0x1fU + +/* Clock branch bitfield positions, for internal use. */ +#define CMU_HF_CLK_BRANCH 0 +#define CMU_HFCORE_CLK_BRANCH 1 +#define CMU_HFPER_CLK_BRANCH 2 +#define CMU_HFPERB_CLK_BRANCH 3 +#define CMU_HFPERC_CLK_BRANCH 4 +#define CMU_HFBUS_CLK_BRANCH 5 +#define CMU_HFEXP_CLK_BRANCH 6 +#define CMU_DBG_CLK_BRANCH 7 +#define CMU_AUX_CLK_BRANCH 8 +#define CMU_RTC_CLK_BRANCH 9 +#define CMU_RTCC_CLK_BRANCH 10 +#define CMU_LETIMER0_CLK_BRANCH 11 +#define CMU_LETIMER1_CLK_BRANCH 12 +#define CMU_LEUART0_CLK_BRANCH 13 +#define CMU_LEUART1_CLK_BRANCH 14 +#define CMU_LFA_CLK_BRANCH 15 +#define CMU_LFB_CLK_BRANCH 16 +#define CMU_LFC_CLK_BRANCH 17 +#define CMU_LFE_CLK_BRANCH 18 +#define CMU_USBC_CLK_BRANCH 19 +#define CMU_USBLE_CLK_BRANCH 20 +#define CMU_LCDPRE_CLK_BRANCH 21 +#define CMU_LCD_CLK_BRANCH 22 +#define CMU_LESENSE_CLK_BRANCH 23 +#define CMU_CSEN_LF_CLK_BRANCH 24 +#define CMU_ADC0ASYNC_CLK_BRANCH 25 +#define CMU_ADC1ASYNC_CLK_BRANCH 26 +#define CMU_SDIOREF_CLK_BRANCH 27 +#define CMU_QSPI0REF_CLK_BRANCH 28 +#define CMU_USBR_CLK_BRANCH 29 +#define CMU_PDMREF_CLK_BRANCH 30 +#define CMU_HFLE_CLK_BRANCH 31 + +#define CMU_CLK_BRANCH_POS 17U +#define CMU_CLK_BRANCH_MASK 0x1fU + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +/* Maximum clock frequency for VSCALE voltages. */ +#define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 20000000UL +#endif + +/* Macros for VSCALE for use with the CMU_UpdateWaitStates(freq, vscale) API. + * NOTE: The values must align with the values in EMU_VScaleEM01_TypeDef for + * Series1 parts (highest VSCALE voltage = lowest numerical value). */ +#define VSCALE_EM01_LOW_POWER 2 +#define VSCALE_EM01_HIGH_PERFORMANCE 0 + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define USBC_CLOCK_PRESENT +#endif +#if defined(USB_PRESENT) && defined(_CMU_USBCTRL_MASK) +#define USBR_CLOCK_PRESENT +#endif +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define PLFRCO_PRESENT +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock divisors. These values are valid for prescalers. */ +#define cmuClkDiv_1 1 /**< Divide clock by 1. */ +#define cmuClkDiv_2 2 /**< Divide clock by 2. */ +#define cmuClkDiv_4 4 /**< Divide clock by 4. */ +#define cmuClkDiv_8 8 /**< Divide clock by 8. */ +#define cmuClkDiv_16 16 /**< Divide clock by 16. */ +#define cmuClkDiv_32 32 /**< Divide clock by 32. */ +#define cmuClkDiv_64 64 /**< Divide clock by 64. */ +#define cmuClkDiv_128 128 /**< Divide clock by 128. */ +#define cmuClkDiv_256 256 /**< Divide clock by 256. */ +#define cmuClkDiv_512 512 /**< Divide clock by 512. */ +#define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */ +#define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */ +#define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */ +#define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */ +#define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */ +#define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */ + +/** Clock divider configuration */ +typedef uint32_t CMU_ClkDiv_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) +/** Clockprescaler configuration */ +typedef uint32_t CMU_ClkPresc_TypeDef; +#endif + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOBand_TypeDef, uint32_t) { + cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ, /**< 1 MHz HFRCO band */ + cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ, /**< 7 MHz HFRCO band */ + cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ, /**< 11 MHz HFRCO band */ + cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ, /**< 14 MHz HFRCO band */ + cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ, /**< 21 MHz HFRCO band */ +#if defined(CMU_HFRCOCTRL_BAND_28MHZ) + cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ, /**< 28 MHz HFRCO band */ +#endif +}; +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOBand_TypeDef, uint32_t) { + cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ, /**< 1 MHz RC band */ + cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ, /**< 7 MHz RC band */ + cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ, /**< 11 MHz RC band */ + cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ, /**< 14 MHz RC band */ + cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ, /**< 21 MHz RC band */ +#if defined(CMU_AUXHFRCOCTRL_BAND_28MHZ) + cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ, /**< 28 MHz RC band */ +#endif +}; +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/** Universal serial high-frequency RC bands */ +SL_ENUM_GENERIC(CMU_USHFRCOBand_TypeDef, uint32_t) { + /** 24 MHz RC band. */ + cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ, + /** 48 MHz RC band. */ + cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ, +}; +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/** High-USHFRCO bands */ +SL_ENUM_GENERIC(CMU_USHFRCOFreq_TypeDef, uint32_t) { + cmuUSHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuUSHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuUSHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ + cmuUSHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ + cmuUSHFRCOFreq_UserDefined = 0, +}; +/** USHFRCO minimum frequency */ +#define CMU_USHFRCO_MIN cmuUSHFRCOFreq_16M0Hz +/** USHFRCO maximum frequency */ +#define CMU_USHFRCO_MAX cmuUSHFRCOFreq_50M0Hz +#endif + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/** High-frequency system RCO bands */ +SL_ENUM_GENERIC(CMU_HFRCOFreq_TypeDef, uint32_t) { + cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_HFRCOCAL13_MASK) + cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL14_MASK) + cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL15_MASK) + cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64 MHz RC band */ +#endif +#if defined(_DEVINFO_HFRCOCAL16_MASK) + cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72 MHz RC band */ +#endif + cmuHFRCOFreq_UserDefined = 0, +}; + +/** HFRCO minimum frequency. */ +#define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz +#if defined(_DEVINFO_HFRCOCAL16_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz +#elif defined(_DEVINFO_HFRCOCAL15_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_64M0Hz +#elif defined(_DEVINFO_HFRCOCAL14_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_56M0Hz +#elif defined(_DEVINFO_HFRCOCAL13_MASK) +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_48M0Hz +#else +/** HFRCO maximum frequency. */ +#define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz +#endif +#endif + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/** AUX high-frequency RCO bands */ +SL_ENUM_GENERIC(CMU_AUXHFRCOFreq_TypeDef, uint32_t) { + cmuAUXHFRCOFreq_1M0Hz = 1000000U, /**< 1 MHz RC band */ + cmuAUXHFRCOFreq_2M0Hz = 2000000U, /**< 2 MHz RC band */ + cmuAUXHFRCOFreq_4M0Hz = 4000000U, /**< 4 MHz RC band */ + cmuAUXHFRCOFreq_7M0Hz = 7000000U, /**< 7 MHz RC band */ + cmuAUXHFRCOFreq_13M0Hz = 13000000U, /**< 13 MHz RC band */ + cmuAUXHFRCOFreq_16M0Hz = 16000000U, /**< 16 MHz RC band */ + cmuAUXHFRCOFreq_19M0Hz = 19000000U, /**< 19 MHz RC band */ + cmuAUXHFRCOFreq_26M0Hz = 26000000U, /**< 26 MHz RC band */ + cmuAUXHFRCOFreq_32M0Hz = 32000000U, /**< 32 MHz RC band */ + cmuAUXHFRCOFreq_38M0Hz = 38000000U, /**< 38 MHz RC band */ +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + cmuAUXHFRCOFreq_48M0Hz = 48000000U, /**< 48 MHz RC band */ +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + cmuAUXHFRCOFreq_50M0Hz = 50000000U, /**< 50 MHz RC band */ +#endif + cmuAUXHFRCOFreq_UserDefined = 0, +}; +/** AUXHFRCO minimum frequency. */ +#define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_50M0Hz +#elif defined(_DEVINFO_AUXHFRCOCAL13_MASK) +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_48M0Hz +#else +/** AUXHFRCO maximum frequency. */ +#define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz +#endif +#endif + +/** Clock points in CMU. See CMU overview in the reference manual. */ +SL_ENUM_GENERIC(CMU_Clock_TypeDef, uint32_t) { + /*******************/ + /* HF clock branch */ + /*******************/ + + /** High-frequency clock */ +#if defined(_CMU_CTRL_HFCLKDIV_MASK) \ + || defined(_CMU_HFPRESC_MASK) + cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Debug clock */ + cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** AUX clock */ + cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(_CMU_HFEXPPRESC_MASK) + /**********************/ + /* HF export sub-branch */ + /**********************/ + + /** Export clock */ + cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) +/**********************************/ +/* HF bus clock sub-branch */ +/**********************************/ + + /** High-frequency bus clock */ +#if defined(_CMU_HFBUSPRESC_MASK) + cmuClock_BUS = (CMU_HFBUSPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO) + /** Cryptography accelerator clock */ + cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO0) + /** Cryptography accelerator 0 clock */ + cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_CRYPTO1) + /** Cryptography accelerator 1 clock */ + cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_LDMA) + /** Direct-memory access controller clock */ + cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_QSPI0) + /** Quad SPI clock */ + cmuClock_QSPI0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_QSPI0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPCRC) + /** General-purpose cyclic redundancy checksum clock */ + cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFBUSCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /** Low-energy clock divided down from HFCLK */ + cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFBUSCLKEN0_PRS) + /** Peripheral reflex system clock */ + cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* HF peripheral clock sub-branch */ + /**********************************/ + + /** High-frequency peripheral clock */ +#if defined(_CMU_HFPRESC_MASK) + cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#else + cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCB_MASK) + /** Branch B figh-frequency peripheral clock */ + cmuClock_HFPERB = (CMU_HFPERPRESCB_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + /** Branch C figh-frequency peripheral clock */ + cmuClock_HFPERC = (CMU_HFPERPRESCC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) + | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PDM) + /** PDM clock */ + cmuClock_PDM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PDM_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF0) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USARTRF1) + /** Universal sync/async receiver/transmitter 0 clock */ + cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART1) + /** Universal sync/async receiver/transmitter 1 clock */ + cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART2) + /** Universal sync/async receiver/transmitter 2 clock */ + cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_USART3) + /** Universal sync/async receiver/transmitter 3 clock */ + cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART4) + /** Universal sync/async receiver/transmitter 4 clock */ + cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_USART5) + /** Universal sync/async receiver/transmitter 5 clock */ + cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART0) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART0_MASK) + /** Universal async receiver/transmitter 0 clock */ + cmuClock_UART0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_UART1) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFPERCLKEN1_UART1_MASK) + /** Universal async receiver/transmitter 1 clock */ + cmuClock_UART1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_UART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER0) + /** Timer 0 clock */ + cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCB_MASK) + | (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER1) + /** Timer 1 clock */ + cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER2) + /** Timer 2 clock */ + cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER3) + /** Timer 3 clock */ + cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER4) + /** Timer 4 clock */ + cmuClock_TIMER4 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER5) + /** Timer 5 clock */ + cmuClock_TIMER5 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TIMER6) + /** Timer 6 clock */ + cmuClock_TIMER6 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TIMER6_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER0) + /** Wide-timer 0 clock */ + cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_WTIMER1) + /** Wide-timer 1 clock */ + cmuClock_WTIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER2) + /** Wide-timer 2 clock */ + cmuClock_WTIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN1_WTIMER3) + /** Wide-timer 3 clock */ + cmuClock_WTIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_WTIMER3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CRYOTIMER) + /** CRYOtimer clock */ + cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP0) + /** Analog comparator 0 clock */ + cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP1) + /** Analog comparator 1 clock */ + cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP2) + /** Analog comparator 2 clock */ + cmuClock_ACMP2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ACMP3) + /** Analog comparator 3 clock */ + cmuClock_ACMP3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ACMP3_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_PRS) + /** Peripheral-reflex system clock */ + cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_DAC0) + /** Digital-to-analog converter 0 clock */ + cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_VDAC0) + /** Voltage digital-to-analog converter 0 clock */ + cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_IDAC0) + /** Current digital-to-analog converter 0 clock */ + cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_GPIO) + /** General-purpose input/output clock */ + cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_VCMP) + /** Voltage comparator clock */ + cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_ADC0) + /** Analog-to-digital converter 0 clock */ + cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_ADC1) + /** Analog-to-digital converter 1 clock */ + cmuClock_ADC1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_ADC1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_I2C0) + /** I2C 0 clock */ + cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C1) + /** I2C 1 clock */ + cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) + #if defined(_CMU_HFPERPRESCC_MASK) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #else + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), + #endif +#endif + +#if defined(CMU_HFPERCLKEN0_I2C2) + /** I2C 2 clock */ + cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFPERCLKEN1_CSEN) + /** Capacitive Sense HF clock */ + cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFPERCLKEN0_TRNG0) + /** True random number generator clock */ + cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN0_MASK) + /** Controller Area Network 0 clock */ + cmuClock_CAN0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN0_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFPERCLKEN1_CAN1_MASK) + /** Controller Area Network 1 clock. */ + cmuClock_CAN1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFPERCLKEN1_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFPERCLKEN1_CAN1_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /**********************/ + /* HF core sub-branch */ + /**********************/ + + /** Core clock */ + cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_HFCORECLKEN0_AES) + /** Advanced encryption standard accelerator clock */ + cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_DMA) + /** Direct memory access controller clock */ + cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_LE) + /** Low-energy clock divided down from HFCORECLK */ + cmuClock_HFLE = (CMU_HFCORECLKLEDIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_EBI) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(_CMU_HFBUSCLKEN0_EBI_MASK) + /** External bus interface clock */ + cmuClock_EBI = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_ETH_MASK) + /** Ethernet clock */ + cmuClock_ETH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_ETH_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_HFBUSCLKEN0_SDIO_MASK) + /** SDIO clock */ + cmuClock_SDIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_SDIO_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(USBC_CLOCK_PRESENT) + /** USB Core clock */ + cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined (USBR_CLOCK_PRESENT) + /** USB Rate clock */ + cmuClock_USBR = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_USBRCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_USBRCLK_EN_REG << CMU_EN_REG_POS) + | (_CMU_USBCTRL_USBCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_HFCORECLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_HFBUSCLKEN0_USB) + /** USB clock */ + cmuClock_USB = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_HFBUSCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF A branch */ + /***************/ + + /** Low-frequency A clock */ + cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFACLKEN0_RTC) + /** Real time counter clock */ + cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER0) + /** Low-energy timer 0 clock */ + cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LETIMER1) + /** Low-energy timer 1 clock */ + cmuClock_LETIMER1 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LETIMER1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFACLKEN0_LCD) + /** Liquid crystal display, pre FDIV clock */ + cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Liquid crystal display clock. Note that FDIV prescaler + * must be set by special API. */ + cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) + | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT0CLKEN) + /** Pulse counter 0 clock */ + cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT1CLKEN) + /** Pulse counter 1 clock */ + cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_PCNTCTRL_PCNT2CLKEN) + /** Pulse counter 2 clock */ + cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) + | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#if defined(CMU_LFACLKEN0_LESENSE) + /** LESENSE clock */ + cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) + | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + + /***************/ + /* LF B branch */ + /***************/ + + /** Low-frequency B clock */ + cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFBCLKEN0_LEUART0) + /** Low-energy universal asynchronous receiver/transmitter 0 clock */ + cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_CSEN) + /** Capacitive Sense LF clock */ + cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_LEUART1) + /** Low-energy universal asynchronous receiver/transmitter 1 clock */ + cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(CMU_LFBCLKEN0_SYSTICK) + /** Cortex SYSTICK LF clock */ + cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) + | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_LFCCLKEN0_MASK) + /***************/ + /* LF C branch */ + /***************/ + + /** Low-frequency C clock */ + cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS), + +#if defined(CMU_LFCCLKEN0_USBLE) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#elif defined(CMU_LFCCLKEN0_USB) + /** USB LE clock */ + cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFCCLKEN0_USB_SHIFT << CMU_EN_BIT_POS) + | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + /***************/ + /* LF E branch */ + /***************/ + + /** Low-frequency E clock */ + cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) + | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS), + + /** Real-time counter and calendar clock */ +#if defined (CMU_LFECLKEN0_RTCC) + cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) + | (CMU_NOSEL_REG << CMU_SEL_REG_POS) + | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) + | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) + | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +#endif + + /**********************************/ + /* Asynchronous peripheral clocks */ + /**********************************/ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + /** ADC0 asynchronous clock */ + cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + /** ADC1 asynchronous clock */ + cmuClock_ADC1ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) + | (CMU_ADC1ASYNCSEL_REG << CMU_SEL_REG_POS) + | (CMU_NO_EN_REG << CMU_EN_REG_POS) + | (0 << CMU_EN_BIT_POS) + | (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKDIS_MASK) + /** SDIO reference clock */ + cmuClock_SDIOREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_SDIOREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_SDIOREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_SDIOCTRL_SDIOCLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKDIS_MASK) + /** QSPI0 reference clock */ + cmuClock_QSPI0REF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_QSPI0REFSEL_REG << CMU_SEL_REG_POS) + | (CMU_QSPI0REF_EN_REG << CMU_EN_REG_POS) + | (_CMU_QSPICTRL_QSPI0CLKDIS_SHIFT << CMU_EN_BIT_POS) + | (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKEN_MASK) + /** PDM reference clock */ + cmuClock_PDMREF = (CMU_NODIV_REG << CMU_DIV_REG_POS) + | (CMU_PDMREFSEL_REG << CMU_SEL_REG_POS) + | (CMU_PDMREF_EN_REG << CMU_EN_REG_POS) + | (_CMU_PDMCTRL_PDMCLKEN_SHIFT << CMU_EN_BIT_POS) + | (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS), +#endif +}; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Clock_TypeDef member */ +#define cmuClock_CORELE cmuClock_HFLE +/** @endcond */ + +/** Oscillator types. */ +SL_ENUM(CMU_Osc_TypeDef) { + cmuOsc_LFXO, /**< Low-frequency crystal oscillator. */ + cmuOsc_LFRCO, /**< Low-frequency RC oscillator. */ + cmuOsc_HFXO, /**< High-frequency crystal oscillator. */ + cmuOsc_HFRCO, /**< High-frequency RC oscillator. */ + cmuOsc_AUXHFRCO, /**< Auxiliary high-frequency RC oscillator. */ +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + cmuOsc_USHFRCO, /**< Universal serial high-frequency RC oscillator */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuOsc_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuOsc_CLKIN0, /**< External oscillator. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuOsc_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +/** Oscillator modes. */ +SL_ENUM(CMU_OscMode_TypeDef) { + cmuOscMode_Crystal, /**< Crystal oscillator. */ + cmuOscMode_AcCoupled, /**< AC-coupled buffer. */ + cmuOscMode_External, /**< External digital clock. */ +}; + +/** Selectable clock sources. */ +SL_ENUM(CMU_Select_TypeDef) { + cmuSelect_Error, /**< Usage error. */ + cmuSelect_Disabled, /**< Clock selector disabled. */ + cmuSelect_LFXO, /**< Low-frequency crystal oscillator. */ + cmuSelect_LFRCO, /**< Low-frequency RC oscillator. */ + cmuSelect_HFXO, /**< High-frequency crystal oscillator. */ + cmuSelect_HFRCO, /**< High-frequency RC oscillator. */ + cmuSelect_HFCLKLE, /**< High-frequency LE clock divided by 2 or 4. */ + cmuSelect_AUXHFRCO, /**< Auxiliary clock source can be used for debug clock. */ + cmuSelect_HFSRCCLK, /**< High-frequency source clock. */ + cmuSelect_HFCLK, /**< Divided HFCLK on Giant for debug clock, undivided on + Tiny Gecko and for USBC (not used on Gecko). */ +#if defined(CMU_STATUS_USHFRCOENS) + cmuSelect_USHFRCO, /**< Universal serial high-frequency RC oscillator. */ +#endif +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + cmuSelect_USHFRCODIV2, /**< Universal serial high-frequency RC oscillator / 2. */ +#endif +#if defined(CMU_HFXOCTRL_HFXOX2EN) + cmuSelect_HFXOX2, /**< High-frequency crystal oscillator x 2. */ +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + cmuSelect_ULFRCO, /**< Ultra low-frequency RC oscillator. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + cmuSelect_HFRCODIV2, /**< High-frequency RC oscillator divided by 2. */ +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + cmuSelect_CLKIN0, /**< External clock input. */ +#endif +#if defined(PLFRCO_PRESENT) + cmuSelect_PLFRCO, /**< Precision Low Frequency Oscillator. */ +#endif +}; + +#if defined(CMU_HFCORECLKEN0_LE) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated CMU_Select_TypeDef member */ +#define cmuSelect_CORELEDIV2 cmuSelect_HFCLKLE +/** @endcond */ +#endif + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/** HFXO tuning modes */ +SL_ENUM_GENERIC(CMU_HFXOTuningMode_TypeDef, uint32_t) { + cmuHFXOTuningMode_Auto = 0, + cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART, /**< Run peak detect optimization only. */ +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART, /**< Run shunt current optimization only. */ + cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART /**< Run peak and shunt current optimization. */ + | CMU_CMD_HFXOSHUNTOPTSTART, +#endif +}; +#endif + +#if defined(_CMU_CTRL_LFXOBOOST_MASK) +/** LFXO Boost values. */ +SL_ENUM(CMU_LFXOBoost_TypeDef) { + cmuLfxoBoost70 = 0x0, + cmuLfxoBoost100 = 0x2, +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + cmuLfxoBoost70Reduced = 0x1, + cmuLfxoBoost100Reduced = 0x3, +#endif +}; +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL reference clock selector. */ +SL_ENUM_GENERIC(CMU_DPLLClkSel_TypeDef, uint32_t) { + cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO, /**< HFXO is DPLL reference clock. */ + cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO, /**< LFXO is DPLL reference clock. */ + cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0 /**< CLKIN0 is DPLL reference clock. */ +}; + +/** DPLL reference clock edge detect selector. */ +SL_ENUM_GENERIC(CMU_DPLLEdgeSel_TypeDef, uint32_t) { + cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL, /**< Detect falling edge of reference clock. */ + cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE /**< Detect rising edge of reference clock. */ +}; + +/** DPLL lock mode selector. */ +SL_ENUM_GENERIC(CMU_DPLLLockMode_TypeDef, uint32_t) { + cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL, /**< Frequency lock mode. */ + cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL /**< Phase lock mode. */ +}; +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_CMU_LFXOCTRL_MASK) + uint8_t ctune; /**< CTUNE (load capacitance) value */ + uint8_t gain; /**< Gain/max startup margin */ +#else + CMU_LFXOBoost_TypeDef boost; /**< LFXO boost */ +#endif + uint8_t timeout; /**< Startup delay */ + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_LFXOInit_TypeDef; + +#if defined(_CMU_LFXOCTRL_MASK) +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + _CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \ + _CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \ + _CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* No CTUNE value needed */ \ + 0, /* No LFXO startup gain */ \ + _CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#else +/** Default LFXO initialization values. */ +#define CMU_LFXOINIT_DEFAULT \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Default LFXO initialization for external clock */ +#define CMU_LFXOINIT_EXTERNAL_CLOCK \ + { \ + cmuLfxoBoost70, \ + _CMU_CTRL_LFXOTIMEOUT_8CYCLES, \ + cmuOscMode_External, \ + } +#endif + +/** HFXO initialization structure. + * Initialization values should be obtained from a configuration tool, + * application note or crystal data sheet. */ +typedef struct { +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint16_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint16_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#elif defined(_CMU_HFXOCTRL_MASK) + bool lowPowerMode; /**< Enable low-power mode */ + bool autoStartEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoSelEm01; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + bool autoStartSelOnRacWakeup; /**< @deprecated Use @ref CMU_HFXOAutostartEnable instead. */ + uint16_t ctuneStartup; /**< Startup phase CTUNE (load capacitance) value */ + uint16_t ctuneSteadyState; /**< Steady-state phase CTUNE (load capacitance) value */ + uint8_t regIshSteadyState; /**< Shunt steady-state current */ + uint8_t xoCoreBiasTrimStartup; /**< Startup XO core bias current trim */ + uint8_t xoCoreBiasTrimSteadyState; /**< Steady-state XO core bias current trim */ + uint8_t thresholdPeakDetect; /**< Peak detection threshold */ + uint8_t timeoutShuntOptimization; /**< Timeout - shunt optimization */ + uint8_t timeoutPeakDetect; /**< Timeout - peak detection */ + uint8_t timeoutSteady; /**< Timeout - steady-state */ + uint8_t timeoutStartup; /**< Timeout - startup */ +#else + uint8_t boost; /**< HFXO Boost, 0=50% 1=70%, 2=80%, 3=100% */ + uint8_t timeout; /**< Startup delay */ + bool glitchDetector; /**< Enable/disable glitch detector */ +#endif + CMU_OscMode_TypeDef mode; /**< Oscillator mode */ +} CMU_HFXOInit_TypeDef; + +#if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) +/** Default HFXO init. */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_External, \ + } +#elif defined(_CMU_HFXOCTRL_MASK) +/** + * Default HFXO initialization values for Platform 2 devices, which contain a + * separate HFXOCTRL register. + */ +#if defined(_EFR_DEVICE) +#define CMU_HFXOINIT_DEFAULT \ + { \ + false, /* Low-noise mode for EFR32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default Shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state XO core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#else /* EFM32 device */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + true, /* Low-power mode for EFM32 */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \ + _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \ + 0xA, /* Default shunt steady-state current */ \ + 0x20, /* Matching errata fix in @ref CHIP_Init() */ \ + 0x7, /* Recommended steady-state osc core bias current */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0xA, /* Recommended peak detection timeout */ \ + 0x4, /* Recommended steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \ + cmuOscMode_Crystal, \ + } +#endif /* _EFR_DEVICE */ +/** Init of HFXO with external clock. */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + true, /* Low-power mode */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + false, /* @deprecated no longer in use */ \ + 0, /* Startup CTUNE=0 recommended for external clock */ \ + 0, /* Steady CTUNE=0 recommended for external clock */ \ + 0xA, /* Default shunt steady-state current */ \ + 0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \ + 0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \ + 0x6, /* Recommended peak detection threshold */ \ + 0x2, /* Recommended shunt optimization timeout */ \ + 0x0, /* Peak-detect not recommended for external clock usage */ \ + _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \ + _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \ + cmuOscMode_External, \ + } +#else /* _CMU_HFXOCTRL_MASK */ +/** + * Default HFXO initialization values for Platform 1 devices. + */ +#define CMU_HFXOINIT_DEFAULT \ + { \ + _CMU_CTRL_HFXOBOOST_DEFAULT, /* 100% HFXO boost */ \ + _CMU_CTRL_HFXOTIMEOUT_DEFAULT, /* 16 K startup delay */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_Crystal, /* Crystal oscillator */ \ + } +/** Default HFXO initialization for external clock */ +#define CMU_HFXOINIT_EXTERNAL_CLOCK \ + { \ + 0, /* Minimal HFXO boost, 50% */ \ + _CMU_CTRL_HFXOTIMEOUT_8CYCLES, /* Minimal startup delay, 8 cycles */ \ + false, /* Disable glitch detector */ \ + cmuOscMode_External, /* External digital clock */ \ + } +#endif /* _CMU_HFXOCTRL_MASK */ + +#if defined(CMU_OSCENCMD_DPLLEN) +/** DPLL initialization structure. + * Frequency will be Fref*(N+1)/(M+1). */ +typedef struct { + uint32_t frequency; /**< PLL frequency value, max 40 MHz. */ + uint16_t n; /**< Factor N. 300 <= N <= 4095 */ + uint16_t m; /**< Factor M. M <= 4095 */ + uint8_t ssInterval; /**< Spread spectrum update interval. */ + uint8_t ssAmplitude; /**< Spread spectrum amplitude. */ + CMU_DPLLClkSel_TypeDef refClk; /**< Reference clock selector. */ + CMU_DPLLEdgeSel_TypeDef edgeSel; /**< Reference clock edge detect selector. */ + CMU_DPLLLockMode_TypeDef lockMode; /**< DPLL lock mode selector. */ + bool autoRecover; /**< Enable automatic lock recovery. */ +} CMU_DPLLInit_TypeDef; + +/** + * DPLL initialization values for 39,998,805 Hz using LFXO as reference + * clock, M=2 and N=3661. + */ +#define CMU_DPLL_LFXO_TO_40MHZ \ + { \ + 39998805, /* Target frequency. */ \ + 3661, /* Factor N. */ \ + 2, /* Factor M. */ \ + 0, /* No spread spectrum clocking. */ \ + 0, /* No spread spectrum clocking. */ \ + cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \ + cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \ + cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \ + true /* Enable automatic lock recovery. */ \ + } +#endif // CMU_OSCENCMD_DPLLEN + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band); + +#elif defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void); +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq); +#endif + +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference); + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel); +#endif + +uint32_t CMU_CalibrateCountGet(void); +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable); +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock); +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div); +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock); + +#if defined(_SILICON_LABS_32B_SERIES_1) +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc); +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock); +#endif + +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref); +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock); +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock); +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock); + +#if defined(CMU_OSCENCMD_DPLLEN) +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init); +#endif +void CMU_FreezeEnable(bool enable); + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band); + +#elif defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void); +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq); +#endif + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +uint32_t CMU_HFRCOStartupDelayGet(void); +void CMU_HFRCOStartupDelaySet(uint32_t delay); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq); +uint32_t CMU_USHFRCOFreqGet(void); +#endif + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel); +#endif + +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit); + +uint32_t CMU_LCDClkFDIVGet(void); +void CMU_LCDClkFDIVSet(uint32_t div); +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit); +void CMU_LFXOPrecisionSet(uint16_t precision); +uint16_t CMU_LFXOPrecisionGet(void); +void CMU_HFXOPrecisionSet(uint16_t precision); +uint16_t CMU_HFXOPrecisionGet(void); + +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait); +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc); +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val); + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode); +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait); +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +void CMU_PCNTClockExternalSet(unsigned int instance, bool external); +bool CMU_PCNTClockExternalGet(unsigned int instance); +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void); +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band); +uint32_t CMU_USHFRCOFreqGet(void); +#endif +void CMU_UpdateWaitStates(uint32_t freq, int vscale); + +#if defined(CMU_CALCTRL_CONT) +/***************************************************************************//** + * @brief + * Configure continuous calibration mode. + * @param[in] enable + * If true, enables continuous calibration, if false disables continuous + * calibration. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateCont(bool enable) +{ + BUS_RegBitWrite(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT, (uint32_t)enable); +} +#endif + +/***************************************************************************//** + * @brief + * Start calibration. + * @note + * This call is usually invoked after CMU_CalibrateConfig() and possibly + * CMU_CalibrateCont(). + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStart(void) +{ + CMU->CMD = CMU_CMD_CALSTART; +} + +#if defined(CMU_CMD_CALSTOP) +/***************************************************************************//** + * @brief + * Stop the calibration counters. + ******************************************************************************/ +__STATIC_INLINE void CMU_CalibrateStop(void) +{ + CMU->CMD = CMU_CMD_CALSTOP; +} +#endif + +/***************************************************************************//** + * @brief + * Convert divider to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] div + * An unscaled divider. + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div) +{ + uint32_t log2; + + /* Fixed 2^n prescalers take argument of 32768 or less. */ + EFM_ASSERT((div > 0U) && (div <= 32768U)); + + /* Count leading zeroes and "reverse" result */ + log2 = 31UL - __CLZ(div); + + return log2; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/***************************************************************************//** + * @brief + * Unlock DPLL. + * @note + * HFRCO is not turned off. + ******************************************************************************/ +__STATIC_INLINE void CMU_DPLLUnlock(void) +{ + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; +} +#endif + +/***************************************************************************//** + * @brief + * Clear one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntClear(uint32_t flags) +{ + CMU->IFC = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntDisable(uint32_t flags) +{ + CMU->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more CMU interrupts. + * + * @note + * Depending on use case, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using @ref CMU_IntClear() prior to enabling + * if the pending interrupt should be ignored. + * + * @param[in] flags + * CMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void CMU_IntEnable(uint32_t flags) +{ + CMU->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending CMU interrupts. + * + * @return + * CMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGet(void) +{ + return CMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending CMU interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * This function does not clear event bits. + * + * @return + * Pending and enabled CMU interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in CMU_IEN and + * - the pending interrupt flags CMU_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = CMU->IEN; + return CMU->IF & ien; +} + +/**************************************************************************//** + * @brief + * Set one or more pending CMU interrupts. + * + * @param[in] flags + * CMU interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void CMU_IntSet(uint32_t flags) +{ + CMU->IFS = flags; +} + +/***************************************************************************//** + * @brief + * Lock the CMU to protect some of its registers against unintended + * modification. + * + * @details + * See the reference manual for CMU registers that will be + * locked. + * + * @note + * If locking the CMU registers, they must be unlocked prior to using any + * CMU API functions modifying CMU registers protected by the lock. + ******************************************************************************/ +__STATIC_INLINE void CMU_Lock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the CMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void CMU_Unlock(void) +{ + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; +} + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if !defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Convert prescaler divider to a logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param[in] presc + * Prescaler value used to set the frequency divider. The divider is equal to + * ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be + * equal to (divider - 1). + * + * @return + * Logarithm base 2 (binary) value, i.e. exponent as used by fixed + * 2^n prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc) +{ + uint32_t log2; + + /* Integer prescalers take argument less than 32768. */ + EFM_ASSERT(presc < 32768U); + + /* Count leading zeroes and "reverse" result. Consider divider value to get + * exponent n from 2^n, so ('presc' +1). */ + log2 = 31UL - __CLZ(presc + (uint32_t) 1); + + /* Check that prescaler is a 2^n number. */ + EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U)); + + return log2; +} +#endif // !defined(_SILICON_LABS_32B_SERIES_0) + +/** @} (end addtogroup cmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(CMU_PRESENT) */ +#endif /* EM_CMU_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h index 1585ec8..1c9c1ca 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_cmu_compat.h @@ -1,184 +1,184 @@ -/***************************************************************************//** - * @file - * @brief CMU Compatibility Header - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CMU_COMPAT_H -#define EM_CMU_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define CMU_IF_CALRDYIF CMU_IF_CALRDY -#define _CMU_IF_CALRDYIF_SHIFT _CMU_IF_CALRDY_SHIFT -#define _CMU_IF_CALRDYIF_MASK _CMU_IF_CALRDY_MASK -#define _CMU_IF_CALRDYIF_DEFAULT _CMU_IF_CALRDY_DEFAULT -#define CMU_IF_CALRDYIF_DEFAULT CMU_IF_CALRDY_DEFAULT - -#define CMU_IF_CALOFIF CMU_IF_CALOF -#define _CMU_IF_CALOFIF_SHIFT _CMU_IF_CALOF_SHIFT -#define _CMU_IF_CALOFIF_MASK _CMU_IF_CALOF_MASK -#define _CMU_IF_CALOFIF_DEFAULT _CMU_IF_CALOF_DEFAULT -#define CMU_IF_CALOFIF_DEFAULT CMU_IF_CALOF_DEFAULT - -#define CMU_IEN_CALRDYIEN CMU_IEN_CALRDY -#define _CMU_IEN_CALRDYIEN_SHIFT _CMU_IEN_CALRDY_SHIFT -#define _CMU_IEN_CALRDYIEN_MASK _CMU_IEN_CALRDY_MASK -#define _CMU_IEN_CALRDYIEN_DEFAULT _CMU_IEN_CALRDY_DEFAULT -#define CMU_IEN_CALRDYIEN_DEFAULT CMU_IEN_CALRDY_DEFAULT - -#define CMU_IEN_CALOFIEN CMU_IEN_CALOF -#define _CMU_IEN_CALOFIEN_SHIFT _CMU_IEN_CALOF_SHIFT -#define _CMU_IEN_CALOFIEN_MASK _CMU_IEN_CALOF_MASK -#define _CMU_IEN_CALOFIEN_DEFAULT _CMU_IEN_CALOF_DEFAULT -#define CMU_IEN_CALOFIEN_DEFAULT CMU_IEN_CALOF_DEFAULT - - -#define HFRCO_IF_RDYIF HFRCO_IF_RDY -#define _HFRCO_IF_RDYIF_SHIFT _HFRCO_IF_RDY_SHIFT -#define _HFRCO_IF_RDYIF_MASK _HFRCO_IF_RDY_MASK -#define _HFRCO_IF_RDYIF_DEFAULT _HFRCO_IF_RDY_DEFAULT -#define HFRCO_IF_RDYIF_DEFAULT HFRCO_IF_RDY_DEFAULT - -#define HFRCO_IEN_RDYIEN HFRCO_IEN_RDY -#define _HFRCO_IEN_RDYIEN_SHIFT _HFRCO_IEN_RDY_SHIFT -#define _HFRCO_IEN_RDYIEN_MASK _HFRCO_IEN_RDY_MASK -#define _HFRCO_IEN_RDYIEN_DEFAULT _HFRCO_IEN_RDY_DEFAULT -#define HFRCO_IEN_RDYIEN_DEFAULT HFRCO_IEN_RDY_DEFAULT - - -#define LFRCO_IF_RDYIF LFRCO_IF_RDY -#define _LFRCO_IF_RDYIF_SHIFT _LFRCO_IF_RDY_SHIFT -#define _LFRCO_IF_RDYIF_MASK _LFRCO_IF_RDY_MASK -#define _LFRCO_IF_RDYIF_DEFAULT _LFRCO_IF_RDY_DEFAULT -#define LFRCO_IF_RDYIF_DEFAULT LFRCO_IF_RDY_DEFAULT - -#define LFRCO_IF_POSEDGEIF LFRCO_IF_POSEDGE -#define _LFRCO_IF_POSEDGEIF_SHIFT _LFRCO_IF_POSEDGE_SHIFT -#define _LFRCO_IF_POSEDGEIF_MASK _LFRCO_IF_POSEDGE_MASK -#define _LFRCO_IF_POSEDGEIF_DEFAULT _LFRCO_IF_POSEDGE_DEFAULT -#define LFRCO_IF_POSEDGEIF_DEFAULT LFRCO_IF_POSEDGE_DEFAULT - -#define LFRCO_IF_NEGEDGEIF LFRCO_IF_NEGEDGE -#define _LFRCO_IF_NEGEDGEIF_SHIFT _LFRCO_IF_NEGEDGE_SHIFT -#define _LFRCO_IF_NEGEDGEIF_MASK _LFRCO_IF_NEGEDGE_MASK -#define _LFRCO_IF_NEGEDGEIF_DEFAULT _LFRCO_IF_NEGEDGE_DEFAULT -#define LFRCO_IF_NEGEDGEIF_DEFAULT LFRCO_IF_NEGEDGE_DEFAULT - -#define LFRCO_IF_TCDONEIF LFRCO_IF_TCDONE -#define _LFRCO_IF_TCDONEIF_SHIFT _LFRCO_IF_TCDONE_SHIFT -#define _LFRCO_IF_TCDONEIF_MASK _LFRCO_IF_TCDONE_MASK -#define _LFRCO_IF_TCDONEIF_DEFAULT _LFRCO_IF_TCDONE_DEFAULT -#define LFRCO_IF_TCDONEIF_DEFAULT LFRCO_IF_TCDONE_DEFAULT - -#define LFRCO_IF_CALDONEIF LFRCO_IF_CALDONE -#define _LFRCO_IF_CALDONEIF_SHIFT _LFRCO_IF_CALDONE_SHIFT -#define _LFRCO_IF_CALDONEIF_MASK _LFRCO_IF_CALDONE_MASK -#define _LFRCO_IF_CALDONEIF_DEFAULT _LFRCO_IF_CALDONE_DEFAULT -#define LFRCO_IF_CALDONEIF_DEFAULT LFRCO_IF_CALDONE_DEFAULT - -#define LFRCO_IF_TEMPCHANGEIF LFRCO_IF_TEMPCHANGE -#define _LFRCO_IF_TEMPCHANGEIF_SHIFT _LFRCO_IF_TEMPCHANGE_SHIFT -#define _LFRCO_IF_TEMPCHANGEIF_MASK _LFRCO_IF_TEMPCHANGE_MASK -#define _LFRCO_IF_TEMPCHANGEIF_DEFAULT _LFRCO_IF_TEMPCHANGE_DEFAULT -#define LFRCO_IF_TEMPCHANGEIF_DEFAULT LFRCO_IF_TEMPCHANGE_DEFAULT - -#define LFRCO_IF_SCHEDERRIF LFRCO_IF_SCHEDERR -#define _LFRCO_IF_SCHEDERRIF_SHIFT _LFRCO_IF_SCHEDERR_SHIFT -#define _LFRCO_IF_SCHEDERRIF_MASK _LFRCO_IF_SCHEDERR_MASK -#define _LFRCO_IF_SCHEDERRIF_DEFAULT _LFRCO_IF_SCHEDERR_DEFAULT -#define LFRCO_IF_SCHEDERRIF_DEFAULT LFRCO_IF_SCHEDERR_DEFAULT - -#define LFRCO_IF_TCOORIF LFRCO_IF_TCOOR -#define _LFRCO_IF_TCOORIF_SHIFT _LFRCO_IF_TCOOR_SHIFT -#define _LFRCO_IF_TCOORIF_MASK _LFRCO_IF_TCOOR_MASK -#define _LFRCO_IF_TCOORIF_DEFAULT _LFRCO_IF_TCOOR_DEFAULT -#define LFRCO_IF_TCOORIF_DEFAULT LFRCO_IF_TCOOR_DEFAULT - -#define LFRCO_IF_CALOORIF LFRCO_IF_CALOOR -#define _LFRCO_IF_CALOORIF_SHIFT _LFRCO_IF_CALOOR_SHIFT -#define _LFRCO_IF_CALOORIF_MASK _LFRCO_IF_CALOOR_MASK -#define _LFRCO_IF_CALOORIF_DEFAULT _LFRCO_IF_CALOOR_DEFAULT -#define LFRCO_IF_CALOORIF_DEFAULT LFRCO_IF_CALOOR_DEFAULT - -#define LFRCO_IEN_RDYIEN LFRCO_IEN_RDY -#define _LFRCO_IEN_RDYIEN_SHIFT _LFRCO_IEN_RDY_SHIFT -#define _LFRCO_IEN_RDYIEN_MASK _LFRCO_IEN_RDY_MASK -#define _LFRCO_IEN_RDYIEN_DEFAULT _LFRCO_IEN_RDY_DEFAULT -#define LFRCO_IEN_RDYIEN_DEFAULT LFRCO_IEN_RDY_DEFAULT - -#define LFRCO_IEN_POSEDGEIEN LFRCO_IEN_POSEDGE -#define _LFRCO_IEN_POSEDGEIEN_SHIFT _LFRCO_IEN_POSEDGE_SHIFT -#define _LFRCO_IEN_POSEDGEIEN_MASK _LFRCO_IEN_POSEDGE_MASK -#define _LFRCO_IEN_POSEDGEIEN_DEFAULT _LFRCO_IEN_POSEDGE_DEFAULT -#define LFRCO_IEN_POSEDGEIEN_DEFAULT LFRCO_IEN_POSEDGE_DEFAULT - -#define LFRCO_IEN_NEGEDGEIEN LFRCO_IEN_NEGEDGE -#define _LFRCO_IEN_NEGEDGEIEN_SHIFT _LFRCO_IEN_NEGEDGE_SHIFT -#define _LFRCO_IEN_NEGEDGEIEN_MASK _LFRCO_IEN_NEGEDGE_MASK -#define _LFRCO_IEN_NEGEDGEIEN_DEFAULT _LFRCO_IEN_NEGEDGE_DEFAULT -#define LFRCO_IEN_NEGEDGEIEN_DEFAULT LFRCO_IEN_NEGEDGE_DEFAULT - -#define LFRCO_IEN_TCDONEIEN LFRCO_IEN_TCDONE -#define _LFRCO_IEN_TCDONEIEN_SHIFT _LFRCO_IEN_TCDONE_SHIFT -#define _LFRCO_IEN_TCDONEIEN_MASK _LFRCO_IEN_TCDONE_MASK -#define _LFRCO_IEN_TCDONEIEN_DEFAULT _LFRCO_IEN_TCDONE_DEFAULT -#define LFRCO_IEN_TCDONEIEN_DEFAULT LFRCO_IEN_TCDONE_DEFAULT - -#define LFRCO_IEN_CALDONEIEN LFRCO_IEN_CALDONE -#define _LFRCO_IEN_CALDONEIEN_SHIFT _LFRCO_IEN_CALDONE_SHIFT -#define _LFRCO_IEN_CALDONEIEN_MASK _LFRCO_IEN_CALDONE_MASK -#define _LFRCO_IEN_CALDONEIEN_DEFAULT _LFRCO_IEN_CALDONE_DEFAULT -#define LFRCO_IEN_CALDONEIEN_DEFAULT LFRCO_IEN_CALDONE_DEFAULT - -#define LFRCO_IEN_TEMPCHANGEIEN LFRCO_IEN_TEMPCHANGE -#define _LFRCO_IEN_TEMPCHANGEIEN_SHIFT _LFRCO_IEN_TEMPCHANGE_SHIFT -#define _LFRCO_IEN_TEMPCHANGEIEN_MASK _LFRCO_IEN_TEMPCHANGE_MASK -#define _LFRCO_IEN_TEMPCHANGEIEN_DEFAULT _LFRCO_IEN_TEMPCHANGE_DEFAULT -#define LFRCO_IEN_TEMPCHANGEIEN_DEFAULT LFRCO_IEN_TEMPCHANGE_DEFAULT - -#define LFRCO_IEN_SCHEDERRIEN LFRCO_IEN_SCHEDERR -#define _LFRCO_IEN_SCHEDERRIEN_SHIFT _LFRCO_IEN_SCHEDERR_SHIFT -#define _LFRCO_IEN_SCHEDERRIEN_MASK _LFRCO_IEN_SCHEDERR_MASK -#define _LFRCO_IEN_SCHEDERRIEN_DEFAULT _LFRCO_IEN_SCHEDERR_DEFAULT -#define LFRCO_IEN_SCHEDERRIEN_DEFAULT LFRCO_IEN_SCHEDERR_DEFAULT - -#define LFRCO_IEN_TCOORIEN LFRCO_IEN_TCOOR -#define _LFRCO_IEN_TCOORIEN_SHIFT _LFRCO_IEN_TCOOR_SHIFT -#define _LFRCO_IEN_TCOORIEN_MASK _LFRCO_IEN_TCOOR_MASK -#define _LFRCO_IEN_TCOORIEN_DEFAULT _LFRCO_IEN_TCOOR_DEFAULT -#define LFRCO_IEN_TCOORIEN_DEFAULT LFRCO_IEN_TCOOR_DEFAULT - -#define LFRCO_IEN_CALOORIEN LFRCO_IEN_CALOOR -#define _LFRCO_IEN_CALOORIEN_SHIFT _LFRCO_IEN_CALOOR_SHIFT -#define _LFRCO_IEN_CALOORIEN_MASK _LFRCO_IEN_CALOOR_MASK -#define _LFRCO_IEN_CALOORIEN_DEFAULT _LFRCO_IEN_CALOOR_DEFAULT -#define LFRCO_IEN_CALOORIEN_DEFAULT LFRCO_IEN_CALOOR_DEFAULT - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ - -#endif +/***************************************************************************//** + * @file + * @brief CMU Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CMU_COMPAT_H +#define EM_CMU_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define CMU_IF_CALRDYIF CMU_IF_CALRDY +#define _CMU_IF_CALRDYIF_SHIFT _CMU_IF_CALRDY_SHIFT +#define _CMU_IF_CALRDYIF_MASK _CMU_IF_CALRDY_MASK +#define _CMU_IF_CALRDYIF_DEFAULT _CMU_IF_CALRDY_DEFAULT +#define CMU_IF_CALRDYIF_DEFAULT CMU_IF_CALRDY_DEFAULT + +#define CMU_IF_CALOFIF CMU_IF_CALOF +#define _CMU_IF_CALOFIF_SHIFT _CMU_IF_CALOF_SHIFT +#define _CMU_IF_CALOFIF_MASK _CMU_IF_CALOF_MASK +#define _CMU_IF_CALOFIF_DEFAULT _CMU_IF_CALOF_DEFAULT +#define CMU_IF_CALOFIF_DEFAULT CMU_IF_CALOF_DEFAULT + +#define CMU_IEN_CALRDYIEN CMU_IEN_CALRDY +#define _CMU_IEN_CALRDYIEN_SHIFT _CMU_IEN_CALRDY_SHIFT +#define _CMU_IEN_CALRDYIEN_MASK _CMU_IEN_CALRDY_MASK +#define _CMU_IEN_CALRDYIEN_DEFAULT _CMU_IEN_CALRDY_DEFAULT +#define CMU_IEN_CALRDYIEN_DEFAULT CMU_IEN_CALRDY_DEFAULT + +#define CMU_IEN_CALOFIEN CMU_IEN_CALOF +#define _CMU_IEN_CALOFIEN_SHIFT _CMU_IEN_CALOF_SHIFT +#define _CMU_IEN_CALOFIEN_MASK _CMU_IEN_CALOF_MASK +#define _CMU_IEN_CALOFIEN_DEFAULT _CMU_IEN_CALOF_DEFAULT +#define CMU_IEN_CALOFIEN_DEFAULT CMU_IEN_CALOF_DEFAULT + + +#define HFRCO_IF_RDYIF HFRCO_IF_RDY +#define _HFRCO_IF_RDYIF_SHIFT _HFRCO_IF_RDY_SHIFT +#define _HFRCO_IF_RDYIF_MASK _HFRCO_IF_RDY_MASK +#define _HFRCO_IF_RDYIF_DEFAULT _HFRCO_IF_RDY_DEFAULT +#define HFRCO_IF_RDYIF_DEFAULT HFRCO_IF_RDY_DEFAULT + +#define HFRCO_IEN_RDYIEN HFRCO_IEN_RDY +#define _HFRCO_IEN_RDYIEN_SHIFT _HFRCO_IEN_RDY_SHIFT +#define _HFRCO_IEN_RDYIEN_MASK _HFRCO_IEN_RDY_MASK +#define _HFRCO_IEN_RDYIEN_DEFAULT _HFRCO_IEN_RDY_DEFAULT +#define HFRCO_IEN_RDYIEN_DEFAULT HFRCO_IEN_RDY_DEFAULT + + +#define LFRCO_IF_RDYIF LFRCO_IF_RDY +#define _LFRCO_IF_RDYIF_SHIFT _LFRCO_IF_RDY_SHIFT +#define _LFRCO_IF_RDYIF_MASK _LFRCO_IF_RDY_MASK +#define _LFRCO_IF_RDYIF_DEFAULT _LFRCO_IF_RDY_DEFAULT +#define LFRCO_IF_RDYIF_DEFAULT LFRCO_IF_RDY_DEFAULT + +#define LFRCO_IF_POSEDGEIF LFRCO_IF_POSEDGE +#define _LFRCO_IF_POSEDGEIF_SHIFT _LFRCO_IF_POSEDGE_SHIFT +#define _LFRCO_IF_POSEDGEIF_MASK _LFRCO_IF_POSEDGE_MASK +#define _LFRCO_IF_POSEDGEIF_DEFAULT _LFRCO_IF_POSEDGE_DEFAULT +#define LFRCO_IF_POSEDGEIF_DEFAULT LFRCO_IF_POSEDGE_DEFAULT + +#define LFRCO_IF_NEGEDGEIF LFRCO_IF_NEGEDGE +#define _LFRCO_IF_NEGEDGEIF_SHIFT _LFRCO_IF_NEGEDGE_SHIFT +#define _LFRCO_IF_NEGEDGEIF_MASK _LFRCO_IF_NEGEDGE_MASK +#define _LFRCO_IF_NEGEDGEIF_DEFAULT _LFRCO_IF_NEGEDGE_DEFAULT +#define LFRCO_IF_NEGEDGEIF_DEFAULT LFRCO_IF_NEGEDGE_DEFAULT + +#define LFRCO_IF_TCDONEIF LFRCO_IF_TCDONE +#define _LFRCO_IF_TCDONEIF_SHIFT _LFRCO_IF_TCDONE_SHIFT +#define _LFRCO_IF_TCDONEIF_MASK _LFRCO_IF_TCDONE_MASK +#define _LFRCO_IF_TCDONEIF_DEFAULT _LFRCO_IF_TCDONE_DEFAULT +#define LFRCO_IF_TCDONEIF_DEFAULT LFRCO_IF_TCDONE_DEFAULT + +#define LFRCO_IF_CALDONEIF LFRCO_IF_CALDONE +#define _LFRCO_IF_CALDONEIF_SHIFT _LFRCO_IF_CALDONE_SHIFT +#define _LFRCO_IF_CALDONEIF_MASK _LFRCO_IF_CALDONE_MASK +#define _LFRCO_IF_CALDONEIF_DEFAULT _LFRCO_IF_CALDONE_DEFAULT +#define LFRCO_IF_CALDONEIF_DEFAULT LFRCO_IF_CALDONE_DEFAULT + +#define LFRCO_IF_TEMPCHANGEIF LFRCO_IF_TEMPCHANGE +#define _LFRCO_IF_TEMPCHANGEIF_SHIFT _LFRCO_IF_TEMPCHANGE_SHIFT +#define _LFRCO_IF_TEMPCHANGEIF_MASK _LFRCO_IF_TEMPCHANGE_MASK +#define _LFRCO_IF_TEMPCHANGEIF_DEFAULT _LFRCO_IF_TEMPCHANGE_DEFAULT +#define LFRCO_IF_TEMPCHANGEIF_DEFAULT LFRCO_IF_TEMPCHANGE_DEFAULT + +#define LFRCO_IF_SCHEDERRIF LFRCO_IF_SCHEDERR +#define _LFRCO_IF_SCHEDERRIF_SHIFT _LFRCO_IF_SCHEDERR_SHIFT +#define _LFRCO_IF_SCHEDERRIF_MASK _LFRCO_IF_SCHEDERR_MASK +#define _LFRCO_IF_SCHEDERRIF_DEFAULT _LFRCO_IF_SCHEDERR_DEFAULT +#define LFRCO_IF_SCHEDERRIF_DEFAULT LFRCO_IF_SCHEDERR_DEFAULT + +#define LFRCO_IF_TCOORIF LFRCO_IF_TCOOR +#define _LFRCO_IF_TCOORIF_SHIFT _LFRCO_IF_TCOOR_SHIFT +#define _LFRCO_IF_TCOORIF_MASK _LFRCO_IF_TCOOR_MASK +#define _LFRCO_IF_TCOORIF_DEFAULT _LFRCO_IF_TCOOR_DEFAULT +#define LFRCO_IF_TCOORIF_DEFAULT LFRCO_IF_TCOOR_DEFAULT + +#define LFRCO_IF_CALOORIF LFRCO_IF_CALOOR +#define _LFRCO_IF_CALOORIF_SHIFT _LFRCO_IF_CALOOR_SHIFT +#define _LFRCO_IF_CALOORIF_MASK _LFRCO_IF_CALOOR_MASK +#define _LFRCO_IF_CALOORIF_DEFAULT _LFRCO_IF_CALOOR_DEFAULT +#define LFRCO_IF_CALOORIF_DEFAULT LFRCO_IF_CALOOR_DEFAULT + +#define LFRCO_IEN_RDYIEN LFRCO_IEN_RDY +#define _LFRCO_IEN_RDYIEN_SHIFT _LFRCO_IEN_RDY_SHIFT +#define _LFRCO_IEN_RDYIEN_MASK _LFRCO_IEN_RDY_MASK +#define _LFRCO_IEN_RDYIEN_DEFAULT _LFRCO_IEN_RDY_DEFAULT +#define LFRCO_IEN_RDYIEN_DEFAULT LFRCO_IEN_RDY_DEFAULT + +#define LFRCO_IEN_POSEDGEIEN LFRCO_IEN_POSEDGE +#define _LFRCO_IEN_POSEDGEIEN_SHIFT _LFRCO_IEN_POSEDGE_SHIFT +#define _LFRCO_IEN_POSEDGEIEN_MASK _LFRCO_IEN_POSEDGE_MASK +#define _LFRCO_IEN_POSEDGEIEN_DEFAULT _LFRCO_IEN_POSEDGE_DEFAULT +#define LFRCO_IEN_POSEDGEIEN_DEFAULT LFRCO_IEN_POSEDGE_DEFAULT + +#define LFRCO_IEN_NEGEDGEIEN LFRCO_IEN_NEGEDGE +#define _LFRCO_IEN_NEGEDGEIEN_SHIFT _LFRCO_IEN_NEGEDGE_SHIFT +#define _LFRCO_IEN_NEGEDGEIEN_MASK _LFRCO_IEN_NEGEDGE_MASK +#define _LFRCO_IEN_NEGEDGEIEN_DEFAULT _LFRCO_IEN_NEGEDGE_DEFAULT +#define LFRCO_IEN_NEGEDGEIEN_DEFAULT LFRCO_IEN_NEGEDGE_DEFAULT + +#define LFRCO_IEN_TCDONEIEN LFRCO_IEN_TCDONE +#define _LFRCO_IEN_TCDONEIEN_SHIFT _LFRCO_IEN_TCDONE_SHIFT +#define _LFRCO_IEN_TCDONEIEN_MASK _LFRCO_IEN_TCDONE_MASK +#define _LFRCO_IEN_TCDONEIEN_DEFAULT _LFRCO_IEN_TCDONE_DEFAULT +#define LFRCO_IEN_TCDONEIEN_DEFAULT LFRCO_IEN_TCDONE_DEFAULT + +#define LFRCO_IEN_CALDONEIEN LFRCO_IEN_CALDONE +#define _LFRCO_IEN_CALDONEIEN_SHIFT _LFRCO_IEN_CALDONE_SHIFT +#define _LFRCO_IEN_CALDONEIEN_MASK _LFRCO_IEN_CALDONE_MASK +#define _LFRCO_IEN_CALDONEIEN_DEFAULT _LFRCO_IEN_CALDONE_DEFAULT +#define LFRCO_IEN_CALDONEIEN_DEFAULT LFRCO_IEN_CALDONE_DEFAULT + +#define LFRCO_IEN_TEMPCHANGEIEN LFRCO_IEN_TEMPCHANGE +#define _LFRCO_IEN_TEMPCHANGEIEN_SHIFT _LFRCO_IEN_TEMPCHANGE_SHIFT +#define _LFRCO_IEN_TEMPCHANGEIEN_MASK _LFRCO_IEN_TEMPCHANGE_MASK +#define _LFRCO_IEN_TEMPCHANGEIEN_DEFAULT _LFRCO_IEN_TEMPCHANGE_DEFAULT +#define LFRCO_IEN_TEMPCHANGEIEN_DEFAULT LFRCO_IEN_TEMPCHANGE_DEFAULT + +#define LFRCO_IEN_SCHEDERRIEN LFRCO_IEN_SCHEDERR +#define _LFRCO_IEN_SCHEDERRIEN_SHIFT _LFRCO_IEN_SCHEDERR_SHIFT +#define _LFRCO_IEN_SCHEDERRIEN_MASK _LFRCO_IEN_SCHEDERR_MASK +#define _LFRCO_IEN_SCHEDERRIEN_DEFAULT _LFRCO_IEN_SCHEDERR_DEFAULT +#define LFRCO_IEN_SCHEDERRIEN_DEFAULT LFRCO_IEN_SCHEDERR_DEFAULT + +#define LFRCO_IEN_TCOORIEN LFRCO_IEN_TCOOR +#define _LFRCO_IEN_TCOORIEN_SHIFT _LFRCO_IEN_TCOOR_SHIFT +#define _LFRCO_IEN_TCOORIEN_MASK _LFRCO_IEN_TCOOR_MASK +#define _LFRCO_IEN_TCOORIEN_DEFAULT _LFRCO_IEN_TCOOR_DEFAULT +#define LFRCO_IEN_TCOORIEN_DEFAULT LFRCO_IEN_TCOOR_DEFAULT + +#define LFRCO_IEN_CALOORIEN LFRCO_IEN_CALOOR +#define _LFRCO_IEN_CALOORIEN_SHIFT _LFRCO_IEN_CALOOR_SHIFT +#define _LFRCO_IEN_CALOORIEN_MASK _LFRCO_IEN_CALOOR_MASK +#define _LFRCO_IEN_CALOORIEN_DEFAULT _LFRCO_IEN_CALOOR_DEFAULT +#define LFRCO_IEN_CALOORIEN_DEFAULT LFRCO_IEN_CALOOR_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h index cf67370..69a5644 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_common.h @@ -1,36 +1,36 @@ -/***************************************************************************//** - * @file - * @brief General purpose utilities. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_COMMON_H -#define EM_COMMON_H - -#include "em_device.h" -#include "sl_common.h" - -#endif /* EM_COMMON_H */ +/***************************************************************************//** + * @file + * @brief General purpose utilities. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_COMMON_H +#define EM_COMMON_H + +#include "em_device.h" +#include "sl_common.h" + +#endif /* EM_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h index 3ad28f9..bd4b524 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core.h @@ -1,229 +1,229 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API (Device Specific) - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_CORE_H -#define EM_CORE_H - -#include "em_device.h" -#include "em_core_generic.h" -#include "sl_common.h" - -#if defined(EMLIB_USER_CONFIG) -#include "emlib_config.h" -#endif - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) -#include "emlib_core_debug_config.h" -#endif - -#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 -#endif - -/***************************************************************************//** - * @addtogroup core - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Number of words in a NVIC mask set. */ -#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) - -/** Number of entries in a default interrupt vector table. */ -#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) - -// Interrupt priorities based on processor architecture -#if defined(__CM3_REV) || defined(__CM4_REV) || defined(__CM7_REV) \ - || defined(__CM23_REV) || defined(__CM33_REV) - -/** Highest priority for core interrupt. */ -#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 - -/** Default priority for core interrupt. */ -#define CORE_INTERRUPT_DEFAULT_PRIORITY 5 - -/** Lowest priority for core interrupt. */ -#define CORE_INTERRUPT_LOWEST_PRIORITY 7 - -/** Default method to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_BASEPRI -#elif defined(__CM0_REV) || defined(__CM0PLUS_REV) - -/** Highest priority for core interrupt. */ -#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 - -/** Default priority for core interrupt. */ -#define CORE_INTERRUPT_DEFAULT_PRIORITY 1 - -/** Lowest priority for core interrupt. */ -#define CORE_INTERRUPT_LOWEST_PRIORITY 3 - -/** Default method to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_PRIMASK -#endif - -#if !defined(CORE_ATOMIC_METHOD) -/** Specify which method to use when implementing ATOMIC sections. You can - * select between BASEPRI or PRIMASK method. - * @note On Cortex-M0+ devices only PRIMASK can be used. */ -#if !defined(SL_CATALOG_DEVICE_INIT_NVIC_PRESENT) -#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK -#else -#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_DEFAULT -#endif -#endif - -// Compile time sanity check. -#if (CORE_NVIC_REG_WORDS > 3) -#error "em_core: Unexpected NVIC external interrupt count." -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ************************ MACRO API *************************************** - ******************************************************************************/ - -// -// NVIC mask section macro API. -// - -/** Allocate storage for NVIC interrupt masks for use by - * CORE_ENTER/EXIT_NVIC() macros. */ -#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState - -/** Allocate storage for NVIC interrupt masks. - * @param[in] x - * The storage variable name to use.*/ -#define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x - -/** Allocate storage for and zero initialize NVIC interrupt mask. - * @param[in] x - * The storage variable name to use.*/ -#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } - -/** NVIC mask style interrupt disable. - * @param[in] mask - * Mask specifying which NVIC interrupts to disable. */ -#define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) - -/** NVIC mask style interrupt enable. - * @param[in] mask - * Mask specifying which NVIC interrupts to enable. */ -#define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) - -/** Convenience macro for implementing a NVIC mask section. - * @param[in] mask - * Mask specifying which NVIC interrupts to disable within the section. - * @param[in] yourcode - * The code for the section. */ -#define CORE_NVIC_SECTION(mask, yourcode) \ - { \ - CORE_DECLARE_NVIC_STATE; \ - CORE_ENTER_NVIC(mask); \ - { \ - yourcode \ - } \ - CORE_EXIT_NVIC(); \ - } - -/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist - * in scope. - * @param[in] disable - * Mask specifying which NVIC interrupts to disable within the section. */ -#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) - -/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist - * in scope. */ -#define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) - -/** NVIC maks style yield. - * @param[in] enable - * Mask specifying which NVIC interrupts to briefly enable. */ -#define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Storage for NVIC interrupt masks. */ -typedef struct { - uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ -} CORE_nvicMask_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -bool CORE_IrqIsBlocked(IRQn_Type irqN); - -void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask); -bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask); - -void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, - const CORE_nvicMask_t *disable); -void CORE_NvicDisableMask(const CORE_nvicMask_t *disable); -void CORE_NvicEnableMask(const CORE_nvicMask_t *enable); -void CORE_YieldNvicMask(const CORE_nvicMask_t *enable); -void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); -void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); -bool CORE_NvicIRQDisabled(IRQn_Type irqN); - -void *CORE_GetNvicRamTableHandler(IRQn_Type irqN); -void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler); -void CORE_InitNvicVectorTable(uint32_t *sourceTable, - uint32_t sourceSize, - uint32_t *targetTable, - uint32_t targetSize, - void *defaultHandler, - bool overwriteActive); - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -uint32_t CORE_get_max_time_critical_section(void); -uint32_t CORE_get_max_time_atomic_section(void); -void CORE_clear_max_time_critical_section(void); -void CORE_clear_max_time_atomic_section(void); -#endif - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup core) */ - -#endif /* EM_CORE_H */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Device Specific) + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_CORE_H +#define EM_CORE_H + +#include "em_device.h" +#include "em_core_generic.h" +#include "sl_common.h" + +#if defined(EMLIB_USER_CONFIG) +#include "emlib_config.h" +#endif + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) +#include "emlib_core_debug_config.h" +#endif + +#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +#endif + +/***************************************************************************//** + * @addtogroup core + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Number of words in a NVIC mask set. */ +#define CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32) + +/** Number of entries in a default interrupt vector table. */ +#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16) + +// Interrupt priorities based on processor architecture +#if defined(__CM3_REV) || defined(__CM4_REV) || defined(__CM7_REV) \ + || defined(__CM23_REV) || defined(__CM33_REV) + +/** Highest priority for core interrupt. */ +#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 + +/** Default priority for core interrupt. */ +#define CORE_INTERRUPT_DEFAULT_PRIORITY 5 + +/** Lowest priority for core interrupt. */ +#define CORE_INTERRUPT_LOWEST_PRIORITY 7 + +/** Default method to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_BASEPRI +#elif defined(__CM0_REV) || defined(__CM0PLUS_REV) + +/** Highest priority for core interrupt. */ +#define CORE_INTERRUPT_HIGHEST_PRIORITY 0 + +/** Default priority for core interrupt. */ +#define CORE_INTERRUPT_DEFAULT_PRIORITY 1 + +/** Lowest priority for core interrupt. */ +#define CORE_INTERRUPT_LOWEST_PRIORITY 3 + +/** Default method to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_PRIMASK +#endif + +#if !defined(CORE_ATOMIC_METHOD) +/** Specify which method to use when implementing ATOMIC sections. You can + * select between BASEPRI or PRIMASK method. + * @note On Cortex-M0+ devices only PRIMASK can be used. */ +#if !defined(SL_CATALOG_DEVICE_INIT_NVIC_PRESENT) +#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK +#else +#define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_DEFAULT +#endif +#endif + +// Compile time sanity check. +#if (CORE_NVIC_REG_WORDS > 3) +#error "em_core: Unexpected NVIC external interrupt count." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +// +// NVIC mask section macro API. +// + +/** Allocate storage for NVIC interrupt masks for use by + * CORE_ENTER/EXIT_NVIC() macros. */ +#define CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState + +/** Allocate storage for NVIC interrupt masks. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_MASK(x) CORE_nvicMask_t x + +/** Allocate storage for and zero initialize NVIC interrupt mask. + * @param[in] x + * The storage variable name to use.*/ +#define CORE_DECLARE_NVIC_ZEROMASK(x) CORE_nvicMask_t x = { { 0 } } + +/** NVIC mask style interrupt disable. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable. */ +#define CORE_NVIC_DISABLE(mask) CORE_NvicDisableMask(mask) + +/** NVIC mask style interrupt enable. + * @param[in] mask + * Mask specifying which NVIC interrupts to enable. */ +#define CORE_NVIC_ENABLE(mask) CORE_NvicEnableMask(mask) + +/** Convenience macro for implementing a NVIC mask section. + * @param[in] mask + * Mask specifying which NVIC interrupts to disable within the section. + * @param[in] yourcode + * The code for the section. */ +#define CORE_NVIC_SECTION(mask, yourcode) \ + { \ + CORE_DECLARE_NVIC_STATE; \ + CORE_ENTER_NVIC(mask); \ + { \ + yourcode \ + } \ + CORE_EXIT_NVIC(); \ + } + +/** Enter NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. + * @param[in] disable + * Mask specifying which NVIC interrupts to disable within the section. */ +#define CORE_ENTER_NVIC(disable) CORE_EnterNvicMask(&nvicState, disable) + +/** Exit NVIC mask section. Assumes that a @ref CORE_DECLARE_NVIC_STATE exist + * in scope. */ +#define CORE_EXIT_NVIC() CORE_NvicEnableMask(&nvicState) + +/** NVIC maks style yield. + * @param[in] enable + * Mask specifying which NVIC interrupts to briefly enable. */ +#define CORE_YIELD_NVIC(enable) CORE_YieldNvicMask(enable) + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Storage for NVIC interrupt masks. */ +typedef struct { + uint32_t a[CORE_NVIC_REG_WORDS]; /*!< Array of NVIC mask words. */ +} CORE_nvicMask_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool CORE_IrqIsBlocked(IRQn_Type irqN); + +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask); +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask); + +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable); +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable); +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable); +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable); +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask); +bool CORE_NvicIRQDisabled(IRQn_Type irqN); + +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN); +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler); +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive); + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +uint32_t CORE_get_max_time_critical_section(void); +uint32_t CORE_get_max_time_atomic_section(void); +void CORE_clear_max_time_critical_section(void); +void CORE_clear_max_time_atomic_section(void); +#endif + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup core) */ + +#endif /* EM_CORE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h index 28b996d..0569570 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_core_generic.h @@ -1,173 +1,173 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API (Generic) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_CORE_GENERIC_H -#define EM_CORE_GENERIC_H - -#include -#include - -/***************************************************************************//** - * @addtogroup core - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Use PRIMASK register to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_PRIMASK 0 - -/** Use BASEPRI register to disable interrupts in ATOMIC sections. */ -#define CORE_ATOMIC_METHOD_BASEPRI 1 - -#if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) -/** The interrupt priority level disabled within ATOMIC regions. Interrupts - * with priority level equal to or lower than this definition will be disabled - * within ATOMIC regions. */ -#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ************************ MACRO API *************************************** - ******************************************************************************/ - -// -// CRITICAL section macro API. -// - -/** Allocate storage for PRIMASK or BASEPRI value for use by - * CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. */ -#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState - -/** CRITICAL style interrupt disable. */ -#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() - -/** CRITICAL style interrupt enable. */ -#define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() - -/** Convenience macro for implementing a CRITICAL section. */ -#define CORE_CRITICAL_SECTION(yourcode) \ - { \ - CORE_DECLARE_IRQ_STATE; \ - CORE_ENTER_CRITICAL(); \ - { \ - yourcode \ - } \ - CORE_EXIT_CRITICAL(); \ - } - -/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() - -/** Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) - -/** CRITICAL style yield. */ -#define CORE_YIELD_CRITICAL() CORE_YieldCritical() - -// -// ATOMIC section macro API. -// - -/** ATOMIC style interrupt disable. */ -#define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() - -/** ATOMIC style interrupt enable. */ -#define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() - -/** Convenience macro for implementing an ATOMIC section. */ -#define CORE_ATOMIC_SECTION(yourcode) \ - { \ - CORE_DECLARE_IRQ_STATE; \ - CORE_ENTER_ATOMIC(); \ - { \ - yourcode \ - } \ - CORE_EXIT_ATOMIC(); \ - } - -/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() - -/** Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in - * scope. */ -#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) - -/** ATOMIC style yield. */ -#define CORE_YIELD_ATOMIC() CORE_YieldAtomic() - -/** Check if IRQ is disabled. */ -#define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() - -/** Check if inside an IRQ handler. */ -#define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Storage for PRIMASK or BASEPRI value. */ -typedef uint32_t CORE_irqState_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void CORE_CriticalDisableIrq(void); -void CORE_CriticalEnableIrq(void); -void CORE_ExitCritical(CORE_irqState_t irqState); -void CORE_YieldCritical(void); -CORE_irqState_t CORE_EnterCritical(void); - -void CORE_AtomicDisableIrq(void); -void CORE_AtomicEnableIrq(void); -void CORE_ExitAtomic(CORE_irqState_t irqState); -void CORE_YieldAtomic(void); -CORE_irqState_t CORE_EnterAtomic(void); - -bool CORE_InIrqContext(void); -bool CORE_IrqIsDisabled(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup core) */ - -#endif /* EM_CORE_GENERIC_H */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_CORE_GENERIC_H +#define EM_CORE_GENERIC_H + +#include +#include + +/***************************************************************************//** + * @addtogroup core + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Use PRIMASK register to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_PRIMASK 0 + +/** Use BASEPRI register to disable interrupts in ATOMIC sections. */ +#define CORE_ATOMIC_METHOD_BASEPRI 1 + +#if !defined(CORE_ATOMIC_BASE_PRIORITY_LEVEL) +/** The interrupt priority level disabled within ATOMIC regions. Interrupts + * with priority level equal to or lower than this definition will be disabled + * within ATOMIC regions. */ +#define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ************************ MACRO API *************************************** + ******************************************************************************/ + +// +// CRITICAL section macro API. +// + +/** Allocate storage for PRIMASK or BASEPRI value for use by + * CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros. */ +#define CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState + +/** CRITICAL style interrupt disable. */ +#define CORE_CRITICAL_IRQ_DISABLE() CORE_CriticalDisableIrq() + +/** CRITICAL style interrupt enable. */ +#define CORE_CRITICAL_IRQ_ENABLE() CORE_CriticalEnableIrq() + +/** Convenience macro for implementing a CRITICAL section. */ +#define CORE_CRITICAL_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_CRITICAL(); \ + { \ + yourcode \ + } \ + CORE_EXIT_CRITICAL(); \ + } + +/** Enter CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_ENTER_CRITICAL() irqState = CORE_EnterCritical() + +/** Exit CRITICAL section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_EXIT_CRITICAL() CORE_ExitCritical(irqState) + +/** CRITICAL style yield. */ +#define CORE_YIELD_CRITICAL() CORE_YieldCritical() + +// +// ATOMIC section macro API. +// + +/** ATOMIC style interrupt disable. */ +#define CORE_ATOMIC_IRQ_DISABLE() CORE_AtomicDisableIrq() + +/** ATOMIC style interrupt enable. */ +#define CORE_ATOMIC_IRQ_ENABLE() CORE_AtomicEnableIrq() + +/** Convenience macro for implementing an ATOMIC section. */ +#define CORE_ATOMIC_SECTION(yourcode) \ + { \ + CORE_DECLARE_IRQ_STATE; \ + CORE_ENTER_ATOMIC(); \ + { \ + yourcode \ + } \ + CORE_EXIT_ATOMIC(); \ + } + +/** Enter ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_ENTER_ATOMIC() irqState = CORE_EnterAtomic() + +/** Exit ATOMIC section. Assumes that a @ref CORE_DECLARE_IRQ_STATE exist in + * scope. */ +#define CORE_EXIT_ATOMIC() CORE_ExitAtomic(irqState) + +/** ATOMIC style yield. */ +#define CORE_YIELD_ATOMIC() CORE_YieldAtomic() + +/** Check if IRQ is disabled. */ +#define CORE_IRQ_DISABLED() CORE_IrqIsDisabled() + +/** Check if inside an IRQ handler. */ +#define CORE_IN_IRQ_CONTEXT() CORE_InIrqContext() + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Storage for PRIMASK or BASEPRI value. */ +typedef uint32_t CORE_irqState_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void CORE_CriticalDisableIrq(void); +void CORE_CriticalEnableIrq(void); +void CORE_ExitCritical(CORE_irqState_t irqState); +void CORE_YieldCritical(void); +CORE_irqState_t CORE_EnterCritical(void); + +void CORE_AtomicDisableIrq(void); +void CORE_AtomicEnableIrq(void); +void CORE_ExitAtomic(CORE_irqState_t irqState); +void CORE_YieldAtomic(void); +CORE_irqState_t CORE_EnterAtomic(void); + +bool CORE_InIrqContext(void); +bool CORE_IrqIsDisabled(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup core) */ + +#endif /* EM_CORE_GENERIC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h index f69acef..51061fe 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_dbg.h @@ -1,134 +1,134 @@ -/***************************************************************************//** - * @file - * @brief Debug (DBG) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_DBG_H -#define EM_DBG_H - -#include -#include "em_device.h" - -#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup dbg - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Lock modes */ -typedef enum { - dbgLockModeAllowErase = 1UL, /**< Lock debug access. */ -#if !defined(_SILICON_LABS_32B_SERIES_0) - dbgLockModePermanent = 2UL /**< Lock debug access permanently. */ -#endif -} DBG_LockMode_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(GPIO_ROUTE_SWCLKPEN) \ - || defined(GPIO_ROUTEPEN_SWCLKTCKPEN) \ - || defined(GPIO_DBGROUTEPEN_SWCLKTCKPEN) -/***************************************************************************//** - * @brief - * Check if a debugger is connected (and debug session activated). - * - * @details - * Used to make run-time decisions depending on whether or not a debug session - * has been active since last reset, i.e., using a debug probe or similar. In - * some cases, special handling is required in that scenario. - * - * @return - * True if a debug session is active since last reset, otherwise false. - ******************************************************************************/ -__STATIC_INLINE bool DBG_Connected(void) -{ - return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false; -} -#endif - -#if defined(GPIO_ROUTE_SWOPEN) \ - || defined(GPIO_ROUTEPEN_SWVPEN) \ - || defined(GPIO_TRACEROUTEPEN_SWVPEN) -void DBG_SWOEnable(unsigned int location); -#endif - -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode); -#endif - -#if defined (EMU_CTRL_EM2DBGEN) -/***************************************************************************//** - * @brief - * Enable or disable debug support while in EM2 mode. - * - * @warning - * Disabling debug support in EM2 will reduce current consumption with 1-2 uA, - * but some debuggers will have problems regaining control over a device which - * is in EM2 and has debug support disabled. - * - * To remedy this, set the WSTK switch next to the battery holder to USB - * (powers down the EFR). Execute Simplicity Commander with command line - * parameters: - * "./commander.exe device recover" - * and then immediately move the switch to the AEM position. An additional - * "./commander.exe device masserase" - * command completes the recovery procedure. - * - * @param[in] enable - * Boolean true enables EM2 debug support, false disables. - ******************************************************************************/ -__STATIC_INLINE void DBG_EM2DebugEnable(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; - } else { - EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; - } -} -#endif - -/** @} (end addtogroup dbg) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ - -#endif /* EM_DBG_H */ +/***************************************************************************//** + * @file + * @brief Debug (DBG) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_DBG_H +#define EM_DBG_H + +#include +#include "em_device.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup dbg + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Lock modes */ +typedef enum { + dbgLockModeAllowErase = 1UL, /**< Lock debug access. */ +#if !defined(_SILICON_LABS_32B_SERIES_0) + dbgLockModePermanent = 2UL /**< Lock debug access permanently. */ +#endif +} DBG_LockMode_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWCLKPEN) \ + || defined(GPIO_ROUTEPEN_SWCLKTCKPEN) \ + || defined(GPIO_DBGROUTEPEN_SWCLKTCKPEN) +/***************************************************************************//** + * @brief + * Check if a debugger is connected (and debug session activated). + * + * @details + * Used to make run-time decisions depending on whether or not a debug session + * has been active since last reset, i.e., using a debug probe or similar. In + * some cases, special handling is required in that scenario. + * + * @return + * True if a debug session is active since last reset, otherwise false. + ******************************************************************************/ +__STATIC_INLINE bool DBG_Connected(void) +{ + return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? true : false; +} +#endif + +#if defined(GPIO_ROUTE_SWOPEN) \ + || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +void DBG_SWOEnable(unsigned int location); +#endif + +#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) +void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode); +#endif + +#if defined (EMU_CTRL_EM2DBGEN) +/***************************************************************************//** + * @brief + * Enable or disable debug support while in EM2 mode. + * + * @warning + * Disabling debug support in EM2 will reduce current consumption with 1-2 uA, + * but some debuggers will have problems regaining control over a device which + * is in EM2 and has debug support disabled. + * + * To remedy this, set the WSTK switch next to the battery holder to USB + * (powers down the EFR). Execute Simplicity Commander with command line + * parameters: + * "./commander.exe device recover" + * and then immediately move the switch to the AEM position. An additional + * "./commander.exe device masserase" + * command completes the recovery procedure. + * + * @param[in] enable + * Boolean true enables EM2 debug support, false disables. + ******************************************************************************/ +__STATIC_INLINE void DBG_EM2DebugEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EM2DBGEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EM2DBGEN; + } +} +#endif + +/** @} (end addtogroup dbg) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ + +#endif /* EM_DBG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h index 1f1a857..d9b65d0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_emu.h @@ -1,1760 +1,1760 @@ -/***************************************************************************//** - * @file - * @brief Energy Management Unit (EMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EMU_H -#define EM_EMU_H - -#include "em_device.h" -#include "sl_status.h" -#if defined(EMU_PRESENT) - -#include -#include "em_bus.h" -#include "sl_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup emu - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) -/** Voltage scaling present */ -#define EMU_VSCALE_PRESENT -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -/** Voltage scaling for EM01 present */ -#define EMU_VSCALE_EM01_PRESENT -#endif -#endif - -#if defined(_EMU_DCDCCTRL_MASK) -/** DC-DC buck converter present */ -#define EMU_SERIES1_DCDC_BUCK_PRESENT -#endif - -#if defined(_SILICON_LABS_DCDC_FEATURE) \ - && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \ - || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) -/** DC-DC buck converter present */ -#define EMU_SERIES2_DCDC_BUCK_PRESENT -#endif - -#if defined(_SILICON_LABS_DCDC_FEATURE) \ - && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \ - || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) -/** DC-DC boost converter present */ -#define EMU_SERIES2_DCDC_BOOST_PRESENT -#endif - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -#if defined(_EMU_EM4CONF_OSC_MASK) -/** EM4 duty oscillator. */ -typedef enum { - /** Select ULFRCO as duty oscillator in EM4. */ - emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, - /** Select LFXO as duty oscillator in EM4. */ - emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, - /** Select LFRCO as duty oscillator in EM4. */ - emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO -} EMU_EM4Osc_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_PROBE_MASK) -/** Backup Power Voltage Probe types. */ -typedef enum { - /** Disable voltage probe. */ - emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, - /** Connect probe to VDD_DREG. */ - emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, - /** Connect probe to BU_IN. */ - emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, - /** Connect probe to BU_OUT. */ - emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT -} EMU_Probe_TypeDef; -#endif - -#if defined(_EMU_PWRCONF_PWRRES_MASK) -/** Backup Power Domain resistor selection. */ -typedef enum { - /** Main power and backup power connected with RES0 series resistance. */ - emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, - /** Main power and backup power connected with RES1 series resistance. */ - emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, - /** Main power and backup power connected with RES2 series resistance. */ - emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, - /** Main power and backup power connected with RES3 series resistance. */ - emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, -} EMU_Resistor_TypeDef; -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/** Backup Power Domain power connection. */ -typedef enum { - /** No connection between main and backup power. */ - emuPower_None = EMU_BUINACT_PWRCON_NONE, - /** Main power and backup power connected through diode, - allowing current from backup to main only. */ - emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, - /** Main power and backup power connected through diode, - allowing current from main to backup only. */ - emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, - /** Main power and backup power connected without diode. */ - emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, -} EMU_Power_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -/** Backup Power Domain power connection configuration when not in backup mode selection. */ -typedef enum { - /** No connection. */ - emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, - /** Allow power from main to backup. */ - emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, - /** Allow power from backup to main. */ - emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, - /** Backup and main power are connected. */ - emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, -} EMU_BUBuInactPwrCon_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -/** Backup Power Domain power connection configuration in backup mode selection. */ -typedef enum { - /** No connection. */ - emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, - /** Allow power from main to backup. */ - emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, - /** Allow power from backup to main. */ - emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, - /** Backup and main power are connected. */ - emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, -} EMU_BUBuActPwrCon_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_PWRRES_MASK) -/** Backup Power Domain resistor selection. */ -typedef enum { - /** Main power and backup power connected with RES0 series resistance. */ - emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, - /** Main power and backup power connected with RES1 series resistance. */ - emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, - /** Main power and backup power connected with RES2 series resistance. */ - emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, - /** Main power and backup power connected with RES3 series resistance. */ - emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, -} EMU_BUPwrRes_TypeDef; -#endif - -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -/** Resistance between backup domain power supply and BU_VOUT. */ -typedef enum { - /** BU_VOUT is not connected. */ - emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, - /** Enable weak switch. */ - emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, - /** Enable medium switch. */ - emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, - /** Enable strong switch. */ - emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, -} EMU_BUVoutRes_TypeDef; -#endif - -/** BOD threshold setting selector, active or inactive mode. */ -typedef enum { - /** Configure BOD threshold for active mode. */ - emuBODMode_Active, - /** Configure BOD threshold for inactive mode. */ - emuBODMode_Inactive, -} EMU_BODMode_TypeDef; - -/** EM4 modes. */ -typedef enum { - /** EM4 Shutoff. */ - emuEM4Shutoff = 0, - /** EM4 Hibernate. */ - emuEM4Hibernate = 1, -} EMU_EM4State_TypeDef; - -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/** EM4 Pin Retention Type. */ -typedef enum { - /** No Retention: Pads enter reset state when entering EM4. */ - emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, - /** Retention through EM4: Pads enter reset state when exiting EM4. */ - emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, - /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to - release pins from retention after EM4 wakeup. */ - emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, -} EMU_EM4PinRetention_TypeDef; -#endif - -/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ -typedef enum { - /** DCDC is connected to DVDD. */ - emuPowerConfig_DcdcToDvdd, -} EMU_PowerConfig_TypeDef; - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC operating modes. */ -typedef enum { - /** DCDC regulator bypass. */ - emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, - /** DCDC low-noise mode. */ - emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, -#if defined(_EMU_DCDCLPEM01CFG_MASK) - /** DCDC low-power mode. */ - emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, -#endif -} EMU_DcdcMode_TypeDef; - -/** DCDC operating modes in EM2 or EM3. */ -typedef enum { - /** DCDC mode is low power. */ - emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER, - /** DCDC mode is according to DCDCMODE field. */ - emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW, -} EMU_DcdcModeEM23_TypeDef; - -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC conduction modes. */ -typedef enum { - /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization - features are available in this mode. */ - emuDcdcConductionMode_ContinuousLN, - /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or - for EFR32 when its radio is not enabled. */ - emuDcdcConductionMode_DiscontinuousLN, -} EMU_DcdcConductionMode_TypeDef; -#endif - -#if defined(_EMU_PWRCTRL_MASK) -/** DCDC to DVDD mode analog peripheral power supply select. */ -typedef enum { - /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ - emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, - /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ - emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD -} EMU_DcdcAnaPeripheralPower_TypeDef; -#endif - -#if defined(_EMU_DCDCMISCCTRL_MASK) -/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ -typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; - -/** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ -#define emuDcdcLnHighEfficiency -1 - -/** Default reverse current for fast transient response mode (low noise). */ -#define emuDcdcLnFastTransient 160 -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC Low-noise RCO band select. */ -typedef enum { - /** Set RCO to 3MHz. */ - emuDcdcLnRcoBand_3MHz = 0, - /** Set RCO to 4MHz. */ - emuDcdcLnRcoBand_4MHz = 1, - /** Set RCO to 5MHz. */ - emuDcdcLnRcoBand_5MHz = 2, - /** Set RCO to 6MHz. */ - emuDcdcLnRcoBand_6MHz = 3, - /** Set RCO to 7MHz. */ - emuDcdcLnRcoBand_7MHz = 4, - /** Set RCO to 8MHz. */ - emuDcdcLnRcoBand_8MHz = 5, - /** Set RCO to 9MHz. */ - emuDcdcLnRcoBand_9MHz = 6, - /** Set RCO to 10MHz. */ - emuDcdcLnRcoBand_10MHz = 7, -} EMU_DcdcLnRcoBand_TypeDef; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated. */ -#define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz -#define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz -#define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz -#define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz -#define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz -#define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz -#define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz -#define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz -/** @endcond */ - -/** DCDC Low Noise Compensator Control register. */ -typedef enum { - /** DCDC capacitor is 1uF. */ - emuDcdcLnCompCtrl_1u0F, - /** DCDC capacitor is 4.7uF. */ - emuDcdcLnCompCtrl_4u7F, -} EMU_DcdcLnCompCtrl_TypeDef; -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) - -/** DCDC mode. */ -typedef enum { - emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */ - emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */ -} EMU_DcdcMode_TypeDef; -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/** VREGIN comparator threshold. */ -typedef enum { - emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */ - emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */ - emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */ - emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */ -} EMU_VreginCmpThreshold_TypeDef; - -/** DCDC Buck Ton max timeout. */ -typedef enum { -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) - emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ - emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ - emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ - emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ - emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ - emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ - emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ - emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */ -#else - emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */ - emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */ - emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */ - emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */ - emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */ - emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */ - emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */ - emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */ - emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */ - emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */ - emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */ - emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */ - emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */ - emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */ - emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */ - emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */ - emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */ - emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */ - emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */ - emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */ - emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */ - emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */ - emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */ - emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */ - emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */ - emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */ - emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */ - emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */ - emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */ - emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */ - emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */ - emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */ -#endif -} EMU_DcdcTonMaxTimeout_TypeDef; - -/** DCDC Buck drive speed. */ -typedef enum { - emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ -} EMU_DcdcDriveSpeed_TypeDef; - -/** DCDC Buck peak current setting. */ -typedef enum { -#if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA) - emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA) - emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA) - emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ -#endif -#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA) - emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA) - emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA) - emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA) - emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ -#endif - emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ - emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ - emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ - emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ - emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ - emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA) - emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA) - emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA) - emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA) - emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */ -#endif -#if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA) - emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ -#endif -} EMU_DcdcPeakCurrent_TypeDef; -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/** DCDC Boost drive speed. */ -typedef enum { - emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ - emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ -} EMU_DcdcBoostDriveSpeed_TypeDef; - -/** DCDC Boost EM01 peak current setting. */ -typedef enum { - emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ - emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ - emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ - emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ - emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ - emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ - emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ - emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ - emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ - emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ -} EMU_DcdcBoostEM01PeakCurrent_TypeDef; - -/** DCDC Boost Toff max timeout */ -typedef enum { - emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */ - emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */ - emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */ - emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */ - emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */ - emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */ - emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */ - emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */ -} EMU_DcdcBoostToffMaxTimeout_TypeDef; - -/** DCDC Boost peak current detection maximum timeout */ -typedef enum { - emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ - emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ - emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ - emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ - emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ - emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ - emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ - emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */ -} EMU_DcdcBoostTonMaxTimeout_TypeDef; - -/** DCDC Boost EM23 peak current setting. */ -typedef enum { - emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ -} EMU_DcdcBoostEM23PeakCurrent_TypeDef; -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ - -#if defined(EMU_STATUS_VMONRDY) -/** VMON channels. */ -typedef enum { - emuVmonChannel_AVDD, - emuVmonChannel_ALTAVDD, - emuVmonChannel_DVDD, - emuVmonChannel_IOVDD0, -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - emuVmonChannel_IOVDD1, -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - emuVmonChannel_BUVDD, -#endif -} EMU_VmonChannel_TypeDef; -#endif /* EMU_STATUS_VMONRDY */ - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/** Bias mode configurations. */ -typedef enum { - emuBiasMode_1KHz, - emuBiasMode_4KHz, - emuBiasMode_Continuous -} EMU_BiasMode_TypeDef; -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/** Supported EM0/1 Voltage Scaling Levels. */ -typedef enum { - /** High-performance voltage level. HF clock can be set to any frequency. */ - emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, - /** Low-power optimized voltage level. HF clock must be limited - to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. - EM0/1 voltage scaling is applied when core clock frequency is - changed from @ref cmu or when calling @ref EMU_EM01Init() when HF - clock is already below the limit. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - /** Minimum VSCALE level in EM0/1 is VSCALE1. */ - emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1, -#else - emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, -#endif -} EMU_VScaleEM01_TypeDef; -#endif - -#if defined(EMU_VSCALE_PRESENT) -/** Supported EM2/3 Voltage Scaling Levels. */ -typedef enum { - /** Fast-wakeup voltage level. */ - emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, - /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 - adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled - up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ - emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, -} EMU_VScaleEM23_TypeDef; -#endif - -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) -/** Supported EM4H Voltage Scaling Levels */ -typedef enum { - /** Fast-wakeup voltage level. */ - emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, - /** Low-power optimized voltage level. Using this voltage level in EM4H - adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled - up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ - emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, -} EMU_VScaleEM4H_TypeDef; -#endif - -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -/** Peripheral EM2 and 3 retention control. */ -typedef enum { -#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) - emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) - emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) - emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) - emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) - emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) - emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) - emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) - emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) - emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */ -#endif - emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) - emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */ -#endif - emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) - emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */ -#endif - emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */ - emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */ - emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) - emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) - emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */ -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) - emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */ -#endif - emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */ - emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */ - emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */ -#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) - emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */ - emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */ -#endif - emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */ - - emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK - | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */ - emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK -#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK -#endif - | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK -#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK - | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK -#endif -#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) - | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */ -#endif - | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, - emuPeripheralRetention_ALL = emuPeripheralRetention_D1 - | emuPeripheralRetention_D2 -#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) - | emuPeripheralRetention_WDOG1 -#endif - | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */ -} EMU_PeripheralRetention_TypeDef; -#endif - -#if defined(_EMU_TEMP_TEMPAVG_MASK) -/** Number of samples to use for temperature averaging. */ -typedef enum { - /** 16 samples used for temperature averaging. */ - emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16, - /** 64 samples used for temperature averaging. */ - emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64, -} EMU_TempAvgNum_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/** EM0 and 1 initialization structure. Voltage scaling is applied when - the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance - is always enabled. */ -typedef struct { - bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ -} EMU_EM01Init_TypeDef; - -/** Default initialization of EM0 and 1 configuration. */ -#define EMU_EM01INIT_DEFAULT \ - { \ - false /* Do not scale down in EM0/1.*/ \ - } -#endif - -/** EM2 and 3 initialization structure. */ -typedef struct { - bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ -#if defined(EMU_VSCALE_PRESENT) - EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ -#endif -} EMU_EM23Init_TypeDef; - -/** Default initialization of EM2 and 3 configuration. */ -#if defined(EMU_VSCALE_PRESENT) -#define EMU_EM23INIT_DEFAULT \ - { \ - false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ - emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ - } -#else -#define EMU_EM23INIT_DEFAULT \ - { \ - false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ - } -#endif - -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -/** EM4 initialization structure. */ -typedef struct { -#if defined(_EMU_EM4CONF_MASK) - /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ - bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ - bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ - EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ - bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ - bool vreg; /**< Enable EM4 voltage regulator. */ -#elif defined(_EMU_EM4CTRL_MASK) - /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ - bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ - bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ - bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ - EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ - EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ -#endif -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) - EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ -#endif -} EMU_EM4Init_TypeDef; -#endif - -#if defined(_EMU_EM4CONF_MASK) -/** Default initialization of EM4 configuration (Series 0). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Do not lock configuration after it's been set. */ \ - false, /* No reset will be asserted due to BOD in EM4. */ \ - emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ - true, /* Wake up on EM4 BURTC interrupt. */ \ - true, /* Enable VREG. */ \ - } - -#elif defined(_EMU_CTRL_EM4HVSCALE_MASK) -/** Default initialization of EM4 configuration (Series 1 with VSCALE). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Retain LFXO configuration upon EM4 entry. */ \ - false, /* Retain LFRCO configuration upon EM4 entry. */ \ - false, /* Retain ULFRCO configuration upon EM4 entry. */ \ - emuEM4Shutoff, /* Use EM4 shutoff state. */ \ - emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ - emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ - } - -#elif defined(_EMU_EM4CTRL_MASK) -/** Default initialization of EM4 configuration (Series 1 without VSCALE). */ -#define EMU_EM4INIT_DEFAULT \ - { \ - false, /* Retain LFXO configuration upon EM4 entry. */ \ - false, /* Retain LFRCO configuration upon EM4 entry. */ \ - false, /* Retain ULFRCO configuration upon EM4 entry. */ \ - emuEM4Shutoff, /* Use EM4 shutoff state. */ \ - emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ - } -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/** Backup Power Domain Initialization structure. */ -typedef struct { - /* Backup Power Domain power configuration. */ - - /** Voltage probe select, selects ADC voltage. */ - EMU_Probe_TypeDef probe; - /** Enable BOD calibration mode. */ - bool bodCal; - /** Enable BU_STAT status pin for active BU mode. */ - bool statusPinEnable; - - /* Backup Power Domain connection configuration. */ - /** Power domain resistor. */ - EMU_Resistor_TypeDef resistor; - /** BU_VOUT strong enable. */ - bool voutStrong; - /** BU_VOUT medium enable. */ - bool voutMed; - /** BU_VOUT weak enable. */ - bool voutWeak; - /** Power connection, when not in Backup Mode. */ - EMU_Power_TypeDef inactivePower; - /** Power connection, when in Backup Mode. */ - EMU_Power_TypeDef activePower; - /** Enable backup power domain, and release reset, enable BU_VIN pin. */ - bool enable; -} EMU_BUPDInit_TypeDef; - -/** Default Backup Power Domain configuration. */ -#define EMU_BUPDINIT_DEFAULT \ - { \ - emuProbe_Disable, /* Do not enable voltage probe. */ \ - false, /* Disable BOD calibration mode. */ \ - false, /* Disable BU_STAT pin for backup mode indication. */ \ - \ - emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ - false, /* Do not enable strong switch. */ \ - false, /* Do not enable medium switch. */ \ - false, /* Do not enable weak switch. */ \ - \ - emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ - emuPower_None, /* No connection between main and backup power. (active mode) */ \ - true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ - } -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -/** Backup Power Domain Initialization structure. */ -typedef struct { - bool disMaxComp; /**< Disable MAIN-BU Comparator. */ - EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ - EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ - EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ - EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ - bool buVinProbeEn; /**< Enable BU_VIN probing. */ - bool staEn; /**< Enable backup mode status export. */ - bool enable; /**< Enable backup power domain. */ -} EMU_BUInit_TypeDef; - -/** Default Backup Power Domain configuration. */ -#define EMU_BUINIT_DEFAULT \ - { \ - false, /* MAIN-BU Comparator is not disabled */ \ - emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \ - emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \ - emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \ - emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \ - false, /* BU_VIN probe is disabled */ \ - false, /* Status export is disabled */ \ - true /* Enable backup mode */ \ - } -#endif - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/** DCDC Boost regulator initialization structure. */ -typedef struct { - EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ - bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */ - EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ - EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ - EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ - EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ -} EMU_DCDCBoostInit_TypeDef; - -/** Default DCDC Boost initialization. */ -#define EMU_DCDCBOOSTINIT_DEFAULT \ - { \ - emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ - emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ - emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ - } -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/** DCDC regulator initialization structure. */ -typedef struct { - EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */ - EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */ - EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ -#if defined(_DCDC_CTRL_DCMONLYEN_MASK) - bool dcmOnlyEn; /**< DCM only mode enable. */ -#endif - EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ - EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ - EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ - EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ -} EMU_DCDCInit_TypeDef; - -/** Default DCDC Buck initialization. */ -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ - emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ - emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - true, /**< Enable DCM only mode. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ - emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ - emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ - emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ - emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ - emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ - emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ - } -#endif -#endif /* SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** DCDC initialization structure. */ -typedef struct { - EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. - @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ - EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ - uint16_t mVout; /**< Target output voltage (mV). */ - uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). - This estimate is also used for EM1 optimization; - if EM1 current is expected to be higher than EM0, - then this parameter should hold the higher EM1 current. */ - uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). - This estimate is also used for EM3 and 4 optimization; - if EM3 or 4 current is expected to be higher than EM2, - then this parameter should hold the higher EM3 or 4 current. */ - uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). - This can be set to the maximum for the power source, - for example the maximum for a battery. */ - EMU_DcdcAnaPeripheralPower_TypeDef - anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ - EMU_DcdcLnReverseCurrentControl_TypeDef - reverseCurrentControl; /**< Low-noise reverse current control. - NOTE: this parameter uses special encoding: - >= 0 is forced CCM mode where the parameter is used as the - reverse current threshold in mA. - -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ - EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ -} EMU_DCDCInit_TypeDef; - -/** Default DCDC initialization. */ -#if defined(_EFM_DEVICE) -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ - } -#elif defined(WGM160PX22KGA2) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#else -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 5, /* Nominal EM0/1 load current of less than 5mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ - emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#endif - -#else /* EFR32 device. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 15, /* Nominal EM0/1 load current of less than 15mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - 160, /* Maximum reverse current of 160mA. */ \ - emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ - } -#else -#define EMU_DCDCINIT_DEFAULT \ - { \ - emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ - emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ - 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ - 15, /* Nominal EM0/1 load current of less than 15mA. */ \ - 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ - 200, /* Maximum average current of 200mA - (assume strong battery or other power source). */ \ - emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ - 160, /* Maximum reverse current of 160mA. */ \ - emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ - } -#endif -#endif -#endif - -#if defined(EMU_STATUS_VMONRDY) -/** VMON initialization structure. */ -typedef struct { - EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ - int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ - bool riseWakeup; /**< Wake up from EM4H on rising edge. */ - bool fallWakeup; /**< Wake up from EM4H on falling edge. */ - bool enable; /**< Enable VMON channel. */ - bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ -} EMU_VmonInit_TypeDef; - -/** Default VMON initialization structure. */ -#define EMU_VMONINIT_DEFAULT \ - { \ - emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ - 3200, /* 3.2 V threshold. */ \ - false, /* Do not wake from EM4H on rising edge. */ \ - false, /* Do not wake from EM4H on falling edge. */ \ - true, /* Enable VMON channel. */ \ - false /* Do not disable IO0 retention */ \ - } - -/** VMON Hysteresis initialization structure. */ -typedef struct { - EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ - int riseThreshold; /**< Rising threshold (mV). */ - int fallThreshold; /**< Falling threshold (mV). */ - bool riseWakeup; /**< Wake up from EM4H on rising edge. */ - bool fallWakeup; /**< Wake up from EM4H on falling edge. */ - bool enable; /**< Enable VMON channel. */ -} EMU_VmonHystInit_TypeDef; - -/** Default VMON Hysteresis initialization structure. */ -#define EMU_VMONHYSTINIT_DEFAULT \ - { \ - emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ - 3200, /* 3.2 V rise threshold. */ \ - 3200, /* 3.2 V fall threshold. */ \ - false, /* Do not wake from EM4H on rising edge. */ \ - false, /* Do not wake from EM4H on falling edge. */ \ - true /* Enable VMON channel. */ \ - } -#endif /* EMU_STATUS_VMONRDY */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); -#endif -void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); -void EMU_EM23PresleepHook(void); -void EMU_EM23PostsleepHook(void); -void EMU_EFPEM23PresleepHook(void); -void EMU_EFPEM23PostsleepHook(void); -void EMU_EnterEM2(bool restore); -void EMU_EnterEM3(bool restore); -void EMU_Save(void); -void EMU_Restore(void); -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); -#endif -void EMU_EM4PresleepHook(void); -void EMU_EFPEM4PresleepHook(void); -void EMU_EnterEM4(void); -void EMU_EnterEM4Wait(void); -#if defined(_EMU_EM4CTRL_MASK) -void EMU_EnterEM4H(void); -void EMU_EnterEM4S(void); -#endif -void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1; -void EMU_RamPowerDown(uint32_t start, uint32_t end); -void EMU_RamPowerUp(void); -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); -#endif -void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1; -#if defined(EMU_VSCALE_EM01_PRESENT) -#if defined(_SILICON_LABS_32B_SERIES_2) -void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage); -#endif -void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); -void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); -#endif -#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) -void EMU_BUDisMaxCompSet(bool disableMainBuComparator); -#endif -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); -#endif -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); -#endif -#if defined(_EMU_BUCTRL_PWRRES_MASK) -void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); -#endif -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); -#endif -#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) -void EMU_BUBuVinProbeEnSet(bool enable); -#endif -#if defined(_EMU_BUCTRL_STATEN_MASK) -void EMU_BUStatEnSet(bool enable); -#endif -#if defined(_EMU_BUCTRL_EN_MASK) -void EMU_BUEnableSet(bool enable); -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -#endif - -#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) -sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -void EMU_DCDCUpdatedHook(void); -#endif - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); -void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); -void EMU_BoostExternalShutdownEnable(bool enable); -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); -bool EMU_DCDCPowerOff(void); -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); -#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) -void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); -#endif -#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) -void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value); -#endif -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#if defined(EMU_DCDCCTRL_DCDCMODEEM23) -void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23); -#endif -void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); -bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); -void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_STATUS_VMONRDY) -void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); -void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); -#endif -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); -#endif -#if defined(_EMU_TEMP_TEMP_MASK) -float EMU_TemperatureGet(void); -#endif -#if defined(EMU_CTRL_EFPDIRECTMODEEN) -void EMU_EFPDirectModeEnable(bool enable); -#endif -#if defined(EMU_CTRL_EFPDRVDECOUPLE) -void EMU_EFPDriveDecoupleSet(bool enable); -#endif -#if defined(EMU_CTRL_EFPDRVDVDD) -void EMU_EFPDriveDvddSet(bool enable); -#endif - -#if defined(_DCDC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Lock DCDC registers in order to protect them against unintended - * modification. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCLock(void) -{ - DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; -} -#endif - -#if defined(_DCDC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Unlock the DCDC so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCUnlock(void) -{ - DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; -} -#endif - -#if defined(_DCDC_SYNCBUSY_MASK) -/***************************************************************************//** - * @brief - * Wait for the DCDC to complete all synchronization of register changes. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void EMU_DCDCSync(uint32_t mask) -{ - while (0UL != (DCDC->SYNCBUSY & mask)) { - /* Wait for previous synchronization to finish */ - } -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Check status of the internal LDO regulator. - * - * @return - * Return true if the regulator is on, false if regulator is off. - ******************************************************************************/ -__STATIC_INLINE bool EMU_LDOStatusGet(void) -{ - if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) { - return true; - } else { - return false; - } -} -#endif - -/***************************************************************************//** - * @brief - * Enter energy mode 1 (EM1). - * - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - ******************************************************************************/ -__STATIC_INLINE void EMU_EnterEM1(void) -{ - /* Enter sleep mode. */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - __WFI(); -} - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Wait for voltage scaling to complete. - ******************************************************************************/ -__STATIC_INLINE void EMU_VScaleWait(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip waiting if the LDO regulator is turned off. */ - return; - } -#endif - - while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { - } -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Get current voltage scaling level. - * - * @return - * Current voltage scaling level. - ******************************************************************************/ -__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) -{ - EMU_VScaleWait(); - return (EMU_VScaleEM01_TypeDef)((uint32_t) - ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) - >> _EMU_STATUS_VSCALE_SHIFT)); -} -#endif - -#if defined(_EMU_STATUS_VMONRDY_MASK) -/***************************************************************************//** - * @brief - * Get the status of the voltage monitor (VMON). - * - * @return - * Status of the VMON. True if all the enabled channels are ready, false if - * one or more of the enabled channels are not ready. - ******************************************************************************/ -__STATIC_INLINE bool EMU_VmonStatusGet(void) -{ - return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; -} -#endif /* _EMU_STATUS_VMONRDY_MASK */ - -#if defined(_EMU_IF_MASK) -/***************************************************************************//** - * @brief - * Clear one or more pending EMU interrupts. - * - * @param[in] flags - * Pending EMU interrupt sources to clear. Use one or more valid - * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntClear(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IF_CLR = flags; -#else - EMU->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more EMU interrupts. - * - * @param[in] flags - * EMU interrupt sources to disable. Use one or more valid - * interrupt flags for the EMU module (EMU_IEN_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntDisable(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IEN_CLR = flags; -#else - EMU->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more EMU interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * @ref EMU_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * EMU interrupt sources to enable. Use one or more valid - * interrupt flags for the EMU module (EMU_IEN_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntEnable(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IEN_SET = flags; -#else - EMU->IEN |= flags; -#endif -} - -#if defined(EMU_CTRL_EFPDRVDVDD) -/***************************************************************************//** - * @brief - * Disable one or more EFP interrupts. - * - * @param[in] flags - * EFP interrupt sources to disable. Use one or more valid - * interrupt flags for the EFP module (EFPIENnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags) -{ - EMU->EFPIEN_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more EFP interrupts. - * - * @param[in] flags - * EFP interrupt sources to enable. Use one or more valid - * interrupt flags for the EFP module (EFPIENnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags) -{ - EMU->EFPIEN_SET = flags; -} - -/***************************************************************************//** - * @brief - * Get pending EMU EFP interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * EMU EFP interrupt sources pending. . - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_EFPIntGet(void) -{ - return EMU->EFPIF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending EMU EFP interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled EMU EFP interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in EMU_EFPIEN and - * - the pending interrupt flags EMU_EFPIF. - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void) -{ - uint32_t ien; - - ien = EMU->EFPIEN; - return EMU->EFPIF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending EMU EFP interrupts. - * - * @param[in] flags - * EMU EFP interrupt sources to set to pending. Use one or more valid - * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntSet(uint32_t flags) -{ - EMU->EFPIF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Clear one or more pending EMU EFP interrupts. - * - * @param[in] flags - * Pending EMU EFP interrupt sources to clear. Use one or more valid - * interrupt flags for the EMU EFP module. - ******************************************************************************/ -__STATIC_INLINE void EMU_EFPIntClear(uint32_t flags) -{ - EMU->EFPIF_CLR = flags; -} -#endif - -/***************************************************************************//** - * @brief - * Get pending EMU interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * EMU interrupt sources pending. Returns one or more valid - * interrupt flags for the EMU module (EMU_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_IntGet(void) -{ - return EMU->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending EMU interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled EMU interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in EMU_IEN and - * - the pending interrupt flags EMU_IF. - ******************************************************************************/ -__STATIC_INLINE uint32_t EMU_IntGetEnabled(void) -{ - uint32_t ien; - - ien = EMU->IEN; - return EMU->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending EMU interrupts. - * - * @param[in] flags - * EMU interrupt sources to set to pending. Use one or more valid - * interrupt flags for the EMU module (EMU_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void EMU_IntSet(uint32_t flags) -{ -#if defined(EMU_HAS_SET_CLEAR) - EMU->IF_SET = flags; -#else - EMU->IFS = flags; -#endif -} -#endif /* _EMU_IF_MASK */ - -#if defined(_EMU_EM4CONF_LOCKCONF_MASK) -/***************************************************************************//** - * @brief - * Enable or disable EM4 lock configuration. - * @param[in] enable - * If true, locks down EM4 configuration. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM4Lock(bool enable) -{ - BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); -} -#endif - -#if defined(_EMU_STATUS_BURDY_MASK) -/***************************************************************************//** - * @brief - * Halts until backup power functionality is ready. - ******************************************************************************/ -__STATIC_INLINE void EMU_BUReady(void) -{ - while (!(EMU->STATUS & EMU_STATUS_BURDY)) - ; -} -#endif - -#if defined(_EMU_ROUTE_BUVINPEN_MASK) -/***************************************************************************//** - * @brief - * Disable BU_VIN support. - * @param[in] enable - * If true, enables BU_VIN input pin support, if false disables it. - ******************************************************************************/ -__STATIC_INLINE void EMU_BUPinEnable(bool enable) -{ - BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); -} -#endif - -/***************************************************************************//** - * @brief - * Lock EMU registers in order to protect them against unintended - * modification. - * - * @note - * If locking EMU registers, they must be unlocked prior to using any - * EMU API functions modifying EMU registers, excluding interrupt control - * and regulator control if the architecture has a EMU_PWRCTRL register. - * An exception to this is the energy mode entering API (EMU_EnterEMn()), - * which can be used when the EMU registers are locked. - ******************************************************************************/ -__STATIC_INLINE void EMU_Lock(void) -{ - EMU->LOCK = 0x0; -} - -/***************************************************************************//** - * @brief - * Unlock the EMU so that writing to locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_Unlock(void) -{ - EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; -} - -#if defined(_EMU_PWRLOCK_MASK) -/***************************************************************************//** - * @brief - * Lock the EMU regulator control registers in order to protect against - * unintended modification. - ******************************************************************************/ -__STATIC_INLINE void EMU_PowerLock(void) -{ - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; -} - -/***************************************************************************//** - * @brief - * Unlock the EMU power control registers so that writing to - * locked registers again is possible. - ******************************************************************************/ -__STATIC_INLINE void EMU_PowerUnlock(void) -{ - EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; -} -#endif - -#if defined(_EMU_CTRL_EM2BLOCK_MASK) -/***************************************************************************//** - * @brief - * Block entering EM2 or higher number energy modes. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM2Block(void) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); -} - -/***************************************************************************//** - * @brief - * Unblock entering EM2 or higher number energy modes. - ******************************************************************************/ -__STATIC_INLINE void EMU_EM2UnBlock(void) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); -} -#endif - -#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/***************************************************************************//** - * @brief - * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained - * through EM4 entry and wakeup. The pin state is released by calling this function. - * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), - * and when initialization is done, this function can release pins and return control - * to the peripherals or GPIO. - ******************************************************************************/ -__STATIC_INLINE void EMU_UnlatchPinRetention(void) -{ - EMU->CMD = EMU_CMD_EM4UNLATCH; -} -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/** Zero degrees Celcius in Kelvin */ -#define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f) -/***************************************************************************//** - * @brief - * Temperature measurement ready status - * - * @return - * True if temperature measurement is ready - ******************************************************************************/ -__STATIC_INLINE bool EMU_TemperatureReady(void) -{ -#if defined(EMU_STATUS_FIRSTTEMPDONE) - return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); -#else - return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u); -#endif -} - -#if defined(_EMU_TEMP_TEMPAVG_MASK) -/***************************************************************************//** - * @brief - * Get averaged temperature in degrees Celsius. - * - * @note - * An averaged temperature measurement must first be requested by calling - * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag - * to go high. - * - * @return - * Averaged temperature - ******************************************************************************/ -__STATIC_INLINE float EMU_TemperatureAvgGet(void) -{ - uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK) - >> _EMU_TEMP_TEMPAVG_SHIFT); - return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; -} - -/***************************************************************************//** - * @brief - * Request averaged temperature. - * - * @note - * EMU must be unlocked by calling @ref EMU_Unlock() before this function - * can be called. - * - * @param[in] numSamples - * Number of temperature samples to average - ******************************************************************************/ -__STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples) -{ - BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples); - EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT; -} - -#endif //defined(_EMU_TEMP_TEMPAVG_MASK) -#endif //defined(_EMU_TEMP_TEMP_MASK) - -/** @} (end addtogroup emu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( EMU_PRESENT ) */ -#endif /* EM_EMU_H */ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EMU_H +#define EM_EMU_H + +#include "em_device.h" +#include "sl_status.h" +#if defined(EMU_PRESENT) + +#include +#include "em_bus.h" +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup emu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200) +/** Voltage scaling present */ +#define EMU_VSCALE_PRESENT +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +/** Voltage scaling for EM01 present */ +#define EMU_VSCALE_EM01_PRESENT +#endif +#endif + +#if defined(_EMU_DCDCCTRL_MASK) +/** DC-DC buck converter present */ +#define EMU_SERIES1_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC buck converter present */ +#define EMU_SERIES2_DCDC_BUCK_PRESENT +#endif + +#if defined(_SILICON_LABS_DCDC_FEATURE) \ + && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \ + || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB)) +/** DC-DC boost converter present */ +#define EMU_SERIES2_DCDC_BOOST_PRESENT +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +#if defined(_EMU_EM4CONF_OSC_MASK) +/** EM4 duty oscillator. */ +typedef enum { + /** Select ULFRCO as duty oscillator in EM4. */ + emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, + /** Select LFXO as duty oscillator in EM4. */ + emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, + /** Select LFRCO as duty oscillator in EM4. */ + emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO +} EMU_EM4Osc_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PROBE_MASK) +/** Backup Power Voltage Probe types. */ +typedef enum { + /** Disable voltage probe. */ + emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, + /** Connect probe to VDD_DREG. */ + emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, + /** Connect probe to BU_IN. */ + emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, + /** Connect probe to BU_OUT. */ + emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT +} EMU_Probe_TypeDef; +#endif + +#if defined(_EMU_PWRCONF_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, +} EMU_Resistor_TypeDef; +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain power connection. */ +typedef enum { + /** No connection between main and backup power. */ + emuPower_None = EMU_BUINACT_PWRCON_NONE, + /** Main power and backup power connected through diode, + allowing current from backup to main only. */ + emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, + /** Main power and backup power connected through diode, + allowing current from main to backup only. */ + emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, + /** Main power and backup power connected without diode. */ + emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, +} EMU_Power_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/** Backup Power Domain power connection configuration when not in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE, +} EMU_BUBuInactPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/** Backup Power Domain power connection configuration in backup mode selection. */ +typedef enum { + /** No connection. */ + emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE, + /** Allow power from main to backup. */ + emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU, + /** Allow power from backup to main. */ + emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN, + /** Backup and main power are connected. */ + emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE, +} EMU_BUBuActPwrCon_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/** Backup Power Domain resistor selection. */ +typedef enum { + /** Main power and backup power connected with RES0 series resistance. */ + emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0, + /** Main power and backup power connected with RES1 series resistance. */ + emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1, + /** Main power and backup power connected with RES2 series resistance. */ + emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2, + /** Main power and backup power connected with RES3 series resistance. */ + emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3, +} EMU_BUPwrRes_TypeDef; +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/** Resistance between backup domain power supply and BU_VOUT. */ +typedef enum { + /** BU_VOUT is not connected. */ + emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS, + /** Enable weak switch. */ + emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK, + /** Enable medium switch. */ + emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED, + /** Enable strong switch. */ + emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG, +} EMU_BUVoutRes_TypeDef; +#endif + +/** BOD threshold setting selector, active or inactive mode. */ +typedef enum { + /** Configure BOD threshold for active mode. */ + emuBODMode_Active, + /** Configure BOD threshold for inactive mode. */ + emuBODMode_Inactive, +} EMU_BODMode_TypeDef; + +/** EM4 modes. */ +typedef enum { + /** EM4 Shutoff. */ + emuEM4Shutoff = 0, + /** EM4 Hibernate. */ + emuEM4Hibernate = 1, +} EMU_EM4State_TypeDef; + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/** EM4 Pin Retention Type. */ +typedef enum { + /** No Retention: Pads enter reset state when entering EM4. */ + emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, + /** Retention through EM4: Pads enter reset state when exiting EM4. */ + emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, + /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to + release pins from retention after EM4 wakeup. */ + emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, +} EMU_EM4PinRetention_TypeDef; +#endif + +/** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ +typedef enum { + /** DCDC is connected to DVDD. */ + emuPowerConfig_DcdcToDvdd, +} EMU_PowerConfig_TypeDef; + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC operating modes. */ +typedef enum { + /** DCDC regulator bypass. */ + emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, + /** DCDC low-noise mode. */ + emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, +#if defined(_EMU_DCDCLPEM01CFG_MASK) + /** DCDC low-power mode. */ + emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, +#endif +} EMU_DcdcMode_TypeDef; + +/** DCDC operating modes in EM2 or EM3. */ +typedef enum { + /** DCDC mode is low power. */ + emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER, + /** DCDC mode is according to DCDCMODE field. */ + emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW, +} EMU_DcdcModeEM23_TypeDef; + +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC conduction modes. */ +typedef enum { + /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization + features are available in this mode. */ + emuDcdcConductionMode_ContinuousLN, + /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or + for EFR32 when its radio is not enabled. */ + emuDcdcConductionMode_DiscontinuousLN, +} EMU_DcdcConductionMode_TypeDef; +#endif + +#if defined(_EMU_PWRCTRL_MASK) +/** DCDC to DVDD mode analog peripheral power supply select. */ +typedef enum { + /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ + emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, + /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ + emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD +} EMU_DcdcAnaPeripheralPower_TypeDef; +#endif + +#if defined(_EMU_DCDCMISCCTRL_MASK) +/** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ +typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; + +/** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ +#define emuDcdcLnHighEfficiency -1 + +/** Default reverse current for fast transient response mode (low noise). */ +#define emuDcdcLnFastTransient 160 +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC Low-noise RCO band select. */ +typedef enum { + /** Set RCO to 3MHz. */ + emuDcdcLnRcoBand_3MHz = 0, + /** Set RCO to 4MHz. */ + emuDcdcLnRcoBand_4MHz = 1, + /** Set RCO to 5MHz. */ + emuDcdcLnRcoBand_5MHz = 2, + /** Set RCO to 6MHz. */ + emuDcdcLnRcoBand_6MHz = 3, + /** Set RCO to 7MHz. */ + emuDcdcLnRcoBand_7MHz = 4, + /** Set RCO to 8MHz. */ + emuDcdcLnRcoBand_8MHz = 5, + /** Set RCO to 9MHz. */ + emuDcdcLnRcoBand_9MHz = 6, + /** Set RCO to 10MHz. */ + emuDcdcLnRcoBand_10MHz = 7, +} EMU_DcdcLnRcoBand_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated. */ +#define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz +#define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz +#define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz +#define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz +#define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz +#define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz +#define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz +#define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz +/** @endcond */ + +/** DCDC Low Noise Compensator Control register. */ +typedef enum { + /** DCDC capacitor is 1uF. */ + emuDcdcLnCompCtrl_1u0F, + /** DCDC capacitor is 4.7uF. */ + emuDcdcLnCompCtrl_4u7F, +} EMU_DcdcLnCompCtrl_TypeDef; +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) + +/** DCDC mode. */ +typedef enum { + emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */ + emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */ +} EMU_DcdcMode_TypeDef; +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** VREGIN comparator threshold. */ +typedef enum { + emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */ + emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */ + emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */ + emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */ +} EMU_VreginCmpThreshold_TypeDef; + +/** DCDC Buck Ton max timeout. */ +typedef enum { +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) + emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */ +#else + emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */ + emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */ + emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */ + emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */ + emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */ + emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */ + emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */ + emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */ + emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */ + emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */ + emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */ + emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */ + emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */ + emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */ + emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */ + emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */ + emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */ + emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */ + emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */ + emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */ + emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */ + emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */ + emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */ + emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */ + emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */ + emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */ + emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */ + emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */ + emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */ + emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */ + emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */ + emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */ +#endif +} EMU_DcdcTonMaxTimeout_TypeDef; + +/** DCDC Buck drive speed. */ +typedef enum { + emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcDriveSpeed_TypeDef; + +/** DCDC Buck peak current setting. */ +typedef enum { +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA) + emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA) + emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA) + emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA) + emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA) + emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */ +#endif + emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */ + emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */ + emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */ + emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */ + emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */ + emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */ +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA) + emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA) + emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA) + emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA) + emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */ +#endif +#if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA) + emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */ +#endif +} EMU_DcdcPeakCurrent_TypeDef; +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost drive speed. */ +typedef enum { + emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ + emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */ +} EMU_DcdcBoostDriveSpeed_TypeDef; + +/** DCDC Boost EM01 peak current setting. */ +typedef enum { + emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */ + emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */ + emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */ + emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */ + emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */ + emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */ + emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */ + emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */ + emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */ + emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */ +} EMU_DcdcBoostEM01PeakCurrent_TypeDef; + +/** DCDC Boost Toff max timeout */ +typedef enum { + emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */ + emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */ + emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */ + emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */ + emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */ + emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */ + emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */ + emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */ +} EMU_DcdcBoostToffMaxTimeout_TypeDef; + +/** DCDC Boost peak current detection maximum timeout */ +typedef enum { + emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */ + emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */ + emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */ + emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */ + emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */ + emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */ + emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */ + emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */ +} EMU_DcdcBoostTonMaxTimeout_TypeDef; + +/** DCDC Boost EM23 peak current setting. */ +typedef enum { + emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */ +} EMU_DcdcBoostEM23PeakCurrent_TypeDef; +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */ + +#if defined(EMU_STATUS_VMONRDY) +/** VMON channels. */ +typedef enum { + emuVmonChannel_AVDD, + emuVmonChannel_ALTAVDD, + emuVmonChannel_DVDD, + emuVmonChannel_IOVDD0, +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + emuVmonChannel_IOVDD1, +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + emuVmonChannel_BUVDD, +#endif +} EMU_VmonChannel_TypeDef; +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/** Bias mode configurations. */ +typedef enum { + emuBiasMode_1KHz, + emuBiasMode_4KHz, + emuBiasMode_Continuous +} EMU_BiasMode_TypeDef; +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** Supported EM0/1 Voltage Scaling Levels. */ +typedef enum { + /** High-performance voltage level. HF clock can be set to any frequency. */ + emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, + /** Low-power optimized voltage level. HF clock must be limited + to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. + EM0/1 voltage scaling is applied when core clock frequency is + changed from @ref cmu or when calling @ref EMU_EM01Init() when HF + clock is already below the limit. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + /** Minimum VSCALE level in EM0/1 is VSCALE1. */ + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1, +#else + emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, +#endif +} EMU_VScaleEM01_TypeDef; +#endif + +#if defined(EMU_VSCALE_PRESENT) +/** Supported EM2/3 Voltage Scaling Levels. */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ + emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, +} EMU_VScaleEM23_TypeDef; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Supported EM4H Voltage Scaling Levels */ +typedef enum { + /** Fast-wakeup voltage level. */ + emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, + /** Low-power optimized voltage level. Using this voltage level in EM4H + adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled + up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ + emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, +} EMU_VScaleEM4H_TypeDef; +#endif + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/** Peripheral EM2 and 3 retention control. */ +typedef enum { +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */ +#endif + emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */ +#endif + emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */ +#endif + emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */ + emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */ + emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */ +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */ +#endif + emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */ + emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */ + emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */ +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */ + emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */ +#endif + emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */ + + emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK + | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */ + emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK +#endif + | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK +#if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK + | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK +#endif +#if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK) + | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */ +#endif + | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, + emuPeripheralRetention_ALL = emuPeripheralRetention_D1 + | emuPeripheralRetention_D2 +#if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK) + | emuPeripheralRetention_WDOG1 +#endif + | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */ +} EMU_PeripheralRetention_TypeDef; +#endif + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/** Number of samples to use for temperature averaging. */ +typedef enum { + /** 16 samples used for temperature averaging. */ + emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16, + /** 64 samples used for temperature averaging. */ + emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64, +} EMU_TempAvgNum_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/** EM0 and 1 initialization structure. Voltage scaling is applied when + the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance + is always enabled. */ +typedef struct { + bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */ +} EMU_EM01Init_TypeDef; + +/** Default initialization of EM0 and 1 configuration. */ +#define EMU_EM01INIT_DEFAULT \ + { \ + false /* Do not scale down in EM0/1.*/ \ + } +#endif + +/** EM2 and 3 initialization structure. */ +typedef struct { + bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */ +#if defined(EMU_VSCALE_PRESENT) + EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */ +#endif +} EMU_EM23Init_TypeDef; + +/** Default initialization of EM2 and 3 configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \ + } +#else +#define EMU_EM23INIT_DEFAULT \ + { \ + false, /* Reduced voltage regulator drive strength in EM2/3.*/ \ + } +#endif + +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/** EM4 initialization structure. */ +typedef struct { +#if defined(_EMU_EM4CONF_MASK) + /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */ + bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */ + bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */ + EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */ + bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */ + bool vreg; /**< Enable EM4 voltage regulator. */ +#elif defined(_EMU_EM4CTRL_MASK) + /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */ + bool retainLfxo; /**< Disable LFXO upon EM4 entry. */ + bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */ + bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */ + EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */ + EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */ +#endif +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */ +#endif +} EMU_EM4Init_TypeDef; +#endif + +#if defined(_EMU_EM4CONF_MASK) +/** Default initialization of EM4 configuration (Series 0). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Do not lock configuration after it's been set. */ \ + false, /* No reset will be asserted due to BOD in EM4. */ \ + emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \ + true, /* Wake up on EM4 BURTC interrupt. */ \ + true, /* Enable VREG. */ \ + } + +#elif defined(_EMU_CTRL_EM4HVSCALE_MASK) +/** Default initialization of EM4 configuration (Series 1 with VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \ + } + +#elif defined(_EMU_EM4CTRL_MASK) +/** Default initialization of EM4 configuration (Series 1 without VSCALE). */ +#define EMU_EM4INIT_DEFAULT \ + { \ + false, /* Retain LFXO configuration upon EM4 entry. */ \ + false, /* Retain LFRCO configuration upon EM4 entry. */ \ + false, /* Retain ULFRCO configuration upon EM4 entry. */ \ + emuEM4Shutoff, /* Use EM4 shutoff state. */ \ + emuPinRetentionDisable, /* Do not retain pins in EM4. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/** Backup Power Domain Initialization structure. */ +typedef struct { + /* Backup Power Domain power configuration. */ + + /** Voltage probe select, selects ADC voltage. */ + EMU_Probe_TypeDef probe; + /** Enable BOD calibration mode. */ + bool bodCal; + /** Enable BU_STAT status pin for active BU mode. */ + bool statusPinEnable; + + /* Backup Power Domain connection configuration. */ + /** Power domain resistor. */ + EMU_Resistor_TypeDef resistor; + /** BU_VOUT strong enable. */ + bool voutStrong; + /** BU_VOUT medium enable. */ + bool voutMed; + /** BU_VOUT weak enable. */ + bool voutWeak; + /** Power connection, when not in Backup Mode. */ + EMU_Power_TypeDef inactivePower; + /** Power connection, when in Backup Mode. */ + EMU_Power_TypeDef activePower; + /** Enable backup power domain, and release reset, enable BU_VIN pin. */ + bool enable; +} EMU_BUPDInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUPDINIT_DEFAULT \ + { \ + emuProbe_Disable, /* Do not enable voltage probe. */ \ + false, /* Disable BOD calibration mode. */ \ + false, /* Disable BU_STAT pin for backup mode indication. */ \ + \ + emuRes_Res0, /* RES0 series resistance between main and backup power. */ \ + false, /* Do not enable strong switch. */ \ + false, /* Do not enable medium switch. */ \ + false, /* Do not enable weak switch. */ \ + \ + emuPower_None, /* No connection between main and backup power. (inactive mode) */ \ + emuPower_None, /* No connection between main and backup power. (active mode) */ \ + true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \ + } +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/** Backup Power Domain Initialization structure. */ +typedef struct { + bool disMaxComp; /**< Disable MAIN-BU Comparator. */ + EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */ + EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */ + EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */ + EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */ + bool buVinProbeEn; /**< Enable BU_VIN probing. */ + bool staEn; /**< Enable backup mode status export. */ + bool enable; /**< Enable backup power domain. */ +} EMU_BUInit_TypeDef; + +/** Default Backup Power Domain configuration. */ +#define EMU_BUINIT_DEFAULT \ + { \ + false, /* MAIN-BU Comparator is not disabled */ \ + emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \ + emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \ + emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \ + emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \ + false, /* BU_VIN probe is disabled */ \ + false, /* Status export is disabled */ \ + true /* Enable backup mode */ \ + } +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/** DCDC Boost regulator initialization structure. */ +typedef struct { + EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ + bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +} EMU_DCDCBoostInit_TypeDef; + +/** Default DCDC Boost initialization. */ +#define EMU_DCDCBOOSTINIT_DEFAULT \ + { \ + emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< disable DCDC boost mode with BOOST_EN=0 */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \ + emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \ + } +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/** DCDC regulator initialization structure. */ +typedef struct { + EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */ + EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */ + EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */ +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + bool dcmOnlyEn; /**< DCM only mode enable. */ +#endif + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */ + EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */ + EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC Buck initialization. */ +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + true, /**< Enable DCM only mode. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuDcdcMode_Regulation, /**< DCDC regulator on. */ \ + emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \ + emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \ + emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \ + emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \ + emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \ + } +#endif +#endif /* SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** DCDC initialization structure. */ +typedef struct { + EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. + @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ + EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */ + uint16_t mVout; /**< Target output voltage (mV). */ + uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA). + This estimate is also used for EM1 optimization; + if EM1 current is expected to be higher than EM0, + then this parameter should hold the higher EM1 current. */ + uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). + This estimate is also used for EM3 and 4 optimization; + if EM3 or 4 current is expected to be higher than EM2, + then this parameter should hold the higher EM3 or 4 current. */ + uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). + This can be set to the maximum for the power source, + for example the maximum for a battery. */ + EMU_DcdcAnaPeripheralPower_TypeDef + anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */ + EMU_DcdcLnReverseCurrentControl_TypeDef + reverseCurrentControl; /**< Low-noise reverse current control. + NOTE: this parameter uses special encoding: + >= 0 is forced CCM mode where the parameter is used as the + reverse current threshold in mA. + -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */ + EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ +} EMU_DCDCInit_TypeDef; + +/** Default DCDC initialization. */ +#if defined(_EFM_DEVICE) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#elif defined(WGM160PX22KGA2) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 5, /* Nominal EM0/1 load current of less than 5mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \ + emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif + +#else /* EFR32 device. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \ + } +#else +#define EMU_DCDCINIT_DEFAULT \ + { \ + emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \ + emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \ + 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \ + 15, /* Nominal EM0/1 load current of less than 15mA. */ \ + 10, /* Nominal EM2/3/4 load current less than 10uA. */ \ + 200, /* Maximum average current of 200mA + (assume strong battery or other power source). */ \ + emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \ + 160, /* Maximum reverse current of 160mA. */ \ + emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \ + } +#endif +#endif +#endif + +#if defined(EMU_STATUS_VMONRDY) +/** VMON initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ + bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */ +} EMU_VmonInit_TypeDef; + +/** Default VMON initialization structure. */ +#define EMU_VMONINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true, /* Enable VMON channel. */ \ + false /* Do not disable IO0 retention */ \ + } + +/** VMON Hysteresis initialization structure. */ +typedef struct { + EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */ + int riseThreshold; /**< Rising threshold (mV). */ + int fallThreshold; /**< Falling threshold (mV). */ + bool riseWakeup; /**< Wake up from EM4H on rising edge. */ + bool fallWakeup; /**< Wake up from EM4H on falling edge. */ + bool enable; /**< Enable VMON channel. */ +} EMU_VmonHystInit_TypeDef; + +/** Default VMON Hysteresis initialization structure. */ +#define EMU_VMONHYSTINIT_DEFAULT \ + { \ + emuVmonChannel_AVDD, /* AVDD VMON channel. */ \ + 3200, /* 3.2 V rise threshold. */ \ + 3200, /* 3.2 V fall threshold. */ \ + false, /* Do not wake from EM4H on rising edge. */ \ + false, /* Do not wake from EM4H on falling edge. */ \ + true /* Enable VMON channel. */ \ + } +#endif /* EMU_STATUS_VMONRDY */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); +#endif +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); +void EMU_EM23PresleepHook(void); +void EMU_EM23PostsleepHook(void); +void EMU_EFPEM23PresleepHook(void); +void EMU_EFPEM23PostsleepHook(void); +void EMU_EnterEM2(bool restore); +void EMU_EnterEM3(bool restore); +void EMU_Save(void); +void EMU_Restore(void); +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); +#endif +void EMU_EM4PresleepHook(void); +void EMU_EFPEM4PresleepHook(void); +void EMU_EnterEM4(void); +void EMU_EnterEM4Wait(void); +#if defined(_EMU_EM4CTRL_MASK) +void EMU_EnterEM4H(void); +void EMU_EnterEM4S(void); +#endif +void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1; +void EMU_RamPowerDown(uint32_t start, uint32_t end); +void EMU_RamPowerUp(void); +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); +#endif +void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1; +#if defined(EMU_VSCALE_EM01_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_2) +void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage); +#endif +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit); +#endif +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +void EMU_BUDisMaxCompSet(bool disableMainBuComparator); +#endif +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon); +#endif +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon); +#endif +#if defined(_EMU_BUCTRL_PWRRES_MASK) +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes); +#endif +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel); +#endif +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +void EMU_BUBuVinProbeEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_STATEN_MASK) +void EMU_BUStatEnSet(bool enable); +#endif +#if defined(_EMU_BUCTRL_EN_MASK) +void EMU_BUEnableSet(bool enable); +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +void EMU_DCDCUpdatedHook(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit); +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01); +void EMU_BoostExternalShutdownEnable(bool enable); +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); +bool EMU_DCDCPowerOff(void); +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01); +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value); +#endif +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value); +#endif +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23); +#endif +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); +bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA); +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); +#endif +#if defined(_EMU_TEMP_TEMP_MASK) +float EMU_TemperatureGet(void); +#endif +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +void EMU_EFPDirectModeEnable(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +void EMU_EFPDriveDecoupleSet(bool enable); +#endif +#if defined(EMU_CTRL_EFPDRVDVDD) +void EMU_EFPDriveDvddSet(bool enable); +#endif + +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Lock DCDC registers in order to protect them against unintended + * modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCLock(void) +{ + DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Unlock the DCDC so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCUnlock(void) +{ + DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY; +} +#endif + +#if defined(_DCDC_SYNCBUSY_MASK) +/***************************************************************************//** + * @brief + * Wait for the DCDC to complete all synchronization of register changes. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void EMU_DCDCSync(uint32_t mask) +{ + while (0UL != (DCDC->SYNCBUSY & mask)) { + /* Wait for previous synchronization to finish */ + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Check status of the internal LDO regulator. + * + * @return + * Return true if the regulator is on, false if regulator is off. + ******************************************************************************/ +__STATIC_INLINE bool EMU_LDOStatusGet(void) +{ + if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) { + return true; + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Enter energy mode 1 (EM1). + * + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + ******************************************************************************/ +__STATIC_INLINE void EMU_EnterEM1(void) +{ + /* Enter sleep mode. */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); +} + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Wait for voltage scaling to complete. + ******************************************************************************/ +__STATIC_INLINE void EMU_VScaleWait(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip waiting if the LDO regulator is turned off. */ + return; + } +#endif + + while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) { + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Get current voltage scaling level. + * + * @return + * Current voltage scaling level. + ******************************************************************************/ +__STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) +{ + EMU_VScaleWait(); + return (EMU_VScaleEM01_TypeDef)((uint32_t) + ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT)); +} +#endif + +#if defined(_EMU_STATUS_VMONRDY_MASK) +/***************************************************************************//** + * @brief + * Get the status of the voltage monitor (VMON). + * + * @return + * Status of the VMON. True if all the enabled channels are ready, false if + * one or more of the enabled channels are not ready. + ******************************************************************************/ +__STATIC_INLINE bool EMU_VmonStatusGet(void) +{ + return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U; +} +#endif /* _EMU_STATUS_VMONRDY_MASK */ + +#if defined(_EMU_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending EMU interrupts. + * + * @param[in] flags + * Pending EMU interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntClear(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_CLR = flags; +#else + EMU->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to disable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntDisable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_CLR = flags; +#else + EMU->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more EMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * @ref EMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * EMU interrupt sources to enable. Use one or more valid + * interrupt flags for the EMU module (EMU_IEN_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntEnable(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IEN_SET = flags; +#else + EMU->IEN |= flags; +#endif +} + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Disable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to disable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags) +{ + EMU->EFPIEN_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more EFP interrupts. + * + * @param[in] flags + * EFP interrupt sources to enable. Use one or more valid + * interrupt flags for the EFP module (EFPIENnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags) +{ + EMU->EFPIEN_SET = flags; +} + +/***************************************************************************//** + * @brief + * Get pending EMU EFP interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU EFP interrupt sources pending. . + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGet(void) +{ + return EMU->EFPIF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU EFP interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU EFP interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_EFPIEN and + * - the pending interrupt flags EMU_EFPIF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->EFPIEN; + return EMU->EFPIF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU EFP interrupts. + * + * @param[in] flags + * EMU EFP interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntSet(uint32_t flags) +{ + EMU->EFPIF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending EMU EFP interrupts. + * + * @param[in] flags + * Pending EMU EFP interrupt sources to clear. Use one or more valid + * interrupt flags for the EMU EFP module. + ******************************************************************************/ +__STATIC_INLINE void EMU_EFPIntClear(uint32_t flags) +{ + EMU->EFPIF_CLR = flags; +} +#endif + +/***************************************************************************//** + * @brief + * Get pending EMU interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * EMU interrupt sources pending. Returns one or more valid + * interrupt flags for the EMU module (EMU_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGet(void) +{ + return EMU->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending EMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled EMU interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in EMU_IEN and + * - the pending interrupt flags EMU_IF. + ******************************************************************************/ +__STATIC_INLINE uint32_t EMU_IntGetEnabled(void) +{ + uint32_t ien; + + ien = EMU->IEN; + return EMU->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending EMU interrupts. + * + * @param[in] flags + * EMU interrupt sources to set to pending. Use one or more valid + * interrupt flags for the EMU module (EMU_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void EMU_IntSet(uint32_t flags) +{ +#if defined(EMU_HAS_SET_CLEAR) + EMU->IF_SET = flags; +#else + EMU->IFS = flags; +#endif +} +#endif /* _EMU_IF_MASK */ + +#if defined(_EMU_EM4CONF_LOCKCONF_MASK) +/***************************************************************************//** + * @brief + * Enable or disable EM4 lock configuration. + * @param[in] enable + * If true, locks down EM4 configuration. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM4Lock(bool enable) +{ + BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); +} +#endif + +#if defined(_EMU_STATUS_BURDY_MASK) +/***************************************************************************//** + * @brief + * Halts until backup power functionality is ready. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUReady(void) +{ + while (!(EMU->STATUS & EMU_STATUS_BURDY)) + ; +} +#endif + +#if defined(_EMU_ROUTE_BUVINPEN_MASK) +/***************************************************************************//** + * @brief + * Disable BU_VIN support. + * @param[in] enable + * If true, enables BU_VIN input pin support, if false disables it. + ******************************************************************************/ +__STATIC_INLINE void EMU_BUPinEnable(bool enable) +{ + BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); +} +#endif + +/***************************************************************************//** + * @brief + * Lock EMU registers in order to protect them against unintended + * modification. + * + * @note + * If locking EMU registers, they must be unlocked prior to using any + * EMU API functions modifying EMU registers, excluding interrupt control + * and regulator control if the architecture has a EMU_PWRCTRL register. + * An exception to this is the energy mode entering API (EMU_EnterEMn()), + * which can be used when the EMU registers are locked. + ******************************************************************************/ +__STATIC_INLINE void EMU_Lock(void) +{ + EMU->LOCK = 0x0; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU so that writing to locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_Unlock(void) +{ + EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; +} + +#if defined(_EMU_PWRLOCK_MASK) +/***************************************************************************//** + * @brief + * Lock the EMU regulator control registers in order to protect against + * unintended modification. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerLock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; +} + +/***************************************************************************//** + * @brief + * Unlock the EMU power control registers so that writing to + * locked registers again is possible. + ******************************************************************************/ +__STATIC_INLINE void EMU_PowerUnlock(void) +{ + EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; +} +#endif + +#if defined(_EMU_CTRL_EM2BLOCK_MASK) +/***************************************************************************//** + * @brief + * Block entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2Block(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U); +} + +/***************************************************************************//** + * @brief + * Unblock entering EM2 or higher number energy modes. + ******************************************************************************/ +__STATIC_INLINE void EMU_EM2UnBlock(void) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U); +} +#endif + +#if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/***************************************************************************//** + * @brief + * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained + * through EM4 entry and wakeup. The pin state is released by calling this function. + * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), + * and when initialization is done, this function can release pins and return control + * to the peripherals or GPIO. + ******************************************************************************/ +__STATIC_INLINE void EMU_UnlatchPinRetention(void) +{ + EMU->CMD = EMU_CMD_EM4UNLATCH; +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/** Zero degrees Celcius in Kelvin */ +#define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f) +/***************************************************************************//** + * @brief + * Temperature measurement ready status + * + * @return + * True if temperature measurement is ready + ******************************************************************************/ +__STATIC_INLINE bool EMU_TemperatureReady(void) +{ +#if defined(EMU_STATUS_FIRSTTEMPDONE) + return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE)); +#else + return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u); +#endif +} + +#if defined(_EMU_TEMP_TEMPAVG_MASK) +/***************************************************************************//** + * @brief + * Get averaged temperature in degrees Celsius. + * + * @note + * An averaged temperature measurement must first be requested by calling + * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag + * to go high. + * + * @return + * Averaged temperature + ******************************************************************************/ +__STATIC_INLINE float EMU_TemperatureAvgGet(void) +{ + uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK) + >> _EMU_TEMP_TEMPAVG_SHIFT); + return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +} + +/***************************************************************************//** + * @brief + * Request averaged temperature. + * + * @note + * EMU must be unlocked by calling @ref EMU_Unlock() before this function + * can be called. + * + * @param[in] numSamples + * Number of temperature samples to average + ******************************************************************************/ +__STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples) +{ + BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples); + EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT; +} + +#endif //defined(_EMU_TEMP_TEMPAVG_MASK) +#endif //defined(_EMU_TEMP_TEMP_MASK) + +/** @} (end addtogroup emu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( EMU_PRESENT ) */ +#endif /* EM_EMU_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h index b0c6a3b..ecc5589 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart.h @@ -1,1223 +1,1223 @@ -/***************************************************************************//** - * @file - * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EUSART_H -#define EM_EUSART_H -#include "em_device.h" -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) -#include "sl_enum.h" -#include "em_eusart_compat.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* *INDENT-OFF* */ -// ***************************************************************************** -/// @addtogroup eusart EUSART - Extended USART -/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter -/// -/// @li @ref eusart_intro -/// @li @ref eusart_example -/// @li @ref eusart_em2 -/// -///@n @section eusart_intro Introduction -/// This module contains functions to control the Enhanced Universal Synchronous -/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon -/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, -/// therefore, be connected to an external transceiver to communicate with -/// another host using the serial link. -/// -/// It supports full duplex asynchronous UART communication as well as RS-485, -/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, -/// and IrDA devices. -/// -/// EUSART has a wide selection of operating modes, frame formats, and baud rates. -/// All features are supported through the API of this module. -/// -/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers -/// provide full support for DMA and more. -/// -///@n @section eusart_example Example -/// -/// EUSART Async TX example: -/// @code{.c} -/// { -/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; -/// -/// // Configure the clocks. -/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); -/// CMU_ClockEnable(cmuClock_EUSART0CLK, true); -/// // Initialize the EUSART -/// EUSART_UartInitHf(EUSART0, &init); -/// EUSART_Tx(EUSART0, data); -/// } -/// -/// @endcode -/// -/// EUSART Sync SPI Transaction example: -/// @code{.c} -/// { -/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF; -/// -/// // Configure the clocks. -/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); -/// CMU_ClockEnable(cmuClock_EUSART1, true); -/// CMU_ClockEnable(cmuClock_GPIO, true); -/// -/// //Configure the SPI ports -/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0); -/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0); -/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0); -/// -/// // Connect EUSART to ports -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT) -/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT) -/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) -/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); -/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN; -/// -/// // Initialize the EUSART -/// EUSART_SpiInit(EUSART1, &init_master); -/// EUSART_Spi_TxRx(EUSART1, data); -/// } -/// -/// @endcode -///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances -/// -/// @note EUSART instances located in the PD1 power domain are non EM2-capable. -/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used -/// to determine whether or not a EUSART instance is EM2-Capable. -/// -/// Follow theses steps when entering in EM2: -/// -# Wait for the current transaction to complete with TXCIF interrupt -/// -# Disable TX and RX using TXDIS and RXDIS cmd -/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low -/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low -/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled -/// -# Enter EM2 -/// -/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO -/// (SCLKPEN and CSPEN) must be re-enabled. For example: -/// -/// @code{.c} -/// { -/// // Enable TX and RX -/// EUSART_Enable(EUSART0, eusartEnable); -/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN, -/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, -/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); -/// } -/// @endcode -/// -/// @{ -// ***************************************************************************** -/* *INDENT-ON* */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Define EUSART FIFO Depth information */ -#if !defined(EUSART_FIFO_DEPTH) -#if defined(EUART_PRESENT) -#define EUSART0_FIFO_DEPTH 4 -#elif defined(EUSART_PRESENT) -#define EUSART0_FIFO_DEPTH 16 -#endif /* EUART_PRESENT */ -#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH -#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH - -#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \ - : ((n) == 1) ? EUSART1_FIFO_DEPTH \ - : ((n) == 2) ? EUSART2_FIFO_DEPTH \ - : ((n) == 3) ? EUSART3_FIFO_DEPTH \ - : ((n) == 4) ? EUSART4_FIFO_DEPTH \ - : 0x0UL) -#endif /* EUSART_FIFO_DEPTH */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/// Enable selection. -typedef enum { - /// Disable the peripheral. - eusartDisable = 0x0, - - /// Enable receiver only, transmitter disabled. - eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS), - - /// Enable transmitter only, receiver disabled. - eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS), - - /// Enable both receiver and transmitter. - eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN) -} EUSART_Enable_TypeDef; - -/// Data bit selection. -typedef enum { - eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits. - eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits. - eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits. -#if defined(EUSART_PRESENT) - eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only. - eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only. - eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only. - eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only. - eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only. - eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only. - eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only. -#endif -} EUSART_Databits_TypeDef; - -/// Parity selection. -typedef enum { - eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity. - eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity. - eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity. -} EUSART_Parity_TypeDef; - -/// Stop bits selection. -typedef enum { - eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits. - eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits. - eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits. - eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits. -} EUSART_Stopbits_TypeDef; - -/// Oversampling selection, used for asynchronous operation. -typedef enum { - eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal). - eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling. - eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling. - eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling. - eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled. -} EUSART_OVS_TypeDef; - -/// HW flow control config. -typedef enum { - eusartHwFlowControlNone = 0, ///< No HW Flow Control. - eusartHwFlowControlCts, ///< CTS HW Flow Control. - eusartHwFlowControlRts, ///< RTS HW Flow Control. - eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control. -} EUSART_HwFlowControl_TypeDef; - -/// Loopback enable. -typedef enum { - eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback. - eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback. -} EUSART_LoopbackEnable_TypeDef; - -/// Majority vote enable. -typedef enum { - eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes. - eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes. -} EUSART_MajorityVote_TypeDef; - -/// Block reception enable. -typedef enum { - eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded. - eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO. -} EUSART_BlockRx_TypeDef; - -/// TX output tristate enable. -typedef enum { - eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output. - eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output. -} EUSART_TristateTx_TypeDef; - -/// IrDA filter enable. -typedef enum { - eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator. - eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator. -} EUSART_IrDARxFilterEnable_TypeDef; - -/// Pulse width selection for IrDA mode. -typedef enum { - /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8 - eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE, - - /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8 - eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO, - - /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8 - eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE, - - /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8 - eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR -} EUSART_IrDAPulseWidth_Typedef; - -/// PRS trigger enable. -typedef enum { - /// Disable trigger on both receiver and transmitter. - eusartPrsTriggerDisable = 0x0, - - /// Enable receive trigger only, transmit disabled. - eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN, - - /// Enable transmit trigger only, receive disabled. - eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN, - - /// Enable trigger on both receive and transmit. - eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN) -} EUSART_PrsTriggerEnable_TypeDef; - -/// PRS Channel type. -typedef uint8_t EUSART_PrsChannel_TypeDef; - -/// IO polarity selection. -typedef enum { - /// Disable inversion on both RX and TX signals. - eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE), - - /// Invert RX signal, before receiver. - eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE, - - /// Invert TX signal, after transmitter. - eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE, - - /// Enable trigger on both receive and transmit. - eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) -} EUSART_InvertIO_TypeDef; - -/// Auto TX delay transmission. -SL_ENUM(EUSART_AutoTxDelay_TypeDef) { - /// Frames are transmitted immediately. - eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE, - - /// Transmission of new frames is delayed by a single bit period. - eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE, - - /// Transmission of new frames is delayed by a two bit periods. - eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE, - - /// Transmission of new frames is delayed by a three bit periods. - eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE -}; - -/// RX FIFO Interrupt ans Status Watermark. -typedef enum { - eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME, - eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES, - eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES, - eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES, -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES, - eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES, - eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES, - eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES, - eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES, - eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES, - eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES, - eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES, - eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES, - eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES, - eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES, - eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES -#endif -} EUSART_RxFifoWatermark_TypeDef; - -/// TX FIFO Interrupt and Status Watermark. -typedef enum { - eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME, - eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES, - eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES, - eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES, -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES, - eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES, - eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES, - eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES, - eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES, - eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES, - eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES, - eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES, - eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES, - eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES, - eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES, - eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES -#endif -} EUSART_TxFifoWatermark_TypeDef; - -#if defined(EUSART_PRESENT) -/// Clock polarity/phase mode. -typedef enum { - /// Clock idle low, sample on rising edge. - eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING, - - /// Clock idle low, sample on falling edge. - eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING, - - /// Clock idle high, sample on falling edge. - eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING, - - /// Clock idle high, sample on rising edge. - eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING -} EUSART_ClockMode_TypeDef; - -/// Chip select polarity. -typedef enum { - /// Chip select active low. - eusartCsActiveLow = EUSART_CFG2_CSINV_AL, - - /// Chip select active high. - eusartCsActiveHigh = EUSART_CFG2_CSINV_AH, -} EUSART_CsPolarity_TypeDef; - -#if defined(EUSART_DALICFG_DALIEN) -/// DALI TX databits (8-32). -typedef enum { - eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits. - eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits. - eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits. - eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. - eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits. - eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. - eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. - eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. - eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. - eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. - eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. - eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. - eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits. - eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. - eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. - eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. - eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. - eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. - eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. - eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. - eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. - eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. - eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits. - eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. - eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. -} EUSART_DaliTxDatabits_TypeDef; - -/// DALI RX databits (8-32). -typedef enum { - eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits. - eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits. - eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits. - eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. - eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits. - eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. - eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. - eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. - eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. - eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. - eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. - eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. - eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits. - eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. - eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. - eusartDaliRxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. - eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. - eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. - eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. - eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. - eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. - eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. - eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits. - eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. - eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. -} EUSART_DaliRxDatabits_TypeDef; -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ -/// Advanced initialization structure. -typedef struct { - /// Hardware flow control mode. - EUSART_HwFlowControl_TypeDef hwFlowControl; - - /// Enable the collision Detection feature. - /// Internal (setting loopbackEnable) or external loopback must be done to use this feature. - bool collisionDetectEnable; - - /// If true, data will be send with most significant bit first. - bool msbFirst; - - /// Enable inversion of RX and/or TX signals. - EUSART_InvertIO_TypeDef invertIO; - - /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. - bool dmaWakeUpOnRx; - - /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation. - bool dmaWakeUpOnTx; - - /// Enable DMA requests blocking while framing or parity errors. - bool dmaHaltOnError; - - /// Start frame that will enable RX operation. 0x00 Disable this feature. - uint8_t startFrame; - - /// Enable automatic tristating of transmistter output when there is nothing to transmit. - bool txAutoTristate; - - /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. - /// The configured RX GPIO signal won't be routed to the EUSART receiver. - bool prsRxEnable; - - /// PRS Channel used to transmit data from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsRxChannel; - - /// Enable Multiprocessor mode. Address and data filtering using the 9th bit. - bool multiProcessorEnable; - - /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise. - bool multiProcessorAddressBitHigh; - - /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed. - EUSART_AutoTxDelay_TypeDef autoTxDelay; - - /// Interrupt and status level of the Receive FIFO. - EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; - - /// Interrupt and status level of the Transmit FIFO. - EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; -} EUSART_AdvancedInit_TypeDef; - -/// Initialization structure. -typedef struct { - /// Specifies whether TX and/or RX will be enabled when initialization completes. - EUSART_Enable_TypeDef enable; - - /// EUSART reference clock assumed when configuring baud rate setup. Set - /// to 0 if using currently configured reference clock. - uint32_t refFreq; - - /// Desired baud rate. If set to 0, Auto Baud feature is enabled and - /// the EUSART will wait for (0x55) frame to detect the Baudrate. - uint32_t baudrate; - - /// Oversampling used. - EUSART_OVS_TypeDef oversampling; - - /// Number of data bits in frame. - EUSART_Databits_TypeDef databits; - - /// Parity mode to use. - EUSART_Parity_TypeDef parity; - - /// Number of stop bits to use. - EUSART_Stopbits_TypeDef stopbits; - - /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes. - EUSART_MajorityVote_TypeDef majorityVote; - - /// Enable Loop Back configuration. - EUSART_LoopbackEnable_TypeDef loopbackEnable; - - /// Advanced initialization structure pointer. It can be NULL. - EUSART_AdvancedInit_TypeDef *advancedSettings; -} EUSART_UartInit_TypeDef; - -/// IrDA Initialization structure. -typedef struct { - /// General EUSART initialization structure. - EUSART_UartInit_TypeDef init; - - /// Enable the IrDA low frequency mode. Only RX operation are enabled. - bool irDALowFrequencyEnable; - - /// Set to enable filter on IrDA demodulator. - EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable; - - /// Configure the pulse width generated by the IrDA modulator as a fraction - /// of the configured EUSART bit period. - EUSART_IrDAPulseWidth_Typedef irDAPulseWidth; -} EUSART_IrDAInit_TypeDef; - -/// PRS Trigger initialization structure. -typedef struct { - /// PRS to EUSART trigger mode. - EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable; - - /// PRS channel to be used to trigger auto transmission. - EUSART_PrsChannel_TypeDef prs_trigger_channel; -} EUSART_PrsTriggerInit_TypeDef; - -#if defined(EUSART_PRESENT) -/// SPI Advanced initialization structure. -typedef struct { - /// Chip select polarity - EUSART_CsPolarity_TypeDef csPolarity; - - /// Enable inversion of RX and/or TX signals. - EUSART_InvertIO_TypeDef invertIO; - - /// Enable automatic chip select. CS is managed by the peripheral. - bool autoCsEnable; - - /// If true, data will be send with most significant bit first. - bool msbFirst; - - /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoCsSetupTime; - - /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoCsHoldTime; - - /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle). - uint8_t autoInterFrameTime; - - /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full. - /// Generates underflow interrupt if the TX FIFO is empty. - bool autoTxEnable; - - /// Default transmitted data when the TXFIFO is empty. - uint16_t defaultTxData; - - /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. - /// Only applicable to EM2 (low frequency) capable EUSART instances. - bool dmaWakeUpOnRx; - - /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. - /// The configured RX GPIO signal won't be routed to the EUSART receiver. - bool prsRxEnable; - - /// PRS Channel used to transmit data from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsRxChannel; - - /// Enable EUSART capability to use a PRS channel as an input SPI Clock. - /// Slave mode only. - bool prsClockEnable; - - /// PRS Channel used to transmit SCLK from PRS to the EUSART. - EUSART_PrsChannel_TypeDef prsClockChannel; - - /// Interrupt and status level of the Receive FIFO. - EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; - - /// Interrupt and status level of the Receive FIFO. - EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; - - /// Force load the first FIFO value. - bool forceLoad; - - /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error. - uint8_t setupWindow; -} EUSART_SpiAdvancedInit_TypeDef; - -/// SPI Initialization structure. -typedef struct { - /// Specifies whether TX and/or RX will be enabled when initialization completes. - EUSART_Enable_TypeDef enable; - - /// EUSART reference clock assumed when configuring baud rate setup. Set - /// to 0 if using currently configured reference clock. - uint32_t refFreq; - - /// Desired bit rate in Hz. - /// Depending on EUSART instance clock, not all bitrates - /// are achievable as the divider is limited to 255. - uint32_t bitRate; - - /// Number of data bits in frame. - EUSART_Databits_TypeDef databits; - - /// Select to operate in master or slave mode. - bool master; - - /// Clock polarity/phase mode. - EUSART_ClockMode_TypeDef clockMode; - - /// Enable Loop Back configuration. - EUSART_LoopbackEnable_TypeDef loopbackEnable; - - /// Advanced initialization structure pointer. It can be NULL. - EUSART_SpiAdvancedInit_TypeDef *advancedSettings; -} EUSART_SpiInit_TypeDef; -#endif /* EUSART_PRESENT */ - -/// DALI Initialization structure. -typedef struct { - /// General EUSART initialization structure. - EUSART_UartInit_TypeDef init; - - /// Enable the DALI low frequency mode. - bool daliLowFrequencyEnable; - -#if defined(EUSART_DALICFG_DALIEN) - /// Number of TX data bits in frame. - EUSART_DaliTxDatabits_TypeDef TXdatabits; - /// Number of RX data bits in frame. - EUSART_DaliRxDatabits_TypeDef RXdatabits; -#endif -} EUSART_DaliInit_TypeDef; - -/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock. -#define EUSART_UART_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 115200, /* 115200 bits/s. */ \ - eusartOVS16, /* Oversampling x16. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteEnable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default start frame configuration, i.e. feature disabled. -#define EUSART_DEFAULT_START_FRAME 0x00u - -/// Default configuration for EUSART advanced initialization structure. -#define EUSART_ADVANCED_INIT_DEFAULT \ - { \ - eusartHwFlowControlNone, /* Flow control disabled. */ \ - false, /* Collision detection disabled. */ \ - false, /* Data is sent with the least significant bit first. */ \ - eusartInvertIODisable, /* RX and TX signal active high. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* No DMA wake up on transmission. */ \ - false, /* Halt DMA on error disabled. */ \ - EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ - false, /* TX auto tristate disabled. */ \ - false, /* Do not use PRS signal as RX signal.*/ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ - false, /* Multiprocessor mode disabled. */ \ - false, /* Multiprocessor address bit : 0.*/ \ - eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - } - -/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock. -#define EUSART_UART_INIT_DEFAULT_LF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 9600, /* 9600 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock. -#define EUSART_IRDA_INIT_DEFAULT_HF \ - { \ - EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \ - false, /* Disable IrDA low frequency mode. */ \ - eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ - eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \ - } - -/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock. -#define EUSART_IRDA_INIT_DEFAULT_LF \ - { \ - { \ - eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 9600, /* 9600 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - }, \ - true, /* Enable IrDA low frequency mode. */ \ - eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ - eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \ - } - -#if defined(EUSART_PRESENT) -/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock. -#define EUSART_SPI_ADVANCED_INIT_DEFAULT \ - { \ - eusartCsActiveLow, /* CS active low. */ \ - eusartInvertIODisable, /* RX and TX signal active High. */ \ - true, /* AutoCS enabled. */ \ - false, /* Data is sent with the least significant bit first. */ \ - 0u, /* CS setup time is 0 baud cycles */ \ - 0u, /* CS hold time is 0 baud cycles */ \ - 0u, /* Inter-frame time is 0 baud cycles */ \ - false, /* AutoTX disabled. */ \ - 0x0000, /* Default transmitted data is 0. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* Do not use PRS signal as RX signal. */ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \ - false, /* Do not use PRS signal as SCLK signal. */ \ - (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - true, /* The first byte sent by the slave won't be the default value if a byte is made available \ - after chip select is asserted. */ \ - 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \ - } - -/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock. -#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 10000000, /* 10 Mbits/s. */ \ - eusartDataBits8, /* 8 data bits. */ \ - true, /* Master mode enabled. */ \ - eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock. -#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 10000000, /* 10 Mbits/s. */ \ - eusartDataBits8, /* 8 data bits. */ \ - false, /* Master mode enabled. */ \ - eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -#if defined(EUSART_DALICFG_DALIEN) -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -/// Default configuration for EUSART advanced initialization structure. -#define EUSART_ADVANCED_DALI_INIT_DEFAULT \ - { \ - eusartHwFlowControlNone, /* Flow control disabled. */ \ - false, /* Collision detection disabled. */ \ - true, /* Data is sent with the most significant bit first. */ \ - eusartInvertIODisable, /* RX and TX signal active high. */ \ - false, /* No DMA wake up on reception. */ \ - false, /* No DMA wake up on transmission. */ \ - false, /* Halt DMA on error disabled. */ \ - EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ - false, /* TX auto tristate disabled. */ \ - false, /* Do not use PRS signal as RX signal.*/ \ - (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ - false, /* Multiprocessor mode disabled. */ \ - false, /* Multiprocessor address bit : 0.*/ \ - eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ - eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ - eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -#define EUSART_UART_DALI_INIT_DEFAULT_HF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 1200, /* 1200 bits/s. */ \ - eusartOVS16, /* Oversampling x16. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteEnable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. -#define EUSART_UART_DALI_INIT_DEFAULT_LF \ - { \ - eusartEnable, /* Enable RX/TX when initialization completed. */ \ - 0, /* Use current configured reference clock for configuring baud rate.*/ \ - 1200, /* 1200 bits/s. */ \ - eusartOVS0, /* Oversampling disabled. */ \ - eusartDataBits8, /* 8 data bits. */ \ - eusartNoParity, /* No parity. */ \ - eusartStopbits1, /* 1 stop bit. */ \ - eusartMajorityVoteDisable, /* Majority vote enabled. */ \ - eusartLoopbackDisable, /* Loop back disabled. */ \ - NULL, /* Default advanced settings. */ \ - } - -/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. -#define EUSART_DALI_INIT_DEFAULT_HF \ - { \ - EUSART_UART_DALI_INIT_DEFAULT_HF, \ - false, /* Disable DALI low frequency mode. */ \ - eusartDaliTxDataBits16, /* TX 16 data bits. */ \ - eusartDaliRxDataBits8, /* RX 8 data bits. */ \ - } \ - -/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. -#define EUSART_DALI_INIT_DEFAULT_LF \ - { \ - EUSART_UART_DALI_INIT_DEFAULT_LF, \ - true, /* Enable DALI low frequency mode. */ \ - eusartDaliTxDataBits16, /* TX 16 data bits. */ \ - eusartDaliRxDataBits8, /* RX 8 data bits. */ \ - } \ - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * Initialize EUSART when used in UART mode with the high frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); - -/***************************************************************************//** - * Initialize EUSART when used in UART mode with the low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); - -/***************************************************************************//** - * Initialize EUSART when used in IrDA mode with the high or low - * frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param irdaInit A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_IrDAInit(EUSART_TypeDef *eusart, - const EUSART_IrDAInit_TypeDef *irdaInit); - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initialize EUSART when used in SPI mode. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init); - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Initialize EUSART when used in DALI mode with the high or low - * frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param daliInit A pointer to the initialization structure. - ******************************************************************************/ -void EUSART_DaliInit(EUSART_TypeDef *eusart, - const EUSART_DaliInit_TypeDef *daliInit); - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure EUSART to its reset state. - * - * @param eusart Pointer to the EUSART peripheral register block. - ******************************************************************************/ -void EUSART_Reset(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Enable/disable EUSART receiver and/or transmitter. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the status for the receiver and transmitter. - ******************************************************************************/ -void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable); - -/***************************************************************************//** - * Receive one 8 bit frame, (or part of 9 bit frame). - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one frame when operating with - * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. - * Notice that possible parity/stop bits are not considered a part of the - * specified frame bit length. - * @note This function will stall if buffer is empty until data is received. - * - * @return Data received. - ******************************************************************************/ -uint8_t EUSART_Rx(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Receive one 8-16 bit frame with extended information. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one frame and additional RX - * status information. - * @note This function will stall if buffer is empty until data is received. - * - * @return Data received and receive status. - ******************************************************************************/ -uint16_t EUSART_RxExt(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Transmit one frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Depending on the frame length configuration, 8 (least significant) bits - * from @p data are transmitted. If the frame length is 9, 8 bits are - * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame - * with full control of all 9 bits. - * @note This function will stall if the 4 frame FIFO is full, until the buffer - * becomes available. - ******************************************************************************/ -void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data); - -/***************************************************************************//** - * Transmit one 8-9 bit frame with extended control. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * @note This function will stall if buffer is full until the buffer becomes - * available. - ******************************************************************************/ -void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data); - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Transmit one 8-16 bit frame and return received data. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @return Data received and receive status. - * - * @note SPI master mode only. - * @note This function will stall if the TX buffer is full until the buffer becomes - * available. - ******************************************************************************/ -uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data); - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Transmit one DALI frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param data Data to transmit. - * - * @note Depending on the TXdatabits configuration, N (least significant) bits - * from @p data are transmitted. - * @note This function will stall if the 16 frame FIFO is full, until the buffer - * becomes available. - ******************************************************************************/ -void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data); - -/***************************************************************************//** - * Receive one 8-32 bit DALI frame. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @note This function is normally used to receive one DALI frame (RXdatabits). - * @note This function will stall if the 16 frame FIFO is empty until new - * data is received. - * - * @return Data received. Depending on the RXdatabits configuration, N - * (least significant) bits are returned. - ******************************************************************************/ -uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart); -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure the baudrate (or as close as possible to a specified baudrate). - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param refFreq The EUSART reference clock frequency in Hz that will be used. - * If set to 0, the currently configured peripheral clock is - * used. - * @param baudrate A baudrate to try to achieve. - ******************************************************************************/ -void EUSART_BaudrateSet(EUSART_TypeDef *eusart, - uint32_t refFreq, - uint32_t baudrate); - -/***************************************************************************//** - * Get the current baudrate. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return The current baudrate. - ******************************************************************************/ -uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart); - -/***************************************************************************//** - * Enable/Disable reception operation until the configured start frame is - * received. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the receiver blocking status. - ******************************************************************************/ -void EUSART_RxBlock(EUSART_TypeDef *eusart, - EUSART_BlockRx_TypeDef enable); - -/***************************************************************************//** - * Enable/Disable the tristating of the transmitter output. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param enable Select the transmitter tristate status. - ******************************************************************************/ -void EUSART_TxTristateSet(EUSART_TypeDef *eusart, - EUSART_TristateTx_TypeDef enable); - -/***************************************************************************//** - * Initialize the automatic enabling of transmissions and/or reception using - * the PRS as a trigger. - * @note - * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before - * enabling the PRS trigger. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init Pointer to the initialization structure. - ******************************************************************************/ -void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, - const EUSART_PrsTriggerInit_TypeDef *init); - -/***************************************************************************//** - * Get EUSART STATUS register. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return STATUS register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart) -{ - return eusart->STATUS; -} - -/***************************************************************************//** - * Clear one or more pending EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IF_CLR = flags; -} - -/***************************************************************************//** - * Disable one or more EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IEN_CLR = flags; -} - -/***************************************************************************//** - * Enable one or more EUSART interrupts. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IEN_SET = flags; -} - -/***************************************************************************//** - * Get pending EUSART interrupt flags. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Pending EUSART interrupt sources. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart) -{ - return eusart->IF; -} - -/***************************************************************************//** - * Get enabled and pending EUSART interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Pending and enabled EUSART interrupt sources. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart) -{ - uint32_t tmp; - - /* Store EUSARTx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - tmp = eusart->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return eusart->IF & tmp; -} - -/***************************************************************************//** - * Set one or more pending EUSART interrupts from SW. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR - * combination of valid interrupt flags for EUSART module - * (EUSART_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags) -{ - eusart->IF_SET = flags; -} - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup eusart) */ -#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ -#endif /* EM_EUSART_H */ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_H +#define EM_EUSART_H +#include "em_device.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "sl_enum.h" +#include "em_eusart_compat.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup eusart EUSART - Extended USART +/// @brief Extended Universal Synchronous/Asynchronous Receiver/Transmitter +/// +/// @li @ref eusart_intro +/// @li @ref eusart_example +/// @li @ref eusart_em2 +/// +///@n @section eusart_intro Introduction +/// This module contains functions to control the Enhanced Universal Synchronous +/// / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon +/// Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, +/// therefore, be connected to an external transceiver to communicate with +/// another host using the serial link. +/// +/// It supports full duplex asynchronous UART communication as well as RS-485, +/// SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, +/// and IrDA devices. +/// +/// EUSART has a wide selection of operating modes, frame formats, and baud rates. +/// All features are supported through the API of this module. +/// +/// This module does not support DMA configuration. UARTDRV and SPIDRV drivers +/// provide full support for DMA and more. +/// +///@n @section eusart_example Example +/// +/// EUSART Async TX example: +/// @code{.c} +/// { +/// EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK); +/// CMU_ClockEnable(cmuClock_EUSART0CLK, true); +/// // Initialize the EUSART +/// EUSART_UartInitHf(EUSART0, &init); +/// EUSART_Tx(EUSART0, data); +/// } +/// +/// @endcode +/// +/// EUSART Sync SPI Transaction example: +/// @code{.c} +/// { +/// EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF; +/// +/// // Configure the clocks. +/// CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL); +/// CMU_ClockEnable(cmuClock_EUSART1, true); +/// CMU_ClockEnable(cmuClock_GPIO, true); +/// +/// //Configure the SPI ports +/// GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0); +/// GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0); +/// +/// // Connect EUSART to ports +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT) +/// | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT) +/// | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT) +/// | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT); +/// GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN; +/// +/// // Initialize the EUSART +/// EUSART_SpiInit(EUSART1, &init_master); +/// EUSART_Spi_TxRx(EUSART1, data); +/// } +/// +/// @endcode +///@n @section eusart_em2 EM2 guidelines for non EM2-Capable instances +/// +/// @note EUSART instances located in the PD1 power domain are non EM2-capable. +/// The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used +/// to determine whether or not a EUSART instance is EM2-Capable. +/// +/// Follow theses steps when entering in EM2: +/// -# Wait for the current transaction to complete with TXCIF interrupt +/// -# Disable TX and RX using TXDIS and RXDIS cmd +/// -# Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low +/// -# Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low +/// -# Disable SCLKPEN and CSPEN in GPIO if they were previously enabled +/// -# Enter EM2 +/// +/// On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO +/// (SCLKPEN and CSPEN) must be re-enabled. For example: +/// +/// @code{.c} +/// { +/// // Enable TX and RX +/// EUSART_Enable(EUSART0, eusartEnable); +/// BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN, +/// _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK, +/// GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN); +/// } +/// @endcode +/// +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Define EUSART FIFO Depth information */ +#if !defined(EUSART_FIFO_DEPTH) +#if defined(EUART_PRESENT) +#define EUSART0_FIFO_DEPTH 4 +#elif defined(EUSART_PRESENT) +#define EUSART0_FIFO_DEPTH 16 +#endif /* EUART_PRESENT */ +#define EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH +#define EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH + +#define EUSART_FIFO_DEPTH(n) (((n) == 0) ? EUSART0_FIFO_DEPTH \ + : ((n) == 1) ? EUSART1_FIFO_DEPTH \ + : ((n) == 2) ? EUSART2_FIFO_DEPTH \ + : ((n) == 3) ? EUSART3_FIFO_DEPTH \ + : ((n) == 4) ? EUSART4_FIFO_DEPTH \ + : 0x0UL) +#endif /* EUSART_FIFO_DEPTH */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/// Enable selection. +typedef enum { + /// Disable the peripheral. + eusartDisable = 0x0, + + /// Enable receiver only, transmitter disabled. + eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS), + + /// Enable transmitter only, receiver disabled. + eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS), + + /// Enable both receiver and transmitter. + eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN) +} EUSART_Enable_TypeDef; + +/// Data bit selection. +typedef enum { + eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN, ///< 7 data bits. + eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT, ///< 8 data bits. + eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE, ///< 9 data bits. +#if defined(EUSART_PRESENT) + eusartDataBits10 = EUSART_FRAMECFG_DATABITS_TEN, ///< 10 data bits, SPI mode only. + eusartDataBits11 = EUSART_FRAMECFG_DATABITS_ELEVEN, ///< 11 data bits, SPI mode only. + eusartDataBits12 = EUSART_FRAMECFG_DATABITS_TWELVE, ///< 12 data bits, SPI mode only. + eusartDataBits13 = EUSART_FRAMECFG_DATABITS_THIRTEEN, ///< 13 data bits, SPI mode only. + eusartDataBits14 = EUSART_FRAMECFG_DATABITS_FOURTEEN, ///< 14 data bits, SPI mode only. + eusartDataBits15 = EUSART_FRAMECFG_DATABITS_FIFTEEN, ///< 15 data bits, SPI mode only. + eusartDataBits16 = EUSART_FRAMECFG_DATABITS_SIXTEEN, ///< 16 data bits, SPI mode only. +#endif +} EUSART_Databits_TypeDef; + +/// Parity selection. +typedef enum { + eusartNoParity = EUSART_FRAMECFG_PARITY_NONE, ///< No parity. + eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN, ///< Even parity. + eusartOddParity = EUSART_FRAMECFG_PARITY_ODD ///< Odd parity. +} EUSART_Parity_TypeDef; + +/// Stop bits selection. +typedef enum { + eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF, ///< 0.5 stop bits. + eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF, ///< 1.5 stop bits. + eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE, ///< 1 stop bits. + eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO ///< 2 stop bits. +} EUSART_Stopbits_TypeDef; + +/// Oversampling selection, used for asynchronous operation. +typedef enum { + eusartOVS16 = EUSART_CFG0_OVS_X16, ///< 16x oversampling (normal). + eusartOVS8 = EUSART_CFG0_OVS_X8, ///< 8x oversampling. + eusartOVS6 = EUSART_CFG0_OVS_X6, ///< 6x oversampling. + eusartOVS4 = EUSART_CFG0_OVS_X4, ///< 4x oversampling. + eusartOVS0 = EUSART_CFG0_OVS_DISABLE ///< Oversampling disabled. +} EUSART_OVS_TypeDef; + +/// HW flow control config. +typedef enum { + eusartHwFlowControlNone = 0, ///< No HW Flow Control. + eusartHwFlowControlCts, ///< CTS HW Flow Control. + eusartHwFlowControlRts, ///< RTS HW Flow Control. + eusartHwFlowControlCtsAndRts ///< CTS and RTS HW Flow Control. +} EUSART_HwFlowControl_TypeDef; + +/// Loopback enable. +typedef enum { + eusartLoopbackEnable = EUSART_CFG0_LOOPBK, ///< Enable loopback. + eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE ///< Disable loopback. +} EUSART_LoopbackEnable_TypeDef; + +/// Majority vote enable. +typedef enum { + eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT, ///< Enable majority vote for 16x, 8x and 6x oversampling modes. + eusartMajorityVoteDisable = EUSART_CFG0_MVDIS ///< Disable majority vote for 16x, 8x and 6x oversampling modes. +} EUSART_MajorityVote_TypeDef; + +/// Block reception enable. +typedef enum { + eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN, ///< Block reception enable, resulting in all incoming frames being discarded. + eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS ///< Block reception disable, resulting in all incoming frames being loaded into the RX FIFO. +} EUSART_BlockRx_TypeDef; + +/// TX output tristate enable. +typedef enum { + eusartTristateTxEnable = EUSART_CMD_TXTRIEN, ///< Tristates the transmitter output. + eusartTristateTxDisable = EUSART_CMD_TXTRIDIS ///< Disables tristating of the transmitter output. +} EUSART_TristateTx_TypeDef; + +/// IrDA filter enable. +typedef enum { + eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE, ///< Enable filter on demodulator. + eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE ///< Disable filter on demodulator. +} EUSART_IrDARxFilterEnable_TypeDef; + +/// Pulse width selection for IrDA mode. +typedef enum { + /// IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8 + eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE, + + /// IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8 + eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO, + + /// IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8 + eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE, + + /// IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8 + eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR +} EUSART_IrDAPulseWidth_Typedef; + +/// PRS trigger enable. +typedef enum { + /// Disable trigger on both receiver and transmitter. + eusartPrsTriggerDisable = 0x0, + + /// Enable receive trigger only, transmit disabled. + eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN, + + /// Enable transmit trigger only, receive disabled. + eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN, + + /// Enable trigger on both receive and transmit. + eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN) +} EUSART_PrsTriggerEnable_TypeDef; + +/// PRS Channel type. +typedef uint8_t EUSART_PrsChannel_TypeDef; + +/// IO polarity selection. +typedef enum { + /// Disable inversion on both RX and TX signals. + eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE), + + /// Invert RX signal, before receiver. + eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE, + + /// Invert TX signal, after transmitter. + eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE, + + /// Enable trigger on both receive and transmit. + eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) +} EUSART_InvertIO_TypeDef; + +/// Auto TX delay transmission. +SL_ENUM(EUSART_AutoTxDelay_TypeDef) { + /// Frames are transmitted immediately. + eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE, + + /// Transmission of new frames is delayed by a single bit period. + eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE, + + /// Transmission of new frames is delayed by a two bit periods. + eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE, + + /// Transmission of new frames is delayed by a three bit periods. + eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE +}; + +/// RX FIFO Interrupt ans Status Watermark. +typedef enum { + eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME, + eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES, + eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES, + eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartRxFiFoWatermark5Frame = EUSART_CFG1_RXFIW_FIVEFRAMES, + eusartRxFiFoWatermark6Frame = EUSART_CFG1_RXFIW_SIXFRAMES, + eusartRxFiFoWatermark7Frame = EUSART_CFG1_RXFIW_SEVENFRAMES, + eusartRxFiFoWatermark8Frame = EUSART_CFG1_RXFIW_EIGHTFRAMES, + eusartRxFiFoWatermark9Frame = EUSART_CFG1_RXFIW_NINEFRAMES, + eusartRxFiFoWatermark10Frame = EUSART_CFG1_RXFIW_TENFRAMES, + eusartRxFiFoWatermark11Frame = EUSART_CFG1_RXFIW_ELEVENFRAMES, + eusartRxFiFoWatermark12Frame = EUSART_CFG1_RXFIW_TWELVEFRAMES, + eusartRxFiFoWatermark13Frame = EUSART_CFG1_RXFIW_THIRTEENFRAMES, + eusartRxFiFoWatermark14Frame = EUSART_CFG1_RXFIW_FOURTEENFRAMES, + eusartRxFiFoWatermark15Frame = EUSART_CFG1_RXFIW_FIFTEENFRAMES, + eusartRxFiFoWatermark16Frame = EUSART_CFG1_RXFIW_SIXTEENFRAMES +#endif +} EUSART_RxFifoWatermark_TypeDef; + +/// TX FIFO Interrupt and Status Watermark. +typedef enum { + eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME, + eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES, + eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES, + eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES, +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + eusartTxFiFoWatermark5Frame = EUSART_CFG1_TXFIW_FIVEFRAMES, + eusartTxFiFoWatermark6Frame = EUSART_CFG1_TXFIW_SIXFRAMES, + eusartTxFiFoWatermark7Frame = EUSART_CFG1_TXFIW_SEVENFRAMES, + eusartTxFiFoWatermark8Frame = EUSART_CFG1_TXFIW_EIGHTFRAMES, + eusartTxFiFoWatermark9Frame = EUSART_CFG1_TXFIW_NINEFRAMES, + eusartTxFiFoWatermark10Frame = EUSART_CFG1_TXFIW_TENFRAMES, + eusartTxFiFoWatermark11Frame = EUSART_CFG1_TXFIW_ELEVENFRAMES, + eusartTxFiFoWatermark12Frame = EUSART_CFG1_TXFIW_TWELVEFRAMES, + eusartTxFiFoWatermark13Frame = EUSART_CFG1_TXFIW_THIRTEENFRAMES, + eusartTxFiFoWatermark14Frame = EUSART_CFG1_TXFIW_FOURTEENFRAMES, + eusartTxFiFoWatermark15Frame = EUSART_CFG1_TXFIW_FIFTEENFRAMES, + eusartTxFiFoWatermark16Frame = EUSART_CFG1_TXFIW_SIXTEENFRAMES +#endif +} EUSART_TxFifoWatermark_TypeDef; + +#if defined(EUSART_PRESENT) +/// Clock polarity/phase mode. +typedef enum { + /// Clock idle low, sample on rising edge. + eusartClockMode0 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle low, sample on falling edge. + eusartClockMode1 = EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING, + + /// Clock idle high, sample on falling edge. + eusartClockMode2 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING, + + /// Clock idle high, sample on rising edge. + eusartClockMode3 = EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING +} EUSART_ClockMode_TypeDef; + +/// Chip select polarity. +typedef enum { + /// Chip select active low. + eusartCsActiveLow = EUSART_CFG2_CSINV_AL, + + /// Chip select active high. + eusartCsActiveHigh = EUSART_CFG2_CSINV_AH, +} EUSART_CsPolarity_TypeDef; + +#if defined(EUSART_DALICFG_DALIEN) +/// DALI TX databits (8-32). +typedef enum { + eusartDaliTxDataBits8 = EUSART_DALICFG_DALITXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliTxDataBits9 = EUSART_DALICFG_DALITXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliTxDataBits10 = EUSART_DALICFG_DALITXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliTxDataBits11 = EUSART_DALICFG_DALITXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliTxDataBits12 = EUSART_DALICFG_DALITXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliTxDataBits13 = EUSART_DALICFG_DALITXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliTxDataBits14 = EUSART_DALICFG_DALITXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliTxDataBits15 = EUSART_DALICFG_DALITXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliTxDataBits16 = EUSART_DALICFG_DALITXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliTxDataBits17 = EUSART_DALICFG_DALITXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliTxDataBits18 = EUSART_DALICFG_DALITXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliTxDataBits19 = EUSART_DALICFG_DALITXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliTxDataBits20 = EUSART_DALICFG_DALITXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliTxDataBits21 = EUSART_DALICFG_DALITXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliTxDataBits22 = EUSART_DALICFG_DALITXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliTxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliTxDataBits24 = EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliTxDataBits25 = EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliTxDataBits26 = EUSART_DALICFG_DALITXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliTxDataBits27 = EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliTxDataBits28 = EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliTxDataBits29 = EUSART_DALICFG_DALITXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliTxDataBits30 = EUSART_DALICFG_DALITXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliTxDataBits31 = EUSART_DALICFG_DALITXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliTxDataBits32 = EUSART_DALICFG_DALITXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliTxDatabits_TypeDef; + +/// DALI RX databits (8-32). +typedef enum { + eusartDaliRxDataBits8 = EUSART_DALICFG_DALIRXDATABITS_EIGHT, ///< Each frame contains 8 data bits. + eusartDaliRxDataBits9 = EUSART_DALICFG_DALIRXDATABITS_NINE, ///< Each frame contains 9 data bits. + eusartDaliRxDataBits10 = EUSART_DALICFG_DALIRXDATABITS_TEN, ///< Each frame contains 10 data bits. + eusartDaliRxDataBits11 = EUSART_DALICFG_DALIRXDATABITS_ELEVEN, ///< Each frame contains 11 data bits. + eusartDaliRxDataBits12 = EUSART_DALICFG_DALIRXDATABITS_TWELVE, ///< Each frame contains 12 data bits. + eusartDaliRxDataBits13 = EUSART_DALICFG_DALIRXDATABITS_THIRTEEN, ///< Each frame contains 13 data bits. + eusartDaliRxDataBits14 = EUSART_DALICFG_DALIRXDATABITS_FOURTEEN, ///< Each frame contains 14 data bits. + eusartDaliRxDataBits15 = EUSART_DALICFG_DALIRXDATABITS_FIFTEEN, ///< Each frame contains 15 data bits. + eusartDaliRxDataBits16 = EUSART_DALICFG_DALIRXDATABITS_SIXTEEN, ///< Each frame contains 16 data bits. + eusartDaliRxDataBits17 = EUSART_DALICFG_DALIRXDATABITS_SEVENTEEN, ///< Each frame contains 17 data bits. + eusartDaliRxDataBits18 = EUSART_DALICFG_DALIRXDATABITS_EIGHTEEN, ///< Each frame contains 18 data bits. + eusartDaliRxDataBits19 = EUSART_DALICFG_DALIRXDATABITS_NINETEEN, ///< Each frame contains 19 data bits. + eusartDaliRxDataBits20 = EUSART_DALICFG_DALIRXDATABITS_TWENTY, ///< Each frame contains 20 data bits. + eusartDaliRxDataBits21 = EUSART_DALICFG_DALIRXDATABITS_TWENTYONE, ///< Each frame contains 21 data bits. + eusartDaliRxDataBits22 = EUSART_DALICFG_DALIRXDATABITS_TWENTYTWO, ///< Each frame contains 22 data bits. + eusartDaliRxDataBits23 = EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE, ///< Each frame contains 23 data bits. + eusartDaliRxDataBits24 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFOUR, ///< Each frame contains 24 data bits. + eusartDaliRxDataBits25 = EUSART_DALICFG_DALIRXDATABITS_TWENTYFIVE, ///< Each frame contains 25 data bits. + eusartDaliRxDataBits26 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSIX, ///< Each frame contains 26 data bits. + eusartDaliRxDataBits27 = EUSART_DALICFG_DALIRXDATABITS_TWENTYSEVEN, ///< Each frame contains 27 data bits. + eusartDaliRxDataBits28 = EUSART_DALICFG_DALIRXDATABITS_TWENTYEIGHT, ///< Each frame contains 28 data bits. + eusartDaliRxDataBits29 = EUSART_DALICFG_DALIRXDATABITS_TWENTYNINE, ///< Each frame contains 29 data bits. + eusartDaliRxDataBits30 = EUSART_DALICFG_DALIRXDATABITS_THIRTY, ///< Each frame contains 30 data bits. + eusartDaliRxDataBits31 = EUSART_DALICFG_DALIRXDATABITS_THIRTYONE, ///< Each frame contains 31 data bits. + eusartDaliRxDataBits32 = EUSART_DALICFG_DALIRXDATABITS_THIRTYTWO, ///< Each frame contains 32 data bits. +} EUSART_DaliRxDatabits_TypeDef; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ +/// Advanced initialization structure. +typedef struct { + /// Hardware flow control mode. + EUSART_HwFlowControl_TypeDef hwFlowControl; + + /// Enable the collision Detection feature. + /// Internal (setting loopbackEnable) or external loopback must be done to use this feature. + bool collisionDetectEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + bool dmaWakeUpOnRx; + + /// Enable the automatic wake up from EM2 to EM1 for DMA TX operation. + bool dmaWakeUpOnTx; + + /// Enable DMA requests blocking while framing or parity errors. + bool dmaHaltOnError; + + /// Start frame that will enable RX operation. 0x00 Disable this feature. + uint8_t startFrame; + + /// Enable automatic tristating of transmistter output when there is nothing to transmit. + bool txAutoTristate; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable Multiprocessor mode. Address and data filtering using the 9th bit. + bool multiProcessorEnable; + + /// Multiprocessor address bit value. If true, 9th bit of address frame must bit 1, 0 otherwise. + bool multiProcessorAddressBitHigh; + + /// Auto TX delay before new transfers. Frames sent back-to-back are not delayed. + EUSART_AutoTxDelay_TypeDef autoTxDelay; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Transmit FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; +} EUSART_AdvancedInit_TypeDef; + +/// Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired baud rate. If set to 0, Auto Baud feature is enabled and + /// the EUSART will wait for (0x55) frame to detect the Baudrate. + uint32_t baudrate; + + /// Oversampling used. + EUSART_OVS_TypeDef oversampling; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Parity mode to use. + EUSART_Parity_TypeDef parity; + + /// Number of stop bits to use. + EUSART_Stopbits_TypeDef stopbits; + + /// Majority Vote can be disabled for 16x, 8x and 6x oversampling modes. + EUSART_MajorityVote_TypeDef majorityVote; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_AdvancedInit_TypeDef *advancedSettings; +} EUSART_UartInit_TypeDef; + +/// IrDA Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the IrDA low frequency mode. Only RX operation are enabled. + bool irDALowFrequencyEnable; + + /// Set to enable filter on IrDA demodulator. + EUSART_IrDARxFilterEnable_TypeDef irDARxFilterEnable; + + /// Configure the pulse width generated by the IrDA modulator as a fraction + /// of the configured EUSART bit period. + EUSART_IrDAPulseWidth_Typedef irDAPulseWidth; +} EUSART_IrDAInit_TypeDef; + +/// PRS Trigger initialization structure. +typedef struct { + /// PRS to EUSART trigger mode. + EUSART_PrsTriggerEnable_TypeDef prs_trigger_enable; + + /// PRS channel to be used to trigger auto transmission. + EUSART_PrsChannel_TypeDef prs_trigger_channel; +} EUSART_PrsTriggerInit_TypeDef; + +#if defined(EUSART_PRESENT) +/// SPI Advanced initialization structure. +typedef struct { + /// Chip select polarity + EUSART_CsPolarity_TypeDef csPolarity; + + /// Enable inversion of RX and/or TX signals. + EUSART_InvertIO_TypeDef invertIO; + + /// Enable automatic chip select. CS is managed by the peripheral. + bool autoCsEnable; + + /// If true, data will be send with most significant bit first. + bool msbFirst; + + /// Auto CS setup time (before transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsSetupTime; + + /// Auto CS hold time (after transmission) in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoCsHoldTime; + + /// Inter-frame time in baud cycles. Acceptable value ( 0 to 7 baud cycle). + uint8_t autoInterFrameTime; + + /// Enable AUTOTX mode. Transmits as long as the RX FIFO is not full. + /// Generates underflow interrupt if the TX FIFO is empty. + bool autoTxEnable; + + /// Default transmitted data when the TXFIFO is empty. + uint16_t defaultTxData; + + /// Enable the automatic wake up from EM2 to EM1 for DMA RX operation. + /// Only applicable to EM2 (low frequency) capable EUSART instances. + bool dmaWakeUpOnRx; + + /// Enable EUSART capability to use a PRS channel as an input data line for the receiver. + /// The configured RX GPIO signal won't be routed to the EUSART receiver. + bool prsRxEnable; + + /// PRS Channel used to transmit data from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsRxChannel; + + /// Enable EUSART capability to use a PRS channel as an input SPI Clock. + /// Slave mode only. + bool prsClockEnable; + + /// PRS Channel used to transmit SCLK from PRS to the EUSART. + EUSART_PrsChannel_TypeDef prsClockChannel; + + /// Interrupt and status level of the Receive FIFO. + EUSART_RxFifoWatermark_TypeDef RxFifoWatermark; + + /// Interrupt and status level of the Receive FIFO. + EUSART_TxFifoWatermark_TypeDef TxFifoWatermark; + + /// Force load the first FIFO value. + bool forceLoad; + + /// Setup window in bus clock cycles before the sampling edge of SCLK at word-boundary to avoid force load error. + uint8_t setupWindow; +} EUSART_SpiAdvancedInit_TypeDef; + +/// SPI Initialization structure. +typedef struct { + /// Specifies whether TX and/or RX will be enabled when initialization completes. + EUSART_Enable_TypeDef enable; + + /// EUSART reference clock assumed when configuring baud rate setup. Set + /// to 0 if using currently configured reference clock. + uint32_t refFreq; + + /// Desired bit rate in Hz. + /// Depending on EUSART instance clock, not all bitrates + /// are achievable as the divider is limited to 255. + uint32_t bitRate; + + /// Number of data bits in frame. + EUSART_Databits_TypeDef databits; + + /// Select to operate in master or slave mode. + bool master; + + /// Clock polarity/phase mode. + EUSART_ClockMode_TypeDef clockMode; + + /// Enable Loop Back configuration. + EUSART_LoopbackEnable_TypeDef loopbackEnable; + + /// Advanced initialization structure pointer. It can be NULL. + EUSART_SpiAdvancedInit_TypeDef *advancedSettings; +} EUSART_SpiInit_TypeDef; +#endif /* EUSART_PRESENT */ + +/// DALI Initialization structure. +typedef struct { + /// General EUSART initialization structure. + EUSART_UartInit_TypeDef init; + + /// Enable the DALI low frequency mode. + bool daliLowFrequencyEnable; + +#if defined(EUSART_DALICFG_DALIEN) + /// Number of TX data bits in frame. + EUSART_DaliTxDatabits_TypeDef TXdatabits; + /// Number of RX data bits in frame. + EUSART_DaliRxDatabits_TypeDef RXdatabits; +#endif +} EUSART_DaliInit_TypeDef; + +/// Default configuration for EUSART initialization structure in UART mode with high-frequency clock. +#define EUSART_UART_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 115200, /* 115200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default start frame configuration, i.e. feature disabled. +#define EUSART_DEFAULT_START_FRAME 0x00u + +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in UART mode with low-frequency clock. +#define EUSART_UART_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_HF \ + { \ + EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \ + false, /* Disable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \ + } + +/// Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock. +#define EUSART_IRDA_INIT_DEFAULT_LF \ + { \ + { \ + eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 9600, /* 9600 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + }, \ + true, /* Enable IrDA low frequency mode. */ \ + eusartIrDARxFilterDisable, /* RX Filter disabled. */ \ + eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \ + } + +#if defined(EUSART_PRESENT) +/// Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock. +#define EUSART_SPI_ADVANCED_INIT_DEFAULT \ + { \ + eusartCsActiveLow, /* CS active low. */ \ + eusartInvertIODisable, /* RX and TX signal active High. */ \ + true, /* AutoCS enabled. */ \ + false, /* Data is sent with the least significant bit first. */ \ + 0u, /* CS setup time is 0 baud cycles */ \ + 0u, /* CS hold time is 0 baud cycles */ \ + 0u, /* Inter-frame time is 0 baud cycles */ \ + false, /* AutoTX disabled. */ \ + 0x0000, /* Default transmitted data is 0. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* Do not use PRS signal as RX signal. */ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX tied to prs channel 0. */ \ + false, /* Do not use PRS signal as SCLK signal. */ \ + (EUSART_PrsChannel_TypeDef) 1u, /* EUSART SCLCK tied to prs channel 1. */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + true, /* The first byte sent by the slave won't be the default value if a byte is made available \ + after chip select is asserted. */ \ + 0x04u, /* Setup window before the sampling edge of SCLK at word-boundary to avoid force load error. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock. +#define EUSART_SPI_MASTER_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + true, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock. +#define EUSART_SPI_SLAVE_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 10000000, /* 10 Mbits/s. */ \ + eusartDataBits8, /* 8 data bits. */ \ + false, /* Master mode enabled. */ \ + eusartClockMode0, /* Clock idle low, sample on rising edge. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +#if defined(EUSART_DALICFG_DALIEN) +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +/// Default configuration for EUSART advanced initialization structure. +#define EUSART_ADVANCED_DALI_INIT_DEFAULT \ + { \ + eusartHwFlowControlNone, /* Flow control disabled. */ \ + false, /* Collision detection disabled. */ \ + true, /* Data is sent with the most significant bit first. */ \ + eusartInvertIODisable, /* RX and TX signal active high. */ \ + false, /* No DMA wake up on reception. */ \ + false, /* No DMA wake up on transmission. */ \ + false, /* Halt DMA on error disabled. */ \ + EUSART_DEFAULT_START_FRAME, /* No start frame. */ \ + false, /* TX auto tristate disabled. */ \ + false, /* Do not use PRS signal as RX signal.*/ \ + (EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \ + false, /* Multiprocessor mode disabled. */ \ + false, /* Multiprocessor address bit : 0.*/ \ + eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \ + eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \ + eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_HF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS16, /* Oversampling x16. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteEnable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_UART_DALI_INIT_DEFAULT_LF \ + { \ + eusartEnable, /* Enable RX/TX when initialization completed. */ \ + 0, /* Use current configured reference clock for configuring baud rate.*/ \ + 1200, /* 1200 bits/s. */ \ + eusartOVS0, /* Oversampling disabled. */ \ + eusartDataBits8, /* 8 data bits. */ \ + eusartNoParity, /* No parity. */ \ + eusartStopbits1, /* 1 stop bit. */ \ + eusartMajorityVoteDisable, /* Majority vote enabled. */ \ + eusartLoopbackDisable, /* Loop back disabled. */ \ + NULL, /* Default advanced settings. */ \ + } + +/// Default configuration for EUSART initialization structure in DALI mode with high-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_HF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_HF, \ + false, /* Disable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +/// Default configuration for EUSART initialization structure in DALI mode with low-frequency clock. +#define EUSART_DALI_INIT_DEFAULT_LF \ + { \ + EUSART_UART_DALI_INIT_DEFAULT_LF, \ + true, /* Enable DALI low frequency mode. */ \ + eusartDaliTxDataBits16, /* TX 16 data bits. */ \ + eusartDaliRxDataBits8, /* RX 8 data bits. */ \ + } \ + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the high frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in UART mode with the low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init); + +/***************************************************************************//** + * Initialize EUSART when used in IrDA mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param irdaInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initialize EUSART when used in SPI mode. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, const EUSART_SpiInit_TypeDef *init); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initialize EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param daliInit A pointer to the initialization structure. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit); + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure EUSART to its reset state. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/disable EUSART receiver and/or transmitter. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the status for the receiver and transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable); + +/***************************************************************************//** + * Receive one 8 bit frame, (or part of 9 bit frame). + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame when operating with + * frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. + * Notice that possible parity/stop bits are not considered a part of the + * specified frame bit length. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received. + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Receive one 8-16 bit frame with extended information. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one frame and additional RX + * status information. + * @note This function will stall if buffer is empty until data is received. + * + * @return Data received and receive status. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Transmit one frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the frame length configuration, 8 (least significant) bits + * from @p data are transmitted. If the frame length is 9, 8 bits are + * transmitted from @p data. See EUSART_TxExt() for transmitting 9 bit frame + * with full control of all 9 bits. + * @note This function will stall if the 4 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data); + +/***************************************************************************//** + * Transmit one 8-9 bit frame with extended control. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * @note This function will stall if buffer is full until the buffer becomes + * available. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmit one 8-16 bit frame and return received data. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @return Data received and receive status. + * + * @note SPI master mode only. + * @note This function will stall if the TX buffer is full until the buffer becomes + * available. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data); + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmit one DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param data Data to transmit. + * + * @note Depending on the TXdatabits configuration, N (least significant) bits + * from @p data are transmitted. + * @note This function will stall if the 16 frame FIFO is full, until the buffer + * becomes available. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data); + +/***************************************************************************//** + * Receive one 8-32 bit DALI frame. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @note This function is normally used to receive one DALI frame (RXdatabits). + * @note This function will stall if the 16 frame FIFO is empty until new + * data is received. + * + * @return Data received. Depending on the RXdatabits configuration, N + * (least significant) bits are returned. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart); +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the baudrate (or as close as possible to a specified baudrate). + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * If set to 0, the currently configured peripheral clock is + * used. + * @param baudrate A baudrate to try to achieve. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate); + +/***************************************************************************//** + * Get the current baudrate. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return The current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart); + +/***************************************************************************//** + * Enable/Disable reception operation until the configured start frame is + * received. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the receiver blocking status. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, + EUSART_BlockRx_TypeDef enable); + +/***************************************************************************//** + * Enable/Disable the tristating of the transmitter output. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param enable Select the transmitter tristate status. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable); + +/***************************************************************************//** + * Initialize the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + * @note + * Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before + * enabling the PRS trigger. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init Pointer to the initialization structure. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * Get EUSART STATUS register. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_StatusGet(EUSART_TypeDef *eusart) +{ + return eusart->STATUS; +} + +/***************************************************************************//** + * Clear one or more pending EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_CLR = flags; +} + +/***************************************************************************//** + * Disable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_CLR = flags; +} + +/***************************************************************************//** + * Enable one or more EUSART interrupts. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Pending EUSART interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IEN_SET = flags; +} + +/***************************************************************************//** + * Get pending EUSART interrupt flags. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGet(EUSART_TypeDef *eusart) +{ + return eusart->IF; +} + +/***************************************************************************//** + * Get enabled and pending EUSART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Pending and enabled EUSART interrupt sources. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_IntGetEnabled(EUSART_TypeDef *eusart) +{ + uint32_t tmp; + + /* Store EUSARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = eusart->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return eusart->IF & tmp; +} + +/***************************************************************************//** + * Set one or more pending EUSART interrupts from SW. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @param flags Interrupt source(s) to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for EUSART module + * (EUSART_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags) +{ + eusart->IF_SET = flags; +} + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup eusart) */ +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ +#endif /* EM_EUSART_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h index 50822e2..96ac200 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_eusart_compat.h @@ -1,218 +1,218 @@ -/***************************************************************************//** - * @file - * @brief EUSART Compatibility Header - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_EUSART_COMPAT_H -#define EM_EUSART_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define EUSART_IF_TXCIF EUSART_IF_TXC -#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT -#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK -#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT -#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT - -#define EUSART_IF_TXFLIF EUSART_IF_TXFL -#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT -#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK -#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT -#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT - -#define EUSART_IF_RXFLIF EUSART_IF_RXFL -#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT -#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK -#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT -#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT - -#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL -#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT -#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK -#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT -#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT - -#define EUSART_IF_RXOFIF EUSART_IF_RXOF -#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT -#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK -#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT -#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT - -#define EUSART_IF_RXUFIF EUSART_IF_RXUF -#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT -#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK -#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT -#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT - -#define EUSART_IF_TXOFIF EUSART_IF_TXOF -#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT -#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK -#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT -#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT - -#define EUSART_IF_PERRIF EUSART_IF_PERR -#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT -#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK -#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT -#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT - -#define EUSART_IF_FERRIF EUSART_IF_FERR -#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT -#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK -#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT -#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT - -#define EUSART_IF_MPAFIF EUSART_IF_MPAF -#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT -#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK -#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT -#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT - -#define EUSART_IF_CCFIF EUSART_IF_CCF -#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT -#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK -#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT -#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT - -#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE -#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT -#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK -#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT -#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT - -#define EUSART_IF_STARTFIF EUSART_IF_STARTF -#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT -#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK -#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT -#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT - -#define EUSART_IF_SIGFIF EUSART_IF_SIGF -#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT -#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK -#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT -#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT - -#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE -#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT -#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK -#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT -#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT - -#define EUSART_IEN_TXCIEN EUSART_IEN_TXC -#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT -#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK -#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT -#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT - -#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL -#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT -#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK -#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT -#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT - -#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL -#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT -#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK -#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT -#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT - -#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL -#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT -#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK -#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT -#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT - -#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF -#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT -#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK -#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT -#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT - -#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF -#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT -#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK -#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT -#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT - -#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF -#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT -#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK -#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT -#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT - -#define EUSART_IEN_PERRIEN EUSART_IEN_PERR -#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT -#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK -#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT -#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT - -#define EUSART_IEN_FERRIEN EUSART_IEN_FERR -#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT -#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK -#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT -#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT - -#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF -#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT -#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK -#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT -#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT - -#define EUSART_IEN_CCFIEN EUSART_IEN_CCF -#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT -#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK -#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT -#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT - -#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE -#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT -#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK -#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT -#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT - -#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF -#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT -#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK -#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT -#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT - -#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF -#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT -#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK -#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT -#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT - -#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE -#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT -#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK -#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT -#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT - -#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2 - -#endif +/***************************************************************************//** + * @file + * @brief EUSART Compatibility Header + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_EUSART_COMPAT_H +#define EM_EUSART_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define EUSART_IF_TXCIF EUSART_IF_TXC +#define _EUSART_IF_TXCIF_SHIFT _EUSART_IF_TXC_SHIFT +#define _EUSART_IF_TXCIF_MASK _EUSART_IF_TXC_MASK +#define _EUSART_IF_TXCIF_DEFAULT _EUSART_IF_TXC_DEFAULT +#define EUSART_IF_TXCIF_DEFAULT EUSART_IF_TXC_DEFAULT + +#define EUSART_IF_TXFLIF EUSART_IF_TXFL +#define _EUSART_IF_TXFLIF_SHIFT _EUSART_IF_TXFL_SHIFT +#define _EUSART_IF_TXFLIF_MASK _EUSART_IF_TXFL_MASK +#define _EUSART_IF_TXFLIF_DEFAULT _EUSART_IF_TXFL_DEFAULT +#define EUSART_IF_TXFLIF_DEFAULT EUSART_IF_TXFL_DEFAULT + +#define EUSART_IF_RXFLIF EUSART_IF_RXFL +#define _EUSART_IF_RXFLIF_SHIFT _EUSART_IF_RXFL_SHIFT +#define _EUSART_IF_RXFLIF_MASK _EUSART_IF_RXFL_MASK +#define _EUSART_IF_RXFLIF_DEFAULT _EUSART_IF_RXFL_DEFAULT +#define EUSART_IF_RXFLIF_DEFAULT EUSART_IF_RXFL_DEFAULT + +#define EUSART_IF_RXFULLIF EUSART_IF_RXFULL +#define _EUSART_IF_RXFULLIF_SHIFT _EUSART_IF_RXFULL_SHIFT +#define _EUSART_IF_RXFULLIF_MASK _EUSART_IF_RXFULL_MASK +#define _EUSART_IF_RXFULLIF_DEFAULT _EUSART_IF_RXFULL_DEFAULT +#define EUSART_IF_RXFULLIF_DEFAULT EUSART_IF_RXFULL_DEFAULT + +#define EUSART_IF_RXOFIF EUSART_IF_RXOF +#define _EUSART_IF_RXOFIF_SHIFT _EUSART_IF_RXOF_SHIFT +#define _EUSART_IF_RXOFIF_MASK _EUSART_IF_RXOF_MASK +#define _EUSART_IF_RXOFIF_DEFAULT _EUSART_IF_RXOF_DEFAULT +#define EUSART_IF_RXOFIF_DEFAULT EUSART_IF_RXOF_DEFAULT + +#define EUSART_IF_RXUFIF EUSART_IF_RXUF +#define _EUSART_IF_RXUFIF_SHIFT _EUSART_IF_RXUF_SHIFT +#define _EUSART_IF_RXUFIF_MASK _EUSART_IF_RXUF_MASK +#define _EUSART_IF_RXUFIF_DEFAULT _EUSART_IF_RXUF_DEFAULT +#define EUSART_IF_RXUFIF_DEFAULT EUSART_IF_RXUF_DEFAULT + +#define EUSART_IF_TXOFIF EUSART_IF_TXOF +#define _EUSART_IF_TXOFIF_SHIFT _EUSART_IF_TXOF_SHIFT +#define _EUSART_IF_TXOFIF_MASK _EUSART_IF_TXOF_MASK +#define _EUSART_IF_TXOFIF_DEFAULT _EUSART_IF_TXOF_DEFAULT +#define EUSART_IF_TXOFIF_DEFAULT EUSART_IF_TXOF_DEFAULT + +#define EUSART_IF_PERRIF EUSART_IF_PERR +#define _EUSART_IF_PERRIF_SHIFT _EUSART_IF_PERR_SHIFT +#define _EUSART_IF_PERRIF_MASK _EUSART_IF_PERR_MASK +#define _EUSART_IF_PERRIF_DEFAULT _EUSART_IF_PERR_DEFAULT +#define EUSART_IF_PERRIF_DEFAULT EUSART_IF_PERR_DEFAULT + +#define EUSART_IF_FERRIF EUSART_IF_FERR +#define _EUSART_IF_FERRIF_SHIFT _EUSART_IF_FERR_SHIFT +#define _EUSART_IF_FERRIF_MASK _EUSART_IF_FERR_MASK +#define _EUSART_IF_FERRIF_DEFAULT _EUSART_IF_FERR_DEFAULT +#define EUSART_IF_FERRIF_DEFAULT EUSART_IF_FERR_DEFAULT + +#define EUSART_IF_MPAFIF EUSART_IF_MPAF +#define _EUSART_IF_MPAFIF_SHIFT _EUSART_IF_MPAF_SHIFT +#define _EUSART_IF_MPAFIF_MASK _EUSART_IF_MPAF_MASK +#define _EUSART_IF_MPAFIF_DEFAULT _EUSART_IF_MPAF_DEFAULT +#define EUSART_IF_MPAFIF_DEFAULT EUSART_IF_MPAF_DEFAULT + +#define EUSART_IF_CCFIF EUSART_IF_CCF +#define _EUSART_IF_CCFIF_SHIFT _EUSART_IF_CCF_SHIFT +#define _EUSART_IF_CCFIF_MASK _EUSART_IF_CCF_MASK +#define _EUSART_IF_CCFIF_DEFAULT _EUSART_IF_CCF_DEFAULT +#define EUSART_IF_CCFIF_DEFAULT EUSART_IF_CCF_DEFAULT + +#define EUSART_IF_TXIDLEIF EUSART_IF_TXIDLE +#define _EUSART_IF_TXIDLEIF_SHIFT _EUSART_IF_TXIDLE_SHIFT +#define _EUSART_IF_TXIDLEIF_MASK _EUSART_IF_TXIDLE_MASK +#define _EUSART_IF_TXIDLEIF_DEFAULT _EUSART_IF_TXIDLE_DEFAULT +#define EUSART_IF_TXIDLEIF_DEFAULT EUSART_IF_TXIDLE_DEFAULT + +#define EUSART_IF_STARTFIF EUSART_IF_STARTF +#define _EUSART_IF_STARTFIF_SHIFT _EUSART_IF_STARTF_SHIFT +#define _EUSART_IF_STARTFIF_MASK _EUSART_IF_STARTF_MASK +#define _EUSART_IF_STARTFIF_DEFAULT _EUSART_IF_STARTF_DEFAULT +#define EUSART_IF_STARTFIF_DEFAULT EUSART_IF_STARTF_DEFAULT + +#define EUSART_IF_SIGFIF EUSART_IF_SIGF +#define _EUSART_IF_SIGFIF_SHIFT _EUSART_IF_SIGF_SHIFT +#define _EUSART_IF_SIGFIF_MASK _EUSART_IF_SIGF_MASK +#define _EUSART_IF_SIGFIF_DEFAULT _EUSART_IF_SIGF_DEFAULT +#define EUSART_IF_SIGFIF_DEFAULT EUSART_IF_SIGF_DEFAULT + +#define EUSART_IF_AUTOBAUDDONEIF EUSART_IF_AUTOBAUDDONE +#define _EUSART_IF_AUTOBAUDDONEIF_SHIFT _EUSART_IF_AUTOBAUDDONE_SHIFT +#define _EUSART_IF_AUTOBAUDDONEIF_MASK _EUSART_IF_AUTOBAUDDONE_MASK +#define _EUSART_IF_AUTOBAUDDONEIF_DEFAULT _EUSART_IF_AUTOBAUDDONE_DEFAULT +#define EUSART_IF_AUTOBAUDDONEIF_DEFAULT EUSART_IF_AUTOBAUDDONE_DEFAULT + +#define EUSART_IEN_TXCIEN EUSART_IEN_TXC +#define _EUSART_IEN_TXCIEN_SHIFT _EUSART_IEN_TXC_SHIFT +#define _EUSART_IEN_TXCIEN_MASK _EUSART_IEN_TXC_MASK +#define _EUSART_IEN_TXCIEN_DEFAULT _EUSART_IEN_TXC_DEFAULT +#define EUSART_IEN_TXCIEN_DEFAULT EUSART_IEN_TXC_DEFAULT + +#define EUSART_IEN_TXFLIEN EUSART_IEN_TXFL +#define _EUSART_IEN_TXFLIEN_SHIFT _EUSART_IEN_TXFL_SHIFT +#define _EUSART_IEN_TXFLIEN_MASK _EUSART_IEN_TXFL_MASK +#define _EUSART_IEN_TXFLIEN_DEFAULT _EUSART_IEN_TXFL_DEFAULT +#define EUSART_IEN_TXFLIEN_DEFAULT EUSART_IEN_TXFL_DEFAULT + +#define EUSART_IEN_RXFLIEN EUSART_IEN_RXFL +#define _EUSART_IEN_RXFLIEN_SHIFT _EUSART_IEN_RXFL_SHIFT +#define _EUSART_IEN_RXFLIEN_MASK _EUSART_IEN_RXFL_MASK +#define _EUSART_IEN_RXFLIEN_DEFAULT _EUSART_IEN_RXFL_DEFAULT +#define EUSART_IEN_RXFLIEN_DEFAULT EUSART_IEN_RXFL_DEFAULT + +#define EUSART_IEN_RXFULLIEN EUSART_IEN_RXFULL +#define _EUSART_IEN_RXFULLIEN_SHIFT _EUSART_IEN_RXFULL_SHIFT +#define _EUSART_IEN_RXFULLIEN_MASK _EUSART_IEN_RXFULL_MASK +#define _EUSART_IEN_RXFULLIEN_DEFAULT _EUSART_IEN_RXFULL_DEFAULT +#define EUSART_IEN_RXFULLIEN_DEFAULT EUSART_IEN_RXFULL_DEFAULT + +#define EUSART_IEN_RXOFIEN EUSART_IEN_RXOF +#define _EUSART_IEN_RXOFIEN_SHIFT _EUSART_IEN_RXOF_SHIFT +#define _EUSART_IEN_RXOFIEN_MASK _EUSART_IEN_RXOF_MASK +#define _EUSART_IEN_RXOFIEN_DEFAULT _EUSART_IEN_RXOF_DEFAULT +#define EUSART_IEN_RXOFIEN_DEFAULT EUSART_IEN_RXOF_DEFAULT + +#define EUSART_IEN_RXUFIEN EUSART_IEN_RXUF +#define _EUSART_IEN_RXUFIEN_SHIFT _EUSART_IEN_RXUF_SHIFT +#define _EUSART_IEN_RXUFIEN_MASK _EUSART_IEN_RXUF_MASK +#define _EUSART_IEN_RXUFIEN_DEFAULT _EUSART_IEN_RXUF_DEFAULT +#define EUSART_IEN_RXUFIEN_DEFAULT EUSART_IEN_RXUF_DEFAULT + +#define EUSART_IEN_TXOFIEN EUSART_IEN_TXOF +#define _EUSART_IEN_TXOFIEN_SHIFT _EUSART_IEN_TXOF_SHIFT +#define _EUSART_IEN_TXOFIEN_MASK _EUSART_IEN_TXOF_MASK +#define _EUSART_IEN_TXOFIEN_DEFAULT _EUSART_IEN_TXOF_DEFAULT +#define EUSART_IEN_TXOFIEN_DEFAULT EUSART_IEN_TXOF_DEFAULT + +#define EUSART_IEN_PERRIEN EUSART_IEN_PERR +#define _EUSART_IEN_PERRIEN_SHIFT _EUSART_IEN_PERR_SHIFT +#define _EUSART_IEN_PERRIEN_MASK _EUSART_IEN_PERR_MASK +#define _EUSART_IEN_PERRIEN_DEFAULT _EUSART_IEN_PERR_DEFAULT +#define EUSART_IEN_PERRIEN_DEFAULT EUSART_IEN_PERR_DEFAULT + +#define EUSART_IEN_FERRIEN EUSART_IEN_FERR +#define _EUSART_IEN_FERRIEN_SHIFT _EUSART_IEN_FERR_SHIFT +#define _EUSART_IEN_FERRIEN_MASK _EUSART_IEN_FERR_MASK +#define _EUSART_IEN_FERRIEN_DEFAULT _EUSART_IEN_FERR_DEFAULT +#define EUSART_IEN_FERRIEN_DEFAULT EUSART_IEN_FERR_DEFAULT + +#define EUSART_IEN_MPAFIEN EUSART_IEN_MPAF +#define _EUSART_IEN_MPAFIEN_SHIFT _EUSART_IEN_MPAF_SHIFT +#define _EUSART_IEN_MPAFIEN_MASK _EUSART_IEN_MPAF_MASK +#define _EUSART_IEN_MPAFIEN_DEFAULT _EUSART_IEN_MPAF_DEFAULT +#define EUSART_IEN_MPAFIEN_DEFAULT EUSART_IEN_MPAF_DEFAULT + +#define EUSART_IEN_CCFIEN EUSART_IEN_CCF +#define _EUSART_IEN_CCFIEN_SHIFT _EUSART_IEN_CCF_SHIFT +#define _EUSART_IEN_CCFIEN_MASK _EUSART_IEN_CCF_MASK +#define _EUSART_IEN_CCFIEN_DEFAULT _EUSART_IEN_CCF_DEFAULT +#define EUSART_IEN_CCFIEN_DEFAULT EUSART_IEN_CCF_DEFAULT + +#define EUSART_IEN_TXIDLEIEN EUSART_IEN_TXIDLE +#define _EUSART_IEN_TXIDLEIEN_SHIFT _EUSART_IEN_TXIDLE_SHIFT +#define _EUSART_IEN_TXIDLEIEN_MASK _EUSART_IEN_TXIDLE_MASK +#define _EUSART_IEN_TXIDLEIEN_DEFAULT _EUSART_IEN_TXIDLE_DEFAULT +#define EUSART_IEN_TXIDLEIEN_DEFAULT EUSART_IEN_TXIDLE_DEFAULT + +#define EUSART_IEN_STARTFIEN EUSART_IEN_STARTF +#define _EUSART_IEN_STARTFIEN_SHIFT _EUSART_IEN_STARTF_SHIFT +#define _EUSART_IEN_STARTFIEN_MASK _EUSART_IEN_STARTF_MASK +#define _EUSART_IEN_STARTFIEN_DEFAULT _EUSART_IEN_STARTF_DEFAULT +#define EUSART_IEN_STARTFIEN_DEFAULT EUSART_IEN_STARTF_DEFAULT + +#define EUSART_IEN_SIGFIEN EUSART_IEN_SIGF +#define _EUSART_IEN_SIGFIEN_SHIFT _EUSART_IEN_SIGF_SHIFT +#define _EUSART_IEN_SIGFIEN_MASK _EUSART_IEN_SIGF_MASK +#define _EUSART_IEN_SIGFIEN_DEFAULT _EUSART_IEN_SIGF_DEFAULT +#define EUSART_IEN_SIGFIEN_DEFAULT EUSART_IEN_SIGF_DEFAULT + +#define EUSART_IEN_AUTOBAUDDONEIEN EUSART_IEN_AUTOBAUDDONE +#define _EUSART_IEN_AUTOBAUDDONEIEN_SHIFT _EUSART_IEN_AUTOBAUDDONE_SHIFT +#define _EUSART_IEN_AUTOBAUDDONEIEN_MASK _EUSART_IEN_AUTOBAUDDONE_MASK +#define _EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT _EUSART_IEN_AUTOBAUDDONE_DEFAULT +#define EUSART_IEN_AUTOBAUDDONEIEN_DEFAULT EUSART_IEN_AUTOBAUDDONE_DEFAULT + +#endif // _SILICON_LABS_32B_SERIES_2_CONFIG_2 + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h index 64f7d19..d20c9e2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpcrc.h @@ -1,346 +1,346 @@ -/***************************************************************************//** - * @file - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_GPCRC_H -#define EM_GPCRC_H - -#include "em_bus.h" -#include "em_device.h" -#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup gpcrc GPCRC - General Purpose CRC - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API - * - * @details - * The GPCRC API functions provide full support for the GPCRC peripheral. - * - * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check - * (CRC) function. It supports a fixed 32-bit polynomial and a user - * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly - * used IEEE 802.3 polynomial 0x04C11DB7. - * - * When using a 16-bit polynomial it is up to the user to choose a polynomial - * that fits the application. Commonly used 16-bit polynomials are 0x1021 - * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). - * See this link for other polynomials: - * https://en.wikipedia.org/wiki/Cyclic_redundancy_check - * - * Before a CRC calculation can begin, call the - * @ref GPCRC_Start function. This function will reset CRC calculation - * by copying the configured initialization value over to the CRC data register. - * - * There are two ways of sending input data to the GPCRC. Either write - * the input data into the input data register using input functions - * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the - * user can configure @ref ldma to transfer data directly to one of the GPCRC - * input data registers. - * - * Examples of GPCRC usage: - * - * A CRC-32 Calculation: - * - * @include em_gpcrc_crc32.c - * - * A CRC-16 Calculation: - * - * @include em_gpcrc_crc16.c - * - * A CRC-CCITT calculation: - * - * @include em_gpcrc_ccit.c - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** CRC initialization structure. */ -typedef struct { - /** - * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial - * or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial - * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the - * 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field. - * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 - * bits are zero. - * - * The polynomial should be written in normal bit order. For instance, - * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert - * it to hex representation and remove the highest order term - * of the polynomial. This will give 0x8005 as the value to write into - * crcPoly. - */ - uint32_t crcPoly; - - /** - * CRC initialization value. This value is assigned to the GPCRC_INIT register. - * The initValue is loaded into the data register when calling the - * @ref GPCRC_Start function or when one of the data registers are read - * while @ref autoInit is enabled. - */ - uint32_t initValue; - - /** - * Reverse byte order. This has an effect when sending a 32-bit word or - * 16-bit half word input to the CRC calculation. When set to true, the input - * bytes are reversed before entering the CRC calculation. When set to - * false, the input bytes stay in the same order. - */ - bool reverseByteOrder; - - /** - * Reverse bits within each input byte. This setting enables or disables byte - * level bit reversal. When byte-level bit reversal is enabled, then each byte - * of input data will be reversed before entering CRC calculation. - */ - bool reverseBits; - - /** - * Enable/disable byte mode. When byte mode is enabled, then all input - * is treated as single byte input even though the input is a 32-bit word - * or a 16-bit half word. Only the least significant byte of the data-word - * will be used for CRC calculation for all writes. - */ - bool enableByteMode; - - /** - * Enable automatic initialization by re-seeding the CRC result based on - * the init value after reading one of the CRC data registers. - */ - bool autoInit; - - /** Enable/disable GPCRC when initialization is completed. */ - bool enable; -} GPCRC_Init_TypeDef; - -/** Default configuration for GPCRC_Init_TypeDef structure. */ -#define GPCRC_INIT_DEFAULT \ - { \ - 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ - 0x00000000UL, /* Initialization value. */ \ - false, /* Byte order is normal. */ \ - false, /* Bit order is not reversed on output. */ \ - false, /* Disable byte mode. */ \ - false, /* Disable automatic initialization on data read. */ \ - true, /* Enable GPCRC. */ \ - } - -/******************************************************************************* - ****************************** PROTOTYPES ********************************* - ******************************************************************************/ - -void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); -void GPCRC_Reset(GPCRC_TypeDef * gpcrc); - -/***************************************************************************//** - * @brief - * Enable/disable GPCRC. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] enable - * True to enable GPCRC, false to disable. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) -{ -#if defined(GPCRC_EN_EN) - BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); -#else - BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); -#endif -} - -/***************************************************************************//** - * @brief - * Issue a command to initialize the CRC calculation. - * - * @details - * Issues the command INIT in GPCRC_CMD that initializes the - * CRC calculation by writing the initial values to the DATA register. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) -{ - gpcrc->CMD = GPCRC_CMD_INIT; -} - -/***************************************************************************//** - * @brief - * Set the initialization value of the CRC. - * - * @param [in] initValue - * Value to use to initialize a CRC calculation. This value is moved into - * the data register when calling @ref GPCRC_Start - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) -{ - gpcrc->INIT = initValue; -} - -/***************************************************************************//** - * @brief - * Write a 32-bit value to the input data register of the CRC. - * - * @details - * Use this function to write a 32-bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) -{ - gpcrc->INPUTDATA = data; -} - -/***************************************************************************//** - * @brief - * Write a 16-bit value to the input data register of the CRC. - * - * @details - * Use this function to write a 16 bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) -{ - gpcrc->INPUTDATAHWORD = data; -} - -/***************************************************************************//** - * @brief - * Write an 8-bit value to the CRC input data register. - * - * @details - * Use this function to write an 8-bit input data to the CRC. CRC - * calculation is based on the provided input data using the configured - * CRC polynomial. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @param[in] data - * Data to be written to the input data register. - ******************************************************************************/ -__STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) -{ - gpcrc->INPUTDATABYTE = data; -} - -/***************************************************************************//** - * @brief - * Read the CRC data register. - * - * @details - * Use this function to read the calculated CRC value. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATA; -} - -/***************************************************************************//** - * @brief - * Read the data register of the CRC bit reversed. - * - * @details - * Use this function to read the calculated CRC value bit reversed. When - * using a 32-bit polynomial, bits [31:0] are reversed, when using a - * 16-bit polynomial, bits [15:0] are reversed. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register bit reversed. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATAREV; -} - -/***************************************************************************//** - * @brief - * Read the data register of the CRC byte reversed. - * - * @details - * Use this function to read the calculated CRC value byte reversed. - * - * @param[in] gpcrc - * Pointer to GPCRC peripheral register block. - * - * @return - * Content of the CRC data register byte reversed. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) -{ - return gpcrc->DATABYTEREV; -} - -/** @} (end addtogroup gpcrc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ -#endif /* EM_GPCRC_H */ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPCRC_H +#define EM_GPCRC_H + +#include "em_bus.h" +#include "em_device.h" +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup gpcrc GPCRC - General Purpose CRC + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API + * + * @details + * The GPCRC API functions provide full support for the GPCRC peripheral. + * + * The GPCRC module is a peripheral that implements a Cyclic Redundancy Check + * (CRC) function. It supports a fixed 32-bit polynomial and a user + * configurable 16-bit polynomial. The fixed 32-bit polynomial is the commonly + * used IEEE 802.3 polynomial 0x04C11DB7. + * + * When using a 16-bit polynomial it is up to the user to choose a polynomial + * that fits the application. Commonly used 16-bit polynomials are 0x1021 + * (CCITT-16), 0x3D65 (IEC16-MBus), and 0x8005 (ZigBee, 802.15.4, and USB). + * See this link for other polynomials: + * https://en.wikipedia.org/wiki/Cyclic_redundancy_check + * + * Before a CRC calculation can begin, call the + * @ref GPCRC_Start function. This function will reset CRC calculation + * by copying the configured initialization value over to the CRC data register. + * + * There are two ways of sending input data to the GPCRC. Either write + * the input data into the input data register using input functions + * @ref GPCRC_InputU32, @ref GPCRC_InputU16 and @ref GPCRC_InputU8, or the + * user can configure @ref ldma to transfer data directly to one of the GPCRC + * input data registers. + * + * Examples of GPCRC usage: + * + * A CRC-32 Calculation: + * + * @include em_gpcrc_crc32.c + * + * A CRC-16 Calculation: + * + * @include em_gpcrc_crc16.c + * + * A CRC-CCITT calculation: + * + * @include em_gpcrc_ccit.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** CRC initialization structure. */ +typedef struct { + /** + * CRC polynomial value. GPCRC supports either a fixed 32-bit polynomial + * or a user-configurable 16 bit polynomial. The fixed 32-bit polynomial + * is the one used in IEEE 802.3, which has the value 0x04C11DB7. To use the + * 32-bit fixed polynomial, assign 0x04C11DB7 to the crcPoly field. + * To use a 16-bit polynomial, assign a value to crcPoly where the upper 16 + * bits are zero. + * + * The polynomial should be written in normal bit order. For instance, + * to use the CRC-16 polynomial X^16 + X^15 + X^2 + 1, first convert + * it to hex representation and remove the highest order term + * of the polynomial. This will give 0x8005 as the value to write into + * crcPoly. + */ + uint32_t crcPoly; + + /** + * CRC initialization value. This value is assigned to the GPCRC_INIT register. + * The initValue is loaded into the data register when calling the + * @ref GPCRC_Start function or when one of the data registers are read + * while @ref autoInit is enabled. + */ + uint32_t initValue; + + /** + * Reverse byte order. This has an effect when sending a 32-bit word or + * 16-bit half word input to the CRC calculation. When set to true, the input + * bytes are reversed before entering the CRC calculation. When set to + * false, the input bytes stay in the same order. + */ + bool reverseByteOrder; + + /** + * Reverse bits within each input byte. This setting enables or disables byte + * level bit reversal. When byte-level bit reversal is enabled, then each byte + * of input data will be reversed before entering CRC calculation. + */ + bool reverseBits; + + /** + * Enable/disable byte mode. When byte mode is enabled, then all input + * is treated as single byte input even though the input is a 32-bit word + * or a 16-bit half word. Only the least significant byte of the data-word + * will be used for CRC calculation for all writes. + */ + bool enableByteMode; + + /** + * Enable automatic initialization by re-seeding the CRC result based on + * the init value after reading one of the CRC data registers. + */ + bool autoInit; + + /** Enable/disable GPCRC when initialization is completed. */ + bool enable; +} GPCRC_Init_TypeDef; + +/** Default configuration for GPCRC_Init_TypeDef structure. */ +#define GPCRC_INIT_DEFAULT \ + { \ + 0x04C11DB7UL, /* CRC32 Polynomial value. */ \ + 0x00000000UL, /* Initialization value. */ \ + false, /* Byte order is normal. */ \ + false, /* Bit order is not reversed on output. */ \ + false, /* Disable byte mode. */ \ + false, /* Disable automatic initialization on data read. */ \ + true, /* Enable GPCRC. */ \ + } + +/******************************************************************************* + ****************************** PROTOTYPES ********************************* + ******************************************************************************/ + +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init); +void GPCRC_Reset(GPCRC_TypeDef * gpcrc); + +/***************************************************************************//** + * @brief + * Enable/disable GPCRC. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] enable + * True to enable GPCRC, false to disable. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Enable(GPCRC_TypeDef * gpcrc, bool enable) +{ +#if defined(GPCRC_EN_EN) + BUS_RegBitWrite(&gpcrc->EN, _GPCRC_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&gpcrc->CTRL, _GPCRC_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Issue a command to initialize the CRC calculation. + * + * @details + * Issues the command INIT in GPCRC_CMD that initializes the + * CRC calculation by writing the initial values to the DATA register. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_Start(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CMD = GPCRC_CMD_INIT; +} + +/***************************************************************************//** + * @brief + * Set the initialization value of the CRC. + * + * @param [in] initValue + * Value to use to initialize a CRC calculation. This value is moved into + * the data register when calling @ref GPCRC_Start + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InitValueSet(GPCRC_TypeDef * gpcrc, uint32_t initValue) +{ + gpcrc->INIT = initValue; +} + +/***************************************************************************//** + * @brief + * Write a 32-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 32-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU32(GPCRC_TypeDef * gpcrc, uint32_t data) +{ + gpcrc->INPUTDATA = data; +} + +/***************************************************************************//** + * @brief + * Write a 16-bit value to the input data register of the CRC. + * + * @details + * Use this function to write a 16 bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU16(GPCRC_TypeDef * gpcrc, uint16_t data) +{ + gpcrc->INPUTDATAHWORD = data; +} + +/***************************************************************************//** + * @brief + * Write an 8-bit value to the CRC input data register. + * + * @details + * Use this function to write an 8-bit input data to the CRC. CRC + * calculation is based on the provided input data using the configured + * CRC polynomial. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @param[in] data + * Data to be written to the input data register. + ******************************************************************************/ +__STATIC_INLINE void GPCRC_InputU8(GPCRC_TypeDef * gpcrc, uint8_t data) +{ + gpcrc->INPUTDATABYTE = data; +} + +/***************************************************************************//** + * @brief + * Read the CRC data register. + * + * @details + * Use this function to read the calculated CRC value. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataRead(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATA; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC bit reversed. + * + * @details + * Use this function to read the calculated CRC value bit reversed. When + * using a 32-bit polynomial, bits [31:0] are reversed, when using a + * 16-bit polynomial, bits [15:0] are reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register bit reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadBitReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATAREV; +} + +/***************************************************************************//** + * @brief + * Read the data register of the CRC byte reversed. + * + * @details + * Use this function to read the calculated CRC value byte reversed. + * + * @param[in] gpcrc + * Pointer to GPCRC peripheral register block. + * + * @return + * Content of the CRC data register byte reversed. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPCRC_DataReadByteReversed(GPCRC_TypeDef * gpcrc) +{ + return gpcrc->DATABYTEREV; +} + +/** @} (end addtogroup gpcrc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ +#endif /* EM_GPCRC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h index db31760..50e980c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_gpio.h @@ -1,1295 +1,1295 @@ -/***************************************************************************//** - * @file - * @brief General Purpose IO (GPIO) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_GPIO_H -#define EM_GPIO_H - -#include "em_device.h" -#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "sl_common.h" -#include "sl_enum.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 14 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 9 -#define _GPIO_PORT_E_PIN_COUNT 12 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xF77FUL -#define _GPIO_PORT_B_PIN_MASK 0x79F8UL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0x01FFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_EFM32_HAPPY_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 12 -#define _GPIO_PORT_D_PIN_COUNT 4 -#define _GPIO_PORT_E_PIN_COUNT 4 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x0707UL -#define _GPIO_PORT_B_PIN_MASK 0x6980UL -#define _GPIO_PORT_C_PIN_MASK 0xEF1FUL -#define _GPIO_PORT_D_PIN_MASK 0x00F0UL -#define _GPIO_PORT_E_PIN_MASK 0x3C00UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 13 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x1FFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_EFM32_GECKO_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 10 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x03FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - -#define _GPIO_PORT_A_PIN_COUNT 10 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 12 -#define _GPIO_PORT_D_PIN_COUNT 8 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 16 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 4 -#define _GPIO_PORT_J_PIN_COUNT 2 -#define _GPIO_PORT_K_PIN_COUNT 3 - -#define _GPIO_PORT_A_PIN_MASK 0x03FFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFC0UL -#define _GPIO_PORT_C_PIN_MASK 0x0FFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFF00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x000FUL -#define _GPIO_PORT_J_PIN_MASK 0xC000UL -#define _GPIO_PORT_K_PIN_MASK 0x0007UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 15 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0x7FFFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) - -#define _GPIO_PORT_A_PIN_COUNT 16 -#define _GPIO_PORT_B_PIN_COUNT 16 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 16 -#define _GPIO_PORT_E_PIN_COUNT 16 -#define _GPIO_PORT_F_PIN_COUNT 16 -#define _GPIO_PORT_G_PIN_COUNT 16 -#define _GPIO_PORT_H_PIN_COUNT 16 -#define _GPIO_PORT_I_PIN_COUNT 16 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_G_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_H_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_I_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - -#define _GPIO_PORT_A_PIN_COUNT 6 -#define _GPIO_PORT_B_PIN_COUNT 5 -#define _GPIO_PORT_C_PIN_COUNT 6 -#define _GPIO_PORT_D_PIN_COUNT 7 -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 8 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0x003FUL -#define _GPIO_PORT_B_PIN_MASK 0xF800UL -#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL -#define _GPIO_PORT_D_PIN_MASK 0xFE00UL -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x00FFUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - -#define _GPIO_PORT_A_PIN_COUNT 14 -#define _GPIO_PORT_B_PIN_COUNT 10 -#define _GPIO_PORT_C_PIN_COUNT 16 -#define _GPIO_PORT_D_PIN_COUNT 9 -#define _GPIO_PORT_E_PIN_COUNT 12 -#define _GPIO_PORT_F_PIN_COUNT 6 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK 0xF77FUL -#define _GPIO_PORT_B_PIN_MASK 0x79F8UL -#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL -#define _GPIO_PORT_D_PIN_MASK 0x01FFUL -#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL -#define _GPIO_PORT_F_PIN_MASK 0x003FUL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#elif defined (_SILICON_LABS_32B_SERIES_2) - -#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT -#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT -#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT -#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT -#define _GPIO_PORT_E_PIN_COUNT 0 -#define _GPIO_PORT_F_PIN_COUNT 0 -#define _GPIO_PORT_G_PIN_COUNT 0 -#define _GPIO_PORT_H_PIN_COUNT 0 -#define _GPIO_PORT_I_PIN_COUNT 0 -#define _GPIO_PORT_J_PIN_COUNT 0 -#define _GPIO_PORT_K_PIN_COUNT 0 - -#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) -#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) -#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) -#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) -#define _GPIO_PORT_E_PIN_MASK 0x0000UL -#define _GPIO_PORT_F_PIN_MASK 0x0000UL -#define _GPIO_PORT_G_PIN_MASK 0x0000UL -#define _GPIO_PORT_H_PIN_MASK 0x0000UL -#define _GPIO_PORT_I_PIN_MASK 0x0000UL -#define _GPIO_PORT_J_PIN_MASK 0x0000UL -#define _GPIO_PORT_K_PIN_MASK 0x0000UL - -#else -#warning "Port and pin masks are not defined for this family." -#endif - -#define _GPIO_PORT_SIZE(port) ( \ - (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ - : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ - : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ - : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ - : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ - : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ - : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ - : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ - : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ - : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ - : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ - : 0) - -#define _GPIO_PORT_MASK(port) ( \ - ((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ - : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ - : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ - : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ - : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ - : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ - : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ - : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ - : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ - : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ - : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ - : 0UL) - -/** Validation of port and pin. */ -#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) -#define GPIO_PORT_PIN_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) - -#if defined(_GPIO_EXTIPINSELL_MASK) -/** Validation of interrupt number and pin. */ -#define GPIO_INTNO_PIN_VALID(intNo, pin) \ - (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ - == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) -#endif - -/** Highest GPIO pin number. */ -#define GPIO_PIN_MAX 15 - -/** Highest GPIO port number. */ -#if (_GPIO_PORT_K_PIN_COUNT > 0) -#define GPIO_PORT_MAX 10 -#elif (_GPIO_PORT_J_PIN_COUNT > 0) -#define GPIO_PORT_MAX 9 -#elif (_GPIO_PORT_I_PIN_COUNT > 0) -#define GPIO_PORT_MAX 8 -#elif (_GPIO_PORT_H_PIN_COUNT > 0) -#define GPIO_PORT_MAX 7 -#elif (_GPIO_PORT_G_PIN_COUNT > 0) -#define GPIO_PORT_MAX 6 -#elif (_GPIO_PORT_F_PIN_COUNT > 0) -#define GPIO_PORT_MAX 5 -#elif (_GPIO_PORT_E_PIN_COUNT > 0) -#define GPIO_PORT_MAX 4 -#elif (_GPIO_PORT_D_PIN_COUNT > 0) -#define GPIO_PORT_MAX 3 -#else -#error "Max GPIO port number is undefined for this part." -#endif - -/** Highest EXT GPIO interrupt number. */ -#define GPIO_EXTINTNO_MAX 15 - -/***************************************************************************//** - * @addtogroup gpio - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** GPIO ports IDs. */ -SL_ENUM(GPIO_Port_TypeDef) { -#if (_GPIO_PORT_A_PIN_COUNT > 0) - /** Port A. */ - gpioPortA = 0, -#endif -#if (_GPIO_PORT_B_PIN_COUNT > 0) - /** Port B. */ - gpioPortB = 1, -#endif -#if (_GPIO_PORT_C_PIN_COUNT > 0) - /** Port C. */ - gpioPortC = 2, -#endif -#if (_GPIO_PORT_D_PIN_COUNT > 0) - /** Port D. */ - gpioPortD = 3, -#endif -#if (_GPIO_PORT_E_PIN_COUNT > 0) - /** Port E. */ - gpioPortE = 4, -#endif -#if (_GPIO_PORT_F_PIN_COUNT > 0) - /** Port F. */ - gpioPortF = 5, -#endif -#if (_GPIO_PORT_G_PIN_COUNT > 0) - /** Port G. */ - gpioPortG = 6, -#endif -#if (_GPIO_PORT_H_PIN_COUNT > 0) - /** Port H. */ - gpioPortH = 7, -#endif -#if (_GPIO_PORT_I_PIN_COUNT > 0) - /** Port I. */ - gpioPortI = 8, -#endif -#if (_GPIO_PORT_J_PIN_COUNT > 0) - /** Port J. */ - gpioPortJ = 9, -#endif -#if (_GPIO_PORT_K_PIN_COUNT > 0) - /** Port K. */ - gpioPortK = 10, -#endif -}; - -#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) -/** GPIO drive mode. */ -SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { - /** Default 6mA. */ - gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, - /** 0.5 mA. */ - gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, - /** 20 mA. */ - gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, - /** 2 mA. */ - gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW -}; -#endif - -#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) -/** GPIO drive strength. */ -SL_ENUM_GENERIC(GPIO_DriveStrength_TypeDef, uint32_t) { - /** GPIO weak 1mA and alternate function weak 1mA. */ - gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, - - /** GPIO weak 1mA and alternate function strong 10mA. */ - gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, - - /** GPIO strong 10mA and alternate function weak 1mA. */ - gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, - - /** GPIO strong 10mA and alternate function strong 10mA. */ - gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, -}; - -/* Deprecated enums. */ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong -#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak -/** @endcond */ -#endif - -/** Pin mode. For more details on each mode, refer to the - * reference manual. */ -SL_ENUM_GENERIC(GPIO_Mode_TypeDef, uint32_t) { - /** Input disabled. Pull-up if DOUT is set. */ - gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, - /** Input enabled. Filter if DOUT is set. */ - gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, - /** Input enabled. DOUT determines pull direction. */ - gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, - /** Input enabled with filter. DOUT determines pull direction. */ - gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, - /** Push-pull output. */ - gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, -#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) - /** Push-pull output with drive-strength set by DRIVEMODE. */ - gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, -#endif -#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) - /** Push-pull using alternate control. */ - gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, -#endif - /** Wired-or output. */ - gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, - /** Wired-or output with pull-down. */ - gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, - /** Open-drain output. */ - gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, - /** Open-drain output with filter. */ - gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, - /** Open-drain output with pull-up. */ - gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, - /** Open-drain output with filter and pull-up. */ - gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, -#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) - /** Open-drain output with drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, - /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, - /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, - /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ - gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER -#endif -#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) - /** Open-drain output using alternate control. */ - gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, - /** Open-drain output using alternate control with filter. */ - gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, - /** Open-drain output using alternate control with pull-up. */ - gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, - /** Open-drain output using alternate control with filter and pull-up. */ - gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, -#endif -}; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void GPIO_DbgLocationSet(unsigned int location); - -/***************************************************************************//** - * @brief - * Enable/disable serial wire clock pin. - * - * @note - * Disabling SWDClk will disable the debug interface, which may result in - * a lockout if done early in startup (before debugger is able to halt core). - * - * @param[in] enable - * @li false - disable serial wire clock. - * @li true - enable serial wire clock (default after reset). - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWCLKPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); -#elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) - BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWCLK pin is not defined." -#endif -} - -/***************************************************************************//** - * @brief - * Enable/disable serial wire data I/O pin. - * - * @note - * Disabling SWDClk will disable the debug interface, which may result in - * a lockout if done early in startup (before debugger is able to halt core). - * - * @param[in] enable - * @li false - disable serial wire data pin. - * @li true - enable serial wire data pin (default after reset). - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWDIOPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); -#elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) - BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWDIO pin is not defined." -#endif -} - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ - || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) -/***************************************************************************//** - * @brief - * Enable/Disable serial wire output pin. - * - * @note - * Enabling this pin is not sufficient to fully enable serial wire output, - * which is also dependent on issues outside the GPIO module. Refer to - * DBG_SWOEnable(). - * - * @warning - * If debug port is locked, SWO pin is not disabled automatically. To avoid - * information leakage through SWO, disable SWO pin after locking debug port. - * - * @param[in] enable - * @li false - disable serial wire viewer pin (default after reset). - * @li true - enable serial wire viewer pin. - ******************************************************************************/ -__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) -{ - unsigned int bit = enable ? 0x1UL : 0x0UL; - -#if defined(_GPIO_ROUTE_SWOPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); -#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) - BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); -#elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) - BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); -#else -#warning "ROUTE enable for SWO/SWV pin is not defined." -#endif -} -#endif - -#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) -void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); -#endif - -#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) -void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); -#endif - -# if defined(_GPIO_EM4WUEN_MASK) -/**************************************************************************//** - * @brief - * Disable GPIO pin wake-up from EM4. - * - * @param[in] pinmask - * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. - * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. - *****************************************************************************/ -__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) -{ - EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); - - GPIO->EM4WUEN &= ~pinmask; -} -#endif - -# if defined(_GPIO_EM4WUEN_MASK) -void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); -#endif - -#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) -/**************************************************************************//** - * @brief - * Check which GPIO pin(s) that caused a wake-up from EM4. - * - * @return - * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the - * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. - *****************************************************************************/ -__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) -{ -#if defined(_GPIO_EM4WUCAUSE_MASK) - return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; -#else - return GPIO->IF & _GPIO_IF_EM4WU_MASK; -#endif -} -#endif - -#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) -/**************************************************************************//** - * @brief - * Enable GPIO pin retention of output enable, output value, pull enable, and - * pull direction in EM4. - * - * @note - * On series 0 devices EM4 gpio retention can either be turned on or off. On - * series 1 devices there are three EM4 GPIO retention modes available. These - * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the EMU_EM4Init() - * to configure the GPIO retention mode on a series 1 device. - * - * The behavior of this function depends on the configured GPIO retention mode. - * If the GPIO retention mode is configured to be "SWUNLATCH" then this - * function will not change anything. If the retention mode is anything else - * then this function will set the GPIO retention mode to "EM4EXIT" when the - * enable argument is true, and "Disabled" when false. - * - * @param[in] enable - * @li true - enable EM4 pin retention. - * @li false - disable EM4 pin retention. - *****************************************************************************/ -__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) -{ -#if defined(GPIO_CTRL_EM4RET) - BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); -#else - - // Leave configuration alone when software unlatch is used. - uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; - if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { - return; - } - - if (enable) { - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; - } else { - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | EMU_EM4CTRL_EM4IORETMODE_DISABLE; - } -#endif -} -#endif - -void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - unsigned int intNo, - bool risingEdge, - bool fallingEdge, - bool enable); - -#if _SILICON_LABS_32B_SERIES > 0 -void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - uint32_t intNo, - bool polarity, - bool enable); -#endif -/***************************************************************************//** - * @brief - * Enable/disable input sensing. - * - * @details - * Disabling input sensing if not used, can save some energy consumption. - * - * @param[in] val - * Bitwise logic OR of one or more of: - * @li GPIO_INSENSE_INT - interrupt input sensing. - * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. - * - * @param[in] mask - * Mask containing bitwise logic OR of bits similar as for @p val used to - * indicate which input sense options to disable/enable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) -{ -#if defined(_GPIO_INSENSE_MASK) - BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); -#else - (void) val; - (void) mask; -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending GPIO interrupts. - * - * @param[in] flags - * Bitwise logic OR of GPIO interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntClear(uint32_t flags) -{ -#if defined(GPIO_HAS_SET_CLEAR) - GPIO->IF_CLR = flags; -#else - GPIO->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more GPIO interrupts. - * - * @param[in] flags - * GPIO interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntDisable(uint32_t flags) -{ - BUS_RegMaskedClear(&(GPIO->IEN), flags); -} - -/***************************************************************************//** - * @brief - * Enable one or more GPIO interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * GPIO_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * GPIO interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void GPIO_IntEnable(uint32_t flags) -{ - BUS_RegMaskedSet(&(GPIO->IEN), flags); -} - -/***************************************************************************//** - * @brief - * Get enabled GPIO interrupts. - * - * @return - * Enabled GPIO interrupt sources. - * - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_EnabledIntGet(void) -{ - return GPIO->IEN; -} - -/***************************************************************************//** - * @brief - * Get pending GPIO interrupts. - * - * @return - * GPIO interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_IntGet(void) -{ - return GPIO->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending GPIO interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled GPIO interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in GPIO_IEN register - * and - * - the OR combination of valid interrupt flags in GPIO_IF register. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) -{ - uint32_t tmp; - - /* Store GPIO->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - tmp = GPIO->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return GPIO->IF & tmp; -} - -/**************************************************************************//** - * @brief - * Set one or more pending GPIO interrupts from SW. - * - * @param[in] flags - * GPIO interrupt sources to set to pending. - *****************************************************************************/ -__STATIC_INLINE void GPIO_IntSet(uint32_t flags) -{ -#if defined (GPIO_HAS_SET_CLEAR) - GPIO->IF_SET = flags; -#else - GPIO->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Lock the GPIO configuration. - ******************************************************************************/ -__STATIC_INLINE void GPIO_Lock(void) -{ - GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; -} - -/***************************************************************************//** - * @brief - * Read the pad value for a single pin in a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number to read. - * - * @return - * The pin value, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - return BUS_RegBitRead(&GPIO->P[port].DIN, pin); -} - -#if defined (_GPIO_P_PINLOCKN_MASK) -/***************************************************************************//** - * @brief - * Lock all GPIO configuration settings for a given pin. - * The lock can only be cleared by a chip reset. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number to lock. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) -{ - BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); -} -#endif - -GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, - unsigned int pin); - -void GPIO_PinModeSet(GPIO_Port_TypeDef port, - unsigned int pin, - GPIO_Mode_TypeDef mode, - unsigned int out); - -/***************************************************************************//** - * @brief - * Set a single pin in GPIO data out port register to 0. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to set. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_P_DOUTCLR_MASK) - GPIO->P[port].DOUTCLR = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_CLR[port].DOUT = 1UL << pin; -#else - BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1UL << pin); -#endif -} - -/***************************************************************************//** - * @brief - * Get current setting for a pin in a GPIO port data out register. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to get setting for. - * - * @return - * The DOUT setting for the requested pin, 0 or 1. - ******************************************************************************/ -__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); -} - -/***************************************************************************//** - * @brief - * Set a single pin in GPIO data out register to 1. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to set. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_P_DOUTSET_MASK) - GPIO->P[port].DOUTSET = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_SET[port].DOUT = 1UL << pin; -#else - BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1UL << pin); -#endif -} - -/***************************************************************************//** - * @brief - * Toggle a single pin in GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin to toggle. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - -#if defined (_GPIO_P_DOUTTGL_MASK) - GPIO->P[port].DOUTTGL = 1UL << pin; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_TGL[port].DOUT = 1UL << pin; -#else - GPIO->P[port].DOUT ^= 1UL << pin; -#endif -} - -/***************************************************************************//** - * @brief - * Read the pad values for GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @return - * The pad values for the GPIO port. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - return GPIO->P[port].DIN; -} - -/***************************************************************************//** - * @brief - * Set bits in DOUT register for a port to 0. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask for bits to clear in DOUT register. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined(_GPIO_P_DOUTCLR_MASK) - GPIO->P[port].DOUTCLR = pins; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_CLR[port].DOUT = pins; -#else - BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current setting for a GPIO port data out register. - * - * @param[in] port - * The GPIO port to access. - * - * @return - * The data out setting for the requested port. - ******************************************************************************/ -__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - return GPIO->P[port].DOUT; -} - -/***************************************************************************//** - * @brief - * Set bits GPIO data out register to 1. - * - * @note - * To ensure that the setting takes effect on the respective output pads, the - * pins must be configured properly. If not, it will take effect - * whenever the pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask for bits to set to 1 in DOUT register. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined(_GPIO_P_DOUTSET_MASK) - GPIO->P[port].DOUTSET = pins; -#elif defined(GPIO_HAS_SET_CLEAR) - GPIO->P_SET[port].DOUT = pins; -#else - BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); -#endif -} - -/***************************************************************************//** - * @brief - * Set GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the respective output pads, the - * pins must be configured properly. If not, it will take effect - * whenever the pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] val - * Value to write to port data out register. - * - * @param[in] mask - * Mask indicating which bits to modify. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, - uint32_t val, - uint32_t mask) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - - GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); -} - -/***************************************************************************//** - * @brief - * Toggle pins in GPIO port data out register. - * - * @note - * To ensure that the setting takes effect on the output pad, the pin must - * be configured properly. If not, it will take effect whenever the - * pin has been properly configured. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pins - * Bit mask with pins to toggle. - ******************************************************************************/ -__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); -#if defined (GPIO_HAS_SET_CLEAR) - GPIO->P_TGL[port].DOUT = pins; -#else - GPIO->P[port].DOUTTGL = pins; -#endif -} - -#if defined(_GPIO_P_CTRL_SLEWRATE_MASK) -/***************************************************************************//** - * @brief - * Set slewrate for pins on a GPIO port. - * - * @param[in] port - * The GPIO port to configure. - * - * @param[in] slewrate - * The slewrate to configure for pins on this GPIO port. - * - * @param[in] slewrateAlt - * The slewrate to configure for pins using alternate modes on this GPIO port. - ******************************************************************************/ -__STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, - uint32_t slewrate, - uint32_t slewrateAlt) -{ - EFM_ASSERT(GPIO_PORT_VALID(port)); - EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK - >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); - EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK - >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); - - GPIO->P[port].CTRL = (GPIO->P[port].CTRL - & ~(_GPIO_P_CTRL_SLEWRATE_MASK - | _GPIO_P_CTRL_SLEWRATEALT_MASK)) - | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) - | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); -} -#endif - -/***************************************************************************//** - * @brief - * Unlock the GPIO configuration. - ******************************************************************************/ -__STATIC_INLINE void GPIO_Unlock(void) -{ - GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; -} - -/** @} (end addtogroup gpio) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ -#endif /* EM_GPIO_H */ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_GPIO_H +#define EM_GPIO_H + +#include "em_device.h" +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "sl_enum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_HAPPY_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 4 +#define _GPIO_PORT_E_PIN_COUNT 4 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x0707UL +#define _GPIO_PORT_B_PIN_MASK 0x6980UL +#define _GPIO_PORT_C_PIN_MASK 0xEF1FUL +#define _GPIO_PORT_D_PIN_MASK 0x00F0UL +#define _GPIO_PORT_E_PIN_MASK 0x3C00UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 13 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x1FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_EFM32_GECKO_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 10 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x03FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFM_DEVICE) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + +#define _GPIO_PORT_A_PIN_COUNT 10 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 12 +#define _GPIO_PORT_D_PIN_COUNT 8 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 4 +#define _GPIO_PORT_J_PIN_COUNT 2 +#define _GPIO_PORT_K_PIN_COUNT 3 + +#define _GPIO_PORT_A_PIN_MASK 0x03FFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFC0UL +#define _GPIO_PORT_C_PIN_MASK 0x0FFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFF00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x000FUL +#define _GPIO_PORT_J_PIN_MASK 0xC000UL +#define _GPIO_PORT_K_PIN_MASK 0x0007UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 15 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0x7FFFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_32B_SERIES_1) && defined(_EFM32_GIANT_FAMILY) + +#define _GPIO_PORT_A_PIN_COUNT 16 +#define _GPIO_PORT_B_PIN_COUNT 16 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 16 +#define _GPIO_PORT_E_PIN_COUNT 16 +#define _GPIO_PORT_F_PIN_COUNT 16 +#define _GPIO_PORT_G_PIN_COUNT 16 +#define _GPIO_PORT_H_PIN_COUNT 16 +#define _GPIO_PORT_I_PIN_COUNT 16 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_B_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_F_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_G_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_H_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_I_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + +#define _GPIO_PORT_A_PIN_COUNT 6 +#define _GPIO_PORT_B_PIN_COUNT 5 +#define _GPIO_PORT_C_PIN_COUNT 6 +#define _GPIO_PORT_D_PIN_COUNT 7 +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 8 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0x003FUL +#define _GPIO_PORT_B_PIN_MASK 0xF800UL +#define _GPIO_PORT_C_PIN_MASK 0x0FC0UL +#define _GPIO_PORT_D_PIN_MASK 0xFE00UL +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x00FFUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + +#define _GPIO_PORT_A_PIN_COUNT 14 +#define _GPIO_PORT_B_PIN_COUNT 10 +#define _GPIO_PORT_C_PIN_COUNT 16 +#define _GPIO_PORT_D_PIN_COUNT 9 +#define _GPIO_PORT_E_PIN_COUNT 12 +#define _GPIO_PORT_F_PIN_COUNT 6 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK 0xF77FUL +#define _GPIO_PORT_B_PIN_MASK 0x79F8UL +#define _GPIO_PORT_C_PIN_MASK 0xFFFFUL +#define _GPIO_PORT_D_PIN_MASK 0x01FFUL +#define _GPIO_PORT_E_PIN_MASK 0xFFF0UL +#define _GPIO_PORT_F_PIN_MASK 0x003FUL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#elif defined (_SILICON_LABS_32B_SERIES_2) + +#define _GPIO_PORT_A_PIN_COUNT GPIO_PA_COUNT +#define _GPIO_PORT_B_PIN_COUNT GPIO_PB_COUNT +#define _GPIO_PORT_C_PIN_COUNT GPIO_PC_COUNT +#define _GPIO_PORT_D_PIN_COUNT GPIO_PD_COUNT +#define _GPIO_PORT_E_PIN_COUNT 0 +#define _GPIO_PORT_F_PIN_COUNT 0 +#define _GPIO_PORT_G_PIN_COUNT 0 +#define _GPIO_PORT_H_PIN_COUNT 0 +#define _GPIO_PORT_I_PIN_COUNT 0 +#define _GPIO_PORT_J_PIN_COUNT 0 +#define _GPIO_PORT_K_PIN_COUNT 0 + +#define _GPIO_PORT_A_PIN_MASK (GPIO_PA_MASK) +#define _GPIO_PORT_B_PIN_MASK (GPIO_PB_MASK) +#define _GPIO_PORT_C_PIN_MASK (GPIO_PC_MASK) +#define _GPIO_PORT_D_PIN_MASK (GPIO_PD_MASK) +#define _GPIO_PORT_E_PIN_MASK 0x0000UL +#define _GPIO_PORT_F_PIN_MASK 0x0000UL +#define _GPIO_PORT_G_PIN_MASK 0x0000UL +#define _GPIO_PORT_H_PIN_MASK 0x0000UL +#define _GPIO_PORT_I_PIN_MASK 0x0000UL +#define _GPIO_PORT_J_PIN_MASK 0x0000UL +#define _GPIO_PORT_K_PIN_MASK 0x0000UL + +#else +#warning "Port and pin masks are not defined for this family." +#endif + +#define _GPIO_PORT_SIZE(port) ( \ + (port) == 0 ? _GPIO_PORT_A_PIN_COUNT \ + : (port) == 1 ? _GPIO_PORT_B_PIN_COUNT \ + : (port) == 2 ? _GPIO_PORT_C_PIN_COUNT \ + : (port) == 3 ? _GPIO_PORT_D_PIN_COUNT \ + : (port) == 4 ? _GPIO_PORT_E_PIN_COUNT \ + : (port) == 5 ? _GPIO_PORT_F_PIN_COUNT \ + : (port) == 6 ? _GPIO_PORT_G_PIN_COUNT \ + : (port) == 7 ? _GPIO_PORT_H_PIN_COUNT \ + : (port) == 8 ? _GPIO_PORT_I_PIN_COUNT \ + : (port) == 9 ? _GPIO_PORT_J_PIN_COUNT \ + : (port) == 10 ? _GPIO_PORT_K_PIN_COUNT \ + : 0) + +#define _GPIO_PORT_MASK(port) ( \ + ((int)port) == 0 ? _GPIO_PORT_A_PIN_MASK \ + : ((int)port) == 1 ? _GPIO_PORT_B_PIN_MASK \ + : ((int)port) == 2 ? _GPIO_PORT_C_PIN_MASK \ + : ((int)port) == 3 ? _GPIO_PORT_D_PIN_MASK \ + : ((int)port) == 4 ? _GPIO_PORT_E_PIN_MASK \ + : ((int)port) == 5 ? _GPIO_PORT_F_PIN_MASK \ + : ((int)port) == 6 ? _GPIO_PORT_G_PIN_MASK \ + : ((int)port) == 7 ? _GPIO_PORT_H_PIN_MASK \ + : ((int)port) == 8 ? _GPIO_PORT_I_PIN_MASK \ + : ((int)port) == 9 ? _GPIO_PORT_J_PIN_MASK \ + : ((int)port) == 10 ? _GPIO_PORT_K_PIN_MASK \ + : 0UL) + +/** Validation of port and pin. */ +#define GPIO_PORT_VALID(port) (_GPIO_PORT_MASK(port) != 0x0UL) +#define GPIO_PORT_PIN_VALID(port, pin) ((((_GPIO_PORT_MASK(port)) >> (pin)) & 0x1UL) == 0x1UL) + +#if defined(_GPIO_EXTIPINSELL_MASK) +/** Validation of interrupt number and pin. */ +#define GPIO_INTNO_PIN_VALID(intNo, pin) \ + (((intNo) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) \ + == ((pin) & ~_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)) +#endif + +/** Highest GPIO pin number. */ +#define GPIO_PIN_MAX 15 + +/** Highest GPIO port number. */ +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define GPIO_PORT_MAX 10 +#elif (_GPIO_PORT_J_PIN_COUNT > 0) +#define GPIO_PORT_MAX 9 +#elif (_GPIO_PORT_I_PIN_COUNT > 0) +#define GPIO_PORT_MAX 8 +#elif (_GPIO_PORT_H_PIN_COUNT > 0) +#define GPIO_PORT_MAX 7 +#elif (_GPIO_PORT_G_PIN_COUNT > 0) +#define GPIO_PORT_MAX 6 +#elif (_GPIO_PORT_F_PIN_COUNT > 0) +#define GPIO_PORT_MAX 5 +#elif (_GPIO_PORT_E_PIN_COUNT > 0) +#define GPIO_PORT_MAX 4 +#elif (_GPIO_PORT_D_PIN_COUNT > 0) +#define GPIO_PORT_MAX 3 +#else +#error "Max GPIO port number is undefined for this part." +#endif + +/** Highest EXT GPIO interrupt number. */ +#define GPIO_EXTINTNO_MAX 15 + +/***************************************************************************//** + * @addtogroup gpio + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** GPIO ports IDs. */ +SL_ENUM(GPIO_Port_TypeDef) { +#if (_GPIO_PORT_A_PIN_COUNT > 0) + /** Port A. */ + gpioPortA = 0, +#endif +#if (_GPIO_PORT_B_PIN_COUNT > 0) + /** Port B. */ + gpioPortB = 1, +#endif +#if (_GPIO_PORT_C_PIN_COUNT > 0) + /** Port C. */ + gpioPortC = 2, +#endif +#if (_GPIO_PORT_D_PIN_COUNT > 0) + /** Port D. */ + gpioPortD = 3, +#endif +#if (_GPIO_PORT_E_PIN_COUNT > 0) + /** Port E. */ + gpioPortE = 4, +#endif +#if (_GPIO_PORT_F_PIN_COUNT > 0) + /** Port F. */ + gpioPortF = 5, +#endif +#if (_GPIO_PORT_G_PIN_COUNT > 0) + /** Port G. */ + gpioPortG = 6, +#endif +#if (_GPIO_PORT_H_PIN_COUNT > 0) + /** Port H. */ + gpioPortH = 7, +#endif +#if (_GPIO_PORT_I_PIN_COUNT > 0) + /** Port I. */ + gpioPortI = 8, +#endif +#if (_GPIO_PORT_J_PIN_COUNT > 0) + /** Port J. */ + gpioPortJ = 9, +#endif +#if (_GPIO_PORT_K_PIN_COUNT > 0) + /** Port K. */ + gpioPortK = 10, +#endif +}; + +#if defined(_GPIO_P_CTRL_DRIVEMODE_MASK) +/** GPIO drive mode. */ +SL_ENUM_GENERIC(GPIO_DriveMode_TypeDef, uint32_t) { + /** Default 6mA. */ + gpioDriveModeStandard = GPIO_P_CTRL_DRIVEMODE_STANDARD, + /** 0.5 mA. */ + gpioDriveModeLowest = GPIO_P_CTRL_DRIVEMODE_LOWEST, + /** 20 mA. */ + gpioDriveModeHigh = GPIO_P_CTRL_DRIVEMODE_HIGH, + /** 2 mA. */ + gpioDriveModeLow = GPIO_P_CTRL_DRIVEMODE_LOW +}; +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) && defined(_GPIO_P_CTRL_DRIVESTRENGTHALT_MASK) +/** GPIO drive strength. */ +SL_ENUM_GENERIC(GPIO_DriveStrength_TypeDef, uint32_t) { + /** GPIO weak 1mA and alternate function weak 1mA. */ + gpioDriveStrengthWeakAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO weak 1mA and alternate function strong 10mA. */ + gpioDriveStrengthWeakAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_WEAK | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, + + /** GPIO strong 10mA and alternate function weak 1mA. */ + gpioDriveStrengthStrongAlternateWeak = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_WEAK, + + /** GPIO strong 10mA and alternate function strong 10mA. */ + gpioDriveStrengthStrongAlternateStrong = GPIO_P_CTRL_DRIVESTRENGTH_STRONG | GPIO_P_CTRL_DRIVESTRENGTHALT_STRONG, +}; + +/* Deprecated enums. */ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#define gpioDriveStrengthStrong gpioDriveStrengthStrongAlternateStrong +#define gpioDriveStrengthWeak gpioDriveStrengthWeakAlternateWeak +/** @endcond */ +#endif + +/** Pin mode. For more details on each mode, refer to the + * reference manual. */ +SL_ENUM_GENERIC(GPIO_Mode_TypeDef, uint32_t) { + /** Input disabled. Pull-up if DOUT is set. */ + gpioModeDisabled = _GPIO_P_MODEL_MODE0_DISABLED, + /** Input enabled. Filter if DOUT is set. */ + gpioModeInput = _GPIO_P_MODEL_MODE0_INPUT, + /** Input enabled. DOUT determines pull direction. */ + gpioModeInputPull = _GPIO_P_MODEL_MODE0_INPUTPULL, + /** Input enabled with filter. DOUT determines pull direction. */ + gpioModeInputPullFilter = _GPIO_P_MODEL_MODE0_INPUTPULLFILTER, + /** Push-pull output. */ + gpioModePushPull = _GPIO_P_MODEL_MODE0_PUSHPULL, +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLDRIVE) + /** Push-pull output with drive-strength set by DRIVEMODE. */ + gpioModePushPullDrive = _GPIO_P_MODEL_MODE0_PUSHPULLDRIVE, +#endif +#if defined(_GPIO_P_MODEL_MODE0_PUSHPULLALT) + /** Push-pull using alternate control. */ + gpioModePushPullAlternate = _GPIO_P_MODEL_MODE0_PUSHPULLALT, +#endif + /** Wired-or output. */ + gpioModeWiredOr = _GPIO_P_MODEL_MODE0_WIREDOR, + /** Wired-or output with pull-down. */ + gpioModeWiredOrPullDown = _GPIO_P_MODEL_MODE0_WIREDORPULLDOWN, + /** Open-drain output. */ + gpioModeWiredAnd = _GPIO_P_MODEL_MODE0_WIREDAND, + /** Open-drain output with filter. */ + gpioModeWiredAndFilter = _GPIO_P_MODEL_MODE0_WIREDANDFILTER, + /** Open-drain output with pull-up. */ + gpioModeWiredAndPullUp = _GPIO_P_MODEL_MODE0_WIREDANDPULLUP, + /** Open-drain output with filter and pull-up. */ + gpioModeWiredAndPullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDPULLUPFILTER, +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDDRIVE) + /** Open-drain output with drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrive = _GPIO_P_MODEL_MODE0_WIREDANDDRIVE, + /** Open-drain output with filter and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDriveFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEFILTER, + /** Open-drain output with pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUp = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUP, + /** Open-drain output with filter, pull-up and drive-strength set by DRIVEMODE. */ + gpioModeWiredAndDrivePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDDRIVEPULLUPFILTER +#endif +#if defined(_GPIO_P_MODEL_MODE0_WIREDANDALT) + /** Open-drain output using alternate control. */ + gpioModeWiredAndAlternate = _GPIO_P_MODEL_MODE0_WIREDANDALT, + /** Open-drain output using alternate control with filter. */ + gpioModeWiredAndAlternateFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTFILTER, + /** Open-drain output using alternate control with pull-up. */ + gpioModeWiredAndAlternatePullUp = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUP, + /** Open-drain output using alternate control with filter and pull-up. */ + gpioModeWiredAndAlternatePullUpFilter = _GPIO_P_MODEL_MODE0_WIREDANDALTPULLUPFILTER, +#endif +}; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void GPIO_DbgLocationSet(unsigned int location); + +/***************************************************************************//** + * @brief + * Enable/disable serial wire clock pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire clock. + * @li true - enable serial wire clock (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDClkEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWCLKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWCLKPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWCLKTCKPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWCLKTCKPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWCLK pin is not defined." +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable serial wire data I/O pin. + * + * @note + * Disabling SWDClk will disable the debug interface, which may result in + * a lockout if done early in startup (before debugger is able to halt core). + * + * @param[in] enable + * @li false - disable serial wire data pin. + * @li true - enable serial wire data pin (default after reset). + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWDIOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWDIOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWDIOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#elif defined(_GPIO_DBGROUTEPEN_SWDIOTMSPEN_MASK) + BUS_RegBitWrite(&(GPIO->DBGROUTEPEN), _GPIO_DBGROUTEPEN_SWDIOTMSPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWDIO pin is not defined." +#endif +} + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) || defined(_GPIO_ROUTEPEN_SWVPEN_MASK) \ + || defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) +/***************************************************************************//** + * @brief + * Enable/Disable serial wire output pin. + * + * @note + * Enabling this pin is not sufficient to fully enable serial wire output, + * which is also dependent on issues outside the GPIO module. Refer to + * DBG_SWOEnable(). + * + * @warning + * If debug port is locked, SWO pin is not disabled automatically. To avoid + * information leakage through SWO, disable SWO pin after locking debug port. + * + * @param[in] enable + * @li false - disable serial wire viewer pin (default after reset). + * @li true - enable serial wire viewer pin. + ******************************************************************************/ +__STATIC_INLINE void GPIO_DbgSWOEnable(bool enable) +{ + unsigned int bit = enable ? 0x1UL : 0x0UL; + +#if defined(_GPIO_ROUTE_SWOPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTE), _GPIO_ROUTE_SWOPEN_SHIFT, bit); +#elif defined(_GPIO_ROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->ROUTEPEN), _GPIO_ROUTEPEN_SWVPEN_SHIFT, bit); +#elif defined(_GPIO_TRACEROUTEPEN_SWVPEN_MASK) + BUS_RegBitWrite(&(GPIO->TRACEROUTEPEN), _GPIO_TRACEROUTEPEN_SWVPEN_SHIFT, bit); +#else +#warning "ROUTE enable for SWO/SWV pin is not defined." +#endif +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode); +#endif + +#if defined(_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, GPIO_DriveStrength_TypeDef strength); +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Disable GPIO pin wake-up from EM4. + * + * @param[in] pinmask + * Bit mask containing the bitwise logic OR of which GPIO pin(s) to disable. + * Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4DisablePinWakeup(uint32_t pinmask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0UL); + + GPIO->EM4WUEN &= ~pinmask; +} +#endif + +# if defined(_GPIO_EM4WUEN_MASK) +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask); +#endif + +#if defined(_GPIO_EM4WUCAUSE_MASK) || defined(_GPIO_IF_EM4WU_MASK) +/**************************************************************************//** + * @brief + * Check which GPIO pin(s) that caused a wake-up from EM4. + * + * @return + * Bit mask containing the bitwise logic OR of which GPIO pin(s) caused the + * wake-up. Refer to Reference Manuals for pinmask to GPIO port/pin mapping. + *****************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EM4GetPinWakeupCause(void) +{ +#if defined(_GPIO_EM4WUCAUSE_MASK) + return GPIO->EM4WUCAUSE & _GPIO_EM4WUCAUSE_MASK; +#else + return GPIO->IF & _GPIO_IF_EM4WU_MASK; +#endif +} +#endif + +#if defined(GPIO_CTRL_EM4RET) || defined(_EMU_EM4CTRL_EM4IORETMODE_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin retention of output enable, output value, pull enable, and + * pull direction in EM4. + * + * @note + * On series 0 devices EM4 gpio retention can either be turned on or off. On + * series 1 devices there are three EM4 GPIO retention modes available. These + * modes are "Disabled", "EM4EXIT" and "SWUNLATCH". Use the EMU_EM4Init() + * to configure the GPIO retention mode on a series 1 device. + * + * The behavior of this function depends on the configured GPIO retention mode. + * If the GPIO retention mode is configured to be "SWUNLATCH" then this + * function will not change anything. If the retention mode is anything else + * then this function will set the GPIO retention mode to "EM4EXIT" when the + * enable argument is true, and "Disabled" when false. + * + * @param[in] enable + * @li true - enable EM4 pin retention. + * @li false - disable EM4 pin retention. + *****************************************************************************/ +__STATIC_INLINE void GPIO_EM4SetPinRetention(bool enable) +{ +#if defined(GPIO_CTRL_EM4RET) + BUS_RegBitWrite(&GPIO->CTRL, _GPIO_CTRL_EM4RET_SHIFT, enable); +#else + + // Leave configuration alone when software unlatch is used. + uint32_t mode = EMU->EM4CTRL & _EMU_EM4CTRL_EM4IORETMODE_MASK; + if (mode == EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH) { + return; + } + + if (enable) { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_EM4EXIT; + } else { + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | EMU_EM4CTRL_EM4IORETMODE_DISABLE; + } +#endif +} +#endif + +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable); + +#if _SILICON_LABS_32B_SERIES > 0 +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable); +#endif +/***************************************************************************//** + * @brief + * Enable/disable input sensing. + * + * @details + * Disabling input sensing if not used, can save some energy consumption. + * + * @param[in] val + * Bitwise logic OR of one or more of: + * @li GPIO_INSENSE_INT - interrupt input sensing. + * @li GPIO_INSENSE_PRS - peripheral reflex system input sensing. + * + * @param[in] mask + * Mask containing bitwise logic OR of bits similar as for @p val used to + * indicate which input sense options to disable/enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_InputSenseSet(uint32_t val, uint32_t mask) +{ +#if defined(_GPIO_INSENSE_MASK) + BUS_RegMaskedWrite(&(GPIO->INSENSE), mask, val); +#else + (void) val; + (void) mask; +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending GPIO interrupts. + * + * @param[in] flags + * Bitwise logic OR of GPIO interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntClear(uint32_t flags) +{ +#if defined(GPIO_HAS_SET_CLEAR) + GPIO->IF_CLR = flags; +#else + GPIO->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more GPIO interrupts. + * + * @param[in] flags + * GPIO interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntDisable(uint32_t flags) +{ + BUS_RegMaskedClear(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Enable one or more GPIO interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * GPIO_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * GPIO interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void GPIO_IntEnable(uint32_t flags) +{ + BUS_RegMaskedSet(&(GPIO->IEN), flags); +} + +/***************************************************************************//** + * @brief + * Get enabled GPIO interrupts. + * + * @return + * Enabled GPIO interrupt sources. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_EnabledIntGet(void) +{ + return GPIO->IEN; +} + +/***************************************************************************//** + * @brief + * Get pending GPIO interrupts. + * + * @return + * GPIO interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGet(void) +{ + return GPIO->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending GPIO interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled GPIO interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in GPIO_IEN register + * and + * - the OR combination of valid interrupt flags in GPIO_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_IntGetEnabled(void) +{ + uint32_t tmp; + + /* Store GPIO->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + tmp = GPIO->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return GPIO->IF & tmp; +} + +/**************************************************************************//** + * @brief + * Set one or more pending GPIO interrupts from SW. + * + * @param[in] flags + * GPIO interrupt sources to set to pending. + *****************************************************************************/ +__STATIC_INLINE void GPIO_IntSet(uint32_t flags) +{ +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->IF_SET = flags; +#else + GPIO->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Lock(void) +{ + GPIO->LOCK = ~GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/***************************************************************************//** + * @brief + * Read the pad value for a single pin in a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to read. + * + * @return + * The pin value, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinInGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DIN, pin); +} + +#if defined (_GPIO_P_PINLOCKN_MASK) +/***************************************************************************//** + * @brief + * Lock all GPIO configuration settings for a given pin. + * The lock can only be cleared by a chip reset. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number to lock. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinLock(GPIO_Port_TypeDef port, unsigned int pin) +{ + BUS_RegBitWrite(&GPIO->P[port].PINLOCKN, pin, 0); +} +#endif + +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin); + +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out); + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out port register to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutClear(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Get current setting for a pin in a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to get setting for. + * + * @return + * The DOUT setting for the requested pin, 0 or 1. + ******************************************************************************/ +__STATIC_INLINE unsigned int GPIO_PinOutGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + return BUS_RegBitRead(&GPIO->P[port].DOUT, pin); +} + +/***************************************************************************//** + * @brief + * Set a single pin in GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to set. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutSet(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = 1UL << pin; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, 1UL << pin); +#endif +} + +/***************************************************************************//** + * @brief + * Toggle a single pin in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PinOutToggle(GPIO_Port_TypeDef port, unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + +#if defined (_GPIO_P_DOUTTGL_MASK) + GPIO->P[port].DOUTTGL = 1UL << pin; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = 1UL << pin; +#else + GPIO->P[port].DOUT ^= 1UL << pin; +#endif +} + +/***************************************************************************//** + * @brief + * Read the pad values for GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The pad values for the GPIO port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortInGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DIN; +} + +/***************************************************************************//** + * @brief + * Set bits in DOUT register for a port to 0. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to clear in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutClear(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTCLR_MASK) + GPIO->P[port].DOUTCLR = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_CLR[port].DOUT = pins; +#else + BUS_RegMaskedClear(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current setting for a GPIO port data out register. + * + * @param[in] port + * The GPIO port to access. + * + * @return + * The data out setting for the requested port. + ******************************************************************************/ +__STATIC_INLINE uint32_t GPIO_PortOutGet(GPIO_Port_TypeDef port) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + return GPIO->P[port].DOUT; +} + +/***************************************************************************//** + * @brief + * Set bits GPIO data out register to 1. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask for bits to set to 1 in DOUT register. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSet(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined(_GPIO_P_DOUTSET_MASK) + GPIO->P[port].DOUTSET = pins; +#elif defined(GPIO_HAS_SET_CLEAR) + GPIO->P_SET[port].DOUT = pins; +#else + BUS_RegMaskedSet(&GPIO->P[port].DOUT, pins); +#endif +} + +/***************************************************************************//** + * @brief + * Set GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the respective output pads, the + * pins must be configured properly. If not, it will take effect + * whenever the pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] val + * Value to write to port data out register. + * + * @param[in] mask + * Mask indicating which bits to modify. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutSetVal(GPIO_Port_TypeDef port, + uint32_t val, + uint32_t mask) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + + GPIO->P[port].DOUT = (GPIO->P[port].DOUT & ~mask) | (val & mask); +} + +/***************************************************************************//** + * @brief + * Toggle pins in GPIO port data out register. + * + * @note + * To ensure that the setting takes effect on the output pad, the pin must + * be configured properly. If not, it will take effect whenever the + * pin has been properly configured. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pins + * Bit mask with pins to toggle. + ******************************************************************************/ +__STATIC_INLINE void GPIO_PortOutToggle(GPIO_Port_TypeDef port, uint32_t pins) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); +#if defined (GPIO_HAS_SET_CLEAR) + GPIO->P_TGL[port].DOUT = pins; +#else + GPIO->P[port].DOUTTGL = pins; +#endif +} + +#if defined(_GPIO_P_CTRL_SLEWRATE_MASK) +/***************************************************************************//** + * @brief + * Set slewrate for pins on a GPIO port. + * + * @param[in] port + * The GPIO port to configure. + * + * @param[in] slewrate + * The slewrate to configure for pins on this GPIO port. + * + * @param[in] slewrateAlt + * The slewrate to configure for pins using alternate modes on this GPIO port. + ******************************************************************************/ +__STATIC_INLINE void GPIO_SlewrateSet(GPIO_Port_TypeDef port, + uint32_t slewrate, + uint32_t slewrateAlt) +{ + EFM_ASSERT(GPIO_PORT_VALID(port)); + EFM_ASSERT(slewrate <= (_GPIO_P_CTRL_SLEWRATE_MASK + >> _GPIO_P_CTRL_SLEWRATE_SHIFT)); + EFM_ASSERT(slewrateAlt <= (_GPIO_P_CTRL_SLEWRATEALT_MASK + >> _GPIO_P_CTRL_SLEWRATEALT_SHIFT)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL + & ~(_GPIO_P_CTRL_SLEWRATE_MASK + | _GPIO_P_CTRL_SLEWRATEALT_MASK)) + | (slewrate << _GPIO_P_CTRL_SLEWRATE_SHIFT) + | (slewrateAlt << _GPIO_P_CTRL_SLEWRATEALT_SHIFT); +} +#endif + +/***************************************************************************//** + * @brief + * Unlock the GPIO configuration. + ******************************************************************************/ +__STATIC_INLINE void GPIO_Unlock(void) +{ + GPIO->LOCK = GPIO_LOCK_LOCKKEY_UNLOCK; +} + +/** @} (end addtogroup gpio) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ +#endif /* EM_GPIO_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h index 74feec9..839b622 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_i2c.h @@ -1,525 +1,525 @@ -/***************************************************************************//** - * @file - * @brief Inter-integrated circuit (I2C) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_I2C_H -#define EM_I2C_H - -#include "em_device.h" -#if defined(I2C_COUNT) && (I2C_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup i2c - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** - * @brief - * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, - * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use - * worst case value of Tlow or Thigh as base. - * - * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz - * @note - * Due to chip characteristics, max value is somewhat reduced. - */ -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GECKO_FAMILY) \ - || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) \ - || defined(_EFM32_HAPPY_FAMILY)) -#define I2C_FREQ_STANDARD_MAX 93000 -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EFM32_WONDER_FAMILY)) -#define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_SERIES_1) -// None of the chips on this platform has been characterized on this parameter. -// Use same value as on Wonder until further notice. -#define I2C_FREQ_STANDARD_MAX 92000 -#elif defined(_SILICON_LABS_32B_SERIES_2) -#define I2C_FREQ_STANDARD_MAX 100000 -#else -#error "Unknown device family." -#endif - -/** - * @brief - * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, - * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use - * worst case value of Tlow or 2xThigh as base. - * - * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz - */ -#define I2C_FREQ_FAST_MAX 392157 - -/** - * @brief - * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. - * @details - * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, - * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use - * worst case value of Tlow or (11/6)xThigh as base. - * - * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz - */ -#define I2C_FREQ_FASTPLUS_MAX 987167 - -/** - * @brief - * Indicate plain write sequence: S+ADDR(W)+DATA0+P. - * @details - * @li S - Start - * @li ADDR(W) - address with W/R bit cleared - * @li DATA0 - Data taken from buffer with index 0 - * @li P - Stop - */ -#define I2C_FLAG_WRITE 0x0001 - -/** - * @brief - * Indicate plain read sequence: S+ADDR(R)+DATA0+P. - * @details - * @li S - Start - * @li ADDR(R) - Address with W/R bit set - * @li DATA0 - Data read into buffer with index 0 - * @li P - Stop - */ -#define I2C_FLAG_READ 0x0002 - -/** - * @brief - * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. - * @details - * @li S - Start - * @li Sr - Repeated start - * @li ADDR(W) - Address with W/R bit cleared - * @li ADDR(R) - Address with W/R bit set - * @li DATAn - Data written from/read into buffer with index n - * @li P - Stop - */ -#define I2C_FLAG_WRITE_READ 0x0004 - -/** - * @brief - * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. - * @details - * @li S - Start - * @li ADDR(W) - Address with W/R bit cleared - * @li DATAn - Data written from buffer with index n - * @li P - Stop - */ -#define I2C_FLAG_WRITE_WRITE 0x0008 - -/** Use 10 bit address. */ -#define I2C_FLAG_10BIT_ADDR 0x0010 - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Clock low to high ratio settings. */ -typedef enum { - i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ - i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ - i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ -} I2C_ClockHLR_TypeDef; - -/** Return codes for single Controller mode transfer function. */ -typedef enum { - /* In progress code (>0) */ - i2cTransferInProgress = 1, /**< Transfer in progress. */ - - /* Complete code (=0) */ - i2cTransferDone = 0, /**< Transfer completed successfully. */ - - /* Transfer error codes (<0). */ - i2cTransferNack = -1, /**< NACK received during transfer. */ - i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ - i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ - i2cTransferUsageFault = -4, /**< Usage fault. */ - i2cTransferSwFault = -5 /**< SW fault. */ -} I2C_TransferReturn_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** I2C initialization structure. */ -typedef struct { - /** Enable I2C peripheral when initialization completed. */ - bool enable; - - /** Set to Controller (true) or Target (false) mode */ - bool master; - - /** - * I2C reference clock assumed when configuring bus frequency setup. - * Set it to 0 if currently configured reference clock will be used - * This parameter is only applicable if operating in Controller mode. - */ - uint32_t refFreq; - - /** - * (Max) I2C bus frequency to use. This parameter is only applicable - * if operating in Controller mode. - */ - uint32_t freq; - - /** Clock low/high ratio control. */ - I2C_ClockHLR_TypeDef clhr; -} I2C_Init_TypeDef; - -/** Suggested default configuration for I2C initialization structure. */ -#define I2C_INIT_DEFAULT \ - { \ - true, /* Enable when initialization done. */ \ - true, /* Set to Controller mode. */ \ - 0, /* Use currently configured reference clock. */ \ - I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ - /* within I2C specification. */ \ - i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ - } - -/** - * @brief - * Master mode transfer message structure used to define a complete - * I2C transfer sequence (from start to stop). - * @details - * The structure allows for defining the following types of sequences - * (refer to defines for sequence details): - * @li #I2C_FLAG_READ - Data read into buf[0].data - * @li #I2C_FLAG_WRITE - Data written from buf[0].data - * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read - * into buf[1].data - * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and - * buf[1].data - */ -typedef struct { - /** - * @brief - * Address to use after (repeated) start. - * @details - * Layout details, A = Address bit, X = don't care bit (set to 0): - * @li 7 bit address - Use format AAAA AAAX - * @li 10 bit address - Use format XXXX XAAX AAAA AAAA - */ - uint16_t addr; - - /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ - uint16_t flags; - - /** - * Buffers used to hold data to send from or receive into, depending - * on sequence type. - */ - struct { - /** Buffer used for data to transmit/receive, must be @p len long. */ - uint8_t *data; - - /** - * Number of bytes in @p data to send or receive. Notice that when - * receiving data to this buffer, at least 1 byte must be received. - * Setting @p len to 0 in the receive case is considered a usage fault. - * Transmitting 0 bytes is legal, in which case only the address - * is transmitted after the start condition. - */ - uint16_t len; - } buf[2]; -} I2C_TransferSeq_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); -void I2C_BusFreqSet(I2C_TypeDef *i2c, - uint32_t freqRef, - uint32_t freqScl, - I2C_ClockHLR_TypeDef i2cMode); -void I2C_Enable(I2C_TypeDef *i2c, bool enable); -void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending I2C interrupts. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IF_CLR = flags; -#else - i2c->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more I2C interrupts. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IEN_CLR = flags; -#else - i2c->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more I2C interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * I2C_IntClear() prior to enabling the interrupt. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IEN_SET = flags; -#else - i2c->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending I2C interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) -{ - return i2c->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending I2C interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * Pending and enabled I2C interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in I2Cn_IEN and - * - the pending interrupt flags I2Cn_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) -{ - uint32_t ien; - - ien = i2c->IEN; - return i2c->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending I2C interrupts from SW. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] flags - * I2C interrupt sources to set to pending. Use a bitwise logic OR combination - * of valid interrupt flags for the I2C module (I2C_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) -{ -#if defined (I2C_HAS_SET_CLEAR) - i2c->IF_SET = flags; -#else - i2c->IFS = flags; -#endif -} - -void I2C_Reset(I2C_TypeDef *i2c); - -/***************************************************************************//** - * @brief - * Get Target address used for I2C peripheral (when operating in Target mode). - * - * @details - * For 10-bit addressing mode, the address is split in two bytes, and only - * the first byte setting is fetched, effectively only controlling the 2 most - * significant bits of the 10-bit address. Full handling of 10-bit addressing - * in Target mode requires additional SW handling. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C Target address in use. The 7 most significant bits define the actual - * address, the least significant bit is reserved and always returned as 0. - ******************************************************************************/ -__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) -{ - return ((uint8_t)(i2c->SADDR)); -} - -/***************************************************************************//** - * @brief - * Set Target address to use for I2C peripheral (when operating in Target mode). - * - * @details - * For 10- bit addressing mode, the address is split in two bytes, and only - * the first byte is set, effectively only controlling the 2 most significant - * bits of the 10-bit address. Full handling of 10-bit addressing in Target - * mode requires additional SW handling. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] addr - * I2C Target address to use. The 7 most significant bits define the actual - * address, the least significant bit is reserved and always set to 0. - ******************************************************************************/ -__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) -{ - i2c->SADDR = (uint32_t)addr & 0xfe; -} - -/***************************************************************************//** - * @brief - * Get Target address mask used for I2C peripheral (when operating in Target - * mode). - * - * @details - * The address mask defines how the comparator works. A bit position with - * value 0 means that the corresponding Target address bit is ignored during - * comparison (don't care). A bit position with value 1 means that the - * corresponding Target address bit must match. - * - * For 10-bit addressing mode, the address is split in two bytes, and only - * the mask for the first address byte is fetched, effectively only - * controlling the 2 most significant bits of the 10-bit address. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @return - * I2C Target address mask in use. The 7 most significant bits define the - * actual address mask, the least significant bit is reserved and always - * returned as 0. - ******************************************************************************/ -__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) -{ - return ((uint8_t)(i2c->SADDRMASK)); -} - -/***************************************************************************//** - * @brief - * Set Target address mask used for I2C peripheral (when operating in Target - * mode). - * - * @details - * The address mask defines how the comparator works. A bit position with - * value 0 means that the corresponding Target address bit is ignored during - * comparison (don't care). A bit position with value 1 means that the - * corresponding Target address bit must match. - * - * For 10-bit addressing mode, the address is split in two bytes, and only - * the mask for the first address byte is set, effectively only controlling - * the 2 most significant bits of the 10-bit address. - * - * @param[in] i2c - * Pointer to I2C peripheral register block. - * - * @param[in] mask - * I2C Target address mask to use. The 7 most significant bits define the - * actual address mask, the least significant bit is reserved and should - * be 0. - ******************************************************************************/ -__STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) -{ - i2c->SADDRMASK = (uint32_t)mask & 0xfe; -} - -I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); -I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, - I2C_TransferSeq_TypeDef *seq); - -/** @} (end addtogroup i2c) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ -#endif /* EM_I2C_H */ +/***************************************************************************//** + * @file + * @brief Inter-integrated circuit (I2C) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_I2C_H +#define EM_I2C_H + +#include "em_device.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup i2c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * Standard mode max frequency assuming using 4:4 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 4.7us, min Thigh = 4.0us, + * max Trise=1.0us, max Tfall=0.3us. Since ratio is 4:4, have to use + * worst case value of Tlow or Thigh as base. + * + * 1/(Tlow + Thigh + 1us + 0.3us) = 1/(4.7 + 4.7 + 1.3)us = 93458Hz + * @note + * Due to chip characteristics, max value is somewhat reduced. + */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GECKO_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) \ + || defined(_EFM32_HAPPY_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 93000 +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY)) +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_1) +// None of the chips on this platform has been characterized on this parameter. +// Use same value as on Wonder until further notice. +#define I2C_FREQ_STANDARD_MAX 92000 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_FREQ_STANDARD_MAX 100000 +#else +#error "Unknown device family." +#endif + +/** + * @brief + * Fast mode max frequency assuming using 6:3 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 1.3us, min Thigh = 0.6us, + * max Trise=0.3us, max Tfall=0.3us. Since ratio is 6:3, have to use + * worst case value of Tlow or 2xThigh as base. + * + * 1/(Tlow + Thigh + 0.3us + 0.3us) = 1/(1.3 + 0.65 + 0.6)us = 392157Hz + */ +#define I2C_FREQ_FAST_MAX 392157 + +/** + * @brief + * Fast mode+ max frequency assuming using 11:6 ratio for Nlow:Nhigh. + * @details + * From I2C specification: Min Tlow = 0.5us, min Thigh = 0.26us, + * max Trise=0.12us, max Tfall=0.12us. Since ratio is 11:6, have to use + * worst case value of Tlow or (11/6)xThigh as base. + * + * 1/(Tlow + Thigh + 0.12us + 0.12us) = 1/(0.5 + 0.273 + 0.24)us = 987167Hz + */ +#define I2C_FREQ_FASTPLUS_MAX 987167 + +/** + * @brief + * Indicate plain write sequence: S+ADDR(W)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(W) - address with W/R bit cleared + * @li DATA0 - Data taken from buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_WRITE 0x0001 + +/** + * @brief + * Indicate plain read sequence: S+ADDR(R)+DATA0+P. + * @details + * @li S - Start + * @li ADDR(R) - Address with W/R bit set + * @li DATA0 - Data read into buffer with index 0 + * @li P - Stop + */ +#define I2C_FLAG_READ 0x0002 + +/** + * @brief + * Indicate combined write/read sequence: S+ADDR(W)+DATA0+Sr+ADDR(R)+DATA1+P. + * @details + * @li S - Start + * @li Sr - Repeated start + * @li ADDR(W) - Address with W/R bit cleared + * @li ADDR(R) - Address with W/R bit set + * @li DATAn - Data written from/read into buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_READ 0x0004 + +/** + * @brief + * Indicate write sequence using two buffers: S+ADDR(W)+DATA0+DATA1+P. + * @details + * @li S - Start + * @li ADDR(W) - Address with W/R bit cleared + * @li DATAn - Data written from buffer with index n + * @li P - Stop + */ +#define I2C_FLAG_WRITE_WRITE 0x0008 + +/** Use 10 bit address. */ +#define I2C_FLAG_10BIT_ADDR 0x0010 + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Clock low to high ratio settings. */ +typedef enum { + i2cClockHLRStandard = _I2C_CTRL_CLHR_STANDARD, /**< Ratio is 4:4 */ + i2cClockHLRAsymetric = _I2C_CTRL_CLHR_ASYMMETRIC, /**< Ratio is 6:3 */ + i2cClockHLRFast = _I2C_CTRL_CLHR_FAST /**< Ratio is 11:3 */ +} I2C_ClockHLR_TypeDef; + +/** Return codes for single Controller mode transfer function. */ +typedef enum { + /* In progress code (>0) */ + i2cTransferInProgress = 1, /**< Transfer in progress. */ + + /* Complete code (=0) */ + i2cTransferDone = 0, /**< Transfer completed successfully. */ + + /* Transfer error codes (<0). */ + i2cTransferNack = -1, /**< NACK received during transfer. */ + i2cTransferBusErr = -2, /**< Bus error during transfer (misplaced START/STOP). */ + i2cTransferArbLost = -3, /**< Arbitration lost during transfer. */ + i2cTransferUsageFault = -4, /**< Usage fault. */ + i2cTransferSwFault = -5 /**< SW fault. */ +} I2C_TransferReturn_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** I2C initialization structure. */ +typedef struct { + /** Enable I2C peripheral when initialization completed. */ + bool enable; + + /** Set to Controller (true) or Target (false) mode */ + bool master; + + /** + * I2C reference clock assumed when configuring bus frequency setup. + * Set it to 0 if currently configured reference clock will be used + * This parameter is only applicable if operating in Controller mode. + */ + uint32_t refFreq; + + /** + * (Max) I2C bus frequency to use. This parameter is only applicable + * if operating in Controller mode. + */ + uint32_t freq; + + /** Clock low/high ratio control. */ + I2C_ClockHLR_TypeDef clhr; +} I2C_Init_TypeDef; + +/** Suggested default configuration for I2C initialization structure. */ +#define I2C_INIT_DEFAULT \ + { \ + true, /* Enable when initialization done. */ \ + true, /* Set to Controller mode. */ \ + 0, /* Use currently configured reference clock. */ \ + I2C_FREQ_STANDARD_MAX, /* Set to standard rate assuring being */ \ + /* within I2C specification. */ \ + i2cClockHLRStandard /* Set to use 4:4 low/high duty cycle. */ \ + } + +/** + * @brief + * Master mode transfer message structure used to define a complete + * I2C transfer sequence (from start to stop). + * @details + * The structure allows for defining the following types of sequences + * (refer to defines for sequence details): + * @li #I2C_FLAG_READ - Data read into buf[0].data + * @li #I2C_FLAG_WRITE - Data written from buf[0].data + * @li #I2C_FLAG_WRITE_READ - Data written from buf[0].data and read + * into buf[1].data + * @li #I2C_FLAG_WRITE_WRITE - Data written from buf[0].data and + * buf[1].data + */ +typedef struct { + /** + * @brief + * Address to use after (repeated) start. + * @details + * Layout details, A = Address bit, X = don't care bit (set to 0): + * @li 7 bit address - Use format AAAA AAAX + * @li 10 bit address - Use format XXXX XAAX AAAA AAAA + */ + uint16_t addr; + + /** Flags defining sequence type and details, see I2C_FLAG_ defines. */ + uint16_t flags; + + /** + * Buffers used to hold data to send from or receive into, depending + * on sequence type. + */ + struct { + /** Buffer used for data to transmit/receive, must be @p len long. */ + uint8_t *data; + + /** + * Number of bytes in @p data to send or receive. Notice that when + * receiving data to this buffer, at least 1 byte must be received. + * Setting @p len to 0 in the receive case is considered a usage fault. + * Transmitting 0 bytes is legal, in which case only the address + * is transmitted after the start condition. + */ + uint16_t len; + } buf[2]; +} I2C_TransferSeq_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c); +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode); +void I2C_Enable(I2C_TypeDef *i2c, bool enable); +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * Pending I2C interrupt source to clear. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntClear(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_CLR = flags; +#else + i2c->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more I2C interrupts. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntDisable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_CLR = flags; +#else + i2c->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more I2C interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * I2C_IntClear() prior to enabling the interrupt. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntEnable(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IEN_SET = flags; +#else + i2c->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending I2C interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGet(I2C_TypeDef *i2c) +{ + return i2c->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending I2C interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * Pending and enabled I2C interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in I2Cn_IEN and + * - the pending interrupt flags I2Cn_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t I2C_IntGetEnabled(I2C_TypeDef *i2c) +{ + uint32_t ien; + + ien = i2c->IEN; + return i2c->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending I2C interrupts from SW. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] flags + * I2C interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the I2C module (I2C_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void I2C_IntSet(I2C_TypeDef *i2c, uint32_t flags) +{ +#if defined (I2C_HAS_SET_CLEAR) + i2c->IF_SET = flags; +#else + i2c->IFS = flags; +#endif +} + +void I2C_Reset(I2C_TypeDef *i2c); + +/***************************************************************************//** + * @brief + * Get Target address used for I2C peripheral (when operating in Target mode). + * + * @details + * For 10-bit addressing mode, the address is split in two bytes, and only + * the first byte setting is fetched, effectively only controlling the 2 most + * significant bits of the 10-bit address. Full handling of 10-bit addressing + * in Target mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address in use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDR)); +} + +/***************************************************************************//** + * @brief + * Set Target address to use for I2C peripheral (when operating in Target mode). + * + * @details + * For 10- bit addressing mode, the address is split in two bytes, and only + * the first byte is set, effectively only controlling the 2 most significant + * bits of the 10-bit address. Full handling of 10-bit addressing in Target + * mode requires additional SW handling. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] addr + * I2C Target address to use. The 7 most significant bits define the actual + * address, the least significant bit is reserved and always set to 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressSet(I2C_TypeDef *i2c, uint8_t addr) +{ + i2c->SADDR = (uint32_t)addr & 0xfe; +} + +/***************************************************************************//** + * @brief + * Get Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is fetched, effectively only + * controlling the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @return + * I2C Target address mask in use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and always + * returned as 0. + ******************************************************************************/ +__STATIC_INLINE uint8_t I2C_SlaveAddressMaskGet(I2C_TypeDef *i2c) +{ + return ((uint8_t)(i2c->SADDRMASK)); +} + +/***************************************************************************//** + * @brief + * Set Target address mask used for I2C peripheral (when operating in Target + * mode). + * + * @details + * The address mask defines how the comparator works. A bit position with + * value 0 means that the corresponding Target address bit is ignored during + * comparison (don't care). A bit position with value 1 means that the + * corresponding Target address bit must match. + * + * For 10-bit addressing mode, the address is split in two bytes, and only + * the mask for the first address byte is set, effectively only controlling + * the 2 most significant bits of the 10-bit address. + * + * @param[in] i2c + * Pointer to I2C peripheral register block. + * + * @param[in] mask + * I2C Target address mask to use. The 7 most significant bits define the + * actual address mask, the least significant bit is reserved and should + * be 0. + ******************************************************************************/ +__STATIC_INLINE void I2C_SlaveAddressMaskSet(I2C_TypeDef *i2c, uint8_t mask) +{ + i2c->SADDRMASK = (uint32_t)mask & 0xfe; +} + +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c); +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq); + +/** @} (end addtogroup i2c) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ +#endif /* EM_I2C_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h index 340474b..43b0eea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_iadc.h @@ -1,1399 +1,1399 @@ -/***************************************************************************//** - * @file - * @brief Incremental Analog to Digital Converter (IADC) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_IADC_H -#define EM_IADC_H - -#include "em_device.h" -#include "em_gpio.h" -#include "em_system.h" -#if defined(IADC_COUNT) && (IADC_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup iadc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Warm-up mode. */ -typedef enum { - /** IADC shutdown after each conversion. */ - iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL, - - /** ADC is kept in standby mode between conversion. */ - iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY, - - /** ADC and reference selected for scan mode kept warmup, allowing - continuous conversion. */ - iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM -} IADC_Warmup_t; - -/** IADC result alignment. */ -typedef enum { - /** IADC results 12-bit right aligned */ - iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12, - - /** IADC results 12-bit left aligned */ - iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12, - -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - /** IADC results 16-bit right aligned */ - iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16, - - /** IADC results 16-bit left aligned */ - iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16, -#endif - -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - /** IADC results 20-bit right aligned */ - iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20, - - /** IADC results 20-bit left aligned */ - iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20, -#endif -} IADC_Alignment_t; - -/** IADC negative input selection. */ -typedef enum { - /** Ground */ - iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)) - | 1, - /** Ground using even mux */ - iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), - -#if defined(_IADC_SCAN_PORTNEG_DAC1) - /** Direct connection to DAC_1 input pin */ - iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADANA1) - /** Direct connection to Pad_ana_1 input pin */ - iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADANA3) - /** Direct connection to Pad_ana_3 input pin */ - iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTNEG_PADREFNEG) - /** Negative reference pin 0 */ - iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), -#endif - /** GPIO port A pin 0 */ - iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), - - /** GPIO port A pin 1 */ - iadcNegInputPortAPin1, - - /** GPIO port A pin 2 */ - iadcNegInputPortAPin2, - - /** GPIO port A pin 3 */ - iadcNegInputPortAPin3, - - /** GPIO port A pin 4 */ - iadcNegInputPortAPin4, - - /** GPIO port A pin 5 */ - iadcNegInputPortAPin5, - - /** GPIO port A pin 6 */ - iadcNegInputPortAPin6, - - /** GPIO port A pin 7 */ - iadcNegInputPortAPin7, - - /** GPIO port A pin 8 */ - iadcNegInputPortAPin8, - - /** GPIO port A pin 9 */ - iadcNegInputPortAPin9, - - /** GPIO port A pin 10 */ - iadcNegInputPortAPin10, - - /** GPIO port A pin 11 */ - iadcNegInputPortAPin11, - - /** GPIO port A pin 12 */ - iadcNegInputPortAPin12, - - /** GPIO port A pin 13 */ - iadcNegInputPortAPin13, - - /** GPIO port A pin 14 */ - iadcNegInputPortAPin14, - - /** GPIO port A pin 15 */ - iadcNegInputPortAPin15, - - /** GPIO port B pin 0 */ - iadcNegInputPortBPin0, - - /** GPIO port B pin 1 */ - iadcNegInputPortBPin1, - - /** GPIO port B pin 2 */ - iadcNegInputPortBPin2, - - /** GPIO port B pin 3 */ - iadcNegInputPortBPin3, - - /** GPIO port B pin 4 */ - iadcNegInputPortBPin4, - - /** GPIO port B pin 5 */ - iadcNegInputPortBPin5, - - /** GPIO port B pin 6 */ - iadcNegInputPortBPin6, - - /** GPIO port B pin 7 */ - iadcNegInputPortBPin7, - - /** GPIO port B pin 8 */ - iadcNegInputPortBPin8, - - /** GPIO port B pin 9 */ - iadcNegInputPortBPin9, - - /** GPIO port B pin 10 */ - iadcNegInputPortBPin10, - - /** GPIO port B pin 11 */ - iadcNegInputPortBPin11, - - /** GPIO port B pin 12 */ - iadcNegInputPortBPin12, - - /** GPIO port B pin 13 */ - iadcNegInputPortBPin13, - - /** GPIO port B pin 14 */ - iadcNegInputPortBPin14, - - /** GPIO port B pin 15 */ - iadcNegInputPortBPin15, - - /** GPIO port C pin 0 */ - iadcNegInputPortCPin0, - - /** GPIO port C pin 1 */ - iadcNegInputPortCPin1, - - /** GPIO port C pin 2 */ - iadcNegInputPortCPin2, - - /** GPIO port C pin 3 */ - iadcNegInputPortCPin3, - - /** GPIO port C pin 4 */ - iadcNegInputPortCPin4, - - /** GPIO port C pin 5 */ - iadcNegInputPortCPin5, - - /** GPIO port C pin 6 */ - iadcNegInputPortCPin6, - - /** GPIO port C pin 7 */ - iadcNegInputPortCPin7, - - /** GPIO port C pin 8 */ - iadcNegInputPortCPin8, - - /** GPIO port C pin 9 */ - iadcNegInputPortCPin9, - - /** GPIO port C pin 10 */ - iadcNegInputPortCPin10, - - /** GPIO port C pin 11 */ - iadcNegInputPortCPin11, - - /** GPIO port C pin 12 */ - iadcNegInputPortCPin12, - - /** GPIO port C pin 13 */ - iadcNegInputPortCPin13, - - /** GPIO port C pin 14 */ - iadcNegInputPortCPin14, - - /** GPIO port C pin 15 */ - iadcNegInputPortCPin15, - - /** GPIO port D pin 0 */ - iadcNegInputPortDPin0, - - /** GPIO port D pin 1 */ - iadcNegInputPortDPin1, - - /** GPIO port D pin 2 */ - iadcNegInputPortDPin2, - - /** GPIO port D pin 3 */ - iadcNegInputPortDPin3, - - /** GPIO port D pin 4 */ - iadcNegInputPortDPin4, - - /** GPIO port D pin 5 */ - iadcNegInputPortDPin5, - - /** GPIO port D pin 6 */ - iadcNegInputPortDPin6, - - /** GPIO port D pin 7 */ - iadcNegInputPortDPin7, - - /** GPIO port D pin 8 */ - iadcNegInputPortDPin8, - - /** GPIO port D pin 9 */ - iadcNegInputPortDPin9, - - /** GPIO port D pin 10 */ - iadcNegInputPortDPin10, - - /** GPIO port D pin 11 */ - iadcNegInputPortDPin11, - - /** GPIO port D pin 12 */ - iadcNegInputPortDPin12, - - /** GPIO port D pin 13 */ - iadcNegInputPortDPin13, - - /** GPIO port D pin 14 */ - iadcNegInputPortDPin14, - - /** GPIO port D pin 15 */ - iadcNegInputPortDPin15 -} IADC_NegInput_t; - -/** IADC positive port selection. */ -typedef enum { - /** Ground */ - iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), - - /** Avdd / 4 */ - iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 0, - - /** Vddio / 4 */ - iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 1, - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - /** Vddio1 / 4 */ - iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 2, - - /** Vddio2 / 4 */ - iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 3, -#else - /** Vss */ - iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 2, - - /** Vss */ - iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 3, -#endif - - /** Dvdd / 4 */ - iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 4, - - /** Decouple */ - iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) - | 7, - -#if defined(_IADC_SCAN_PORTPOS_DAC0) - /** Direct connection to DAC_0 input pin */ - iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADANA0) - /** Direct connection to Pad_ana_0 input pin */ - iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADANA2) - /** Direct connection to Pad_ana_2 input pin */ - iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif -#if defined(_IADC_SCAN_PORTPOS_PADREFPOS) - /** Positive reference pin 0 */ - iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), -#endif - - /** GPIO port A pin 0 */ - iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), - - /** GPIO port A pin 1 */ - iadcPosInputPortAPin1, - - /** GPIO port A pin 2 */ - iadcPosInputPortAPin2, - - /** GPIO port A pin 3 */ - iadcPosInputPortAPin3, - - /** GPIO port A pin 4 */ - iadcPosInputPortAPin4, - - /** GPIO port A pin 5 */ - iadcPosInputPortAPin5, - - /** GPIO port A pin 6 */ - iadcPosInputPortAPin6, - - /** GPIO port A pin 7 */ - iadcPosInputPortAPin7, - - /** GPIO port A pin 8 */ - iadcPosInputPortAPin8, - - /** GPIO port A pin 9 */ - iadcPosInputPortAPin9, - - /** GPIO port A pin 10 */ - iadcPosInputPortAPin10, - - /** GPIO port A pin 11 */ - iadcPosInputPortAPin11, - - /** GPIO port A pin 12 */ - iadcPosInputPortAPin12, - - /** GPIO port A pin 13 */ - iadcPosInputPortAPin13, - - /** GPIO port A pin 14 */ - iadcPosInputPortAPin14, - - /** GPIO port A pin 15 */ - iadcPosInputPortAPin15, - - /** GPIO port B pin 0 */ - iadcPosInputPortBPin0, - - /** GPIO port B pin 1 */ - iadcPosInputPortBPin1, - - /** GPIO port B pin 2 */ - iadcPosInputPortBPin2, - - /** GPIO port B pin 3 */ - iadcPosInputPortBPin3, - - /** GPIO port B pin 4 */ - iadcPosInputPortBPin4, - - /** GPIO port B pin 5 */ - iadcPosInputPortBPin5, - - /** GPIO port B pin 6 */ - iadcPosInputPortBPin6, - - /** GPIO port B pin 7 */ - iadcPosInputPortBPin7, - - /** GPIO port B pin 8 */ - iadcPosInputPortBPin8, - - /** GPIO port B pin 9 */ - iadcPosInputPortBPin9, - - /** GPIO port B pin 10 */ - iadcPosInputPortBPin10, - - /** GPIO port B pin 11 */ - iadcPosInputPortBPin11, - - /** GPIO port B pin 12 */ - iadcPosInputPortBPin12, - - /** GPIO port B pin 13 */ - iadcPosInputPortBPin13, - - /** GPIO port B pin 14 */ - iadcPosInputPortBPin14, - - /** GPIO port B pin 15 */ - iadcPosInputPortBPin15, - - /** GPIO port C pin 0 */ - iadcPosInputPortCPin0, - - /** GPIO port C pin 1 */ - iadcPosInputPortCPin1, - - /** GPIO port C pin 2 */ - iadcPosInputPortCPin2, - - /** GPIO port C pin 3 */ - iadcPosInputPortCPin3, - - /** GPIO port C pin 4 */ - iadcPosInputPortCPin4, - - /** GPIO port C pin 5 */ - iadcPosInputPortCPin5, - - /** GPIO port C pin 6 */ - iadcPosInputPortCPin6, - - /** GPIO port C pin 7 */ - iadcPosInputPortCPin7, - - /** GPIO port C pin 8 */ - iadcPosInputPortCPin8, - - /** GPIO port C pin 9 */ - iadcPosInputPortCPin9, - - /** GPIO port C pin 10 */ - iadcPosInputPortCPin10, - - /** GPIO port C pin 11 */ - iadcPosInputPortCPin11, - - /** GPIO port C pin 12 */ - iadcPosInputPortCPin12, - - /** GPIO port C pin 13 */ - iadcPosInputPortCPin13, - - /** GPIO port C pin 14 */ - iadcPosInputPortCPin14, - - /** GPIO port C pin 15 */ - iadcPosInputPortCPin15, - - /** GPIO port D pin 0 */ - iadcPosInputPortDPin0, - - /** GPIO port D pin 1 */ - iadcPosInputPortDPin1, - - /** GPIO port D pin 2 */ - iadcPosInputPortDPin2, - - /** GPIO port D pin 3 */ - iadcPosInputPortDPin3, - - /** GPIO port D pin 4 */ - iadcPosInputPortDPin4, - - /** GPIO port D pin 5 */ - iadcPosInputPortDPin5, - - /** GPIO port D pin 6 */ - iadcPosInputPortDPin6, - - /** GPIO port D pin 7 */ - iadcPosInputPortDPin7, - - /** GPIO port D pin 8 */ - iadcPosInputPortDPin8, - - /** GPIO port D pin 9 */ - iadcPosInputPortDPin9, - - /** GPIO port D pin 10 */ - iadcPosInputPortDPin10, - - /** GPIO port D pin 11 */ - iadcPosInputPortDPin11, - - /** GPIO port D pin 12 */ - iadcPosInputPortDPin12, - - /** GPIO port D pin 13 */ - iadcPosInputPortDPin13, - - /** GPIO port D pin 14 */ - iadcPosInputPortDPin14, - - /** GPIO port D pin 15 */ - iadcPosInputPortDPin15 -} IADC_PosInput_t; - -/** IADC Commands. */ -typedef enum { - /** Start single queue */ - iadcCmdStartSingle = IADC_CMD_SINGLESTART, - - /** Stop single queue */ - iadcCmdStopSingle = IADC_CMD_SINGLESTOP, - - /** Start scan queue */ - iadcCmdStartScan = IADC_CMD_SCANSTART, - - /** Stop scan queue */ - iadcCmdStopScan = IADC_CMD_SCANSTOP, - - /** Enable Timer */ - iadcCmdEnableTimer = IADC_CMD_TIMEREN, - - /** Disable Timer */ - iadcCmdDisableTimer = IADC_CMD_TIMERDIS -} IADC_Cmd_t; - -/** IADC Configuration. */ -typedef enum { - /** Normal mode */ - iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL, -#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) - /** High Speed mode */ - iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED, -#endif -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - /** High Accuracy mode */ - iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY -#endif -} IADC_CfgAdcMode_t; - -/** IADC Over sampling rate for high speed. */ -typedef enum { - /** High speed oversampling of 2x */ - iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2, - - /** High speed oversampling of 4x */ - iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4, - - /** High speed oversampling of 8x */ - iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8, - - /** High speed oversampling of 16x */ - iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16, - - /** High speed oversampling of 32x */ - iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32, - - /** High speed oversampling of 64x */ - iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64 -} IADC_CfgOsrHighSpeed_t; - -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** IADC Over sampling rate for high accuracy. */ -typedef enum { - /** High accuracy oversampling of 16x */ - iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16, - - /** High accuracy oversampling of 32x */ - iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32, - - /** High accuracy oversampling of 64x */ - iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64, - - /** High accuracy oversampling of 92x */ - iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92, - - /** High accuracy oversampling of 128x */ - iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128, - - /** High accuracy oversampling of 256x */ - iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256 -} IADC_CfgOsrHighAccuracy_t; -#endif - -/** IADC Analog Gain. */ -typedef enum { -#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) - /** Analog gain of 0.25x */ - iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25, -#endif - /** Analog gain of 0.5x */ - iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5, - - /** Analog gain of 1x */ - iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1, - - /** Analog gain of 2x */ - iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2, - - /** Analog gain of 3x */ - iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3, - - /** Analog gain of 4x */ - iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4 -} IADC_CfgAnalogGain_t; - -/** IADC Reference */ -typedef enum { - /** Internal 1.2V Band Gap Reference (buffered) to ground */ - iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, - - /** External reference (unbuffered) VREFP to VREFN. - * VEVREF up to AVDD. When inputs are routed to external GPIO pins, - * the maximum pin voltage is limited to the lower - * of the IOVDD and AVDD supplies. - * The internal calibration values correspond to a 1.25V reference, - * use of other voltages may require recalibration. - * See AN1189: Incremental Analog to Digital Converter (IADC) */ - iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, - -#if defined(_IADC_CFG_REFSEL_VREF2P5) - /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ - iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, -#endif - - /** VDDX (unbuffered) to ground. */ - iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX, - - /** 0.8 * VDDX (buffered) to ground. */ - iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF, - -#if defined(_IADC_CFG_REFSEL_VREFBUF) - /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */ - iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF, -#endif - -#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) - /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */ - iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF, -#endif -} IADC_CfgReference_t; - -/** IADC Two's complement results */ -typedef enum { - /** Automatic. Single ended => Unipolar, Differential => Bipolar */ - iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO, - - /** All results in unipolar format. Negative diff input gives 0 as result. */ - iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR, - - /** All results in bipolar (2's complement) format. Half range for SE. */ - iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR -} IADC_CfgTwosComp_t; - -/** IADC trigger action */ -typedef enum { - /** Start single/scan queue immediately */ - iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE, - - /** Timer starts single/scan queue */ - iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER, - - /** PRS0 from timer in same clock group starts single/scan queue */ - iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP, - - /** PRS0 positive edge starts single/scan queue */ - iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS, - - /** PRS0 negative edge starts single/scan queue */ - iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG, - -#if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE) - /** LESENSE starts scan queue */ - iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE -#endif -} IADC_TriggerSel_t; - -/** IADC trigger action */ -typedef enum { - /** Convert single/scan queue once per trigger */ - iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE, - - /** Convert single/scan queue continuously */ - iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS, -} IADC_TriggerAction_t; - -/** IADC data valid level before requesting DMA transfer */ -typedef enum { - /** Data valid level is 1 before requesting DMA transfer */ - iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1, - - /** Data valid level is 2 before requesting DMA transfer */ - iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2, - - /** Data valid level is 3 before requesting DMA transfer */ - iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3, - - /** Data valid level is 4 before requesting DMA transfer */ - iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4, - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 2 - /** Data valid level is 5 before requesting DMA transfer */ - iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5, - - /** Data valid level is 6 before requesting DMA transfer */ - iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6, - - /** Data valid level is 7 before requesting DMA transfer */ - iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7, -#endif - -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 3 - /** Data valid level is 8 before requesting DMA transfer */ - iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8 -#endif -#endif -} IADC_FifoCfgDvl_t; - -#if defined(_IADC_CFG_DIGAVG_MASK) -/** IADC digital averaging function. */ -typedef enum { - /** Average over 1 sample (no averaging). */ - iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1, - - /** Average over 2 samples. */ - iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2, - - /** Average over 4 samples. */ - iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4, - - /** Average over 8 samples. */ - iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8, - - /** Average over 16 samples. */ - iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16 -} IADC_DigitalAveraging_t; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** IADC init structure, common for single conversion and scan sequence. */ -typedef struct { - bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */ - bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */ - bool debugHalt; /**< Halt IADC during debug mode. */ - IADC_Warmup_t warmup; /**< IADC warmup mode. */ - uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us. - Used as time reference for IADC delays, e.g. warmup. - If the user sets timebase to 0, then IADC_Init() will - calculate the timebase using the currently defined CMU - clock setting for the IADC. */ - uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which - will be used if the calculated prescaler value is less. */ - uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */ - uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */ - uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */ -} IADC_Init_t; - -/** Default config for IADC init structure. */ -#define IADC_INIT_DEFAULT \ - { \ - false, /* IADC clock not disabled on PRS0*/ \ - false, /* IADC clock not disabled on PRS1 */ \ - false, /* Do not halt during debug */ \ - iadcWarmupNormal, /* IADC shutdown after each conversion. */ \ - 0, /* Calculate timebase. */ \ - 0, /* Max IADC clock rate. */ \ - _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \ - _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \ - _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \ - } - -/** IADC config structure */ -typedef struct { - IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */ - IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */ -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */ -#endif - IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */ - IADC_CfgReference_t reference; /**< Reference selection. */ - IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */ - uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */ - uint32_t vRef; /**< Vref magnitude expressed in millivolts. */ -#if defined(_IADC_CFG_DIGAVG_MASK) - IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */ -#endif -} IADC_Config_t; - -#if defined(_IADC_CFG_DIGAVG_MASK) -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210, /* Vref expressed in millivolts. */ \ - iadcDigitalAverage1 /* No averaging. */ \ - } -#else -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210, /* Vref expressed in millivolts. */ \ - iadcDigitalAverage1 /* No averaging. */ \ - } -#endif -#else -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210 /* Vref expressed in millivolts. */ \ - } -#else -/** Default IADC config structure. */ -#define IADC_CONFIG_DEFAULT \ - { \ - iadcCfgModeNormal, /* Normal mode for IADC. */ \ - iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ - iadcCfgAnalogGain1x, /* 1x analog gain. */ \ - iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ - iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ - 0, /* Max IADC analog clock rate. */ \ - 1210 /* Vref expressed in millivolts. */ \ - } -#endif -#endif - -/** Structure for all IADC configs. */ -typedef struct { - /** All IADC configs. */ - IADC_Config_t configs[IADC0_CONFIGNUM]; -} IADC_AllConfigs_t; - -/** Default IADC sructure for all configs. */ -#define IADC_ALLCONFIGS_DEFAULT \ - { \ - { \ - IADC_CONFIG_DEFAULT, \ - IADC_CONFIG_DEFAULT \ - } \ - } - -/** IADC scan init structure */ -typedef struct { - IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ - bool showId; /**< Tag FIFO entry with scan table entry id. */ - IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ - bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ - IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ - IADC_TriggerAction_t triggerAction; /**< Trigger action. */ - bool start; /**< Start scan immediately. */ -} IADC_InitScan_t; - -/** Default config for IADC scan init structure. */ -#define IADC_INITSCAN_DEFAULT \ - { \ - iadcAlignRight12, /* Results 12-bit right aligned */ \ - false, /* Do not show ID in result */ \ - iadcFifoCfgDvl4, /* Use HW default value. */ \ - false, /* Do not wake up DMA on scan FIFO DVL */ \ - iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \ - iadcTriggerActionOnce, /* Convert once on scan trigger */ \ - false /* Do not start scan queue */ \ - } - -/** IADC single init structure */ -typedef struct { - IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ - bool showId; /**< Tag FIFO entry with single indicator (0x20). */ - IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ - bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ - IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ - IADC_TriggerAction_t triggerAction; /**< Trigger action. */ - bool singleTailgate; /**< If true, wait until end of SCAN queue - before single queue warmup and conversion. */ - bool start; /**< Start scan immediately. */ -} IADC_InitSingle_t; - -/** Default config for IADC single init structure. */ -#define IADC_INITSINGLE_DEFAULT \ - { \ - iadcAlignRight12, /* Results 12-bit right aligned */ \ - false, /* Do not show ID in result */ \ - iadcFifoCfgDvl4, /* Use HW default value. */ \ - false, /* Do not wake up DMA on single FIFO DVL */ \ - iadcTriggerSelImmediate, /* Start single immediately on trigger */ \ - iadcTriggerActionOnce, /* Convert once on single trigger */ \ - false, /* No tailgating */ \ - false /* Do not start single queue */ \ - } - -/** IADC single input selection structure */ -typedef struct { - IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ - IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ - uint8_t configId; /**< Configuration id. */ - bool compare; /**< Perform digital window comparison on the result from this entry. */ -} IADC_SingleInput_t; - -/** Default config for IADC single input structure. */ -#define IADC_SINGLEINPUT_DEFAULT \ - { \ - iadcNegInputGnd, /* Negative input GND */ \ - iadcPosInputGnd, /* Positive input GND */ \ - 0, /* Config 0 */ \ - false /* Do not compare results */ \ - } - -/** IADC scan table entry structure */ -typedef struct { - IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ - IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ - uint8_t configId; /**< Configuration id. */ - bool compare; /**< Perform digital window comparison on the result from this entry. */ - bool includeInScan; /**< Include this scan table entry in scan operation. */ -} IADC_ScanTableEntry_t; - -/** Default config for IADC scan table entry structure. */ -#define IADC_SCANTABLEENTRY_DEFAULT \ - { \ - iadcNegInputGnd,/* Negative input GND */ \ - iadcPosInputGnd,/* Positive input GND */ \ - 0, /* Config 0 */ \ - false, /* Do not compare results */ \ - false /* Do not include in scan */ \ - } - -/** Structure for IADC scan table. */ -typedef struct { - /** IADC scan table entries. */ - IADC_ScanTableEntry_t entries[IADC0_ENTRIES]; -} IADC_ScanTable_t; - -/** Default IADC structure for scan table */ -#define IADC_SCANTABLE_DEFAULT \ - { \ - { \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT, \ - IADC_SCANTABLEENTRY_DEFAULT \ - } \ - } - -/** Structure holding IADC result, including data and ID */ -typedef struct { - uint32_t data; /**< ADC sample data. */ - uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */ -} IADC_Result_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init, - const IADC_AllConfigs_t *allConfigs); -void IADC_reset(IADC_TypeDef *iadc); -void IADC_initScan(IADC_TypeDef *iadc, - const IADC_InitScan_t *init, - const IADC_ScanTable_t *scanTable); -void IADC_updateScanEntry(IADC_TypeDef *iadc, - uint8_t id, - IADC_ScanTableEntry_t *entry); -void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask); -void IADC_initSingle(IADC_TypeDef *iadc, - const IADC_InitSingle_t *init, - const IADC_SingleInput_t *input); -void IADC_updateSingleInput(IADC_TypeDef *iadc, - const IADC_SingleInput_t *input); -uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, - uint32_t srcClkFreq, - uint32_t cmuClkFreq); -uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, - uint32_t adcClkFreq, - uint32_t cmuClkFreq, - IADC_CfgAdcMode_t adcMode, - uint8_t srcClkPrescaler); -uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq); -IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc); -IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc); -uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference); - -/***************************************************************************//** - * @brief - * Pull data from single data FIFO. If showId was set when initializing - * single mode, the results will contain the ID (0x20). - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc) -{ - return iadc->SINGLEFIFODATA; -} - -/***************************************************************************//** - * @brief - * Read most recent single conversion data. If showId was set when - * initializing single mode, the data will contain the ID (0x20). Calling - * this function will not affect the state of the single data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc) -{ - return iadc->SINGLEDATA; -} - -/***************************************************************************//** - * @brief - * Pull data from scan data FIFO. If showId was set for the scan entry - * initialization, the data will contain the ID of the scan entry. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc) -{ - return iadc->SCANFIFODATA; -} - -/***************************************************************************//** - * @brief - * Read most recent scan conversion data. If showId was set for the scan - * entry initialization, the data will contain the ID of the scan entry. - * Calling this function will not affect the state of the scan data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion data. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc) -{ - return iadc->SCANDATA; -} - -/***************************************************************************//** - * @brief - * Clear one or more pending IADC interrupts. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * Pending IADC interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IF_CLR = flags; -} - -/***************************************************************************//** - * @brief - * Disable one or more IADC interrupts. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags) -{ -#if defined (IADC_HAS_SET_CLEAR) - iadc->IEN_CLR = flags; -#else - iadc->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more IADC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. Consider using IADC_intClear() prior to enabling - * if such a pending interrupt should be ignored. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending IADC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * IADC interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc) -{ - return iadc->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending IADC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Pending and enabled IADC interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn - * register (IADCx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the IADC module - * (IADCx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc) -{ - uint32_t ien; - - /* Store IADCx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = iadc->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return iadc->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending IADC interrupts from SW. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] flags - * IADC interrupt sources to set to pending. Use a bitwise logic OR combination - * of valid interrupt flags for the IADC module (IADC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags) -{ - iadc->IF_SET = flags; -} - -/***************************************************************************//** - * @brief - * Start/stop scan sequence, single conversion and/or timer. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] cmd - * Command to be performed. - ******************************************************************************/ -__STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd) -{ - iadc->CMD = (uint32_t)cmd; -} - -/***************************************************************************//** - * @brief - * Get the scan mask currently used in the IADC. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Mask of scan table entries currently included in scan. - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc) -{ - return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT; -} - -/***************************************************************************//** - * @brief - * Get status bits of IADC. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * IADC status bits - ******************************************************************************/ -__STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc) -{ - return iadc->STATUS; -} - -/***************************************************************************//** - * @brief - * Get the number of elements in the IADC single FIFO. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Number of elements in single FIFO - ******************************************************************************/ -__STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc) -{ - return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK) - >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get the number of elements in the IADC scan FIFO. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Number of elements in scan FIFO - ******************************************************************************/ -__STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc) -{ - return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK) - >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT); -} - -/***************************************************************************//** - * @brief - * Convert the GPIO port/pin to IADC negative input selection. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO in - * - * @return - * IADC negative input selection - ******************************************************************************/ -__STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port, - uint8_t pin) -{ - uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin; - - return (IADC_NegInput_t) input; -} - -/***************************************************************************//** - * @brief - * Convert the GPIO port/pin to IADC positive input selection. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO in - * - * @return - * IADC positive input selection - ******************************************************************************/ -__STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port, - uint8_t pin) -{ - uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin; - - return (IADC_PosInput_t) input; -} - -/** @} (end addtogroup iadc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ -#endif /* EM_IADC_H */ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_IADC_H +#define EM_IADC_H + +#include "em_device.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup iadc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Warm-up mode. */ +typedef enum { + /** IADC shutdown after each conversion. */ + iadcWarmupNormal = _IADC_CTRL_WARMUPMODE_NORMAL, + + /** ADC is kept in standby mode between conversion. */ + iadcWarmupKeepInStandby = _IADC_CTRL_WARMUPMODE_KEEPINSTANDBY, + + /** ADC and reference selected for scan mode kept warmup, allowing + continuous conversion. */ + iadcWarmupKeepWarm = _IADC_CTRL_WARMUPMODE_KEEPWARM +} IADC_Warmup_t; + +/** IADC result alignment. */ +typedef enum { + /** IADC results 12-bit right aligned */ + iadcAlignRight12 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT12, + + /** IADC results 12-bit left aligned */ + iadcAlignLeft12 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT12, + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + /** IADC results 16-bit right aligned */ + iadcAlignRight16 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT16, + + /** IADC results 16-bit left aligned */ + iadcAlignLeft16 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT16, +#endif + +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + /** IADC results 20-bit right aligned */ + iadcAlignRight20 = _IADC_SCANFIFOCFG_ALIGNMENT_RIGHT20, + + /** IADC results 20-bit left aligned */ + iadcAlignLeft20 = _IADC_SCANFIFOCFG_ALIGNMENT_LEFT20, +#endif +} IADC_Alignment_t; + +/** IADC negative input selection. */ +typedef enum { + /** Ground */ + iadcNegInputGnd = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)) + | 1, + /** Ground using even mux */ + iadcNegInputGndaux = (_IADC_SCAN_PORTNEG_GND << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + +#if defined(_IADC_SCAN_PORTNEG_DAC1) + /** Direct connection to DAC_1 input pin */ + iadcNegInputDac1 = (_IADC_SCAN_PORTNEG_DAC1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA1) + /** Direct connection to Pad_ana_1 input pin */ + iadcNegInputPadAna1 = (_IADC_SCAN_PORTNEG_PADANA1 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADANA3) + /** Direct connection to Pad_ana_3 input pin */ + iadcNegInputPadAna3 = (_IADC_SCAN_PORTNEG_PADANA3 << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTNEG_PADREFNEG) + /** Negative reference pin 0 */ + iadcNegInputNegRef = (_IADC_SCAN_PORTNEG_PADREFNEG << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), +#endif + /** GPIO port A pin 0 */ + iadcNegInputPortAPin0 = (_IADC_SCAN_PORTNEG_PORTA << (_IADC_SCAN_PORTNEG_SHIFT - _IADC_SCAN_PINNEG_SHIFT)), + + /** GPIO port A pin 1 */ + iadcNegInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcNegInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcNegInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcNegInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcNegInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcNegInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcNegInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcNegInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcNegInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcNegInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcNegInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcNegInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcNegInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcNegInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcNegInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcNegInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcNegInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcNegInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcNegInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcNegInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcNegInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcNegInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcNegInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcNegInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcNegInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcNegInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcNegInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcNegInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcNegInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcNegInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcNegInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcNegInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcNegInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcNegInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcNegInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcNegInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcNegInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcNegInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcNegInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcNegInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcNegInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcNegInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcNegInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcNegInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcNegInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcNegInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcNegInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcNegInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcNegInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcNegInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcNegInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcNegInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcNegInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcNegInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcNegInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcNegInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcNegInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcNegInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcNegInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcNegInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcNegInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcNegInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcNegInputPortDPin15 +} IADC_NegInput_t; + +/** IADC positive port selection. */ +typedef enum { + /** Ground */ + iadcPosInputGnd = (_IADC_SCAN_PORTPOS_GND << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** Avdd / 4 */ + iadcPosInputAvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 0, + + /** Vddio / 4 */ + iadcPosInputVddio = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 1, + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + /** Vddio1 / 4 */ + iadcPosInputVddio1 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vddio2 / 4 */ + iadcPosInputVddio2 = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#else + /** Vss */ + iadcPosInputVss = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 2, + + /** Vss */ + iadcPosInputVssaux = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 3, +#endif + + /** Dvdd / 4 */ + iadcPosInputDvdd = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 4, + + /** Decouple */ + iadcPosInputDecouple = (_IADC_SCAN_PORTPOS_SUPPLY << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)) + | 7, + +#if defined(_IADC_SCAN_PORTPOS_DAC0) + /** Direct connection to DAC_0 input pin */ + iadcPosInputDac0 = (_IADC_SCAN_PORTPOS_DAC0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA0) + /** Direct connection to Pad_ana_0 input pin */ + iadcPosInputPadAna0 = (_IADC_SCAN_PORTPOS_PADANA0 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADANA2) + /** Direct connection to Pad_ana_2 input pin */ + iadcPosInputPadAna2 = (_IADC_SCAN_PORTPOS_PADANA2 << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif +#if defined(_IADC_SCAN_PORTPOS_PADREFPOS) + /** Positive reference pin 0 */ + iadcPosInputPosRef = (_IADC_SCAN_PORTPOS_PADREFPOS << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), +#endif + + /** GPIO port A pin 0 */ + iadcPosInputPortAPin0 = (_IADC_SCAN_PORTPOS_PORTA << (_IADC_SCAN_PORTPOS_SHIFT - _IADC_SCAN_PINPOS_SHIFT)), + + /** GPIO port A pin 1 */ + iadcPosInputPortAPin1, + + /** GPIO port A pin 2 */ + iadcPosInputPortAPin2, + + /** GPIO port A pin 3 */ + iadcPosInputPortAPin3, + + /** GPIO port A pin 4 */ + iadcPosInputPortAPin4, + + /** GPIO port A pin 5 */ + iadcPosInputPortAPin5, + + /** GPIO port A pin 6 */ + iadcPosInputPortAPin6, + + /** GPIO port A pin 7 */ + iadcPosInputPortAPin7, + + /** GPIO port A pin 8 */ + iadcPosInputPortAPin8, + + /** GPIO port A pin 9 */ + iadcPosInputPortAPin9, + + /** GPIO port A pin 10 */ + iadcPosInputPortAPin10, + + /** GPIO port A pin 11 */ + iadcPosInputPortAPin11, + + /** GPIO port A pin 12 */ + iadcPosInputPortAPin12, + + /** GPIO port A pin 13 */ + iadcPosInputPortAPin13, + + /** GPIO port A pin 14 */ + iadcPosInputPortAPin14, + + /** GPIO port A pin 15 */ + iadcPosInputPortAPin15, + + /** GPIO port B pin 0 */ + iadcPosInputPortBPin0, + + /** GPIO port B pin 1 */ + iadcPosInputPortBPin1, + + /** GPIO port B pin 2 */ + iadcPosInputPortBPin2, + + /** GPIO port B pin 3 */ + iadcPosInputPortBPin3, + + /** GPIO port B pin 4 */ + iadcPosInputPortBPin4, + + /** GPIO port B pin 5 */ + iadcPosInputPortBPin5, + + /** GPIO port B pin 6 */ + iadcPosInputPortBPin6, + + /** GPIO port B pin 7 */ + iadcPosInputPortBPin7, + + /** GPIO port B pin 8 */ + iadcPosInputPortBPin8, + + /** GPIO port B pin 9 */ + iadcPosInputPortBPin9, + + /** GPIO port B pin 10 */ + iadcPosInputPortBPin10, + + /** GPIO port B pin 11 */ + iadcPosInputPortBPin11, + + /** GPIO port B pin 12 */ + iadcPosInputPortBPin12, + + /** GPIO port B pin 13 */ + iadcPosInputPortBPin13, + + /** GPIO port B pin 14 */ + iadcPosInputPortBPin14, + + /** GPIO port B pin 15 */ + iadcPosInputPortBPin15, + + /** GPIO port C pin 0 */ + iadcPosInputPortCPin0, + + /** GPIO port C pin 1 */ + iadcPosInputPortCPin1, + + /** GPIO port C pin 2 */ + iadcPosInputPortCPin2, + + /** GPIO port C pin 3 */ + iadcPosInputPortCPin3, + + /** GPIO port C pin 4 */ + iadcPosInputPortCPin4, + + /** GPIO port C pin 5 */ + iadcPosInputPortCPin5, + + /** GPIO port C pin 6 */ + iadcPosInputPortCPin6, + + /** GPIO port C pin 7 */ + iadcPosInputPortCPin7, + + /** GPIO port C pin 8 */ + iadcPosInputPortCPin8, + + /** GPIO port C pin 9 */ + iadcPosInputPortCPin9, + + /** GPIO port C pin 10 */ + iadcPosInputPortCPin10, + + /** GPIO port C pin 11 */ + iadcPosInputPortCPin11, + + /** GPIO port C pin 12 */ + iadcPosInputPortCPin12, + + /** GPIO port C pin 13 */ + iadcPosInputPortCPin13, + + /** GPIO port C pin 14 */ + iadcPosInputPortCPin14, + + /** GPIO port C pin 15 */ + iadcPosInputPortCPin15, + + /** GPIO port D pin 0 */ + iadcPosInputPortDPin0, + + /** GPIO port D pin 1 */ + iadcPosInputPortDPin1, + + /** GPIO port D pin 2 */ + iadcPosInputPortDPin2, + + /** GPIO port D pin 3 */ + iadcPosInputPortDPin3, + + /** GPIO port D pin 4 */ + iadcPosInputPortDPin4, + + /** GPIO port D pin 5 */ + iadcPosInputPortDPin5, + + /** GPIO port D pin 6 */ + iadcPosInputPortDPin6, + + /** GPIO port D pin 7 */ + iadcPosInputPortDPin7, + + /** GPIO port D pin 8 */ + iadcPosInputPortDPin8, + + /** GPIO port D pin 9 */ + iadcPosInputPortDPin9, + + /** GPIO port D pin 10 */ + iadcPosInputPortDPin10, + + /** GPIO port D pin 11 */ + iadcPosInputPortDPin11, + + /** GPIO port D pin 12 */ + iadcPosInputPortDPin12, + + /** GPIO port D pin 13 */ + iadcPosInputPortDPin13, + + /** GPIO port D pin 14 */ + iadcPosInputPortDPin14, + + /** GPIO port D pin 15 */ + iadcPosInputPortDPin15 +} IADC_PosInput_t; + +/** IADC Commands. */ +typedef enum { + /** Start single queue */ + iadcCmdStartSingle = IADC_CMD_SINGLESTART, + + /** Stop single queue */ + iadcCmdStopSingle = IADC_CMD_SINGLESTOP, + + /** Start scan queue */ + iadcCmdStartScan = IADC_CMD_SCANSTART, + + /** Stop scan queue */ + iadcCmdStopScan = IADC_CMD_SCANSTOP, + + /** Enable Timer */ + iadcCmdEnableTimer = IADC_CMD_TIMEREN, + + /** Disable Timer */ + iadcCmdDisableTimer = IADC_CMD_TIMERDIS +} IADC_Cmd_t; + +/** IADC Configuration. */ +typedef enum { + /** Normal mode */ + iadcCfgModeNormal = _IADC_CFG_ADCMODE_NORMAL, +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + /** High Speed mode */ + iadcCfgModeHighSpeed = _IADC_CFG_ADCMODE_HIGHSPEED, +#endif +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + /** High Accuracy mode */ + iadcCfgModeHighAccuracy = _IADC_CFG_ADCMODE_HIGHACCURACY +#endif +} IADC_CfgAdcMode_t; + +/** IADC Over sampling rate for high speed. */ +typedef enum { + /** High speed oversampling of 2x */ + iadcCfgOsrHighSpeed2x = _IADC_CFG_OSRHS_HISPD2, + + /** High speed oversampling of 4x */ + iadcCfgOsrHighSpeed4x = _IADC_CFG_OSRHS_HISPD4, + + /** High speed oversampling of 8x */ + iadcCfgOsrHighSpeed8x = _IADC_CFG_OSRHS_HISPD8, + + /** High speed oversampling of 16x */ + iadcCfgOsrHighSpeed16x = _IADC_CFG_OSRHS_HISPD16, + + /** High speed oversampling of 32x */ + iadcCfgOsrHighSpeed32x = _IADC_CFG_OSRHS_HISPD32, + + /** High speed oversampling of 64x */ + iadcCfgOsrHighSpeed64x = _IADC_CFG_OSRHS_HISPD64 +} IADC_CfgOsrHighSpeed_t; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** IADC Over sampling rate for high accuracy. */ +typedef enum { + /** High accuracy oversampling of 16x */ + iadcCfgOsrHighAccuracy16x = _IADC_CFG_OSRHA_HIACC16, + + /** High accuracy oversampling of 32x */ + iadcCfgOsrHighAccuracy32x = _IADC_CFG_OSRHA_HIACC32, + + /** High accuracy oversampling of 64x */ + iadcCfgOsrHighAccuracy64x = _IADC_CFG_OSRHA_HIACC64, + + /** High accuracy oversampling of 92x */ + iadcCfgOsrHighAccuracy92x = _IADC_CFG_OSRHA_HIACC92, + + /** High accuracy oversampling of 128x */ + iadcCfgOsrHighAccuracy128x = _IADC_CFG_OSRHA_HIACC128, + + /** High accuracy oversampling of 256x */ + iadcCfgOsrHighAccuracy256x = _IADC_CFG_OSRHA_HIACC256 +} IADC_CfgOsrHighAccuracy_t; +#endif + +/** IADC Analog Gain. */ +typedef enum { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + /** Analog gain of 0.25x */ + iadcCfgAnalogGain0P25x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P25, +#endif + /** Analog gain of 0.5x */ + iadcCfgAnalogGain0P5x = _IADC_CFG_ANALOGGAIN_ANAGAIN0P5, + + /** Analog gain of 1x */ + iadcCfgAnalogGain1x = _IADC_CFG_ANALOGGAIN_ANAGAIN1, + + /** Analog gain of 2x */ + iadcCfgAnalogGain2x = _IADC_CFG_ANALOGGAIN_ANAGAIN2, + + /** Analog gain of 3x */ + iadcCfgAnalogGain3x = _IADC_CFG_ANALOGGAIN_ANAGAIN3, + + /** Analog gain of 4x */ + iadcCfgAnalogGain4x = _IADC_CFG_ANALOGGAIN_ANAGAIN4 +} IADC_CfgAnalogGain_t; + +/** IADC Reference */ +typedef enum { + /** Internal 1.2V Band Gap Reference (buffered) to ground */ + iadcCfgReferenceInt1V2 = _IADC_CFG_REFSEL_VBGR, + + /** External reference (unbuffered) VREFP to VREFN. + * VEVREF up to AVDD. When inputs are routed to external GPIO pins, + * the maximum pin voltage is limited to the lower + * of the IOVDD and AVDD supplies. + * The internal calibration values correspond to a 1.25V reference, + * use of other voltages may require recalibration. + * See AN1189: Incremental Analog to Digital Converter (IADC) */ + iadcCfgReferenceExt1V25 = _IADC_CFG_REFSEL_VREF, + +#if defined(_IADC_CFG_REFSEL_VREF2P5) + /** External reference (unbuffered) VREFP to VREFN. Supports 2.5V in high accuracy mode. */ + iadcCfgReferenceExt2V5 = _IADC_CFG_REFSEL_VREF2P5, +#endif + + /** VDDX (unbuffered) to ground. */ + iadcCfgReferenceVddx = _IADC_CFG_REFSEL_VDDX, + + /** 0.8 * VDDX (buffered) to ground. */ + iadcCfgReferenceVddX0P8Buf = _IADC_CFG_REFSEL_VDDX0P8BUF, + +#if defined(_IADC_CFG_REFSEL_VREFBUF) + /** pad_vrefp (buffered) to pad_vrefn (pad_refp < vddx - 0.3) */ + iadcCfgReferenceBuf = _IADC_CFG_REFSEL_VREFBUF, +#endif + +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + /** pad_vref (buffered) * 0.8 to pad_vrefn (LPF pad_refp noise) */ + iadcCfgReference0P8Buf = _IADC_CFG_REFSEL_VREF0P8BUF, +#endif +} IADC_CfgReference_t; + +/** IADC Two's complement results */ +typedef enum { + /** Automatic. Single ended => Unipolar, Differential => Bipolar */ + iadcCfgTwosCompAuto = _IADC_CFG_TWOSCOMPL_AUTO, + + /** All results in unipolar format. Negative diff input gives 0 as result. */ + iadcCfgTwosCompUnipolar = _IADC_CFG_TWOSCOMPL_FORCEUNIPOLAR, + + /** All results in bipolar (2's complement) format. Half range for SE. */ + iadcCfgTwosCompBipolar = _IADC_CFG_TWOSCOMPL_FORCEBIPOLAR +} IADC_CfgTwosComp_t; + +/** IADC trigger action */ +typedef enum { + /** Start single/scan queue immediately */ + iadcTriggerSelImmediate = _IADC_TRIGGER_SCANTRIGSEL_IMMEDIATE, + + /** Timer starts single/scan queue */ + iadcTriggerSelTimer = _IADC_TRIGGER_SCANTRIGSEL_TIMER, + + /** PRS0 from timer in same clock group starts single/scan queue */ + iadcTriggerSelPrs0SameClk = _IADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP, + + /** PRS0 positive edge starts single/scan queue */ + iadcTriggerSelPrs0PosEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSPOS, + + /** PRS0 negative edge starts single/scan queue */ + iadcTriggerSelPrs0NegEdge = _IADC_TRIGGER_SCANTRIGSEL_PRSNEG, + +#if defined(_IADC_TRIGGER_SCANTRIGSEL_LESENSE) + /** LESENSE starts scan queue */ + iadcTriggerSelLesense = _IADC_TRIGGER_SCANTRIGSEL_LESENSE +#endif +} IADC_TriggerSel_t; + +/** IADC trigger action */ +typedef enum { + /** Convert single/scan queue once per trigger */ + iadcTriggerActionOnce = _IADC_TRIGGER_SCANTRIGACTION_ONCE, + + /** Convert single/scan queue continuously */ + iadcTriggerActionContinuous = _IADC_TRIGGER_SCANTRIGACTION_CONTINUOUS, +} IADC_TriggerAction_t; + +/** IADC data valid level before requesting DMA transfer */ +typedef enum { + /** Data valid level is 1 before requesting DMA transfer */ + iadcFifoCfgDvl1 = _IADC_SCANFIFOCFG_DVL_VALID1, + + /** Data valid level is 2 before requesting DMA transfer */ + iadcFifoCfgDvl2 = _IADC_SCANFIFOCFG_DVL_VALID2, + + /** Data valid level is 3 before requesting DMA transfer */ + iadcFifoCfgDvl3 = _IADC_SCANFIFOCFG_DVL_VALID3, + + /** Data valid level is 4 before requesting DMA transfer */ + iadcFifoCfgDvl4 = _IADC_SCANFIFOCFG_DVL_VALID4, + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 2 + /** Data valid level is 5 before requesting DMA transfer */ + iadcFifoCfgDvl5 = _IADC_SCANFIFOCFG_DVL_VALID5, + + /** Data valid level is 6 before requesting DMA transfer */ + iadcFifoCfgDvl6 = _IADC_SCANFIFOCFG_DVL_VALID6, + + /** Data valid level is 7 before requesting DMA transfer */ + iadcFifoCfgDvl7 = _IADC_SCANFIFOCFG_DVL_VALID7, +#endif + +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 3 + /** Data valid level is 8 before requesting DMA transfer */ + iadcFifoCfgDvl8 = _IADC_SCANFIFOCFG_DVL_VALID8 +#endif +#endif +} IADC_FifoCfgDvl_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +/** IADC digital averaging function. */ +typedef enum { + /** Average over 1 sample (no averaging). */ + iadcDigitalAverage1 = _IADC_CFG_DIGAVG_AVG1, + + /** Average over 2 samples. */ + iadcDigitalAverage2 = _IADC_CFG_DIGAVG_AVG2, + + /** Average over 4 samples. */ + iadcDigitalAverage4 = _IADC_CFG_DIGAVG_AVG4, + + /** Average over 8 samples. */ + iadcDigitalAverage8 = _IADC_CFG_DIGAVG_AVG8, + + /** Average over 16 samples. */ + iadcDigitalAverage16 = _IADC_CFG_DIGAVG_AVG16 +} IADC_DigitalAveraging_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** IADC init structure, common for single conversion and scan sequence. */ +typedef struct { + bool iadcClkSuspend0; /**< Suspend IADC_CLK when in scan mode until PRS trigger. */ + bool iadcClkSuspend1; /**< Suspend IADC_CLK when in single mode until PRS trigger. */ + bool debugHalt; /**< Halt IADC during debug mode. */ + IADC_Warmup_t warmup; /**< IADC warmup mode. */ + uint8_t timebase; /**< IADC clock cycles (timebase+1) corresponding to 1us. + Used as time reference for IADC delays, e.g. warmup. + If the user sets timebase to 0, then IADC_Init() will + calculate the timebase using the currently defined CMU + clock setting for the IADC. */ + uint8_t srcClkPrescale; /**< User requested source clock divider (prescale+1) which + will be used if the calculated prescaler value is less. */ + uint16_t timerCycles; /**< Number of ADC_CLK cycles per TIMER event. */ + uint16_t greaterThanEqualThres; /**< Digital window comparator greater-than or equal threshold. */ + uint16_t lessThanEqualThres; /**< Digital window comparator less-than or equal threshold. */ +} IADC_Init_t; + +/** Default config for IADC init structure. */ +#define IADC_INIT_DEFAULT \ + { \ + false, /* IADC clock not disabled on PRS0*/ \ + false, /* IADC clock not disabled on PRS1 */ \ + false, /* Do not halt during debug */ \ + iadcWarmupNormal, /* IADC shutdown after each conversion. */ \ + 0, /* Calculate timebase. */ \ + 0, /* Max IADC clock rate. */ \ + _IADC_TIMER_TIMER_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADGT_DEFAULT, /* Use HW default value. */ \ + _IADC_CMPTHR_ADLT_DEFAULT, /* Use HW default value. */ \ + } + +/** IADC config structure */ +typedef struct { + IADC_CfgAdcMode_t adcMode; /**< IADC mode; Normal, High speed or High Accuracy. */ + IADC_CfgOsrHighSpeed_t osrHighSpeed; /**< Over sampling ratio for High Speed and Normal modes. */ +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + IADC_CfgOsrHighAccuracy_t osrHighAccuracy; /**< Over sampling ratio for High Accuracy mode. */ +#endif + IADC_CfgAnalogGain_t analogGain; /**< Analog gain. */ + IADC_CfgReference_t reference; /**< Reference selection. */ + IADC_CfgTwosComp_t twosComplement; /**< Two's complement reporting. */ + uint32_t adcClkPrescale; /**< ADC_CLK divider (prescale+1). */ + uint32_t vRef; /**< Vref magnitude expressed in millivolts. */ +#if defined(_IADC_CFG_DIGAVG_MASK) + IADC_DigitalAveraging_t digAvg; /**< Digital average mode. */ +#endif +} IADC_Config_t; + +#if defined(_IADC_CFG_DIGAVG_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high accuracy over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210, /* Vref expressed in millivolts. */ \ + iadcDigitalAverage1 /* No averaging. */ \ + } +#endif +#else +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgOsrHighAccuracy92x, /* 92x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#else +/** Default IADC config structure. */ +#define IADC_CONFIG_DEFAULT \ + { \ + iadcCfgModeNormal, /* Normal mode for IADC. */ \ + iadcCfgOsrHighSpeed2x, /* 2x high speed over sampling. */ \ + iadcCfgAnalogGain1x, /* 1x analog gain. */ \ + iadcCfgReferenceInt1V2, /* Internal 1.2V band gap reference. */ \ + iadcCfgTwosCompAuto, /* Automatic Two's Complement. */ \ + 0, /* Max IADC analog clock rate. */ \ + 1210 /* Vref expressed in millivolts. */ \ + } +#endif +#endif + +/** Structure for all IADC configs. */ +typedef struct { + /** All IADC configs. */ + IADC_Config_t configs[IADC0_CONFIGNUM]; +} IADC_AllConfigs_t; + +/** Default IADC sructure for all configs. */ +#define IADC_ALLCONFIGS_DEFAULT \ + { \ + { \ + IADC_CONFIG_DEFAULT, \ + IADC_CONFIG_DEFAULT \ + } \ + } + +/** IADC scan init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with scan table entry id. */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool start; /**< Start scan immediately. */ +} IADC_InitScan_t; + +/** Default config for IADC scan init structure. */ +#define IADC_INITSCAN_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on scan FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start scan immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on scan trigger */ \ + false /* Do not start scan queue */ \ + } + +/** IADC single init structure */ +typedef struct { + IADC_Alignment_t alignment; /**< Alignment of data in FIFO. */ + bool showId; /**< Tag FIFO entry with single indicator (0x20). */ + IADC_FifoCfgDvl_t dataValidLevel; /**< Data valid level before requesting DMA transfer. */ + bool fifoDmaWakeup; /**< Wake-up DMA when FIFO reaches data valid level. */ + IADC_TriggerSel_t triggerSelect; /**< Trigger selection. */ + IADC_TriggerAction_t triggerAction; /**< Trigger action. */ + bool singleTailgate; /**< If true, wait until end of SCAN queue + before single queue warmup and conversion. */ + bool start; /**< Start scan immediately. */ +} IADC_InitSingle_t; + +/** Default config for IADC single init structure. */ +#define IADC_INITSINGLE_DEFAULT \ + { \ + iadcAlignRight12, /* Results 12-bit right aligned */ \ + false, /* Do not show ID in result */ \ + iadcFifoCfgDvl4, /* Use HW default value. */ \ + false, /* Do not wake up DMA on single FIFO DVL */ \ + iadcTriggerSelImmediate, /* Start single immediately on trigger */ \ + iadcTriggerActionOnce, /* Convert once on single trigger */ \ + false, /* No tailgating */ \ + false /* Do not start single queue */ \ + } + +/** IADC single input selection structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ +} IADC_SingleInput_t; + +/** Default config for IADC single input structure. */ +#define IADC_SINGLEINPUT_DEFAULT \ + { \ + iadcNegInputGnd, /* Negative input GND */ \ + iadcPosInputGnd, /* Positive input GND */ \ + 0, /* Config 0 */ \ + false /* Do not compare results */ \ + } + +/** IADC scan table entry structure */ +typedef struct { + IADC_NegInput_t negInput; /**< Port/pin input for the negative side of the ADC. */ + IADC_PosInput_t posInput; /**< Port/pin input for the positive side of the ADC. */ + uint8_t configId; /**< Configuration id. */ + bool compare; /**< Perform digital window comparison on the result from this entry. */ + bool includeInScan; /**< Include this scan table entry in scan operation. */ +} IADC_ScanTableEntry_t; + +/** Default config for IADC scan table entry structure. */ +#define IADC_SCANTABLEENTRY_DEFAULT \ + { \ + iadcNegInputGnd,/* Negative input GND */ \ + iadcPosInputGnd,/* Positive input GND */ \ + 0, /* Config 0 */ \ + false, /* Do not compare results */ \ + false /* Do not include in scan */ \ + } + +/** Structure for IADC scan table. */ +typedef struct { + /** IADC scan table entries. */ + IADC_ScanTableEntry_t entries[IADC0_ENTRIES]; +} IADC_ScanTable_t; + +/** Default IADC structure for scan table */ +#define IADC_SCANTABLE_DEFAULT \ + { \ + { \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT, \ + IADC_SCANTABLEENTRY_DEFAULT \ + } \ + } + +/** Structure holding IADC result, including data and ID */ +typedef struct { + uint32_t data; /**< ADC sample data. */ + uint8_t id; /**< ID of FIFO entry; Scan table entry id or single indicator (0x20). */ +} IADC_Result_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void IADC_init(IADC_TypeDef *iadc, const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs); +void IADC_reset(IADC_TypeDef *iadc); +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable); +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry); +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask); +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input); +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input); +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq); +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler); +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq); +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc); +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc); +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference); + +/***************************************************************************//** + * @brief + * Pull data from single data FIFO. If showId was set when initializing + * single mode, the results will contain the ID (0x20). + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullSingleFifoData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion data. If showId was set when + * initializing single mode, the data will contain the ID (0x20). Calling + * this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readSingleData(IADC_TypeDef *iadc) +{ + return iadc->SINGLEDATA; +} + +/***************************************************************************//** + * @brief + * Pull data from scan data FIFO. If showId was set for the scan entry + * initialization, the data will contain the ID of the scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_pullScanFifoData(IADC_TypeDef *iadc) +{ + return iadc->SCANFIFODATA; +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion data. If showId was set for the scan + * entry initialization, the data will contain the ID of the scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion data. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_readScanData(IADC_TypeDef *iadc) +{ + return iadc->SCANDATA; +} + +/***************************************************************************//** + * @brief + * Clear one or more pending IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * Pending IADC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_clearInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_CLR = flags; +} + +/***************************************************************************//** + * @brief + * Disable one or more IADC interrupts. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_disableInt(IADC_TypeDef *iadc, uint32_t flags) +{ +#if defined (IADC_HAS_SET_CLEAR) + iadc->IEN_CLR = flags; +#else + iadc->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more IADC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. Consider using IADC_intClear() prior to enabling + * if such a pending interrupt should be ignored. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_enableInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending IADC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getInt(IADC_TypeDef *iadc) +{ + return iadc->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending IADC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Pending and enabled IADC interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in IADCx_IEN_nnn + * register (IADCx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the IADC module + * (IADCx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getEnabledInt(IADC_TypeDef *iadc) +{ + uint32_t ien; + + /* Store IADCx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = iadc->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return iadc->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending IADC interrupts from SW. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] flags + * IADC interrupt sources to set to pending. Use a bitwise logic OR combination + * of valid interrupt flags for the IADC module (IADC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void IADC_setInt(IADC_TypeDef *iadc, uint32_t flags) +{ + iadc->IF_SET = flags; +} + +/***************************************************************************//** + * @brief + * Start/stop scan sequence, single conversion and/or timer. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] cmd + * Command to be performed. + ******************************************************************************/ +__STATIC_INLINE void IADC_command(IADC_TypeDef *iadc, IADC_Cmd_t cmd) +{ + iadc->CMD = (uint32_t)cmd; +} + +/***************************************************************************//** + * @brief + * Get the scan mask currently used in the IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Mask of scan table entries currently included in scan. + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getScanMask(IADC_TypeDef *iadc) +{ + return (iadc->STMASK) >> _IADC_STMASK_STMASK_SHIFT; +} + +/***************************************************************************//** + * @brief + * Get status bits of IADC. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * IADC status bits + ******************************************************************************/ +__STATIC_INLINE uint32_t IADC_getStatus(IADC_TypeDef *iadc) +{ + return iadc->STATUS; +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC single FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in single FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getSingleFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SINGLEFIFOSTAT & _IADC_SINGLEFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SINGLEFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the number of elements in the IADC scan FIFO. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Number of elements in scan FIFO + ******************************************************************************/ +__STATIC_INLINE uint8_t IADC_getScanFifoCnt(IADC_TypeDef *iadc) +{ + return (uint8_t) ((iadc->SCANFIFOSTAT & _IADC_SCANFIFOSTAT_FIFOREADCNT_MASK) + >> _IADC_SCANFIFOSTAT_FIFOREADCNT_SHIFT); +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC negative input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC negative input selection + ******************************************************************************/ +__STATIC_INLINE IADC_NegInput_t IADC_portPinToNegInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTNEG_PORTA) << 4) | pin; + + return (IADC_NegInput_t) input; +} + +/***************************************************************************//** + * @brief + * Convert the GPIO port/pin to IADC positive input selection. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO in + * + * @return + * IADC positive input selection + ******************************************************************************/ +__STATIC_INLINE IADC_PosInput_t IADC_portPinToPosInput(GPIO_Port_TypeDef port, + uint8_t pin) +{ + uint32_t input = (((uint32_t) port + _IADC_SCAN_PORTPOS_PORTA) << 4) | pin; + + return (IADC_PosInput_t) input; +} + +/** @} (end addtogroup iadc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ +#endif /* EM_IADC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h index 5a9bc5f..2c9cfab 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ldma.h @@ -1,2819 +1,2819 @@ -/***************************************************************************//** - * @file - * @brief Direct memory access (LDMA) API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_LDMA_H -#define EM_LDMA_H - -#include "em_device.h" - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup ldma LDMA - Linked DMA - * @brief Linked Direct Memory Access (LDMA) Peripheral API - * - * @details - * LDMA API functions provide full support for the LDMA peripheral. - * - * LDMA supports these DMA transfer types: - * - * @li Memory to memory. - * @li Memory to peripheral. - * @li Peripheral to memory. - * @li Peripheral to peripheral. - * @li Constant value to memory. - * - * LDMA supports linked lists of DMA descriptors allowing: - * - * @li Circular and ping-pong buffer transfers. - * @li Scatter-gather transfers. - * @li Looped transfers. - * - * LDMA has some advanced features: - * - * @li Intra-channel synchronization (SYNC), allowing hardware events to - * pause and restart a DMA sequence. - * @li Immediate-write (WRI), allowing DMA to write a constant anywhere - * in the memory map. - * @li Complex flow control allowing if-else constructs. - * - * Basic understanding of LDMA controller is assumed. Please refer to - * the reference manual for further details. The LDMA examples described - * in the reference manual are particularly helpful in understanding LDMA - * operations. - * - * In order to use the DMA controller, the initialization function @ref - * LDMA_Init() must have been executed once (normally during system initialization). - * - * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), - * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t - * and @ref LDMA_Descriptor_t structure parameters. - * The LDMA_Descriptor_t structure parameter may be a - * pointer to an array of descriptors, descriptors in array should - * be linked together as needed. - * - * Transfer and descriptor initialization macros are provided for the most common - * transfer types. Due to the flexibility of LDMA peripheral, only a small - * subset of all possible initializer macros are provided, users should create - * new ones when needed. - * - * Examples of LDMA usage: - * - * A simple memory to memory transfer: - * - * @include em_ldma_single.c - * - * @n A linked list of three memory to memory transfers: - * - * @include em_ldma_link_memory.c - * - * @n DMA from serial port peripheral to memory: - * - * @include em_ldma_peripheral.c - * - * @n Ping-pong DMA from serial port peripheral to memory: - * - * @include em_ldma_pingpong.c - * - * @note LDMA module does not implement LDMA interrupt handler. A - * template for an LDMA IRQ handler is included here as an example. - * - * @include em_ldma_irq.c - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** - * Controls the number of unit data transfers per arbitration - * cycle, providing a means to balance DMA channels' load on the controller. - */ -typedef enum { - ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ - ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ - ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ - ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ - ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ - ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ - ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ - ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ - ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ -} LDMA_CtrlBlockSize_t; - -/** DMA structure type. */ -typedef enum { - ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ - ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ - ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ -} LDMA_CtrlStructType_t; - -/** DMA transfer block or cycle selector. */ -typedef enum { - ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ - ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ -} LDMA_CtrlReqMode_t; - -/** Source address increment unit size. */ -typedef enum { - ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ - ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ - ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ - ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ -} LDMA_CtrlSrcInc_t; - -/** DMA transfer unit size. */ -typedef enum { - ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ - ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ - ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ -} LDMA_CtrlSize_t; - -/** Destination address increment unit size. */ -typedef enum { - ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ - ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ - ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ - ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ -} LDMA_CtrlDstInc_t; - -/** Source addressing mode. */ -typedef enum { - ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ - ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ -} LDMA_CtrlSrcAddrMode_t; - -/** Destination addressing mode. */ -typedef enum { - ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ - ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ -} LDMA_CtrlDstAddrMode_t; - -/** DMA link load address mode. */ -typedef enum { - ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ - ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ -} LDMA_LinkMode_t; - -/** Insert extra arbitration slots to increase channel arbitration priority. */ -typedef enum { - ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ - ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ - ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ - ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ -} LDMA_CfgArbSlots_t; - -/** Source address increment sign. */ -typedef enum { - ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ - ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ -} LDMA_CfgSrcIncSign_t; - -/** Destination address increment sign. */ -typedef enum { - ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ - ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ -} LDMA_CfgDstIncSign_t; - -#if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK) -/** Structure fetch operation bus port. */ -typedef enum { - ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgStructBusPort_t; -#endif - -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -/** Source operation bus port. */ -typedef enum { - ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgSrcBusPort_t; -#endif - -#if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK) -/** Destination operation bus port. */ -typedef enum { - ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */ - ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */ -} LDMA_CfgDstBusPort_t; -#endif - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** Rules table mode (interleaving destination). */ -typedef enum { - ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */ - ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */ - ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */ -} LDMA_RulesTblMode_t; -#endif - -#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) -/** Peripherals that can trigger LDMA transfers. */ -typedef enum { - ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 - ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 - ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 - ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 - ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 - ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF - ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 - ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 - ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 - ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF - ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV - ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT - ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL - ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT - ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY - ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV - ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT - ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL - ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT - ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY - ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV - ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT - ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL - ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT - ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY - ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV - ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL - ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV - ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL - ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI - ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV) - ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF - ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 - ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 - ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 - ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 - ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 - ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF - ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF - ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG - ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN - ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE - ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA - ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 - ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 - ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 - ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF - ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 - ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 - ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 - ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF - ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 - ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 - ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 - ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF - ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 - ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 - ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 - ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF - ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 - ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 - ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 - ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF - ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD - ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD, - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 - ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 - ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 - ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF - ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ) - ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ) - ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ) - ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ) - ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL - ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL - ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL - ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL - ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL - ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL - ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL - ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL - ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL - ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL - ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL - ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL. - #endif - #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL - ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL. - #endif - #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO) - ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO. - #endif -} LDMA_PeripheralSignal_t; - -#else -/** Peripherals that can trigger LDMA transfers. */ -typedef enum { - ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) - ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) - ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) - ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) - ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) - ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) - ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) - ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) - ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) - ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) - ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) - ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) - ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) - ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) - ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) - ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) - ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) - ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) - ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) - ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) - ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) - ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) - ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) - ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) - ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) - ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) - ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) - ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) - ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) - ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) - ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) - ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) - ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) - ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) - ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) - ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) - ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) - ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) - ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) - ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) - ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) - ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) - ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) - ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) - ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) - ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) - ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) - ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) - ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) - ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) - ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) - ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) - ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) - ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) - ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) - ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) - ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) - ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) - ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) - ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) - ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) - ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) - ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) - ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) - ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) - ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) - ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) - ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) - ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) - ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) - ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) - ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) - ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) - ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) - ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) - ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) - ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) - ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) - ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) - ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) - ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) - ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) - ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) - ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) - ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) - ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) - ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) - ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) - ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) - ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) - ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) - ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) - ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) - ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) - ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) - ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) - ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) - ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) - ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) - ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) - ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) - ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) - ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) - ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) - ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) - ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) - ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) - ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) - ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) - ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) - ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) - ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) - ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) - ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) - ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) - ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) - ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) - ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) - ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) - ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) - ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) - ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. - #endif - #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) - ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. - #endif -} LDMA_PeripheralSignal_t; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** - * @brief - * DMA descriptor. - * @details - * The LDMA DMA controller supports three different DMA descriptors. Each - * consists of four WORDs which map directly onto HW control registers for a - * given DMA channel. The three descriptor types are XFER, SYNC and WRI. - * Refer to the reference manual for further information. - */ -typedef union { - /** - * TRANSFER DMA descriptor, this is the only descriptor type which can be - * used to start a DMA transfer. - */ - struct { - uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t srcAddr; /**< DMA source address. */ - uint32_t dstAddr; /**< DMA destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } xfer; - - /** SYNCHRONIZE DMA descriptor, used for intra channel transfer - * synchronization. - */ - struct { - uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ - uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ - uint32_t reserved1 : 16; /**< Reserved. */ - uint32_t matchVal : 8; /**< Sync trigger match value. */ - uint32_t matchEn : 8; /**< Sync trigger match enable. */ - uint32_t reserved2 : 16; /**< Reserved. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } sync; - - /** WRITE DMA descriptor, used for write immediate operations. */ - struct { - uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ - uint32_t reserved0 : 1; /**< Reserved. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t immVal; /**< Data to be written at dstAddr. */ - uint32_t dstAddr; /**< DMA write destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - } wri; -} LDMA_Descriptor_t; - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA extended descriptor. - * @details - * The extended descriptor adds additional fields for the extended features - * available on the MMLDMA peripheral: destination interleaving and bufferable. - * The same three different DMA descriptors supported by the LDMA DMA controller - * are available. Each consists of seven WORDs (instead of four in non-extended - * descriptors) which map directly onto HW control registers for a given DMA - * channel. The three descriptor types are XFER, SYNC and WRI. But the - * extended fields are true only for XFER. The extended fields are the following: - * - * +- +- CTRL - * | Original | SRC - * | Structure | DST - * Extended | +- LINK - * Structure | XCTRL - * | Reserved for future usage - * +- ILSRC - * - * Refer to the reference manual for further information. - */ -typedef struct { - uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ - uint32_t extend : 1; /**< Extend data structure. */ - uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ - uint32_t xferCnt : 11; /**< Transfer count minus one. */ - uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ - uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ - uint32_t doneIfs : 1; /**< Generate interrupt when done. */ - uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ - uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ - uint32_t ignoreSrec : 1; /**< Ignore single requests. */ - uint32_t srcInc : 2; /**< Source address increment unit size. */ - uint32_t size : 2; /**< DMA transfer unit size. */ - uint32_t dstInc : 2; /**< Destination address increment unit size. */ - uint32_t srcAddrMode : 1; /**< Source addressing mode. */ - uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ - - uint32_t srcAddr; /**< DMA source address. */ - uint32_t dstAddr; /**< DMA destination address. */ - - uint32_t linkMode : 1; /**< Select absolute or relative link address. */ - uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ - int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ - - uint32_t reserved1 : 4; /**< Reserved */ - uint32_t dstIlEn : 1; /**< Destination interleave. */ - uint32_t IlMode : 2; /**< Interleave mode. */ - uint32_t bufferable : 1; /**< Allow AHB buffering. */ - uint32_t reserved2 : 24; /**< Reserved */ - - uint32_t reserved3; /**< Reserved */ - uint32_t IlSrc; /**< DMA rules table base address in memory. */ -} LDMA_DescriptorExtend_t; -#endif - -/** @brief LDMA initialization configuration structure. */ -typedef struct { - uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ - uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ - uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ - uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ -} LDMA_Init_t; - -/** - * @brief - * DMA transfer configuration structure. - * @details - * This structure configures all aspects of a DMA transfer. - */ -typedef struct { - uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ - uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ - uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ - uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ - uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ - bool ldmaReqDis; /**< Mask the PRS trigger input. */ - bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ - LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */ - LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ - LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ - uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) - LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */ - LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */ - LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */ -#endif -} LDMA_TransferCfg_t; - -/******************************************************************************* - ******************************** DEFINES ********************************** - ******************************************************************************/ - -/** @brief Size in words of a non-extended DMA descriptor. */ -#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4 - -/** @brief Size in words of an extended DMA descriptor. */ -#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7 - -/** @brief Maximum transfer size possible per descriptor. */ -#define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) - -/** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */ -#define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT) - -/** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */ -#define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT) - -/******************************************************************************* - ************************** STRUCT INITIALIZERS **************************** - ******************************************************************************/ - -/** @brief Default DMA initialization structure. */ -#define LDMA_INIT_DEFAULT \ - { \ - .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ - .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ - .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ - .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ - } - -/** - * @brief - * Generic DMA transfer configuration for memory to memory transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_MEMORY() \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_MEMORY() \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for looped memory to memory transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ - loopCnt, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ - { \ - 0, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ - loopCnt \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for memory to/from peripheral transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ - } -#endif - -/** - * @brief - * Generic DMA transfer configuration for looped memory to/from peripheral transfers. - */ -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) -#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \ - ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ - } -#else -#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ - { \ - signal, 0, 0, 0, 0, \ - false, false, ldmaCfgArbSlotsAs1, \ - ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory word transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory word transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory half-word transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory half-word transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for single memory to memory byte transfer. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for single memory to memory byte transfer - * using the extended descriptor fields. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer - * using the extended descriptor fields. - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0, /* Must be set runtime ! */ \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory word transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory half-word transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of half-words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeHalf, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for linked memory to memory byte transfer - * using the extended descriptor fields. - * - * Link address is a relative address. - * @note - * The linkAddr member of the transfer descriptor is initialized to 4 - * (regular descriptor) or 7 (extended descriptor), assuming that - * the next descriptor immediately follows this descriptor (in memory). - * @param[in] src Source data address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 1, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 0, \ - .reqMode = ldmaCtrlReqModeAll, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. - * @param[in] src Peripheral data source register address. - * @param[in] dest Peripheral data destination register address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral - * using the extended descriptor fields. - * @note - * For the extended descriptor, if IlMode uses the absolute addressing, the - * rules are used directly as the destination addresses of the corresponding - * data. Thus the argument 'dest' will be ignored by the DMA engine. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - */ -#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for word transfers from a peripheral to memory. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncOne, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for word transfers from a peripheral to memory - * using the extended descriptor fields. - * @param[in] src Peripheral data source register address. - * @param[in] dest Destination data address. - * @param[in] count Number of words to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncNone, \ - .size = ldmaCtrlSizeWord, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ - { \ - .xfer = \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * DMA descriptor initializer for byte transfers from memory to a peripheral - * using the extended descriptor fields. - * @note - * For the extended descriptor, if IlMode uses the absolute addressing, the - * rules are used directly as the destination addresses of the corresponding - * data. Thus the argument 'dest' will be ignored by the DMA engine. - * @param[in] src Source data address. - * @param[in] dest Peripheral data register destination address. - * @param[in] count Number of bytes to transfer. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \ - { \ - .structType = ldmaCtrlStructTypeXfer, \ - .extend = 1, \ - .structReq = 0, \ - .xferCnt = (count) - 1, \ - .byteSwap = 0, \ - .blockSize = ldmaCtrlBlockSizeUnit1, \ - .doneIfs = 1, \ - .reqMode = ldmaCtrlReqModeBlock, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = ldmaCtrlSrcIncOne, \ - .size = ldmaCtrlSizeByte, \ - .dstInc = ldmaCtrlDstIncNone, \ - .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ - .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ - .srcAddr = (uint32_t)(src), \ - .dstAddr = (uint32_t)(dest), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ - .dstIlEn = 0, \ - .IlMode = 0, \ - .bufferable = 0, \ - .IlSrc = 0 \ - } -#endif - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * @param[in] value Immediate value to write. - * @param[in] address Write address. - */ -#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 1, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] value Immediate value to write. - * @param[in] address Write address. - */ -#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for Immediate WRITE transfer - * @param[in] value Immediate value to write. - * @param[in] address Write address. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ - { \ - .wri = \ - { \ - .structType = ldmaCtrlStructTypeWrite, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .immVal = (value), \ - .dstAddr = (uint32_t)(address), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - */ -#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 1, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = 0, \ - .link = 0, \ - .linkAddr = 0 \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * - * Link address must be an absolute address. - * @note - * The linkAddr member of the transfer descriptor is not initialized. - * linkAddr must be initialized by using the proper bits right-shift - * to get the correct bits from the absolute address. - * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: - * @code - desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode - * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR - * if linkAddr is read. - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - */ -#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = ldmaLinkModeAbs, \ - .link = 1, \ - .linkAddr = 0 /* Must be set runtime ! */ \ - } \ - } - -/** - * @brief - * DMA descriptor initializer for SYNC transfer - * @param[in] set Sync pattern bits to set. - * @param[in] clr Sync pattern bits to clear. - * @param[in] matchValue Sync pattern to match. - * @param[in] matchEnable Sync pattern bits to enable for match. - * @param[in] linkjmp Address of descriptor to link to, expressed as a - * signed number of descriptors from "here". - * 1=one descriptor forward in memory, - * 0=this descriptor, - * -1=one descriptor back in memory. - */ -#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ - { \ - .sync = \ - { \ - .structType = ldmaCtrlStructTypeSync, \ - .structReq = 1, \ - .xferCnt = 0, \ - .byteSwap = 0, \ - .blockSize = 0, \ - .doneIfs = 0, \ - .reqMode = 0, \ - .decLoopCnt = 0, \ - .ignoreSrec = 0, \ - .srcInc = 0, \ - .size = 0, \ - .dstInc = 0, \ - .srcAddrMode = 0, \ - .dstAddrMode = 0, \ - .syncSet = (set), \ - .syncClr = (clr), \ - .matchVal = (matchValue), \ - .matchEn = (matchEnable), \ - .linkMode = ldmaLinkModeRel, \ - .link = 1, \ - .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ - } \ - } - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/** - * @brief - * Initializer for the destination interleaving portion of the DMA extended descriptor. - * @param[in] desc Transfer-type descriptor. - * @param[in] ilmode Rules table addressing mode for interleaved data. - * @param[in] ilsrc Base address for rules table in memory. - */ -#define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \ - { \ - (desc).dstIlEn = true; \ - (desc).IlMode = (ilmode); \ - (desc).IlSrc = (uint32_t)(ilsrc); \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void LDMA_DeInit(void); -void LDMA_EnableChannelRequest(int ch, bool enable); -void LDMA_Init(const LDMA_Init_t *init); -void LDMA_StartTransfer(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_Descriptor_t *descriptor); -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -void LDMA_StartTransferExtend(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_DescriptorExtend_t *descriptor_ext); -#endif -void LDMA_StopTransfer(int ch); -bool LDMA_TransferDone(int ch); -uint32_t LDMA_TransferRemainingCount(int ch); - -#if defined(_LDMA_SWRST_MASK) -/***************************************************************************//** - * @brief - * Reset the LDMA. - ******************************************************************************/ -__STATIC_INLINE void LDMA_Reset(void) -{ - LDMA->SWRST_SET = LDMA_SWRST_SWRST; - - /* Wait for reset to complete. */ - while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) { - } -} -#endif - -/***************************************************************************//** - * @brief - * Check if a certain channel is enabled. - * - * @param[in] ch - * LDMA channel to check. - * - * @return - * return true if the LDMA channel is enabled and false if the channel is not - * enabled. - ******************************************************************************/ -__STATIC_INLINE bool LDMA_ChannelEnabled(int ch) -{ - if ((ch < 0) || (ch > 31)) { - return false; - } -#if defined(_LDMA_CHSTATUS_MASK) - return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch))); -#else - // We've already confirmed ch is between 0 and 31, - // so it's now safe to cast it to uint8_t - return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch))); -#endif -} - -/***************************************************************************//** - * @brief - * Clear one or more pending LDMA interrupts. - * - * @param[in] flags - * Pending LDMA interrupt sources to clear. Use one or more valid - * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntClear(uint32_t flags) -{ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = flags; -#else - LDMA->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more LDMA interrupts. - * - * @param[in] flags - * LDMA interrupt sources to disable. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntDisable(uint32_t flags) -{ - LDMA->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more LDMA interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * LDMA_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * LDMA interrupt sources to enable. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR - * and one done flag for each channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntEnable(uint32_t flags) -{ - LDMA->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending LDMA interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @return - * LDMA interrupt sources pending. Returns one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and - * one flag for each LDMA channel. - ******************************************************************************/ -__STATIC_INLINE uint32_t LDMA_IntGet(void) -{ - return LDMA->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending LDMA interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled LDMA interrupt sources - * Return value is the bitwise AND of - * - the enabled interrupt sources in LDMA_IEN and - * - the pending interrupt flags LDMA_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) -{ - uint32_t ien; - - ien = LDMA->IEN; - return LDMA->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending LDMA interrupts - * - * @param[in] flags - * LDMA interrupt sources to set to pending. Use one or more valid - * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and - * one done flag for each LDMA channel. - ******************************************************************************/ -__STATIC_INLINE void LDMA_IntSet(uint32_t flags) -{ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_SET = flags; -#else - LDMA->IFS = flags; -#endif -} - -/** @} (end addtogroup ldma) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ -#endif /* EM_LDMA_H */ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LDMA_H +#define EM_LDMA_H + +#include "em_device.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup ldma LDMA - Linked DMA + * @brief Linked Direct Memory Access (LDMA) Peripheral API + * + * @details + * LDMA API functions provide full support for the LDMA peripheral. + * + * LDMA supports these DMA transfer types: + * + * @li Memory to memory. + * @li Memory to peripheral. + * @li Peripheral to memory. + * @li Peripheral to peripheral. + * @li Constant value to memory. + * + * LDMA supports linked lists of DMA descriptors allowing: + * + * @li Circular and ping-pong buffer transfers. + * @li Scatter-gather transfers. + * @li Looped transfers. + * + * LDMA has some advanced features: + * + * @li Intra-channel synchronization (SYNC), allowing hardware events to + * pause and restart a DMA sequence. + * @li Immediate-write (WRI), allowing DMA to write a constant anywhere + * in the memory map. + * @li Complex flow control allowing if-else constructs. + * + * Basic understanding of LDMA controller is assumed. Please refer to + * the reference manual for further details. The LDMA examples described + * in the reference manual are particularly helpful in understanding LDMA + * operations. + * + * In order to use the DMA controller, the initialization function @ref + * LDMA_Init() must have been executed once (normally during system initialization). + * + * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(), + * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t + * and @ref LDMA_Descriptor_t structure parameters. + * The LDMA_Descriptor_t structure parameter may be a + * pointer to an array of descriptors, descriptors in array should + * be linked together as needed. + * + * Transfer and descriptor initialization macros are provided for the most common + * transfer types. Due to the flexibility of LDMA peripheral, only a small + * subset of all possible initializer macros are provided, users should create + * new ones when needed. + * + * Examples of LDMA usage: + * + * A simple memory to memory transfer: + * + * @include em_ldma_single.c + * + * @n A linked list of three memory to memory transfers: + * + * @include em_ldma_link_memory.c + * + * @n DMA from serial port peripheral to memory: + * + * @include em_ldma_peripheral.c + * + * @n Ping-pong DMA from serial port peripheral to memory: + * + * @include em_ldma_pingpong.c + * + * @note LDMA module does not implement LDMA interrupt handler. A + * template for an LDMA IRQ handler is included here as an example. + * + * @include em_ldma_irq.c + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** + * Controls the number of unit data transfers per arbitration + * cycle, providing a means to balance DMA channels' load on the controller. + */ +typedef enum { + ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */ + ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */ + ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */ + ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */ + ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */ + ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */ + ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */ + ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */ + ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */ +} LDMA_CtrlBlockSize_t; + +/** DMA structure type. */ +typedef enum { + ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */ + ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */ + ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */ +} LDMA_CtrlStructType_t; + +/** DMA transfer block or cycle selector. */ +typedef enum { + ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */ + ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */ +} LDMA_CtrlReqMode_t; + +/** Source address increment unit size. */ +typedef enum { + ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */ + ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */ + ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */ + ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */ +} LDMA_CtrlSrcInc_t; + +/** DMA transfer unit size. */ +typedef enum { + ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */ + ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */ + ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */ +} LDMA_CtrlSize_t; + +/** Destination address increment unit size. */ +typedef enum { + ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */ + ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */ + ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */ + ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */ +} LDMA_CtrlDstInc_t; + +/** Source addressing mode. */ +typedef enum { + ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlSrcAddrMode_t; + +/** Destination addressing mode. */ +typedef enum { + ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */ + ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */ +} LDMA_CtrlDstAddrMode_t; + +/** DMA link load address mode. */ +typedef enum { + ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */ + ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */ +} LDMA_LinkMode_t; + +/** Insert extra arbitration slots to increase channel arbitration priority. */ +typedef enum { + ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */ + ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */ + ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */ + ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */ +} LDMA_CfgArbSlots_t; + +/** Source address increment sign. */ +typedef enum { + ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */ + ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */ +} LDMA_CfgSrcIncSign_t; + +/** Destination address increment sign. */ +typedef enum { + ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */ + ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */ +} LDMA_CfgDstIncSign_t; + +#if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK) +/** Structure fetch operation bus port. */ +typedef enum { + ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgStructBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +/** Source operation bus port. */ +typedef enum { + ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgSrcBusPort_t; +#endif + +#if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK) +/** Destination operation bus port. */ +typedef enum { + ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */ + ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */ +} LDMA_CfgDstBusPort_t; +#endif + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** Rules table mode (interleaving destination). */ +typedef enum { + ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */ + ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */ + ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */ +} LDMA_RulesTblMode_t; +#endif + +#if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0) +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 + ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 + ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 + ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 + ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF + ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 + ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 + ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 + ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF + ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV + ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT + ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL + ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT + ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY + ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV + ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL + ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY + ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV + ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT + ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL + ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT + ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY + ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV + ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL + ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV + ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL + ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI + ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF + ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 + ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 + ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 + ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 + ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 + ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF + ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF + ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG + ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN + ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE + ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA + ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 + ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 + ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 + ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF + ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 + ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 + ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 + ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF + ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 + ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 + ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 + ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF + ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 + ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 + ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 + ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF + ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 + ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 + ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 + ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF + ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD + ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD, + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 + ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 + ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 + ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF + ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ) + ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ) + ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ) + ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ) + ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL + ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL + ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL + ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL + ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL + ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL + ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL + ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL + ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL + ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL + ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL + ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL. + #endif + #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL + ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL. + #endif + #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO. + #endif +} LDMA_PeripheralSignal_t; + +#else +/** Peripherals that can trigger LDMA transfers. */ +typedef enum { + ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering. + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN) + ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE) + ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN) + ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE) + ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD) + ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR) + ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR) + ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD) + ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR) + ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD) + ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR) + ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR) + ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD) + ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR) + ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD) + ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR) + ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR) + ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD) + ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR) + ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN) + ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA) + ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY) + ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY) + ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL) + ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY) + ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC) + ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC) + ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV) + ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL) + ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV) + ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL) + ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV) + ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL) + ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV) + ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV) + ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL) + ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY) + ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV) + ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL) + ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY) + ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA) + ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV) + ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0) + ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1) + ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0) + ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1) + ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2) + ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF) + ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0) + ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1) + ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2) + ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3) + ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF) + ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0) + ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1) + ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2) + ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF) + ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0) + ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1) + ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2) + ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF) + ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0) + ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1) + ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2) + ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF) + ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0) + ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1) + ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2) + ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF) + ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0) + ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1) + ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2) + ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF) + ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV) + ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL) + ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY) + ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV) + ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL) + ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY) + ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV) + ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL) + ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY) + ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV) + ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT) + ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL) + ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT) + ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY) + ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV) + ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL) + ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY) + ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV) + ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT) + ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL) + ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT) + ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY) + ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV) + ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT) + ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL) + ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT) + ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY) + ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV) + ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL) + ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY) + ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0) + ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1) + ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0) + ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1) + ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2) + ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF) + ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0) + ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1) + ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2) + ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3) + ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF) + ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0) + ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1) + ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2) + ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF) + ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0) + ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1) + ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2) + ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2. + #endif + #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF) + ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF. + #endif +} LDMA_PeripheralSignal_t; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** + * @brief + * DMA descriptor. + * @details + * The LDMA DMA controller supports three different DMA descriptors. Each + * consists of four WORDs which map directly onto HW control registers for a + * given DMA channel. The three descriptor types are XFER, SYNC and WRI. + * Refer to the reference manual for further information. + */ +typedef union { + /** + * TRANSFER DMA descriptor, this is the only descriptor type which can be + * used to start a DMA transfer. + */ + struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } xfer; + + /** SYNCHRONIZE DMA descriptor, used for intra channel transfer + * synchronization. + */ + struct { + uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */ + uint32_t reserved1 : 16; /**< Reserved. */ + uint32_t matchVal : 8; /**< Sync trigger match value. */ + uint32_t matchEn : 8; /**< Sync trigger match enable. */ + uint32_t reserved2 : 16; /**< Reserved. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } sync; + + /** WRITE DMA descriptor, used for write immediate operations. */ + struct { + uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */ + uint32_t reserved0 : 1; /**< Reserved. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t immVal; /**< Data to be written at dstAddr. */ + uint32_t dstAddr; /**< DMA write destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + } wri; +} LDMA_Descriptor_t; + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA extended descriptor. + * @details + * The extended descriptor adds additional fields for the extended features + * available on the MMLDMA peripheral: destination interleaving and bufferable. + * The same three different DMA descriptors supported by the LDMA DMA controller + * are available. Each consists of seven WORDs (instead of four in non-extended + * descriptors) which map directly onto HW control registers for a given DMA + * channel. The three descriptor types are XFER, SYNC and WRI. But the + * extended fields are true only for XFER. The extended fields are the following: + * + * +- +- CTRL + * | Original | SRC + * | Structure | DST + * Extended | +- LINK + * Structure | XCTRL + * | Reserved for future usage + * +- ILSRC + * + * Refer to the reference manual for further information. + */ +typedef struct { + uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */ + uint32_t extend : 1; /**< Extend data structure. */ + uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */ + uint32_t xferCnt : 11; /**< Transfer count minus one. */ + uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */ + uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */ + uint32_t doneIfs : 1; /**< Generate interrupt when done. */ + uint32_t reqMode : 1; /**< Block or cycle transfer selector. */ + uint32_t decLoopCnt : 1; /**< Enable looped transfers. */ + uint32_t ignoreSrec : 1; /**< Ignore single requests. */ + uint32_t srcInc : 2; /**< Source address increment unit size. */ + uint32_t size : 2; /**< DMA transfer unit size. */ + uint32_t dstInc : 2; /**< Destination address increment unit size. */ + uint32_t srcAddrMode : 1; /**< Source addressing mode. */ + uint32_t dstAddrMode : 1; /**< Destination addressing mode. */ + + uint32_t srcAddr; /**< DMA source address. */ + uint32_t dstAddr; /**< DMA destination address. */ + + uint32_t linkMode : 1; /**< Select absolute or relative link address. */ + uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */ + int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */ + + uint32_t reserved1 : 4; /**< Reserved */ + uint32_t dstIlEn : 1; /**< Destination interleave. */ + uint32_t IlMode : 2; /**< Interleave mode. */ + uint32_t bufferable : 1; /**< Allow AHB buffering. */ + uint32_t reserved2 : 24; /**< Reserved */ + + uint32_t reserved3; /**< Reserved */ + uint32_t IlSrc; /**< DMA rules table base address in memory. */ +} LDMA_DescriptorExtend_t; +#endif + +/** @brief LDMA initialization configuration structure. */ +typedef struct { + uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */ + uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */ + uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */ + uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */ +} LDMA_Init_t; + +/** + * @brief + * DMA transfer configuration structure. + * @details + * This structure configures all aspects of a DMA transfer. + */ +typedef struct { + uint32_t ldmaReqSel; /**< Selects DMA trigger source. */ + uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */ + uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */ + uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */ + uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */ + bool ldmaReqDis; /**< Mask the PRS trigger input. */ + bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */ + LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */ + LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */ + LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */ + uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */ + LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */ + LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */ +#endif +} LDMA_TransferCfg_t; + +/******************************************************************************* + ******************************** DEFINES ********************************** + ******************************************************************************/ + +/** @brief Size in words of a non-extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4 + +/** @brief Size in words of an extended DMA descriptor. */ +#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7 + +/** @brief Maximum transfer size possible per descriptor. */ +#define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1)) + +/** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */ +#define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT) + +/** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */ +#define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT) + +/******************************************************************************* + ************************** STRUCT INITIALIZERS **************************** + ******************************************************************************/ + +/** @brief Default DMA initialization structure. */ +#define LDMA_INIT_DEFAULT \ + { \ + .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \ + .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \ + .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \ + .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \ + } + +/** + * @brief + * Generic DMA transfer configuration for memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY() \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to memory transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \ + { \ + 0, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \ + loopCnt \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \ + } +#endif + +/** + * @brief + * Generic DMA transfer configuration for looped memory to/from peripheral transfers. + */ +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \ + ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \ + } +#else +#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \ + { \ + signal, 0, 0, 0, 0, \ + false, false, ldmaCfgArbSlotsAs1, \ + ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory half-word transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for single memory to memory byte transfer + * using the extended descriptor fields. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0, /* Must be set runtime ! */ \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory half-word transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of half-words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeHalf, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for linked memory to memory byte transfer + * using the extended descriptor fields. + * + * Link address is a relative address. + * @note + * The linkAddr member of the transfer descriptor is initialized to 4 + * (regular descriptor) or 7 (extended descriptor), assuming that + * the next descriptor immediately follows this descriptor (in memory). + * @param[in] src Source data address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 1, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 0, \ + .reqMode = ldmaCtrlReqModeAll, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to a peripheral. + * @param[in] src Peripheral data source register address. + * @param[in] dest Peripheral data destination register address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + */ +#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncOne, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for word transfers from a peripheral to memory + * using the extended descriptor fields. + * @param[in] src Peripheral data source register address. + * @param[in] dest Destination data address. + * @param[in] count Number of words to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncNone, \ + .size = ldmaCtrlSizeWord, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \ + { \ + .xfer = \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * DMA descriptor initializer for byte transfers from memory to a peripheral + * using the extended descriptor fields. + * @note + * For the extended descriptor, if IlMode uses the absolute addressing, the + * rules are used directly as the destination addresses of the corresponding + * data. Thus the argument 'dest' will be ignored by the DMA engine. + * @param[in] src Source data address. + * @param[in] dest Peripheral data register destination address. + * @param[in] count Number of bytes to transfer. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \ + { \ + .structType = ldmaCtrlStructTypeXfer, \ + .extend = 1, \ + .structReq = 0, \ + .xferCnt = (count) - 1, \ + .byteSwap = 0, \ + .blockSize = ldmaCtrlBlockSizeUnit1, \ + .doneIfs = 1, \ + .reqMode = ldmaCtrlReqModeBlock, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = ldmaCtrlSrcIncOne, \ + .size = ldmaCtrlSizeByte, \ + .dstInc = ldmaCtrlDstIncNone, \ + .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \ + .dstAddrMode = ldmaCtrlDstAddrModeAbs, \ + .srcAddr = (uint32_t)(src), \ + .dstAddr = (uint32_t)(dest), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \ + .dstIlEn = 0, \ + .IlMode = 0, \ + .bufferable = 0, \ + .IlSrc = 0 \ + } +#endif + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] value Immediate value to write. + * @param[in] address Write address. + */ +#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for Immediate WRITE transfer + * @param[in] value Immediate value to write. + * @param[in] address Write address. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \ + { \ + .wri = \ + { \ + .structType = ldmaCtrlStructTypeWrite, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .immVal = (value), \ + .dstAddr = (uint32_t)(address), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 1, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = 0, \ + .link = 0, \ + .linkAddr = 0 \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * + * Link address must be an absolute address. + * @note + * The linkAddr member of the transfer descriptor is not initialized. + * linkAddr must be initialized by using the proper bits right-shift + * to get the correct bits from the absolute address. + * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation: + * @code + desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode + * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR + * if linkAddr is read. + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + */ +#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeAbs, \ + .link = 1, \ + .linkAddr = 0 /* Must be set runtime ! */ \ + } \ + } + +/** + * @brief + * DMA descriptor initializer for SYNC transfer + * @param[in] set Sync pattern bits to set. + * @param[in] clr Sync pattern bits to clear. + * @param[in] matchValue Sync pattern to match. + * @param[in] matchEnable Sync pattern bits to enable for match. + * @param[in] linkjmp Address of descriptor to link to, expressed as a + * signed number of descriptors from "here". + * 1=one descriptor forward in memory, + * 0=this descriptor, + * -1=one descriptor back in memory. + */ +#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \ + { \ + .sync = \ + { \ + .structType = ldmaCtrlStructTypeSync, \ + .structReq = 1, \ + .xferCnt = 0, \ + .byteSwap = 0, \ + .blockSize = 0, \ + .doneIfs = 0, \ + .reqMode = 0, \ + .decLoopCnt = 0, \ + .ignoreSrec = 0, \ + .srcInc = 0, \ + .size = 0, \ + .dstInc = 0, \ + .srcAddrMode = 0, \ + .dstAddrMode = 0, \ + .syncSet = (set), \ + .syncClr = (clr), \ + .matchVal = (matchValue), \ + .matchEn = (matchEnable), \ + .linkMode = ldmaLinkModeRel, \ + .link = 1, \ + .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \ + } \ + } + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/** + * @brief + * Initializer for the destination interleaving portion of the DMA extended descriptor. + * @param[in] desc Transfer-type descriptor. + * @param[in] ilmode Rules table addressing mode for interleaved data. + * @param[in] ilsrc Base address for rules table in memory. + */ +#define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \ + { \ + (desc).dstIlEn = true; \ + (desc).IlMode = (ilmode); \ + (desc).IlSrc = (uint32_t)(ilsrc); \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void LDMA_DeInit(void); +void LDMA_EnableChannelRequest(int ch, bool enable); +void LDMA_Init(const LDMA_Init_t *init); +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor); +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext); +#endif +void LDMA_StopTransfer(int ch); +bool LDMA_TransferDone(int ch); +uint32_t LDMA_TransferRemainingCount(int ch); + +#if defined(_LDMA_SWRST_MASK) +/***************************************************************************//** + * @brief + * Reset the LDMA. + ******************************************************************************/ +__STATIC_INLINE void LDMA_Reset(void) +{ + LDMA->SWRST_SET = LDMA_SWRST_SWRST; + + /* Wait for reset to complete. */ + while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) { + } +} +#endif + +/***************************************************************************//** + * @brief + * Check if a certain channel is enabled. + * + * @param[in] ch + * LDMA channel to check. + * + * @return + * return true if the LDMA channel is enabled and false if the channel is not + * enabled. + ******************************************************************************/ +__STATIC_INLINE bool LDMA_ChannelEnabled(int ch) +{ + if ((ch < 0) || (ch > 31)) { + return false; + } +#if defined(_LDMA_CHSTATUS_MASK) + return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch))); +#else + // We've already confirmed ch is between 0 and 31, + // so it's now safe to cast it to uint8_t + return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch))); +#endif +} + +/***************************************************************************//** + * @brief + * Clear one or more pending LDMA interrupts. + * + * @param[in] flags + * Pending LDMA interrupt sources to clear. Use one or more valid + * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntClear(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = flags; +#else + LDMA->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LDMA interrupts. + * + * @param[in] flags + * LDMA interrupt sources to disable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntDisable(uint32_t flags) +{ + LDMA->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LDMA interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LDMA_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * LDMA interrupt sources to enable. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR + * and one done flag for each channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntEnable(uint32_t flags) +{ + LDMA->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LDMA interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @return + * LDMA interrupt sources pending. Returns one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and + * one flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGet(void) +{ + return LDMA->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LDMA interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled LDMA interrupt sources + * Return value is the bitwise AND of + * - the enabled interrupt sources in LDMA_IEN and + * - the pending interrupt flags LDMA_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t LDMA_IntGetEnabled(void) +{ + uint32_t ien; + + ien = LDMA->IEN; + return LDMA->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LDMA interrupts + * + * @param[in] flags + * LDMA interrupt sources to set to pending. Use one or more valid + * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and + * one done flag for each LDMA channel. + ******************************************************************************/ +__STATIC_INLINE void LDMA_IntSet(uint32_t flags) +{ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_SET = flags; +#else + LDMA->IFS = flags; +#endif +} + +/** @} (end addtogroup ldma) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ +#endif /* EM_LDMA_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h index 5bbb638..43baefa 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_letimer.h @@ -1,334 +1,334 @@ -/***************************************************************************//** - * @file - * @brief Low Energy Timer (LETIMER) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_LETIMER_H -#define EM_LETIMER_H - -#include -#include "em_device.h" -#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup letimer - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Repeat mode. */ -typedef enum { - /** Count until stopped by SW. */ - letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, - /** Count REP0 times. */ - letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, - /** - * Count REP0 times, if REP1 has been written to, it is loaded into - * REP0 when REP0 is about to be decremented to 0. - */ - letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, - /** - * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 - * are decremented when counter underflows. - */ - letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE -} LETIMER_RepeatMode_TypeDef; - -/** Underflow action on output. */ -typedef enum { - /** No output action. */ - letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, - /** Toggle output when counter underflows. */ - letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, - /** Hold output one LETIMER clock cycle when counter underflows. */ - letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, - /** Set output idle when counter underflows, and active when matching COMP1. */ - letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM -} LETIMER_UFOA_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** LETIMER initialization structure. */ -typedef struct { - bool enable; /**< Start counting when initialization completes. */ - bool debugRun; /**< Counter shall keep running during debug halt. */ -#if defined(LETIMER_CTRL_RTCC0TEN) - bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ - bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ -#endif - bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ - bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ - uint8_t out0Pol; /**< Idle value for output 0. */ - uint8_t out1Pol; /**< Idle value for output 1. */ - LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ - LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ - LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ - uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ -} LETIMER_Init_TypeDef; - -/** Default configuration for LETIMER initialization structure. */ -#if defined(LETIMER_CTRL_RTCC0TEN) -#define LETIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - false, /* Do not start counting on RTC COMP0 match. */ \ - false, /* Do not start counting on RTC COMP1 match. */ \ - false, /* Do not load COMP0 into CNT on underflow. */ \ - false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ - 0, /* Idle value 0 for output 0. */ \ - 0, /* Idle value 0 for output 1. */ \ - letimerUFOANone, /* No action on underflow on output 0. */ \ - letimerUFOANone, /* No action on underflow on output 1. */ \ - letimerRepeatFree, /* Count until stopped by SW. */ \ - 0 /* Use default top Value. */ \ - } -#else -#define LETIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - false, /* Do not load COMP0 into CNT on underflow. */ \ - false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ - 0, /* Idle value 0 for output 0. */ \ - 0, /* Idle value 0 for output 1. */ \ - letimerUFOANone, /* No action on underflow on output 0. */ \ - letimerUFOANone, /* No action on underflow on output 1. */ \ - letimerRepeatFree, /* Count until stopped by SW. */ \ - 0 /* Use default top Value. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); -void LETIMER_CompareSet(LETIMER_TypeDef *letimer, - unsigned int comp, - uint32_t value); -uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer); -#if !defined(_EFM32_GECKO_FAMILY) -void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value); -#endif - -void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); -#if defined(_LETIMER_FREEZE_MASK) -void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); -#endif -void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending LETIMER interrupts. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * Pending LETIMER interrupt source to clear. Use a bitwise logic OR - * combination of valid interrupt flags for the LETIMER module - * (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) -{ -#if defined (LETIMER_HAS_SET_CLEAR) - letimer->IF_CLR = flags; -#else - letimer->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more LETIMER interrupts. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) -{ - letimer->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more LETIMER interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * LETIMER_IntClear() prior to enabling the interrupt. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) -{ - letimer->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending LETIMER interrupt flags. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @return - * LETIMER interrupt sources pending. A bitwise logic OR combination of - * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) -{ - return letimer->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending LETIMER interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Event bits are not cleared by the use of this function. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @return - * Pending and enabled LETIMER interrupt sources. - * Return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn - * register (LETIMER_IEN_nnn) and - * - the OR combination of valid interrupt flags of the LETIMER module - * (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) -{ - uint32_t ien; - - /* Store flags in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = letimer->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return letimer->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending LETIMER interrupts from SW. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @param[in] flags - * LETIMER interrupt sources to set to pending. Use a bitwise logic OR - * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) -{ -#if defined (LETIMER_HAS_SET_CLEAR) - letimer->IF_SET = flags; -#else - letimer->IFS = flags; -#endif -} - -#if defined(_LETIMER_LOCK_MASK) -/***************************************************************************//** - * @brief - * Lock LETIMER registers. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - * - * @note When LETIMER registers are locked LETIMER_EN, LETIMER_SWRST, - * LETIMER_CTRL, LETIMER_CMD, LETIMER_CNT, LETIMER_COMPx, - * LETIMER_TOP, LETIMER_TOPBUFF, LETIMER_REPx, and PRSMODE registers - * cannot be written to. - ******************************************************************************/ -__STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer) -{ - letimer->LOCK = ~LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; -} -#endif - -#if defined(_LETIMER_LOCK_MASK) -/***************************************************************************//** - * @brief - * Unlock LETIMER registers. - * - * @param[in] letimer - * Pointer to LETIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void LETIMER_Unlock(LETIMER_TypeDef *letimer) -{ - letimer->LOCK = LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; -} -#endif - -uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); -void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, - unsigned int rep, - uint32_t value); -void LETIMER_Reset(LETIMER_TypeDef *letimer); -void LETIMER_SyncWait(LETIMER_TypeDef *letimer); -void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); -uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer); - -/** @} (end addtogroup letimer) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ -#endif /* EM_LETIMER_H */ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_LETIMER_H +#define EM_LETIMER_H + +#include +#include "em_device.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup letimer + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Repeat mode. */ +typedef enum { + /** Count until stopped by SW. */ + letimerRepeatFree = _LETIMER_CTRL_REPMODE_FREE, + /** Count REP0 times. */ + letimerRepeatOneshot = _LETIMER_CTRL_REPMODE_ONESHOT, + /** + * Count REP0 times, if REP1 has been written to, it is loaded into + * REP0 when REP0 is about to be decremented to 0. + */ + letimerRepeatBuffered = _LETIMER_CTRL_REPMODE_BUFFERED, + /** + * Run as long as both REP0 and REP1 are not 0. Both REP0 and REP1 + * are decremented when counter underflows. + */ + letimerRepeatDouble = _LETIMER_CTRL_REPMODE_DOUBLE +} LETIMER_RepeatMode_TypeDef; + +/** Underflow action on output. */ +typedef enum { + /** No output action. */ + letimerUFOANone = _LETIMER_CTRL_UFOA0_NONE, + /** Toggle output when counter underflows. */ + letimerUFOAToggle = _LETIMER_CTRL_UFOA0_TOGGLE, + /** Hold output one LETIMER clock cycle when counter underflows. */ + letimerUFOAPulse = _LETIMER_CTRL_UFOA0_PULSE, + /** Set output idle when counter underflows, and active when matching COMP1. */ + letimerUFOAPwm = _LETIMER_CTRL_UFOA0_PWM +} LETIMER_UFOA_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** LETIMER initialization structure. */ +typedef struct { + bool enable; /**< Start counting when initialization completes. */ + bool debugRun; /**< Counter shall keep running during debug halt. */ +#if defined(LETIMER_CTRL_RTCC0TEN) + bool rtcComp0Enable; /**< Start counting on RTC COMP0 match. */ + bool rtcComp1Enable; /**< Start counting on RTC COMP1 match. */ +#endif + bool comp0Top; /**< Load COMP0 register into CNT when counter underflows. */ + bool bufTop; /**< Load COMP1 into COMP0 when REP0 reaches 0. */ + uint8_t out0Pol; /**< Idle value for output 0. */ + uint8_t out1Pol; /**< Idle value for output 1. */ + LETIMER_UFOA_TypeDef ufoa0; /**< Underflow output 0 action. */ + LETIMER_UFOA_TypeDef ufoa1; /**< Underflow output 1 action. */ + LETIMER_RepeatMode_TypeDef repMode; /**< Repeat mode. */ + uint32_t topValue; /**< Top value. Counter wraps when top value matches counter value is reached. */ +} LETIMER_Init_TypeDef; + +/** Default configuration for LETIMER initialization structure. */ +#if defined(LETIMER_CTRL_RTCC0TEN) +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not start counting on RTC COMP0 match. */ \ + false, /* Do not start counting on RTC COMP1 match. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#else +#define LETIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + false, /* Do not load COMP0 into CNT on underflow. */ \ + false, /* Do not load COMP1 into COMP0 when REP0 reaches 0. */ \ + 0, /* Idle value 0 for output 0. */ \ + 0, /* Idle value 0 for output 1. */ \ + letimerUFOANone, /* No action on underflow on output 0. */ \ + letimerUFOANone, /* No action on underflow on output 1. */ \ + letimerRepeatFree, /* Count until stopped by SW. */ \ + 0 /* Use default top Value. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp); +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value); +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer); +#if !defined(_EFM32_GECKO_FAMILY) +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value); +#endif + +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable); +#if defined(_LETIMER_FREEZE_MASK) +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable); +#endif +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * Pending LETIMER interrupt source to clear. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntClear(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_CLR = flags; +#else + letimer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more LETIMER interrupts. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntDisable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more LETIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * LETIMER_IntClear() prior to enabling the interrupt. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntEnable(LETIMER_TypeDef *letimer, uint32_t flags) +{ + letimer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending LETIMER interrupt flags. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * LETIMER interrupt sources pending. A bitwise logic OR combination of + * valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGet(LETIMER_TypeDef *letimer) +{ + return letimer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending LETIMER interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Event bits are not cleared by the use of this function. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @return + * Pending and enabled LETIMER interrupt sources. + * Return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in LETIMER_IEN_nnn + * register (LETIMER_IEN_nnn) and + * - the OR combination of valid interrupt flags of the LETIMER module + * (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t LETIMER_IntGetEnabled(LETIMER_TypeDef *letimer) +{ + uint32_t ien; + + /* Store flags in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = letimer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return letimer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending LETIMER interrupts from SW. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @param[in] flags + * LETIMER interrupt sources to set to pending. Use a bitwise logic OR + * combination of valid interrupt flags for the LETIMER module (LETIMER_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void LETIMER_IntSet(LETIMER_TypeDef *letimer, uint32_t flags) +{ +#if defined (LETIMER_HAS_SET_CLEAR) + letimer->IF_SET = flags; +#else + letimer->IFS = flags; +#endif +} + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Lock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + * + * @note When LETIMER registers are locked LETIMER_EN, LETIMER_SWRST, + * LETIMER_CTRL, LETIMER_CMD, LETIMER_CNT, LETIMER_COMPx, + * LETIMER_TOP, LETIMER_TOPBUFF, LETIMER_REPx, and PRSMODE registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Lock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = ~LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +#if defined(_LETIMER_LOCK_MASK) +/***************************************************************************//** + * @brief + * Unlock LETIMER registers. + * + * @param[in] letimer + * Pointer to LETIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void LETIMER_Unlock(LETIMER_TypeDef *letimer) +{ + letimer->LOCK = LETIMER_LOCK_LETIMERLOCKKEY_UNLOCK; +} +#endif + +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep); +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value); +void LETIMER_Reset(LETIMER_TypeDef *letimer); +void LETIMER_SyncWait(LETIMER_TypeDef *letimer); +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value); +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer); + +/** @} (end addtogroup letimer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ +#endif /* EM_LETIMER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h index d7fe030..2ced370 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc.h @@ -1,882 +1,882 @@ -/***************************************************************************//** - * @file - * @brief Flash Controller (MSC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_MSC_H -#define EM_MSC_H - -#include "em_device.h" -#if defined(MSC_COUNT) && (MSC_COUNT > 0) - -#include -#include -#include "em_bus.h" -#include "em_msc_compat.h" -#include "em_ramfunc.h" -#include "sl_assert.h" - -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - #include "sli_tz_ns_interface.h" - #include "sli_tz_service_msc.h" - #include "sli_tz_s_interface.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup msc MSC - Memory System Controller - * @brief Memory System Controller API - * @details - * Contains functions to control the MSC, primarily the Flash. - * Users can perform Flash memory write and erase operations, as well as - * optimization of the CPU instruction fetch interface for the application. - * Available instruction fetch features depends on the MCU or SoC family, but - * features such as instruction pre-fetch, cache, and configurable branch prediction - * are typically available. - * - * @note Flash wait-state configuration is handled by @ref cmu. - * When core clock configuration is changed by a call to functions such as - * CMU_ClockSelectSet() or CMU_HFRCOBandSet(), then Flash wait-state - * configuration is also updated. - * - * MSC resets into a safe state. To initialize the instruction interface - * to recommended settings: - * @include em_msc_init_exec.c - * - * @note The optimal configuration is highly application dependent. Performance - * benchmarking is supported by most families. See MSC_StartCacheMeasurement() - * and MSC_GetCacheMeasurement() for more details. - * - * @note - * The flash write and erase runs from RAM on the EFM32G devices. On all other - * devices the flash write and erase functions run from flash. - * - * @note - * Flash erase may add ms of delay to interrupt latency if executing from Flash. - * - * Flash write and erase operations are supported by @ref MSC_WriteWord(), - * @ref MSC_ErasePage(), and MSC_MassErase(). - * Mass erase is supported for MCU and SoC families with larger Flash sizes. - * - * @note - * @ref MSC_Init() must be called prior to any Flash write or erase operation. - * - * The following steps are necessary to perform a page erase and write: - * @include em_msc_erase_write.c - * - * @deprecated - * The configuration called EM_MSC_RUN_FROM_FLASH is deprecated. This was - * previously used for allocating the flash write functions in either flash - * or RAM. - * - * @note - * The configuration EM_MSC_RUN_FROM_RAM is used to allocate the flash - * write functions in RAM. By default, flash write - * functions are placed in RAM on EFM32G and Series 2 devices - * unless SL_RAMFUNC_DISABLE is defined. For other devices, - * flash write functions are placed in FLASH by default unless - * EM_MSC_RUN_FROM_RAM is defined and SL_RAMFUNC_DISABLE is not defined. - * - * @deprecated - * The function called MSC_WriteWordFast() is deprecated. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************* DEFINES ***************************************** - ******************************************************************************/ - -/** - * @brief - * Timeout used while waiting for Flash to become ready after a write. - * This number indicates the number of iterations to perform before - * issuing a timeout. - * - * @note - * Timeout is set very large (in the order of 100x longer than - * necessary). This is to avoid any corner case. - */ -#define MSC_PROGRAM_TIMEOUT 10000000UL - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if (defined(_EFM32_GECKO_FAMILY) \ - || defined(_SILICON_LABS_32B_SERIES_2) \ - || defined(EM_MSC_RUN_FROM_RAM)) \ - && !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) -#define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR -#define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN -#define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END -#else -#define MSC_RAMFUNC_DECLARATOR -#define MSC_RAMFUNC_DEFINITION_BEGIN -#define MSC_RAMFUNC_DEFINITION_END -#endif -/** @endcond */ - -/******************************************************************************* - ************************* TYPEDEFS **************************************** - ******************************************************************************/ - -/** Return codes for writing/erasing Flash. */ -typedef enum { - mscReturnOk = 0, /**< Flash write/erase successful. */ - mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ - mscReturnLocked = -2, /**< Flash address is locked. */ - mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ - mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ -} MSC_Status_TypeDef; - -#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) -/** Strategy for prioritized bus access. */ -typedef enum { - mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ - mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ - mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ - mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ -} MSC_BusStrategy_Typedef; -#endif - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -/** AHBHOST masters that can use alternate MPAHBRAM ports. */ -typedef enum { - mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, - mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, - mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, - mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, - mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) - mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK) - mscDmemMasterMVPAHBDATA1 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK) - mscDmemMasterMVPAHBDATA2 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_MASK) - mscDmemMasterLDMA1 = _SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_MASK) - mscDmemMasterSRWLDMA = _SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_MASK) - mscDmemMasterUSB = _SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_SHIFT, -#endif -#if defined(_SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_MASK) - mscDmemMasterBUFC = _SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_SHIFT -#endif -} MSC_DmemMaster_TypeDef; -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -/** AHB port given priority. */ -typedef enum { - mscPortPriorityNone = _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE, - mscPortPriorityPort0 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0, - mscPortPriorityPort1 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1, -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2) - mscPortPriorityPort2 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2, -#endif -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3) - mscPortPriorityPort3 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3, -#endif -} MSC_PortPriority_TypeDef; -#endif - -#if defined(MSC_READCTRL_DOUTBUFEN) || defined(MSC_RDATACTRL_DOUTBUFEN) -/** Code execution configuration */ -typedef struct { - bool doutBufEn; /**< Flash dout pipeline buffer enable */ -} MSC_ExecConfig_TypeDef; - -/** Default MSC ExecConfig initialization */ -#define MSC_EXECCONFIG_DEFAULT \ - { \ - false, \ - } - -#else -/** Code execution configuration. */ -typedef struct { - bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ - bool prefetchEn; /**< Enable MSC prefetching. */ - bool ifcDis; /**< Disable instruction cache. */ - bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ - bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ - bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ -} MSC_ExecConfig_TypeDef; - -/** Default MSC ExecConfig initialization. */ -#define MSC_EXECCONFIG_DEFAULT \ - { \ - false, \ - true, \ - false, \ - false, \ - false, \ - false, \ - } -#endif - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) - -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) -/** EFM32GG11B incorporates 2 memory banks including ECC support. */ -#define MSC_ECC_BANKS (2) - -/** Default MSC EccConfig initialization. */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -/** EFM32GG12B incorporates 3 memory banks including ECC support. */ -#define MSC_ECC_BANKS (3) - -/** Default MSC EccConfig initialization. */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - -/** xG26 chips incorporate 2 memory banks including ECC support. */ -#define MSC_ECC_BANKS (2) -/** Default MSC EccConfig initialization */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false, false }, \ - { 0, 1 }, \ - } - -#elif defined(_SILICON_LABS_32B_SERIES_2) - -/** Series 2 chips incorporate 1 memory bank including ECC support. */ -#define MSC_ECC_BANKS (1) -/** Default MSC EccConfig initialization */ -#define MSC_ECCCONFIG_DEFAULT \ - { \ - { false }, \ - { 0, 1 }, \ - } - -#else -#error Device not supported. -#endif - -/** ECC configuration. */ -typedef struct { - bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable - Error Correcting Code (ECC) for - each RAM bank that supports ECC on - the device. */ - uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to - use for ECC initialization. */ -} MSC_EccConfig_TypeDef; - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated type names. */ -#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef -#define msc_Return_TypeDef MSC_Status_TypeDef -/** @endcond */ - -/******************************************************************************* - ************************* Inline Functions ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the status of the MSC register lock. - * - * @return - * Boolean true if register lock is applied, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool MSC_LockGetLocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return (bool)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_LOCKED_SID); -#elif defined(_MSC_STATUS_REGLOCK_MASK) - return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; -#else - return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED; -#endif -} - -/***************************************************************************//** - * @brief - * Set the MSC register lock to a locked state. - ******************************************************************************/ -__STATIC_INLINE void MSC_LockSetLocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_SET_LOCKED_SID); -#else - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; -#endif -} - -/***************************************************************************//** - * @brief - * Set the MSC register lock to an unlocked state. - ******************************************************************************/ -__STATIC_INLINE void MSC_LockSetUnlocked(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_SET_UNLOCKED_SID); -#else - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; -#endif -} - -/***************************************************************************//** - * @brief - * Get the current value of the read control register (MSC_READCTRL). - * - * @return - * The 32-bit value read from the MSC_READCTRL register. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_READCTRL_SID); -#else - return MSC->READCTRL; -#endif -} - -/***************************************************************************//** - * @brief - * Write a value to the read control register (MSC_READCTRL). - * - * @param[in] value - * The 32-bit value to write to the MSC_READCTRL register. - ******************************************************************************/ -__STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_READCTRL_SID, - value); -#else - MSC->READCTRL = value; -#endif -} - -#if defined(_MSC_PAGELOCK0_MASK) || defined(_MSC_INST_PAGELOCKWORD0_MASK) - -/***************************************************************************//** - * @brief - * Set the lockbit for a flash page in order to prevent page writes/erases to - * the corresponding page. - * - * @param[in] page_number - * The index of the page to apply the pagelock to. Must be in the range - * [0, (flash_size / page_size) - 1]. - ******************************************************************************/ -__STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_PAGELOCK_SID, - page_number); -#else - EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); - - #if defined(_MSC_PAGELOCK0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; - #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; - #endif - - pagelock_registers[page_number / 32] |= (1 << (page_number % 32)); -#endif -} - -/***************************************************************************//** - * @brief - * Get the value of the lockbit for a flash page. - * - * @param[in] page_number - * The index of the page to get the lockbit value from. Must be in the range - * [0, (flash_size / page_size) - 1]. - * - * @return - * Boolean true if the page is locked, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return (bool)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_GET_PAGELOCK_SID, - page_number); -#else - EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); - - #if defined(_MSC_PAGELOCK0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; - #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) - uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; - #endif - - return pagelock_registers[page_number / 32] & (1 << (page_number % 32)); -#endif -} - -#endif // _MSC_PAGELOCK0_MASK || _MSC_INST_PAGELOCKWORD0_MASK - -#if defined(_MSC_USERDATASIZE_MASK) - -/***************************************************************************//** - * @brief - * Get the size of the user data region in flash. - * - * @return - * The size of the user data region divided by 256. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_UserDataGetSize(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_USERDATA_SIZE_SID); -#else - return MSC->USERDATASIZE; -#endif -} - -#endif // _MSC_USERDATASIZE_MASK - -#if defined(_MSC_MISCLOCKWORD_MASK) - -/***************************************************************************//** - * @brief - * Get the current value of the mass erase and user data page lock word - * (MSC_MISCLOCKWORD). - * - * @return - * The 32-bit value read from the MSC_MISCLOCKWORD register. - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - return sli_tz_ns_interface_dispatch_simple_noarg( - (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, - SLI_TZ_MSC_GET_MISCLOCKWORD_SID); -#else - return MSC->MISCLOCKWORD; -#endif -} - -/***************************************************************************//** - * @brief - * Write a value to the mass erase and user data page lock word - * (MSC_MISCLOCKWORD). - * - * @param[in] value - * The 32-bit value to write to the MSC_MISCLOCKWORD register. - ******************************************************************************/ -__STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value) -{ -#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - (void)sli_tz_ns_interface_dispatch_simple( - (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, - SLI_TZ_MSC_SET_MISCLOCKWORD_SID, - value); -#else - MSC->MISCLOCKWORD = value; -#endif -} - -#endif // _MSC_USERDATASIZE_MASK - -#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - -/***************************************************************************//** - * @brief - * Clear one or more pending MSC interrupts. - * - * @param[in] flags - * Pending MSC interrupt source to clear. Use a bitwise logic OR combination - * of valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntClear(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IF_CLR = flags; -#else - MSC->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more MSC interrupts. - * - * @param[in] flags - * MSC interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntDisable(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IEN_CLR = flags; -#else - MSC->IEN &= ~(flags); -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more MSC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * MSC_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * MSC interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntEnable(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IEN_SET = flags; -#else - MSC->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending MSC interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @return - * MSC interrupt sources pending. A bitwise logic OR combination of valid - * interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_IntGet(void) -{ - return MSC->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending MSC interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled MSC interrupt sources. - * The return value is the bitwise AND of - * - the enabled interrupt sources in MSC_IEN and - * - the pending interrupt flags MSC_IF - ******************************************************************************/ -__STATIC_INLINE uint32_t MSC_IntGetEnabled(void) -{ - uint32_t ien; - - ien = MSC->IEN; - return MSC->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending MSC interrupts from SW. - * - * @param[in] flags - * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of - * valid interrupt flags for the MSC module (MSC_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE void MSC_IntSet(uint32_t flags) -{ -#if defined(MSC_HAS_SET_CLEAR) - MSC->IF_SET = flags; -#else - MSC->IFS = flags; -#endif -} - -#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) -/***************************************************************************//** - * @brief - * Start measuring the cache hit ratio. - * @details - * Starts performance counters. It is defined inline to - * minimize the impact of this code on the measurement itself. - ******************************************************************************/ -__STATIC_INLINE void MSC_StartCacheMeasurement(void) -{ - /* Clear CMOF and CHOF to catch these later. */ - MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; - - /* Start performance counters. */ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_STARTPC; -#else - MSC->CMD = MSC_CMD_STARTPC; -#endif -} - -/***************************************************************************//** - * @brief - * Stop measuring the hit rate. - * @note - * Defined inline to minimize the impact of this - * code on the measurement itself. - * Only works for relatively short sections of code. - * To measure longer sections of code, implement an IRQ Handler for - * the CHOF and CMOF overflow interrupts. These overflows need to be - * counted and included in the total. - * Functions can then be implemented as follows: - * @verbatim - * volatile uint32_t hitOverflows - * volatile uint32_t missOverflows - * - * void MSC_IRQHandler(void) - * { - * uint32_t flags; - * flags = MSC->IF; - * if (flags & MSC_IF_CHOF) { - * MSC->IFC = MSC_IF_CHOF; - * hitOverflows++; - * } - * if (flags & MSC_IF_CMOF) { - * MSC->IFC = MSC_IF_CMOF; - * missOverflows++; - * } - * } - * - * void startPerformanceCounters(void) - * { - * hitOverflows = 0; - * missOverflows = 0; - * - * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); - * NVIC_EnableIRQ(MSC_IRQn); - * - * MSC_StartCacheMeasurement(); - * } - * @endverbatim - * @return - * Returns -1 if there has been no cache accesses. - * Returns -2 if there has been an overflow in the performance counters. - * If not, it will return the percentage of hits versus misses. - ******************************************************************************/ -__STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) -{ - int32_t total; - int32_t hits; - /* Stop counter before computing hit-rate. */ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_STOPPC; -#else - MSC->CMD = MSC_CMD_STOPPC; -#endif - - /* Check for overflows in performance counters. */ - if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { - return -2; - } - - hits = (int32_t)MSC->CACHEHITS; - total = (int32_t)MSC->CACHEMISSES + hits; - - /* To avoid a division by zero. */ - if (total == 0) { - return -1; - } - - return (hits * 100) / total; -} - -/***************************************************************************//** - * @brief - * Flush contents of instruction cache. - ******************************************************************************/ -__STATIC_INLINE void MSC_FlushCache(void) -{ -#if defined(_MSC_CACHECMD_MASK) - MSC->CACHECMD = MSC_CACHECMD_INVCACHE; -#else - MSC->CMD = MSC_CMD_INVCACHE; -#endif -} - -/***************************************************************************//** - * @brief - * Enable or disable instruction cache functionality. - * @param[in] enable - * Enable instruction cache. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableCache(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); -} - -#if defined(MSC_READCTRL_ICCDIS) -/***************************************************************************//** - * @brief - * Enable or disable instruction cache functionality in IRQs. - * @param[in] enable - * Enable instruction cache. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); -} -#endif - -/***************************************************************************//** - * @brief - * Enable or disable instruction cache flushing when writing to flash. - * @param[in] enable - * Enable automatic cache flushing. Default is on. - ******************************************************************************/ -__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) -{ - BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); -} -#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ - -#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) -/***************************************************************************//** - * @brief - * Configure which unit should get priority on system bus. - * @param[in] mode - * Unit to prioritize bus accesses for. - ******************************************************************************/ -__STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) -{ - MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; -} -#endif - -/******************************************************************************* - ************************* PROTOTYPES ************************************** - ******************************************************************************/ - -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); -#endif - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port); -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority); -MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void); -#endif - -#if !defined(_SILICON_LABS_32B_SERIES_2) -/* Note that this function is deprecated because we no longer support - * placing msc code in ram. */ -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, - void const *data, - uint32_t numBytes); -#endif - -#if defined(MSC_WRITECMD_ERASEMAIN0) -/***************************************************************************//** - * @brief - * Erase the entire Flash in one operation. - * - * @note - * This command will erase the entire contents of the device. - * Use with care, both a debug session and all contents of the flash will be - * lost. The lock bit, MLW will prevent this operation from executing and - * might prevent a successful mass erase. - * - * @return - * Returns the status of the operation. - ******************************************************************************/ -SL_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_MassErase(void); -#endif - -#endif /* !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT */ - -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); - -MSC_RAMFUNC_DECLARATOR -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes); - -#if (_SILICON_LABS_32B_SERIES > 0) -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes); -#endif - -void MSC_Init(void); -void MSC_Deinit(void); - -/** @} (end addtogroup msc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ -#endif /* EM_MSC_H */ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_H +#define EM_MSC_H + +#include "em_device.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include +#include +#include "em_bus.h" +#include "em_msc_compat.h" +#include "em_ramfunc.h" +#include "sl_assert.h" + +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + #include "sli_tz_ns_interface.h" + #include "sli_tz_service_msc.h" + #include "sli_tz_s_interface.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup msc MSC - Memory System Controller + * @brief Memory System Controller API + * @details + * Contains functions to control the MSC, primarily the Flash. + * Users can perform Flash memory write and erase operations, as well as + * optimization of the CPU instruction fetch interface for the application. + * Available instruction fetch features depends on the MCU or SoC family, but + * features such as instruction pre-fetch, cache, and configurable branch prediction + * are typically available. + * + * @note Flash wait-state configuration is handled by @ref cmu. + * When core clock configuration is changed by a call to functions such as + * CMU_ClockSelectSet() or CMU_HFRCOBandSet(), then Flash wait-state + * configuration is also updated. + * + * MSC resets into a safe state. To initialize the instruction interface + * to recommended settings: + * @include em_msc_init_exec.c + * + * @note The optimal configuration is highly application dependent. Performance + * benchmarking is supported by most families. See MSC_StartCacheMeasurement() + * and MSC_GetCacheMeasurement() for more details. + * + * @note + * The flash write and erase runs from RAM on the EFM32G devices. On all other + * devices the flash write and erase functions run from flash. + * + * @note + * Flash erase may add ms of delay to interrupt latency if executing from Flash. + * + * Flash write and erase operations are supported by @ref MSC_WriteWord(), + * @ref MSC_ErasePage(), and MSC_MassErase(). + * Mass erase is supported for MCU and SoC families with larger Flash sizes. + * + * @note + * @ref MSC_Init() must be called prior to any Flash write or erase operation. + * + * The following steps are necessary to perform a page erase and write: + * @include em_msc_erase_write.c + * + * @deprecated + * The configuration called EM_MSC_RUN_FROM_FLASH is deprecated. This was + * previously used for allocating the flash write functions in either flash + * or RAM. + * + * @note + * The configuration EM_MSC_RUN_FROM_RAM is used to allocate the flash + * write functions in RAM. By default, flash write + * functions are placed in RAM on EFM32G and Series 2 devices + * unless SL_RAMFUNC_DISABLE is defined. For other devices, + * flash write functions are placed in FLASH by default unless + * EM_MSC_RUN_FROM_RAM is defined and SL_RAMFUNC_DISABLE is not defined. + * + * @deprecated + * The function called MSC_WriteWordFast() is deprecated. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************* DEFINES ***************************************** + ******************************************************************************/ + +/** + * @brief + * Timeout used while waiting for Flash to become ready after a write. + * This number indicates the number of iterations to perform before + * issuing a timeout. + * + * @note + * Timeout is set very large (in the order of 100x longer than + * necessary). This is to avoid any corner case. + */ +#define MSC_PROGRAM_TIMEOUT 10000000UL + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if (defined(_EFM32_GECKO_FAMILY) \ + || defined(_SILICON_LABS_32B_SERIES_2) \ + || defined(EM_MSC_RUN_FROM_RAM)) \ + && !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +#define MSC_RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +#else +#define MSC_RAMFUNC_DECLARATOR +#define MSC_RAMFUNC_DEFINITION_BEGIN +#define MSC_RAMFUNC_DEFINITION_END +#endif +/** @endcond */ + +/******************************************************************************* + ************************* TYPEDEFS **************************************** + ******************************************************************************/ + +/** Return codes for writing/erasing Flash. */ +typedef enum { + mscReturnOk = 0, /**< Flash write/erase successful. */ + mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not Flash. */ + mscReturnLocked = -2, /**< Flash address is locked. */ + mscReturnTimeOut = -3, /**< Timeout while writing to Flash. */ + mscReturnUnaligned = -4 /**< Unaligned access to Flash. */ +} MSC_Status_TypeDef; + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/** Strategy for prioritized bus access. */ +typedef enum { + mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses. */ + mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses. */ + mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses. */ + mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority. */ +} MSC_BusStrategy_Typedef; +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/** AHBHOST masters that can use alternate MPAHBRAM ports. */ +typedef enum { + mscDmemMasterLDMA = _SYSCFG_DMEM0PORTMAPSEL_LDMAPORTSEL_SHIFT, + mscDmemMasterSRWAES = _SYSCFG_DMEM0PORTMAPSEL_SRWAESPORTSEL_SHIFT, + mscDmemMasterAHBSRW = _SYSCFG_DMEM0PORTMAPSEL_AHBSRWPORTSEL_SHIFT, + mscDmemMasterSRWECA0 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA0PORTSEL_SHIFT, + mscDmemMasterSRWECA1 = _SYSCFG_DMEM0PORTMAPSEL_SRWECA1PORTSEL_SHIFT, +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_MASK) + mscDmemMasterMVPAHBDATA0 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA0PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_MASK) + mscDmemMasterMVPAHBDATA1 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_MASK) + mscDmemMasterMVPAHBDATA2 = _SYSCFG_DMEM0PORTMAPSEL_MVPAHBDATA2PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_MASK) + mscDmemMasterLDMA1 = _SYSCFG_DMEM0PORTMAPSEL_LDMA1PORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_MASK) + mscDmemMasterSRWLDMA = _SYSCFG_DMEM0PORTMAPSEL_SRWLDMAPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_MASK) + mscDmemMasterUSB = _SYSCFG_DMEM0PORTMAPSEL_USBPORTSEL_SHIFT, +#endif +#if defined(_SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_MASK) + mscDmemMasterBUFC = _SYSCFG_DMEM0PORTMAPSEL_BUFCPORTSEL_SHIFT +#endif +} MSC_DmemMaster_TypeDef; +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/** AHB port given priority. */ +typedef enum { + mscPortPriorityNone = _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE, + mscPortPriorityPort0 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0, + mscPortPriorityPort1 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1, +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2) + mscPortPriorityPort2 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2, +#endif +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3) + mscPortPriorityPort3 = _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3, +#endif +} MSC_PortPriority_TypeDef; +#endif + +#if defined(MSC_READCTRL_DOUTBUFEN) || defined(MSC_RDATACTRL_DOUTBUFEN) +/** Code execution configuration */ +typedef struct { + bool doutBufEn; /**< Flash dout pipeline buffer enable */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + } + +#else +/** Code execution configuration. */ +typedef struct { + bool scbtEn; /**< Enable Suppressed Conditional Branch Target Prefetch. */ + bool prefetchEn; /**< Enable MSC prefetching. */ + bool ifcDis; /**< Disable instruction cache. */ + bool aiDis; /**< Disable automatic cache invalidation on write or erase. */ + bool iccDis; /**< Disable automatic caching of fetches in interrupt context. */ + bool useHprot; /**< Use ahb_hprot to determine if the instruction is cacheable or not. */ +} MSC_ExecConfig_TypeDef; + +/** Default MSC ExecConfig initialization. */ +#define MSC_EXECCONFIG_DEFAULT \ + { \ + false, \ + true, \ + false, \ + false, \ + false, \ + false, \ + } +#endif + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/** EFM32GG11B incorporates 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/** EFM32GG12B incorporates 3 memory banks including ECC support. */ +#define MSC_ECC_BANKS (3) + +/** Default MSC EccConfig initialization. */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + +/** xG26 chips incorporate 2 memory banks including ECC support. */ +#define MSC_ECC_BANKS (2) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false, false }, \ + { 0, 1 }, \ + } + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +/** Series 2 chips incorporate 1 memory bank including ECC support. */ +#define MSC_ECC_BANKS (1) +/** Default MSC EccConfig initialization */ +#define MSC_ECCCONFIG_DEFAULT \ + { \ + { false }, \ + { 0, 1 }, \ + } + +#else +#error Device not supported. +#endif + +/** ECC configuration. */ +typedef struct { + bool enableEccBank[MSC_ECC_BANKS]; /**< Array of bools to enable/disable + Error Correcting Code (ECC) for + each RAM bank that supports ECC on + the device. */ + uint32_t dmaChannels[2]; /**< Array of 2 DMA channel numbers to + use for ECC initialization. */ +} MSC_EccConfig_TypeDef; + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated type names. */ +#define mscBusStrategy_Typedef MSC_BusStrategy_Typedef +#define msc_Return_TypeDef MSC_Status_TypeDef +/** @endcond */ + +/******************************************************************************* + ************************* Inline Functions ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the status of the MSC register lock. + * + * @return + * Boolean true if register lock is applied, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_LockGetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_LOCKED_SID); +#elif defined(_MSC_STATUS_REGLOCK_MASK) + return (MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != MSC_STATUS_REGLOCK_UNLOCKED; +#else + return (MSC->LOCK & _MSC_LOCK_MASK) != MSC_LOCK_LOCKKEY_UNLOCKED; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to a locked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetLocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_LOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the MSC register lock to an unlocked state. + ******************************************************************************/ +__STATIC_INLINE void MSC_LockSetUnlocked(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_SET_UNLOCKED_SID); +#else + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the current value of the read control register (MSC_READCTRL). + * + * @return + * The 32-bit value read from the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_ReadCTRLGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_READCTRL_SID); +#else + return MSC->READCTRL; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the read control register (MSC_READCTRL). + * + * @param[in] value + * The 32-bit value to write to the MSC_READCTRL register. + ******************************************************************************/ +__STATIC_INLINE void MSC_ReadCTRLSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_READCTRL_SID, + value); +#else + MSC->READCTRL = value; +#endif +} + +#if defined(_MSC_PAGELOCK0_MASK) || defined(_MSC_INST_PAGELOCKWORD0_MASK) + +/***************************************************************************//** + * @brief + * Set the lockbit for a flash page in order to prevent page writes/erases to + * the corresponding page. + * + * @param[in] page_number + * The index of the page to apply the pagelock to. Must be in the range + * [0, (flash_size / page_size) - 1]. + ******************************************************************************/ +__STATIC_INLINE void MSC_PageLockSetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + pagelock_registers[page_number / 32] |= (1 << (page_number % 32)); +#endif +} + +/***************************************************************************//** + * @brief + * Get the value of the lockbit for a flash page. + * + * @param[in] page_number + * The index of the page to get the lockbit value from. Must be in the range + * [0, (flash_size / page_size) - 1]. + * + * @return + * Boolean true if the page is locked, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool MSC_PageLockGetLocked(uint32_t page_number) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return (bool)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_GET_PAGELOCK_SID, + page_number); +#else + EFM_ASSERT(page_number < (FLASH_SIZE / FLASH_PAGE_SIZE)); + + #if defined(_MSC_PAGELOCK0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->PAGELOCK0; + #elif defined(_MSC_INST_PAGELOCKWORD0_MASK) + uint32_t *pagelock_registers = (uint32_t *)&MSC->INST_PAGELOCKWORD0; + #endif + + return pagelock_registers[page_number / 32] & (1 << (page_number % 32)); +#endif +} + +#endif // _MSC_PAGELOCK0_MASK || _MSC_INST_PAGELOCKWORD0_MASK + +#if defined(_MSC_USERDATASIZE_MASK) + +/***************************************************************************//** + * @brief + * Get the size of the user data region in flash. + * + * @return + * The size of the user data region divided by 256. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_UserDataGetSize(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_USERDATA_SIZE_SID); +#else + return MSC->USERDATASIZE; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if defined(_MSC_MISCLOCKWORD_MASK) + +/***************************************************************************//** + * @brief + * Get the current value of the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @return + * The 32-bit value read from the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_MiscLockWordGet(void) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + return sli_tz_ns_interface_dispatch_simple_noarg( + (sli_tz_veneer_simple_noarg_fn)sli_tz_s_interface_dispatch_simple_no_args, + SLI_TZ_MSC_GET_MISCLOCKWORD_SID); +#else + return MSC->MISCLOCKWORD; +#endif +} + +/***************************************************************************//** + * @brief + * Write a value to the mass erase and user data page lock word + * (MSC_MISCLOCKWORD). + * + * @param[in] value + * The 32-bit value to write to the MSC_MISCLOCKWORD register. + ******************************************************************************/ +__STATIC_INLINE void MSC_MiscLockWordSet(uint32_t value) +{ +#if defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + (void)sli_tz_ns_interface_dispatch_simple( + (sli_tz_veneer_simple_fn)sli_tz_s_interface_dispatch_simple, + SLI_TZ_MSC_SET_MISCLOCKWORD_SID, + value); +#else + MSC->MISCLOCKWORD = value; +#endif +} + +#endif // _MSC_USERDATASIZE_MASK + +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + +/***************************************************************************//** + * @brief + * Clear one or more pending MSC interrupts. + * + * @param[in] flags + * Pending MSC interrupt source to clear. Use a bitwise logic OR combination + * of valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntClear(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_CLR = flags; +#else + MSC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more MSC interrupts. + * + * @param[in] flags + * MSC interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntDisable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_CLR = flags; +#else + MSC->IEN &= ~(flags); +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more MSC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * MSC_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * MSC interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntEnable(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IEN_SET = flags; +#else + MSC->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending MSC interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @return + * MSC interrupt sources pending. A bitwise logic OR combination of valid + * interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGet(void) +{ + return MSC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending MSC interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled MSC interrupt sources. + * The return value is the bitwise AND of + * - the enabled interrupt sources in MSC_IEN and + * - the pending interrupt flags MSC_IF + ******************************************************************************/ +__STATIC_INLINE uint32_t MSC_IntGetEnabled(void) +{ + uint32_t ien; + + ien = MSC->IEN; + return MSC->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending MSC interrupts from SW. + * + * @param[in] flags + * MSC interrupt sources to set to pending. Use a bitwise logic OR combination of + * valid interrupt flags for the MSC module (MSC_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE void MSC_IntSet(uint32_t flags) +{ +#if defined(MSC_HAS_SET_CLEAR) + MSC->IF_SET = flags; +#else + MSC->IFS = flags; +#endif +} + +#if defined(MSC_IF_CHOF) && defined(MSC_IF_CMOF) +/***************************************************************************//** + * @brief + * Start measuring the cache hit ratio. + * @details + * Starts performance counters. It is defined inline to + * minimize the impact of this code on the measurement itself. + ******************************************************************************/ +__STATIC_INLINE void MSC_StartCacheMeasurement(void) +{ + /* Clear CMOF and CHOF to catch these later. */ + MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF; + + /* Start performance counters. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STARTPC; +#else + MSC->CMD = MSC_CMD_STARTPC; +#endif +} + +/***************************************************************************//** + * @brief + * Stop measuring the hit rate. + * @note + * Defined inline to minimize the impact of this + * code on the measurement itself. + * Only works for relatively short sections of code. + * To measure longer sections of code, implement an IRQ Handler for + * the CHOF and CMOF overflow interrupts. These overflows need to be + * counted and included in the total. + * Functions can then be implemented as follows: + * @verbatim + * volatile uint32_t hitOverflows + * volatile uint32_t missOverflows + * + * void MSC_IRQHandler(void) + * { + * uint32_t flags; + * flags = MSC->IF; + * if (flags & MSC_IF_CHOF) { + * MSC->IFC = MSC_IF_CHOF; + * hitOverflows++; + * } + * if (flags & MSC_IF_CMOF) { + * MSC->IFC = MSC_IF_CMOF; + * missOverflows++; + * } + * } + * + * void startPerformanceCounters(void) + * { + * hitOverflows = 0; + * missOverflows = 0; + * + * MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF); + * NVIC_EnableIRQ(MSC_IRQn); + * + * MSC_StartCacheMeasurement(); + * } + * @endverbatim + * @return + * Returns -1 if there has been no cache accesses. + * Returns -2 if there has been an overflow in the performance counters. + * If not, it will return the percentage of hits versus misses. + ******************************************************************************/ +__STATIC_INLINE int32_t MSC_GetCacheMeasurement(void) +{ + int32_t total; + int32_t hits; + /* Stop counter before computing hit-rate. */ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_STOPPC; +#else + MSC->CMD = MSC_CMD_STOPPC; +#endif + + /* Check for overflows in performance counters. */ + if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF)) { + return -2; + } + + hits = (int32_t)MSC->CACHEHITS; + total = (int32_t)MSC->CACHEMISSES + hits; + + /* To avoid a division by zero. */ + if (total == 0) { + return -1; + } + + return (hits * 100) / total; +} + +/***************************************************************************//** + * @brief + * Flush contents of instruction cache. + ******************************************************************************/ +__STATIC_INLINE void MSC_FlushCache(void) +{ +#if defined(_MSC_CACHECMD_MASK) + MSC->CACHECMD = MSC_CACHECMD_INVCACHE; +#else + MSC->CMD = MSC_CMD_INVCACHE; +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCache(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, !enable); +} + +#if defined(MSC_READCTRL_ICCDIS) +/***************************************************************************//** + * @brief + * Enable or disable instruction cache functionality in IRQs. + * @param[in] enable + * Enable instruction cache. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableCacheIRQs(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, !enable); +} +#endif + +/***************************************************************************//** + * @brief + * Enable or disable instruction cache flushing when writing to flash. + * @param[in] enable + * Enable automatic cache flushing. Default is on. + ******************************************************************************/ +__STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable) +{ + BUS_RegBitWrite(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, !enable); +} +#endif /* defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF ) */ + +#if defined(_MSC_READCTRL_BUSSTRATEGY_MASK) +/***************************************************************************//** + * @brief + * Configure which unit should get priority on system bus. + * @param[in] mode + * Unit to prioritize bus accesses for. + ******************************************************************************/ +__STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode) +{ + MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode; +} +#endif + +/******************************************************************************* + ************************* PROTOTYPES ************************************** + ******************************************************************************/ + +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig); +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig); +#endif + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port); +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority); +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void); +#endif + +#if !defined(_SILICON_LABS_32B_SERIES_2) +/* Note that this function is deprecated because we no longer support + * placing msc code in ram. */ +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes); +#endif + +#if defined(MSC_WRITECMD_ERASEMAIN0) +/***************************************************************************//** + * @brief + * Erase the entire Flash in one operation. + * + * @note + * This command will erase the entire contents of the device. + * Use with care, both a debug session and all contents of the flash will be + * lost. The lock bit, MLW will prevent this operation from executing and + * might prevent a successful mass erase. + * + * @return + * Returns the status of the operation. + ******************************************************************************/ +SL_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_MassErase(void); +#endif + +#endif /* !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT */ + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress); + +MSC_RAMFUNC_DECLARATOR +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes); + +#if (_SILICON_LABS_32B_SERIES > 0) +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes); +#endif + +void MSC_Init(void); +void MSC_Deinit(void); + +/** @} (end addtogroup msc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ +#endif /* EM_MSC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h index d5044ba..77beeda 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_msc_compat.h @@ -1,81 +1,81 @@ -/***************************************************************************//** - * @file - * @brief Flash Controller (MSC) Compatibility Header - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_MSC_COMPAT_H -#define EM_MSC_COMPAT_H - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - -#define MSC_IF_PWROFFIF MSC_IF_PWROFF -#define _MSC_IF_PWROFFIF_SHIFT _MSC_IF_PWROFF_SHIFT -#define _MSC_IF_PWROFFIF_MASK _MSC_IF_PWROFF_MASK -#define _MSC_IF_PWROFFIF_DEFAULT _MSC_IF_PWROFF_DEFAULT -#define MSC_IF_PWROFFIF_DEFAULT MSC_IF_PWROFF_DEFAULT - -#define MSC_IEN_PWROFFIEN MSC_IEN_PWROFF -#define _MSC_IEN_PWROFFIEN_SHIFT _MSC_IEN_PWROFF_SHIFT -#define _MSC_IEN_PWROFFIEN_MASK _MSC_IEN_PWROFF_MASK -#define _MSC_IEN_PWROFFIEN_DEFAULT _MSC_IEN_PWROFF_DEFAULT -#define MSC_IEN_PWROFFIEN_DEFAULT MSC_IEN_PWROFF_DEFAULT - - -#define ICACHE_IEN_RAMERRORIEN ICACHE_IEN_RAMERROR -#define _ICACHE_IEN_RAMERRORIEN_SHIFT _ICACHE_IEN_RAMERROR_SHIFT -#define _ICACHE_IEN_RAMERRORIEN_MASK _ICACHE_IEN_RAMERROR_MASK -#define _ICACHE_IEN_RAMERRORIEN_DEFAULT _ICACHE_IEN_RAMERROR_DEFAULT -#define ICACHE_IEN_RAMERRORIEN_DEFAULT ICACHE_IEN_RAMERROR_DEFAULT - - -#define SYSCFG_IF_FRCRAMERR1BIF SYSCFG_IF_FRCRAMERR1B -#define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT _SYSCFG_IF_FRCRAMERR1B_SHIFT -#define _SYSCFG_IF_FRCRAMERR1BIF_MASK _SYSCFG_IF_FRCRAMERR1B_MASK -#define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT _SYSCFG_IF_FRCRAMERR1B_DEFAULT -#define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT SYSCFG_IF_FRCRAMERR1B_DEFAULT - -#define SYSCFG_IF_FRCRAMERR2BIF SYSCFG_IF_FRCRAMERR2B -#define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT _SYSCFG_IF_FRCRAMERR2B_SHIFT -#define _SYSCFG_IF_FRCRAMERR2BIF_MASK _SYSCFG_IF_FRCRAMERR2B_MASK -#define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT _SYSCFG_IF_FRCRAMERR2B_DEFAULT -#define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT SYSCFG_IF_FRCRAMERR2B_DEFAULT - -#define SYSCFG_IEN_FRCRAMERR1BIEN SYSCFG_IEN_FRCRAMERR1B -#define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR1B_SHIFT -#define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK _SYSCFG_IEN_FRCRAMERR1B_MASK -#define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR1B_DEFAULT -#define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR1B_DEFAULT - -#define SYSCFG_IEN_FRCRAMERR2BIEN SYSCFG_IEN_FRCRAMERR2B -#define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR2B_SHIFT -#define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK _SYSCFG_IEN_FRCRAMERR2B_MASK -#define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR2B_DEFAULT -#define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR2B_DEFAULT - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ -#endif /* EM_MSC_COMPAT_H */ +/***************************************************************************//** + * @file + * @brief Flash Controller (MSC) Compatibility Header + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_MSC_COMPAT_H +#define EM_MSC_COMPAT_H + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + +#define MSC_IF_PWROFFIF MSC_IF_PWROFF +#define _MSC_IF_PWROFFIF_SHIFT _MSC_IF_PWROFF_SHIFT +#define _MSC_IF_PWROFFIF_MASK _MSC_IF_PWROFF_MASK +#define _MSC_IF_PWROFFIF_DEFAULT _MSC_IF_PWROFF_DEFAULT +#define MSC_IF_PWROFFIF_DEFAULT MSC_IF_PWROFF_DEFAULT + +#define MSC_IEN_PWROFFIEN MSC_IEN_PWROFF +#define _MSC_IEN_PWROFFIEN_SHIFT _MSC_IEN_PWROFF_SHIFT +#define _MSC_IEN_PWROFFIEN_MASK _MSC_IEN_PWROFF_MASK +#define _MSC_IEN_PWROFFIEN_DEFAULT _MSC_IEN_PWROFF_DEFAULT +#define MSC_IEN_PWROFFIEN_DEFAULT MSC_IEN_PWROFF_DEFAULT + + +#define ICACHE_IEN_RAMERRORIEN ICACHE_IEN_RAMERROR +#define _ICACHE_IEN_RAMERRORIEN_SHIFT _ICACHE_IEN_RAMERROR_SHIFT +#define _ICACHE_IEN_RAMERRORIEN_MASK _ICACHE_IEN_RAMERROR_MASK +#define _ICACHE_IEN_RAMERRORIEN_DEFAULT _ICACHE_IEN_RAMERROR_DEFAULT +#define ICACHE_IEN_RAMERRORIEN_DEFAULT ICACHE_IEN_RAMERROR_DEFAULT + + +#define SYSCFG_IF_FRCRAMERR1BIF SYSCFG_IF_FRCRAMERR1B +#define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT _SYSCFG_IF_FRCRAMERR1B_SHIFT +#define _SYSCFG_IF_FRCRAMERR1BIF_MASK _SYSCFG_IF_FRCRAMERR1B_MASK +#define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT _SYSCFG_IF_FRCRAMERR1B_DEFAULT +#define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT SYSCFG_IF_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IF_FRCRAMERR2BIF SYSCFG_IF_FRCRAMERR2B +#define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT _SYSCFG_IF_FRCRAMERR2B_SHIFT +#define _SYSCFG_IF_FRCRAMERR2BIF_MASK _SYSCFG_IF_FRCRAMERR2B_MASK +#define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT _SYSCFG_IF_FRCRAMERR2B_DEFAULT +#define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT SYSCFG_IF_FRCRAMERR2B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR1BIEN SYSCFG_IEN_FRCRAMERR1B +#define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR1B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK _SYSCFG_IEN_FRCRAMERR1B_MASK +#define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR1B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR1B_DEFAULT + +#define SYSCFG_IEN_FRCRAMERR2BIEN SYSCFG_IEN_FRCRAMERR2B +#define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT _SYSCFG_IEN_FRCRAMERR2B_SHIFT +#define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK _SYSCFG_IEN_FRCRAMERR2B_MASK +#define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT _SYSCFG_IEN_FRCRAMERR2B_DEFAULT +#define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT SYSCFG_IEN_FRCRAMERR2B_DEFAULT + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_2 */ +#endif /* EM_MSC_COMPAT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h index 0a27947..2e3cad0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_prs.h @@ -1,1164 +1,1164 @@ -/***************************************************************************//** - * @file - * @brief Peripheral Reflex System (PRS) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_PRS_H -#define EM_PRS_H - -#include "em_device.h" -#include "em_gpio.h" - -#include -#include - -#if defined(PRS_COUNT) && (PRS_COUNT > 0) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup prs - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM -#elif defined(_EFM32_GECKO_FAMILY) -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT 0 -#else -/** PRS Synchronous channel count. */ - #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT -/** PRS Asynchronous channel count. */ - #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT -#endif - -#if !defined(_EFM32_GECKO_FAMILY) -/** PRS asynchronous support */ -#define PRS_ASYNC_SUPPORTED 1 -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Some devices have renamed signals so some of these signals are mapped to - common names. */ -#if defined(PRS_USART0_RXDATAV) -#define PRS_USART0_RXDATA PRS_USART0_RXDATAV -#endif -#if defined(PRS_USART1_RXDATAV) -#define PRS_USART1_RXDATA PRS_USART1_RXDATAV -#endif -#if defined(PRS_USART2_RXDATAV) -#define PRS_USART2_RXDATA PRS_USART2_RXDATAV -#endif -#if defined(PRS_BURTC_OVERFLOW) -#define PRS_BURTC_OF PRS_BURTC_OVERFLOW -#endif -#if defined(PRS_BURTC_COMP0) -#define PRS_BURTC_COMP PRS_BURTC_COMP0 -#endif -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** PRS Channel type. */ -typedef enum { - prsTypeAsync, /**< Asynchronous channel type. */ - prsTypeSync /**< Synchronous channel type.*/ -} PRS_ChType_t; - -/** Edge detection type. */ -typedef enum { - prsEdgeOff, /**< Leave signal as is. */ - prsEdgePos, /**< Generate pulses on positive edge. */ - prsEdgeNeg, /**< Generate pulses on negative edge. */ - prsEdgeBoth /**< Generate pulses on both edges. */ -} PRS_Edge_TypeDef; - -#if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) -/** Logic functions that can be used when combining two PRS channels. */ -typedef enum { - prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, /**< Logical 0. */ - prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, /**< A NOR B. */ - prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, /**< (!A) NOR B. */ - prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, /**< !A. */ - prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, /**< A AND (!B). */ - prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, /**< !B. */ - prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, /**< A XOR B. */ - prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, /**< A NAND B. */ - prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, /**< A AND B. */ - prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, /**< A XNOR B. */ - prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, /**< B. */ - prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, /**< (!A) OR B. */ - prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, /**< A. */ - prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, /**< A OR (!B). */ - prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, /**< A OR B. */ - prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, /**< Logical 1. */ -} PRS_Logic_t; -#endif - -/** PRS Signal. */ -typedef enum { -#if defined(_PRS_SYNC_CH_CTRL_SOURCESEL_MASK) - prsSignalNone = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x0 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ - prsSignalSW = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x1 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ -#else - prsSignalNone = PRS_CH_CTRL_SOURCESEL_NONE | (0x0 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ - prsSignalSW = PRS_CH_CTRL_SOURCESEL_NONE | (0x1 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ -#endif - -#if defined(PRS_PRS_CH11) - prsSignalPRS_CH0 = PRS_PRS_CH0, /**< PRS_CH0 signal */ - prsSignalPRS_CH1 = PRS_PRS_CH1, /**< PRS_CH1 signal */ - prsSignalPRS_CH2 = PRS_PRS_CH2, /**< PRS_CH2 signal */ - prsSignalPRS_CH3 = PRS_PRS_CH3, /**< PRS_CH3 signal */ - prsSignalPRS_CH4 = PRS_PRS_CH4, /**< PRS_CH4 signal */ - prsSignalPRS_CH5 = PRS_PRS_CH5, /**< PRS_CH5 signal */ - prsSignalPRS_CH6 = PRS_PRS_CH6, /**< PRS_CH6 signal */ - prsSignalPRS_CH7 = PRS_PRS_CH7, /**< PRS_CH7 signal */ - prsSignalPRS_CH8 = PRS_PRS_CH8, /**< PRS_CH8 signal */ - prsSignalPRS_CH9 = PRS_PRS_CH9, /**< PRS_CH9 signal */ - prsSignalPRS_CH10 = PRS_PRS_CH10, /**< PRS_CH10 signal */ - prsSignalPRS_CH11 = PRS_PRS_CH11, /**< PRS_CH11 signal */ -#endif -#if defined(PRS_PRS_CH23) - prsSignalPRS_CH12 = PRS_PRS_CH12, /**< PRS_CH12 signal */ - prsSignalPRS_CH13 = PRS_PRS_CH13, /**< PRS_CH13 signal */ - prsSignalPRS_CH14 = PRS_PRS_CH14, /**< PRS_CH14 signal */ - prsSignalPRS_CH15 = PRS_PRS_CH15, /**< PRS_CH15 signal */ - prsSignalPRS_CH16 = PRS_PRS_CH16, /**< PRS_CH16 signal */ - prsSignalPRS_CH17 = PRS_PRS_CH17, /**< PRS_CH17 signal */ - prsSignalPRS_CH18 = PRS_PRS_CH18, /**< PRS_CH18 signal */ - prsSignalPRS_CH19 = PRS_PRS_CH19, /**< PRS_CH19 signal */ - prsSignalPRS_CH20 = PRS_PRS_CH20, /**< PRS_CH20 signal */ - prsSignalPRS_CH21 = PRS_PRS_CH21, /**< PRS_CH21 signal */ - prsSignalPRS_CH22 = PRS_PRS_CH22, /**< PRS_CH22 signal */ - prsSignalPRS_CH23 = PRS_PRS_CH23, /**< PRS_CH23 signal */ -#endif - -#if defined(PRS_ADC0_SINGLE) - prsSignalADC0_SINGLE = PRS_ADC0_SINGLE, /**< ADC0_SINGLE signal */ - prsSignalADC0_SCAN = PRS_ADC0_SCAN, /**< ADC0_SCAN signal */ -#endif -#if defined(PRS_ADC1_SINGLE) - prsSignalADC1_SINGLE = PRS_ADC1_SINGLE, /**< ADC1_SINGLE signal */ - prsSignalADC1_SCAN = PRS_ADC1_SCAN, /**< ADC1_SCAN signal */ -#endif - - /* Timer Signals */ -#if defined(TIMER0) - prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ - prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ - prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ - prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ - prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER1) - prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ - prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ - prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ - prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ - prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER2) - prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ - prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ - prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ - prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ - prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER3) - prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ - prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ - prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ - prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ - prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ -#if defined(PRS_TIMER1_CC3) - prsSignalTIMER1_CC3 = PRS_TIMER1_CC3, /**< TIMER3 capture/compare channel 3 Signal. */ -#endif -#endif -#if defined(TIMER4) - prsSignalTIMER4_UF = PRS_TIMER4_UF, /**< TIMER4 underflow Signal. */ - prsSignalTIMER4_OF = PRS_TIMER4_OF, /**< TIMER4 overflow Signal. */ - prsSignalTIMER4_CC0 = PRS_TIMER4_CC0, /**< TIMER4 capture/compare channel 0 Signal. */ - prsSignalTIMER4_CC1 = PRS_TIMER4_CC1, /**< TIMER4 capture/compare channel 1 Signal. */ - prsSignalTIMER4_CC2 = PRS_TIMER4_CC2, /**< TIMER4 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER5) - prsSignalTIMER5_UF = PRS_TIMER5_UF, /**< TIMER5 underflow Signal. */ - prsSignalTIMER5_OF = PRS_TIMER5_OF, /**< TIMER5 overflow Signal. */ - prsSignalTIMER5_CC0 = PRS_TIMER5_CC0, /**< TIMER5 capture/compare channel 0 Signal. */ - prsSignalTIMER5_CC1 = PRS_TIMER5_CC1, /**< TIMER5 capture/compare channel 1 Signal. */ - prsSignalTIMER5_CC2 = PRS_TIMER5_CC2, /**< TIMER5 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER6) - prsSignalTIMER6_UF = PRS_TIMER6_UF, /**< TIMER6 underflow Signal. */ - prsSignalTIMER6_OF = PRS_TIMER6_OF, /**< TIMER6 overflow Signal. */ - prsSignalTIMER6_CC0 = PRS_TIMER6_CC0, /**< TIMER6 capture/compare channel 0 Signal. */ - prsSignalTIMER6_CC1 = PRS_TIMER6_CC1, /**< TIMER6 capture/compare channel 1 Signal. */ - prsSignalTIMER6_CC2 = PRS_TIMER6_CC2, /**< TIMER6 capture/compare channel 2 Signal. */ -#endif -#if defined(TIMER7) - prsSignalTIMER7_UF = PRS_TIMER7_UF, /**< TIMER7 underflow Signal. */ - prsSignalTIMER7_OF = PRS_TIMER7_OF, /**< TIMER7 overflow Signal. */ - prsSignalTIMER7_CC0 = PRS_TIMER7_CC0, /**< TIMER7 capture/compare channel 0 Signal. */ - prsSignalTIMER7_CC1 = PRS_TIMER7_CC1, /**< TIMER7 capture/compare channel 1 Signal. */ - prsSignalTIMER7_CC2 = PRS_TIMER7_CC2, /**< TIMER7 capture/compare channel 2 Signal. */ -#endif -#if defined(PRS_LETIMER0_CH0) - prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ - prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ -#endif -#if defined(PRS_LETIMER1_CH0) - prsSignalLETIMER1_CH0 = PRS_LETIMER1_CH0, /**< LETIMER1 channel 0 Signal. */ - prsSignalLETIMER1_CH1 = PRS_LETIMER1_CH1, /**< LETIMER1 channel 1 Signal. */ -#endif -#if defined(PRS_PCNT0_TCC) - prsSignalPCNT0_TCC = PRS_PCNT0_TCC, /**< PCNT0_TCC Signal. */ -#endif -#if defined(PRS_PCNT0_UFOF) - prsSignalPCNT0_UFOF = PRS_PCNT0_UFOF, /**< PCNT0_TCC Signal. */ - prsSignalPCNT0_DIR = PRS_PCNT0_DIR, /**< PCNT0_TCC Signal. */ -#endif -#if defined(PRS_PCNT1_TCC) - prsSignalPCNT1_TCC = PRS_PCNT1_TCC, /**< PCNT1_TCC Signal. */ - prsSignalPCNT1_UFOF = PRS_PCNT1_UFOF, /**< PCNT1_TCC Signal. */ - prsSignalPCNT1_DIR = PRS_PCNT1_DIR, /**< PCNT1_TCC Signal. */ -#endif -#if defined(PRS_PCNT2_TCC) - prsSignalPCNT2_TCC = PRS_PCNT2_TCC, /**< PCNT2_TCC Signal. */ - prsSignalPCNT2_UFOF = PRS_PCNT2_UFOF, /**< PCNT2_TCC Signal. */ - prsSignalPCNT2_DIR = PRS_PCNT2_DIR, /**< PCNT2_TCC Signal. */ -#endif -#if defined(PRS_CRYOTIMER_PERIOD) - prsSignalCRYOTIMER_PERIOD = PRS_CRYOTIMER_PERIOD, /**< CRYOTIMER_PERIOD Signal. */ -#endif -#if defined(PRS_CORE_CTIOUT0) - prsSignalCORE_CTIOUT0 = PRS_CORE_CTIOUT0, /**< CORE CTIOUT0 Signal. */ - prsSignalCORE_CTIOUT1 = PRS_CORE_CTIOUT1, /**< CORE CTIOUT1 Signal. */ - prsSignalCORE_CTIOUT2 = PRS_CORE_CTIOUT2, /**< CORE CTIOUT2 Signal. */ - prsSignalCORE_CTIOUT3 = PRS_CORE_CTIOUT3, /**< CORE CTIOUT3 Signal. */ -#endif -#if defined(PRS_CMUL_CLKOUT0) - prsSignalCMUL_CLKOUT0 = PRS_CMUL_CLKOUT0, /**< CMU CLKOUT0 Signal. */ - prsSignalCMUL_CLKOUT1 = PRS_CMUL_CLKOUT1, /**< CMU CLKOUT1 Signal. */ - prsSignalCMUL_CLKOUT2 = PRS_CMUL_CLKOUT2, /**< CMU CLKOUT2 Signal. */ -#endif -#if defined(PRS_PRSL_ASYNCH0) - prsSignalPRSL_ASYNCH0 = PRS_PRSL_ASYNCH0, /**< PRS channel 0 Signal. */ - prsSignalPRSL_ASYNCH1 = PRS_PRSL_ASYNCH1, /**< PRS channel 1 Signal. */ - prsSignalPRSL_ASYNCH2 = PRS_PRSL_ASYNCH2, /**< PRS channel 2 Signal. */ - prsSignalPRSL_ASYNCH3 = PRS_PRSL_ASYNCH3, /**< PRS channel 3 Signal. */ - prsSignalPRSL_ASYNCH4 = PRS_PRSL_ASYNCH4, /**< PRS channel 4 Signal. */ - prsSignalPRSL_ASYNCH5 = PRS_PRSL_ASYNCH5, /**< PRS channel 5 Signal. */ - prsSignalPRSL_ASYNCH6 = PRS_PRSL_ASYNCH6, /**< PRS channel 6 Signal. */ - prsSignalPRSL_ASYNCH7 = PRS_PRSL_ASYNCH7, /**< PRS channel 7 Signal. */ - prsSignalPRS_ASYNCH8 = PRS_PRS_ASYNCH8, /**< PRS channel 8 Signal. */ - prsSignalPRS_ASYNCH9 = PRS_PRS_ASYNCH9, /**< PRS channel 9 Signal. */ - prsSignalPRS_ASYNCH10 = PRS_PRS_ASYNCH10, /**< PRS channel 10 Signal. */ - prsSignalPRS_ASYNCH11 = PRS_PRS_ASYNCH11, /**< PRS channel 11 Signal. */ -#endif - - /* RTC/RTCC/SYSRTC/BURTC Signals */ -#if defined(PRS_RTC_OF) - prsSignalRTC_OF = PRS_RTC_OF, /**< RTC_OF signal. */ - prsSignalRTC_COMP0 = PRS_RTC_COMP0, /**< RTC_COMP0 signal. */ - prsSignalRTC_COMP1 = PRS_RTC_COMP1, /**< RTC_COMP1 signal. */ -#if defined(PRS_RTC_COMP5) - prsSignalRTC_COMP2 = PRS_RTC_COMP2, /**< RTC_COMP2 signal. */ - prsSignalRTC_COMP3 = PRS_RTC_COMP3, /**< RTC_COMP3 signal. */ - prsSignalRTC_COMP4 = PRS_RTC_COMP4, /**< RTC_COMP4 signal. */ - prsSignalRTC_COMP5 = PRS_RTC_COMP5, /**< RTC_COMP5 signal. */ -#endif -#endif -#if defined(RTCC) - prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ - prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ - prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ -#endif -#if defined(BURTC) - prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ - prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ -#endif -#if defined(SYSRTC0) - prsSignalSYSRTC0_GRP0OUT0 = PRS_SYSRTC0_GRP0OUT0, /**< SYSRTC GRP0OUT0 Signal. */ - prsSignalSYSRTC0_GRP0OUT1 = PRS_SYSRTC0_GRP0OUT1, /**< SYSRTC GRP0OUT1 Signal. */ - prsSignalSYSRTC0_GRP1OUT0 = PRS_SYSRTC0_GRP1OUT0, /**< SYSRTC GRP1OUT0 Signal. */ - prsSignalSYSRTC0_GRP1OUT1 = PRS_SYSRTC0_GRP1OUT1, /**< SYSRTC GRP1OUT1 Signal. */ -#endif -#if defined(PRS_HFXO0L_STATUS) - prsSignalHFXO0L_STATUS = PRS_HFXO0L_STATUS, /**< HFXO0L_STATUS Signal. */ - prsSignalHFXO0L_STATUS1 = PRS_HFXO0L_STATUS1, /**< HFXO0L_STATUS1 Signal. */ -#endif -#if defined(PRS_HFRCO0_COREEN) - prsSignalHFRCO0_COREEN = PRS_HFRCO0_COREEN, /**< HFRCO0_COREEN Signal. */ - prsSignalHFRCO0_STATE0 = PRS_HFRCO0_STATE0, /**< HFRCO0_STATE0 Signal. */ - prsSignalHFRCO0_STATE1 = PRS_HFRCO0_STATE1, /**< HFRCO0_STATE1 Signal. */ - prsSignalHFRCO0_STATE2 = PRS_HFRCO0_STATE2, /**< HFRCO0_STATE2 Signal. */ -#endif -#if defined(PRS_HFRCOEM23_COREEN) - prsSignalHFRCOEM23_COREEN = PRS_HFRCOEM23_COREEN, /**< HFRCOEM23_COREEN Signal. */ - prsSignalHFRCOEM23_STATE0 = PRS_HFRCOEM23_STATE0, /**< HFRCOEM23_STATE0 Signal. */ - prsSignalHFRCOEM23_STATE1 = PRS_HFRCOEM23_STATE1, /**< HFRCOEM23_STATE1 Signal. */ - prsSignalHFRCOEM23_STATE2 = PRS_HFRCOEM23_STATE2, /**< HFRCOEM23_STATE2 Signal. */ -#endif - - /* ACMP Signals */ -#if defined(ACMP0) - prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ -#endif -#if defined(ACMP1) - prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ -#endif -#if defined(ACMP2) - prsSignalACMP2_OUT = PRS_ACMP2_OUT, /**< ACMP2 output Signal. */ -#endif -#if defined(ACMP3) - prsSignalACMP3_OUT = PRS_ACMP3_OUT, /**< ACMP3 output Signal. */ -#endif - - /* VDAC Signals */ -#if defined(VDAC0) & (_SILICON_LABS_32B_SERIES >= 2) - prsSignalVDAC0_CH0WARM = PRS_VDAC0L_CH0WARM, /**< VDAC0 channel 0 warmed Signal. */ - prsSignalVDAC0_CH1WARM = PRS_VDAC0L_CH1WARM, /**< VDAC0 channel 1 warmed Signal. */ - prsSignalVDAC0_CH0DONE = PRS_VDAC0L_CH0DONEASYNC, /**< VDAC0 channel 0 conversion done Signal. */ - prsSignalVDAC0_CH1DONE = PRS_VDAC0L_CH1DONEASYNC, /**< VDAC0 channel 1 conversion done Signal. */ - prsSignalVDAC0_INTERNALTIMEROF = PRS_VDAC0L_INTERNALTIMEROF, /**< VDAC0 internal timer overflow Signal. */ - prsSignalVDAC0_REFRESHTIMEROF = PRS_VDAC0L_REFRESHTIMEROF, /**< VDAC0 internal timer overflow Signal. */ -#endif -#if defined(PRS_VDAC0_OPA3) - prsSignalVDAC0_CH0 = PRS_VDAC0_CH0, /**< VDAC0_CH0 Signal. */ - prsSignalVDAC0_CH1 = PRS_VDAC0_CH1, /**< VDAC0_CH1 Signal. */ - prsSignalVDAC0_OPA0 = PRS_VDAC0_OPA0, /**< VDAC0_OPA0 Signal. */ - prsSignalVDAC0_OPA1 = PRS_VDAC0_OPA1, /**< VDAC0_OPA1 Signal. */ - prsSignalVDAC0_OPA2 = PRS_VDAC0_OPA2, /**< VDAC0_OPA2 Signal. */ - prsSignalVDAC0_OPA3 = PRS_VDAC0_OPA3, /**< VDAC0_OPA3 Signal. */ -#endif -#if defined(VDAC1) & (_SILICON_LABS_32B_SERIES >= 2) - prsSignalVDAC1_CH0WARM = PRS_VDAC1L_CH0WARM, /**< VDAC1 channel 0 warmed Signal. */ - prsSignalVDAC1_CH1WARM = PRS_VDAC1L_CH1WARM, /**< VDAC1 channel 1 warmed Signal. */ - prsSignalVDAC1_CH0DONE = PRS_VDAC1L_CH0DONEASYNC, /**< VDAC1 channel 0 conversion done Signal. */ - prsSignalVDAC1_CH1DONE = PRS_VDAC1L_CH1DONEASYNC, /**< VDAC1 channel 1 conversion done Signal. */ - prsSignalVDAC1_INTERNALTIMEROF = PRS_VDAC1L_INTERNALTIMEROF, /**< VDAC1 internal timer overflow Signal. */ - prsSignalVDAC1_REFRESHTIMEROF = PRS_VDAC1L_REFRESHTIMEROF, /**< VDAC1 internal timer overflow Signal. */ -#endif - -#if defined(PRS_LESENSE_SCANRES15) - prsSignalLESENSE_SCANRES0 = PRS_LESENSE_SCANRES0, /**< LESENSE_SCANRES0 Signal. */ - prsSignalLESENSE_SCANRES1 = PRS_LESENSE_SCANRES1, /**< LESENSE_SCANRES1 Signal. */ - prsSignalLESENSE_SCANRES2 = PRS_LESENSE_SCANRES2, /**< LESENSE_SCANRES2 Signal. */ - prsSignalLESENSE_SCANRES3 = PRS_LESENSE_SCANRES3, /**< LESENSE_SCANRES3 Signal. */ - prsSignalLESENSE_SCANRES4 = PRS_LESENSE_SCANRES4, /**< LESENSE_SCANRES4 Signal. */ - prsSignalLESENSE_SCANRES5 = PRS_LESENSE_SCANRES5, /**< LESENSE_SCANRES5 Signal. */ - prsSignalLESENSE_SCANRES6 = PRS_LESENSE_SCANRES6, /**< LESENSE_SCANRES6 Signal. */ - prsSignalLESENSE_SCANRES7 = PRS_LESENSE_SCANRES7, /**< LESENSE_SCANRES7 Signal. */ - prsSignalLESENSE_SCANRES8 = PRS_LESENSE_SCANRES8, /**< LESENSE_SCANRES8 Signal. */ - prsSignalLESENSE_SCANRES9 = PRS_LESENSE_SCANRES9, /**< LESENSE_SCANRES9 Signal. */ - prsSignalLESENSE_SCANRES10 = PRS_LESENSE_SCANRES10, /**< LESENSE_SCANRES10 Signal. */ - prsSignalLESENSE_SCANRES11 = PRS_LESENSE_SCANRES11, /**< LESENSE_SCANRES11 Signal. */ - prsSignalLESENSE_SCANRES12 = PRS_LESENSE_SCANRES12, /**< LESENSE_SCANRES12 Signal. */ - prsSignalLESENSE_SCANRES13 = PRS_LESENSE_SCANRES13, /**< LESENSE_SCANRES13 Signal. */ - prsSignalLESENSE_SCANRES14 = PRS_LESENSE_SCANRES14, /**< LESENSE_SCANRES14 Signal. */ - prsSignalLESENSE_SCANRES15 = PRS_LESENSE_SCANRES15, /**< LESENSE_SCANRES15 Signal. */ -#endif -#if defined(PRS_LESENSE_DEC2) - prsSignalLESENSE_DEC0 = PRS_LESENSE_DEC0, /**< LESENSE_DEC0 Signal. */ - prsSignalLESENSE_DEC1 = PRS_LESENSE_DEC1, /**< LESENSE_DEC1 Signal. */ - prsSignalLESENSE_DEC2 = PRS_LESENSE_DEC2, /**< LESENSE_DEC2 Signal. */ -#endif -#if defined(PRS_LESENSE_DECOUT2) - prsSignalLESENSE_DECOUT0 = PRS_LESENSE_DECOUT0, /**< LESENSE_DECOUT0 Signal. */ - prsSignalLESENSE_DECOUT1 = PRS_LESENSE_DECOUT1, /**< LESENSE_DECOUT1 Signal. */ - prsSignalLESENSE_DECOUT2 = PRS_LESENSE_DECOUT2, /**< LESENSE_DECOUT2 Signal. */ -#endif -#if defined(PRS_LESENSE_DECCMP) - prsSignalLESENSE_DECCMP = PRS_LESENSE_DECCMP, /**< LESENSE_DECCMP Signal. */ -#endif -#if defined(PRS_LESENSE_MEASACT) - prsSignalLESENSE_MEASACT = PRS_LESENSE_MEASACT, /**< LESENSE_MEASACT Signal. */ -#endif - - /* USART Signals */ -#if defined(USART0) - prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 TX complete Signal. */ -#if defined(PRS_USART0_RXDATA) - prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 RX data available Signal. */ -#endif -#if defined(PRS_USART0_RXDATAV) - prsSignalUSART0_RXDATAV = PRS_USART0_RXDATAV, /**< USART0 RX data available Signal. */ -#endif -#if defined(PRS_USART0_IRTX) - prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR TX Signal. */ -#endif -#if defined(PRS_USART0_RTS) - prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ - prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 TX Signal. */ - prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ -#endif -#endif -#if defined(USART1) - prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 TX complete Signal. */ -#if defined(PRS_USART1_RXDATA) - prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 RX data available Signal. */ -#endif -#if defined(PRS_USART1_RXDATAV) - prsSignalUSART1_RXDATAV = PRS_USART1_RXDATAV, /**< USART1 RX data available Signal. */ -#endif -#if defined(PRS_USART1_IRTX) - prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR TX Signal. */ -#endif -#if defined(PRS_USART1_RTS) - prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ - prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 TX Signal. */ - prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ -#endif -#endif -#if defined(USART2) - prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 TX complete Signal. */ -#if defined(PRS_USART2_RXDATA) - prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 RX data available Signal. */ -#endif -#if defined(PRS_USART2_RXDATAV) - prsSignalUSART2_RXDATAV = PRS_USART2_RXDATAV, /**< USART2 RX data available Signal. */ -#endif -#if defined(PRS_USART2_IRTX) - prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR TX Signal. */ -#endif -#if defined(PRS_USART2_RTS) - prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ - prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 TX Signal. */ - prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ -#endif -#endif -#if defined(PRS_USART3_TXC) - prsSignalUSART3_TXC = PRS_USART3_TXC, /**< USART3 TX complete Signal. */ - prsSignalUSART3_RXDATAV = PRS_USART3_RXDATAV, /**< USART3 RX data available Signal. */ - prsSignalUSART3_RTS = PRS_USART3_RTS, /**< USART3 RTS Signal. */ - prsSignalUSART3_TX = PRS_USART3_TX, /**< USART3 TX Signal. */ - prsSignalUSART3_CS = PRS_USART3_CS, /**< USART3 chip select Signal. */ -#endif -#if defined(PRS_USART4_TXC) - prsSignalUSART4_TXC = PRS_USART4_TXC, /**< USART4 TX complete Signal. */ - prsSignalUSART4_RXDATAV = PRS_USART4_RXDATAV, /**< USART4 RX data available Signal. */ - prsSignalUSART4_RTS = PRS_USART4_RTS, /**< USART4 RTS Signal. */ - prsSignalUSART4_TX = PRS_USART4_TX, /**< USART4 TX Signal. */ - prsSignalUSART4_CS = PRS_USART4_CS, /**< USART4 chip select Signal. */ -#endif -#if defined(PRS_USART5_TXC) - prsSignalUSART5_TXC = PRS_USART5_TXC, /**< USART5 TX complete Signal. */ - prsSignalUSART5_RXDATAV = PRS_USART5_RXDATAV, /**< USART5 RX data available Signal. */ - prsSignalUSART5_RTS = PRS_USART5_RTS, /**< USART5 RTS Signal. */ - prsSignalUSART5_TX = PRS_USART5_TX, /**< USART5 TX Signal. */ - prsSignalUSART5_CS = PRS_USART5_CS, /**< USART5 chip select Signal. */ -#endif - -#if defined(UART0) - prsSignalUART0_TXC = PRS_UART0_TXC, /**< UART0 TX complete Signal. */ - prsSignalUART0_RXDATAV = PRS_UART0_RXDATAV, /**< UART0 RX data available Signal. */ -#if defined(PRS_UART1_IRTX) - prsSignalUART0_IRTX = PRS_UART0_IRTX, /**< UART0 IR TX Signal. */ -#endif -#if defined(PRS_UART0_RTS) - prsSignalUART0_RTS = PRS_UART0_RTS, /**< UART0 RTS Signal. */ - prsSignalUART0_TX = PRS_UART0_TX, /**< UART0 TX Signal. */ - prsSignalUART0_CS = PRS_UART0_CS, /**< UART0 chip select Signal. */ -#endif -#endif - -#if defined(UART1) - prsSignalUART1_TXC = PRS_UART1_TXC, /**< UART1 TX complete Signal. */ - prsSignalUART1_RXDATAV = PRS_UART1_RXDATAV, /**< UART1 RX data available Signal. */ -#if defined(PRS_UART1_IRTX) - prsSignalUART1_IRTX = PRS_UART1_IRTX, /**< UART1 IR RX Signal. */ -#endif -#if defined(PRS_UART1_RTS) - prsSignalUART1_RTS = PRS_UART1_RTS, /**< UART1 RTS Signal. */ - prsSignalUART1_TX = PRS_UART1_TX, /**< UART1 RX Signal. */ - prsSignalUART1_CS = PRS_UART1_CS, /**< UART1 chip select Signal. */ -#endif -#endif - -#if defined(PRS_USB_SOF) - prsSignalUSB_SOF = PRS_USB_SOF, /**< USB_SOF Signal. */ - prsSignalUSB_SOFSR = PRS_USB_SOFSR, /**< USB_SOFSR Signal. */ -#endif - -#if defined(PRS_CM4_TXEV) - prsSignalCM4_TXEV = PRS_CM4_TXEV, /**< TXEV Signal. */ -#endif -#if defined(PRS_CM4_ICACHEPCHITSOF) - prsSignalCM4_ICACHEPCHITSOF = PRS_CM4_ICACHEPCHITSOF, /**< ICACHEPCHITSOF Signal. */ - prsSignalCM4_ICACHEPCMISSESOF = PRS_CM4_ICACHEPCMISSESOF, /**< ICACHEPCMISSESOF Signal. */ -#endif - -#if defined(PRS_WTIMER0_UF) - prsSignalWTIMER0_UF = PRS_WTIMER0_UF, /**< WTIMER0_UF Signal. */ - prsSignalWTIMER0_OF = PRS_WTIMER0_OF, /**< WTIMER0_OF Signal. */ - prsSignalWTIMER0_CC0 = PRS_WTIMER0_CC0, /**< WTIMER0_CC0 Signal. */ - prsSignalWTIMER0_CC1 = PRS_WTIMER0_CC1, /**< WTIMER0_CC1 Signal. */ - prsSignalWTIMER0_CC2 = PRS_WTIMER0_CC2, /**< WTIMER0_CC2 Signal. */ -#endif -#if defined(PRS_WTIMER1_UF) - prsSignalWTIMER1_UF = PRS_WTIMER1_UF, /**< WTIMER1_UF Signal. */ - prsSignalWTIMER1_OF = PRS_WTIMER1_OF, /**< WTIMER1_OF Signal. */ - prsSignalWTIMER1_CC0 = PRS_WTIMER1_CC0, /**< WTIMER1_CC0 Signal. */ - prsSignalWTIMER1_CC1 = PRS_WTIMER1_CC1, /**< WTIMER1_CC1 Signal. */ - prsSignalWTIMER1_CC2 = PRS_WTIMER1_CC2, /**< WTIMER1_CC2 Signal. */ - prsSignalWTIMER1_CC3 = PRS_WTIMER1_CC3, /**< WTIMER1_CC3 Signal. */ -#endif -#if defined(PRS_WTIMER2_UF) - prsSignalWTIMER2_UF = PRS_WTIMER2_UF, /**< WTIMER2_UF Signal. */ - prsSignalWTIMER2_OF = PRS_WTIMER2_OF, /**< WTIMER2_OF Signal. */ - prsSignalWTIMER2_CC0 = PRS_WTIMER2_CC0, /**< WTIMER2_CC0 Signal. */ - prsSignalWTIMER2_CC1 = PRS_WTIMER2_CC1, /**< WTIMER2_CC1 Signal. */ - prsSignalWTIMER2_CC2 = PRS_WTIMER2_CC2, /**< WTIMER2_CC2 Signal. */ -#endif -#if defined(PRS_WTIMER3_UF) - prsSignalWTIMER3_UF = PRS_WTIMER3_UF, /**< WTIMER3_UF Signal. */ - prsSignalWTIMER3_OF = PRS_WTIMER3_OF, /**< WTIMER3_OF Signal. */ - prsSignalWTIMER3_CC0 = PRS_WTIMER3_CC0, /**< WTIMER3_CC0 Signal. */ - prsSignalWTIMER3_CC1 = PRS_WTIMER3_CC1, /**< WTIMER3_CC1 Signal. */ - prsSignalWTIMER3_CC2 = PRS_WTIMER3_CC2, /**< WTIMER3_CC2 Signal. */ -#endif - -/* EUSART Signals */ -#if defined(EUSART0) - prsSignalEUSART0_CS = PRS_EUSART0L_CS, /**< EUSART0 chip select Signal. */ - prsSignalEUSART0_IRTX = PRS_EUSART0L_IRDATX, /**< EUSART0 IR RX Signal. */ - prsSignalEUSART0_RTS = PRS_EUSART0L_RTS, /**< EUSART0 RTS Signal. */ - prsSignalEUSART0_RXDATA = PRS_EUSART0L_RXDATAV, /**< EUSART0 RX data available Signal. */ - prsSignalEUSART0_TX = PRS_EUSART0L_TX, /**< EUSART0 TX Signal. */ - prsSignalEUSART0_TXC = PRS_EUSART0L_TXC, /**< EUSART0 TX complete Signal. */ - prsSignalEUSART0_RXFL = PRS_EUSART0L_RXFL, /**< EUSART0 rxfl Signal. */ - prsSignalEUSART0_TXFL = PRS_EUSART0L_TXFL, /**< EUSART0 txfl Signal. */ -#endif -#if defined(EUSART1) - prsSignalEUSART1_CS = PRS_EUSART1L_CS, /**< EUSART1 chip select Signal. */ - prsSignalEUSART1_IRTX = PRS_EUSART1L_IRDATX, /**< EUSART1 IR TX Signal. */ - prsSignalEUSART1_RTS = PRS_EUSART1L_RTS, /**< EUSART1 RTS Signal. */ - prsSignalEUSART1_RXDATA = PRS_EUSART1L_RXDATAV, /**< EUSART1 RX data available Signal. */ - prsSignalEUSART1_TX = PRS_EUSART1L_TX, /**< EUSART1 TX Signal. */ - prsSignalEUSART1_TXC = PRS_EUSART1L_TXC, /**< EUSART1 TX complete Signal. */ - prsSignalEUSART1_RXFL = PRS_EUSART1L_RXFL, /**< EUSART1 rxfl Signal. */ - prsSignalEUSART1_TXFL = PRS_EUSART1L_TXFL, /**< EUSART1 txfl Signal. */ -#endif -#if defined(EUSART2) -#if defined(PRS_EUSART2L_CS) - prsSignalEUSART2_CS = PRS_EUSART2L_CS, /**< EUSART2 chip select Signal. */ - prsSignalEUSART2_IRTX = PRS_EUSART2L_IRDATX, /**< EUSART2 IR TX Signal. */ - prsSignalEUSART2_RTS = PRS_EUSART2L_RTS, /**< EUSART2 RTS Signal. */ - prsSignalEUSART2_RXDATA = PRS_EUSART2L_RXDATAV, /**< EUSART2 RX data available Signal. */ - prsSignalEUSART2_TX = PRS_EUSART2L_TX, /**< EUSART2 TX Signal. */ - prsSignalEUSART2_TXC = PRS_EUSART2L_TXC, /**< EUSART2 TX complete Signal. */ - prsSignalEUSART2_RXFL = PRS_EUSART2L_RXFL, /**< EUSART2 rxfl Signal. */ - prsSignalEUSART2_TXFL = PRS_EUSART2L_TXFL, /**< EUSART2 txfl Signal. */ -#else - prsSignalEUSART2_CS = PRS_EUSART2_CS, /**< EUSART2 chip select Signal. */ - prsSignalEUSART2_IRTX = PRS_EUSART2_IRDATX, /**< EUSART2 IR TX Signal. */ - prsSignalEUSART2_RTS = PRS_EUSART2_RTS, /**< EUSART2 RTS Signal. */ - prsSignalEUSART2_RXDATA = PRS_EUSART2_RXDATAV, /**< EUSART2 RX data available Signal. */ - prsSignalEUSART2_TX = PRS_EUSART2_TX, /**< EUSART2 TX Signal. */ - prsSignalEUSART2_TXC = PRS_EUSART2_TXC, /**< EUSART2 TX complete Signal. */ - prsSignalEUSART2_RXFL = PRS_EUSART2_RXFL, /**< EUSART2 rxfl Signal. */ - prsSignalEUSART2_TXFL = PRS_EUSART2_TXFL, /**< EUSART2 txfl Signal. */ -#endif -#endif -#if defined(EUSART3) -#if defined(PRS_EUSART3L_CS) - prsSignalEUSART3_CS = PRS_EUSART3L_CS, /**< EUSART3 chip select Signal. */ - prsSignalEUSART3_IRTX = PRS_EUSART3L_IRDATX, /**< EUSART3 IR TX Signal. */ - prsSignalEUSART3_RTS = PRS_EUSART3L_RTS, /**< EUSART3 RTS Signal. */ - prsSignalEUSART3_RXDATA = PRS_EUSART3L_RXDATAV, /**< EUSART3 RX data available Signal. */ - prsSignalEUSART3_TX = PRS_EUSART3L_TX, /**< EUSART3 TX Signal. */ - prsSignalEUSART3_TXC = PRS_EUSART3L_TXC, /**< EUSART3 TX complete Signal. */ - prsSignalEUSART3_RXFL = PRS_EUSART3L_RXFL, /**< EUSART3 rxfl Signal. */ - prsSignalEUSART3_TXFL = PRS_EUSART3L_TXFL, /**< EUSART3 txfl Signal. */ -#else - prsSignalEUSART3_CS = PRS_EUSART3_CS, /**< EUSART3 chip select Signal. */ - prsSignalEUSART3_IRTX = PRS_EUSART3_IRDATX, /**< EUSART3 IR TX Signal. */ - prsSignalEUSART3_RTS = PRS_EUSART3_RTS, /**< EUSART3 RTS Signal. */ - prsSignalEUSART3_RXDATA = PRS_EUSART3_RXDATAV, /**< EUSART3 RX data available Signal. */ - prsSignalEUSART3_TX = PRS_EUSART3_TX, /**< EUSART3 TX Signal. */ - prsSignalEUSART3_TXC = PRS_EUSART3_TXC, /**< EUSART3 TX complete Signal. */ - prsSignalEUSART3_RXFL = PRS_EUSART3_RXFL, /**< EUSART3 rxfl Signal. */ - prsSignalEUSART3_TXFL = PRS_EUSART3_TXFL, /**< EUSART3 txfl Signal. */ -#endif -#endif -#if defined(EUSART4) - prsSignalEUSART4_CS = PRS_EUSART4L_CS, /**< EUSART4 chip select Signal. */ - prsSignalEUSART4_IRTX = PRS_EUSART4L_IRDATX, /**< EUSART4 IR TX Signal. */ - prsSignalEUSART4_RTS = PRS_EUSART4L_RTS, /**< EUSART4 RTS Signal. */ - prsSignalEUSART4_RXDATA = PRS_EUSART4L_RXDATAV, /**< EUSART4 RX data available Signal. */ - prsSignalEUSART4_TX = PRS_EUSART4L_TX, /**< EUSART4 TX Signal. */ - prsSignalEUSART4_TXC = PRS_EUSART4L_TXC, /**< EUSART4 TX complete Signal. */ - prsSignalEUSART4_RXFL = PRS_EUSART4L_RXFL, /**< EUSART4 rxfl Signal. */ - prsSignalEUSART4_TXFL = PRS_EUSART4L_TXFL, /**< EUSART4 txfl Signal. */ -#endif - /* ADC Signals */ -#if defined(IADC0) - prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ - prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ - prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ -#endif - - /* GPIO pin Signals */ - prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ - prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ - prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ - prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ - prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ - prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ - prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ - prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ -#if defined(PRS_GPIO_PIN15) - prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ - prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ - prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ - prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ - prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ - prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ - prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ - prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ -#endif -#if defined(PRS_AGCL_CCA) - prsSignalAGCL_CCA = PRS_AGCL_CCA, /**< AGCL_CCA Signal. */ - prsSignalAGCL_CCAREQ = PRS_AGCL_CCAREQ, /**< AGCL_CCAREQ Signal. */ - prsSignalAGCL_GAINADJUST = PRS_AGCL_GAINADJUST, /**< AGCL_GAINADJUST Signal. */ - prsSignalAGCL_GAINOK = PRS_AGCL_GAINOK, /**< AGCL_GAINOK Signal. */ - prsSignalAGCL_GAINREDUCED = PRS_AGCL_GAINREDUCED, /**< AGCL_GAINREDUCED Signal. */ - prsSignalAGCL_IFPKI1 = PRS_AGCL_IFPKI1, /**< AGCL_IFPKI1 Signal. */ - prsSignalAGCL_IFPKQ2 = PRS_AGCL_IFPKQ2, /**< AGCL_IFPKQ2 Signal. */ - prsSignalAGCL_IFPKRST = PRS_AGCL_IFPKRST, /**< AGCL_IFPKRST Signal. */ -#endif -#if defined(PRS_AGC_PEAKDET) - prsSignalAGC_PEAKDET = PRS_AGC_PEAKDET, /**< AGC_PEAKDET Signal. */ - prsSignalAGC_PROPAGATED = PRS_AGC_PROPAGATED, /**< AGC_PROPAGATED Signal. */ - prsSignalAGC_RSSIDONE = PRS_AGC_RSSIDONE, /**< AGC_RSSIDONE Signal. */ -#endif -#if defined(PRS_BUFC_THR0) - prsSignalBUFC_THR0 = PRS_BUFC_THR0, /**< BUFC_THR0 Signal. */ - prsSignalBUFC_THR1 = PRS_BUFC_THR1, /**< BUFC_THR1 Signal. */ - prsSignalBUFC_THR2 = PRS_BUFC_THR2, /**< BUFC_THR2 Signal. */ - prsSignalBUFC_THR3 = PRS_BUFC_THR3, /**< BUFC_THR3 Signal. */ -#endif -#if defined(PRS_BUFC_CNT0) - prsSignalBUFC_CNT0 = PRS_BUFC_CNT0, /**< BUFC_CNT0 Signal. */ - prsSignalBUFC_CNT1 = PRS_BUFC_CNT1, /**< BUFC_CNT1 Signal. */ - prsSignalBUFC_FULL = PRS_BUFC_FULL, /**< BUFC_FULL Signal. */ -#endif -#if defined(PRS_MODEML_ADVANCE) - prsSignalMODEML_ADVANCE = PRS_MODEML_ADVANCE, /**< MODEML_ADVANCE Signal. */ - prsSignalMODEML_ANT0 = PRS_MODEML_ANT0, /**< MODEML_ANT0 Signal. */ - prsSignalMODEML_ANT1 = PRS_MODEML_ANT1, /**< MODEML_ANT1 Signal. */ - prsSignalMODEML_COHDSADET = PRS_MODEML_COHDSADET, /**< MODEML_COHDSADET Signal. */ - prsSignalMODEML_COHDSALIVE = PRS_MODEML_COHDSALIVE, /**< MODEML_COHDSALIVE Signal. */ - prsSignalMODEML_DCLK = PRS_MODEML_DCLK, /**< MODEML_DCLK Signal. */ - prsSignalMODEML_DOUT = PRS_MODEML_DOUT, /**< MODEML_DOUT Signal. */ - prsSignalMODEML_FRAMEDET = PRS_MODEML_FRAMEDET, /**< MODEML_FRAMEDET Signal. */ -#endif -#if defined(PRS_MODEM_FRAMEDET) - prsSignalMODEM_FRAMEDET = PRS_MODEM_FRAMEDET, /**< MODEM_FRAMEDET Signal. */ - prsSignalMODEM_TIMDET = PRS_MODEM_TIMDET, /**< MODEM_TIMDET Signal. */ - prsSignalMODEM_SYNCSENT = PRS_MODEM_SYNCSENT, /**< MODEM_SYNCSENT Signal. */ - prsSignalMODEM_PRESENT = PRS_MODEM_PRESENT, /**< MODEM_PRESENT Signal. */ - prsSignalMODEM_ANT0 = PRS_MODEM_ANT0, /**< MODEM_ANT0 Signal. */ - prsSignalMODEM_ANT1 = PRS_MODEM_ANT1, /**< MODEM_ANT1 Signal. */ -#endif -#if defined(PRS_MODEM_FRAMESENT) - prsSignalMODEM_FRAMESENT = PRS_MODEM_FRAMESENT, /**< MODEM_FRAMESENT Signal. */ -#endif -#if defined(PRS_MODEM_PREDET) - prsSignalMODEM_PREDET = PRS_MODEM_PREDET, /**< MODEM_PREDET Signal. */ -#endif -#if defined(PRS_MODEM_LRDSADET) - prsSignalMODEM_LRDSADET = PRS_MODEM_LRDSADET, /**< MODEM_LRDSADET Signal. */ - prsSignalMODEM_LRDSALIVE = PRS_MODEM_LRDSALIVE, /**< MODEM_LRDSALIVE Signal. */ -#endif -#if defined(PRS_MODEM_LOWCORR) - prsSignalMODEM_LOWCORR = PRS_MODEM_LOWCORR, /**< MODEM_LOWCORR Signal. */ - prsSignalMODEM_NEWSYMBOL = PRS_MODEM_NEWSYMBOL, /**< MODEM_NEWSYMBOL Signal. */ - prsSignalMODEM_NEWWND = PRS_MODEM_NEWWND, /**< MODEM_NEWWND Signal. */ - prsSignalMODEM_POSTPONE = PRS_MODEM_POSTPONE, /**< MODEM_POSTPONE Signal. */ -#endif -#if defined(PRS_MODEMH_PRESENT) - prsSignalMODEMH_PRESENT = PRS_MODEMH_PRESENT, /**< MODEMH_PRESENT Signal. */ - prsSignalMODEMH_RSSIJUMP = PRS_MODEMH_RSSIJUMP, /**< MODEMH_RSSIJUMP Signal. */ - prsSignalMODEMH_SYNCSENT = PRS_MODEMH_SYNCSENT, /**< MODEMH_SYNCSENT Signal. */ - prsSignalMODEMH_TIMDET = PRS_MODEMH_TIMDET, /**< MODEMH_TIMDET Signal. */ - prsSignalMODEMH_WEAK = PRS_MODEMH_WEAK, /**< MODEMH_WEAK Signal. */ - prsSignalMODEMH_EOF = PRS_MODEMH_EOF, /**< MODEMH_EOF Signal. */ -#endif -#if defined(PRS_MODEMH_SI) - prsSignalMODEMH_SI = PRS_MODEMH_SI, /**< MODEMH_SI Signal. */ -#endif -#if defined(PRS_FRC_DCLK) - prsSignalFRC_DCLK = PRS_FRC_DCLK, /**< FRC_DCLK Signal. */ - prsSignalFRC_DOUT = PRS_FRC_DOUT, /**< FRC_DOUT Signal. */ -#endif -#if defined(PRS_PROTIMERL_BOF) - prsSignalPROTIMERL_BOF = PRS_PROTIMERL_BOF, /**< PROTIMERL_BOF Signal. */ - prsSignalPROTIMERL_CC0 = PRS_PROTIMERL_CC0, /**< PROTIMERL_CC0 Signal. */ - prsSignalPROTIMERL_CC1 = PRS_PROTIMERL_CC1, /**< PROTIMERL_CC1 Signal. */ - prsSignalPROTIMERL_CC2 = PRS_PROTIMERL_CC2, /**< PROTIMERL_CC2 Signal. */ - prsSignalPROTIMERL_CC3 = PRS_PROTIMERL_CC3, /**< PROTIMERL_CC3 Signal. */ - prsSignalPROTIMERL_CC4 = PRS_PROTIMERL_CC4, /**< PROTIMERL_CC4 Signal. */ - prsSignalPROTIMERL_LBTF = PRS_PROTIMERL_LBTF, /**< PROTIMERL_LBTF Signal. */ - prsSignalPROTIMERL_LBTR = PRS_PROTIMERL_LBTR, /**< PROTIMERL_LBTR Signal. */ -#endif -#if defined(PRS_PROTIMER_LBTR) - prsSignalPROTIMER_LBTR = PRS_PROTIMER_LBTR, /**< PROTIMER_LBTR Signal. */ - prsSignalPROTIMER_LBTF = PRS_PROTIMER_LBTF, /**< PROTIMER_LBTF Signal. */ -#endif -#if defined(PRS_PROTIMER_LBTS) - prsSignalPROTIMER_LBTS = PRS_PROTIMER_LBTS, /**< PROTIMER_LBTS Signal. */ -#endif -#if defined(PRS_PROTIMER_POF) - prsSignalPROTIMER_POF = PRS_PROTIMER_POF, /**< PROTIMER_POF Signal. */ - prsSignalPROTIMER_T0MATCH = PRS_PROTIMER_T0MATCH, /**< PROTIMER_T0MATCH Signal. */ - prsSignalPROTIMER_T0UF = PRS_PROTIMER_T0UF, /**< PROTIMER_T0UF Signal. */ - prsSignalPROTIMER_T1MATCH = PRS_PROTIMER_T1MATCH, /**< PROTIMER_T1MATCH Signal. */ - prsSignalPROTIMER_T1UF = PRS_PROTIMER_T1UF, /**< PROTIMER_T1UF Signal. */ - prsSignalPROTIMER_WOF = PRS_PROTIMER_WOF, /**< PROTIMER_WOF Signal. */ -#endif -#if defined(PRS_RAC_ACTIVE) - prsSignalRAC_ACTIVE = PRS_RAC_ACTIVE, /**< RAC_ACTIVE Signal. */ - prsSignalRAC_LNAEN = PRS_RAC_LNAEN, /**< RAC_LNAEN Signal. */ - prsSignalRAC_PAEN = PRS_RAC_PAEN, /**< RAC_PAEN Signal. */ - prsSignalRAC_RX = PRS_RAC_RX, /**< RAC_RX Signal. */ - prsSignalRAC_TX = PRS_RAC_TX, /**< RAC_TX Signal. */ -#endif -#if defined(PRS_RACL_ACTIVE) - prsSignalRACL_ACTIVE = PRS_RACL_ACTIVE, /**< RACL_ACTIVE Signal. */ - prsSignalRACL_LNAEN = PRS_RACL_LNAEN, /**< RACL_LNAEN Signal. */ - prsSignalRACL_PAEN = PRS_RACL_PAEN, /**< RACL_PAEN Signal. */ - prsSignalRACL_RX = PRS_RACL_RX, /**< RACL_RX Signal. */ - prsSignalRACL_TX = PRS_RACL_TX, /**< RACL_TX Signal. */ - prsSignalRACL_CTIOUT0 = PRS_RACL_CTIOUT0, /**< RACL_CTIOUT0 Signal. */ - prsSignalRACL_CTIOUT1 = PRS_RACL_CTIOUT1, /**< RACL_CTIOUT1 Signal. */ - prsSignalRACL_CTIOUT2 = PRS_RACL_CTIOUT2, /**< RACL_CTIOUT2 Signal. */ -#endif -#if defined(PRS_RAC_CTIOUT3) - prsSignalRAC_CTIOUT3 = PRS_RAC_CTIOUT3, /**< RAC_CTIOUT3 Signal. */ -#endif -#if defined(PRS_RAC_AUXADCDATA) - prsSignalRAC_AUXADCDATA = PRS_RAC_AUXADCDATA, /**< RAC_AUXADCDATA Signal. */ - prsSignalRAC_AUXADCDATAVALID = PRS_RAC_AUXADCDATAVALID, /**< RAC_AUXADCDATAVALID Signal. */ -#endif -#if defined(PRS_SYNTH_MUX0) - prsSignalSYNTH_MUX0 = PRS_SYNTH_MUX0, /**< SYNTH_MUX0 Signal. */ - prsSignalSYNTH_MUX1 = PRS_SYNTH_MUX1, /**< SYNTH_MUX1 Signal. */ -#endif -#if defined(PRS_PRORTC_CCV0) - prsSignalPRORTC_CCV0 = PRS_PRORTC_CCV0, /**< PRORTC_CCV0 Signal. */ - prsSignalPRORTC_CCV1 = PRS_PRORTC_CCV1, /**< PRORTC_CCV1 Signal. */ -#endif -#if defined(RFFPLL0) - prsSignalRFFPLL0L_CLKDIGDIV4 = PRS_RFFPLL0L_CLKDIGDIV4, /**< RFFPLL0L CLKDIGDIV4 Signal. */ - prsSignalRFFPLL0L_CLKMODEMDIV4 = PRS_RFFPLL0L_CLKMODEMDIV4, /**< RFFPLL0L CLKMODEMDIV4 Signal. */ -#if defined(PRS_RFFPLL0L_RFBIASFSMSTATE0) - prsSignalRFFPLL0L_RFBIASFSMSTATE0 = PRS_RFFPLL0L_RFBIASFSMSTATE0, /**< RFFPLL0L RFBIASFSMSTATE0 Signal. */ - prsSignalRFFPLL0L_RFBIASFSMSTATE1 = PRS_RFFPLL0L_RFBIASFSMSTATE1, /**< RFFPLL0L RFBIASFSMSTATE1 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE0 = PRS_RFFPLL0L_RFFPLLFSMSTATE0, /**< RFFPLL0L RFFPLLFSMSTATE0 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE1 = PRS_RFFPLL0L_RFFPLLFSMSTATE1, /**< RFFPLL0L RFFPLLFSMSTATE1 Signal. */ - prsSignalRFFPLL0L_RFFPLLFSMSTATE2 = PRS_RFFPLL0L_RFFPLLFSMSTATE2, /**< RFFPLL0L RFFPLLFSMSTATE2 Signal. */ - prsSignalRFFPLL0L_RFBIASFSMSTATE2 = PRS_RFFPLL0L_RFBIASFSMSTATE2, /**< RFFPLL0L RFBIASFSMSTATE2 Signal. */ - prsSignalRFFPLL0_RFFPLLFSMSTATE3 = PRS_RFFPLL0_RFFPLLFSMSTATE3, /**< RFFPLL0 RFFPLLFSMSTATE3 Signal. */ -#endif -#endif -#if defined(FEFILT0) - prsSignalFEFILT0_REMPTY = PRS_FEFILT0_REMPTY, /**< FEFILT0 REMPTY Signal. */ - prsSignalFEFILT0_WFULL = PRS_FEFILT0_WFULL, /**< FEFILT0 WFULL Signal. */ -#endif -#if defined(FEFILT0) - prsSignalFEFILT1_REMPTY = PRS_FEFILT1_REMPTY, /**< FEFILT1 REMPTY Signal. */ - prsSignalFEFILT1_WFULL = PRS_FEFILT1_WFULL, /**< FEFILT1 WFULL Signal. */ -#endif -#if defined(ETAMPDET) - prsSignalETAMPDET_TAMPERSRCETAMPDET = PRS_ETAMPDET_TAMPERSRCETAMPDET, /**< ETAMPDET TAMPERSRCETAMPDET Signal. */ -#endif -#if defined(SMCTRL) - prsSignalSMCTRLL_SOFTM0 = PRS_SMCTRLL_SOFTM0, /**< SMCTRLL SOFTM0 Signal. */ - prsSignalSMCTRLL_SOFTM1 = PRS_SMCTRLL_SOFTM1, /**< SMCTRLL SOFTM1 Signal. */ - prsSignalSMCTRLL_SOFTM2 = PRS_SMCTRLL_SOFTM2, /**< SMCTRLL SOFTM2 Signal. */ - prsSignalSMCTRLL_SOFTM3 = PRS_SMCTRLL_SOFTM3, /**< SMCTRLL SOFTM3 Signal. */ - prsSignalSMCTRLL_SOFTM4 = PRS_SMCTRLL_SOFTM4, /**< SMCTRLL SOFTM4 Signal. */ - prsSignalSMCTRLL_SOFTM5 = PRS_SMCTRLL_SOFTM5, /**< SMCTRLL SOFTM5 Signal. */ - prsSignalSMCTRLL_SOFTM6 = PRS_SMCTRLL_SOFTM6, /**< SMCTRLL SOFTM6 Signal. */ - prsSignalSMCTRLL_SOFTM7 = PRS_SMCTRLL_SOFTM7, /**< SMCTRLL SOFTM7 Signal. */ - prsSignalSMCTRL_SOFTM8 = PRS_SMCTRL_SOFTM8, /**< SMCTRL SOFTM8 Signal. */ - prsSignalSMCTRL_SOFTM9 = PRS_SMCTRL_SOFTM9, /**< SMCTRL SOFTM9 Signal. */ - prsSignalSMCTRL_SOFTM10 = PRS_SMCTRL_SOFTM10, /**< SMCTRL SOFTM10 Signal. */ - prsSignalSMCTRL_SOFTM11 = PRS_SMCTRL_SOFTM11, /**< SMCTRL SOFTM11 Signal. */ -#endif -#if defined(PRS_SEHFRCO_COREEN) - prsSignalSEHFRCO_COREEN = PRS_SEHFRCO_COREEN, /**< SEHFRCO COREEN Signal. */ - prsSignalSEHFRCO_STATE0 = PRS_SEHFRCO_STATE0, /**< SEHFRCO STATE0 Signal. */ - prsSignalSEHFRCO_STATE1 = PRS_SEHFRCO_STATE1, /**< SEHFRCO STATE1 Signal. */ - prsSignalSEHFRCO_STATE2 = PRS_SEHFRCO_STATE2, /**< SEHFRCO STATE2 Signal. */ -#endif -#if defined(PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY) - prsSignalSEATAMPDET_SEATAMPDETSUPTPDELAY = PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY, /**< SEATAMPDET SEATAMPDETSUPTPDELAY Signal. */ -#endif -#if defined(PRS_DCDC_MONO70NSANA) - prsSignalDCDC_MONO70NSANA = PRS_DCDC_MONO70NSANA, /** DCDC Pulses for Coulomb Counter Calibration Signal. */ -#endif -#if defined(PRS_LFRCO_CALMEAS) - prsSignalLFRCO_CALMEAS = PRS_LFRCO_CALMEAS, /** LFRCO Calibration Measure Signal. */ - prsSignalLFRCO_SDM = PRS_LFRCO_SDM, /** LFRCO Sigma Delta Modulator output Signal. */ - prsSignalLFRCO_TCMEAS = PRS_LFRCO_TCMEAS, /** LFRCO Temperature Check Measure Signal. */ -#endif -} PRS_Signal_t; - -#if defined(_SILICON_LABS_32B_SERIES_2) -/** PRS Consumers. */ -typedef enum { - prsConsumerNone = 0x000, /**< No PRS consumer */ - prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ - prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ -#if defined(IADC_PRESENT) - prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ - prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ -#endif - prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ - prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ -#if defined(LETIMER0) - prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_CLEAR), /**< LETIMER0 clear consumer. */ - prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_START), /**< LETIMER0 start consumer. */ - prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_STOP), /**< LETIMER0 stop consumer. */ -#endif - prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ - prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ - prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ - prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ - prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ - prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ - prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ - prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ - prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ - prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ - prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ - prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ -#if defined(TIMER4) - prsConsumerTIMER4_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC0), /**< TIMER4 capture/compare channel 0 consumer. */ - prsConsumerTIMER4_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC1), /**< TIMER4 capture/compare channel 1 consumer. */ - prsConsumerTIMER4_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC2), /**< TIMER4 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER5) - prsConsumerTIMER5_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC0), /**< TIMER5 capture/compare channel 0 consumer. */ - prsConsumerTIMER5_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC1), /**< TIMER5 capture/compare channel 1 consumer. */ - prsConsumerTIMER5_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC2), /**< TIMER5 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER6) - prsConsumerTIMER6_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC0), /**< TIMER6 capture/compare channel 0 consumer. */ - prsConsumerTIMER6_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC1), /**< TIMER6 capture/compare channel 1 consumer. */ - prsConsumerTIMER6_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC2), /**< TIMER6 capture/compare channel 2 consumer. */ -#endif -#if defined(TIMER7) - prsConsumerTIMER7_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC0), /**< TIMER7 capture/compare channel 0 consumer. */ - prsConsumerTIMER7_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC1), /**< TIMER7 capture/compare channel 1 consumer. */ - prsConsumerTIMER7_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC2), /**< TIMER7 capture/compare channel 2 consumer. */ -#endif -#if defined(USART0) - prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ - prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ - prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 RX consumer. */ - prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ -#endif -#if defined(USART1) - prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ - prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ - prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 TX consumer. */ - prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ -#endif -#if defined(USART2) - prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ - prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ - prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 RX consumer. */ - prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ -#endif -#if defined(EUSART0) - prsConsumerEUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART0_CLK), /**< EUSART0 clk consumer. */ - prsConsumerEUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART0_RX), /**< EUSART0 RX consumer. */ - prsConsumerEUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART0_TRIGGER), /**< EUSART0 trigger consumer. */ -#endif -#if defined(EUSART1) - prsConsumerEUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART1_CLK), /**< EUSART1 clk consumer. */ - prsConsumerEUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART1_RX), /**< EUSART1 RX consumer. */ - prsConsumerEUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART1_TRIGGER), /**< EUSART1 trigger consumer. */ -#endif -#if defined(EUSART2) - prsConsumerEUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART2_CLK), /**< EUSART1 clk consumer. */ - prsConsumerEUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART2_RX), /**< EUSART2 RX consumer. */ - prsConsumerEUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART2_TRIGGER), /**< EUSART2 trigger consumer. */ -#endif -#if defined(EUSART3) - prsConsumerEUSART3_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART3_RX), /**< EUSART3 RX consumer. */ - prsConsumerEUSART3_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART3_TRIGGER), /**< EUSART3 trigger consumer. */ -#endif -#if defined(EUSART4) - prsConsumerEUSART4_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART4_RX), /**< EUSART4 RX consumer. */ - prsConsumerEUSART4_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART4_TRIGGER), /**< EUSART4 trigger consumer. */ -#endif -#if defined(EUART0) - prsConsumerEUART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUART0_RX), /**< EUART0 RX consumer. */ - prsConsumerEUART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUART0_TRIGGER), /**< EUART0 TRIGGER Consumer. */ -#endif - prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ - prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ -#if defined(WDOG1) - prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ - prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ -#endif -#if defined(PCNT0) - prsConsumerPCNT0_IN0 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S0IN), /**< PCNT0 input 0 consumer. */ - prsConsumerPCNT0_IN1 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S1IN), /**< PCNT0 input 1 consumer. */ -#endif -#if defined(_PRS_CONSUMER_RTCC_CC2_MASK) - prsConsumerRTCC_CC0 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC0), /**< RTCC capture/compare channel 0 consumer. */ - prsConsumerRTCC_CC1 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC1), /**< RTCC capture/compare channel 1 consumer. */ - prsConsumerRTCC_CC2 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC2), /**< RTCC capture/compare channel 2 consumer. */ -#endif -#if defined(SYSRTC0) - prsConsumerSYSRTC0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN0), /**< SYSRTC0 input 0 consumer. */ - prsConsumerSYSRTC0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN1), /**< SYSRTC0 input 1 consumer. */ -#endif -#if defined(_PRS_CONSUMER_HFXO0_OSCREQ_MASK) - prsConsumerHFXO0_OSCREQ = offsetof(PRS_TypeDef, CONSUMER_HFXO0_OSCREQ), /**< OSCREQ consumer. */ - prsConsumerHFXO0_TIMEOUT = offsetof(PRS_TypeDef, CONSUMER_HFXO0_TIMEOUT), /**< HFXO0_TIMEOUT consumer. */ -#endif -#if defined(LESENSE) - prsConsumerLESENSE_START = offsetof(PRS_TypeDef, CONSUMER_LESENSE_START), /**< LESENSE_START consumer. */ -#endif -#if defined(VDAC0) - prsConsumerVDAC0_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH0), /**< VDAC0 ASYNC TRIGER CH0 consumer. */ - prsConsumerVDAC0_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH1), /**< VDAC0 ASYNC TRIGER CH1 consumer. */ - prsConsumerVDAC0_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH0), /**< VDAC0 SYNC TRIGER CH0 consumer. */ - prsConsumerVDAC0_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH1), /**< VDAC0 SYNC TRIGER CH1 consumer. */ -#endif -#if defined(VDAC1) - prsConsumerVDAC1_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH0), /**< VDAC1 ASYNC TRIGER CH0 consumer. */ - prsConsumerVDAC1_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH1), /**< VDAC1 ASYNC TRIGER CH1 consumer. */ - prsConsumerVDAC1_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH0), /**< VDAC1 SYNC TRIGER CH0 consumer. */ - prsConsumerVDAC1_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH1), /**< VDAC1 SYNC TRIGER CH1 consumer. */ -#endif -} PRS_Consumer_t; -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Set level control bit for one or more channels. - * - * @details - * The level value for a channel is XORed with both the pulse possibly issued - * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). - * - * @cond DOXYDOC_S2_DEVICE - * @note - * Note that software level control is only available for asynchronous - * channels on Series 2 devices. - * @endcond - * - * @param[in] level - * Level to use for channels indicated by @p mask. Use logical OR combination - * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. - * - * @param[in] mask - * Mask indicating which channels to set level for. Use logical OR combination - * of PRS_SWLEVEL_CHnLEVEL defines. - ******************************************************************************/ -__STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) -{ -#if defined(_PRS_SWLEVEL_MASK) - PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); -#else - PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); -#endif -} - -/***************************************************************************//** - * @brief - * Get level control bit for all channels. - * - * @return - * The current software level configuration. - ******************************************************************************/ -__STATIC_INLINE uint32_t PRS_LevelGet(void) -{ -#if defined(_PRS_SWLEVEL_MASK) - return PRS->SWLEVEL; -#else - return PRS->ASYNC_SWLEVEL; -#endif -} - -#if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) -/***************************************************************************//** - * @brief - * Get the PRS channel values for all channels. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * The current PRS channel output values for all channels as a bitset. - ******************************************************************************/ -__STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) -{ -#if defined(_PRS_ASYNC_PEEK_MASK) - if (type == prsTypeAsync) { - return PRS->ASYNC_PEEK; - } else { - return PRS->SYNC_PEEK; - } -#else - (void) type; - return PRS->PEEK; -#endif -} - -/***************************************************************************//** - * @brief - * Get the PRS channel value for a single channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * The current PRS channel output value. This is either 0 or 1. - ******************************************************************************/ -__STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) -{ - return (0UL != ((PRS_Values(type) >> ch) & 0x1U)); -} -#endif - -/***************************************************************************//** - * @brief - * Trigger a high pulse (one HFPERCLK) for one or more channels. - * - * @details - * Setting a bit for a channel causes the bit in the register to remain high - * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit - * in PRS SWLEVEL register and the PRS input signal selected for the - * channel(s). - * - * @param[in] channels - * Logical ORed combination of channels to trigger a pulse for. Use - * PRS_SWPULSE_CHnPULSE defines. - ******************************************************************************/ -__STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) -{ -#if defined(_PRS_SWPULSE_MASK) - PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; -#else - PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; -#endif -} - -/***************************************************************************//** - * @brief - * Set the PRS channel level for one asynchronous PRS channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] level - * true to set the level high (1) and false to set the level low (0). - ******************************************************************************/ -__STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) -{ - PRS_LevelSet((uint32_t) level << ch, 0x1UL << ch); -} - -/***************************************************************************//** - * @brief - * Trigger a pulse on one PRS channel. - * - * @param[in] ch - * PRS channel number. - ******************************************************************************/ -__STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) -{ - PRS_PulseTrigger(0x1UL << ch); -} - -void PRS_SourceSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal, - PRS_Edge_TypeDef edge); - -#if defined(PRS_ASYNC_SUPPORTED) -void PRS_SourceAsyncSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal); -#endif -#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) -void PRS_GpioOutputLocation(unsigned int ch, - unsigned int location); -#endif - -int PRS_GetFreeChannel(PRS_ChType_t type); -void PRS_Reset(void); -void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); -#if defined(_SILICON_LABS_32B_SERIES_2) -uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource); -uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal); -void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); -void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); -void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); -#endif - -/** @} (end addtogroup prs) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ -#endif /* EM_PRS_H */ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_PRS_H +#define EM_PRS_H + +#include "em_device.h" +#include "em_gpio.h" + +#include +#include + +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup prs + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_SYNC_CH_NUM +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_ASYNC_CH_NUM +#elif defined(_EFM32_GECKO_FAMILY) +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT 0 +#else +/** PRS Synchronous channel count. */ + #define PRS_SYNC_CHAN_COUNT PRS_CHAN_COUNT +/** PRS Asynchronous channel count. */ + #define PRS_ASYNC_CHAN_COUNT PRS_CHAN_COUNT +#endif + +#if !defined(_EFM32_GECKO_FAMILY) +/** PRS asynchronous support */ +#define PRS_ASYNC_SUPPORTED 1 +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Some devices have renamed signals so some of these signals are mapped to + common names. */ +#if defined(PRS_USART0_RXDATAV) +#define PRS_USART0_RXDATA PRS_USART0_RXDATAV +#endif +#if defined(PRS_USART1_RXDATAV) +#define PRS_USART1_RXDATA PRS_USART1_RXDATAV +#endif +#if defined(PRS_USART2_RXDATAV) +#define PRS_USART2_RXDATA PRS_USART2_RXDATAV +#endif +#if defined(PRS_BURTC_OVERFLOW) +#define PRS_BURTC_OF PRS_BURTC_OVERFLOW +#endif +#if defined(PRS_BURTC_COMP0) +#define PRS_BURTC_COMP PRS_BURTC_COMP0 +#endif +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** PRS Channel type. */ +typedef enum { + prsTypeAsync, /**< Asynchronous channel type. */ + prsTypeSync /**< Synchronous channel type.*/ +} PRS_ChType_t; + +/** Edge detection type. */ +typedef enum { + prsEdgeOff, /**< Leave signal as is. */ + prsEdgePos, /**< Generate pulses on positive edge. */ + prsEdgeNeg, /**< Generate pulses on negative edge. */ + prsEdgeBoth /**< Generate pulses on both edges. */ +} PRS_Edge_TypeDef; + +#if defined(_PRS_ASYNC_CH_CTRL_FNSEL_MASK) +/** Logic functions that can be used when combining two PRS channels. */ +typedef enum { + prsLogic_Zero = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ZERO, /**< Logical 0. */ + prsLogic_A_NOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NOR_B, /**< A NOR B. */ + prsLogic_NOT_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_AND_B, /**< (!A) NOR B. */ + prsLogic_NOT_A = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A, /**< !A. */ + prsLogic_A_AND_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_NOT_B, /**< A AND (!B). */ + prsLogic_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_B, /**< !B. */ + prsLogic_A_XOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XOR_B, /**< A XOR B. */ + prsLogic_A_NAND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_NAND_B, /**< A NAND B. */ + prsLogic_A_AND_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_AND_B, /**< A AND B. */ + prsLogic_A_XNOR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_XNOR_B, /**< A XNOR B. */ + prsLogic_B = _PRS_ASYNC_CH_CTRL_FNSEL_B, /**< B. */ + prsLogic_NOT_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_NOT_A_OR_B, /**< (!A) OR B. */ + prsLogic_A = _PRS_ASYNC_CH_CTRL_FNSEL_A, /**< A. */ + prsLogic_A_OR_NOT_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_NOT_B, /**< A OR (!B). */ + prsLogic_A_OR_B = _PRS_ASYNC_CH_CTRL_FNSEL_A_OR_B, /**< A OR B. */ + prsLogic_One = _PRS_ASYNC_CH_CTRL_FNSEL_LOGICAL_ONE, /**< Logical 1. */ +} PRS_Logic_t; +#endif + +/** PRS Signal. */ +typedef enum { +#if defined(_PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + prsSignalNone = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x0 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_SYNC_CH_CTRL_SOURCESEL_DEFAULT | (0x1 << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#else + prsSignalNone = PRS_CH_CTRL_SOURCESEL_NONE | (0x0 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< No Signal. */ + prsSignalSW = PRS_CH_CTRL_SOURCESEL_NONE | (0x1 << _PRS_CH_CTRL_SIGSEL_SHIFT), /**< Software-reserved Signal. */ +#endif + +#if defined(PRS_PRS_CH11) + prsSignalPRS_CH0 = PRS_PRS_CH0, /**< PRS_CH0 signal */ + prsSignalPRS_CH1 = PRS_PRS_CH1, /**< PRS_CH1 signal */ + prsSignalPRS_CH2 = PRS_PRS_CH2, /**< PRS_CH2 signal */ + prsSignalPRS_CH3 = PRS_PRS_CH3, /**< PRS_CH3 signal */ + prsSignalPRS_CH4 = PRS_PRS_CH4, /**< PRS_CH4 signal */ + prsSignalPRS_CH5 = PRS_PRS_CH5, /**< PRS_CH5 signal */ + prsSignalPRS_CH6 = PRS_PRS_CH6, /**< PRS_CH6 signal */ + prsSignalPRS_CH7 = PRS_PRS_CH7, /**< PRS_CH7 signal */ + prsSignalPRS_CH8 = PRS_PRS_CH8, /**< PRS_CH8 signal */ + prsSignalPRS_CH9 = PRS_PRS_CH9, /**< PRS_CH9 signal */ + prsSignalPRS_CH10 = PRS_PRS_CH10, /**< PRS_CH10 signal */ + prsSignalPRS_CH11 = PRS_PRS_CH11, /**< PRS_CH11 signal */ +#endif +#if defined(PRS_PRS_CH23) + prsSignalPRS_CH12 = PRS_PRS_CH12, /**< PRS_CH12 signal */ + prsSignalPRS_CH13 = PRS_PRS_CH13, /**< PRS_CH13 signal */ + prsSignalPRS_CH14 = PRS_PRS_CH14, /**< PRS_CH14 signal */ + prsSignalPRS_CH15 = PRS_PRS_CH15, /**< PRS_CH15 signal */ + prsSignalPRS_CH16 = PRS_PRS_CH16, /**< PRS_CH16 signal */ + prsSignalPRS_CH17 = PRS_PRS_CH17, /**< PRS_CH17 signal */ + prsSignalPRS_CH18 = PRS_PRS_CH18, /**< PRS_CH18 signal */ + prsSignalPRS_CH19 = PRS_PRS_CH19, /**< PRS_CH19 signal */ + prsSignalPRS_CH20 = PRS_PRS_CH20, /**< PRS_CH20 signal */ + prsSignalPRS_CH21 = PRS_PRS_CH21, /**< PRS_CH21 signal */ + prsSignalPRS_CH22 = PRS_PRS_CH22, /**< PRS_CH22 signal */ + prsSignalPRS_CH23 = PRS_PRS_CH23, /**< PRS_CH23 signal */ +#endif + +#if defined(PRS_ADC0_SINGLE) + prsSignalADC0_SINGLE = PRS_ADC0_SINGLE, /**< ADC0_SINGLE signal */ + prsSignalADC0_SCAN = PRS_ADC0_SCAN, /**< ADC0_SCAN signal */ +#endif +#if defined(PRS_ADC1_SINGLE) + prsSignalADC1_SINGLE = PRS_ADC1_SINGLE, /**< ADC1_SINGLE signal */ + prsSignalADC1_SCAN = PRS_ADC1_SCAN, /**< ADC1_SCAN signal */ +#endif + + /* Timer Signals */ +#if defined(TIMER0) + prsSignalTIMER0_UF = PRS_TIMER0_UF, /**< TIMER0 underflow Signal. */ + prsSignalTIMER0_OF = PRS_TIMER0_OF, /**< TIMER0 overflow Signal. */ + prsSignalTIMER0_CC0 = PRS_TIMER0_CC0, /**< TIMER0 capture/compare channel 0 Signal. */ + prsSignalTIMER0_CC1 = PRS_TIMER0_CC1, /**< TIMER0 capture/compare channel 1 Signal. */ + prsSignalTIMER0_CC2 = PRS_TIMER0_CC2, /**< TIMER0 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER1) + prsSignalTIMER1_UF = PRS_TIMER1_UF, /**< TIMER1 underflow Signal. */ + prsSignalTIMER1_OF = PRS_TIMER1_OF, /**< TIMER1 overflow Signal. */ + prsSignalTIMER1_CC0 = PRS_TIMER1_CC0, /**< TIMER1 capture/compare channel 0 Signal. */ + prsSignalTIMER1_CC1 = PRS_TIMER1_CC1, /**< TIMER1 capture/compare channel 1 Signal. */ + prsSignalTIMER1_CC2 = PRS_TIMER1_CC2, /**< TIMER1 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER2) + prsSignalTIMER2_UF = PRS_TIMER2_UF, /**< TIMER2 underflow Signal. */ + prsSignalTIMER2_OF = PRS_TIMER2_OF, /**< TIMER2 overflow Signal. */ + prsSignalTIMER2_CC0 = PRS_TIMER2_CC0, /**< TIMER2 capture/compare channel 0 Signal. */ + prsSignalTIMER2_CC1 = PRS_TIMER2_CC1, /**< TIMER2 capture/compare channel 1 Signal. */ + prsSignalTIMER2_CC2 = PRS_TIMER2_CC2, /**< TIMER2 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER3) + prsSignalTIMER3_UF = PRS_TIMER3_UF, /**< TIMER3 underflow Signal. */ + prsSignalTIMER3_OF = PRS_TIMER3_OF, /**< TIMER3 overflow Signal. */ + prsSignalTIMER3_CC0 = PRS_TIMER3_CC0, /**< TIMER3 capture/compare channel 0 Signal. */ + prsSignalTIMER3_CC1 = PRS_TIMER3_CC1, /**< TIMER3 capture/compare channel 1 Signal. */ + prsSignalTIMER3_CC2 = PRS_TIMER3_CC2, /**< TIMER3 capture/compare channel 2 Signal. */ +#if defined(PRS_TIMER1_CC3) + prsSignalTIMER1_CC3 = PRS_TIMER1_CC3, /**< TIMER3 capture/compare channel 3 Signal. */ +#endif +#endif +#if defined(TIMER4) + prsSignalTIMER4_UF = PRS_TIMER4_UF, /**< TIMER4 underflow Signal. */ + prsSignalTIMER4_OF = PRS_TIMER4_OF, /**< TIMER4 overflow Signal. */ + prsSignalTIMER4_CC0 = PRS_TIMER4_CC0, /**< TIMER4 capture/compare channel 0 Signal. */ + prsSignalTIMER4_CC1 = PRS_TIMER4_CC1, /**< TIMER4 capture/compare channel 1 Signal. */ + prsSignalTIMER4_CC2 = PRS_TIMER4_CC2, /**< TIMER4 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER5) + prsSignalTIMER5_UF = PRS_TIMER5_UF, /**< TIMER5 underflow Signal. */ + prsSignalTIMER5_OF = PRS_TIMER5_OF, /**< TIMER5 overflow Signal. */ + prsSignalTIMER5_CC0 = PRS_TIMER5_CC0, /**< TIMER5 capture/compare channel 0 Signal. */ + prsSignalTIMER5_CC1 = PRS_TIMER5_CC1, /**< TIMER5 capture/compare channel 1 Signal. */ + prsSignalTIMER5_CC2 = PRS_TIMER5_CC2, /**< TIMER5 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER6) + prsSignalTIMER6_UF = PRS_TIMER6_UF, /**< TIMER6 underflow Signal. */ + prsSignalTIMER6_OF = PRS_TIMER6_OF, /**< TIMER6 overflow Signal. */ + prsSignalTIMER6_CC0 = PRS_TIMER6_CC0, /**< TIMER6 capture/compare channel 0 Signal. */ + prsSignalTIMER6_CC1 = PRS_TIMER6_CC1, /**< TIMER6 capture/compare channel 1 Signal. */ + prsSignalTIMER6_CC2 = PRS_TIMER6_CC2, /**< TIMER6 capture/compare channel 2 Signal. */ +#endif +#if defined(TIMER7) + prsSignalTIMER7_UF = PRS_TIMER7_UF, /**< TIMER7 underflow Signal. */ + prsSignalTIMER7_OF = PRS_TIMER7_OF, /**< TIMER7 overflow Signal. */ + prsSignalTIMER7_CC0 = PRS_TIMER7_CC0, /**< TIMER7 capture/compare channel 0 Signal. */ + prsSignalTIMER7_CC1 = PRS_TIMER7_CC1, /**< TIMER7 capture/compare channel 1 Signal. */ + prsSignalTIMER7_CC2 = PRS_TIMER7_CC2, /**< TIMER7 capture/compare channel 2 Signal. */ +#endif +#if defined(PRS_LETIMER0_CH0) + prsSignalLETIMER0_CH0 = PRS_LETIMER0_CH0, /**< LETIMER0 channel 0 Signal. */ + prsSignalLETIMER0_CH1 = PRS_LETIMER0_CH1, /**< LETIMER0 channel 1 Signal. */ +#endif +#if defined(PRS_LETIMER1_CH0) + prsSignalLETIMER1_CH0 = PRS_LETIMER1_CH0, /**< LETIMER1 channel 0 Signal. */ + prsSignalLETIMER1_CH1 = PRS_LETIMER1_CH1, /**< LETIMER1 channel 1 Signal. */ +#endif +#if defined(PRS_PCNT0_TCC) + prsSignalPCNT0_TCC = PRS_PCNT0_TCC, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT0_UFOF) + prsSignalPCNT0_UFOF = PRS_PCNT0_UFOF, /**< PCNT0_TCC Signal. */ + prsSignalPCNT0_DIR = PRS_PCNT0_DIR, /**< PCNT0_TCC Signal. */ +#endif +#if defined(PRS_PCNT1_TCC) + prsSignalPCNT1_TCC = PRS_PCNT1_TCC, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_UFOF = PRS_PCNT1_UFOF, /**< PCNT1_TCC Signal. */ + prsSignalPCNT1_DIR = PRS_PCNT1_DIR, /**< PCNT1_TCC Signal. */ +#endif +#if defined(PRS_PCNT2_TCC) + prsSignalPCNT2_TCC = PRS_PCNT2_TCC, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_UFOF = PRS_PCNT2_UFOF, /**< PCNT2_TCC Signal. */ + prsSignalPCNT2_DIR = PRS_PCNT2_DIR, /**< PCNT2_TCC Signal. */ +#endif +#if defined(PRS_CRYOTIMER_PERIOD) + prsSignalCRYOTIMER_PERIOD = PRS_CRYOTIMER_PERIOD, /**< CRYOTIMER_PERIOD Signal. */ +#endif +#if defined(PRS_CORE_CTIOUT0) + prsSignalCORE_CTIOUT0 = PRS_CORE_CTIOUT0, /**< CORE CTIOUT0 Signal. */ + prsSignalCORE_CTIOUT1 = PRS_CORE_CTIOUT1, /**< CORE CTIOUT1 Signal. */ + prsSignalCORE_CTIOUT2 = PRS_CORE_CTIOUT2, /**< CORE CTIOUT2 Signal. */ + prsSignalCORE_CTIOUT3 = PRS_CORE_CTIOUT3, /**< CORE CTIOUT3 Signal. */ +#endif +#if defined(PRS_CMUL_CLKOUT0) + prsSignalCMUL_CLKOUT0 = PRS_CMUL_CLKOUT0, /**< CMU CLKOUT0 Signal. */ + prsSignalCMUL_CLKOUT1 = PRS_CMUL_CLKOUT1, /**< CMU CLKOUT1 Signal. */ + prsSignalCMUL_CLKOUT2 = PRS_CMUL_CLKOUT2, /**< CMU CLKOUT2 Signal. */ +#endif +#if defined(PRS_PRSL_ASYNCH0) + prsSignalPRSL_ASYNCH0 = PRS_PRSL_ASYNCH0, /**< PRS channel 0 Signal. */ + prsSignalPRSL_ASYNCH1 = PRS_PRSL_ASYNCH1, /**< PRS channel 1 Signal. */ + prsSignalPRSL_ASYNCH2 = PRS_PRSL_ASYNCH2, /**< PRS channel 2 Signal. */ + prsSignalPRSL_ASYNCH3 = PRS_PRSL_ASYNCH3, /**< PRS channel 3 Signal. */ + prsSignalPRSL_ASYNCH4 = PRS_PRSL_ASYNCH4, /**< PRS channel 4 Signal. */ + prsSignalPRSL_ASYNCH5 = PRS_PRSL_ASYNCH5, /**< PRS channel 5 Signal. */ + prsSignalPRSL_ASYNCH6 = PRS_PRSL_ASYNCH6, /**< PRS channel 6 Signal. */ + prsSignalPRSL_ASYNCH7 = PRS_PRSL_ASYNCH7, /**< PRS channel 7 Signal. */ + prsSignalPRS_ASYNCH8 = PRS_PRS_ASYNCH8, /**< PRS channel 8 Signal. */ + prsSignalPRS_ASYNCH9 = PRS_PRS_ASYNCH9, /**< PRS channel 9 Signal. */ + prsSignalPRS_ASYNCH10 = PRS_PRS_ASYNCH10, /**< PRS channel 10 Signal. */ + prsSignalPRS_ASYNCH11 = PRS_PRS_ASYNCH11, /**< PRS channel 11 Signal. */ +#endif + + /* RTC/RTCC/SYSRTC/BURTC Signals */ +#if defined(PRS_RTC_OF) + prsSignalRTC_OF = PRS_RTC_OF, /**< RTC_OF signal. */ + prsSignalRTC_COMP0 = PRS_RTC_COMP0, /**< RTC_COMP0 signal. */ + prsSignalRTC_COMP1 = PRS_RTC_COMP1, /**< RTC_COMP1 signal. */ +#if defined(PRS_RTC_COMP5) + prsSignalRTC_COMP2 = PRS_RTC_COMP2, /**< RTC_COMP2 signal. */ + prsSignalRTC_COMP3 = PRS_RTC_COMP3, /**< RTC_COMP3 signal. */ + prsSignalRTC_COMP4 = PRS_RTC_COMP4, /**< RTC_COMP4 signal. */ + prsSignalRTC_COMP5 = PRS_RTC_COMP5, /**< RTC_COMP5 signal. */ +#endif +#endif +#if defined(RTCC) + prsSignalRTCC_CCV0 = PRS_RTCC_CCV0, /**< RTCC capture/compare channel 0 Signal. */ + prsSignalRTCC_CCV1 = PRS_RTCC_CCV1, /**< RTCC capture/compare channel 1 Signal. */ + prsSignalRTCC_CCV2 = PRS_RTCC_CCV2, /**< RTCC capture/compare channel 2 Signal. */ +#endif +#if defined(BURTC) + prsSignalBURTC_COMP = PRS_BURTC_COMP, /**< BURTC compare Signal. */ + prsSignalBURTC_OF = PRS_BURTC_OF, /**< BURTC overflow Signal. */ +#endif +#if defined(SYSRTC0) + prsSignalSYSRTC0_GRP0OUT0 = PRS_SYSRTC0_GRP0OUT0, /**< SYSRTC GRP0OUT0 Signal. */ + prsSignalSYSRTC0_GRP0OUT1 = PRS_SYSRTC0_GRP0OUT1, /**< SYSRTC GRP0OUT1 Signal. */ + prsSignalSYSRTC0_GRP1OUT0 = PRS_SYSRTC0_GRP1OUT0, /**< SYSRTC GRP1OUT0 Signal. */ + prsSignalSYSRTC0_GRP1OUT1 = PRS_SYSRTC0_GRP1OUT1, /**< SYSRTC GRP1OUT1 Signal. */ +#endif +#if defined(PRS_HFXO0L_STATUS) + prsSignalHFXO0L_STATUS = PRS_HFXO0L_STATUS, /**< HFXO0L_STATUS Signal. */ + prsSignalHFXO0L_STATUS1 = PRS_HFXO0L_STATUS1, /**< HFXO0L_STATUS1 Signal. */ +#endif +#if defined(PRS_HFRCO0_COREEN) + prsSignalHFRCO0_COREEN = PRS_HFRCO0_COREEN, /**< HFRCO0_COREEN Signal. */ + prsSignalHFRCO0_STATE0 = PRS_HFRCO0_STATE0, /**< HFRCO0_STATE0 Signal. */ + prsSignalHFRCO0_STATE1 = PRS_HFRCO0_STATE1, /**< HFRCO0_STATE1 Signal. */ + prsSignalHFRCO0_STATE2 = PRS_HFRCO0_STATE2, /**< HFRCO0_STATE2 Signal. */ +#endif +#if defined(PRS_HFRCOEM23_COREEN) + prsSignalHFRCOEM23_COREEN = PRS_HFRCOEM23_COREEN, /**< HFRCOEM23_COREEN Signal. */ + prsSignalHFRCOEM23_STATE0 = PRS_HFRCOEM23_STATE0, /**< HFRCOEM23_STATE0 Signal. */ + prsSignalHFRCOEM23_STATE1 = PRS_HFRCOEM23_STATE1, /**< HFRCOEM23_STATE1 Signal. */ + prsSignalHFRCOEM23_STATE2 = PRS_HFRCOEM23_STATE2, /**< HFRCOEM23_STATE2 Signal. */ +#endif + + /* ACMP Signals */ +#if defined(ACMP0) + prsSignalACMP0_OUT = PRS_ACMP0_OUT, /**< ACMP0 Signal. */ +#endif +#if defined(ACMP1) + prsSignalACMP1_OUT = PRS_ACMP1_OUT, /**< ACMP1 output Signal. */ +#endif +#if defined(ACMP2) + prsSignalACMP2_OUT = PRS_ACMP2_OUT, /**< ACMP2 output Signal. */ +#endif +#if defined(ACMP3) + prsSignalACMP3_OUT = PRS_ACMP3_OUT, /**< ACMP3 output Signal. */ +#endif + + /* VDAC Signals */ +#if defined(VDAC0) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC0_CH0WARM = PRS_VDAC0L_CH0WARM, /**< VDAC0 channel 0 warmed Signal. */ + prsSignalVDAC0_CH1WARM = PRS_VDAC0L_CH1WARM, /**< VDAC0 channel 1 warmed Signal. */ + prsSignalVDAC0_CH0DONE = PRS_VDAC0L_CH0DONEASYNC, /**< VDAC0 channel 0 conversion done Signal. */ + prsSignalVDAC0_CH1DONE = PRS_VDAC0L_CH1DONEASYNC, /**< VDAC0 channel 1 conversion done Signal. */ + prsSignalVDAC0_INTERNALTIMEROF = PRS_VDAC0L_INTERNALTIMEROF, /**< VDAC0 internal timer overflow Signal. */ + prsSignalVDAC0_REFRESHTIMEROF = PRS_VDAC0L_REFRESHTIMEROF, /**< VDAC0 internal timer overflow Signal. */ +#endif +#if defined(PRS_VDAC0_OPA3) + prsSignalVDAC0_CH0 = PRS_VDAC0_CH0, /**< VDAC0_CH0 Signal. */ + prsSignalVDAC0_CH1 = PRS_VDAC0_CH1, /**< VDAC0_CH1 Signal. */ + prsSignalVDAC0_OPA0 = PRS_VDAC0_OPA0, /**< VDAC0_OPA0 Signal. */ + prsSignalVDAC0_OPA1 = PRS_VDAC0_OPA1, /**< VDAC0_OPA1 Signal. */ + prsSignalVDAC0_OPA2 = PRS_VDAC0_OPA2, /**< VDAC0_OPA2 Signal. */ + prsSignalVDAC0_OPA3 = PRS_VDAC0_OPA3, /**< VDAC0_OPA3 Signal. */ +#endif +#if defined(VDAC1) & (_SILICON_LABS_32B_SERIES >= 2) + prsSignalVDAC1_CH0WARM = PRS_VDAC1L_CH0WARM, /**< VDAC1 channel 0 warmed Signal. */ + prsSignalVDAC1_CH1WARM = PRS_VDAC1L_CH1WARM, /**< VDAC1 channel 1 warmed Signal. */ + prsSignalVDAC1_CH0DONE = PRS_VDAC1L_CH0DONEASYNC, /**< VDAC1 channel 0 conversion done Signal. */ + prsSignalVDAC1_CH1DONE = PRS_VDAC1L_CH1DONEASYNC, /**< VDAC1 channel 1 conversion done Signal. */ + prsSignalVDAC1_INTERNALTIMEROF = PRS_VDAC1L_INTERNALTIMEROF, /**< VDAC1 internal timer overflow Signal. */ + prsSignalVDAC1_REFRESHTIMEROF = PRS_VDAC1L_REFRESHTIMEROF, /**< VDAC1 internal timer overflow Signal. */ +#endif + +#if defined(PRS_LESENSE_SCANRES15) + prsSignalLESENSE_SCANRES0 = PRS_LESENSE_SCANRES0, /**< LESENSE_SCANRES0 Signal. */ + prsSignalLESENSE_SCANRES1 = PRS_LESENSE_SCANRES1, /**< LESENSE_SCANRES1 Signal. */ + prsSignalLESENSE_SCANRES2 = PRS_LESENSE_SCANRES2, /**< LESENSE_SCANRES2 Signal. */ + prsSignalLESENSE_SCANRES3 = PRS_LESENSE_SCANRES3, /**< LESENSE_SCANRES3 Signal. */ + prsSignalLESENSE_SCANRES4 = PRS_LESENSE_SCANRES4, /**< LESENSE_SCANRES4 Signal. */ + prsSignalLESENSE_SCANRES5 = PRS_LESENSE_SCANRES5, /**< LESENSE_SCANRES5 Signal. */ + prsSignalLESENSE_SCANRES6 = PRS_LESENSE_SCANRES6, /**< LESENSE_SCANRES6 Signal. */ + prsSignalLESENSE_SCANRES7 = PRS_LESENSE_SCANRES7, /**< LESENSE_SCANRES7 Signal. */ + prsSignalLESENSE_SCANRES8 = PRS_LESENSE_SCANRES8, /**< LESENSE_SCANRES8 Signal. */ + prsSignalLESENSE_SCANRES9 = PRS_LESENSE_SCANRES9, /**< LESENSE_SCANRES9 Signal. */ + prsSignalLESENSE_SCANRES10 = PRS_LESENSE_SCANRES10, /**< LESENSE_SCANRES10 Signal. */ + prsSignalLESENSE_SCANRES11 = PRS_LESENSE_SCANRES11, /**< LESENSE_SCANRES11 Signal. */ + prsSignalLESENSE_SCANRES12 = PRS_LESENSE_SCANRES12, /**< LESENSE_SCANRES12 Signal. */ + prsSignalLESENSE_SCANRES13 = PRS_LESENSE_SCANRES13, /**< LESENSE_SCANRES13 Signal. */ + prsSignalLESENSE_SCANRES14 = PRS_LESENSE_SCANRES14, /**< LESENSE_SCANRES14 Signal. */ + prsSignalLESENSE_SCANRES15 = PRS_LESENSE_SCANRES15, /**< LESENSE_SCANRES15 Signal. */ +#endif +#if defined(PRS_LESENSE_DEC2) + prsSignalLESENSE_DEC0 = PRS_LESENSE_DEC0, /**< LESENSE_DEC0 Signal. */ + prsSignalLESENSE_DEC1 = PRS_LESENSE_DEC1, /**< LESENSE_DEC1 Signal. */ + prsSignalLESENSE_DEC2 = PRS_LESENSE_DEC2, /**< LESENSE_DEC2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECOUT2) + prsSignalLESENSE_DECOUT0 = PRS_LESENSE_DECOUT0, /**< LESENSE_DECOUT0 Signal. */ + prsSignalLESENSE_DECOUT1 = PRS_LESENSE_DECOUT1, /**< LESENSE_DECOUT1 Signal. */ + prsSignalLESENSE_DECOUT2 = PRS_LESENSE_DECOUT2, /**< LESENSE_DECOUT2 Signal. */ +#endif +#if defined(PRS_LESENSE_DECCMP) + prsSignalLESENSE_DECCMP = PRS_LESENSE_DECCMP, /**< LESENSE_DECCMP Signal. */ +#endif +#if defined(PRS_LESENSE_MEASACT) + prsSignalLESENSE_MEASACT = PRS_LESENSE_MEASACT, /**< LESENSE_MEASACT Signal. */ +#endif + + /* USART Signals */ +#if defined(USART0) + prsSignalUSART0_TXC = PRS_USART0_TXC, /**< USART0 TX complete Signal. */ +#if defined(PRS_USART0_RXDATA) + prsSignalUSART0_RXDATA = PRS_USART0_RXDATA, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_RXDATAV) + prsSignalUSART0_RXDATAV = PRS_USART0_RXDATAV, /**< USART0 RX data available Signal. */ +#endif +#if defined(PRS_USART0_IRTX) + prsSignalUSART0_IRTX = PRS_USART0_IRTX, /**< USART0 IR TX Signal. */ +#endif +#if defined(PRS_USART0_RTS) + prsSignalUSART0_RTS = PRS_USART0_RTS, /**< USART0 RTS Signal. */ + prsSignalUSART0_TX = PRS_USART0_TX, /**< USART0 TX Signal. */ + prsSignalUSART0_CS = PRS_USART0_CS, /**< USART0 chip select Signal. */ +#endif +#endif +#if defined(USART1) + prsSignalUSART1_TXC = PRS_USART1_TXC, /**< USART1 TX complete Signal. */ +#if defined(PRS_USART1_RXDATA) + prsSignalUSART1_RXDATA = PRS_USART1_RXDATA, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_RXDATAV) + prsSignalUSART1_RXDATAV = PRS_USART1_RXDATAV, /**< USART1 RX data available Signal. */ +#endif +#if defined(PRS_USART1_IRTX) + prsSignalUSART1_IRTX = PRS_USART1_IRTX, /**< USART1 IR TX Signal. */ +#endif +#if defined(PRS_USART1_RTS) + prsSignalUSART1_RTS = PRS_USART1_RTS, /**< USART1 RTS Signal. */ + prsSignalUSART1_TX = PRS_USART1_TX, /**< USART1 TX Signal. */ + prsSignalUSART1_CS = PRS_USART1_CS, /**< USART1 chip select Signal. */ +#endif +#endif +#if defined(USART2) + prsSignalUSART2_TXC = PRS_USART2_TXC, /**< USART2 TX complete Signal. */ +#if defined(PRS_USART2_RXDATA) + prsSignalUSART2_RXDATA = PRS_USART2_RXDATA, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_RXDATAV) + prsSignalUSART2_RXDATAV = PRS_USART2_RXDATAV, /**< USART2 RX data available Signal. */ +#endif +#if defined(PRS_USART2_IRTX) + prsSignalUSART2_IRTX = PRS_USART2_IRTX, /**< USART2 IR TX Signal. */ +#endif +#if defined(PRS_USART2_RTS) + prsSignalUSART2_RTS = PRS_USART2_RTS, /**< USART2 RTS Signal. */ + prsSignalUSART2_TX = PRS_USART2_TX, /**< USART2 TX Signal. */ + prsSignalUSART2_CS = PRS_USART2_CS, /**< USART2 chip select Signal. */ +#endif +#endif +#if defined(PRS_USART3_TXC) + prsSignalUSART3_TXC = PRS_USART3_TXC, /**< USART3 TX complete Signal. */ + prsSignalUSART3_RXDATAV = PRS_USART3_RXDATAV, /**< USART3 RX data available Signal. */ + prsSignalUSART3_RTS = PRS_USART3_RTS, /**< USART3 RTS Signal. */ + prsSignalUSART3_TX = PRS_USART3_TX, /**< USART3 TX Signal. */ + prsSignalUSART3_CS = PRS_USART3_CS, /**< USART3 chip select Signal. */ +#endif +#if defined(PRS_USART4_TXC) + prsSignalUSART4_TXC = PRS_USART4_TXC, /**< USART4 TX complete Signal. */ + prsSignalUSART4_RXDATAV = PRS_USART4_RXDATAV, /**< USART4 RX data available Signal. */ + prsSignalUSART4_RTS = PRS_USART4_RTS, /**< USART4 RTS Signal. */ + prsSignalUSART4_TX = PRS_USART4_TX, /**< USART4 TX Signal. */ + prsSignalUSART4_CS = PRS_USART4_CS, /**< USART4 chip select Signal. */ +#endif +#if defined(PRS_USART5_TXC) + prsSignalUSART5_TXC = PRS_USART5_TXC, /**< USART5 TX complete Signal. */ + prsSignalUSART5_RXDATAV = PRS_USART5_RXDATAV, /**< USART5 RX data available Signal. */ + prsSignalUSART5_RTS = PRS_USART5_RTS, /**< USART5 RTS Signal. */ + prsSignalUSART5_TX = PRS_USART5_TX, /**< USART5 TX Signal. */ + prsSignalUSART5_CS = PRS_USART5_CS, /**< USART5 chip select Signal. */ +#endif + +#if defined(UART0) + prsSignalUART0_TXC = PRS_UART0_TXC, /**< UART0 TX complete Signal. */ + prsSignalUART0_RXDATAV = PRS_UART0_RXDATAV, /**< UART0 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART0_IRTX = PRS_UART0_IRTX, /**< UART0 IR TX Signal. */ +#endif +#if defined(PRS_UART0_RTS) + prsSignalUART0_RTS = PRS_UART0_RTS, /**< UART0 RTS Signal. */ + prsSignalUART0_TX = PRS_UART0_TX, /**< UART0 TX Signal. */ + prsSignalUART0_CS = PRS_UART0_CS, /**< UART0 chip select Signal. */ +#endif +#endif + +#if defined(UART1) + prsSignalUART1_TXC = PRS_UART1_TXC, /**< UART1 TX complete Signal. */ + prsSignalUART1_RXDATAV = PRS_UART1_RXDATAV, /**< UART1 RX data available Signal. */ +#if defined(PRS_UART1_IRTX) + prsSignalUART1_IRTX = PRS_UART1_IRTX, /**< UART1 IR RX Signal. */ +#endif +#if defined(PRS_UART1_RTS) + prsSignalUART1_RTS = PRS_UART1_RTS, /**< UART1 RTS Signal. */ + prsSignalUART1_TX = PRS_UART1_TX, /**< UART1 RX Signal. */ + prsSignalUART1_CS = PRS_UART1_CS, /**< UART1 chip select Signal. */ +#endif +#endif + +#if defined(PRS_USB_SOF) + prsSignalUSB_SOF = PRS_USB_SOF, /**< USB_SOF Signal. */ + prsSignalUSB_SOFSR = PRS_USB_SOFSR, /**< USB_SOFSR Signal. */ +#endif + +#if defined(PRS_CM4_TXEV) + prsSignalCM4_TXEV = PRS_CM4_TXEV, /**< TXEV Signal. */ +#endif +#if defined(PRS_CM4_ICACHEPCHITSOF) + prsSignalCM4_ICACHEPCHITSOF = PRS_CM4_ICACHEPCHITSOF, /**< ICACHEPCHITSOF Signal. */ + prsSignalCM4_ICACHEPCMISSESOF = PRS_CM4_ICACHEPCMISSESOF, /**< ICACHEPCMISSESOF Signal. */ +#endif + +#if defined(PRS_WTIMER0_UF) + prsSignalWTIMER0_UF = PRS_WTIMER0_UF, /**< WTIMER0_UF Signal. */ + prsSignalWTIMER0_OF = PRS_WTIMER0_OF, /**< WTIMER0_OF Signal. */ + prsSignalWTIMER0_CC0 = PRS_WTIMER0_CC0, /**< WTIMER0_CC0 Signal. */ + prsSignalWTIMER0_CC1 = PRS_WTIMER0_CC1, /**< WTIMER0_CC1 Signal. */ + prsSignalWTIMER0_CC2 = PRS_WTIMER0_CC2, /**< WTIMER0_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER1_UF) + prsSignalWTIMER1_UF = PRS_WTIMER1_UF, /**< WTIMER1_UF Signal. */ + prsSignalWTIMER1_OF = PRS_WTIMER1_OF, /**< WTIMER1_OF Signal. */ + prsSignalWTIMER1_CC0 = PRS_WTIMER1_CC0, /**< WTIMER1_CC0 Signal. */ + prsSignalWTIMER1_CC1 = PRS_WTIMER1_CC1, /**< WTIMER1_CC1 Signal. */ + prsSignalWTIMER1_CC2 = PRS_WTIMER1_CC2, /**< WTIMER1_CC2 Signal. */ + prsSignalWTIMER1_CC3 = PRS_WTIMER1_CC3, /**< WTIMER1_CC3 Signal. */ +#endif +#if defined(PRS_WTIMER2_UF) + prsSignalWTIMER2_UF = PRS_WTIMER2_UF, /**< WTIMER2_UF Signal. */ + prsSignalWTIMER2_OF = PRS_WTIMER2_OF, /**< WTIMER2_OF Signal. */ + prsSignalWTIMER2_CC0 = PRS_WTIMER2_CC0, /**< WTIMER2_CC0 Signal. */ + prsSignalWTIMER2_CC1 = PRS_WTIMER2_CC1, /**< WTIMER2_CC1 Signal. */ + prsSignalWTIMER2_CC2 = PRS_WTIMER2_CC2, /**< WTIMER2_CC2 Signal. */ +#endif +#if defined(PRS_WTIMER3_UF) + prsSignalWTIMER3_UF = PRS_WTIMER3_UF, /**< WTIMER3_UF Signal. */ + prsSignalWTIMER3_OF = PRS_WTIMER3_OF, /**< WTIMER3_OF Signal. */ + prsSignalWTIMER3_CC0 = PRS_WTIMER3_CC0, /**< WTIMER3_CC0 Signal. */ + prsSignalWTIMER3_CC1 = PRS_WTIMER3_CC1, /**< WTIMER3_CC1 Signal. */ + prsSignalWTIMER3_CC2 = PRS_WTIMER3_CC2, /**< WTIMER3_CC2 Signal. */ +#endif + +/* EUSART Signals */ +#if defined(EUSART0) + prsSignalEUSART0_CS = PRS_EUSART0L_CS, /**< EUSART0 chip select Signal. */ + prsSignalEUSART0_IRTX = PRS_EUSART0L_IRDATX, /**< EUSART0 IR RX Signal. */ + prsSignalEUSART0_RTS = PRS_EUSART0L_RTS, /**< EUSART0 RTS Signal. */ + prsSignalEUSART0_RXDATA = PRS_EUSART0L_RXDATAV, /**< EUSART0 RX data available Signal. */ + prsSignalEUSART0_TX = PRS_EUSART0L_TX, /**< EUSART0 TX Signal. */ + prsSignalEUSART0_TXC = PRS_EUSART0L_TXC, /**< EUSART0 TX complete Signal. */ + prsSignalEUSART0_RXFL = PRS_EUSART0L_RXFL, /**< EUSART0 rxfl Signal. */ + prsSignalEUSART0_TXFL = PRS_EUSART0L_TXFL, /**< EUSART0 txfl Signal. */ +#endif +#if defined(EUSART1) + prsSignalEUSART1_CS = PRS_EUSART1L_CS, /**< EUSART1 chip select Signal. */ + prsSignalEUSART1_IRTX = PRS_EUSART1L_IRDATX, /**< EUSART1 IR TX Signal. */ + prsSignalEUSART1_RTS = PRS_EUSART1L_RTS, /**< EUSART1 RTS Signal. */ + prsSignalEUSART1_RXDATA = PRS_EUSART1L_RXDATAV, /**< EUSART1 RX data available Signal. */ + prsSignalEUSART1_TX = PRS_EUSART1L_TX, /**< EUSART1 TX Signal. */ + prsSignalEUSART1_TXC = PRS_EUSART1L_TXC, /**< EUSART1 TX complete Signal. */ + prsSignalEUSART1_RXFL = PRS_EUSART1L_RXFL, /**< EUSART1 rxfl Signal. */ + prsSignalEUSART1_TXFL = PRS_EUSART1L_TXFL, /**< EUSART1 txfl Signal. */ +#endif +#if defined(EUSART2) +#if defined(PRS_EUSART2L_CS) + prsSignalEUSART2_CS = PRS_EUSART2L_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2L_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2L_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2L_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2L_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2L_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2L_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2L_TXFL, /**< EUSART2 txfl Signal. */ +#else + prsSignalEUSART2_CS = PRS_EUSART2_CS, /**< EUSART2 chip select Signal. */ + prsSignalEUSART2_IRTX = PRS_EUSART2_IRDATX, /**< EUSART2 IR TX Signal. */ + prsSignalEUSART2_RTS = PRS_EUSART2_RTS, /**< EUSART2 RTS Signal. */ + prsSignalEUSART2_RXDATA = PRS_EUSART2_RXDATAV, /**< EUSART2 RX data available Signal. */ + prsSignalEUSART2_TX = PRS_EUSART2_TX, /**< EUSART2 TX Signal. */ + prsSignalEUSART2_TXC = PRS_EUSART2_TXC, /**< EUSART2 TX complete Signal. */ + prsSignalEUSART2_RXFL = PRS_EUSART2_RXFL, /**< EUSART2 rxfl Signal. */ + prsSignalEUSART2_TXFL = PRS_EUSART2_TXFL, /**< EUSART2 txfl Signal. */ +#endif +#endif +#if defined(EUSART3) +#if defined(PRS_EUSART3L_CS) + prsSignalEUSART3_CS = PRS_EUSART3L_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3L_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3L_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3L_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3L_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3L_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3L_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3L_TXFL, /**< EUSART3 txfl Signal. */ +#else + prsSignalEUSART3_CS = PRS_EUSART3_CS, /**< EUSART3 chip select Signal. */ + prsSignalEUSART3_IRTX = PRS_EUSART3_IRDATX, /**< EUSART3 IR TX Signal. */ + prsSignalEUSART3_RTS = PRS_EUSART3_RTS, /**< EUSART3 RTS Signal. */ + prsSignalEUSART3_RXDATA = PRS_EUSART3_RXDATAV, /**< EUSART3 RX data available Signal. */ + prsSignalEUSART3_TX = PRS_EUSART3_TX, /**< EUSART3 TX Signal. */ + prsSignalEUSART3_TXC = PRS_EUSART3_TXC, /**< EUSART3 TX complete Signal. */ + prsSignalEUSART3_RXFL = PRS_EUSART3_RXFL, /**< EUSART3 rxfl Signal. */ + prsSignalEUSART3_TXFL = PRS_EUSART3_TXFL, /**< EUSART3 txfl Signal. */ +#endif +#endif +#if defined(EUSART4) + prsSignalEUSART4_CS = PRS_EUSART4L_CS, /**< EUSART4 chip select Signal. */ + prsSignalEUSART4_IRTX = PRS_EUSART4L_IRDATX, /**< EUSART4 IR TX Signal. */ + prsSignalEUSART4_RTS = PRS_EUSART4L_RTS, /**< EUSART4 RTS Signal. */ + prsSignalEUSART4_RXDATA = PRS_EUSART4L_RXDATAV, /**< EUSART4 RX data available Signal. */ + prsSignalEUSART4_TX = PRS_EUSART4L_TX, /**< EUSART4 TX Signal. */ + prsSignalEUSART4_TXC = PRS_EUSART4L_TXC, /**< EUSART4 TX complete Signal. */ + prsSignalEUSART4_RXFL = PRS_EUSART4L_RXFL, /**< EUSART4 rxfl Signal. */ + prsSignalEUSART4_TXFL = PRS_EUSART4L_TXFL, /**< EUSART4 txfl Signal. */ +#endif + /* ADC Signals */ +#if defined(IADC0) + prsSignalIADC0_SCANENTRY = PRS_IADC0_SCANENTRYDONE, /**< IADC0 scan entry Signal. */ + prsSignalIADC0_SCANTABLE = PRS_IADC0_SCANTABLEDONE, /**< IADC0 scan table Signal. */ + prsSignalIADC0_SINGLE = PRS_IADC0_SINGLEDONE, /**< IADC0 single Signal. */ +#endif + + /* GPIO pin Signals */ + prsSignalGPIO_PIN0 = PRS_GPIO_PIN0, /**< GPIO Pin 0 Signal. */ + prsSignalGPIO_PIN1 = PRS_GPIO_PIN1, /**< GPIO Pin 1 Signal. */ + prsSignalGPIO_PIN2 = PRS_GPIO_PIN2, /**< GPIO Pin 2 Signal. */ + prsSignalGPIO_PIN3 = PRS_GPIO_PIN3, /**< GPIO Pin 3 Signal. */ + prsSignalGPIO_PIN4 = PRS_GPIO_PIN4, /**< GPIO Pin 4 Signal. */ + prsSignalGPIO_PIN5 = PRS_GPIO_PIN5, /**< GPIO Pin 5 Signal. */ + prsSignalGPIO_PIN6 = PRS_GPIO_PIN6, /**< GPIO Pin 6 Signal. */ + prsSignalGPIO_PIN7 = PRS_GPIO_PIN7, /**< GPIO Pin 7 Signal. */ +#if defined(PRS_GPIO_PIN15) + prsSignalGPIO_PIN8 = PRS_GPIO_PIN8, /**< GPIO Pin 8 Signal. */ + prsSignalGPIO_PIN9 = PRS_GPIO_PIN9, /**< GPIO Pin 9 Signal. */ + prsSignalGPIO_PIN10 = PRS_GPIO_PIN10, /**< GPIO Pin 10 Signal. */ + prsSignalGPIO_PIN11 = PRS_GPIO_PIN11, /**< GPIO Pin 11 Signal. */ + prsSignalGPIO_PIN12 = PRS_GPIO_PIN12, /**< GPIO Pin 12 Signal. */ + prsSignalGPIO_PIN13 = PRS_GPIO_PIN13, /**< GPIO Pin 13 Signal. */ + prsSignalGPIO_PIN14 = PRS_GPIO_PIN14, /**< GPIO Pin 14 Signal. */ + prsSignalGPIO_PIN15 = PRS_GPIO_PIN15, /**< GPIO Pin 15 Signal. */ +#endif +#if defined(PRS_AGCL_CCA) + prsSignalAGCL_CCA = PRS_AGCL_CCA, /**< AGCL_CCA Signal. */ + prsSignalAGCL_CCAREQ = PRS_AGCL_CCAREQ, /**< AGCL_CCAREQ Signal. */ + prsSignalAGCL_GAINADJUST = PRS_AGCL_GAINADJUST, /**< AGCL_GAINADJUST Signal. */ + prsSignalAGCL_GAINOK = PRS_AGCL_GAINOK, /**< AGCL_GAINOK Signal. */ + prsSignalAGCL_GAINREDUCED = PRS_AGCL_GAINREDUCED, /**< AGCL_GAINREDUCED Signal. */ + prsSignalAGCL_IFPKI1 = PRS_AGCL_IFPKI1, /**< AGCL_IFPKI1 Signal. */ + prsSignalAGCL_IFPKQ2 = PRS_AGCL_IFPKQ2, /**< AGCL_IFPKQ2 Signal. */ + prsSignalAGCL_IFPKRST = PRS_AGCL_IFPKRST, /**< AGCL_IFPKRST Signal. */ +#endif +#if defined(PRS_AGC_PEAKDET) + prsSignalAGC_PEAKDET = PRS_AGC_PEAKDET, /**< AGC_PEAKDET Signal. */ + prsSignalAGC_PROPAGATED = PRS_AGC_PROPAGATED, /**< AGC_PROPAGATED Signal. */ + prsSignalAGC_RSSIDONE = PRS_AGC_RSSIDONE, /**< AGC_RSSIDONE Signal. */ +#endif +#if defined(PRS_BUFC_THR0) + prsSignalBUFC_THR0 = PRS_BUFC_THR0, /**< BUFC_THR0 Signal. */ + prsSignalBUFC_THR1 = PRS_BUFC_THR1, /**< BUFC_THR1 Signal. */ + prsSignalBUFC_THR2 = PRS_BUFC_THR2, /**< BUFC_THR2 Signal. */ + prsSignalBUFC_THR3 = PRS_BUFC_THR3, /**< BUFC_THR3 Signal. */ +#endif +#if defined(PRS_BUFC_CNT0) + prsSignalBUFC_CNT0 = PRS_BUFC_CNT0, /**< BUFC_CNT0 Signal. */ + prsSignalBUFC_CNT1 = PRS_BUFC_CNT1, /**< BUFC_CNT1 Signal. */ + prsSignalBUFC_FULL = PRS_BUFC_FULL, /**< BUFC_FULL Signal. */ +#endif +#if defined(PRS_MODEML_ADVANCE) + prsSignalMODEML_ADVANCE = PRS_MODEML_ADVANCE, /**< MODEML_ADVANCE Signal. */ + prsSignalMODEML_ANT0 = PRS_MODEML_ANT0, /**< MODEML_ANT0 Signal. */ + prsSignalMODEML_ANT1 = PRS_MODEML_ANT1, /**< MODEML_ANT1 Signal. */ + prsSignalMODEML_COHDSADET = PRS_MODEML_COHDSADET, /**< MODEML_COHDSADET Signal. */ + prsSignalMODEML_COHDSALIVE = PRS_MODEML_COHDSALIVE, /**< MODEML_COHDSALIVE Signal. */ + prsSignalMODEML_DCLK = PRS_MODEML_DCLK, /**< MODEML_DCLK Signal. */ + prsSignalMODEML_DOUT = PRS_MODEML_DOUT, /**< MODEML_DOUT Signal. */ + prsSignalMODEML_FRAMEDET = PRS_MODEML_FRAMEDET, /**< MODEML_FRAMEDET Signal. */ +#endif +#if defined(PRS_MODEM_FRAMEDET) + prsSignalMODEM_FRAMEDET = PRS_MODEM_FRAMEDET, /**< MODEM_FRAMEDET Signal. */ + prsSignalMODEM_TIMDET = PRS_MODEM_TIMDET, /**< MODEM_TIMDET Signal. */ + prsSignalMODEM_SYNCSENT = PRS_MODEM_SYNCSENT, /**< MODEM_SYNCSENT Signal. */ + prsSignalMODEM_PRESENT = PRS_MODEM_PRESENT, /**< MODEM_PRESENT Signal. */ + prsSignalMODEM_ANT0 = PRS_MODEM_ANT0, /**< MODEM_ANT0 Signal. */ + prsSignalMODEM_ANT1 = PRS_MODEM_ANT1, /**< MODEM_ANT1 Signal. */ +#endif +#if defined(PRS_MODEM_FRAMESENT) + prsSignalMODEM_FRAMESENT = PRS_MODEM_FRAMESENT, /**< MODEM_FRAMESENT Signal. */ +#endif +#if defined(PRS_MODEM_PREDET) + prsSignalMODEM_PREDET = PRS_MODEM_PREDET, /**< MODEM_PREDET Signal. */ +#endif +#if defined(PRS_MODEM_LRDSADET) + prsSignalMODEM_LRDSADET = PRS_MODEM_LRDSADET, /**< MODEM_LRDSADET Signal. */ + prsSignalMODEM_LRDSALIVE = PRS_MODEM_LRDSALIVE, /**< MODEM_LRDSALIVE Signal. */ +#endif +#if defined(PRS_MODEM_LOWCORR) + prsSignalMODEM_LOWCORR = PRS_MODEM_LOWCORR, /**< MODEM_LOWCORR Signal. */ + prsSignalMODEM_NEWSYMBOL = PRS_MODEM_NEWSYMBOL, /**< MODEM_NEWSYMBOL Signal. */ + prsSignalMODEM_NEWWND = PRS_MODEM_NEWWND, /**< MODEM_NEWWND Signal. */ + prsSignalMODEM_POSTPONE = PRS_MODEM_POSTPONE, /**< MODEM_POSTPONE Signal. */ +#endif +#if defined(PRS_MODEMH_PRESENT) + prsSignalMODEMH_PRESENT = PRS_MODEMH_PRESENT, /**< MODEMH_PRESENT Signal. */ + prsSignalMODEMH_RSSIJUMP = PRS_MODEMH_RSSIJUMP, /**< MODEMH_RSSIJUMP Signal. */ + prsSignalMODEMH_SYNCSENT = PRS_MODEMH_SYNCSENT, /**< MODEMH_SYNCSENT Signal. */ + prsSignalMODEMH_TIMDET = PRS_MODEMH_TIMDET, /**< MODEMH_TIMDET Signal. */ + prsSignalMODEMH_WEAK = PRS_MODEMH_WEAK, /**< MODEMH_WEAK Signal. */ + prsSignalMODEMH_EOF = PRS_MODEMH_EOF, /**< MODEMH_EOF Signal. */ +#endif +#if defined(PRS_MODEMH_SI) + prsSignalMODEMH_SI = PRS_MODEMH_SI, /**< MODEMH_SI Signal. */ +#endif +#if defined(PRS_FRC_DCLK) + prsSignalFRC_DCLK = PRS_FRC_DCLK, /**< FRC_DCLK Signal. */ + prsSignalFRC_DOUT = PRS_FRC_DOUT, /**< FRC_DOUT Signal. */ +#endif +#if defined(PRS_PROTIMERL_BOF) + prsSignalPROTIMERL_BOF = PRS_PROTIMERL_BOF, /**< PROTIMERL_BOF Signal. */ + prsSignalPROTIMERL_CC0 = PRS_PROTIMERL_CC0, /**< PROTIMERL_CC0 Signal. */ + prsSignalPROTIMERL_CC1 = PRS_PROTIMERL_CC1, /**< PROTIMERL_CC1 Signal. */ + prsSignalPROTIMERL_CC2 = PRS_PROTIMERL_CC2, /**< PROTIMERL_CC2 Signal. */ + prsSignalPROTIMERL_CC3 = PRS_PROTIMERL_CC3, /**< PROTIMERL_CC3 Signal. */ + prsSignalPROTIMERL_CC4 = PRS_PROTIMERL_CC4, /**< PROTIMERL_CC4 Signal. */ + prsSignalPROTIMERL_LBTF = PRS_PROTIMERL_LBTF, /**< PROTIMERL_LBTF Signal. */ + prsSignalPROTIMERL_LBTR = PRS_PROTIMERL_LBTR, /**< PROTIMERL_LBTR Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTR) + prsSignalPROTIMER_LBTR = PRS_PROTIMER_LBTR, /**< PROTIMER_LBTR Signal. */ + prsSignalPROTIMER_LBTF = PRS_PROTIMER_LBTF, /**< PROTIMER_LBTF Signal. */ +#endif +#if defined(PRS_PROTIMER_LBTS) + prsSignalPROTIMER_LBTS = PRS_PROTIMER_LBTS, /**< PROTIMER_LBTS Signal. */ +#endif +#if defined(PRS_PROTIMER_POF) + prsSignalPROTIMER_POF = PRS_PROTIMER_POF, /**< PROTIMER_POF Signal. */ + prsSignalPROTIMER_T0MATCH = PRS_PROTIMER_T0MATCH, /**< PROTIMER_T0MATCH Signal. */ + prsSignalPROTIMER_T0UF = PRS_PROTIMER_T0UF, /**< PROTIMER_T0UF Signal. */ + prsSignalPROTIMER_T1MATCH = PRS_PROTIMER_T1MATCH, /**< PROTIMER_T1MATCH Signal. */ + prsSignalPROTIMER_T1UF = PRS_PROTIMER_T1UF, /**< PROTIMER_T1UF Signal. */ + prsSignalPROTIMER_WOF = PRS_PROTIMER_WOF, /**< PROTIMER_WOF Signal. */ +#endif +#if defined(PRS_RAC_ACTIVE) + prsSignalRAC_ACTIVE = PRS_RAC_ACTIVE, /**< RAC_ACTIVE Signal. */ + prsSignalRAC_LNAEN = PRS_RAC_LNAEN, /**< RAC_LNAEN Signal. */ + prsSignalRAC_PAEN = PRS_RAC_PAEN, /**< RAC_PAEN Signal. */ + prsSignalRAC_RX = PRS_RAC_RX, /**< RAC_RX Signal. */ + prsSignalRAC_TX = PRS_RAC_TX, /**< RAC_TX Signal. */ +#endif +#if defined(PRS_RACL_ACTIVE) + prsSignalRACL_ACTIVE = PRS_RACL_ACTIVE, /**< RACL_ACTIVE Signal. */ + prsSignalRACL_LNAEN = PRS_RACL_LNAEN, /**< RACL_LNAEN Signal. */ + prsSignalRACL_PAEN = PRS_RACL_PAEN, /**< RACL_PAEN Signal. */ + prsSignalRACL_RX = PRS_RACL_RX, /**< RACL_RX Signal. */ + prsSignalRACL_TX = PRS_RACL_TX, /**< RACL_TX Signal. */ + prsSignalRACL_CTIOUT0 = PRS_RACL_CTIOUT0, /**< RACL_CTIOUT0 Signal. */ + prsSignalRACL_CTIOUT1 = PRS_RACL_CTIOUT1, /**< RACL_CTIOUT1 Signal. */ + prsSignalRACL_CTIOUT2 = PRS_RACL_CTIOUT2, /**< RACL_CTIOUT2 Signal. */ +#endif +#if defined(PRS_RAC_CTIOUT3) + prsSignalRAC_CTIOUT3 = PRS_RAC_CTIOUT3, /**< RAC_CTIOUT3 Signal. */ +#endif +#if defined(PRS_RAC_AUXADCDATA) + prsSignalRAC_AUXADCDATA = PRS_RAC_AUXADCDATA, /**< RAC_AUXADCDATA Signal. */ + prsSignalRAC_AUXADCDATAVALID = PRS_RAC_AUXADCDATAVALID, /**< RAC_AUXADCDATAVALID Signal. */ +#endif +#if defined(PRS_SYNTH_MUX0) + prsSignalSYNTH_MUX0 = PRS_SYNTH_MUX0, /**< SYNTH_MUX0 Signal. */ + prsSignalSYNTH_MUX1 = PRS_SYNTH_MUX1, /**< SYNTH_MUX1 Signal. */ +#endif +#if defined(PRS_PRORTC_CCV0) + prsSignalPRORTC_CCV0 = PRS_PRORTC_CCV0, /**< PRORTC_CCV0 Signal. */ + prsSignalPRORTC_CCV1 = PRS_PRORTC_CCV1, /**< PRORTC_CCV1 Signal. */ +#endif +#if defined(RFFPLL0) + prsSignalRFFPLL0L_CLKDIGDIV4 = PRS_RFFPLL0L_CLKDIGDIV4, /**< RFFPLL0L CLKDIGDIV4 Signal. */ + prsSignalRFFPLL0L_CLKMODEMDIV4 = PRS_RFFPLL0L_CLKMODEMDIV4, /**< RFFPLL0L CLKMODEMDIV4 Signal. */ +#if defined(PRS_RFFPLL0L_RFBIASFSMSTATE0) + prsSignalRFFPLL0L_RFBIASFSMSTATE0 = PRS_RFFPLL0L_RFBIASFSMSTATE0, /**< RFFPLL0L RFBIASFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE1 = PRS_RFFPLL0L_RFBIASFSMSTATE1, /**< RFFPLL0L RFBIASFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE0 = PRS_RFFPLL0L_RFFPLLFSMSTATE0, /**< RFFPLL0L RFFPLLFSMSTATE0 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE1 = PRS_RFFPLL0L_RFFPLLFSMSTATE1, /**< RFFPLL0L RFFPLLFSMSTATE1 Signal. */ + prsSignalRFFPLL0L_RFFPLLFSMSTATE2 = PRS_RFFPLL0L_RFFPLLFSMSTATE2, /**< RFFPLL0L RFFPLLFSMSTATE2 Signal. */ + prsSignalRFFPLL0L_RFBIASFSMSTATE2 = PRS_RFFPLL0L_RFBIASFSMSTATE2, /**< RFFPLL0L RFBIASFSMSTATE2 Signal. */ + prsSignalRFFPLL0_RFFPLLFSMSTATE3 = PRS_RFFPLL0_RFFPLLFSMSTATE3, /**< RFFPLL0 RFFPLLFSMSTATE3 Signal. */ +#endif +#endif +#if defined(FEFILT0) + prsSignalFEFILT0_REMPTY = PRS_FEFILT0_REMPTY, /**< FEFILT0 REMPTY Signal. */ + prsSignalFEFILT0_WFULL = PRS_FEFILT0_WFULL, /**< FEFILT0 WFULL Signal. */ +#endif +#if defined(FEFILT0) + prsSignalFEFILT1_REMPTY = PRS_FEFILT1_REMPTY, /**< FEFILT1 REMPTY Signal. */ + prsSignalFEFILT1_WFULL = PRS_FEFILT1_WFULL, /**< FEFILT1 WFULL Signal. */ +#endif +#if defined(ETAMPDET) + prsSignalETAMPDET_TAMPERSRCETAMPDET = PRS_ETAMPDET_TAMPERSRCETAMPDET, /**< ETAMPDET TAMPERSRCETAMPDET Signal. */ +#endif +#if defined(SMCTRL) + prsSignalSMCTRLL_SOFTM0 = PRS_SMCTRLL_SOFTM0, /**< SMCTRLL SOFTM0 Signal. */ + prsSignalSMCTRLL_SOFTM1 = PRS_SMCTRLL_SOFTM1, /**< SMCTRLL SOFTM1 Signal. */ + prsSignalSMCTRLL_SOFTM2 = PRS_SMCTRLL_SOFTM2, /**< SMCTRLL SOFTM2 Signal. */ + prsSignalSMCTRLL_SOFTM3 = PRS_SMCTRLL_SOFTM3, /**< SMCTRLL SOFTM3 Signal. */ + prsSignalSMCTRLL_SOFTM4 = PRS_SMCTRLL_SOFTM4, /**< SMCTRLL SOFTM4 Signal. */ + prsSignalSMCTRLL_SOFTM5 = PRS_SMCTRLL_SOFTM5, /**< SMCTRLL SOFTM5 Signal. */ + prsSignalSMCTRLL_SOFTM6 = PRS_SMCTRLL_SOFTM6, /**< SMCTRLL SOFTM6 Signal. */ + prsSignalSMCTRLL_SOFTM7 = PRS_SMCTRLL_SOFTM7, /**< SMCTRLL SOFTM7 Signal. */ + prsSignalSMCTRL_SOFTM8 = PRS_SMCTRL_SOFTM8, /**< SMCTRL SOFTM8 Signal. */ + prsSignalSMCTRL_SOFTM9 = PRS_SMCTRL_SOFTM9, /**< SMCTRL SOFTM9 Signal. */ + prsSignalSMCTRL_SOFTM10 = PRS_SMCTRL_SOFTM10, /**< SMCTRL SOFTM10 Signal. */ + prsSignalSMCTRL_SOFTM11 = PRS_SMCTRL_SOFTM11, /**< SMCTRL SOFTM11 Signal. */ +#endif +#if defined(PRS_SEHFRCO_COREEN) + prsSignalSEHFRCO_COREEN = PRS_SEHFRCO_COREEN, /**< SEHFRCO COREEN Signal. */ + prsSignalSEHFRCO_STATE0 = PRS_SEHFRCO_STATE0, /**< SEHFRCO STATE0 Signal. */ + prsSignalSEHFRCO_STATE1 = PRS_SEHFRCO_STATE1, /**< SEHFRCO STATE1 Signal. */ + prsSignalSEHFRCO_STATE2 = PRS_SEHFRCO_STATE2, /**< SEHFRCO STATE2 Signal. */ +#endif +#if defined(PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY) + prsSignalSEATAMPDET_SEATAMPDETSUPTPDELAY = PRS_SEATAMPDET_SEATAMPDETSUPTPDELAY, /**< SEATAMPDET SEATAMPDETSUPTPDELAY Signal. */ +#endif +#if defined(PRS_DCDC_MONO70NSANA) + prsSignalDCDC_MONO70NSANA = PRS_DCDC_MONO70NSANA, /** DCDC Pulses for Coulomb Counter Calibration Signal. */ +#endif +#if defined(PRS_LFRCO_CALMEAS) + prsSignalLFRCO_CALMEAS = PRS_LFRCO_CALMEAS, /** LFRCO Calibration Measure Signal. */ + prsSignalLFRCO_SDM = PRS_LFRCO_SDM, /** LFRCO Sigma Delta Modulator output Signal. */ + prsSignalLFRCO_TCMEAS = PRS_LFRCO_TCMEAS, /** LFRCO Temperature Check Measure Signal. */ +#endif +} PRS_Signal_t; + +#if defined(_SILICON_LABS_32B_SERIES_2) +/** PRS Consumers. */ +typedef enum { + prsConsumerNone = 0x000, /**< No PRS consumer */ + prsConsumerCMU_CALDN = offsetof(PRS_TypeDef, CONSUMER_CMU_CALDN), /**< CMU calibration down consumer. */ + prsConsumerCMU_CALUP = offsetof(PRS_TypeDef, CONSUMER_CMU_CALUP), /**< CMU calibration up consumer. */ +#if defined(IADC_PRESENT) + prsConsumerIADC0_SCANTRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SCANTRIGGER), /**< IADC0 scan trigger consumer. */ + prsConsumerIADC0_SINGLETRIGGER = offsetof(PRS_TypeDef, CONSUMER_IADC0_SINGLETRIGGER), /**< IADC0 single trigger consumer. */ +#endif + prsConsumerLDMA_REQUEST0 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ0), /**< LDMA Request 0 consumer. */ + prsConsumerLDMA_REQUEST1 = offsetof(PRS_TypeDef, CONSUMER_LDMAXBAR_DMAREQ1), /**< LDMA Request 1 consumer. */ +#if defined(LETIMER0) + prsConsumerLETIMER0_CLEAR = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_CLEAR), /**< LETIMER0 clear consumer. */ + prsConsumerLETIMER0_START = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_START), /**< LETIMER0 start consumer. */ + prsConsumerLETIMER0_STOP = offsetof(PRS_TypeDef, CONSUMER_LETIMER0_STOP), /**< LETIMER0 stop consumer. */ +#endif + prsConsumerTIMER0_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC0), /**< TIMER0 capture/compare channel 0 consumer. */ + prsConsumerTIMER0_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC1), /**< TIMER0 capture/compare channel 1 consumer. */ + prsConsumerTIMER0_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER0_CC2), /**< TIMER0 capture/compare channel 2 consumer. */ + prsConsumerTIMER1_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC0), /**< TIMER1 capture/compare channel 0 consumer. */ + prsConsumerTIMER1_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC1), /**< TIMER1 capture/compare channel 1 consumer. */ + prsConsumerTIMER1_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER1_CC2), /**< TIMER1 capture/compare channel 2 consumer. */ + prsConsumerTIMER2_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC0), /**< TIMER2 capture/compare channel 0 consumer. */ + prsConsumerTIMER2_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC1), /**< TIMER2 capture/compare channel 1 consumer. */ + prsConsumerTIMER2_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER2_CC2), /**< TIMER2 capture/compare channel 2 consumer. */ + prsConsumerTIMER3_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC0), /**< TIMER3 capture/compare channel 0 consumer. */ + prsConsumerTIMER3_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC1), /**< TIMER3 capture/compare channel 1 consumer. */ + prsConsumerTIMER3_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER3_CC2), /**< TIMER3 capture/compare channel 2 consumer. */ +#if defined(TIMER4) + prsConsumerTIMER4_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC0), /**< TIMER4 capture/compare channel 0 consumer. */ + prsConsumerTIMER4_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC1), /**< TIMER4 capture/compare channel 1 consumer. */ + prsConsumerTIMER4_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER4_CC2), /**< TIMER4 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER5) + prsConsumerTIMER5_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC0), /**< TIMER5 capture/compare channel 0 consumer. */ + prsConsumerTIMER5_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC1), /**< TIMER5 capture/compare channel 1 consumer. */ + prsConsumerTIMER5_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER5_CC2), /**< TIMER5 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER6) + prsConsumerTIMER6_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC0), /**< TIMER6 capture/compare channel 0 consumer. */ + prsConsumerTIMER6_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC1), /**< TIMER6 capture/compare channel 1 consumer. */ + prsConsumerTIMER6_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER6_CC2), /**< TIMER6 capture/compare channel 2 consumer. */ +#endif +#if defined(TIMER7) + prsConsumerTIMER7_CC0 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC0), /**< TIMER7 capture/compare channel 0 consumer. */ + prsConsumerTIMER7_CC1 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC1), /**< TIMER7 capture/compare channel 1 consumer. */ + prsConsumerTIMER7_CC2 = offsetof(PRS_TypeDef, CONSUMER_TIMER7_CC2), /**< TIMER7 capture/compare channel 2 consumer. */ +#endif +#if defined(USART0) + prsConsumerUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_USART0_CLK), /**< USART0 clock consumer. */ + prsConsumerUSART0_IR = offsetof(PRS_TypeDef, CONSUMER_USART0_IR), /**< USART0 IR consumer. */ + prsConsumerUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_USART0_RX), /**< USART0 RX consumer. */ + prsConsumerUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART0_TRIGGER), /**< USART0 trigger consumer. */ +#endif +#if defined(USART1) + prsConsumerUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_USART1_CLK), /**< USART1 clock consumer. */ + prsConsumerUSART1_IR = offsetof(PRS_TypeDef, CONSUMER_USART1_IR), /**< USART1 IR consumer. */ + prsConsumerUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_USART1_RX), /**< USART1 TX consumer. */ + prsConsumerUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART1_TRIGGER), /**< USART1 trigger consumer. */ +#endif +#if defined(USART2) + prsConsumerUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_USART2_CLK), /**< USART2 clock consumer. */ + prsConsumerUSART2_IR = offsetof(PRS_TypeDef, CONSUMER_USART2_IR), /**< USART2 IR consumer. */ + prsConsumerUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_USART2_RX), /**< USART2 RX consumer. */ + prsConsumerUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_USART2_TRIGGER), /**< USART2 trigger consumer. */ +#endif +#if defined(EUSART0) + prsConsumerEUSART0_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART0_CLK), /**< EUSART0 clk consumer. */ + prsConsumerEUSART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART0_RX), /**< EUSART0 RX consumer. */ + prsConsumerEUSART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART0_TRIGGER), /**< EUSART0 trigger consumer. */ +#endif +#if defined(EUSART1) + prsConsumerEUSART1_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART1_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART1_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART1_RX), /**< EUSART1 RX consumer. */ + prsConsumerEUSART1_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART1_TRIGGER), /**< EUSART1 trigger consumer. */ +#endif +#if defined(EUSART2) + prsConsumerEUSART2_CLK = offsetof(PRS_TypeDef, CONSUMER_EUSART2_CLK), /**< EUSART1 clk consumer. */ + prsConsumerEUSART2_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART2_RX), /**< EUSART2 RX consumer. */ + prsConsumerEUSART2_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART2_TRIGGER), /**< EUSART2 trigger consumer. */ +#endif +#if defined(EUSART3) + prsConsumerEUSART3_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART3_RX), /**< EUSART3 RX consumer. */ + prsConsumerEUSART3_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART3_TRIGGER), /**< EUSART3 trigger consumer. */ +#endif +#if defined(EUSART4) + prsConsumerEUSART4_RX = offsetof(PRS_TypeDef, CONSUMER_EUSART4_RX), /**< EUSART4 RX consumer. */ + prsConsumerEUSART4_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUSART4_TRIGGER), /**< EUSART4 trigger consumer. */ +#endif +#if defined(EUART0) + prsConsumerEUART0_RX = offsetof(PRS_TypeDef, CONSUMER_EUART0_RX), /**< EUART0 RX consumer. */ + prsConsumerEUART0_TRIGGER = offsetof(PRS_TypeDef, CONSUMER_EUART0_TRIGGER), /**< EUART0 TRIGGER Consumer. */ +#endif + prsConsumerWDOG0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC0), /**< WDOG0 source 0 consumer. */ + prsConsumerWDOG0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG0_SRC1), /**< WDOG0 source 1 consumer. */ +#if defined(WDOG1) + prsConsumerWDOG1_SRC0 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC0), /**< WDOG1 source 0 consumer. */ + prsConsumerWDOG1_SRC1 = offsetof(PRS_TypeDef, CONSUMER_WDOG1_SRC1), /**< WDOG1 source 1 consumer. */ +#endif +#if defined(PCNT0) + prsConsumerPCNT0_IN0 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S0IN), /**< PCNT0 input 0 consumer. */ + prsConsumerPCNT0_IN1 = offsetof(PRS_TypeDef, CONSUMER_PCNT0_S1IN), /**< PCNT0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_RTCC_CC2_MASK) + prsConsumerRTCC_CC0 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC0), /**< RTCC capture/compare channel 0 consumer. */ + prsConsumerRTCC_CC1 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC1), /**< RTCC capture/compare channel 1 consumer. */ + prsConsumerRTCC_CC2 = offsetof(PRS_TypeDef, CONSUMER_RTCC_CC2), /**< RTCC capture/compare channel 2 consumer. */ +#endif +#if defined(SYSRTC0) + prsConsumerSYSRTC0_SRC0 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN0), /**< SYSRTC0 input 0 consumer. */ + prsConsumerSYSRTC0_SRC1 = offsetof(PRS_TypeDef, CONSUMER_SYSRTC0_IN1), /**< SYSRTC0 input 1 consumer. */ +#endif +#if defined(_PRS_CONSUMER_HFXO0_OSCREQ_MASK) + prsConsumerHFXO0_OSCREQ = offsetof(PRS_TypeDef, CONSUMER_HFXO0_OSCREQ), /**< OSCREQ consumer. */ + prsConsumerHFXO0_TIMEOUT = offsetof(PRS_TypeDef, CONSUMER_HFXO0_TIMEOUT), /**< HFXO0_TIMEOUT consumer. */ +#endif +#if defined(LESENSE) + prsConsumerLESENSE_START = offsetof(PRS_TypeDef, CONSUMER_LESENSE_START), /**< LESENSE_START consumer. */ +#endif +#if defined(VDAC0) + prsConsumerVDAC0_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH0), /**< VDAC0 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_ASYNCTRIGCH1), /**< VDAC0 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH0), /**< VDAC0 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC0_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC0_SYNCTRIGCH1), /**< VDAC0 SYNC TRIGER CH1 consumer. */ +#endif +#if defined(VDAC1) + prsConsumerVDAC1_ASYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH0), /**< VDAC1 ASYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_ASYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_ASYNCTRIGCH1), /**< VDAC1 ASYNC TRIGER CH1 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH0 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH0), /**< VDAC1 SYNC TRIGER CH0 consumer. */ + prsConsumerVDAC1_SYNCTRIGCH1 = offsetof(PRS_TypeDef, CONSUMER_VDAC1_SYNCTRIGCH1), /**< VDAC1 SYNC TRIGER CH1 consumer. */ +#endif +} PRS_Consumer_t; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set level control bit for one or more channels. + * + * @details + * The level value for a channel is XORed with both the pulse possibly issued + * by PRS_PulseTrigger() and the PRS input signal selected for the channel(s). + * + * @cond DOXYDOC_S2_DEVICE + * @note + * Note that software level control is only available for asynchronous + * channels on Series 2 devices. + * @endcond + * + * @param[in] level + * Level to use for channels indicated by @p mask. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines for channels to set high level, otherwise 0. + * + * @param[in] mask + * Mask indicating which channels to set level for. Use logical OR combination + * of PRS_SWLEVEL_CHnLEVEL defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_LevelSet(uint32_t level, uint32_t mask) +{ +#if defined(_PRS_SWLEVEL_MASK) + PRS->SWLEVEL = (PRS->SWLEVEL & ~mask) | (level & mask); +#else + PRS->ASYNC_SWLEVEL = (PRS->ASYNC_SWLEVEL & ~mask) | (level & mask); +#endif +} + +/***************************************************************************//** + * @brief + * Get level control bit for all channels. + * + * @return + * The current software level configuration. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_LevelGet(void) +{ +#if defined(_PRS_SWLEVEL_MASK) + return PRS->SWLEVEL; +#else + return PRS->ASYNC_SWLEVEL; +#endif +} + +#if defined(_PRS_ASYNC_PEEK_MASK) || defined(_PRS_PEEK_MASK) +/***************************************************************************//** + * @brief + * Get the PRS channel values for all channels. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output values for all channels as a bitset. + ******************************************************************************/ +__STATIC_INLINE uint32_t PRS_Values(PRS_ChType_t type) +{ +#if defined(_PRS_ASYNC_PEEK_MASK) + if (type == prsTypeAsync) { + return PRS->ASYNC_PEEK; + } else { + return PRS->SYNC_PEEK; + } +#else + (void) type; + return PRS->PEEK; +#endif +} + +/***************************************************************************//** + * @brief + * Get the PRS channel value for a single channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * The current PRS channel output value. This is either 0 or 1. + ******************************************************************************/ +__STATIC_INLINE bool PRS_ChannelValue(unsigned int ch, PRS_ChType_t type) +{ + return (0UL != ((PRS_Values(type) >> ch) & 0x1U)); +} +#endif + +/***************************************************************************//** + * @brief + * Trigger a high pulse (one HFPERCLK) for one or more channels. + * + * @details + * Setting a bit for a channel causes the bit in the register to remain high + * for one HFPERCLK cycle. Pulse is XORed with both the corresponding bit + * in PRS SWLEVEL register and the PRS input signal selected for the + * channel(s). + * + * @param[in] channels + * Logical ORed combination of channels to trigger a pulse for. Use + * PRS_SWPULSE_CHnPULSE defines. + ******************************************************************************/ +__STATIC_INLINE void PRS_PulseTrigger(uint32_t channels) +{ +#if defined(_PRS_SWPULSE_MASK) + PRS->SWPULSE = channels & _PRS_SWPULSE_MASK; +#else + PRS->ASYNC_SWPULSE = channels & _PRS_ASYNC_SWPULSE_MASK; +#endif +} + +/***************************************************************************//** + * @brief + * Set the PRS channel level for one asynchronous PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] level + * true to set the level high (1) and false to set the level low (0). + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelLevelSet(unsigned int ch, bool level) +{ + PRS_LevelSet((uint32_t) level << ch, 0x1UL << ch); +} + +/***************************************************************************//** + * @brief + * Trigger a pulse on one PRS channel. + * + * @param[in] ch + * PRS channel number. + ******************************************************************************/ +__STATIC_INLINE void PRS_ChannelPulse(unsigned int ch) +{ + PRS_PulseTrigger(0x1UL << ch); +} + +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge); + +#if defined(PRS_ASYNC_SUPPORTED) +void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal); +#endif +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location); +#endif + +int PRS_GetFreeChannel(PRS_ChType_t type); +void PRS_Reset(void); +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal); +#if defined(_SILICON_LABS_32B_SERIES_2) +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource); +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal); +void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer); +void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin); +void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic); +#endif + +/** @} (end addtogroup prs) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ +#endif /* EM_PRS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h index 1fc99a0..35243a0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_ramfunc.h @@ -1,167 +1,167 @@ -/***************************************************************************//** - * @file - * @brief RAM code support. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_RAMFUNC_H -#define EM_RAMFUNC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* *INDENT-OFF* */ -/***************************************************************************//** - * @addtogroup ramfunc RAMFUNC - RAM Function Support - * @brief RAM code support - * @details - * Provides support for executing code from RAM. - * Provides a unified method to manage RAM code across all supported tools. - * @{ - - @note - Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common). - - @note - Functions executing from RAM should not be declared as static. - - @warning - Standard library facilities are available to the tool with GCC in hosted - mode (default), regardless of the section attribute. Calls to standard - libraries placed in the default section may therefore occur. To disable - hosted mode, add '-ffreestanding' to the build command line. This is the - only way to guarantee no calls to standard libraries with GCC. - Read more at www.gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html - - @warning - Keil/ARM uVision users must add a section named "ram_code" in their linker - scatter file. This section must be in RAM memory. Look in the MCU SDK for - example scatter files (ram_code.sct). - - @n @section ramfunc_usage Usage - - In your .h file: - @verbatim - #include "em_ramfunc.h" - - SL_RAMFUNC_DECLARATOR - void MyPrint(const char* string); - @endverbatim - - Issues have been observed with ARM GCC when there is no declarator. It is - recommended to have a declarator also for internal functions but move the - declarator to the .c file. - - In your .c file: - @verbatim - #include "em_ramfunc.h" - - SL_RAMFUNC_DEFINITION_BEGIN - void MyPrint(const char* string) - { - ... - } - SL_RAMFUNC_DEFINITION_END - @endverbatim - - ******************************************************************************/ -/* *INDENT-ON* */ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -/** - * @brief - * This define is not present by default. By compiling with define - * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros - * will be placed in default code space (Flash) instead. - * - * @note - * This define is not present by default. - */ -#if defined(DOXY_DOC_ONLY) -#define SL_RAMFUNC_DISABLE -#endif - -#if defined(SL_RAMFUNC_DISABLE) -/** @brief Compiler ported function declarator for RAM code. */ -#define SL_RAMFUNC_DECLARATOR - -/** @brief Compiler ported function definition begin marker for RAM code. */ -#define SL_RAMFUNC_DEFINITION_BEGIN - -/** @brief Compiler ported function definition end marker for RAM code. */ -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__CC_ARM) -/* MDK-ARM compiler */ -#define SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") -#define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") - -#elif defined(__ICCARM__) -/* IAR Embedded Workbench */ -#define SL_RAMFUNC_DECLARATOR __ramfunc -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) && (defined(__CROSSWORKS_ARM) || defined(__SES_ARM)) -/* Rowley Crossworks and Segger Embedded Studio */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".fast"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32) -/* Zephyr environment */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#elif defined(__GNUC__) -/* Simplicity Studio, Atollic and Vanilla armgcc */ -#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram"))) -#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR -#define SL_RAMFUNC_DEFINITION_END - -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Deprecated macro names */ -#define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR -#define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN -#define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END -/** @endcond */ - -/** @} (end addtogroup ramfunc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_RAMFUNC_H */ +/***************************************************************************//** + * @file + * @brief RAM code support. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RAMFUNC_H +#define EM_RAMFUNC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* *INDENT-OFF* */ +/***************************************************************************//** + * @addtogroup ramfunc RAMFUNC - RAM Function Support + * @brief RAM code support + * @details + * Provides support for executing code from RAM. + * Provides a unified method to manage RAM code across all supported tools. + * @{ + + @note + Other cross-compiler support macros are implemented in [COMMON](../../common/api/group-common). + + @note + Functions executing from RAM should not be declared as static. + + @warning + Standard library facilities are available to the tool with GCC in hosted + mode (default), regardless of the section attribute. Calls to standard + libraries placed in the default section may therefore occur. To disable + hosted mode, add '-ffreestanding' to the build command line. This is the + only way to guarantee no calls to standard libraries with GCC. + Read more at www.gcc.gnu.org/onlinedocs/gcc-5.3.0/gcc/Standards.html + + @warning + Keil/ARM uVision users must add a section named "ram_code" in their linker + scatter file. This section must be in RAM memory. Look in the MCU SDK for + example scatter files (ram_code.sct). + + @n @section ramfunc_usage Usage + + In your .h file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DECLARATOR + void MyPrint(const char* string); + @endverbatim + + Issues have been observed with ARM GCC when there is no declarator. It is + recommended to have a declarator also for internal functions but move the + declarator to the .c file. + + In your .c file: + @verbatim + #include "em_ramfunc.h" + + SL_RAMFUNC_DEFINITION_BEGIN + void MyPrint(const char* string) + { + ... + } + SL_RAMFUNC_DEFINITION_END + @endverbatim + + ******************************************************************************/ +/* *INDENT-ON* */ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +/** + * @brief + * This define is not present by default. By compiling with define + * @ref SL_RAMFUNC_DISABLE, code placed in RAM by SL_RAMFUNC macros + * will be placed in default code space (Flash) instead. + * + * @note + * This define is not present by default. + */ +#if defined(DOXY_DOC_ONLY) +#define SL_RAMFUNC_DISABLE +#endif + +#if defined(SL_RAMFUNC_DISABLE) +/** @brief Compiler ported function declarator for RAM code. */ +#define SL_RAMFUNC_DECLARATOR + +/** @brief Compiler ported function definition begin marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_BEGIN + +/** @brief Compiler ported function definition end marker for RAM code. */ +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__CC_ARM) +/* MDK-ARM compiler */ +#define SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_BEGIN _Pragma("arm section code=\"ram_code\"") +#define SL_RAMFUNC_DEFINITION_END _Pragma("arm section code") + +#elif defined(__ICCARM__) +/* IAR Embedded Workbench */ +#define SL_RAMFUNC_DECLARATOR __ramfunc +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && (defined(__CROSSWORKS_ARM) || defined(__SES_ARM)) +/* Rowley Crossworks and Segger Embedded Studio */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".fast"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) && defined(CONFIG_SOC_FAMILY_EXX32) +/* Zephyr environment */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ramfunc"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#elif defined(__GNUC__) +/* Simplicity Studio, Atollic and Vanilla armgcc */ +#define SL_RAMFUNC_DECLARATOR __attribute__ ((section(".ram"))) +#define SL_RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DECLARATOR +#define SL_RAMFUNC_DEFINITION_END + +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Deprecated macro names */ +#define RAMFUNC_DECLARATOR SL_RAMFUNC_DECLARATOR +#define RAMFUNC_DEFINITION_BEGIN SL_RAMFUNC_DEFINITION_BEGIN +#define RAMFUNC_DEFINITION_END SL_RAMFUNC_DEFINITION_END +/** @endcond */ + +/** @} (end addtogroup ramfunc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_RAMFUNC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h index 81304c0..d1b1785 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rmu.h @@ -1,178 +1,178 @@ -/***************************************************************************//** - * @file - * @brief Reset Management Unit (RMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_RMU_H -#define EM_RMU_H - -#include "em_device.h" -#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) -#include "sl_assert.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup rmu - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** RMU reset modes. */ -typedef enum { -#if defined(_RMU_CTRL_PINRMODE_MASK) - rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, /**< Reset mode disabled. */ - rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, /**< Reset mode limited. */ - rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, /**< Reset mode extended. */ - rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, /**< Reset mode full. */ -#elif defined(_EMU_RSTCTRL_MASK) - rmuResetModeDisabled = 0, /**< Reset mode disabled. */ - rmuResetModeEnabled = 1, /**< Reset mode enabled. */ -#else - rmuResetModeClear = 0, /**< Reset mode clear. */ - rmuResetModeSet = 1, /**< Reset mode set. */ -#endif -} RMU_ResetMode_TypeDef; - -/** RMU controlled peripheral reset control and reset source control. */ -typedef enum { -#if defined(RMU_CTRL_BURSTEN) - rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ -#endif -#if defined(RMU_CTRL_LOCKUPRDIS) - rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ -#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) - rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ -#endif -#if defined(_RMU_CTRL_WDOGRMODE_MASK) - rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ -#endif -#if defined(_RMU_CTRL_LOCKUPRMODE_MASK) - rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ -#endif -#if defined(_RMU_CTRL_SYSRMODE_MASK) - rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ -#endif -#if defined(_RMU_CTRL_PINRMODE_MASK) - rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ -#endif - -#if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) - rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ -#endif -#if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) - rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ -#endif -#if defined(_EMU_RSTCTRL_SYSRMODE_MASK) - rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ -#endif -#if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) - rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ -#endif -#if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) - rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) - rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD1BODRMODE_MASK) - rmuResetIOVDD1 = _EMU_RSTCTRL_IOVDD1BODRMODE_MASK, /**< IOVDD1 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_IOVDD2BODRMODE_MASK) - rmuResetIOVDD2 = _EMU_RSTCTRL_IOVDD2BODRMODE_MASK, /**< IOVDD2 monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) - rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ -#endif -#if defined(_EMU_RSTCTRL_SESYSRMODE_MASK) - rmuResetSESys = _EMU_RSTCTRL_SESYSRMODE_MASK, /**< M0+ (SE) system reset select */ -#endif -#if defined(_EMU_RSTCTRL_SELOCKUPRMODE_MASK) - rmuResetSELockup = _EMU_RSTCTRL_SELOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ -#endif -#if defined(_EMU_RSTCTRL_DCIRMODE_MASK) - rmuResetDCI = _EMU_RSTCTRL_DCIRMODE_MASK, /**< DCI reset select */ -#endif -} RMU_Reset_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/** RMU_LockupResetDisable kept for backwards compatibility. */ -#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) - -void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); -void RMU_ResetCauseClear(void); -uint32_t RMU_ResetCauseGet(void); - -#if defined(_RMU_CTRL_RESETSTATE_MASK) -/***************************************************************************//** - * @brief - * Set user reset state. Reset only by a Power-on-reset and a pin reset. - * - * @param[in] userState User state to set - ******************************************************************************/ -__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) -{ - EFM_ASSERT(!(userState - & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); - RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) - | (userState << _RMU_CTRL_RESETSTATE_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get user reset state. Reset only by a Power-on-reset and a pin reset. - * - * @return - * Reset surviving user state. - ******************************************************************************/ -__STATIC_INLINE uint32_t RMU_UserResetStateGet(void) -{ - uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) - >> _RMU_CTRL_RESETSTATE_SHIFT; - return userState; -} -#endif - -/** @} (end addtogroup rmu) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ -#endif /* EM_RMU_H */ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RMU_H +#define EM_RMU_H + +#include "em_device.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) +#include "sl_assert.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup rmu + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** RMU reset modes. */ +typedef enum { +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetModeDisabled = _RMU_CTRL_PINRMODE_DISABLED, /**< Reset mode disabled. */ + rmuResetModeLimited = _RMU_CTRL_PINRMODE_LIMITED, /**< Reset mode limited. */ + rmuResetModeExtended = _RMU_CTRL_PINRMODE_EXTENDED, /**< Reset mode extended. */ + rmuResetModeFull = _RMU_CTRL_PINRMODE_FULL, /**< Reset mode full. */ +#elif defined(_EMU_RSTCTRL_MASK) + rmuResetModeDisabled = 0, /**< Reset mode disabled. */ + rmuResetModeEnabled = 1, /**< Reset mode enabled. */ +#else + rmuResetModeClear = 0, /**< Reset mode clear. */ + rmuResetModeSet = 1, /**< Reset mode set. */ +#endif +} RMU_ResetMode_TypeDef; + +/** RMU controlled peripheral reset control and reset source control. */ +typedef enum { +#if defined(RMU_CTRL_BURSTEN) + rmuResetBU = _RMU_CTRL_BURSTEN_MASK, /**< Reset control over Backup Power domain select. */ +#endif +#if defined(RMU_CTRL_LOCKUPRDIS) + rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_MASK, /**< Cortex lockup reset select. */ +#elif defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetLockUp = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_WDOGRMODE_MASK) + rmuResetWdog = _RMU_CTRL_WDOGRMODE_MASK, /**< WDOG reset select. */ +#endif +#if defined(_RMU_CTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _RMU_CTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select. */ +#endif +#if defined(_RMU_CTRL_SYSRMODE_MASK) + rmuResetSys = _RMU_CTRL_SYSRMODE_MASK, /**< SYSRESET select. */ +#endif +#if defined(_RMU_CTRL_PINRMODE_MASK) + rmuResetPin = _RMU_CTRL_PINRMODE_MASK, /**< Pin reset select. */ +#endif + +#if defined(_EMU_RSTCTRL_WDOG0RMODE_MASK) + rmuResetWdog0 = _EMU_RSTCTRL_WDOG0RMODE_MASK, /**< WDOG0 reset select */ +#endif +#if defined(_EMU_RSTCTRL_WDOG1RMODE_MASK) + rmuResetWdog1 = _EMU_RSTCTRL_WDOG1RMODE_MASK, /**< WDOG1 reset select */ +#endif +#if defined(_EMU_RSTCTRL_SYSRMODE_MASK) + rmuResetSys = _EMU_RSTCTRL_SYSRMODE_MASK, /**< SYSRESET select */ +#endif +#if defined(_EMU_RSTCTRL_LOCKUPRMODE_MASK) + rmuResetCoreLockup = _EMU_RSTCTRL_LOCKUPRMODE_MASK, /**< Cortex lockup reset select */ +#endif +#if defined(_EMU_RSTCTRL_AVDDBODRMODE_MASK) + rmuResetAVDD = _EMU_RSTCTRL_AVDDBODRMODE_MASK, /**< AVDD monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD0BODRMODE_MASK) + rmuResetIOVDD0 = _EMU_RSTCTRL_IOVDD0BODRMODE_MASK, /**< IOVDD0 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD1BODRMODE_MASK) + rmuResetIOVDD1 = _EMU_RSTCTRL_IOVDD1BODRMODE_MASK, /**< IOVDD1 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_IOVDD2BODRMODE_MASK) + rmuResetIOVDD2 = _EMU_RSTCTRL_IOVDD2BODRMODE_MASK, /**< IOVDD2 monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_DECBODRMODE_MASK) + rmuResetDecouple = _EMU_RSTCTRL_DECBODRMODE_MASK, /**< Decouple monitoring select */ +#endif +#if defined(_EMU_RSTCTRL_SESYSRMODE_MASK) + rmuResetSESys = _EMU_RSTCTRL_SESYSRMODE_MASK, /**< M0+ (SE) system reset select */ +#endif +#if defined(_EMU_RSTCTRL_SELOCKUPRMODE_MASK) + rmuResetSELockup = _EMU_RSTCTRL_SELOCKUPRMODE_MASK, /**< M0+ (SE) lockup select */ +#endif +#if defined(_EMU_RSTCTRL_DCIRMODE_MASK) + rmuResetDCI = _EMU_RSTCTRL_DCIRMODE_MASK, /**< DCI reset select */ +#endif +} RMU_Reset_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/** RMU_LockupResetDisable kept for backwards compatibility. */ +#define RMU_LockupResetDisable(A) RMU_ResetControl(rmuResetLockUp, A) + +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode); +void RMU_ResetCauseClear(void); +uint32_t RMU_ResetCauseGet(void); + +#if defined(_RMU_CTRL_RESETSTATE_MASK) +/***************************************************************************//** + * @brief + * Set user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @param[in] userState User state to set + ******************************************************************************/ +__STATIC_INLINE void RMU_UserResetStateSet(uint32_t userState) +{ + EFM_ASSERT(!(userState + & ~(_RMU_CTRL_RESETSTATE_MASK >> _RMU_CTRL_RESETSTATE_SHIFT))); + RMU->CTRL = (RMU->CTRL & ~_RMU_CTRL_RESETSTATE_MASK) + | (userState << _RMU_CTRL_RESETSTATE_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get user reset state. Reset only by a Power-on-reset and a pin reset. + * + * @return + * Reset surviving user state. + ******************************************************************************/ +__STATIC_INLINE uint32_t RMU_UserResetStateGet(void) +{ + uint32_t userState = (RMU->CTRL & _RMU_CTRL_RESETSTATE_MASK) + >> _RMU_CTRL_RESETSTATE_SHIFT; + return userState; +} +#endif + +/** @} (end addtogroup rmu) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ +#endif /* EM_RMU_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rtcc.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rtcc.h index 4e91b31..cd83805 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rtcc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_rtcc.h @@ -1,980 +1,980 @@ -/***************************************************************************//** - * @file - * @brief Real Time Counter (RTCC) peripheral API. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_RTCC_H -#define EM_RTCC_H - -#include "em_device.h" -#if defined(RTCC_COUNT) && (RTCC_COUNT == 1) - -#include -#include "sl_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup rtcc - * @{ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) -/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC - * Registers". */ -#define ERRATA_FIX_RTCC_E203 -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) -/* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra - * current". */ -#define ERRATA_FIX_RTCC_E204 -#endif -/** @endcond */ - -/******************************************************************************* - ********************************* ENUM ************************************ - ******************************************************************************/ - -#if defined (_RTCC_CTRL_CNTMODE_MASK) -/** Operational mode of the counter. */ -typedef enum { - /** Normal counter mode. The counter is incremented by 1 for each tick. */ - rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL, - - /** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more - * details on the calendar mode. */ - rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR -} RTCC_CntMode_TypeDef; -#endif - -/** Counter prescaler selection. */ -#if defined (_RTCC_CTRL_CNTPRESC_DIV1) -typedef enum { - rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */ - rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */ - rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */ - rtccCntPresc_8 = _RTCC_CTRL_CNTPRESC_DIV8, /**< Divide clock by 8. */ - rtccCntPresc_16 = _RTCC_CTRL_CNTPRESC_DIV16, /**< Divide clock by 16. */ - rtccCntPresc_32 = _RTCC_CTRL_CNTPRESC_DIV32, /**< Divide clock by 32. */ - rtccCntPresc_64 = _RTCC_CTRL_CNTPRESC_DIV64, /**< Divide clock by 64. */ - rtccCntPresc_128 = _RTCC_CTRL_CNTPRESC_DIV128, /**< Divide clock by 128. */ - rtccCntPresc_256 = _RTCC_CTRL_CNTPRESC_DIV256, /**< Divide clock by 256. */ - rtccCntPresc_512 = _RTCC_CTRL_CNTPRESC_DIV512, /**< Divide clock by 512. */ - rtccCntPresc_1024 = _RTCC_CTRL_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ - rtccCntPresc_2048 = _RTCC_CTRL_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ - rtccCntPresc_4096 = _RTCC_CTRL_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ - rtccCntPresc_8192 = _RTCC_CTRL_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ - rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ - rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ -} RTCC_CntPresc_TypeDef; - -#elif defined (_RTCC_CFG_CNTPRESC_DIV1) -typedef enum { - rtccCntPresc_1 = _RTCC_CFG_CNTPRESC_DIV1, /**< Divide clock by 1. */ - rtccCntPresc_2 = _RTCC_CFG_CNTPRESC_DIV2, /**< Divide clock by 2. */ - rtccCntPresc_4 = _RTCC_CFG_CNTPRESC_DIV4, /**< Divide clock by 4. */ - rtccCntPresc_8 = _RTCC_CFG_CNTPRESC_DIV8, /**< Divide clock by 8. */ - rtccCntPresc_16 = _RTCC_CFG_CNTPRESC_DIV16, /**< Divide clock by 16. */ - rtccCntPresc_32 = _RTCC_CFG_CNTPRESC_DIV32, /**< Divide clock by 32. */ - rtccCntPresc_64 = _RTCC_CFG_CNTPRESC_DIV64, /**< Divide clock by 64. */ - rtccCntPresc_128 = _RTCC_CFG_CNTPRESC_DIV128, /**< Divide clock by 128. */ - rtccCntPresc_256 = _RTCC_CFG_CNTPRESC_DIV256, /**< Divide clock by 256. */ - rtccCntPresc_512 = _RTCC_CFG_CNTPRESC_DIV512, /**< Divide clock by 512. */ - rtccCntPresc_1024 = _RTCC_CFG_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ - rtccCntPresc_2048 = _RTCC_CFG_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ - rtccCntPresc_4096 = _RTCC_CFG_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ - rtccCntPresc_8192 = _RTCC_CFG_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ - rtccCntPresc_16384 = _RTCC_CFG_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ - rtccCntPresc_32768 = _RTCC_CFG_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ -} RTCC_CntPresc_TypeDef; -#endif - -/** Prescaler mode of the RTCC counter. */ -#if defined (_RTCC_CTRL_CNTTICK_MASK) -typedef enum { - /** CNT register ticks according to prescaler value. */ - rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC, - - /** CNT register ticks when PRECNT matches the 15 least significant bits of - * ch. 0 CCV register. */ - rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH -} RTCC_PrescMode_TypeDef; - -#elif defined (_RTCC_CFG_CNTTICK_MASK) -typedef enum { - /** CNT register ticks according to the prescaler value. */ - rtccCntTickPresc = _RTCC_CFG_CNTTICK_PRESC, - - /** CNT register ticks when PRECNT matches the 15 least significant bits of - * ch. 0 CCV register. */ - rtccCntTickCCV0Match = _RTCC_CFG_CNTTICK_CCV0MATCH -} RTCC_PrescMode_TypeDef; -#endif - -/** Capture/Compare channel mode. */ -typedef enum { - rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */ - rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */ - rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */ -} RTCC_CapComChMode_TypeDef; - -/** Compare match output action mode. */ -typedef enum { - rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */ - rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */ - rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */ - rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */ -} RTCC_CompMatchOutAction_TypeDef; - -/** PRS channel number. This type is used when configuring input capture mode on - * a RTCC channel. */ -typedef uint8_t RTCC_PRSSel_TypeDef; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** Deprecated PRS channel values. New code should use an integer instead of - * using these deprecated enum values. */ -#define rtccPRSCh0 0U -#define rtccPRSCh1 1U -#define rtccPRSCh2 2U -#define rtccPRSCh3 3U -#define rtccPRSCh4 4U -#define rtccPRSCh5 5U -#define rtccPRSCh6 6U -#define rtccPRSCh7 7U -#define rtccPRSCh8 8U -#define rtccPRSCh9 9U -#define rtccPRSCh10 10U -#define rtccPRSCh11 11U -/** @endcond */ - -/** Input edge select. */ -typedef enum { - rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */ - rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */ - rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */ - rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */ -} RTCC_InEdgeSel_TypeDef; - -/** Capture/Compare channel compare mode. */ -typedef enum { - /** CCVx is compared with the CNT register. */ - rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT, - - /** CCVx is compared with a CNT[16:0] and PRECNT[14:0]. */ - rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT -} RTCC_CompBase_TypeDef; - -#if defined (_RTCC_CC_CTRL_DAYCC_MASK) -/** Day compare mode. */ -typedef enum { - rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */ - rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */ -} RTCC_DayCompareMode_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** RTCC initialization structure. */ -typedef struct { - /** Enable/disable counting when initialization is completed. */ - bool enable; - - /** Enable/disable timer counting during debug halt. */ - bool debugRun; - - /** Enable/disable pre-counter wrap on ch. 0 CCV value. */ - bool precntWrapOnCCV0; - - /** Enable/disable counter wrap on ch. 1 CCV value. */ - bool cntWrapOnCCV1; - - /** Counter prescaler. */ - RTCC_CntPresc_TypeDef presc; - - /** Prescaler mode. */ - RTCC_PrescMode_TypeDef prescMode; - -#if defined(_RTCC_CTRL_BUMODETSEN_MASK) - /** Enable/disable storing RTCC counter value in RTCC_CCV2 upon backup mode - * entry. */ - bool enaBackupModeSet; -#endif - -#if defined(_RTCC_CTRL_OSCFDETEN_MASK) - /** Enable/disable the check that sets OSCFFAIL interrupt flag if no - * LFCLK-RTCC ticks are detected within one ULFRCO cycles. */ - bool enaOSCFailDetect; -#endif - -#if defined (_RTCC_CTRL_CNTMODE_MASK) - /** Select operational mode of the counter. */ - RTCC_CntMode_TypeDef cntMode; -#endif - -#if defined (_RTCC_CTRL_LYEARCORRDIS_MASK) - /** Disable leap year correction for calendar mode. When this parameter is - * set to false, February has 29 days if (year % 4 == 0). If set to true, - * February always has 28 days. */ - bool disLeapYearCorr; -#endif -} RTCC_Init_TypeDef; - -/** RTCC capture/compare channel configuration structure. */ -typedef struct { - /** Select mode of Capture/Compare channel. */ - RTCC_CapComChMode_TypeDef chMode; - - /** Compare mode channel match output action. */ - RTCC_CompMatchOutAction_TypeDef compMatchOutAction; - - /** Capture mode channel PRS input channel selection. */ - RTCC_PRSSel_TypeDef prsSel; - - /** Capture mode channel input edge selection. */ - RTCC_InEdgeSel_TypeDef inputEdgeSel; - - /** Comparison base of channel in compare mode. */ - RTCC_CompBase_TypeDef compBase; - -#if defined (_RTCC_CC_CTRL_COMPMASK_MASK) - /** The COMPMASK (5 bit) most significant bits of compare value will not - * be subject to comparison. */ - uint8_t compMask; -#endif - -#if defined (_RTCC_CC_CTRL_DAYCC_MASK) - /** Day compare mode. */ - RTCC_DayCompareMode_TypeDef dayCompMode; -#endif -} RTCC_CCChConf_TypeDef; - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Default RTCC initialization structure. */ -#if defined(_SILICON_LABS_32B_SERIES_2) -#define RTCC_INIT_DEFAULT \ - { \ - true, /* Start counting when init done. */ \ - false, /* Disable RTCC during debug halt. */ \ - false, /* Disable precounter wrap on ch. 0 CCV value. */ \ - false, /* Disable counter wrap on ch. 1 CCV value. */ \ - rtccCntPresc_32, /* 977 us per tick. */ \ - rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ - } - -#elif defined(_RTCC_CTRL_BUMODETSEN_MASK) -#define RTCC_INIT_DEFAULT \ - { \ - true, /* Start counting when initialization is done. */ \ - false, /* Disable RTCC during debug halt. */ \ - false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ - false, /* Disable counter wrap on ch. 1 CCV value. */ \ - rtccCntPresc_32, /* 977 us per tick. */ \ - rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ - false, /* No RTCC storage on backup mode entry. */ \ - false, /* No RTCC oscillator failure detection. */ \ - rtccCntModeNormal, /* Normal RTCC mode. */ \ - false, /* No leap year correction. */ \ - } - -#else -#define RTCC_INIT_DEFAULT \ - { \ - true, /* Start counting when initialization is done. */ \ - false, /* Disable RTCC during debug halt. */ \ - false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ - false, /* Disable counter wrap on ch. 1 CCV value. */ \ - rtccCntPresc_32, /* 977 us per tick. */ \ - rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ - false, /* No RTCC oscillator failure detection. */ \ - rtccCntModeNormal, /* Normal RTCC mode. */ \ - false, /* No leap year correction. */ \ - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** Default RTCC channel output compare initialization structure. */ -#define RTCC_CH_INIT_COMPARE_DEFAULT \ - { \ - rtccCapComChModeCompare, /* Select output compare mode. */ \ - rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \ - 0, /* Don't care. */ \ - rtccInEdgeNone, /* Don't care. */ \ - rtccCompBaseCnt, /* Use CNT for comparison. */ \ - } - -/** Default RTCC channel input capture initialization structure. */ -#define RTCC_CH_INIT_CAPTURE_DEFAULT \ - { \ - rtccCapComChModeCapture, /* Select input capture mode. */ \ - rtccCompMatchOutActionPulse, /* Don't care. */ \ - 0, /* Use PRS channel 0 as trigger. */ \ - rtccInEdgeRising, /* Capture on rising edge. */ \ - rtccCompBaseCnt, /* Don't care. */ \ - } - -#else // Series 1 devices - -/** Default RTCC channel output compare initialization structure. */ -#define RTCC_CH_INIT_COMPARE_DEFAULT \ - { \ - rtccCapComChModeCompare, /* Select output compare mode. */ \ - rtccCompMatchOutActionPulse, /* Create pulse on compare match.*/ \ - 0, /* PRS channel 0 (not used). */ \ - rtccInEdgeNone, /* No edge detection. */ \ - rtccCompBaseCnt, /* Counter comparison base. */ \ - 0, /* No compare mask bits set. */ \ - rtccDayCompareModeMonth /* Don't care */ \ - } - -/** Default RTCC channel input capture initialization structure. */ -#define RTCC_CH_INIT_CAPTURE_DEFAULT \ - { \ - rtccCapComChModeCapture, /* Select input capture mode. */ \ - rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \ - 0, /* PRS channel 0. */ \ - rtccInEdgeRising, /* Rising edge detection. */ \ - rtccCompBaseCnt, /* Don't care. */ \ - 0, /* Don't care. */ \ - rtccDayCompareModeMonth /* Don't care */ \ - } - -#endif - -/** Number of RTCC capture/compare channels */ -#if !defined(RTCC_CC_NUM) -#define RTCC_CC_NUM 3UL -#endif - -/** Validation of valid RTCC channel for assert statements. */ -#define RTCC_CH_VALID(ch) ((unsigned)(ch) < RTCC_CC_NUM) - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the RTCC compare register value for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @return - * Compare register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_ChannelCompareValueGet(int ch) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); -#if defined (_RTCC_CC_CCV_MASK) - return RTCC->CC[ch].CCV; -#elif defined (_RTCC_CC_OCVALUE_MASK) - return RTCC->CC[ch].OCVALUE; -#endif -} - -/***************************************************************************//** - * @brief - * Set the RTCC compare register value for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @param[in] value - * Compare register value - ******************************************************************************/ -__STATIC_INLINE void RTCC_ChannelCompareValueSet(int ch, uint32_t value) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); -#if defined (_RTCC_CC_CCV_MASK) - RTCC->CC[ch].CCV = value; -#elif defined (_RTCC_CC_OCVALUE_MASK) - RTCC->CC[ch].OCVALUE = value; -#endif -} - -/***************************************************************************//** - * @brief - * Get the RTCC input capture register value for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @return - * Capture register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_ChannelCaptureValueGet(int ch) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); -#if defined (_RTCC_CC_CCV_MASK) - return RTCC->CC[ch].CCV; -#elif defined (_RTCC_CC_ICVALUE_MASK) - return RTCC->CC[ch].ICVALUE; -#endif -} - -/***************************************************************************//** - * @brief - * Get the RTCC capture/compare register value for a selected channel. - * For parts with separate capture compare value registers, this function - * returns the compare value. - * - * @param[in] ch - * Channel selector. - * - * @return - * Capture/compare register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_ChannelCCVGet(int ch) -{ - return RTCC_ChannelCompareValueGet(ch); -} - -/***************************************************************************//** - * @brief - * Set RTCC capture/compare register value for a selected channel. - * For parts with separate capture compare value registers, this function - * sets the compare value. - * - * @param[in] ch - * Channel selector. - * - * @param[in] value - * Capture/compare register value - ******************************************************************************/ -__STATIC_INLINE void RTCC_ChannelCCVSet(int ch, uint32_t value) -{ - RTCC_ChannelCompareValueSet(ch, value); -} - -#if defined (_RTCC_CC_DATE_MASK) -/***************************************************************************//** - * @brief - * Get the calendar DATE register content for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @return - * DATE register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_ChannelDateGet(int ch) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); - return RTCC->CC[ch].DATE; -} - -/***************************************************************************//** - * @brief - * Set the calendar DATE register for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @param[in] date - * DATE value. - ******************************************************************************/ -__STATIC_INLINE void RTCC_ChannelDateSet(int ch, uint32_t date) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); - RTCC->CC[ch].DATE = date; -} - -/***************************************************************************//** - * @brief - * Get the calendar TIME register content for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @return - * TIME register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_ChannelTimeGet(int ch) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); - return RTCC->CC[ch].TIME; -} - -/***************************************************************************//** - * @brief - * Set the calendar TIME register for a selected channel. - * - * @param[in] ch - * Channel selector. - * - * @param[in] time - * TIME value. - ******************************************************************************/ -__STATIC_INLINE void RTCC_ChannelTimeSet(int ch, uint32_t time) -{ - EFM_ASSERT(RTCC_CH_VALID(ch) ); - RTCC->CC[ch].TIME = time; -} -#endif /* defined (_RTCC_CC_DATE_MASK) */ - -/***************************************************************************//** - * @brief - * Get the combined CNT/PRECNT register content. - * - * @return - * CNT/PRECNT register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_CombinedCounterGet(void) -{ -#if defined (RTCC_SYNCBUSY_CNT) || defined (RTCC_SYNCBUSY_CNT) - while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_CNT | RTCC_SYNCBUSY_PRECNT)) != 0U) { - /* Wait for CNT and PRECNT to synchronize */ - } -#endif - return RTCC->COMBCNT; -} - -/***************************************************************************//** - * @brief - * Get the RTCC counter value. - * - * @return - * Current RTCC counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_CounterGet(void) -{ -#if defined (RTCC_SYNCBUSY_CNT) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { - /* Wait for CNT to synchronize before getting value */ - } -#endif - return RTCC->CNT; -} - -/***************************************************************************//** - * @brief - * Set the RTCC CNT counter. - * - * @param[in] value - * CNT value. - ******************************************************************************/ -__STATIC_INLINE void RTCC_CounterSet(uint32_t value) -{ -#if defined (RTCC_SYNCBUSY_CNT) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { - /* Wait for CNT to synchronize before setting new value */ - } -#endif - - RTCC->CNT = value; -} - -#if defined (_RTCC_CC_DATE_MASK) -/***************************************************************************//** - * @brief - * Get the DATE register value. - * - * @return - * Current DATE register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_DateGet(void) -{ - return RTCC->DATE; -} - -/***************************************************************************//** - * @brief - * Set the RTCC DATE register. - * - * @param[in] date - * DATE value. - ******************************************************************************/ -__STATIC_INLINE void RTCC_DateSet(uint32_t date) -{ - RTCC->DATE = date; -} -#endif /* defined (_RTCC_CC_DATE_MASK) */ - -#if defined (RTCC_EM4WUEN_EM4WU) -/***************************************************************************//** - * @brief - * Enable/disable EM4 wakeup capability. - * - * @param[in] enable - * Set to true to enable EM4 wakeup, set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable) -{ - if ( enable ) { - RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU; - } else { - RTCC->EM4WUEN = 0; - } -} -#endif - -void RTCC_Enable(bool enable); - -void RTCC_Init(const RTCC_Init_TypeDef *init); - -void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr); - -/***************************************************************************//** - * @brief - * Clear one or more pending RTCC interrupts. - * - * @param[in] flags - * RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed - * together to clear multiple interrupt sources. - ******************************************************************************/ -__STATIC_INLINE void RTCC_IntClear(uint32_t flags) -{ -#if defined (RTCC_HAS_SET_CLEAR) - RTCC->IF_CLR = flags; -#else - RTCC->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more RTCC interrupts. - * - * @param[in] flags - * RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed - * together to disable multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void RTCC_IntDisable(uint32_t flags) -{ - RTCC->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more RTCC interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * RTCC_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed - * together to set multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void RTCC_IntEnable(uint32_t flags) -{ - RTCC->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending RTCC interrupt flags. - * - * @note - * Event bits are not cleared by using this function. - * - * @return - * Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed - * together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_IntGet(void) -{ - return RTCC->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending RTCC interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @return - * Pending and enabled RTCC interrupt sources. Returns a set of interrupt - * flags OR-ed together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_IntGetEnabled(void) -{ - uint32_t tmp; - - tmp = RTCC->IEN; - - /* Bitwise AND of pending and enabled interrupt flags. */ - return RTCC->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending RTCC interrupts from SW. - * - * @param[in] flags - * RTCC interrupt sources to set to pending. Use a set of interrupt flags - * (RTCC_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void RTCC_IntSet(uint32_t flags) -{ -#if defined (RTCC_HAS_SET_CLEAR) - RTCC->IF_SET = flags; -#else - RTCC->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Lock RTCC registers. - * - * @note - * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, - * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers - * cannot be written to. - ******************************************************************************/ -__STATIC_INLINE void RTCC_Lock(void) -{ -#if defined(ERRATA_FIX_RTCC_E203) - /* RTCC_E203 - Potential Stability Issue with RTCC Registers. - * RTCC_LOCK register must be modified while RTCC clock is disabled. */ - uint32_t lfeReg = CMU->LFECLKEN0; - bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); - if (cmuLocked) { - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; - } - CMU->LFECLKEN0 = 0x0; -#endif - RTCC->LOCK = ~RTCC_LOCK_LOCKKEY_UNLOCK; -#if defined(ERRATA_FIX_RTCC_E203) - /* Restore clock state after RTCC_E203 fix. */ - CMU->LFECLKEN0 = lfeReg; - if (cmuLocked) { - CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; - } -#endif -} - -/***************************************************************************//** - * @brief - * Get the RTCC pre-counter value. - * - * @return - * Current RTCC pre-counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_PreCounterGet(void) -{ -#if defined (RTCC_SYNCBUSY_PRECNT) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { - /* Wait for PRECNT to synchronize */ - } -#endif - return RTCC->PRECNT; -} - -/***************************************************************************//** - * @brief - * Set the RTCC pre-counter value. - * - * @param[in] preCntVal - * RTCC pre-counter value to be set. - ******************************************************************************/ -__STATIC_INLINE void RTCC_PreCounterSet(uint32_t preCntVal) -{ -#if defined (RTCC_SYNCBUSY_PRECNT) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { - /* Wait for PRECNT to synchronize */ - } -#endif - - RTCC->PRECNT = preCntVal; -} - -void RTCC_Reset(void); - -#if defined (_RTCC_POWERDOWN_MASK) -/***************************************************************************//** - * @brief - * Power down retention RAM. - * - * @note - * Once retention RAM is powered down, it cannot be powered up again. - ******************************************************************************/ -__STATIC_INLINE void RTCC_RetentionRamPowerDown(void) -{ -#if !defined(ERRATA_FIX_RTCC_E204) - /* Devices that are affected by RTCC_E204 should always keep RTCC - * backup RAM retained. */ - RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; -#endif -} -#endif - -void RTCC_StatusClear(void); - -/***************************************************************************//** - * @brief - * Get the STATUS register value. - * - * @return - * Current STATUS register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_StatusGet(void) -{ -#if defined (RTCC_SYNCBUSY_CMD) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { - // Wait for synchronization. - } -#elif defined (RTCC_SYNCBUSY_START) - while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_START | RTCC_SYNCBUSY_STOP)) != 0U) { - /* Wait for synchronization. */ - } -#endif - return RTCC->STATUS; -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Wait for the RTCC to complete all synchronization of register changes - * and commands. - ******************************************************************************/ -__STATIC_INLINE void RTCC_SyncWait(void) -{ - while ((RTCC->EN != 0U) && (RTCC->SYNCBUSY != 0U)) { - /* Wait for synchronization to finish */ - } -} - -/***************************************************************************//** - * @brief - * Start the RTCC counter. - * - * @details - * This function will send a start command to the RTCC peripheral. The RTCC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref RTCC_SyncWait() function can be used to wait for the start command - * to be executed. - * - * @note - * This function requires the RTCC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void RTCC_Start(void) -{ - RTCC_SyncWait(); - RTCC->CMD = RTCC_CMD_START; -} - -/***************************************************************************//** - * @brief - * Stop the RTCC counter. - * - * @details - * This function will send a stop command to the RTCC peripheral. The RTCC - * peripheral will use some LF clock ticks before the command is executed. - * The @ref RTCC_SyncWait() function can be used to wait for the stop command - * to be executed. - * - * @note - * This function requires the RTCC to be enabled. - ******************************************************************************/ -__STATIC_INLINE void RTCC_Stop(void) -{ - RTCC_SyncWait(); - RTCC->CMD = RTCC_CMD_STOP; -} -#endif - -#if defined (_RTCC_TIME_MASK) -/***************************************************************************//** - * @brief - * Get the TIME register value. - * - * @return - * Current TIME register value. - ******************************************************************************/ -__STATIC_INLINE uint32_t RTCC_TimeGet(void) -{ - return RTCC->TIME; -} - -/***************************************************************************//** - * @brief - * Set the RTCC TIME register. - * - * @param[in] time - * TIME value. - ******************************************************************************/ -__STATIC_INLINE void RTCC_TimeSet(uint32_t time) -{ - RTCC->TIME = time; -} -#endif - -/***************************************************************************//** - * @brief - * Unlock RTCC registers. - * - * @note - * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, - * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers - * cannot be written to. - ******************************************************************************/ -__STATIC_INLINE void RTCC_Unlock(void) -{ -#if defined(ERRATA_FIX_RTCC_E203) - /* RTCC_E203 - Potential Stability Issue with RTCC Registers. - * RTCC_LOCK register must be modified while RTCC clock is disabled. */ - uint32_t lfeReg = CMU->LFECLKEN0; - bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); - if (cmuLocked) { - CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; - } - CMU->LFECLKEN0 = 0x0; -#endif - RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; -#if defined(ERRATA_FIX_RTCC_E203) - /* Restore clock state after RTCC_E203 fix. */ - CMU->LFECLKEN0 = lfeReg; - if (cmuLocked) { - CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; - } -#endif -} - -/** @} (end addtogroup rtcc) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */ -#endif /* EM_RTCC_H */ +/***************************************************************************//** + * @file + * @brief Real Time Counter (RTCC) peripheral API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_RTCC_H +#define EM_RTCC_H + +#include "em_device.h" +#if defined(RTCC_COUNT) && (RTCC_COUNT == 1) + +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup rtcc + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +/* Enable fix for errata "RTCC_E203 - Potential Stability Issue with RTCC + * Registers". */ +#define ERRATA_FIX_RTCC_E203 +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +/* Enable fix for errata "RTCC_E204 - Disabling the RTCC Backup RAM may consume extra + * current". */ +#define ERRATA_FIX_RTCC_E204 +#endif +/** @endcond */ + +/******************************************************************************* + ********************************* ENUM ************************************ + ******************************************************************************/ + +#if defined (_RTCC_CTRL_CNTMODE_MASK) +/** Operational mode of the counter. */ +typedef enum { + /** Normal counter mode. The counter is incremented by 1 for each tick. */ + rtccCntModeNormal = _RTCC_CTRL_CNTMODE_NORMAL, + + /** Calendar mode. Refer to the RTCC chapter of the Reference Manual for more + * details on the calendar mode. */ + rtccCntModeCalendar = _RTCC_CTRL_CNTMODE_CALENDAR +} RTCC_CntMode_TypeDef; +#endif + +/** Counter prescaler selection. */ +#if defined (_RTCC_CTRL_CNTPRESC_DIV1) +typedef enum { + rtccCntPresc_1 = _RTCC_CTRL_CNTPRESC_DIV1, /**< Divide clock by 1. */ + rtccCntPresc_2 = _RTCC_CTRL_CNTPRESC_DIV2, /**< Divide clock by 2. */ + rtccCntPresc_4 = _RTCC_CTRL_CNTPRESC_DIV4, /**< Divide clock by 4. */ + rtccCntPresc_8 = _RTCC_CTRL_CNTPRESC_DIV8, /**< Divide clock by 8. */ + rtccCntPresc_16 = _RTCC_CTRL_CNTPRESC_DIV16, /**< Divide clock by 16. */ + rtccCntPresc_32 = _RTCC_CTRL_CNTPRESC_DIV32, /**< Divide clock by 32. */ + rtccCntPresc_64 = _RTCC_CTRL_CNTPRESC_DIV64, /**< Divide clock by 64. */ + rtccCntPresc_128 = _RTCC_CTRL_CNTPRESC_DIV128, /**< Divide clock by 128. */ + rtccCntPresc_256 = _RTCC_CTRL_CNTPRESC_DIV256, /**< Divide clock by 256. */ + rtccCntPresc_512 = _RTCC_CTRL_CNTPRESC_DIV512, /**< Divide clock by 512. */ + rtccCntPresc_1024 = _RTCC_CTRL_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ + rtccCntPresc_2048 = _RTCC_CTRL_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ + rtccCntPresc_4096 = _RTCC_CTRL_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ + rtccCntPresc_8192 = _RTCC_CTRL_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ + rtccCntPresc_16384 = _RTCC_CTRL_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ + rtccCntPresc_32768 = _RTCC_CTRL_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ +} RTCC_CntPresc_TypeDef; + +#elif defined (_RTCC_CFG_CNTPRESC_DIV1) +typedef enum { + rtccCntPresc_1 = _RTCC_CFG_CNTPRESC_DIV1, /**< Divide clock by 1. */ + rtccCntPresc_2 = _RTCC_CFG_CNTPRESC_DIV2, /**< Divide clock by 2. */ + rtccCntPresc_4 = _RTCC_CFG_CNTPRESC_DIV4, /**< Divide clock by 4. */ + rtccCntPresc_8 = _RTCC_CFG_CNTPRESC_DIV8, /**< Divide clock by 8. */ + rtccCntPresc_16 = _RTCC_CFG_CNTPRESC_DIV16, /**< Divide clock by 16. */ + rtccCntPresc_32 = _RTCC_CFG_CNTPRESC_DIV32, /**< Divide clock by 32. */ + rtccCntPresc_64 = _RTCC_CFG_CNTPRESC_DIV64, /**< Divide clock by 64. */ + rtccCntPresc_128 = _RTCC_CFG_CNTPRESC_DIV128, /**< Divide clock by 128. */ + rtccCntPresc_256 = _RTCC_CFG_CNTPRESC_DIV256, /**< Divide clock by 256. */ + rtccCntPresc_512 = _RTCC_CFG_CNTPRESC_DIV512, /**< Divide clock by 512. */ + rtccCntPresc_1024 = _RTCC_CFG_CNTPRESC_DIV1024, /**< Divide clock by 1024. */ + rtccCntPresc_2048 = _RTCC_CFG_CNTPRESC_DIV2048, /**< Divide clock by 2048. */ + rtccCntPresc_4096 = _RTCC_CFG_CNTPRESC_DIV4096, /**< Divide clock by 4096. */ + rtccCntPresc_8192 = _RTCC_CFG_CNTPRESC_DIV8192, /**< Divide clock by 8192. */ + rtccCntPresc_16384 = _RTCC_CFG_CNTPRESC_DIV16384, /**< Divide clock by 16384. */ + rtccCntPresc_32768 = _RTCC_CFG_CNTPRESC_DIV32768 /**< Divide clock by 32768. */ +} RTCC_CntPresc_TypeDef; +#endif + +/** Prescaler mode of the RTCC counter. */ +#if defined (_RTCC_CTRL_CNTTICK_MASK) +typedef enum { + /** CNT register ticks according to prescaler value. */ + rtccCntTickPresc = _RTCC_CTRL_CNTTICK_PRESC, + + /** CNT register ticks when PRECNT matches the 15 least significant bits of + * ch. 0 CCV register. */ + rtccCntTickCCV0Match = _RTCC_CTRL_CNTTICK_CCV0MATCH +} RTCC_PrescMode_TypeDef; + +#elif defined (_RTCC_CFG_CNTTICK_MASK) +typedef enum { + /** CNT register ticks according to the prescaler value. */ + rtccCntTickPresc = _RTCC_CFG_CNTTICK_PRESC, + + /** CNT register ticks when PRECNT matches the 15 least significant bits of + * ch. 0 CCV register. */ + rtccCntTickCCV0Match = _RTCC_CFG_CNTTICK_CCV0MATCH +} RTCC_PrescMode_TypeDef; +#endif + +/** Capture/Compare channel mode. */ +typedef enum { + rtccCapComChModeOff = _RTCC_CC_CTRL_MODE_OFF, /**< Capture/Compare channel turned off. */ + rtccCapComChModeCapture = _RTCC_CC_CTRL_MODE_INPUTCAPTURE, /**< Capture mode. */ + rtccCapComChModeCompare = _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Compare mode. */ +} RTCC_CapComChMode_TypeDef; + +/** Compare match output action mode. */ +typedef enum { + rtccCompMatchOutActionPulse = _RTCC_CC_CTRL_CMOA_PULSE, /**< Generate a pulse. */ + rtccCompMatchOutActionToggle = _RTCC_CC_CTRL_CMOA_TOGGLE, /**< Toggle output. */ + rtccCompMatchOutActionClear = _RTCC_CC_CTRL_CMOA_CLEAR, /**< Clear output. */ + rtccCompMatchOutActionSet = _RTCC_CC_CTRL_CMOA_SET /**< Set output. */ +} RTCC_CompMatchOutAction_TypeDef; + +/** PRS channel number. This type is used when configuring input capture mode on + * a RTCC channel. */ +typedef uint8_t RTCC_PRSSel_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel values. New code should use an integer instead of + * using these deprecated enum values. */ +#define rtccPRSCh0 0U +#define rtccPRSCh1 1U +#define rtccPRSCh2 2U +#define rtccPRSCh3 3U +#define rtccPRSCh4 4U +#define rtccPRSCh5 5U +#define rtccPRSCh6 6U +#define rtccPRSCh7 7U +#define rtccPRSCh8 8U +#define rtccPRSCh9 9U +#define rtccPRSCh10 10U +#define rtccPRSCh11 11U +/** @endcond */ + +/** Input edge select. */ +typedef enum { + rtccInEdgeRising = _RTCC_CC_CTRL_ICEDGE_RISING, /**< Rising edges detected. */ + rtccInEdgeFalling = _RTCC_CC_CTRL_ICEDGE_FALLING, /**< Falling edges detected. */ + rtccInEdgeBoth = _RTCC_CC_CTRL_ICEDGE_BOTH, /**< Both edges detected. */ + rtccInEdgeNone = _RTCC_CC_CTRL_ICEDGE_NONE /**< No edge detection, signal is left as is. */ +} RTCC_InEdgeSel_TypeDef; + +/** Capture/Compare channel compare mode. */ +typedef enum { + /** CCVx is compared with the CNT register. */ + rtccCompBaseCnt = _RTCC_CC_CTRL_COMPBASE_CNT, + + /** CCVx is compared with a CNT[16:0] and PRECNT[14:0]. */ + rtccCompBasePreCnt = _RTCC_CC_CTRL_COMPBASE_PRECNT +} RTCC_CompBase_TypeDef; + +#if defined (_RTCC_CC_CTRL_DAYCC_MASK) +/** Day compare mode. */ +typedef enum { + rtccDayCompareModeMonth = _RTCC_CC_CTRL_DAYCC_MONTH, /**< Day of month is selected for Capture/Compare. */ + rtccDayCompareModeWeek = _RTCC_CC_CTRL_DAYCC_WEEK /**< Day of week is selected for Capture/Compare. */ +} RTCC_DayCompareMode_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** RTCC initialization structure. */ +typedef struct { + /** Enable/disable counting when initialization is completed. */ + bool enable; + + /** Enable/disable timer counting during debug halt. */ + bool debugRun; + + /** Enable/disable pre-counter wrap on ch. 0 CCV value. */ + bool precntWrapOnCCV0; + + /** Enable/disable counter wrap on ch. 1 CCV value. */ + bool cntWrapOnCCV1; + + /** Counter prescaler. */ + RTCC_CntPresc_TypeDef presc; + + /** Prescaler mode. */ + RTCC_PrescMode_TypeDef prescMode; + +#if defined(_RTCC_CTRL_BUMODETSEN_MASK) + /** Enable/disable storing RTCC counter value in RTCC_CCV2 upon backup mode + * entry. */ + bool enaBackupModeSet; +#endif + +#if defined(_RTCC_CTRL_OSCFDETEN_MASK) + /** Enable/disable the check that sets OSCFFAIL interrupt flag if no + * LFCLK-RTCC ticks are detected within one ULFRCO cycles. */ + bool enaOSCFailDetect; +#endif + +#if defined (_RTCC_CTRL_CNTMODE_MASK) + /** Select operational mode of the counter. */ + RTCC_CntMode_TypeDef cntMode; +#endif + +#if defined (_RTCC_CTRL_LYEARCORRDIS_MASK) + /** Disable leap year correction for calendar mode. When this parameter is + * set to false, February has 29 days if (year % 4 == 0). If set to true, + * February always has 28 days. */ + bool disLeapYearCorr; +#endif +} RTCC_Init_TypeDef; + +/** RTCC capture/compare channel configuration structure. */ +typedef struct { + /** Select mode of Capture/Compare channel. */ + RTCC_CapComChMode_TypeDef chMode; + + /** Compare mode channel match output action. */ + RTCC_CompMatchOutAction_TypeDef compMatchOutAction; + + /** Capture mode channel PRS input channel selection. */ + RTCC_PRSSel_TypeDef prsSel; + + /** Capture mode channel input edge selection. */ + RTCC_InEdgeSel_TypeDef inputEdgeSel; + + /** Comparison base of channel in compare mode. */ + RTCC_CompBase_TypeDef compBase; + +#if defined (_RTCC_CC_CTRL_COMPMASK_MASK) + /** The COMPMASK (5 bit) most significant bits of compare value will not + * be subject to comparison. */ + uint8_t compMask; +#endif + +#if defined (_RTCC_CC_CTRL_DAYCC_MASK) + /** Day compare mode. */ + RTCC_DayCompareMode_TypeDef dayCompMode; +#endif +} RTCC_CCChConf_TypeDef; + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Default RTCC initialization structure. */ +#if defined(_SILICON_LABS_32B_SERIES_2) +#define RTCC_INIT_DEFAULT \ + { \ + true, /* Start counting when init done. */ \ + false, /* Disable RTCC during debug halt. */ \ + false, /* Disable precounter wrap on ch. 0 CCV value. */ \ + false, /* Disable counter wrap on ch. 1 CCV value. */ \ + rtccCntPresc_32, /* 977 us per tick. */ \ + rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ + } + +#elif defined(_RTCC_CTRL_BUMODETSEN_MASK) +#define RTCC_INIT_DEFAULT \ + { \ + true, /* Start counting when initialization is done. */ \ + false, /* Disable RTCC during debug halt. */ \ + false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ + false, /* Disable counter wrap on ch. 1 CCV value. */ \ + rtccCntPresc_32, /* 977 us per tick. */ \ + rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ + false, /* No RTCC storage on backup mode entry. */ \ + false, /* No RTCC oscillator failure detection. */ \ + rtccCntModeNormal, /* Normal RTCC mode. */ \ + false, /* No leap year correction. */ \ + } + +#else +#define RTCC_INIT_DEFAULT \ + { \ + true, /* Start counting when initialization is done. */ \ + false, /* Disable RTCC during debug halt. */ \ + false, /* Disable pre-counter wrap on ch. 0 CCV value. */ \ + false, /* Disable counter wrap on ch. 1 CCV value. */ \ + rtccCntPresc_32, /* 977 us per tick. */ \ + rtccCntTickPresc, /* Counter increments according to prescaler value.*/ \ + false, /* No RTCC oscillator failure detection. */ \ + rtccCntModeNormal, /* Normal RTCC mode. */ \ + false, /* No leap year correction. */ \ + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** Default RTCC channel output compare initialization structure. */ +#define RTCC_CH_INIT_COMPARE_DEFAULT \ + { \ + rtccCapComChModeCompare, /* Select output compare mode. */ \ + rtccCompMatchOutActionPulse, /* Create pulse on compare match. */ \ + 0, /* Don't care. */ \ + rtccInEdgeNone, /* Don't care. */ \ + rtccCompBaseCnt, /* Use CNT for comparison. */ \ + } + +/** Default RTCC channel input capture initialization structure. */ +#define RTCC_CH_INIT_CAPTURE_DEFAULT \ + { \ + rtccCapComChModeCapture, /* Select input capture mode. */ \ + rtccCompMatchOutActionPulse, /* Don't care. */ \ + 0, /* Use PRS channel 0 as trigger. */ \ + rtccInEdgeRising, /* Capture on rising edge. */ \ + rtccCompBaseCnt, /* Don't care. */ \ + } + +#else // Series 1 devices + +/** Default RTCC channel output compare initialization structure. */ +#define RTCC_CH_INIT_COMPARE_DEFAULT \ + { \ + rtccCapComChModeCompare, /* Select output compare mode. */ \ + rtccCompMatchOutActionPulse, /* Create pulse on compare match.*/ \ + 0, /* PRS channel 0 (not used). */ \ + rtccInEdgeNone, /* No edge detection. */ \ + rtccCompBaseCnt, /* Counter comparison base. */ \ + 0, /* No compare mask bits set. */ \ + rtccDayCompareModeMonth /* Don't care */ \ + } + +/** Default RTCC channel input capture initialization structure. */ +#define RTCC_CH_INIT_CAPTURE_DEFAULT \ + { \ + rtccCapComChModeCapture, /* Select input capture mode. */ \ + rtccCompMatchOutActionPulse, /* Create pulse on capture. */ \ + 0, /* PRS channel 0. */ \ + rtccInEdgeRising, /* Rising edge detection. */ \ + rtccCompBaseCnt, /* Don't care. */ \ + 0, /* Don't care. */ \ + rtccDayCompareModeMonth /* Don't care */ \ + } + +#endif + +/** Number of RTCC capture/compare channels */ +#if !defined(RTCC_CC_NUM) +#define RTCC_CC_NUM 3UL +#endif + +/** Validation of valid RTCC channel for assert statements. */ +#define RTCC_CH_VALID(ch) ((unsigned)(ch) < RTCC_CC_NUM) + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the RTCC compare register value for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @return + * Compare register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_ChannelCompareValueGet(int ch) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); +#if defined (_RTCC_CC_CCV_MASK) + return RTCC->CC[ch].CCV; +#elif defined (_RTCC_CC_OCVALUE_MASK) + return RTCC->CC[ch].OCVALUE; +#endif +} + +/***************************************************************************//** + * @brief + * Set the RTCC compare register value for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @param[in] value + * Compare register value + ******************************************************************************/ +__STATIC_INLINE void RTCC_ChannelCompareValueSet(int ch, uint32_t value) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); +#if defined (_RTCC_CC_CCV_MASK) + RTCC->CC[ch].CCV = value; +#elif defined (_RTCC_CC_OCVALUE_MASK) + RTCC->CC[ch].OCVALUE = value; +#endif +} + +/***************************************************************************//** + * @brief + * Get the RTCC input capture register value for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @return + * Capture register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_ChannelCaptureValueGet(int ch) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); +#if defined (_RTCC_CC_CCV_MASK) + return RTCC->CC[ch].CCV; +#elif defined (_RTCC_CC_ICVALUE_MASK) + return RTCC->CC[ch].ICVALUE; +#endif +} + +/***************************************************************************//** + * @brief + * Get the RTCC capture/compare register value for a selected channel. + * For parts with separate capture compare value registers, this function + * returns the compare value. + * + * @param[in] ch + * Channel selector. + * + * @return + * Capture/compare register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_ChannelCCVGet(int ch) +{ + return RTCC_ChannelCompareValueGet(ch); +} + +/***************************************************************************//** + * @brief + * Set RTCC capture/compare register value for a selected channel. + * For parts with separate capture compare value registers, this function + * sets the compare value. + * + * @param[in] ch + * Channel selector. + * + * @param[in] value + * Capture/compare register value + ******************************************************************************/ +__STATIC_INLINE void RTCC_ChannelCCVSet(int ch, uint32_t value) +{ + RTCC_ChannelCompareValueSet(ch, value); +} + +#if defined (_RTCC_CC_DATE_MASK) +/***************************************************************************//** + * @brief + * Get the calendar DATE register content for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @return + * DATE register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_ChannelDateGet(int ch) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); + return RTCC->CC[ch].DATE; +} + +/***************************************************************************//** + * @brief + * Set the calendar DATE register for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @param[in] date + * DATE value. + ******************************************************************************/ +__STATIC_INLINE void RTCC_ChannelDateSet(int ch, uint32_t date) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); + RTCC->CC[ch].DATE = date; +} + +/***************************************************************************//** + * @brief + * Get the calendar TIME register content for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @return + * TIME register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_ChannelTimeGet(int ch) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); + return RTCC->CC[ch].TIME; +} + +/***************************************************************************//** + * @brief + * Set the calendar TIME register for a selected channel. + * + * @param[in] ch + * Channel selector. + * + * @param[in] time + * TIME value. + ******************************************************************************/ +__STATIC_INLINE void RTCC_ChannelTimeSet(int ch, uint32_t time) +{ + EFM_ASSERT(RTCC_CH_VALID(ch) ); + RTCC->CC[ch].TIME = time; +} +#endif /* defined (_RTCC_CC_DATE_MASK) */ + +/***************************************************************************//** + * @brief + * Get the combined CNT/PRECNT register content. + * + * @return + * CNT/PRECNT register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_CombinedCounterGet(void) +{ +#if defined (RTCC_SYNCBUSY_CNT) || defined (RTCC_SYNCBUSY_CNT) + while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_CNT | RTCC_SYNCBUSY_PRECNT)) != 0U) { + /* Wait for CNT and PRECNT to synchronize */ + } +#endif + return RTCC->COMBCNT; +} + +/***************************************************************************//** + * @brief + * Get the RTCC counter value. + * + * @return + * Current RTCC counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_CounterGet(void) +{ +#if defined (RTCC_SYNCBUSY_CNT) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { + /* Wait for CNT to synchronize before getting value */ + } +#endif + return RTCC->CNT; +} + +/***************************************************************************//** + * @brief + * Set the RTCC CNT counter. + * + * @param[in] value + * CNT value. + ******************************************************************************/ +__STATIC_INLINE void RTCC_CounterSet(uint32_t value) +{ +#if defined (RTCC_SYNCBUSY_CNT) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CNT) != 0U) { + /* Wait for CNT to synchronize before setting new value */ + } +#endif + + RTCC->CNT = value; +} + +#if defined (_RTCC_CC_DATE_MASK) +/***************************************************************************//** + * @brief + * Get the DATE register value. + * + * @return + * Current DATE register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_DateGet(void) +{ + return RTCC->DATE; +} + +/***************************************************************************//** + * @brief + * Set the RTCC DATE register. + * + * @param[in] date + * DATE value. + ******************************************************************************/ +__STATIC_INLINE void RTCC_DateSet(uint32_t date) +{ + RTCC->DATE = date; +} +#endif /* defined (_RTCC_CC_DATE_MASK) */ + +#if defined (RTCC_EM4WUEN_EM4WU) +/***************************************************************************//** + * @brief + * Enable/disable EM4 wakeup capability. + * + * @param[in] enable + * Set to true to enable EM4 wakeup, set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void RTCC_EM4WakeupEnable(bool enable) +{ + if ( enable ) { + RTCC->EM4WUEN = RTCC_EM4WUEN_EM4WU; + } else { + RTCC->EM4WUEN = 0; + } +} +#endif + +void RTCC_Enable(bool enable); + +void RTCC_Init(const RTCC_Init_TypeDef *init); + +void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr); + +/***************************************************************************//** + * @brief + * Clear one or more pending RTCC interrupts. + * + * @param[in] flags + * RTCC interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources. + ******************************************************************************/ +__STATIC_INLINE void RTCC_IntClear(uint32_t flags) +{ +#if defined (RTCC_HAS_SET_CLEAR) + RTCC->IF_CLR = flags; +#else + RTCC->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more RTCC interrupts. + * + * @param[in] flags + * RTCC interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void RTCC_IntDisable(uint32_t flags) +{ + RTCC->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more RTCC interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * RTCC_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * RTCC interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void RTCC_IntEnable(uint32_t flags) +{ + RTCC->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending RTCC interrupt flags. + * + * @note + * Event bits are not cleared by using this function. + * + * @return + * Pending RTCC interrupt sources. Returns a set of interrupt flags OR-ed + * together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_IntGet(void) +{ + return RTCC->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending RTCC interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @return + * Pending and enabled RTCC interrupt sources. Returns a set of interrupt + * flags OR-ed together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_IntGetEnabled(void) +{ + uint32_t tmp; + + tmp = RTCC->IEN; + + /* Bitwise AND of pending and enabled interrupt flags. */ + return RTCC->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending RTCC interrupts from SW. + * + * @param[in] flags + * RTCC interrupt sources to set to pending. Use a set of interrupt flags + * (RTCC_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void RTCC_IntSet(uint32_t flags) +{ +#if defined (RTCC_HAS_SET_CLEAR) + RTCC->IF_SET = flags; +#else + RTCC->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Lock RTCC registers. + * + * @note + * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, + * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void RTCC_Lock(void) +{ +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers. + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif + RTCC->LOCK = ~RTCC_LOCK_LOCKKEY_UNLOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif +} + +/***************************************************************************//** + * @brief + * Get the RTCC pre-counter value. + * + * @return + * Current RTCC pre-counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_PreCounterGet(void) +{ +#if defined (RTCC_SYNCBUSY_PRECNT) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { + /* Wait for PRECNT to synchronize */ + } +#endif + return RTCC->PRECNT; +} + +/***************************************************************************//** + * @brief + * Set the RTCC pre-counter value. + * + * @param[in] preCntVal + * RTCC pre-counter value to be set. + ******************************************************************************/ +__STATIC_INLINE void RTCC_PreCounterSet(uint32_t preCntVal) +{ +#if defined (RTCC_SYNCBUSY_PRECNT) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_PRECNT) != 0U) { + /* Wait for PRECNT to synchronize */ + } +#endif + + RTCC->PRECNT = preCntVal; +} + +void RTCC_Reset(void); + +#if defined (_RTCC_POWERDOWN_MASK) +/***************************************************************************//** + * @brief + * Power down retention RAM. + * + * @note + * Once retention RAM is powered down, it cannot be powered up again. + ******************************************************************************/ +__STATIC_INLINE void RTCC_RetentionRamPowerDown(void) +{ +#if !defined(ERRATA_FIX_RTCC_E204) + /* Devices that are affected by RTCC_E204 should always keep RTCC + * backup RAM retained. */ + RTCC->POWERDOWN = RTCC_POWERDOWN_RAM; +#endif +} +#endif + +void RTCC_StatusClear(void); + +/***************************************************************************//** + * @brief + * Get the STATUS register value. + * + * @return + * Current STATUS register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_StatusGet(void) +{ +#if defined (RTCC_SYNCBUSY_CMD) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { + // Wait for synchronization. + } +#elif defined (RTCC_SYNCBUSY_START) + while ((RTCC->SYNCBUSY & (RTCC_SYNCBUSY_START | RTCC_SYNCBUSY_STOP)) != 0U) { + /* Wait for synchronization. */ + } +#endif + return RTCC->STATUS; +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Wait for the RTCC to complete all synchronization of register changes + * and commands. + ******************************************************************************/ +__STATIC_INLINE void RTCC_SyncWait(void) +{ + while ((RTCC->EN != 0U) && (RTCC->SYNCBUSY != 0U)) { + /* Wait for synchronization to finish */ + } +} + +/***************************************************************************//** + * @brief + * Start the RTCC counter. + * + * @details + * This function will send a start command to the RTCC peripheral. The RTCC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref RTCC_SyncWait() function can be used to wait for the start command + * to be executed. + * + * @note + * This function requires the RTCC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void RTCC_Start(void) +{ + RTCC_SyncWait(); + RTCC->CMD = RTCC_CMD_START; +} + +/***************************************************************************//** + * @brief + * Stop the RTCC counter. + * + * @details + * This function will send a stop command to the RTCC peripheral. The RTCC + * peripheral will use some LF clock ticks before the command is executed. + * The @ref RTCC_SyncWait() function can be used to wait for the stop command + * to be executed. + * + * @note + * This function requires the RTCC to be enabled. + ******************************************************************************/ +__STATIC_INLINE void RTCC_Stop(void) +{ + RTCC_SyncWait(); + RTCC->CMD = RTCC_CMD_STOP; +} +#endif + +#if defined (_RTCC_TIME_MASK) +/***************************************************************************//** + * @brief + * Get the TIME register value. + * + * @return + * Current TIME register value. + ******************************************************************************/ +__STATIC_INLINE uint32_t RTCC_TimeGet(void) +{ + return RTCC->TIME; +} + +/***************************************************************************//** + * @brief + * Set the RTCC TIME register. + * + * @param[in] time + * TIME value. + ******************************************************************************/ +__STATIC_INLINE void RTCC_TimeSet(uint32_t time) +{ + RTCC->TIME = time; +} +#endif + +/***************************************************************************//** + * @brief + * Unlock RTCC registers. + * + * @note + * When RTCC registers are locked, RTCC_CTRL, RTCC_PRECNT, RTCC_CNT, + * RTCC_TIME, RTCC_DATE, RTCC_IEN, RTCC_POWERDOWN and RTCC_CCx_XXX registers + * cannot be written to. + ******************************************************************************/ +__STATIC_INLINE void RTCC_Unlock(void) +{ +#if defined(ERRATA_FIX_RTCC_E203) + /* RTCC_E203 - Potential Stability Issue with RTCC Registers. + * RTCC_LOCK register must be modified while RTCC clock is disabled. */ + uint32_t lfeReg = CMU->LFECLKEN0; + bool cmuLocked = (CMU->LOCK == CMU_LOCK_LOCKKEY_LOCKED); + if (cmuLocked) { + CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK; + } + CMU->LFECLKEN0 = 0x0; +#endif + RTCC->LOCK = RTCC_LOCK_LOCKKEY_UNLOCK; +#if defined(ERRATA_FIX_RTCC_E203) + /* Restore clock state after RTCC_E203 fix. */ + CMU->LFECLKEN0 = lfeReg; + if (cmuLocked) { + CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK; + } +#endif +} + +/** @} (end addtogroup rtcc) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined( RTCC_COUNT ) && ( RTC_COUNT == 1 ) */ +#endif /* EM_RTCC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h index 6847770..c1e1024 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_se.h @@ -1,640 +1,640 @@ -/***************************************************************************//** - * @file - * @brief Secure Element API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_SE_H -#define EM_SE_H - -#if defined(__linux__) - -#define SLI_EM_SE_HOST - -#else - -#include "em_device.h" - -#endif // __linux__ - -#include "sl_common.h" - -#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup se SE - Secure Element - * - * @brief Secure Element peripheral API - * - * @details - * Abstraction of the Secure Element's mailbox interface. - * - * For series 2 devices with a part number that is xG23 or higher, the - * following step is necessary for basic operation: - * - * Clock enable: - * @code - CMU_ClockEnable(cmuClock_SEMAILBOX, true);@endcode - * - * @note The high-level SE API has been moved to the SE manager, and the - * implementation in em_se should not be used. - * - * @note Using the SE's mailbox is not thread-safe in EMLIB, and accessing the - * SE's mailbox both in regular and IRQ context is not safe. SE operations - * should be performed using the SE manager if possible. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -#if defined(CRYPTOACC_PRESENT) -/** Root Code Mailbox is invalid. */ -#define SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL -/** Root Code Mailbox magic word */ -#define SE_RESPONSE_MAILBOX_VALID 0xE5ECC0DEUL -#endif - -/** Response status codes for the Secure Element */ -#define SE_RESPONSE_MASK 0x000F0000UL -/** Command executed successfully or signature was successfully validated. */ -#define SE_RESPONSE_OK 0x00000000UL - -/** Maximum amount of parameters supported by the hardware FIFO */ -#define SE_FIFO_MAX_PARAMETERS 13U - -/** Stop datatransfer */ -#define SE_DATATRANSFER_STOP 0x00000001UL -/** Discard datatransfer */ -#define SE_DATATRANSFER_DISCARD 0x40000000UL -/** Realign datatransfer */ -#define SE_DATATRANSFER_REALIGN 0x20000000UL -/** Datatransfer Const Address*/ -#define SE_DATATRANSFER_CONSTADDRESS 0x10000000UL -/** Stop Length Mask */ -#define SE_DATATRANSFER_LENGTH_MASK 0x0FFFFFFFUL - -/** Maximum amount of parameters for largest command in defined command set */ -#ifndef SE_MAX_PARAMETERS -#define SE_MAX_PARAMETERS 4U -#endif - -/* Sanity-check defines */ -#if SE_MAX_PARAMETERS > SE_FIFO_MAX_PARAMETERS -#error "Trying to configure more parameters than supported by the hardware" -#endif - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/** - * SE DMA transfer descriptor. Can be linked to each other to provide - * scatter-gather behavior. - */ -typedef struct { - volatile void* volatile data; /**< Data pointer */ - void* volatile next; /**< Next descriptor */ - volatile uint32_t length; /**< Length */ -} SE_DataTransfer_t; - -/** Default initialization of data transfer struct */ -#define SE_DATATRANSFER_DEFAULT(address, length) \ - { \ - (void*)(address), /* Pointer to data block */ \ - (void*)SE_DATATRANSFER_STOP, /* This is the last block by default */ \ - (length) | SE_DATATRANSFER_REALIGN /* Add size, use realign by default */ \ - } - -/** - * SE Command structure to which all commands to the SE must adhere. - */ -typedef struct { - uint32_t command; /**< SE Command */ - SE_DataTransfer_t* data_in; /**< Input data */ - SE_DataTransfer_t* data_out; /**< Output data */ - uint32_t parameters[SE_MAX_PARAMETERS];/**< Parameters */ - size_t num_parameters; /**< Number of parameters */ -} SE_Command_t; - -/** Default initialization of command struct */ -#define SE_COMMAND_DEFAULT(command) \ - { \ - (command), /* Given command */ \ - NULL, /* No data in */ \ - NULL, /* No data out */ \ - { 0, 0, 0, 0 }, /* No parameters */ \ - 0 /* No parameters */ \ - } - -/** Possible responses to a command */ -typedef uint32_t SE_Response_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void SE_addDataInput(SE_Command_t *command, - SE_DataTransfer_t *data); - -void SE_addDataOutput(SE_Command_t *command, - SE_DataTransfer_t *data); - -void SE_addParameter(SE_Command_t *command, uint32_t parameter); - -#if !defined(SLI_EM_SE_HOST) -void SE_executeCommand(SE_Command_t *command); -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(CRYPTOACC_PRESENT) -SE_Response_t SE_getVersion(uint32_t *version); -SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus); -SE_Response_t SE_getOTPVersion(uint32_t *otpVersion); -SE_Response_t SE_ackCommand(SE_Command_t *command); -#endif // #if defined(CRYPTOACC_PRESENT) - -// Utilities -#if defined(SEMAILBOX_PRESENT) -__STATIC_INLINE bool SE_isCommandCompleted(void); -__STATIC_INLINE SE_Response_t SE_readCommandResponse(void); -#elif defined(CRYPTOACC_PRESENT) -bool SE_isCommandCompleted(void); -uint32_t SE_readExecutedCommand(void); -SE_Response_t SE_readCommandResponse(void); -#endif // #if defined(SEMAILBOX_PRESENT) - -#if !defined(SLI_EM_SE_HOST) -__STATIC_INLINE void SE_waitCommandCompletion(void); -__STATIC_INLINE void SE_disableInterrupt(uint32_t flags); -__STATIC_INLINE void SE_enableInterrupt(uint32_t flags); -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Check whether the running command has completed. - * - * @details - * This function polls the SE-to-host mailbox interrupt flag. - * - * @return True if a command has completed and the result is available - ******************************************************************************/ -__STATIC_INLINE bool SE_isCommandCompleted(void) -{ - return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT); -} -#endif // #if defined(SEMAILBOX_PRESENT) - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Read the status of the previously executed command. - * - * @details - * This function reads the status of the previously executed command. - * - * @note - * The command response needs to be read for every executed command, and can - * only be read once per executed command (FIFO behavior). - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully or a signature - * was successfully verified. - ******************************************************************************/ -__STATIC_INLINE SE_Response_t SE_readCommandResponse(void) -{ - SE_waitCommandCompletion(); - return (SE_Response_t)(SEMAILBOX_HOST->RX_HEADER & SE_RESPONSE_MASK); -} -#endif // #if defined(SEMAILBOX_PRESENT) - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * Wait for completion of the current command. - * - * @details - * This function "busy"-waits until the execution of the ongoing instruction - * has completed. - ******************************************************************************/ -__STATIC_INLINE void SE_waitCommandCompletion(void) -{ - /* Wait for completion */ - while (!SE_isCommandCompleted()) { - } -} - -/***************************************************************************//** - * @brief - * Disable one or more SE interrupts. - * - * @param[in] flags - * SE interrupt sources to disable. Use a bitwise logic OR combination of - * valid interrupt flags for the Secure Element module - * (SE_CONFIGURATION_(TX/RX)INTEN). - ******************************************************************************/ -__STATIC_INLINE void SE_disableInterrupt(uint32_t flags) -{ -#if defined(SEMAILBOX_PRESENT) - SEMAILBOX_HOST->CONFIGURATION &= ~flags; -#else - (void) flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more SE interrupts. - * - * @param[in] flags - * SE interrupt sources to enable. Use a bitwise logic OR combination of - * valid interrupt flags for the Secure Element module - * (SEMAILBOX_CONFIGURATION_TXINTEN or SEMAILBOX_CONFIGURATION_RXINTEN). - ******************************************************************************/ -__STATIC_INLINE void SE_enableInterrupt(uint32_t flags) -{ -#if defined(SEMAILBOX_PRESENT) - SEMAILBOX_HOST->CONFIGURATION |= flags; -#else - (void) flags; -#endif -} - -#endif // #if !defined(SLI_EM_SE_HOST) - -/******************************************************************************* - ***************************** DEPRECATED ********************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup se_deprecated Deprecated Functions - * @brief Deprecated Functions - * - * @deprecated - * The following functions have been deprecated and will be removed in a - * future version of EMLIB. All high-level functionality have been moved to - * the SE manager. - * - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ - -#if !defined(SLI_EM_SE_HOST) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(SEMAILBOX_PRESENT) -/* Command words for the Security Engine. */ -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_WRAP_KEY 0x01000000UL -#define SE_COMMAND_UNWRAP_KEY 0x01020000UL -#define SE_COMMAND_TRANSFER_KEY 0x01060000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_CREATE_KEY 0x02000000UL -#define SE_COMMAND_READPUB_KEY 0x02010000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_DERIVE_KEY_PBKDF2 0x02020002UL -#define SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_HASH 0x03000000UL -#define SE_COMMAND_HASHUPDATE 0x03010000UL -#define SE_COMMAND_HMAC 0x03020000UL - -#define SE_COMMAND_AES_ENCRYPT 0x04000000UL -#define SE_COMMAND_AES_DECRYPT 0x04010000UL -#define SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL -#define SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL -#define SE_COMMAND_AES_CMAC 0x04040000UL -#define SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL -#define SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL - -#define SE_COMMAND_SIGNATURE_SIGN 0x06000000UL -#define SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_EDDSA_SIGN 0x06020000UL -#define SE_COMMAND_EDDSA_VERIFY 0x06030000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL -#define SE_COMMAND_READ_CLOCK 0x07020000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_ATTEST_CERTIFY 0x0A000000UL -#define SE_COMMAND_ATTEST_TIME 0x0A010000UL -#define SE_COMMAND_ATTEST_PUBKEY 0x0A020000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL -#define SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL -#define SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL -#define SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL -#define SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -#define SE_COMMAND_AEAD_ENCRYPT 0x0C000000UL -#define SE_COMMAND_AEAD_DECRYPT 0x0C010000UL -#define SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL -#define SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL -#define SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -#define SE_COMMAND_DH 0x0E000000UL - -#endif // #if defined(SEMAILBOX_PRESENT) - -#define SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL -#define SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL -#define SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL -#define SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL -#define SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL -#define SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL - -#if defined(SEMAILBOX_PRESENT) - -#define SE_COMMAND_STATUS_SE_VERSION 0x43080000UL -#define SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL - -#define SE_COMMAND_WRITE_USER_DATA 0x43090000UL -#define SE_COMMAND_ERASE_USER_DATA 0x430A0000UL - -#define SE_COMMAND_DBG_LOCK_APPLY 0x430C0000 -#define SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000 -#define SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000 -#define SE_COMMAND_DEVICE_ERASE 0x430F0000 -#define SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000 -#define SE_COMMAND_DBG_LOCK_STATUS 0x43110000 - -#define SE_COMMAND_PROTECTED_REGISTER 0x43210000 - -#define SE_COMMAND_GET_CHALLENGE 0xFD000000UL -#define SE_COMMAND_ROLL_CHALLENGE 0xFD000100UL -#define SE_COMMAND_OPEN_DEBUG 0xFD010001UL -#define SE_COMMAND_DISABLE_TAMPER 0xFD020001UL - -#define SE_COMMAND_READ_SERIAL 0xFE000000UL -#define SE_COMMAND_GET_STATUS 0xFE010000UL -#define SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL - -#define SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL -#define SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL - -#define SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL -#define SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL -#endif /* SEMAILBOX_PRESENT */ - -#if defined(SEMAILBOX_PRESENT) -/* Command options for the Secure Element commands. */ -/** Use MD5 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_MD5 0x00000100UL -/** Use SHA1 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL -/** Use SHA224 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL -/** Use SHA256 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -/** Use SHA384 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL -/** Use SHA512 as hash algorithm */ -#define SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL -#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ - -/** Execute algorithm in ECB mode */ -#define SE_COMMAND_OPTION_MODE_ECB 0x00000100UL -/** Execute algorithm in CBC mode */ -#define SE_COMMAND_OPTION_MODE_CBC 0x00000200UL -/** Execute algorithm in CTR mode */ -#define SE_COMMAND_OPTION_MODE_CTR 0x00000300UL -/** Execute algorithm in CFB mode */ -#define SE_COMMAND_OPTION_MODE_CFB 0x00000400UL -/** Execute algorithm in OFB mode */ -#define SE_COMMAND_OPTION_MODE_OFB 0x00000500UL -/** Execute algorithm in XTS mode */ -#define SE_COMMAND_OPTION_MODE_XTS 0x00000800UL - -#define SE_COMMAND_OPTION_CERT_DEVICE 0x00000100UL -#define SE_COMMAND_OPTION_CERT_BATCH 0x00000200UL -#define SE_COMMAND_OPTION_CERT_FACTORY 0x00000300UL - -/** Pubkey type */ -#define SE_KEY_TYPE_ROOT 0x00000300UL - -/** Run the whole algorithm, all data present */ -#define SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL -/** Start the algorithm, but get a context to later add more data */ -#define SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL -/** End the algorithm, get the result */ -#define SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL -/** Add more data input to the algorithm. Need to supply previous context, - * and get a context back */ -#define SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL - -/** Padding options for signature functionality. */ -#define SE_COMMAND_OPTION_PADDING_NONE 0x00000000UL -#define SE_COMMAND_OPTION_PADDING_EMSA_PKCS 0x00000003UL -#define SE_COMMAND_OPTION_PADDING_PSS 0x00000004UL - -/* Special parameters for the Secure Element commands. */ -#define SE_COMMAND_OPTION_READ 0x00000000UL -#define SE_COMMAND_OPTION_WRITE 0x00000100UL - -/** Magic parameter for deleting user data */ -#define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL - -#endif /* SEMAILBOX_PRESENT */ - -/** Pubkey types */ -#define SE_KEY_TYPE_BOOT 0x00000100UL -#define SE_KEY_TYPE_AUTH 0x00000200UL - -#define SE_COMMAND_INIT_OTP 0xFF000001UL -#define SE_COMMAND_INIT_PUBKEY 0xFF070001UL - -#define SE_COMMAND_READ_PUBKEY 0xFF080001UL - -/** - * Command was not recognized as a valid command, or is not allowed in the - * current context. - */ -#define SE_RESPONSE_INVALID_COMMAND 0x00010000UL -/** - * User did not provide the required credentials to be allowed to execute the - * command. - */ -#define SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL -/** - * Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to - * verify the given signature as being correct. - */ -#define SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL -/** A command started in non-secure mode is trying to access secure memory. */ -#define SE_RESPONSE_BUS_ERROR 0x00040000UL -/** Internal error */ -#define SE_RESPONSE_INTERNAL_ERROR 0x00050000UL -/** An internal error was raised and the command did not execute. */ -#define SE_RESPONSE_CRYPTO_ERROR 0x00060000UL -/** One of the passed parameters is deemed invalid (e.g. out of bounds). */ -#define SE_RESPONSE_INVALID_PARAMETER 0x00070000UL -/** Failure while checking the host for secure boot */ -#define SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL -/** Failure during selftest */ -#define SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL -/** Feature/item not initialized or not present */ -#define SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL -/* Abort status code is given when no operation is attempted. */ -#define SE_RESPONSE_ABORT 0x00FF0000UL - -/** @endcond */ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ - -/** SE OTP initialization struct */ -typedef struct { - /** Enable secure boot for the host. */ - bool enableSecureBoot; - /** Require certificate based secure boot signing. */ - bool verifySecureBootCertificate; - /** Enable anti-rollback for host application upgrades. */ - bool enableAntiRollback; - - /** Set flag to enable locking down all flash pages that cover the - * secure-booted image, except the last page if end of signature is not - * page-aligned. */ - bool secureBootPageLockNarrow; - /** Set flag to enable locking down all flash pages that cover the - * secure-booted image, including the last page if end of signature is not - * page-aligned. */ - bool secureBootPageLockFull; -} SE_OTPInit_t; - -/** SE debug status */ -typedef struct { - /** Whether debug lock is enabled */ - bool debugLockEnabled; - /** Whether device erase is enabled */ - bool deviceEraseEnabled; - /** Whether secure debug is enabled */ - bool secureDebugEnabled; -} SE_DebugStatus_t; - -/** SE status */ -typedef struct { - /** Boot status code / error code (Bits [7:0]). */ - uint32_t bootStatus; - /** SE firmware version. */ - uint32_t seFwVersion; - /** Host firmware version (if available). */ - uint32_t hostFwVersion; - /** Debug lock status. */ - SE_DebugStatus_t debugStatus; - /** Secure boot enabled. */ - bool secureBootEnabled; -} SE_Status_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_initPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) -SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_initPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) SL_DEPRECATED_API_SDK_4_4; - -#if defined(SEMAILBOX_PRESENT) - -// User data commands -SE_Response_t SE_writeUserData(uint32_t offset, - void *data, - uint32_t numBytes) -SL_DEPRECATED_API_SDK_3_0; - -SE_Response_t SE_eraseUserData(void) SL_DEPRECATED_API_SDK_3_0; - -// Initialization commands -SE_Response_t SE_readPubkey(uint32_t key_type, - void* pubkey, - uint32_t numBytes, - bool signature) SL_DEPRECATED_API_SDK_4_4; - -// Debug commands -SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugLockApply(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugSecureEnable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_debugSecureDisable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_deviceEraseDisable(void) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_deviceErase(void) SL_DEPRECATED_API_SDK_3_0; - -// Device status commands -SE_Response_t SE_getStatus(SE_Status_t *output) SL_DEPRECATED_API_SDK_3_0; -SE_Response_t SE_serialNumber(void *serial) SL_DEPRECATED_API_SDK_3_0; - -#endif // #if defined(SEMAILBOX_PRESENT) -#endif // #if !defined(SLI_EM_SE_HOST) - -/** @} (end addtogroup se_deprecated) */ - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup se) */ - -#endif /* defined(SEMAILBOX_PRESENT) - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) */ - -#endif /* EM_SE_H */ +/***************************************************************************//** + * @file + * @brief Secure Element API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_SE_H +#define EM_SE_H + +#if defined(__linux__) + +#define SLI_EM_SE_HOST + +#else + +#include "em_device.h" + +#endif // __linux__ + +#include "sl_common.h" + +#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup se SE - Secure Element + * + * @brief Secure Element peripheral API + * + * @details + * Abstraction of the Secure Element's mailbox interface. + * + * For series 2 devices with a part number that is xG23 or higher, the + * following step is necessary for basic operation: + * + * Clock enable: + * @code + CMU_ClockEnable(cmuClock_SEMAILBOX, true);@endcode + * + * @note The high-level SE API has been moved to the SE manager, and the + * implementation in em_se should not be used. + * + * @note Using the SE's mailbox is not thread-safe in EMLIB, and accessing the + * SE's mailbox both in regular and IRQ context is not safe. SE operations + * should be performed using the SE manager if possible. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +#if defined(CRYPTOACC_PRESENT) +/** Root Code Mailbox is invalid. */ +#define SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL +/** Root Code Mailbox magic word */ +#define SE_RESPONSE_MAILBOX_VALID 0xE5ECC0DEUL +#endif + +/** Response status codes for the Secure Element */ +#define SE_RESPONSE_MASK 0x000F0000UL +/** Command executed successfully or signature was successfully validated. */ +#define SE_RESPONSE_OK 0x00000000UL + +/** Maximum amount of parameters supported by the hardware FIFO */ +#define SE_FIFO_MAX_PARAMETERS 13U + +/** Stop datatransfer */ +#define SE_DATATRANSFER_STOP 0x00000001UL +/** Discard datatransfer */ +#define SE_DATATRANSFER_DISCARD 0x40000000UL +/** Realign datatransfer */ +#define SE_DATATRANSFER_REALIGN 0x20000000UL +/** Datatransfer Const Address*/ +#define SE_DATATRANSFER_CONSTADDRESS 0x10000000UL +/** Stop Length Mask */ +#define SE_DATATRANSFER_LENGTH_MASK 0x0FFFFFFFUL + +/** Maximum amount of parameters for largest command in defined command set */ +#ifndef SE_MAX_PARAMETERS +#define SE_MAX_PARAMETERS 4U +#endif + +/* Sanity-check defines */ +#if SE_MAX_PARAMETERS > SE_FIFO_MAX_PARAMETERS +#error "Trying to configure more parameters than supported by the hardware" +#endif + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/** + * SE DMA transfer descriptor. Can be linked to each other to provide + * scatter-gather behavior. + */ +typedef struct { + volatile void* volatile data; /**< Data pointer */ + void* volatile next; /**< Next descriptor */ + volatile uint32_t length; /**< Length */ +} SE_DataTransfer_t; + +/** Default initialization of data transfer struct */ +#define SE_DATATRANSFER_DEFAULT(address, length) \ + { \ + (void*)(address), /* Pointer to data block */ \ + (void*)SE_DATATRANSFER_STOP, /* This is the last block by default */ \ + (length) | SE_DATATRANSFER_REALIGN /* Add size, use realign by default */ \ + } + +/** + * SE Command structure to which all commands to the SE must adhere. + */ +typedef struct { + uint32_t command; /**< SE Command */ + SE_DataTransfer_t* data_in; /**< Input data */ + SE_DataTransfer_t* data_out; /**< Output data */ + uint32_t parameters[SE_MAX_PARAMETERS];/**< Parameters */ + size_t num_parameters; /**< Number of parameters */ +} SE_Command_t; + +/** Default initialization of command struct */ +#define SE_COMMAND_DEFAULT(command) \ + { \ + (command), /* Given command */ \ + NULL, /* No data in */ \ + NULL, /* No data out */ \ + { 0, 0, 0, 0 }, /* No parameters */ \ + 0 /* No parameters */ \ + } + +/** Possible responses to a command */ +typedef uint32_t SE_Response_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void SE_addDataInput(SE_Command_t *command, + SE_DataTransfer_t *data); + +void SE_addDataOutput(SE_Command_t *command, + SE_DataTransfer_t *data); + +void SE_addParameter(SE_Command_t *command, uint32_t parameter); + +#if !defined(SLI_EM_SE_HOST) +void SE_executeCommand(SE_Command_t *command); +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(CRYPTOACC_PRESENT) +SE_Response_t SE_getVersion(uint32_t *version); +SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus); +SE_Response_t SE_getOTPVersion(uint32_t *otpVersion); +SE_Response_t SE_ackCommand(SE_Command_t *command); +#endif // #if defined(CRYPTOACC_PRESENT) + +// Utilities +#if defined(SEMAILBOX_PRESENT) +__STATIC_INLINE bool SE_isCommandCompleted(void); +__STATIC_INLINE SE_Response_t SE_readCommandResponse(void); +#elif defined(CRYPTOACC_PRESENT) +bool SE_isCommandCompleted(void); +uint32_t SE_readExecutedCommand(void); +SE_Response_t SE_readCommandResponse(void); +#endif // #if defined(SEMAILBOX_PRESENT) + +#if !defined(SLI_EM_SE_HOST) +__STATIC_INLINE void SE_waitCommandCompletion(void); +__STATIC_INLINE void SE_disableInterrupt(uint32_t flags); +__STATIC_INLINE void SE_enableInterrupt(uint32_t flags); +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Check whether the running command has completed. + * + * @details + * This function polls the SE-to-host mailbox interrupt flag. + * + * @return True if a command has completed and the result is available + ******************************************************************************/ +__STATIC_INLINE bool SE_isCommandCompleted(void) +{ + return (bool)(SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT); +} +#endif // #if defined(SEMAILBOX_PRESENT) + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Read the status of the previously executed command. + * + * @details + * This function reads the status of the previously executed command. + * + * @note + * The command response needs to be read for every executed command, and can + * only be read once per executed command (FIFO behavior). + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully or a signature + * was successfully verified. + ******************************************************************************/ +__STATIC_INLINE SE_Response_t SE_readCommandResponse(void) +{ + SE_waitCommandCompletion(); + return (SE_Response_t)(SEMAILBOX_HOST->RX_HEADER & SE_RESPONSE_MASK); +} +#endif // #if defined(SEMAILBOX_PRESENT) + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * Wait for completion of the current command. + * + * @details + * This function "busy"-waits until the execution of the ongoing instruction + * has completed. + ******************************************************************************/ +__STATIC_INLINE void SE_waitCommandCompletion(void) +{ + /* Wait for completion */ + while (!SE_isCommandCompleted()) { + } +} + +/***************************************************************************//** + * @brief + * Disable one or more SE interrupts. + * + * @param[in] flags + * SE interrupt sources to disable. Use a bitwise logic OR combination of + * valid interrupt flags for the Secure Element module + * (SE_CONFIGURATION_(TX/RX)INTEN). + ******************************************************************************/ +__STATIC_INLINE void SE_disableInterrupt(uint32_t flags) +{ +#if defined(SEMAILBOX_PRESENT) + SEMAILBOX_HOST->CONFIGURATION &= ~flags; +#else + (void) flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more SE interrupts. + * + * @param[in] flags + * SE interrupt sources to enable. Use a bitwise logic OR combination of + * valid interrupt flags for the Secure Element module + * (SEMAILBOX_CONFIGURATION_TXINTEN or SEMAILBOX_CONFIGURATION_RXINTEN). + ******************************************************************************/ +__STATIC_INLINE void SE_enableInterrupt(uint32_t flags) +{ +#if defined(SEMAILBOX_PRESENT) + SEMAILBOX_HOST->CONFIGURATION |= flags; +#else + (void) flags; +#endif +} + +#endif // #if !defined(SLI_EM_SE_HOST) + +/******************************************************************************* + ***************************** DEPRECATED ********************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup se_deprecated Deprecated Functions + * @brief Deprecated Functions + * + * @deprecated + * The following functions have been deprecated and will be removed in a + * future version of EMLIB. All high-level functionality have been moved to + * the SE manager. + * + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ + +#if !defined(SLI_EM_SE_HOST) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(SEMAILBOX_PRESENT) +/* Command words for the Security Engine. */ +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_WRAP_KEY 0x01000000UL +#define SE_COMMAND_UNWRAP_KEY 0x01020000UL +#define SE_COMMAND_TRANSFER_KEY 0x01060000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_CREATE_KEY 0x02000000UL +#define SE_COMMAND_READPUB_KEY 0x02010000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_DERIVE_KEY_PBKDF2 0x02020002UL +#define SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_HASH 0x03000000UL +#define SE_COMMAND_HASHUPDATE 0x03010000UL +#define SE_COMMAND_HMAC 0x03020000UL + +#define SE_COMMAND_AES_ENCRYPT 0x04000000UL +#define SE_COMMAND_AES_DECRYPT 0x04010000UL +#define SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL +#define SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL +#define SE_COMMAND_AES_CMAC 0x04040000UL +#define SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL +#define SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL + +#define SE_COMMAND_SIGNATURE_SIGN 0x06000000UL +#define SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_EDDSA_SIGN 0x06020000UL +#define SE_COMMAND_EDDSA_VERIFY 0x06030000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL +#define SE_COMMAND_READ_CLOCK 0x07020000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_ATTEST_CERTIFY 0x0A000000UL +#define SE_COMMAND_ATTEST_TIME 0x0A010000UL +#define SE_COMMAND_ATTEST_PUBKEY 0x0A020000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL +#define SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL +#define SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL +#define SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL +#define SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +#define SE_COMMAND_AEAD_ENCRYPT 0x0C000000UL +#define SE_COMMAND_AEAD_DECRYPT 0x0C010000UL +#define SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL +#define SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL +#define SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +#define SE_COMMAND_DH 0x0E000000UL + +#endif // #if defined(SEMAILBOX_PRESENT) + +#define SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL +#define SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL +#define SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL +#define SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL +#define SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL +#define SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL + +#if defined(SEMAILBOX_PRESENT) + +#define SE_COMMAND_STATUS_SE_VERSION 0x43080000UL +#define SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL + +#define SE_COMMAND_WRITE_USER_DATA 0x43090000UL +#define SE_COMMAND_ERASE_USER_DATA 0x430A0000UL + +#define SE_COMMAND_DBG_LOCK_APPLY 0x430C0000 +#define SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000 +#define SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000 +#define SE_COMMAND_DEVICE_ERASE 0x430F0000 +#define SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000 +#define SE_COMMAND_DBG_LOCK_STATUS 0x43110000 + +#define SE_COMMAND_PROTECTED_REGISTER 0x43210000 + +#define SE_COMMAND_GET_CHALLENGE 0xFD000000UL +#define SE_COMMAND_ROLL_CHALLENGE 0xFD000100UL +#define SE_COMMAND_OPEN_DEBUG 0xFD010001UL +#define SE_COMMAND_DISABLE_TAMPER 0xFD020001UL + +#define SE_COMMAND_READ_SERIAL 0xFE000000UL +#define SE_COMMAND_GET_STATUS 0xFE010000UL +#define SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL + +#define SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL +#define SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL + +#define SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL +#define SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL +#endif /* SEMAILBOX_PRESENT */ + +#if defined(SEMAILBOX_PRESENT) +/* Command options for the Secure Element commands. */ +/** Use MD5 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_MD5 0x00000100UL +/** Use SHA1 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL +/** Use SHA224 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL +/** Use SHA256 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +/** Use SHA384 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL +/** Use SHA512 as hash algorithm */ +#define SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL +#endif /* _SILICON_LABS_SECURITY_FEATURE_VAULT */ + +/** Execute algorithm in ECB mode */ +#define SE_COMMAND_OPTION_MODE_ECB 0x00000100UL +/** Execute algorithm in CBC mode */ +#define SE_COMMAND_OPTION_MODE_CBC 0x00000200UL +/** Execute algorithm in CTR mode */ +#define SE_COMMAND_OPTION_MODE_CTR 0x00000300UL +/** Execute algorithm in CFB mode */ +#define SE_COMMAND_OPTION_MODE_CFB 0x00000400UL +/** Execute algorithm in OFB mode */ +#define SE_COMMAND_OPTION_MODE_OFB 0x00000500UL +/** Execute algorithm in XTS mode */ +#define SE_COMMAND_OPTION_MODE_XTS 0x00000800UL + +#define SE_COMMAND_OPTION_CERT_DEVICE 0x00000100UL +#define SE_COMMAND_OPTION_CERT_BATCH 0x00000200UL +#define SE_COMMAND_OPTION_CERT_FACTORY 0x00000300UL + +/** Pubkey type */ +#define SE_KEY_TYPE_ROOT 0x00000300UL + +/** Run the whole algorithm, all data present */ +#define SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL +/** Start the algorithm, but get a context to later add more data */ +#define SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL +/** End the algorithm, get the result */ +#define SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL +/** Add more data input to the algorithm. Need to supply previous context, + * and get a context back */ +#define SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL + +/** Padding options for signature functionality. */ +#define SE_COMMAND_OPTION_PADDING_NONE 0x00000000UL +#define SE_COMMAND_OPTION_PADDING_EMSA_PKCS 0x00000003UL +#define SE_COMMAND_OPTION_PADDING_PSS 0x00000004UL + +/* Special parameters for the Secure Element commands. */ +#define SE_COMMAND_OPTION_READ 0x00000000UL +#define SE_COMMAND_OPTION_WRITE 0x00000100UL + +/** Magic parameter for deleting user data */ +#define SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL + +#endif /* SEMAILBOX_PRESENT */ + +/** Pubkey types */ +#define SE_KEY_TYPE_BOOT 0x00000100UL +#define SE_KEY_TYPE_AUTH 0x00000200UL + +#define SE_COMMAND_INIT_OTP 0xFF000001UL +#define SE_COMMAND_INIT_PUBKEY 0xFF070001UL + +#define SE_COMMAND_READ_PUBKEY 0xFF080001UL + +/** + * Command was not recognized as a valid command, or is not allowed in the + * current context. + */ +#define SE_RESPONSE_INVALID_COMMAND 0x00010000UL +/** + * User did not provide the required credentials to be allowed to execute the + * command. + */ +#define SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL +/** + * Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to + * verify the given signature as being correct. + */ +#define SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL +/** A command started in non-secure mode is trying to access secure memory. */ +#define SE_RESPONSE_BUS_ERROR 0x00040000UL +/** Internal error */ +#define SE_RESPONSE_INTERNAL_ERROR 0x00050000UL +/** An internal error was raised and the command did not execute. */ +#define SE_RESPONSE_CRYPTO_ERROR 0x00060000UL +/** One of the passed parameters is deemed invalid (e.g. out of bounds). */ +#define SE_RESPONSE_INVALID_PARAMETER 0x00070000UL +/** Failure while checking the host for secure boot */ +#define SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL +/** Failure during selftest */ +#define SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL +/** Feature/item not initialized or not present */ +#define SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL +/* Abort status code is given when no operation is attempted. */ +#define SE_RESPONSE_ABORT 0x00FF0000UL + +/** @endcond */ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ + +/** SE OTP initialization struct */ +typedef struct { + /** Enable secure boot for the host. */ + bool enableSecureBoot; + /** Require certificate based secure boot signing. */ + bool verifySecureBootCertificate; + /** Enable anti-rollback for host application upgrades. */ + bool enableAntiRollback; + + /** Set flag to enable locking down all flash pages that cover the + * secure-booted image, except the last page if end of signature is not + * page-aligned. */ + bool secureBootPageLockNarrow; + /** Set flag to enable locking down all flash pages that cover the + * secure-booted image, including the last page if end of signature is not + * page-aligned. */ + bool secureBootPageLockFull; +} SE_OTPInit_t; + +/** SE debug status */ +typedef struct { + /** Whether debug lock is enabled */ + bool debugLockEnabled; + /** Whether device erase is enabled */ + bool deviceEraseEnabled; + /** Whether secure debug is enabled */ + bool secureDebugEnabled; +} SE_DebugStatus_t; + +/** SE status */ +typedef struct { + /** Boot status code / error code (Bits [7:0]). */ + uint32_t bootStatus; + /** SE firmware version. */ + uint32_t seFwVersion; + /** Host firmware version (if available). */ + uint32_t hostFwVersion; + /** Debug lock status. */ + SE_DebugStatus_t debugStatus; + /** Secure boot enabled. */ + bool secureBootEnabled; +} SE_Status_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_initPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) +SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_initPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) SL_DEPRECATED_API_SDK_4_4; + +#if defined(SEMAILBOX_PRESENT) + +// User data commands +SE_Response_t SE_writeUserData(uint32_t offset, + void *data, + uint32_t numBytes) +SL_DEPRECATED_API_SDK_3_0; + +SE_Response_t SE_eraseUserData(void) SL_DEPRECATED_API_SDK_3_0; + +// Initialization commands +SE_Response_t SE_readPubkey(uint32_t key_type, + void* pubkey, + uint32_t numBytes, + bool signature) SL_DEPRECATED_API_SDK_4_4; + +// Debug commands +SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugLockApply(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugSecureEnable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_debugSecureDisable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_deviceEraseDisable(void) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_deviceErase(void) SL_DEPRECATED_API_SDK_3_0; + +// Device status commands +SE_Response_t SE_getStatus(SE_Status_t *output) SL_DEPRECATED_API_SDK_3_0; +SE_Response_t SE_serialNumber(void *serial) SL_DEPRECATED_API_SDK_3_0; + +#endif // #if defined(SEMAILBOX_PRESENT) +#endif // #if !defined(SLI_EM_SE_HOST) + +/** @} (end addtogroup se_deprecated) */ + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup se) */ + +#endif /* defined(SEMAILBOX_PRESENT) + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) */ + +#endif /* EM_SE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h index 2f448f9..10826f4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_smu.h @@ -1,1712 +1,1712 @@ -/***************************************************************************//** - * @file - * @brief Security Management Unit (SMU) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SMU_H -#define EM_SMU_H - -#include "em_device.h" -#if defined(SMU_COUNT) && (SMU_COUNT > 0) - -#include "sl_assert.h" -#include "em_bus.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup smu SMU - Security Management Unit - * @brief Security Management Unit (SMU) Peripheral API - * - * @details - * SMU forms the control and status/reporting component of bus-level - * security in EFM32/EFR32 devices. - * - * Peripheral-level protection is provided via the Peripheral Protection Unit - * (PPU). PPU provides hardware access barrier to any peripheral that is - * configured to be protected. When an attempt is made to access a peripheral - * without the required privilege/security level, PPU detects the fault - * and intercepts the access. No write or read of the peripheral register - * space occurs, and an all-zero value is returned if the access is a read. - * - * Usage example - * @include em_smu_init.c - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** SMU peripheral identifiers. */ -typedef enum { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ -#if defined(_SMU_PPUPATD0_CSEN_SHIFT) - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ -#endif -#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ -#endif - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ -#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ -#endif - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#if defined(_SMU_PPUPATD0_ACMP0_SHIFT) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ -#endif -#if defined(_SMU_PPUPATD0_ACMP1_SHIFT) - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ -#endif -#if defined(_SMU_PPUPATD0_ADC0_SHIFT) - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ -#endif - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ -#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ -#endif - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ -#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ -#endif - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ -#if defined(_SMU_PPUPATD0_LESENSE_SHIFT) - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ -#endif - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ -#if defined(_SMU_PPUPATD0_PCNT0_SHIFT) - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ -#endif - smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ - smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ -#if defined(_SMU_PPUPATD0_ETH_SHIFT) - smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ -#endif - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ - smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ -#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) - smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ -#endif - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ -#if defined(_SMU_PPUPATD1_SDIO_SHIFT) - smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ - smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ - smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */ - smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */ - smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ - smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */ -#if defined(_SMU_PPUPATD1_USB_SHIFT) - smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */ - smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ -#if defined(_SMU_PPUPATD0_ETH_SHIFT) - smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ -#endif - smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ - smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ - smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ -#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) - smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ -#endif - smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ -#if defined(_SMU_PPUPATD1_SDIO_SHIFT) - smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ - smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ - smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ - smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ - smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ -#if defined(_SMU_PPUPATD1_USB_SHIFT) - smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ - smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ - smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ - smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ - smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ - smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ - smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ - smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ - smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ -#if defined(_SMU_PPUPATD0_LCD_SHIFT) - smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ -#endif - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ - smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ - smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ - smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ - smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ - smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ - smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ - smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */ - smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ - smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ - smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ - smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ - smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ - smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ - smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ - smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ - -#elif defined(_SILICON_LABS_32B_SERIES_2) -#if defined(SMU_PPUPATD0_SCRATCHPAD) - smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */ -#endif - smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ - smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ -#if defined(_SMU_PPUPATD0_HFXO0_SHIFT) - smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif -#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) - smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif - smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */ - smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */ - smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */ - smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */ - smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */ - smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */ - smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ - smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */ - smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ - smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ - smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ - smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */ - smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ - smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ - smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */ - smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */ -#if defined(_SMU_PPUPATD0_TIMER4_SHIFT) - smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER5_SHIFT) - smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER6_SHIFT) - smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */ -#endif -#if defined(_SMU_PPUPATD0_TIMER7_SHIFT) - smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */ -#endif -#if defined(_SMU_PPUPATD0_USART0_SHIFT) - smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ -#endif -#if defined(_SMU_PPUPATD0_USART1_SHIFT) - smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ -#endif -#if defined(_SMU_PPUPATD0_USART2_SHIFT) - smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ -#endif - smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */ -#if defined(_SMU_PPUPATD0_I2C1_SHIFT) - smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ -#endif -#if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT) - smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */ -#endif -#if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT) - smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */ -#endif - -#if defined(SMU_PPUPATD0_LVGD) - smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */ -#endif - smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */ -#if defined(_SMU_PPUPATD0_BURAM_SHIFT) - smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ -#endif -#if defined(_SMU_PPUPATD1_BURAM_SHIFT) - smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ -#endif -#if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT) - smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/ -#endif -#if defined(_SMU_PPUPATD0_GPCRC_SHIFT) - smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ -#endif -#if defined(_SMU_PPUPATD1_GPCRC_SHIFT) - smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ -#endif -#if defined(_SMU_PPUPATD0_DCDC_SHIFT) - smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ -#endif -#if defined(_SMU_PPUPATD0_RTCC_SHIFT) - smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ -#endif -#if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT) - smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */ -#endif -#if defined(_SMU_PPUPATD1_EUSART0_SHIFT) - smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */ -#endif -#if defined(_SMU_PPUPATD0_EUSART1_SHIFT) - smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART1_SHIFT) - smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ -#endif -#if defined(_SMU_PPUPATD0_EUSART2_SHIFT) - smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART2_SHIFT) - smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART3_SHIFT) - smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */ -#endif -#if defined(_SMU_PPUPATD1_EUSART4_SHIFT) - smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */ -#endif -#if defined(_SMU_PPUPATD1_RTCC_SHIFT) - smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ -#endif -#if defined(_SMU_PPUPATD1_SYSRTC_SHIFT) - smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */ -#endif -#if defined(_SMU_PPUPATD1_LCD_SHIFT) - smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */ -#endif -#if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT) - smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */ -#endif -#if defined(_SMU_PPUPATD1_DMEM_SHIFT) - smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */ -#endif -#if defined(_SMU_PPUPATD1_LCDRF_SHIFT) - smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */ -#endif -#if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT) - smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */ -#endif -#if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT) - smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */ -#endif -#if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT) - smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */ -#endif -#if defined(_SMU_PPUPATD1_VDAC0_SHIFT) - smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ -#endif -#if defined(_SMU_PPUPATD1_VDAC1_SHIFT) - smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */ -#endif -#if defined(_SMU_PPUPATD1_PCNT_SHIFT) - smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */ -#endif -#if defined(_SMU_PPUPATD1_LESENSE_SHIFT) - smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ -#endif -#if defined(_SMU_PPUPATD1_HFRCO1_SHIFT) - smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */ -#endif -#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) - smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ -#endif -#if defined(_SMU_PPUPATD1_DCDC_SHIFT) - smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ -#endif -#if defined(_SMU_PPUPATD1_PDM_SHIFT) - smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */ -#endif -#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT) - smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */ -#endif -#if defined(_SMU_PPUPATD1_SEPUF_SHIFT) - smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */ -#endif - smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */ -#if defined(_SMU_PPUPATD1_IADC0_SHIFT) - smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */ -#endif -#if defined(_SMU_PPUPATD1_ACMP0_SHIFT) - smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ -#endif -#if defined(_SMU_PPUPATD1_ACMP1_SHIFT) - smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ -#endif -#if defined(_SMU_PPUPATD1_I2C0_SHIFT) - smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ -#endif -#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT) - smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */ -#endif - smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ -#if defined(_SMU_PPUPATD1_WDOG1_SHIFT) - smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ -#endif - smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */ -#if defined(_SMU_PPUPATD1_RADIOAES_SHIFT) - smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */ -#endif -#if defined(_SMU_PPUPATD1_EUART0_SHIFT) - smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */ -#endif -#if defined(_SMU_PPUPATD1_BUFC_SHIFT) - smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */ -#endif - smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ -#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT) - smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */ -#endif -#if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT) - smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */ -#endif -#if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT) - smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */ -#endif -#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT) - smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */ -#endif -#if defined(_SMU_PPUPATD1_MVP_SHIFT) - smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */ -#endif -#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT) - smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */ -#endif -#else -#error "No peripherals defined for SMU for this device configuration." -#endif - smuPeripheralEnd /**< SMU peripheral end. */ -} SMU_Peripheral_TypeDef; - -/** SMU peripheral privileged access enablers. */ -typedef struct { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - - bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ - bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedETH : 1; /**< Privileged access enabler for ETH. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ - bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */ - bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */ - bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ - bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ - bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ - bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ - bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ - bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ - bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ - bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ - bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ - bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ - bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ - bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ - bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ - bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ - bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ - bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ - bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ - bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ - bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */ - bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ - bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ - bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ - bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ - bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ - bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ - bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ - bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ - bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ - bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ - bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ - bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ - - bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ - bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */ - bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - - bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ - bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ - bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */ - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */ - bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ - bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ - bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ - bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ - bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */ - bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */ - bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ - bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */ - bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ - bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ - - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ - bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ - bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ - bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ - bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ - bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ - bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ - bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ - bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ - bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ - bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ - bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ - bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ - bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ - bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ - bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ - bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ - bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ - bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ - bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ - bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ - bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ - bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ - bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ - bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ - bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ - bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ - bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ - bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ - bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ - bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ - bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ - bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ - bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ - bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ - - bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ - bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ - bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ - bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ - bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ - bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ - bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ - bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ - bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ - bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ - bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ - bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ - bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ - bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ - bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ - bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ - bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ - bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ - bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ - bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ - bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ - bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ - bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ - bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ - bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ - bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ - -#else -#error "No peripherals defined for SMU for this device configuration" -#endif -} SMU_PrivilegedAccess_TypeDef; - -/******************************************************************************* - ****************************** STRUCTS ************************************ - ******************************************************************************/ - -/** SMU initialization structure. */ -typedef struct { - union { -#if defined(_SMU_PPUNSPATD2_MASK) - uint32_t reg[3]; /**< Peripheral access control array.*/ -#else - uint32_t reg[2]; /**< Peripheral access control array.*/ -#endif - SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/ - } ppu; /**< PPU init array.*/ - bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/ -} SMU_Init_TypeDef; - -/** Default SMU initialization structure settings. */ -#define SMU_INIT_DEFAULT { \ - { { 0 } }, /* No peripherals access protected. */ \ - true /* Enable SMU.*/ \ -} - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Enable or disable PPU of SMU. - * - * @param[in] enable - * Set to true to enable PPU; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void SMU_EnablePPU(bool enable) -{ -#if defined (_SMU_PPUCTRL_ENABLE_SHIFT) - BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); -#else - (void)enable; -#endif -} - -/***************************************************************************//** - * @brief - * Initialize PPU of SMU. - * - * @param[in] init - * Pointer to initialization structure that defines which peripherals should - * only be accessed from privileged mode, and if PPU should be enabled. - ******************************************************************************/ -__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0]; - SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1]; -#if defined(_SMU_PPUNSPATD2_MASK) - SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2]; -#endif //defined(_SMU_PPUNSPATD2_MASK) -#else - SMU->PPUPATD0 = init->ppu.reg[0]; - SMU->PPUPATD1 = init->ppu.reg[1]; -#if defined(_SMU_PPUNSPATD2_MASK) - SMU->PPUPATD2 = init->ppu.reg[2]; -#endif //defined(_SMU_PPUNSPATD2_MASK) -#endif //SL_TRUSTZONE_SECURE - - SMU_EnablePPU(init->enable); -} -/***************************************************************************//** - * @brief - * Change access settings for a peripheral. - * - * @details - * Set to limit access of a peripheral from privileged mode. - * - * @param[in] peripheral - * ID of the peripheral to change access settings for. - * - * @param[in] privileged - * Set to true if the peripheral should only be accessed from privileged - * mode; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, - bool privileged) -{ - EFM_ASSERT(peripheral < smuPeripheralEnd); - -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - if (peripheral < 32) { - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged); - } else if (peripheral < 64) { - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged); - } else { -#if defined(_SMU_PPUNSPATD2_MASK) - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); -#else - EFM_ASSERT(false); -#endif //defined(_SMU_PPUNSPATD2_MASK) - } -#else - if (peripheral < 32) { - BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); - } else if (peripheral < 64) { - BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); - } else { -#if defined(_SMU_PPUNSPATD2_MASK) - BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); -#else - EFM_ASSERT(false); -#endif //defined(_SMU_PPUNSPATD2_MASK) - } -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Get the ID of the peripheral that caused an access fault. - * - * @note - * The return value is only valid if SMU_IF_PPUPRIV interrupt flag - * is set. - * - * @return - * ID of the peripheral that caused an access fault. - ******************************************************************************/ -__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS; -#else - return (SMU_Peripheral_TypeDef)SMU->PPUFS; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Clear one or more pending SMU interrupts. - * - * @param[in] flags - * Bitwise logic OR of SMU interrupt sources to clear. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntClear(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIF_CLR = flags; -#else - SMU->IF_CLR = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IFC = flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Disable one or more SMU interrupts. - * - * @param[in] flags - * SMU interrupt sources to disable. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntDisable(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIEN_CLR = flags; -#else - SMU->IEN_CLR = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IEN &= ~flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Enable one or more SMU interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * SMU_IntClear() prior to enabling the interrupt. - * - * @param[in] flags - * SMU interrupt sources to enable. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntEnable(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIEN_SET = flags; -#else - SMU->IEN_SET = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IEN |= flags; -#endif //SMU_HAS_SET_CLEAR -} - -/***************************************************************************//** - * @brief - * Get pending SMU interrupts. - * - * @return - * SMU interrupt sources pending. - ******************************************************************************/ -__STATIC_INLINE uint32_t SMU_IntGet(void) -{ -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - return SMU_NS_CFGNS->NSIF; -#else - return SMU->IF; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Get enabled and pending SMU interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @note - * Interrupt flags are not cleared by this function. - * - * @return - * Pending and enabled SMU interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in SMU_IEN register - * and - * - the OR combination of valid interrupt flags in SMU_IF register. - ******************************************************************************/ -__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) -{ - uint32_t tmp; - -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - // Store SMU->IEN in temporary variable to define explicit order - // of volatile accesses. - tmp = SMU_NS_CFGNS->NSIEN; - - // Bitwise AND of pending and enabled interrupts. - return SMU_NS_CFGNS->NSIF & tmp; -#else - // Store SMU->IEN in temporary variable to define explicit order - // of volatile accesses. - tmp = SMU->IEN; - - // Bitwise AND of pending and enabled interrupts. - return SMU->IF & tmp; -#endif //SL_TRUSTZONE_SECURE -} - -/***************************************************************************//** - * @brief - * Set one or more pending SMU interrupts from SW. - * - * @param[in] flags - * SMU interrupt sources to set to pending. - ******************************************************************************/ -__STATIC_INLINE void SMU_IntSet(uint32_t flags) -{ -#if defined (SMU_HAS_SET_CLEAR) -#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - SMU_NS_CFGNS->NSIF_SET = flags; -#else - SMU->IF_SET = flags; -#endif //SL_TRUSTZONE_SECURE -#else - SMU->IFS = flags; -#endif //SMU_HAS_SET_CLEAR -} - -/**************************************************************************//** -* @brief -* SMU secure IRQ Handler. -* -* @details -* When a PPU detects an access to a secure peripheral at its non-secure -* address or an access to a non-secure peripheral at its secure -* address, PPUSECIF in SMU_IF is set and the ID of the peripheral being -* accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's -* Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler -* Will handle the interrupt. -******************************************************************************/ -#if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2) -void SMU_SECURE_IRQHandler(void) -{ - if (SMU_IF_PPUSEC) { - EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC); - } - - if (SMU_IF_BMPUSEC) { - EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC); - } - - // PPUFS contains the ID of the peripheral caused the fault - // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields. - EFM_ASSERT(SMU->PPUFS); - - while (1) { - // do nothing - } -} -#endif //SL_TRUSTZONE_SECURE - -/** @} (end addtogroup smu) */ - -#ifdef __cplusplus -} -#endif - -#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) -#endif // EM_SMU_H +/***************************************************************************//** + * @file + * @brief Security Management Unit (SMU) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SMU_H +#define EM_SMU_H + +#include "em_device.h" +#if defined(SMU_COUNT) && (SMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_bus.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup smu SMU - Security Management Unit + * @brief Security Management Unit (SMU) Peripheral API + * + * @details + * SMU forms the control and status/reporting component of bus-level + * security in EFM32/EFR32 devices. + * + * Peripheral-level protection is provided via the Peripheral Protection Unit + * (PPU). PPU provides hardware access barrier to any peripheral that is + * configured to be protected. When an attempt is made to access a peripheral + * without the required privilege/security level, PPU detects the fault + * and intercepts the access. No write or read of the peripheral register + * space occurs, and an all-zero value is returned if the access is a read. + * + * Usage example + * @include em_smu_init.c + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** SMU peripheral identifiers. */ +typedef enum { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */ +#if defined(_SMU_PPUPATD0_CSEN_SHIFT) + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ +#endif +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#if defined(_SMU_PPUPATD0_ACMP0_SHIFT) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ +#endif +#if defined(_SMU_PPUPATD0_ACMP1_SHIFT) + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ +#endif +#if defined(_SMU_PPUPATD0_ADC0_SHIFT) + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ +#endif + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ +#if defined(_SMU_PPUPATD0_VDAC0_SHIFT) + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ +#endif + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ +#if defined(_SMU_PPUPATD0_IDAC0_SHIFT) + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ +#endif + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ +#if defined(_SMU_PPUPATD0_LESENSE_SHIFT) + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ +#endif + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ +#if defined(_SMU_PPUPATD0_PCNT0_SHIFT) + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ +#endif + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */ + smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */ + smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ + smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */ + smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ +#if defined(_SMU_PPUPATD0_ETH_SHIFT) + smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */ +#endif + smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */ + smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */ + smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */ +#if defined(_SMU_PPUPATD1_QSPI0_SHIFT) + smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */ +#endif + smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */ + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ +#if defined(_SMU_PPUPATD1_SDIO_SHIFT) + smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */ + smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */ + smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */ + smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */ + smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */ +#if defined(_SMU_PPUPATD1_USB_SHIFT) + smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */ + smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */ + smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */ + smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */ + smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */ + smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */ + smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */ + smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */ + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */ + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */ + smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */ + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */ +#if defined(_SMU_PPUPATD0_LCD_SHIFT) + smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */ +#endif + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */ + smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */ + smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */ + smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */ + smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */ + smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */ + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */ + smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */ + smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */ + smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */ + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */ + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */ + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */ + smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */ + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */ + smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */ + smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(SMU_PPUPATD0_SCRATCHPAD) + smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */ +#endif + smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */ + smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */ +#if defined(_SMU_PPUPATD0_HFXO0_SHIFT) + smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif + smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */ + smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */ + smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */ + smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */ + smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */ + smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */ + smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */ + smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */ + smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */ + smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */ + smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */ + smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */ + smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */ + smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */ + smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */ + smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */ +#if defined(_SMU_PPUPATD0_TIMER4_SHIFT) + smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER5_SHIFT) + smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER6_SHIFT) + smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */ +#endif +#if defined(_SMU_PPUPATD0_TIMER7_SHIFT) + smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */ +#endif +#if defined(_SMU_PPUPATD0_USART0_SHIFT) + smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */ +#endif +#if defined(_SMU_PPUPATD0_USART1_SHIFT) + smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */ +#endif +#if defined(_SMU_PPUPATD0_USART2_SHIFT) + smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */ +#endif + smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */ +#if defined(_SMU_PPUPATD0_I2C1_SHIFT) + smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */ +#endif +#if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT) + smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */ +#endif +#if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT) + smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */ +#endif + +#if defined(SMU_PPUPATD0_LVGD) + smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */ +#endif + smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */ +#if defined(_SMU_PPUPATD0_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD1_BURAM_SHIFT) + smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */ +#endif +#if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT) + smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/ +#endif +#if defined(_SMU_PPUPATD0_GPCRC_SHIFT) + smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD1_GPCRC_SHIFT) + smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */ +#endif +#if defined(_SMU_PPUPATD0_DCDC_SHIFT) + smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD0_RTCC_SHIFT) + smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT) + smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_EUSART0_SHIFT) + smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART1_SHIFT) + smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART1_SHIFT) + smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */ +#endif +#if defined(_SMU_PPUPATD0_EUSART2_SHIFT) + smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART2_SHIFT) + smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART3_SHIFT) + smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */ +#endif +#if defined(_SMU_PPUPATD1_EUSART4_SHIFT) + smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */ +#endif +#if defined(_SMU_PPUPATD1_RTCC_SHIFT) + smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */ +#endif +#if defined(_SMU_PPUPATD1_SYSRTC_SHIFT) + smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */ +#endif +#if defined(_SMU_PPUPATD1_LCD_SHIFT) + smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */ +#endif +#if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT) + smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */ +#endif +#if defined(_SMU_PPUPATD1_DMEM_SHIFT) + smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */ +#endif +#if defined(_SMU_PPUPATD1_LCDRF_SHIFT) + smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */ +#endif +#if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT) + smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */ +#endif +#if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT) + smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */ +#endif +#if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT) + smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */ +#endif +#if defined(_SMU_PPUPATD1_VDAC0_SHIFT) + smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */ +#endif +#if defined(_SMU_PPUPATD1_VDAC1_SHIFT) + smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */ +#endif +#if defined(_SMU_PPUPATD1_PCNT_SHIFT) + smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */ +#endif +#if defined(_SMU_PPUPATD1_LESENSE_SHIFT) + smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */ +#endif +#if defined(_SMU_PPUPATD1_HFRCO1_SHIFT) + smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */ +#endif +#if defined(_SMU_PPUPATD1_HFXO0_SHIFT) + smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */ +#endif +#if defined(_SMU_PPUPATD1_DCDC_SHIFT) + smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */ +#endif +#if defined(_SMU_PPUPATD1_PDM_SHIFT) + smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */ +#endif +#if defined(_SMU_PPUPATD1_RFSENSE_SHIFT) + smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */ +#endif +#if defined(_SMU_PPUPATD1_SEPUF_SHIFT) + smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */ +#endif + smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */ +#if defined(_SMU_PPUPATD1_IADC0_SHIFT) + smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP0_SHIFT) + smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */ +#endif +#if defined(_SMU_PPUPATD1_ACMP1_SHIFT) + smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */ +#endif +#if defined(_SMU_PPUPATD1_I2C0_SHIFT) + smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */ +#endif +#if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT) + smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */ +#endif + smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */ +#if defined(_SMU_PPUPATD1_WDOG1_SHIFT) + smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */ +#endif + smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */ +#if defined(_SMU_PPUPATD1_RADIOAES_SHIFT) + smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */ +#endif +#if defined(_SMU_PPUPATD1_EUART0_SHIFT) + smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */ +#endif +#if defined(_SMU_PPUPATD1_BUFC_SHIFT) + smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */ +#endif + smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */ +#if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT) + smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */ +#endif +#if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT) + smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */ +#endif +#if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT) + smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */ +#endif +#if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT) + smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */ +#endif +#if defined(_SMU_PPUPATD1_MVP_SHIFT) + smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */ +#endif +#if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT) + smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */ +#endif +#else +#error "No peripherals defined for SMU for this device configuration." +#endif + smuPeripheralEnd /**< SMU peripheral end. */ +} SMU_Peripheral_TypeDef; + +/** SMU peripheral privileged access enablers. */ +typedef struct { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + + bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedETH : 1; /**< Privileged access enabler for ETH. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */ + bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */ + bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */ + bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */ + bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */ + bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */ + bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */ + bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */ + bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */ + bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */ + bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */ + bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */ + bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */ + bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */ + bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */ + bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */ + bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */ + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */ + bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */ + bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */ + bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */ + bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */ + bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */ + bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */ + bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */ + bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */ + bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */ + bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */ + bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */ + bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */ + bool privilegedUSB : 1; /**< Privileged access enabler for USB. */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */ + bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */ + bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + + bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */ + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */ + bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */ + bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */ + bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */ + bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */ + bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */ + bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */ + bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */ + bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCI : 1; /**< Privileged access enabler for DCI */ + + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedPDM : 1; /**< Privileged access enabler for PDM */ + bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */ + bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */ + bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */ + bool privilegedEMU : 1; /**< Privileged access enabler for EMU */ + bool privilegedCMU : 1; /**< Privileged access enabler for CMU */ + bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */ + bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */ + bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */ + bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */ + bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */ + bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */ + bool privilegedMSC : 1; /**< Privileged access enabler for MSC */ + bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */ + bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */ + bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */ + bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */ + bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */ + bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */ + bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */ + bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */ + bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */ + bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */ + bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */ + bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */ + bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */ + bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */ + bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */ + bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */ + bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */ + bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */ + bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */ + bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */ + bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */ + bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */ + + bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */ + bool privilegedLCD : 1; /**< Privileged access enabler for LCD */ + bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */ + bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */ + bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */ + bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */ + bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */ + bool privilegedSMU : 1; /**< Privileged access enabler for SMU */ + bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */ + bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */ + bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */ + bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */ + bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */ + bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */ + bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */ + bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */ + bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */ + bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */ + bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */ + bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */ + bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */ + bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */ + bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */ + bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */ + bool privilegedMVP : 1; /**< Privileged access enabler for MVP */ + bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */ + +#else +#error "No peripherals defined for SMU for this device configuration" +#endif +} SMU_PrivilegedAccess_TypeDef; + +/******************************************************************************* + ****************************** STRUCTS ************************************ + ******************************************************************************/ + +/** SMU initialization structure. */ +typedef struct { + union { +#if defined(_SMU_PPUNSPATD2_MASK) + uint32_t reg[3]; /**< Peripheral access control array.*/ +#else + uint32_t reg[2]; /**< Peripheral access control array.*/ +#endif + SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/ + } ppu; /**< PPU init array.*/ + bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/ +} SMU_Init_TypeDef; + +/** Default SMU initialization structure settings. */ +#define SMU_INIT_DEFAULT { \ + { { 0 } }, /* No peripherals access protected. */ \ + true /* Enable SMU.*/ \ +} + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable or disable PPU of SMU. + * + * @param[in] enable + * Set to true to enable PPU; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_EnablePPU(bool enable) +{ +#if defined (_SMU_PPUCTRL_ENABLE_SHIFT) + BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable); +#else + (void)enable; +#endif +} + +/***************************************************************************//** + * @brief + * Initialize PPU of SMU. + * + * @param[in] init + * Pointer to initialization structure that defines which peripherals should + * only be accessed from privileged mode, and if PPU should be enabled. + ******************************************************************************/ +__STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0]; + SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#else + SMU->PPUPATD0 = init->ppu.reg[0]; + SMU->PPUPATD1 = init->ppu.reg[1]; +#if defined(_SMU_PPUNSPATD2_MASK) + SMU->PPUPATD2 = init->ppu.reg[2]; +#endif //defined(_SMU_PPUNSPATD2_MASK) +#endif //SL_TRUSTZONE_SECURE + + SMU_EnablePPU(init->enable); +} +/***************************************************************************//** + * @brief + * Change access settings for a peripheral. + * + * @details + * Set to limit access of a peripheral from privileged mode. + * + * @param[in] peripheral + * ID of the peripheral to change access settings for. + * + * @param[in] privileged + * Set to true if the peripheral should only be accessed from privileged + * mode; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral, + bool privileged) +{ + EFM_ASSERT(peripheral < smuPeripheralEnd); + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + if (peripheral < 32) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#else + if (peripheral < 32) { + BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged); + } else if (peripheral < 64) { + BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged); + } else { +#if defined(_SMU_PPUNSPATD2_MASK) + BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged); +#else + EFM_ASSERT(false); +#endif //defined(_SMU_PPUNSPATD2_MASK) + } +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get the ID of the peripheral that caused an access fault. + * + * @note + * The return value is only valid if SMU_IF_PPUPRIV interrupt flag + * is set. + * + * @return + * ID of the peripheral that caused an access fault. + ******************************************************************************/ +__STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS; +#else + return (SMU_Peripheral_TypeDef)SMU->PPUFS; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Clear one or more pending SMU interrupts. + * + * @param[in] flags + * Bitwise logic OR of SMU interrupt sources to clear. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntClear(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_CLR = flags; +#else + SMU->IF_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFC = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Disable one or more SMU interrupts. + * + * @param[in] flags + * SMU interrupt sources to disable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntDisable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_CLR = flags; +#else + SMU->IEN_CLR = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN &= ~flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Enable one or more SMU interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * SMU_IntClear() prior to enabling the interrupt. + * + * @param[in] flags + * SMU interrupt sources to enable. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntEnable(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIEN_SET = flags; +#else + SMU->IEN_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IEN |= flags; +#endif //SMU_HAS_SET_CLEAR +} + +/***************************************************************************//** + * @brief + * Get pending SMU interrupts. + * + * @return + * SMU interrupt sources pending. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGet(void) +{ +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + return SMU_NS_CFGNS->NSIF; +#else + return SMU->IF; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Get enabled and pending SMU interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled SMU interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in SMU_IEN register + * and + * - the OR combination of valid interrupt flags in SMU_IF register. + ******************************************************************************/ +__STATIC_INLINE uint32_t SMU_IntGetEnabled(void) +{ + uint32_t tmp; + +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU_NS_CFGNS->NSIEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU_NS_CFGNS->NSIF & tmp; +#else + // Store SMU->IEN in temporary variable to define explicit order + // of volatile accesses. + tmp = SMU->IEN; + + // Bitwise AND of pending and enabled interrupts. + return SMU->IF & tmp; +#endif //SL_TRUSTZONE_SECURE +} + +/***************************************************************************//** + * @brief + * Set one or more pending SMU interrupts from SW. + * + * @param[in] flags + * SMU interrupt sources to set to pending. + ******************************************************************************/ +__STATIC_INLINE void SMU_IntSet(uint32_t flags) +{ +#if defined (SMU_HAS_SET_CLEAR) +#if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + SMU_NS_CFGNS->NSIF_SET = flags; +#else + SMU->IF_SET = flags; +#endif //SL_TRUSTZONE_SECURE +#else + SMU->IFS = flags; +#endif //SMU_HAS_SET_CLEAR +} + +/**************************************************************************//** +* @brief +* SMU secure IRQ Handler. +* +* @details +* When a PPU detects an access to a secure peripheral at its non-secure +* address or an access to a non-secure peripheral at its secure +* address, PPUSECIF in SMU_IF is set and the ID of the peripheral being +* accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's +* Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler +* Will handle the interrupt. +******************************************************************************/ +#if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2) +void SMU_SECURE_IRQHandler(void) +{ + if (SMU_IF_PPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC); + } + + if (SMU_IF_BMPUSEC) { + EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC); + } + + // PPUFS contains the ID of the peripheral caused the fault + // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields. + EFM_ASSERT(SMU->PPUFS); + + while (1) { + // do nothing + } +} +#endif //SL_TRUSTZONE_SECURE + +/** @} (end addtogroup smu) */ + +#ifdef __cplusplus +} +#endif + +#endif // defined(SMU_COUNT) && (SMU_COUNT > 0) +#endif // EM_SMU_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h index fb10b4a..17a4d58 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_syscfg.h @@ -1,171 +1,171 @@ -/***************************************************************************//** - * @file - * @brief API defining acces to SYSCFG registers - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SYSCFG_H -#define EM_SYSCFG_H - -#include "em_device.h" - -#if defined(SL_TRUSTZONE_NONSECURE) -#include "sli_tz_service_syscfg.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(SYSCFG) -/******************************************************************************* - ******************************** TZ SERVICES ********************************** - ******************************************************************************/ - -#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) -/******************************************************************************* - * @brief Reads CHIPREV register - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_readChipRev(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_read_chiprev_register(); -#else - return SYSCFG->CHIPREV; -#endif -} -#endif // defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - -#if defined(_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) -/******************************************************************************* - * @brief Sets DMEM0RAMCTRL RAMWSEN bit to 1 - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); -#else - - SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL | _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; -#endif -} - -/******************************************************************************* - * @brief Clears DMEM0RAMCTRL RAMWSEN bit to 0 - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); -#else - SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; -#endif -} - -/******************************************************************************* - * @brief Reads DMEM0RAMCTRL RAMWSEN bit - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); -#else - return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; -#endif -} - -#endif //_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK -#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) - -/******************************************************************************* - * @brief Reads DMEM0RETNCTRL register - ******************************************************************************/ -__STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - return sli_tz_syscfg_read_dmem0retnctrl_register(); -#else - return SYSCFG->DMEM0RETNCTRL; -#endif -} -/******************************************************************************* - * @brief Mask DMEM0RETNCTRL register with provided mask - * - * @param mask - A mask that is to be used to mask the DMEM0RETNCTRL register - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_mask_dmem0retnctrl_register(mask); -#else - SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; -#endif -} - -/******************************************************************************* - * @brief Set DMEM0RETNCTRL to zero - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_zero_dmem0retnctrl_register(); -#else - SYSCFG->DMEM0RETNCTRL = 0x0UL; -#endif -} -#endif // _SYSCFG_DMEM0RETNCTRL_MASK - -#if defined(_SYSCFG_CFGSYSTIC_MASK) -/******************************************************************************* - * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_set_systicextclken_cfgsystic(); -#else - SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); -#endif -} - -/******************************************************************************* - * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero - ******************************************************************************/ -__STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) -{ -#if defined(SL_TRUSTZONE_NONSECURE) - sli_tz_syscfg_clear_systicextclken_cfgsystic(); -#else - SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); -#endif -} -#endif //_SYSCFG_CFGSYSTIC_MASK -#endif //SYSCFG -#ifdef __cplusplus -} -#endif -#endif // EM_SYSCFG_H +/***************************************************************************//** + * @file + * @brief API defining acces to SYSCFG registers + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSCFG_H +#define EM_SYSCFG_H + +#include "em_device.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +#include "sli_tz_service_syscfg.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SYSCFG) +/******************************************************************************* + ******************************** TZ SERVICES ********************************** + ******************************************************************************/ + +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) +/******************************************************************************* + * @brief Reads CHIPREV register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readChipRev(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_chiprev_register(); +#else + return SYSCFG->CHIPREV; +#endif +} +#endif // defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + +#if defined(_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) +/******************************************************************************* + * @brief Sets DMEM0RAMCTRL RAMWSEN bit to 1 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_dmem0ramctrl_ramwsen_bit(); +#else + + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL | _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Clears DMEM0RAMCTRL RAMWSEN bit to 0 + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_dmem0ramctrl_ramwsen_bit(); +#else + SYSCFG->DMEM0RAMCTRL = SYSCFG->DMEM0RAMCTRL & ~_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK; +#endif +} + +/******************************************************************************* + * @brief Reads DMEM0RAMCTRL RAMWSEN bit + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_getDmem0RamCtrlRamwsenBit(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_get_dmem0ramctrl_ramwsen_bit(); +#else + return (SYSCFG->DMEM0RAMCTRL & _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK) >> _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT; +#endif +} + +#endif //_SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) + +/******************************************************************************* + * @brief Reads DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE uint32_t SYSCFG_readDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + return sli_tz_syscfg_read_dmem0retnctrl_register(); +#else + return SYSCFG->DMEM0RETNCTRL; +#endif +} +/******************************************************************************* + * @brief Mask DMEM0RETNCTRL register with provided mask + * + * @param mask - A mask that is to be used to mask the DMEM0RETNCTRL register + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_maskDmem0RetnCtrl(uint32_t mask) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_mask_dmem0retnctrl_register(mask); +#else + SYSCFG->DMEM0RETNCTRL = SYSCFG->DMEM0RETNCTRL | mask; +#endif +} + +/******************************************************************************* + * @brief Set DMEM0RETNCTRL to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_zeroDmem0RetnCtrl(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_zero_dmem0retnctrl_register(); +#else + SYSCFG->DMEM0RETNCTRL = 0x0UL; +#endif +} +#endif // _SYSCFG_DMEM0RETNCTRL_MASK + +#if defined(_SYSCFG_CFGSYSTIC_MASK) +/******************************************************************************* + * @brief Set SYSTICEXTCLKEN bit in CFGSYSTIC to one + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_setSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_set_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC | _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} + +/******************************************************************************* + * @brief Clear SYSTICEXTCLKEN bit in CFGSYSTIC to zero + ******************************************************************************/ +__STATIC_INLINE void SYSCFG_clearSysTicExtClkEnCfgSysTic(void) +{ +#if defined(SL_TRUSTZONE_NONSECURE) + sli_tz_syscfg_clear_systicextclken_cfgsystic(); +#else + SYSCFG->CFGSYSTIC = (SYSCFG->CFGSYSTIC & ~_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK); +#endif +} +#endif //_SYSCFG_CFGSYSTIC_MASK +#endif //SYSCFG +#ifdef __cplusplus +} +#endif +#endif // EM_SYSCFG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h index 88d9f73..6bae748 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system.h @@ -1,361 +1,361 @@ -/***************************************************************************//** - * @file - * @brief System API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_SYSTEM_H -#define EM_SYSTEM_H - -#include "em_device.h" -#include "em_system_generic.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup system SYSTEM - System Utils - * @brief System API - * @details - * This module contains functions to read information such as RAM and Flash size, - * device unique ID, chip revision, family, and part number from DEVINFO and - * SCB blocks. Functions to configure and read status from FPU are available for - * compatible devices. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Family identifiers. */ -typedef enum { -/* New style family #defines */ -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) - systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) - systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) - systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) - systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) - systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) - systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) - systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) - systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) - systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) - systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) - systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) - systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) - systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) - systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) - systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) - systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) - systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) - systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) - systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) - systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) - systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) - systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) - systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) - systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) - systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) - systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) - systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) - systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) - systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) - systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) - systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) - systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) - systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) - systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) - systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) - systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) - systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) - systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) - systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) - systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) - systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) - systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) - systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) - systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) - systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L) - systemPartFamilyZen13L = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L, /**< EFR32 Zen Gecko Series 1 Configuration 3 Led Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S) - systemPartFamilyZen13S = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S, /**< EFR32 Zen Gecko Series 1 Configuration 3 Sensor Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) - systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) - systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) - systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) - systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) - systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) - systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) - systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ - systemPartFamilyMightyRcp21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty RCP Series 2 Config 1 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - systemPartFamilyMighty22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyFlex22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyBlue22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 2 Value Device Family */ - systemPartFamilyEfm32Pearl22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - systemPartFamilyFlex23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilyZen23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilyEfm32Pearl23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family */ - systemPartFamilySideWalk23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) - systemPartFamilyMighty24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family */ - systemPartFamilyFlex24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 4 Value Device Family */ - systemPartFamilyBlue24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 4 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - systemPartFamilyFlex25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 5 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - systemPartFamilyMighty26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family */ - systemPartFamilyBlue26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 6 Value Device Family */ - systemPartFamilyEfm32Pearl26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - systemPartFamilyMighty27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family */ - systemPartFamilyBlue27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 7 Value Device Family */ -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - systemPartFamilyFlex28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilyZen28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilySideWalk28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family */ - systemPartFamilyEfm32Pearl28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family */ -#endif -/* Deprecated family #defines */ -#if defined(_DEVINFO_PART_DEVICE_FAMILY_G) - systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) - systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) - systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) - systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) - systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) - systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ -#endif -#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) - systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ -#endif - systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. - Family ID is missing - on unprogrammed parts. */ -} SYSTEM_PartFamily_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Chip revision details. */ -typedef struct { - uint8_t minor; /**< Minor revision number. */ - uint8_t major; /**< Major revision number. */ -#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - uint16_t partNumber; /**< Device part number. */ -#else - uint8_t family; /**< Device family number. */ -#endif -} SYSTEM_ChipRevision_TypeDef; - -#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) -/** Floating point co-processor access modes. */ -typedef enum { - fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ - fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ - fpuAccessReserved = (0xA << 20), /**< Reserved. */ - fpuAccessFull = (0xF << 20) /**< Full access. */ -} SYSTEM_FpuAccess_TypeDef; -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); -SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void); - -#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) -/***************************************************************************//** - * @brief - * Get DEVINFO revision. - * - * @return - * Revision of the DEVINFO contents. - ******************************************************************************/ -__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) -{ -#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) - return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) - >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); -#elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) - return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) - >> _DEVINFO_INFO_DEVINFOREV_SHIFT); -#endif -} -#endif - -#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) -/***************************************************************************//** - * @brief - * Set floating point co-processor (FPU) access mode. - * - * @param[in] accessMode - * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef - * for details. - ******************************************************************************/ -__STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) -{ - SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; -} -#endif - -/** @} (end addtogroup system) */ - -#ifdef __cplusplus -} -#endif -#endif /* EM_SYSTEM_H */ +/***************************************************************************//** + * @file + * @brief System API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_SYSTEM_H +#define EM_SYSTEM_H + +#include "em_device.h" +#include "em_system_generic.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system SYSTEM - System Utils + * @brief System API + * @details + * This module contains functions to read information such as RAM and Flash size, + * device unique ID, chip revision, family, and part number from DEVINFO and + * SCB blocks. Functions to configure and read status from FPU are available for + * compatible devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family identifiers. */ +typedef enum { +/* New style family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32G) + systemPartFamilyEfm32Gecko = _DEVINFO_PART_DEVICE_FAMILY_EFM32G, /**< EFM32 Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG) + systemPartFamilyEfm32Giant = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG, /**< EFM32 Giant Gecko Series 0 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B) + systemPartFamilyEfm32Giant11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG11B, /**< EFM32 Giant Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B) + systemPartFamilyEfm32Giant12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32GG12B, /**< EFM32 Giant Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG) + systemPartFamilyEfm32Tiny = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG, /**< EFM32 Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B) + systemPartFamilyEfm32Tiny11B = _DEVINFO_PART_DEVICE_FAMILY_EFM32TG11B, /**< EFM32 Tiny Gecko 11 Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32LG) + systemPartFamilyEfm32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EFM32LG, /**< EFM32 Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32WG) + systemPartFamilyEfm32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EFM32WG, /**< EFM32 Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG) + systemPartFamilyEfm32Zero = _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG, /**< EFM32 Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32HG) + systemPartFamilyEfm32Happy = _DEVINFO_PART_DEVICE_FAMILY_EFM32HG, /**< EFM32 Happy Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B) + systemPartFamilyEfm32Pearl1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B, /**< EFM32 Pearl Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B) + systemPartFamilyEfm32Jade1B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B, /**< EFM32 Jade Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B) + systemPartFamilyEfm32Pearl12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B, /**< EFM32 Pearl Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B) + systemPartFamilyEfm32Jade12B = _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B, /**< EFM32 Jade Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32WG) + systemPartFamilyEzr32Wonder = _DEVINFO_PART_DEVICE_FAMILY_EZR32WG, /**< EZR32 Wonder Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32LG) + systemPartFamilyEzr32Leopard = _DEVINFO_PART_DEVICE_FAMILY_EZR32LG, /**< EZR32 Leopard Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EZR32HG) + systemPartFamilyEzr32Happy = _DEVINFO_PART_DEVICE_FAMILY_EZR32HG, /**< EZR32 Happy Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P) + systemPartFamilyMighty1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B) + systemPartFamilyMighty1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V) + systemPartFamilyMighty1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V, /**< EFR32 Mighty Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P) + systemPartFamilyBlue1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P, /**< EFR32 Blue Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B) + systemPartFamilyBlue1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B, /**< EFR32 Blue Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V) + systemPartFamilyBlue1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V, /**< EFR32 Blue Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P) + systemPartFamilyFlex1P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P, /**< EFR32 Flex Gecko Series 1 Configuration 1 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B) + systemPartFamilyFlex1B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B, /**< EFR32 Flex Gecko Series 1 Configuration 1 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V) + systemPartFamilyFlex1V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V, /**< EFR32 Flex Gecko Series 1 Configuration 1 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P) + systemPartFamilyMighty12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B) + systemPartFamilyMighty12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V) + systemPartFamilyMighty12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V, /**< EFR32 Mighty Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P) + systemPartFamilyBlue12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P, /**< EFR32 Blue Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B) + systemPartFamilyBlue12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B, /**< EFR32 Blue Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V) + systemPartFamilyBlue12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V, /**< EFR32 Blue Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P) + systemPartFamilyFlex12P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P, /**< EFR32 Flex Gecko Series 1 Configuration 2 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B) + systemPartFamilyFlex12B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B, /**< EFR32 Flex Gecko Series 1 Configuration 2 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V) + systemPartFamilyFlex12V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V, /**< EFR32 Flex Gecko Series 1 Configuration 2 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P) + systemPartFamilyMighty13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B) + systemPartFamilyMighty13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V) + systemPartFamilyMighty13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V, /**< EFR32 Mighty Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P) + systemPartFamilyBlue13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P, /**< EFR32 Blue Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B) + systemPartFamilyBlue13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B, /**< EFR32 Blue Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V) + systemPartFamilyBlue13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V, /**< EFR32 Blue Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P) + systemPartFamilyFlex13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P, /**< EFR32 Flex Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B) + systemPartFamilyFlex13B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B, /**< EFR32 Flex Gecko Series 1 Configuration 3 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V) + systemPartFamilyFlex13V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V, /**< EFR32 Flex Gecko Series 1 Configuration 3 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P) + systemPartFamilyZen13P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13P, /**< EFR32 Zen Gecko Series 1 Configuration 3 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L) + systemPartFamilyZen13L = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13L, /**< EFR32 Zen Gecko Series 1 Configuration 3 Led Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S) + systemPartFamilyZen13S = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG13S, /**< EFR32 Zen Gecko Series 1 Configuration 3 Sensor Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P) + systemPartFamilyMighty14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14P, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B) + systemPartFamilyMighty14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14B, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V) + systemPartFamilyMighty14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32MG14V, /**< EFR32 Mighty Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P) + systemPartFamilyFlex14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14P, /**< EFR32 Flex Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B) + systemPartFamilyFlex14B = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14B, /**< EFR32 Flex Gecko Series 1 Configuration 4 Basic Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V) + systemPartFamilyFlex14V = _DEVINFO_PART_DEVICE_FAMILY_EFR32FG14V, /**< EFR32 Flex Gecko Series 1 Configuration 4 Value Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P) + systemPartFamilyZen14P = _DEVINFO_PART_DEVICE_FAMILY_EFR32ZG14P, /**< EFR32 Zen Gecko Series 1 Configuration 4 Premium Device Family. */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + systemPartFamilyMighty21 = DEVINFO_PART_FAMILY_MG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyFlex21 = DEVINFO_PART_FAMILY_FG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyBlue21 = DEVINFO_PART_FAMILY_BG | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 1 Value Device Family */ + systemPartFamilyMightyRcp21 = DEVINFO_PART_FAMILY_MR | (21 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty RCP Series 2 Config 1 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + systemPartFamilyMighty22 = DEVINFO_PART_FAMILY_MG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyFlex22 = DEVINFO_PART_FAMILY_FG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyBlue22 = DEVINFO_PART_FAMILY_BG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 2 Value Device Family */ + systemPartFamilyEfm32Pearl22 = DEVINFO_PART_FAMILY_PG | (22 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 2 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + systemPartFamilyFlex23 = DEVINFO_PART_FAMILY_FG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyZen23 = DEVINFO_PART_FAMILY_ZG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilyEfm32Pearl23 = DEVINFO_PART_FAMILY_PG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 3 Value Device Family */ + systemPartFamilySideWalk23 = DEVINFO_PART_FAMILY_SG | (23 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 3 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) + systemPartFamilyMighty24 = DEVINFO_PART_FAMILY_MG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyFlex24 = DEVINFO_PART_FAMILY_FG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 4 Value Device Family */ + systemPartFamilyBlue24 = DEVINFO_PART_FAMILY_BG | (24 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 4 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + systemPartFamilyFlex25 = DEVINFO_PART_FAMILY_FG | (25 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 5 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + systemPartFamilyMighty26 = DEVINFO_PART_FAMILY_MG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyBlue26 = DEVINFO_PART_FAMILY_BG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 6 Value Device Family */ + systemPartFamilyEfm32Pearl26 = DEVINFO_PART_FAMILY_PG | (26 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 6 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + systemPartFamilyMighty27 = DEVINFO_PART_FAMILY_MG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Mighty Gecko Series 2 Config 7 Value Device Family */ + systemPartFamilyBlue27 = DEVINFO_PART_FAMILY_BG | (27 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Blue Gecko Series 2 Config 7 Value Device Family */ +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + systemPartFamilyFlex28 = DEVINFO_PART_FAMILY_FG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Flex Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyZen28 = DEVINFO_PART_FAMILY_ZG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Zen Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilySideWalk28 = DEVINFO_PART_FAMILY_SG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFR32 Side Walk Gecko Series 2 Config 8 Value Device Family */ + systemPartFamilyEfm32Pearl28 = DEVINFO_PART_FAMILY_PG | (28 << _DEVINFO_PART_FAMILYNUM_SHIFT), /**< EFM32 Pearl Gecko Series 2 Config 8 Value Device Family */ +#endif +/* Deprecated family #defines */ +#if defined(_DEVINFO_PART_DEVICE_FAMILY_G) + systemPartFamilyGecko = _DEVINFO_PART_DEVICE_FAMILY_G, /**< Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_GG) + systemPartFamilyGiant = _DEVINFO_PART_DEVICE_FAMILY_GG, /**< Giant Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_TG) + systemPartFamilyTiny = _DEVINFO_PART_DEVICE_FAMILY_TG, /**< Tiny Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_LG) + systemPartFamilyLeopard = _DEVINFO_PART_DEVICE_FAMILY_LG, /**< Leopard Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_WG) + systemPartFamilyWonder = _DEVINFO_PART_DEVICE_FAMILY_WG, /**< Wonder Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_ZG) + systemPartFamilyZero = _DEVINFO_PART_DEVICE_FAMILY_ZG, /**< Zero Gecko Device Family. */ +#endif +#if defined(_DEVINFO_PART_DEVICE_FAMILY_HG) + systemPartFamilyHappy = _DEVINFO_PART_DEVICE_FAMILY_HG, /**< Happy Gecko Device Family. */ +#endif + systemPartFamilyUnknown = 0xFF /**< Unknown Device Family. + Family ID is missing + on unprogrammed parts. */ +} SYSTEM_PartFamily_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Chip revision details. */ +typedef struct { + uint8_t minor; /**< Minor revision number. */ + uint8_t major; /**< Major revision number. */ +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + uint16_t partNumber; /**< Device part number. */ +#else + uint8_t family; /**< Device family number. */ +#endif +} SYSTEM_ChipRevision_TypeDef; + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/** Floating point co-processor access modes. */ +typedef enum { + fpuAccessDenied = (0x0 << 20), /**< Access denied, any attempted access generates a NOCP UsageFault. */ + fpuAccessPrivilegedOnly = (0x5 << 20), /**< Privileged access only, an unprivileged access generates a NOCP UsageFault. */ + fpuAccessReserved = (0xA << 20), /**< Reserved. */ + fpuAccessFull = (0xF << 20) /**< Full access. */ +} SYSTEM_FpuAccess_TypeDef; +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev); +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void); + +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) || defined(_DEVINFO_INFO_DEVINFOREV_MASK) +/***************************************************************************//** + * @brief + * Get DEVINFO revision. + * + * @return + * Revision of the DEVINFO contents. + ******************************************************************************/ +__STATIC_INLINE uint8_t SYSTEM_GetDevinfoRev(void) +{ +#if defined(_DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->DEVINFOREV & _DEVINFO_DEVINFOREV_DEVINFOREV_MASK) + >> _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT); +#elif defined(_DEVINFO_INFO_DEVINFOREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_DEVINFOREV_MASK) + >> _DEVINFO_INFO_DEVINFOREV_SHIFT); +#endif +} +#endif + +#if defined(__FPU_PRESENT) && (__FPU_PRESENT == 1) +/***************************************************************************//** + * @brief + * Set floating point co-processor (FPU) access mode. + * + * @param[in] accessMode + * Floating point co-processor access mode. See @ref SYSTEM_FpuAccess_TypeDef + * for details. + ******************************************************************************/ +__STATIC_INLINE void SYSTEM_FpuAccessModeSet(SYSTEM_FpuAccess_TypeDef accessMode) +{ + SCB->CPACR = (SCB->CPACR & ~(0xFUL << 20)) | (uint32_t)accessMode; +} +#endif + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif +#endif /* EM_SYSTEM_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h index fffec7f..ed96b00 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_system_generic.h @@ -1,91 +1,91 @@ -/***************************************************************************//** - * @file - * @brief System API (Generic) - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef EM_SYSTEM_GENERIC_H -#define EM_SYSTEM_GENERIC_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Family security capability. */ -typedef enum { - securityCapabilityUnknown, /**< Unknown security capability. */ - securityCapabilityNA, /**< Security capability not applicable. */ - securityCapabilityBasic, /**< Basic security capability. */ - securityCapabilityRoT, /**< Root of Trust security capability. */ - securityCapabilitySE, /**< Secure Element security capability. */ - securityCapabilityVault /**< Secure Vault security capability. */ -} SYSTEM_SecurityCapability_TypeDef; - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** DEVINFO calibration address/value pair. */ -typedef struct { - uint32_t address; /**< Peripheral calibration register address. */ - uint32_t calValue; /**< Calibration value for register at address. */ -} -SYSTEM_CalAddrVal_TypeDef; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); -SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void); -uint64_t SYSTEM_GetUnique(void); -uint8_t SYSTEM_GetProdRev(void); -uint32_t SYSTEM_GetSRAMBaseAddress(void); -uint16_t SYSTEM_GetSRAMSize(void); -uint16_t SYSTEM_GetFlashSize(void); -uint32_t SYSTEM_GetFlashPageSize(void); -uint16_t SYSTEM_GetPartNumber(void); -uint8_t SYSTEM_GetCalibrationTemperature(void); - -/** @} (end addtogroup system) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_SYSTEM_GENERIC_H */ +/***************************************************************************//** + * @file + * @brief System API (Generic) + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef EM_SYSTEM_GENERIC_H +#define EM_SYSTEM_GENERIC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Family security capability. */ +typedef enum { + securityCapabilityUnknown, /**< Unknown security capability. */ + securityCapabilityNA, /**< Security capability not applicable. */ + securityCapabilityBasic, /**< Basic security capability. */ + securityCapabilityRoT, /**< Root of Trust security capability. */ + securityCapabilitySE, /**< Secure Element security capability. */ + securityCapabilityVault /**< Secure Vault security capability. */ +} SYSTEM_SecurityCapability_TypeDef; + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** DEVINFO calibration address/value pair. */ +typedef struct { + uint32_t address; /**< Peripheral calibration register address. */ + uint32_t calValue; /**< Calibration value for register at address. */ +} +SYSTEM_CalAddrVal_TypeDef; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress); +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void); +uint64_t SYSTEM_GetUnique(void); +uint8_t SYSTEM_GetProdRev(void); +uint32_t SYSTEM_GetSRAMBaseAddress(void); +uint16_t SYSTEM_GetSRAMSize(void); +uint16_t SYSTEM_GetFlashSize(void); +uint32_t SYSTEM_GetFlashPageSize(void); +uint16_t SYSTEM_GetPartNumber(void); +uint8_t SYSTEM_GetCalibrationTemperature(void); + +/** @} (end addtogroup system) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_SYSTEM_GENERIC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h index b0ae8e3..8ee671b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_timer.h @@ -1,1238 +1,1238 @@ -/***************************************************************************//** - * @file - * @brief Timer/counter (TIMER) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_TIMER_H -#define EM_TIMER_H - -#include "em_device.h" -#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) - -#include -#include "sl_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup timer - * @{ - ****************************************************************************** - * @deprecated - * Deprecated macro TIMER_CH_VALID for SDID 80, new code should use TIMER_REF_CH_VALID.*/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of TIMER register block pointer reference for assert statements. */ -#define TIMER_REF_VALID(ref) TIMER_Valid(ref) - -/** Validation of TIMER compare/capture channel number. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#define TIMER_CH_VALID(ch) ((ch) < 3) -#elif defined(_SILICON_LABS_32B_SERIES_1) -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define TIMER_CH_VALID(ch) _Pragma("GCC warning \"'TIMER_CH_VALID' macro is deprecated for EFR32xG1, Use TIMER_REF_CH_VALID instead\"") ((ch) < 4) -#else -#define TIMER_CH_VALID(ch) ((ch) < 4) -#endif -#else -#define TIMER_CH_VALID(ch) ((ch) < 3) -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define TIMER_REF_CH_VALID(ref, ch) ((ref == TIMER0) ? ((ch) < 3) : ((ch) < 4)) -#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_REF_CH_VALID(ref, ch) -#else -#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_CH_VALID(ch) -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Timer compare/capture mode. */ -typedef enum { -#if defined (_TIMER_CC_CTRL_MODE_MASK) - timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ - timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ - timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ - timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ -#endif -#if defined (_TIMER_CC_CFG_MODE_MASK) - timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ - timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ - timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ - timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ -#endif -} TIMER_CCMode_TypeDef; - -/** Clock select. */ -typedef enum { -#if defined (_TIMER_CTRL_CLKSEL_MASK) - timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ - timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ - timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ -#endif -#if defined (_TIMER_CFG_CLKSEL_MASK) - timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ - timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ - timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ -#endif -} TIMER_ClkSel_TypeDef; - -/** Input capture edge select. */ -typedef enum { - /** Rising edges detected. */ - timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, - - /** Falling edges detected. */ - timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, - - /** Both edges detected. */ - timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, - - /** No edge detection, leave signal as is. */ - timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE -} TIMER_Edge_TypeDef; - -/** Input capture event control. */ -typedef enum { - /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ - timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, - /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ - timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, - /** - * PRS output pulse, interrupt flag, and DMA request set on rising edge (if - * input capture edge = BOTH). - */ - timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, - /** - * PRS output pulse, interrupt flag, and DMA request set on falling edge (if - * input capture edge = BOTH). - */ - timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING -} TIMER_Event_TypeDef; - -/** Input edge action. */ -typedef enum { - /** No action taken. */ - timerInputActionNone = _TIMER_CTRL_FALLA_NONE, - - /** Start counter without reload. */ - timerInputActionStart = _TIMER_CTRL_FALLA_START, - - /** Stop counter without reload. */ - timerInputActionStop = _TIMER_CTRL_FALLA_STOP, - - /** Reload and start counter. */ - timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART -} TIMER_InputAction_TypeDef; - -/** Timer mode. */ -typedef enum { -#if defined (_TIMER_CTRL_MODE_MASK) - timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ - timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ - timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ - timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ -#endif -#if defined (_TIMER_CFG_MODE_MASK) - timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ - timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ - timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ - timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ -#endif -} TIMER_Mode_TypeDef; - -/** Compare/capture output action. */ -typedef enum { - /** No action. */ - timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, - - /** Toggle on event. */ - timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, - - /** Clear on event. */ - timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, - - /** Set on event. */ - timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET -} TIMER_OutputAction_TypeDef; - -/** Prescaler. */ -typedef enum { -#if defined (_TIMER_CTRL_PRESC_MASK) - timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ - timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ - timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ - timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ - timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ - timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ - timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ - timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ - timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ - timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ - timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ -#endif -#if defined (_TIMER_CFG_PRESC_MASK) - timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ - timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ - timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ - timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ - timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ - timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ - timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ - timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ - timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ - timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ - timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ -#endif -} TIMER_Prescale_TypeDef; - -/** Peripheral Reflex System signal. */ -typedef uint8_t TIMER_PRSSEL_TypeDef; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** Deprecated PRS channel selector. New code should use an integer instead of - * using these deprecated enum values. */ -#define timerPRSSELCh0 0UL -#define timerPRSSELCh1 1UL -#define timerPRSSELCh2 2UL -#define timerPRSSELCh3 3UL -#define timerPRSSELCh4 4UL -#define timerPRSSELCh5 5UL -#define timerPRSSELCh6 6UL -#define timerPRSSELCh7 7UL -#define timerPRSSELCh8 8UL -#define timerPRSSELCh9 9UL -#define timerPRSSELCh10 10UL -#define timerPRSSELCh11 11UL -/** @endcond */ - -#if defined (_TIMER_CC_CFG_INSEL_MASK) -/** PRS input type */ -typedef enum { - timerPrsInputNone = 0x0, /**< No PRS input. */ - timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, /**< Synchronous PRS selected. */ - timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, /**< Asynchronous level PRS selected. */ - timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, /**< Asynchronous pulse PRS selected. */ -} TIMER_PrsInput_TypeDef; -#endif - -#if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) -/** DT (Dead Time) Fault Actions. */ -typedef enum { -#if defined(_TIMER_DTFC_DTFA_MASK) - timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ - timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ - timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ - timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ -#endif -#if defined(_TIMER_DTFCFG_DTFA_MASK) - timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ - timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ - timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ - timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ -#endif -} TIMER_DtiFaultAction_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** TIMER initialization structure. */ -typedef struct { - /** Start counting when initialization completed. */ - bool enable; - - /** Counter shall keep running during debug halt. */ - bool debugRun; - - /** Prescaling factor, if HFPER / HFPERB clock used. */ - TIMER_Prescale_TypeDef prescale; - - /** Clock selection. */ - TIMER_ClkSel_TypeDef clkSel; - -#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ - && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) - /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ - bool count2x; - - /** ATI (Always Track Inputs) makes CCPOL always track - * the polarity of the inputs. */ - bool ati; - - /** Reload-Start Sets COIST - * When enabled, compare output is set to COIST value on a Reload-Start event. */ - bool rssCoist; -#endif - - /** Action on falling input edge. */ - TIMER_InputAction_TypeDef fallAction; - - /** Action on rising input edge. */ - TIMER_InputAction_TypeDef riseAction; - - /** Counting mode. */ - TIMER_Mode_TypeDef mode; - - /** DMA request clear on active. */ - bool dmaClrAct; - - /** Select X2 or X4 quadrature decode mode (if used). */ - bool quadModeX4; - - /** Determines if only counting up or down once. */ - bool oneShot; - - /** Timer can be start/stop/reload by other timers. */ - bool sync; - -#if defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT) - /** Disable ability of timer to start/stop/reload other timers that have their SYNC bit set. */ - bool disSyncOut; -#endif -} TIMER_Init_TypeDef; - -/** Default configuration for TIMER initialization structure. */ -#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ - && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) -#if (defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT)) -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - false, /* Not 2x count mode. */ \ - false, /* No ATI. */ \ - false, /* No RSSCOIST. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false, /* Not started/stopped/reloaded by other timers. */ \ - false /* Disable ability to start/stop/reload other timers. */ \ - } -#else -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - false, /* Not 2x count mode. */ \ - false, /* No ATI. */ \ - false, /* No RSSCOIST. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false /* Not started/stopped/reloaded by other timers. */ \ - } -#endif -#else -#define TIMER_INIT_DEFAULT \ - { \ - true, /* Enable timer when initialization completes. */ \ - false, /* Stop counter during debug halt. */ \ - timerPrescale1, /* No prescaling. */ \ - timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ - timerInputActionNone, /* No action on falling input edge. */ \ - timerInputActionNone, /* No action on rising input edge. */ \ - timerModeUp, /* Up-counting. */ \ - false, /* Do not clear DMA requests when DMA channel is active. */ \ - false, /* Select X2 quadrature decode mode (if used). */ \ - false, /* Disable one shot. */ \ - false /* Not started/stopped/reloaded by other timers. */ \ - } -#endif - -/** PRS Output configuration. */ -typedef enum { - timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ - timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ - timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ -} TIMER_PrsOutput_t; - -/** TIMER compare/capture initialization structure. */ -typedef struct { - /** Input capture event control. */ - TIMER_Event_TypeDef eventCtrl; - - /** Input capture edge select. */ - TIMER_Edge_TypeDef edge; - - /** - * Peripheral reflex system trigger selection. Only applicable if @p prsInput - * is enabled. - */ - TIMER_PRSSEL_TypeDef prsSel; - - /** Counter underflow output action. */ - TIMER_OutputAction_TypeDef cufoa; - - /** Counter overflow output action. */ - TIMER_OutputAction_TypeDef cofoa; - - /** Counter match output action. */ - TIMER_OutputAction_TypeDef cmoa; - - /** Compare/capture channel mode. */ - TIMER_CCMode_TypeDef mode; - - /** Enable digital filter. */ - bool filter; - - /** Select TIMERnCCx (false) or PRS input (true). */ - bool prsInput; - - /** - * Compare output initial state. Only used in Output Compare and PWM mode. - * When true, the compare/PWM output is set high when the counter is - * disabled. When counting resumes, this value will represent the initial - * value for the compare/PWM output. If the bit is cleared, the output - * will be cleared when the counter is disabled. - */ - bool coist; - - /** Invert output from compare/capture channel. */ - bool outInvert; - - /** - * PRS output configuration. PRS output from a timer can either be a - * pulse output or a level output that follows the CC out value. - */ - TIMER_PrsOutput_t prsOutput; - -#if defined(_TIMER_CC_CFG_INSEL_MASK) - /** When PRS input is used this field is used to configure the type of - * PRS input. */ - TIMER_PrsInput_TypeDef prsInputType; -#endif -} TIMER_InitCC_TypeDef; - -/** Default configuration for TIMER compare/capture initialization structure. */ -#if defined(_TIMER_CC_CFG_INSEL_MASK) -#define TIMER_INITCC_DEFAULT \ - { \ - timerEventEveryEdge, /* Event on every capture. */ \ - timerEdgeRising, /* Input capture edge on rising edge. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerOutputActionNone, /* No action on underflow. */ \ - timerOutputActionNone, /* No action on overflow. */ \ - timerOutputActionNone, /* No action on match. */ \ - timerCCModeOff, /* Disable compare/capture channel. */ \ - false, /* Disable filter. */ \ - false, /* No PRS input. */ \ - false, /* Clear output when counter disabled. */ \ - false, /* Do not invert output. */ \ - timerPrsOutputDefault, /* Use default PRS output configuration. */ \ - timerPrsInputNone /* No PRS input, so input type is none. */ \ - } -#else -#define TIMER_INITCC_DEFAULT \ - { \ - timerEventEveryEdge, /* Event on every capture. */ \ - timerEdgeRising, /* Input capture edge on rising edge. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerOutputActionNone, /* No action on underflow. */ \ - timerOutputActionNone, /* No action on overflow. */ \ - timerOutputActionNone, /* No action on match. */ \ - timerCCModeOff, /* Disable compare/capture channel. */ \ - false, /* Disable filter. */ \ - false, /* No PRS input. */ \ - false, /* Clear output when counter disabled. */ \ - false, /* Do not invert output. */ \ - timerPrsOutputDefault, /* Use default PRS output configuration. */ \ - } -#endif - -#if defined(_TIMER_DTCTRL_MASK) -/** TIMER Dead Time Insertion (DTI) initialization structure. */ -typedef struct { - /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ - bool enable; - - /** DTI Output Polarity. */ - bool activeLowOut; - - /** DTI Complementary Output Invert. */ - bool invertComplementaryOut; - - /** Enable Automatic Start-up functionality (when debugger exits). */ - bool autoRestart; - - /** Enable/disable PRS as DTI input. */ - bool enablePrsSource; - - /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource - is enabled. */ - TIMER_PRSSEL_TypeDef prsSel; - - /** DTI prescaling factor, if HFPER / HFPERB clock used. */ - TIMER_Prescale_TypeDef prescale; - - /** DTI Rise Time */ - unsigned int riseTime; - - /** DTI Fall Time */ - unsigned int fallTime; - - /** DTI outputs enable bit mask, consisting of one bit per DTI - output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. - This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags - (defined in \_timer.h) OR'ed together. */ - uint32_t outputsEnableMask; - - /** Enable core lockup as a fault source. */ - bool enableFaultSourceCoreLockup; - - /** Enable debugger as a fault source. */ - bool enableFaultSourceDebugger; - - /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ - bool enableFaultSourcePrsSel0; - - /** Select which PRS signal to be PRS fault source 0. */ - TIMER_PRSSEL_TypeDef faultSourcePrsSel0; - - /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ - bool enableFaultSourcePrsSel1; - - /** Select which PRS signal to be PRS fault source 1. */ - TIMER_PRSSEL_TypeDef faultSourcePrsSel1; - - /** Fault Action */ - TIMER_DtiFaultAction_TypeDef faultAction; -} TIMER_InitDTI_TypeDef; - -/** Default configuration for TIMER DTI initialization structure. */ -#define TIMER_INITDTI_DEFAULT \ - { \ - true, /* Enable the DTI. */ \ - false, /* CC[0|1|2] outputs are active high. */ \ - false, /* CDTI[0|1|2] outputs are not inverted. */ \ - false, /* No auto restart when debugger exits. */ \ - false, /* No PRS source selected. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerPrescale1, /* No prescaling. */ \ - 0, /* No rise time. */ \ - 0, /* No fall time. */ \ - TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ - true, /* Enable core lockup as fault source. */ \ - true, /* Enable debugger as fault source. */ \ - false, /* Disable PRS fault source 0. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - false, /* Disable PRS fault source 1. */ \ - 0, /* Not used by default, select PRS channel 0. */ \ - timerDtiFaultActionInactive, /* No fault action. */ \ - } -#endif /* _TIMER_DTCTRL_MASK */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -#if defined(TIMER_STATUS_SYNCBUSY) -void TIMER_SyncWait(TIMER_TypeDef * timer); -#endif - -/***************************************************************************//** - * @brief - * Validate the TIMER register block pointer. - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * True if ref points to a valid timer, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) -{ - return (ref == TIMER0) -#if defined(TIMER1) - || (ref == TIMER1) -#endif -#if defined(TIMER2) - || (ref == TIMER2) -#endif -#if defined(TIMER3) - || (ref == TIMER3) -#endif -#if defined(TIMER4) - || (ref == TIMER4) -#endif -#if defined(TIMER5) - || (ref == TIMER5) -#endif -#if defined(TIMER6) - || (ref == TIMER6) -#endif -#if defined(TIMER7) - || (ref == TIMER7) -#endif -#if defined(TIMER8) - || (ref == TIMER8) -#endif -#if defined(TIMER9) - || (ref == TIMER9) -#endif -#if defined(WTIMER0) - || (ref == WTIMER0) -#endif -#if defined(WTIMER1) - || (ref == WTIMER1) -#endif -#if defined(WTIMER2) - || (ref == WTIMER2) -#endif -#if defined(WTIMER3) - || (ref == WTIMER3) -#endif - ; -} - -/***************************************************************************//** - * @brief - * Check whether the TIMER is valid and supports Dead Timer Insertion (DTI). - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * True if ref points to a valid timer that supports DTI, false otherwise. - ******************************************************************************/ -__STATIC_INLINE bool TIMER_SupportsDTI(const TIMER_TypeDef *ref) -{ - (void) ref; - - return 0 -#if defined(TIMER0_DTI) -#if (TIMER0_DTI == 1) - || (ref == TIMER0) -#endif -#elif defined(_TIMER_DTCTRL_MASK) - || (ref == TIMER0) -#endif -#if defined(TIMER1_DTI) && (TIMER1_DTI == 1) - || (ref == TIMER1) -#endif -#if defined(TIMER2_DTI) && (TIMER2_DTI == 1) - || (ref == TIMER2) -#endif -#if defined(TIMER3_DTI) && (TIMER3_DTI == 1) - || (ref == TIMER3) -#endif -#if defined(TIMER4_DTI) && (TIMER4_DTI == 1) - || (ref == TIMER4) -#endif -#if defined(TIMER5_DTI) && (TIMER5_DTI == 1) - || (ref == TIMER5) -#endif -#if defined(TIMER6_DTI) && (TIMER6_DTI == 1) - || (ref == TIMER6) -#endif -#if defined(TIMER7_DTI) && (TIMER7_DTI == 1) - || (ref == TIMER7) -#endif -#if defined(TIMER8_DTI) && (TIMER8_DTI == 1) - || (ref == TIMER8) -#endif -#if defined(TIMER9_DTI) && (TIMER9_DTI == 1) - || (ref == TIMER9) -#endif -#if defined(WTIMER0) - || (ref == WTIMER0) -#endif - ; -} - -/***************************************************************************//** - * @brief - * Get the Max count of the timer. - * - * @param[in] ref - * Pointer to the TIMER peripheral register block. - * - * @return - * The max count value of the timer. This is 0xFFFF for 16 bit timers - * and 0xFFFFFFFF for 32 bit timers. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) -{ - (void) ref; - -#if defined(WTIMER_PRESENT) - if ((ref == WTIMER0) -#if defined(WTIMER1) - || (ref == WTIMER1) -#endif -#if defined(WTIMER2) - || (ref == WTIMER2) -#endif -#if defined(WTIMER3) - || (ref == WTIMER3) -#endif - ) { - return 0xFFFFFFFFUL; - } -#endif /* defined(WTIMER_PRESENT) */ - -#if defined(_SILICON_LABS_32B_SERIES_2) - EFM_ASSERT(TIMER_NUM(ref) != -1); - - return (uint32_t)((1ULL << TIMER_CNTWIDTH(TIMER_NUM(ref))) - 1); -#else - return 0xFFFFUL; -#endif /* defined(_SILICON_LABS_32B_SERIES_2) */ -} - -/***************************************************************************//** - * @brief - * Get compare/capture value for the compare/capture channel. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @return - * Current capture value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) -{ -#if defined (_TIMER_CC_CFG_MASK) - if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { - return timer->CC[ch].ICF; - } else { - return timer->CC[ch].OC; - } -#else - return timer->CC[ch].CCV; -#endif -} - -/***************************************************************************//** - * @brief - * Get the buffered compare/capture value for compare/capture channel. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @return - * Current buffered capture value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) -{ -#if defined (_TIMER_CC_CFG_MASK) - if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { - return timer->CC[ch].ICOF; - } else { - return timer->CC[ch].OCB; - } -#else - return timer->CC[ch].CCVB; -#endif -} - -/***************************************************************************//** - * @brief - * Set the compare value buffer for the compare/capture channel when operating in - * compare or PWM mode. - * - * @details - * The compare value buffer holds the value which will be written to - * TIMERn_CCx_CCV on an update event if the buffer has been updated since - * the last event. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @param[in] val - * Value to set in compare value buffer register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, - unsigned int ch, - uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (_TIMER_CC_CFG_MASK) - EFM_ASSERT(timer->EN & TIMER_EN_EN); - timer->CC[ch].OCB = val; -#else - timer->CC[ch].CCVB = val; -#endif -} - -/***************************************************************************//** - * @brief - * Set the compare value for compare/capture channel when operating in compare - * or PWM mode. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] ch - * Compare/capture channel to access. - * - * @param[in] val - * Value to set in compare value register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, - unsigned int ch, - uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (_TIMER_CC_CFG_MASK) - EFM_ASSERT(timer->EN & TIMER_EN_EN); - timer->CC[ch].OC = val; -#else - timer->CC[ch].CCV = val; -#endif -} - -/***************************************************************************//** - * @brief - * Get the TIMER counter value. - * - * @param[in] timer - * Pointer to TIMER peripheral register block. - * - * @return - * Current TIMER counter value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) -{ - return timer->CNT; -} - -/***************************************************************************//** - * @brief - * Set the TIMER counter value. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set counter to. - ******************************************************************************/ -__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined(TIMER_HAS_SET_CLEAR) - bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; - timer->EN_SET = TIMER_EN_EN; -#endif - timer->CNT = val; -#if defined(TIMER_HAS_SET_CLEAR) - if (!enabled) { - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - } -#endif -} - -/***************************************************************************//** - * @brief - * Start/stop TIMER. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] enable - * Set to true to enable counting; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - - if (enable) { - timer->CMD = TIMER_CMD_START; - } else { - timer->CMD = TIMER_CMD_STOP; - } -} - -void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); -void TIMER_InitCC(TIMER_TypeDef *timer, - unsigned int ch, - const TIMER_InitCC_TypeDef *init); - -#if defined(_TIMER_DTCTRL_MASK) -void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); - -/***************************************************************************//** - * @brief - * Enable or disable DTI unit. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] enable - * Set to true to enable DTI unit; set to false otherwise. - ******************************************************************************/ -__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) -{ -#if defined(TIMER_HAS_SET_CLEAR) - uint32_t timerEn = timer->EN & TIMER_EN_EN; - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - if (enable) { - timer->DTCFG_SET = TIMER_DTCFG_DTEN; - } else { - timer->DTCFG_CLR = TIMER_DTCFG_DTEN; - } - timer->EN_SET = timerEn; -#else - EFM_ASSERT(TIMER_SupportsDTI(timer)); - - if (enable) { - timer->DTCTRL |= TIMER_DTCTRL_DTEN; - } else { - timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; - } -#endif -} - -/***************************************************************************//** - * @brief - * Get DTI fault source flags status. - * - * @note - * Event bits are not cleared by this function. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * Status of the DTI fault source flags. Returns one or more valid - * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); - return timer->DTFAULT; -} - -/***************************************************************************//** - * @brief - * Clear DTI fault source flags. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * DTI fault source(s) to clear. Use one or more valid DTI fault - * source flags (TIMER_DTFAULT_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) - -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTFAULTC = flags; -} -#endif /* _TIMER_DTCTRL_MASK */ - -/***************************************************************************//** - * @brief - * Clear one or more pending TIMER interrupts. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * Pending TIMER interrupt source(s) to clear. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) -{ -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_CLR = flags; -#else - timer->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more TIMER interrupts. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to disable. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) -{ - timer->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more TIMER interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * TIMER_IntClear() prior to enabling the interrupt. - - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to enable. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) -{ - timer->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending TIMER interrupt flags. - * - * @note - * Event bits are not cleared by this function. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * TIMER interrupt source(s) pending. Returns one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) -{ - return timer->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending TIMER interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @note - * Interrupt flags are not cleared by this function. - * - * @return - * Pending and enabled TIMER interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn - * register (TIMERx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the TIMER module - * (TIMERx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) -{ - uint32_t ien; - - /* Store TIMER->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = timer->IEN; - - /* Bitwise AND of pending and enabled interrupts */ - return timer->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending TIMER interrupts from SW. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] flags - * TIMER interrupt source(s) to set to pending. Use one or more valid - * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) -{ -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_SET = flags; -#else - timer->IFS = flags; -#endif -} - -#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) -/***************************************************************************//** - * @brief - * Lock some TIMER registers to protect them from being - * modified. - * - * @details - * Refer to the reference manual for TIMER registers that will be locked. - * - * @note - * If locking the TIMER registers, they must be unlocked prior to using any - * TIMER API function that modifies TIMER registers protected by the lock. - * - * @param[in] timer - * Pointer to TIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER0 == timer); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; -} -#endif - -void TIMER_Reset(TIMER_TypeDef *timer); - -/***************************************************************************//** - * @brief - * Set the top value buffer for the timer. - * - * @details - * When top value buffer register is updated, value is loaded into - * top value register at the next wrap around. This feature is useful - * in order to update top value safely when timer is running. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set in top value buffer register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->TOPB = val; -} - -/***************************************************************************//** - * @brief - * Get the top value setting for the timer. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @return - * Current top value. - ******************************************************************************/ -__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) -{ - return timer->TOP; -} - -/***************************************************************************//** - * @brief - * Set the top value for timer. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - * - * @param[in] val - * Value to set in top value register. - ******************************************************************************/ -__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) -{ - EFM_ASSERT(val <= TIMER_MaxCount(timer)); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->TOP = val; -} - -#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) -/***************************************************************************//** - * @brief - * Unlock TIMER to enable writing to locked registers again. - * - * @param[in] timer - * Pointer to the TIMER peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) -{ - EFM_ASSERT(TIMER0 == timer); -#if defined (TIMER_EN_EN) - EFM_ASSERT(timer->EN & TIMER_EN_EN); -#endif - - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; -} -#endif - -/** @} (end addtogroup timer) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ -#endif /* EM_TIMER_H */ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_TIMER_H +#define EM_TIMER_H + +#include "em_device.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include +#include "sl_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup timer + * @{ + ****************************************************************************** + * @deprecated + * Deprecated macro TIMER_CH_VALID for SDID 80, new code should use TIMER_REF_CH_VALID.*/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of TIMER register block pointer reference for assert statements. */ +#define TIMER_REF_VALID(ref) TIMER_Valid(ref) + +/** Validation of TIMER compare/capture channel number. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#define TIMER_CH_VALID(ch) ((ch) < 3) +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_CH_VALID(ch) _Pragma("GCC warning \"'TIMER_CH_VALID' macro is deprecated for EFR32xG1, Use TIMER_REF_CH_VALID instead\"") ((ch) < 4) +#else +#define TIMER_CH_VALID(ch) ((ch) < 4) +#endif +#else +#define TIMER_CH_VALID(ch) ((ch) < 3) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define TIMER_REF_CH_VALID(ref, ch) ((ref == TIMER0) ? ((ch) < 3) : ((ch) < 4)) +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_REF_CH_VALID(ref, ch) +#else +#define TIMER_REF_CH_VALIDATE(ref, ch) TIMER_CH_VALID(ch) +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Timer compare/capture mode. */ +typedef enum { +#if defined (_TIMER_CC_CTRL_MODE_MASK) + timerCCModeOff = _TIMER_CC_CTRL_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CTRL_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CTRL_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CTRL_MODE_PWM /**< Pulse-Width modulation. */ +#endif +#if defined (_TIMER_CC_CFG_MODE_MASK) + timerCCModeOff = _TIMER_CC_CFG_MODE_OFF, /**< Channel turned off. */ + timerCCModeCapture = _TIMER_CC_CFG_MODE_INPUTCAPTURE, /**< Input capture. */ + timerCCModeCompare = _TIMER_CC_CFG_MODE_OUTPUTCOMPARE, /**< Output compare. */ + timerCCModePWM = _TIMER_CC_CFG_MODE_PWM /**< Pulse-Width modulation. */ +#endif +} TIMER_CCMode_TypeDef; + +/** Clock select. */ +typedef enum { +#if defined (_TIMER_CTRL_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CTRL_CLKSEL_PRESCHFPERCLK, /**< Prescaled HFPER / HFPERB clock. */ + timerClkSelCC1 = _TIMER_CTRL_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CTRL_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +#if defined (_TIMER_CFG_CLKSEL_MASK) + timerClkSelHFPerClk = _TIMER_CFG_CLKSEL_PRESCEM01GRPACLK, /**< Prescaled EM01GRPA clock. */ + timerClkSelCC1 = _TIMER_CFG_CLKSEL_CC1, /**< Compare/Capture Channel 1 Input. */ + timerClkSelCascade = _TIMER_CFG_CLKSEL_TIMEROUF /**< Cascaded clocked by underflow or overflow by lower numbered timer. */ +#endif +} TIMER_ClkSel_TypeDef; + +/** Input capture edge select. */ +typedef enum { + /** Rising edges detected. */ + timerEdgeRising = _TIMER_CC_CTRL_ICEDGE_RISING, + + /** Falling edges detected. */ + timerEdgeFalling = _TIMER_CC_CTRL_ICEDGE_FALLING, + + /** Both edges detected. */ + timerEdgeBoth = _TIMER_CC_CTRL_ICEDGE_BOTH, + + /** No edge detection, leave signal as is. */ + timerEdgeNone = _TIMER_CC_CTRL_ICEDGE_NONE +} TIMER_Edge_TypeDef; + +/** Input capture event control. */ +typedef enum { + /** PRS output pulse, interrupt flag, and DMA request set on every capture. */ + timerEventEveryEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE, + /** PRS output pulse, interrupt flag, and DMA request set on every second capture. */ + timerEventEvery2ndEdge = _TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE, + /** + * PRS output pulse, interrupt flag, and DMA request set on rising edge (if + * input capture edge = BOTH). + */ + timerEventRising = _TIMER_CC_CTRL_ICEVCTRL_RISING, + /** + * PRS output pulse, interrupt flag, and DMA request set on falling edge (if + * input capture edge = BOTH). + */ + timerEventFalling = _TIMER_CC_CTRL_ICEVCTRL_FALLING +} TIMER_Event_TypeDef; + +/** Input edge action. */ +typedef enum { + /** No action taken. */ + timerInputActionNone = _TIMER_CTRL_FALLA_NONE, + + /** Start counter without reload. */ + timerInputActionStart = _TIMER_CTRL_FALLA_START, + + /** Stop counter without reload. */ + timerInputActionStop = _TIMER_CTRL_FALLA_STOP, + + /** Reload and start counter. */ + timerInputActionReloadStart = _TIMER_CTRL_FALLA_RELOADSTART +} TIMER_InputAction_TypeDef; + +/** Timer mode. */ +typedef enum { +#if defined (_TIMER_CTRL_MODE_MASK) + timerModeUp = _TIMER_CTRL_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CTRL_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CTRL_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CTRL_MODE_QDEC /**< Quadrature decoder. */ +#endif +#if defined (_TIMER_CFG_MODE_MASK) + timerModeUp = _TIMER_CFG_MODE_UP, /**< Up-counting. */ + timerModeDown = _TIMER_CFG_MODE_DOWN, /**< Down-counting. */ + timerModeUpDown = _TIMER_CFG_MODE_UPDOWN, /**< Up/down-counting. */ + timerModeQDec = _TIMER_CFG_MODE_QDEC /**< Quadrature decoder. */ +#endif +} TIMER_Mode_TypeDef; + +/** Compare/capture output action. */ +typedef enum { + /** No action. */ + timerOutputActionNone = _TIMER_CC_CTRL_CUFOA_NONE, + + /** Toggle on event. */ + timerOutputActionToggle = _TIMER_CC_CTRL_CUFOA_TOGGLE, + + /** Clear on event. */ + timerOutputActionClear = _TIMER_CC_CTRL_CUFOA_CLEAR, + + /** Set on event. */ + timerOutputActionSet = _TIMER_CC_CTRL_CUFOA_SET +} TIMER_OutputAction_TypeDef; + +/** Prescaler. */ +typedef enum { +#if defined (_TIMER_CTRL_PRESC_MASK) + timerPrescale1 = _TIMER_CTRL_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CTRL_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CTRL_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CTRL_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CTRL_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CTRL_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CTRL_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CTRL_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CTRL_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CTRL_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CTRL_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +#if defined (_TIMER_CFG_PRESC_MASK) + timerPrescale1 = _TIMER_CFG_PRESC_DIV1, /**< Divide by 1. */ + timerPrescale2 = _TIMER_CFG_PRESC_DIV2, /**< Divide by 2. */ + timerPrescale4 = _TIMER_CFG_PRESC_DIV4, /**< Divide by 4. */ + timerPrescale8 = _TIMER_CFG_PRESC_DIV8, /**< Divide by 8. */ + timerPrescale16 = _TIMER_CFG_PRESC_DIV16, /**< Divide by 16. */ + timerPrescale32 = _TIMER_CFG_PRESC_DIV32, /**< Divide by 32. */ + timerPrescale64 = _TIMER_CFG_PRESC_DIV64, /**< Divide by 64. */ + timerPrescale128 = _TIMER_CFG_PRESC_DIV128, /**< Divide by 128. */ + timerPrescale256 = _TIMER_CFG_PRESC_DIV256, /**< Divide by 256. */ + timerPrescale512 = _TIMER_CFG_PRESC_DIV512, /**< Divide by 512. */ + timerPrescale1024 = _TIMER_CFG_PRESC_DIV1024 /**< Divide by 1024. */ +#endif +} TIMER_Prescale_TypeDef; + +/** Peripheral Reflex System signal. */ +typedef uint8_t TIMER_PRSSEL_TypeDef; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector. New code should use an integer instead of + * using these deprecated enum values. */ +#define timerPRSSELCh0 0UL +#define timerPRSSELCh1 1UL +#define timerPRSSELCh2 2UL +#define timerPRSSELCh3 3UL +#define timerPRSSELCh4 4UL +#define timerPRSSELCh5 5UL +#define timerPRSSELCh6 6UL +#define timerPRSSELCh7 7UL +#define timerPRSSELCh8 8UL +#define timerPRSSELCh9 9UL +#define timerPRSSELCh10 10UL +#define timerPRSSELCh11 11UL +/** @endcond */ + +#if defined (_TIMER_CC_CFG_INSEL_MASK) +/** PRS input type */ +typedef enum { + timerPrsInputNone = 0x0, /**< No PRS input. */ + timerPrsInputSync = _TIMER_CC_CFG_INSEL_PRSSYNC, /**< Synchronous PRS selected. */ + timerPrsInputAsyncLevel = _TIMER_CC_CFG_INSEL_PRSASYNCLEVEL, /**< Asynchronous level PRS selected. */ + timerPrsInputAsyncPulse = _TIMER_CC_CFG_INSEL_PRSASYNCPULSE, /**< Asynchronous pulse PRS selected. */ +} TIMER_PrsInput_TypeDef; +#endif + +#if defined(_TIMER_DTFC_DTFA_MASK) || defined(_TIMER_DTFCFG_DTFA_MASK) +/** DT (Dead Time) Fault Actions. */ +typedef enum { +#if defined(_TIMER_DTFC_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFC_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFC_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFC_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFC_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +#if defined(_TIMER_DTFCFG_DTFA_MASK) + timerDtiFaultActionNone = _TIMER_DTFCFG_DTFA_NONE, /**< No action on fault. */ + timerDtiFaultActionInactive = _TIMER_DTFCFG_DTFA_INACTIVE, /**< Set outputs inactive. */ + timerDtiFaultActionClear = _TIMER_DTFCFG_DTFA_CLEAR, /**< Clear outputs. */ + timerDtiFaultActionTristate = _TIMER_DTFCFG_DTFA_TRISTATE /**< Tristate outputs. */ +#endif +} TIMER_DtiFaultAction_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** TIMER initialization structure. */ +typedef struct { + /** Start counting when initialization completed. */ + bool enable; + + /** Counter shall keep running during debug halt. */ + bool debugRun; + + /** Prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** Clock selection. */ + TIMER_ClkSel_TypeDef clkSel; + +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) + /** 2x Count mode, counter increments/decrements by 2, meant for PWM mode. */ + bool count2x; + + /** ATI (Always Track Inputs) makes CCPOL always track + * the polarity of the inputs. */ + bool ati; + + /** Reload-Start Sets COIST + * When enabled, compare output is set to COIST value on a Reload-Start event. */ + bool rssCoist; +#endif + + /** Action on falling input edge. */ + TIMER_InputAction_TypeDef fallAction; + + /** Action on rising input edge. */ + TIMER_InputAction_TypeDef riseAction; + + /** Counting mode. */ + TIMER_Mode_TypeDef mode; + + /** DMA request clear on active. */ + bool dmaClrAct; + + /** Select X2 or X4 quadrature decode mode (if used). */ + bool quadModeX4; + + /** Determines if only counting up or down once. */ + bool oneShot; + + /** Timer can be start/stop/reload by other timers. */ + bool sync; + +#if defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT) + /** Disable ability of timer to start/stop/reload other timers that have their SYNC bit set. */ + bool disSyncOut; +#endif +} TIMER_Init_TypeDef; + +/** Default configuration for TIMER initialization structure. */ +#if defined(TIMER_CTRL_X2CNT) && (defined(TIMER_CTRL_ATI) || defined(TIMER_CFG_ATI)) \ + && (defined(TIMER_CTRL_RSSCOIST) || defined(TIMER_CFG_RSSCOIST)) +#if (defined(TIMER_CTRL_DISSYNCOUT) || defined(TIMER_CFG_DISSYNCOUT)) +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false, /* Not started/stopped/reloaded by other timers. */ \ + false /* Disable ability to start/stop/reload other timers. */ \ + } +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + false, /* Not 2x count mode. */ \ + false, /* No ATI. */ \ + false, /* No RSSCOIST. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif +#else +#define TIMER_INIT_DEFAULT \ + { \ + true, /* Enable timer when initialization completes. */ \ + false, /* Stop counter during debug halt. */ \ + timerPrescale1, /* No prescaling. */ \ + timerClkSelHFPerClk, /* Select HFPER / HFPERB clock. */ \ + timerInputActionNone, /* No action on falling input edge. */ \ + timerInputActionNone, /* No action on rising input edge. */ \ + timerModeUp, /* Up-counting. */ \ + false, /* Do not clear DMA requests when DMA channel is active. */ \ + false, /* Select X2 quadrature decode mode (if used). */ \ + false, /* Disable one shot. */ \ + false /* Not started/stopped/reloaded by other timers. */ \ + } +#endif + +/** PRS Output configuration. */ +typedef enum { + timerPrsOutputPulse = 0, /**< Pulse PRS output from a channel. */ + timerPrsOutputLevel = 1, /**< PRS output follows CC out level. */ + timerPrsOutputDefault = timerPrsOutputPulse, /**< Default PRS output behavior. */ +} TIMER_PrsOutput_t; + +/** TIMER compare/capture initialization structure. */ +typedef struct { + /** Input capture event control. */ + TIMER_Event_TypeDef eventCtrl; + + /** Input capture edge select. */ + TIMER_Edge_TypeDef edge; + + /** + * Peripheral reflex system trigger selection. Only applicable if @p prsInput + * is enabled. + */ + TIMER_PRSSEL_TypeDef prsSel; + + /** Counter underflow output action. */ + TIMER_OutputAction_TypeDef cufoa; + + /** Counter overflow output action. */ + TIMER_OutputAction_TypeDef cofoa; + + /** Counter match output action. */ + TIMER_OutputAction_TypeDef cmoa; + + /** Compare/capture channel mode. */ + TIMER_CCMode_TypeDef mode; + + /** Enable digital filter. */ + bool filter; + + /** Select TIMERnCCx (false) or PRS input (true). */ + bool prsInput; + + /** + * Compare output initial state. Only used in Output Compare and PWM mode. + * When true, the compare/PWM output is set high when the counter is + * disabled. When counting resumes, this value will represent the initial + * value for the compare/PWM output. If the bit is cleared, the output + * will be cleared when the counter is disabled. + */ + bool coist; + + /** Invert output from compare/capture channel. */ + bool outInvert; + + /** + * PRS output configuration. PRS output from a timer can either be a + * pulse output or a level output that follows the CC out value. + */ + TIMER_PrsOutput_t prsOutput; + +#if defined(_TIMER_CC_CFG_INSEL_MASK) + /** When PRS input is used this field is used to configure the type of + * PRS input. */ + TIMER_PrsInput_TypeDef prsInputType; +#endif +} TIMER_InitCC_TypeDef; + +/** Default configuration for TIMER compare/capture initialization structure. */ +#if defined(_TIMER_CC_CFG_INSEL_MASK) +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + timerPrsInputNone /* No PRS input, so input type is none. */ \ + } +#else +#define TIMER_INITCC_DEFAULT \ + { \ + timerEventEveryEdge, /* Event on every capture. */ \ + timerEdgeRising, /* Input capture edge on rising edge. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerOutputActionNone, /* No action on underflow. */ \ + timerOutputActionNone, /* No action on overflow. */ \ + timerOutputActionNone, /* No action on match. */ \ + timerCCModeOff, /* Disable compare/capture channel. */ \ + false, /* Disable filter. */ \ + false, /* No PRS input. */ \ + false, /* Clear output when counter disabled. */ \ + false, /* Do not invert output. */ \ + timerPrsOutputDefault, /* Use default PRS output configuration. */ \ + } +#endif + +#if defined(_TIMER_DTCTRL_MASK) +/** TIMER Dead Time Insertion (DTI) initialization structure. */ +typedef struct { + /** Enable DTI or leave it disabled until @ref TIMER_EnableDTI() is called. */ + bool enable; + + /** DTI Output Polarity. */ + bool activeLowOut; + + /** DTI Complementary Output Invert. */ + bool invertComplementaryOut; + + /** Enable Automatic Start-up functionality (when debugger exits). */ + bool autoRestart; + + /** Enable/disable PRS as DTI input. */ + bool enablePrsSource; + + /** Select which PRS channel as DTI input. Only valid if @p enablePrsSource + is enabled. */ + TIMER_PRSSEL_TypeDef prsSel; + + /** DTI prescaling factor, if HFPER / HFPERB clock used. */ + TIMER_Prescale_TypeDef prescale; + + /** DTI Rise Time */ + unsigned int riseTime; + + /** DTI Fall Time */ + unsigned int fallTime; + + /** DTI outputs enable bit mask, consisting of one bit per DTI + output signal, i.e., CC0, CC1, CC2, CDTI0, CDTI1, and CDTI2. + This value should consist of one or more TIMER_DTOGEN_DTOGnnnEN flags + (defined in \_timer.h) OR'ed together. */ + uint32_t outputsEnableMask; + + /** Enable core lockup as a fault source. */ + bool enableFaultSourceCoreLockup; + + /** Enable debugger as a fault source. */ + bool enableFaultSourceDebugger; + + /** Enable PRS fault source 0 (@p faultSourcePrsSel0). */ + bool enableFaultSourcePrsSel0; + + /** Select which PRS signal to be PRS fault source 0. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel0; + + /** Enable PRS fault source 1 (@p faultSourcePrsSel1). */ + bool enableFaultSourcePrsSel1; + + /** Select which PRS signal to be PRS fault source 1. */ + TIMER_PRSSEL_TypeDef faultSourcePrsSel1; + + /** Fault Action */ + TIMER_DtiFaultAction_TypeDef faultAction; +} TIMER_InitDTI_TypeDef; + +/** Default configuration for TIMER DTI initialization structure. */ +#define TIMER_INITDTI_DEFAULT \ + { \ + true, /* Enable the DTI. */ \ + false, /* CC[0|1|2] outputs are active high. */ \ + false, /* CDTI[0|1|2] outputs are not inverted. */ \ + false, /* No auto restart when debugger exits. */ \ + false, /* No PRS source selected. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerPrescale1, /* No prescaling. */ \ + 0, /* No rise time. */ \ + 0, /* No fall time. */ \ + TIMER_DTOGEN_DTOGCC0EN | TIMER_DTOGEN_DTOGCDTI0EN, /* Enable CC0 and CDTI0. */ \ + true, /* Enable core lockup as fault source. */ \ + true, /* Enable debugger as fault source. */ \ + false, /* Disable PRS fault source 0. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + false, /* Disable PRS fault source 1. */ \ + 0, /* Not used by default, select PRS channel 0. */ \ + timerDtiFaultActionInactive, /* No fault action. */ \ + } +#endif /* _TIMER_DTCTRL_MASK */ + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +#if defined(TIMER_STATUS_SYNCBUSY) +void TIMER_SyncWait(TIMER_TypeDef * timer); +#endif + +/***************************************************************************//** + * @brief + * Validate the TIMER register block pointer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_Valid(const TIMER_TypeDef *ref) +{ + return (ref == TIMER0) +#if defined(TIMER1) + || (ref == TIMER1) +#endif +#if defined(TIMER2) + || (ref == TIMER2) +#endif +#if defined(TIMER3) + || (ref == TIMER3) +#endif +#if defined(TIMER4) + || (ref == TIMER4) +#endif +#if defined(TIMER5) + || (ref == TIMER5) +#endif +#if defined(TIMER6) + || (ref == TIMER6) +#endif +#if defined(TIMER7) + || (ref == TIMER7) +#endif +#if defined(TIMER8) + || (ref == TIMER8) +#endif +#if defined(TIMER9) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Check whether the TIMER is valid and supports Dead Timer Insertion (DTI). + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * True if ref points to a valid timer that supports DTI, false otherwise. + ******************************************************************************/ +__STATIC_INLINE bool TIMER_SupportsDTI(const TIMER_TypeDef *ref) +{ + (void) ref; + + return 0 +#if defined(TIMER0_DTI) +#if (TIMER0_DTI == 1) + || (ref == TIMER0) +#endif +#elif defined(_TIMER_DTCTRL_MASK) + || (ref == TIMER0) +#endif +#if defined(TIMER1_DTI) && (TIMER1_DTI == 1) + || (ref == TIMER1) +#endif +#if defined(TIMER2_DTI) && (TIMER2_DTI == 1) + || (ref == TIMER2) +#endif +#if defined(TIMER3_DTI) && (TIMER3_DTI == 1) + || (ref == TIMER3) +#endif +#if defined(TIMER4_DTI) && (TIMER4_DTI == 1) + || (ref == TIMER4) +#endif +#if defined(TIMER5_DTI) && (TIMER5_DTI == 1) + || (ref == TIMER5) +#endif +#if defined(TIMER6_DTI) && (TIMER6_DTI == 1) + || (ref == TIMER6) +#endif +#if defined(TIMER7_DTI) && (TIMER7_DTI == 1) + || (ref == TIMER7) +#endif +#if defined(TIMER8_DTI) && (TIMER8_DTI == 1) + || (ref == TIMER8) +#endif +#if defined(TIMER9_DTI) && (TIMER9_DTI == 1) + || (ref == TIMER9) +#endif +#if defined(WTIMER0) + || (ref == WTIMER0) +#endif + ; +} + +/***************************************************************************//** + * @brief + * Get the Max count of the timer. + * + * @param[in] ref + * Pointer to the TIMER peripheral register block. + * + * @return + * The max count value of the timer. This is 0xFFFF for 16 bit timers + * and 0xFFFFFFFF for 32 bit timers. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_MaxCount(const TIMER_TypeDef *ref) +{ + (void) ref; + +#if defined(WTIMER_PRESENT) + if ((ref == WTIMER0) +#if defined(WTIMER1) + || (ref == WTIMER1) +#endif +#if defined(WTIMER2) + || (ref == WTIMER2) +#endif +#if defined(WTIMER3) + || (ref == WTIMER3) +#endif + ) { + return 0xFFFFFFFFUL; + } +#endif /* defined(WTIMER_PRESENT) */ + +#if defined(_SILICON_LABS_32B_SERIES_2) + EFM_ASSERT(TIMER_NUM(ref) != -1); + + return (uint32_t)((1ULL << TIMER_CNTWIDTH(TIMER_NUM(ref))) - 1); +#else + return 0xFFFFUL; +#endif /* defined(_SILICON_LABS_32B_SERIES_2) */ +} + +/***************************************************************************//** + * @brief + * Get compare/capture value for the compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICF; + } else { + return timer->CC[ch].OC; + } +#else + return timer->CC[ch].CCV; +#endif +} + +/***************************************************************************//** + * @brief + * Get the buffered compare/capture value for compare/capture channel. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @return + * Current buffered capture value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CaptureBufGet(TIMER_TypeDef *timer, unsigned int ch) +{ +#if defined (_TIMER_CC_CFG_MASK) + if ((timer->CC[ch].CFG & _TIMER_CC_CFG_MODE_MASK) == TIMER_CC_CFG_MODE_INPUTCAPTURE) { + return timer->CC[ch].ICOF; + } else { + return timer->CC[ch].OCB; + } +#else + return timer->CC[ch].CCVB; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value buffer for the compare/capture channel when operating in + * compare or PWM mode. + * + * @details + * The compare value buffer holds the value which will be written to + * TIMERn_CCx_CCV on an update event if the buffer has been updated since + * the last event. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareBufSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OCB = val; +#else + timer->CC[ch].CCVB = val; +#endif +} + +/***************************************************************************//** + * @brief + * Set the compare value for compare/capture channel when operating in compare + * or PWM mode. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] ch + * Compare/capture channel to access. + * + * @param[in] val + * Value to set in compare value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CompareSet(TIMER_TypeDef *timer, + unsigned int ch, + uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (_TIMER_CC_CFG_MASK) + EFM_ASSERT(timer->EN & TIMER_EN_EN); + timer->CC[ch].OC = val; +#else + timer->CC[ch].CCV = val; +#endif +} + +/***************************************************************************//** + * @brief + * Get the TIMER counter value. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + * + * @return + * Current TIMER counter value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_CounterGet(TIMER_TypeDef *timer) +{ + return timer->CNT; +} + +/***************************************************************************//** + * @brief + * Set the TIMER counter value. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set counter to. + ******************************************************************************/ +__STATIC_INLINE void TIMER_CounterSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined(TIMER_HAS_SET_CLEAR) + bool enabled = (timer->EN & TIMER_EN_EN) != 0UL; + timer->EN_SET = TIMER_EN_EN; +#endif + timer->CNT = val; +#if defined(TIMER_HAS_SET_CLEAR) + if (!enabled) { + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + } +#endif +} + +/***************************************************************************//** + * @brief + * Start/stop TIMER. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable counting; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Enable(TIMER_TypeDef *timer, bool enable) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + + if (enable) { + timer->CMD = TIMER_CMD_START; + } else { + timer->CMD = TIMER_CMD_STOP; + } +} + +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init); +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init); + +#if defined(_TIMER_DTCTRL_MASK) +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init); + +/***************************************************************************//** + * @brief + * Enable or disable DTI unit. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] enable + * Set to true to enable DTI unit; set to false otherwise. + ******************************************************************************/ +__STATIC_INLINE void TIMER_EnableDTI(TIMER_TypeDef *timer, bool enable) +{ +#if defined(TIMER_HAS_SET_CLEAR) + uint32_t timerEn = timer->EN & TIMER_EN_EN; + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + if (enable) { + timer->DTCFG_SET = TIMER_DTCFG_DTEN; + } else { + timer->DTCFG_CLR = TIMER_DTCFG_DTEN; + } + timer->EN_SET = timerEn; +#else + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + if (enable) { + timer->DTCTRL |= TIMER_DTCTRL_DTEN; + } else { + timer->DTCTRL &= ~TIMER_DTCTRL_DTEN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Get DTI fault source flags status. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Status of the DTI fault source flags. Returns one or more valid + * DTI fault source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_GetDTIFault(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + return timer->DTFAULT; +} + +/***************************************************************************//** + * @brief + * Clear DTI fault source flags. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * DTI fault source(s) to clear. Use one or more valid DTI fault + * source flags (TIMER_DTFAULT_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_ClearDTIFault(TIMER_TypeDef *timer, uint32_t flags) + +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTFAULTC = flags; +} +#endif /* _TIMER_DTCTRL_MASK */ + +/***************************************************************************//** + * @brief + * Clear one or more pending TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * Pending TIMER interrupt source(s) to clear. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntClear(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = flags; +#else + timer->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more TIMER interrupts. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to disable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntDisable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more TIMER interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * TIMER_IntClear() prior to enabling the interrupt. + + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to enable. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntEnable(TIMER_TypeDef *timer, uint32_t flags) +{ + timer->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending TIMER interrupt flags. + * + * @note + * Event bits are not cleared by this function. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * TIMER interrupt source(s) pending. Returns one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGet(TIMER_TypeDef *timer) +{ + return timer->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending TIMER interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @note + * Interrupt flags are not cleared by this function. + * + * @return + * Pending and enabled TIMER interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in TIMERx_IEN_nnn + * register (TIMERx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the TIMER module + * (TIMERx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_IntGetEnabled(TIMER_TypeDef *timer) +{ + uint32_t ien; + + /* Store TIMER->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = timer->IEN; + + /* Bitwise AND of pending and enabled interrupts */ + return timer->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending TIMER interrupts from SW. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] flags + * TIMER interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the TIMER module (TIMER_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void TIMER_IntSet(TIMER_TypeDef *timer, uint32_t flags) +{ +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_SET = flags; +#else + timer->IFS = flags; +#endif +} + +#if defined(_TIMER_DTLOCK_LOCKKEY_LOCK) +/***************************************************************************//** + * @brief + * Lock some TIMER registers to protect them from being + * modified. + * + * @details + * Refer to the reference manual for TIMER registers that will be locked. + * + * @note + * If locking the TIMER registers, they must be unlocked prior to using any + * TIMER API function that modifies TIMER registers protected by the lock. + * + * @param[in] timer + * Pointer to TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Lock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_LOCK; +} +#endif + +void TIMER_Reset(TIMER_TypeDef *timer); + +/***************************************************************************//** + * @brief + * Set the top value buffer for the timer. + * + * @details + * When top value buffer register is updated, value is loaded into + * top value register at the next wrap around. This feature is useful + * in order to update top value safely when timer is running. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value buffer register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopBufSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOPB = val; +} + +/***************************************************************************//** + * @brief + * Get the top value setting for the timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @return + * Current top value. + ******************************************************************************/ +__STATIC_INLINE uint32_t TIMER_TopGet(TIMER_TypeDef *timer) +{ + return timer->TOP; +} + +/***************************************************************************//** + * @brief + * Set the top value for timer. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + * + * @param[in] val + * Value to set in top value register. + ******************************************************************************/ +__STATIC_INLINE void TIMER_TopSet(TIMER_TypeDef *timer, uint32_t val) +{ + EFM_ASSERT(val <= TIMER_MaxCount(timer)); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->TOP = val; +} + +#if defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) +/***************************************************************************//** + * @brief + * Unlock TIMER to enable writing to locked registers again. + * + * @param[in] timer + * Pointer to the TIMER peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void TIMER_Unlock(TIMER_TypeDef *timer) +{ + EFM_ASSERT(TIMER0 == timer); +#if defined (TIMER_EN_EN) + EFM_ASSERT(timer->EN & TIMER_EN_EN); +#endif + + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; +} +#endif + +/** @} (end addtogroup timer) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ +#endif /* EM_TIMER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h index c4c0305..170b7a9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_usart.h @@ -1,1093 +1,1093 @@ -/***************************************************************************//** - * @file - * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) - * peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_USART_H -#define EM_USART_H - -#include "em_device.h" -#if defined(USART_COUNT) && (USART_COUNT > 0) - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup usart USART - Synchronous/Asynchronous Serial - * @brief Universal Synchronous/Asynchronous Receiver/Transmitter - * Peripheral API - * @details - * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) - * is a very flexible serial I/O module. It supports full duplex asynchronous UART - * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface - * with ISO7816 Smart-Cards, and IrDA devices. - * - * The USART has a wide selection of operating modes, frame formats, and baud rates. - * All features are supported through the API of this module. - * - * Triple buffering and DMA support makes high data-rates possible with minimal - * CPU intervention. It is possible to transmit and receive large frames while - * the MCU remains in EM1 Sleep. - * - * This module does not support DMA configuration. The UARTDRV and SPIDRV drivers - * provide full support for DMA and more. - * - * The following steps are necessary for basic operation: - * - * Clock enable: - * @include em_usart_clock_enable.c - * - * To initialize the USART for asynchronous operation (e.g., UART): - * @include em_usart_init_async.c - * - * To initialize the USART for synchronous operation (e.g., SPI): - * @include em_usart_init_sync.c - * - * After pins are assigned for the application/board, enable pins at the - * desired location. Available locations can be obtained from the Pin Definitions - * section in the data sheet. - * @if DOXYDOC_P1_DEVICE - * @include em_usart_route_p1.c - * @note UART hardware flow control is not directly supported in hardware on - * _SILICON_LABS_32B_SERIES_0 parts. - * @endif - * @if DOXYDOC_P2_DEVICE - * @include em_usart_route_p2.c - * @endif - * @note UARTDRV supports all types of UART flow control. Software assisted - * hardware flow control is available for parts without true UART hardware - * flow control. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Databit selection. */ -typedef enum { - usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ - usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ - usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ - usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ - usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ - usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ - usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ - usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ - usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ - usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ - usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ - usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ - usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ -} USART_Databits_TypeDef; - -/** Enable selection. */ -typedef enum { - /** Disable both receiver and transmitter. */ - usartDisable = 0x0, - - /** Enable receiver only, transmitter disabled. */ - usartEnableRx = USART_CMD_RXEN, - - /** Enable transmitter only, receiver disabled. */ - usartEnableTx = USART_CMD_TXEN, - - /** Enable both receiver and transmitter. */ - usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) -} USART_Enable_TypeDef; - -/** Oversampling selection, used for asynchronous operation. */ -typedef enum { - usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ - usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ - usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ - usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ -} USART_OVS_TypeDef; - -/** Parity selection, mainly used for asynchronous operation. */ -typedef enum { - usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ - usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ - usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ -} USART_Parity_TypeDef; - -/** Stop bits selection, used for asynchronous operation. */ -typedef enum { - usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ - usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ - usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ - usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ -} USART_Stopbits_TypeDef; - -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) -/** Hardware Flow Control Selection. */ -typedef enum { - /** No hardware flow control. */ - usartHwFlowControlNone = 0, - /** CTS signal is enabled for TX flow control. */ - usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, - /** RTS signal is enabled for RX flow control. */ - usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, - /** CTS and RTS signals are enabled for TX and RX flow control. */ - usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, -} USART_HwFlowControl_TypeDef; - -#elif defined(USART_CTRLX_CTSEN) -/** Hardware Flow Control Selection. */ -typedef enum { - /** No hardware flow control. */ - usartHwFlowControlNone = 0, - /** CTS signal is enabled for TX flow control. */ - usartHwFlowControlCts, - /** RTS signal is enabled for RX flow control. */ - usartHwFlowControlRts, - /** CTS and RTS signals are enabled for TX and RX flow control. */ - usartHwFlowControlCtsAndRts -} USART_HwFlowControl_TypeDef; -#endif - -/** Clock polarity/phase mode. */ -typedef enum { - /** Clock idle low, sample on rising edge. */ - usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, - - /** Clock idle low, sample on falling edge. */ - usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, - - /** Clock idle high, sample on falling edge. */ - usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, - - /** Clock idle high, sample on rising edge. */ - usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING -} USART_ClockMode_TypeDef; - -/** Pulse width selection for IrDA mode. */ -typedef enum { - /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ - usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, - - /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ - usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, - - /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ - usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, - - /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ - usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR -} USART_IrDAPw_Typedef; - -/** PRS Channel type */ -typedef uint8_t USART_PRS_Channel_t; - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** Deprecated PRS channel selector value. - * New code should use an integer instead. */ -#define usartIrDAPrsCh0 0U -#define usartIrDAPrsCh1 1U -#define usartIrDAPrsCh2 2U -#define usartIrDAPrsCh3 3U -#define usartIrDAPrsCh4 4U -#define usartIrDAPrsCh5 5U -#define usartIrDAPrsCh6 6U -#define usartIrDAPrsCh7 7U -#define usartPrsRxCh0 0U -#define usartPrsRxCh1 1U -#define usartPrsRxCh2 2U -#define usartPrsRxCh3 3U -#define usartPrsRxCh4 4U -#define usartPrsRxCh5 5U -#define usartPrsRxCh6 6U -#define usartPrsRxCh7 7U -#define usartPrsRxCh8 8U -#define usartPrsRxCh9 9U -#define usartPrsRxCh10 10U -#define usartPrsRxCh11 11U -#define usartPrsTriggerCh0 0U -#define usartPrsTriggerCh1 1U -#define usartPrsTriggerCh2 2U -#define usartPrsTriggerCh3 3U -#define usartPrsTriggerCh4 4U -#define usartPrsTriggerCh5 5U -#define usartPrsTriggerCh6 6U -#define usartPrsTriggerCh7 7U -/** @endcond */ - -#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) -/** I2S format selection. */ -typedef enum { - usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ - usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ - usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ - usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ - usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ - usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ - usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ - usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ -} USART_I2sFormat_TypeDef; - -/** I2S frame data justify. */ -typedef enum { - usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ - usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ -} USART_I2sJustify_TypeDef; - -#elif defined(_USART_I2SCTRL_MASK) -/** I2S format selection. */ -typedef enum { - usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ - usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ - usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ - usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ - usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ - usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ - usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ - usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ -} USART_I2sFormat_TypeDef; - -/** I2S frame data justify. */ -typedef enum { - usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ - usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ -} USART_I2sJustify_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Asynchronous mode initialization structure. */ -typedef struct { - /** Specifies whether TX and/or RX is enabled when initialization is completed. */ - USART_Enable_TypeDef enable; - - /** - * USART/UART reference clock assumed when configuring baud rate setup. - * Set to 0 to use the currently configured reference clock. - */ - uint32_t refFreq; - - /** Desired baud rate. */ - uint32_t baudrate; - - /** Oversampling used. */ - USART_OVS_TypeDef oversampling; - - /** Number of data bits in frame. Notice that UART modules only support 8 or - * 9 data bits. */ - USART_Databits_TypeDef databits; - - /** Parity mode to use. */ - USART_Parity_TypeDef parity; - - /** Number of stop bits to use. */ - USART_Stopbits_TypeDef stopbits; - -#if !defined(_EFM32_GECKO_FAMILY) - /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ - bool mvdis; - - /** Enable USART Rx via PRS. */ - bool prsRxEnable; - - /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ - USART_PRS_Channel_t prsRxCh; -#endif - - /** Auto CS enabling. */ - bool autoCsEnable; - - /** Enable CS invert. By default, chip select is active low. - * Set to true to make chip select active high. */ - bool csInv; - -#if (_SILICON_LABS_32B_SERIES > 0) - /** Auto CS hold time in baud cycles. */ - uint8_t autoCsHold; - - /** Auto CS setup time in baud cycles. */ - uint8_t autoCsSetup; - - /** Hardware flow control mode. */ - USART_HwFlowControl_TypeDef hwFlowControl; -#endif -} USART_InitAsync_TypeDef; - -/** USART PRS trigger enable. */ -typedef struct { -#if defined(USART_TRIGCTRL_AUTOTXTEN) - /** Enable AUTOTX. */ - bool autoTxTriggerEnable; -#endif - /** Trigger receive via PRS channel. */ - bool rxTriggerEnable; - /** Trigger transmit via PRS channel. */ - bool txTriggerEnable; - /** PRS channel to be used to trigger auto transmission. */ - USART_PRS_Channel_t prsTriggerChannel; -} USART_PrsTriggerInit_TypeDef; - -/** Default configuration for USART asynchronous initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Async struct for the EFM32G device */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Auto CS functionality enable/disable switch. */ \ - false, /* No CS invert. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Async struct for Series 0 devices */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch. */ \ - false, /* No CS invert. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Async struct for Series 1 and Series 2 devices */ -#define USART_INITASYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartNoParity, /* No parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles. */ \ - 0, /* Auto CS Setup cycles. */ \ - usartHwFlowControlNone /* No HW flow control. */ \ - } -#endif - -/** Default configuration for USART PRS triggering structure. */ -#if defined(USART_TRIGCTRL_AUTOTXTEN) -#define USART_INITPRSTRIGGER_DEFAULT \ - { \ - false, /* Do not enable autoTX triggering. */ \ - false, /* Do not enable receive triggering. */ \ - false, /* Do not enable transmit triggering. */ \ - 0 /* Set default channel to zero. */ \ - } -#else -#define USART_INITPRSTRIGGER_DEFAULT \ - { \ - false, /* Do not enable receive triggering. */ \ - false, /* Do not enable transmit triggering. */ \ - 0 /* Set default channel to zero. */ \ - } -#endif - -/** Synchronous mode initialization structure. */ -typedef struct { - /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ - USART_Enable_TypeDef enable; - - /** - * USART/UART reference clock assumed when configuring baud rate setup. - * Set to 0 to use the currently configured reference clock. - */ - uint32_t refFreq; - - /** Desired baud rate. */ - uint32_t baudrate; - - /** Number of data bits in frame. */ - USART_Databits_TypeDef databits; - - /** Select if to operate in master or slave mode. */ - bool master; - - /** Select if to send most or least significant bit first. */ - bool msbf; - - /** Clock polarity/phase mode. */ - USART_ClockMode_TypeDef clockMode; - -#if !defined(_EFM32_GECKO_FAMILY) - /** Enable USART Rx via PRS. */ - bool prsRxEnable; - - /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ - USART_PRS_Channel_t prsRxCh; -#endif - -#if defined(USART_TRIGCTRL_AUTOTXTEN) - /** Enable AUTOTX mode. Transmits as long as RX is not full. - * Generates underflows if TX is empty. */ - bool autoTx; -#endif - - /** Auto CS enabling */ - bool autoCsEnable; - - /** Enable CS invert. By default, chip select is active low. - * Set to true to make chip select active high. */ - bool csInv; - -#if defined(_USART_TIMING_CSHOLD_MASK) - /** Auto CS hold time in baud cycles */ - uint8_t autoCsHold; - - /** Auto CS setup time in baud cycles */ - uint8_t autoCsSetup; -#endif -} USART_InitSync_TypeDef; - -/** Default configuration for USART sync initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Sync configuration for EFM32G devices. */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 data bits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Sync configuration for series 0 devices. */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 data bits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Sync configuration for series 2 devices */ -#define USART_INITSYNC_DEFAULT \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits8, /* 8 databits. */ \ - true, /* Master mode. */ \ - false, /* Send least significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode. */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles. */ \ - 0 /* Auto CS Setup cycles. */ \ - } -#endif - -/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ -typedef struct { - /** General Asynchronous initialization structure. */ - USART_InitAsync_TypeDef async; - - /** Set to invert Rx signal before IrDA demodulator. */ - bool irRxInv; - - /** Set to enable filter on IrDA demodulator. */ - bool irFilt; - - /** Configure the pulse width generated by the IrDA modulator as a fraction - * of the configured USART bit period. */ - USART_IrDAPw_Typedef irPw; - -#if defined(USART_IRCTRL_IRPRSEN) - /** Enable the PRS channel selected by irPrsSel as input to IrDA module - * instead of TX. */ - bool irPrsEn; - - /** PRS can be used as input to the pulse modulator instead of TX. - * This value selects the channel to use. */ - USART_PRS_Channel_t irPrsSel; -#endif -} USART_InitIrDA_TypeDef; - -/** Default configuration for IrDA mode initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART IrDA struct for the EFM32G device */ -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART IrDA struct for Series 0 devices */ -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART IrDA struct for Series 1 and Series 2 devices */ -#if defined(USART_IRCTRL_IRPRSEN) -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0, /* Auto CS Setup cycles */ \ - usartHwFlowControlNone /* No HW flow control */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ - false, /* Routing to PRS is disabled. */ \ - 0 /* PRS channel 0. */ \ - } -#else -#define USART_INITIRDA_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 115200, /* 115200 bits/s. */ \ - usartOVS16, /* 16x oversampling. */ \ - usartDatabits8, /* 8 data bits. */ \ - usartEvenParity, /* Even parity. */ \ - usartStopbits1, /* 1 stop bit. */ \ - false, /* Do not disable majority vote. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* Auto CS functionality enable/disable switch */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0, /* Auto CS Setup cycles */ \ - usartHwFlowControlNone /* No HW flow control */ \ - }, \ - false, /* Rx invert disabled. */ \ - false, /* Filtering disabled. */ \ - usartIrDAPwTHREE /* Pulse width is set to ONE. */ \ - } -#endif -#endif - -#if defined(_USART_I2SCTRL_MASK) -/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ -typedef struct { - /** General Synchronous initialization structure. */ - USART_InitSync_TypeDef sync; - - /** I2S mode. */ - USART_I2sFormat_TypeDef format; - - /** Delay on I2S data. Set to add a one-cycle delay between a transition - * on the word-clock and the start of the I2S word. - * Should be set for standard I2S format. */ - bool delay; - - /** Separate DMA Request For Left/Right Data. */ - bool dmaSplit; - - /** Justification of I2S data within the frame. */ - USART_I2sJustify_TypeDef justify; - - /** Stereo or Mono, set to true for mono. */ - bool mono; -} USART_InitI2s_TypeDef; - -/** Default configuration for I2S mode initialization structure. */ -#if defined(_EFM32_GECKO_FAMILY) -/* Default USART Sync configuration for EFM32G devices. */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Master mode. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#elif defined(_SILICON_LABS_32B_SERIES_0) -/* Default USART Sync configuration for series 0 devices. */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnable, /* Enable RX/TX when initialization is complete. */ \ - 0, /* Use current configured reference clock for configuring baud rate. */ \ - 1000000, /* 1 Mbits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Master mode. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Not USART PRS input mode. */ \ - 0, /* PRS channel 0. */ \ - false, /* No AUTOTX mode. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#elif (_SILICON_LABS_32B_SERIES > 0) -/* Default USART Sync configuration for series 2 devices */ -#define USART_INITI2S_DEFAULT \ - { \ - { \ - usartEnableTx, /* Enable TX when init completed. */ \ - 0, /* Use current configured reference clock for configuring baudrate. */ \ - 1000000, /* Baudrate 1M bits/s. */ \ - usartDatabits16, /* 16 databits. */ \ - true, /* Operate as I2S master. */ \ - true, /* Most significant bit first. */ \ - usartClockMode0, /* Clock idle low, sample on rising edge. */ \ - false, /* Don't enable USARTRx via PRS. */ \ - usartPrsRxCh0, /* PRS channel selection (dummy). */ \ - false, /* Disable AUTOTX mode. */ \ - false, /* No AUTOCS mode */ \ - false, /* No CS invert. */ \ - 0, /* Auto CS Hold cycles */ \ - 0 /* Auto CS Setup cycles */ \ - }, \ - usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ - true, /* Delay on I2S data. */ \ - false, /* No DMA split. */ \ - usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ - false /* Stereo mode. */ \ - } -#endif -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void USART_BaudrateAsyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate, - USART_OVS_TypeDef ovs); -uint32_t USART_BaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - bool syncmode, - USART_OVS_TypeDef ovs); -uint32_t USART_BaudrateGet(USART_TypeDef *usart); -void USART_BaudrateSyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate); -void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); - -void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); -void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); -void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); - -#if defined(_USART_I2SCTRL_MASK) -void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); -#endif -void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); - -/***************************************************************************//** - * @brief - * Clear one or more pending USART interrupts. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * Pending USART/UART interrupt source(s) to clear. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) -{ -#if defined (USART_HAS_SET_CLEAR) - usart->IF_CLR = flags; -#else - usart->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more USART interrupts. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to disable. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) -{ - usart->IEN &= ~flags; -} - -/***************************************************************************//** - * @brief - * Enable one or more USART interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * USART_IntClear() prior to enabling the interrupt. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to enable. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) -{ - usart->IEN |= flags; -} - -/***************************************************************************//** - * @brief - * Get pending USART interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @return - * USART/UART interrupt source(s) pending. Returns one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) -{ - return usart->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending USART interrupt flags. - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @note - * Interrupt flags are not cleared by the use of this function. - * - * @return - * Pending and enabled USART interrupt sources. - * The return value is the bitwise AND combination of - * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn - * register (USARTx_IEN_nnn) and - * - the OR combination of valid interrupt flags of the USART module - * (USARTx_IF_nnn). - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) -{ - uint32_t ien; - - /* Store USARTx->IEN in temporary variable in order to define explicit order - * of volatile accesses. */ - ien = usart->IEN; - - /* Bitwise AND of pending and enabled interrupts. */ - return usart->IF & ien; -} - -/***************************************************************************//** - * @brief - * Set one or more pending USART interrupts from SW. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @param[in] flags - * USART/UART interrupt source(s) to set to pending. Use one or more valid - * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. - ******************************************************************************/ -__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) -{ -#if defined (USART_HAS_SET_CLEAR) - usart->IF_SET = flags; -#else - usart->IFS = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get USART STATUS register. - * - * @param[in] usart - * Pointer to the USART/UART peripheral register block. - * - * @return - * STATUS register value. - * - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) -{ - return usart->STATUS; -} - -void USART_Reset(USART_TypeDef *usart); -uint8_t USART_Rx(USART_TypeDef *usart); -uint16_t USART_RxDouble(USART_TypeDef *usart); -uint32_t USART_RxDoubleExt(USART_TypeDef *usart); -uint16_t USART_RxExt(USART_TypeDef *usart); - -/***************************************************************************//** - * @brief - * Receive one 4-8 bit frame, (or part of 10-16 bit frame). - * - * @details - * This function is used to quickly receive one 4-8 bits frame by reading the - * RXDATA register directly, without checking the STATUS register for the - * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, - * i.e., waiting is superfluous, in order to quickly read the received data. - * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. - * - * @note - * Because this function does not check whether the RXDATA register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a - * better choice if the validity of the RXDATA register is not certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) -{ - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Receive two 4-8 bit frames, or one 10-16 bit frame. - * - * @details - * This function is used to quickly receive one 10-16 bits frame or two 4-8 - * bit frames by reading the RXDOUBLE register directly, without checking - * the STATUS register for the RXDATAV flag. This can be useful from the - * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to - * quickly read the received data. - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() - * for reception of two 9 bit frames. - * - * @note - * Because this function does not check whether the RXDOUBLE register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is - * normally a better choice if the validity of the RXDOUBLE register is not - * certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) -{ - return (uint16_t)usart->RXDOUBLE; -} - -/***************************************************************************//** - * @brief - * Receive two 4-9 bit frames, or one 10-16 bit frame with extended - * information. - * - * @details - * This function is used to quickly receive one 10-16 bits frame or two 4-9 - * bit frames by reading the RXDOUBLEX register directly, without checking - * the STATUS register for the RXDATAV flag. This can be useful from the - * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to - * quickly read the received data. - * - * @note - * Because this function does not check whether the RXDOUBLEX register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is - * normally a better choice if the validity of the RXDOUBLEX register is not - * certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) -{ - return usart->RXDOUBLEX; -} - -/***************************************************************************//** - * @brief - * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended - * information. - * - * @details - * This function is used to quickly receive one 4-9 bit frame, (or part of - * 10-16 bit frame) with extended information by reading the RXDATAX register - * directly, without checking the STATUS register for the RXDATAV flag. This - * can be useful from the RXDATAV interrupt handler, i.e., waiting is - * superfluous, in order to quickly read the received data. - * - * @note - * Because this function does not check whether the RXDATAX register actually - * holds valid data, it should only be used in situations when it is certain - * that there is valid data, ensured by some external program routine, e.g., - * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally - * a better choice if the validity of the RXDATAX register is not certain. - * - * @note - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of specified frame bit length. - * - * @param[in] usart - * Pointer to USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) -{ - return (uint16_t)usart->RXDATAX; -} - -uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); -void USART_Tx(USART_TypeDef *usart, uint8_t data); -void USART_TxDouble(USART_TypeDef *usart, uint16_t data); -void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); -void USART_TxExt(USART_TypeDef *usart, uint16_t data); - -/** @} (end addtogroup usart) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ -#endif /* EM_USART_H */ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_USART_H +#define EM_USART_H + +#include "em_device.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup usart USART - Synchronous/Asynchronous Serial + * @brief Universal Synchronous/Asynchronous Receiver/Transmitter + * Peripheral API + * @details + * The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) + * is a very flexible serial I/O module. It supports full duplex asynchronous UART + * communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface + * with ISO7816 Smart-Cards, and IrDA devices. + * + * The USART has a wide selection of operating modes, frame formats, and baud rates. + * All features are supported through the API of this module. + * + * Triple buffering and DMA support makes high data-rates possible with minimal + * CPU intervention. It is possible to transmit and receive large frames while + * the MCU remains in EM1 Sleep. + * + * This module does not support DMA configuration. The UARTDRV and SPIDRV drivers + * provide full support for DMA and more. + * + * The following steps are necessary for basic operation: + * + * Clock enable: + * @include em_usart_clock_enable.c + * + * To initialize the USART for asynchronous operation (e.g., UART): + * @include em_usart_init_async.c + * + * To initialize the USART for synchronous operation (e.g., SPI): + * @include em_usart_init_sync.c + * + * After pins are assigned for the application/board, enable pins at the + * desired location. Available locations can be obtained from the Pin Definitions + * section in the data sheet. + * @if DOXYDOC_P1_DEVICE + * @include em_usart_route_p1.c + * @note UART hardware flow control is not directly supported in hardware on + * _SILICON_LABS_32B_SERIES_0 parts. + * @endif + * @if DOXYDOC_P2_DEVICE + * @include em_usart_route_p2.c + * @endif + * @note UARTDRV supports all types of UART flow control. Software assisted + * hardware flow control is available for parts without true UART hardware + * flow control. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Databit selection. */ +typedef enum { + usartDatabits4 = USART_FRAME_DATABITS_FOUR, /**< 4 data bits (not available for UART). */ + usartDatabits5 = USART_FRAME_DATABITS_FIVE, /**< 5 data bits (not available for UART). */ + usartDatabits6 = USART_FRAME_DATABITS_SIX, /**< 6 data bits (not available for UART). */ + usartDatabits7 = USART_FRAME_DATABITS_SEVEN, /**< 7 data bits (not available for UART). */ + usartDatabits8 = USART_FRAME_DATABITS_EIGHT, /**< 8 data bits. */ + usartDatabits9 = USART_FRAME_DATABITS_NINE, /**< 9 data bits. */ + usartDatabits10 = USART_FRAME_DATABITS_TEN, /**< 10 data bits (not available for UART). */ + usartDatabits11 = USART_FRAME_DATABITS_ELEVEN, /**< 11 data bits (not available for UART). */ + usartDatabits12 = USART_FRAME_DATABITS_TWELVE, /**< 12 data bits (not available for UART). */ + usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, /**< 13 data bits (not available for UART). */ + usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, /**< 14 data bits (not available for UART). */ + usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN, /**< 15 data bits (not available for UART). */ + usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN /**< 16 data bits (not available for UART). */ +} USART_Databits_TypeDef; + +/** Enable selection. */ +typedef enum { + /** Disable both receiver and transmitter. */ + usartDisable = 0x0, + + /** Enable receiver only, transmitter disabled. */ + usartEnableRx = USART_CMD_RXEN, + + /** Enable transmitter only, receiver disabled. */ + usartEnableTx = USART_CMD_TXEN, + + /** Enable both receiver and transmitter. */ + usartEnable = (USART_CMD_RXEN | USART_CMD_TXEN) +} USART_Enable_TypeDef; + +/** Oversampling selection, used for asynchronous operation. */ +typedef enum { + usartOVS16 = USART_CTRL_OVS_X16, /**< 16x oversampling (normal). */ + usartOVS8 = USART_CTRL_OVS_X8, /**< 8x oversampling. */ + usartOVS6 = USART_CTRL_OVS_X6, /**< 6x oversampling. */ + usartOVS4 = USART_CTRL_OVS_X4 /**< 4x oversampling. */ +} USART_OVS_TypeDef; + +/** Parity selection, mainly used for asynchronous operation. */ +typedef enum { + usartNoParity = USART_FRAME_PARITY_NONE, /**< No parity. */ + usartEvenParity = USART_FRAME_PARITY_EVEN, /**< Even parity. */ + usartOddParity = USART_FRAME_PARITY_ODD /**< Odd parity. */ +} USART_Parity_TypeDef; + +/** Stop bits selection, used for asynchronous operation. */ +typedef enum { + usartStopbits0p5 = USART_FRAME_STOPBITS_HALF, /**< 0.5 stop bits. */ + usartStopbits1 = USART_FRAME_STOPBITS_ONE, /**< 1 stop bits. */ + usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, /**< 1.5 stop bits. */ + usartStopbits2 = USART_FRAME_STOPBITS_TWO /**< 2 stop bits. */ +} USART_Stopbits_TypeDef; + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts = USART_ROUTEPEN_CTSPEN, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts = USART_ROUTEPEN_RTSPEN, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts = USART_ROUTEPEN_CTSPEN | USART_ROUTEPEN_RTSPEN, +} USART_HwFlowControl_TypeDef; + +#elif defined(USART_CTRLX_CTSEN) +/** Hardware Flow Control Selection. */ +typedef enum { + /** No hardware flow control. */ + usartHwFlowControlNone = 0, + /** CTS signal is enabled for TX flow control. */ + usartHwFlowControlCts, + /** RTS signal is enabled for RX flow control. */ + usartHwFlowControlRts, + /** CTS and RTS signals are enabled for TX and RX flow control. */ + usartHwFlowControlCtsAndRts +} USART_HwFlowControl_TypeDef; +#endif + +/** Clock polarity/phase mode. */ +typedef enum { + /** Clock idle low, sample on rising edge. */ + usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle low, sample on falling edge. */ + usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING, + + /** Clock idle high, sample on falling edge. */ + usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING, + + /** Clock idle high, sample on rising edge. */ + usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING +} USART_ClockMode_TypeDef; + +/** Pulse width selection for IrDA mode. */ +typedef enum { + /** IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1 */ + usartIrDAPwONE = USART_IRCTRL_IRPW_ONE, + + /** IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1 */ + usartIrDAPwTWO = USART_IRCTRL_IRPW_TWO, + + /** IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1 */ + usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE, + + /** IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1 */ + usartIrDAPwFOUR = USART_IRCTRL_IRPW_FOUR +} USART_IrDAPw_Typedef; + +/** PRS Channel type */ +typedef uint8_t USART_PRS_Channel_t; + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/** Deprecated PRS channel selector value. + * New code should use an integer instead. */ +#define usartIrDAPrsCh0 0U +#define usartIrDAPrsCh1 1U +#define usartIrDAPrsCh2 2U +#define usartIrDAPrsCh3 3U +#define usartIrDAPrsCh4 4U +#define usartIrDAPrsCh5 5U +#define usartIrDAPrsCh6 6U +#define usartIrDAPrsCh7 7U +#define usartPrsRxCh0 0U +#define usartPrsRxCh1 1U +#define usartPrsRxCh2 2U +#define usartPrsRxCh3 3U +#define usartPrsRxCh4 4U +#define usartPrsRxCh5 5U +#define usartPrsRxCh6 6U +#define usartPrsRxCh7 7U +#define usartPrsRxCh8 8U +#define usartPrsRxCh9 9U +#define usartPrsRxCh10 10U +#define usartPrsRxCh11 11U +#define usartPrsTriggerCh0 0U +#define usartPrsTriggerCh1 1U +#define usartPrsTriggerCh2 2U +#define usartPrsTriggerCh3 3U +#define usartPrsTriggerCh4 4U +#define usartPrsTriggerCh5 5U +#define usartPrsTriggerCh6 6U +#define usartPrsTriggerCh7 7U +/** @endcond */ + +#if defined(_USART_I2SCTRL_MASK) && defined(USART_I2SCTRL_I2SEN) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_I2SFORMAT_W32D32, /**< 32-bit word, 32-bit data */ + usartI2sFormatW32D24M = USART_I2SCTRL_I2SFORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked */ + usartI2sFormatW32D24 = USART_I2SCTRL_I2SFORMAT_W32D24, /**< 32-bit word, 24-bit data */ + usartI2sFormatW32D16 = USART_I2SCTRL_I2SFORMAT_W32D16, /**< 32-bit word, 16-bit data */ + usartI2sFormatW32D8 = USART_I2SCTRL_I2SFORMAT_W32D8, /**< 32-bit word, 8-bit data */ + usartI2sFormatW16D16 = USART_I2SCTRL_I2SFORMAT_W16D16, /**< 16-bit word, 16-bit data */ + usartI2sFormatW16D8 = USART_I2SCTRL_I2SFORMAT_W16D8, /**< 16-bit word, 8-bit data */ + usartI2sFormatW8D8 = USART_I2SCTRL_I2SFORMAT_W8D8 /**< 8-bit word, 8-bit data */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_I2SJUSTIFY_LEFT, /**< Data is left-justified within the frame */ + usartI2sJustifyRight = USART_I2SCTRL_I2SJUSTIFY_RIGHT /**< Data is right-justified within the frame */ +} USART_I2sJustify_TypeDef; + +#elif defined(_USART_I2SCTRL_MASK) +/** I2S format selection. */ +typedef enum { + usartI2sFormatW32D32 = USART_I2SCTRL_FORMAT_W32D32, /**< 32-bit word, 32-bit data. */ + usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M, /**< 32-bit word, 32-bit data with 8 lsb masked. */ + usartI2sFormatW32D24 = USART_I2SCTRL_FORMAT_W32D24, /**< 32-bit word, 24-bit data. */ + usartI2sFormatW32D16 = USART_I2SCTRL_FORMAT_W32D16, /**< 32-bit word, 16-bit data. */ + usartI2sFormatW32D8 = USART_I2SCTRL_FORMAT_W32D8, /**< 32-bit word, 8-bit data. */ + usartI2sFormatW16D16 = USART_I2SCTRL_FORMAT_W16D16, /**< 16-bit word, 16-bit data. */ + usartI2sFormatW16D8 = USART_I2SCTRL_FORMAT_W16D8, /**< 16-bit word, 8-bit data. */ + usartI2sFormatW8D8 = USART_I2SCTRL_FORMAT_W8D8 /**< 8-bit word, 8-bit data. */ +} USART_I2sFormat_TypeDef; + +/** I2S frame data justify. */ +typedef enum { + usartI2sJustifyLeft = USART_I2SCTRL_JUSTIFY_LEFT, /**< Data is left-justified within the frame. */ + usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT /**< Data is right-justified within the frame. */ +} USART_I2sJustify_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Asynchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX is enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Oversampling used. */ + USART_OVS_TypeDef oversampling; + + /** Number of data bits in frame. Notice that UART modules only support 8 or + * 9 data bits. */ + USART_Databits_TypeDef databits; + + /** Parity mode to use. */ + USART_Parity_TypeDef parity; + + /** Number of stop bits to use. */ + USART_Stopbits_TypeDef stopbits; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */ + bool mvdis; + + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + + /** Auto CS enabling. */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if (_SILICON_LABS_32B_SERIES > 0) + /** Auto CS hold time in baud cycles. */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles. */ + uint8_t autoCsSetup; + + /** Hardware flow control mode. */ + USART_HwFlowControl_TypeDef hwFlowControl; +#endif +} USART_InitAsync_TypeDef; + +/** USART PRS trigger enable. */ +typedef struct { +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX. */ + bool autoTxTriggerEnable; +#endif + /** Trigger receive via PRS channel. */ + bool rxTriggerEnable; + /** Trigger transmit via PRS channel. */ + bool txTriggerEnable; + /** PRS channel to be used to trigger auto transmission. */ + USART_PRS_Channel_t prsTriggerChannel; +} USART_PrsTriggerInit_TypeDef; + +/** Default configuration for USART asynchronous initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Async struct for the EFM32G device */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Async struct for Series 0 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Async struct for Series 1 and Series 2 devices */ +#define USART_INITASYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartNoParity, /* No parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0, /* Auto CS Setup cycles. */ \ + usartHwFlowControlNone /* No HW flow control. */ \ + } +#endif + +/** Default configuration for USART PRS triggering structure. */ +#if defined(USART_TRIGCTRL_AUTOTXTEN) +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable autoTX triggering. */ \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#else +#define USART_INITPRSTRIGGER_DEFAULT \ + { \ + false, /* Do not enable receive triggering. */ \ + false, /* Do not enable transmit triggering. */ \ + 0 /* Set default channel to zero. */ \ + } +#endif + +/** Synchronous mode initialization structure. */ +typedef struct { + /** Specifies whether TX and/or RX shall be enabled when initialization is completed. */ + USART_Enable_TypeDef enable; + + /** + * USART/UART reference clock assumed when configuring baud rate setup. + * Set to 0 to use the currently configured reference clock. + */ + uint32_t refFreq; + + /** Desired baud rate. */ + uint32_t baudrate; + + /** Number of data bits in frame. */ + USART_Databits_TypeDef databits; + + /** Select if to operate in master or slave mode. */ + bool master; + + /** Select if to send most or least significant bit first. */ + bool msbf; + + /** Clock polarity/phase mode. */ + USART_ClockMode_TypeDef clockMode; + +#if !defined(_EFM32_GECKO_FAMILY) + /** Enable USART Rx via PRS. */ + bool prsRxEnable; + + /** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */ + USART_PRS_Channel_t prsRxCh; +#endif + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + /** Enable AUTOTX mode. Transmits as long as RX is not full. + * Generates underflows if TX is empty. */ + bool autoTx; +#endif + + /** Auto CS enabling */ + bool autoCsEnable; + + /** Enable CS invert. By default, chip select is active low. + * Set to true to make chip select active high. */ + bool csInv; + +#if defined(_USART_TIMING_CSHOLD_MASK) + /** Auto CS hold time in baud cycles */ + uint8_t autoCsHold; + + /** Auto CS setup time in baud cycles */ + uint8_t autoCsSetup; +#endif +} USART_InitSync_TypeDef; + +/** Default configuration for USART sync initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 data bits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITSYNC_DEFAULT \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits8, /* 8 databits. */ \ + true, /* Master mode. */ \ + false, /* Send least significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode. */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles. */ \ + 0 /* Auto CS Setup cycles. */ \ + } +#endif + +/** IrDA mode initialization structure. Inherited from asynchronous mode initialization structure. */ +typedef struct { + /** General Asynchronous initialization structure. */ + USART_InitAsync_TypeDef async; + + /** Set to invert Rx signal before IrDA demodulator. */ + bool irRxInv; + + /** Set to enable filter on IrDA demodulator. */ + bool irFilt; + + /** Configure the pulse width generated by the IrDA modulator as a fraction + * of the configured USART bit period. */ + USART_IrDAPw_Typedef irPw; + +#if defined(USART_IRCTRL_IRPRSEN) + /** Enable the PRS channel selected by irPrsSel as input to IrDA module + * instead of TX. */ + bool irPrsEn; + + /** PRS can be used as input to the pulse modulator instead of TX. + * This value selects the channel to use. */ + USART_PRS_Channel_t irPrsSel; +#endif +} USART_InitIrDA_TypeDef; + +/** Default configuration for IrDA mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART IrDA struct for the EFM32G device */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART IrDA struct for Series 0 devices */ +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART IrDA struct for Series 1 and Series 2 devices */ +#if defined(USART_IRCTRL_IRPRSEN) +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \ + false, /* Routing to PRS is disabled. */ \ + 0 /* PRS channel 0. */ \ + } +#else +#define USART_INITIRDA_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 115200, /* 115200 bits/s. */ \ + usartOVS16, /* 16x oversampling. */ \ + usartDatabits8, /* 8 data bits. */ \ + usartEvenParity, /* Even parity. */ \ + usartStopbits1, /* 1 stop bit. */ \ + false, /* Do not disable majority vote. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* Auto CS functionality enable/disable switch */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0, /* Auto CS Setup cycles */ \ + usartHwFlowControlNone /* No HW flow control */ \ + }, \ + false, /* Rx invert disabled. */ \ + false, /* Filtering disabled. */ \ + usartIrDAPwTHREE /* Pulse width is set to ONE. */ \ + } +#endif +#endif + +#if defined(_USART_I2SCTRL_MASK) +/** I2S mode initialization structure. Inherited from synchronous mode initialization structure. */ +typedef struct { + /** General Synchronous initialization structure. */ + USART_InitSync_TypeDef sync; + + /** I2S mode. */ + USART_I2sFormat_TypeDef format; + + /** Delay on I2S data. Set to add a one-cycle delay between a transition + * on the word-clock and the start of the I2S word. + * Should be set for standard I2S format. */ + bool delay; + + /** Separate DMA Request For Left/Right Data. */ + bool dmaSplit; + + /** Justification of I2S data within the frame. */ + USART_I2sJustify_TypeDef justify; + + /** Stereo or Mono, set to true for mono. */ + bool mono; +} USART_InitI2s_TypeDef; + +/** Default configuration for I2S mode initialization structure. */ +#if defined(_EFM32_GECKO_FAMILY) +/* Default USART Sync configuration for EFM32G devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif defined(_SILICON_LABS_32B_SERIES_0) +/* Default USART Sync configuration for series 0 devices. */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnable, /* Enable RX/TX when initialization is complete. */ \ + 0, /* Use current configured reference clock for configuring baud rate. */ \ + 1000000, /* 1 Mbits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Master mode. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Not USART PRS input mode. */ \ + 0, /* PRS channel 0. */ \ + false, /* No AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#elif (_SILICON_LABS_32B_SERIES > 0) +/* Default USART Sync configuration for series 2 devices */ +#define USART_INITI2S_DEFAULT \ + { \ + { \ + usartEnableTx, /* Enable TX when init completed. */ \ + 0, /* Use current configured reference clock for configuring baudrate. */ \ + 1000000, /* Baudrate 1M bits/s. */ \ + usartDatabits16, /* 16 databits. */ \ + true, /* Operate as I2S master. */ \ + true, /* Most significant bit first. */ \ + usartClockMode0, /* Clock idle low, sample on rising edge. */ \ + false, /* Don't enable USARTRx via PRS. */ \ + usartPrsRxCh0, /* PRS channel selection (dummy). */ \ + false, /* Disable AUTOTX mode. */ \ + false, /* No AUTOCS mode */ \ + false, /* No CS invert. */ \ + 0, /* Auto CS Hold cycles */ \ + 0 /* Auto CS Setup cycles */ \ + }, \ + usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \ + true, /* Delay on I2S data. */ \ + false, /* No DMA split. */ \ + usartI2sJustifyLeft,/* Data is left-justified within the frame */ \ + false /* Stereo mode. */ \ + } +#endif +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs); +uint32_t USART_BaudrateGet(USART_TypeDef *usart); +void USART_BaudrateSyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate); +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable); + +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init); +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init); +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init); + +#if defined(_USART_I2SCTRL_MASK) +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init); +#endif +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init); + +/***************************************************************************//** + * @brief + * Clear one or more pending USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * Pending USART/UART interrupt source(s) to clear. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_CLR = flags; +#else + usart->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more USART interrupts. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to disable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN &= ~flags; +} + +/***************************************************************************//** + * @brief + * Enable one or more USART interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * USART_IntClear() prior to enabling the interrupt. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to enable. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags) +{ + usart->IEN |= flags; +} + +/***************************************************************************//** + * @brief + * Get pending USART interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * USART/UART interrupt source(s) pending. Returns one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart) +{ + return usart->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending USART interrupt flags. + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @note + * Interrupt flags are not cleared by the use of this function. + * + * @return + * Pending and enabled USART interrupt sources. + * The return value is the bitwise AND combination of + * - the OR combination of enabled interrupt sources in USARTx_IEN_nnn + * register (USARTx_IEN_nnn) and + * - the OR combination of valid interrupt flags of the USART module + * (USARTx_IF_nnn). + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart) +{ + uint32_t ien; + + /* Store USARTx->IEN in temporary variable in order to define explicit order + * of volatile accesses. */ + ien = usart->IEN; + + /* Bitwise AND of pending and enabled interrupts. */ + return usart->IF & ien; +} + +/***************************************************************************//** + * @brief + * Set one or more pending USART interrupts from SW. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @param[in] flags + * USART/UART interrupt source(s) to set to pending. Use one or more valid + * interrupt flags for the USART module (USART_IF_nnn) OR'ed together. + ******************************************************************************/ +__STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags) +{ +#if defined (USART_HAS_SET_CLEAR) + usart->IF_SET = flags; +#else + usart->IFS = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get USART STATUS register. + * + * @param[in] usart + * Pointer to the USART/UART peripheral register block. + * + * @return + * STATUS register value. + * + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart) +{ + return usart->STATUS; +} + +void USART_Reset(USART_TypeDef *usart); +uint8_t USART_Rx(USART_TypeDef *usart); +uint16_t USART_RxDouble(USART_TypeDef *usart); +uint32_t USART_RxDoubleExt(USART_TypeDef *usart); +uint16_t USART_RxExt(USART_TypeDef *usart); + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is used to quickly receive one 4-8 bits frame by reading the + * RXDATA register directly, without checking the STATUS register for the + * RXDATAV flag. This can be useful from the RXDATAV interrupt handler, + * i.e., waiting is superfluous, in order to quickly read the received data. + * Please refer to @ref USART_RxDataXGet() for reception of 9 bit frames. + * + * @note + * Because this function does not check whether the RXDATA register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_Rx() is normally a + * better choice if the validity of the RXDATA register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart) +{ + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames, or one 10-16 bit frame. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-8 + * bit frames by reading the RXDOUBLE register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. Please refer to @ref USART_RxDoubleXGet() + * for reception of two 9 bit frames. + * + * @note + * Because this function does not check whether the RXDOUBLE register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDouble() is + * normally a better choice if the validity of the RXDOUBLE register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is used to quickly receive one 10-16 bits frame or two 4-9 + * bit frames by reading the RXDOUBLEX register directly, without checking + * the STATUS register for the RXDATAV flag. This can be useful from the + * RXDATAV interrupt handler, i.e., waiting is superfluous, in order to + * quickly read the received data. + * + * @note + * Because this function does not check whether the RXDOUBLEX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxDoubleExt() is + * normally a better choice if the validity of the RXDOUBLEX register is not + * certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart) +{ + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is used to quickly receive one 4-9 bit frame, (or part of + * 10-16 bit frame) with extended information by reading the RXDATAX register + * directly, without checking the STATUS register for the RXDATAV flag. This + * can be useful from the RXDATAV interrupt handler, i.e., waiting is + * superfluous, in order to quickly read the received data. + * + * @note + * Because this function does not check whether the RXDATAX register actually + * holds valid data, it should only be used in situations when it is certain + * that there is valid data, ensured by some external program routine, e.g., + * when handling an RXDATAV interrupt. The @ref USART_RxExt() is normally + * a better choice if the validity of the RXDATAX register is not certain. + * + * @note + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of specified frame bit length. + * + * @param[in] usart + * Pointer to USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart) +{ + return (uint16_t)usart->RXDATAX; +} + +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data); +void USART_Tx(USART_TypeDef *usart, uint8_t data); +void USART_TxDouble(USART_TypeDef *usart, uint16_t data); +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data); +void USART_TxExt(USART_TypeDef *usart, uint16_t data); + +/** @} (end addtogroup usart) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ +#endif /* EM_USART_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h index f44110b..6794f83 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_version.h @@ -1,68 +1,68 @@ -/***************************************************************************//** - * @file - * @brief CMSIS and EMLIB versions - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_VERSION_H -#define EM_VERSION_H - -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup version VERSION - Version Defines - * @brief Version API - * @details - * Macros specifying the EMLIB and CMSIS version. - * @{ - ******************************************************************************/ - -/* *INDENT-OFF* */ -/** Version number of targeted CMSIS package. */ -#define _CMSIS_VERSION 5.8.0 -/* *INDENT-ON* */ - -/** Major version of CMSIS. */ -#define _CMSIS_VERSION_MAJOR 5 - -/** Minor version of CMSIS. */ -#define _CMSIS_VERSION_MINOR 8 - -/** Patch revision of CMSIS. */ -#define _CMSIS_VERSION_PATCH 0 - -/** @} (end addtogroup version) */ - -#ifdef __cplusplus -} -#endif - -#endif /* EM_VERSION_H */ +/***************************************************************************//** + * @file + * @brief CMSIS and EMLIB versions + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_VERSION_H +#define EM_VERSION_H + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup version VERSION - Version Defines + * @brief Version API + * @details + * Macros specifying the EMLIB and CMSIS version. + * @{ + ******************************************************************************/ + +/* *INDENT-OFF* */ +/** Version number of targeted CMSIS package. */ +#define _CMSIS_VERSION 5.8.0 +/* *INDENT-ON* */ + +/** Major version of CMSIS. */ +#define _CMSIS_VERSION_MAJOR 5 + +/** Minor version of CMSIS. */ +#define _CMSIS_VERSION_MINOR 8 + +/** Patch revision of CMSIS. */ +#define _CMSIS_VERSION_PATCH 0 + +/** @} (end addtogroup version) */ + +#ifdef __cplusplus +} +#endif + +#endif /* EM_VERSION_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h index f77281a..3461939 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/em_wdog.h @@ -1,455 +1,455 @@ -/***************************************************************************//** - * @file - * @brief Watchdog (WDOG) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef EM_WDOG_H -#define EM_WDOG_H - -#include "em_device.h" -#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) - -#include -#include "sl_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup wdog - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** Default WDOG instance for deprecated functions. */ -#if !defined(DEFAULT_WDOG) -#if defined(WDOG0) -#define DEFAULT_WDOG WDOG0 -#elif defined(WDOG) -#define DEFAULT_WDOG WDOG -#endif -#endif - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** Watchdog clock selection. */ -#if defined(_WDOG_CTRL_CLKSEL_MASK) -typedef enum { - wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */ - wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */ - wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */ -} WDOG_ClkSel_TypeDef; -#endif - -/** Watchdog period selection. */ -typedef enum { - wdogPeriod_9 = 0x0, /**< 9 clock periods */ - wdogPeriod_17 = 0x1, /**< 17 clock periods */ - wdogPeriod_33 = 0x2, /**< 33 clock periods */ - wdogPeriod_65 = 0x3, /**< 65 clock periods */ - wdogPeriod_129 = 0x4, /**< 129 clock periods */ - wdogPeriod_257 = 0x5, /**< 257 clock periods */ - wdogPeriod_513 = 0x6, /**< 513 clock periods */ - wdogPeriod_1k = 0x7, /**< 1025 clock periods */ - wdogPeriod_2k = 0x8, /**< 2049 clock periods */ - wdogPeriod_4k = 0x9, /**< 4097 clock periods */ - wdogPeriod_8k = 0xA, /**< 8193 clock periods */ - wdogPeriod_16k = 0xB, /**< 16385 clock periods */ - wdogPeriod_32k = 0xC, /**< 32769 clock periods */ - wdogPeriod_64k = 0xD, /**< 65537 clock periods */ - wdogPeriod_128k = 0xE, /**< 131073 clock periods */ - wdogPeriod_256k = 0xF /**< 262145 clock periods */ -} WDOG_PeriodSel_TypeDef; - -#if defined(_WDOG_CTRL_WARNSEL_MASK) \ - || defined(_WDOG_CFG_WARNSEL_MASK) -/** Select Watchdog warning timeout period as percentage of timeout. */ -typedef enum { - wdogWarnDisable = 0, /**< Watchdog warning period is disabled. */ - wdogWarnTime25pct = 1, /**< Watchdog warning period is 25% of the timeout. */ - wdogWarnTime50pct = 2, /**< Watchdog warning period is 50% of the timeout. */ - wdogWarnTime75pct = 3, /**< Watchdog warning period is 75% of the timeout. */ -} WDOG_WarnSel_TypeDef; -#endif - -#if defined(_WDOG_CTRL_WINSEL_MASK) \ - || defined(_WDOG_CFG_WINSEL_MASK) -/** Select Watchdog illegal window limit. */ -typedef enum { - wdogIllegalWindowDisable = 0, /**< Watchdog illegal window disabled. */ - wdogIllegalWindowTime12_5pct = 1, /**< Window timeout is 12.5% of the timeout. */ - wdogIllegalWindowTime25_0pct = 2, /**< Window timeout is 25% of the timeout. */ - wdogIllegalWindowTime37_5pct = 3, /**< Window timeout is 37.5% of the timeout. */ - wdogIllegalWindowTime50_0pct = 4, /**< Window timeout is 50% of the timeout. */ - wdogIllegalWindowTime62_5pct = 5, /**< Window timeout is 62.5% of the timeout. */ - wdogIllegalWindowTime75_0pct = 6, /**< Window timeout is 75% of the timeout. */ - wdogIllegalWindowTime87_5pct = 7, /**< Window timeout is 87.5% of the timeout. */ -} WDOG_WinSel_TypeDef; -#endif - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** Watchdog initialization structure. */ -typedef struct { - /** Enable Watchdog when initialization completed. */ - bool enable; - - /** Counter keeps running during debug halt. */ - bool debugRun; - -#if defined(_WDOG_CTRL_CLRSRC_MASK) \ - || defined(_WDOG_CFG_CLRSRC_MASK) - /** Select WDOG clear source: - * False: Write to the clear bit will clear the WDOG counter - * True: Rising edge on the PRS Source 0 will clear the WDOG counter - * */ - bool clrSrc; -#endif - -#if defined(_WDOG_CFG_EM1RUN_MASK) - /** Counter keeps running when in EM1. Available for series2. */ - bool em1Run; -#endif - - /** Counter keeps running when in EM2. */ - bool em2Run; - - /** Counter keeps running when in EM3. */ - bool em3Run; - - /** Block EMU from entering EM4. */ - bool em4Block; - -#if defined(_WDOG_CFG_MASK) - /** When set, a PRS Source 0 missing event will trigger a WDOG reset. */ - bool prs0MissRstEn; - - /** When set, a PRS Source 1 missing event will trigger a WDOG reset. */ - bool prs1MissRstEn; -#endif - - /** Block SW from disabling LFRCO/LFXO oscillators. */ -#if defined(_WDOG_CTRL_SWOSCBLOCK_MASK) - bool swoscBlock; -#endif - - /** Block SW from modifying the configuration (a reset is needed to reconfigure). */ - bool lock; - - /** Clock source to use for Watchdog. */ -#if defined(_WDOG_CTRL_CLKSEL_MASK) - WDOG_ClkSel_TypeDef clkSel; -#endif - - /** Watchdog timeout period. */ - WDOG_PeriodSel_TypeDef perSel; - -#if defined(_WDOG_CTRL_WARNSEL_MASK) \ - || defined(_WDOG_CFG_WARNSEL_MASK) - /** Select warning time as % of the Watchdog timeout */ - WDOG_WarnSel_TypeDef warnSel; -#endif - -#if defined(_WDOG_CTRL_WINSEL_MASK) \ - || defined(_WDOG_CFG_WINSEL_MASK) - /** Select illegal window time as % of the Watchdog timeout */ - WDOG_WinSel_TypeDef winSel; -#endif - -#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ - || defined(_WDOG_CFG_WDOGRSTDIS_MASK) - /** Disable Watchdog reset output if true */ - bool resetDisable; -#endif -} WDOG_Init_TypeDef; - -/** Suggested default configuration for WDOG initialization structure. */ -#if defined(_WDOG_CFG_MASK) && defined(_WDOG_CFG_EM1RUN_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM1. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ - false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#elif defined(_WDOG_CFG_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ - false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#elif defined(_WDOG_CTRL_WARNSEL_MASK) \ - && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ - && defined(_WDOG_CTRL_WINSEL_MASK) -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* The clear bit will clear the WDOG counter. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogClkSelLFRCO, /* Select 32.768 kHZ WDOG oscillator. */ \ - wdogPeriod_256k, /* Set longest possible timeout period. */ \ - wdogWarnDisable, /* Disable warning interrupt. */ \ - wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ - false /* Do not disable reset. */ \ - } -#else -#define WDOG_INIT_DEFAULT \ - { \ - true, /* Start Watchdog when initialization is done. */ \ - false, /* WDOG is not counting during debug halt. */ \ - false, /* WDOG is not counting when in EM2. */ \ - false, /* WDOG is not counting when in EM3. */ \ - false, /* EM4 can be entered. */ \ - false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ - false, /* Do not lock WDOG configuration. */ \ - wdogClkSelLFRCO, /* Select 32.768 kHz WDOG oscillator. */ \ - wdogPeriod_256k /* Set longest possible timeout period. */ \ - } -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable); -void WDOGn_Feed(WDOG_TypeDef *wdog); -void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init); -void WDOGn_Lock(WDOG_TypeDef *wdog); -void WDOGn_SyncWait(WDOG_TypeDef *wdog); -void WDOGn_Unlock(WDOG_TypeDef *wdog); - -#if defined(_WDOG_IF_MASK) -/***************************************************************************//** - * @brief - * Clear one or more pending WDOG interrupts. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to clear. Use a set of interrupt flags OR-ed - * together to clear multiple interrupt sources. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntClear(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IF_CLR = flags; -#else - wdog->IFC = flags; -#endif -} - -/***************************************************************************//** - * @brief - * Disable one or more WDOG interrupts. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to disable. Use a set of interrupt flags OR-ed - * together to disable multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntDisable(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IEN_CLR = flags; -#else - wdog->IEN &= ~flags; -#endif -} - -/***************************************************************************//** - * @brief - * Enable one or more WDOG interrupts. - * - * @note - * Depending on the use, a pending interrupt may already be set prior to - * enabling the interrupt. To ignore a pending interrupt, consider using - * WDOG_IntClear() prior to enabling the interrupt. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to enable. Use a set of interrupt flags OR-ed - * together to set multiple interrupt. - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntEnable(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IEN_SET = flags; -#else - wdog->IEN |= flags; -#endif -} - -/***************************************************************************//** - * @brief - * Get pending WDOG interrupt flags. - * - * @note - * The event bits are not cleared by the use of this function. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * Pending WDOG interrupt sources. Returns a set of interrupt flags OR-ed - * together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t WDOGn_IntGet(WDOG_TypeDef *wdog) -{ - return wdog->IF; -} - -/***************************************************************************//** - * @brief - * Get enabled and pending WDOG interrupt flags. - * - * @details - * Useful for handling more interrupt sources in the same interrupt handler. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * Pending and enabled WDOG interrupt sources. Returns a set of interrupt - * flags OR-ed together for the interrupt sources set. - ******************************************************************************/ -__STATIC_INLINE uint32_t WDOGn_IntGetEnabled(WDOG_TypeDef *wdog) -{ - uint32_t tmp; - - tmp = wdog->IEN; - - /* Bitwise AND of pending and enabled interrupt flags. */ - return wdog->IF & tmp; -} - -/***************************************************************************//** - * @brief - * Set one or more pending WDOG interrupts from SW. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] flags - * WDOG interrupt sources to set to pending. Use a set of interrupt flags - * (WDOG_IFS_nnn). - ******************************************************************************/ -__STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags) -{ -#if defined(WDOG_HAS_SET_CLEAR) - wdog->IF_SET = flags; -#else - wdog->IFS = flags; -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Get enabled status of the Watchdog. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * True if Watchdog is enabled. - ******************************************************************************/ -__STATIC_INLINE bool WDOGn_IsEnabled(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_EN_MASK) - return (wdog->EN & _WDOG_EN_EN_MASK) == WDOG_EN_EN; -#else - return (wdog->CTRL & _WDOG_CTRL_EN_MASK) == WDOG_CTRL_EN; -#endif -} - -/***************************************************************************//** - * @brief - * Get locked status of the Watchdog. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @return - * True if Watchdog is locked. - ******************************************************************************/ -__STATIC_INLINE bool WDOGn_IsLocked(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_STATUS_MASK) - return (wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED; -#else - return (wdog->CTRL & _WDOG_CTRL_LOCK_MASK) == WDOG_CTRL_LOCK; -#endif -} - -/** @} (end addtogroup wdog) */ - -#ifdef __cplusplus -} -#endif - -#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ -#endif /* EM_WDOG_H */ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef EM_WDOG_H +#define EM_WDOG_H + +#include "em_device.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include +#include "sl_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup wdog + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** Default WDOG instance for deprecated functions. */ +#if !defined(DEFAULT_WDOG) +#if defined(WDOG0) +#define DEFAULT_WDOG WDOG0 +#elif defined(WDOG) +#define DEFAULT_WDOG WDOG +#endif +#endif + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** Watchdog clock selection. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) +typedef enum { + wdogClkSelULFRCO = _WDOG_CTRL_CLKSEL_ULFRCO, /**< Ultra low frequency (1 kHz) clock */ + wdogClkSelLFRCO = _WDOG_CTRL_CLKSEL_LFRCO, /**< Low frequency RC oscillator */ + wdogClkSelLFXO = _WDOG_CTRL_CLKSEL_LFXO /**< Low frequency crystal oscillator */ +} WDOG_ClkSel_TypeDef; +#endif + +/** Watchdog period selection. */ +typedef enum { + wdogPeriod_9 = 0x0, /**< 9 clock periods */ + wdogPeriod_17 = 0x1, /**< 17 clock periods */ + wdogPeriod_33 = 0x2, /**< 33 clock periods */ + wdogPeriod_65 = 0x3, /**< 65 clock periods */ + wdogPeriod_129 = 0x4, /**< 129 clock periods */ + wdogPeriod_257 = 0x5, /**< 257 clock periods */ + wdogPeriod_513 = 0x6, /**< 513 clock periods */ + wdogPeriod_1k = 0x7, /**< 1025 clock periods */ + wdogPeriod_2k = 0x8, /**< 2049 clock periods */ + wdogPeriod_4k = 0x9, /**< 4097 clock periods */ + wdogPeriod_8k = 0xA, /**< 8193 clock periods */ + wdogPeriod_16k = 0xB, /**< 16385 clock periods */ + wdogPeriod_32k = 0xC, /**< 32769 clock periods */ + wdogPeriod_64k = 0xD, /**< 65537 clock periods */ + wdogPeriod_128k = 0xE, /**< 131073 clock periods */ + wdogPeriod_256k = 0xF /**< 262145 clock periods */ +} WDOG_PeriodSel_TypeDef; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) +/** Select Watchdog warning timeout period as percentage of timeout. */ +typedef enum { + wdogWarnDisable = 0, /**< Watchdog warning period is disabled. */ + wdogWarnTime25pct = 1, /**< Watchdog warning period is 25% of the timeout. */ + wdogWarnTime50pct = 2, /**< Watchdog warning period is 50% of the timeout. */ + wdogWarnTime75pct = 3, /**< Watchdog warning period is 75% of the timeout. */ +} WDOG_WarnSel_TypeDef; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) +/** Select Watchdog illegal window limit. */ +typedef enum { + wdogIllegalWindowDisable = 0, /**< Watchdog illegal window disabled. */ + wdogIllegalWindowTime12_5pct = 1, /**< Window timeout is 12.5% of the timeout. */ + wdogIllegalWindowTime25_0pct = 2, /**< Window timeout is 25% of the timeout. */ + wdogIllegalWindowTime37_5pct = 3, /**< Window timeout is 37.5% of the timeout. */ + wdogIllegalWindowTime50_0pct = 4, /**< Window timeout is 50% of the timeout. */ + wdogIllegalWindowTime62_5pct = 5, /**< Window timeout is 62.5% of the timeout. */ + wdogIllegalWindowTime75_0pct = 6, /**< Window timeout is 75% of the timeout. */ + wdogIllegalWindowTime87_5pct = 7, /**< Window timeout is 87.5% of the timeout. */ +} WDOG_WinSel_TypeDef; +#endif + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** Watchdog initialization structure. */ +typedef struct { + /** Enable Watchdog when initialization completed. */ + bool enable; + + /** Counter keeps running during debug halt. */ + bool debugRun; + +#if defined(_WDOG_CTRL_CLRSRC_MASK) \ + || defined(_WDOG_CFG_CLRSRC_MASK) + /** Select WDOG clear source: + * False: Write to the clear bit will clear the WDOG counter + * True: Rising edge on the PRS Source 0 will clear the WDOG counter + * */ + bool clrSrc; +#endif + +#if defined(_WDOG_CFG_EM1RUN_MASK) + /** Counter keeps running when in EM1. Available for series2. */ + bool em1Run; +#endif + + /** Counter keeps running when in EM2. */ + bool em2Run; + + /** Counter keeps running when in EM3. */ + bool em3Run; + + /** Block EMU from entering EM4. */ + bool em4Block; + +#if defined(_WDOG_CFG_MASK) + /** When set, a PRS Source 0 missing event will trigger a WDOG reset. */ + bool prs0MissRstEn; + + /** When set, a PRS Source 1 missing event will trigger a WDOG reset. */ + bool prs1MissRstEn; +#endif + + /** Block SW from disabling LFRCO/LFXO oscillators. */ +#if defined(_WDOG_CTRL_SWOSCBLOCK_MASK) + bool swoscBlock; +#endif + + /** Block SW from modifying the configuration (a reset is needed to reconfigure). */ + bool lock; + + /** Clock source to use for Watchdog. */ +#if defined(_WDOG_CTRL_CLKSEL_MASK) + WDOG_ClkSel_TypeDef clkSel; +#endif + + /** Watchdog timeout period. */ + WDOG_PeriodSel_TypeDef perSel; + +#if defined(_WDOG_CTRL_WARNSEL_MASK) \ + || defined(_WDOG_CFG_WARNSEL_MASK) + /** Select warning time as % of the Watchdog timeout */ + WDOG_WarnSel_TypeDef warnSel; +#endif + +#if defined(_WDOG_CTRL_WINSEL_MASK) \ + || defined(_WDOG_CFG_WINSEL_MASK) + /** Select illegal window time as % of the Watchdog timeout */ + WDOG_WinSel_TypeDef winSel; +#endif + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + || defined(_WDOG_CFG_WDOGRSTDIS_MASK) + /** Disable Watchdog reset output if true */ + bool resetDisable; +#endif +} WDOG_Init_TypeDef; + +/** Suggested default configuration for WDOG initialization structure. */ +#if defined(_WDOG_CFG_MASK) && defined(_WDOG_CFG_EM1RUN_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM1. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CFG_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* PRS Source 0 missing event will not trigger a WDOG reset. */ \ + false, /* PRS Source 1 missing event will not trigger a WDOG reset. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#elif defined(_WDOG_CTRL_WARNSEL_MASK) \ + && defined(_WDOG_CTRL_WDOGRSTDIS_MASK) \ + && defined(_WDOG_CTRL_WINSEL_MASK) +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* The clear bit will clear the WDOG counter. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHZ WDOG oscillator. */ \ + wdogPeriod_256k, /* Set longest possible timeout period. */ \ + wdogWarnDisable, /* Disable warning interrupt. */ \ + wdogIllegalWindowDisable, /* Disable illegal window interrupt. */ \ + false /* Do not disable reset. */ \ + } +#else +#define WDOG_INIT_DEFAULT \ + { \ + true, /* Start Watchdog when initialization is done. */ \ + false, /* WDOG is not counting during debug halt. */ \ + false, /* WDOG is not counting when in EM2. */ \ + false, /* WDOG is not counting when in EM3. */ \ + false, /* EM4 can be entered. */ \ + false, /* Do not block disabling LFRCO/LFXO in CMU. */ \ + false, /* Do not lock WDOG configuration. */ \ + wdogClkSelLFRCO, /* Select 32.768 kHz WDOG oscillator. */ \ + wdogPeriod_256k /* Set longest possible timeout period. */ \ + } +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable); +void WDOGn_Feed(WDOG_TypeDef *wdog); +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init); +void WDOGn_Lock(WDOG_TypeDef *wdog); +void WDOGn_SyncWait(WDOG_TypeDef *wdog); +void WDOGn_Unlock(WDOG_TypeDef *wdog); + +#if defined(_WDOG_IF_MASK) +/***************************************************************************//** + * @brief + * Clear one or more pending WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to clear. Use a set of interrupt flags OR-ed + * together to clear multiple interrupt sources. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntClear(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_CLR = flags; +#else + wdog->IFC = flags; +#endif +} + +/***************************************************************************//** + * @brief + * Disable one or more WDOG interrupts. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to disable. Use a set of interrupt flags OR-ed + * together to disable multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntDisable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_CLR = flags; +#else + wdog->IEN &= ~flags; +#endif +} + +/***************************************************************************//** + * @brief + * Enable one or more WDOG interrupts. + * + * @note + * Depending on the use, a pending interrupt may already be set prior to + * enabling the interrupt. To ignore a pending interrupt, consider using + * WDOG_IntClear() prior to enabling the interrupt. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to enable. Use a set of interrupt flags OR-ed + * together to set multiple interrupt. + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntEnable(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IEN_SET = flags; +#else + wdog->IEN |= flags; +#endif +} + +/***************************************************************************//** + * @brief + * Get pending WDOG interrupt flags. + * + * @note + * The event bits are not cleared by the use of this function. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending WDOG interrupt sources. Returns a set of interrupt flags OR-ed + * together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGet(WDOG_TypeDef *wdog) +{ + return wdog->IF; +} + +/***************************************************************************//** + * @brief + * Get enabled and pending WDOG interrupt flags. + * + * @details + * Useful for handling more interrupt sources in the same interrupt handler. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * Pending and enabled WDOG interrupt sources. Returns a set of interrupt + * flags OR-ed together for the interrupt sources set. + ******************************************************************************/ +__STATIC_INLINE uint32_t WDOGn_IntGetEnabled(WDOG_TypeDef *wdog) +{ + uint32_t tmp; + + tmp = wdog->IEN; + + /* Bitwise AND of pending and enabled interrupt flags. */ + return wdog->IF & tmp; +} + +/***************************************************************************//** + * @brief + * Set one or more pending WDOG interrupts from SW. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] flags + * WDOG interrupt sources to set to pending. Use a set of interrupt flags + * (WDOG_IFS_nnn). + ******************************************************************************/ +__STATIC_INLINE void WDOGn_IntSet(WDOG_TypeDef *wdog, uint32_t flags) +{ +#if defined(WDOG_HAS_SET_CLEAR) + wdog->IF_SET = flags; +#else + wdog->IFS = flags; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get enabled status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is enabled. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsEnabled(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_EN_MASK) + return (wdog->EN & _WDOG_EN_EN_MASK) == WDOG_EN_EN; +#else + return (wdog->CTRL & _WDOG_CTRL_EN_MASK) == WDOG_CTRL_EN; +#endif +} + +/***************************************************************************//** + * @brief + * Get locked status of the Watchdog. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @return + * True if Watchdog is locked. + ******************************************************************************/ +__STATIC_INLINE bool WDOGn_IsLocked(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_STATUS_MASK) + return (wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED; +#else + return (wdog->CTRL & _WDOG_CTRL_LOCK_MASK) == WDOG_CTRL_LOCK; +#endif +} + +/** @} (end addtogroup wdog) */ + +#ifdef __cplusplus +} +#endif + +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ +#endif /* EM_WDOG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h index eb57d5c..9b2e671 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/inc/sli_em_cmu.h @@ -1,1899 +1,1899 @@ -/***************************************************************************//** - * @file - * @brief Clock Management Unit Private API definition. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_EM_CMU_H -#define SLI_EM_CMU_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(_SILICON_LABS_32B_SERIES_2) - -/***************************************************************************//** - * @brief Performs pre-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPreClockSelect(void); - -/***************************************************************************//** - * @brief Performs post-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPostClockSelect(void); - -/***************************************************************************//** - * @brief Sets the HFXO0 FORCEEN bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK and the selected clock source is HFXO. - ******************************************************************************/ -void sli_em_cmu_HFXOSetForceEnable(void); - -/***************************************************************************//** - * @brief This function will set the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENSet(void); - -/***************************************************************************//** - * @brief This function will clear the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENClear(void); - -#define CMU_SYSCLK_SELECT_HFRCODPLL \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#define CMU_SYSCLK_SELECT_HFXO \ - do { \ - sli_em_cmu_HFXOSetForceEnable(); \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ - } \ - } while (0) - -#define CMU_SYSCLK_SELECT_CLKIN0 \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#define CMU_SYSCLK_SELECT_FSRCO \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#if defined(RFFPLL_PRESENT) - -#define CMU_SYSCLK_SELECT_RFFPLLSYS \ - do { \ - sli_em_cmu_SYSCLKInitPreClockSelect(); \ - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ - | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ - sli_em_cmu_SYSCLKInitPostClockSelect(); \ - } while (0) - -#endif /* RFFPLL_PRESENT */ - -#if defined(IADC_PRESENT) -#define CMU_IADCCLK_SELECT_EM01GRPACLK \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK - -#if defined(HFRCOEM23_PRESENT) -#define CMU_IADCCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 -#endif /* HFRCOEM23_PRESENT */ - -#define CMU_IADCCLK_SELECT_FSRCO \ - do { \ - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ - | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO -#endif /* IADC_PRESENT */ - -#define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL -#endif /* KEYSCAN_PRESENT*/ - -#define CMU_EM01GRPACLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO -#endif /* KEYSCAN_PRESENT*/ - -#if defined(HFRCOEM23_PRESENT) -#define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 -#endif /* KEYSCAN_PRESENT*/ -#endif /* HFRCOEM23_PRESENT */ - -#define CMU_EM01GRPACLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO -#endif /* KEYSCAN_PRESENT*/ - -#define CMU_EM01GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) -#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT -#endif /* KEYSCAN_PRESENT*/ -#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) -#define CMU_EM01GRPACLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#if TIMER_COUNT > 4 -#define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 4 */ -#if TIMER_COUNT > 7 -#define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 7 */ -#if TIMER_COUNT > 9 -#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* TIMER_COUNT > 9 */ -#if defined(KEYSCAN_PRESENT) -#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT -#endif /* KEYSCAN_PRESENT*/ -#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ - -#define CMU_SYSTICK_SELECT_EM23GRPACLK \ - do { \ - sli_em_cmu_SYSTICEXTCLKENSet(); \ - SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ - } while (0) - -#define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK -#define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK -#define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK - -#define CMU_SYSTICK_SELECT_HCLK \ - do { \ - sli_em_cmu_SYSTICEXTCLKENClear(); \ - SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ - } while (0) - -#define CMU_EM23GRPACLK_SELECT_LFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO -#endif /* LESENSE_PRESENT */ - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EM23GRPACLK_SELECT_PLFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO -#endif /* LESENSE_PRESENT */ -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_EM23GRPACLK_SELECT_LFXO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO -#endif /* LESENSE_PRESENT */ - -#define CMU_EM23GRPACLK_SELECT_ULFRCO \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#if defined(LESENSE_PRESENT) -#define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO -#endif /* LESENSE_PRESENT */ - -#define CMU_EM23GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_EM4GRPACLK_SELECT_LFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EM4GRPACLK_SELECT_PLFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_EM4GRPACLK_SELECT_LFXO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO - -#define CMU_EM4GRPACLK_SELECT_ULFRCO \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO - -#define CMU_EM4GRPACLK_SELECT_DISABLED \ - do { \ - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ - | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) -#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL - -#define CMU_EM01GRPBCLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO - -#define CMU_EM01GRPBCLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO - -#define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ - } while (0) - -#define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 - -#define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT - -#define CMU_EM01GRPBCLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT - -#define CMU_EM01GRPBCLK_SELECT_DISABLED \ - do { \ - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ - -#define CMU_WDOG0_SELECT_LFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_WDOG0_SELECT_PLFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_WDOG0_SELECT_LFXO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO - -#define CMU_WDOG0_SELECT_ULFRCO \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO - -#define CMU_WDOG0_SELECT_HCLKDIV1024 \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ - } while (0) - -#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 - -#define CMU_WDOG0_SELECT_DISABLED \ - do { \ - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED - -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) -#define CMU_WDOG1_SELECT_LFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_WDOG1_SELECT_PLFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_WDOG1_SELECT_LFXO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO - -#define CMU_WDOG1_SELECT_ULFRCO \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO - -#define CMU_WDOG1_SELECT_HCLKDIV1024 \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ - } while (0) - -#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 - -#define CMU_WDOG1_SELECT_DISABLED \ - do { \ - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ - | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED -#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ - -#define CMU_DPLLREFCLK_SELECT_HFXO \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_LFXO \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_CLKIN0 \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ - } while (0) - -#define CMU_DPLLREFCLK_SELECT_DISABLED \ - do { \ - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ - | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) -#define CMU_TRACECLK_RESTORE_TRACE_PRE() \ - bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ - if (restoreTrace) { \ - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ - } \ - do {} while (0) - -#define CMU_TRACECLK_RESTORE_TRACE_POST() \ - if (restoreTrace) { \ - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ - } \ - do {} while (0) - -#else -#define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) -#define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#define CMU_TRACECLK_SELECT_HCLK \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - #define CMU_TRACECLK_SELECT_SYSCLK \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#define CMU_TRACECLK_SELECT_HFRCODPLLRT \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) -#define CMU_TRACECLK_SELECT_HFRCOEM23 \ - do { \ - CMU_TRACECLK_RESTORE_TRACE_PRE(); \ - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ - | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ - CMU_TRACECLK_RESTORE_TRACE_POST(); \ - } while (0) - -#endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ - -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) -#define CMU_EUART0_SELECT_EM01GRPACLK \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK - -#define CMU_EUART0_SELECT_EM23GRPACLK \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK - -#define CMU_EUART0_SELECT_DISABLED \ - do { \ - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) -#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED -#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ - -#if defined(EUSART_PRESENT) -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) -#define CMU_EUSART0_SELECT_EM01GRPACLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) -#define CMU_EUSART0_SELECT_EM01GRPCCLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) -#define CMU_EUSART0_SELECT_EM23GRPACLK \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) -#define CMU_EUSART0_SELECT_FSRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) -#define CMU_EUSART0_SELECT_HFRCOEM23 \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) -#define CMU_EUSART0_SELECT_LFRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_EUSART0_SELECT_PLFRCO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) -#define CMU_EUSART0_SELECT_LFXO \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) -#define CMU_EUSART0_SELECT_DISABLED \ - do { \ - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ - | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED -#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ -#endif /* EUSART_PRESENT */ - -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -#define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) -#define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ -#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ - -#define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#define CMU_EM01GRPCCLK_SELECT_FSRCO \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#define CMU_EM01GRPCCLK_SELECT_HFXO \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) -#define CMU_EM01GRPCCLK_SELECT_HFXORT \ - do { \ - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ - | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ - } while (0) - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 -#define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 -#define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 -#define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 -#define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT -#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ -#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ -#endif /* _CMU_EM01GRPCCLKCTRL_MASK */ - -#if defined (RTCC_PRESENT) -#define CMU_RTCC_SELECT_LFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_RTCC_SELECT_PLFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_RTCC_SELECT_LFXO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO - -#define CMU_RTCC_SELECT_ULFRCO \ - do { \ - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ - | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO - -#endif /* RTCC_PRESENT */ - -#if defined(SYSRTC_PRESENT) -#define CMU_SYSRTC_SELECT_LFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_SYSRTC_SELECT_PLFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_SYSRTC_SELECT_LFXO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO - -#define CMU_SYSRTC_SELECT_ULFRCO \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO - -#define CMU_SYSRTC_SELECT_DISABLED \ - do { \ - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ - | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ - } while (0) - -#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED -#endif /* SYSRTC_PRESENT */ - -#if defined(LCD_PRESENT) -#define CMU_LCD_SELECT_LFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO - -#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) -#define CMU_LCD_SELECT_PLFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO -#endif /* LFRCO_PRECISION_MODE */ - -#define CMU_LCD_SELECT_LFXO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO - -#define CMU_LCD_SELECT_ULFRCO \ - do { \ - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ - | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ - } while (0) - -#define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO -#endif /* LCD_PRESENT */ - -#if defined(VDAC_PRESENT) -#define CMU_VDAC0_SELECT_FSRCO \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO - -#define CMU_VDAC0_SELECT_HFRCOEM23 \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 - -#define CMU_VDAC0_SELECT_EM01GRPACLK \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK - -#define CMU_VDAC0_SELECT_EM23GRPACLK \ - do { \ - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK - -#if (VDAC_COUNT > 1) -#define CMU_VDAC1_SELECT_FSRCO \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO - -#define CMU_VDAC1_SELECT_HFRCOEM23 \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 - -#define CMU_VDAC1_SELECT_EM01GRPACLK \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK - -#define CMU_VDAC1_SELECT_EM23GRPACLK \ - do { \ - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ - | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK -#endif /* VDAC_COUNT > 1 */ -#endif /* VDAC_PRESENT */ - -#if defined(PCNT_PRESENT) -#define CMU_PCNT0_SELECT_EM23GRPACLK \ - do { \ - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ - | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ - } while (0) - -#define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK - -#define CMU_PCNT0_SELECT_PCNTEXTCLK \ - do { \ - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ - | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ - } while (0) - -#define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK -#endif /* PCNT_PRESENT */ - -#if defined(LESENSE_PRESENT) -#define CMU_LESENSEHFCLK_SELECT_FSRCO \ - do { \ - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ - | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ - } while (0) - -#define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ - do { \ - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ - | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ - } while (0) -#endif /* LESENSE_PRESENT */ - -#if defined(USB_PRESENT) -#define CMU_USB_SELECT_USBPLL0 \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ - } while (0) - -#define CMU_USB_SELECT_LFXO \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ - } while (0) - -#define CMU_USB_SELECT_LFRCO \ - do { \ - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ - | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ - } while (0) -#endif /* USB_PRESENT */ - -#elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the System Core Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the HF Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigHFClock(void); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * an LF clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @param[in]osc - * Reference to a low-frequency oscillator. One of the following values is valid: - * - cmuOsc_LFXO - * - cmuOsc_LFRCO - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and LFXO or LFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFXO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFXO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFXO(void); - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCO(void); - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCODIV2(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * CLKIN0 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and CLKIN0 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectCLKIN0(void); -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCO(void); -#endif - -#define CMU_HF_SELECT_LFXO \ - do { \ - sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ - } while (0) - -#define CMU_HF_SELECT_LFRCO \ - do { \ - sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ - } while (0) - -#define CMU_HF_SELECT_HFXO \ - do { \ - sli_em_cmu_HFClockSelectHFXO(); \ - } while (0) - -#define CMU_HF_SELECT_HFRCO \ - do { \ - sli_em_cmu_HFClockSelectHFRCO(); \ - } while (0) - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -#define CMU_HF_SELECT_USHFRCODIV2 \ - do { \ - sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -#define CMU_HF_SELECT_HFRCODIV2 \ - do { \ - sli_em_cmu_HFClockSelectHFRCODIV2(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -#define CMU_HF_SELECT_CLKIN0 \ - do { \ - sli_em_cmu_HFClockSelectCLKIN0(); \ - } while (0) -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -#define CMU_HF_SELECT_USHFRCO \ - do { \ - sli_em_cmu_HFClockSelectUSHFRCO(); \ - } while (0) -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ - } while (0) - -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFA_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ - -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigHFClock(); \ - BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ - } while (0) - -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFB_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ - -#if defined(_CMU_LFCCLKSEL_MASK) -#define CMU_LFC_SELECT_DISABLED \ - do { \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ - } while (0) - -#define CMU_LFC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ - } while (0) - -#define CMU_LFC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ - } while (0) - -#define CMU_LFC_SELECT_ULFRCO \ - do { \ - CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ - } while (0) - -#endif /* _CMU_LFCCLKSEL_MASK */ - -#define CMU_LFE_SELECT_DISABLED \ - do { \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ - } while (0) - -#define CMU_LFE_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ - } while (0) - -#define CMU_LFE_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ - } while (0) - -#define CMU_LFE_SELECT_ULFRCO \ - do { \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ - } while (0) - -#if defined(CMU_OSCENCMD_PLFRCOEN) -#define CMU_LFE_SELECT_PLFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ - CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ - } while (0) -#endif /* CMU_OSCENCMD_PLFRCOEN */ -#endif /* _SILICON_LABS_32B_SERIES_1 */ - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(_CMU_LFCLKSEL_LFAE_MASK) -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ - | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ - } while (0) -#endif - -#else -#define CMU_LFA_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#define CMU_LFA_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) -#define CMU_LFA_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ - | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ - } while (0) -#endif /* CMU_LFA_SELECT_HFCLKLE */ -#endif /* _CMU_LFCLKSEL_LFAE_MASK */ - -#if defined(_CMU_LFCLKSEL_LFBE_MASK) -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL \ - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ - | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ - } while (0) -#endif - -#else -#define CMU_LFB_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#define CMU_LFB_SELECT_HFCLKLE \ - do { \ - sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) - -#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) -#define CMU_LFB_SELECT_ULFRCO \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ - | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ - } while (0) -#endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ -#endif /* _CMU_LFCLKSEL_LFBE_MASK */ - -#define CMU_LFC_SELECT_DISABLED \ - do { \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) - -#define CMU_LFC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) - -#define CMU_LFC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ - | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ - } while (0) -#endif /* _SILICON_LABS_32B_SERIES_0 */ - -#if defined(_CMU_DBGCLKSEL_DBG_MASK) -#define CMU_DBG_SELECT_AUXHFRCO \ - do { \ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ - } while (0) - -#define CMU_DBG_SELECT_HFCLK \ - do { \ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ - } while (0) -#endif /* _CMU_DBGCLKSEL_DBG_MASK */ - -#if defined(CMU_CTRL_DBGCLK) -#define CMU_DBG_SELECT_AUXHFRCO \ - do { \ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ - | CMU_CTRL_DBGCLK_AUXHFRCO; \ - } while (0) - -#define CMU_DBG_SELECT_HFCLK \ - do { \ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ - | CMU_CTRL_DBGCLK_HFCLK; \ - } while (0) -#endif /* CMU_CTRL_DBGCLK */ - -#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) -#define CMU_USBC_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ - while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ - } while (0) - -#define CMU_USBC_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ - while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ - } while (0) - -#if defined(CMU_STATUS_USBCHFCLKSEL) -#define CMU_USBC_SELECT_HFCLK \ - do { \ - CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ - while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ - } while (0) -#endif /* CMU_STATUS_USBCHFCLKSEL */ - -#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) -#define CMU_USBC_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ - while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ - } while (0) -#endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ -#endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) -#define CMU_ADC0ASYNC_SELECT_DISABLED \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) -#define CMU_ADC1ASYNC_SELECT_DISABLED \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) - -#define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ - do { \ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ - | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) -#define CMU_SDIOREF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) - -#define CMU_SDIOREF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ - | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) -#define CMU_QSPI0REF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_AUXHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) - -#define CMU_QSPI0REF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ - | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) -#define CMU_USBR_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFXOX2 \ - do { \ - EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ - CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_LFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) - -#define CMU_USBR_SELECT_LFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ - | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) -#define CMU_PDMREF_SELECT_USHFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) - -#define CMU_PDMREF_SELECT_HFXO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) - -#define CMU_PDMREF_SELECT_HFRCO \ - do { \ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ - | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ - } while (0) -#endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ -#endif /* _SILICON_LABS_32B_SERIES_2 */ -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* SLI_EM_CMU_H */ +/***************************************************************************//** + * @file + * @brief Clock Management Unit Private API definition. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_EM_CMU_H +#define SLI_EM_CMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void); + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(void); + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void); + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void); + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void); + +#define CMU_SYSCLK_SELECT_HFRCODPLL \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#define CMU_SYSCLK_SELECT_HFXO \ + do { \ + sli_em_cmu_HFXOSetForceEnable(); \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_HFXO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \ + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \ + } \ + } while (0) + +#define CMU_SYSCLK_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_CLKIN0; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#define CMU_SYSCLK_SELECT_FSRCO \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_FSRCO; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#if defined(RFFPLL_PRESENT) + +#define CMU_SYSCLK_SELECT_RFFPLLSYS \ + do { \ + sli_em_cmu_SYSCLKInitPreClockSelect(); \ + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) \ + | CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; \ + sli_em_cmu_SYSCLKInitPostClockSelect(); \ + } while (0) + +#endif /* RFFPLL_PRESENT */ + +#if defined(IADC_PRESENT) +#define CMU_IADCCLK_SELECT_EM01GRPACLK \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_IADC0_SELECT_EM01GRPACLK CMU_IADCCLK_SELECT_EM01GRPACLK + +#if defined(HFRCOEM23_PRESENT) +#define CMU_IADCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_IADC0_SELECT_HFRCOEM23 CMU_IADCCLK_SELECT_HFRCOEM23 +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_IADCCLK_SELECT_FSRCO \ + do { \ + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) \ + | CMU_IADCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_IADC0_SELECT_FSRCO CMU_IADCCLK_SELECT_FSRCO +#endif /* IADC_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER1_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER2_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER3_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER6_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER7_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#define CMU_TIMER9_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLL CMU_EM01GRPACLK_SELECT_HFRCODPLL +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER1_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER2_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER3_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER6_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER7_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#define CMU_TIMER9_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXO CMU_EM01GRPACLK_SELECT_HFXO +#endif /* KEYSCAN_PRESENT*/ + +#if defined(HFRCOEM23_PRESENT) +#define CMU_EM01GRPACLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER1_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER2_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER3_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER6_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER7_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#define CMU_TIMER9_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCOEM23 CMU_EM01GRPACLK_SELECT_HFRCOEM23 +#endif /* KEYSCAN_PRESENT*/ +#endif /* HFRCOEM23_PRESENT */ + +#define CMU_EM01GRPACLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_TIMER0_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER1_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER2_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER3_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER6_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER7_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#define CMU_TIMER9_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_FSRCO CMU_EM01GRPACLK_SELECT_FSRCO +#endif /* KEYSCAN_PRESENT*/ + +#define CMU_EM01GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPACLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER1_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER2_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER3_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER6_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER7_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#define CMU_TIMER9_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFRCODPLLRT CMU_EM01GRPACLK_SELECT_HFRCODPLLRT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT */ + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPACLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_TIMER0_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER1_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER2_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER3_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#if TIMER_COUNT > 4 +#define CMU_TIMER4_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 4 */ +#if TIMER_COUNT > 7 +#define CMU_TIMER5_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER6_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER7_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 7 */ +#if TIMER_COUNT > 9 +#define CMU_TIMER8_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#define CMU_TIMER9_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* TIMER_COUNT > 9 */ +#if defined(KEYSCAN_PRESENT) +#define CMU_KEYSCAN_SELECT_HFXORT CMU_EM01GRPACLK_SELECT_HFXORT +#endif /* KEYSCAN_PRESENT*/ +#endif /* CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT */ + +#define CMU_SYSTICK_SELECT_EM23GRPACLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENSet(); \ + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_SYSTICK_SELECT_LFXO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_LFRCO CMU_SYSTICK_SELECT_EM23GRPACLK +#define CMU_SYSTICK_SELECT_ULFRCO CMU_SYSTICK_SELECT_EM23GRPACLK + +#define CMU_SYSTICK_SELECT_HCLK \ + do { \ + sli_em_cmu_SYSTICEXTCLKENClear(); \ + SysTick->CTRL = (SysTick->CTRL | ~SysTick_CTRL_CLKSOURCE_Msk); \ + } while (0) + +#define CMU_EM23GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#define CMU_LESENSECLK_SELECT_LFRCO CMU_EM23GRPACLK_SELECT_LFRCO +#endif /* LESENSE_PRESENT */ + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM23GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#define CMU_LESENSECLK_SELECT_PLFRCO CMU_EM23GRPACLK_SELECT_PLFRCO +#endif /* LESENSE_PRESENT */ +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM23GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#define CMU_LESENSECLK_SELECT_LFXO CMU_EM23GRPACLK_SELECT_LFXO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LETIMER0_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#if defined(LESENSE_PRESENT) +#define CMU_LESENSE_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#define CMU_LESENSECLK_SELECT_ULFRCO CMU_EM23GRPACLK_SELECT_ULFRCO +#endif /* LESENSE_PRESENT */ + +#define CMU_EM23GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EM4GRPACLK_SELECT_LFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFRCO CMU_EM4GRPACLK_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EM4GRPACLK_SELECT_PLFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_PLFRCO CMU_EM4GRPACLK_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_EM4GRPACLK_SELECT_LFXO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_BURTC_SELECT_LFXO CMU_EM4GRPACLK_SELECT_LFXO + +#define CMU_EM4GRPACLK_SELECT_ULFRCO \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_BURTC_SELECT_ULFRCO CMU_EM4GRPACLK_SELECT_ULFRCO + +#define CMU_EM4GRPACLK_SELECT_DISABLED \ + do { \ + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) \ + | CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLL CMU_EM01GRPBCLK_SELECT_HFRCODPLL + +#define CMU_EM01GRPBCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO CMU_EM01GRPBCLK_SELECT_HFXO + +#define CMU_EM01GRPBCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_PDMREF_SELECT_FSRCO CMU_EM01GRPBCLK_SELECT_FSRCO + +#define CMU_EM01GRPBCLK_SELECT_CLKIN0 \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_PDMREF_SELECT_CLKIN0 CMU_EM01GRPBCLK_SELECT_CLKIN0 + +#define CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCODPLLRT CMU_EM01GRPBCLK_SELECT_HFRCODPLLRT + +#define CMU_EM01GRPBCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXORT CMU_EM01GRPBCLK_SELECT_HFXORT + +#define CMU_EM01GRPBCLK_SELECT_DISABLED \ + do { \ + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#endif /* defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) */ + +#define CMU_WDOG0_SELECT_LFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFRCO CMU_WDOG0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG0_SELECT_PLFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_PLFRCO CMU_WDOG0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG0_SELECT_LFXO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_LFXO CMU_WDOG0_SELECT_LFXO + +#define CMU_WDOG0_SELECT_ULFRCO \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_ULFRCO CMU_WDOG0_SELECT_ULFRCO + +#define CMU_WDOG0_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG0CLK_SELECT_HCLKDIV1024 CMU_WDOG0_SELECT_HCLKDIV1024 + +#define CMU_WDOG0_SELECT_DISABLED \ + do { \ + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG0CLK_SELECT_DISABLED CMU_WDOG0_SELECT_DISABLED + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +#define CMU_WDOG1_SELECT_LFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFRCO CMU_WDOG1_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_WDOG1_SELECT_PLFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_PLFRCO CMU_WDOG1_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_WDOG1_SELECT_LFXO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_LFXO CMU_WDOG1_SELECT_LFXO + +#define CMU_WDOG1_SELECT_ULFRCO \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_ULFRCO CMU_WDOG1_SELECT_ULFRCO + +#define CMU_WDOG1_SELECT_HCLKDIV1024 \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; \ + } while (0) + +#define CMU_WDOG1CLK_SELECT_HCLKDIV1024 CMU_WDOG1_SELECT_HCLKDIV1024 + +#define CMU_WDOG1_SELECT_DISABLED \ + do { \ + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) \ + | CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_WDOG1CLK_SELECT_DISABLED CMU_WDOG1_SELECT_DISABLED +#endif /* defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) */ + +#define CMU_DPLLREFCLK_SELECT_HFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_LFXO \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_CLKIN0 \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; \ + } while (0) + +#define CMU_DPLLREFCLK_SELECT_DISABLED \ + do { \ + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) \ + | CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) +#define CMU_TRACECLK_RESTORE_TRACE_PRE() \ + bool restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; \ + if (restoreTrace) { \ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#define CMU_TRACECLK_RESTORE_TRACE_POST() \ + if (restoreTrace) { \ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; \ + } \ + do {} while (0) + +#else +#define CMU_TRACECLK_RESTORE_TRACE_PRE() do {} while (0) +#define CMU_TRACECLK_RESTORE_TRACE_POST() do {} while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define CMU_TRACECLK_SELECT_HCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* _SILICON_LABS_32B_SERIES_2_CONFIG_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + #define CMU_TRACECLK_SELECT_SYSCLK \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_SYSCLK; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#define CMU_TRACECLK_SELECT_HFRCODPLLRT \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_TRACECLK_SELECT_HFRCOEM23 \ + do { \ + CMU_TRACECLK_RESTORE_TRACE_PRE(); \ + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) \ + | CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; \ + CMU_TRACECLK_RESTORE_TRACE_POST(); \ + } while (0) + +#endif /* CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +#define CMU_EUART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM01GRPACLK CMU_EUART0_SELECT_EM01GRPACLK + +#define CMU_EUART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUART0CLK_SELECT_EM23GRPACLK CMU_EUART0_SELECT_EM23GRPACLK + +#define CMU_EUART0_SELECT_DISABLED \ + do { \ + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) +#define CMU_EUART0CLK_SELECT_DISABLED CMU_EUART0_SELECT_DISABLED +#endif /* _CMU_EUART0CLKCTRL_CLKSEL_MASK */ + +#if defined(EUSART_PRESENT) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) +#define CMU_EUSART0_SELECT_EM01GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPACLK CMU_EUSART0_SELECT_EM01GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) +#define CMU_EUSART0_SELECT_EM01GRPCCLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM01GRPCCLK CMU_EUSART0_SELECT_EM01GRPCCLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) +#define CMU_EUSART0_SELECT_EM23GRPACLK \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_EM23GRPACLK CMU_EUSART0_SELECT_EM23GRPACLK +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) +#define CMU_EUSART0_SELECT_FSRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_FSRCO CMU_EUSART0_SELECT_FSRCO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) +#define CMU_EUSART0_SELECT_HFRCOEM23 \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_HFRCOEM23 CMU_EUSART0_SELECT_HFRCOEM23 +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23 */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) +#define CMU_EUSART0_SELECT_LFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFRCO CMU_EUSART0_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_EUSART0_SELECT_PLFRCO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_PLFRCO CMU_EUSART0_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) +#define CMU_EUSART0_SELECT_LFXO \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_LFXO CMU_EUSART0_SELECT_LFXO +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_LFXO */ + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) +#define CMU_EUSART0_SELECT_DISABLED \ + do { \ + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) \ + | _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_EUSART0CLK_SELECT_DISABLED CMU_EUSART0_SELECT_DISABLED +#endif /* _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED */ +#endif /* EUSART_PRESENT */ + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLL \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLL CMU_EM01GRPCCLK_SELECT_HFRCODPLL +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) +#define CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCODPLLRT CMU_EM01GRPCCLK_SELECT_HFRCODPLLRT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT */ + +#define CMU_EM01GRPCCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFRCOEM23 CMU_EM01GRPCCLK_SELECT_HFRCOEM23 +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#define CMU_EM01GRPCCLK_SELECT_FSRCO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_FSRCO CMU_EM01GRPCCLK_SELECT_FSRCO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#define CMU_EM01GRPCCLK_SELECT_HFXO \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXO CMU_EM01GRPCCLK_SELECT_HFXO +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) +#define CMU_EM01GRPCCLK_SELECT_HFXORT \ + do { \ + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) \ + | _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; \ + } while (0) + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 +#define CMU_EUSART1_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 1 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 +#define CMU_EUSART2_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 2 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 +#define CMU_EUSART3_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 3 */ +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 +#define CMU_EUSART4_SELECT_HFXORT CMU_EM01GRPCCLK_SELECT_HFXORT +#endif /* EUSART_PRESENT && EUSART_COUNT > 4 */ +#endif /* CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT */ +#endif /* _CMU_EM01GRPCCLKCTRL_MASK */ + +#if defined (RTCC_PRESENT) +#define CMU_RTCC_SELECT_LFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFRCO CMU_RTCC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_RTCC_SELECT_PLFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_PLFRCO CMU_RTCC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_RTCC_SELECT_LFXO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_LFXO CMU_RTCC_SELECT_LFXO + +#define CMU_RTCC_SELECT_ULFRCO \ + do { \ + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) \ + | CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_RTCCCLK_SELECT_ULFRCO CMU_RTCC_SELECT_ULFRCO + +#endif /* RTCC_PRESENT */ + +#if defined(SYSRTC_PRESENT) +#define CMU_SYSRTC_SELECT_LFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFRCO CMU_SYSRTC_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_SYSRTC_SELECT_PLFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_PLFRCO CMU_SYSRTC_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_SYSRTC_SELECT_LFXO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_LFXO CMU_SYSRTC_SELECT_LFXO + +#define CMU_SYSRTC_SELECT_ULFRCO \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_ULFRCO CMU_SYSRTC_SELECT_ULFRCO + +#define CMU_SYSRTC_SELECT_DISABLED \ + do { \ + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) \ + | CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; \ + } while (0) + +#define CMU_SYSRTCCLK_SELECT_DISABLED CMU_SYSRTC_SELECT_DISABLED +#endif /* SYSRTC_PRESENT */ + +#if defined(LCD_PRESENT) +#define CMU_LCD_SELECT_LFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFRCO CMU_LCD_SELECT_LFRCO + +#if defined(LFRCO_PRECISION_MODE) && (LFRCO_PRECISION_MODE == 1) +#define CMU_LCD_SELECT_PLFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_PLFRCO CMU_LCD_SELECT_PLFRCO +#endif /* LFRCO_PRECISION_MODE */ + +#define CMU_LCD_SELECT_LFXO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_LFXO CMU_LCD_SELECT_LFXO + +#define CMU_LCD_SELECT_ULFRCO \ + do { \ + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) \ + | CMU_LCDCLKCTRL_CLKSEL_ULFRCO; \ + } while (0) + +#define CMU_LCDCLK_SELECT_ULFRCO CMU_LCD_SELECT_ULFRCO +#endif /* LCD_PRESENT */ + +#if defined(VDAC_PRESENT) +#define CMU_VDAC0_SELECT_FSRCO \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_FSRCO CMU_VDAC_SELECT_FSRCO + +#define CMU_VDAC0_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_HFRCOEM23 CMU_VDAC_SELECT_HFRCOEM23 + +#define CMU_VDAC0_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM01GRPACLK CMU_VDAC_SELECT_EM01GRPACLK + +#define CMU_VDAC0_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC0CLK_SELECT_EM23GRPACLK CMU_VDAC_SELECT_EM23GRPACLK + +#if (VDAC_COUNT > 1) +#define CMU_VDAC1_SELECT_FSRCO \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_FSRCO CMU_VDAC1_SELECT_FSRCO + +#define CMU_VDAC1_SELECT_HFRCOEM23 \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_HFRCOEM23 CMU_VDAC1_SELECT_HFRCOEM23 + +#define CMU_VDAC1_SELECT_EM01GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM01GRPACLK CMU_VDAC1_SELECT_EM01GRPACLK + +#define CMU_VDAC1_SELECT_EM23GRPACLK \ + do { \ + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) \ + | CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_VDAC1CLK_SELECT_EM23GRPACLK CMU_VDAC1_SELECT_EM23GRPACLK +#endif /* VDAC_COUNT > 1 */ +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +#define CMU_PCNT0_SELECT_EM23GRPACLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_EM23GRPACLK CMU_PCNT0_SELECT_EM23GRPACLK + +#define CMU_PCNT0_SELECT_PCNTEXTCLK \ + do { \ + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) \ + | CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; \ + } while (0) + +#define CMU_PCNT0CLK_SELECT_PCNTEXTCLK CMU_PCNT0_SELECT_PCNTEXTCLK +#endif /* PCNT_PRESENT */ + +#if defined(LESENSE_PRESENT) +#define CMU_LESENSEHFCLK_SELECT_FSRCO \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; \ + } while (0) + +#define CMU_LESENSEHFCLK_SELECT_HFRCOEM23 \ + do { \ + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) \ + | CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; \ + } while (0) +#endif /* LESENSE_PRESENT */ + +#if defined(USB_PRESENT) +#define CMU_USB_SELECT_USBPLL0 \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_USBPLL0; \ + } while (0) + +#define CMU_USB_SELECT_LFXO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFXO; \ + } while (0) + +#define CMU_USB_SELECT_LFRCO \ + do { \ + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) \ + | CMU_USB0CLKCTRL_CLKSEL_LFRCO; \ + } while (0) +#endif /* USB_PRESENT */ + +#elif defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_0) + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void); + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @param[in]osc + * Reference to a low-frequency oscillator. One of the following values is valid: + * - cmuOsc_LFXO + * - cmuOsc_LFRCO + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void); + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void); + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void); +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void); +#endif + +#define CMU_HF_SELECT_LFXO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFXO); \ + } while (0) + +#define CMU_HF_SELECT_LFRCO \ + do { \ + sli_em_cmu_HFClockSelectLFOsc((uint8_t)cmuOsc_LFRCO); \ + } while (0) + +#define CMU_HF_SELECT_HFXO \ + do { \ + sli_em_cmu_HFClockSelectHFXO(); \ + } while (0) + +#define CMU_HF_SELECT_HFRCO \ + do { \ + sli_em_cmu_HFClockSelectHFRCO(); \ + } while (0) + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +#define CMU_HF_SELECT_USHFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +#define CMU_HF_SELECT_HFRCODIV2 \ + do { \ + sli_em_cmu_HFClockSelectHFRCODIV2(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +#define CMU_HF_SELECT_CLKIN0 \ + do { \ + sli_em_cmu_HFClockSelectCLKIN0(); \ + } while (0) +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +#define CMU_HF_SELECT_USHFRCO \ + do { \ + sli_em_cmu_HFClockSelectUSHFRCO(); \ + } while (0) +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_DISABLED; \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFXO; \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_LFRCO; \ + } while (0) + +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFA_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFACLKSEL = _CMU_LFACLKSEL_LFA_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_DISABLED; \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFXO; \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_LFRCO; \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigHFClock(); \ + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_HFCLKLE; \ + } while (0) + +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFB_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFBCLKSEL = _CMU_LFBCLKSEL_LFB_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ + +#if defined(_CMU_LFCCLKSEL_MASK) +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_DISABLED; \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFXO; \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_LFRCO; \ + } while (0) + +#define CMU_LFC_SELECT_ULFRCO \ + do { \ + CMU->LFCCLKSEL = _CMU_LFCCLKSEL_LFC_ULFRCO; \ + } while (0) + +#endif /* _CMU_LFCCLKSEL_MASK */ + +#define CMU_LFE_SELECT_DISABLED \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_DISABLED; \ + } while (0) + +#define CMU_LFE_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFXO; \ + } while (0) + +#define CMU_LFE_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_LFRCO; \ + } while (0) + +#define CMU_LFE_SELECT_ULFRCO \ + do { \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_ULFRCO; \ + } while (0) + +#if defined(CMU_OSCENCMD_PLFRCOEN) +#define CMU_LFE_SELECT_PLFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); \ + CMU->LFECLKSEL = _CMU_LFECLKSEL_LFE_PLFRCO; \ + } while (0) +#endif /* CMU_OSCENCMD_PLFRCOEN */ +#endif /* _SILICON_LABS_32B_SERIES_1 */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_CMU_LFCLKSEL_LFAE_MASK) +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFAE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFA_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFXO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_LFRCO << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#define CMU_LFA_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) +#define CMU_LFA_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) \ + | (_CMU_LFCLKSEL_LFA_DISABLED << _CMU_LFCLKSEL_LFA_SHIFT); \ + } while (0) +#endif /* CMU_LFA_SELECT_HFCLKLE */ +#endif /* _CMU_LFCLKSEL_LFAE_MASK */ + +#if defined(_CMU_LFCLKSEL_LFBE_MASK) +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (0 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL \ + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT) \ + | (1 << _CMU_LFCLKSEL_LFBE_SHIFT); \ + } while (0) +#endif + +#else +#define CMU_LFB_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFXO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_LFRCO << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#define CMU_LFB_SELECT_HFCLKLE \ + do { \ + sli_em_cmu_SetHFLEConfigSystemCoreClock(); \ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) + +#if defined(CMU_LFCLKSEL_LFBE_ULFRCO) +#define CMU_LFB_SELECT_ULFRCO \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) \ + | (_CMU_LFCLKSEL_LFB_DISABLED << _CMU_LFCLKSEL_LFB_SHIFT); \ + } while (0) +#endif /* CMU_LFCLKSEL_LFBE_ULFRCO */ +#endif /* _CMU_LFCLKSEL_LFBE_MASK */ + +#define CMU_LFC_SELECT_DISABLED \ + do { \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_DISABLED << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFXO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) + +#define CMU_LFC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) \ + | (_CMU_LFCLKSEL_LFC_LFRCO << _CMU_LFCLKSEL_LFC_SHIFT); \ + } while (0) +#endif /* _SILICON_LABS_32B_SERIES_0 */ + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; \ + } while (0) +#endif /* _CMU_DBGCLKSEL_DBG_MASK */ + +#if defined(CMU_CTRL_DBGCLK) +#define CMU_DBG_SELECT_AUXHFRCO \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_AUXHFRCO; \ + } while (0) + +#define CMU_DBG_SELECT_HFCLK \ + do { \ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) \ + | CMU_CTRL_DBGCLK_HFCLK; \ + } while (0) +#endif /* CMU_CTRL_DBGCLK */ + +#if defined(USB_PRESENT) && defined(_CMU_HFCORECLKEN0_USBC_MASK) +#define CMU_USBC_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) {} \ + } while (0) + +#define CMU_USBC_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) {} \ + } while (0) + +#if defined(CMU_STATUS_USBCHFCLKSEL) +#define CMU_USBC_SELECT_HFCLK \ + do { \ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; \ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) {} \ + } while (0) +#endif /* CMU_STATUS_USBCHFCLKSEL */ + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) +#define CMU_USBC_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; \ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) {} \ + } while (0) +#endif /* CMU_CMD_USBCCLKSEL_USHFRCO */ +#endif /* USB_PRESENT && _CMU_HFCORECLKEN0_USBC_MASK */ + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +#define CMU_ADC0ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_DISABLED << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFXO << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC0ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC0CLKSEL_MASK */ + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) +#define CMU_ADC1ASYNC_SELECT_DISABLED \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_DISABLED << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFXO << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) + +#define CMU_ADC1ASYNC_SELECT_HFSRCCLK \ + do { \ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) \ + | (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_ADCCTRL_ADC1CLKSEL_MASK */ + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) +#define CMU_SDIOREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_HFXO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) + +#define CMU_SDIOREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) \ + | (_CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_SDIOCTRL_SDIOCLKSEL_MASK */ + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) +#define CMU_QSPI0REF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_HFXO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_AUXHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) + +#define CMU_QSPI0REF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) \ + | (_CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_QSPICTRL_QSPI0CLKSEL_MASK */ + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) +#define CMU_USBR_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_USHFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFXOX2 \ + do { \ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); \ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFXOX2 << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_HFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFXO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) + +#define CMU_USBR_SELECT_LFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); \ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) \ + | (_CMU_USBCTRL_USBCLKSEL_LFRCO << _CMU_USBCTRL_USBCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_USBCTRL_USBCLKSEL_MASK */ + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) +#define CMU_PDMREF_SELECT_USHFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_USHFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFXO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFXO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) + +#define CMU_PDMREF_SELECT_HFRCO \ + do { \ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); \ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) \ + | (_CMU_PDMCTRL_PDMCLKSEL_HFRCO << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); \ + } while (0) +#endif /* _CMU_PDMCTRL_PDMCLKSEL_MASK */ +#endif /* _SILICON_LABS_32B_SERIES_2 */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_EM_CMU_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c index fef386c..3bf0608 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_burtc.c @@ -1,431 +1,431 @@ -/***************************************************************************//** - * @file - * @brief Backup Real Time Counter (BURTC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_burtc.h" -#if defined(BURTC_PRESENT) - -/***************************************************************************//** - * @addtogroup burtc BURTC - Backup RTC - * @brief Backup Real Time Counter (BURTC) Peripheral API - * @details - * This module contains functions to control the BURTC peripheral of Silicon - * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all - * energy modes. The Backup RTC is also available when the system is in backup - * mode. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/***************************************************************************//** - * @brief Convert dividend to a prescaler logarithmic value. Only works for even - * numbers equal to 2^n. - * @param[in] div Unscaled dividend, - * @return Base 2 logarithm of input, as used by fixed prescalers. - ******************************************************************************/ -__STATIC_INLINE uint32_t divToLog2(uint32_t div) -{ - uint32_t log2; - - /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ - EFM_ASSERT((div > 0UL) && (div <= 32768UL)); - - /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ - log2 = (31UL - __CLZ(div)); - - return log2; -} - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to low frequency domain to complete. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void regSync(uint32_t mask) -{ -#if defined(_BURTC_FREEZE_MASK) - /* Avoid deadlock if modifying the same register twice when freeze mode is - activated or when a clock is not selected for the BURTC. If a clock is - not selected, then the sync is done once the clock source is set. */ - if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) - || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) - || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { - return; - } -#endif - - /* Wait for any pending previous write operation to complete */ - /* in low frequency domain. This is only required for the Gecko Family. */ - while ((BURTC->SYNCBUSY & mask) != 0U) { - } -} -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief Initialize BURTC. - * - * @details - * Configures the BURTC peripheral. - * - * @note - * Before initialization, BURTC module must first be enabled by clearing the - * reset bit in the RMU, i.e., - * @verbatim - * RMU_ResetControl(rmuResetBU, rmuResetModeClear); - * @endverbatim - * Compare channel 0 must be configured outside this function, before - * initialization if enable is set to true. The counter will always be reset. - * - * @param[in] burtcInit - * A pointer to the BURTC initialization structure. - ******************************************************************************/ -void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - uint32_t ctrl; - uint32_t presc; - - /* Check initializer structure integrity. */ - EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); - /* Clock divider must be between 1 and 128, really on the form 2^n. */ - EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); - - /* Ignored compare bits during low power operation must be less than 7. */ - /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ - EFM_ASSERT(burtcInit->lowPowerComp <= 6); - /* You cannot enable the BURTC if mode is set to disabled. */ - EFM_ASSERT((burtcInit->enable == false) - || ((burtcInit->enable == true) - && (burtcInit->mode != burtcModeDisable))); - /* Low power mode is only available with LFRCO or LFXO as clock source. */ - EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) - || ((burtcInit->clkSel == burtcClkSelULFRCO) - && (burtcInit->lowPowerMode == burtcLPDisable))); - - /* Calculate a prescaler value from the clock divider input. */ - /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of - value 1 will select a 2 kHz ULFRCO clock, while any other value will - select a 1 kHz ULFRCO clock source. */ - presc = divToLog2(burtcInit->clkDiv); - - /* Make sure all registers are updated simultaneously. */ - if (burtcInit->enable) { - BURTC_FreezeEnable(true); - } - - /* Modification of LPMODE register requires sync with potential ongoing - * register updates in LF domain. */ - regSync(BURTC_SYNCBUSY_LPMODE); - - /* Configure low power mode. */ - BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); - - /* New configuration. */ - ctrl = (BURTC_CTRL_RSTEN - | (burtcInit->mode) - | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) - | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) - | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) - | (presc << _BURTC_CTRL_PRESC_SHIFT) - | (burtcInit->clkSel) - | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); - - /* Clear interrupts. */ - BURTC_IntClear(0xFFFFFFFF); - - /* Set the new configuration. */ - BURTC->CTRL = ctrl; - - /* Enable BURTC and counter. */ - if (burtcInit->enable) { - /* To enable BURTC counter, disable reset. */ - BURTC_Enable(true); - - /* Clear freeze. */ - BURTC_FreezeEnable(false); - } -#elif defined(_SILICON_LABS_32B_SERIES_2) - uint32_t presc; - - presc = divToLog2(burtcInit->clkDiv); - - if (BURTC->EN != 0U) { - BURTC_SyncWait(); - } - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_SYNCBUSY_EN_MASK) - regSync(BURTC_SYNCBUSY_EN); -#elif defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - - BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) - | ((burtcInit->compare0Top ? 1UL : 0UL) << _BURTC_CFG_COMPTOP_SHIFT) - | ((burtcInit->debugRun ? 1UL : 0UL) << _BURTC_CFG_DEBUGRUN_SHIFT); - BURTC->EM4WUEN = ((burtcInit->em4comp ? 1UL : 0UL) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) - | ((burtcInit->em4overflow ? 1UL : 0UL) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); - BURTC->EN_SET = BURTC_EN_EN; - if (burtcInit->start) { - BURTC_Start(); - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Enable or Disable BURTC peripheral. - * - * @param[in] enable - * true to enable, false to disable. - ******************************************************************************/ -void BURTC_Enable(bool enable) -{ -#if defined(_BURTC_SYNCBUSY_EN_MASK) - regSync(BURTC_SYNCBUSY_EN); -#endif - - if ((BURTC->EN == 0U) && !enable) { - /* Trying to disable BURTC when it's already disabled */ - return; - } - - if (BURTC->EN != 0U) { - /* Modifying the enable bit while synchronization is active will BusFault */ - BURTC_SyncWait(); - } - - if (enable) { - BURTC->EN_SET = BURTC_EN_EN; - } else { - BURTC_Stop(); - BURTC_SyncWait(); /* Wait for the stop to synchronize */ - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - } -} -#elif defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Enable or Disable BURTC peripheral reset and start counter - * @param[in] enable - * If true; asserts reset to BURTC, halts counter, if false; deassert reset - ******************************************************************************/ -void BURTC_Enable(bool enable) -{ - /* Note! If mode is disabled, BURTC counter will not start */ - EFM_ASSERT(((enable == true) - && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) - != BURTC_CTRL_MODE_DISABLE)) - || (enable == false)); - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); -} -#endif - -/***************************************************************************//** - * @brief Set BURTC compare channel. - * - * @param[in] comp Compare the channel index, must be 0 for current devices. - * - * @param[in] value New compare value. - ******************************************************************************/ -void BURTC_CompareSet(unsigned int comp, uint32_t value) -{ - (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ - - EFM_ASSERT(comp == 0U); - -#if defined(_BURTC_COMP0_MASK) - /* Modification of COMP0 register requires sync with potential ongoing - * register updates in LF domain. */ - regSync(BURTC_SYNCBUSY_COMP0); - - /* Configure compare channel 0/. */ - BURTC->COMP0 = value; -#else - /* Wait for last potential write to complete. */ - regSync(BURTC_SYNCBUSY_COMP); - - /* Configure compare channel 0 */ - BURTC->COMP = value; - regSync(BURTC_SYNCBUSY_COMP); -#endif -} - -/***************************************************************************//** - * @brief Get the BURTC compare value. - * - * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. - * - * @return The currently configured value for this compare channel. - ******************************************************************************/ -uint32_t BURTC_CompareGet(unsigned int comp) -{ - (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ - - EFM_ASSERT(comp == 0U); -#if defined(_BURTC_COMP0_MASK) - return BURTC->COMP0; -#else - return BURTC->COMP; -#endif -} - -/***************************************************************************//** - * @brief Reset counter - ******************************************************************************/ -void BURTC_CounterReset(void) -{ -#if defined(_BURTC_CTRL_MASK) - /* Set and clear reset bit */ - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); - BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); -#else - BURTC_Stop(); - BURTC->CNT = 0U; - BURTC_Start(); -#endif -} - -/***************************************************************************//** - * @brief - * Restore BURTC to reset state. - * @note - * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. - * LOCK will not be reset to default value, as this will disable access - * to core BURTC registers. - ******************************************************************************/ -void BURTC_Reset(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_0) - bool buResetState; - - /* Read reset state, set reset, and restore state. */ - buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); - BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); - BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); -#elif defined(_SILICON_LABS_32B_SERIES_2) - if (BURTC->EN != 0U) { - BURTC_SyncWait(); - } - BURTC->EN_SET = BURTC_EN_EN; - BURTC_Stop(); - BURTC->CNT = 0x0; - BURTC->PRECNT = 0x0; - BURTC->COMP = 0x0; - BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; - BURTC->IEN = _BURTC_IEN_RESETVALUE; - BURTC->IF_CLR = _BURTC_IF_MASK; - /* Wait for all values to synchronize. BusFaults can happen if we don't - * do this before the enable bit is cleared. */ - BURTC_SyncWait(); - BURTC->EN_CLR = BURTC_EN_EN; -#if defined(_BURTC_SYNCBUSY_EN_MASK) - while (BURTC->SYNCBUSY != 0U) { - // Wait for the EN=0 to synchronize - } -#elif defined(_BURTC_EN_DISABLING_MASK) - while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - BURTC->CFG = _BURTC_CFG_RESETVALUE; -#endif -} - -#if defined(_BURTC_CTRL_MASK) -/***************************************************************************//** - * @brief - * Get the clock frequency of the BURTC. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t BURTC_ClockFreqGet(void) -{ - uint32_t clkSel; - uint32_t clkDiv; - uint32_t frequency; - - clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; - clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; - - switch (clkSel) { - /** Ultra-low frequency (1 kHz) clock. */ - case BURTC_CTRL_CLKSEL_ULFRCO: - if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { - frequency = 2000; /* 2 kHz when clock divisor is 1. */ - } else { - frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different - from 1. */ - } - break; - - /** Low-frequency RC oscillator. */ - case BURTC_CTRL_CLKSEL_LFRCO: - frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ - break; - - /** Low-frequency crystal oscillator. */ - case BURTC_CTRL_CLKSEL_LFXO: - frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ - break; - - default: - /* No clock selected for BURTC. */ - frequency = 0; - } - return frequency; -} -#endif - -/** @} (end addtogroup burtc) */ - -#endif /* BURTC_PRESENT */ +/***************************************************************************//** + * @file + * @brief Backup Real Time Counter (BURTC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_burtc.h" +#if defined(BURTC_PRESENT) + +/***************************************************************************//** + * @addtogroup burtc BURTC - Backup RTC + * @brief Backup Real Time Counter (BURTC) Peripheral API + * @details + * This module contains functions to control the BURTC peripheral of Silicon + * Labs 32-bit MCUs. The Backup Real Time Counter allows timekeeping in all + * energy modes. The Backup RTC is also available when the system is in backup + * mode. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/***************************************************************************//** + * @brief Convert dividend to a prescaler logarithmic value. Only works for even + * numbers equal to 2^n. + * @param[in] div Unscaled dividend, + * @return Base 2 logarithm of input, as used by fixed prescalers. + ******************************************************************************/ +__STATIC_INLINE uint32_t divToLog2(uint32_t div) +{ + uint32_t log2; + + /* Prescaler accepts an argument of 128 or less, valid values being 2^n. */ + EFM_ASSERT((div > 0UL) && (div <= 32768UL)); + + /* Count leading zeroes and "reverse" result, Cortex-M3 intrinsic. */ + log2 = (31UL - __CLZ(div)); + + return log2; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(uint32_t mask) +{ +#if defined(_BURTC_FREEZE_MASK) + /* Avoid deadlock if modifying the same register twice when freeze mode is + activated or when a clock is not selected for the BURTC. If a clock is + not selected, then the sync is done once the clock source is set. */ + if ((BURTC->FREEZE & BURTC_FREEZE_REGFREEZE) + || ((BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK) == BURTC_CTRL_CLKSEL_NONE) + || ((BURTC->CTRL & _BURTC_CTRL_RSTEN_MASK) == BURTC_CTRL_RSTEN)) { + return; + } +#endif + + /* Wait for any pending previous write operation to complete */ + /* in low frequency domain. This is only required for the Gecko Family. */ + while ((BURTC->SYNCBUSY & mask) != 0U) { + } +} +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief Initialize BURTC. + * + * @details + * Configures the BURTC peripheral. + * + * @note + * Before initialization, BURTC module must first be enabled by clearing the + * reset bit in the RMU, i.e., + * @verbatim + * RMU_ResetControl(rmuResetBU, rmuResetModeClear); + * @endverbatim + * Compare channel 0 must be configured outside this function, before + * initialization if enable is set to true. The counter will always be reset. + * + * @param[in] burtcInit + * A pointer to the BURTC initialization structure. + ******************************************************************************/ +void BURTC_Init(const BURTC_Init_TypeDef *burtcInit) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + uint32_t ctrl; + uint32_t presc; + + /* Check initializer structure integrity. */ + EFM_ASSERT(burtcInit != (BURTC_Init_TypeDef *) 0); + /* Clock divider must be between 1 and 128, really on the form 2^n. */ + EFM_ASSERT((burtcInit->clkDiv >= 1) && (burtcInit->clkDiv <= 128)); + + /* Ignored compare bits during low power operation must be less than 7. */ + /* Note! Giant Gecko revision C errata, do NOT use LPCOMP=7. */ + EFM_ASSERT(burtcInit->lowPowerComp <= 6); + /* You cannot enable the BURTC if mode is set to disabled. */ + EFM_ASSERT((burtcInit->enable == false) + || ((burtcInit->enable == true) + && (burtcInit->mode != burtcModeDisable))); + /* Low power mode is only available with LFRCO or LFXO as clock source. */ + EFM_ASSERT((burtcInit->clkSel != burtcClkSelULFRCO) + || ((burtcInit->clkSel == burtcClkSelULFRCO) + && (burtcInit->lowPowerMode == burtcLPDisable))); + + /* Calculate a prescaler value from the clock divider input. */ + /* Note! If clock select (clkSel) is ULFRCO, a clock divisor (clkDiv) of + value 1 will select a 2 kHz ULFRCO clock, while any other value will + select a 1 kHz ULFRCO clock source. */ + presc = divToLog2(burtcInit->clkDiv); + + /* Make sure all registers are updated simultaneously. */ + if (burtcInit->enable) { + BURTC_FreezeEnable(true); + } + + /* Modification of LPMODE register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_LPMODE); + + /* Configure low power mode. */ + BURTC->LPMODE = (uint32_t) (burtcInit->lowPowerMode); + + /* New configuration. */ + ctrl = (BURTC_CTRL_RSTEN + | (burtcInit->mode) + | (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) + | (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) + | (burtcInit->lowPowerComp << _BURTC_CTRL_LPCOMP_SHIFT) + | (presc << _BURTC_CTRL_PRESC_SHIFT) + | (burtcInit->clkSel) + | (burtcInit->timeStamp << _BURTC_CTRL_BUMODETSEN_SHIFT)); + + /* Clear interrupts. */ + BURTC_IntClear(0xFFFFFFFF); + + /* Set the new configuration. */ + BURTC->CTRL = ctrl; + + /* Enable BURTC and counter. */ + if (burtcInit->enable) { + /* To enable BURTC counter, disable reset. */ + BURTC_Enable(true); + + /* Clear freeze. */ + BURTC_FreezeEnable(false); + } +#elif defined(_SILICON_LABS_32B_SERIES_2) + uint32_t presc; + + presc = divToLog2(burtcInit->clkDiv); + + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + + BURTC->CFG = (presc << _BURTC_CFG_CNTPRESC_SHIFT) + | ((burtcInit->compare0Top ? 1UL : 0UL) << _BURTC_CFG_COMPTOP_SHIFT) + | ((burtcInit->debugRun ? 1UL : 0UL) << _BURTC_CFG_DEBUGRUN_SHIFT); + BURTC->EM4WUEN = ((burtcInit->em4comp ? 1UL : 0UL) << _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT) + | ((burtcInit->em4overflow ? 1UL : 0UL) << _BURTC_EM4WUEN_OFEM4WUEN_SHIFT); + BURTC->EN_SET = BURTC_EN_EN; + if (burtcInit->start) { + BURTC_Start(); + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral. + * + * @param[in] enable + * true to enable, false to disable. + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ +#if defined(_BURTC_SYNCBUSY_EN_MASK) + regSync(BURTC_SYNCBUSY_EN); +#endif + + if ((BURTC->EN == 0U) && !enable) { + /* Trying to disable BURTC when it's already disabled */ + return; + } + + if (BURTC->EN != 0U) { + /* Modifying the enable bit while synchronization is active will BusFault */ + BURTC_SyncWait(); + } + + if (enable) { + BURTC->EN_SET = BURTC_EN_EN; + } else { + BURTC_Stop(); + BURTC_SyncWait(); /* Wait for the stop to synchronize */ + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } +} +#elif defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Enable or Disable BURTC peripheral reset and start counter + * @param[in] enable + * If true; asserts reset to BURTC, halts counter, if false; deassert reset + ******************************************************************************/ +void BURTC_Enable(bool enable) +{ + /* Note! If mode is disabled, BURTC counter will not start */ + EFM_ASSERT(((enable == true) + && ((BURTC->CTRL & _BURTC_CTRL_MODE_MASK) + != BURTC_CTRL_MODE_DISABLE)) + || (enable == false)); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, (uint32_t) !enable); +} +#endif + +/***************************************************************************//** + * @brief Set BURTC compare channel. + * + * @param[in] comp Compare the channel index, must be 0 for current devices. + * + * @param[in] value New compare value. + ******************************************************************************/ +void BURTC_CompareSet(unsigned int comp, uint32_t value) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); + +#if defined(_BURTC_COMP0_MASK) + /* Modification of COMP0 register requires sync with potential ongoing + * register updates in LF domain. */ + regSync(BURTC_SYNCBUSY_COMP0); + + /* Configure compare channel 0/. */ + BURTC->COMP0 = value; +#else + /* Wait for last potential write to complete. */ + regSync(BURTC_SYNCBUSY_COMP); + + /* Configure compare channel 0 */ + BURTC->COMP = value; + regSync(BURTC_SYNCBUSY_COMP); +#endif +} + +/***************************************************************************//** + * @brief Get the BURTC compare value. + * + * @param[in] comp Compare the channel index value, must be 0 for Giant/Leopard Gecko. + * + * @return The currently configured value for this compare channel. + ******************************************************************************/ +uint32_t BURTC_CompareGet(unsigned int comp) +{ + (void) comp; /* Unused parameter when EFM_ASSERT is undefined. */ + + EFM_ASSERT(comp == 0U); +#if defined(_BURTC_COMP0_MASK) + return BURTC->COMP0; +#else + return BURTC->COMP; +#endif +} + +/***************************************************************************//** + * @brief Reset counter + ******************************************************************************/ +void BURTC_CounterReset(void) +{ +#if defined(_BURTC_CTRL_MASK) + /* Set and clear reset bit */ + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1U); + BUS_RegBitWrite(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0U); +#else + BURTC_Stop(); + BURTC->CNT = 0U; + BURTC_Start(); +#endif +} + +/***************************************************************************//** + * @brief + * Restore BURTC to reset state. + * @note + * Before accessing the BURTC, BURSTEN in RMU->CTRL must be cleared. + * LOCK will not be reset to default value, as this will disable access + * to core BURTC registers. + ******************************************************************************/ +void BURTC_Reset(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_0) + bool buResetState; + + /* Read reset state, set reset, and restore state. */ + buResetState = BUS_RegBitRead(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, 1); + BUS_RegBitWrite(&RMU->CTRL, _RMU_CTRL_BURSTEN_SHIFT, buResetState); +#elif defined(_SILICON_LABS_32B_SERIES_2) + if (BURTC->EN != 0U) { + BURTC_SyncWait(); + } + BURTC->EN_SET = BURTC_EN_EN; + BURTC_Stop(); + BURTC->CNT = 0x0; + BURTC->PRECNT = 0x0; + BURTC->COMP = 0x0; + BURTC->EM4WUEN = _BURTC_EM4WUEN_RESETVALUE; + BURTC->IEN = _BURTC_IEN_RESETVALUE; + BURTC->IF_CLR = _BURTC_IF_MASK; + /* Wait for all values to synchronize. BusFaults can happen if we don't + * do this before the enable bit is cleared. */ + BURTC_SyncWait(); + BURTC->EN_CLR = BURTC_EN_EN; +#if defined(_BURTC_SYNCBUSY_EN_MASK) + while (BURTC->SYNCBUSY != 0U) { + // Wait for the EN=0 to synchronize + } +#elif defined(_BURTC_EN_DISABLING_MASK) + while (BURTC->EN & _BURTC_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + BURTC->CFG = _BURTC_CFG_RESETVALUE; +#endif +} + +#if defined(_BURTC_CTRL_MASK) +/***************************************************************************//** + * @brief + * Get the clock frequency of the BURTC. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t BURTC_ClockFreqGet(void) +{ + uint32_t clkSel; + uint32_t clkDiv; + uint32_t frequency; + + clkSel = BURTC->CTRL & _BURTC_CTRL_CLKSEL_MASK; + clkDiv = (BURTC->CTRL & _BURTC_CTRL_PRESC_MASK) >> _BURTC_CTRL_PRESC_SHIFT; + + switch (clkSel) { + /** Ultra-low frequency (1 kHz) clock. */ + case BURTC_CTRL_CLKSEL_ULFRCO: + if (_BURTC_CTRL_PRESC_DIV1 == clkDiv) { + frequency = 2000; /* 2 kHz when clock divisor is 1. */ + } else { + frequency = SystemULFRCOClockGet(); /* 1 kHz when divisor is different + from 1. */ + } + break; + + /** Low-frequency RC oscillator. */ + case BURTC_CTRL_CLKSEL_LFRCO: + frequency = SystemLFRCOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + /** Low-frequency crystal oscillator. */ + case BURTC_CTRL_CLKSEL_LFXO: + frequency = SystemLFXOClockGet() / (1 << clkDiv); /* freq=32768/2^clkDiv */ + break; + + default: + /* No clock selected for BURTC. */ + frequency = 0; + } + return frequency; +} +#endif + +/** @} (end addtogroup burtc) */ + +#endif /* BURTC_PRESENT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c index 1f37e34..5d91602 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_cmu.c @@ -1,11811 +1,11811 @@ -/***************************************************************************//** - * @file - * @brief Clock management unit (CMU) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_cmu.h" -#if defined(CMU_PRESENT) - -#include -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "sl_common.h" -#include "em_emu.h" -#include "em_gpio.h" -#include "em_system.h" -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -#include "em_msc.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -/***************************************************************************//** - * @addtogroup cmu CMU - Clock Management Unit - * @brief Clock management unit (CMU) Peripheral API - * @details - * This module contains functions for the CMU peripheral of Silicon Labs 32-bit - * MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock - * multiplexers, pre-scalers, calibration modules and wait-states. - * @{ - ******************************************************************************/ -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -// Maximum allowed core frequency vs. wait-states on flash accesses. -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 40000000UL - -// Maximum allowed core frequency vs. wait-states on sram accesses. -#define CMU_MAX_SRAM_FREQ_0WS 50000000UL -#define CMU_MAX_SRAM_FREQ_1WS 80000000UL - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 40000000UL -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -// Maximum allowed core frequency vs. wait-states and vscale on flash accesses. -#define CMU_MAX_FREQ_0WS_1V1 40000000UL - -#define CMU_MAX_FREQ_0WS_1V0 20000000UL -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define CMU_MAX_FREQ_0WS_1V1 25000000UL -#define CMU_MAX_FREQ_1WS_1V1 50000000UL -#define CMU_MAX_FREQ_2WS_1V1 75000000UL -#else - #warning "MCU flash wait states not supported" -#endif - -// Maximum allowed PCLK frequency. -#define CMU_MAX_PCLK_FREQ 50000000UL - -// Maximum allowed RHCLK frequency. -#define CMU_MAX_RHCLK_FREQ 40000000UL - -#if defined(EMU_VSCALE_EM01_PRESENT) -// This macro is intended to be used as input to CMU_UpdateWaitStates() -#define VSCALE_DEFAULT (2 - (int)EMU_VScaleGet()) -#else -#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE -#endif - -#if defined(PLFRCO_PRESENT) -// Typical frequency for HFXO as recommanded in the datasheets. -// see AN0016: Oscillator Design Considerations -// -// Recommended for most wireless applications -// to meet transceiver electrical specifications -#define XTAL_38M4 38400000UL -// Recommended for implementing Z-Wave devices -#define XTAL_39M0 39000000UL -// High Precision mode calibration Counts for 38.4MHz -#define LFRCO_NOMCAL_XTAL_38M4 _LFRCO_NOMCAL_RESETVALUE -#define LFRCO_NOMCALINV_XTAL_38M4 _LFRCO_NOMCALINV_RESETVALUE -// High Precision mode calibration Counts for 39.0MHz. -#define LFRCO_NOMCAL_XTAL_39M0 0x0005CFBBUL -#define LFRCO_NOMCALINV_XTAL_39M0 0x0000581AUL -#endif - -#define PLL0_USB_OUTPUT_FREQ 48000000UL - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -// Table of HFRCOCAL values and their associated min/max frequencies and -// optional band enumerator. -static const struct hfrcoCalTableElement{ - uint32_t minFreq; - uint32_t maxFreq; - uint32_t value; - CMU_HFRCODPLLFreq_TypeDef band; -} hfrcoCalTable[] = -{ - // minFreq maxFreq HFRCOCAL value band - { 900000UL, 1080000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, - { 1080000UL, 1300000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1300000UL, 1530000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1530000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 1800000UL, 2150000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, - { 2150000UL, 2600000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 2600000UL, 3050000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 3050000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 3600000UL, 4300000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, - { 4300000UL, 5200000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 5200000UL, 6100000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 6100000UL, 7800000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, - { 7800000UL, 9800000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 9800000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, - { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, - { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, - { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, - { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, - { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, - { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, - { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, - { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, - { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, - { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz }, -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - { 80000000UL, 100000000UL, 0xCCF19F00UL, cmuHFRCODPLLFreq_100M0Hz } -#endif -}; - -static uint16_t lfxo_precision = 0xFFFF; -static uint16_t hfxo_precision = 0xFFFF; - -#define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ - / sizeof(struct hfrcoCalTableElement)) - -// CTUNE delta needed for some series 2 chips. This delta is added to the tuning capacitance on XO. -// The inter-chip buffered crystal sharing feature added from the EFR32xG23 creates an imbalance -// between XI and XO capacitance load internally on the chip. The delta allows to compensate for -// the difference. -#if defined(_SILICON_LABS_32B_SERIES_2) -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -static int8_t ctuneDelta = 40; // Recommendation from analog team to counter the internal chip imbalance. -#else -static int8_t ctuneDelta = 0; -#endif -#endif - -/******************************************************************************* - ************************** LOCAL PROTOTYPES ******************************* - ******************************************************************************/ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -#if defined(PDM_PRESENT) -static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(EUART_PRESENT) -static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(EUSART_PRESENT) -static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#endif -#if defined(LCD_PRESENT) -static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(VDAC_PRESENT) -static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if (VDAC_COUNT > 1) -static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#endif -#if defined(PCNT_PRESENT) -static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if defined(LESENSE_PRESENT) -static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -static void rhclkPrescMax(void); -static void rhclkPrescOptimize(void); -#endif -#endif - -#if defined(HFRCOEM23_PRESENT) -static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); -#endif -static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale); -static void flashWaitStateControl(uint32_t coreFreq, int vscale); -static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); -#if defined(IADC_PRESENT) -static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void pclkDivMax(void); -static void pclkDivOptimize(void); -#if defined(RTCC_PRESENT) -static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#elif defined(SYSRTC_PRESENT) -static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void waitStateMax(void); -static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if WDOG_COUNT > 1 -static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#if defined(USB_PRESENT) -static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); -#endif -/** @endcond */ - -// The following code is common for all SERIES_2 configurations. - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Calibrate an oscillator. - * - * @details - * Run a calibration of a selectable reference clock againt HCLK. Please - * refer to the reference manual, CMU chapter, for further details. - * - * @note - * This function will not return until calibration measurement is completed. - * - * @param[in] cycles - * The number of HCLK cycles to run calibration. Increasing this number - * increases precision, but the calibration will take more time. - * - * @param[in] ref - * The reference clock used to compare against HCLK. - * - * @return - * The number of ticks the selected reference clock ticked while running - * cycles ticks of the HCLK clock. - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) -{ - // Check for cycle count overflow -#if defined(_CMU_CALCTRL_CALTOP_MASK) - EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK - >> _CMU_CALCTRL_CALTOP_SHIFT)); -#elif defined(_CMU_CALTOP_CALTOP_MASK) - EFM_ASSERT(cycles <= (_CMU_CALTOP_CALTOP_MASK - >> _CMU_CALTOP_CALTOP_SHIFT)); -#endif - - CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); - CMU_CalibrateStart(); - return CMU_CalibrateCountGet(); -} - -/***************************************************************************//** - * @brief - * Configure clock calibration. - * - * @details - * Configure a calibration for a selectable clock source against another - * selectable reference clock. - * Refer to the reference manual, CMU chapter, for further details. - * - * @note - * After configuration, a call to @ref CMU_CalibrateStart() is required, and - * the resulting calibration value can be read with the - * @ref CMU_CalibrateCountGet() function call. - * - * @param[in] downCycles - * The number of downSel clock cycles to run calibration. Increasing this - * number increases precision, but the calibration will take more time. - * - * @param[in] downSel - * The clock which will be counted down downCycles cycles. - * - * @param[in] upSel - * The reference clock, the number of cycles generated by this clock will - * be counted and added up, the result can be given with the - * @ref CMU_CalibrateCountGet() function call. - ******************************************************************************/ -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, - CMU_Select_TypeDef upSel) -{ - // Keep untouched configuration settings - uint32_t calCtrl = CMU->CALCTRL - & ~(_CMU_CALCTRL_UPSEL_MASK - | _CMU_CALCTRL_DOWNSEL_MASK -#if defined(_CMU_CALCTRL_CALTOP_MASK) - | _CMU_CALCTRL_CALTOP_MASK -#endif - ); - - // Check for cycle count overflow -#if defined(_CMU_CALCTRL_CALTOP_MASK) - EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK - >> _CMU_CALCTRL_CALTOP_SHIFT)); - calCtrl |= downCycles; -#elif defined(_CMU_CALTOP_CALTOP_MASK) - EFM_ASSERT(downCycles <= (_CMU_CALTOP_CALTOP_MASK >> _CMU_CALTOP_CALTOP_SHIFT)); - CMU->CALTOP = downCycles << _CMU_CALTOP_CALTOP_SHIFT; -#endif - - // Set down counting clock source selector - switch (downSel) { - case cmuSelect_HCLK: - calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; - break; - - case cmuSelect_PRS: - calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; - break; - - case cmuSelect_HFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; - break; - - case cmuSelect_LFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; - break; - - case cmuSelect_HFRCODPLL: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; - break; - - case cmuSelect_ULFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - break; - - default: - EFM_ASSERT(false); - break; - } - - // Set up counting clock source selector - switch (upSel) { - case cmuSelect_PRS: - calCtrl |= CMU_CALCTRL_UPSEL_PRS; - break; - - case cmuSelect_HFXO: - calCtrl |= CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuSelect_LFXO: - calCtrl |= CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuSelect_HFRCODPLL: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; - break; - - case cmuSelect_ULFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - break; - - default: - EFM_ASSERT(false); - break; - } - - CMU->CALCTRL = calCtrl; -} - -/***************************************************************************//** - * @brief - * Get calibration count value. - * - * @note - * If continuous calibration mode is active, calibration busy will almost - * always be off, and reading the value will be just needed, where the normal - * case would be that this function call has been triggered by the CALRDY - * interrupt flag. - * - * @return - * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) - * in the period of DOWNSEL oscillator clock cycles configured by a previous - * write operation to CMU->CALCNT. - ******************************************************************************/ -uint32_t CMU_CalibrateCountGet(void) -{ - // Wait until calibration completes, UNLESS continuous calibration mode is on - if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { - // Wait until calibration completes - while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { - } - } - return CMU->CALCNT; -} - -/***************************************************************************//** - * @brief - * Direct a clock to a GPIO pin. - * - * @param[in] clkNo - * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2. - * - * @param[in] sel - * Select clock source. - * - * @param[in] clkDiv - * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is - * selected as clock source. - * - * @param[in] port - * GPIO port. - * - * @param[in] pin - * GPIO pin. - * - * @note - * Refer to the reference manual and the datasheet for details on which - * GPIO port/pins that are available. - ******************************************************************************/ -void CMU_ClkOutPinConfig(uint32_t clkNo, - CMU_Select_TypeDef sel, - CMU_ClkDiv_TypeDef clkDiv, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - uint32_t tmp = 0U, mask; - - EFM_ASSERT(pin <= 15U); - - switch (clkNo) { - case 0: - case 1: - EFM_ASSERT((port == 2U) || (port == 3U)); - break; - case 2: - EFM_ASSERT((port == 0U) || (port == 1U)); - break; - default: - EFM_ASSERT(false); - break; - } - - switch (sel) { - case cmuSelect_Disabled: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; - break; - - case cmuSelect_FSRCO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; - break; - - case cmuSelect_HFXO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; - break; - - case cmuSelect_HFRCODPLL: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; - break; -#endif - - case cmuSelect_EXPCLK: - EFM_ASSERT((clkDiv > 0U) && (clkDiv <= 32U)); - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; - break; - - case cmuSelect_LFXO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; - break; - - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; - break; - - case cmuSelect_HCLK: - tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; - break; - - default: - EFM_ASSERT(false); - break; - } - - mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK - << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); - tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; - - if (sel == cmuSelect_EXPCLK) { - tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; - mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; - } - - CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; - - if (sel == cmuSelect_Disabled) { - GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; - GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); - } else { - GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; - if (clkNo == 0U) { - GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); - } else if (clkNo == 1) { - GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); - } else { - GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) - | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); - } - GPIO_PinModeSet(port, pin, gpioModePushPull, 0); - } -} - -/***************************************************************************//** - * @brief - * Get clock divisor. - * - * @param[in] clock - * Clock point to get divisor for. Notice that not all clock points - * have a divisors. Please refer to CMU overview in reference manual. - * - * @return - * The current clock point divisor. 1 is returned - * if @p clock specifies a clock point without divisor. - ******************************************************************************/ -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - - switch (clock) { - case cmuClock_HCLK: - case cmuClock_CORE: - ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (ret == 2U ) { // Unused value, illegal prescaler - EFM_ASSERT(false); - } -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - if (!((ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV1) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV2) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV4) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV8) - || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV16))) { - // Illegal prescaler - EFM_ASSERT(false); - } -#endif - break; - -#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) - case cmuClock_TRACECLK: - ret = (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_PRESC_MASK) - >> _CMU_TRACECLKCTRL_PRESC_SHIFT; - if (!((ret == _CMU_TRACECLKCTRL_PRESC_DIV1) - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV2) -#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV3) -#endif - || (ret == _CMU_TRACECLKCTRL_PRESC_DIV4))) { - // Illegal prescaler - EFM_ASSERT(false); - } - break; -#endif - - case cmuClock_EXPCLK: - ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) - >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; - break; - - case cmuClock_PCLK: - ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) - >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; - break; - - default: - break; - } - return 1U + ret; -} - -/***************************************************************************//** - * @brief - * Set clock divisor. - * - * @param[in] clock - * Clock point to set divisor for. Notice that not all clock points - * have a divisor, please refer to CMU overview in the reference - * manual. - * - * @param[in] div - * The clock divisor to use. - ******************************************************************************/ -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) -{ -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - bool restoreTrace; -#endif - - switch (clock) { - case cmuClock_HCLK: - case cmuClock_CORE: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U) - || (div == 8U) || (div == 16U)); -#endif - - // Set max wait-states and PCLK divisor while changing core clock - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Set new divisor - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) - | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); - - // Update CMSIS core clock variable and set optimum wait-states - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - break; - -#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) - case cmuClock_TRACECLK: -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; - if (restoreTrace) { - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } -#endif -#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 3U) || (div == 4U)); -#else - EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); -#endif - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_PRESC_MASK) - | ((div - 1U) << _CMU_TRACECLKCTRL_PRESC_SHIFT); -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - if (restoreTrace) { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - break; -#endif - - case cmuClock_EXPCLK: - EFM_ASSERT((div >= 1U) && (div <= 32U)); - CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) - | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); - break; - - case cmuClock_PCLK: - EFM_ASSERT((div == 1U) || (div == 2U)); - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) - | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); - break; - - default: - EFM_ASSERT(false); - break; - } -} - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @details - * Module clocks sre disabled after reset. If a module clock is disabled, the - * registers of that module are not accessible and accessing such registers - * will hardfault the Cortex core. - * - * @param[in] clock - * The clock to enable/disable. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - volatile uint32_t *reg = NULL; - uint32_t bit; - - /* Identify the enable register. */ - if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_NO_EN_REG) { - EFM_ASSERT(false); /* No enable for this clock. */ - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN0_EN_REG) { - reg = &CMU->CLKEN0; - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN1_EN_REG) { - reg = &CMU->CLKEN1; -#if defined(_CMU_CLKEN2_MASK) - } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN2_EN_REG) { - reg = &CMU->CLKEN2; -#endif - } else { -#if defined(CRYPTOACC_PRESENT) - reg = &CMU->CRYPTOACCCLKCTRL; -#else - // No register to enable clock. Possible hard fault exception. - EFM_ASSERT(false); -#endif - } - - /* Get the bit position used to enable/disable. */ - bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; - - /* Set/clear bit as requested. */ - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -/***************************************************************************//** - * @brief - * Get clock frequency for a clock point. - * - * @param[in] clock - * Clock point to fetch frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - - switch (clock) { - case cmuClock_SYSCLK: - ret = SystemSYSCLKGet(); - break; - - case cmuClock_CORE: - case cmuClock_HCLK: - case cmuClock_LDMA: - case cmuClock_GPCRC: - ret = SystemHCLKGet(); - break; - - case cmuClock_EXPCLK: - ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); - break; - - case cmuClock_I2C1: - case cmuClock_PRS: - case cmuClock_PCLK: - case cmuClock_GPIO: - case cmuClock_USART0: - case cmuClock_USART1: - case cmuClock_USART2: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); - break; - - case cmuClock_I2C0: - case cmuClock_LSPCLK: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; - break; - -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(&ret, NULL); - break; -#endif - - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(&ret, NULL); - break; - - case cmuClock_SYSTICK: - sysTickClkGet(&ret, NULL); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: - em23GrpaClkGet(&ret, NULL); - break; - - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: - em4GrpaClkGet(&ret, NULL); - break; - - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(&ret, NULL); - break; - - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(&ret, NULL); - break; - - case cmuClock_DPLLREFCLK: - dpllRefClkGet(&ret, NULL); - break; - - case cmuClock_TRACECLK: - traceClkGet(&ret, NULL); - break; - - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(&ret, NULL); - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} -#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -/***************************************************************************//** - * @brief - * Get clock frequency for a clock point. - * - * @param[in] clock - * Clock point to fetch frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret = 0U; - uint32_t freq = 0U; - - switch (clock) { - case cmuClock_SYSCLK: - ret = SystemSYSCLKGet(); - break; - - case cmuClock_HCLK: - case cmuClock_CORE: - case cmuClock_ICACHE: - case cmuClock_MSC: - case cmuClock_LDMA: - case cmuClock_SMU: -#if defined(RADIOAES_PRESENT) - case cmuClock_RADIOAES: -#endif -#if defined(CRYPTOACC_PRESENT) - case cmuClock_CRYPTOACC: - case cmuClock_CRYPTOAES: - case cmuClock_CRYPTOPK: -#endif -#if defined(MVP_PRESENT) - case cmuClock_MVP: -#endif - ret = SystemHCLKGet(); - break; - - case cmuClock_EXPCLK: - ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); - break; - - case cmuClock_PCLK: -#if defined(USART_PRESENT) - case cmuClock_USART0: -#if USART_COUNT > 1 - case cmuClock_USART1: -#endif -#endif - case cmuClock_I2C1: - case cmuClock_PRS: - case cmuClock_GPIO: - case cmuClock_GPCRC: - case cmuClock_LDMAXBAR: - case cmuClock_SYSCFG: - case cmuClock_DCDC: - case cmuClock_BURAM: - case cmuClock_DPLL0: - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); - break; - - case cmuClock_LSPCLK: - case cmuClock_I2C0: - case cmuClock_AMUXCP0: -#if defined(ACMP_PRESENT) - case cmuClock_ACMP0: -#if ACMP_COUNT > 1 - case cmuClock_ACMP1: -#endif -#endif - ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; - break; - - case cmuClock_TRACECLK: - traceClkGet(&freq, NULL); - ret = freq / CMU_ClockDivGet(cmuClock_TRACECLK); - break; - - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(&ret, NULL); - break; -#if defined(PDM_PRESENT) - case cmuClock_PDM: - case cmuClock_EM01GRPBCLK: - em01GrpbClkGet(&ret, NULL); - break; -#endif -#if defined(EUART_PRESENT) - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - euart0ClkGet(&ret, NULL); - break; -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - eusart0ClkGet(&ret, NULL); - break; -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - em01GrpcClkGet(&ret, NULL); - break; -#endif -#endif - -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(&ret, NULL); - break; -#endif - - case cmuClock_SYSTICK: - sysTickClkGet(&ret, NULL); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - em23GrpaClkGet(&ret, NULL); - break; - - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(&ret, NULL); - break; -#if WDOG_COUNT > 1 - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(&ret, NULL); - break; -#endif -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(&ret, NULL); - break; -#endif -#if defined(SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - sysrtcClkGet(&ret, NULL); - break; -#endif -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - lcdClkGet(&ret, NULL); - break; -#endif -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - vdac0ClkGet(&ret, NULL); - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - vdac1ClkGet(&ret, NULL); - break; -#endif -#endif /* VDAC_PRESENT */ -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - pcnt0ClkGet(&ret, NULL); - break; -#endif -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - lesenseHFClkGet(&ret, NULL); - break; -#endif - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - em4GrpaClkGet(&ret, NULL); - break; - -#if defined(USB_PRESENT) - case cmuClock_USB: - usbClkGet(&ret, NULL); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - return ret; -} -#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -/***************************************************************************//** - * @brief - * Get currently selected reference clock used for a clock branch. - * - * @param[in] clock - * Clock branch to fetch selected ref. clock for. - * - * @return - * Reference clock used for clocking selected branch, #cmuSelect_Error if - * invalid @p clock provided. - ******************************************************************************/ -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef ret = cmuSelect_Error; - - switch (clock) { -// ----------------------------------------------------------------------------- - case cmuClock_SYSCLK: - switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { - case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: - ret = cmuSelect_HFRCODPLL; - break; - - case CMU_SYSCLKCTRL_CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: - ret = cmuSelect_CLKIN0; - break; - - case CMU_SYSCLKCTRL_CLKSEL_FSRCO: - ret = cmuSelect_FSRCO; - break; - -#if defined(RFFPLL_PRESENT) - case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: - ret = cmuSelect_RFFPLLSYS; - break; -#endif - default: - ret = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - break; - -// ----------------------------------------------------------------------------- -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - iadcClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - em01GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- - case cmuClock_SYSTICK: - sysTickClkGet(NULL, &ret); - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - em23GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- - case cmuClock_BURTC: - case cmuClock_EM4GRPACLK: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - em4GrpaClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) - case cmuClock_PDMREF: - case cmuClock_EM01GRPBCLK: - em01GrpbClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - wdog0ClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - wdog1ClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_DPLLREFCLK: - dpllRefClkGet(NULL, &ret); - break; - -// ----------------------------------------------------------------------------- -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) - case cmuClock_TRACECLK: - traceClkGet(NULL, &ret); - break; -#endif - -// ----------------------------------------------------------------------------- -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - euart0ClkGet(NULL, &ret); - break; -#elif defined(EUSART_PRESENT) - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - eusart0ClkGet(NULL, &ret); - break; - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - em01GrpcClkGet(NULL, &ret); - break; -#endif - #endif - -// ----------------------------------------------------------------------------- -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - rtccClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - sysrtcClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - lcdClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - vdac0ClkGet(NULL, &ret); - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - vdac1ClkGet(NULL, &ret); - break; -#endif -#endif -// ----------------------------------------------------------------------------- -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - pcnt0ClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - lesenseHFClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(USB_PRESENT) - case cmuClock_USB: - usbClkGet(NULL, &ret); - break; -#endif -// ----------------------------------------------------------------------------- - default: - EFM_ASSERT(false); - break; - } - return ret; -} - -/***************************************************************************//** - * @brief Performs pre-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPreClockSelect(void) -{ -#if defined(EMU_VSCALE_EM01_PRESENT) - // VSCALE up before changing clock. - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); -#endif - - // Set max wait-states and PCLK divisor while changing core clock. - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif -} - -/***************************************************************************//** - * @brief Performs post-clock-selection operations to initialize the system clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK. - ******************************************************************************/ -void sli_em_cmu_SYSCLKInitPostClockSelect(void) -{ - // Update CMSIS core clock variable and set optimum wait-states. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(EMU_VSCALE_EM01_PRESENT) - // Check if possible to downscale VSCALE setting. - EMU_VScaleEM01ByClock(0, true); -#endif - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif -} - -/***************************************************************************//** - * @brief Sets the HFXO0 FORCEEN bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSCLK and the selected clock source is HFXO. - ******************************************************************************/ -void sli_em_cmu_HFXOSetForceEnable(void) -{ -#if defined(_CMU_CLKEN0_MASK) && defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -} - -/***************************************************************************//** - * @brief This function will set the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENSet(void) -{ -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - - SYSCFG_setSysTicExtClkEnCfgSysTic(); - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} - -/***************************************************************************//** - * @brief This function will clear the SYSCFG->CFGSYSTIC bit. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is SYSTICK. - ******************************************************************************/ -void sli_em_cmu_SYSTICEXTCLKENClear(void) -{ -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - - SYSCFG_clearSysTicExtClkEnCfgSysTic(); - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} - -/***************************************************************************//** - * @brief - * Select reference clock/oscillator used for a clock branch. - * - * @param[in] clock - * Clock branch to select reference clock for. - * - * @param[in] ref - * Reference selected for clocking, please refer to reference manual for - * for details on which reference is available for a specific clock branch. - ******************************************************************************/ -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) -{ - uint32_t tmp = 0U; - bool oscForceEnStatus = false; -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - bool syscfgClkIsOff = false; -#endif -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - bool restoreTrace; -#endif - - switch (clock) { -// ----------------------------------------------------------------------------- - case cmuClock_SYSCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; -#if defined(_CMU_CLKEN0_MASK) -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif -#endif - // Make sure HFXO is enabled. - oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_FSRCO: - tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; - break; - -#if defined(RFFPLL_PRESENT) - case cmuSelect_RFFPLLSYS: - tmp = CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - // VSCALE up before changing clock. - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); -#endif - - // Set max wait-states and PCLK divisor while changing core clock. - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Switch to selected oscillator. - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; - - // Update CMSIS core clock variable and set optimum wait-states. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(EMU_VSCALE_EM01_PRESENT) - // Check if possible to downscale VSCALE setting. - EMU_VScaleEM01ByClock(0, true); -#endif - - // Set optimal PCLK divisor - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - - if (oscForceEnStatus == false) { - switch (ref) { - case cmuSelect_HFXO: - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - break; - - default: - break; - } - } - break; - -// ----------------------------------------------------------------------------- -#if defined(IADC_PRESENT) - case cmuClock_IADC0: - case cmuClock_IADCCLK: - switch (ref) { - case cmuSelect_EM01GRPACLK: - tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_TIMER0: - case cmuClock_TIMER1: - case cmuClock_TIMER2: - case cmuClock_TIMER3: -#if TIMER_COUNT > 4 - case cmuClock_TIMER4: -#endif -#if TIMER_COUNT > 7 - case cmuClock_TIMER5: - case cmuClock_TIMER6: - case cmuClock_TIMER7: -#endif -#if TIMER_COUNT > 9 - case cmuClock_TIMER8: - case cmuClock_TIMER9: -#endif -#if defined(KEYSCAN_PRESENT) - case cmuClock_KEYSCAN: -#endif - case cmuClock_EM01GRPACLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuSelect_HFRCOEM23: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - case cmuSelect_FSRCO: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; - break; - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL - & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -// ----------------------------------------------------------------------------- - case cmuClock_SYSTICK: - switch (ref) { - case cmuSelect_EM23GRPACLK: - case cmuSelect_LFXO: - case cmuSelect_LFRCO: - case cmuSelect_ULFRCO: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSCFG_setSysTicExtClkEnCfgSysTic(); -#else - syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - SYSCFG_setSysTicExtClkEnCfgSysTic(); - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif - SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); - break; - case cmuSelect_HCLK: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - SYSCFG_clearSysTicExtClkEnCfgSysTic(); -#else - syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - SYSCFG_clearSysTicExtClkEnCfgSysTic(); - if (syscfgClkIsOff) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif - SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); - break; - default: - EFM_ASSERT(false); - break; - } - break; - - case cmuClock_LETIMER0: - case cmuClock_EM23GRPACLK: -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - case cmuClock_LESENSECLK: -#endif - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL - & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -// ----------------------------------------------------------------------------- - case cmuClock_BURTC: -#if defined(ETAMPDET_PRESENT) - case cmuClock_ETAMPDET: -#endif - case cmuClock_EM4GRPACLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL - & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; - break; - -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_PDMREF: - case cmuClock_EM01GRPBCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; - break; - - case cmuSelect_HFXO: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; - break; - - case cmuSelect_FSRCO: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; - break; - - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; - break; - - case cmuSelect_Disabled: - tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL - & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_WDOG0: - case cmuClock_WDOG0CLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_HCLKDIV1024: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; - break; - - case cmuSelect_Disabled: - tmp = CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) - | tmp; - break; - -#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_WDOG1: - case cmuClock_WDOG1CLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_HCLKDIV1024: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; - break; - - case cmuSelect_Disabled: - tmp = CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif - -// ----------------------------------------------------------------------------- - case cmuClock_DPLLREFCLK: - switch (ref) { - case cmuSelect_HFXO: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; - break; - - case cmuSelect_LFXO: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_CLKIN0: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; - break; - - case cmuSelect_Disabled: - tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL - & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; - break; - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_TRACECLK: -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; - if (restoreTrace) { - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - switch (ref) { -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - case cmuSelect_HCLK: - tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - case cmuSelect_SYSCLK: - tmp = CMU_TRACECLKCTRL_CLKSEL_SYSCLK; - break; - - case cmuSelect_HFRCODPLLRT: - tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) - case cmuSelect_HFRCOEM23: - tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) - | tmp; -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ - && defined(CoreDebug_DEMCR_TRCENA_Msk) - if (restoreTrace) { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } -#endif - break; -#endif - -#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) -// ----------------------------------------------------------------------------- - case cmuClock_EUART0: - case cmuClock_EUART0CLK: - switch (ref) { - case cmuSelect_EM01GRPACLK: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; - break; - - case cmuSelect_EM23GRPACLK: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - case cmuSelect_Disabled: - tmp = _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#elif defined(EUSART_PRESENT) - case cmuClock_EUSART0: - case cmuClock_EUSART0CLK: - switch (ref) { -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) - case cmuSelect_EM01GRPACLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - case cmuSelect_EM01GRPCCLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) - case cmuSelect_EM23GRPACLK: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) - case cmuSelect_FSRCO: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) - case cmuSelect_HFRCOEM23: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; - break; -#endif -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) - case cmuSelect_LFXO: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; - break; -#endif - -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) - case cmuSelect_Disabled: - tmp = _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) - | tmp; - break; - -#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 - case cmuClock_EUSART1: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 - case cmuClock_EUSART2: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 - case cmuClock_EUSART3: -#endif -#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 - case cmuClock_EUSART4: -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) - case cmuClock_EM01GRPCCLK: - switch (ref) { - case cmuSelect_HFRCODPLL: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) - case cmuSelect_HFRCODPLLRT: - tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; - break; -#endif - case cmuSelect_HFRCOEM23: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; - break; - - case cmuSelect_FSRCO: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; - break; - - case cmuSelect_HFXO: - tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) - case cmuSelect_HFXORT: - tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -#endif - -// ----------------------------------------------------------------------------- -#if defined (RTCC_PRESENT) - case cmuClock_RTCC: - case cmuClock_RTCCCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined (SYSRTC_PRESENT) - case cmuClock_SYSRTC: - case cmuClock_SYSRTCCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; - break; - - case cmuSelect_Disabled: - tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LCD_PRESENT) - case cmuClock_LCD: - case cmuClock_LCDCLK: - switch (ref) { - case cmuSelect_LFRCO: -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: -#endif - tmp = CMU_LCDCLKCTRL_CLKSEL_LFRCO; - break; - - case cmuSelect_LFXO: - tmp = CMU_LCDCLKCTRL_CLKSEL_LFXO; - break; - - case cmuSelect_ULFRCO: - tmp = CMU_LCDCLKCTRL_CLKSEL_ULFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(VDAC_PRESENT) - case cmuClock_VDAC0: - case cmuClock_VDAC0CLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; - break; - case cmuSelect_EM01GRPACLK: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; - break; - case cmuSelect_EM23GRPACLK: - tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#if (VDAC_COUNT > 1) - case cmuClock_VDAC1: - case cmuClock_VDAC1CLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; - break; - case cmuSelect_EM01GRPACLK: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; - break; - case cmuSelect_EM23GRPACLK: - tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -#endif /* VDAC_PRESENT */ -// ----------------------------------------------------------------------------- -#if defined(PCNT_PRESENT) - case cmuClock_PCNT0: - case cmuClock_PCNT0CLK: - switch (ref) { - case cmuSelect_EM23GRPACLK: - tmp = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; - break; - - case cmuSelect_PCNTEXTCLK: - tmp = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSEHFCLK: - switch (ref) { - case cmuSelect_FSRCO: - tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; - break; - case cmuSelect_HFRCOEM23: - tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- -#if defined(USB_PRESENT) - case cmuClock_USB: - switch (ref) { - case cmuSelect_USBPLL0: - tmp = CMU_USB0CLKCTRL_CLKSEL_USBPLL0; - break; - case cmuSelect_LFXO: - tmp = CMU_USB0CLKCTRL_CLKSEL_LFXO; - break; - case cmuSelect_LFRCO: - tmp = CMU_USB0CLKCTRL_CLKSEL_LFRCO; - break; - - default: - EFM_ASSERT(false); - break; - } - CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) - | tmp; - break; -#endif -// ----------------------------------------------------------------------------- - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified low frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_LFXO: - precision = lfxo_precision; - break; - -#if defined(PLFRCO_PRESENT) -#if defined(LFRCO_CFG_HIGHPRECEN) - case cmuSelect_LFRCO: - case cmuSelect_PLFRCO: - - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; - - if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { - precision = 500; - } else { - precision = 0xFFFF; - } - break; -#endif -#endif - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified high frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_HFXO: - precision = hfxo_precision; - break; - - case cmuSelect_HFRCODPLL: - precision = 0xFFFF; - break; - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Get HFRCODPLL band in use. - * - * @return - * HFRCODPLL band in use. - ******************************************************************************/ -CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) -{ - return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); -} - -/***************************************************************************//** - * @brief - * Set HFRCODPLL band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] freq - * HFRCODPLL frequency band to activate. - ******************************************************************************/ -void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) -{ - uint32_t hfrcoFreqRangeExpected; - uint32_t hfrcoFreqRangeActual; - uint32_t hfrcoCalCurrent; - uint32_t freqCal, sysFreq; -#if defined(EMU_VSCALE_EM01_PRESENT) - uint32_t prevFreq; -#endif - - // Get calibration data from DEVINFO - freqCal = HFRCODPLLDevinfoGet(freq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - -#if defined(CMU_CLKEN0_DPLL0) - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; -#endif - - // Make sure DPLL is disabled before configuring - if (DPLL0->EN == DPLL_EN_EN) { - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while (DPLL0->EN & DPLL_EN_DISABLING) { - } -#else - while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { - } -#endif - } - - // Set max wait-states and PCLK divisor while changing core clock - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - } - - // Set divider for 1, 2 and 4MHz bands - freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; - switch (freq) { - case cmuHFRCODPLLFreq_1M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV4; - break; - - case cmuHFRCODPLLFreq_2M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV2; - break; - - default: - break; - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - prevFreq = SystemHFRCODPLLClockGet(); - - if ((uint32_t)freq > prevFreq) { - /* When increasing frequency voltage scale must be done before the change. */ - EMU_VScaleEM01ByClock((uint32_t)freq, true); - } -#endif - - // updates to the CAL register are deferred if FREQBSY is high, so wait - // until HFRCO is not busy to keep going - while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { - } - - /* - * Some devices have clamped frequency ranges, so instead of the usual [0:16] - * interval, the upper limit is 12. Hardware takes care of clamping the value, - * but a situation might occur where tuning and frequency range are not - * in sync. So try to detect if the value has been clamped, and if it happened - * revert back to the previous value. - */ - hfrcoCalCurrent = HFRCO0->CAL; - HFRCO0->CAL = freqCal; - - // values are not shifted, not necessary for comparison - hfrcoFreqRangeExpected = (freqCal & _HFRCO_CAL_FREQRANGE_MASK); - hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); - - EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); - if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { - // Update CMSIS HFRCODPLL frequency. - SystemHFRCODPLLClockSet(freq); - } else { - // revert back to previous value - HFRCO0->CAL = hfrcoCalCurrent; -#if defined(EMU_VSCALE_EM01_PRESENT) - freq = (CMU_HFRCODPLLFreq_TypeDef)prevFreq; -#endif - } - - // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access - // wait-state configuration and PCLK divisor for this frequency. - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= (uint32_t)freq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - } - -#if defined(EMU_VSCALE_EM01_PRESENT) - if ((uint32_t)freq <= prevFreq) { - /* When decreasing frequency voltage scale must be done after the change. */ - EMU_VScaleEM01ByClock(0, true); - } -#endif -} - -/**************************************************************************//** - * @brief - * Lock the DPLL to a given frequency. - * The frequency is given by: Fout = Fref * (N+1) / (M+1). - * - * @note - * This function does not check if the given N & M values will actually - * produce the desired target frequency. @n - * N & M limitations: @n - * 300 < N <= 4095 @n - * 0 <= M <= 4095 @n - * Any peripheral running off HFRCODPLL should be switched to a lower - * frequency clock (if possible) prior to calling this function to avoid - * over-clocking. - * - * @param[in] init - * DPLL setup parameter struct. - * - * @return - * Returns false on invalid target frequency or DPLL locking error. - *****************************************************************************/ -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) -{ - int index = 0; - unsigned int i; - bool hclkDivIncreased = false; - uint32_t hfrcoCalVal, lockStatus = 0, hclkDiv = 0, sysFreq; - uint32_t hfrcoFreqRangeExpected; - uint32_t hfrcoFreqRangeActual; - uint32_t hfrcoCalCurrent; - bool hfrcoClamped = false; - bool restoreDpll; - -#if defined(CMU_CLKEN0_DPLL0) - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; -#endif - - restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; - - // Make sure DPLL is disabled before configuring - DPLL0->EN_CLR = DPLL_EN_EN; -#if defined(DPLL_EN_DISABLING) - while (DPLL0->EN & DPLL_EN_DISABLING) { - } -#else - while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { - } -#endif - EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); - EFM_ASSERT(init->frequency - <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); - - EFM_ASSERT(init->n > 300U); - EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); - EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); - -#if defined(EMU_VSCALE_EM01_PRESENT) - if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) - && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EFM_ASSERT(false); - return false; - } -#endif - - // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. - for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { - if ((init->frequency >= hfrcoCalTable[i].minFreq) - && (init->frequency <= hfrcoCalTable[i].maxFreq)) { - index = (int)i; // Correct band found - break; - } - } - if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { - EFM_ASSERT(false); - return false; // Target frequency out of spec. - } - hfrcoCalVal = hfrcoCalTable[index].value; - - // Check if a calibrated HFRCOCAL.TUNING value is present in device DI page. - if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { - uint32_t tuning; - - tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) - & _HFRCO_CAL_TUNING_MASK) - >> _HFRCO_CAL_TUNING_SHIFT; - hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; - } - - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - // Set max wait-states and PCLK divisor while changing core clock - waitStateMax(); - pclkDivMax(); -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set largest prescaler for radio clock tree - rhclkPrescMax(); -#endif - - // Increase HCLK divider value (if possible) while locking DPLL to - // avoid over-clocking. - hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); - hclkDivIncreased = true; - if (hclkDiv == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 2U); - } else if (hclkDiv == 2U) { - CMU_ClockDivSet(cmuClock_HCLK, 4U); - } else { - hclkDivIncreased = false; - } - } - - // updates to the CAL register are deferred if FREQBSY is high, so wait - // until HFRCO is not busy to keep going - while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { - } - - /* - * Some devices have clamped frequency ranges, so instead of the usual [0:16] - * interval, the upper limit is 12. Hardware takes care of clamping the value, - * but a situation might occur where tuning and frequency range are not - * in sync. So try to detect if the value has been clamped, and if it happened - * revert back to the previous value. - */ - hfrcoCalCurrent = HFRCO0->CAL; - HFRCO0->CAL = hfrcoCalVal; - - // values are not shifted, not necessary for comparison - hfrcoFreqRangeExpected = (hfrcoCalVal & _HFRCO_CAL_FREQRANGE_MASK); - hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); - - EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); - if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { - DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) - | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); - - /* For series 2 silicon, macro expansion is used to select clock - * sources since it results in less code size when compared to the legacy - * CMU_ClockSelectSet function. - */ - if (init->refClk == cmuSelect_HFXO) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, HFXO); - } else if (init->refClk == cmuSelect_LFXO) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, LFXO); - } else if (init->refClk == cmuSelect_CLKIN0) { - CMU_CLOCK_SELECT_SET(DPLLREFCLK, CLKIN0); - } - - DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) - | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) - | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) - | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); - - // Update CMSIS HFRCODPLL frequency. - SystemHFRCODPLLClockSet(init->frequency); - } else { - hfrcoClamped = true; - HFRCO0->CAL = hfrcoCalCurrent; - } - - /* - * if HFRCO frequency range has been clamped, re-enable DPLL only if it was - * previously enabled - */ - if (!hfrcoClamped || restoreDpll) { - DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; - - // Lock DPLL - DPLL0->EN_SET = DPLL_EN_EN; - while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK - | DPLL_IF_LOCKFAILLOW - | DPLL_IF_LOCKFAILHIGH))) == 0UL) { - } - } - - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - if (hclkDivIncreased) { - // Restore original HCLK divider - CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); - } - - // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= init->frequency); - EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); - EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); - - // Set optimal wait-states and PCLK divisor - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - pclkDivOptimize(); -#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) - // Set optimal RHCLK prescaler - rhclkPrescOptimize(); -#endif - } - - if (hfrcoClamped) { - return false; - } else if (lockStatus == DPLL_IF_LOCK) { - return true; - } - return false; -} - -#if defined(USBPLL_PRESENT) -/***************************************************************************//** - * @brief - * Initialize the USB PLL control registers. - * - * @note - * The HFXO reference frequency must be updated if crystal value is - * different from default value. - * - * @param[in] pllInit - * USB PLL parameters - ******************************************************************************/ -void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit) -{ - CMU->CLKEN1_SET = CMU_CLKEN1_USB; - - USBPLL0->LOCK = USBPLL_LOCK_LOCKKEY_UNLOCK; - - // Stop the PLL for configuration purposes - USBPLL0->CTRL_SET = USBPLL_CTRL_DISONDEMAND; - USBPLL0->CTRL_CLR = USBPLL_CTRL_FORCEEN; - - while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; - - if (pllInit->hfxoRefFreq == cmuHFXORefFreq_39M0Hz) { - // Set DCO in low frequency mode for 39 MHz crystal. - USBPLL0->DCOCTRL_SET = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; - } else { - USBPLL0->DCOCTRL_CLR = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; - } - - while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; - - USBPLL0->CTRL = (USBPLL0->CTRL & ~(_USBPLL_CTRL_SHUNTREGLPEN_MASK - | _USBPLL_CTRL_DIVR_MASK - | _USBPLL_CTRL_DIVX_MASK - | _USBPLL_CTRL_DIVN_MASK - | _USBPLL_CTRL_DISONDEMAND_MASK - | _USBPLL_CTRL_FORCEEN_MASK)) - | pllInit->hfxoRefFreq - | pllInit->shuntRegEn << _USBPLL_CTRL_SHUNTREGLPEN_SHIFT - | pllInit->disOnDemand << _USBPLL_CTRL_DISONDEMAND_SHIFT - | pllInit->forceEn << _USBPLL_CTRL_FORCEEN_SHIFT; - - while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; - - if (pllInit->forceEn) { - CMU_WaitUSBPLLLock(); - } - - if (pllInit->regLock) { - USBPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -#if defined(RFFPLL_PRESENT) -/***************************************************************************//** - * @brief - * Initialize the RFFPLL control registers. - * - * @param[in] pllInit - * RFF PLL parameters - ******************************************************************************/ -void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit) -{ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_RFFPLLSYS); - EFM_ASSERT(pllInit->dividerY >= 8 && pllInit->dividerY <= 31); - EFM_ASSERT(pllInit->dividerX >= 4 && pllInit->dividerX <= 15); - EFM_ASSERT(pllInit->dividerN >= 32 && pllInit->dividerN <= 127); - - CMU->CLKEN1_SET = CMU_CLKEN1_RFFPLL0; - - RFFPLL0->LOCK = RFFPLL_LOCK_LOCKKEY_UNLOCK; - - RFFPLL0->CTRL = (RFFPLL0->CTRL & ~(_RFFPLL_CTRL_DISONDEMAND_MASK | _RFFPLL_CTRL_FORCEEN_MASK)) - | (pllInit->disOnDemand << _RFFPLL_CTRL_DISONDEMAND_SHIFT) - | (pllInit->forceEn << _RFFPLL_CTRL_FORCEEN_SHIFT); - - RFFPLL0->RFFPLLCTRL1 = (RFFPLL0->RFFPLLCTRL1 & ~(_RFFPLL_RFFPLLCTRL1_DIVY_MASK | _RFFPLL_RFFPLLCTRL1_DIVX_MASK | _RFFPLL_RFFPLLCTRL1_DIVN_MASK)) - | (pllInit->dividerY << _RFFPLL_RFFPLLCTRL1_DIVY_SHIFT) - | (pllInit->dividerX << _RFFPLL_RFFPLLCTRL1_DIVX_SHIFT) - | (pllInit->dividerN << _RFFPLL_RFFPLLCTRL1_DIVN_SHIFT); - - // Update CMSIS RFFPLL frequency. - SystemRFFPLLClockSet(pllInit->frequency); - - if (pllInit->forceEn) { - CMU_WaitRFFPLLLock(); - } - - if (pllInit->regLock) { - RFFPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -/**************************************************************************//** - * @brief - * Initialize all HFXO control registers. - * - * @note - * HFXO configuration should be obtained from a configuration tool, - * app note or crystal datasheet. This function returns early if HFXO is - * already selected as SYSCLK. - * - * @param[in] hfxoInit - * HFXO setup parameters. - *****************************************************************************/ -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) -{ - // Check all initialization structure members which may overflow target - // bitfield. - EFM_ASSERT(hfxoInit->timeoutCbLsb - <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK - >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); - EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock - <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK - >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); - EFM_ASSERT(hfxoInit->timeoutSteady - <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK - >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneXoStartup - <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK - >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneXiStartup - <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK - >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->coreBiasStartup - <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK - >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); - EFM_ASSERT(hfxoInit->imCoreBiasStartup - <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK - >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); - EFM_ASSERT(hfxoInit->coreDegenAna - <= (_HFXO_XTALCTRL_COREDGENANA_MASK - >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); - EFM_ASSERT(hfxoInit->ctuneFixAna - <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK - >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); - EFM_ASSERT(hfxoInit->mode - <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); - - // Return early if HFXO is already selected as SYSCLK. - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { - return; - } - -#if defined(CMU_CLKEN0_HFXO0) - // Enable HFXO module clock. - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - // Disable HFXO. - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND -#if defined(_HFXO_CTRL_DISONDEMANDBUFOUT_MASK) - | HFXO_CTRL_DISONDEMANDBUFOUT -#endif - ; - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; - while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { - } -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - -#if defined(_DEVINFO_HFXOCAL_VTRTRIMANA_MASK) && defined(_HFXO_BUFOUTTRIM_MASK) && defined(_HFXO_SWRST_MASK) - { - uint32_t tmp; - - tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, - _DEVINFO_HFXOCAL_VTRTRIMANA_MASK); - tmp >>= _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT; - BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, - _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK, - tmp << _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT); - } -#endif - -#if defined(_DEVINFO_HFXOCAL_SHUNTBIASANA_MASK) && defined(_HFXO_LOWPWRCTRL_MASK) && defined(_HFXO_SWRST_MASK) - { - uint32_t tmp; - - tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, - _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK); - tmp >>= _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT; - BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, - _HFXO_LOWPWRCTRL_SHUNTBIASANA_MASK, - tmp << _HFXO_LOWPWRCTRL_SHUNTBIASANA_SHIFT); - } -#endif - - // Configure HFXO as specified in initialization struct, use - // timeoutSteadyFirstLock as TIMEOUTSTEADY value. - HFXO0->XTALCFG = - (uint32_t)((hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) - | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) - | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) - | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) - | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) - | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); - - HFXO0->XTALCTRL = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) - | (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) - | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) - | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) - | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) - | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - // See [PM-2871] for details. - BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), - 0x00000C00U, - 0x00000002U << 10); -#endif - - HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK - | _HFXO_CFG_ENXIDCBIASANA_MASK - | _HFXO_CFG_MODE_MASK)) - | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) - ? 0 : HFXO_CFG_SQBUFSCHTRGANA) - | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) - | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); - - if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { - // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared. - HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK - | _HFXO_CTRL_FORCEXI2GNDANA_MASK - | _HFXO_CTRL_DISONDEMAND_MASK -#if defined(HFXO_CTRL_EM23ONDEMAND) - | _HFXO_CTRL_EM23ONDEMAND_MASK -#endif - | _HFXO_CTRL_FORCEEN_MASK)) - | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) - | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) -#if defined(HFXO_CTRL_EM23ONDEMAND) - | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) -#endif - | HFXO_CTRL_FORCEEN; - - // Wait for HFXO lock and core bias algorithm to complete. -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY - | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) - != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS - | HFXO_STATUS_FSMLOCK)) { - } -#else - while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY - | HFXO_STATUS_ENS)) - != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS)) { - } -#endif - // Set DISONDEMAND to be able to enter new values for use on subsequent locks. - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD = HFXO_CMD_MANUALOVERRIDE; -#endif -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - } -#endif - // Set new TIMEOUTSTEADY value for use on subsequent locks. - HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) - | (hfxoInit->timeoutSteady - << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); - - // Skip core bias algorithm on subsequent locks. - HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; - - if (hfxoInit->disOnDemand == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; - } - - if (hfxoInit->forceEn == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; -#if defined(HFXO_STATUS_SYNCBUSY) - while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { - } -#endif - } - } else { - // Lock HFXO in EXTERNAL SINE mode. - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - //See [PM-3665] for details. - if (hfxoInit->mode == cmuHfxoOscMode_ExternalSinePkDet) { - HFXO0->XTALCFG = 0; - HFXO0->XTALCTRL = 0; - - const uint32_t PKDETTHSTARTUP_PARAMETER_1 = 2UL; - BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), - 0x0000F000U | 0x00000F00U, - (PKDETTHSTARTUP_PARAMETER_1 << 12) | (PKDETTHSTARTUP_PARAMETER_1 << 8)); - } -#endif - - HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK - | _HFXO_CTRL_FORCEXI2GNDANA_MASK - | _HFXO_CTRL_DISONDEMAND_MASK -#if defined(HFXO_CTRL_EM23ONDEMAND) - | _HFXO_CTRL_EM23ONDEMAND_MASK -#endif - | _HFXO_CTRL_FORCEEN_MASK)) - | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) - | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) -#if defined(HFXO_CTRL_EM23ONDEMAND) - | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) -#endif - | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); - } - - if (hfxoInit->regLock) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } -} - -#if defined(HFXO0_BUFOUT) -/**************************************************************************//** - * @brief - * Initialize HFXO Bufout (Crystal sharing) leader control registers. - * Configure the bufout request input GPIO as a clock request signal - * to add the crystal sharing follower chip as a source of clock request. - * - * @warning - * If EM2 capabilities are needed, a GPIO that fully retains its - * capabilities while in EM2 must be selected. - * - * @param[in] bufoutInit - * Bufout setup parameters. - * - * @param[in] port - * Bufout request GPIO port. - * - * @param[in] pin - * Bufout request GPIO pin. - *****************************************************************************/ -void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - // Configure Bufout request GPIO. - GPIO_PinModeSet(port, pin, gpioModeInput, 0U); - GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT - | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; - - bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; - - BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, - _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK - | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, - bufoutInit->minimalStartupDelay << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT - | bufoutInit->timeoutStartup << _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT); - - if (wasLocked) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } -} -#endif - -#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) -/**************************************************************************//** - * @brief - * Initialize HFXO Bufout (Crystal sharing) follower control registers. - * Configure the clock request signal to a specified GPIO to automatically - * request the high frequency crystal oscillator sine wave clock. - * This function must be used in conjunction with CMU_HFXOInit() configured - * with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode. - * - * @warning - * If EM2 capabilities are needed, a GPIO that fully retains its - * capabilities while in EM2 must be selected. - * - * @note - * This function can be emulated on XG21/XG22 chips by controlling the clock - * request GPIO to ask the crystal sharing leader clock when needed. - * - * @param[in] prsStatusSelectOutput - * Selected HFXO PRS signal output. - * - * @param[in] prsAsyncCh - * PRS producer asynchronous signal channel. - * - * @param[in] port - * Bufout request GPIO port. - * - * @param[in] pin - * Bufout request GPIO pin. - *****************************************************************************/ -void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, - unsigned int prsAsyncCh, - GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(prsAsyncCh < PRS_ASYNC_CH_NUM); - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - uint32_t mask = 0U, prsSignal = 0U, value = 0U; - - switch (prsStatusSelectOutput) { - case PRS_Status_select_0: - mask = _HFXO_CTRL_PRSSTATUSSEL0_MASK; - value = _HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT; - prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS; - break; - - case PRS_Status_select_1: -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - // Power Manager module requires the HFXO PRS Producer output 1 for its usage. - EFM_ASSERT(false); -#else - mask = _HFXO_CTRL_PRSSTATUSSEL1_MASK; - value = _HFXO_CTRL_PRSSTATUSSEL1_ENS << _HFXO_CTRL_PRSSTATUSSEL1_SHIFT; - prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1; -#endif - break; - - default: - EFM_ASSERT(false); - break; - } - - bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; - - // Unlock register interface. - HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; - - BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); - - if (wasLocked) { - HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; - } - - value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT - | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT - | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT - | prsSignal << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; - - mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK - | _PRS_ASYNC_CH_CTRL_FNSEL_MASK - | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK - | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; - - BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); - - GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); - - (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[prsAsyncCh] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT - | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; - GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + prsAsyncCh); -} -#endif - -/**************************************************************************//** - * @brief - * Set the HFXO crystal tuning capacitance. - * - * @param[in] ctune - * The desired tuning capacitance value. Each step corresponds to - * approximately 80fF. Min value is 0. Max value is 255. - * - * @return - * SL_STATUS_OK if initialization parameter is valid. - * SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid. - * - * @note - * While the oscillator is running in steady operation state, it may be - * desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA - * fields in the HFXO_XTALCTRL register. When tuning, care should be taken to - * make small changes to the CTUNE registers. Ideally, change the CTUNE - * registers by one LSB at a time and alternate between the XI and XO - * registers. Sufficient wait time for settling, on the order of - * TIMEOUTSTEADY, should pass before new frequency measurement is taken. - *****************************************************************************/ -sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) -{ - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // Make sure the given CTUNE value is within the allowable range - if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Keep oscillator running, if it is enabled - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - // Manual override needs COREBIASOPTRDY asserted, - // or the command will be ignored. - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - } - } - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - int32_t ctuneXoana = ctune + CMU_HFXOCTuneDeltaGet(); - if (ctuneXoana < 0) { - ctuneXoana = 0; - } else if (ctuneXoana > (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT)) { - ctuneXoana = (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); // Max value - } - - HFXO0->XTALCTRL = ((HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXOANA_MASK | _HFXO_XTALCTRL_CTUNEXIANA_MASK)) - | ((uint32_t)ctuneXoana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) - | ((ctune << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) & _HFXO_XTALCTRL_CTUNEXIANA_MASK)); - - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); - - // Unforce to return control to hardware request - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); - } - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * @brief - * Get the HFXO crystal tuning capacitance. - * - * @return - * The HFXO crystal tuning capacitance. - * - * @note - This function only returns the CTUNE XI value. The XO value can be - different and can be found using the delta (difference between XI and XO). - See @ref CMU_HFXOCTuneDeltaGet to retrieve the delta value. - *****************************************************************************/ -uint32_t CMU_HFXOCTuneGet(void) -{ - uint32_t ctune = 0; - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // Keep oscillator running, if it is enabled - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - // Manual override needs COREBIASOPTRDY asserted, - // or the command will be ignored. - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - } - } - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) - >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); - - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); - - // Unforce to return control to hardware request - if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { - BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); - } - - return ctune; -} - -/**************************************************************************//** - * @brief - * Set the HFXO crystal tuning delta. - * - * @param[in] delta - * Chip dependent crystal capacitor bank delta between HFXO XI and XO. - * - * @note - * The delta between XI and XO is applicable for the series 2 EFR32xG2x - * devices only. - *****************************************************************************/ -void CMU_HFXOCTuneDeltaSet(int32_t delta) -{ - ctuneDelta = (int8_t)delta; -} - -/**************************************************************************//** - * @brief - * Get the HFXO crystal tuning delta. - * - * @return - * Chip dependent crystal capacitor bank tuning delta. - *****************************************************************************/ -int32_t CMU_HFXOCTuneDeltaGet(void) -{ - return (int32_t)ctuneDelta; -} - -/**************************************************************************//** - * @brief - * Recalibrate the HFXO's Core Bias Current. - * - * @note - * Care should be taken when using this function as it can cause disturbance - * on the HFXO frequency while the optimization is underway. It's recommended - * to only use this function when HFXO isn't being used. It's also a blocking - * function that can be time consuming. - *****************************************************************************/ -void CMU_HFXOCoreBiasCurrentCalibrate(void) -{ - uint32_t hfxoCtrlBkup = HFXO0->CTRL; - - // These two bits need to be set to allow writing the registers - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; - while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) { - // Wait for crystal to startup - } - - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - // Wait for crystal to switch modes. - } -#endif - - while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) - != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { - // Making sure HFXO is in steady state - } - - // Start core bias optimization - HFXO0->CMD_SET = HFXO_CMD_COREBIASOPT; - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == HFXO_STATUS_COREBIASOPTRDY) { - // Wait for core bias optimization to start - } - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - // Wait for core bias optimization to finish - } - - // Force COREBIASANA bitfields modification -#if defined(HFXO_CMD_MANUALOVERRIDE) - HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; -#endif - - while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { - // Wait for core bias current value to be written in COREBIASANA bitfields - } - - BUS_RegMaskedWrite(&HFXO0->CTRL, (_HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK), hfxoCtrlBkup); -} - -/**************************************************************************//** - * @brief - * Initialize LFXO control registers. - * - * @note - * LFXO configuration should be obtained from a configuration tool, - * app note or crystal datasheet. This function disables the LFXO to ensure - * a valid state before update. - * - * @param[in] lfxoInit - * LFXO setup parameters - *****************************************************************************/ -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) -{ - EFM_ASSERT(lfxoInit->timeout - <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); - EFM_ASSERT(lfxoInit->mode - <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); - EFM_ASSERT(lfxoInit->gain - <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); - EFM_ASSERT(lfxoInit->capTune - <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); - - // Max internal capacitance tuning value is 0x4F (20 pF) - uint8_t ctune = (uint8_t) SL_MIN(0x4FU, lfxoInit->capTune); - -#if defined(CMU_CLKEN0_LFXO) - // Enable LFXO module clock. - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - - // Unlock register interface - LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; - - // Disable LFXO - LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; - LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; - while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { - } - - // Configure LFXO as specified - LFXO->CAL = ((uint32_t)lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) - | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); - - LFXO->CFG = (uint32_t)((lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) - | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) - | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) - | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT)); - - LFXO->CTRL = (uint32_t)((lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) - | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) - | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) - | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT)); - - if (lfxoInit->regLock) { - LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; - } -} - -/**************************************************************************//** - * @brief - * Sets LFXO's crystal precision, in PPM. - * - * @note - * LFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_LFXOPrecisionSet(uint16_t precision) -{ - lfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets LFXO's crystal precision, in PPM. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_LFXOPrecisionGet(void) -{ - return lfxo_precision; -} - -/**************************************************************************//** - * @brief - * Sets HFXO's crystal precision, in PPM. - * - * @note - * HFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_HFXOPrecisionSet(uint16_t precision) -{ - hfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets HFXO's crystal precision, in PPM. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_HFXOPrecisionGet(void) -{ - return hfxo_precision; -} - -#if defined(PLFRCO_PRESENT) -/**************************************************************************//** - * @brief - * Configure the LFRCO precision. - * - * @details - * When enabling high precision mode on the LFRCO the hardware will tune - * the oscillator automatically using the HFXO as a reference. - * - * @note - * Refer to the reference manual and the datasheet for details about - * NOMCAL and NOMCALINV calibration count values. - * - * @param[in] precision - * LFRCO precision, this can be either high or default. - *****************************************************************************/ -void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision) -{ - uint32_t ref = 0; - uint32_t nomcal = 0; - uint32_t nomcalinv = 0; - - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; - - LFRCO->CTRL = LFRCO_CTRL_DISONDEMAND; // Force disable - while ((LFRCO->STATUS & LFRCO_STATUS_ENS) != 0U) { - // Wait for LFRCO to stop - } - - if (precision == cmuPrecisionHigh) { - ref = SystemHFXOClockGet(); - // Use precomputed value for HFXO typical frequencies - if (ref == XTAL_38M4) { - nomcal = LFRCO_NOMCAL_XTAL_38M4; - nomcalinv = LFRCO_NOMCALINV_XTAL_38M4; - } else if (ref == XTAL_39M0) { - nomcal = LFRCO_NOMCAL_XTAL_39M0; - nomcalinv = LFRCO_NOMCALINV_XTAL_39M0; - } else { - // Compute calibration count, based on HFXO frequency - nomcal = (5 * ref) >> 9; - nomcalinv = ((1UL << 31) / 5) << 2; - nomcalinv /= (ref >> 9); - } - - LFRCO->NOMCAL = nomcal; - LFRCO->NOMCALINV = nomcalinv; - - LFRCO->CFG = LFRCO_CFG_HIGHPRECEN; - } else { - LFRCO->CFG = 0; - } - LFRCO->CTRL = _LFRCO_CTRL_RESETVALUE; -} -#endif - -/***************************************************************************//** - * @brief - * Get oscillator frequency tuning setting. - * - * @param[in] osc - * Oscillator to get tuning value for. - * - * @return - * The oscillator frequency tuning setting in use. - ******************************************************************************/ -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) -{ - uint32_t ret = 0U; - - switch (osc) { -#if defined(_LFRCO_CAL_FREQTRIM_MASK) - case cmuOsc_LFRCO: -#if defined(CMU_CLKEN0_LFRCO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; -#endif - ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; - break; -#endif - - case cmuOsc_HFRCODPLL: -#if defined(CMU_CLKEN0_HFRCO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; -#endif - ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuOsc_HFRCOEM23: - ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; - break; -#endif - - case cmuOsc_HFXO: -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - ret = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK) >> _HFXO_XTALCTRL_COREBIASANA_SHIFT; - break; - - case cmuOsc_LFXO: -#if defined(CMU_CLKEN0_LFXO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - ret = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the oscillator frequency tuning control. - * - * @note - * Oscillator tuning is done during production, and the tuning value is - * automatically loaded after a reset. Changing the tuning value from the - * calibrated value is for more advanced use. Certain oscillators also have - * build-in tuning optimization. - * - * @param[in] osc - * Oscillator to set tuning value for. - * - * @param[in] val - * The oscillator frequency tuning setting to use. - ******************************************************************************/ -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) -{ - bool disondemand = false; - bool lfxo_lock_status = false; - uint8_t ctune = 0; - - switch (osc) { -#if defined(_LFRCO_CAL_FREQTRIM_MASK) - case cmuOsc_LFRCO: -#if defined(CMU_CLKEN0_LFRCO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; -#endif - EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK - >> _LFRCO_CAL_FREQTRIM_SHIFT)); - val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; - while (LFRCO->SYNCBUSY != 0U) { - } - LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) - | (val << _LFRCO_CAL_FREQTRIM_SHIFT); - break; -#endif - - case cmuOsc_HFRCODPLL: -#if defined(CMU_CLKEN0_HFRCO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; -#endif - EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); - val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; - while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { - } - HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) - | (val << _HFRCO_CAL_TUNING_SHIFT); - break; - -#if defined(HFRCOEM23_PRESENT) - case cmuOsc_HFRCOEM23: - EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); - val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; - while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { - } - HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) - | (val << _HFRCO_CAL_TUNING_SHIFT); - break; -#endif - - case cmuOsc_HFXO: -#if defined(CMU_CLKEN0_HFXO0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; -#endif - EFM_ASSERT(val <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); - // Make sure HFXO is disable - EFM_ASSERT((HFXO0->STATUS & HFXO_STATUS_ENS) == 0); - - // Set DISONDEMAND if not already set and wait for FSMLOCK to be clear so that - // software can write to register - disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) >> _HFXO_CTRL_DISONDEMAND_SHIFT; - if (disondemand == false) { - HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; - } -#if defined(HFXO_STATUS_FSMLOCK) - while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { - } -#endif - // Update Core Bias Ana setting and enable Optimization skip - HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) - | (val << _HFXO_XTALCTRL_COREBIASANA_SHIFT) - | HFXO_XTALCTRL_SKIPCOREBIASOPT; - // Clear back DISONDEMAND if needed - if (disondemand == false) { - HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; - } - break; - - case cmuOsc_LFXO: -#if defined(CMU_CLKEN0_LFXO) - CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; -#endif - lfxo_lock_status = (LFXO->STATUS & _LFXO_STATUS_LOCK_MASK) >> _LFXO_STATUS_LOCK_SHIFT; - // Unlock register interface if register is locked before - if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { - LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; - } - - EFM_ASSERT(val <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); - // Max internal capacitance tuning value is 0x4F (20 pF) - ctune = (uint8_t) SL_MIN(0x4FU, val); - - // Wait for CALBSY bit to clear before writing the tuning value to CAL register - while (((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) >> _LFXO_SYNCBUSY_CAL_SHIFT) != 0U) { - } - LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) - | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); - - // Lock register interface again - if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { - LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; - } - break; - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Configure wait state settings necessary to switch to a given core clock - * frequency at a certain voltage scale level. - * - * @details - * This function will set up the necessary flash wait states. Updating the - * wait state configuration must be done before increasing the clock - * frequency and it must be done after decreasing the clock frequency. - * Updating the wait state configuration must be done before core voltage is - * decreased and it must be done after a core voltage is increased. - * - * @param[in] freq - * The core clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 1, higher number is lower voltage. - * @li 0 = 1.1 V (VSCALE2) - * @li 1 = 1.0 V (VSCALE1) - ******************************************************************************/ -void CMU_UpdateWaitStates(uint32_t freq, int vscale) -{ - if (vscale > 0) { - flashWaitStateControl(freq, VSCALE_EM01_LOW_POWER); - } else { - flashWaitStateControl(freq, VSCALE_EM01_HIGH_PERFORMANCE); - } -} - -/**************************************************************************//** - * @brief - * Select the PCNTn clock. - * - * @param[in] instance - * PCNT instance number to set selected clock source for. - * - * @param[in] external - * Set to true to select the external clock, false to select EM23GRPACLK. - *****************************************************************************/ -void CMU_PCNTClockExternalSet(unsigned int instance, bool external) -{ - (void)instance; -#if defined(PCNT_PRESENT) - if (external) { - CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; - } else { - CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; - } -#else - (void)external; -#endif -} - -#if defined(HFRCOEM23_PRESENT) -/***************************************************************************//** - * @brief - * Get HFRCOEM23 band in use. - * - * @return - * HFRCOEM23 band in use. - ******************************************************************************/ -CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) -{ - return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); -} - -/***************************************************************************//** - * @brief - * Set HFRCOEM23 band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] freq - * HFRCOEM23 frequency band to activate. - ******************************************************************************/ -void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) -{ - uint32_t freqCal; - - // Get calibration data from DEVINFO - freqCal = HFRCOEM23DevinfoGet(freq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); -#if defined(CMU_CLKEN0_HFRCOEM23) - CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; -#endif - - // Set divider for 1, 2 and 4MHz bands - freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; - switch (freq) { - case cmuHFRCOEM23Freq_1M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV4; - break; - - case cmuHFRCOEM23Freq_2M0Hz: - freqCal |= HFRCO_CAL_CLKDIV_DIV2; - break; - - default: - break; - } - - // Activate new band selection - HFRCOEM23->CAL = freqCal; -} -#endif // defined(HFRCOEM23_PRESENT) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) -#if defined(PDM_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM01GRPBCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - switch (CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0: - f = SystemCLKIN0Get(); - s = cmuSelect_CLKIN0; - break; - - case CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(EUART_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EUART0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - switch (CMU->EUART0CLKCTRL & _CMU_EUART0CLKCTRL_CLKSEL_MASK) { - case CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(freq, sel); - break; - - case CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(freq, sel); - break; - - default: - if (freq != NULL) { - *freq = 0U; - } - if (sel != NULL) { - *sel = cmuSelect_Error; - } - EFM_ASSERT(false); - break; - } -} -#endif - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EUSART0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EUSART0CLKCTRL & _CMU_EUSART0CLKCTRL_CLKSEL_MASK) { -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK: - em01GrpcClkGet(&f, NULL); - s = cmuSelect_EM01GRPCCLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) - case CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) - case CMU_EUSART0CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) - case CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) - case CMU_EUSART0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFXO) - case CMU_EUSART0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; -#endif - -#if defined(CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) - case CMU_EUSART0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(_CMU_EM01GRPCCLKCTRL_MASK) -/**************************************************************************//** -* @brief -* Get selected oscillator and frequency for @ref cmuClock_EM01GRPCCLK -* clock tree. -* -* @param[out] freq -* The frequency. -* -* @param[out] sel -* The selected oscillator. -******************************************************************************/ -static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - - case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) - case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; -#endif - - case _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(_CMU_EM01GRPCCLKCTRL_MASK) -#endif // defined(EUSART_PRESENT) - -#if defined(LCD_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_LCDCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->LCDCLKCTRL & _CMU_LCDCLKCTRL_CLKSEL_MASK) { - case CMU_LCDCLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_LCDCLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_LCDCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(LCD_PRESENT) - -#if defined(VDAC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_VDAC0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->VDAC0CLKCTRL & _CMU_VDAC0CLKCTRL_CLKSEL_MASK) { - case CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_VDAC0CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if (VDAC_COUNT > 1) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_VDAC1CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->VDAC1CLKCTRL & _CMU_VDAC1CLKCTRL_CLKSEL_MASK) { - case CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_VDAC1CLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif -#endif /* VDAC_PRESENT */ - -#if defined(PCNT_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_PCNT0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->PCNT0CLKCTRL & _CMU_PCNT0CLKCTRL_CLKSEL_MASK) { - case CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK: - em23GrpaClkGet(&f, NULL); - s = cmuSelect_EM23GRPACLK; - break; - - case CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0: - f = 0U; // external or PRS source so the frequency is undefined. - s = cmuSelect_PCNTEXTCLK; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(LESENSE_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_LESENSEHFCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->LESENSEHFCLKCTRL & _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) { - case CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; - - case CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ - && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -/***************************************************************************//** - * @brief - * Set maximum allowed prescaler for radio clock tree (RHCLK). - ******************************************************************************/ -static void rhclkPrescMax(void) -{ - // Set largest prescaler (DIV2). - CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_RHCLKPRESC; -} - -/***************************************************************************//** - * @brief - * Set radio clock tree prescaler to achieve highest possible frequency - * and still be within spec. - ******************************************************************************/ -static void rhclkPrescOptimize(void) -{ - if (CMU_ClockFreqGet(cmuClock_SYSCLK) <= CMU_MAX_RHCLK_FREQ) { - // Set smallest prescaler (DIV1). - CMU->SYSCLKCTRL_CLR = CMU_SYSCLKCTRL_RHCLKPRESC; - } -} -#endif // ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) -#endif // #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - -#if defined(HFRCOEM23_PRESENT) -/***************************************************************************//** - * @brief - * Get calibrated HFRCOEM23 tuning value from Device information (DI) page - * for a given frequency. Calibration value is not available for all frequency - * bands. - * - * @param[in] freq - * HFRCOEM23 frequency band - ******************************************************************************/ -static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) -{ - uint32_t ret = 0U; - - switch (freq) { - // 1, 2 and 4MHz share the same calibration word - case cmuHFRCOEM23Freq_1M0Hz: - case cmuHFRCOEM23Freq_2M0Hz: - case cmuHFRCOEM23Freq_4M0Hz: - ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_13M0Hz: - ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_16M0Hz: - ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_19M0Hz: - ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_26M0Hz: - ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_32M0Hz: - ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_40M0Hz: - ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; - break; - - case cmuHFRCOEM23Freq_UserDefined: - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} -#endif // defined(HFRCOEM23_PRESENT) - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_TRACECLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - -#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) - switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { -#if defined(_CMU_TRACECLKCTRL_CLKSEL_HCLK) - case CMU_TRACECLKCTRL_CLKSEL_HCLK: - f = SystemHCLKGet(); - s = cmuSelect_HCLK; - break; -#endif -#if defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) - case CMU_TRACECLKCTRL_CLKSEL_SYSCLK: - f = SystemSYSCLKGet(); - s = cmuSelect_SYSCLK; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) - case CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - -#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } -#else - f = SystemSYSCLKGet(); - s = cmuSelect_SYSCLK; -#endif - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { - case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: - f = SystemCLKIN0Get(); - s = cmuSelect_CLKIN0; - break; - - case CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLL; - break; - - case CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXO; - break; - -#if defined(HFRCOEM23_PRESENT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - - case CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - case CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT: - f = SystemHFRCODPLLClockGet(); - s = cmuSelect_HFRCODPLLRT; - break; -#endif - -#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) - case CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT: - f = SystemHFXOClockGet(); - s = cmuSelect_HFXORT; - break; -#endif - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale) -{ - uint32_t flashWs = MSC_READCTRL_MODE_WS3; - - if (vscale == 0) { - // VScale 1.1V core frequency ranges for wait-states configurations. - if (0) { - } -#if defined(CMU_MAX_FREQ_2WS_1V1) - else if (freq > CMU_MAX_FREQ_2WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS3; - } -#endif -#if defined(CMU_MAX_FREQ_1WS_1V1) - else if (freq > CMU_MAX_FREQ_1WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS2; - } -#endif -#if defined(CMU_MAX_FREQ_0WS_1V1) - else if (freq > CMU_MAX_FREQ_0WS_1V1) { - flashWs = MSC_READCTRL_MODE_WS1; - } -#endif - else { - flashWs = MSC_READCTRL_MODE_WS0; - } - } else if (vscale >= 1) { - // VScale 1.0V core frequency ranges for wait-states configurations. - if (0) { - } -#if defined(CMU_MAX_FREQ_2WS_1V0) - else if (freq > CMU_MAX_FREQ_2WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS3; - } -#endif -#if defined(CMU_MAX_FREQ_1WS_1V0) - else if (freq > CMU_MAX_FREQ_1WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS2; - } -#endif -#if defined(CMU_MAX_FREQ_0WS_1V0) - else if (freq > CMU_MAX_FREQ_0WS_1V0) { - flashWs = MSC_READCTRL_MODE_WS1; - } -#endif - else { - flashWs = MSC_READCTRL_MODE_WS0; - } - } - return flashWs; -} - -/***************************************************************************//** - * @brief - * Configure flash access wait states to support the given core clock - * frequency and vscale level. - * - * @note Current implementation sets wait states depending on frequency only. - * This assumes that applications running on Vscale enabled microcontrollers - * never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). - * Series 2 Config 1 devices does not support vscale. - * - * @param[in] coreFreq - * The core clock frequency to configure flash wait-states. - * - * @param[in] vscale - * Voltage Scale level. Supported levels are 0 and 1 where 0 is the default. - * @li 0 = 1.1 V (VSCALE2) - * @li 1 = 1.0 V (VSCALE1) - ******************************************************************************/ -static void flashWaitStateControl(uint32_t coreFreq, int vscale) -{ - (void)vscale; - - uint32_t mode; - bool mscLocked; - -#if defined(CMU_CLKEN1_MSC) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - coreFreq *= CMU_ClockDivGet(cmuClock_CORE); -#endif - - // Make sure the MSC is unlocked - mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - // Get current flash read setting - mode = MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK; - - // Set new mode based on the core clock frequency - mode |= getWaitStatesByFrequencyAndVScale(coreFreq, vscale); - - MSC_ReadCTRLSet(mode); - - // Set sram wait states for config 1 mcu. -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - // Set new mode based on the core clock frequency - if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { - SYSCFG_setDmem0RamCtrlRamwsenBit(); - } else { - SYSCFG_clearDmem0RamCtrlRamwsenBit(); - } -#endif - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -/***************************************************************************//** - * @brief - * Get calibrated HFRCODPLL tuning value from Device information (DI) page - * for a given frequency. Calibration value is not available for all frequency - * bands. - * - * @param[in] freq - * HFRCODPLL frequency band - ******************************************************************************/ -static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) -{ - uint32_t ret = 0U; - - switch (freq) { - // 1, 2 and 4MHz share the same calibration word - case cmuHFRCODPLLFreq_1M0Hz: - case cmuHFRCODPLLFreq_2M0Hz: - case cmuHFRCODPLLFreq_4M0Hz: - ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_7M0Hz: - ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_13M0Hz: - ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_16M0Hz: - ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_19M0Hz: - ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_26M0Hz: - ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_32M0Hz: - ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_38M0Hz: - ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_48M0Hz: - ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_56M0Hz: - ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_64M0Hz: - ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; - break; - - case cmuHFRCODPLLFreq_80M0Hz: - ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; - break; - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - case cmuHFRCODPLLFreq_100M0Hz: - ret = DEVINFO->HFRCODPLLCAL[17].HFRCODPLLCAL; - break; -#endif - - case cmuHFRCODPLLFreq_UserDefined: - break; - - default: - EFM_ASSERT(false); - break; - } - return ret; -} - -#if defined(IADC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_IADCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { - case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: - em01GrpaClkGet(&f, NULL); - s = cmuSelect_EM01GRPACLK; - break; - -#if defined(HFRCOEM23_PRESENT) - case CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: - f = SystemHFRCOEM23ClockGet(); - s = cmuSelect_HFRCOEM23; - break; -#endif - - case CMU_IADCCLKCTRL_CLKSEL_FSRCO: - f = SystemFSRCOClockGet(); - s = cmuSelect_FSRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/***************************************************************************//** - * @brief - * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. - ******************************************************************************/ -static void pclkDivMax(void) -{ - // Set largest divisor for PCLK clock tree. - CMU_ClockDivSet(cmuClock_PCLK, 2U); -} - -/***************************************************************************//** - * @brief - * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible - * frequency and still be within spec. - ******************************************************************************/ -static void pclkDivOptimize(void) -{ - CMU_ClkDiv_TypeDef div = 2U; - - if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { - div = 1U; - } - CMU_ClockDivSet(cmuClock_PCLK, div); -} - -#if defined(RTCC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { - case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_RTCCCLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -#if defined(SYSRTC_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_SYSRTCCLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/***************************************************************************//** - * @brief - * Set wait-states to values valid for maximum allowable core clock frequency. - ******************************************************************************/ -static void waitStateMax(void) -{ - flashWaitStateControl(SystemMaxCoreClockGet(), 0); -} - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { - case CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: - f = SystemHCLKGet() / 1024U; - s = cmuSelect_HCLKDIV1024; - break; - - case CMU_WDOG0CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { - case CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: - f = SystemULFRCOClockGet(); - s = cmuSelect_ULFRCO; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: - f = SystemHCLKGet() / 1024U; - s = cmuSelect_HCLKDIV1024; - break; - - case CMU_WDOG1CLKCTRL_CLKSEL_DISABLED: - s = cmuSelect_Disabled; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif // defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 - -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_SYSTICK - * clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { - f = SystemHCLKGet(); - s = cmuSelect_HCLK; - } else { - em23GrpaClkGet(&f, &s); - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} - -#if defined(USB_PRESENT) -/***************************************************************************//** - * @brief - * Get selected oscillator and frequency for @ref cmuClock_USB clock tree. - * - * @param[out] freq - * The frequency. - * - * @param[out] sel - * The selected oscillator. - ******************************************************************************/ -static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) -{ - uint32_t f = 0U; - CMU_Select_TypeDef s; - - switch (CMU->USB0CLKCTRL & _CMU_USB0CLKCTRL_CLKSEL_MASK) { - case CMU_USB0CLKCTRL_CLKSEL_USBPLL0: - f = PLL0_USB_OUTPUT_FREQ; - s = cmuSelect_USBPLL0; - break; - - case CMU_USB0CLKCTRL_CLKSEL_LFXO: - f = SystemLFXOClockGet(); - s = cmuSelect_LFXO; - break; - - case CMU_USB0CLKCTRL_CLKSEL_LFRCO: - f = SystemLFRCOClockGet(); - s = cmuSelect_LFRCO; - break; - - default: - s = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - if (freq != NULL) { - *freq = f; - } - if (sel != NULL) { - *sel = s; - } -} -#endif - -/** @endcond */ - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_SILICON_LABS_32B_SERIES_0) -/** The maximum allowed core frequency when using 0 wait-states on flash access. */ -#define CMU_MAX_FREQ_0WS 16000000 -/** The maximum allowed core frequency when using 1 wait-states on flash access */ -#define CMU_MAX_FREQ_1WS 32000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) -// EFR32xG1x and EFM32xG1x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) -// EFR32xG12x and EFM32xG12x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V1 21330000 -#define CMU_MAX_FREQ_1WS_1V1 32000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) -// EFR32xG13x and EFM32xG13x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) -// EFR32xG14x and EFM32xG14x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 40000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) -// EFM32GG11x -#define CMU_MAX_FREQ_0WS_1V2 18000000 -#define CMU_MAX_FREQ_1WS_1V2 36000000 -#define CMU_MAX_FREQ_2WS_1V2 54000000 -#define CMU_MAX_FREQ_3WS_1V2 72000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) -// EFM32TG11x -#define CMU_MAX_FREQ_0WS_1V2 25000000 -#define CMU_MAX_FREQ_1WS_1V2 48000000 -#define CMU_MAX_FREQ_0WS_1V0 10000000 -#define CMU_MAX_FREQ_1WS_1V0 21000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) -// EFM32GG12x -#define CMU_MAX_FREQ_0WS_1V2 18000000 -#define CMU_MAX_FREQ_1WS_1V2 36000000 -#define CMU_MAX_FREQ_2WS_1V2 54000000 -#define CMU_MAX_FREQ_3WS_1V2 72000000 -#define CMU_MAX_FREQ_0WS_1V0 7000000 -#define CMU_MAX_FREQ_1WS_1V0 14000000 -#define CMU_MAX_FREQ_2WS_1V0 20000000 - -#else -#error "Max Flash wait-state frequencies are not defined for this platform." -#endif - -/** The maximum frequency for the HFLE interface. */ -#if defined(CMU_CTRL_HFLE) -/** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_WONDER_FAMILY) \ - || defined(_EZR32_WONDER_FAMILY)) -#define CMU_MAX_FREQ_HFLE 24000000UL -/** The maximum HFLE frequency for other series 0 parts with maximum core clock - higher than 32 MHz. */ -#elif defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EZR32_LEOPARD_FAMILY)) -#define CMU_MAX_FREQ_HFLE maxFreqHfle() -#endif -#elif defined(CMU_CTRL_WSHFLE) -/** The maximum HFLE frequency for series 1 parts. */ -#define CMU_MAX_FREQ_HFLE 32000000UL -#endif - -#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) -#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) -#elif defined(CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) -#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) -#endif - -#if defined(CMU_HFXOCTRL_MODE_EXTCLK) -/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ -#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK -#endif - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) -#define VSCALE_DEFAULT ((int)EMU_VScaleGet()) -#else -#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; -#endif -#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) -#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) -#endif - -#if defined(CMU_OSCENCMD_DPLLEN) -/** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and - an optional band enumerator. */ -static const struct hfrcoCtrlTableElement{ - uint32_t minFreq; - uint32_t maxFreq; - uint32_t value; - CMU_HFRCOFreq_TypeDef band; -} hfrcoCtrlTable[] = -{ - // minFreq maxFreq HFRCOCTRL value band - { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, - { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, - { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, - { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, - { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, - { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, - { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, - { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, - { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, - { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) - { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, - { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, - { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, - { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) - { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, - { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } -#else - #error "HFRCOCTRL values not set for this platform." -#endif -}; - -#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ - / sizeof(struct hfrcoCtrlTableElement)) -#endif // CMU_OSCENCMD_DPLLEN - -#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) -/* Devices with Voltage Scaling needs extra handling of wait states. */ -static const struct flashWsTableElement{ - uint32_t maxFreq; - uint8_t vscale; - uint8_t ws; -} flashWsTable[] = -{ -#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) - { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ - { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ - { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ - { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ - { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ - { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ - { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ -#else - { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ - { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ - { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ - { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ - { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ -#endif -}; - -#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ - || defined(_CMU_USHFRCOTUNE_MASK) -#ifndef EFM32_USHFRCO_STARTUP_FREQ -#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) -#endif - -static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; -#endif - -/******************************************************************************* - ************************** LOCAL PROTOTYPES ******************************* - ******************************************************************************/ -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); -#endif - -static void hfperClkSafePrescaler(void); -static void hfperClkOptimizedPrescaler(void); - -static uint16_t lfxo_precision = 0xFFFF; -static uint16_t hfxo_precision = 0xFFFF; - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_GIANT_FAMILY) \ - || defined(_EZR32_LEOPARD_FAMILY)) -/***************************************************************************//** - * @brief - * Return maximum allowed frequency for low energy peripherals. - ******************************************************************************/ -static uint32_t maxFreqHfle(void) -{ - uint16_t majorMinorRev; - - switch (SYSTEM_GetFamily()) { - case systemPartFamilyEfm32Leopard: - case systemPartFamilyEzr32Leopard: - /* CHIP MAJOR bit [5:0] */ - majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); - /* CHIP MINOR bit [7:4] */ - majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); - /* CHIP MINOR bit [3:0] */ - majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); - - if (majorMinorRev >= 0x0204) { - return 24000000; - } else { - return 32000000; - } - - case systemPartFamilyEfm32Giant: - return 32000000; - - default: - /* Invalid device family. */ - EFM_ASSERT(false); - return 0; - } -} -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Unified definitions for the HFLE wait-state and prescaler fields. */ -#if defined(CMU_CTRL_HFLE) -#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK -#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT -#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV -#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK -#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT -#elif defined(CMU_CTRL_WSHFLE) -#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK -#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT -#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC -#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK -#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT -#endif -/** @endcond */ - -/***************************************************************************//** - * @brief - * Set HFLE wait-states and HFCLKLE prescaler according to wanted HF clock. - * - * @param[in] hfFreq - * The HF clock frequency to use. - * This is: - * CORE clock on Series0 devices. - * HF clock on on Series1 devices. - ******************************************************************************/ -static void setHfLeConfig(uint32_t hfFreq) -{ - unsigned int hfleWs; - uint32_t hflePresc; - - /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the - fields are changed to more than 1 bit. */ - EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); - - /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is - above maxLeFreq. - - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ - - hfleWs = 1; - if (hfFreq <= CMU_MAX_FREQ_HFLE) { - hfleWs = 0; - hflePresc = 0; - } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { - hflePresc = 1; - } else { - hflePresc = 2; - } - BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); - GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) - | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); -} - -#if defined(_CMU_CTRL_HFLE_MASK) -/***************************************************************************//** - * @brief - * Get HFLE wait-state configuration. - * - * @return - * The current wait-state configuration. - ******************************************************************************/ -static uint32_t getHfLeConfig(void) -{ - uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); - return ws; -} -#endif -#endif - -/***************************************************************************//** - * @brief - * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, - * by default also as a debug clock. - * - * @return - * AUX Frequency in Hz. - ******************************************************************************/ -static uint32_t auxClkGet(void) -{ - uint32_t ret; - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) - ret = (uint32_t)auxHfrcoFreq; - -#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) - /* All series 0 families except EFM32G */ - switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { - case CMU_AUXHFRCOCTRL_BAND_1MHZ: - if ( SYSTEM_GetProdRev() >= 19 ) { - ret = 1200000; - } else { - ret = 1000000; - } - break; - - case CMU_AUXHFRCOCTRL_BAND_7MHZ: - if ( SYSTEM_GetProdRev() >= 19 ) { - ret = 6600000; - } else { - ret = 7000000; - } - break; - - case CMU_AUXHFRCOCTRL_BAND_11MHZ: - ret = 11000000; - break; - - case CMU_AUXHFRCOCTRL_BAND_14MHZ: - ret = 14000000; - break; - - case CMU_AUXHFRCOCTRL_BAND_21MHZ: - ret = 21000000; - break; - -#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) - case CMU_AUXHFRCOCTRL_BAND_28MHZ: - ret = 28000000; - break; -#endif - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - -#else - /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ - ret = 14000000; - -#endif - - return ret; -} - -#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ - || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) -/***************************************************************************//** - * @brief - * Get the HFSRCCLK frequency. - * - * @return - * HFSRCCLK Frequency in Hz. - ******************************************************************************/ -static uint32_t hfSrcClkGet(void) -{ - uint32_t ret; - - ret = SystemHFClockGet(); - return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT)); -} -#endif - -/***************************************************************************//** - * @brief - * Get the Debug Trace clock frequency. - * - * @return - * Debug Trace frequency in Hz. - ******************************************************************************/ -static uint32_t dbgClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get selected clock source */ - clk = CMU_ClockSelectGet(cmuClock_DBG); - - switch (clk) { - case cmuSelect_HFCLK: - ret = SystemHFClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) -/***************************************************************************//** - * @brief - * Get the ADC n asynchronous clock frequency. - * - * @return - * ADC n asynchronous frequency in Hz. - ******************************************************************************/ -static uint32_t adcAsyncClkGet(uint32_t adc) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - switch (adc) { - case 0: - clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); - break; - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case 1: - clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); - break; -#endif - - default: - EFM_ASSERT(false); - return 0; - } - - switch (clk) { - case cmuSelect_Disabled: - ret = 0; - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_HFSRCCLK: - ret = hfSrcClkGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_SDIOCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the SDIO reference clock frequency. - * - * @return - * SDIO reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t sdioRefClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_SDIOREF); - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_QSPICTRL_MASK) -/***************************************************************************//** - * @brief - * Get the QSPI n reference clock frequency. - * - * @return - * QSPI n reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t qspiRefClkGet(uint32_t qspi) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - switch (qspi) { - case 0: - clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); - break; - - default: - EFM_ASSERT(false); - return 0; - } - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_AUXHFRCO: - ret = auxClkGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(_CMU_PDMCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the PDM reference clock frequency. - * - * @return - * PDM reference clock frequency in Hz. - ******************************************************************************/ -static uint32_t pdmRefClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_PDMREF); - - switch (clk) { - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -#if defined(USBR_CLOCK_PRESENT) -/***************************************************************************//** - * @brief - * Get the USB rate clock frequency. - * - * @return - * USB rate clock frequency in Hz. - ******************************************************************************/ -static uint32_t usbRateClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - clk = CMU_ClockSelectGet(cmuClock_USBR); - - switch (clk) { - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; - - case cmuSelect_HFXO: - ret = SystemHFXOClockGet(); - break; - - case cmuSelect_HFXOX2: - ret = 2u * SystemHFXOClockGet(); - break; - - case cmuSelect_HFRCO: - ret = SystemHfrcoFreq; - break; - - case cmuSelect_LFXO: - ret = SystemLFXOClockGet(); - break; - - case cmuSelect_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - return ret; -} -#endif - -/***************************************************************************//** - * @brief - * Configure flash access wait states to support the given core clock - * frequency. - * - * @param[in] coreFreq - * The core clock frequency to configure flash wait-states. - * - * @param[in] vscale - * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. - ******************************************************************************/ -static void flashWaitStateControl(uint32_t coreFreq, int vscale) -{ - uint32_t mode; -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ -#endif - (void) vscale; /* vscale parameter is only used on some devices. */ - - /* Get mode and SCBTP enable. */ - mode = MSC_ReadCTRLGet() & _MSC_READCTRL_MODE_MASK; - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - /* Devices with MODE and SCBTP in the same register field. */ - switch (mode) { - case MSC_READCTRL_MODE_WS0: - case MSC_READCTRL_MODE_WS1: -#if defined(MSC_READCTRL_MODE_WS2) - case MSC_READCTRL_MODE_WS2: -#endif - scbtpEn = false; - break; - - default: /* WSxSCBTP */ - scbtpEn = true; - break; - } - - /* Set mode based on the core clock frequency and SCBTP enable. */ - if (false) { - } -#if defined(MSC_READCTRL_MODE_WS2) - else if (coreFreq > CMU_MAX_FREQ_1WS) { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); - } -#endif - else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); - } else { - mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); - } -#else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ - - if (coreFreq <= CMU_MAX_FREQ_0WS) { - mode = 0; - } else if (coreFreq <= CMU_MAX_FREQ_1WS) { - mode = 1; - } -#endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ -// End defined(_SILICON_LABS_32B_SERIES_0) - -#elif defined(_SILICON_LABS_32B_SERIES_1) -#if defined(_EMU_STATUS_VSCALE_MASK) - - /* These devices have specific requirements on the supported flash wait state - * depending on the frequency and voltage scale level. */ - uint32_t i; - for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { - if ((flashWsTable[i].vscale == (uint8_t)vscale) - && (coreFreq <= flashWsTable[i].maxFreq)) { - break; // Found a matching entry. - } - } - - if (i == FLASH_WS_TABLE_ENTRIES) { - mode = 3; // Worst case flash wait state for unsupported cases. - EFM_ASSERT(false); - } else { - mode = flashWsTable[i].ws; - } - mode = mode << _MSC_READCTRL_MODE_SHIFT; - -#else - /* Devices where MODE and SCBTP are in separate fields and where the device - * either does not support voltage scale or where the voltage scale does - * not impact the flash wait state configuration. */ - if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { - mode = 0; - } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { - mode = 1; - } -#if defined(MSC_READCTRL_MODE_WS2) - else if (coreFreq <= CMU_MAX_FREQ_2WS) { - mode = 2; - } -#endif -#if defined(MSC_READCTRL_MODE_WS3) - else if (coreFreq <= CMU_MAX_FREQ_3WS) { - mode = 3; - } -#endif - mode = mode << _MSC_READCTRL_MODE_SHIFT; -#endif -// End defined(_SILICON_LABS_32B_SERIES_1) - -#else -#error "Undefined 32B SERIES!" -#endif - - mode = (MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK) | mode; - MSC_ReadCTRLSet(mode); -} - -/***************************************************************************//** - * @brief - * Configure flash access wait states to the most conservative setting for - * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) - * setting. - ******************************************************************************/ -static void flashWaitStateMax(void) -{ - /* Make sure the MSC is unlocked */ - bool mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - flashWaitStateControl(SystemMaxCoreClockGet(), 0); - - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) -/***************************************************************************//** - * @brief - * Configure RAM access wait states to support the given core clock - * frequency. - * - * @param[in] coreFreq - * The core clock frequency to configure RAM wait-states. - * - * @param[in] vscale - * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. - ******************************************************************************/ -static void setRamWaitState(uint32_t coreFreq, int vscale) -{ - uint32_t limit = 38000000; - if (vscale == 2) { - limit = 16000000; - } - - if (coreFreq > limit) { - BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); - } else { - BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); - } -} -#endif - -#if defined(_MSC_CTRL_WAITMODE_MASK) -/***************************************************************************//** - * @brief - * Configure the wait state for peripheral accesses over the bus to support - * the given bus clock frequency. - * - * @param[in] busFreq - * A peripheral bus clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 2. - * - * @li 0 = 1.2 V (VSCALE2) - * @li 2 = 1.0 V (VSCALE0) - * ******************************************************************************/ -static void setBusWaitState(uint32_t busFreq, int vscale) -{ - if ((busFreq > 50000000) && (vscale == 0)) { - BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); - } else { - BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); - } -} -#endif - -#if defined(PLFRCO_PRESENT) -static bool deviceHasPlfrco(void) -{ - SYSTEM_ChipRevision_TypeDef rev; - - if (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) { - // check the xG13 rev and check if it's >= Rev A3 - SYSTEM_ChipRevisionGet(&rev); - return (rev.major > 1) || (rev.minor >= 3); - } else { - return false; - } -} -#endif - -/***************************************************************************//** - * @brief - * Configure various wait states to switch to a certain frequency - * and a certain voltage scale. - * - * @details - * This function will set up the necessary flash, bus, and RAM wait states. - * Updating the wait state configuration must be done before - * increasing the clock frequency and it must be done after decreasing the - * clock frequency. Updating the wait state configuration must be done before - * core voltage is decreased and it must be done after a core voltage is - * increased. - * - * @param[in] freq - * The core clock frequency to configure wait-states. - * - * @param[in] vscale - * The voltage scale to configure wait-states. Expected values are - * 0 or 2, higher number is lower voltage. - * - * @li 0 = 1.2 V (VSCALE2) - * @li 2 = 1.0 V (VSCALE0) - * - ******************************************************************************/ -void CMU_UpdateWaitStates(uint32_t freq, int vscale) -{ - /* Make sure the MSC is unlocked */ - bool mscLocked = MSC_LockGetLocked(); - MSC_LockSetUnlocked(); - - flashWaitStateControl(freq, vscale); -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) - setRamWaitState(freq, vscale); -#endif -#if defined(_MSC_CTRL_WAITMODE_MASK) - setBusWaitState(freq, vscale); -#endif - - if (mscLocked) { - MSC_LockSetLocked(); - } -} - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) -/***************************************************************************//** - * @brief - * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. - ******************************************************************************/ -static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) -{ - uint32_t regIshUpper; - const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK - >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; - /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ - regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); - regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; - return regIshUpper; -} -#endif - -#if defined(_CMU_HFXOCTRL_MASK) -/***************************************************************************//** - * @brief - * Get the HFXO tuning mode. - * - * @return - * The current HFXO tuning mode from the HFXOCTRL register. - ******************************************************************************/ -__STATIC_INLINE uint32_t getHfxoTuningMode(void) -{ -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; -#else - return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) - >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; -#endif -} - -/***************************************************************************//** - * @brief - * Set the HFXO tuning mode. - * - * @param[in] mode - * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or - * HFXO_TUNING_MODE_CMD. - ******************************************************************************/ -__STATIC_INLINE void setHfxoTuningMode(uint32_t mode) -{ -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); -#else - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) - | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Get the LFnCLK frequency based on the current configuration. - * - * @param[in] lfClkBranch - * Selected LF branch. - * - * @return - * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is - * returned. - ******************************************************************************/ -static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) -{ - uint32_t sel; - uint32_t ret = 0; - - switch (lfClkBranch) { - case cmuClock_LFA: - case cmuClock_LFB: -#if defined(_CMU_LFCCLKEN0_MASK) - case cmuClock_LFC: -#endif -#if defined(_CMU_LFECLKSEL_MASK) - case cmuClock_LFE: -#endif - break; - - default: - EFM_ASSERT(false); - break; - } - - sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); - - /* Get clock select field */ - switch (lfClkBranch) { - case cmuClock_LFA: -#if defined(_CMU_LFCLKSEL_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; -#elif defined(_CMU_LFACLKSEL_MASK) - sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; - - case cmuClock_LFB: -#if defined(_CMU_LFCLKSEL_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; -#elif defined(_CMU_LFBCLKSEL_MASK) - sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; - -#if defined(_CMU_LFCCLKEN0_MASK) - case cmuClock_LFC: -#if defined(_CMU_LFCLKSEL_LFC_MASK) - sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; -#elif defined(_CMU_LFCCLKSEL_LFC_MASK) - sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; -#else - EFM_ASSERT(false); -#endif - break; -#endif - -#if defined(_CMU_LFECLKSEL_MASK) - case cmuClock_LFE: - sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - /* Get the clock frequency. */ -#if defined(_CMU_LFCLKSEL_MASK) - switch (sel) { - case _CMU_LFCLKSEL_LFA_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - case _CMU_LFCLKSEL_LFA_LFXO: - ret = SystemLFXOClockGet(); - break; - -#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) - case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: -#if defined(CMU_MAX_FREQ_HFLE) - /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the - * frequency of CMU_HFCORECLKLEDIV2. */ - ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); -#else - ret = SystemCoreClockGet() / 2U; -#endif - break; -#endif - - case _CMU_LFCLKSEL_LFA_DISABLED: - ret = 0; -#if defined(CMU_LFCLKSEL_LFAE) - /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ - if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { - if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA - ? _CMU_LFCLKSEL_LFAE_SHIFT - : _CMU_LFCLKSEL_LFBE_SHIFT)) { - ret = SystemULFRCOClockGet(); - } - } -#endif - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } -#endif /* _CMU_LFCLKSEL_MASK */ - -#if defined(_CMU_LFACLKSEL_MASK) - switch (sel) { - case _CMU_LFACLKSEL_LFA_LFRCO: - ret = SystemLFRCOClockGet(); - break; - - case _CMU_LFACLKSEL_LFA_LFXO: - ret = SystemLFXOClockGet(); - break; - - case _CMU_LFACLKSEL_LFA_ULFRCO: - ret = SystemULFRCOClockGet(); - break; - -#if defined(PLFRCO_PRESENT) - case _CMU_LFACLKSEL_LFA_PLFRCO: - ret = SystemLFRCOClockGet(); - break; -#endif - -#if defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) - case _CMU_LFBCLKSEL_LFB_HFCLKLE: - ret = SystemHFClockGet() - / SL_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) - >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); - break; -#endif - - case _CMU_LFACLKSEL_LFA_DISABLED: - ret = 0; - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } -#endif - - return ret; -} - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to low-frequency domain to complete. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void syncReg(uint32_t mask) -{ - /* Avoid a deadlock if modifying the same register twice when freeze mode is */ - /* activated. */ - if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { - return; - } - - /* Wait for any pending previous write operation to complete */ - /* in low-frequency domain. */ - while ((CMU->SYNCBUSY & mask) != 0UL) { - } -} - -#if defined(USBC_CLOCK_PRESENT) -/***************************************************************************//** - * @brief - * Get the USBC frequency. - * - * @return - * USBC frequency in Hz. - ******************************************************************************/ -static uint32_t usbCClkGet(void) -{ - uint32_t ret; - CMU_Select_TypeDef clk; - - /* Get the selected clock source. */ - clk = CMU_ClockSelectGet(cmuClock_USBC); - - switch (clk) { - case cmuSelect_LFXO: - ret = SystemLFXOClockGet(); - break; - case cmuSelect_LFRCO: - ret = SystemLFRCOClockGet(); - break; -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuSelect_USHFRCO: - ret = ushfrcoFreq; - break; -#endif - case cmuSelect_HFCLK: - ret = SystemHFClockGet(); - break; - default: - /* Clock is not enabled */ - ret = 0; - break; - } - return ret; -} -#endif - -/***************************************************************************//** - * @brief - * Set HFPER clock tree prescalers to safe values. - * - * @note - * This function applies to EFM32GG11B. There are 3 HFPER clock trees with - * these frequency limits: - * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. - * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - ******************************************************************************/ -static void hfperClkSafePrescaler(void) -{ -#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ - && defined(_CMU_HFPERPRESCC_MASK) - // Assuming a maximum HFCLK of 72MHz, set prescalers to DIV4. - CMU_ClockPrescSet(cmuClock_HFPER, 3U); - CMU_ClockPrescSet(cmuClock_HFPERB, 3U); - CMU_ClockPrescSet(cmuClock_HFPERC, 3U); -#endif -} - -/***************************************************************************//** - * @brief - * Set HFPER clock tree prescalers to give highest possible clock node - * frequency while still beeing within spec. - * - * @note - * This function applies to EFM32GG11B. There are 3 HFPER clock trees with - * these frequency limits: - * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. - * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. - ******************************************************************************/ -static void hfperClkOptimizedPrescaler(void) -{ -#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ - && defined(_CMU_HFPERPRESCC_MASK) - uint32_t hfClkFreq, divisor; - - hfClkFreq = SystemHFClockGet(); - - if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { - divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) - if (divisor > 0U) { - divisor--; // Convert to prescaler - } - CMU_ClockPrescSet(cmuClock_HFPER, divisor); - CMU_ClockPrescSet(cmuClock_HFPERB, divisor); - CMU_ClockPrescSet(cmuClock_HFPERC, divisor); - } else { - divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; - if (divisor > 0U) { - divisor--; - } - CMU_ClockPrescSet(cmuClock_HFPER, divisor); - CMU_ClockPrescSet(cmuClock_HFPERC, divisor); - - divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; - if (divisor > 0U) { - divisor--; - } - CMU_ClockPrescSet(cmuClock_HFPERB, divisor); - } -#endif -} - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Get the AUXHFRCO band in use. - * - * @return - * AUXHFRCO band in use. - ******************************************************************************/ -CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) -{ - return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL - & _CMU_AUXHFRCOCTRL_BAND_MASK) - >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); -} -#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Set the AUXHFRCO band and the tuning value based on the value in the - * calibration table made during production. - * - * @param[in] band - * AUXHFRCO band to activate. - ******************************************************************************/ -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) -{ - uint32_t tuning; - - /* Read a tuning value from the calibration table. */ - switch (band) { - case cmuAUXHFRCOBand_1MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; - break; - - case cmuAUXHFRCOBand_7MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; - break; - - case cmuAUXHFRCOBand_11MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; - break; - - case cmuAUXHFRCOBand_14MHz: - tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) - >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; - break; - - case cmuAUXHFRCOBand_21MHz: - tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) - >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; - break; - -#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) - case cmuAUXHFRCOBand_28MHz: - tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) - >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* Set band/tuning. */ - CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL - & ~(_CMU_AUXHFRCOCTRL_BAND_MASK - | _CMU_AUXHFRCOCTRL_TUNING_MASK)) - | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) - | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -} -#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the AUXHFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * AUXHFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) -{ - switch (freq) { - /* 1, 2, and 4 MHz share the same calibration word. */ - case cmuAUXHFRCOFreq_1M0Hz: - case cmuAUXHFRCOFreq_2M0Hz: - case cmuAUXHFRCOFreq_4M0Hz: - return DEVINFO->AUXHFRCOCAL0; - - case cmuAUXHFRCOFreq_7M0Hz: - return DEVINFO->AUXHFRCOCAL3; - - case cmuAUXHFRCOFreq_13M0Hz: - return DEVINFO->AUXHFRCOCAL6; - - case cmuAUXHFRCOFreq_16M0Hz: - return DEVINFO->AUXHFRCOCAL7; - - case cmuAUXHFRCOFreq_19M0Hz: - return DEVINFO->AUXHFRCOCAL8; - - case cmuAUXHFRCOFreq_26M0Hz: - return DEVINFO->AUXHFRCOCAL10; - - case cmuAUXHFRCOFreq_32M0Hz: - return DEVINFO->AUXHFRCOCAL11; - - case cmuAUXHFRCOFreq_38M0Hz: - return DEVINFO->AUXHFRCOCAL12; - -#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) - case cmuAUXHFRCOFreq_48M0Hz: - return DEVINFO->AUXHFRCOCAL13; -#endif -#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) - case cmuAUXHFRCOFreq_50M0Hz: - return DEVINFO->AUXHFRCOCAL14; -#endif - - default: /* cmuAUXHFRCOFreq_UserDefined */ - return 0; - } -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/***************************************************************************//** - * @brief - * Get the current AUXHFRCO frequency. - * - * @return - * AUXHFRCO frequency. - ******************************************************************************/ -CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) -{ - return auxHfrcoFreq; -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) -/***************************************************************************//** - * @brief - * Set AUXHFRCO calibration for the selected target frequency. - * - * @param[in] setFreq - * AUXHFRCO frequency to set - ******************************************************************************/ -void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - - /* Get DEVINFO index and set global auxHfrcoFreq. */ - freqCal = CMU_AUXHFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - auxHfrcoFreq = setFreq; - - /* Wait for any previous sync to complete, then set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { - } - - /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ - switch (setFreq) { - case cmuAUXHFRCOFreq_1M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; - break; - - case cmuAUXHFRCOFreq_2M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; - break; - - case cmuAUXHFRCOFreq_4M0Hz: - freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) - | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; - break; - - default: - break; - } - CMU->AUXHFRCOCTRL = freqCal; -} -#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ - -/***************************************************************************//** - * @brief - * Calibrate the clock. - * - * @details - * Run a calibration for HFCLK against a selectable reference clock. - * See the reference manual, CMU chapter, for more details. - * - * @note - * This function will not return until the calibration measurement is completed. - * - * @param[in] HFCycles - * The number of HFCLK cycles to run the calibration. Increasing this number - * increases precision but the calibration will take more time. - * - * @param[in] reference - * The reference clock used to compare HFCLK. - * - * @return - * The number of ticks the reference clock after HFCycles ticks on the HF - * clock. - ******************************************************************************/ -uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) -{ - EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); - - /* Set the reference clock source. */ - switch (reference) { - case cmuOsc_LFXO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuOsc_LFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuOsc_HFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - return 0; - } - - /* Set the top value. */ - CMU->CALCNT = HFCycles; - - /* Start the calibration. */ - CMU->CMD = CMU_CMD_CALSTART; - -#if defined(CMU_STATUS_CALRDY) - /* Wait until calibration completes. */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { - } -#else - /* Wait until calibration completes. */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - - return CMU->CALCNT; -} - -#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) -/***************************************************************************//** - * @brief - * Configure the clock calibration. - * - * @details - * Configure a calibration for a selectable clock source against another - * selectable reference clock. - * See the reference manual, CMU chapter, for more details. - * - * @note - * After configuration, a call to @ref CMU_CalibrateStart() is required and - * the resulting calibration value can be read out with the - * @ref CMU_CalibrateCountGet() function call. - * - * @param[in] downCycles - * The number of downSel clock cycles to run the calibration. Increasing this - * number increases precision but the calibration will take more time. - * - * @param[in] downSel - * The clock, which will be counted down downCycles. - * - * @param[in] upSel - * The reference clock; the number of cycles generated by this clock will - * be counted and added up and the result can be given with the - * @ref CMU_CalibrateCountGet() function call. - ******************************************************************************/ -void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, - CMU_Osc_TypeDef upSel) -{ - /* Keep configuration settings untouched. */ - uint32_t calCtrl = CMU->CALCTRL - & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); - - /* 20 bits of precision to calibration count register. */ - EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); - - /* Set down counting clock source - down counter. */ - switch (downSel) { - case cmuOsc_LFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; - break; - - case cmuOsc_LFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; - break; - - case cmuOsc_HFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - /* Set the top value to be counted down by the downSel clock. */ - CMU->CALCNT = downCycles; - - /* Set the reference clock source - up counter. */ - switch (upSel) { - case cmuOsc_LFXO: - calCtrl |= CMU_CALCTRL_UPSEL_LFXO; - break; - - case cmuOsc_LFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_PLFRCO; - break; -#endif - - case cmuOsc_HFXO: - calCtrl |= CMU_CALCTRL_UPSEL_HFXO; - break; - - case cmuOsc_HFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; - break; - - case cmuOsc_AUXHFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; - break; - -#if defined (_CMU_USHFRCOCTRL_MASK) - case cmuOsc_USHFRCO: - calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - - CMU->CALCTRL = calCtrl; -} -#endif - -/***************************************************************************//** - * @brief - * Get the calibration count register. - * @note - * If continuous calibration mode is active, calibration busy will almost - * always be off and only the value needs to be read. In a normal case, - * this function call is triggered by the CALRDY - * interrupt flag. - * @return - * The calibration count, the number of UPSEL clocks - * in the period of DOWNSEL oscillator clock cycles configured by a previous - * write operation to CMU->CALCNT. - ******************************************************************************/ -uint32_t CMU_CalibrateCountGet(void) -{ - /* Wait until calibration completes, UNLESS continuous calibration mode is */ - /* active. */ -#if defined(CMU_CALCTRL_CONT) - if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { -#if defined(CMU_STATUS_CALRDY) - /* Wait until calibration completes */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { - } -#else - /* Wait until calibration completes */ - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - } -#else - while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { - } -#endif - return CMU->CALCNT; -} - -/***************************************************************************//** - * @brief - * Get the clock divisor/prescaler. - * - * @param[in] clock - * A clock point to get the divisor/prescaler for. Notice that not all clock points - * have a divisor/prescaler. See the CMU overview in the reference manual. - * - * @return - * The current clock point divisor/prescaler. 1 is returned - * if @p clock specifies a clock point without a divisor/prescaler. - ******************************************************************************/ -CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - return 1UL + (uint32_t)CMU_ClockPrescGet(clock); - -#elif defined(_SILICON_LABS_32B_SERIES_0) - uint32_t divReg; - CMU_ClkDiv_TypeDef ret; - - /* Get divisor reg ID. */ - divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; - - switch (divReg) { -#if defined(_CMU_CTRL_HFCLKDIV_MASK) - case CMU_HFCLKDIV_REG: - ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) - >> _CMU_CTRL_HFCLKDIV_SHIFT); - break; -#endif - - case CMU_HFPERCLKDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV - & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - - case CMU_HFCORECLKDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV - & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) - >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - case CMU_HFCORECLKLEDIV_REG: - ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV - & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - >> _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); - ret = SL_Log2ToDiv(ret + 1U); - break; -#endif - - case CMU_LFAPRESC0_REG: - switch (clock) { - case cmuClock_RTC: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT); - ret = SL_Log2ToDiv(ret); - break; - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCDpre: - ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT) - + CMU_DivToLog2(cmuClkDiv_16)); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT); - ret = SL_Log2ToDiv(ret); - break; -#endif - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - break; - - default: - ret = cmuClkDiv_1; - EFM_ASSERT(false); - break; - } - - return ret; -#endif -} - -/***************************************************************************//** - * @brief - * Set the clock divisor/prescaler. - * - * @note - * If setting an LF clock prescaler, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * Clock point to set divisor/prescaler for. Notice that not all clock points - * have a divisor/prescaler. See the CMU overview in the reference - * manual. - * - * @param[in] div - * The clock divisor to use (<= cmuClkDiv_512). - ******************************************************************************/ -void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); - -#elif defined(_SILICON_LABS_32B_SERIES_0) - uint32_t freq; - uint32_t divReg; - - /* Get the divisor reg ID. */ - divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; - - switch (divReg) { -#if defined(_CMU_CTRL_HFCLKDIV_MASK) - case CMU_HFCLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); - - /* Configure worst case wait states for flash access before setting divisor. */ - flashWaitStateMax(); - - /* Set the divider. */ - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) - | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); - - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - - /* Optimize flash access wait state setting for the current core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - break; -#endif - - case CMU_HFPERCLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); - break; - -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - case CMU_HFCORECLKLEDIV_REG: - /* - This divisor is usually set when changing HF clock to keep HFLE clock - within safe bounds. This code path ignore these constraints. - */ - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div) - 1U; - CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV - & ~_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - | (div << _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); - break; -#endif - - case CMU_HFCORECLKDIV_REG: - EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); - - /* Configure worst case wait states for flash access before setting the divisor. */ - flashWaitStateMax(); - -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet() / div); -#endif - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV - & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) - | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); - - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - - /* Optimize wait state setting for the current core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(freq); -#endif - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { - case cmuClock_RTC: - EFM_ASSERT(div <= cmuClkDiv_32768); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) - | (div << _CMU_LFAPRESC0_RTC_SHIFT); - break; - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - EFM_ASSERT(div <= cmuClkDiv_32768); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) - | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); - break; -#endif - -#if defined(LCD_PRESENT) - case cmuClock_LCDpre: - EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) - | ((div - CMU_DivToLog2(cmuClkDiv_16)) - << _CMU_LFAPRESC0_LCD_SHIFT); - break; -#endif /* defined(LCD_PRESENT) */ - -#if defined(LESENSE_PRESENT) - case cmuClock_LESENSE: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) - | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); - break; -#endif /* defined(LESENSE_PRESENT) */ - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) - | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - EFM_ASSERT(div <= cmuClkDiv_8); - - /* LF register about to be modified requires sync. busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - /* Convert to the correct scale. */ - div = CMU_DivToLog2(div); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) - | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - default: - EFM_ASSERT(false); - break; - } -#endif -} - -/***************************************************************************//** - * @brief - * Enable/disable a clock. - * - * @details - * In general, module clocking is disabled after a reset. If a module - * clock is disabled, the registers of that module are not accessible and - * reading from such registers may return undefined values. Writing to - * registers of clock-disabled modules has no effect. - * Avoid accessing module registers of a module with a disabled clock. - * - * @note - * If enabling/disabling an LF clock, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * The clock to enable/disable. Notice that not all defined clock - * points have separate enable/disable control. See the CMU overview - * in the reference manual. - * - * @param[in] enable - * @li true - enable specified clock. - * @li false - disable specified clock. - ******************************************************************************/ -void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) -{ - volatile uint32_t *reg; - uint32_t bit; - uint32_t sync = 0; - - /* Identify enable register */ - switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { -#if defined(_CMU_CTRL_HFPERCLKEN_MASK) - case CMU_CTRL_EN_REG: - reg = &CMU->CTRL; - break; -#endif - -#if defined(_CMU_HFCORECLKEN0_MASK) - case CMU_HFCORECLKEN0_EN_REG: - reg = &CMU->HFCORECLKEN0; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif - break; -#endif - -#if defined(_CMU_HFBUSCLKEN0_MASK) - case CMU_HFBUSCLKEN0_EN_REG: - reg = &CMU->HFBUSCLKEN0; - break; -#endif - -#if defined(_CMU_HFPERCLKDIV_MASK) - case CMU_HFPERCLKDIV_EN_REG: - reg = &CMU->HFPERCLKDIV; - break; -#endif - - case CMU_HFPERCLKEN0_EN_REG: - reg = &CMU->HFPERCLKEN0; - break; - -#if defined(_CMU_HFPERCLKEN1_MASK) - case CMU_HFPERCLKEN1_EN_REG: - reg = &CMU->HFPERCLKEN1; - break; -#endif - - case CMU_LFACLKEN0_EN_REG: - reg = &CMU->LFACLKEN0; - sync = CMU_SYNCBUSY_LFACLKEN0; - break; - - case CMU_LFBCLKEN0_EN_REG: - reg = &CMU->LFBCLKEN0; - sync = CMU_SYNCBUSY_LFBCLKEN0; - break; - -#if defined(_CMU_LFCCLKEN0_MASK) - case CMU_LFCCLKEN0_EN_REG: - reg = &CMU->LFCCLKEN0; - sync = CMU_SYNCBUSY_LFCCLKEN0; - break; -#endif - -#if defined(_CMU_LFECLKEN0_MASK) - case CMU_LFECLKEN0_EN_REG: - reg = &CMU->LFECLKEN0; - sync = CMU_SYNCBUSY_LFECLKEN0; - break; -#endif - -#if defined(_CMU_SDIOCTRL_MASK) - case CMU_SDIOREF_EN_REG: - reg = &CMU->SDIOCTRL; - enable = !enable; - break; -#endif - -#if defined(_CMU_QSPICTRL_MASK) - case CMU_QSPI0REF_EN_REG: - reg = &CMU->QSPICTRL; - enable = !enable; - break; -#endif -#if defined(_CMU_USBCTRL_MASK) - case CMU_USBRCLK_EN_REG: - reg = &CMU->USBCTRL; - break; -#endif -#if defined(_CMU_PDMCTRL_MASK) - case CMU_PDMREF_EN_REG: - reg = &CMU->PDMCTRL; - break; -#endif - - case CMU_PCNT_EN_REG: - reg = &CMU->PCNTCTRL; - break; - - default: /* Cannot enable/disable a clock point. */ - EFM_ASSERT(false); - return; - } - - /* Get the bit position used to enable/disable. */ - bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; - - /* LF synchronization required. */ - if (sync > 0UL) { - syncReg(sync); - } - - /* Set/clear bit as requested. */ - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Get the clock frequency for a clock point. - * - * @param[in] clock - * A clock point to fetch the frequency for. - * - * @return - * The current frequency in Hz. - ******************************************************************************/ -uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) -{ - uint32_t ret; - - switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { - case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - break; - - case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPER divider. */ -#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) - >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; -#endif -#if defined(_CMU_HFPERPRESC_PRESC_MASK) - ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) - >> _CMU_HFPERPRESC_PRESC_SHIFT); -#endif - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPERB prescaler. */ - ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) - >> _CMU_HFPERPRESCB_PRESC_SHIFT); - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - /* Calculate frequency after HFPERC prescaler. */ - ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) - >> _CMU_HFPERPRESCC_PRESC_SHIFT); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -#if defined(CRYPTO_PRESENT) \ - || defined(LDMA_PRESENT) \ - || defined(GPCRC_PRESENT) \ - || defined(PRS_PRESENT) \ - || defined(GPIO_PRESENT) - case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); -#if defined(_CMU_HFBUSPRESC_MASK) - ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) - >> _CMU_HFBUSPRESC_PRESC_SHIFT); -#endif - break; -#endif - - case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) - >> _CMU_HFCOREPRESC_PRESC_SHIFT); - break; - - case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = SystemHFClockGet(); - ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) - >> _CMU_HFEXPPRESC_PRESC_SHIFT); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(AES_PRESENT) \ - || defined(DMA_PRESENT) \ - || defined(EBI_PRESENT) \ - || defined(USB_PRESENT) - case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - { - ret = SystemCoreClockGet(); - } break; -#endif -#endif - - case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - break; - -#if defined(_CMU_LFACLKEN0_RTC_MASK) - case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT; - break; -#endif - -#if defined(_CMU_LFECLKEN0_RTCC_MASK) - case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFE); - ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) - >> _CMU_LFEPRESC0_RTCC_SHIFT; - break; -#endif - -#if defined(_CMU_LFACLKEN0_LETIMER0_MASK) - case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFACLKEN0_LETIMER1_MASK) - case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFACLKEN0_LCD_MASK) - case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT) - + CMU_DivToLog2(cmuClkDiv_16); -#else - ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT); -#endif - break; - -#if defined(_CMU_LCDCTRL_MASK) - case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT; - ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) - >> _CMU_LCDCTRL_FDIV_SHIFT); - break; -#endif -#endif - -#if defined(_CMU_LFACLKEN0_LESENSE_MASK) - case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFA); - ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT; - break; -#endif - - case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); - break; - -#if defined(_CMU_LFBCLKEN0_LEUART0_MASK) - case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFBCLKEN0_LEUART1_MASK) - case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); -#if defined(_SILICON_LABS_32B_SERIES_0) - ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT; -#else - ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFBCLKEN0_CSEN_MASK) - case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFB); - ret /= SL_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) - >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); - break; -#endif - -#if defined(CMU_LFCCLKEN0_USB) - case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFC); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) - case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = lfClkGet(cmuClock_LFE); - break; -#endif - - case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = dbgClkGet(); - break; - - case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = auxClkGet(); - break; - -#if defined(USBC_CLOCK_PRESENT) - case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = usbCClkGet(); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = adcAsyncClkGet(0); -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = adcAsyncClkGet(1); -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = sdioRefClkGet(); - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = qspiRefClkGet(0); - break; -#endif - -#if defined(USBR_CLOCK_PRESENT) - case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = usbRateClkGet(); - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): - ret = pdmRefClkGet(); - break; -#endif - - case (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): -#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) - ret = SystemCoreClockGet() / CMU_ClockDivGet(clock); -#elif defined(_CMU_HFPRESC_HFCLKLEPRESC_MASK) - ret = SystemHFClockGet() / CMU_ClockDivGet(clock); -#else - ret = SystemCoreClockGet() / 2; -#endif - break; - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - - return ret; -} - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Get the clock prescaler. - * - * @param[in] clock - * A clock point to get the prescaler for. Notice that not all clock points - * have a prescaler. See the CMU overview in the reference manual. - * - * @return - * The prescaler value of the current clock point. 0 is returned - * if @p clock specifies a clock point without a prescaler. - ******************************************************************************/ -uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) -{ - uint32_t prescReg; - uint32_t ret; - - /* Get the prescaler register ID. */ - prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; - - switch (prescReg) { - case CMU_HFPRESC_REG: - ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT; - break; - - case CMU_HFEXPPRESC_REG: - ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) - >> _CMU_HFEXPPRESC_PRESC_SHIFT; - break; - - case CMU_HFCLKLEPRESC_REG: - ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) - >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; - ret = SL_Log2ToDiv(ret + 1U) - 1U; - break; - - case CMU_HFPERPRESC_REG: - ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) - >> _CMU_HFPERPRESC_PRESC_SHIFT; - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case CMU_HFPERPRESCB_REG: - ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) - >> _CMU_HFPERPRESCB_PRESC_SHIFT; - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case CMU_HFPERPRESCC_REG: - ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) - >> _CMU_HFPERPRESCC_PRESC_SHIFT; - break; -#endif - - case CMU_HFCOREPRESC_REG: - ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) - >> _CMU_HFCOREPRESC_PRESC_SHIFT; - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) - >> _CMU_LFAPRESC0_LETIMER0_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) - >> _CMU_LFAPRESC0_LESENSE_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) - case cmuClock_LETIMER1: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) - >> _CMU_LFAPRESC0_LETIMER1_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCD: - case cmuClock_LCDpre: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) - >> _CMU_LFAPRESC0_LCD_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFAPRESC0_RTC_MASK) - case cmuClock_RTC: - ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) - >> _CMU_LFAPRESC0_RTC_SHIFT; - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) - >> _CMU_LFBPRESC0_LEUART0_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) - >> _CMU_LFBPRESC0_LEUART1_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret) - 1U; - break; -#endif - -#if defined(_CMU_LFBPRESC0_CSEN_MASK) - case cmuClock_CSEN_LF: - ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) - >> _CMU_LFBPRESC0_CSEN_SHIFT; - /* Convert the exponent to a prescaler value. */ - ret = SL_Log2ToDiv(ret + 4U) - 1U; - break; -#endif - - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFEPRESC0_REG: - switch (clock) { -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: - ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) - >> _CMU_LFEPRESC0_RTCC_SHIFT; - break; - - default: - ret = 0U; - EFM_ASSERT(false); - break; -#endif - } - break; - -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ - || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case CMU_ADCASYNCDIV_REG: - switch (clock) { -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - case cmuClock_ADC0ASYNC: - ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; - break; -#endif -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case cmuClock_ADC1ASYNC: - ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) - >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; - break; -#endif - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(_CMU_HFBUSPRESC_MASK) - case CMU_HFBUSPRESC_REG: - ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) - >> _CMU_HFBUSPRESC_PRESC_SHIFT; - break; -#endif - default: - ret = 0U; - EFM_ASSERT(false); - break; - } - - return ret; -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Set the clock prescaler. - * - * @note - * If setting an LF clock prescaler, synchronization into the low-frequency - * domain is required. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. See @ref CMU_FreezeEnable() for - * a suggestion on how to reduce the stalling time in some use cases. - * - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * A clock point to set the prescaler for. Notice that not all clock points - * have a prescaler. See the CMU overview in the reference manual. - * - * @param[in] presc - * The clock prescaler. The prescaler value is linked to the clock divider by: - * divider = 'presc' + 1. - ******************************************************************************/ -void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) -{ - uint32_t freq; - uint32_t prescReg; - - /* Get the divisor reg ID. */ - prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; - - switch (prescReg) { - case CMU_HFPRESC_REG: - EFM_ASSERT(presc < 32U); - - /* Configure worst case wait-states for flash and HFLE, set safe HFPER - clock-tree prescalers. */ - flashWaitStateMax(); - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); - hfperClkSafePrescaler(); - - CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) - | (presc << _CMU_HFPRESC_PRESC_SHIFT); - - /* Update the CMSIS core clock variable (this function updates the global - variable). */ - freq = SystemCoreClockGet(); - /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree - prescalers. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - setHfLeConfig(SystemHFClockGet()); - hfperClkOptimizedPrescaler(); - break; - - case CMU_HFEXPPRESC_REG: - EFM_ASSERT(presc < 32U); - - CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) - | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); - break; - - case CMU_HFCLKLEPRESC_REG: - presc = CMU_DivToLog2(presc); - CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) - | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); - break; - - case CMU_HFPERPRESC_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) - | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); - break; - -#if defined(_CMU_HFPERPRESCB_MASK) - case CMU_HFPERPRESCB_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) - | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); - break; -#endif - -#if defined(_CMU_HFPERPRESCC_MASK) - case CMU_HFPERPRESCC_REG: - EFM_ASSERT(presc < 512U); - CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) - | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); - break; -#endif - - case CMU_HFCOREPRESC_REG: - EFM_ASSERT(presc < 512U); - - /* Configure worst case wait-states for flash. */ - flashWaitStateMax(); - - CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) - | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); - - /* Update the CMSIS core clock variable (this function updates the global variable). - Optimize flash and HFLE wait states. */ - freq = SystemCoreClockGet(); - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - break; - - case CMU_LFAPRESC0_REG: - switch (clock) { -#if defined(RTC_PRESENT) - case cmuClock_RTC: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) - | (presc << _CMU_LFAPRESC0_RTC_SHIFT); - break; -#endif - -#if defined(RTCC_PRESENT) - case cmuClock_RTCC: -#if defined(_CMU_LFEPRESC0_RTCC_MASK) -#if defined(_CMU_LFEPRESC0_RTCC_DIV4) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); -#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); -#else - EFM_ASSERT(presc <= 0U); -#endif - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFEPRESC0); - - CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) - | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); -#else - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) - | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); -#endif - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) - case cmuClock_LETIMER0: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) - | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) - case cmuClock_LETIMER1: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) - | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LESENSE_MASK) - case cmuClock_LESENSE: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) - | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); - break; -#endif - -#if defined(_CMU_LFAPRESC0_LCD_MASK) - case cmuClock_LCDpre: - case cmuClock_LCD: - EFM_ASSERT(presc <= 32768U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFAPRESC0); - - CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) - | (presc << _CMU_LFAPRESC0_LCD_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFBPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFBPRESC0_LEUART0_MASK) - case cmuClock_LEUART0: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) - | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_LEUART1_MASK) - case cmuClock_LEUART1: - EFM_ASSERT(presc <= 8U); - - /* Convert the prescaler value to a DIV exponent scale. */ - presc = CMU_PrescToLog2(presc); - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) - | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); - break; -#endif - -#if defined(_CMU_LFBPRESC0_CSEN_MASK) - case cmuClock_CSEN_LF: - EFM_ASSERT((presc <= 127U) && (presc >= 15U)); - - /* Convert the prescaler value to a DIV exponent scale. - * DIV16 is the lowest supported prescaler. */ - presc = CMU_PrescToLog2(presc) - 4U; - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFBPRESC0); - - CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) - | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - - case CMU_LFEPRESC0_REG: - switch (clock) { -#if defined(_CMU_LFEPRESC0_RTCC_MASK) - case cmuClock_RTCC: -#if defined(_CMU_LFEPRESC0_RTCC_DIV4) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); -#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) - EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); -#else - EFM_ASSERT(presc <= 0U); -#endif - - /* LF register about to be modified requires sync. Busy check. */ - syncReg(CMU_SYNCBUSY_LFEPRESC0); - - CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) - | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } - break; - -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ - || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case CMU_ADCASYNCDIV_REG: - switch (clock) { -#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) - case cmuClock_ADC0ASYNC: - EFM_ASSERT(presc <= 3); - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) - | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) - case cmuClock_ADC1ASYNC: - EFM_ASSERT(presc <= 3); - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) - | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); - break; -#endif - default: - EFM_ASSERT(false); - break; - } - break; -#endif - -#if defined(_CMU_HFBUSPRESC_MASK) - case CMU_HFBUSPRESC_REG: - EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); - CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) - | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} -#endif - -/***************************************************************************//** - * @brief - * Get the currently selected reference clock used for a clock branch. - * - * @param[in] clock - * Clock branch to fetch selected ref. clock for. One of: - * @li #cmuClock_HF - * @li #cmuClock_LFA - * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO - * @li #cmuClock_LFC - * @endif @if _SILICON_LABS_32B_SERIES_1 - * @li #cmuClock_LFE - * @endif - * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT - * @li #cmuClock_USBC - * @endif - * - * @return - * The reference clock used for clocking the selected branch, #cmuSelect_Error if - * invalid @p clock provided. - ******************************************************************************/ -CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef ret = cmuSelect_Disabled; - uint32_t selReg; - - selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; - - switch (selReg) { - case CMU_HFCLKSEL_REG: -#if defined(_CMU_HFCLKSTATUS_MASK) - switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { - case CMU_HFCLKSTATUS_SELECTED_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_HFCLKSTATUS_SELECTED_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_HFCLKSTATUS_SELECTED_HFXO: - ret = cmuSelect_HFXO; - break; - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: - ret = cmuSelect_HFRCODIV2; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case CMU_HFCLKSTATUS_SELECTED_CLKIN0: - ret = cmuSelect_CLKIN0; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case CMU_HFCLKSTATUS_SELECTED_USHFRCO: - ret = cmuSelect_USHFRCO; - break; -#endif - - default: - ret = cmuSelect_HFRCO; - break; - } -#else - switch (CMU->STATUS - & (CMU_STATUS_HFRCOSEL - | CMU_STATUS_HFXOSEL - | CMU_STATUS_LFRCOSEL -#if defined(CMU_STATUS_USHFRCODIV2SEL) - | CMU_STATUS_USHFRCODIV2SEL -#endif - | CMU_STATUS_LFXOSEL)) { - case CMU_STATUS_LFXOSEL: - ret = cmuSelect_LFXO; - break; - - case CMU_STATUS_LFRCOSEL: - ret = cmuSelect_LFRCO; - break; - - case CMU_STATUS_HFXOSEL: - ret = cmuSelect_HFXO; - break; - -#if defined(CMU_STATUS_USHFRCODIV2SEL) - case CMU_STATUS_USHFRCODIV2SEL: - ret = cmuSelect_USHFRCODIV2; - break; -#endif - - default: - ret = cmuSelect_HFRCO; - break; - } -#endif - break; - -#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) - case CMU_LFACLKSEL_REG: -#if defined(_CMU_LFCLKSEL_MASK) - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { - case CMU_LFCLKSEL_LFA_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFA_LFXO: - ret = cmuSelect_LFXO; - break; - -#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) - case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: - ret = cmuSelect_HFCLKLE; - break; -#endif - - default: -#if defined(CMU_LFCLKSEL_LFAE) - if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { - ret = cmuSelect_ULFRCO; - break; - } -#else - ret = cmuSelect_Disabled; -#endif - break; - } - -#elif defined(_CMU_LFACLKSEL_MASK) - switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { - case CMU_LFACLKSEL_LFA_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFACLKSEL_LFA_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFACLKSEL_LFA_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFACLKSEL_LFA_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } -#endif - break; -#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ - -#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) - case CMU_LFBCLKSEL_REG: -#if defined(_CMU_LFCLKSEL_MASK) - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { - case CMU_LFCLKSEL_LFB_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFB_LFXO: - ret = cmuSelect_LFXO; - break; - -#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) - case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: - ret = cmuSelect_HFCLKLE; - break; -#endif - -#if defined(CMU_LFCLKSEL_LFB_HFCLKLE) - case CMU_LFCLKSEL_LFB_HFCLKLE: - ret = cmuSelect_HFCLKLE; - break; -#endif - - default: -#if defined(CMU_LFCLKSEL_LFBE) - if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { - ret = cmuSelect_ULFRCO; - break; - } -#else - ret = cmuSelect_Disabled; -#endif - break; - } - -#elif defined(_CMU_LFBCLKSEL_MASK) - switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { - case CMU_LFBCLKSEL_LFB_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFBCLKSEL_LFB_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFBCLKSEL_LFB_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - - case CMU_LFBCLKSEL_LFB_HFCLKLE: - ret = cmuSelect_HFCLKLE; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFBCLKSEL_LFB_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } -#endif - break; -#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ - -#if defined(_CMU_LFCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { - case CMU_LFCLKSEL_LFC_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCLKSEL_LFC_LFXO: - ret = cmuSelect_LFXO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_LFECLKSEL_LFE_MASK) - case CMU_LFECLKSEL_REG: - switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { - case CMU_LFECLKSEL_LFE_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFECLKSEL_LFE_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFECLKSEL_LFE_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case CMU_LFECLKSEL_LFE_PLFRCO: - ret = cmuSelect_PLFRCO; - break; -#endif - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif /* CMU_LFECLKSEL_REG */ - -#if defined(_CMU_LFCCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { - case CMU_LFCCLKSEL_LFC_LFRCO: - ret = cmuSelect_LFRCO; - break; - - case CMU_LFCCLKSEL_LFC_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_LFCCLKSEL_LFC_ULFRCO: - ret = cmuSelect_ULFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif /* CMU_LFCCLKSEL_REG */ - - case CMU_DBGCLKSEL_REG: -#if defined(_CMU_DBGCLKSEL_DBG_MASK) - switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { - case CMU_DBGCLKSEL_DBG_HFCLK: - ret = cmuSelect_HFCLK; - break; - - case CMU_DBGCLKSEL_DBG_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - -#elif defined(_CMU_CTRL_DBGCLK_MASK) - switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { - case CMU_CTRL_DBGCLK_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_CTRL_DBGCLK_HFCLK: - ret = cmuSelect_HFCLK; - break; - } -#else - ret = cmuSelect_AUXHFRCO; -#endif - break; - -#if defined(USBC_CLOCK_PRESENT) - case CMU_USBCCLKSEL_REG: - switch (CMU->STATUS - & (CMU_STATUS_USBCLFXOSEL -#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) - | CMU_STATUS_USBCHFCLKSEL -#endif -#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) - | CMU_STATUS_USBCUSHFRCOSEL -#endif - | CMU_STATUS_USBCLFRCOSEL)) { -#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) - case CMU_STATUS_USBCHFCLKSEL: - ret = cmuSelect_HFCLK; - break; -#endif - -#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) - case CMU_STATUS_USBCUSHFRCOSEL: - ret = cmuSelect_USHFRCO; - break; -#endif - - case CMU_STATUS_USBCLFXOSEL: - ret = cmuSelect_LFXO; - break; - - case CMU_STATUS_USBCLFRCOSEL: - ret = cmuSelect_LFRCO; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case CMU_ADC0ASYNCSEL_REG: - switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { - case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: - ret = cmuSelect_Disabled; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: - ret = cmuSelect_HFSRCCLK; - break; - - default: - ret = cmuSelect_Disabled; - break; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case CMU_ADC1ASYNCSEL_REG: - switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { - case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: - ret = cmuSelect_Disabled; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: - ret = cmuSelect_HFSRCCLK; - break; - } - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case CMU_SDIOREFSEL_REG: - switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { - case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - } - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case CMU_QSPI0REFSEL_REG: - switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { - case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: - ret = cmuSelect_AUXHFRCO; - break; - - case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - } - break; -#endif - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) - case CMU_USBRCLKSEL_REG: - switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { - case CMU_USBCTRL_USBCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - - case CMU_USBCTRL_USBCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_USBCTRL_USBCLKSEL_HFXOX2: - ret = cmuSelect_HFXOX2; - break; - - case CMU_USBCTRL_USBCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - - case CMU_USBCTRL_USBCLKSEL_LFXO: - ret = cmuSelect_LFXO; - break; - - case CMU_USBCTRL_USBCLKSEL_LFRCO: - ret = cmuSelect_LFRCO; - break; - } - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case CMU_PDMREFSEL_REG: - switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { - case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: - ret = cmuSelect_USHFRCO; - break; - - case CMU_PDMCTRL_PDMCLKSEL_HFXO: - ret = cmuSelect_HFXO; - break; - - case CMU_PDMCTRL_PDMCLKSEL_HFRCO: - ret = cmuSelect_HFRCO; - break; - } - break; -#endif - - default: - ret = cmuSelect_Error; - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the System Core Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigSystemCoreClock(void) -{ -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif -} - -/***************************************************************************//** - * @brief This function configures the HFLE wait-states and divider suitable - * for the HF Clock. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock source is HFCLKLE. - ******************************************************************************/ -void sli_em_cmu_SetHFLEConfigHFClock(void) -{ -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * an LF clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and LFXO or LFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc) -{ - if (osc == (uint8_t)cmuOsc_LFXO) { - // Enable LFXO oscillator - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - // Enable LFRCO oscillator - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - } else { - EFM_ASSERT(false); - } - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_SILICON_LABS_32B_SERIES_1) - // Select HF clock source. - if (osc == (uint8_t)cmuOsc_LFXO) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; - } -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - // Select HF clock source. - if (osc == (uint8_t)cmuOsc_LFXO) { - CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; - } else if (osc == (uint8_t)cmuOsc_LFRCO) { - CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; - } -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFXO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFXO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFXO(void) -{ -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = SystemHFXOClockGet(); - EMU_VScaleEM01ByClock(vScaleFrequency, false); -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - // This is known after 'select' is written below. - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif -#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) - // Adjust HFXO buffer current for frequencies above 32 MHz. - if (SystemHFXOClockGet() > 32000000) { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; - } else { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; - } -#endif - - // Enable HFXO oscillator - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Wait for voltage upscaling to complete before the clock is set. - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - -#if defined(CMU_HFCLKSEL_HF_HFXO) - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(CMU_CMD_HFCLKSEL_HFXO) - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Keep EMU module informed on the source HF clock frequency. This will apply voltage - // downscaling after clock is set if downscaling is configured. - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCO(void) -{ -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = 0; /* Use default. */ - if (((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); - } - if (vScaleFrequency != 0UL) { - EMU_VScaleEM01ByClock(vScaleFrequency, false); - } -#endif - -#if defined(CMU_MAX_FREQ_HFLE) - // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - // This is known after 'select' is written below. - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif - - // Enable HFRCO oscillator - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Wait for voltage upscaling to complete before the clock is set. - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemHFClockGet()); -#endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - // Set HFLE clock. - setHfLeConfig(SystemCoreClockGet()); -#endif -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Keep EMU module informed on the source HF clock frequency. This will apply voltage - // downscaling after clock is set if downscaling is configured. - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCODIV2(void) -{ - // Enable USHFRCO oscillator - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemCoreClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * HFRCODIV2 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and HFRCODIV2 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectHFRCODIV2(void) -{ - // Enable HFRCO oscillator - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * CLKIN0 as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and CLKIN0 is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectCLKIN0(void) -{ - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_CLKIN0; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) -/***************************************************************************//** - * @brief This function is used to initialize the HF clock and selecting - * USHFRCO as the clock source. - * - * @note FOR INTERNAL USE ONLY. - * - * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when - * the clock is HF and USHFRCO is selected as the clock source. - ******************************************************************************/ -void sli_em_cmu_HFClockSelectUSHFRCO(void) -{ - // Enable USHFRCO oscillator - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - // Configure worst case wait-states for flash and set safe HFPER - // clock-tree prescalers. - flashWaitStateMax(); - hfperClkSafePrescaler(); - - // Select HF clock source. - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_USHFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - setHfLeConfig(SystemHFClockGet()); -#endif - - // Optimize flash access wait state setting for the currently selected core clk. - CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); - // Set optimized HFPER clock-tree prescalers. - hfperClkOptimizedPrescaler(); -} -#endif - -/***************************************************************************//** - * @brief - * Select the reference clock/oscillator used for a clock branch. - * - * @details - * Notice that if a selected reference is not enabled prior to selecting its - * use, it will be enabled and this function will wait for the selected - * oscillator to be stable. It will however NOT be disabled if another - * reference clock is selected later. - * - * This feature is particularly important if selecting a new reference - * clock for the clock branch clocking the core. Otherwise, the system - * may halt. - * - * @note - * HFCLKLE prescaler is automatically modified when peripherals with clock - * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. - * - * @param[in] clock - * A clock branch to select reference clock for. One of: - * @li #cmuClock_HF - * @li #cmuClock_LFA - * @li #cmuClock_LFB - * @if _CMU_LFCCLKEN0_MASK - * @li #cmuClock_LFC - * @endif - * @if _CMU_LFECLKEN0_MASK - * @li #cmuClock_LFE - * @endif - * @li #cmuClock_DBG - * @if _CMU_CMD_USBCLKSEL_MASK - * @li #cmuClock_USBC - * @endif - * @if _CMU_USBCTRL_MASK - * @li #cmuClock_USBR - * @endif - * - * @param[in] ref - * A reference selected for clocking. See the reference manual - * for details about references available for a specific clock branch. - * @li #cmuSelect_HFRCO - * @li #cmuSelect_LFRCO - * @li #cmuSelect_HFXO - * @if _CMU_HFXOCTRL_HFXOX2EN_MASK - * @li #cmuSelect_HFXOX2 - * @endif - * @li #cmuSelect_LFXO - * @li #cmuSelect_HFCLKLE - * @li #cmuSelect_AUXHFRCO - * @if _CMU_USHFRCOCTRL_MASK - * @li #cmuSelect_USHFRCO - * @endif - * @li #cmuSelect_HFCLK - * @ifnot DOXYDOC_EFM32_GECKO_FAMILY - * @li #cmuSelect_ULFRCO - * @endif - * @if CMU_OSCENCMD_PLFRCOEN - * @li #cmuSelect_PLFRCO - * @endif - ******************************************************************************/ -void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) -{ - uint32_t select = (uint32_t)cmuOsc_HFRCO; - CMU_Osc_TypeDef osc = cmuOsc_HFRCO; - uint32_t freq; - uint32_t tmp; - uint32_t selRegId; -#if defined(_SILICON_LABS_32B_SERIES_1) - volatile uint32_t *selReg = NULL; -#endif -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) - uint32_t lfExtended = 0; -#endif - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - uint32_t vScaleFrequency = 0; /* Use default. */ - - /* Start voltage upscaling before the clock is set. */ - if (clock == cmuClock_HF) { - if (ref == cmuSelect_HFXO) { - vScaleFrequency = SystemHFXOClockGet(); - } else if ((ref == cmuSelect_HFRCO) - && ((uint32_t)CMU_HFRCOBandGet() - > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); - } else { - /* Use the default frequency. */ - } - if (vScaleFrequency != 0UL) { - EMU_VScaleEM01ByClock(vScaleFrequency, false); - } - } -#endif - - selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; - - switch (selRegId) { - case CMU_HFCLKSEL_REG: - switch (ref) { - case cmuSelect_LFXO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_LFXO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_LFXO; -#endif - osc = cmuOsc_LFXO; - break; - - case cmuSelect_LFRCO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_LFRCO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_LFRCO; -#endif - osc = cmuOsc_LFRCO; - break; - - case cmuSelect_HFXO: -#if defined(CMU_HFCLKSEL_HF_HFXO) - select = CMU_HFCLKSEL_HF_HFXO; -#elif defined(CMU_CMD_HFCLKSEL_HFXO) - select = CMU_CMD_HFCLKSEL_HFXO; -#endif - osc = cmuOsc_HFXO; -#if defined(CMU_MAX_FREQ_HFLE) - /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - This is known after 'select' is written below. */ - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif -#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) - /* Adjust HFXO buffer current for frequencies above 32 MHz. */ - if (SystemHFXOClockGet() > 32000000) { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; - } else { - CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) - | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; - } -#endif - break; - - case cmuSelect_HFRCO: -#if defined(_SILICON_LABS_32B_SERIES_1) - select = CMU_HFCLKSEL_HF_HFRCO; -#elif defined(_SILICON_LABS_32B_SERIES_0) - select = CMU_CMD_HFCLKSEL_HFRCO; -#endif - osc = cmuOsc_HFRCO; -#if defined(CMU_MAX_FREQ_HFLE) - /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. - This is known after 'select' is written below. */ - setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); -#endif - break; - -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - case cmuSelect_USHFRCODIV2: - select = CMU_CMD_HFCLKSEL_USHFRCODIV2; - osc = cmuOsc_USHFRCO; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case cmuSelect_HFRCODIV2: - select = CMU_HFCLKSEL_HF_HFRCODIV2; - osc = cmuOsc_HFRCO; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case cmuSelect_CLKIN0: - select = CMU_HFCLKSEL_HF_CLKIN0; - osc = cmuOsc_CLKIN0; - break; -#endif - -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case cmuSelect_USHFRCO: - select = CMU_HFCLKSEL_HF_USHFRCO; - osc = cmuOsc_USHFRCO; - break; -#endif - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) - case cmuSelect_ULFRCO: - /* ULFRCO cannot be used as HFCLK. */ - EFM_ASSERT(false); - return; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - if (osc != cmuOsc_CLKIN0) { - CMU_OscillatorEnable(osc, true, true); - } -#else - CMU_OscillatorEnable(osc, true, true); -#endif - - /* Configure worst case wait-states for flash and set safe HFPER - clock-tree prescalers. */ - flashWaitStateMax(); - hfperClkSafePrescaler(); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* Wait for voltage upscaling to complete before the clock is set. */ - if (vScaleFrequency != 0UL) { - EMU_VScaleWait(); - } -#endif - - /* Switch to the selected oscillator. */ -#if defined(_CMU_HFCLKSEL_MASK) - CMU->HFCLKSEL = select; -#else - CMU->CMD = select; -#endif - /* Update the CMSIS core clock variable. */ - /* (The function will update the global variable). */ - freq = SystemCoreClockGet(); - -#if defined(CMU_MAX_FREQ_HFLE) - /* Update the HFLE configuration after 'select' is set. - Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ -#if defined(_SILICON_LABS_32B_SERIES_0) - setHfLeConfig(freq); -#else - setHfLeConfig(SystemHFClockGet()); -#endif -#endif - - /* Optimize flash access wait state setting for the currently selected core clk. */ - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* Keep EMU module informed on the source HF clock frequency. This will apply voltage - downscaling after clock is set if downscaling is configured. */ - if (vScaleFrequency == 0UL) { - EMU_VScaleEM01ByClock(0, true); - } -#endif - /* Set optimized HFPER clock-tree prescalers. */ - hfperClkOptimizedPrescaler(); - break; - -#if defined(_SILICON_LABS_32B_SERIES_1) - case CMU_LFACLKSEL_REG: - selReg = &CMU->LFACLKSEL; - /* HFCLKCLE can't be used as LFACLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH - /* Fall through and select the clock source. */ - -#if defined(_CMU_LFCCLKSEL_MASK) - case CMU_LFCCLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; - /* HFCLKCLE can't be used as LFCCLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH -#endif - /* Fall through and select the clock source. */ - - case CMU_LFECLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; - /* HFCLKCLE can't be used as LFECLK. */ - EFM_ASSERT(ref != cmuSelect_HFCLKLE); - SL_FALLTHROUGH - /* Fall through and select the clock source. */ - - case CMU_LFBCLKSEL_REG: - selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFACLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFACLKSEL_LFA_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFACLKSEL_LFA_LFRCO; - break; - - case cmuSelect_HFCLKLE: - /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ - setHfLeConfig(SystemHFClockGet()); - BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); - tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; - break; - - case cmuSelect_ULFRCO: - /* ULFRCO is always on, there is no need to enable it. */ - tmp = _CMU_LFACLKSEL_LFA_ULFRCO; - break; - -#if defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: - CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); - tmp = _CMU_LFACLKSEL_LFA_PLFRCO; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - *selReg = tmp; - break; - -#elif defined(_SILICON_LABS_32B_SERIES_0) - case CMU_LFACLKSEL_REG: - case CMU_LFBCLKSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFCLKSEL_LFA_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFCLKSEL_LFA_LFRCO; - break; - - case cmuSelect_HFCLKLE: -#if defined(CMU_MAX_FREQ_HFLE) - /* Set the HFLE wait-state and divider. */ - freq = SystemCoreClockGet(); - setHfLeConfig(freq); -#endif - /* Ensure HFCORE to LE clocking is enabled. */ - BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); - tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; - break; - -#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) - case cmuSelect_ULFRCO: - /* ULFRCO is always enabled. */ - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - lfExtended = 1; - break; -#endif - - default: - /* An illegal clock source for LFA/LFB selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - if (selRegId == CMU_LFACLKSEL_REG) { -#if defined(_CMU_LFCLKSEL_LFAE_MASK) - CMU->LFCLKSEL = (CMU->LFCLKSEL - & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) - | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) - | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); -#else - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) - | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); -#endif - } else { -#if defined(_CMU_LFCLKSEL_LFBE_MASK) - CMU->LFCLKSEL = (CMU->LFCLKSEL - & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) - | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) - | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); -#else - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) - | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); -#endif - } - break; - -#if defined(_CMU_LFCLKSEL_LFC_MASK) - case CMU_LFCCLKSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_LFCLKSEL_LFA_DISABLED; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_LFCLKSEL_LFC_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_LFCLKSEL_LFC_LFRCO; - break; - - default: - /* An illegal clock source for LFC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) - | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); - break; -#endif -#endif - -#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) - case CMU_DBGCLKSEL_REG: - switch (ref) { -#if defined(_CMU_DBGCLKSEL_DBG_MASK) - case cmuSelect_AUXHFRCO: - /* Select AUXHFRCO as a debug clock. */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; - break; - - case cmuSelect_HFCLK: - /* Select divided HFCLK as a debug clock. */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; - break; -#endif - -#if defined(CMU_CTRL_DBGCLK) - case cmuSelect_AUXHFRCO: - /* Select AUXHFRCO as a debug clock. */ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) - | CMU_CTRL_DBGCLK_AUXHFRCO; - break; - - case cmuSelect_HFCLK: - /* Select divided HFCLK as a debug clock. */ - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) - | CMU_CTRL_DBGCLK_HFCLK; - break; -#endif - - default: - /* An illegal clock source for debug selected. */ - EFM_ASSERT(false); - return; - } - break; -#endif - -#if defined(USBC_CLOCK_PRESENT) - case CMU_USBCCLKSEL_REG: - switch (ref) { - case cmuSelect_LFXO: - /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { - } - break; - - case cmuSelect_LFRCO: - /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { - } - break; - -#if defined(CMU_STATUS_USBCHFCLKSEL) - case cmuSelect_HFCLK: - /* Select undivided HFCLK as a clock source for USB. */ - /* The oscillator must already be enabled to avoid a core lockup. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { - } - break; -#endif - -#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) - case cmuSelect_USHFRCO: - /* Select USHFRCO as a clock source for USB. */ - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - - /* Switch the oscillator. */ - CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; - - /* Wait until the clock is activated. */ - while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { - } - break; -#endif - - default: - /* An illegal clock source for USB. */ - EFM_ASSERT(false); - return; - } - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) - case CMU_ADC0ASYNCSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; - break; - - case cmuSelect_HFSRCCLK: - tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; - break; - - default: - /* An illegal clock source for ADC0ASYNC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) - | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) - case CMU_ADC1ASYNCSEL_REG: - switch (ref) { - case cmuSelect_Disabled: - tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; - break; - - case cmuSelect_HFSRCCLK: - tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; - break; - - default: - /* An illegal clock source for ADC1ASYNC selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) - | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - case CMU_SDIOREFSEL_REG: - switch (ref) { - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; - break; - - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; - break; - - default: - /* An illegal clock source for SDIOREF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) - | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - case CMU_QSPI0REFSEL_REG: - switch (ref) { - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; - break; - - case cmuSelect_AUXHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; - break; - - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; - break; - - default: - /* An illegal clock source for QSPI0REF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) - | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) - case CMU_USBRCLKSEL_REG: - switch (ref) { - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; - break; - - case cmuSelect_HFXOX2: - /* Only allowed for HFXO frequencies up to 25 MHz. */ - EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); - - /* Enable HFXO X2. */ - CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; - - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - - tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; - break; - - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; - break; - - case cmuSelect_LFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; - break; - - case cmuSelect_LFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); - tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; - break; - - default: - /* An illegal clock source for USBR selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) - | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); - break; -#endif - -#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) - case CMU_PDMREFSEL_REG: - switch (ref) { - case cmuSelect_USHFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; - break; - - case cmuSelect_HFXO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; - break; - - case cmuSelect_HFRCO: - /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ - CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); - tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; - break; - - default: - /* An illegal clock source for PDMREF selected. */ - EFM_ASSERT(false); - return; - } - - /* Apply select. */ - CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) - | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified low frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_LFXO: - precision = lfxo_precision; - break; - -#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) - case cmuSelect_PLFRCO: - precision = 500; - break; -#endif - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the specified high frequency clock branch. - * - * @param[in] clock - * Clock branch. - * - * @return - * Precision, in PPM, of the specified clock branch. - * - * @note - * This function is only for internal usage. - * - * @note - * The current implementation of this function is used to determine if the - * clock has a precision <= 500 ppm or not (which is the minimum required - * for BLE). Future version of this function should provide more accurate - * precision numbers to allow for further optimizations from the stacks. - ******************************************************************************/ -uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) -{ - CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); - uint16_t precision; - - switch (src) { - case cmuSelect_HFXO: - precision = hfxo_precision; - break; - - case cmuSelect_HFRCO: - precision = 0xFFFF; - break; - - default: - precision = 0xFFFF; - break; - } - - return precision; -} - -#if defined(CMU_OSCENCMD_DPLLEN) -/**************************************************************************//** - * @brief - * Lock the DPLL to a given frequency. - * - * The frequency is given by: Fout = Fref * (N+1) / (M+1). - * - * @note - * This function does not check if the given N & M values will actually - * produce the desired target frequency. @n - * N & M limitations: @n - * 300 < N <= 4095 @n - * 0 <= M <= 4095 @n - * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to - * calling this function to avoid over-clocking. - * - * HFCLKLE prescaler is automatically modified before updating HFRCO - * based on the maximum HFLE frequency allowed. - * - * @param[in] init - * DPLL setup parameters. - * - * @return - * Returns false on invalid target frequency or DPLL locking error. - *****************************************************************************/ -bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) -{ - int index = 0; - unsigned int i; - bool hfrcoDiv2override = false; - uint32_t hfrcoCtrlVal, lockStatus, sysFreq; - - EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); - EFM_ASSERT(init->frequency - <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); - EFM_ASSERT(init->n > 300U); - EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); - EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); - EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK - >> _CMU_HFRCOSS_SSINV_SHIFT)); - EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK - >> _CMU_HFRCOSS_SSAMP_SHIFT)); - -#if defined(_EMU_STATUS_VSCALE_MASK) - if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) - && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EFM_ASSERT(false); - return false; - } -#endif - - // Find the correct HFRCO band and retrieve a HFRCOCTRL value. - for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { - if ((init->frequency >= hfrcoCtrlTable[i].minFreq) - && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { - index = (int)i; // Correct band found - break; - } - } - if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { - EFM_ASSERT(false); - return false; // Target frequency out of spec. - } - hfrcoCtrlVal = hfrcoCtrlTable[index].value; - - // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. - if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { - uint32_t tuning; - - tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) - & _CMU_HFRCOCTRL_TUNING_MASK) - >> _CMU_HFRCOCTRL_TUNING_SHIFT; - - // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency - // of the band shifts down by 5.8%. 9 is subtracted to compensate. - if (tuning > 9UL) { - tuning -= 9UL; - } else { - tuning = 0UL; - } - - hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; - } - - // Update the CMSIS frequency SystemHfrcoFreq value. - SystemHfrcoFreq = init->frequency; - - // Set maximum wait-states while changing the core clock. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - flashWaitStateMax(); - } - - // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - setHfLeConfig(init->frequency); - - // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. - hfrcoDiv2override = true; - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; - } - - CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; - while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { - } - CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW - | CMU_IFC_DPLLLOCKFAILHIGH; - CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) - | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); - CMU->HFRCOCTRL = hfrcoCtrlVal; - CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) - | ((init->autoRecover ? 1UL : 0UL) - << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) - | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) - | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); - CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; - while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY - | CMU_IF_DPLLLOCKFAILLOW - | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { - } - - // Restore to HFRCO - if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) - && (hfrcoDiv2override == true)) { - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; - } - - // If HFRCO is selected as an HF clock, optimize the flash access wait-state - // configuration for this frequency and update the CMSIS core clock variable. - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= init->frequency); - EFM_ASSERT(sysFreq <= SystemHfrcoFreq); - EFM_ASSERT(init->frequency == SystemHfrcoFreq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - } - - // Reduce HFLE frequency if possible. - setHfLeConfig(SystemHFClockGet()); - -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Update voltage scaling. - EMU_VScaleEM01ByClock(0, true); -#endif - - if (lockStatus == CMU_IF_DPLLRDY) { - return true; - } - return false; -} -#endif // CMU_OSCENCMD_DPLLEN - -/**************************************************************************//** - * @brief - * CMU low frequency register synchronization freeze control. - * - * @details - * Some CMU registers require synchronization into the low-frequency (LF) - * domain. The freeze feature allows for several such registers to be - * modified before passing them to the LF domain simultaneously (which - * takes place when the freeze mode is disabled). - * - * Another use case for this feature is using an API (such - * as the CMU API) for modifying several bit fields consecutively in the - * same register. If freeze mode is enabled during this sequence, stalling - * can be avoided. - * - * @note - * When enabling freeze mode, this function will wait for all current - * ongoing CMU synchronization to LF domain to complete (normally - * synchronization will not be in progress.) However, for this reason, when - * using freeze mode, modifications of registers requiring LF synchronization - * should be done within one freeze enable/disable block to avoid unnecessary - * stalling. - * - * @param[in] enable - * @li true - enable freeze, modified registers are not propagated to the - * LF domain - * @li false - disable freeze, modified registers are propagated to the LF - * domain - *****************************************************************************/ -void CMU_FreezeEnable(bool enable) -{ - if (enable) { - /* Wait for any ongoing LF synchronizations to complete. This */ - /* protects against the rare case when a user */ - /* - modifies a register requiring LF sync */ - /* - then enables freeze before LF sync completed */ - /* - then modifies the same register again */ - /* since modifying a register while it is in sync progress should be */ - /* avoided. */ - while (CMU->SYNCBUSY != 0UL) { - } - - CMU->FREEZE = CMU_FREEZE_REGFREEZE; - } else { - CMU->FREEZE = 0; - } -} - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Get HFRCO band in use. - * - * @return - * HFRCO band in use. - ******************************************************************************/ -CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) -{ - return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) - >> _CMU_HFRCOCTRL_BAND_SHIFT); -} -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_HFRCOCTRL_BAND_MASK) -/***************************************************************************//** - * @brief - * Set HFRCO band and the tuning value based on the value in the calibration - * table made during production. - * - * @note - * HFCLKLE prescaler is automatically modified based on the maximum - * HFLE frequency allowed. - * - * @param[in] band - * HFRCO band to activate. - ******************************************************************************/ -void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) -{ - uint32_t tuning; - uint32_t freq; - CMU_Select_TypeDef osc; - - /* Read the tuning value from the calibration table. */ - switch (band) { - case cmuHFRCOBand_1MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) - >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; - break; - - case cmuHFRCOBand_7MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) - >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; - break; - - case cmuHFRCOBand_11MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) - >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; - break; - - case cmuHFRCOBand_14MHz: - tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) - >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; - break; - - case cmuHFRCOBand_21MHz: - tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) - >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; - break; - -#if defined(_CMU_HFRCOCTRL_BAND_28MHZ) - case cmuHFRCOBand_28MHz: - tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) - >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; - break; -#endif - - default: - EFM_ASSERT(false); - return; - } - - /* If HFRCO is used for the core clock, flash access WS has to be considered. */ - osc = CMU_ClockSelectGet(cmuClock_HF); - if (osc == cmuSelect_HFRCO) { - /* Configure worst case wait states for flash access before setting the divider. */ - flashWaitStateMax(); - } - - /* Set band/tuning. */ - CMU->HFRCOCTRL = (CMU->HFRCOCTRL - & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) - | (band << _CMU_HFRCOCTRL_BAND_SHIFT) - | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); - - /* If HFRCO is used for the core clock, optimize flash WS. */ - if (osc == cmuSelect_HFRCO) { - /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ - freq = SystemCoreClockGet(); - CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); - } - -#if defined(CMU_MAX_FREQ_HFLE) - /* Reduce HFLE frequency if possible. */ - setHfLeConfig(SystemCoreClockGet()); -#endif -} -#endif /* _CMU_HFRCOCTRL_BAND_MASK */ - -#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the HFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * HFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) -{ - switch (freq) { - /* 1, 2, and 4 MHz share the same calibration word. */ - case cmuHFRCOFreq_1M0Hz: - case cmuHFRCOFreq_2M0Hz: - case cmuHFRCOFreq_4M0Hz: - return DEVINFO->HFRCOCAL0; - - case cmuHFRCOFreq_7M0Hz: - return DEVINFO->HFRCOCAL3; - - case cmuHFRCOFreq_13M0Hz: - return DEVINFO->HFRCOCAL6; - - case cmuHFRCOFreq_16M0Hz: - return DEVINFO->HFRCOCAL7; - - case cmuHFRCOFreq_19M0Hz: - return DEVINFO->HFRCOCAL8; - - case cmuHFRCOFreq_26M0Hz: - return DEVINFO->HFRCOCAL10; - - case cmuHFRCOFreq_32M0Hz: - return DEVINFO->HFRCOCAL11; - - case cmuHFRCOFreq_38M0Hz: - return DEVINFO->HFRCOCAL12; - -#if defined(_DEVINFO_HFRCOCAL13_MASK) - case cmuHFRCOFreq_48M0Hz: - return DEVINFO->HFRCOCAL13; -#endif - -#if defined(_DEVINFO_HFRCOCAL14_MASK) - case cmuHFRCOFreq_56M0Hz: - return DEVINFO->HFRCOCAL14; -#endif - -#if defined(_DEVINFO_HFRCOCAL15_MASK) - case cmuHFRCOFreq_64M0Hz: - return DEVINFO->HFRCOCAL15; -#endif - -#if defined(_DEVINFO_HFRCOCAL16_MASK) - case cmuHFRCOFreq_72M0Hz: - return DEVINFO->HFRCOCAL16; -#endif - - default: /* cmuHFRCOFreq_UserDefined */ - return 0; - } -} - -/***************************************************************************//** - * @brief - * Get the current HFRCO frequency. - * - * @return - * HFRCO frequency. - ******************************************************************************/ -CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) -{ - return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Set the HFRCO calibration for the selected target frequency. - * - * @note - * HFCLKLE prescaler is automatically modified based on the maximum - * HFLE frequency allowed. - * - * @param[in] setFreq - * HFRCO frequency to set. - ******************************************************************************/ -void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - uint32_t sysFreq; - uint32_t prevFreq; - - /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ - freqCal = CMU_HFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); - prevFreq = SystemHfrcoFreq; - SystemHfrcoFreq = (uint32_t)setFreq; - - /* Set maximum wait-states and set safe HFPER clock-tree prescalers while - changing the core clock. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - flashWaitStateMax(); - hfperClkSafePrescaler(); - } - - /* Wait for any previous sync to complete and set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { - } - - /* Check for valid calibration data. */ - EFM_ASSERT(freqCal != UINT_MAX); - - /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ - switch (setFreq) { - case cmuHFRCOFreq_1M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV4; - break; - - case cmuHFRCOFreq_2M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV2; - break; - - case cmuHFRCOFreq_4M0Hz: - freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV1; - break; - - default: - break; - } - - /* Update HFLE configuration before updating HFRCO. - Use the new set frequency. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ - setHfLeConfig((uint32_t)setFreq); - } - - if ((uint32_t)setFreq > prevFreq) { -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* When increasing frequency voltage scale must be done before the change. */ - EMU_VScaleEM01ByClock((uint32_t)setFreq, true); -#endif - } - - CMU->HFRCOCTRL = freqCal; - - /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration - for this frequency and update the CMSIS core clock variable. */ - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ - sysFreq = SystemCoreClockGet(); - EFM_ASSERT(sysFreq <= (uint32_t)setFreq); - EFM_ASSERT(sysFreq <= SystemHfrcoFreq); - EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); - CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); - } - - /* Reduce HFLE frequency if possible. */ - setHfLeConfig(SystemHFClockGet()); - - if ((uint32_t)setFreq <= prevFreq) { -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - /* When decreasing frequency voltage scale must be done after the change */ - EMU_VScaleEM01ByClock(0, true); -#endif - } - if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { - /* Set optimized HFPER clock-tree prescalers. */ - hfperClkOptimizedPrescaler(); - } -} -#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) -/***************************************************************************//** - * @brief - * Get the HFRCO startup delay. - * - * @details - * See the reference manual for more details. - * - * @return - * The startup delay in use. - ******************************************************************************/ -uint32_t CMU_HFRCOStartupDelayGet(void) -{ - return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) - >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; -} - -/***************************************************************************//** - * @brief - * Set the HFRCO startup delay. - * - * @details - * See the reference manual for more details. - * - * @param[in] delay - * The startup delay to set (<= 31). - ******************************************************************************/ -void CMU_HFRCOStartupDelaySet(uint32_t delay) -{ - EFM_ASSERT(delay <= 31); - - delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; - CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) - | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); -} -#endif - -#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) -/**************************************************************************//** - * @brief - * Get the USHFRCO frequency calibration word in DEVINFO. - * - * @param[in] freq - * Frequency in Hz. - * - * @return - * USHFRCO calibration word for a given frequency. - *****************************************************************************/ -static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) -{ - switch (freq) { - case cmuUSHFRCOFreq_16M0Hz: - return DEVINFO->USHFRCOCAL7; - - case cmuUSHFRCOFreq_32M0Hz: - return DEVINFO->USHFRCOCAL11; - - case cmuUSHFRCOFreq_48M0Hz: - return DEVINFO->USHFRCOCAL13; - - case cmuUSHFRCOFreq_50M0Hz: - return DEVINFO->USHFRCOCAL14; - - default: /* cmuUSHFRCOFreq_UserDefined */ - return 0; - } -} - -/***************************************************************************//** - * @brief - * Get the current USHFRCO frequency. - * - * @return - * HFRCO frequency. - ******************************************************************************/ -CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) -{ - return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Get USHFRCO frequency. - * - * @return - * USHFRCO frequency. - ******************************************************************************/ -uint32_t CMU_USHFRCOFreqGet(void) -{ - return ushfrcoFreq; -} - -/***************************************************************************//** - * @brief - * Set the USHFRCO calibration for the selected target frequency. - * - * @param[in] setFreq - * USHFRCO frequency to set. - ******************************************************************************/ -void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) -{ - uint32_t freqCal; - - /* Get DEVINFO calibration values. */ - freqCal = CMU_USHFRCODevinfoGet(setFreq); - EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); - ushfrcoFreq = (uint32_t)setFreq; - - /* Wait for any previous sync to complete and set calibration data - for the selected frequency. */ - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; - - CMU->USHFRCOCTRL = freqCal; -} -#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ - -#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) -/***************************************************************************//** - * @brief - * Enable or disable HFXO autostart. - * - * @param[in] userSel - * Additional user specified enable bit. - * - * @param[in] enEM0EM1Start - * If true, HFXO is automatically started upon entering EM0/EM1 entry from - * EM2/EM3. HFXO selection has to be handled by the user. - * If false, HFXO is not started automatically when entering EM0/EM1. - * - * @param[in] enEM0EM1StartSel - * If true, HFXO is automatically started and immediately selected upon - * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of - * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically - * modified if userSel is specified. - * If false, HFXO is not started or selected automatically when entering - * EM0/EM1. - ******************************************************************************/ -void CMU_HFXOAutostartEnable(uint32_t userSel, - bool enEM0EM1Start, - bool enEM0EM1StartSel) -{ - uint32_t hfxoFreq; - uint32_t hfxoCtrl; - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) - if (enEM0EM1StartSel) { - /* Voltage scaling is not compatible with HFXO auto start and select. */ - EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); - } -#endif - - /* Mask supported enable bits. */ -#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) - userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; -#else - userSel = 0; -#endif - - hfxoFreq = SystemHFXOClockGet(); -#if defined(_EMU_CMD_EM01VSCALE0_MASK) - // Update voltage scaling. - EMU_VScaleEM01ByClock(hfxoFreq, true); -#endif - /* Set wait-states for HFXO if automatic start and select is configured. */ - if ((userSel > 0UL) || enEM0EM1StartSel) { - CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT); - setHfLeConfig(hfxoFreq / CMU_ClockDivGet(cmuClock_HF)); - } - - if (enEM0EM1Start || enEM0EM1StartSel) { - /* Enable the HFXO once in order to finish first time calibrations. */ - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - } - - /* Since call to CMU_OscillatorEnable() can change the CMU->HFXOCTRL register, - * it's important to read the CMU->HFXOCTRL register after the call to CMU_OscillatorEnable(). */ - hfxoCtrl = CMU->HFXOCTRL & ~(userSel - | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK - | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); - - hfxoCtrl |= userSel - | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) - | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); - - /* Update HFXOCTRL after wait-states are updated as HF may automatically switch - to HFXO when automatic select is enabled . */ - CMU->HFXOCTRL = hfxoCtrl; -} -#endif - -/**************************************************************************//** - * @brief - * Set HFXO control registers. - * - * @note - * HFXO configuration should be obtained from a configuration tool, - * app note, or crystal data sheet. This function disables the HFXO to - * ensure a valid state before update. - * - * @param[in] hfxoInit - * HFXO setup parameters. - *****************************************************************************/ -void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) -{ - /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); - - /* HFXO must be disabled before reconfiguration. */ - CMU_OscillatorEnable(cmuOsc_HFXO, false, true); - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) - uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; - - switch (hfxoInit->mode) { - case cmuOscMode_Crystal: - tmp = CMU_HFXOCTRL_MODE_XTAL; - break; - case cmuOscMode_External: - tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; - break; - case cmuOscMode_AcCoupled: - tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; - break; - default: - EFM_ASSERT(false); /* Unsupported configuration */ - break; - } - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; - -#if defined(CMU_HFXOCTRL_HFXOX2EN) - /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ - tmp = 0; - if (SystemHFXOClockGet() <= 25000000) { - tmp |= CMU_HFXOCTRL_HFXOX2EN; - } - - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; -#endif - - /* Set tuning for startup and steady state. */ - CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup - << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) - | (hfxoInit->xoCoreBiasTrimStartup - << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK - | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) - | (hfxoInit->ctuneSteadyState - << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) - | (hfxoInit->xoCoreBiasTrimSteadyState - << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); - - /* Set timeouts */ - CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect - << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) - | (hfxoInit->timeoutSteady - << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) - | (hfxoInit->timeoutStartup - << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); - -#elif defined(_CMU_HFXOCTRL_MASK) - uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; - - /* AC coupled external clock not supported. */ - EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); - if (hfxoInit->mode == cmuOscMode_External) { - tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; - } - - /* Apply control settings. */ - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) - | tmp; - BUS_RegBitWrite(&CMU->HFXOCTRL, - _CMU_HFXOCTRL_LOWPOWER_SHIFT, - (unsigned)hfxoInit->lowPowerMode); - - /* Set XTAL tuning parameters. */ - -#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) - /* Set peak detection threshold. */ - CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) - | (hfxoInit->thresholdPeakDetect - << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); -#endif - /* Set tuning for startup and steady state. */ - CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup - << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) - | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup - << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); - - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK - | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) - | ((uint32_t)hfxoInit->ctuneSteadyState - << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) - | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState - << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) - | ((uint32_t)hfxoInit->regIshSteadyState - << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) - | getRegIshUpperVal(hfxoInit->regIshSteadyState); - - /* Set timeouts. */ - CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect - << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutSteady - << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutStartup - << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) - | ((uint32_t)hfxoInit->timeoutShuntOptimization - << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); - -#else - CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK - | _CMU_CTRL_HFXOBOOST_MASK - | _CMU_CTRL_HFXOMODE_MASK - | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) - | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) - | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) - | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) - | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); -#endif -} - -/***************************************************************************//** - * @brief - * Get the LCD framerate divisor (FDIV) setting. - * - * @return - * The LCD framerate divisor. - ******************************************************************************/ -uint32_t CMU_LCDClkFDIVGet(void) -{ -#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) - return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; -#else - return 0; -#endif /* defined(LCD_PRESENT) */ -} - -/***************************************************************************//** - * @brief - * Set the LCD framerate divisor (FDIV) setting. - * - * @note - * The FDIV field (CMU LCDCTRL register) should only be modified while the - * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function - * will NOT modify FDIV if the LCD module clock is enabled. See - * @ref CMU_ClockEnable() for disabling/enabling LCD clock. - * - * @param[in] div - * The FDIV setting to use. - ******************************************************************************/ -void CMU_LCDClkFDIVSet(uint32_t div) -{ -#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) - EFM_ASSERT(div <= cmuClkDiv_128); - - /* Do not allow modification if LCD clock enabled. */ - if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { - return; - } - - div <<= _CMU_LCDCTRL_FDIV_SHIFT; - div &= _CMU_LCDCTRL_FDIV_MASK; - CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; -#else - (void)div; /* Unused parameter. */ -#endif /* defined(LCD_PRESENT) */ -} - -/**************************************************************************//** - * @brief - * Set LFXO control registers. - * - * @note - * LFXO configuration should be obtained from a configuration tool, - * app note, or crystal data sheet. This function disables the LFXO when - * necessary to ensure a valid state before update. - * - * @param[in] lfxoInit - * LFXO setup parameters. - *****************************************************************************/ -void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) -{ - /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); - -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK - | _CMU_LFXOCTRL_GAIN_MASK - | _CMU_LFXOCTRL_TIMEOUT_MASK - | _CMU_LFXOCTRL_MODE_MASK)) - | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) - | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) - | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) - | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); - - /* If LFXO already contains the correct configuration then there is no need - * to stop the oscillator and apply new settings. The LFXO can be running out - * of reset, in which case there is no need to disable it unless necessary. */ - if (reg != CMU->LFXOCTRL) { - CMU_OscillatorEnable(cmuOsc_LFXO, false, true); - CMU->LFXOCTRL = reg; - } -#elif defined(_SILICON_LABS_32B_SERIES_0) - /* LFXO must be disabled before reconfiguration. */ - CMU_OscillatorEnable(cmuOsc_LFXO, false, true); - - bool cmuBoost = (lfxoInit->boost & 0x2); - BUS_RegMaskedWrite(&CMU->CTRL, - _CMU_CTRL_LFXOTIMEOUT_MASK - | _CMU_CTRL_LFXOBOOST_MASK - | _CMU_CTRL_LFXOMODE_MASK, - ((uint32_t)lfxoInit->timeout - << _CMU_CTRL_LFXOTIMEOUT_SHIFT) - | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) - | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); -#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) - /* EFM32GG has a "reduce startup boost" field in the EMU */ - bool emuReduce = (lfxoInit->boost & 0x1); - BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); -#endif -#endif -} - -/**************************************************************************//** - * @brief - * Sets LFXO's crystal precision, in PPM. - * - * @note - * LFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_LFXOPrecisionSet(uint16_t precision) -{ - lfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets LFXO's crystal precision, in PPM. - * - * @param[in] precision - * LFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_LFXOPrecisionGet(void) -{ - return lfxo_precision; -} - -/**************************************************************************//** - * @brief - * Sets HFXO's crystal precision, in PPM. - * - * @note - * HFXO precision should be obtained from a crystal datasheet. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -void CMU_HFXOPrecisionSet(uint16_t precision) -{ - hfxo_precision = precision; -} - -/**************************************************************************//** - * @brief - * Gets HFXO's crystal precision, in PPM. - * - * @param[in] precision - * HFXO's crystal precision, in PPM. - *****************************************************************************/ -uint16_t CMU_HFXOPrecisionGet(void) -{ - return hfxo_precision; -} - -/***************************************************************************//** - * @brief - * Enable/disable oscillator. - * - * @note - * WARNING: When this function is called to disable either cmuOsc_LFXO or - * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register - * are reset to the reset value. In other words, if external clock sources are selected - * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared - * and needs to be reconfigured if needed later. - * - * @param[in] osc - * The oscillator to enable/disable. - * - * @param[in] enable - * @li true - enable specified oscillator. - * @li false - disable specified oscillator. - * - * @param[in] wait - * Only used if @p enable is true. - * @li true - wait for oscillator start-up time to timeout before returning. - * @li false - do not wait for oscillator start-up time to timeout before - * returning. - ******************************************************************************/ -void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) -{ - uint32_t rdyBitPos; -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t ensBitPos; -#endif -#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) - uint32_t hfxoTrimStatus; -#endif - - uint32_t enBit; - uint32_t disBit; - - switch (osc) { - case cmuOsc_HFRCO: - enBit = CMU_OSCENCMD_HFRCOEN; - disBit = CMU_OSCENCMD_HFRCODIS; - rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_HFXO: - enBit = CMU_OSCENCMD_HFXOEN; - disBit = CMU_OSCENCMD_HFXODIS; - rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; -#endif - break; - - case cmuOsc_AUXHFRCO: - enBit = CMU_OSCENCMD_AUXHFRCOEN; - disBit = CMU_OSCENCMD_AUXHFRCODIS; - rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_LFRCO: - enBit = CMU_OSCENCMD_LFRCOEN; - disBit = CMU_OSCENCMD_LFRCODIS; - rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; -#endif - break; - - case cmuOsc_LFXO: - enBit = CMU_OSCENCMD_LFXOEN; - disBit = CMU_OSCENCMD_LFXODIS; - rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; -#endif - break; - -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - case cmuOsc_USHFRCO: - enBit = CMU_OSCENCMD_USHFRCOEN; - disBit = CMU_OSCENCMD_USHFRCODIS; - rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; -#if defined(_SILICON_LABS_32B_SERIES_1) - ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; -#endif - break; -#endif - -#if defined(PLFRCO_PRESENT) - case cmuOsc_PLFRCO: - if (!deviceHasPlfrco()) { - while (true) { // PLFRCO is not available - EFM_ASSERT(false); - } - } - enBit = CMU_OSCENCMD_PLFRCOEN; - disBit = CMU_OSCENCMD_PLFRCODIS; - rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; - ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; - break; -#endif - - default: - /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled - and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily - intended for information: the ULFRCO is always on. */ - EFM_ASSERT(false); - return; - } - - if (enable) { - #if defined(_CMU_HFXOCTRL_MASK) - bool firstHfxoEnable = false; - - /* Enabling the HFXO for the first time requires special handling. - * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the - * first time the HFXO is enabled. */ - if (osc == cmuOsc_HFXO) { - if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { - /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); -#endif - - firstHfxoEnable = true; - /* The first time that an external clock is enabled, switch to CMD mode to make sure that - * only SCO and not PDA tuning is performed. */ - if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { - setHfxoTuningMode(HFXO_TUNING_MODE_CMD); - } - } - } -#endif - CMU->OSCENCMD = enBit; - -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Always wait for ENS to go high. */ - while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { - } -#endif - - /* Wait for the clock to become ready after enable. */ - if (wait) { - while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { - } -#if defined(_SILICON_LABS_32B_SERIES_1) - if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { - if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) - == CMU_HFXOCTRL_MODE_DIGEXTCLK) { -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - /* External clock mode should only do shunt current optimization. */ - (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, - cmuHFXOTuningMode_ShuntCommand, - true); -#endif - } else { - /* Wait for the peak detection and shunt current optimization - to complete. */ - (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); - } - - /* Disable the HFXO again to apply the trims. Apply trim from - HFXOTRIMSTATUS when disabled. */ - hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); - CMU_OscillatorEnable(cmuOsc_HFXO, false, true); - CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); - - /* Restart in CMD mode. */ - CMU->OSCENCMD = enBit; - while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { - } - } -#endif - } - } else { - CMU->OSCENCMD = disBit; - -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Always wait for ENS to go low. */ - while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { - } - - if (wait) { - /* Wait for RDY to go low as well. */ - while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { - } - } -#endif - } -} - -/***************************************************************************//** - * @brief - * Get the oscillator frequency tuning setting. - * - * @param[in] osc - * An oscillator to get tuning value for, one of the following: - * @li #cmuOsc_LFRCO - * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK - * @li #cmuOsc_USHFRCO - * @endif - * @li #cmuOsc_AUXHFRCO - * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined - * - * @return - * The oscillator frequency tuning setting in use. - ******************************************************************************/ -uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) -{ - uint32_t ret; - - switch (osc) { - case cmuOsc_LFRCO: - ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) - >> _CMU_LFRCOCTRL_TUNING_SHIFT; - break; - - case cmuOsc_HFRCO: - ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) - >> _CMU_HFRCOCTRL_TUNING_SHIFT; - break; - -#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) - case cmuOsc_USHFRCO: - ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) - >> _CMU_USHFRCOCTRL_TUNING_SHIFT; - break; -#endif - - case cmuOsc_AUXHFRCO: - ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) - >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; - break; - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - case cmuOsc_HFXO: - ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK -#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) - | _CMU_HFXOTRIMSTATUS_REGISH_MASK -#endif - ); - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - case cmuOsc_LFXO: - ret = (CMU->LFXOCTRL & _CMU_LFXOCTRL_TUNING_MASK) >> _CMU_LFXOCTRL_TUNING_SHIFT; - break; -#endif - - default: - ret = 0; - EFM_ASSERT(false); - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the oscillator frequency tuning control. - * - * @note - * Oscillator tuning is done during production and the tuning value is - * automatically loaded after reset. Changing the tuning value from the - * calibrated value is for more advanced use. Certain oscillators also have - * build-in tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_LFRCO - * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK - * @li #cmuOsc_USHFRCO - * @endif - * @li #cmuOsc_AUXHFRCO - * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. - * - * @param[in] val - * The oscillator frequency tuning setting to use. - ******************************************************************************/ -void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - uint8_t ctune = 0; -#endif - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - uint32_t regIshUpper; -#endif - - switch (osc) { - case cmuOsc_LFRCO: - EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK - >> _CMU_LFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) - | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); - break; - - case cmuOsc_HFRCO: - EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK - >> _CMU_HFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) - | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); - break; - -#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) - case cmuOsc_USHFRCO: - EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK - >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { - } -#endif - CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) - | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); - break; -#endif - - case cmuOsc_AUXHFRCO: - EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK - >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); - val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); -#if defined(_SILICON_LABS_32B_SERIES_1) - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { - } -#endif - CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) - | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); - break; - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - case cmuOsc_HFXO: - - /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ - EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); - - /* Switch to command mode. Automatic SCO and PDA calibration is not done - at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ - CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) - | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; - -#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) - >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK - | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) - | val - | regIshUpper; -#else - CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL - & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) - | val; -#endif - - break; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) - case cmuOsc_LFXO: - EFM_ASSERT(val <= (_CMU_LFXOCTRL_TUNING_MASK >> _CMU_LFXOCTRL_TUNING_SHIFT)); - // Max internal capacitance tuning value is 0x4F (20 pF) - ctune = (uint8_t) SL_MIN(0x4FU, val); - - // Wait for the CMU_LFXOCTRL is ready for update - while (BUS_RegBitRead(&CMU->SYNCBUSY, - _CMU_SYNCBUSY_LFXOBSY_SHIFT) != 0UL) { - } - CMU->LFXOCTRL = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK)) - | ((uint32_t)ctune << _CMU_LFXOCTRL_TUNING_SHIFT); - break; -#endif - - default: - EFM_ASSERT(false); - break; - } -} - -#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) -/***************************************************************************//** - * @brief - * Wait for the oscillator tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_HFXO - * - * @param[in] mode - * Tuning optimization mode. - * - * @return - * Returns false on invalid parameters or oscillator error status. - ******************************************************************************/ -bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode) -{ - uint32_t waitFlags; - EFM_ASSERT(osc == cmuOsc_HFXO); - - /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ - (void)osc; - - if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { - waitFlags = HFXO_TUNING_READY_FLAGS; - } else { - /* Set wait flags for each command and wait. */ - switch (mode) { -#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) - case cmuHFXOTuningMode_ShuntCommand: - waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; - break; -#endif - case cmuHFXOTuningMode_Auto: - waitFlags = HFXO_TUNING_READY_FLAGS; - break; - -#if defined(CMU_CMD_HFXOSHUNTOPTSTART) - case cmuHFXOTuningMode_PeakShuntCommand: - waitFlags = HFXO_TUNING_READY_FLAGS; - break; -#endif - - default: - waitFlags = _CMU_STATUS_MASK; - EFM_ASSERT(false); - break; - } - } - while ((CMU->STATUS & waitFlags) != waitFlags) { - } - -#if defined(CMU_IF_HFXOPEAKDETERR) - /* Check error flags. */ - if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { - return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; - } -#endif - return true; -} - -/***************************************************************************//** - * @brief - * Start and optionally wait for the oscillator tuning optimization. - * - * @param[in] osc - * An oscillator to set tuning value for, one of the following: - * @li #cmuOsc_HFXO - * - * @param[in] mode - * Tuning optimization mode. - * - * @param[in] wait - * Wait for tuning optimization to complete. - * true - wait for tuning optimization to complete. - * false - return without waiting. - * - * @return - * Returns false on invalid parameters or oscillator error status. - ******************************************************************************/ -bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, - CMU_HFXOTuningMode_TypeDef mode, - bool wait) -{ - switch (osc) { - case cmuOsc_HFXO: - if ((unsigned)mode != 0U) { -#if defined(CMU_IF_HFXOPEAKDETERR) - /* Clear the error flag before command write. */ - CMU->IFC = CMU_IFC_HFXOPEAKDETERR; -#endif - CMU->CMD = (uint32_t)mode; - } - if (wait) { - return CMU_OscillatorTuningWait(osc, mode); - } - break; - - default: - EFM_ASSERT(false); - break; - } - return true; -} -#endif - -/**************************************************************************//** - * @brief - * Determine if the currently selected PCNTn clock used is external or LFBCLK. - * - * @param[in] instance - * PCNT instance number to get currently selected clock source for. - * - * @return - * @li true - selected clock is external clock. - * @li false - selected clock is LFBCLK. - *****************************************************************************/ -bool CMU_PCNTClockExternalGet(unsigned int instance) -{ - uint32_t setting; - - switch (instance) { -#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) - case 0: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; - break; - -#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) - case 1: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; - break; - -#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) - case 2: - setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; - break; -#endif -#endif -#endif - - default: - setting = 0; - break; - } - return setting > 0UL ? true : false; -} - -/**************************************************************************//** - * @brief - * Select the PCNTn clock. - * - * @param[in] instance - * PCNT instance number to set selected clock source for. - * - * @param[in] external - * Set to true to select the external clock, false to select LFBCLK. - *****************************************************************************/ -void CMU_PCNTClockExternalSet(unsigned int instance, bool external) -{ -#if defined(PCNT_PRESENT) - uint32_t setting = 0; - - EFM_ASSERT(instance < (unsigned)PCNT_COUNT); - - if (external) { - setting = 1; - } - - BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); - -#else - (void)instance; /* An unused parameter */ - (void)external; /* An unused parameter */ -#endif -} - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/***************************************************************************//** - * @brief - * Get USHFRCO band in use. - * - * @return - * USHFRCO band in use. - ******************************************************************************/ -CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) -{ - return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF - & _CMU_USHFRCOCONF_BAND_MASK) - >> _CMU_USHFRCOCONF_BAND_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get USHFRCO frequency. - * - * @return - * USHFRCO frequency. - ******************************************************************************/ -uint32_t CMU_USHFRCOFreqGet(void) -{ - return ushfrcoFreq; -} -#endif - -#if defined(_CMU_USHFRCOCONF_BAND_MASK) -/***************************************************************************//** - * @brief - * Set the USHFRCO band to use. - * - * @param[in] band - * USHFRCO band to activate. - ******************************************************************************/ -void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) -{ - uint32_t tuning; - uint32_t fineTuning; - - /* Cannot switch band if USHFRCO is already selected as HF clock. */ - EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCODIV2); - - /* Read tuning value from calibration table. */ - switch (band) { - case cmuUSHFRCOBand_24MHz: - tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; - fineTuning = (DEVINFO->USHFRCOCAL0 - & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; - ushfrcoFreq = 24000000UL; - break; - - case cmuUSHFRCOBand_48MHz: - tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; - fineTuning = (DEVINFO->USHFRCOCAL0 - & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) - >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; - /* Enable the clock divider before switching the band from 24 to 48 MHz */ - BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); - ushfrcoFreq = 48000000UL; - break; - - default: - EFM_ASSERT(false); - return; - } - - /* Set band and tuning. */ - CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) - | (band << _CMU_USHFRCOCONF_BAND_SHIFT); - CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) - | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); - CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) - | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); - - /* Disable the clock divider after switching the band from 48 to 24 MHz. */ - if (band == cmuUSHFRCOBand_24MHz) { - BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); - } -} -#endif - -#endif // defined(_SILICON_LABS_32B_SERIES_2) -/** @} (end addtogroup cmu) */ -#endif /* defined(CMU_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Clock management unit (CMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_cmu.h" +#if defined(CMU_PRESENT) + +#include +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "sl_common.h" +#include "em_emu.h" +#include "em_gpio.h" +#include "em_system.h" +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +#include "em_msc.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +/***************************************************************************//** + * @addtogroup cmu CMU - Clock Management Unit + * @brief Clock management unit (CMU) Peripheral API + * @details + * This module contains functions for the CMU peripheral of Silicon Labs 32-bit + * MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock + * multiplexers, pre-scalers, calibration modules and wait-states. + * @{ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +// Maximum allowed core frequency vs. wait-states on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL + +// Maximum allowed core frequency vs. wait-states on sram accesses. +#define CMU_MAX_SRAM_FREQ_0WS 50000000UL +#define CMU_MAX_SRAM_FREQ_1WS 80000000UL + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 40000000UL +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +// Maximum allowed core frequency vs. wait-states and vscale on flash accesses. +#define CMU_MAX_FREQ_0WS_1V1 40000000UL + +#define CMU_MAX_FREQ_0WS_1V0 20000000UL +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define CMU_MAX_FREQ_0WS_1V1 25000000UL +#define CMU_MAX_FREQ_1WS_1V1 50000000UL +#define CMU_MAX_FREQ_2WS_1V1 75000000UL +#else + #warning "MCU flash wait states not supported" +#endif + +// Maximum allowed PCLK frequency. +#define CMU_MAX_PCLK_FREQ 50000000UL + +// Maximum allowed RHCLK frequency. +#define CMU_MAX_RHCLK_FREQ 40000000UL + +#if defined(EMU_VSCALE_EM01_PRESENT) +// This macro is intended to be used as input to CMU_UpdateWaitStates() +#define VSCALE_DEFAULT (2 - (int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +#if defined(PLFRCO_PRESENT) +// Typical frequency for HFXO as recommanded in the datasheets. +// see AN0016: Oscillator Design Considerations +// +// Recommended for most wireless applications +// to meet transceiver electrical specifications +#define XTAL_38M4 38400000UL +// Recommended for implementing Z-Wave devices +#define XTAL_39M0 39000000UL +// High Precision mode calibration Counts for 38.4MHz +#define LFRCO_NOMCAL_XTAL_38M4 _LFRCO_NOMCAL_RESETVALUE +#define LFRCO_NOMCALINV_XTAL_38M4 _LFRCO_NOMCALINV_RESETVALUE +// High Precision mode calibration Counts for 39.0MHz. +#define LFRCO_NOMCAL_XTAL_39M0 0x0005CFBBUL +#define LFRCO_NOMCALINV_XTAL_39M0 0x0000581AUL +#endif + +#define PLL0_USB_OUTPUT_FREQ 48000000UL + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Table of HFRCOCAL values and their associated min/max frequencies and +// optional band enumerator. +static const struct hfrcoCalTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCODPLLFreq_TypeDef band; +} hfrcoCalTable[] = +{ + // minFreq maxFreq HFRCOCAL value band + { 900000UL, 1080000UL, 0x82401F00UL, cmuHFRCODPLLFreq_1M0Hz }, + { 1080000UL, 1300000UL, 0xA2411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1300000UL, 1530000UL, 0xA2421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1530000UL, 1800000UL, 0xB6439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 1800000UL, 2150000UL, 0x81401F00UL, cmuHFRCODPLLFreq_2M0Hz }, + { 2150000UL, 2600000UL, 0xA1411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 2600000UL, 3050000UL, 0xA1421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3050000UL, 3600000UL, 0xB5439F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 3600000UL, 4300000UL, 0x80401F00UL, cmuHFRCODPLLFreq_4M0Hz }, + { 4300000UL, 5200000UL, 0xA0411F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 5200000UL, 6100000UL, 0xA0421F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 6100000UL, 7800000UL, 0xB4439F00UL, cmuHFRCODPLLFreq_7M0Hz }, + { 7800000UL, 9800000UL, 0xB4449F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 9800000UL, 11800000UL, 0xB4459F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0xB4669F00UL, cmuHFRCODPLLFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0xB4679F00UL, cmuHFRCODPLLFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0xA8689F00UL, cmuHFRCODPLLFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0xB8899F3AUL, (CMU_HFRCODPLLFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0xB88A9F00UL, cmuHFRCODPLLFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0xB8AB9F00UL, cmuHFRCODPLLFreq_32M0Hz }, + { 34800000UL, 42800000UL, 0xA8CC9F00UL, cmuHFRCODPLLFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0xACED9F00UL, cmuHFRCODPLLFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0xBCEE9F00UL, cmuHFRCODPLLFreq_56M0Hz }, + { 60500000UL, 72600000UL, 0xBCEF9F00UL, cmuHFRCODPLLFreq_64M0Hz }, + { 72600000UL, 80000000UL, 0xCCF09F00UL, cmuHFRCODPLLFreq_80M0Hz }, +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + { 80000000UL, 100000000UL, 0xCCF19F00UL, cmuHFRCODPLLFreq_100M0Hz } +#endif +}; + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +#define HFRCOCALTABLE_ENTRIES (sizeof(hfrcoCalTable) \ + / sizeof(struct hfrcoCalTableElement)) + +// CTUNE delta needed for some series 2 chips. This delta is added to the tuning capacitance on XO. +// The inter-chip buffered crystal sharing feature added from the EFR32xG23 creates an imbalance +// between XI and XO capacitance load internally on the chip. The delta allows to compensate for +// the difference. +#if defined(_SILICON_LABS_32B_SERIES_2) +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +static int8_t ctuneDelta = 40; // Recommendation from analog team to counter the internal chip imbalance. +#else +static int8_t ctuneDelta = 0; +#endif +#endif + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUART_PRESENT) +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(EUSART_PRESENT) +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(LCD_PRESENT) +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(VDAC_PRESENT) +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if (VDAC_COUNT > 1) +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#endif +#if defined(PCNT_PRESENT) +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if defined(LESENSE_PRESENT) +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +static void rhclkPrescMax(void); +static void rhclkPrescOptimize(void); +#endif +#endif + +#if defined(HFRCOEM23_PRESENT) +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq); +#endif +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale); +static void flashWaitStateControl(uint32_t coreFreq, int vscale); +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq); +#if defined(IADC_PRESENT) +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void pclkDivMax(void); +static void pclkDivOptimize(void); +#if defined(RTCC_PRESENT) +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#elif defined(SYSRTC_PRESENT) +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void waitStateMax(void); +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if WDOG_COUNT > 1 +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#if defined(USB_PRESENT) +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel); +#endif +/** @endcond */ + +// The following code is common for all SERIES_2 configurations. + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Calibrate an oscillator. + * + * @details + * Run a calibration of a selectable reference clock againt HCLK. Please + * refer to the reference manual, CMU chapter, for further details. + * + * @note + * This function will not return until calibration measurement is completed. + * + * @param[in] cycles + * The number of HCLK cycles to run calibration. Increasing this number + * increases precision, but the calibration will take more time. + * + * @param[in] ref + * The reference clock used to compare against HCLK. + * + * @return + * The number of ticks the selected reference clock ticked while running + * cycles ticks of the HCLK clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref) +{ + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(cycles <= (_CMU_CALTOP_CALTOP_MASK + >> _CMU_CALTOP_CALTOP_SHIFT)); +#endif + + CMU_CalibrateConfig(cycles, cmuSelect_HCLK, ref); + CMU_CalibrateStart(); + return CMU_CalibrateCountGet(); +} + +/***************************************************************************//** + * @brief + * Configure clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * Refer to the reference manual, CMU chapter, for further details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required, and + * the resulting calibration value can be read with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run calibration. Increasing this + * number increases precision, but the calibration will take more time. + * + * @param[in] downSel + * The clock which will be counted down downCycles cycles. + * + * @param[in] upSel + * The reference clock, the number of cycles generated by this clock will + * be counted and added up, the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, + CMU_Select_TypeDef upSel) +{ + // Keep untouched configuration settings + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK + | _CMU_CALCTRL_DOWNSEL_MASK +#if defined(_CMU_CALCTRL_CALTOP_MASK) + | _CMU_CALCTRL_CALTOP_MASK +#endif + ); + + // Check for cycle count overflow +#if defined(_CMU_CALCTRL_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALCTRL_CALTOP_MASK + >> _CMU_CALCTRL_CALTOP_SHIFT)); + calCtrl |= downCycles; +#elif defined(_CMU_CALTOP_CALTOP_MASK) + EFM_ASSERT(downCycles <= (_CMU_CALTOP_CALTOP_MASK >> _CMU_CALTOP_CALTOP_SHIFT)); + CMU->CALTOP = downCycles << _CMU_CALTOP_CALTOP_SHIFT; +#endif + + // Set down counting clock source selector + switch (downSel) { + case cmuSelect_HCLK: + calCtrl |= CMU_CALCTRL_DOWNSEL_HCLK; + break; + + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_DOWNSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + // Set up counting clock source selector + switch (upSel) { + case cmuSelect_PRS: + calCtrl |= CMU_CALCTRL_UPSEL_PRS; + break; + + case cmuSelect_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuSelect_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuSelect_HFRCODPLL: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + calCtrl |= CMU_CALCTRL_UPSEL_FSRCO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + + case cmuSelect_ULFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + break; + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} + +/***************************************************************************//** + * @brief + * Get calibration count value. + * + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off, and reading the value will be just needed, where the normal + * case would be that this function call has been triggered by the CALRDY + * interrupt flag. + * + * @return + * Calibration count, the number of UPSEL clocks (see @ref CMU_CalibrateConfig()) + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + // Wait until calibration completes, UNLESS continuous calibration mode is on + if ((CMU->CALCTRL & CMU_CALCTRL_CONT) == 0UL) { + // Wait until calibration completes + while ((CMU->STATUS & CMU_STATUS_CALRDY) == 0UL) { + } + } + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Direct a clock to a GPIO pin. + * + * @param[in] clkNo + * Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2. + * + * @param[in] sel + * Select clock source. + * + * @param[in] clkDiv + * Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is + * selected as clock source. + * + * @param[in] port + * GPIO port. + * + * @param[in] pin + * GPIO pin. + * + * @note + * Refer to the reference manual and the datasheet for details on which + * GPIO port/pins that are available. + ******************************************************************************/ +void CMU_ClkOutPinConfig(uint32_t clkNo, + CMU_Select_TypeDef sel, + CMU_ClkDiv_TypeDef clkDiv, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + uint32_t tmp = 0U, mask; + + EFM_ASSERT(pin <= 15U); + + switch (clkNo) { + case 0: + case 1: + EFM_ASSERT((port == 2U) || (port == 3U)); + break; + case 2: + EFM_ASSERT((port == 0U) || (port == 1U)); + break; + default: + EFM_ASSERT(false); + break; + } + + switch (sel) { + case cmuSelect_Disabled: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO; + break; + + case cmuSelect_HFRCODPLL: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCOEM23; + break; +#endif + + case cmuSelect_EXPCLK: + EFM_ASSERT((clkDiv > 0U) && (clkDiv <= 32U)); + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK; + break; + + case cmuSelect_LFXO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO; + break; + + case cmuSelect_HCLK: + tmp = CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK; + break; + + default: + EFM_ASSERT(false); + break; + } + + mask = _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK + << (clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT); + tmp <<= clkNo * _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT; + + if (sel == cmuSelect_EXPCLK) { + tmp |= (clkDiv - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + mask |= _CMU_EXPORTCLKCTRL_PRESC_MASK; + } + + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~mask) | tmp; + + if (sel == cmuSelect_Disabled) { + GPIO->CMUROUTE_CLR.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + GPIO_PinModeSet(port, pin, gpioModeDisabled, 0); + } else { + GPIO->CMUROUTE_SET.ROUTEEN = GPIO_CMU_ROUTEEN_CLKOUT0PEN << clkNo; + if (clkNo == 0U) { + GPIO->CMUROUTE.CLKOUT0ROUTE = (port << _GPIO_CMU_CLKOUT0ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT0ROUTE_PIN_SHIFT); + } else if (clkNo == 1) { + GPIO->CMUROUTE.CLKOUT1ROUTE = (port << _GPIO_CMU_CLKOUT1ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT1ROUTE_PIN_SHIFT); + } else { + GPIO->CMUROUTE.CLKOUT2ROUTE = (port << _GPIO_CMU_CLKOUT2ROUTE_PORT_SHIFT) + | (pin << _GPIO_CMU_CLKOUT2ROUTE_PIN_SHIFT); + } + GPIO_PinModeSet(port, pin, gpioModePushPull, 0); + } +} + +/***************************************************************************//** + * @brief + * Get clock divisor. + * + * @param[in] clock + * Clock point to get divisor for. Notice that not all clock points + * have a divisors. Please refer to CMU overview in reference manual. + * + * @return + * The current clock point divisor. 1 is returned + * if @p clock specifies a clock point without divisor. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_HCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (ret == 2U ) { // Unused value, illegal prescaler + EFM_ASSERT(false); + } +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + if (!((ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV1) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV2) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV4) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV8) + || (ret == _CMU_SYSCLKCTRL_HCLKPRESC_DIV16))) { + // Illegal prescaler + EFM_ASSERT(false); + } +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: + ret = (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_PRESC_MASK) + >> _CMU_TRACECLKCTRL_PRESC_SHIFT; + if (!((ret == _CMU_TRACECLKCTRL_PRESC_DIV1) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV2) +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV3) +#endif + || (ret == _CMU_TRACECLKCTRL_PRESC_DIV4))) { + // Illegal prescaler + EFM_ASSERT(false); + } + break; +#endif + + case cmuClock_EXPCLK: + ret = (CMU->EXPORTCLKCTRL & _CMU_EXPORTCLKCTRL_PRESC_MASK) + >> _CMU_EXPORTCLKCTRL_PRESC_SHIFT; + break; + + case cmuClock_PCLK: + ret = (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_PCLKPRESC_MASK) + >> _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT; + break; + + default: + break; + } + return 1U + ret; +} + +/***************************************************************************//** + * @brief + * Set clock divisor. + * + * @param[in] clock + * Clock point to set divisor for. Notice that not all clock points + * have a divisor, please refer to CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use. + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { + case cmuClock_HCLK: + case cmuClock_CORE: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U) + || (div == 8U) || (div == 16U)); +#endif + + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Set new divisor + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_HCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT); + + // Update CMSIS core clock variable and set optimum wait-states + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + break; + +#if defined(_CMU_TRACECLKCTRL_PRESC_MASK) + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif +#if defined(_CMU_TRACECLKCTRL_PRESC_DIV3) + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 3U) || (div == 4U)); +#else + EFM_ASSERT((div == 1U) || (div == 2U) || (div == 4U)); +#endif + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_TRACECLKCTRL_PRESC_SHIFT); +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + + case cmuClock_EXPCLK: + EFM_ASSERT((div >= 1U) && (div <= 32U)); + CMU->EXPORTCLKCTRL = (CMU->EXPORTCLKCTRL & ~_CMU_EXPORTCLKCTRL_PRESC_MASK) + | ((div - 1U) << _CMU_EXPORTCLKCTRL_PRESC_SHIFT); + break; + + case cmuClock_PCLK: + EFM_ASSERT((div == 1U) || (div == 2U)); + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_PCLKPRESC_MASK) + | ((div - 1U) << _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT); + break; + + default: + EFM_ASSERT(false); + break; + } +} + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * Module clocks sre disabled after reset. If a module clock is disabled, the + * registers of that module are not accessible and accessing such registers + * will hardfault the Cortex core. + * + * @param[in] clock + * The clock to enable/disable. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg = NULL; + uint32_t bit; + + /* Identify the enable register. */ + if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_NO_EN_REG) { + EFM_ASSERT(false); /* No enable for this clock. */ + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN0_EN_REG) { + reg = &CMU->CLKEN0; + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN1_EN_REG) { + reg = &CMU->CLKEN1; +#if defined(_CMU_CLKEN2_MASK) + } else if (((unsigned)clock >> CMU_EN_REG_POS) == CMU_CLKEN2_EN_REG) { + reg = &CMU->CLKEN2; +#endif + } else { +#if defined(CRYPTOACC_PRESENT) + reg = &CMU->CRYPTOACCCLKCTRL; +#else + // No register to enable clock. Possible hard fault exception. + EFM_ASSERT(false); +#endif + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_CORE: + case cmuClock_HCLK: + case cmuClock_LDMA: + case cmuClock_GPCRC: + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_I2C1: + case cmuClock_PRS: + case cmuClock_PCLK: + case cmuClock_GPIO: + case cmuClock_USART0: + case cmuClock_USART1: + case cmuClock_USART2: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_I2C0: + case cmuClock_LSPCLK: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: + em4GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; + + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; + + case cmuClock_DPLLREFCLK: + dpllRefClkGet(&ret, NULL); + break; + + case cmuClock_TRACECLK: + traceClkGet(&ret, NULL); + break; + + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +/***************************************************************************//** + * @brief + * Get clock frequency for a clock point. + * + * @param[in] clock + * Clock point to fetch frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret = 0U; + uint32_t freq = 0U; + + switch (clock) { + case cmuClock_SYSCLK: + ret = SystemSYSCLKGet(); + break; + + case cmuClock_HCLK: + case cmuClock_CORE: + case cmuClock_ICACHE: + case cmuClock_MSC: + case cmuClock_LDMA: + case cmuClock_SMU: +#if defined(RADIOAES_PRESENT) + case cmuClock_RADIOAES: +#endif +#if defined(CRYPTOACC_PRESENT) + case cmuClock_CRYPTOACC: + case cmuClock_CRYPTOAES: + case cmuClock_CRYPTOPK: +#endif +#if defined(MVP_PRESENT) + case cmuClock_MVP: +#endif + ret = SystemHCLKGet(); + break; + + case cmuClock_EXPCLK: + ret = SystemSYSCLKGet() / CMU_ClockDivGet(cmuClock_EXPCLK); + break; + + case cmuClock_PCLK: +#if defined(USART_PRESENT) + case cmuClock_USART0: +#if USART_COUNT > 1 + case cmuClock_USART1: +#endif +#endif + case cmuClock_I2C1: + case cmuClock_PRS: + case cmuClock_GPIO: + case cmuClock_GPCRC: + case cmuClock_LDMAXBAR: + case cmuClock_SYSCFG: + case cmuClock_DCDC: + case cmuClock_BURAM: + case cmuClock_DPLL0: + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK); + break; + + case cmuClock_LSPCLK: + case cmuClock_I2C0: + case cmuClock_AMUXCP0: +#if defined(ACMP_PRESENT) + case cmuClock_ACMP0: +#if ACMP_COUNT > 1 + case cmuClock_ACMP1: +#endif +#endif + ret = SystemHCLKGet() / CMU_ClockDivGet(cmuClock_PCLK) / 2U; + break; + + case cmuClock_TRACECLK: + traceClkGet(&freq, NULL); + ret = freq / CMU_ClockDivGet(cmuClock_TRACECLK); + break; + + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(&ret, NULL); + break; +#if defined(PDM_PRESENT) + case cmuClock_PDM: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(&ret, NULL); + break; +#endif +#if defined(EUART_PRESENT) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(&ret, NULL); + break; +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 0 + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(&ret, NULL); + break; +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(&ret, NULL); + break; +#endif +#endif + +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(&ret, NULL); + break; +#endif + + case cmuClock_SYSTICK: + sysTickClkGet(&ret, NULL); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(&ret, NULL); + break; + + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(&ret, NULL); + break; +#if WDOG_COUNT > 1 + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(&ret, NULL); + break; +#endif +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(&ret, NULL); + break; +#endif +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(&ret, NULL); + break; +#endif +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(&ret, NULL); + break; +#endif +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(&ret, NULL); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(&ret, NULL); + break; +#endif +#endif /* VDAC_PRESENT */ +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(&ret, NULL); + break; +#endif +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(&ret, NULL); + break; +#endif + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(&ret, NULL); + break; + +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(&ret, NULL); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif // (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +/***************************************************************************//** + * @brief + * Get currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. + * + * @return + * Reference clock used for clocking selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Error; + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK) { + case CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL: + ret = cmuSelect_HFRCODPLL; + break; + + case CMU_SYSCLKCTRL_CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SYSCLKCTRL_CLKSEL_CLKIN0: + ret = cmuSelect_CLKIN0; + break; + + case CMU_SYSCLKCTRL_CLKSEL_FSRCO: + ret = cmuSelect_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS: + ret = cmuSelect_RFFPLLSYS; + break; +#endif + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + iadcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + em01GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + sysTickClkGet(NULL, &ret); + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + em23GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: + case cmuClock_EM4GRPACLK: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + em4GrpaClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + em01GrpbClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + wdog0ClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + wdog1ClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + dpllRefClkGet(NULL, &ret); + break; + +// ----------------------------------------------------------------------------- +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + case cmuClock_TRACECLK: + traceClkGet(NULL, &ret); + break; +#endif + +// ----------------------------------------------------------------------------- +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + euart0ClkGet(NULL, &ret); + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + eusart0ClkGet(NULL, &ret); + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + em01GrpcClkGet(NULL, &ret); + break; +#endif + #endif + +// ----------------------------------------------------------------------------- +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + rtccClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + sysrtcClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + lcdClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + vdac0ClkGet(NULL, &ret); + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + vdac1ClkGet(NULL, &ret); + break; +#endif +#endif +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + pcnt0ClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + lesenseHFClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + usbClkGet(NULL, &ret); + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +/***************************************************************************//** + * @brief Performs pre-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPreClockSelect(void) +{ +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif +} + +/***************************************************************************//** + * @brief Performs post-clock-selection operations to initialize the system clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK. + ******************************************************************************/ +void sli_em_cmu_SYSCLKInitPostClockSelect(void) +{ + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif +} + +/***************************************************************************//** + * @brief Sets the HFXO0 FORCEEN bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSCLK and the selected clock source is HFXO. + ******************************************************************************/ +void sli_em_cmu_HFXOSetForceEnable(void) +{ +#if defined(_CMU_CLKEN0_MASK) && defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +} + +/***************************************************************************//** + * @brief This function will set the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENSet(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_setSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief This function will clear the SYSCFG->CFGSYSTIC bit. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is SYSTICK. + ******************************************************************************/ +void sli_em_cmu_SYSTICEXTCLKENClear(void) +{ +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + bool syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} + +/***************************************************************************//** + * @brief + * Select reference clock/oscillator used for a clock branch. + * + * @param[in] clock + * Clock branch to select reference clock for. + * + * @param[in] ref + * Reference selected for clocking, please refer to reference manual for + * for details on which reference is available for a specific clock branch. + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t tmp = 0U; + bool oscForceEnStatus = false; +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + bool syscfgClkIsOff = false; +#endif +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + bool restoreTrace; +#endif + + switch (clock) { +// ----------------------------------------------------------------------------- + case cmuClock_SYSCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_SYSCLKCTRL_CLKSEL_HFXO; +#if defined(_CMU_CLKEN0_MASK) +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif +#endif + // Make sure HFXO is enabled. + oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_SYSCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_FSRCO: + tmp = CMU_SYSCLKCTRL_CLKSEL_FSRCO; + break; + +#if defined(RFFPLL_PRESENT) + case cmuSelect_RFFPLLSYS: + tmp = CMU_SYSCLKCTRL_CLKSEL_RFFPLL0SYS; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + // VSCALE up before changing clock. + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, true); +#endif + + // Set max wait-states and PCLK divisor while changing core clock. + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Switch to selected oscillator. + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | tmp; + + // Update CMSIS core clock variable and set optimum wait-states. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(EMU_VSCALE_EM01_PRESENT) + // Check if possible to downscale VSCALE setting. + EMU_VScaleEM01ByClock(0, true); +#endif + + // Set optimal PCLK divisor + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + + if (oscForceEnStatus == false) { + switch (ref) { + case cmuSelect_HFXO: + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + break; + + default: + break; + } + } + break; + +// ----------------------------------------------------------------------------- +#if defined(IADC_PRESENT) + case cmuClock_IADC0: + case cmuClock_IADCCLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_IADCCLKCTRL_CLKSEL_FSRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->IADCCLKCTRL = (CMU->IADCCLKCTRL & ~_CMU_IADCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_TIMER0: + case cmuClock_TIMER1: + case cmuClock_TIMER2: + case cmuClock_TIMER3: +#if TIMER_COUNT > 4 + case cmuClock_TIMER4: +#endif +#if TIMER_COUNT > 7 + case cmuClock_TIMER5: + case cmuClock_TIMER6: + case cmuClock_TIMER7: +#endif +#if TIMER_COUNT > 9 + case cmuClock_TIMER8: + case cmuClock_TIMER9: +#endif +#if defined(KEYSCAN_PRESENT) + case cmuClock_KEYSCAN: +#endif + case cmuClock_EM01GRPACLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuSelect_HFRCOEM23: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL + & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_SYSTICK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + case cmuSelect_LFXO: + case cmuSelect_LFRCO: + case cmuSelect_ULFRCO: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_setSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_setSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL & ~SysTick_CTRL_CLKSOURCE_Msk); + break; + case cmuSelect_HCLK: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + SYSCFG_clearSysTicExtClkEnCfgSysTic(); +#else + syscfgClkIsOff = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) == 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + SYSCFG_clearSysTicExtClkEnCfgSysTic(); + if (syscfgClkIsOff) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif + SysTick->CTRL = (SysTick->CTRL | SysTick_CTRL_CLKSOURCE_Msk); + break; + default: + EFM_ASSERT(false); + break; + } + break; + + case cmuClock_LETIMER0: + case cmuClock_EM23GRPACLK: +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + case cmuClock_LESENSECLK: +#endif + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM23GRPACLKCTRL = (CMU->EM23GRPACLKCTRL + & ~_CMU_EM23GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +// ----------------------------------------------------------------------------- + case cmuClock_BURTC: +#if defined(ETAMPDET_PRESENT) + case cmuClock_ETAMPDET: +#endif + case cmuClock_EM4GRPACLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM4GRPACLKCTRL = (CMU->EM4GRPACLKCTRL + & ~_CMU_EM4GRPACLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_PDMREF: + case cmuClock_EM01GRPBCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL; + break; + + case cmuSelect_HFXO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_FSRCO: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT; + break; + + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT; + break; + + case cmuSelect_Disabled: + tmp = CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL + & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_WDOG0: + case cmuClock_WDOG0CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG0CLKCTRL = (CMU->WDOG0CLKCTRL & ~_CMU_WDOG0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(_CMU_WDOG1CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_WDOG1: + case cmuClock_WDOG1CLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_HCLKDIV1024: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024; + break; + + case cmuSelect_Disabled: + tmp = CMU_WDOG1CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->WDOG1CLKCTRL = (CMU->WDOG1CLKCTRL & ~_CMU_WDOG1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif + +// ----------------------------------------------------------------------------- + case cmuClock_DPLLREFCLK: + switch (ref) { + case cmuSelect_HFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; + break; + + case cmuSelect_LFXO: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_CLKIN0: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0; + break; + + case cmuSelect_Disabled: + tmp = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->DPLLREFCLKCTRL = (CMU->DPLLREFCLKCTRL + & ~_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) | tmp; + break; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_TRACECLK: +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + restoreTrace = CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk; + if (restoreTrace) { + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + switch (ref) { +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + case cmuSelect_HCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_HCLK; + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + case cmuSelect_SYSCLK: + tmp = CMU_TRACECLKCTRL_CLKSEL_SYSCLK; + break; + + case cmuSelect_HFRCODPLLRT: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->TRACECLKCTRL = (CMU->TRACECLKCTRL & ~_CMU_TRACECLKCTRL_CLKSEL_MASK) + | tmp; +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)) \ + && defined(CoreDebug_DEMCR_TRCENA_Msk) + if (restoreTrace) { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } +#endif + break; +#endif + +#if defined(_CMU_EUART0CLKCTRL_CLKSEL_MASK) +// ----------------------------------------------------------------------------- + case cmuClock_EUART0: + case cmuClock_EUART0CLK: + switch (ref) { + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_Disabled: + tmp = _CMU_EUART0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->EUART0CLKCTRL = (CMU->EUART0CLKCTRL & ~_CMU_EUART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#elif defined(EUSART_PRESENT) + case cmuClock_EUSART0: + case cmuClock_EUSART0CLK: + switch (ref) { +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case cmuSelect_EM01GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case cmuSelect_EM01GRPCCLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case cmuSelect_EM23GRPACLK: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case cmuSelect_FSRCO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_FSRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case cmuSelect_HFRCOEM23: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFRCO; + break; +#endif +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case cmuSelect_LFXO: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_LFXO; + break; +#endif + +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case cmuSelect_Disabled: + tmp = _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + CMU->EUSART0CLKCTRL = (CMU->EUSART0CLKCTRL & ~_CMU_EUSART0CLKCTRL_CLKSEL_MASK) + | tmp; + break; + +#if defined(EUSART_PRESENT) && EUSART_COUNT > 1 + case cmuClock_EUSART1: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 2 + case cmuClock_EUSART2: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 3 + case cmuClock_EUSART3: +#endif +#if defined(EUSART_PRESENT) && EUSART_COUNT > 4 + case cmuClock_EUSART4: +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) + case cmuClock_EM01GRPCCLK: + switch (ref) { + case cmuSelect_HFRCODPLL: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case cmuSelect_HFRCODPLLRT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT; + break; +#endif + case cmuSelect_HFRCOEM23: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23; + break; + + case cmuSelect_FSRCO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; + break; + + case cmuSelect_HFXO: + tmp = _CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case cmuSelect_HFXORT: + tmp = CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif + +// ----------------------------------------------------------------------------- +#if defined (RTCC_PRESENT) + case cmuClock_RTCC: + case cmuClock_RTCCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_RTCCCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->RTCCCLKCTRL = (CMU->RTCCCLKCTRL & ~_CMU_RTCCCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined (SYSRTC_PRESENT) + case cmuClock_SYSRTC: + case cmuClock_SYSRTCCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO; + break; + + case cmuSelect_Disabled: + tmp = CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->SYSRTC0CLKCTRL = (CMU->SYSRTC0CLKCTRL & ~_CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LCD_PRESENT) + case cmuClock_LCD: + case cmuClock_LCDCLK: + switch (ref) { + case cmuSelect_LFRCO: +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: +#endif + tmp = CMU_LCDCLKCTRL_CLKSEL_LFRCO; + break; + + case cmuSelect_LFXO: + tmp = CMU_LCDCLKCTRL_CLKSEL_LFXO; + break; + + case cmuSelect_ULFRCO: + tmp = CMU_LCDCLKCTRL_CLKSEL_ULFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LCDCLKCTRL = (CMU->LCDCLKCTRL & ~_CMU_LCDCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(VDAC_PRESENT) + case cmuClock_VDAC0: + case cmuClock_VDAC0CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC0CLKCTRL = (CMU->VDAC0CLKCTRL & ~_CMU_VDAC0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#if (VDAC_COUNT > 1) + case cmuClock_VDAC1: + case cmuClock_VDAC1CLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23; + break; + case cmuSelect_EM01GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK; + break; + case cmuSelect_EM23GRPACLK: + tmp = CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->VDAC1CLKCTRL = (CMU->VDAC1CLKCTRL & ~_CMU_VDAC1CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +#endif /* VDAC_PRESENT */ +// ----------------------------------------------------------------------------- +#if defined(PCNT_PRESENT) + case cmuClock_PCNT0: + case cmuClock_PCNT0CLK: + switch (ref) { + case cmuSelect_EM23GRPACLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + break; + + case cmuSelect_PCNTEXTCLK: + tmp = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->PCNT0CLKCTRL = (CMU->PCNT0CLKCTRL & ~_CMU_PCNT0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSEHFCLK: + switch (ref) { + case cmuSelect_FSRCO: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO; + break; + case cmuSelect_HFRCOEM23: + tmp = CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->LESENSEHFCLKCTRL = (CMU->LESENSEHFCLKCTRL & ~_CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- +#if defined(USB_PRESENT) + case cmuClock_USB: + switch (ref) { + case cmuSelect_USBPLL0: + tmp = CMU_USB0CLKCTRL_CLKSEL_USBPLL0; + break; + case cmuSelect_LFXO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFXO; + break; + case cmuSelect_LFRCO: + tmp = CMU_USB0CLKCTRL_CLKSEL_LFRCO; + break; + + default: + EFM_ASSERT(false); + break; + } + CMU->USB0CLKCTRL = (CMU->USB0CLKCTRL & ~_CMU_USB0CLKCTRL_CLKSEL_MASK) + | tmp; + break; +#endif +// ----------------------------------------------------------------------------- + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(PLFRCO_PRESENT) +#if defined(LFRCO_CFG_HIGHPRECEN) + case cmuSelect_LFRCO: + case cmuSelect_PLFRCO: + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { + precision = 500; + } else { + precision = 0xFFFF; + } + break; +#endif +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCODPLL: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Get HFRCODPLL band in use. + * + * @return + * HFRCODPLL band in use. + ******************************************************************************/ +CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void) +{ + return (CMU_HFRCODPLLFreq_TypeDef)SystemHFRCODPLLClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCODPLL band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCODPLL frequency band to activate. + ******************************************************************************/ +void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + uint32_t freqCal, sysFreq; +#if defined(EMU_VSCALE_EM01_PRESENT) + uint32_t prevFreq; +#endif + + // Get calibration data from DEVINFO + freqCal = HFRCODPLLDevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + // Make sure DPLL is disabled before configuring + if (DPLL0->EN == DPLL_EN_EN) { + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + } + + // Set max wait-states and PCLK divisor while changing core clock + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + } + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCODPLLFreq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCODPLLFreq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + prevFreq = SystemHFRCODPLLClockGet(); + + if ((uint32_t)freq > prevFreq) { + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)freq, true); + } +#endif + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = freqCal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (freqCal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(freq); + } else { + // revert back to previous value + HFRCO0->CAL = hfrcoCalCurrent; +#if defined(EMU_VSCALE_EM01_PRESENT) + freq = (CMU_HFRCODPLLFreq_TypeDef)prevFreq; +#endif + } + + // If HFRCODPLL is selected as SYSCLK (and HCLK), optimize flash access + // wait-state configuration and PCLK divisor for this frequency. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)freq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((uint32_t)freq <= prevFreq) { + /* When decreasing frequency voltage scale must be done after the change. */ + EMU_VScaleEM01ByClock(0, true); + } +#endif +} + +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCODPLL should be switched to a lower + * frequency clock (if possible) prior to calling this function to avoid + * over-clocking. + * + * @param[in] init + * DPLL setup parameter struct. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hclkDivIncreased = false; + uint32_t hfrcoCalVal, lockStatus = 0, hclkDiv = 0, sysFreq; + uint32_t hfrcoFreqRangeExpected; + uint32_t hfrcoFreqRangeActual; + uint32_t hfrcoCalCurrent; + bool hfrcoClamped = false; + bool restoreDpll; + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0 | CMU_CLKEN0_HFRCO0; +#endif + + restoreDpll = DPLL0->EN & _DPLL_EN_EN_MASK; + + // Make sure DPLL is disabled before configuring + DPLL0->EN_CLR = DPLL_EN_EN; +#if defined(DPLL_EN_DISABLING) + while (DPLL0->EN & DPLL_EN_DISABLING) { + } +#else + while ((DPLL0->STATUS & (DPLL_STATUS_ENS | DPLL_STATUS_RDY)) != 0UL) { + } +#endif + EFM_ASSERT(init->frequency >= hfrcoCalTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCalTable[HFRCOCALTABLE_ENTRIES - 1U].maxFreq); + + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_DPLL_CFG1_N_MASK >> _DPLL_CFG1_N_SHIFT)); + EFM_ASSERT(init->m <= (_DPLL_CFG1_M_MASK >> _DPLL_CFG1_M_SHIFT)); + +#if defined(EMU_VSCALE_EM01_PRESENT) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find correct HFRCODPLL band, and retrieve a HFRCOCAL value. + for (i = 0; i < HFRCOCALTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCalTable[i].minFreq) + && (init->frequency <= hfrcoCalTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCALTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCalVal = hfrcoCalTable[index].value; + + // Check if a calibrated HFRCOCAL.TUNING value is present in device DI page. + if (hfrcoCalTable[index].band != (CMU_HFRCODPLLFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (HFRCODPLLDevinfoGet(hfrcoCalTable[index].band) + & _HFRCO_CAL_TUNING_MASK) + >> _HFRCO_CAL_TUNING_SHIFT; + hfrcoCalVal |= tuning << _HFRCO_CAL_TUNING_SHIFT; + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + // Set max wait-states and PCLK divisor while changing core clock + waitStateMax(); + pclkDivMax(); +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set largest prescaler for radio clock tree + rhclkPrescMax(); +#endif + + // Increase HCLK divider value (if possible) while locking DPLL to + // avoid over-clocking. + hclkDiv = CMU_ClockDivGet(cmuClock_HCLK); + hclkDivIncreased = true; + if (hclkDiv == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } else if (hclkDiv == 2U) { + CMU_ClockDivSet(cmuClock_HCLK, 4U); + } else { + hclkDivIncreased = false; + } + } + + // updates to the CAL register are deferred if FREQBSY is high, so wait + // until HFRCO is not busy to keep going + while (HFRCO0->STATUS & (HFRCO_STATUS_SYNCBUSY | HFRCO_STATUS_FREQBSY)) { + } + + /* + * Some devices have clamped frequency ranges, so instead of the usual [0:16] + * interval, the upper limit is 12. Hardware takes care of clamping the value, + * but a situation might occur where tuning and frequency range are not + * in sync. So try to detect if the value has been clamped, and if it happened + * revert back to the previous value. + */ + hfrcoCalCurrent = HFRCO0->CAL; + HFRCO0->CAL = hfrcoCalVal; + + // values are not shifted, not necessary for comparison + hfrcoFreqRangeExpected = (hfrcoCalVal & _HFRCO_CAL_FREQRANGE_MASK); + hfrcoFreqRangeActual = (HFRCO0->CAL & _HFRCO_CAL_FREQRANGE_MASK); + + EFM_ASSERT(hfrcoFreqRangeExpected == hfrcoFreqRangeActual); + if (hfrcoFreqRangeExpected == hfrcoFreqRangeActual) { + DPLL0->CFG1 = ((uint32_t)init->n << _DPLL_CFG1_N_SHIFT) + | ((uint32_t)init->m << _DPLL_CFG1_M_SHIFT); + + /* For series 2 silicon, macro expansion is used to select clock + * sources since it results in less code size when compared to the legacy + * CMU_ClockSelectSet function. + */ + if (init->refClk == cmuSelect_HFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, HFXO); + } else if (init->refClk == cmuSelect_LFXO) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, LFXO); + } else if (init->refClk == cmuSelect_CLKIN0) { + CMU_CLOCK_SELECT_SET(DPLLREFCLK, CLKIN0); + } + + DPLL0->CFG = ((init->autoRecover ? 1UL : 0UL) << _DPLL_CFG_AUTORECOVER_SHIFT) + | ((init->ditherEn ? 1UL : 0UL) << _DPLL_CFG_DITHEN_SHIFT) + | ((uint32_t)init->edgeSel << _DPLL_CFG_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _DPLL_CFG_MODE_SHIFT); + + // Update CMSIS HFRCODPLL frequency. + SystemHFRCODPLLClockSet(init->frequency); + } else { + hfrcoClamped = true; + HFRCO0->CAL = hfrcoCalCurrent; + } + + /* + * if HFRCO frequency range has been clamped, re-enable DPLL only if it was + * previously enabled + */ + if (!hfrcoClamped || restoreDpll) { + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + + // Lock DPLL + DPLL0->EN_SET = DPLL_EN_EN; + while ((lockStatus = (DPLL0->IF & (DPLL_IF_LOCK + | DPLL_IF_LOCKFAILLOW + | DPLL_IF_LOCKFAILHIGH))) == 0UL) { + } + } + + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + if (hclkDivIncreased) { + // Restore original HCLK divider + CMU_ClockDivSet(cmuClock_HCLK, hclkDiv); + } + + // Call @ref SystemCoreClockGet() to update CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHFRCODPLLClockGet()); + EFM_ASSERT(init->frequency == SystemHFRCODPLLClockGet()); + + // Set optimal wait-states and PCLK divisor + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + pclkDivOptimize(); +#if (defined(CMU_SYSCLKCTRL_RHCLKPRESC) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) + // Set optimal RHCLK prescaler + rhclkPrescOptimize(); +#endif + } + + if (hfrcoClamped) { + return false; + } else if (lockStatus == DPLL_IF_LOCK) { + return true; + } + return false; +} + +#if defined(USBPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the USB PLL control registers. + * + * @note + * The HFXO reference frequency must be updated if crystal value is + * different from default value. + * + * @param[in] pllInit + * USB PLL parameters + ******************************************************************************/ +void CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit) +{ + CMU->CLKEN1_SET = CMU_CLKEN1_USB; + + USBPLL0->LOCK = USBPLL_LOCK_LOCKKEY_UNLOCK; + + // Stop the PLL for configuration purposes + USBPLL0->CTRL_SET = USBPLL_CTRL_DISONDEMAND; + USBPLL0->CTRL_CLR = USBPLL_CTRL_FORCEEN; + + while (USBPLL0->STATUS & USBPLL_STATUS_PLLLOCK) ; + + if (pllInit->hfxoRefFreq == cmuHFXORefFreq_39M0Hz) { + // Set DCO in low frequency mode for 39 MHz crystal. + USBPLL0->DCOCTRL_SET = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } else { + USBPLL0->DCOCTRL_CLR = _USBPLL_DCOCTRL_DCOBIASHALF_MASK; + } + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + USBPLL0->CTRL = (USBPLL0->CTRL & ~(_USBPLL_CTRL_SHUNTREGLPEN_MASK + | _USBPLL_CTRL_DIVR_MASK + | _USBPLL_CTRL_DIVX_MASK + | _USBPLL_CTRL_DIVN_MASK + | _USBPLL_CTRL_DISONDEMAND_MASK + | _USBPLL_CTRL_FORCEEN_MASK)) + | pllInit->hfxoRefFreq + | pllInit->shuntRegEn << _USBPLL_CTRL_SHUNTREGLPEN_SHIFT + | pllInit->disOnDemand << _USBPLL_CTRL_DISONDEMAND_SHIFT + | pllInit->forceEn << _USBPLL_CTRL_FORCEEN_SHIFT; + + while (USBPLL0->STATUS & USBPLL_STATUS_SYNCBUSY) ; + + if (pllInit->forceEn) { + CMU_WaitUSBPLLLock(); + } + + if (pllInit->regLock) { + USBPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(RFFPLL_PRESENT) +/***************************************************************************//** + * @brief + * Initialize the RFFPLL control registers. + * + * @param[in] pllInit + * RFF PLL parameters + ******************************************************************************/ +void CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit) +{ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_RFFPLLSYS); + EFM_ASSERT(pllInit->dividerY >= 8 && pllInit->dividerY <= 31); + EFM_ASSERT(pllInit->dividerX >= 4 && pllInit->dividerX <= 15); + EFM_ASSERT(pllInit->dividerN >= 32 && pllInit->dividerN <= 127); + + CMU->CLKEN1_SET = CMU_CLKEN1_RFFPLL0; + + RFFPLL0->LOCK = RFFPLL_LOCK_LOCKKEY_UNLOCK; + + RFFPLL0->CTRL = (RFFPLL0->CTRL & ~(_RFFPLL_CTRL_DISONDEMAND_MASK | _RFFPLL_CTRL_FORCEEN_MASK)) + | (pllInit->disOnDemand << _RFFPLL_CTRL_DISONDEMAND_SHIFT) + | (pllInit->forceEn << _RFFPLL_CTRL_FORCEEN_SHIFT); + + RFFPLL0->RFFPLLCTRL1 = (RFFPLL0->RFFPLLCTRL1 & ~(_RFFPLL_RFFPLLCTRL1_DIVY_MASK | _RFFPLL_RFFPLLCTRL1_DIVX_MASK | _RFFPLL_RFFPLLCTRL1_DIVN_MASK)) + | (pllInit->dividerY << _RFFPLL_RFFPLLCTRL1_DIVY_SHIFT) + | (pllInit->dividerX << _RFFPLL_RFFPLLCTRL1_DIVX_SHIFT) + | (pllInit->dividerN << _RFFPLL_RFFPLLCTRL1_DIVN_SHIFT); + + // Update CMSIS RFFPLL frequency. + SystemRFFPLLClockSet(pllInit->frequency); + + if (pllInit->forceEn) { + CMU_WaitRFFPLLLock(); + } + + if (pllInit->regLock) { + RFFPLL0->LOCK = ~USBPLL_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +/**************************************************************************//** + * @brief + * Initialize all HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function returns early if HFXO is + * already selected as SYSCLK. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + // Check all initialization structure members which may overflow target + // bitfield. + EFM_ASSERT(hfxoInit->timeoutCbLsb + <= (_HFXO_XTALCFG_TIMEOUTCBLSB_MASK + >> _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteadyFirstLock + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->timeoutSteady + <= (_HFXO_XTALCFG_TIMEOUTSTEADY_MASK + >> _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXoStartup + <= (_HFXO_XTALCFG_CTUNEXOSTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneXiStartup + <= (_HFXO_XTALCFG_CTUNEXISTARTUP_MASK + >> _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->coreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUP_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT)); + EFM_ASSERT(hfxoInit->imCoreBiasStartup + <= (_HFXO_XTALCFG_COREBIASSTARTUPI_MASK + >> _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + EFM_ASSERT(hfxoInit->coreDegenAna + <= (_HFXO_XTALCTRL_COREDGENANA_MASK + >> _HFXO_XTALCTRL_COREDGENANA_SHIFT)); + EFM_ASSERT(hfxoInit->ctuneFixAna + <= (_HFXO_XTALCTRL_CTUNEFIXANA_MASK + >> _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT)); + EFM_ASSERT(hfxoInit->mode + <= (_HFXO_CFG_MODE_MASK >> _HFXO_CFG_MODE_SHIFT)); + + // Return early if HFXO is already selected as SYSCLK. + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFXO) { + return; + } + +#if defined(CMU_CLKEN0_HFXO0) + // Enable HFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable HFXO. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND +#if defined(_HFXO_CTRL_DISONDEMANDBUFOUT_MASK) + | HFXO_CTRL_DISONDEMANDBUFOUT +#endif + ; + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { + } +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + +#if defined(_DEVINFO_HFXOCAL_VTRTRIMANA_MASK) && defined(_HFXO_BUFOUTTRIM_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_VTRTRIMANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_VTRTRIMANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->BUFOUTTRIM, + _HFXO_BUFOUTTRIM_VTRTRIMANA_MASK, + tmp << _HFXO_BUFOUTTRIM_VTRTRIMANA_SHIFT); + } +#endif + +#if defined(_DEVINFO_HFXOCAL_SHUNTBIASANA_MASK) && defined(_HFXO_LOWPWRCTRL_MASK) && defined(_HFXO_SWRST_MASK) + { + uint32_t tmp; + + tmp = BUS_RegMaskedRead(&DEVINFO->HFXOCAL, + _DEVINFO_HFXOCAL_SHUNTBIASANA_MASK); + tmp >>= _DEVINFO_HFXOCAL_SHUNTBIASANA_SHIFT; + BUS_RegMaskedWrite(&HFXO0->LOWPWRCTRL, + _HFXO_LOWPWRCTRL_SHUNTBIASANA_MASK, + tmp << _HFXO_LOWPWRCTRL_SHUNTBIASANA_SHIFT); + } +#endif + + // Configure HFXO as specified in initialization struct, use + // timeoutSteadyFirstLock as TIMEOUTSTEADY value. + HFXO0->XTALCFG = + (uint32_t)((hfxoInit->timeoutCbLsb << _HFXO_XTALCFG_TIMEOUTCBLSB_SHIFT) + | (hfxoInit->timeoutSteadyFirstLock << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT) + | (hfxoInit->ctuneXoStartup << _HFXO_XTALCFG_CTUNEXOSTARTUP_SHIFT) + | (hfxoInit->ctuneXiStartup << _HFXO_XTALCFG_CTUNEXISTARTUP_SHIFT) + | (hfxoInit->coreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT) + | (hfxoInit->imCoreBiasStartup << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)); + + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_SKIPCOREBIASOPT_MASK) + | (hfxoInit->coreDegenAna << _HFXO_XTALCTRL_COREDGENANA_SHIFT) + | (hfxoInit->ctuneFixAna << _HFXO_XTALCTRL_CTUNEFIXANA_SHIFT) + | (hfxoInit->ctuneXoAna << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | (hfxoInit->ctuneXiAna << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) + | (hfxoInit->coreBiasAna << _HFXO_XTALCTRL_COREBIASANA_SHIFT); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + // See [PM-2871] for details. + BUS_RegMaskedWrite((volatile uint32_t*)(HFXO0_BASE + 0x38U), + 0x00000C00U, + 0x00000002U << 10); +#endif + + HFXO0->CFG = (HFXO0->CFG & ~(_HFXO_CFG_SQBUFSCHTRGANA_MASK + | _HFXO_CFG_ENXIDCBIASANA_MASK + | _HFXO_CFG_MODE_MASK)) + | ((hfxoInit->mode == cmuHfxoOscMode_Crystal) + ? 0 : HFXO_CFG_SQBUFSCHTRGANA) + | (hfxoInit->enXiDcBiasAna << _HFXO_CFG_ENXIDCBIASANA_SHIFT) + | (hfxoInit->mode << _HFXO_CFG_MODE_SHIFT); + + if (hfxoInit->mode == cmuHfxoOscMode_Crystal) { + // Lock HFXO with FORCEEN bit set and DISONDEMAND bit cleared. + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->forceXi2GndAna << _HFXO_CTRL_FORCEXI2GNDANA_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | HFXO_CTRL_FORCEEN; + + // Wait for HFXO lock and core bias algorithm to complete. +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS | HFXO_STATUS_FSMLOCK)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS + | HFXO_STATUS_FSMLOCK)) { + } +#else + while ((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY + | HFXO_STATUS_ENS)) + != (HFXO_STATUS_RDY | HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_ENS)) { + } +#endif + // Set DISONDEMAND to be able to enter new values for use on subsequent locks. + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD = HFXO_CMD_MANUALOVERRIDE; +#endif +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Set new TIMEOUTSTEADY value for use on subsequent locks. + HFXO0->XTALCFG = (HFXO0->XTALCFG & ~_HFXO_XTALCFG_TIMEOUTSTEADY_MASK) + | (hfxoInit->timeoutSteady + << _HFXO_XTALCFG_TIMEOUTSTEADY_SHIFT); + + // Skip core bias algorithm on subsequent locks. + HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT; + + if (hfxoInit->disOnDemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + + if (hfxoInit->forceEn == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; +#if defined(HFXO_STATUS_SYNCBUSY) + while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { + } +#endif + } + } else { + // Lock HFXO in EXTERNAL SINE mode. + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + //See [PM-3665] for details. + if (hfxoInit->mode == cmuHfxoOscMode_ExternalSinePkDet) { + HFXO0->XTALCFG = 0; + HFXO0->XTALCTRL = 0; + + const uint32_t PKDETTHSTARTUP_PARAMETER_1 = 2UL; + BUS_RegMaskedWrite((volatile uint32_t *)(HFXO0_BASE + 0x34U), + 0x0000F000U | 0x00000F00U, + (PKDETTHSTARTUP_PARAMETER_1 << 12) | (PKDETTHSTARTUP_PARAMETER_1 << 8)); + } +#endif + + HFXO0->CTRL = (HFXO0->CTRL & ~(_HFXO_CTRL_FORCEXO2GNDANA_MASK + | _HFXO_CTRL_FORCEXI2GNDANA_MASK + | _HFXO_CTRL_DISONDEMAND_MASK +#if defined(HFXO_CTRL_EM23ONDEMAND) + | _HFXO_CTRL_EM23ONDEMAND_MASK +#endif + | _HFXO_CTRL_FORCEEN_MASK)) + | (hfxoInit->forceXo2GndAna << _HFXO_CTRL_FORCEXO2GNDANA_SHIFT) + | (hfxoInit->disOnDemand << _HFXO_CTRL_DISONDEMAND_SHIFT) +#if defined(HFXO_CTRL_EM23ONDEMAND) + | (hfxoInit->em23OnDemand << _HFXO_CTRL_EM23ONDEMAND_SHIFT) +#endif + | (hfxoInit->forceEn << _HFXO_CTRL_FORCEEN_SHIFT); + } + + if (hfxoInit->regLock) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +#if defined(HFXO0_BUFOUT) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) leader control registers. + * Configure the bufout request input GPIO as a clock request signal + * to add the crystal sharing follower chip as a source of clock request. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @param[in] bufoutInit + * Bufout setup parameters. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // Configure Bufout request GPIO. + GPIO_PinModeSet(port, pin, gpioModeInput, 0U); + GPIO->SYXOROUTE[0].BUFOUTREQINASYNCROUTE = pin << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PIN_SHIFT + | port << _GPIO_SYXO_BUFOUTREQINASYNCROUTE_PORT_SHIFT; + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + HFXO0->CTRL_CLR = _HFXO_CTRL_BUFOUTFREEZE_MASK | _HFXO_CTRL_DISONDEMANDBUFOUT_MASK; + + BUS_RegMaskedWrite(&HFXO0->BUFOUTCTRL, + _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_MASK + | _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_MASK, + bufoutInit->minimalStartupDelay << _HFXO_BUFOUTCTRL_MINIMUMSTARTUPDELAY_SHIFT + | bufoutInit->timeoutStartup << _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_SHIFT); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } +} +#endif + +#if defined(_HFXO_CTRL_PRSSTATUSSEL0_MASK) +/**************************************************************************//** + * @brief + * Initialize HFXO Bufout (Crystal sharing) follower control registers. + * Configure the clock request signal to a specified GPIO to automatically + * request the high frequency crystal oscillator sine wave clock. + * This function must be used in conjunction with CMU_HFXOInit() configured + * with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode. + * + * @warning + * If EM2 capabilities are needed, a GPIO that fully retains its + * capabilities while in EM2 must be selected. + * + * @note + * This function can be emulated on XG21/XG22 chips by controlling the clock + * request GPIO to ask the crystal sharing leader clock when needed. + * + * @param[in] prsStatusSelectOutput + * Selected HFXO PRS signal output. + * + * @param[in] prsAsyncCh + * PRS producer asynchronous signal channel. + * + * @param[in] port + * Bufout request GPIO port. + * + * @param[in] pin + * Bufout request GPIO pin. + *****************************************************************************/ +void CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, + unsigned int prsAsyncCh, + GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(prsAsyncCh < PRS_ASYNC_CH_NUM); + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + uint32_t mask = 0U, prsSignal = 0U, value = 0U; + + switch (prsStatusSelectOutput) { + case PRS_Status_select_0: + mask = _HFXO_CTRL_PRSSTATUSSEL0_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL0_ENS << _HFXO_CTRL_PRSSTATUSSEL0_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS; + break; + + case PRS_Status_select_1: +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Power Manager module requires the HFXO PRS Producer output 1 for its usage. + EFM_ASSERT(false); +#else + mask = _HFXO_CTRL_PRSSTATUSSEL1_MASK; + value = _HFXO_CTRL_PRSSTATUSSEL1_ENS << _HFXO_CTRL_PRSSTATUSSEL1_SHIFT; + prsSignal = _PRS_ASYNC_CH_CTRL_SIGSEL_HFXO0LSTATUS1; +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + bool wasLocked = HFXO0->STATUS & HFXO_STATUS_LOCK_LOCKED ? true : false; + + // Unlock register interface. + HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; + + BUS_RegMaskedWrite(&HFXO0->CTRL, mask, value); + + if (wasLocked) { + HFXO0->LOCK = ~HFXO_LOCK_LOCKKEY_UNLOCK; + } + + value = _PRS_ASYNC_CH_CTRL_AUXSEL_DEFAULT << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_FNSEL_A << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT + | _PRS_ASYNC_CH_CTRL_SOURCESEL_HFXO0L << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT + | prsSignal << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + + mask = _PRS_ASYNC_CH_CTRL_AUXSEL_MASK + | _PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK + | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK; + + BUS_RegMaskedWrite(&(PRS->ASYNC_CH[prsAsyncCh].CTRL), mask, value); + + GPIO_PinModeSet(port, pin, gpioModeWiredOrPullDown, 0U); + + (&(GPIO->PRSROUTE[0].ASYNCH0ROUTE))[prsAsyncCh] = pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT + | port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT; + GPIO->PRSROUTE[0].ROUTEEN = 1U << (_GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT + prsAsyncCh); +} +#endif + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning capacitance. + * + * @param[in] ctune + * The desired tuning capacitance value. Each step corresponds to + * approximately 80fF. Min value is 0. Max value is 255. + * + * @return + * SL_STATUS_OK if initialization parameter is valid. + * SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid. + * + * @note + * While the oscillator is running in steady operation state, it may be + * desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA + * fields in the HFXO_XTALCTRL register. When tuning, care should be taken to + * make small changes to the CTUNE registers. Ideally, change the CTUNE + * registers by one LSB at a time and alternate between the XI and XO + * registers. Sufficient wait time for settling, on the order of + * TIMEOUTSTEADY, should pass before new frequency measurement is taken. + *****************************************************************************/ +sl_status_t CMU_HFXOCTuneSet(uint32_t ctune) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Make sure the given CTUNE value is within the allowable range + if (ctune > (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + int32_t ctuneXoana = ctune + CMU_HFXOCTuneDeltaGet(); + if (ctuneXoana < 0) { + ctuneXoana = 0; + } else if (ctuneXoana > (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT)) { + ctuneXoana = (int32_t)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); // Max value + } + + HFXO0->XTALCTRL = ((HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXOANA_MASK | _HFXO_XTALCTRL_CTUNEXIANA_MASK)) + | ((uint32_t)ctuneXoana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) + | ((ctune << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) & _HFXO_XTALCTRL_CTUNEXIANA_MASK)); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning capacitance. + * + * @return + * The HFXO crystal tuning capacitance. + * + * @note + This function only returns the CTUNE XI value. The XO value can be + different and can be found using the delta (difference between XI and XO). + See @ref CMU_HFXOCTuneDeltaGet to retrieve the delta value. + *****************************************************************************/ +uint32_t CMU_HFXOCTuneGet(void) +{ + uint32_t ctune = 0; + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // Keep oscillator running, if it is enabled + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + // Manual override needs COREBIASOPTRDY asserted, + // or the command will be ignored. + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + } + } + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + ctune = ((HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK) + >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT); + + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_DISONDEMAND_MASK, hfxoCtrlBkup); + + // Unforce to return control to hardware request + if (HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) { + BUS_RegMaskedWrite(&HFXO0->CTRL, _HFXO_CTRL_FORCEEN_MASK, hfxoCtrlBkup); + } + + return ctune; +} + +/**************************************************************************//** + * @brief + * Set the HFXO crystal tuning delta. + * + * @param[in] delta + * Chip dependent crystal capacitor bank delta between HFXO XI and XO. + * + * @note + * The delta between XI and XO is applicable for the series 2 EFR32xG2x + * devices only. + *****************************************************************************/ +void CMU_HFXOCTuneDeltaSet(int32_t delta) +{ + ctuneDelta = (int8_t)delta; +} + +/**************************************************************************//** + * @brief + * Get the HFXO crystal tuning delta. + * + * @return + * Chip dependent crystal capacitor bank tuning delta. + *****************************************************************************/ +int32_t CMU_HFXOCTuneDeltaGet(void) +{ + return (int32_t)ctuneDelta; +} + +/**************************************************************************//** + * @brief + * Recalibrate the HFXO's Core Bias Current. + * + * @note + * Care should be taken when using this function as it can cause disturbance + * on the HFXO frequency while the optimization is underway. It's recommended + * to only use this function when HFXO isn't being used. It's also a blocking + * function that can be time consuming. + *****************************************************************************/ +void CMU_HFXOCoreBiasCurrentCalibrate(void) +{ + uint32_t hfxoCtrlBkup = HFXO0->CTRL; + + // These two bits need to be set to allow writing the registers + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY)) { + // Wait for crystal to startup + } + + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + // Wait for crystal to switch modes. + } +#endif + + while ((HFXO0->STATUS & (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) + != (HFXO_STATUS_COREBIASOPTRDY | HFXO_STATUS_RDY | HFXO_STATUS_ENS)) { + // Making sure HFXO is in steady state + } + + // Start core bias optimization + HFXO0->CMD_SET = HFXO_CMD_COREBIASOPT; + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == HFXO_STATUS_COREBIASOPTRDY) { + // Wait for core bias optimization to start + } + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias optimization to finish + } + + // Force COREBIASANA bitfields modification +#if defined(HFXO_CMD_MANUALOVERRIDE) + HFXO0->CMD_SET = HFXO_CMD_MANUALOVERRIDE; +#endif + + while ((HFXO0->STATUS & HFXO_STATUS_COREBIASOPTRDY) == 0) { + // Wait for core bias current value to be written in COREBIASANA bitfields + } + + BUS_RegMaskedWrite(&HFXO0->CTRL, (_HFXO_CTRL_DISONDEMAND_MASK | _HFXO_CTRL_FORCEEN_MASK), hfxoCtrlBkup); +} + +/**************************************************************************//** + * @brief + * Initialize LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note or crystal datasheet. This function disables the LFXO to ensure + * a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + EFM_ASSERT(lfxoInit->timeout + <= (_LFXO_CFG_TIMEOUT_MASK >> _LFXO_CFG_TIMEOUT_SHIFT)); + EFM_ASSERT(lfxoInit->mode + <= (_LFXO_CFG_MODE_MASK >> _LFXO_CFG_MODE_SHIFT)); + EFM_ASSERT(lfxoInit->gain + <= (_LFXO_CAL_GAIN_MASK >> _LFXO_CAL_GAIN_SHIFT)); + EFM_ASSERT(lfxoInit->capTune + <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + + // Max internal capacitance tuning value is 0x4F (20 pF) + uint8_t ctune = (uint8_t) SL_MIN(0x4FU, lfxoInit->capTune); + +#if defined(CMU_CLKEN0_LFXO) + // Enable LFXO module clock. + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + + // Unlock register interface + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + + // Disable LFXO + LFXO->CTRL_SET = LFXO_CTRL_DISONDEMAND; + LFXO->CTRL_CLR = LFXO_CTRL_FORCEEN; + while ((LFXO->STATUS & _LFXO_STATUS_ENS_MASK) != 0U) { + } + + // Configure LFXO as specified + LFXO->CAL = ((uint32_t)lfxoInit->gain << _LFXO_CAL_GAIN_SHIFT) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + LFXO->CFG = (uint32_t)((lfxoInit->timeout << _LFXO_CFG_TIMEOUT_SHIFT) + | (lfxoInit->mode << _LFXO_CFG_MODE_SHIFT) + | (lfxoInit->highAmplitudeEn << _LFXO_CFG_HIGHAMPL_SHIFT) + | (lfxoInit->agcEn << _LFXO_CFG_AGC_SHIFT)); + + LFXO->CTRL = (uint32_t)((lfxoInit->failDetEM4WUEn << _LFXO_CTRL_FAILDETEM4WUEN_SHIFT) + | (lfxoInit->failDetEn << _LFXO_CTRL_FAILDETEN_SHIFT) + | (lfxoInit->disOnDemand << _LFXO_CTRL_DISONDEMAND_SHIFT) + | (lfxoInit->forceEn << _LFXO_CTRL_FORCEEN_SHIFT)); + + if (lfxoInit->regLock) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +#if defined(PLFRCO_PRESENT) +/**************************************************************************//** + * @brief + * Configure the LFRCO precision. + * + * @details + * When enabling high precision mode on the LFRCO the hardware will tune + * the oscillator automatically using the HFXO as a reference. + * + * @note + * Refer to the reference manual and the datasheet for details about + * NOMCAL and NOMCALINV calibration count values. + * + * @param[in] precision + * LFRCO precision, this can be either high or default. + *****************************************************************************/ +void CMU_LFRCOSetPrecision(CMU_Precision_TypeDef precision) +{ + uint32_t ref = 0; + uint32_t nomcal = 0; + uint32_t nomcalinv = 0; + + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + LFRCO->CTRL = LFRCO_CTRL_DISONDEMAND; // Force disable + while ((LFRCO->STATUS & LFRCO_STATUS_ENS) != 0U) { + // Wait for LFRCO to stop + } + + if (precision == cmuPrecisionHigh) { + ref = SystemHFXOClockGet(); + // Use precomputed value for HFXO typical frequencies + if (ref == XTAL_38M4) { + nomcal = LFRCO_NOMCAL_XTAL_38M4; + nomcalinv = LFRCO_NOMCALINV_XTAL_38M4; + } else if (ref == XTAL_39M0) { + nomcal = LFRCO_NOMCAL_XTAL_39M0; + nomcalinv = LFRCO_NOMCALINV_XTAL_39M0; + } else { + // Compute calibration count, based on HFXO frequency + nomcal = (5 * ref) >> 9; + nomcalinv = ((1UL << 31) / 5) << 2; + nomcalinv /= (ref >> 9); + } + + LFRCO->NOMCAL = nomcal; + LFRCO->NOMCALINV = nomcalinv; + + LFRCO->CFG = LFRCO_CFG_HIGHPRECEN; + } else { + LFRCO->CFG = 0; + } + LFRCO->CTRL = _LFRCO_CTRL_RESETVALUE; +} +#endif + +/***************************************************************************//** + * @brief + * Get oscillator frequency tuning setting. + * + * @param[in] osc + * Oscillator to get tuning value for. + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret = 0U; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + ret = (LFRCO->CAL & _LFRCO_CAL_FREQTRIM_MASK) >> _LFRCO_CAL_FREQTRIM_SHIFT; + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + ret = (HFRCO0->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + ret = (HFRCOEM23->CAL & _HFRCO_CAL_TUNING_MASK) >> _HFRCO_CAL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + ret = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK) >> _HFXO_XTALCTRL_COREBIASANA_SHIFT; + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + ret = (LFXO->CAL & _LFXO_CAL_CAPTUNE_MASK) >> _LFXO_CAL_CAPTUNE_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production, and the tuning value is + * automatically loaded after a reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * Oscillator to set tuning value for. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ + bool disondemand = false; + bool lfxo_lock_status = false; + uint8_t ctune = 0; + + switch (osc) { +#if defined(_LFRCO_CAL_FREQTRIM_MASK) + case cmuOsc_LFRCO: +#if defined(CMU_CLKEN0_LFRCO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; +#endif + EFM_ASSERT(val <= (_LFRCO_CAL_FREQTRIM_MASK + >> _LFRCO_CAL_FREQTRIM_SHIFT)); + val &= _LFRCO_CAL_FREQTRIM_MASK >> _LFRCO_CAL_FREQTRIM_SHIFT; + while (LFRCO->SYNCBUSY != 0U) { + } + LFRCO->CAL = (LFRCO->CAL & ~_LFRCO_CAL_FREQTRIM_MASK) + | (val << _LFRCO_CAL_FREQTRIM_SHIFT); + break; +#endif + + case cmuOsc_HFRCODPLL: +#if defined(CMU_CLKEN0_HFRCO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCO0; +#endif + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCO0->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCO0->CAL = (HFRCO0->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; + +#if defined(HFRCOEM23_PRESENT) + case cmuOsc_HFRCOEM23: + EFM_ASSERT(val <= (_HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT)); + val &= _HFRCO_CAL_TUNING_MASK >> _HFRCO_CAL_TUNING_SHIFT; + while ((HFRCOEM23->STATUS & HFRCO_STATUS_SYNCBUSY) != 0UL) { + } + HFRCOEM23->CAL = (HFRCOEM23->CAL & ~_HFRCO_CAL_TUNING_MASK) + | (val << _HFRCO_CAL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_HFXO: +#if defined(CMU_CLKEN0_HFXO0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; +#endif + EFM_ASSERT(val <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT)); + // Make sure HFXO is disable + EFM_ASSERT((HFXO0->STATUS & HFXO_STATUS_ENS) == 0); + + // Set DISONDEMAND if not already set and wait for FSMLOCK to be clear so that + // software can write to register + disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) >> _HFXO_CTRL_DISONDEMAND_SHIFT; + if (disondemand == false) { + HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND; + } +#if defined(HFXO_STATUS_FSMLOCK) + while ((HFXO0->STATUS & HFXO_STATUS_FSMLOCK) != 0) { + } +#endif + // Update Core Bias Ana setting and enable Optimization skip + HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) + | (val << _HFXO_XTALCTRL_COREBIASANA_SHIFT) + | HFXO_XTALCTRL_SKIPCOREBIASOPT; + // Clear back DISONDEMAND if needed + if (disondemand == false) { + HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND; + } + break; + + case cmuOsc_LFXO: +#if defined(CMU_CLKEN0_LFXO) + CMU->CLKEN0_SET = CMU_CLKEN0_LFXO; +#endif + lfxo_lock_status = (LFXO->STATUS & _LFXO_STATUS_LOCK_MASK) >> _LFXO_STATUS_LOCK_SHIFT; + // Unlock register interface if register is locked before + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = LFXO_LOCK_LOCKKEY_UNLOCK; + } + + EFM_ASSERT(val <= (_LFXO_CAL_CAPTUNE_MASK >> _LFXO_CAL_CAPTUNE_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for CALBSY bit to clear before writing the tuning value to CAL register + while (((LFXO->SYNCBUSY & _LFXO_SYNCBUSY_CAL_MASK) >> _LFXO_SYNCBUSY_CAL_SHIFT) != 0U) { + } + LFXO->CAL = (LFXO->CAL & ~_LFXO_CAL_CAPTUNE_MASK) + | ((uint32_t)ctune << _LFXO_CAL_CAPTUNE_SHIFT); + + // Lock register interface again + if (lfxo_lock_status == _LFXO_STATUS_LOCK_LOCKED) { + LFXO->LOCK = ~LFXO_LOCK_LOCKKEY_UNLOCK; + } + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure wait state settings necessary to switch to a given core clock + * frequency at a certain voltage scale level. + * + * @details + * This function will set up the necessary flash wait states. Updating the + * wait state configuration must be done before increasing the clock + * frequency and it must be done after decreasing the clock frequency. + * Updating the wait state configuration must be done before core voltage is + * decreased and it must be done after a core voltage is increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 1, higher number is lower voltage. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + if (vscale > 0) { + flashWaitStateControl(freq, VSCALE_EM01_LOW_POWER); + } else { + flashWaitStateControl(freq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select EM23GRPACLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ + (void)instance; +#if defined(PCNT_PRESENT) + if (external) { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0; + } else { + CMU->PCNT0CLKCTRL = CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK; + } +#else + (void)external; +#endif +} + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get HFRCOEM23 band in use. + * + * @return + * HFRCOEM23 band in use. + ******************************************************************************/ +CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet(void) +{ + return (CMU_HFRCOEM23Freq_TypeDef)SystemHFRCOEM23ClockGet(); +} + +/***************************************************************************//** + * @brief + * Set HFRCOEM23 band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] freq + * HFRCOEM23 frequency band to activate. + ******************************************************************************/ +void CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t freqCal; + + // Get calibration data from DEVINFO + freqCal = HFRCOEM23DevinfoGet(freq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); +#if defined(CMU_CLKEN0_HFRCOEM23) + CMU->CLKEN0_SET = CMU_CLKEN0_HFRCOEM23; +#endif + + // Set divider for 1, 2 and 4MHz bands + freqCal &= ~_HFRCO_CAL_CLKDIV_MASK; + switch (freq) { + case cmuHFRCOEM23Freq_1M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV4; + break; + + case cmuHFRCOEM23Freq_2M0Hz: + freqCal |= HFRCO_CAL_CLKDIV_DIV2; + break; + + default: + break; + } + + // Activate new band selection + HFRCOEM23->CAL = freqCal; +} +#endif // defined(HFRCOEM23_PRESENT) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) +#if defined(PDM_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPBCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + switch (CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(EUART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void euart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + switch (CMU->EUART0CLKCTRL & _CMU_EUART0CLKCTRL_CLKSEL_MASK) { + case CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(freq, sel); + break; + + case CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(freq, sel); + break; + + default: + if (freq != NULL) { + *freq = 0U; + } + if (sel != NULL) { + *sel = cmuSelect_Error; + } + EFM_ASSERT(false); + break; + } +} +#endif + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EUSART0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void eusart0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EUSART0CLKCTRL & _CMU_EUSART0CLKCTRL_CLKSEL_MASK) { +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK: + em01GrpcClkGet(&f, NULL); + s = cmuSelect_EM01GRPCCLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK) + case CMU_EUSART0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_FSRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23) + case CMU_EUSART0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFRCO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_LFXO) + case CMU_EUSART0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; +#endif + +#if defined(CMU_EUSART0CLKCTRL_CLKSEL_DISABLED) + case CMU_EUSART0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_CMU_EM01GRPCCLKCTRL_MASK) +/**************************************************************************//** +* @brief +* Get selected oscillator and frequency for @ref cmuClock_EM01GRPCCLK +* clock tree. +* +* @param[out] freq +* The frequency. +* +* @param[out] sel +* The selected oscillator. +******************************************************************************/ +static void em01GrpcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + + case _CMU_EM01GRPCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPCCLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + case _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_CMU_EM01GRPCCLKCTRL_MASK) +#endif // defined(EUSART_PRESENT) + +#if defined(LCD_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LCDCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lcdClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LCDCLKCTRL & _CMU_LCDCLKCTRL_CLKSEL_MASK) { + case CMU_LCDCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_LCDCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(LCD_PRESENT) + +#if defined(VDAC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC0CLKCTRL & _CMU_VDAC0CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC0CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC0CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if (VDAC_COUNT > 1) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_VDAC1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void vdac1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->VDAC1CLKCTRL & _CMU_VDAC1CLKCTRL_CLKSEL_MASK) { + case CMU_VDAC1CLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_VDAC1CLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif +#endif /* VDAC_PRESENT */ + +#if defined(PCNT_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_PCNT0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void pcnt0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->PCNT0CLKCTRL & _CMU_PCNT0CLKCTRL_CLKSEL_MASK) { + case CMU_PCNT0CLKCTRL_CLKSEL_EM23GRPACLK: + em23GrpaClkGet(&f, NULL); + s = cmuSelect_EM23GRPACLK; + break; + + case CMU_PCNT0CLKCTRL_CLKSEL_PCNTS0: + f = 0U; // external or PRS source so the frequency is undefined. + s = cmuSelect_PCNTEXTCLK; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(LESENSE_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_LESENSEHFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void lesenseHFClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->LESENSEHFCLKCTRL & _CMU_LESENSEHFCLKCTRL_CLKSEL_MASK) { + case CMU_LESENSEHFCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; + + case CMU_LESENSEHFCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) \ + && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +/***************************************************************************//** + * @brief + * Set maximum allowed prescaler for radio clock tree (RHCLK). + ******************************************************************************/ +static void rhclkPrescMax(void) +{ + // Set largest prescaler (DIV2). + CMU->SYSCLKCTRL_SET = CMU_SYSCLKCTRL_RHCLKPRESC; +} + +/***************************************************************************//** + * @brief + * Set radio clock tree prescaler to achieve highest possible frequency + * and still be within spec. + ******************************************************************************/ +static void rhclkPrescOptimize(void) +{ + if (CMU_ClockFreqGet(cmuClock_SYSCLK) <= CMU_MAX_RHCLK_FREQ) { + // Set smallest prescaler (DIV1). + CMU->SYSCLKCTRL_CLR = CMU_SYSCLKCTRL_RHCLKPRESC; + } +} +#endif // ((defined(CMU_SYSCLKCTRL_RHCLKPRESC)) && (_SILICON_LABS_EFR32_RADIO_TYPE != _SILICON_LABS_EFR32_RADIO_NONE)) +#endif // #if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + +#if defined(HFRCOEM23_PRESENT) +/***************************************************************************//** + * @brief + * Get calibrated HFRCOEM23 tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCOEM23 frequency band + ******************************************************************************/ +static uint32_t HFRCOEM23DevinfoGet(CMU_HFRCOEM23Freq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCOEM23Freq_1M0Hz: + case cmuHFRCOEM23Freq_2M0Hz: + case cmuHFRCOEM23Freq_4M0Hz: + ret = DEVINFO->HFRCOEM23CAL[0].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_13M0Hz: + ret = DEVINFO->HFRCOEM23CAL[6].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_16M0Hz: + ret = DEVINFO->HFRCOEM23CAL[7].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_19M0Hz: + ret = DEVINFO->HFRCOEM23CAL[8].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_26M0Hz: + ret = DEVINFO->HFRCOEM23CAL[10].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_32M0Hz: + ret = DEVINFO->HFRCOEM23CAL[11].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_40M0Hz: + ret = DEVINFO->HFRCOEM23CAL[12].HFRCOEM23CAL; + break; + + case cmuHFRCOEM23Freq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} +#endif // defined(HFRCOEM23_PRESENT) + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_TRACECLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void traceClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + +#if defined(_CMU_TRACECLKCTRL_CLKSEL_MASK) + switch (CMU->TRACECLKCTRL & _CMU_TRACECLKCTRL_CLKSEL_MASK) { +#if defined(_CMU_TRACECLKCTRL_CLKSEL_HCLK) + case CMU_TRACECLKCTRL_CLKSEL_HCLK: + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + break; +#endif +#if defined(_CMU_TRACECLKCTRL_CLKSEL_SYSCLK) + case CMU_TRACECLKCTRL_CLKSEL_SYSCLK: + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23) + case CMU_TRACECLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + +#if defined(CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_TRACECLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } +#else + f = SystemSYSCLKGet(); + s = cmuSelect_SYSCLK; +#endif + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_DPLLREFCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void dpllRefClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { + case CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + f = SystemCLKIN0Get(); + s = cmuSelect_CLKIN0; + break; + + case CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM01GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em01GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLL; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXO: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXO; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + case CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLLRT: + f = SystemHFRCODPLLClockGet(); + s = cmuSelect_HFRCODPLLRT; + break; +#endif + +#if defined(CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT) + case CMU_EM01GRPACLKCTRL_CLKSEL_HFXORT: + f = SystemHFXOClockGet(); + s = cmuSelect_HFXORT; + break; +#endif + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM23GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em23GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM23GRPACLKCTRL & _CMU_EM23GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_EM4GRPACLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void em4GrpaClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +__STATIC_INLINE uint32_t getWaitStatesByFrequencyAndVScale(uint32_t freq, int vscale) +{ + uint32_t flashWs = MSC_READCTRL_MODE_WS3; + + if (vscale == 0) { + // VScale 1.1V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V1) + else if (freq > CMU_MAX_FREQ_2WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V1) + else if (freq > CMU_MAX_FREQ_1WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V1) + else if (freq > CMU_MAX_FREQ_0WS_1V1) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } else if (vscale >= 1) { + // VScale 1.0V core frequency ranges for wait-states configurations. + if (0) { + } +#if defined(CMU_MAX_FREQ_2WS_1V0) + else if (freq > CMU_MAX_FREQ_2WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS3; + } +#endif +#if defined(CMU_MAX_FREQ_1WS_1V0) + else if (freq > CMU_MAX_FREQ_1WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS2; + } +#endif +#if defined(CMU_MAX_FREQ_0WS_1V0) + else if (freq > CMU_MAX_FREQ_0WS_1V0) { + flashWs = MSC_READCTRL_MODE_WS1; + } +#endif + else { + flashWs = MSC_READCTRL_MODE_WS0; + } + } + return flashWs; +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency and vscale level. + * + * @note Current implementation sets wait states depending on frequency only. + * This assumes that applications running on Vscale enabled microcontrollers + * never attemtps to set core frequency above 40MHz at VSCALE1 (1.0V). + * Series 2 Config 1 devices does not support vscale. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 1 where 0 is the default. + * @li 0 = 1.1 V (VSCALE2) + * @li 1 = 1.0 V (VSCALE1) + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + (void)vscale; + + uint32_t mode; + bool mscLocked; + +#if defined(CMU_CLKEN1_MSC) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + coreFreq *= CMU_ClockDivGet(cmuClock_CORE); +#endif + + // Make sure the MSC is unlocked + mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + // Get current flash read setting + mode = MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK; + + // Set new mode based on the core clock frequency + mode |= getWaitStatesByFrequencyAndVScale(coreFreq, vscale); + + MSC_ReadCTRLSet(mode); + + // Set sram wait states for config 1 mcu. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // Set new mode based on the core clock frequency + if (coreFreq > CMU_MAX_SRAM_FREQ_0WS) { + SYSCFG_setDmem0RamCtrlRamwsenBit(); + } else { + SYSCFG_clearDmem0RamCtrlRamwsenBit(); + } +#endif + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +/***************************************************************************//** + * @brief + * Get calibrated HFRCODPLL tuning value from Device information (DI) page + * for a given frequency. Calibration value is not available for all frequency + * bands. + * + * @param[in] freq + * HFRCODPLL frequency band + ******************************************************************************/ +static uint32_t HFRCODPLLDevinfoGet(CMU_HFRCODPLLFreq_TypeDef freq) +{ + uint32_t ret = 0U; + + switch (freq) { + // 1, 2 and 4MHz share the same calibration word + case cmuHFRCODPLLFreq_1M0Hz: + case cmuHFRCODPLLFreq_2M0Hz: + case cmuHFRCODPLLFreq_4M0Hz: + ret = DEVINFO->HFRCODPLLCAL[0].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_7M0Hz: + ret = DEVINFO->HFRCODPLLCAL[3].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_13M0Hz: + ret = DEVINFO->HFRCODPLLCAL[6].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_16M0Hz: + ret = DEVINFO->HFRCODPLLCAL[7].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_19M0Hz: + ret = DEVINFO->HFRCODPLLCAL[8].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_26M0Hz: + ret = DEVINFO->HFRCODPLLCAL[10].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_32M0Hz: + ret = DEVINFO->HFRCODPLLCAL[11].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_38M0Hz: + ret = DEVINFO->HFRCODPLLCAL[12].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_48M0Hz: + ret = DEVINFO->HFRCODPLLCAL[13].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_56M0Hz: + ret = DEVINFO->HFRCODPLLCAL[14].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_64M0Hz: + ret = DEVINFO->HFRCODPLLCAL[15].HFRCODPLLCAL; + break; + + case cmuHFRCODPLLFreq_80M0Hz: + ret = DEVINFO->HFRCODPLLCAL[16].HFRCODPLLCAL; + break; + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + case cmuHFRCODPLLFreq_100M0Hz: + ret = DEVINFO->HFRCODPLLCAL[17].HFRCODPLLCAL; + break; +#endif + + case cmuHFRCODPLLFreq_UserDefined: + break; + + default: + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(IADC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_IADCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void iadcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->IADCCLKCTRL & _CMU_IADCCLKCTRL_CLKSEL_MASK) { + case CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK: + em01GrpaClkGet(&f, NULL); + s = cmuSelect_EM01GRPACLK; + break; + +#if defined(HFRCOEM23_PRESENT) + case CMU_IADCCLKCTRL_CLKSEL_HFRCOEM23: + f = SystemHFRCOEM23ClockGet(); + s = cmuSelect_HFRCOEM23; + break; +#endif + + case CMU_IADCCLKCTRL_CLKSEL_FSRCO: + f = SystemFSRCOClockGet(); + s = cmuSelect_FSRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set maximum allowed divisor for @ref cmuClock_PCLK clock tree. + ******************************************************************************/ +static void pclkDivMax(void) +{ + // Set largest divisor for PCLK clock tree. + CMU_ClockDivSet(cmuClock_PCLK, 2U); +} + +/***************************************************************************//** + * @brief + * Set @ref cmuClock_PCLK clock tree divisor to achieve highest possible + * frequency and still be within spec. + ******************************************************************************/ +static void pclkDivOptimize(void) +{ + CMU_ClkDiv_TypeDef div = 2U; + + if (CMU_ClockFreqGet(cmuClock_HCLK) <= CMU_MAX_PCLK_FREQ) { + div = 1U; + } + CMU_ClockDivSet(cmuClock_PCLK, div); +} + +#if defined(RTCC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_RTCCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void rtccClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { + case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_RTCCCLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +#if defined(SYSRTC_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSRTCCLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysrtcClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->SYSRTC0CLKCTRL & _CMU_SYSRTC0CLKCTRL_CLKSEL_MASK) { + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/***************************************************************************//** + * @brief + * Set wait-states to values valid for maximum allowable core clock frequency. + ******************************************************************************/ +static void waitStateMax(void) +{ + flashWaitStateControl(SystemMaxCoreClockGet(), 0); +} + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG0CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog0ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG0CLKCTRL & _CMU_WDOG0CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG0CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_WDOG1CLK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void wdog1ClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->WDOG1CLKCTRL & _CMU_WDOG1CLKCTRL_CLKSEL_MASK) { + case CMU_WDOG1CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_ULFRCO: + f = SystemULFRCOClockGet(); + s = cmuSelect_ULFRCO; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_HCLKDIV1024: + f = SystemHCLKGet() / 1024U; + s = cmuSelect_HCLKDIV1024; + break; + + case CMU_WDOG1CLKCTRL_CLKSEL_DISABLED: + s = cmuSelect_Disabled; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif // defined(_SILICON_LABS_32B_SERIES_2) && WDOG_COUNT > 1 + +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_SYSTICK + * clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void sysTickClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + if (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) { + f = SystemHCLKGet(); + s = cmuSelect_HCLK; + } else { + em23GrpaClkGet(&f, &s); + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} + +#if defined(USB_PRESENT) +/***************************************************************************//** + * @brief + * Get selected oscillator and frequency for @ref cmuClock_USB clock tree. + * + * @param[out] freq + * The frequency. + * + * @param[out] sel + * The selected oscillator. + ******************************************************************************/ +static void usbClkGet(uint32_t *freq, CMU_Select_TypeDef *sel) +{ + uint32_t f = 0U; + CMU_Select_TypeDef s; + + switch (CMU->USB0CLKCTRL & _CMU_USB0CLKCTRL_CLKSEL_MASK) { + case CMU_USB0CLKCTRL_CLKSEL_USBPLL0: + f = PLL0_USB_OUTPUT_FREQ; + s = cmuSelect_USBPLL0; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFXO: + f = SystemLFXOClockGet(); + s = cmuSelect_LFXO; + break; + + case CMU_USB0CLKCTRL_CLKSEL_LFRCO: + f = SystemLFRCOClockGet(); + s = cmuSelect_LFRCO; + break; + + default: + s = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + if (freq != NULL) { + *freq = f; + } + if (sel != NULL) { + *sel = s; + } +} +#endif + +/** @endcond */ + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_SILICON_LABS_32B_SERIES_0) +/** The maximum allowed core frequency when using 0 wait-states on flash access. */ +#define CMU_MAX_FREQ_0WS 16000000 +/** The maximum allowed core frequency when using 1 wait-states on flash access */ +#define CMU_MAX_FREQ_1WS 32000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) +// EFR32xG1x and EFM32xG1x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 84) +// EFR32xG12x and EFM32xG12x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V1 21330000 +#define CMU_MAX_FREQ_1WS_1V1 32000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) +// EFR32xG13x and EFM32xG13x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 95) +// EFR32xG14x and EFM32xG14x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 40000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 100) +// EFM32GG11x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 103) +// EFM32TG11x +#define CMU_MAX_FREQ_0WS_1V2 25000000 +#define CMU_MAX_FREQ_1WS_1V2 48000000 +#define CMU_MAX_FREQ_0WS_1V0 10000000 +#define CMU_MAX_FREQ_1WS_1V0 21000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#elif (_SILICON_LABS_GECKO_INTERNAL_SDID == 106) +// EFM32GG12x +#define CMU_MAX_FREQ_0WS_1V2 18000000 +#define CMU_MAX_FREQ_1WS_1V2 36000000 +#define CMU_MAX_FREQ_2WS_1V2 54000000 +#define CMU_MAX_FREQ_3WS_1V2 72000000 +#define CMU_MAX_FREQ_0WS_1V0 7000000 +#define CMU_MAX_FREQ_1WS_1V0 14000000 +#define CMU_MAX_FREQ_2WS_1V0 20000000 + +#else +#error "Max Flash wait-state frequencies are not defined for this platform." +#endif + +/** The maximum frequency for the HFLE interface. */ +#if defined(CMU_CTRL_HFLE) +/** The maximum HFLE frequency for series 0 EFM32 and EZR32 Wonder Gecko. */ +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_WONDER_FAMILY) \ + || defined(_EZR32_WONDER_FAMILY)) +#define CMU_MAX_FREQ_HFLE 24000000UL +/** The maximum HFLE frequency for other series 0 parts with maximum core clock + higher than 32 MHz. */ +#elif defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +#define CMU_MAX_FREQ_HFLE maxFreqHfle() +#endif +#elif defined(CMU_CTRL_WSHFLE) +/** The maximum HFLE frequency for series 1 parts. */ +#define CMU_MAX_FREQ_HFLE 32000000UL +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_TUNING_MODE_AUTO (_CMU_HFXOCTRL_PEAKDETMODE_AUTOCMD) +#define HFXO_TUNING_MODE_CMD (_CMU_HFXOCTRL_PEAKDETMODE_CMD) +#endif + +#if defined(CMU_HFXOCTRL_MODE_EXTCLK) +/** HFXO external clock mode is renamed from EXTCLK to DIGEXTCLK. */ +#define CMU_HFXOCTRL_MODE_DIGEXTCLK CMU_HFXOCTRL_MODE_EXTCLK +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) +#define VSCALE_DEFAULT ((int)EMU_VScaleGet()) +#else +#define VSCALE_DEFAULT VSCALE_EM01_HIGH_PERFORMANCE +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz; +#endif +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) +#define HFXO_INVALID_TRIM (~_CMU_HFXOTRIMSTATUS_MASK) +#endif + +#if defined(CMU_OSCENCMD_DPLLEN) +/** A table of HFRCOCTRL values and their associated minimum/maximum frequencies and + an optional band enumerator. */ +static const struct hfrcoCtrlTableElement{ + uint32_t minFreq; + uint32_t maxFreq; + uint32_t value; + CMU_HFRCOFreq_TypeDef band; +} hfrcoCtrlTable[] = +{ + // minFreq maxFreq HFRCOCTRL value band + { 860000UL, 1050000UL, 0xBC601F00UL, cmuHFRCOFreq_1M0Hz }, + { 1050000UL, 1280000UL, 0xBC611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1280000UL, 1480000UL, 0xBCA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1480000UL, 1800000UL, 0xAD231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 1800000UL, 2110000UL, 0xBA601F00UL, cmuHFRCOFreq_2M0Hz }, + { 2110000UL, 2560000UL, 0xBA611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2560000UL, 2970000UL, 0xBAA21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 2970000UL, 3600000UL, 0xAB231F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 3600000UL, 4220000UL, 0xB8601F00UL, cmuHFRCOFreq_4M0Hz }, + { 4220000UL, 5120000UL, 0xB8611F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5120000UL, 5930000UL, 0xB8A21F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 5930000UL, 7520000UL, 0xA9231F00UL, cmuHFRCOFreq_7M0Hz }, + { 7520000UL, 9520000UL, 0x99241F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 9520000UL, 11800000UL, 0x99251F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 11800000UL, 14400000UL, 0x99261F00UL, cmuHFRCOFreq_13M0Hz }, + { 14400000UL, 17200000UL, 0x99271F00UL, cmuHFRCOFreq_16M0Hz }, + { 17200000UL, 19700000UL, 0x99481F00UL, cmuHFRCOFreq_19M0Hz }, + { 19700000UL, 23800000UL, 0x99491F35UL, (CMU_HFRCOFreq_TypeDef)0 }, + { 23800000UL, 28700000UL, 0x994A1F00UL, cmuHFRCOFreq_26M0Hz }, + { 28700000UL, 34800000UL, 0x996B1F00UL, cmuHFRCOFreq_32M0Hz }, +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + { 34800000UL, 40000000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 51600000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz }, + { 51600000UL, 60500000UL, 0x998E1F00UL, cmuHFRCOFreq_56M0Hz }, + { 60500000UL, 72000000UL, 0xA98F1F00UL, cmuHFRCOFreq_64M0Hz } +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) + { 34800000UL, 42800000UL, 0x996C1F00UL, cmuHFRCOFreq_38M0Hz }, + { 42800000UL, 48000000UL, 0x996D1F00UL, cmuHFRCOFreq_48M0Hz } +#else + #error "HFRCOCTRL values not set for this platform." +#endif +}; + +#define HFRCOCTRLTABLE_ENTRIES (sizeof(hfrcoCtrlTable) \ + / sizeof(struct hfrcoCtrlTableElement)) +#endif // CMU_OSCENCMD_DPLLEN + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(_EMU_STATUS_VSCALE_MASK) +/* Devices with Voltage Scaling needs extra handling of wait states. */ +static const struct flashWsTableElement{ + uint32_t maxFreq; + uint8_t vscale; + uint8_t ws; +} flashWsTable[] = +{ +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 100 || _SILICON_LABS_GECKO_INTERNAL_SDID == 106) + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at max frequency 18 MHz and 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at max frequency 36 MHz and 1.2V */ + { CMU_MAX_FREQ_2WS_1V2, 0, 2 }, /* 2 wait states at max frequency 54 MHz and 1.2V */ + { CMU_MAX_FREQ_3WS_1V2, 0, 3 }, /* 3 wait states at max frequency 72 MHz and 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at max frequency 7 MHz and 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at max frequency 14 MHz and 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at max frequency 21 MHz and 1.0V */ +#else + { CMU_MAX_FREQ_0WS_1V2, 0, 0 }, /* 0 wait states at 1.2V */ + { CMU_MAX_FREQ_1WS_1V2, 0, 1 }, /* 1 wait states at 1.2V */ + { CMU_MAX_FREQ_0WS_1V0, 2, 0 }, /* 0 wait states at 1.0V */ + { CMU_MAX_FREQ_1WS_1V0, 2, 1 }, /* 1 wait states at 1.0V */ + { CMU_MAX_FREQ_2WS_1V0, 2, 2 }, /* 2 wait states at 1.0V */ +#endif +}; + +#define FLASH_WS_TABLE_ENTRIES (sizeof(flashWsTable) / sizeof(flashWsTable[0])) +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) \ + || defined(_CMU_USHFRCOTUNE_MASK) +#ifndef EFM32_USHFRCO_STARTUP_FREQ +#define EFM32_USHFRCO_STARTUP_FREQ (48000000UL) +#endif + +static uint32_t ushfrcoFreq = EFM32_USHFRCO_STARTUP_FREQ; +#endif + +/******************************************************************************* + ************************** LOCAL PROTOTYPES ******************************* + ******************************************************************************/ +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq); +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq); +#endif + +static void hfperClkSafePrescaler(void); +static void hfperClkOptimizedPrescaler(void); + +static uint16_t lfxo_precision = 0xFFFF; +static uint16_t hfxo_precision = 0xFFFF; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_GIANT_FAMILY) \ + || defined(_EZR32_LEOPARD_FAMILY)) +/***************************************************************************//** + * @brief + * Return maximum allowed frequency for low energy peripherals. + ******************************************************************************/ +static uint32_t maxFreqHfle(void) +{ + uint16_t majorMinorRev; + + switch (SYSTEM_GetFamily()) { + case systemPartFamilyEfm32Leopard: + case systemPartFamilyEzr32Leopard: + /* CHIP MAJOR bit [5:0] */ + majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) << 8); + /* CHIP MINOR bit [7:4] */ + majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + + if (majorMinorRev >= 0x0204) { + return 24000000; + } else { + return 32000000; + } + + case systemPartFamilyEfm32Giant: + return 32000000; + + default: + /* Invalid device family. */ + EFM_ASSERT(false); + return 0; + } +} +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Unified definitions for the HFLE wait-state and prescaler fields. */ +#if defined(CMU_CTRL_HFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_HFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_HFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFCORECLKDIV +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT +#elif defined(CMU_CTRL_WSHFLE) +#define _GENERIC_HFLE_WS_MASK _CMU_CTRL_WSHFLE_MASK +#define _GENERIC_HFLE_WS_SHIFT _CMU_CTRL_WSHFLE_SHIFT +#define GENERIC_HFLE_PRESC_REG CMU->HFPRESC +#define _GENERIC_HFLE_PRESC_MASK _CMU_HFPRESC_HFCLKLEPRESC_MASK +#define _GENERIC_HFLE_PRESC_SHIFT _CMU_HFPRESC_HFCLKLEPRESC_SHIFT +#endif +/** @endcond */ + +/***************************************************************************//** + * @brief + * Set HFLE wait-states and HFCLKLE prescaler according to wanted HF clock. + * + * @param[in] hfFreq + * The HF clock frequency to use. + * This is: + * CORE clock on Series0 devices. + * HF clock on on Series1 devices. + ******************************************************************************/ +static void setHfLeConfig(uint32_t hfFreq) +{ + unsigned int hfleWs; + uint32_t hflePresc; + + /* Check for 1 bit fields. @ref BUS_RegBitWrite() below are going to fail if the + fields are changed to more than 1 bit. */ + EFM_ASSERT((_GENERIC_HFLE_WS_MASK >> _GENERIC_HFLE_WS_SHIFT) == 0x1U); + + /* - Enable HFLE wait-state to allow access to LE peripherals when HFBUSCLK is + above maxLeFreq. + - Set HFLE prescaler. Allowed HFLE clock frequency is maxLeFreq. */ + + hfleWs = 1; + if (hfFreq <= CMU_MAX_FREQ_HFLE) { + hfleWs = 0; + hflePresc = 0; + } else if (hfFreq <= (2UL * CMU_MAX_FREQ_HFLE)) { + hflePresc = 1; + } else { + hflePresc = 2; + } + BUS_RegBitWrite(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT, hfleWs); + GENERIC_HFLE_PRESC_REG = (GENERIC_HFLE_PRESC_REG & ~_GENERIC_HFLE_PRESC_MASK) + | (hflePresc << _GENERIC_HFLE_PRESC_SHIFT); +} + +#if defined(_CMU_CTRL_HFLE_MASK) +/***************************************************************************//** + * @brief + * Get HFLE wait-state configuration. + * + * @return + * The current wait-state configuration. + ******************************************************************************/ +static uint32_t getHfLeConfig(void) +{ + uint32_t ws = BUS_RegBitRead(&CMU->CTRL, _GENERIC_HFLE_WS_SHIFT); + return ws; +} +#endif +#endif + +/***************************************************************************//** + * @brief + * Get the AUX clock frequency. Used by MSC flash programming and LESENSE, + * by default also as a debug clock. + * + * @return + * AUX Frequency in Hz. + ******************************************************************************/ +static uint32_t auxClkGet(void) +{ + uint32_t ret; + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) + ret = (uint32_t)auxHfrcoFreq; + +#elif defined(_CMU_AUXHFRCOCTRL_BAND_MASK) + /* All series 0 families except EFM32G */ + switch (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) { + case CMU_AUXHFRCOCTRL_BAND_1MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 1200000; + } else { + ret = 1000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_7MHZ: + if ( SYSTEM_GetProdRev() >= 19 ) { + ret = 6600000; + } else { + ret = 7000000; + } + break; + + case CMU_AUXHFRCOCTRL_BAND_11MHZ: + ret = 11000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_14MHZ: + ret = 14000000; + break; + + case CMU_AUXHFRCOCTRL_BAND_21MHZ: + ret = 21000000; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case CMU_AUXHFRCOCTRL_BAND_28MHZ: + ret = 28000000; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + +#else + /* Gecko has a fixed 14 MHz AUXHFRCO clock. */ + ret = 14000000; + +#endif + + return ret; +} + +#if defined (_CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK) \ + || defined (_CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK) +/***************************************************************************//** + * @brief + * Get the HFSRCCLK frequency. + * + * @return + * HFSRCCLK Frequency in Hz. + ******************************************************************************/ +static uint32_t hfSrcClkGet(void) +{ + uint32_t ret; + + ret = SystemHFClockGet(); + return ret * (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT)); +} +#endif + +/***************************************************************************//** + * @brief + * Get the Debug Trace clock frequency. + * + * @return + * Debug Trace frequency in Hz. + ******************************************************************************/ +static uint32_t dbgClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get selected clock source */ + clk = CMU_ClockSelectGet(cmuClock_DBG); + + switch (clk) { + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) +/***************************************************************************//** + * @brief + * Get the ADC n asynchronous clock frequency. + * + * @return + * ADC n asynchronous frequency in Hz. + ******************************************************************************/ +static uint32_t adcAsyncClkGet(uint32_t adc) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (adc) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_ADC0ASYNC); + break; + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case 1: + clk = CMU_ClockSelectGet(cmuClock_ADC1ASYNC); + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_Disabled: + ret = 0; + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFSRCCLK: + ret = hfSrcClkGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_SDIOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the SDIO reference clock frequency. + * + * @return + * SDIO reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t sdioRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_SDIOREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_QSPICTRL_MASK) +/***************************************************************************//** + * @brief + * Get the QSPI n reference clock frequency. + * + * @return + * QSPI n reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t qspiRefClkGet(uint32_t qspi) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + switch (qspi) { + case 0: + clk = CMU_ClockSelectGet(cmuClock_QSPI0REF); + break; + + default: + EFM_ASSERT(false); + return 0; + } + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_AUXHFRCO: + ret = auxClkGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(_CMU_PDMCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the PDM reference clock frequency. + * + * @return + * PDM reference clock frequency in Hz. + ******************************************************************************/ +static uint32_t pdmRefClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_PDMREF); + + switch (clk) { + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +#if defined(USBR_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USB rate clock frequency. + * + * @return + * USB rate clock frequency in Hz. + ******************************************************************************/ +static uint32_t usbRateClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + clk = CMU_ClockSelectGet(cmuClock_USBR); + + switch (clk) { + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; + + case cmuSelect_HFXO: + ret = SystemHFXOClockGet(); + break; + + case cmuSelect_HFXOX2: + ret = 2u * SystemHFXOClockGet(); + break; + + case cmuSelect_HFRCO: + ret = SystemHfrcoFreq; + break; + + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Configure flash access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure flash wait-states. + * + * @param[in] vscale + * Voltage Scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void flashWaitStateControl(uint32_t coreFreq, int vscale) +{ + uint32_t mode; +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */ +#endif + (void) vscale; /* vscale parameter is only used on some devices. */ + + /* Get mode and SCBTP enable. */ + mode = MSC_ReadCTRLGet() & _MSC_READCTRL_MODE_MASK; + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + /* Devices with MODE and SCBTP in the same register field. */ + switch (mode) { + case MSC_READCTRL_MODE_WS0: + case MSC_READCTRL_MODE_WS1: +#if defined(MSC_READCTRL_MODE_WS2) + case MSC_READCTRL_MODE_WS2: +#endif + scbtpEn = false; + break; + + default: /* WSxSCBTP */ + scbtpEn = true; + break; + } + + /* Set mode based on the core clock frequency and SCBTP enable. */ + if (false) { + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq > CMU_MAX_FREQ_1WS) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2); + } +#endif + else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS)) { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS1SCBTP : MSC_READCTRL_MODE_WS1); + } else { + mode = (scbtpEn ? MSC_READCTRL_MODE_WS0SCBTP : MSC_READCTRL_MODE_WS0); + } +#else /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ + + if (coreFreq <= CMU_MAX_FREQ_0WS) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS) { + mode = 1; + } +#endif /* defined(MSC_READCTRL_MODE_WS0SCBTP) */ +// End defined(_SILICON_LABS_32B_SERIES_0) + +#elif defined(_SILICON_LABS_32B_SERIES_1) +#if defined(_EMU_STATUS_VSCALE_MASK) + + /* These devices have specific requirements on the supported flash wait state + * depending on the frequency and voltage scale level. */ + uint32_t i; + for (i = 0; i < FLASH_WS_TABLE_ENTRIES; i++) { + if ((flashWsTable[i].vscale == (uint8_t)vscale) + && (coreFreq <= flashWsTable[i].maxFreq)) { + break; // Found a matching entry. + } + } + + if (i == FLASH_WS_TABLE_ENTRIES) { + mode = 3; // Worst case flash wait state for unsupported cases. + EFM_ASSERT(false); + } else { + mode = flashWsTable[i].ws; + } + mode = mode << _MSC_READCTRL_MODE_SHIFT; + +#else + /* Devices where MODE and SCBTP are in separate fields and where the device + * either does not support voltage scale or where the voltage scale does + * not impact the flash wait state configuration. */ + if (coreFreq <= CMU_MAX_FREQ_0WS_1V2) { + mode = 0; + } else if (coreFreq <= CMU_MAX_FREQ_1WS_1V2) { + mode = 1; + } +#if defined(MSC_READCTRL_MODE_WS2) + else if (coreFreq <= CMU_MAX_FREQ_2WS) { + mode = 2; + } +#endif +#if defined(MSC_READCTRL_MODE_WS3) + else if (coreFreq <= CMU_MAX_FREQ_3WS) { + mode = 3; + } +#endif + mode = mode << _MSC_READCTRL_MODE_SHIFT; +#endif +// End defined(_SILICON_LABS_32B_SERIES_1) + +#else +#error "Undefined 32B SERIES!" +#endif + + mode = (MSC_ReadCTRLGet() & ~_MSC_READCTRL_MODE_MASK) | mode; + MSC_ReadCTRLSet(mode); +} + +/***************************************************************************//** + * @brief + * Configure flash access wait states to the most conservative setting for + * this target. Retain SCBTP (Suppressed Conditional Branch Target Prefetch) + * setting. + ******************************************************************************/ +static void flashWaitStateMax(void) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(SystemMaxCoreClockGet(), 0); + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) +/***************************************************************************//** + * @brief + * Configure RAM access wait states to support the given core clock + * frequency. + * + * @param[in] coreFreq + * The core clock frequency to configure RAM wait-states. + * + * @param[in] vscale + * A voltage scale level. Supported levels are 0 and 2 where 0 is the default. + ******************************************************************************/ +static void setRamWaitState(uint32_t coreFreq, int vscale) +{ + uint32_t limit = 38000000; + if (vscale == 2) { + limit = 16000000; + } + + if (coreFreq > limit) { + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } else { + BUS_RegMaskedClear(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); + } +} +#endif + +#if defined(_MSC_CTRL_WAITMODE_MASK) +/***************************************************************************//** + * @brief + * Configure the wait state for peripheral accesses over the bus to support + * the given bus clock frequency. + * + * @param[in] busFreq + * A peripheral bus clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * ******************************************************************************/ +static void setBusWaitState(uint32_t busFreq, int vscale) +{ + if ((busFreq > 50000000) && (vscale == 0)) { + BUS_RegMaskedSet(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } else { + BUS_RegMaskedClear(&MSC->CTRL, MSC_CTRL_WAITMODE_WS1); + } +} +#endif + +#if defined(PLFRCO_PRESENT) +static bool deviceHasPlfrco(void) +{ + SYSTEM_ChipRevision_TypeDef rev; + + if (_SILICON_LABS_GECKO_INTERNAL_SDID == 89) { + // check the xG13 rev and check if it's >= Rev A3 + SYSTEM_ChipRevisionGet(&rev); + return (rev.major > 1) || (rev.minor >= 3); + } else { + return false; + } +} +#endif + +/***************************************************************************//** + * @brief + * Configure various wait states to switch to a certain frequency + * and a certain voltage scale. + * + * @details + * This function will set up the necessary flash, bus, and RAM wait states. + * Updating the wait state configuration must be done before + * increasing the clock frequency and it must be done after decreasing the + * clock frequency. Updating the wait state configuration must be done before + * core voltage is decreased and it must be done after a core voltage is + * increased. + * + * @param[in] freq + * The core clock frequency to configure wait-states. + * + * @param[in] vscale + * The voltage scale to configure wait-states. Expected values are + * 0 or 2, higher number is lower voltage. + * + * @li 0 = 1.2 V (VSCALE2) + * @li 2 = 1.0 V (VSCALE0) + * + ******************************************************************************/ +void CMU_UpdateWaitStates(uint32_t freq, int vscale) +{ + /* Make sure the MSC is unlocked */ + bool mscLocked = MSC_LockGetLocked(); + MSC_LockSetUnlocked(); + + flashWaitStateControl(freq, vscale); +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + setRamWaitState(freq, vscale); +#endif +#if defined(_MSC_CTRL_WAITMODE_MASK) + setBusWaitState(freq, vscale); +#endif + + if (mscLocked) { + MSC_LockSetLocked(); + } +} + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK) +/***************************************************************************//** + * @brief + * Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH. + ******************************************************************************/ +static uint32_t getRegIshUpperVal(uint32_t steadyStateRegIsh) +{ + uint32_t regIshUpper; + const uint32_t upperMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK + >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + /* Add 3 as specified in the register description for CMU_HFXOSTEADYSTATECTRL_REGISHUPPER. */ + regIshUpper = SL_MIN(steadyStateRegIsh + 3UL, upperMax); + regIshUpper <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT; + return regIshUpper; +} +#endif + +#if defined(_CMU_HFXOCTRL_MASK) +/***************************************************************************//** + * @brief + * Get the HFXO tuning mode. + * + * @return + * The current HFXO tuning mode from the HFXOCTRL register. + ******************************************************************************/ +__STATIC_INLINE uint32_t getHfxoTuningMode(void) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT; +#else + return (CMU->HFXOCTRL & _CMU_HFXOCTRL_PEAKDETMODE_MASK) + >> _CMU_HFXOCTRL_PEAKDETMODE_SHIFT; +#endif +} + +/***************************************************************************//** + * @brief + * Set the HFXO tuning mode. + * + * @param[in] mode + * The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or + * HFXO_TUNING_MODE_CMD. + ******************************************************************************/ +__STATIC_INLINE void setHfxoTuningMode(uint32_t mode) +{ +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_SHIFT); +#else + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETMODE_MASK) + | (mode << _CMU_HFXOCTRL_PEAKDETMODE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Get the LFnCLK frequency based on the current configuration. + * + * @param[in] lfClkBranch + * Selected LF branch. + * + * @return + * The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is + * returned. + ******************************************************************************/ +static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch) +{ + uint32_t sel; + uint32_t ret = 0; + + switch (lfClkBranch) { + case cmuClock_LFA: + case cmuClock_LFB: +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#endif +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: +#endif + break; + + default: + EFM_ASSERT(false); + break; + } + + sel = (uint32_t)CMU_ClockSelectGet(lfClkBranch); + + /* Get clock select field */ + switch (lfClkBranch) { + case cmuClock_LFA: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT; +#elif defined(_CMU_LFACLKSEL_MASK) + sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + + case cmuClock_LFB: +#if defined(_CMU_LFCLKSEL_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT; +#elif defined(_CMU_LFBCLKSEL_MASK) + sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case cmuClock_LFC: +#if defined(_CMU_LFCLKSEL_LFC_MASK) + sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT; +#elif defined(_CMU_LFCCLKSEL_LFC_MASK) + sel = (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) >> _CMU_LFCCLKSEL_LFC_SHIFT; +#else + EFM_ASSERT(false); +#endif + break; +#endif + +#if defined(_CMU_LFECLKSEL_MASK) + case cmuClock_LFE: + sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Get the clock frequency. */ +#if defined(_CMU_LFCLKSEL_MASK) + switch (sel) { + case _CMU_LFCLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFCLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + +#if defined(_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: +#if defined(CMU_MAX_FREQ_HFLE) + /* HFLE bit is or'ed by hardware with HFCORECLKLEDIV to reduce the + * frequency of CMU_HFCORECLKLEDIV2. */ + ret = SystemCoreClockGet() / (1U << (getHfLeConfig() + 1)); +#else + ret = SystemCoreClockGet() / 2U; +#endif + break; +#endif + + case _CMU_LFCLKSEL_LFA_DISABLED: + ret = 0; +#if defined(CMU_LFCLKSEL_LFAE) + /* Check LF Extended bit setting for LFA or LFB ULFRCO clock. */ + if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB)) { + if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA + ? _CMU_LFCLKSEL_LFAE_SHIFT + : _CMU_LFCLKSEL_LFBE_SHIFT)) { + ret = SystemULFRCOClockGet(); + } + } +#endif + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif /* _CMU_LFCLKSEL_MASK */ + +#if defined(_CMU_LFACLKSEL_MASK) + switch (sel) { + case _CMU_LFACLKSEL_LFA_LFRCO: + ret = SystemLFRCOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_LFXO: + ret = SystemLFXOClockGet(); + break; + + case _CMU_LFACLKSEL_LFA_ULFRCO: + ret = SystemULFRCOClockGet(); + break; + +#if defined(PLFRCO_PRESENT) + case _CMU_LFACLKSEL_LFA_PLFRCO: + ret = SystemLFRCOClockGet(); + break; +#endif + +#if defined(_CMU_LFBCLKSEL_LFB_HFCLKLE) + case _CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = SystemHFClockGet() + / SL_Log2ToDiv(((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT) + 1UL); + break; +#endif + + case _CMU_LFACLKSEL_LFA_DISABLED: + ret = 0; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } +#endif + + return ret; +} + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to low-frequency domain to complete. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void syncReg(uint32_t mask) +{ + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if ((CMU->FREEZE & CMU_FREEZE_REGFREEZE) != 0UL) { + return; + } + + /* Wait for any pending previous write operation to complete */ + /* in low-frequency domain. */ + while ((CMU->SYNCBUSY & mask) != 0UL) { + } +} + +#if defined(USBC_CLOCK_PRESENT) +/***************************************************************************//** + * @brief + * Get the USBC frequency. + * + * @return + * USBC frequency in Hz. + ******************************************************************************/ +static uint32_t usbCClkGet(void) +{ + uint32_t ret; + CMU_Select_TypeDef clk; + + /* Get the selected clock source. */ + clk = CMU_ClockSelectGet(cmuClock_USBC); + + switch (clk) { + case cmuSelect_LFXO: + ret = SystemLFXOClockGet(); + break; + case cmuSelect_LFRCO: + ret = SystemLFRCOClockGet(); + break; +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuSelect_USHFRCO: + ret = ushfrcoFreq; + break; +#endif + case cmuSelect_HFCLK: + ret = SystemHFClockGet(); + break; + default: + /* Clock is not enabled */ + ret = 0; + break; + } + return ret; +} +#endif + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to safe values. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkSafePrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + // Assuming a maximum HFCLK of 72MHz, set prescalers to DIV4. + CMU_ClockPrescSet(cmuClock_HFPER, 3U); + CMU_ClockPrescSet(cmuClock_HFPERB, 3U); + CMU_ClockPrescSet(cmuClock_HFPERC, 3U); +#endif +} + +/***************************************************************************//** + * @brief + * Set HFPER clock tree prescalers to give highest possible clock node + * frequency while still beeing within spec. + * + * @note + * This function applies to EFM32GG11B. There are 3 HFPER clock trees with + * these frequency limits: + * HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + * HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. + * HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. + ******************************************************************************/ +static void hfperClkOptimizedPrescaler(void) +{ +#if defined(_CMU_HFPERPRESC_MASK) && defined(_CMU_HFPERPRESCB_MASK) \ + && defined(_CMU_HFPERPRESCC_MASK) + uint32_t hfClkFreq, divisor; + + hfClkFreq = SystemHFClockGet(); + + if ( EMU_VScaleGet() == emuVScaleEM01_LowPower) { + divisor = (hfClkFreq + 20000000U - 1U) / 20000000U; // ceil(x) + if (divisor > 0U) { + divisor--; // Convert to prescaler + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + } else { + divisor = (hfClkFreq + 50000000U - 1U) / 50000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPER, divisor); + CMU_ClockPrescSet(cmuClock_HFPERC, divisor); + + divisor = (hfClkFreq + 72000000U - 1U) / 72000000U; + if (divisor > 0U) { + divisor--; + } + CMU_ClockPrescSet(cmuClock_HFPERB, divisor); + } +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get the AUXHFRCO band in use. + * + * @return + * AUXHFRCO band in use. + ******************************************************************************/ +CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL + & _CMU_AUXHFRCOCTRL_BAND_MASK) + >> _CMU_AUXHFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the AUXHFRCO band and the tuning value based on the value in the + * calibration table made during production. + * + * @param[in] band + * AUXHFRCO band to activate. + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band) +{ + uint32_t tuning; + + /* Read a tuning value from the calibration table. */ + switch (band) { + case cmuAUXHFRCOBand_1MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT; + break; + + case cmuAUXHFRCOBand_7MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT; + break; + + case cmuAUXHFRCOBand_11MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT; + break; + + case cmuAUXHFRCOBand_14MHz: + tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) + >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT; + break; + + case cmuAUXHFRCOBand_21MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_AUXHFRCOCTRL_BAND_28MHZ) + case cmuAUXHFRCOBand_28MHz: + tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) + >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Set band/tuning. */ + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL + & ~(_CMU_AUXHFRCOCTRL_BAND_MASK + | _CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +} +#endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the AUXHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * AUXHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuAUXHFRCOFreq_1M0Hz: + case cmuAUXHFRCOFreq_2M0Hz: + case cmuAUXHFRCOFreq_4M0Hz: + return DEVINFO->AUXHFRCOCAL0; + + case cmuAUXHFRCOFreq_7M0Hz: + return DEVINFO->AUXHFRCOCAL3; + + case cmuAUXHFRCOFreq_13M0Hz: + return DEVINFO->AUXHFRCOCAL6; + + case cmuAUXHFRCOFreq_16M0Hz: + return DEVINFO->AUXHFRCOCAL7; + + case cmuAUXHFRCOFreq_19M0Hz: + return DEVINFO->AUXHFRCOCAL8; + + case cmuAUXHFRCOFreq_26M0Hz: + return DEVINFO->AUXHFRCOCAL10; + + case cmuAUXHFRCOFreq_32M0Hz: + return DEVINFO->AUXHFRCOCAL11; + + case cmuAUXHFRCOFreq_38M0Hz: + return DEVINFO->AUXHFRCOCAL12; + +#if defined(_DEVINFO_AUXHFRCOCAL13_MASK) + case cmuAUXHFRCOFreq_48M0Hz: + return DEVINFO->AUXHFRCOCAL13; +#endif +#if defined(_DEVINFO_AUXHFRCOCAL14_MASK) + case cmuAUXHFRCOFreq_50M0Hz: + return DEVINFO->AUXHFRCOCAL14; +#endif + + default: /* cmuAUXHFRCOFreq_UserDefined */ + return 0; + } +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Get the current AUXHFRCO frequency. + * + * @return + * AUXHFRCO frequency. + ******************************************************************************/ +CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet(void) +{ + return auxHfrcoFreq; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_AUXHFRCOCTRL_FREQRANGE_MASK) +/***************************************************************************//** + * @brief + * Set AUXHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * AUXHFRCO frequency to set + ******************************************************************************/ +void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO index and set global auxHfrcoFreq. */ + freqCal = CMU_AUXHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + auxHfrcoFreq = setFreq; + + /* Wait for any previous sync to complete, then set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } + + /* Set a divider in AUXHFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuAUXHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuAUXHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuAUXHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK) + | CMU_AUXHFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + CMU->AUXHFRCOCTRL = freqCal; +} +#endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */ + +/***************************************************************************//** + * @brief + * Calibrate the clock. + * + * @details + * Run a calibration for HFCLK against a selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * This function will not return until the calibration measurement is completed. + * + * @param[in] HFCycles + * The number of HFCLK cycles to run the calibration. Increasing this number + * increases precision but the calibration will take more time. + * + * @param[in] reference + * The reference clock used to compare HFCLK. + * + * @return + * The number of ticks the reference clock after HFCycles ticks on the HF + * clock. + ******************************************************************************/ +uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference) +{ + EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set the reference clock source. */ + switch (reference) { + case cmuOsc_LFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + CMU->CALCTRL = CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return 0; + } + + /* Set the top value. */ + CMU->CALCNT = HFCycles; + + /* Start the calibration. */ + CMU->CMD = CMU_CMD_CALSTART; + +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes. */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + + return CMU->CALCNT; +} + +#if defined(_CMU_CALCTRL_UPSEL_MASK) && defined(_CMU_CALCTRL_DOWNSEL_MASK) +/***************************************************************************//** + * @brief + * Configure the clock calibration. + * + * @details + * Configure a calibration for a selectable clock source against another + * selectable reference clock. + * See the reference manual, CMU chapter, for more details. + * + * @note + * After configuration, a call to @ref CMU_CalibrateStart() is required and + * the resulting calibration value can be read out with the + * @ref CMU_CalibrateCountGet() function call. + * + * @param[in] downCycles + * The number of downSel clock cycles to run the calibration. Increasing this + * number increases precision but the calibration will take more time. + * + * @param[in] downSel + * The clock, which will be counted down downCycles. + * + * @param[in] upSel + * The reference clock; the number of cycles generated by this clock will + * be counted and added up and the result can be given with the + * @ref CMU_CalibrateCountGet() function call. + ******************************************************************************/ +void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, + CMU_Osc_TypeDef upSel) +{ + /* Keep configuration settings untouched. */ + uint32_t calCtrl = CMU->CALCTRL + & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK); + + /* 20 bits of precision to calibration count register. */ + EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT)); + + /* Set down counting clock source - down counter. */ + switch (downSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_DOWNSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + /* Set the top value to be counted down by the downSel clock. */ + CMU->CALCNT = downCycles; + + /* Set the reference clock source - up counter. */ + switch (upSel) { + case cmuOsc_LFXO: + calCtrl |= CMU_CALCTRL_UPSEL_LFXO; + break; + + case cmuOsc_LFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_LFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_PLFRCO; + break; +#endif + + case cmuOsc_HFXO: + calCtrl |= CMU_CALCTRL_UPSEL_HFXO; + break; + + case cmuOsc_HFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_HFRCO; + break; + + case cmuOsc_AUXHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO; + break; + +#if defined (_CMU_USHFRCOCTRL_MASK) + case cmuOsc_USHFRCO: + calCtrl |= CMU_CALCTRL_UPSEL_USHFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + + CMU->CALCTRL = calCtrl; +} +#endif + +/***************************************************************************//** + * @brief + * Get the calibration count register. + * @note + * If continuous calibration mode is active, calibration busy will almost + * always be off and only the value needs to be read. In a normal case, + * this function call is triggered by the CALRDY + * interrupt flag. + * @return + * The calibration count, the number of UPSEL clocks + * in the period of DOWNSEL oscillator clock cycles configured by a previous + * write operation to CMU->CALCNT. + ******************************************************************************/ +uint32_t CMU_CalibrateCountGet(void) +{ + /* Wait until calibration completes, UNLESS continuous calibration mode is */ + /* active. */ +#if defined(CMU_CALCTRL_CONT) + if (BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT) == 0UL) { +#if defined(CMU_STATUS_CALRDY) + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT) == 0UL) { + } +#else + /* Wait until calibration completes */ + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + } +#else + while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT) != 0UL) { + } +#endif + return CMU->CALCNT; +} + +/***************************************************************************//** + * @brief + * Get the clock divisor/prescaler. + * + * @param[in] clock + * A clock point to get the divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference manual. + * + * @return + * The current clock point divisor/prescaler. 1 is returned + * if @p clock specifies a clock point without a divisor/prescaler. + ******************************************************************************/ +CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + return 1UL + (uint32_t)CMU_ClockPrescGet(clock); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t divReg; + CMU_ClkDiv_TypeDef ret; + + /* Get divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) + >> _CMU_CTRL_HFCLKDIV_SHIFT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV + & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + + case CMU_HFCORECLKDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV + & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + >> _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + ret = SL_Log2ToDiv(ret + 1U); + break; +#endif + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT); + ret = SL_Log2ToDiv(ret); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16)); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); + ret = SL_Log2ToDiv(ret); + break; +#endif + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + break; + + default: + ret = cmuClkDiv_1; + EFM_ASSERT(false); + break; + } + + return ret; +#endif +} + +/***************************************************************************//** + * @brief + * Set the clock divisor/prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * Clock point to set divisor/prescaler for. Notice that not all clock points + * have a divisor/prescaler. See the CMU overview in the reference + * manual. + * + * @param[in] div + * The clock divisor to use (<= cmuClkDiv_512). + ******************************************************************************/ +void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1U)); + +#elif defined(_SILICON_LABS_32B_SERIES_0) + uint32_t freq; + uint32_t divReg; + + /* Get the divisor reg ID. */ + divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK; + + switch (divReg) { +#if defined(_CMU_CTRL_HFCLKDIV_MASK) + case CMU_HFCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_8)); + + /* Configure worst case wait states for flash access before setting divisor. */ + flashWaitStateMax(); + + /* Set the divider. */ + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) + | ((div - 1) << _CMU_CTRL_HFCLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize flash access wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; +#endif + + case CMU_HFPERCLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + | (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT); + break; + +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + case CMU_HFCORECLKLEDIV_REG: + /* + This divisor is usually set when changing HF clock to keep HFLE clock + within safe bounds. This code path ignore these constraints. + */ + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div) - 1U; + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT); + break; +#endif + + case CMU_HFCORECLKDIV_REG: + EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512)); + + /* Configure worst case wait states for flash access before setting the divisor. */ + flashWaitStateMax(); + +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet() / div); +#endif + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV + & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) + | (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT); + + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + + /* Optimize wait state setting for the current core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(freq); +#endif + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { + case cmuClock_RTC: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (div << _CMU_LFAPRESC0_RTC_SHIFT); + break; + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(div <= cmuClkDiv_32768); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(LCD_PRESENT) + case cmuClock_LCDpre: + EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128)); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | ((div - CMU_DivToLog2(cmuClkDiv_16)) + << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif /* defined(LCD_PRESENT) */ + +#if defined(LESENSE_PRESENT) + case cmuClock_LESENSE: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (div << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif /* defined(LESENSE_PRESENT) */ + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(div <= cmuClkDiv_8); + + /* LF register about to be modified requires sync. busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + /* Convert to the correct scale. */ + div = CMU_DivToLog2(div); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + default: + EFM_ASSERT(false); + break; + } +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable a clock. + * + * @details + * In general, module clocking is disabled after a reset. If a module + * clock is disabled, the registers of that module are not accessible and + * reading from such registers may return undefined values. Writing to + * registers of clock-disabled modules has no effect. + * Avoid accessing module registers of a module with a disabled clock. + * + * @note + * If enabling/disabling an LF clock, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * The clock to enable/disable. Notice that not all defined clock + * points have separate enable/disable control. See the CMU overview + * in the reference manual. + * + * @param[in] enable + * @li true - enable specified clock. + * @li false - disable specified clock. + ******************************************************************************/ +void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable) +{ + volatile uint32_t *reg; + uint32_t bit; + uint32_t sync = 0; + + /* Identify enable register */ + switch (((unsigned)clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK) { +#if defined(_CMU_CTRL_HFPERCLKEN_MASK) + case CMU_CTRL_EN_REG: + reg = &CMU->CTRL; + break; +#endif + +#if defined(_CMU_HFCORECLKEN0_MASK) + case CMU_HFCORECLKEN0_EN_REG: + reg = &CMU->HFCORECLKEN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + break; +#endif + +#if defined(_CMU_HFBUSCLKEN0_MASK) + case CMU_HFBUSCLKEN0_EN_REG: + reg = &CMU->HFBUSCLKEN0; + break; +#endif + +#if defined(_CMU_HFPERCLKDIV_MASK) + case CMU_HFPERCLKDIV_EN_REG: + reg = &CMU->HFPERCLKDIV; + break; +#endif + + case CMU_HFPERCLKEN0_EN_REG: + reg = &CMU->HFPERCLKEN0; + break; + +#if defined(_CMU_HFPERCLKEN1_MASK) + case CMU_HFPERCLKEN1_EN_REG: + reg = &CMU->HFPERCLKEN1; + break; +#endif + + case CMU_LFACLKEN0_EN_REG: + reg = &CMU->LFACLKEN0; + sync = CMU_SYNCBUSY_LFACLKEN0; + break; + + case CMU_LFBCLKEN0_EN_REG: + reg = &CMU->LFBCLKEN0; + sync = CMU_SYNCBUSY_LFBCLKEN0; + break; + +#if defined(_CMU_LFCCLKEN0_MASK) + case CMU_LFCCLKEN0_EN_REG: + reg = &CMU->LFCCLKEN0; + sync = CMU_SYNCBUSY_LFCCLKEN0; + break; +#endif + +#if defined(_CMU_LFECLKEN0_MASK) + case CMU_LFECLKEN0_EN_REG: + reg = &CMU->LFECLKEN0; + sync = CMU_SYNCBUSY_LFECLKEN0; + break; +#endif + +#if defined(_CMU_SDIOCTRL_MASK) + case CMU_SDIOREF_EN_REG: + reg = &CMU->SDIOCTRL; + enable = !enable; + break; +#endif + +#if defined(_CMU_QSPICTRL_MASK) + case CMU_QSPI0REF_EN_REG: + reg = &CMU->QSPICTRL; + enable = !enable; + break; +#endif +#if defined(_CMU_USBCTRL_MASK) + case CMU_USBRCLK_EN_REG: + reg = &CMU->USBCTRL; + break; +#endif +#if defined(_CMU_PDMCTRL_MASK) + case CMU_PDMREF_EN_REG: + reg = &CMU->PDMCTRL; + break; +#endif + + case CMU_PCNT_EN_REG: + reg = &CMU->PCNTCTRL; + break; + + default: /* Cannot enable/disable a clock point. */ + EFM_ASSERT(false); + return; + } + + /* Get the bit position used to enable/disable. */ + bit = ((unsigned)clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK; + + /* LF synchronization required. */ + if (sync > 0UL) { + syncReg(sync); + } + + /* Set/clear bit as requested. */ + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the clock frequency for a clock point. + * + * @param[in] clock + * A clock point to fetch the frequency for. + * + * @return + * The current frequency in Hz. + ******************************************************************************/ +uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock) +{ + uint32_t ret; + + switch ((unsigned)clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS)) { + case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + break; + + case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPER divider. */ +#if defined(_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) + >> _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT; +#endif +#if defined(_CMU_HFPERPRESC_PRESC_MASK) + ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT); +#endif + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case (CMU_HFPERB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERB prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case (CMU_HFPERC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + /* Calculate frequency after HFPERC prescaler. */ + ret /= 1U + ((CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#if defined(CRYPTO_PRESENT) \ + || defined(LDMA_PRESENT) \ + || defined(GPCRC_PRESENT) \ + || defined(PRS_PRESENT) \ + || defined(GPIO_PRESENT) + case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); +#if defined(_CMU_HFBUSPRESC_MASK) + ret /= 1U + ((CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT); +#endif + break; +#endif + + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT); + break; + + case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = SystemHFClockGet(); + ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(AES_PRESENT) \ + || defined(DMA_PRESENT) \ + || defined(EBI_PRESENT) \ + || defined(USB_PRESENT) + case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + { + ret = SystemCoreClockGet(); + } break; +#endif +#endif + + case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + break; + +#if defined(_CMU_LFACLKEN0_RTC_MASK) + case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + break; +#endif + +#if defined(_CMU_LFECLKEN0_RTCC_MASK) + case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + ret >>= (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER0_MASK) + case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LETIMER1_MASK) + case (CMU_LETIMER1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFACLKEN0_LCD_MASK) + case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT) + + CMU_DivToLog2(cmuClkDiv_16); +#else + ret /= SL_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT); +#endif + break; + +#if defined(_CMU_LCDCTRL_MASK) + case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) + >> _CMU_LCDCTRL_FDIV_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_LFACLKEN0_LESENSE_MASK) + case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFA); + ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + break; +#endif + + case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + break; + +#if defined(_CMU_LFBCLKEN0_LEUART0_MASK) + case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_LEUART1_MASK) + case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); +#if defined(_SILICON_LABS_32B_SERIES_0) + ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; +#else + ret /= SL_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFBCLKEN0_CSEN_MASK) + case (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFB); + ret /= SL_Log2ToDiv(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT) + 4UL); + break; +#endif + +#if defined(CMU_LFCCLKEN0_USB) + case (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFC); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = lfClkGet(cmuClock_LFE); + break; +#endif + + case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = dbgClkGet(); + break; + + case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = auxClkGet(); + break; + +#if defined(USBC_CLOCK_PRESENT) + case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbCClkGet(); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(0); +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case (CMU_ADC1ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = adcAsyncClkGet(1); +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + ret /= 1U + ((CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case (CMU_SDIOREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = sdioRefClkGet(); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case (CMU_QSPI0REF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = qspiRefClkGet(0); + break; +#endif + +#if defined(USBR_CLOCK_PRESENT) + case (CMU_USBR_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = usbRateClkGet(); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case (CMU_PDMREF_CLK_BRANCH << CMU_CLK_BRANCH_POS): + ret = pdmRefClkGet(); + break; +#endif + + case (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS): +#if defined(_CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) + ret = SystemCoreClockGet() / CMU_ClockDivGet(clock); +#elif defined(_CMU_HFPRESC_HFCLKLEPRESC_MASK) + ret = SystemHFClockGet() / CMU_ClockDivGet(clock); +#else + ret = SystemCoreClockGet() / 2; +#endif + break; + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Get the clock prescaler. + * + * @param[in] clock + * A clock point to get the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @return + * The prescaler value of the current clock point. 0 is returned + * if @p clock specifies a clock point without a prescaler. + ******************************************************************************/ +uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock) +{ + uint32_t prescReg; + uint32_t ret; + + /* Get the prescaler register ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT; + break; + + case CMU_HFEXPPRESC_REG: + ret = (CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK) + >> _CMU_HFEXPPRESC_PRESC_SHIFT; + break; + + case CMU_HFCLKLEPRESC_REG: + ret = (CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK) + >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT; + ret = SL_Log2ToDiv(ret + 1U) - 1U; + break; + + case CMU_HFPERPRESC_REG: + ret = (CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK) + >> _CMU_HFPERPRESC_PRESC_SHIFT; + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + ret = (CMU->HFPERPRESCB & _CMU_HFPERPRESCB_PRESC_MASK) + >> _CMU_HFPERPRESCB_PRESC_SHIFT; + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + ret = (CMU->HFPERPRESCC & _CMU_HFPERPRESCC_PRESC_MASK) + >> _CMU_HFPERPRESCC_PRESC_SHIFT; + break; +#endif + + case CMU_HFCOREPRESC_REG: + ret = (CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK) + >> _CMU_HFCOREPRESC_PRESC_SHIFT; + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) + >> _CMU_LFAPRESC0_LETIMER0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) + >> _CMU_LFAPRESC0_LESENSE_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER1_MASK) + >> _CMU_LFAPRESC0_LETIMER1_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCD: + case cmuClock_LCDpre: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) + >> _CMU_LFAPRESC0_LCD_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFAPRESC0_RTC_MASK) + case cmuClock_RTC: + ret = (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) + >> _CMU_LFAPRESC0_RTC_SHIFT; + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) + >> _CMU_LFBPRESC0_LEUART0_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) + >> _CMU_LFBPRESC0_LEUART1_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret) - 1U; + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + ret = (CMU->LFBPRESC0 & _CMU_LFBPRESC0_CSEN_MASK) + >> _CMU_LFBPRESC0_CSEN_SHIFT; + /* Convert the exponent to a prescaler value. */ + ret = SL_Log2ToDiv(ret + 4U) - 1U; + break; +#endif + + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: + ret = (CMU->LFEPRESC0 & _CMU_LFEPRESC0_RTCC_MASK) + >> _CMU_LFEPRESC0_RTCC_SHIFT; + break; + + default: + ret = 0U; + EFM_ASSERT(false); + break; +#endif + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC0CLKDIV_SHIFT; + break; +#endif +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + ret = (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKDIV_MASK) + >> _CMU_ADCCTRL_ADC1CLKDIV_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + ret = (CMU->HFBUSPRESC & _CMU_HFBUSPRESC_MASK) + >> _CMU_HFBUSPRESC_PRESC_SHIFT; + break; +#endif + default: + ret = 0U; + EFM_ASSERT(false); + break; + } + + return ret; +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Set the clock prescaler. + * + * @note + * If setting an LF clock prescaler, synchronization into the low-frequency + * domain is required. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. See @ref CMU_FreezeEnable() for + * a suggestion on how to reduce the stalling time in some use cases. + * + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock point to set the prescaler for. Notice that not all clock points + * have a prescaler. See the CMU overview in the reference manual. + * + * @param[in] presc + * The clock prescaler. The prescaler value is linked to the clock divider by: + * divider = 'presc' + 1. + ******************************************************************************/ +void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc) +{ + uint32_t freq; + uint32_t prescReg; + + /* Get the divisor reg ID. */ + prescReg = ((unsigned)clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK; + + switch (prescReg) { + case CMU_HFPRESC_REG: + EFM_ASSERT(presc < 32U); + + /* Configure worst case wait-states for flash and HFLE, set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); + hfperClkSafePrescaler(); + + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK) + | (presc << _CMU_HFPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global + variable). */ + freq = SystemCoreClockGet(); + /* Optimize flash and HFLE wait states and set optimized HFPER clock-tree + prescalers. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + setHfLeConfig(SystemHFClockGet()); + hfperClkOptimizedPrescaler(); + break; + + case CMU_HFEXPPRESC_REG: + EFM_ASSERT(presc < 32U); + + CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK) + | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT); + break; + + case CMU_HFCLKLEPRESC_REG: + presc = CMU_DivToLog2(presc); + CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK) + | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT); + break; + + case CMU_HFPERPRESC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK) + | (presc << _CMU_HFPERPRESC_PRESC_SHIFT); + break; + +#if defined(_CMU_HFPERPRESCB_MASK) + case CMU_HFPERPRESCB_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCB = (CMU->HFPERPRESCB & ~_CMU_HFPERPRESCB_PRESC_MASK) + | (presc << _CMU_HFPERPRESCB_PRESC_SHIFT); + break; +#endif + +#if defined(_CMU_HFPERPRESCC_MASK) + case CMU_HFPERPRESCC_REG: + EFM_ASSERT(presc < 512U); + CMU->HFPERPRESCC = (CMU->HFPERPRESCC & ~_CMU_HFPERPRESCC_PRESC_MASK) + | (presc << _CMU_HFPERPRESCC_PRESC_SHIFT); + break; +#endif + + case CMU_HFCOREPRESC_REG: + EFM_ASSERT(presc < 512U); + + /* Configure worst case wait-states for flash. */ + flashWaitStateMax(); + + CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK) + | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT); + + /* Update the CMSIS core clock variable (this function updates the global variable). + Optimize flash and HFLE wait states. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + break; + + case CMU_LFAPRESC0_REG: + switch (clock) { +#if defined(RTC_PRESENT) + case cmuClock_RTC: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) + | (presc << _CMU_LFAPRESC0_RTC_SHIFT); + break; +#endif + +#if defined(RTCC_PRESENT) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_MASK) +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); +#else + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK) + | (presc << _CMU_LFAPRESC0_RTCC_SHIFT); +#endif + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER0_MASK) + case cmuClock_LETIMER0: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LETIMER1_MASK) + case cmuClock_LETIMER1: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER1_MASK) + | (presc << _CMU_LFAPRESC0_LETIMER1_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LESENSE_MASK) + case cmuClock_LESENSE: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) + | (presc << _CMU_LFAPRESC0_LESENSE_SHIFT); + break; +#endif + +#if defined(_CMU_LFAPRESC0_LCD_MASK) + case cmuClock_LCDpre: + case cmuClock_LCD: + EFM_ASSERT(presc <= 32768U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFAPRESC0); + + CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) + | (presc << _CMU_LFAPRESC0_LCD_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFBPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFBPRESC0_LEUART0_MASK) + case cmuClock_LEUART0: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) + | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_LEUART1_MASK) + case cmuClock_LEUART1: + EFM_ASSERT(presc <= 8U); + + /* Convert the prescaler value to a DIV exponent scale. */ + presc = CMU_PrescToLog2(presc); + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) + | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT); + break; +#endif + +#if defined(_CMU_LFBPRESC0_CSEN_MASK) + case cmuClock_CSEN_LF: + EFM_ASSERT((presc <= 127U) && (presc >= 15U)); + + /* Convert the prescaler value to a DIV exponent scale. + * DIV16 is the lowest supported prescaler. */ + presc = CMU_PrescToLog2(presc) - 4U; + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFBPRESC0); + + CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_CSEN_MASK) + | (presc << _CMU_LFBPRESC0_CSEN_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + + case CMU_LFEPRESC0_REG: + switch (clock) { +#if defined(_CMU_LFEPRESC0_RTCC_MASK) + case cmuClock_RTCC: +#if defined(_CMU_LFEPRESC0_RTCC_DIV4) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV4); +#elif defined(_CMU_LFEPRESC0_RTCC_DIV2) + EFM_ASSERT(presc <= _CMU_LFEPRESC0_RTCC_DIV2); +#else + EFM_ASSERT(presc <= 0U); +#endif + + /* LF register about to be modified requires sync. Busy check. */ + syncReg(CMU_SYNCBUSY_LFEPRESC0); + + CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK) + | (presc << _CMU_LFEPRESC0_RTCC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } + break; + +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) \ + || defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case CMU_ADCASYNCDIV_REG: + switch (clock) { +#if defined(_CMU_ADCCTRL_ADC0CLKDIV_MASK) + case cmuClock_ADC0ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC0CLKDIV_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKDIV_MASK) + case cmuClock_ADC1ASYNC: + EFM_ASSERT(presc <= 3); + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKDIV_MASK) + | (presc << _CMU_ADCCTRL_ADC1CLKDIV_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + break; +#endif + +#if defined(_CMU_HFBUSPRESC_MASK) + case CMU_HFBUSPRESC_REG: + EFM_ASSERT(presc <= _CMU_HFBUSPRESC_MASK >> _CMU_HFBUSPRESC_PRESC_SHIFT); + CMU->HFBUSPRESC = (CMU->HFBUSPRESC & ~_CMU_HFBUSPRESC_MASK) + | (presc << _CMU_HFBUSPRESC_PRESC_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} +#endif + +/***************************************************************************//** + * @brief + * Get the currently selected reference clock used for a clock branch. + * + * @param[in] clock + * Clock branch to fetch selected ref. clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB @if _CMU_LFCLKSEL_LFAE_ULFRCO + * @li #cmuClock_LFC + * @endif @if _SILICON_LABS_32B_SERIES_1 + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG @if DOXYDOC_USB_PRESENT + * @li #cmuClock_USBC + * @endif + * + * @return + * The reference clock used for clocking the selected branch, #cmuSelect_Error if + * invalid @p clock provided. + ******************************************************************************/ +CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef ret = cmuSelect_Disabled; + uint32_t selReg; + + selReg = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selReg) { + case CMU_HFCLKSEL_REG: +#if defined(_CMU_HFCLKSTATUS_MASK) + switch (CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) { + case CMU_HFCLKSTATUS_SELECTED_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_HFCLKSTATUS_SELECTED_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_HFCLKSTATUS_SELECTED_HFXO: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case CMU_HFCLKSTATUS_SELECTED_HFRCODIV2: + ret = cmuSelect_HFRCODIV2; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case CMU_HFCLKSTATUS_SELECTED_CLKIN0: + ret = cmuSelect_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case CMU_HFCLKSTATUS_SELECTED_USHFRCO: + ret = cmuSelect_USHFRCO; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#else + switch (CMU->STATUS + & (CMU_STATUS_HFRCOSEL + | CMU_STATUS_HFXOSEL + | CMU_STATUS_LFRCOSEL +#if defined(CMU_STATUS_USHFRCODIV2SEL) + | CMU_STATUS_USHFRCODIV2SEL +#endif + | CMU_STATUS_LFXOSEL)) { + case CMU_STATUS_LFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_LFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + case CMU_STATUS_HFXOSEL: + ret = cmuSelect_HFXO; + break; + +#if defined(CMU_STATUS_USHFRCODIV2SEL) + case CMU_STATUS_USHFRCODIV2SEL: + ret = cmuSelect_USHFRCODIV2; + break; +#endif + + default: + ret = cmuSelect_HFRCO; + break; + } +#endif + break; + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFACLKSEL_MASK) + case CMU_LFACLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) { + case CMU_LFCLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFAE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFACLKSEL_MASK) + switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) { + case CMU_LFACLKSEL_LFA_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFACLKSEL_LFA_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFACLKSEL_LFA_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFACLKSEL_LFA_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFACLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_MASK) || defined(_CMU_LFBCLKSEL_MASK) + case CMU_LFBCLKSEL_REG: +#if defined(_CMU_LFCLKSEL_MASK) + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) { + case CMU_LFCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + +#if defined(CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2) + case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2: + ret = cmuSelect_HFCLKLE; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFB_HFCLKLE) + case CMU_LFCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; +#endif + + default: +#if defined(CMU_LFCLKSEL_LFBE) + if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK) { + ret = cmuSelect_ULFRCO; + break; + } +#else + ret = cmuSelect_Disabled; +#endif + break; + } + +#elif defined(_CMU_LFBCLKSEL_MASK) + switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) { + case CMU_LFBCLKSEL_LFB_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFBCLKSEL_LFB_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFBCLKSEL_LFB_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + case CMU_LFBCLKSEL_LFB_HFCLKLE: + ret = cmuSelect_HFCLKLE; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFBCLKSEL_LFB_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } +#endif + break; +#endif /* _CMU_LFCLKSEL_MASK || _CMU_LFBCLKSEL_MASK */ + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) { + case CMU_LFCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_LFECLKSEL_LFE_MASK) + case CMU_LFECLKSEL_REG: + switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) { + case CMU_LFECLKSEL_LFE_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFECLKSEL_LFE_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFECLKSEL_LFE_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case CMU_LFECLKSEL_LFE_PLFRCO: + ret = cmuSelect_PLFRCO; + break; +#endif + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFECLKSEL_REG */ + +#if defined(_CMU_LFCCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (CMU->LFCCLKSEL & _CMU_LFCCLKSEL_LFC_MASK) { + case CMU_LFCCLKSEL_LFC_LFRCO: + ret = cmuSelect_LFRCO; + break; + + case CMU_LFCCLKSEL_LFC_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_LFCCLKSEL_LFC_ULFRCO: + ret = cmuSelect_ULFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif /* CMU_LFCCLKSEL_REG */ + + case CMU_DBGCLKSEL_REG: +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK) { + case CMU_DBGCLKSEL_DBG_HFCLK: + ret = cmuSelect_HFCLK; + break; + + case CMU_DBGCLKSEL_DBG_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + +#elif defined(_CMU_CTRL_DBGCLK_MASK) + switch (CMU->CTRL & _CMU_CTRL_DBGCLK_MASK) { + case CMU_CTRL_DBGCLK_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_CTRL_DBGCLK_HFCLK: + ret = cmuSelect_HFCLK; + break; + } +#else + ret = cmuSelect_AUXHFRCO; +#endif + break; + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (CMU->STATUS + & (CMU_STATUS_USBCLFXOSEL +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + | CMU_STATUS_USBCHFCLKSEL +#endif +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + | CMU_STATUS_USBCUSHFRCOSEL +#endif + | CMU_STATUS_USBCLFRCOSEL)) { +#if defined(_CMU_STATUS_USBCHFCLKSEL_MASK) + case CMU_STATUS_USBCHFCLKSEL: + ret = cmuSelect_HFCLK; + break; +#endif + +#if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK) + case CMU_STATUS_USBCUSHFRCOSEL: + ret = cmuSelect_USHFRCO; + break; +#endif + + case CMU_STATUS_USBCLFXOSEL: + ret = cmuSelect_LFXO; + break; + + case CMU_STATUS_USBCLFRCOSEL: + ret = cmuSelect_LFRCO; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC0CLKSEL_MASK) { + case CMU_ADCCTRL_ADC0CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + + default: + ret = cmuSelect_Disabled; + break; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (CMU->ADCCTRL & _CMU_ADCCTRL_ADC1CLKSEL_MASK) { + case CMU_ADCCTRL_ADC1CLKSEL_DISABLED: + ret = cmuSelect_Disabled; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK: + ret = cmuSelect_HFSRCCLK; + break; + } + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (CMU->SDIOCTRL & _CMU_SDIOCTRL_SDIOCLKSEL_MASK) { + case CMU_SDIOCTRL_SDIOCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (CMU->QSPICTRL & _CMU_QSPICTRL_QSPI0CLKSEL_MASK) { + case CMU_QSPICTRL_QSPI0CLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO: + ret = cmuSelect_AUXHFRCO; + break; + + case CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + } + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (CMU->USBCTRL & _CMU_USBCTRL_USBCLKSEL_MASK) { + case CMU_USBCTRL_USBCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_HFXOX2: + ret = cmuSelect_HFXOX2; + break; + + case CMU_USBCTRL_USBCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFXO: + ret = cmuSelect_LFXO; + break; + + case CMU_USBCTRL_USBCLKSEL_LFRCO: + ret = cmuSelect_LFRCO; + break; + } + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (CMU->PDMCTRL & _CMU_PDMCTRL_PDMCLKSEL_MASK) { + case CMU_PDMCTRL_PDMCLKSEL_USHFRCO: + ret = cmuSelect_USHFRCO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFXO: + ret = cmuSelect_HFXO; + break; + + case CMU_PDMCTRL_PDMCLKSEL_HFRCO: + ret = cmuSelect_HFRCO; + break; + } + break; +#endif + + default: + ret = cmuSelect_Error; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the System Core Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigSystemCoreClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function configures the HFLE wait-states and divider suitable + * for the HF Clock. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock source is HFCLKLE. + ******************************************************************************/ +void sli_em_cmu_SetHFLEConfigHFClock(void) +{ +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * an LF clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and LFXO or LFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectLFOsc(uint8_t osc) +{ + if (osc == (uint8_t)cmuOsc_LFXO) { + // Enable LFXO oscillator + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + // Enable LFRCO oscillator + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + } else { + EFM_ASSERT(false); + } + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + if (osc == (uint8_t)cmuOsc_LFXO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFXO; + } else if (osc == (uint8_t)cmuOsc_LFRCO) { + CMU->CMD = CMU_CMD_HFCLKSEL_LFRCO; + } +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFXO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFXO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFXO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = SystemHFXOClockGet(); + EMU_VScaleEM01ByClock(vScaleFrequency, false); +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + // Adjust HFXO buffer current for frequencies above 32 MHz. + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + + // Enable HFXO oscillator + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(CMU_HFCLKSEL_HF_HFXO) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCO(void) +{ +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + if (((uint32_t)CMU_HFRCOBandGet() > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } +#endif + +#if defined(CMU_MAX_FREQ_HFLE) + // Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + // This is known after 'select' is written below. + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Wait for voltage upscaling to complete before the clock is set. + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemHFClockGet()); +#endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + // Set HFLE clock. + setHfLeConfig(SystemCoreClockGet()); +#endif +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Keep EMU module informed on the source HF clock frequency. This will apply voltage + // downscaling after clock is set if downscaling is configured. + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCODIV2(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemCoreClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * HFRCODIV2 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and HFRCODIV2 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectHFRCODIV2(void) +{ + // Enable HFRCO oscillator + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * CLKIN0 as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and CLKIN0 is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectCLKIN0(void) +{ + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_CLKIN0; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) +/***************************************************************************//** + * @brief This function is used to initialize the HF clock and selecting + * USHFRCO as the clock source. + * + * @note FOR INTERNAL USE ONLY. + * + * @note This function is needed for macro expansion of CMU_CLOCK_SELECT_SET when + * the clock is HF and USHFRCO is selected as the clock source. + ******************************************************************************/ +void sli_em_cmu_HFClockSelectUSHFRCO(void) +{ + // Enable USHFRCO oscillator + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + // Configure worst case wait-states for flash and set safe HFPER + // clock-tree prescalers. + flashWaitStateMax(); + hfperClkSafePrescaler(); + + // Select HF clock source. + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_USHFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + setHfLeConfig(SystemHFClockGet()); +#endif + + // Optimize flash access wait state setting for the currently selected core clk. + CMU_UpdateWaitStates(SystemCoreClockGet(), VSCALE_DEFAULT); + // Set optimized HFPER clock-tree prescalers. + hfperClkOptimizedPrescaler(); +} +#endif + +/***************************************************************************//** + * @brief + * Select the reference clock/oscillator used for a clock branch. + * + * @details + * Notice that if a selected reference is not enabled prior to selecting its + * use, it will be enabled and this function will wait for the selected + * oscillator to be stable. It will however NOT be disabled if another + * reference clock is selected later. + * + * This feature is particularly important if selecting a new reference + * clock for the clock branch clocking the core. Otherwise, the system + * may halt. + * + * @note + * HFCLKLE prescaler is automatically modified when peripherals with clock + * domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed. + * + * @param[in] clock + * A clock branch to select reference clock for. One of: + * @li #cmuClock_HF + * @li #cmuClock_LFA + * @li #cmuClock_LFB + * @if _CMU_LFCCLKEN0_MASK + * @li #cmuClock_LFC + * @endif + * @if _CMU_LFECLKEN0_MASK + * @li #cmuClock_LFE + * @endif + * @li #cmuClock_DBG + * @if _CMU_CMD_USBCLKSEL_MASK + * @li #cmuClock_USBC + * @endif + * @if _CMU_USBCTRL_MASK + * @li #cmuClock_USBR + * @endif + * + * @param[in] ref + * A reference selected for clocking. See the reference manual + * for details about references available for a specific clock branch. + * @li #cmuSelect_HFRCO + * @li #cmuSelect_LFRCO + * @li #cmuSelect_HFXO + * @if _CMU_HFXOCTRL_HFXOX2EN_MASK + * @li #cmuSelect_HFXOX2 + * @endif + * @li #cmuSelect_LFXO + * @li #cmuSelect_HFCLKLE + * @li #cmuSelect_AUXHFRCO + * @if _CMU_USHFRCOCTRL_MASK + * @li #cmuSelect_USHFRCO + * @endif + * @li #cmuSelect_HFCLK + * @ifnot DOXYDOC_EFM32_GECKO_FAMILY + * @li #cmuSelect_ULFRCO + * @endif + * @if CMU_OSCENCMD_PLFRCOEN + * @li #cmuSelect_PLFRCO + * @endif + ******************************************************************************/ +void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref) +{ + uint32_t select = (uint32_t)cmuOsc_HFRCO; + CMU_Osc_TypeDef osc = cmuOsc_HFRCO; + uint32_t freq; + uint32_t tmp; + uint32_t selRegId; +#if defined(_SILICON_LABS_32B_SERIES_1) + volatile uint32_t *selReg = NULL; +#endif +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + uint32_t lfExtended = 0; +#endif + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + uint32_t vScaleFrequency = 0; /* Use default. */ + + /* Start voltage upscaling before the clock is set. */ + if (clock == cmuClock_HF) { + if (ref == cmuSelect_HFXO) { + vScaleFrequency = SystemHFXOClockGet(); + } else if ((ref == cmuSelect_HFRCO) + && ((uint32_t)CMU_HFRCOBandGet() + > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + vScaleFrequency = (uint32_t)CMU_HFRCOBandGet(); + } else { + /* Use the default frequency. */ + } + if (vScaleFrequency != 0UL) { + EMU_VScaleEM01ByClock(vScaleFrequency, false); + } + } +#endif + + selRegId = ((unsigned)clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK; + + switch (selRegId) { + case CMU_HFCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFXO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFXO; +#endif + osc = cmuOsc_LFXO; + break; + + case cmuSelect_LFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_LFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_LFRCO; +#endif + osc = cmuOsc_LFRCO; + break; + + case cmuSelect_HFXO: +#if defined(CMU_HFCLKSEL_HF_HFXO) + select = CMU_HFCLKSEL_HF_HFXO; +#elif defined(CMU_CMD_HFCLKSEL_HFXO) + select = CMU_CMD_HFCLKSEL_HFXO; +#endif + osc = cmuOsc_HFXO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif +#if defined(CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ) + /* Adjust HFXO buffer current for frequencies above 32 MHz. */ + if (SystemHFXOClockGet() > 32000000) { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ; + } else { + CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ; + } +#endif + break; + + case cmuSelect_HFRCO: +#if defined(_SILICON_LABS_32B_SERIES_1) + select = CMU_HFCLKSEL_HF_HFRCO; +#elif defined(_SILICON_LABS_32B_SERIES_0) + select = CMU_CMD_HFCLKSEL_HFRCO; +#endif + osc = cmuOsc_HFRCO; +#if defined(CMU_MAX_FREQ_HFLE) + /* Set 1 HFLE wait-state until the new HFCLKLE frequency is known. + This is known after 'select' is written below. */ + setHfLeConfig(CMU_MAX_FREQ_HFLE + 1UL); +#endif + break; + +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + select = CMU_CMD_HFCLKSEL_USHFRCODIV2; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + select = CMU_HFCLKSEL_HF_HFRCODIV2; + osc = cmuOsc_HFRCO; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + select = CMU_HFCLKSEL_HF_CLKIN0; + osc = cmuOsc_CLKIN0; + break; +#endif + +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + select = CMU_HFCLKSEL_HF_USHFRCO; + osc = cmuOsc_USHFRCO; + break; +#endif + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) || defined(CMU_LFACLKSEL_LFA_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO cannot be used as HFCLK. */ + EFM_ASSERT(false); + return; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + if (osc != cmuOsc_CLKIN0) { + CMU_OscillatorEnable(osc, true, true); + } +#else + CMU_OscillatorEnable(osc, true, true); +#endif + + /* Configure worst case wait-states for flash and set safe HFPER + clock-tree prescalers. */ + flashWaitStateMax(); + hfperClkSafePrescaler(); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Wait for voltage upscaling to complete before the clock is set. */ + if (vScaleFrequency != 0UL) { + EMU_VScaleWait(); + } +#endif + + /* Switch to the selected oscillator. */ +#if defined(_CMU_HFCLKSEL_MASK) + CMU->HFCLKSEL = select; +#else + CMU->CMD = select; +#endif + /* Update the CMSIS core clock variable. */ + /* (The function will update the global variable). */ + freq = SystemCoreClockGet(); + +#if defined(CMU_MAX_FREQ_HFLE) + /* Update the HFLE configuration after 'select' is set. + Note that the HFCLKLE clock is connected differently on platforms 1 and 2. */ +#if defined(_SILICON_LABS_32B_SERIES_0) + setHfLeConfig(freq); +#else + setHfLeConfig(SystemHFClockGet()); +#endif +#endif + + /* Optimize flash access wait state setting for the currently selected core clk. */ + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* Keep EMU module informed on the source HF clock frequency. This will apply voltage + downscaling after clock is set if downscaling is configured. */ + if (vScaleFrequency == 0UL) { + EMU_VScaleEM01ByClock(0, true); + } +#endif + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) + case CMU_LFACLKSEL_REG: + selReg = &CMU->LFACLKSEL; + /* HFCLKCLE can't be used as LFACLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + +#if defined(_CMU_LFCCLKSEL_MASK) + case CMU_LFCCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFCCLKSEL : selReg; + /* HFCLKCLE can't be used as LFCCLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH +#endif + /* Fall through and select the clock source. */ + + case CMU_LFECLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg; + /* HFCLKCLE can't be used as LFECLK. */ + EFM_ASSERT(ref != cmuSelect_HFCLKLE); + SL_FALLTHROUGH + /* Fall through and select the clock source. */ + + case CMU_LFBCLKSEL_REG: + selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg; + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFACLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that thes elected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: + /* Ensure the correct HFLE wait-states and enable HFCLK to LE.*/ + setHfLeConfig(SystemHFClockGet()); + BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE; + break; + + case cmuSelect_ULFRCO: + /* ULFRCO is always on, there is no need to enable it. */ + tmp = _CMU_LFACLKSEL_LFA_ULFRCO; + break; + +#if defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + CMU_OscillatorEnable(cmuOsc_PLFRCO, true, true); + tmp = _CMU_LFACLKSEL_LFA_PLFRCO; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + *selReg = tmp; + break; + +#elif defined(_SILICON_LABS_32B_SERIES_0) + case CMU_LFACLKSEL_REG: + case CMU_LFBCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFA_LFRCO; + break; + + case cmuSelect_HFCLKLE: +#if defined(CMU_MAX_FREQ_HFLE) + /* Set the HFLE wait-state and divider. */ + freq = SystemCoreClockGet(); + setHfLeConfig(freq); +#endif + /* Ensure HFCORE to LE clocking is enabled. */ + BUS_RegBitWrite(&CMU->HFCORECLKEN0, _CMU_HFCORECLKEN0_LE_SHIFT, 1); + tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2; + break; + +#if defined(CMU_LFCLKSEL_LFAE_ULFRCO) + case cmuSelect_ULFRCO: + /* ULFRCO is always enabled. */ + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + lfExtended = 1; + break; +#endif + + default: + /* An illegal clock source for LFA/LFB selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + if (selRegId == CMU_LFACLKSEL_REG) { +#if defined(_CMU_LFCLKSEL_LFAE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) + | (tmp << _CMU_LFCLKSEL_LFA_SHIFT); +#endif + } else { +#if defined(_CMU_LFCLKSEL_LFBE_MASK) + CMU->LFCLKSEL = (CMU->LFCLKSEL + & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK)) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT) + | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT); +#else + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) + | (tmp << _CMU_LFCLKSEL_LFB_SHIFT); +#endif + } + break; + +#if defined(_CMU_LFCLKSEL_LFC_MASK) + case CMU_LFCCLKSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_LFCLKSEL_LFA_DISABLED; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_LFCLKSEL_LFC_LFRCO; + break; + + default: + /* An illegal clock source for LFC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK) + | (tmp << _CMU_LFCLKSEL_LFC_SHIFT); + break; +#endif +#endif + +#if defined(_CMU_DBGCLKSEL_DBG_MASK) || defined(CMU_CTRL_DBGCLK) + case CMU_DBGCLKSEL_REG: + switch (ref) { +#if defined(_CMU_DBGCLKSEL_DBG_MASK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; + break; +#endif + +#if defined(CMU_CTRL_DBGCLK) + case cmuSelect_AUXHFRCO: + /* Select AUXHFRCO as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_AUXHFRCO; + break; + + case cmuSelect_HFCLK: + /* Select divided HFCLK as a debug clock. */ + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK)) + | CMU_CTRL_DBGCLK_HFCLK; + break; +#endif + + default: + /* An illegal clock source for debug selected. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(USBC_CLOCK_PRESENT) + case CMU_USBCCLKSEL_REG: + switch (ref) { + case cmuSelect_LFXO: + /* Select LFXO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFXOSEL) == 0) { + } + break; + + case cmuSelect_LFRCO: + /* Select LFRCO as a clock source for USB. It can only be used in sleep mode. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL) == 0) { + } + break; + +#if defined(CMU_STATUS_USBCHFCLKSEL) + case cmuSelect_HFCLK: + /* Select undivided HFCLK as a clock source for USB. */ + /* The oscillator must already be enabled to avoid a core lockup. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV; + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL) == 0) { + } + break; +#endif + +#if defined(CMU_CMD_USBCCLKSEL_USHFRCO) + case cmuSelect_USHFRCO: + /* Select USHFRCO as a clock source for USB. */ + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + + /* Switch the oscillator. */ + CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO; + + /* Wait until the clock is activated. */ + while ((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL) == 0) { + } + break; +#endif + + default: + /* An illegal clock source for USB. */ + EFM_ASSERT(false); + return; + } + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC0CLKSEL_MASK) + case CMU_ADC0ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC0CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC0ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC0CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_ADCCTRL_ADC1CLKSEL_MASK) + case CMU_ADC1ASYNCSEL_REG: + switch (ref) { + case cmuSelect_Disabled: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_DISABLED; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_AUXHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFXO; + break; + + case cmuSelect_HFSRCCLK: + tmp = _CMU_ADCCTRL_ADC1CLKSEL_HFSRCCLK; + break; + + default: + /* An illegal clock source for ADC1ASYNC selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->ADCCTRL = (CMU->ADCCTRL & ~_CMU_ADCCTRL_ADC1CLKSEL_MASK) + | (tmp << _CMU_ADCCTRL_ADC1CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + case CMU_SDIOREFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_SDIOCTRL_SDIOCLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for SDIOREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->SDIOCTRL = (CMU->SDIOCTRL & ~_CMU_SDIOCTRL_SDIOCLKSEL_MASK) + | (tmp << _CMU_SDIOCTRL_SDIOCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + case CMU_QSPI0REFSEL_REG: + switch (ref) { + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_HFXO; + break; + + case cmuSelect_AUXHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_AUXHFRCO; + break; + + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_QSPICTRL_QSPI0CLKSEL_USHFRCO; + break; + + default: + /* An illegal clock source for QSPI0REF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->QSPICTRL = (CMU->QSPICTRL & ~_CMU_QSPICTRL_QSPI0CLKSEL_MASK) + | (tmp << _CMU_QSPICTRL_QSPI0CLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_USBCTRL_USBCLKSEL_MASK) + case CMU_USBRCLKSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFXO; + break; + + case cmuSelect_HFXOX2: + /* Only allowed for HFXO frequencies up to 25 MHz. */ + EFM_ASSERT(SystemHFXOClockGet() <= 25000000u); + + /* Enable HFXO X2. */ + CMU->HFXOCTRL |= CMU_HFXOCTRL_HFXOX2EN; + + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + + tmp = _CMU_USBCTRL_USBCLKSEL_HFXOX2; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_HFRCO; + break; + + case cmuSelect_LFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFXO; + break; + + case cmuSelect_LFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_LFRCO, true, true); + tmp = _CMU_USBCTRL_USBCLKSEL_LFRCO; + break; + + default: + /* An illegal clock source for USBR selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->USBCTRL = (CMU->USBCTRL & ~_CMU_USBCTRL_USBCLKSEL_MASK) + | (tmp << _CMU_USBCTRL_USBCLKSEL_SHIFT); + break; +#endif + +#if defined(_CMU_PDMCTRL_PDMCLKSEL_MASK) + case CMU_PDMREFSEL_REG: + switch (ref) { + case cmuSelect_USHFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_USHFRCO; + break; + + case cmuSelect_HFXO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFXO; + break; + + case cmuSelect_HFRCO: + /* Ensure that the selected oscillator is enabled, waiting for it to stabilize. */ + CMU_OscillatorEnable(cmuOsc_HFRCO, true, true); + tmp = _CMU_PDMCTRL_PDMCLKSEL_HFRCO; + break; + + default: + /* An illegal clock source for PDMREF selected. */ + EFM_ASSERT(false); + return; + } + + /* Apply select. */ + CMU->PDMCTRL = (CMU->PDMCTRL & ~_CMU_PDMCTRL_PDMCLKSEL_MASK) + | (tmp << _CMU_PDMCTRL_PDMCLKSEL_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified low frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_LFXO: + precision = lfxo_precision; + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) + case cmuSelect_PLFRCO: + precision = 500; + break; +#endif + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the specified high frequency clock branch. + * + * @param[in] clock + * Clock branch. + * + * @return + * Precision, in PPM, of the specified clock branch. + * + * @note + * This function is only for internal usage. + * + * @note + * The current implementation of this function is used to determine if the + * clock has a precision <= 500 ppm or not (which is the minimum required + * for BLE). Future version of this function should provide more accurate + * precision numbers to allow for further optimizations from the stacks. + ******************************************************************************/ +uint16_t CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock) +{ + CMU_Select_TypeDef src = CMU_ClockSelectGet(clock); + uint16_t precision; + + switch (src) { + case cmuSelect_HFXO: + precision = hfxo_precision; + break; + + case cmuSelect_HFRCO: + precision = 0xFFFF; + break; + + default: + precision = 0xFFFF; + break; + } + + return precision; +} + +#if defined(CMU_OSCENCMD_DPLLEN) +/**************************************************************************//** + * @brief + * Lock the DPLL to a given frequency. + * + * The frequency is given by: Fout = Fref * (N+1) / (M+1). + * + * @note + * This function does not check if the given N & M values will actually + * produce the desired target frequency. @n + * N & M limitations: @n + * 300 < N <= 4095 @n + * 0 <= M <= 4095 @n + * Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to + * calling this function to avoid over-clocking. + * + * HFCLKLE prescaler is automatically modified before updating HFRCO + * based on the maximum HFLE frequency allowed. + * + * @param[in] init + * DPLL setup parameters. + * + * @return + * Returns false on invalid target frequency or DPLL locking error. + *****************************************************************************/ +bool CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init) +{ + int index = 0; + unsigned int i; + bool hfrcoDiv2override = false; + uint32_t hfrcoCtrlVal, lockStatus, sysFreq; + + EFM_ASSERT(init->frequency >= hfrcoCtrlTable[0].minFreq); + EFM_ASSERT(init->frequency + <= hfrcoCtrlTable[HFRCOCTRLTABLE_ENTRIES - 1U].maxFreq); + EFM_ASSERT(init->n > 300U); + EFM_ASSERT(init->n <= (_CMU_DPLLCTRL1_N_MASK >> _CMU_DPLLCTRL1_N_SHIFT)); + EFM_ASSERT(init->m <= (_CMU_DPLLCTRL1_M_MASK >> _CMU_DPLLCTRL1_M_SHIFT)); + EFM_ASSERT(init->ssInterval <= (_CMU_HFRCOSS_SSINV_MASK + >> _CMU_HFRCOSS_SSINV_SHIFT)); + EFM_ASSERT(init->ssAmplitude <= (_CMU_HFRCOSS_SSAMP_MASK + >> _CMU_HFRCOSS_SSAMP_SHIFT)); + +#if defined(_EMU_STATUS_VSCALE_MASK) + if ((EMU_VScaleGet() == emuVScaleEM01_LowPower) + && (init->frequency > CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EFM_ASSERT(false); + return false; + } +#endif + + // Find the correct HFRCO band and retrieve a HFRCOCTRL value. + for (i = 0; i < HFRCOCTRLTABLE_ENTRIES; i++) { + if ((init->frequency >= hfrcoCtrlTable[i].minFreq) + && (init->frequency <= hfrcoCtrlTable[i].maxFreq)) { + index = (int)i; // Correct band found + break; + } + } + if ((uint32_t)index == HFRCOCTRLTABLE_ENTRIES) { + EFM_ASSERT(false); + return false; // Target frequency out of spec. + } + hfrcoCtrlVal = hfrcoCtrlTable[index].value; + + // Check if a calibrated HFRCOCTRL.TUNING value is in device DI page. + if (hfrcoCtrlTable[index].band != (CMU_HFRCOFreq_TypeDef)0) { + uint32_t tuning; + + tuning = (CMU_HFRCODevinfoGet(hfrcoCtrlTable[index].band) + & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + + // When HFRCOCTRL.FINETUNINGEN is enabled, the center frequency + // of the band shifts down by 5.8%. 9 is subtracted to compensate. + if (tuning > 9UL) { + tuning -= 9UL; + } else { + tuning = 0UL; + } + + hfrcoCtrlVal |= tuning << _CMU_HFRCOCTRL_TUNING_SHIFT; + } + + // Update the CMSIS frequency SystemHfrcoFreq value. + SystemHfrcoFreq = init->frequency; + + // Set maximum wait-states while changing the core clock. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + } + + // Update the HFLE configuration before updating HFRCO, use new DPLL frequency. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + setHfLeConfig(init->frequency); + + // Switch to HFRCO/2 before setting DPLL to avoid over-clocking. + hfrcoDiv2override = true; + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCODIV2; + } + + CMU->OSCENCMD = CMU_OSCENCMD_DPLLDIS; + while ((CMU->STATUS & (CMU_STATUS_DPLLENS | CMU_STATUS_DPLLRDY)) != 0UL) { + } + CMU->IFC = CMU_IFC_DPLLRDY | CMU_IFC_DPLLLOCKFAILLOW + | CMU_IFC_DPLLLOCKFAILHIGH; + CMU->DPLLCTRL1 = ((uint32_t)init->n << _CMU_DPLLCTRL1_N_SHIFT) + | ((uint32_t)init->m << _CMU_DPLLCTRL1_M_SHIFT); + CMU->HFRCOCTRL = hfrcoCtrlVal; + CMU->DPLLCTRL = ((uint32_t)init->refClk << _CMU_DPLLCTRL_REFSEL_SHIFT) + | ((init->autoRecover ? 1UL : 0UL) + << _CMU_DPLLCTRL_AUTORECOVER_SHIFT) + | ((uint32_t)init->edgeSel << _CMU_DPLLCTRL_EDGESEL_SHIFT) + | ((uint32_t)init->lockMode << _CMU_DPLLCTRL_MODE_SHIFT); + CMU->OSCENCMD = CMU_OSCENCMD_DPLLEN; + while ((lockStatus = (CMU->IF & (CMU_IF_DPLLRDY + | CMU_IF_DPLLLOCKFAILLOW + | CMU_IF_DPLLLOCKFAILHIGH))) == 0UL) { + } + + // Restore to HFRCO + if ((CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCODIV2) + && (hfrcoDiv2override == true)) { + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + } + + // If HFRCO is selected as an HF clock, optimize the flash access wait-state + // configuration for this frequency and update the CMSIS core clock variable. + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + // Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= init->frequency); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT(init->frequency == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + // Reduce HFLE frequency if possible. + setHfLeConfig(SystemHFClockGet()); + +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(0, true); +#endif + + if (lockStatus == CMU_IF_DPLLRDY) { + return true; + } + return false; +} +#endif // CMU_OSCENCMD_DPLLEN + +/**************************************************************************//** + * @brief + * CMU low frequency register synchronization freeze control. + * + * @details + * Some CMU registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * Another use case for this feature is using an API (such + * as the CMU API) for modifying several bit fields consecutively in the + * same register. If freeze mode is enabled during this sequence, stalling + * can be avoided. + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing CMU synchronization to LF domain to complete (normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring LF synchronization + * should be done within one freeze enable/disable block to avoid unnecessary + * stalling. + * + * @param[in] enable + * @li true - enable freeze, modified registers are not propagated to the + * LF domain + * @li false - disable freeze, modified registers are propagated to the LF + * domain + *****************************************************************************/ +void CMU_FreezeEnable(bool enable) +{ + if (enable) { + /* Wait for any ongoing LF synchronizations to complete. This */ + /* protects against the rare case when a user */ + /* - modifies a register requiring LF sync */ + /* - then enables freeze before LF sync completed */ + /* - then modifies the same register again */ + /* since modifying a register while it is in sync progress should be */ + /* avoided. */ + while (CMU->SYNCBUSY != 0UL) { + } + + CMU->FREEZE = CMU_FREEZE_REGFREEZE; + } else { + CMU->FREEZE = 0; + } +} + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Get HFRCO band in use. + * + * @return + * HFRCO band in use. + ******************************************************************************/ +CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) + >> _CMU_HFRCOCTRL_BAND_SHIFT); +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_BAND_MASK) +/***************************************************************************//** + * @brief + * Set HFRCO band and the tuning value based on the value in the calibration + * table made during production. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] band + * HFRCO band to activate. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t freq; + CMU_Select_TypeDef osc; + + /* Read the tuning value from the calibration table. */ + switch (band) { + case cmuHFRCOBand_1MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) + >> _DEVINFO_HFRCOCAL0_BAND1_SHIFT; + break; + + case cmuHFRCOBand_7MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) + >> _DEVINFO_HFRCOCAL0_BAND7_SHIFT; + break; + + case cmuHFRCOBand_11MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) + >> _DEVINFO_HFRCOCAL0_BAND11_SHIFT; + break; + + case cmuHFRCOBand_14MHz: + tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) + >> _DEVINFO_HFRCOCAL0_BAND14_SHIFT; + break; + + case cmuHFRCOBand_21MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) + >> _DEVINFO_HFRCOCAL1_BAND21_SHIFT; + break; + +#if defined(_CMU_HFRCOCTRL_BAND_28MHZ) + case cmuHFRCOBand_28MHz: + tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) + >> _DEVINFO_HFRCOCAL1_BAND28_SHIFT; + break; +#endif + + default: + EFM_ASSERT(false); + return; + } + + /* If HFRCO is used for the core clock, flash access WS has to be considered. */ + osc = CMU_ClockSelectGet(cmuClock_HF); + if (osc == cmuSelect_HFRCO) { + /* Configure worst case wait states for flash access before setting the divider. */ + flashWaitStateMax(); + } + + /* Set band/tuning. */ + CMU->HFRCOCTRL = (CMU->HFRCOCTRL + & ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) + | (band << _CMU_HFRCOCTRL_BAND_SHIFT) + | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT); + + /* If HFRCO is used for the core clock, optimize flash WS. */ + if (osc == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + freq = SystemCoreClockGet(); + CMU_UpdateWaitStates(freq, VSCALE_DEFAULT); + } + +#if defined(CMU_MAX_FREQ_HFLE) + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemCoreClockGet()); +#endif +} +#endif /* _CMU_HFRCOCTRL_BAND_MASK */ + +#if defined(_CMU_HFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the HFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * HFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq) +{ + switch (freq) { + /* 1, 2, and 4 MHz share the same calibration word. */ + case cmuHFRCOFreq_1M0Hz: + case cmuHFRCOFreq_2M0Hz: + case cmuHFRCOFreq_4M0Hz: + return DEVINFO->HFRCOCAL0; + + case cmuHFRCOFreq_7M0Hz: + return DEVINFO->HFRCOCAL3; + + case cmuHFRCOFreq_13M0Hz: + return DEVINFO->HFRCOCAL6; + + case cmuHFRCOFreq_16M0Hz: + return DEVINFO->HFRCOCAL7; + + case cmuHFRCOFreq_19M0Hz: + return DEVINFO->HFRCOCAL8; + + case cmuHFRCOFreq_26M0Hz: + return DEVINFO->HFRCOCAL10; + + case cmuHFRCOFreq_32M0Hz: + return DEVINFO->HFRCOCAL11; + + case cmuHFRCOFreq_38M0Hz: + return DEVINFO->HFRCOCAL12; + +#if defined(_DEVINFO_HFRCOCAL13_MASK) + case cmuHFRCOFreq_48M0Hz: + return DEVINFO->HFRCOCAL13; +#endif + +#if defined(_DEVINFO_HFRCOCAL14_MASK) + case cmuHFRCOFreq_56M0Hz: + return DEVINFO->HFRCOCAL14; +#endif + +#if defined(_DEVINFO_HFRCOCAL15_MASK) + case cmuHFRCOFreq_64M0Hz: + return DEVINFO->HFRCOCAL15; +#endif + +#if defined(_DEVINFO_HFRCOCAL16_MASK) + case cmuHFRCOFreq_72M0Hz: + return DEVINFO->HFRCOCAL16; +#endif + + default: /* cmuHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current HFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void) +{ + return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO calibration for the selected target frequency. + * + * @note + * HFCLKLE prescaler is automatically modified based on the maximum + * HFLE frequency allowed. + * + * @param[in] setFreq + * HFRCO frequency to set. + ******************************************************************************/ +void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + uint32_t sysFreq; + uint32_t prevFreq; + + /* Get the DEVINFO index and set the CMSIS frequency SystemHfrcoFreq. */ + freqCal = CMU_HFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0UL) && (freqCal != UINT_MAX)); + prevFreq = SystemHfrcoFreq; + SystemHfrcoFreq = (uint32_t)setFreq; + + /* Set maximum wait-states and set safe HFPER clock-tree prescalers while + changing the core clock. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + flashWaitStateMax(); + hfperClkSafePrescaler(); + } + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } + + /* Check for valid calibration data. */ + EFM_ASSERT(freqCal != UINT_MAX); + + /* Set divider in HFRCOCTRL for 1, 2, and 4 MHz. */ + switch (setFreq) { + case cmuHFRCOFreq_1M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + break; + + case cmuHFRCOFreq_2M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV2; + break; + + case cmuHFRCOFreq_4M0Hz: + freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV1; + break; + + default: + break; + } + + /* Update HFLE configuration before updating HFRCO. + Use the new set frequency. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* setFreq is worst-case as dividers may reduce the HFLE frequency. */ + setHfLeConfig((uint32_t)setFreq); + } + + if ((uint32_t)setFreq > prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When increasing frequency voltage scale must be done before the change. */ + EMU_VScaleEM01ByClock((uint32_t)setFreq, true); +#endif + } + + CMU->HFRCOCTRL = freqCal; + + /* If HFRCO is selected as an HF clock, optimize the flash access wait-state configuration + for this frequency and update the CMSIS core clock variable. */ + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Call @ref SystemCoreClockGet() to update the CMSIS core clock variable. */ + sysFreq = SystemCoreClockGet(); + EFM_ASSERT(sysFreq <= (uint32_t)setFreq); + EFM_ASSERT(sysFreq <= SystemHfrcoFreq); + EFM_ASSERT((uint32_t)setFreq == SystemHfrcoFreq); + CMU_UpdateWaitStates(sysFreq, VSCALE_DEFAULT); + } + + /* Reduce HFLE frequency if possible. */ + setHfLeConfig(SystemHFClockGet()); + + if ((uint32_t)setFreq <= prevFreq) { +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + /* When decreasing frequency voltage scale must be done after the change */ + EMU_VScaleEM01ByClock(0, true); +#endif + } + if (CMU_ClockSelectGet(cmuClock_HF) == cmuSelect_HFRCO) { + /* Set optimized HFPER clock-tree prescalers. */ + hfperClkOptimizedPrescaler(); + } +} +#endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFRCOCTRL_SUDELAY_MASK) +/***************************************************************************//** + * @brief + * Get the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @return + * The startup delay in use. + ******************************************************************************/ +uint32_t CMU_HFRCOStartupDelayGet(void) +{ + return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) + >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; +} + +/***************************************************************************//** + * @brief + * Set the HFRCO startup delay. + * + * @details + * See the reference manual for more details. + * + * @param[in] delay + * The startup delay to set (<= 31). + ******************************************************************************/ +void CMU_HFRCOStartupDelaySet(uint32_t delay) +{ + EFM_ASSERT(delay <= 31); + + delay &= _CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT; + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) + | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT); +} +#endif + +#if defined(_CMU_USHFRCOCTRL_FREQRANGE_MASK) +/**************************************************************************//** + * @brief + * Get the USHFRCO frequency calibration word in DEVINFO. + * + * @param[in] freq + * Frequency in Hz. + * + * @return + * USHFRCO calibration word for a given frequency. + *****************************************************************************/ +static uint32_t CMU_USHFRCODevinfoGet(CMU_USHFRCOFreq_TypeDef freq) +{ + switch (freq) { + case cmuUSHFRCOFreq_16M0Hz: + return DEVINFO->USHFRCOCAL7; + + case cmuUSHFRCOFreq_32M0Hz: + return DEVINFO->USHFRCOCAL11; + + case cmuUSHFRCOFreq_48M0Hz: + return DEVINFO->USHFRCOCAL13; + + case cmuUSHFRCOFreq_50M0Hz: + return DEVINFO->USHFRCOCAL14; + + default: /* cmuUSHFRCOFreq_UserDefined */ + return 0; + } +} + +/***************************************************************************//** + * @brief + * Get the current USHFRCO frequency. + * + * @return + * HFRCO frequency. + ******************************************************************************/ +CMU_USHFRCOFreq_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOFreq_TypeDef) ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} + +/***************************************************************************//** + * @brief + * Set the USHFRCO calibration for the selected target frequency. + * + * @param[in] setFreq + * USHFRCO frequency to set. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOFreq_TypeDef setFreq) +{ + uint32_t freqCal; + + /* Get DEVINFO calibration values. */ + freqCal = CMU_USHFRCODevinfoGet(setFreq); + EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX)); + ushfrcoFreq = (uint32_t)setFreq; + + /* Wait for any previous sync to complete and set calibration data + for the selected frequency. */ + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) ; + + CMU->USHFRCOCTRL = freqCal; +} +#endif /* _CMU_USHFRCOCTRL_FREQRANGE_MASK */ + +#if defined(_CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK) +/***************************************************************************//** + * @brief + * Enable or disable HFXO autostart. + * + * @param[in] userSel + * Additional user specified enable bit. + * + * @param[in] enEM0EM1Start + * If true, HFXO is automatically started upon entering EM0/EM1 entry from + * EM2/EM3. HFXO selection has to be handled by the user. + * If false, HFXO is not started automatically when entering EM0/EM1. + * + * @param[in] enEM0EM1StartSel + * If true, HFXO is automatically started and immediately selected upon + * entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of + * HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically + * modified if userSel is specified. + * If false, HFXO is not started or selected automatically when entering + * EM0/EM1. + ******************************************************************************/ +void CMU_HFXOAutostartEnable(uint32_t userSel, + bool enEM0EM1Start, + bool enEM0EM1StartSel) +{ + uint32_t hfxoFreq; + uint32_t hfxoCtrl; + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) + if (enEM0EM1StartSel) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) == EMU_CTRL_EM23VSCALE_VSCALE2); + } +#endif + + /* Mask supported enable bits. */ +#if defined(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK) + userSel &= _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK; +#else + userSel = 0; +#endif + + hfxoFreq = SystemHFXOClockGet(); +#if defined(_EMU_CMD_EM01VSCALE0_MASK) + // Update voltage scaling. + EMU_VScaleEM01ByClock(hfxoFreq, true); +#endif + /* Set wait-states for HFXO if automatic start and select is configured. */ + if ((userSel > 0UL) || enEM0EM1StartSel) { + CMU_UpdateWaitStates(hfxoFreq, VSCALE_DEFAULT); + setHfLeConfig(hfxoFreq / CMU_ClockDivGet(cmuClock_HF)); + } + + if (enEM0EM1Start || enEM0EM1StartSel) { + /* Enable the HFXO once in order to finish first time calibrations. */ + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + } + + /* Since call to CMU_OscillatorEnable() can change the CMU->HFXOCTRL register, + * it's important to read the CMU->HFXOCTRL register after the call to CMU_OscillatorEnable(). */ + hfxoCtrl = CMU->HFXOCTRL & ~(userSel + | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK + | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK); + + hfxoCtrl |= userSel + | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0UL) + | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0UL); + + /* Update HFXOCTRL after wait-states are updated as HF may automatically switch + to HFXO when automatic select is enabled . */ + CMU->HFXOCTRL = hfxoCtrl; +} +#endif + +/**************************************************************************//** + * @brief + * Set HFXO control registers. + * + * @note + * HFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the HFXO to + * ensure a valid state before update. + * + * @param[in] hfxoInit + * HFXO setup parameters. + *****************************************************************************/ +void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit) +{ + /* Do not disable HFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO); + + /* HFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && (_SILICON_LABS_GECKO_INTERNAL_SDID >= 100) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + switch (hfxoInit->mode) { + case cmuOscMode_Crystal: + tmp = CMU_HFXOCTRL_MODE_XTAL; + break; + case cmuOscMode_External: + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + break; + case cmuOscMode_AcCoupled: + tmp = CMU_HFXOCTRL_MODE_ACBUFEXTCLK; + break; + default: + EFM_ASSERT(false); /* Unsupported configuration */ + break; + } + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) | tmp; + +#if defined(CMU_HFXOCTRL_HFXOX2EN) + /* HFXO Doubler can only be enabled on crystals up to max 25 MHz. */ + tmp = 0; + if (SystemHFXOClockGet() <= 25000000) { + tmp |= CMU_HFXOCTRL_HFXOX2EN; + } + + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_HFXOX2EN_MASK) | tmp; +#endif + + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = (hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK)) + | (hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | (hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT); + + /* Set timeouts */ + CMU->HFXOTIMEOUTCTRL = (hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | (hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | (hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT); + +#elif defined(_CMU_HFXOCTRL_MASK) + uint32_t tmp = CMU_HFXOCTRL_MODE_XTAL; + + /* AC coupled external clock not supported. */ + EFM_ASSERT(hfxoInit->mode != cmuOscMode_AcCoupled); + if (hfxoInit->mode == cmuOscMode_External) { + tmp = CMU_HFXOCTRL_MODE_DIGEXTCLK; + } + + /* Apply control settings. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_MODE_MASK) + | tmp; + BUS_RegBitWrite(&CMU->HFXOCTRL, + _CMU_HFXOCTRL_LOWPOWER_SHIFT, + (unsigned)hfxoInit->lowPowerMode); + + /* Set XTAL tuning parameters. */ + +#if defined(_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + /* Set peak detection threshold. */ + CMU->HFXOCTRL1 = (CMU->HFXOCTRL1 & ~_CMU_HFXOCTRL1_PEAKDETTHR_MASK) + | (hfxoInit->thresholdPeakDetect + << _CMU_HFXOCTRL1_PEAKDETTHR_SHIFT); +#endif + /* Set tuning for startup and steady state. */ + CMU->HFXOSTARTUPCTRL = ((uint32_t)hfxoInit->ctuneStartup + << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimStartup + << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT); + + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK + | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | ((uint32_t)hfxoInit->ctuneSteadyState + << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT) + | ((uint32_t)hfxoInit->xoCoreBiasTrimSteadyState + << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT) + | ((uint32_t)hfxoInit->regIshSteadyState + << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT) + | getRegIshUpperVal(hfxoInit->regIshSteadyState); + + /* Set timeouts. */ + CMU->HFXOTIMEOUTCTRL = ((uint32_t)hfxoInit->timeoutPeakDetect + << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutSteady + << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutStartup + << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT) + | ((uint32_t)hfxoInit->timeoutShuntOptimization + << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT); + +#else + CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_HFXOTIMEOUT_MASK + | _CMU_CTRL_HFXOBOOST_MASK + | _CMU_CTRL_HFXOMODE_MASK + | _CMU_CTRL_HFXOGLITCHDETEN_MASK)) + | (hfxoInit->timeout << _CMU_CTRL_HFXOTIMEOUT_SHIFT) + | (hfxoInit->boost << _CMU_CTRL_HFXOBOOST_SHIFT) + | (hfxoInit->mode << _CMU_CTRL_HFXOMODE_SHIFT) + | (hfxoInit->glitchDetector ? CMU_CTRL_HFXOGLITCHDETEN : 0); +#endif +} + +/***************************************************************************//** + * @brief + * Get the LCD framerate divisor (FDIV) setting. + * + * @return + * The LCD framerate divisor. + ******************************************************************************/ +uint32_t CMU_LCDClkFDIVGet(void) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT; +#else + return 0; +#endif /* defined(LCD_PRESENT) */ +} + +/***************************************************************************//** + * @brief + * Set the LCD framerate divisor (FDIV) setting. + * + * @note + * The FDIV field (CMU LCDCTRL register) should only be modified while the + * LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function + * will NOT modify FDIV if the LCD module clock is enabled. See + * @ref CMU_ClockEnable() for disabling/enabling LCD clock. + * + * @param[in] div + * The FDIV setting to use. + ******************************************************************************/ +void CMU_LCDClkFDIVSet(uint32_t div) +{ +#if defined(LCD_PRESENT) && defined(_CMU_LCDCTRL_MASK) + EFM_ASSERT(div <= cmuClkDiv_128); + + /* Do not allow modification if LCD clock enabled. */ + if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD) { + return; + } + + div <<= _CMU_LCDCTRL_FDIV_SHIFT; + div &= _CMU_LCDCTRL_FDIV_MASK; + CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div; +#else + (void)div; /* Unused parameter. */ +#endif /* defined(LCD_PRESENT) */ +} + +/**************************************************************************//** + * @brief + * Set LFXO control registers. + * + * @note + * LFXO configuration should be obtained from a configuration tool, + * app note, or crystal data sheet. This function disables the LFXO when + * necessary to ensure a valid state before update. + * + * @param[in] lfxoInit + * LFXO setup parameters. + *****************************************************************************/ +void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit) +{ + /* Do not disable LFXO if it is currently selected as the HF/Core clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO); + +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t reg = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK + | _CMU_LFXOCTRL_GAIN_MASK + | _CMU_LFXOCTRL_TIMEOUT_MASK + | _CMU_LFXOCTRL_MODE_MASK)) + | ((uint32_t)lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT) + | ((uint32_t)lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT) + | ((uint32_t)lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_LFXOCTRL_MODE_SHIFT); + + /* If LFXO already contains the correct configuration then there is no need + * to stop the oscillator and apply new settings. The LFXO can be running out + * of reset, in which case there is no need to disable it unless necessary. */ + if (reg != CMU->LFXOCTRL) { + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + CMU->LFXOCTRL = reg; + } +#elif defined(_SILICON_LABS_32B_SERIES_0) + /* LFXO must be disabled before reconfiguration. */ + CMU_OscillatorEnable(cmuOsc_LFXO, false, true); + + bool cmuBoost = (lfxoInit->boost & 0x2); + BUS_RegMaskedWrite(&CMU->CTRL, + _CMU_CTRL_LFXOTIMEOUT_MASK + | _CMU_CTRL_LFXOBOOST_MASK + | _CMU_CTRL_LFXOMODE_MASK, + ((uint32_t)lfxoInit->timeout + << _CMU_CTRL_LFXOTIMEOUT_SHIFT) + | ((cmuBoost ? 1 : 0) << _CMU_CTRL_LFXOBOOST_SHIFT) + | ((uint32_t)lfxoInit->mode << _CMU_CTRL_LFXOMODE_SHIFT)); +#if defined(_EMU_AUXCTRL_REDLFXOBOOST_MASK) + /* EFM32GG has a "reduce startup boost" field in the EMU */ + bool emuReduce = (lfxoInit->boost & 0x1); + BUS_RegBitWrite(&EMU->AUXCTRL, _EMU_AUXCTRL_REDLFXOBOOST_SHIFT, emuReduce ? 1 : 0); +#endif +#endif +} + +/**************************************************************************//** + * @brief + * Sets LFXO's crystal precision, in PPM. + * + * @note + * LFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_LFXOPrecisionSet(uint16_t precision) +{ + lfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets LFXO's crystal precision, in PPM. + * + * @param[in] precision + * LFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_LFXOPrecisionGet(void) +{ + return lfxo_precision; +} + +/**************************************************************************//** + * @brief + * Sets HFXO's crystal precision, in PPM. + * + * @note + * HFXO precision should be obtained from a crystal datasheet. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +void CMU_HFXOPrecisionSet(uint16_t precision) +{ + hfxo_precision = precision; +} + +/**************************************************************************//** + * @brief + * Gets HFXO's crystal precision, in PPM. + * + * @param[in] precision + * HFXO's crystal precision, in PPM. + *****************************************************************************/ +uint16_t CMU_HFXOPrecisionGet(void) +{ + return hfxo_precision; +} + +/***************************************************************************//** + * @brief + * Enable/disable oscillator. + * + * @note + * WARNING: When this function is called to disable either cmuOsc_LFXO or + * cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register + * are reset to the reset value. In other words, if external clock sources are selected + * in either LFXOMODE or HFXOMODE fields, the configuration will be cleared + * and needs to be reconfigured if needed later. + * + * @param[in] osc + * The oscillator to enable/disable. + * + * @param[in] enable + * @li true - enable specified oscillator. + * @li false - disable specified oscillator. + * + * @param[in] wait + * Only used if @p enable is true. + * @li true - wait for oscillator start-up time to timeout before returning. + * @li false - do not wait for oscillator start-up time to timeout before + * returning. + ******************************************************************************/ +void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait) +{ + uint32_t rdyBitPos; +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t ensBitPos; +#endif +#if defined(_CMU_STATUS_HFXOPEAKDETRDY_MASK) + uint32_t hfxoTrimStatus; +#endif + + uint32_t enBit; + uint32_t disBit; + + switch (osc) { + case cmuOsc_HFRCO: + enBit = CMU_OSCENCMD_HFRCOEN; + disBit = CMU_OSCENCMD_HFRCODIS; + rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_HFXO: + enBit = CMU_OSCENCMD_HFXOEN; + disBit = CMU_OSCENCMD_HFXODIS; + rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_HFXOENS_SHIFT; +#endif + break; + + case cmuOsc_AUXHFRCO: + enBit = CMU_OSCENCMD_AUXHFRCOEN; + disBit = CMU_OSCENCMD_AUXHFRCODIS; + rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFRCO: + enBit = CMU_OSCENCMD_LFRCOEN; + disBit = CMU_OSCENCMD_LFRCODIS; + rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT; +#endif + break; + + case cmuOsc_LFXO: + enBit = CMU_OSCENCMD_LFXOEN; + disBit = CMU_OSCENCMD_LFXODIS; + rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_LFXOENS_SHIFT; +#endif + break; + +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + case cmuOsc_USHFRCO: + enBit = CMU_OSCENCMD_USHFRCOEN; + disBit = CMU_OSCENCMD_USHFRCODIS; + rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT; +#if defined(_SILICON_LABS_32B_SERIES_1) + ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT; +#endif + break; +#endif + +#if defined(PLFRCO_PRESENT) + case cmuOsc_PLFRCO: + if (!deviceHasPlfrco()) { + while (true) { // PLFRCO is not available + EFM_ASSERT(false); + } + } + enBit = CMU_OSCENCMD_PLFRCOEN; + disBit = CMU_OSCENCMD_PLFRCODIS; + rdyBitPos = _CMU_STATUS_PLFRCORDY_SHIFT; + ensBitPos = _CMU_STATUS_PLFRCOENS_SHIFT; + break; +#endif + + default: + /* Undefined clock source, cmuOsc_CLKIN0 or cmuOsc_ULFRCO. ULFRCO is always enabled + and cannot be disabled. In other words,the definition of cmuOsc_ULFRCO is primarily + intended for information: the ULFRCO is always on. */ + EFM_ASSERT(false); + return; + } + + if (enable) { + #if defined(_CMU_HFXOCTRL_MASK) + bool firstHfxoEnable = false; + + /* Enabling the HFXO for the first time requires special handling. + * PEAKDETSHUTOPTMODE field of the HFXOCTRL register is used to see if this is the + * first time the HFXO is enabled. */ + if (osc == cmuOsc_HFXO) { + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + /* REGPWRSEL must be set to DVDD before the HFXO can be enabled. */ +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + EFM_ASSERT((EMU->PWRCTRL & EMU_PWRCTRL_REGPWRSEL_DVDD) != 0UL); +#endif + + firstHfxoEnable = true; + /* The first time that an external clock is enabled, switch to CMD mode to make sure that + * only SCO and not PDA tuning is performed. */ + if ((CMU->HFXOCTRL & (_CMU_HFXOCTRL_MODE_MASK)) == CMU_HFXOCTRL_MODE_DIGEXTCLK) { + setHfxoTuningMode(HFXO_TUNING_MODE_CMD); + } + } + } +#endif + CMU->OSCENCMD = enBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go high. */ + while (BUS_RegBitRead(&CMU->STATUS, ensBitPos) == 0UL) { + } +#endif + + /* Wait for the clock to become ready after enable. */ + if (wait) { + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } +#if defined(_SILICON_LABS_32B_SERIES_1) + if ((osc == cmuOsc_HFXO) && firstHfxoEnable) { + if ((CMU->HFXOCTRL & _CMU_HFXOCTRL_MODE_MASK) + == CMU_HFXOCTRL_MODE_DIGEXTCLK) { +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + /* External clock mode should only do shunt current optimization. */ + (void)CMU_OscillatorTuningOptimize(cmuOsc_HFXO, + cmuHFXOTuningMode_ShuntCommand, + true); +#endif + } else { + /* Wait for the peak detection and shunt current optimization + to complete. */ + (void)CMU_OscillatorTuningWait(cmuOsc_HFXO, cmuHFXOTuningMode_Auto); + } + + /* Disable the HFXO again to apply the trims. Apply trim from + HFXOTRIMSTATUS when disabled. */ + hfxoTrimStatus = CMU_OscillatorTuningGet(cmuOsc_HFXO); + CMU_OscillatorEnable(cmuOsc_HFXO, false, true); + CMU_OscillatorTuningSet(cmuOsc_HFXO, hfxoTrimStatus); + + /* Restart in CMD mode. */ + CMU->OSCENCMD = enBit; + while (BUS_RegBitRead(&CMU->STATUS, rdyBitPos) == 0UL) { + } + } +#endif + } + } else { + CMU->OSCENCMD = disBit; + +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Always wait for ENS to go low. */ + while ((CMU->STATUS & (0x1 << ensBitPos)) != 0U) { + } + + if (wait) { + /* Wait for RDY to go low as well. */ + while ((CMU->STATUS & (0x1 << rdyBitPos)) != 0U) { + } + } +#endif + } +} + +/***************************************************************************//** + * @brief + * Get the oscillator frequency tuning setting. + * + * @param[in] osc + * An oscillator to get tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE is defined + * + * @return + * The oscillator frequency tuning setting in use. + ******************************************************************************/ +uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc) +{ + uint32_t ret; + + switch (osc) { + case cmuOsc_LFRCO: + ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) + >> _CMU_LFRCOCTRL_TUNING_SHIFT; + break; + + case cmuOsc_HFRCO: + ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) + >> _CMU_HFRCOCTRL_TUNING_SHIFT; + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + ret = (CMU->USHFRCOCTRL & _CMU_USHFRCOCTRL_TUNING_MASK) + >> _CMU_USHFRCOCTRL_TUNING_SHIFT; + break; +#endif + + case cmuOsc_AUXHFRCO: + ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT; + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + ret = CMU->HFXOTRIMSTATUS & (_CMU_HFXOTRIMSTATUS_IBTRIMXOCORE_MASK +#if defined(_CMU_HFXOTRIMSTATUS_REGISH_MASK) + | _CMU_HFXOTRIMSTATUS_REGISH_MASK +#endif + ); + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + ret = (CMU->LFXOCTRL & _CMU_LFXOCTRL_TUNING_MASK) >> _CMU_LFXOCTRL_TUNING_SHIFT; + break; +#endif + + default: + ret = 0; + EFM_ASSERT(false); + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the oscillator frequency tuning control. + * + * @note + * Oscillator tuning is done during production and the tuning value is + * automatically loaded after reset. Changing the tuning value from the + * calibrated value is for more advanced use. Certain oscillators also have + * build-in tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_LFRCO + * @li #cmuOsc_HFRCO @if _CMU_USHFRCOCTRL_TUNING_MASK + * @li #cmuOsc_USHFRCO + * @endif + * @li #cmuOsc_AUXHFRCO + * @li #cmuOsc_HFXO if PEAKDETSHUNTOPTMODE is available. Note that CMD mode is set. + * + * @param[in] val + * The oscillator frequency tuning setting to use. + ******************************************************************************/ +void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + uint8_t ctune = 0; +#endif + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + uint32_t regIshUpper; +#endif + + switch (osc) { + case cmuOsc_LFRCO: + EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK + >> _CMU_LFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) + | (val << _CMU_LFRCOCTRL_TUNING_SHIFT); + break; + + case cmuOsc_HFRCO: + EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK + >> _CMU_HFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_HFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) + | (val << _CMU_HFRCOCTRL_TUNING_SHIFT); + break; + +#if defined (_CMU_USHFRCOCTRL_TUNING_MASK) + case cmuOsc_USHFRCO: + EFM_ASSERT(val <= (_CMU_USHFRCOCTRL_TUNING_MASK + >> _CMU_USHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_USHFRCOCTRL_TUNING_MASK >> _CMU_USHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_USHFRCOBSY_SHIFT)) { + } +#endif + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~(_CMU_USHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_USHFRCOCTRL_TUNING_SHIFT); + break; +#endif + + case cmuOsc_AUXHFRCO: + EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK + >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT)); + val &= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT); +#if defined(_SILICON_LABS_32B_SERIES_1) + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT) != 0UL) { + } +#endif + CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) + | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT); + break; + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + case cmuOsc_HFXO: + + /* Do set PEAKDETSHUNTOPTMODE or HFXOSTEADYSTATECTRL if HFXO is enabled. */ + EFM_ASSERT((CMU->STATUS & CMU_STATUS_HFXOENS) == 0UL); + + /* Switch to command mode. Automatic SCO and PDA calibration is not done + at the next enable. Set user REGISH, REGISHUPPER, and IBTRIMXOCORE. */ + CMU->HFXOCTRL = (CMU->HFXOCTRL & ~_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) + | CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_CMD; + +#if defined(_CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + regIshUpper = getRegIshUpperVal((val & _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK) + >> _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT); + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~(_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK + | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK)) + | val + | regIshUpper; +#else + CMU->HFXOSTEADYSTATECTRL = (CMU->HFXOSTEADYSTATECTRL + & ~_CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK) + | val; +#endif + + break; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) && !defined(_EFR32_ZEN_FAMILY) + case cmuOsc_LFXO: + EFM_ASSERT(val <= (_CMU_LFXOCTRL_TUNING_MASK >> _CMU_LFXOCTRL_TUNING_SHIFT)); + // Max internal capacitance tuning value is 0x4F (20 pF) + ctune = (uint8_t) SL_MIN(0x4FU, val); + + // Wait for the CMU_LFXOCTRL is ready for update + while (BUS_RegBitRead(&CMU->SYNCBUSY, + _CMU_SYNCBUSY_LFXOBSY_SHIFT) != 0UL) { + } + CMU->LFXOCTRL = (CMU->LFXOCTRL & ~(_CMU_LFXOCTRL_TUNING_MASK)) + | ((uint32_t)ctune << _CMU_LFXOCTRL_TUNING_SHIFT); + break; +#endif + + default: + EFM_ASSERT(false); + break; + } +} + +#if defined(_CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK) || defined(_CMU_HFXOCTRL_PEAKDETMODE_MASK) +/***************************************************************************//** + * @brief + * Wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode) +{ + uint32_t waitFlags; + EFM_ASSERT(osc == cmuOsc_HFXO); + + /* Currently implemented for HFXO with PEAKDETSHUNTOPTMODE only. */ + (void)osc; + + if (getHfxoTuningMode() == HFXO_TUNING_MODE_AUTO) { + waitFlags = HFXO_TUNING_READY_FLAGS; + } else { + /* Set wait flags for each command and wait. */ + switch (mode) { +#if defined(_CMU_STATUS_HFXOSHUNTOPTRDY_MASK) + case cmuHFXOTuningMode_ShuntCommand: + waitFlags = CMU_STATUS_HFXOSHUNTOPTRDY; + break; +#endif + case cmuHFXOTuningMode_Auto: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; + +#if defined(CMU_CMD_HFXOSHUNTOPTSTART) + case cmuHFXOTuningMode_PeakShuntCommand: + waitFlags = HFXO_TUNING_READY_FLAGS; + break; +#endif + + default: + waitFlags = _CMU_STATUS_MASK; + EFM_ASSERT(false); + break; + } + } + while ((CMU->STATUS & waitFlags) != waitFlags) { + } + +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Check error flags. */ + if ((waitFlags & CMU_STATUS_HFXOPEAKDETRDY) != 0UL) { + return (CMU->IF & CMU_IF_HFXOPEAKDETERR) != 0UL ? true : false; + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Start and optionally wait for the oscillator tuning optimization. + * + * @param[in] osc + * An oscillator to set tuning value for, one of the following: + * @li #cmuOsc_HFXO + * + * @param[in] mode + * Tuning optimization mode. + * + * @param[in] wait + * Wait for tuning optimization to complete. + * true - wait for tuning optimization to complete. + * false - return without waiting. + * + * @return + * Returns false on invalid parameters or oscillator error status. + ******************************************************************************/ +bool CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, + CMU_HFXOTuningMode_TypeDef mode, + bool wait) +{ + switch (osc) { + case cmuOsc_HFXO: + if ((unsigned)mode != 0U) { +#if defined(CMU_IF_HFXOPEAKDETERR) + /* Clear the error flag before command write. */ + CMU->IFC = CMU_IFC_HFXOPEAKDETERR; +#endif + CMU->CMD = (uint32_t)mode; + } + if (wait) { + return CMU_OscillatorTuningWait(osc, mode); + } + break; + + default: + EFM_ASSERT(false); + break; + } + return true; +} +#endif + +/**************************************************************************//** + * @brief + * Determine if the currently selected PCNTn clock used is external or LFBCLK. + * + * @param[in] instance + * PCNT instance number to get currently selected clock source for. + * + * @return + * @li true - selected clock is external clock. + * @li false - selected clock is LFBCLK. + *****************************************************************************/ +bool CMU_PCNTClockExternalGet(unsigned int instance) +{ + uint32_t setting; + + switch (instance) { +#if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK) + case 0: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK) + case 1: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0; + break; + +#if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK) + case 2: + setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0; + break; +#endif +#endif +#endif + + default: + setting = 0; + break; + } + return setting > 0UL ? true : false; +} + +/**************************************************************************//** + * @brief + * Select the PCNTn clock. + * + * @param[in] instance + * PCNT instance number to set selected clock source for. + * + * @param[in] external + * Set to true to select the external clock, false to select LFBCLK. + *****************************************************************************/ +void CMU_PCNTClockExternalSet(unsigned int instance, bool external) +{ +#if defined(PCNT_PRESENT) + uint32_t setting = 0; + + EFM_ASSERT(instance < (unsigned)PCNT_COUNT); + + if (external) { + setting = 1; + } + + BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2U) + 1U, setting); + +#else + (void)instance; /* An unused parameter */ + (void)external; /* An unused parameter */ +#endif +} + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Get USHFRCO band in use. + * + * @return + * USHFRCO band in use. + ******************************************************************************/ +CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void) +{ + return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF + & _CMU_USHFRCOCONF_BAND_MASK) + >> _CMU_USHFRCOCONF_BAND_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get USHFRCO frequency. + * + * @return + * USHFRCO frequency. + ******************************************************************************/ +uint32_t CMU_USHFRCOFreqGet(void) +{ + return ushfrcoFreq; +} +#endif + +#if defined(_CMU_USHFRCOCONF_BAND_MASK) +/***************************************************************************//** + * @brief + * Set the USHFRCO band to use. + * + * @param[in] band + * USHFRCO band to activate. + ******************************************************************************/ +void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band) +{ + uint32_t tuning; + uint32_t fineTuning; + + /* Cannot switch band if USHFRCO is already selected as HF clock. */ + EFM_ASSERT(CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_USHFRCODIV2); + + /* Read tuning value from calibration table. */ + switch (band) { + case cmuUSHFRCOBand_24MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT; + ushfrcoFreq = 24000000UL; + break; + + case cmuUSHFRCOBand_48MHz: + tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT; + fineTuning = (DEVINFO->USHFRCOCAL0 + & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK) + >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT; + /* Enable the clock divider before switching the band from 24 to 48 MHz */ + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0); + ushfrcoFreq = 48000000UL; + break; + + default: + EFM_ASSERT(false); + return; + } + + /* Set band and tuning. */ + CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK) + | (band << _CMU_USHFRCOCONF_BAND_SHIFT); + CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK) + | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT); + CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK) + | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT); + + /* Disable the clock divider after switching the band from 48 to 24 MHz. */ + if (band == cmuUSHFRCOBand_24MHz) { + BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1); + } +} +#endif + +#endif // defined(_SILICON_LABS_32B_SERIES_2) +/** @} (end addtogroup cmu) */ +#endif /* defined(CMU_PRESENT) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_core.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_core.c index 571ec9b..4c4c434 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_core.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_core.c @@ -1,1028 +1,1028 @@ -/***************************************************************************//** - * @file - * @brief Core interrupt handling API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_core.h" -#include "sl_assert.h" - -/* *INDENT-OFF* */ -// ***************************************************************************** -/// @addtogroup core CORE - Core Interrupt -/// -///@n @section core_intro Introduction -/// -/// CORE interrupt API provides a simple and safe means -/// to disable and enable interrupts to protect sections of code. -/// -/// This is often referred to as "critical sections". This module provides -/// support for three types of critical sections, each with different interrupt -/// blocking capabilities. -/// -/// @li CRITICAL section: Inside a critical section, all interrupts are -/// disabled (except for fault handlers). The PRIMASK register is always used for -/// interrupt disable/enable. -/// @li ATOMIC section: This type of section is configurable and the default -/// method is to use PRIMASK. With BASEPRI configuration, interrupts with priority -/// equal to or lower than a given configurable level are disabled. The interrupt -/// disable priority level is defined at compile time. The BASEPRI register is not -/// available for all architectures. -/// @li NVIC mask section: Disable NVIC (external interrupts) on an -/// individual manner. -/// -/// em_core also has an API for manipulating RAM-based interrupt vector tables. -/// -///@n @section core_conf Compile-time Configuration -/// -/// The following #defines are used to configure em_core: -/// @code{.c} -/// // The interrupt priority level used inside ATOMIC sections. -/// #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 -/// -/// // A method used for interrupt disable/enable within ATOMIC sections. -/// #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK -/// @endcode -/// -/// If the default values do not support your needs, they can be overridden -/// by supplying -D compiler flags on the compiler command line or by collecting -/// all macro redefinitions in a file named @em emlib_config.h and then supplying -/// -DEMLIB_USER_CONFIG on a compiler command line. -/// -/// @note The default emlib configuration for ATOMIC section interrupt disable -/// method is using PRIMASK, i.e., ATOMIC sections are implemented as -/// CRITICAL sections. -/// -/// @note Due to architectural limitations Cortex-M0+ devices do not support -/// ATOMIC type critical sections using the BASEPRI register. On M0+ -/// devices ATOMIC section helper macros are available but they are -/// implemented as CRITICAL sections using PRIMASK register. -/// -///@n @section core_macro_api Macro API -/// -/// The primary em_core API is the macro API. Macro API will map to correct -/// CORE functions according to the selected @ref CORE_ATOMIC_METHOD and similar -/// configurations (the full CORE API is of course also available). -/// The most useful macros are as follows: -/// -/// @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_ATOMIC() @n -/// @ref CORE_EXIT_ATOMIC()@n -/// Used together to implement an ATOMIC section. -/// @code{.c} -/// { -/// CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to -/// // atomic section entry. -/// -/// CORE_ENTER_ATOMIC(); // Enter atomic section. -/// -/// ... -/// ... your code goes here ... -/// ... -/// -/// CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. -/// } -/// @endcode -/// -/// @n @ref CORE_ATOMIC_SECTION(yourcode)@n -/// A concatenation of all three macros above. -/// @code{.c} -/// { -/// CORE_ATOMIC_SECTION( -/// ... -/// ... your code goes here ... -/// ... -/// ) -/// } -/// @endcode -/// -/// @n @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_CRITICAL() @n -/// @ref CORE_EXIT_CRITICAL() @n @ref CORE_CRITICAL_SECTION(yourcode)@n -/// These macros implement CRITICAL sections in a similar fashion as described -/// above for ATOMIC sections. -/// -/// @n @ref CORE_DECLARE_NVIC_STATE @n @ref CORE_ENTER_NVIC() @n -/// @ref CORE_EXIT_NVIC() @n @ref CORE_NVIC_SECTION(yourcode)@n -/// These macros implement NVIC mask sections in a similar fashion as described -/// above for ATOMIC sections. See @ref core_examples for an example. -/// -/// Refer to @em Macros or Macro Definition Documentation below for a -/// full list of macros. -/// -///@n @section core_reimplementation API reimplementation -/// -/// Most of the functions in the API are implemented as weak functions. This means -/// that it is easy to reimplement when special needs arise. Shown below is a -/// reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: -/// @code{.c} -/// CORE_irqState_t CORE_EnterCritical(void) -/// { -/// vPortEnterCritical(); -/// return 0; -/// } -/// -/// void CORE_ExitCritical(CORE_irqState_t irqState) -/// { -/// (void)irqState; -/// vPortExitCritical(); -/// } -/// @endcode -/// Also note that CORE_Enter/ExitCritical() are not implemented as inline -/// functions. As a result, reimplementations will be possible even when original -/// implementations are inside a linked library. -/// -/// Some RTOSes must be notified on interrupt handler entry and exit. Macros -/// @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable -/// placeholders for inserting such code. Insert these macros in all your -/// interrupt handlers and then override the default macro implementations. -/// This is an example if uC/OS is used: -/// @code{.c} -/// // In emlib_config.h: -/// -/// #define CORE_INTERRUPT_ENTRY() OSIntEnter() -/// #define CORE_INTERRUPT_EXIT() OSIntExit() -/// @endcode -/// -///@n @section core_vector_tables Interrupt vector tables -/// -/// When using RAM based interrupt vector tables it is the user's responsibility -/// to allocate the table space correctly. The tables must be aligned as specified -/// in the CPU reference manual. -/// -/// @ref CORE_InitNvicVectorTable()@n -/// Initialize a RAM based vector table by copying table entries from a source -/// vector table to a target table. VTOR is set to the address of the target -/// vector table. -/// -/// @n @ref CORE_GetNvicRamTableHandler() @n @ref CORE_SetNvicRamTableHandler()@n -/// Use these functions to get or set the interrupt handler for a specific IRQn. -/// They both use the interrupt vector table defined by the current -/// VTOR register value. -/// -///@n @section core_max_timing Maximum Interrupt Disabled Time -/// -/// The maximum time spent (in cycles) in critical and atomic sections can be -/// measured for performance and interrupt latency analysis. -/// To enable the timings, use the SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING -/// configuration option. When enabled, the functions -/// @n @ref CORE_get_max_time_critical_section() -/// @n @ref CORE_get_max_time_atomic_section() @n -/// can be used to get the max timings since startup. -/// -///@n @section core_examples Examples -/// -/// Implement an NVIC critical section: -/// @code{.c} -/// { -/// CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask -/// -/// // Set mask bits for IRQs to block in the NVIC critical section. -/// // In many cases, you can create the disable mask once upon application -/// // startup and use the mask globally throughout the application lifetime. -/// CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); -/// CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); -/// -/// // Enter NVIC critical section with the disable mask -/// CORE_NVIC_SECTION(&mask, -/// ... -/// ... your code goes here ... -/// ... -/// ) -/// } -/// @endcode -/// -///@n @section core_porting Porting from em_int -/// -/// Existing code using INT_Enable() and INT_Disable() must be ported to the -/// em_core API. While em_int used, a global counter to store the interrupt state, -/// em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to -/// be replaced with a declaration of the interrupt state variable before entering -/// the critical section. -/// -/// Since the state variable is in local scope, the critical section exit -/// needs to occur within the scope of the variable. If multiple nested critical -/// sections are used, each needs to have its own state variable in its own scope. -/// -/// In many cases, completely disabling all interrupts using CRITICAL sections -/// might be more heavy-handed than needed. When porting, consider whether other -/// types of sections, such as ATOMIC or NVIC mask, can be used to only disable -/// a subset of the interrupts. -/// -/// Replacing em_int calls with em_core function calls: -/// @code{.c} -/// void func(void) -/// { -/// // INT_Disable(); -/// CORE_DECLARE_IRQ_STATE; -/// CORE_ENTER_ATOMIC(); -/// . -/// . -/// . -/// // INT_Enable(); -/// CORE_EXIT_ATOMIC(); -/// } -/// @endcode -/// @{ -// ***************************************************************************** -/* *INDENT-ON* */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#if !defined(CORE_INTERRUPT_ENTRY) -// Some RTOSes must be notified on interrupt entry (and exit). -// Use this macro at the start of all your interrupt handlers. -// Reimplement the macro in emlib_config.h to suit the needs of your RTOS. -/** Placeholder for optional interrupt handler entry code. This might be needed - * when working with an RTOS. */ -#define CORE_INTERRUPT_ENTRY() -#endif - -#if !defined(CORE_INTERRUPT_EXIT) -/** Placeholder for optional interrupt handler exit code. This might be needed - * when working with an RTOS. */ -#define CORE_INTERRUPT_EXIT() -#endif - -// Compile time sanity check. -#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \ - && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI) -#error "em_core: Undefined ATOMIC IRQ handling strategy." -#endif - -/******************************************************************************* - ************************** STRUCTS **************************************** - ******************************************************************************/ -/** A Cycle Counter Instance. */ -typedef struct { - uint32_t start; /*!< Cycle counter at start of recording. */ - uint32_t cycles; /*!< Cycles elapsed in last recording. */ - uint32_t max; /*!< Max recorded cycles since last reset or init. */ -} dwt_cycle_counter_handle_t; - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -// cycle counter to record atomic sections -dwt_cycle_counter_handle_t atomic_cycle_counter = { 0 }; -// cycle counter to record critical sections -dwt_cycle_counter_handle_t critical_cycle_counter = { 0 }; -#endif - -/** @endcond */ - -/******************************************************************************* - *************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -static void cycle_counter_start(dwt_cycle_counter_handle_t *handle); -static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle); -#endif - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable interrupts. - * - * Disable all interrupts by setting PRIMASK. - * (Fault exception handlers will still be enabled). - ******************************************************************************/ -SL_WEAK void CORE_CriticalDisableIrq(void) -{ - __disable_irq(); -} - -/***************************************************************************//** - * @brief - * Enable interrupts. - * - * Enable interrupts by clearing PRIMASK. - ******************************************************************************/ -SL_WEAK void CORE_CriticalEnableIrq(void) -{ - __enable_irq(); -} - -/***************************************************************************//** - * @brief - * Enter a CRITICAL section. - * - * When a CRITICAL section is entered, all interrupts (except fault handlers) - * are disabled. - * - * @return - * The value of PRIMASK register prior to the CRITICAL section entry. - ******************************************************************************/ -SL_WEAK CORE_irqState_t CORE_EnterCritical(void) -{ - CORE_irqState_t irqState = __get_PRIMASK(); - __disable_irq(); - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&critical_cycle_counter); -#endif - } - return irqState; -} - -/***************************************************************************//** - * @brief - * Exit a CRITICAL section. - * - * @param[in] irqState - * The interrupt priority blocking level to restore to PRIMASK when exiting - * the CRITICAL section. This value is usually the one returned by a prior - * call to @ref CORE_EnterCritical(). - ******************************************************************************/ -SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) -{ - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&critical_cycle_counter); -#endif - __enable_irq(); - } -} - -/***************************************************************************//** - * @brief - * Brief interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @note - * Usually used within a CRITICAL section. - ******************************************************************************/ -SL_WEAK void CORE_YieldCritical(void) -{ - if ((__get_PRIMASK() & 1U) != 0U) { - __enable_irq(); - __ISB(); - __disable_irq(); - } -} - -/***************************************************************************//** - * @brief - * Disable interrupts. - * - * Disable interrupts with a priority lower or equal to - * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register - * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_CriticalDisableIrq(). - ******************************************************************************/ -SL_WEAK void CORE_AtomicDisableIrq(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8UL - __NVIC_PRIO_BITS)); -#else - __disable_irq(); -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enable interrupts. - * - * Enable interrupts by setting core BASEPRI register to 0. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK - * is set (CPU is inside a CRITICAL section), interrupts will still be - * disabled after calling this function. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_CriticalEnableIrq(). - ******************************************************************************/ -SL_WEAK void CORE_AtomicEnableIrq(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - __set_BASEPRI(0); -#else - __enable_irq(); -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enter an ATOMIC section. - * - * When an ATOMIC section is entered, interrupts with priority lower or equal - * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_EnterCritical(). - * - * @return - * The value of BASEPRI register prior to ATOMIC section entry. - ******************************************************************************/ -SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - CORE_irqState_t irqState = __get_BASEPRI(); - __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS)); - if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) - != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&atomic_cycle_counter); -#endif - } - return irqState; -#else - CORE_irqState_t irqState = __get_PRIMASK(); - __disable_irq(); - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_start(&atomic_cycle_counter); -#endif - } - return irqState; -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Exit an ATOMIC section. - * - * @param[in] irqState - * The interrupt priority blocking level to restore to BASEPRI when exiting - * the ATOMIC section. This value is usually the one returned by a prior - * call to @ref CORE_EnterAtomic(). - * - * @note - * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_ExitCritical(). - ******************************************************************************/ -SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) - != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&atomic_cycle_counter); -#endif - } - __set_BASEPRI(irqState); -#else - if (irqState == 0U) { -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - cycle_counter_stop(&atomic_cycle_counter); -#endif - __enable_irq(); - } -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Brief interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @note - * Usully used within an ATOMIC section. - * - * @note - * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this - * function is identical to @ref CORE_YieldCritical(). - ******************************************************************************/ -SL_WEAK void CORE_YieldAtomic(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - CORE_irqState_t basepri = __get_BASEPRI(); - if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { - __set_BASEPRI(0); - __ISB(); - __set_BASEPRI(basepri); - } -#else - if ((__get_PRIMASK() & 1U) != 0U) { - __enable_irq(); - __ISB(); - __disable_irq(); - } -#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) -} - -/***************************************************************************//** - * @brief - * Enter a NVIC mask section. - * - * When a NVIC mask section is entered, specified NVIC interrupts - * are disabled. - * - * @param[out] nvicState - * Return NVIC interrupts enable mask prior to section entry. - * - * @param[in] disable - * A mask specifying which NVIC interrupts to disable within the section. - ******************************************************************************/ -void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, - const CORE_nvicMask_t *disable) -{ - CORE_CRITICAL_SECTION( - *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; - ) -} - -/***************************************************************************//** - * @brief - * Disable NVIC interrupts. - * - * @param[in] disable - * A mask specifying which NVIC interrupts to disable. - ******************************************************************************/ -void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) -{ - CORE_CRITICAL_SECTION( - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; - ) -} - -/***************************************************************************//** - * @brief - * Set current NVIC interrupt enable mask. - * - * @param[out] enable - * A mask specifying which NVIC interrupts are currently enabled. - ******************************************************************************/ -void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) -{ - CORE_CRITICAL_SECTION( - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; - ) -} - -/***************************************************************************//** - * @brief - * Brief NVIC interrupt enable/disable sequence to allow handling of - * pending interrupts. - * - * @param[in] enable - * A mask specifying which NVIC interrupts to briefly enable. - * - * @note - * Usually used within an NVIC mask section. - ******************************************************************************/ -void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) -{ - CORE_nvicMask_t nvicMask; - - // Get current NVIC enable mask. - CORE_CRITICAL_SECTION( - nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) - - // Make a mask with bits set for those interrupts that are currently - // disabled but are set in the enable mask. -#if (CORE_NVIC_REG_WORDS == 1) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - - if (nvicMask.a[0] != 0) { -#elif (CORE_NVIC_REG_WORDS == 2) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[1] &= enable->a[1]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; - - if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { -#elif (CORE_NVIC_REG_WORDS == 3) - nvicMask.a[0] &= enable->a[0]; - nvicMask.a[1] &= enable->a[1]; - nvicMask.a[2] &= enable->a[2]; - nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; - nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; - nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; - - if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U) || (nvicMask.a[2] != 0U)) { -#endif - - // Enable previously disabled interrupts. - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; - - // Disable those interrupts again. - *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; - } -} - -/***************************************************************************//** - * @brief - * Utility function to set an IRQn bit in a NVIC enable/disable mask. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in,out] mask - * The mask to set the interrupt bit in. - ******************************************************************************/ -void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) -{ - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); -} - -/***************************************************************************//** - * @brief - * Utility function to clear an IRQn bit in a NVIC enable/disable mask. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in,out] mask - * The mask to clear the interrupt bit in. - ******************************************************************************/ -void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) -{ - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); -} - -/***************************************************************************//** - * @brief - * Check whether the current CPU operation mode is handler mode. - * - * @return - * True if the CPU is in handler mode (currently executing an interrupt handler). - * @n False if the CPU is in thread mode. - ******************************************************************************/ -SL_WEAK bool CORE_InIrqContext(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; -} - -/***************************************************************************//** - * @brief - * Check if a specific interrupt is disabled or blocked. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt to check. - * - * @return - * True if the interrupt is disabled or blocked. - ******************************************************************************/ -SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) -{ - uint32_t irqPri, activeIrq; - -#if (__CORTEX_M >= 3) - uint32_t basepri; - - EFM_ASSERT((irqN >= MemoryManagement_IRQn) - && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); -#else - EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); -#endif - - if ((__get_PRIMASK() & 1U) != 0U) { - return true; // All IRQs are disabled. - } - - if (CORE_NvicIRQDisabled(irqN)) { - return true; // The IRQ in question is disabled. - } - - irqPri = NVIC_GetPriority(irqN); -#if (__CORTEX_M >= 3) - basepri = __get_BASEPRI(); - if ((basepri != 0U) - && (irqPri >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { - return true; // The IRQ in question has too low - } // priority vs. BASEPRI. -#endif - - // Check if already in an interrupt handler. If so, an interrupt with a - // higher priority (lower priority value) can preempt. - activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; - if (activeIrq != 0U) { - if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { - return true; // The IRQ in question has too low - } // priority vs. current active IRQ - } - - return false; -} - -/***************************************************************************//** - * @brief - * Check if interrupts are disabled. - * - * @return - * True if interrupts are disabled. - ******************************************************************************/ -SL_WEAK bool CORE_IrqIsDisabled(void) -{ -#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK) - return (__get_PRIMASK() & 1U) == 1U; - -#elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) - return ((__get_PRIMASK() & 1U) == 1U) - || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL - << (8U - __NVIC_PRIO_BITS))); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current NVIC enable mask state. - * - * @param[out] mask - * The current NVIC enable mask. - ******************************************************************************/ -void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) -{ - CORE_CRITICAL_SECTION( - *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) -} - -/***************************************************************************//** - * @brief - * Get NVIC disable state for a given mask. - * - * @param[in] mask - * An NVIC mask to check. - * - * @return - * True if all NVIC interrupt mask bits are clear. - ******************************************************************************/ -bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) -{ - CORE_nvicMask_t nvicMask; - - CORE_CRITICAL_SECTION( - nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - ) - -#if (CORE_NVIC_REG_WORDS == 1) - return (mask->a[0] & nvicMask.a[0]) == 0U; - -#elif (CORE_NVIC_REG_WORDS == 2) - return ((mask->a[0] & nvicMask.a[0]) == 0U) - && ((mask->a[1] & nvicMask.a[1]) == 0U); - -#elif (CORE_NVIC_REG_WORDS == 3) - return ((mask->a[0] & nvicMask.a[0]) == 0U) - && ((mask->a[1] & nvicMask.a[1]) == 0U) - && ((mask->a[2] & nvicMask.a[2]) == 0U); -#endif -} - -/***************************************************************************//** - * @brief - * Check if an NVIC interrupt is disabled. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt to check. - * - * @return - * True if the interrupt is disabled. - ******************************************************************************/ -bool CORE_NvicIRQDisabled(IRQn_Type irqN) -{ - CORE_nvicMask_t *mask; - - EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); - mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); - return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) - == 0UL; -} - -/***************************************************************************//** - * @brief - * Utility function to get the handler for a specific interrupt. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @return - * The handler address. - * - * @note - * Uses the interrupt vector table defined by the current VTOR register value. - ******************************************************************************/ -void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) -{ - EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); - return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); -} - -/***************************************************************************//** - * @brief - * Utility function to set the handler for a specific interrupt. - * - * @param[in] irqN - * The IRQn_Type enumerator for the interrupt. - * - * @param[in] handler - * The handler address. - * - * @note - * Uses the interrupt vector table defined by the current VTOR register value. - ******************************************************************************/ -void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) -{ - EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); - ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); -} - -/***************************************************************************//** - * @brief - * Initialize an interrupt vector table by copying table entries from a - * source to a target table. - * - * @note This function will set a new VTOR register value. - * - * @param[in] sourceTable - * The address of the source vector table. - * - * @param[in] sourceSize - * A number of entries in the source vector table. - * - * @param[in] targetTable - * The address of the target (new) vector table. - * - * @param[in] targetSize - * A number of entries in the target vector table. - * - * @param[in] defaultHandler - * An address of the interrupt handler used for target entries for which where there - * is no corresponding source entry (i.e., the target table is larger than the source - * table). - * - * @param[in] overwriteActive - * When true, a target table entry is always overwritten with the - * corresponding source entry. If false, a target table entry is only - * overwritten if it is zero. This makes it possible for an application - * to partly initialize a target table before passing it to this function. - * - ******************************************************************************/ -void CORE_InitNvicVectorTable(uint32_t *sourceTable, - uint32_t sourceSize, - uint32_t *targetTable, - uint32_t targetSize, - void *defaultHandler, - bool overwriteActive) -{ - uint32_t i; - - // ASSERT on non SRAM-based target table. - EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) - && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); - - // ASSERT if misaligned with respect to the VTOR register implementation. -#if defined(SCB_VTOR_TBLBASE_Msk) - EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk - | SCB_VTOR_TBLBASE_Msk)) == 0U); -#else - EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); -#endif - - // ASSERT if misaligned with respect to the vector table size. - // The vector table address must be aligned at its size rounded up to nearest 2^n. - EFM_ASSERT(((uint32_t)targetTable - & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) - == 0UL); - - for (i = 0; i < targetSize; i++) { - if (overwriteActive) { // Overwrite target entries. - if (i < sourceSize) { // targetSize <= sourceSize - targetTable[i] = sourceTable[i]; - } else { // targetSize > sourceSize - targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); - } - } else { // Overwrite target entries which are 0. - if (i < sourceSize) { // targetSize <= sourceSize - if (targetTable[i] == 0U) { - targetTable[i] = sourceTable[i]; - } - } else { // targetSize > sourceSize - if (targetTable[i] == 0U) { - targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); - } - } - } - } - SCB->VTOR = (uint32_t)targetTable; -} - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) || defined(DOXYGEN) -/***************************************************************************//** - * @brief - * Start a recording. - * - * @param[in] handle - * Pointer to initialized counter handle. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -static void cycle_counter_start(dwt_cycle_counter_handle_t *handle) -{ - handle->start = DWT->CYCCNT; -} - -/***************************************************************************//** - * @brief - * Stop a recording. - * - * @param[in] handle - * Pointer to initialized counter handle. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle) -{ - handle->cycles = DWT->CYCCNT - handle->start; - - if (handle->cycles > handle->max) { - handle->max = handle->cycles; - } -} - -/***************************************************************************//** - * @brief - * Returns the max time spent in critical section. - * - * @return - * The max time spent in critical section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -uint32_t CORE_get_max_time_critical_section(void) -{ - return critical_cycle_counter.max; -} - -/***************************************************************************//** - * @brief - * Returns the max time spent in atomic section. - * - * @return - * The max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -uint32_t CORE_get_max_time_atomic_section(void) -{ - return atomic_cycle_counter.max; -} - -/***************************************************************************//** - * @brief - * Clears the max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -void CORE_clear_max_time_critical_section(void) -{ - critical_cycle_counter.max = 0; -} - -/***************************************************************************//** - * @brief - * Clears the max time spent in atomic section. - * - * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. - ******************************************************************************/ -void CORE_clear_max_time_atomic_section(void) -{ - atomic_cycle_counter.max = 0; -} -#endif //(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - -/** @} (end addtogroup core) */ +/***************************************************************************//** + * @file + * @brief Core interrupt handling API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_core.h" +#include "sl_assert.h" + +/* *INDENT-OFF* */ +// ***************************************************************************** +/// @addtogroup core CORE - Core Interrupt +/// +///@n @section core_intro Introduction +/// +/// CORE interrupt API provides a simple and safe means +/// to disable and enable interrupts to protect sections of code. +/// +/// This is often referred to as "critical sections". This module provides +/// support for three types of critical sections, each with different interrupt +/// blocking capabilities. +/// +/// @li CRITICAL section: Inside a critical section, all interrupts are +/// disabled (except for fault handlers). The PRIMASK register is always used for +/// interrupt disable/enable. +/// @li ATOMIC section: This type of section is configurable and the default +/// method is to use PRIMASK. With BASEPRI configuration, interrupts with priority +/// equal to or lower than a given configurable level are disabled. The interrupt +/// disable priority level is defined at compile time. The BASEPRI register is not +/// available for all architectures. +/// @li NVIC mask section: Disable NVIC (external interrupts) on an +/// individual manner. +/// +/// em_core also has an API for manipulating RAM-based interrupt vector tables. +/// +///@n @section core_conf Compile-time Configuration +/// +/// The following #defines are used to configure em_core: +/// @code{.c} +/// // The interrupt priority level used inside ATOMIC sections. +/// #define CORE_ATOMIC_BASE_PRIORITY_LEVEL 3 +/// +/// // A method used for interrupt disable/enable within ATOMIC sections. +/// #define CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK +/// @endcode +/// +/// If the default values do not support your needs, they can be overridden +/// by supplying -D compiler flags on the compiler command line or by collecting +/// all macro redefinitions in a file named @em emlib_config.h and then supplying +/// -DEMLIB_USER_CONFIG on a compiler command line. +/// +/// @note The default emlib configuration for ATOMIC section interrupt disable +/// method is using PRIMASK, i.e., ATOMIC sections are implemented as +/// CRITICAL sections. +/// +/// @note Due to architectural limitations Cortex-M0+ devices do not support +/// ATOMIC type critical sections using the BASEPRI register. On M0+ +/// devices ATOMIC section helper macros are available but they are +/// implemented as CRITICAL sections using PRIMASK register. +/// +///@n @section core_macro_api Macro API +/// +/// The primary em_core API is the macro API. Macro API will map to correct +/// CORE functions according to the selected @ref CORE_ATOMIC_METHOD and similar +/// configurations (the full CORE API is of course also available). +/// The most useful macros are as follows: +/// +/// @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_ATOMIC() @n +/// @ref CORE_EXIT_ATOMIC()@n +/// Used together to implement an ATOMIC section. +/// @code{.c} +/// { +/// CORE_DECLARE_IRQ_STATE; // Storage for saving IRQ state prior to +/// // atomic section entry. +/// +/// CORE_ENTER_ATOMIC(); // Enter atomic section. +/// +/// ... +/// ... your code goes here ... +/// ... +/// +/// CORE_EXIT_ATOMIC(); // Exit atomic section, IRQ state is restored. +/// } +/// @endcode +/// +/// @n @ref CORE_ATOMIC_SECTION(yourcode)@n +/// A concatenation of all three macros above. +/// @code{.c} +/// { +/// CORE_ATOMIC_SECTION( +/// ... +/// ... your code goes here ... +/// ... +/// ) +/// } +/// @endcode +/// +/// @n @ref CORE_DECLARE_IRQ_STATE @n @ref CORE_ENTER_CRITICAL() @n +/// @ref CORE_EXIT_CRITICAL() @n @ref CORE_CRITICAL_SECTION(yourcode)@n +/// These macros implement CRITICAL sections in a similar fashion as described +/// above for ATOMIC sections. +/// +/// @n @ref CORE_DECLARE_NVIC_STATE @n @ref CORE_ENTER_NVIC() @n +/// @ref CORE_EXIT_NVIC() @n @ref CORE_NVIC_SECTION(yourcode)@n +/// These macros implement NVIC mask sections in a similar fashion as described +/// above for ATOMIC sections. See @ref core_examples for an example. +/// +/// Refer to @em Macros or Macro Definition Documentation below for a +/// full list of macros. +/// +///@n @section core_reimplementation API reimplementation +/// +/// Most of the functions in the API are implemented as weak functions. This means +/// that it is easy to reimplement when special needs arise. Shown below is a +/// reimplementation of CRITICAL sections suitable if FreeRTOS OS is used: +/// @code{.c} +/// CORE_irqState_t CORE_EnterCritical(void) +/// { +/// vPortEnterCritical(); +/// return 0; +/// } +/// +/// void CORE_ExitCritical(CORE_irqState_t irqState) +/// { +/// (void)irqState; +/// vPortExitCritical(); +/// } +/// @endcode +/// Also note that CORE_Enter/ExitCritical() are not implemented as inline +/// functions. As a result, reimplementations will be possible even when original +/// implementations are inside a linked library. +/// +/// Some RTOSes must be notified on interrupt handler entry and exit. Macros +/// @ref CORE_INTERRUPT_ENTRY() and @ref CORE_INTERRUPT_EXIT() are suitable +/// placeholders for inserting such code. Insert these macros in all your +/// interrupt handlers and then override the default macro implementations. +/// This is an example if uC/OS is used: +/// @code{.c} +/// // In emlib_config.h: +/// +/// #define CORE_INTERRUPT_ENTRY() OSIntEnter() +/// #define CORE_INTERRUPT_EXIT() OSIntExit() +/// @endcode +/// +///@n @section core_vector_tables Interrupt vector tables +/// +/// When using RAM based interrupt vector tables it is the user's responsibility +/// to allocate the table space correctly. The tables must be aligned as specified +/// in the CPU reference manual. +/// +/// @ref CORE_InitNvicVectorTable()@n +/// Initialize a RAM based vector table by copying table entries from a source +/// vector table to a target table. VTOR is set to the address of the target +/// vector table. +/// +/// @n @ref CORE_GetNvicRamTableHandler() @n @ref CORE_SetNvicRamTableHandler()@n +/// Use these functions to get or set the interrupt handler for a specific IRQn. +/// They both use the interrupt vector table defined by the current +/// VTOR register value. +/// +///@n @section core_max_timing Maximum Interrupt Disabled Time +/// +/// The maximum time spent (in cycles) in critical and atomic sections can be +/// measured for performance and interrupt latency analysis. +/// To enable the timings, use the SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING +/// configuration option. When enabled, the functions +/// @n @ref CORE_get_max_time_critical_section() +/// @n @ref CORE_get_max_time_atomic_section() @n +/// can be used to get the max timings since startup. +/// +///@n @section core_examples Examples +/// +/// Implement an NVIC critical section: +/// @code{.c} +/// { +/// CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask +/// +/// // Set mask bits for IRQs to block in the NVIC critical section. +/// // In many cases, you can create the disable mask once upon application +/// // startup and use the mask globally throughout the application lifetime. +/// CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask); +/// CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask); +/// +/// // Enter NVIC critical section with the disable mask +/// CORE_NVIC_SECTION(&mask, +/// ... +/// ... your code goes here ... +/// ... +/// ) +/// } +/// @endcode +/// +///@n @section core_porting Porting from em_int +/// +/// Existing code using INT_Enable() and INT_Disable() must be ported to the +/// em_core API. While em_int used, a global counter to store the interrupt state, +/// em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to +/// be replaced with a declaration of the interrupt state variable before entering +/// the critical section. +/// +/// Since the state variable is in local scope, the critical section exit +/// needs to occur within the scope of the variable. If multiple nested critical +/// sections are used, each needs to have its own state variable in its own scope. +/// +/// In many cases, completely disabling all interrupts using CRITICAL sections +/// might be more heavy-handed than needed. When porting, consider whether other +/// types of sections, such as ATOMIC or NVIC mask, can be used to only disable +/// a subset of the interrupts. +/// +/// Replacing em_int calls with em_core function calls: +/// @code{.c} +/// void func(void) +/// { +/// // INT_Disable(); +/// CORE_DECLARE_IRQ_STATE; +/// CORE_ENTER_ATOMIC(); +/// . +/// . +/// . +/// // INT_Enable(); +/// CORE_EXIT_ATOMIC(); +/// } +/// @endcode +/// @{ +// ***************************************************************************** +/* *INDENT-ON* */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#if !defined(CORE_INTERRUPT_ENTRY) +// Some RTOSes must be notified on interrupt entry (and exit). +// Use this macro at the start of all your interrupt handlers. +// Reimplement the macro in emlib_config.h to suit the needs of your RTOS. +/** Placeholder for optional interrupt handler entry code. This might be needed + * when working with an RTOS. */ +#define CORE_INTERRUPT_ENTRY() +#endif + +#if !defined(CORE_INTERRUPT_EXIT) +/** Placeholder for optional interrupt handler exit code. This might be needed + * when working with an RTOS. */ +#define CORE_INTERRUPT_EXIT() +#endif + +// Compile time sanity check. +#if (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_PRIMASK) \ + && (CORE_ATOMIC_METHOD != CORE_ATOMIC_METHOD_BASEPRI) +#error "em_core: Undefined ATOMIC IRQ handling strategy." +#endif + +/******************************************************************************* + ************************** STRUCTS **************************************** + ******************************************************************************/ +/** A Cycle Counter Instance. */ +typedef struct { + uint32_t start; /*!< Cycle counter at start of recording. */ + uint32_t cycles; /*!< Cycles elapsed in last recording. */ + uint32_t max; /*!< Max recorded cycles since last reset or init. */ +} dwt_cycle_counter_handle_t; + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +// cycle counter to record atomic sections +dwt_cycle_counter_handle_t atomic_cycle_counter = { 0 }; +// cycle counter to record critical sections +dwt_cycle_counter_handle_t critical_cycle_counter = { 0 }; +#endif + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle); +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle); +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable all interrupts by setting PRIMASK. + * (Fault exception handlers will still be enabled). + ******************************************************************************/ +SL_WEAK void CORE_CriticalDisableIrq(void) +{ + __disable_irq(); +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by clearing PRIMASK. + ******************************************************************************/ +SL_WEAK void CORE_CriticalEnableIrq(void) +{ + __enable_irq(); +} + +/***************************************************************************//** + * @brief + * Enter a CRITICAL section. + * + * When a CRITICAL section is entered, all interrupts (except fault handlers) + * are disabled. + * + * @return + * The value of PRIMASK register prior to the CRITICAL section entry. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterCritical(void) +{ + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&critical_cycle_counter); +#endif + } + return irqState; +} + +/***************************************************************************//** + * @brief + * Exit a CRITICAL section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to PRIMASK when exiting + * the CRITICAL section. This value is usually the one returned by a prior + * call to @ref CORE_EnterCritical(). + ******************************************************************************/ +SL_WEAK void CORE_ExitCritical(CORE_irqState_t irqState) +{ + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&critical_cycle_counter); +#endif + __enable_irq(); + } +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usually used within a CRITICAL section. + ******************************************************************************/ +SL_WEAK void CORE_YieldCritical(void) +{ + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +} + +/***************************************************************************//** + * @brief + * Disable interrupts. + * + * Disable interrupts with a priority lower or equal to + * @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register + * to CORE_ATOMIC_BASE_PRIORITY_LEVEL. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalDisableIrq(). + ******************************************************************************/ +SL_WEAK void CORE_AtomicDisableIrq(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8UL - __NVIC_PRIO_BITS)); +#else + __disable_irq(); +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enable interrupts. + * + * Enable interrupts by setting core BASEPRI register to 0. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_BASEPRI and PRIMASK + * is set (CPU is inside a CRITICAL section), interrupts will still be + * disabled after calling this function. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_CriticalEnableIrq(). + ******************************************************************************/ +SL_WEAK void CORE_AtomicEnableIrq(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + __set_BASEPRI(0); +#else + __enable_irq(); +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enter an ATOMIC section. + * + * When an ATOMIC section is entered, interrupts with priority lower or equal + * to @ref CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_EnterCritical(). + * + * @return + * The value of BASEPRI register prior to ATOMIC section entry. + ******************************************************************************/ +SL_WEAK CORE_irqState_t CORE_EnterAtomic(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + CORE_irqState_t irqState = __get_BASEPRI(); + __set_BASEPRI(CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS)); + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&atomic_cycle_counter); +#endif + } + return irqState; +#else + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_start(&atomic_cycle_counter); +#endif + } + return irqState; +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Exit an ATOMIC section. + * + * @param[in] irqState + * The interrupt priority blocking level to restore to BASEPRI when exiting + * the ATOMIC section. This value is usually the one returned by a prior + * call to @ref CORE_EnterAtomic(). + * + * @note + * If @ref CORE_ATOMIC_METHOD is set to @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_ExitCritical(). + ******************************************************************************/ +SL_WEAK void CORE_ExitAtomic(CORE_irqState_t irqState) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + if ((irqState & (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) + != (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&atomic_cycle_counter); +#endif + } + __set_BASEPRI(irqState); +#else + if (irqState == 0U) { +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + cycle_counter_stop(&atomic_cycle_counter); +#endif + __enable_irq(); + } +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Brief interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @note + * Usully used within an ATOMIC section. + * + * @note + * If @ref CORE_ATOMIC_METHOD is @ref CORE_ATOMIC_METHOD_PRIMASK, this + * function is identical to @ref CORE_YieldCritical(). + ******************************************************************************/ +SL_WEAK void CORE_YieldAtomic(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + CORE_irqState_t basepri = __get_BASEPRI(); + if (basepri >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL << (8U - __NVIC_PRIO_BITS))) { + __set_BASEPRI(0); + __ISB(); + __set_BASEPRI(basepri); + } +#else + if ((__get_PRIMASK() & 1U) != 0U) { + __enable_irq(); + __ISB(); + __disable_irq(); + } +#endif // (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) +} + +/***************************************************************************//** + * @brief + * Enter a NVIC mask section. + * + * When a NVIC mask section is entered, specified NVIC interrupts + * are disabled. + * + * @param[out] nvicState + * Return NVIC interrupts enable mask prior to section entry. + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable within the section. + ******************************************************************************/ +void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, + const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *nvicState = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]); + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Disable NVIC interrupts. + * + * @param[in] disable + * A mask specifying which NVIC interrupts to disable. + ******************************************************************************/ +void CORE_NvicDisableMask(const CORE_nvicMask_t *disable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = *disable; + ) +} + +/***************************************************************************//** + * @brief + * Set current NVIC interrupt enable mask. + * + * @param[out] enable + * A mask specifying which NVIC interrupts are currently enabled. + ******************************************************************************/ +void CORE_NvicEnableMask(const CORE_nvicMask_t *enable) +{ + CORE_CRITICAL_SECTION( + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = *enable; + ) +} + +/***************************************************************************//** + * @brief + * Brief NVIC interrupt enable/disable sequence to allow handling of + * pending interrupts. + * + * @param[in] enable + * A mask specifying which NVIC interrupts to briefly enable. + * + * @note + * Usually used within an NVIC mask section. + ******************************************************************************/ +void CORE_YieldNvicMask(const CORE_nvicMask_t *enable) +{ + CORE_nvicMask_t nvicMask; + + // Get current NVIC enable mask. + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + + // Make a mask with bits set for those interrupts that are currently + // disabled but are set in the enable mask. +#if (CORE_NVIC_REG_WORDS == 1) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + + if (nvicMask.a[0] != 0) { +#elif (CORE_NVIC_REG_WORDS == 2) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U)) { +#elif (CORE_NVIC_REG_WORDS == 3) + nvicMask.a[0] &= enable->a[0]; + nvicMask.a[1] &= enable->a[1]; + nvicMask.a[2] &= enable->a[2]; + nvicMask.a[0] = ~nvicMask.a[0] & enable->a[0]; + nvicMask.a[1] = ~nvicMask.a[1] & enable->a[1]; + nvicMask.a[2] = ~nvicMask.a[2] & enable->a[2]; + + if ((nvicMask.a[0] != 0U) || (nvicMask.a[1] != 0U) || (nvicMask.a[2] != 0U)) { +#endif + + // Enable previously disabled interrupts. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]) = nvicMask; + + // Disable those interrupts again. + *(CORE_nvicMask_t*)((uint32_t)&NVIC->ICER[0]) = nvicMask; + } +} + +/***************************************************************************//** + * @brief + * Utility function to set an IRQn bit in a NVIC enable/disable mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to set the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] |= 1UL << ((unsigned)irqN & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Utility function to clear an IRQn bit in a NVIC enable/disable mask. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in,out] mask + * The mask to clear the interrupt bit in. + ******************************************************************************/ +void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask) +{ + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask->a[(unsigned)irqN >> 5] &= ~(1UL << ((unsigned)irqN & 0x1FUL)); +} + +/***************************************************************************//** + * @brief + * Check whether the current CPU operation mode is handler mode. + * + * @return + * True if the CPU is in handler mode (currently executing an interrupt handler). + * @n False if the CPU is in thread mode. + ******************************************************************************/ +SL_WEAK bool CORE_InIrqContext(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U; +} + +/***************************************************************************//** + * @brief + * Check if a specific interrupt is disabled or blocked. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled or blocked. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsBlocked(IRQn_Type irqN) +{ + uint32_t irqPri, activeIrq; + +#if (__CORTEX_M >= 3) + uint32_t basepri; + + EFM_ASSERT((irqN >= MemoryManagement_IRQn) + && (irqN < (IRQn_Type)EXT_IRQ_COUNT)); +#else + EFM_ASSERT((irqN >= SVCall_IRQn) && ((IRQn_Type)irqN < EXT_IRQ_COUNT)); +#endif + + if ((__get_PRIMASK() & 1U) != 0U) { + return true; // All IRQs are disabled. + } + + if (CORE_NvicIRQDisabled(irqN)) { + return true; // The IRQ in question is disabled. + } + + irqPri = NVIC_GetPriority(irqN); +#if (__CORTEX_M >= 3) + basepri = __get_BASEPRI(); + if ((basepri != 0U) + && (irqPri >= (basepri >> (8U - __NVIC_PRIO_BITS)))) { + return true; // The IRQ in question has too low + } // priority vs. BASEPRI. +#endif + + // Check if already in an interrupt handler. If so, an interrupt with a + // higher priority (lower priority value) can preempt. + activeIrq = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos; + if (activeIrq != 0U) { + if (irqPri >= NVIC_GetPriority((IRQn_Type)(activeIrq - 16U))) { + return true; // The IRQ in question has too low + } // priority vs. current active IRQ + } + + return false; +} + +/***************************************************************************//** + * @brief + * Check if interrupts are disabled. + * + * @return + * True if interrupts are disabled. + ******************************************************************************/ +SL_WEAK bool CORE_IrqIsDisabled(void) +{ +#if (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_PRIMASK) + return (__get_PRIMASK() & 1U) == 1U; + +#elif (CORE_ATOMIC_METHOD == CORE_ATOMIC_METHOD_BASEPRI) + return ((__get_PRIMASK() & 1U) == 1U) + || (__get_BASEPRI() >= (CORE_ATOMIC_BASE_PRIORITY_LEVEL + << (8U - __NVIC_PRIO_BITS))); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current NVIC enable mask state. + * + * @param[out] mask + * The current NVIC enable mask. + ******************************************************************************/ +void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask) +{ + CORE_CRITICAL_SECTION( + *mask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) +} + +/***************************************************************************//** + * @brief + * Get NVIC disable state for a given mask. + * + * @param[in] mask + * An NVIC mask to check. + * + * @return + * True if all NVIC interrupt mask bits are clear. + ******************************************************************************/ +bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask) +{ + CORE_nvicMask_t nvicMask; + + CORE_CRITICAL_SECTION( + nvicMask = *(CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + ) + +#if (CORE_NVIC_REG_WORDS == 1) + return (mask->a[0] & nvicMask.a[0]) == 0U; + +#elif (CORE_NVIC_REG_WORDS == 2) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U); + +#elif (CORE_NVIC_REG_WORDS == 3) + return ((mask->a[0] & nvicMask.a[0]) == 0U) + && ((mask->a[1] & nvicMask.a[1]) == 0U) + && ((mask->a[2] & nvicMask.a[2]) == 0U); +#endif +} + +/***************************************************************************//** + * @brief + * Check if an NVIC interrupt is disabled. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt to check. + * + * @return + * True if the interrupt is disabled. + ******************************************************************************/ +bool CORE_NvicIRQDisabled(IRQn_Type irqN) +{ + CORE_nvicMask_t *mask; + + EFM_ASSERT(((int)irqN >= 0) && ((int)irqN < EXT_IRQ_COUNT)); + mask = (CORE_nvicMask_t*)((uint32_t)&NVIC->ISER[0]); + return (mask->a[(unsigned)irqN >> 5U] & (1UL << ((unsigned)irqN & 0x1FUL))) + == 0UL; +} + +/***************************************************************************//** + * @brief + * Utility function to get the handler for a specific interrupt. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @return + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void *CORE_GetNvicRamTableHandler(IRQn_Type irqN) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + return (void*)((uint32_t*)(((uint32_t*)SCB->VTOR)[(int)irqN + 16])); +} + +/***************************************************************************//** + * @brief + * Utility function to set the handler for a specific interrupt. + * + * @param[in] irqN + * The IRQn_Type enumerator for the interrupt. + * + * @param[in] handler + * The handler address. + * + * @note + * Uses the interrupt vector table defined by the current VTOR register value. + ******************************************************************************/ +void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler) +{ + EFM_ASSERT(((int)irqN >= -16) && ((int)irqN < EXT_IRQ_COUNT)); + ((uint32_t*)SCB->VTOR)[(int)irqN + 16] = (uint32_t)((uint32_t*)handler); +} + +/***************************************************************************//** + * @brief + * Initialize an interrupt vector table by copying table entries from a + * source to a target table. + * + * @note This function will set a new VTOR register value. + * + * @param[in] sourceTable + * The address of the source vector table. + * + * @param[in] sourceSize + * A number of entries in the source vector table. + * + * @param[in] targetTable + * The address of the target (new) vector table. + * + * @param[in] targetSize + * A number of entries in the target vector table. + * + * @param[in] defaultHandler + * An address of the interrupt handler used for target entries for which where there + * is no corresponding source entry (i.e., the target table is larger than the source + * table). + * + * @param[in] overwriteActive + * When true, a target table entry is always overwritten with the + * corresponding source entry. If false, a target table entry is only + * overwritten if it is zero. This makes it possible for an application + * to partly initialize a target table before passing it to this function. + * + ******************************************************************************/ +void CORE_InitNvicVectorTable(uint32_t *sourceTable, + uint32_t sourceSize, + uint32_t *targetTable, + uint32_t targetSize, + void *defaultHandler, + bool overwriteActive) +{ + uint32_t i; + + // ASSERT on non SRAM-based target table. + EFM_ASSERT(((uint32_t)targetTable >= SRAM_BASE) + && ((uint32_t)targetTable < (SRAM_BASE + SRAM_SIZE))); + + // ASSERT if misaligned with respect to the VTOR register implementation. +#if defined(SCB_VTOR_TBLBASE_Msk) + EFM_ASSERT(((uint32_t)targetTable & ~(SCB_VTOR_TBLOFF_Msk + | SCB_VTOR_TBLBASE_Msk)) == 0U); +#else + EFM_ASSERT(((uint32_t)targetTable & ~SCB_VTOR_TBLOFF_Msk) == 0U); +#endif + + // ASSERT if misaligned with respect to the vector table size. + // The vector table address must be aligned at its size rounded up to nearest 2^n. + EFM_ASSERT(((uint32_t)targetTable + & ((1UL << (32UL - __CLZ((targetSize * 4UL) - 1UL))) - 1UL)) + == 0UL); + + for (i = 0; i < targetSize; i++) { + if (overwriteActive) { // Overwrite target entries. + if (i < sourceSize) { // targetSize <= sourceSize + targetTable[i] = sourceTable[i]; + } else { // targetSize > sourceSize + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } else { // Overwrite target entries which are 0. + if (i < sourceSize) { // targetSize <= sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = sourceTable[i]; + } + } else { // targetSize > sourceSize + if (targetTable[i] == 0U) { + targetTable[i] = (uint32_t)((uint32_t*)defaultHandler); + } + } + } + } + SCB->VTOR = (uint32_t)targetTable; +} + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) || defined(DOXYGEN) +/***************************************************************************//** + * @brief + * Start a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_start(dwt_cycle_counter_handle_t *handle) +{ + handle->start = DWT->CYCCNT; +} + +/***************************************************************************//** + * @brief + * Stop a recording. + * + * @param[in] handle + * Pointer to initialized counter handle. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +static void cycle_counter_stop(dwt_cycle_counter_handle_t *handle) +{ + handle->cycles = DWT->CYCCNT - handle->start; + + if (handle->cycles > handle->max) { + handle->max = handle->cycles; + } +} + +/***************************************************************************//** + * @brief + * Returns the max time spent in critical section. + * + * @return + * The max time spent in critical section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +uint32_t CORE_get_max_time_critical_section(void) +{ + return critical_cycle_counter.max; +} + +/***************************************************************************//** + * @brief + * Returns the max time spent in atomic section. + * + * @return + * The max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +uint32_t CORE_get_max_time_atomic_section(void) +{ + return atomic_cycle_counter.max; +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +void CORE_clear_max_time_critical_section(void) +{ + critical_cycle_counter.max = 0; +} + +/***************************************************************************//** + * @brief + * Clears the max time spent in atomic section. + * + * @note SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled. + ******************************************************************************/ +void CORE_clear_max_time_atomic_section(void) +{ + atomic_cycle_counter.max = 0; +} +#endif //(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + +/** @} (end addtogroup core) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c index b9c22a4..b567495 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_dbg.c @@ -1,214 +1,214 @@ -/***************************************************************************//** - * @file - * @brief Debug (DBG) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_dbg.h" - -#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "em_gpio.h" -#include "em_msc.h" -#if defined(_SILICON_LABS_32B_SERIES_2) -#include "em_se.h" -#endif - -/***************************************************************************//** - * @addtogroup dbg DBG - Debug - * @brief Debug (DBG) Peripheral API - * @details - * This module contains functions to control the DBG peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The Debug Interface is used to program and debug - * Silicon Labs devices. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN) \ - || defined(GPIO_TRACEROUTEPEN_SWVPEN) -/***************************************************************************//** - * @brief - * Enable Serial Wire Output (SWO) pin. - * - * @details - * The SWO pin (sometimes denoted SWV, serial wire viewer) allows for - * miscellaneous output to be passed from the Cortex-M3 debug trace module to - * an external debug probe. By default, the debug trace module and pin output - * may be disabled. - * - * Since the SWO pin is only useful when using a debugger, a suggested use - * of this function during startup may be: - * @verbatim - * if (DBG_Connected()) - * { - * DBG_SWOEnable(1); - * } - * @endverbatim - * By checking if the debugger is attached, a setup leading to a higher energy - * consumption when the debugger is attached can be avoided when not using - * a debugger. - * - * Another alternative may be to set the debugger tool chain to configure - * the required setup (similar to the content of this function) by some - * sort of toolchain scripting during its attach/reset procedure. In that - * case, the above suggested code for enabling the SWO pin is not required - * in the application. - * - * @param[in] location - * A pin location used for SWO pin on the application in use. - ******************************************************************************/ -void DBG_SWOEnable(unsigned int location) -{ - int port; - int pin; - -#if defined(GPIO_SWV_PORT) - - port = GPIO_SWV_PORT; - pin = GPIO_SWV_PIN; - -#else - EFM_ASSERT(location < AFCHANLOC_MAX); - #if defined (AF_DBG_SWO_PORT) - port = AF_DBG_SWO_PORT(location); - pin = AF_DBG_SWO_PIN(location); - #elif defined (AF_DBG_SWV_PORT) - port = AF_DBG_SWV_PORT(location); - pin = AF_DBG_SWV_PIN(location); - - #else - #warning "AF debug port is not defined." - #endif -#endif - - /* Port/pin location not defined for the device. */ - if ((pin < 0) || (port < 0)) { - EFM_ASSERT(0); - return; - } - - /* Ensure that the auxiliary clock going to the Cortex debug trace module is enabled. */ -#if !defined(_SILICON_LABS_32B_SERIES_2) - CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, false); -#endif - - /* Set the selected pin location for the SWO pin and enable it. */ - GPIO_DbgLocationSet(location); - GPIO_DbgSWOEnable(true); - - /* Configure the SWO pin for output. */ - GPIO_PinModeSet((GPIO_Port_TypeDef)port, pin, gpioModePushPull, 0); -} -#endif - -#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) - -/***************************************************************************//** - * @brief - * Disable debug access. - * - * @cond DOXYDOC_S2_DEVICE - * @details - * SE interface is used to disable debug access. By choosing - * @ref dbgLockModePermanent, debug access is blocked permanently. SE disables - * the device erase command and thereafter disables debug access. - * @endcond - * @cond DOXYDOC_P2_DEVICE - * @ - * @details - * Debug access is blocked using debug lock word. On series 1 devices, - * if @ref dbgLockModePermanent is chosen, debug access is blocked - * permanently using AAP lock word. - * @endcond - * @param[in] lockMode - * Debug lock mode to be used. - * - * @cond !DOXYDOC_P1_DEVICE - * @warning - * If @ref dbgLockModePermanent is chosen as the lock mode, the debug port - * will be closed permanently and is irreversible. - * @endcond - ******************************************************************************/ -void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode) -{ -#if defined(SEMAILBOX_PRESENT) - if (lockMode == dbgLockModeAllowErase) { - SE_debugLockApply(); - } else if (lockMode == dbgLockModePermanent) { - SE_deviceEraseDisable(); - SE_debugLockApply(); - } else { - /* Invalid input */ - EFM_ASSERT(0); - } -#else -#if defined(_SILICON_LABS_32B_SERIES_0) - if (lockMode != dbgLockModeAllowErase) { - EFM_ASSERT(0); - } -#else - if ((lockMode != dbgLockModeAllowErase) && (lockMode != dbgLockModePermanent)) { - EFM_ASSERT(0); - } -#endif - - bool wasLocked; - uint32_t lockWord = 0x0; - wasLocked = ((MSC->LOCK & _MSC_LOCK_MASK) != 0U); - MSC_Init(); - - uint32_t *dlw = (uint32_t*)(LOCKBITS_BASE + (127 * 4)); - - if (*dlw == 0xFFFFFFFF) { - MSC_WriteWord(dlw, &lockWord, sizeof(lockWord)); - } -#if !defined(_SILICON_LABS_32B_SERIES_0) - uint32_t *alw = (uint32_t*)(LOCKBITS_BASE + (124 * 4)); - - if (lockMode == dbgLockModePermanent) { - if (*alw == 0xFFFFFFFF) { - MSC_WriteWord(alw, &lockWord, sizeof(lockWord)); - } - } -#endif - - if (wasLocked) { - MSC_Deinit(); - } -#endif -} - -#endif /* defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) */ - -/** @} (end addtogroup dbg) */ -#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ +/***************************************************************************//** + * @file + * @brief Debug (DBG) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_dbg.h" + +#if defined(CoreDebug_DHCSR_C_DEBUGEN_Msk) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "em_gpio.h" +#include "em_msc.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_se.h" +#endif + +/***************************************************************************//** + * @addtogroup dbg DBG - Debug + * @brief Debug (DBG) Peripheral API + * @details + * This module contains functions to control the DBG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The Debug Interface is used to program and debug + * Silicon Labs devices. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(GPIO_ROUTE_SWOPEN) || defined(GPIO_ROUTEPEN_SWVPEN) \ + || defined(GPIO_TRACEROUTEPEN_SWVPEN) +/***************************************************************************//** + * @brief + * Enable Serial Wire Output (SWO) pin. + * + * @details + * The SWO pin (sometimes denoted SWV, serial wire viewer) allows for + * miscellaneous output to be passed from the Cortex-M3 debug trace module to + * an external debug probe. By default, the debug trace module and pin output + * may be disabled. + * + * Since the SWO pin is only useful when using a debugger, a suggested use + * of this function during startup may be: + * @verbatim + * if (DBG_Connected()) + * { + * DBG_SWOEnable(1); + * } + * @endverbatim + * By checking if the debugger is attached, a setup leading to a higher energy + * consumption when the debugger is attached can be avoided when not using + * a debugger. + * + * Another alternative may be to set the debugger tool chain to configure + * the required setup (similar to the content of this function) by some + * sort of toolchain scripting during its attach/reset procedure. In that + * case, the above suggested code for enabling the SWO pin is not required + * in the application. + * + * @param[in] location + * A pin location used for SWO pin on the application in use. + ******************************************************************************/ +void DBG_SWOEnable(unsigned int location) +{ + int port; + int pin; + +#if defined(GPIO_SWV_PORT) + + port = GPIO_SWV_PORT; + pin = GPIO_SWV_PIN; + +#else + EFM_ASSERT(location < AFCHANLOC_MAX); + #if defined (AF_DBG_SWO_PORT) + port = AF_DBG_SWO_PORT(location); + pin = AF_DBG_SWO_PIN(location); + #elif defined (AF_DBG_SWV_PORT) + port = AF_DBG_SWV_PORT(location); + pin = AF_DBG_SWV_PIN(location); + + #else + #warning "AF debug port is not defined." + #endif +#endif + + /* Port/pin location not defined for the device. */ + if ((pin < 0) || (port < 0)) { + EFM_ASSERT(0); + return; + } + + /* Ensure that the auxiliary clock going to the Cortex debug trace module is enabled. */ +#if !defined(_SILICON_LABS_32B_SERIES_2) + CMU_OscillatorEnable(cmuOsc_AUXHFRCO, true, false); +#endif + + /* Set the selected pin location for the SWO pin and enable it. */ + GPIO_DbgLocationSet(location); + GPIO_DbgSWOEnable(true); + + /* Configure the SWO pin for output. */ + GPIO_PinModeSet((GPIO_Port_TypeDef)port, pin, gpioModePushPull, 0); +} +#endif + +#if defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) + +/***************************************************************************//** + * @brief + * Disable debug access. + * + * @cond DOXYDOC_S2_DEVICE + * @details + * SE interface is used to disable debug access. By choosing + * @ref dbgLockModePermanent, debug access is blocked permanently. SE disables + * the device erase command and thereafter disables debug access. + * @endcond + * @cond DOXYDOC_P2_DEVICE + * @ + * @details + * Debug access is blocked using debug lock word. On series 1 devices, + * if @ref dbgLockModePermanent is chosen, debug access is blocked + * permanently using AAP lock word. + * @endcond + * @param[in] lockMode + * Debug lock mode to be used. + * + * @cond !DOXYDOC_P1_DEVICE + * @warning + * If @ref dbgLockModePermanent is chosen as the lock mode, the debug port + * will be closed permanently and is irreversible. + * @endcond + ******************************************************************************/ +void DBG_DisableDebugAccess(DBG_LockMode_TypeDef lockMode) +{ +#if defined(SEMAILBOX_PRESENT) + if (lockMode == dbgLockModeAllowErase) { + SE_debugLockApply(); + } else if (lockMode == dbgLockModePermanent) { + SE_deviceEraseDisable(); + SE_debugLockApply(); + } else { + /* Invalid input */ + EFM_ASSERT(0); + } +#else +#if defined(_SILICON_LABS_32B_SERIES_0) + if (lockMode != dbgLockModeAllowErase) { + EFM_ASSERT(0); + } +#else + if ((lockMode != dbgLockModeAllowErase) && (lockMode != dbgLockModePermanent)) { + EFM_ASSERT(0); + } +#endif + + bool wasLocked; + uint32_t lockWord = 0x0; + wasLocked = ((MSC->LOCK & _MSC_LOCK_MASK) != 0U); + MSC_Init(); + + uint32_t *dlw = (uint32_t*)(LOCKBITS_BASE + (127 * 4)); + + if (*dlw == 0xFFFFFFFF) { + MSC_WriteWord(dlw, &lockWord, sizeof(lockWord)); + } +#if !defined(_SILICON_LABS_32B_SERIES_0) + uint32_t *alw = (uint32_t*)(LOCKBITS_BASE + (124 * 4)); + + if (lockMode == dbgLockModePermanent) { + if (*alw == 0xFFFFFFFF) { + MSC_WriteWord(alw, &lockWord, sizeof(lockWord)); + } + } +#endif + + if (wasLocked) { + MSC_Deinit(); + } +#endif +} + +#endif /* defined(LOCKBITS_BASE) && !defined(_EFM32_GECKO_FAMILY) */ + +/** @} (end addtogroup dbg) */ +#endif /* defined( CoreDebug_DHCSR_C_DEBUGEN_Msk ) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c index feadce5..af6b2cc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_emu.c @@ -1,4188 +1,4188 @@ -/***************************************************************************//** - * @file - * @brief Energy Management Unit (EMU) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include - -#include "em_emu.h" -#if defined(EMU_PRESENT) && (EMU_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include "em_core.h" -#include "em_system.h" -#include "em_ramfunc.h" - -#if defined(SL_CATALOG_METRIC_EM23_WAKE_PRESENT) -#include "sli_metric_em23_wake.h" -#include "sli_metric_em23_wake_config.h" -#endif - -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) -#include "sli_metric_em4_wake.h" -#endif - -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -/* Consistency check, since restoring assumes similar bit positions in */ -/* CMU OSCENCMD and STATUS regs. */ -#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) -#error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions -#endif -#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) -#error Conflict in HFXOENS and HFXOEN bitpositions -#endif -#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) -#error Conflict in LFRCOENS and LFRCOEN bitpositions -#endif -#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) -#error Conflict in LFXOENS and LFXOEN bitpositions -#endif - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ -#if defined(_SILICON_LABS_32B_SERIES_0) -/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ -#if defined(_EFM32_GECKO_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) -#define NON_WIC_INT_MASK_1 (~(0x0U)) - -#elif defined(_EFM32_TINY_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x001be323U)) -#define NON_WIC_INT_MASK_1 (~(0x0U)) - -#elif defined(_EFM32_GIANT_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) -#define NON_WIC_INT_MASK_1 (~(0x00000046U)) - -#elif defined(_EFM32_WONDER_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) -#define NON_WIC_INT_MASK_1 (~(0x00000046U)) - -#elif defined(_EFM32_ZERO_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x00005c6bU)) -#define NON_WIC_INT_MASK_1 (~(0x00000000U)) - -#elif defined(_EFM32_HAPPY_FAMILY) -#define ERRATA_FIX_EMU_E107_ENABLE -#define NON_WIC_INT_MASK_0 (~(0x00085c6bU)) -#define NON_WIC_INT_MASK_1 (~(0x00000000U)) - -#endif -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ - || (defined(_SILICON_LABS_32B_SERIES_0) \ - && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) -// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. -#define ERRATA_FIX_EMU_E110_ENABLE -#endif - -/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) -#define ERRATA_FIX_EMU_E108_ENABLE -#endif - -/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_EMU_E208_ENABLE -#endif - -/* Enable FETCNT tuning errata fix. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE -#endif - -/* Enable LN handshake errata fix. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE -typedef enum { - errataFixDcdcHsInit, - errataFixDcdcHsTrimSet, - errataFixDcdcHsBypassLn, - errataFixDcdcHsLnWaitDone -} errataFixDcdcHs_TypeDef; -static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; -#endif - -/* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S - * while powering the analog peripherals from DVDD, firmware must switch - * over to powering the analog peripherals from AVDD and delay the EM4S entry - * with 30 us. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -#define ERRATA_FIX_EM4S_DELAY_ENTRY -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ - && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) -/* EMU_E220 DECBOD Errata fix. DECBOD Reset can occur - * during voltage scaling after EM2/3 wakeup. */ -#define ERRATA_FIX_EMU_E220_DECBOD_ENABLE -#define EMU_PORBOD (*(volatile uint32_t *) (EMU_BASE + 0x14C)) -#define EMU_PORBOD_GMC_CALIB_DISABLE (0x1UL << 31) -#endif - -/* Used to figure out if a memory address is inside or outside of a RAM block. - * A memory address is inside a RAM block if the address is greater than the - * RAM block address. */ -#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) - -/* RAM Block layout for various device families. Note that some devices - * have special layout in RAM0 and some devices have a special RAM block - * at the end of their block layout. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) -#define RAM1_BLOCKS 2U -#define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) -#define RAM0_BLOCKS 2U -#define RAM0_BLOCK_SIZE 0x4000U -#define RAM1_BLOCKS 2U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#define RAM0_BLOCKS 1U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB block -#define RAM1_BLOCKS 1U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB block -#define RAM2_BLOCKS 1U -#define RAM2_BLOCK_SIZE 0x800U // 2 kB block -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) -#define RAM0_BLOCKS 8U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM1_BLOCKS 8U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 4U -#define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM1_BLOCKS 4U -#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks -#define RAM2_BLOCKS 4U -#define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#define RAM0_BLOCKS 6U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) -#define RAM0_BLOCKS 4U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define RAM0_BLOCKS 16U -#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks -#endif - -#if defined(_SILICON_LABS_32B_SERIES_0) -/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ -#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) -#else -#define RAM0_END RAM_MEM_END -#endif - -#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) -#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) -#elif defined(CMU_STATUS_HFXOPEAKDETRDY) -#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#if !defined(PWRCFG_DCDCTODVDD_VMIN) -/** DCDCTODVDD output range maximum. */ -#define PWRCFG_DCDCTODVDD_VMIN 1800U -#endif -#if !defined(PWRCFG_DCDCTODVDD_VMAX) -/** DCDCTODVDD output range minimum. */ -#define PWRCFG_DCDCTODVDD_VMAX 3000U -#endif -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) || defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -#define DCDC_LP_PFET_CNT 7 -#define DCDC_LP_NFET_CNT 7 -#endif - -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) -#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/* Translate fields with different names across platform generations to common names. */ -#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT -#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK -#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT -#endif -#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT -#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK -#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT -#endif - -/* Disable LP mode hysteresis in the state machine control. */ -#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) -/* Comparator threshold on the high side. */ -#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) -#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) - -#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) -#endif - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/* EMU DCDC MODE set timeout. */ -#define EMU_DCDC_MODE_SET_TIMEOUT 1000000 -#endif -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -#define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) -#define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) -#define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) -#define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/* As the energy mode at which a temperature measurement was taken at is - * not known, the chosen constant for the TEMPCO calculation is midway between - * the EM0/EM1 constant and the EM2/EM3/EM4 constant. - */ -#define EMU_TEMPCO_CONST (0.273f) -#endif - -#define EMU_EM4_ENTRY_WAIT_LOOPS 200 - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -/* Static user configuration. */ -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -static uint16_t dcdcMaxCurrent_mA; -static uint16_t dcdcEm01LoadCurrent_mA; -static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; -#endif -#if defined(EMU_VSCALE_EM01_PRESENT) -static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; -#endif - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/* Convert from level to EM0/1 command bit */ -__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - return EMU_CMD_EM01VSCALE1 << ((uint32_t)level - _EMU_STATUS_VSCALE_VSCALE1); -#else - return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); -#endif -} -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); -SL_RAMFUNC_DEFINITION_BEGIN -static void __attribute__ ((noinline)) ramWFI(void) -{ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) - __WFI(); // Enter EM2 or EM3 - if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { - for (volatile int i = 0; i < 6; i++) { - } // Dummy wait loop ... - } - -#else - __WFI(); // Enter EM2 or EM3 -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Warray-bounds" -#endif - *(volatile uint32_t*)4; // Clear faulty read data after wakeup -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif -#endif -} -SL_RAMFUNC_DEFINITION_END -#endif - -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) -SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); -SL_RAMFUNC_DEFINITION_BEGIN -static void __attribute__ ((noinline)) ramWFI(void) -{ - /* Second part of EMU_E220 DECBOD Errata fix. Calibration needs to be disabled - * quickly when coming out of EM2/EM3. Ram execution is needed to meet timing. - * Calibration is re-enabled after voltage scaling completes. */ - uint32_t temp = EMU_PORBOD | EMU_PORBOD_GMC_CALIB_DISABLE; - __WFI(); - EMU_PORBOD = temp; -} -SL_RAMFUNC_DEFINITION_END -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) -/***************************************************************************//** - * @brief - * Save/restore/update oscillator, core clock and voltage scaling configuration on - * EM2 or EM3 entry/exit. - * - * @details - * Hardware may automatically change the oscillator and the voltage scaling configuration - * when going into or out of an energy mode. Static data in this function keeps track of - * such configuration bits and is used to restore state if needed. - * - ******************************************************************************/ -typedef enum { - emState_Save, /* Save EMU and CMU state. */ - emState_Restore, /* Restore and unlock. */ -} emState_TypeDef; - -static void emState(emState_TypeDef action) -{ - uint32_t oscEnCmd; - uint32_t cmuLocked; - static uint32_t cmuStatus; - static CMU_Select_TypeDef hfClock; -#if defined(EMU_VSCALE_PRESENT) - static uint8_t vScaleStatus; - static uint32_t hfrcoCtrl; -#endif - - /* Save or update state. */ - if (action == emState_Save) { - /* Save configuration. */ - cmuStatus = CMU->STATUS; - hfClock = CMU_ClockSelectGet(cmuClock_HF); -#if defined(EMU_VSCALE_PRESENT) - /* Save vscale. */ - EMU_VScaleWait(); - vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) - >> _EMU_STATUS_VSCALE_SHIFT); - hfrcoCtrl = CMU->HFRCOCTRL; -#endif - } else { /* Restore state. */ - /* Apply saved configuration. */ -#if defined(EMU_VSCALE_PRESENT) -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == true) - /* Restore voltage scaling level if LDO regulator is on. */ -#endif - { - /* Restore EM0 and 1 voltage scaling level. - @ref EMU_VScaleWait() is called later, - just before HF clock select is set. */ - EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); - } -#endif - /* CMU registers may be locked. */ - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); - -#if defined(_CMU_OSCENCMD_MASK) - /* AUXHFRCO are automatically disabled (except if using debugger). */ - /* HFRCO, USHFRCO and HFXO are automatically disabled. */ - /* LFRCO/LFXO may be disabled by SW in EM3. */ - /* Restore according to status prior to entering energy mode. */ - oscEnCmd = 0; - oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U - ? CMU_OSCENCMD_HFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U - ? CMU_OSCENCMD_AUXHFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U - ? CMU_OSCENCMD_LFRCOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U - ? CMU_OSCENCMD_HFXOEN : 0U; - oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U - ? CMU_OSCENCMD_LFXOEN : 0U; -#if defined(_CMU_STATUS_USHFRCOENS_MASK) - oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U - ? CMU_OSCENCMD_USHFRCOEN : 0U; -#endif - CMU->OSCENCMD = oscEnCmd; -#endif - -#if defined(_EMU_STATUS_VSCALE_MASK) - /* Wait for upscale to complete and then restore selected clock. */ - EMU_VScaleWait(); - if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { - /* Restore HFRCO frequency which was automatically adjusted by hardware. */ - while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { - } - CMU->HFRCOCTRL = hfrcoCtrl; - if (hfClock == cmuSelect_HFRCO) { - /* Optimize wait state after EM2/EM3 wakeup because hardware has - * modified them. */ - CMU_UpdateWaitStates(SystemHfrcoFreq, (int)EMU_VScaleGet()); - } - } -#endif - - switch (hfClock) { - case cmuSelect_LFXO: - CMU_CLOCK_SELECT_SET(HF, LFXO); - break; - case cmuSelect_LFRCO: - CMU_CLOCK_SELECT_SET(HF, LFRCO); - break; - case cmuSelect_HFXO: - CMU_CLOCK_SELECT_SET(HF, HFXO); - break; -#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) - case cmuSelect_USHFRCODIV2: - CMU_CLOCK_SELECT_SET(HF, USHFRCODIV2); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) - case cmuSelect_HFRCODIV2: - CMU_CLOCK_SELECT_SET(HF, HFRCODIV2); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) - case cmuSelect_CLKIN0: - CMU_CLOCK_SELECT_SET(HF, CLKIN0); - break; -#endif -#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) - case cmuSelect_USHFRCO: - CMU_CLOCK_SELECT_SET(HF, USHFRCO); - break; -#endif - } - -#if defined(_CMU_OSCENCMD_MASK) - /* If HFRCO was disabled before entering Energy Mode, turn it off again */ - /* as it is automatically enabled by wake up */ - if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { - CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; - } -#endif - - /* Restore CMU register locking */ - if (cmuLocked != 0U) { - CMU_Lock(); - } - } -} -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) -/* Get enable conditions for errata EMU_E107 fix. */ -__STATIC_INLINE bool getErrataFixEmuE107En(void) -{ -#if defined(_EFM32_HAPPY_FAMILY) \ - || defined(_EFM32_TINY_FAMILY) \ - || defined(_EFM32_WONDER_FAMILY) \ - || defined(_EFM32_ZERO_FAMILY) - // all revisions have the errata - return true; -#else - /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation - * would be needed in this case. - */ - uint16_t majorMinorRev; - - /* CHIP MAJOR bit [3:0]. */ - majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) - << 8; - /* CHIP MINOR bit [7:4]. */ - majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) - << 4; - /* CHIP MINOR bit [3:0]. */ - majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; - -#if defined(_EFM32_GECKO_FAMILY) - // all GECKO revisions except Revision E have the errata - return (majorMinorRev <= 0x0103); -#elif defined(_EFM32_GIANT_FAMILY) - // all LEOPARD GECKO (Major = 0x01 Or 0x02) revisions have the errata - // all GIANT GECKO (Major = 0x01) revisions except Revision E have the errata - return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204) || (majorMinorRev == 0x0205); -#else - /* Invalid configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; -#endif -#endif /* #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) #else */ -} -#endif /* #if defined(ERRATA_FIX_EMU_E107_ENABLE) */ - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -/* Get enable conditions for errata EMU_E110 fix. */ -__STATIC_INLINE bool getErrataFixEmuE110En(void) -{ - /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation - * would be needed in this case. - */ - uint16_t majorMinorRev; - - /* CHIP MAJOR bit [3:0]. */ - majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT) - << 8; - /* CHIP MINOR bit [7:4]. */ - majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) - << 4; - /* CHIP MINOR bit [3:0]. */ - majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_ZERO_FAMILY) - return (majorMinorRev == 0x0100); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) - return ((majorMinorRev == 0x0100 || majorMinorRev == 0x0101)); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_WONDER_FAMILY) - return (majorMinorRev == 0x0100); -#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) - return (majorMinorRev == 0x0204); -#else - /* Invalid configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; -#endif -} -#endif /* #if defined(ERRATA_FIX_EMU_E110_ENABLE) */ - -/* LP prepare / LN restore P/NFET count. */ -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) -static void currentLimitersUpdate(void); -static void dcdcFetCntSet(bool lpModeSet) -{ - uint32_t tmp; - static uint32_t emuDcdcMiscCtrlReg; - - if (lpModeSet) { - emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; - tmp = EMU->DCDCMISCCTRL - & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); - tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) - | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); - EMU->DCDCMISCCTRL = tmp; - currentLimitersUpdate(); - } else { - EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; - currentLimitersUpdate(); - } -} -#endif - -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) -static void dcdcHsFixLnBlock(void) -{ - if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) - || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { - /* Wait for LNRUNNING */ - if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { - while (!(EMU_DCDCSTATUS & (0x1 << 16))) { - } - } - errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; - } -} -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) -/* Configure EMU and CMU for EM2 and 3 voltage downscale. */ -static void vScaleDownEM23Setup(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - /* Wait until previous scaling is done. */ - EMU_VScaleWait(); - - uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; - uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; - - /* Inverse coding. */ - if (em23vs > em01vs) { - EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; -#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) - /* Set RAM wait states for safe EM2 wakeup. */ - BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN - | MSC_RAMCTRL_RAM1WSEN - | MSC_RAMCTRL_RAM2WSEN)); -#endif - } else { - EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; - } -} - -/* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ -static void vScaleAfterWakeup(void) -{ - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 - * entry if voltage scaling in EM2/EM3 is enabled. The hardware would - * then update the HFRCO frequency to 19 MHz automatically. */ - uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) - >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; - if (freqRange == 0x08U) { - SystemHfrcoFreq = 19000000; - } - } -} -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) -typedef enum { - dpllState_Save, /* Save DPLL state. */ - dpllState_Restore, /* Restore DPLL. */ -} dpllState_TypeDef; - -/***************************************************************************//** - * @brief - * Save or restore DPLL state. - * - * @param[in] action - * Value to indicate saving DPLL state or restoring its state. - * - * @note - * The function is used in EMU_Save() and EMU_Restore() to handle the - * DPLL state before entering EM2 or EM3 and after exiting EM2 or EM3. - * The function is required for the EFR32xG22 and EFR32xG27 families. - * On those families devices, the DPLL is disabled automatically when - * entering EM2, EM3. But exiting EM2, EM3 won't re-enable automatically - * the DPLL. Hence, the software needs to re-enable the DPLL upon EM2/3 - * exit. - ******************************************************************************/ -static void dpllState(dpllState_TypeDef action) -{ - CMU_ClkDiv_TypeDef div; - static uint32_t dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - - if (action == dpllState_Save) { - dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; - if (DPLL0->EN == DPLL_EN_EN) { - /* DPLL is in use, save reference clock selection. */ - dpllRefClk = CMU->DPLLREFCLKCTRL; - } - } else { /* Restore */ - if ((dpllRefClk != CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED) - && (DPLL0->EN != DPLL_EN_EN)) { - /* Restore DPLL reference clock selection. */ - CMU->DPLLREFCLKCTRL = dpllRefClk; - /* Only wait for DPLL lock if HFRCODPLL is used as SYSCLK. */ - if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { - /* Set HCLK prescaler to safe value to avoid overclocking while locking. */ - div = CMU_ClockDivGet(cmuClock_HCLK); - if (div == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 2U); - } - - /* Relock DPLL and wait for ready. */ - DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; - DPLL0->EN_SET = DPLL_EN_EN; - while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { - } - - /* Restore HCLK prescaler. */ - if (div == 1U) { - CMU_ClockDivSet(cmuClock_HCLK, 1U); - } - } else { - /* Relock DPLL and exit without waiting for ready. */ - DPLL0->EN_SET = DPLL_EN_EN; - } - } - } -} -#endif - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup emu EMU - Energy Management Unit - * @brief Energy Management Unit (EMU) Peripheral API - * @details - * This module contains functions to control the EMU peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes - * in Silicon Labs microcontrollers. - * @{ - ******************************************************************************/ - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 0 and 1 configuration. - * - * @param[in] em01Init - * Energy Mode 0 and 1 configuration structure. - ******************************************************************************/ -void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) -{ - vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = - em01Init->vScaleEM01LowPowerVoltageEnable; - EMU_VScaleEM01ByClock(0, true); -} -#endif - -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 2 and 3 configuration. - * - * @param[in] em23Init - * Energy Mode 2 and 3 configuration structure. - ******************************************************************************/ -void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) -{ -#if defined(_EMU_CTRL_EMVREG_MASK) - EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) - : (EMU->CTRL & ~EMU_CTRL_EMVREG); -#elif defined(_EMU_CTRL_EM23VREG_MASK) - EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) - : (EMU->CTRL & ~EMU_CTRL_EM23VREG); -#else - (void)em23Init; -#endif - -#if defined(EMU_VSCALE_PRESENT) - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) - | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); -#if defined(CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) - if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { - /* Voltage scaling is not compatible with HFXO auto start and select. */ - EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); - } -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Energy mode 2/3 pre-sleep hook function. - * - * @details - * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions - * just prior to execution of the WFI instruction. The function implementation - * does not perform anything, but it is SL_WEAK so that it can be re- - * implemented in application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM23PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 2/3 pre-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM23PresleepHook() but is reserved - * for EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM23PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Energy mode 2/3 post-sleep hook function. - * - * @details - * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions - * just after wakeup from the WFI instruction. The function implementation - * does not perform anything, but it is SL_WEAK so that it can be re- - * implemented in application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM23PostsleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 2/3 post-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM23PostsleepHook() but is reserved - * for EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM23PostsleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Enter energy mode 2 (EM2). - * - * @details - * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO - * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering - * EM0, HFRCO is re-enabled and the core will be clocked by the configured - * HFRCO band. This ensures a quick wakeup from EM2. - * - * However, prior to entering EM2, the core may have been using another - * oscillator than HFRCO. The @p restore parameter gives the user the option - * to restore all HF oscillators according to state prior to entering EM2, - * as well as the clock used to clock the core. This restore procedure is - * handled by SW. However, since handled by SW, it will not be restored - * before completing the interrupt function(s) waking up the core! - * - * @note - * If restoring core clock to use the HFXO oscillator, which has been - * disabled during EM2 mode, this function will stall until the oscillator - * has stabilized. Stalling time can be reduced by adding interrupt - * support detecting stable oscillator, and an asynchronous switch to the - * original oscillator. See CMU documentation. Such a feature is however - * outside the scope of the implementation in this function. - * @note - * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature - * can not be used. - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - * @par - * If HFXO is re-enabled by this function, and NOT used to clock the core, - * this function will not wait for HFXO to stabilize. This must be considered - * by the application if trying to use features relying on that oscillator - * upon return. - * @par - * If a debugger is attached, the AUXHFRCO will not be disabled if enabled - * upon entering EM2. It will thus remain enabled when returning to EM0 - * regardless of the @p restore parameter. - * @par - * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(), - * the automatic starting and selecting of the core clocks will be done, - * regardless of the @p restore parameter, when waking up on the wakeup - * sources corresponding to the autostart and select setting. - * @par - * If voltage scaling is supported, the restore parameter is true and the EM0 - * voltage scaling level is set higher than the EM2 level, then the EM0 level is - * also restored. - * @par - * On Series 2 Config 2 devices (EFRxG22), this function will also relock the - * DPLL if the DPLL is used and @p restore is true. - * - * Note that the hardware will automatically update the HFRCO frequency in the - * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the - * restore argument to this function is true then software will restore the - * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is - * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and - * all wait states are at a safe value. - * - * @param[in] restore - * @li true - save and restore oscillators, clocks and voltage scaling, see - * function details. - * @li false - do not save and restore oscillators and clocks, see function - * details. - * @par - * The @p restore option should only be used if all clock control is done - * via the CMU API. - ******************************************************************************/ -void EMU_EnterEM2(bool restore) -{ -#if defined(SLI_METRIC_EM2_HOOK) - sli_metric_em23_wake_init(SLI_INIT_EM2_WAKE); -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - bool errataFixEmuE107En; - uint32_t nonWicIntEn[2]; -#endif - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - bool errataFixEmuE110En; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Save); - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Only save EMU and CMU state if restored on wake-up. */ - if (restore) { - emState(emState_Save); - } -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - vScaleDownEM23Setup(); -#endif - - /* Enter Cortex deep sleep mode. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. - Disable the enabled non-WIC interrupts. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - errataFixEmuE107En = getErrataFixEmuE107En(); - if (errataFixEmuE107En) { - nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; - NVIC->ICER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; - NVIC->ICER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - - EMU_EM23PresleepHook(); - EMU_EFPEM23PresleepHook(); -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - errataFixEmuE110En = getErrataFixEmuE110En(); - if (errataFixEmuE110En) { -#endif - CORE_CRITICAL_SECTION(ramWFI(); ) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -} else { - __WFI(); -} -#endif -#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - // Apply errata fix if voltage scaling in EM2 is used. - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - CORE_CRITICAL_SECTION(ramWFI(); ) - } else { - __WFI(); - } -#else - __WFI(); -#endif - EMU_EFPEM23PostsleepHook(); - EMU_EM23PostsleepHook(); - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(false); -#endif - - /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - if (errataFixEmuE107En) { - NVIC->ISER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - NVIC->ISER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Restore oscillators/clocks and voltage scaling if supported. */ - if (restore) { - emState(emState_Restore); - } -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - else { - vScaleAfterWakeup(); - } -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled - * after voltage scaling completes. */ - EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); -#endif -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Restore); - } -#endif - - if (!restore) { - /* If not restoring, and the original clock was not HFRCO, the CMSIS */ - /* core clock variable must be updated since HF clock has changed */ - /* to HFRCO. */ - SystemCoreClockUpdate(); - } -} - -/***************************************************************************//** - * @brief - * Enter energy mode 3 (EM3). - * - * @details - * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, - * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, - * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When - * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the - * configured HFRCO band. This ensures a quick wakeup from EM3. - * - * However, prior to entering EM3, the core may have been using an - * oscillator other than HFRCO. The @p restore parameter gives the user the option - * to restore all HF/LF oscillators according to state prior to entering EM3, - * as well as the clock used to clock the core. This restore procedure is - * handled by software. However, since it is handled by software, it will not be restored - * before completing the interrupt function(s) waking up the core! - * - * @note - * If restoring core clock to use an oscillator other than HFRCO, this - * function will stall until the oscillator has stabilized. Stalling time - * can be reduced by adding interrupt support detecting stable oscillator, - * and an asynchronous switch to the original oscillator. See CMU - * documentation. This feature is, however, outside the scope of the - * implementation in this function. - * @note - * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature - * can't be used. - * @note - * This function is incompatible with the Power Manager module. When the - * Power Manager module is present, it must be the one deciding at which - * EM level the device sleeps to ensure the application properly works. Using - * both at the same time could lead to undefined behavior in the application. - * @par - * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock - * the core, this function will not wait for those oscillators to stabilize. - * This must be considered by the application if trying to use features - * relying on those oscillators upon return. - * @par - * If a debugger is attached, the AUXHFRCO will not be disabled if enabled - * upon entering EM3. It will, therefore, remain enabled when returning to EM0 - * regardless of the @p restore parameter. - * @par - * If voltage scaling is supported, the restore parameter is true and the EM0 - * voltage scaling level is set higher than the EM3 level, then the EM0 level is - * also restored. - * @par - * On Series 2 Config 2 devices (EFRxG22), this function will also relock the - * DPLL if the DPLL is used and @p restore is true. - * - * @param[in] restore - * @li true - save and restore oscillators, clocks and voltage scaling, see - * function details. - * @li false - do not save and restore oscillators and clocks, see function - * details. - * @par - * The @p restore option should only be used if all clock control is done - * via the CMU API. - ******************************************************************************/ -void EMU_EnterEM3(bool restore) -{ -#if defined(SLI_METRIC_EM3_HOOK) - sli_metric_em23_wake_init(SLI_INIT_EM3_WAKE); -#endif - -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - bool errataFixEmuE107En; - uint32_t nonWicIntEn[2]; -#endif - -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - bool errataFixEmuE110En; -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Save); - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Only save EMU and CMU state if restored on wake-up. */ - if (restore) { - emState(emState_Save); - } -#endif - -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - vScaleDownEM23Setup(); -#endif - -#if defined(_CMU_OSCENCMD_MASK) - uint32_t cmuLocked; - cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; - CMU_Unlock(); - - /* Disable LF oscillators. */ - CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; - - /* Restore CMU register locking. */ - if (cmuLocked != 0U) { - CMU_Lock(); - } -#endif - - /* Enter Cortex deep sleep mode. */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. - Disable the enabled non-WIC interrupts. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - errataFixEmuE107En = getErrataFixEmuE107En(); - if (errataFixEmuE107En) { - nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; - NVIC->ICER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; - NVIC->ICER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - - EMU_EM23PresleepHook(); -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ - || defined(ERRATA_FIX_EMU_E110_ENABLE) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) - errataFixEmuE110En = getErrataFixEmuE110En(); - if (errataFixEmuE110En) { -#endif - CORE_CRITICAL_SECTION(ramWFI(); ) -#if defined(ERRATA_FIX_EMU_E110_ENABLE) -} else { - __WFI(); -} -#endif -#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - // Apply errata fix if voltage scaling in EM2 is used. - if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { - CORE_CRITICAL_SECTION(ramWFI(); ) - } else { - __WFI(); - } -#else - __WFI(); -#endif - EMU_EM23PostsleepHook(); - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(false); -#endif - - /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ -#if defined(ERRATA_FIX_EMU_E107_ENABLE) - if (errataFixEmuE107En) { - NVIC->ISER[0] = nonWicIntEn[0]; -#if (NON_WIC_INT_MASK_1 != (~(0x0U))) - NVIC->ISER[1] = nonWicIntEn[1]; -#endif - } -#endif - -#if (_SILICON_LABS_32B_SERIES < 2) - /* Restore oscillators/clocks and voltage scaling if supported. */ - if (restore) { - emState(emState_Restore); - } -#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) - else { - vScaleAfterWakeup(); - } -#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) - /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled - * after voltage scaling completes. */ - EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); -#endif -#endif -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - if (restore) { - dpllState(dpllState_Restore); - } -#endif - - if (!restore) { - /* If not restoring, and the original clock was not HFRCO, the CMSIS */ - /* core clock variable must be updated since HF clock has changed */ - /* to HFRCO. */ - SystemCoreClockUpdate(); - } -} - -/***************************************************************************//** - * @brief - * Save the CMU HF clock select state, oscillator enable, and voltage scaling - * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called - * with the restore parameter set to false. Calling this function is - * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the - * restore parameter set to true, but it allows the state to be saved without - * going to sleep. The state can be restored manually by calling - * @ref EMU_Restore(). - ******************************************************************************/ -void EMU_Save(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Save); -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - dpllState(dpllState_Save); -#endif -} - -/***************************************************************************//** - * @brief - * Restore CMU HF clock select state, oscillator enable, and voltage scaling - * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called - * with the restore parameter set to false. Calling this function is - * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the - * restore parameter set to true, but it allows the application to evaluate the - * wakeup reason before restoring state. - ******************************************************************************/ -void EMU_Restore(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Restore); -#endif -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - dpllState(dpllState_Restore); -#endif -} - -#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) -/***************************************************************************//** - * @brief - * Update the EMU module with Energy Mode 4 configuration. - * - * @param[in] em4Init - * Energy Mode 4 configuration structure. - ******************************************************************************/ -void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) -{ -#if defined(_EMU_EM4CONF_MASK) - /* Initialization for platforms with EMU->EM4CONF register. */ - uint32_t em4conf = EMU->EM4CONF; - - /* Clear fields that will be reconfigured. */ - em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK - | _EMU_EM4CONF_OSC_MASK - | _EMU_EM4CONF_BURTCWU_MASK - | _EMU_EM4CONF_VREGEN_MASK - | _EMU_EM4CONF_BUBODRSTDIS_MASK); - - /* Configure new settings. */ - em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) - | (em4Init->osc) - | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) - | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) - | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); - - /* Apply configuration. Note that lock can be set after this stage. */ - EMU->EM4CONF = em4conf; - -#elif defined(_EMU_EM4CTRL_EM4STATE_MASK) - /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ - - uint32_t em4ctrl = EMU->EM4CTRL; - - em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK - | _EMU_EM4CTRL_RETAINLFRCO_MASK - | _EMU_EM4CTRL_RETAINULFRCO_MASK - | _EMU_EM4CTRL_EM4STATE_MASK - | _EMU_EM4CTRL_EM4IORETMODE_MASK); - - em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) - | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) - | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) - | (em4Init->em4State == emuEM4Hibernate - ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) - | ((uint32_t)em4Init->pinRetentionMode); - - EMU->EM4CTRL = em4ctrl; -#elif defined(_EMU_EM4CTRL_MASK) - EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) - | (uint32_t)em4Init->pinRetentionMode; -#endif - -#if defined(_EMU_CTRL_EM4HVSCALE_MASK) - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) - | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Energy mode 4 pre-sleep hook function. - * - * @details - * This function is called by @ref EMU_EnterEM4() just prior to the sequence - * of writes to put the device in EM4. The function implementation does not - * perform anything, but it is SL_WEAK so that it can be re-implemented in - * application code if actions are needed. - ******************************************************************************/ -SL_WEAK void EMU_EM4PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * EFP's Energy mode 4 pre-sleep hook function. - * - * @details - * This function is similar to @ref EMU_EM4PresleepHook() but is reserved for - * EFP usage. - * - * @note - * The function is primarily meant to be used in systems with EFP circuitry. - * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). - * In such systems there is a need to drive certain signals to EFP pins to - * notify about energy mode transitions. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM4PresleepHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 (EM4). - * - * @note - * Only a power on reset or external reset pin can wake the device from EM4. - ******************************************************************************/ -void EMU_EnterEM4(void) -{ -#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) - sli_metric_em4_wake_init(); -#endif - int i; - -#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) - uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); - uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) - | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); -#else - uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) - | (2U << _EMU_CTRL_EM4CTRL_SHIFT); - uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) - | (3U << _EMU_CTRL_EM4CTRL_SHIFT); -#endif - - /* Make sure that the register write lock is disabled. */ - EMU_Unlock(); - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should - * switch to bypass mode before entering EM4S. Other devices handle this - * automatically at the hardware level. */ - if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { - uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; - if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE - || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { - EMU_DCDCModeSet(emuDcdcMode_Bypass); - } - } -#endif - -#if defined(_DCDC_IF_EM4ERR_MASK) - /* Make sure DCDC Mode is not modified, from this point forward, - * by another code section. */ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - - /* Workaround for bug that may cause a Hard Fault on EM4 entry */ - CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); - /* The buck DC-DC is available in all energy modes except for EM4. - * The DC-DC converter must first be turned off and switched over to bypass mode. */ -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ - || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) - EMU_DCDCModeSet(emuDcdcMode_Bypass); -#endif -#endif - -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) - if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { - /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. - * Full description of errata fix can be found in the errata document. */ - __disable_irq(); - *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; - *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); - *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); - } -#endif - -#if defined(ERRATA_FIX_EMU_E108_ENABLE) - /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ - __disable_irq(); - *(volatile uint32_t *)0x400C80E4 = 0; -#endif - -#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) - dcdcFetCntSet(true); -#endif -#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) - dcdcHsFixLnBlock(); -#endif - -#if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) - /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ - if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { - if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { - BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); - /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement - * before entering EM4. */ - uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) - | CMU_HFRCOCTRL_CLKDIV_DIV4; - while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { - } - CMU->HFRCOCTRL = freqCal; - CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; - while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { - } - CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; - __NOP(); - } - } -#endif - - EMU_EM4PresleepHook(); - EMU_EFPEM4PresleepHook(); - - for (i = 0; i < 4; i++) { -#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) - EMU->EM4CTRL = em4seq2; - EMU->EM4CTRL = em4seq3; - } - EMU->EM4CTRL = em4seq2; -#else - EMU->CTRL = em4seq2; - EMU->CTRL = em4seq3; - } - EMU->CTRL = em4seq2; -#endif - -#if defined(_DCDC_IF_EM4ERR_MASK) - EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); - CORE_EXIT_CRITICAL(); -#endif -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 (EM4). - * - * @details - * This function waits after the EM4 entry request to make sure the CPU - * is properly shutdown or the EM4 entry failed. - * - * @note - * Only a power on reset or external reset pin can wake the device from EM4. - ******************************************************************************/ -void EMU_EnterEM4Wait(void) -{ - EMU_EnterEM4(); - - // The EM4 entry waiting loop should take 4 cycles by loop minimally (Compiler dependent). - // We would then wait for (EMU_EM4_ENTRY_WAIT_LOOPS * 4) clock cycles. - for (uint16_t i = 0; i < EMU_EM4_ENTRY_WAIT_LOOPS; i++) { - __NOP(); - } -} - -#if defined(_EMU_EM4CTRL_MASK) -/***************************************************************************//** - * @brief - * Enter energy mode 4 hibernate (EM4H). - * - * @note - * Retention of clocks and GPIO in EM4 can be configured using - * @ref EMU_EM4Init before calling this function. - ******************************************************************************/ -void EMU_EnterEM4H(void) -{ -#if defined(_EMU_EM4CTRL_EM4STATE_MASK) - BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); -#endif - EMU_EnterEM4(); -} - -/***************************************************************************//** - * @brief - * Enter energy mode 4 shutoff (EM4S). - * - * @note - * Retention of clocks and GPIO in EM4 can be configured using - * @ref EMU_EM4Init before calling this function. - ******************************************************************************/ -void EMU_EnterEM4S(void) -{ -#if defined(_EMU_EM4CTRL_EM4STATE_MASK) - BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); -#endif - EMU_EnterEM4(); -} -#endif - -/***************************************************************************//** - * @brief - * Power down memory block. - * - * @param[in] blocks - * Specifies a logical OR of bits indicating memory blocks to power down. - * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot - * be disabled. See the reference manual for available - * memory blocks for a device. - * - * @note - * Only a POR reset can power up the specified memory block(s) after power down. - * - * @deprecated - * This function is deprecated, use @ref EMU_RamPowerDown() instead which - * maps a user provided memory range into RAM blocks to power down. - ******************************************************************************/ -void EMU_MemPwrDown(uint32_t blocks) -{ -#if defined(_EMU_MEMCTRL_MASK) - EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; -#elif defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; -#else - (void)blocks; -#endif -} - -/***************************************************************************//** - * @brief - * Power down RAM memory blocks. - * - * @details - * This function will power down all the RAM blocks that are within a given - * range. The RAM block layout is different between device families, so this - * function can be used in a generic way to power down a RAM memory region - * which is known to be unused. - * - * This function will only power down blocks which are completely enclosed - * by the memory range given by [start, end). - * - * This is an example to power down all RAM blocks except the first - * one. The first RAM block is special in that it cannot be powered down - * by the hardware. The size of the first RAM block is device-specific. - * See the reference manual to find the RAM block sizes. - * - * @code - * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); - * @endcode - * - * @note - * Only a reset can power up the specified memory block(s) after power down - * on a series 0 device. The specified memory block(s) will stay off - * until a call to EMU_RamPowerUp() is done on series 1/2. - * - * @param[in] start - * The start address of the RAM region to power down. This address is - * inclusive. - * - * @param[in] end - * The end address of the RAM region to power down. This address is - * exclusive. If this parameter is 0, all RAM blocks contained in the - * region from start to the upper RAM address will be powered down. - ******************************************************************************/ -void EMU_RamPowerDown(uint32_t start, uint32_t end) -{ - uint32_t mask = 0; - (void) start; - - if (end == 0U) { - end = SRAM_BASE + SRAM_SIZE; - } - - // Check to see if something in RAM0 can be powered down. - if (end > RAM0_END) { -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 - // Block 0 is 16 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 - // Block 0 is 4 kB and cannot be powered off. - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB - mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) - // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. - // This condition happens when the block 0 disable bit flag is available in the retention control register. - for (unsigned i = 1; i < RAM0_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i); - } -#elif defined(RAM0_BLOCKS) - // These platforms have equally-sized RAM blocks and block 0 cannot be powered down. - for (unsigned i = 1; i < RAM0_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); - } -#endif - } - - // Power down the selected blocks. -#if defined(_EMU_MEMCTRL_MASK) - EMU->MEMCTRL = EMU->MEMCTRL | mask; -#elif defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = EMU->RAM0CTRL | mask; -#elif defined(_SILICON_LABS_32B_SERIES_2) -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - SYSCFG_maskDmem0RetnCtrl(mask); -#else - // These devices are unable to power down RAM blocks. - (void) mask; - (void) start; -#endif - -#if defined(RAM1_MEM_END) - mask = 0; - if (end > RAM1_MEM_END) { - for (unsigned i = 0; i < RAM1_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; - } - } - EMU->RAM1CTRL |= mask; -#endif - -#if defined(RAM2_MEM_END) - mask = 0; - if (end > RAM2_MEM_END) { - for (unsigned i = 0; i < RAM2_BLOCKS; i++) { - mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; - } - } - EMU->RAM2CTRL |= mask; -#endif -} - -/***************************************************************************//** - * @brief - * Power up all available RAM memory blocks. - * - * @details - * This function will power up all the RAM blocks on a device, this means - * that the RAM blocks are retained in EM2/EM3. Note that this functionality - * is not supported on Series 0 devices. Only a reset will power up the RAM - * blocks on a series 0 device. - ******************************************************************************/ -void EMU_RamPowerUp(void) -{ -#if defined(_EMU_RAM0CTRL_MASK) - EMU->RAM0CTRL = 0x0UL; -#endif -#if defined(_EMU_RAM1CTRL_MASK) - EMU->RAM1CTRL = 0x0UL; -#endif -#if defined(_EMU_RAM2CTRL_MASK) - EMU->RAM2CTRL = 0x0UL; -#endif -#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - SYSCFG_zeroDmem0RetnCtrl(); -#endif -} - -#if defined(_EMU_EM23PERNORETAINCTRL_MASK) -/***************************************************************************//** - * @brief - * Set EM2 3 peripheral retention control. - * - * @param[in] periMask - * A peripheral select mask. Use | operator to select multiple peripherals, for example - * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. - * @param[in] enable - * Peripheral retention enable (true) or disable (false). - * - * - * @note - * Only peripheral retention disable is currently supported. Peripherals are - * enabled by default and can only be disabled. - ******************************************************************************/ -void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) -{ - EFM_ASSERT(!enable); - EMU->EM23PERNORETAINCTRL = (uint32_t)periMask - & (uint32_t)emuPeripheralRetention_ALL; -} -#endif - -/***************************************************************************//** - * @brief - * Update EMU module with CMU oscillator selection/enable status. - * - * @deprecated - * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). - ******************************************************************************/ -void EMU_UpdateOscConfig(void) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - emState(emState_Save); -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) && defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Energy mode 01 voltage scaling hook function. - * - * @param[in] voltage - * Voltage scaling level requested. - * - * @details - * This function is called by EMU_VScaleEM01 to let EFP know that voltage scaling - * is requested. - ******************************************************************************/ -SL_WEAK void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage) -{ - (void)voltage; -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Voltage scale in EM0 and 1 by clock frequency. - * - * @param[in] clockFrequency - * Use CMSIS HF clock if 0 or override to custom clock. Providing a - * custom clock frequency is required if using a non-standard HFXO - * frequency. - * @param[in] wait - * Wait for scaling to complete. - * - * @note - * This function is primarily needed by the @ref cmu. - ******************************************************************************/ -void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) -{ - uint32_t hfSrcClockFrequency; - -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - /* VSCALE frequency is HFSRCCLK. */ - if (clockFrequency == 0U) { -#if defined(_SILICON_LABS_32B_SERIES_2) - hfSrcClockFrequency = SystemSYSCLKGet(); -#else - uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT); - hfSrcClockFrequency = SystemHFClockGet() * hfPresc; -#endif - } else { - hfSrcClockFrequency = clockFrequency; - } - - /* Apply EM0 and 1 voltage scaling command. */ - if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable - && (hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { - EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); - } else { - EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); - } -} -#endif - -#if defined(EMU_VSCALE_EM01_PRESENT) -/***************************************************************************//** - * @brief - * Force voltage scaling in EM0 and 1 to a specific voltage level. - * - * @param[in] voltage - * Target VSCALE voltage level. - * @param[in] wait - * Wait for scaling to complete. - * - * @note - * This function is useful for upscaling before programming Flash from @ref msc - * and downscaling after programming is done. Flash programming is only supported - * at @ref emuVScaleEM01_HighPerformance. - * - * @note - * This function ignores vScaleEM01LowPowerVoltageEnable set from @ref - * EMU_EM01Init(). - ******************************************************************************/ -void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) -{ - uint32_t hfFreq; - uint32_t hfSrcClockFrequency; - -#if defined(_SILICON_LABS_32B_SERIES_1) - if (EMU_LDOStatusGet() == false) { - /* Skip voltage scaling if the LDO regulator is turned off. */ - return; - } -#endif - - if (EMU_VScaleGet() == voltage) { - /* Voltage is already at the correct level. */ - return; - } - -#if defined(_SILICON_LABS_32B_SERIES_2) - (void)wait; - CORE_DECLARE_IRQ_STATE; - - hfFreq = SystemSYSCLKGet(); - hfSrcClockFrequency = hfFreq; - - if (voltage == emuVScaleEM01_LowPower) { - EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); - /* Update wait states before scaling down voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); - } - - CORE_ENTER_CRITICAL(); - EMU->IF_CLR = EMU_IF_VSCALEDONE; - EMU_EFPEM01VScale(voltage); - EMU->CMD = vScaleEM01Cmd(voltage); - - // Note that VSCALEDONE interrupt flag must be used instead of VSCALEBUSY - // because hardware does not set the VSCALEBUSY flag immediately. - while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) - && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { - EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); - // Wait for VSCALE completion. - // SRAM accesses will fault the core while scaling. - } - CORE_EXIT_CRITICAL(); - -#else - uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) - >> _CMU_HFPRESC_PRESC_SHIFT); - hfFreq = SystemHFClockGet(); - hfSrcClockFrequency = hfFreq * hfPresc; - - if (voltage == emuVScaleEM01_LowPower) { - EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); - /* Update wait states before scaling down voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); - } - - EMU->CMD = vScaleEM01Cmd(voltage); - - if (wait) { - EMU_VScaleWait(); - } -#endif - - if (voltage == emuVScaleEM01_HighPerformance) { - /* Update wait states after scaling up voltage. */ - CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_HIGH_PERFORMANCE); - } -} -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) -/***************************************************************************//** - * @brief - * Configure Backup Power Domain settings. - * - * @param[in] bupdInit - * Backup power domain initialization structure. - ******************************************************************************/ -void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) -{ - uint32_t reg; - - /* Set the power connection configuration. */ - reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK - | _EMU_PWRCONF_VOUTSTRONG_MASK - | _EMU_PWRCONF_VOUTMED_MASK - | _EMU_PWRCONF_VOUTWEAK_MASK); - - reg |= bupdInit->resistor - | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) - | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) - | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); - - EMU->PWRCONF = reg; - - /* Set the backup domain inactive mode configuration. */ - reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); - reg |= (bupdInit->inactivePower); - EMU->BUINACT = reg; - - /* Set the backup domain active mode configuration. */ - reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); - reg |= (bupdInit->activePower); - EMU->BUACT = reg; - - /* Set the power control configuration */ - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK - | _EMU_BUCTRL_BODCAL_MASK - | _EMU_BUCTRL_STATEN_MASK - | _EMU_BUCTRL_EN_MASK); - - /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and - release reset. */ - reg |= bupdInit->probe - | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) - | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) - | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); - - /* Enable configuration. */ - EMU->BUCTRL = reg; - - /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ - EMU_BUPinEnable(bupdInit->enable); - - /* If enable is true, release BU reset. If not, keep reset asserted. */ - BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); -} - -/***************************************************************************//** - * @brief - * Configure the Backup Power Domain BOD Threshold value. - * @note - * These values are precalibrated. - * @param[in] mode Active or Inactive mode - * @param[in] value - ******************************************************************************/ -void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) -{ - EFM_ASSERT(value < 8); - EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); - - switch (mode) { - case emuBODMode_Active: - EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) - | (value << _EMU_BUACT_BUEXTHRES_SHIFT); - break; - case emuBODMode_Inactive: - EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) - | (value << _EMU_BUINACT_BUENTHRES_SHIFT); - break; - } -} - -/***************************************************************************//** - * @brief - * Configure the Backup Power Domain BOD Threshold Range. - * @note - * These values are precalibrated. - * @param[in] mode Active or Inactive mode - * @param[in] value - ******************************************************************************/ -void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) -{ - EFM_ASSERT(value < 4); - EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); - - switch (mode) { - case emuBODMode_Active: - EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) - | (value << _EMU_BUACT_BUEXRANGE_SHIFT); - break; - case emuBODMode_Inactive: - EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) - | (value << _EMU_BUINACT_BUENRANGE_SHIFT); - break; - } -} -#endif - -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) -/***************************************************************************//** - * @brief - * Configure Backup Power Domain settings. - * - * @param[in] buInit - * Backup power domain initialization structure. - ******************************************************************************/ -void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) -{ - uint32_t reg = 0; - - /* Set the backup power configuration. */ - reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); - reg |= (uint32_t)(buInit->inactivePwrCon); - reg |= (uint32_t)(buInit->activePwrCon); - reg |= (uint32_t)(buInit->pwrRes); - reg |= (uint32_t)(buInit->voutRes); - reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); - reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); - reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) -/***************************************************************************//** - * @brief - * Disable Main Backup Power Domain comparator. - * - * @param[in] disableMainBuComparator - * True to disable main BU comparator. - ******************************************************************************/ -void EMU_BUDisMaxCompSet(bool disableMainBuComparator) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); - reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) -/***************************************************************************//** - * @brief - * Configure power connection configuration when not in Backup mode. - * - * @param[in] inactPwrCon - * Inactive power configuration. - ******************************************************************************/ -void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); - reg |= (uint32_t)(inactPwrCon); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) -/***************************************************************************//** - * @brief - * Configure power connection configuration when in Backup mode. - * - * @param[in] actPwrCon - * Active power configuration. - ******************************************************************************/ -void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); - reg |= (uint32_t)(actPwrCon); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_PWRRES_MASK) -/***************************************************************************//** - * @brief - * Power domain resistor selection. - * - * @param[in] pwrRes - * Resistor selection. - ******************************************************************************/ -void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); - reg |= (uint32_t)(pwrRes); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_VOUTRES_MASK) -/***************************************************************************//** - * @brief - * B_VOUT resistor select. - * - * @param[in] resistorSel - * Resistor selection. - ******************************************************************************/ -void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); - reg |= (uint32_t)(resistorSel); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) -/***************************************************************************//** - * @brief - * Enable BU_VIN probing - * - * @param[in] enable - * True to enable BU_VIN probing. False to disable. - ******************************************************************************/ -void EMU_BUBuVinProbeEnSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); - reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_STATEN_MASK) -/***************************************************************************//** - * @brief - * Enable backup mode status export. - * - * @param[in] enable - * True to enable status export. False to disable. - ******************************************************************************/ -void EMU_BUStatEnSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); - reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(_EMU_BUCTRL_EN_MASK) -/***************************************************************************//** - * @brief - * Enable backup mode. - * - * @param[in] enable - * True to enable backup mode. False to disable. - ******************************************************************************/ -void EMU_BUEnableSet(bool enable) -{ - uint32_t reg; - - reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); - reg |= (enable << _EMU_BUCTRL_EN_SHIFT); - EMU->BUCTRL = reg; -} -#endif - -#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* Internal DCDC trim modes. */ -typedef enum { - dcdcTrimMode_EM234H_LP = 0, -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - dcdcTrimMode_EM01_LP, -#endif - dcdcTrimMode_LN, -} dcdcTrimMode_TypeDef; - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Load DCDC calibration constants from the DI page. A constant means that calibration - * data that does not change depending on other configuration parameters. - * - * @return - * False if calibration registers are locked. - ******************************************************************************/ -static bool dcdcConstCalibrationLoad(void) -{ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint32_t val; - volatile uint32_t *reg; - - /* DI calibration data in Flash. */ - volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); - volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); - volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); - volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); - volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); - volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); - - if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { - val = *(diCal_EMU_DCDCLNFREQCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLNVCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLPCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCLPVCTRL + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; - *reg = val; - - val = *(diCal_EMU_DCDCTRIM0 + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; - *reg = val; - - val = *(diCal_EMU_DCDCTRIM1 + 1); - reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; - *reg = val; - - return true; - } - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - -#else - return true; -#endif -} - -/***************************************************************************//** - * @brief - * Set recommended and validated current optimization and timing settings. - * - ******************************************************************************/ -static void dcdcValidatedConfigSet(void) -{ - uint32_t lnForceCcm; - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint32_t dcdcTiming; - SYSTEM_ChipRevision_TypeDef rev; -#endif - - /* Enable duty cycling of the bias. */ - EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; - - /* Set low-noise RCO for LNFORCECCM configuration. - * LNFORCECCM is default 1 for EFR32 - * LNFORCECCM is default 0 for EFM32 - */ - lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - if (lnForceCcm != 0U) { - /* 7 MHz is recommended for LNFORCECCM = 1. */ - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); - } else { - /* 3 MHz is recommended for LNFORCECCM = 0. */ - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); - } - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; - EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS - | EMU_DCDCMISCCTRL_LPCMPHYSHI; - - SYSTEM_ChipRevisionGet(&rev); - if ((rev.major == 1) - && (rev.minor < 3) - && (errataFixDcdcHsState == errataFixDcdcHsInit)) { - /* LPCMPWAITDIS = 1 */ - EMU_DCDCSMCTRL |= 1; - - dcdcTiming = EMU->DCDCTIMING; - dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK - | _EMU_DCDCTIMING_LNWAIT_MASK - | _EMU_DCDCTIMING_BYPWAIT_MASK); - - dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) - | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) - | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); - EMU->DCDCTIMING = dcdcTiming; - - errataFixDcdcHsState = errataFixDcdcHsTrimSet; - } -#endif -} - -/***************************************************************************//** - * @brief - * Compute current limiters: - * LNCLIMILIMSEL: LN current limiter threshold - * LPCLIMILIMSEL: LP current limiter threshold - * DCDCZDETCTRL: zero detector limiter threshold - ******************************************************************************/ -static void currentLimitersUpdate(void) -{ - uint32_t lncLimSel; - uint32_t zdetLimSel; - uint32_t pFetCnt; - uint16_t maxReverseCurrent_mA; - - /* 80 mA as recommended peak in Application Note AN0948. - The peak current is the average current plus 50% of the current ripple. - Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also - a constant, lpcLimImSel = 1. The following calculation is provided - for documentation only. */ - const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) - / (5 * (DCDC_LP_PFET_CNT + 1))) - - 1; - const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; - - /* Get enabled PFETs. */ - pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) - >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; - - /* Compute the LN current limiter threshold from the nominal user input current and - LN PFETCNT as described in the register description for - EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ - lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) - + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) - / (5U * (pFetCnt + 1U))) - - 1U; - - /* Saturate the register field value. */ - lncLimSel = SL_MIN(lncLimSel, - _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK - >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); - - lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; - - /* Check for overflow. */ - EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); - EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); - - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK - | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) - | (lncLimSel | lpcLimSel); - - /* Compute the reverse current limit threshold for the zero detector from the user input - maximum reverse current and LN PFETCNT as described in the register description - for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ - if (dcdcReverseCurrentControl >= 0) { - /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ - maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; - - zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) - + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) - / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); - /* Saturate the register field value. */ - zdetLimSel = SL_MIN(zdetLimSel, - _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK - >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); - - zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; - - /* Check for overflow. */ - EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); - - EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) - | zdetLimSel; - } -} - -/***************************************************************************//** - * @brief - * Set static variables that hold the user set maximum peak current - * and reverse current. Update limiters. - * - * @param[in] maxCurrent_mA - * Set the maximum peak current that the DCDC can draw from the power source. - * @param[in] reverseCurrentControl - * Reverse the current control as defined by - * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. - ******************************************************************************/ -static void userCurrentLimitsSet(uint32_t maxCurrent_mA, - EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) -{ - dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; - dcdcReverseCurrentControl = reverseCurrentControl; -} - -/***************************************************************************//** - * @brief - * Set DCDC low noise compensator control register. - * - * @param[in] comp - * Low-noise mode compensator trim setpoint. - ******************************************************************************/ -static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) -{ - switch (comp) { - case emuDcdcLnCompCtrl_1u0F: - EMU->DCDCLNCOMPCTRL = 0x57204077UL; - break; - - case emuDcdcLnCompCtrl_4u7F: - EMU->DCDCLNCOMPCTRL = 0xB7102137UL; - break; - - default: - EFM_ASSERT(false); - break; - } -} - -/***************************************************************************//** - * @brief - * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback - * attenuation, and DEVINFOREV. - * - * @param[in] lpAttenuation - * LP feedback attenuation. - * @param[in] lpCmpBias - * lpCmpBias selection. - * @param[in] trimMode - * DCDC trim mode. - ******************************************************************************/ -static bool lpCmpHystCalibrationLoad(bool lpAttenuation, - uint8_t lpCmpBias, - dcdcTrimMode_TypeDef trimMode) -{ - uint32_t lpcmpHystSel; -#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - (void)lpAttenuation; -#endif - - /* Get calibration data revision. */ -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); - - /* Load LPATT indexed calibration data. */ - if (devinfoRev < 4) { - lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; - - if (lpAttenuation) { - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; - } else { - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; - } - } else -#endif - { - /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ - lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; - switch (lpCmpBias) { - case 0: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; - break; - - case 1: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; - break; - - case 2: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; - break; - - case 3: - lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - } - - /* Set trims. */ - if (trimMode == dcdcTrimMode_EM234H_LP) { - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; - if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; - } - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) - if (trimMode == dcdcTrimMode_EM01_LP) { - /* Make sure the sel value is within the field range. */ - lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; - if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; - } -#endif - - return true; -} - -/***************************************************************************//** - * @brief - * Load LPVREF low and high from DEVINFO. - * - * @param[out] vrefL - * LPVREF low from DEVINFO. - * @param[out] vrefH - * LPVREF high from DEVINFO. - * @param[in] lpAttenuation - * LP feedback attenuation. - * @param[in] lpcmpBias - * lpcmpBias to look up in DEVINFO. - ******************************************************************************/ -static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, - uint32_t *vrefH, - bool lpAttenuation, - uint8_t lpcmpBias) -{ - uint32_t vrefLow = 0; - uint32_t vrefHigh = 0; - - /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) - and LPATT (lpAttenuation) */ - uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); - switch (switchVal) { - case ((0 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; - break; - - case ((1 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL2; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; - break; - - case ((2 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; - break; - - case ((3 << 8) | 1): - vrefLow = DEVINFO->DCDCLPVCTRL3; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; - break; - - case ((0 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; - break; - - case ((1 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL0; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) - >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; - break; - - case ((2 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; - break; - - case ((3 << 8) | 0): - vrefLow = DEVINFO->DCDCLPVCTRL1; - vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; - vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) - >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; - break; - - default: - EFM_ASSERT(false); - break; - } - *vrefL = vrefLow; - *vrefH = vrefHigh; -} - -/***************************************************************************//** - * @brief - * Configure the DCDC regulator. - * - * @note - * Do not call this function if the power circuit is configured for NODCDC as - * described in the Power Configurations section of the Reference Manual. - * Instead, call @ref EMU_DCDCPowerOff(). - * - * @param[in] dcdcInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) -{ - uint32_t lpCmpBiasSelEM234H; - -#if defined(_EMU_PWRCFG_MASK) - /* Set the external power configuration. This enables writing to the other - DCDC registers. */ - EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; - - /* EMU->PWRCFG is write-once and POR reset only. Check that - the desired power configuration was set. */ - if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { - /* If this assert triggers unexpectedly, power cycle the - kit to reset the power configuration. */ - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } -#endif - - /* Load DCDC calibration data from the DI page. */ - (void)dcdcConstCalibrationLoad(); - - /* Check current parameters */ - EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); - EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); - - if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { - /* DCDC low-noise supports max 200 mA. */ - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); - } -#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) - else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { - /* Up to 10 mA is supported for EM01-LP mode. */ - EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); - } -#endif - else { - /* No need to check the EM01 load limit. */ - } - - /* EM2/3/4 current above 10 mA is not supported. */ - EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); - - if (dcdcInit->em234LoadCurrent_uA < 75U) { - lpCmpBiasSelEM234H = 0; - } else if (dcdcInit->em234LoadCurrent_uA < 500U) { - lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { - lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } else { - lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; - } - - /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ - - /* Set DCDC low-power mode comparator bias selection. */ - - /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. - => Updates DCDCMISCCTRL_LNFORCECCM */ - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK - | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) - | ((uint32_t)lpCmpBiasSelEM234H - | (dcdcInit->reverseCurrentControl >= 0 - ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* Only 10 mA EM01-LP current is supported. */ - EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; -#endif - - /* 2. Set recommended and validated current optimization settings. - <= Depends on LNFORCECCM - => Updates DCDCLNFREQCTRL_RCOBAND */ - dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; - dcdcValidatedConfigSet(); - - /* 3. Updated static currents and limits user data. - Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ - userCurrentLimitsSet(dcdcInit->maxCurrent_mA, - dcdcInit->reverseCurrentControl); - - /* 4. Optimize LN slice based on the given user input load current. - <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND - <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl - => Updates DCDCMISCCTRL_P/NFETCNT - => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL - => Updates DCDCZDETCTRL_ZDETILIMSEL */ - EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); - - /* ======================================================= */ - - /* Set DCDC low noise mode compensator control register. */ - compCtrlSet(dcdcInit->dcdcLnCompCtrl); - - /* Set DCDC output voltage. */ - if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - -#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) - /* Select analog peripheral power supply. This must be done before - DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ - BUS_RegBitWrite(&EMU->PWRCTRL, - _EMU_PWRCTRL_ANASW_SHIFT, - dcdcInit->anaPeripheralPower ? 1 : 0); -#endif - -#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) - /* Select DVDD as input to the digital regulator. The switch to DVDD will take - effect once the DCDC output is stable. */ - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - - /* Set EM0 DCDC operating mode. Output voltage set in - @ref EMU_DCDCOutputVoltageSet() above takes effect if mode - is changed from bypass/off mode. */ - EMU_DCDCModeSet(dcdcInit->dcdcMode); - -#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) - /* Select the analog peripheral power supply. This must be done after - DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ - BUS_RegBitWrite(&EMU->PWRCTRL, - _EMU_PWRCTRL_ANASW_SHIFT, - dcdcInit->anaPeripheralPower - == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); -#endif - - return true; -} - -/***************************************************************************//** - * @brief - * Set DCDC regulator operating mode. - * - * @param[in] dcdcMode - * DCDC mode. - ******************************************************************************/ -void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) -{ - bool dcdcLocked; - uint32_t currentDcdcMode; - - dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); - EMU_PowerUnlock(); - - /* Wait for any previous write sync to complete and read DCDC mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); - - /* Enable bypass current limiter when not in bypass mode to prevent - excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ - if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); - } - - if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { - /* Mode already set. If already in bypass, make sure the bypass current limiter - is disabled. */ - if (dcdcMode == emuDcdcMode_Bypass) { - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); - } - return; - } - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) - - /* Fix for errata DCDC_E203. */ - if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) - && (dcdcMode == emuDcdcMode_LowNoise)) { - errataFixDcdcHsState = errataFixDcdcHsBypassLn; - } -#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_80) - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - /* Fix for errata DCDC_E204. */ - if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) - && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { - /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ - EMU_IntClear(EMU_IFC_DCDCLNRUNNING); - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; - while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { - } - } -#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_84) - - /* Set user-requested mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) - | (uint32_t)dcdcMode; - - /* Disable bypass current limiter after bypass mode is entered. - Enable the limiter if any other mode is entered. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, - _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, - dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); - - if (dcdcLocked) { - EMU_PowerLock(); - } -} - -#if defined(EMU_DCDCCTRL_DCDCMODEEM23) -/***************************************************************************//** - * @brief - * Set DCDC Mode EM23 operating mode. - * - * @param[in] dcdcModeEM23 - * DCDC mode EM23. - ******************************************************************************/ -void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23) -{ - bool dcdcLocked; - - dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); - EMU_PowerUnlock(); - - /* Set user-requested mode. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { - } - EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) - | (uint32_t)dcdcModeEM23; - - if (dcdcLocked) { - EMU_PowerLock(); - } -} -#endif - -/***************************************************************************//** - * @brief - * Power off the DCDC regulator. - * - * @details - * This function powers off the DCDC controller. This function should only be - * used if the external power circuit is wired for no DCDC. If the external power - * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the - * DCDC in bypass mode to disable DCDC. - * - * @return - * Return false if the DCDC could not be disabled. - ******************************************************************************/ -bool EMU_DCDCPowerOff(void) -{ - bool dcdcModeSet; - -#if defined(_EMU_PWRCFG_MASK) - /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ - EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; -#endif - - /* Select DVDD as input to the digital regulator. */ -#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; -#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) - EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; -#endif - - /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required - mode could be set. */ - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; - - dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); - EFM_ASSERT(dcdcModeSet); - - return dcdcModeSet; -} - -/***************************************************************************//** - * @brief - * Set DCDC LN regulator conduction mode. - * - * @param[in] conductionMode - * DCDC LN conduction mode. - * @param[in] rcoDefaultSet - * The default DCDC RCO band for the conductionMode will be used if true. - * Otherwise, the current RCO configuration is used. - ******************************************************************************/ -void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, - bool rcoDefaultSet) -{ - EMU_DcdcMode_TypeDef currentDcdcMode - = (EMU_DcdcMode_TypeDef)((uint32_t) - (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); - EMU_DcdcLnRcoBand_TypeDef rcoBand - = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) - ((EMU->DCDCLNFREQCTRL - & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); - - /* Set bypass mode and wait for bypass mode to settle before - EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ - EMU_IntClear(EMU_IFC_DCDCINBYPASS); - EMU_DCDCModeSet(emuDcdcMode_Bypass); - while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { - } - while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { - } - if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { - EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; - if (rcoDefaultSet) { - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); - } else { - /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ - EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); - } - } else { - EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; - if (rcoDefaultSet) { - EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); - } - } - EMU_DCDCModeSet(currentDcdcMode); - /* Update slice configuration as it depends on conduction mode and RCO band.*/ - EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); -} - -/***************************************************************************//** - * @brief - * Set the DCDC output voltage. - * - * @note - * The DCDC is not characterized for the entire valid output voltage range. - * For that reason an upper limit of 3.0V output voltage is enforced. - * - * @param[in] mV - * Target DCDC output voltage in mV. - * - * @param[in] setLpVoltage - * Update LP voltage - * - * @param[in] setLnVoltage - * Update LN voltage - * - * @return - * True if the mV parameter is valid. - ******************************************************************************/ -bool EMU_DCDCOutputVoltageSet(uint32_t mV, - bool setLpVoltage, - bool setLnVoltage) -{ -#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - - bool validOutVoltage; - bool attenuationSet; - uint32_t mVlow = 0; - uint32_t mVhigh = 0; - uint32_t mVdiff; - uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; - uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; - uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; - uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; - - /* Check that the set voltage is within valid range. - Voltages are obtained from the data sheet. */ - validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) - && (mV <= PWRCFG_DCDCTODVDD_VMAX); - - if (!validOutVoltage) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* Set attenuation to use and low/high range. */ - attenuationSet = mV > 1800U; - if (attenuationSet) { - mVlow = 1800; - mVhigh = 3000; - mVdiff = mVhigh - mVlow; - } else { - mVlow = 1200; - mVhigh = 1800; - mVdiff = mVhigh - mVlow; - } - - /* Get 2-point calibration data from DEVINFO. */ - - /* LN mode */ - if (attenuationSet) { - vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; - vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; - vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; - } else { - vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; - vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; - vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) - >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; - } - - /* LP EM234H mode */ - lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) - ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) - >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); - lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], - &vrefHigh[dcdcTrimMode_EM234H_LP], - attenuationSet, - lpcmpBias[dcdcTrimMode_EM234H_LP]); - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* LP EM01 mode */ - lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) - ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); - lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], - &vrefHigh[dcdcTrimMode_EM01_LP], - attenuationSet, - lpcmpBias[dcdcTrimMode_EM01_LP]); -#endif - - /* Calculate output voltage trims. */ - vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) - / mVdiff; - vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; - - vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) - / mVdiff; - vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) - / mVdiff; - vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; -#endif - - /* Range checks */ - if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) - || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) - || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) -#endif - || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) - || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* Update output voltage tuning for LN and LP modes. */ - if (setLnVoltage) { - EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) - | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) - | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); - } - - if (setLpVoltage) { - /* Load LP EM234H comparator hysteresis calibration. */ - if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - -#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) - /* Load LP EM234H comparator hysteresis calibration. */ - if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { - EFM_ASSERT(false); - /* Return when assertions are disabled. */ - return false; - } - - /* LP VREF is that maximum of trims for EM01 and EM234H. */ - vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); -#endif - - /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ - vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); - EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) - | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) - | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); - } -#endif - return true; -} - -/***************************************************************************//** - * @brief - * Optimize the DCDC slice count based on the estimated average load current - * in EM0. - * - * @param[in] em0LoadCurrentmA - * Estimated average EM0 load current in mA. - ******************************************************************************/ -void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) -{ - uint32_t sliceCount = 0; - uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; - - /* Set the recommended slice count. */ - if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) - && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { - if (em0LoadCurrentmA < 20U) { - sliceCount = 4; - } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) - && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { - if (em0LoadCurrentmA < 10U) { - sliceCount = 4; - } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) - && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { - if (em0LoadCurrentmA < 40U) { - sliceCount = 8; - } else { - sliceCount = 16; - } - } else { - /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended - configuration. */ - EFM_ASSERT(false); - } - - /* The selected slices are PSLICESEL + 1. */ - sliceCount--; - - /* Apply slice count to both N and P slice. */ - sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT - | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); - EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK - | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) - | sliceCount; - - /* Update the current limiters. */ - currentLimitersUpdate(); -} - -/***************************************************************************//** - * @brief - * Set DCDC Low-noise RCO band. - * - * @param[in] band - * RCO band to set. - ******************************************************************************/ -void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) -{ - uint32_t forcedCcm; - forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); - - /* DCM mode supports up to 4 MHz LN RCO. */ - EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) - || (forcedCcm != 0U)); - - EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) - | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); - - /* Update slice configuration as this depends on the RCO band. */ - EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); -} -#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/***************************************************************************//** - * @brief - * Configure the DCDC Boost regulator. - * - * @param[in] dcdcBoostInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) -{ - bool dcdcLocked; - - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif - - DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) - | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); - DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) - | ((uint32_t)dcdcBoostInit->peakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT); - DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) - | ((uint32_t)dcdcBoostInit->peakCurrentEM23 << _DCDC_BSTEM23CTRL_IPKVAL_SHIFT); - - EMU_BoostExternalShutdownEnable(dcdcBoostInit->externalShutdownEn); - - EMU_DCDCModeSet(emuDcdcMode_Regulation); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - - return true; -} - -/***************************************************************************//** - * @brief - * Set EM01 mode Boost Peak Current setting. - * - * @param[in] boostPeakCurrentEM01 - * Boost Peak load current coefficient in EM01 mode. - ******************************************************************************/ -void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - /* Wait for synchronization before writing new value */ -#if defined(_DCDC_SYNCBUSY_MASK) - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif - - BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, - _DCDC_BSTEM01CTRL_IPKVAL_MASK, - ((uint32_t)boostPeakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT)); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} - -/***************************************************************************//** - * @brief - * Enable/disable Boost External Shutdown Mode. - * - * @param[in] enable - * The boost DC-DC converter can be activated or deactivated - * from a dedicated BOOST_EN pin on the device if enable is true. - ******************************************************************************/ -void EMU_BoostExternalShutdownEnable(bool enable) -{ - if (enable) { - EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; - } else { - EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; - } -} -#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ - || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) -/***************************************************************************//** - * @brief - * Indicate that the DCDC peripheral bus clock enable has changed allowing - * RAIL to react accordingly. - * - * @details - * This function is called after DCDC has been enabled or disabled. - * The function implementation does not perform anything, but it is SL_WEAK - * so that it can use the RAIL version if needed. - ******************************************************************************/ -SL_WEAK void EMU_DCDCUpdatedHook(void) -{ -} - -/***************************************************************************//** - * @brief - * Set DCDC regulator operating mode. - * - * @param[in] dcdcMode - * DCDC mode. - * @return - * Returns the status of the DCDC mode set operation. - * @verbatim - * SL_STATUS_OK - Operation completed successfully. - * SL_STATUS_TIMEOUT - Operation EMU DCDC set mode timeout. - * @endverbatim - ******************************************************************************/ -sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) -{ - bool dcdcLocked; - uint32_t currentDcdcMode; - sl_status_t error = SL_STATUS_OK; - uint32_t timeout = 0; - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - if (dcdcMode == emuDcdcMode_Bypass) { -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_CTRL_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_CTRL); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif - currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT; - - if (currentDcdcMode != emuDcdcMode_Bypass) { - /* Switch to BYPASS mode if it is not the current mode */ - DCDC->CTRL_CLR = DCDC_CTRL_MODE; - while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for BYPASS switch enable. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } - } -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_CLR = DCDC_EN_EN; -#endif - } else { - while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for VREGIN voltage to rise above threshold. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } else { - DCDC->IF_CLR = DCDC_IF_REGULATION; - DCDC->CTRL_SET = DCDC_CTRL_MODE; - timeout = 0; - while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { - /* Wait for DCDC to complete it's startup. */ - timeout++; - } - if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { - error = SL_STATUS_TIMEOUT; - } - } - } - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - return error; -} -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT || EMU_SERIES2_DCDC_BOOST_PRESENT */ - -#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) -/***************************************************************************//** - * @brief - * Configure the DCDC regulator. - * - * @param[in] dcdcInit - * The DCDC initialization structure. - * - * @return - * True if initialization parameters are valid. - ******************************************************************************/ -bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) -{ - bool dcdcLocked; - - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; -#if defined(_DCDC_EN_EN_MASK) - DCDC->EN_SET = DCDC_EN_EN; -#endif - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold - << _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT) - | EMU_VREGVDDCMPCTRL_VREGINCMPEN; - -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_CTRL_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_CTRL | DCDC_SYNCBUSY_EM01CTRL0 | DCDC_SYNCBUSY_EM23CTRL0); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif -#if defined(_DCDC_CTRL_DCMONLYEN_MASK) - DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK - | _DCDC_CTRL_DCMONLYEN_MASK)) - | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT) - | ((uint32_t)(dcdcInit->dcmOnlyEn ? 1U : 0U) << _DCDC_CTRL_DCMONLYEN_SHIFT); -#else - DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK)) - | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT); -#endif - DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT) - | ((uint32_t)dcdcInit->peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT); - DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT) - | ((uint32_t)dcdcInit->peakCurrentEM23 << _DCDC_EM23CTRL0_IPKVAL_SHIFT); - - EMU_DCDCModeSet(dcdcInit->mode); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - EMU_DCDCUpdatedHook(); - - return true; -} - -/***************************************************************************//** - * @brief - * Power off the DCDC regulator. - * - * @return - * Returns true. - ******************************************************************************/ -bool EMU_DCDCPowerOff(void) -{ - EMU_DCDCModeSet(emuDcdcMode_Bypass); - return true; -} - -/***************************************************************************//** - * @brief - * Set EMO1 mode Peak Current setting. - * - * @param[in] peakCurrentEM01 - * Peak load current coefficient in EM01 mode. - ******************************************************************************/ -void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - -#if defined(_DCDC_EN_EN_MASK) - bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0); - DCDC->EN_SET = DCDC_EN_EN; -#endif - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - - /* Wait for synchronization before writing new value */ -#if defined(_DCDC_SYNCBUSY_MASK) -#if defined(_DCDC_SYNCBUSY_EM01CTRL0_MASK) - EMU_DCDCSync(DCDC_SYNCBUSY_EM01CTRL0); -#else - EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); -#endif -#endif - - BUS_RegMaskedWrite(&DCDC->EM01CTRL0, - _DCDC_EM01CTRL0_IPKVAL_MASK, - ((uint32_t)peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT)); - -#if defined(_DCDC_EN_EN_MASK) - if (!dcdcWasEnabled) { - DCDC->EN_CLR = DCDC_EN_EN; - } -#endif - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} - -#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) -/***************************************************************************//** - * @brief - * Set PFMX mode Peak Current setting. - * - * @param[in] value - * Peak load current coefficient in PFMX mode. - ******************************************************************************/ -void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - /* Verification that the parameter is in range. */ - /* if not, restrict value to maximum allowed. */ - EFM_ASSERT(value <= (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)); - if (value > (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)) { - value = (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT); - } - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - /* Wait for synchronization before writing new value */ - EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); -#endif - - DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK) - | value << _DCDC_PFMXCTRL_IPKVAL_SHIFT); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} -#endif /* _DCDC_PFMXCTRL_IPKVAL_MASK */ - -#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) -/***************************************************************************//** - * @brief - * Set Ton_max timeout control. - * - * @param[in] value - * Maximum time for peak current detection. - ******************************************************************************/ -void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) -{ - bool dcdcLocked = false; - bool dcdcClkWasEnabled = false; - - dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; - - dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); - EMU_DCDCUnlock(); - -#if defined(_DCDC_SYNCBUSY_MASK) - /* Wait for synchronization before writing new value */ - EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); -#endif - - DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) - | value << _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT); - - if (dcdcLocked) { - EMU_DCDCLock(); - } - - if (!dcdcClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; - } - - EMU_DCDCUpdatedHook(); -} -#endif /* _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK */ -#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ - -#if defined(EMU_STATUS_VMONRDY) - -/***************************************************************************//** - * @brief - * Get the calibrated threshold value. - * - * @details - * All VMON channels have two calibration fields in the DI page that - * describes the threshold at 1.86 V and 2.98 V. This function will convert - * the uncalibrated input voltage threshold in millivolts into a calibrated - * threshold. - * - * @param[in] channel - * A VMON channel. - * - * @param[in] threshold - * A desired threshold in millivolts. - * - * @return - * A calibrated threshold value to use. The first digit of the return value is placed - * in the "fine" register fields while the next digits are placed in the - * "coarse" register fields. - ******************************************************************************/ -static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, - int threshold) -{ - uint32_t tDiff = 0; - uint32_t tLow = 0; - uint32_t tHigh = 0; - uint32_t calReg; - - /* Get calibration values for 1.86 V and 2.98 V */ - switch (channel) { - case emuVmonChannel_AVDD: - calReg = DEVINFO->VMONCAL0; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_ALTAVDD: - calReg = DEVINFO->VMONCAL0; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_DVDD: - calReg = DEVINFO->VMONCAL1; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); - break; - case emuVmonChannel_IOVDD0: - calReg = DEVINFO->VMONCAL1; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - calReg = DEVINFO->VMONCAL2; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - calReg = DEVINFO->VMONCAL2; - tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); - tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) - + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) - >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); - break; -#endif - default: - EFM_ASSERT(false); - break; - } - - tDiff = tHigh - tLow; - if (tDiff > 0) { - /* Calculate threshold. - * - * Note that volt is used in the reference manual. However, the results - * should be in millivolts. The precision of Va and Vb are increased in the - * calculation instead of using floating points. - */ - uint32_t va = (1120U * 100U) / (tDiff); - uint32_t vb = (1860U * 100U) - (va * tLow); - // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. - if (va != 0) { - /* Round the threshold to the nearest integer value. */ - return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; - } - } - - /* Uncalibrated device guard. */ - return (uint32_t)threshold; -} - -/***************************************************************************//** - * @brief - * Initialize a VMON channel. - * - * @details - * Initialize a VMON channel without hysteresis. If the channel supports - * separate rise and fall triggers, both thresholds will be set to the same - * value. The threshold will be converted to a register field value based - * on calibration values from the DI page. - * - * @param[in] vmonInit - * The VMON initialization structure. - ******************************************************************************/ -void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) -{ - uint32_t thresholdCoarse, thresholdFine; - uint32_t threshold; - - EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); - - threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); - thresholdFine = threshold % 10U; - thresholdCoarse = threshold / 10U; - - /* Saturate the threshold to maximum values. */ - if (thresholdCoarse > 0xFU) { - thresholdCoarse = 0xF; - thresholdFine = 9; - } - - switch (vmonInit->channel) { - case emuVmonChannel_AVDD: - EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) - | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); - break; - case emuVmonChannel_ALTAVDD: - EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); - break; - case emuVmonChannel_DVDD: - EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); - break; - case emuVmonChannel_IOVDD0: - EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) - | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) - | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) - | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) - | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) - | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); - break; -#endif - default: - EFM_ASSERT(false); - return; - } -} - -/***************************************************************************//** - * @brief - * Initialize a VMON channel with hysteresis (separate rise and fall triggers). - * - * @details - * Initialize a VMON channel which supports hysteresis. The AVDD channel is - * the only channel to support separate rise and fall triggers. The rise and - * fall thresholds will be converted to a register field value based on the - * calibration values from the DI page. - * - * @param[in] vmonInit - * The VMON hysteresis initialization structure. - ******************************************************************************/ -void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) -{ - uint32_t riseThreshold; - uint32_t fallThreshold; - - /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ - EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); - EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); - /* The fall threshold has to be lower than rise threshold. */ - EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); - - riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); - fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); - - switch (vmonInit->channel) { - case emuVmonChannel_AVDD: - EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) - | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) - | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) - | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) - | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) - | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) - | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); - break; - default: - EFM_ASSERT(false); - return; - } -} - -/***************************************************************************//** - * @brief - * Enable or disable a VMON channel. - * - * @param[in] channel - * A VMON channel to enable/disable. - * - * @param[in] enable - * Indicates whether to enable or disable. - ******************************************************************************/ -void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) -{ - uint32_t volatile * reg; - uint32_t bit; - - switch (channel) { - case emuVmonChannel_AVDD: - reg = &(EMU->VMONAVDDCTRL); - bit = _EMU_VMONAVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_ALTAVDD: - reg = &(EMU->VMONALTAVDDCTRL); - bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_DVDD: - reg = &(EMU->VMONDVDDCTRL); - bit = _EMU_VMONDVDDCTRL_EN_SHIFT; - break; - case emuVmonChannel_IOVDD0: - reg = &(EMU->VMONIO0CTRL); - bit = _EMU_VMONIO0CTRL_EN_SHIFT; - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - reg = &(EMU->VMONIO1CTRL); - bit = _EMU_VMONIO1CTRL_EN_SHIFT; - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - reg = &(EMU->VMONBUVDDCTRL); - bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; - break; -#endif - default: - EFM_ASSERT(false); - return; - } - - BUS_RegBitWrite(reg, bit, (uint32_t)enable); -} - -/***************************************************************************//** - * @brief - * Get the status of a voltage monitor channel. - * - * @param[in] channel - * A VMON channel to get the status for. - * - * @return - * A status of the selected VMON channel. True if the channel is triggered. - ******************************************************************************/ -bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) -{ - uint32_t bit; - switch (channel) { - case emuVmonChannel_AVDD: - bit = _EMU_STATUS_VMONAVDD_SHIFT; - break; - case emuVmonChannel_ALTAVDD: - bit = _EMU_STATUS_VMONALTAVDD_SHIFT; - break; - case emuVmonChannel_DVDD: - bit = _EMU_STATUS_VMONDVDD_SHIFT; - break; - case emuVmonChannel_IOVDD0: - bit = _EMU_STATUS_VMONIO0_SHIFT; - break; -#if defined(_EMU_VMONIO1CTRL_EN_MASK) - case emuVmonChannel_IOVDD1: - bit = _EMU_STATUS_VMONIO1_SHIFT; - break; -#endif -#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) - case emuVmonChannel_BUVDD: - bit = _EMU_STATUS_VMONBUVDD_SHIFT; - break; -#endif - default: - bit = 0; - EFM_ASSERT(false); - break; - } - - return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; -} -#endif /* EMU_STATUS_VMONRDY */ - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/***************************************************************************//** - * @brief - * Adjust the bias refresh rate. - * - * @details - * This function is only meant to be used under high-temperature operation on - * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will - * increase the typical current consumption. See application note 1027 - * and errata documents for more details. - * - * @param [in] mode - * The new bias refresh rate. - ******************************************************************************/ -void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) -{ - uint32_t freq = 0x2u; - bool emuTestLocked = false; - - if (mode == emuBiasMode_1KHz) { - freq = 0x0u; - } - - if (EMU_TESTLOCK == 0x1u) { - emuTestLocked = true; - EMU_TESTLOCK = 0xADE8u; - } - - if (mode == emuBiasMode_Continuous) { - EMU_BIASCONF &= ~0x74u; - } else { - EMU_BIASCONF |= 0x74u; - } - - EMU_BIASTESTCTRL |= 0x8u; - CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) - | ((freq & 0x3u) << 10u); - EMU_BIASTESTCTRL &= ~0x8u; - - if (emuTestLocked) { - EMU_TESTLOCK = 0u; - } -} -#endif - -#if defined(_EMU_TEMP_TEMP_MASK) -/***************************************************************************//** - * @brief - * Get temperature in degrees Celsius - * - * @return - * Temperature in degrees Celsius - ******************************************************************************/ -float EMU_TemperatureGet(void) -{ -#if defined(_EMU_TEMP_TEMPLSB_MASK) - return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) - >> _EMU_TEMP_TEMPLSB_SHIFT) - ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; -#else - uint32_t val1; - uint32_t val2; - float tempCo; - uint32_t diTemp, diEmu; - - // Calculate calibration temp based on DI page values - diTemp = ((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); - diEmu = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); - tempCo = EMU_TEMPCO_CONST + (diEmu / 100.0f); - - // Read temperature twice to ensure a stable value - do { - val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) - >> _EMU_TEMP_TEMP_SHIFT; - val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) - >> _EMU_TEMP_TEMP_SHIFT; - } while (val1 != val2); - - return diTemp + tempCo * ((int) diEmu - (int) val1); -#endif -} -#endif // defined(_EMU_TEMP_TEMP_MASK) - -#if defined(EMU_CTRL_EFPDIRECTMODEEN) -/***************************************************************************//** - * @brief - * Enable/disable EFP Direct Mode. - * - * @param[in] enable - * True to enable direct mode. - ******************************************************************************/ -void EMU_EFPDirectModeEnable(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; - } -} -#endif - -#if defined(EMU_CTRL_EFPDRVDECOUPLE) -/***************************************************************************//** - * @brief - * Set to enable EFP to drive Decouple voltage. - * - * @details - * Once set, internal LDO will be disabled, and the EMU will control EFP for - * voltage-scaling. Note that because this bit disables the internal LDO - * powering the core, it should not be set until after EFP's DECOUPLE output has - * been configured and enabled. - * - * @param[in] enable - * True to enable EFP to drive Decouple voltage. - ******************************************************************************/ -void EMU_EFPDriveDecoupleSet(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; - } -} -#endif - -#if defined(EMU_CTRL_EFPDRVDVDD) -/***************************************************************************//** - * @brief - * Set to enable EFP to drive DVDD voltage. - * - * @details - * Set this if EFP's DCDC output is powering DVDD supply. This mode assumes that - * internal DCDC is not being used. - * - * @param[in] enable - * True to enable EFP to drive DVDD voltage. - ******************************************************************************/ -void EMU_EFPDriveDvddSet(bool enable) -{ - if (enable) { - EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; - } else { - EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; - } -} -#endif - -/** @} (end addtogroup emu) */ -#endif /* __EM_EMU_H */ +/***************************************************************************//** + * @file + * @brief Energy Management Unit (EMU) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include + +#include "em_emu.h" +#if defined(EMU_PRESENT) && (EMU_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" +#include "em_ramfunc.h" + +#if defined(SL_CATALOG_METRIC_EM23_WAKE_PRESENT) +#include "sli_metric_em23_wake.h" +#include "sli_metric_em23_wake_config.h" +#endif + +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) +#include "sli_metric_em4_wake.h" +#endif + +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/* Consistency check, since restoring assumes similar bit positions in */ +/* CMU OSCENCMD and STATUS regs. */ +#if defined(CMU_STATUS_AUXHFRCOENS) && (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN) +#error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_HFXOENS) && (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN) +#error Conflict in HFXOENS and HFXOEN bitpositions +#endif +#if defined(CMU_STATUS_LFRCOENS) && (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN) +#error Conflict in LFRCOENS and LFRCOEN bitpositions +#endif +#if defined(CMU_STATUS_LFXOENS) && (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN) +#error Conflict in LFXOENS and LFXOEN bitpositions +#endif + +/******************************************************************************* + ****************************** DEFINES ************************************ + ******************************************************************************/ +#if defined(_SILICON_LABS_32B_SERIES_0) +/* Fix for errata EMU_E107 - non-WIC interrupt masks. */ +#if defined(_EFM32_GECKO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x0dfc0323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_TINY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x001be323U)) +#define NON_WIC_INT_MASK_1 (~(0x0U)) + +#elif defined(_EFM32_GIANT_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_WONDER_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0xff020e63U)) +#define NON_WIC_INT_MASK_1 (~(0x00000046U)) + +#elif defined(_EFM32_ZERO_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00005c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#elif defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E107_ENABLE +#define NON_WIC_INT_MASK_0 (~(0x00085c6bU)) +#define NON_WIC_INT_MASK_1 (~(0x00000000U)) + +#endif +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_74) \ + || (defined(_SILICON_LABS_32B_SERIES_0) \ + && (defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY))) +// Fix for errata EMU_E110 - Potential Hard Fault when Exiting EM2. +#define ERRATA_FIX_EMU_E110_ENABLE +#endif + +/* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) +#define ERRATA_FIX_EMU_E108_ENABLE +#endif + +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_EMU_E208_ENABLE +#endif + +/* Enable FETCNT tuning errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_FETCNT_SET_ENABLE +#endif + +/* Enable LN handshake errata fix. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE +typedef enum { + errataFixDcdcHsInit, + errataFixDcdcHsTrimSet, + errataFixDcdcHsBypassLn, + errataFixDcdcHsLnWaitDone +} errataFixDcdcHs_TypeDef; +static errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit; +#endif + +/* Fix for errata for EFM32GG11 and EFM32TG11. If a device is entering EM4S + * while powering the analog peripherals from DVDD, firmware must switch + * over to powering the analog peripherals from AVDD and delay the EM4S entry + * with 30 us. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define ERRATA_FIX_EM4S_DELAY_ENTRY +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + && !defined(ERRATA_FIX_EMU_E220_DECBOD_IGNORE) +/* EMU_E220 DECBOD Errata fix. DECBOD Reset can occur + * during voltage scaling after EM2/3 wakeup. */ +#define ERRATA_FIX_EMU_E220_DECBOD_ENABLE +#define EMU_PORBOD (*(volatile uint32_t *) (EMU_BASE + 0x14C)) +#define EMU_PORBOD_GMC_CALIB_DISABLE (0x1UL << 31) +#endif + +/* Used to figure out if a memory address is inside or outside of a RAM block. + * A memory address is inside a RAM block if the address is greater than the + * RAM block address. */ +#define ADDRESS_NOT_IN_BLOCK(addr, block) ((addr) <= (block) ? 1UL : 0UL) + +/* RAM Block layout for various device families. Note that some devices + * have special layout in RAM0 and some devices have a special RAM block + * at the end of their block layout. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x10000U // 64 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +#define RAM0_BLOCKS 2U +#define RAM0_BLOCK_SIZE 0x4000U +#define RAM1_BLOCKS 2U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#define RAM0_BLOCKS 1U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM1_BLOCKS 1U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB block +#define RAM2_BLOCKS 1U +#define RAM2_BLOCK_SIZE 0x800U // 2 kB block +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x2000U // 8 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GECKO_FAMILY) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x1000U // 4 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) +#define RAM0_BLOCKS 8U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 8U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x10000U // 64 kB blocks +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM1_BLOCKS 4U +#define RAM1_BLOCK_SIZE 0x4000U // 16 kB blocks +#define RAM2_BLOCKS 4U +#define RAM2_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#define RAM0_BLOCKS 6U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) +#define RAM0_BLOCKS 4U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x8000U // 32 kB blocks +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define RAM0_BLOCKS 16U +#define RAM0_BLOCK_SIZE 0x4000U // 16 kB blocks +#endif + +#if defined(_SILICON_LABS_32B_SERIES_0) +/* RAM_MEM_END on Gecko devices have a value larger than the SRAM_SIZE. */ +#define RAM0_END (SRAM_BASE + SRAM_SIZE - 1) +#else +#define RAM0_END RAM_MEM_END +#endif + +#if defined(CMU_STATUS_HFXOSHUNTOPTRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY | CMU_STATUS_HFXOSHUNTOPTRDY) +#elif defined(CMU_STATUS_HFXOPEAKDETRDY) +#define HFXO_STATUS_READY_FLAGS (CMU_STATUS_HFXOPEAKDETRDY) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#if !defined(PWRCFG_DCDCTODVDD_VMIN) +/** DCDCTODVDD output range maximum. */ +#define PWRCFG_DCDCTODVDD_VMIN 1800U +#endif +#if !defined(PWRCFG_DCDCTODVDD_VMAX) +/** DCDCTODVDD output range minimum. */ +#define PWRCFG_DCDCTODVDD_VMAX 3000U +#endif +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) || defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +#define DCDC_LP_PFET_CNT 7 +#define DCDC_LP_NFET_CNT 7 +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +#define EMU_DCDCSTATUS (*(volatile uint32_t *)(EMU_BASE + 0x7C)) +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/* Translate fields with different names across platform generations to common names. */ +#if defined(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT +#elif defined(_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK +#define _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT +#endif +#if defined(_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT +#elif defined(_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK +#define _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT +#endif + +/* Disable LP mode hysteresis in the state machine control. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) +/* Comparator threshold on the high side. */ +#define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) +#define EMU_DCDCSMCTRL (*(volatile uint32_t *)(EMU_BASE + 0x44)) + +#define DCDC_TRIM_MODES ((uint8_t)dcdcTrimMode_LN + 1) +#endif + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/* EMU DCDC MODE set timeout. */ +#define EMU_DCDC_MODE_SET_TIMEOUT 1000000 +#endif +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +#define EMU_TESTLOCK (*(volatile uint32_t *) (EMU_BASE + 0x190)) +#define EMU_BIASCONF (*(volatile uint32_t *) (EMU_BASE + 0x164)) +#define EMU_BIASTESTCTRL (*(volatile uint32_t *) (EMU_BASE + 0x19C)) +#define CMU_ULFRCOCTRL (*(volatile uint32_t *) (CMU_BASE + 0x03C)) +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/* As the energy mode at which a temperature measurement was taken at is + * not known, the chosen constant for the TEMPCO calculation is midway between + * the EM0/EM1 constant and the EM2/EM3/EM4 constant. + */ +#define EMU_TEMPCO_CONST (0.273f) +#endif + +#define EMU_EM4_ENTRY_WAIT_LOOPS 200 + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +/* Static user configuration. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +static uint16_t dcdcMaxCurrent_mA; +static uint16_t dcdcEm01LoadCurrent_mA; +static EMU_DcdcLnReverseCurrentControl_TypeDef dcdcReverseCurrentControl; +#endif +#if defined(EMU_VSCALE_EM01_PRESENT) +static EMU_EM01Init_TypeDef vScaleEM01Config = { false }; +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/* Convert from level to EM0/1 command bit */ +__STATIC_INLINE uint32_t vScaleEM01Cmd(EMU_VScaleEM01_TypeDef level) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + return EMU_CMD_EM01VSCALE1 << ((uint32_t)level - _EMU_STATUS_VSCALE_VSCALE1); +#else + return EMU_CMD_EM01VSCALE0 << (_EMU_STATUS_VSCALE_VSCALE0 - (uint32_t)level); +#endif +} +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) + __WFI(); // Enter EM2 or EM3 + if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) { + for (volatile int i = 0; i < 6; i++) { + } // Dummy wait loop ... + } + +#else + __WFI(); // Enter EM2 or EM3 +#if defined(__GNUC__) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" +#endif + *(volatile uint32_t*)4; // Clear faulty read data after wakeup +#if defined(__GNUC__) +#pragma GCC diagnostic pop +#endif +#endif +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) +SL_RAMFUNC_DECLARATOR static void __attribute__ ((noinline)) ramWFI(void); +SL_RAMFUNC_DEFINITION_BEGIN +static void __attribute__ ((noinline)) ramWFI(void) +{ + /* Second part of EMU_E220 DECBOD Errata fix. Calibration needs to be disabled + * quickly when coming out of EM2/EM3. Ram execution is needed to meet timing. + * Calibration is re-enabled after voltage scaling completes. */ + uint32_t temp = EMU_PORBOD | EMU_PORBOD_GMC_CALIB_DISABLE; + __WFI(); + EMU_PORBOD = temp; +} +SL_RAMFUNC_DEFINITION_END +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) +/***************************************************************************//** + * @brief + * Save/restore/update oscillator, core clock and voltage scaling configuration on + * EM2 or EM3 entry/exit. + * + * @details + * Hardware may automatically change the oscillator and the voltage scaling configuration + * when going into or out of an energy mode. Static data in this function keeps track of + * such configuration bits and is used to restore state if needed. + * + ******************************************************************************/ +typedef enum { + emState_Save, /* Save EMU and CMU state. */ + emState_Restore, /* Restore and unlock. */ +} emState_TypeDef; + +static void emState(emState_TypeDef action) +{ + uint32_t oscEnCmd; + uint32_t cmuLocked; + static uint32_t cmuStatus; + static CMU_Select_TypeDef hfClock; +#if defined(EMU_VSCALE_PRESENT) + static uint8_t vScaleStatus; + static uint32_t hfrcoCtrl; +#endif + + /* Save or update state. */ + if (action == emState_Save) { + /* Save configuration. */ + cmuStatus = CMU->STATUS; + hfClock = CMU_ClockSelectGet(cmuClock_HF); +#if defined(EMU_VSCALE_PRESENT) + /* Save vscale. */ + EMU_VScaleWait(); + vScaleStatus = (uint8_t)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) + >> _EMU_STATUS_VSCALE_SHIFT); + hfrcoCtrl = CMU->HFRCOCTRL; +#endif + } else { /* Restore state. */ + /* Apply saved configuration. */ +#if defined(EMU_VSCALE_PRESENT) +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == true) + /* Restore voltage scaling level if LDO regulator is on. */ +#endif + { + /* Restore EM0 and 1 voltage scaling level. + @ref EMU_VScaleWait() is called later, + just before HF clock select is set. */ + EMU->CMD = vScaleEM01Cmd((EMU_VScaleEM01_TypeDef)vScaleStatus); + } +#endif + /* CMU registers may be locked. */ + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + +#if defined(_CMU_OSCENCMD_MASK) + /* AUXHFRCO are automatically disabled (except if using debugger). */ + /* HFRCO, USHFRCO and HFXO are automatically disabled. */ + /* LFRCO/LFXO may be disabled by SW in EM3. */ + /* Restore according to status prior to entering energy mode. */ + oscEnCmd = 0; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFRCOENS) != 0U + ? CMU_OSCENCMD_HFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_AUXHFRCOENS) != 0U + ? CMU_OSCENCMD_AUXHFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFRCOENS) != 0U + ? CMU_OSCENCMD_LFRCOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_HFXOENS) != 0U + ? CMU_OSCENCMD_HFXOEN : 0U; + oscEnCmd |= (cmuStatus & CMU_STATUS_LFXOENS) != 0U + ? CMU_OSCENCMD_LFXOEN : 0U; +#if defined(_CMU_STATUS_USHFRCOENS_MASK) + oscEnCmd |= (cmuStatus & CMU_STATUS_USHFRCOENS) != 0U + ? CMU_OSCENCMD_USHFRCOEN : 0U; +#endif + CMU->OSCENCMD = oscEnCmd; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) + /* Wait for upscale to complete and then restore selected clock. */ + EMU_VScaleWait(); + if ((EMU->CTRL & _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK) != 0U) { + /* Restore HFRCO frequency which was automatically adjusted by hardware. */ + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0U) { + } + CMU->HFRCOCTRL = hfrcoCtrl; + if (hfClock == cmuSelect_HFRCO) { + /* Optimize wait state after EM2/EM3 wakeup because hardware has + * modified them. */ + CMU_UpdateWaitStates(SystemHfrcoFreq, (int)EMU_VScaleGet()); + } + } +#endif + + switch (hfClock) { + case cmuSelect_LFXO: + CMU_CLOCK_SELECT_SET(HF, LFXO); + break; + case cmuSelect_LFRCO: + CMU_CLOCK_SELECT_SET(HF, LFRCO); + break; + case cmuSelect_HFXO: + CMU_CLOCK_SELECT_SET(HF, HFXO); + break; +#if defined(CMU_CMD_HFCLKSEL_USHFRCODIV2) + case cmuSelect_USHFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, USHFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_HFRCODIV2) + case cmuSelect_HFRCODIV2: + CMU_CLOCK_SELECT_SET(HF, HFRCODIV2); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_CLKIN0) + case cmuSelect_CLKIN0: + CMU_CLOCK_SELECT_SET(HF, CLKIN0); + break; +#endif +#if defined(CMU_HFCLKSTATUS_SELECTED_USHFRCO) + case cmuSelect_USHFRCO: + CMU_CLOCK_SELECT_SET(HF, USHFRCO); + break; +#endif + } + +#if defined(_CMU_OSCENCMD_MASK) + /* If HFRCO was disabled before entering Energy Mode, turn it off again */ + /* as it is automatically enabled by wake up */ + if ((cmuStatus & CMU_STATUS_HFRCOENS) == 0U) { + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; + } +#endif + + /* Restore CMU register locking */ + if (cmuLocked != 0U) { + CMU_Lock(); + } + } +} +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) +/* Get enable conditions for errata EMU_E107 fix. */ +__STATIC_INLINE bool getErrataFixEmuE107En(void) +{ +#if defined(_EFM32_HAPPY_FAMILY) \ + || defined(_EFM32_TINY_FAMILY) \ + || defined(_EFM32_WONDER_FAMILY) \ + || defined(_EFM32_ZERO_FAMILY) + // all revisions have the errata + return true; +#else + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_EFM32_GECKO_FAMILY) + // all GECKO revisions except Revision E have the errata + return (majorMinorRev <= 0x0103); +#elif defined(_EFM32_GIANT_FAMILY) + // all LEOPARD GECKO (Major = 0x01 Or 0x02) revisions have the errata + // all GIANT GECKO (Major = 0x01) revisions except Revision E have the errata + return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204) || (majorMinorRev == 0x0205); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +#endif /* #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY) #else */ +} +#endif /* #if defined(ERRATA_FIX_EMU_E107_ENABLE) */ + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +/* Get enable conditions for errata EMU_E110 fix. */ +__STATIC_INLINE bool getErrataFixEmuE110En(void) +{ + /* SYSTEM_ChipRevisionGet() could have been used here, but a faster implementation + * would be needed in this case. + */ + uint16_t majorMinorRev; + + /* CHIP MAJOR bit [3:0]. */ + majorMinorRev = ((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT) + << 8; + /* CHIP MINOR bit [7:4]. */ + majorMinorRev |= ((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) + << 4; + /* CHIP MINOR bit [3:0]. */ + majorMinorRev |= (ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_ZERO_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_HAPPY_FAMILY) + return ((majorMinorRev == 0x0100 || majorMinorRev == 0x0101)); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_WONDER_FAMILY) + return (majorMinorRev == 0x0100); +#elif defined(_SILICON_LABS_32B_SERIES_0) && defined(_EFM32_GIANT_FAMILY) + return (majorMinorRev == 0x0204); +#else + /* Invalid configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; +#endif +} +#endif /* #if defined(ERRATA_FIX_EMU_E110_ENABLE) */ + +/* LP prepare / LN restore P/NFET count. */ +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) +static void currentLimitersUpdate(void); +static void dcdcFetCntSet(bool lpModeSet) +{ + uint32_t tmp; + static uint32_t emuDcdcMiscCtrlReg; + + if (lpModeSet) { + emuDcdcMiscCtrlReg = EMU->DCDCMISCCTRL; + tmp = EMU->DCDCMISCCTRL + & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK); + tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT) + | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = tmp; + currentLimitersUpdate(); + } else { + EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg; + currentLimitersUpdate(); + } +} +#endif + +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) +static void dcdcHsFixLnBlock(void) +{ + if ((errataFixDcdcHsState == errataFixDcdcHsTrimSet) + || (errataFixDcdcHsState == errataFixDcdcHsBypassLn)) { + /* Wait for LNRUNNING */ + if ((EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE) { + while (!(EMU_DCDCSTATUS & (0x1 << 16))) { + } + } + errataFixDcdcHsState = errataFixDcdcHsLnWaitDone; + } +} +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) +/* Configure EMU and CMU for EM2 and 3 voltage downscale. */ +static void vScaleDownEM23Setup(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* Wait until previous scaling is done. */ + EMU_VScaleWait(); + + uint32_t em23vs = (EMU->CTRL & _EMU_CTRL_EM23VSCALE_MASK) >> _EMU_CTRL_EM23VSCALE_SHIFT; + uint32_t em01vs = (EMU->STATUS & _EMU_STATUS_VSCALE_MASK) >> _EMU_STATUS_VSCALE_SHIFT; + + /* Inverse coding. */ + if (em23vs > em01vs) { + EMU->CTRL |= EMU_CTRL_EM23VSCALEAUTOWSEN; +#if defined(_MSC_RAMCTRL_RAMWSEN_MASK) + /* Set RAM wait states for safe EM2 wakeup. */ + BUS_RegMaskedSet(&MSC->RAMCTRL, (MSC_RAMCTRL_RAMWSEN + | MSC_RAMCTRL_RAM1WSEN + | MSC_RAMCTRL_RAM2WSEN)); +#endif + } else { + EMU->CTRL &= ~EMU_CTRL_EM23VSCALEAUTOWSEN; + } +} + +/* Handle automatic HFRCO adjustment that may have occurred during EM2/EM3. */ +static void vScaleAfterWakeup(void) +{ + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + /* The hardware may have updated the HFRCOCTRL register during EM2/EM3 + * entry if voltage scaling in EM2/EM3 is enabled. The hardware would + * then update the HFRCO frequency to 19 MHz automatically. */ + uint32_t freqRange = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_FREQRANGE_MASK) + >> _CMU_HFRCOCTRL_FREQRANGE_SHIFT; + if (freqRange == 0x08U) { + SystemHfrcoFreq = 19000000; + } + } +} +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) +typedef enum { + dpllState_Save, /* Save DPLL state. */ + dpllState_Restore, /* Restore DPLL. */ +} dpllState_TypeDef; + +/***************************************************************************//** + * @brief + * Save or restore DPLL state. + * + * @param[in] action + * Value to indicate saving DPLL state or restoring its state. + * + * @note + * The function is used in EMU_Save() and EMU_Restore() to handle the + * DPLL state before entering EM2 or EM3 and after exiting EM2 or EM3. + * The function is required for the EFR32xG22 and EFR32xG27 families. + * On those families devices, the DPLL is disabled automatically when + * entering EM2, EM3. But exiting EM2, EM3 won't re-enable automatically + * the DPLL. Hence, the software needs to re-enable the DPLL upon EM2/3 + * exit. + ******************************************************************************/ +static void dpllState(dpllState_TypeDef action) +{ + CMU_ClkDiv_TypeDef div; + static uint32_t dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + + if (action == dpllState_Save) { + dpllRefClk = CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED; + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; + if (DPLL0->EN == DPLL_EN_EN) { + /* DPLL is in use, save reference clock selection. */ + dpllRefClk = CMU->DPLLREFCLKCTRL; + } + } else { /* Restore */ + if ((dpllRefClk != CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED) + && (DPLL0->EN != DPLL_EN_EN)) { + /* Restore DPLL reference clock selection. */ + CMU->DPLLREFCLKCTRL = dpllRefClk; + /* Only wait for DPLL lock if HFRCODPLL is used as SYSCLK. */ + if (CMU_ClockSelectGet(cmuClock_SYSCLK) == cmuSelect_HFRCODPLL) { + /* Set HCLK prescaler to safe value to avoid overclocking while locking. */ + div = CMU_ClockDivGet(cmuClock_HCLK); + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 2U); + } + + /* Relock DPLL and wait for ready. */ + DPLL0->IF_CLR = DPLL_IF_LOCK | DPLL_IF_LOCKFAILLOW | DPLL_IF_LOCKFAILHIGH; + DPLL0->EN_SET = DPLL_EN_EN; + while ((DPLL0->IF & DPLL_IF_LOCK) == 0U) { + } + + /* Restore HCLK prescaler. */ + if (div == 1U) { + CMU_ClockDivSet(cmuClock_HCLK, 1U); + } + } else { + /* Relock DPLL and exit without waiting for ready. */ + DPLL0->EN_SET = DPLL_EN_EN; + } + } + } +} +#endif + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup emu EMU - Energy Management Unit + * @brief Energy Management Unit (EMU) Peripheral API + * @details + * This module contains functions to control the EMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The EMU handles the different low energy modes + * in Silicon Labs microcontrollers. + * @{ + ******************************************************************************/ + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 0 and 1 configuration. + * + * @param[in] em01Init + * Energy Mode 0 and 1 configuration structure. + ******************************************************************************/ +void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init) +{ + vScaleEM01Config.vScaleEM01LowPowerVoltageEnable = + em01Init->vScaleEM01LowPowerVoltageEnable; + EMU_VScaleEM01ByClock(0, true); +} +#endif + +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 2 and 3 configuration. + * + * @param[in] em23Init + * Energy Mode 2 and 3 configuration structure. + ******************************************************************************/ +void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init) +{ +#if defined(_EMU_CTRL_EMVREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EMVREG) + : (EMU->CTRL & ~EMU_CTRL_EMVREG); +#elif defined(_EMU_CTRL_EM23VREG_MASK) + EMU->CTRL = em23Init->em23VregFullEn ? (EMU->CTRL | EMU_CTRL_EM23VREG) + : (EMU->CTRL & ~EMU_CTRL_EM23VREG); +#else + (void)em23Init; +#endif + +#if defined(EMU_VSCALE_PRESENT) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM23VSCALE_MASK) + | ((uint32_t)em23Init->vScaleEM23Voltage << _EMU_CTRL_EM23VSCALE_SHIFT); +#if defined(CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) + if (em23Init->vScaleEM23Voltage == emuVScaleEM23_LowPower) { + /* Voltage scaling is not compatible with HFXO auto start and select. */ + EFM_ASSERT((CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1) == 0U); + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just prior to execution of the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PresleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is called by EMU_EnterEM2() and EMU_EnterEM3() functions + * just after wakeup from the WFI instruction. The function implementation + * does not perform anything, but it is SL_WEAK so that it can be re- + * implemented in application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 2/3 post-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM23PostsleepHook() but is reserved + * for EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM23PostsleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 2 (EM2). + * + * @details + * When entering EM2, high-frequency clocks are disabled, i.e., HFXO, HFRCO + * and AUXHFRCO (for AUXHFRCO, see exception note below). When re-entering + * EM0, HFRCO is re-enabled and the core will be clocked by the configured + * HFRCO band. This ensures a quick wakeup from EM2. + * + * However, prior to entering EM2, the core may have been using another + * oscillator than HFRCO. The @p restore parameter gives the user the option + * to restore all HF oscillators according to state prior to entering EM2, + * as well as the clock used to clock the core. This restore procedure is + * handled by SW. However, since handled by SW, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use the HFXO oscillator, which has been + * disabled during EM2 mode, this function will stall until the oscillator + * has stabilized. Stalling time can be reduced by adding interrupt + * support detecting stable oscillator, and an asynchronous switch to the + * original oscillator. See CMU documentation. Such a feature is however + * outside the scope of the implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can not be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO is re-enabled by this function, and NOT used to clock the core, + * this function will not wait for HFXO to stabilize. This must be considered + * by the application if trying to use features relying on that oscillator + * upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM2. It will thus remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If HFXO autostart and select is enabled by using CMU_HFXOAutostartEnable(), + * the automatic starting and selecting of the core clocks will be done, + * regardless of the @p restore parameter, when waking up on the wakeup + * sources corresponding to the autostart and select setting. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM2 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * Note that the hardware will automatically update the HFRCO frequency in the + * case where voltage scaling is used in EM2/EM3 and not in EM0/EM1. When the + * restore argument to this function is true then software will restore the + * original HFRCO frequency after EM2/EM3 wake up. If the restore argument is + * false then the HFRCO frequency is 19 MHz when coming out of EM2/EM3 and + * all wait states are at a safe value. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM2(bool restore) +{ +#if defined(SLI_METRIC_EM2_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM2_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + + EMU_EM23PresleepHook(); + EMU_EFPEM23PresleepHook(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EFPEM23PostsleepHook(); + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Enter energy mode 3 (EM3). + * + * @details + * When entering EM3, the high-frequency clocks are disabled by hardware, i.e., HFXO, + * HFRCO, and AUXHFRCO (for AUXHFRCO, see exception note below). In addition, + * the low-frequency clocks, i.e., LFXO and LFRCO are disabled by software. When + * re-entering EM0, HFRCO is re-enabled and the core will be clocked by the + * configured HFRCO band. This ensures a quick wakeup from EM3. + * + * However, prior to entering EM3, the core may have been using an + * oscillator other than HFRCO. The @p restore parameter gives the user the option + * to restore all HF/LF oscillators according to state prior to entering EM3, + * as well as the clock used to clock the core. This restore procedure is + * handled by software. However, since it is handled by software, it will not be restored + * before completing the interrupt function(s) waking up the core! + * + * @note + * If restoring core clock to use an oscillator other than HFRCO, this + * function will stall until the oscillator has stabilized. Stalling time + * can be reduced by adding interrupt support detecting stable oscillator, + * and an asynchronous switch to the original oscillator. See CMU + * documentation. This feature is, however, outside the scope of the + * implementation in this function. + * @note + * If ERRATA_FIX_EMU_E110_ENABLE is active, the core's SLEEPONEXIT feature + * can't be used. + * @note + * This function is incompatible with the Power Manager module. When the + * Power Manager module is present, it must be the one deciding at which + * EM level the device sleeps to ensure the application properly works. Using + * both at the same time could lead to undefined behavior in the application. + * @par + * If HFXO/LFXO/LFRCO are re-enabled by this function, and NOT used to clock + * the core, this function will not wait for those oscillators to stabilize. + * This must be considered by the application if trying to use features + * relying on those oscillators upon return. + * @par + * If a debugger is attached, the AUXHFRCO will not be disabled if enabled + * upon entering EM3. It will, therefore, remain enabled when returning to EM0 + * regardless of the @p restore parameter. + * @par + * If voltage scaling is supported, the restore parameter is true and the EM0 + * voltage scaling level is set higher than the EM3 level, then the EM0 level is + * also restored. + * @par + * On Series 2 Config 2 devices (EFRxG22), this function will also relock the + * DPLL if the DPLL is used and @p restore is true. + * + * @param[in] restore + * @li true - save and restore oscillators, clocks and voltage scaling, see + * function details. + * @li false - do not save and restore oscillators and clocks, see function + * details. + * @par + * The @p restore option should only be used if all clock control is done + * via the CMU API. + ******************************************************************************/ +void EMU_EnterEM3(bool restore) +{ +#if defined(SLI_METRIC_EM3_HOOK) + sli_metric_em23_wake_init(SLI_INIT_EM3_WAKE); +#endif + +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + bool errataFixEmuE107En; + uint32_t nonWicIntEn[2]; +#endif + +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + bool errataFixEmuE110En; +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Save); + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Only save EMU and CMU state if restored on wake-up. */ + if (restore) { + emState(emState_Save); + } +#endif + +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + vScaleDownEM23Setup(); +#endif + +#if defined(_CMU_OSCENCMD_MASK) + uint32_t cmuLocked; + cmuLocked = CMU->LOCK & CMU_LOCK_LOCKKEY_LOCKED; + CMU_Unlock(); + + /* Disable LF oscillators. */ + CMU->OSCENCMD = CMU_OSCENCMD_LFXODIS | CMU_OSCENCMD_LFRCODIS; + + /* Restore CMU register locking. */ + if (cmuLocked != 0U) { + CMU_Lock(); + } +#endif + + /* Enter Cortex deep sleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Fix for errata EMU_E107 - store non-WIC interrupt enable flags. + Disable the enabled non-WIC interrupts. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + errataFixEmuE107En = getErrataFixEmuE107En(); + if (errataFixEmuE107En) { + nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0; + NVIC->ICER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1; + NVIC->ICER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + + EMU_EM23PresleepHook(); +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_205) \ + || defined(ERRATA_FIX_EMU_E110_ENABLE) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) + errataFixEmuE110En = getErrataFixEmuE110En(); + if (errataFixEmuE110En) { +#endif + CORE_CRITICAL_SECTION(ramWFI(); ) +#if defined(ERRATA_FIX_EMU_E110_ENABLE) +} else { + __WFI(); +} +#endif +#elif defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + // Apply errata fix if voltage scaling in EM2 is used. + if ((EMU->CTRL & EMU_CTRL_EM23VSCALEAUTOWSEN) != 0U) { + CORE_CRITICAL_SECTION(ramWFI(); ) + } else { + __WFI(); + } +#else + __WFI(); +#endif + EMU_EM23PostsleepHook(); + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(false); +#endif + + /* Fix for errata EMU_E107 - restore state of non-WIC interrupt enable flags. */ +#if defined(ERRATA_FIX_EMU_E107_ENABLE) + if (errataFixEmuE107En) { + NVIC->ISER[0] = nonWicIntEn[0]; +#if (NON_WIC_INT_MASK_1 != (~(0x0U))) + NVIC->ISER[1] = nonWicIntEn[1]; +#endif + } +#endif + +#if (_SILICON_LABS_32B_SERIES < 2) + /* Restore oscillators/clocks and voltage scaling if supported. */ + if (restore) { + emState(emState_Restore); + } +#if defined(_EMU_CTRL_EM23VSCALE_MASK) && defined(EMU_CTRL_EM23VSCALEAUTOWSEN) + else { + vScaleAfterWakeup(); + } +#if defined(ERRATA_FIX_EMU_E220_DECBOD_ENABLE) + /* Third part of EMU_E220 DECBOD Errata fix. Calibration needs to be enabled + * after voltage scaling completes. */ + EMU_PORBOD &= ~(EMU_PORBOD_GMC_CALIB_DISABLE); +#endif +#endif +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + if (restore) { + dpllState(dpllState_Restore); + } +#endif + + if (!restore) { + /* If not restoring, and the original clock was not HFRCO, the CMSIS */ + /* core clock variable must be updated since HF clock has changed */ + /* to HFRCO. */ + SystemCoreClockUpdate(); + } +} + +/***************************************************************************//** + * @brief + * Save the CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) before @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the state to be saved without + * going to sleep. The state can be restored manually by calling + * @ref EMU_Restore(). + ******************************************************************************/ +void EMU_Save(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Save); +#endif +} + +/***************************************************************************//** + * @brief + * Restore CMU HF clock select state, oscillator enable, and voltage scaling + * (if available) after @ref EMU_EnterEM2() or @ref EMU_EnterEM3() are called + * with the restore parameter set to false. Calling this function is + * equivalent to calling @ref EMU_EnterEM2() or @ref EMU_EnterEM3() with the + * restore parameter set to true, but it allows the application to evaluate the + * wakeup reason before restoring state. + ******************************************************************************/ +void EMU_Restore(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Restore); +#endif +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + dpllState(dpllState_Restore); +#endif +} + +#if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Update the EMU module with Energy Mode 4 configuration. + * + * @param[in] em4Init + * Energy Mode 4 configuration structure. + ******************************************************************************/ +void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init) +{ +#if defined(_EMU_EM4CONF_MASK) + /* Initialization for platforms with EMU->EM4CONF register. */ + uint32_t em4conf = EMU->EM4CONF; + + /* Clear fields that will be reconfigured. */ + em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK + | _EMU_EM4CONF_OSC_MASK + | _EMU_EM4CONF_BURTCWU_MASK + | _EMU_EM4CONF_VREGEN_MASK + | _EMU_EM4CONF_BUBODRSTDIS_MASK); + + /* Configure new settings. */ + em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT) + | (em4Init->osc) + | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT) + | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT) + | (em4Init->buBodRstDis << _EMU_EM4CONF_BUBODRSTDIS_SHIFT); + + /* Apply configuration. Note that lock can be set after this stage. */ + EMU->EM4CONF = em4conf; + +#elif defined(_EMU_EM4CTRL_EM4STATE_MASK) + /* Initialization for platforms with EMU->EM4CTRL register and EM4H and EM4S. */ + + uint32_t em4ctrl = EMU->EM4CTRL; + + em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK + | _EMU_EM4CTRL_RETAINLFRCO_MASK + | _EMU_EM4CTRL_RETAINULFRCO_MASK + | _EMU_EM4CTRL_EM4STATE_MASK + | _EMU_EM4CTRL_EM4IORETMODE_MASK); + + em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0U) + | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0U) + | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0U) + | (em4Init->em4State == emuEM4Hibernate + ? EMU_EM4CTRL_EM4STATE_EM4H : 0U) + | ((uint32_t)em4Init->pinRetentionMode); + + EMU->EM4CTRL = em4ctrl; +#elif defined(_EMU_EM4CTRL_MASK) + EMU->EM4CTRL = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4IORETMODE_MASK) + | (uint32_t)em4Init->pinRetentionMode; +#endif + +#if defined(_EMU_CTRL_EM4HVSCALE_MASK) + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM4HVSCALE_MASK) + | ((uint32_t)em4Init->vScaleEM4HVoltage << _EMU_CTRL_EM4HVSCALE_SHIFT); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Energy mode 4 pre-sleep hook function. + * + * @details + * This function is called by @ref EMU_EnterEM4() just prior to the sequence + * of writes to put the device in EM4. The function implementation does not + * perform anything, but it is SL_WEAK so that it can be re-implemented in + * application code if actions are needed. + ******************************************************************************/ +SL_WEAK void EMU_EM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * EFP's Energy mode 4 pre-sleep hook function. + * + * @details + * This function is similar to @ref EMU_EM4PresleepHook() but is reserved for + * EFP usage. + * + * @note + * The function is primarily meant to be used in systems with EFP circuitry. + * (EFP = Energy Friendly Pmic (PMIC = Power Management IC)). + * In such systems there is a need to drive certain signals to EFP pins to + * notify about energy mode transitions. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM4PresleepHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + ******************************************************************************/ +void EMU_EnterEM4(void) +{ +#if defined(SL_CATALOG_METRIC_EM4_WAKE_PRESENT) + sli_metric_em4_wake_init(); +#endif + int i; + +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + uint32_t em4seq2 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (2U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); + uint32_t em4seq3 = (EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK) + | (3U << _EMU_EM4CTRL_EM4ENTRY_SHIFT); +#else + uint32_t em4seq2 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (2U << _EMU_CTRL_EM4CTRL_SHIFT); + uint32_t em4seq3 = (EMU->CTRL & ~_EMU_CTRL_EM4CTRL_MASK) + | (3U << _EMU_CTRL_EM4CTRL_SHIFT); +#endif + + /* Make sure that the register write lock is disabled. */ + EMU_Unlock(); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + /* The DCDC is not supported in EM4S. EFM32xG1 and EFR32xG1 devices should + * switch to bypass mode before entering EM4S. Other devices handle this + * automatically at the hardware level. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + uint32_t dcdcMode = EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK; + if (dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWNOISE + || dcdcMode == EMU_DCDCCTRL_DCDCMODE_LOWPOWER) { + EMU_DCDCModeSet(emuDcdcMode_Bypass); + } + } +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + /* Make sure DCDC Mode is not modified, from this point forward, + * by another code section. */ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + + /* Workaround for bug that may cause a Hard Fault on EM4 entry */ + CMU_CLOCK_SELECT_SET(SYSCLK, FSRCO); + /* The buck DC-DC is available in all energy modes except for EM4. + * The DC-DC converter must first be turned off and switched over to bypass mode. */ +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \ + || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)) + EMU_DCDCModeSet(emuDcdcMode_Bypass); +#endif +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_ENABLE) + if (EMU->EM4CTRL & EMU_EM4CTRL_EM4STATE_EM4H) { + /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. + * Full description of errata fix can be found in the errata document. */ + __disable_irq(); + *(volatile uint32_t *)(EMU_BASE + 0x190UL) = 0x0000ADE8UL; + *(volatile uint32_t *)(EMU_BASE + 0x198UL) |= (0x1UL << 7); + *(volatile uint32_t *)(EMU_BASE + 0x88UL) |= (0x1UL << 8); + } +#endif + +#if defined(ERRATA_FIX_EMU_E108_ENABLE) + /* Fix for errata EMU_E108 - High Current Consumption on EM4 Entry. */ + __disable_irq(); + *(volatile uint32_t *)0x400C80E4 = 0; +#endif + +#if defined(ERRATA_FIX_DCDC_FETCNT_SET_ENABLE) + dcdcFetCntSet(true); +#endif +#if defined(ERRATA_FIX_DCDC_LNHS_BLOCK_ENABLE) + dcdcHsFixLnBlock(); +#endif + +#if defined(ERRATA_FIX_EM4S_DELAY_ENTRY) + /* Fix for errata where firmware must clear ANASW and delay EM4S entry by 30 us. */ + if ((EMU->EM4CTRL & _EMU_EM4CTRL_EM4STATE_MASK) == EMU_EM4CTRL_EM4STATE_EM4S) { + if ((EMU->PWRCTRL & _EMU_PWRCTRL_ANASW_MASK) == EMU_PWRCTRL_ANASW_DVDD) { + BUS_RegMaskedClear(&EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_MASK); + /* Switch to 1 MHz HFRCO. This delays enough to meet the 30 us requirement + * before entering EM4. */ + uint32_t freqCal = (DEVINFO->HFRCOCAL0 & ~_CMU_HFRCOCTRL_CLKDIV_MASK) + | CMU_HFRCOCTRL_CLKDIV_DIV4; + while ((CMU->SYNCBUSY & CMU_SYNCBUSY_HFRCOBSY) != 0UL) { + } + CMU->HFRCOCTRL = freqCal; + CMU->OSCENCMD = CMU_OSCENCMD_HFRCOEN; + while ((CMU->STATUS & CMU_STATUS_HFRCORDY) == 0U) { + } + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFRCO; + __NOP(); + } + } +#endif + + EMU_EM4PresleepHook(); + EMU_EFPEM4PresleepHook(); + + for (i = 0; i < 4; i++) { +#if defined(_EMU_EM4CTRL_EM4ENTRY_SHIFT) + EMU->EM4CTRL = em4seq2; + EMU->EM4CTRL = em4seq3; + } + EMU->EM4CTRL = em4seq2; +#else + EMU->CTRL = em4seq2; + EMU->CTRL = em4seq3; + } + EMU->CTRL = em4seq2; +#endif + +#if defined(_DCDC_IF_EM4ERR_MASK) + EFM_ASSERT((DCDC->IF & _DCDC_IF_EM4ERR_MASK) == 0); + CORE_EXIT_CRITICAL(); +#endif +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 (EM4). + * + * @details + * This function waits after the EM4 entry request to make sure the CPU + * is properly shutdown or the EM4 entry failed. + * + * @note + * Only a power on reset or external reset pin can wake the device from EM4. + ******************************************************************************/ +void EMU_EnterEM4Wait(void) +{ + EMU_EnterEM4(); + + // The EM4 entry waiting loop should take 4 cycles by loop minimally (Compiler dependent). + // We would then wait for (EMU_EM4_ENTRY_WAIT_LOOPS * 4) clock cycles. + for (uint16_t i = 0; i < EMU_EM4_ENTRY_WAIT_LOOPS; i++) { + __NOP(); + } +} + +#if defined(_EMU_EM4CTRL_MASK) +/***************************************************************************//** + * @brief + * Enter energy mode 4 hibernate (EM4H). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4H(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 1); +#endif + EMU_EnterEM4(); +} + +/***************************************************************************//** + * @brief + * Enter energy mode 4 shutoff (EM4S). + * + * @note + * Retention of clocks and GPIO in EM4 can be configured using + * @ref EMU_EM4Init before calling this function. + ******************************************************************************/ +void EMU_EnterEM4S(void) +{ +#if defined(_EMU_EM4CTRL_EM4STATE_MASK) + BUS_RegBitWrite(&EMU->EM4CTRL, _EMU_EM4CTRL_EM4STATE_SHIFT, 0); +#endif + EMU_EnterEM4(); +} +#endif + +/***************************************************************************//** + * @brief + * Power down memory block. + * + * @param[in] blocks + * Specifies a logical OR of bits indicating memory blocks to power down. + * Bit 0 selects block 1, bit 1 selects block 2, and so on. Memory block 0 cannot + * be disabled. See the reference manual for available + * memory blocks for a device. + * + * @note + * Only a POR reset can power up the specified memory block(s) after power down. + * + * @deprecated + * This function is deprecated, use @ref EMU_RamPowerDown() instead which + * maps a user provided memory range into RAM blocks to power down. + ******************************************************************************/ +void EMU_MemPwrDown(uint32_t blocks) +{ +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = blocks & _EMU_MEMCTRL_MASK; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = blocks & _EMU_RAM0CTRL_MASK; +#else + (void)blocks; +#endif +} + +/***************************************************************************//** + * @brief + * Power down RAM memory blocks. + * + * @details + * This function will power down all the RAM blocks that are within a given + * range. The RAM block layout is different between device families, so this + * function can be used in a generic way to power down a RAM memory region + * which is known to be unused. + * + * This function will only power down blocks which are completely enclosed + * by the memory range given by [start, end). + * + * This is an example to power down all RAM blocks except the first + * one. The first RAM block is special in that it cannot be powered down + * by the hardware. The size of the first RAM block is device-specific. + * See the reference manual to find the RAM block sizes. + * + * @code + * EMU_RamPowerDown(SRAM_BASE, SRAM_BASE + SRAM_SIZE); + * @endcode + * + * @note + * Only a reset can power up the specified memory block(s) after power down + * on a series 0 device. The specified memory block(s) will stay off + * until a call to EMU_RamPowerUp() is done on series 1/2. + * + * @param[in] start + * The start address of the RAM region to power down. This address is + * inclusive. + * + * @param[in] end + * The end address of the RAM region to power down. This address is + * exclusive. If this parameter is 0, all RAM blocks contained in the + * region from start to the upper RAM address will be powered down. + ******************************************************************************/ +void EMU_RamPowerDown(uint32_t start, uint32_t end) +{ + uint32_t mask = 0; + (void) start; + + if (end == 0U) { + end = SRAM_BASE + SRAM_SIZE; + } + + // Check to see if something in RAM0 can be powered down. + if (end > RAM0_END) { +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) // EFM32xG12 and EFR32xG12 + // Block 0 is 16 kB and cannot be powered off. + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 0; // Block 1, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 1; // Block 2, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x2000C000UL) << 2; // Block 3, 16 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20010000UL) << 3; // Block 4, 64 kB +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) // EFM32xG1 and EFR32xG1 + // Block 0 is 4 kB and cannot be powered off. + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20001000UL) << 0; // Block 1, 4 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20002000UL) << 1; // Block 2, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20004000UL) << 2; // Block 3, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 3; // Block 4, 7 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // Lynx has 2 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + // Leopard has 3 blocks. We do no shut off block 0 because we dont want to disable all RAM0 + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20006000UL) << 1; // Block 1, 8 kB + mask |= ADDRESS_NOT_IN_BLOCK(start, 0x20008000UL) << 2; // Block 2, 32 kB +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) + // These platforms have equally-sized RAM blocks and block 0 can be powered down but should not. + // This condition happens when the block 0 disable bit flag is available in the retention control register. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i); + } +#elif defined(RAM0_BLOCKS) + // These platforms have equally-sized RAM blocks and block 0 cannot be powered down. + for (unsigned i = 1; i < RAM0_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM_MEM_BASE + (i * RAM0_BLOCK_SIZE)) << (i - 1U); + } +#endif + } + + // Power down the selected blocks. +#if defined(_EMU_MEMCTRL_MASK) + EMU->MEMCTRL = EMU->MEMCTRL | mask; +#elif defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = EMU->RAM0CTRL | mask; +#elif defined(_SILICON_LABS_32B_SERIES_2) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_maskDmem0RetnCtrl(mask); +#else + // These devices are unable to power down RAM blocks. + (void) mask; + (void) start; +#endif + +#if defined(RAM1_MEM_END) + mask = 0; + if (end > RAM1_MEM_END) { + for (unsigned i = 0; i < RAM1_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM1_MEM_BASE + (i * RAM1_BLOCK_SIZE)) << i; + } + } + EMU->RAM1CTRL |= mask; +#endif + +#if defined(RAM2_MEM_END) + mask = 0; + if (end > RAM2_MEM_END) { + for (unsigned i = 0; i < RAM2_BLOCKS; i++) { + mask |= ADDRESS_NOT_IN_BLOCK(start, RAM2_MEM_BASE + (i * RAM2_BLOCK_SIZE)) << i; + } + } + EMU->RAM2CTRL |= mask; +#endif +} + +/***************************************************************************//** + * @brief + * Power up all available RAM memory blocks. + * + * @details + * This function will power up all the RAM blocks on a device, this means + * that the RAM blocks are retained in EM2/EM3. Note that this functionality + * is not supported on Series 0 devices. Only a reset will power up the RAM + * blocks on a series 0 device. + ******************************************************************************/ +void EMU_RamPowerUp(void) +{ +#if defined(_EMU_RAM0CTRL_MASK) + EMU->RAM0CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM1CTRL_MASK) + EMU->RAM1CTRL = 0x0UL; +#endif +#if defined(_EMU_RAM2CTRL_MASK) + EMU->RAM2CTRL = 0x0UL; +#endif +#if defined(_SYSCFG_DMEM0RETNCTRL_MASK) +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + SYSCFG_zeroDmem0RetnCtrl(); +#endif +} + +#if defined(_EMU_EM23PERNORETAINCTRL_MASK) +/***************************************************************************//** + * @brief + * Set EM2 3 peripheral retention control. + * + * @param[in] periMask + * A peripheral select mask. Use | operator to select multiple peripherals, for example + * @ref emuPeripheralRetention_LEUART0 | @ref emuPeripheralRetention_VDAC0. + * @param[in] enable + * Peripheral retention enable (true) or disable (false). + * + * + * @note + * Only peripheral retention disable is currently supported. Peripherals are + * enabled by default and can only be disabled. + ******************************************************************************/ +void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable) +{ + EFM_ASSERT(!enable); + EMU->EM23PERNORETAINCTRL = (uint32_t)periMask + & (uint32_t)emuPeripheralRetention_ALL; +} +#endif + +/***************************************************************************//** + * @brief + * Update EMU module with CMU oscillator selection/enable status. + * + * @deprecated + * Oscillator status is saved in @ref EMU_EnterEM2() and @ref EMU_EnterEM3(). + ******************************************************************************/ +void EMU_UpdateOscConfig(void) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + emState(emState_Save); +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) && defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Energy mode 01 voltage scaling hook function. + * + * @param[in] voltage + * Voltage scaling level requested. + * + * @details + * This function is called by EMU_VScaleEM01 to let EFP know that voltage scaling + * is requested. + ******************************************************************************/ +SL_WEAK void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage) +{ + (void)voltage; +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Voltage scale in EM0 and 1 by clock frequency. + * + * @param[in] clockFrequency + * Use CMSIS HF clock if 0 or override to custom clock. Providing a + * custom clock frequency is required if using a non-standard HFXO + * frequency. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is primarily needed by the @ref cmu. + ******************************************************************************/ +void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait) +{ + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + /* VSCALE frequency is HFSRCCLK. */ + if (clockFrequency == 0U) { +#if defined(_SILICON_LABS_32B_SERIES_2) + hfSrcClockFrequency = SystemSYSCLKGet(); +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfSrcClockFrequency = SystemHFClockGet() * hfPresc; +#endif + } else { + hfSrcClockFrequency = clockFrequency; + } + + /* Apply EM0 and 1 voltage scaling command. */ + if (vScaleEM01Config.vScaleEM01LowPowerVoltageEnable + && (hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX)) { + EMU_VScaleEM01(emuVScaleEM01_LowPower, wait); + } else { + EMU_VScaleEM01(emuVScaleEM01_HighPerformance, wait); + } +} +#endif + +#if defined(EMU_VSCALE_EM01_PRESENT) +/***************************************************************************//** + * @brief + * Force voltage scaling in EM0 and 1 to a specific voltage level. + * + * @param[in] voltage + * Target VSCALE voltage level. + * @param[in] wait + * Wait for scaling to complete. + * + * @note + * This function is useful for upscaling before programming Flash from @ref msc + * and downscaling after programming is done. Flash programming is only supported + * at @ref emuVScaleEM01_HighPerformance. + * + * @note + * This function ignores vScaleEM01LowPowerVoltageEnable set from @ref + * EMU_EM01Init(). + ******************************************************************************/ +void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait) +{ + uint32_t hfFreq; + uint32_t hfSrcClockFrequency; + +#if defined(_SILICON_LABS_32B_SERIES_1) + if (EMU_LDOStatusGet() == false) { + /* Skip voltage scaling if the LDO regulator is turned off. */ + return; + } +#endif + + if (EMU_VScaleGet() == voltage) { + /* Voltage is already at the correct level. */ + return; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + (void)wait; + CORE_DECLARE_IRQ_STATE; + + hfFreq = SystemSYSCLKGet(); + hfSrcClockFrequency = hfFreq; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + CORE_ENTER_CRITICAL(); + EMU->IF_CLR = EMU_IF_VSCALEDONE; + EMU_EFPEM01VScale(voltage); + EMU->CMD = vScaleEM01Cmd(voltage); + + // Note that VSCALEDONE interrupt flag must be used instead of VSCALEBUSY + // because hardware does not set the VSCALEBUSY flag immediately. + while (((EMU->IF & EMU_IF_VSCALEDONE) == 0U) + && ((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U)) { + EFM_ASSERT((EMU->STATUS & EMU_STATUS_VSCALEFAILED) == 0U); + // Wait for VSCALE completion. + // SRAM accesses will fault the core while scaling. + } + CORE_EXIT_CRITICAL(); + +#else + uint32_t hfPresc = 1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK) + >> _CMU_HFPRESC_PRESC_SHIFT); + hfFreq = SystemHFClockGet(); + hfSrcClockFrequency = hfFreq * hfPresc; + + if (voltage == emuVScaleEM01_LowPower) { + EFM_ASSERT(hfSrcClockFrequency <= CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX); + /* Update wait states before scaling down voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_LOW_POWER); + } + + EMU->CMD = vScaleEM01Cmd(voltage); + + if (wait) { + EMU_VScaleWait(); + } +#endif + + if (voltage == emuVScaleEM01_HighPerformance) { + /* Update wait states after scaling up voltage. */ + CMU_UpdateWaitStates(hfFreq, VSCALE_EM01_HIGH_PERFORMANCE); + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] bupdInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit) +{ + uint32_t reg; + + /* Set the power connection configuration. */ + reg = EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK + | _EMU_PWRCONF_VOUTSTRONG_MASK + | _EMU_PWRCONF_VOUTMED_MASK + | _EMU_PWRCONF_VOUTWEAK_MASK); + + reg |= bupdInit->resistor + | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT) + | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT) + | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT); + + EMU->PWRCONF = reg; + + /* Set the backup domain inactive mode configuration. */ + reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK); + reg |= (bupdInit->inactivePower); + EMU->BUINACT = reg; + + /* Set the backup domain active mode configuration. */ + reg = EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK); + reg |= (bupdInit->activePower); + EMU->BUACT = reg; + + /* Set the power control configuration */ + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK + | _EMU_BUCTRL_BODCAL_MASK + | _EMU_BUCTRL_STATEN_MASK + | _EMU_BUCTRL_EN_MASK); + + /* Note the use of ->enable to enable BUPD. Use BU_VIN pin input and + release reset. */ + reg |= bupdInit->probe + | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT) + | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT) + | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT); + + /* Enable configuration. */ + EMU->BUCTRL = reg; + + /* If enable is true, enable BU_VIN input power pin. If not, disable it. */ + EMU_BUPinEnable(bupdInit->enable); + + /* If enable is true, release BU reset. If not, keep reset asserted. */ + BUS_RegBitWrite(&(RMU->CTRL), _RMU_CTRL_BURSTEN_SHIFT, !bupdInit->enable); +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold value. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 8); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXTHRES_MASK >> _EMU_BUACT_BUEXTHRES_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK) + | (value << _EMU_BUACT_BUEXTHRES_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK) + | (value << _EMU_BUINACT_BUENTHRES_SHIFT); + break; + } +} + +/***************************************************************************//** + * @brief + * Configure the Backup Power Domain BOD Threshold Range. + * @note + * These values are precalibrated. + * @param[in] mode Active or Inactive mode + * @param[in] value + ******************************************************************************/ +void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value) +{ + EFM_ASSERT(value < 4); + EFM_ASSERT(value <= (_EMU_BUACT_BUEXRANGE_MASK >> _EMU_BUACT_BUEXRANGE_SHIFT)); + + switch (mode) { + case emuBODMode_Active: + EMU->BUACT = (EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK) + | (value << _EMU_BUACT_BUEXRANGE_SHIFT); + break; + case emuBODMode_Inactive: + EMU->BUINACT = (EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK) + | (value << _EMU_BUINACT_BUENRANGE_SHIFT); + break; + } +} +#endif + +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1) +/***************************************************************************//** + * @brief + * Configure Backup Power Domain settings. + * + * @param[in] buInit + * Backup power domain initialization structure. + ******************************************************************************/ +void EMU_BUInit(const EMU_BUInit_TypeDef *buInit) +{ + uint32_t reg = 0; + + /* Set the backup power configuration. */ + reg |= (buInit->disMaxComp << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + reg |= (uint32_t)(buInit->inactivePwrCon); + reg |= (uint32_t)(buInit->activePwrCon); + reg |= (uint32_t)(buInit->pwrRes); + reg |= (uint32_t)(buInit->voutRes); + reg |= (buInit->buVinProbeEn << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + reg |= (buInit->staEn << _EMU_BUCTRL_STATEN_SHIFT); + reg |= (buInit->enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_DISMAXCOMP_MASK) +/***************************************************************************//** + * @brief + * Disable Main Backup Power Domain comparator. + * + * @param[in] disableMainBuComparator + * True to disable main BU comparator. + ******************************************************************************/ +void EMU_BUDisMaxCompSet(bool disableMainBuComparator) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_DISMAXCOMP_MASK); + reg |= (disableMainBuComparator << _EMU_BUCTRL_DISMAXCOMP_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when not in Backup mode. + * + * @param[in] inactPwrCon + * Inactive power configuration. + ******************************************************************************/ +void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUINACTPWRCON_MASK); + reg |= (uint32_t)(inactPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUACTPWRCON_MASK) +/***************************************************************************//** + * @brief + * Configure power connection configuration when in Backup mode. + * + * @param[in] actPwrCon + * Active power configuration. + ******************************************************************************/ +void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUACTPWRCON_MASK); + reg |= (uint32_t)(actPwrCon); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_PWRRES_MASK) +/***************************************************************************//** + * @brief + * Power domain resistor selection. + * + * @param[in] pwrRes + * Resistor selection. + ******************************************************************************/ +void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_PWRRES_MASK); + reg |= (uint32_t)(pwrRes); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_VOUTRES_MASK) +/***************************************************************************//** + * @brief + * B_VOUT resistor select. + * + * @param[in] resistorSel + * Resistor selection. + ******************************************************************************/ +void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_VOUTRES_MASK); + reg |= (uint32_t)(resistorSel); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK) +/***************************************************************************//** + * @brief + * Enable BU_VIN probing + * + * @param[in] enable + * True to enable BU_VIN probing. False to disable. + ******************************************************************************/ +void EMU_BUBuVinProbeEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_BUVINPROBEEN_MASK); + reg |= (enable << _EMU_BUCTRL_BUVINPROBEEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_STATEN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode status export. + * + * @param[in] enable + * True to enable status export. False to disable. + ******************************************************************************/ +void EMU_BUStatEnSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_STATEN_MASK); + reg |= (enable << _EMU_BUCTRL_STATEN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(_EMU_BUCTRL_EN_MASK) +/***************************************************************************//** + * @brief + * Enable backup mode. + * + * @param[in] enable + * True to enable backup mode. False to disable. + ******************************************************************************/ +void EMU_BUEnableSet(bool enable) +{ + uint32_t reg; + + reg = EMU->BUCTRL & ~(_EMU_BUCTRL_EN_MASK); + reg |= (enable << _EMU_BUCTRL_EN_SHIFT); + EMU->BUCTRL = reg; +} +#endif + +#if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* Internal DCDC trim modes. */ +typedef enum { + dcdcTrimMode_EM234H_LP = 0, +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + dcdcTrimMode_EM01_LP, +#endif + dcdcTrimMode_LN, +} dcdcTrimMode_TypeDef; + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Load DCDC calibration constants from the DI page. A constant means that calibration + * data that does not change depending on other configuration parameters. + * + * @return + * False if calibration registers are locked. + ******************************************************************************/ +static bool dcdcConstCalibrationLoad(void) +{ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t val; + volatile uint32_t *reg; + + /* DI calibration data in Flash. */ + volatile uint32_t* const diCal_EMU_DCDCLNFREQCTRL = (volatile uint32_t *)(0x0FE08038); + volatile uint32_t* const diCal_EMU_DCDCLNVCTRL = (volatile uint32_t *)(0x0FE08040); + volatile uint32_t* const diCal_EMU_DCDCLPCTRL = (volatile uint32_t *)(0x0FE08048); + volatile uint32_t* const diCal_EMU_DCDCLPVCTRL = (volatile uint32_t *)(0x0FE08050); + volatile uint32_t* const diCal_EMU_DCDCTRIM0 = (volatile uint32_t *)(0x0FE08058); + volatile uint32_t* const diCal_EMU_DCDCTRIM1 = (volatile uint32_t *)(0x0FE08060); + + if (DEVINFO->DCDCLPVCTRL0 != UINT_MAX) { + val = *(diCal_EMU_DCDCLNFREQCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLNVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCLPVCTRL + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM0 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM0; + *reg = val; + + val = *(diCal_EMU_DCDCTRIM1 + 1); + reg = (volatile uint32_t *)*diCal_EMU_DCDCTRIM1; + *reg = val; + + return true; + } + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + +#else + return true; +#endif +} + +/***************************************************************************//** + * @brief + * Set recommended and validated current optimization and timing settings. + * + ******************************************************************************/ +static void dcdcValidatedConfigSet(void) +{ + uint32_t lnForceCcm; + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint32_t dcdcTiming; + SYSTEM_ChipRevision_TypeDef rev; +#endif + + /* Enable duty cycling of the bias. */ + EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN; + + /* Set low-noise RCO for LNFORCECCM configuration. + * LNFORCECCM is default 1 for EFR32 + * LNFORCECCM is default 0 for EFM32 + */ + lnForceCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + if (lnForceCcm != 0U) { + /* 7 MHz is recommended for LNFORCECCM = 1. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } else { + /* 3 MHz is recommended for LNFORCECCM = 0. */ + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK; + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LPCMPHYSDIS + | EMU_DCDCMISCCTRL_LPCMPHYSHI; + + SYSTEM_ChipRevisionGet(&rev); + if ((rev.major == 1) + && (rev.minor < 3) + && (errataFixDcdcHsState == errataFixDcdcHsInit)) { + /* LPCMPWAITDIS = 1 */ + EMU_DCDCSMCTRL |= 1; + + dcdcTiming = EMU->DCDCTIMING; + dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK + | _EMU_DCDCTIMING_LNWAIT_MASK + | _EMU_DCDCTIMING_BYPWAIT_MASK); + + dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT) + | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT) + | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT)); + EMU->DCDCTIMING = dcdcTiming; + + errataFixDcdcHsState = errataFixDcdcHsTrimSet; + } +#endif +} + +/***************************************************************************//** + * @brief + * Compute current limiters: + * LNCLIMILIMSEL: LN current limiter threshold + * LPCLIMILIMSEL: LP current limiter threshold + * DCDCZDETCTRL: zero detector limiter threshold + ******************************************************************************/ +static void currentLimitersUpdate(void) +{ + uint32_t lncLimSel; + uint32_t zdetLimSel; + uint32_t pFetCnt; + uint16_t maxReverseCurrent_mA; + + /* 80 mA as recommended peak in Application Note AN0948. + The peak current is the average current plus 50% of the current ripple. + Hence, a 14 mA average current is recommended in LP mode. Since LP PFETCNT is also + a constant, lpcLimImSel = 1. The following calculation is provided + for documentation only. */ + const uint32_t lpcLim = (((14 + 40) + ((14 + 40) / 2)) + / (5 * (DCDC_LP_PFET_CNT + 1))) + - 1; + const uint32_t lpcLimSel = lpcLim << _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT; + + /* Get enabled PFETs. */ + pFetCnt = (EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK) + >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT; + + /* Compute the LN current limiter threshold from the nominal user input current and + LN PFETCNT as described in the register description for + EMU_DCDCMISCCTRL_LNCLIMILIMSEL. */ + lncLimSel = ((((uint32_t)dcdcMaxCurrent_mA + 40U) + + (((uint32_t)dcdcMaxCurrent_mA + 40U) / 2U)) + / (5U * (pFetCnt + 1U))) + - 1U; + + /* Saturate the register field value. */ + lncLimSel = SL_MIN(lncLimSel, + _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + >> _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT); + + lncLimSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((lncLimSel & ~_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK) == 0x0U); + EFM_ASSERT((lpcLimSel & ~_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK) == 0x0U); + + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK + | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK)) + | (lncLimSel | lpcLimSel); + + /* Compute the reverse current limit threshold for the zero detector from the user input + maximum reverse current and LN PFETCNT as described in the register description + for EMU_DCDCZDETCTRL_ZDETILIMSEL. */ + if (dcdcReverseCurrentControl >= 0) { + /* If dcdcReverseCurrentControl < 0, EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ + maxReverseCurrent_mA = (uint16_t)dcdcReverseCurrentControl; + + zdetLimSel = ((((uint32_t)maxReverseCurrent_mA + 40U) + + (((uint32_t)maxReverseCurrent_mA + 40U) / 2U)) + / ((2U * (pFetCnt + 1U)) + ((pFetCnt + 1U) / 2U))); + /* Saturate the register field value. */ + zdetLimSel = SL_MIN(zdetLimSel, + _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK + >> _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT); + + zdetLimSel <<= _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT; + + /* Check for overflow. */ + EFM_ASSERT((zdetLimSel & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) == 0x0U); + + EMU->DCDCZDETCTRL = (EMU->DCDCZDETCTRL & ~_EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK) + | zdetLimSel; + } +} + +/***************************************************************************//** + * @brief + * Set static variables that hold the user set maximum peak current + * and reverse current. Update limiters. + * + * @param[in] maxCurrent_mA + * Set the maximum peak current that the DCDC can draw from the power source. + * @param[in] reverseCurrentControl + * Reverse the current control as defined by + * @ref EMU_DcdcLnReverseCurrentControl_TypeDef. Positive values have unit mA. + ******************************************************************************/ +static void userCurrentLimitsSet(uint32_t maxCurrent_mA, + EMU_DcdcLnReverseCurrentControl_TypeDef reverseCurrentControl) +{ + dcdcMaxCurrent_mA = (uint16_t)maxCurrent_mA; + dcdcReverseCurrentControl = reverseCurrentControl; +} + +/***************************************************************************//** + * @brief + * Set DCDC low noise compensator control register. + * + * @param[in] comp + * Low-noise mode compensator trim setpoint. + ******************************************************************************/ +static void compCtrlSet(EMU_DcdcLnCompCtrl_TypeDef comp) +{ + switch (comp) { + case emuDcdcLnCompCtrl_1u0F: + EMU->DCDCLNCOMPCTRL = 0x57204077UL; + break; + + case emuDcdcLnCompCtrl_4u7F: + EMU->DCDCLNCOMPCTRL = 0xB7102137UL; + break; + + default: + EFM_ASSERT(false); + break; + } +} + +/***************************************************************************//** + * @brief + * Load EMU_DCDCLPCTRL_LPCMPHYSSEL depending on LP bias, LP feedback + * attenuation, and DEVINFOREV. + * + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpCmpBias + * lpCmpBias selection. + * @param[in] trimMode + * DCDC trim mode. + ******************************************************************************/ +static bool lpCmpHystCalibrationLoad(bool lpAttenuation, + uint8_t lpCmpBias, + dcdcTrimMode_TypeDef trimMode) +{ + uint32_t lpcmpHystSel; +#if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + (void)lpAttenuation; +#endif + + /* Get calibration data revision. */ +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + uint8_t devinfoRev = SYSTEM_GetDevinfoRev(); + + /* Load LPATT indexed calibration data. */ + if (devinfoRev < 4) { + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL0; + + if (lpAttenuation) { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT; + } else { + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT; + } + } else +#endif + { + /* devinfoRev >= 4: load LPCMPBIAS indexed calibration data. */ + lpcmpHystSel = DEVINFO->DCDCLPCMPHYSSEL1; + switch (lpCmpBias) { + case 0: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT; + break; + + case 1: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT; + break; + + case 2: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT; + break; + + case 3: + lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + } + + /* Set trims. */ + if (trimMode == dcdcTrimMode_EM234H_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT; + if ((lpcmpHystSel & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPCTRL = (EMU->DCDCLPCTRL & ~_GENERIC_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK) | lpcmpHystSel; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) + if (trimMode == dcdcTrimMode_EM01_LP) { + /* Make sure the sel value is within the field range. */ + lpcmpHystSel <<= _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT; + if ((lpcmpHystSel & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) != 0U) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK) | lpcmpHystSel; + } +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Load LPVREF low and high from DEVINFO. + * + * @param[out] vrefL + * LPVREF low from DEVINFO. + * @param[out] vrefH + * LPVREF high from DEVINFO. + * @param[in] lpAttenuation + * LP feedback attenuation. + * @param[in] lpcmpBias + * lpcmpBias to look up in DEVINFO. + ******************************************************************************/ +static void lpGetDevinfoVrefLowHigh(uint32_t *vrefL, + uint32_t *vrefH, + bool lpAttenuation, + uint8_t lpcmpBias) +{ + uint32_t vrefLow = 0; + uint32_t vrefHigh = 0; + + /* Find VREF high and low in DEVINFO indexed by LPCMPBIAS (lpcmpBias) + and LPATT (lpAttenuation) */ + uint32_t switchVal = ((uint32_t)lpcmpBias << 8) | (lpAttenuation ? 1U : 0U); + switch (switchVal) { + case ((0 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL2; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 1): + vrefLow = DEVINFO->DCDCLPVCTRL3; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT; + break; + + case ((0 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT; + break; + + case ((1 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL0; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK) + >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT; + break; + + case ((2 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT; + break; + + case ((3 << 8) | 0): + vrefLow = DEVINFO->DCDCLPVCTRL1; + vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT; + vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK) + >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT; + break; + + default: + EFM_ASSERT(false); + break; + } + *vrefL = vrefLow; + *vrefH = vrefHigh; +} + +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @note + * Do not call this function if the power circuit is configured for NODCDC as + * described in the Power Configurations section of the Reference Manual. + * Instead, call @ref EMU_DCDCPowerOff(). + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + uint32_t lpCmpBiasSelEM234H; + +#if defined(_EMU_PWRCFG_MASK) + /* Set the external power configuration. This enables writing to the other + DCDC registers. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; + + /* EMU->PWRCFG is write-once and POR reset only. Check that + the desired power configuration was set. */ + if ((EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != EMU_PWRCFG_PWRCFG_DCDCTODVDD) { + /* If this assert triggers unexpectedly, power cycle the + kit to reset the power configuration. */ + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } +#endif + + /* Load DCDC calibration data from the DI page. */ + (void)dcdcConstCalibrationLoad(); + + /* Check current parameters */ + EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200U); + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA); + EFM_ASSERT(dcdcInit->reverseCurrentControl <= 200); + + if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise) { + /* DCDC low-noise supports max 200 mA. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200U); + } +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + else if (dcdcInit->dcdcMode == emuDcdcMode_LowPower) { + /* Up to 10 mA is supported for EM01-LP mode. */ + EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 10U); + } +#endif + else { + /* No need to check the EM01 load limit. */ + } + + /* EM2/3/4 current above 10 mA is not supported. */ + EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 10000U); + + if (dcdcInit->em234LoadCurrent_uA < 75U) { + lpCmpBiasSelEM234H = 0; + } else if (dcdcInit->em234LoadCurrent_uA < 500U) { + lpCmpBiasSelEM234H = 1U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else if (dcdcInit->em234LoadCurrent_uA < 2500U) { + lpCmpBiasSelEM234H = 2U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } else { + lpCmpBiasSelEM234H = 3U << _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT; + } + + /* ==== THESE NEXT STEPS ARE STRONGLY ORDER DEPENDENT ==== */ + + /* Set DCDC low-power mode comparator bias selection. */ + + /* 1. Set DCDC low-power mode comparator bias selection and forced CCM. + => Updates DCDCMISCCTRL_LNFORCECCM */ + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK + | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) + | ((uint32_t)lpCmpBiasSelEM234H + | (dcdcInit->reverseCurrentControl >= 0 + ? EMU_DCDCMISCCTRL_LNFORCECCM : 0U)); +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Only 10 mA EM01-LP current is supported. */ + EMU->DCDCLPEM01CFG = (EMU->DCDCLPEM01CFG & ~_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + | EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3; +#endif + + /* 2. Set recommended and validated current optimization settings. + <= Depends on LNFORCECCM + => Updates DCDCLNFREQCTRL_RCOBAND */ + dcdcEm01LoadCurrent_mA = dcdcInit->em01LoadCurrent_mA; + dcdcValidatedConfigSet(); + + /* 3. Updated static currents and limits user data. + Limiters are updated in @ref EMU_DCDCOptimizeSlice(). */ + userCurrentLimitsSet(dcdcInit->maxCurrent_mA, + dcdcInit->reverseCurrentControl); + + /* 4. Optimize LN slice based on the given user input load current. + <= Depends on DCDCMISCCTRL_LNFORCECCM and DCDCLNFREQCTRL_RCOBAND + <= Depends on dcdcInit->maxCurrent_mA and dcdcInit->reverseCurrentControl + => Updates DCDCMISCCTRL_P/NFETCNT + => Updates DCDCMISCCTRL_LNCLIMILIMSEL and DCDCMISCCTRL_LPCLIMILIMSEL + => Updates DCDCZDETCTRL_ZDETILIMSEL */ + EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA); + + /* ======================================================= */ + + /* Set DCDC low noise mode compensator control register. */ + compCtrlSet(dcdcInit->dcdcLnCompCtrl); + + /* Set DCDC output voltage. */ + if (!EMU_DCDCOutputVoltageSet(dcdcInit->mVout, true, true)) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID == 80) + /* Select analog peripheral power supply. This must be done before + DCDC mode is set for all EFM32xG1 and EFR32xG1 devices. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower ? 1 : 0); +#endif + +#if defined(_EMU_PWRCTRL_REGPWRSEL_MASK) + /* Select DVDD as input to the digital regulator. The switch to DVDD will take + effect once the DCDC output is stable. */ + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set EM0 DCDC operating mode. Output voltage set in + @ref EMU_DCDCOutputVoltageSet() above takes effect if mode + is changed from bypass/off mode. */ + EMU_DCDCModeSet(dcdcInit->dcdcMode); + +#if (_SILICON_LABS_GECKO_INTERNAL_SDID != 80) + /* Select the analog peripheral power supply. This must be done after + DCDC mode is set for all devices other than EFM32xG1 and EFR32xG1. */ + BUS_RegBitWrite(&EMU->PWRCTRL, + _EMU_PWRCTRL_ANASW_SHIFT, + dcdcInit->anaPeripheralPower + == emuDcdcAnaPeripheralPower_DCDC ? 1U : 0U); +#endif + + return true; +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + ******************************************************************************/ +void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Wait for any previous write sync to complete and read DCDC mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + currentDcdcMode = (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK); + + /* Enable bypass current limiter when not in bypass mode to prevent + excessive current between VREGVDD and DVDD supplies when reentering bypass mode. */ + if (currentDcdcMode != EMU_DCDCCTRL_DCDCMODE_BYPASS) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 1); + } + + if ((EMU_DcdcMode_TypeDef)currentDcdcMode == dcdcMode) { + /* Mode already set. If already in bypass, make sure the bypass current limiter + is disabled. */ + if (dcdcMode == emuDcdcMode_Bypass) { + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, 0); + } + return; + } + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) + + /* Fix for errata DCDC_E203. */ + if ((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS) + && (dcdcMode == emuDcdcMode_LowNoise)) { + errataFixDcdcHsState = errataFixDcdcHsBypassLn; + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_80) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Fix for errata DCDC_E204. */ + if (((currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_OFF) || (currentDcdcMode == EMU_DCDCCTRL_DCDCMODE_BYPASS)) + && ((dcdcMode == emuDcdcMode_LowPower) || (dcdcMode == emuDcdcMode_LowNoise))) { + /* Always start in LOWNOISE. Switch to LOWPOWER mode once LOWNOISE startup is complete. */ + EMU_IntClear(EMU_IFC_DCDCLNRUNNING); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | EMU_DCDCCTRL_DCDCMODE_LOWNOISE; + while ((EMU_IntGet() & EMU_IF_DCDCLNRUNNING) == 0U) { + } + } +#endif // (_SILICON_LABS_GECKO_INTERNAL_SDID_84) + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) + | (uint32_t)dcdcMode; + + /* Disable bypass current limiter after bypass mode is entered. + Enable the limiter if any other mode is entered. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + BUS_RegBitWrite(&EMU->DCDCCLIMCTRL, + _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, + dcdcMode == emuDcdcMode_Bypass ? 0U : 1U); + + if (dcdcLocked) { + EMU_PowerLock(); + } +} + +#if defined(EMU_DCDCCTRL_DCDCMODEEM23) +/***************************************************************************//** + * @brief + * Set DCDC Mode EM23 operating mode. + * + * @param[in] dcdcModeEM23 + * DCDC mode EM23. + ******************************************************************************/ +void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23) +{ + bool dcdcLocked; + + dcdcLocked = (EMU->PWRLOCK == EMU_PWRLOCK_LOCKKEY_LOCKED); + EMU_PowerUnlock(); + + /* Set user-requested mode. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0UL) { + } + EMU->DCDCCTRL = (EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODEEM23_MASK) + | (uint32_t)dcdcModeEM23; + + if (dcdcLocked) { + EMU_PowerLock(); + } +} +#endif + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @details + * This function powers off the DCDC controller. This function should only be + * used if the external power circuit is wired for no DCDC. If the external power + * circuit is wired for DCDC usage, use @ref EMU_DCDCInit() and set the + * DCDC in bypass mode to disable DCDC. + * + * @return + * Return false if the DCDC could not be disabled. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + bool dcdcModeSet; + +#if defined(_EMU_PWRCFG_MASK) + /* Set DCDCTODVDD only to enable write access to EMU->DCDCCTRL. */ + EMU->PWRCFG = EMU_PWRCFG_PWRCFG_DCDCTODVDD; +#endif + + /* Select DVDD as input to the digital regulator. */ +#if defined(EMU_PWRCTRL_IMMEDIATEPWRSWITCH) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD | EMU_PWRCTRL_IMMEDIATEPWRSWITCH; +#elif defined(EMU_PWRCTRL_REGPWRSEL_DVDD) + EMU->PWRCTRL |= EMU_PWRCTRL_REGPWRSEL_DVDD; +#endif + + /* Set DCDC to OFF and disable LP in EM2/3/4. Verify that the required + mode could be set. */ + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF; + + dcdcModeSet = (EMU->DCDCCTRL == EMU_DCDCCTRL_DCDCMODE_OFF); + EFM_ASSERT(dcdcModeSet); + + return dcdcModeSet; +} + +/***************************************************************************//** + * @brief + * Set DCDC LN regulator conduction mode. + * + * @param[in] conductionMode + * DCDC LN conduction mode. + * @param[in] rcoDefaultSet + * The default DCDC RCO band for the conductionMode will be used if true. + * Otherwise, the current RCO configuration is used. + ******************************************************************************/ +void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, + bool rcoDefaultSet) +{ + EMU_DcdcMode_TypeDef currentDcdcMode + = (EMU_DcdcMode_TypeDef)((uint32_t) + (EMU->DCDCCTRL & _EMU_DCDCCTRL_DCDCMODE_MASK)); + EMU_DcdcLnRcoBand_TypeDef rcoBand + = (EMU_DcdcLnRcoBand_TypeDef)((uint32_t) + ((EMU->DCDCLNFREQCTRL + & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT)); + + /* Set bypass mode and wait for bypass mode to settle before + EMU_DCDCMISCCTRL_LNFORCECCM is set. Restore current DCDC mode. */ + EMU_IntClear(EMU_IFC_DCDCINBYPASS); + EMU_DCDCModeSet(emuDcdcMode_Bypass); + while ((EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY) != 0U) { + } + while ((EMU_IntGet() & EMU_IF_DCDCINBYPASS) == 0U) { + } + if (conductionMode == emuDcdcConductionMode_DiscontinuousLN) { + EMU->DCDCMISCCTRL &= ~EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_3MHz); + } else { + /* emuDcdcConductionMode_DiscontinuousLN supports up to 4MHz LN RCO. */ + EFM_ASSERT(rcoBand <= emuDcdcLnRcoBand_4MHz); + } + } else { + EMU->DCDCMISCCTRL |= EMU_DCDCMISCCTRL_LNFORCECCM; + if (rcoDefaultSet) { + EMU_DCDCLnRcoBandSet(emuDcdcLnRcoBand_7MHz); + } + } + EMU_DCDCModeSet(currentDcdcMode); + /* Update slice configuration as it depends on conduction mode and RCO band.*/ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} + +/***************************************************************************//** + * @brief + * Set the DCDC output voltage. + * + * @note + * The DCDC is not characterized for the entire valid output voltage range. + * For that reason an upper limit of 3.0V output voltage is enforced. + * + * @param[in] mV + * Target DCDC output voltage in mV. + * + * @param[in] setLpVoltage + * Update LP voltage + * + * @param[in] setLnVoltage + * Update LN voltage + * + * @return + * True if the mV parameter is valid. + ******************************************************************************/ +bool EMU_DCDCOutputVoltageSet(uint32_t mV, + bool setLpVoltage, + bool setLnVoltage) +{ +#if defined(_DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + + bool validOutVoltage; + bool attenuationSet; + uint32_t mVlow = 0; + uint32_t mVhigh = 0; + uint32_t mVdiff; + uint32_t vrefVal[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefLow[DCDC_TRIM_MODES] = { 0 }; + uint32_t vrefHigh[DCDC_TRIM_MODES] = { 0 }; + uint8_t lpcmpBias[DCDC_TRIM_MODES] = { 0 }; + + /* Check that the set voltage is within valid range. + Voltages are obtained from the data sheet. */ + validOutVoltage = (mV >= PWRCFG_DCDCTODVDD_VMIN) + && (mV <= PWRCFG_DCDCTODVDD_VMAX); + + if (!validOutVoltage) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Set attenuation to use and low/high range. */ + attenuationSet = mV > 1800U; + if (attenuationSet) { + mVlow = 1800; + mVhigh = 3000; + mVdiff = mVhigh - mVlow; + } else { + mVlow = 1200; + mVhigh = 1800; + mVdiff = mVhigh - mVlow; + } + + /* Get 2-point calibration data from DEVINFO. */ + + /* LN mode */ + if (attenuationSet) { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT; + } else { + vrefLow[dcdcTrimMode_LN] = DEVINFO->DCDCLNVCTRL0; + vrefHigh[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT; + vrefLow[dcdcTrimMode_LN] = (vrefLow[dcdcTrimMode_LN] & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK) + >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT; + } + + /* LP EM234H mode */ + lpcmpBias[dcdcTrimMode_EM234H_LP] = (uint8_t) + ((EMU->DCDCMISCCTRL & _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_MASK) + >> _GENERIC_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM234H_LP], + &vrefHigh[dcdcTrimMode_EM234H_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM234H_LP]); + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* LP EM01 mode */ + lpcmpBias[dcdcTrimMode_EM01_LP] = (uint8_t) + ((EMU->DCDCLPEM01CFG & _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + >> _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT); + lpGetDevinfoVrefLowHigh(&vrefLow[dcdcTrimMode_EM01_LP], + &vrefHigh[dcdcTrimMode_EM01_LP], + attenuationSet, + lpcmpBias[dcdcTrimMode_EM01_LP]); +#endif + + /* Calculate output voltage trims. */ + vrefVal[dcdcTrimMode_LN] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_LN] - vrefLow[dcdcTrimMode_LN])) + / mVdiff; + vrefVal[dcdcTrimMode_LN] += vrefLow[dcdcTrimMode_LN]; + + vrefVal[dcdcTrimMode_EM234H_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM234H_LP] - vrefLow[dcdcTrimMode_EM234H_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM234H_LP] += vrefLow[dcdcTrimMode_EM234H_LP]; + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + vrefVal[dcdcTrimMode_EM01_LP] = ((mV - mVlow) * (vrefHigh[dcdcTrimMode_EM01_LP] - vrefLow[dcdcTrimMode_EM01_LP])) + / mVdiff; + vrefVal[dcdcTrimMode_EM01_LP] += vrefLow[dcdcTrimMode_EM01_LP]; +#endif + + /* Range checks */ + if ((vrefVal[dcdcTrimMode_LN] > vrefHigh[dcdcTrimMode_LN]) + || (vrefVal[dcdcTrimMode_LN] < vrefLow[dcdcTrimMode_LN]) +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + || (vrefVal[dcdcTrimMode_EM01_LP] > vrefHigh[dcdcTrimMode_EM01_LP]) + || (vrefVal[dcdcTrimMode_EM01_LP] < vrefLow[dcdcTrimMode_EM01_LP]) +#endif + || (vrefVal[dcdcTrimMode_EM234H_LP] > vrefHigh[dcdcTrimMode_EM234H_LP]) + || (vrefVal[dcdcTrimMode_EM234H_LP] < vrefLow[dcdcTrimMode_EM234H_LP])) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* Update output voltage tuning for LN and LP modes. */ + if (setLnVoltage) { + EMU->DCDCLNVCTRL = (EMU->DCDCLNVCTRL & ~(_EMU_DCDCLNVCTRL_LNVREF_MASK | _EMU_DCDCLNVCTRL_LNATT_MASK)) + | (vrefVal[dcdcTrimMode_LN] << _EMU_DCDCLNVCTRL_LNVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLNVCTRL_LNATT : 0U); + } + + if (setLpVoltage) { + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM234H_LP], dcdcTrimMode_EM234H_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + +#if defined(_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK) + /* Load LP EM234H comparator hysteresis calibration. */ + if (!(lpCmpHystCalibrationLoad(attenuationSet, lpcmpBias[dcdcTrimMode_EM01_LP], dcdcTrimMode_EM01_LP))) { + EFM_ASSERT(false); + /* Return when assertions are disabled. */ + return false; + } + + /* LP VREF is that maximum of trims for EM01 and EM234H. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MAX(vrefVal[dcdcTrimMode_EM234H_LP], vrefVal[dcdcTrimMode_EM01_LP]); +#endif + + /* Don't exceed the maximum available code as specified in the reference manual for EMU_DCDCLPVCTRL. */ + vrefVal[dcdcTrimMode_EM234H_LP] = SL_MIN(vrefVal[dcdcTrimMode_EM234H_LP], 0xE7U); + EMU->DCDCLPVCTRL = (EMU->DCDCLPVCTRL & ~(_EMU_DCDCLPVCTRL_LPVREF_MASK | _EMU_DCDCLPVCTRL_LPATT_MASK)) + | (vrefVal[dcdcTrimMode_EM234H_LP] << _EMU_DCDCLPVCTRL_LPVREF_SHIFT) + | (attenuationSet ? EMU_DCDCLPVCTRL_LPATT : 0U); + } +#endif + return true; +} + +/***************************************************************************//** + * @brief + * Optimize the DCDC slice count based on the estimated average load current + * in EM0. + * + * @param[in] em0LoadCurrentmA + * Estimated average EM0 load current in mA. + ******************************************************************************/ +void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA) +{ + uint32_t sliceCount = 0; + uint32_t rcoBand = (EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT; + + /* Set the recommended slice count. */ + if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand >= (uint32_t)emuDcdcLnRcoBand_5MHz)) { + if (em0LoadCurrentmA < 20U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 20U) && (em0LoadCurrentmA < 40U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) == 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 10U) { + sliceCount = 4; + } else if ((em0LoadCurrentmA >= 10U) && (em0LoadCurrentmA < 20U)) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else if (((EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) != 0U) + && (rcoBand <= (uint32_t)emuDcdcLnRcoBand_4MHz)) { + if (em0LoadCurrentmA < 40U) { + sliceCount = 8; + } else { + sliceCount = 16; + } + } else { + /* This configuration is not recommended. @ref EMU_DCDCInit() applies a recommended + configuration. */ + EFM_ASSERT(false); + } + + /* The selected slices are PSLICESEL + 1. */ + sliceCount--; + + /* Apply slice count to both N and P slice. */ + sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT + | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT); + EMU->DCDCMISCCTRL = (EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK + | _EMU_DCDCMISCCTRL_NFETCNT_MASK)) + | sliceCount; + + /* Update the current limiters. */ + currentLimitersUpdate(); +} + +/***************************************************************************//** + * @brief + * Set DCDC Low-noise RCO band. + * + * @param[in] band + * RCO band to set. + ******************************************************************************/ +void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band) +{ + uint32_t forcedCcm; + forcedCcm = BUS_RegBitRead(&EMU->DCDCMISCCTRL, _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT); + + /* DCM mode supports up to 4 MHz LN RCO. */ + EFM_ASSERT(((forcedCcm == 0U) && band <= emuDcdcLnRcoBand_4MHz) + || (forcedCcm != 0U)); + + EMU->DCDCLNFREQCTRL = (EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK) + | ((uint32_t)band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT); + + /* Update slice configuration as this depends on the RCO band. */ + EMU_DCDCOptimizeSlice(dcdcEm01LoadCurrent_mA); +} +#endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC Boost regulator. + * + * @param[in] dcdcBoostInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + DCDC->BSTCTRL = (DCDC->BSTCTRL & ~(_DCDC_BSTCTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcBoostInit->tonMax << _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT); + DCDC->BSTEM01CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM01 << _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT); + DCDC->BSTEM23CTRL = ((uint32_t)dcdcBoostInit->driveSpeedEM23 << _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT) + | ((uint32_t)dcdcBoostInit->peakCurrentEM23 << _DCDC_BSTEM23CTRL_IPKVAL_SHIFT); + + EMU_BoostExternalShutdownEnable(dcdcBoostInit->externalShutdownEn); + + EMU_DCDCModeSet(emuDcdcMode_Regulation); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Set EM01 mode Boost Peak Current setting. + * + * @param[in] boostPeakCurrentEM01 + * Boost Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif + + BUS_RegMaskedWrite(&DCDC->BSTEM01CTRL, + _DCDC_BSTEM01CTRL_IPKVAL_MASK, + ((uint32_t)boostPeakCurrentEM01 << _DCDC_BSTEM01CTRL_IPKVAL_SHIFT)); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +/***************************************************************************//** + * @brief + * Enable/disable Boost External Shutdown Mode. + * + * @param[in] enable + * The boost DC-DC converter can be activated or deactivated + * from a dedicated BOOST_EN pin on the device if enable is true. + ******************************************************************************/ +void EMU_BoostExternalShutdownEnable(bool enable) +{ + if (enable) { + EMU->BOOSTCTRL_CLR = EMU_BOOSTCTRL_BOOSTENCTRL; + } else { + EMU->BOOSTCTRL_SET = EMU_BOOSTCTRL_BOOSTENCTRL; + } +} +#endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \ + || defined(EMU_SERIES2_DCDC_BOOST_PRESENT) +/***************************************************************************//** + * @brief + * Indicate that the DCDC peripheral bus clock enable has changed allowing + * RAIL to react accordingly. + * + * @details + * This function is called after DCDC has been enabled or disabled. + * The function implementation does not perform anything, but it is SL_WEAK + * so that it can use the RAIL version if needed. + ******************************************************************************/ +SL_WEAK void EMU_DCDCUpdatedHook(void) +{ +} + +/***************************************************************************//** + * @brief + * Set DCDC regulator operating mode. + * + * @param[in] dcdcMode + * DCDC mode. + * @return + * Returns the status of the DCDC mode set operation. + * @verbatim + * SL_STATUS_OK - Operation completed successfully. + * SL_STATUS_TIMEOUT - Operation EMU DCDC set mode timeout. + * @endverbatim + ******************************************************************************/ +sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode) +{ + bool dcdcLocked; + uint32_t currentDcdcMode; + sl_status_t error = SL_STATUS_OK; + uint32_t timeout = 0; + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + if (dcdcMode == emuDcdcMode_Bypass) { +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + currentDcdcMode = (DCDC->CTRL & _DCDC_CTRL_MODE_MASK) >> _DCDC_CTRL_MODE_SHIFT; + + if (currentDcdcMode != emuDcdcMode_Bypass) { + /* Switch to BYPASS mode if it is not the current mode */ + DCDC->CTRL_CLR = DCDC_CTRL_MODE; + while (((DCDC->STATUS & DCDC_STATUS_BYPSW) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for BYPASS switch enable. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_CLR = DCDC_EN_EN; +#endif + } else { + while (((DCDC->STATUS & DCDC_STATUS_VREGIN) != 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for VREGIN voltage to rise above threshold. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } else { + DCDC->IF_CLR = DCDC_IF_REGULATION; + DCDC->CTRL_SET = DCDC_CTRL_MODE; + timeout = 0; + while (((DCDC->IF & DCDC_IF_REGULATION) == 0U) && (timeout < EMU_DCDC_MODE_SET_TIMEOUT)) { + /* Wait for DCDC to complete it's startup. */ + timeout++; + } + if (timeout >= EMU_DCDC_MODE_SET_TIMEOUT) { + error = SL_STATUS_TIMEOUT; + } + } + } + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + return error; +} +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT || EMU_SERIES2_DCDC_BOOST_PRESENT */ + +#if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) +/***************************************************************************//** + * @brief + * Configure the DCDC regulator. + * + * @param[in] dcdcInit + * The DCDC initialization structure. + * + * @return + * True if initialization parameters are valid. + ******************************************************************************/ +bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit) +{ + bool dcdcLocked; + + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; +#if defined(_DCDC_EN_EN_MASK) + DCDC->EN_SET = DCDC_EN_EN; +#endif + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + EMU->VREGVDDCMPCTRL = ((uint32_t)dcdcInit->cmpThreshold + << _EMU_VREGVDDCMPCTRL_THRESSEL_SHIFT) + | EMU_VREGVDDCMPCTRL_VREGINCMPEN; + +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_CTRL_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_CTRL | DCDC_SYNCBUSY_EM01CTRL0 | DCDC_SYNCBUSY_EM23CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif +#if defined(_DCDC_CTRL_DCMONLYEN_MASK) + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK + | _DCDC_CTRL_DCMONLYEN_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT) + | ((uint32_t)(dcdcInit->dcmOnlyEn ? 1U : 0U) << _DCDC_CTRL_DCMONLYEN_SHIFT); +#else + DCDC->CTRL = (DCDC->CTRL & ~(_DCDC_CTRL_IPKTMAXCTRL_MASK)) + | ((uint32_t)dcdcInit->tonMax << _DCDC_CTRL_IPKTMAXCTRL_SHIFT); +#endif + DCDC->EM01CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM01 << _DCDC_EM01CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT); + DCDC->EM23CTRL0 = ((uint32_t)dcdcInit->driveSpeedEM23 << _DCDC_EM23CTRL0_DRVSPEED_SHIFT) + | ((uint32_t)dcdcInit->peakCurrentEM23 << _DCDC_EM23CTRL0_IPKVAL_SHIFT); + + EMU_DCDCModeSet(dcdcInit->mode); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + EMU_DCDCUpdatedHook(); + + return true; +} + +/***************************************************************************//** + * @brief + * Power off the DCDC regulator. + * + * @return + * Returns true. + ******************************************************************************/ +bool EMU_DCDCPowerOff(void) +{ + EMU_DCDCModeSet(emuDcdcMode_Bypass); + return true; +} + +/***************************************************************************//** + * @brief + * Set EMO1 mode Peak Current setting. + * + * @param[in] peakCurrentEM01 + * Peak load current coefficient in EM01 mode. + ******************************************************************************/ +void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + +#if defined(_DCDC_EN_EN_MASK) + bool dcdcWasEnabled = ((DCDC->EN & DCDC_EN_EN) != 0); + DCDC->EN_SET = DCDC_EN_EN; +#endif + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + + /* Wait for synchronization before writing new value */ +#if defined(_DCDC_SYNCBUSY_MASK) +#if defined(_DCDC_SYNCBUSY_EM01CTRL0_MASK) + EMU_DCDCSync(DCDC_SYNCBUSY_EM01CTRL0); +#else + EMU_DCDCSync(_DCDC_SYNCBUSY_MASK); +#endif +#endif + + BUS_RegMaskedWrite(&DCDC->EM01CTRL0, + _DCDC_EM01CTRL0_IPKVAL_MASK, + ((uint32_t)peakCurrentEM01 << _DCDC_EM01CTRL0_IPKVAL_SHIFT)); + +#if defined(_DCDC_EN_EN_MASK) + if (!dcdcWasEnabled) { + DCDC->EN_CLR = DCDC_EN_EN; + } +#endif + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} + +#if defined(_DCDC_PFMXCTRL_IPKVAL_MASK) +/***************************************************************************//** + * @brief + * Set PFMX mode Peak Current setting. + * + * @param[in] value + * Peak load current coefficient in PFMX mode. + ******************************************************************************/ +void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + /* Verification that the parameter is in range. */ + /* if not, restrict value to maximum allowed. */ + EFM_ASSERT(value <= (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)); + if (value > (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT)) { + value = (_DCDC_PFMXCTRL_IPKVAL_MASK >> _DCDC_PFMXCTRL_IPKVAL_SHIFT); + } + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKVAL_MASK) + | value << _DCDC_PFMXCTRL_IPKVAL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKVAL_MASK */ + +#if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) +/***************************************************************************//** + * @brief + * Set Ton_max timeout control. + * + * @param[in] value + * Maximum time for peak current detection. + ******************************************************************************/ +void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value) +{ + bool dcdcLocked = false; + bool dcdcClkWasEnabled = false; + + dcdcClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_DCDC) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_DCDC; + + dcdcLocked = ((DCDC->LOCKSTATUS & DCDC_LOCKSTATUS_LOCK) != 0); + EMU_DCDCUnlock(); + +#if defined(_DCDC_SYNCBUSY_MASK) + /* Wait for synchronization before writing new value */ + EMU_DCDCSync(DCDC_SYNCBUSY_PFMXCTRL); +#endif + + DCDC->PFMXCTRL = ((DCDC->PFMXCTRL & ~_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK) + | value << _DCDC_PFMXCTRL_IPKTMAXCTRL_SHIFT); + + if (dcdcLocked) { + EMU_DCDCLock(); + } + + if (!dcdcClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_DCDC; + } + + EMU_DCDCUpdatedHook(); +} +#endif /* _DCDC_PFMXCTRL_IPKTMAXCTRL_MASK */ +#endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */ + +#if defined(EMU_STATUS_VMONRDY) + +/***************************************************************************//** + * @brief + * Get the calibrated threshold value. + * + * @details + * All VMON channels have two calibration fields in the DI page that + * describes the threshold at 1.86 V and 2.98 V. This function will convert + * the uncalibrated input voltage threshold in millivolts into a calibrated + * threshold. + * + * @param[in] channel + * A VMON channel. + * + * @param[in] threshold + * A desired threshold in millivolts. + * + * @return + * A calibrated threshold value to use. The first digit of the return value is placed + * in the "fine" register fields while the next digits are placed in the + * "coarse" register fields. + ******************************************************************************/ +static uint32_t vmonCalibratedThreshold(EMU_VmonChannel_TypeDef channel, + int threshold) +{ + uint32_t tDiff = 0; + uint32_t tLow = 0; + uint32_t tHigh = 0; + uint32_t calReg; + + /* Get calibration values for 1.86 V and 2.98 V */ + switch (channel) { + case emuVmonChannel_AVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_ALTAVDD: + calReg = DEVINFO->VMONCAL0; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_DVDD: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT); + break; + case emuVmonChannel_IOVDD0: + calReg = DEVINFO->VMONCAL1; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO11V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO11V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_IO12V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_IO12V98THRESFINE_SHIFT); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + calReg = DEVINFO->VMONCAL2; + tLow = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD1V86THRESFINE_SHIFT); + tHigh = (10U * ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESCOARSE_SHIFT)) + + ((calReg & _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_MASK) + >> _DEVINFO_VMONCAL2_BUVDD2V98THRESFINE_SHIFT); + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + tDiff = tHigh - tLow; + if (tDiff > 0) { + /* Calculate threshold. + * + * Note that volt is used in the reference manual. However, the results + * should be in millivolts. The precision of Va and Vb are increased in the + * calculation instead of using floating points. + */ + uint32_t va = (1120U * 100U) / (tDiff); + uint32_t vb = (1860U * 100U) - (va * tLow); + // If (tHigh - tLow) is large, Va could be zero. Caught by CSTAT. + if (va != 0) { + /* Round the threshold to the nearest integer value. */ + return (((uint32_t)threshold * 100U) - vb + (va / 2U)) / va; + } + } + + /* Uncalibrated device guard. */ + return (uint32_t)threshold; +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel. + * + * @details + * Initialize a VMON channel without hysteresis. If the channel supports + * separate rise and fall triggers, both thresholds will be set to the same + * value. The threshold will be converted to a register field value based + * on calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON initialization structure. + ******************************************************************************/ +void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit) +{ + uint32_t thresholdCoarse, thresholdFine; + uint32_t threshold; + + EFM_ASSERT((vmonInit->threshold >= 1620) && (vmonInit->threshold <= 3400)); + + threshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->threshold); + thresholdFine = threshold % 10U; + thresholdCoarse = threshold / 10U; + + /* Saturate the threshold to maximum values. */ + if (thresholdCoarse > 0xFU) { + thresholdCoarse = 0xF; + thresholdFine = 9; + } + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_ALTAVDD: + EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0U); + break; + case emuVmonChannel_DVDD: + EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0U); + break; + case emuVmonChannel_IOVDD0: + EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0U); + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + EMU->VMONIO1CTRL = (thresholdCoarse << _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONIO1CTRL_THRESFINE_SHIFT) + | (vmonInit->retDisable ? EMU_VMONIO1CTRL_RETDIS : 0U) + | (vmonInit->riseWakeup ? EMU_VMONIO1CTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONIO1CTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONIO1CTRL_EN : 0U); + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + EMU->VMONBUVDDCTRL = (thresholdCoarse << _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT) + | (thresholdFine << _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONBUVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONBUVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONBUVDDCTRL_EN : 0U); + break; +#endif + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Initialize a VMON channel with hysteresis (separate rise and fall triggers). + * + * @details + * Initialize a VMON channel which supports hysteresis. The AVDD channel is + * the only channel to support separate rise and fall triggers. The rise and + * fall thresholds will be converted to a register field value based on the + * calibration values from the DI page. + * + * @param[in] vmonInit + * The VMON hysteresis initialization structure. + ******************************************************************************/ +void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit) +{ + uint32_t riseThreshold; + uint32_t fallThreshold; + + /* VMON supports voltages between 1620 mV and 3400 mV (inclusive). */ + EFM_ASSERT((vmonInit->riseThreshold >= 1620) && (vmonInit->riseThreshold <= 3400)); + EFM_ASSERT((vmonInit->fallThreshold >= 1620) && (vmonInit->fallThreshold <= 3400)); + /* The fall threshold has to be lower than rise threshold. */ + EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold); + + riseThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->riseThreshold); + fallThreshold = vmonCalibratedThreshold(vmonInit->channel, vmonInit->fallThreshold); + + switch (vmonInit->channel) { + case emuVmonChannel_AVDD: + EMU->VMONAVDDCTRL = ((riseThreshold / 10U) << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT) + | ((riseThreshold % 10U) << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT) + | ((fallThreshold / 10U) << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT) + | ((fallThreshold % 10U) << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT) + | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0U) + | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0U) + | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0U); + break; + default: + EFM_ASSERT(false); + return; + } +} + +/***************************************************************************//** + * @brief + * Enable or disable a VMON channel. + * + * @param[in] channel + * A VMON channel to enable/disable. + * + * @param[in] enable + * Indicates whether to enable or disable. + ******************************************************************************/ +void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable) +{ + uint32_t volatile * reg; + uint32_t bit; + + switch (channel) { + case emuVmonChannel_AVDD: + reg = &(EMU->VMONAVDDCTRL); + bit = _EMU_VMONAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + reg = &(EMU->VMONALTAVDDCTRL); + bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_DVDD: + reg = &(EMU->VMONDVDDCTRL); + bit = _EMU_VMONDVDDCTRL_EN_SHIFT; + break; + case emuVmonChannel_IOVDD0: + reg = &(EMU->VMONIO0CTRL); + bit = _EMU_VMONIO0CTRL_EN_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + reg = &(EMU->VMONIO1CTRL); + bit = _EMU_VMONIO1CTRL_EN_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + reg = &(EMU->VMONBUVDDCTRL); + bit = _EMU_VMONBUVDDCTRL_EN_SHIFT; + break; +#endif + default: + EFM_ASSERT(false); + return; + } + + BUS_RegBitWrite(reg, bit, (uint32_t)enable); +} + +/***************************************************************************//** + * @brief + * Get the status of a voltage monitor channel. + * + * @param[in] channel + * A VMON channel to get the status for. + * + * @return + * A status of the selected VMON channel. True if the channel is triggered. + ******************************************************************************/ +bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel) +{ + uint32_t bit; + switch (channel) { + case emuVmonChannel_AVDD: + bit = _EMU_STATUS_VMONAVDD_SHIFT; + break; + case emuVmonChannel_ALTAVDD: + bit = _EMU_STATUS_VMONALTAVDD_SHIFT; + break; + case emuVmonChannel_DVDD: + bit = _EMU_STATUS_VMONDVDD_SHIFT; + break; + case emuVmonChannel_IOVDD0: + bit = _EMU_STATUS_VMONIO0_SHIFT; + break; +#if defined(_EMU_VMONIO1CTRL_EN_MASK) + case emuVmonChannel_IOVDD1: + bit = _EMU_STATUS_VMONIO1_SHIFT; + break; +#endif +#if defined(_EMU_VMONBUVDDCTRL_EN_MASK) + case emuVmonChannel_BUVDD: + bit = _EMU_STATUS_VMONBUVDD_SHIFT; + break; +#endif + default: + bit = 0; + EFM_ASSERT(false); + break; + } + + return BUS_RegBitRead(&EMU->STATUS, bit) != 0U; +} +#endif /* EMU_STATUS_VMONRDY */ + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/***************************************************************************//** + * @brief + * Adjust the bias refresh rate. + * + * @details + * This function is only meant to be used under high-temperature operation on + * EFR32xG1 and EFM32xG1 devices. Adjusting the bias mode will + * increase the typical current consumption. See application note 1027 + * and errata documents for more details. + * + * @param [in] mode + * The new bias refresh rate. + ******************************************************************************/ +void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode) +{ + uint32_t freq = 0x2u; + bool emuTestLocked = false; + + if (mode == emuBiasMode_1KHz) { + freq = 0x0u; + } + + if (EMU_TESTLOCK == 0x1u) { + emuTestLocked = true; + EMU_TESTLOCK = 0xADE8u; + } + + if (mode == emuBiasMode_Continuous) { + EMU_BIASCONF &= ~0x74u; + } else { + EMU_BIASCONF |= 0x74u; + } + + EMU_BIASTESTCTRL |= 0x8u; + CMU_ULFRCOCTRL = (CMU_ULFRCOCTRL & ~0xC00u) + | ((freq & 0x3u) << 10u); + EMU_BIASTESTCTRL &= ~0x8u; + + if (emuTestLocked) { + EMU_TESTLOCK = 0u; + } +} +#endif + +#if defined(_EMU_TEMP_TEMP_MASK) +/***************************************************************************//** + * @brief + * Get temperature in degrees Celsius + * + * @return + * Temperature in degrees Celsius + ******************************************************************************/ +float EMU_TemperatureGet(void) +{ +#if defined(_EMU_TEMP_TEMPLSB_MASK) + return ((float) ((EMU->TEMP & (_EMU_TEMP_TEMP_MASK | _EMU_TEMP_TEMPLSB_MASK) ) + >> _EMU_TEMP_TEMPLSB_SHIFT) + ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN; +#else + uint32_t val1; + uint32_t val2; + float tempCo; + uint32_t diTemp, diEmu; + + // Calculate calibration temp based on DI page values + diTemp = ((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) >> _DEVINFO_CAL_TEMP_SHIFT); + diEmu = ((DEVINFO->EMUTEMP & _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK) >> _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT); + tempCo = EMU_TEMPCO_CONST + (diEmu / 100.0f); + + // Read temperature twice to ensure a stable value + do { + val1 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + val2 = (EMU->TEMP & _EMU_TEMP_TEMP_MASK) + >> _EMU_TEMP_TEMP_SHIFT; + } while (val1 != val2); + + return diTemp + tempCo * ((int) diEmu - (int) val1); +#endif +} +#endif // defined(_EMU_TEMP_TEMP_MASK) + +#if defined(EMU_CTRL_EFPDIRECTMODEEN) +/***************************************************************************//** + * @brief + * Enable/disable EFP Direct Mode. + * + * @param[in] enable + * True to enable direct mode. + ******************************************************************************/ +void EMU_EFPDirectModeEnable(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDIRECTMODEEN; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDIRECTMODEEN; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDECOUPLE) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive Decouple voltage. + * + * @details + * Once set, internal LDO will be disabled, and the EMU will control EFP for + * voltage-scaling. Note that because this bit disables the internal LDO + * powering the core, it should not be set until after EFP's DECOUPLE output has + * been configured and enabled. + * + * @param[in] enable + * True to enable EFP to drive Decouple voltage. + ******************************************************************************/ +void EMU_EFPDriveDecoupleSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDECOUPLE; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDECOUPLE; + } +} +#endif + +#if defined(EMU_CTRL_EFPDRVDVDD) +/***************************************************************************//** + * @brief + * Set to enable EFP to drive DVDD voltage. + * + * @details + * Set this if EFP's DCDC output is powering DVDD supply. This mode assumes that + * internal DCDC is not being used. + * + * @param[in] enable + * True to enable EFP to drive DVDD voltage. + ******************************************************************************/ +void EMU_EFPDriveDvddSet(bool enable) +{ + if (enable) { + EMU->CTRL_SET = EMU_CTRL_EFPDRVDVDD; + } else { + EMU->CTRL_CLR = EMU_CTRL_EFPDRVDVDD; + } +} +#endif + +/** @} (end addtogroup emu) */ +#endif /* __EM_EMU_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c index bcfafa1..603ca03 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_eusart.c @@ -1,1395 +1,1395 @@ -/***************************************************************************//** - * @file - * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_eusart.h" -#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) -#include "em_cmu.h" -#include - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -#if defined(EUART_PRESENT) - #define EUSART_REF_VALID(ref) ((ref) == EUART0) - #define EUSART_EM2_CAPABLE(ref) (true) - #define EUSART_RX_FIFO_SIZE 4u -#elif defined(EUSART_PRESENT) - #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1) - #define EUSART_RX_FIFO_SIZE 16u -#endif - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ -#if defined(EUSART_DALICFG_DALIEN) -static uint8_t dali_tx_nb_packets[EUSART_COUNT]; -static uint8_t dali_rx_nb_packets[EUSART_COUNT]; -#endif /* EUSART_DALICFG_DALIEN */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart); - -static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_UartInit_TypeDef *init, - const EUSART_IrDAInit_TypeDef *irdaInit, - const EUSART_DaliInit_TypeDef *daliInit); - -#if defined(EUSART_PRESENT) -static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_SpiInit_TypeDef *init); -#endif - -/***************************************************************************//** - * Wait for ongoing sync of register(s) to the low-frequency domain to complete. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param mask A bitmask corresponding to SYNCBUSY register defined bits, - * indicating registers that must complete any ongoing - * synchronization. - ******************************************************************************/ -__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask) -{ - // Wait for any pending previous write operation to have been completed - // in the low-frequency domain. - while ((eusart->SYNCBUSY & mask) != 0U) { - } -} - -/***************************************************************************//** - * Calculate baudrate for a given reference frequency, clock division, - * and oversampling rate. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - EUSART_OVS_TypeDef ovs); - -/***************************************************************************//** - * Execute the EUSART peripheral disabling sequence. - ******************************************************************************/ -__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initializes the EUSART when used with the high frequency clock. - ******************************************************************************/ -void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(init); - - // Assert features specific to HF. - // The oversampling must not be disabled when using a high frequency clock. - EFM_ASSERT(init->oversampling != eusartOVS0); - - // Uart mode only supports up to 9 databits frame. - EFM_ASSERT(init->databits <= eusartDataBits9); - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, init, NULL, NULL); -} - -/***************************************************************************//** - * Initializes the EUSART when used with the low frequency clock. - * - * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral - * clock frequency must be at least three times higher than the - * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), - * thus 32768 / 3 ~ 9600 baudrate. - ******************************************************************************/ -void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) -{ - // Make sure the module exists and is Low frequency capable. - EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // Init structure must be provided. - EFM_ASSERT(init); - - // Assert features specific to LF. - // LFXO, LFRCO, ULFRCO can be a clock source in LF. -#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) - { - CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL; -#if defined(EUART_PRESENT) - if (eusart == EUART0) { - clock_source = CMU_ClockSelectGet(cmuClock_EUART0); - } -#endif -#if defined(EUSART_PRESENT) && defined(EUSART0) - if (eusart == EUSART0) { - clock_source = CMU_ClockSelectGet(cmuClock_EUSART0); - } -#endif - - EFM_ASSERT( - (clock_source == cmuSelect_ULFRCO) - || (clock_source == cmuSelect_LFXO) - || (clock_source == cmuSelect_LFRCO) - || (clock_source == cmuSelect_EM23GRPACLK) -#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) - || (clock_source == cmuSelect_EM01GRPCCLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK or EM01GRPCCLK */ -#endif - ); - } -#endif - // Uart mode only supports up to 9 databits frame. - EFM_ASSERT(init->databits <= eusartDataBits9); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(init->oversampling == eusartOVS0); - // The Majority Vote must be disabled when using a low frequency clock. - EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable); - // Number of stop bits can only be 1 or 2 in LF. - EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2)); - // In LF, max baudrate is 9600. See Note #1. - EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0); - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, init, NULL, NULL); -} - -/***************************************************************************//** - * Initializes the EUSART when used in IrDA mode with the high or low - * frequency clock. - ******************************************************************************/ -void EUSART_IrDAInit(EUSART_TypeDef *eusart, - const EUSART_IrDAInit_TypeDef *irdaInit) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(irdaInit); - - if (irdaInit->irDALowFrequencyEnable) { - // Validate the low frequency capability of the EUSART instance. - EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0); - // Number of stop bits can only be 1 or 2 in LF. - EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2)); - // In LF, max baudrate is 9600. See Note #1. - EFM_ASSERT(irdaInit->init.baudrate <= 9600); - EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable); - } else { - EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0); - // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. - EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000); - } - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL); -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initializes the EUSART when used in SPI mode. - ******************************************************************************/ -void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(init); - if (init->master) { - EFM_ASSERT(init->bitRate <= 20000000); - - if (init->advancedSettings) { - EFM_ASSERT(!(init->advancedSettings->prsClockEnable)); - } - } else { - EFM_ASSERT(init->bitRate <= 10000000); - if (init->advancedSettings && init->advancedSettings->forceLoad) { - // If baud-rate is more than 5MHz, a value of 4 is recommended, any values - // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz, - // value of 5 is recommended, values higher than 5 can be used but it may make the load - // error easy to occur. The recommended values for frequency bands should be sufficient - // to work all the time. - EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4) - || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5)); - } - } - - EUSART_SyncInitCommon(eusart, init); -} - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Initializes the EUSART when used in DALI mode with the high or low - * frequency clock. - * - * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral - * clock frequency must be at least three times higher than the - * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), - * thus 32768 / 3 ~ 9600 baudrate. - ******************************************************************************/ -void EUSART_DaliInit(EUSART_TypeDef *eusart, - const EUSART_DaliInit_TypeDef *daliInit) -{ - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - // Init structure must be provided. - EFM_ASSERT(daliInit); - - if (daliInit->init.loopbackEnable) { - // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, - // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should - // be set the same as DALITXDATABITS. - EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT) - == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT)); - } - - if (daliInit->daliLowFrequencyEnable) { - // Validate the low frequency capability of the EUSART instance. - EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); - // The oversampling must be disabled when using a low frequency clock. - EFM_ASSERT(daliInit->init.oversampling == eusartOVS0); - // In LF, max baudrate is 9600. See Note #1. - // but manchester is running at 2x clock 9600 => 4800 - EFM_ASSERT(daliInit->init.baudrate <= 4800); - } else { - EFM_ASSERT(daliInit->init.oversampling != eusartOVS0); - // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. - // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps - EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600); - } - - // Initialize EUSART with common features to HF and LF. - EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit); -} -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configure the EUSART to its reset state. - ******************************************************************************/ -void EUSART_Reset(EUSART_TypeDef *eusart) -{ - // 1. Properly disable the module - EUSART_Disable(eusart); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) - // Manual toggling tx_sclk_mst to synchronize handshake - // when switching from SPI master to other modes - // so module is disabling correctly. - uint32_t forcedClkCycle = 4u; - - while (forcedClkCycle--) { - eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK; - eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK; - } -#endif - // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set). - // Set all configurable register to its reset value. - // Note: Program desired settings to all registers that have names ending with CFG in the following sequence: - // a. CFG2 -#if defined(EUSART_PRESENT) - eusart->CFG2 = _EUSART_CFG2_RESETVALUE; -#endif - // b. CFG1 - eusart->CFG1 = _EUSART_CFG1_RESETVALUE; - // c. CFG0 - eusart->CFG0 = _EUSART_CFG0_RESETVALUE; - // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence) - eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE; -#if defined(EUSART_PRESENT) - eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE; -#if defined(EUSART_DALICFG_DALIEN) - eusart->DALICFG = _EUSART_DALICFG_RESETVALUE; -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE; - eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE; - eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE; - eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE; - eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE; - eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE; - eusart->IEN = _EUSART_IEN_RESETVALUE; - eusart->IF_CLR = _EUSART_IF_MASK; - - // no need to sync while EN=0, multiple writes can be queued up, - // and the last one will synchronize once EN=1 - eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE; -} - -/***************************************************************************//** - * Enables/disables the EUSART receiver and/or transmitter. - ******************************************************************************/ -void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable) -{ - uint32_t tmp = 0; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - if (enable == eusartDisable) { - EUSART_Disable(eusart); - } else { - // Enable peripheral to configure Rx and Tx. - eusart->EN_SET = EUSART_EN_EN; - - // Enable or disable Rx and/or Tx - tmp = (enable) - & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK - | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK); - - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - eusart->CMD = tmp; - eusart_sync(eusart, - EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN - | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS); - - // Wait for the status register to be updated. - tmp = 0; - if (_EUSART_CMD_RXEN_MASK & enable) { - tmp |= EUSART_STATUS_RXENS; - } - if (_EUSART_CMD_TXEN_MASK & enable) { - tmp |= EUSART_STATUS_TXENS; - } - while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { - } - } -} - -/***************************************************************************//** - * Receives one 8 bit frame, (or part of 9 bit frame). - * - * @note (1) Handles the case where the RX Fifo Watermark has been set to N frames, - * and when N is greater than one. Attempt to read a frame from the RX Fifo. - * If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU - * interrupt flag is set. If the flag is set, wait to read again until the RXFL - * status flag is set, indicating there are N frames in the RX Fifo, where N - * is equal to the RX watermark level. Once there are N frames in the Fifo, - * read and return one frame. For consecutive N-1 reads there will be data available - * in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating - * delays between reads and sending N data frames in "bursts". - ******************************************************************************/ -uint8_t EUSART_Rx(EUSART_TypeDef *eusart) -{ - // If RX watermark has not been configured. - if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) { - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - return (uint8_t)eusart->RXDATA; - } - - // See Note #1. - uint8_t rx_data = eusart->RXDATA; - // If there is underflow i.e Rx data read was unsuccessful - if (eusart->IF & EUSART_IF_RXUF) { - // Wait until data becomes available in Rx fifo - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } - // Read Rx data again once data is available in the fifo - rx_data = eusart->RXDATA; - } - - return rx_data; -} - -/***************************************************************************//** - * Receives one 8-9 bit frame with extended information. - ******************************************************************************/ -uint16_t EUSART_RxExt(EUSART_TypeDef *eusart) -{ - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - - return (uint16_t)eusart->RXDATA; -} - -/***************************************************************************//** - * Transmits one frame. - ******************************************************************************/ -void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - eusart->TXDATA = (uint32_t)data; -} - -/***************************************************************************//** - * Transmits one 8-9 bit frame with extended control. - ******************************************************************************/ -void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - eusart->TXDATA = (uint32_t)data; -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Transmits one 8-16 bit frame and return received data. - ******************************************************************************/ -uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data) -{ - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - eusart->TXDATA = (uint32_t)data; - - // Wait for Rx data to be available. - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } - return (uint16_t)eusart->RXDATA; -} - -#if defined(EUSART_DALICFG_DALIEN) -/***************************************************************************//** - * Transmits one frame. - ******************************************************************************/ -void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data) -{ - uint32_t packet; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // Check that transmit FIFO is not full. - while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { - } - - for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) { - // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data - // First write to TXDATA register should contain 16 LSBs of the TX frame. - // Transmission will not start after this first write. - // Second write to TXDATA register should contain the remaining TX frame bits. - // This second write will result in start of transmission. - packet = (data >> (index * 16)); - // To ensure compatibility with future devices, always write bits [31:16] to 0. - packet &= 0x0000FFFF; - eusart->TXDATA = packet; - } -} - -/***************************************************************************//** - * Receive one frame. - ******************************************************************************/ -uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart) -{ - uint32_t data = 0; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { - } // Wait for incoming data. - - for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) { - // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data - // When receiving a frame that has more than 16 databits, - // RXDATA register needs to be read twice: - // First read will provide 16 LSBs of the received frame. - // Second read will provide the remaining RX frame bits. - data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16)); - } - return data; -} - -#endif /* EUSART_DALICFG_DALIEN */ -#endif /* EUSART_PRESENT */ - -/***************************************************************************//** - * Configures the baudrate (or as close as possible to a specified baudrate) - * depending on the current mode of the EU(S)ART peripheral. - * - * @note (1) When the oversampling is disabled, the peripheral clock frequency - * must be at least three times higher than the chosen baud rate. - ******************************************************************************/ -void EUSART_BaudrateSet(EUSART_TypeDef *eusart, - uint32_t refFreq, - uint32_t baudrate) -{ - uint32_t clkdiv; - uint8_t oversample = 0; - - // Prevent dividing by 0. - EFM_ASSERT(baudrate); - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // Get the current frequency. - if (!refFreq) { - refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); - } - -#if defined(EUSART_PRESENT) - // In synchronous mode (ex: SPI) - if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) { - EFM_ASSERT(baudrate <= refFreq); - - EUSART_Enable_TypeDef txrxEnStatus = eusartDisable; - bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true; - clkdiv = refFreq / baudrate - 1UL; - - // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV), - // the resulting spi master bus clock will be undefined because the result will be truncated. - EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT)); - - if (wasEnabled) { - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); - - // Save the state of the reveiver and transmitter before disabling the peripheral. - if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) { - txrxEnStatus = eusartEnable; - } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) { - txrxEnStatus = eusartEnableRx; - } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) { - txrxEnStatus = eusartEnableTx; - } else { - EFM_ASSERT(false); - } - - // Disable the eusart to be able to modify the CFG2 register. - EUSART_Disable(eusart); - } - - // In Synchronous mode the clock divider that is managing the bitRate - // is located inside the sdiv bitfield of the CFG2 register instead of - // the CLKDIV register combined with the oversample setting for asynchronous mode. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK); - - if (wasEnabled) { - EUSART_Enable(eusart, txrxEnStatus); - } - } else // In asynchronous mode (ex: UART) -#endif - { - // The peripheral must be enabled to configure the baud rate. - EFM_ASSERT(eusart->EN == EUSART_EN_EN); - -#if defined(EUSART_DALICFG_DALIEN) - if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { - // adjust for manchester double-clocking scheme - baudrate *= 2; - } -#endif - - /* - * Use integer division to avoid forcing in float division - * utils, and yet keep rounding effect errors to a minimum. - * - * CLKDIV is given by: - * - * CLKDIV = 256 * (fUARTn/(oversample * br) - 1) - * or - * CLKDIV = (256 * fUARTn)/(oversample * br) - 256 - * - * Since fUARTn may be derived from HFCORECLK, consider the overflow when - * using integer arithmetic. - * - * The basic problem with integer division in the above formula is that - * the dividend (256 * fUARTn) may become higher than the maximum 32 bit - * integer. Yet, the dividend should be evaluated first before dividing - * to get as small rounding effects as possible. - * Also, harsh restrictions on the maximum fUARTn value should not be made. - * - * Since the last 3 bits of CLKDIV are don't care, base the - * integer arithmetic on the below formula: - * - * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32 - * - * and calculate 1/8 of CLKDIV first. This allows for fUARTn - * up to 128 MHz without overflowing a 32 bit value. - */ - - // Map oversampling. - switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) { - case eusartOVS16: - EFM_ASSERT(baudrate <= (refFreq / 16)); - oversample = 16; - break; - - case eusartOVS8: - EFM_ASSERT(baudrate <= (refFreq / 8)); - oversample = 8; - break; - - case eusartOVS6: - EFM_ASSERT(baudrate <= (refFreq / 6)); - oversample = 6; - break; - - case eusartOVS4: - EFM_ASSERT(baudrate <= (refFreq / 4)); - oversample = 4; - break; - - case eusartOVS0: - EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1. - oversample = 1; - break; - - default: - // Invalid input - EFM_ASSERT(0); - break; - } - - if (oversample > 0U) { - // Calculate and set the CLKDIV with fractional bits. - clkdiv = (32 * refFreq) / (baudrate * oversample); - clkdiv -= 32; - clkdiv *= 8; - - // Verify that the resulting clock divider is within limits. - EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); - - // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits. - clkdiv &= _EUSART_CLKDIV_MASK; - - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - eusart->CLKDIV = clkdiv; - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - } - } -} - -/***************************************************************************//** - * Gets the current baudrate. - ******************************************************************************/ -uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart) -{ - uint32_t freq; - uint32_t div = 1; - uint32_t br = 0; - EUSART_OVS_TypeDef ovs = eusartOVS0; - - // Make sure the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); - -#if defined(EUSART_PRESENT) - // In synchronous mode (ex: SPI) - if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) { - div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT; - br = freq / (div + 1); - } - // In asynchronous mode (ex: UART) - else -#endif - { - div = eusart->CLKDIV; - ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK); - br = EUSART_AsyncBaudrateCalc(freq, div, ovs); - -#if defined(EUSART_DALICFG_DALIEN) - if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { - // adjust for manchester double-clocking scheme - br /= 2; - } -#endif - } - - return br; -} - -/***************************************************************************//** - * Enable/Disable reception operations until the configured start frame is - * received. - ******************************************************************************/ -void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - tmp = ((uint32_t)(enable)); - tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK); - - eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); - eusart->CMD_SET = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); - - tmp = 0u; - if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) { - tmp |= EUSART_STATUS_RXBLOCK; - } - while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) { - } // Wait for the status register to be updated. -} - -/***************************************************************************//** - * Enables/Disables the tristating of the transmitter output. - ******************************************************************************/ -void EUSART_TxTristateSet(EUSART_TypeDef *eusart, - EUSART_TristateTx_TypeDef enable) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - tmp = ((uint32_t)(enable)); - tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK); - - eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); - eusart->CMD = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); - - tmp = 0u; - if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) { - tmp |= EUSART_STATUS_TXTRI; - } - while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) { - } // Wait for the status register to be updated. -} - -/***************************************************************************//** - * Initializes the automatic enabling of transmissions and/or reception using - * the PRS as a trigger. - ******************************************************************************/ -void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, - const EUSART_PrsTriggerInit_TypeDef *init) -{ - uint32_t tmp; - - // Make sure that the module exists on the selected chip. - EFM_ASSERT(EUSART_REF_VALID(eusart)); - - // The peripheral must be enabled to configure the PRS trigger. - EFM_ASSERT(eusart->EN == EUSART_EN_EN); - -#if defined(EUART_PRESENT) - PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK); -#else - -#if defined(EUSART0) - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK); - } -#endif -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK); - } -#endif -#endif - - tmp = ((uint32_t)(init->prs_trigger_enable)); - tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); - - eusart->TRIGCTRL_SET = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); - - tmp = ~((uint32_t)(init->prs_trigger_enable)); - tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); - eusart->TRIGCTRL_CLR = tmp; - eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); -} - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * Gets the clock associated to the specified EUSART instance. - * - * @param eusart Pointer to the EUSART peripheral register block. - * - * @return Clock corresponding to the eusart. - ******************************************************************************/ -static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart) -{ - CMU_Clock_TypeDef clock; - -#if defined(EUART0) - if (eusart == EUART0) { - clock = cmuClock_EUART0; - } -#endif -#if defined(EUSART0) - if (eusart == EUSART0) { - clock = cmuClock_EUSART0; - } -#endif -#if defined(EUSART1) - else if (eusart == EUSART1) { - clock = cmuClock_EUSART1; - } -#endif -#if defined(EUSART2) - else if (eusart == EUSART2) { - clock = cmuClock_EUSART2; - } -#endif -#if defined(EUSART3) - else if (eusart == EUSART3) { - clock = cmuClock_EUSART3; - } -#endif -#if defined(EUSART4) - else if (eusart == EUSART4) { - clock = cmuClock_EUSART4; - } -#endif - else { - EFM_ASSERT(0); - return (CMU_Clock_TypeDef)0u; - } - return clock; -} - -/***************************************************************************//** - * Initializes the EUSART with asynchronous common settings to high - * and low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - * @param irdaInit Pointer to IrDA initialization structure. - ******************************************************************************/ -static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, - const EUSART_UartInit_TypeDef *init, - const EUSART_IrDAInit_TypeDef *irdaInit, - const EUSART_DaliInit_TypeDef *daliInit) -{ - // LF register about to be modified requires sync busy check. - if (eusart->EN) { - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - } - // Initialize EUSART registers to hardware reset state. - EUSART_Reset(eusart); - - // Configure frame format - eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK - | _EUSART_FRAMECFG_STOPBITS_MASK - | _EUSART_FRAMECFG_PARITY_MASK)) - | (uint32_t)(init->databits) - | (uint32_t)(init->parity) - | (uint32_t)(init->stopbits); - - // Configure global configuration register 0. - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK - | _EUSART_CFG0_LOOPBK_MASK - | _EUSART_CFG0_MVDIS_MASK)) - | (uint32_t)(init->oversampling) - | (uint32_t)(init->loopbackEnable) - | (uint32_t)(init->majorityVote); - - if (init->baudrate == 0) { - eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN; - } - - if (init->advancedSettings) { - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK - | _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK - | _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK - | _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK)) - | (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT) - | (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT) - | (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK)) - | (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT) - | (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT) - | (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT) - | (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT); - - // Configure global configuration register 1. - eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK - | _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK)) - | (uint32_t)(init->advancedSettings->RxFifoWatermark) - | (uint32_t)(init->advancedSettings->TxFifoWatermark) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT); - - if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts - || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) { - eusart->CFG1 |= EUSART_CFG1_CTSEN; - } - // Enable RTS route pin if necessary. CTS is an input so it is enabled by default. - if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts) - || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) { -#if defined(EUART0) - GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; -#elif defined(EUSART0) - GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; -#endif - } else { -#if defined(EUART0) - GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; -#elif defined(EUSART0) - GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; -#endif - } - eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame; - if (init->advancedSettings->startFrame) { - eusart->CFG1 |= EUSART_CFG1_SFUBRX; - } - if (init->advancedSettings->prsRxEnable) { - eusart->CFG1 |= EUSART_CFG1_RXPRSEN; - // Configure PRS channel as input data line for EUSART. -#if defined(EUART_PRESENT) - PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK); -#elif defined(EUSART_PRESENT) - - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); - } -#endif -#endif - } - - // Configure global configuration timing register. - eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK) - | (uint32_t)(init->advancedSettings->autoTxDelay); - } - - if (irdaInit) { - if (irdaInit->irDALowFrequencyEnable) { - eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN); - } else { - // Configure IrDA HF configuration register. - eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK - | _EUSART_IRHFCFG_IRHFEN_MASK - | _EUSART_IRHFCFG_IRHFFILT_MASK)) - | (uint32_t)(EUSART_IRHFCFG_IRHFEN) - | (uint32_t)(irdaInit->irDAPulseWidth) - | (uint32_t)(irdaInit->irDARxFilterEnable); - } - } - -#if defined(EUSART_DALICFG_DALIEN) - // DALI-specific configuration section - if (daliInit) { - if (init->loopbackEnable) { - // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, - // then in this case DALIRXENDT should be set to 1. - eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT; - } - - if (EUSART_REF_VALID(eusart)) { - uint8_t index = EUSART_NUM(eusart); - - // keep track of the number of 16-bits packet to send - if (daliInit->TXdatabits <= eusartDaliTxDataBits16) { - dali_tx_nb_packets[index] = 1; - } else { - dali_tx_nb_packets[index] = 2; - } - - // keep track of the number of 16-bits packet to receive - if (daliInit->RXdatabits <= eusartDaliRxDataBits16) { - dali_rx_nb_packets[index] = 1; - } else { - dali_rx_nb_packets[index] = 2; - } - } - - // Configure the numbers of bits per TX and RX frames - eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK - | _EUSART_DALICFG_DALIRXDATABITS_MASK)) - | daliInit->TXdatabits - | daliInit->RXdatabits; - eusart->DALICFG_SET = EUSART_DALICFG_DALIEN; - } -#else - (void)(daliInit); -#endif /* EUSART_DALICFG_DALIEN */ - - // Enable EUSART IP. - EUSART_Enable(eusart, eusartEnable); - - // Configure the baudrate if auto baud detection is not used. - if (init->baudrate) { - EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate); - } - - // Finally enable the Rx and/or Tx channel (as specified). - EUSART_Enable(eusart, init->enable); - while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { - } -} - -#if defined(EUSART_PRESENT) -/***************************************************************************//** - * Initializes the EUSART with synchronous common settings to high - * and low frequency clock. - * - * @param eusart Pointer to the EUSART peripheral register block. - * @param init A pointer to the initialization structure. - ******************************************************************************/ -static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, - EUSART_SpiInit_TypeDef const *init) -{ - void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization. - - // LF register about to be modified requires sync busy check. - if (eusart->EN) { - eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); - } - - // Initialize EUSART registers to hardware reset state. - EUSART_Reset(eusart); - - // Configure global configuration register 2. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK - | _EUSART_CFG2_CLKPOL_MASK - | _EUSART_CFG2_CLKPHA_MASK - | _EUSART_CFG2_FORCELOAD_MASK)) - | (uint32_t)(init->master) - | (uint32_t)(init->clockMode) - | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default. - - if (advancedSetting_ptr) { - // Configure global configuration register 2. - eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK - | _EUSART_CFG2_AUTOCS_MASK - | _EUSART_CFG2_AUTOTX_MASK - | _EUSART_CFG2_CSINV_MASK - | _EUSART_CFG2_CLKPRSEN_MASK)) - | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT) - | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT) - | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT) - | (uint32_t)(init->advancedSettings->csPolarity) - | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT); - - // Only applicable to EM2 (low frequency) capable EUSART instances. - eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK - | _EUSART_CFG1_TXFIW_MASK)) - | (uint32_t)(init->advancedSettings->RxFifoWatermark) - | (uint32_t)(init->advancedSettings->TxFifoWatermark) - | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) - | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT); - } - - eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK - | _EUSART_CFG0_LOOPBK_MASK)) - | (uint32_t)(_EUSART_CFG0_SYNC_SYNC) - | (uint32_t)(init->loopbackEnable); - - if (advancedSetting_ptr) { - eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK); - eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT; - - // Configure global configurationTiming register. - eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK - | _EUSART_TIMINGCFG_CSHOLD_MASK - | _EUSART_TIMINGCFG_ICS_MASK - | _EUSART_TIMINGCFG_SETUPWINDOW_MASK)) - | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT) - & _EUSART_TIMINGCFG_CSSETUP_MASK) - | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT) - & _EUSART_TIMINGCFG_CSHOLD_MASK) - | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT) - & _EUSART_TIMINGCFG_ICS_MASK) - | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT) - & _EUSART_TIMINGCFG_SETUPWINDOW_MASK) - ; - } - - // Configure frame format - eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK)) - | (uint32_t)(init->databits); - - if (advancedSetting_ptr) { - eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK); - - if (init->advancedSettings->prsRxEnable) { - //Configure PRS channel as input data line for EUSART. - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); - } -#endif - } - - if (init->advancedSettings->prsClockEnable) { - //Configure PRS channel as SCLK input for EUSART. - if (eusart == EUSART0) { - PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK); - } -#if defined(EUSART1) - if (eusart == EUSART1) { - PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK); - } -#endif -#if defined(EUSART2) - if (eusart == EUSART2) { - PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK); - } -#endif -#if defined(EUSART3) - if (eusart == EUSART3) { - PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK); - } -#endif -#if defined(EUSART4) - if (eusart == EUSART4) { - PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK); - } -#endif - } - } - - // Set baudrate for synchronous operation mode. - EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate); - - // Enable EUSART IP. - EUSART_Enable(eusart, eusartEnable); - - // Finally enable the Rx and/or Tx channel (as specified). - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization. - eusart->CMD = (uint32_t)init->enable; - eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); - while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { - } -} -#endif - -/***************************************************************************//** - * Calculate baudrate for a given reference frequency, clock division, - * and oversampling rate when the module is in UART mode. - * - * @param refFreq The EUSART reference clock frequency in Hz that will be used. - * @param clkdiv Clock division factor to be used. - * @param ovs Oversampling to be used. - * - * @return Computed baudrate from given settings. - ******************************************************************************/ -__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - EUSART_OVS_TypeDef ovs) -{ - uint32_t oversample; - uint64_t divisor; - uint64_t factor; - uint64_t remainder; - uint64_t quotient; - uint32_t br; - - // Out of bound clkdiv. - EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); - - // Mask out unused bits - clkdiv &= _EUSART_CLKDIV_MASK; - - /* Use integer division to avoid forcing in float division - * utils and yet keep rounding effect errors to a minimum. - * - * Baudrate in is given by: - * - * br = fUARTn/(oversample * (1 + (CLKDIV / 256))) - * or - * br = (256 * fUARTn)/(oversample * (256 + CLKDIV)) - * - * 256 factor of the dividend is reduced with a - * (part of) oversample part of the divisor. - */ - - switch (ovs) { - case eusartOVS16: - oversample = 1; - factor = 256 / 16; - break; - - case eusartOVS8: - oversample = 1; - factor = 256 / 8; - break; - - case eusartOVS6: - oversample = 3; - factor = 256 / 2; - break; - - case eusartOVS4: - oversample = 1; - factor = 256 / 4; - break; - - case eusartOVS0: - oversample = 1; - factor = 256; - break; - - default: - return 0u; - break; - } - - /* - * The basic problem with integer division in the above formula is that - * the dividend (factor * fUARTn) may become larger than a 32 bit - * integer. Yet we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. Too harsh restrictions - * should not be made on the maximum fUARTn value either. - * - * For division a/b, - * - * a = qb + r - * - * where q is the quotient and r is the remainder, both integers. - * - * The original baudrate formula can be rewritten as - * - * br = xa / b = x(qb + r)/b = xq + xr/b - * - * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to - * variable names. - */ - - /* - * The divisor will never exceed max 32 bit value since - * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8) - * and 'oversample' has been reduced to <= 3. - */ - divisor = (uint64_t)(oversample * (256 + clkdiv)); - - quotient = refFreq / divisor; - remainder = refFreq % divisor; - - // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum - // 32 bit value. However, factor * remainder can become larger than 32-bit - // because of the size of _EUSART_CLKDIV_DIV_MASK on some families. - br = (uint32_t) (factor * quotient); - - /* - * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which - * means dividend (factor * remainder) worst case is - * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400. - */ - br += (uint32_t) ((factor * remainder) / divisor); - - return br; -} - -/***************************************************************************//** - * Perform EUSART Module disablement - resetting all internal flops/FSM. - * - * @param eusart Pointer to the EUSART peripheral register block. - ******************************************************************************/ -__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart) -{ - if (eusart->EN & _EUSART_EN_EN_MASK) { - // This step should be skipped especially in Synchronous Slave mode when - // external SCLK is not running and CS is active -#if defined(EUSART_PRESENT) - if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK)) -#endif - { - // General Programming Guideline to properly disable the module: - // 1a. Disable TX and RX using TXDIS and RXDIS cmd - eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS; - // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low; - eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS)); - // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low - while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) { - } - } -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - eusart->CLKDIV = eusart->CLKDIV; - eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); - - // Read data until FIFO is emptied - // but taking care not to underflow the receiver - while (eusart->STATUS & EUSART_STATUS_RXFL) { - eusart->RXDATA; - } -#endif - - eusart->EN_CLR = EUSART_EN_EN; - -#if defined(_EUSART_EN_DISABLING_MASK) - // 2. Polling for EUSARTn_EN.DISABLING = 0. - while (eusart->EN & _EUSART_EN_DISABLING_MASK) { - } -#endif - } -} - -#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Universal asynchronous receiver/transmitter (EUSART) peripheral API + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_eusart.h" +#if defined(EUART_PRESENT) || defined(EUSART_PRESENT) +#include "em_cmu.h" +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +#if defined(EUART_PRESENT) + #define EUSART_REF_VALID(ref) ((ref) == EUART0) + #define EUSART_EM2_CAPABLE(ref) (true) + #define EUSART_RX_FIFO_SIZE 4u +#elif defined(EUSART_PRESENT) + #define EUSART_REF_VALID(ref) (EUSART_NUM(ref) != -1) + #define EUSART_RX_FIFO_SIZE 16u +#endif + +/******************************************************************************* + ************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ +#if defined(EUSART_DALICFG_DALIEN) +static uint8_t dali_tx_nb_packets[EUSART_COUNT]; +static uint8_t dali_rx_nb_packets[EUSART_COUNT]; +#endif /* EUSART_DALICFG_DALIEN */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart); + +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit); + +#if defined(EUSART_PRESENT) +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_SpiInit_TypeDef *init); +#endif + +/***************************************************************************//** + * Wait for ongoing sync of register(s) to the low-frequency domain to complete. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param mask A bitmask corresponding to SYNCBUSY register defined bits, + * indicating registers that must complete any ongoing + * synchronization. + ******************************************************************************/ +__STATIC_INLINE void eusart_sync(EUSART_TypeDef *eusart, uint32_t mask) +{ + // Wait for any pending previous write operation to have been completed + // in the low-frequency domain. + while ((eusart->SYNCBUSY & mask) != 0U) { + } +} + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs); + +/***************************************************************************//** + * Execute the EUSART peripheral disabling sequence. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initializes the EUSART when used with the high frequency clock. + ******************************************************************************/ +void EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to HF. + // The oversampling must not be disabled when using a high frequency clock. + EFM_ASSERT(init->oversampling != eusartOVS0); + + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used with the low frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init) +{ + // Make sure the module exists and is Low frequency capable. + EFM_ASSERT(EUSART_REF_VALID(eusart) && EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // Init structure must be provided. + EFM_ASSERT(init); + + // Assert features specific to LF. + // LFXO, LFRCO, ULFRCO can be a clock source in LF. +#if defined(DEBUG_EFM) || defined(DEBUG_EFM_USER) + { + CMU_Select_TypeDef clock_source = (CMU_Select_TypeDef) NULL; +#if defined(EUART_PRESENT) + if (eusart == EUART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUART0); + } +#endif +#if defined(EUSART_PRESENT) && defined(EUSART0) + if (eusart == EUSART0) { + clock_source = CMU_ClockSelectGet(cmuClock_EUSART0); + } +#endif + + EFM_ASSERT( + (clock_source == cmuSelect_ULFRCO) + || (clock_source == cmuSelect_LFXO) + || (clock_source == cmuSelect_LFRCO) + || (clock_source == cmuSelect_EM23GRPACLK) +#if defined(_CMU_EUSART0CLKCTRL_CLKSEL_EM01GRPCCLK) + || (clock_source == cmuSelect_EM01GRPCCLK) /* ULFRCO, LFXO, LFRCO, EM23GRPACLK or EM01GRPCCLK */ +#endif + ); + } +#endif + // Uart mode only supports up to 9 databits frame. + EFM_ASSERT(init->databits <= eusartDataBits9); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(init->oversampling == eusartOVS0); + // The Majority Vote must be disabled when using a low frequency clock. + EFM_ASSERT(init->majorityVote == eusartMajorityVoteDisable); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((init->stopbits == eusartStopbits1) || (init->stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(init->baudrate <= 9600 && init->baudrate != 0); + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, init, NULL, NULL); +} + +/***************************************************************************//** + * Initializes the EUSART when used in IrDA mode with the high or low + * frequency clock. + ******************************************************************************/ +void EUSART_IrDAInit(EUSART_TypeDef *eusart, + const EUSART_IrDAInit_TypeDef *irdaInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(irdaInit); + + if (irdaInit->irDALowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(irdaInit->init.oversampling == eusartOVS0); + // Number of stop bits can only be 1 or 2 in LF. + EFM_ASSERT((irdaInit->init.stopbits == eusartStopbits1) || (irdaInit->init.stopbits == eusartStopbits2)); + // In LF, max baudrate is 9600. See Note #1. + EFM_ASSERT(irdaInit->init.baudrate <= 9600); + EFM_ASSERT(irdaInit->init.enable == eusartEnableRx || irdaInit->init.enable == eusartDisable); + } else { + EFM_ASSERT(irdaInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + EFM_ASSERT(irdaInit->init.baudrate >= 2400 && irdaInit->init.baudrate <= 1152000); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &irdaInit->init, irdaInit, NULL); +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART when used in SPI mode. + ******************************************************************************/ +void EUSART_SpiInit(EUSART_TypeDef *eusart, EUSART_SpiInit_TypeDef const *init) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(init); + if (init->master) { + EFM_ASSERT(init->bitRate <= 20000000); + + if (init->advancedSettings) { + EFM_ASSERT(!(init->advancedSettings->prsClockEnable)); + } + } else { + EFM_ASSERT(init->bitRate <= 10000000); + if (init->advancedSettings && init->advancedSettings->forceLoad) { + // If baud-rate is more than 5MHz, a value of 4 is recommended, any values + // smaller than that can be tried out but avoid using 0. If baud-rate is less than 5MHz, + // value of 5 is recommended, values higher than 5 can be used but it may make the load + // error easy to occur. The recommended values for frequency bands should be sufficient + // to work all the time. + EFM_ASSERT((init->bitRate >= 5000000 && init->advancedSettings->setupWindow <= 4) + || (init->bitRate < 5000000 && init->advancedSettings->setupWindow >= 5)); + } + } + + EUSART_SyncInitCommon(eusart, init); +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Initializes the EUSART when used in DALI mode with the high or low + * frequency clock. + * + * @note (1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral + * clock frequency must be at least three times higher than the + * chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), + * thus 32768 / 3 ~ 9600 baudrate. + ******************************************************************************/ +void EUSART_DaliInit(EUSART_TypeDef *eusart, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + // Init structure must be provided. + EFM_ASSERT(daliInit); + + if (daliInit->init.loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1 and DALIRXDATABITS should + // be set the same as DALITXDATABITS. + EFM_ASSERT( (daliInit->TXdatabits >> _EUSART_DALICFG_DALITXDATABITS_SHIFT) + == (daliInit->RXdatabits >> _EUSART_DALICFG_DALIRXDATABITS_SHIFT)); + } + + if (daliInit->daliLowFrequencyEnable) { + // Validate the low frequency capability of the EUSART instance. + EFM_ASSERT(EUSART_EM2_CAPABLE(EUSART_NUM(eusart))); + // The oversampling must be disabled when using a low frequency clock. + EFM_ASSERT(daliInit->init.oversampling == eusartOVS0); + // In LF, max baudrate is 9600. See Note #1. + // but manchester is running at 2x clock 9600 => 4800 + EFM_ASSERT(daliInit->init.baudrate <= 4800); + } else { + EFM_ASSERT(daliInit->init.oversampling != eusartOVS0); + // In HF, 2.4 kbps <= baudrate <= 1.152 Mbps. + // but manchester is running at 2x clock so 2.4 kbps => 1.2 kbps + EFM_ASSERT(daliInit->init.baudrate >= 1200 && daliInit->init.baudrate <= 57600); + } + + // Initialize EUSART with common features to HF and LF. + EUSART_AsyncInitCommon(eusart, &daliInit->init, NULL, daliInit); +} +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configure the EUSART to its reset state. + ******************************************************************************/ +void EUSART_Reset(EUSART_TypeDef *eusart) +{ + // 1. Properly disable the module + EUSART_Disable(eusart); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) + // Manual toggling tx_sclk_mst to synchronize handshake + // when switching from SPI master to other modes + // so module is disabling correctly. + uint32_t forcedClkCycle = 4u; + + while (forcedClkCycle--) { + eusart->CFG2_SET = _EUSART_CFG2_CLKPHA_MASK; + eusart->CFG2_CLR = _EUSART_CFG2_CLKPHA_MASK; + } +#endif + // All registers that end with CFG should be programmed before EUSART gets enabled (EUSARTn_EN is set). + // Set all configurable register to its reset value. + // Note: Program desired settings to all registers that have names ending with CFG in the following sequence: + // a. CFG2 +#if defined(EUSART_PRESENT) + eusart->CFG2 = _EUSART_CFG2_RESETVALUE; +#endif + // b. CFG1 + eusart->CFG1 = _EUSART_CFG1_RESETVALUE; + // c. CFG0 + eusart->CFG0 = _EUSART_CFG0_RESETVALUE; + // d. FRAMECFG, DTXDATCFG, TIMINGCFG (Any sequence) + eusart->FRAMECFG = _EUSART_FRAMECFG_RESETVALUE; +#if defined(EUSART_PRESENT) + eusart->DTXDATCFG = _EUSART_DTXDATCFG_RESETVALUE; +#if defined(EUSART_DALICFG_DALIEN) + eusart->DALICFG = _EUSART_DALICFG_RESETVALUE; +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + eusart->TIMINGCFG = _EUSART_TIMINGCFG_RESETVALUE; + eusart->IRHFCFG = _EUSART_IRHFCFG_RESETVALUE; + eusart->IRLFCFG = _EUSART_IRLFCFG_RESETVALUE; + eusart->STARTFRAMECFG = _EUSART_STARTFRAMECFG_RESETVALUE; + eusart->SIGFRAMECFG = _EUSART_SIGFRAMECFG_RESETVALUE; + eusart->TRIGCTRL = _EUSART_TRIGCTRL_RESETVALUE; + eusart->IEN = _EUSART_IEN_RESETVALUE; + eusart->IF_CLR = _EUSART_IF_MASK; + + // no need to sync while EN=0, multiple writes can be queued up, + // and the last one will synchronize once EN=1 + eusart->CLKDIV = _EUSART_CLKDIV_RESETVALUE; +} + +/***************************************************************************//** + * Enables/disables the EUSART receiver and/or transmitter. + ******************************************************************************/ +void EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable) +{ + uint32_t tmp = 0; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + if (enable == eusartDisable) { + EUSART_Disable(eusart); + } else { + // Enable peripheral to configure Rx and Tx. + eusart->EN_SET = EUSART_EN_EN; + + // Enable or disable Rx and/or Tx + tmp = (enable) + & (_EUSART_CMD_RXEN_MASK | _EUSART_CMD_TXEN_MASK + | _EUSART_CMD_RXDIS_MASK | _EUSART_CMD_TXDIS_MASK); + + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + eusart->CMD = tmp; + eusart_sync(eusart, + EUSART_SYNCBUSY_RXEN | EUSART_SYNCBUSY_TXEN + | EUSART_SYNCBUSY_RXDIS | EUSART_SYNCBUSY_TXDIS); + + // Wait for the status register to be updated. + tmp = 0; + if (_EUSART_CMD_RXEN_MASK & enable) { + tmp |= EUSART_STATUS_RXENS; + } + if (_EUSART_CMD_TXEN_MASK & enable) { + tmp |= EUSART_STATUS_TXENS; + } + while ((eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) != tmp) { + } + } +} + +/***************************************************************************//** + * Receives one 8 bit frame, (or part of 9 bit frame). + * + * @note (1) Handles the case where the RX Fifo Watermark has been set to N frames, + * and when N is greater than one. Attempt to read a frame from the RX Fifo. + * If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU + * interrupt flag is set. If the flag is set, wait to read again until the RXFL + * status flag is set, indicating there are N frames in the RX Fifo, where N + * is equal to the RX watermark level. Once there are N frames in the Fifo, + * read and return one frame. For consecutive N-1 reads there will be data available + * in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating + * delays between reads and sending N data frames in "bursts". + ******************************************************************************/ +uint8_t EUSART_Rx(EUSART_TypeDef *eusart) +{ + // If RX watermark has not been configured. + if ((eusart->CFG1 & _EUSART_CFG1_RXFIW_MASK) == EUSART_CFG1_RXFIW_DEFAULT) { + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + return (uint8_t)eusart->RXDATA; + } + + // See Note #1. + uint8_t rx_data = eusart->RXDATA; + // If there is underflow i.e Rx data read was unsuccessful + if (eusart->IF & EUSART_IF_RXUF) { + // Wait until data becomes available in Rx fifo + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + // Read Rx data again once data is available in the fifo + rx_data = eusart->RXDATA; + } + + return rx_data; +} + +/***************************************************************************//** + * Receives one 8-9 bit frame with extended information. + ******************************************************************************/ +uint16_t EUSART_RxExt(EUSART_TypeDef *eusart) +{ + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + return (uint16_t)eusart->RXDATA; +} + +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * Transmits one 8-9 bit frame with extended control. + ******************************************************************************/ +void EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + eusart->TXDATA = (uint32_t)data; +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Transmits one 8-16 bit frame and return received data. + ******************************************************************************/ +uint16_t EUSART_Spi_TxRx(EUSART_TypeDef *eusart, uint16_t data) +{ + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + eusart->TXDATA = (uint32_t)data; + + // Wait for Rx data to be available. + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } + return (uint16_t)eusart->RXDATA; +} + +#if defined(EUSART_DALICFG_DALIEN) +/***************************************************************************//** + * Transmits one frame. + ******************************************************************************/ +void EUSART_Dali_Tx(EUSART_TypeDef *eusart, uint32_t data) +{ + uint32_t packet; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Check that transmit FIFO is not full. + while (!(eusart->STATUS & EUSART_STATUS_TXFL)) { + } + + for (uint8_t index = 0; index < dali_tx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // First write to TXDATA register should contain 16 LSBs of the TX frame. + // Transmission will not start after this first write. + // Second write to TXDATA register should contain the remaining TX frame bits. + // This second write will result in start of transmission. + packet = (data >> (index * 16)); + // To ensure compatibility with future devices, always write bits [31:16] to 0. + packet &= 0x0000FFFF; + eusart->TXDATA = packet; + } +} + +/***************************************************************************//** + * Receive one frame. + ******************************************************************************/ +uint32_t EUSART_Dali_Rx(EUSART_TypeDef *eusart) +{ + uint32_t data = 0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + while (!(eusart->STATUS & EUSART_STATUS_RXFL)) { + } // Wait for incoming data. + + for (uint8_t index = 0; index < dali_rx_nb_packets[EUSART_NUM(eusart)]; index++) { + // when DALICFG.DALIEN is set to 1, then all 16 bits [15:0] represent data + // When receiving a frame that has more than 16 databits, + // RXDATA register needs to be read twice: + // First read will provide 16 LSBs of the received frame. + // Second read will provide the remaining RX frame bits. + data |= ((eusart->RXDATA & _EUSART_RXDATA_RXDATA_MASK) << (index * 16)); + } + return data; +} + +#endif /* EUSART_DALICFG_DALIEN */ +#endif /* EUSART_PRESENT */ + +/***************************************************************************//** + * Configures the baudrate (or as close as possible to a specified baudrate) + * depending on the current mode of the EU(S)ART peripheral. + * + * @note (1) When the oversampling is disabled, the peripheral clock frequency + * must be at least three times higher than the chosen baud rate. + ******************************************************************************/ +void EUSART_BaudrateSet(EUSART_TypeDef *eusart, + uint32_t refFreq, + uint32_t baudrate) +{ + uint32_t clkdiv; + uint8_t oversample = 0; + + // Prevent dividing by 0. + EFM_ASSERT(baudrate); + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // Get the current frequency. + if (!refFreq) { + refFreq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + } + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK ) { + EFM_ASSERT(baudrate <= refFreq); + + EUSART_Enable_TypeDef txrxEnStatus = eusartDisable; + bool wasEnabled = (eusart->EN & _EUSART_EN_EN_MASK) == true; + clkdiv = refFreq / baudrate - 1UL; + + // If the desired bit rate requires a divider larger than the Synchronous divider bitfield (CFG2_SDIV), + // the resulting spi master bus clock will be undefined because the result will be truncated. + EFM_ASSERT(clkdiv <= (_EUSART_CFG2_SDIV_MASK >> _EUSART_CFG2_SDIV_SHIFT)); + + if (wasEnabled) { + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + + // Save the state of the reveiver and transmitter before disabling the peripheral. + if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK | _EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnable; + } else if (eusart->STATUS & (_EUSART_STATUS_RXENS_MASK)) { + txrxEnStatus = eusartEnableRx; + } else if (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK)) { + txrxEnStatus = eusartEnableTx; + } else { + EFM_ASSERT(false); + } + + // Disable the eusart to be able to modify the CFG2 register. + EUSART_Disable(eusart); + } + + // In Synchronous mode the clock divider that is managing the bitRate + // is located inside the sdiv bitfield of the CFG2 register instead of + // the CLKDIV register combined with the oversample setting for asynchronous mode. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_SDIV_MASK)) | ((clkdiv << _EUSART_CFG2_SDIV_SHIFT) & _EUSART_CFG2_SDIV_MASK); + + if (wasEnabled) { + EUSART_Enable(eusart, txrxEnStatus); + } + } else // In asynchronous mode (ex: UART) +#endif + { + // The peripheral must be enabled to configure the baud rate. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + baudrate *= 2; + } +#endif + + /* + * Use integer division to avoid forcing in float division + * utils, and yet keep rounding effect errors to a minimum. + * + * CLKDIV is given by: + * + * CLKDIV = 256 * (fUARTn/(oversample * br) - 1) + * or + * CLKDIV = (256 * fUARTn)/(oversample * br) - 256 + * + * Since fUARTn may be derived from HFCORECLK, consider the overflow when + * using integer arithmetic. + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fUARTn) may become higher than the maximum 32 bit + * integer. Yet, the dividend should be evaluated first before dividing + * to get as small rounding effects as possible. + * Also, harsh restrictions on the maximum fUARTn value should not be made. + * + * Since the last 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula: + * + * CLKDIV/8 = ((32*fUARTn)/(br * Oversample)) - 32 + * + * and calculate 1/8 of CLKDIV first. This allows for fUARTn + * up to 128 MHz without overflowing a 32 bit value. + */ + + // Map oversampling. + switch (eusart->CFG0 & _EUSART_CFG0_OVS_MASK) { + case eusartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case eusartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case eusartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case eusartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + case eusartOVS0: + EFM_ASSERT(refFreq >= (3 * baudrate)); // See Note #1. + oversample = 1; + break; + + default: + // Invalid input + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + // Calculate and set the CLKDIV with fractional bits. + clkdiv = (32 * refFreq) / (baudrate * oversample); + clkdiv -= 32; + clkdiv *= 8; + + // Verify that the resulting clock divider is within limits. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // If the EFM_ASSERT is not enabled, make sure not to write to reserved bits. + clkdiv &= _EUSART_CLKDIV_MASK; + + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + eusart->CLKDIV = clkdiv; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + } + } +} + +/***************************************************************************//** + * Gets the current baudrate. + ******************************************************************************/ +uint32_t EUSART_BaudrateGet(EUSART_TypeDef *eusart) +{ + uint32_t freq; + uint32_t div = 1; + uint32_t br = 0; + EUSART_OVS_TypeDef ovs = eusartOVS0; + + // Make sure the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + freq = CMU_ClockFreqGet(EUSART_ClockGet(eusart)); + +#if defined(EUSART_PRESENT) + // In synchronous mode (ex: SPI) + if (eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) { + div = (eusart->CFG2 & _EUSART_CFG2_SDIV_MASK) >> _EUSART_CFG2_SDIV_SHIFT; + br = freq / (div + 1); + } + // In asynchronous mode (ex: UART) + else +#endif + { + div = eusart->CLKDIV; + ovs = (EUSART_OVS_TypeDef)(eusart->CFG0 & _EUSART_CFG0_OVS_MASK); + br = EUSART_AsyncBaudrateCalc(freq, div, ovs); + +#if defined(EUSART_DALICFG_DALIEN) + if (eusart->DALICFG & EUSART_DALICFG_DALIEN) { + // adjust for manchester double-clocking scheme + br /= 2; + } +#endif + } + + return br; +} + +/***************************************************************************//** + * Enable/Disable reception operations until the configured start frame is + * received. + ******************************************************************************/ +void EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_RXBLOCKEN_MASK | _EUSART_CMD_RXBLOCKDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + eusart->CMD_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXBLOCKEN | EUSART_SYNCBUSY_RXBLOCKDIS); + + tmp = 0u; + if ((_EUSART_CMD_RXBLOCKEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_RXBLOCK; + } + while ((eusart->STATUS & _EUSART_STATUS_RXBLOCK_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Enables/Disables the tristating of the transmitter output. + ******************************************************************************/ +void EUSART_TxTristateSet(EUSART_TypeDef *eusart, + EUSART_TristateTx_TypeDef enable) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + tmp = ((uint32_t)(enable)); + tmp &= (_EUSART_CMD_TXTRIEN_MASK | _EUSART_CMD_TXTRIDIS_MASK); + + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + eusart->CMD = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_TXTRIEN | EUSART_SYNCBUSY_TXTRIDIS); + + tmp = 0u; + if ((_EUSART_CMD_TXTRIEN_MASK & enable) != 0u) { + tmp |= EUSART_STATUS_TXTRI; + } + while ((eusart->STATUS & _EUSART_STATUS_TXTRI_MASK) != tmp) { + } // Wait for the status register to be updated. +} + +/***************************************************************************//** + * Initializes the automatic enabling of transmissions and/or reception using + * the PRS as a trigger. + ******************************************************************************/ +void EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, + const EUSART_PrsTriggerInit_TypeDef *init) +{ + uint32_t tmp; + + // Make sure that the module exists on the selected chip. + EFM_ASSERT(EUSART_REF_VALID(eusart)); + + // The peripheral must be enabled to configure the PRS trigger. + EFM_ASSERT(eusart->EN == EUSART_EN_EN); + +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUART0_TRIGGER_MASK); +#else + +#if defined(EUSART0) + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART0_TRIGGER_MASK); + } +#endif +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART1_TRIGGER_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART2_TRIGGER_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART3_TRIGGER_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_TRIGGER = (init->prs_trigger_channel & _PRS_CONSUMER_EUSART4_TRIGGER_MASK); + } +#endif +#endif + + tmp = ((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + + eusart->TRIGCTRL_SET = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); + + tmp = ~((uint32_t)(init->prs_trigger_enable)); + tmp &= (_EUSART_TRIGCTRL_RXTEN_MASK | _EUSART_TRIGCTRL_TXTEN_MASK); + eusart->TRIGCTRL_CLR = tmp; + eusart_sync(eusart, EUSART_SYNCBUSY_RXTEN | EUSART_SYNCBUSY_TXTEN); +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Gets the clock associated to the specified EUSART instance. + * + * @param eusart Pointer to the EUSART peripheral register block. + * + * @return Clock corresponding to the eusart. + ******************************************************************************/ +static CMU_Clock_TypeDef EUSART_ClockGet(EUSART_TypeDef *eusart) +{ + CMU_Clock_TypeDef clock; + +#if defined(EUART0) + if (eusart == EUART0) { + clock = cmuClock_EUART0; + } +#endif +#if defined(EUSART0) + if (eusart == EUSART0) { + clock = cmuClock_EUSART0; + } +#endif +#if defined(EUSART1) + else if (eusart == EUSART1) { + clock = cmuClock_EUSART1; + } +#endif +#if defined(EUSART2) + else if (eusart == EUSART2) { + clock = cmuClock_EUSART2; + } +#endif +#if defined(EUSART3) + else if (eusart == EUSART3) { + clock = cmuClock_EUSART3; + } +#endif +#if defined(EUSART4) + else if (eusart == EUSART4) { + clock = cmuClock_EUSART4; + } +#endif + else { + EFM_ASSERT(0); + return (CMU_Clock_TypeDef)0u; + } + return clock; +} + +/***************************************************************************//** + * Initializes the EUSART with asynchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + * @param irdaInit Pointer to IrDA initialization structure. + ******************************************************************************/ +static void EUSART_AsyncInitCommon(EUSART_TypeDef *eusart, + const EUSART_UartInit_TypeDef *init, + const EUSART_IrDAInit_TypeDef *irdaInit, + const EUSART_DaliInit_TypeDef *daliInit) +{ + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK + | _EUSART_FRAMECFG_STOPBITS_MASK + | _EUSART_FRAMECFG_PARITY_MASK)) + | (uint32_t)(init->databits) + | (uint32_t)(init->parity) + | (uint32_t)(init->stopbits); + + // Configure global configuration register 0. + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_OVS_MASK + | _EUSART_CFG0_LOOPBK_MASK + | _EUSART_CFG0_MVDIS_MASK)) + | (uint32_t)(init->oversampling) + | (uint32_t)(init->loopbackEnable) + | (uint32_t)(init->majorityVote); + + if (init->baudrate == 0) { + eusart->CFG0 |= EUSART_CFG0_AUTOBAUDEN; + } + + if (init->advancedSettings) { + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_ERRSDMA_MASK | _EUSART_CFG0_AUTOTRI_MASK + | _EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK + | _EUSART_CFG0_CCEN_MASK | _EUSART_CFG0_MPM_MASK + | _EUSART_CFG0_MPAB_MASK | _EUSART_CFG0_MSBF_MASK)) + | (uint32_t)(init->advancedSettings->dmaHaltOnError << _EUSART_CFG0_ERRSDMA_SHIFT) + | (uint32_t)(init->advancedSettings->txAutoTristate << _EUSART_CFG0_AUTOTRI_SHIFT) + | (uint32_t)(init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK)) + | (uint32_t)(init->advancedSettings->collisionDetectEnable << _EUSART_CFG0_CCEN_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorEnable << _EUSART_CFG0_MPM_SHIFT) + | (uint32_t)(init->advancedSettings->multiProcessorAddressBitHigh << _EUSART_CFG0_MPAB_SHIFT) + | (uint32_t)(init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT); + + // Configure global configuration register 1. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK | _EUSART_CFG1_TXFIW_MASK + | _EUSART_CFG1_RXDMAWU_MASK | _EUSART_CFG1_TXDMAWU_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnTx << _EUSART_CFG1_TXDMAWU_SHIFT); + + if (init->advancedSettings->hwFlowControl == eusartHwFlowControlCts + || init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts) { + eusart->CFG1 |= EUSART_CFG1_CTSEN; + } + // Enable RTS route pin if necessary. CTS is an input so it is enabled by default. + if ((init->advancedSettings->hwFlowControl == eusartHwFlowControlRts) + || (init->advancedSettings->hwFlowControl == eusartHwFlowControlCtsAndRts)) { +#if defined(EUART0) + GPIO->EUARTROUTE_SET->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_SET[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } else { +#if defined(EUART0) + GPIO->EUARTROUTE_CLR->ROUTEEN = GPIO_EUART_ROUTEEN_RTSPEN; +#elif defined(EUSART0) + GPIO->EUSARTROUTE_CLR[EUSART_NUM(eusart)].ROUTEEN = GPIO_EUSART_ROUTEEN_RTSPEN; +#endif + } + eusart->STARTFRAMECFG_SET = (uint32_t)init->advancedSettings->startFrame; + if (init->advancedSettings->startFrame) { + eusart->CFG1 |= EUSART_CFG1_SFUBRX; + } + if (init->advancedSettings->prsRxEnable) { + eusart->CFG1 |= EUSART_CFG1_RXPRSEN; + // Configure PRS channel as input data line for EUSART. +#if defined(EUART_PRESENT) + PRS->CONSUMER_EUART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUART0_RX_MASK); +#elif defined(EUSART_PRESENT) + + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif +#endif + } + + // Configure global configuration timing register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~_EUSART_TIMINGCFG_TXDELAY_MASK) + | (uint32_t)(init->advancedSettings->autoTxDelay); + } + + if (irdaInit) { + if (irdaInit->irDALowFrequencyEnable) { + eusart->IRLFCFG_SET = (uint32_t)(EUSART_IRLFCFG_IRLFEN); + } else { + // Configure IrDA HF configuration register. + eusart->IRHFCFG_SET = (eusart->IRHFCFG & ~(_EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFEN_MASK + | _EUSART_IRHFCFG_IRHFFILT_MASK)) + | (uint32_t)(EUSART_IRHFCFG_IRHFEN) + | (uint32_t)(irdaInit->irDAPulseWidth) + | (uint32_t)(irdaInit->irDARxFilterEnable); + } + } + +#if defined(EUSART_DALICFG_DALIEN) + // DALI-specific configuration section + if (daliInit) { + if (init->loopbackEnable) { + // If LOOPBK in CFG0 is set to 1 in order to do loopback testing for DALI, + // then in this case DALIRXENDT should be set to 1. + eusart->DALICFG_SET = EUSART_DALICFG_DALIRXENDT; + } + + if (EUSART_REF_VALID(eusart)) { + uint8_t index = EUSART_NUM(eusart); + + // keep track of the number of 16-bits packet to send + if (daliInit->TXdatabits <= eusartDaliTxDataBits16) { + dali_tx_nb_packets[index] = 1; + } else { + dali_tx_nb_packets[index] = 2; + } + + // keep track of the number of 16-bits packet to receive + if (daliInit->RXdatabits <= eusartDaliRxDataBits16) { + dali_rx_nb_packets[index] = 1; + } else { + dali_rx_nb_packets[index] = 2; + } + } + + // Configure the numbers of bits per TX and RX frames + eusart->DALICFG = (eusart->DALICFG & ~(_EUSART_DALICFG_DALITXDATABITS_MASK + | _EUSART_DALICFG_DALIRXDATABITS_MASK)) + | daliInit->TXdatabits + | daliInit->RXdatabits; + eusart->DALICFG_SET = EUSART_DALICFG_DALIEN; + } +#else + (void)(daliInit); +#endif /* EUSART_DALICFG_DALIEN */ + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Configure the baudrate if auto baud detection is not used. + if (init->baudrate) { + EUSART_BaudrateSet(eusart, init->refFreq, init->baudrate); + } + + // Finally enable the Rx and/or Tx channel (as specified). + EUSART_Enable(eusart, init->enable); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} + +#if defined(EUSART_PRESENT) +/***************************************************************************//** + * Initializes the EUSART with synchronous common settings to high + * and low frequency clock. + * + * @param eusart Pointer to the EUSART peripheral register block. + * @param init A pointer to the initialization structure. + ******************************************************************************/ +static void EUSART_SyncInitCommon(EUSART_TypeDef *eusart, + EUSART_SpiInit_TypeDef const *init) +{ + void* advancedSetting_ptr = (void*)init->advancedSettings; // Used to avoid GCC over optimization. + + // LF register about to be modified requires sync busy check. + if (eusart->EN) { + eusart_sync(eusart, _EUSART_SYNCBUSY_MASK); + } + + // Initialize EUSART registers to hardware reset state. + EUSART_Reset(eusart); + + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_MASTER_MASK + | _EUSART_CFG2_CLKPOL_MASK + | _EUSART_CFG2_CLKPHA_MASK + | _EUSART_CFG2_FORCELOAD_MASK)) + | (uint32_t)(init->master) + | (uint32_t)(init->clockMode) + | (uint32_t)(EUSART_CFG2_FORCELOAD); // Force load feature enabled by default. + + if (advancedSetting_ptr) { + // Configure global configuration register 2. + eusart->CFG2 = (eusart->CFG2 & ~(_EUSART_CFG2_FORCELOAD_MASK + | _EUSART_CFG2_AUTOCS_MASK + | _EUSART_CFG2_AUTOTX_MASK + | _EUSART_CFG2_CSINV_MASK + | _EUSART_CFG2_CLKPRSEN_MASK)) + | (uint32_t)(init->advancedSettings->forceLoad << _EUSART_CFG2_FORCELOAD_SHIFT) + | (uint32_t)(init->advancedSettings->autoCsEnable << _EUSART_CFG2_AUTOCS_SHIFT) + | (uint32_t)(init->advancedSettings->autoTxEnable << _EUSART_CFG2_AUTOTX_SHIFT) + | (uint32_t)(init->advancedSettings->csPolarity) + | (uint32_t)(init->advancedSettings->prsClockEnable << _EUSART_CFG2_CLKPRSEN_SHIFT); + + // Only applicable to EM2 (low frequency) capable EUSART instances. + eusart->CFG1 = (eusart->CFG1 & ~(_EUSART_CFG1_RXFIW_MASK + | _EUSART_CFG1_TXFIW_MASK)) + | (uint32_t)(init->advancedSettings->RxFifoWatermark) + | (uint32_t)(init->advancedSettings->TxFifoWatermark) + | (uint32_t)(init->advancedSettings->dmaWakeUpOnRx << _EUSART_CFG1_RXDMAWU_SHIFT) + | (uint32_t)(init->advancedSettings->prsRxEnable << _EUSART_CFG1_RXPRSEN_SHIFT); + } + + eusart->CFG0 = (eusart->CFG0 & ~(_EUSART_CFG0_SYNC_MASK + | _EUSART_CFG0_LOOPBK_MASK)) + | (uint32_t)(_EUSART_CFG0_SYNC_SYNC) + | (uint32_t)(init->loopbackEnable); + + if (advancedSetting_ptr) { + eusart->CFG0 |= (uint32_t)init->advancedSettings->invertIO & (_EUSART_CFG0_RXINV_MASK | _EUSART_CFG0_TXINV_MASK); + eusart->CFG0 |= (uint32_t)init->advancedSettings->msbFirst << _EUSART_CFG0_MSBF_SHIFT; + + // Configure global configurationTiming register. + eusart->TIMINGCFG = (eusart->TIMINGCFG & ~(_EUSART_TIMINGCFG_CSSETUP_MASK + | _EUSART_TIMINGCFG_CSHOLD_MASK + | _EUSART_TIMINGCFG_ICS_MASK + | _EUSART_TIMINGCFG_SETUPWINDOW_MASK)) + | ((uint32_t)(init->advancedSettings->autoCsSetupTime << _EUSART_TIMINGCFG_CSSETUP_SHIFT) + & _EUSART_TIMINGCFG_CSSETUP_MASK) + | ((uint32_t)(init->advancedSettings->autoCsHoldTime << _EUSART_TIMINGCFG_CSHOLD_SHIFT) + & _EUSART_TIMINGCFG_CSHOLD_MASK) + | ((uint32_t)(init->advancedSettings->autoInterFrameTime << _EUSART_TIMINGCFG_ICS_SHIFT) + & _EUSART_TIMINGCFG_ICS_MASK) + | ((uint32_t)(init->advancedSettings->setupWindow << _EUSART_TIMINGCFG_SETUPWINDOW_SHIFT) + & _EUSART_TIMINGCFG_SETUPWINDOW_MASK) + ; + } + + // Configure frame format + eusart->FRAMECFG = (eusart->FRAMECFG & ~(_EUSART_FRAMECFG_DATABITS_MASK)) + | (uint32_t)(init->databits); + + if (advancedSetting_ptr) { + eusart->DTXDATCFG = (init->advancedSettings->defaultTxData & _EUSART_DTXDATCFG_MASK); + + if (init->advancedSettings->prsRxEnable) { + //Configure PRS channel as input data line for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART0_RX_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART1_RX_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART2_RX_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART3_RX_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_RX_SET = (init->advancedSettings->prsRxChannel & _PRS_CONSUMER_EUSART4_RX_MASK); + } +#endif + } + + if (init->advancedSettings->prsClockEnable) { + //Configure PRS channel as SCLK input for EUSART. + if (eusart == EUSART0) { + PRS->CONSUMER_EUSART0_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART0_CLK_MASK); + } +#if defined(EUSART1) + if (eusart == EUSART1) { + PRS->CONSUMER_EUSART1_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART1_CLK_MASK); + } +#endif +#if defined(EUSART2) + if (eusart == EUSART2) { + PRS->CONSUMER_EUSART2_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART2_CLK_MASK); + } +#endif +#if defined(EUSART3) + if (eusart == EUSART3) { + PRS->CONSUMER_EUSART3_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART3_CLK_MASK); + } +#endif +#if defined(EUSART4) + if (eusart == EUSART4) { + PRS->CONSUMER_EUSART4_CLK_SET = (init->advancedSettings->prsClockChannel & _PRS_CONSUMER_EUSART4_CLK_MASK); + } +#endif + } + } + + // Set baudrate for synchronous operation mode. + EUSART_BaudrateSet(eusart, init->refFreq, init->bitRate); + + // Enable EUSART IP. + EUSART_Enable(eusart, eusartEnable); + + // Finally enable the Rx and/or Tx channel (as specified). + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); // Wait for low frequency register synchronization. + eusart->CMD = (uint32_t)init->enable; + eusart_sync(eusart, _EUSART_SYNCBUSY_RXEN_MASK | _EUSART_SYNCBUSY_TXEN_MASK); + while (~EUSART_StatusGet(eusart) & (_EUSART_STATUS_RXIDLE_MASK | _EUSART_STATUS_TXIDLE_MASK)) { + } +} +#endif + +/***************************************************************************//** + * Calculate baudrate for a given reference frequency, clock division, + * and oversampling rate when the module is in UART mode. + * + * @param refFreq The EUSART reference clock frequency in Hz that will be used. + * @param clkdiv Clock division factor to be used. + * @param ovs Oversampling to be used. + * + * @return Computed baudrate from given settings. + ******************************************************************************/ +__STATIC_INLINE uint32_t EUSART_AsyncBaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + EUSART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + // Out of bound clkdiv. + EFM_ASSERT(clkdiv <= _EUSART_CLKDIV_MASK); + + // Mask out unused bits + clkdiv &= _EUSART_CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * Baudrate in is given by: + * + * br = fUARTn/(oversample * (1 + (CLKDIV / 256))) + * or + * br = (256 * fUARTn)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case eusartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case eusartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case eusartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + case eusartOVS4: + oversample = 1; + factor = 256 / 4; + break; + + case eusartOVS0: + oversample = 1; + factor = 256; + break; + + default: + return 0u; + break; + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fUARTn) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fUARTn value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _EUSART_CLKDIV_MASK (currently 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + // The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum + // 32 bit value. However, factor * remainder can become larger than 32-bit + // because of the size of _EUSART_CLKDIV_DIV_MASK on some families. + br = (uint32_t) (factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _EUSART_CLKDIV_MASK)) = 0xC001_7400. + */ + br += (uint32_t) ((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * Perform EUSART Module disablement - resetting all internal flops/FSM. + * + * @param eusart Pointer to the EUSART peripheral register block. + ******************************************************************************/ +__STATIC_INLINE void EUSART_Disable(EUSART_TypeDef *eusart) +{ + if (eusart->EN & _EUSART_EN_EN_MASK) { + // This step should be skipped especially in Synchronous Slave mode when + // external SCLK is not running and CS is active +#if defined(EUSART_PRESENT) + if (!(eusart->CFG0 & _EUSART_CFG0_SYNC_MASK) || (eusart->CFG2 & _EUSART_CFG2_MASTER_MASK)) +#endif + { + // General Programming Guideline to properly disable the module: + // 1a. Disable TX and RX using TXDIS and RXDIS cmd + eusart->CMD = EUSART_CMD_TXDIS | EUSART_CMD_RXDIS; + // 1b. Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low; + eusart_sync(eusart, (EUSART_SYNCBUSY_TXDIS | EUSART_SYNCBUSY_RXDIS)); + // 1c. Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low + while (eusart->STATUS & (_EUSART_STATUS_TXENS_MASK | _EUSART_STATUS_RXENS_MASK)) { + } + } +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + eusart->CLKDIV = eusart->CLKDIV; + eusart_sync(eusart, _EUSART_SYNCBUSY_DIV_MASK); + + // Read data until FIFO is emptied + // but taking care not to underflow the receiver + while (eusart->STATUS & EUSART_STATUS_RXFL) { + eusart->RXDATA; + } +#endif + + eusart->EN_CLR = EUSART_EN_EN; + +#if defined(_EUSART_EN_DISABLING_MASK) + // 2. Polling for EUSARTn_EN.DISABLING = 0. + while (eusart->EN & _EUSART_EN_DISABLING_MASK) { + } +#endif + } +} + +#endif /* defined(EUART_PRESENT) || defined(EUSART_PRESENT) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c index 7c55113..7d81d69 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpcrc.c @@ -1,138 +1,138 @@ -/***************************************************************************//** - * @file - * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_common.h" -#include "em_gpcrc.h" -#include "sl_assert.h" - -#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) - -/***************************************************************************//** - * @addtogroup gpcrc - * @{ - ******************************************************************************/ - -/******************************************************************************* - *************************** GLOBAL FUNCTIONS ****************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize the General Purpose Cyclic Redundancy Check (GPCRC) module. - * - * @details - * Use this function to configure the operational parameters of the GPCRC, - * such as the polynomial to use and how the input should be preprocessed - * before entering the CRC calculation. - * - * @note - * This function will not copy the initialization value to the data register - * to prepare for a new CRC calculation. Either call - * @ref GPCRC_Start before each calculation or by use the - * autoInit functionality. - * - * @param[in] gpcrc - * A pointer to the GPCRC peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure the GPCRC. - ******************************************************************************/ -void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init) -{ - uint32_t polySelect; - uint32_t revPoly = 0; - - if (init->crcPoly == 0x04C11DB7) { - polySelect = GPCRC_CTRL_POLYSEL_CRC32; - } else { - // If not using the fixed CRC-32 polynomial, use 16-bit. - EFM_ASSERT((init->crcPoly & 0xFFFF0000UL) == 0U); -#if defined(GPCRC_CTRL_POLYSEL_CRC16) - polySelect = GPCRC_CTRL_POLYSEL_CRC16; -#else - polySelect = GPCRC_CTRL_POLYSEL_16; -#endif - revPoly = SL_RBIT16(init->crcPoly); - } - -#if defined(GPCRC_EN_EN) - if (init->enable) { - gpcrc->EN_SET = GPCRC_EN_EN; - } else { - gpcrc->EN_CLR = GPCRC_EN_EN; - } - - gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) - | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) - | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) - | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) - | polySelect); -#else - gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) - | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) - | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) - | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) - | polySelect - | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT)); -#endif - -#if defined(GPCRC_CTRL_POLYSEL_CRC16) - if (polySelect == GPCRC_CTRL_POLYSEL_CRC16) { -#else - if (polySelect == GPCRC_CTRL_POLYSEL_16) { -#endif - // Set the CRC polynomial value. - gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK; - } - - // Load the CRC initialization value to GPCRC_INIT. - gpcrc->INIT = init->initValue; -} - -/***************************************************************************//** - * @brief - * Reset GPCRC registers to the hardware reset state. - * - * @note - * The data registers are not reset by this function. - * - * @param[in] gpcrc - * A pointer to the GPCRC peripheral register block. - ******************************************************************************/ -void GPCRC_Reset(GPCRC_TypeDef * gpcrc) -{ - gpcrc->CTRL = _GPCRC_CTRL_RESETVALUE; - gpcrc->POLY = _GPCRC_POLY_RESETVALUE; - gpcrc->INIT = _GPCRC_INIT_RESETVALUE; -} - -/** @} (end addtogroup gpcrc) */ - -#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief General Purpose Cyclic Redundancy Check (GPCRC) API. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_common.h" +#include "em_gpcrc.h" +#include "sl_assert.h" + +#if defined(GPCRC_PRESENT) && (GPCRC_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpcrc + * @{ + ******************************************************************************/ + +/******************************************************************************* + *************************** GLOBAL FUNCTIONS ****************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize the General Purpose Cyclic Redundancy Check (GPCRC) module. + * + * @details + * Use this function to configure the operational parameters of the GPCRC, + * such as the polynomial to use and how the input should be preprocessed + * before entering the CRC calculation. + * + * @note + * This function will not copy the initialization value to the data register + * to prepare for a new CRC calculation. Either call + * @ref GPCRC_Start before each calculation or by use the + * autoInit functionality. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the GPCRC. + ******************************************************************************/ +void GPCRC_Init(GPCRC_TypeDef * gpcrc, const GPCRC_Init_TypeDef * init) +{ + uint32_t polySelect; + uint32_t revPoly = 0; + + if (init->crcPoly == 0x04C11DB7) { + polySelect = GPCRC_CTRL_POLYSEL_CRC32; + } else { + // If not using the fixed CRC-32 polynomial, use 16-bit. + EFM_ASSERT((init->crcPoly & 0xFFFF0000UL) == 0U); +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + polySelect = GPCRC_CTRL_POLYSEL_CRC16; +#else + polySelect = GPCRC_CTRL_POLYSEL_16; +#endif + revPoly = SL_RBIT16(init->crcPoly); + } + +#if defined(GPCRC_EN_EN) + if (init->enable) { + gpcrc->EN_SET = GPCRC_EN_EN; + } else { + gpcrc->EN_CLR = GPCRC_EN_EN; + } + + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect); +#else + gpcrc->CTRL = (((uint32_t)init->autoInit << _GPCRC_CTRL_AUTOINIT_SHIFT) + | ((uint32_t)init->reverseByteOrder << _GPCRC_CTRL_BYTEREVERSE_SHIFT) + | ((uint32_t)init->reverseBits << _GPCRC_CTRL_BITREVERSE_SHIFT) + | ((uint32_t)init->enableByteMode << _GPCRC_CTRL_BYTEMODE_SHIFT) + | polySelect + | ((uint32_t)init->enable << _GPCRC_CTRL_EN_SHIFT)); +#endif + +#if defined(GPCRC_CTRL_POLYSEL_CRC16) + if (polySelect == GPCRC_CTRL_POLYSEL_CRC16) { +#else + if (polySelect == GPCRC_CTRL_POLYSEL_16) { +#endif + // Set the CRC polynomial value. + gpcrc->POLY = revPoly & _GPCRC_POLY_POLY_MASK; + } + + // Load the CRC initialization value to GPCRC_INIT. + gpcrc->INIT = init->initValue; +} + +/***************************************************************************//** + * @brief + * Reset GPCRC registers to the hardware reset state. + * + * @note + * The data registers are not reset by this function. + * + * @param[in] gpcrc + * A pointer to the GPCRC peripheral register block. + ******************************************************************************/ +void GPCRC_Reset(GPCRC_TypeDef * gpcrc) +{ + gpcrc->CTRL = _GPCRC_CTRL_RESETVALUE; + gpcrc->POLY = _GPCRC_POLY_RESETVALUE; + gpcrc->INIT = _GPCRC_INIT_RESETVALUE; +} + +/** @} (end addtogroup gpcrc) */ + +#endif /* defined(GPCRC_COUNT) && (GPCRC_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c index 9c4ddf4..13704e0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_gpio.c @@ -1,452 +1,452 @@ -/***************************************************************************//** - * @file - * @brief General Purpose IO (GPIO) peripheral API - * devices. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_gpio.h" - -#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) - -/***************************************************************************//** - * @addtogroup gpio GPIO - General Purpose Input/Output - * @brief General Purpose Input/Output (GPIO) API - * @details - * This module contains functions to control the GPIO peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration - * and direct pin manipulation and sensing as well as routing for peripheral - * pin connections. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the pin typically usable in assert statements. */ -#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) -#define GPIO_STRENGTH_VALID(strength) (!((strength) \ - & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ - | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Sets the pin location of the debug pins (Serial Wire interface). - * - * @note - * Changing the pins used for debugging uncontrolled, may result in a lockout. - * - * @param[in] location - * The debug pin location to use (0-3). - ******************************************************************************/ -void GPIO_DbgLocationSet(unsigned int location) -{ -#if defined (_GPIO_ROUTE_SWLOCATION_MASK) - EFM_ASSERT(location < AFCHANLOC_MAX); - - GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) - | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); -#elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) - EFM_ASSERT(location < AFCHANLOC_MAX); - - GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) - | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); -#else - (void)location; -#endif -} - -#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) -/***************************************************************************//** - * @brief - * Sets drive mode for a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] mode - * Drive mode to use for the port. - ******************************************************************************/ -void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) -{ - EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); - - GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) - | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); -} -#endif - -#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) -/***************************************************************************//** - * @brief - * Sets the drive strength for a GPIO port. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] strength - * The drive strength to use for the port. - ******************************************************************************/ -void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, - GPIO_DriveStrength_TypeDef strength) -{ - EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); - BUS_RegMaskedWrite(&GPIO->P[port].CTRL, - _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, - strength); -} -#endif - -/***************************************************************************//** - * @brief - * Configure the GPIO external pin interrupt. - * - * @details - * It is recommended to disable interrupts before configuring the GPIO pin interrupt. - * See @ref GPIO_IntDisable() for more information. - * - * The GPIO interrupt handler must be in place before enabling the - * interrupt. - * - * Notice that any pending interrupt for the selected interrupt is cleared - * by this function. - * - * @note - * On series 0 devices, the pin number parameter is not used. The - * pin number used on these devices is hardwired to the interrupt with the - * same number. @n - * On series 1 devices, the pin number can be selected freely within a group. - * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin - * number within the interrupt groups are: - * 0: pins 0-3 (interrupt number 0-3) - * 1: pins 4-7 (interrupt number 4-7) - * 2: pins 8-11 (interrupt number 8-11) - * 3: pins 12-15 (interrupt number 12-15) - * - * @param[in] port - * The port to associate with the @p pin. - * - * @param[in] pin - * The pin number on the port. - * - * @param[in] intNo - * The interrupt number to trigger. - * - * @param[in] risingEdge - * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. - * - * @param[in] fallingEdge - * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. - * - * @param[in] enable - * Set to true if the interrupt will be enabled after the configuration is complete. - * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). - ******************************************************************************/ -void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - unsigned int intNo, - bool risingEdge, - bool fallingEdge, - bool enable) -{ -#if defined (_GPIO_EXTIPSELH_MASK) - uint32_t tmp = 0; -#endif -#if !defined(_GPIO_EXTIPINSELL_MASK) - (void)pin; -#endif - - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); -#if defined(_GPIO_EXTIPINSELL_MASK) - EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); -#endif - - /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls - * pins 8-15 of the interrupt configuration. */ - if (intNo < 8) { - BUS_RegMaskedWrite(&GPIO->EXTIPSELL, - _GPIO_EXTIPSELL_EXTIPSEL0_MASK - << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), - (uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); - } else { -#if defined(_GPIO_EXTIPSELH_MASK) - tmp = intNo - 8; -#if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPSELH, - _GPIO_EXTIPSELH_EXTIPSEL0_MASK - << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), - (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); -#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPSELH, - _GPIO_EXTIPSELH_EXTIPSEL8_MASK - << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), - (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); -#else -#error Invalid GPIO_EXTIPINSELH bit fields -#endif -#endif /* #if defined(_GPIO_EXTIPSELH_MASK) */ - } - -#if defined(_GPIO_EXTIPINSELL_MASK) - - /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls - * interrupt 8-15 of the interrupt/pin number mapping. */ - if (intNo < 8) { - BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, - _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK - << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) - << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); - } else { -#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, - _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK - << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) - << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); -#endif -#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) - BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, - _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK - << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), - (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) - << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); -#endif - } -#endif - - /* Enable/disable the rising edge interrupt. */ - BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); - - /* Enable/disable the falling edge interrupt. */ - BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); - - /* Clear any pending interrupt. */ - GPIO_IntClear(1 << intNo); - - /* Finally enable/disable interrupt. */ - BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); -} - -#if _SILICON_LABS_32B_SERIES > 0 -/***************************************************************************//** - * @brief - * Configure EM4WU pins as external level-sensitive interrupts. - * - * @details - * It is recommended to disable interrupts before configuring the GPIO pin interrupt. - * See @ref GPIO_IntDisable() for more information. - * - * The GPIO interrupt handler must be in place before enabling the - * interrupt. - * - * Notice that any pending interrupt for the selected interrupt is cleared - * by this function. - * - * @note - * The selected port/pin must be mapped to an existant EM4WU interrupt. - * Each EM4WU signal is connected to a fixed pin. - * Refer to the Alternate Function Table in the device Datasheet for the - * location of each EM4WU signal. For example, on xG22 device, the interrupt - * of EM4WU6 is fixed to pin PC00. - * - * @param[in] port - * The port to associate with the @p pin. - * - * @param[in] pin - * The pin number on the port. - * - * @param[in] intNo - * The EM4WU interrupt number to trigger. - * - * @param[in] polarity - * true = Active high level-sensitive interrupt. - * false = Active low level-sensitive interrupt. - * - * @param[in] enable - * Set to true if the interrupt will be enabled after the configuration is complete. - * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). - ******************************************************************************/ -void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, - unsigned int pin, - uint32_t intNo, - bool polarity, - bool enable) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - // GPIO pin mode set. - GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity); - - // Enable EM4WU function and set polarity - uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); - uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); - - GPIO_EM4EnablePinWakeup(pinmask, polarityMask); - - // Enable EM4WU interrupt -#if defined(_SILICON_LABS_32B_SERIES_1) - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); -#else - BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Set the mode for a GPIO pin. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number in the port. - * - * @param[in] mode - * The desired pin mode. - * - * @param[in] out - * A value to set for the pin in the DOUT register. The DOUT setting is important for - * some input mode configurations to determine the pull-up/down direction. - ******************************************************************************/ -void GPIO_PinModeSet(GPIO_Port_TypeDef port, - unsigned int pin, - GPIO_Mode_TypeDef mode, - unsigned int out) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - /* If disabling a pin, do not modify DOUT to reduce the chance of */ - /* a glitch/spike (may not be sufficient precaution in all use cases). */ - if (mode != gpioModeDisabled) { - if (out) { - GPIO_PinOutSet(port, pin); - } else { - GPIO_PinOutClear(port, pin); - } - } - - /* There are two registers controlling the pins for each port. The MODEL - * register controls pins 0-7 and MODEH controls pins 8-15. */ - if (pin < 8) { - // Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C) - // Compiler assigned 8 bits for enum. Same thing for other branch. - BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); - } else { - BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4)); - } - - if (mode == gpioModeDisabled) { - if (out) { - GPIO_PinOutSet(port, pin); - } else { - GPIO_PinOutClear(port, pin); - } - } -} - -/***************************************************************************//** - * @brief - * Get the mode for a GPIO pin. - * - * @param[in] port - * The GPIO port to access. - * - * @param[in] pin - * The pin number in the port. - * - * @return - * The pin mode. - ******************************************************************************/ -GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, - unsigned int pin) -{ - EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); - - if (pin < 8) { - return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); - } else { - return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); - } -} - -#if defined(_GPIO_EM4WUEN_MASK) -/**************************************************************************//** - * @brief - * Enable GPIO pin wake-up from EM4. When the function exits, - * EM4 mode can be safely entered. - * - * @note - * It is assumed that the GPIO pin modes are set correctly. - * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. - * - * @param[in] pinmask - * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. - * See Reference Manuals for a pinmask to the GPIO port/pin mapping. - * @param[in] polaritymask - * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. - * See Reference Manuals for pinmask-to-GPIO port/pin mapping. - *****************************************************************************/ -void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) -{ - EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); - -#if defined(_GPIO_EM4WUPOL_MASK) - EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); - GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ - GPIO->EM4WUPOL |= pinmask & polaritymask; -#elif defined(_GPIO_EXTILEVEL_MASK) - EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); - GPIO->EXTILEVEL &= ~pinmask; - GPIO->EXTILEVEL |= pinmask & polaritymask; -#endif - GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ - - GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ - -#if defined(_GPIO_CMD_EM4WUCLR_MASK) - GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ -#else - GPIO_IntClear(pinmask); -#endif -} -#endif - -/** @} (end addtogroup gpio) */ - -#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief General Purpose IO (GPIO) peripheral API + * devices. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_gpio.h" + +#if defined(GPIO_COUNT) && (GPIO_COUNT > 0) + +/***************************************************************************//** + * @addtogroup gpio GPIO - General Purpose Input/Output + * @brief General Purpose Input/Output (GPIO) API + * @details + * This module contains functions to control the GPIO peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration + * and direct pin manipulation and sensing as well as routing for peripheral + * pin connections. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the pin typically usable in assert statements. */ +#define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3) +#define GPIO_STRENGTH_VALID(strength) (!((strength) \ + & ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \ + | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK))) +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Sets the pin location of the debug pins (Serial Wire interface). + * + * @note + * Changing the pins used for debugging uncontrolled, may result in a lockout. + * + * @param[in] location + * The debug pin location to use (0-3). + ******************************************************************************/ +void GPIO_DbgLocationSet(unsigned int location) +{ +#if defined (_GPIO_ROUTE_SWLOCATION_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) + | (location << _GPIO_ROUTE_SWLOCATION_SHIFT); +#elif defined (_GPIO_ROUTELOC0_SWVLOC_MASK) + EFM_ASSERT(location < AFCHANLOC_MAX); + + GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~_GPIO_ROUTELOC0_SWVLOC_MASK) + | (location << _GPIO_ROUTELOC0_SWVLOC_SHIFT); +#else + (void)location; +#endif +} + +#if defined (_GPIO_P_CTRL_DRIVEMODE_MASK) +/***************************************************************************//** + * @brief + * Sets drive mode for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] mode + * Drive mode to use for the port. + ******************************************************************************/ +void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode)); + + GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK)) + | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT); +} +#endif + +#if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK) +/***************************************************************************//** + * @brief + * Sets the drive strength for a GPIO port. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] strength + * The drive strength to use for the port. + ******************************************************************************/ +void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port, + GPIO_DriveStrength_TypeDef strength) +{ + EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGTH_VALID(strength)); + BUS_RegMaskedWrite(&GPIO->P[port].CTRL, + _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK, + strength); +} +#endif + +/***************************************************************************//** + * @brief + * Configure the GPIO external pin interrupt. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * On series 0 devices, the pin number parameter is not used. The + * pin number used on these devices is hardwired to the interrupt with the + * same number. @n + * On series 1 devices, the pin number can be selected freely within a group. + * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin + * number within the interrupt groups are: + * 0: pins 0-3 (interrupt number 0-3) + * 1: pins 4-7 (interrupt number 4-7) + * 2: pins 8-11 (interrupt number 8-11) + * 3: pins 12-15 (interrupt number 12-15) + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The interrupt number to trigger. + * + * @param[in] risingEdge + * Set to true if the interrupt will be enabled on the rising edge. Otherwise, false. + * + * @param[in] fallingEdge + * Set to true if the interrupt will be enabled on the falling edge. Otherwise, false. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_ExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + unsigned int intNo, + bool risingEdge, + bool fallingEdge, + bool enable) +{ +#if defined (_GPIO_EXTIPSELH_MASK) + uint32_t tmp = 0; +#endif +#if !defined(_GPIO_EXTIPINSELL_MASK) + (void)pin; +#endif + + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); +#if defined(_GPIO_EXTIPINSELL_MASK) + EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin)); +#endif + + /* The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls + * pins 8-15 of the interrupt configuration. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPSELL, + _GPIO_EXTIPSELL_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo), + (uint32_t)port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo)); + } else { +#if defined(_GPIO_EXTIPSELH_MASK) + tmp = intNo - 8; +#if defined(_GPIO_EXTIPSELH_EXTIPSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL0_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#elif defined(_GPIO_EXTIPSELH_EXTIPSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPSELH, + _GPIO_EXTIPSELH_EXTIPSEL8_MASK + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp), + (uint32_t)port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#else +#error Invalid GPIO_EXTIPINSELH bit fields +#endif +#endif /* #if defined(_GPIO_EXTIPSELH_MASK) */ + } + +#if defined(_GPIO_EXTIPINSELL_MASK) + + /* The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls + * interrupt 8-15 of the interrupt/pin number mapping. */ + if (intNo < 8) { + BUS_RegMaskedWrite(&GPIO->EXTIPINSELL, + _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo)); + } else { +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp)); +#endif +#if defined (_GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + BUS_RegMaskedWrite(&GPIO->EXTIPINSELH, + _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK + << (_GPIO_EXTIPINSELH_EXTIPINSEL1_SHIFT * tmp), + (uint32_t)((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL0_MASK) + << (_GPIO_EXTIPSELH_EXTIPSEL1_SHIFT * tmp)); +#endif + } +#endif + + /* Enable/disable the rising edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge); + + /* Enable/disable the falling edge interrupt. */ + BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge); + + /* Clear any pending interrupt. */ + GPIO_IntClear(1 << intNo); + + /* Finally enable/disable interrupt. */ + BUS_RegBitWrite(&(GPIO->IEN), intNo, enable); +} + +#if _SILICON_LABS_32B_SERIES > 0 +/***************************************************************************//** + * @brief + * Configure EM4WU pins as external level-sensitive interrupts. + * + * @details + * It is recommended to disable interrupts before configuring the GPIO pin interrupt. + * See @ref GPIO_IntDisable() for more information. + * + * The GPIO interrupt handler must be in place before enabling the + * interrupt. + * + * Notice that any pending interrupt for the selected interrupt is cleared + * by this function. + * + * @note + * The selected port/pin must be mapped to an existant EM4WU interrupt. + * Each EM4WU signal is connected to a fixed pin. + * Refer to the Alternate Function Table in the device Datasheet for the + * location of each EM4WU signal. For example, on xG22 device, the interrupt + * of EM4WU6 is fixed to pin PC00. + * + * @param[in] port + * The port to associate with the @p pin. + * + * @param[in] pin + * The pin number on the port. + * + * @param[in] intNo + * The EM4WU interrupt number to trigger. + * + * @param[in] polarity + * true = Active high level-sensitive interrupt. + * false = Active low level-sensitive interrupt. + * + * @param[in] enable + * Set to true if the interrupt will be enabled after the configuration is complete. + * False to leave disabled. See @ref GPIO_IntDisable() and @ref GPIO_IntEnable(). + ******************************************************************************/ +void GPIO_EM4WUExtIntConfig(GPIO_Port_TypeDef port, + unsigned int pin, + uint32_t intNo, + bool polarity, + bool enable) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + // GPIO pin mode set. + GPIO_PinModeSet(port, pin, gpioModeInputPullFilter, (unsigned int)!polarity); + + // Enable EM4WU function and set polarity + uint32_t polarityMask = (uint32_t)polarity << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + uint32_t pinmask = 1UL << (intNo + _GPIO_EM4WUEN_EM4WUEN_SHIFT); + + GPIO_EM4EnablePinWakeup(pinmask, polarityMask); + + // Enable EM4WU interrupt +#if defined(_SILICON_LABS_32B_SERIES_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WU_SHIFT, enable); +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN_SHIFT, enable); +#else + BUS_RegBitWrite(&(GPIO->IEN), intNo + _GPIO_IEN_EM4WUIEN0_SHIFT, enable); +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Set the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @param[in] mode + * The desired pin mode. + * + * @param[in] out + * A value to set for the pin in the DOUT register. The DOUT setting is important for + * some input mode configurations to determine the pull-up/down direction. + ******************************************************************************/ +void GPIO_PinModeSet(GPIO_Port_TypeDef port, + unsigned int pin, + GPIO_Mode_TypeDef mode, + unsigned int out) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + /* If disabling a pin, do not modify DOUT to reduce the chance of */ + /* a glitch/spike (may not be sufficient precaution in all use cases). */ + if (mode != gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } + + /* There are two registers controlling the pins for each port. The MODEL + * register controls pins 0-7 and MODEH controls pins 8-15. */ + if (pin < 8) { + // Cast parameter [mode] to 32 bits to fix C99 Undefined Behavior (see SEI CERT C INT34-C) + // Compiler assigned 8 bits for enum. Same thing for other branch. + BUS_RegMaskedWrite(&(GPIO->P[port].MODEL), 0xFu << (pin * 4), (uint32_t)mode << (pin * 4)); + } else { + BUS_RegMaskedWrite(&(GPIO->P[port].MODEH), 0xFu << ((pin - 8) * 4), (uint32_t)mode << ((pin - 8) * 4)); + } + + if (mode == gpioModeDisabled) { + if (out) { + GPIO_PinOutSet(port, pin); + } else { + GPIO_PinOutClear(port, pin); + } + } +} + +/***************************************************************************//** + * @brief + * Get the mode for a GPIO pin. + * + * @param[in] port + * The GPIO port to access. + * + * @param[in] pin + * The pin number in the port. + * + * @return + * The pin mode. + ******************************************************************************/ +GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port, + unsigned int pin) +{ + EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin)); + + if (pin < 8) { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF); + } else { + return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF); + } +} + +#if defined(_GPIO_EM4WUEN_MASK) +/**************************************************************************//** + * @brief + * Enable GPIO pin wake-up from EM4. When the function exits, + * EM4 mode can be safely entered. + * + * @note + * It is assumed that the GPIO pin modes are set correctly. + * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull. + * + * @param[in] pinmask + * A bitmask containing the bitwise logic OR of which GPIO pin(s) to enable. + * See Reference Manuals for a pinmask to the GPIO port/pin mapping. + * @param[in] polaritymask + * A bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity. + * See Reference Manuals for pinmask-to-GPIO port/pin mapping. + *****************************************************************************/ +void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask) +{ + EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0); + +#if defined(_GPIO_EM4WUPOL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0); + GPIO->EM4WUPOL &= ~pinmask; /* Set the wakeup polarity. */ + GPIO->EM4WUPOL |= pinmask & polaritymask; +#elif defined(_GPIO_EXTILEVEL_MASK) + EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0); + GPIO->EXTILEVEL &= ~pinmask; + GPIO->EXTILEVEL |= pinmask & polaritymask; +#endif + GPIO->EM4WUEN |= pinmask; /* Enable wakeup. */ + + GPIO_EM4SetPinRetention(true); /* Enable the pin retention. */ + +#if defined(_GPIO_CMD_EM4WUCLR_MASK) + GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear the wake-up logic. */ +#else + GPIO_IntClear(pinmask); +#endif +} +#endif + +/** @} (end addtogroup gpio) */ + +#endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c index dde3240..9f53b28 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_i2c.c @@ -1,940 +1,940 @@ -/***************************************************************************//** - * @file - * @brief Inter-integrated Circuit (I2C) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_i2c.h" -#if defined(I2C_COUNT) && (I2C_COUNT > 0) - -#include "em_cmu.h" -#include "em_bus.h" -#include "sl_assert.h" - - #include - -/***************************************************************************//** - * @addtogroup i2c I2C - Inter-Integrated Circuit - * @brief Inter-integrated Circuit (I2C) Peripheral API - * @details - * This module contains functions to control the I2C peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C - * buses with the lowest energy consumption possible. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of the I2C register block pointer reference for assert statements. */ -#if (I2C_COUNT == 1) -#define I2C_REF_VALID(ref) ((ref) == I2C0) -#elif (I2C_COUNT == 2) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) -#elif (I2C_COUNT == 3) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) -#elif (I2C_COUNT == 4) -#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2) || ((ref) == I2C3)) -#endif - -/** Error flags indicating that the I2C transfer has failed. */ -/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ -/* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ -/* RXUF is only likely to occur with the software if using a debugger peeking into */ -/* the RXDATA register. Therefore, those types of faults are ignored. */ -#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) -#define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) - -/* Maximum I2C transmission rate constant. */ -#if defined(_SILICON_LABS_32B_SERIES_0) -#if defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY) -#define I2C_CR_MAX 8 -#else -#define I2C_CR_MAX 4 -#endif -#elif defined(_SILICON_LABS_32B_SERIES_1) -#define I2C_CR_MAX 8 -#elif defined(_SILICON_LABS_32B_SERIES_2) -#define I2C_CR_MAX 8 -#else -#warning "Max I2C transmission rate constant is not defined" -#endif - -/** @endcond */ - -/******************************************************************************* - ******************************** ENUMS ************************************ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Master mode transfer states. */ -typedef enum { - i2cStateStartAddrSend, /**< Send start + (first part of) address. */ - i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ - i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ - i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ - i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ - i2cStateDataSend, /**< Send data. */ - i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ - i2cStateWFData, /**< Wait for data. */ - i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ - i2cStateDone /**< Transfer completed successfully. */ -} I2C_TransferState_TypeDef; - -/** @endcond */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Structure used to store state information on an ongoing master mode transfer. */ -typedef struct { - /** Current state. */ - I2C_TransferState_TypeDef state; - - /** Result return code. */ - I2C_TransferReturn_TypeDef result; - - /** Offset in the current sequence buffer. */ - uint16_t offset; - - /* Index to the current sequence buffer in use. */ - uint8_t bufIndx; - - /** Reference to the I2C transfer sequence definition provided by the user. */ - I2C_TransferSeq_TypeDef *seq; -} I2C_Transfer_TypeDef; - -/** @endcond */ - -/******************************************************************************* - ***************************** LOCAL DATA *******^************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** - * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined - * index (0x3) to reflect a default setting just in case. - */ -static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; - -/** A transfer state information for an ongoing master mode transfer. */ -static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Empty received data buffer. - ******************************************************************************/ -static void flushRx(I2C_TypeDef *i2c) -{ - while (i2c->STATUS & I2C_STATUS_RXDATAV) { - i2c->RXDATA; - } - -#if defined(_SILICON_LABS_32B_SERIES_2) - /* SW needs to clear RXDATAV IF on Series 2 devices. - Flag is kept high by HW if buffer is not empty. */ - I2C_IntClear(i2c, I2C_IF_RXDATAV); -#endif -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the current configured I2C bus frequency. - * - * @details - * This frequency is only relevant when acting as master. - * - * @note - * The actual frequency is a real number, this function returns a rounded - * down (truncated) integer value. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @return - * The current I2C frequency in Hz. - ******************************************************************************/ -uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) -{ - uint32_t freqHfper = 0; - uint32_t n; - - /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) - * For more details, see the reference manual - * I2C Clock Generation chapter. */ - if (i2c == I2C0) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); -#if defined(I2C1) - } else if (i2c == I2C1) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); -#endif -#if defined(I2C2) - } else if (i2c == I2C2) { - freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); -#endif - } else { - EFM_ASSERT(false); - } - - /* n = Nlow + Nhigh */ - n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) - >> _I2C_CTRL_CLHR_SHIFT]; - return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); -} - -/***************************************************************************//** - * @brief - * Set the I2C bus frequency. - * - * @details - * The bus frequency is only relevant when acting as master. The bus - * frequency should not be set higher than the maximum frequency accepted by the - * slowest device on the bus. - * - * Notice that, due to asymmetric requirements on low and high I2C clock - * cycles in the I2C specification, the maximum frequency allowed - * to comply with the specification may be somewhat lower than expected. - * - * See the reference manual, details on I2C clock generation, - * for maximum allowed theoretical frequencies for different modes. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] freqRef - * An I2C reference clock frequency in Hz that will be used. If set to 0, - * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual - * configured value has the consequence of reducing the real I2C frequency. - * - * @param[in] freqScl - * A bus frequency to set (bus speed may be lower due to integer - * prescaling). Safe (according to the I2C specification) maximum frequencies for - * standard fast and fast+ modes are available using I2C_FREQ_ defines. - * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) - * The slowest slave device on a bus must always be considered. - * - * @param[in] i2cMode - * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, - * make sure all devices on the bus support the specified mode. Using a - * non-standard ratio is useful to achieve a higher bus clock in fast and - * fast+ modes. - ******************************************************************************/ -void I2C_BusFreqSet(I2C_TypeDef *i2c, - uint32_t freqRef, - uint32_t freqScl, - I2C_ClockHLR_TypeDef i2cMode) -{ - uint32_t n, minFreq, denominator; - int32_t div; - - /* Avoid dividing by 0. */ - EFM_ASSERT(freqScl); - if (!freqScl) { - return; - } - - /* Ensure mode is valid */ - i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; - - /* Set the CLHR (clock low-to-high ratio). */ - i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; - BUS_RegMaskedWrite(&i2c->CTRL, - _I2C_CTRL_CLHR_MASK, - i2cMode << _I2C_CTRL_CLHR_SHIFT); - - if (freqRef == 0) { - if (i2c == I2C0) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C0); -#if defined(I2C1) - } else if (i2c == I2C1) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C1); -#endif -#if defined(I2C2) - } else if (i2c == I2C2) { - freqRef = CMU_ClockFreqGet(cmuClock_I2C2); -#endif - } else { - EFM_ASSERT(false); - } - } - - /* Check the minumum HF peripheral clock. */ - minFreq = UINT_MAX; - if (i2c->CTRL & I2C_CTRL_SLAVE) { - switch (i2cMode) { - case i2cClockHLRStandard: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 4200000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 2000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 2000000; break; -#endif - case i2cClockHLRAsymetric: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 11000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 5000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 5000000; break; -#endif - case i2cClockHLRFast: -#if defined(_SILICON_LABS_32B_SERIES_0) - minFreq = 24400000; break; -#elif defined(_SILICON_LABS_32B_SERIES_1) - minFreq = 14000000; break; -#elif defined(_SILICON_LABS_32B_SERIES_2) - minFreq = 14000000; break; -#endif - default: - /* MISRA requires the default case. */ - break; - } - } else { - /* For master mode, platform 1 and 2 share the same - minimum frequencies. */ - switch (i2cMode) { - case i2cClockHLRStandard: - minFreq = 2000000; break; - case i2cClockHLRAsymetric: - minFreq = 9000000; break; - case i2cClockHLRFast: - minFreq = 20000000; break; - default: - /* MISRA requires default case */ - break; - } - } - - /* Frequency most be larger-than. */ - EFM_ASSERT(freqRef > minFreq); - - /* SCL frequency is given by: - * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) - * - * Therefore, - * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 - * - * For more details, see the reference manual - * I2C Clock Generation chapter. */ - - /* n = Nlow + Nhigh */ - n = (uint32_t)i2cNSum[i2cMode]; - denominator = n * freqScl; - - /* Explicitly ensure denominator is never zero. */ - if (denominator == 0) { - EFM_ASSERT(0); - return; - } - /* Perform integer division so that div is rounded up. */ - div = (int32_t)(((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) - / denominator) - 1); - EFM_ASSERT(div >= 0); - EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); - - /* The clock divisor must be at least 1 in slave mode according to the reference */ - /* manual (in which case there is normally no need to set the bus frequency). */ - if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { - div = 1; - } - i2c->CLKDIV = (uint32_t)div; -} - -/***************************************************************************//** - * @brief - * Enable/disable I2C. - * - * @note - * After enabling the I2C (from being disabled), the I2C is in BUSY state. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] enable - * True to enable counting, false to disable. - ******************************************************************************/ -void I2C_Enable(I2C_TypeDef *i2c, bool enable) -{ - EFM_ASSERT(I2C_REF_VALID(i2c)); - -#if defined (_I2C_EN_MASK) - BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); -#else - BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); -#endif -} - -/***************************************************************************//** - * @brief - * Initialize I2C. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] init - * A pointer to the I2C initialization structure. - ******************************************************************************/ -void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) -{ - EFM_ASSERT(I2C_REF_VALID(i2c)); - - i2c->IEN = 0; - I2C_IntClear(i2c, _I2C_IF_MASK); - - /* Set SLAVE select mode. */ - BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); - - I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); - - I2C_Enable(i2c, init->enable); -} - -/***************************************************************************//** - * @brief - * Reset I2C to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * centralized setup of this feature. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - ******************************************************************************/ -void I2C_Reset(I2C_TypeDef *i2c) -{ - // Cancel ongoing operations and clear TX buffer - i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; - i2c->CTRL = _I2C_CTRL_RESETVALUE; - i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; - i2c->SADDR = _I2C_SADDR_RESETVALUE; - i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; - i2c->IEN = _I2C_IEN_RESETVALUE; -#if defined (_I2C_EN_EN_MASK) - i2c->EN = _I2C_EN_RESETVALUE; -#endif - - // Empty received data buffer - flushRx(i2c); - I2C_IntClear(i2c, _I2C_IF_MASK); - /* Do not reset the route register; setting should be done independently. */ -} - -// ***************************************************************************** -/// @brief -/// Continue an initiated I2C transfer (single master mode only). -/// -/// @details -/// This function is used repeatedly after a I2C_TransferInit() to -/// complete a transfer. It may be used in polled mode as the below example -/// shows: -/// @code{.c} -/// I2C_TransferReturn_TypeDef ret; -/// -/// // Do a polled transfer -/// ret = I2C_TransferInit(I2C0, seq); -/// while (ret == i2cTransferInProgress) -/// { -/// ret = I2C_Transfer(I2C0); -/// } -/// @endcode -/// It may also be used in interrupt driven mode, where this function is invoked -/// from the interrupt handler. Notice that, if used in interrupt mode, NVIC -/// interrupts must be configured and enabled for the I2C bus used. I2C -/// peripheral specific interrupts are managed by this software. -/// -/// @note -/// Only single master mode is supported. -/// -/// @param[in] i2c -/// A pointer to the I2C peripheral register block. -/// -/// @return -/// Returns status for an ongoing transfer. -/// @li #i2cTransferInProgress - indicates that transfer not finished. -/// @li #i2cTransferDone - transfer completed successfully. -/// @li otherwise some sort of error has occurred. -/// -// ***************************************************************************** -I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) -{ - uint32_t tmp; - uint32_t pending; - I2C_Transfer_TypeDef *transfer; - I2C_TransferSeq_TypeDef *seq; - bool finished = false; - - EFM_ASSERT(I2C_REF_VALID(i2c)); - - /* Support up to 2 I2C buses. */ - if (i2c == I2C0) { - transfer = i2cTransfer; - } -#if (I2C_COUNT > 1) - else if (i2c == I2C1) { - transfer = i2cTransfer + 1; - } -#endif -#if (I2C_COUNT > 2) - else if (i2c == I2C2) { - transfer = i2cTransfer + 2; - } -#endif -#if (I2C_COUNT > 3) - else if (i2c == I2C3) { - transfer = i2cTransfer + 3; - } -#endif - else { - return i2cTransferUsageFault; - } - - seq = transfer->seq; - while (!finished) { - pending = i2c->IF; - - /* If some sort of fault, abort transfer. */ - if (pending & I2C_IF_ERRORS) { - if (pending & I2C_IF_ARBLOST) { - /* If an arbitration fault, indicates either a slave device */ - /* not responding as expected, or other master which is not */ - /* supported by this software. */ - transfer->result = i2cTransferArbLost; - } else if (pending & I2C_IF_BUSERR) { - /* A bus error indicates a misplaced start or stop, which should */ - /* not occur in master mode controlled by this software. */ - transfer->result = i2cTransferBusErr; - } - - /* Ifan error occurs, it is difficult to know */ - /* an exact cause and how to resolve. It will be up to a wrapper */ - /* to determine how to handle a fault/recovery if possible. */ - transfer->state = i2cStateDone; - break; - } - - switch (transfer->state) { - /***************************************************/ - /* Send the first start+address (first byte if 10 bit). */ - /***************************************************/ - case i2cStateStartAddrSend: - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; - - /* In 10 bit address mode, the address following the first */ - /* start always indicates write. */ - } else { - tmp = (uint32_t)(seq->addr) & 0xfe; - - if (seq->flags & I2C_FLAG_READ) { - /* Indicate read request */ - tmp |= 1; - } - } - - transfer->state = i2cStateAddrWFAckNack; - i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ - i2c->CMD = I2C_CMD_START; - finished = true; - break; - - /*******************************************************/ - /* Wait for ACK/NACK on the address (first byte if 10 bit). */ - /*******************************************************/ - case i2cStateAddrWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* If a 10 bit address, send the 2nd byte of the address. */ - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - transfer->state = i2cStateAddrWF2ndAckNack; - i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; - } else { - /* Determine whether receiving or sending data. */ - if (seq->flags & I2C_FLAG_READ) { - transfer->state = i2cStateWFData; - if (seq->buf[transfer->bufIndx].len == 1) { - i2c->CMD = I2C_CMD_NACK; - } - } else { - transfer->state = i2cStateDataSend; - continue; - } - } - } - finished = true; - break; - - /******************************************************/ - /* Wait for ACK/NACK on the second byte of a 10 bit address. */ - /******************************************************/ - case i2cStateAddrWF2ndAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* If using a plain read sequence with a 10 bit address, switch to send */ - /* a repeated start. */ - if (seq->flags & I2C_FLAG_READ) { - transfer->state = i2cStateRStartAddrSend; - } - /* Otherwise, expected to write 0 or more bytes. */ - else { - transfer->state = i2cStateDataSend; - } - continue; - } - finished = true; - break; - - /*******************************/ - /* Send a repeated start+address */ - /*******************************/ - case i2cStateRStartAddrSend: - if (seq->flags & I2C_FLAG_10BIT_ADDR) { - tmp = (uint32_t)((seq->addr >> 8) & 0x06) | 0xf0; - } else { - tmp = (uint32_t)(seq->addr & 0xfe); - } - - /* If this is a write+read combined sequence, read is about to start. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - /* Indicate a read request. */ - tmp |= 1; - /* If reading only one byte, prepare the NACK now before START command. */ - if (seq->buf[transfer->bufIndx].len == 1) { - i2c->CMD = I2C_CMD_NACK; - } - } - - transfer->state = i2cStateRAddrWFAckNack; - /* The START command has to be written first since repeated start. Otherwise, */ - /* data would be sent first. */ - i2c->CMD = I2C_CMD_START; - i2c->TXDATA = tmp; - - finished = true; - break; - - /**********************************************************************/ - /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ - /**********************************************************************/ - case i2cStateRAddrWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - - /* Determine whether receiving or sending data. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - transfer->state = i2cStateWFData; - } else { - transfer->state = i2cStateDataSend; - continue; - } - } - finished = true; - break; - - /*****************************/ - /* Send a data byte to the slave */ - /*****************************/ - case i2cStateDataSend: - /* Reached end of data buffer. */ - if (transfer->offset >= seq->buf[transfer->bufIndx].len) { - /* Move to the next message part. */ - transfer->offset = 0; - transfer->bufIndx++; - - /* Send a repeated start when switching to read mode on the 2nd buffer. */ - if (seq->flags & I2C_FLAG_WRITE_READ) { - transfer->state = i2cStateRStartAddrSend; - continue; - } - - /* Only writing from one buffer or finished both buffers. */ - if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - finished = true; - break; - } - - /* Reprocess in case the next buffer is empty. */ - continue; - } - - /* Send byte. */ - i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); - transfer->state = i2cStateDataWFAckNack; - finished = true; - break; - - /*********************************************************/ - /* Wait for ACK/NACK from the slave after sending data to it. */ - /*********************************************************/ - case i2cStateDataWFAckNack: - if (pending & I2C_IF_NACK) { - I2C_IntClear(i2c, I2C_IF_NACK); - transfer->result = i2cTransferNack; - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else if (pending & I2C_IF_ACK) { - I2C_IntClear(i2c, I2C_IF_ACK); - transfer->state = i2cStateDataSend; - continue; - } - finished = true; - break; - - /****************************/ - /* Wait for data from slave */ - /****************************/ - case i2cStateWFData: - if (pending & I2C_IF_RXDATAV) { - uint8_t data; - unsigned int rxLen = seq->buf[transfer->bufIndx].len; - - /* Must read out data not to block further progress. */ - data = (uint8_t)(i2c->RXDATA); - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)) - // Errata I2C_E303. I2C Fails to Indicate New Incoming Data. - uint32_t status = i2c->STATUS; - // look for invalid RXDATAV = 0 and RXFULL = 1 condition - if (((status & I2C_IF_RXDATAV) == 0) & ((status & I2C_IF_RXFULL) != 0)) { - // Performing a dummy read of the RXFIFO (I2C_RXDATA). - // This restores the expected RXDATAV = 1 and RXFULL = 0 condition. - (void)i2c->RXDATA; - // The dummy read will also set the RXUFIF flag bit, which should be ignored and cleared. - I2C_IntClear(i2c, I2C_IF_RXUF); - } -#endif - - /* SW needs to clear RXDATAV IF on Series 2 devices. - Flag is kept high by HW if buffer is not empty. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - I2C_IntClear(i2c, I2C_IF_RXDATAV); -#endif - - /* Make sure that there is no storing beyond the end of the buffer (just in case). */ - if (transfer->offset < rxLen) { - seq->buf[transfer->bufIndx].data[transfer->offset++] = data; - } - - /* If all requested data is read, the sequence should end. */ - if (transfer->offset >= rxLen) { - transfer->state = i2cStateWFStopSent; - i2c->CMD = I2C_CMD_STOP; - } else { - /* Send ACK and wait for the next byte. */ - i2c->CMD = I2C_CMD_ACK; - - if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { - /* If receiving more than one byte and this is the next - to last byte, transmit the NACK now before receiving - the last byte. */ - i2c->CMD = I2C_CMD_NACK; - } - } - } - finished = true; - break; - - /***********************************/ - /* Wait for STOP to have been sent */ - /***********************************/ - case i2cStateWFStopSent: - if (pending & I2C_IF_MSTOP) { - I2C_IntClear(i2c, I2C_IF_MSTOP); - transfer->state = i2cStateDone; - } - finished = true; - break; - - /******************************/ - /* An unexpected state, software fault */ - /******************************/ - default: - transfer->result = i2cTransferSwFault; - transfer->state = i2cStateDone; - finished = true; - break; - } - } - - if (transfer->state == i2cStateDone) { - /* Disable interrupt sources when done. */ - i2c->IEN = 0; - - /* Update the result unless a fault has already occurred. */ - if (transfer->result == i2cTransferInProgress) { - transfer->result = i2cTransferDone; - } - } - /* Until transfer is done, keep returning i2cTransferInProgress. */ - else { - return i2cTransferInProgress; - } - - return transfer->result; -} - -/***************************************************************************//** - * @brief - * Prepare and start an I2C transfer (single master mode only). - * - * @details - * This function must be invoked to start an I2C transfer - * sequence. To complete the transfer, I2C_Transfer() must - * be used either in polled mode or by adding a small driver wrapper using - * interrupts. - * - * @note - * Only single master mode is supported. - * - * @param[in] i2c - * A pointer to the I2C peripheral register block. - * - * @param[in] seq - * A pointer to the sequence structure defining the I2C transfer to take place. The - * referenced structure must exist until the transfer has fully completed. - * - * @return - * Returns the status for an ongoing transfer: - * @li #i2cTransferInProgress - indicates that the transfer is not finished. - * @li Otherwise, an error has occurred. - ******************************************************************************/ -I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, - I2C_TransferSeq_TypeDef *seq) -{ - I2C_Transfer_TypeDef *transfer; - - EFM_ASSERT(I2C_REF_VALID(i2c)); - EFM_ASSERT(seq); - - /* Support up to 2 I2C buses. */ - if (i2c == I2C0) { - transfer = i2cTransfer; - } -#if (I2C_COUNT > 1) - else if (i2c == I2C1) { - transfer = i2cTransfer + 1; - } -#endif -#if (I2C_COUNT > 2) - else if (i2c == I2C2) { - transfer = i2cTransfer + 2; - } -#endif -#if (I2C_COUNT > 3) - else if (i2c == I2C3) { - transfer = i2cTransfer + 3; - } -#endif - else { - return i2cTransferUsageFault; - } - - /* Check if in a busy state. Since this software assumes a single master, */ - /* issue an abort. The BUSY state is normal after a reset. */ - if (i2c->STATE & I2C_STATE_BUSY) { - i2c->CMD = I2C_CMD_ABORT; - } - - /* Do not try to read 0 bytes. It is not */ - /* possible according to the I2C spec, since the slave will always start */ - /* sending the first byte ACK on an address. The read operation can */ - /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ - if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) - || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) - ) { - return i2cTransferUsageFault; - } - - /* Prepare for a transfer. */ - transfer->state = i2cStateStartAddrSend; - transfer->result = i2cTransferInProgress; - transfer->offset = 0; - transfer->bufIndx = 0; - transfer->seq = seq; - - /* Ensure buffers are empty. */ - i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; - flushRx(i2c); - - /* Clear all pending interrupts prior to starting a transfer. */ - I2C_IntClear(i2c, _I2C_IF_MASK); - - /* Enable relevant interrupts. */ - /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ - /* that is left for an additional driver wrapper. */ - i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP - | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; - - /* Start a transfer. */ - return I2C_Transfer(i2c); -} - -/** @} (end addtogroup i2c) */ -#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Inter-integrated Circuit (I2C) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_i2c.h" +#if defined(I2C_COUNT) && (I2C_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" + + #include + +/***************************************************************************//** + * @addtogroup i2c I2C - Inter-Integrated Circuit + * @brief Inter-integrated Circuit (I2C) Peripheral API + * @details + * This module contains functions to control the I2C peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C + * buses with the lowest energy consumption possible. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of the I2C register block pointer reference for assert statements. */ +#if (I2C_COUNT == 1) +#define I2C_REF_VALID(ref) ((ref) == I2C0) +#elif (I2C_COUNT == 2) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1)) +#elif (I2C_COUNT == 3) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2)) +#elif (I2C_COUNT == 4) +#define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2) || ((ref) == I2C3)) +#endif + +/** Error flags indicating that the I2C transfer has failed. */ +/* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */ +/* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */ +/* RXUF is only likely to occur with the software if using a debugger peeking into */ +/* the RXDATA register. Therefore, those types of faults are ignored. */ +#define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST) +#define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST) + +/* Maximum I2C transmission rate constant. */ +#if defined(_SILICON_LABS_32B_SERIES_0) +#if defined(_EFM32_HAPPY_FAMILY) || defined(_EFM32_ZERO_FAMILY) +#define I2C_CR_MAX 8 +#else +#define I2C_CR_MAX 4 +#endif +#elif defined(_SILICON_LABS_32B_SERIES_1) +#define I2C_CR_MAX 8 +#elif defined(_SILICON_LABS_32B_SERIES_2) +#define I2C_CR_MAX 8 +#else +#warning "Max I2C transmission rate constant is not defined" +#endif + +/** @endcond */ + +/******************************************************************************* + ******************************** ENUMS ************************************ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Master mode transfer states. */ +typedef enum { + i2cStateStartAddrSend, /**< Send start + (first part of) address. */ + i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */ + i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */ + i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */ + i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */ + i2cStateDataSend, /**< Send data. */ + i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */ + i2cStateWFData, /**< Wait for data. */ + i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */ + i2cStateDone /**< Transfer completed successfully. */ +} I2C_TransferState_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Structure used to store state information on an ongoing master mode transfer. */ +typedef struct { + /** Current state. */ + I2C_TransferState_TypeDef state; + + /** Result return code. */ + I2C_TransferReturn_TypeDef result; + + /** Offset in the current sequence buffer. */ + uint16_t offset; + + /* Index to the current sequence buffer in use. */ + uint8_t bufIndx; + + /** Reference to the I2C transfer sequence definition provided by the user. */ + I2C_TransferSeq_TypeDef *seq; +} I2C_Transfer_TypeDef; + +/** @endcond */ + +/******************************************************************************* + ***************************** LOCAL DATA *******^************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** + * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined + * index (0x3) to reflect a default setting just in case. + */ +static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 }; + +/** A transfer state information for an ongoing master mode transfer. */ +static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT]; + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Empty received data buffer. + ******************************************************************************/ +static void flushRx(I2C_TypeDef *i2c) +{ + while (i2c->STATUS & I2C_STATUS_RXDATAV) { + i2c->RXDATA; + } + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the current configured I2C bus frequency. + * + * @details + * This frequency is only relevant when acting as master. + * + * @note + * The actual frequency is a real number, this function returns a rounded + * down (truncated) integer value. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @return + * The current I2C frequency in Hz. + ******************************************************************************/ +uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c) +{ + uint32_t freqHfper = 0; + uint32_t n; + + /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX) + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + if (i2c == I2C0) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqHfper = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK) + >> _I2C_CTRL_CLHR_SHIFT]; + return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX); +} + +/***************************************************************************//** + * @brief + * Set the I2C bus frequency. + * + * @details + * The bus frequency is only relevant when acting as master. The bus + * frequency should not be set higher than the maximum frequency accepted by the + * slowest device on the bus. + * + * Notice that, due to asymmetric requirements on low and high I2C clock + * cycles in the I2C specification, the maximum frequency allowed + * to comply with the specification may be somewhat lower than expected. + * + * See the reference manual, details on I2C clock generation, + * for maximum allowed theoretical frequencies for different modes. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] freqRef + * An I2C reference clock frequency in Hz that will be used. If set to 0, + * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual + * configured value has the consequence of reducing the real I2C frequency. + * + * @param[in] freqScl + * A bus frequency to set (bus speed may be lower due to integer + * prescaling). Safe (according to the I2C specification) maximum frequencies for + * standard fast and fast+ modes are available using I2C_FREQ_ defines. + * (Using I2C_FREQ_ defines requires corresponding setting of @p type.) + * The slowest slave device on a bus must always be considered. + * + * @param[in] i2cMode + * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, + * make sure all devices on the bus support the specified mode. Using a + * non-standard ratio is useful to achieve a higher bus clock in fast and + * fast+ modes. + ******************************************************************************/ +void I2C_BusFreqSet(I2C_TypeDef *i2c, + uint32_t freqRef, + uint32_t freqScl, + I2C_ClockHLR_TypeDef i2cMode) +{ + uint32_t n, minFreq, denominator; + int32_t div; + + /* Avoid dividing by 0. */ + EFM_ASSERT(freqScl); + if (!freqScl) { + return; + } + + /* Ensure mode is valid */ + i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT; + + /* Set the CLHR (clock low-to-high ratio). */ + i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK; + BUS_RegMaskedWrite(&i2c->CTRL, + _I2C_CTRL_CLHR_MASK, + i2cMode << _I2C_CTRL_CLHR_SHIFT); + + if (freqRef == 0) { + if (i2c == I2C0) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C0); +#if defined(I2C1) + } else if (i2c == I2C1) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C1); +#endif +#if defined(I2C2) + } else if (i2c == I2C2) { + freqRef = CMU_ClockFreqGet(cmuClock_I2C2); +#endif + } else { + EFM_ASSERT(false); + } + } + + /* Check the minumum HF peripheral clock. */ + minFreq = UINT_MAX; + if (i2c->CTRL & I2C_CTRL_SLAVE) { + switch (i2cMode) { + case i2cClockHLRStandard: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 4200000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 2000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 2000000; break; +#endif + case i2cClockHLRAsymetric: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 11000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 5000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 5000000; break; +#endif + case i2cClockHLRFast: +#if defined(_SILICON_LABS_32B_SERIES_0) + minFreq = 24400000; break; +#elif defined(_SILICON_LABS_32B_SERIES_1) + minFreq = 14000000; break; +#elif defined(_SILICON_LABS_32B_SERIES_2) + minFreq = 14000000; break; +#endif + default: + /* MISRA requires the default case. */ + break; + } + } else { + /* For master mode, platform 1 and 2 share the same + minimum frequencies. */ + switch (i2cMode) { + case i2cClockHLRStandard: + minFreq = 2000000; break; + case i2cClockHLRAsymetric: + minFreq = 9000000; break; + case i2cClockHLRFast: + minFreq = 20000000; break; + default: + /* MISRA requires default case */ + break; + } + } + + /* Frequency most be larger-than. */ + EFM_ASSERT(freqRef > minFreq); + + /* SCL frequency is given by: + * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX) + * + * Therefore, + * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1 + * + * For more details, see the reference manual + * I2C Clock Generation chapter. */ + + /* n = Nlow + Nhigh */ + n = (uint32_t)i2cNSum[i2cMode]; + denominator = n * freqScl; + + /* Explicitly ensure denominator is never zero. */ + if (denominator == 0) { + EFM_ASSERT(0); + return; + } + /* Perform integer division so that div is rounded up. */ + div = (int32_t)(((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1) + / denominator) - 1); + EFM_ASSERT(div >= 0); + EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK); + + /* The clock divisor must be at least 1 in slave mode according to the reference */ + /* manual (in which case there is normally no need to set the bus frequency). */ + if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) { + div = 1; + } + i2c->CLKDIV = (uint32_t)div; +} + +/***************************************************************************//** + * @brief + * Enable/disable I2C. + * + * @note + * After enabling the I2C (from being disabled), the I2C is in BUSY state. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void I2C_Enable(I2C_TypeDef *i2c, bool enable) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + +#if defined (_I2C_EN_MASK) + BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable); +#else + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable); +#endif +} + +/***************************************************************************//** + * @brief + * Initialize I2C. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] init + * A pointer to the I2C initialization structure. + ******************************************************************************/ +void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init) +{ + EFM_ASSERT(I2C_REF_VALID(i2c)); + + i2c->IEN = 0; + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Set SLAVE select mode. */ + BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1); + + I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr); + + I2C_Enable(i2c, init->enable); +} + +/***************************************************************************//** + * @brief + * Reset I2C to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * centralized setup of this feature. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + ******************************************************************************/ +void I2C_Reset(I2C_TypeDef *i2c) +{ + // Cancel ongoing operations and clear TX buffer + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT; + i2c->CTRL = _I2C_CTRL_RESETVALUE; + i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE; + i2c->SADDR = _I2C_SADDR_RESETVALUE; + i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE; + i2c->IEN = _I2C_IEN_RESETVALUE; +#if defined (_I2C_EN_EN_MASK) + i2c->EN = _I2C_EN_RESETVALUE; +#endif + + // Empty received data buffer + flushRx(i2c); + I2C_IntClear(i2c, _I2C_IF_MASK); + /* Do not reset the route register; setting should be done independently. */ +} + +// ***************************************************************************** +/// @brief +/// Continue an initiated I2C transfer (single master mode only). +/// +/// @details +/// This function is used repeatedly after a I2C_TransferInit() to +/// complete a transfer. It may be used in polled mode as the below example +/// shows: +/// @code{.c} +/// I2C_TransferReturn_TypeDef ret; +/// +/// // Do a polled transfer +/// ret = I2C_TransferInit(I2C0, seq); +/// while (ret == i2cTransferInProgress) +/// { +/// ret = I2C_Transfer(I2C0); +/// } +/// @endcode +/// It may also be used in interrupt driven mode, where this function is invoked +/// from the interrupt handler. Notice that, if used in interrupt mode, NVIC +/// interrupts must be configured and enabled for the I2C bus used. I2C +/// peripheral specific interrupts are managed by this software. +/// +/// @note +/// Only single master mode is supported. +/// +/// @param[in] i2c +/// A pointer to the I2C peripheral register block. +/// +/// @return +/// Returns status for an ongoing transfer. +/// @li #i2cTransferInProgress - indicates that transfer not finished. +/// @li #i2cTransferDone - transfer completed successfully. +/// @li otherwise some sort of error has occurred. +/// +// ***************************************************************************** +I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c) +{ + uint32_t tmp; + uint32_t pending; + I2C_Transfer_TypeDef *transfer; + I2C_TransferSeq_TypeDef *seq; + bool finished = false; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + seq = transfer->seq; + while (!finished) { + pending = i2c->IF; + + /* If some sort of fault, abort transfer. */ + if (pending & I2C_IF_ERRORS) { + if (pending & I2C_IF_ARBLOST) { + /* If an arbitration fault, indicates either a slave device */ + /* not responding as expected, or other master which is not */ + /* supported by this software. */ + transfer->result = i2cTransferArbLost; + } else if (pending & I2C_IF_BUSERR) { + /* A bus error indicates a misplaced start or stop, which should */ + /* not occur in master mode controlled by this software. */ + transfer->result = i2cTransferBusErr; + } + + /* Ifan error occurs, it is difficult to know */ + /* an exact cause and how to resolve. It will be up to a wrapper */ + /* to determine how to handle a fault/recovery if possible. */ + transfer->state = i2cStateDone; + break; + } + + switch (transfer->state) { + /***************************************************/ + /* Send the first start+address (first byte if 10 bit). */ + /***************************************************/ + case i2cStateStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0; + + /* In 10 bit address mode, the address following the first */ + /* start always indicates write. */ + } else { + tmp = (uint32_t)(seq->addr) & 0xfe; + + if (seq->flags & I2C_FLAG_READ) { + /* Indicate read request */ + tmp |= 1; + } + } + + transfer->state = i2cStateAddrWFAckNack; + i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */ + i2c->CMD = I2C_CMD_START; + finished = true; + break; + + /*******************************************************/ + /* Wait for ACK/NACK on the address (first byte if 10 bit). */ + /*******************************************************/ + case i2cStateAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If a 10 bit address, send the 2nd byte of the address. */ + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + transfer->state = i2cStateAddrWF2ndAckNack; + i2c->TXDATA = (uint32_t)(seq->addr) & 0xff; + } else { + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateWFData; + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + } + finished = true; + break; + + /******************************************************/ + /* Wait for ACK/NACK on the second byte of a 10 bit address. */ + /******************************************************/ + case i2cStateAddrWF2ndAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* If using a plain read sequence with a 10 bit address, switch to send */ + /* a repeated start. */ + if (seq->flags & I2C_FLAG_READ) { + transfer->state = i2cStateRStartAddrSend; + } + /* Otherwise, expected to write 0 or more bytes. */ + else { + transfer->state = i2cStateDataSend; + } + continue; + } + finished = true; + break; + + /*******************************/ + /* Send a repeated start+address */ + /*******************************/ + case i2cStateRStartAddrSend: + if (seq->flags & I2C_FLAG_10BIT_ADDR) { + tmp = (uint32_t)((seq->addr >> 8) & 0x06) | 0xf0; + } else { + tmp = (uint32_t)(seq->addr & 0xfe); + } + + /* If this is a write+read combined sequence, read is about to start. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + /* Indicate a read request. */ + tmp |= 1; + /* If reading only one byte, prepare the NACK now before START command. */ + if (seq->buf[transfer->bufIndx].len == 1) { + i2c->CMD = I2C_CMD_NACK; + } + } + + transfer->state = i2cStateRAddrWFAckNack; + /* The START command has to be written first since repeated start. Otherwise, */ + /* data would be sent first. */ + i2c->CMD = I2C_CMD_START; + i2c->TXDATA = tmp; + + finished = true; + break; + + /**********************************************************************/ + /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */ + /**********************************************************************/ + case i2cStateRAddrWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + + /* Determine whether receiving or sending data. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateWFData; + } else { + transfer->state = i2cStateDataSend; + continue; + } + } + finished = true; + break; + + /*****************************/ + /* Send a data byte to the slave */ + /*****************************/ + case i2cStateDataSend: + /* Reached end of data buffer. */ + if (transfer->offset >= seq->buf[transfer->bufIndx].len) { + /* Move to the next message part. */ + transfer->offset = 0; + transfer->bufIndx++; + + /* Send a repeated start when switching to read mode on the 2nd buffer. */ + if (seq->flags & I2C_FLAG_WRITE_READ) { + transfer->state = i2cStateRStartAddrSend; + continue; + } + + /* Only writing from one buffer or finished both buffers. */ + if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + finished = true; + break; + } + + /* Reprocess in case the next buffer is empty. */ + continue; + } + + /* Send byte. */ + i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]); + transfer->state = i2cStateDataWFAckNack; + finished = true; + break; + + /*********************************************************/ + /* Wait for ACK/NACK from the slave after sending data to it. */ + /*********************************************************/ + case i2cStateDataWFAckNack: + if (pending & I2C_IF_NACK) { + I2C_IntClear(i2c, I2C_IF_NACK); + transfer->result = i2cTransferNack; + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else if (pending & I2C_IF_ACK) { + I2C_IntClear(i2c, I2C_IF_ACK); + transfer->state = i2cStateDataSend; + continue; + } + finished = true; + break; + + /****************************/ + /* Wait for data from slave */ + /****************************/ + case i2cStateWFData: + if (pending & I2C_IF_RXDATAV) { + uint8_t data; + unsigned int rxLen = seq->buf[transfer->bufIndx].len; + + /* Must read out data not to block further progress. */ + data = (uint8_t)(i2c->RXDATA); + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)) + // Errata I2C_E303. I2C Fails to Indicate New Incoming Data. + uint32_t status = i2c->STATUS; + // look for invalid RXDATAV = 0 and RXFULL = 1 condition + if (((status & I2C_IF_RXDATAV) == 0) & ((status & I2C_IF_RXFULL) != 0)) { + // Performing a dummy read of the RXFIFO (I2C_RXDATA). + // This restores the expected RXDATAV = 1 and RXFULL = 0 condition. + (void)i2c->RXDATA; + // The dummy read will also set the RXUFIF flag bit, which should be ignored and cleared. + I2C_IntClear(i2c, I2C_IF_RXUF); + } +#endif + + /* SW needs to clear RXDATAV IF on Series 2 devices. + Flag is kept high by HW if buffer is not empty. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + I2C_IntClear(i2c, I2C_IF_RXDATAV); +#endif + + /* Make sure that there is no storing beyond the end of the buffer (just in case). */ + if (transfer->offset < rxLen) { + seq->buf[transfer->bufIndx].data[transfer->offset++] = data; + } + + /* If all requested data is read, the sequence should end. */ + if (transfer->offset >= rxLen) { + transfer->state = i2cStateWFStopSent; + i2c->CMD = I2C_CMD_STOP; + } else { + /* Send ACK and wait for the next byte. */ + i2c->CMD = I2C_CMD_ACK; + + if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) { + /* If receiving more than one byte and this is the next + to last byte, transmit the NACK now before receiving + the last byte. */ + i2c->CMD = I2C_CMD_NACK; + } + } + } + finished = true; + break; + + /***********************************/ + /* Wait for STOP to have been sent */ + /***********************************/ + case i2cStateWFStopSent: + if (pending & I2C_IF_MSTOP) { + I2C_IntClear(i2c, I2C_IF_MSTOP); + transfer->state = i2cStateDone; + } + finished = true; + break; + + /******************************/ + /* An unexpected state, software fault */ + /******************************/ + default: + transfer->result = i2cTransferSwFault; + transfer->state = i2cStateDone; + finished = true; + break; + } + } + + if (transfer->state == i2cStateDone) { + /* Disable interrupt sources when done. */ + i2c->IEN = 0; + + /* Update the result unless a fault has already occurred. */ + if (transfer->result == i2cTransferInProgress) { + transfer->result = i2cTransferDone; + } + } + /* Until transfer is done, keep returning i2cTransferInProgress. */ + else { + return i2cTransferInProgress; + } + + return transfer->result; +} + +/***************************************************************************//** + * @brief + * Prepare and start an I2C transfer (single master mode only). + * + * @details + * This function must be invoked to start an I2C transfer + * sequence. To complete the transfer, I2C_Transfer() must + * be used either in polled mode or by adding a small driver wrapper using + * interrupts. + * + * @note + * Only single master mode is supported. + * + * @param[in] i2c + * A pointer to the I2C peripheral register block. + * + * @param[in] seq + * A pointer to the sequence structure defining the I2C transfer to take place. The + * referenced structure must exist until the transfer has fully completed. + * + * @return + * Returns the status for an ongoing transfer: + * @li #i2cTransferInProgress - indicates that the transfer is not finished. + * @li Otherwise, an error has occurred. + ******************************************************************************/ +I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c, + I2C_TransferSeq_TypeDef *seq) +{ + I2C_Transfer_TypeDef *transfer; + + EFM_ASSERT(I2C_REF_VALID(i2c)); + EFM_ASSERT(seq); + + /* Support up to 2 I2C buses. */ + if (i2c == I2C0) { + transfer = i2cTransfer; + } +#if (I2C_COUNT > 1) + else if (i2c == I2C1) { + transfer = i2cTransfer + 1; + } +#endif +#if (I2C_COUNT > 2) + else if (i2c == I2C2) { + transfer = i2cTransfer + 2; + } +#endif +#if (I2C_COUNT > 3) + else if (i2c == I2C3) { + transfer = i2cTransfer + 3; + } +#endif + else { + return i2cTransferUsageFault; + } + + /* Check if in a busy state. Since this software assumes a single master, */ + /* issue an abort. The BUSY state is normal after a reset. */ + if (i2c->STATE & I2C_STATE_BUSY) { + i2c->CMD = I2C_CMD_ABORT; + } + + /* Do not try to read 0 bytes. It is not */ + /* possible according to the I2C spec, since the slave will always start */ + /* sending the first byte ACK on an address. The read operation can */ + /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */ + if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len)) + || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len)) + ) { + return i2cTransferUsageFault; + } + + /* Prepare for a transfer. */ + transfer->state = i2cStateStartAddrSend; + transfer->result = i2cTransferInProgress; + transfer->offset = 0; + transfer->bufIndx = 0; + transfer->seq = seq; + + /* Ensure buffers are empty. */ + i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX; + flushRx(i2c); + + /* Clear all pending interrupts prior to starting a transfer. */ + I2C_IntClear(i2c, _I2C_IF_MASK); + + /* Enable relevant interrupts. */ + /* Notice that the I2C interrupt must also be enabled in the NVIC, but */ + /* that is left for an additional driver wrapper. */ + i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP + | I2C_IEN_RXDATAV | I2C_IEN_ERRORS; + + /* Start a transfer. */ + return I2C_Transfer(i2c); +} + +/** @} (end addtogroup i2c) */ +#endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c index 8981b26..f2d5f3d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_iadc.c @@ -1,1178 +1,1178 @@ -/***************************************************************************//** - * @file - * @brief Incremental Analog to Digital Converter (IADC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_iadc.h" - -#if defined(IADC_COUNT) && (IADC_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include - -/***************************************************************************//** - * @addtogroup emlib - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup iadc IADC - Incremental ADC - * @brief Incremental Analog to Digital Converter (IADC) Peripheral API - * @details - * This module contains functions to control the IADC peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The IADC is used to convert analog signals into a - * digital representation. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -// Validation of IADC register block pointer reference for assert statements. -#if defined(IADC_NUM) -#define IADC_REF_VALID(ref) (IADC_NUM(ref) != -1) -#else -#if (IADC_COUNT == 1) -#define IADC_REF_VALID(ref) ((ref) == IADC0) -#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : -1) -#elif (IADC_COUNT == 2) -#define IADC_REF_VALID(ref) (((ref) == IADC0) || ((ref) == IADC1)) -#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : ((ref) == IADC1) ? 1 : -1) -#endif -#endif - -// Max IADC clock rates -#define IADC_CLK_MAX_FREQ 40000000UL -#define IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ 20000000UL -#define IADC_ANA_CLK_NORMAL_MAX_FREQ 10000000UL -#define IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ 5000000UL -#if defined (_IADC_CFG_ADCMODE_HIGHSPEED) -#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ - (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ - : ((adcMode) == iadcCfgModeHighSpeed \ - ? IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ \ - : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ) \ - ) -#else -#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ - (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ - : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ \ - ) -#endif - -#define IADC_ROUND_D2I(n) (int)((n) < 0.0f ? ((n) - 0.5f) : ((n) + 0.5f)) - -#define IADC0_SCANENTRIES IADC0_ENTRIES -#define IADC0_FIFOENTRIES 0x4UL - -#define IADC1_SCANENTRIES IADC1_ENTRIES -#define IADC1_FIFOENTRIES 0x4UL - -#if defined(IADC_ENTRIES) -#define IADC_SCANENTRIES(iadc) IADC_ENTRIES(IADC_NUM(iadc)) -#else -#define IADC_SCANENTRIES(iadc) ( \ - (iadc) == IADC0 ? IADC0_SCANENTRIES \ - : 0UL) -#endif - -#if !defined(IADC_CONFIGNUM) -#define IADC_CONFIGNUM(iadc) ( \ - (iadc) == 0 ? IADC0_CONFIGNUM \ - : 0UL) -#endif - -#define IADC_FIFOENTRIES(iadc) ( \ - (iadc) == IADC0 ? IADC0_FIFOENTRIES \ - : 0UL) - -#define IADC_CMU_CLOCK(iadc) ( \ - (iadc) == IADC0 ? cmuClock_IADC0 \ - : cmuClock_IADC0) - -/** @endcond */ - -/******************************************************************************* - *************************** LOCAL FUNCTIONS ******************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -static void IADC_disable(IADC_TypeDef *iadc) -{ -#if defined(IADC_STATUS_SYNCBUSY) - while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { - // Wait for synchronization to finish before disable - } -#endif - iadc->EN_CLR = IADC_EN_EN; -#if defined(_IADC_EN_DISABLING_MASK) - while (IADC0->EN & _IADC_EN_DISABLING_MASK) { - } -#endif -} - -static void IADC_enable(IADC_TypeDef *iadc) -{ - iadc->EN_SET = IADC_EN_EN; -} - -static IADC_Result_t IADC_ConvertRawDataToResult(uint32_t rawData, - IADC_Alignment_t alignment) -{ - IADC_Result_t result; - - switch (alignment) { - case iadcAlignRight12: -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - case iadcAlignRight16: -#endif -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - case iadcAlignRight20: -#endif - // Mask out ID and replace with sign extension - result.data = (rawData & 0x00FFFFFFUL) - | ((rawData & 0x00800000UL) != 0x0UL ? 0xFF000000UL : 0x0UL); - // Mask out data and shift down - result.id = (uint8_t)((rawData & 0xFF000000UL) >> 24); - break; - - case iadcAlignLeft12: -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) - case iadcAlignLeft16: -#endif -#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) - case iadcAlignLeft20: -#endif - result.data = rawData & 0xFFFFFF00UL; - result.id = (uint8_t)(rawData & 0x000000FFUL); - break; - default: - break; - } - return result; -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize IADC. - * - * @details - * Initializes common parts for both single conversion and scan sequence. - * In addition, single and/or scan control configuration must be done, please - * refer to @ref IADC_initSingle() and @ref IADC_initScan() respectively. - * - * @note - * This function will stop any ongoing conversions. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC initialization structure. - * - * @param[in] allConfigs - * Pointer to structure holding all configs. - ******************************************************************************/ -void IADC_init(IADC_TypeDef *iadc, - const IADC_Init_t *init, - const IADC_AllConfigs_t *allConfigs) -{ - uint32_t tmp; - uint32_t config; - uint16_t wantedPrescale; - uint8_t srcClkPrescale; - uint32_t adcClkPrescale; - uint8_t timebase; - unsigned uiAnaGain; - uint16_t uiGainCAna; - IADC_CfgAdcMode_t adcMode; -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - float anaGain; - int anaGainRound; - float offsetAna; - float offset2; - int offsetLong; - int offsetAna1HiAccInt; - uint8_t osrValue; - float offsetAnaBase; - float gainSysHiAcc; - float refVoltage = 0; - // Over sampling ratio for high accuracy conversions - const float osrHiAcc[6] = { 16.0, 32.0, 64.0, 92.0, 128.0, 256.0 }; -#endif - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - // Calculate min allowed SRC_CLK prescaler setting - srcClkPrescale = IADC_calcSrcClkPrescale(iadc, IADC_CLK_MAX_FREQ, 0); - - wantedPrescale = init->srcClkPrescale; - // Use wanted SRC_CLK prescaler setting instead if it is high enough - if (wantedPrescale >= srcClkPrescale) { - srcClkPrescale = wantedPrescale; - } - - IADC_disable(iadc); - - timebase = init->timebase; - if (timebase == 0) { - // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set - // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. - uint32_t srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); - // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE to obtain valid frequency - if (srcClkFreq >= IADC_CLK_MAX_FREQ) { - srcClkFreq = srcClkFreq / srcClkPrescale; - } - // Calculate timebase based on CMU_IADCCLKCTRL - timebase = IADC_calcTimebase(iadc, srcClkFreq); - } - - tmp = (((uint32_t)(init->warmup) << _IADC_CTRL_WARMUPMODE_SHIFT) - & _IADC_CTRL_WARMUPMODE_MASK) - | (((uint32_t)(timebase) << _IADC_CTRL_TIMEBASE_SHIFT) - & _IADC_CTRL_TIMEBASE_MASK) - | (((uint32_t)(srcClkPrescale) << _IADC_CTRL_HSCLKRATE_SHIFT) - & _IADC_CTRL_HSCLKRATE_MASK); - - if (init->iadcClkSuspend0) { - tmp |= IADC_CTRL_ADCCLKSUSPEND0; - } - if (init->iadcClkSuspend1) { - tmp |= IADC_CTRL_ADCCLKSUSPEND1; - } - if (init->debugHalt) { - tmp |= IADC_CTRL_DBGHALT; - } - iadc->CTRL = tmp; - - iadc->TIMER = ((uint32_t) (init->timerCycles) << _IADC_TIMER_TIMER_SHIFT) - & _IADC_TIMER_TIMER_MASK; - - iadc->CMPTHR = (((uint32_t) (init->greaterThanEqualThres) << _IADC_CMPTHR_ADGT_SHIFT) - & _IADC_CMPTHR_ADGT_MASK) - | (((uint32_t) (init->lessThanEqualThres) << _IADC_CMPTHR_ADLT_SHIFT) - & _IADC_CMPTHR_ADLT_MASK); - - // Write configurations - for (config = 0; config < IADC_CONFIGNUM(IADC_NUM(iadc)); config++) { - // Find min allowed ADC_CLK prescaler setting for given mode - adcMode = allConfigs->configs[config].adcMode; - wantedPrescale = allConfigs->configs[config].adcClkPrescale; - adcClkPrescale = IADC_calcAdcClkPrescale(iadc, - IADC_ANA_CLK_MAX_FREQ(adcMode), - 0, - adcMode, - srcClkPrescale); - - // Use wanted ADC_CLK prescaler setting instead if it is high enough - adcClkPrescale = SL_MAX(adcClkPrescale, wantedPrescale); - - tmp = iadc->CFG[config].CFG & ~(_IADC_CFG_ADCMODE_MASK | _IADC_CFG_OSRHS_MASK - | _IADC_CFG_ANALOGGAIN_MASK | _IADC_CFG_REFSEL_MASK -#if defined(_IADC_CFG_DIGAVG_MASK) - | _IADC_CFG_DIGAVG_MASK -#endif - | _IADC_CFG_TWOSCOMPL_MASK -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - | _IADC_CFG_OSRHA_MASK -#endif - ); - iadc->CFG[config].CFG = tmp - | (((uint32_t)(adcMode) << _IADC_CFG_ADCMODE_SHIFT) & _IADC_CFG_ADCMODE_MASK) - | (((uint32_t)(allConfigs->configs[config].osrHighSpeed) << _IADC_CFG_OSRHS_SHIFT) - & _IADC_CFG_OSRHS_MASK) -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - | (((uint32_t)(allConfigs->configs[config].osrHighAccuracy) << _IADC_CFG_OSRHA_SHIFT) - & _IADC_CFG_OSRHA_MASK) -#endif - | (((uint32_t)(allConfigs->configs[config].analogGain) << _IADC_CFG_ANALOGGAIN_SHIFT) - & _IADC_CFG_ANALOGGAIN_MASK) - | (((uint32_t)(allConfigs->configs[config].reference) << _IADC_CFG_REFSEL_SHIFT) - & _IADC_CFG_REFSEL_MASK) -#if defined(_IADC_CFG_DIGAVG_MASK) - | (((uint32_t)(allConfigs->configs[config].digAvg) << _IADC_CFG_DIGAVG_SHIFT) - & _IADC_CFG_DIGAVG_MASK) -#endif - | (((uint32_t)(allConfigs->configs[config].twosComplement) << _IADC_CFG_TWOSCOMPL_SHIFT) - & _IADC_CFG_TWOSCOMPL_MASK); - - uiAnaGain = (iadc->CFG[config].CFG & _IADC_CFG_ANALOGGAIN_MASK) >> _IADC_CFG_ANALOGGAIN_SHIFT; - switch (uiAnaGain) { -#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) - case iadcCfgAnalogGain0P25x: // 0.25x -#endif - case iadcCfgAnalogGain0P5x: // 0.5x - case iadcCfgAnalogGain1x: // 1x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); - break; - case iadcCfgAnalogGain2x: // 2x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA2_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT); - break; - case iadcCfgAnalogGain3x: // 3x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA3_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT); - break; - case iadcCfgAnalogGain4x: // 4x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA4_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT); - break; - default: // 1x - uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); - break; - } - - // Gain and offset correction is applied according to adcMode and oversampling rate. - switch (adcMode) { - float offset; - uint32_t scale; - int iOffset, iOsr; - case iadcCfgModeNormal: -#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) - case iadcCfgModeHighSpeed: -#endif - offset = 0.0f; - if (uiAnaGain == iadcCfgAnalogGain2x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT); - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT); - } - } else if (uiAnaGain == iadcCfgAnalogGain3x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 2; - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 2; - } - } else if (uiAnaGain == iadcCfgAnalogGain4x) { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 3; - } else { - offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 3; - } - } - - // Set correct gain correction bitfields in scale variable. - tmp = (uint32_t)uiGainCAna & 0x9FFFU; - scale = tmp << _IADC_SCALE_GAIN13LSB_SHIFT; - if ((tmp & 0x8000U) != 0U) { - scale |= IADC_SCALE_GAIN3MSB; - } - - // Adjust offset according to selected OSR. - iOsr = 1U << (((iadc->CFG[config].CFG & _IADC_CFG_OSRHS_MASK) >> _IADC_CFG_OSRHS_SHIFT) + 1U); - if (iOsr == 2) { - if (adcMode == iadcCfgModeNormal) { - offset += (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 & _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK); - } else { - offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 & _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK); - } - } else { - if (adcMode == iadcCfgModeNormal) { - offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL1 & _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK) - offset; - } else { - offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL1 & _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK) - offset; - } - offset /= iOsr / 2.0f; - offset += (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK); - } - - // Compensate offset according to selected reference voltage. - if (allConfigs->configs[config].reference == iadcCfgReferenceInt1V2) { - // Internal reference voltage (VBGR) depends on the chip revision. - offset *= 1.25f / (IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f); - } else { - offset *= 1.25f / (allConfigs->configs[config].vRef / 1000.0f); - } - - // Compensate offset for systematic offset. - offset = (offset * 4.0f) + (640.0f * (256.0f / iOsr)); - - // Apply gain error correction. - if (scale != 0x80000000U) { - offset = (uiGainCAna / 32768.0f) * (offset + 524288.0f) - 524288.0f; - } - - iOffset = IADC_ROUND_D2I(-offset); - // We only have 18 bits available for OFFSET in SCALE register. - // OFFSET is a 2nd complement number. - if (iOffset > 131071) { // Positive overflow at 0x0001FFFF ? - scale |= 0x1FFFFU; - } else if (iOffset < -131072) { // Negative overflow at 0xFFFE0000 ? - scale |= 0x20000U; - } else { - scale |= (uint32_t)iOffset & 0x3FFFFU; - } - iadc->CFG[config].SCALE = scale; - break; - -#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) - case iadcCfgModeHighAccuracy: - // Get reference voltage in volts - refVoltage = IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f; - - // Get OSR from config register - osrValue = (iadc->CFG[config].CFG & _IADC_CFG_OSRHA_MASK) >> _IADC_CFG_OSRHA_SHIFT; - - // 1. Calculate gain correction - if ((uint32_t)osrHiAcc[osrValue] == 92U) { - // for OSR = 92, gainSysHiAcc = 0.957457 - gainSysHiAcc = 0.957457; - } else { - // for OSR != 92, gainSysHiAcc = OSR/(OSR + 1) - gainSysHiAcc = osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f); - } - anaGain = (float) uiGainCAna / 32768.0f * gainSysHiAcc; - anaGainRound = IADC_ROUND_D2I(32768.0f * anaGain); - IADC0->CFG[config].SCALE &= ~_IADC_SCALE_MASK; - - // Write GAIN3MSB - if ((uint32_t)anaGainRound & 0x8000) { - IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN100; - } else { - IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN011; - } - // Write GAIN13LSB - IADC0->CFG[config].SCALE |= ((uint32_t)anaGainRound & 0x1FFF) << _IADC_SCALE_GAIN13LSB_SHIFT; - - // Get offset value for high accuracy mode from DEVINFO - offsetAna1HiAccInt = (uint16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK) - >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT; - - // 2. OSR adjustment - // Get offset from DEVINFO - offsetAnaBase = (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK) - >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT; - // 1 << osrValue is the same as pow(2, osrValue) - offsetAna = offsetAnaBase + (offsetAna1HiAccInt) / (1 << osrValue); - - // 3. Reference voltage adjustment - offsetAna = (offsetAna) * (1.25f / refVoltage); - - // 4. Calculate final offset - offset2 = 262144.0f / osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f) + offsetAna * 4.0f + 524288.0f; - offset2 = (uiGainCAna / 32768.0f * (-1.0f)) * offset2 + 524288.0f; - offsetLong = IADC_ROUND_D2I(offset2); - - // 5. Write offset to scale register - IADC0->CFG[config].SCALE |= (uint32_t)(offsetLong & _IADC_SCALE_OFFSET_MASK); - break; -#endif - default: - // Mode not supported. - EFM_ASSERT(false); - break; - } - iadc->CFG[config].SCHED = ((adcClkPrescale << _IADC_SCHED_PRESCALE_SHIFT) - & _IADC_SCHED_PRESCALE_MASK); - } - IADC_enable(iadc); -} - -/***************************************************************************//** - * @brief - * Initialize IADC scan sequence. - * - * @details - * This function will configure scan mode and set up entries in the scan - * table. The scan table mask can be updated by calling IADC_updateScanMask. - * - * @note - * This function will stop any ongoing conversions. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC initialization structure. - * - * @param[in] scanTable - * Pointer to IADC scan table structure. - ******************************************************************************/ -void IADC_initScan(IADC_TypeDef *iadc, - const IADC_InitScan_t *init, - const IADC_ScanTable_t *scanTable) -{ - uint32_t i; - uint32_t tmp; - EFM_ASSERT(IADC_REF_VALID(iadc)); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. - EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); -#endif - - IADC_disable(iadc); - - iadc->SCANFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT) - & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - | (init->showId ? IADC_SCANFIFOCFG_SHOWID : 0UL) - | (((uint32_t) (init->dataValidLevel) << _IADC_SCANFIFOCFG_DVL_SHIFT) - & _IADC_SCANFIFOCFG_DVL_MASK) - | (init->fifoDmaWakeup ? IADC_SCANFIFOCFG_DMAWUFIFOSCAN : 0UL); - - // Clear bitfields for scan conversion in IADCn->TRIGGER and set new values - iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SCANTRIGSEL_MASK - | _IADC_TRIGGER_SCANTRIGACTION_MASK)) - | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SCANTRIGSEL_SHIFT) - & _IADC_TRIGGER_SCANTRIGSEL_MASK) - | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SCANTRIGACTION_SHIFT) - & _IADC_TRIGGER_SCANTRIGACTION_MASK); - - // Write scan table - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - iadc->SCANTABLE[i].SCAN = (((uint32_t) (scanTable->entries[i].negInput) << _IADC_SCAN_PINNEG_SHIFT) - & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) - | (((uint32_t) (scanTable->entries[i].posInput) << _IADC_SCAN_PINPOS_SHIFT) - & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) - | (((uint32_t) (scanTable->entries[i].configId) << _IADC_SCAN_CFG_SHIFT) - & _IADC_SCAN_CFG_MASK) - | (scanTable->entries[i].compare ? IADC_SCAN_CMP : 0UL); - } - - IADC_enable(iadc); - - // Set scan mask - tmp = 0; - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - if (scanTable->entries[i].includeInScan) { - tmp |= (1UL << i) << _IADC_MASKREQ_MASKREQ_SHIFT; - } - } - iadc->MASKREQ = tmp; - - if (init->start) { - IADC_command(iadc, iadcCmdStartScan); - } -} - -/***************************************************************************//** - * @brief - * Initialize single IADC conversion. - * - * @details - * This function will initialize the single conversion and configure the - * single input selection. - * - * @note - * This function will stop any ongoing conversions. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] init - * Pointer to IADC single initialization structure. - * - * @param[in] input - * Pointer to IADC single input selection initialization structure. - ******************************************************************************/ -void IADC_initSingle(IADC_TypeDef *iadc, - const IADC_InitSingle_t *init, - const IADC_SingleInput_t *input) -{ - EFM_ASSERT(IADC_REF_VALID(iadc)); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) - // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. - EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); -#endif - IADC_disable(iadc); - - iadc->SINGLEFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT) - & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - | (init->showId ? IADC_SINGLEFIFOCFG_SHOWID : 0UL) - | (((uint32_t) (init->dataValidLevel) << _IADC_SINGLEFIFOCFG_DVL_SHIFT) - & _IADC_SINGLEFIFOCFG_DVL_MASK) - | (init->fifoDmaWakeup ? IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE : 0UL); - - // Clear bitfields for single conversion in IADCn->TRIGGER and set new values - iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SINGLETRIGSEL_MASK - | _IADC_TRIGGER_SINGLETRIGACTION_MASK - | _IADC_TRIGGER_SINGLETAILGATE_MASK)) - | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SINGLETRIGSEL_SHIFT) - & _IADC_TRIGGER_SINGLETRIGSEL_MASK) - | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SINGLETRIGACTION_SHIFT) - & _IADC_TRIGGER_SINGLETRIGACTION_MASK) - | (init->singleTailgate ? IADC_TRIGGER_SINGLETAILGATE : 0UL); - - IADC_updateSingleInput(iadc, input); - - IADC_enable(iadc); - - if (init->start) { - IADC_command(iadc, iadcCmdStartSingle); - } -} - -/***************************************************************************//** - * @brief - * Update IADC single input selection. - * - * @details - * This function updates the single input selection. The function can be - * called while single and/or scan conversions are ongoing and the new input - * configuration will take place on the next single conversion. - * - * @note If an even numbered pin is selected for the positive input, the - * negative input must use an odd numbered pin and vice versa. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] input - * Pointer to single input selection structure. - ******************************************************************************/ -void IADC_updateSingleInput(IADC_TypeDef *iadc, - const IADC_SingleInput_t *input) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADCn->SINGLE has WSYNC type and can only be written while enabled - IADC_enable(iadc); - - iadc->SINGLE = (((uint32_t) (input->negInput) << _IADC_SINGLE_PINNEG_SHIFT) - & (_IADC_SINGLE_PORTNEG_MASK | _IADC_SINGLE_PINNEG_MASK)) - | (((uint32_t) (input->posInput) << _IADC_SINGLE_PINPOS_SHIFT) - & (_IADC_SINGLE_PORTPOS_MASK | _IADC_SINGLE_PINPOS_MASK)) - | (((uint32_t) (input->configId) << _IADC_SINGLE_CFG_SHIFT) - & _IADC_SINGLE_CFG_MASK) - | (input->compare ? IADC_SINGLE_CMP : 0UL); - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Set mask of IADC scan table entries to include in scan. - * - * @details - * Set mask of scan table entries to include in next scan. This function - * can be called while scan conversions are ongoing, but the new scan mask - * will take effect once the ongoing scan is completed. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] mask - * Mask of scan table entries to include in scan. - ******************************************************************************/ -void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - EFM_ASSERT(mask <= ((1UL << IADC_SCANENTRIES(iadc)) - 1UL)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADC must be enabled to update scan table mask - IADC_enable(iadc); - - iadc->MASKREQ = (mask << _IADC_MASKREQ_MASKREQ_SHIFT) - & _IADC_MASKREQ_MASKREQ_MASK; - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Add/update entry in scan table. - * - * @details - * This function will update or add an entry in the scan table with a specific - * ID. - * - * @note - * This function will stop any ongoing conversions. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] id - * ID of scan table entry to add. - * - * @param[in] entry - * Pointer to scan table entry structure. - ******************************************************************************/ -void IADC_updateScanEntry(IADC_TypeDef *iadc, - uint8_t id, - IADC_ScanTableEntry_t *entry) -{ - bool enabled; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - - enabled = (iadc->EN & IADC_EN_EN) != 0UL; - - // IADC must be disabled to update scan table - IADC_disable(iadc); - - // Update entry in scan table - iadc->SCANTABLE[id].SCAN = (((uint32_t) (entry->negInput) << _IADC_SCAN_PINNEG_SHIFT) - & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) - | (((uint32_t) (entry->posInput) << _IADC_SCAN_PINPOS_SHIFT) - & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) - | (((uint32_t) (entry->configId) << _IADC_SCAN_CFG_SHIFT) - & _IADC_SCAN_CFG_MASK) - | (entry->compare ? IADC_SCAN_CMP : 0UL); - - // IADC must be enabled to update scan table mask - IADC_enable(iadc); - - if (entry->includeInScan) { - iadc->MASKREQ_SET = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; - } else { - iadc->MASKREQ_CLR = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; - } - - // Restore enabled state - if (!enabled) { - IADC_disable(iadc); - } -} - -/***************************************************************************//** - * @brief - * Reset IADC to same state as after a HW reset. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - ******************************************************************************/ -void IADC_reset(IADC_TypeDef *iadc) -{ - uint32_t i; - EFM_ASSERT(IADC_REF_VALID(iadc)); - - // Write all WSYNC registers to reset value while enabled - IADC_enable(iadc); - - // Stop conversions and timer, before resetting other registers. - iadc->CMD = IADC_CMD_SINGLESTOP | IADC_CMD_SCANSTOP | IADC_CMD_TIMERDIS; - - // Wait for all IADC operations to stop - while ((iadc->STATUS & (IADC_STATUS_CONVERTING - | IADC_STATUS_SCANQUEUEPENDING - | IADC_STATUS_SINGLEQUEUEPENDING - | IADC_STATUS_TIMERACTIVE)) - != 0UL) { - } - - // Reset all WSYNC registers - iadc->MASKREQ = _IADC_MASKREQ_RESETVALUE; - iadc->SINGLE = _IADC_SINGLE_RESETVALUE; - - // Wait for SINGLE and MASQREQ writes to propagate to working registers - while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING - | IADC_STATUS_SINGLEWRITEPENDING)) - != 0UL) { - } - - // Pull from FIFOs until they are empty - - // Errata IADC_E305: Check SINGLEFIFOSTAT to make sure that SINGLEFIFO is getting emptied in case - // where STATUS register is incorrect. - while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { - (void) IADC_pullSingleFifoData(iadc); - } - - // Errata IADC_E305: check SCANFIFOSTAT to make sure that SCANFIFO is getting emptied in case - // where STATUS register is incorrect. - while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { - (void) IADC_pullScanFifoData(iadc); - } - - // Read data registers to clear data valid flags - (void) IADC_readSingleData(iadc); - (void) IADC_readScanData(iadc); - - // Write all WSTATIC registers to reset value while disabled - IADC_disable(iadc); - - // Reset all WSTATIC registers - iadc->CTRL = _IADC_CTRL_RESETVALUE; - iadc->TIMER = _IADC_TIMER_RESETVALUE; - iadc->TRIGGER = _IADC_TRIGGER_RESETVALUE; - - iadc->CMPTHR = _IADC_CMPTHR_RESETVALUE; - iadc->SINGLEFIFOCFG = _IADC_SINGLEFIFOCFG_RESETVALUE; - iadc->SCANFIFOCFG = _IADC_SCANFIFOCFG_RESETVALUE; - - for (i = 0; i < IADC_CONFIGNUM(IADC_NUM(iadc)); i++) { - iadc->CFG[i].CFG = _IADC_CFG_RESETVALUE; - iadc->CFG[i].SCALE = _IADC_SCALE_RESETVALUE; - iadc->CFG[i].SCHED = _IADC_SCHED_RESETVALUE; - } - - for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { - iadc->SCANTABLE[i].SCAN = _IADC_SCAN_RESETVALUE; - } - - // Clear interrupt flags and disable interrupts - IADC_clearInt(iadc, _IADC_IF_MASK); - IADC_disableInt(iadc, _IADC_IEN_MASK); -} - -/***************************************************************************//** - * @brief - * Calculate timebase value in order to get a timebase providing at least 1us. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] srcClkFreq Frequency in Hz of reference CLK_SRC_ADC clock. Set to 0 to - * derive srcClkFreq from CLK_CMU_ADC and prescaler HSCLKRATE. - * - * @return - * Timebase value to use for IADC in order to achieve at least 1 us. - ******************************************************************************/ -uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq) -{ - EFM_ASSERT(IADC_REF_VALID(iadc)); - - if (srcClkFreq == 0UL) { - // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set - // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. - srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); - - // Just in case, make sure we get non-zero frequency for below calculation - if (srcClkFreq == 0UL) { - srcClkFreq = 1; - } - // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE - if (srcClkFreq > IADC_CLK_MAX_FREQ) { - uint32_t prescaler = (uint32_t)(IADC0->CTRL & _IADC_CTRL_HSCLKRATE_MASK) >> _IADC_CTRL_HSCLKRATE_SHIFT; - srcClkFreq /= (prescaler + 1); - } - } - - // Determine number of ADCCLK cycle >= 1us - srcClkFreq += 999999UL; - srcClkFreq /= 1000000UL; - - // Convert to N+1 format - srcClkFreq -= 1UL; - - // Limit to max allowed register setting - srcClkFreq = SL_MIN(srcClkFreq, (_IADC_CTRL_TIMEBASE_MASK >> _IADC_CTRL_TIMEBASE_SHIFT)); - - // Return timebase value - return (uint8_t) srcClkFreq; -} - -/***************************************************************************//** - * @brief - * Calculate prescaler for CLK_SRC_ADC high speed clock - * - * @details - * The IADC high speed clock is given by: CLK_SRC_ADC / (srcClkPrescaler + 1). - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] srcClkFreq CLK_SRC_ADC frequency wanted. The frequency will - * automatically be adjusted to be within valid range according to reference - * manual. - * - * @param[in] cmuClkFreq Frequency in Hz of reference CLK_CMU_ADC. Set to 0 - * to use currently defined CMU clock setting for the IADC. - * - * @return - * Divider value to use for IADC in order to achieve a high speed clock value - * <= @p srcClkFreq. - ******************************************************************************/ -uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, - uint32_t srcClkFreq, - uint32_t cmuClkFreq) -{ - uint32_t ret; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - EFM_ASSERT(srcClkFreq); - - // Make sure wanted CLK_SRC_ADC clock is below max allowed frequency - srcClkFreq = SL_MIN(srcClkFreq, IADC_CLK_MAX_FREQ); - - // Use current CLK_CMU_ADC frequency? - if (cmuClkFreq == 0UL) { - cmuClkFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); - } - - ret = (cmuClkFreq + srcClkFreq - 1UL) / srcClkFreq; - if (ret != 0UL) { - ret--; - } - - // Limit to max allowed register setting - if (ret > _IADC_CTRL_HSCLKRATE_DIV4) { - ret = _IADC_CTRL_HSCLKRATE_DIV4; - } - - return (uint8_t)ret; -} - -/***************************************************************************//** - * @brief - * Calculate prescaler for ADC_CLK clock. - * - * @details - * The ADC_CLK is given by: CLK_SRC_ADC / (adcClkprescale + 1). - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @param[in] adcClkFreq ADC_CLK frequency wanted. The frequency will - * automatically be adjusted to be within valid range according to reference - * manual. - * - * @param[in] cmuClkFreq Frequency in Hz of CLK_CMU_ADC Set to 0 to - * use currently defined IADC clock setting (in CMU). - * - * @param[in] adcMode Mode for IADC config. - * - * @param[in] srcClkPrescaler Precaler setting for ADC_CLK - * - * @return - * Divider value to use for IADC in order to achieve a ADC_CLK frequency - * <= @p adcClkFreq. - ******************************************************************************/ -uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, - uint32_t adcClkFreq, - uint32_t cmuClkFreq, - IADC_CfgAdcMode_t adcMode, - uint8_t srcClkPrescaler) -{ - uint32_t ret; - uint32_t resFreq; - - EFM_ASSERT(IADC_REF_VALID(iadc)); - EFM_ASSERT(adcClkFreq); - - // Make sure wanted analog clock is below max allowed frequency for the given - // mode. - if (adcClkFreq > IADC_ANA_CLK_MAX_FREQ(adcMode)) { - adcClkFreq = IADC_ANA_CLK_MAX_FREQ(adcMode); - } - - // Use current CLK_CMU_ADC frequency? - if (cmuClkFreq == 0UL) { - resFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); - } else { - resFreq = cmuClkFreq; - } - - // Apply CLK_SRC_ADC prescaler - resFreq /= srcClkPrescaler + 1UL; - - ret = (resFreq + adcClkFreq - 1UL) / adcClkFreq; - if (ret != 0UL) { - ret--; - } - - // Limit to max allowed register setting - ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); - - return (uint16_t)ret; -} - -/***************************************************************************//** - * @brief - * Pull result from single data FIFO. The result struct includes both the data - * and the ID (0x20) if showId was set when initializing single mode. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SINGLEFIFODATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Read most recent single conversion result. The result struct includes both - * the data and the ID (0x20) if showId was set when initializing single mode. - * Calling this function will not affect the state of the single data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Single conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SINGLEDATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Pull result from scan data FIFO. The result struct includes both the data - * and the ID (0x20) if showId was set when initializing scan entry. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SCANFIFODATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Read most recent scan conversion result. The result struct includes both - * the data and the ID (0x20) if showId was set when initializing scan entry. - * Calling this function will not affect the state of the scan data FIFO. - * - * @note - * Check data valid flag before calling this function. - * - * @param[in] iadc - * Pointer to IADC peripheral register block. - * - * @return - * Scan conversion result struct holding data and id. - ******************************************************************************/ -IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc) -{ - uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) - >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; - return IADC_ConvertRawDataToResult(iadc->SCANDATA, - (IADC_Alignment_t) alignment); -} - -/***************************************************************************//** - * @brief - * Get reference voltage selection. - * - * @param[in] reference - * IADC Reference selection. - * - * @return - * IADC reference voltage in millivolts. - ******************************************************************************/ -uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference) -{ - uint32_t refVoltage = 0; - // Get chip revision - SYSTEM_ChipRevision_TypeDef chipRev; - SYSTEM_ChipRevisionGet(&chipRev); - switch (reference) { - case iadcCfgReferenceInt1V2: -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - if (chipRev.major == 1UL) { - refVoltage = 1210; - } else { - refVoltage = 1180; - } -#else - refVoltage = 1210; -#endif - break; - case iadcCfgReferenceExt1V25: - refVoltage = 1250; - break; -#if defined(_IADC_CFG_REFSEL_VREF2P5) - case iadcCfgReferenceExt2V5: - refVoltage = 2500; - break; -#endif - case iadcCfgReferenceVddx: - refVoltage = 3000; - break; - case iadcCfgReferenceVddX0P8Buf: - refVoltage = 2400; - break; -#if defined(_IADC_CFG_REFSEL_VREFBUF) - case iadcCfgReferenceBuf: - refVoltage = 12500; - break; -#endif -#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) - case iadcCfgReference0P8Buf: - refVoltage = 1000; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - - return refVoltage; -} - -/** @} (end addtogroup iadc) */ -/** @} (end addtogroup emlib) */ -#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_iadc.h" + +#if defined(IADC_COUNT) && (IADC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include + +/***************************************************************************//** + * @addtogroup emlib + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup iadc IADC - Incremental ADC + * @brief Incremental Analog to Digital Converter (IADC) Peripheral API + * @details + * This module contains functions to control the IADC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The IADC is used to convert analog signals into a + * digital representation. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +// Validation of IADC register block pointer reference for assert statements. +#if defined(IADC_NUM) +#define IADC_REF_VALID(ref) (IADC_NUM(ref) != -1) +#else +#if (IADC_COUNT == 1) +#define IADC_REF_VALID(ref) ((ref) == IADC0) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : -1) +#elif (IADC_COUNT == 2) +#define IADC_REF_VALID(ref) (((ref) == IADC0) || ((ref) == IADC1)) +#define IADC_NUM(ref) (((ref) == IADC0) ? 0 : ((ref) == IADC1) ? 1 : -1) +#endif +#endif + +// Max IADC clock rates +#define IADC_CLK_MAX_FREQ 40000000UL +#define IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ 20000000UL +#define IADC_ANA_CLK_NORMAL_MAX_FREQ 10000000UL +#define IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ 5000000UL +#if defined (_IADC_CFG_ADCMODE_HIGHSPEED) +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : ((adcMode) == iadcCfgModeHighSpeed \ + ? IADC_ANA_CLK_HIGH_SPEED_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ) \ + ) +#else +#define IADC_ANA_CLK_MAX_FREQ(adcMode) ( \ + (adcMode) == iadcCfgModeNormal ? IADC_ANA_CLK_NORMAL_MAX_FREQ \ + : IADC_ANA_CLK_HIGH_ACCURACY_MAX_FREQ \ + ) +#endif + +#define IADC_ROUND_D2I(n) (int)((n) < 0.0f ? ((n) - 0.5f) : ((n) + 0.5f)) + +#define IADC0_SCANENTRIES IADC0_ENTRIES +#define IADC0_FIFOENTRIES 0x4UL + +#define IADC1_SCANENTRIES IADC1_ENTRIES +#define IADC1_FIFOENTRIES 0x4UL + +#if defined(IADC_ENTRIES) +#define IADC_SCANENTRIES(iadc) IADC_ENTRIES(IADC_NUM(iadc)) +#else +#define IADC_SCANENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_SCANENTRIES \ + : 0UL) +#endif + +#if !defined(IADC_CONFIGNUM) +#define IADC_CONFIGNUM(iadc) ( \ + (iadc) == 0 ? IADC0_CONFIGNUM \ + : 0UL) +#endif + +#define IADC_FIFOENTRIES(iadc) ( \ + (iadc) == IADC0 ? IADC0_FIFOENTRIES \ + : 0UL) + +#define IADC_CMU_CLOCK(iadc) ( \ + (iadc) == IADC0 ? cmuClock_IADC0 \ + : cmuClock_IADC0) + +/** @endcond */ + +/******************************************************************************* + *************************** LOCAL FUNCTIONS ******************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +static void IADC_disable(IADC_TypeDef *iadc) +{ +#if defined(IADC_STATUS_SYNCBUSY) + while ((iadc->STATUS & IADC_STATUS_SYNCBUSY) != 0U) { + // Wait for synchronization to finish before disable + } +#endif + iadc->EN_CLR = IADC_EN_EN; +#if defined(_IADC_EN_DISABLING_MASK) + while (IADC0->EN & _IADC_EN_DISABLING_MASK) { + } +#endif +} + +static void IADC_enable(IADC_TypeDef *iadc) +{ + iadc->EN_SET = IADC_EN_EN; +} + +static IADC_Result_t IADC_ConvertRawDataToResult(uint32_t rawData, + IADC_Alignment_t alignment) +{ + IADC_Result_t result; + + switch (alignment) { + case iadcAlignRight12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignRight16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignRight20: +#endif + // Mask out ID and replace with sign extension + result.data = (rawData & 0x00FFFFFFUL) + | ((rawData & 0x00800000UL) != 0x0UL ? 0xFF000000UL : 0x0UL); + // Mask out data and shift down + result.id = (uint8_t)((rawData & 0xFF000000UL) >> 24); + break; + + case iadcAlignLeft12: +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT16) + case iadcAlignLeft16: +#endif +#if defined(IADC_SINGLEFIFOCFG_ALIGNMENT_RIGHT20) + case iadcAlignLeft20: +#endif + result.data = rawData & 0xFFFFFF00UL; + result.id = (uint8_t)(rawData & 0x000000FFUL); + break; + default: + break; + } + return result; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize IADC. + * + * @details + * Initializes common parts for both single conversion and scan sequence. + * In addition, single and/or scan control configuration must be done, please + * refer to @ref IADC_initSingle() and @ref IADC_initScan() respectively. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] allConfigs + * Pointer to structure holding all configs. + ******************************************************************************/ +void IADC_init(IADC_TypeDef *iadc, + const IADC_Init_t *init, + const IADC_AllConfigs_t *allConfigs) +{ + uint32_t tmp; + uint32_t config; + uint16_t wantedPrescale; + uint8_t srcClkPrescale; + uint32_t adcClkPrescale; + uint8_t timebase; + unsigned uiAnaGain; + uint16_t uiGainCAna; + IADC_CfgAdcMode_t adcMode; +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + float anaGain; + int anaGainRound; + float offsetAna; + float offset2; + int offsetLong; + int offsetAna1HiAccInt; + uint8_t osrValue; + float offsetAnaBase; + float gainSysHiAcc; + float refVoltage = 0; + // Over sampling ratio for high accuracy conversions + const float osrHiAcc[6] = { 16.0, 32.0, 64.0, 92.0, 128.0, 256.0 }; +#endif + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Calculate min allowed SRC_CLK prescaler setting + srcClkPrescale = IADC_calcSrcClkPrescale(iadc, IADC_CLK_MAX_FREQ, 0); + + wantedPrescale = init->srcClkPrescale; + // Use wanted SRC_CLK prescaler setting instead if it is high enough + if (wantedPrescale >= srcClkPrescale) { + srcClkPrescale = wantedPrescale; + } + + IADC_disable(iadc); + + timebase = init->timebase; + if (timebase == 0) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + uint32_t srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE to obtain valid frequency + if (srcClkFreq >= IADC_CLK_MAX_FREQ) { + srcClkFreq = srcClkFreq / srcClkPrescale; + } + // Calculate timebase based on CMU_IADCCLKCTRL + timebase = IADC_calcTimebase(iadc, srcClkFreq); + } + + tmp = (((uint32_t)(init->warmup) << _IADC_CTRL_WARMUPMODE_SHIFT) + & _IADC_CTRL_WARMUPMODE_MASK) + | (((uint32_t)(timebase) << _IADC_CTRL_TIMEBASE_SHIFT) + & _IADC_CTRL_TIMEBASE_MASK) + | (((uint32_t)(srcClkPrescale) << _IADC_CTRL_HSCLKRATE_SHIFT) + & _IADC_CTRL_HSCLKRATE_MASK); + + if (init->iadcClkSuspend0) { + tmp |= IADC_CTRL_ADCCLKSUSPEND0; + } + if (init->iadcClkSuspend1) { + tmp |= IADC_CTRL_ADCCLKSUSPEND1; + } + if (init->debugHalt) { + tmp |= IADC_CTRL_DBGHALT; + } + iadc->CTRL = tmp; + + iadc->TIMER = ((uint32_t) (init->timerCycles) << _IADC_TIMER_TIMER_SHIFT) + & _IADC_TIMER_TIMER_MASK; + + iadc->CMPTHR = (((uint32_t) (init->greaterThanEqualThres) << _IADC_CMPTHR_ADGT_SHIFT) + & _IADC_CMPTHR_ADGT_MASK) + | (((uint32_t) (init->lessThanEqualThres) << _IADC_CMPTHR_ADLT_SHIFT) + & _IADC_CMPTHR_ADLT_MASK); + + // Write configurations + for (config = 0; config < IADC_CONFIGNUM(IADC_NUM(iadc)); config++) { + // Find min allowed ADC_CLK prescaler setting for given mode + adcMode = allConfigs->configs[config].adcMode; + wantedPrescale = allConfigs->configs[config].adcClkPrescale; + adcClkPrescale = IADC_calcAdcClkPrescale(iadc, + IADC_ANA_CLK_MAX_FREQ(adcMode), + 0, + adcMode, + srcClkPrescale); + + // Use wanted ADC_CLK prescaler setting instead if it is high enough + adcClkPrescale = SL_MAX(adcClkPrescale, wantedPrescale); + + tmp = iadc->CFG[config].CFG & ~(_IADC_CFG_ADCMODE_MASK | _IADC_CFG_OSRHS_MASK + | _IADC_CFG_ANALOGGAIN_MASK | _IADC_CFG_REFSEL_MASK +#if defined(_IADC_CFG_DIGAVG_MASK) + | _IADC_CFG_DIGAVG_MASK +#endif + | _IADC_CFG_TWOSCOMPL_MASK +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | _IADC_CFG_OSRHA_MASK +#endif + ); + iadc->CFG[config].CFG = tmp + | (((uint32_t)(adcMode) << _IADC_CFG_ADCMODE_SHIFT) & _IADC_CFG_ADCMODE_MASK) + | (((uint32_t)(allConfigs->configs[config].osrHighSpeed) << _IADC_CFG_OSRHS_SHIFT) + & _IADC_CFG_OSRHS_MASK) +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + | (((uint32_t)(allConfigs->configs[config].osrHighAccuracy) << _IADC_CFG_OSRHA_SHIFT) + & _IADC_CFG_OSRHA_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].analogGain) << _IADC_CFG_ANALOGGAIN_SHIFT) + & _IADC_CFG_ANALOGGAIN_MASK) + | (((uint32_t)(allConfigs->configs[config].reference) << _IADC_CFG_REFSEL_SHIFT) + & _IADC_CFG_REFSEL_MASK) +#if defined(_IADC_CFG_DIGAVG_MASK) + | (((uint32_t)(allConfigs->configs[config].digAvg) << _IADC_CFG_DIGAVG_SHIFT) + & _IADC_CFG_DIGAVG_MASK) +#endif + | (((uint32_t)(allConfigs->configs[config].twosComplement) << _IADC_CFG_TWOSCOMPL_SHIFT) + & _IADC_CFG_TWOSCOMPL_MASK); + + uiAnaGain = (iadc->CFG[config].CFG & _IADC_CFG_ANALOGGAIN_MASK) >> _IADC_CFG_ANALOGGAIN_SHIFT; + switch (uiAnaGain) { +#if defined(_IADC_CFG_ANALOGGAIN_ANAGAIN0P25) + case iadcCfgAnalogGain0P25x: // 0.25x +#endif + case iadcCfgAnalogGain0P5x: // 0.5x + case iadcCfgAnalogGain1x: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + case iadcCfgAnalogGain2x: // 2x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA2_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA2_SHIFT); + break; + case iadcCfgAnalogGain3x: // 3x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA3_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA3_SHIFT); + break; + case iadcCfgAnalogGain4x: // 4x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN1 & _DEVINFO_IADC0GAIN1_GAINCANA4_MASK) >> _DEVINFO_IADC0GAIN1_GAINCANA4_SHIFT); + break; + default: // 1x + uiGainCAna = (uint16_t)((DEVINFO->IADC0GAIN0 & _DEVINFO_IADC0GAIN0_GAINCANA1_MASK) >> _DEVINFO_IADC0GAIN0_GAINCANA1_SHIFT); + break; + } + + // Gain and offset correction is applied according to adcMode and oversampling rate. + switch (adcMode) { + float offset; + uint32_t scale; + int iOffset, iOsr; + case iadcCfgModeNormal: +#if defined(_IADC_CFG_ADCMODE_HIGHSPEED) + case iadcCfgModeHighSpeed: +#endif + offset = 0.0f; + if (uiAnaGain == iadcCfgAnalogGain2x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT); + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT); + } + } else if (uiAnaGain == iadcCfgAnalogGain3x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 2; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 2; + } + } else if (uiAnaGain == iadcCfgAnalogGain4x) { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 >> _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA2NORM_SHIFT) * 3; + } else { + offset = (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 >> _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA2HISPD_SHIFT) * 3; + } + } + + // Set correct gain correction bitfields in scale variable. + tmp = (uint32_t)uiGainCAna & 0x9FFFU; + scale = tmp << _IADC_SCALE_GAIN13LSB_SHIFT; + if ((tmp & 0x8000U) != 0U) { + scale |= IADC_SCALE_GAIN3MSB; + } + + // Adjust offset according to selected OSR. + iOsr = 1U << (((iadc->CFG[config].CFG & _IADC_CFG_OSRHS_MASK) >> _IADC_CFG_OSRHS_SHIFT) + 1U); + if (iOsr == 2) { + if (adcMode == iadcCfgModeNormal) { + offset += (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL0 & _DEVINFO_IADC0NORMALOFFSETCAL0_OFFSETANA1NORM_MASK); + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL0 & _DEVINFO_IADC0HISPDOFFSETCAL0_OFFSETANA1HISPD_MASK); + } + } else { + if (adcMode == iadcCfgModeNormal) { + offset = (int16_t)(DEVINFO->IADC0NORMALOFFSETCAL1 & _DEVINFO_IADC0NORMALOFFSETCAL1_OFFSETANA3NORM_MASK) - offset; + } else { + offset += (int16_t)(DEVINFO->IADC0HISPDOFFSETCAL1 & _DEVINFO_IADC0HISPDOFFSETCAL1_OFFSETANA3HISPD_MASK) - offset; + } + offset /= iOsr / 2.0f; + offset += (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK); + } + + // Compensate offset according to selected reference voltage. + if (allConfigs->configs[config].reference == iadcCfgReferenceInt1V2) { + // Internal reference voltage (VBGR) depends on the chip revision. + offset *= 1.25f / (IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f); + } else { + offset *= 1.25f / (allConfigs->configs[config].vRef / 1000.0f); + } + + // Compensate offset for systematic offset. + offset = (offset * 4.0f) + (640.0f * (256.0f / iOsr)); + + // Apply gain error correction. + if (scale != 0x80000000U) { + offset = (uiGainCAna / 32768.0f) * (offset + 524288.0f) - 524288.0f; + } + + iOffset = IADC_ROUND_D2I(-offset); + // We only have 18 bits available for OFFSET in SCALE register. + // OFFSET is a 2nd complement number. + if (iOffset > 131071) { // Positive overflow at 0x0001FFFF ? + scale |= 0x1FFFFU; + } else if (iOffset < -131072) { // Negative overflow at 0xFFFE0000 ? + scale |= 0x20000U; + } else { + scale |= (uint32_t)iOffset & 0x3FFFFU; + } + iadc->CFG[config].SCALE = scale; + break; + +#if defined(_IADC_CFG_ADCMODE_HIGHACCURACY) + case iadcCfgModeHighAccuracy: + // Get reference voltage in volts + refVoltage = IADC_getReferenceVoltage(allConfigs->configs[config].reference) / 1000.0f; + + // Get OSR from config register + osrValue = (iadc->CFG[config].CFG & _IADC_CFG_OSRHA_MASK) >> _IADC_CFG_OSRHA_SHIFT; + + // 1. Calculate gain correction + if ((uint32_t)osrHiAcc[osrValue] == 92U) { + // for OSR = 92, gainSysHiAcc = 0.957457 + gainSysHiAcc = 0.957457; + } else { + // for OSR != 92, gainSysHiAcc = OSR/(OSR + 1) + gainSysHiAcc = osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f); + } + anaGain = (float) uiGainCAna / 32768.0f * gainSysHiAcc; + anaGainRound = IADC_ROUND_D2I(32768.0f * anaGain); + IADC0->CFG[config].SCALE &= ~_IADC_SCALE_MASK; + + // Write GAIN3MSB + if ((uint32_t)anaGainRound & 0x8000) { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN100; + } else { + IADC0->CFG[config].SCALE |= IADC_SCALE_GAIN3MSB_GAIN011; + } + // Write GAIN13LSB + IADC0->CFG[config].SCALE |= ((uint32_t)anaGainRound & 0x1FFF) << _IADC_SCALE_GAIN13LSB_SHIFT; + + // Get offset value for high accuracy mode from DEVINFO + offsetAna1HiAccInt = (uint16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANA1HIACC_SHIFT; + + // 2. OSR adjustment + // Get offset from DEVINFO + offsetAnaBase = (int16_t)(DEVINFO->IADC0OFFSETCAL0 & _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_MASK) + >> _DEVINFO_IADC0OFFSETCAL0_OFFSETANABASE_SHIFT; + // 1 << osrValue is the same as pow(2, osrValue) + offsetAna = offsetAnaBase + (offsetAna1HiAccInt) / (1 << osrValue); + + // 3. Reference voltage adjustment + offsetAna = (offsetAna) * (1.25f / refVoltage); + + // 4. Calculate final offset + offset2 = 262144.0f / osrHiAcc[osrValue] / (osrHiAcc[osrValue] + 1.0f) + offsetAna * 4.0f + 524288.0f; + offset2 = (uiGainCAna / 32768.0f * (-1.0f)) * offset2 + 524288.0f; + offsetLong = IADC_ROUND_D2I(offset2); + + // 5. Write offset to scale register + IADC0->CFG[config].SCALE |= (uint32_t)(offsetLong & _IADC_SCALE_OFFSET_MASK); + break; +#endif + default: + // Mode not supported. + EFM_ASSERT(false); + break; + } + iadc->CFG[config].SCHED = ((adcClkPrescale << _IADC_SCHED_PRESCALE_SHIFT) + & _IADC_SCHED_PRESCALE_MASK); + } + IADC_enable(iadc); +} + +/***************************************************************************//** + * @brief + * Initialize IADC scan sequence. + * + * @details + * This function will configure scan mode and set up entries in the scan + * table. The scan table mask can be updated by calling IADC_updateScanMask. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC initialization structure. + * + * @param[in] scanTable + * Pointer to IADC scan table structure. + ******************************************************************************/ +void IADC_initScan(IADC_TypeDef *iadc, + const IADC_InitScan_t *init, + const IADC_ScanTable_t *scanTable) +{ + uint32_t i; + uint32_t tmp; + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + + IADC_disable(iadc); + + iadc->SCANFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SCANFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SCANFIFOCFG_DVL_SHIFT) + & _IADC_SCANFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SCANFIFOCFG_DMAWUFIFOSCAN : 0UL); + + // Clear bitfields for scan conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SCANTRIGSEL_MASK + | _IADC_TRIGGER_SCANTRIGACTION_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SCANTRIGSEL_SHIFT) + & _IADC_TRIGGER_SCANTRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SCANTRIGACTION_SHIFT) + & _IADC_TRIGGER_SCANTRIGACTION_MASK); + + // Write scan table + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = (((uint32_t) (scanTable->entries[i].negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (scanTable->entries[i].posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (scanTable->entries[i].configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (scanTable->entries[i].compare ? IADC_SCAN_CMP : 0UL); + } + + IADC_enable(iadc); + + // Set scan mask + tmp = 0; + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + if (scanTable->entries[i].includeInScan) { + tmp |= (1UL << i) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + } + iadc->MASKREQ = tmp; + + if (init->start) { + IADC_command(iadc, iadcCmdStartScan); + } +} + +/***************************************************************************//** + * @brief + * Initialize single IADC conversion. + * + * @details + * This function will initialize the single conversion and configure the + * single input selection. + * + * @note + * This function will stop any ongoing conversions. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] init + * Pointer to IADC single initialization structure. + * + * @param[in] input + * Pointer to IADC single input selection initialization structure. + ******************************************************************************/ +void IADC_initSingle(IADC_TypeDef *iadc, + const IADC_InitSingle_t *init, + const IADC_SingleInput_t *input) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) + // Errata IADC_E305. Makes sure that DVL is equal or less than 7 entries. + EFM_ASSERT(init->dataValidLevel <= iadcFifoCfgDvl7); +#endif + IADC_disable(iadc); + + iadc->SINGLEFIFOCFG = (((uint32_t) (init->alignment) << _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT) + & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + | (init->showId ? IADC_SINGLEFIFOCFG_SHOWID : 0UL) + | (((uint32_t) (init->dataValidLevel) << _IADC_SINGLEFIFOCFG_DVL_SHIFT) + & _IADC_SINGLEFIFOCFG_DVL_MASK) + | (init->fifoDmaWakeup ? IADC_SINGLEFIFOCFG_DMAWUFIFOSINGLE : 0UL); + + // Clear bitfields for single conversion in IADCn->TRIGGER and set new values + iadc->TRIGGER = (iadc->TRIGGER & ~(_IADC_TRIGGER_SINGLETRIGSEL_MASK + | _IADC_TRIGGER_SINGLETRIGACTION_MASK + | _IADC_TRIGGER_SINGLETAILGATE_MASK)) + | (((uint32_t) (init->triggerSelect) << _IADC_TRIGGER_SINGLETRIGSEL_SHIFT) + & _IADC_TRIGGER_SINGLETRIGSEL_MASK) + | (((uint32_t) (init->triggerAction) << _IADC_TRIGGER_SINGLETRIGACTION_SHIFT) + & _IADC_TRIGGER_SINGLETRIGACTION_MASK) + | (init->singleTailgate ? IADC_TRIGGER_SINGLETAILGATE : 0UL); + + IADC_updateSingleInput(iadc, input); + + IADC_enable(iadc); + + if (init->start) { + IADC_command(iadc, iadcCmdStartSingle); + } +} + +/***************************************************************************//** + * @brief + * Update IADC single input selection. + * + * @details + * This function updates the single input selection. The function can be + * called while single and/or scan conversions are ongoing and the new input + * configuration will take place on the next single conversion. + * + * @note If an even numbered pin is selected for the positive input, the + * negative input must use an odd numbered pin and vice versa. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] input + * Pointer to single input selection structure. + ******************************************************************************/ +void IADC_updateSingleInput(IADC_TypeDef *iadc, + const IADC_SingleInput_t *input) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADCn->SINGLE has WSYNC type and can only be written while enabled + IADC_enable(iadc); + + iadc->SINGLE = (((uint32_t) (input->negInput) << _IADC_SINGLE_PINNEG_SHIFT) + & (_IADC_SINGLE_PORTNEG_MASK | _IADC_SINGLE_PINNEG_MASK)) + | (((uint32_t) (input->posInput) << _IADC_SINGLE_PINPOS_SHIFT) + & (_IADC_SINGLE_PORTPOS_MASK | _IADC_SINGLE_PINPOS_MASK)) + | (((uint32_t) (input->configId) << _IADC_SINGLE_CFG_SHIFT) + & _IADC_SINGLE_CFG_MASK) + | (input->compare ? IADC_SINGLE_CMP : 0UL); + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Set mask of IADC scan table entries to include in scan. + * + * @details + * Set mask of scan table entries to include in next scan. This function + * can be called while scan conversions are ongoing, but the new scan mask + * will take effect once the ongoing scan is completed. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] mask + * Mask of scan table entries to include in scan. + ******************************************************************************/ +void IADC_setScanMask(IADC_TypeDef *iadc, uint32_t mask) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + EFM_ASSERT(mask <= ((1UL << IADC_SCANENTRIES(iadc)) - 1UL)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + iadc->MASKREQ = (mask << _IADC_MASKREQ_MASKREQ_SHIFT) + & _IADC_MASKREQ_MASKREQ_MASK; + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Add/update entry in scan table. + * + * @details + * This function will update or add an entry in the scan table with a specific + * ID. + * + * @note + * This function will stop any ongoing conversions. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] id + * ID of scan table entry to add. + * + * @param[in] entry + * Pointer to scan table entry structure. + ******************************************************************************/ +void IADC_updateScanEntry(IADC_TypeDef *iadc, + uint8_t id, + IADC_ScanTableEntry_t *entry) +{ + bool enabled; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + + enabled = (iadc->EN & IADC_EN_EN) != 0UL; + + // IADC must be disabled to update scan table + IADC_disable(iadc); + + // Update entry in scan table + iadc->SCANTABLE[id].SCAN = (((uint32_t) (entry->negInput) << _IADC_SCAN_PINNEG_SHIFT) + & (_IADC_SCAN_PORTNEG_MASK | _IADC_SCAN_PINNEG_MASK)) + | (((uint32_t) (entry->posInput) << _IADC_SCAN_PINPOS_SHIFT) + & (_IADC_SCAN_PORTPOS_MASK | _IADC_SCAN_PINPOS_MASK)) + | (((uint32_t) (entry->configId) << _IADC_SCAN_CFG_SHIFT) + & _IADC_SCAN_CFG_MASK) + | (entry->compare ? IADC_SCAN_CMP : 0UL); + + // IADC must be enabled to update scan table mask + IADC_enable(iadc); + + if (entry->includeInScan) { + iadc->MASKREQ_SET = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } else { + iadc->MASKREQ_CLR = (1UL << (id & 0x1FUL)) << _IADC_MASKREQ_MASKREQ_SHIFT; + } + + // Restore enabled state + if (!enabled) { + IADC_disable(iadc); + } +} + +/***************************************************************************//** + * @brief + * Reset IADC to same state as after a HW reset. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + ******************************************************************************/ +void IADC_reset(IADC_TypeDef *iadc) +{ + uint32_t i; + EFM_ASSERT(IADC_REF_VALID(iadc)); + + // Write all WSYNC registers to reset value while enabled + IADC_enable(iadc); + + // Stop conversions and timer, before resetting other registers. + iadc->CMD = IADC_CMD_SINGLESTOP | IADC_CMD_SCANSTOP | IADC_CMD_TIMERDIS; + + // Wait for all IADC operations to stop + while ((iadc->STATUS & (IADC_STATUS_CONVERTING + | IADC_STATUS_SCANQUEUEPENDING + | IADC_STATUS_SINGLEQUEUEPENDING + | IADC_STATUS_TIMERACTIVE)) + != 0UL) { + } + + // Reset all WSYNC registers + iadc->MASKREQ = _IADC_MASKREQ_RESETVALUE; + iadc->SINGLE = _IADC_SINGLE_RESETVALUE; + + // Wait for SINGLE and MASQREQ writes to propagate to working registers + while ((iadc->STATUS & (IADC_STATUS_MASKREQWRITEPENDING + | IADC_STATUS_SINGLEWRITEPENDING)) + != 0UL) { + } + + // Pull from FIFOs until they are empty + + // Errata IADC_E305: Check SINGLEFIFOSTAT to make sure that SINGLEFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SINGLEFIFODV) != 0UL) || (iadc->SINGLEFIFOSTAT > 0)) { + (void) IADC_pullSingleFifoData(iadc); + } + + // Errata IADC_E305: check SCANFIFOSTAT to make sure that SCANFIFO is getting emptied in case + // where STATUS register is incorrect. + while (((iadc->STATUS & IADC_STATUS_SCANFIFODV) != 0UL) || (iadc->SCANFIFOSTAT > 0)) { + (void) IADC_pullScanFifoData(iadc); + } + + // Read data registers to clear data valid flags + (void) IADC_readSingleData(iadc); + (void) IADC_readScanData(iadc); + + // Write all WSTATIC registers to reset value while disabled + IADC_disable(iadc); + + // Reset all WSTATIC registers + iadc->CTRL = _IADC_CTRL_RESETVALUE; + iadc->TIMER = _IADC_TIMER_RESETVALUE; + iadc->TRIGGER = _IADC_TRIGGER_RESETVALUE; + + iadc->CMPTHR = _IADC_CMPTHR_RESETVALUE; + iadc->SINGLEFIFOCFG = _IADC_SINGLEFIFOCFG_RESETVALUE; + iadc->SCANFIFOCFG = _IADC_SCANFIFOCFG_RESETVALUE; + + for (i = 0; i < IADC_CONFIGNUM(IADC_NUM(iadc)); i++) { + iadc->CFG[i].CFG = _IADC_CFG_RESETVALUE; + iadc->CFG[i].SCALE = _IADC_SCALE_RESETVALUE; + iadc->CFG[i].SCHED = _IADC_SCHED_RESETVALUE; + } + + for (i = 0; i < IADC_SCANENTRIES(iadc); i++) { + iadc->SCANTABLE[i].SCAN = _IADC_SCAN_RESETVALUE; + } + + // Clear interrupt flags and disable interrupts + IADC_clearInt(iadc, _IADC_IF_MASK); + IADC_disableInt(iadc, _IADC_IEN_MASK); +} + +/***************************************************************************//** + * @brief + * Calculate timebase value in order to get a timebase providing at least 1us. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq Frequency in Hz of reference CLK_SRC_ADC clock. Set to 0 to + * derive srcClkFreq from CLK_CMU_ADC and prescaler HSCLKRATE. + * + * @return + * Timebase value to use for IADC in order to achieve at least 1 us. + ******************************************************************************/ +uint8_t IADC_calcTimebase(IADC_TypeDef *iadc, uint32_t srcClkFreq) +{ + EFM_ASSERT(IADC_REF_VALID(iadc)); + + if (srcClkFreq == 0UL) { + // CLK_SRC_ADC is derived from CLK_CMU_ADC, and must be no faster than 40 MHz. Therefore we set + // srcClkFreq's original value to CLK_CMU_ADC before evaluating the prescaling conditions. + srcClkFreq = CMU_ClockFreqGet(cmuClock_IADC0); + + // Just in case, make sure we get non-zero frequency for below calculation + if (srcClkFreq == 0UL) { + srcClkFreq = 1; + } + // If srcClkFreq is greater than 40MHz, then divide by the prescaler HSCLKRATE + if (srcClkFreq > IADC_CLK_MAX_FREQ) { + uint32_t prescaler = (uint32_t)(IADC0->CTRL & _IADC_CTRL_HSCLKRATE_MASK) >> _IADC_CTRL_HSCLKRATE_SHIFT; + srcClkFreq /= (prescaler + 1); + } + } + + // Determine number of ADCCLK cycle >= 1us + srcClkFreq += 999999UL; + srcClkFreq /= 1000000UL; + + // Convert to N+1 format + srcClkFreq -= 1UL; + + // Limit to max allowed register setting + srcClkFreq = SL_MIN(srcClkFreq, (_IADC_CTRL_TIMEBASE_MASK >> _IADC_CTRL_TIMEBASE_SHIFT)); + + // Return timebase value + return (uint8_t) srcClkFreq; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for CLK_SRC_ADC high speed clock + * + * @details + * The IADC high speed clock is given by: CLK_SRC_ADC / (srcClkPrescaler + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] srcClkFreq CLK_SRC_ADC frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of reference CLK_CMU_ADC. Set to 0 + * to use currently defined CMU clock setting for the IADC. + * + * @return + * Divider value to use for IADC in order to achieve a high speed clock value + * <= @p srcClkFreq. + ******************************************************************************/ +uint8_t IADC_calcSrcClkPrescale(IADC_TypeDef *iadc, + uint32_t srcClkFreq, + uint32_t cmuClkFreq) +{ + uint32_t ret; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(srcClkFreq); + + // Make sure wanted CLK_SRC_ADC clock is below max allowed frequency + srcClkFreq = SL_MIN(srcClkFreq, IADC_CLK_MAX_FREQ); + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + cmuClkFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } + + ret = (cmuClkFreq + srcClkFreq - 1UL) / srcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + if (ret > _IADC_CTRL_HSCLKRATE_DIV4) { + ret = _IADC_CTRL_HSCLKRATE_DIV4; + } + + return (uint8_t)ret; +} + +/***************************************************************************//** + * @brief + * Calculate prescaler for ADC_CLK clock. + * + * @details + * The ADC_CLK is given by: CLK_SRC_ADC / (adcClkprescale + 1). + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @param[in] adcClkFreq ADC_CLK frequency wanted. The frequency will + * automatically be adjusted to be within valid range according to reference + * manual. + * + * @param[in] cmuClkFreq Frequency in Hz of CLK_CMU_ADC Set to 0 to + * use currently defined IADC clock setting (in CMU). + * + * @param[in] adcMode Mode for IADC config. + * + * @param[in] srcClkPrescaler Precaler setting for ADC_CLK + * + * @return + * Divider value to use for IADC in order to achieve a ADC_CLK frequency + * <= @p adcClkFreq. + ******************************************************************************/ +uint32_t IADC_calcAdcClkPrescale(IADC_TypeDef *iadc, + uint32_t adcClkFreq, + uint32_t cmuClkFreq, + IADC_CfgAdcMode_t adcMode, + uint8_t srcClkPrescaler) +{ + uint32_t ret; + uint32_t resFreq; + + EFM_ASSERT(IADC_REF_VALID(iadc)); + EFM_ASSERT(adcClkFreq); + + // Make sure wanted analog clock is below max allowed frequency for the given + // mode. + if (adcClkFreq > IADC_ANA_CLK_MAX_FREQ(adcMode)) { + adcClkFreq = IADC_ANA_CLK_MAX_FREQ(adcMode); + } + + // Use current CLK_CMU_ADC frequency? + if (cmuClkFreq == 0UL) { + resFreq = CMU_ClockFreqGet(IADC_CMU_CLOCK(iadc)); + } else { + resFreq = cmuClkFreq; + } + + // Apply CLK_SRC_ADC prescaler + resFreq /= srcClkPrescaler + 1UL; + + ret = (resFreq + adcClkFreq - 1UL) / adcClkFreq; + if (ret != 0UL) { + ret--; + } + + // Limit to max allowed register setting + ret = SL_MIN(ret, (_IADC_SCHED_PRESCALE_MASK >> _IADC_SCHED_PRESCALE_SHIFT)); + + return (uint16_t)ret; +} + +/***************************************************************************//** + * @brief + * Pull result from single data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing single mode. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullSingleFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent single conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing single mode. + * Calling this function will not affect the state of the single data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Single conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readSingleResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SINGLEFIFOCFG & _IADC_SINGLEFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SINGLEFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SINGLEDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Pull result from scan data FIFO. The result struct includes both the data + * and the ID (0x20) if showId was set when initializing scan entry. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_pullScanFifoResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANFIFODATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Read most recent scan conversion result. The result struct includes both + * the data and the ID (0x20) if showId was set when initializing scan entry. + * Calling this function will not affect the state of the scan data FIFO. + * + * @note + * Check data valid flag before calling this function. + * + * @param[in] iadc + * Pointer to IADC peripheral register block. + * + * @return + * Scan conversion result struct holding data and id. + ******************************************************************************/ +IADC_Result_t IADC_readScanResult(IADC_TypeDef *iadc) +{ + uint32_t alignment = (iadc->SCANFIFOCFG & _IADC_SCANFIFOCFG_ALIGNMENT_MASK) + >> _IADC_SCANFIFOCFG_ALIGNMENT_SHIFT; + return IADC_ConvertRawDataToResult(iadc->SCANDATA, + (IADC_Alignment_t) alignment); +} + +/***************************************************************************//** + * @brief + * Get reference voltage selection. + * + * @param[in] reference + * IADC Reference selection. + * + * @return + * IADC reference voltage in millivolts. + ******************************************************************************/ +uint32_t IADC_getReferenceVoltage(IADC_CfgReference_t reference) +{ + uint32_t refVoltage = 0; + // Get chip revision + SYSTEM_ChipRevision_TypeDef chipRev; + SYSTEM_ChipRevisionGet(&chipRev); + switch (reference) { + case iadcCfgReferenceInt1V2: +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + if (chipRev.major == 1UL) { + refVoltage = 1210; + } else { + refVoltage = 1180; + } +#else + refVoltage = 1210; +#endif + break; + case iadcCfgReferenceExt1V25: + refVoltage = 1250; + break; +#if defined(_IADC_CFG_REFSEL_VREF2P5) + case iadcCfgReferenceExt2V5: + refVoltage = 2500; + break; +#endif + case iadcCfgReferenceVddx: + refVoltage = 3000; + break; + case iadcCfgReferenceVddX0P8Buf: + refVoltage = 2400; + break; +#if defined(_IADC_CFG_REFSEL_VREFBUF) + case iadcCfgReferenceBuf: + refVoltage = 12500; + break; +#endif +#if defined(_IADC_CFG_REFSEL_VREF0P8BUF) + case iadcCfgReference0P8Buf: + refVoltage = 1000; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + + return refVoltage; +} + +/** @} (end addtogroup iadc) */ +/** @} (end addtogroup emlib) */ +#endif /* defined(IADC_COUNT) && (IADC_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c index 2754046..d19c76a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_ldma.c @@ -1,498 +1,498 @@ -/***************************************************************************//** - * @file - * @brief Direct memory access (LDMA) module peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_ldma.h" - -#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) - -#include -#include "sl_assert.h" -#include "em_bus.h" -#include "em_cmu.h" -#include "em_core.h" - -/***************************************************************************//** - * @addtogroup ldma - * @{ - ******************************************************************************/ - -#if defined(LDMA_IRQ_HANDLER_TEMPLATE) -/***************************************************************************//** - * @brief - * A template for an LDMA IRQ handler. - ******************************************************************************/ -void LDMA_IRQHandler(void) -{ - uint32_t ch; - /* Get all pending and enabled interrupts. */ - uint32_t pending = LDMA_IntGetEnabled(); - - /* Loop on an LDMA error to enable debugging. */ - while (pending & LDMA_IF_ERROR) { - } - - /* Iterate over all LDMA channels. */ - for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { - uint32_t mask = 0x1 << ch; - if (pending & mask) { - /* Clear the interrupt flag. */ - LDMA->IFC = mask; - - /* Perform more actions here, execute callbacks, and so on. */ - } - } -} -#endif - -/***************************************************************************//** - * @brief - * De-initialize the LDMA controller. - * - * LDMA interrupts are disabled and the LDMA clock is stopped. - ******************************************************************************/ -void LDMA_DeInit(void) -{ - NVIC_DisableIRQ(LDMA_IRQn); - LDMA->IEN = 0; -#if defined(_LDMA_CHDIS_MASK) - LDMA->CHDIS = _LDMA_CHEN_MASK; -#else - LDMA->CHEN = 0; -#endif -#if defined(LDMA_EN_EN) - LDMA->EN = 0; -#if defined(LDMA_EN_DISABLING) - while (LDMA->EN & _LDMA_EN_DISABLING_MASK) { - } -#endif -#endif - - CMU_ClockEnable(cmuClock_LDMA, false); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - CMU_ClockEnable(cmuClock_LDMAXBAR, false); -#endif -} - -/***************************************************************************//** - * @brief - * Enable or disable an LDMA channel request. - * - * @details - * Use this function to enable or disable an LDMA channel request. This will - * prevent the LDMA from proceeding after its current transaction if disabled. - * - * @param[in] ch - * LDMA channel to enable or disable requests. - * - * @param[in] enable - * If 'true', the request will be enabled. If 'false', the request will be disabled. - ******************************************************************************/ -void LDMA_EnableChannelRequest(int ch, bool enable) -{ - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - - BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); -} - -/***************************************************************************//** - * @brief - * Initialize the LDMA controller. - * - * @details - * This function will disable all the LDMA channels and enable the LDMA bus - * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC - * and set the LDMA IRQ priority to a user-configurable priority. The LDMA - * interrupt priority is configured using the @ref LDMA_Init_t structure. - * - * @note - * Since this function enables the LDMA IRQ, always add a custom - * LDMA_IRQHandler to the application to handle any interrupts - * from LDMA. - * - * @param[in] init - * A pointer to the initialization structure used to configure the LDMA. - ******************************************************************************/ -void LDMA_Init(const LDMA_Init_t *init) -{ - uint32_t ldmaCtrlVal; - EFM_ASSERT(init != NULL); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) - & ~_LDMA_CTRL_NUMFIXED_MASK)); - -#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - -#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#endif - - EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); - - CMU_ClockEnable(cmuClock_LDMA, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) - CMU_ClockEnable(cmuClock_LDMAXBAR, true); -#endif - -#if defined(LDMA_EN_EN) - LDMA->EN = LDMA_EN_EN; -#endif - - ldmaCtrlVal = (uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; - -#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); -#endif - - LDMA->CTRL = ldmaCtrlVal; - -#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - LDMA->SYNCHWEN = ((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); -#endif - -#if defined(_LDMA_CHDIS_MASK) - LDMA->CHDIS = _LDMA_CHEN_MASK; -#else - LDMA->CHEN = 0; -#endif - LDMA->DBGHALT = 0; - LDMA->REQDIS = 0; - - /* Enable the LDMA error interrupt. */ - LDMA->IEN = LDMA_IEN_ERROR; -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = 0xFFFFFFFFU; -#else - LDMA->IFC = 0xFFFFFFFFU; -#endif - NVIC_ClearPendingIRQ(LDMA_IRQn); - - /* Range is 0-7, where 0 is the highest priority. */ - NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); - - NVIC_EnableIRQ(LDMA_IRQn); -} - -/***************************************************************************//** - * @brief - * Start a DMA transfer. - * - * @param[in] ch - * A DMA channel. - * - * @param[in] transfer - * The initialization structure used to configure the transfer. - * - * @param[in] descriptor - * The transfer descriptor, which can be an array of descriptors linked together. - * Each descriptor's fields stored in RAM will be loaded into the certain - * hardware registers at the proper time to perform the DMA transfer. - ******************************************************************************/ -void LDMA_StartTransfer(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_Descriptor_t *descriptor) -{ -#if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - uint32_t tmp; -#endif - CORE_DECLARE_IRQ_STATE; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - EFM_ASSERT(transfer != NULL); - -#if defined (_LDMAXBAR_CH_REQSEL_MASK) - EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); -#elif defined (_LDMA_CH_REQSEL_MASK) - EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); -#endif - -#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); -#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) - & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); -#endif - - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) - & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) - & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) - & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); - EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) - & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); - - /* Clear the pending channel interrupt. */ -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chMask; -#else - LDMA->IFC = chMask; -#endif - -#if defined(LDMAXBAR) - LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; -#else - LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; -#endif - LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; - LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) - | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) - | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) -#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) - | (transfer->ldmaCfgStructBusPort << _LDMA_CH_CFG_STRUCTBUSPORT_SHIFT) - | (transfer->ldmaCfgSrcBusPort << _LDMA_CH_CFG_SRCBUSPORT_SHIFT) - | (transfer->ldmaCfgDstBusPort << _LDMA_CH_CFG_DSTBUSPORT_SHIFT) -#endif - ; - - /* Set the descriptor address. */ - LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; - - /* A critical region. */ - CORE_ENTER_ATOMIC(); - - /* Enable the channel interrupt. */ - LDMA->IEN |= chMask; - - if (transfer->ldmaReqDis) { - LDMA->REQDIS |= chMask; - } - - if (transfer->ldmaDbgHalt) { - LDMA->DBGHALT |= chMask; - } - -#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) - - LDMA->SYNCHWEN_CLR = - (((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - & _LDMA_SYNCHWEN_MASK; - - LDMA->SYNCHWEN_SET = - (((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) - | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) - & _LDMA_SYNCHWEN_MASK; - -#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) - - tmp = LDMA->CTRL; - - if (transfer->ldmaCtrlSyncPrsClrOff) { - tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK - | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); - } - - if (transfer->ldmaCtrlSyncPrsClrOn) { - tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; - } - - if (transfer->ldmaCtrlSyncPrsSetOff) { - tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK - | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); - } - - if (transfer->ldmaCtrlSyncPrsSetOn) { - tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; - } - - LDMA->CTRL = tmp; - -#else - - #error "SYNC Set and SYNC Clear not defined" - -#endif - - BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ - LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ - - /* A critical region end. */ - CORE_EXIT_ATOMIC(); -} - -#if defined(_LDMA_CH_CTRL_EXTEND_MASK) -/***************************************************************************//** - * @brief - * Start an extended DMA transfer. - * - * @param[in] ch - * A DMA channel. - * - * @param[in] transfer - * The initialization structure used to configure the transfer. - * - * @param[in] descriptor_ext - * The extended transfer descriptor, which can be an array of descriptors - * linked together. Each descriptor's fields stored in RAM will be loaded - * into the certain hardware registers at the proper time to perform the DMA - * transfer. - ******************************************************************************/ -void LDMA_StartTransferExtend(int ch, - const LDMA_TransferCfg_t *transfer, - const LDMA_DescriptorExtend_t *descriptor_ext) -{ - // Ensure destination interleaving supported for given channel. - EFM_ASSERT(((1 << ch) & LDMA_ILCHNL)); - - LDMA_StartTransfer(ch, - transfer, - (const LDMA_Descriptor_t *)descriptor_ext); -} -#endif - -/***************************************************************************//** - * @brief - * Stop a DMA transfer. - * - * @note - * The DMA will complete the current AHB burst transfer before stopping. - * - * @param[in] ch - * A DMA channel to stop. - ******************************************************************************/ -void LDMA_StopTransfer(int ch) -{ - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - -#if defined(_LDMA_CHDIS_MASK) - CORE_ATOMIC_SECTION( - LDMA->IEN &= ~chMask; - LDMA->CHDIS = chMask; - ) -#else - CORE_ATOMIC_SECTION( - LDMA->IEN &= ~chMask; - BUS_RegMaskedClear(&LDMA->CHEN, chMask); - ) -#endif -} - -/***************************************************************************//** - * @brief - * Check if a DMA transfer has completed. - * - * @param[in] ch - * A DMA channel to check. - * - * @return - * True if transfer has completed, false if not. - ******************************************************************************/ -bool LDMA_TransferDone(int ch) -{ - bool retVal = false; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - -#if defined(_LDMA_CHSTATUS_MASK) - CORE_ATOMIC_SECTION( - if (((LDMA->CHSTATUS & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { - retVal = true; - } - ) -#else - CORE_ATOMIC_SECTION( - if (((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { - retVal = true; - } - ) -#endif - - return retVal; -} - -/***************************************************************************//** - * @brief - * Get the number of items remaining in a transfer. - * - * @note - * This function does not take into account that a DMA transfer with - * a chain of linked transfers might be ongoing. It will only check the - * count for the current transfer. - * - * @param[in] ch - * The channel number of the transfer to check. - * - * @return - * A number of items remaining in the transfer. - ******************************************************************************/ -uint32_t LDMA_TransferRemainingCount(int ch) -{ - uint32_t remaining, done, iflag; - uint32_t chMask = 1UL << (uint8_t)ch; - - EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); - - CORE_ATOMIC_SECTION( - iflag = LDMA->IF; - done = LDMA->CHDONE; - remaining = LDMA->CH[ch].CTRL; - ) - - iflag &= chMask; - done &= chMask; - remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) - >> _LDMA_CH_CTRL_XFERCNT_SHIFT; - - if (done || ((remaining == 0) && iflag)) { - return 0; - } - - /* +1 because XFERCNT is 0-based. */ - return remaining + 1; -} - -/** @} (end addtogroup ldma) */ -#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ +/***************************************************************************//** + * @file + * @brief Direct memory access (LDMA) module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_ldma.h" + +#if defined(LDMA_PRESENT) && (LDMA_COUNT == 1) + +#include +#include "sl_assert.h" +#include "em_bus.h" +#include "em_cmu.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup ldma + * @{ + ******************************************************************************/ + +#if defined(LDMA_IRQ_HANDLER_TEMPLATE) +/***************************************************************************//** + * @brief + * A template for an LDMA IRQ handler. + ******************************************************************************/ +void LDMA_IRQHandler(void) +{ + uint32_t ch; + /* Get all pending and enabled interrupts. */ + uint32_t pending = LDMA_IntGetEnabled(); + + /* Loop on an LDMA error to enable debugging. */ + while (pending & LDMA_IF_ERROR) { + } + + /* Iterate over all LDMA channels. */ + for (ch = 0; ch < DMA_CHAN_COUNT; ch++) { + uint32_t mask = 0x1 << ch; + if (pending & mask) { + /* Clear the interrupt flag. */ + LDMA->IFC = mask; + + /* Perform more actions here, execute callbacks, and so on. */ + } + } +} +#endif + +/***************************************************************************//** + * @brief + * De-initialize the LDMA controller. + * + * LDMA interrupts are disabled and the LDMA clock is stopped. + ******************************************************************************/ +void LDMA_DeInit(void) +{ + NVIC_DisableIRQ(LDMA_IRQn); + LDMA->IEN = 0; +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif +#if defined(LDMA_EN_EN) + LDMA->EN = 0; +#if defined(LDMA_EN_DISABLING) + while (LDMA->EN & _LDMA_EN_DISABLING_MASK) { + } +#endif +#endif + + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +} + +/***************************************************************************//** + * @brief + * Enable or disable an LDMA channel request. + * + * @details + * Use this function to enable or disable an LDMA channel request. This will + * prevent the LDMA from proceeding after its current transaction if disabled. + * + * @param[in] ch + * LDMA channel to enable or disable requests. + * + * @param[in] enable + * If 'true', the request will be enabled. If 'false', the request will be disabled. + ******************************************************************************/ +void LDMA_EnableChannelRequest(int ch, bool enable) +{ + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + BUS_RegBitWrite(&LDMA->REQDIS, ch, !enable); +} + +/***************************************************************************//** + * @brief + * Initialize the LDMA controller. + * + * @details + * This function will disable all the LDMA channels and enable the LDMA bus + * clock in the CMU. This function will also enable the LDMA IRQ in the NVIC + * and set the LDMA IRQ priority to a user-configurable priority. The LDMA + * interrupt priority is configured using the @ref LDMA_Init_t structure. + * + * @note + * Since this function enables the LDMA IRQ, always add a custom + * LDMA_IRQHandler to the application to handle any interrupts + * from LDMA. + * + * @param[in] init + * A pointer to the initialization structure used to configure the LDMA. + ******************************************************************************/ +void LDMA_Init(const LDMA_Init_t *init) +{ + uint32_t ldmaCtrlVal; + EFM_ASSERT(init != NULL); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT) + & ~_LDMA_CTRL_NUMFIXED_MASK)); + +#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); +#endif + +#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); +#endif + + EFM_ASSERT(init->ldmaInitIrqPriority < (1 << __NVIC_PRIO_BITS)); + + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif + +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + + ldmaCtrlVal = (uint32_t)init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT; + +#if defined(_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + ldmaCtrlVal |= (init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + | (init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); +#endif + + LDMA->CTRL = ldmaCtrlVal; + +#if defined(_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + LDMA->SYNCHWEN = ((uint32_t)init->ldmaInitCtrlSyncPrsClrEn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)init->ldmaInitCtrlSyncPrsSetEn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT); +#endif + +#if defined(_LDMA_CHDIS_MASK) + LDMA->CHDIS = _LDMA_CHEN_MASK; +#else + LDMA->CHEN = 0; +#endif + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Enable the LDMA error interrupt. */ + LDMA->IEN = LDMA_IEN_ERROR; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = 0xFFFFFFFFU; +#else + LDMA->IFC = 0xFFFFFFFFU; +#endif + NVIC_ClearPendingIRQ(LDMA_IRQn); + + /* Range is 0-7, where 0 is the highest priority. */ + NVIC_SetPriority(LDMA_IRQn, init->ldmaInitIrqPriority); + + NVIC_EnableIRQ(LDMA_IRQn); +} + +/***************************************************************************//** + * @brief + * Start a DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor + * The transfer descriptor, which can be an array of descriptors linked together. + * Each descriptor's fields stored in RAM will be loaded into the certain + * hardware registers at the proper time to perform the DMA transfer. + ******************************************************************************/ +void LDMA_StartTransfer(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_Descriptor_t *descriptor) +{ +#if !(defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + uint32_t tmp; +#endif + CORE_DECLARE_IRQ_STATE; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + EFM_ASSERT(transfer != NULL); + +#if defined (_LDMAXBAR_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMAXBAR_CH_REQSEL_MASK)); +#elif defined (_LDMA_CH_REQSEL_MASK) + EFM_ASSERT(!(transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK)); +#endif + +#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + & ~_LDMA_SYNCHWEN_SYNCSETEN_MASK)); +#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSCLREN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT) + & ~_LDMA_CTRL_SYNCPRSSETEN_MASK)); +#endif + + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + & ~_LDMA_CH_CFG_ARBSLOTS_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_SRCINCSIGN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) + & ~_LDMA_CH_CFG_DSTINCSIGN_MASK)); + EFM_ASSERT(!(((uint32_t)transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT) + & ~_LDMA_CH_LOOP_LOOPCNT_MASK)); + + /* Clear the pending channel interrupt. */ +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + +#if defined(LDMAXBAR) + LDMAXBAR->CH[ch].REQSEL = transfer->ldmaReqSel; +#else + LDMA->CH[ch].REQSEL = transfer->ldmaReqSel; +#endif + LDMA->CH[ch].LOOP = transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT; + LDMA->CH[ch].CFG = (transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT) + | (transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT) + | (transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT) +#if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK) + | (transfer->ldmaCfgStructBusPort << _LDMA_CH_CFG_STRUCTBUSPORT_SHIFT) + | (transfer->ldmaCfgSrcBusPort << _LDMA_CH_CFG_SRCBUSPORT_SHIFT) + | (transfer->ldmaCfgDstBusPort << _LDMA_CH_CFG_DSTBUSPORT_SHIFT) +#endif + ; + + /* Set the descriptor address. */ + LDMA->CH[ch].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK; + + /* A critical region. */ + CORE_ENTER_ATOMIC(); + + /* Enable the channel interrupt. */ + LDMA->IEN |= chMask; + + if (transfer->ldmaReqDis) { + LDMA->REQDIS |= chMask; + } + + if (transfer->ldmaDbgHalt) { + LDMA->DBGHALT |= chMask; + } + +#if defined (_LDMA_SYNCHWEN_SYNCCLREN_SHIFT) && defined (_LDMA_SYNCHWEN_SYNCSETEN_SHIFT) + + LDMA->SYNCHWEN_CLR = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOff << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOff << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + + LDMA->SYNCHWEN_SET = + (((uint32_t)transfer->ldmaCtrlSyncPrsClrOn << _LDMA_SYNCHWEN_SYNCCLREN_SHIFT) + | ((uint32_t)transfer->ldmaCtrlSyncPrsSetOn << _LDMA_SYNCHWEN_SYNCSETEN_SHIFT)) + & _LDMA_SYNCHWEN_MASK; + +#elif defined (_LDMA_CTRL_SYNCPRSCLREN_SHIFT) && defined (_LDMA_CTRL_SYNCPRSSETEN_SHIFT) + + tmp = LDMA->CTRL; + + if (transfer->ldmaCtrlSyncPrsClrOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK + | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsClrOn) { + tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT; + } + + if (transfer->ldmaCtrlSyncPrsSetOff) { + tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK + | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT); + } + + if (transfer->ldmaCtrlSyncPrsSetOn) { + tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT; + } + + LDMA->CTRL = tmp; + +#else + + #error "SYNC Set and SYNC Clear not defined" + +#endif + + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); /* Clear the done flag. */ + LDMA->LINKLOAD = chMask; /* Start a transfer by loading the descriptor. */ + + /* A critical region end. */ + CORE_EXIT_ATOMIC(); +} + +#if defined(_LDMA_CH_CTRL_EXTEND_MASK) +/***************************************************************************//** + * @brief + * Start an extended DMA transfer. + * + * @param[in] ch + * A DMA channel. + * + * @param[in] transfer + * The initialization structure used to configure the transfer. + * + * @param[in] descriptor_ext + * The extended transfer descriptor, which can be an array of descriptors + * linked together. Each descriptor's fields stored in RAM will be loaded + * into the certain hardware registers at the proper time to perform the DMA + * transfer. + ******************************************************************************/ +void LDMA_StartTransferExtend(int ch, + const LDMA_TransferCfg_t *transfer, + const LDMA_DescriptorExtend_t *descriptor_ext) +{ + // Ensure destination interleaving supported for given channel. + EFM_ASSERT(((1 << ch) & LDMA_ILCHNL)); + + LDMA_StartTransfer(ch, + transfer, + (const LDMA_Descriptor_t *)descriptor_ext); +} +#endif + +/***************************************************************************//** + * @brief + * Stop a DMA transfer. + * + * @note + * The DMA will complete the current AHB burst transfer before stopping. + * + * @param[in] ch + * A DMA channel to stop. + ******************************************************************************/ +void LDMA_StopTransfer(int ch) +{ + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHDIS_MASK) + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + LDMA->CHDIS = chMask; + ) +#else + CORE_ATOMIC_SECTION( + LDMA->IEN &= ~chMask; + BUS_RegMaskedClear(&LDMA->CHEN, chMask); + ) +#endif +} + +/***************************************************************************//** + * @brief + * Check if a DMA transfer has completed. + * + * @param[in] ch + * A DMA channel to check. + * + * @return + * True if transfer has completed, false if not. + ******************************************************************************/ +bool LDMA_TransferDone(int ch) +{ + bool retVal = false; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + +#if defined(_LDMA_CHSTATUS_MASK) + CORE_ATOMIC_SECTION( + if (((LDMA->CHSTATUS & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#else + CORE_ATOMIC_SECTION( + if (((LDMA->CHEN & chMask) == 0) && ((LDMA->CHDONE & chMask) == chMask)) { + retVal = true; + } + ) +#endif + + return retVal; +} + +/***************************************************************************//** + * @brief + * Get the number of items remaining in a transfer. + * + * @note + * This function does not take into account that a DMA transfer with + * a chain of linked transfers might be ongoing. It will only check the + * count for the current transfer. + * + * @param[in] ch + * The channel number of the transfer to check. + * + * @return + * A number of items remaining in the transfer. + ******************************************************************************/ +uint32_t LDMA_TransferRemainingCount(int ch) +{ + uint32_t remaining, done, iflag; + uint32_t chMask = 1UL << (uint8_t)ch; + + EFM_ASSERT(ch < (int)DMA_CHAN_COUNT); + + CORE_ATOMIC_SECTION( + iflag = LDMA->IF; + done = LDMA->CHDONE; + remaining = LDMA->CH[ch].CTRL; + ) + + iflag &= chMask; + done &= chMask; + remaining = (remaining & _LDMA_CH_CTRL_XFERCNT_MASK) + >> _LDMA_CH_CTRL_XFERCNT_SHIFT; + + if (done || ((remaining == 0) && iflag)) { + return 0; + } + + /* +1 because XFERCNT is 0-based. */ + return remaining + 1; +} + +/** @} (end addtogroup ldma) */ +#endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c index 230b80a..5abc6f2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_letimer.c @@ -1,685 +1,685 @@ -/***************************************************************************//** - * @file - * @brief Low Energy Timer (LETIMER) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_letimer.h" -#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) -#include "em_cmu.h" -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup letimer LETIMER - Low Energy Timer - * @brief Low Energy Timer (LETIMER) Peripheral API - * @details - * This module contains functions to control the LETIMER peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track - * of time and output configurable waveforms. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** A validation of the valid comparator register for assert statements. */ -#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) - -/** A validation of the LETIMER register block pointer reference for assert statements. */ -#if (LETIMER_COUNT == 1) -#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) -#elif (LETIMER_COUNT == 2) -#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) -#else -#error Undefined number of analog comparators (ACMP). -#endif - -/** A validation of the valid repeat counter register for assert statements. */ -#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. - * - * @note - * See the reference manual chapter about Access to Low Energy Peripherals - * (Asynchronos Registers) for details. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] mask - * A bitmask corresponding to SYNCBUSY register defined bits, indicating - * registers that must complete any ongoing synchronization. - ******************************************************************************/ -__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) -{ -#if defined(_LETIMER_FREEZE_MASK) - /* Avoid a deadlock if modifying the same register twice when freeze mode is */ - /* activated. */ - if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { - return; - } -#endif - - /* Wait for any pending write operation to complete. */ - while (letimer->SYNCBUSY & mask) { - } -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the LETIMER compare register value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] comp - * A compare register to get, either 0 or 1. - * - * @return - * A compare register value, 0 if invalid register selected. - ******************************************************************************/ -uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) -{ - uint32_t ret; - - EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); - - /* Initialize the selected compare value. */ - switch (comp) { - case 0: -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - ret = letimer->COMP0; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_COMP1) - regSync(letimer, LETIMER_SYNCBUSY_COMP1); -#endif - ret = letimer->COMP1; - break; - - default: - /* An unknown compare register selected. */ - ret = 0; - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Get LETIMER counter value. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @return - * Current LETIMER counter value. - ******************************************************************************/ -uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) -{ -#if defined(LETIMER_SYNCBUSY_CNT) - regSync(letimer, LETIMER_SYNCBUSY_CNT); -#endif - return letimer->CNT; -} - -#if !defined(_EFM32_GECKO_FAMILY) -/***************************************************************************//** - * @brief - * Set LETIMER counter value. - * - * @param[in] letimer - * Pointer to the LETIMER peripheral register block. - * - * @param[in] value - * New counter value. - ******************************************************************************/ -void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value) -{ -#if defined(LETIMER_SYNCBUSY_CNT) - regSync(letimer, LETIMER_SYNCBUSY_CNT); -#endif - letimer->CNT = value; -} -#endif - -/***************************************************************************//** - * @brief - * Set the LETIMER compare register value. - * - * @note - * The setting of a compare register requires synchronization into the - * low frequency domain. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. This only applies to the Gecko Family. See - * comments in the LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] comp - * A compare register to set, either 0 or 1. - * - * @param[in] value - * An initialization value (<= 0x0000ffff). - ******************************************************************************/ -void LETIMER_CompareSet(LETIMER_TypeDef *letimer, - unsigned int comp, - uint32_t value) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer) - && LETIMER_COMP_REG_VALID(comp) - && ((value & ~(_LETIMER_COMP0_COMP0_MASK - >> _LETIMER_COMP0_COMP0_SHIFT)) - == 0)); - - /* Initialize the selected compare value. */ - switch (comp) { - case 0: -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - letimer->COMP0 = value; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_COMP1) - regSync(letimer, LETIMER_SYNCBUSY_COMP1); -#endif - letimer->COMP1 = value; - break; - - default: - /* An unknown compare register selected, abort. */ - break; - } -} - -/***************************************************************************//** - * @brief - * Start/stop LETIMER. - * - * @note - * The enabling/disabling of the LETIMER modifies the LETIMER CMD register - * which requires synchronization into the low-frequency domain. If this - * register is modified before a previous update to the same register has - * completed, this function will stall until the previous synchronization has - * completed. This only applies to the Gecko Family. See comments in the - * LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] enable - * True to enable counting, false to disable. - ******************************************************************************/ -void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer)); - -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) - regSync(letimer, LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START); -#endif - - if (enable) { - letimer->CMD = LETIMER_CMD_START; - } else { - letimer->CMD = LETIMER_CMD_STOP; - } -} - -#if defined(_LETIMER_FREEZE_MASK) -/***************************************************************************//** - * @brief - * LETIMER register synchronization freeze control. - * - * @details - * Some LETIMER registers require synchronization into the low-frequency (LF) - * domain. The freeze feature allows for several such registers to be - * modified before passing them to the LF domain simultaneously (which - * takes place when the freeze mode is disabled). - * - * @note - * When enabling freeze mode, this function will wait for all current - * ongoing LETIMER synchronization to the LF domain to complete (Normally - * synchronization will not be in progress.) However, for this reason, when - * using freeze mode, modifications of registers requiring the LF synchronization - * should be done within one freeze enable/disable block to avoid unecessary - * stalling. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] enable - * @li True - enable freeze, modified registers are not propagated to the - * LF domain - * @li False - disables freeze, modified registers are propagated to the LF - * domain - ******************************************************************************/ -void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) -{ - if (enable) { - /* - * Wait for any ongoing LF synchronization to complete to - * protect against the rare case when a user - * - modifies a register requiring LF sync - * - then enables freeze before LF sync completed - * - then modifies the same register again - * since modifying a register while it is in sync progress should be - * avoided. - */ - while (letimer->SYNCBUSY) { - } - - letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; - } else { - letimer->FREEZE = 0; - } -} -#endif /* defined(_LETIMER_FREEZE_MASK) */ - -/***************************************************************************//** - * @brief - * Initialize LETIMER. - * - * @details - * Note that the compare/repeat values must be set separately with - * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done - * prior using this function if configuring the LETIMER to start when - * initialization is complete. - * - * @note - * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers - * which require synchronization into the low-frequency domain. If any of those - * registers are modified before a previous update to the same register has - * completed, this function will stall until the previous synchronization has - * completed. This only applies to the Gecko Family. See comments in the - * LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] init - * A pointer to the LETIMER initialization structure. - ******************************************************************************/ -void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) -{ - uint32_t tmp = 0; - - EFM_ASSERT(LETIMER_REF_VALID(letimer)); - -#if defined (LETIMER_EN_EN) - letimer->EN_SET = LETIMER_EN_EN; -#endif - - /* Stop the timer if specified to be disabled and running. */ - if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined(LETIMER_SYNCBUSY_STOP) - regSync(letimer, LETIMER_SYNCBUSY_STOP); -#endif - letimer->CMD = LETIMER_CMD_STOP; - } - - /* Configure the DEBUGRUN flag, which sets whether or not the counter should be - * updated when the debugger is active. */ - if (init->debugRun) { - tmp |= LETIMER_CTRL_DEBUGRUN; - } - -#if defined(LETIMER_CTRL_RTCC0TEN) - if (init->rtcComp0Enable) { - tmp |= LETIMER_CTRL_RTCC0TEN; - } - - if (init->rtcComp1Enable) { - tmp |= LETIMER_CTRL_RTCC1TEN; - } -#endif - - if ((init->comp0Top) || (init->topValue != 0U)) { -#if defined (LETIMER_CTRL_COMP0TOP) - tmp |= LETIMER_CTRL_COMP0TOP; - if (init->topValue != 0U) { - letimer->COMP0 = init->topValue; - } -#elif defined (LETIMER_CTRL_CNTTOPEN) - tmp |= LETIMER_CTRL_CNTTOPEN; - if (init->topValue != 0U) { - letimer->TOP = init->topValue; - } -#endif - } - - if (init->bufTop) { - tmp |= LETIMER_CTRL_BUFTOP; - } - - if (init->out0Pol) { - tmp |= LETIMER_CTRL_OPOL0; - } - - if (init->out1Pol) { - tmp |= LETIMER_CTRL_OPOL1; - } - - tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; - tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; - tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; - -#if defined(LETIMER_SYNCBUSY_CTRL) - /* LF register about to be modified requires sync; busy check. */ - regSync(letimer, LETIMER_SYNCBUSY_CTRL); -#endif - letimer->CTRL = tmp; - - /* Start the timer if specified to be enabled and not already running. */ - if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { -#if defined(LETIMER_SYNCBUSY_CMD) - regSync(letimer, LETIMER_SYNCBUSY_CMD); -#elif defined(LETIMER_SYNCBUSY_START) - regSync(letimer, LETIMER_SYNCBUSY_START); -#endif - letimer->CMD = LETIMER_CMD_START; - } -} - -/***************************************************************************//** - * @brief - * Get the LETIMER repeat register value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] rep - * Repeat register to get, either 0 or 1. - * - * @return - * Repeat register value, 0 if invalid register selected. - ******************************************************************************/ -uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) -{ - uint32_t ret; - - EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); - - /* Initialize the selected compare value. */ - switch (rep) { - case 0: -#if defined(LETIMER_SYNCBUSY_REP0) - /* Wait for sync to complete to read the potentially pending value. */ - regSync(letimer, LETIMER_SYNCBUSY_REP0); -#endif - ret = letimer->REP0; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_REP1) - regSync(letimer, LETIMER_SYNCBUSY_REP1); -#endif - ret = letimer->REP1; - break; - - default: - /* An unknown compare register selected. */ - ret = 0; - break; - } - - return ret; -} - -/***************************************************************************//** - * @brief - * Set the LETIMER repeat counter register value. - * - * @note - * The setting of a repeat counter register requires synchronization into the - * low-frequency domain. If the same register is modified before a previous - * update has completed, this function will stall until the previous - * synchronization has completed. This only applies to the Gecko Family. See - * comments in the LETIMER_Sync() internal function call. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] rep - * Repeat counter register to set, either 0 or 1. - * - * @param[in] value - * An initialization value (<= 0x0000ffff). - ******************************************************************************/ -void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, - unsigned int rep, - uint32_t value) -{ - EFM_ASSERT(LETIMER_REF_VALID(letimer) - && LETIMER_REP_REG_VALID(rep) - && ((value & ~(_LETIMER_REP0_REP0_MASK - >> _LETIMER_REP0_REP0_SHIFT)) - == 0)); - - /* Initialize the selected compare value. */ - switch (rep) { - case 0: -#if defined(LETIMER_SYNCBUSY_REP0) - regSync(letimer, LETIMER_SYNCBUSY_REP0); -#endif - letimer->REP0 = value; - break; - - case 1: -#if defined(LETIMER_SYNCBUSY_REP1) - regSync(letimer, LETIMER_SYNCBUSY_REP1); -#endif - letimer->REP1 = value; - break; - - default: - /* An unknown compare register selected, abort. */ - break; - } -} - -/***************************************************************************//** - * @brief - * Reset LETIMER to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * a centralized setup of this feature. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - ******************************************************************************/ -void LETIMER_Reset(LETIMER_TypeDef *letimer) -{ -#if defined(LETIMER_EN_EN) - letimer->EN_SET = LETIMER_EN_EN; -#endif - LETIMER_SyncWait(letimer); - -#if defined(LETIMER_SWRST_SWRST) - letimer->SWRST_SET = LETIMER_SWRST_SWRST; - while (letimer->SWRST & _LETIMER_SWRST_RESETTING_MASK) { - } -#else - -#if defined(_LETIMER_FREEZE_MASK) - /* Freeze registers to avoid stalling for LF synchronization. */ - LETIMER_FreezeEnable(letimer, true); -#endif - - /* Make sure disabled first, before resetting other registers. */ - letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR - | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; - letimer->CTRL = _LETIMER_CTRL_RESETVALUE; - letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; - letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; - letimer->REP0 = _LETIMER_REP0_RESETVALUE; - letimer->REP1 = _LETIMER_REP1_RESETVALUE; - letimer->IEN = _LETIMER_IEN_RESETVALUE; - LETIMER_IntClear(letimer, _LETIMER_IF_MASK); - -#if defined(_LETIMER_FREEZE_MASK) - /* Unfreeze registers and pass new settings to LETIMER. */ - LETIMER_FreezeEnable(letimer, false); -#endif - - LETIMER_SyncWait(letimer); - -#if defined (LETIMER_EN_EN) - letimer->EN_CLR = LETIMER_EN_EN; -#if defined(_LETIMER_EN_DISABLING_MASK) - /* - * Currently, there are no chips without SWRST and with LETIMER_EN_DISABLING - * so this code should never be reached, but that way the same pattern of - * checking the disabling bit is spread across emlib, and code is slightly - * more resilient to feature addition/removal. - */ - while (letimer->EN & _LETIMER_EN_DISABLING_MASK) { - } -#endif -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Wait for the LETIMER to complete all synchronization of register changes - * and commands. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - ******************************************************************************/ -void LETIMER_SyncWait(LETIMER_TypeDef *letimer) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { - /* Wait for previous synchronization to finish */ - } -#else - while (letimer->SYNCBUSY != 0U) { - /* Wait for previous synchronization to finish */ - } -#endif -} - -/***************************************************************************//** - * @brief - * Set the LETIMER top value. - * - * @note - * The LETIMER is a down-counter, so when the counter reaches 0 then the top - * value will be loaded into the counter. This function can be used to set - * the top value. - * - * If the LETIMER is not already configured to use a top value then this - * function will enable that functionality for the user. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @param[in] value - * The top value. This can be a 16 bit value on series-0 and series-1 devices - * and a 24 bit value on series-2 devices. - ******************************************************************************/ -void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) -{ -#if defined(LETIMER_SYNCBUSY_CTRL) - regSync(letimer, LETIMER_SYNCBUSY_CTRL); -#elif defined(LETIMER_SYNCBUSY_TOP) - regSync(letimer, LETIMER_SYNCBUSY_TOP); -#endif - -#if defined(_LETIMER_TOP_MASK) - /* Make sure TOP value is enabled. */ - if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { - letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; - } - letimer->TOP = value; -#else - /* Make sure TOP value is enabled. */ - if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { - letimer->CTRL |= LETIMER_CTRL_COMP0TOP; - } - LETIMER_CompareSet(letimer, 0, value); -#endif -} - -/***************************************************************************//** - * @brief - * Get the current LETIMER top value. - * - * @param[in] letimer - * A pointer to the LETIMER peripheral register block. - * - * @return - * The top value. This will be a 16 bit value on series-0 and series-1 - * devices and a 24 bit value on series-2 devices. - ******************************************************************************/ -uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) -{ -#if defined(_LETIMER_TOP_MASK) - regSync(letimer, LETIMER_SYNCBUSY_TOP); - return letimer->TOP; -#else -#if defined(LETIMER_SYNCBUSY_COMP0) - regSync(letimer, LETIMER_SYNCBUSY_COMP0); -#endif - return letimer->COMP0; -#endif -} - -/** @} (end addtogroup letimer) */ -#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Low Energy Timer (LETIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_letimer.h" +#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) +#include "em_cmu.h" +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup letimer LETIMER - Low Energy Timer + * @brief Low Energy Timer (LETIMER) Peripheral API + * @details + * This module contains functions to control the LETIMER peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The LETIMER is a down-counter that can keep track + * of time and output configurable waveforms. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** A validation of the valid comparator register for assert statements. */ +#define LETIMER_COMP_REG_VALID(reg) (((reg) <= 1)) + +/** A validation of the LETIMER register block pointer reference for assert statements. */ +#if (LETIMER_COUNT == 1) +#define LETIMER_REF_VALID(ref) ((ref) == LETIMER0) +#elif (LETIMER_COUNT == 2) +#define LETIMER_REF_VALID(ref) (((ref) == LETIMER0) || ((ref) == LETIMER1)) +#else +#error Undefined number of analog comparators (ACMP). +#endif + +/** A validation of the valid repeat counter register for assert statements. */ +#define LETIMER_REP_REG_VALID(reg) (((reg) <= 1)) + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for an ongoing sync of register(s) to the low-frequency domain to complete. + * + * @note + * See the reference manual chapter about Access to Low Energy Peripherals + * (Asynchronos Registers) for details. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] mask + * A bitmask corresponding to SYNCBUSY register defined bits, indicating + * registers that must complete any ongoing synchronization. + ******************************************************************************/ +__STATIC_INLINE void regSync(LETIMER_TypeDef *letimer, uint32_t mask) +{ +#if defined(_LETIMER_FREEZE_MASK) + /* Avoid a deadlock if modifying the same register twice when freeze mode is */ + /* activated. */ + if (letimer->FREEZE & LETIMER_FREEZE_REGFREEZE) { + return; + } +#endif + + /* Wait for any pending write operation to complete. */ + while (letimer->SYNCBUSY & mask) { + } +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get the LETIMER compare register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to get, either 0 or 1. + * + * @return + * A compare register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_CompareGet(LETIMER_TypeDef *letimer, unsigned int comp) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_COMP_REG_VALID(comp)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + ret = letimer->COMP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + ret = letimer->COMP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Get LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @return + * Current LETIMER counter value. + ******************************************************************************/ +uint32_t LETIMER_CounterGet(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + return letimer->CNT; +} + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Set LETIMER counter value. + * + * @param[in] letimer + * Pointer to the LETIMER peripheral register block. + * + * @param[in] value + * New counter value. + ******************************************************************************/ +void LETIMER_CounterSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CNT) + regSync(letimer, LETIMER_SYNCBUSY_CNT); +#endif + letimer->CNT = value; +} +#endif + +/***************************************************************************//** + * @brief + * Set the LETIMER compare register value. + * + * @note + * The setting of a compare register requires synchronization into the + * low frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] comp + * A compare register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_CompareSet(LETIMER_TypeDef *letimer, + unsigned int comp, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_COMP_REG_VALID(comp) + && ((value & ~(_LETIMER_COMP0_COMP0_MASK + >> _LETIMER_COMP0_COMP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (comp) { + case 0: +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + letimer->COMP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_COMP1) + regSync(letimer, LETIMER_SYNCBUSY_COMP1); +#endif + letimer->COMP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Start/stop LETIMER. + * + * @note + * The enabling/disabling of the LETIMER modifies the LETIMER CMD register + * which requires synchronization into the low-frequency domain. If this + * register is modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * True to enable counting, false to disable. + ******************************************************************************/ +void LETIMER_Enable(LETIMER_TypeDef *letimer, bool enable) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined (LETIMER_SYNCBUSY_START) && defined (LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP | LETIMER_SYNCBUSY_START); +#endif + + if (enable) { + letimer->CMD = LETIMER_CMD_START; + } else { + letimer->CMD = LETIMER_CMD_STOP; + } +} + +#if defined(_LETIMER_FREEZE_MASK) +/***************************************************************************//** + * @brief + * LETIMER register synchronization freeze control. + * + * @details + * Some LETIMER registers require synchronization into the low-frequency (LF) + * domain. The freeze feature allows for several such registers to be + * modified before passing them to the LF domain simultaneously (which + * takes place when the freeze mode is disabled). + * + * @note + * When enabling freeze mode, this function will wait for all current + * ongoing LETIMER synchronization to the LF domain to complete (Normally + * synchronization will not be in progress.) However, for this reason, when + * using freeze mode, modifications of registers requiring the LF synchronization + * should be done within one freeze enable/disable block to avoid unecessary + * stalling. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] enable + * @li True - enable freeze, modified registers are not propagated to the + * LF domain + * @li False - disables freeze, modified registers are propagated to the LF + * domain + ******************************************************************************/ +void LETIMER_FreezeEnable(LETIMER_TypeDef *letimer, bool enable) +{ + if (enable) { + /* + * Wait for any ongoing LF synchronization to complete to + * protect against the rare case when a user + * - modifies a register requiring LF sync + * - then enables freeze before LF sync completed + * - then modifies the same register again + * since modifying a register while it is in sync progress should be + * avoided. + */ + while (letimer->SYNCBUSY) { + } + + letimer->FREEZE = LETIMER_FREEZE_REGFREEZE; + } else { + letimer->FREEZE = 0; + } +} +#endif /* defined(_LETIMER_FREEZE_MASK) */ + +/***************************************************************************//** + * @brief + * Initialize LETIMER. + * + * @details + * Note that the compare/repeat values must be set separately with + * LETIMER_CompareSet() and LETIMER_RepeatSet(). That should probably be done + * prior using this function if configuring the LETIMER to start when + * initialization is complete. + * + * @note + * The initialization of the LETIMER modifies the LETIMER CTRL/CMD registers + * which require synchronization into the low-frequency domain. If any of those + * registers are modified before a previous update to the same register has + * completed, this function will stall until the previous synchronization has + * completed. This only applies to the Gecko Family. See comments in the + * LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] init + * A pointer to the LETIMER initialization structure. + ******************************************************************************/ +void LETIMER_Init(LETIMER_TypeDef *letimer, const LETIMER_Init_TypeDef *init) +{ + uint32_t tmp = 0; + + EFM_ASSERT(LETIMER_REF_VALID(letimer)); + +#if defined (LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled and running. */ + if (!(init->enable) && (letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_STOP) + regSync(letimer, LETIMER_SYNCBUSY_STOP); +#endif + letimer->CMD = LETIMER_CMD_STOP; + } + + /* Configure the DEBUGRUN flag, which sets whether or not the counter should be + * updated when the debugger is active. */ + if (init->debugRun) { + tmp |= LETIMER_CTRL_DEBUGRUN; + } + +#if defined(LETIMER_CTRL_RTCC0TEN) + if (init->rtcComp0Enable) { + tmp |= LETIMER_CTRL_RTCC0TEN; + } + + if (init->rtcComp1Enable) { + tmp |= LETIMER_CTRL_RTCC1TEN; + } +#endif + + if ((init->comp0Top) || (init->topValue != 0U)) { +#if defined (LETIMER_CTRL_COMP0TOP) + tmp |= LETIMER_CTRL_COMP0TOP; + if (init->topValue != 0U) { + letimer->COMP0 = init->topValue; + } +#elif defined (LETIMER_CTRL_CNTTOPEN) + tmp |= LETIMER_CTRL_CNTTOPEN; + if (init->topValue != 0U) { + letimer->TOP = init->topValue; + } +#endif + } + + if (init->bufTop) { + tmp |= LETIMER_CTRL_BUFTOP; + } + + if (init->out0Pol) { + tmp |= LETIMER_CTRL_OPOL0; + } + + if (init->out1Pol) { + tmp |= LETIMER_CTRL_OPOL1; + } + + tmp |= init->ufoa0 << _LETIMER_CTRL_UFOA0_SHIFT; + tmp |= init->ufoa1 << _LETIMER_CTRL_UFOA1_SHIFT; + tmp |= init->repMode << _LETIMER_CTRL_REPMODE_SHIFT; + +#if defined(LETIMER_SYNCBUSY_CTRL) + /* LF register about to be modified requires sync; busy check. */ + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#endif + letimer->CTRL = tmp; + + /* Start the timer if specified to be enabled and not already running. */ + if (init->enable && !(letimer->STATUS & LETIMER_STATUS_RUNNING)) { +#if defined(LETIMER_SYNCBUSY_CMD) + regSync(letimer, LETIMER_SYNCBUSY_CMD); +#elif defined(LETIMER_SYNCBUSY_START) + regSync(letimer, LETIMER_SYNCBUSY_START); +#endif + letimer->CMD = LETIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Get the LETIMER repeat register value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat register to get, either 0 or 1. + * + * @return + * Repeat register value, 0 if invalid register selected. + ******************************************************************************/ +uint32_t LETIMER_RepeatGet(LETIMER_TypeDef *letimer, unsigned int rep) +{ + uint32_t ret; + + EFM_ASSERT(LETIMER_REF_VALID(letimer) && LETIMER_REP_REG_VALID(rep)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + /* Wait for sync to complete to read the potentially pending value. */ + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + ret = letimer->REP0; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + ret = letimer->REP1; + break; + + default: + /* An unknown compare register selected. */ + ret = 0; + break; + } + + return ret; +} + +/***************************************************************************//** + * @brief + * Set the LETIMER repeat counter register value. + * + * @note + * The setting of a repeat counter register requires synchronization into the + * low-frequency domain. If the same register is modified before a previous + * update has completed, this function will stall until the previous + * synchronization has completed. This only applies to the Gecko Family. See + * comments in the LETIMER_Sync() internal function call. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] rep + * Repeat counter register to set, either 0 or 1. + * + * @param[in] value + * An initialization value (<= 0x0000ffff). + ******************************************************************************/ +void LETIMER_RepeatSet(LETIMER_TypeDef *letimer, + unsigned int rep, + uint32_t value) +{ + EFM_ASSERT(LETIMER_REF_VALID(letimer) + && LETIMER_REP_REG_VALID(rep) + && ((value & ~(_LETIMER_REP0_REP0_MASK + >> _LETIMER_REP0_REP0_SHIFT)) + == 0)); + + /* Initialize the selected compare value. */ + switch (rep) { + case 0: +#if defined(LETIMER_SYNCBUSY_REP0) + regSync(letimer, LETIMER_SYNCBUSY_REP0); +#endif + letimer->REP0 = value; + break; + + case 1: +#if defined(LETIMER_SYNCBUSY_REP1) + regSync(letimer, LETIMER_SYNCBUSY_REP1); +#endif + letimer->REP1 = value; + break; + + default: + /* An unknown compare register selected, abort. */ + break; + } +} + +/***************************************************************************//** + * @brief + * Reset LETIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_Reset(LETIMER_TypeDef *letimer) +{ +#if defined(LETIMER_EN_EN) + letimer->EN_SET = LETIMER_EN_EN; +#endif + LETIMER_SyncWait(letimer); + +#if defined(LETIMER_SWRST_SWRST) + letimer->SWRST_SET = LETIMER_SWRST_SWRST; + while (letimer->SWRST & _LETIMER_SWRST_RESETTING_MASK) { + } +#else + +#if defined(_LETIMER_FREEZE_MASK) + /* Freeze registers to avoid stalling for LF synchronization. */ + LETIMER_FreezeEnable(letimer, true); +#endif + + /* Make sure disabled first, before resetting other registers. */ + letimer->CMD = LETIMER_CMD_STOP | LETIMER_CMD_CLEAR + | LETIMER_CMD_CTO0 | LETIMER_CMD_CTO1; + letimer->CTRL = _LETIMER_CTRL_RESETVALUE; + letimer->COMP0 = _LETIMER_COMP0_RESETVALUE; + letimer->COMP1 = _LETIMER_COMP1_RESETVALUE; + letimer->REP0 = _LETIMER_REP0_RESETVALUE; + letimer->REP1 = _LETIMER_REP1_RESETVALUE; + letimer->IEN = _LETIMER_IEN_RESETVALUE; + LETIMER_IntClear(letimer, _LETIMER_IF_MASK); + +#if defined(_LETIMER_FREEZE_MASK) + /* Unfreeze registers and pass new settings to LETIMER. */ + LETIMER_FreezeEnable(letimer, false); +#endif + + LETIMER_SyncWait(letimer); + +#if defined (LETIMER_EN_EN) + letimer->EN_CLR = LETIMER_EN_EN; +#if defined(_LETIMER_EN_DISABLING_MASK) + /* + * Currently, there are no chips without SWRST and with LETIMER_EN_DISABLING + * so this code should never be reached, but that way the same pattern of + * checking the disabling bit is spread across emlib, and code is slightly + * more resilient to feature addition/removal. + */ + while (letimer->EN & _LETIMER_EN_DISABLING_MASK) { + } +#endif +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the LETIMER to complete all synchronization of register changes + * and commands. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + ******************************************************************************/ +void LETIMER_SyncWait(LETIMER_TypeDef *letimer) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((letimer->EN != 0U) && (letimer->SYNCBUSY != 0U)) { + /* Wait for previous synchronization to finish */ + } +#else + while (letimer->SYNCBUSY != 0U) { + /* Wait for previous synchronization to finish */ + } +#endif +} + +/***************************************************************************//** + * @brief + * Set the LETIMER top value. + * + * @note + * The LETIMER is a down-counter, so when the counter reaches 0 then the top + * value will be loaded into the counter. This function can be used to set + * the top value. + * + * If the LETIMER is not already configured to use a top value then this + * function will enable that functionality for the user. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @param[in] value + * The top value. This can be a 16 bit value on series-0 and series-1 devices + * and a 24 bit value on series-2 devices. + ******************************************************************************/ +void LETIMER_TopSet(LETIMER_TypeDef *letimer, uint32_t value) +{ +#if defined(LETIMER_SYNCBUSY_CTRL) + regSync(letimer, LETIMER_SYNCBUSY_CTRL); +#elif defined(LETIMER_SYNCBUSY_TOP) + regSync(letimer, LETIMER_SYNCBUSY_TOP); +#endif + +#if defined(_LETIMER_TOP_MASK) + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_CNTTOPEN) == 0U) { + letimer->CTRL_SET = LETIMER_CTRL_CNTTOPEN; + } + letimer->TOP = value; +#else + /* Make sure TOP value is enabled. */ + if ((letimer->CTRL & LETIMER_CTRL_COMP0TOP) == 0U) { + letimer->CTRL |= LETIMER_CTRL_COMP0TOP; + } + LETIMER_CompareSet(letimer, 0, value); +#endif +} + +/***************************************************************************//** + * @brief + * Get the current LETIMER top value. + * + * @param[in] letimer + * A pointer to the LETIMER peripheral register block. + * + * @return + * The top value. This will be a 16 bit value on series-0 and series-1 + * devices and a 24 bit value on series-2 devices. + ******************************************************************************/ +uint32_t LETIMER_TopGet(LETIMER_TypeDef *letimer) +{ +#if defined(_LETIMER_TOP_MASK) + regSync(letimer, LETIMER_SYNCBUSY_TOP); + return letimer->TOP; +#else +#if defined(LETIMER_SYNCBUSY_COMP0) + regSync(letimer, LETIMER_SYNCBUSY_COMP0); +#endif + return letimer->COMP0; +#endif +} + +/** @} (end addtogroup letimer) */ +#endif /* defined(LETIMER_COUNT) && (LETIMER_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c index bca6b0a..0f35292 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_msc.c @@ -1,2075 +1,2075 @@ -/***************************************************************************//** - * @file - * @brief Flash controller (MSC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_msc.h" -#if defined(MSC_COUNT) && (MSC_COUNT > 0) - -#include "sl_assert.h" -#include "em_cmu.h" -#include "sl_common.h" -#include "em_core.h" -#include "em_system.h" - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(__ICCARM__) -/* Suppress warnings originating from use of EFM_ASSERT() with IAR Embedded Workbench */ -#pragma diag_suppress=Ta022,Ta023 -#endif - -#if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) -#error "Running Flash write/erase operations from Flash is not supported on EFM32G." -#endif - -/******************************************************************************* - ****************************** DEFINES ****************************** - ******************************************************************************/ -#if defined(MSC_WRITECTRL_WDOUBLE) -#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) -#else -#define WORDS_PER_DATA_PHASE (1) -#endif - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/* Fix for errata FLASH_E201 - Potential program failure after Power On */ -#define ERRATA_FIX_FLASH_E201_EN -#endif - -#define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) -/* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 - banks (not RAM2). It is necessary to figure out which is biggest to - calculate the number of DMA descriptors needed. */ -#define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) - -#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) - -#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) - -#define ECC_CTRL_REG (MSC->ECCCTRL) -#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) -#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) -#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) - -#define ECC_IFC_REG (MSC->IFC) -#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ - | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) - -#define ECC_FAULT_CTRL_REG (MSC->CTRL) -#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) - -#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) -/* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and - RAM2 banks. All banks are of equal size. */ -#define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) - -#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) - -#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) - -#define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) -#define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) - -#define ECC_CTRL_REG (MSC->ECCCTRL) -#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) -#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) -#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) -#define ECC_RAM2_SYNDROMES_INIT (MSC_ECCCTRL_RAM2ECCEWEN) -#define ECC_RAM2_CORRECTION_EN (MSC_ECCCTRL_RAM2ECCCHKEN) - -#define ECC_IFC_REG (MSC->IFC) -#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ - | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ - | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) - -#define ECC_FAULT_CTRL_REG (MSC->CTRL) -#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) - -#elif defined(_SILICON_LABS_32B_SERIES_2) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -/* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the - main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ -#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) -#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN) - -#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) - -/* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the - main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ -#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEN) -#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) - -#define ECC_IF_REG (SYSCFG->IF) -#define ECC_IF_1BIT_ERROR (SYSCFG_IF_RAMERR1B) - -#elif defined(_MPAHBRAM_CTRL_MASK) - -/* From Series 2 Config 3, aka EFR32XG23, ECC is now standalone in the - * MPAHBRAM module */ -#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) -#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) -#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) -#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) -#endif - -#define ECC_IF_REG (DMEM->IF) -/* number of AHB ports is between 1 and 4 */ -#if defined(MPAHBRAM_IF_AHB3ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B | MPAHBRAM_IF_AHB3ERR1B) -#elif defined(MPAHBRAM_IF_AHB2ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B) -#elif defined(MPAHBRAM_IF_AHB1ERR1B) -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B) -#else -#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B) -#endif - -#else - -#error "Unknown device" - -#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */ - -#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - -#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE) -#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE) -#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) -#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE) - -#define ECC_CTRL0_REG (DMEM0->CTRL) -#define ECC_CTRL1_REG (DMEM1->CTRL) - -#define ECC_IFC0_REG (DMEM0->IF_CLR) -#define ECC_IFC1_REG (DMEM1->IF_CLR) -#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) - -#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL) -#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL) -#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) - -#else - -#define ECC_RAM0_MEM_BASE (SRAM_BASE) -#define ECC_RAM0_MEM_SIZE (SRAM_SIZE) - -#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) -#define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) -#define ECC_IFC_REG (SYSCFG->IF_CLR) -#define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) -#define ECC_FAULT_CTRL_REG (SYSCFG->CTRL) -#define ECC_FAULT_EN (SYSCFG_CTRL_RAMECCERRFAULTEN) - -#elif defined(_MPAHBRAM_CTRL_MASK) -#define ECC_CTRL_REG (DMEM->CTRL) -#define ECC_IFC_REG (DMEM->IF_CLR) -#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) -#define ECC_FAULT_CTRL_REG (DMEM->CTRL) -#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) -#endif - -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#else - -#error Unknown device. - -#endif - -#define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ - >> _LDMA_CH_CTRL_XFERCNT_SHIFT) -#define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ - -#define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -/***************************************************************************//** - * @brief - * Get locked status of the MSC registers. - * - * @detail - * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions - * that can be placed either in flash or in RAM. - ******************************************************************************/ -#if defined(_MSC_STATUS_REGLOCK_MASK) -#define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) -#else -#define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) -#endif - -/******************************************************************************* - ****************************** TYPEDEFS ****************************** - ******************************************************************************/ - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -typedef struct { - uint32_t initSyndromeEnable; - uint32_t correctionEnable; - uint32_t base; - uint32_t size; -} MSC_EccBank_Typedef; - -#endif - -/******************************************************************************* - ****************************** LOCALS ******************************* - ******************************************************************************/ -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) -static const MSC_EccBank_Typedef eccBankTbl[MSC_ECC_BANKS] = -{ - { - ECC_RAM0_SYNDROMES_INIT, ECC_RAM0_CORRECTION_EN, - ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE - }, -#if MSC_ECC_BANKS > 1 - { - ECC_RAM1_SYNDROMES_INIT, ECC_RAM1_CORRECTION_EN, - ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE - }, -#if MSC_ECC_BANKS > 2 - { - ECC_RAM2_SYNDROMES_INIT, ECC_RAM2_CORRECTION_EN, - ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE - }, -#endif -#endif -}; -#endif - -/******************************************************************************* - ****************************** FUNCTIONS ****************************** - ******************************************************************************/ -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_WriteWordI(uint32_t *address, - void const *data, - uint32_t numBytes); - -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_LoadWriteData(uint32_t* data, - uint32_t numWords); - -MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef -MSC_LoadVerifyAddress(uint32_t* address); - -/** @endcond */ - -/***************************************************************************//** - * @addtogroup msc - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Wait for a specified MSC status or timeout. - * - * @param[in] mask - * MSC->STATUS register mask to apply when testing for specified status. - * @param[in] value - * The value the MSC->STATUS test is waiting to see. - * @return - * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - Specified status criteria fulfilled. - * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * write or erase a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) -{ - uint32_t timeOut = MSC_PROGRAM_TIMEOUT; - - while (timeOut) { - uint32_t status = MSC->STATUS; - - /* if INVADDR is asserted by MSC, BUSY will never go high, can be checked early */ - if (status & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - /* - * if requested operation fails because flash is locked, BUSY will be high - * for a few cycles and it's not safe to clear WRITECTRL.WREN during that - * period. mscStatusWait should return only when it's safe to do so. - * - * So if user is checking BUSY flag, make sure it matches user's expected - * value and only then check the lock bits. Otherwise, do check early and - * bail out if necessary. - */ - - if ((!(mask & MSC_STATUS_BUSY)) - && (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK))) { - return mscReturnLocked; - } - - if ((status & mask) == value) { - if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { - return mscReturnLocked; - } else { - return mscReturnOk; - } - } - - timeOut--; - } - - return mscReturnTimeOut; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. It is assumed that start address is word - * aligned and that numBytes is an integer multiple of four, and that the - * write operation does not cross a flash page boundary. - * - * @param[in] address - * Pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * Returns the status of the write operation, @ref MSC_Status_TypeDef - * @verbatim - * flashReturnOk - Operation completed successfully. - * flashReturnInvalidAddr - Operation tried to write to a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * program a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -msc_Return_TypeDef writeBurst(uint32_t address, - const uint32_t *data, - uint32_t numBytes) -{ - msc_Return_TypeDef retVal; - - MSC->ADDRB = address; - - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - MSC->WDATA = *data++; - numBytes -= 4; - - while (numBytes) { - retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY); - - if (retVal != mscReturnOk) { - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - return retVal; - } - - MSC->WDATA = *data++; - numBytes -= 4; - } - - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - - if (retVal == mscReturnOk) { - // We need to check twice to be sure - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Initialize MSC module. Puts MSC hw in a known state. - ******************************************************************************/ -void MSC_Init(void) -{ -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - // Unlock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; -} - -/***************************************************************************//** - * @brief - * Turn off MSC flash write enable and lock MSC registers. - ******************************************************************************/ -void MSC_Deinit(void) -{ - // Unlock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - // Lock MSC - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_CLR = CMU_CLKEN1_MSC; -#endif -} - -/***************************************************************************//** - * @brief - * Set MSC code execution configuration - * - * @param[in] execConfig - * Code execution configuration - ******************************************************************************/ -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) -{ - uint32_t mscReadCtrl; - -#if defined(MSC_RDATACTRL_DOUTBUFEN) - mscReadCtrl = MSC->RDATACTRL & ~MSC_RDATACTRL_DOUTBUFEN; - - if (execConfig->doutBufEn) { - mscReadCtrl |= MSC_RDATACTRL_DOUTBUFEN; - } - - MSC->RDATACTRL = mscReadCtrl; -#elif defined(MSC_READCTRL_DOUTBUFEN) - mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; - - if (execConfig->doutBufEn) { - mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; - } - MSC->READCTRL = mscReadCtrl; -#endif -} - -/***************************************************************************//** - * @brief - * Erases a page in flash memory. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved - * automatically by using attributes in the function proctype. For Keil - * uVision you must define a section called "ram_code" and place this manually - * in your project's scatter file. - * - * @param[in] startAddress - * Pointer to the flash page to erase. Must be aligned to beginning of page - * boundary. - * @return - * Returns the status of erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - Operation completed successfully. - * mscReturnInvalidAddr - Operation tried to erase a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * erase a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) -{ - MSC_Status_TypeDef retVal; - bool wasLocked; - - // Address must be aligned to page boundary - EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; - MSC->ADDRB = (uint32_t)startAddress; - MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; - - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - - if (retVal == mscReturnOk) { - // We need to check twice to be sure - retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); - } - - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. Write data must be aligned to words and - * contain a number of bytes that is divisible by four. - * @note - * It is recommended to erase the flash page before performing a write. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved - * automatically by using attributes in the function proctype. For Keil - * uVision you must define a section called "ram_code" and place this manually - * in your project's scatter file. - * - * The Flash memory is organized into 64-bit wide double-words. - * Each 64-bit double-word can be written only twice using burst write - * operation between erasing cycles. The user's application must store data in - * RAM to sustain burst write operation. - * - * EFR32XG21 RevC is not able to program every word twice before the next erase. - * - * @param[in] address - * Pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * Returns the status of the write operation, @ref MSC_Status_TypeDef - * @verbatim - * flashReturnOk - Operation completed successfully. - * flashReturnInvalidAddr - Operation tried to write to a non-flash area. - * flashReturnLocked - MSC registers are locked or the operation tried to - * program a locked area of the flash. - * flashReturnTimeOut - Operation timed out. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - uint32_t addr; - const uint8_t *pData; - uint32_t burstLen; - MSC_Status_TypeDef retVal = mscReturnOk; - bool wasLocked; - - // Check alignment (must be aligned to words) - EFM_ASSERT(((uint32_t)address & 0x3U) == 0); - // Check number of bytes, must be divisable by four - EFM_ASSERT((numBytes & 0x3U) == 0); - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - // Enable flash write - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; - - addr = (uint32_t)address; - pData = (uint8_t*)data; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); - - if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) - != mscReturnOk) { - break; - } - - addr += burstLen; - pData += burstLen; - numBytes -= burstLen; - } - - // Disable flash write - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_MassErase(void) -{ - MSC_Status_TypeDef retVal; - - if (MSC_IS_LOCKED()) { - return mscReturnLocked; - } - - MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // Set write enable bit - MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; // Enable Write ctrl access - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; // Start Mass erase procedure - retVal = mscStatusWait(MSC_STATUS_BUSY, 0); // Wait for end of busy flag or a problem (INVADDR, LOCK, REGLOCK, TIMEOUT) - MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; // Reenable mass erase lock bit - MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Disable Write ctrl access - - return retVal; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory using the DMA. - * - * @details - * This function uses the LDMA to write data to the internal flash memory. - * This is the fastest way to write data to the flash and should be used when - * the application wants to achieve write speeds like they are reported in the - * datasheet. Note that copying data from flash to flash will be slower than - * copying from RAM to flash. So the source data must be in RAM in order to - * see the write speeds similar to the datasheet numbers. - * - * @note - * This function requires that the LDMA and LDMAXBAR clock is enabled. - * - * @param[in] ch - * DMA channel to use - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * - * @param[in] data - * Data to write to flash and be aligned to words. - * - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * @endverbatim - ******************************************************************************/ -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes) -{ - uint32_t words = numBytes / 4; - uint32_t burstLen; - uint32_t src = (uint32_t) data; - uint32_t dst = (uint32_t) address; - bool wasLocked; - - EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); - - LDMA->EN_SET = 0x1; - LDMAXBAR->CH[ch].REQSEL = LDMAXBAR_CH_REQSEL_SOURCESEL_MSC - | LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA; - LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; - LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; - LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; - -#if defined(_CMU_CLKEN1_MASK) - CMU->CLKEN1_SET = CMU_CLKEN1_MSC; -#endif - // Unlock MSC - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Enable writing to the MSC module. - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); - words = burstLen / 4; - - // Load the address. - MSC->ADDRB = dst; - - // Check for an invalid address. - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE - | LDMA_CH_CTRL_SIZE_WORD - | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); - LDMA->CH[ch].SRC = (uint32_t)src; - LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; - - // Enable channel - LDMA->CHEN_SET = (0x1 << ch); - - while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { - ; - } - - LDMA->CHDONE_CLR = (0x1 << ch); - LDMA->CHDIS_SET = (0x1 << ch); - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - dst += burstLen; - src += burstLen; - numBytes -= burstLen; - } - - // Disable writing to the MSC module. - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return mscReturnOk; -} - -#else // defined(_SILICON_LABS_32B_SERIES_2) - -/***************************************************************************//** - * @brief - * Enables the flash controller for writing. - * @note - * This function must be called before flash operations when - * AUXHFRCO clock has been changed from a default band. - ******************************************************************************/ -void MSC_Init(void) -{ -#if defined(_MSC_TIMEBASE_MASK) - uint32_t freq, cycles; -#endif - -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done. Flash erase and write requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Unlock the MSC module. */ - MSC->LOCK = MSC_UNLOCK_CODE; - /* Disable writing to the Flash. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - -#if defined(_MSC_TIMEBASE_MASK) - /* Configure MSC->TIMEBASE according to a selected frequency. */ - freq = CMU_ClockFreqGet(cmuClock_AUX); - - /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band - is tuned to 1.2 MHz on newer revisions. */ - if (freq > 1200000) { - /* Calculate a number of clock cycles for 1 us as a base period. */ - freq = (freq * 11) / 10; - cycles = (freq / 1000000) + 1; - - /* Configure clock cycles for flash timing. */ - MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK - | _MSC_TIMEBASE_PERIOD_MASK)) - | MSC_TIMEBASE_PERIOD_1US - | (cycles << _MSC_TIMEBASE_BASE_SHIFT); - } else { - /* Calculate a number of clock cycles for 5 us as a base period. */ - freq = (freq * 5 * 11) / 10; - cycles = (freq / 1000000) + 1; - - /* Configure clock cycles for flash timing */ - MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK - | _MSC_TIMEBASE_PERIOD_MASK)) - | MSC_TIMEBASE_PERIOD_5US - | (cycles << _MSC_TIMEBASE_BASE_SHIFT); - } -#endif -} - -/***************************************************************************//** - * @brief - * Disables the flash controller for writing. - ******************************************************************************/ -void MSC_Deinit(void) -{ - /* Disable writing to the Flash. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - /* Lock the MSC module.*/ - MSC->LOCK = 0; -} - -/***************************************************************************//** - * @brief - * Set the MSC code execution configuration. - * - * @param[in] execConfig - * The code execution configuration. - ******************************************************************************/ -void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) -{ - uint32_t mscReadCtrl; - -#if defined(MSC_READCTRL_MODE_WS0SCBTP) - mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; - if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS0; - } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { - mscReadCtrl |= MSC_READCTRL_MODE_WS1; - } else { - /* No change needed. */ - } -#endif - - mscReadCtrl = MSC->READCTRL & ~(0 -#if defined(MSC_READCTRL_SCBTP) - | MSC_READCTRL_SCBTP -#endif -#if defined(MSC_READCTRL_USEHPROT) - | MSC_READCTRL_USEHPROT -#endif -#if defined(MSC_READCTRL_PREFETCH) - | MSC_READCTRL_PREFETCH -#endif -#if defined(MSC_READCTRL_ICCDIS) - | MSC_READCTRL_ICCDIS -#endif -#if defined(MSC_READCTRL_AIDIS) - | MSC_READCTRL_AIDIS -#endif -#if defined(MSC_READCTRL_IFCDIS) - | MSC_READCTRL_IFCDIS -#endif - ); - mscReadCtrl |= (0 -#if defined(MSC_READCTRL_SCBTP) - | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) -#endif -#if defined(MSC_READCTRL_USEHPROT) - | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) -#endif -#if defined(MSC_READCTRL_PREFETCH) - | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) -#endif -#if defined(MSC_READCTRL_ICCDIS) - | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) -#endif -#if defined(MSC_READCTRL_AIDIS) - | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) -#endif -#if defined(MSC_READCTRL_IFCDIS) - | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) -#endif - ); - - MSC->READCTRL = mscReadCtrl; -} - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/***************************************************************************//** - * @brief - * Perform the address phase of the flash write cycle. - * @details - * This function performs the address phase of a flash write operation by - * writing the given flash address to the ADDRB register and issuing the - * LADDRIM command to load the address. - * @param[in] address - * An address in flash memory. Must be aligned at a 4 byte boundary. - * @return - * Returns the status of the address load operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - The operation completed successfully. - * mscReturnInvalidAddr - The operation tried to erase a non-flash area. - * mscReturnLocked - The operation tried to erase a locked area of the Flash. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) -{ - uint32_t timeOut; - - /* Wait for the MSC to become ready. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - /* Load the address. */ - MSC->ADDRB = (uint32_t)address; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - /* Check for an invalid address. */ - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - return mscReturnOk; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Perform a flash data write phase. - * @details - * This function performs the data phase of a flash write operation by loading - * the given number of 32-bit words to the WDATA register. - * @param[in] data - * A pointer to the first data word to load. - * @param[in] numWords - * A number of data words (32-bit) to load. - * @return - * Returns the status of the data load operation. - * @verbatim - * mscReturnOk - An operation completed successfully. - * mscReturnTimeOut - An operation timed out waiting for the flash operation - * to complete. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, - uint32_t numWords) -{ - uint32_t timeOut; - uint32_t wordIndex; - bool useWDouble = false; - MSC_Status_TypeDef retval = mscReturnOk; - -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) - /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ - if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { - /* If the number of words to be written is odd, align by writing - a single word first, before setting the WDOUBLE bit. */ - if (numWords & 0x1) { - /* Wait for the MSC to become ready for the next word. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { - timeOut--; - } - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - - /* Clear the double word option to write the initial single word. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; - /* Write first data word. */ - MSC->WDATA = *data++; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - - /* Wait for the operation to finish. It may be required to change the WDOUBLE - configuration after the initial write. It should not be changed while BUSY. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for timeout. */ - if (timeOut == 0) { - return mscReturnTimeOut; - } - /* Check for a write protected flash area. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - return mscReturnLocked; - } - /* Subtract this initial odd word for the write loop below. */ - numWords -= 1; - retval = mscReturnOk; - } - /* Set the double word option to write two words per - data phase. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; - useWDouble = true; - } -#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ - - /* Write the rest as a double word write if wordsPerDataPhase == 2 */ - if (numWords > 0) { - /* Requires a system core clock at 1MHz or higher */ - EFM_ASSERT(SystemCoreClock >= 1000000); - wordIndex = 0; - while (wordIndex < numWords) { - if (!useWDouble) { - MSC->WDATA = *data++; - wordIndex++; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; - } else { - /* Trigger a double write according to flash properties. */ -#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) - MSC->WDATA = *data++; - while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; - MSC->WDATA = *data++; - wordIndex += 2; - MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; -#endif - } - - /* Wait for the transaction to finish. */ - timeOut = MSC_PROGRAM_TIMEOUT; - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for a timeout. */ - if (timeOut == 0) { - retval = mscReturnTimeOut; - break; - } - /* Check for a write protected flash area. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - retval = mscReturnLocked; - break; - } -#if defined(_EFM32_GECKO_FAMILY) - MSC->ADDRB += 4; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; -#endif - } - } - -#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) - /* Clear a double word option, which should not be left on when returning. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; -#endif - - return retval; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * An internal flash write function. - * @param[in] address - * A write address. - * @param[in] data - * A pointer to the first data word to load. - * @param[in] numBytes - * A nsumber of data bytes to load, which must be a multiple of 4 bytes. - * @return - * Returns the status of the data load operation. - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - uint32_t wordCount; - uint32_t numWords; - uint32_t pageWords; - uint32_t* pData; - bool wasLocked; - MSC_Status_TypeDef retval = mscReturnOk; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* Check alignment (must be aligned to words). */ - EFM_ASSERT(((uint32_t) address & 0x3) == 0); - - /* Check a number of bytes. Must be divisible by four. */ - EFM_ASSERT((numBytes & 0x3) == 0); - -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done and flash write requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Convert bytes to words. */ - numWords = numBytes >> 2; - EFM_ASSERT(numWords > 0); - - /* The following loop splits the data into chunks corresponding to flash pages. - The address is loaded only once per page because the hardware automatically - increments the address internally for each data load inside a page. */ - for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { - /* First, the address is loaded. The address is auto-incremented within a page. - Therefore, the address phase is only needed once for each page. */ - retval = MSC_LoadVerifyAddress(address + wordCount); - if (mscReturnOk != retval) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return retval; - } - /* Compute the number of words to write to the current page. */ - pageWords = - (FLASH_PAGE_SIZE - - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) - / sizeof(uint32_t); - if (pageWords > numWords - wordCount) { - pageWords = numWords - wordCount; - } - /* Write the data in the current page. */ - retval = MSC_LoadWriteData(pData, pageWords); - if (mscReturnOk != retval) { - break; - } - wordCount += pageWords; - pData += pageWords; - } - -#if defined(ERRATA_FIX_FLASH_E201_EN) - /* Fix for errata FLASH_E201 - Potential program failure after Power On. - * - * Check if the first word was programmed correctly. If a failure is detected, - * retry programming of the first word. - * - * A full description of the errata is in the errata document. */ - pData = (uint32_t *) data; - if (*address != *pData) { - retval = MSC_LoadVerifyAddress(address); - if (mscReturnOk == retval) { - retval = MSC_LoadWriteData(pData, 1); - } - } -#endif - - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - -#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) -#if (WORDS_PER_DATA_PHASE == 2) - /* Turn off the double word write cycle support. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; -#endif -#endif - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return retval; -} -MSC_RAMFUNC_DEFINITION_END - -/** @endcond */ - -/***************************************************************************//** - * @brief - * Erases a page in flash memory. - * @note - * For the Gecko family, it is required to run this function from RAM. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, this is - * achieved automatically by using attributes in the function proctype. For Keil - * uVision IDE, define a section called "ram_code" and place this manually in - * the project's scatter file. - * - * @param[in] startAddress - * A pointer to the flash page to erase. Must be aligned to the beginning of the page - * boundary. - * @return - * Returns the status of erase operation, @ref MSC_Status_TypeDef - * @verbatim - * mscReturnOk - The operation completed successfully. - * mscReturnInvalidAddr - The operation tried to erase a non-flash area. - * mscReturnLocked - The operation tried to erase a locked area of the flash. - * mscReturnTimeOut - The operation timed out waiting for the flash operation - * to complete. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) -{ - uint32_t timeOut = MSC_PROGRAM_TIMEOUT; - bool wasLocked; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* An address must be aligned to pages. */ - EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); -#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) - /* VSCALE must be done and flash erase requires VSCALE2. */ - EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); - EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); -#endif - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Load an address. */ - MSC->ADDRB = (uint32_t)startAddress; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - /* Check for an invalid address. */ - if (MSC->STATUS & MSC_STATUS_INVADDR) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnInvalidAddr; - } - - /* Send erase page command. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; - - /* Wait for the erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { - timeOut--; - } - /* Check for write protected page. */ - if (MSC->STATUS & MSC_STATUS_LOCKED) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnLocked; - } - if (timeOut == 0) { - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnTimeOut; - } - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - return mscReturnOk; -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. This function is interrupt-safe, but slower than - * MSC_WriteWordFast(), which writes to flash with interrupts disabled. - * Write data must be aligned to words and contain a number of bytes that is - * divisible by four. - * @note - * It is recommended to erase the flash page before performing a write. - * - * For the Gecko family, it is required to run this function from RAM. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, - * this is done automatically by using attributes in the function proctype. - * For Keil uVision IDE, define a section called "ram_code" and place it - * manually in the project's scatter file. - * - * This function requires a system core clock at 1 MHz or higher. - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * flashReturnLocked - The operation tried to erase a locked area of the Flash. - * flashReturnTimeOut - The operation timed out waiting for the flash operation - * to complete, or the MSC module timed out waiting for the software to write - * the next word into the DWORD register. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - return MSC_WriteWordI(address, data, numBytes); -} -MSC_RAMFUNC_DEFINITION_END - -/***************************************************************************//** - * @brief - * Writes data to flash memory. This function is faster than MSC_WriteWord(), - * but it disables interrupts. Write data must be aligned to words and contain - * a number of bytes that is divisible by four. - * @warning - * This function is only available for certain devices. - * @note - * It is recommended to erase the flash page before performing a write. - * It is required to run this function from RAM on parts that include a - * flash write buffer. - * - * For IAR Embedded Workbench, Simplicity Studio and GCC, - * this is done automatically by using attributes in the function proctype. - * For Keil uVision IDE, define a section called "ram_code" and place this manually - * in the project's scatter file. - * - * @deprecated - * This function is deprecated, the functionality is the same as calling - * @ref MSC_WriteWord(). - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * A number of bytes to write from the Flash. NB: Must be divisible by four. - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * flashReturnLocked - The operation tried to erase a locked area of the flash. - * flashReturnTimeOut - The operation timed out waiting for flash operation - * to complete. Or the MSC timed out waiting for the software to write - * the next word into the DWORD register. - * @endverbatim - ******************************************************************************/ -MSC_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, - void const *data, - uint32_t numBytes) -{ - return MSC_WriteWord(address, data, numBytes); -} -MSC_RAMFUNC_DEFINITION_END - -#if (_SILICON_LABS_32B_SERIES > 0) -/***************************************************************************//** - * @brief - * Writes data from RAM to flash memory using the DMA. - * - * @details - * This function uses the LDMA to write data to the internal flash memory. - * This is the fastest way to write data to the flash and should be used when - * the application wants to achieve write speeds like they are reported in the - * datasheet. Note that this function only supports writing data from RAM to - * flash, it does not support writing data from flash to flash. - * - * @note - * This function requires that the LDMA clock is enabled. - * - * @param[in] ch - * DMA channel to use - * - * @param[in] address - * A pointer to the flash word to write to. Must be aligned to words. - * - * @param[in] data - * Data to write to flash. Note that this argument must be an address in RAM. - * This function does not support copying data from flash to flash on series-1 - * devices. Must be aligned to words. - * - * @param[in] numBytes - * A number of bytes to write from flash. NB: Must be divisible by four. - * - * @return - * Returns the status of the write operation. - * @verbatim - * flashReturnOk - The operation completed successfully. - * flashReturnInvalidAddr - The operation tried to erase a non-flash area. - * @endverbatim - ******************************************************************************/ -MSC_Status_TypeDef MSC_WriteWordDma(int ch, - uint32_t *address, - const void *data, - uint32_t numBytes) -{ - uint32_t words = numBytes / 4; - uint32_t burstLen; - uint32_t src = (uint32_t) data; - uint32_t dst = (uint32_t) address; - bool wasLocked; - - EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); - - // Verify that the data argument is in RAM - if (((uint32_t)data < SRAM_BASE) || ((uint32_t)data > (SRAM_BASE + SRAM_SIZE))) { - EFM_ASSERT(false); - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].REQSEL = LDMA_CH_REQSEL_SOURCESEL_MSC - | LDMA_CH_REQSEL_SIGSEL_MSCWDATA; - LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; - LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; - LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; - - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - // Enable writing to the MSC module. - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - while (numBytes) { - // Max burst length is up to next flash page boundary - burstLen = SL_MIN(numBytes, - ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); - words = burstLen / 4; - - // Load the address. - MSC->ADDRB = dst; - MSC->WRITECMD = MSC_WRITECMD_LADDRIM; - - // Check for an invalid address. - if (MSC->STATUS & MSC_STATUS_INVADDR) { - return mscReturnInvalidAddr; - } - - LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE - | LDMA_CH_CTRL_SIZE_WORD - | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); - LDMA->CH[ch].SRC = (uint32_t)src; - LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; - - // Enable channel - LDMA->CHEN |= (0x1 << ch); - MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; - - while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { - ; - } - BUS_RegMaskedClear(&LDMA->CHDONE, (0x1 << ch)); - BUS_RegMaskedClear(&LDMA->CHEN, (0x1 << ch)); - - dst += burstLen; - src += burstLen; - numBytes -= burstLen; - } - - MSC->WRITECMD = MSC_WRITECMD_WRITEEND; - - // Disable writing to the MSC module. - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - return mscReturnOk; -} -#endif - -#if defined(_MSC_MASSLOCK_MASK) -SL_RAMFUNC_DEFINITION_BEGIN -MSC_Status_TypeDef MSC_MassErase(void) -{ - bool wasLocked; - wasLocked = MSC_IS_LOCKED(); - MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; - - /* Enable writing to the MSC module. */ - MSC->WRITECTRL |= MSC_WRITECTRL_WREN; - - /* Unlock the device mass erase. */ - MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; - - /* Erase the first 512 K block. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; - - /* Waiting for erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { - } - -#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) - /* Erase the second 512 K block. */ - MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; - - /* Waiting for erase to complete. */ - while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { - } -#endif - - /* Restore the mass erase lock. */ - MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; - - /* Disable writing to the MSC module. */ - MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; - - if (wasLocked) { - MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; - } - - /* This will only successfully return if calling function is also in SRAM. */ - return mscReturnOk; -} -SL_RAMFUNC_DEFINITION_END -#endif // defined(_MSC_MASSLOCK_MASK) - -#endif // defined(_SILICON_LABS_32B_SERIES_2) - -#if defined(_MSC_ECCCTRL_MASK) \ - || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ - || defined(_MPAHBRAM_CTRL_MASK) - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_MPAHBRAM_CTRL_MASK) - -/***************************************************************************//** - * @brief - * Read and write existing values in RAM (for ECC initialization). - * - * @details - * This function uses core to load and store the existing data - * values in the given RAM bank. - * - * @param[in] eccBank - * Pointer to ECC RAM bank (MSC_EccBank_Typedef) - ******************************************************************************/ -static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) -{ - volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; - const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); - volatile uint32_t *ctrlreg; - uint32_t enableEcc; - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ctrlreg = &ECC_CTRL0_REG; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ctrlreg = &ECC_CTRL1_REG; - } else { - EFM_ASSERT(0); - return; - } -#else - ctrlreg = &ECC_CTRL_REG; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - - EFM_ASSERT(ramptr < endptr); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) - enableEcc = eccBank->initSyndromeEnable; -#elif defined(_MPAHBRAM_CTRL_MASK) - /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes - to be written in ECC */ - enableEcc = eccBank->correctionEnable; - - /* Enable ECC syndrome write */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_CTRL0_REG |= eccBank->initSyndromeEnable; - ECC_IFC0_REG = ECC_IFC_MASK; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_CTRL1_REG |= eccBank->initSyndromeEnable; - ECC_IFC1_REG = ECC_IFC_MASK; - } -#else - ECC_CTRL_REG |= eccBank->initSyndromeEnable; - ECC_IFC_REG = ECC_IFC_MASK; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#endif - -#ifndef __GNUC__ -#define __asm__ asm -#endif - - /* - * Performs a read and write of all RAM address to initialize - * ECC syndromes. ECC is initialized by reading a RAM address - * while ECC is disabled and write it back while ECC is enabled. - * - * HardFault could occur if we try to read values from RAM while ECC - * is enabled and not initialized. In this case, ECC tries to correct the - * value and ended giving the wrong value which could be sometimes an - * non-existing address. - * - * So for ECC initialization to work properly, this must ensures that while - * ECC is enabled, RAM will be accessed only through writes, no reads shall - * occur. It's hard to have such guarantee with C code, because the C - * compiler with optimization settings, can get in the way - * and do some unwanted reads while ECC is enabled. Assembly allows such - * guarantee and let ECC be initialized without triggering errors. - */ - - __asm__ volatile ( - "1:\n\t" /* define label 1 */ - "LDR r1, [%[ramptr]]\n\t" /* load content of ramptr into R1, ECC - is disabled to get a correct value */ - "LDR r0, [%[ctrlreg]]\n\t" /* load ctrlreg content into R0 */ - "ORR r0, r0, %[enableEcc]\n\t" /* OR R0 and enableEcc, and store result - in R0 */ - "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is - enabled from now on */ - "STR r1, [%[ramptr]]\n\t" /* write back ram content where it was, - syndrome will be written in ECC */ - "BIC r0, r0, %[enableEcc]\n\t" /* bit clear enableEcc from R0, and store - result in R0 */ - "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is - disabled */ - "ADDS %[ramptr], %[ramptr], #4\n\t" /* increment ramptr by 4 (size of - a word) */ - "CMP %[ramptr], %[endptr]\n\t" /* compare ramptr and endptr... */ - "BCC 1b\n\t" /* ... and jump back to label 1 if Carrry - Clear (meaning ramptr < endptr) */ - "ORR r0, r0, %[enableEcc]\n\t" /* and re-enable ECC ASAP to be sure no */ - "STR r0, [%[ctrlreg]]\n\t" /* STR occurs with ECC disabled */ - :[ramptr] "+r" (ramptr) - :[endptr] "r" (endptr), - [ctrlreg] "r" (ctrlreg), - [enableEcc] "r" (enableEcc) - : "r0", "r1", /* R0 and R1 used as temporary registers */ - "memory" /* Memory pointed by ramptr is modified */ - ); -} - -#else - -/***************************************************************************//** - * @brief - * DMA read and write existing values (for ECC initialization). - * - * @details - * This function uses DMA to read and write the existing data values in - * the RAM region specified by start and size. The function will use the - * 2 DMA channels specified by the channels[2] array. - * - * @param[in] start - * Start address of address range in RAM to read/write. - * - * @param[in] size - * Size of address range in RAM to read/write. - * - * @param[in] channels[2] - * Array of 2 DMA channels to use. - ******************************************************************************/ -static void mscEccReadWriteExistingDma(uint32_t start, - uint32_t size, - uint32_t channels[2]) -{ - uint32_t descCnt = 0; - volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; - uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); - /* Assert that the 2 DMA channel numbers are different. */ - EFM_ASSERT(channels[0] != channels[1]); - - /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order - to match the total xfer size of the descriptor chain with the largest - ECC RAM bank. */ - EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); - - /* Initialize LDMA descriptor chain. */ - do { - dmaDesc[descCnt][0] = /* DMA desc CTRL word */ - LDMA_CH_CTRL_STRUCTTYPE_TRANSFER - | LDMA_CH_CTRL_STRUCTREQ - | _LDMA_CH_CTRL_XFERCNT_MASK - | LDMA_CH_CTRL_BLOCKSIZE_ALL - | LDMA_CH_CTRL_REQMODE_ALL - | LDMA_CH_CTRL_SRCINC_ONE - | LDMA_CH_CTRL_SIZE_WORD - | LDMA_CH_CTRL_DSTINC_ONE; - - /* source and destination address */ - dmaDesc[descCnt][1] = start; - dmaDesc[descCnt][2] = start; - /* link to next descriptor */ - dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK - | (((uint32_t) &dmaDesc[descCnt + 1][0]) - & _LDMA_CH_LINK_LINKADDR_MASK); - - start += ECC_DMA_DESC_SIZE; - size -= ECC_DMA_DESC_SIZE; - descCnt++; - } while (size); - - /* Make sure descCnt is valid to avoid out-of-bounds access when writing to - dmaDesc array. */ - if ((descCnt < 2) || (descCnt > ECC_DMA_DESCS)) { - while (true) { - EFM_ASSERT(false); - } - } - - /* Now, divide the descriptor list in two parts, one for each channel, - by setting the link bit and address 0 of the descriptor in the middle - to 0. */ - dmaDesc[(descCnt / 2) - 1][3] = 0; - - /* Set last descriptor link bit and address to 0. */ - dmaDesc[descCnt - 1][3] = 0; - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - /* Start the LDMA clock now */ - CMU_ClockEnable(cmuClock_LDMA, true); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - CMU_ClockEnable(cmuClock_LDMAXBAR, true); -#endif -#endif - /* Round robin scheduling for all channels (0 = no fixed priority channels). - */ - LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; -#if defined(LDMA_EN_EN) - LDMA->EN = LDMA_EN_EN; -#endif - LDMA->CHEN = 0; - LDMA->DBGHALT = 0; - LDMA->REQDIS = 0; - - /* Disable LDMA interrupts, and clear interrupt status. */ - LDMA->IEN = 0; -#if defined (LDMA_HAS_SET_CLEAR) - LDMA->IF_CLR = chMask; -#else - LDMA->IFC = chMask; -#endif - - /* Disable looping */ - LDMA->CH[channels[0]].LOOP = 0; - LDMA->CH[channels[1]].LOOP = 0; - - /* Set descriptor address for first channel. */ - LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) - & _LDMA_CH_LINK_LINKADDR_MASK; - /* Set descriptor address for second channel. */ - LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) - & _LDMA_CH_LINK_LINKADDR_MASK; - /* Clear the channel done flags. */ - BUS_RegMaskedClear(&LDMA->CHDONE, chMask); - - /* Start transfer by loading descriptors. */ - LDMA->LINKLOAD = chMask; - - /* Wait until finished. */ - while (!( -#if defined(_LDMA_CHSTATUS_MASK) - ((LDMA->CHSTATUS & chMask) == 0) -#else - ((LDMA->CHEN & chMask) == 0) -#endif - && ((LDMA->CHDONE & chMask) == chMask))) { - } - -#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - /* Stop the LDMA clock now */ - CMU_ClockEnable(cmuClock_LDMA, false); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - CMU_ClockEnable(cmuClock_LDMAXBAR, false); -#endif -#endif -} -#endif // #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_MPAHBRAM_CTRL_MASK) - -/***************************************************************************//** - * @brief - * Initialize ECC for a given memory bank. - * - * @brief - * This function initializes ECC for a given memory bank which is specified - * with the MSC_EccBank_Typedef structure input parameter. - * - * @param[in] eccBank - * ECC memory bank device structure. - * - * @param[in] dmaChannels - * Array of 2 DMA channels that may be used during ECC initialization. - * - ******************************************************************************/ -static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, - uint32_t dmaChannels[2]) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ - || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ - || defined(_MPAHBRAM_CTRL_MASK) - (void) dmaChannels; -#if !defined(_MPAHBRAM_CTRL_MASK) - /* Disable ECC write */ - ECC_CTRL_REG &= ~eccBank->initSyndromeEnable; -#endif - /* Initialize ECC syndromes by using core cpu to load and store the existing - data values in RAM. */ - mscEccReadWriteExistingPio(eccBank); -#else - /* Enable ECC write */ - ECC_CTRL_REG |= eccBank->initSyndromeEnable; - /* Initialize ECC syndromes by using DMA to read and write the existing - data values in RAM. */ - mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); -#endif - - /* Clear any ECC errors that may have been reported before or during - initialization. */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_IFC0_REG = ECC_IFC_MASK; - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_IFC1_REG = ECC_IFC_MASK; - } -#else - ECC_IFC_REG = ECC_IFC_MASK; -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ - -#if !defined(_MPAHBRAM_CTRL_MASK) - /* Enable ECC decoder to detect and report ECC errors. */ - ECC_CTRL_REG |= eccBank->correctionEnable; -#endif - - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * @brief - * Disable ECC for a given memory bank. - * - * @brief - * This function disables ECC for a given memory bank which is specified - * with the MSC_EccBank_Typedef structure input parameter. - * - * @param[in] eccBank - * ECC memory bank device structure. - * - ******************************************************************************/ -static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) -{ - /* Disable ECC write (encoder) and checking (decoder). */ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) - if (eccBank->base == ECC_RAM0_MEM_BASE) { - ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); - } else if (eccBank->base == ECC_RAM1_MEM_BASE) { - ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); - } -#else - ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); -#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ -} - -/***************************************************************************//** - * @brief - * Configure Error Correcting Code (ECC). - * - * @details - * This function configures ECC support according to the configuration - * input parameter. If the user requests enabling ECC for a given RAM bank - * this function will initialize ECC memory (syndromes) for the bank by - * reading and writing the existing values in memory. I.e. all data is - * preserved. The initialization process runs in a critical section - * disallowing interrupts and thread scheduling, and will consume a - * considerable amount of clock cycles. Therefore the user should carefully - * assess where to call this function. The user can consider to increase - * the clock frequency in order to reduce the execution time. - * This function makes use of 2 DMA channels to move data to/from RAM in an - * efficient way. The user can select which 2 DMA channels to use in order - * to avoid conflicts with the application. However the user must make sure - * that no other DMA operations takes place while this function is executing. - * If the application has been using the DMA controller prior to calling this - * function, the application will need to reinitialize DMA registers after - * this function has completed. - * - * @note - * This function protects the ECC initialization procedure from interrupts - * and other threads by using a critical section (defined by em_core.h) - * When running on RTOS the user may need to override CORE_EnterCritical - * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. - * - * @param[in] eccConfig - * ECC configuration - ******************************************************************************/ -void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) -{ - unsigned int cnt; -#if defined(ECC_FAULT_CTRL_REG) - uint32_t faultCtrlReg = ECC_FAULT_CTRL_REG; - /* Disable ECC faults if ecc fault ctrl register is defined. */ - faultCtrlReg &= ~ECC_FAULT_EN; - ECC_FAULT_CTRL_REG = faultCtrlReg; -#endif - - /* Loop through the ECC banks array, enable or disable according to - the eccConfig->enableEccBank array. */ - for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { - if (eccConfig->enableEccBank[cnt]) { - mscEccBankInit(&eccBankTbl[cnt], eccConfig->dmaChannels); - } else { - mscEccBankDisable(&eccBankTbl[cnt]); - } - } - -#if defined(ECC_FAULT_CTRL_REG) && !defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) - /* - * Enable ECC faults if ecc fault ctrl register is set. - * On Series 1 Config 1, aka EFM32GG11, ECC faults should stay disabled. - * Reload register first, in case it was modified and/or shared by bank - * init functions. - */ - faultCtrlReg = ECC_FAULT_CTRL_REG; - faultCtrlReg |= ECC_FAULT_EN; - ECC_FAULT_CTRL_REG = faultCtrlReg; -#endif -} - -#endif /* #if defined(_MSC_ECCCTRL_MASK) */ - -#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) -/***************************************************************************//** - * @brief - * Set MPAHBRAM port to use to access DMEM. - * - * @details - * This function configures which MPAHBRAM slave port is used to access DMEM. - * Depending on the use case, it might improve performance by spreading the - * load over the N ports (N is usually 2 or 4), instead of starving because a - * port is used by another master. - * - * @param[in] master - * AHBHOST master to be configured. - * @param[in] port - * AHBHOST slave port to use. - ******************************************************************************/ -void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port) -{ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - uint32_t bitfieldMask = DMEM_NUM_PORTS - 1; -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1; -#endif - - /* make sure master is within the mask of port map that can be changed - * make sure port is a sensible value - */ - EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0); - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - EFM_ASSERT(port < DMEM_NUM_PORTS); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - EFM_ASSERT(port < DMEM0_NUM_PORTS); -#endif - -#if defined(CMU_CLKEN0_SYSCFG) - bool disableSyscfgClk = false; - - if (!(CMU->CLKEN0 & _CMU_CLKEN0_SYSCFG_MASK)) { - disableSyscfgClk = true; - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - } -#endif - - BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, - bitfieldMask << master, - (uint32_t)port << master); - -#if defined(CMU_CLKEN0_SYSCFG) - if (disableSyscfgClk) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } -#endif -} -#endif - -#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) -/***************************************************************************//** - * @brief - * Set MPAHBRAM port priority for arbitration when multiple concurrent - * transactions to DMEM. - * - * @details - * This function configures which MPAHBRAM slave port will have priority. - * The AHB port arbitration default scheme, round-robin arbitration, is - * selected when portPriority == mscPortPriorityNone. - * - * @note - * Doing this can potentially starve the others AHB port(s). - * - * @param[in] portPriority - * AHBHOST slave port having elevated priority. - ******************************************************************************/ -void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority) -{ -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); - - BUS_RegMaskedWrite(&DMEM->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); - - BUS_RegMaskedWrite(&DMEM0->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); - BUS_RegMaskedWrite(&DMEM1->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, - (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -#endif -} - -/***************************************************************************//** - * @brief - * Get MPAHBRAM port arbitration priority selection. - * - * @details - * This function returns the AHBHOST slave with raised priority. - * - * @return - * Returns the AHBHOST slave port given priority or none. - ******************************************************************************/ -MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void) -{ - uint32_t port = 0; - -#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) - port = BUS_RegMaskedRead(&DMEM->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); -#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) - port = BUS_RegMaskedRead(&DMEM0->CTRL, - _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); -#endif - - return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); -} -#endif /* if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) */ - -/** @} (end addtogroup msc) */ -#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Flash controller (MSC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_msc.h" +#if defined(MSC_COUNT) && (MSC_COUNT > 0) + +#include "sl_assert.h" +#include "em_cmu.h" +#include "sl_common.h" +#include "em_core.h" +#include "em_system.h" + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(__ICCARM__) +/* Suppress warnings originating from use of EFM_ASSERT() with IAR Embedded Workbench */ +#pragma diag_suppress=Ta022,Ta023 +#endif + +#if defined(EM_MSC_RUN_FROM_FLASH) && defined(_EFM32_GECKO_FAMILY) +#error "Running Flash write/erase operations from Flash is not supported on EFM32G." +#endif + +/******************************************************************************* + ****************************** DEFINES ****************************** + ******************************************************************************/ +#if defined(MSC_WRITECTRL_WDOUBLE) +#define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2) +#else +#define WORDS_PER_DATA_PHASE (1) +#endif + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata FLASH_E201 - Potential program failure after Power On */ +#define ERRATA_FIX_FLASH_E201_EN +#endif + +#define FLASH_PAGE_MASK (~(FLASH_PAGE_SIZE - 1U)) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +#if defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) +/* On Series 1 Config 1 EFM32GG11, ECC is supported for RAM0 and RAM1 + banks (not RAM2). It is necessary to figure out which is biggest to + calculate the number of DMA descriptors needed. */ +#define ECC_RAM_SIZE_MAX (SL_MAX(RAM0_MEM_SIZE, RAM1_MEM_SIZE)) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106) +/* On Series 1 Config 2 EFM32GG12, ECC is supported for RAM0, RAM1 and + RAM2 banks. All banks are of equal size. */ +#define ECC_RAM_SIZE_MAX (RAM0_MEM_SIZE) + +#define ECC_RAM0_MEM_BASE (RAM0_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (RAM0_MEM_SIZE) + +#define ECC_RAM1_MEM_BASE (RAM1_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (RAM1_MEM_SIZE) + +#define ECC_RAM2_MEM_BASE (RAM2_MEM_BASE) +#define ECC_RAM2_MEM_SIZE (RAM2_MEM_SIZE) + +#define ECC_CTRL_REG (MSC->ECCCTRL) +#define ECC_RAM0_SYNDROMES_INIT (MSC_ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (MSC_ECCCTRL_RAMECCCHKEN) +#define ECC_RAM1_SYNDROMES_INIT (MSC_ECCCTRL_RAM1ECCEWEN) +#define ECC_RAM1_CORRECTION_EN (MSC_ECCCTRL_RAM1ECCCHKEN) +#define ECC_RAM2_SYNDROMES_INIT (MSC_ECCCTRL_RAM2ECCEWEN) +#define ECC_RAM2_CORRECTION_EN (MSC_ECCCTRL_RAM2ECCCHKEN) + +#define ECC_IFC_REG (MSC->IFC) +#define ECC_IFC_MASK (MSC_IFC_RAMERR1B | MSC_IFC_RAMERR2B \ + | MSC_IFC_RAM1ERR1B | MSC_IFC_RAM1ERR2B \ + | MSC_IFC_RAM2ERR1B | MSC_IFC_RAM2ERR2B) + +#define ECC_FAULT_CTRL_REG (MSC->CTRL) +#define ECC_FAULT_EN (MSC_CTRL_RAMECCERRFAULTEN) + +#elif defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +/* On Series 2 Config 1, aka EFR32XG21, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN) + +#elif (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) + +/* On Series 2 Config 2, aka EFR32XG22, ECC is supported for the + main DMEM RAM banks which is controlled with one ECC encoder/decoder. */ +#define ECC_RAM0_SYNDROMES_INIT (SYSCFG_DMEM0ECCCTRL_RAMECCEN) +#define ECC_RAM0_CORRECTION_EN (SYSCFG_DMEM0ECCCTRL_RAMECCEWEN) + +#define ECC_IF_REG (SYSCFG->IF) +#define ECC_IF_1BIT_ERROR (SYSCFG_IF_RAMERR1B) + +#elif defined(_MPAHBRAM_CTRL_MASK) + +/* From Series 2 Config 3, aka EFR32XG23, ECC is now standalone in the + * MPAHBRAM module */ +#define ECC_RAM0_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM0_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) +#define ECC_RAM1_SYNDROMES_INIT (MPAHBRAM_CTRL_ECCWEN) +#define ECC_RAM1_CORRECTION_EN (MPAHBRAM_CTRL_ECCEN) +#endif + +#define ECC_IF_REG (DMEM->IF) +/* number of AHB ports is between 1 and 4 */ +#if defined(MPAHBRAM_IF_AHB3ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B | MPAHBRAM_IF_AHB3ERR1B) +#elif defined(MPAHBRAM_IF_AHB2ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B | MPAHBRAM_IF_AHB2ERR1B) +#elif defined(MPAHBRAM_IF_AHB1ERR1B) +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B | MPAHBRAM_IF_AHB1ERR1B) +#else +#define ECC_IF_1BIT_ERROR (MPAHBRAM_IF_AHB0ERR1B) +#endif + +#else + +#error "Unknown device" + +#endif /* #if defined(if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) */ + +#define ECC_RAM_SIZE_MAX (RAM_MEM_SIZE) + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + +#define ECC_RAM0_MEM_BASE (DMEM0_RAM0_RAM_MEM_BASE) +#define ECC_RAM0_MEM_SIZE (DMEM0_RAM0_RAM_MEM_SIZE) +#define ECC_RAM1_MEM_BASE (DMEM1_RAM0_RAM_MEM_BASE) +#define ECC_RAM1_MEM_SIZE (DMEM1_RAM0_RAM_MEM_SIZE) + +#define ECC_CTRL0_REG (DMEM0->CTRL) +#define ECC_CTRL1_REG (DMEM1->CTRL) + +#define ECC_IFC0_REG (DMEM0->IF_CLR) +#define ECC_IFC1_REG (DMEM1->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) + +#define ECC_FAULT_CTRL0_REG (DMEM0->CTRL) +#define ECC_FAULT_CTRL1_REG (DMEM1->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) + +#else + +#define ECC_RAM0_MEM_BASE (SRAM_BASE) +#define ECC_RAM0_MEM_SIZE (SRAM_SIZE) + +#if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)) +#define ECC_CTRL_REG (SYSCFG->DMEM0ECCCTRL) +#define ECC_IFC_REG (SYSCFG->IF_CLR) +#define ECC_IFC_MASK (SYSCFG_IF_RAMERR1B | SYSCFG_IF_RAMERR2B) +#define ECC_FAULT_CTRL_REG (SYSCFG->CTRL) +#define ECC_FAULT_EN (SYSCFG_CTRL_RAMECCERRFAULTEN) + +#elif defined(_MPAHBRAM_CTRL_MASK) +#define ECC_CTRL_REG (DMEM->CTRL) +#define ECC_IFC_REG (DMEM->IF_CLR) +#define ECC_IFC_MASK (_MPAHBRAM_IF_MASK) +#define ECC_FAULT_CTRL_REG (DMEM->CTRL) +#define ECC_FAULT_EN (MPAHBRAM_CTRL_ECCERRFAULTEN) +#endif + +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#else + +#error Unknown device. + +#endif + +#define ECC_DMA_MAX_XFERCNT (_LDMA_CH_CTRL_XFERCNT_MASK \ + >> _LDMA_CH_CTRL_XFERCNT_SHIFT) +#define ECC_DMA_DESC_SIZE ((ECC_DMA_MAX_XFERCNT + 1) * 4) /* 4 bytes units */ + +#define ECC_DMA_DESCS (ECC_RAM_SIZE_MAX / ECC_DMA_DESC_SIZE) + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +/***************************************************************************//** + * @brief + * Get locked status of the MSC registers. + * + * @detail + * MSC_IS_LOCKED() is implemented as a macro because it's used inside functions + * that can be placed either in flash or in RAM. + ******************************************************************************/ +#if defined(_MSC_STATUS_REGLOCK_MASK) +#define MSC_IS_LOCKED() ((MSC->STATUS & _MSC_STATUS_REGLOCK_MASK) != 0U) +#else +#define MSC_IS_LOCKED() ((MSC->LOCK & _MSC_LOCK_MASK) != 0U) +#endif + +/******************************************************************************* + ****************************** TYPEDEFS ****************************** + ******************************************************************************/ + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +typedef struct { + uint32_t initSyndromeEnable; + uint32_t correctionEnable; + uint32_t base; + uint32_t size; +} MSC_EccBank_Typedef; + +#endif + +/******************************************************************************* + ****************************** LOCALS ******************************* + ******************************************************************************/ +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) +static const MSC_EccBank_Typedef eccBankTbl[MSC_ECC_BANKS] = +{ + { + ECC_RAM0_SYNDROMES_INIT, ECC_RAM0_CORRECTION_EN, + ECC_RAM0_MEM_BASE, ECC_RAM0_MEM_SIZE + }, +#if MSC_ECC_BANKS > 1 + { + ECC_RAM1_SYNDROMES_INIT, ECC_RAM1_CORRECTION_EN, + ECC_RAM1_MEM_BASE, ECC_RAM1_MEM_SIZE + }, +#if MSC_ECC_BANKS > 2 + { + ECC_RAM2_SYNDROMES_INIT, ECC_RAM2_CORRECTION_EN, + ECC_RAM2_MEM_BASE, ECC_RAM2_MEM_SIZE + }, +#endif +#endif +}; +#endif + +/******************************************************************************* + ****************************** FUNCTIONS ****************************** + ******************************************************************************/ +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadWriteData(uint32_t* data, + uint32_t numWords); + +MSC_RAMFUNC_DECLARATOR MSC_Status_TypeDef +MSC_LoadVerifyAddress(uint32_t* address); + +/** @endcond */ + +/***************************************************************************//** + * @addtogroup msc + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Wait for a specified MSC status or timeout. + * + * @param[in] mask + * MSC->STATUS register mask to apply when testing for specified status. + * @param[in] value + * The value the MSC->STATUS test is waiting to see. + * @return + * Returns the status of a write or erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Specified status criteria fulfilled. + * mscReturnInvalidAddr - Operation tried to write or erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * write or erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef mscStatusWait(uint32_t mask, uint32_t value) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + + while (timeOut) { + uint32_t status = MSC->STATUS; + + /* if INVADDR is asserted by MSC, BUSY will never go high, can be checked early */ + if (status & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + /* + * if requested operation fails because flash is locked, BUSY will be high + * for a few cycles and it's not safe to clear WRITECTRL.WREN during that + * period. mscStatusWait should return only when it's safe to do so. + * + * So if user is checking BUSY flag, make sure it matches user's expected + * value and only then check the lock bits. Otherwise, do check early and + * bail out if necessary. + */ + + if ((!(mask & MSC_STATUS_BUSY)) + && (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK))) { + return mscReturnLocked; + } + + if ((status & mask) == value) { + if (status & (MSC_STATUS_LOCKED | MSC_STATUS_REGLOCK)) { + return mscReturnLocked; + } else { + return mscReturnOk; + } + } + + timeOut--; + } + + return mscReturnTimeOut; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. It is assumed that start address is word + * aligned and that numBytes is an integer multiple of four, and that the + * write operation does not cross a flash page boundary. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +msc_Return_TypeDef writeBurst(uint32_t address, + const uint32_t *data, + uint32_t numBytes) +{ + msc_Return_TypeDef retVal; + + MSC->ADDRB = address; + + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + MSC->WDATA = *data++; + numBytes -= 4; + + while (numBytes) { + retVal = mscStatusWait(MSC_STATUS_WDATAREADY, MSC_STATUS_WDATAREADY); + + if (retVal != mscReturnOk) { + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + return retVal; + } + + MSC->WDATA = *data++; + numBytes -= 4; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Initialize MSC module. Puts MSC hw in a known state. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; +} + +/***************************************************************************//** + * @brief + * Turn off MSC flash write enable and lock MSC registers. + ******************************************************************************/ +void MSC_Deinit(void) +{ + // Unlock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + // Lock MSC + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_CLR = CMU_CLKEN1_MSC; +#endif +} + +/***************************************************************************//** + * @brief + * Set MSC code execution configuration + * + * @param[in] execConfig + * Code execution configuration + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_RDATACTRL_DOUTBUFEN) + mscReadCtrl = MSC->RDATACTRL & ~MSC_RDATACTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_RDATACTRL_DOUTBUFEN; + } + + MSC->RDATACTRL = mscReadCtrl; +#elif defined(MSC_READCTRL_DOUTBUFEN) + mscReadCtrl = MSC->READCTRL & ~MSC_READCTRL_DOUTBUFEN; + + if (execConfig->doutBufEn) { + mscReadCtrl |= MSC_READCTRL_DOUTBUFEN; + } + MSC->READCTRL = mscReadCtrl; +#endif +} + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * @param[in] startAddress + * Pointer to the flash page to erase. Must be aligned to beginning of page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - Operation completed successfully. + * mscReturnInvalidAddr - Operation tried to erase a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * erase a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + MSC_Status_TypeDef retVal; + bool wasLocked; + + // Address must be aligned to page boundary + EFM_ASSERT((((uint32_t)startAddress) & (FLASH_PAGE_SIZE - 1U)) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + + if (retVal == mscReturnOk) { + // We need to check twice to be sure + retVal = mscStatusWait((MSC_STATUS_BUSY | MSC_STATUS_PENDING), 0); + } + + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. Write data must be aligned to words and + * contain a number of bytes that is divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC this will be achieved + * automatically by using attributes in the function proctype. For Keil + * uVision you must define a section called "ram_code" and place this manually + * in your project's scatter file. + * + * The Flash memory is organized into 64-bit wide double-words. + * Each 64-bit double-word can be written only twice using burst write + * operation between erasing cycles. The user's application must store data in + * RAM to sustain burst write operation. + * + * EFR32XG21 RevC is not able to program every word twice before the next erase. + * + * @param[in] address + * Pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * Returns the status of the write operation, @ref MSC_Status_TypeDef + * @verbatim + * flashReturnOk - Operation completed successfully. + * flashReturnInvalidAddr - Operation tried to write to a non-flash area. + * flashReturnLocked - MSC registers are locked or the operation tried to + * program a locked area of the flash. + * flashReturnTimeOut - Operation timed out. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t addr; + const uint8_t *pData; + uint32_t burstLen; + MSC_Status_TypeDef retVal = mscReturnOk; + bool wasLocked; + + // Check alignment (must be aligned to words) + EFM_ASSERT(((uint32_t)address & 0x3U) == 0); + // Check number of bytes, must be divisable by four + EFM_ASSERT((numBytes & 0x3U) == 0); + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + // Enable flash write + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; + + addr = (uint32_t)address; + pData = (uint8_t*)data; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((addr + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - addr); + + if ((retVal = writeBurst(addr, (const uint32_t*)pData, burstLen)) + != mscReturnOk) { + break; + } + + addr += burstLen; + pData += burstLen; + numBytes -= burstLen; + } + + // Disable flash write + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + MSC_Status_TypeDef retVal; + + if (MSC_IS_LOCKED()) { + return mscReturnLocked; + } + + MSC->WRITECTRL_SET = MSC_WRITECTRL_WREN; // Set write enable bit + MSC->MISCLOCKWORD_CLR = MSC_MISCLOCKWORD_MELOCKBIT; // Enable Write ctrl access + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; // Start Mass erase procedure + retVal = mscStatusWait(MSC_STATUS_BUSY, 0); // Wait for end of busy flag or a problem (INVADDR, LOCK, REGLOCK, TIMEOUT) + MSC->MISCLOCKWORD_SET = MSC_MISCLOCKWORD_MELOCKBIT; // Reenable mass erase lock bit + MSC->WRITECTRL_CLR = MSC_WRITECTRL_WREN; // Disable Write ctrl access + + return retVal; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that copying data from flash to flash will be slower than + * copying from RAM to flash. So the source data must be in RAM in order to + * see the write speeds similar to the datasheet numbers. + * + * @note + * This function requires that the LDMA and LDMAXBAR clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash and be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + LDMA->EN_SET = 0x1; + LDMAXBAR->CH[ch].REQSEL = LDMAXBAR_CH_REQSEL_SOURCESEL_MSC + | LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + +#if defined(_CMU_CLKEN1_MASK) + CMU->CLKEN1_SET = CMU_CLKEN1_MSC; +#endif + // Unlock MSC + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN_SET = (0x1 << ch); + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + + LDMA->CHDONE_CLR = (0x1 << ch); + LDMA->CHDIS_SET = (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} + +#else // defined(_SILICON_LABS_32B_SERIES_2) + +/***************************************************************************//** + * @brief + * Enables the flash controller for writing. + * @note + * This function must be called before flash operations when + * AUXHFRCO clock has been changed from a default band. + ******************************************************************************/ +void MSC_Init(void) +{ +#if defined(_MSC_TIMEBASE_MASK) + uint32_t freq, cycles; +#endif + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done. Flash erase and write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Unlock the MSC module. */ + MSC->LOCK = MSC_UNLOCK_CODE; + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_TIMEBASE_MASK) + /* Configure MSC->TIMEBASE according to a selected frequency. */ + freq = CMU_ClockFreqGet(cmuClock_AUX); + + /* Timebase 5us is used for the 1/1.2 MHz band only. Note that the 1 MHz band + is tuned to 1.2 MHz on newer revisions. */ + if (freq > 1200000) { + /* Calculate a number of clock cycles for 1 us as a base period. */ + freq = (freq * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing. */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_1US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } else { + /* Calculate a number of clock cycles for 5 us as a base period. */ + freq = (freq * 5 * 11) / 10; + cycles = (freq / 1000000) + 1; + + /* Configure clock cycles for flash timing */ + MSC->TIMEBASE = (MSC->TIMEBASE & ~(_MSC_TIMEBASE_BASE_MASK + | _MSC_TIMEBASE_PERIOD_MASK)) + | MSC_TIMEBASE_PERIOD_5US + | (cycles << _MSC_TIMEBASE_BASE_SHIFT); + } +#endif +} + +/***************************************************************************//** + * @brief + * Disables the flash controller for writing. + ******************************************************************************/ +void MSC_Deinit(void) +{ + /* Disable writing to the Flash. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + /* Lock the MSC module.*/ + MSC->LOCK = 0; +} + +/***************************************************************************//** + * @brief + * Set the MSC code execution configuration. + * + * @param[in] execConfig + * The code execution configuration. + ******************************************************************************/ +void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig) +{ + uint32_t mscReadCtrl; + +#if defined(MSC_READCTRL_MODE_WS0SCBTP) + mscReadCtrl = MSC->READCTRL & _MSC_READCTRL_MODE_MASK; + if ((mscReadCtrl == MSC_READCTRL_MODE_WS0) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1) && (execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1SCBTP; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS0SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS0; + } else if ((mscReadCtrl == MSC_READCTRL_MODE_WS1SCBTP) && (!execConfig->scbtEn)) { + mscReadCtrl |= MSC_READCTRL_MODE_WS1; + } else { + /* No change needed. */ + } +#endif + + mscReadCtrl = MSC->READCTRL & ~(0 +#if defined(MSC_READCTRL_SCBTP) + | MSC_READCTRL_SCBTP +#endif +#if defined(MSC_READCTRL_USEHPROT) + | MSC_READCTRL_USEHPROT +#endif +#if defined(MSC_READCTRL_PREFETCH) + | MSC_READCTRL_PREFETCH +#endif +#if defined(MSC_READCTRL_ICCDIS) + | MSC_READCTRL_ICCDIS +#endif +#if defined(MSC_READCTRL_AIDIS) + | MSC_READCTRL_AIDIS +#endif +#if defined(MSC_READCTRL_IFCDIS) + | MSC_READCTRL_IFCDIS +#endif + ); + mscReadCtrl |= (0 +#if defined(MSC_READCTRL_SCBTP) + | (execConfig->scbtEn ? MSC_READCTRL_SCBTP : 0) +#endif +#if defined(MSC_READCTRL_USEHPROT) + | (execConfig->useHprot ? MSC_READCTRL_USEHPROT : 0) +#endif +#if defined(MSC_READCTRL_PREFETCH) + | (execConfig->prefetchEn ? MSC_READCTRL_PREFETCH : 0) +#endif +#if defined(MSC_READCTRL_ICCDIS) + | (execConfig->iccDis ? MSC_READCTRL_ICCDIS : 0) +#endif +#if defined(MSC_READCTRL_AIDIS) + | (execConfig->aiDis ? MSC_READCTRL_AIDIS : 0) +#endif +#if defined(MSC_READCTRL_IFCDIS) + | (execConfig->ifcDis ? MSC_READCTRL_IFCDIS : 0) +#endif + ); + + MSC->READCTRL = mscReadCtrl; +} + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/***************************************************************************//** + * @brief + * Perform the address phase of the flash write cycle. + * @details + * This function performs the address phase of a flash write operation by + * writing the given flash address to the ADDRB register and issuing the + * LADDRIM command to load the address. + * @param[in] address + * An address in flash memory. Must be aligned at a 4 byte boundary. + * @return + * Returns the status of the address load operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the Flash. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadVerifyAddress(uint32_t* address) +{ + uint32_t timeOut; + + /* Wait for the MSC to become ready. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Load the address. */ + MSC->ADDRB = (uint32_t)address; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Perform a flash data write phase. + * @details + * This function performs the data phase of a flash write operation by loading + * the given number of 32-bit words to the WDATA register. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numWords + * A number of data words (32-bit) to load. + * @return + * Returns the status of the data load operation. + * @verbatim + * mscReturnOk - An operation completed successfully. + * mscReturnTimeOut - An operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_LoadWriteData(uint32_t* data, + uint32_t numWords) +{ + uint32_t timeOut; + uint32_t wordIndex; + bool useWDouble = false; + MSC_Status_TypeDef retval = mscReturnOk; + +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* If the LPWRITE (Low Power Write) is NOT enabled, set WDOUBLE (Write Double word). */ + if (!(MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE)) { + /* If the number of words to be written is odd, align by writing + a single word first, before setting the WDOUBLE bit. */ + if (numWords & 0x1) { + /* Wait for the MSC to become ready for the next word. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((!(MSC->STATUS & MSC_STATUS_WDATAREADY)) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + + /* Clear the double word option to write the initial single word. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; + /* Write first data word. */ + MSC->WDATA = *data++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + + /* Wait for the operation to finish. It may be required to change the WDOUBLE + configuration after the initial write. It should not be changed while BUSY. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for timeout. */ + if (timeOut == 0) { + return mscReturnTimeOut; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + return mscReturnLocked; + } + /* Subtract this initial odd word for the write loop below. */ + numWords -= 1; + retval = mscReturnOk; + } + /* Set the double word option to write two words per + data phase. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE; + useWDouble = true; + } +#endif /* defined( _MSC_WRITECTRL_LPWRITE_MASK ) && defined( _MSC_WRITECTRL_WDOUBLE_MASK ) */ + + /* Write the rest as a double word write if wordsPerDataPhase == 2 */ + if (numWords > 0) { + /* Requires a system core clock at 1MHz or higher */ + EFM_ASSERT(SystemCoreClock >= 1000000); + wordIndex = 0; + while (wordIndex < numWords) { + if (!useWDouble) { + MSC->WDATA = *data++; + wordIndex++; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; + } else { + /* Trigger a double write according to flash properties. */ +#if defined(_SILICON_LABS_32B_SERIES_0) && defined(_MSC_WRITECTRL_WDOUBLE_MASK) + MSC->WDATA = *data++; + while (!(MSC->STATUS & MSC_STATUS_WDATAREADY)) ; + MSC->WDATA = *data++; + wordIndex += 2; + MSC->WRITECMD = MSC_WRITECMD_WRITEONCE; +#endif + } + + /* Wait for the transaction to finish. */ + timeOut = MSC_PROGRAM_TIMEOUT; + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for a timeout. */ + if (timeOut == 0) { + retval = mscReturnTimeOut; + break; + } + /* Check for a write protected flash area. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + retval = mscReturnLocked; + break; + } +#if defined(_EFM32_GECKO_FAMILY) + MSC->ADDRB += 4; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; +#endif + } + } + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) + /* Clear a double word option, which should not be left on when returning. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif + + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * An internal flash write function. + * @param[in] address + * A write address. + * @param[in] data + * A pointer to the first data word to load. + * @param[in] numBytes + * A nsumber of data bytes to load, which must be a multiple of 4 bytes. + * @return + * Returns the status of the data load operation. + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordI(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + uint32_t wordCount; + uint32_t numWords; + uint32_t pageWords; + uint32_t* pData; + bool wasLocked; + MSC_Status_TypeDef retval = mscReturnOk; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Check alignment (must be aligned to words). */ + EFM_ASSERT(((uint32_t) address & 0x3) == 0); + + /* Check a number of bytes. Must be divisible by four. */ + EFM_ASSERT((numBytes & 0x3) == 0); + +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash write requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Convert bytes to words. */ + numWords = numBytes >> 2; + EFM_ASSERT(numWords > 0); + + /* The following loop splits the data into chunks corresponding to flash pages. + The address is loaded only once per page because the hardware automatically + increments the address internally for each data load inside a page. */ + for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; ) { + /* First, the address is loaded. The address is auto-incremented within a page. + Therefore, the address phase is only needed once for each page. */ + retval = MSC_LoadVerifyAddress(address + wordCount); + if (mscReturnOk != retval) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; + } + /* Compute the number of words to write to the current page. */ + pageWords = + (FLASH_PAGE_SIZE + - (((uint32_t) (address + wordCount)) & (FLASH_PAGE_SIZE - 1))) + / sizeof(uint32_t); + if (pageWords > numWords - wordCount) { + pageWords = numWords - wordCount; + } + /* Write the data in the current page. */ + retval = MSC_LoadWriteData(pData, pageWords); + if (mscReturnOk != retval) { + break; + } + wordCount += pageWords; + pData += pageWords; + } + +#if defined(ERRATA_FIX_FLASH_E201_EN) + /* Fix for errata FLASH_E201 - Potential program failure after Power On. + * + * Check if the first word was programmed correctly. If a failure is detected, + * retry programming of the first word. + * + * A full description of the errata is in the errata document. */ + pData = (uint32_t *) data; + if (*address != *pData) { + retval = MSC_LoadVerifyAddress(address); + if (mscReturnOk == retval) { + retval = MSC_LoadWriteData(pData, 1); + } + } +#endif + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + +#if defined(_MSC_WRITECTRL_WDOUBLE_MASK) +#if (WORDS_PER_DATA_PHASE == 2) + /* Turn off the double word write cycle support. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE; +#endif +#endif + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return retval; +} +MSC_RAMFUNC_DEFINITION_END + +/** @endcond */ + +/***************************************************************************//** + * @brief + * Erases a page in flash memory. + * @note + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, this is + * achieved automatically by using attributes in the function proctype. For Keil + * uVision IDE, define a section called "ram_code" and place this manually in + * the project's scatter file. + * + * @param[in] startAddress + * A pointer to the flash page to erase. Must be aligned to the beginning of the page + * boundary. + * @return + * Returns the status of erase operation, @ref MSC_Status_TypeDef + * @verbatim + * mscReturnOk - The operation completed successfully. + * mscReturnInvalidAddr - The operation tried to erase a non-flash area. + * mscReturnLocked - The operation tried to erase a locked area of the flash. + * mscReturnTimeOut - The operation timed out waiting for the flash operation + * to complete. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) +{ + uint32_t timeOut = MSC_PROGRAM_TIMEOUT; + bool wasLocked; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* An address must be aligned to pages. */ + EFM_ASSERT((((uint32_t) startAddress) & (FLASH_PAGE_SIZE - 1)) == 0); +#if defined(_EMU_STATUS_VSCALE_MASK) && defined(_SILICON_LABS_32B_SERIES_1) + /* VSCALE must be done and flash erase requires VSCALE2. */ + EFM_ASSERT(!(EMU->STATUS & _EMU_STATUS_VSCALEBUSY_MASK)); + EFM_ASSERT((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) == EMU_STATUS_VSCALE_VSCALE2); +#endif + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Load an address. */ + MSC->ADDRB = (uint32_t)startAddress; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + /* Check for an invalid address. */ + if (MSC->STATUS & MSC_STATUS_INVADDR) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnInvalidAddr; + } + + /* Send erase page command. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEPAGE; + + /* Wait for the erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) && (timeOut != 0)) { + timeOut--; + } + /* Check for write protected page. */ + if (MSC->STATUS & MSC_STATUS_LOCKED) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnLocked; + } + if (timeOut == 0) { + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnTimeOut; + } + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + return mscReturnOk; +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is interrupt-safe, but slower than + * MSC_WriteWordFast(), which writes to flash with interrupts disabled. + * Write data must be aligned to words and contain a number of bytes that is + * divisible by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * For the Gecko family, it is required to run this function from RAM. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place it + * manually in the project's scatter file. + * + * This function requires a system core clock at 1 MHz or higher. + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the Flash. + * flashReturnTimeOut - The operation timed out waiting for the flash operation + * to complete, or the MSC module timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWordI(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +/***************************************************************************//** + * @brief + * Writes data to flash memory. This function is faster than MSC_WriteWord(), + * but it disables interrupts. Write data must be aligned to words and contain + * a number of bytes that is divisible by four. + * @warning + * This function is only available for certain devices. + * @note + * It is recommended to erase the flash page before performing a write. + * It is required to run this function from RAM on parts that include a + * flash write buffer. + * + * For IAR Embedded Workbench, Simplicity Studio and GCC, + * this is done automatically by using attributes in the function proctype. + * For Keil uVision IDE, define a section called "ram_code" and place this manually + * in the project's scatter file. + * + * @deprecated + * This function is deprecated, the functionality is the same as calling + * @ref MSC_WriteWord(). + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * A number of bytes to write from the Flash. NB: Must be divisible by four. + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * flashReturnLocked - The operation tried to erase a locked area of the flash. + * flashReturnTimeOut - The operation timed out waiting for flash operation + * to complete. Or the MSC timed out waiting for the software to write + * the next word into the DWORD register. + * @endverbatim + ******************************************************************************/ +MSC_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, + void const *data, + uint32_t numBytes) +{ + return MSC_WriteWord(address, data, numBytes); +} +MSC_RAMFUNC_DEFINITION_END + +#if (_SILICON_LABS_32B_SERIES > 0) +/***************************************************************************//** + * @brief + * Writes data from RAM to flash memory using the DMA. + * + * @details + * This function uses the LDMA to write data to the internal flash memory. + * This is the fastest way to write data to the flash and should be used when + * the application wants to achieve write speeds like they are reported in the + * datasheet. Note that this function only supports writing data from RAM to + * flash, it does not support writing data from flash to flash. + * + * @note + * This function requires that the LDMA clock is enabled. + * + * @param[in] ch + * DMA channel to use + * + * @param[in] address + * A pointer to the flash word to write to. Must be aligned to words. + * + * @param[in] data + * Data to write to flash. Note that this argument must be an address in RAM. + * This function does not support copying data from flash to flash on series-1 + * devices. Must be aligned to words. + * + * @param[in] numBytes + * A number of bytes to write from flash. NB: Must be divisible by four. + * + * @return + * Returns the status of the write operation. + * @verbatim + * flashReturnOk - The operation completed successfully. + * flashReturnInvalidAddr - The operation tried to erase a non-flash area. + * @endverbatim + ******************************************************************************/ +MSC_Status_TypeDef MSC_WriteWordDma(int ch, + uint32_t *address, + const void *data, + uint32_t numBytes) +{ + uint32_t words = numBytes / 4; + uint32_t burstLen; + uint32_t src = (uint32_t) data; + uint32_t dst = (uint32_t) address; + bool wasLocked; + + EFM_ASSERT((ch >= 0) && (ch < (int)DMA_CHAN_COUNT)); + + // Verify that the data argument is in RAM + if (((uint32_t)data < SRAM_BASE) || ((uint32_t)data > (SRAM_BASE + SRAM_SIZE))) { + EFM_ASSERT(false); + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].REQSEL = LDMA_CH_REQSEL_SOURCESEL_MSC + | LDMA_CH_REQSEL_SIGSEL_MSCWDATA; + LDMA->CH[ch].CFG = _LDMA_CH_CFG_RESETVALUE; + LDMA->CH[ch].LOOP = _LDMA_CH_LOOP_RESETVALUE; + LDMA->CH[ch].LINK = _LDMA_CH_LINK_RESETVALUE; + + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + // Enable writing to the MSC module. + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + while (numBytes) { + // Max burst length is up to next flash page boundary + burstLen = SL_MIN(numBytes, + ((dst + FLASH_PAGE_SIZE) & FLASH_PAGE_MASK) - dst); + words = burstLen / 4; + + // Load the address. + MSC->ADDRB = dst; + MSC->WRITECMD = MSC_WRITECMD_LADDRIM; + + // Check for an invalid address. + if (MSC->STATUS & MSC_STATUS_INVADDR) { + return mscReturnInvalidAddr; + } + + LDMA->CH[ch].CTRL = LDMA_CH_CTRL_DSTINC_NONE + | LDMA_CH_CTRL_SIZE_WORD + | ((words - 1) << _LDMA_CH_CTRL_XFERCNT_SHIFT); + LDMA->CH[ch].SRC = (uint32_t)src; + LDMA->CH[ch].DST = (uint32_t)&MSC->WDATA; + + // Enable channel + LDMA->CHEN |= (0x1 << ch); + MSC->WRITECMD = MSC_WRITECMD_WRITETRIG; + + while ((LDMA->CHDONE & (0x1 << ch)) == 0x0) { + ; + } + BUS_RegMaskedClear(&LDMA->CHDONE, (0x1 << ch)); + BUS_RegMaskedClear(&LDMA->CHEN, (0x1 << ch)); + + dst += burstLen; + src += burstLen; + numBytes -= burstLen; + } + + MSC->WRITECMD = MSC_WRITECMD_WRITEEND; + + // Disable writing to the MSC module. + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + return mscReturnOk; +} +#endif + +#if defined(_MSC_MASSLOCK_MASK) +SL_RAMFUNC_DEFINITION_BEGIN +MSC_Status_TypeDef MSC_MassErase(void) +{ + bool wasLocked; + wasLocked = MSC_IS_LOCKED(); + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + /* Enable writing to the MSC module. */ + MSC->WRITECTRL |= MSC_WRITECTRL_WREN; + + /* Unlock the device mass erase. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_UNLOCK; + + /* Erase the first 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN0; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } + +#if ((FLASH_SIZE >= (512 * 1024)) && defined(_MSC_WRITECMD_ERASEMAIN1_MASK)) + /* Erase the second 512 K block. */ + MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1; + + /* Waiting for erase to complete. */ + while ((MSC->STATUS & MSC_STATUS_BUSY) != 0U) { + } +#endif + + /* Restore the mass erase lock. */ + MSC->MASSLOCK = MSC_MASSLOCK_LOCKKEY_LOCK; + + /* Disable writing to the MSC module. */ + MSC->WRITECTRL &= ~MSC_WRITECTRL_WREN; + + if (wasLocked) { + MSC->LOCK = MSC_LOCK_LOCKKEY_LOCK; + } + + /* This will only successfully return if calling function is also in SRAM. */ + return mscReturnOk; +} +SL_RAMFUNC_DEFINITION_END +#endif // defined(_MSC_MASSLOCK_MASK) + +#endif // defined(_SILICON_LABS_32B_SERIES_2) + +#if defined(_MSC_ECCCTRL_MASK) \ + || defined(_SYSCFG_DMEM0ECCCTRL_MASK) \ + || defined(_MPAHBRAM_CTRL_MASK) + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Read and write existing values in RAM (for ECC initialization). + * + * @details + * This function uses core to load and store the existing data + * values in the given RAM bank. + * + * @param[in] eccBank + * Pointer to ECC RAM bank (MSC_EccBank_Typedef) + ******************************************************************************/ +static void mscEccReadWriteExistingPio(const MSC_EccBank_Typedef *eccBank) +{ + volatile uint32_t *ramptr = (volatile uint32_t *) eccBank->base; + const uint32_t *endptr = (const uint32_t *) (eccBank->base + eccBank->size); + volatile uint32_t *ctrlreg; + uint32_t enableEcc; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ctrlreg = &ECC_CTRL0_REG; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ctrlreg = &ECC_CTRL1_REG; + } else { + EFM_ASSERT(0); + return; + } +#else + ctrlreg = &ECC_CTRL_REG; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + + EFM_ASSERT(ramptr < endptr); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) + enableEcc = eccBank->initSyndromeEnable; +#elif defined(_MPAHBRAM_CTRL_MASK) + /* MPAHBRAM ECC requires both ECCEN and ECCWEN to be set for the syndromes + to be written in ECC */ + enableEcc = eccBank->correctionEnable; + + /* Enable ECC syndrome write */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG |= eccBank->initSyndromeEnable; + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG |= eccBank->initSyndromeEnable; + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#endif + +#ifndef __GNUC__ +#define __asm__ asm +#endif + + /* + * Performs a read and write of all RAM address to initialize + * ECC syndromes. ECC is initialized by reading a RAM address + * while ECC is disabled and write it back while ECC is enabled. + * + * HardFault could occur if we try to read values from RAM while ECC + * is enabled and not initialized. In this case, ECC tries to correct the + * value and ended giving the wrong value which could be sometimes an + * non-existing address. + * + * So for ECC initialization to work properly, this must ensures that while + * ECC is enabled, RAM will be accessed only through writes, no reads shall + * occur. It's hard to have such guarantee with C code, because the C + * compiler with optimization settings, can get in the way + * and do some unwanted reads while ECC is enabled. Assembly allows such + * guarantee and let ECC be initialized without triggering errors. + */ + + __asm__ volatile ( + "1:\n\t" /* define label 1 */ + "LDR r1, [%[ramptr]]\n\t" /* load content of ramptr into R1, ECC + is disabled to get a correct value */ + "LDR r0, [%[ctrlreg]]\n\t" /* load ctrlreg content into R0 */ + "ORR r0, r0, %[enableEcc]\n\t" /* OR R0 and enableEcc, and store result + in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + enabled from now on */ + "STR r1, [%[ramptr]]\n\t" /* write back ram content where it was, + syndrome will be written in ECC */ + "BIC r0, r0, %[enableEcc]\n\t" /* bit clear enableEcc from R0, and store + result in R0 */ + "STR r0, [%[ctrlreg]]\n\t" /* write R0 into ctrlreg, ECC is + disabled */ + "ADDS %[ramptr], %[ramptr], #4\n\t" /* increment ramptr by 4 (size of + a word) */ + "CMP %[ramptr], %[endptr]\n\t" /* compare ramptr and endptr... */ + "BCC 1b\n\t" /* ... and jump back to label 1 if Carrry + Clear (meaning ramptr < endptr) */ + "ORR r0, r0, %[enableEcc]\n\t" /* and re-enable ECC ASAP to be sure no */ + "STR r0, [%[ctrlreg]]\n\t" /* STR occurs with ECC disabled */ + :[ramptr] "+r" (ramptr) + :[endptr] "r" (endptr), + [ctrlreg] "r" (ctrlreg), + [enableEcc] "r" (enableEcc) + : "r0", "r1", /* R0 and R1 used as temporary registers */ + "memory" /* Memory pointed by ramptr is modified */ + ); +} + +#else + +/***************************************************************************//** + * @brief + * DMA read and write existing values (for ECC initialization). + * + * @details + * This function uses DMA to read and write the existing data values in + * the RAM region specified by start and size. The function will use the + * 2 DMA channels specified by the channels[2] array. + * + * @param[in] start + * Start address of address range in RAM to read/write. + * + * @param[in] size + * Size of address range in RAM to read/write. + * + * @param[in] channels[2] + * Array of 2 DMA channels to use. + ******************************************************************************/ +static void mscEccReadWriteExistingDma(uint32_t start, + uint32_t size, + uint32_t channels[2]) +{ + uint32_t descCnt = 0; + volatile uint32_t dmaDesc[ECC_DMA_DESCS][4]; + uint32_t chMask = (1 << channels[0]) | (1 << channels[1]); + /* Assert that the 2 DMA channel numbers are different. */ + EFM_ASSERT(channels[0] != channels[1]); + + /* Make sure ECC_RAM_SIZE_MAX is a multiple of ECC_DMA_DESC_SIZE in order + to match the total xfer size of the descriptor chain with the largest + ECC RAM bank. */ + EFM_ASSERT((ECC_RAM_SIZE_MAX % ECC_DMA_DESC_SIZE) == 0); + + /* Initialize LDMA descriptor chain. */ + do { + dmaDesc[descCnt][0] = /* DMA desc CTRL word */ + LDMA_CH_CTRL_STRUCTTYPE_TRANSFER + | LDMA_CH_CTRL_STRUCTREQ + | _LDMA_CH_CTRL_XFERCNT_MASK + | LDMA_CH_CTRL_BLOCKSIZE_ALL + | LDMA_CH_CTRL_REQMODE_ALL + | LDMA_CH_CTRL_SRCINC_ONE + | LDMA_CH_CTRL_SIZE_WORD + | LDMA_CH_CTRL_DSTINC_ONE; + + /* source and destination address */ + dmaDesc[descCnt][1] = start; + dmaDesc[descCnt][2] = start; + /* link to next descriptor */ + dmaDesc[descCnt][3] = LDMA_CH_LINK_LINK + | (((uint32_t) &dmaDesc[descCnt + 1][0]) + & _LDMA_CH_LINK_LINKADDR_MASK); + + start += ECC_DMA_DESC_SIZE; + size -= ECC_DMA_DESC_SIZE; + descCnt++; + } while (size); + + /* Make sure descCnt is valid to avoid out-of-bounds access when writing to + dmaDesc array. */ + if ((descCnt < 2) || (descCnt > ECC_DMA_DESCS)) { + while (true) { + EFM_ASSERT(false); + } + } + + /* Now, divide the descriptor list in two parts, one for each channel, + by setting the link bit and address 0 of the descriptor in the middle + to 0. */ + dmaDesc[(descCnt / 2) - 1][3] = 0; + + /* Set last descriptor link bit and address to 0. */ + dmaDesc[descCnt - 1][3] = 0; + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Start the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, true); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, true); +#endif +#endif + /* Round robin scheduling for all channels (0 = no fixed priority channels). + */ + LDMA->CTRL = 0 << _LDMA_CTRL_NUMFIXED_SHIFT; +#if defined(LDMA_EN_EN) + LDMA->EN = LDMA_EN_EN; +#endif + LDMA->CHEN = 0; + LDMA->DBGHALT = 0; + LDMA->REQDIS = 0; + + /* Disable LDMA interrupts, and clear interrupt status. */ + LDMA->IEN = 0; +#if defined (LDMA_HAS_SET_CLEAR) + LDMA->IF_CLR = chMask; +#else + LDMA->IFC = chMask; +#endif + + /* Disable looping */ + LDMA->CH[channels[0]].LOOP = 0; + LDMA->CH[channels[1]].LOOP = 0; + + /* Set descriptor address for first channel. */ + LDMA->CH[channels[0]].LINK = ((uint32_t)&dmaDesc[0][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Set descriptor address for second channel. */ + LDMA->CH[channels[1]].LINK = ((uint32_t)&dmaDesc[descCnt / 2][0]) + & _LDMA_CH_LINK_LINKADDR_MASK; + /* Clear the channel done flags. */ + BUS_RegMaskedClear(&LDMA->CHDONE, chMask); + + /* Start transfer by loading descriptors. */ + LDMA->LINKLOAD = chMask; + + /* Wait until finished. */ + while (!( +#if defined(_LDMA_CHSTATUS_MASK) + ((LDMA->CHSTATUS & chMask) == 0) +#else + ((LDMA->CHEN & chMask) == 0) +#endif + && ((LDMA->CHDONE & chMask) == chMask))) { + } + +#if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + /* Stop the LDMA clock now */ + CMU_ClockEnable(cmuClock_LDMA, false); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + CMU_ClockEnable(cmuClock_LDMAXBAR, false); +#endif +#endif +} +#endif // #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) || defined(_MPAHBRAM_CTRL_MASK) + +/***************************************************************************//** + * @brief + * Initialize ECC for a given memory bank. + * + * @brief + * This function initializes ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + * @param[in] dmaChannels + * Array of 2 DMA channels that may be used during ECC initialization. + * + ******************************************************************************/ +static void mscEccBankInit(const MSC_EccBank_Typedef *eccBank, + uint32_t dmaChannels[2]) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \ + || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \ + || defined(_MPAHBRAM_CTRL_MASK) + (void) dmaChannels; +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Disable ECC write */ + ECC_CTRL_REG &= ~eccBank->initSyndromeEnable; +#endif + /* Initialize ECC syndromes by using core cpu to load and store the existing + data values in RAM. */ + mscEccReadWriteExistingPio(eccBank); +#else + /* Enable ECC write */ + ECC_CTRL_REG |= eccBank->initSyndromeEnable; + /* Initialize ECC syndromes by using DMA to read and write the existing + data values in RAM. */ + mscEccReadWriteExistingDma(eccBank->base, eccBank->size, dmaChannels); +#endif + + /* Clear any ECC errors that may have been reported before or during + initialization. */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_IFC0_REG = ECC_IFC_MASK; + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_IFC1_REG = ECC_IFC_MASK; + } +#else + ECC_IFC_REG = ECC_IFC_MASK; +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ + +#if !defined(_MPAHBRAM_CTRL_MASK) + /* Enable ECC decoder to detect and report ECC errors. */ + ECC_CTRL_REG |= eccBank->correctionEnable; +#endif + + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * @brief + * Disable ECC for a given memory bank. + * + * @brief + * This function disables ECC for a given memory bank which is specified + * with the MSC_EccBank_Typedef structure input parameter. + * + * @param[in] eccBank + * ECC memory bank device structure. + * + ******************************************************************************/ +static void mscEccBankDisable(const MSC_EccBank_Typedef *eccBank) +{ + /* Disable ECC write (encoder) and checking (decoder). */ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 2) + if (eccBank->base == ECC_RAM0_MEM_BASE) { + ECC_CTRL0_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } else if (eccBank->base == ECC_RAM1_MEM_BASE) { + ECC_CTRL1_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); + } +#else + ECC_CTRL_REG &= ~(eccBank->initSyndromeEnable | eccBank->correctionEnable); +#endif /* defined(DMEM_COUNT) && (DMEM_COUNT == 2) */ +} + +/***************************************************************************//** + * @brief + * Configure Error Correcting Code (ECC). + * + * @details + * This function configures ECC support according to the configuration + * input parameter. If the user requests enabling ECC for a given RAM bank + * this function will initialize ECC memory (syndromes) for the bank by + * reading and writing the existing values in memory. I.e. all data is + * preserved. The initialization process runs in a critical section + * disallowing interrupts and thread scheduling, and will consume a + * considerable amount of clock cycles. Therefore the user should carefully + * assess where to call this function. The user can consider to increase + * the clock frequency in order to reduce the execution time. + * This function makes use of 2 DMA channels to move data to/from RAM in an + * efficient way. The user can select which 2 DMA channels to use in order + * to avoid conflicts with the application. However the user must make sure + * that no other DMA operations takes place while this function is executing. + * If the application has been using the DMA controller prior to calling this + * function, the application will need to reinitialize DMA registers after + * this function has completed. + * + * @note + * This function protects the ECC initialization procedure from interrupts + * and other threads by using a critical section (defined by em_core.h) + * When running on RTOS the user may need to override CORE_EnterCritical + * CORE_ExitCritical which are declared as 'SL_WEAK' in em_core.c. + * + * @param[in] eccConfig + * ECC configuration + ******************************************************************************/ +void MSC_EccConfigSet(MSC_EccConfig_TypeDef *eccConfig) +{ + unsigned int cnt; +#if defined(ECC_FAULT_CTRL_REG) + uint32_t faultCtrlReg = ECC_FAULT_CTRL_REG; + /* Disable ECC faults if ecc fault ctrl register is defined. */ + faultCtrlReg &= ~ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif + + /* Loop through the ECC banks array, enable or disable according to + the eccConfig->enableEccBank array. */ + for (cnt = 0; cnt < MSC_ECC_BANKS; cnt++) { + if (eccConfig->enableEccBank[cnt]) { + mscEccBankInit(&eccBankTbl[cnt], eccConfig->dmaChannels); + } else { + mscEccBankDisable(&eccBankTbl[cnt]); + } + } + +#if defined(ECC_FAULT_CTRL_REG) && !defined(_SILICON_LABS_32B_SERIES_1_CONFIG_1) + /* + * Enable ECC faults if ecc fault ctrl register is set. + * On Series 1 Config 1, aka EFM32GG11, ECC faults should stay disabled. + * Reload register first, in case it was modified and/or shared by bank + * init functions. + */ + faultCtrlReg = ECC_FAULT_CTRL_REG; + faultCtrlReg |= ECC_FAULT_EN; + ECC_FAULT_CTRL_REG = faultCtrlReg; +#endif +} + +#endif /* #if defined(_MSC_ECCCTRL_MASK) */ + +#if defined(_SYSCFG_DMEM0PORTMAPSEL_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port to use to access DMEM. + * + * @details + * This function configures which MPAHBRAM slave port is used to access DMEM. + * Depending on the use case, it might improve performance by spreading the + * load over the N ports (N is usually 2 or 4), instead of starving because a + * port is used by another master. + * + * @param[in] master + * AHBHOST master to be configured. + * @param[in] port + * AHBHOST slave port to use. + ******************************************************************************/ +void MSC_DmemPortMapSet(MSC_DmemMaster_TypeDef master, uint8_t port) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + uint32_t bitfieldMask = DMEM_NUM_PORTS - 1; +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + uint32_t bitfieldMask = DMEM0_NUM_PORTS - 1; +#endif + + /* make sure master is within the mask of port map that can be changed + * make sure port is a sensible value + */ + EFM_ASSERT(((1 << master) & _SYSCFG_DMEM0PORTMAPSEL_MASK) != 0x0); + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(port < DMEM_NUM_PORTS); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(port < DMEM0_NUM_PORTS); +#endif + +#if defined(CMU_CLKEN0_SYSCFG) + bool disableSyscfgClk = false; + + if (!(CMU->CLKEN0 & _CMU_CLKEN0_SYSCFG_MASK)) { + disableSyscfgClk = true; + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + } +#endif + + BUS_RegMaskedWrite(&SYSCFG->DMEM0PORTMAPSEL, + bitfieldMask << master, + (uint32_t)port << master); + +#if defined(CMU_CLKEN0_SYSCFG) + if (disableSyscfgClk) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } +#endif +} +#endif + +#if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) +/***************************************************************************//** + * @brief + * Set MPAHBRAM port priority for arbitration when multiple concurrent + * transactions to DMEM. + * + * @details + * This function configures which MPAHBRAM slave port will have priority. + * The AHB port arbitration default scheme, round-robin arbitration, is + * selected when portPriority == mscPortPriorityNone. + * + * @note + * Doing this can potentially starve the others AHB port(s). + * + * @param[in] portPriority + * AHBHOST slave port having elevated priority. + ******************************************************************************/ +void MSC_PortSetPriority(MSC_PortPriority_TypeDef portPriority) +{ +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + EFM_ASSERT(portPriority < ((DMEM_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + EFM_ASSERT(portPriority < ((DMEM0_NUM_PORTS + 1) << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT)); + + BUS_RegMaskedWrite(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); + BUS_RegMaskedWrite(&DMEM1->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK, + (uint32_t)portPriority << _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +#endif +} + +/***************************************************************************//** + * @brief + * Get MPAHBRAM port arbitration priority selection. + * + * @details + * This function returns the AHBHOST slave with raised priority. + * + * @return + * Returns the AHBHOST slave port given priority or none. + ******************************************************************************/ +MSC_PortPriority_TypeDef MSC_PortGetCurrentPriority(void) +{ + uint32_t port = 0; + +#if defined(DMEM_COUNT) && (DMEM_COUNT == 1) + port = BUS_RegMaskedRead(&DMEM->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#elif defined(DMEM_COUNT) && (DMEM_COUNT == 2) + port = BUS_RegMaskedRead(&DMEM0->CTRL, + _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK); +#endif + + return (MSC_PortPriority_TypeDef)(port >> _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT); +} +#endif /* if defined(_MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK) */ + +/** @} (end addtogroup msc) */ +#endif /* defined(MSC_COUNT) && (MSC_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c index 3dbfc4d..8c0a858 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_prs.c @@ -1,661 +1,661 @@ -/***************************************************************************//** - * @file - * @brief Peripheral Reflex System (PRS) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_prs.h" -#if defined(PRS_COUNT) && (PRS_COUNT > 0) - -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup prs PRS - Peripheral Reflex System - * @brief Peripheral Reflex System (PRS) Peripheral API - * @details - * This module contains functions to control the PRS peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous - * communication between peripherals on the MCU or SoC. - * @{ - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/* Generic defines for async and sync signals applying to all TIMER instances. - * Those defines map to TIMER2 but it could be any TIMER instance number. */ -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 -#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 - -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 -#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get PRS source signal for a channel. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] ch - * channel number. - * - * @return - * PRS signal assigned to the channel. - ******************************************************************************/ -static PRS_Signal_t getSignal(unsigned int ch, PRS_ChType_t type) -{ - PRS_Signal_t signal; - -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) - if (type == prsTypeAsync) { - signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL - & (_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK)); - } else { - signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL - & (_PRS_SYNC_CH_CTRL_SOURCESEL_MASK | _PRS_SYNC_CH_CTRL_SIGSEL_MASK)); - } -#else - (void) type; - signal = (PRS_Signal_t) (PRS->CH[ch].CTRL - & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK)); -#endif - return signal; -} - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Convert an async PRS source to a sync source. - * - * @details - * This conversion must be done because the id's of the same peripheral - * source is different depending on if it's used as an asynchronous PRS source - * or a synchronous PRS source. - * - * @param[in] asyncSource - * The id of the asynchronous PRS source. - * - * @return - * The id of the corresponding synchronous PRS source. - ******************************************************************************/ -uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource) -{ - uint32_t syncSource = 0; - - switch (asyncSource) { - case _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_NONE; - break; -#if defined(IADC_PRESENT) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; - break; -#endif - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; - break; - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; - break; -#if defined(TIMER4) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4; - break; -#endif -#if defined(TIMER5) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5; - break; -#endif -#if defined(TIMER6) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6; - break; -#endif -#if defined(TIMER7) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7; - break; -#endif -#if defined(VDAC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0; - break; -#endif -#if defined(VDAC1) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: - syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1; - break; -#endif - default: - EFM_ASSERT(false); - break; - } - return syncSource; -} - -/***************************************************************************//** - * @brief - * Convert an async PRS signal to a sync signal. - * - * @details - * PRS values for some peripherals signals differ between asynchronous and - * synchronous PRS channels. This function must be used to handle the - * conversion. - * - * @param[in] asyncSource - * The id of the asynchronous PRS source. - * - * @param[in] asyncSignal - * The id of the asynchronous PRS signal. - * - * @return - * The id of the corresponding synchronous PRS signal. - ******************************************************************************/ -uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) -{ - uint32_t syncSignal = asyncSignal; - - switch (asyncSource) { - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: -#endif -#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: -#endif - /* Async and sync signal values are consistent across all timers instances. - * Generic defines are used. */ - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#if defined(IADC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(VDAC0) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif -#if defined(VDAC1) - case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: - switch (asyncSignal) { - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC; - break; - case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC: - syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC; - break; - default: - EFM_ASSERT(false); - break; - } - break; -#endif - default: - // No translation - break; - } - return syncSignal; -} -#endif - -/***************************************************************************//** - * @brief - * Set a source and signal for a channel. - * - * @param[in] ch - * A channel to define the signal and source for. - * - * @param[in] source - * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. - * - * @param[in] signal - * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x - * defines. - * - * @param[in] edge - * An edge (for selected source/signal) to generate the pulse for. - ******************************************************************************/ -void PRS_SourceSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal, - PRS_Edge_TypeDef edge) -{ -#if defined(_PRS_SYNC_CH_CTRL_MASK) - (void) edge; - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) - | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); -#else - EFM_ASSERT(ch < PRS_CHAN_COUNT); - PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) - | (signal & _PRS_CH_CTRL_SIGSEL_MASK) - | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; -#endif -} - -#if defined(PRS_ASYNC_SUPPORTED) -/***************************************************************************//** - * @brief - * Set the source and asynchronous signal for a channel. - * - * @details - * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in - * EM2/EM3. - * There is a limitation to reflexes operating in asynchronous mode in - * that they can only be used by a subset of the reflex consumers. See - * the PRS chapter in the reference manual for the complete list of - * supported asynchronous signals and consumers. - * - * @note - * This function is not supported on EFM32GxxxFyyy parts. - * In asynchronous mode, the edge detector only works in EM0 and should - * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) - * by default. - * - * @param[in] ch - * A channel to define the source and asynchronous signal for. - * - * @param[in] source - * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. - * - * @param[in] signal - * An asynchronous signal (for selected @p source) to use. Use one of the - * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. - ******************************************************************************/ -void PRS_SourceAsyncSignalSet(unsigned int ch, - uint32_t source, - uint32_t signal) -{ - PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); -} -#endif - -#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) -/***************************************************************************//** - * @brief - * Send the output of a PRS channel to a GPIO pin. - * - * @details - * This function is used to send the output of a PRS channel to a GPIO pin. - * Note that there are certain restrictions to where a PRS channel can be - * routed. Consult the datasheet of the device to see if a channel can be - * routed to the requested GPIO pin. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] location - * PRS routing location. - ******************************************************************************/ -void PRS_GpioOutputLocation(unsigned int ch, - unsigned int location) -{ - EFM_ASSERT(ch < PRS_CHAN_COUNT); - -#if defined(_PRS_ROUTE_MASK) - PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) - | (1 << ch); -#else - uint32_t shift = (ch % 4) * 8; - uint32_t mask = location << shift; - uint32_t locationGroup = ch / 4; - /* Since all ROUTELOCx registers are in consecutive memory locations, treat them - * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ - volatile uint32_t * routeloc = &PRS->ROUTELOC0; - routeloc[locationGroup] |= mask; - PRS->ROUTEPEN |= 1 << ch; -#endif -} -#endif - -/***************************************************************************//** - * @brief - * Search for the first free PRS channel. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @return - * Channel number >= 0 if an unused PRS channel was found. If no free PRS - * channel was found then -1 is returned. - ******************************************************************************/ -int PRS_GetFreeChannel(PRS_ChType_t type) -{ - int ch = -1; - PRS_Signal_t signal; - int max; - - if (type == prsTypeAsync) { - max = PRS_ASYNC_CHAN_COUNT; - } else { - max = PRS_SYNC_CHAN_COUNT; - } - - for (int i = 0; i < max; i++) { - signal = getSignal(i, type); - if (signal == prsSignalNone) { - ch = i; - break; - } - } - return ch; -} - -/***************************************************************************//** - * @brief - * Reset all PRS channels - * - * @details - * This function will reset all the PRS channel configuration. - ******************************************************************************/ -void PRS_Reset(void) -{ - unsigned int i; - -#if defined(_SILICON_LABS_32B_SERIES_2) - PRS->ASYNC_SWLEVEL = 0; - for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { - PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; - } - for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { - PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; - } -#else - PRS->SWLEVEL = 0x0; - for (i = 0; i < PRS_CHAN_COUNT; i++) { - PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; - } -#endif -} - -/***************************************************************************//** - * @brief - * Connect a PRS signal to a channel. - * - * @details - * This function will make the PRS signal available on the specific channel. - * Only a single PRS signal can be connected to any given channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] signal - * This is the PRS signal that should be placed on the channel. - ******************************************************************************/ -void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) -{ -#if defined(_PRS_ASYNC_CH_CTRL_MASK) - // Series 2 devices - uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) - >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; - uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) - >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; - if (type == prsTypeAsync) { - EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); - PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A - | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) - | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); - } else { - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - signalField = PRS_ConvertToSyncSignal(sourceField, signalField); - sourceField = PRS_ConvertToSyncSource(sourceField); - PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) - | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); - } -#else - // Series 0 and Series 1 devices - uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK - | _PRS_CH_CTRL_SIGSEL_MASK); - if (type == prsTypeAsync) { -#if defined(PRS_ASYNC_SUPPORTED) - EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); - PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF - | PRS_CH_CTRL_ASYNC - | signalField; -#endif - } else { - EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); - PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF - | signalField; - } -#endif -} - -#if defined(_SILICON_LABS_32B_SERIES_2) -/***************************************************************************//** - * @brief - * Connect a peripheral consumer to a PRS channel. - * - * @details - * Different peripherals can use PRS channels as their input. This function - * can be used to connect a peripheral consumer to a PRS channel. Multiple - * consumers can be connected to a single PRS channel. - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] consumer - * This is the PRS consumer. - ******************************************************************************/ -void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) -{ - EFM_ASSERT((uint32_t)consumer <= 0xFFF); - volatile uint32_t * addr = (volatile uint32_t *) PRS; - uint32_t offset = (uint32_t) consumer; - addr = addr + offset / 4; - - if (consumer != prsConsumerNone) { - if (type == prsTypeAsync) { - *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; - } else { - *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; - } - } -} - -/***************************************************************************//** - * @brief - * Send the output of a PRS channel to a GPIO pin. - * - * @details - * This function is used to send the output of a PRS channel to a GPIO pin. - * Note that there are certain restrictions to where a PRS channel can be - * routed. Consult the datasheet of the device to see if a channel can be - * routed to the requested GPIO pin. Some devices for instance can only route - * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 - * can only be routed to GPIO pins PCx and PDx - * - * @param[in] ch - * PRS channel number. - * - * @param[in] type - * PRS channel type. This can be either @ref prsTypeAsync or - * @ref prsTypeSync. - * - * @param[in] port - * GPIO port - * - * @param[in] pin - * GPIO pin - ******************************************************************************/ -void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) -{ - volatile uint32_t * addr; - if (type == prsTypeAsync) { - addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; - } else { - addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; - } - addr += ch; - *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) - | ((uint32_t)pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); - - if (type == prsTypeAsync) { - GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); - } else { - GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); - } -} - -/***************************************************************************//** - * @brief - * Combine two PRS channels using a logic function. - * - * @details - * This function allows you to combine the output of one PRS channel with the - * the signal of another PRS channel using various logic functions. Note that - * for series 2, config 1 devices, the hardware only allows a PRS channel to - * be combined with the previous channel. So for instance channel 5 can be - * combined only with channel 4. - * - * The logic function operates on two PRS channels called A and B. The output - * of PRS channel B is combined with the PRS source configured for channel A - * to produce an output. This output is used as the output of channel A. - * - * @param[in] chA - * PRS Channel for the A input. - * - * @param[in] chB - * PRS Channel for the B input. - * - * @param[in] logic - * The logic function to use when combining the Channel A and Channel B. The - * output of the logic function is the output of Channel A. Function like - * AND, OR, XOR, NOT and more are available. - ******************************************************************************/ -void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) -{ - EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); - EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); - PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) - | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); - -#else - PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL - & ~(_PRS_ASYNC_CH_CTRL_FNSEL_MASK - | _PRS_ASYNC_CH_CTRL_AUXSEL_MASK)) - | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT) - | ((uint32_t)chB << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT); -#endif -} -#endif - -/** @} (end addtogroup prs) */ -#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Peripheral Reflex System (PRS) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_prs.h" +#if defined(PRS_COUNT) && (PRS_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup prs PRS - Peripheral Reflex System + * @brief Peripheral Reflex System (PRS) Peripheral API + * @details + * This module contains functions to control the PRS peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The PRS allows configurable, fast, and autonomous + * communication between peripherals on the MCU or SoC. + * @{ + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/* Generic defines for async and sync signals applying to all TIMER instances. + * Those defines map to TIMER2 but it could be any TIMER instance number. */ +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_ASYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2UF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2OF +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC0 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC1 +#define _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2 _PRS_SYNC_CH_CTRL_SIGSEL_TIMER2CC2 + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get PRS source signal for a channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] ch + * channel number. + * + * @return + * PRS signal assigned to the channel. + ******************************************************************************/ +static PRS_Signal_t getSignal(unsigned int ch, PRS_ChType_t type) +{ + PRS_Signal_t signal; + +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + if (type == prsTypeAsync) { + signal = (PRS_Signal_t) (PRS->ASYNC_CH[ch].CTRL + & (_PRS_ASYNC_CH_CTRL_SOURCESEL_MASK | _PRS_ASYNC_CH_CTRL_SIGSEL_MASK)); + } else { + signal = (PRS_Signal_t) (PRS->SYNC_CH[ch].CTRL + & (_PRS_SYNC_CH_CTRL_SOURCESEL_MASK | _PRS_SYNC_CH_CTRL_SIGSEL_MASK)); + } +#else + (void) type; + signal = (PRS_Signal_t) (PRS->CH[ch].CTRL + & (_PRS_CH_CTRL_SOURCESEL_MASK | _PRS_CH_CTRL_SIGSEL_MASK)); +#endif + return signal; +} + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Convert an async PRS source to a sync source. + * + * @details + * This conversion must be done because the id's of the same peripheral + * source is different depending on if it's used as an asynchronous PRS source + * or a synchronous PRS source. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @return + * The id of the corresponding synchronous PRS source. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSource(uint32_t asyncSource) +{ + uint32_t syncSource = 0; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_NONE: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_NONE; + break; +#if defined(IADC_PRESENT) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_IADC0; + break; +#endif + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER0; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER1; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER2; + break; + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER3; + break; +#if defined(TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER4; + break; +#endif +#if defined(TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER5; + break; +#endif +#if defined(TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER6; + break; +#endif +#if defined(TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_TIMER7; + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC0; + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + syncSource = _PRS_SYNC_CH_CTRL_SOURCESEL_VDAC1; + break; +#endif + default: + EFM_ASSERT(false); + break; + } + return syncSource; +} + +/***************************************************************************//** + * @brief + * Convert an async PRS signal to a sync signal. + * + * @details + * PRS values for some peripherals signals differ between asynchronous and + * synchronous PRS channels. This function must be used to handle the + * conversion. + * + * @param[in] asyncSource + * The id of the asynchronous PRS source. + * + * @param[in] asyncSignal + * The id of the asynchronous PRS signal. + * + * @return + * The id of the corresponding synchronous PRS signal. + ******************************************************************************/ +uint32_t PRS_ConvertToSyncSignal(uint32_t asyncSource, uint32_t asyncSignal) +{ + uint32_t syncSignal = asyncSignal; + + switch (asyncSource) { + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER0: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER1: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER2: + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER3: +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER4: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER5: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER6: +#endif +#if defined(_PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_TIMER7: +#endif + /* Async and sync signal values are consistent across all timers instances. + * Generic defines are used. */ + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERUF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERUF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMEROF: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMEROF; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC0: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC0; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC1: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC1; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_TIMERCC2: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_TIMERCC2; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#if defined(IADC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_IADC0: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANENTRYDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SCANTABLEDONE; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_IADC0SINGLEDONE; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC0) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC0L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC0LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC0CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif +#if defined(VDAC1) + case _PRS_ASYNC_CH_CTRL_SOURCESEL_VDAC1L: + switch (asyncSignal) { + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH0DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH0DONESYNC; + break; + case _PRS_ASYNC_CH_CTRL_SIGSEL_VDAC1LCH1DONEASYNC: + syncSignal = _PRS_SYNC_CH_CTRL_SIGSEL_VDAC1CH1DONESYNC; + break; + default: + EFM_ASSERT(false); + break; + } + break; +#endif + default: + // No translation + break; + } + return syncSignal; +} +#endif + +/***************************************************************************//** + * @brief + * Set a source and signal for a channel. + * + * @param[in] ch + * A channel to define the signal and source for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * A signal (for selected @p source) to use. Use one of PRS_CH_CTRL_SIGSEL_x + * defines. + * + * @param[in] edge + * An edge (for selected source/signal) to generate the pulse for. + ******************************************************************************/ +void PRS_SourceSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal, + PRS_Edge_TypeDef edge) +{ +#if defined(_PRS_SYNC_CH_CTRL_MASK) + (void) edge; + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->SYNC_CH[ch].CTRL = (source & _PRS_SYNC_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_SYNC_CH_CTRL_SIGSEL_MASK); +#else + EFM_ASSERT(ch < PRS_CHAN_COUNT); + PRS->CH[ch].CTRL = (source & _PRS_CH_CTRL_SOURCESEL_MASK) + | (signal & _PRS_CH_CTRL_SIGSEL_MASK) + | (uint32_t)edge << _PRS_CH_CTRL_EDSEL_SHIFT; +#endif +} + +#if defined(PRS_ASYNC_SUPPORTED) +/***************************************************************************//** + * @brief + * Set the source and asynchronous signal for a channel. + * + * @details + * Asynchronous reflexes are not clocked on HFPERCLK and can be used even in + * EM2/EM3. + * There is a limitation to reflexes operating in asynchronous mode in + * that they can only be used by a subset of the reflex consumers. See + * the PRS chapter in the reference manual for the complete list of + * supported asynchronous signals and consumers. + * + * @note + * This function is not supported on EFM32GxxxFyyy parts. + * In asynchronous mode, the edge detector only works in EM0 and should + * not be used. The EDSEL parameter in PRS_CHx_CTRL register is set to 0 (OFF) + * by default. + * + * @param[in] ch + * A channel to define the source and asynchronous signal for. + * + * @param[in] source + * A source to select for the channel. Use one of PRS_CH_CTRL_SOURCESEL_x defines. + * + * @param[in] signal + * An asynchronous signal (for selected @p source) to use. Use one of the + * PRS_CH_CTRL_SIGSEL_x defines that support asynchronous operation. + ******************************************************************************/ +void PRS_SourceAsyncSignalSet(unsigned int ch, + uint32_t source, + uint32_t signal) +{ + PRS_ConnectSignal(ch, prsTypeAsync, (PRS_Signal_t) (source | signal)); +} +#endif + +#if defined(_PRS_ROUTELOC0_MASK) || (defined(_PRS_ROUTE_MASK) && (_PRS_ROUTE_MASK)) +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] location + * PRS routing location. + ******************************************************************************/ +void PRS_GpioOutputLocation(unsigned int ch, + unsigned int location) +{ + EFM_ASSERT(ch < PRS_CHAN_COUNT); + +#if defined(_PRS_ROUTE_MASK) + PRS->ROUTE |= (location << _PRS_ROUTE_LOCATION_SHIFT) + | (1 << ch); +#else + uint32_t shift = (ch % 4) * 8; + uint32_t mask = location << shift; + uint32_t locationGroup = ch / 4; + /* Since all ROUTELOCx registers are in consecutive memory locations, treat them + * as an array starting at ROUTELOC0 and use locationGroup to index into this array */ + volatile uint32_t * routeloc = &PRS->ROUTELOC0; + routeloc[locationGroup] |= mask; + PRS->ROUTEPEN |= 1 << ch; +#endif +} +#endif + +/***************************************************************************//** + * @brief + * Search for the first free PRS channel. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @return + * Channel number >= 0 if an unused PRS channel was found. If no free PRS + * channel was found then -1 is returned. + ******************************************************************************/ +int PRS_GetFreeChannel(PRS_ChType_t type) +{ + int ch = -1; + PRS_Signal_t signal; + int max; + + if (type == prsTypeAsync) { + max = PRS_ASYNC_CHAN_COUNT; + } else { + max = PRS_SYNC_CHAN_COUNT; + } + + for (int i = 0; i < max; i++) { + signal = getSignal(i, type); + if (signal == prsSignalNone) { + ch = i; + break; + } + } + return ch; +} + +/***************************************************************************//** + * @brief + * Reset all PRS channels + * + * @details + * This function will reset all the PRS channel configuration. + ******************************************************************************/ +void PRS_Reset(void) +{ + unsigned int i; + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRS->ASYNC_SWLEVEL = 0; + for (i = 0; i < PRS_ASYNC_CHAN_COUNT; i++) { + PRS->ASYNC_CH[i].CTRL = _PRS_ASYNC_CH_CTRL_RESETVALUE; + } + for (i = 0; i < PRS_SYNC_CHAN_COUNT; i++) { + PRS->SYNC_CH[i].CTRL = _PRS_SYNC_CH_CTRL_RESETVALUE; + } +#else + PRS->SWLEVEL = 0x0; + for (i = 0; i < PRS_CHAN_COUNT; i++) { + PRS->CH[i].CTRL = _PRS_CH_CTRL_RESETVALUE; + } +#endif +} + +/***************************************************************************//** + * @brief + * Connect a PRS signal to a channel. + * + * @details + * This function will make the PRS signal available on the specific channel. + * Only a single PRS signal can be connected to any given channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] signal + * This is the PRS signal that should be placed on the channel. + ******************************************************************************/ +void PRS_ConnectSignal(unsigned int ch, PRS_ChType_t type, PRS_Signal_t signal) +{ +#if defined(_PRS_ASYNC_CH_CTRL_MASK) + // Series 2 devices + uint32_t sourceField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SOURCESEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT; + uint32_t signalField = ((uint32_t)signal & _PRS_ASYNC_CH_CTRL_SIGSEL_MASK) + >> _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT; + if (type == prsTypeAsync) { + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->ASYNC_CH[ch].CTRL = PRS_ASYNC_CH_CTRL_FNSEL_A + | (sourceField << _PRS_ASYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_ASYNC_CH_CTRL_SIGSEL_SHIFT); + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + signalField = PRS_ConvertToSyncSignal(sourceField, signalField); + sourceField = PRS_ConvertToSyncSource(sourceField); + PRS->SYNC_CH[ch].CTRL = (sourceField << _PRS_SYNC_CH_CTRL_SOURCESEL_SHIFT) + | (signalField << _PRS_SYNC_CH_CTRL_SIGSEL_SHIFT); + } +#else + // Series 0 and Series 1 devices + uint32_t signalField = (uint32_t) signal & (_PRS_CH_CTRL_SOURCESEL_MASK + | _PRS_CH_CTRL_SIGSEL_MASK); + if (type == prsTypeAsync) { +#if defined(PRS_ASYNC_SUPPORTED) + EFM_ASSERT(ch < PRS_ASYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | PRS_CH_CTRL_ASYNC + | signalField; +#endif + } else { + EFM_ASSERT(ch < PRS_SYNC_CHAN_COUNT); + PRS->CH[ch].CTRL = PRS_CH_CTRL_EDSEL_OFF + | signalField; + } +#endif +} + +#if defined(_SILICON_LABS_32B_SERIES_2) +/***************************************************************************//** + * @brief + * Connect a peripheral consumer to a PRS channel. + * + * @details + * Different peripherals can use PRS channels as their input. This function + * can be used to connect a peripheral consumer to a PRS channel. Multiple + * consumers can be connected to a single PRS channel. + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] consumer + * This is the PRS consumer. + ******************************************************************************/ +void PRS_ConnectConsumer(unsigned int ch, PRS_ChType_t type, PRS_Consumer_t consumer) +{ + EFM_ASSERT((uint32_t)consumer <= 0xFFF); + volatile uint32_t * addr = (volatile uint32_t *) PRS; + uint32_t offset = (uint32_t) consumer; + addr = addr + offset / 4; + + if (consumer != prsConsumerNone) { + if (type == prsTypeAsync) { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + *addr = ch << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} + +/***************************************************************************//** + * @brief + * Send the output of a PRS channel to a GPIO pin. + * + * @details + * This function is used to send the output of a PRS channel to a GPIO pin. + * Note that there are certain restrictions to where a PRS channel can be + * routed. Consult the datasheet of the device to see if a channel can be + * routed to the requested GPIO pin. Some devices for instance can only route + * the async channels 0-5 on GPIO pins PAx and PBx while async channels 6-11 + * can only be routed to GPIO pins PCx and PDx + * + * @param[in] ch + * PRS channel number. + * + * @param[in] type + * PRS channel type. This can be either @ref prsTypeAsync or + * @ref prsTypeSync. + * + * @param[in] port + * GPIO port + * + * @param[in] pin + * GPIO pin + ******************************************************************************/ +void PRS_PinOutput(unsigned int ch, PRS_ChType_t type, GPIO_Port_TypeDef port, uint8_t pin) +{ + volatile uint32_t * addr; + if (type == prsTypeAsync) { + addr = &GPIO->PRSROUTE[0].ASYNCH0ROUTE; + } else { + addr = &GPIO->PRSROUTE[0].SYNCH0ROUTE; + } + addr += ch; + *addr = ((uint32_t)port << _GPIO_PRS_ASYNCH0ROUTE_PORT_SHIFT) + | ((uint32_t)pin << _GPIO_PRS_ASYNCH0ROUTE_PIN_SHIFT); + + if (type == prsTypeAsync) { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_ASYNCH0PEN_SHIFT); + } else { + GPIO->PRSROUTE[0].ROUTEEN |= 0x1 << (ch + _GPIO_PRS_ROUTEEN_SYNCH0PEN_SHIFT); + } +} + +/***************************************************************************//** + * @brief + * Combine two PRS channels using a logic function. + * + * @details + * This function allows you to combine the output of one PRS channel with the + * the signal of another PRS channel using various logic functions. Note that + * for series 2, config 1 devices, the hardware only allows a PRS channel to + * be combined with the previous channel. So for instance channel 5 can be + * combined only with channel 4. + * + * The logic function operates on two PRS channels called A and B. The output + * of PRS channel B is combined with the PRS source configured for channel A + * to produce an output. This output is used as the output of channel A. + * + * @param[in] chA + * PRS Channel for the A input. + * + * @param[in] chB + * PRS Channel for the B input. + * + * @param[in] logic + * The logic function to use when combining the Channel A and Channel B. The + * output of the logic function is the output of Channel A. Function like + * AND, OR, XOR, NOT and more are available. + ******************************************************************************/ +void PRS_Combine(unsigned int chA, unsigned int chB, PRS_Logic_t logic) +{ + EFM_ASSERT(chA < PRS_ASYNC_CHAN_COUNT); + EFM_ASSERT(chB < PRS_ASYNC_CHAN_COUNT); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + EFM_ASSERT(chA == ((chB + 1) % PRS_ASYNC_CHAN_COUNT)); + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); + +#else + PRS->ASYNC_CH[chA].CTRL = (PRS->ASYNC_CH[chA].CTRL + & ~(_PRS_ASYNC_CH_CTRL_FNSEL_MASK + | _PRS_ASYNC_CH_CTRL_AUXSEL_MASK)) + | ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT) + | ((uint32_t)chB << _PRS_ASYNC_CH_CTRL_AUXSEL_SHIFT); +#endif +} +#endif + +/** @} (end addtogroup prs) */ +#endif /* defined(PRS_COUNT) && (PRS_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c index 30f8062..2709a8a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rmu.c @@ -1,382 +1,382 @@ -/***************************************************************************//** - * @file - * @brief Reset Management Unit (RMU) peripheral module peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_rmu.h" -#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) - -#include "sl_common.h" -#include "em_emu.h" -#include "em_bus.h" - -/***************************************************************************//** - * @addtogroup rmu RMU - Reset Management Unit - * @brief Reset Management Unit (RMU) Peripheral API - * @details - * This module contains functions to control the RMU peripheral of Silicon - * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is - * responsible for connecting the different reset sources to the reset lines of - * the MCU or SoC. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ***************************** DEFINES ********************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -#if defined(_RMU_RSTCAUSE_MASK) - -/** Reset cause XMASKS for series-0 and series-1 devices. - Reset cause zero and "don't care" bit definitions (XMASKs). - An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK - is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask - in @ref RMU_ResetCauseMasks_Typedef. */ - -/* EFM32G */ -#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ -#define NUM_RSTCAUSES 7 - -/* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ -#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ -#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ -#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ -#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ -#define NUM_RSTCAUSES 11 - -/* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ -#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ -#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ -#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ -#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ -#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ -#define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ -#define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ -#define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ -#define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ -#define NUM_RSTCAUSES 16 - -/* EFM32xG1, EFM32xG12, EFM32xG13 */ -#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ -#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ -#define NUM_RSTCAUSES 9 - -/* EFM32GG11 */ -#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) -#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ -#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ -#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ -#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ -#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ -#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ -#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ -#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ -#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ -#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ -#define NUM_RSTCAUSES 10 - -#else -#error "RMU_RSTCAUSE XMASKs are not defined for this family." -#endif - -/* Pin reset definitions. */ -#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) -#define LB_CLW0_PINRESETSOFT (1 << 2) - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) -/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ -#define ERRATA_FIX_EMU_E208_EN -#endif - -#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ - -/******************************************************************************* - ******************************* STRUCTS *********************************** - ******************************************************************************/ - -#if defined(_RMU_RSTCAUSE_MASK) -/** Reset cause mask type for series-0 and series-1 devices. */ -typedef struct { - /** Reset cause 1 bits. */ - uint32_t resetCauseMask; - /** Reset cause 0 and "don't care" bits. */ - uint32_t resetCauseZeroXMask; -} RMU_ResetCauseMasks_Typedef; -#endif - -/******************************************************************************* - ******************************* TYPEDEFS ********************************** - ******************************************************************************/ - -#if defined(_RMU_RSTCAUSE_MASK) -/** Reset cause mask table. */ -static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = -{ - { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, -#if defined(RMU_RSTCAUSE_BODUNREGRST) - { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODREGRST) - { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_AVDDBOD) - { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_DVDDBOD) - { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_DECBOD) - { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, -#endif - { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, - { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, - { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, - { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, -#if defined(RMU_RSTCAUSE_EM4RST) - { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_EM4WURST) - { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODAVDD0) - { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, -#endif -#if defined(RMU_RSTCAUSE_BODAVDD1) - { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, -#endif -#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) - { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, - { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, - { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, - { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, - { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, -#elif defined(RMU_RSTCAUSE_BUMODERST) - { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, -#endif -}; -#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ - -/******************************************************************************* - ******************************** TEST ******************************** - ******************************************************************************/ -#if defined(EMLIB_REGRESSION_TEST) -/* A test variable that replaces the RSTCAUSE cause register when testing - the RMU_ResetCauseGet function. */ -extern uint32_t rstCause; -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Disable/enable reset for various peripherals and signal sources. - * - * @param[in] reset Reset types to enable/disable.s - * - * @param[in] mode Reset mode. - ******************************************************************************/ -void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) -{ - /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ -#if defined(_RMU_CTRL_PINRMODE_MASK) - uint32_t val; -#endif - uint32_t shift; - - shift = SL_CTZ((uint32_t)reset); -#if defined(_EMU_RSTCTRL_MASK) - BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); -#elif defined(_RMU_CTRL_PINRMODE_MASK) - val = (uint32_t)mode << shift; - RMU->CTRL = (RMU->CTRL & ~reset) | val; -#else - BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); -#endif -} - -/***************************************************************************//** - * @brief - * Clear the reset cause register. - * - * @details - * This function clears all the reset cause bits of the RSTCAUSE register. - * The reset cause bits must be cleared by software before a new reset occurs. - * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). - ******************************************************************************/ -void RMU_ResetCauseClear(void) -{ -#if defined(_EMU_RSTCTRL_MASK) - EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; -#else - RMU->CMD = RMU_CMD_RCCLR; -#endif - -#if defined(EMU_AUXCTRL_HRCCLR) - { - uint32_t locked; - - /* Clear reset causes not cleared with the RMU CMD register. */ - /* (If EMU registers are locked, they must be unlocked first) */ - locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; - if (locked) { - EMU_Unlock(); - } - - BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); - BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); - - if (locked) { - EMU_Lock(); - } - } -#endif -} - -/***************************************************************************//** - * @brief - * Get the cause of the last reset. - * - * @details - * To be useful, the reset cause must be cleared by software before a new - * reset occurs. Otherwise, reset causes may accumulate. See @ref - * RMU_ResetCauseClear(). This function call will return the main cause for - * reset, which can be a bit mask (several causes) and clear away "noise". - * - * @return - * A reset cause mask. See the reference manual for a description - * of the reset cause mask. - ******************************************************************************/ -uint32_t RMU_ResetCauseGet(void) -{ -#if defined(_EMU_RSTCAUSE_MASK) -#if defined(EMLIB_REGRESSION_TEST) - return rstCause; -#else - return EMU->RSTCAUSE; -#endif -#endif - -#if defined(_RMU_RSTCAUSE_MASK) -#if !defined(EMLIB_REGRESSION_TEST) - uint32_t rstCause = RMU->RSTCAUSE; -#endif - uint32_t validRstCause = 0; - uint32_t zeroXMask; - uint32_t i; - - for (i = 0; i < NUM_RSTCAUSES; i++) { - zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; -#if defined(_SILICON_LABS_32B_SERIES_1) - /* Handle soft/hard pin reset. */ - if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { - /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ - switch (resetCauseMasks[i].resetCauseMask) { - case RMU_RSTCAUSE_LOCKUPRST: - /* Fallthrough */ - case RMU_RSTCAUSE_SYSREQRST: - /* Fallthrough */ - case RMU_RSTCAUSE_WDOGRST: - /* Fallthrough */ - case RMU_RSTCAUSE_EM4RST: - zeroXMask |= RMU_RSTCAUSE_EXTRST; - break; - default: - /* MISRA requires a default case. */ - break; - } - } -#endif - -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) - /* Ignore BOD flags impacted by EMU_E208. */ - if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { - zeroXMask &= ~(RMU_RSTCAUSE_DECBOD - | RMU_RSTCAUSE_DVDDBOD - | RMU_RSTCAUSE_AVDDBOD); - } -#endif - - /* Check reset cause requirements. Note that a bit is "don't care" if 0 in - both resetCauseMask and resetCauseZeroXMask. */ - if ((rstCause & resetCauseMasks[i].resetCauseMask) - && !(rstCause & zeroXMask)) { - /* Add this reset-cause to the mask of qualified reset-causes. */ - validRstCause |= resetCauseMasks[i].resetCauseMask; - } - } -#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) - /* Clear BOD flags impacted by EMU_E208. */ - if (validRstCause & RMU_RSTCAUSE_EM4RST) { - validRstCause &= ~(RMU_RSTCAUSE_DECBOD - | RMU_RSTCAUSE_DVDDBOD - | RMU_RSTCAUSE_AVDDBOD); - } -#endif - return validRstCause; -#endif -} - -/** @} (end addtogroup rmu) */ -#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Reset Management Unit (RMU) peripheral module peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_rmu.h" +#if (defined(RMU_COUNT) && (RMU_COUNT > 0)) || (_EMU_RSTCTRL_MASK) + +#include "sl_common.h" +#include "em_emu.h" +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup rmu RMU - Reset Management Unit + * @brief Reset Management Unit (RMU) Peripheral API + * @details + * This module contains functions to control the RMU peripheral of Silicon + * Labs 32-bit MCUs and SoCs. RMU ensures correct reset operation and is + * responsible for connecting the different reset sources to the reset lines of + * the MCU or SoC. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ***************************** DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +#if defined(_RMU_RSTCAUSE_MASK) + +/** Reset cause XMASKS for series-0 and series-1 devices. + Reset cause zero and "don't care" bit definitions (XMASKs). + An XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK + is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask + in @ref RMU_ResetCauseMasks_Typedef. */ + +/* EFM32G */ +#if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ +#define NUM_RSTCAUSES 7 + +/* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ +#elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ +#define NUM_RSTCAUSES 11 + +/* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ +#elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ +#define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ +#define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ +#define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ +#define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ +#define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ +#define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ +#define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ +#define NUM_RSTCAUSES 16 + +/* EFM32xG1, EFM32xG12, EFM32xG13 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 9 + +/* EFM32GG11 */ +#elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) +#define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ +#define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ +#define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ +#define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ +#define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ +#define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ +#define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ +#define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ +#define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ +#define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ +#define NUM_RSTCAUSES 10 + +#else +#error "RMU_RSTCAUSE XMASKs are not defined for this family." +#endif + +/* Pin reset definitions. */ +#define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) +#define LB_CLW0_PINRESETSOFT (1 << 2) + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) +/* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H. */ +#define ERRATA_FIX_EMU_E208_EN +#endif + +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************* STRUCTS *********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask type for series-0 and series-1 devices. */ +typedef struct { + /** Reset cause 1 bits. */ + uint32_t resetCauseMask; + /** Reset cause 0 and "don't care" bits. */ + uint32_t resetCauseZeroXMask; +} RMU_ResetCauseMasks_Typedef; +#endif + +/******************************************************************************* + ******************************* TYPEDEFS ********************************** + ******************************************************************************/ + +#if defined(_RMU_RSTCAUSE_MASK) +/** Reset cause mask table. */ +static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = +{ + { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, +#if defined(RMU_RSTCAUSE_BODUNREGRST) + { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODREGRST) + { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_AVDDBOD) + { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DVDDBOD) + { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_DECBOD) + { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, +#endif + { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, + { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, + { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, + { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, +#if defined(RMU_RSTCAUSE_EM4RST) + { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_EM4WURST) + { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD0) + { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, +#endif +#if defined(RMU_RSTCAUSE_BODAVDD1) + { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, +#endif +#if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) + { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, + { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, + { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, + { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#elif defined(RMU_RSTCAUSE_BUMODERST) + { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, +#endif +}; +#endif /* #if defined(_RMU_RSTCAUSE_MASK) */ + +/******************************************************************************* + ******************************** TEST ******************************** + ******************************************************************************/ +#if defined(EMLIB_REGRESSION_TEST) +/* A test variable that replaces the RSTCAUSE cause register when testing + the RMU_ResetCauseGet function. */ +extern uint32_t rstCause; +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Disable/enable reset for various peripherals and signal sources. + * + * @param[in] reset Reset types to enable/disable.s + * + * @param[in] mode Reset mode. + ******************************************************************************/ +void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) +{ + /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear. */ +#if defined(_RMU_CTRL_PINRMODE_MASK) + uint32_t val; +#endif + uint32_t shift; + + shift = SL_CTZ((uint32_t)reset); +#if defined(_EMU_RSTCTRL_MASK) + BUS_RegBitWrite(&EMU->RSTCTRL, (uint32_t)shift, mode ? 1 : 0); +#elif defined(_RMU_CTRL_PINRMODE_MASK) + val = (uint32_t)mode << shift; + RMU->CTRL = (RMU->CTRL & ~reset) | val; +#else + BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); +#endif +} + +/***************************************************************************//** + * @brief + * Clear the reset cause register. + * + * @details + * This function clears all the reset cause bits of the RSTCAUSE register. + * The reset cause bits must be cleared by software before a new reset occurs. + * Otherwise, reset causes may accumulate. See @ref RMU_ResetCauseGet(). + ******************************************************************************/ +void RMU_ResetCauseClear(void) +{ +#if defined(_EMU_RSTCTRL_MASK) + EMU->CMD_SET = EMU_CMD_RSTCAUSECLR; +#else + RMU->CMD = RMU_CMD_RCCLR; +#endif + +#if defined(EMU_AUXCTRL_HRCCLR) + { + uint32_t locked; + + /* Clear reset causes not cleared with the RMU CMD register. */ + /* (If EMU registers are locked, they must be unlocked first) */ + locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; + if (locked) { + EMU_Unlock(); + } + + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); + BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); + + if (locked) { + EMU_Lock(); + } + } +#endif +} + +/***************************************************************************//** + * @brief + * Get the cause of the last reset. + * + * @details + * To be useful, the reset cause must be cleared by software before a new + * reset occurs. Otherwise, reset causes may accumulate. See @ref + * RMU_ResetCauseClear(). This function call will return the main cause for + * reset, which can be a bit mask (several causes) and clear away "noise". + * + * @return + * A reset cause mask. See the reference manual for a description + * of the reset cause mask. + ******************************************************************************/ +uint32_t RMU_ResetCauseGet(void) +{ +#if defined(_EMU_RSTCAUSE_MASK) +#if defined(EMLIB_REGRESSION_TEST) + return rstCause; +#else + return EMU->RSTCAUSE; +#endif +#endif + +#if defined(_RMU_RSTCAUSE_MASK) +#if !defined(EMLIB_REGRESSION_TEST) + uint32_t rstCause = RMU->RSTCAUSE; +#endif + uint32_t validRstCause = 0; + uint32_t zeroXMask; + uint32_t i; + + for (i = 0; i < NUM_RSTCAUSES; i++) { + zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; +#if defined(_SILICON_LABS_32B_SERIES_1) + /* Handle soft/hard pin reset. */ + if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { + /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset. */ + switch (resetCauseMasks[i].resetCauseMask) { + case RMU_RSTCAUSE_LOCKUPRST: + /* Fallthrough */ + case RMU_RSTCAUSE_SYSREQRST: + /* Fallthrough */ + case RMU_RSTCAUSE_WDOGRST: + /* Fallthrough */ + case RMU_RSTCAUSE_EM4RST: + zeroXMask |= RMU_RSTCAUSE_EXTRST; + break; + default: + /* MISRA requires a default case. */ + break; + } + } +#endif + +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Ignore BOD flags impacted by EMU_E208. */ + if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { + zeroXMask &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif + + /* Check reset cause requirements. Note that a bit is "don't care" if 0 in + both resetCauseMask and resetCauseZeroXMask. */ + if ((rstCause & resetCauseMasks[i].resetCauseMask) + && !(rstCause & zeroXMask)) { + /* Add this reset-cause to the mask of qualified reset-causes. */ + validRstCause |= resetCauseMasks[i].resetCauseMask; + } + } +#if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) + /* Clear BOD flags impacted by EMU_E208. */ + if (validRstCause & RMU_RSTCAUSE_EM4RST) { + validRstCause &= ~(RMU_RSTCAUSE_DECBOD + | RMU_RSTCAUSE_DVDDBOD + | RMU_RSTCAUSE_AVDDBOD); + } +#endif + return validRstCause; +#endif +} + +/** @} (end addtogroup rmu) */ +#endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rtcc.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rtcc.c index b276711..46088d0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rtcc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_rtcc.c @@ -1,250 +1,250 @@ -/***************************************************************************//** - * @file - * @brief Real Time Counter with Calendar (RTCC) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_rtcc.h" -#if defined(RTCC_COUNT) && (RTCC_COUNT == 1) -#include "em_bus.h" - -/***************************************************************************//** - * @addtogroup rtcc RTCC - Real Timer Counter/Calendar - * @brief Real Time Counter and Calendar (RTCC) Peripheral API - * @details - * This module contains functions to control the RTCC peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The RTCC ensures timekeeping in low energy modes. - * The RTCC also includes a BCD calendar mode for easy time and date keeping. - * @{ - ******************************************************************************/ - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Configure the selected capture/compare channel of the RTCC. - * - * @details - * Use this function to configure an RTCC channel. - * Select capture/compare mode, match output action, overflow output action, - * and PRS input configuration. - * See the configuration structure @ref RTCC_CCChConf_TypeDef for more - * details. - * - * @param[in] ch - * A channel selector. - * - * @param[in] confPtr - * A pointer to the configuration structure. - ******************************************************************************/ -void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr) -{ - EFM_ASSERT(RTCC_CH_VALID(ch)); - -#if defined(_SILICON_LABS_32B_SERIES_1) - EFM_ASSERT((uint32_t)confPtr->compMask - < (_RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT) - + 1U); - - /** Configure the selected capture/compare channel. */ - RTCC->CC[ch].CTRL = ((uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) - | ((uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) - | ((uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT) - | ((uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) - | ((uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT) - | ((uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT) - | ((uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT); -#else - - /** Configure the selected capture/compare channel. */ - RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) - | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) - | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) - | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT); - if (confPtr->chMode == rtccCapComChModeCapture) { - volatile uint32_t *reg = &PRS->CONSUMER_RTCC_CC0; - reg[ch] = confPtr->prsSel; - } -#endif -} - -/***************************************************************************//** - * @brief - * Enable/disable RTCC counting. - * - * @param[in] enable - * True to enable RTCC counting, false to disable counting. - ******************************************************************************/ -void RTCC_Enable(bool enable) -{ -#if defined (_RTCC_CTRL_ENABLE_SHIFT) - /* Bitbanding the enable bit in the CTRL register (atomic). */ - BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, (uint32_t)enable); -#elif defined (RTCC_CMD_START) - - /* Quick exit if we want to disable RTCC and it's already disabled. */ - if ((RTCC->EN == 0U) && !enable) { - return; - } - - if (RTCC->EN != 0U) { - /* Modifying the enable bit while synchronization is active will BusFault */ - RTCC_SyncWait(); - } - - if (enable) { - RTCC->EN_SET = RTCC_EN_EN; - RTCC_Start(); - } else { - RTCC_Stop(); - RTCC_SyncWait(); - RTCC->EN_CLR = RTCC_EN_EN; - } -#endif -} - -/***************************************************************************//** - * @brief - * Initialize RTCC. - * - * @details - * Note that the compare values must be set separately with RTCC_CompareSet(), - * which should probably be done prior to the use of this function if - * configuring the RTCC to start when initialization is completed. - * - * @param[in] init - * A pointer to the RTCC initialization structure. - ******************************************************************************/ -void RTCC_Init(const RTCC_Init_TypeDef *init) -{ -#if defined (_RTCC_CTRL_MASK) - RTCC->CTRL = ((init->enable ? 1UL : 0UL) << _RTCC_CTRL_ENABLE_SHIFT) - | ((init->debugRun ? 1UL : 0UL) << _RTCC_CTRL_DEBUGRUN_SHIFT) - | ((init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CTRL_PRECCV0TOP_SHIFT) - | ((init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CTRL_CCV1TOP_SHIFT) - | ((uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT) - | ((uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT) -#if defined(_RTCC_CTRL_BUMODETSEN_MASK) - | ((uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT) -#endif - | ((init->enaOSCFailDetect ? 1UL : 0UL) << _RTCC_CTRL_OSCFDETEN_SHIFT) - | ((uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT) - | ((init->disLeapYearCorr ? 1UL : 0UL) << _RTCC_CTRL_LYEARCORRDIS_SHIFT); - -#elif defined (_RTCC_CFG_MASK) - if (RTCC->EN != 0U) { - RTCC_SyncWait(); - } - RTCC->EN_CLR = RTCC_EN_EN; - RTCC->CFG = ((init->debugRun ? 1UL : 0UL) << _RTCC_CFG_DEBUGRUN_SHIFT) - | ( (init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CFG_PRECNTCCV0TOP_SHIFT) - | ( (init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CFG_CNTCCV1TOP_SHIFT) - | ( (uint32_t)init->presc << _RTCC_CFG_CNTPRESC_SHIFT) - | ( (uint32_t)init->prescMode << _RTCC_CFG_CNTTICK_SHIFT); - RTCC->EN_SET = RTCC_EN_EN; - RTCC->CMD = init->enable ? RTCC_CMD_START : RTCC_CMD_STOP; -#endif -} - -/***************************************************************************//** - * @brief - * Restore RTCC to its reset state. - ******************************************************************************/ -void RTCC_Reset(void) -{ - unsigned int i; - -#if defined(_RTCC_CTRL_MASK) - /* Restore all RTCC registers to their default values. */ - RTCC_Unlock(); - RTCC->CTRL = _RTCC_CTRL_RESETVALUE; - RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; - RTCC->CNT = _RTCC_CNT_RESETVALUE; - RTCC->TIME = _RTCC_TIME_RESETVALUE; - RTCC->DATE = _RTCC_DATE_RESETVALUE; - RTCC->IEN = _RTCC_IEN_RESETVALUE; - RTCC->IFC = _RTCC_IFC_MASK; - RTCC_StatusClear(); - RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE; - - for (i = 0; i < RTCC_CC_NUM; i++) { - RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; - RTCC->CC[i].CCV = _RTCC_CC_CCV_RESETVALUE; - RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE; - RTCC->CC[i].DATE = _RTCC_CC_DATE_RESETVALUE; - } - -#elif defined(_RTCC_CFG_MASK) - - /* Restore all RTCC registers to their default values. */ - RTCC_Unlock(); - RTCC->EN_SET = RTCC_EN_EN; - RTCC_Stop(); - RTCC_SyncWait(); - RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; - RTCC->CNT = _RTCC_CNT_RESETVALUE; - RTCC->IEN = _RTCC_IEN_RESETVALUE; - RTCC_IntClear(_RTCC_IF_MASK); - RTCC_StatusClear(); - - for (i = 0; i < RTCC_CC_NUM; i++) { - RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; - RTCC->CC[i].OCVALUE = _RTCC_CC_OCVALUE_RESETVALUE; - } - RTCC_SyncWait(); - RTCC->EN_CLR = RTCC_EN_EN; - RTCC->CFG = _RTCC_CFG_RESETVALUE; -#endif -} - -/***************************************************************************//** - * @brief - * Clear the STATUS register. - ******************************************************************************/ -void RTCC_StatusClear(void) -{ -#if defined (RTCC_CMD_CLRSTATUS) - while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { - // Wait for synchronization. - } - RTCC->CMD = RTCC_CMD_CLRSTATUS; -#endif -} - -/** @} (end addtogroup rtcc) */ - -#endif /* defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 ) */ +/***************************************************************************//** + * @file + * @brief Real Time Counter with Calendar (RTCC) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_rtcc.h" +#if defined(RTCC_COUNT) && (RTCC_COUNT == 1) +#include "em_bus.h" + +/***************************************************************************//** + * @addtogroup rtcc RTCC - Real Timer Counter/Calendar + * @brief Real Time Counter and Calendar (RTCC) Peripheral API + * @details + * This module contains functions to control the RTCC peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The RTCC ensures timekeeping in low energy modes. + * The RTCC also includes a BCD calendar mode for easy time and date keeping. + * @{ + ******************************************************************************/ + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Configure the selected capture/compare channel of the RTCC. + * + * @details + * Use this function to configure an RTCC channel. + * Select capture/compare mode, match output action, overflow output action, + * and PRS input configuration. + * See the configuration structure @ref RTCC_CCChConf_TypeDef for more + * details. + * + * @param[in] ch + * A channel selector. + * + * @param[in] confPtr + * A pointer to the configuration structure. + ******************************************************************************/ +void RTCC_ChannelInit(int ch, RTCC_CCChConf_TypeDef const *confPtr) +{ + EFM_ASSERT(RTCC_CH_VALID(ch)); + +#if defined(_SILICON_LABS_32B_SERIES_1) + EFM_ASSERT((uint32_t)confPtr->compMask + < (_RTCC_CC_CTRL_COMPMASK_MASK >> _RTCC_CC_CTRL_COMPMASK_SHIFT) + + 1U); + + /** Configure the selected capture/compare channel. */ + RTCC->CC[ch].CTRL = ((uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) + | ((uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) + | ((uint32_t)confPtr->prsSel << _RTCC_CC_CTRL_PRSSEL_SHIFT) + | ((uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT) + | ((uint32_t)confPtr->compMask << _RTCC_CC_CTRL_COMPMASK_SHIFT) + | ((uint32_t)confPtr->dayCompMode << _RTCC_CC_CTRL_DAYCC_SHIFT); +#else + + /** Configure the selected capture/compare channel. */ + RTCC->CC[ch].CTRL = ( (uint32_t)confPtr->chMode << _RTCC_CC_CTRL_MODE_SHIFT) + | ( (uint32_t)confPtr->compMatchOutAction << _RTCC_CC_CTRL_CMOA_SHIFT) + | ( (uint32_t)confPtr->inputEdgeSel << _RTCC_CC_CTRL_ICEDGE_SHIFT) + | ( (uint32_t)confPtr->compBase << _RTCC_CC_CTRL_COMPBASE_SHIFT); + if (confPtr->chMode == rtccCapComChModeCapture) { + volatile uint32_t *reg = &PRS->CONSUMER_RTCC_CC0; + reg[ch] = confPtr->prsSel; + } +#endif +} + +/***************************************************************************//** + * @brief + * Enable/disable RTCC counting. + * + * @param[in] enable + * True to enable RTCC counting, false to disable counting. + ******************************************************************************/ +void RTCC_Enable(bool enable) +{ +#if defined (_RTCC_CTRL_ENABLE_SHIFT) + /* Bitbanding the enable bit in the CTRL register (atomic). */ + BUS_RegBitWrite((&RTCC->CTRL), _RTCC_CTRL_ENABLE_SHIFT, (uint32_t)enable); +#elif defined (RTCC_CMD_START) + + /* Quick exit if we want to disable RTCC and it's already disabled. */ + if ((RTCC->EN == 0U) && !enable) { + return; + } + + if (RTCC->EN != 0U) { + /* Modifying the enable bit while synchronization is active will BusFault */ + RTCC_SyncWait(); + } + + if (enable) { + RTCC->EN_SET = RTCC_EN_EN; + RTCC_Start(); + } else { + RTCC_Stop(); + RTCC_SyncWait(); + RTCC->EN_CLR = RTCC_EN_EN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Initialize RTCC. + * + * @details + * Note that the compare values must be set separately with RTCC_CompareSet(), + * which should probably be done prior to the use of this function if + * configuring the RTCC to start when initialization is completed. + * + * @param[in] init + * A pointer to the RTCC initialization structure. + ******************************************************************************/ +void RTCC_Init(const RTCC_Init_TypeDef *init) +{ +#if defined (_RTCC_CTRL_MASK) + RTCC->CTRL = ((init->enable ? 1UL : 0UL) << _RTCC_CTRL_ENABLE_SHIFT) + | ((init->debugRun ? 1UL : 0UL) << _RTCC_CTRL_DEBUGRUN_SHIFT) + | ((init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CTRL_PRECCV0TOP_SHIFT) + | ((init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CTRL_CCV1TOP_SHIFT) + | ((uint32_t)init->presc << _RTCC_CTRL_CNTPRESC_SHIFT) + | ((uint32_t)init->prescMode << _RTCC_CTRL_CNTTICK_SHIFT) +#if defined(_RTCC_CTRL_BUMODETSEN_MASK) + | ((uint32_t)init->enaBackupModeSet << _RTCC_CTRL_BUMODETSEN_SHIFT) +#endif + | ((init->enaOSCFailDetect ? 1UL : 0UL) << _RTCC_CTRL_OSCFDETEN_SHIFT) + | ((uint32_t)init->cntMode << _RTCC_CTRL_CNTMODE_SHIFT) + | ((init->disLeapYearCorr ? 1UL : 0UL) << _RTCC_CTRL_LYEARCORRDIS_SHIFT); + +#elif defined (_RTCC_CFG_MASK) + if (RTCC->EN != 0U) { + RTCC_SyncWait(); + } + RTCC->EN_CLR = RTCC_EN_EN; + RTCC->CFG = ((init->debugRun ? 1UL : 0UL) << _RTCC_CFG_DEBUGRUN_SHIFT) + | ( (init->precntWrapOnCCV0 ? 1UL : 0UL) << _RTCC_CFG_PRECNTCCV0TOP_SHIFT) + | ( (init->cntWrapOnCCV1 ? 1UL : 0UL) << _RTCC_CFG_CNTCCV1TOP_SHIFT) + | ( (uint32_t)init->presc << _RTCC_CFG_CNTPRESC_SHIFT) + | ( (uint32_t)init->prescMode << _RTCC_CFG_CNTTICK_SHIFT); + RTCC->EN_SET = RTCC_EN_EN; + RTCC->CMD = init->enable ? RTCC_CMD_START : RTCC_CMD_STOP; +#endif +} + +/***************************************************************************//** + * @brief + * Restore RTCC to its reset state. + ******************************************************************************/ +void RTCC_Reset(void) +{ + unsigned int i; + +#if defined(_RTCC_CTRL_MASK) + /* Restore all RTCC registers to their default values. */ + RTCC_Unlock(); + RTCC->CTRL = _RTCC_CTRL_RESETVALUE; + RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; + RTCC->CNT = _RTCC_CNT_RESETVALUE; + RTCC->TIME = _RTCC_TIME_RESETVALUE; + RTCC->DATE = _RTCC_DATE_RESETVALUE; + RTCC->IEN = _RTCC_IEN_RESETVALUE; + RTCC->IFC = _RTCC_IFC_MASK; + RTCC_StatusClear(); + RTCC->EM4WUEN = _RTCC_EM4WUEN_RESETVALUE; + + for (i = 0; i < RTCC_CC_NUM; i++) { + RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; + RTCC->CC[i].CCV = _RTCC_CC_CCV_RESETVALUE; + RTCC->CC[i].TIME = _RTCC_CC_TIME_RESETVALUE; + RTCC->CC[i].DATE = _RTCC_CC_DATE_RESETVALUE; + } + +#elif defined(_RTCC_CFG_MASK) + + /* Restore all RTCC registers to their default values. */ + RTCC_Unlock(); + RTCC->EN_SET = RTCC_EN_EN; + RTCC_Stop(); + RTCC_SyncWait(); + RTCC->PRECNT = _RTCC_PRECNT_RESETVALUE; + RTCC->CNT = _RTCC_CNT_RESETVALUE; + RTCC->IEN = _RTCC_IEN_RESETVALUE; + RTCC_IntClear(_RTCC_IF_MASK); + RTCC_StatusClear(); + + for (i = 0; i < RTCC_CC_NUM; i++) { + RTCC->CC[i].CTRL = _RTCC_CC_CTRL_RESETVALUE; + RTCC->CC[i].OCVALUE = _RTCC_CC_OCVALUE_RESETVALUE; + } + RTCC_SyncWait(); + RTCC->EN_CLR = RTCC_EN_EN; + RTCC->CFG = _RTCC_CFG_RESETVALUE; +#endif +} + +/***************************************************************************//** + * @brief + * Clear the STATUS register. + ******************************************************************************/ +void RTCC_StatusClear(void) +{ +#if defined (RTCC_CMD_CLRSTATUS) + while ((RTCC->SYNCBUSY & RTCC_SYNCBUSY_CMD) != 0U) { + // Wait for synchronization. + } + RTCC->CMD = RTCC_CMD_CLRSTATUS; +#endif +} + +/** @} (end addtogroup rtcc) */ + +#endif /* defined( RTCC_COUNT ) && ( RTCC_COUNT == 1 ) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_se.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_se.c index 649cec5..df9faaf 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_se.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_se.c @@ -1,1372 +1,1372 @@ -/***************************************************************************//** - * @file - * @brief Secure Element API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_se.h" - -#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - -#include "em_core.h" -#include "sl_assert.h" -#include "em_system.h" - -#endif - -/***************************************************************************//** - * @addtogroup se - * @{ - ******************************************************************************/ - -/******************************************************************************* - ****************************** DEFINES *********************************** - ******************************************************************************/ -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/* OTP initialization structure defines. */ -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) - -#if defined(CRYPTOACC_PRESENT) - -/// Signal that OTP version is incorporated into the status field of the output -#define SE_VSE_REPLY_STATUS_OTP_VERSION_SET (1 << 21) -/// Mask defining the region of the status field that contains the OTP version -/// number. -#define SE_VSE_REPLY_STATUS_OTP_VERSION_MASK (0xFF000000UL) -/// Shift to insert a number into the otp version part of the status field -#define SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT (24) - -/* Size of VSE Mailbox instance. - There are two instances, input and output. */ -#define ROOT_MAILBOX_SIZE (512UL) - -/* Base addresses of the VSE Input and Output Mailbox data structures. - (Must be stored in a RAM area which is not used by the VSE) - We use the upper 1KB of FRC RAM for the VSE mailboxes. */ -#define ROOT_MAILBOX_OUTPUT_S_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE) -#define ROOT_MAILBOX_INPUT_S_BASE (ROOT_MAILBOX_OUTPUT_S_BASE - ROOT_MAILBOX_SIZE) - -// SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S is defined in sl_trustzone_secure_config.h -#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) \ - || (defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S) && SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) - -#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_S_MEM_BASE - -#define ROOT_MAILBOX_OUTPUT_BASE SYSCFG->ROOTDATA1; -#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED ROOT_MAILBOX_OUTPUT_S_BASE -#else -#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_NS_MEM_BASE - -// VSE will always output the secure address, if NS is desired, caculate the NS address. -#define ROOT_MAILBOX_OUTPUT_BASE (SYSCFG->ROOTDATA1 - RDMEM_FRCRAM_S_MEM_BASE + RDMEM_FRCRAM_NS_MEM_BASE); -#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED (RDMEM_FRCRAM_NS_MEM_END + 1 - ROOT_MAILBOX_SIZE) -#endif -#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - ROOT_MAILBOX_SIZE) - -/* Position of parameter number field in VSE Input Mailbox LENGTH field.*/ -#define ROOT_MB_LENGTH_PARAM_NUM_SHIFT (24) - -/* Done flag indicating that the VSE Mailbox handler has completed - processing the mailbox command. */ -#define ROOT_MB_DONE (1 << 23) - -/* VSE Configuration Status bits mask */ -#define ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK (0xFFFF) - -#endif // #if defined(CRYPTOACC_PRESENT) -/** @endcond */ - -/******************************************************************************* - ****************************** TYPEDEFS *********************************** - ******************************************************************************/ -#if defined(CRYPTOACC_PRESENT) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -// VSE Input Mailbox structure -typedef struct { - volatile uint32_t magic; - volatile uint32_t command; - volatile uint32_t length; - volatile uint32_t data[0]; -} root_InputMailbox_t; - -// VSE Output Mailbox structure -typedef struct { - volatile uint32_t magic; - volatile uint32_t version; - volatile uint32_t status; - volatile uint32_t command; - volatile uint32_t length; - volatile uint32_t data[0]; -} root_OutputMailbox_t; -/** @endcond */ - -#endif // #if defined(CRYPTOACC_PRESENT) - -/******************************************************************************* - ************************** STATIC FUNCTIONS ******************************* - ******************************************************************************/ - -#if defined(SEMAILBOX_PRESENT) -/***************************************************************************//** - * @brief - * Write to FIFO - * - * @param value - * Value to write to FIFO - ******************************************************************************/ -#if defined(_SEMAILBOX_FIFO_RESETVALUE) -__STATIC_INLINE void writeToFifo(uint32_t value) -{ - SEMAILBOX_HOST->FIFO = value; -} -#else -__STATIC_INLINE void writeToFifo(uint32_t value) -{ - SEMAILBOX_HOST->FIFO[0].DATA = value; -} -#endif - -#endif // SEMAILBOX_PRESENT - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Add input data to a command - * - * @details - * This function adds a buffer of input data to the given SE command structure - * The buffer gets appended by reference at the end of the list of already - * added buffers. - * - * @note - * Note that this function does not copy either the data buffer or the buffer - * structure, so make sure to keep the data object in scope until the command - * has been executed by the secure element. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @param[in] data - * Pointer to a data transfer structure. - ******************************************************************************/ -void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data) -{ - if (command->data_in == NULL) { - command->data_in = data; - } else { - SE_DataTransfer_t *next = command->data_in; - while (next->next != (void*)SE_DATATRANSFER_STOP) { - next = (SE_DataTransfer_t*)next->next; - } - next->next = data; - } -} - -/***************************************************************************//** - * @brief - * Add output data to a command - * - * @details - * This function adds a buffer of output data to the given command structure - * The buffer gets appended by reference at the end of the list of already - * added buffers. - * - * @note - * Note that this function does not copy either the data buffer or the buffer - * structure, so make sure to keep the data object in scope until the command - * has been executed by the secure element. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @param[in] data - * Pointer to a data transfer structure. - ******************************************************************************/ -void SE_addDataOutput(SE_Command_t *command, - SE_DataTransfer_t *data) -{ - if (command->data_out == NULL) { - command->data_out = data; - } else { - SE_DataTransfer_t *next = command->data_out; - while (next->next != (void*)SE_DATATRANSFER_STOP) { - next = (SE_DataTransfer_t*)next->next; - } - next->next = data; - } -} - -/***************************************************************************//** - * @brief - * Add a parameter to a command - * - * @details - * This function adds a parameter word to the passed command. - * - * @note - * Make sure to not exceed @ref SE_MAX_PARAMETERS. - * - * @param[in] command - * Pointer to a filled-out SE command structure. - * @param[in] parameter - * Parameter to add. - ******************************************************************************/ -void SE_addParameter(SE_Command_t *command, uint32_t parameter) -{ - if (command->num_parameters >= SE_MAX_PARAMETERS) { - EFM_ASSERT(command->num_parameters < SE_MAX_PARAMETERS); - return; - } - - command->parameters[command->num_parameters] = parameter; - command->num_parameters += 1; -} - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * Execute the passed command - * - * @details - * This function starts the execution of the passed command by the secure - * element. When started, wait for the RXINT interrupt flag, or call - * @ref SE_waitCommandCompletion to busy-wait. After completion, you have to - * call @ref SE_readCommandResponse to get the command's execution status. - * - * @param[in] command - * Pointer to a filled-out SE command structure. - ******************************************************************************/ -void SE_executeCommand(SE_Command_t *command) -{ - // Don't overflow our struct - if (command->num_parameters > SE_MAX_PARAMETERS) { - EFM_ASSERT(command->num_parameters <= SE_MAX_PARAMETERS); - return; - } - -#if defined(SEMAILBOX_PRESENT) - - // Wait for room available in the mailbox - while (!(SEMAILBOX_HOST->TX_STATUS & SEMAILBOX_TX_STATUS_TXINT)) ; - - // Write header to start transaction - SEMAILBOX_HOST->TX_HEADER = sizeof(uint32_t) * (4 + command->num_parameters); - - // Write command into FIFO - writeToFifo(command->command); - - // Write DMA descriptors into FIFO - writeToFifo((uint32_t)command->data_in); - writeToFifo((uint32_t)command->data_out); - - // Write applicable parameters into FIFO - for (size_t i = 0; i < command->num_parameters; i++) { - writeToFifo(command->parameters[i]); - } - -#elif defined(CRYPTOACC_PRESENT) - // Prepare the VSE Mailbox within a critical section to prevent - // the process from getting interrupted. At this point, the only option - // we have is to go through a reset, so it is safe to enter the critical section. - (void)CORE_EnterCritical(); - - // Setup pointer to the VSE Mailbox Input data structure - // (must be stored in a RAM area which is not used by the VSE) - root_InputMailbox_t *rootInMb = (root_InputMailbox_t*)ROOT_MAILBOX_INPUT_BASE; - uint32_t *mbData; - unsigned int mbDataLen, inDataLen, i; - SE_DataTransfer_t *inDataDesc; - uint32_t *inData; - uint32_t checksum; - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - - // Store the secure memory base addresses for VSE to be able to read from the address - // Set base of Mailbox Input data structure in SYSCFG register in order - // for VSE to find it. - SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_S_BASE; - // Set base of Mailbox Output data structure in SYSCFG register in order - // for VSE to know where to write output data. - // Write command into FIFO - SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_S_BASE; - - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - rootInMb->magic = SE_RESPONSE_MAILBOX_VALID; - rootInMb->command = command->command; - - // Write applicable parameters into Mailbox DATA array - mbData = (uint32_t*) rootInMb->data; - for (mbDataLen = 0; mbDataLen < command->num_parameters; mbDataLen++) { - mbData[mbDataLen] = command->parameters[mbDataLen]; - } - - // Write input data into Mailbox DATA array - inDataLen = 0; - for (inDataDesc = command->data_in; inDataDesc; inDataDesc = (SE_DataTransfer_t*) inDataDesc->next) { - inData = (uint32_t*) inDataDesc->data; - for (i = 0; i < (inDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); i++) { - // Make sure we do not overflow the input mailbox. - EFM_ASSERT(mbDataLen < ROOT_MAILBOX_SIZE); - mbData[mbDataLen++] = inData[i]; - inDataLen++; - } - if (inDataDesc->next == (void*)SE_DATATRANSFER_STOP) { - break; - } - } - - // Write number of parameters and data words to 'length' field of mailbox. - rootInMb->length = - inDataLen | (command->num_parameters << ROOT_MB_LENGTH_PARAM_NUM_SHIFT); - - // Calculate checksum using bitwise XOR over the all words in the mailbox - // data structure, minus the CHECKSUM word (32bit = 4bytes ) at the end. - checksum = rootInMb->magic; - checksum ^= rootInMb->command; - checksum ^= rootInMb->length; - for (i = 0; i < mbDataLen; i++) { - checksum ^= mbData[i]; - } - - // Finally, write the calculated checksum to mailbox checksum field - mbData[mbDataLen] = checksum; - - __NVIC_SystemReset(); - -#endif // #if defined(SEMAILBOX_PRESENT) -} - -#endif // #if !defined(SLI_EM_SE_HOST) - -#if defined(CRYPTOACC_PRESENT) -/***************************************************************************//** - * @brief - * Check whether the VSE Output Mailbox is valid. - * - * @return True if the VSE Output Mailbox is valid (magic and checksum OK) - ******************************************************************************/ -bool rootIsOutputMailboxValid(void) -{ - // Setup pointer to the VSE Output Mailbox data structure - // (must be stored in a RAM area which is not used by the VSE) - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if ((uint32_t)rootOutMb > ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - || (uint32_t)rootOutMb < RDMEM_FRCRAM_MEM_BASE) { - return false; - } - - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - uint32_t *mbPtr = (uint32_t*) rootOutMb; - uint32_t checksum; - unsigned int mbLen, cnt; - - // Verify magic word of mailbox - if (rootOutMb->magic != SE_RESPONSE_MAILBOX_VALID) { - return false; - } - - // Get length of mailbox - mbLen = sizeof(root_OutputMailbox_t) / sizeof(uint32_t) + rootOutMb->length; - if (mbLen >= ROOT_MAILBOX_SIZE) { - return false; - } - // Calculate checksum using bitwise XOR over all words in the mailbox - // data structure, minus the CHECKSUM word at the end. - for (checksum = 0, cnt = 0; cnt < mbLen; cnt++) { - checksum ^= mbPtr[cnt]; - } - - // Verify that the calculated checksum is equal to the mailbox checksum. - return (mbPtr[mbLen] == checksum); -} - -/***************************************************************************//** - * @brief - * Get current SE version - * - * @details - * This function returns the current VSE version - * - * @param[in] version - * Pointer to location where to copy the version of VSE to. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_getVersion(uint32_t *version) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (version == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Return the 'version' from the Output Mailbox - *version = rootOutMb->version; - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Get VSE configuration and status bits - * - * @details - * This function returns the current VSE configuration and status bits. - * The following list explains what the different bits in cfgStatus indicate. - * A bit value of 1 means enabled, while 0 means disabled: - * * [0]: Secure boot - * * [1]: Verify secure boot certificate - * * [2]: Anti-rollback - * * [3]: Narrow page lock - * * [4]: Full page lock - * The following status bits can be read with VSE versions - * higher than 1.2.2. - * * [10]: Debug port lock - * * [11]: Device erase enabled - * * [12]: Secure debug enabled - * * [15]: Debug port register state, 1 if the debug port is locked. - * - * @param[out] cfgStatus - * Pointer to location to copy Configuration Status bits into. - * - * @note - * This function will check that the mailbox content is valid before - * reading the status bits. If the command response has already been read - * with a call to @ref SE_ackCommand(), the validity check will fail, and - * the config status bits cannot be read before a reset has occurred. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (cfgStatus == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Return the configuration status bits - *cfgStatus = rootOutMb->status & ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK; - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Get the version number of the OTP from the status field of the output - * mailbox - * @details - * This function checks if the OTP version number flag is set in the output - * mailbox. If it is, the version number is writen to @ref otpVersion pointer - * location. If not, it returns error response. - * - * @param[out] otpVersion - * Pointer to location to copy OTP version number into. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - ******************************************************************************/ -SE_Response_t SE_getOTPVersion(uint32_t *otpVersion) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - if (otpVersion == NULL) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - // First verify that the response is ok. - if (!rootIsOutputMailboxValid()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - bool isOTPVersionSet = rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_SET; - if (isOTPVersionSet) { - // Return the OTP version from the status field. - *otpVersion = (rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_MASK) >> SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT; - } else { - return SE_RESPONSE_INVALID_COMMAND; - } - - return SE_RESPONSE_OK; -} - -/***************************************************************************//** - * @brief - * Check whether the running command has completed. - * - * @details - * This function polls the SE-to-host mailbox interrupt flag. - * - * @return True if a command has completed and the result is available - ******************************************************************************/ -bool SE_isCommandCompleted(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the response is ok - if (!rootIsOutputMailboxValid()) { - return false; - } - - // Check status MB_DONE flag of the mailbox - return ((rootOutMb->status & ROOT_MB_DONE) == ROOT_MB_DONE); -} - -/***************************************************************************//** - * @brief - * Read the previously executed command. - * - * @details - * This function reads the previously executed command. - * - * @return - * One of the SE command words. - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid. - ******************************************************************************/ -uint32_t SE_readExecutedCommand(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - return rootOutMb->command; -} - -/***************************************************************************//** - * @brief - * Read the status of the previously executed command. - * - * @details - * This function reads the status of the previously executed command. - * - * @return - * One of the SE_RESPONSE return codes: - * SE_RESPONSE_OK when the command was executed successfully or a signature - * was successfully verified, - * SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, e.g. - * because of conflicting Secure/Non-Secure memory accesses, - * SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid - ******************************************************************************/ -SE_Response_t SE_readCommandResponse(void) -{ - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - return (SE_Response_t)(rootOutMb->status & SE_RESPONSE_MASK); -} - -/***************************************************************************//** - * @brief - * Acknowledge and get status and output data of a completed command. - * - * @details - * This function acknowledges and gets the status and output data of a - * completed mailbox command. - * The mailbox command is acknowledged by inverting all bits in the checksum - * (XOR with 0xFFFFFFFF). - * The output data is copied into the linked list of output buffers pointed - * to in the given command data structure. - * - * @param[in] command - * Pointer to an SE command structure. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - * @retval SE_RESPONSE_MAILBOX_INVALID when mailbox command not done or invalid - ******************************************************************************/ -SE_Response_t SE_ackCommand(SE_Command_t *command) -{ - // Setup pointer to the VSE Output Mailbox data structure - // (must be stored in a RAM area which is not used by the VSE) - bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; - root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; - if (!sysCfgClkWasEnabled) { - CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; - } - uint32_t *mbData = (uint32_t*) rootOutMb->data; - SE_DataTransfer_t *outDataDesc = command->data_out; - unsigned int outDataLen, outDataCnt, i, outDescLen; - uint32_t *outData; - - // First verify that the Output Mailbox includes a valid response. - if (!SE_isCommandCompleted()) { - return SE_RESPONSE_MAILBOX_INVALID; - } - - // Get output data length - outDataLen = rootOutMb->length; - - // Acknowledge the output mailbox response by invalidating checksum - mbData[outDataLen] ^= 0xFFFFFFFFUL; - - // Check command status code - if ((rootOutMb->status & SE_RESPONSE_MASK) != SE_RESPONSE_OK) { - return rootOutMb->status & SE_RESPONSE_MASK; - } - - // Copy data from the Output Mailbox to the linked list of output - // buffers provided by the user - outDataCnt = 0; - while (outDataDesc && (outDataCnt < outDataLen)) { - outData = (uint32_t*) outDataDesc->data; - outDescLen = - (outDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); - for (i = 0; (i < outDescLen) && (outDataCnt < outDataLen); i++) { - outData[i] = mbData[outDataCnt++]; - } - // If we have reached the end of a buffer, go to next buffer descriptor - if (i == outDescLen) { - outDataDesc = (SE_DataTransfer_t*) - ((uint32_t)outDataDesc->next & ~SE_DATATRANSFER_STOP); - } - } - - // Check if the output data list is too small to copy all output data in - // mailbox. - if ((outDataDesc == 0) && (outDataCnt < outDataLen)) { - return SE_RESPONSE_INVALID_PARAMETER; - } - - return SE_RESPONSE_OK; -} - -#endif // #if defined(CRYPTOACC_PRESENT) - -/******************************************************************************* - ***************************** DEPRECATED ********************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup se_deprecated - * - * @{ - ******************************************************************************/ - -/******************************************************************************* -* The following functions have been deprecated and will be removed in a future -* version of emlib. All high-level functionality have been moved to the SE -* manager. -*******************************************************************************/ - -#if !defined(SLI_EM_SE_HOST) -/***************************************************************************//** - * @brief - * - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Init pubkey or pubkey signature. - * - * @details - * Initialize public key stored in the SE, or its corresponding signature. The - * command can be used to write: - * * SE_KEY_TYPE_BOOT -- public key used to perform secure boot - * * SE_KEY_TYPE_AUTH -- public key used to perform secure debug - * - * @note - * These keys can not be overwritten, so this command can only be issued once - * per key per part. - * - * @param[in] key_type - * ID of key type to initialize. - * - * @param[in] pubkey - * Pointer to a buffer that contains the public key or signature. - * Must be word aligned and have a length of 64 bytes. - * - * @param[in] numBytes - * Length of pubkey buffer (64 bytes). - * - * @param[in] signature - * If true, initialize signature for the specified key type instead of the - * public key itself. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed - ******************************************************************************/ -SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) -{ - uint32_t commandWord = SE_COMMAND_INIT_PUBKEY; - SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; - - EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) - || (key_type == SE_KEY_TYPE_AUTH)); - - EFM_ASSERT(numBytes == 64); - EFM_ASSERT(!((size_t)pubkey & 3U)); - - // Find parity word - volatile uint32_t parity = 0; - for (size_t i = 0; i < numBytes / 4; i++) { - parity = parity ^ ((uint32_t *)pubkey)[i]; - } - - // SE command structures -#if defined(SEMAILBOX_PRESENT) - commandWord = - (signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY; -#elif defined(CRYPTOACC_PRESENT) - (void)signature; -#endif - SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); - - SE_DataTransfer_t parityData = SE_DATATRANSFER_DEFAULT(&parity, 4); - SE_addDataInput(&command, &parityData); - - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); - SE_addDataInput(&command, &pubkeyData); - - SE_executeCommand(&command); -#if defined(SEMAILBOX_PRESENT) - res = SE_readCommandResponse(); -#endif - return res; -} - -/***************************************************************************//** - * @brief - * - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Initialize SE one-time-programmable (OTP) configuration. - * - * @details - * Configuration is performed by setting the desired options in the - * @ref SE_OTPInit_t structure. - * - * This function can be used to enable secure boot, to configure flash page - * locking, and to enable anti-rollback protection when using the SE to - * perform an application upgrade, typically a Gecko bootloader upgrade. - * - * Before secure boot can be enabled, the public key used for secure boot - * verification must be uploaded using @ref SE_initPubkey(). - * - * @warning - * This command can only be executed once per device! When the configuration - * has been programmed it is not possible to update any of the fields. - * - * @param[in] otp_init - * @ref SE_OTPInit_t structure containing the SE configuration. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - ******************************************************************************/ -SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) -{ - uint32_t mcuSettingsFlags = 0; - - SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; - - if (otp_init->enableSecureBoot) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; - -#if defined(SEMAILBOX_PRESENT) - uint8_t pubkey[64]; - { - EFM_ASSERT(!((size_t)pubkey & 3U)); - // SE command structures - SE_Command_t commandPubkeyRead = SE_COMMAND_DEFAULT(SE_COMMAND_READ_PUBKEY | SE_KEY_TYPE_BOOT); - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, sizeof(pubkey)); - SE_addDataOutput(&commandPubkeyRead, &pubkeyData); - SE_executeCommand(&commandPubkeyRead); - res = SE_readCommandResponse(); - if (res != SE_RESPONSE_OK) { - return SE_RESPONSE_ABORT; - } - res = SE_RESPONSE_INVALID_COMMAND; - } -#endif - } - if (otp_init->verifySecureBootCertificate) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; - } - if (otp_init->enableAntiRollback) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; - } - - if (otp_init->secureBootPageLockNarrow && otp_init->secureBootPageLockFull) { - return SE_RESPONSE_ABORT; - } - if (otp_init->secureBootPageLockNarrow) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; - } - if (otp_init->secureBootPageLockFull) { - mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; - } - - // Find parity word - volatile uint32_t parity = 0; - parity = parity ^ mcuSettingsFlags; - - volatile uint32_t parameters[2] = { - parity, - sizeof(mcuSettingsFlags) - }; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_INIT_OTP); - -#if defined(SEMAILBOX_PRESENT) - static struct ReservedSettings { - uint8_t reserved1[16]; - uint8_t reserved2[2]; - uint8_t reserved3[2]; - } reservedSettings = { - { 0x00 }, - { 0xFF }, - { 0x00 } - }; - - for (size_t i = 0; i < 5; i++) { - parity = parity ^ ((uint32_t*)(&reservedSettings))[i]; - } - parameters[0] = parity; - parameters[1] = parameters[1] + sizeof(reservedSettings); - - SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(&command, ¶metersData); - - SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); - SE_addDataInput(&command, &mcuSettingsFlagsData); - - SE_DataTransfer_t reservedSettingsData = SE_DATATRANSFER_DEFAULT((volatile void *)&reservedSettings, sizeof(reservedSettings)); - SE_addDataInput(&command, &reservedSettingsData); - - SE_executeCommand(&command); - - res = SE_readCommandResponse(); -#elif defined(CRYPTOACC_PRESENT) - SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(&command, ¶metersData); - - SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); - SE_addDataInput(&command, &mcuSettingsFlagsData); - - SE_executeCommand(&command); -#else - (void)command; - (void)parameters; -#endif - - return res; -} - -#if defined(SEMAILBOX_PRESENT) - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Writes data to User Data section in MTP. Write data must be aligned to - * word size and contain a number of bytes that is divisable by four. - * - * @note - * It is recommended to erase the flash page before performing a write. - * - * @param[in] offset - * Offset to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] numBytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -SE_Response_t SE_writeUserData(uint32_t offset, - void *data, - uint32_t numBytes) -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_WRITE_USER_DATA); - SE_DataTransfer_t userData = SE_DATATRANSFER_DEFAULT(data, numBytes); - - SE_addDataInput(&command, &userData); - - SE_addParameter(&command, offset); - SE_addParameter(&command, numBytes); - - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Erases User Data section in MTP. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully or a - * signature was successfully verified, - * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, - * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, - * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, - * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, - * e.g. because of conflicting Secure/Non-Secure - * memory accesses, - * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -SE_Response_t SE_eraseUserData() -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_ERASE_USER_DATA); - - SE_addParameter(&command, SE_COMMAND_OPTION_ERASE_UD); - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Returns the current boot status, versions and system configuration. - * - * @param[out] status - * @ref SE_Status_t containing current SE status. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK upon command completion. Errors are encoded in the - * different parts of the returned status object. - ******************************************************************************/ -SE_Response_t SE_getStatus(SE_Status_t *status) -{ - volatile uint32_t output[9] = { 0 }; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_GET_STATUS); - SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT((void*)output, 4 * 9); - - SE_addDataOutput(&command, &outData); - - // Execute command and return response - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - - // Update status object - status->bootStatus = output[4]; - status->seFwVersion = output[5]; - status->hostFwVersion = output[6]; - - SE_DebugStatus_t debugStatus; - debugStatus.debugLockEnabled = (output[7] & (1 << 0)); - debugStatus.deviceEraseEnabled = (output[7] & (1 << 1)); - debugStatus.secureDebugEnabled = (output[7] & (1 << 2)); - status->debugStatus = debugStatus; - - status->secureBootEnabled = ((output[8] & 0x1) && ((output[8] & ~0x1) == 0)); - - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Read the serial number of the SE module. - * - * @param[out] serial - * Pointer to array of size 16 bytes. - * - * @return - * One of the @ref SE_Response_t return codes. - * @retval SE_RESPONSE_OK when serial number is returned successfully, - * @retval SE_RESPONSE_INTERNAL_ERROR if not. - ******************************************************************************/ -SE_Response_t SE_serialNumber(void *serial) -{ - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_READ_SERIAL); - SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT(serial, 16); - - SE_addDataOutput(&command, &outData); - - // Execute command and return response - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Read pubkey or pubkey signature. - * - * @details - * Read out a public key stored in the SE, or its signature. The command can - * be used to read: - * * SE_KEY_TYPE_BOOT - * * SE_KEY_TYPE_AUTH - * - * @param[in] key_type - * ID of key type to read. - * - * @param[out] pubkey - * Pointer to a buffer to contain the returned public key. - * Must be word aligned and have a length of 64 bytes. - * - * @param[in] numBytes - * Length of pubkey buffer (64 bytes). - * - * @param[in] signature - * If true, the function will return the signature programmed for the - * specified public key instead of the public key itself. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully - * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set - * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed - ******************************************************************************/ -SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) -{ - EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) - || (key_type == SE_KEY_TYPE_AUTH)); - - EFM_ASSERT(numBytes == 64); - EFM_ASSERT(!((size_t)pubkey & 3U)); - - // SE command structures - uint32_t commandWord = - (signature) ? SE_COMMAND_READ_PUBKEY_SIGNATURE : SE_COMMAND_READ_PUBKEY; - SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); - - SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); - SE_addDataOutput(&command, &pubkeyData); - - SE_executeCommand(&command); - SE_Response_t res = SE_readCommandResponse(); - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Returns the current debug lock configuration. - * @param[out] status - * The command returns a @ref SE_DebugStatus_t with the current status of the - * debug configuration. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there are configuration errors. - ******************************************************************************/ -SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) -{ - SE_Response_t res; - - // SE command structures - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_STATUS); - - volatile uint32_t status_word = 0; - SE_DataTransfer_t statusData = SE_DATATRANSFER_DEFAULT((void*)&status_word, 4); - SE_addDataOutput(&command, &statusData); - - SE_executeCommand(&command); - res = SE_readCommandResponse(); - - status->debugLockEnabled = (status_word & (1 << 0)); - status->deviceEraseEnabled = (status_word & (1 << 1)); - status->secureDebugEnabled = (status_word & (1 << 2)); - - return res; -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Enables the debug lock for the part. - * @details - * The debug port will be closed and the only way to open it is through - * device erase (if enabled) or temporarily through secure debug unlock (if - * enabled). - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR there was a problem locking the debug port. - ******************************************************************************/ -SE_Response_t SE_debugLockApply(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_APPLY); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Enables the secure debug functionality. - * @details - * Enables the secure debug functionality. This functionality makes it - * possible to open a locked debug port by signing a cryptographic challenge - * and using the debug command interface (DCI). - * - * This command can only be executed before the debug port is locked, and - * after a secure debug public key has been installed in the SE using - * @ref SE_initPubkey() or the corresponding DCI command. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INVALID_COMMAND if debug port is locked. - * @retval SE_RESPONSE_INVALID_PARAMETER if secure debug certificates are - * missing. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_debugSecureEnable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_ENABLE_SECURE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Disables the secure debug functionality. - * @details - * Disables the secure debug functionality that can be used to open a - * locked debug port. - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_debugSecureDisable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_DISABLE_SECURE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Performs a device mass erase and debug unlock. - * - * @details - * Performs a device mass erase and resets the debug configuration to its - * initial unlocked state. Only available before @ref SE_deviceEraseDisable or - * the corresponding DCI command has been executed. - * - * @note - * This command clears and verifies the complete flash and ram of the - * system, excluding the user data pages and one-time programmable - * commissioning information in the secure element. - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INVALID_COMMAND if device erase is disabled. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_deviceErase(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -/***************************************************************************//** - * @brief - * @deprecated - * This function has been moved to the SE manager, and will be removed in a - * future version of emlib. - * - * Disabled device erase functionality. - * - * @details - * This command disables the device erase command. It does not lock the - * debug interface to the part, but it is a permanent action for the part. - * If device erase is disabled and the device is debug locked, there is no - * way to permanently unlock the part. If secure debug unlock is enabled, - * secure debug unlock can still be used to temporarily open the debug port. - * - * @warning - * This command permanently disables the device erase functionality! - * - * @return - * One of the SE_RESPONSE return codes. - * @retval SE_RESPONSE_OK when the command was executed successfully. - * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. - ******************************************************************************/ -SE_Response_t SE_deviceEraseDisable(void) -{ - SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE_DISABLE); - SE_executeCommand(&command); - - return SE_readCommandResponse(); -} - -#endif // #if defined(SEMAILBOX_PRESENT) -#endif // #if !defined(SLI_EM_SE_HOST) - -/** @} (end addtogroup deprecated_se) */ -/** @} (end addtogroup se) */ - -#endif /* defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) */ +/***************************************************************************//** + * @file + * @brief Secure Element API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_se.h" + +#if defined(SLI_EM_SE_HOST) || defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + +#include "em_core.h" +#include "sl_assert.h" +#include "em_system.h" + +#endif + +/***************************************************************************//** + * @addtogroup se + * @{ + ******************************************************************************/ + +/******************************************************************************* + ****************************** DEFINES *********************************** + ******************************************************************************/ +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +/* OTP initialization structure defines. */ +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) + +#if defined(CRYPTOACC_PRESENT) + +/// Signal that OTP version is incorporated into the status field of the output +#define SE_VSE_REPLY_STATUS_OTP_VERSION_SET (1 << 21) +/// Mask defining the region of the status field that contains the OTP version +/// number. +#define SE_VSE_REPLY_STATUS_OTP_VERSION_MASK (0xFF000000UL) +/// Shift to insert a number into the otp version part of the status field +#define SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT (24) + +/* Size of VSE Mailbox instance. + There are two instances, input and output. */ +#define ROOT_MAILBOX_SIZE (512UL) + +/* Base addresses of the VSE Input and Output Mailbox data structures. + (Must be stored in a RAM area which is not used by the VSE) + We use the upper 1KB of FRC RAM for the VSE mailboxes. */ +#define ROOT_MAILBOX_OUTPUT_S_BASE (RDMEM_FRCRAM_S_MEM_END + 1 - ROOT_MAILBOX_SIZE) +#define ROOT_MAILBOX_INPUT_S_BASE (ROOT_MAILBOX_OUTPUT_S_BASE - ROOT_MAILBOX_SIZE) + +// SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S is defined in sl_trustzone_secure_config.h +#if ((defined(SL_TRUSTZONE_SECURE) && !defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) \ + || (defined(SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S) && SL_TRUSTZONE_PERIPHERAL_AHBRADIO_S)) + +#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_S_MEM_BASE + +#define ROOT_MAILBOX_OUTPUT_BASE SYSCFG->ROOTDATA1; +#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED ROOT_MAILBOX_OUTPUT_S_BASE +#else +#define RDMEM_FRCRAM_MEM_BASE RDMEM_FRCRAM_NS_MEM_BASE + +// VSE will always output the secure address, if NS is desired, caculate the NS address. +#define ROOT_MAILBOX_OUTPUT_BASE (SYSCFG->ROOTDATA1 - RDMEM_FRCRAM_S_MEM_BASE + RDMEM_FRCRAM_NS_MEM_BASE); +#define ROOT_MAILBOX_OUTPUT_BASE_EXPECTED (RDMEM_FRCRAM_NS_MEM_END + 1 - ROOT_MAILBOX_SIZE) +#endif +#define ROOT_MAILBOX_INPUT_BASE (ROOT_MAILBOX_OUTPUT_BASE_EXPECTED - ROOT_MAILBOX_SIZE) + +/* Position of parameter number field in VSE Input Mailbox LENGTH field.*/ +#define ROOT_MB_LENGTH_PARAM_NUM_SHIFT (24) + +/* Done flag indicating that the VSE Mailbox handler has completed + processing the mailbox command. */ +#define ROOT_MB_DONE (1 << 23) + +/* VSE Configuration Status bits mask */ +#define ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK (0xFFFF) + +#endif // #if defined(CRYPTOACC_PRESENT) +/** @endcond */ + +/******************************************************************************* + ****************************** TYPEDEFS *********************************** + ******************************************************************************/ +#if defined(CRYPTOACC_PRESENT) +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +// VSE Input Mailbox structure +typedef struct { + volatile uint32_t magic; + volatile uint32_t command; + volatile uint32_t length; + volatile uint32_t data[0]; +} root_InputMailbox_t; + +// VSE Output Mailbox structure +typedef struct { + volatile uint32_t magic; + volatile uint32_t version; + volatile uint32_t status; + volatile uint32_t command; + volatile uint32_t length; + volatile uint32_t data[0]; +} root_OutputMailbox_t; +/** @endcond */ + +#endif // #if defined(CRYPTOACC_PRESENT) + +/******************************************************************************* + ************************** STATIC FUNCTIONS ******************************* + ******************************************************************************/ + +#if defined(SEMAILBOX_PRESENT) +/***************************************************************************//** + * @brief + * Write to FIFO + * + * @param value + * Value to write to FIFO + ******************************************************************************/ +#if defined(_SEMAILBOX_FIFO_RESETVALUE) +__STATIC_INLINE void writeToFifo(uint32_t value) +{ + SEMAILBOX_HOST->FIFO = value; +} +#else +__STATIC_INLINE void writeToFifo(uint32_t value) +{ + SEMAILBOX_HOST->FIFO[0].DATA = value; +} +#endif + +#endif // SEMAILBOX_PRESENT + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Add input data to a command + * + * @details + * This function adds a buffer of input data to the given SE command structure + * The buffer gets appended by reference at the end of the list of already + * added buffers. + * + * @note + * Note that this function does not copy either the data buffer or the buffer + * structure, so make sure to keep the data object in scope until the command + * has been executed by the secure element. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @param[in] data + * Pointer to a data transfer structure. + ******************************************************************************/ +void SE_addDataInput(SE_Command_t *command, SE_DataTransfer_t *data) +{ + if (command->data_in == NULL) { + command->data_in = data; + } else { + SE_DataTransfer_t *next = command->data_in; + while (next->next != (void*)SE_DATATRANSFER_STOP) { + next = (SE_DataTransfer_t*)next->next; + } + next->next = data; + } +} + +/***************************************************************************//** + * @brief + * Add output data to a command + * + * @details + * This function adds a buffer of output data to the given command structure + * The buffer gets appended by reference at the end of the list of already + * added buffers. + * + * @note + * Note that this function does not copy either the data buffer or the buffer + * structure, so make sure to keep the data object in scope until the command + * has been executed by the secure element. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @param[in] data + * Pointer to a data transfer structure. + ******************************************************************************/ +void SE_addDataOutput(SE_Command_t *command, + SE_DataTransfer_t *data) +{ + if (command->data_out == NULL) { + command->data_out = data; + } else { + SE_DataTransfer_t *next = command->data_out; + while (next->next != (void*)SE_DATATRANSFER_STOP) { + next = (SE_DataTransfer_t*)next->next; + } + next->next = data; + } +} + +/***************************************************************************//** + * @brief + * Add a parameter to a command + * + * @details + * This function adds a parameter word to the passed command. + * + * @note + * Make sure to not exceed @ref SE_MAX_PARAMETERS. + * + * @param[in] command + * Pointer to a filled-out SE command structure. + * @param[in] parameter + * Parameter to add. + ******************************************************************************/ +void SE_addParameter(SE_Command_t *command, uint32_t parameter) +{ + if (command->num_parameters >= SE_MAX_PARAMETERS) { + EFM_ASSERT(command->num_parameters < SE_MAX_PARAMETERS); + return; + } + + command->parameters[command->num_parameters] = parameter; + command->num_parameters += 1; +} + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * Execute the passed command + * + * @details + * This function starts the execution of the passed command by the secure + * element. When started, wait for the RXINT interrupt flag, or call + * @ref SE_waitCommandCompletion to busy-wait. After completion, you have to + * call @ref SE_readCommandResponse to get the command's execution status. + * + * @param[in] command + * Pointer to a filled-out SE command structure. + ******************************************************************************/ +void SE_executeCommand(SE_Command_t *command) +{ + // Don't overflow our struct + if (command->num_parameters > SE_MAX_PARAMETERS) { + EFM_ASSERT(command->num_parameters <= SE_MAX_PARAMETERS); + return; + } + +#if defined(SEMAILBOX_PRESENT) + + // Wait for room available in the mailbox + while (!(SEMAILBOX_HOST->TX_STATUS & SEMAILBOX_TX_STATUS_TXINT)) ; + + // Write header to start transaction + SEMAILBOX_HOST->TX_HEADER = sizeof(uint32_t) * (4 + command->num_parameters); + + // Write command into FIFO + writeToFifo(command->command); + + // Write DMA descriptors into FIFO + writeToFifo((uint32_t)command->data_in); + writeToFifo((uint32_t)command->data_out); + + // Write applicable parameters into FIFO + for (size_t i = 0; i < command->num_parameters; i++) { + writeToFifo(command->parameters[i]); + } + +#elif defined(CRYPTOACC_PRESENT) + // Prepare the VSE Mailbox within a critical section to prevent + // the process from getting interrupted. At this point, the only option + // we have is to go through a reset, so it is safe to enter the critical section. + (void)CORE_EnterCritical(); + + // Setup pointer to the VSE Mailbox Input data structure + // (must be stored in a RAM area which is not used by the VSE) + root_InputMailbox_t *rootInMb = (root_InputMailbox_t*)ROOT_MAILBOX_INPUT_BASE; + uint32_t *mbData; + unsigned int mbDataLen, inDataLen, i; + SE_DataTransfer_t *inDataDesc; + uint32_t *inData; + uint32_t checksum; + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + + // Store the secure memory base addresses for VSE to be able to read from the address + // Set base of Mailbox Input data structure in SYSCFG register in order + // for VSE to find it. + SYSCFG->ROOTDATA0 = ROOT_MAILBOX_INPUT_S_BASE; + // Set base of Mailbox Output data structure in SYSCFG register in order + // for VSE to know where to write output data. + // Write command into FIFO + SYSCFG->ROOTDATA1 = ROOT_MAILBOX_OUTPUT_S_BASE; + + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + rootInMb->magic = SE_RESPONSE_MAILBOX_VALID; + rootInMb->command = command->command; + + // Write applicable parameters into Mailbox DATA array + mbData = (uint32_t*) rootInMb->data; + for (mbDataLen = 0; mbDataLen < command->num_parameters; mbDataLen++) { + mbData[mbDataLen] = command->parameters[mbDataLen]; + } + + // Write input data into Mailbox DATA array + inDataLen = 0; + for (inDataDesc = command->data_in; inDataDesc; inDataDesc = (SE_DataTransfer_t*) inDataDesc->next) { + inData = (uint32_t*) inDataDesc->data; + for (i = 0; i < (inDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); i++) { + // Make sure we do not overflow the input mailbox. + EFM_ASSERT(mbDataLen < ROOT_MAILBOX_SIZE); + mbData[mbDataLen++] = inData[i]; + inDataLen++; + } + if (inDataDesc->next == (void*)SE_DATATRANSFER_STOP) { + break; + } + } + + // Write number of parameters and data words to 'length' field of mailbox. + rootInMb->length = + inDataLen | (command->num_parameters << ROOT_MB_LENGTH_PARAM_NUM_SHIFT); + + // Calculate checksum using bitwise XOR over the all words in the mailbox + // data structure, minus the CHECKSUM word (32bit = 4bytes ) at the end. + checksum = rootInMb->magic; + checksum ^= rootInMb->command; + checksum ^= rootInMb->length; + for (i = 0; i < mbDataLen; i++) { + checksum ^= mbData[i]; + } + + // Finally, write the calculated checksum to mailbox checksum field + mbData[mbDataLen] = checksum; + + __NVIC_SystemReset(); + +#endif // #if defined(SEMAILBOX_PRESENT) +} + +#endif // #if !defined(SLI_EM_SE_HOST) + +#if defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @brief + * Check whether the VSE Output Mailbox is valid. + * + * @return True if the VSE Output Mailbox is valid (magic and checksum OK) + ******************************************************************************/ +bool rootIsOutputMailboxValid(void) +{ + // Setup pointer to the VSE Output Mailbox data structure + // (must be stored in a RAM area which is not used by the VSE) + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if ((uint32_t)rootOutMb > ROOT_MAILBOX_OUTPUT_BASE_EXPECTED + || (uint32_t)rootOutMb < RDMEM_FRCRAM_MEM_BASE) { + return false; + } + + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + uint32_t *mbPtr = (uint32_t*) rootOutMb; + uint32_t checksum; + unsigned int mbLen, cnt; + + // Verify magic word of mailbox + if (rootOutMb->magic != SE_RESPONSE_MAILBOX_VALID) { + return false; + } + + // Get length of mailbox + mbLen = sizeof(root_OutputMailbox_t) / sizeof(uint32_t) + rootOutMb->length; + if (mbLen >= ROOT_MAILBOX_SIZE) { + return false; + } + // Calculate checksum using bitwise XOR over all words in the mailbox + // data structure, minus the CHECKSUM word at the end. + for (checksum = 0, cnt = 0; cnt < mbLen; cnt++) { + checksum ^= mbPtr[cnt]; + } + + // Verify that the calculated checksum is equal to the mailbox checksum. + return (mbPtr[mbLen] == checksum); +} + +/***************************************************************************//** + * @brief + * Get current SE version + * + * @details + * This function returns the current VSE version + * + * @param[in] version + * Pointer to location where to copy the version of VSE to. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_getVersion(uint32_t *version) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (version == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Return the 'version' from the Output Mailbox + *version = rootOutMb->version; + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Get VSE configuration and status bits + * + * @details + * This function returns the current VSE configuration and status bits. + * The following list explains what the different bits in cfgStatus indicate. + * A bit value of 1 means enabled, while 0 means disabled: + * * [0]: Secure boot + * * [1]: Verify secure boot certificate + * * [2]: Anti-rollback + * * [3]: Narrow page lock + * * [4]: Full page lock + * The following status bits can be read with VSE versions + * higher than 1.2.2. + * * [10]: Debug port lock + * * [11]: Device erase enabled + * * [12]: Secure debug enabled + * * [15]: Debug port register state, 1 if the debug port is locked. + * + * @param[out] cfgStatus + * Pointer to location to copy Configuration Status bits into. + * + * @note + * This function will check that the mailbox content is valid before + * reading the status bits. If the command response has already been read + * with a call to @ref SE_ackCommand(), the validity check will fail, and + * the config status bits cannot be read before a reset has occurred. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_getConfigStatusBits(uint32_t *cfgStatus) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (cfgStatus == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Return the configuration status bits + *cfgStatus = rootOutMb->status & ROOT_MB_OUTPUT_STATUS_CONFIG_BITS_MASK; + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Get the version number of the OTP from the status field of the output + * mailbox + * @details + * This function checks if the OTP version number flag is set in the output + * mailbox. If it is, the version number is writen to @ref otpVersion pointer + * location. If not, it returns error response. + * + * @param[out] otpVersion + * Pointer to location to copy OTP version number into. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + ******************************************************************************/ +SE_Response_t SE_getOTPVersion(uint32_t *otpVersion) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + if (otpVersion == NULL) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + // First verify that the response is ok. + if (!rootIsOutputMailboxValid()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + bool isOTPVersionSet = rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_SET; + if (isOTPVersionSet) { + // Return the OTP version from the status field. + *otpVersion = (rootOutMb->status & SE_VSE_REPLY_STATUS_OTP_VERSION_MASK) >> SE_VSE_REPLY_STATUS_OTP_VERSION_SHIFT; + } else { + return SE_RESPONSE_INVALID_COMMAND; + } + + return SE_RESPONSE_OK; +} + +/***************************************************************************//** + * @brief + * Check whether the running command has completed. + * + * @details + * This function polls the SE-to-host mailbox interrupt flag. + * + * @return True if a command has completed and the result is available + ******************************************************************************/ +bool SE_isCommandCompleted(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the response is ok + if (!rootIsOutputMailboxValid()) { + return false; + } + + // Check status MB_DONE flag of the mailbox + return ((rootOutMb->status & ROOT_MB_DONE) == ROOT_MB_DONE); +} + +/***************************************************************************//** + * @brief + * Read the previously executed command. + * + * @details + * This function reads the previously executed command. + * + * @return + * One of the SE command words. + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid. + ******************************************************************************/ +uint32_t SE_readExecutedCommand(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + return rootOutMb->command; +} + +/***************************************************************************//** + * @brief + * Read the status of the previously executed command. + * + * @details + * This function reads the status of the previously executed command. + * + * @return + * One of the SE_RESPONSE return codes: + * SE_RESPONSE_OK when the command was executed successfully or a signature + * was successfully verified, + * SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, e.g. + * because of conflicting Secure/Non-Secure memory accesses, + * SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * SE_RESPONSE_MAILBOX_INVALID when the mailbox content is invalid + ******************************************************************************/ +SE_Response_t SE_readCommandResponse(void) +{ + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + return (SE_Response_t)(rootOutMb->status & SE_RESPONSE_MASK); +} + +/***************************************************************************//** + * @brief + * Acknowledge and get status and output data of a completed command. + * + * @details + * This function acknowledges and gets the status and output data of a + * completed mailbox command. + * The mailbox command is acknowledged by inverting all bits in the checksum + * (XOR with 0xFFFFFFFF). + * The output data is copied into the linked list of output buffers pointed + * to in the given command data structure. + * + * @param[in] command + * Pointer to an SE command structure. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + * @retval SE_RESPONSE_MAILBOX_INVALID when mailbox command not done or invalid + ******************************************************************************/ +SE_Response_t SE_ackCommand(SE_Command_t *command) +{ + // Setup pointer to the VSE Output Mailbox data structure + // (must be stored in a RAM area which is not used by the VSE) + bool sysCfgClkWasEnabled = ((CMU->CLKEN0 & CMU_CLKEN0_SYSCFG) != 0); + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; + root_OutputMailbox_t *rootOutMb = (root_OutputMailbox_t *) ROOT_MAILBOX_OUTPUT_BASE; + if (!sysCfgClkWasEnabled) { + CMU->CLKEN0_CLR = CMU_CLKEN0_SYSCFG; + } + uint32_t *mbData = (uint32_t*) rootOutMb->data; + SE_DataTransfer_t *outDataDesc = command->data_out; + unsigned int outDataLen, outDataCnt, i, outDescLen; + uint32_t *outData; + + // First verify that the Output Mailbox includes a valid response. + if (!SE_isCommandCompleted()) { + return SE_RESPONSE_MAILBOX_INVALID; + } + + // Get output data length + outDataLen = rootOutMb->length; + + // Acknowledge the output mailbox response by invalidating checksum + mbData[outDataLen] ^= 0xFFFFFFFFUL; + + // Check command status code + if ((rootOutMb->status & SE_RESPONSE_MASK) != SE_RESPONSE_OK) { + return rootOutMb->status & SE_RESPONSE_MASK; + } + + // Copy data from the Output Mailbox to the linked list of output + // buffers provided by the user + outDataCnt = 0; + while (outDataDesc && (outDataCnt < outDataLen)) { + outData = (uint32_t*) outDataDesc->data; + outDescLen = + (outDataDesc->length & SE_DATATRANSFER_LENGTH_MASK) / sizeof(uint32_t); + for (i = 0; (i < outDescLen) && (outDataCnt < outDataLen); i++) { + outData[i] = mbData[outDataCnt++]; + } + // If we have reached the end of a buffer, go to next buffer descriptor + if (i == outDescLen) { + outDataDesc = (SE_DataTransfer_t*) + ((uint32_t)outDataDesc->next & ~SE_DATATRANSFER_STOP); + } + } + + // Check if the output data list is too small to copy all output data in + // mailbox. + if ((outDataDesc == 0) && (outDataCnt < outDataLen)) { + return SE_RESPONSE_INVALID_PARAMETER; + } + + return SE_RESPONSE_OK; +} + +#endif // #if defined(CRYPTOACC_PRESENT) + +/******************************************************************************* + ***************************** DEPRECATED ********************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup se_deprecated + * + * @{ + ******************************************************************************/ + +/******************************************************************************* +* The following functions have been deprecated and will be removed in a future +* version of emlib. All high-level functionality have been moved to the SE +* manager. +*******************************************************************************/ + +#if !defined(SLI_EM_SE_HOST) +/***************************************************************************//** + * @brief + * + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Init pubkey or pubkey signature. + * + * @details + * Initialize public key stored in the SE, or its corresponding signature. The + * command can be used to write: + * * SE_KEY_TYPE_BOOT -- public key used to perform secure boot + * * SE_KEY_TYPE_AUTH -- public key used to perform secure debug + * + * @note + * These keys can not be overwritten, so this command can only be issued once + * per key per part. + * + * @param[in] key_type + * ID of key type to initialize. + * + * @param[in] pubkey + * Pointer to a buffer that contains the public key or signature. + * Must be word aligned and have a length of 64 bytes. + * + * @param[in] numBytes + * Length of pubkey buffer (64 bytes). + * + * @param[in] signature + * If true, initialize signature for the specified key type instead of the + * public key itself. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed + ******************************************************************************/ +SE_Response_t SE_initPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) +{ + uint32_t commandWord = SE_COMMAND_INIT_PUBKEY; + SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; + + EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) + || (key_type == SE_KEY_TYPE_AUTH)); + + EFM_ASSERT(numBytes == 64); + EFM_ASSERT(!((size_t)pubkey & 3U)); + + // Find parity word + volatile uint32_t parity = 0; + for (size_t i = 0; i < numBytes / 4; i++) { + parity = parity ^ ((uint32_t *)pubkey)[i]; + } + + // SE command structures +#if defined(SEMAILBOX_PRESENT) + commandWord = + (signature) ? SE_COMMAND_INIT_PUBKEY_SIGNATURE : SE_COMMAND_INIT_PUBKEY; +#elif defined(CRYPTOACC_PRESENT) + (void)signature; +#endif + SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); + + SE_DataTransfer_t parityData = SE_DATATRANSFER_DEFAULT(&parity, 4); + SE_addDataInput(&command, &parityData); + + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); + SE_addDataInput(&command, &pubkeyData); + + SE_executeCommand(&command); +#if defined(SEMAILBOX_PRESENT) + res = SE_readCommandResponse(); +#endif + return res; +} + +/***************************************************************************//** + * @brief + * + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Initialize SE one-time-programmable (OTP) configuration. + * + * @details + * Configuration is performed by setting the desired options in the + * @ref SE_OTPInit_t structure. + * + * This function can be used to enable secure boot, to configure flash page + * locking, and to enable anti-rollback protection when using the SE to + * perform an application upgrade, typically a Gecko bootloader upgrade. + * + * Before secure boot can be enabled, the public key used for secure boot + * verification must be uploaded using @ref SE_initPubkey(). + * + * @warning + * This command can only be executed once per device! When the configuration + * has been programmed it is not possible to update any of the fields. + * + * @param[in] otp_init + * @ref SE_OTPInit_t structure containing the SE configuration. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + ******************************************************************************/ +SE_Response_t SE_initOTP(SE_OTPInit_t *otp_init) +{ + uint32_t mcuSettingsFlags = 0; + + SE_Response_t res = SE_RESPONSE_INVALID_COMMAND; + + if (otp_init->enableSecureBoot) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; + +#if defined(SEMAILBOX_PRESENT) + uint8_t pubkey[64]; + { + EFM_ASSERT(!((size_t)pubkey & 3U)); + // SE command structures + SE_Command_t commandPubkeyRead = SE_COMMAND_DEFAULT(SE_COMMAND_READ_PUBKEY | SE_KEY_TYPE_BOOT); + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, sizeof(pubkey)); + SE_addDataOutput(&commandPubkeyRead, &pubkeyData); + SE_executeCommand(&commandPubkeyRead); + res = SE_readCommandResponse(); + if (res != SE_RESPONSE_OK) { + return SE_RESPONSE_ABORT; + } + res = SE_RESPONSE_INVALID_COMMAND; + } +#endif + } + if (otp_init->verifySecureBootCertificate) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; + } + if (otp_init->enableAntiRollback) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; + } + + if (otp_init->secureBootPageLockNarrow && otp_init->secureBootPageLockFull) { + return SE_RESPONSE_ABORT; + } + if (otp_init->secureBootPageLockNarrow) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; + } + if (otp_init->secureBootPageLockFull) { + mcuSettingsFlags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; + } + + // Find parity word + volatile uint32_t parity = 0; + parity = parity ^ mcuSettingsFlags; + + volatile uint32_t parameters[2] = { + parity, + sizeof(mcuSettingsFlags) + }; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_INIT_OTP); + +#if defined(SEMAILBOX_PRESENT) + static struct ReservedSettings { + uint8_t reserved1[16]; + uint8_t reserved2[2]; + uint8_t reserved3[2]; + } reservedSettings = { + { 0x00 }, + { 0xFF }, + { 0x00 } + }; + + for (size_t i = 0; i < 5; i++) { + parity = parity ^ ((uint32_t*)(&reservedSettings))[i]; + } + parameters[0] = parity; + parameters[1] = parameters[1] + sizeof(reservedSettings); + + SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(&command, ¶metersData); + + SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); + SE_addDataInput(&command, &mcuSettingsFlagsData); + + SE_DataTransfer_t reservedSettingsData = SE_DATATRANSFER_DEFAULT((volatile void *)&reservedSettings, sizeof(reservedSettings)); + SE_addDataInput(&command, &reservedSettingsData); + + SE_executeCommand(&command); + + res = SE_readCommandResponse(); +#elif defined(CRYPTOACC_PRESENT) + SE_DataTransfer_t parametersData = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(&command, ¶metersData); + + SE_DataTransfer_t mcuSettingsFlagsData = SE_DATATRANSFER_DEFAULT((volatile void *)&mcuSettingsFlags, sizeof(mcuSettingsFlags)); + SE_addDataInput(&command, &mcuSettingsFlagsData); + + SE_executeCommand(&command); +#else + (void)command; + (void)parameters; +#endif + + return res; +} + +#if defined(SEMAILBOX_PRESENT) + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Writes data to User Data section in MTP. Write data must be aligned to + * word size and contain a number of bytes that is divisable by four. + * + * @note + * It is recommended to erase the flash page before performing a write. + * + * @param[in] offset + * Offset to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] numBytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +SE_Response_t SE_writeUserData(uint32_t offset, + void *data, + uint32_t numBytes) +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_WRITE_USER_DATA); + SE_DataTransfer_t userData = SE_DATATRANSFER_DEFAULT(data, numBytes); + + SE_addDataInput(&command, &userData); + + SE_addParameter(&command, offset); + SE_addParameter(&command, numBytes); + + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Erases User Data section in MTP. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully or a + * signature was successfully verified, + * @retval SE_RESPONSE_INVALID_COMMAND when the command ID was not recognized, + * @retval SE_RESPONSE_AUTHORIZATION_ERROR when the command is not authorized, + * @retval SE_RESPONSE_INVALID_SIGNATURE when signature verification failed, + * @retval SE_RESPONSE_BUS_ERROR when a bus error was thrown during the command, + * e.g. because of conflicting Secure/Non-Secure + * memory accesses, + * @retval SE_RESPONSE_CRYPTO_ERROR on an internal SE failure, or + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +SE_Response_t SE_eraseUserData() +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_ERASE_USER_DATA); + + SE_addParameter(&command, SE_COMMAND_OPTION_ERASE_UD); + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Returns the current boot status, versions and system configuration. + * + * @param[out] status + * @ref SE_Status_t containing current SE status. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK upon command completion. Errors are encoded in the + * different parts of the returned status object. + ******************************************************************************/ +SE_Response_t SE_getStatus(SE_Status_t *status) +{ + volatile uint32_t output[9] = { 0 }; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_GET_STATUS); + SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT((void*)output, 4 * 9); + + SE_addDataOutput(&command, &outData); + + // Execute command and return response + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + + // Update status object + status->bootStatus = output[4]; + status->seFwVersion = output[5]; + status->hostFwVersion = output[6]; + + SE_DebugStatus_t debugStatus; + debugStatus.debugLockEnabled = (output[7] & (1 << 0)); + debugStatus.deviceEraseEnabled = (output[7] & (1 << 1)); + debugStatus.secureDebugEnabled = (output[7] & (1 << 2)); + status->debugStatus = debugStatus; + + status->secureBootEnabled = ((output[8] & 0x1) && ((output[8] & ~0x1) == 0)); + + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Read the serial number of the SE module. + * + * @param[out] serial + * Pointer to array of size 16 bytes. + * + * @return + * One of the @ref SE_Response_t return codes. + * @retval SE_RESPONSE_OK when serial number is returned successfully, + * @retval SE_RESPONSE_INTERNAL_ERROR if not. + ******************************************************************************/ +SE_Response_t SE_serialNumber(void *serial) +{ + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_READ_SERIAL); + SE_DataTransfer_t outData = SE_DATATRANSFER_DEFAULT(serial, 16); + + SE_addDataOutput(&command, &outData); + + // Execute command and return response + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Read pubkey or pubkey signature. + * + * @details + * Read out a public key stored in the SE, or its signature. The command can + * be used to read: + * * SE_KEY_TYPE_BOOT + * * SE_KEY_TYPE_AUTH + * + * @param[in] key_type + * ID of key type to read. + * + * @param[out] pubkey + * Pointer to a buffer to contain the returned public key. + * Must be word aligned and have a length of 64 bytes. + * + * @param[in] numBytes + * Length of pubkey buffer (64 bytes). + * + * @param[in] signature + * If true, the function will return the signature programmed for the + * specified public key instead of the public key itself. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully + * @retval SE_RESPONSE_TEST_FAILED when the pubkey is not set + * @retval SE_RESPONSE_INVALID_PARAMETER when an invalid type is passed + ******************************************************************************/ +SE_Response_t SE_readPubkey(uint32_t key_type, void *pubkey, uint32_t numBytes, bool signature) +{ + EFM_ASSERT((key_type == SE_KEY_TYPE_BOOT) + || (key_type == SE_KEY_TYPE_AUTH)); + + EFM_ASSERT(numBytes == 64); + EFM_ASSERT(!((size_t)pubkey & 3U)); + + // SE command structures + uint32_t commandWord = + (signature) ? SE_COMMAND_READ_PUBKEY_SIGNATURE : SE_COMMAND_READ_PUBKEY; + SE_Command_t command = SE_COMMAND_DEFAULT(commandWord | key_type); + + SE_DataTransfer_t pubkeyData = SE_DATATRANSFER_DEFAULT(pubkey, numBytes); + SE_addDataOutput(&command, &pubkeyData); + + SE_executeCommand(&command); + SE_Response_t res = SE_readCommandResponse(); + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Returns the current debug lock configuration. + * @param[out] status + * The command returns a @ref SE_DebugStatus_t with the current status of the + * debug configuration. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there are configuration errors. + ******************************************************************************/ +SE_Response_t SE_debugLockStatus(SE_DebugStatus_t *status) +{ + SE_Response_t res; + + // SE command structures + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_STATUS); + + volatile uint32_t status_word = 0; + SE_DataTransfer_t statusData = SE_DATATRANSFER_DEFAULT((void*)&status_word, 4); + SE_addDataOutput(&command, &statusData); + + SE_executeCommand(&command); + res = SE_readCommandResponse(); + + status->debugLockEnabled = (status_word & (1 << 0)); + status->deviceEraseEnabled = (status_word & (1 << 1)); + status->secureDebugEnabled = (status_word & (1 << 2)); + + return res; +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Enables the debug lock for the part. + * @details + * The debug port will be closed and the only way to open it is through + * device erase (if enabled) or temporarily through secure debug unlock (if + * enabled). + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR there was a problem locking the debug port. + ******************************************************************************/ +SE_Response_t SE_debugLockApply(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_APPLY); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Enables the secure debug functionality. + * @details + * Enables the secure debug functionality. This functionality makes it + * possible to open a locked debug port by signing a cryptographic challenge + * and using the debug command interface (DCI). + * + * This command can only be executed before the debug port is locked, and + * after a secure debug public key has been installed in the SE using + * @ref SE_initPubkey() or the corresponding DCI command. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INVALID_COMMAND if debug port is locked. + * @retval SE_RESPONSE_INVALID_PARAMETER if secure debug certificates are + * missing. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_debugSecureEnable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_ENABLE_SECURE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Disables the secure debug functionality. + * @details + * Disables the secure debug functionality that can be used to open a + * locked debug port. + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_debugSecureDisable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DBG_LOCK_DISABLE_SECURE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Performs a device mass erase and debug unlock. + * + * @details + * Performs a device mass erase and resets the debug configuration to its + * initial unlocked state. Only available before @ref SE_deviceEraseDisable or + * the corresponding DCI command has been executed. + * + * @note + * This command clears and verifies the complete flash and ram of the + * system, excluding the user data pages and one-time programmable + * commissioning information in the secure element. + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INVALID_COMMAND if device erase is disabled. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_deviceErase(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +/***************************************************************************//** + * @brief + * @deprecated + * This function has been moved to the SE manager, and will be removed in a + * future version of emlib. + * + * Disabled device erase functionality. + * + * @details + * This command disables the device erase command. It does not lock the + * debug interface to the part, but it is a permanent action for the part. + * If device erase is disabled and the device is debug locked, there is no + * way to permanently unlock the part. If secure debug unlock is enabled, + * secure debug unlock can still be used to temporarily open the debug port. + * + * @warning + * This command permanently disables the device erase functionality! + * + * @return + * One of the SE_RESPONSE return codes. + * @retval SE_RESPONSE_OK when the command was executed successfully. + * @retval SE_RESPONSE_INTERNAL_ERROR if there was a problem during execution. + ******************************************************************************/ +SE_Response_t SE_deviceEraseDisable(void) +{ + SE_Command_t command = SE_COMMAND_DEFAULT(SE_COMMAND_DEVICE_ERASE_DISABLE); + SE_executeCommand(&command); + + return SE_readCommandResponse(); +} + +#endif // #if defined(SEMAILBOX_PRESENT) +#endif // #if !defined(SLI_EM_SE_HOST) + +/** @} (end addtogroup deprecated_se) */ +/** @} (end addtogroup se) */ + +#endif /* defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_system.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_system.c index 9af59cf..1e3b64f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_system.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_system.c @@ -1,436 +1,436 @@ -/***************************************************************************//** - * @file - * @brief System Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_system.h" -#include "sl_assert.h" -#include -#if defined(SYSCFG_PRESENT) -#include "em_syscfg.h" -#endif -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/* Bit mask used to extract the part number value without the new naming - * bitfield. */ -#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 -#define SYSCFG_CHIPREV_PARTNUMBER0 0xF - -/* Bit mask to convert NON-SECURE to SECURE */ -#define CONVERT_NS_TO_S (~(1 << 28U)) - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get a chip major/minor revision. - * - * @param[out] rev - * A location to place the chip revision information. - ******************************************************************************/ -void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) -{ -#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ -#if defined(CMU_CLKEN0_SYSCFG) - CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; -#endif - uint32_t chiprev = SYSCFG_readChipRev(); -#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) - rev->partNumber = ((chiprev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chiprev & SYSCFG_CHIPREV_PARTNUMBER0); -#else - rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; -#endif - rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; - rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; -#else - uint8_t tmp; - - EFM_ASSERT(rev); - - /* CHIP FAMILY bit [5:2] */ - tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) - >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); - /* CHIP FAMILY bit [1:0] */ - tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) - >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); - rev->family = tmp; - - /* CHIP MAJOR bit [3:0] */ - rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) - >> _ROMTABLE_PID0_REVMAJOR_SHIFT); - - /* CHIP MINOR bit [7:4] */ - tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) - >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); - /* CHIP MINOR bit [3:0] */ - tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) - >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); - rev->minor = tmp; -#endif -} - -/***************************************************************************//** - * @brief - * Get a factory calibration value for a given peripheral register. - * - * @param[in] regAddress - * The peripheral calibration register address to get a calibration value for. If - * the calibration value is found, this register is updated with the - * calibration value. - * - * @return - * True if a calibration value exists, false otherwise. - ******************************************************************************/ -bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) -{ - SYSTEM_CalAddrVal_TypeDef * p, * end; - - uint32_t s_regAddress = (uint32_t)regAddress; - s_regAddress = s_regAddress & CONVERT_NS_TO_S; - -#if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) - p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; - end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; -#else - p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); - end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; -#endif - - for (; p < end; p++) { - if (p->address == 0) { - /* p->address == 0 marks the end of the table */ - return false; - } - if (p->address == s_regAddress) { - *regAddress = p->calValue; - return true; - } - } - /* Nothing found for regAddress. */ - return false; -} - -/***************************************************************************//** - * @brief - * Get family security capability. - * - * @note - * This function retrieves the family security capability based on the - * device number. The device number is one letter and 3 digits: - * DEVICENUMBER = (alpha-'A')*1000 + numeric. i.e. 0d = "A000"; 1123d = "B123". - * The security capabilities are represented by ::SYSTEM_SecurityCapability_TypeDef. - * - * @return - * Security capability of MCU. - ******************************************************************************/ -SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void) -{ - SYSTEM_SecurityCapability_TypeDef sc; - -#if (_SILICON_LABS_32B_SERIES == 0) - sc = securityCapabilityNA; -#elif (_SILICON_LABS_32B_SERIES == 1) - sc = securityCapabilityBasic; -#else - sc = securityCapabilityUnknown; -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - uint16_t mcuFeatureSetMajor; - uint16_t deviceNumber; - deviceNumber = SYSTEM_GetPartNumber(); - mcuFeatureSetMajor = 'A' + (deviceNumber / 1000); -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" - mcuFeatureSetMajor = 'C'; -#endif - - switch (mcuFeatureSetMajor) { - case 'A': - sc = securityCapabilitySE; - break; - - case 'B': - sc = securityCapabilityVault; - break; - - case 'C': - sc = securityCapabilityRoT; - break; - - default: - sc = securityCapabilityUnknown; - break; - } -#endif - - return sc; -} - -/***************************************************************************//** - * @brief - * Get the unique number for this device. - * - * @return - * Unique number for this device. - ******************************************************************************/ -uint64_t SYSTEM_GetUnique(void) -{ -#if defined (_DEVINFO_EUI64H_MASK) - uint32_t tmp = DEVINFO->EUI64L; - return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; -#elif defined(_DEVINFO_UNIQUEH_MASK) - uint32_t tmp = DEVINFO->UNIQUEL; - return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; -#else -#error (em_system.c): Location of device unique number is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the production revision for this part. - * - * @return - * Production revision for this part. - ******************************************************************************/ -uint8_t SYSTEM_GetProdRev(void) -{ -#if defined (_DEVINFO_PART_PROD_REV_MASK) - return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) - >> _DEVINFO_PART_PROD_REV_SHIFT); -#elif defined (_DEVINFO_INFO_PRODREV_MASK) - return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) - >> _DEVINFO_INFO_PRODREV_SHIFT); -#else -#error (em_system.c): Location of production revision is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the SRAM Base Address. - * - * @note - * This function is used to retrieve the base address of the SRAM. - * - * @return - * Base address SRAM (32-bit unsigned integer). - ******************************************************************************/ -uint32_t SYSTEM_GetSRAMBaseAddress(void) -{ - return (uint32_t)SRAM_BASE; -} - -/***************************************************************************//** - * @brief - * Get the SRAM size (in KB). - * - * @note - * This function retrieves SRAM size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use SRAM_SIZE instead. - * - * @return - * Size of internal SRAM (in KB). - ******************************************************************************/ -uint16_t SYSTEM_GetSRAMSize(void) -{ - uint16_t sizekb; - -#if defined(_EFM32_GECKO_FAMILY) - /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ - if (SYSTEM_GetProdRev() < 5) { - sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT; - } -#endif - sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT); - -#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) - /* Do not include EFR32xG1 RAMH. */ - sizekb--; -#endif - - return sizekb; -} - -/***************************************************************************//** - * @brief - * Get the flash size (in KB). - * - * @note - * This function retrieves flash size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use FLASH_SIZE instead. - * - * @return - * Size of internal flash (in KB). - ******************************************************************************/ -uint16_t SYSTEM_GetFlashSize(void) -{ -#if defined(_EFM32_GECKO_FAMILY) - /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ - if (SYSTEM_GetProdRev() < 5) { - return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) - >> _DEVINFO_MSIZE_SRAM_SHIFT; - } -#endif - return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) - >> _DEVINFO_MSIZE_FLASH_SHIFT); -} - -/***************************************************************************//** - * @brief - * Get the flash page size in bytes. - * - * @note - * This function retrieves flash page size by reading the chip device - * info structure. If your binary is made for one specific device only, - * use FLASH_PAGE_SIZE instead. - * - * @return - * Page size of internal flash in bytes. - ******************************************************************************/ -uint32_t SYSTEM_GetFlashPageSize(void) -{ - uint32_t tmp; - -#if defined(_SILICON_LABS_32B_SERIES_0) - -#if defined(_EFM32_GIANT_FAMILY) - if (SYSTEM_GetProdRev() < 18) { - /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ - return FLASH_PAGE_SIZE; - } -#elif defined(_EFM32_ZERO_FAMILY) - if (SYSTEM_GetProdRev() < 24) { - /* Early Zero devices have an incorrect DEVINFO flash page size */ - return FLASH_PAGE_SIZE; - } -#endif -#endif - -#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) - tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) - >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; -#elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) - tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) - >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; -#else -#error (em_system.c): Location of flash page size is not defined. -#endif - - return 1UL << ((tmp + 10UL) & 0x1FUL); -} - -/***************************************************************************//** - * @brief - * Get the MCU part number. - * - * @return - * The part number of MCU. - ******************************************************************************/ -uint16_t SYSTEM_GetPartNumber(void) -{ -#if defined(_DEVINFO_PART_DEVICENUM_MASK) - return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) - >> _DEVINFO_PART_DEVICENUM_SHIFT); -#elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) - return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) - >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); -#else -#error (em_system.c): Location of device part number is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the calibration temperature (in degrees Celsius). - * - * @return - * Calibration temperature in Celsius. - ******************************************************************************/ -uint8_t SYSTEM_GetCalibrationTemperature(void) -{ -#if defined(_DEVINFO_CAL_TEMP_MASK) - return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) - >> _DEVINFO_CAL_TEMP_SHIFT); -#elif defined(_DEVINFO_CALTEMP_TEMP_MASK) - return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) - >> _DEVINFO_CALTEMP_TEMP_SHIFT); -#else -#error (em_system.c): Location of calibration temperature is not defined. -#endif -} - -/***************************************************************************//** - * @brief - * Get the MCU family identifier. - * - * @note - * This function retrieves family ID by reading the chip's device info - * structure in flash memory. Users can retrieve family ID directly - * by reading DEVINFO->PART item and decode with mask and shift - * \#defines defined in \_devinfo.h (refer to code - * below for details). - * - * @return - * Family identifier of MCU. - ******************************************************************************/ -SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) -{ -#if defined(_DEVINFO_PART_FAMILY_MASK) - return (SYSTEM_PartFamily_TypeDef) - ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK - | _DEVINFO_PART_FAMILYNUM_MASK)))); -#elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) - return (SYSTEM_PartFamily_TypeDef) - ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) - >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); -#else - #error (em_system.h): Location of device family name is not defined. -#endif -} - -/** @} (end addtogroup system) */ +/***************************************************************************//** + * @file + * @brief System Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_system.h" +#include "sl_assert.h" +#include +#if defined(SYSCFG_PRESENT) +#include "em_syscfg.h" +#endif +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/* Bit mask used to extract the part number value without the new naming + * bitfield. */ +#define SYSCFG_CHIPREV_PARTNUMBER1 0xFE0 +#define SYSCFG_CHIPREV_PARTNUMBER0 0xF + +/* Bit mask to convert NON-SECURE to SECURE */ +#define CONVERT_NS_TO_S (~(1 << 28U)) + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Get a chip major/minor revision. + * + * @param[out] rev + * A location to place the chip revision information. + ******************************************************************************/ +void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev) +{ +#if defined(_SYSCFG_CHIPREV_FAMILY_MASK) || defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + /* On series-2 (and higher) the revision info is in the SYSCFG->CHIPREV register. */ +#if defined(CMU_CLKEN0_SYSCFG) + CMU->CLKEN0_SET = CMU_CLKEN0_SYSCFG; +#endif + uint32_t chiprev = SYSCFG_readChipRev(); +#if defined(_SYSCFG_CHIPREV_PARTNUMBER_MASK) + rev->partNumber = ((chiprev & SYSCFG_CHIPREV_PARTNUMBER1) >> 5) | (chiprev & SYSCFG_CHIPREV_PARTNUMBER0); +#else + rev->family = (chiprev & _SYSCFG_CHIPREV_FAMILY_MASK) >> _SYSCFG_CHIPREV_FAMILY_SHIFT; +#endif + rev->major = (chiprev & _SYSCFG_CHIPREV_MAJOR_MASK) >> _SYSCFG_CHIPREV_MAJOR_SHIFT; + rev->minor = (chiprev & _SYSCFG_CHIPREV_MINOR_MASK) >> _SYSCFG_CHIPREV_MINOR_SHIFT; +#else + uint8_t tmp; + + EFM_ASSERT(rev); + + /* CHIP FAMILY bit [5:2] */ + tmp = (uint8_t)(((ROMTABLE->PID1 & _ROMTABLE_PID1_FAMILYMSB_MASK) + >> _ROMTABLE_PID1_FAMILYMSB_SHIFT) << 2); + /* CHIP FAMILY bit [1:0] */ + tmp |= (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_FAMILYLSB_MASK) + >> _ROMTABLE_PID0_FAMILYLSB_SHIFT); + rev->family = tmp; + + /* CHIP MAJOR bit [3:0] */ + rev->major = (uint8_t)((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK) + >> _ROMTABLE_PID0_REVMAJOR_SHIFT); + + /* CHIP MINOR bit [7:4] */ + tmp = (uint8_t)(((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK) + >> _ROMTABLE_PID2_REVMINORMSB_SHIFT) << 4); + /* CHIP MINOR bit [3:0] */ + tmp |= (uint8_t)((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK) + >> _ROMTABLE_PID3_REVMINORLSB_SHIFT); + rev->minor = tmp; +#endif +} + +/***************************************************************************//** + * @brief + * Get a factory calibration value for a given peripheral register. + * + * @param[in] regAddress + * The peripheral calibration register address to get a calibration value for. If + * the calibration value is found, this register is updated with the + * calibration value. + * + * @return + * True if a calibration value exists, false otherwise. + ******************************************************************************/ +bool SYSTEM_GetCalibrationValue(volatile uint32_t *regAddress) +{ + SYSTEM_CalAddrVal_TypeDef * p, * end; + + uint32_t s_regAddress = (uint32_t)regAddress; + s_regAddress = s_regAddress & CONVERT_NS_TO_S; + +#if defined(MSC_FLASH_CHIPCONFIG_MEM_BASE) + p = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_BASE; + end = (SYSTEM_CalAddrVal_TypeDef *)MSC_FLASH_CHIPCONFIG_MEM_END; +#else + p = (SYSTEM_CalAddrVal_TypeDef *)(DEVINFO_BASE & 0xFFFFF000U); + end = (SYSTEM_CalAddrVal_TypeDef *)DEVINFO_BASE; +#endif + + for (; p < end; p++) { + if (p->address == 0) { + /* p->address == 0 marks the end of the table */ + return false; + } + if (p->address == s_regAddress) { + *regAddress = p->calValue; + return true; + } + } + /* Nothing found for regAddress. */ + return false; +} + +/***************************************************************************//** + * @brief + * Get family security capability. + * + * @note + * This function retrieves the family security capability based on the + * device number. The device number is one letter and 3 digits: + * DEVICENUMBER = (alpha-'A')*1000 + numeric. i.e. 0d = "A000"; 1123d = "B123". + * The security capabilities are represented by ::SYSTEM_SecurityCapability_TypeDef. + * + * @return + * Security capability of MCU. + ******************************************************************************/ +SYSTEM_SecurityCapability_TypeDef SYSTEM_GetSecurityCapability(void) +{ + SYSTEM_SecurityCapability_TypeDef sc; + +#if (_SILICON_LABS_32B_SERIES == 0) + sc = securityCapabilityNA; +#elif (_SILICON_LABS_32B_SERIES == 1) + sc = securityCapabilityBasic; +#else + sc = securityCapabilityUnknown; +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + uint16_t mcuFeatureSetMajor; + uint16_t deviceNumber; + deviceNumber = SYSTEM_GetPartNumber(); + mcuFeatureSetMajor = 'A' + (deviceNumber / 1000); +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + // override feature set since BRD4182A Rev A00 -> rev B02 are marked "A" + mcuFeatureSetMajor = 'C'; +#endif + + switch (mcuFeatureSetMajor) { + case 'A': + sc = securityCapabilitySE; + break; + + case 'B': + sc = securityCapabilityVault; + break; + + case 'C': + sc = securityCapabilityRoT; + break; + + default: + sc = securityCapabilityUnknown; + break; + } +#endif + + return sc; +} + +/***************************************************************************//** + * @brief + * Get the unique number for this device. + * + * @return + * Unique number for this device. + ******************************************************************************/ +uint64_t SYSTEM_GetUnique(void) +{ +#if defined (_DEVINFO_EUI64H_MASK) + uint32_t tmp = DEVINFO->EUI64L; + return (uint64_t)((uint64_t)DEVINFO->EUI64H << 32) | tmp; +#elif defined(_DEVINFO_UNIQUEH_MASK) + uint32_t tmp = DEVINFO->UNIQUEL; + return (uint64_t)((uint64_t)DEVINFO->UNIQUEH << 32) | tmp; +#else +#error (em_system.c): Location of device unique number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the production revision for this part. + * + * @return + * Production revision for this part. + ******************************************************************************/ +uint8_t SYSTEM_GetProdRev(void) +{ +#if defined (_DEVINFO_PART_PROD_REV_MASK) + return (uint8_t)((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) + >> _DEVINFO_PART_PROD_REV_SHIFT); +#elif defined (_DEVINFO_INFO_PRODREV_MASK) + return (uint8_t)((DEVINFO->INFO & _DEVINFO_INFO_PRODREV_MASK) + >> _DEVINFO_INFO_PRODREV_SHIFT); +#else +#error (em_system.c): Location of production revision is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the SRAM Base Address. + * + * @note + * This function is used to retrieve the base address of the SRAM. + * + * @return + * Base address SRAM (32-bit unsigned integer). + ******************************************************************************/ +uint32_t SYSTEM_GetSRAMBaseAddress(void) +{ + return (uint32_t)SRAM_BASE; +} + +/***************************************************************************//** + * @brief + * Get the SRAM size (in KB). + * + * @note + * This function retrieves SRAM size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use SRAM_SIZE instead. + * + * @return + * Size of internal SRAM (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetSRAMSize(void) +{ + uint16_t sizekb; + +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + sizekb = (DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT; + } +#endif + sizekb = (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT); + +#if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) && defined(_EFR_DEVICE) + /* Do not include EFR32xG1 RAMH. */ + sizekb--; +#endif + + return sizekb; +} + +/***************************************************************************//** + * @brief + * Get the flash size (in KB). + * + * @note + * This function retrieves flash size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_SIZE instead. + * + * @return + * Size of internal flash (in KB). + ******************************************************************************/ +uint16_t SYSTEM_GetFlashSize(void) +{ +#if defined(_EFM32_GECKO_FAMILY) + /* Early Gecko devices had a bug where SRAM and Flash size were swapped. */ + if (SYSTEM_GetProdRev() < 5) { + return (DEVINFO->MSIZE & _DEVINFO_MSIZE_SRAM_MASK) + >> _DEVINFO_MSIZE_SRAM_SHIFT; + } +#endif + return (uint16_t)((DEVINFO->MSIZE & _DEVINFO_MSIZE_FLASH_MASK) + >> _DEVINFO_MSIZE_FLASH_SHIFT); +} + +/***************************************************************************//** + * @brief + * Get the flash page size in bytes. + * + * @note + * This function retrieves flash page size by reading the chip device + * info structure. If your binary is made for one specific device only, + * use FLASH_PAGE_SIZE instead. + * + * @return + * Page size of internal flash in bytes. + ******************************************************************************/ +uint32_t SYSTEM_GetFlashPageSize(void) +{ + uint32_t tmp; + +#if defined(_SILICON_LABS_32B_SERIES_0) + +#if defined(_EFM32_GIANT_FAMILY) + if (SYSTEM_GetProdRev() < 18) { + /* Early Giant/Leopard devices did not have MEMINFO in DEVINFO. */ + return FLASH_PAGE_SIZE; + } +#elif defined(_EFM32_ZERO_FAMILY) + if (SYSTEM_GetProdRev() < 24) { + /* Early Zero devices have an incorrect DEVINFO flash page size */ + return FLASH_PAGE_SIZE; + } +#endif +#endif + +#if defined(_DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASHPAGESIZE_MASK) + >> _DEVINFO_MEMINFO_FLASHPAGESIZE_SHIFT; +#elif defined(_DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + tmp = (DEVINFO->MEMINFO & _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK) + >> _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT; +#else +#error (em_system.c): Location of flash page size is not defined. +#endif + + return 1UL << ((tmp + 10UL) & 0x1FUL); +} + +/***************************************************************************//** + * @brief + * Get the MCU part number. + * + * @return + * The part number of MCU. + ******************************************************************************/ +uint16_t SYSTEM_GetPartNumber(void) +{ +#if defined(_DEVINFO_PART_DEVICENUM_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICENUM_MASK) + >> _DEVINFO_PART_DEVICENUM_SHIFT); +#elif defined(_DEVINFO_PART_DEVICE_NUMBER_MASK) + return (uint16_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) + >> _DEVINFO_PART_DEVICE_NUMBER_SHIFT); +#else +#error (em_system.c): Location of device part number is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the calibration temperature (in degrees Celsius). + * + * @return + * Calibration temperature in Celsius. + ******************************************************************************/ +uint8_t SYSTEM_GetCalibrationTemperature(void) +{ +#if defined(_DEVINFO_CAL_TEMP_MASK) + return (uint8_t)((DEVINFO->CAL & _DEVINFO_CAL_TEMP_MASK) + >> _DEVINFO_CAL_TEMP_SHIFT); +#elif defined(_DEVINFO_CALTEMP_TEMP_MASK) + return (uint8_t)((DEVINFO->CALTEMP & _DEVINFO_CALTEMP_TEMP_MASK) + >> _DEVINFO_CALTEMP_TEMP_SHIFT); +#else +#error (em_system.c): Location of calibration temperature is not defined. +#endif +} + +/***************************************************************************//** + * @brief + * Get the MCU family identifier. + * + * @note + * This function retrieves family ID by reading the chip's device info + * structure in flash memory. Users can retrieve family ID directly + * by reading DEVINFO->PART item and decode with mask and shift + * \#defines defined in \_devinfo.h (refer to code + * below for details). + * + * @return + * Family identifier of MCU. + ******************************************************************************/ +SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void) +{ +#if defined(_DEVINFO_PART_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & (_DEVINFO_PART_FAMILY_MASK + | _DEVINFO_PART_FAMILYNUM_MASK)))); +#elif defined(_DEVINFO_PART_DEVICE_FAMILY_MASK) + return (SYSTEM_PartFamily_TypeDef) + ((uint32_t)((DEVINFO->PART & _DEVINFO_PART_DEVICE_FAMILY_MASK) + >> _DEVINFO_PART_DEVICE_FAMILY_SHIFT)); +#else + #error (em_system.h): Location of device family name is not defined. +#endif +} + +/** @} (end addtogroup system) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c index c542a8b..033e64a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_timer.c @@ -1,520 +1,520 @@ -/***************************************************************************//** - * @file - * @brief Timer/counter (TIMER) Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_timer.h" -#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) - -#include "sl_assert.h" - -/***************************************************************************//** - * @addtogroup timer TIMER - Timer/Counter - * @brief Timer/Counter (TIMER) Peripheral API - * @details - * The timer module consists of three main parts: - * @li General timer configuration and enable control. - * @li Compare/capture control. - * @li Dead time insertion control (may not be available for all timers). - * @{ - ******************************************************************************/ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -#if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) - -/** Map TIMER reference to index of device. */ -#if defined(TIMER9) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : (timer) == TIMER5 ? 5 \ - : (timer) == TIMER6 ? 6 \ - : (timer) == TIMER7 ? 7 \ - : (timer) == TIMER8 ? 8 \ - : (timer) == TIMER9 ? 9 \ - : -1) -#elif defined(TIMER7) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : (timer) == TIMER5 ? 5 \ - : (timer) == TIMER6 ? 6 \ - : (timer) == TIMER7 ? 7 \ - : -1) -#elif defined(TIMER4) -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : (timer) == TIMER4 ? 4 \ - : -1) -#else -#define TIMER_DEVICE_ID(timer) ( \ - (timer) == TIMER0 ? 0 \ - : (timer) == TIMER1 ? 1 \ - : (timer) == TIMER2 ? 2 \ - : (timer) == TIMER3 ? 3 \ - : -1) -#endif - -#define TIMER_INPUT_CHANNEL_DTI 3UL -#define TIMER_INPUT_CHANNEL_DTIFS1 4UL -#define TIMER_INPUT_CHANNEL_DTIFS2 5UL - -/** - * TIMER PRS registers are moved into the PRS register space on series 2 devices. - * The PRS Consumer registers for a timer consist of 6 registers. - * - * [0] - CC0 PRS Consumer - * [1] - CC1 PRS Consumer - * [2] - CC2 PRS Consumer - * [3] - DTI PRS Consumer - * [4] - DTIFS1 PRS Consumer - * [5] - DTIFS2 PRS Consumer - */ -typedef struct { - __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ -} PRS_TIMERn_Consumer_TypeDef; - -typedef struct { - PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; -} PRS_TIMERn_TypeDef; - -/** - * @brief Configure a timer capture/compare channel to use a PRS channel as input. - * - * @param[in] timer - * - * @param[in] cc - * Timer input channel. Valid input is 0-5. - * 0 - CC0 - * 1 - CC1 - * 2 - CC2 - * 3 - DTI - * 4 - DTIFS1 - * 5 - DTIFS2 - * - * @param[in] prsCh - * PRS channel number. - * - * @param[in] async - * true for asynchronous PRS channel, false for synchronous PRS channel. - */ -static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) -{ - int i = TIMER_DEVICE_ID(timer); - volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; - EFM_ASSERT(i >= 0); - - if (i >= 0) { - if (async) { - base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; - } else { - base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; - } - } -} -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Initialize TIMER. - * - * @details - * Notice that the counter top must be configured separately with, for instance - * TIMER_TopSet(). In addition, compare/capture and dead-time insertion - * initialization must be initialized separately if used, which should probably - * be done prior to using this function if configuring the TIMER to - * start when initialization is completed. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] init - * A pointer to the TIMER initialization structure. - ******************************************************************************/ -void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - uint32_t ctrlRegVal = 0; - -#if defined (_TIMER_CFG_PRESC_SHIFT) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) - | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) - | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) - | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) - | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) - | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) - | (init->oneShot ? TIMER_CFG_OSMEN : 0) - | (init->sync ? TIMER_CFG_SYNC : 0) - | (init->disSyncOut ? TIMER_CFG_DISSYNCOUT : 0) - | (init->ati ? TIMER_CFG_ATI : 0) - | (init->rssCoist ? TIMER_CFG_RSSCOIST : 0); - timer->EN_SET = TIMER_EN_EN; -#endif - - /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ - if (!(init->enable)) { - timer->CMD = TIMER_CMD_STOP; - } - - /* Reset the counter. */ - timer->CNT = _TIMER_CNT_RESETVALUE; - -#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) - ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) - | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) - | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) - | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) - | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) - | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) - | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) - | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) - | (init->oneShot ? TIMER_CTRL_OSMEN : 0) -#if defined(TIMER_CTRL_DISSYNCOUT) - | (init->disSyncOut ? TIMER_CTRL_DISSYNCOUT : 0) -#endif - | (init->sync ? TIMER_CTRL_SYNC : 0); - -#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) && defined(TIMER_CTRL_RSSCOIST) - ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) - | (init->ati ? TIMER_CTRL_ATI : 0) - | (init->rssCoist ? TIMER_CTRL_RSSCOIST : 0); -#endif - -#else - ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) - | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) - | (init->count2x ? TIMER_CTRL_X2CNT : 0); -#endif - - timer->CTRL = ctrlRegVal; - - /* Start the timer if specified to be enabled (doesn't hurt if already started). */ - if (init->enable) { - timer->CMD = TIMER_CMD_START; - } -} - -/***************************************************************************//** - * @brief - * Initialize the TIMER compare/capture channel. - * - * @details - * Notice that if operating the channel in compare mode, the CCV and CCVB register - * must be set separately, as required. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] ch - * A compare/capture channel to initialize for. - * - * @param[in] init - * A pointer to the TIMER initialization structure. - ******************************************************************************/ -void TIMER_InitCC(TIMER_TypeDef *timer, - unsigned int ch, - const TIMER_InitCC_TypeDef *init) -{ - EFM_ASSERT(TIMER_REF_VALID(timer)); - EFM_ASSERT(TIMER_REF_CH_VALIDATE(timer, ch)); - -#if defined (_TIMER_CC_CFG_MASK) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CC[ch].CFG = - ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) - | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) - | (init->coist ? TIMER_CC_CFG_COIST : 0) - | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); - - if (init->prsInput) { - timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; - bool async = (init->prsInputType != timerPrsInputSync); - timerPrsConfig(timer, ch, init->prsSel, async); - } else { - timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; - } - timer->EN_SET = TIMER_EN_EN; - - timer->CC[ch].CTRL = - ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) - | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) - | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) - | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) - | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) - | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); -#else - timer->CC[ch].CTRL = - ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) - | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) - | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) - | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) - | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) - | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) - | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) - | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) - | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) - | (init->coist ? TIMER_CC_CTRL_COIST : 0) - | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) -#if defined(_TIMER_CC_CTRL_PRSCONF_MASK) - | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) -#endif - ; -#endif -} - -#if defined(_TIMER_DTCTRL_MASK) -/***************************************************************************//** - * @brief - * Initialize the TIMER DTI unit. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - * - * @param[in] init - * A pointer to the TIMER DTI initialization structure. - ******************************************************************************/ -void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) -{ - EFM_ASSERT(TIMER_SupportsDTI(timer)); - - /* Make sure the DTI unit is disabled while initializing. */ - TIMER_EnableDTI(timer, false); - -#if defined (_TIMER_DTCFG_MASK) - TIMER_SyncWait(timer); - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) - | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); - if (init->enablePrsSource) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); - } - - timer->DTTIMECFG = - ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) - | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) - | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); - - timer->DTFCFG = - (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) - | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) - | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) - | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) - | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); - - if (init->enableFaultSourcePrsSel0) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); - } - if (init->enableFaultSourcePrsSel1) { - timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); - } - - timer->EN_SET = TIMER_EN_EN; -#endif - -#if defined(TIMER_DTCTRL_DTDAS) - /* Set up the DTCTRL register. - The enable bit will be set at the end of the function if specified. */ - timer->DTCTRL = - (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) - | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) - | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) - | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) - | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); -#endif - -#if defined (TIMER_DTCFG_DTDAS) - timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) - | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); -#endif - -#if defined (_TIMER_DTTIME_DTPRESC_SHIFT) - /* Set up the DTTIME register. */ - timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) - | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) - | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); -#endif - -#if defined (TIMER_DTFC_DTLOCKUPFEN) - /* Set up the DTFC register. */ - timer->DTFC = - (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) - | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) - | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) - | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) - | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) - | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) - | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); -#endif - - /* Set up the DTOGEN register. */ - timer->DTOGEN = init->outputsEnableMask; - - /* Clear any previous DTI faults. */ - TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); - - /* Enable/disable before returning. */ - TIMER_EnableDTI(timer, init->enable); -} -#endif - -/***************************************************************************//** - * @brief - * Reset the TIMER to the same state that it was in after a hardware reset. - * - * @note - * The ROUTE register is NOT reset by this function to allow for - * a centralized setup of this feature. - * - * @param[in] timer - * A pointer to the TIMER peripheral register block. - ******************************************************************************/ -void TIMER_Reset(TIMER_TypeDef *timer) -{ - int i; - - EFM_ASSERT(TIMER_REF_VALID(timer)); - -#if defined(TIMER_EN_EN) - timer->EN_SET = TIMER_EN_EN; -#endif - - /* Make sure disabled first, before resetting other registers. */ - timer->CMD = TIMER_CMD_STOP; - - timer->CTRL = _TIMER_CTRL_RESETVALUE; - timer->IEN = _TIMER_IEN_RESETVALUE; -#if defined (TIMER_HAS_SET_CLEAR) - timer->IF_CLR = _TIMER_IF_MASK; -#else - timer->IFC = _TIMER_IFC_MASK; -#endif - timer->TOPB = _TIMER_TOPB_RESETVALUE; - /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ - timer->TOP = _TIMER_TOP_RESETVALUE; - timer->CNT = _TIMER_CNT_RESETVALUE; - /* Do not reset the route register, setting should be done independently. */ - /* Note: The ROUTE register may be locked by the DTLOCK register. */ - - for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { - timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; -#if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) - timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; - timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; -#endif -#if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ - && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) - timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; - timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; -#endif - } - - /* Reset dead time insertion module, which has no effect on timers without DTI. */ -#if defined(_TIMER_DTCFG_MASK) - timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; - timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; - timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; - timer->DTFAULTC = _TIMER_DTFAULTC_MASK; -#elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) - /* Unlock DTI registers first if locked. */ - timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; - timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; - timer->DTTIME = _TIMER_DTTIME_RESETVALUE; - timer->DTFC = _TIMER_DTFC_RESETVALUE; - timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; - timer->DTFAULTC = _TIMER_DTFAULTC_MASK; -#endif - -#if defined(_TIMER_CFG_MASK) - TIMER_SyncWait(timer); - /* CFG registers must be reset after the timer is disabled */ - timer->EN_CLR = TIMER_EN_EN; -#if defined(_TIMER_EN_DISABLING_MASK) - while (timer->EN & _TIMER_EN_DISABLING_MASK) { - } -#endif - timer->CFG = _TIMER_CFG_RESETVALUE; - for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { - timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; - } - timer->DTCFG = _TIMER_DTCFG_RESETVALUE; - timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; - timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; -#endif -} - -#if defined(TIMER_STATUS_SYNCBUSY) -/** - * @brief Wait for pending synchronization to finish - * - * @param[in] timer - */ -void TIMER_SyncWait(TIMER_TypeDef * timer) -{ - while (((timer->EN & TIMER_EN_EN) != 0U) - && ((timer->STATUS & TIMER_STATUS_SYNCBUSY) != 0U)) { - /* Wait for synchronization to complete */ - } -} -#endif - -/** @} (end addtogroup timer) */ -#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Timer/counter (TIMER) Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_timer.h" +#if defined(TIMER_COUNT) && (TIMER_COUNT > 0) + +#include "sl_assert.h" + +/***************************************************************************//** + * @addtogroup timer TIMER - Timer/Counter + * @brief Timer/Counter (TIMER) Peripheral API + * @details + * The timer module consists of three main parts: + * @li General timer configuration and enable control. + * @li Compare/capture control. + * @li Dead time insertion control (may not be available for all timers). + * @{ + ******************************************************************************/ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ +#if defined(_PRS_CONSUMER_TIMER0_CC0_MASK) + +/** Map TIMER reference to index of device. */ +#if defined(TIMER9) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : (timer) == TIMER8 ? 8 \ + : (timer) == TIMER9 ? 9 \ + : -1) +#elif defined(TIMER7) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : (timer) == TIMER5 ? 5 \ + : (timer) == TIMER6 ? 6 \ + : (timer) == TIMER7 ? 7 \ + : -1) +#elif defined(TIMER4) +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : (timer) == TIMER4 ? 4 \ + : -1) +#else +#define TIMER_DEVICE_ID(timer) ( \ + (timer) == TIMER0 ? 0 \ + : (timer) == TIMER1 ? 1 \ + : (timer) == TIMER2 ? 2 \ + : (timer) == TIMER3 ? 3 \ + : -1) +#endif + +#define TIMER_INPUT_CHANNEL_DTI 3UL +#define TIMER_INPUT_CHANNEL_DTIFS1 4UL +#define TIMER_INPUT_CHANNEL_DTIFS2 5UL + +/** + * TIMER PRS registers are moved into the PRS register space on series 2 devices. + * The PRS Consumer registers for a timer consist of 6 registers. + * + * [0] - CC0 PRS Consumer + * [1] - CC1 PRS Consumer + * [2] - CC2 PRS Consumer + * [3] - DTI PRS Consumer + * [4] - DTIFS1 PRS Consumer + * [5] - DTIFS2 PRS Consumer + */ +typedef struct { + __IOM uint32_t CONSUMER_CH[6]; /**< TIMER PRS consumers. */ +} PRS_TIMERn_Consumer_TypeDef; + +typedef struct { + PRS_TIMERn_Consumer_TypeDef TIMER_CONSUMER[TIMER_COUNT]; +} PRS_TIMERn_TypeDef; + +/** + * @brief Configure a timer capture/compare channel to use a PRS channel as input. + * + * @param[in] timer + * + * @param[in] cc + * Timer input channel. Valid input is 0-5. + * 0 - CC0 + * 1 - CC1 + * 2 - CC2 + * 3 - DTI + * 4 - DTIFS1 + * 5 - DTIFS2 + * + * @param[in] prsCh + * PRS channel number. + * + * @param[in] async + * true for asynchronous PRS channel, false for synchronous PRS channel. + */ +static void timerPrsConfig(TIMER_TypeDef * timer, unsigned int cc, unsigned int prsCh, bool async) +{ + int i = TIMER_DEVICE_ID(timer); + volatile PRS_TIMERn_TypeDef * base = (PRS_TIMERn_TypeDef *) &PRS->CONSUMER_TIMER0_CC0; + EFM_ASSERT(i >= 0); + + if (i >= 0) { + if (async) { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_PRSSEL_SHIFT; + } else { + base->TIMER_CONSUMER[i].CONSUMER_CH[cc] = prsCh << _PRS_CONSUMER_TIMER0_CC0_SPRSSEL_SHIFT; + } + } +} +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Initialize TIMER. + * + * @details + * Notice that the counter top must be configured separately with, for instance + * TIMER_TopSet(). In addition, compare/capture and dead-time insertion + * initialization must be initialized separately if used, which should probably + * be done prior to using this function if configuring the TIMER to + * start when initialization is completed. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + uint32_t ctrlRegVal = 0; + +#if defined (_TIMER_CFG_PRESC_SHIFT) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = ((uint32_t)init->prescale << _TIMER_CFG_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CFG_CLKSEL_SHIFT) + | ((uint32_t)init->mode << _TIMER_CFG_MODE_SHIFT) + | (init->debugRun ? TIMER_CFG_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CFG_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CFG_QDM_X4 : 0) + | (init->oneShot ? TIMER_CFG_OSMEN : 0) + | (init->sync ? TIMER_CFG_SYNC : 0) + | (init->disSyncOut ? TIMER_CFG_DISSYNCOUT : 0) + | (init->ati ? TIMER_CFG_ATI : 0) + | (init->rssCoist ? TIMER_CFG_RSSCOIST : 0); + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Stop the timer if specified to be disabled (doesn't hurt if already stopped). */ + if (!(init->enable)) { + timer->CMD = TIMER_CMD_STOP; + } + + /* Reset the counter. */ + timer->CNT = _TIMER_CNT_RESETVALUE; + +#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) + ctrlRegVal = ((uint32_t)init->prescale << _TIMER_CTRL_PRESC_SHIFT) + | ((uint32_t)init->clkSel << _TIMER_CTRL_CLKSEL_SHIFT) + | ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CTRL_MODE_SHIFT) + | (init->debugRun ? TIMER_CTRL_DEBUGRUN : 0) + | (init->dmaClrAct ? TIMER_CTRL_DMACLRACT : 0) + | (init->quadModeX4 ? TIMER_CTRL_QDM_X4 : 0) + | (init->oneShot ? TIMER_CTRL_OSMEN : 0) +#if defined(TIMER_CTRL_DISSYNCOUT) + | (init->disSyncOut ? TIMER_CTRL_DISSYNCOUT : 0) +#endif + | (init->sync ? TIMER_CTRL_SYNC : 0); + +#if defined(TIMER_CTRL_X2CNT) && defined(TIMER_CTRL_ATI) && defined(TIMER_CTRL_RSSCOIST) + ctrlRegVal |= (init->count2x ? TIMER_CTRL_X2CNT : 0) + | (init->ati ? TIMER_CTRL_ATI : 0) + | (init->rssCoist ? TIMER_CTRL_RSSCOIST : 0); +#endif + +#else + ctrlRegVal = ((uint32_t)init->fallAction << _TIMER_CTRL_FALLA_SHIFT) + | ((uint32_t)init->riseAction << _TIMER_CTRL_RISEA_SHIFT) + | (init->count2x ? TIMER_CTRL_X2CNT : 0); +#endif + + timer->CTRL = ctrlRegVal; + + /* Start the timer if specified to be enabled (doesn't hurt if already started). */ + if (init->enable) { + timer->CMD = TIMER_CMD_START; + } +} + +/***************************************************************************//** + * @brief + * Initialize the TIMER compare/capture channel. + * + * @details + * Notice that if operating the channel in compare mode, the CCV and CCVB register + * must be set separately, as required. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] ch + * A compare/capture channel to initialize for. + * + * @param[in] init + * A pointer to the TIMER initialization structure. + ******************************************************************************/ +void TIMER_InitCC(TIMER_TypeDef *timer, + unsigned int ch, + const TIMER_InitCC_TypeDef *init) +{ + EFM_ASSERT(TIMER_REF_VALID(timer)); + EFM_ASSERT(TIMER_REF_CH_VALIDATE(timer, ch)); + +#if defined (_TIMER_CC_CFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CC[ch].CFG = + ((uint32_t)init->mode << _TIMER_CC_CFG_MODE_SHIFT) + | (init->filter ? TIMER_CC_CFG_FILT_ENABLE : 0) + | (init->coist ? TIMER_CC_CFG_COIST : 0) + | ((uint32_t)init->prsOutput << _TIMER_CC_CFG_PRSCONF_SHIFT); + + if (init->prsInput) { + timer->CC[ch].CFG |= (uint32_t)init->prsInputType << _TIMER_CC_CFG_INSEL_SHIFT; + bool async = (init->prsInputType != timerPrsInputSync); + timerPrsConfig(timer, ch, init->prsSel, async); + } else { + timer->CC[ch].CFG |= TIMER_CC_CFG_INSEL_PIN; + } + timer->EN_SET = TIMER_EN_EN; + + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0); +#else + timer->CC[ch].CTRL = + ((uint32_t)init->eventCtrl << _TIMER_CC_CTRL_ICEVCTRL_SHIFT) + | ((uint32_t)init->edge << _TIMER_CC_CTRL_ICEDGE_SHIFT) + | ((uint32_t)init->prsSel << _TIMER_CC_CTRL_PRSSEL_SHIFT) + | ((uint32_t)init->cufoa << _TIMER_CC_CTRL_CUFOA_SHIFT) + | ((uint32_t)init->cofoa << _TIMER_CC_CTRL_COFOA_SHIFT) + | ((uint32_t)init->cmoa << _TIMER_CC_CTRL_CMOA_SHIFT) + | ((uint32_t)init->mode << _TIMER_CC_CTRL_MODE_SHIFT) + | (init->filter ? TIMER_CC_CTRL_FILT_ENABLE : 0) + | (init->prsInput ? TIMER_CC_CTRL_INSEL_PRS : 0) + | (init->coist ? TIMER_CC_CTRL_COIST : 0) + | (init->outInvert ? TIMER_CC_CTRL_OUTINV : 0) +#if defined(_TIMER_CC_CTRL_PRSCONF_MASK) + | ((uint32_t)init->prsOutput << _TIMER_CC_CTRL_PRSCONF_SHIFT) +#endif + ; +#endif +} + +#if defined(_TIMER_DTCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize the TIMER DTI unit. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + * + * @param[in] init + * A pointer to the TIMER DTI initialization structure. + ******************************************************************************/ +void TIMER_InitDTI(TIMER_TypeDef *timer, const TIMER_InitDTI_TypeDef *init) +{ + EFM_ASSERT(TIMER_SupportsDTI(timer)); + + /* Make sure the DTI unit is disabled while initializing. */ + TIMER_EnableDTI(timer, false); + +#if defined (_TIMER_DTCFG_MASK) + TIMER_SyncWait(timer); + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->DTCFG = (init->autoRestart ? TIMER_DTCFG_DTDAS : 0) + | (init->enablePrsSource ? TIMER_DTCFG_DTPRSEN : 0); + if (init->enablePrsSource) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTI, init->prsSel, true); + } + + timer->DTTIMECFG = + ((uint32_t)init->prescale << _TIMER_DTTIMECFG_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIMECFG_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIMECFG_DTFALLT_SHIFT); + + timer->DTFCFG = + (init->enableFaultSourceCoreLockup ? TIMER_DTFCFG_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFCFG_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFCFG_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFCFG_DTPRS1FEN : 0) + | ((uint32_t)(init->faultAction) << _TIMER_DTFCFG_DTFA_SHIFT); + + if (init->enableFaultSourcePrsSel0) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS1, init->faultSourcePrsSel0, true); + } + if (init->enableFaultSourcePrsSel1) { + timerPrsConfig(timer, TIMER_INPUT_CHANNEL_DTIFS2, init->faultSourcePrsSel1, true); + } + + timer->EN_SET = TIMER_EN_EN; +#endif + +#if defined(TIMER_DTCTRL_DTDAS) + /* Set up the DTCTRL register. + The enable bit will be set at the end of the function if specified. */ + timer->DTCTRL = + (init->autoRestart ? TIMER_DTCTRL_DTDAS : 0) + | (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0) + | (init->enablePrsSource ? TIMER_DTCTRL_DTPRSEN : 0) + | ((uint32_t)(init->prsSel) << _TIMER_DTCTRL_DTPRSSEL_SHIFT); +#endif + +#if defined (TIMER_DTCFG_DTDAS) + timer->DTCTRL = (init->activeLowOut ? TIMER_DTCTRL_DTIPOL : 0) + | (init->invertComplementaryOut ? TIMER_DTCTRL_DTCINV : 0); +#endif + +#if defined (_TIMER_DTTIME_DTPRESC_SHIFT) + /* Set up the DTTIME register. */ + timer->DTTIME = ((uint32_t)init->prescale << _TIMER_DTTIME_DTPRESC_SHIFT) + | ((uint32_t)init->riseTime << _TIMER_DTTIME_DTRISET_SHIFT) + | ((uint32_t)init->fallTime << _TIMER_DTTIME_DTFALLT_SHIFT); +#endif + +#if defined (TIMER_DTFC_DTLOCKUPFEN) + /* Set up the DTFC register. */ + timer->DTFC = + (init->enableFaultSourceCoreLockup ? TIMER_DTFC_DTLOCKUPFEN : 0) + | (init->enableFaultSourceDebugger ? TIMER_DTFC_DTDBGFEN : 0) + | (init->enableFaultSourcePrsSel0 ? TIMER_DTFC_DTPRS0FEN : 0) + | (init->enableFaultSourcePrsSel1 ? TIMER_DTFC_DTPRS1FEN : 0) + | ((uint32_t)init->faultAction << _TIMER_DTFC_DTFA_SHIFT) + | ((uint32_t)init->faultSourcePrsSel0 << _TIMER_DTFC_DTPRS0FSEL_SHIFT) + | ((uint32_t)init->faultSourcePrsSel1 << _TIMER_DTFC_DTPRS1FSEL_SHIFT); +#endif + + /* Set up the DTOGEN register. */ + timer->DTOGEN = init->outputsEnableMask; + + /* Clear any previous DTI faults. */ + TIMER_ClearDTIFault(timer, TIMER_GetDTIFault(timer)); + + /* Enable/disable before returning. */ + TIMER_EnableDTI(timer, init->enable); +} +#endif + +/***************************************************************************//** + * @brief + * Reset the TIMER to the same state that it was in after a hardware reset. + * + * @note + * The ROUTE register is NOT reset by this function to allow for + * a centralized setup of this feature. + * + * @param[in] timer + * A pointer to the TIMER peripheral register block. + ******************************************************************************/ +void TIMER_Reset(TIMER_TypeDef *timer) +{ + int i; + + EFM_ASSERT(TIMER_REF_VALID(timer)); + +#if defined(TIMER_EN_EN) + timer->EN_SET = TIMER_EN_EN; +#endif + + /* Make sure disabled first, before resetting other registers. */ + timer->CMD = TIMER_CMD_STOP; + + timer->CTRL = _TIMER_CTRL_RESETVALUE; + timer->IEN = _TIMER_IEN_RESETVALUE; +#if defined (TIMER_HAS_SET_CLEAR) + timer->IF_CLR = _TIMER_IF_MASK; +#else + timer->IFC = _TIMER_IFC_MASK; +#endif + timer->TOPB = _TIMER_TOPB_RESETVALUE; + /* Write TOP after TOPB to invalidate TOPB (clear TIMER_STATUS_TOPBV). */ + timer->TOP = _TIMER_TOP_RESETVALUE; + timer->CNT = _TIMER_CNT_RESETVALUE; + /* Do not reset the route register, setting should be done independently. */ + /* Note: The ROUTE register may be locked by the DTLOCK register. */ + + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CTRL = _TIMER_CC_CTRL_RESETVALUE; +#if defined (_TIMER_CC_CCV_RESETVALUE) && defined (_TIMER_CC_CCVB_RESETVALUE) + timer->CC[i].CCV = _TIMER_CC_CCV_RESETVALUE; + timer->CC[i].CCVB = _TIMER_CC_CCVB_RESETVALUE; +#endif +#if defined (_TIMER_CC_OC_RESETVALUE) && defined (_TIMER_CC_OCB_RESETVALUE) \ + && defined (_TIMER_CC_ICF_RESETVALUE) && defined (_TIMER_CC_ICOF_RESETVALUE) + timer->CC[i].OC = _TIMER_CC_OC_RESETVALUE; + timer->CC[i].OCB = _TIMER_CC_OCB_RESETVALUE; +#endif + } + + /* Reset dead time insertion module, which has no effect on timers without DTI. */ +#if defined(_TIMER_DTCFG_MASK) + timer->DTLOCK = TIMER_DTLOCK_DTILOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#elif defined(TIMER_DTLOCK_LOCKKEY_UNLOCK) + /* Unlock DTI registers first if locked. */ + timer->DTLOCK = TIMER_DTLOCK_LOCKKEY_UNLOCK; + timer->DTCTRL = _TIMER_DTCTRL_RESETVALUE; + timer->DTTIME = _TIMER_DTTIME_RESETVALUE; + timer->DTFC = _TIMER_DTFC_RESETVALUE; + timer->DTOGEN = _TIMER_DTOGEN_RESETVALUE; + timer->DTFAULTC = _TIMER_DTFAULTC_MASK; +#endif + +#if defined(_TIMER_CFG_MASK) + TIMER_SyncWait(timer); + /* CFG registers must be reset after the timer is disabled */ + timer->EN_CLR = TIMER_EN_EN; +#if defined(_TIMER_EN_DISABLING_MASK) + while (timer->EN & _TIMER_EN_DISABLING_MASK) { + } +#endif + timer->CFG = _TIMER_CFG_RESETVALUE; + for (i = 0; TIMER_REF_CH_VALIDATE(timer, i); i++) { + timer->CC[i].CFG = _TIMER_CC_CFG_RESETVALUE; + } + timer->DTCFG = _TIMER_DTCFG_RESETVALUE; + timer->DTFCFG = _TIMER_DTFCFG_RESETVALUE; + timer->DTTIMECFG = _TIMER_DTTIMECFG_RESETVALUE; +#endif +} + +#if defined(TIMER_STATUS_SYNCBUSY) +/** + * @brief Wait for pending synchronization to finish + * + * @param[in] timer + */ +void TIMER_SyncWait(TIMER_TypeDef * timer) +{ + while (((timer->EN & TIMER_EN_EN) != 0U) + && ((timer->STATUS & TIMER_STATUS_SYNCBUSY) != 0U)) { + /* Wait for synchronization to complete */ + } +} +#endif + +/** @} (end addtogroup timer) */ +#endif /* defined(TIMER_COUNT) && (TIMER_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c index 0b8cef0..a76baad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_usart.c @@ -1,1444 +1,1444 @@ -/***************************************************************************//** - * @file - * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) - * Peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_usart.h" -#if defined(USART_COUNT) && (USART_COUNT > 0) - -#include "em_cmu.h" -#include "em_bus.h" -#include "sl_assert.h" -#if defined(USART_CTRLX_CTSEN) -#include "em_gpio.h" -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ - -/** Validation of USART register block pointer reference for assert statements. */ -#if (USART_COUNT == 1) && defined(USART0) -#define USART_REF_VALID(ref) ((ref) == USART0) - -#elif (USART_COUNT == 1) && defined(USART1) -#define USART_REF_VALID(ref) ((ref) == USART1) - -#elif (USART_COUNT == 2) && defined(USART2) -#define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) - -#elif (USART_COUNT == 2) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - -#elif (USART_COUNT == 3) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2)) -#elif (USART_COUNT == 4) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3)) -#elif (USART_COUNT == 5) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3) \ - || ((ref) == USART4)) -#elif (USART_COUNT == 6) -#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ - || ((ref) == USART2) || ((ref) == USART3) \ - || ((ref) == USART4) || ((ref) == USART5)) -#else -#error "Undefined number of USARTs." -#endif - -#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) - #if (USARTRF_COUNT == 1) && defined(USARTRF0) - #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) - #elif (USARTRF_COUNT == 1) && defined(USARTRF1) - #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) - #else - #define USARTRF_REF_VALID(ref) (0) - #endif -#else - #define USARTRF_REF_VALID(ref) (0) -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) -#elif defined(_SILICON_LABS_32B_SERIES_1) - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) -// If GG11 or TG11 - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) - #elif defined(USART3) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) - #elif defined(USART2) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) - #else - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - #if defined(_EZR32_HAPPY_FAMILY) - #define USART_IRDA_VALID(ref) ((ref) == USART0) - #elif defined(_EFM32_HAPPY_FAMILY) - #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #elif defined(USART0) - #define USART_IRDA_VALID(ref) ((ref) == USART0) - #elif (USART_COUNT == 1) && defined(USART1) - #define USART_IRDA_VALID(ref) ((ref) == USART1) - #elif defined(USARTRF0) - #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) - #else - #define USART_IRDA_VALID(ref) (0) - #endif -#endif - -#if (_SILICON_LABS_32B_SERIES == 2) - #define USART_I2S_VALID(ref) USART_REF_VALID(ref) -#elif defined(_SILICON_LABS_32B_SERIES_1) - #if defined(USART4) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) - #elif defined(USART3) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) - #else - #define USART_I2S_VALID(ref) ((ref) == USART1) - #endif -#elif defined(_SILICON_LABS_32B_SERIES_0) - #if defined(_EZR32_HAPPY_FAMILY) - #define USART_I2S_VALID(ref) ((ref) == USART0) - #elif defined(_EFM32_HAPPY_FAMILY) - #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) - #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) - #define USART_I2S_VALID(ref) ((ref) == USART1) - #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) - #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) - #endif -#endif - -#if defined(UART_COUNT) && (UART_COUNT == 1) && !defined(_UART_IPVERSION_MASK) - #define UART_REF_VALID(ref) ((ref) == UART0) -#elif defined(UART_COUNT) && (UART_COUNT == 2) && !defined(_UART_IPVERSION_MASK) - #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) -#else - #define UART_REF_VALID(ref) (0) -#endif - -#if defined(_USART_CLKDIV_DIVEXT_MASK) - #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) -#else - #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK -#endif - -/** @endcond */ - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if !defined(_EFM32_GECKO_FAMILY) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Rx input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_INPUT_MASK) - usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) - | USART_INPUT_RXPRS; -#elif defined(USART_CTRLX_RXPRSEN) - if (usart == USART0) { - PRS->CONSUMER_USART0_RX = ch; - } -#if defined(USART1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_RX = ch; - } -#endif -#if defined(USART2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_RX = ch; - } -#endif - usart->CTRLX |= USART_CTRLX_RXPRSEN; -#endif -} -#endif - -#if defined(USART_IRCTRL_IRPRSEN) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Ir input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_IRCTRL_IRPRSSEL_SHIFT) - usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) - | USART_IRCTRL_IRPRSEN; -#else - (void)ch; - usart->IRCTRL |= USART_IRCTRL_IRPRSEN; -#endif -} -#endif - -#if defined(USART_IRCTRL_IRPRSEN) && defined(CONSUMER_USART0_IR) -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Ir input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ - if (usart == USART0) { - PRS->CONSUMER_USART0_IR = ch; - } -#if defined(USART1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_IR = ch; - } -#endif -#if defined(USART2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_IR = ch; - } -#endif - usart->IRCTRL |= USART_IRCTRL_IRPRSEN; -} -#endif - -/***************************************************************************//** - * @brief - * Configure a PRS channel as USART Trigger input - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] ch - * PRS channel. - ******************************************************************************/ -static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) -{ -#if defined(_USART_IRCTRL_IRPRSSEL_MASK) - usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) - | (ch << _USART_TRIGCTRL_TSEL_SHIFT); -#else - if (usart == USART0) { - PRS->CONSUMER_USART0_TRIGGER = ch; - } -#if (USART_COUNT > 1) - else if (usart == USART1) { - PRS->CONSUMER_USART1_TRIGGER = ch; - } -#endif -#if (USART_COUNT > 2) - else if (usart == USART2) { - PRS->CONSUMER_USART2_TRIGGER = ch; - } -#endif -#endif -} - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup usart - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Configure USART/UART operating in asynchronous mode to use a given - * baudrate (or as close as possible to a specified baudrate). - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] refFreq - * USART/UART reference clock frequency in Hz. If set to 0, - * the currently configured reference clock is assumed. - * - * @param[in] baudrate - * Baudrate to try to achieve for USART/UART. - * - * @param[in] ovs - * Oversampling to be used. Normal is 16x oversampling but lower oversampling - * may be used to achieve higher rates or better baudrate accuracy in some - * cases. Notice that lower oversampling frequency makes the channel more - * vulnerable to bit faults during reception due to clock inaccuracies - * compared to the link partner. - ******************************************************************************/ -void USART_BaudrateAsyncSet(USART_TypeDef *usart, - uint32_t refFreq, - uint32_t baudrate, - USART_OVS_TypeDef ovs) -{ - uint32_t clkdiv; - uint32_t oversample = 0; - - /* Inhibit divide by 0 */ - EFM_ASSERT(baudrate); - - /* - * Use integer division to avoid forcing in float division - * utils and yet keep rounding effect errors to a minimum. - * - * CLKDIV in asynchronous mode is given by: - * - * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) - * or - * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 - * - * The basic problem with integer division in the above formula is that - * the dividend (256 * fHFPERCLK) may become higher than max 32 bit - * integer. Yet, we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. - * Too harsh restrictions on maximum fHFPERCLK value should not be made. - * - * It is possible to factorize 256 and oversample/br. However, - * since the last 6 or 3 bits of CLKDIV are don't care, base the - * integer arithmetic on the below formula - * - * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) - * or - * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) - * - * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK - * up to 1 GHz without overflowing a 32 bit value. - */ - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ - if (!refFreq) { -#if defined(_SILICON_LABS_32B_SERIES_2) - refFreq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - } - - /* Map oversampling. */ - switch (ovs) { - case usartOVS16: - EFM_ASSERT(baudrate <= (refFreq / 16)); - oversample = 16; - break; - - case usartOVS8: - EFM_ASSERT(baudrate <= (refFreq / 8)); - oversample = 8; - break; - - case usartOVS6: - EFM_ASSERT(baudrate <= (refFreq / 6)); - oversample = 6; - break; - - case usartOVS4: - EFM_ASSERT(baudrate <= (refFreq / 4)); - oversample = 4; - break; - - default: - /* Invalid input */ - EFM_ASSERT(0); - break; - } - - if (oversample > 0U) { - /* Calculate and set CLKDIV with fractional bits. - * The added (oversample*baudrate)/2 in the first line is to round the - * divisor to the nearest fractional divisor. */ - #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) - /* Devices with 2 fractional bits. CLKDIV[7:6] */ - clkdiv = 4 * refFreq + (oversample * baudrate) / 2; - clkdiv /= oversample * baudrate; - clkdiv -= 4; - clkdiv *= 64; - #else - /* Devices with 5 fractional bits. CLKDIV[7:3] */ - clkdiv = 32 * refFreq + (oversample * baudrate) / 2; - clkdiv /= oversample * baudrate; - clkdiv -= 32; - clkdiv *= 8; - #endif - - /* Verify that the resulting clock divider is within limits. */ - EFM_ASSERT(clkdiv <= CLKDIV_MASK); - - /* Make sure that reserved bits are not written to. */ - clkdiv &= CLKDIV_MASK; - - usart->CTRL &= ~_USART_CTRL_OVS_MASK; - usart->CTRL |= ovs; - usart->CLKDIV = clkdiv; - } -} - -/***************************************************************************//** - * @brief - * Calculate baudrate for USART/UART given reference frequency, clock division, - * and oversampling rate (if async mode). - * - * @details - * This function returns the baudrate that a USART/UART module will use if - * configured with the given frequency, clock divisor, and mode. Notice that - * this function will not use the hardware configuration. It can be used - * to determine if a given configuration is sufficiently accurate for the - * application. - * - * @param[in] refFreq - * USART/UART HF peripheral frequency used. - * - * @param[in] clkdiv - * A clock division factor to be used. - * - * @param[in] syncmode - * @li True - synchronous mode operation. - * @li False - asynchronous mode operation. - * - * @param[in] ovs - * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. - * - * @return - * Baudrate with given settings. - ******************************************************************************/ -uint32_t USART_BaudrateCalc(uint32_t refFreq, - uint32_t clkdiv, - bool syncmode, - USART_OVS_TypeDef ovs) -{ - uint32_t oversample; - uint64_t divisor; - uint64_t factor; - uint64_t remainder; - uint64_t quotient; - uint32_t br; - - /* Out of bound clkdiv. */ - EFM_ASSERT(clkdiv <= CLKDIV_MASK); - - /* Mask out unused bits */ - clkdiv &= CLKDIV_MASK; - - /* Use integer division to avoid forcing in float division */ - /* utils and yet keep rounding effect errors to a minimum. */ - - /* Baudrate calculation depends on if synchronous or asynchronous mode. */ - if (syncmode) { - /* - * Baudrate is given by: - * - * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) - * - * which can be rewritten to - * - * br = (128 * fHFPERCLK)/(256 + CLKDIV) - */ - oversample = 1; /* Not used in sync mode, i.e., 1 */ - factor = 128; - } else { - /* - * Baudrate in asynchronous mode is given by: - * - * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) - * - * which can be rewritten to - * - * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) - * - * 256 factor of the dividend is reduced with a - * (part of) oversample part of the divisor. - */ - - switch (ovs) { - case usartOVS16: - oversample = 1; - factor = 256 / 16; - break; - - case usartOVS8: - oversample = 1; - factor = 256 / 8; - break; - - case usartOVS6: - oversample = 3; - factor = 256 / 2; - break; - - default: - oversample = 1; - factor = 256 / 4; - break; - } - } - - /* - * The basic problem with integer division in the above formula is that - * the dividend (factor * fHFPERCLK) may become larger than a 32 bit - * integer. Yet we want to evaluate the dividend first before dividing - * to get as small rounding effects as possible. Too harsh restrictions - * should not be made on the maximum fHFPERCLK value either. - * - * For division a/b, - * - * a = qb + r - * - * where q is the quotient and r is the remainder, both integers. - * - * The original baudrate formula can be rewritten as - * - * br = xa / b = x(qb + r)/b = xq + xr/b - * - * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to - * variable names. - */ - - /* - * The divisor will never exceed max 32 bit value since - * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) - * and 'oversample' has been reduced to <= 3. - */ - divisor = (uint64_t)(oversample * (256 + clkdiv)); - - quotient = refFreq / divisor; - remainder = refFreq % divisor; - - /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ - /* 32 bit value. However, factor * remainder can become larger than 32-bit */ - /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ - br = (uint32_t)(factor * quotient); - - /* - * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which - * means dividend (factor * remainder) worst case is - * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. - */ - br += (uint32_t)((factor * remainder) / divisor); - - return br; -} - -/***************************************************************************//** - * @brief - * Get the current baudrate for USART/UART. - * - * @details - * This function returns the actual baudrate (not considering oscillator - * inaccuracies) used by a USART/UART peripheral. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * The current baudrate. - ******************************************************************************/ -uint32_t USART_BaudrateGet(USART_TypeDef *usart) -{ - uint32_t freq; - USART_OVS_TypeDef ovs; - bool syncmode; - - if (usart->CTRL & USART_CTRL_SYNC) { - syncmode = true; - } else { - syncmode = false; - } - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ -#if defined(_SILICON_LABS_32B_SERIES_2) - freq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - freq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - freq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - freq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); - return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); -} - -/***************************************************************************//** - * @brief - * Configure the USART operating in synchronous mode to use a given baudrate - * (or as close as possible to a specified baudrate). - * - * @details - * The configuration will be set to use a baudrate <= the specified baudrate - * to ensure that the baudrate does not exceed the specified value. - * - * The fractional clock division is suppressed, although the hardware design allows it. - * It could cause half clock cycles to exceed a specified limit and thus - * potentially violate specifications for the slave device. In some special - * situations, a fractional clock division may be useful even in synchronous - * mode, but in those cases it must be directly adjusted, possibly assisted - * by USART_BaudrateCalc(): - * - * @warning - * The consequence of the aforementioned suppression of the fractional part of - * the clock divider is that some frequencies won't be achievable. The divider - * will only be able to be an integer value so the reference clock will only be - * dividable by N (where N is a positive integer). - * - * @param[in] usart - * A pointer to the USART peripheral register block. (Cannot be used on UART - * modules.) - * - * @param[in] refFreq - * A USART reference clock frequency in Hz that will be used. If set to 0, - * the currently-configured reference clock is assumed. - * - * @param[in] baudrate - * Baudrate to try to achieve for USART. - ******************************************************************************/ -void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) -{ - uint32_t clkdiv; - - /* Prevent dividing by 0. */ - EFM_ASSERT(baudrate); - - /* - * CLKDIV in synchronous mode is given by: - * - * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) - */ - - /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ - if (!refFreq) { -#if defined(_SILICON_LABS_32B_SERIES_2) - refFreq = CMU_ClockFreqGet(cmuClock_PCLK); -#else -#if defined(_CMU_HFPERPRESCB_MASK) - if (usart == USART2) { - refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); - } else { - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); - } -#else - refFreq = CMU_ClockFreqGet(cmuClock_HFPER); -#endif -#endif - } - - /* - * The clock divider computation is done by using unsigned integer. - * The goal is to truncate the fractional part of the resulting - * clock divider value. - * Note: The divider field of the USART->CLKDIV register is of the following form: - * xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider - * and y is the 5 bits fractional part. - */ - clkdiv = (refFreq - 1) / (2 * baudrate); - clkdiv = clkdiv << 8; - - /* Verify that resulting clock divider is within limits. */ - EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); - - usart->CLKDIV = clkdiv; -} - -/***************************************************************************//** - * @brief - * Enable/disable USART/UART receiver and/or transmitter. - * - * @details - * Notice that this function does not do any configuration. Enabling should - * normally be done after initialization (if not enabled as part - * of initialization). - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] enable - * Select the status for the receiver/transmitter. - ******************************************************************************/ -void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) -{ - uint32_t tmp; - - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart)); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - - /* Disable as specified. */ - tmp = ~((uint32_t)enable); - tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; - usart->CMD = tmp << 1; - - /* Enable as specified. */ - usart->CMD = (uint32_t)enable; - -#if defined(USART_EN_EN) - if (enable == usartDisable) { - usart->EN_CLR = USART_EN_EN; - } -#endif -} - -/***************************************************************************//** - * @brief - * Initialize USART/UART for normal asynchronous mode. - * - * @details - * This function will configure basic settings to operate in normal - * asynchronous mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL register. - * - * Notice that pins used by the USART/UART module must be properly configured - * by the user explicitly for the USART/UART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure the basic async setup. - ******************************************************************************/ -void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart)); - - /* Initialize USART registers to hardware reset state. */ - USART_Reset(usart); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - -#if defined(USART_CTRL_MVDIS) - /* Disable the majority vote if specified. */ - if (init->mvdis) { - usart->CTRL |= USART_CTRL_MVDIS; - } -#endif - -#if !defined(_EFM32_GECKO_FAMILY) - /* Configure the PRS input mode. */ - if (init->prsRxEnable) { - prsRxInput(usart, init->prsRxCh); - } -#endif - - /* Configure databits, stopbits, and parity. */ - usart->FRAME = (uint32_t)init->databits - | (uint32_t)init->stopbits - | (uint32_t)init->parity; - - /* Configure baudrate. */ - USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); - - if (init->autoCsEnable) { - usart->CTRL |= USART_CTRL_AUTOCS; - } - if (init->csInv) { - usart->CTRL |= USART_CTRL_CSINV; - } -#if defined(_USART_TIMING_CSHOLD_MASK) - usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) - & _USART_TIMING_CSHOLD_MASK) - | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) - & _USART_TIMING_CSSETUP_MASK); - -#endif - -#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) - usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); - usart->ROUTEPEN |= init->hwFlowControl; - -#elif defined(USART_CTRLX_CTSEN) - if ((init->hwFlowControl == usartHwFlowControlRts) - || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { -#if USART_COUNT > 1 - GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#else - //! @todo cleanup when ADM is updated to have USART_NUM macros - GPIO->USARTROUTE_SET[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#endif - } else { -#if USART_COUNT > 1 - GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#else - //! @todo cleanup when ADM is updated to have USART_NUM macros - GPIO->USARTROUTE_CLR[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; -#endif - } - - if ((init->hwFlowControl == usartHwFlowControlCts) - || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { - usart->CTRLX_SET = USART_CTRLX_CTSEN; - } else { - usart->CTRLX_CLR = USART_CTRLX_CTSEN; - } -#endif - - /* Finally, enable (as specified). */ - usart->CMD = (uint32_t)init->enable; -} - -/***************************************************************************//** - * @brief - * Initialize USART for synchronous mode. - * - * @details - * This function will configure basic settings to operate in - * synchronous mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL register. - * - * Notice that pins used by the USART module must be properly configured - * by the user explicitly for the USART to work as intended. - * (When configuring pins remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. (UART does not support this - * mode.) - * - * @param[in] init - * A pointer to the initialization structure used to configure basic async setup. - ******************************************************************************/ -void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); - - /* Initialize USART registers to hardware reset state. */ - USART_Reset(usart); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; -#endif - - /* Set bits for synchronous mode. */ - usart->CTRL |= (USART_CTRL_SYNC) - | (uint32_t)init->clockMode - | (init->msbf ? USART_CTRL_MSBF : 0); - -#if defined(_USART_CTRL_AUTOTX_MASK) - usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; -#endif - -#if !defined(_EFM32_GECKO_FAMILY) - if (init->prsRxEnable) { - prsRxInput(usart, init->prsRxCh); - } -#endif - - /* Configure databits, leave stopbits and parity at reset default (not used). */ - usart->FRAME = (uint32_t)init->databits - | USART_FRAME_STOPBITS_DEFAULT - | USART_FRAME_PARITY_DEFAULT; - - /* Configure the baudrate. */ - USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); - - /* Finally, enable (as specified). */ - if (init->master) { - usart->CMD = USART_CMD_MASTEREN; - } - - if (init->autoCsEnable) { - usart->CTRL |= USART_CTRL_AUTOCS; - } - if (init->csInv) { - usart->CTRL |= USART_CTRL_CSINV; - } -#if defined(_USART_TIMING_CSHOLD_MASK) - usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) - & _USART_TIMING_CSHOLD_MASK) - | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) - & _USART_TIMING_CSSETUP_MASK); -#endif - - usart->CMD = (uint32_t)init->enable; -} - -/***************************************************************************//** - * @brief - * Initialize USART for asynchronous IrDA mode. - * - * @details - * This function will configure basic settings to operate in - * asynchronous IrDA mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL and IRCTRL - * registers. - * - * Notice that pins used by the USART/UART module must be properly configured - * by the user explicitly for the USART/UART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. - * - * @param[in] init - * A pointer to the initialization structure used to configure async IrDA setup. - * - * @note - * Not all USART instances support IrDA. See the data sheet for your device. - * - ******************************************************************************/ -void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) -{ - EFM_ASSERT(USART_IRDA_VALID(usart)); - - /* Initialize USART as an async device. */ - USART_InitAsync(usart, &(init->async)); - - /* Set IrDA modulation to RZI (return-to-zero-inverted). */ - usart->CTRL |= USART_CTRL_TXINV; - - /* Invert the Rx signal before the demodulator if enabled. */ - if (init->irRxInv) { - usart->CTRL |= USART_CTRL_RXINV; - } - - /* Configure IrDA. */ - usart->IRCTRL = (uint32_t)init->irPw - | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); - -#if defined(USART_IRCTRL_IRPRSEN) - if (init->irPrsEn) { - prsIrInput(usart, init->irPrsSel); - } -#endif - - /* Enable IrDA. */ - usart->IRCTRL |= USART_IRCTRL_IREN; -} - -#if defined(_USART_I2SCTRL_MASK) -/***************************************************************************//** - * @brief - * Initialize USART for I2S mode. - * - * @details - * This function will configure basic settings to operate in I2S - * mode. - * - * A special control setup not covered by this function must be done after - * using this function by direct modification of the CTRL and I2SCTRL - * registers. - * - * Notice that pins used by the USART module must be properly configured - * by the user explicitly for the USART to work as intended. - * (When configuring pins, remember to consider the sequence of - * configuration to avoid unintended pulses/glitches on output - * pins.) - * - * @param[in] usart - * A pointer to the USART peripheral register block. (UART does not support this - * mode.) - * - * @param[in] init - * A pointer to the initialization structure used to configure the basic I2S setup. - * - * @note - * This function does not apply to all USART's. See the chip Reference Manual. - * - ******************************************************************************/ -void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) -{ - USART_Enable_TypeDef enable; - - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_I2S_VALID(usart)); - - /* Override the enable setting. */ - enable = init->sync.enable; - init->sync.enable = usartDisable; - - /* Initialize USART as a sync device. */ - USART_InitSync(usart, &init->sync); - - /* Configure and enable I2CCTRL register according to the selected mode. */ - usart->I2SCTRL = (uint32_t)init->format - | (uint32_t)init->justify - | (init->delay ? USART_I2SCTRL_DELAY : 0) - | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) - | (init->mono ? USART_I2SCTRL_MONO : 0) - | USART_I2SCTRL_EN; - - if (enable != usartDisable) { - USART_Enable(usart, enable); - } -} -#endif - -/***************************************************************************//** - * @brief - * Initialize the automatic transmissions using PRS channel as a trigger. - * @note - * Initialize USART with USART_Init() before setting up the PRS configuration. - * - * @param[in] usart - * A pointer to USART to configure. - * - * @param[in] init - * A pointer to the initialization structure. - ******************************************************************************/ -void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) -{ - uint32_t trigctrl; - - prsTriggerInput(usart, init->prsTriggerChannel); - /* Clear values that will be reconfigured. */ - trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK - | _USART_TRIGCTRL_TXTEN_MASK -#if defined(USART_TRIGCTRL_AUTOTXTEN) - | _USART_TRIGCTRL_AUTOTXTEN_MASK -#endif - ); - -#if defined(USART_TRIGCTRL_AUTOTXTEN) - if (init->autoTxTriggerEnable) { - trigctrl |= USART_TRIGCTRL_AUTOTXTEN; - } -#endif - if (init->txTriggerEnable) { - trigctrl |= USART_TRIGCTRL_TXTEN; - } - if (init->rxTriggerEnable) { - trigctrl |= USART_TRIGCTRL_RXTEN; - } - usart->TRIGCTRL = trigctrl; -} - -/***************************************************************************//** - * @brief - * Reset USART/UART to the same state that it was in after a hardware reset. - * - * @param[in] usart - * A pointer to USART/UART peripheral register block. - ******************************************************************************/ -void USART_Reset(USART_TypeDef *usart) -{ - /* Make sure the module exists on the selected chip. */ - EFM_ASSERT(USART_REF_VALID(usart) - || USARTRF_REF_VALID(usart) - || UART_REF_VALID(usart) ); - -#if defined(USART_EN_EN) - usart->EN_SET = USART_EN_EN; - /* Make sure disabled first, before resetting other registers. */ - usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS - | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX - | USART_CMD_CLEARRX; - - usart->CTRL = _USART_CTRL_RESETVALUE; - usart->CTRLX = _USART_CTRLX_RESETVALUE; - usart->FRAME = _USART_FRAME_RESETVALUE; - usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; - usart->CLKDIV = _USART_CLKDIV_RESETVALUE; - usart->IEN = _USART_IEN_RESETVALUE; - usart->IF_CLR = _USART_IF_MASK; - usart->TIMING = _USART_TIMING_RESETVALUE; - - if (USART_IRDA_VALID(usart)) { - usart->IRCTRL = _USART_IRCTRL_RESETVALUE; - } - - if (USART_I2S_VALID(usart)) { - usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; - } - usart->EN_CLR = USART_EN_EN; - -#else - /* Make sure disabled first, before resetting other registers */ - usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS - | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX - | USART_CMD_CLEARRX; - - usart->CTRL = _USART_CTRL_RESETVALUE; - usart->FRAME = _USART_FRAME_RESETVALUE; - usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; - usart->CLKDIV = _USART_CLKDIV_RESETVALUE; - usart->IEN = _USART_IEN_RESETVALUE; - usart->IFC = _USART_IFC_MASK; -#if defined(_USART_TIMING_MASK) - usart->TIMING = _USART_TIMING_RESETVALUE; -#endif -#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) - usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; - usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; - usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; -#else - usart->ROUTE = _USART_ROUTE_RESETVALUE; -#endif - - if (USART_IRDA_VALID(usart)) { - usart->IRCTRL = _USART_IRCTRL_RESETVALUE; - } - -#if defined(_USART_INPUT_RESETVALUE) - usart->INPUT = _USART_INPUT_RESETVALUE; -#endif - -#if defined(_USART_I2SCTRL_RESETVALUE) - if (USART_I2S_VALID(usart)) { - usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; - } -#endif -#endif -} - -/***************************************************************************//** - * @brief - * Receive one 4-8 bit frame, (or part of 10-16 bit frame). - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 4-8 bits. See @ref USART_RxExt() for reception of - * 9 bit frames. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDataGet() to read the RXDATA - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint8_t USART_Rx(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXDATAV)) { - } - - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Receive two 4-8 bit frames or one 10-16 bit frame. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits. See @ref USART_RxDoubleExt() for - * reception of two 9 bit frames. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint16_t USART_RxDouble(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXFULL)) { - } - - return (uint16_t)usart->RXDOUBLE; -} - -/***************************************************************************//** - * @brief - * Receive two 4-9 bit frames, or one 10-16 bit frame with extended - * information. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 10-16 bits and additional RX status information is required. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint32_t USART_RxDoubleExt(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXFULL)) { - } - - return usart->RXDOUBLEX; -} - -/***************************************************************************//** - * @brief - * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended - * information. - * - * @details - * This function is normally used to receive one frame when operating with - * frame length 4-9 bits and additional RX status information is required. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is empty until data is received. - * Alternatively, the user can explicitly check whether data is available. - * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX - * register directly. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @return - * Data received. - ******************************************************************************/ -uint16_t USART_RxExt(USART_TypeDef *usart) -{ - while (!(usart->STATUS & USART_STATUS_RXDATAV)) { - } - - return (uint16_t)usart->RXDATAX; -} - -/***************************************************************************//** - * @brief - * Perform one 8 bit frame SPI transfer. - * - * @note - * This function will stall if the transmit buffer is full. When a transmit - * buffer becomes available, data is written and the function will wait until - * data is fully transmitted. The SPI return value is then read out and - * returned. - * - * @param[in] usart - * A pointer to the USART peripheral register block. - * - * @param[in] data - * Data to transmit. - * - * @return - * Data received. - ******************************************************************************/ -uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) -{ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATA = (uint32_t)data; - while (!(usart->STATUS & USART_STATUS_TXC)) { - } - return (uint8_t)usart->RXDATA; -} - -/***************************************************************************//** - * @brief - * Transmit one 4-9 bit frame. - * - * @details - * Depending on the frame length configuration, 4-8 (least significant) bits from - * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from - * @p data and one bit as specified by CTRL register, BIT8DV field. - * See USART_TxExt() for transmitting 9 bit frame with full control of - * all 9 bits. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit. See details above for more information. - ******************************************************************************/ -void USART_Tx(USART_TypeDef *usart, uint8_t data) -{ - /* Check that transmit buffer is empty */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATA = (uint32_t)data; -} - -/***************************************************************************//** - * @brief - * Transmit two 4-9 bit frames or one 10-16 bit frame. - * - * @details - * Depending on the frame length configuration, 4-8 (least significant) bits from - * each byte in @p data are transmitted. If frame length is 9, 8 bits are - * transmitted from each byte in @p data adding one bit as specified by the CTRL - * register, BIT8DV field, to each byte. See USART_TxDoubleExt() - * for transmitting two 9 bit frames with full control of all 9 bits. - * - * If the frame length is 10-16, 10-16 (least significant) bits from @p data - * are transmitted. - * - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit, the least significant byte holds the frame transmitted - * first. See details above for more info. - ******************************************************************************/ -void USART_TxDouble(USART_TypeDef *usart, uint16_t data) -{ - /* Check that transmit buffer is empty */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDOUBLE = (uint32_t)data; -} - -/***************************************************************************//** - * @brief - * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. - * - * @details - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit with extended control. Contains two 16 bit words - * concatenated. Least significant word holds the frame transmitted first. If the frame - * length is 4-9, two frames with 4-9 least significant bits from each 16 bit - * word are transmitted. - * @par - * If the frame length is 10-16 bits, 8 data bits are taken from the least - * significant 16 bit word and the remaining bits from the other 16 bit word. - * @par - * Additional control bits are available as documented in the reference - * manual (set to 0 if not used). For 10-16 bit frame length, these control - * bits are taken from the most significant 16 bit word. - ******************************************************************************/ -void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) -{ - /* Check that transmit buffer is empty. */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDOUBLEX = data; -} - -/***************************************************************************//** - * @brief - * Transmit one 4-9 bit frame with extended control. - * - * @details - * Notice that possible parity/stop bits in asynchronous mode are not - * considered part of a specified frame bit length. - * - * @note - * This function will stall if the buffer is full until the buffer becomes available. - * - * @param[in] usart - * A pointer to the USART/UART peripheral register block. - * - * @param[in] data - * Data to transmit with extended control. Least significant bit contains - * frame bits. Additional control bits are available as documented in - * the reference manual (set to 0 if not used). - ******************************************************************************/ -void USART_TxExt(USART_TypeDef *usart, uint16_t data) -{ - /* Check that the transmit buffer is empty. */ - while (!(usart->STATUS & USART_STATUS_TXBL)) { - } - usart->TXDATAX = (uint32_t)data; -} - -/** @} (end addtogroup usart) */ -#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART) + * Peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_usart.h" +#if defined(USART_COUNT) && (USART_COUNT > 0) + +#include "em_cmu.h" +#include "em_bus.h" +#include "sl_assert.h" +#if defined(USART_CTRLX_CTSEN) +#include "em_gpio.h" +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ + +/** Validation of USART register block pointer reference for assert statements. */ +#if (USART_COUNT == 1) && defined(USART0) +#define USART_REF_VALID(ref) ((ref) == USART0) + +#elif (USART_COUNT == 1) && defined(USART1) +#define USART_REF_VALID(ref) ((ref) == USART1) + +#elif (USART_COUNT == 2) && defined(USART2) +#define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + +#elif (USART_COUNT == 2) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + +#elif (USART_COUNT == 3) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2)) +#elif (USART_COUNT == 4) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3)) +#elif (USART_COUNT == 5) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4)) +#elif (USART_COUNT == 6) +#define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) \ + || ((ref) == USART2) || ((ref) == USART3) \ + || ((ref) == USART4) || ((ref) == USART5)) +#else +#error "Undefined number of USARTs." +#endif + +#if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0) + #if (USARTRF_COUNT == 1) && defined(USARTRF0) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0) + #elif (USARTRF_COUNT == 1) && defined(USARTRF1) + #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1) + #else + #define USARTRF_REF_VALID(ref) (0) + #endif +#else + #define USARTRF_REF_VALID(ref) (0) +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_IRDA_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100) || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103) +// If GG11 or TG11 + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART2)) + #elif defined(USART3) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2) || ((ref) == USART3)) + #elif defined(USART2) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || ((ref) == USART2)) + #else + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(USART0) + #define USART_IRDA_VALID(ref) ((ref) == USART0) + #elif (USART_COUNT == 1) && defined(USART1) + #define USART_IRDA_VALID(ref) ((ref) == USART1) + #elif defined(USARTRF0) + #define USART_IRDA_VALID(ref) ((ref) == USARTRF0) + #else + #define USART_IRDA_VALID(ref) (0) + #endif +#endif + +#if (_SILICON_LABS_32B_SERIES == 2) + #define USART_I2S_VALID(ref) USART_REF_VALID(ref) +#elif defined(_SILICON_LABS_32B_SERIES_1) + #if defined(USART4) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3) || ((ref) == USART4)) + #elif defined(USART3) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART3)) + #else + #define USART_I2S_VALID(ref) ((ref) == USART1) + #endif +#elif defined(_SILICON_LABS_32B_SERIES_0) + #if defined(_EZR32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART0) + #elif defined(_EFM32_HAPPY_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1)) + #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) + #define USART_I2S_VALID(ref) ((ref) == USART1) + #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY) + #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2)) + #endif +#endif + +#if defined(UART_COUNT) && (UART_COUNT == 1) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) ((ref) == UART0) +#elif defined(UART_COUNT) && (UART_COUNT == 2) && !defined(_UART_IPVERSION_MASK) + #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1)) +#else + #define UART_REF_VALID(ref) (0) +#endif + +#if defined(_USART_CLKDIV_DIVEXT_MASK) + #define CLKDIV_MASK (_USART_CLKDIV_DIV_MASK | _USART_CLKDIV_DIVEXT_MASK) +#else + #define CLKDIV_MASK _USART_CLKDIV_DIV_MASK +#endif + +/** @endcond */ + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if !defined(_EFM32_GECKO_FAMILY) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Rx input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsRxInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_INPUT_MASK) + usart->INPUT = ((uint32_t)ch << _USART_INPUT_RXPRSSEL_SHIFT) + | USART_INPUT_RXPRS; +#elif defined(USART_CTRLX_RXPRSEN) + if (usart == USART0) { + PRS->CONSUMER_USART0_RX = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_RX = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_RX = ch; + } +#endif + usart->CTRLX |= USART_CTRLX_RXPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_SHIFT) + usart->IRCTRL |= ((uint32_t)ch << _USART_IRCTRL_IRPRSSEL_SHIFT) + | USART_IRCTRL_IRPRSEN; +#else + (void)ch; + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +#endif +} +#endif + +#if defined(USART_IRCTRL_IRPRSEN) && defined(CONSUMER_USART0_IR) +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Ir input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsIrInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ + if (usart == USART0) { + PRS->CONSUMER_USART0_IR = ch; + } +#if defined(USART1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_IR = ch; + } +#endif +#if defined(USART2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_IR = ch; + } +#endif + usart->IRCTRL |= USART_IRCTRL_IRPRSEN; +} +#endif + +/***************************************************************************//** + * @brief + * Configure a PRS channel as USART Trigger input + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] ch + * PRS channel. + ******************************************************************************/ +static void prsTriggerInput(USART_TypeDef *usart, USART_PRS_Channel_t ch) +{ +#if defined(_USART_IRCTRL_IRPRSSEL_MASK) + usart->TRIGCTRL = (usart->TRIGCTRL & ~_USART_TRIGCTRL_TSEL_MASK) + | (ch << _USART_TRIGCTRL_TSEL_SHIFT); +#else + if (usart == USART0) { + PRS->CONSUMER_USART0_TRIGGER = ch; + } +#if (USART_COUNT > 1) + else if (usart == USART1) { + PRS->CONSUMER_USART1_TRIGGER = ch; + } +#endif +#if (USART_COUNT > 2) + else if (usart == USART2) { + PRS->CONSUMER_USART2_TRIGGER = ch; + } +#endif +#endif +} + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup usart + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Configure USART/UART operating in asynchronous mode to use a given + * baudrate (or as close as possible to a specified baudrate). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] refFreq + * USART/UART reference clock frequency in Hz. If set to 0, + * the currently configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART/UART. + * + * @param[in] ovs + * Oversampling to be used. Normal is 16x oversampling but lower oversampling + * may be used to achieve higher rates or better baudrate accuracy in some + * cases. Notice that lower oversampling frequency makes the channel more + * vulnerable to bit faults during reception due to clock inaccuracies + * compared to the link partner. + ******************************************************************************/ +void USART_BaudrateAsyncSet(USART_TypeDef *usart, + uint32_t refFreq, + uint32_t baudrate, + USART_OVS_TypeDef ovs) +{ + uint32_t clkdiv; + uint32_t oversample = 0; + + /* Inhibit divide by 0 */ + EFM_ASSERT(baudrate); + + /* + * Use integer division to avoid forcing in float division + * utils and yet keep rounding effect errors to a minimum. + * + * CLKDIV in asynchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1) + * or + * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256 + * + * The basic problem with integer division in the above formula is that + * the dividend (256 * fHFPERCLK) may become higher than max 32 bit + * integer. Yet, we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. + * Too harsh restrictions on maximum fHFPERCLK value should not be made. + * + * It is possible to factorize 256 and oversample/br. However, + * since the last 6 or 3 bits of CLKDIV are don't care, base the + * integer arithmetic on the below formula + * + * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care) + * or + * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care) + * + * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK + * up to 1 GHz without overflowing a 32 bit value. + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* Map oversampling. */ + switch (ovs) { + case usartOVS16: + EFM_ASSERT(baudrate <= (refFreq / 16)); + oversample = 16; + break; + + case usartOVS8: + EFM_ASSERT(baudrate <= (refFreq / 8)); + oversample = 8; + break; + + case usartOVS6: + EFM_ASSERT(baudrate <= (refFreq / 6)); + oversample = 6; + break; + + case usartOVS4: + EFM_ASSERT(baudrate <= (refFreq / 4)); + oversample = 4; + break; + + default: + /* Invalid input */ + EFM_ASSERT(0); + break; + } + + if (oversample > 0U) { + /* Calculate and set CLKDIV with fractional bits. + * The added (oversample*baudrate)/2 in the first line is to round the + * divisor to the nearest fractional divisor. */ + #if defined(_SILICON_LABS_32B_SERIES_0) && !defined(_EFM32_HAPPY_FAMILY) + /* Devices with 2 fractional bits. CLKDIV[7:6] */ + clkdiv = 4 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 4; + clkdiv *= 64; + #else + /* Devices with 5 fractional bits. CLKDIV[7:3] */ + clkdiv = 32 * refFreq + (oversample * baudrate) / 2; + clkdiv /= oversample * baudrate; + clkdiv -= 32; + clkdiv *= 8; + #endif + + /* Verify that the resulting clock divider is within limits. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Make sure that reserved bits are not written to. */ + clkdiv &= CLKDIV_MASK; + + usart->CTRL &= ~_USART_CTRL_OVS_MASK; + usart->CTRL |= ovs; + usart->CLKDIV = clkdiv; + } +} + +/***************************************************************************//** + * @brief + * Calculate baudrate for USART/UART given reference frequency, clock division, + * and oversampling rate (if async mode). + * + * @details + * This function returns the baudrate that a USART/UART module will use if + * configured with the given frequency, clock divisor, and mode. Notice that + * this function will not use the hardware configuration. It can be used + * to determine if a given configuration is sufficiently accurate for the + * application. + * + * @param[in] refFreq + * USART/UART HF peripheral frequency used. + * + * @param[in] clkdiv + * A clock division factor to be used. + * + * @param[in] syncmode + * @li True - synchronous mode operation. + * @li False - asynchronous mode operation. + * + * @param[in] ovs + * Oversampling used if in asynchronous mode. Not used if @p syncmode is true. + * + * @return + * Baudrate with given settings. + ******************************************************************************/ +uint32_t USART_BaudrateCalc(uint32_t refFreq, + uint32_t clkdiv, + bool syncmode, + USART_OVS_TypeDef ovs) +{ + uint32_t oversample; + uint64_t divisor; + uint64_t factor; + uint64_t remainder; + uint64_t quotient; + uint32_t br; + + /* Out of bound clkdiv. */ + EFM_ASSERT(clkdiv <= CLKDIV_MASK); + + /* Mask out unused bits */ + clkdiv &= CLKDIV_MASK; + + /* Use integer division to avoid forcing in float division */ + /* utils and yet keep rounding effect errors to a minimum. */ + + /* Baudrate calculation depends on if synchronous or asynchronous mode. */ + if (syncmode) { + /* + * Baudrate is given by: + * + * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (128 * fHFPERCLK)/(256 + CLKDIV) + */ + oversample = 1; /* Not used in sync mode, i.e., 1 */ + factor = 128; + } else { + /* + * Baudrate in asynchronous mode is given by: + * + * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256))) + * + * which can be rewritten to + * + * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV)) + * + * 256 factor of the dividend is reduced with a + * (part of) oversample part of the divisor. + */ + + switch (ovs) { + case usartOVS16: + oversample = 1; + factor = 256 / 16; + break; + + case usartOVS8: + oversample = 1; + factor = 256 / 8; + break; + + case usartOVS6: + oversample = 3; + factor = 256 / 2; + break; + + default: + oversample = 1; + factor = 256 / 4; + break; + } + } + + /* + * The basic problem with integer division in the above formula is that + * the dividend (factor * fHFPERCLK) may become larger than a 32 bit + * integer. Yet we want to evaluate the dividend first before dividing + * to get as small rounding effects as possible. Too harsh restrictions + * should not be made on the maximum fHFPERCLK value either. + * + * For division a/b, + * + * a = qb + r + * + * where q is the quotient and r is the remainder, both integers. + * + * The original baudrate formula can be rewritten as + * + * br = xa / b = x(qb + r)/b = xq + xr/b + * + * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to + * variable names. + */ + + /* + * The divisor will never exceed max 32 bit value since + * clkdiv <= _USART_CLKDIV_DIV_MASK (currently 0x1FFFC0 or 0x7FFFF8) + * and 'oversample' has been reduced to <= 3. + */ + divisor = (uint64_t)(oversample * (256 + clkdiv)); + + quotient = refFreq / divisor; + remainder = refFreq % divisor; + + /* The factor <= 128 and since divisor >= 256, the below cannot exceed the maximum */ + /* 32 bit value. However, factor * remainder can become larger than 32-bit */ + /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */ + br = (uint32_t)(factor * quotient); + + /* + * The factor <= 128 and remainder < (oversample*(256 + clkdiv)), which + * means dividend (factor * remainder) worst case is + * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400. + */ + br += (uint32_t)((factor * remainder) / divisor); + + return br; +} + +/***************************************************************************//** + * @brief + * Get the current baudrate for USART/UART. + * + * @details + * This function returns the actual baudrate (not considering oscillator + * inaccuracies) used by a USART/UART peripheral. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * The current baudrate. + ******************************************************************************/ +uint32_t USART_BaudrateGet(USART_TypeDef *usart) +{ + uint32_t freq; + USART_OVS_TypeDef ovs; + bool syncmode; + + if (usart->CTRL & USART_CTRL_SYNC) { + syncmode = true; + } else { + syncmode = false; + } + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ +#if defined(_SILICON_LABS_32B_SERIES_2) + freq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + freq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + freq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + freq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK); + return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs); +} + +/***************************************************************************//** + * @brief + * Configure the USART operating in synchronous mode to use a given baudrate + * (or as close as possible to a specified baudrate). + * + * @details + * The configuration will be set to use a baudrate <= the specified baudrate + * to ensure that the baudrate does not exceed the specified value. + * + * The fractional clock division is suppressed, although the hardware design allows it. + * It could cause half clock cycles to exceed a specified limit and thus + * potentially violate specifications for the slave device. In some special + * situations, a fractional clock division may be useful even in synchronous + * mode, but in those cases it must be directly adjusted, possibly assisted + * by USART_BaudrateCalc(): + * + * @warning + * The consequence of the aforementioned suppression of the fractional part of + * the clock divider is that some frequencies won't be achievable. The divider + * will only be able to be an integer value so the reference clock will only be + * dividable by N (where N is a positive integer). + * + * @param[in] usart + * A pointer to the USART peripheral register block. (Cannot be used on UART + * modules.) + * + * @param[in] refFreq + * A USART reference clock frequency in Hz that will be used. If set to 0, + * the currently-configured reference clock is assumed. + * + * @param[in] baudrate + * Baudrate to try to achieve for USART. + ******************************************************************************/ +void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate) +{ + uint32_t clkdiv; + + /* Prevent dividing by 0. */ + EFM_ASSERT(baudrate); + + /* + * CLKDIV in synchronous mode is given by: + * + * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1) + */ + + /* HFPERCLK/HFPERBCLK used to clock all USART/UART peripheral modules. */ + if (!refFreq) { +#if defined(_SILICON_LABS_32B_SERIES_2) + refFreq = CMU_ClockFreqGet(cmuClock_PCLK); +#else +#if defined(_CMU_HFPERPRESCB_MASK) + if (usart == USART2) { + refFreq = CMU_ClockFreqGet(cmuClock_HFPERB); + } else { + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); + } +#else + refFreq = CMU_ClockFreqGet(cmuClock_HFPER); +#endif +#endif + } + + /* + * The clock divider computation is done by using unsigned integer. + * The goal is to truncate the fractional part of the resulting + * clock divider value. + * Note: The divider field of the USART->CLKDIV register is of the following form: + * xxxxxxxxxxxxxxx.yyyyy where x is the 15 bits integral part of the divider + * and y is the 5 bits fractional part. + */ + clkdiv = (refFreq - 1) / (2 * baudrate); + clkdiv = clkdiv << 8; + + /* Verify that resulting clock divider is within limits. */ + EFM_ASSERT(!(clkdiv & ~CLKDIV_MASK)); + + usart->CLKDIV = clkdiv; +} + +/***************************************************************************//** + * @brief + * Enable/disable USART/UART receiver and/or transmitter. + * + * @details + * Notice that this function does not do any configuration. Enabling should + * normally be done after initialization (if not enabled as part + * of initialization). + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] enable + * Select the status for the receiver/transmitter. + ******************************************************************************/ +void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable) +{ + uint32_t tmp; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Disable as specified. */ + tmp = ~((uint32_t)enable); + tmp &= _USART_CMD_RXEN_MASK | _USART_CMD_TXEN_MASK; + usart->CMD = tmp << 1; + + /* Enable as specified. */ + usart->CMD = (uint32_t)enable; + +#if defined(USART_EN_EN) + if (enable == usartDisable) { + usart->EN_CLR = USART_EN_EN; + } +#endif +} + +/***************************************************************************//** + * @brief + * Initialize USART/UART for normal asynchronous mode. + * + * @details + * This function will configure basic settings to operate in normal + * asynchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic async setup. + ******************************************************************************/ +void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart)); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + +#if defined(USART_CTRL_MVDIS) + /* Disable the majority vote if specified. */ + if (init->mvdis) { + usart->CTRL |= USART_CTRL_MVDIS; + } +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + /* Configure the PRS input mode. */ + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, stopbits, and parity. */ + usart->FRAME = (uint32_t)init->databits + | (uint32_t)init->stopbits + | (uint32_t)init->parity; + + /* Configure baudrate. */ + USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling); + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); + +#endif + +#if defined(_USART_ROUTEPEN_RTSPEN_MASK) && defined(_USART_ROUTEPEN_CTSPEN_MASK) + usart->ROUTEPEN &= ~(_USART_ROUTEPEN_RTSPEN_MASK | _USART_ROUTEPEN_CTSPEN_MASK); + usart->ROUTEPEN |= init->hwFlowControl; + +#elif defined(USART_CTRLX_CTSEN) + if ((init->hwFlowControl == usartHwFlowControlRts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { +#if USART_COUNT > 1 + GPIO->USARTROUTE_SET[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_SET[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } else { +#if USART_COUNT > 1 + GPIO->USARTROUTE_CLR[USART_NUM(usart)].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#else + //! @todo cleanup when ADM is updated to have USART_NUM macros + GPIO->USARTROUTE_CLR[0].ROUTEEN = GPIO_USART_ROUTEEN_RTSPEN; +#endif + } + + if ((init->hwFlowControl == usartHwFlowControlCts) + || (init->hwFlowControl == usartHwFlowControlCtsAndRts)) { + usart->CTRLX_SET = USART_CTRLX_CTSEN; + } else { + usart->CTRLX_CLR = USART_CTRLX_CTSEN; + } +#endif + + /* Finally, enable (as specified). */ + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for synchronous mode. + * + * @details + * This function will configure basic settings to operate in + * synchronous mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL register. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure basic async setup. + ******************************************************************************/ +void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) ); + + /* Initialize USART registers to hardware reset state. */ + USART_Reset(usart); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; +#endif + + /* Set bits for synchronous mode. */ + usart->CTRL |= (USART_CTRL_SYNC) + | (uint32_t)init->clockMode + | (init->msbf ? USART_CTRL_MSBF : 0); + +#if defined(_USART_CTRL_AUTOTX_MASK) + usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0; +#endif + +#if !defined(_EFM32_GECKO_FAMILY) + if (init->prsRxEnable) { + prsRxInput(usart, init->prsRxCh); + } +#endif + + /* Configure databits, leave stopbits and parity at reset default (not used). */ + usart->FRAME = (uint32_t)init->databits + | USART_FRAME_STOPBITS_DEFAULT + | USART_FRAME_PARITY_DEFAULT; + + /* Configure the baudrate. */ + USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate); + + /* Finally, enable (as specified). */ + if (init->master) { + usart->CMD = USART_CMD_MASTEREN; + } + + if (init->autoCsEnable) { + usart->CTRL |= USART_CTRL_AUTOCS; + } + if (init->csInv) { + usart->CTRL |= USART_CTRL_CSINV; + } +#if defined(_USART_TIMING_CSHOLD_MASK) + usart->TIMING = (((uint32_t)init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT) + & _USART_TIMING_CSHOLD_MASK) + | (((uint32_t)init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT) + & _USART_TIMING_CSSETUP_MASK); +#endif + + usart->CMD = (uint32_t)init->enable; +} + +/***************************************************************************//** + * @brief + * Initialize USART for asynchronous IrDA mode. + * + * @details + * This function will configure basic settings to operate in + * asynchronous IrDA mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and IRCTRL + * registers. + * + * Notice that pins used by the USART/UART module must be properly configured + * by the user explicitly for the USART/UART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] init + * A pointer to the initialization structure used to configure async IrDA setup. + * + * @note + * Not all USART instances support IrDA. See the data sheet for your device. + * + ******************************************************************************/ +void USARTn_InitIrDA(USART_TypeDef *usart, const USART_InitIrDA_TypeDef *init) +{ + EFM_ASSERT(USART_IRDA_VALID(usart)); + + /* Initialize USART as an async device. */ + USART_InitAsync(usart, &(init->async)); + + /* Set IrDA modulation to RZI (return-to-zero-inverted). */ + usart->CTRL |= USART_CTRL_TXINV; + + /* Invert the Rx signal before the demodulator if enabled. */ + if (init->irRxInv) { + usart->CTRL |= USART_CTRL_RXINV; + } + + /* Configure IrDA. */ + usart->IRCTRL = (uint32_t)init->irPw + | ((init->irFilt ? 1UL : 0UL) << _USART_IRCTRL_IRFILT_SHIFT); + +#if defined(USART_IRCTRL_IRPRSEN) + if (init->irPrsEn) { + prsIrInput(usart, init->irPrsSel); + } +#endif + + /* Enable IrDA. */ + usart->IRCTRL |= USART_IRCTRL_IREN; +} + +#if defined(_USART_I2SCTRL_MASK) +/***************************************************************************//** + * @brief + * Initialize USART for I2S mode. + * + * @details + * This function will configure basic settings to operate in I2S + * mode. + * + * A special control setup not covered by this function must be done after + * using this function by direct modification of the CTRL and I2SCTRL + * registers. + * + * Notice that pins used by the USART module must be properly configured + * by the user explicitly for the USART to work as intended. + * (When configuring pins, remember to consider the sequence of + * configuration to avoid unintended pulses/glitches on output + * pins.) + * + * @param[in] usart + * A pointer to the USART peripheral register block. (UART does not support this + * mode.) + * + * @param[in] init + * A pointer to the initialization structure used to configure the basic I2S setup. + * + * @note + * This function does not apply to all USART's. See the chip Reference Manual. + * + ******************************************************************************/ +void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init) +{ + USART_Enable_TypeDef enable; + + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_I2S_VALID(usart)); + + /* Override the enable setting. */ + enable = init->sync.enable; + init->sync.enable = usartDisable; + + /* Initialize USART as a sync device. */ + USART_InitSync(usart, &init->sync); + + /* Configure and enable I2CCTRL register according to the selected mode. */ + usart->I2SCTRL = (uint32_t)init->format + | (uint32_t)init->justify + | (init->delay ? USART_I2SCTRL_DELAY : 0) + | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0) + | (init->mono ? USART_I2SCTRL_MONO : 0) + | USART_I2SCTRL_EN; + + if (enable != usartDisable) { + USART_Enable(usart, enable); + } +} +#endif + +/***************************************************************************//** + * @brief + * Initialize the automatic transmissions using PRS channel as a trigger. + * @note + * Initialize USART with USART_Init() before setting up the PRS configuration. + * + * @param[in] usart + * A pointer to USART to configure. + * + * @param[in] init + * A pointer to the initialization structure. + ******************************************************************************/ +void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init) +{ + uint32_t trigctrl; + + prsTriggerInput(usart, init->prsTriggerChannel); + /* Clear values that will be reconfigured. */ + trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK + | _USART_TRIGCTRL_TXTEN_MASK +#if defined(USART_TRIGCTRL_AUTOTXTEN) + | _USART_TRIGCTRL_AUTOTXTEN_MASK +#endif + ); + +#if defined(USART_TRIGCTRL_AUTOTXTEN) + if (init->autoTxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_AUTOTXTEN; + } +#endif + if (init->txTriggerEnable) { + trigctrl |= USART_TRIGCTRL_TXTEN; + } + if (init->rxTriggerEnable) { + trigctrl |= USART_TRIGCTRL_RXTEN; + } + usart->TRIGCTRL = trigctrl; +} + +/***************************************************************************//** + * @brief + * Reset USART/UART to the same state that it was in after a hardware reset. + * + * @param[in] usart + * A pointer to USART/UART peripheral register block. + ******************************************************************************/ +void USART_Reset(USART_TypeDef *usart) +{ + /* Make sure the module exists on the selected chip. */ + EFM_ASSERT(USART_REF_VALID(usart) + || USARTRF_REF_VALID(usart) + || UART_REF_VALID(usart) ); + +#if defined(USART_EN_EN) + usart->EN_SET = USART_EN_EN; + /* Make sure disabled first, before resetting other registers. */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->CTRLX = _USART_CTRLX_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IF_CLR = _USART_IF_MASK; + usart->TIMING = _USART_TIMING_RESETVALUE; + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } + usart->EN_CLR = USART_EN_EN; + +#else + /* Make sure disabled first, before resetting other registers */ + usart->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS + | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX + | USART_CMD_CLEARRX; + + usart->CTRL = _USART_CTRL_RESETVALUE; + usart->FRAME = _USART_FRAME_RESETVALUE; + usart->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE; + usart->CLKDIV = _USART_CLKDIV_RESETVALUE; + usart->IEN = _USART_IEN_RESETVALUE; + usart->IFC = _USART_IFC_MASK; +#if defined(_USART_TIMING_MASK) + usart->TIMING = _USART_TIMING_RESETVALUE; +#endif +#if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK) + usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE; + usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE; + usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE; +#else + usart->ROUTE = _USART_ROUTE_RESETVALUE; +#endif + + if (USART_IRDA_VALID(usart)) { + usart->IRCTRL = _USART_IRCTRL_RESETVALUE; + } + +#if defined(_USART_INPUT_RESETVALUE) + usart->INPUT = _USART_INPUT_RESETVALUE; +#endif + +#if defined(_USART_I2SCTRL_RESETVALUE) + if (USART_I2S_VALID(usart)) { + usart->I2SCTRL = _USART_I2SCTRL_RESETVALUE; + } +#endif +#endif +} + +/***************************************************************************//** + * @brief + * Receive one 4-8 bit frame, (or part of 10-16 bit frame). + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-8 bits. See @ref USART_RxExt() for reception of + * 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataGet() to read the RXDATA + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_Rx(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Receive two 4-8 bit frames or one 10-16 bit frame. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits. See @ref USART_RxDoubleExt() for + * reception of two 9 bit frames. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleGet() to read the RXDOUBLE + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxDouble(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return (uint16_t)usart->RXDOUBLE; +} + +/***************************************************************************//** + * @brief + * Receive two 4-9 bit frames, or one 10-16 bit frame with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 10-16 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDoubleXGet() to read the RXDOUBLEX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint32_t USART_RxDoubleExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXFULL)) { + } + + return usart->RXDOUBLEX; +} + +/***************************************************************************//** + * @brief + * Receive one 4-9 bit frame (or part of 10-16 bit frame) with extended + * information. + * + * @details + * This function is normally used to receive one frame when operating with + * frame length 4-9 bits and additional RX status information is required. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is empty until data is received. + * Alternatively, the user can explicitly check whether data is available. + * If data is available, call @ref USART_RxDataXGet() to read the RXDATAX + * register directly. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @return + * Data received. + ******************************************************************************/ +uint16_t USART_RxExt(USART_TypeDef *usart) +{ + while (!(usart->STATUS & USART_STATUS_RXDATAV)) { + } + + return (uint16_t)usart->RXDATAX; +} + +/***************************************************************************//** + * @brief + * Perform one 8 bit frame SPI transfer. + * + * @note + * This function will stall if the transmit buffer is full. When a transmit + * buffer becomes available, data is written and the function will wait until + * data is fully transmitted. The SPI return value is then read out and + * returned. + * + * @param[in] usart + * A pointer to the USART peripheral register block. + * + * @param[in] data + * Data to transmit. + * + * @return + * Data received. + ******************************************************************************/ +uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data) +{ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; + while (!(usart->STATUS & USART_STATUS_TXC)) { + } + return (uint8_t)usart->RXDATA; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * @p data are transmitted. If the frame length is 9, 8 bits are transmitted from + * @p data and one bit as specified by CTRL register, BIT8DV field. + * See USART_TxExt() for transmitting 9 bit frame with full control of + * all 9 bits. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit. See details above for more information. + ******************************************************************************/ +void USART_Tx(USART_TypeDef *usart, uint8_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATA = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame. + * + * @details + * Depending on the frame length configuration, 4-8 (least significant) bits from + * each byte in @p data are transmitted. If frame length is 9, 8 bits are + * transmitted from each byte in @p data adding one bit as specified by the CTRL + * register, BIT8DV field, to each byte. See USART_TxDoubleExt() + * for transmitting two 9 bit frames with full control of all 9 bits. + * + * If the frame length is 10-16, 10-16 (least significant) bits from @p data + * are transmitted. + * + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit, the least significant byte holds the frame transmitted + * first. See details above for more info. + ******************************************************************************/ +void USART_TxDouble(USART_TypeDef *usart, uint16_t data) +{ + /* Check that transmit buffer is empty */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLE = (uint32_t)data; +} + +/***************************************************************************//** + * @brief + * Transmit two 4-9 bit frames or one 10-16 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Contains two 16 bit words + * concatenated. Least significant word holds the frame transmitted first. If the frame + * length is 4-9, two frames with 4-9 least significant bits from each 16 bit + * word are transmitted. + * @par + * If the frame length is 10-16 bits, 8 data bits are taken from the least + * significant 16 bit word and the remaining bits from the other 16 bit word. + * @par + * Additional control bits are available as documented in the reference + * manual (set to 0 if not used). For 10-16 bit frame length, these control + * bits are taken from the most significant 16 bit word. + ******************************************************************************/ +void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data) +{ + /* Check that transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDOUBLEX = data; +} + +/***************************************************************************//** + * @brief + * Transmit one 4-9 bit frame with extended control. + * + * @details + * Notice that possible parity/stop bits in asynchronous mode are not + * considered part of a specified frame bit length. + * + * @note + * This function will stall if the buffer is full until the buffer becomes available. + * + * @param[in] usart + * A pointer to the USART/UART peripheral register block. + * + * @param[in] data + * Data to transmit with extended control. Least significant bit contains + * frame bits. Additional control bits are available as documented in + * the reference manual (set to 0 if not used). + ******************************************************************************/ +void USART_TxExt(USART_TypeDef *usart, uint16_t data) +{ + /* Check that the transmit buffer is empty. */ + while (!(usart->STATUS & USART_STATUS_TXBL)) { + } + usart->TXDATAX = (uint32_t)data; +} + +/** @} (end addtogroup usart) */ +#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c index 4fa0346..859b4b7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/emlib/src/em_wdog.c @@ -1,355 +1,355 @@ -/***************************************************************************//** - * @file - * @brief Watchdog (WDOG) peripheral API - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_wdog.h" -#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) - -#include "em_bus.h" -#include "em_core.h" - -/***************************************************************************//** - * @addtogroup wdog WDOG - Watchdog - * @brief Watchdog (WDOG) Peripheral API - * @details - * This module contains functions to control the WDOG peripheral of Silicon - * Labs 32-bit MCUs and SoCs. The WDOG resets the system in case of a fault - * condition. - * @{ - ******************************************************************************/ - -/** In some scenarioes when the watchdog is disabled the synchronization - * register might be set and not be cleared until the watchdog is enabled - * again. This will happen when for instance some watchdog register is modified - * while the watchdog clock is disabled. In these scenarioes we need to make - * sure that the software does not wait forever. */ -#define WDOG_SYNC_TIMEOUT 30000 - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Enable/disable the watchdog timer. - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * A pointer to the WDOG peripheral register block. - * - * @param[in] enable - * True to enable Watchdog, false to disable. Watchdog cannot be disabled if - * it's been locked. - ******************************************************************************/ -void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable) -{ - // SYNCBUSY may stall when locked. -#if defined(_WDOG_STATUS_MASK) - if ((wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED) { - return; - } -#else - if (wdog->CTRL & WDOG_CTRL_LOCK) { - return; - } -#endif - -#if defined(_WDOG_EN_MASK) - if (!enable) { - while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { - } - wdog->EN_CLR = WDOG_EN_EN; -#if defined(_WDOG_EN_DISABLING_MASK) - while (wdog->EN & _WDOG_EN_DISABLING_MASK) { - } -#endif - } else { - wdog->EN_SET = WDOG_EN_EN; - } -#else - // Wait for previous operations/modifications to complete - int i = 0; - while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) - && (i < WDOG_SYNC_TIMEOUT)) { - i++; - } - - bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); - - // Make sure to only write to the CTRL register if we are changing mode - if (wdogState != enable) { - BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); - } -#endif -} - -/***************************************************************************//** - * @brief - * Feed WDOG. - * - * @details - * When WDOG is activated, it must be fed (i.e., clearing the counter) - * before it reaches the defined timeout period. Otherwise, WDOG - * will generate a reset. - * - * @note - * Note that WDOG is an asynchronous peripheral and when calling the - * WDOGn_Feed() function the hardware starts the process of clearing the - * counter. This process takes some time before it completes depending on the - * selected oscillator (up to 4 peripheral clock cycles). When using the - * ULFRCO for instance as the oscillator the watchdog runs on a 1 kHz clock - * and a watchdog clear operation might take up to 4 ms. - * - * If the device enters EM2 or EM3 while a command is in progress then that - * command will be aborted. An application can use @ref WDOGn_SyncWait() - * to wait for a command to complete. - * - * @param[in] wdog - * A pointer to the WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Feed(WDOG_TypeDef *wdog) -{ -#if (_SILICON_LABS_32B_SERIES < 2) - - // WDOG should not be fed while it is disabled. - if (!(wdog->CTRL & WDOG_CTRL_EN)) { - return; - } - - // If a previous clearing is synchronized to the LF domain, there - // is no point in waiting for it to complete before clearing over again. - // This avoids stalling the core in the typical use case where some idle loop - // keeps clearing WDOG. - if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { - return; - } - // Before writing to the WDOG_CMD register, make sure that - // any previous write to the WDOG_CTRL is complete. - while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { - } - - wdog->CMD = WDOG_CMD_CLEAR; - -#else // Series 2 devices - - CORE_DECLARE_IRQ_STATE; - - // WDOG should not be fed while it is disabled. - if ((wdog->EN & WDOG_EN_EN) == 0U) { - return; - } - - // We need an atomic section around the check for sync and the clear command - // because sending a clear command while a previous command is being synchronized - // will cause a BusFault. - CORE_ENTER_ATOMIC(); - if ((wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) == 0U) { - wdog->CMD = WDOG_CMD_CLEAR; - } - CORE_EXIT_ATOMIC(); - -#endif -} - -/***************************************************************************//** - * @brief - * Initialize WDOG (assuming the WDOG configuration has not been - * locked). - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * Pointer to the WDOG peripheral register block. - * - * @param[in] init - * The structure holding the WDOG configuration. A default setting - * #WDOG_INIT_DEFAULT is available for initialization. - ******************************************************************************/ -void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init) -{ -#if defined(_WDOG_CFG_MASK) - // Handle series-2 devices - - if (wdog->EN != 0U) { - while (wdog->SYNCBUSY != 0U) { - // Wait for any potential synchronization to finish - } - wdog->EN_CLR = WDOG_EN_EN; -#if defined(_WDOG_EN_DISABLING_MASK) - while (wdog->EN & _WDOG_EN_DISABLING_MASK) { - /* Wait for disabling to finish */ - } -#endif - } - - wdog->CFG = (init->debugRun ? WDOG_CFG_DEBUGRUN : 0U) - | (init->clrSrc ? WDOG_CFG_CLRSRC : 0U) -#if defined(_WDOG_CFG_EM1RUN_MASK) - | (init->em1Run ? WDOG_CFG_EM1RUN : 0U) -#endif - | (init->em2Run ? WDOG_CFG_EM2RUN : 0U) - | (init->em3Run ? WDOG_CFG_EM3RUN : 0U) - | (init->em4Block ? WDOG_CFG_EM4BLOCK : 0U) - | (init->prs0MissRstEn ? WDOG_CFG_PRS0MISSRSTEN : 0U) - | (init->prs1MissRstEn ? WDOG_CFG_PRS1MISSRSTEN : 0U) - | (init->resetDisable ? WDOG_CFG_WDOGRSTDIS : 0U) - | ((uint32_t)(init->warnSel) << _WDOG_CFG_WARNSEL_SHIFT) - | ((uint32_t)(init->winSel) << _WDOG_CFG_WINSEL_SHIFT) - | ((uint32_t)(init->perSel) << _WDOG_CFG_PERSEL_SHIFT); - - WDOGn_Enable(wdog, init->enable); - - if (init->lock) { - WDOGn_Lock(wdog); - } -#else - // Handle series-0 and series-1 devices - uint32_t setting; - - setting = (init->enable ? WDOG_CTRL_EN : 0U) - | (init->debugRun ? WDOG_CTRL_DEBUGRUN : 0U) -#if defined(_WDOG_CTRL_CLRSRC_MASK) - | (init->clrSrc ? WDOG_CTRL_CLRSRC : 0U) -#endif - | (init->em2Run ? WDOG_CTRL_EM2RUN : 0U) - | (init->em3Run ? WDOG_CTRL_EM3RUN : 0U) - | (init->em4Block ? WDOG_CTRL_EM4BLOCK : 0U) - | (init->swoscBlock ? WDOG_CTRL_SWOSCBLOCK : 0U) - | (init->lock ? WDOG_CTRL_LOCK : 0U) - | ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) - | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT); - -#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) - setting |= (init->resetDisable ? WDOG_CTRL_WDOGRSTDIS : 0U); -#endif -#if defined(_WDOG_CTRL_WARNSEL_MASK) - setting |= ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT); -#endif -#if defined(_WDOG_CTRL_WINSEL_MASK) - setting |= ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT); -#endif - - // Wait for previous operations/modifications to complete - int i = 0; - while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) - && (i < WDOG_SYNC_TIMEOUT)) { - i++; - } - wdog->CTRL = setting; -#endif -} - -/***************************************************************************//** - * @brief - * Lock the WDOG configuration. - * - * @details - * This prevents errors from overwriting the WDOG configuration, possibly - * disabling it. Only a reset can unlock the WDOG configuration once locked. - * - * If the LFRCO or LFXO clocks are used to clock WDOG, - * consider using the option of inhibiting those clocks to be disabled. - * See the WDOG_Enable() initialization structure. - * - * @note - * This function modifies the WDOG CTRL register which requires - * synchronization into the low-frequency domain. If this register is modified - * before a previous update to the same register has completed, this function - * will stall until the previous synchronization has completed. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Lock(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_LOCK_MASK) - wdog->LOCK = _WDOG_LOCK_LOCKKEY_LOCK; -#else - // Wait for any pending previous write operation to have been completed in - // the low-frequency domain. - while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { - } - - // Disable writing to the control register. - BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); -#endif -} - -/***************************************************************************//** - * @brief - * Wait for the WDOG to complete all synchronization of register changes - * and commands. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_SyncWait(WDOG_TypeDef *wdog) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - while ((wdog->EN != 0U) && (wdog->SYNCBUSY != 0U)) { - // Wait for synchronization to finish - } -#else - while (wdog->SYNCBUSY != 0U) { - // Wait for synchronization to finish - } -#endif -} - -/***************************************************************************//** - * @brief - * Unlock the WDOG configuration. - * - * @details - * Note that this function will have no effect on devices where a reset is - * the only way to unlock the watchdog. - * - * @param[in] wdog - * A pointer to WDOG peripheral register block. - ******************************************************************************/ -void WDOGn_Unlock(WDOG_TypeDef *wdog) -{ -#if defined(_WDOG_LOCK_MASK) - wdog->LOCK = _WDOG_LOCK_LOCKKEY_UNLOCK; -#else - (void) wdog; -#endif -} - -/** @} (end addtogroup wdog) */ -#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ +/***************************************************************************//** + * @file + * @brief Watchdog (WDOG) peripheral API + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_wdog.h" +#if defined(WDOG_COUNT) && (WDOG_COUNT > 0) + +#include "em_bus.h" +#include "em_core.h" + +/***************************************************************************//** + * @addtogroup wdog WDOG - Watchdog + * @brief Watchdog (WDOG) Peripheral API + * @details + * This module contains functions to control the WDOG peripheral of Silicon + * Labs 32-bit MCUs and SoCs. The WDOG resets the system in case of a fault + * condition. + * @{ + ******************************************************************************/ + +/** In some scenarioes when the watchdog is disabled the synchronization + * register might be set and not be cleared until the watchdog is enabled + * again. This will happen when for instance some watchdog register is modified + * while the watchdog clock is disabled. In these scenarioes we need to make + * sure that the software does not wait forever. */ +#define WDOG_SYNC_TIMEOUT 30000 + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Enable/disable the watchdog timer. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + * + * @param[in] enable + * True to enable Watchdog, false to disable. Watchdog cannot be disabled if + * it's been locked. + ******************************************************************************/ +void WDOGn_Enable(WDOG_TypeDef *wdog, bool enable) +{ + // SYNCBUSY may stall when locked. +#if defined(_WDOG_STATUS_MASK) + if ((wdog->STATUS & _WDOG_STATUS_LOCK_MASK) == WDOG_STATUS_LOCK_LOCKED) { + return; + } +#else + if (wdog->CTRL & WDOG_CTRL_LOCK) { + return; + } +#endif + +#if defined(_WDOG_EN_MASK) + if (!enable) { + while (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + } +#endif + } else { + wdog->EN_SET = WDOG_EN_EN; + } +#else + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + + bool wdogState = ((wdog->CTRL & _WDOG_CTRL_EN_MASK) != 0U); + + // Make sure to only write to the CTRL register if we are changing mode + if (wdogState != enable) { + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_EN_SHIFT, enable); + } +#endif +} + +/***************************************************************************//** + * @brief + * Feed WDOG. + * + * @details + * When WDOG is activated, it must be fed (i.e., clearing the counter) + * before it reaches the defined timeout period. Otherwise, WDOG + * will generate a reset. + * + * @note + * Note that WDOG is an asynchronous peripheral and when calling the + * WDOGn_Feed() function the hardware starts the process of clearing the + * counter. This process takes some time before it completes depending on the + * selected oscillator (up to 4 peripheral clock cycles). When using the + * ULFRCO for instance as the oscillator the watchdog runs on a 1 kHz clock + * and a watchdog clear operation might take up to 4 ms. + * + * If the device enters EM2 or EM3 while a command is in progress then that + * command will be aborted. An application can use @ref WDOGn_SyncWait() + * to wait for a command to complete. + * + * @param[in] wdog + * A pointer to the WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Feed(WDOG_TypeDef *wdog) +{ +#if (_SILICON_LABS_32B_SERIES < 2) + + // WDOG should not be fed while it is disabled. + if (!(wdog->CTRL & WDOG_CTRL_EN)) { + return; + } + + // If a previous clearing is synchronized to the LF domain, there + // is no point in waiting for it to complete before clearing over again. + // This avoids stalling the core in the typical use case where some idle loop + // keeps clearing WDOG. + if (wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) { + return; + } + // Before writing to the WDOG_CMD register, make sure that + // any previous write to the WDOG_CTRL is complete. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + wdog->CMD = WDOG_CMD_CLEAR; + +#else // Series 2 devices + + CORE_DECLARE_IRQ_STATE; + + // WDOG should not be fed while it is disabled. + if ((wdog->EN & WDOG_EN_EN) == 0U) { + return; + } + + // We need an atomic section around the check for sync and the clear command + // because sending a clear command while a previous command is being synchronized + // will cause a BusFault. + CORE_ENTER_ATOMIC(); + if ((wdog->SYNCBUSY & WDOG_SYNCBUSY_CMD) == 0U) { + wdog->CMD = WDOG_CMD_CLEAR; + } + CORE_EXIT_ATOMIC(); + +#endif +} + +/***************************************************************************//** + * @brief + * Initialize WDOG (assuming the WDOG configuration has not been + * locked). + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * Pointer to the WDOG peripheral register block. + * + * @param[in] init + * The structure holding the WDOG configuration. A default setting + * #WDOG_INIT_DEFAULT is available for initialization. + ******************************************************************************/ +void WDOGn_Init(WDOG_TypeDef *wdog, const WDOG_Init_TypeDef *init) +{ +#if defined(_WDOG_CFG_MASK) + // Handle series-2 devices + + if (wdog->EN != 0U) { + while (wdog->SYNCBUSY != 0U) { + // Wait for any potential synchronization to finish + } + wdog->EN_CLR = WDOG_EN_EN; +#if defined(_WDOG_EN_DISABLING_MASK) + while (wdog->EN & _WDOG_EN_DISABLING_MASK) { + /* Wait for disabling to finish */ + } +#endif + } + + wdog->CFG = (init->debugRun ? WDOG_CFG_DEBUGRUN : 0U) + | (init->clrSrc ? WDOG_CFG_CLRSRC : 0U) +#if defined(_WDOG_CFG_EM1RUN_MASK) + | (init->em1Run ? WDOG_CFG_EM1RUN : 0U) +#endif + | (init->em2Run ? WDOG_CFG_EM2RUN : 0U) + | (init->em3Run ? WDOG_CFG_EM3RUN : 0U) + | (init->em4Block ? WDOG_CFG_EM4BLOCK : 0U) + | (init->prs0MissRstEn ? WDOG_CFG_PRS0MISSRSTEN : 0U) + | (init->prs1MissRstEn ? WDOG_CFG_PRS1MISSRSTEN : 0U) + | (init->resetDisable ? WDOG_CFG_WDOGRSTDIS : 0U) + | ((uint32_t)(init->warnSel) << _WDOG_CFG_WARNSEL_SHIFT) + | ((uint32_t)(init->winSel) << _WDOG_CFG_WINSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CFG_PERSEL_SHIFT); + + WDOGn_Enable(wdog, init->enable); + + if (init->lock) { + WDOGn_Lock(wdog); + } +#else + // Handle series-0 and series-1 devices + uint32_t setting; + + setting = (init->enable ? WDOG_CTRL_EN : 0U) + | (init->debugRun ? WDOG_CTRL_DEBUGRUN : 0U) +#if defined(_WDOG_CTRL_CLRSRC_MASK) + | (init->clrSrc ? WDOG_CTRL_CLRSRC : 0U) +#endif + | (init->em2Run ? WDOG_CTRL_EM2RUN : 0U) + | (init->em3Run ? WDOG_CTRL_EM3RUN : 0U) + | (init->em4Block ? WDOG_CTRL_EM4BLOCK : 0U) + | (init->swoscBlock ? WDOG_CTRL_SWOSCBLOCK : 0U) + | (init->lock ? WDOG_CTRL_LOCK : 0U) + | ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) + | ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT); + +#if defined(_WDOG_CTRL_WDOGRSTDIS_MASK) + setting |= (init->resetDisable ? WDOG_CTRL_WDOGRSTDIS : 0U); +#endif +#if defined(_WDOG_CTRL_WARNSEL_MASK) + setting |= ((uint32_t)(init->warnSel) << _WDOG_CTRL_WARNSEL_SHIFT); +#endif +#if defined(_WDOG_CTRL_WINSEL_MASK) + setting |= ((uint32_t)(init->winSel) << _WDOG_CTRL_WINSEL_SHIFT); +#endif + + // Wait for previous operations/modifications to complete + int i = 0; + while (((wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U) + && (i < WDOG_SYNC_TIMEOUT)) { + i++; + } + wdog->CTRL = setting; +#endif +} + +/***************************************************************************//** + * @brief + * Lock the WDOG configuration. + * + * @details + * This prevents errors from overwriting the WDOG configuration, possibly + * disabling it. Only a reset can unlock the WDOG configuration once locked. + * + * If the LFRCO or LFXO clocks are used to clock WDOG, + * consider using the option of inhibiting those clocks to be disabled. + * See the WDOG_Enable() initialization structure. + * + * @note + * This function modifies the WDOG CTRL register which requires + * synchronization into the low-frequency domain. If this register is modified + * before a previous update to the same register has completed, this function + * will stall until the previous synchronization has completed. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Lock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_LOCK; +#else + // Wait for any pending previous write operation to have been completed in + // the low-frequency domain. + while ( (wdog->SYNCBUSY & WDOG_SYNCBUSY_CTRL) != 0U ) { + } + + // Disable writing to the control register. + BUS_RegBitWrite(&wdog->CTRL, _WDOG_CTRL_LOCK_SHIFT, 1); +#endif +} + +/***************************************************************************//** + * @brief + * Wait for the WDOG to complete all synchronization of register changes + * and commands. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_SyncWait(WDOG_TypeDef *wdog) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + while ((wdog->EN != 0U) && (wdog->SYNCBUSY != 0U)) { + // Wait for synchronization to finish + } +#else + while (wdog->SYNCBUSY != 0U) { + // Wait for synchronization to finish + } +#endif +} + +/***************************************************************************//** + * @brief + * Unlock the WDOG configuration. + * + * @details + * Note that this function will have no effect on devices where a reset is + * the only way to unlock the watchdog. + * + * @param[in] wdog + * A pointer to WDOG peripheral register block. + ******************************************************************************/ +void WDOGn_Unlock(WDOG_TypeDef *wdog) +{ +#if defined(_WDOG_LOCK_MASK) + wdog->LOCK = _WDOG_LOCK_LOCKKEY_UNLOCK; +#else + (void) wdog; +#endif +} + +/** @} (end addtogroup wdog) */ +#endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h index 392e044..95fb973 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/chip/efr32/efr32xg2x/rail_chip_specific.h @@ -1,754 +1,754 @@ -/***************************************************************************//** - * @file - * @brief This file contains the type definitions for efr32xg2x chip-specific - * aspects of RAIL. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifdef SLI_LIBRARY_BUILD - -// This file should not be included when doing SLI_LIBRARY_BUILDs - -#else//!SLI_LIBRARY_BUILD - -#ifndef __RAIL_CHIP_SPECIFIC_H_ -#if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS) -#warning rail_chip_specific.h should only be included by rail_types.h -#include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h -#else // __RAIL_TYPES_H__ -/// Include guard -#define __RAIL_CHIP_SPECIFIC_H_ - -#include "rail_features.h" -#ifdef RAIL_INTERNAL_BUILD -#include "rail_chip_specific_internal.h" -#endif - -#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) -// Copied from rail_types.h to satisfy doxygen build. -/// The RAIL library does not use enumerations because the ARM EABI leaves their -/// size ambiguous, which causes problems if the application is built -/// with different flags than the library. Instead, uint8_t typedefs -/// are used in compiled code for all enumerations. For documentation purposes, this is -/// converted to an actual enumeration since it's much easier to read in Doxygen. -#define RAIL_ENUM(name) enum name -/// This macro is a more generic version of the \ref RAIL_ENUM() macro that -/// allows the size of the type to be overridden instead of forcing the use of -/// a uint8_t. See \ref RAIL_ENUM() for more information. -#define RAIL_ENUM_GENERIC(name, type) enum name -#endif //(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup General_EFR32XG2 EFR32xG2 - * @{ - * @brief EFR32xG2-specific initialization data types - * @ingroup General - */ - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES - * @brief The EFR32XG21 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 560 - -/** - * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES - * @brief The EFR32XG22 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 568 - -/** - * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES - * @brief The EFR32XG23 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 584 - -/** - * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES - * @brief The EFR32XG24 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 592 - -/** - * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES - * @brief The EFR32XG25 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 592 - -/** - * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES - * @brief The EFR32XG27 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG27_STATE_BUFFER_BYTES 568 - -/** - * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES - * @brief The EFR32XG28 series size needed for - * \ref RAIL_StateBufferEntry_t::bufferBytes. - */ -#define RAIL_EFR32XG28_STATE_BUFFER_BYTES 584 - -#ifndef RAIL_STATE_BUFFER_BYTES -/** - * @def RAIL_STATE_BUFFER_BYTES - * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes - * on this platform for this radio. This compile-time size may be slightly - * larger than what \ref RAIL_GetStateBufferSize() determines at run-time. - */ -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES -#else -#define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen -#error "Unsupported platform!" -#endif -#endif //#ifndef RAIL_STATE_BUFFER_BYTES - -/** - * @def RAIL_SEQ_IMAGE_1 - * @brief A macro for the first sequencer image. - */ -#define RAIL_SEQ_IMAGE_1 1 - -/** - * @def RAIL_SEQ_IMAGE_2 - * @brief A macro for the second sequencer image. - */ -#define RAIL_SEQ_IMAGE_2 2 - -#ifndef RAIL_INTERNAL_BUILD -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -/** - * @def RAIL_SEQ_IMAGE_PA_10_DBM - * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs - * with a 10 dBm PA. - */ -#define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1 - -/** - * @def RAIL_SEQ_IMAGE_PA_20_DBM - * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs - * with a 20 dBm PA. - */ -#define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2 - -/** - * @def RAIL_SEQ_IMAGE_COUNT - * @brief A macro for the total number of sequencer images supported on the - * platform. - */ -#define RAIL_SEQ_IMAGE_COUNT 2 - -#else //(_SILICON_LABS_32B_SERIES_2_CONFIG != 4) - -/** - * @def RAIL_SEQ_IMAGE_DEFAULT - * @brief A chip-specific macro for the default sequencer image on platforms - * that support only one sequencer image. - */ -#define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1 - -/** - * @def RAIL_SEQ_IMAGE_COUNT - * @brief A macro for the total number of sequencer images supported on the - * platform. - */ -#define RAIL_SEQ_IMAGE_COUNT 1 -#endif //(_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -#endif //RAIL_INTERNAL_BUILD - -/** - * @struct RAIL_RffpllConfig_t - * @brief Stores information relevant to the Radio-Friendly Frequency - * Phase-Locked Loop (RFFPLL) for the PHY configuration currently loaded in - * memory. - */ -typedef struct { - uint32_t dividers; // Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values - uint32_t radioFreqHz; // Radio clock frequency in Hz - uint32_t sysclkFreqHz; // System clock frequency in Hz -} RAIL_RffpllConfig_t; - -/** - * @def RAIL_RFFPLL_DIVIDERX_MASK - * @brief Bit mask for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERX_MASK 0x000000FFUL - -/** - * @def RAIL_RFFPLL_DIVIDERX_SHIFT - * @brief Shift value for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERX_SHIFT 0 - -/** - * @def RAIL_RFFPLL_DIVIDERY_MASK - * @brief Bit mask for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERY_MASK 0x0000FF00UL - -/** - * @def RAIL_RFFPLL_DIVIDERY_SHIFT - * @brief Shift value for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERY_SHIFT 8 - -/** - * @def RAIL_RFFPLL_DIVIDERN_MASK - * @brief Bit mask for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERN_MASK 0x00FF0000UL - -/** - * @def RAIL_RFFPLL_DIVIDERN_SHIFT - * @brief Shift value for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. - */ -#define RAIL_RFFPLL_DIVIDERN_SHIFT 16 - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group General_EFR32XG2 - -// ----------------------------------------------------------------------------- -// Multiprotocol -// ----------------------------------------------------------------------------- -/** - * @addtogroup Multiprotocol_EFR32 EFR32 - * @{ - * @brief EFR32-specific multiprotocol support defines - * @ingroup Multiprotocol - */ - -/** - * @def TRANSITION_TIME_US - * @brief Time it takes to take care of protocol switching. - */ -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1 -// XG22 + devices -#define TRANSITION_TIME_US 510 -#else -// XG21 -#define TRANSITION_TIME_US 500 -#endif - -/** @} */ // end of group Multiprotocol_EFR32 - -// ----------------------------------------------------------------------------- -// Calibration -// ----------------------------------------------------------------------------- -/** - * @addtogroup Calibration_EFR32XG2X EFR32XG2X - * @{ - * @brief EFR32XG2X-specific Calibrations - * @ingroup Calibration - */ - -/** - * @def RAIL_RF_PATHS_2P4GIG - * @brief Indicates the number of 2.4 GHz RF Paths suppported - */ -#ifndef RAIL_RF_PATHS_2P4GIG -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) -#define RAIL_RF_PATHS_2P4GIG 2 -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_RF_PATHS_2P4GIG 1 -#else -#define RAIL_RF_PATHS_2P4GIG 0 -#endif - -/** - * @def RAIL_RF_PATHS_SUBGIG - * @brief Indicates the number of sub-GHz RF Paths supported - */ -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 -#define RAIL_RF_PATHS_SUBGIG 2 -#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 -#define RAIL_RF_PATHS_SUBGIG 2 -#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 -#define RAIL_RF_PATHS_SUBGIG 1 -#else -#define RAIL_RF_PATHS_SUBGIG 0 -#endif -#endif //#ifndef RAIL_RF_PATHS_2P4GIG - -/** - * @def RAIL_RF_PATHS - * @brief Indicates the number of RF Paths supported - */ -#define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG) - -#if (RAIL_RF_PATHS > RAIL_MAX_RF_PATHS) -#error "Update rail_types.h RAIL_MAX_RF_PATHS" -#endif - -/** - * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS - * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths - * Needed for backwards compatibility. - */ -#if RAIL_RF_PATHS > 1 -#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1 -#else -#ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen -#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 -#endif //DOXYGEN_SHOULD_SKIP_THIS -#endif - -/** - * @struct RAIL_ChannelConfigEntryAttr - * @brief A channel configuration entry attribute structure. Items listed - * are designed to be altered and updated during run-time. - */ -struct RAIL_ChannelConfigEntryAttr { - /** IR calibration attributes specific to each channel configuration entry. */ - #if RAIL_SUPPORTS_OFDM_PA - RAIL_IrCalValues_t calValues; - #else//!RAIL_SUPPORTS_OFDM_PA - RAIL_RxIrCalValues_t calValues; - #endif//RAIL_SUPPORTS_OFDM_PA -}; - -/** @} */ // end of group Calibration_EFR32 - -// ----------------------------------------------------------------------------- -// Transmit -// ----------------------------------------------------------------------------- -/** - * @addtogroup PA_EFR32XG2X EFR32XG2X - * @{ - * @ingroup PA - * @brief Types specific to the EFR32 for dealing with the on-chip PAs. - */ - -#ifndef RAIL_TX_POWER_LEVEL_2P4_HP_MAX -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (90U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (1U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (64U) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - * EFR32XG24: capable of 20dBm max output power has max powerlevel:180 - * EFR32XG24: capable of 10dBm max output power has max powerlevel:90 - */ -#if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) -#else -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (90U) -#endif -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (127U) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) -#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) -#else //efr32xg23 -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_HP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LLP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LLP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_2P4_LLP mode. - */ -#define RAIL_TX_POWER_LEVEL_2P4_LLP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) -#endif //_SILICON_LABS_32B_SERIES_2_CONFIG -#endif //RAIL_TX_POWER_LEVEL_2P4_HP_MAX -#if RAIL_FEAT_SUBGIG_RADIO -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8 -#ifndef RAIL_SUBGIG_MAX -#define RAIL_SUBGIG_MAX 240U -#endif -#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 -#define RAIL_SUBGIG_MAX 79U -#endif -#define RAIL_SUBGIG_MIN 1U - -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_MP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_LP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN) -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. - */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (RAIL_SUBGIG_MIN) -#endif //RAIL_FEAT_SUBGIG_RADIO - -#if RAIL_SUPPORTS_OFDM_PA -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 5 -#define RAIL_OFDM_PA_MAX 204U -#define RAIL_OFDM_PA_EFF_MAX 204U -#define RAIL_OFDM_PA_MULT 5U -#define RAIL_OFDM_PA_MIN 0U -#define RAIL_OFDM_PA_EFF_MIN 0U -#endif -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_OFDM_PA mode. - */ -#define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_OFDM_PA mode. - */ -#define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN) -#if RAIL_SUPPORTS_EFF -/** - * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode. - */ -#define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MAX (RAIL_OFDM_PA_EFF_MAX) -/** - * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref - * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode. - */ -#define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MIN (RAIL_OFDM_PA_EFF_MIN) -#endif -#endif //RAIL_SUPPORTS_OFDM_PA - -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_MP_MAX RAIL_TX_POWER_LEVEL_2P4_MP_MAX -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_MP_MIN RAIL_TX_POWER_LEVEL_2P4_MP_MIN -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX -/** Backwards compatability define */ -#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN - -/** - * The number of PA's on this chip. (Including Virtual PAs) - */ -#ifndef RAIL_NUM_PA -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_NUM_PA (2U) -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) -#define RAIL_NUM_PA (4U) -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_NUM_PA (5U) -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_NUM_PA (4U) -#else -#define RAIL_NUM_PA (3U) -#endif -#endif //#ifndef RAIL_NUM_PA - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -// Only those supported per-platform are defined, for use with #ifdef in -// apps or librail code. -#if RAIL_SUPPORTS_2P4GHZ_BAND -#define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP) -#define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP) -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 -#define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP) -#define RAIL_TX_POWER_MODE_2P4_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_MP) -#endif//_SILICON_LABS_32B_SERIES_2_CONFIG == 1 -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) -#define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP) -#define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP) -#endif//((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) -#define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) -#define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST) -#endif//RAIL_SUPPORTS_2P4GHZ_BAND - -#if RAIL_SUPPORTS_SUBGHZ_BAND -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE -#define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) -#else//!RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE -#define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP) -#define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG) -#define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP) -#define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP) -#define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP) -#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE -#define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST) -#if RAIL_SUPPORTS_EFF -#define RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) -#endif//RAIL_SUPPORTS_EFF -#endif//RAIL_SUPPORTS_SUBGHZ_BAND -#if RAIL_SUPPORTS_OFDM_PA -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE -#define RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) -#define RAIL_TX_POWER_MODE_OFDM_PA ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA) -#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE -#if RAIL_SUPPORTS_EFF -#define RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) -#endif//RAIL_SUPPORTS_EFF -#endif//RAIL_SUPPORTS_OFDM_PA -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group PA_EFR32 - -/****************************************************************************** - * RX Channel Hopping - *****************************************************************************/ -/** - * @addtogroup Rx_Channel_Hopping RX Channel Hopping - * @{ - */ - -#if _SILICON_LABS_32B_SERIES_2_CONFIG == 8 -/// The static amount of memory needed per channel for channel hopping, measured -/// in 32 bit words, regardless of the size of radio configuration structures. -#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (65U) -#else -/// The static amount of memory needed per channel for channel hopping, measured -/// in 32 bit words, regardless of the size of radio configuration structures. -#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (56U) -#endif - -#if (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ - > RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE) -#error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE" -#endif - -/** @} */ // end of group Rx_Channel_Hopping - -/** - * @addtogroup Sleep - * @{ - */ - -/// Default PRS channel to use when configuring sleep -#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) - -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -/// Default RTCC channel to use when configuring sleep -#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U) -#else -/// Default RTCC channel to use when configuring sleep -#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) -#endif - -/// Default timer synchronization configuration -#define RAIL_TIMER_SYNC_DEFAULT { \ - RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \ - RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \ - RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \ -} - -/** @} */ // end of group Sleep - -/** - * @addtogroup State_Transitions_EFR32XG2X - * @{ - * @ingroup State_Transitions - */ - -/** - * @def RAIL_MINIMUM_TRANSITION_US - * @brief The minimum value for a consistent RAIL transition - * @note Transitions may need to be slower than this when using longer - * \ref RAIL_TxPowerConfig_t::rampTime values - */ -#define RAIL_MINIMUM_TRANSITION_US (100U) - -/** - * @def RAIL_MAXIMUM_TRANSITION_US - * @brief The maximum value for a consistent RAIL transition - */ -#define RAIL_MAXIMUM_TRANSITION_US (1000000U) - -/** @} */ // end of group State_Transitions_EFR32 - -#ifdef __cplusplus -} -#endif - -#endif //__RAIL_TYPES_H__ - -#endif //__RAIL_CHIP_SPECIFIC_H_ - -#endif // SLI_LIBRARY_BUILD +/***************************************************************************//** + * @file + * @brief This file contains the type definitions for efr32xg2x chip-specific + * aspects of RAIL. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifdef SLI_LIBRARY_BUILD + +// This file should not be included when doing SLI_LIBRARY_BUILDs + +#else//!SLI_LIBRARY_BUILD + +#ifndef __RAIL_CHIP_SPECIFIC_H_ +#if !defined(__RAIL_TYPES_H__) && !defined(DOXYGEN_SHOULD_SKIP_THIS) +#warning rail_chip_specific.h should only be included by rail_types.h +#include "rail_types.h" // Force rail_chip_specific.h only within rail_types.h +#else // __RAIL_TYPES_H__ +/// Include guard +#define __RAIL_CHIP_SPECIFIC_H_ + +#include "rail_features.h" +#ifdef RAIL_INTERNAL_BUILD +#include "rail_chip_specific_internal.h" +#endif + +#if (defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) +// Copied from rail_types.h to satisfy doxygen build. +/// The RAIL library does not use enumerations because the ARM EABI leaves their +/// size ambiguous, which causes problems if the application is built +/// with different flags than the library. Instead, uint8_t typedefs +/// are used in compiled code for all enumerations. For documentation purposes, this is +/// converted to an actual enumeration since it's much easier to read in Doxygen. +#define RAIL_ENUM(name) enum name +/// This macro is a more generic version of the \ref RAIL_ENUM() macro that +/// allows the size of the type to be overridden instead of forcing the use of +/// a uint8_t. See \ref RAIL_ENUM() for more information. +#define RAIL_ENUM_GENERIC(name, type) enum name +#endif //(defined(DOXYGEN_SHOULD_SKIP_THIS) && !defined(RAIL_ENUM)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup General_EFR32XG2 EFR32xG2 + * @{ + * @brief EFR32xG2-specific initialization data types + * @ingroup General + */ + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_EFR32XG21_STATE_BUFFER_BYTES + * @brief The EFR32XG21 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG21_STATE_BUFFER_BYTES 560 + +/** + * @def RAIL_EFR32XG22_STATE_BUFFER_BYTES + * @brief The EFR32XG22 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG22_STATE_BUFFER_BYTES 568 + +/** + * @def RAIL_EFR32XG23_STATE_BUFFER_BYTES + * @brief The EFR32XG23 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG23_STATE_BUFFER_BYTES 584 + +/** + * @def RAIL_EFR32XG24_STATE_BUFFER_BYTES + * @brief The EFR32XG24 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG24_STATE_BUFFER_BYTES 592 + +/** + * @def RAIL_EFR32XG25_STATE_BUFFER_BYTES + * @brief The EFR32XG25 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG25_STATE_BUFFER_BYTES 592 + +/** + * @def RAIL_EFR32XG27_STATE_BUFFER_BYTES + * @brief The EFR32XG27 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG27_STATE_BUFFER_BYTES 568 + +/** + * @def RAIL_EFR32XG28_STATE_BUFFER_BYTES + * @brief The EFR32XG28 series size needed for + * \ref RAIL_StateBufferEntry_t::bufferBytes. + */ +#define RAIL_EFR32XG28_STATE_BUFFER_BYTES 584 + +#ifndef RAIL_STATE_BUFFER_BYTES +/** + * @def RAIL_STATE_BUFFER_BYTES + * @brief The size needed for \ref RAIL_StateBufferEntry_t::bufferBytes + * on this platform for this radio. This compile-time size may be slightly + * larger than what \ref RAIL_GetStateBufferSize() determines at run-time. + */ +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG21_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG22_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG23_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG24_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG25_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG27_STATE_BUFFER_BYTES +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_STATE_BUFFER_BYTES RAIL_EFR32XG28_STATE_BUFFER_BYTES +#else +#define RAIL_STATE_BUFFER_BYTES 0 // Sate Doxygen +#error "Unsupported platform!" +#endif +#endif //#ifndef RAIL_STATE_BUFFER_BYTES + +/** + * @def RAIL_SEQ_IMAGE_1 + * @brief A macro for the first sequencer image. + */ +#define RAIL_SEQ_IMAGE_1 1 + +/** + * @def RAIL_SEQ_IMAGE_2 + * @brief A macro for the second sequencer image. + */ +#define RAIL_SEQ_IMAGE_2 2 + +#ifndef RAIL_INTERNAL_BUILD +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +/** + * @def RAIL_SEQ_IMAGE_PA_10_DBM + * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs + * with a 10 dBm PA. + */ +#define RAIL_SEQ_IMAGE_PA_10_DBM RAIL_SEQ_IMAGE_1 + +/** + * @def RAIL_SEQ_IMAGE_PA_20_DBM + * @brief A chip-specific macro for the sequencer image used on EFR32XG24 and EFR32XG26 OPNs + * with a 20 dBm PA. + */ +#define RAIL_SEQ_IMAGE_PA_20_DBM RAIL_SEQ_IMAGE_2 + +/** + * @def RAIL_SEQ_IMAGE_COUNT + * @brief A macro for the total number of sequencer images supported on the + * platform. + */ +#define RAIL_SEQ_IMAGE_COUNT 2 + +#else //(_SILICON_LABS_32B_SERIES_2_CONFIG != 4) + +/** + * @def RAIL_SEQ_IMAGE_DEFAULT + * @brief A chip-specific macro for the default sequencer image on platforms + * that support only one sequencer image. + */ +#define RAIL_SEQ_IMAGE_DEFAULT RAIL_SEQ_IMAGE_1 + +/** + * @def RAIL_SEQ_IMAGE_COUNT + * @brief A macro for the total number of sequencer images supported on the + * platform. + */ +#define RAIL_SEQ_IMAGE_COUNT 1 +#endif //(_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +#endif //RAIL_INTERNAL_BUILD + +/** + * @struct RAIL_RffpllConfig_t + * @brief Stores information relevant to the Radio-Friendly Frequency + * Phase-Locked Loop (RFFPLL) for the PHY configuration currently loaded in + * memory. + */ +typedef struct { + uint32_t dividers; // Divider X (Modem Clock), Divider Y (M33 System Clock), and Divider N (Feedback) values + uint32_t radioFreqHz; // Radio clock frequency in Hz + uint32_t sysclkFreqHz; // System clock frequency in Hz +} RAIL_RffpllConfig_t; + +/** + * @def RAIL_RFFPLL_DIVIDERX_MASK + * @brief Bit mask for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERX_MASK 0x000000FFUL + +/** + * @def RAIL_RFFPLL_DIVIDERX_SHIFT + * @brief Shift value for RFFPLL DIVX in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERX_SHIFT 0 + +/** + * @def RAIL_RFFPLL_DIVIDERY_MASK + * @brief Bit mask for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERY_MASK 0x0000FF00UL + +/** + * @def RAIL_RFFPLL_DIVIDERY_SHIFT + * @brief Shift value for RFFPLL DIVY in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERY_SHIFT 8 + +/** + * @def RAIL_RFFPLL_DIVIDERN_MASK + * @brief Bit mask for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERN_MASK 0x00FF0000UL + +/** + * @def RAIL_RFFPLL_DIVIDERN_SHIFT + * @brief Shift value for RFFPLL DIVN in \ref RAIL_RffpllConfig_t::dividers. + */ +#define RAIL_RFFPLL_DIVIDERN_SHIFT 16 + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group General_EFR32XG2 + +// ----------------------------------------------------------------------------- +// Multiprotocol +// ----------------------------------------------------------------------------- +/** + * @addtogroup Multiprotocol_EFR32 EFR32 + * @{ + * @brief EFR32-specific multiprotocol support defines + * @ingroup Multiprotocol + */ + +/** + * @def TRANSITION_TIME_US + * @brief Time it takes to take care of protocol switching. + */ +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1 +// XG22 + devices +#define TRANSITION_TIME_US 510 +#else +// XG21 +#define TRANSITION_TIME_US 500 +#endif + +/** @} */ // end of group Multiprotocol_EFR32 + +// ----------------------------------------------------------------------------- +// Calibration +// ----------------------------------------------------------------------------- +/** + * @addtogroup Calibration_EFR32XG2X EFR32XG2X + * @{ + * @brief EFR32XG2X-specific Calibrations + * @ingroup Calibration + */ + +/** + * @def RAIL_RF_PATHS_2P4GIG + * @brief Indicates the number of 2.4 GHz RF Paths suppported + */ +#ifndef RAIL_RF_PATHS_2P4GIG +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) +#define RAIL_RF_PATHS_2P4GIG 2 +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_RF_PATHS_2P4GIG 1 +#else +#define RAIL_RF_PATHS_2P4GIG 0 +#endif + +/** + * @def RAIL_RF_PATHS_SUBGIG + * @brief Indicates the number of sub-GHz RF Paths supported + */ +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 +#define RAIL_RF_PATHS_SUBGIG 2 +#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 +#define RAIL_RF_PATHS_SUBGIG 2 +#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 +#define RAIL_RF_PATHS_SUBGIG 1 +#else +#define RAIL_RF_PATHS_SUBGIG 0 +#endif +#endif //#ifndef RAIL_RF_PATHS_2P4GIG + +/** + * @def RAIL_RF_PATHS + * @brief Indicates the number of RF Paths supported + */ +#define RAIL_RF_PATHS (RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG) + +#if (RAIL_RF_PATHS > RAIL_MAX_RF_PATHS) +#error "Update rail_types.h RAIL_MAX_RF_PATHS" +#endif + +/** + * @def RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS + * @brief Indicates this version of RAIL supports IR calibration on multiple RF paths + * Needed for backwards compatibility. + */ +#if RAIL_RF_PATHS > 1 +#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 1 +#else +#ifdef DOXYGEN_SHOULD_SKIP_THIS // Leave undefined except for doxygen +#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS 0 +#endif //DOXYGEN_SHOULD_SKIP_THIS +#endif + +/** + * @struct RAIL_ChannelConfigEntryAttr + * @brief A channel configuration entry attribute structure. Items listed + * are designed to be altered and updated during run-time. + */ +struct RAIL_ChannelConfigEntryAttr { + /** IR calibration attributes specific to each channel configuration entry. */ + #if RAIL_SUPPORTS_OFDM_PA + RAIL_IrCalValues_t calValues; + #else//!RAIL_SUPPORTS_OFDM_PA + RAIL_RxIrCalValues_t calValues; + #endif//RAIL_SUPPORTS_OFDM_PA +}; + +/** @} */ // end of group Calibration_EFR32 + +// ----------------------------------------------------------------------------- +// Transmit +// ----------------------------------------------------------------------------- +/** + * @addtogroup PA_EFR32XG2X EFR32XG2X + * @{ + * @ingroup PA + * @brief Types specific to the EFR32 for dealing with the on-chip PAs. + */ + +#ifndef RAIL_TX_POWER_LEVEL_2P4_HP_MAX +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (90U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (1U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (64U) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + * EFR32XG24: capable of 20dBm max output power has max powerlevel:180 + * EFR32XG24: capable of 10dBm max output power has max powerlevel:90 + */ +#if defined (_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (180U) +#else +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (90U) +#endif +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (127U) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (0U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (15U) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (0U) +#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 8 +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) +#else //efr32xg23 +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX (240) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_HP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN (1U) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_MP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_MP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LLP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LLP_MAX (RAIL_TX_POWER_LEVEL_2P4_HP_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_2P4_LLP mode. + */ +#define RAIL_TX_POWER_LEVEL_2P4_LLP_MIN (RAIL_TX_POWER_LEVEL_2P4_HP_MIN) +#endif //_SILICON_LABS_32B_SERIES_2_CONFIG +#endif //RAIL_TX_POWER_LEVEL_2P4_HP_MAX +#if RAIL_FEAT_SUBGIG_RADIO +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 3 || _SILICON_LABS_32B_SERIES_2_CONFIG == 8 +#ifndef RAIL_SUBGIG_MAX +#define RAIL_SUBGIG_MAX 240U +#endif +#elif _SILICON_LABS_32B_SERIES_2_CONFIG == 5 +#define RAIL_SUBGIG_MAX 79U +#endif +#define RAIL_SUBGIG_MIN 1U + +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX (RAIL_SUBGIG_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN (RAIL_SUBGIG_MIN) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX (RAIL_SUBGIG_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_MP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN (RAIL_SUBGIG_MIN) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX (RAIL_SUBGIG_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_LP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN (RAIL_SUBGIG_MIN) +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX (RAIL_SUBGIG_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_SUBGIG_LLP mode. + */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN (RAIL_SUBGIG_MIN) +#endif //RAIL_FEAT_SUBGIG_RADIO + +#if RAIL_SUPPORTS_OFDM_PA +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 5 +#define RAIL_OFDM_PA_MAX 204U +#define RAIL_OFDM_PA_EFF_MAX 204U +#define RAIL_OFDM_PA_MULT 5U +#define RAIL_OFDM_PA_MIN 0U +#define RAIL_OFDM_PA_EFF_MIN 0U +#endif +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_OFDM_PA mode. + */ +#define RAIL_TX_POWER_LEVEL_OFDM_PA_MAX (RAIL_OFDM_PA_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_OFDM_PA mode. + */ +#define RAIL_TX_POWER_LEVEL_OFDM_PA_MIN (RAIL_OFDM_PA_MIN) +#if RAIL_SUPPORTS_EFF +/** + * The maximum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode. + */ +#define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MAX (RAIL_OFDM_PA_EFF_MAX) +/** + * The minimum valid value for the \ref RAIL_TxPowerLevel_t when in \ref + * RAIL_TX_POWER_MODE_OFDM_PA_EFF_MAXDBM mode. + */ +#define RAIL_TX_POWER_LEVEL_OFDM_PA_EFF_MAXDBM_MIN (RAIL_OFDM_PA_EFF_MIN) +#endif +#endif //RAIL_SUPPORTS_OFDM_PA + +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_MP_MAX RAIL_TX_POWER_LEVEL_2P4_MP_MAX +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_MP_MIN RAIL_TX_POWER_LEVEL_2P4_MP_MIN +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX +/** Backwards compatability define */ +#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN + +/** + * The number of PA's on this chip. (Including Virtual PAs) + */ +#ifndef RAIL_NUM_PA +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_NUM_PA (2U) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) +#define RAIL_NUM_PA (4U) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_NUM_PA (5U) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_NUM_PA (4U) +#else +#define RAIL_NUM_PA (3U) +#endif +#endif //#ifndef RAIL_NUM_PA + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +// Only those supported per-platform are defined, for use with #ifdef in +// apps or librail code. +#if RAIL_SUPPORTS_2P4GHZ_BAND +#define RAIL_TX_POWER_MODE_2P4GIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HP) +#define RAIL_TX_POWER_MODE_2P4_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HP) +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 1 +#define RAIL_TX_POWER_MODE_2P4GIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_MP) +#define RAIL_TX_POWER_MODE_2P4_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_MP) +#endif//_SILICON_LABS_32B_SERIES_2_CONFIG == 1 +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) +#define RAIL_TX_POWER_MODE_2P4GIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_LP) +#define RAIL_TX_POWER_MODE_2P4_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_LP) +#endif//((_SILICON_LABS_32B_SERIES_2_CONFIG != 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 8)) +#define RAIL_TX_POWER_MODE_2P4GIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) +#define RAIL_TX_POWER_MODE_2P4_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_2P4_HIGHEST) +#endif//RAIL_SUPPORTS_2P4GHZ_BAND + +#if RAIL_SUPPORTS_SUBGHZ_BAND +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +#define RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) +#else//!RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +#define RAIL_TX_POWER_MODE_SUBGIG_HP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HP) +#define RAIL_TX_POWER_MODE_SUBGIG ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG) +#define RAIL_TX_POWER_MODE_SUBGIG_MP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_MP) +#define RAIL_TX_POWER_MODE_SUBGIG_LP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LP) +#define RAIL_TX_POWER_MODE_SUBGIG_LLP ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_LLP) +#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +#define RAIL_TX_POWER_MODE_SUBGIG_HIGHEST ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_HIGHEST) +#if RAIL_SUPPORTS_EFF +#define RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) +#endif//RAIL_SUPPORTS_EFF +#endif//RAIL_SUPPORTS_SUBGHZ_BAND +#if RAIL_SUPPORTS_OFDM_PA +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +#define RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) +#define RAIL_TX_POWER_MODE_OFDM_PA ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA) +#endif//RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE +#if RAIL_SUPPORTS_EFF +#define RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) +#endif//RAIL_SUPPORTS_EFF +#endif//RAIL_SUPPORTS_OFDM_PA +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group PA_EFR32 + +/****************************************************************************** + * RX Channel Hopping + *****************************************************************************/ +/** + * @addtogroup Rx_Channel_Hopping RX Channel Hopping + * @{ + */ + +#if _SILICON_LABS_32B_SERIES_2_CONFIG == 8 +/// The static amount of memory needed per channel for channel hopping, measured +/// in 32 bit words, regardless of the size of radio configuration structures. +#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (65U) +#else +/// The static amount of memory needed per channel for channel hopping, measured +/// in 32 bit words, regardless of the size of radio configuration structures. +#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL (56U) +#endif + +#if (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ + > RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE) +#error "Update rail_types.h RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE" +#endif + +/** @} */ // end of group Rx_Channel_Hopping + +/** + * @addtogroup Sleep + * @{ + */ + +/// Default PRS channel to use when configuring sleep +#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT (7U) + +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +/// Default RTCC channel to use when configuring sleep +#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (1U) +#else +/// Default RTCC channel to use when configuring sleep +#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT (0U) +#endif + +/// Default timer synchronization configuration +#define RAIL_TIMER_SYNC_DEFAULT { \ + RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \ + RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \ + RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \ +} + +/** @} */ // end of group Sleep + +/** + * @addtogroup State_Transitions_EFR32XG2X + * @{ + * @ingroup State_Transitions + */ + +/** + * @def RAIL_MINIMUM_TRANSITION_US + * @brief The minimum value for a consistent RAIL transition + * @note Transitions may need to be slower than this when using longer + * \ref RAIL_TxPowerConfig_t::rampTime values + */ +#define RAIL_MINIMUM_TRANSITION_US (100U) + +/** + * @def RAIL_MAXIMUM_TRANSITION_US + * @brief The maximum value for a consistent RAIL transition + */ +#define RAIL_MAXIMUM_TRANSITION_US (1000000U) + +/** @} */ // end of group State_Transitions_EFR32 + +#ifdef __cplusplus +} +#endif + +#endif //__RAIL_TYPES_H__ + +#endif //__RAIL_CHIP_SPECIFIC_H_ + +#endif // SLI_LIBRARY_BUILD diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail.h index c46eefb..fa2bb92 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail.h @@ -1,7547 +1,7547 @@ -/***************************************************************************//** - * @file - * @brief The main header file for the RAIL library. It describes the external - * APIs available to a RAIL user - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_H__ -#define __RAIL_H__ - -#include // For memcpy() - -// Get the RAIL-specific structures and types -#include "rail_types.h" -#include "rail_assert_error_codes.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup RAIL_API RAIL API - * @brief This is the primary API layer for the Radio Abstraction Interface - * Layer (RAIL) - * @{ - */ - -/** - * @defgroup Chip_Specific Chip-Specific - * @brief Chip-Specific RAIL APIs, types, and information - */ - -/** - * @defgroup Protocol_Specific Protocol-specific - * @brief Protocol-Specific RAIL APIs - */ - -/****************************************************************************** - * General Radio Operation - *****************************************************************************/ -/** - * @addtogroup General - * @brief Basic APIs to set up and interact with the RAIL library - * @{ - */ - -/** - * Get the version information for the compiled RAIL library. - * - * @param[out] version A pointer to \ref RAIL_Version_t structure to - * populate with version information. - * @param[in] verbose Populate \ref RAIL_Version_t struct with verbose - * information. - * - * The version information contains a major version number, a minor version - * number, and a rev (revision) number. - */ -void RAIL_GetVersion(RAIL_Version_t *version, bool verbose); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/** - * A global pointer to the head of a linked list of state buffers - * \ref RAIL_Init() can use. - * - * RAIL internally provides one statically-allocated RAM state buffer - * for a single protocol and two for dynamic multiprotocol. If your - * application needs more, they can be provided via \ref - * RAIL_AddStateBuffer3() or RAIL_AddStateBuffer4(), which use - * internal buffers, or the more general \ref RAIL_AddStateBuffer(). - * - * This symbol is WEAK in the RAIL library in case an application wants - * to allocate and provide its own buffers. However, this use is highly - * discouraged. - */ -extern RAIL_StateBufferEntry_t *RAIL_StateBufferHead; - -/** - * Get the run-time size of the radio's state buffer. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Size, in bytes, of the radio's internal state buffer. - * If the handle is invalid, 0 is returned. - * - * See \ref RAIL_STATE_BUFFER_BYTES for a compile-time estimated size - * definition, which may be larger than what this function returns. - */ -uint32_t RAIL_GetStateBufferSize(RAIL_Handle_t genericRailHandle); - -/** - * Add an app-provided state buffer to the \ref RAIL_StateBufferHead list. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @param[in] newEntry pointer to a \ref RAIL_StateBufferEntry_t to - * add to the liked list of state buffers headed by - * \ref RAIL_StateBufferHead. Both the \ref RAIL_StateBufferEntry_t - * to which this parameter points and the \ref - * RAIL_StateBufferEntry_t::buffer to which that points must be - * allocated in RAM and persist indefinitely beyond this call. - * @return Status code indicating success of the function call. - * An error should be returned if the entry's - * \ref RAIL_StateBufferEntry_t::bufferBytes is too small or - * the RAIL_StateBufferEntry_t::buffer pointer seems invalid. - * - * RAIL's internal \ref RAIL_StateBufferHead should prove - * sufficient for most applications, providing one (single protocol) - * or two (dynamic multiprotocol) buffers preallocated in RAM for - * use by \ref RAIL_Init(). This function exists for dynamic - * multiprotocol applications that needs more than two protocols, or - * that prefer to dynamically allocate RAIL state buffers just prior - * to calling \ref RAIL_Init() rather than having them statically - * allocated in RAM. - */ -RAIL_Status_t RAIL_AddStateBuffer(RAIL_Handle_t genericRailHandle, - RAIL_StateBufferEntry_t *newEntry); - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * Add a 3rd multiprotocol internal state buffer for use by \ref RAIL_Init(). - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * An error is returned if the 3rd state buffer was previously added - * or this isn't the RAIL multiprotocol library. - */ -RAIL_Status_t RAIL_AddStateBuffer3(RAIL_Handle_t genericRailHandle); - -/** - * Add a 4th multiprotocol internal state buffer for use by \ref RAIL_Init(). - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * An error is returned if the 4th state buffer was previously added. - * or this isn't the RAIL multiprotocol library. - */ -RAIL_Status_t RAIL_AddStateBuffer4(RAIL_Handle_t genericRailHandle); - -/** - * Allocate a DMA channel for RAIL to work with. - * - * @param[in] channel The DMA channel to use when copying memory. If a value of - * RAIL_DMA_INVALID is passed, RAIL will stop using any DMA channel. - * @return Status code indicating success of the function call. - * - * To use this API, the application must initialize the DMA engine - * on the chip and allocate a DMA channel. This channel will be used - * periodically to copy memory more efficiently. Call this function - * before RAIL_Init to have the most benefit. If the application needs - * to take back control of the DMA channel that RAIL is using, this API may be - * called with a channel of RAIL_DMA_INVALID to tell RAIL to stop using DMA. - */ -RAIL_Status_t RAIL_UseDma(uint8_t channel); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Load the first image \ref RAIL_SEQ_IMAGE_1 into the radio sequencer during - * RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSequencerImage1(RAIL_Handle_t genericRailHandle); - -/** - * Load the second image \ref RAIL_SEQ_IMAGE_2 into the radio sequencer during - * RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. On platforms where \ref RAIL_SEQ_IMAGE_COUNT < 2, - * the function returns with \ref RAIL_STATUS_INVALID_CALL. - */ -RAIL_Status_t RAIL_LoadSequencerImage2(RAIL_Handle_t genericRailHandle); - -/** - * Callback used to load the radio sequencer image during RAIL initialization. - * This function is optional to implement. - * - * @return Status code indicating success of the function call. - * - * This callback is used by RAIL to load a radio sequencer image during \ref - * RAIL_Init via an API such as \ref RAIL_LoadSequencerImage1. If this - * function is not implemented, a default image will be loaded. On some - * platforms, (in particular EFR32XG24), not implementing this function may - * result in a larger overall code size due to unused sequencer images not - * being dead stripped. - * - * @note If this function is implemented without a call to an image loading API - * such as \ref RAIL_LoadSequencerImage1, an assert will occur during - * RAIL initialization. Similarly, if an image is loaded that is - * unsupported by the platform, an assert will occur. - */ -RAIL_Status_t RAILCb_RadioSequencerImageLoad(void); - -/** - * Load the FSK, OFDM and OQPSK image into the software modem (SFM) sequencer - * during RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSfmSunFskOfdmOqpsk(RAIL_Handle_t genericRailHandle); - -/** - * Load the OFDM and OQPSK image into the software modem (SFM) sequencer during - * RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSfmSunOfdmOqpsk(RAIL_Handle_t genericRailHandle); - -/** - * Load the OFDM image into the software modem (SFM) sequencer during - * RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSfmSunOfdm(RAIL_Handle_t genericRailHandle); - -/** - * Load the empty image into the software modem (SFM) sequencer during - * RAIL initialization. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Status code indicating success of the function call. - * - * This function must only be called from within the RAIL callback context of - * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref - * RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_LoadSfmEmpty(RAIL_Handle_t genericRailHandle); - -/** - * Callback used to load the software modem (SFM) sequencer image during RAIL - * initialization. This function is optional to implement. - * - * @return Status code indicating success of the function call. - * - * This callback is used by RAIL to load a software modem sequencer image during \ref - * RAIL_Init via an API such as \ref RAIL_LoadSfmSunFskOfdmOqpsk. If this - * function is not implemented, a default image including FSK, OFDM andd OQPSK - * modulations will be loaded. - * - * @note If this function is implemented without a call to an image loading API - * such as \ref RAIL_LoadSfmSunFskOfdmOqpsk, an assert will occur during - * RAIL initialization. Similiarly, if an image is loaded that is - * unsupported by the platform, an assert will occur. - */ -RAIL_Status_t RAILCb_LoadSfmSequencer(void); -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Initialize RAIL. - * - * @param[in,out] railCfg The configuration and state structure for setting up - * the library, which contains memory and other options that RAIL needs. - * This structure must be allocated in application global read-write - * memory. RAIL may modify fields within or referenced by this structure - * during its operation. - * @param[in] cb A callback that notifies the application when the radio is - * finished initializing and is ready for further configuration. This - * callback is useful for potential transceiver products that require a - * power up sequence before further configuration is available. After the - * callback fires, the radio is ready for additional configuration before - * transmit and receive operations. - * @return Handle for initialized rail instance or NULL if an - * invalid value was passed in the railCfg. - * - * @note Call this function only once per protocol. If called - * again, it will do nothing and return NULL. - */ -RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg, - RAIL_InitCompleteCallbackPtr_t cb); - -/** - * Get RAIL initialization status. - * - * @return True if the radio has finished initializing and - * false otherwise. - * - * RAIL APIs, e.g., RAIL_GetTime(), which work only if RAIL_Init() has been called, - * can use RAIL_IsInitialized() to determine whether RAIL has been initialized or not. - */ -bool RAIL_IsInitialized(void); - -/** - * Collect entropy from the radio if available. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] buffer The buffer to write the collected entropy. - * @param[in] bytes The number of bytes to fill in the input buffer. - * @return Returns the number of bytes of entropy collected. For - * chips that don't support entropy collection, the function returns 0. - * Values less than the requested amount may also be returned on platforms - * that use entropy pools to collect random data periodically. - * - * Attempts to fill the provided buffer with the requested number of bytes of - * entropy. If the requested number of bytes can't be provided, as many - * bytes as possible will be filled and returned. For chips - * that do not support this function, 0 bytes are always returned. For - * information about the specific mechanism for gathering entropy, see - * documentation for the chip family. - */ -uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle, - uint8_t *buffer, - uint16_t bytes); - -/** @} */ // end of group General - -/****************************************************************************** - * PTI - *****************************************************************************/ -/** - * @addtogroup PTI Packet Trace (PTI) - * @brief Basic APIs to set up and interact with PTI settings - * @{ - */ - -/** - * Configure PTI pin locations, serial protocols, and baud rates. - * - * @param[in] railHandle A RAIL instance handle (currently not used). - * @param[in] ptiConfig A configuration structure applied to the - * relevant PTI registers. A NULL ptiConfig will produce undefined - * behavior. - * @return Status code indicating success of the function call. - * - * This method must be called before RAIL_EnablePti() is called. - * Although a RAIL handle is included for potential future - * expansion of this function, it is currently not used. That is, - * there is only one PTI configuration that can be active on a - * chip, regardless of the number of protocols (unless the application - * updates the configuration upon a protocol switch), - * and the configuration is not saved in the RAIL instance. For optimal - * future compatibility, pass in a chip-specific handle, such as - * \ref RAIL_EFR32_HANDLE. - * - * PTI should be configured only when the radio is off (idle). - * - * @note On EFR32 platforms GPIO configuration must be unlocked - * (see GPIO->LOCK register) to configure or use PTI. - */ -RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle, - const RAIL_PtiConfig_t *ptiConfig); - -/** - * Get the currently-active PTI configuration. - * - * @param[in] railHandle A RAIL instance handle (currently not used). - * @param[out] ptiConfig A configuration structure filled with the active - * PTI configuration. - * @return RAIL status indicating success of the function call. - * - * Although most combinations of configurations can be set, it is safest - * to call this method after configuration to confirm which values were - * actually set. As in RAIL_ConfigPti, railHandle is not used. This function - * always returns the single active PTI configuration regardless of the - * active protocol. For optimal future compatibility, pass in a - * chip-specific handle, such as \ref RAIL_EFR32_HANDLE. - */ -RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle, - RAIL_PtiConfig_t *ptiConfig); - -/** - * Enable Packet Trace Interface (PTI) output of packet data. - * - * @param[in] railHandle A RAIL instance handle (currently not used). - * @param[in] enable PTI is enabled if true; disable if false. - * @return RAIL status indicating success of the function call. - * - * Similarly to having only one PTI configuration per chip, - * PTI can only be enabled or disabled for all protocols. It cannot - * be individually set to enabled and disabled per protocol - * (unless the application switches it when - * the protocol switches), and enable/disable is not saved as part of the - * RAIL instance. For optimal future compatibility, pass in a chip-specific - * handle, such as \ref RAIL_EFR32_HANDLE. - * - * PTI should be enabled or disabled only when the radio is off (idle). - * - * @warning On EFR32 platforms GPIO configuration must be unlocked - * (see GPIO->LOCK register) to configure or use PTI, otherwise a fault - * or assert might occur. - * If GPIO configuration locking is desired, PTI must be disabled - * beforehand either with this function or with \ref RAIL_ConfigPti() - * using \ref RAIL_PTI_MODE_DISABLED. - */ -RAIL_Status_t RAIL_EnablePti(RAIL_Handle_t railHandle, - bool enable); - -/** - * Set a protocol that RAIL outputs on PTI. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] protocol The enumeration representing which protocol the node is using. - * @return Status code indicating success of the function call. - * - * The protocol is output via PTI for each packet. - * Before any protocol is set, the default value is \ref - * RAIL_PTI_PROTOCOL_CUSTOM. Use one of the enumeration values so that - * the Network Analyzer can decode the packet. - * - * @note This function cannot be called unless the radio is currently in the - * \ref RAIL_RF_STATE_IDLE or \ref RAIL_RF_STATE_INACTIVE states. For this - * reason, call this function early on before starting radio - * operations and not changed later. - */ -RAIL_Status_t RAIL_SetPtiProtocol(RAIL_Handle_t railHandle, - RAIL_PtiProtocol_t protocol); - -/** - * Get the protocol that RAIL outputs on PTI. - * - * @param[in] railHandle A RAIL instance handle. - * @return PTI protocol in use. - */ -RAIL_PtiProtocol_t RAIL_GetPtiProtocol(RAIL_Handle_t railHandle); - -/** @} */ // end of group PTI - -/****************************************************************************** - * Antenna Control - *****************************************************************************/ -/** - * @addtogroup Antenna_Control Antenna Control - * @brief Basic APIs to control the antenna functionality - * @{ - */ -/** - * Configure antenna path and pin locations. - * - * @warning This API must be called before any TX or RX occurs. Otherwise, - * the antenna configurations for those functions will not take effect. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config A configuration structure applied to the relevant Antenna - * Configuration registers. A NULL configuration will produce undefined behavior. - * @return Status code indicating success of the function call. - * - * This function informs RAIL how to select each antenna, but not when. - * Antenna selection for receive is controlled by the - * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA0 and - * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA1 options - * (and the \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA_AUTO combination). - * Antenna selection for transmit is controlled by the - * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA0 and - * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA1 options. - * - * Although a RAIL handle is included for potential future - * expansion of this function, it is currently not used. That is, - * only one antenna configuration can be active on a - * chip, regardless of the number of protocols (unless the application - * updates the configuration upon a protocol switch), - * and the configuration is not saved in the RAIL instance. For optimal - * future compatibility, pass in a chip-specific handle, such as - * \ref RAIL_EFR32_HANDLE. - */ -RAIL_Status_t RAIL_ConfigAntenna(RAIL_Handle_t railHandle, - const RAIL_AntennaConfig_t *config); - -/** - * Get the default RF path. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] rfPath Pointer to RF path. - * @return A status code indicating success of the function call. - * - * If multiple protocols are used, this function returns - * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is - * not active. In that case, the caller must attempt to re-call this function later, - * for example when \ref RAIL_EVENT_CONFIG_SCHEDULED trigger. - */ -RAIL_Status_t RAIL_GetRfPath(RAIL_Handle_t railHandle, RAIL_AntennaSel_t *rfPath); - -/** @} */ // end of group Antenna_Control - -/****************************************************************************** - * Radio Configuration - *****************************************************************************/ -/// @addtogroup Radio_Configuration Radio Configuration -/// @brief Routines for setting up and querying radio configuration information. -/// -/// These routines allow for runtime flexibility in the radio -/// configuration. Some of the parameters, however, are meant to be generated -/// from the radio calculator in Simplicity Studio. The basic code to configure -/// the radio from this calculator output looks like the example below. -/// -/// @code{.c} -/// // Associate a specific channel configuration with a particular RAIL instance and -/// // load the settings that correspond to the first usable channel. -/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); -/// @endcode -/// -/// For more information about the types of parameters that can be changed in -/// the other functions and how to use them, see their individual documentation. -/// -/// @{ - -/** - * Load a static radio configuration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config A pointer to a radio configuration. - * @return Status code indicating success of the function call. - * - * The configuration passed into this function should be auto-generated - * and not manually created or edited. By default, do not call this function - * in RAIL 2.x and later unless instructed by Silicon Labs because it - * may bypass updating certain RAIL state. In RAIL 2.x and later, the - * RAIL_ConfigChannels function applies the default radio configuration - * automatically. - */ -RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle, - RAIL_RadioConfig_t config); - -/** - * Modify the currently configured fixed frame length in bytes. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] length The expected fixed frame length. A value of 0 is infinite. - * A value of RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to - * the length specified by the default frame type configuration. - * @return Length configured; The new frame length configured into the hardware - * for use. 0 if in infinite mode, or RAIL_SETFIXEDLENGTH_INVALID if the frame - * length has not yet been overridden by a valid value. - * - * Sets the fixed-length configuration for transmit and receive. - * Be careful when using this function in receive and transmit as this - * function changes the default frame configuration and remains in force until - * it is called again with an input value of RAIL_SETFIXEDLENGTH_INVALID. This - * function will override any fixed or variable length settings from a radio - * configuration. - */ -uint16_t RAIL_SetFixedLength(RAIL_Handle_t railHandle, uint16_t length); - -/** - * Configure the channels supported by this device. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config A pointer to the channel configuration for your device. - * This pointer will be cached in the library so it must - * exist for the runtime of the application. Typically, this should be - * what is stored in Flash by the configuration tool. - * @param[in] cb Function called whenever a radio configuration change occurs. - * @return Returns the first available channel in the configuration. - * - * When configuring channels on EFR32, the radio tuner is reconfigured - * based on the frequency and channel spacing in the channel configuration. - * - * @note config can be NULL to simply register or unregister the cb callback - * function when using RAIL internal protocol-specific radio configuration - * APIs for BLE, IEEE 802.15.4, or Z-Wave, which lack callback specification. - * In this use case, 0 is returned. - */ -uint16_t RAIL_ConfigChannels(RAIL_Handle_t railHandle, - const RAIL_ChannelConfig_t *config, - RAIL_RadioConfigChangedCallback_t cb); - -/** - * Get verbose listing of channel metadata for the current channel configuration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] channelMetadata Allocated array that will be populated with - * channel metadata. - * @param[in,out] length Pointer to the length of the channelMetadata. - * This value will be updated to the number of channels written to the array. - * @param[in] minChannel Minimum channel number about which to collect data. - * @param[in] maxChannel Maximum channel number about which to collect data. - * @return Status of the call. \ref RAIL_STATUS_INVALID_PARAMETER means that, - * based on the currently active radio configuration, there are more - * channels to write than there is space provided in the allocated - * channelMetadata. However, the channel metadata that was written is valid. - * \ref RAIL_STATUS_INVALID_STATE indicates that the channel configuration - * has not been configured. \ref RAIL_STATUS_NO_ERROR indicates complete - * success. - */ -RAIL_Status_t RAIL_GetChannelMetadata(RAIL_Handle_t railHandle, - RAIL_ChannelMetadata_t *channelMetadata, - uint16_t *length, - uint16_t minChannel, - uint16_t maxChannel); - -/** - * Check whether the channel exists in RAIL. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel A channel number to check. - * @return Returns RAIL_STATUS_NO_ERROR if channel exists - * - * Returns RAIL_STATUS_INVALID_PARAMETER if the given channel does not exist - * in the channel configuration currently used or RAIL_STATUS_NO_ERROR if the - * channel is valid. - */ -RAIL_Status_t RAIL_IsValidChannel(RAIL_Handle_t railHandle, - uint16_t channel); - -/** - * Cause radio settings associated with a particular channel to be applied to - * hardware. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel The channel to prepare for use. - * @return \ref RAIL_STATUS_NO_ERROR on success or - * \ref RAIL_STATUS_INVALID_PARAMETER if the given channel does not have an - * associated channel configuration entry. - * - * This function walks the channelConfigEntry list and applies the configuration - * associated with the specified channel. This function manually - * changes channels without starting a TX or RX operation. - * - * When successful, the radio is idled. - * When unsuccessful, the radio state will not be altered. - */ -RAIL_Status_t RAIL_PrepareChannel(RAIL_Handle_t railHandle, uint16_t channel); - -/** - * Return the current RAIL channel. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] channel The channel for which RAIL is currently configured. - * @return RAIL_STATUS_NO_ERROR on success or - * RAIL_STATUS_INVALID_CALL if the radio is not configured for any channel or - * RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. - * - * This function returns the channel most recently specified in API calls that - * pass in a channel to tune to, namely \ref RAIL_PrepareChannel, - * \ref RAIL_StartTx, \ref RAIL_StartScheduledTx, \ref RAIL_StartCcaCsmaTx, - * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, - * \ref RAIL_StartScheduledCcaLbtTx, \ref RAIL_StartRx, \ref RAIL_ScheduleRx, - * \ref RAIL_StartAverageRssi, \ref RAIL_StartTxStream, \ref RAIL_StartTxStreamAlt. - * It doesn't follow changes RAIL performs implicitly during channel hopping and - * mode switch. - */ -RAIL_Status_t RAIL_GetChannel(RAIL_Handle_t railHandle, uint16_t *channel); - -/** - * Return the current RAIL channel. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] channel The channel for which RAIL is currently configured. - * @return RAIL_STATUS_NO_ERROR on success or - * RAIL_STATUS_INVALID_CALL if the radio is not configured for any channel or - * RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. - * - * This function returns the channel the radio is currently tuned to if the - * specified RAIL handle is active. It returns the channel it will be tuned to - * during the next protocol switch if the handle is inactive. - * The channel returned may be different than what \ref RAIL_GetChannel returns - * when channel hopping or mode switch are involved. - */ -RAIL_Status_t RAIL_GetChannelAlt(RAIL_Handle_t railHandle, uint16_t *channel); - -/** - * Return the symbol rate for the current PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return The symbol rate in symbols per second or 0. - * - * The symbol rate is the rate of symbol changes over the air. For non-DSSS - * PHYs, this is the same as the baudrate. For DSSS PHYs, it is the baudrate - * divided by the length of a chipping sequence. For more information, - * see the modem calculator documentation. If the rate cannot be - * calculated, this function returns 0. - */ -uint32_t RAIL_GetSymbolRate(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Calculate the symbol rate for the current PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return The symbol rate in symbols per second or 0. - * - * This function calculates the symbol rate when the radio configuration does - * not include that information. In general, this function should be - * implemented automatically in the radio configuration as a stub. - */ -uint32_t RAILCb_CalcSymbolRate(RAIL_Handle_t railHandle); -#endif - -/** - * Return the bit rate for the current PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return The bit rate in bits per second or 0. - * - * The bit rate is the effective over-the-air data rate. It does not account - * for extra spreading for forward error correction, and so on, but - * accounts for modulation schemes, DSSS, and other configurations. For more - * information, see the modem calculator documentation. If the rate cannot be - * calculated, this function returns 0. - */ -uint32_t RAIL_GetBitRate(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Calculate the bit rate for the current PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return The bit rate in bits per second or 0. - * - * This function calculates the bit rate when the radio configuration does - * not include that information. In general, this function should be - * implemented automatically in the radio configuration as a stub. - */ -uint32_t RAILCb_CalcBitRate(RAIL_Handle_t railHandle); -#endif -/** - * Set the PA capacitor tune value for transmit and receive. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] txPaCtuneValue PA Ctune value for TX mode. - * @param[in] rxPaCtuneValue PA Ctune value for RX mode. - * @return Status code indicating success of the function call. - * - * Tunes the impedance of the transmit - * and receive modes by changing the amount of capacitance at - * the PA output. - * Changes made to the TX Power configuration, e.g., calling \ref RAIL_ConfigTxPower, - * will undo changes made to PA capacitor tune value for transmit and receive - * via \ref RAIL_SetPaCTune. - */ -RAIL_Status_t RAIL_SetPaCTune(RAIL_Handle_t railHandle, - uint8_t txPaCtuneValue, - uint8_t rxPaCtuneValue); - -/** - * Get the sync words and their length. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] syncWordConfig An application-provided non-NULL pointer to store - * \ref RAIL_SyncWordConfig_t sync word information. - * @return Status code indicating success of the function call. - **/ -RAIL_Status_t RAIL_GetSyncWords(RAIL_Handle_t railHandle, - RAIL_SyncWordConfig_t *syncWordConfig); - -/** - * Set the selected sync words and their length. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] syncWordConfig A non-NULL pointer to \ref RAIL_SyncWordConfig_t - * specifying the sync words and their length. - * The desired length should be between 2 and 32 bits inclusive, however it is - * recommended to not change the length below what the PHY syncWord length is - * configured to be. Changing the syncWord length, especially to that which is - * lower than the default length, may result in a decrease in packet reception - * rate or may not work at all. - * Other values will result in \ref RAIL_STATUS_INVALID_PARAMETER. The default - * syncWord continues to be valid. - * @return Status code indicating success of the function call. - * When the custom sync word(s) applied by this API are no longer needed, or to - * revert to default sync word, calling RAIL_ConfigChannels() will re-establish - * the sync words specified in the radio configuration. - * - * This function will return \ref RAIL_STATUS_INVALID_STATE if called when BLE - * has been enabled for this railHandle. When changing sync words in BLE mode, - * use \ref RAIL_BLE_ConfigChannelRadioParams instead. - **/ -RAIL_Status_t RAIL_ConfigSyncWords(RAIL_Handle_t railHandle, - const RAIL_SyncWordConfig_t *syncWordConfig); - -/** - * Sets the whitening initialization value. - * - * @param[in] railHandle A RAIL instance handle. - * @return The whitening initialization value currently being used. - */ -uint16_t RAIL_GetWhiteningInitVal(RAIL_Handle_t railHandle); - -/** - * Returns the CRC initialization value. - * - * @param[in] railHandle A RAIL instance handle. - * @return The CRC initialization value currently being used. - */ -uint32_t RAIL_GetCrcInitVal(RAIL_Handle_t railHandle); - -/** - * Sets the whitening initialization value. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] whiteInit A whitening initialization value. - * @return Status code indicating success of the function call. - * - * Use this function to override the whitening initialization value - * defined by the current PHY's radio configuration. The new value - * will persist until this function is called again, \ref - * RAIL_ResetWhiteningInitVal() is called, or the PHY is - * changed. - * - * @note Overriding a PHY's whitening initialization value - * will break communication with peers unless they effect - * a similar change. - * - * @warning This API must not be used when either 802.15.4 - * or BLE modes are enabled. - */ -RAIL_Status_t RAIL_SetWhiteningInitVal(RAIL_Handle_t railHandle, - uint16_t whiteInit); - -/** - * Sets the CRC initialization value. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] crcInit A CRC initialization value. - * @return Status code indicating success of the function call. - * - * Use this function to override the CRC initialization value - * defined by the current PHY's radio configuration. The new value - * will persist until this function is called again, \ref - * RAIL_ResetCrcInitVal() is called, or the PHY is changed. - * - * @note Overriding a PHY's CRC initialization value - * will break communication with peers unless they effect - * a similar change. - * - * @warning This API must not be used when either 802.15.4 - * or BLE modes are enabled. - */ -RAIL_Status_t RAIL_SetCrcInitVal(RAIL_Handle_t railHandle, - uint32_t crcInit); - -/** - * Restores the whitening initialization value to its initial setting - * from the Radio Configurator. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. - * - * Can use this function after using \ref RAIL_SetWhiteningInitVal(). - */ -RAIL_Status_t RAIL_ResetWhiteningInitVal(RAIL_Handle_t railHandle); - -/** - * Restores the CRC initialization value to its initial setting from - * the Radio Configurator. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. - * - * Can use this function after using \ref RAIL_SetCrcInitVal(). - */ -RAIL_Status_t RAIL_ResetCrcInitVal(RAIL_Handle_t railHandle); - -/** @} */ // end of group Radio_Configuration - -/****************************************************************************** - * Timing Information - *****************************************************************************/ -/// @addtogroup System_Timing System Timing -/// @brief Functionality related to the RAIL timer and general system time. -/// -/// These functions can be used to get information about the current system time -/// or to manipulate the RAIL timer. -/// -/// The system time returned by RAIL_GetTime() is in the same timebase that is -/// used throughout RAIL. Any callbacks or structures that provide a timestamp, -/// such as \ref RAIL_RxPacketDetails_t::timeReceived, will use the same timebase -/// as will any APIs that accept an absolute time for scheduling their action. -/// Throughout the documentation, the timebase is referred to as the RAIL -/// timebase. The timebase is currently a value in microseconds from \ref -/// RAIL_Init() time, which means that it will wrap every 1.19 hours. -/// (`(2^32 - 1) / (3600 sec/hr * 1000000 us/sec)`). -/// -/// The provided timer is hardware-backed and interrupt-driven. It can be used -/// for timing any event in the system, but is especially helpful for -/// timing protocol-based state machines and other systems that interact with -/// the radio. To avoid processing the expiration in interrupt -/// context, leave the cb parameter passed to RAIL_SetTimer() as NULL and poll -/// for expiration with the RAIL_IsTimerExpired() function. See below for an -/// example of the interrupt driven method of interacting with the timer. -/// -/// @code{.c} -/// void timerCb(RAIL_Handle_t cbArg) -/// { -/// // Timer callback action -/// } -/// -/// void main(void) -/// { -/// // Initialize RAIL ... -/// -/// // Set up a timer for 1 ms from now -/// RAIL_SetTimer(railHandle, 1000, RAIL_TIME_RELATIVE, &timerCb); -/// -/// // Run main loop -/// while(1); -/// } -/// @endcode -/// -/// If multiple software timers are needed to be run off of the one available -/// hardware timer, enable a software multiplexing layer within RAIL -/// using the \ref RAIL_ConfigMultiTimer() function. This will allow you to -/// set up as many timers as you want using the RAIL_*MultiTimer() functions. See -/// the example below for using the multitimer functionality. -/// -/// @code{.c} -/// // Declare timer structures in global space or somewhere that will exist -/// // until the callback has fired -/// RAIL_MultiTimer_t tmr1, tmr2; -/// -/// void timerCb(RAIL_MultiTimer_t *tmr, -/// RAIL_Time_t expectedTimeOfEvent, -/// void *cbArg) -/// { -/// if (tmr == tmr1) { -/// // Timer 1 action -/// } else { -/// // Timer 2 action -/// } -/// } -/// -/// void main(void) -/// { -/// // Initialize RAIL ... -/// -/// RAIL_ConfigMultiTimer(true); -/// -/// // Set up one timer for 1 ms from now and one at time 2000000 in the RAIL -/// // timebase -/// RAIL_SetMultiTimer(&tmr1, 1000, RAIL_TIME_RELATIVE, &timerCb, NULL); -/// RAIL_SetMultiTimer(&tmr2, 2000000, RAIL_TIME_ABSOLUTE, &timerCb, NULL); -/// -/// // Run main loop -/// while(1); -/// } -/// @endcode -/// -/// @{ - -/** - * Get the current RAIL time. - * - * @return Returns the RAIL timebase in microseconds. Note that this wraps - * after about 1.19 hours since it's stored in a 32 bit value. - * - * Returns the current time in the RAIL timebase (microseconds). It can be - * used to compare with packet timestamps or to schedule transmits. - */ -RAIL_Time_t RAIL_GetTime(void); - -/** - * Set the current RAIL time. - * - * @warning Use this API only for testing purposes or in - * very limited circumstances during RAIL Timer Synchronization. - * Undefined behavior can result by calling it in multiprotocol or - * when the radio is not idle or timed events are active. Applications - * using \ref RAIL_GetTime() may not be designed for discontinuous - * changes to the RAIL time base. - * - * @param[in] time Set the RAIL timebase to this value in microseconds. - * @return Status code indicating the success of the function call. - * - * Sets the current time in the RAIL timebase in microseconds. - */ -RAIL_Status_t RAIL_SetTime(RAIL_Time_t time); - -/** - * Blocking delay routine for a specified number of microseconds. - * - * @param[in] microseconds Delay duration in microseconds. - * @return Status code indicating success of the function call. - * - * Use this RAIL API only for short blocking delays because it has less overhead - * than calling RAIL_GetTime() in a loop. - * @note - * Passing large delay values may give unpredictable results or trigger - * the Watchdog reset. - * \n Also, this function will start the clocks required for the RAIL timebase if they - * are not running, except between \ref RAIL_Sleep() and \ref RAIL_Wake() - * where the timer must remain stopped. - * \n Interrupts are not disabled during the delay, so the delay may be longer if an - * interrupt extends beyond the delay duration. - */ -RAIL_Status_t RAIL_DelayUs(RAIL_Time_t microseconds); - -/** - * Schedule a timer to expire using the RAIL timebase. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] time The timer's expiration time in the RAIL timebase. - * @param[in] mode Indicates whether the time argument is an absolute - * RAIL time or relative to the current RAIL time. Specifying mode - * \ref RAIL_TIME_DISABLED is the same as calling RAIL_CancelTimer(). - * @param[in] cb The callback for RAIL to call when the timer expires. - * @return RAIL_STATUS_NO_ERROR on success and - * RAIL_STATUS_INVALID_PARAMETER if the timer can't be scheduled. - * - * Configures a timer to expire after a period in the RAIL timebase. - * This timer can be used to implement low-level protocol features. - * - * @warning Attempting to schedule the timer when it is - * still running from a previous request is bad practice, unless the cb - * callback is identical to that used in the previous request, in which case - * the timer is rescheduled to the new time. Note that if the original timer - * expires as it is being rescheduled, the callback may or may not occur. It - * is generally good practice to cancel a running timer before rescheduling - * it to minimize ambiguity. - */ -RAIL_Status_t RAIL_SetTimer(RAIL_Handle_t railHandle, - RAIL_Time_t time, - RAIL_TimeMode_t mode, - RAIL_TimerCallback_t cb); - -/** - * Return the absolute time that the RAIL timer was configured to expire. - * - * @param[in] railHandle A RAIL instance handle. - * @return The absolute time that this timer was set to expire. - * - * Provides the absolute time regardless of the \ref RAIL_TimeMode_t that - * was passed into \ref RAIL_SetTimer. Note that the time might be in the - * past if the timer has already expired. The return value is undefined if the - * timer was never set. - */ -RAIL_Time_t RAIL_GetTimer(RAIL_Handle_t railHandle); - -/** - * Stop the currently scheduled RAIL timer. - * - * @param[in] railHandle A RAIL instance handle. - * Cancels the timer. If this function is called before the timer expires, - * the cb callback specified in the earlier RAIL_SetTimer() call will never - * be called. - */ -void RAIL_CancelTimer(RAIL_Handle_t railHandle); - -/** - * Check whether the RAIL timer has expired. - * - * @param[in] railHandle A RAIL instance handle. - * @return True if the previously scheduled timer has expired and false - * otherwise. - * - * Polling with this function is an alternative to the callback. - */ -bool RAIL_IsTimerExpired(RAIL_Handle_t railHandle); - -/** - * Check whether the RAIL timer is currently running. - * - * @param[in] railHandle A RAIL instance handle. - * @return Returns true if the timer is running and false if - * the timer has expired or was never set. - */ -bool RAIL_IsTimerRunning(RAIL_Handle_t railHandle); - -/** - * Configure the RAIL software timer feature. - * - * @param[in] enable Enables/disables the RAIL multitimer. - * @return True if the multitimer was successfully enabled/disabled, false - * otherwise. - * - * Turning this on will add a software timer layer above the physical RAIL timer - * so that the user can have as many timers as desired. It is not necessary to - * call this function if the MultiTimer APIs are not used. - * - * @note This function must be called before calling \ref RAIL_SetMultiTimer. - * This function is a no-op on multiprotocol as this layer is already used - * under the hood. - * Do not call this function while the RAIL timer is running. - * Call \ref RAIL_IsTimerRunning before enabling/disabling the multitimer. - * If the multitimer is not needed, do not call this function to - * allow the multitimer code to be dead stripped. If the multitimer is - * enabled for use, the multitimer and timer APIs can both be used. - * However, no timer can be in use while this function is being called. - */ -bool RAIL_ConfigMultiTimer(bool enable); - -/** - * Start a multitimer instance. - * - * @note - * It is legal to start an already running timer. If this is done, the timer - * will first be stopped before the new configuration is applied. - * If expirationTime is 0, the callback is called - * immediately. - * - * @param[in,out] tmr A pointer to the timer instance to start. - * @param[in] expirationTime A time when the timer is set to expire. - * @param[in] expirationMode Select mode of expirationTime. See \ref - * RAIL_TimeMode_t. - * @param[in] callback A function to call on timer expiry. See \ref - * RAIL_MultiTimerCallback_t. NULL is a legal value. - * @param[in] cbArg An extra callback function parameter for the user application. - * - * @return - * \ref RAIL_STATUS_NO_ERROR on success.@n - * \ref RAIL_STATUS_INVALID_PARAMETER if tmr has an illegal value or if - * timeout is in the past. - */ -RAIL_Status_t RAIL_SetMultiTimer(RAIL_MultiTimer_t *tmr, - RAIL_Time_t expirationTime, - RAIL_TimeMode_t expirationMode, - RAIL_MultiTimerCallback_t callback, - void *cbArg); - -/** - * Stop the currently scheduled RAIL multitimer. - * - * @param[in,out] tmr A RAIL timer instance handle. - * - * @return - * true if the timer was successfully canceled. - * false if the timer was not running. - * - * Cancels the timer. If this function is called before the timer expires, - * the cb callback specified in the earlier RAIL_SetTimer() call will never - * be called. - */ -bool RAIL_CancelMultiTimer(RAIL_MultiTimer_t *tmr); - -/** - * Check if a given timer is running. - * - * @param[in] tmr A pointer to the timer structure to query. - * - * @return - * true if the timer is running. - * false if the timer is not running. - */ -bool RAIL_IsMultiTimerRunning(RAIL_MultiTimer_t *tmr); - -/** - * Check if a given timer has expired. - * - * @param[in] tmr A pointer to the timer structure to query. - * - * @return - * true if the timer is expired. - * false if the timer is running. - */ -bool RAIL_IsMultiTimerExpired(RAIL_MultiTimer_t *tmr); - -/** - * Get time left before a given timer instance expires. - * - * @param[in] tmr A pointer to the timer structure to query. - * @param[in] timeMode Indicates how the function provides the time - * remaining. By choosing \ref - * RAIL_TimeMode_t::RAIL_TIME_ABSOLUTE, the function returns the - * absolute expiration time, and by choosing \ref - * RAIL_TimeMode_t::RAIL_TIME_DELAY, the function returns the - * amount of time remaining before the timer's expiration. - * - * @return - * Time left expressed in RAIL's time units. - * 0 if the soft timer is not running or has already expired. - */ -RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, - RAIL_TimeMode_t timeMode); - -/** @} */ // end of group System_Timing - -/****************************************************************************** - * Sleep APIs - *****************************************************************************/ -/// @addtogroup Sleep -/// @brief These APIs help when putting the system to an EM2/EM3/EM4 sleep -/// states where the high frequency clock is disabled. -/// @{ -/// -/// The RAIL library has its own timebase and the ability to schedule operations -/// into the future. When going to any power mode that disables the HF clock -/// used for the radio (EM2/EM3/EM4), it is important that this timebase is -/// synchronized to a running LFCLK and the chip is set to wake up before the -/// next scheduled event. -/// If RAIL has not been configured to use the power manager, -/// \ref RAIL_Sleep and \ref RAIL_Wake must be called for performing this -/// synchronization. -/// If RAIL has been configured to use the power manager, -/// \ref RAIL_InitPowerManager, it will automatically perform timer -/// synchronization based on the selected \ref RAIL_TimerSyncConfig_t. Calls to -/// \ref RAIL_Sleep and \ref RAIL_Wake are unsupported in such a scenario. -/// -/// Following example code snippets demonstrate synchronizing the timebase -/// with and without timer synchronization: -/// -/// Sleep with timer synchronization: -/// -/// When sleeping with timer synchronization, you must first get the required -/// LFCLK up and running and leave it running across sleep so that the high -/// frequency clock that drives the RAIL time base can be synchronized to it. -/// The \ref RAIL_Sleep() API will also set up a wake event on the timer to wake -/// up wakeupTime before the next timer event so that it can run successfully. -/// See the \ref efr32_main sections on Low-Frequency Clocks and RAIL Timer -/// Synchronization for more setup details. -/// -/// This is useful when maintaining packet timestamps -/// across sleep or use the scheduled RX/TX APIs while sleeping in between. It -/// does take more time and code to do the synchronization. If your -/// application does not need this, it should be avoided. -/// -/// Example (without Power Manager): -/// @code{.c} -/// #include -/// #include -/// -/// extern RAIL_Handle_t railHandle; -/// // Wakeup time for your crystal/board/chip combination -/// extern uint32_t wakeupTime; -/// -/// void main(void) { -/// RAIL_Status_t status; -/// bool shouldSleep = false; -/// -/// // This function depends on your board/chip but it must enable the LFCLK -/// // you intend to use for RTCC sync before we configure sleep as that function -/// // will attempt to auto detect the clock. -/// BoardSetupLFCLK() -/// -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// -/// // Application main loop -/// while(1) { -/// // ... do normal app stuff and set shouldSleep to true when we want to -/// // sleep -/// if (shouldSleep) { -/// bool sleepAllowed = false; -/// -/// // Go critical to assess sleep decisions -/// CORE_ENTER_CRITICAL(); -/// if (RAIL_Sleep(wakeupTime, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { -/// printf("Error trying to go to sleep!"); -/// CORE_EXIT_CRITICAL(); -/// continue; -/// } -/// if (sleepAllowed) { -/// // Go to sleep -/// } -/// // Wakeup and sync the RAIL timebase back up -/// RAIL_Wake(0); -/// CORE_EXIT_CRITICAL(); -/// } -/// } -/// } -/// @endcode -/// -/// Example (with Power Manager): -/// @code{.c} -/// #include -/// #include -/// #include -/// -/// extern RAIL_Handle_t railHandle; -/// -/// void main(void) { -/// RAIL_Status_t status; -/// bool shouldSleep = false; -/// -/// // This function depends on your board/chip but it must enable the LFCLK -/// // you intend to use for RTCC sync before we configure sleep as that function -/// // will attempt to auto detect the clock. -/// BoardSetupLFCLK(); -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// // Initialize application-level power manager service -/// sl_power_manager_init(); -/// // Initialize RAIL library's use of the power manager -/// RAIL_InitPowerManager(); -/// -/// // Application main loop -/// while(1) { -/// // ... do normal app stuff and set shouldSleep to true when we want to -/// // sleep -/// if (shouldSleep) { -/// // Let the CPU go to sleep if the system allows it. -/// sl_power_manager_sleep(); -/// } -/// } -/// } -/// @endcode -/// -/// RAIL APIs such as, \ref RAIL_StartScheduledTx, \ref RAIL_ScheduleRx, -/// \ref RAIL_SetTimer, \ref RAIL_SetMultiTimer can be used to schedule periodic -/// wakeups to perform a scheduled operation. The call to -/// sl_power_manager_sleep() in the main loop ensures that the device sleeps -/// until the scheduled operation is due. -/// Upon completion, each instantaneous or scheduled RX/TX operation will -/// indicate radio busy to the power manager to allow the application to -/// service the RAIL event and perform subsequent operations before going to -/// sleep. Therefore, it is important that the application idle the radio by either -/// calling \ref RAIL_Idle or \ref RAIL_YieldRadio. -/// If the radio transitions to RX after an RX or TX operation, -/// always call \ref RAIL_Idle in order transition to a lower sleep state. -/// If the radio transitions to idle after an RX or TX operation, -/// \ref RAIL_YieldRadio should suffice in indicating to the power manager -/// that the radio is no longer busy and the device can sleep. -/// -/// The following example shows scheduling periodic TX on getting a TX completion -/// event: -/// @code{.c} -/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { -/// // Omitting other event handlers -/// if (events & RAIL_EVENTS_TX_COMPLETION) { -/// // Schedule the next TX. -/// RAIL_ScheduleTxConfig_t config = { -/// .when = (RAIL_Time_t)parameters->startTime, -/// .mode = (RAIL_TimeMode_t)parameters->startTimeMode -/// }; -/// (void)RAIL_StartScheduledTx(radio.handle, channel, 0, &config, NULL); -/// } -/// } -/// @endcode -/// -/// @note The above code assumes that RAIL automatic state transitions after TX -/// are idle. Set \ref RAIL_SetTxTransitions to ensure the right state -/// transitions. Radio must be idle for the device to enter EM2 or lower -/// energy mode. -/// -/// @note When using the power manager, usage of \ref RAIL_YieldRadio in -/// single protocol RAIL is similar to its usage in multiprotocol RAIL. -/// See \ref rail_radio_scheduler_yield for more details. -/// -/// @note Back to back scheduled operations do not require an explicit call to -/// \ref RAIL_YieldRadio if the radio transitions to idle. -/// -/// Sleep without timer synchronization: -/// -/// When sleeping without timer synchronization, you are free to enable only the -/// LFCLKs and wake sources required by the application. RAIL will not attempt -/// to configure any wake events and may miss anything that occurs over sleep. -/// -/// This is useful when your application does not care about -/// packet timestamps or scheduling operations accurately over sleep. -/// -/// Example (without Power Manager): -/// @code{.c} -/// #include -/// #include -/// -/// extern RAIL_Handle_t railHandle; -/// -/// void main(void) { -/// RAIL_Status_t status; -/// bool shouldSleep = false; -/// -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// -/// // Application main loop -/// while(1) { -/// // ... do normal app stuff and set shouldSleep to true when we want to -/// // sleep -/// if (shouldSleep) { -/// bool sleepAllowed = false; -/// uint32_t sleepTime = 0; -/// -/// // Go critical to assess sleep decisions -/// CORE_ENTER_CRITICAL(); -/// if (RAIL_Sleep(0, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { -/// printf("Error trying to go to sleep!"); -/// CORE_EXIT_CRITICAL(); -/// continue; -/// } -/// if (sleepAllowed) { -/// // Go to sleep and optionally update sleepTime to the correct value -/// // in microseconds -/// } -/// // Wakeup and sync the RAIL timebase back up -/// RAIL_Wake(sleepTime); -/// CORE_EXIT_CRITICAL(); -/// } -/// } -/// } -/// @endcode -/// -/// Example (with Power Manager): -/// @code{.c} -/// #include -/// #include -/// #include -/// -/// extern RAIL_Handle_t railHandle; -/// -/// void main(void) { -/// RAIL_Status_t status; -/// bool shouldSleep = false; -/// -/// // This function depends on your board/chip but it must enable the LFCLK -/// // you intend to use for RTCC sync before we configure sleep as that function -/// // will attempt to auto detect the clock. -/// BoardSetupLFCLK(); -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// // Initialize application-level power manager service -/// sl_power_manager_init(); -/// // Initialize RAIL library's use of the power manager -/// RAIL_InitPowerManager(); -/// -/// // Application main loop -/// while(1) { -/// // ... do normal app stuff and set shouldSleep to true when we want to -/// // sleep -/// if (shouldSleep) { -/// // Let the CPU go to sleep if the system allows it. -/// sl_power_manager_sleep(); -/// } -/// } -/// } -/// @endcode -/** - * Configure RAIL timer synchronization. This function is optional to implement. - * - * @param[in,out] timerSyncConfig A pointer to the \ref RAIL_TimerSyncConfig_t - * structure containing the configuration parameters for timer sync. The - * \ref RAIL_TimerSyncConfig_t::sleep field is ignored in this call. - * - * This function is called during \ref RAIL_ConfigSleep to allow an application - * to configure the PRS and RTCC channels used for timer sync to values other - * than their defaults. The default channels are populated in timerSyncConfig and - * can be overwritten by the application. If this function is not implemented by the - * application, a default implementation from within the RAIL library will be used - * that simply maintains the default channel values in timerSyncConfig. - * - * If an unsupported channel is selected by the application, \ref RAIL_ConfigSleep - * will return \ref RAIL_STATUS_INVALID_PARAMETER. - * - * @code{.c} - * void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig) - * { - * timerSyncConfig->prsChannel = MY_TIMERSYNC_PRS_CHANNEL; - * timerSyncConfig->rtccChannel = MY_TIMERSYNC_RTCC_CHANNEL; - * } - * @endcode - */ -void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig); - -/** - * Initialize RAIL timer synchronization. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] sleepConfig A sleep configuration. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle, - RAIL_SleepConfig_t sleepConfig); - -/** - * Initialize RAIL timer synchronization. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] syncConfig A pointer to the timer synchronization configuration. - * - * The default structure used to enable timer synchronization across sleep is - * \ref RAIL_TIMER_SYNC_DEFAULT. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ConfigSleepAlt(RAIL_Handle_t railHandle, - RAIL_TimerSyncConfig_t *syncConfig); - -/** - * Stop the RAIL timer and prepare RAIL for sleep. - * - * @param[in] wakeupProcessTime Time in microseconds that the application and - * hardware need to recover from sleep state. - * @param[out] deepSleepAllowed - * true - system can go to deep sleep. - * false - system should not go to deep sleep. Deep sleep should be blocked - * in this case. - * - * @return Status code indicating success of the function call. - * - * @warning The active RAIL configuration must be idle to enable sleep. - * - * @note This API must not be called if RAIL Power Manager is initialized. - */ -RAIL_Status_t RAIL_Sleep(uint16_t wakeupProcessTime, bool *deepSleepAllowed); - -/** - * Wake RAIL from sleep and restart the RAIL timer. - * - * @param[in] elapsedTime Add the sleep duration to the RAIL timer - * before restarting the RAIL timer. - * - * @return Status code indicating success of the function call. - * - * If the timer sync was enabled by \ref RAIL_ConfigSleep, synchronize the RAIL - * timer using an alternate timer. Otherwise, add elapsedTime to the RAIL - * timer. - * - * @note This API must not be called if RAIL Power Manager is initialized. - */ -RAIL_Status_t RAIL_Wake(RAIL_Time_t elapsedTime); - -/** - * Initialize RAIL Power Manager. - * - * @return Status code indicating success of the function call. - * - * @note Call this function only when the application is built - * and initialized with Power Manager plugin. - * RAIL will perform timer synchronization, upon transitioning from EM2 or lower - * to EM1 or higher energy mode or vice-versa, in the Power Manager EM - * transition callback. Since EM transition callbacks are not called in a - * deterministic order, it is suggested to not call any RAIL time dependent APIs - * in an EM transition callback. - */ -RAIL_Status_t RAIL_InitPowerManager(void); - -/** - * Stop the RAIL Power Manager. - * - * @return Status code indicating success of the function call. - * - * @note The active RAIL configuration must be idle to disable radio - * power manager and there should be no outstanding requirements by - * radio power manager. - */ -RAIL_Status_t RAIL_DeinitPowerManager(void); - -/** @} */ // end of group Sleep - -/****************************************************************************** - * Events - *****************************************************************************/ -/** - * @addtogroup Events - * @brief APIs related to events - * @{ - */ - -/** - * Configure radio events. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mask A bitmask of events to configure. - * @param[in] events A bitmask of events to trigger \ref RAIL_Config_t::eventsCallback - * For a full list of available callbacks, see - * RAIL_EVENT_* set of defines. - * @return Status code indicating success of the function call. - * - * Sets up which radio interrupts generate a RAIL event. The full list of - * options is in \ref RAIL_Events_t. - */ -RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, - RAIL_Events_t mask, - RAIL_Events_t events); - -/** @} */ // end of group Events - -/****************************************************************************** - * Data Management - *****************************************************************************/ -/// @addtogroup Data_Management Data Management -/// @brief Data management functions -/// -/// These functions allow the application to choose how data is presented to -/// the application. RAIL provides data in a packet-based method or in a -/// FIFO-based method. As originally conceived, -/// \ref RAIL_DataMethod_t::PACKET_MODE was designed for handling packets -/// that fit within RAIL's FIFOs while \ref RAIL_DataMethod_t::FIFO_MODE -/// was designed for handling packets larger than RAIL's FIFOs could hold. -/// Conceptually it is still useful to think of these modes this way, but -/// functionally their distinction has become blurred by improvements in -/// RAIL's flexibility -- applications now have much more control over both -/// receive and transmit FIFO sizes, and the FIFO-management and threshold -/// APIs and related events are no longer restricted to \ref -/// RAIL_DataMethod_t::FIFO_MODE operation but can be used in \ref -/// RAIL_DataMethod_t::PACKET_MODE too. -/// -/// The application can configure RAIL data management through -/// RAIL_ConfigData(). This function allows the application to specify the type -/// of radio data (\ref RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and -/// the method of interacting with data (\ref RAIL_DataMethod_t). By default, -/// RAIL configures TX and RX both with packet data source and \ref -/// RAIL_DataMethod_t::PACKET_MODE. -/// -/// For transmit, \ref RAIL_DataMethod_t::PACKET_MODE and \ref -/// RAIL_DataMethod_t::FIFO_MODE are functionally the same: -/// - When not actively transmitting, load a packet's initial transmit -/// data using RAIL_WriteTxFifo() with reset set to true. Alternatively -/// this data copying can be avoided by changing the transmit FIFO to an -/// already-loaded section of memory with \ref RAIL_SetTxFifo(). -/// - When actively transmitting, load remaining transmit data with -/// RAIL_WriteTxFifo() with reset set to false. -/// - If transmit packets exceed the FIFO size, set the transmit FIFO -/// threshold through RAIL_SetTxFifoThreshold(). The \ref -/// RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY -/// will occur telling the application to load more TX packet data, if -/// needed, to prevent a \ref RAIL_EVENT_TX_UNDERFLOW event from occurring. -/// One can get how much space is available in the transmit FIFO for more -/// transmit data through RAIL_GetTxFifoSpaceAvailable(). -/// - After transmit completes, the transmit FIFO can be manually reset -/// with RAIL_ResetFifo(), but this should rarely be necessary. -/// -/// The transmit FIFO is specified by the application and its size is -/// the value returned from the most recent call to RAIL_SetTxFifo(). -/// The transmit FIFO is edge-based in that it only provides the \ref -/// RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event once when the threshold is crossed -/// in the emptying direction. -/// -/// For receive, the distinction between \ref RAIL_DataMethod_t::PACKET_MODE -/// and \ref RAIL_DataMethod_t::FIFO_MODE basically boils down to how -/// unsuccessfully-received packets are handled. In \ref -/// RAIL_DataMethod_t::PACKET_MODE, data from such packets is automatically -/// rolled back as if the packet was never received, while in \ref -/// RAIL_DataMethod_t::FIFO_MODE, rollback does not occur putting more onus -/// on the application to deal with that data. -/// -/// In receive \ref RAIL_DataMethod_t::PACKET_MODE data management: -/// - Packet lengths are determined from the Radio Configurator configuration -/// and can be read out at the end using \ref RAIL_GetRxPacketInfo(). -/// - Received packet data is made available on successful packet completion -/// via \ref RAIL_Config_t::eventsCallback with \ref -/// RAIL_EVENT_RX_PACKET_RECEIVED which can then use RAIL_GetRxPacketInfo() -/// and RAIL_GetRxPacketDetailsAlt() to access packet information and -/// RAIL_PeekRxPacket() to access packet data. -/// - Filtered, Aborted, or FrameError received packet data is automatically -/// rolled back (dropped) without the application needing to worry about -/// consuming it. -/// The application can choose to not even be bothered with the events -/// related to such packets: \ref RAIL_EVENT_RX_ADDRESS_FILTERED, -/// \ref RAIL_EVENT_RX_PACKET_ABORTED, or \ref RAIL_EVENT_RX_FRAME_ERROR. -/// -/// In receive \ref RAIL_DataMethod_t::FIFO_MODE data management: -/// - Packet Lengths are determined from the Radio Configurator configuration -/// or by application knowledge of packet payload structure. -/// - Received data can be retrieved prior to packet completion through -/// RAIL_ReadRxFifo() and is never rolled back on Filtered, Aborted, or -/// FrameError packets. The application should enable and handle these -/// events so it can flush any packet data it's already retrieved. -/// - After packet completion, remaining packet data for Filtered, Aborted, -/// or FrameError packets remains in the FIFO and the appropriate event is -/// triggered to the user. This data may be consumed in the callback unlike -/// in packet mode where it is automatically rolled back. At the end of the -/// callback all remaining data in the FIFO will be cleaned up as usual. -/// Keep in mind that RAIL_GetRxPacketDetailsAlt() provides packet detailed -/// information only for successfully received packets. -/// -/// Common receive data management features: -/// - Set the receive FIFO threshold through RAIL_SetRxFifoThreshold(). The -/// \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL -/// will occur telling the application to consume some RX packet data to -/// prevent a \ref RAIL_EVENT_RX_FIFO_OVERFLOW event from occurring. -/// - Get receive FIFO count information through -/// RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST) -/// (or RAIL_GetRxFifoBytesAvailable()). -/// - After receive completes and all its data has been consumed, the receive -/// FIFO can be manually reset with RAIL_ResetFifo(), though this should -/// rarely be necessary and should only be done with the radio idle. -/// -/// When trying to determine an appropriate threshold, the application needs -/// to know the size of each FIFO. The default receive FIFO is internal to RAIL -/// with a size of 512 bytes. This can be changed, however, using -/// \ref RAIL_SetRxFifo() and the default may be removed entirely by calling -/// this from the RAILCb_SetupRxFifo() callback. The receive FIFO event is -/// level-based in that the \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will -/// constantly pend if the threshold is exceeded. This normally means that -/// inside this event's callback, the application should empty enough of the FIFO -/// to go under the threshold. To defer reading the FIFO to main context, the -/// application can disable or re-enable the receive FIFO threshold event using -/// RAIL_ConfigEvents() with the mask \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL. -/// -/// The receive FIFO can store multiple packets and processing of a packet can -/// be deferred from the RAIL event callback to main-loop processing -/// by using RAIL_HoldRxPacket() in the event callback and -/// RAIL_ReleaseRxPacket() in the main-loop. -/// On some platforms, the receive FIFO is supplemented by an internal -/// fixed-size packet metadata FIFO that limits the number of packets -/// RAIL and applications can hold onto for deferred processing. -/// See chip-specific documentation, such as \ref efr32_main, for more -/// information. Note that when using multiprotocol the receive FIFO is reset -/// prior to a protocol switch so held packets will be lost if not processed -/// before then. -/// -/// While \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL occurs solely based on the -/// state of the receive FIFO used for packet data, both -/// \ref RAIL_EVENT_RX_FIFO_FULL and \ref RAIL_EVENT_RX_FIFO_OVERFLOW -/// can occur coincident with packet completion when either that or the -/// internal packet metadata FIFO fills or overflows. -/// \ref RAIL_EVENT_RX_FIFO_FULL informs the application it should -/// immediately process and free up the oldest packets/data to make room -/// for new packets/data, reducing the possibility of packet/data loss -/// and \ref RAIL_EVENT_RX_FIFO_OVERFLOW. -/// -/// Before a packet is fully received you can always use -/// RAIL_PeekRxPacket() to look at the contents. In FIFO mode, you may also -/// consume its data with \ref RAIL_ReadRxFifo(). Remember that none of these -/// APIs will read across a packet boundary (even in FIFO mode) so you will -/// need to handle each received packet individually. -/// -/// While RAIL defaults to \ref RAIL_DataMethod_t::PACKET_MODE, the -/// application can explicitly initialize RAIL for \ref -/// RAIL_DataMethod_t::PACKET_MODE in the following manner: -/// @code{.c} -/// extern RAIL_Handle_t railHandle; -/// static const RAIL_DataConfig_t railDataConfig = { -/// .txSource = TX_PACKET_DATA, -/// .rxSource = RX_PACKET_DATA, -/// .txMethod = PACKET_MODE, -/// .rxMethod = PACKET_MODE, -/// }; -/// -/// status = RAIL_ConfigData(railHandle, &railDataConfig); -/// -/// // Events that can occur in Packet Mode: -/// // RAIL_EVENT_TX_PACKET_SENT -/// // RAIL_EVENT_RX_PACKET_RECEIVED -/// // and optionally (packet data automatically dropped): -/// // RAIL_EVENT_RX_ADDRESS_FILTERED -/// // RAIL_EVENT_RX_PACKET_ABORTED -/// // RAIL_EVENT_RX_FRAME_ERROR -/// // and if enabled: -/// // RAIL_EVENT_TX_UNDERFLOW -/// // RAIL_EVENT_TXACK_UNDERFLOW -/// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY -/// // RAIL_EVENT_RX_FIFO_ALMOST_FULL -/// @endcode -/// -/// Initializing RAIL for \ref RAIL_DataMethod_t::FIFO_MODE requires a few -/// more function calls: -/// @code{.c} -/// extern RAIL_Handle_t railHandle; -/// static const RAIL_DataConfig_t railDataConfig = { -/// .txSource = TX_PACKET_DATA, -/// .rxSource = RX_PACKET_DATA, -/// .txMethod = FIFO_MODE, -/// .rxMethod = FIFO_MODE, -/// }; -/// -/// status = RAIL_ConfigData(railHandle, &railDataConfig); -/// -/// // Gets the size of the FIFOs. -/// // Assume that the transmit and receive FIFOs are the same size -/// uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable(railHandle); -/// -/// // Sets the transmit and receive FIFO thresholds. -/// // For this example, set the threshold in the middle of each FIFO. -/// RAIL_SetRxFifoThreshold(railHandle, fifoSize / 2); -/// RAIL_SetTxFifoThreshold(railHandle, fifoSize / 2); -/// -/// // Events that can occur in FIFO mode: -/// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY -/// // RAIL_EVENT_TX_UNDERFLOW -/// // RAIL_EVENT_TXACK_UNDERFLOW -/// // RAIL_EVENT_TX_PACKET_SENT -/// // RAIL_EVENT_RX_FIFO_ALMOST_FULL -/// // RAIL_EVENT_RX_FIFO_OVERFLOW -/// // RAIL_EVENT_RX_ADDRESS_FILTERED -/// // RAIL_EVENT_RX_PACKET_ABORTED -/// // RAIL_EVENT_RX_FRAME_ERROR -/// // RAIL_EVENT_RX_PACKET_RECEIVED -/// @endcode -/// -/// On receive, an application can use a different \ref RAIL_RxDataSource_t that -/// is only compatible with \ref RAIL_DataMethod_t::FIFO_MODE. All that differs -/// from the FIFO mode example above is the RAIL_DataConfig_t::rxSource setting. -/// IQ data samples are taken at the hardware's oversample rate and the amount -/// of data can easily overwhelm the CPU processing time. The sample rate -/// depends on the chosen PHY, as determined by the data rate and the decimation -/// chain. It is not recommended to use the IQ data source with sample -/// rates above 300 k samples/second because the CPU might not be able to keep up -/// with the data stream. Depending on the application and the needed CPU -/// bandwidth, slower data rates may be required. On EFR32xG22 and later -/// platforms, it is recommended to reset the RX buffer before initiating a -/// receive for all modes except \ref RAIL_RxDataSource_t::RX_PACKET_DATA since -/// the RX buffer has to be 32-bit aligned. If the buffer is not reset -/// but is 32-bit aligned, capture is performed on the remaining space available. -/// If the buffer is not reset and is not 32-bit aligned, then -/// RAIL_ConfigData() returns \ref RAIL_STATUS_INVALID_STATE. -/// @code{.c} -/// // Reset RX buffer (EFR32xG22 and later platforms) -/// RAIL_ResetFifo(railHandle, false, true); -/// -/// // IQ data is provided into the receive FIFO. -/// static const RAIL_DataConfig_t railDataConfig = { -/// .txSource = TX_PACKET_DATA, -/// .rxSource = RX_IQDATA_FILTLSB, -/// .txMethod = FIFO_MODE, -/// .rxMethod = FIFO_MODE, -/// }; -/// -/// // IQ data comes in the following format when reading out of the FIFO: -/// //------------------------------------ -/// // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] | -/// //------------------------------------ -/// @endcode -/// -/// @{ - -/** - * RAIL data management configuration - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] dataConfig RAIL data configuration structure. - * @return Status code indicating success of the function call. - * - * This function configures how RAIL manages data. The application can - * configure RAIL to receive data in a packet-based or FIFO-based manner. - * \ref RAIL_DataMethod_t::FIFO_MODE is necessary to receive packets larger - * than the radio's receive FIFO. It is also required for receive data - * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. - * - * Generally with \ref RAIL_DataMethod_t::FIFO_MODE, the application sets - * appropriate FIFO thresholds via RAIL_SetTxFifoThreshold() and - * RAIL_SetRxFifoThreshold() and then enables and handles the - * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event callback (to feed more packet - * data via RAIL_WriteTxFifo() before the FIFO underflows) and the \ref - * RAIL_EVENT_RX_FIFO_ALMOST_FULL event callback (to consume packet data - * via RAIL_ReadRxFifo() before the receive FIFO overflows). - * - * When configuring TX for \ref RAIL_DataMethod_t::FIFO_MODE, this - * function resets the transmit FIFO. When configuring TX or RX for - * \ref RAIL_DataMethod_t::PACKET_MODE, this function will reset - * the corresponding FIFO thresholds such that they won't trigger the - * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL or \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY - * events. - * - * When \ref RAIL_DataConfig_t::rxMethod is set to \ref - * RAIL_DataMethod_t::FIFO_MODE, the radio won't drop packet data of - * aborted or CRC error packets, but will present it to the application - * to deal with accordingly. On completion of erroneous packets, the - * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_ABORTED, - * \ref RAIL_EVENT_RX_FRAME_ERROR, or \ref RAIL_EVENT_RX_ADDRESS_FILTERED will - * tell the application it can drop any data it read via RAIL_ReadRxFifo() during reception. - * For CRC error packets when the \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS - * RX option is in effect, the application should check for that from the - * \ref RAIL_RxPacketStatus_t obtained by calling RAIL_GetRxPacketInfo(). - * RAIL will automatically flush any remaining packet data after reporting - * one of these packet completion events or the application can explicitly - * flush it by calling RAIL_ReleaseRxPacket(). - * - * When \ref RAIL_DataConfig_t::rxMethod is set to \ref - * RAIL_DataMethod_t::PACKET_MODE, the radio will roll back (drop) all packet - * data associated with aborted packets including those with CRC errors - * (unless configured to ignore CRC errors via the - * \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS RX option). The application will - * never have to deal with packet data from these packets. - * In either mode, the application can set RX options as needed. - * - * When \ref RAIL_DataConfig_t::rxSource is set to a value other than - * \ref RX_PACKET_DATA and \ref RAIL_Config_t::eventsCallback - * \ref RAIL_EVENT_RX_FIFO_OVERFLOW is enabled RX will be terminated - * if a RX FIFO overflow occurs. If \ref RAIL_EVENT_RX_FIFO_OVERFLOW - * is not enabled, data will be discarded until the overflow condition - * is resolved. To continue capturing data RX must be restarted using - * \ref RAIL_StartRx(). - * - */ -RAIL_Status_t RAIL_ConfigData(RAIL_Handle_t railHandle, - const RAIL_DataConfig_t *dataConfig); - -/** - * Write data to the transmit FIFO previously established by RAIL_SetTxFifo(). - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] dataPtr An application-provided pointer to transmit data. - * @param[in] writeLength A number of bytes to write to the transmit FIFO. - * @param[in] reset If true, resets transmit FIFO before writing the data. - * @return The number of bytes written to the transmit FIFO. - * - * This function reads data from the provided dataPtr and writes it to the transmit - * FIFO that was previously established by RAIL_SetTxFifo(). - * If the requested writeLength exceeds the current number of bytes open - * in the transmit FIFO, the function only writes until the transmit FIFO - * is full. The function returns the number of bytes written to the transmit - * FIFO or returns zero if railHandle is NULL or if the transmit FIFO is full. - * - * @note The protocol's packet configuration, as set up by the radio - * configurator or via RAIL_SetFixedLength(), determines how many - * bytes of data are consumed from the transmit FIFO for a successful transmit - * operation, not the writeLength value passed in. If not enough data has - * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will - * occur. If too much data is put into the transmit FIFO, the extra data will - * either become the first bytes - * sent in a subsequent packet, or will be thrown away if the FIFO gets - * reset prior to the next transmit. In general, the proper number of - * packet bytes to put into the transmit FIFO are all payload bytes except - * for any CRC bytes, which the packet configuration causes to be sent - * automatically. - * - * @note This function does not create a critical section but, depending on the - * application, a critical section could be appropriate. - */ -uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, - const uint8_t *dataPtr, - uint16_t writeLength, - bool reset); - -/** - * Set the address of the transmit FIFO, a circular buffer used for TX data. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] addr An appropriately-aligned (see below) pointer to a read-write memory - * location in RAM used as the transmit FIFO. This memory must persist until the next - * call to this function or \ref RAIL_SetTxFifoAlt. - * @param[in] initLength A number of initial bytes already in the transmit FIFO. - * @param[in] size A desired size of the transmit FIFO in bytes. - * @return Returns the FIFO size in bytes, 0 if an error occurs. - * - * This function sets the memory location for the transmit FIFO. \ref RAIL_SetTxFifo or - * \ref RAIL_SetTxFifoAlt must be called at least once before any transmit operations occur. - * - * FIFO size can be determined by the return value of this function. The - * chosen size is determined based on the available FIFO sizes supported by the - * hardware. Similarly, some hardware has stricter FIFO alignment requirements; - * 32-bit alignment provides the maximum portability across all RAIL platforms. - * For more on supported FIFO sizes and alignments, see chip-specific - * documentation, such as \ref efr32_main. The returned FIFO size will be the - * closest allowed size less than or equal to the passed in size parameter, - * unless the size parameter is smaller than the minimum FIFO size, in that case - * 0 is returned. If the initLength parameter is larger than the returned - * size, the FIFO will be filled up to its size. - * - * A user may write to the custom memory location directly before calling this - * function, or use \ref RAIL_WriteTxFifo to write to the memory location after - * calling this function. Users must specify the initLength for - * previously-written memory to be set in the transmit FIFO. - * - * This function reserves the block of RAM starting at addr with a length of the - * returned FIFO size, which is used internally as a circular buffer for the - * transmit FIFO. It must be able to hold the entire FIFO size. The caller must - * guarantee that the custom FIFO remains intact and unchanged (except via calls - * to \ref RAIL_WriteTxFifo) until the next call to this function. - * - * @note The protocol's packet configuration, as set up by the radio - * configurator or via RAIL_SetFixedLength(), determines how many - * bytes of data are consumed from the transmit FIFO for a successful transmit - * operation, not the initLength value passed in. If not enough data has - * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will - * occur. If too much data is put into the transmit FIFO, the extra data - * will either become the first bytes - * sent in a subsequent packet, or will be thrown away if the FIFO gets - * reset prior to the next transmit. In general, the proper number of - * packet bytes to put into the transmit FIFO are all payload bytes except - * for any CRC bytes which the packet configuration causes to be sent - * automatically. - */ -uint16_t RAIL_SetTxFifo(RAIL_Handle_t railHandle, - uint8_t *addr, - uint16_t initLength, - uint16_t size); - -/** - * Set the address of the transmit FIFO, a circular buffer used for TX data which - * can start at offset distance from the FIFO base address. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] addr An appropriately-aligned (see \ref RAIL_SetTxFifo description) - * pointer to a read-write memory location in RAM used as the transmit FIFO. This memory - * must persist until the next call to this function or \ref RAIL_SetTxFifo. - * @param[in] startOffset A number of bytes defining the start position of the TX data - * from the transmit FIFO base address, only valid if initLength is not 0. - * @param[in] initLength The number of valid bytes already in the transmit FIFO after startOffset. - * @param[in] size A desired size of the transmit FIFO in bytes. - * @return Returns the FIFO size in bytes, 0 if an error occurs. - * - * This function is similar to \ref RAIL_SetTxFifo except a startOffset can be specified - * to indicate where the transmit packet data starts. This allows an application to - * place unaligned initial packet data within the aligned transmit FIFO (initLength > 0). - * Specifying a startOffset will not reduce the FIFO threshold or affect - * \ref RAIL_GetTxFifoSpaceAvailable(). - * \ref RAIL_SetTxFifo or \ref RAIL_SetTxFifoAlt must be called at least once before any transmit - * operations occur. - * FIFO size handling is quite same as \ref RAIL_SetTxFifo. Only difference is that if the - * initLength plus startOffset parameters are larger than the returned size, the FIFO - * will be filled up to its size from startOffset. - * Note that the startOffset is essentially forgotten after the next transmit -- - * i.e. it applies onto to the next transmit operation, and is not re-established when - * the transmit FIFO is reset. - */ -uint16_t RAIL_SetTxFifoAlt(RAIL_Handle_t railHandle, - uint8_t *addr, - uint16_t startOffset, - uint16_t initLength, - uint16_t size); -/** - * Set the address of the receive FIFO, a circular buffer used for RX data. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] addr A pointer to a read-write memory location in RAM used as - * the receive FIFO. This memory must persist until the next call to this - * function. - * @param[in,out] size A desired size of the receive FIFO in bytes. This will - * be populated with the actual size during the function call. - * @return Status code indicating success of the function call. - * - * This function sets the memory location for the receive FIFO. It - * must be called at least once before any receive operations occur. - * - * @note After it is called, any prior receive FIFO is orphaned. To avoid - * orphaning the default internal 512-byte receive FIFO so it does - * not unnecessarily consume RAM resources in your application, - * implement \ref RAILCb_SetupRxFifo() to call this function. - * - * FIFO size can be determined by the return value of this function. The - * chosen size is determined based on the available FIFO sizes supported by the - * hardware. Similarly, some hardware has stricter FIFO alignment requirements; - * 32-bit alignment provides the maximum portability across all RAIL platforms. - * For more on supported FIFO sizes and alignments, see chip-specific - * documentation, such as \ref efr32_main. The returned FIFO size will be the - * closest allowed size less than or equal to the passed in size parameter, - * unless the size parameter is smaller than the minimum FIFO size. - * - * This function reserves the block of RAM starting at addr with a length - * of size, which is used internally as a circular buffer for the receive FIFO. - * It must be able to hold the entire FIFO size. The caller must guarantee that - * the custom FIFO remains intact and unchanged (except via incoming packet data - * being written) until the next call to this function. - * - * In multiprotocol, RAIL currently shares one receive FIFO across all - * protocols. This function will return \ref RAIL_STATUS_INVALID_STATE if the - * requested \ref RAIL_Handle_t is not active. - */ -RAIL_Status_t RAIL_SetRxFifo(RAIL_Handle_t railHandle, - uint8_t *addr, - uint16_t *size); - -/// Set up the receive FIFO to use. This function is optional to implement. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @return Status code indicating success of the function call. -/// -/// This function is called during the \ref RAIL_Init process to set up the FIFO -/// to use for received packets. If not implemented by the application, -/// a default implementation from within the RAIL library will be used to -/// initialize an internal default 512-byte receive FIFO. -/// -/// If this function returns an error, the RAIL_Init process will fail. -/// -/// During this function, the application should generally call -/// \ref RAIL_SetRxFifo. If that does not happen, the application needs to -/// set up the receive FIFO via a call to \ref RAIL_SetRxFifo before attempting -/// to receive any packets. An example implementation may look like the following: -/// @code{.c} -/// #define RX_FIFO_SIZE 1024 -/// static uint8_t rxFifo[RX_FIFO_SIZE]; -/// -/// RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle) -/// { -/// uint16_t rxFifoSize = RX_FIFO_SIZE; -/// RAIL_Status_t status = RAIL_SetRxFifo(railHandle, &rxFifo[0], &rxFifoSize); -/// if (rxFifoSize != RX_FIFO_SIZE) { -/// // We set up an incorrect FIFO size -/// return RAIL_STATUS_INVALID_PARAMETER; -/// } -/// if (status == RAIL_STATUS_INVALID_STATE) { -/// // Allow failures due to multiprotocol -/// return RAIL_STATUS_NO_ERROR; -/// } -/// return status; -/// } -/// @endcode -RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle); - -/** - * Read packet data from RAIL's internal receive FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] dataPtr An application-provided pointer to store data. - * If NULL, the data is thrown away rather than copied out. - * @param[in] readLength A number of packet bytes to read from the FIFO. - * @return The number of packet bytes read from the receive FIFO. - * - * This function reads packet data from the head of receive FIFO and - * writes it to the provided dataPtr. It does not permit reading more - * data than is available in the FIFO, nor does it permit reading more - * data than remains in the oldest unreleased packet. - * - * Because this function does not have a critical section, use it - * only in one context or make sure function calls are protected to prevent - * buffer corruption. - * - * @warning This function is intended for use only with \ref - * RAIL_DataMethod_t::FIFO_MODE and should never be called in \ref - * RAIL_DataMethod_t::PACKET_MODE where it could lead to receive FIFO - * corruption. - * - * @note When reading data from an arriving packet that is not yet complete, - * keep in mind its data is highly suspect because it has not yet passed - * any CRC integrity checking. Also note that the packet could be aborted, - * canceled, or fail momentarily, invalidating its data in Packet mode. - * Furthermore, there is a small chance towards the end of packet reception - * that the receive FIFO could include not only packet data received so far, - * but also some raw radio-appended info detail bytes that RAIL's - * packet-completion processing will subsequently deal with. It's up to the - * application to know its packet format well enough to avoid reading this - * info because it will corrupt the packet's details and possibly corrupt the - * receive FIFO. - */ -uint16_t RAIL_ReadRxFifo(RAIL_Handle_t railHandle, - uint8_t *dataPtr, - uint16_t readLength); - -/** - * Configure the RAIL transmit FIFO almost empty threshold. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] txThreshold The threshold below which the - * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event will fire. - * @return Configured transmit FIFO threshold value. - * - * This function configures the threshold for the transmit FIFO. When the - * number of bytes in the transmit FIFO falls below the configured threshold, - * \ref RAIL_Config_t::eventsCallback will fire with \ref - * RAIL_EVENT_TX_FIFO_ALMOST_EMPTY set. - * The txThreshold value should be smaller than or equal to the transmit - * FIFO size; higher values will be pegged to the FIFO size. - * A value of 0 or \ref RAIL_FIFO_THRESHOLD_DISABLED will disable the - * threshold, returning \ref RAIL_FIFO_THRESHOLD_DISABLED. - */ -uint16_t RAIL_SetTxFifoThreshold(RAIL_Handle_t railHandle, - uint16_t txThreshold); - -/** - * Configure the RAIL receive FIFO almost full threshold. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] rxThreshold The threshold above which the - * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will fire. - * @return Configured receive FIFO threshold value. - * - * This function configures the threshold for the receive FIFO. When the - * number of bytes of packet data in the receive FIFO exceeds the - * configured threshold, \ref RAIL_Config_t::eventsCallback will keep - * firing with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL set as long as the - * number of bytes in the receive FIFO exceeds the configured threshold - * value. The rxThreshold value should be smaller than the receive FIFO - * size; anything else, including a value of - * \ref RAIL_FIFO_THRESHOLD_DISABLED, will disable the threshold, - * returning \ref RAIL_FIFO_THRESHOLD_DISABLED. - * - * @note To avoid sticking in the event handler (even in idle state): - * 1. Disable the event (via the config events API or the - * \ref RAIL_FIFO_THRESHOLD_DISABLED parameter) - * 2. Increase FIFO threshold - * 3. Read the FIFO (that's not an option in - * \ref RAIL_DataMethod_t::PACKET_MODE) in the event handler - */ -uint16_t RAIL_SetRxFifoThreshold(RAIL_Handle_t railHandle, - uint16_t rxThreshold); - -/** - * Get the RAIL transmit FIFO almost empty threshold value. - * - * @param[in] railHandle A RAIL instance handle. - * @return Configured TX Threshold value. - * - * Retrieves the configured TX threshold value. - */ -uint16_t RAIL_GetTxFifoThreshold(RAIL_Handle_t railHandle); - -/** - * Get the RAIL receive FIFO almost full threshold value. - * - * @param[in] railHandle A RAIL instance handle. - * @return Configured RX Threshold value. - * - * Retrieves the configured RX threshold value. - */ -uint16_t RAIL_GetRxFifoThreshold(RAIL_Handle_t railHandle); - -/** - * Reset the RAIL transmit and/or receive FIFOs. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] txFifo If true, reset the transmit FIFO. - * @param[in] rxFifo If true, reset the receive FIFO. - * - * This function can reset each FIFO independently. - * The application should not reset the receive FIFO while receiving a frame, - * nor should it reset the transmit FIFO while transmitting a frame. - */ -void RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo); - -/** - * Get the number of bytes used in the receive FIFO. - * Only use this function in RX \ref RAIL_DataMethod_t::FIFO_MODE. - * Apps should use RAIL_GetRxPacketInfo() instead. - * - * @param[in] railHandle A RAIL instance handle. - * @return Number of bytes used in the receive FIFO. - * - * This function indicates how much packet-related data exists in the receive FIFO - * that could be read. - * - * @note The number of bytes returned may not just reflect the current - * packet's data but could also include raw appended info bytes added - * after successful packet reception and bytes from subsequently received - * packets. It is up to the app to never try to consume more than the - * packet's actual data when using the value returned here in a subsequent - * call to RAIL_ReadRxFifo(), otherwise the receive FIFO will be corrupted. - */ -uint16_t RAIL_GetRxFifoBytesAvailable(RAIL_Handle_t railHandle); - -/** - * Get the number of bytes unused in the transmit FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @return Number of bytes unused in the transmit FIFO. - * - * This function indicates how much space is available in the transmit FIFO for writing - * additional packet data. - */ -uint16_t RAIL_GetTxFifoSpaceAvailable(RAIL_Handle_t railHandle); - -/** @} */ // end of group Data_Management - -/****************************************************************************** - * State Transitions - *****************************************************************************/ -/** - * @addtogroup State_Transitions State Transitions - * @{ - */ - -/** - * Configure RAIL automatic state transitions after RX. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] transitions The state transitions to apply after reception. - * @return Status code indicating success of the function call. - * - * This function fails if unsupported transitions are passed in or if the - * radio is currently in the RX state. Success can transition to TX, RX, or - * IDLE, while error can transition to RX or IDLE. The timings of state - * transitions from the RX state are not guaranteed when packets are longer - * than 16 seconds on-air. - */ -RAIL_Status_t RAIL_SetRxTransitions(RAIL_Handle_t railHandle, - const RAIL_StateTransitions_t *transitions); - -/** - * Get the current RAIL automatic state transitions after RX. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] transitions The state transitions that apply after receive. - * @return Status code indicating a success of the function call. - * - * Retrieves the current state transitions after RX and stores them in the - * transitions argument. - */ -RAIL_Status_t RAIL_GetRxTransitions(RAIL_Handle_t railHandle, - RAIL_StateTransitions_t *transitions); - -/** - * Configure RAIL automatic state transitions after TX. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] transitions The state transitions to apply after transmission. - * @return Status code indicating a success of the function call. - * - * This function fails if unsupported transitions are passed in or if the - * radio is currently in the TX state. Success and error can each transition - * to RX or IDLE. For the ability to run repeated transmits, see - * \ref RAIL_SetNextTxRepeat. - */ -RAIL_Status_t RAIL_SetTxTransitions(RAIL_Handle_t railHandle, - const RAIL_StateTransitions_t *transitions); - -/** - * Get the current RAIL automatic state transitions after TX. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] transitions The state transitions that apply after transmission. - * @return Status code indicating a success of the function call. - * - * Retrieves the current state transitions after TX and stores them in the - * transitions argument. - */ -RAIL_Status_t RAIL_GetTxTransitions(RAIL_Handle_t railHandle, - RAIL_StateTransitions_t *transitions); - -/** - * Set up automatic repeated transmits after the next transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] repeatConfig The configuration structure for repeated transmits. - * @return Status code indicating a success of the function call. - * - * Repeated transmits will occur after an application-initiated transmit caused - * by calling one of the \ref Packet_TX APIs. The repetition will only occur - * after the first application-initiated transmit after this function is - * called. Future repeated transmits must be requested by calling this function - * again. - * - * Each repeated transmit that occurs will have full \ref PTI information, and - * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. - * - * If a TX error occurs during the repetition, the process will abort and the - * TX error transition from \ref RAIL_SetTxTransitions will be used. If the - * repetition completes successfully, then the TX success transition from - * \ref RAIL_SetTxTransitions will be used. - * - * Use \ref RAIL_GetTxPacketsRemaining() if need to know how many transmit - * completion events are expected before the repeating sequence is done, or - * how many were not performed due to a transmit error. - * - * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending - * repeated transmits. The state will also be cleared by another call to this - * function. A DMP switch will clear this - * state only if the initial transmit triggering the repeated transmits has - * started. - * - * One can change the repeated transmit configuration by re-calling - * this function with new parameters as long as that occurs prior to - * calling a \ref Packet_TX API. Passing a \ref - * RAIL_TxRepeatConfig_t::iterations count of 0 will prevent the next - * transmit from repeating. - * - * The application is responsible for populating the transmit data to be used - * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. - * Data will be transmitted from the Transmit FIFO. If the Transmit FIFO does - * not have sufficient data to transmit, a TX error will be caused and a \ref - * RAIL_EVENT_TX_UNDERFLOW will occur. In order to avoid an underflow, the - * application should queue data to be transmitted as early as possible. - * Consider using \ref RAIL_TX_OPTION_RESEND if the same packet data is to - * be repeated: then the Transmit FIFO only needs to be set/written once. - * - * Do not call this function after starting a transmit operation via a \ref - * Packet_TX API call or - * before processing the final transmit completion event of a prior transmit. - * This function will fail to (re)configure the repetition if a transmit of any - * kind is ongoing, including during the time between an initial transmit and - * the end of a previously-configured repetition. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_TX_TO_TX or the runtime - * call \ref RAIL_SupportsTxToTx() to check whether the platform supports - * this feature. - */ -RAIL_Status_t RAIL_SetNextTxRepeat(RAIL_Handle_t railHandle, - const RAIL_TxRepeatConfig_t *repeatConfig); - -/** - * Get the number of transmits remaining in a repeat operation. - * Must only be called from within event callback context when handling - * one of the \ref RAIL_EVENTS_TX_COMPLETION events. - * - * @param[in] railHandle A RAIL instance handle. - * @return transmits remaining as described below. - * - * If the TX completion event is \ref RAIL_EVENT_TX_PACKET_SENT the - * returned value indicates how many more such events are expected - * before the repeat transmit operation is done. Due to interrupt - * latency and timing, this may be an overcount if greater than 0 - * but is guaranteed to be accurate when 0. - * - * If the TX completion event is an error, the returned value indicates - * the number of requested transmits that were not performed. For - * \ref RAIL_EVENT_TX_ABORTED and \ref RAIL_EVENT_TX_UNDERFLOW the - * count does not include the failing transmit itself. For the other - * errors where a transmit never started or was blocked, the count - * would include the failing transmit, which may be one higher than - * the configured \ref RAIL_TxRepeatConfig_t::iterations if it was - * the original transmit that was blocked. - * - * If an infinite repeat was configured, this will return \ref - * RAIL_TX_REPEAT_INFINITE_ITERATIONS. - */ -uint16_t RAIL_GetTxPacketsRemaining(RAIL_Handle_t railHandle); - -/** - * Configure RAIL automatic state transition timing. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] timings The timings used to configure the RAIL state - * machine. This structure is overwritten with the actual times that were - * set, if an input timing is invalid. - * @return Status code indicating a success of the function call. - * - * The timings given are close to the actual transition time. However, - * a still uncharacterized software overhead occurs. Also, timings are not - * always adhered to when using an automatic transition after an error, due to - * the cleanup required to recover from the error. - */ -RAIL_Status_t RAIL_SetStateTiming(RAIL_Handle_t railHandle, - RAIL_StateTiming_t *timings); - -/** - * Place the radio into an idle state. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode The method for shutting down the radio. - * @param[in] wait Whether this function should wait for the radio to reach - * idle before returning. - * - * This function is used to remove the radio from TX and RX states. How these - * states are left is defined by the mode parameter. - * - * In multiprotocol, this API will also cause the radio to be yielded so that - * other tasks can be run. See \ref rail_radio_scheduler_yield for more details. - */ -void RAIL_Idle(RAIL_Handle_t railHandle, - RAIL_IdleMode_t mode, - bool wait); - -/** - * Get the current radio state. - * - * @param[in] railHandle A RAIL instance handle. - * @return An enumeration for the current radio state. - * - * Returns the state of the radio as a bitmask containing: - * \ref RAIL_RF_STATE_IDLE, \ref RAIL_RF_STATE_RX, \ref RAIL_RF_STATE_TX, - * and \ref RAIL_RF_STATE_ACTIVE. \ref RAIL_RF_STATE_IDLE, \ref - * RAIL_RF_STATE_RX, and \ref RAIL_RF_STATE_TX bits are mutually exclusive. - * The radio can transition through intermediate states, - * which are not reported but are instead considered part of the state - * most closely associated. For example, when the radio is warming up - * or shutting down the transmitter or receiver, this function returns - * \ref RAIL_RF_STATE_TX or \ref RAIL_RF_STATE_RX, respectively. - * When transitioning directly from RX to TX or vice-versa, this function - * returns the earlier state. - * - * @note For a more detailed radio state, see \ref RAIL_GetRadioStateDetail - */ -RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle); - -/** - * Get the detailed current radio state. - * - * @param[in] railHandle A RAIL instance handle. - * @return An enumeration for the current detailed radio state. - * - * Returns the state of the radio as a bitmask. The three core radio states - * IDLE, RX, and TX are represented by mutually exclusive bits \ref - * RAIL_RF_STATE_DETAIL_IDLE_STATE, \ref RAIL_RF_STATE_DETAIL_RX_STATE, and - * \ref RAIL_RF_STATE_DETAIL_TX_STATE respectively. If the radio is - * transitioning between these three states, the returned bitmask will have - * \ref RAIL_RF_STATE_DETAIL_TRANSITION set along with a bit corresponding to - * the destination core radio state. If, while in the receive state, the radio - * is actively receiving a packet, \ref RAIL_RF_STATE_DETAIL_ACTIVE will be set; - * otherwise, this bit will be clear. If frame detection is disabled, \ref - * RAIL_RF_STATE_DETAIL_NO_FRAMES in the returned state bitmask will be set; - * otherwise, this bit will be clear. If the radio is performing an LBT/CSMA - * operation (e.g., a backoff period) \ref RAIL_RF_STATE_DETAIL_LBT in the - * returned state bitmask will be set; otherwise, this bit will be clear. - * - * For the most part, the more detailed radio states returned by this API - * correspond to radio states returned by \ref RAIL_GetRadioState as follows: - * - * \ref RAIL_RadioStateDetail_t \ref RAIL_RadioState_t - * RAIL_RF_STATE_DETAIL_INACTIVE RAIL_RF_STATE_INACTIVE - * RAIL_RF_STATE_DETAIL_IDLE_STATE - * | RAIL_STATE_DETAIL_TRANSITION If RX overflow or leaving RX unforced: - * RAIL_RF_STATE_RX - * Else if leaving TX unforced: - * RAIL_RF_STATE_TX - * Else: - * RAIL_RF_STATE_IDLE - * RAIL_RF_STATE_DETAIL_IDLE_STATE RAIL_RF_STATE_IDLE - * RAIL_RF_STATE_DETAIL_IDLE_STATE - * | RAIL_STATE_DETAIL_LBT RAIL_RF_STATE_TX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_STATE_DETAIL_TRANSITION If leaving TX: - * RAIL_RF_STATE_TX - * Else: - * RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_RF_STATE_DETAIL_TRANSITION - * | RAIL_RF_STATE_DETAIL_NO_FRAMES If leaving TX: - * RAIL_RF_STATE_TX - * Else: - * RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_RF_STATE_DETAIL_NO_FRAMES RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_RF_STATE_DETAIL_LBT RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_RF_STATE_DETAIL_NO_FRAMES - * | RAIL_RF_STATE_DETAIL_LBT RAIL_RF_STATE_RX - * RAIL_RF_STATE_DETAIL_RX_STATE - * | RAIL_RF_STATE_DETAIL_ACTIVE RAIL_RF_STATE_RX_ACTIVE - * RAIL_RF_STATE_DETAIL_TX_STATE - * | RAIL_RF_STATE_TRANSITION If leaving RX: - * RAIL_RF_STATE_RX - * Else: - * RAIL_RF_STATE_TX - * RAIL_RF_STATE_DETAIL_TX_STATE - * | RAIL_RF_STATE_ACTIVE RAIL_RF_STATE_TX_ACTIVE - */ -RAIL_RadioStateDetail_t RAIL_GetRadioStateDetail(RAIL_Handle_t railHandle); - -/** - * Enable/disable caching of synth calibration value. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable A booloean to enable or disable caching of synth calibration. - * @return Status code indicating success of the function call. - * - * Once enabled, the sequencer will start caching synth calibration values for - * channels and apply them instead of performing calibration on every state - * transition and channel change. - * This will increase the transition time for the first time calibration is - * performed. Subsequent state transitions will be faster. The cache size is 2. - * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING internally uses this feature - * and there is no need to enable/disable it. This function returns - * \ref RAIL_STATUS_INVALID_STATE if we try to disable it while - * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is enabled. - * - * @note This function will improve the minimum timings that can be achieved in - * \ref RAIL_StateTiming_t::idleToRx, \ref RAIL_StateTiming_t::idleToTx, - * \ref RAIL_StateTiming_t::rxToTx, \ref RAIL_StateTiming_t::txToRx and - * \ref RAIL_StateTiming_t::txToTx. A call to \ref RAIL_SetStateTiming() - * is needed to achieve lower transition times. - * - * @note On a protocol switch the cache is cleared, so it is not suitable for - * applications where a protocol switch happens frequently, like with - * Dynamic Multiprotocol. - */ -RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); - -/** @} */ // end of group State_Transitions - -/****************************************************************************** - * Transmit - *****************************************************************************/ -/** - * @addtogroup Transmit - * @brief APIs related to transmitting data packets - * @{ - */ - -/// @addtogroup PA Power Amplifier (PA) -/// @brief APIs for interacting with one of the on chip PAs. -/// -/// These APIs let you configure the on-chip PA to get the appropriate output -/// power. -/// -/// These are the function types: -/// 1) Configuration functions: These functions set and get configuration -/// for the PA. In this case, "configuration" refers to a) indicating -/// which PA to use, b) the voltage supplied by your board to the PA, -/// and c) the ramp time over which to ramp the PA up to its full -/// power. -/// 2) Power-setting functions: These functions consume the actual -/// values written to the PA registers and write them appropriately. -/// These values are referred to as "(raw) power levels". The range of -/// acceptable values for these functions depends on which PA is -/// currently active. The higher the power level set, the higher -/// the dBm power output by the chip. However, the mapping -/// between dBm and these power levels can vary greatly between -/// modules/boards. -/// 3) Conversion functions: These functions convert -/// between the "power levels" discussed previously and the -/// dBm values output by the chip. Continue reading for more information -/// about unit conversion. -/// -/// The accuracy of the chip output power is application-specific. -/// For some protocols or channels, the protocol itself or -/// legal limitations require applications to know exactly what power -/// they're transmitting at, in dBm. Other applications do not have -/// these restrictions, and users determine power level(s) -/// that fit their criteria for the trade-off between radio range and -/// power savings, regardless of what dBm power that maps to. -/// -/// \ref RAIL_ConvertRawToDbm and \ref RAIL_ConvertDbmToRaw, -/// which convert between the dBm power and the raw power levels, -/// provide a solution that fits all these applications. -/// The levels of customization are outlined below: -/// 1) No customization needed: for a given dBm value, the result -/// of RAIL_ConvertDbmToRaw provides an appropriate -/// raw power level that, when written to the registers via -/// RAIL_SetPowerLevel, causes the chip to output at that -/// dBm power. In this case, no action is needed by the user, -/// the WEAK versions of the conversion functions can be used -/// and the default include paths in pa_conversions_efr32.h can -/// be used. -/// 2) The mapping of power level to dBm is not ideal, but the -/// level of precision is sufficient: In pa_conversions_efr32.c, -/// the WEAK versions of the conversion functions work by using -/// 8-segment piecewise linear curves to convert between dBm -/// and power levels for PA's with hundreds of power levels -/// and simple mapping tables for use with PA's with only a few -/// levels. If this method is sufficiently precise, but the mapping -/// between power levels and dBm is incorrect, -/// copy pa_curves_efr32.h into a new file, updating the segments -/// to form a better fit (_DCDC_CURVES or _VBAT_CURVES defines) and -/// then add the RAIL_PA_CURVES define to your build with the path -/// to the new file. -/// 3) A different level of precision is needed and the fit is bad: -/// If the piecewise-linear line segment fit is not appropriate for -/// your solution, the functions in pa_conversions_efr32.c can be -/// totally rewritten, as long as RAIL_ConvertDbmToRaw and -/// RAIL_ConvertRawToDbm have the same signatures. It is completely -/// acceptable to re-write these in a way that makes the -/// pa_curves_efr32.h and pa_curve_types_efr32.h files referenced in -/// pa_conversions_efr32.h unnecessary. Those files are needed solely -/// for the provided conversion methods. -/// 4) dBm values are not necessary: If the application does not require -/// dBm values at all, overwrite -/// RAIL_ConvertDbmToRaw and RAIL_ConvertRawToDbm with smaller functions -/// (i.e., return 0 or whatever was input). These functions are called -/// from within the RAIL library, so they can never be deadstripped, -/// but making them as small as possible is the best way to reduce code -/// size. From there, call RAIL_SetTxPower, without -/// converting from a dBm value. To stop the library from coercing the -/// power based on channels, overwrite RAIL_ConvertRawToDbm -/// to always return 0 and overwrite RAIL_ConvertDbmToRaw to -/// always return 255. -/// -/// The following is example code that shows how to initialize your PA -/// @code{.c} -/// -/// #include "pa_conversions_efr32.h" -/// -/// // A helper macro to declare all the curve structures used by the provided -/// // conversion functions. -/// RAIL_DECLARE_TX_POWER_VBAT_CURVES(piecewiseSegments, curvesSg, curves24Hp, curves24Lp); -/// -/// // Puts the variables declared above into the appropriate structure. -/// RAIL_TxPowerCurvesConfig_t txPowerCurvesConfig = { curves24Hp, curvesSg, curves24Lp, piecewiseSegments }; -/// -/// // Saves those curves -/// // to be referenced when the conversion functions are called. -/// RAIL_InitTxPowerCurves(&txPowerCurvesConfig); -/// -/// // Declares the structure used to configure the PA. -/// RAIL_TxPowerConfig_t txPowerConfig = { RAIL_TX_POWER_MODE_2P4_HP, 3300, 10 }; -/// -/// // Initializes the PA. Here, it is assumed that 'railHandle' is a valid RAIL_Handle_t -/// // that has already been initialized. -/// RAIL_ConfigTxPower(railHandle, &txPowerConfig); -/// -/// // Picks a dBm power to use: 100 deci-dBm = 10 dBm. See docs on RAIL_TxPower_t. -/// RAIL_TxPower_t power = 100; -/// -/// // Gets the config written by RAIL_ConfigTxPower to confirm what was actually set. -/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); -/// -/// // RAIL_ConvertDbmToRaw is the default weak version, -/// // or the customer version, if overwritten. -/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, -/// txPowerConfig.mode, -/// power); -/// -/// // Writes the result of the conversion to the PA power registers in terms -/// // of raw power levels. -/// RAIL_SetTxPower(railHandle, powerLevel); -/// @endcode -/// -/// @note All lines following "RAIL_TxPower_t power = 100;" can be -/// replaced with the provided utility function, \ref RAIL_SetTxPowerDbm. -/// However, the full example here was provided for clarity. See the -/// documentation on \ref RAIL_SetTxPowerDbm for more details. -/// -/// @{ - -/** - * Initialize TX power settings. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config An instance which contains desired initial settings - * for the TX amplifier. - * @return RAIL_Status_t indicating success or an error. - * - * These settings include the selection between the multiple TX amplifiers, - * voltage supplied to the TX power amplifier, and ramp times. This must - * be called before any transmit occurs or \ref RAIL_SetTxPower is called. - * While this function should always be called during initialization, - * it can also be called any time if these settings need to change to adapt - * to a different application/protocol. This API also resets TX power to - * \ref RAIL_TX_POWER_LEVEL_INVALID, so \ref RAIL_SetTxPower must be called - * afterwards. - * - * At times, certain combinations of configurations cannot be achieved. - * This API attempts to get as close as possible to the requested settings. The - * following "RAIL_Get..." API can be used to determine what values were set. A - * change in \ref RAIL_TxPowerConfig_t::rampTime may affect the minimum timings - * that can be achieved in \ref RAIL_StateTiming_t::idleToTx and - * \ref RAIL_StateTiming_t::rxToTx. Call \ref RAIL_SetStateTiming() again to - * check whether these times have changed. - */ -RAIL_Status_t RAIL_ConfigTxPower(RAIL_Handle_t railHandle, - const RAIL_TxPowerConfig_t *config); - -/** - * Get the TX power settings currently used in the amplifier. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] config A pointer to memory allocated to hold the current TxPower - * configuration structure. A NULL configuration will produce undefined - * behavior. - * @return RAIL status variable indicating whether or not the get was - * successful. - * - * Note that this API does not return the current TX power, which is separately - * managed by the \ref RAIL_GetTxPower / \ref RAIL_SetTxPower APIs. Use this API - * to determine which values were set as a result of - * \ref RAIL_ConfigTxPower. - */ -RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle, - RAIL_TxPowerConfig_t *config); - -/** - * Set the TX power in units of raw units (see \ref rail_chip_specific.h for - * value ranges). - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] powerLevel Power in chip-specific \ref RAIL_TxPowerLevel_t units. - * @return RAIL_Status_t indicating success or an error. - * - * To convert between decibels and the integer values that the - * registers take, call \ref RAIL_ConvertDbmToRaw. - * A weak version of this function, which works well with our boards is provided. However, - * customers using a custom board need to characterize - * chip operation on that board and override the function to convert - * appropriately from the desired dB values to raw integer values. - * - * Depending on the configuration used in \ref RAIL_ConfigTxPower, not all - * power levels are achievable. This API will get as close as possible to - * the desired power without exceeding it, and calling \ref RAIL_GetTxPower is - * the only way to know the exact value written. - * - * Calling this function before configuring the PA (i.e., before a successful - * call to \ref RAIL_ConfigTxPower) will return an error. - */ -RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle, - RAIL_TxPowerLevel_t powerLevel); - -/** - * Return the current power setting of the PA. - * - * @param[in] railHandle A RAIL instance handle. - * @return The chip-specific \ref RAIL_TxPowerLevel_t value of the current - * transmit power. - * - * This API returns the raw value that was set by \ref RAIL_SetTxPower. - * A weak version of \ref RAIL_ConvertRawToDbm that works - * with our boards to convert the raw values into actual output dBm values is provided. - * However, customers using a custom board need to - * re-characterize the relationship between raw and decibel values and rewrite - * the provided function. - * - * Calling this function before configuring the PA (i.e., before a successful - * call to \ref RAIL_ConfigTxPower) will return an error - * (RAIL_TX_POWER_LEVEL_INVALID). - */ -RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); - -/** - * Convert raw values written to registers to decibel value (in units of - * deci-dBm). - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode PA mode for which to convert. - * @param[in] powerLevel A raw amplifier register value to be converted to - * deci-dBm. - * @return raw amplifier values converted to units of deci-dBm. - * - * A weak version of this function is provided that is tuned - * to provide accurate values for our boards. For a - * custom board, the relationship between what is written to the TX amplifier - * and the actual output power should be re-characterized and implemented in an - * overriding version of \ref RAIL_ConvertRawToDbm. For minimum code size and - * best speed, use only raw values with the TxPower API and override this - * function with a smaller function. In the weak version provided with the RAIL - * library, railHandle is only used to indicate to the user from where the - * function was called, so it is OK to use either a real protocol handle, or one - * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. - * - * Although the definitions of this function may change, the signature - * must be as declared here. - */ -RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPowerLevel_t powerLevel); - -/** - * Convert the desired decibel value (in units of deci-dBm) - * to raw integer values used by the TX amplifier registers. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode PA mode for which to do the conversion. - * @param[in] power Desired dBm values in units of deci-dBm. - * @return deci-dBm value converted to a raw - * integer value that can be used directly with \ref RAIL_SetTxPower. - * - * A weak version of this function is provided that is tuned - * to provide accurate values for our boards. For a - * custom board, the relationship between what is written to the TX amplifier - * and the actual output power should be characterized and implemented in an - * overriding version of \ref RAIL_ConvertDbmToRaw. For minimum code size and - * best speed use only raw values with the TxPower API and override this - * function with a smaller function. In the weak version provided with the RAIL - * library, railHandle is only used to indicate to the user from where the - * function was called, so it is OK to use either a real protocol handle, or one - * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. - * - * Although the definitions of this function may change, the signature - * must be as declared here. - * - * @note This function is called from within the RAIL library for - * comparison between channel limitations and current power. It will - * throw an assert if you haven't called RAIL_InitTxPowerCurves - * which initializes the mappings between raw power levels and - * actual dBm powers. To avoid the assert, ensure that the - * maxPower of all channel configuration entries is \ref RAIL_TX_POWER_MAX - * or above, or override this function to always return 255. - */ -RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPower_t power); - -struct RAIL_TxPowerCurvesConfigAlt; -/// Verify the TX Power Curves on modules. -/// -/// @param[in] config TX Power Curves to use on this module. -/// -/// This function only needs to be called when using a module and has no -/// effect otherwise. Transmit will not work before this function is called. -void RAIL_VerifyTxPowerCurves(const struct RAIL_TxPowerCurvesConfigAlt *config); - -/// Set the TX power in terms of deci-dBm instead of raw power level. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @param[in] power A desired deci-dBm power to be set. -/// @return RAIL Status variable indicate whether setting the -/// power was successful. -/// -/// This is a utility function for user convenience. Normally, to set TX -/// power in dBm, do the following: -/// -/// @code{.c} -/// RAIL_TxPower_t power = 100; // 100 deci-dBm, 10 dBm -/// RAIL_TxPowerConfig_t txPowerConfig; -/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); -/// // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs -/// // by default, or the customer version, if overwritten. -/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, -/// txPowerConfig.mode, -/// power); -/// RAIL_SetTxPower(railHandle, powerLevel); -/// @endcode -/// -/// This function wraps all those calls in a single function with power passed in -/// as a parameter. -/// -RAIL_Status_t RAIL_SetTxPowerDbm(RAIL_Handle_t railHandle, - RAIL_TxPower_t power); - -/// Get the TX power in terms of deci-dBm instead of raw power level. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @return The current output power in deci-dBm. -/// -/// This is a utility function for user convenience. Normally, to get TX -/// power in dBm, do the following: -/// -/// @code{.c} -/// RAIL_TxPowerLevel_t powerLevel = RAIL_GetTxPower(railHandle); -/// RAIL_TxPowerConfig_t txPowerConfig; -/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); -/// // RAIL_ConvertRawToDbm will be the weak version provided by Silicon Labs -/// // by default, or the customer version, if overwritten. -/// RAIL_TxPower_t power = RAIL_ConvertRawToDbm(railHandle, -/// txPowerConfig.mode, -/// powerLevel); -/// return power; -/// @endcode -/// -/// This function wraps all those calls in a single function with power returned -/// as the result. -/// -RAIL_TxPower_t RAIL_GetTxPowerDbm(RAIL_Handle_t railHandle); - -/** - * Get the TX PA power setting table and related values. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode PA mode for which to get the powersetting table - * @param[out] minPower A pointer to a \ref RAIL_TxPower_t - * @param[out] maxPower A pointer to a \ref RAIL_TxPower_t - * @param[out] step In deci-dBm increments. A pointer to a \ref RAIL_TxPowerLevel_t - * @return Power setting table start address. When NULL is returned all out params - * above won't be set. - * - * The number of entries in the table can be calculated based on the minPower, maxPower, - * and step parameters. For example, for minPower = 115 (11.5 dBm), maxPower = 300 (30 dBm), - * and step = 1, the number of entries in table would be 186 - */ -const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, - RAIL_TxPower_t *minPower, RAIL_TxPower_t *maxPower, - RAIL_TxPowerLevel_t *step); - -/** - * Set the TX PA power setting used to configure the PA hardware for the PA output - * power determined by \ref RAIL_SetTxPowerDbm(). - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] paPowerSetting The desired PA power setting. - * @param[in] minPowerDbm The minimum power in dBm that the PA can output. - * @param[in] maxPowerDbm The maximum power in dBm that the PA can output. - * @param[in] currentPowerDbm The corresponding output power in dBm for this power setting. - * @return RAIL Status variable indicate whether setting the - * PA power setting was successful. - */ -RAIL_Status_t RAIL_SetPaPowerSetting(RAIL_Handle_t railHandle, - RAIL_PaPowerSetting_t paPowerSetting, - RAIL_TxPower_t minPowerDbm, - RAIL_TxPower_t maxPowerDbm, - RAIL_TxPower_t currentPowerDbm); - -/** - * Get the TX PA power setting, which is used to configure power configurations - * when the dBm to paPowerSetting mapping table mode is used. - * - * @param[in] railHandle A RAIL instance handle. - * @return The current PA power setting. - */ -RAIL_PaPowerSetting_t RAIL_GetPaPowerSetting(RAIL_Handle_t railHandle); - -/** - * Enable automatic switching between PAs internally to the RAIL library. - * While PA Automode is enabled, the PA will be chosen and set automatically whenever - * \ref RAIL_SetTxPowerDbm is called or whenever powers are coerced automatically, - * internally to the RAIL library during a channel change. While PA Auto Mode - * is enabled, users cannot call \ref RAIL_ConfigTxPower or - * \ref RAIL_SetTxPower. When entering auto mode, \ref RAIL_SetTxPowerDbm must - * be called to specify the desired power. When leaving auto mode, - * \ref RAIL_ConfigTxPower as well as one of \ref RAIL_SetTxPower or - * \ref RAIL_SetTxPowerDbm must be called to re-specify the desired PA and power - * level combination. - * - * @note: Power conversion curves must be initialized before calling this function. - * That is, \ref RAIL_ConvertDbmToRaw and \ref RAIL_ConvertRawToDbm most both be - * able to operate properly to ensure that PA Auto Mode functions correctly. - * See the PA Conversions plugin or AN1127 for more details. - * - * @param[in] railHandle A real (not generic) RAIL instance handle. - * @param[in] enable Enable or disable PA Auto Mode. - * @return Status parameter indicating success of function call. - */ -RAIL_Status_t RAIL_EnablePaAutoMode(RAIL_Handle_t railHandle, bool enable); - -/** - * Query status of PA Auto Mode. - * - * @param[in] railHandle A real (not generic) RAIL instance handle on which to - * query PA Auto Mode status. - * @return Indicator of whether Auto Mode is enabled (true) or not (false). - */ -bool RAIL_IsPaAutoModeEnabled(RAIL_Handle_t railHandle); - -/** - * Callback that decides which PA and power level should be - * used while in PA auto mode. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] power Pointer to the dBm output power (in deci-dBm, 10*dBm) - * being requested. The value this points to when the function returns - * will be applied to the radio. - * @param[out] mode Pointer to the \ref RAIL_TxPowerMode_t to be used to - * achieve the requested power. The value this points to when the function - * returns will be applied to the radio. - * @param[in] chCfgEntry Pointer to a \ref RAIL_ChannelConfigEntry_t. - * While switching channels, it will be the entry RAIL is switch *to*, - * during a call to \ref RAIL_SetTxPowerDbm, it will be the entry - * RAIL is *already on*. Can be NULL if a channel configuration - * was not set or no valid channels are present. - * @return Return status indicating result of function call. If this - * is anything except \ref RAIL_STATUS_NO_ERROR, neither PA's nor their - * powers will be configured automatically. - * - * Whatever values mode and powerLevel point to when this function return - * will be applied to the PA hardware and used for transmits. - * @note The mode and power level provided by this function depends on the - * RAIL_PaAutoModeConfig provided for the chip. The RAIL_PaAutoModeConfig - * definition for a chip should tend to all the bands supported by the chip and - * cover the full range of power to find a valid entry for requested power - * for a specific band. - */ -RAIL_Status_t RAILCb_PaAutoModeDecision(RAIL_Handle_t railHandle, - RAIL_TxPower_t *power, - RAIL_TxPowerMode_t *mode, - const RAIL_ChannelConfigEntry_t *chCfgEntry); - -/** @} */ // end of group PA - -/// @addtogroup Packet_TX Packet Transmit -/// @brief APIs which initiate a packet transmission in RAIL -/// -/// When using any of these functions, the data to be transmitted must have been -/// previously written to the Transmit FIFO via \ref RAIL_SetTxFifo() and/or -/// \ref RAIL_WriteTxFifo(). -/// -/// @{ - -/** - * Start a transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * The transmit process will begin immediately or as soon as a packet being - * received has finished. The data to be transmitted must have been previously - * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, any ongoing packet reception is aborted. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Schedule sending a packet. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] config A pointer to the \ref RAIL_ScheduleTxConfig_t - * structure containing when the transmit should occur. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, a transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * The transmit process will begin at the scheduled time. The data to be - * transmitted must have been previously established via \ref RAIL_SetTxFifo() - * and/or \ref RAIL_WriteTxFifo(). - * The time (in microseconds) and whether that time is absolute or - * relative is specified using the \ref RAIL_ScheduleTxConfig_t structure. - * What to do if a scheduled transmit fires in - * the middle of receiving a packet is also specified in this structure. - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, the channel is changed immediately and - * will abort any ongoing packet reception. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartScheduledTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_ScheduleTxConfig_t *config, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Start a transmit using CSMA. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] csmaConfig A pointer to the RAIL_CsmaConfig_t structure - * describing the CSMA parameters to use for this transmit. - * \n In multiprotocol this must point to global or heap storage that remains - * valid after the API returns until the transmit is actually started. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, a transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * Perform the Carrier Sense Multiple Access (CSMA) algorithm, and if - * the channel is deemed clear (RSSI below the specified threshold), it will - * commence transmission. The data to be transmitted must have been previously - * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). - * Packets can be received during CSMA backoff periods if receive is active - * throughout the CSMA process. This will happen either by starting the CSMA - * process while receive is already active, or if the csmaBackoff time in - * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by - * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the - * idleToRx time, receive will only be active during CSMA's clear channel - * assessments. - * - * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback - * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents - * of the transmit FIFO remain intact. - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, the channel is changed immediately and any ongoing - * packet reception is aborted. - * - * Returns an error if a scheduled RX is still in progress. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartCcaCsmaTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_CsmaConfig_t *csmaConfig, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Start a transmit using LBT. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] lbtConfig A pointer to the RAIL_LbtConfig_t structure - * describing the LBT parameters to use for this transmit. - * \n In multiprotocol this must point to global or heap storage that remains - * valid after the API returns until the transmit is actually started. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, a transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * Performs the Listen Before Talk (LBT) algorithm, and if the channel - * is deemed clear (RSSI below the specified threshold), it will commence - * transmission. The data to be transmitted must have been previously established - * via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). - * Packets can be received during LBT backoff periods if receive is active - * throughout the LBT process. This will happen either by starting the LBT - * process while receive is already active, or if the lbtBackoff time in - * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by - * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the - * idleToRx time, receive will only be active during LBT's clear channel - * assessments. - * - * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback occurs with - * \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents - * of the transmit FIFO remain intact. - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, the channel is changed immediately and any ongoing - * packet reception is aborted. - * - * Returns an error if a scheduled RX is still in progress. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartCcaLbtTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_LbtConfig_t *lbtConfig, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Schedule a transmit using CSMA. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] scheduleTxConfig A pointer to the \ref RAIL_ScheduleTxConfig_t - * structure describing the CSMA parameters to use for this transmit. - * @param[in] csmaConfig A pointer to the \ref RAIL_CsmaConfig_t structure - * describing the CSMA parameters to use for this transmit. - * \n In multiprotocol this must point to global or heap storage that remains - * valid after the API returns until the transmit is actually started. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, a transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * Internally, the RAIL library needs a PRS channel for this feature. - * It will allocate an available PRS channel to use and hold onto that - * channel for future use. If no PRS channel is available, the function - * returns with \ref RAIL_STATUS_INVALID_CALL. - * - * Perform the Carrier Sense Multiple Access (CSMA) algorithm at the scheduled time, - * and if the channel is deemed clear (RSSI below the specified threshold), it will - * commence transmission. The data to be transmitted must have been previously - * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). - * Packets can be received during CSMA backoff periods if receive is active - * throughout the CSMA process. This will happen either by starting the CSMA - * process while receive is already active, or if the csmaBackoff time in - * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by - * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the - * idleToRx time, receive will only be active during CSMA's clear channel - * assessments. - * - * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback - * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents - * of the transmit FIFO remain intact. - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, the channel is changed immediately and any ongoing - * packet reception is aborted. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartScheduledCcaCsmaTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_ScheduleTxConfig_t *scheduleTxConfig, - const RAIL_CsmaConfig_t *csmaConfig, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Schedule a transmit using LBT. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel Define the channel to transmit on. - * @param[in] options TX options to be applied to this transmit only. - * @param[in] scheduleTxConfig A pointer to the \ref RAIL_ScheduleTxConfig_t - * structure describing the CSMA parameters to use for this transmit. - * @param[in] lbtConfig A pointer to the \ref RAIL_LbtConfig_t structure - * describing the LBT parameters to use for this transmit. - * \n In multiprotocol this must point to global or heap storage that remains - * valid after the API returns until the transmit is actually started. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this transmit appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. If successfully - * initiated, a transmit completion or failure will be reported by a later - * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. - * - * Internally, the RAIL library needs a PRS channel for this feature. - * It will allocate an available PRS channel to use and hold onto that - * channel for future use. If no PRS channel is available, the function - * returns with \ref RAIL_STATUS_INVALID_CALL. - * - * Performs the Listen Before Talk (LBT) algorithm at the scheduled time, - * and if the channel is deemed clear (RSSI below the specified threshold), it will - * commence transmission. The data to be transmitted must have been previously - * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). - * Packets can be received during LBT backoff periods if receive is active - * throughout the LBT process. This will happen either by starting the LBT - * process while receive is already active, or if the lbtBackoff time in - * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by - * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the - * idleToRx time, receive will only be active during LBT's clear channel - * assessments. - * - * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback - * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents of the transmit - * FIFO remain intact. - * - * Returns an error if a previous transmit is still in progress. - * If changing channels, the channel is changed immediately and any ongoing - * packet reception is aborted. - * - * In multiprotocol, ensure that the radio is properly yielded after this - * operation completes. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_StartScheduledCcaLbtTx(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_TxOptions_t options, - const RAIL_ScheduleTxConfig_t *scheduleTxConfig, - const RAIL_LbtConfig_t *lbtConfig, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** @} */ // end of group Packet_TX - -/** - * Stop an active or pending transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode Configure the types of transmits to stop. - * @return \ref RAIL_STATUS_NO_ERROR if the transmit was successfully - * stopped or \ref RAIL_STATUS_INVALID_STATE if there is no transmit - * operation to stop. - * - * @note When mode includes \ref RAIL_STOP_MODE_ACTIVE, this can also stop - * an active auto-ACK transmit. When an active transmit is stopped, \ref - * RAIL_EVENT_TX_ABORTED or \ref RAIL_EVENT_TXACK_ABORTED should occur. - * When mode includes \ref RAIL_STOP_MODE_PENDING this can also stop - * a \ref RAIL_TX_OPTION_CCA_ONLY transmit operation. When a pending - * transmit is stopped, \ref RAIL_EVENT_TX_BLOCKED should occur. - */ -RAIL_Status_t RAIL_StopTx(RAIL_Handle_t railHandle, RAIL_StopMode_t mode); - -/** - * Set the CCA threshold in dBm. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] ccaThresholdDbm The CCA threshold in dBm. - * @return Status code indicating success of the function call. - * - * Unlike RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(), which can cause a - * transmit, this function only modifies the CCA threshold. A possible - * use case for this function involves setting the CCA threshold to invalid RSSI - * of -128 which blocks transmission by preventing clear channel assessments - * from succeeding. - */ -RAIL_Status_t RAIL_SetCcaThreshold(RAIL_Handle_t railHandle, - int8_t ccaThresholdDbm); - -/** - * Get detailed information about the last packet transmitted. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] pPacketDetails An application-provided pointer to store - * RAIL_TxPacketDetails_t corresponding to the transmit event. - * The isAck and timeSent fields totalPacketBytes and timePosition - * must be initialized prior to each call: - * - isAck true to obtain details about the most recent ACK transmit, - * false to obtain details about the most recent app-initiated transmit. - * - totalPacketBytes with the total number of bytes of the transmitted - * packet for RAIL to use when calculating the specified timestamp. - * This should account for all bytes sent over the air after the - * Preamble and Sync word(s), including CRC bytes. - * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying - * the packet position to put in the timeSent field on return. - * This field will also be updated with the actual position corresponding - * to the timeSent value filled in. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, - * or an appropriate error code otherwise. - * - * @note Consider using \ref RAIL_GetTxPacketDetailsAlt2 for smaller code size. - * - * This function can only be called from callback context for either - * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT - * events. - */ -RAIL_Status_t RAIL_GetTxPacketDetails(RAIL_Handle_t railHandle, - RAIL_TxPacketDetails_t *pPacketDetails); - -/** - * Get detailed information about the last packet transmitted. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] isAck True to obtain details about the most recent ACK transmit. - * False to obtain details about the most recent app-initiated transmit. - * @param[out] pPacketTime An application-provided non-NULL pointer to store a - * RAIL_Time_t corresponding to the transmit event. This will be populated - * with a timestamp corresponding to an arbitrary location in the packet. Call - * \ref RAIL_GetTxTimePreambleStart, \ref RAIL_GetTxTimeSyncWordEnd, or - * \ref RAIL_GetTxTimeFrameEnd to adjust the timestamp for different locations - * in the packet. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was filled in, - * or an appropriate error code otherwise. - * - * @note Consider using \ref RAIL_GetTxPacketDetailsAlt2 to pass in - * a \ref RAIL_PacketTimeStamp_t structure instead of a \ref RAIL_Time_t - * structure, particularly when \ref RAIL_PacketTimePosition_t information - * is needed or useful. - * - * This function can only be called from callback context for either - * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT - * events. - */ -RAIL_Status_t RAIL_GetTxPacketDetailsAlt(RAIL_Handle_t railHandle, - bool isAck, - RAIL_Time_t *pPacketTime); - -/** - * Get detailed information about the last packet transmitted. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails An application-provided pointer to store - * RAIL_TxPacketDetails_t corresponding to the transmit event. - * The isAck must be initialized prior to each call: - * - isAck true to obtain details about the most recent ACK transmit, - * false to obtain details about the most recent app-initiated transmit. - * The timeSent field packetTime will be populated with a timestamp corresponding - * to a default location in the packet. The timeSent field timePosition will - * be populated with a \ref RAIL_PacketTimePosition_t value specifying that - * default packet location. Call \ref RAIL_GetTxTimePreambleStartAlt, - * \ref RAIL_GetTxTimeSyncWordEndAlt, or \ref RAIL_GetTxTimeFrameEndAlt to - * adjust the timestamp for different locations in the packet. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, - * or an appropriate error code otherwise. - * - * This function can only be called from callback context for either - * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT - * events. - */ -RAIL_Status_t RAIL_GetTxPacketDetailsAlt2(RAIL_Handle_t railHandle, - RAIL_TxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL TX completion timestamp to refer to the start of the - * preamble. Also used to retrieve the \ref RAIL_EVENT_TX_STARTED - * timestamp. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the transmitted - * packet for RAIL to use when adjusting the provided timestamp. This - * should account for all bytes transmitted over the air after the Preamble - * and Sync word(s), including CRC bytes. Pass \ref RAIL_TX_STARTED_BYTES - * to retrieve the start-of-normal-TX timestamp (see below). - * @param[in, out] pPacketTime This points to the \ref RAIL_Time_t returned - * from a previous call to \ref RAIL_GetTxPacketDetailsAlt for this same - * packet. That time will be updated with the time that the preamble for - * this packet started on air. - * Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully - * determined or an appropriate error code otherwise. - * - * When used for timestamp adjustment, call this function in the - * same transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt() is called. - * - * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED - * event to retrieve that event's start-of-normal-TX timestamp. (ACK - * transmits currently have no equivalent event or associated timestamp.) - * In this case, totalPacketBytes must be \ref RAIL_TX_STARTED_BYTES, and - * pPacketTime is an output-only parameter filled in with that time (so no - * need to initialize it beforehand by calling \ref - * RAIL_GetTxPacketDetailsAlt()). - * - */ -RAIL_Status_t RAIL_GetTxTimePreambleStart(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL TX completion timestamp to refer to the start of the - * preamble. Also used to retrieve the \ref RAIL_EVENT_TX_STARTED - * timestamp. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. - * The application must update the timeSent field totalPacketBytes to be - * the total number of bytes of the sent packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * transmitted over the air after the Preamble and Sync word(s), including CRC - * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX - * timestamp (see below). After this function, the timeSent field packetTime - * will be updated with the time that the preamble for this packet started on air. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * When used for timestamp adjustment, call this function in the - * same transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt2() is called. - * - * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED - * event to retrieve that event's start-of-normal-TX timestamp. (ACK - * transmits currently have no equivalent event or associated timestamp.) - * In this case, the timeSent field totalPacketBytes must be - * \ref RAIL_TX_STARTED_BYTES, and the timeSent field packetTime is an - * output-only parameter filled in with that time (so no need to initialize - * it beforehand by calling \ref RAIL_GetTxPacketDetailsAlt2()). - * - */ -RAIL_Status_t RAIL_GetTxTimePreambleStartAlt(RAIL_Handle_t railHandle, - RAIL_TxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL TX timestamp to refer to the end of the sync word. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the transmitted - * packet for RAIL to use when calculating the specified timestamp. This - * should account for all bytes transmitted over the air after the Preamble - * and Sync word(s), including CRC bytes. - * @param[in, out] pPacketTime The time that was returned in a - * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt - * for this same packet. After this function, the time at that location will - * be updated with the time that the sync word for this packet finished on - * air. Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, - * or an appropriate error code otherwise. - * - * Call the timestamp adjustment function in the same - * transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt() is called. - */ -RAIL_Status_t RAIL_GetTxTimeSyncWordEnd(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL TX timestamp to refer to the end of the sync word. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. - * The application must update the timeSent field totalPacketBytes to be - * the total number of bytes of the sent packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * transmitted over the air after the Preamble and Sync word(s), including CRC - * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX - * timestamp (see below). After this function, the timeSent field packetTime - * will be updated with the time that the sync word for this packet finished on - * air. Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * Call the timestamp adjustment function in the same - * transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt2() is called. - */ -RAIL_Status_t RAIL_GetTxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, - RAIL_TxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL TX timestamp to refer to the end of frame. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the transmitted - * packet for RAIL to use when calculating the specified timestamp. This - * should account for all bytes transmitted over the air after the Preamble - * and Sync word(s), including CRC bytes. - * @param[in, out] pPacketTime The time that was returned in a - * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt - * for this same packet. After this function, the time at that location will - * be updated with the time that this packet finished on air. Must be - * non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, - * or an appropriate error code otherwise. - * - * Call the timestamp adjustment function in the same - * transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt() is called. - */ -RAIL_Status_t RAIL_GetTxTimeFrameEnd(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL TX timestamp to refer to the end of frame. - * - * @param[in] railHandle A RAIL instance handle. - - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. - * The application must update the timeSent field totalPacketBytes to be - * the total number of bytes of the sent packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * transmitted over the air after the Preamble and Sync word(s), including CRC - * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX - * timestamp (see below). After this function, the timeSent field packetTime - * will be updated with the time that this packet finished on air. Must be - * non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * Call the timestamp adjustment function in the same - * transmit-complete event-handling context as - * \ref RAIL_GetTxPacketDetailsAlt2() is called. - */ -RAIL_Status_t RAIL_GetTxTimeFrameEndAlt(RAIL_Handle_t railHandle, - RAIL_TxPacketDetails_t *pPacketDetails); - -/** - * Prevent the radio from starting a transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Enable/Disable TX hold off. - * - * Enable TX hold off to prevent the radio from starting any transmits. - * Disable TX hold off to allow the radio to transmit again. - * Attempting to transmit with the TX hold off enabled will result in - * \ref RAIL_EVENT_TX_BLOCKED and/or \ref RAIL_EVENT_TXACK_BLOCKED - * events. - * - * @note This function does not affect a transmit that has already started. - * To stop an already-started transmission, use RAIL_Idle() with - * \ref RAIL_IDLE_ABORT. - */ -void RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable); - -/** - * Check whether or not TX hold off is enabled. - * - * @param[in] railHandle A RAIL instance handle. - * @return Returns true if TX hold off is enabled, false otherwise. - * - * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff. - * Attempting to transmit with the TX hold off enabled will block the - * transmission and result in \ref RAIL_EVENT_TX_BLOCKED - * and/or \ref RAIL_EVENT_TXACK_BLOCKED events. - */ -bool RAIL_IsTxHoldOffEnabled(RAIL_Handle_t railHandle); - -/** - * Set an alternate transmitter preamble length. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] length The desired preamble length, in bits. - * @return Status code indicating success of the function call. - * - * To cause a transmission to use this alternate preamble length, - * specify \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN in the txOptions - * parameter passed to the respective RAIL transmit API. - * - * @note Attempting to set a preamble length of 0xFFFF bits will result in - * \ref RAIL_STATUS_INVALID_PARAMETER. - **/ -RAIL_Status_t RAIL_SetTxAltPreambleLength(RAIL_Handle_t railHandle, uint16_t length); - -/** @} */ // end of group Transmit - -/****************************************************************************** - * Receive - *****************************************************************************/ -/** - * @addtogroup Receive - * @brief APIs related to packet receive - * @{ - */ - -/** - * Configure receive options. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mask A bitmask containing which options should be modified. - * @param[in] options A bitmask containing desired configuration settings. - * Bit positions for each option are found in the \ref RAIL_RxOptions_t. - * @return Status code indicating success of the function call. - * - * Configure the radio receive flow based on the list of available options. - * Only the options indicated by the mask parameter will be affected. Pass - * \ref RAIL_RX_OPTIONS_ALL to set all parameters. - * The previous settings may affect the current frame if a packet is - * received during this configuration. - * - * @note: On chips where \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING - * is true, enabling \ref RAIL_RX_OPTION_CHANNEL_SWITCHING without configuring - * RX channel switching, via \ref RAIL_IEEE802154_ConfigRxChannelSwitching, - * will return \ref RAIL_STATUS_INVALID_PARAMETER for only this option. - * Any other RX options (except antenna selection) would still take effect. - */ -RAIL_Status_t RAIL_ConfigRxOptions(RAIL_Handle_t railHandle, - RAIL_RxOptions_t mask, - RAIL_RxOptions_t options); - -/** - * Include the code necessary for frame type based length decoding. - * - * @param[in] railHandle A RAIL instance handle. - * - * This function must be called before \ref RAIL_ConfigChannels to allow configurations - * using a frame type based length setup. In RAIL 2.x, it is called by default - * in the \ref RAILCb_ConfigFrameTypeLength API which can be overridden to save - * code space. In future versions, the user may be required to call this API - * explicitly. - */ -void RAIL_IncludeFrameTypeLength(RAIL_Handle_t railHandle); - -/** - * Handle frame type length. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] frameType A frame type configuration structure. - * - * This function is implemented in the radio configuration. - * Currently, the frame type passed in only handles packet length decoding. If - * NULL is passed into this function, it clears any currently configured - * frame type settings. This will either be implemented as an empty function in - * the radio configuration if it is not needed, to assist in dead code - * elimination. - */ -void RAILCb_ConfigFrameTypeLength(RAIL_Handle_t railHandle, - const RAIL_FrameType_t *frameType); - -/** - * Start the receiver on a specific channel. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel The channel to listen on. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this receive appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. - * - * This is a non-blocking function. Whenever a packet is received, \ref RAIL_Config_t::eventsCallback - * will fire with \ref RAIL_EVENT_RX_PACKET_RECEIVED set. If you call - * this while not idle but with a different channel, any ongoing - * receive or transmit operation will be aborted. - */ -RAIL_Status_t RAIL_StartRx(RAIL_Handle_t railHandle, - uint16_t channel, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Schedule a receive window for some future time. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel A channel to listen on. - * @param[in] cfg The configuration structure to define the receive window. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this receive appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. - * - * This API immediately changes the channel and schedules receive to start - * at the specified time and end at the given end time. If you do not specify - * an end time, you may call this API later with an end time as long as you set - * the start time to disabled. You can also terminate the receive - * operation immediately using the RAIL_Idle() function. Note that relative - * end times are always relative to the start unless no start time is - * specified. If changing channels, the channel is changed immediately and - * will abort any ongoing packet transmission or reception. - * - * Returns an error if a CSMA or LBT transmit is still in progress. - * - * In multiprotocol, ensure that you properly yield the radio after this - * call. See \ref rail_radio_scheduler_yield for more details. - */ -RAIL_Status_t RAIL_ScheduleRx(RAIL_Handle_t railHandle, - uint16_t channel, - const RAIL_ScheduleRxConfig_t *cfg, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/****************************************************************************** - * Packet Information (RX) - *****************************************************************************/ -/// @addtogroup Packet_Information Packet Information -/// @brief APIs to get information about received packets. -/// -/// After receiving a packet, RAIL will trigger a -/// \ref RAIL_EVENT_RX_PACKET_RECEIVED event. At that point, there is a variety -/// of information available to the application about the received packet. The -/// following example code assumes that the -/// \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO is not used, and the application -/// wants as much data about the packet as possible. -/// -/// @code{.c} -/// // Get all information about a received packet. -/// RAIL_Status_t status; -/// RAIL_RxPacketInfo_t rxInfo; -/// RAIL_RxPacketDetails_t rxDetails; -/// RAIL_RxPacketHandle_t rxHandle -/// = RAIL_GetRxPacketInfo(railHandle, RAIL_RX_PACKET_HANDLE_NEWEST, &rxInfo); -/// assert(rxHandle != RAIL_RX_PACKET_HANDLE_INVALID); -/// status = RAIL_GetRxPacketDetailsAlt(railHandle, rxHandle, &rxDetails); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// if (rxDetails.timeReceived.timePosition == RAIL_PACKET_TIME_INVALID) { -/// return; // No timestamp available for this packet -/// } -/// // CRC_BYTES only needs to be added when not using RAIL_RX_OPTION_STORE_CRC -/// rxDetails.timeReceived.totalPacketBytes = rxInfo.packetBytes + CRC_BYTES; -/// // Choose the function which gives the desired timestamp -/// status = RAIL_GetRxTimeFrameEndAlt(railHandle, &rxDetails); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// // Now all fields of rxInfo and rxDetails have been populated correctly -/// @endcode -/// -/// @{ - -/** - * Get basic information about a pending or received packet. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] packetHandle A packet handle for the unreleased packet as - * returned from a previous call, or sentinel values - * \ref RAIL_RX_PACKET_HANDLE_OLDEST, - * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE or - * \ref RAIL_RX_PACKET_HANDLE_NEWEST. - * @param[out] pPacketInfo An application-provided pointer to store - * \ref RAIL_RxPacketInfo_t for the requested packet. Must be non-NULL. - * @return The packet handle for the requested packet: - * if packetHandle was one of the sentinel values, returns the actual - * packet handle for that packet, otherwise returns packetHandle. - * It may return \ref RAIL_RX_PACKET_HANDLE_INVALID to indicate an error. - * - * This function can be used in any RX mode. It does not free up any - * internal resources. If used in RX \ref RAIL_DataMethod_t::FIFO_MODE, the - * value in \ref RAIL_RxPacketInfo_t::packetBytes will only return the data - * remaining in the FIFO. Any data read via earlier calls to - * \ref RAIL_ReadRxFifo() is not included. - * - * @note When getting information about an arriving packet that is not yet complete, - * (i.e., pPacketInfo->packetStatus == \ref RAIL_RX_PACKET_RECEIVING), keep - * in mind its data is highly suspect because it has not yet passed any CRC - * integrity checking. Also note that the packet could be aborted, canceled, or - * fail momentarily, invalidating its data in Packet mode. Furthermore, there - * is a small chance towards the end of packet reception that the filled-in - * RAIL_RxPacketInfo_t could include not only packet data received so far, - * but also some raw radio-appended info detail bytes that RAIL's - * packet-completion processing will subsequently deal with. It's up to the - * application to know its packet format well enough to avoid confusing such - * info as packet data. - */ -RAIL_RxPacketHandle_t RAIL_GetRxPacketInfo(RAIL_Handle_t railHandle, - RAIL_RxPacketHandle_t packetHandle, - RAIL_RxPacketInfo_t *pPacketInfo); - -/** - * Get information about the live incoming packet (if any). - * Differs from \ref RAIL_GetRxPacketInfo() by only returning information - * about a packet actively being received, something which even the - * \ref RAIL_RX_PACKET_HANDLE_NEWEST may not represent if there are - * completed but unprocessed packets in the receive FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] pPacketInfo Application provided pointer to store - * RAIL_RxPacketInfo_t for the incoming packet. - * - * This function can only be called from callback context, e.g., - * when handling \ref RAIL_EVENT_RX_FILTER_PASSED or - * \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND. - * It must not be used with receive \ref RAIL_DataMethod_t::FIFO_MODE - * if any portion of an incoming packet has already been extracted from - * the receive FIFO. - * - * @note The incomplete data of an arriving packet is highly suspect because - * it has not yet passed any CRC integrity checking. Also note that the - * packet could be aborted, canceled, or fail momentarily, invalidating - * its data in Packet mode. Furthermore, there is a small chance towards - * the end of packet reception that the filled-in RAIL_RxPacketInfo_t - * could include not only packet data received so far, but also some raw - * radio-appended info detail bytes that RAIL's packet-completion - * processing will subsequently deal with. It's up to the application to - * know its packet format well enough to avoid confusing such info as - * packet data. - */ -void RAIL_GetRxIncomingPacketInfo(RAIL_Handle_t railHandle, - RAIL_RxPacketInfo_t *pPacketInfo); - -/** - * Copy a full packet to a user-specified contiguous buffer. - * - * @param[out] pDest An application-provided pointer to a buffer of at - * least pPacketInfo->packetBytes in size to store the packet data - * contiguously. This buffer must never overlay RAIL's receive FIFO buffer. - * Exactly pPacketInfo->packetBytes of packet data will be written into it. - * @param[in] pPacketInfo - * \ref RAIL_RxPacketInfo_t for the requested packet. - * - * @note This is a convenience helper function, which - * is intended to be expedient. As a result, it does not - * check the validity of its arguments, - * so don't pass either as NULL, and don't - * pass a pDest pointer to a buffer that's too small for the packet's data. - * @note If only a portion of the packet is needed, use RAIL_PeekRxPacket() - * instead. - */ -static inline -void RAIL_CopyRxPacket(uint8_t *pDest, - const RAIL_RxPacketInfo_t *pPacketInfo) -{ - (void)memcpy(pDest, pPacketInfo->firstPortionData, pPacketInfo->firstPortionBytes); - if (pPacketInfo->lastPortionData != NULL) { - uint16_t size = pPacketInfo->packetBytes - pPacketInfo->firstPortionBytes; - (void)memcpy(pDest + pPacketInfo->firstPortionBytes, - pPacketInfo->lastPortionData, size); - } -} - -/** - * Get detailed information about a received packet. - * This function can be used in any RX mode; it does not free up any - * internal resources. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] packetHandle A packet handle for the unreleased packet as - * returned from a previous call to RAIL_GetRxPacketInfo() or - * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST, - * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE - * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. - * @param[in,out] pPacketDetails An application-provided non-NULL pointer to - * store \ref RAIL_RxPacketDetails_t for the requested packet. - * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, - * the timeReceived fields totalPacketBytes and timePosition must be - * initialized prior to each call: - * - totalPacketBytes with the total number of bytes of the received - * packet for RAIL to use when calculating the specified timestamp. - * This should account for all bytes received over the air after the - * Preamble and Sync word(s), including CRC bytes. - * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying - * the packet position to put in the timeReceived field on return. - * This field will also be updated with the actual position corresponding - * to the timeReceived value filled in. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, - * or an appropriate error code otherwise. - * - * @note Certain details are always available, while others are only available - * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO - * option is not in effect and the received packet's - * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. - * See \ref RAIL_RxPacketDetails_t for clarification. - * - * @note Consider using \ref RAIL_GetRxPacketDetailsAlt for smaller code size. - */ -RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle, - RAIL_RxPacketHandle_t packetHandle, - RAIL_RxPacketDetails_t *pPacketDetails); - -/** - * Get detailed information about a received packet. - * This function can be used in any RX mode. It does not free up any - * internal resources. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] packetHandle A packet handle for the unreleased packet as - * returned from a previous call to RAIL_GetRxPacketInfo() or - * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST - * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE or - * \ref RAIL_RX_PACKET_HANDLE_NEWEST. - * @param[out] pPacketDetails An application-provided non-NULL pointer to - * store \ref RAIL_RxPacketDetails_t for the requested packet. - * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, - * the timeReceived field packetTime will be populated with a timestamp - * corresponding to a default location in the packet. The timeReceived field - * timePosition will be populated with a \ref RAIL_PacketTimePosition_t value - * specifying that default packet location. Call - * \ref RAIL_GetRxTimePreambleStart, \ref RAIL_GetRxTimeSyncWordEnd, or - * \ref RAIL_GetRxTimeFrameEnd to adjust that timestamp for different - * locations in the packet. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, - * or an appropriate error code otherwise. - * - * This alternative API allows for smaller code size by deadstripping the - * timestamp adjustment algorithms which are not in use. - * - * @note Certain details are always available, while others are only available - * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO - * option is not in effect and the received packet's - * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. - * See \ref RAIL_RxPacketDetails_t for clarification. - */ -RAIL_Status_t RAIL_GetRxPacketDetailsAlt(RAIL_Handle_t railHandle, - RAIL_RxPacketHandle_t packetHandle, - RAIL_RxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL RX timestamp to refer to the start of the preamble. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the received packet - * for RAIL to use when calculating the specified timestamp. This should - * account for all bytes received over the air after the Preamble and Sync - * word(s), including CRC bytes. - * @param[in, out] pPacketTime The time that was returned in the - * \ref RAIL_PacketTimeStamp_t::packetTime field of - * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to - * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this - * function, the time at that location will be updated with the time that the - * preamble for this packet started on air. Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, - * or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API - * may return incorrect timestamps when sub-phys are in use. Prefer - * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See - * \ref RAIL_RxPacketDetails_t::subPhyId for more details. - */ -RAIL_Status_t RAIL_GetRxTimePreambleStart(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL RX timestamp to refer to the start of the preamble. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. - * The application must update the timeReceived field totalPacketBytes to be - * the total number of bytes of the received packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * received over the air after the Preamble and Sync word(s), including CRC - * bytes. After this function, the timeReceived field packetTime will be - * updated with the time that the preamble for this packet started on air. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_GetRxTimePreambleStartAlt(RAIL_Handle_t railHandle, - RAIL_RxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL RX timestamp to refer to the end of the sync word. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the received packet - * for RAIL to use when calculating the specified timestamp. This should - * account for all bytes received over the air after the Preamble and Sync - * word(s), including CRC bytes. - * @param[in, out] pPacketTime The time that was returned in the - * \ref RAIL_PacketTimeStamp_t::packetTime field of - * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to - * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this - * function, the time at that location will be updated with the time that the - * sync word for this packet finished on air. Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, - * or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API - * may return incorrect timestamps when sub-phys are in use. Prefer - * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See - * \ref RAIL_RxPacketDetails_t::subPhyId for more details. - */ -RAIL_Status_t RAIL_GetRxTimeSyncWordEnd(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL RX timestamp to refer to the end of the sync word. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. - * The application must update the timeReceived field totalPacketBytes to be - * the total number of bytes of the received packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * received over the air after the Preamble and Sync word(s), including CRC - * bytes. After this function, the timeReceived field packetTime will be - * updated with the time that the sync word for this packet finished on air. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_GetRxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, - RAIL_RxPacketDetails_t *pPacketDetails); - -/** - * Adjust a RAIL RX timestamp to refer to the end of frame. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] totalPacketBytes The total number of bytes of the received packet - * for RAIL to use when calculating the specified timestamp. This should - * account for all bytes received over the air after the Preamble and Sync - * word(s), including CRC bytes. - * @param[in, out] pPacketTime The time that was returned in the - * \ref RAIL_PacketTimeStamp_t::packetTime field of - * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to - * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this - * function, the time at that location will be updated with the time that this - * packet finished on air. Must be non-NULL. - * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, - * or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API - * may return incorrect timestamps when sub-phys are in use. Prefer - * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See - * \ref RAIL_RxPacketDetails_t::subPhyId for more details. - */ -RAIL_Status_t RAIL_GetRxTimeFrameEnd(RAIL_Handle_t railHandle, - uint16_t totalPacketBytes, - RAIL_Time_t *pPacketTime); - -/** - * Adjust a RAIL RX timestamp to refer to the end of frame. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] pPacketDetails The non-NULL details that were returned from - * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. - * The application must update the timeReceived field totalPacketBytes to be - * the total number of bytes of the received packet for RAIL to use when - * calculating the specified timestamp. This should account for all bytes - * received over the air after the Preamble and Sync word(s), including CRC - * bytes. After this function, the timeReceived field packetTime will be - * updated with the time that the packet finished on air. - * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully - * calculated, or an appropriate error code otherwise. - * - * Call this API while the given railHandle is active, or it will - * return an error code of \ref RAIL_STATUS_INVALID_STATE. - */ -RAIL_Status_t RAIL_GetRxTimeFrameEndAlt(RAIL_Handle_t railHandle, - RAIL_RxPacketDetails_t *pPacketDetails); - -/** @} */ // end of group Packet_Information - -/** - * Place a temporary hold on this packet's data and information resources - * within RAIL. - * This function can only be called from within RAIL callback context. - * It can be used in any RX mode. - * - * Normally, when RAIL issues its callback indicating a packet is ready - * or aborted, it expects the application's callback to retrieve and - * copy (or discard) the packet's information and data, and will free up - * its internal packet data after the callback returns. This function - * tells RAIL to hold onto those resources after the callback returns in - * case the application wants to defer processing the packet to a later - * time, e.g., outside of callback context. - * - * @param[in] railHandle A RAIL instance handle. - * @return The packet handle for the packet associated with the callback, - * \ref RAIL_RX_PACKET_HANDLE_INVALID if no such packet yet exists or - * railHandle is not active. - * - * @note When using multiprotocol the receive FIFO is reset during protocol - * switches so any packets held with \ref RAIL_HoldRxPacket() will be lost. It - * is best to avoid using this in DMP or to at least reset any internal held - * packet information when the \ref RAIL_EVENT_CONFIG_UNSCHEDULED occurs. - */ -RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle); - -/** - * Copy 'len' bytes of packet data starting from 'offset' from the - * receive FIFO. Those bytes remain valid for re-peeking. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] packetHandle A packet handle as returned from a previous - * RAIL_GetRxPacketInfo() or RAIL_HoldRxPacket() call, or - * sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST, - * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE - * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. - * @param[out] pDst A pointer to the location where the received bytes will - * be copied. If NULL, no copying occurs. - * @param[in] len A number of packet data bytes to copy. - * @param[in] offset A byte offset within remaining packet data from which - * to copy. - * @return Number of packet bytes copied. - * - * @note Peek does not permit peeking beyond the requested packet's - * available packet data (though there is a small chance it might - * for a \ref RAIL_RX_PACKET_HANDLE_NEWEST packet at the very end of - * still being received). Nor can one peek into already-consumed data read - * by RAIL_ReadRxFifo(). len and offset are relative to the remaining data - * available in the packet, if any was already consumed by RAIL_ReadRxFifo(). - */ -uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle, - RAIL_RxPacketHandle_t packetHandle, - uint8_t *pDst, - uint16_t len, - uint16_t offset); - -/** - * Release RAIL's internal resources for the packet. - * This function must be called for any packet previously held via - * RAIL_HoldRxPacket(). It may optionally be called within a - * callback context to release RAIL resources sooner than at - * callback completion time when not holding the packet. - * This function can be used in any RX mode. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] packetHandle A packet handle as returned from a previous - * RAIL_HoldRxPacket() call, or sentinel values - * \ref RAIL_RX_PACKET_HANDLE_OLDEST, - * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE - * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. - * The latter might be used within RAIL callback context to explicitly - * release the packet associated with the callback early, before it's - * released automatically by RAIL on callback return (unless explicitly - * held). - * @return \ref RAIL_STATUS_NO_ERROR if the held packet was released - * or an appropriate error code otherwise. - */ -RAIL_Status_t RAIL_ReleaseRxPacket(RAIL_Handle_t railHandle, - RAIL_RxPacketHandle_t packetHandle); - -/** - * Return the current raw RSSI. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] wait if false returns instant RSSI with no checks. - * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI - * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. - * - * Gets the current RSSI value. This value represents the current energy of the - * channel. It can change rapidly and will be low if no RF energy is - * in the current channel. The function from the value reported to dBm is an - * offset dependent on the PHY and the PCB layout. Characterize the - * RSSI received on your hardware and apply an offset in the application to - * account for board and PHY parameters. When 'wait' is false, the radio needs - * to be currently in RX and have been in there for a sufficient amount of time - * for a fresh RSSI value to be read and returned. Otherwise, the RSSI is - * considered stale and \ref RAIL_RSSI_INVALID is returned instead. When 'wait' - * is true, if the radio is transitioning to or already in RX, this function - * will wait for a valid RSSI to be read and return it. Otherwise, if the radio - * is in or transitions to IDLE or TX, \ref RAIL_RSSI_INVALID will be returned. - * On low datarate PHYs, this function can take a significantly longer time when - * wait is true. - * - * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. - * Additionally, 'wait' should never be set 'true' in multiprotocol - * as the wait time is not consistent, so scheduling a scheduler - * slot cannot be done accurately. Rather if waiting for a valid RSSI is - * desired, use \ref RAIL_GetRssiAlt instead to apply a bounded time period. - * - * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), - * pass true for the wait parameter otherwise it's very likely - * \ref RAIL_RSSI_INVALID will be returned. - * - * @note If RX channel hopping is turned on, do not use this API. - * Instead, see RAIL_GetChannelHoppingRssi(). - * - * @note When 'wait' is false, this API is equivalent to \ref RAIL_GetRssiAlt - * with 'waitTimeout' set to \ref RAIL_GET_RSSI_NO_WAIT. When 'wait' is - * true, this API is equivalent to \ref RAIL_GetRssiAlt with 'waitTimeout' - * set to \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT. Consider using - * \ref RAIL_GetRssiAlt if a bounded maximum wait timeout is desired. - */ -int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); - -/** - * Return the current raw RSSI within a definitive time period. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] waitTimeout Sets the maximum time to wait for a valid RSSI. - * If equal to \ref RAIL_GET_RSSI_NO_WAIT returns instant RSSI with no checks. - * If equal to \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT waits for a valid RSSI - * with no maximum timeout. - * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI - * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. - * - * Gets the current RSSI value. This value represents the current energy of the - * channel. It can change rapidly, and will be low if no RF energy is - * in the current channel. The function from the value reported to dBm is an - * offset dependent on the PHY and the PCB layout. Characterize the - * RSSI received on your hardware and apply an offset in the application to - * account for board and PHY parameters. If a value of \ref RAIL_GET_RSSI_NO_WAIT - * is given for waitTimeout, the radio needs to be currently in RX and have been - * in there for a sufficient amount of time for a fresh RSSI value to be read and - * returned. Otherwise the RSSI is considered stale and \ref RAIL_RSSI_INVALID is - * returned instead. For non-zero values of waitTimeout, if the radio is - * transitioning to or already in RX, this function will wait a maximum time equal - * to waitTimeout (or indefinitely if waitTimeout is set to - * \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT) for a valid RSSI to be read and return - * it. Otherwise, if the waitTimeout is reached, or the radio is in or transitions - * to IDLE or TX, \ref RAIL_RSSI_INVALID will be returned. On low datarate PHYs, - * this function can take a significantly longer time when waitTimeout is non-zero. - * - * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. - * Additionally, 'waitTimeout' should never be set to a value other than - * \ref RAIL_GET_RSSI_NO_WAIT in multiprotocol as the integration between this - * feature and the radio scheduler has not been implemented. - * - * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), - * pass true for the wait parameter otherwise it's very likely - * \ref RAIL_RSSI_INVALID will be returned. - * - * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), - * the RSSI value returned could come from either antenna and vary between antennas. - * - * @note If RX channel hopping is turned on, do not use this API. - * Instead, see RAIL_GetChannelHoppingRssi(). - */ -int16_t RAIL_GetRssiAlt(RAIL_Handle_t railHandle, RAIL_Time_t waitTimeout); - -/** - * Start the RSSI averaging over a specified time in us. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel The physical channel to set. - * @param[in] averagingTimeUs Averaging time in microseconds. - * @param[in] schedulerInfo Information to allow the radio scheduler to place - * this operation appropriately. This is only used in multiprotocol version of - * RAIL and may be set to NULL in all other versions. - * @return Status code indicating success of the function call. - * - * Starts a non-blocking hardware-based RSSI averaging mechanism. Only a single - * instance of RSSI averaging can be run at any time and the radio must be idle - * to start. - * - * In multiprotocol, this is a scheduled event. It will start when railHandle - * becomes active. railHandle needs to stay active until the averaging - * completes. If the averaging is interrupted, calls to - * \ref RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID. - * - * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio - * after this event completes (i.e., when \ref RAIL_EVENT_RSSI_AVERAGE_DONE - * occurs). - * - * @note If the radio is idled while RSSI averaging is still in effect, a - * \ref RAIL_EVENT_RSSI_AVERAGE_DONE event may not occur and - * \ref RAIL_IsAverageRssiReady may never return true. - */ -RAIL_Status_t RAIL_StartAverageRssi(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_Time_t averagingTimeUs, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Query whether the RSSI averaging is done. - * - * @param[in] railHandle A RAIL instance handle. - * @return Returns true if done and false otherwise. - * - * This function can be used to poll for completion of the RSSI averaging - * to avoid relying on an interrupt-based callback. - * - * @note If the radio is idled while RSSI averaging is still in effect, - * this function may never return true. - */ -bool RAIL_IsAverageRssiReady(RAIL_Handle_t railHandle); - -/** - * Get the RSSI averaged over a specified time in us. - * - * @param[in] railHandle A RAIL instance handle. - * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled - * an RSSI value can't be obtained. Otherwise, return the RSSI in - * quarter dBm,dbm*4. - * - * Gets the hardware RSSI average after issuing RAIL_StartAverageRssi. - * Use after \ref RAIL_StartAverageRssi. - */ -int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle); - -/** - * Set the RSSI offset. - * - * @param[in] railHandle a RAIL instance handle. - * @param[in] rssiOffset desired offset to be added to the RSSI measurements. - * @return Status code indicating success of the function call. - * \ref RAIL_STATUS_INVALID_CALL if called with chip-specific handle, such - * as \ref RAIL_EFR32_HANDLE, after RAIL initialization. - * \ref RAIL_STATUS_INVALID_PARAMETER if the RSSI offset is deemed large - * enough to cause the RSSI readings to underflow or overflow. - * - * Adds an offset to the RSSI in dBm. This offset affects all functionality that - * depends on RSSI values, such as CCA functions. Do not modify the offset - * dynamically during packet reception. This function - * can only be called while the radio is off, or in the case of multiprotocol, - * on an inactive protocol. - * - * @note: If RAIL has not been initialized, a chip-specific handle, - * such as \ref RAIL_EFR32_HANDLE, can be used to set a chip level RSSI offset. - * - * @note: Setting a large rssiOffset may still cause the RSSI readings to - * underflow. If that happens, the RSSI value returned by - * \ref RAIL_GetRssi, \ref RAIL_GetAverageRssi, - * \ref RAIL_GetChannelHoppingRssi etc. will be \ref RAIL_RSSI_LOWEST - * - * @note: During \ref Rx_Channel_Hopping this API will not update the - * RSSI offset immediately if channel hopping has already been configured. - * A subsequent call to \ref RAIL_ZWAVE_ConfigRxChannelHopping or - * \ref RAIL_ConfigRxChannelHopping is required for the new RSSI offset to - * take effect. - */ -RAIL_Status_t RAIL_SetRssiOffset(RAIL_Handle_t railHandle, int8_t rssiOffset); - -/** - * Get the RSSI offset. - * - * @param[in] railHandle a RAIL instance handle. - * @return rssiOffset in dBm corresponding to the current handle. - * - * @note: A chip-specific handle, such as \ref RAIL_EFR32_HANDLE, can be used to - * get the chip level RSSI offset otherwise this will return the RSSI offset - * value associated with the RAIL instance handle, exclusive of any chip level - * RSSI offset correction, if any. - */ -int8_t RAIL_GetRssiOffset(RAIL_Handle_t railHandle); - -/** - * Set the RSSI detection threshold(in dBm) to trigger - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD. - * - * @param[in] railHandle a RAIL instance handle. - * @param[in] rssiThresholdDbm desired RSSI threshold(in dBm) over which the event - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD is triggered. - * @return Status code indicating success of the function call. - * Returns \ref RAIL_STATUS_INVALID_STATE in multiprotocol, - * if the requested \ref RAIL_Handle_t is not active. - * Returns \ref RAIL_STATUS_INVALID_CALL if called on parts on which this function - * is not supported. - * - * When in receive, RSSI is sampled and if it exceeds the threshold, - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD is triggered. - * - * @note: - * If the radio is idled or this function is called with rssiThresholdDbm as - * \ref RAIL_RSSI_INVALID_DBM while RSSI detect is still in effect, a - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD may not occur and the detection is disabled. - * If the RSSI is already above threshold when this function is called then - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD will occur. - * Once the RSSI goes over the configured threshold and - * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD occurs, this function needs to be - * called again to reactivate the RSSI threshold detection. - * This function is only available on series-2 Sub-GHz parts EFR32XG23 and EFR32XG25. - */ -RAIL_Status_t RAIL_SetRssiDetectThreshold(RAIL_Handle_t railHandle, - int8_t rssiThresholdDbm); - -/** - * Get the RSSI detection threshold(in dBm). - * - * @param[in] railHandle a RAIL instance handle. - * @return rssiThreshold (in dBm) corresponding to the current handle. - * @note: - * The function returns \ref RAIL_RSSI_INVALID_DBM when - * \ref RAIL_SetRssiDetectThreshold is not supported or disabled. - * In multiprotocol, the function returns \ref RAIL_RSSI_INVALID_DBM if railHandle - * is not active. - * This function is only available on series-2 Sub-GHz parts EFR32XG23 and EFR32XG25. - */ -int8_t RAIL_GetRssiDetectThreshold(RAIL_Handle_t railHandle); - -/** - * Set up a callback function capable of converting a RX packet's LQI value - * before being consumed by application code. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] cb A callback of type \ref RAIL_ConvertLqiCallback_t that is - * called before the RX packet LQI value is loaded into the \ref - * RAIL_RxPacketDetails_t structure for application consumption. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ConvertLqi(RAIL_Handle_t railHandle, - RAIL_ConvertLqiCallback_t cb); - -/****************************************************************************** - * Address Filtering (RX) - *****************************************************************************/ -/** - * @addtogroup Address_Filtering Address Filtering - * @brief Configuration APIs for receive packet address filtering. - * - * The address filtering code examines the packet as follows. - * - * | `Bytes: 0 - 255` | `0 - 8` | `0 - 255` | `0 - 8` | `Variable` | - * |:----------------:|---------:|----------:|---------:|:----------:| - * | `Data0` | `Field0` | `Data1` | `Field1` | `Data2` | - * - * In the above structure, anything listed as DataN is an optional section of - * bytes that RAIL will not process for address filtering. The FieldN segments - * reference specific sections in the packet that will each be interpreted - * as an address during address filtering. The application may submit up to - * four addresses to attempt to match each field segment and each address may - * have a size of up to 8 bytes. To set up address filtering, first configure - * the locations and length of the addresses in the packet. Next, configure - * which combinations of matches in Field0 and Field1 should constitute an - * address match. Last, enter addresses into tables for each field and - * enable them. The first two of these are part of the \ref RAIL_AddrConfig_t - * structure while the second part is configured at runtime using the - * RAIL_SetAddressFilterAddress() API. A brief description of each - * configuration is listed below. - * - * The offsets and sizes of the fields - * are assumed fixed for the RAIL address filter. To set them, specify - * arrays for these values in the sizes and offsets entries in the - * \ref RAIL_AddrConfig_t structure. A size of zero indicates that a field is - * disabled. The start offset for a field is relative to the previous start - * offset and, if you're using FrameType decoding, the first start offset is - * relative to the end of the byte containing the frame type. - * - * Configuring which combinations of Field0 and Field1 constitute a match is - * the most complex portion of the address filter. The easiest way to think - * about this is with a truth table. If you consider each of the four possible - * address entries in a field, you can have a match on any one of those or a - * match for none of them. This is shown in the 5x5 truth table below where - * Field0 matches are the rows and Field1 matches are the columns. - * - * | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | - * |----------------|----------|-----------|-----------|-----------|-----------| - * | __No Match__ | bit0 | bit1 | bit2 | bit3 | bit4 | - * | __Address 0__ | bit5 | bit6 | bit7 | bit8 | bit9 | - * | __Address 1__ | bit10 | bit11 | bit12 | bit13 | bit14 | - * | __Address 2__ | bit15 | bit16 | bit17 | bit18 | bit19 | - * | __Address 3__ | bit20 | bit21 | bit22 | bit23 | bit24 | - * - * Because this is only 25 bits, it can be represented in one 32-bit integer - * where 1 indicates a filter pass and 0 indicates a filter fail. This is the - * matchTable parameter in the configuration structure and is used during - * filtering. For common simple configurations, two defines are provided with - * the truth tables as shown below. The first is \ref - * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD, which can be used if only using - * one address field (either field). If using two fields and want to - * force in the same address entry in each field, use the second define: \ref - * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems, - * create a valid custom table. - * - * @note Address filtering does not function reliably with PHYs that use a data - * rate greater than 500 kbps. If this is a requirement, filtering must - * currently be done by the application. - * - * @{ - */ - -/** - * Configure address filtering. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] addrConfig The configuration structure, which defines how - * addresses are set up in your packets. - * @return Status code indicating success of the function call. - * - * You must call this function to set up address filtering. You may call it - * multiple times but all previous information is wiped out each time you call - * and any configured addresses must be reset. - */ -RAIL_Status_t RAIL_ConfigAddressFilter(RAIL_Handle_t railHandle, - const RAIL_AddrConfig_t *addrConfig); - -/** - * Enable address filtering. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable An argument to indicate whether or not to enable address - * filtering. - * @return True if address filtering was enabled to start with and false - * otherwise. - * - * Only allow packets through that pass the current address filtering - * configuration. This does not reset or change the configuration so you can - * set that up before turning on this feature. - */ -bool RAIL_EnableAddressFilter(RAIL_Handle_t railHandle, bool enable); - -/** - * Return whether address filtering is currently enabled. - * - * @param[in] railHandle A RAIL instance handle. - * @return True if address filtering is enabled and false otherwise. - */ -bool RAIL_IsAddressFilterEnabled(RAIL_Handle_t railHandle); - -/** - * Reset the address filtering configuration. - * - * @param[in] railHandle A RAIL instance handle. - * - * Resets all structures related to address filtering. This does not disable - * address filtering. It leaves the radio in a state where no packets - * pass filtering. - */ -void RAIL_ResetAddressFilter(RAIL_Handle_t railHandle); - -/** - * Set an address for filtering in hardware. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] field Indicates an address field for this address. - * @param[in] index Indicates a match entry for this address for a - * given field. - * @param[in] value A pointer to the address data. This must be at least as - * long as the size specified in RAIL_ConfigAddressFilter(). The first byte, - * value[0], will be compared to the first byte received over the air for this - * address field. - * @param[in] enable A boolean to indicate whether this address should be - * enabled immediately. - * @return Status code indicating success of the function call. - * - * This function loads the given address into hardware for filtering and - * starts filtering if you set the enable parameter to true. Otherwise, - * call RAIL_EnableAddressFilterAddress() to turn it on later. - */ -RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, - uint8_t field, - uint8_t index, - const uint8_t *value, - bool enable); - -/** - * Set an address bit mask for filtering in hardware. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] field Indicates an address field for this address bit mask. - * @param[in] bitMask A pointer to the address bitmask. This must be at least - * as long as the size specified in RAIL_ConfigAddressFilter(). The first - * byte, bitMask[0], will be applied to the first byte received over the air - * for this address field. Bits set to 1 in the bit mask indicate which bit - * positions in the incoming packet to compare against the stored addresses - * during address filtering. Bits set to 0 indicate which bit positions to - * ignore in the incoming packet during address filtering. This bit mask is - * applied to all address entries. - * @return Status code indicating success of the function call. - * - * This function loads the given address bit mask into hardware for use when - * address filtering is enabled. All bits in the stored address bit mask are - * set to 1 during hardware initialization and when either \ref - * RAIL_ConfigAddressFilter() or \ref RAIL_ResetAddressFilter() are called. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips - * or the EFR32XG21. Use the compile time symbol \ref - * RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK or the runtime call \ref - * RAIL_SupportsAddrFilterAddressBitMask() to check whether the platform - * supports this feature. - */ -RAIL_Status_t RAIL_SetAddressFilterAddressMask(RAIL_Handle_t railHandle, - uint8_t field, - const uint8_t *bitMask); - -/** - * Enable address filtering for the specified address. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable An argument to indicate whether or not to enable address - * filtering. - * @param[in] field Indicates an address for the address. - * @param[in] index Indicates a match entry in the given field you want to enable. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, - bool enable, - uint8_t field, - uint8_t index); - -/** @} */ // end of group Address_Filtering - -/** @} */ // end of group Receive - -/****************************************************************************** - * Auto-ACKing - *****************************************************************************/ -/// @addtogroup Auto_Ack Auto-ACK -/// @brief APIs for configuring auto-ACK functionality -/// -/// These APIs configure the radio for automatic acknowledgment -/// features. Auto-ACK inherently changes how the underlying state machine -/// behaves so users should not modify RAIL_SetRxTransitions() and -/// RAIL_SetTxTransitions() while using auto-ACK features. -/// -/// @code{.c} -/// // Go to RX after ACK operation. -/// RAIL_AutoAckConfig_t autoAckConfig = { -/// .enable = true, -/// .ackTimeout = 1000, -/// // "error" param ignored -/// .rxTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX}, -/// // "error" param ignored -/// .txTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX} -/// }; -/// -/// RAIL_Status_t status = RAIL_ConfigAutoAck(railHandle, &autoAckConfig); -/// -/// uint8_t ackData[] = {0x05, 0x02, 0x10, 0x00}; -/// -/// RAIL_Status_t status = RAIL_WriteAutoAckFifo(railHandle, -/// ackData, -/// sizeof(ackData)); -/// @endcode -/// -/// The acknowledgment transmits based on the frame format configured via -/// the Radio Configurator. For example, if the frame format is using a variable -/// length scheme, the ACK will be sent according to that scheme. If a 10-byte -/// packet is loaded into the ACK, but the variable length field of the ACK -/// payload specifies a length of 5, only 5 bytes will transmit for the ACK. -/// The converse is also true, if the frame length is configured to be a fixed -/// 10-byte packet but only 5 bytes are loaded into the ACK buffer, a TX -/// underflow occurs during the ACK transmit. -/// -/// Unlike in non-auto-ACK mode, auto-ACK mode will always return to a single -/// state after all ACK sequences complete, regardless of whether -/// the ACK was successfully received/sent or not. See the documentation -/// of \ref RAIL_ConfigAutoAck() for configuration information. To -/// suspend automatic acknowledgment of a series of packets after transmit -/// or receive call RAIL_PauseTxAutoAck() or RAIL_PauseRxAutoAck() respectively -/// with the pause parameter set to true. When auto-ACKing is paused, after -/// receiving or transmitting a packet (regardless of success), the radio -/// transitions to the same state it would use while ACKing. To return to -/// normal state transition logic outside of ACKing, call \ref -/// RAIL_ConfigAutoAck() with the \ref RAIL_AutoAckConfig_t::enable field false -/// and specify the desired transitions in the \ref -/// RAIL_AutoAckConfig_t::rxTransitions and RAIL_AutoAckConfig_t::txTransitions -/// fields. To get out of a paused state and resume auto-ACKing, call -/// RAIL_PauseTxAutoAck() and/or RAIL_PauseRxAutoAck() with the pause parameter -/// set to false. -/// -/// Applications can cancel the transmission of an ACK with -/// RAIL_CancelAutoAck(). Conversely, applications can control if a transmit -/// operation should wait for an ACK after transmitting by using -/// the \ref RAIL_TX_OPTION_WAIT_FOR_ACK option. -/// -/// When \ref Antenna_Control is used for multiple antennas, ACKs are -/// transmitted on the antenna that was selected to receive the packet -/// being acknowledged. When receiving an ACK, the -/// \ref RAIL_RxOptions_t antenna options are used just like for any other -/// receive. -/// -/// If the ACK payload is dynamic, the application must call -/// RAIL_WriteAutoAckFifo() with the appropriate ACK payload after the -/// application processes the receive. RAIL can auto-ACK from the normal -/// transmit buffer if RAIL_UseTxFifoForAutoAck() is called before the radio -/// transmits the ACK. Ensure the transmit buffer contains data loaded by -/// RAIL_WriteTxFifo(). -/// -/// Standard-based protocols that contain auto-ACK functionality are normally -/// configured in the protocol-specific configuration function. For example, -/// RAIL_IEEE802154_Init() provides auto-ACK configuration parameters in \ref -/// RAIL_IEEE802154_Config_t and should only be configured through that -/// function. It is not advisable to call both RAIL_IEEE802154_Init() and \ref -/// RAIL_ConfigAutoAck(). However, ACK modification functions are still valid to -/// use with protocol-specific ACKs. To cancel an IEEE 802.15.4 ACK transmit, -/// use RAIL_CancelAutoAck(). -/// -/// @{ - -/// Configure and enable automatic acknowledgment. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @param[in] config Auto-ACK configuration structure. -/// @return Status code indicating success of the function call. -/// -/// Configures the RAIL state machine to for hardware-accelerated automatic -/// acknowledgment. ACK timing parameters are defined in the configuration -/// structure. -/// -/// While auto-ACKing is enabled, do not call the following RAIL functions: -/// - RAIL_SetRxTransitions() -/// - RAIL_SetTxTransitions() -/// -/// Note that if you are enabling auto-ACK (i.e., "enable" field is true) -/// the "error" fields of rxTransitions and txTransitions are ignored. -/// After all ACK sequences, (success or fail) the state machine will return -/// the radio to the "success" state, which can be either -/// \ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE (returning to -/// \ref RAIL_RF_STATE_TX is not supported). -/// If you need information about the -/// actual success of the ACK sequence, use RAIL events such as -/// \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an ACK was sent, or -/// \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an ACK was received -/// within the specified timeout. -/// -/// To set a certain turnaround time (i.e., txToRx and rxToTx -/// in \ref RAIL_StateTiming_t), make txToRx lower than -/// desired to ensure you get to RX in time to receive the ACK. -/// Silicon Labs recommends setting 10 us lower than desired: -/// -/// @code{.c} -/// void setAutoAckStateTimings() -/// { -/// RAIL_StateTiming_t timings; -/// -/// // User is already in auto-ACK and wants a turnaround of 192 us. -/// timings.rxToTx = 192; -/// timings.txToRx = 192 - 10; -/// -/// // Set other fields of timings... -/// timings.idleToRx = 100; -/// timings.idleToTx = 100; -/// timings.rxSearchTimeout = 0; -/// timings.txToRxSearchTimeout = 0; -/// -/// RAIL_SetStateTiming(railHandle, &timings); -/// } -/// @endcode -/// -/// As opposed to an explicit "Disable" API, set the "enable" -/// field of the RAIL_AutoAckConfig_t to false. Then, auto-ACK will be -/// disabled and state transitions will be returned to the values set -/// in \ref RAIL_AutoAckConfig_t. When disabling, the "ackTimeout" field -/// isn't used. -/// -/// @note Auto-ACKing may not be enabled while RX Channel Hopping is enabled, -/// or when BLE is enabled. -/// -RAIL_Status_t RAIL_ConfigAutoAck(RAIL_Handle_t railHandle, - const RAIL_AutoAckConfig_t *config); - -/** - * Return the enable status of the auto-ACK feature. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if auto-ACK is enabled, false if disabled. - */ -bool RAIL_IsAutoAckEnabled(RAIL_Handle_t railHandle); - -/** - * Load the auto-ACK buffer with ACK data. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] ackData A pointer to ACK data to transmit. - * This may be NULL, in which case it's assumed the data has already - * been emplaced into the ACK buffer and RAIL just needs to be told - * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get - * the address of RAIL's AutoACK buffer in RAM and its size. - * @param[in] ackDataLen The number of bytes in ACK data. - * @return Status code indicating success of the function call. - * - * If the ACK buffer is available for updates, load the ACK buffer with data. - * If it is not available, \ref RAIL_STATUS_INVALID_STATE is returned. - * If ackDataLen exceeds \ref RAIL_AUTOACK_MAX_LENGTH then - * \ref RAIL_STATUS_INVALID_PARAMETER will be returned and nothing is - * written to the ACK buffer (unless ackData is NULL in which case this - * indicates the application has already likely corrupted RAM). - */ -RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle, - const uint8_t *ackData, - uint8_t ackDataLen); - -/** - * Get the address and size of the auto-ACK buffer for direct access. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] ackBuffer A pointer to a uint8_t pointer that will be - * updated to the RAM base address of the TXACK buffer. - * @param[in,out] ackBufferBytes A pointer to a uint16_t that will be - * updated to the size of the TXACK buffer, in bytes, which is - * currently \ref RAIL_AUTOACK_MAX_LENGTH. - * @return Status code indicating success of the function call. - * - * Applications can use this to more flexibly write AutoAck data into - * the buffer directly and in pieces, passing NULL ackData parameter to - * \ref RAIL_WriteAutoAckFifo() or \ref RAIL_IEEE802154_WriteEnhAck() - * to inform RAIL of its final length. - */ -RAIL_Status_t RAIL_GetAutoAckFifo(RAIL_Handle_t railHandle, - uint8_t **ackBuffer, - uint16_t *ackBufferBytes); - -/** - * Pause/resume RX auto-ACK functionality. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] pause Pause or resume RX auto-ACKing. - * - * When RX auto-ACKing is paused, the radio transitions to default - * state after receiving a packet and does not transmit an ACK. - * When RX auto-ACK is resumed, the radio resumes automatically ACKing - * every successfully received packet. - */ -void RAIL_PauseRxAutoAck(RAIL_Handle_t railHandle, - bool pause); - -/** - * Return whether the RX auto-ACK is paused. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RX auto-ACK is paused, false if not paused. - */ -bool RAIL_IsRxAutoAckPaused(RAIL_Handle_t railHandle); - -/** - * Pause/resume TX auto-ACK functionality. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] pause Pause or resume TX auto-ACKing. - * - * When TX auto-ACKing is paused, the radio transitions to a default - * state after transmitting a packet and does not wait for an ACK. When TX - * auto-ACK is resumed, the radio resumes automatically waiting for - * an ACK after a successful transmit. - */ -void RAIL_PauseTxAutoAck(RAIL_Handle_t railHandle, bool pause); - -/** - * Return whether the TX auto-ACK is paused. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if TX auto-ACK is paused, false if not paused. - */ -bool RAIL_IsTxAutoAckPaused(RAIL_Handle_t railHandle); - -/** - * Modify the upcoming ACK to use the Transmit FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. The call will - * fail if it is too late to modify the outgoing ACK. - * - * This function allows the application to use the normal Transmit FIFO as - * the data source for the upcoming ACK. The ACK modification to use the - * Transmit FIFO only applies to one ACK transmission. - * - * This function only returns true if the following conditions are met: - * - Radio has not already decided to use the ACK buffer AND - * - Radio is either looking for sync, receiving the packet after sync, or in - * the Rx2Tx turnaround before the ACK is sent. - * - * @note The Transmit FIFO must not be used for AutoACK when IEEE 802.15.4, - * Z-Wave, or BLE protocols are active. - */ -RAIL_Status_t RAIL_UseTxFifoForAutoAck(RAIL_Handle_t railHandle); - -/** - * Cancel the upcoming ACK. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. This call will - * fail if it is too late to modify the outgoing ACK. - * - * This function allows the application to cancel the upcoming automatic - * acknowledgment. - * - * This function only returns true if the following conditions are met: - * - Radio has not already decided to transmit the ACK AND - * - Radio is either looking for sync, receiving the packet after sync or in - * the Rx2Tx turnaround before the ACK is sent. - */ -RAIL_Status_t RAIL_CancelAutoAck(RAIL_Handle_t railHandle); - -/** - * Return whether the radio is currently waiting for an ACK. - * - * @param[in] railHandle A RAIL instance handle. - * @return True if radio is waiting for ACK, false if radio is not waiting for - * an ACK. - * - * This function allows the application to query whether the radio is currently - * waiting for an ACK after a transmit operation. - */ -bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); - -/** @} */ // end of group Auto_Ack - -/****************************************************************************** - * Calibration - *****************************************************************************/ -/// @addtogroup Calibration -/// @brief APIs for calibrating the radio -/// @{ -/// -/// These APIs calibrate the radio. The RAIL library -/// determines which calibrations are necessary. Calibrations can -/// be enabled/disabled with the RAIL_CalMask_t parameter. -/// -/// Some calibrations produce values that can be saved and reapplied to -/// avoid repeating the calibration process. -/// -/// Calibrations can either be run with \ref RAIL_Calibrate, or with the -/// individual chip-specific calibration routines. An example for running code -/// with \ref RAIL_Calibrate looks like the following: -/// -/// @code{.c} -/// static RAIL_CalValues_t calValues = RAIL_CALVALUES_UNINIT; -/// -/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { -/// // Omitting other event handlers -/// if (events & RAIL_EVENT_CAL_NEEDED) { -/// // Run all pending calibrations, and save the results -/// RAIL_Calibrate(railHandle, &calValues, RAIL_CAL_ALL_PENDING); -/// } -/// } -/// @endcode -/// -/// Alternatively, if the image rejection calibration for your chip can be -/// determined ahead of time, such as by running the calibration on a separate -/// firmware image on each chip, the following calibration process will -/// result in smaller code. -/// -/// @code{.c} -/// static uint32_t imageRejection = IRCAL_VALUE; -/// -/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { -/// // Omitting other event handlers -/// if (events & RAIL_EVENT_CAL_NEEDED) { -/// RAIL_CalMask_t pendingCals = RAIL_GetPendingCal(railHandle); -/// // Disable the radio if we have to do an offline calibration -/// if (pendingCals & RAIL_CAL_TEMP_VC0) { -/// RAIL_CalibrateTemp(railHandle); -/// } -/// if (pendingCals & RAIL_CAL_ONETIME_IRCAL) { -/// RAIL_ApplyIrCalibration(railHandle, imageRejection); -/// } -/// } -/// } -/// @endcode - -/** - * Initialize RAIL calibration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] calEnable A bitmask that indicates which calibrations - * to enable for a callback notification. - * The exact meaning of these bits is chip-specific. - * @return Status code indicating success of the function call. - * - * Calibration initialization provides the calibration settings that - * correspond to the current radio configuration. - */ -RAIL_Status_t RAIL_ConfigCal(RAIL_Handle_t railHandle, - RAIL_CalMask_t calEnable); - -/** - * Start the calibration process. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] calValues A structure of calibration values to apply. - * If a valid calibration structure is provided and the structure - * contains valid calibration values, those values will be applied to the - * hardware and the RAIL library will cache those values for use again later. - * If a valid calibration structure is provided and the structure - * contains a calibration value of \ref RAIL_CAL_INVALID_VALUE for the - * desired calibration, the desired calibration will run, the calibration - * values structure will be updated with a valid calibration value, and the - * RAIL library will cache that value for use again later. - * If a NULL pointer is provided, the desired calibration will run - * and the RAIL library will cache that value for use again later. However, - * the valid calibration value will not be returned to the application. - * @param[in] calForce A mask to force specific calibration(s) to execute. - * To run all pending calibrations, use the value \ref RAIL_CAL_ALL_PENDING. - * Only the calibrations specified will run, even if not enabled during - * initialization. - * @return Status code indicating success of the function call. - * - * If calibrations were performed previously and the application saves the - * calibration values (i.e., call this function with a calibration values - * structure containing calibration values of \ref RAIL_CAL_INVALID_VALUE - * before a reset), the application can later bypass the time it would normally - * take to recalibrate hardware by reusing previous calibration values (i.e., - * call this function with a calibration values structure containing valid - * calibration values after a reset). - * - * If multiple protocols are used, this function will make the given railHandle - * active, if not already, and perform calibration. If called during a protocol - * switch, to perform an IR calibration for the first time, it will - * return \ref RAIL_STATUS_INVALID_STATE, in which case the application must - * defer calibration until after the protocol switch is complete. Silicon Labs - * recommends calling this function from the application main loop. - * - * @note Instead of this function, consider using the individual chip-specific - * functions. Using the individual functions will allow for better - * dead-stripping if not all calibrations are run. - * @note Some calibrations should only be executed when the radio is IDLE. See - * chip-specific documentation for more details. - */ -RAIL_Status_t RAIL_Calibrate(RAIL_Handle_t railHandle, - RAIL_CalValues_t *calValues, - RAIL_CalMask_t calForce); - -/** - * Return the current set of pending calibrations. - * - * @param[in] railHandle A RAIL instance handle. - * @return A mask of all pending calibrations that the user has been asked to - * perform. - * - * This function returns a full set of pending calibrations. The only way - * to clear pending calibrations is to perform them using the \ref - * RAIL_Calibrate() API with the appropriate list of calibrations. - */ -RAIL_CalMask_t RAIL_GetPendingCal(RAIL_Handle_t railHandle); - -/** - * Apply a given image rejection calibration value. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] imageRejection The image rejection value to apply. - * @return A status code indicating success of the function call. - * - * Take an image rejection calibration value and apply it. This value should be - * determined from a previous run of \ref RAIL_CalibrateIr on the same - * physical device with the same radio configuration. The imageRejection value - * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. - * - * If multiple protocols are used, this function will return - * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is - * not active. In that case, the caller must attempt to re-call this function later. - * - * @deprecated Please use \ref RAIL_ApplyIrCalibrationAlt instead. - */ -RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle, - uint32_t imageRejection); - -/** - * Apply a given image rejection calibration value. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] imageRejection Pointer to the image rejection value to apply. - * @param[in] rfPath RF path to calibrate. - * @return A status code indicating success of the function call. - * - * Take an image rejection calibration value and apply it. This value should be - * determined from a previous run of \ref RAIL_CalibrateIrAlt on the same - * physical device with the same radio configuration. The imageRejection value - * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. - * @note: To make sure the imageRejection value is stored/configured correctly, - * \ref RAIL_ConfigAntenna should be called before calling this API. - * - * If multiple protocols are used, this function will return - * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is - * not active. In that case, the caller must attempt to re-call this function later. - */ -RAIL_Status_t RAIL_ApplyIrCalibrationAlt(RAIL_Handle_t railHandle, - RAIL_IrCalValues_t *imageRejection, - RAIL_AntennaSel_t rfPath); - -/** - * Run the image rejection calibration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. - * - * Run the image rejection calibration and apply the resulting value. If the - * imageRejection parameter is not NULL, store the value at that - * location. The imageRejection value will also be stored to the - * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running - * calibration that adds significant code space when run and can be run with a - * separate firmware image on each device to save code space in the - * final image. - * - * If multiple protocols are used, this function will make the given railHandle - * active, if not already, and perform calibration. If called during a protocol - * switch, it will return \ref RAIL_STATUS_INVALID_STATE. In this case, - * \ref RAIL_ApplyIrCalibration may be called to apply a previously determined - * IR calibration value, or the app must defer calibration until the - * protocol switch is complete. Silicon Labs recommends calling this function - * from the application main loop. - * - * @deprecated Please use \ref RAIL_CalibrateIrAlt instead. - */ -RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle, - uint32_t *imageRejection); - -/** - * Run the image rejection calibration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection Pointer to the image rejection result. - * @param[in] rfPath RF path to calibrate. - * @return A status code indicating success of the function call. - * - * Run the image rejection calibration and apply the resulting value. If the - * imageRejection parameter is not NULL, store the value at that - * location. The imageRejection value will also be stored to the - * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running - * calibration that adds significant code space when run and can be run with a - * separate firmware image on each device to save code space in the - * final image. - * @note: To make sure the imageRejection value is stored/configured correctly, - * \ref RAIL_ConfigAntenna should be called before calling this API. - * - * If multiple protocols are used, this function will return - * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is - * not active. In that case, the caller must attempt to re-call this function later. - */ -RAIL_Status_t RAIL_CalibrateIrAlt(RAIL_Handle_t railHandle, - RAIL_IrCalValues_t *imageRejection, - RAIL_AntennaSel_t rfPath); - -/** - * Run the temperature calibration. - * - * @param[in] railHandle A RAIL instance handle. - * @return A status code indicating success of the function call. - * - * Run the temperature calibration, which needs to recalibrate the synth if - * the temperature crosses 0C or the temperature delta since the last - * calibration exceeds 70C while in receive. RAIL will run the VCO calibration - * automatically upon entering receive or transmit states, so the application - * can omit this calibration if the stack re-enters receive or transmit with - * enough frequency to avoid reaching the temperature delta. If the application - * does not calibrate for temperature, it's possible to miss receive packets due - * to a drift in the carrier frequency. - * - * If multiple protocols are used, this function will return - * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is - * not active. In that case, the calibration will be automatically performed - * next time the radio enters receive. - */ -RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle); - -/** - * Performs HFXO compensation. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] crystalPPMError Current deviation that has been corrected, - * measured in PPM. May be NULL. - * @return A status code indicating the result of the function call. - * - * Compute the PPM correction using the thermistor value available when - * \ref RAIL_EVENT_THERMISTOR_DONE occurs, after - * \ref RAIL_StartThermistorMeasurement() call. - * Then correct the RF frequency as well as TX and RX sampling. - * - * This function calls the following RAIL functions in sequence saving having - * to call them individually: - * - \ref RAIL_ConvertThermistorImpedance() - * - \ref RAIL_ComputeHFXOPPMError() - * - \ref RAIL_CompensateHFXO() - * - * @note This function makes the radio idle. - */ -RAIL_Status_t RAIL_CalibrateHFXO(RAIL_Handle_t railHandle, int8_t *crystalPPMError); - -/** - * Enable/disable the PA calibration. - * - * @param[in] enable Enables/disables the PA calibration. - * - * Enabling will ensure that the PA power remains constant chip-to-chip. - * By default, this feature is disabled after reset. - * - * @note Call this function before \ref RAIL_ConfigTxPower() if this - * feature is desired. - */ -void RAIL_EnablePaCal(bool enable); - -/** @} */ // end of group Calibration - -/****************************************************************************** - * RF Sense Structures - *****************************************************************************/ -/** - * @addtogroup Rf_Sense RF Sense - * @{ - */ - -/** - * Start/stop the RF Sense functionality in Energy Detection Mode for use - * during low-energy sleep modes. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] band The frequency band(s) on which to sense the RF energy. - * To stop RF Sense, specify \ref RAIL_RFSENSE_OFF. - * @param[in] senseTime The time (in microseconds) the RF energy must be - * continually detected to be considered "sensed". - * @param[in] cb \ref RAIL_RfSense_CallbackPtr_t is called when the RF is - * sensed. Set null if polling via \ref RAIL_IsRfSensed(). - * @return The actual senseTime used, which may be different than - * requested due to limitations of the hardware. If 0, RF sense was - * disabled or could not be enabled (no callback will be issued). - * - * The EFR32 has the ability to sense the presence of RF Energy above -20 dBm - * within either or both the 2.4 GHz and Sub-GHz bands and trigger an event - * if that energy is continuously present for certain durations of time. - * - * @note After RF energy has been sensed, the RF Sense is automatically - * disabled and \ref RAIL_StartRfSense() must be called again to reactivate it. - * If RF energy has not been sensed and to manually disable RF Sense, - * \ref RAIL_StartRfSense() must be called with band specified as - * \ref RAIL_RFSENSE_OFF or with senseTime set to 0 microseconds. - * - * @note Packet reception is not guaranteed to work correctly once RF Sense is - * enabled, both in single protocol and multiprotocol RAIL. - * To be safe, an application should turn this on only after idling - * the radio to stop receive and turn it off before attempting to restart - * receive. Since EM4 sleep causes the chip to come up through the reset - * vector any wake from EM4 must also shut off RF Sense to ensure proper - * receive functionality. - * - * @warning For some chips, RF Sense functionality is only guaranteed within - * a specified temperature range. - * See chip-specific documentation for more details. - */ -RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, - RAIL_RfSenseBand_t band, - RAIL_Time_t senseTime, - RAIL_RfSense_CallbackPtr_t cb); - -/// Start/stop the RF Sense functionality in Selective(OOK Based) Mode for use -/// during low-energy sleep modes. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @param[in] config \ref RAIL_RfSenseSelectiveOokConfig_t holds the RFSENSE -/// configuration for Selective(OOK) mode. -/// @return Status code indicating success of the function call. -/// -/// Some chips support Selective RF energy detection (OOK mode) where the -/// user can program the chip to look for a particular sync word pattern -/// (1byte - 4bytes) sent using OOK and wake only when that is detected. -/// See chip-specific documentation for more details. -/// -/// The following code gives an example of how to use RF Sense functionality -/// in Selective(OOK Based) Mode. -/// @code{.c} -/// -/// // Syncword Length in bytes, 1-4 bytes. -/// #define NUMSYNCWORDBYTES (2U) -/// // Syncword Value. -/// #define SYNCWORD (0xB16FU) -/// -/// // Configure the transmitting node for sending the wakeup packet. -/// RAIL_Idle(railHandle, RAIL_IDLE_ABORT, true); -/// RAIL_ConfigRfSenseSelectiveOokWakeupPhy(railHandle); -/// RAIL_SetRfSenseSelectiveOokWakeupPayload(railHandle, NUMSYNCWORDBYTES, SYNCWORD); -/// RAIL_StartTx(railHandle, channel, RAIL_TX_OPTIONS_DEFAULT, NULL); -/// -/// // Configure the receiving node (EFR32XG22) for RF Sense. -/// RAIL_RfSenseSelectiveOokConfig_t config = { -/// .band = rfBand, -/// .syncWordNumBytes = NUMSYNCWORDBYTES, -/// .syncWord = SYNCWORD, -/// .cb = &RAILCb_SensedRf -/// }; -/// RAIL_StartSelectiveOokRfSense(railHandle, &config); -/// -/// @endcode -/// -/// @note After RF energy has been sensed, the RF Sense is automatically -/// disabled and \ref RAIL_StartSelectiveOokRfSense() must be called again to -/// reactivate. If RF energy has not been sensed and to manually disable -/// RF Sense, \ref RAIL_StartSelectiveOokRfSense() must be called with band -/// specified as \ref RAIL_RFSENSE_OFF or with -/// \ref RAIL_RfSenseSelectiveOokConfig_t as NULL. -/// -/// @note Packet reception is not guaranteed to work correctly once RF Sense is -/// enabled, both in single protocol and multiprotocol RAIL. -/// To be safe, an application should turn this on only after idling -/// the radio to stop receive and turn it off before attempting to restart -/// receive. Since EM4 sleep causes the chip to come up through the reset -/// vector any wake from EM4 must also shut off RF Sense to ensure proper -/// receive functionality. -/// -RAIL_Status_t RAIL_StartSelectiveOokRfSense(RAIL_Handle_t railHandle, - RAIL_RfSenseSelectiveOokConfig_t *config); - -/** - * Switch to RF Sense Selective(OOK) PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * This function switches to the RFSENSE Selective(OOK) PHY for transmitting a - * packet to wake up a chip that supports Selective RF energy detection (OOK - * mode). You may only call this function while the radio is idle. While the - * radio is configured for this PHY, receive functionality should not be used. - * - * @note The user must also set up the transmit FIFO, via - * \ref RAIL_SetRfSenseSelectiveOokWakeupPayload, post this function call to - * include the first byte as the Preamble Byte, followed by the - * Syncword (1byte - 4bytes). - * See chip-specific documentation for more details. - */ -RAIL_Status_t RAIL_ConfigRfSenseSelectiveOokWakeupPhy(RAIL_Handle_t railHandle); - -/** - * Set the transmit payload for waking up a node configured for - * RF Sense Selective(OOK). - * - * @param[in] railHandle A handle for RAIL instance. - * @param[in] numSyncwordBytes Syncword Length in bytes, 1-4 bytes. - * @param[in] syncword Syncword Value. - * @return A status code indicating success of the function call. - * - * @note You must call this function after the chip has been set up with the - * RF Sense Selective(OOK) PHY, using \ref RAIL_ConfigRfSenseSelectiveOokWakeupPhy. - * - */ -RAIL_Status_t RAIL_SetRfSenseSelectiveOokWakeupPayload(RAIL_Handle_t railHandle, - uint8_t numSyncwordBytes, - uint32_t syncword); - -/** - * Check whether the RF was sensed. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense. - * False otherwise. - * - * This function is useful if \ref RAIL_StartRfSense is called with a null - * callback. It is generally used after EM4 reboot but can be used any time. - */ -bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); - -/** @} */ // end of group Rf_Sense - -/****************************************************************************** - * RX Channel Hopping - *****************************************************************************/ -/** - * @addtogroup Rx_Channel_Hopping RX Channel Hopping - * @brief Hardware accelerated hopping between channels while waiting for a - * packet in receive. - * @{ - * - * Channel hopping provides a hardware accelerated method for - * scanning across multiple channels quickly, as part of a receive protocol. - * While it is possible to call \ref RAIL_StartRx on different channels, - * back to back, and listen on many channels sequentially in that way, the - * time it takes to switch channels with that method may be too long for some - * protocols. This API pre-computes necessary channel change operations - * for a given list of channels, so that the radio can move from channel - * to channel much faster. Additionally, it leads to more succinct code - * as channel changes will be done implicitly, without requiring numerous calls - * to \ref RAIL_StartRx. Currently, while this feature is enabled, the radio - * will hop channels in the given sequence each time it enters RX. - * Note that RX Channel hopping and EFR32xG25's concurrent mode / collision - * detection are mutually exclusive. - * - * The channel hopping buffer requires RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL - * number of 32-bit words of overhead per channel, plus 3 words overall plus the - * twice the size of the radioConfigDeltaSubtract of the whole radio configuration, - * plus the twice the sum of the sizes of all the radioConfigDeltaAdds of - * all the channel hopping channels. - * - * The following code gives an example of how to use - * the RX Channel Hopping API. - * @code{.c} - * - - * #define CHANNEL_HOPPING_NUMBER_OF_CHANNELS 4 - * #define CHANNEL_HOPPING_BUFFER_SIZE do { \ - * 3 + \ - * (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ - * * CHANNEL_HOPPING_NUMBER_OF_CHANNELS) + \ - * 2 * (SIZEOF_UINT32_DELTA_SUBTRACT + \ - * SIZEOF_UINT32_DELTA_ADD_0 + \ - * SIZEOF_UINT32_DELTA_ADD_1 + \ - * SIZEOF_UINT32_DELTA_ADD_2 + \ - * SIZEOF_UINT32_DELTA_ADD_3) \ - * } while (0) - * - * RAIL_RxChannelHoppingConfigEntry_t channelHoppingEntries[CHANNEL_HOPPING_NUMBER_OF_CHANNELS]; - * uint32_t channelHoppingBuffer[CHANNEL_HOPPING_BUFFER_SIZE]; - * - * RAIL_RxChannelHoppingConfig_t channelHoppingConfig = { - * .buffer = channelHoppingBuffer, - * .bufferLength = CHANNEL_HOPPING_BUFFER_SIZE, - * .numberOfChannels = CHANNEL_HOPPING_NUMBER_OF_CHANNELS, - * .entries = channelHoppingEntries - * }; - * - * channelHoppingEntries[0].channel = 1; - * channelHoppingEntries[1].channel = 2; - * channelHoppingEntries[2].channel = 3; - * - * RAIL_ConfigRxChannelHopping(railHandle, &channelHoppingConfig); - * RAIL_EnableRxChannelHopping(railHandle, true, true) - * @endcode - */ - -/** - * Configure RX channel hopping. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config Configuration parameters for RX Channel Hopping. - * @return Status code indicating success of the function call. - * - * Configure channel hopping channels, conditions, and parameters. This - * API must be called before \ref RAIL_EnableRxChannelHopping(). This API must - * never be called while the radio is on with RX Duty Cycle or Channel - * Hopping enabled. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or - * the runtime call \ref RAIL_SupportsChannelHopping() to check whether - * the platform supports this feature. - * - * @note Calling this function will overwrite any settings configured with - * \ref RAIL_ConfigRxDutyCycle. - */ -RAIL_Status_t RAIL_ConfigRxChannelHopping(RAIL_Handle_t railHandle, - RAIL_RxChannelHoppingConfig_t *config); - -/** - * Enable RX channel hopping. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Enable (true) or disable (false) RX Channel Hopping. - * @param[in] reset Start from the first channel of the channel hopping - * sequence (true) or from wherever hopping left off last time the code - * left RX. - * @return Status code indicating success of the function call. - * - * Enable or disable Channel Hopping. Additionally, specify whether hopping - * should be reset to start from the channel at index zero, or continue - * from the channel last hopped to. The radio should not be on when - * this API is called. \ref RAIL_ConfigRxChannelHopping must be called - * successfully before this API is called. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or - * the runtime call \ref RAIL_SupportsChannelHopping() to check whether - * the platform supports this feature. - * - * @note RX Channel Hopping may not be enabled while auto-ACKing is enabled. - * - * @note Calling this function will overwrite any settings configured with - * \ref RAIL_EnableRxDutyCycle. - */ -RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, - bool enable, - bool reset); -/** - * Get RSSI of one channel in the channel hopping sequence, during - * channel hopping. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channelIndex Index in the channel hopping sequence of the - * channel of interest - * @return Latest RSSI for the channel at the specified index. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or - * the runtime call \ref RAIL_SupportsChannelHopping() to check whether - * the platform supports this feature. - * - * @note In multiprotocol, this function returns \ref RAIL_RSSI_INVALID - * immediately if railHandle is not the current active \ref RAIL_Handle_t. - * - * @note \ref RAIL_ConfigRxChannelHopping must be called successfully - * before this API is called. - * - * @note When the Z-Wave protocol is active, it is expected that after - * \ref RAIL_ConfigRxChannelHopping is called successfully on EFR32XG1 - * family of chips, running \ref RAIL_GetChannelHoppingRssi() on a 40kbps - * PHY will not work well. Plan to use the 9.6kbps PHY for estimating - * channel noise instead. On EFR32XG2 family of chips, running - * \ref RAIL_GetChannelHoppingRssi() on the 9.6kbps PHY returns the RSSI - * measurement of the 40kpbs PHY. This is because the 9.6kbps PHY has - * trouble with RSSI measurements on EFR32XG2 family of chips. - */ -int16_t RAIL_GetChannelHoppingRssi(RAIL_Handle_t railHandle, - uint8_t channelIndex); - -/// Configure RX duty cycle mode. -/// -/// @param[in] railHandle A RAIL instance handle. -/// @param[in] config Configuration structure to specify duty cycle parameters. -/// @return Status code indicating success of the function call. -/// -/// Configure RX duty cycle mode. With this mode enabled, every time the radio -/// enters RX, it will duty cycle on and off to save power. The duty cycle -/// ratio can be altered dynamically and intelligently by the hardware by -/// staying on longer if a preamble or other packet segments are detected in -/// the air. This API must never be called while the radio is on with RX Duty -/// Cycle or Channel Hopping enabled. -/// For short delays (in the order of microseconds), -/// \ref RAIL_RxDutyCycleConfig_t::delay, this can be used to save receive -/// current while having little impact on the radio performance, for protocols -/// with long preambles. For long delays (in the order of milliseconds or higher) -/// the chip can be put into EM2 energy mode before re-entering RX, -/// to save extra power, with some application hooks as shown below. -/// -/// @code{.c} -/// #include -/// #include -/// -/// extern RAIL_Handle_t railHandle; -/// RAIL_Time_t periodicWakeupUs; -/// -/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { -/// // Omitting other event handlers -/// if (events & RAIL_EVENT_RX_DUTY_CYCLE_RX_END) { -/// // Schedule the next receive. -/// RAIL_ScheduleRxConfig_t rxCfg = { -/// .start = periodicWakeupUs, -/// .startMode = RAIL_TIME_DELAY, -/// .end = 0U, -/// .endMode = RAIL_TIME_DISABLED, -/// .rxTransitionEndSchedule = 0U, -/// .hardWindowEnd = 0U -/// }; -/// -/// RAIL_Idle(railHandle, RAIL_IDLE_ABORT, true); -/// RAIL_ScheduleRx(railHandle, channel, &rxCfg, NULL); -/// } -/// } -/// -/// void main(void) { -/// RAIL_Status_t status; -/// bool shouldSleep = false; -/// -/// // This function depends on your board/chip but it must enable the LFCLK -/// // you intend to use for RTCC sync before we configure sleep as that -/// // function will attempt to auto detect the clock. -/// BoardSetupLFCLK(); -/// // Initialize Power Manager module -/// sl_power_manager_init(); -/// // Initialize RAIL Power Manager -/// RAIL_InitPowerManager(); -/// -/// // Configure sleep for timer synchronization -/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); -/// assert(status == RAIL_STATUS_NO_ERROR); -/// -/// // Application main loop -/// while(1) { -/// // ... do normal app stuff and set shouldSleep when we want to sleep -/// if (shouldSleep) { -/// // Let the CPU go to sleep if the system allows it. -/// sl_power_manager_sleep(); -/// } -/// } -/// } -/// @endcode -/// -/// @note This feature/API is not supported on the EFR32XG1 family of chips. -/// Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or -/// the runtime call \ref RAIL_SupportsChannelHopping() to check whether -/// the platform supports this feature. -/// -/// @note Calling this function will overwrite any settings configured with -/// \ref RAIL_ConfigRxChannelHopping. -RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, - const RAIL_RxDutyCycleConfig_t *config); - -/** - * Enable RX duty cycle mode. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Enable (true) or disable (false) RX Duty Cycling. - * @return Status code indicating success of the function call. - * - * Enable or disable RX duty cycle mode. After this is called, the radio - * will begin duty cycling each time it enters RX, based on the - * configuration passed to \ref RAIL_ConfigRxDutyCycle. This API must not - * be called while the radio is on. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or - * the runtime call \ref RAIL_SupportsChannelHopping() to check whether - * the platform supports this feature. - * - * @note Calling this function will overwrite any settings configured with - * \ref RAIL_EnableRxChannelHopping. - */ -RAIL_Status_t RAIL_EnableRxDutyCycle(RAIL_Handle_t railHandle, - bool enable); - -/** - * Get the default RX duty cycle configuration. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] config An application-provided non-NULL pointer to store - * the default RX duty cycle configuration. - * @return Status code indicating success of the function call. - * Note that RAIL_STATUS_INVALID_PARAMETER will be returned if the current - * channel's radio configuration does not support the requested information. - * - * To save power during RX, an application may want to go to low power as long as - * possible by periodically waking up and trying to - * "sense" if there are any incoming packets. This API returns the recommended - * RX duty cycle configuration, so the application can enter low power mode - * periodically without missing packets. To wake up - * earlier, the application can reduce the delay parameter. - * Note that these value might be different if any configuration / channel has - * changed. - **/ -RAIL_Status_t RAIL_GetDefaultRxDutyCycleConfig(RAIL_Handle_t railHandle, - RAIL_RxDutyCycleConfig_t *config); - -/** @} */ // end of group Rx_Channel_Hopping - -/****************************************************************************** - * Multiprotocol-Specific Functions - *****************************************************************************/ -/** - * @addtogroup Multiprotocol - * @brief Multiprotocol scheduler APIs to support multiple time-sliced PHYs. - * @{ - */ - -/** - * Yield the radio to other configurations. - * - * @param[in] railHandle A RAIL instance handle. - * - * This function is used to indicate that the previous transmit or scheduled - * receive operation has completed. It must be used in multiprotocol RAIL because - * the scheduler assumes that any transmit or receive operation that is started - * can go on indefinitely based on state transitions and your protocol. - * RAIL will not allow a lower priority tasks to run until this is called so it - * can negatively impact performance of those protocols if this is omitted or - * delayed. It is also possible to call the \ref RAIL_Idle() API to - * both terminate the operation and idle the radio. In single protocol RAIL - * this API does nothing, however, if RAIL Power Manager is initialized, - * calling \ref RAIL_YieldRadio after scheduled TX/RX and instantaneous TX - * completion, is required, to indicate to the Power Manager that the the radio - * is no longer busy and can be idled for sleeping. - * - * See \ref rail_radio_scheduler_yield for more details. - */ -void RAIL_YieldRadio(RAIL_Handle_t railHandle); - -/** - * Get the status of the RAIL scheduler. - * - * @param[in] railHandle A RAIL instance handle. - * @return \ref RAIL_SchedulerStatus_t status. - * - * This function can only be called from a callback context after the - * \ref RAIL_EVENT_SCHEDULER_STATUS event occurs. - */ -RAIL_SchedulerStatus_t RAIL_GetSchedulerStatus(RAIL_Handle_t railHandle); - -/** - * Get the status of the RAIL scheduler, specific to the radio operation, - * along with \ref RAIL_Status_t returned by RAIL API invoked by the - * RAIL scheduler. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] pSchedulerStatus An application-provided pointer to store - * \ref RAIL_SchedulerStatus_t status. Can be NULL as long as - * \ref RAIL_Status_t pointer is not NULL. - * @param[out] pRailStatus An application-provided pointer to store - * \ref RAIL_Status_t of the RAIL API invoked by the RAIL scheduler. - * Can be NULL as long as \ref RAIL_SchedulerStatus_t pointer is not NULL. - * @return \ref RAIL_Status_t indicating success of the function call. - * - * This function can only be called from a callback context after the - * \ref RAIL_EVENT_SCHEDULER_STATUS event occurs. - */ -RAIL_Status_t RAIL_GetSchedulerStatusAlt(RAIL_Handle_t railHandle, - RAIL_SchedulerStatus_t *pSchedulerStatus, - RAIL_Status_t *pRailStatus); - -/** - * Change the priority of a specified task type in multiprotocol. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] priority Desired new priority for the railHandle's active task - * @param[in] taskType Type of task whose priority should be updated - * @return \ref RAIL_Status_t indicating success of the function call. - * - * While the application can use this function however it likes, a major use - * case is being able to increase an infinite receive priority while receiving - * a packet. In other words, a given RAIL_Handle_t can maintain a very low - * priority background receive, but upon getting a - * \ref RAIL_EVENT_RX_SYNC1_DETECT_SHIFT or - * \ref RAIL_EVENT_RX_SYNC2_DETECT_SHIFT event, the app can call this function - * to increase the background RX priority to lower the risk another protocol - * might preempt during packet reception. - */ -RAIL_Status_t RAIL_SetTaskPriority(RAIL_Handle_t railHandle, - uint8_t priority, - RAIL_TaskType_t taskType); - -/** - * Get time needed to switch between protocols. - * - * @return \ref RAIL_Time_t Time needed to switch between protocols. - */ -RAIL_Time_t RAIL_GetTransitionTime(void); - -/** - * Set time needed to switch between protocols. Call this API - * only once, before any protocol is initialized via - * \ref RAIL_Init(). Changing this value during normal operation - * can result in improper scheduling behavior. - * - * @param[in] transitionTime Time needed to switch between protocols. - */ -void RAIL_SetTransitionTime(RAIL_Time_t transitionTime); - -/** @} */ // end of group Multiprotocol - -/****************************************************************************** - * Diagnostic - *****************************************************************************/ -/** - * @addtogroup Diagnostic - * @brief APIs for diagnostic and test chip modes - * @{ - */ - -/** - * Configure direct mode for RAIL. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] directModeConfig Configuration structure to specify direct mode - * parameters. Default configuration will be used if NULL is passed. - * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. - * - * This API configures direct mode and should be called before - * calling \ref RAIL_EnableDirectMode(). If this function is not called, the - * following default configuration will be used: \n - * \b EFR32xG1x \n - * Sync Rx : false \n - * Sync Tx : false \n - * TX data in (DIN) : EFR32_PC10 \n - * RX data out (DOUT) : EFR32_PC11 \n - * TX/RX clk out (DCLK) : EFR32_PC9 \n - * \b EFR32xG2x: \n - * Sync Rx : false \n - * Sync Tx : false \n - * TX data in (DIN) : EFR32_PA7 \n - * RX data out (DOUT) : EFR32_PA5 \n - * TX/RX clk out (DCLK) : EFR32_PA6 - * - * @warning This API is not safe to use in a multiprotocol app. - */ -RAIL_Status_t RAIL_ConfigDirectMode(RAIL_Handle_t railHandle, - const RAIL_DirectModeConfig_t *directModeConfig); - -/** - * Enable or disable direct mode for RAIL. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Whether or not to enable direct mode for TX and RX. - * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. - * * - * See \ref RAIL_EnableDirectModeAlt() for more detailed function - * description. - * - * @warning New applications should consider using RAIL_EnableDirectModeAlt() for - * this functionality. - * - * @note This feature is only available on certain devices. - * \ref RAIL_SupportsDirectMode() can be used to check if a particular - * device supports this feature or not. - * - * @warning This API is not safe to use in a true multiprotocol app. - */ -RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, - bool enable); - -/** - * Enable or disable direct mode for RAIL. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enableDirectTx Enable direct mode for data being transmitted out - * of the radio. - * @param[in] enableDirectRx Enable direct mode for data being received from the - * radio. - * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. - * - * This API enables or disables the modem and GPIOs for direct mode operation. - * see \ref RAIL_ConfigDirectMode for information on selecting the - * correct hardware configuration. If direct mode is enabled, - * packets are output and input directly to the radio via GPIO - * and RAIL packet handling is ignored. - * - * @note This feature is only available on certain chips. - * \ref RAIL_SupportsDirectMode() can be used to check if a particular - * chip supports this feature or not. - * - * @warning this API is not safe to use in a true multiprotocol app. - */ -RAIL_Status_t RAIL_EnableDirectModeAlt(RAIL_Handle_t railHandle, - bool enableDirectTx, - bool enableDirectRx); - -/** - * Get the radio subsystem clock frequency in Hz. - * - * @param[in] railHandle A RAIL instance handle. - * @return Radio subsystem clock frequency in Hz. - */ -uint32_t RAIL_GetRadioClockFreqHz(RAIL_Handle_t railHandle); - -/** - * Set the crystal tuning. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] tune A chip-dependent crystal capacitor bank tuning parameter. - * @return Status code indicating success of the function call. - * - * Tunes the crystal that the radio depends on to change the location of the - * center frequency for transmitting and receiving. This function will only - * succeed if the radio is idle at the time of the call. - * - * @note This function proportionally affects the entire chip's timing - * across all its peripherals, including radio tuning and channel spacing. - * It is recommended to call this function only when HFXO is not being used, - * as it can cause disturbance on the HFXO frequency. - * A separate function, \ref RAIL_SetFreqOffset(), can be used to adjust - * just the radio tuner without disturbing channel spacing or other chip - * peripheral timing. - * @note On EFR32xG2 series devices, this API sets CTUNEXIANA and internally - * CTUNEXOANA = CTUNEXIANA + delta where delta is set or changed by - * \ref RAIL_SetTuneDelta. The default delta may not be 0 on some devices. - */ -RAIL_Status_t RAIL_SetTune(RAIL_Handle_t railHandle, uint32_t tune); - -/** - * Get the crystal tuning. - * - * @param[in] railHandle A RAIL instance handle. - * @return A chip-dependent crystal capacitor bank tuning parameter. - * - * Retrieves the current tuning value used by the crystal that the radio - * depends on. - * @note On EFR32xG2 series devices, this is the CTUNEXIANA value. - */ -uint32_t RAIL_GetTune(RAIL_Handle_t railHandle); - -/** - * Set the crystal tuning delta. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] delta A chip-dependent crystal capacitor bank tuning delta. - * @return Status code indicating success of the function call. - * - * Set the CTUNEXOANA delta for \ref RAIL_SetTune to use on EFR32xG2 series devices: - * CTUNEXOANA = CTUNEXIANA + delta. This function does not change CTUNE values; - * call \ref RAIL_SetTune to put a new delta into effect. - * - */ -RAIL_Status_t RAIL_SetTuneDelta(RAIL_Handle_t railHandle, int32_t delta); - -/** - * Get the crystal tuning delta on EFR32xG2 series devices. - * - * @param[in] railHandle A RAIL instance handle. - * @return A chip-dependent crystal capacitor bank tuning delta. - * - * Retrieves the current tuning delta used by \ref RAIL_SetTune. - * @note The default delta if \ref RAIL_SetTuneDelta has never been called - * is device-dependent and may not be 0. - */ -int32_t RAIL_GetTuneDelta(RAIL_Handle_t railHandle); - -/** - * Get the frequency offset. - * - * @param[in] railHandle A RAIL instance handle. - * @return Returns the measured frequency offset on a received packet. - * The units are described in the \ref RAIL_FrequencyOffset_t - * documentation. If this returns \ref RAIL_FREQUENCY_OFFSET_INVALID, - * it was called while the radio wasn't active and there is no way - * to get the frequency offset. - * - * Retrieves the measured frequency offset used during the previous - * received packet, which includes the current radio frequency offset - * (see \ref RAIL_SetFreqOffset()). If the chip has not been in RX, - * it returns the nominal radio frequency offset. - * - * @note Changing to any non-idle radio state after reception can cause this - * value to be overwritten so it is safest to capture during packet reception. - */ -RAIL_FrequencyOffset_t RAIL_GetRxFreqOffset(RAIL_Handle_t railHandle); - -/** - * Set the nominal radio frequency offset. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] freqOffset \ref RAIL_FrequencyOffset_t parameter (signed, 2's - * complement). - * @return Status code indicating success of the function call. - * - * This function is used to adjust the radio's tuning frequency slightly up or down. - * It might be used in conjunction with \ref RAIL_GetRxFreqOffset() after - * receiving a packet from a peer to adjust the tuner to better match the - * peer's tuned frequency. - * - * @note Unlike \ref RAIL_SetTune(), which affects the entire chip's - * timing including radio tuning and channel spacing, this function - * only affects radio tuning without disturbing channel spacing or - * other chip peripheral timing. - */ -RAIL_Status_t RAIL_SetFreqOffset(RAIL_Handle_t railHandle, - RAIL_FrequencyOffset_t freqOffset); - -/** - * Start transmitting a stream on a certain channel. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel A channel on which to emit a stream. - * @param[in] mode Choose the stream mode (PN9, and so on). - * @return Status code indicating success of the function call. - * - * Begins streaming onto the given channel. The sources can either be an - * unmodulated carrier wave or an encoded stream of bits from a PN9 source. - * All ongoing radio operations will be stopped before transmission begins. - */ -RAIL_Status_t RAIL_StartTxStream(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_StreamMode_t mode); - -/** - * Start transmitting a stream on a certain channel with the ability to select - * an antenna. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] channel A channel on which to emit a stream. - * @param[in] mode Choose the stream mode (PN9, and so on). - * @param[in] options Choose the TX Antenna option. - * Takes only \ref RAIL_TX_OPTION_ANTENNA0, \ref RAIL_TX_OPTION_ANTENNA1, - * \ref RAIL_TX_OPTIONS_DEFAULT or \ref RAIL_TX_OPTIONS_NONE from the - * \ref RAIL_TxOptions_t. If some other value is used then, transmission - * is possible on any antenna. - * @return Status code indicating success of the function call. - * - * Begins streaming onto the given channel. The sources can either be an - * unmodulated carrier wave or an encoded stream of bits from a PN9 source. - * All ongoing radio operations will be stopped before transmission begins. - */ -RAIL_Status_t RAIL_StartTxStreamAlt(RAIL_Handle_t railHandle, - uint16_t channel, - RAIL_StreamMode_t mode, - RAIL_TxOptions_t options); - -/** - * Stop stream transmission. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. - * - * Halts the transmission started by RAIL_StartTxStream(). - */ -RAIL_Status_t RAIL_StopTxStream(RAIL_Handle_t railHandle); - -/** - * Stop infinite preamble transmission started and start transmitting the rest - * of the packet. - * - * This function is only useful for radio configurations that specify an - * infinite preamble. Call this API only after \ref RAIL_EVENT_TX_STARTED - * has occurred and the radio is transmitting. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call: - * \ref RAIL_STATUS_NO_ERROR if infinite preamble was stopped; - * \ref RAIL_STATUS_INVALID_CALL if the radio isn't configured for infinite - * preamble; - * \ref RAIL_STATUS_INVALID_STATE if the radio isn't transmitting. - */ -RAIL_Status_t RAIL_StopInfinitePreambleTx(RAIL_Handle_t railHandle); - -/** - * Configure the verification of radio memory contents. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] configVerify A configuration structure made available to - * RAIL to perform radio state verification. This structure must be - * allocated in application global read-write memory. RAIL may modify - * fields within or referenced by this structure during its operation. - * @param[in] radioConfig A pointer to a radioConfig that is to be used as a - * white list for verifying memory contents. - * @param[in] cb A callback that notifies the application of a mismatch in - * expected vs actual memory contents. A NULL parameter may be passed in - * if a callback is not provided by the application. - * @return \ref RAIL_STATUS_NO_ERROR if setup of the verification feature - * successfully occurred. - * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided railHandle - * or configVerify structures are invalid. - */ -RAIL_Status_t RAIL_ConfigVerification(RAIL_Handle_t railHandle, - RAIL_VerifyConfig_t *configVerify, - RAIL_RadioConfig_t radioConfig, - RAIL_VerifyCallbackPtr_t cb); - -/** - * Verify radio memory contents. - * - * @param[in,out] configVerify A configuration structure made available to - * RAIL to perform radio state verification. This structure must be - * allocated in application global read-write memory. RAIL may modify - * fields within or referenced by this structure during its operation. - * @param[in] durationUs The duration (in microseconds) for how long memory - * verification should occur before returning to the application. A value of - * RAIL_VERIFY_DURATION_MAX indicates that all memory contents should be - * verified before returning to the application. - * @param[in] restart This flag only has meaning if a previous call of this - * function returned \ref RAIL_STATUS_SUSPENDED. By restarting (true), the - * verification process starts over from the beginning, or by resuming - * where verification left off after being suspended (false), verification - * can proceed towards completion. - * @return \ref RAIL_STATUS_NO_ERROR if the contents of all applicable - * memory locations have been verified. - * \ref RAIL_STATUS_SUSPENDED is returned if the provided test duration - * expired but the time was not sufficient to verify all memory contents. - * By calling \ref RAIL_Verify again, further verification will commence. - * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided - * verifyConfig structure pointer is not configured for use by the active - * RAIL handle. - * \ref RAIL_STATUS_INVALID_STATE is returned if any of the verified - * memory contents are different from their reference values. - */ -RAIL_Status_t RAIL_Verify(RAIL_VerifyConfig_t *configVerify, - uint32_t durationUs, - bool restart); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/** - * A global pointer to the memory address of the internal RAIL hardware timer - * that drives the RAIL timebase. - * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. The ticks wrap after - * about 17 minutes since it does not use the full 32-bit range. - * For more details, check the documentation for \ref RAIL_TimerTick_t. - */ -extern const volatile RAIL_TimerTick_t *RAIL_TimerTick; - -/** - * A global pointer to the memory address of the internal RAIL hardware timer - * that captures the latest RX packet reception time. This would not include - * the RX chain delay, so may not be equal to the packet timestamp, passed to - * the application, representing the actual on-air time the packet finished. - * - * @note The corresponding timer tick value is not adjusted for overflow or the - * clock period, and will simply be a register read. The ticks wrap after - * about 17 minutes since it does not use the full 32-bit range. - * For more details, check the documentation for \ref RAIL_TimerTick_t. - */ -extern const volatile RAIL_TimerTick_t *RAIL_RxPacketTimestamp; - -/** - * Get elapsed time, in microseconds, between two \ref RAIL_TimerTick_t ticks. - * - * @param[in] startTick Tick recorded at the start of the operation. - * @param[in] endTick Tick recorded at the end of the operation. - * - * @return Returns the elapsed time, in microseconds, between two timer ticks. - */ -RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, - RAIL_TimerTick_t endTick); - -/** - * Get \ref RAIL_TimerTick_t tick corresponding to the \ref RAIL_Time_t time. - * - * @param[in] microseconds Time in microseconds. - * - * @return Returns the \ref RAIL_TimerTick_t tick corresponding to the - * \ref RAIL_Time_t time. - */ -RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); - -/** - * Enable radio state change interrupt. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Enable/disable Radio state change interrupt. - * @return Status code indicating success of the function call. Returns - * \ref RAIL_STATUS_NO_ERROR once the interrupt has been enabled or disabled. - * - * @note If enabled, state change events are reported through the separate - * RAILCb_RadioStateChanged() callback. - */ -RAIL_Status_t RAIL_EnableRadioStateChanged(RAIL_Handle_t railHandle, - bool enable); - -/** - * Get the current radio state. - * - * @param[in] railHandle A RAIL instance handle. - * @return An enumeration, \ref RAIL_RadioStateEfr32_t, for the current radio - * state. - * - */ -RAIL_RadioStateEfr32_t RAIL_GetRadioStateAlt(RAIL_Handle_t railHandle); - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group Diagnostic - -/****************************************************************************** - * Energy Friendly Front End Module (EFF) - *****************************************************************************/ -/** - * @addtogroup EFF Energy Friendly Front End Module (EFF) - * @brief APIs for configuring and controlling an attached Energy Friendly Front - * End Module (EFF). - * - * The EFF is a high-performance, transmit/receive (T/R) front end module (FEM) - * for sub-GHz EFR32 devices. RAIL includes built-in functionality to transmit - * and receive via an attached EFF. This functionality optimizes RF performance - * while ensuring that the EFF stays within safe operating temperature limits. - * - * Configuration and control of the EFF is performed by the \ref rail_util_eff. - * - * @note The EFF is only supported with EFR32XG25 devices. - * @{ - */ - -/** Minimum power for CLPC usage in deci-dBm. Below this power CLPC will not activate. - * Recommend staying above 19 dBm for best performance. Signed unit, do not add U. */ -#define RAIL_CLPC_MINIMUM_POWER 180 - -/** - * Configure the attached EFF device. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @param[in] config A pointer to a \ref RAIL_EffConfig_t struct that contains - * configuration data for the EFF. - * @return Status code indicating success of the function call. - */ - -RAIL_Status_t RAIL_ConfigEff(RAIL_Handle_t genericRailHandle, - const RAIL_EffConfig_t *config); - -/** Number of temperature values provided for the EFF thermal protection */ -#define RAIL_EFF_TEMP_MEASURE_COUNT (6U) -/** Number of deprecated temperature values in EFF thermal protection */ -#define RAIL_EFF_TEMP_MEASURE_DEPRECATED_COUNT (2U) -/** Number of temperature values provided for HFXO metrics */ -#define RAIL_HFXO_TEMP_MEASURE_COUNT (1U) - -/** Total number of temperature values provided by \ref RAIL_GetTemperature(). */ -#define RAIL_TEMP_MEASURE_COUNT (RAIL_CHIP_TEMP_MEASURE_COUNT \ - + RAIL_EFF_TEMP_MEASURE_COUNT \ - + RAIL_EFF_TEMP_MEASURE_DEPRECATED_COUNT \ - + RAIL_HFXO_TEMP_MEASURE_COUNT) - -/** - * Get the different temperature measurements in Kelvin done by sequencer or host. - * Values that are not populated yet or incorrect are set to 0. - * - * Temperatures, in Kelvin, are stored in tempBuffer such as: - * tempBuffer[0] is the chip temperature - * tempBuffer[1] is the minimal chip temperature - * tempBuffer[2] is the maximal chip temperature - * - * If \ref RAIL_SUPPORTS_EFF is defined - * tempBuffer[3] is the EFF temperature before Tx - * tempBuffer[4] is the EFF temperature after Tx - * tempBuffer[5] is the minimal EFF temperature value before Tx - * tempBuffer[6] is the minimal EFF temperature value after Tx - * tempBuffer[7] is the maximal EFF temperature value before Tx - * tempBuffer[8] is the maximal EFF temperature value after Tx - * tempBuffer[9] is not used - * tempBuffer[10] is not used - * - * If \ref RAIL_SUPPORTS_HFXO_COMPENSATION - * tempBuffer[11] is the HFXO temperature - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] tempBuffer The address of the array that will contain temperatures. - * tempBuffer array must be at least \ref RAIL_TEMP_MEASURE_COUNT int16_t. - * @param[in] reset Reset min, max and average temperature values. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetTemperature(RAIL_Handle_t railHandle, - int16_t tempBuffer[RAIL_TEMP_MEASURE_COUNT], - bool reset); - -/** Number of bytes provided by \ref RAIL_GetSetEffClpcControl(). */ -#define RAIL_EFF_CONTROL_SIZE (52U) - -/** - * Get the different EFF Control measurements. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] tempBuffer The address of the target array. - * tempBuffer array must be at least \ref RAIL_EFF_CONTROL_SIZE bytes. - * @param[in] reset Reset the EFF Control measurements. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcControl(RAIL_Handle_t railHandle, - uint16_t tempBuffer[RAIL_EFF_CONTROL_SIZE / sizeof(uint16_t)], - bool reset); - -/** - * Copy the current FEM_DATA pin values into newMode. If changeMode is true, - * update FEM_DATA pin values with newMode first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newMode A pointer to a uint8_t that will contain the FEM_DATA pin values - * @param[in] changeMode If true, use newMode to update FEM_DATA pin values - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcFemdata(RAIL_Handle_t railHandle, - uint8_t *newMode, - bool changeMode); - -/** - * Copy the current Rural to Urban trip voltage into newTrip. If changeTrip is true, - * update current Rural to Urban trip voltage with newTrip first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newTrip A pointer to a uint16_t that will contain the Rural to Urban trip voltage, in millivolts - * @param[in] changeTrip If true, use newTrip to update current Rural to Urban trip voltage - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffLnaRuralUrbanMv(RAIL_Handle_t railHandle, - uint16_t *newTrip, - bool changeTrip); - -/** - * Copy the current Urban to Bypass trip voltage into newTrip. If changeTrip is true, - * update current Urban to Bypass trip voltage with newTrip first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newTrip A pointer to a uint16_t that will contain the Urban to Bypass trip voltage, in millivolts - * @param[in] changeTrip If true, use newTrip to update current Urban to Bypass trip voltage - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffLnaUrbanBypassMv(RAIL_Handle_t railHandle, - uint16_t *newTrip, - bool changeTrip); - -/** - * Copy the current Urban dwell time into newDwellTime. If changeDwellTime is true, - * update current Urban dwell time with newDwellTime first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newDwellTime A pointer to a uint16_t that will contain the Urban dwell - * dwell time, in milliseconds - * @param[in] changeDwellTime If true, use newDwellTime to update current Urban dwell time - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffLnaUrbanDwellTimeMs(RAIL_Handle_t railHandle, - uint32_t *newDwellTime, - bool changeDwellTime); - -/** - * Copy the current Bypass dwell time into newDwellTime. If changeDwellTime is true, - * update current Bypass dwell time with newDwellTime first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newDwellTime A pointer to a uint16_t that will contain the Bypass dwell - * dwell time, in milliseconds - * @param[in] changeDwellTime If true, use newDwellTime to update current Bypass dwell time - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffLnaBypassDwellTimeMs(RAIL_Handle_t railHandle, - uint32_t *newDwellTime, - bool changeDwellTime); - -/** - * If changeValues is true, update current CLPC Fast Loop calibration - * values using the new variables. If false, copy the current CLPC - * Fast Loop calibration values into new variables. - * - * @param[in] railHandle A RAIL instance handle - * @param[in] modeSensorIndex The mode sensor to use for this operation. - * @param[in,out] calibrationEntry The calibration entry to retrieve or update - * @param[in] changeValues If true, use new values to update the CLPC fast loop calibration - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcFastLoopCal(RAIL_Handle_t railHandle, - RAIL_EffModeSensor_t modeSensorIndex, - RAIL_EffCalConfig_t *calibrationEntry, - bool changeValues); - -/** - * If changeValues is true, update current CLPC Fast Loop calibration - * equations using the new variables. If false, copy the current CLPC - * Fast Loop calibration equations into new variables. - * - * @param[in] railHandle A RAIL instance handle - * @param[in] modeSensorIndex The mode sensor to use for this operation. - * @param[in,out] newSlope1e1MvPerDdbm A pointer to a uint16_t that will contain the CLPC Cal slope, in mV/ddBm * 10 - * @param[in,out] newoffset290Ddbm A pointer to a uint16_t that will contain the CLPC Cal offset from 29 dB - * @param[in] changeValues If true, use new values to update the CLPC fast loop calibration equations - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcFastLoopCalSlp(RAIL_Handle_t railHandle, - RAIL_EffModeSensor_t modeSensorIndex, - int16_t *newSlope1e1MvPerDdbm, - int16_t *newoffset290Ddbm, - bool changeValues); - -/** - * If changeValues is true, update current CLPC Fast Loop Target and - * Slope. If false, copy the current CLPC Fast Loop values into - * newTarget and newSlope. - * - * @param[in] railHandle A RAIL instance handle - * @param[in] modeSensorIndex The mode sensor to use for this operation. - * @param[in,out] newTargetMv A pointer to a uint16_t that will contain the CLPC Fast Loop Target in mV - * @param[in,out] newSlopeMvPerPaLevel A pointer to a uint16_t that will contain the CLPC Fast Loop Slope in mV/(PA power level) - * @param[in] changeValues If true, use newTargetMv and newSlopeMvPerPaLevel to update the CLPC Fast Loop values - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcFastLoop(RAIL_Handle_t railHandle, - RAIL_EffModeSensor_t modeSensorIndex, - uint16_t *newTargetMv, - uint16_t *newSlopeMvPerPaLevel, - bool changeValues); - -/** - * Copy the current CLPC Enable in to newClpcEnable. If changeClpcEnable is true, - * update current CLPC Enable with newClpcEnable first. - * - * @param[in] railHandle A RAIL instance handle - * @param[in,out] newClpcEnable A pointer to a uint8_t that will contain the CLPC Enable - * @param[in] changeClpcEnable If true, use newClpcEnable to update the current CLPC Enable - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetSetEffClpcEnable(RAIL_Handle_t railHandle, - uint8_t *newClpcEnable, - bool changeClpcEnable); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Get or set the EFF CLPC control flags for internal developer control. - * This interface may change at any time. - * - * @param[in] railHandle A RAIL instance handle - * @param[in] flags Pointer to the location of a single uint8_t containing flag values - * @param[in] change If true, use flags to update current EFF CLPC flags - * @return RAIL_Status_t indicating success or failure of the function - */ -RAIL_Status_t RAIL_GetSetEffClpcFlags(RAIL_Handle_t railHandle, - uint8_t *flags, - bool change); -#endif - -/** - * Get and set the EFF temperature threshold. - * - * The EFR32 device periodically takes temperature measurements of the attached - * EFF device. If the EFF temperature ever exceeds the EFF temperature - * threshold, any active transmit operation is aborted and future transmit - * operations are blocked until the EFF temperature falls below the threshold. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] newThresholdK A pointer to a uint16_t that will contain the - * current EFF temperature threshold, in Kelvin. - * @param[in] changeThreshold If true, use newThresholdK to update - * current EFF temperature threshold. - * @return Status code indicating the result of the function call. - */ -RAIL_Status_t RAIL_GetSetEffTempThreshold(RAIL_Handle_t railHandle, - uint16_t *newThresholdK, - bool changeThreshold); - -/** @} */ // end of group EFF - -/****************************************************************************** - * Thermal Protection - *****************************************************************************/ -/** - * @addtogroup Thermal_Protection Thermal Protection - * @{ - */ - -/** - * Enable or disable the thermal protection if \ref RAIL_SUPPORTS_THERMAL_PROTECTION - * is defined and update the temperature threshold and cool down hysteresis preventing or - * allowing transmissions. - * - * When the temperature threshold minus a precise number of degrees - * specified by the cool down hysteresis parameter is exceeded, - * any future transmits are blocked until the temperature decreases below that limit. - * Besides, if the temperature threshold is exceeded, any active transmit is aborted. - * - * By default the threshold is set to \ref RAIL_CHIP_TEMP_THRESHOLD_MAX and - * the cool down hysteresis is set to \ref RAIL_CHIP_TEMP_COOLDOWN_DEFAULT. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @param[in] chipTempConfig A pointer to the struct \ref RAIL_ChipTempConfig_t that contains - * the configuration to be applied. - * @return Status code indicating the result of the function call. - * Returns RAIL_STATUS_INVALID_PARAMETER if enable field from \ref RAIL_ChipTempConfig_t - * is set to false when an EFF is present on the board. - * - * @note The thermal protection is automatically enabled when an EFF is present - * on the board. There is no use in calling this API in this case. - */ -RAIL_Status_t RAIL_ConfigThermalProtection(RAIL_Handle_t genericRailHandle, - const RAIL_ChipTempConfig_t *chipTempConfig); - -/** - * Get the current thermal configuration parameter and status. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @param[in,out] chipTempConfig A pointer to the struct \ref RAIL_ChipTempConfig_t that will contain - * the current configuration. - * @return Status code indicating the result of the function call. - */ -RAIL_Status_t RAIL_GetThermalProtection(RAIL_Handle_t genericRailHandle, - RAIL_ChipTempConfig_t *chipTempConfig); - -/** @} */ // end of group Thermal_Protection - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/****************************************************************************** - * Debug - *****************************************************************************/ -/** - * @addtogroup Debug - * @brief APIs for debugging - * @{ - */ - -/** - * Configure the debug mode for the radio library. Do not use this function - * unless instructed by Silicon Labs. - * @param[in] railHandle A RAIL instance handle. - * @param[in] debugMode Debug mode to enter. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_SetDebugMode(RAIL_Handle_t railHandle, uint32_t debugMode); - -/** - * Return the debug mode for the radio library. Do not use this function - * unless instructed by Silicon Labs. - * @param[in] railHandle A RAIL instance handle. - * @return Debug mode for the radio library. - */ -uint32_t RAIL_GetDebugMode(RAIL_Handle_t railHandle); - -/** - * Override the radio base frequency. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] freq A desired frequency in Hz. - * @return Status code indicating success of the function call. - * - * Sets the radio to transmit at the frequency given. This function can only - * be used while in \ref RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency - * needs to be close to the base frequency of the current PHY. After this - * call, a full reset is needed to restore normal RAIL operation. - */ -RAIL_Status_t RAIL_OverrideDebugFrequency(RAIL_Handle_t railHandle, - uint32_t freq); - -/** - * Get the size of the radio's multiprotocol scheduler state buffer. - * - * @param[in] genericRailHandle A generic RAIL instance handle. - * @return Size, in bytes, of the radio's internal scheduler state buffer. - * Zero is returned if the handle is invalid or this is the singleprotocol - * library. - */ -uint32_t RAIL_GetSchedBufferSize(RAIL_Handle_t genericRailHandle); - -/** @} */ // end of group Debug - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/****************************************************************************** - * Assertion Callback - *****************************************************************************/ -/** - * @addtogroup Assertions - * @brief Callbacks called by assertions - * - * The assertion framework was implemented to not only - * assert that certain conditions are true in a block of code, but also - * to handle them more appropriately. In previous implementations, - * the behavior upon a failed assert was to hang in a while(1) loop. - * However, with the callback, each assert is given a unique error code so that - * they can be handled on a more case-by-case basis. For documentation on each - * of the errors, see the rail_assert_error_codes.h file. - * RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error. - * With asserts built into the library, users can choose how to handle each - * error inside the callback. - * - * @{ - */ - -/** - * Callback called upon failed assertion. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] errorCode Value passed in by the calling assertion API indicating - * the RAIL error that is indicated by the failing assertion. - */ -void RAILCb_AssertFailed(RAIL_Handle_t railHandle, - RAIL_AssertErrorCodes_t errorCode); - -/** @} */ // end of group Assertions - -/****************************************************************************** - * External_Thermistor - *****************************************************************************/ -/** - * @addtogroup External_Thermistor External Thermistor - * @brief APIs to measure temperature using an external thermistor - * - * This feature allows reading the temperature via an external thermistor on - * chips that support it. This will require connecting the necessary components - * and configuring the pins as required. - * - * @{ - */ - -/** - * Start a thermistor measurement. To get the thermistor impedance, call the - * function \ref RAIL_GetThermistorImpedance. On platforms having - * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR, this function reconfigures - * GPIO_THMSW_EN_PIN located in GPIO_THMSW_EN_PORT. - * To locate this pin, refer to the data sheet or appropriate header files - * of the device. For proper operation, \ref RAIL_Init must be called before - * using this function. - * - * @note This function is not designed for safe usage in multiprotocol - * applications. - * @note When an EFF is attached, this function must not be called during - * transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. - * Returns RAIL_STATUS_INVALID_STATE if the thermistor is started while the - * radio is transmitting. - */ -RAIL_Status_t RAIL_StartThermistorMeasurement(RAIL_Handle_t railHandle); - -/** - * Get the thermistor impedance measurement and return \ref - * RAIL_INVALID_THERMISTOR_VALUE if the thermistor is not properly - * configured or the thermistor measurement is not ready. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] thermistorImpedance Current thermistor impedance measurement in - * Ohms. - * @return Status code indicating success of the function call. - * - * @note This function is already called in \ref RAIL_CalibrateHFXO(). - * It does not need to be manually called during the compensation sequence. - */ -RAIL_Status_t RAIL_GetThermistorImpedance(RAIL_Handle_t railHandle, - uint32_t *thermistorImpedance); - -/** - * Convert the thermistor impedance into temperature, in Celsius. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] thermistorImpedance Current thermistor impedance measurement in - * Ohms. - * @param[out] thermistorTemperatureC Pointer to current thermistor temperature - * in eighth of Celsius degree - * @return Status code indicating success of the function call. - * - * A version of this function is provided in the \ref rail_util_thermistor - * plugin for Silicon Labs radio boards. For custom boards this function can be - * modified and re-implemented as needed. - * - * The variable railHandle is only used to indicate to the user from where the - * function was called, so it is okay to use either a real protocol handle, - * or one of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. - * - * @note This plugin is mandatory on EFR32xG25 platform. - */ -RAIL_Status_t RAIL_ConvertThermistorImpedance(RAIL_Handle_t railHandle, - uint32_t thermistorImpedance, - int16_t *thermistorTemperatureC); - -/** - * Compute the crystal PPM deviation from the thermistor temperature. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] crystalTemperatureC Current crystal temperature. - * @param[out] crystalPPMError Pointer to current ppm error. - * @return Status code indicating success of the function call. - * - * This function is provided in the rail_util_thermistor plugin to get - * accurate values from our boards thermistor. For a custom board, this - * function could be modified and re-implemented for other needs. - * The variable railHandle is only used to indicate to the user from where the - * function was called, so it is okay to use either a real protocol handle, - * or one of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. - * - * @note This plugin is mandatory on EFR32xG25 platform. - */ -RAIL_Status_t RAIL_ComputeHFXOPPMError(RAIL_Handle_t railHandle, - int16_t crystalTemperatureC, - int8_t *crystalPPMError); - -/** - * Configure the GPIO for thermistor usage. - * - * @param railHandle A RAIL instance handle. - * @param[in] pHfxoThermistorConfig The thermistor configuration pointing to - * the GPIO port and pin to access. - * @return Status code indicating the result of the function call. - * - * @note The port and pin that must be passed in \ref RAIL_HFXOThermistorConfig_t - * are GPIO_THMSW_EN_PORT and GPIO_THMSW_EN_PIN respectively. - */ -RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, - const RAIL_HFXOThermistorConfig_t *pHfxoThermistorConfig); - -/** - * Configure the temperature parameters for HFXO compensation. - * - * @param railHandle A RAIL instance handle. - * @param[in] pHfxoCompensationConfig HFXO compensation parameters pointing to the - * temperature variations used to trigger a compensation. - * @return Status code indicating the result of the function call. - * - * @note This function must be called after \ref RAIL_ConfigHFXOThermistor to succeed. - * - * In \ref RAIL_HFXOCompensationConfig_t, deltaNominal and deltaCritical define - * the temperature variation triggering a new compensation. - * The field zoneTemperatureC defines the temperature separating - * the nominal case (below) from the critical one (above). - * - * When enabled and either deltaNominal or deltaCritical are exceeded, RAIL raises - * event \ref RAIL_EVENT_CAL_NEEDED with \ref RAIL_CAL_TEMP_HFXO bit set. - * The API \ref RAIL_StartThermistorMeasurement() must be called afterwards. - * The latter will raise RAIL_EVENT_THERMISTOR_DONE with calibration bit - * \ref RAIL_CAL_COMPENSATE_HFXO set and RAIL_CalibrateHFXO() must follow. - * - * @note Set deltaNominal and deltaCritical to 0 to perform compensation after - * each transmit. - */ -RAIL_Status_t RAIL_ConfigHFXOCompensation(RAIL_Handle_t railHandle, - const RAIL_HFXOCompensationConfig_t *pHfxoCompensationConfig); - -/** - * Get the temperature parameters for HFXO compensation. - * - * @param railHandle A RAIL instance handle. - * @param pHfxoCompensationConfig HFXO compensation parameters pointing to the - * temperature variations used to trigger a compensation. - * @return Status code indicating the result of the function call. - */ -RAIL_Status_t RAIL_GetHFXOCompensationConfig(RAIL_Handle_t railHandle, - RAIL_HFXOCompensationConfig_t *pHfxoCompensationConfig); - -/** - * Compute a frequency offset and compensate HFXO accordingly. - * - * @param railHandle A RAIL instance handle. - * @param crystalPPMError The current ppm error. Positive values indicate the HFXO - * frequency is too high; negative values indicate it's too low. - * @return Status code indicating success of the function call. - * - * @note This function only works for platforms having - * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR alongside \ref RAIL_SUPPORTS_HFXO_COMPENSATION. - */ -RAIL_Status_t RAIL_CompensateHFXO(RAIL_Handle_t railHandle, int8_t crystalPPMError); -/** @} */ // end of group External_Thermistor - -/** - * @addtogroup Features - * @{ - */ - -/** - * Indicate whether RAIL supports 2.4 GHz band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 2.4 GHz band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_2P4GHZ_BAND. - */ -bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports SubGHz band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the SubGHz band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SUBGHZ_BAND. - */ -bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports dual 2.4 GHz and SubGHz band operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the dual band is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_BAND. - */ -bool RAIL_SupportsDualBand(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports bit masked address filtering. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if bit masked address filtering is supported; false otherwise. - * - * Runtime refinement of compile-time - * \ref RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK. - */ -bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports address filter mask information - * for incoming packets in - * \ref RAIL_RxPacketInfo_t::filterMask and - * \ref RAIL_IEEE802154_Address_t::filterMask. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if address filter information is supported; false otherwise - * (in which case \ref RAIL_RxPacketInfo_t::filterMask value is undefined). - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. - */ -bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports alternate TX power settings. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if alternate TX power settings are supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_ALTERNATE_TX_POWER. - */ -bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports antenna diversity. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if antenna diversity is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. - * - * @note Certain radio configurations may not support this feature even - * if the chip in general claims to support it. - */ -bool RAIL_SupportsAntennaDiversity(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports AUXADC measurements on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if AUXADC measurements are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_AUXADC. - */ -bool RAIL_SupportsAuxAdc(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports channel hopping on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if channel hopping is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_CHANNEL_HOPPING. - */ -bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports direct mode. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if direct mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_DIRECT_MODE. - */ -bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports dual sync words. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if dual sync words are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_SYNC_WORDS. - * - * @note Certain radio configurations may not support this feature even - * if the chip in general claims to support it. - */ -bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports start to start TX repeats. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if start to start TX repeats are supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_TX_REPEAT_START_TO_START. - */ -bool RAIL_SupportsTxRepeatStartToStart(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports EFF. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if EFF identifier is supported; false otherwise. - */ -bool RAIL_SupportsEff(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports thermistor measurements on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if thermistor measurements are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. - */ -bool RAIL_SupportsExternalThermistor(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports HFXO compensation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if HFXO compensation is supported and - * \ref RAIL_ConfigHFXOThermistor() has been successfully called; - * false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_HFXO_COMPENSATION. - */ -bool RAIL_SupportsHFXOCompensation(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports MFM protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if MFM protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_MFM. - */ -bool RAIL_SupportsMfm(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports OFDM band operation on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if OFDM operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_OFDM_PA. - */ -bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports a high-precision LFRCO. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if high-precision LFRCO is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PRECISION_LFRCO. - */ -bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports radio entropy. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if radio entropy is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RADIO_ENTROPY. - */ -bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports RFSENSE Energy Detection Mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RFSENSE Energy Detection Mode is supported; false otherwise. - * - * Runtime refinement of compile-time - * \ref RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION. - */ -bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports RFSENSE Selective(OOK) Mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if RFSENSE Selective(OOK) Mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. - */ -bool RAIL_SupportsRfSenseSelectiveOok(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports configurable RSSI threshold - * set by \ref RAIL_SetRssiDetectThreshold(). - * - * @param[in] railHandle A RAIL instance handle. - * @return true if setting configurable RSSI is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD. - */ -bool RAIL_SupportsRssiDetectThreshold(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports RX direct mode data to FIFO. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if direct mode data to FIFO is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO. - */ -bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports raw RX data - * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if direct mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RX_RAW_DATA. - */ -bool RAIL_SupportsRxRawData(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports SQ-based PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the SQ-based PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SQ_PHY. - */ -bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports a particular power mode (PA). - * @note Consider using \ref RAIL_SupportsTxPowerModeAlt to also get the power - * mode's lowest allowed power level. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] powerMode The power mode to check if supported. - * @param[out] pMaxPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that - * if non-NULL will be filled in with the power mode's highest power level - * allowed if this function returns true. - * @return true if the powerMode is supported; false otherwise. - * - * This function has no compile-time equivalent. - */ -bool RAIL_SupportsTxPowerMode(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t powerMode, - RAIL_TxPowerLevel_t *pMaxPowerLevel); - -/** - * Indicate whether this chip supports a particular power mode (PA) and - * provides the maximum and minimum power level for that power mode - * if supported by the chip. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] powerMode A pointer to PA power mode to check if supported. - * For platforms that support \ref RAIL_TX_POWER_MODE_2P4_HIGHEST or - * \ref RAIL_TX_POWER_MODE_SUBGIG_HIGHEST the powerMode is updated - * to the highest corresponding PA available on the chip. - * @param[out] maxPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that - * if non-NULL will be filled in with the power mode's highest power level - * allowed if this function returns true. - * @param[out] minPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that - * if non-NULL will be filled in with the power mode's lowest power level - * allowed if this function returns true. - * @return true if powerMode is supported; false otherwise. - */ -bool RAIL_SupportsTxPowerModeAlt(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t *powerMode, - RAIL_TxPowerLevel_t *maxPowerLevel, - RAIL_TxPowerLevel_t *minPowerLevel); - -/** - * Indicate whether this chip supports automatic TX to TX transitions. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if TX to TX transitions are supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TX_TO_TX. - */ -bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports the BLE protocol on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_BLE. - */ -bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE 1Mbps Non-Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps Non-Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI. - */ -bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE 1Mbps Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI. - */ -bool RAIL_BLE_Supports1MbpsViterbi(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE 1Mbps operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 1Mbps operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS. - */ -static inline -bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) -{ - bool temp = RAIL_BLE_Supports1MbpsViterbi(railHandle); // Required for MISRA compliance - return (RAIL_BLE_Supports1MbpsNonViterbi(railHandle) - || temp); -} - -/** - * Indicate whether this chip supports BLE 2Mbps Non-Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps Non-Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI. - */ -bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE 2Mbps Viterbi PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps Viterbi is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI. - */ -bool RAIL_BLE_Supports2MbpsViterbi(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE 2Mbps operation. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE 2Mbps operation is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS. - */ -static inline -bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle) -{ - bool temp = RAIL_BLE_Supports2MbpsViterbi(railHandle); // Required for MISRA compliance - return (RAIL_BLE_Supports2MbpsNonViterbi(railHandle) - || temp); -} - -/** - * Indicate whether this chip supports BLE Antenna Switching needed for - * Angle-of-Arrival receives or Angle-of-Departure transmits. - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Antenna Switching is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING. - */ -bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE Coded PHY used for Long-Range. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Coded PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CODED_PHY. - */ -bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE CTE (Constant Tone Extension) - * needed for Angle-of-Arrival/Departure transmits. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE CTE is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CTE. - */ -bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Indicate whether this chip supports BLE HADM. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE HADM is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_HADM. - */ -bool RAIL_BLE_SupportsHadm(RAIL_Handle_t railHandle); -#endif - -/** - * Indicate whether this chip supports BLE IQ Sampling needed for - * Angle-of-Arrival/Departure receives. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE IQ Sampling is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_IQ_SAMPLING. - */ -bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE PHY switch to RX - * functionality, which is used to switch BLE PHYs at a specific time - * to receive auxiliary packets. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE PHY switch to RX is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. - */ -bool RAIL_BLE_SupportsPhySwitchToRx(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the Quuppa PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Quuppa is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_QUUPPA. - */ -bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE signal identifier. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if signal identifier is supported; false otherwise. - */ -bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous - * BLE 1Mbps and Coded PHY reception. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if BLE Simulscan PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY. - */ -bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4 protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154. - */ -bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Indicate whether this chip supports the IEEE 802.15.4 2Mbps PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 2Mbps PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY. - */ -bool RAIL_IEEE802154_Supports2MbpsPhy(RAIL_Handle_t railHandle); -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Indicate whether this chip supports the IEEE 802.15.4 Wi-Fi Coexistence PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 COEX PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. - */ -bool RAIL_IEEE802154_SupportsCoexPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4 2.4 GHz band variant. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if IEEE 802.15.4 2.4 GHz band variant is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_IEEE802154_BAND_2P4. - */ -bool RAIL_SupportsIEEE802154Band2P4(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the thermal protection. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if thermal protection is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_THERMAL_PROTECTION. - */ -bool RAIL_SupportsThermalProtection(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4 2.4 RX channel switching. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if IEEE 802.15.4 2.4 GHz RX channel switching is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING. - */ -bool RAIL_IEEE802154_SupportsRxChannelSwitching(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4 PHY with custom settings. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the 802.15.4 PHY with custom settings is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY. - */ -bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4 - * front end module optimized PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if a front end module is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY. - */ -bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports canceling the frame-pending lookup - * event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND when the radio - * transitions to a state that renders the the reporting of this event moot - * (i.e., too late for the stack to influence the outgoing ACK). - * - * @param[in] railHandle A RAIL instance handle. - * @return true if canceling the lookup event is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. - */ -bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports early triggering of the frame-pending - * lookup event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND - * just after MAC address fields have been received. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if early triggering is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. - */ -bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); - -/** - * Indicate whether RAIL supports dual PA mode on this chip. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the dual PA mode is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG. - */ -bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced ACKing. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4E Enhanced ACKing is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. - */ -bool RAIL_IEEE802154_SupportsEEnhancedAck(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4E-2012 Multipurpose frame - * reception. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Multipurpose frame reception is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. - */ -bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the IEEE 802.15.4E-2012 feature - * subset needed for Zigbee R22 GB868. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4E GB868 subset is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. - */ -bool RAIL_IEEE802154_SupportsESubsetGB868(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 reception and - * transmission of frames with 4-byte CRC. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G 4-byte CRC is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. - */ -bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4G dynamic FEC. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if dynamic FEC is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_DYNFEC. - */ -bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports Wi-SUN. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Wi-SUN is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_SUPPORTS_PROTOCOL_WI_SUN. - */ -bool RAIL_SupportsProtocolWiSUN(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports Wi-SUN mode switching. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Wi-SUN mode switching is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_MODESWITCH. - */ -bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 feature - * subset needed for Zigbee R22 GB868. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G GB868 subset is supported; false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. - */ -bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 reception - * of unwhitened frames. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G unwhitened frame reception is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. - */ -bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4G-2012 transmission - * of unwhitened frames. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if 802.15.4G unwhitened frame transmit is supported; - * false otherwise. - * - * Runtime refinement of compile-time \ref - * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. - */ -bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports WMBUS simultaneous M2O RX of T and C modes. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the WMBUS simultaneous M2O RX of T and C modes is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX. - */ -bool RAIL_WMBUS_SupportsSimultaneousTCRx(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the Z-Wave protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. - */ -bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the Z-Wave concurrent PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave concurrent PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_CONC_PHY. - */ -bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports the Z-Wave energy detect PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if the Z-Wave energy detect PHY is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_ED_PHY. - */ -bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports Z-Wave Region in PTI. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if ZWAVE Region in PTI is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. - */ -bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports IEEE 802.15.4 signal identifier. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if signal identifier is supported; false otherwise. - */ -bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports fast RX2RX. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if fast RX2RX is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_FAST_RX2RX. - */ -bool RAIL_SupportsFastRx2Rx(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports collision detection. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if collision detection is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_COLLISION_DETECTION. - */ -bool RAIL_SupportsCollisionDetection(RAIL_Handle_t railHandle); - -/** - * Indicate whether this chip supports Sidewalk protocol. - * - * @param[in] railHandle A RAIL instance handle. - * @return true if Sidewalk protocol is supported; false otherwise. - * - * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK. - */ -bool RAIL_SupportsProtocolSidewalk(RAIL_Handle_t railHandle); - -/** @} */ // end of group Features - -/** @} */ // end of group RAIL_API - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_H__ +/***************************************************************************//** + * @file + * @brief The main header file for the RAIL library. It describes the external + * APIs available to a RAIL user + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_H__ +#define __RAIL_H__ + +#include // For memcpy() + +// Get the RAIL-specific structures and types +#include "rail_types.h" +#include "rail_assert_error_codes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RAIL_API RAIL API + * @brief This is the primary API layer for the Radio Abstraction Interface + * Layer (RAIL) + * @{ + */ + +/** + * @defgroup Chip_Specific Chip-Specific + * @brief Chip-Specific RAIL APIs, types, and information + */ + +/** + * @defgroup Protocol_Specific Protocol-specific + * @brief Protocol-Specific RAIL APIs + */ + +/****************************************************************************** + * General Radio Operation + *****************************************************************************/ +/** + * @addtogroup General + * @brief Basic APIs to set up and interact with the RAIL library + * @{ + */ + +/** + * Get the version information for the compiled RAIL library. + * + * @param[out] version A pointer to \ref RAIL_Version_t structure to + * populate with version information. + * @param[in] verbose Populate \ref RAIL_Version_t struct with verbose + * information. + * + * The version information contains a major version number, a minor version + * number, and a rev (revision) number. + */ +void RAIL_GetVersion(RAIL_Version_t *version, bool verbose); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/** + * A global pointer to the head of a linked list of state buffers + * \ref RAIL_Init() can use. + * + * RAIL internally provides one statically-allocated RAM state buffer + * for a single protocol and two for dynamic multiprotocol. If your + * application needs more, they can be provided via \ref + * RAIL_AddStateBuffer3() or RAIL_AddStateBuffer4(), which use + * internal buffers, or the more general \ref RAIL_AddStateBuffer(). + * + * This symbol is WEAK in the RAIL library in case an application wants + * to allocate and provide its own buffers. However, this use is highly + * discouraged. + */ +extern RAIL_StateBufferEntry_t *RAIL_StateBufferHead; + +/** + * Get the run-time size of the radio's state buffer. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Size, in bytes, of the radio's internal state buffer. + * If the handle is invalid, 0 is returned. + * + * See \ref RAIL_STATE_BUFFER_BYTES for a compile-time estimated size + * definition, which may be larger than what this function returns. + */ +uint32_t RAIL_GetStateBufferSize(RAIL_Handle_t genericRailHandle); + +/** + * Add an app-provided state buffer to the \ref RAIL_StateBufferHead list. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @param[in] newEntry pointer to a \ref RAIL_StateBufferEntry_t to + * add to the liked list of state buffers headed by + * \ref RAIL_StateBufferHead. Both the \ref RAIL_StateBufferEntry_t + * to which this parameter points and the \ref + * RAIL_StateBufferEntry_t::buffer to which that points must be + * allocated in RAM and persist indefinitely beyond this call. + * @return Status code indicating success of the function call. + * An error should be returned if the entry's + * \ref RAIL_StateBufferEntry_t::bufferBytes is too small or + * the RAIL_StateBufferEntry_t::buffer pointer seems invalid. + * + * RAIL's internal \ref RAIL_StateBufferHead should prove + * sufficient for most applications, providing one (single protocol) + * or two (dynamic multiprotocol) buffers preallocated in RAM for + * use by \ref RAIL_Init(). This function exists for dynamic + * multiprotocol applications that needs more than two protocols, or + * that prefer to dynamically allocate RAIL state buffers just prior + * to calling \ref RAIL_Init() rather than having them statically + * allocated in RAM. + */ +RAIL_Status_t RAIL_AddStateBuffer(RAIL_Handle_t genericRailHandle, + RAIL_StateBufferEntry_t *newEntry); + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * Add a 3rd multiprotocol internal state buffer for use by \ref RAIL_Init(). + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * An error is returned if the 3rd state buffer was previously added + * or this isn't the RAIL multiprotocol library. + */ +RAIL_Status_t RAIL_AddStateBuffer3(RAIL_Handle_t genericRailHandle); + +/** + * Add a 4th multiprotocol internal state buffer for use by \ref RAIL_Init(). + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * An error is returned if the 4th state buffer was previously added. + * or this isn't the RAIL multiprotocol library. + */ +RAIL_Status_t RAIL_AddStateBuffer4(RAIL_Handle_t genericRailHandle); + +/** + * Allocate a DMA channel for RAIL to work with. + * + * @param[in] channel The DMA channel to use when copying memory. If a value of + * RAIL_DMA_INVALID is passed, RAIL will stop using any DMA channel. + * @return Status code indicating success of the function call. + * + * To use this API, the application must initialize the DMA engine + * on the chip and allocate a DMA channel. This channel will be used + * periodically to copy memory more efficiently. Call this function + * before RAIL_Init to have the most benefit. If the application needs + * to take back control of the DMA channel that RAIL is using, this API may be + * called with a channel of RAIL_DMA_INVALID to tell RAIL to stop using DMA. + */ +RAIL_Status_t RAIL_UseDma(uint8_t channel); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Load the first image \ref RAIL_SEQ_IMAGE_1 into the radio sequencer during + * RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_LoadSequencerImage1(RAIL_Handle_t genericRailHandle); + +/** + * Load the second image \ref RAIL_SEQ_IMAGE_2 into the radio sequencer during + * RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_RadioSequencerImageLoad. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. On platforms where \ref RAIL_SEQ_IMAGE_COUNT < 2, + * the function returns with \ref RAIL_STATUS_INVALID_CALL. + */ +RAIL_Status_t RAIL_LoadSequencerImage2(RAIL_Handle_t genericRailHandle); + +/** + * Callback used to load the radio sequencer image during RAIL initialization. + * This function is optional to implement. + * + * @return Status code indicating success of the function call. + * + * This callback is used by RAIL to load a radio sequencer image during \ref + * RAIL_Init via an API such as \ref RAIL_LoadSequencerImage1. If this + * function is not implemented, a default image will be loaded. On some + * platforms, (in particular EFR32XG24), not implementing this function may + * result in a larger overall code size due to unused sequencer images not + * being dead stripped. + * + * @note If this function is implemented without a call to an image loading API + * such as \ref RAIL_LoadSequencerImage1, an assert will occur during + * RAIL initialization. Similarly, if an image is loaded that is + * unsupported by the platform, an assert will occur. + */ +RAIL_Status_t RAILCb_RadioSequencerImageLoad(void); + +/** + * Load the FSK, OFDM and OQPSK image into the software modem (SFM) sequencer + * during RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_LoadSfmSunFskOfdmOqpsk(RAIL_Handle_t genericRailHandle); + +/** + * Load the OFDM and OQPSK image into the software modem (SFM) sequencer during + * RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_LoadSfmSunOfdmOqpsk(RAIL_Handle_t genericRailHandle); + +/** + * Load the OFDM image into the software modem (SFM) sequencer during + * RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_LoadSfmSunOfdm(RAIL_Handle_t genericRailHandle); + +/** + * Load the empty image into the software modem (SFM) sequencer during + * RAIL initialization. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Status code indicating success of the function call. + * + * This function must only be called from within the RAIL callback context of + * \ref RAILCb_LoadSfmSequencer. Otherwise, the function returns \ref + * RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_LoadSfmEmpty(RAIL_Handle_t genericRailHandle); + +/** + * Callback used to load the software modem (SFM) sequencer image during RAIL + * initialization. This function is optional to implement. + * + * @return Status code indicating success of the function call. + * + * This callback is used by RAIL to load a software modem sequencer image during \ref + * RAIL_Init via an API such as \ref RAIL_LoadSfmSunFskOfdmOqpsk. If this + * function is not implemented, a default image including FSK, OFDM andd OQPSK + * modulations will be loaded. + * + * @note If this function is implemented without a call to an image loading API + * such as \ref RAIL_LoadSfmSunFskOfdmOqpsk, an assert will occur during + * RAIL initialization. Similiarly, if an image is loaded that is + * unsupported by the platform, an assert will occur. + */ +RAIL_Status_t RAILCb_LoadSfmSequencer(void); +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Initialize RAIL. + * + * @param[in,out] railCfg The configuration and state structure for setting up + * the library, which contains memory and other options that RAIL needs. + * This structure must be allocated in application global read-write + * memory. RAIL may modify fields within or referenced by this structure + * during its operation. + * @param[in] cb A callback that notifies the application when the radio is + * finished initializing and is ready for further configuration. This + * callback is useful for potential transceiver products that require a + * power up sequence before further configuration is available. After the + * callback fires, the radio is ready for additional configuration before + * transmit and receive operations. + * @return Handle for initialized rail instance or NULL if an + * invalid value was passed in the railCfg. + * + * @note Call this function only once per protocol. If called + * again, it will do nothing and return NULL. + */ +RAIL_Handle_t RAIL_Init(RAIL_Config_t *railCfg, + RAIL_InitCompleteCallbackPtr_t cb); + +/** + * Get RAIL initialization status. + * + * @return True if the radio has finished initializing and + * false otherwise. + * + * RAIL APIs, e.g., RAIL_GetTime(), which work only if RAIL_Init() has been called, + * can use RAIL_IsInitialized() to determine whether RAIL has been initialized or not. + */ +bool RAIL_IsInitialized(void); + +/** + * Collect entropy from the radio if available. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] buffer The buffer to write the collected entropy. + * @param[in] bytes The number of bytes to fill in the input buffer. + * @return Returns the number of bytes of entropy collected. For + * chips that don't support entropy collection, the function returns 0. + * Values less than the requested amount may also be returned on platforms + * that use entropy pools to collect random data periodically. + * + * Attempts to fill the provided buffer with the requested number of bytes of + * entropy. If the requested number of bytes can't be provided, as many + * bytes as possible will be filled and returned. For chips + * that do not support this function, 0 bytes are always returned. For + * information about the specific mechanism for gathering entropy, see + * documentation for the chip family. + */ +uint16_t RAIL_GetRadioEntropy(RAIL_Handle_t railHandle, + uint8_t *buffer, + uint16_t bytes); + +/** @} */ // end of group General + +/****************************************************************************** + * PTI + *****************************************************************************/ +/** + * @addtogroup PTI Packet Trace (PTI) + * @brief Basic APIs to set up and interact with PTI settings + * @{ + */ + +/** + * Configure PTI pin locations, serial protocols, and baud rates. + * + * @param[in] railHandle A RAIL instance handle (currently not used). + * @param[in] ptiConfig A configuration structure applied to the + * relevant PTI registers. A NULL ptiConfig will produce undefined + * behavior. + * @return Status code indicating success of the function call. + * + * This method must be called before RAIL_EnablePti() is called. + * Although a RAIL handle is included for potential future + * expansion of this function, it is currently not used. That is, + * there is only one PTI configuration that can be active on a + * chip, regardless of the number of protocols (unless the application + * updates the configuration upon a protocol switch), + * and the configuration is not saved in the RAIL instance. For optimal + * future compatibility, pass in a chip-specific handle, such as + * \ref RAIL_EFR32_HANDLE. + * + * PTI should be configured only when the radio is off (idle). + * + * @note On EFR32 platforms GPIO configuration must be unlocked + * (see GPIO->LOCK register) to configure or use PTI. + */ +RAIL_Status_t RAIL_ConfigPti(RAIL_Handle_t railHandle, + const RAIL_PtiConfig_t *ptiConfig); + +/** + * Get the currently-active PTI configuration. + * + * @param[in] railHandle A RAIL instance handle (currently not used). + * @param[out] ptiConfig A configuration structure filled with the active + * PTI configuration. + * @return RAIL status indicating success of the function call. + * + * Although most combinations of configurations can be set, it is safest + * to call this method after configuration to confirm which values were + * actually set. As in RAIL_ConfigPti, railHandle is not used. This function + * always returns the single active PTI configuration regardless of the + * active protocol. For optimal future compatibility, pass in a + * chip-specific handle, such as \ref RAIL_EFR32_HANDLE. + */ +RAIL_Status_t RAIL_GetPtiConfig(RAIL_Handle_t railHandle, + RAIL_PtiConfig_t *ptiConfig); + +/** + * Enable Packet Trace Interface (PTI) output of packet data. + * + * @param[in] railHandle A RAIL instance handle (currently not used). + * @param[in] enable PTI is enabled if true; disable if false. + * @return RAIL status indicating success of the function call. + * + * Similarly to having only one PTI configuration per chip, + * PTI can only be enabled or disabled for all protocols. It cannot + * be individually set to enabled and disabled per protocol + * (unless the application switches it when + * the protocol switches), and enable/disable is not saved as part of the + * RAIL instance. For optimal future compatibility, pass in a chip-specific + * handle, such as \ref RAIL_EFR32_HANDLE. + * + * PTI should be enabled or disabled only when the radio is off (idle). + * + * @warning On EFR32 platforms GPIO configuration must be unlocked + * (see GPIO->LOCK register) to configure or use PTI, otherwise a fault + * or assert might occur. + * If GPIO configuration locking is desired, PTI must be disabled + * beforehand either with this function or with \ref RAIL_ConfigPti() + * using \ref RAIL_PTI_MODE_DISABLED. + */ +RAIL_Status_t RAIL_EnablePti(RAIL_Handle_t railHandle, + bool enable); + +/** + * Set a protocol that RAIL outputs on PTI. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] protocol The enumeration representing which protocol the node is using. + * @return Status code indicating success of the function call. + * + * The protocol is output via PTI for each packet. + * Before any protocol is set, the default value is \ref + * RAIL_PTI_PROTOCOL_CUSTOM. Use one of the enumeration values so that + * the Network Analyzer can decode the packet. + * + * @note This function cannot be called unless the radio is currently in the + * \ref RAIL_RF_STATE_IDLE or \ref RAIL_RF_STATE_INACTIVE states. For this + * reason, call this function early on before starting radio + * operations and not changed later. + */ +RAIL_Status_t RAIL_SetPtiProtocol(RAIL_Handle_t railHandle, + RAIL_PtiProtocol_t protocol); + +/** + * Get the protocol that RAIL outputs on PTI. + * + * @param[in] railHandle A RAIL instance handle. + * @return PTI protocol in use. + */ +RAIL_PtiProtocol_t RAIL_GetPtiProtocol(RAIL_Handle_t railHandle); + +/** @} */ // end of group PTI + +/****************************************************************************** + * Antenna Control + *****************************************************************************/ +/** + * @addtogroup Antenna_Control Antenna Control + * @brief Basic APIs to control the antenna functionality + * @{ + */ +/** + * Configure antenna path and pin locations. + * + * @warning This API must be called before any TX or RX occurs. Otherwise, + * the antenna configurations for those functions will not take effect. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A configuration structure applied to the relevant Antenna + * Configuration registers. A NULL configuration will produce undefined behavior. + * @return Status code indicating success of the function call. + * + * This function informs RAIL how to select each antenna, but not when. + * Antenna selection for receive is controlled by the + * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA0 and + * \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA1 options + * (and the \ref RAIL_RxOptions_t::RAIL_RX_OPTION_ANTENNA_AUTO combination). + * Antenna selection for transmit is controlled by the + * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA0 and + * \ref RAIL_TxOptions_t::RAIL_TX_OPTION_ANTENNA1 options. + * + * Although a RAIL handle is included for potential future + * expansion of this function, it is currently not used. That is, + * only one antenna configuration can be active on a + * chip, regardless of the number of protocols (unless the application + * updates the configuration upon a protocol switch), + * and the configuration is not saved in the RAIL instance. For optimal + * future compatibility, pass in a chip-specific handle, such as + * \ref RAIL_EFR32_HANDLE. + */ +RAIL_Status_t RAIL_ConfigAntenna(RAIL_Handle_t railHandle, + const RAIL_AntennaConfig_t *config); + +/** + * Get the default RF path. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] rfPath Pointer to RF path. + * @return A status code indicating success of the function call. + * + * If multiple protocols are used, this function returns + * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is + * not active. In that case, the caller must attempt to re-call this function later, + * for example when \ref RAIL_EVENT_CONFIG_SCHEDULED trigger. + */ +RAIL_Status_t RAIL_GetRfPath(RAIL_Handle_t railHandle, RAIL_AntennaSel_t *rfPath); + +/** @} */ // end of group Antenna_Control + +/****************************************************************************** + * Radio Configuration + *****************************************************************************/ +/// @addtogroup Radio_Configuration Radio Configuration +/// @brief Routines for setting up and querying radio configuration information. +/// +/// These routines allow for runtime flexibility in the radio +/// configuration. Some of the parameters, however, are meant to be generated +/// from the radio calculator in Simplicity Studio. The basic code to configure +/// the radio from this calculator output looks like the example below. +/// +/// @code{.c} +/// // Associate a specific channel configuration with a particular RAIL instance and +/// // load the settings that correspond to the first usable channel. +/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); +/// @endcode +/// +/// For more information about the types of parameters that can be changed in +/// the other functions and how to use them, see their individual documentation. +/// +/// @{ + +/** + * Load a static radio configuration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A pointer to a radio configuration. + * @return Status code indicating success of the function call. + * + * The configuration passed into this function should be auto-generated + * and not manually created or edited. By default, do not call this function + * in RAIL 2.x and later unless instructed by Silicon Labs because it + * may bypass updating certain RAIL state. In RAIL 2.x and later, the + * RAIL_ConfigChannels function applies the default radio configuration + * automatically. + */ +RAIL_Status_t RAIL_ConfigRadio(RAIL_Handle_t railHandle, + RAIL_RadioConfig_t config); + +/** + * Modify the currently configured fixed frame length in bytes. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] length The expected fixed frame length. A value of 0 is infinite. + * A value of RAIL_SETFIXEDLENGTH_INVALID restores the frame's length back to + * the length specified by the default frame type configuration. + * @return Length configured; The new frame length configured into the hardware + * for use. 0 if in infinite mode, or RAIL_SETFIXEDLENGTH_INVALID if the frame + * length has not yet been overridden by a valid value. + * + * Sets the fixed-length configuration for transmit and receive. + * Be careful when using this function in receive and transmit as this + * function changes the default frame configuration and remains in force until + * it is called again with an input value of RAIL_SETFIXEDLENGTH_INVALID. This + * function will override any fixed or variable length settings from a radio + * configuration. + */ +uint16_t RAIL_SetFixedLength(RAIL_Handle_t railHandle, uint16_t length); + +/** + * Configure the channels supported by this device. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config A pointer to the channel configuration for your device. + * This pointer will be cached in the library so it must + * exist for the runtime of the application. Typically, this should be + * what is stored in Flash by the configuration tool. + * @param[in] cb Function called whenever a radio configuration change occurs. + * @return Returns the first available channel in the configuration. + * + * When configuring channels on EFR32, the radio tuner is reconfigured + * based on the frequency and channel spacing in the channel configuration. + * + * @note config can be NULL to simply register or unregister the cb callback + * function when using RAIL internal protocol-specific radio configuration + * APIs for BLE, IEEE 802.15.4, or Z-Wave, which lack callback specification. + * In this use case, 0 is returned. + */ +uint16_t RAIL_ConfigChannels(RAIL_Handle_t railHandle, + const RAIL_ChannelConfig_t *config, + RAIL_RadioConfigChangedCallback_t cb); + +/** + * Get verbose listing of channel metadata for the current channel configuration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] channelMetadata Allocated array that will be populated with + * channel metadata. + * @param[in,out] length Pointer to the length of the channelMetadata. + * This value will be updated to the number of channels written to the array. + * @param[in] minChannel Minimum channel number about which to collect data. + * @param[in] maxChannel Maximum channel number about which to collect data. + * @return Status of the call. \ref RAIL_STATUS_INVALID_PARAMETER means that, + * based on the currently active radio configuration, there are more + * channels to write than there is space provided in the allocated + * channelMetadata. However, the channel metadata that was written is valid. + * \ref RAIL_STATUS_INVALID_STATE indicates that the channel configuration + * has not been configured. \ref RAIL_STATUS_NO_ERROR indicates complete + * success. + */ +RAIL_Status_t RAIL_GetChannelMetadata(RAIL_Handle_t railHandle, + RAIL_ChannelMetadata_t *channelMetadata, + uint16_t *length, + uint16_t minChannel, + uint16_t maxChannel); + +/** + * Check whether the channel exists in RAIL. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel A channel number to check. + * @return Returns RAIL_STATUS_NO_ERROR if channel exists + * + * Returns RAIL_STATUS_INVALID_PARAMETER if the given channel does not exist + * in the channel configuration currently used or RAIL_STATUS_NO_ERROR if the + * channel is valid. + */ +RAIL_Status_t RAIL_IsValidChannel(RAIL_Handle_t railHandle, + uint16_t channel); + +/** + * Cause radio settings associated with a particular channel to be applied to + * hardware. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel The channel to prepare for use. + * @return \ref RAIL_STATUS_NO_ERROR on success or + * \ref RAIL_STATUS_INVALID_PARAMETER if the given channel does not have an + * associated channel configuration entry. + * + * This function walks the channelConfigEntry list and applies the configuration + * associated with the specified channel. This function manually + * changes channels without starting a TX or RX operation. + * + * When successful, the radio is idled. + * When unsuccessful, the radio state will not be altered. + */ +RAIL_Status_t RAIL_PrepareChannel(RAIL_Handle_t railHandle, uint16_t channel); + +/** + * Return the current RAIL channel. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] channel The channel for which RAIL is currently configured. + * @return RAIL_STATUS_NO_ERROR on success or + * RAIL_STATUS_INVALID_CALL if the radio is not configured for any channel or + * RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. + * + * This function returns the channel most recently specified in API calls that + * pass in a channel to tune to, namely \ref RAIL_PrepareChannel, + * \ref RAIL_StartTx, \ref RAIL_StartScheduledTx, \ref RAIL_StartCcaCsmaTx, + * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, + * \ref RAIL_StartScheduledCcaLbtTx, \ref RAIL_StartRx, \ref RAIL_ScheduleRx, + * \ref RAIL_StartAverageRssi, \ref RAIL_StartTxStream, \ref RAIL_StartTxStreamAlt. + * It doesn't follow changes RAIL performs implicitly during channel hopping and + * mode switch. + */ +RAIL_Status_t RAIL_GetChannel(RAIL_Handle_t railHandle, uint16_t *channel); + +/** + * Return the current RAIL channel. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] channel The channel for which RAIL is currently configured. + * @return RAIL_STATUS_NO_ERROR on success or + * RAIL_STATUS_INVALID_CALL if the radio is not configured for any channel or + * RAIL_STATUS_INVALID_PARAMETER if channel parameter is NULL. + * + * This function returns the channel the radio is currently tuned to if the + * specified RAIL handle is active. It returns the channel it will be tuned to + * during the next protocol switch if the handle is inactive. + * The channel returned may be different than what \ref RAIL_GetChannel returns + * when channel hopping or mode switch are involved. + */ +RAIL_Status_t RAIL_GetChannelAlt(RAIL_Handle_t railHandle, uint16_t *channel); + +/** + * Return the symbol rate for the current PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return The symbol rate in symbols per second or 0. + * + * The symbol rate is the rate of symbol changes over the air. For non-DSSS + * PHYs, this is the same as the baudrate. For DSSS PHYs, it is the baudrate + * divided by the length of a chipping sequence. For more information, + * see the modem calculator documentation. If the rate cannot be + * calculated, this function returns 0. + */ +uint32_t RAIL_GetSymbolRate(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Calculate the symbol rate for the current PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return The symbol rate in symbols per second or 0. + * + * This function calculates the symbol rate when the radio configuration does + * not include that information. In general, this function should be + * implemented automatically in the radio configuration as a stub. + */ +uint32_t RAILCb_CalcSymbolRate(RAIL_Handle_t railHandle); +#endif + +/** + * Return the bit rate for the current PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return The bit rate in bits per second or 0. + * + * The bit rate is the effective over-the-air data rate. It does not account + * for extra spreading for forward error correction, and so on, but + * accounts for modulation schemes, DSSS, and other configurations. For more + * information, see the modem calculator documentation. If the rate cannot be + * calculated, this function returns 0. + */ +uint32_t RAIL_GetBitRate(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Calculate the bit rate for the current PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return The bit rate in bits per second or 0. + * + * This function calculates the bit rate when the radio configuration does + * not include that information. In general, this function should be + * implemented automatically in the radio configuration as a stub. + */ +uint32_t RAILCb_CalcBitRate(RAIL_Handle_t railHandle); +#endif +/** + * Set the PA capacitor tune value for transmit and receive. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] txPaCtuneValue PA Ctune value for TX mode. + * @param[in] rxPaCtuneValue PA Ctune value for RX mode. + * @return Status code indicating success of the function call. + * + * Tunes the impedance of the transmit + * and receive modes by changing the amount of capacitance at + * the PA output. + * Changes made to the TX Power configuration, e.g., calling \ref RAIL_ConfigTxPower, + * will undo changes made to PA capacitor tune value for transmit and receive + * via \ref RAIL_SetPaCTune. + */ +RAIL_Status_t RAIL_SetPaCTune(RAIL_Handle_t railHandle, + uint8_t txPaCtuneValue, + uint8_t rxPaCtuneValue); + +/** + * Get the sync words and their length. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] syncWordConfig An application-provided non-NULL pointer to store + * \ref RAIL_SyncWordConfig_t sync word information. + * @return Status code indicating success of the function call. + **/ +RAIL_Status_t RAIL_GetSyncWords(RAIL_Handle_t railHandle, + RAIL_SyncWordConfig_t *syncWordConfig); + +/** + * Set the selected sync words and their length. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] syncWordConfig A non-NULL pointer to \ref RAIL_SyncWordConfig_t + * specifying the sync words and their length. + * The desired length should be between 2 and 32 bits inclusive, however it is + * recommended to not change the length below what the PHY syncWord length is + * configured to be. Changing the syncWord length, especially to that which is + * lower than the default length, may result in a decrease in packet reception + * rate or may not work at all. + * Other values will result in \ref RAIL_STATUS_INVALID_PARAMETER. The default + * syncWord continues to be valid. + * @return Status code indicating success of the function call. + * When the custom sync word(s) applied by this API are no longer needed, or to + * revert to default sync word, calling RAIL_ConfigChannels() will re-establish + * the sync words specified in the radio configuration. + * + * This function will return \ref RAIL_STATUS_INVALID_STATE if called when BLE + * has been enabled for this railHandle. When changing sync words in BLE mode, + * use \ref RAIL_BLE_ConfigChannelRadioParams instead. + **/ +RAIL_Status_t RAIL_ConfigSyncWords(RAIL_Handle_t railHandle, + const RAIL_SyncWordConfig_t *syncWordConfig); + +/** + * Sets the whitening initialization value. + * + * @param[in] railHandle A RAIL instance handle. + * @return The whitening initialization value currently being used. + */ +uint16_t RAIL_GetWhiteningInitVal(RAIL_Handle_t railHandle); + +/** + * Returns the CRC initialization value. + * + * @param[in] railHandle A RAIL instance handle. + * @return The CRC initialization value currently being used. + */ +uint32_t RAIL_GetCrcInitVal(RAIL_Handle_t railHandle); + +/** + * Sets the whitening initialization value. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] whiteInit A whitening initialization value. + * @return Status code indicating success of the function call. + * + * Use this function to override the whitening initialization value + * defined by the current PHY's radio configuration. The new value + * will persist until this function is called again, \ref + * RAIL_ResetWhiteningInitVal() is called, or the PHY is + * changed. + * + * @note Overriding a PHY's whitening initialization value + * will break communication with peers unless they effect + * a similar change. + * + * @warning This API must not be used when either 802.15.4 + * or BLE modes are enabled. + */ +RAIL_Status_t RAIL_SetWhiteningInitVal(RAIL_Handle_t railHandle, + uint16_t whiteInit); + +/** + * Sets the CRC initialization value. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] crcInit A CRC initialization value. + * @return Status code indicating success of the function call. + * + * Use this function to override the CRC initialization value + * defined by the current PHY's radio configuration. The new value + * will persist until this function is called again, \ref + * RAIL_ResetCrcInitVal() is called, or the PHY is changed. + * + * @note Overriding a PHY's CRC initialization value + * will break communication with peers unless they effect + * a similar change. + * + * @warning This API must not be used when either 802.15.4 + * or BLE modes are enabled. + */ +RAIL_Status_t RAIL_SetCrcInitVal(RAIL_Handle_t railHandle, + uint32_t crcInit); + +/** + * Restores the whitening initialization value to its initial setting + * from the Radio Configurator. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * + * Can use this function after using \ref RAIL_SetWhiteningInitVal(). + */ +RAIL_Status_t RAIL_ResetWhiteningInitVal(RAIL_Handle_t railHandle); + +/** + * Restores the CRC initialization value to its initial setting from + * the Radio Configurator. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * + * Can use this function after using \ref RAIL_SetCrcInitVal(). + */ +RAIL_Status_t RAIL_ResetCrcInitVal(RAIL_Handle_t railHandle); + +/** @} */ // end of group Radio_Configuration + +/****************************************************************************** + * Timing Information + *****************************************************************************/ +/// @addtogroup System_Timing System Timing +/// @brief Functionality related to the RAIL timer and general system time. +/// +/// These functions can be used to get information about the current system time +/// or to manipulate the RAIL timer. +/// +/// The system time returned by RAIL_GetTime() is in the same timebase that is +/// used throughout RAIL. Any callbacks or structures that provide a timestamp, +/// such as \ref RAIL_RxPacketDetails_t::timeReceived, will use the same timebase +/// as will any APIs that accept an absolute time for scheduling their action. +/// Throughout the documentation, the timebase is referred to as the RAIL +/// timebase. The timebase is currently a value in microseconds from \ref +/// RAIL_Init() time, which means that it will wrap every 1.19 hours. +/// (`(2^32 - 1) / (3600 sec/hr * 1000000 us/sec)`). +/// +/// The provided timer is hardware-backed and interrupt-driven. It can be used +/// for timing any event in the system, but is especially helpful for +/// timing protocol-based state machines and other systems that interact with +/// the radio. To avoid processing the expiration in interrupt +/// context, leave the cb parameter passed to RAIL_SetTimer() as NULL and poll +/// for expiration with the RAIL_IsTimerExpired() function. See below for an +/// example of the interrupt driven method of interacting with the timer. +/// +/// @code{.c} +/// void timerCb(RAIL_Handle_t cbArg) +/// { +/// // Timer callback action +/// } +/// +/// void main(void) +/// { +/// // Initialize RAIL ... +/// +/// // Set up a timer for 1 ms from now +/// RAIL_SetTimer(railHandle, 1000, RAIL_TIME_RELATIVE, &timerCb); +/// +/// // Run main loop +/// while(1); +/// } +/// @endcode +/// +/// If multiple software timers are needed to be run off of the one available +/// hardware timer, enable a software multiplexing layer within RAIL +/// using the \ref RAIL_ConfigMultiTimer() function. This will allow you to +/// set up as many timers as you want using the RAIL_*MultiTimer() functions. See +/// the example below for using the multitimer functionality. +/// +/// @code{.c} +/// // Declare timer structures in global space or somewhere that will exist +/// // until the callback has fired +/// RAIL_MultiTimer_t tmr1, tmr2; +/// +/// void timerCb(RAIL_MultiTimer_t *tmr, +/// RAIL_Time_t expectedTimeOfEvent, +/// void *cbArg) +/// { +/// if (tmr == tmr1) { +/// // Timer 1 action +/// } else { +/// // Timer 2 action +/// } +/// } +/// +/// void main(void) +/// { +/// // Initialize RAIL ... +/// +/// RAIL_ConfigMultiTimer(true); +/// +/// // Set up one timer for 1 ms from now and one at time 2000000 in the RAIL +/// // timebase +/// RAIL_SetMultiTimer(&tmr1, 1000, RAIL_TIME_RELATIVE, &timerCb, NULL); +/// RAIL_SetMultiTimer(&tmr2, 2000000, RAIL_TIME_ABSOLUTE, &timerCb, NULL); +/// +/// // Run main loop +/// while(1); +/// } +/// @endcode +/// +/// @{ + +/** + * Get the current RAIL time. + * + * @return Returns the RAIL timebase in microseconds. Note that this wraps + * after about 1.19 hours since it's stored in a 32 bit value. + * + * Returns the current time in the RAIL timebase (microseconds). It can be + * used to compare with packet timestamps or to schedule transmits. + */ +RAIL_Time_t RAIL_GetTime(void); + +/** + * Set the current RAIL time. + * + * @warning Use this API only for testing purposes or in + * very limited circumstances during RAIL Timer Synchronization. + * Undefined behavior can result by calling it in multiprotocol or + * when the radio is not idle or timed events are active. Applications + * using \ref RAIL_GetTime() may not be designed for discontinuous + * changes to the RAIL time base. + * + * @param[in] time Set the RAIL timebase to this value in microseconds. + * @return Status code indicating the success of the function call. + * + * Sets the current time in the RAIL timebase in microseconds. + */ +RAIL_Status_t RAIL_SetTime(RAIL_Time_t time); + +/** + * Blocking delay routine for a specified number of microseconds. + * + * @param[in] microseconds Delay duration in microseconds. + * @return Status code indicating success of the function call. + * + * Use this RAIL API only for short blocking delays because it has less overhead + * than calling RAIL_GetTime() in a loop. + * @note + * Passing large delay values may give unpredictable results or trigger + * the Watchdog reset. + * \n Also, this function will start the clocks required for the RAIL timebase if they + * are not running, except between \ref RAIL_Sleep() and \ref RAIL_Wake() + * where the timer must remain stopped. + * \n Interrupts are not disabled during the delay, so the delay may be longer if an + * interrupt extends beyond the delay duration. + */ +RAIL_Status_t RAIL_DelayUs(RAIL_Time_t microseconds); + +/** + * Schedule a timer to expire using the RAIL timebase. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] time The timer's expiration time in the RAIL timebase. + * @param[in] mode Indicates whether the time argument is an absolute + * RAIL time or relative to the current RAIL time. Specifying mode + * \ref RAIL_TIME_DISABLED is the same as calling RAIL_CancelTimer(). + * @param[in] cb The callback for RAIL to call when the timer expires. + * @return RAIL_STATUS_NO_ERROR on success and + * RAIL_STATUS_INVALID_PARAMETER if the timer can't be scheduled. + * + * Configures a timer to expire after a period in the RAIL timebase. + * This timer can be used to implement low-level protocol features. + * + * @warning Attempting to schedule the timer when it is + * still running from a previous request is bad practice, unless the cb + * callback is identical to that used in the previous request, in which case + * the timer is rescheduled to the new time. Note that if the original timer + * expires as it is being rescheduled, the callback may or may not occur. It + * is generally good practice to cancel a running timer before rescheduling + * it to minimize ambiguity. + */ +RAIL_Status_t RAIL_SetTimer(RAIL_Handle_t railHandle, + RAIL_Time_t time, + RAIL_TimeMode_t mode, + RAIL_TimerCallback_t cb); + +/** + * Return the absolute time that the RAIL timer was configured to expire. + * + * @param[in] railHandle A RAIL instance handle. + * @return The absolute time that this timer was set to expire. + * + * Provides the absolute time regardless of the \ref RAIL_TimeMode_t that + * was passed into \ref RAIL_SetTimer. Note that the time might be in the + * past if the timer has already expired. The return value is undefined if the + * timer was never set. + */ +RAIL_Time_t RAIL_GetTimer(RAIL_Handle_t railHandle); + +/** + * Stop the currently scheduled RAIL timer. + * + * @param[in] railHandle A RAIL instance handle. + * Cancels the timer. If this function is called before the timer expires, + * the cb callback specified in the earlier RAIL_SetTimer() call will never + * be called. + */ +void RAIL_CancelTimer(RAIL_Handle_t railHandle); + +/** + * Check whether the RAIL timer has expired. + * + * @param[in] railHandle A RAIL instance handle. + * @return True if the previously scheduled timer has expired and false + * otherwise. + * + * Polling with this function is an alternative to the callback. + */ +bool RAIL_IsTimerExpired(RAIL_Handle_t railHandle); + +/** + * Check whether the RAIL timer is currently running. + * + * @param[in] railHandle A RAIL instance handle. + * @return Returns true if the timer is running and false if + * the timer has expired or was never set. + */ +bool RAIL_IsTimerRunning(RAIL_Handle_t railHandle); + +/** + * Configure the RAIL software timer feature. + * + * @param[in] enable Enables/disables the RAIL multitimer. + * @return True if the multitimer was successfully enabled/disabled, false + * otherwise. + * + * Turning this on will add a software timer layer above the physical RAIL timer + * so that the user can have as many timers as desired. It is not necessary to + * call this function if the MultiTimer APIs are not used. + * + * @note This function must be called before calling \ref RAIL_SetMultiTimer. + * This function is a no-op on multiprotocol as this layer is already used + * under the hood. + * Do not call this function while the RAIL timer is running. + * Call \ref RAIL_IsTimerRunning before enabling/disabling the multitimer. + * If the multitimer is not needed, do not call this function to + * allow the multitimer code to be dead stripped. If the multitimer is + * enabled for use, the multitimer and timer APIs can both be used. + * However, no timer can be in use while this function is being called. + */ +bool RAIL_ConfigMultiTimer(bool enable); + +/** + * Start a multitimer instance. + * + * @note + * It is legal to start an already running timer. If this is done, the timer + * will first be stopped before the new configuration is applied. + * If expirationTime is 0, the callback is called + * immediately. + * + * @param[in,out] tmr A pointer to the timer instance to start. + * @param[in] expirationTime A time when the timer is set to expire. + * @param[in] expirationMode Select mode of expirationTime. See \ref + * RAIL_TimeMode_t. + * @param[in] callback A function to call on timer expiry. See \ref + * RAIL_MultiTimerCallback_t. NULL is a legal value. + * @param[in] cbArg An extra callback function parameter for the user application. + * + * @return + * \ref RAIL_STATUS_NO_ERROR on success.@n + * \ref RAIL_STATUS_INVALID_PARAMETER if tmr has an illegal value or if + * timeout is in the past. + */ +RAIL_Status_t RAIL_SetMultiTimer(RAIL_MultiTimer_t *tmr, + RAIL_Time_t expirationTime, + RAIL_TimeMode_t expirationMode, + RAIL_MultiTimerCallback_t callback, + void *cbArg); + +/** + * Stop the currently scheduled RAIL multitimer. + * + * @param[in,out] tmr A RAIL timer instance handle. + * + * @return + * true if the timer was successfully canceled. + * false if the timer was not running. + * + * Cancels the timer. If this function is called before the timer expires, + * the cb callback specified in the earlier RAIL_SetTimer() call will never + * be called. + */ +bool RAIL_CancelMultiTimer(RAIL_MultiTimer_t *tmr); + +/** + * Check if a given timer is running. + * + * @param[in] tmr A pointer to the timer structure to query. + * + * @return + * true if the timer is running. + * false if the timer is not running. + */ +bool RAIL_IsMultiTimerRunning(RAIL_MultiTimer_t *tmr); + +/** + * Check if a given timer has expired. + * + * @param[in] tmr A pointer to the timer structure to query. + * + * @return + * true if the timer is expired. + * false if the timer is running. + */ +bool RAIL_IsMultiTimerExpired(RAIL_MultiTimer_t *tmr); + +/** + * Get time left before a given timer instance expires. + * + * @param[in] tmr A pointer to the timer structure to query. + * @param[in] timeMode Indicates how the function provides the time + * remaining. By choosing \ref + * RAIL_TimeMode_t::RAIL_TIME_ABSOLUTE, the function returns the + * absolute expiration time, and by choosing \ref + * RAIL_TimeMode_t::RAIL_TIME_DELAY, the function returns the + * amount of time remaining before the timer's expiration. + * + * @return + * Time left expressed in RAIL's time units. + * 0 if the soft timer is not running or has already expired. + */ +RAIL_Time_t RAIL_GetMultiTimer(RAIL_MultiTimer_t *tmr, + RAIL_TimeMode_t timeMode); + +/** @} */ // end of group System_Timing + +/****************************************************************************** + * Sleep APIs + *****************************************************************************/ +/// @addtogroup Sleep +/// @brief These APIs help when putting the system to an EM2/EM3/EM4 sleep +/// states where the high frequency clock is disabled. +/// @{ +/// +/// The RAIL library has its own timebase and the ability to schedule operations +/// into the future. When going to any power mode that disables the HF clock +/// used for the radio (EM2/EM3/EM4), it is important that this timebase is +/// synchronized to a running LFCLK and the chip is set to wake up before the +/// next scheduled event. +/// If RAIL has not been configured to use the power manager, +/// \ref RAIL_Sleep and \ref RAIL_Wake must be called for performing this +/// synchronization. +/// If RAIL has been configured to use the power manager, +/// \ref RAIL_InitPowerManager, it will automatically perform timer +/// synchronization based on the selected \ref RAIL_TimerSyncConfig_t. Calls to +/// \ref RAIL_Sleep and \ref RAIL_Wake are unsupported in such a scenario. +/// +/// Following example code snippets demonstrate synchronizing the timebase +/// with and without timer synchronization: +/// +/// Sleep with timer synchronization: +/// +/// When sleeping with timer synchronization, you must first get the required +/// LFCLK up and running and leave it running across sleep so that the high +/// frequency clock that drives the RAIL time base can be synchronized to it. +/// The \ref RAIL_Sleep() API will also set up a wake event on the timer to wake +/// up wakeupTime before the next timer event so that it can run successfully. +/// See the \ref efr32_main sections on Low-Frequency Clocks and RAIL Timer +/// Synchronization for more setup details. +/// +/// This is useful when maintaining packet timestamps +/// across sleep or use the scheduled RX/TX APIs while sleeping in between. It +/// does take more time and code to do the synchronization. If your +/// application does not need this, it should be avoided. +/// +/// Example (without Power Manager): +/// @code{.c} +/// #include +/// #include +/// +/// extern RAIL_Handle_t railHandle; +/// // Wakeup time for your crystal/board/chip combination +/// extern uint32_t wakeupTime; +/// +/// void main(void) { +/// RAIL_Status_t status; +/// bool shouldSleep = false; +/// +/// // This function depends on your board/chip but it must enable the LFCLK +/// // you intend to use for RTCC sync before we configure sleep as that function +/// // will attempt to auto detect the clock. +/// BoardSetupLFCLK() +/// +/// // Configure sleep for timer synchronization +/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// +/// // Application main loop +/// while(1) { +/// // ... do normal app stuff and set shouldSleep to true when we want to +/// // sleep +/// if (shouldSleep) { +/// bool sleepAllowed = false; +/// +/// // Go critical to assess sleep decisions +/// CORE_ENTER_CRITICAL(); +/// if (RAIL_Sleep(wakeupTime, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { +/// printf("Error trying to go to sleep!"); +/// CORE_EXIT_CRITICAL(); +/// continue; +/// } +/// if (sleepAllowed) { +/// // Go to sleep +/// } +/// // Wakeup and sync the RAIL timebase back up +/// RAIL_Wake(0); +/// CORE_EXIT_CRITICAL(); +/// } +/// } +/// } +/// @endcode +/// +/// Example (with Power Manager): +/// @code{.c} +/// #include +/// #include +/// #include +/// +/// extern RAIL_Handle_t railHandle; +/// +/// void main(void) { +/// RAIL_Status_t status; +/// bool shouldSleep = false; +/// +/// // This function depends on your board/chip but it must enable the LFCLK +/// // you intend to use for RTCC sync before we configure sleep as that function +/// // will attempt to auto detect the clock. +/// BoardSetupLFCLK(); +/// // Configure sleep for timer synchronization +/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// // Initialize application-level power manager service +/// sl_power_manager_init(); +/// // Initialize RAIL library's use of the power manager +/// RAIL_InitPowerManager(); +/// +/// // Application main loop +/// while(1) { +/// // ... do normal app stuff and set shouldSleep to true when we want to +/// // sleep +/// if (shouldSleep) { +/// // Let the CPU go to sleep if the system allows it. +/// sl_power_manager_sleep(); +/// } +/// } +/// } +/// @endcode +/// +/// RAIL APIs such as, \ref RAIL_StartScheduledTx, \ref RAIL_ScheduleRx, +/// \ref RAIL_SetTimer, \ref RAIL_SetMultiTimer can be used to schedule periodic +/// wakeups to perform a scheduled operation. The call to +/// sl_power_manager_sleep() in the main loop ensures that the device sleeps +/// until the scheduled operation is due. +/// Upon completion, each instantaneous or scheduled RX/TX operation will +/// indicate radio busy to the power manager to allow the application to +/// service the RAIL event and perform subsequent operations before going to +/// sleep. Therefore, it is important that the application idle the radio by either +/// calling \ref RAIL_Idle or \ref RAIL_YieldRadio. +/// If the radio transitions to RX after an RX or TX operation, +/// always call \ref RAIL_Idle in order transition to a lower sleep state. +/// If the radio transitions to idle after an RX or TX operation, +/// \ref RAIL_YieldRadio should suffice in indicating to the power manager +/// that the radio is no longer busy and the device can sleep. +/// +/// The following example shows scheduling periodic TX on getting a TX completion +/// event: +/// @code{.c} +/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { +/// // Omitting other event handlers +/// if (events & RAIL_EVENTS_TX_COMPLETION) { +/// // Schedule the next TX. +/// RAIL_ScheduleTxConfig_t config = { +/// .when = (RAIL_Time_t)parameters->startTime, +/// .mode = (RAIL_TimeMode_t)parameters->startTimeMode +/// }; +/// (void)RAIL_StartScheduledTx(radio.handle, channel, 0, &config, NULL); +/// } +/// } +/// @endcode +/// +/// @note The above code assumes that RAIL automatic state transitions after TX +/// are idle. Set \ref RAIL_SetTxTransitions to ensure the right state +/// transitions. Radio must be idle for the device to enter EM2 or lower +/// energy mode. +/// +/// @note When using the power manager, usage of \ref RAIL_YieldRadio in +/// single protocol RAIL is similar to its usage in multiprotocol RAIL. +/// See \ref rail_radio_scheduler_yield for more details. +/// +/// @note Back to back scheduled operations do not require an explicit call to +/// \ref RAIL_YieldRadio if the radio transitions to idle. +/// +/// Sleep without timer synchronization: +/// +/// When sleeping without timer synchronization, you are free to enable only the +/// LFCLKs and wake sources required by the application. RAIL will not attempt +/// to configure any wake events and may miss anything that occurs over sleep. +/// +/// This is useful when your application does not care about +/// packet timestamps or scheduling operations accurately over sleep. +/// +/// Example (without Power Manager): +/// @code{.c} +/// #include +/// #include +/// +/// extern RAIL_Handle_t railHandle; +/// +/// void main(void) { +/// RAIL_Status_t status; +/// bool shouldSleep = false; +/// +/// // Configure sleep for timer synchronization +/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// +/// // Application main loop +/// while(1) { +/// // ... do normal app stuff and set shouldSleep to true when we want to +/// // sleep +/// if (shouldSleep) { +/// bool sleepAllowed = false; +/// uint32_t sleepTime = 0; +/// +/// // Go critical to assess sleep decisions +/// CORE_ENTER_CRITICAL(); +/// if (RAIL_Sleep(0, &sleepAllowed) != RAIL_STATUS_NO_ERROR) { +/// printf("Error trying to go to sleep!"); +/// CORE_EXIT_CRITICAL(); +/// continue; +/// } +/// if (sleepAllowed) { +/// // Go to sleep and optionally update sleepTime to the correct value +/// // in microseconds +/// } +/// // Wakeup and sync the RAIL timebase back up +/// RAIL_Wake(sleepTime); +/// CORE_EXIT_CRITICAL(); +/// } +/// } +/// } +/// @endcode +/// +/// Example (with Power Manager): +/// @code{.c} +/// #include +/// #include +/// #include +/// +/// extern RAIL_Handle_t railHandle; +/// +/// void main(void) { +/// RAIL_Status_t status; +/// bool shouldSleep = false; +/// +/// // This function depends on your board/chip but it must enable the LFCLK +/// // you intend to use for RTCC sync before we configure sleep as that function +/// // will attempt to auto detect the clock. +/// BoardSetupLFCLK(); +/// // Configure sleep for timer synchronization +/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// // Initialize application-level power manager service +/// sl_power_manager_init(); +/// // Initialize RAIL library's use of the power manager +/// RAIL_InitPowerManager(); +/// +/// // Application main loop +/// while(1) { +/// // ... do normal app stuff and set shouldSleep to true when we want to +/// // sleep +/// if (shouldSleep) { +/// // Let the CPU go to sleep if the system allows it. +/// sl_power_manager_sleep(); +/// } +/// } +/// } +/// @endcode +/** + * Configure RAIL timer synchronization. This function is optional to implement. + * + * @param[in,out] timerSyncConfig A pointer to the \ref RAIL_TimerSyncConfig_t + * structure containing the configuration parameters for timer sync. The + * \ref RAIL_TimerSyncConfig_t::sleep field is ignored in this call. + * + * This function is called during \ref RAIL_ConfigSleep to allow an application + * to configure the PRS and RTCC channels used for timer sync to values other + * than their defaults. The default channels are populated in timerSyncConfig and + * can be overwritten by the application. If this function is not implemented by the + * application, a default implementation from within the RAIL library will be used + * that simply maintains the default channel values in timerSyncConfig. + * + * If an unsupported channel is selected by the application, \ref RAIL_ConfigSleep + * will return \ref RAIL_STATUS_INVALID_PARAMETER. + * + * @code{.c} + * void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig) + * { + * timerSyncConfig->prsChannel = MY_TIMERSYNC_PRS_CHANNEL; + * timerSyncConfig->rtccChannel = MY_TIMERSYNC_RTCC_CHANNEL; + * } + * @endcode + */ +void RAILCb_ConfigSleepTimerSync(RAIL_TimerSyncConfig_t *timerSyncConfig); + +/** + * Initialize RAIL timer synchronization. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] sleepConfig A sleep configuration. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ConfigSleep(RAIL_Handle_t railHandle, + RAIL_SleepConfig_t sleepConfig); + +/** + * Initialize RAIL timer synchronization. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] syncConfig A pointer to the timer synchronization configuration. + * + * The default structure used to enable timer synchronization across sleep is + * \ref RAIL_TIMER_SYNC_DEFAULT. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ConfigSleepAlt(RAIL_Handle_t railHandle, + RAIL_TimerSyncConfig_t *syncConfig); + +/** + * Stop the RAIL timer and prepare RAIL for sleep. + * + * @param[in] wakeupProcessTime Time in microseconds that the application and + * hardware need to recover from sleep state. + * @param[out] deepSleepAllowed + * true - system can go to deep sleep. + * false - system should not go to deep sleep. Deep sleep should be blocked + * in this case. + * + * @return Status code indicating success of the function call. + * + * @warning The active RAIL configuration must be idle to enable sleep. + * + * @note This API must not be called if RAIL Power Manager is initialized. + */ +RAIL_Status_t RAIL_Sleep(uint16_t wakeupProcessTime, bool *deepSleepAllowed); + +/** + * Wake RAIL from sleep and restart the RAIL timer. + * + * @param[in] elapsedTime Add the sleep duration to the RAIL timer + * before restarting the RAIL timer. + * + * @return Status code indicating success of the function call. + * + * If the timer sync was enabled by \ref RAIL_ConfigSleep, synchronize the RAIL + * timer using an alternate timer. Otherwise, add elapsedTime to the RAIL + * timer. + * + * @note This API must not be called if RAIL Power Manager is initialized. + */ +RAIL_Status_t RAIL_Wake(RAIL_Time_t elapsedTime); + +/** + * Initialize RAIL Power Manager. + * + * @return Status code indicating success of the function call. + * + * @note Call this function only when the application is built + * and initialized with Power Manager plugin. + * RAIL will perform timer synchronization, upon transitioning from EM2 or lower + * to EM1 or higher energy mode or vice-versa, in the Power Manager EM + * transition callback. Since EM transition callbacks are not called in a + * deterministic order, it is suggested to not call any RAIL time dependent APIs + * in an EM transition callback. + */ +RAIL_Status_t RAIL_InitPowerManager(void); + +/** + * Stop the RAIL Power Manager. + * + * @return Status code indicating success of the function call. + * + * @note The active RAIL configuration must be idle to disable radio + * power manager and there should be no outstanding requirements by + * radio power manager. + */ +RAIL_Status_t RAIL_DeinitPowerManager(void); + +/** @} */ // end of group Sleep + +/****************************************************************************** + * Events + *****************************************************************************/ +/** + * @addtogroup Events + * @brief APIs related to events + * @{ + */ + +/** + * Configure radio events. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mask A bitmask of events to configure. + * @param[in] events A bitmask of events to trigger \ref RAIL_Config_t::eventsCallback + * For a full list of available callbacks, see + * RAIL_EVENT_* set of defines. + * @return Status code indicating success of the function call. + * + * Sets up which radio interrupts generate a RAIL event. The full list of + * options is in \ref RAIL_Events_t. + */ +RAIL_Status_t RAIL_ConfigEvents(RAIL_Handle_t railHandle, + RAIL_Events_t mask, + RAIL_Events_t events); + +/** @} */ // end of group Events + +/****************************************************************************** + * Data Management + *****************************************************************************/ +/// @addtogroup Data_Management Data Management +/// @brief Data management functions +/// +/// These functions allow the application to choose how data is presented to +/// the application. RAIL provides data in a packet-based method or in a +/// FIFO-based method. As originally conceived, +/// \ref RAIL_DataMethod_t::PACKET_MODE was designed for handling packets +/// that fit within RAIL's FIFOs while \ref RAIL_DataMethod_t::FIFO_MODE +/// was designed for handling packets larger than RAIL's FIFOs could hold. +/// Conceptually it is still useful to think of these modes this way, but +/// functionally their distinction has become blurred by improvements in +/// RAIL's flexibility -- applications now have much more control over both +/// receive and transmit FIFO sizes, and the FIFO-management and threshold +/// APIs and related events are no longer restricted to \ref +/// RAIL_DataMethod_t::FIFO_MODE operation but can be used in \ref +/// RAIL_DataMethod_t::PACKET_MODE too. +/// +/// The application can configure RAIL data management through +/// RAIL_ConfigData(). This function allows the application to specify the type +/// of radio data (\ref RAIL_TxDataSource_t and \ref RAIL_RxDataSource_t) and +/// the method of interacting with data (\ref RAIL_DataMethod_t). By default, +/// RAIL configures TX and RX both with packet data source and \ref +/// RAIL_DataMethod_t::PACKET_MODE. +/// +/// For transmit, \ref RAIL_DataMethod_t::PACKET_MODE and \ref +/// RAIL_DataMethod_t::FIFO_MODE are functionally the same: +/// - When not actively transmitting, load a packet's initial transmit +/// data using RAIL_WriteTxFifo() with reset set to true. Alternatively +/// this data copying can be avoided by changing the transmit FIFO to an +/// already-loaded section of memory with \ref RAIL_SetTxFifo(). +/// - When actively transmitting, load remaining transmit data with +/// RAIL_WriteTxFifo() with reset set to false. +/// - If transmit packets exceed the FIFO size, set the transmit FIFO +/// threshold through RAIL_SetTxFifoThreshold(). The \ref +/// RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY +/// will occur telling the application to load more TX packet data, if +/// needed, to prevent a \ref RAIL_EVENT_TX_UNDERFLOW event from occurring. +/// One can get how much space is available in the transmit FIFO for more +/// transmit data through RAIL_GetTxFifoSpaceAvailable(). +/// - After transmit completes, the transmit FIFO can be manually reset +/// with RAIL_ResetFifo(), but this should rarely be necessary. +/// +/// The transmit FIFO is specified by the application and its size is +/// the value returned from the most recent call to RAIL_SetTxFifo(). +/// The transmit FIFO is edge-based in that it only provides the \ref +/// RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event once when the threshold is crossed +/// in the emptying direction. +/// +/// For receive, the distinction between \ref RAIL_DataMethod_t::PACKET_MODE +/// and \ref RAIL_DataMethod_t::FIFO_MODE basically boils down to how +/// unsuccessfully-received packets are handled. In \ref +/// RAIL_DataMethod_t::PACKET_MODE, data from such packets is automatically +/// rolled back as if the packet was never received, while in \ref +/// RAIL_DataMethod_t::FIFO_MODE, rollback does not occur putting more onus +/// on the application to deal with that data. +/// +/// In receive \ref RAIL_DataMethod_t::PACKET_MODE data management: +/// - Packet lengths are determined from the Radio Configurator configuration +/// and can be read out at the end using \ref RAIL_GetRxPacketInfo(). +/// - Received packet data is made available on successful packet completion +/// via \ref RAIL_Config_t::eventsCallback with \ref +/// RAIL_EVENT_RX_PACKET_RECEIVED which can then use RAIL_GetRxPacketInfo() +/// and RAIL_GetRxPacketDetailsAlt() to access packet information and +/// RAIL_PeekRxPacket() to access packet data. +/// - Filtered, Aborted, or FrameError received packet data is automatically +/// rolled back (dropped) without the application needing to worry about +/// consuming it. +/// The application can choose to not even be bothered with the events +/// related to such packets: \ref RAIL_EVENT_RX_ADDRESS_FILTERED, +/// \ref RAIL_EVENT_RX_PACKET_ABORTED, or \ref RAIL_EVENT_RX_FRAME_ERROR. +/// +/// In receive \ref RAIL_DataMethod_t::FIFO_MODE data management: +/// - Packet Lengths are determined from the Radio Configurator configuration +/// or by application knowledge of packet payload structure. +/// - Received data can be retrieved prior to packet completion through +/// RAIL_ReadRxFifo() and is never rolled back on Filtered, Aborted, or +/// FrameError packets. The application should enable and handle these +/// events so it can flush any packet data it's already retrieved. +/// - After packet completion, remaining packet data for Filtered, Aborted, +/// or FrameError packets remains in the FIFO and the appropriate event is +/// triggered to the user. This data may be consumed in the callback unlike +/// in packet mode where it is automatically rolled back. At the end of the +/// callback all remaining data in the FIFO will be cleaned up as usual. +/// Keep in mind that RAIL_GetRxPacketDetailsAlt() provides packet detailed +/// information only for successfully received packets. +/// +/// Common receive data management features: +/// - Set the receive FIFO threshold through RAIL_SetRxFifoThreshold(). The +/// \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL +/// will occur telling the application to consume some RX packet data to +/// prevent a \ref RAIL_EVENT_RX_FIFO_OVERFLOW event from occurring. +/// - Get receive FIFO count information through +/// RAIL_GetRxPacketInfo(\ref RAIL_RX_PACKET_HANDLE_NEWEST) +/// (or RAIL_GetRxFifoBytesAvailable()). +/// - After receive completes and all its data has been consumed, the receive +/// FIFO can be manually reset with RAIL_ResetFifo(), though this should +/// rarely be necessary and should only be done with the radio idle. +/// +/// When trying to determine an appropriate threshold, the application needs +/// to know the size of each FIFO. The default receive FIFO is internal to RAIL +/// with a size of 512 bytes. This can be changed, however, using +/// \ref RAIL_SetRxFifo() and the default may be removed entirely by calling +/// this from the RAILCb_SetupRxFifo() callback. The receive FIFO event is +/// level-based in that the \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will +/// constantly pend if the threshold is exceeded. This normally means that +/// inside this event's callback, the application should empty enough of the FIFO +/// to go under the threshold. To defer reading the FIFO to main context, the +/// application can disable or re-enable the receive FIFO threshold event using +/// RAIL_ConfigEvents() with the mask \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL. +/// +/// The receive FIFO can store multiple packets and processing of a packet can +/// be deferred from the RAIL event callback to main-loop processing +/// by using RAIL_HoldRxPacket() in the event callback and +/// RAIL_ReleaseRxPacket() in the main-loop. +/// On some platforms, the receive FIFO is supplemented by an internal +/// fixed-size packet metadata FIFO that limits the number of packets +/// RAIL and applications can hold onto for deferred processing. +/// See chip-specific documentation, such as \ref efr32_main, for more +/// information. Note that when using multiprotocol the receive FIFO is reset +/// prior to a protocol switch so held packets will be lost if not processed +/// before then. +/// +/// While \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL occurs solely based on the +/// state of the receive FIFO used for packet data, both +/// \ref RAIL_EVENT_RX_FIFO_FULL and \ref RAIL_EVENT_RX_FIFO_OVERFLOW +/// can occur coincident with packet completion when either that or the +/// internal packet metadata FIFO fills or overflows. +/// \ref RAIL_EVENT_RX_FIFO_FULL informs the application it should +/// immediately process and free up the oldest packets/data to make room +/// for new packets/data, reducing the possibility of packet/data loss +/// and \ref RAIL_EVENT_RX_FIFO_OVERFLOW. +/// +/// Before a packet is fully received you can always use +/// RAIL_PeekRxPacket() to look at the contents. In FIFO mode, you may also +/// consume its data with \ref RAIL_ReadRxFifo(). Remember that none of these +/// APIs will read across a packet boundary (even in FIFO mode) so you will +/// need to handle each received packet individually. +/// +/// While RAIL defaults to \ref RAIL_DataMethod_t::PACKET_MODE, the +/// application can explicitly initialize RAIL for \ref +/// RAIL_DataMethod_t::PACKET_MODE in the following manner: +/// @code{.c} +/// extern RAIL_Handle_t railHandle; +/// static const RAIL_DataConfig_t railDataConfig = { +/// .txSource = TX_PACKET_DATA, +/// .rxSource = RX_PACKET_DATA, +/// .txMethod = PACKET_MODE, +/// .rxMethod = PACKET_MODE, +/// }; +/// +/// status = RAIL_ConfigData(railHandle, &railDataConfig); +/// +/// // Events that can occur in Packet Mode: +/// // RAIL_EVENT_TX_PACKET_SENT +/// // RAIL_EVENT_RX_PACKET_RECEIVED +/// // and optionally (packet data automatically dropped): +/// // RAIL_EVENT_RX_ADDRESS_FILTERED +/// // RAIL_EVENT_RX_PACKET_ABORTED +/// // RAIL_EVENT_RX_FRAME_ERROR +/// // and if enabled: +/// // RAIL_EVENT_TX_UNDERFLOW +/// // RAIL_EVENT_TXACK_UNDERFLOW +/// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY +/// // RAIL_EVENT_RX_FIFO_ALMOST_FULL +/// @endcode +/// +/// Initializing RAIL for \ref RAIL_DataMethod_t::FIFO_MODE requires a few +/// more function calls: +/// @code{.c} +/// extern RAIL_Handle_t railHandle; +/// static const RAIL_DataConfig_t railDataConfig = { +/// .txSource = TX_PACKET_DATA, +/// .rxSource = RX_PACKET_DATA, +/// .txMethod = FIFO_MODE, +/// .rxMethod = FIFO_MODE, +/// }; +/// +/// status = RAIL_ConfigData(railHandle, &railDataConfig); +/// +/// // Gets the size of the FIFOs. +/// // Assume that the transmit and receive FIFOs are the same size +/// uint16_t fifoSize = RAIL_GetTxFifoSpaceAvailable(railHandle); +/// +/// // Sets the transmit and receive FIFO thresholds. +/// // For this example, set the threshold in the middle of each FIFO. +/// RAIL_SetRxFifoThreshold(railHandle, fifoSize / 2); +/// RAIL_SetTxFifoThreshold(railHandle, fifoSize / 2); +/// +/// // Events that can occur in FIFO mode: +/// // RAIL_EVENT_TX_FIFO_ALMOST_EMPTY +/// // RAIL_EVENT_TX_UNDERFLOW +/// // RAIL_EVENT_TXACK_UNDERFLOW +/// // RAIL_EVENT_TX_PACKET_SENT +/// // RAIL_EVENT_RX_FIFO_ALMOST_FULL +/// // RAIL_EVENT_RX_FIFO_OVERFLOW +/// // RAIL_EVENT_RX_ADDRESS_FILTERED +/// // RAIL_EVENT_RX_PACKET_ABORTED +/// // RAIL_EVENT_RX_FRAME_ERROR +/// // RAIL_EVENT_RX_PACKET_RECEIVED +/// @endcode +/// +/// On receive, an application can use a different \ref RAIL_RxDataSource_t that +/// is only compatible with \ref RAIL_DataMethod_t::FIFO_MODE. All that differs +/// from the FIFO mode example above is the RAIL_DataConfig_t::rxSource setting. +/// IQ data samples are taken at the hardware's oversample rate and the amount +/// of data can easily overwhelm the CPU processing time. The sample rate +/// depends on the chosen PHY, as determined by the data rate and the decimation +/// chain. It is not recommended to use the IQ data source with sample +/// rates above 300 k samples/second because the CPU might not be able to keep up +/// with the data stream. Depending on the application and the needed CPU +/// bandwidth, slower data rates may be required. On EFR32xG22 and later +/// platforms, it is recommended to reset the RX buffer before initiating a +/// receive for all modes except \ref RAIL_RxDataSource_t::RX_PACKET_DATA since +/// the RX buffer has to be 32-bit aligned. If the buffer is not reset +/// but is 32-bit aligned, capture is performed on the remaining space available. +/// If the buffer is not reset and is not 32-bit aligned, then +/// RAIL_ConfigData() returns \ref RAIL_STATUS_INVALID_STATE. +/// @code{.c} +/// // Reset RX buffer (EFR32xG22 and later platforms) +/// RAIL_ResetFifo(railHandle, false, true); +/// +/// // IQ data is provided into the receive FIFO. +/// static const RAIL_DataConfig_t railDataConfig = { +/// .txSource = TX_PACKET_DATA, +/// .rxSource = RX_IQDATA_FILTLSB, +/// .txMethod = FIFO_MODE, +/// .rxMethod = FIFO_MODE, +/// }; +/// +/// // IQ data comes in the following format when reading out of the FIFO: +/// //------------------------------------ +/// // I[LSB] | I[MSB] | Q[LSB] | Q[MSB] | +/// //------------------------------------ +/// @endcode +/// +/// @{ + +/** + * RAIL data management configuration + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] dataConfig RAIL data configuration structure. + * @return Status code indicating success of the function call. + * + * This function configures how RAIL manages data. The application can + * configure RAIL to receive data in a packet-based or FIFO-based manner. + * \ref RAIL_DataMethod_t::FIFO_MODE is necessary to receive packets larger + * than the radio's receive FIFO. It is also required for receive data + * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. + * + * Generally with \ref RAIL_DataMethod_t::FIFO_MODE, the application sets + * appropriate FIFO thresholds via RAIL_SetTxFifoThreshold() and + * RAIL_SetRxFifoThreshold() and then enables and handles the + * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event callback (to feed more packet + * data via RAIL_WriteTxFifo() before the FIFO underflows) and the \ref + * RAIL_EVENT_RX_FIFO_ALMOST_FULL event callback (to consume packet data + * via RAIL_ReadRxFifo() before the receive FIFO overflows). + * + * When configuring TX for \ref RAIL_DataMethod_t::FIFO_MODE, this + * function resets the transmit FIFO. When configuring TX or RX for + * \ref RAIL_DataMethod_t::PACKET_MODE, this function will reset + * the corresponding FIFO thresholds such that they won't trigger the + * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL or \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY + * events. + * + * When \ref RAIL_DataConfig_t::rxMethod is set to \ref + * RAIL_DataMethod_t::FIFO_MODE, the radio won't drop packet data of + * aborted or CRC error packets, but will present it to the application + * to deal with accordingly. On completion of erroneous packets, the + * \ref RAIL_Config_t::eventsCallback with \ref RAIL_EVENT_RX_PACKET_ABORTED, + * \ref RAIL_EVENT_RX_FRAME_ERROR, or \ref RAIL_EVENT_RX_ADDRESS_FILTERED will + * tell the application it can drop any data it read via RAIL_ReadRxFifo() during reception. + * For CRC error packets when the \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS + * RX option is in effect, the application should check for that from the + * \ref RAIL_RxPacketStatus_t obtained by calling RAIL_GetRxPacketInfo(). + * RAIL will automatically flush any remaining packet data after reporting + * one of these packet completion events or the application can explicitly + * flush it by calling RAIL_ReleaseRxPacket(). + * + * When \ref RAIL_DataConfig_t::rxMethod is set to \ref + * RAIL_DataMethod_t::PACKET_MODE, the radio will roll back (drop) all packet + * data associated with aborted packets including those with CRC errors + * (unless configured to ignore CRC errors via the + * \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS RX option). The application will + * never have to deal with packet data from these packets. + * In either mode, the application can set RX options as needed. + * + * When \ref RAIL_DataConfig_t::rxSource is set to a value other than + * \ref RX_PACKET_DATA and \ref RAIL_Config_t::eventsCallback + * \ref RAIL_EVENT_RX_FIFO_OVERFLOW is enabled RX will be terminated + * if a RX FIFO overflow occurs. If \ref RAIL_EVENT_RX_FIFO_OVERFLOW + * is not enabled, data will be discarded until the overflow condition + * is resolved. To continue capturing data RX must be restarted using + * \ref RAIL_StartRx(). + * + */ +RAIL_Status_t RAIL_ConfigData(RAIL_Handle_t railHandle, + const RAIL_DataConfig_t *dataConfig); + +/** + * Write data to the transmit FIFO previously established by RAIL_SetTxFifo(). + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] dataPtr An application-provided pointer to transmit data. + * @param[in] writeLength A number of bytes to write to the transmit FIFO. + * @param[in] reset If true, resets transmit FIFO before writing the data. + * @return The number of bytes written to the transmit FIFO. + * + * This function reads data from the provided dataPtr and writes it to the transmit + * FIFO that was previously established by RAIL_SetTxFifo(). + * If the requested writeLength exceeds the current number of bytes open + * in the transmit FIFO, the function only writes until the transmit FIFO + * is full. The function returns the number of bytes written to the transmit + * FIFO or returns zero if railHandle is NULL or if the transmit FIFO is full. + * + * @note The protocol's packet configuration, as set up by the radio + * configurator or via RAIL_SetFixedLength(), determines how many + * bytes of data are consumed from the transmit FIFO for a successful transmit + * operation, not the writeLength value passed in. If not enough data has + * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will + * occur. If too much data is put into the transmit FIFO, the extra data will + * either become the first bytes + * sent in a subsequent packet, or will be thrown away if the FIFO gets + * reset prior to the next transmit. In general, the proper number of + * packet bytes to put into the transmit FIFO are all payload bytes except + * for any CRC bytes, which the packet configuration causes to be sent + * automatically. + * + * @note This function does not create a critical section but, depending on the + * application, a critical section could be appropriate. + */ +uint16_t RAIL_WriteTxFifo(RAIL_Handle_t railHandle, + const uint8_t *dataPtr, + uint16_t writeLength, + bool reset); + +/** + * Set the address of the transmit FIFO, a circular buffer used for TX data. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] addr An appropriately-aligned (see below) pointer to a read-write memory + * location in RAM used as the transmit FIFO. This memory must persist until the next + * call to this function or \ref RAIL_SetTxFifoAlt. + * @param[in] initLength A number of initial bytes already in the transmit FIFO. + * @param[in] size A desired size of the transmit FIFO in bytes. + * @return Returns the FIFO size in bytes, 0 if an error occurs. + * + * This function sets the memory location for the transmit FIFO. \ref RAIL_SetTxFifo or + * \ref RAIL_SetTxFifoAlt must be called at least once before any transmit operations occur. + * + * FIFO size can be determined by the return value of this function. The + * chosen size is determined based on the available FIFO sizes supported by the + * hardware. Similarly, some hardware has stricter FIFO alignment requirements; + * 32-bit alignment provides the maximum portability across all RAIL platforms. + * For more on supported FIFO sizes and alignments, see chip-specific + * documentation, such as \ref efr32_main. The returned FIFO size will be the + * closest allowed size less than or equal to the passed in size parameter, + * unless the size parameter is smaller than the minimum FIFO size, in that case + * 0 is returned. If the initLength parameter is larger than the returned + * size, the FIFO will be filled up to its size. + * + * A user may write to the custom memory location directly before calling this + * function, or use \ref RAIL_WriteTxFifo to write to the memory location after + * calling this function. Users must specify the initLength for + * previously-written memory to be set in the transmit FIFO. + * + * This function reserves the block of RAM starting at addr with a length of the + * returned FIFO size, which is used internally as a circular buffer for the + * transmit FIFO. It must be able to hold the entire FIFO size. The caller must + * guarantee that the custom FIFO remains intact and unchanged (except via calls + * to \ref RAIL_WriteTxFifo) until the next call to this function. + * + * @note The protocol's packet configuration, as set up by the radio + * configurator or via RAIL_SetFixedLength(), determines how many + * bytes of data are consumed from the transmit FIFO for a successful transmit + * operation, not the initLength value passed in. If not enough data has + * been put into the transmit FIFO, a \ref RAIL_EVENT_TX_UNDERFLOW event will + * occur. If too much data is put into the transmit FIFO, the extra data + * will either become the first bytes + * sent in a subsequent packet, or will be thrown away if the FIFO gets + * reset prior to the next transmit. In general, the proper number of + * packet bytes to put into the transmit FIFO are all payload bytes except + * for any CRC bytes which the packet configuration causes to be sent + * automatically. + */ +uint16_t RAIL_SetTxFifo(RAIL_Handle_t railHandle, + uint8_t *addr, + uint16_t initLength, + uint16_t size); + +/** + * Set the address of the transmit FIFO, a circular buffer used for TX data which + * can start at offset distance from the FIFO base address. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] addr An appropriately-aligned (see \ref RAIL_SetTxFifo description) + * pointer to a read-write memory location in RAM used as the transmit FIFO. This memory + * must persist until the next call to this function or \ref RAIL_SetTxFifo. + * @param[in] startOffset A number of bytes defining the start position of the TX data + * from the transmit FIFO base address, only valid if initLength is not 0. + * @param[in] initLength The number of valid bytes already in the transmit FIFO after startOffset. + * @param[in] size A desired size of the transmit FIFO in bytes. + * @return Returns the FIFO size in bytes, 0 if an error occurs. + * + * This function is similar to \ref RAIL_SetTxFifo except a startOffset can be specified + * to indicate where the transmit packet data starts. This allows an application to + * place unaligned initial packet data within the aligned transmit FIFO (initLength > 0). + * Specifying a startOffset will not reduce the FIFO threshold or affect + * \ref RAIL_GetTxFifoSpaceAvailable(). + * \ref RAIL_SetTxFifo or \ref RAIL_SetTxFifoAlt must be called at least once before any transmit + * operations occur. + * FIFO size handling is quite same as \ref RAIL_SetTxFifo. Only difference is that if the + * initLength plus startOffset parameters are larger than the returned size, the FIFO + * will be filled up to its size from startOffset. + * Note that the startOffset is essentially forgotten after the next transmit -- + * i.e. it applies onto to the next transmit operation, and is not re-established when + * the transmit FIFO is reset. + */ +uint16_t RAIL_SetTxFifoAlt(RAIL_Handle_t railHandle, + uint8_t *addr, + uint16_t startOffset, + uint16_t initLength, + uint16_t size); +/** + * Set the address of the receive FIFO, a circular buffer used for RX data. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] addr A pointer to a read-write memory location in RAM used as + * the receive FIFO. This memory must persist until the next call to this + * function. + * @param[in,out] size A desired size of the receive FIFO in bytes. This will + * be populated with the actual size during the function call. + * @return Status code indicating success of the function call. + * + * This function sets the memory location for the receive FIFO. It + * must be called at least once before any receive operations occur. + * + * @note After it is called, any prior receive FIFO is orphaned. To avoid + * orphaning the default internal 512-byte receive FIFO so it does + * not unnecessarily consume RAM resources in your application, + * implement \ref RAILCb_SetupRxFifo() to call this function. + * + * FIFO size can be determined by the return value of this function. The + * chosen size is determined based on the available FIFO sizes supported by the + * hardware. Similarly, some hardware has stricter FIFO alignment requirements; + * 32-bit alignment provides the maximum portability across all RAIL platforms. + * For more on supported FIFO sizes and alignments, see chip-specific + * documentation, such as \ref efr32_main. The returned FIFO size will be the + * closest allowed size less than or equal to the passed in size parameter, + * unless the size parameter is smaller than the minimum FIFO size. + * + * This function reserves the block of RAM starting at addr with a length + * of size, which is used internally as a circular buffer for the receive FIFO. + * It must be able to hold the entire FIFO size. The caller must guarantee that + * the custom FIFO remains intact and unchanged (except via incoming packet data + * being written) until the next call to this function. + * + * In multiprotocol, RAIL currently shares one receive FIFO across all + * protocols. This function will return \ref RAIL_STATUS_INVALID_STATE if the + * requested \ref RAIL_Handle_t is not active. + */ +RAIL_Status_t RAIL_SetRxFifo(RAIL_Handle_t railHandle, + uint8_t *addr, + uint16_t *size); + +/// Set up the receive FIFO to use. This function is optional to implement. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @return Status code indicating success of the function call. +/// +/// This function is called during the \ref RAIL_Init process to set up the FIFO +/// to use for received packets. If not implemented by the application, +/// a default implementation from within the RAIL library will be used to +/// initialize an internal default 512-byte receive FIFO. +/// +/// If this function returns an error, the RAIL_Init process will fail. +/// +/// During this function, the application should generally call +/// \ref RAIL_SetRxFifo. If that does not happen, the application needs to +/// set up the receive FIFO via a call to \ref RAIL_SetRxFifo before attempting +/// to receive any packets. An example implementation may look like the following: +/// @code{.c} +/// #define RX_FIFO_SIZE 1024 +/// static uint8_t rxFifo[RX_FIFO_SIZE]; +/// +/// RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle) +/// { +/// uint16_t rxFifoSize = RX_FIFO_SIZE; +/// RAIL_Status_t status = RAIL_SetRxFifo(railHandle, &rxFifo[0], &rxFifoSize); +/// if (rxFifoSize != RX_FIFO_SIZE) { +/// // We set up an incorrect FIFO size +/// return RAIL_STATUS_INVALID_PARAMETER; +/// } +/// if (status == RAIL_STATUS_INVALID_STATE) { +/// // Allow failures due to multiprotocol +/// return RAIL_STATUS_NO_ERROR; +/// } +/// return status; +/// } +/// @endcode +RAIL_Status_t RAILCb_SetupRxFifo(RAIL_Handle_t railHandle); + +/** + * Read packet data from RAIL's internal receive FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] dataPtr An application-provided pointer to store data. + * If NULL, the data is thrown away rather than copied out. + * @param[in] readLength A number of packet bytes to read from the FIFO. + * @return The number of packet bytes read from the receive FIFO. + * + * This function reads packet data from the head of receive FIFO and + * writes it to the provided dataPtr. It does not permit reading more + * data than is available in the FIFO, nor does it permit reading more + * data than remains in the oldest unreleased packet. + * + * Because this function does not have a critical section, use it + * only in one context or make sure function calls are protected to prevent + * buffer corruption. + * + * @warning This function is intended for use only with \ref + * RAIL_DataMethod_t::FIFO_MODE and should never be called in \ref + * RAIL_DataMethod_t::PACKET_MODE where it could lead to receive FIFO + * corruption. + * + * @note When reading data from an arriving packet that is not yet complete, + * keep in mind its data is highly suspect because it has not yet passed + * any CRC integrity checking. Also note that the packet could be aborted, + * canceled, or fail momentarily, invalidating its data in Packet mode. + * Furthermore, there is a small chance towards the end of packet reception + * that the receive FIFO could include not only packet data received so far, + * but also some raw radio-appended info detail bytes that RAIL's + * packet-completion processing will subsequently deal with. It's up to the + * application to know its packet format well enough to avoid reading this + * info because it will corrupt the packet's details and possibly corrupt the + * receive FIFO. + */ +uint16_t RAIL_ReadRxFifo(RAIL_Handle_t railHandle, + uint8_t *dataPtr, + uint16_t readLength); + +/** + * Configure the RAIL transmit FIFO almost empty threshold. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] txThreshold The threshold below which the + * \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event will fire. + * @return Configured transmit FIFO threshold value. + * + * This function configures the threshold for the transmit FIFO. When the + * number of bytes in the transmit FIFO falls below the configured threshold, + * \ref RAIL_Config_t::eventsCallback will fire with \ref + * RAIL_EVENT_TX_FIFO_ALMOST_EMPTY set. + * The txThreshold value should be smaller than or equal to the transmit + * FIFO size; higher values will be pegged to the FIFO size. + * A value of 0 or \ref RAIL_FIFO_THRESHOLD_DISABLED will disable the + * threshold, returning \ref RAIL_FIFO_THRESHOLD_DISABLED. + */ +uint16_t RAIL_SetTxFifoThreshold(RAIL_Handle_t railHandle, + uint16_t txThreshold); + +/** + * Configure the RAIL receive FIFO almost full threshold. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] rxThreshold The threshold above which the + * \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL event will fire. + * @return Configured receive FIFO threshold value. + * + * This function configures the threshold for the receive FIFO. When the + * number of bytes of packet data in the receive FIFO exceeds the + * configured threshold, \ref RAIL_Config_t::eventsCallback will keep + * firing with \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL set as long as the + * number of bytes in the receive FIFO exceeds the configured threshold + * value. The rxThreshold value should be smaller than the receive FIFO + * size; anything else, including a value of + * \ref RAIL_FIFO_THRESHOLD_DISABLED, will disable the threshold, + * returning \ref RAIL_FIFO_THRESHOLD_DISABLED. + * + * @note To avoid sticking in the event handler (even in idle state): + * 1. Disable the event (via the config events API or the + * \ref RAIL_FIFO_THRESHOLD_DISABLED parameter) + * 2. Increase FIFO threshold + * 3. Read the FIFO (that's not an option in + * \ref RAIL_DataMethod_t::PACKET_MODE) in the event handler + */ +uint16_t RAIL_SetRxFifoThreshold(RAIL_Handle_t railHandle, + uint16_t rxThreshold); + +/** + * Get the RAIL transmit FIFO almost empty threshold value. + * + * @param[in] railHandle A RAIL instance handle. + * @return Configured TX Threshold value. + * + * Retrieves the configured TX threshold value. + */ +uint16_t RAIL_GetTxFifoThreshold(RAIL_Handle_t railHandle); + +/** + * Get the RAIL receive FIFO almost full threshold value. + * + * @param[in] railHandle A RAIL instance handle. + * @return Configured RX Threshold value. + * + * Retrieves the configured RX threshold value. + */ +uint16_t RAIL_GetRxFifoThreshold(RAIL_Handle_t railHandle); + +/** + * Reset the RAIL transmit and/or receive FIFOs. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] txFifo If true, reset the transmit FIFO. + * @param[in] rxFifo If true, reset the receive FIFO. + * + * This function can reset each FIFO independently. + * The application should not reset the receive FIFO while receiving a frame, + * nor should it reset the transmit FIFO while transmitting a frame. + */ +void RAIL_ResetFifo(RAIL_Handle_t railHandle, bool txFifo, bool rxFifo); + +/** + * Get the number of bytes used in the receive FIFO. + * Only use this function in RX \ref RAIL_DataMethod_t::FIFO_MODE. + * Apps should use RAIL_GetRxPacketInfo() instead. + * + * @param[in] railHandle A RAIL instance handle. + * @return Number of bytes used in the receive FIFO. + * + * This function indicates how much packet-related data exists in the receive FIFO + * that could be read. + * + * @note The number of bytes returned may not just reflect the current + * packet's data but could also include raw appended info bytes added + * after successful packet reception and bytes from subsequently received + * packets. It is up to the app to never try to consume more than the + * packet's actual data when using the value returned here in a subsequent + * call to RAIL_ReadRxFifo(), otherwise the receive FIFO will be corrupted. + */ +uint16_t RAIL_GetRxFifoBytesAvailable(RAIL_Handle_t railHandle); + +/** + * Get the number of bytes unused in the transmit FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @return Number of bytes unused in the transmit FIFO. + * + * This function indicates how much space is available in the transmit FIFO for writing + * additional packet data. + */ +uint16_t RAIL_GetTxFifoSpaceAvailable(RAIL_Handle_t railHandle); + +/** @} */ // end of group Data_Management + +/****************************************************************************** + * State Transitions + *****************************************************************************/ +/** + * @addtogroup State_Transitions State Transitions + * @{ + */ + +/** + * Configure RAIL automatic state transitions after RX. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] transitions The state transitions to apply after reception. + * @return Status code indicating success of the function call. + * + * This function fails if unsupported transitions are passed in or if the + * radio is currently in the RX state. Success can transition to TX, RX, or + * IDLE, while error can transition to RX or IDLE. The timings of state + * transitions from the RX state are not guaranteed when packets are longer + * than 16 seconds on-air. + */ +RAIL_Status_t RAIL_SetRxTransitions(RAIL_Handle_t railHandle, + const RAIL_StateTransitions_t *transitions); + +/** + * Get the current RAIL automatic state transitions after RX. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] transitions The state transitions that apply after receive. + * @return Status code indicating a success of the function call. + * + * Retrieves the current state transitions after RX and stores them in the + * transitions argument. + */ +RAIL_Status_t RAIL_GetRxTransitions(RAIL_Handle_t railHandle, + RAIL_StateTransitions_t *transitions); + +/** + * Configure RAIL automatic state transitions after TX. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] transitions The state transitions to apply after transmission. + * @return Status code indicating a success of the function call. + * + * This function fails if unsupported transitions are passed in or if the + * radio is currently in the TX state. Success and error can each transition + * to RX or IDLE. For the ability to run repeated transmits, see + * \ref RAIL_SetNextTxRepeat. + */ +RAIL_Status_t RAIL_SetTxTransitions(RAIL_Handle_t railHandle, + const RAIL_StateTransitions_t *transitions); + +/** + * Get the current RAIL automatic state transitions after TX. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] transitions The state transitions that apply after transmission. + * @return Status code indicating a success of the function call. + * + * Retrieves the current state transitions after TX and stores them in the + * transitions argument. + */ +RAIL_Status_t RAIL_GetTxTransitions(RAIL_Handle_t railHandle, + RAIL_StateTransitions_t *transitions); + +/** + * Set up automatic repeated transmits after the next transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] repeatConfig The configuration structure for repeated transmits. + * @return Status code indicating a success of the function call. + * + * Repeated transmits will occur after an application-initiated transmit caused + * by calling one of the \ref Packet_TX APIs. The repetition will only occur + * after the first application-initiated transmit after this function is + * called. Future repeated transmits must be requested by calling this function + * again. + * + * Each repeated transmit that occurs will have full \ref PTI information, and + * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. + * + * If a TX error occurs during the repetition, the process will abort and the + * TX error transition from \ref RAIL_SetTxTransitions will be used. If the + * repetition completes successfully, then the TX success transition from + * \ref RAIL_SetTxTransitions will be used. + * + * Use \ref RAIL_GetTxPacketsRemaining() if need to know how many transmit + * completion events are expected before the repeating sequence is done, or + * how many were not performed due to a transmit error. + * + * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending + * repeated transmits. The state will also be cleared by another call to this + * function. A DMP switch will clear this + * state only if the initial transmit triggering the repeated transmits has + * started. + * + * One can change the repeated transmit configuration by re-calling + * this function with new parameters as long as that occurs prior to + * calling a \ref Packet_TX API. Passing a \ref + * RAIL_TxRepeatConfig_t::iterations count of 0 will prevent the next + * transmit from repeating. + * + * The application is responsible for populating the transmit data to be used + * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. + * Data will be transmitted from the Transmit FIFO. If the Transmit FIFO does + * not have sufficient data to transmit, a TX error will be caused and a \ref + * RAIL_EVENT_TX_UNDERFLOW will occur. In order to avoid an underflow, the + * application should queue data to be transmitted as early as possible. + * Consider using \ref RAIL_TX_OPTION_RESEND if the same packet data is to + * be repeated: then the Transmit FIFO only needs to be set/written once. + * + * Do not call this function after starting a transmit operation via a \ref + * Packet_TX API call or + * before processing the final transmit completion event of a prior transmit. + * This function will fail to (re)configure the repetition if a transmit of any + * kind is ongoing, including during the time between an initial transmit and + * the end of a previously-configured repetition. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_TX_TO_TX or the runtime + * call \ref RAIL_SupportsTxToTx() to check whether the platform supports + * this feature. + */ +RAIL_Status_t RAIL_SetNextTxRepeat(RAIL_Handle_t railHandle, + const RAIL_TxRepeatConfig_t *repeatConfig); + +/** + * Get the number of transmits remaining in a repeat operation. + * Must only be called from within event callback context when handling + * one of the \ref RAIL_EVENTS_TX_COMPLETION events. + * + * @param[in] railHandle A RAIL instance handle. + * @return transmits remaining as described below. + * + * If the TX completion event is \ref RAIL_EVENT_TX_PACKET_SENT the + * returned value indicates how many more such events are expected + * before the repeat transmit operation is done. Due to interrupt + * latency and timing, this may be an overcount if greater than 0 + * but is guaranteed to be accurate when 0. + * + * If the TX completion event is an error, the returned value indicates + * the number of requested transmits that were not performed. For + * \ref RAIL_EVENT_TX_ABORTED and \ref RAIL_EVENT_TX_UNDERFLOW the + * count does not include the failing transmit itself. For the other + * errors where a transmit never started or was blocked, the count + * would include the failing transmit, which may be one higher than + * the configured \ref RAIL_TxRepeatConfig_t::iterations if it was + * the original transmit that was blocked. + * + * If an infinite repeat was configured, this will return \ref + * RAIL_TX_REPEAT_INFINITE_ITERATIONS. + */ +uint16_t RAIL_GetTxPacketsRemaining(RAIL_Handle_t railHandle); + +/** + * Configure RAIL automatic state transition timing. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] timings The timings used to configure the RAIL state + * machine. This structure is overwritten with the actual times that were + * set, if an input timing is invalid. + * @return Status code indicating a success of the function call. + * + * The timings given are close to the actual transition time. However, + * a still uncharacterized software overhead occurs. Also, timings are not + * always adhered to when using an automatic transition after an error, due to + * the cleanup required to recover from the error. + */ +RAIL_Status_t RAIL_SetStateTiming(RAIL_Handle_t railHandle, + RAIL_StateTiming_t *timings); + +/** + * Place the radio into an idle state. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode The method for shutting down the radio. + * @param[in] wait Whether this function should wait for the radio to reach + * idle before returning. + * + * This function is used to remove the radio from TX and RX states. How these + * states are left is defined by the mode parameter. + * + * In multiprotocol, this API will also cause the radio to be yielded so that + * other tasks can be run. See \ref rail_radio_scheduler_yield for more details. + */ +void RAIL_Idle(RAIL_Handle_t railHandle, + RAIL_IdleMode_t mode, + bool wait); + +/** + * Get the current radio state. + * + * @param[in] railHandle A RAIL instance handle. + * @return An enumeration for the current radio state. + * + * Returns the state of the radio as a bitmask containing: + * \ref RAIL_RF_STATE_IDLE, \ref RAIL_RF_STATE_RX, \ref RAIL_RF_STATE_TX, + * and \ref RAIL_RF_STATE_ACTIVE. \ref RAIL_RF_STATE_IDLE, \ref + * RAIL_RF_STATE_RX, and \ref RAIL_RF_STATE_TX bits are mutually exclusive. + * The radio can transition through intermediate states, + * which are not reported but are instead considered part of the state + * most closely associated. For example, when the radio is warming up + * or shutting down the transmitter or receiver, this function returns + * \ref RAIL_RF_STATE_TX or \ref RAIL_RF_STATE_RX, respectively. + * When transitioning directly from RX to TX or vice-versa, this function + * returns the earlier state. + * + * @note For a more detailed radio state, see \ref RAIL_GetRadioStateDetail + */ +RAIL_RadioState_t RAIL_GetRadioState(RAIL_Handle_t railHandle); + +/** + * Get the detailed current radio state. + * + * @param[in] railHandle A RAIL instance handle. + * @return An enumeration for the current detailed radio state. + * + * Returns the state of the radio as a bitmask. The three core radio states + * IDLE, RX, and TX are represented by mutually exclusive bits \ref + * RAIL_RF_STATE_DETAIL_IDLE_STATE, \ref RAIL_RF_STATE_DETAIL_RX_STATE, and + * \ref RAIL_RF_STATE_DETAIL_TX_STATE respectively. If the radio is + * transitioning between these three states, the returned bitmask will have + * \ref RAIL_RF_STATE_DETAIL_TRANSITION set along with a bit corresponding to + * the destination core radio state. If, while in the receive state, the radio + * is actively receiving a packet, \ref RAIL_RF_STATE_DETAIL_ACTIVE will be set; + * otherwise, this bit will be clear. If frame detection is disabled, \ref + * RAIL_RF_STATE_DETAIL_NO_FRAMES in the returned state bitmask will be set; + * otherwise, this bit will be clear. If the radio is performing an LBT/CSMA + * operation (e.g., a backoff period) \ref RAIL_RF_STATE_DETAIL_LBT in the + * returned state bitmask will be set; otherwise, this bit will be clear. + * + * For the most part, the more detailed radio states returned by this API + * correspond to radio states returned by \ref RAIL_GetRadioState as follows: + * + * \ref RAIL_RadioStateDetail_t \ref RAIL_RadioState_t + * RAIL_RF_STATE_DETAIL_INACTIVE RAIL_RF_STATE_INACTIVE + * RAIL_RF_STATE_DETAIL_IDLE_STATE + * | RAIL_STATE_DETAIL_TRANSITION If RX overflow or leaving RX unforced: + * RAIL_RF_STATE_RX + * Else if leaving TX unforced: + * RAIL_RF_STATE_TX + * Else: + * RAIL_RF_STATE_IDLE + * RAIL_RF_STATE_DETAIL_IDLE_STATE RAIL_RF_STATE_IDLE + * RAIL_RF_STATE_DETAIL_IDLE_STATE + * | RAIL_STATE_DETAIL_LBT RAIL_RF_STATE_TX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_STATE_DETAIL_TRANSITION If leaving TX: + * RAIL_RF_STATE_TX + * Else: + * RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_RF_STATE_DETAIL_TRANSITION + * | RAIL_RF_STATE_DETAIL_NO_FRAMES If leaving TX: + * RAIL_RF_STATE_TX + * Else: + * RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_RF_STATE_DETAIL_NO_FRAMES RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_RF_STATE_DETAIL_LBT RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_RF_STATE_DETAIL_NO_FRAMES + * | RAIL_RF_STATE_DETAIL_LBT RAIL_RF_STATE_RX + * RAIL_RF_STATE_DETAIL_RX_STATE + * | RAIL_RF_STATE_DETAIL_ACTIVE RAIL_RF_STATE_RX_ACTIVE + * RAIL_RF_STATE_DETAIL_TX_STATE + * | RAIL_RF_STATE_TRANSITION If leaving RX: + * RAIL_RF_STATE_RX + * Else: + * RAIL_RF_STATE_TX + * RAIL_RF_STATE_DETAIL_TX_STATE + * | RAIL_RF_STATE_ACTIVE RAIL_RF_STATE_TX_ACTIVE + */ +RAIL_RadioStateDetail_t RAIL_GetRadioStateDetail(RAIL_Handle_t railHandle); + +/** + * Enable/disable caching of synth calibration value. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable A booloean to enable or disable caching of synth calibration. + * @return Status code indicating success of the function call. + * + * Once enabled, the sequencer will start caching synth calibration values for + * channels and apply them instead of performing calibration on every state + * transition and channel change. + * This will increase the transition time for the first time calibration is + * performed. Subsequent state transitions will be faster. The cache size is 2. + * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING internally uses this feature + * and there is no need to enable/disable it. This function returns + * \ref RAIL_STATUS_INVALID_STATE if we try to disable it while + * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is enabled. + * + * @note This function will improve the minimum timings that can be achieved in + * \ref RAIL_StateTiming_t::idleToRx, \ref RAIL_StateTiming_t::idleToTx, + * \ref RAIL_StateTiming_t::rxToTx, \ref RAIL_StateTiming_t::txToRx and + * \ref RAIL_StateTiming_t::txToTx. A call to \ref RAIL_SetStateTiming() + * is needed to achieve lower transition times. + * + * @note On a protocol switch the cache is cleared, so it is not suitable for + * applications where a protocol switch happens frequently, like with + * Dynamic Multiprotocol. + */ +RAIL_Status_t RAIL_EnableCacheSynthCal(RAIL_Handle_t railHandle, bool enable); + +/** @} */ // end of group State_Transitions + +/****************************************************************************** + * Transmit + *****************************************************************************/ +/** + * @addtogroup Transmit + * @brief APIs related to transmitting data packets + * @{ + */ + +/// @addtogroup PA Power Amplifier (PA) +/// @brief APIs for interacting with one of the on chip PAs. +/// +/// These APIs let you configure the on-chip PA to get the appropriate output +/// power. +/// +/// These are the function types: +/// 1) Configuration functions: These functions set and get configuration +/// for the PA. In this case, "configuration" refers to a) indicating +/// which PA to use, b) the voltage supplied by your board to the PA, +/// and c) the ramp time over which to ramp the PA up to its full +/// power. +/// 2) Power-setting functions: These functions consume the actual +/// values written to the PA registers and write them appropriately. +/// These values are referred to as "(raw) power levels". The range of +/// acceptable values for these functions depends on which PA is +/// currently active. The higher the power level set, the higher +/// the dBm power output by the chip. However, the mapping +/// between dBm and these power levels can vary greatly between +/// modules/boards. +/// 3) Conversion functions: These functions convert +/// between the "power levels" discussed previously and the +/// dBm values output by the chip. Continue reading for more information +/// about unit conversion. +/// +/// The accuracy of the chip output power is application-specific. +/// For some protocols or channels, the protocol itself or +/// legal limitations require applications to know exactly what power +/// they're transmitting at, in dBm. Other applications do not have +/// these restrictions, and users determine power level(s) +/// that fit their criteria for the trade-off between radio range and +/// power savings, regardless of what dBm power that maps to. +/// +/// \ref RAIL_ConvertRawToDbm and \ref RAIL_ConvertDbmToRaw, +/// which convert between the dBm power and the raw power levels, +/// provide a solution that fits all these applications. +/// The levels of customization are outlined below: +/// 1) No customization needed: for a given dBm value, the result +/// of RAIL_ConvertDbmToRaw provides an appropriate +/// raw power level that, when written to the registers via +/// RAIL_SetPowerLevel, causes the chip to output at that +/// dBm power. In this case, no action is needed by the user, +/// the WEAK versions of the conversion functions can be used +/// and the default include paths in pa_conversions_efr32.h can +/// be used. +/// 2) The mapping of power level to dBm is not ideal, but the +/// level of precision is sufficient: In pa_conversions_efr32.c, +/// the WEAK versions of the conversion functions work by using +/// 8-segment piecewise linear curves to convert between dBm +/// and power levels for PA's with hundreds of power levels +/// and simple mapping tables for use with PA's with only a few +/// levels. If this method is sufficiently precise, but the mapping +/// between power levels and dBm is incorrect, +/// copy pa_curves_efr32.h into a new file, updating the segments +/// to form a better fit (_DCDC_CURVES or _VBAT_CURVES defines) and +/// then add the RAIL_PA_CURVES define to your build with the path +/// to the new file. +/// 3) A different level of precision is needed and the fit is bad: +/// If the piecewise-linear line segment fit is not appropriate for +/// your solution, the functions in pa_conversions_efr32.c can be +/// totally rewritten, as long as RAIL_ConvertDbmToRaw and +/// RAIL_ConvertRawToDbm have the same signatures. It is completely +/// acceptable to re-write these in a way that makes the +/// pa_curves_efr32.h and pa_curve_types_efr32.h files referenced in +/// pa_conversions_efr32.h unnecessary. Those files are needed solely +/// for the provided conversion methods. +/// 4) dBm values are not necessary: If the application does not require +/// dBm values at all, overwrite +/// RAIL_ConvertDbmToRaw and RAIL_ConvertRawToDbm with smaller functions +/// (i.e., return 0 or whatever was input). These functions are called +/// from within the RAIL library, so they can never be deadstripped, +/// but making them as small as possible is the best way to reduce code +/// size. From there, call RAIL_SetTxPower, without +/// converting from a dBm value. To stop the library from coercing the +/// power based on channels, overwrite RAIL_ConvertRawToDbm +/// to always return 0 and overwrite RAIL_ConvertDbmToRaw to +/// always return 255. +/// +/// The following is example code that shows how to initialize your PA +/// @code{.c} +/// +/// #include "pa_conversions_efr32.h" +/// +/// // A helper macro to declare all the curve structures used by the provided +/// // conversion functions. +/// RAIL_DECLARE_TX_POWER_VBAT_CURVES(piecewiseSegments, curvesSg, curves24Hp, curves24Lp); +/// +/// // Puts the variables declared above into the appropriate structure. +/// RAIL_TxPowerCurvesConfig_t txPowerCurvesConfig = { curves24Hp, curvesSg, curves24Lp, piecewiseSegments }; +/// +/// // Saves those curves +/// // to be referenced when the conversion functions are called. +/// RAIL_InitTxPowerCurves(&txPowerCurvesConfig); +/// +/// // Declares the structure used to configure the PA. +/// RAIL_TxPowerConfig_t txPowerConfig = { RAIL_TX_POWER_MODE_2P4_HP, 3300, 10 }; +/// +/// // Initializes the PA. Here, it is assumed that 'railHandle' is a valid RAIL_Handle_t +/// // that has already been initialized. +/// RAIL_ConfigTxPower(railHandle, &txPowerConfig); +/// +/// // Picks a dBm power to use: 100 deci-dBm = 10 dBm. See docs on RAIL_TxPower_t. +/// RAIL_TxPower_t power = 100; +/// +/// // Gets the config written by RAIL_ConfigTxPower to confirm what was actually set. +/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); +/// +/// // RAIL_ConvertDbmToRaw is the default weak version, +/// // or the customer version, if overwritten. +/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, +/// txPowerConfig.mode, +/// power); +/// +/// // Writes the result of the conversion to the PA power registers in terms +/// // of raw power levels. +/// RAIL_SetTxPower(railHandle, powerLevel); +/// @endcode +/// +/// @note All lines following "RAIL_TxPower_t power = 100;" can be +/// replaced with the provided utility function, \ref RAIL_SetTxPowerDbm. +/// However, the full example here was provided for clarity. See the +/// documentation on \ref RAIL_SetTxPowerDbm for more details. +/// +/// @{ + +/** + * Initialize TX power settings. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config An instance which contains desired initial settings + * for the TX amplifier. + * @return RAIL_Status_t indicating success or an error. + * + * These settings include the selection between the multiple TX amplifiers, + * voltage supplied to the TX power amplifier, and ramp times. This must + * be called before any transmit occurs or \ref RAIL_SetTxPower is called. + * While this function should always be called during initialization, + * it can also be called any time if these settings need to change to adapt + * to a different application/protocol. This API also resets TX power to + * \ref RAIL_TX_POWER_LEVEL_INVALID, so \ref RAIL_SetTxPower must be called + * afterwards. + * + * At times, certain combinations of configurations cannot be achieved. + * This API attempts to get as close as possible to the requested settings. The + * following "RAIL_Get..." API can be used to determine what values were set. A + * change in \ref RAIL_TxPowerConfig_t::rampTime may affect the minimum timings + * that can be achieved in \ref RAIL_StateTiming_t::idleToTx and + * \ref RAIL_StateTiming_t::rxToTx. Call \ref RAIL_SetStateTiming() again to + * check whether these times have changed. + */ +RAIL_Status_t RAIL_ConfigTxPower(RAIL_Handle_t railHandle, + const RAIL_TxPowerConfig_t *config); + +/** + * Get the TX power settings currently used in the amplifier. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] config A pointer to memory allocated to hold the current TxPower + * configuration structure. A NULL configuration will produce undefined + * behavior. + * @return RAIL status variable indicating whether or not the get was + * successful. + * + * Note that this API does not return the current TX power, which is separately + * managed by the \ref RAIL_GetTxPower / \ref RAIL_SetTxPower APIs. Use this API + * to determine which values were set as a result of + * \ref RAIL_ConfigTxPower. + */ +RAIL_Status_t RAIL_GetTxPowerConfig(RAIL_Handle_t railHandle, + RAIL_TxPowerConfig_t *config); + +/** + * Set the TX power in units of raw units (see \ref rail_chip_specific.h for + * value ranges). + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] powerLevel Power in chip-specific \ref RAIL_TxPowerLevel_t units. + * @return RAIL_Status_t indicating success or an error. + * + * To convert between decibels and the integer values that the + * registers take, call \ref RAIL_ConvertDbmToRaw. + * A weak version of this function, which works well with our boards is provided. However, + * customers using a custom board need to characterize + * chip operation on that board and override the function to convert + * appropriately from the desired dB values to raw integer values. + * + * Depending on the configuration used in \ref RAIL_ConfigTxPower, not all + * power levels are achievable. This API will get as close as possible to + * the desired power without exceeding it, and calling \ref RAIL_GetTxPower is + * the only way to know the exact value written. + * + * Calling this function before configuring the PA (i.e., before a successful + * call to \ref RAIL_ConfigTxPower) will return an error. + */ +RAIL_Status_t RAIL_SetTxPower(RAIL_Handle_t railHandle, + RAIL_TxPowerLevel_t powerLevel); + +/** + * Return the current power setting of the PA. + * + * @param[in] railHandle A RAIL instance handle. + * @return The chip-specific \ref RAIL_TxPowerLevel_t value of the current + * transmit power. + * + * This API returns the raw value that was set by \ref RAIL_SetTxPower. + * A weak version of \ref RAIL_ConvertRawToDbm that works + * with our boards to convert the raw values into actual output dBm values is provided. + * However, customers using a custom board need to + * re-characterize the relationship between raw and decibel values and rewrite + * the provided function. + * + * Calling this function before configuring the PA (i.e., before a successful + * call to \ref RAIL_ConfigTxPower) will return an error + * (RAIL_TX_POWER_LEVEL_INVALID). + */ +RAIL_TxPowerLevel_t RAIL_GetTxPower(RAIL_Handle_t railHandle); + +/** + * Convert raw values written to registers to decibel value (in units of + * deci-dBm). + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode PA mode for which to convert. + * @param[in] powerLevel A raw amplifier register value to be converted to + * deci-dBm. + * @return raw amplifier values converted to units of deci-dBm. + * + * A weak version of this function is provided that is tuned + * to provide accurate values for our boards. For a + * custom board, the relationship between what is written to the TX amplifier + * and the actual output power should be re-characterized and implemented in an + * overriding version of \ref RAIL_ConvertRawToDbm. For minimum code size and + * best speed, use only raw values with the TxPower API and override this + * function with a smaller function. In the weak version provided with the RAIL + * library, railHandle is only used to indicate to the user from where the + * function was called, so it is OK to use either a real protocol handle, or one + * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. + * + * Although the definitions of this function may change, the signature + * must be as declared here. + */ +RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPowerLevel_t powerLevel); + +/** + * Convert the desired decibel value (in units of deci-dBm) + * to raw integer values used by the TX amplifier registers. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode PA mode for which to do the conversion. + * @param[in] power Desired dBm values in units of deci-dBm. + * @return deci-dBm value converted to a raw + * integer value that can be used directly with \ref RAIL_SetTxPower. + * + * A weak version of this function is provided that is tuned + * to provide accurate values for our boards. For a + * custom board, the relationship between what is written to the TX amplifier + * and the actual output power should be characterized and implemented in an + * overriding version of \ref RAIL_ConvertDbmToRaw. For minimum code size and + * best speed use only raw values with the TxPower API and override this + * function with a smaller function. In the weak version provided with the RAIL + * library, railHandle is only used to indicate to the user from where the + * function was called, so it is OK to use either a real protocol handle, or one + * of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. + * + * Although the definitions of this function may change, the signature + * must be as declared here. + * + * @note This function is called from within the RAIL library for + * comparison between channel limitations and current power. It will + * throw an assert if you haven't called RAIL_InitTxPowerCurves + * which initializes the mappings between raw power levels and + * actual dBm powers. To avoid the assert, ensure that the + * maxPower of all channel configuration entries is \ref RAIL_TX_POWER_MAX + * or above, or override this function to always return 255. + */ +RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t power); + +struct RAIL_TxPowerCurvesConfigAlt; +/// Verify the TX Power Curves on modules. +/// +/// @param[in] config TX Power Curves to use on this module. +/// +/// This function only needs to be called when using a module and has no +/// effect otherwise. Transmit will not work before this function is called. +void RAIL_VerifyTxPowerCurves(const struct RAIL_TxPowerCurvesConfigAlt *config); + +/// Set the TX power in terms of deci-dBm instead of raw power level. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @param[in] power A desired deci-dBm power to be set. +/// @return RAIL Status variable indicate whether setting the +/// power was successful. +/// +/// This is a utility function for user convenience. Normally, to set TX +/// power in dBm, do the following: +/// +/// @code{.c} +/// RAIL_TxPower_t power = 100; // 100 deci-dBm, 10 dBm +/// RAIL_TxPowerConfig_t txPowerConfig; +/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); +/// // RAIL_ConvertDbmToRaw will be the weak version provided by Silicon Labs +/// // by default, or the customer version, if overwritten. +/// RAIL_TxPowerLevel_t powerLevel = RAIL_ConvertDbmToRaw(railHandle, +/// txPowerConfig.mode, +/// power); +/// RAIL_SetTxPower(railHandle, powerLevel); +/// @endcode +/// +/// This function wraps all those calls in a single function with power passed in +/// as a parameter. +/// +RAIL_Status_t RAIL_SetTxPowerDbm(RAIL_Handle_t railHandle, + RAIL_TxPower_t power); + +/// Get the TX power in terms of deci-dBm instead of raw power level. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @return The current output power in deci-dBm. +/// +/// This is a utility function for user convenience. Normally, to get TX +/// power in dBm, do the following: +/// +/// @code{.c} +/// RAIL_TxPowerLevel_t powerLevel = RAIL_GetTxPower(railHandle); +/// RAIL_TxPowerConfig_t txPowerConfig; +/// RAIL_GetTxPowerConfig(railHandle, &txPowerConfig); +/// // RAIL_ConvertRawToDbm will be the weak version provided by Silicon Labs +/// // by default, or the customer version, if overwritten. +/// RAIL_TxPower_t power = RAIL_ConvertRawToDbm(railHandle, +/// txPowerConfig.mode, +/// powerLevel); +/// return power; +/// @endcode +/// +/// This function wraps all those calls in a single function with power returned +/// as the result. +/// +RAIL_TxPower_t RAIL_GetTxPowerDbm(RAIL_Handle_t railHandle); + +/** + * Get the TX PA power setting table and related values. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode PA mode for which to get the powersetting table + * @param[out] minPower A pointer to a \ref RAIL_TxPower_t + * @param[out] maxPower A pointer to a \ref RAIL_TxPower_t + * @param[out] step In deci-dBm increments. A pointer to a \ref RAIL_TxPowerLevel_t + * @return Power setting table start address. When NULL is returned all out params + * above won't be set. + * + * The number of entries in the table can be calculated based on the minPower, maxPower, + * and step parameters. For example, for minPower = 115 (11.5 dBm), maxPower = 300 (30 dBm), + * and step = 1, the number of entries in table would be 186 + */ +const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, + RAIL_TxPower_t *minPower, RAIL_TxPower_t *maxPower, + RAIL_TxPowerLevel_t *step); + +/** + * Set the TX PA power setting used to configure the PA hardware for the PA output + * power determined by \ref RAIL_SetTxPowerDbm(). + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] paPowerSetting The desired PA power setting. + * @param[in] minPowerDbm The minimum power in dBm that the PA can output. + * @param[in] maxPowerDbm The maximum power in dBm that the PA can output. + * @param[in] currentPowerDbm The corresponding output power in dBm for this power setting. + * @return RAIL Status variable indicate whether setting the + * PA power setting was successful. + */ +RAIL_Status_t RAIL_SetPaPowerSetting(RAIL_Handle_t railHandle, + RAIL_PaPowerSetting_t paPowerSetting, + RAIL_TxPower_t minPowerDbm, + RAIL_TxPower_t maxPowerDbm, + RAIL_TxPower_t currentPowerDbm); + +/** + * Get the TX PA power setting, which is used to configure power configurations + * when the dBm to paPowerSetting mapping table mode is used. + * + * @param[in] railHandle A RAIL instance handle. + * @return The current PA power setting. + */ +RAIL_PaPowerSetting_t RAIL_GetPaPowerSetting(RAIL_Handle_t railHandle); + +/** + * Enable automatic switching between PAs internally to the RAIL library. + * While PA Automode is enabled, the PA will be chosen and set automatically whenever + * \ref RAIL_SetTxPowerDbm is called or whenever powers are coerced automatically, + * internally to the RAIL library during a channel change. While PA Auto Mode + * is enabled, users cannot call \ref RAIL_ConfigTxPower or + * \ref RAIL_SetTxPower. When entering auto mode, \ref RAIL_SetTxPowerDbm must + * be called to specify the desired power. When leaving auto mode, + * \ref RAIL_ConfigTxPower as well as one of \ref RAIL_SetTxPower or + * \ref RAIL_SetTxPowerDbm must be called to re-specify the desired PA and power + * level combination. + * + * @note: Power conversion curves must be initialized before calling this function. + * That is, \ref RAIL_ConvertDbmToRaw and \ref RAIL_ConvertRawToDbm most both be + * able to operate properly to ensure that PA Auto Mode functions correctly. + * See the PA Conversions plugin or AN1127 for more details. + * + * @param[in] railHandle A real (not generic) RAIL instance handle. + * @param[in] enable Enable or disable PA Auto Mode. + * @return Status parameter indicating success of function call. + */ +RAIL_Status_t RAIL_EnablePaAutoMode(RAIL_Handle_t railHandle, bool enable); + +/** + * Query status of PA Auto Mode. + * + * @param[in] railHandle A real (not generic) RAIL instance handle on which to + * query PA Auto Mode status. + * @return Indicator of whether Auto Mode is enabled (true) or not (false). + */ +bool RAIL_IsPaAutoModeEnabled(RAIL_Handle_t railHandle); + +/** + * Callback that decides which PA and power level should be + * used while in PA auto mode. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] power Pointer to the dBm output power (in deci-dBm, 10*dBm) + * being requested. The value this points to when the function returns + * will be applied to the radio. + * @param[out] mode Pointer to the \ref RAIL_TxPowerMode_t to be used to + * achieve the requested power. The value this points to when the function + * returns will be applied to the radio. + * @param[in] chCfgEntry Pointer to a \ref RAIL_ChannelConfigEntry_t. + * While switching channels, it will be the entry RAIL is switch *to*, + * during a call to \ref RAIL_SetTxPowerDbm, it will be the entry + * RAIL is *already on*. Can be NULL if a channel configuration + * was not set or no valid channels are present. + * @return Return status indicating result of function call. If this + * is anything except \ref RAIL_STATUS_NO_ERROR, neither PA's nor their + * powers will be configured automatically. + * + * Whatever values mode and powerLevel point to when this function return + * will be applied to the PA hardware and used for transmits. + * @note The mode and power level provided by this function depends on the + * RAIL_PaAutoModeConfig provided for the chip. The RAIL_PaAutoModeConfig + * definition for a chip should tend to all the bands supported by the chip and + * cover the full range of power to find a valid entry for requested power + * for a specific band. + */ +RAIL_Status_t RAILCb_PaAutoModeDecision(RAIL_Handle_t railHandle, + RAIL_TxPower_t *power, + RAIL_TxPowerMode_t *mode, + const RAIL_ChannelConfigEntry_t *chCfgEntry); + +/** @} */ // end of group PA + +/// @addtogroup Packet_TX Packet Transmit +/// @brief APIs which initiate a packet transmission in RAIL +/// +/// When using any of these functions, the data to be transmitted must have been +/// previously written to the Transmit FIFO via \ref RAIL_SetTxFifo() and/or +/// \ref RAIL_WriteTxFifo(). +/// +/// @{ + +/** + * Start a transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * The transmit process will begin immediately or as soon as a packet being + * received has finished. The data to be transmitted must have been previously + * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, any ongoing packet reception is aborted. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Schedule sending a packet. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] config A pointer to the \ref RAIL_ScheduleTxConfig_t + * structure containing when the transmit should occur. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, a transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * The transmit process will begin at the scheduled time. The data to be + * transmitted must have been previously established via \ref RAIL_SetTxFifo() + * and/or \ref RAIL_WriteTxFifo(). + * The time (in microseconds) and whether that time is absolute or + * relative is specified using the \ref RAIL_ScheduleTxConfig_t structure. + * What to do if a scheduled transmit fires in + * the middle of receiving a packet is also specified in this structure. + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, the channel is changed immediately and + * will abort any ongoing packet reception. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartScheduledTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_ScheduleTxConfig_t *config, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Start a transmit using CSMA. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] csmaConfig A pointer to the RAIL_CsmaConfig_t structure + * describing the CSMA parameters to use for this transmit. + * \n In multiprotocol this must point to global or heap storage that remains + * valid after the API returns until the transmit is actually started. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, a transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * Perform the Carrier Sense Multiple Access (CSMA) algorithm, and if + * the channel is deemed clear (RSSI below the specified threshold), it will + * commence transmission. The data to be transmitted must have been previously + * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). + * Packets can be received during CSMA backoff periods if receive is active + * throughout the CSMA process. This will happen either by starting the CSMA + * process while receive is already active, or if the csmaBackoff time in + * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by + * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the + * idleToRx time, receive will only be active during CSMA's clear channel + * assessments. + * + * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback + * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents + * of the transmit FIFO remain intact. + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, the channel is changed immediately and any ongoing + * packet reception is aborted. + * + * Returns an error if a scheduled RX is still in progress. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartCcaCsmaTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_CsmaConfig_t *csmaConfig, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Start a transmit using LBT. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] lbtConfig A pointer to the RAIL_LbtConfig_t structure + * describing the LBT parameters to use for this transmit. + * \n In multiprotocol this must point to global or heap storage that remains + * valid after the API returns until the transmit is actually started. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, a transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * Performs the Listen Before Talk (LBT) algorithm, and if the channel + * is deemed clear (RSSI below the specified threshold), it will commence + * transmission. The data to be transmitted must have been previously established + * via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). + * Packets can be received during LBT backoff periods if receive is active + * throughout the LBT process. This will happen either by starting the LBT + * process while receive is already active, or if the lbtBackoff time in + * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by + * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the + * idleToRx time, receive will only be active during LBT's clear channel + * assessments. + * + * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback occurs with + * \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents + * of the transmit FIFO remain intact. + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, the channel is changed immediately and any ongoing + * packet reception is aborted. + * + * Returns an error if a scheduled RX is still in progress. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartCcaLbtTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_LbtConfig_t *lbtConfig, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Schedule a transmit using CSMA. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] scheduleTxConfig A pointer to the \ref RAIL_ScheduleTxConfig_t + * structure describing the CSMA parameters to use for this transmit. + * @param[in] csmaConfig A pointer to the \ref RAIL_CsmaConfig_t structure + * describing the CSMA parameters to use for this transmit. + * \n In multiprotocol this must point to global or heap storage that remains + * valid after the API returns until the transmit is actually started. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, a transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * Internally, the RAIL library needs a PRS channel for this feature. + * It will allocate an available PRS channel to use and hold onto that + * channel for future use. If no PRS channel is available, the function + * returns with \ref RAIL_STATUS_INVALID_CALL. + * + * Perform the Carrier Sense Multiple Access (CSMA) algorithm at the scheduled time, + * and if the channel is deemed clear (RSSI below the specified threshold), it will + * commence transmission. The data to be transmitted must have been previously + * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). + * Packets can be received during CSMA backoff periods if receive is active + * throughout the CSMA process. This will happen either by starting the CSMA + * process while receive is already active, or if the csmaBackoff time in + * the \ref RAIL_CsmaConfig_t is less than the idleToRx time (set by + * RAIL_SetStateTiming()). If the csmaBackoff time is greater than the + * idleToRx time, receive will only be active during CSMA's clear channel + * assessments. + * + * If the CSMA algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback + * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents + * of the transmit FIFO remain intact. + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, the channel is changed immediately and any ongoing + * packet reception is aborted. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartScheduledCcaCsmaTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_ScheduleTxConfig_t *scheduleTxConfig, + const RAIL_CsmaConfig_t *csmaConfig, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Schedule a transmit using LBT. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel Define the channel to transmit on. + * @param[in] options TX options to be applied to this transmit only. + * @param[in] scheduleTxConfig A pointer to the \ref RAIL_ScheduleTxConfig_t + * structure describing the CSMA parameters to use for this transmit. + * @param[in] lbtConfig A pointer to the \ref RAIL_LbtConfig_t structure + * describing the LBT parameters to use for this transmit. + * \n In multiprotocol this must point to global or heap storage that remains + * valid after the API returns until the transmit is actually started. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this transmit appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. If successfully + * initiated, a transmit completion or failure will be reported by a later + * \ref RAIL_Config_t::eventsCallback with the appropriate \ref RAIL_Events_t. + * + * Internally, the RAIL library needs a PRS channel for this feature. + * It will allocate an available PRS channel to use and hold onto that + * channel for future use. If no PRS channel is available, the function + * returns with \ref RAIL_STATUS_INVALID_CALL. + * + * Performs the Listen Before Talk (LBT) algorithm at the scheduled time, + * and if the channel is deemed clear (RSSI below the specified threshold), it will + * commence transmission. The data to be transmitted must have been previously + * established via \ref RAIL_SetTxFifo() and/or \ref RAIL_WriteTxFifo(). + * Packets can be received during LBT backoff periods if receive is active + * throughout the LBT process. This will happen either by starting the LBT + * process while receive is already active, or if the lbtBackoff time in + * the \ref RAIL_LbtConfig_t is less than the idleToRx time (set by + * RAIL_SetStateTiming()). If the lbtBackoff time is greater than the + * idleToRx time, receive will only be active during LBT's clear channel + * assessments. + * + * If the LBT algorithm deems the channel busy, the \ref RAIL_Config_t::eventsCallback + * occurs with \ref RAIL_EVENT_TX_CHANNEL_BUSY, and the contents of the transmit + * FIFO remain intact. + * + * Returns an error if a previous transmit is still in progress. + * If changing channels, the channel is changed immediately and any ongoing + * packet reception is aborted. + * + * In multiprotocol, ensure that the radio is properly yielded after this + * operation completes. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_StartScheduledCcaLbtTx(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_TxOptions_t options, + const RAIL_ScheduleTxConfig_t *scheduleTxConfig, + const RAIL_LbtConfig_t *lbtConfig, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** @} */ // end of group Packet_TX + +/** + * Stop an active or pending transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode Configure the types of transmits to stop. + * @return \ref RAIL_STATUS_NO_ERROR if the transmit was successfully + * stopped or \ref RAIL_STATUS_INVALID_STATE if there is no transmit + * operation to stop. + * + * @note When mode includes \ref RAIL_STOP_MODE_ACTIVE, this can also stop + * an active auto-ACK transmit. When an active transmit is stopped, \ref + * RAIL_EVENT_TX_ABORTED or \ref RAIL_EVENT_TXACK_ABORTED should occur. + * When mode includes \ref RAIL_STOP_MODE_PENDING this can also stop + * a \ref RAIL_TX_OPTION_CCA_ONLY transmit operation. When a pending + * transmit is stopped, \ref RAIL_EVENT_TX_BLOCKED should occur. + */ +RAIL_Status_t RAIL_StopTx(RAIL_Handle_t railHandle, RAIL_StopMode_t mode); + +/** + * Set the CCA threshold in dBm. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] ccaThresholdDbm The CCA threshold in dBm. + * @return Status code indicating success of the function call. + * + * Unlike RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(), which can cause a + * transmit, this function only modifies the CCA threshold. A possible + * use case for this function involves setting the CCA threshold to invalid RSSI + * of -128 which blocks transmission by preventing clear channel assessments + * from succeeding. + */ +RAIL_Status_t RAIL_SetCcaThreshold(RAIL_Handle_t railHandle, + int8_t ccaThresholdDbm); + +/** + * Get detailed information about the last packet transmitted. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pPacketDetails An application-provided pointer to store + * RAIL_TxPacketDetails_t corresponding to the transmit event. + * The isAck and timeSent fields totalPacketBytes and timePosition + * must be initialized prior to each call: + * - isAck true to obtain details about the most recent ACK transmit, + * false to obtain details about the most recent app-initiated transmit. + * - totalPacketBytes with the total number of bytes of the transmitted + * packet for RAIL to use when calculating the specified timestamp. + * This should account for all bytes sent over the air after the + * Preamble and Sync word(s), including CRC bytes. + * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying + * the packet position to put in the timeSent field on return. + * This field will also be updated with the actual position corresponding + * to the timeSent value filled in. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, + * or an appropriate error code otherwise. + * + * @note Consider using \ref RAIL_GetTxPacketDetailsAlt2 for smaller code size. + * + * This function can only be called from callback context for either + * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT + * events. + */ +RAIL_Status_t RAIL_GetTxPacketDetails(RAIL_Handle_t railHandle, + RAIL_TxPacketDetails_t *pPacketDetails); + +/** + * Get detailed information about the last packet transmitted. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] isAck True to obtain details about the most recent ACK transmit. + * False to obtain details about the most recent app-initiated transmit. + * @param[out] pPacketTime An application-provided non-NULL pointer to store a + * RAIL_Time_t corresponding to the transmit event. This will be populated + * with a timestamp corresponding to an arbitrary location in the packet. Call + * \ref RAIL_GetTxTimePreambleStart, \ref RAIL_GetTxTimeSyncWordEnd, or + * \ref RAIL_GetTxTimeFrameEnd to adjust the timestamp for different locations + * in the packet. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was filled in, + * or an appropriate error code otherwise. + * + * @note Consider using \ref RAIL_GetTxPacketDetailsAlt2 to pass in + * a \ref RAIL_PacketTimeStamp_t structure instead of a \ref RAIL_Time_t + * structure, particularly when \ref RAIL_PacketTimePosition_t information + * is needed or useful. + * + * This function can only be called from callback context for either + * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT + * events. + */ +RAIL_Status_t RAIL_GetTxPacketDetailsAlt(RAIL_Handle_t railHandle, + bool isAck, + RAIL_Time_t *pPacketTime); + +/** + * Get detailed information about the last packet transmitted. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails An application-provided pointer to store + * RAIL_TxPacketDetails_t corresponding to the transmit event. + * The isAck must be initialized prior to each call: + * - isAck true to obtain details about the most recent ACK transmit, + * false to obtain details about the most recent app-initiated transmit. + * The timeSent field packetTime will be populated with a timestamp corresponding + * to a default location in the packet. The timeSent field timePosition will + * be populated with a \ref RAIL_PacketTimePosition_t value specifying that + * default packet location. Call \ref RAIL_GetTxTimePreambleStartAlt, + * \ref RAIL_GetTxTimeSyncWordEndAlt, or \ref RAIL_GetTxTimeFrameEndAlt to + * adjust the timestamp for different locations in the packet. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, + * or an appropriate error code otherwise. + * + * This function can only be called from callback context for either + * \ref RAIL_EVENT_TX_PACKET_SENT or \ref RAIL_EVENT_TXACK_PACKET_SENT + * events. + */ +RAIL_Status_t RAIL_GetTxPacketDetailsAlt2(RAIL_Handle_t railHandle, + RAIL_TxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL TX completion timestamp to refer to the start of the + * preamble. Also used to retrieve the \ref RAIL_EVENT_TX_STARTED + * timestamp. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the transmitted + * packet for RAIL to use when adjusting the provided timestamp. This + * should account for all bytes transmitted over the air after the Preamble + * and Sync word(s), including CRC bytes. Pass \ref RAIL_TX_STARTED_BYTES + * to retrieve the start-of-normal-TX timestamp (see below). + * @param[in, out] pPacketTime This points to the \ref RAIL_Time_t returned + * from a previous call to \ref RAIL_GetTxPacketDetailsAlt for this same + * packet. That time will be updated with the time that the preamble for + * this packet started on air. + * Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully + * determined or an appropriate error code otherwise. + * + * When used for timestamp adjustment, call this function in the + * same transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt() is called. + * + * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED + * event to retrieve that event's start-of-normal-TX timestamp. (ACK + * transmits currently have no equivalent event or associated timestamp.) + * In this case, totalPacketBytes must be \ref RAIL_TX_STARTED_BYTES, and + * pPacketTime is an output-only parameter filled in with that time (so no + * need to initialize it beforehand by calling \ref + * RAIL_GetTxPacketDetailsAlt()). + * + */ +RAIL_Status_t RAIL_GetTxTimePreambleStart(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL TX completion timestamp to refer to the start of the + * preamble. Also used to retrieve the \ref RAIL_EVENT_TX_STARTED + * timestamp. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * The application must update the timeSent field totalPacketBytes to be + * the total number of bytes of the sent packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * transmitted over the air after the Preamble and Sync word(s), including CRC + * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX + * timestamp (see below). After this function, the timeSent field packetTime + * will be updated with the time that the preamble for this packet started on air. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * When used for timestamp adjustment, call this function in the + * same transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt2() is called. + * + * This function may be called when handling the \ref RAIL_EVENT_TX_STARTED + * event to retrieve that event's start-of-normal-TX timestamp. (ACK + * transmits currently have no equivalent event or associated timestamp.) + * In this case, the timeSent field totalPacketBytes must be + * \ref RAIL_TX_STARTED_BYTES, and the timeSent field packetTime is an + * output-only parameter filled in with that time (so no need to initialize + * it beforehand by calling \ref RAIL_GetTxPacketDetailsAlt2()). + * + */ +RAIL_Status_t RAIL_GetTxTimePreambleStartAlt(RAIL_Handle_t railHandle, + RAIL_TxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL TX timestamp to refer to the end of the sync word. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the transmitted + * packet for RAIL to use when calculating the specified timestamp. This + * should account for all bytes transmitted over the air after the Preamble + * and Sync word(s), including CRC bytes. + * @param[in, out] pPacketTime The time that was returned in a + * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt + * for this same packet. After this function, the time at that location will + * be updated with the time that the sync word for this packet finished on + * air. Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, + * or an appropriate error code otherwise. + * + * Call the timestamp adjustment function in the same + * transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt() is called. + */ +RAIL_Status_t RAIL_GetTxTimeSyncWordEnd(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL TX timestamp to refer to the end of the sync word. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * The application must update the timeSent field totalPacketBytes to be + * the total number of bytes of the sent packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * transmitted over the air after the Preamble and Sync word(s), including CRC + * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX + * timestamp (see below). After this function, the timeSent field packetTime + * will be updated with the time that the sync word for this packet finished on + * air. Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * Call the timestamp adjustment function in the same + * transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt2() is called. + */ +RAIL_Status_t RAIL_GetTxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, + RAIL_TxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL TX timestamp to refer to the end of frame. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the transmitted + * packet for RAIL to use when calculating the specified timestamp. This + * should account for all bytes transmitted over the air after the Preamble + * and Sync word(s), including CRC bytes. + * @param[in, out] pPacketTime The time that was returned in a + * \ref RAIL_Time_t from a previous call to \ref RAIL_GetTxPacketDetailsAlt + * for this same packet. After this function, the time at that location will + * be updated with the time that this packet finished on air. Must be + * non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, + * or an appropriate error code otherwise. + * + * Call the timestamp adjustment function in the same + * transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt() is called. + */ +RAIL_Status_t RAIL_GetTxTimeFrameEnd(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL TX timestamp to refer to the end of frame. + * + * @param[in] railHandle A RAIL instance handle. + + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetTxPacketDetailsAlt2 for this same packet. + * The application must update the timeSent field totalPacketBytes to be + * the total number of bytes of the sent packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * transmitted over the air after the Preamble and Sync word(s), including CRC + * bytes. Pass \ref RAIL_TX_STARTED_BYTES to retrieve the start-of-normal-TX + * timestamp (see below). After this function, the timeSent field packetTime + * will be updated with the time that this packet finished on air. Must be + * non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * Call the timestamp adjustment function in the same + * transmit-complete event-handling context as + * \ref RAIL_GetTxPacketDetailsAlt2() is called. + */ +RAIL_Status_t RAIL_GetTxTimeFrameEndAlt(RAIL_Handle_t railHandle, + RAIL_TxPacketDetails_t *pPacketDetails); + +/** + * Prevent the radio from starting a transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Enable/Disable TX hold off. + * + * Enable TX hold off to prevent the radio from starting any transmits. + * Disable TX hold off to allow the radio to transmit again. + * Attempting to transmit with the TX hold off enabled will result in + * \ref RAIL_EVENT_TX_BLOCKED and/or \ref RAIL_EVENT_TXACK_BLOCKED + * events. + * + * @note This function does not affect a transmit that has already started. + * To stop an already-started transmission, use RAIL_Idle() with + * \ref RAIL_IDLE_ABORT. + */ +void RAIL_EnableTxHoldOff(RAIL_Handle_t railHandle, bool enable); + +/** + * Check whether or not TX hold off is enabled. + * + * @param[in] railHandle A RAIL instance handle. + * @return Returns true if TX hold off is enabled, false otherwise. + * + * TX hold off can be enabled/disabled using \ref RAIL_EnableTxHoldOff. + * Attempting to transmit with the TX hold off enabled will block the + * transmission and result in \ref RAIL_EVENT_TX_BLOCKED + * and/or \ref RAIL_EVENT_TXACK_BLOCKED events. + */ +bool RAIL_IsTxHoldOffEnabled(RAIL_Handle_t railHandle); + +/** + * Set an alternate transmitter preamble length. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] length The desired preamble length, in bits. + * @return Status code indicating success of the function call. + * + * To cause a transmission to use this alternate preamble length, + * specify \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN in the txOptions + * parameter passed to the respective RAIL transmit API. + * + * @note Attempting to set a preamble length of 0xFFFF bits will result in + * \ref RAIL_STATUS_INVALID_PARAMETER. + **/ +RAIL_Status_t RAIL_SetTxAltPreambleLength(RAIL_Handle_t railHandle, uint16_t length); + +/** @} */ // end of group Transmit + +/****************************************************************************** + * Receive + *****************************************************************************/ +/** + * @addtogroup Receive + * @brief APIs related to packet receive + * @{ + */ + +/** + * Configure receive options. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mask A bitmask containing which options should be modified. + * @param[in] options A bitmask containing desired configuration settings. + * Bit positions for each option are found in the \ref RAIL_RxOptions_t. + * @return Status code indicating success of the function call. + * + * Configure the radio receive flow based on the list of available options. + * Only the options indicated by the mask parameter will be affected. Pass + * \ref RAIL_RX_OPTIONS_ALL to set all parameters. + * The previous settings may affect the current frame if a packet is + * received during this configuration. + * + * @note: On chips where \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING + * is true, enabling \ref RAIL_RX_OPTION_CHANNEL_SWITCHING without configuring + * RX channel switching, via \ref RAIL_IEEE802154_ConfigRxChannelSwitching, + * will return \ref RAIL_STATUS_INVALID_PARAMETER for only this option. + * Any other RX options (except antenna selection) would still take effect. + */ +RAIL_Status_t RAIL_ConfigRxOptions(RAIL_Handle_t railHandle, + RAIL_RxOptions_t mask, + RAIL_RxOptions_t options); + +/** + * Include the code necessary for frame type based length decoding. + * + * @param[in] railHandle A RAIL instance handle. + * + * This function must be called before \ref RAIL_ConfigChannels to allow configurations + * using a frame type based length setup. In RAIL 2.x, it is called by default + * in the \ref RAILCb_ConfigFrameTypeLength API which can be overridden to save + * code space. In future versions, the user may be required to call this API + * explicitly. + */ +void RAIL_IncludeFrameTypeLength(RAIL_Handle_t railHandle); + +/** + * Handle frame type length. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] frameType A frame type configuration structure. + * + * This function is implemented in the radio configuration. + * Currently, the frame type passed in only handles packet length decoding. If + * NULL is passed into this function, it clears any currently configured + * frame type settings. This will either be implemented as an empty function in + * the radio configuration if it is not needed, to assist in dead code + * elimination. + */ +void RAILCb_ConfigFrameTypeLength(RAIL_Handle_t railHandle, + const RAIL_FrameType_t *frameType); + +/** + * Start the receiver on a specific channel. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel The channel to listen on. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this receive appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. + * + * This is a non-blocking function. Whenever a packet is received, \ref RAIL_Config_t::eventsCallback + * will fire with \ref RAIL_EVENT_RX_PACKET_RECEIVED set. If you call + * this while not idle but with a different channel, any ongoing + * receive or transmit operation will be aborted. + */ +RAIL_Status_t RAIL_StartRx(RAIL_Handle_t railHandle, + uint16_t channel, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Schedule a receive window for some future time. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel A channel to listen on. + * @param[in] cfg The configuration structure to define the receive window. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this receive appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. + * + * This API immediately changes the channel and schedules receive to start + * at the specified time and end at the given end time. If you do not specify + * an end time, you may call this API later with an end time as long as you set + * the start time to disabled. You can also terminate the receive + * operation immediately using the RAIL_Idle() function. Note that relative + * end times are always relative to the start unless no start time is + * specified. If changing channels, the channel is changed immediately and + * will abort any ongoing packet transmission or reception. + * + * Returns an error if a CSMA or LBT transmit is still in progress. + * + * In multiprotocol, ensure that you properly yield the radio after this + * call. See \ref rail_radio_scheduler_yield for more details. + */ +RAIL_Status_t RAIL_ScheduleRx(RAIL_Handle_t railHandle, + uint16_t channel, + const RAIL_ScheduleRxConfig_t *cfg, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/****************************************************************************** + * Packet Information (RX) + *****************************************************************************/ +/// @addtogroup Packet_Information Packet Information +/// @brief APIs to get information about received packets. +/// +/// After receiving a packet, RAIL will trigger a +/// \ref RAIL_EVENT_RX_PACKET_RECEIVED event. At that point, there is a variety +/// of information available to the application about the received packet. The +/// following example code assumes that the +/// \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO is not used, and the application +/// wants as much data about the packet as possible. +/// +/// @code{.c} +/// // Get all information about a received packet. +/// RAIL_Status_t status; +/// RAIL_RxPacketInfo_t rxInfo; +/// RAIL_RxPacketDetails_t rxDetails; +/// RAIL_RxPacketHandle_t rxHandle +/// = RAIL_GetRxPacketInfo(railHandle, RAIL_RX_PACKET_HANDLE_NEWEST, &rxInfo); +/// assert(rxHandle != RAIL_RX_PACKET_HANDLE_INVALID); +/// status = RAIL_GetRxPacketDetailsAlt(railHandle, rxHandle, &rxDetails); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// if (rxDetails.timeReceived.timePosition == RAIL_PACKET_TIME_INVALID) { +/// return; // No timestamp available for this packet +/// } +/// // CRC_BYTES only needs to be added when not using RAIL_RX_OPTION_STORE_CRC +/// rxDetails.timeReceived.totalPacketBytes = rxInfo.packetBytes + CRC_BYTES; +/// // Choose the function which gives the desired timestamp +/// status = RAIL_GetRxTimeFrameEndAlt(railHandle, &rxDetails); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// // Now all fields of rxInfo and rxDetails have been populated correctly +/// @endcode +/// +/// @{ + +/** + * Get basic information about a pending or received packet. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] packetHandle A packet handle for the unreleased packet as + * returned from a previous call, or sentinel values + * \ref RAIL_RX_PACKET_HANDLE_OLDEST, + * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE or + * \ref RAIL_RX_PACKET_HANDLE_NEWEST. + * @param[out] pPacketInfo An application-provided pointer to store + * \ref RAIL_RxPacketInfo_t for the requested packet. Must be non-NULL. + * @return The packet handle for the requested packet: + * if packetHandle was one of the sentinel values, returns the actual + * packet handle for that packet, otherwise returns packetHandle. + * It may return \ref RAIL_RX_PACKET_HANDLE_INVALID to indicate an error. + * + * This function can be used in any RX mode. It does not free up any + * internal resources. If used in RX \ref RAIL_DataMethod_t::FIFO_MODE, the + * value in \ref RAIL_RxPacketInfo_t::packetBytes will only return the data + * remaining in the FIFO. Any data read via earlier calls to + * \ref RAIL_ReadRxFifo() is not included. + * + * @note When getting information about an arriving packet that is not yet complete, + * (i.e., pPacketInfo->packetStatus == \ref RAIL_RX_PACKET_RECEIVING), keep + * in mind its data is highly suspect because it has not yet passed any CRC + * integrity checking. Also note that the packet could be aborted, canceled, or + * fail momentarily, invalidating its data in Packet mode. Furthermore, there + * is a small chance towards the end of packet reception that the filled-in + * RAIL_RxPacketInfo_t could include not only packet data received so far, + * but also some raw radio-appended info detail bytes that RAIL's + * packet-completion processing will subsequently deal with. It's up to the + * application to know its packet format well enough to avoid confusing such + * info as packet data. + */ +RAIL_RxPacketHandle_t RAIL_GetRxPacketInfo(RAIL_Handle_t railHandle, + RAIL_RxPacketHandle_t packetHandle, + RAIL_RxPacketInfo_t *pPacketInfo); + +/** + * Get information about the live incoming packet (if any). + * Differs from \ref RAIL_GetRxPacketInfo() by only returning information + * about a packet actively being received, something which even the + * \ref RAIL_RX_PACKET_HANDLE_NEWEST may not represent if there are + * completed but unprocessed packets in the receive FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] pPacketInfo Application provided pointer to store + * RAIL_RxPacketInfo_t for the incoming packet. + * + * This function can only be called from callback context, e.g., + * when handling \ref RAIL_EVENT_RX_FILTER_PASSED or + * \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND. + * It must not be used with receive \ref RAIL_DataMethod_t::FIFO_MODE + * if any portion of an incoming packet has already been extracted from + * the receive FIFO. + * + * @note The incomplete data of an arriving packet is highly suspect because + * it has not yet passed any CRC integrity checking. Also note that the + * packet could be aborted, canceled, or fail momentarily, invalidating + * its data in Packet mode. Furthermore, there is a small chance towards + * the end of packet reception that the filled-in RAIL_RxPacketInfo_t + * could include not only packet data received so far, but also some raw + * radio-appended info detail bytes that RAIL's packet-completion + * processing will subsequently deal with. It's up to the application to + * know its packet format well enough to avoid confusing such info as + * packet data. + */ +void RAIL_GetRxIncomingPacketInfo(RAIL_Handle_t railHandle, + RAIL_RxPacketInfo_t *pPacketInfo); + +/** + * Copy a full packet to a user-specified contiguous buffer. + * + * @param[out] pDest An application-provided pointer to a buffer of at + * least pPacketInfo->packetBytes in size to store the packet data + * contiguously. This buffer must never overlay RAIL's receive FIFO buffer. + * Exactly pPacketInfo->packetBytes of packet data will be written into it. + * @param[in] pPacketInfo + * \ref RAIL_RxPacketInfo_t for the requested packet. + * + * @note This is a convenience helper function, which + * is intended to be expedient. As a result, it does not + * check the validity of its arguments, + * so don't pass either as NULL, and don't + * pass a pDest pointer to a buffer that's too small for the packet's data. + * @note If only a portion of the packet is needed, use RAIL_PeekRxPacket() + * instead. + */ +static inline +void RAIL_CopyRxPacket(uint8_t *pDest, + const RAIL_RxPacketInfo_t *pPacketInfo) +{ + (void)memcpy(pDest, pPacketInfo->firstPortionData, pPacketInfo->firstPortionBytes); + if (pPacketInfo->lastPortionData != NULL) { + uint16_t size = pPacketInfo->packetBytes - pPacketInfo->firstPortionBytes; + (void)memcpy(pDest + pPacketInfo->firstPortionBytes, + pPacketInfo->lastPortionData, size); + } +} + +/** + * Get detailed information about a received packet. + * This function can be used in any RX mode; it does not free up any + * internal resources. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] packetHandle A packet handle for the unreleased packet as + * returned from a previous call to RAIL_GetRxPacketInfo() or + * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST, + * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE + * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. + * @param[in,out] pPacketDetails An application-provided non-NULL pointer to + * store \ref RAIL_RxPacketDetails_t for the requested packet. + * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, + * the timeReceived fields totalPacketBytes and timePosition must be + * initialized prior to each call: + * - totalPacketBytes with the total number of bytes of the received + * packet for RAIL to use when calculating the specified timestamp. + * This should account for all bytes received over the air after the + * Preamble and Sync word(s), including CRC bytes. + * - timePosition with a \ref RAIL_PacketTimePosition_t value specifying + * the packet position to put in the timeReceived field on return. + * This field will also be updated with the actual position corresponding + * to the timeReceived value filled in. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, + * or an appropriate error code otherwise. + * + * @note Certain details are always available, while others are only available + * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO + * option is not in effect and the received packet's + * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. + * See \ref RAIL_RxPacketDetails_t for clarification. + * + * @note Consider using \ref RAIL_GetRxPacketDetailsAlt for smaller code size. + */ +RAIL_Status_t RAIL_GetRxPacketDetails(RAIL_Handle_t railHandle, + RAIL_RxPacketHandle_t packetHandle, + RAIL_RxPacketDetails_t *pPacketDetails); + +/** + * Get detailed information about a received packet. + * This function can be used in any RX mode. It does not free up any + * internal resources. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] packetHandle A packet handle for the unreleased packet as + * returned from a previous call to RAIL_GetRxPacketInfo() or + * RAIL_HoldRxPacket(), or sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST + * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE or + * \ref RAIL_RX_PACKET_HANDLE_NEWEST. + * @param[out] pPacketDetails An application-provided non-NULL pointer to + * store \ref RAIL_RxPacketDetails_t for the requested packet. + * For \ref RAIL_RxPacketStatus_t RAIL_RX_PACKET_READY_ packets, + * the timeReceived field packetTime will be populated with a timestamp + * corresponding to a default location in the packet. The timeReceived field + * timePosition will be populated with a \ref RAIL_PacketTimePosition_t value + * specifying that default packet location. Call + * \ref RAIL_GetRxTimePreambleStart, \ref RAIL_GetRxTimeSyncWordEnd, or + * \ref RAIL_GetRxTimeFrameEnd to adjust that timestamp for different + * locations in the packet. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketDetails was filled in, + * or an appropriate error code otherwise. + * + * This alternative API allows for smaller code size by deadstripping the + * timestamp adjustment algorithms which are not in use. + * + * @note Certain details are always available, while others are only available + * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO + * option is not in effect and the received packet's + * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. + * See \ref RAIL_RxPacketDetails_t for clarification. + */ +RAIL_Status_t RAIL_GetRxPacketDetailsAlt(RAIL_Handle_t railHandle, + RAIL_RxPacketHandle_t packetHandle, + RAIL_RxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL RX timestamp to refer to the start of the preamble. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the received packet + * for RAIL to use when calculating the specified timestamp. This should + * account for all bytes received over the air after the Preamble and Sync + * word(s), including CRC bytes. + * @param[in, out] pPacketTime The time that was returned in the + * \ref RAIL_PacketTimeStamp_t::packetTime field of + * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to + * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this + * function, the time at that location will be updated with the time that the + * preamble for this packet started on air. Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, + * or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API + * may return incorrect timestamps when sub-phys are in use. Prefer + * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See + * \ref RAIL_RxPacketDetails_t::subPhyId for more details. + */ +RAIL_Status_t RAIL_GetRxTimePreambleStart(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL RX timestamp to refer to the start of the preamble. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * The application must update the timeReceived field totalPacketBytes to be + * the total number of bytes of the received packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * received over the air after the Preamble and Sync word(s), including CRC + * bytes. After this function, the timeReceived field packetTime will be + * updated with the time that the preamble for this packet started on air. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_GetRxTimePreambleStartAlt(RAIL_Handle_t railHandle, + RAIL_RxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL RX timestamp to refer to the end of the sync word. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the received packet + * for RAIL to use when calculating the specified timestamp. This should + * account for all bytes received over the air after the Preamble and Sync + * word(s), including CRC bytes. + * @param[in, out] pPacketTime The time that was returned in the + * \ref RAIL_PacketTimeStamp_t::packetTime field of + * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to + * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this + * function, the time at that location will be updated with the time that the + * sync word for this packet finished on air. Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, + * or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API + * may return incorrect timestamps when sub-phys are in use. Prefer + * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See + * \ref RAIL_RxPacketDetails_t::subPhyId for more details. + */ +RAIL_Status_t RAIL_GetRxTimeSyncWordEnd(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL RX timestamp to refer to the end of the sync word. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * The application must update the timeReceived field totalPacketBytes to be + * the total number of bytes of the received packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * received over the air after the Preamble and Sync word(s), including CRC + * bytes. After this function, the timeReceived field packetTime will be + * updated with the time that the sync word for this packet finished on air. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_GetRxTimeSyncWordEndAlt(RAIL_Handle_t railHandle, + RAIL_RxPacketDetails_t *pPacketDetails); + +/** + * Adjust a RAIL RX timestamp to refer to the end of frame. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] totalPacketBytes The total number of bytes of the received packet + * for RAIL to use when calculating the specified timestamp. This should + * account for all bytes received over the air after the Preamble and Sync + * word(s), including CRC bytes. + * @param[in, out] pPacketTime The time that was returned in the + * \ref RAIL_PacketTimeStamp_t::packetTime field of + * \ref RAIL_RxPacketDetails_t::timeReceived from a previous call to + * \ref RAIL_GetRxPacketDetailsAlt for this same packet. After this + * function, the time at that location will be updated with the time that this + * packet finished on air. Must be non-NULL. + * @return \ref RAIL_STATUS_NO_ERROR if pPacketTime was successfully calculated, + * or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. Note that this API + * may return incorrect timestamps when sub-phys are in use. Prefer + * \ref RAIL_GetRxTimePreambleStartAlt in those situations. See + * \ref RAIL_RxPacketDetails_t::subPhyId for more details. + */ +RAIL_Status_t RAIL_GetRxTimeFrameEnd(RAIL_Handle_t railHandle, + uint16_t totalPacketBytes, + RAIL_Time_t *pPacketTime); + +/** + * Adjust a RAIL RX timestamp to refer to the end of frame. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] pPacketDetails The non-NULL details that were returned from + * a previous call to \ref RAIL_GetRxPacketDetailsAlt for this same packet. + * The application must update the timeReceived field totalPacketBytes to be + * the total number of bytes of the received packet for RAIL to use when + * calculating the specified timestamp. This should account for all bytes + * received over the air after the Preamble and Sync word(s), including CRC + * bytes. After this function, the timeReceived field packetTime will be + * updated with the time that the packet finished on air. + * @return \ref RAIL_STATUS_NO_ERROR if the packet time was successfully + * calculated, or an appropriate error code otherwise. + * + * Call this API while the given railHandle is active, or it will + * return an error code of \ref RAIL_STATUS_INVALID_STATE. + */ +RAIL_Status_t RAIL_GetRxTimeFrameEndAlt(RAIL_Handle_t railHandle, + RAIL_RxPacketDetails_t *pPacketDetails); + +/** @} */ // end of group Packet_Information + +/** + * Place a temporary hold on this packet's data and information resources + * within RAIL. + * This function can only be called from within RAIL callback context. + * It can be used in any RX mode. + * + * Normally, when RAIL issues its callback indicating a packet is ready + * or aborted, it expects the application's callback to retrieve and + * copy (or discard) the packet's information and data, and will free up + * its internal packet data after the callback returns. This function + * tells RAIL to hold onto those resources after the callback returns in + * case the application wants to defer processing the packet to a later + * time, e.g., outside of callback context. + * + * @param[in] railHandle A RAIL instance handle. + * @return The packet handle for the packet associated with the callback, + * \ref RAIL_RX_PACKET_HANDLE_INVALID if no such packet yet exists or + * railHandle is not active. + * + * @note When using multiprotocol the receive FIFO is reset during protocol + * switches so any packets held with \ref RAIL_HoldRxPacket() will be lost. It + * is best to avoid using this in DMP or to at least reset any internal held + * packet information when the \ref RAIL_EVENT_CONFIG_UNSCHEDULED occurs. + */ +RAIL_RxPacketHandle_t RAIL_HoldRxPacket(RAIL_Handle_t railHandle); + +/** + * Copy 'len' bytes of packet data starting from 'offset' from the + * receive FIFO. Those bytes remain valid for re-peeking. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] packetHandle A packet handle as returned from a previous + * RAIL_GetRxPacketInfo() or RAIL_HoldRxPacket() call, or + * sentinel values \ref RAIL_RX_PACKET_HANDLE_OLDEST, + * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE + * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. + * @param[out] pDst A pointer to the location where the received bytes will + * be copied. If NULL, no copying occurs. + * @param[in] len A number of packet data bytes to copy. + * @param[in] offset A byte offset within remaining packet data from which + * to copy. + * @return Number of packet bytes copied. + * + * @note Peek does not permit peeking beyond the requested packet's + * available packet data (though there is a small chance it might + * for a \ref RAIL_RX_PACKET_HANDLE_NEWEST packet at the very end of + * still being received). Nor can one peek into already-consumed data read + * by RAIL_ReadRxFifo(). len and offset are relative to the remaining data + * available in the packet, if any was already consumed by RAIL_ReadRxFifo(). + */ +uint16_t RAIL_PeekRxPacket(RAIL_Handle_t railHandle, + RAIL_RxPacketHandle_t packetHandle, + uint8_t *pDst, + uint16_t len, + uint16_t offset); + +/** + * Release RAIL's internal resources for the packet. + * This function must be called for any packet previously held via + * RAIL_HoldRxPacket(). It may optionally be called within a + * callback context to release RAIL resources sooner than at + * callback completion time when not holding the packet. + * This function can be used in any RX mode. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] packetHandle A packet handle as returned from a previous + * RAIL_HoldRxPacket() call, or sentinel values + * \ref RAIL_RX_PACKET_HANDLE_OLDEST, + * \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE + * or \ref RAIL_RX_PACKET_HANDLE_NEWEST. + * The latter might be used within RAIL callback context to explicitly + * release the packet associated with the callback early, before it's + * released automatically by RAIL on callback return (unless explicitly + * held). + * @return \ref RAIL_STATUS_NO_ERROR if the held packet was released + * or an appropriate error code otherwise. + */ +RAIL_Status_t RAIL_ReleaseRxPacket(RAIL_Handle_t railHandle, + RAIL_RxPacketHandle_t packetHandle); + +/** + * Return the current raw RSSI. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] wait if false returns instant RSSI with no checks. + * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI + * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. + * + * Gets the current RSSI value. This value represents the current energy of the + * channel. It can change rapidly and will be low if no RF energy is + * in the current channel. The function from the value reported to dBm is an + * offset dependent on the PHY and the PCB layout. Characterize the + * RSSI received on your hardware and apply an offset in the application to + * account for board and PHY parameters. When 'wait' is false, the radio needs + * to be currently in RX and have been in there for a sufficient amount of time + * for a fresh RSSI value to be read and returned. Otherwise, the RSSI is + * considered stale and \ref RAIL_RSSI_INVALID is returned instead. When 'wait' + * is true, if the radio is transitioning to or already in RX, this function + * will wait for a valid RSSI to be read and return it. Otherwise, if the radio + * is in or transitions to IDLE or TX, \ref RAIL_RSSI_INVALID will be returned. + * On low datarate PHYs, this function can take a significantly longer time when + * wait is true. + * + * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID + * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * Additionally, 'wait' should never be set 'true' in multiprotocol + * as the wait time is not consistent, so scheduling a scheduler + * slot cannot be done accurately. Rather if waiting for a valid RSSI is + * desired, use \ref RAIL_GetRssiAlt instead to apply a bounded time period. + * + * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), + * pass true for the wait parameter otherwise it's very likely + * \ref RAIL_RSSI_INVALID will be returned. + * + * @note If RX channel hopping is turned on, do not use this API. + * Instead, see RAIL_GetChannelHoppingRssi(). + * + * @note When 'wait' is false, this API is equivalent to \ref RAIL_GetRssiAlt + * with 'waitTimeout' set to \ref RAIL_GET_RSSI_NO_WAIT. When 'wait' is + * true, this API is equivalent to \ref RAIL_GetRssiAlt with 'waitTimeout' + * set to \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT. Consider using + * \ref RAIL_GetRssiAlt if a bounded maximum wait timeout is desired. + */ +int16_t RAIL_GetRssi(RAIL_Handle_t railHandle, bool wait); + +/** + * Return the current raw RSSI within a definitive time period. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] waitTimeout Sets the maximum time to wait for a valid RSSI. + * If equal to \ref RAIL_GET_RSSI_NO_WAIT returns instant RSSI with no checks. + * If equal to \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT waits for a valid RSSI + * with no maximum timeout. + * @return \ref RAIL_RSSI_INVALID if the receiver is disabled and an RSSI + * value can't be obtained. Otherwise, return the RSSI in quarter dBm, dbm*4. + * + * Gets the current RSSI value. This value represents the current energy of the + * channel. It can change rapidly, and will be low if no RF energy is + * in the current channel. The function from the value reported to dBm is an + * offset dependent on the PHY and the PCB layout. Characterize the + * RSSI received on your hardware and apply an offset in the application to + * account for board and PHY parameters. If a value of \ref RAIL_GET_RSSI_NO_WAIT + * is given for waitTimeout, the radio needs to be currently in RX and have been + * in there for a sufficient amount of time for a fresh RSSI value to be read and + * returned. Otherwise the RSSI is considered stale and \ref RAIL_RSSI_INVALID is + * returned instead. For non-zero values of waitTimeout, if the radio is + * transitioning to or already in RX, this function will wait a maximum time equal + * to waitTimeout (or indefinitely if waitTimeout is set to + * \ref RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT) for a valid RSSI to be read and return + * it. Otherwise, if the waitTimeout is reached, or the radio is in or transitions + * to IDLE or TX, \ref RAIL_RSSI_INVALID will be returned. On low datarate PHYs, + * this function can take a significantly longer time when waitTimeout is non-zero. + * + * In multiprotocol, this function returns \ref RAIL_RSSI_INVALID + * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * Additionally, 'waitTimeout' should never be set to a value other than + * \ref RAIL_GET_RSSI_NO_WAIT in multiprotocol as the integration between this + * feature and the radio scheduler has not been implemented. + * + * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), + * pass true for the wait parameter otherwise it's very likely + * \ref RAIL_RSSI_INVALID will be returned. + * + * @note If RX Antenna Diversity is enabled via \ref RAIL_ConfigRxOptions(), + * the RSSI value returned could come from either antenna and vary between antennas. + * + * @note If RX channel hopping is turned on, do not use this API. + * Instead, see RAIL_GetChannelHoppingRssi(). + */ +int16_t RAIL_GetRssiAlt(RAIL_Handle_t railHandle, RAIL_Time_t waitTimeout); + +/** + * Start the RSSI averaging over a specified time in us. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel The physical channel to set. + * @param[in] averagingTimeUs Averaging time in microseconds. + * @param[in] schedulerInfo Information to allow the radio scheduler to place + * this operation appropriately. This is only used in multiprotocol version of + * RAIL and may be set to NULL in all other versions. + * @return Status code indicating success of the function call. + * + * Starts a non-blocking hardware-based RSSI averaging mechanism. Only a single + * instance of RSSI averaging can be run at any time and the radio must be idle + * to start. + * + * In multiprotocol, this is a scheduled event. It will start when railHandle + * becomes active. railHandle needs to stay active until the averaging + * completes. If the averaging is interrupted, calls to + * \ref RAIL_GetAverageRssi will return \ref RAIL_RSSI_INVALID. + * + * Also in multiprotocol, the user is required to call \ref RAIL_YieldRadio + * after this event completes (i.e., when \ref RAIL_EVENT_RSSI_AVERAGE_DONE + * occurs). + * + * @note If the radio is idled while RSSI averaging is still in effect, a + * \ref RAIL_EVENT_RSSI_AVERAGE_DONE event may not occur and + * \ref RAIL_IsAverageRssiReady may never return true. + */ +RAIL_Status_t RAIL_StartAverageRssi(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_Time_t averagingTimeUs, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Query whether the RSSI averaging is done. + * + * @param[in] railHandle A RAIL instance handle. + * @return Returns true if done and false otherwise. + * + * This function can be used to poll for completion of the RSSI averaging + * to avoid relying on an interrupt-based callback. + * + * @note If the radio is idled while RSSI averaging is still in effect, + * this function may never return true. + */ +bool RAIL_IsAverageRssiReady(RAIL_Handle_t railHandle); + +/** + * Get the RSSI averaged over a specified time in us. + * + * @param[in] railHandle A RAIL instance handle. + * @return Return \ref RAIL_RSSI_INVALID if the receiver is disabled + * an RSSI value can't be obtained. Otherwise, return the RSSI in + * quarter dBm,dbm*4. + * + * Gets the hardware RSSI average after issuing RAIL_StartAverageRssi. + * Use after \ref RAIL_StartAverageRssi. + */ +int16_t RAIL_GetAverageRssi(RAIL_Handle_t railHandle); + +/** + * Set the RSSI offset. + * + * @param[in] railHandle a RAIL instance handle. + * @param[in] rssiOffset desired offset to be added to the RSSI measurements. + * @return Status code indicating success of the function call. + * \ref RAIL_STATUS_INVALID_CALL if called with chip-specific handle, such + * as \ref RAIL_EFR32_HANDLE, after RAIL initialization. + * \ref RAIL_STATUS_INVALID_PARAMETER if the RSSI offset is deemed large + * enough to cause the RSSI readings to underflow or overflow. + * + * Adds an offset to the RSSI in dBm. This offset affects all functionality that + * depends on RSSI values, such as CCA functions. Do not modify the offset + * dynamically during packet reception. This function + * can only be called while the radio is off, or in the case of multiprotocol, + * on an inactive protocol. + * + * @note: If RAIL has not been initialized, a chip-specific handle, + * such as \ref RAIL_EFR32_HANDLE, can be used to set a chip level RSSI offset. + * + * @note: Setting a large rssiOffset may still cause the RSSI readings to + * underflow. If that happens, the RSSI value returned by + * \ref RAIL_GetRssi, \ref RAIL_GetAverageRssi, + * \ref RAIL_GetChannelHoppingRssi etc. will be \ref RAIL_RSSI_LOWEST + * + * @note: During \ref Rx_Channel_Hopping this API will not update the + * RSSI offset immediately if channel hopping has already been configured. + * A subsequent call to \ref RAIL_ZWAVE_ConfigRxChannelHopping or + * \ref RAIL_ConfigRxChannelHopping is required for the new RSSI offset to + * take effect. + */ +RAIL_Status_t RAIL_SetRssiOffset(RAIL_Handle_t railHandle, int8_t rssiOffset); + +/** + * Get the RSSI offset. + * + * @param[in] railHandle a RAIL instance handle. + * @return rssiOffset in dBm corresponding to the current handle. + * + * @note: A chip-specific handle, such as \ref RAIL_EFR32_HANDLE, can be used to + * get the chip level RSSI offset otherwise this will return the RSSI offset + * value associated with the RAIL instance handle, exclusive of any chip level + * RSSI offset correction, if any. + */ +int8_t RAIL_GetRssiOffset(RAIL_Handle_t railHandle); + +/** + * Set the RSSI detection threshold(in dBm) to trigger + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD. + * + * @param[in] railHandle a RAIL instance handle. + * @param[in] rssiThresholdDbm desired RSSI threshold(in dBm) over which the event + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD is triggered. + * @return Status code indicating success of the function call. + * Returns \ref RAIL_STATUS_INVALID_STATE in multiprotocol, + * if the requested \ref RAIL_Handle_t is not active. + * Returns \ref RAIL_STATUS_INVALID_CALL if called on parts on which this function + * is not supported. + * + * When in receive, RSSI is sampled and if it exceeds the threshold, + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD is triggered. + * + * @note: + * If the radio is idled or this function is called with rssiThresholdDbm as + * \ref RAIL_RSSI_INVALID_DBM while RSSI detect is still in effect, a + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD may not occur and the detection is disabled. + * If the RSSI is already above threshold when this function is called then + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD will occur. + * Once the RSSI goes over the configured threshold and + * \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD occurs, this function needs to be + * called again to reactivate the RSSI threshold detection. + * This function is only available on series-2 Sub-GHz parts EFR32XG23 and EFR32XG25. + */ +RAIL_Status_t RAIL_SetRssiDetectThreshold(RAIL_Handle_t railHandle, + int8_t rssiThresholdDbm); + +/** + * Get the RSSI detection threshold(in dBm). + * + * @param[in] railHandle a RAIL instance handle. + * @return rssiThreshold (in dBm) corresponding to the current handle. + * @note: + * The function returns \ref RAIL_RSSI_INVALID_DBM when + * \ref RAIL_SetRssiDetectThreshold is not supported or disabled. + * In multiprotocol, the function returns \ref RAIL_RSSI_INVALID_DBM if railHandle + * is not active. + * This function is only available on series-2 Sub-GHz parts EFR32XG23 and EFR32XG25. + */ +int8_t RAIL_GetRssiDetectThreshold(RAIL_Handle_t railHandle); + +/** + * Set up a callback function capable of converting a RX packet's LQI value + * before being consumed by application code. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] cb A callback of type \ref RAIL_ConvertLqiCallback_t that is + * called before the RX packet LQI value is loaded into the \ref + * RAIL_RxPacketDetails_t structure for application consumption. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ConvertLqi(RAIL_Handle_t railHandle, + RAIL_ConvertLqiCallback_t cb); + +/****************************************************************************** + * Address Filtering (RX) + *****************************************************************************/ +/** + * @addtogroup Address_Filtering Address Filtering + * @brief Configuration APIs for receive packet address filtering. + * + * The address filtering code examines the packet as follows. + * + * | `Bytes: 0 - 255` | `0 - 8` | `0 - 255` | `0 - 8` | `Variable` | + * |:----------------:|---------:|----------:|---------:|:----------:| + * | `Data0` | `Field0` | `Data1` | `Field1` | `Data2` | + * + * In the above structure, anything listed as DataN is an optional section of + * bytes that RAIL will not process for address filtering. The FieldN segments + * reference specific sections in the packet that will each be interpreted + * as an address during address filtering. The application may submit up to + * four addresses to attempt to match each field segment and each address may + * have a size of up to 8 bytes. To set up address filtering, first configure + * the locations and length of the addresses in the packet. Next, configure + * which combinations of matches in Field0 and Field1 should constitute an + * address match. Last, enter addresses into tables for each field and + * enable them. The first two of these are part of the \ref RAIL_AddrConfig_t + * structure while the second part is configured at runtime using the + * RAIL_SetAddressFilterAddress() API. A brief description of each + * configuration is listed below. + * + * The offsets and sizes of the fields + * are assumed fixed for the RAIL address filter. To set them, specify + * arrays for these values in the sizes and offsets entries in the + * \ref RAIL_AddrConfig_t structure. A size of zero indicates that a field is + * disabled. The start offset for a field is relative to the previous start + * offset and, if you're using FrameType decoding, the first start offset is + * relative to the end of the byte containing the frame type. + * + * Configuring which combinations of Field0 and Field1 constitute a match is + * the most complex portion of the address filter. The easiest way to think + * about this is with a truth table. If you consider each of the four possible + * address entries in a field, you can have a match on any one of those or a + * match for none of them. This is shown in the 5x5 truth table below where + * Field0 matches are the rows and Field1 matches are the columns. + * + * | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | + * |----------------|----------|-----------|-----------|-----------|-----------| + * | __No Match__ | bit0 | bit1 | bit2 | bit3 | bit4 | + * | __Address 0__ | bit5 | bit6 | bit7 | bit8 | bit9 | + * | __Address 1__ | bit10 | bit11 | bit12 | bit13 | bit14 | + * | __Address 2__ | bit15 | bit16 | bit17 | bit18 | bit19 | + * | __Address 3__ | bit20 | bit21 | bit22 | bit23 | bit24 | + * + * Because this is only 25 bits, it can be represented in one 32-bit integer + * where 1 indicates a filter pass and 0 indicates a filter fail. This is the + * matchTable parameter in the configuration structure and is used during + * filtering. For common simple configurations, two defines are provided with + * the truth tables as shown below. The first is \ref + * ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD, which can be used if only using + * one address field (either field). If using two fields and want to + * force in the same address entry in each field, use the second define: \ref + * ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD. For more complex systems, + * create a valid custom table. + * + * @note Address filtering does not function reliably with PHYs that use a data + * rate greater than 500 kbps. If this is a requirement, filtering must + * currently be done by the application. + * + * @{ + */ + +/** + * Configure address filtering. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] addrConfig The configuration structure, which defines how + * addresses are set up in your packets. + * @return Status code indicating success of the function call. + * + * You must call this function to set up address filtering. You may call it + * multiple times but all previous information is wiped out each time you call + * and any configured addresses must be reset. + */ +RAIL_Status_t RAIL_ConfigAddressFilter(RAIL_Handle_t railHandle, + const RAIL_AddrConfig_t *addrConfig); + +/** + * Enable address filtering. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable An argument to indicate whether or not to enable address + * filtering. + * @return True if address filtering was enabled to start with and false + * otherwise. + * + * Only allow packets through that pass the current address filtering + * configuration. This does not reset or change the configuration so you can + * set that up before turning on this feature. + */ +bool RAIL_EnableAddressFilter(RAIL_Handle_t railHandle, bool enable); + +/** + * Return whether address filtering is currently enabled. + * + * @param[in] railHandle A RAIL instance handle. + * @return True if address filtering is enabled and false otherwise. + */ +bool RAIL_IsAddressFilterEnabled(RAIL_Handle_t railHandle); + +/** + * Reset the address filtering configuration. + * + * @param[in] railHandle A RAIL instance handle. + * + * Resets all structures related to address filtering. This does not disable + * address filtering. It leaves the radio in a state where no packets + * pass filtering. + */ +void RAIL_ResetAddressFilter(RAIL_Handle_t railHandle); + +/** + * Set an address for filtering in hardware. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] field Indicates an address field for this address. + * @param[in] index Indicates a match entry for this address for a + * given field. + * @param[in] value A pointer to the address data. This must be at least as + * long as the size specified in RAIL_ConfigAddressFilter(). The first byte, + * value[0], will be compared to the first byte received over the air for this + * address field. + * @param[in] enable A boolean to indicate whether this address should be + * enabled immediately. + * @return Status code indicating success of the function call. + * + * This function loads the given address into hardware for filtering and + * starts filtering if you set the enable parameter to true. Otherwise, + * call RAIL_EnableAddressFilterAddress() to turn it on later. + */ +RAIL_Status_t RAIL_SetAddressFilterAddress(RAIL_Handle_t railHandle, + uint8_t field, + uint8_t index, + const uint8_t *value, + bool enable); + +/** + * Set an address bit mask for filtering in hardware. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] field Indicates an address field for this address bit mask. + * @param[in] bitMask A pointer to the address bitmask. This must be at least + * as long as the size specified in RAIL_ConfigAddressFilter(). The first + * byte, bitMask[0], will be applied to the first byte received over the air + * for this address field. Bits set to 1 in the bit mask indicate which bit + * positions in the incoming packet to compare against the stored addresses + * during address filtering. Bits set to 0 indicate which bit positions to + * ignore in the incoming packet during address filtering. This bit mask is + * applied to all address entries. + * @return Status code indicating success of the function call. + * + * This function loads the given address bit mask into hardware for use when + * address filtering is enabled. All bits in the stored address bit mask are + * set to 1 during hardware initialization and when either \ref + * RAIL_ConfigAddressFilter() or \ref RAIL_ResetAddressFilter() are called. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips + * or the EFR32XG21. Use the compile time symbol \ref + * RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK or the runtime call \ref + * RAIL_SupportsAddrFilterAddressBitMask() to check whether the platform + * supports this feature. + */ +RAIL_Status_t RAIL_SetAddressFilterAddressMask(RAIL_Handle_t railHandle, + uint8_t field, + const uint8_t *bitMask); + +/** + * Enable address filtering for the specified address. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable An argument to indicate whether or not to enable address + * filtering. + * @param[in] field Indicates an address for the address. + * @param[in] index Indicates a match entry in the given field you want to enable. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_EnableAddressFilterAddress(RAIL_Handle_t railHandle, + bool enable, + uint8_t field, + uint8_t index); + +/** @} */ // end of group Address_Filtering + +/** @} */ // end of group Receive + +/****************************************************************************** + * Auto-ACKing + *****************************************************************************/ +/// @addtogroup Auto_Ack Auto-ACK +/// @brief APIs for configuring auto-ACK functionality +/// +/// These APIs configure the radio for automatic acknowledgment +/// features. Auto-ACK inherently changes how the underlying state machine +/// behaves so users should not modify RAIL_SetRxTransitions() and +/// RAIL_SetTxTransitions() while using auto-ACK features. +/// +/// @code{.c} +/// // Go to RX after ACK operation. +/// RAIL_AutoAckConfig_t autoAckConfig = { +/// .enable = true, +/// .ackTimeout = 1000, +/// // "error" param ignored +/// .rxTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX}, +/// // "error" param ignored +/// .txTransitions = { RAIL_RF_STATE_RX, RAIL_RF_STATE_RX} +/// }; +/// +/// RAIL_Status_t status = RAIL_ConfigAutoAck(railHandle, &autoAckConfig); +/// +/// uint8_t ackData[] = {0x05, 0x02, 0x10, 0x00}; +/// +/// RAIL_Status_t status = RAIL_WriteAutoAckFifo(railHandle, +/// ackData, +/// sizeof(ackData)); +/// @endcode +/// +/// The acknowledgment transmits based on the frame format configured via +/// the Radio Configurator. For example, if the frame format is using a variable +/// length scheme, the ACK will be sent according to that scheme. If a 10-byte +/// packet is loaded into the ACK, but the variable length field of the ACK +/// payload specifies a length of 5, only 5 bytes will transmit for the ACK. +/// The converse is also true, if the frame length is configured to be a fixed +/// 10-byte packet but only 5 bytes are loaded into the ACK buffer, a TX +/// underflow occurs during the ACK transmit. +/// +/// Unlike in non-auto-ACK mode, auto-ACK mode will always return to a single +/// state after all ACK sequences complete, regardless of whether +/// the ACK was successfully received/sent or not. See the documentation +/// of \ref RAIL_ConfigAutoAck() for configuration information. To +/// suspend automatic acknowledgment of a series of packets after transmit +/// or receive call RAIL_PauseTxAutoAck() or RAIL_PauseRxAutoAck() respectively +/// with the pause parameter set to true. When auto-ACKing is paused, after +/// receiving or transmitting a packet (regardless of success), the radio +/// transitions to the same state it would use while ACKing. To return to +/// normal state transition logic outside of ACKing, call \ref +/// RAIL_ConfigAutoAck() with the \ref RAIL_AutoAckConfig_t::enable field false +/// and specify the desired transitions in the \ref +/// RAIL_AutoAckConfig_t::rxTransitions and RAIL_AutoAckConfig_t::txTransitions +/// fields. To get out of a paused state and resume auto-ACKing, call +/// RAIL_PauseTxAutoAck() and/or RAIL_PauseRxAutoAck() with the pause parameter +/// set to false. +/// +/// Applications can cancel the transmission of an ACK with +/// RAIL_CancelAutoAck(). Conversely, applications can control if a transmit +/// operation should wait for an ACK after transmitting by using +/// the \ref RAIL_TX_OPTION_WAIT_FOR_ACK option. +/// +/// When \ref Antenna_Control is used for multiple antennas, ACKs are +/// transmitted on the antenna that was selected to receive the packet +/// being acknowledged. When receiving an ACK, the +/// \ref RAIL_RxOptions_t antenna options are used just like for any other +/// receive. +/// +/// If the ACK payload is dynamic, the application must call +/// RAIL_WriteAutoAckFifo() with the appropriate ACK payload after the +/// application processes the receive. RAIL can auto-ACK from the normal +/// transmit buffer if RAIL_UseTxFifoForAutoAck() is called before the radio +/// transmits the ACK. Ensure the transmit buffer contains data loaded by +/// RAIL_WriteTxFifo(). +/// +/// Standard-based protocols that contain auto-ACK functionality are normally +/// configured in the protocol-specific configuration function. For example, +/// RAIL_IEEE802154_Init() provides auto-ACK configuration parameters in \ref +/// RAIL_IEEE802154_Config_t and should only be configured through that +/// function. It is not advisable to call both RAIL_IEEE802154_Init() and \ref +/// RAIL_ConfigAutoAck(). However, ACK modification functions are still valid to +/// use with protocol-specific ACKs. To cancel an IEEE 802.15.4 ACK transmit, +/// use RAIL_CancelAutoAck(). +/// +/// @{ + +/// Configure and enable automatic acknowledgment. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @param[in] config Auto-ACK configuration structure. +/// @return Status code indicating success of the function call. +/// +/// Configures the RAIL state machine to for hardware-accelerated automatic +/// acknowledgment. ACK timing parameters are defined in the configuration +/// structure. +/// +/// While auto-ACKing is enabled, do not call the following RAIL functions: +/// - RAIL_SetRxTransitions() +/// - RAIL_SetTxTransitions() +/// +/// Note that if you are enabling auto-ACK (i.e., "enable" field is true) +/// the "error" fields of rxTransitions and txTransitions are ignored. +/// After all ACK sequences, (success or fail) the state machine will return +/// the radio to the "success" state, which can be either +/// \ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE (returning to +/// \ref RAIL_RF_STATE_TX is not supported). +/// If you need information about the +/// actual success of the ACK sequence, use RAIL events such as +/// \ref RAIL_EVENT_TXACK_PACKET_SENT to make sure an ACK was sent, or +/// \ref RAIL_EVENT_RX_ACK_TIMEOUT to make sure that an ACK was received +/// within the specified timeout. +/// +/// To set a certain turnaround time (i.e., txToRx and rxToTx +/// in \ref RAIL_StateTiming_t), make txToRx lower than +/// desired to ensure you get to RX in time to receive the ACK. +/// Silicon Labs recommends setting 10 us lower than desired: +/// +/// @code{.c} +/// void setAutoAckStateTimings() +/// { +/// RAIL_StateTiming_t timings; +/// +/// // User is already in auto-ACK and wants a turnaround of 192 us. +/// timings.rxToTx = 192; +/// timings.txToRx = 192 - 10; +/// +/// // Set other fields of timings... +/// timings.idleToRx = 100; +/// timings.idleToTx = 100; +/// timings.rxSearchTimeout = 0; +/// timings.txToRxSearchTimeout = 0; +/// +/// RAIL_SetStateTiming(railHandle, &timings); +/// } +/// @endcode +/// +/// As opposed to an explicit "Disable" API, set the "enable" +/// field of the RAIL_AutoAckConfig_t to false. Then, auto-ACK will be +/// disabled and state transitions will be returned to the values set +/// in \ref RAIL_AutoAckConfig_t. When disabling, the "ackTimeout" field +/// isn't used. +/// +/// @note Auto-ACKing may not be enabled while RX Channel Hopping is enabled, +/// or when BLE is enabled. +/// +RAIL_Status_t RAIL_ConfigAutoAck(RAIL_Handle_t railHandle, + const RAIL_AutoAckConfig_t *config); + +/** + * Return the enable status of the auto-ACK feature. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if auto-ACK is enabled, false if disabled. + */ +bool RAIL_IsAutoAckEnabled(RAIL_Handle_t railHandle); + +/** + * Load the auto-ACK buffer with ACK data. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] ackData A pointer to ACK data to transmit. + * This may be NULL, in which case it's assumed the data has already + * been emplaced into the ACK buffer and RAIL just needs to be told + * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get + * the address of RAIL's AutoACK buffer in RAM and its size. + * @param[in] ackDataLen The number of bytes in ACK data. + * @return Status code indicating success of the function call. + * + * If the ACK buffer is available for updates, load the ACK buffer with data. + * If it is not available, \ref RAIL_STATUS_INVALID_STATE is returned. + * If ackDataLen exceeds \ref RAIL_AUTOACK_MAX_LENGTH then + * \ref RAIL_STATUS_INVALID_PARAMETER will be returned and nothing is + * written to the ACK buffer (unless ackData is NULL in which case this + * indicates the application has already likely corrupted RAM). + */ +RAIL_Status_t RAIL_WriteAutoAckFifo(RAIL_Handle_t railHandle, + const uint8_t *ackData, + uint8_t ackDataLen); + +/** + * Get the address and size of the auto-ACK buffer for direct access. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] ackBuffer A pointer to a uint8_t pointer that will be + * updated to the RAM base address of the TXACK buffer. + * @param[in,out] ackBufferBytes A pointer to a uint16_t that will be + * updated to the size of the TXACK buffer, in bytes, which is + * currently \ref RAIL_AUTOACK_MAX_LENGTH. + * @return Status code indicating success of the function call. + * + * Applications can use this to more flexibly write AutoAck data into + * the buffer directly and in pieces, passing NULL ackData parameter to + * \ref RAIL_WriteAutoAckFifo() or \ref RAIL_IEEE802154_WriteEnhAck() + * to inform RAIL of its final length. + */ +RAIL_Status_t RAIL_GetAutoAckFifo(RAIL_Handle_t railHandle, + uint8_t **ackBuffer, + uint16_t *ackBufferBytes); + +/** + * Pause/resume RX auto-ACK functionality. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] pause Pause or resume RX auto-ACKing. + * + * When RX auto-ACKing is paused, the radio transitions to default + * state after receiving a packet and does not transmit an ACK. + * When RX auto-ACK is resumed, the radio resumes automatically ACKing + * every successfully received packet. + */ +void RAIL_PauseRxAutoAck(RAIL_Handle_t railHandle, + bool pause); + +/** + * Return whether the RX auto-ACK is paused. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RX auto-ACK is paused, false if not paused. + */ +bool RAIL_IsRxAutoAckPaused(RAIL_Handle_t railHandle); + +/** + * Pause/resume TX auto-ACK functionality. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] pause Pause or resume TX auto-ACKing. + * + * When TX auto-ACKing is paused, the radio transitions to a default + * state after transmitting a packet and does not wait for an ACK. When TX + * auto-ACK is resumed, the radio resumes automatically waiting for + * an ACK after a successful transmit. + */ +void RAIL_PauseTxAutoAck(RAIL_Handle_t railHandle, bool pause); + +/** + * Return whether the TX auto-ACK is paused. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if TX auto-ACK is paused, false if not paused. + */ +bool RAIL_IsTxAutoAckPaused(RAIL_Handle_t railHandle); + +/** + * Modify the upcoming ACK to use the Transmit FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. The call will + * fail if it is too late to modify the outgoing ACK. + * + * This function allows the application to use the normal Transmit FIFO as + * the data source for the upcoming ACK. The ACK modification to use the + * Transmit FIFO only applies to one ACK transmission. + * + * This function only returns true if the following conditions are met: + * - Radio has not already decided to use the ACK buffer AND + * - Radio is either looking for sync, receiving the packet after sync, or in + * the Rx2Tx turnaround before the ACK is sent. + * + * @note The Transmit FIFO must not be used for AutoACK when IEEE 802.15.4, + * Z-Wave, or BLE protocols are active. + */ +RAIL_Status_t RAIL_UseTxFifoForAutoAck(RAIL_Handle_t railHandle); + +/** + * Cancel the upcoming ACK. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. This call will + * fail if it is too late to modify the outgoing ACK. + * + * This function allows the application to cancel the upcoming automatic + * acknowledgment. + * + * This function only returns true if the following conditions are met: + * - Radio has not already decided to transmit the ACK AND + * - Radio is either looking for sync, receiving the packet after sync or in + * the Rx2Tx turnaround before the ACK is sent. + */ +RAIL_Status_t RAIL_CancelAutoAck(RAIL_Handle_t railHandle); + +/** + * Return whether the radio is currently waiting for an ACK. + * + * @param[in] railHandle A RAIL instance handle. + * @return True if radio is waiting for ACK, false if radio is not waiting for + * an ACK. + * + * This function allows the application to query whether the radio is currently + * waiting for an ACK after a transmit operation. + */ +bool RAIL_IsAutoAckWaitingForAck(RAIL_Handle_t railHandle); + +/** @} */ // end of group Auto_Ack + +/****************************************************************************** + * Calibration + *****************************************************************************/ +/// @addtogroup Calibration +/// @brief APIs for calibrating the radio +/// @{ +/// +/// These APIs calibrate the radio. The RAIL library +/// determines which calibrations are necessary. Calibrations can +/// be enabled/disabled with the RAIL_CalMask_t parameter. +/// +/// Some calibrations produce values that can be saved and reapplied to +/// avoid repeating the calibration process. +/// +/// Calibrations can either be run with \ref RAIL_Calibrate, or with the +/// individual chip-specific calibration routines. An example for running code +/// with \ref RAIL_Calibrate looks like the following: +/// +/// @code{.c} +/// static RAIL_CalValues_t calValues = RAIL_CALVALUES_UNINIT; +/// +/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { +/// // Omitting other event handlers +/// if (events & RAIL_EVENT_CAL_NEEDED) { +/// // Run all pending calibrations, and save the results +/// RAIL_Calibrate(railHandle, &calValues, RAIL_CAL_ALL_PENDING); +/// } +/// } +/// @endcode +/// +/// Alternatively, if the image rejection calibration for your chip can be +/// determined ahead of time, such as by running the calibration on a separate +/// firmware image on each chip, the following calibration process will +/// result in smaller code. +/// +/// @code{.c} +/// static uint32_t imageRejection = IRCAL_VALUE; +/// +/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { +/// // Omitting other event handlers +/// if (events & RAIL_EVENT_CAL_NEEDED) { +/// RAIL_CalMask_t pendingCals = RAIL_GetPendingCal(railHandle); +/// // Disable the radio if we have to do an offline calibration +/// if (pendingCals & RAIL_CAL_TEMP_VC0) { +/// RAIL_CalibrateTemp(railHandle); +/// } +/// if (pendingCals & RAIL_CAL_ONETIME_IRCAL) { +/// RAIL_ApplyIrCalibration(railHandle, imageRejection); +/// } +/// } +/// } +/// @endcode + +/** + * Initialize RAIL calibration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] calEnable A bitmask that indicates which calibrations + * to enable for a callback notification. + * The exact meaning of these bits is chip-specific. + * @return Status code indicating success of the function call. + * + * Calibration initialization provides the calibration settings that + * correspond to the current radio configuration. + */ +RAIL_Status_t RAIL_ConfigCal(RAIL_Handle_t railHandle, + RAIL_CalMask_t calEnable); + +/** + * Start the calibration process. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] calValues A structure of calibration values to apply. + * If a valid calibration structure is provided and the structure + * contains valid calibration values, those values will be applied to the + * hardware and the RAIL library will cache those values for use again later. + * If a valid calibration structure is provided and the structure + * contains a calibration value of \ref RAIL_CAL_INVALID_VALUE for the + * desired calibration, the desired calibration will run, the calibration + * values structure will be updated with a valid calibration value, and the + * RAIL library will cache that value for use again later. + * If a NULL pointer is provided, the desired calibration will run + * and the RAIL library will cache that value for use again later. However, + * the valid calibration value will not be returned to the application. + * @param[in] calForce A mask to force specific calibration(s) to execute. + * To run all pending calibrations, use the value \ref RAIL_CAL_ALL_PENDING. + * Only the calibrations specified will run, even if not enabled during + * initialization. + * @return Status code indicating success of the function call. + * + * If calibrations were performed previously and the application saves the + * calibration values (i.e., call this function with a calibration values + * structure containing calibration values of \ref RAIL_CAL_INVALID_VALUE + * before a reset), the application can later bypass the time it would normally + * take to recalibrate hardware by reusing previous calibration values (i.e., + * call this function with a calibration values structure containing valid + * calibration values after a reset). + * + * If multiple protocols are used, this function will make the given railHandle + * active, if not already, and perform calibration. If called during a protocol + * switch, to perform an IR calibration for the first time, it will + * return \ref RAIL_STATUS_INVALID_STATE, in which case the application must + * defer calibration until after the protocol switch is complete. Silicon Labs + * recommends calling this function from the application main loop. + * + * @note Instead of this function, consider using the individual chip-specific + * functions. Using the individual functions will allow for better + * dead-stripping if not all calibrations are run. + * @note Some calibrations should only be executed when the radio is IDLE. See + * chip-specific documentation for more details. + */ +RAIL_Status_t RAIL_Calibrate(RAIL_Handle_t railHandle, + RAIL_CalValues_t *calValues, + RAIL_CalMask_t calForce); + +/** + * Return the current set of pending calibrations. + * + * @param[in] railHandle A RAIL instance handle. + * @return A mask of all pending calibrations that the user has been asked to + * perform. + * + * This function returns a full set of pending calibrations. The only way + * to clear pending calibrations is to perform them using the \ref + * RAIL_Calibrate() API with the appropriate list of calibrations. + */ +RAIL_CalMask_t RAIL_GetPendingCal(RAIL_Handle_t railHandle); + +/** + * Apply a given image rejection calibration value. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] imageRejection The image rejection value to apply. + * @return A status code indicating success of the function call. + * + * Take an image rejection calibration value and apply it. This value should be + * determined from a previous run of \ref RAIL_CalibrateIr on the same + * physical device with the same radio configuration. The imageRejection value + * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. + * + * If multiple protocols are used, this function will return + * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is + * not active. In that case, the caller must attempt to re-call this function later. + * + * @deprecated Please use \ref RAIL_ApplyIrCalibrationAlt instead. + */ +RAIL_Status_t RAIL_ApplyIrCalibration(RAIL_Handle_t railHandle, + uint32_t imageRejection); + +/** + * Apply a given image rejection calibration value. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] imageRejection Pointer to the image rejection value to apply. + * @param[in] rfPath RF path to calibrate. + * @return A status code indicating success of the function call. + * + * Take an image rejection calibration value and apply it. This value should be + * determined from a previous run of \ref RAIL_CalibrateIrAlt on the same + * physical device with the same radio configuration. The imageRejection value + * will also be stored to the \ref RAIL_ChannelConfigEntry_t::attr, if possible. + * @note: To make sure the imageRejection value is stored/configured correctly, + * \ref RAIL_ConfigAntenna should be called before calling this API. + * + * If multiple protocols are used, this function will return + * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is + * not active. In that case, the caller must attempt to re-call this function later. + */ +RAIL_Status_t RAIL_ApplyIrCalibrationAlt(RAIL_Handle_t railHandle, + RAIL_IrCalValues_t *imageRejection, + RAIL_AntennaSel_t rfPath); + +/** + * Run the image rejection calibration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] imageRejection The result of the image rejection calibration. + * @return A status code indicating success of the function call. + * + * Run the image rejection calibration and apply the resulting value. If the + * imageRejection parameter is not NULL, store the value at that + * location. The imageRejection value will also be stored to the + * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running + * calibration that adds significant code space when run and can be run with a + * separate firmware image on each device to save code space in the + * final image. + * + * If multiple protocols are used, this function will make the given railHandle + * active, if not already, and perform calibration. If called during a protocol + * switch, it will return \ref RAIL_STATUS_INVALID_STATE. In this case, + * \ref RAIL_ApplyIrCalibration may be called to apply a previously determined + * IR calibration value, or the app must defer calibration until the + * protocol switch is complete. Silicon Labs recommends calling this function + * from the application main loop. + * + * @deprecated Please use \ref RAIL_CalibrateIrAlt instead. + */ +RAIL_Status_t RAIL_CalibrateIr(RAIL_Handle_t railHandle, + uint32_t *imageRejection); + +/** + * Run the image rejection calibration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] imageRejection Pointer to the image rejection result. + * @param[in] rfPath RF path to calibrate. + * @return A status code indicating success of the function call. + * + * Run the image rejection calibration and apply the resulting value. If the + * imageRejection parameter is not NULL, store the value at that + * location. The imageRejection value will also be stored to the + * \ref RAIL_ChannelConfigEntry_t::attr, if possible. This is a long-running + * calibration that adds significant code space when run and can be run with a + * separate firmware image on each device to save code space in the + * final image. + * @note: To make sure the imageRejection value is stored/configured correctly, + * \ref RAIL_ConfigAntenna should be called before calling this API. + * + * If multiple protocols are used, this function will return + * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is + * not active. In that case, the caller must attempt to re-call this function later. + */ +RAIL_Status_t RAIL_CalibrateIrAlt(RAIL_Handle_t railHandle, + RAIL_IrCalValues_t *imageRejection, + RAIL_AntennaSel_t rfPath); + +/** + * Run the temperature calibration. + * + * @param[in] railHandle A RAIL instance handle. + * @return A status code indicating success of the function call. + * + * Run the temperature calibration, which needs to recalibrate the synth if + * the temperature crosses 0C or the temperature delta since the last + * calibration exceeds 70C while in receive. RAIL will run the VCO calibration + * automatically upon entering receive or transmit states, so the application + * can omit this calibration if the stack re-enters receive or transmit with + * enough frequency to avoid reaching the temperature delta. If the application + * does not calibrate for temperature, it's possible to miss receive packets due + * to a drift in the carrier frequency. + * + * If multiple protocols are used, this function will return + * \ref RAIL_STATUS_INVALID_STATE if it is called and the given railHandle is + * not active. In that case, the calibration will be automatically performed + * next time the radio enters receive. + */ +RAIL_Status_t RAIL_CalibrateTemp(RAIL_Handle_t railHandle); + +/** + * Performs HFXO compensation. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] crystalPPMError Current deviation that has been corrected, + * measured in PPM. May be NULL. + * @return A status code indicating the result of the function call. + * + * Compute the PPM correction using the thermistor value available when + * \ref RAIL_EVENT_THERMISTOR_DONE occurs, after + * \ref RAIL_StartThermistorMeasurement() call. + * Then correct the RF frequency as well as TX and RX sampling. + * + * This function calls the following RAIL functions in sequence saving having + * to call them individually: + * - \ref RAIL_ConvertThermistorImpedance() + * - \ref RAIL_ComputeHFXOPPMError() + * - \ref RAIL_CompensateHFXO() + * + * @note This function makes the radio idle. + */ +RAIL_Status_t RAIL_CalibrateHFXO(RAIL_Handle_t railHandle, int8_t *crystalPPMError); + +/** + * Enable/disable the PA calibration. + * + * @param[in] enable Enables/disables the PA calibration. + * + * Enabling will ensure that the PA power remains constant chip-to-chip. + * By default, this feature is disabled after reset. + * + * @note Call this function before \ref RAIL_ConfigTxPower() if this + * feature is desired. + */ +void RAIL_EnablePaCal(bool enable); + +/** @} */ // end of group Calibration + +/****************************************************************************** + * RF Sense Structures + *****************************************************************************/ +/** + * @addtogroup Rf_Sense RF Sense + * @{ + */ + +/** + * Start/stop the RF Sense functionality in Energy Detection Mode for use + * during low-energy sleep modes. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] band The frequency band(s) on which to sense the RF energy. + * To stop RF Sense, specify \ref RAIL_RFSENSE_OFF. + * @param[in] senseTime The time (in microseconds) the RF energy must be + * continually detected to be considered "sensed". + * @param[in] cb \ref RAIL_RfSense_CallbackPtr_t is called when the RF is + * sensed. Set null if polling via \ref RAIL_IsRfSensed(). + * @return The actual senseTime used, which may be different than + * requested due to limitations of the hardware. If 0, RF sense was + * disabled or could not be enabled (no callback will be issued). + * + * The EFR32 has the ability to sense the presence of RF Energy above -20 dBm + * within either or both the 2.4 GHz and Sub-GHz bands and trigger an event + * if that energy is continuously present for certain durations of time. + * + * @note After RF energy has been sensed, the RF Sense is automatically + * disabled and \ref RAIL_StartRfSense() must be called again to reactivate it. + * If RF energy has not been sensed and to manually disable RF Sense, + * \ref RAIL_StartRfSense() must be called with band specified as + * \ref RAIL_RFSENSE_OFF or with senseTime set to 0 microseconds. + * + * @note Packet reception is not guaranteed to work correctly once RF Sense is + * enabled, both in single protocol and multiprotocol RAIL. + * To be safe, an application should turn this on only after idling + * the radio to stop receive and turn it off before attempting to restart + * receive. Since EM4 sleep causes the chip to come up through the reset + * vector any wake from EM4 must also shut off RF Sense to ensure proper + * receive functionality. + * + * @warning For some chips, RF Sense functionality is only guaranteed within + * a specified temperature range. + * See chip-specific documentation for more details. + */ +RAIL_Time_t RAIL_StartRfSense(RAIL_Handle_t railHandle, + RAIL_RfSenseBand_t band, + RAIL_Time_t senseTime, + RAIL_RfSense_CallbackPtr_t cb); + +/// Start/stop the RF Sense functionality in Selective(OOK Based) Mode for use +/// during low-energy sleep modes. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @param[in] config \ref RAIL_RfSenseSelectiveOokConfig_t holds the RFSENSE +/// configuration for Selective(OOK) mode. +/// @return Status code indicating success of the function call. +/// +/// Some chips support Selective RF energy detection (OOK mode) where the +/// user can program the chip to look for a particular sync word pattern +/// (1byte - 4bytes) sent using OOK and wake only when that is detected. +/// See chip-specific documentation for more details. +/// +/// The following code gives an example of how to use RF Sense functionality +/// in Selective(OOK Based) Mode. +/// @code{.c} +/// +/// // Syncword Length in bytes, 1-4 bytes. +/// #define NUMSYNCWORDBYTES (2U) +/// // Syncword Value. +/// #define SYNCWORD (0xB16FU) +/// +/// // Configure the transmitting node for sending the wakeup packet. +/// RAIL_Idle(railHandle, RAIL_IDLE_ABORT, true); +/// RAIL_ConfigRfSenseSelectiveOokWakeupPhy(railHandle); +/// RAIL_SetRfSenseSelectiveOokWakeupPayload(railHandle, NUMSYNCWORDBYTES, SYNCWORD); +/// RAIL_StartTx(railHandle, channel, RAIL_TX_OPTIONS_DEFAULT, NULL); +/// +/// // Configure the receiving node (EFR32XG22) for RF Sense. +/// RAIL_RfSenseSelectiveOokConfig_t config = { +/// .band = rfBand, +/// .syncWordNumBytes = NUMSYNCWORDBYTES, +/// .syncWord = SYNCWORD, +/// .cb = &RAILCb_SensedRf +/// }; +/// RAIL_StartSelectiveOokRfSense(railHandle, &config); +/// +/// @endcode +/// +/// @note After RF energy has been sensed, the RF Sense is automatically +/// disabled and \ref RAIL_StartSelectiveOokRfSense() must be called again to +/// reactivate. If RF energy has not been sensed and to manually disable +/// RF Sense, \ref RAIL_StartSelectiveOokRfSense() must be called with band +/// specified as \ref RAIL_RFSENSE_OFF or with +/// \ref RAIL_RfSenseSelectiveOokConfig_t as NULL. +/// +/// @note Packet reception is not guaranteed to work correctly once RF Sense is +/// enabled, both in single protocol and multiprotocol RAIL. +/// To be safe, an application should turn this on only after idling +/// the radio to stop receive and turn it off before attempting to restart +/// receive. Since EM4 sleep causes the chip to come up through the reset +/// vector any wake from EM4 must also shut off RF Sense to ensure proper +/// receive functionality. +/// +RAIL_Status_t RAIL_StartSelectiveOokRfSense(RAIL_Handle_t railHandle, + RAIL_RfSenseSelectiveOokConfig_t *config); + +/** + * Switch to RF Sense Selective(OOK) PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * This function switches to the RFSENSE Selective(OOK) PHY for transmitting a + * packet to wake up a chip that supports Selective RF energy detection (OOK + * mode). You may only call this function while the radio is idle. While the + * radio is configured for this PHY, receive functionality should not be used. + * + * @note The user must also set up the transmit FIFO, via + * \ref RAIL_SetRfSenseSelectiveOokWakeupPayload, post this function call to + * include the first byte as the Preamble Byte, followed by the + * Syncword (1byte - 4bytes). + * See chip-specific documentation for more details. + */ +RAIL_Status_t RAIL_ConfigRfSenseSelectiveOokWakeupPhy(RAIL_Handle_t railHandle); + +/** + * Set the transmit payload for waking up a node configured for + * RF Sense Selective(OOK). + * + * @param[in] railHandle A handle for RAIL instance. + * @param[in] numSyncwordBytes Syncword Length in bytes, 1-4 bytes. + * @param[in] syncword Syncword Value. + * @return A status code indicating success of the function call. + * + * @note You must call this function after the chip has been set up with the + * RF Sense Selective(OOK) PHY, using \ref RAIL_ConfigRfSenseSelectiveOokWakeupPhy. + * + */ +RAIL_Status_t RAIL_SetRfSenseSelectiveOokWakeupPayload(RAIL_Handle_t railHandle, + uint8_t numSyncwordBytes, + uint32_t syncword); + +/** + * Check whether the RF was sensed. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RF was sensed since the last call to \ref RAIL_StartRfSense. + * False otherwise. + * + * This function is useful if \ref RAIL_StartRfSense is called with a null + * callback. It is generally used after EM4 reboot but can be used any time. + */ +bool RAIL_IsRfSensed(RAIL_Handle_t railHandle); + +/** @} */ // end of group Rf_Sense + +/****************************************************************************** + * RX Channel Hopping + *****************************************************************************/ +/** + * @addtogroup Rx_Channel_Hopping RX Channel Hopping + * @brief Hardware accelerated hopping between channels while waiting for a + * packet in receive. + * @{ + * + * Channel hopping provides a hardware accelerated method for + * scanning across multiple channels quickly, as part of a receive protocol. + * While it is possible to call \ref RAIL_StartRx on different channels, + * back to back, and listen on many channels sequentially in that way, the + * time it takes to switch channels with that method may be too long for some + * protocols. This API pre-computes necessary channel change operations + * for a given list of channels, so that the radio can move from channel + * to channel much faster. Additionally, it leads to more succinct code + * as channel changes will be done implicitly, without requiring numerous calls + * to \ref RAIL_StartRx. Currently, while this feature is enabled, the radio + * will hop channels in the given sequence each time it enters RX. + * Note that RX Channel hopping and EFR32xG25's concurrent mode / collision + * detection are mutually exclusive. + * + * The channel hopping buffer requires RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL + * number of 32-bit words of overhead per channel, plus 3 words overall plus the + * twice the size of the radioConfigDeltaSubtract of the whole radio configuration, + * plus the twice the sum of the sizes of all the radioConfigDeltaAdds of + * all the channel hopping channels. + * + * The following code gives an example of how to use + * the RX Channel Hopping API. + * @code{.c} + * + + * #define CHANNEL_HOPPING_NUMBER_OF_CHANNELS 4 + * #define CHANNEL_HOPPING_BUFFER_SIZE do { \ + * 3 + \ + * (RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ + * * CHANNEL_HOPPING_NUMBER_OF_CHANNELS) + \ + * 2 * (SIZEOF_UINT32_DELTA_SUBTRACT + \ + * SIZEOF_UINT32_DELTA_ADD_0 + \ + * SIZEOF_UINT32_DELTA_ADD_1 + \ + * SIZEOF_UINT32_DELTA_ADD_2 + \ + * SIZEOF_UINT32_DELTA_ADD_3) \ + * } while (0) + * + * RAIL_RxChannelHoppingConfigEntry_t channelHoppingEntries[CHANNEL_HOPPING_NUMBER_OF_CHANNELS]; + * uint32_t channelHoppingBuffer[CHANNEL_HOPPING_BUFFER_SIZE]; + * + * RAIL_RxChannelHoppingConfig_t channelHoppingConfig = { + * .buffer = channelHoppingBuffer, + * .bufferLength = CHANNEL_HOPPING_BUFFER_SIZE, + * .numberOfChannels = CHANNEL_HOPPING_NUMBER_OF_CHANNELS, + * .entries = channelHoppingEntries + * }; + * + * channelHoppingEntries[0].channel = 1; + * channelHoppingEntries[1].channel = 2; + * channelHoppingEntries[2].channel = 3; + * + * RAIL_ConfigRxChannelHopping(railHandle, &channelHoppingConfig); + * RAIL_EnableRxChannelHopping(railHandle, true, true) + * @endcode + */ + +/** + * Configure RX channel hopping. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config Configuration parameters for RX Channel Hopping. + * @return Status code indicating success of the function call. + * + * Configure channel hopping channels, conditions, and parameters. This + * API must be called before \ref RAIL_EnableRxChannelHopping(). This API must + * never be called while the radio is on with RX Duty Cycle or Channel + * Hopping enabled. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or + * the runtime call \ref RAIL_SupportsChannelHopping() to check whether + * the platform supports this feature. + * + * @note Calling this function will overwrite any settings configured with + * \ref RAIL_ConfigRxDutyCycle. + */ +RAIL_Status_t RAIL_ConfigRxChannelHopping(RAIL_Handle_t railHandle, + RAIL_RxChannelHoppingConfig_t *config); + +/** + * Enable RX channel hopping. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Enable (true) or disable (false) RX Channel Hopping. + * @param[in] reset Start from the first channel of the channel hopping + * sequence (true) or from wherever hopping left off last time the code + * left RX. + * @return Status code indicating success of the function call. + * + * Enable or disable Channel Hopping. Additionally, specify whether hopping + * should be reset to start from the channel at index zero, or continue + * from the channel last hopped to. The radio should not be on when + * this API is called. \ref RAIL_ConfigRxChannelHopping must be called + * successfully before this API is called. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or + * the runtime call \ref RAIL_SupportsChannelHopping() to check whether + * the platform supports this feature. + * + * @note RX Channel Hopping may not be enabled while auto-ACKing is enabled. + * + * @note Calling this function will overwrite any settings configured with + * \ref RAIL_EnableRxDutyCycle. + */ +RAIL_Status_t RAIL_EnableRxChannelHopping(RAIL_Handle_t railHandle, + bool enable, + bool reset); +/** + * Get RSSI of one channel in the channel hopping sequence, during + * channel hopping. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channelIndex Index in the channel hopping sequence of the + * channel of interest + * @return Latest RSSI for the channel at the specified index. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or + * the runtime call \ref RAIL_SupportsChannelHopping() to check whether + * the platform supports this feature. + * + * @note In multiprotocol, this function returns \ref RAIL_RSSI_INVALID + * immediately if railHandle is not the current active \ref RAIL_Handle_t. + * + * @note \ref RAIL_ConfigRxChannelHopping must be called successfully + * before this API is called. + * + * @note When the Z-Wave protocol is active, it is expected that after + * \ref RAIL_ConfigRxChannelHopping is called successfully on EFR32XG1 + * family of chips, running \ref RAIL_GetChannelHoppingRssi() on a 40kbps + * PHY will not work well. Plan to use the 9.6kbps PHY for estimating + * channel noise instead. On EFR32XG2 family of chips, running + * \ref RAIL_GetChannelHoppingRssi() on the 9.6kbps PHY returns the RSSI + * measurement of the 40kpbs PHY. This is because the 9.6kbps PHY has + * trouble with RSSI measurements on EFR32XG2 family of chips. + */ +int16_t RAIL_GetChannelHoppingRssi(RAIL_Handle_t railHandle, + uint8_t channelIndex); + +/// Configure RX duty cycle mode. +/// +/// @param[in] railHandle A RAIL instance handle. +/// @param[in] config Configuration structure to specify duty cycle parameters. +/// @return Status code indicating success of the function call. +/// +/// Configure RX duty cycle mode. With this mode enabled, every time the radio +/// enters RX, it will duty cycle on and off to save power. The duty cycle +/// ratio can be altered dynamically and intelligently by the hardware by +/// staying on longer if a preamble or other packet segments are detected in +/// the air. This API must never be called while the radio is on with RX Duty +/// Cycle or Channel Hopping enabled. +/// For short delays (in the order of microseconds), +/// \ref RAIL_RxDutyCycleConfig_t::delay, this can be used to save receive +/// current while having little impact on the radio performance, for protocols +/// with long preambles. For long delays (in the order of milliseconds or higher) +/// the chip can be put into EM2 energy mode before re-entering RX, +/// to save extra power, with some application hooks as shown below. +/// +/// @code{.c} +/// #include +/// #include +/// +/// extern RAIL_Handle_t railHandle; +/// RAIL_Time_t periodicWakeupUs; +/// +/// void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) { +/// // Omitting other event handlers +/// if (events & RAIL_EVENT_RX_DUTY_CYCLE_RX_END) { +/// // Schedule the next receive. +/// RAIL_ScheduleRxConfig_t rxCfg = { +/// .start = periodicWakeupUs, +/// .startMode = RAIL_TIME_DELAY, +/// .end = 0U, +/// .endMode = RAIL_TIME_DISABLED, +/// .rxTransitionEndSchedule = 0U, +/// .hardWindowEnd = 0U +/// }; +/// +/// RAIL_Idle(railHandle, RAIL_IDLE_ABORT, true); +/// RAIL_ScheduleRx(railHandle, channel, &rxCfg, NULL); +/// } +/// } +/// +/// void main(void) { +/// RAIL_Status_t status; +/// bool shouldSleep = false; +/// +/// // This function depends on your board/chip but it must enable the LFCLK +/// // you intend to use for RTCC sync before we configure sleep as that +/// // function will attempt to auto detect the clock. +/// BoardSetupLFCLK(); +/// // Initialize Power Manager module +/// sl_power_manager_init(); +/// // Initialize RAIL Power Manager +/// RAIL_InitPowerManager(); +/// +/// // Configure sleep for timer synchronization +/// status = RAIL_ConfigSleep(railHandle, RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED); +/// assert(status == RAIL_STATUS_NO_ERROR); +/// +/// // Application main loop +/// while(1) { +/// // ... do normal app stuff and set shouldSleep when we want to sleep +/// if (shouldSleep) { +/// // Let the CPU go to sleep if the system allows it. +/// sl_power_manager_sleep(); +/// } +/// } +/// } +/// @endcode +/// +/// @note This feature/API is not supported on the EFR32XG1 family of chips. +/// Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or +/// the runtime call \ref RAIL_SupportsChannelHopping() to check whether +/// the platform supports this feature. +/// +/// @note Calling this function will overwrite any settings configured with +/// \ref RAIL_ConfigRxChannelHopping. +RAIL_Status_t RAIL_ConfigRxDutyCycle(RAIL_Handle_t railHandle, + const RAIL_RxDutyCycleConfig_t *config); + +/** + * Enable RX duty cycle mode. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Enable (true) or disable (false) RX Duty Cycling. + * @return Status code indicating success of the function call. + * + * Enable or disable RX duty cycle mode. After this is called, the radio + * will begin duty cycling each time it enters RX, based on the + * configuration passed to \ref RAIL_ConfigRxDutyCycle. This API must not + * be called while the radio is on. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_CHANNEL_HOPPING or + * the runtime call \ref RAIL_SupportsChannelHopping() to check whether + * the platform supports this feature. + * + * @note Calling this function will overwrite any settings configured with + * \ref RAIL_EnableRxChannelHopping. + */ +RAIL_Status_t RAIL_EnableRxDutyCycle(RAIL_Handle_t railHandle, + bool enable); + +/** + * Get the default RX duty cycle configuration. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] config An application-provided non-NULL pointer to store + * the default RX duty cycle configuration. + * @return Status code indicating success of the function call. + * Note that RAIL_STATUS_INVALID_PARAMETER will be returned if the current + * channel's radio configuration does not support the requested information. + * + * To save power during RX, an application may want to go to low power as long as + * possible by periodically waking up and trying to + * "sense" if there are any incoming packets. This API returns the recommended + * RX duty cycle configuration, so the application can enter low power mode + * periodically without missing packets. To wake up + * earlier, the application can reduce the delay parameter. + * Note that these value might be different if any configuration / channel has + * changed. + **/ +RAIL_Status_t RAIL_GetDefaultRxDutyCycleConfig(RAIL_Handle_t railHandle, + RAIL_RxDutyCycleConfig_t *config); + +/** @} */ // end of group Rx_Channel_Hopping + +/****************************************************************************** + * Multiprotocol-Specific Functions + *****************************************************************************/ +/** + * @addtogroup Multiprotocol + * @brief Multiprotocol scheduler APIs to support multiple time-sliced PHYs. + * @{ + */ + +/** + * Yield the radio to other configurations. + * + * @param[in] railHandle A RAIL instance handle. + * + * This function is used to indicate that the previous transmit or scheduled + * receive operation has completed. It must be used in multiprotocol RAIL because + * the scheduler assumes that any transmit or receive operation that is started + * can go on indefinitely based on state transitions and your protocol. + * RAIL will not allow a lower priority tasks to run until this is called so it + * can negatively impact performance of those protocols if this is omitted or + * delayed. It is also possible to call the \ref RAIL_Idle() API to + * both terminate the operation and idle the radio. In single protocol RAIL + * this API does nothing, however, if RAIL Power Manager is initialized, + * calling \ref RAIL_YieldRadio after scheduled TX/RX and instantaneous TX + * completion, is required, to indicate to the Power Manager that the the radio + * is no longer busy and can be idled for sleeping. + * + * See \ref rail_radio_scheduler_yield for more details. + */ +void RAIL_YieldRadio(RAIL_Handle_t railHandle); + +/** + * Get the status of the RAIL scheduler. + * + * @param[in] railHandle A RAIL instance handle. + * @return \ref RAIL_SchedulerStatus_t status. + * + * This function can only be called from a callback context after the + * \ref RAIL_EVENT_SCHEDULER_STATUS event occurs. + */ +RAIL_SchedulerStatus_t RAIL_GetSchedulerStatus(RAIL_Handle_t railHandle); + +/** + * Get the status of the RAIL scheduler, specific to the radio operation, + * along with \ref RAIL_Status_t returned by RAIL API invoked by the + * RAIL scheduler. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] pSchedulerStatus An application-provided pointer to store + * \ref RAIL_SchedulerStatus_t status. Can be NULL as long as + * \ref RAIL_Status_t pointer is not NULL. + * @param[out] pRailStatus An application-provided pointer to store + * \ref RAIL_Status_t of the RAIL API invoked by the RAIL scheduler. + * Can be NULL as long as \ref RAIL_SchedulerStatus_t pointer is not NULL. + * @return \ref RAIL_Status_t indicating success of the function call. + * + * This function can only be called from a callback context after the + * \ref RAIL_EVENT_SCHEDULER_STATUS event occurs. + */ +RAIL_Status_t RAIL_GetSchedulerStatusAlt(RAIL_Handle_t railHandle, + RAIL_SchedulerStatus_t *pSchedulerStatus, + RAIL_Status_t *pRailStatus); + +/** + * Change the priority of a specified task type in multiprotocol. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] priority Desired new priority for the railHandle's active task + * @param[in] taskType Type of task whose priority should be updated + * @return \ref RAIL_Status_t indicating success of the function call. + * + * While the application can use this function however it likes, a major use + * case is being able to increase an infinite receive priority while receiving + * a packet. In other words, a given RAIL_Handle_t can maintain a very low + * priority background receive, but upon getting a + * \ref RAIL_EVENT_RX_SYNC1_DETECT_SHIFT or + * \ref RAIL_EVENT_RX_SYNC2_DETECT_SHIFT event, the app can call this function + * to increase the background RX priority to lower the risk another protocol + * might preempt during packet reception. + */ +RAIL_Status_t RAIL_SetTaskPriority(RAIL_Handle_t railHandle, + uint8_t priority, + RAIL_TaskType_t taskType); + +/** + * Get time needed to switch between protocols. + * + * @return \ref RAIL_Time_t Time needed to switch between protocols. + */ +RAIL_Time_t RAIL_GetTransitionTime(void); + +/** + * Set time needed to switch between protocols. Call this API + * only once, before any protocol is initialized via + * \ref RAIL_Init(). Changing this value during normal operation + * can result in improper scheduling behavior. + * + * @param[in] transitionTime Time needed to switch between protocols. + */ +void RAIL_SetTransitionTime(RAIL_Time_t transitionTime); + +/** @} */ // end of group Multiprotocol + +/****************************************************************************** + * Diagnostic + *****************************************************************************/ +/** + * @addtogroup Diagnostic + * @brief APIs for diagnostic and test chip modes + * @{ + */ + +/** + * Configure direct mode for RAIL. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] directModeConfig Configuration structure to specify direct mode + * parameters. Default configuration will be used if NULL is passed. + * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. + * + * This API configures direct mode and should be called before + * calling \ref RAIL_EnableDirectMode(). If this function is not called, the + * following default configuration will be used: \n + * \b EFR32xG1x \n + * Sync Rx : false \n + * Sync Tx : false \n + * TX data in (DIN) : EFR32_PC10 \n + * RX data out (DOUT) : EFR32_PC11 \n + * TX/RX clk out (DCLK) : EFR32_PC9 \n + * \b EFR32xG2x: \n + * Sync Rx : false \n + * Sync Tx : false \n + * TX data in (DIN) : EFR32_PA7 \n + * RX data out (DOUT) : EFR32_PA5 \n + * TX/RX clk out (DCLK) : EFR32_PA6 + * + * @warning This API is not safe to use in a multiprotocol app. + */ +RAIL_Status_t RAIL_ConfigDirectMode(RAIL_Handle_t railHandle, + const RAIL_DirectModeConfig_t *directModeConfig); + +/** + * Enable or disable direct mode for RAIL. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Whether or not to enable direct mode for TX and RX. + * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. + * * + * See \ref RAIL_EnableDirectModeAlt() for more detailed function + * description. + * + * @warning New applications should consider using RAIL_EnableDirectModeAlt() for + * this functionality. + * + * @note This feature is only available on certain devices. + * \ref RAIL_SupportsDirectMode() can be used to check if a particular + * device supports this feature or not. + * + * @warning This API is not safe to use in a true multiprotocol app. + */ +RAIL_Status_t RAIL_EnableDirectMode(RAIL_Handle_t railHandle, + bool enable); + +/** + * Enable or disable direct mode for RAIL. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enableDirectTx Enable direct mode for data being transmitted out + * of the radio. + * @param[in] enableDirectRx Enable direct mode for data being received from the + * radio. + * @return \ref RAIL_STATUS_NO_ERROR on success and an error code on failure. + * + * This API enables or disables the modem and GPIOs for direct mode operation. + * see \ref RAIL_ConfigDirectMode for information on selecting the + * correct hardware configuration. If direct mode is enabled, + * packets are output and input directly to the radio via GPIO + * and RAIL packet handling is ignored. + * + * @note This feature is only available on certain chips. + * \ref RAIL_SupportsDirectMode() can be used to check if a particular + * chip supports this feature or not. + * + * @warning this API is not safe to use in a true multiprotocol app. + */ +RAIL_Status_t RAIL_EnableDirectModeAlt(RAIL_Handle_t railHandle, + bool enableDirectTx, + bool enableDirectRx); + +/** + * Get the radio subsystem clock frequency in Hz. + * + * @param[in] railHandle A RAIL instance handle. + * @return Radio subsystem clock frequency in Hz. + */ +uint32_t RAIL_GetRadioClockFreqHz(RAIL_Handle_t railHandle); + +/** + * Set the crystal tuning. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] tune A chip-dependent crystal capacitor bank tuning parameter. + * @return Status code indicating success of the function call. + * + * Tunes the crystal that the radio depends on to change the location of the + * center frequency for transmitting and receiving. This function will only + * succeed if the radio is idle at the time of the call. + * + * @note This function proportionally affects the entire chip's timing + * across all its peripherals, including radio tuning and channel spacing. + * It is recommended to call this function only when HFXO is not being used, + * as it can cause disturbance on the HFXO frequency. + * A separate function, \ref RAIL_SetFreqOffset(), can be used to adjust + * just the radio tuner without disturbing channel spacing or other chip + * peripheral timing. + * @note On EFR32xG2 series devices, this API sets CTUNEXIANA and internally + * CTUNEXOANA = CTUNEXIANA + delta where delta is set or changed by + * \ref RAIL_SetTuneDelta. The default delta may not be 0 on some devices. + */ +RAIL_Status_t RAIL_SetTune(RAIL_Handle_t railHandle, uint32_t tune); + +/** + * Get the crystal tuning. + * + * @param[in] railHandle A RAIL instance handle. + * @return A chip-dependent crystal capacitor bank tuning parameter. + * + * Retrieves the current tuning value used by the crystal that the radio + * depends on. + * @note On EFR32xG2 series devices, this is the CTUNEXIANA value. + */ +uint32_t RAIL_GetTune(RAIL_Handle_t railHandle); + +/** + * Set the crystal tuning delta. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] delta A chip-dependent crystal capacitor bank tuning delta. + * @return Status code indicating success of the function call. + * + * Set the CTUNEXOANA delta for \ref RAIL_SetTune to use on EFR32xG2 series devices: + * CTUNEXOANA = CTUNEXIANA + delta. This function does not change CTUNE values; + * call \ref RAIL_SetTune to put a new delta into effect. + * + */ +RAIL_Status_t RAIL_SetTuneDelta(RAIL_Handle_t railHandle, int32_t delta); + +/** + * Get the crystal tuning delta on EFR32xG2 series devices. + * + * @param[in] railHandle A RAIL instance handle. + * @return A chip-dependent crystal capacitor bank tuning delta. + * + * Retrieves the current tuning delta used by \ref RAIL_SetTune. + * @note The default delta if \ref RAIL_SetTuneDelta has never been called + * is device-dependent and may not be 0. + */ +int32_t RAIL_GetTuneDelta(RAIL_Handle_t railHandle); + +/** + * Get the frequency offset. + * + * @param[in] railHandle A RAIL instance handle. + * @return Returns the measured frequency offset on a received packet. + * The units are described in the \ref RAIL_FrequencyOffset_t + * documentation. If this returns \ref RAIL_FREQUENCY_OFFSET_INVALID, + * it was called while the radio wasn't active and there is no way + * to get the frequency offset. + * + * Retrieves the measured frequency offset used during the previous + * received packet, which includes the current radio frequency offset + * (see \ref RAIL_SetFreqOffset()). If the chip has not been in RX, + * it returns the nominal radio frequency offset. + * + * @note Changing to any non-idle radio state after reception can cause this + * value to be overwritten so it is safest to capture during packet reception. + */ +RAIL_FrequencyOffset_t RAIL_GetRxFreqOffset(RAIL_Handle_t railHandle); + +/** + * Set the nominal radio frequency offset. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] freqOffset \ref RAIL_FrequencyOffset_t parameter (signed, 2's + * complement). + * @return Status code indicating success of the function call. + * + * This function is used to adjust the radio's tuning frequency slightly up or down. + * It might be used in conjunction with \ref RAIL_GetRxFreqOffset() after + * receiving a packet from a peer to adjust the tuner to better match the + * peer's tuned frequency. + * + * @note Unlike \ref RAIL_SetTune(), which affects the entire chip's + * timing including radio tuning and channel spacing, this function + * only affects radio tuning without disturbing channel spacing or + * other chip peripheral timing. + */ +RAIL_Status_t RAIL_SetFreqOffset(RAIL_Handle_t railHandle, + RAIL_FrequencyOffset_t freqOffset); + +/** + * Start transmitting a stream on a certain channel. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel A channel on which to emit a stream. + * @param[in] mode Choose the stream mode (PN9, and so on). + * @return Status code indicating success of the function call. + * + * Begins streaming onto the given channel. The sources can either be an + * unmodulated carrier wave or an encoded stream of bits from a PN9 source. + * All ongoing radio operations will be stopped before transmission begins. + */ +RAIL_Status_t RAIL_StartTxStream(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_StreamMode_t mode); + +/** + * Start transmitting a stream on a certain channel with the ability to select + * an antenna. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] channel A channel on which to emit a stream. + * @param[in] mode Choose the stream mode (PN9, and so on). + * @param[in] options Choose the TX Antenna option. + * Takes only \ref RAIL_TX_OPTION_ANTENNA0, \ref RAIL_TX_OPTION_ANTENNA1, + * \ref RAIL_TX_OPTIONS_DEFAULT or \ref RAIL_TX_OPTIONS_NONE from the + * \ref RAIL_TxOptions_t. If some other value is used then, transmission + * is possible on any antenna. + * @return Status code indicating success of the function call. + * + * Begins streaming onto the given channel. The sources can either be an + * unmodulated carrier wave or an encoded stream of bits from a PN9 source. + * All ongoing radio operations will be stopped before transmission begins. + */ +RAIL_Status_t RAIL_StartTxStreamAlt(RAIL_Handle_t railHandle, + uint16_t channel, + RAIL_StreamMode_t mode, + RAIL_TxOptions_t options); + +/** + * Stop stream transmission. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * + * Halts the transmission started by RAIL_StartTxStream(). + */ +RAIL_Status_t RAIL_StopTxStream(RAIL_Handle_t railHandle); + +/** + * Stop infinite preamble transmission started and start transmitting the rest + * of the packet. + * + * This function is only useful for radio configurations that specify an + * infinite preamble. Call this API only after \ref RAIL_EVENT_TX_STARTED + * has occurred and the radio is transmitting. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call: + * \ref RAIL_STATUS_NO_ERROR if infinite preamble was stopped; + * \ref RAIL_STATUS_INVALID_CALL if the radio isn't configured for infinite + * preamble; + * \ref RAIL_STATUS_INVALID_STATE if the radio isn't transmitting. + */ +RAIL_Status_t RAIL_StopInfinitePreambleTx(RAIL_Handle_t railHandle); + +/** + * Configure the verification of radio memory contents. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] configVerify A configuration structure made available to + * RAIL to perform radio state verification. This structure must be + * allocated in application global read-write memory. RAIL may modify + * fields within or referenced by this structure during its operation. + * @param[in] radioConfig A pointer to a radioConfig that is to be used as a + * white list for verifying memory contents. + * @param[in] cb A callback that notifies the application of a mismatch in + * expected vs actual memory contents. A NULL parameter may be passed in + * if a callback is not provided by the application. + * @return \ref RAIL_STATUS_NO_ERROR if setup of the verification feature + * successfully occurred. + * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided railHandle + * or configVerify structures are invalid. + */ +RAIL_Status_t RAIL_ConfigVerification(RAIL_Handle_t railHandle, + RAIL_VerifyConfig_t *configVerify, + RAIL_RadioConfig_t radioConfig, + RAIL_VerifyCallbackPtr_t cb); + +/** + * Verify radio memory contents. + * + * @param[in,out] configVerify A configuration structure made available to + * RAIL to perform radio state verification. This structure must be + * allocated in application global read-write memory. RAIL may modify + * fields within or referenced by this structure during its operation. + * @param[in] durationUs The duration (in microseconds) for how long memory + * verification should occur before returning to the application. A value of + * RAIL_VERIFY_DURATION_MAX indicates that all memory contents should be + * verified before returning to the application. + * @param[in] restart This flag only has meaning if a previous call of this + * function returned \ref RAIL_STATUS_SUSPENDED. By restarting (true), the + * verification process starts over from the beginning, or by resuming + * where verification left off after being suspended (false), verification + * can proceed towards completion. + * @return \ref RAIL_STATUS_NO_ERROR if the contents of all applicable + * memory locations have been verified. + * \ref RAIL_STATUS_SUSPENDED is returned if the provided test duration + * expired but the time was not sufficient to verify all memory contents. + * By calling \ref RAIL_Verify again, further verification will commence. + * \ref RAIL_STATUS_INVALID_PARAMETER is returned if the provided + * verifyConfig structure pointer is not configured for use by the active + * RAIL handle. + * \ref RAIL_STATUS_INVALID_STATE is returned if any of the verified + * memory contents are different from their reference values. + */ +RAIL_Status_t RAIL_Verify(RAIL_VerifyConfig_t *configVerify, + uint32_t durationUs, + bool restart); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/** + * A global pointer to the memory address of the internal RAIL hardware timer + * that drives the RAIL timebase. + * + * @note The corresponding timer tick value is not adjusted for overflow or the + * clock period, and will simply be a register read. The ticks wrap after + * about 17 minutes since it does not use the full 32-bit range. + * For more details, check the documentation for \ref RAIL_TimerTick_t. + */ +extern const volatile RAIL_TimerTick_t *RAIL_TimerTick; + +/** + * A global pointer to the memory address of the internal RAIL hardware timer + * that captures the latest RX packet reception time. This would not include + * the RX chain delay, so may not be equal to the packet timestamp, passed to + * the application, representing the actual on-air time the packet finished. + * + * @note The corresponding timer tick value is not adjusted for overflow or the + * clock period, and will simply be a register read. The ticks wrap after + * about 17 minutes since it does not use the full 32-bit range. + * For more details, check the documentation for \ref RAIL_TimerTick_t. + */ +extern const volatile RAIL_TimerTick_t *RAIL_RxPacketTimestamp; + +/** + * Get elapsed time, in microseconds, between two \ref RAIL_TimerTick_t ticks. + * + * @param[in] startTick Tick recorded at the start of the operation. + * @param[in] endTick Tick recorded at the end of the operation. + * + * @return Returns the elapsed time, in microseconds, between two timer ticks. + */ +RAIL_Time_t RAIL_TimerTicksToUs(RAIL_TimerTick_t startTick, + RAIL_TimerTick_t endTick); + +/** + * Get \ref RAIL_TimerTick_t tick corresponding to the \ref RAIL_Time_t time. + * + * @param[in] microseconds Time in microseconds. + * + * @return Returns the \ref RAIL_TimerTick_t tick corresponding to the + * \ref RAIL_Time_t time. + */ +RAIL_TimerTick_t RAIL_UsToTimerTicks(RAIL_Time_t microseconds); + +/** + * Enable radio state change interrupt. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Enable/disable Radio state change interrupt. + * @return Status code indicating success of the function call. Returns + * \ref RAIL_STATUS_NO_ERROR once the interrupt has been enabled or disabled. + * + * @note If enabled, state change events are reported through the separate + * RAILCb_RadioStateChanged() callback. + */ +RAIL_Status_t RAIL_EnableRadioStateChanged(RAIL_Handle_t railHandle, + bool enable); + +/** + * Get the current radio state. + * + * @param[in] railHandle A RAIL instance handle. + * @return An enumeration, \ref RAIL_RadioStateEfr32_t, for the current radio + * state. + * + */ +RAIL_RadioStateEfr32_t RAIL_GetRadioStateAlt(RAIL_Handle_t railHandle); + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group Diagnostic + +/****************************************************************************** + * Energy Friendly Front End Module (EFF) + *****************************************************************************/ +/** + * @addtogroup EFF Energy Friendly Front End Module (EFF) + * @brief APIs for configuring and controlling an attached Energy Friendly Front + * End Module (EFF). + * + * The EFF is a high-performance, transmit/receive (T/R) front end module (FEM) + * for sub-GHz EFR32 devices. RAIL includes built-in functionality to transmit + * and receive via an attached EFF. This functionality optimizes RF performance + * while ensuring that the EFF stays within safe operating temperature limits. + * + * Configuration and control of the EFF is performed by the \ref rail_util_eff. + * + * @note The EFF is only supported with EFR32XG25 devices. + * @{ + */ + +/** Minimum power for CLPC usage in deci-dBm. Below this power CLPC will not activate. + * Recommend staying above 19 dBm for best performance. Signed unit, do not add U. */ +#define RAIL_CLPC_MINIMUM_POWER 180 + +/** + * Configure the attached EFF device. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @param[in] config A pointer to a \ref RAIL_EffConfig_t struct that contains + * configuration data for the EFF. + * @return Status code indicating success of the function call. + */ + +RAIL_Status_t RAIL_ConfigEff(RAIL_Handle_t genericRailHandle, + const RAIL_EffConfig_t *config); + +/** Number of temperature values provided for the EFF thermal protection */ +#define RAIL_EFF_TEMP_MEASURE_COUNT (6U) +/** Number of deprecated temperature values in EFF thermal protection */ +#define RAIL_EFF_TEMP_MEASURE_DEPRECATED_COUNT (2U) +/** Number of temperature values provided for HFXO metrics */ +#define RAIL_HFXO_TEMP_MEASURE_COUNT (1U) + +/** Total number of temperature values provided by \ref RAIL_GetTemperature(). */ +#define RAIL_TEMP_MEASURE_COUNT (RAIL_CHIP_TEMP_MEASURE_COUNT \ + + RAIL_EFF_TEMP_MEASURE_COUNT \ + + RAIL_EFF_TEMP_MEASURE_DEPRECATED_COUNT \ + + RAIL_HFXO_TEMP_MEASURE_COUNT) + +/** + * Get the different temperature measurements in Kelvin done by sequencer or host. + * Values that are not populated yet or incorrect are set to 0. + * + * Temperatures, in Kelvin, are stored in tempBuffer such as: + * tempBuffer[0] is the chip temperature + * tempBuffer[1] is the minimal chip temperature + * tempBuffer[2] is the maximal chip temperature + * + * If \ref RAIL_SUPPORTS_EFF is defined + * tempBuffer[3] is the EFF temperature before Tx + * tempBuffer[4] is the EFF temperature after Tx + * tempBuffer[5] is the minimal EFF temperature value before Tx + * tempBuffer[6] is the minimal EFF temperature value after Tx + * tempBuffer[7] is the maximal EFF temperature value before Tx + * tempBuffer[8] is the maximal EFF temperature value after Tx + * tempBuffer[9] is not used + * tempBuffer[10] is not used + * + * If \ref RAIL_SUPPORTS_HFXO_COMPENSATION + * tempBuffer[11] is the HFXO temperature + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] tempBuffer The address of the array that will contain temperatures. + * tempBuffer array must be at least \ref RAIL_TEMP_MEASURE_COUNT int16_t. + * @param[in] reset Reset min, max and average temperature values. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetTemperature(RAIL_Handle_t railHandle, + int16_t tempBuffer[RAIL_TEMP_MEASURE_COUNT], + bool reset); + +/** Number of bytes provided by \ref RAIL_GetSetEffClpcControl(). */ +#define RAIL_EFF_CONTROL_SIZE (52U) + +/** + * Get the different EFF Control measurements. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] tempBuffer The address of the target array. + * tempBuffer array must be at least \ref RAIL_EFF_CONTROL_SIZE bytes. + * @param[in] reset Reset the EFF Control measurements. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcControl(RAIL_Handle_t railHandle, + uint16_t tempBuffer[RAIL_EFF_CONTROL_SIZE / sizeof(uint16_t)], + bool reset); + +/** + * Copy the current FEM_DATA pin values into newMode. If changeMode is true, + * update FEM_DATA pin values with newMode first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newMode A pointer to a uint8_t that will contain the FEM_DATA pin values + * @param[in] changeMode If true, use newMode to update FEM_DATA pin values + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcFemdata(RAIL_Handle_t railHandle, + uint8_t *newMode, + bool changeMode); + +/** + * Copy the current Rural to Urban trip voltage into newTrip. If changeTrip is true, + * update current Rural to Urban trip voltage with newTrip first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newTrip A pointer to a uint16_t that will contain the Rural to Urban trip voltage, in millivolts + * @param[in] changeTrip If true, use newTrip to update current Rural to Urban trip voltage + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffLnaRuralUrbanMv(RAIL_Handle_t railHandle, + uint16_t *newTrip, + bool changeTrip); + +/** + * Copy the current Urban to Bypass trip voltage into newTrip. If changeTrip is true, + * update current Urban to Bypass trip voltage with newTrip first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newTrip A pointer to a uint16_t that will contain the Urban to Bypass trip voltage, in millivolts + * @param[in] changeTrip If true, use newTrip to update current Urban to Bypass trip voltage + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffLnaUrbanBypassMv(RAIL_Handle_t railHandle, + uint16_t *newTrip, + bool changeTrip); + +/** + * Copy the current Urban dwell time into newDwellTime. If changeDwellTime is true, + * update current Urban dwell time with newDwellTime first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newDwellTime A pointer to a uint16_t that will contain the Urban dwell + * dwell time, in milliseconds + * @param[in] changeDwellTime If true, use newDwellTime to update current Urban dwell time + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffLnaUrbanDwellTimeMs(RAIL_Handle_t railHandle, + uint32_t *newDwellTime, + bool changeDwellTime); + +/** + * Copy the current Bypass dwell time into newDwellTime. If changeDwellTime is true, + * update current Bypass dwell time with newDwellTime first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newDwellTime A pointer to a uint16_t that will contain the Bypass dwell + * dwell time, in milliseconds + * @param[in] changeDwellTime If true, use newDwellTime to update current Bypass dwell time + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffLnaBypassDwellTimeMs(RAIL_Handle_t railHandle, + uint32_t *newDwellTime, + bool changeDwellTime); + +/** + * If changeValues is true, update current CLPC Fast Loop calibration + * values using the new variables. If false, copy the current CLPC + * Fast Loop calibration values into new variables. + * + * @param[in] railHandle A RAIL instance handle + * @param[in] modeSensorIndex The mode sensor to use for this operation. + * @param[in,out] calibrationEntry The calibration entry to retrieve or update + * @param[in] changeValues If true, use new values to update the CLPC fast loop calibration + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcFastLoopCal(RAIL_Handle_t railHandle, + RAIL_EffModeSensor_t modeSensorIndex, + RAIL_EffCalConfig_t *calibrationEntry, + bool changeValues); + +/** + * If changeValues is true, update current CLPC Fast Loop calibration + * equations using the new variables. If false, copy the current CLPC + * Fast Loop calibration equations into new variables. + * + * @param[in] railHandle A RAIL instance handle + * @param[in] modeSensorIndex The mode sensor to use for this operation. + * @param[in,out] newSlope1e1MvPerDdbm A pointer to a uint16_t that will contain the CLPC Cal slope, in mV/ddBm * 10 + * @param[in,out] newoffset290Ddbm A pointer to a uint16_t that will contain the CLPC Cal offset from 29 dB + * @param[in] changeValues If true, use new values to update the CLPC fast loop calibration equations + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcFastLoopCalSlp(RAIL_Handle_t railHandle, + RAIL_EffModeSensor_t modeSensorIndex, + int16_t *newSlope1e1MvPerDdbm, + int16_t *newoffset290Ddbm, + bool changeValues); + +/** + * If changeValues is true, update current CLPC Fast Loop Target and + * Slope. If false, copy the current CLPC Fast Loop values into + * newTarget and newSlope. + * + * @param[in] railHandle A RAIL instance handle + * @param[in] modeSensorIndex The mode sensor to use for this operation. + * @param[in,out] newTargetMv A pointer to a uint16_t that will contain the CLPC Fast Loop Target in mV + * @param[in,out] newSlopeMvPerPaLevel A pointer to a uint16_t that will contain the CLPC Fast Loop Slope in mV/(PA power level) + * @param[in] changeValues If true, use newTargetMv and newSlopeMvPerPaLevel to update the CLPC Fast Loop values + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcFastLoop(RAIL_Handle_t railHandle, + RAIL_EffModeSensor_t modeSensorIndex, + uint16_t *newTargetMv, + uint16_t *newSlopeMvPerPaLevel, + bool changeValues); + +/** + * Copy the current CLPC Enable in to newClpcEnable. If changeClpcEnable is true, + * update current CLPC Enable with newClpcEnable first. + * + * @param[in] railHandle A RAIL instance handle + * @param[in,out] newClpcEnable A pointer to a uint8_t that will contain the CLPC Enable + * @param[in] changeClpcEnable If true, use newClpcEnable to update the current CLPC Enable + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetSetEffClpcEnable(RAIL_Handle_t railHandle, + uint8_t *newClpcEnable, + bool changeClpcEnable); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Get or set the EFF CLPC control flags for internal developer control. + * This interface may change at any time. + * + * @param[in] railHandle A RAIL instance handle + * @param[in] flags Pointer to the location of a single uint8_t containing flag values + * @param[in] change If true, use flags to update current EFF CLPC flags + * @return RAIL_Status_t indicating success or failure of the function + */ +RAIL_Status_t RAIL_GetSetEffClpcFlags(RAIL_Handle_t railHandle, + uint8_t *flags, + bool change); +#endif + +/** + * Get and set the EFF temperature threshold. + * + * The EFR32 device periodically takes temperature measurements of the attached + * EFF device. If the EFF temperature ever exceeds the EFF temperature + * threshold, any active transmit operation is aborted and future transmit + * operations are blocked until the EFF temperature falls below the threshold. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] newThresholdK A pointer to a uint16_t that will contain the + * current EFF temperature threshold, in Kelvin. + * @param[in] changeThreshold If true, use newThresholdK to update + * current EFF temperature threshold. + * @return Status code indicating the result of the function call. + */ +RAIL_Status_t RAIL_GetSetEffTempThreshold(RAIL_Handle_t railHandle, + uint16_t *newThresholdK, + bool changeThreshold); + +/** @} */ // end of group EFF + +/****************************************************************************** + * Thermal Protection + *****************************************************************************/ +/** + * @addtogroup Thermal_Protection Thermal Protection + * @{ + */ + +/** + * Enable or disable the thermal protection if \ref RAIL_SUPPORTS_THERMAL_PROTECTION + * is defined and update the temperature threshold and cool down hysteresis preventing or + * allowing transmissions. + * + * When the temperature threshold minus a precise number of degrees + * specified by the cool down hysteresis parameter is exceeded, + * any future transmits are blocked until the temperature decreases below that limit. + * Besides, if the temperature threshold is exceeded, any active transmit is aborted. + * + * By default the threshold is set to \ref RAIL_CHIP_TEMP_THRESHOLD_MAX and + * the cool down hysteresis is set to \ref RAIL_CHIP_TEMP_COOLDOWN_DEFAULT. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @param[in] chipTempConfig A pointer to the struct \ref RAIL_ChipTempConfig_t that contains + * the configuration to be applied. + * @return Status code indicating the result of the function call. + * Returns RAIL_STATUS_INVALID_PARAMETER if enable field from \ref RAIL_ChipTempConfig_t + * is set to false when an EFF is present on the board. + * + * @note The thermal protection is automatically enabled when an EFF is present + * on the board. There is no use in calling this API in this case. + */ +RAIL_Status_t RAIL_ConfigThermalProtection(RAIL_Handle_t genericRailHandle, + const RAIL_ChipTempConfig_t *chipTempConfig); + +/** + * Get the current thermal configuration parameter and status. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @param[in,out] chipTempConfig A pointer to the struct \ref RAIL_ChipTempConfig_t that will contain + * the current configuration. + * @return Status code indicating the result of the function call. + */ +RAIL_Status_t RAIL_GetThermalProtection(RAIL_Handle_t genericRailHandle, + RAIL_ChipTempConfig_t *chipTempConfig); + +/** @} */ // end of group Thermal_Protection + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/****************************************************************************** + * Debug + *****************************************************************************/ +/** + * @addtogroup Debug + * @brief APIs for debugging + * @{ + */ + +/** + * Configure the debug mode for the radio library. Do not use this function + * unless instructed by Silicon Labs. + * @param[in] railHandle A RAIL instance handle. + * @param[in] debugMode Debug mode to enter. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_SetDebugMode(RAIL_Handle_t railHandle, uint32_t debugMode); + +/** + * Return the debug mode for the radio library. Do not use this function + * unless instructed by Silicon Labs. + * @param[in] railHandle A RAIL instance handle. + * @return Debug mode for the radio library. + */ +uint32_t RAIL_GetDebugMode(RAIL_Handle_t railHandle); + +/** + * Override the radio base frequency. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] freq A desired frequency in Hz. + * @return Status code indicating success of the function call. + * + * Sets the radio to transmit at the frequency given. This function can only + * be used while in \ref RAIL_DEBUG_MODE_FREQ_OVERRIDE. The given frequency + * needs to be close to the base frequency of the current PHY. After this + * call, a full reset is needed to restore normal RAIL operation. + */ +RAIL_Status_t RAIL_OverrideDebugFrequency(RAIL_Handle_t railHandle, + uint32_t freq); + +/** + * Get the size of the radio's multiprotocol scheduler state buffer. + * + * @param[in] genericRailHandle A generic RAIL instance handle. + * @return Size, in bytes, of the radio's internal scheduler state buffer. + * Zero is returned if the handle is invalid or this is the singleprotocol + * library. + */ +uint32_t RAIL_GetSchedBufferSize(RAIL_Handle_t genericRailHandle); + +/** @} */ // end of group Debug + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/****************************************************************************** + * Assertion Callback + *****************************************************************************/ +/** + * @addtogroup Assertions + * @brief Callbacks called by assertions + * + * The assertion framework was implemented to not only + * assert that certain conditions are true in a block of code, but also + * to handle them more appropriately. In previous implementations, + * the behavior upon a failed assert was to hang in a while(1) loop. + * However, with the callback, each assert is given a unique error code so that + * they can be handled on a more case-by-case basis. For documentation on each + * of the errors, see the rail_assert_error_codes.h file. + * RAIL_ASSERT_ERROR_MESSAGES[errorCode] gives the explanation of the error. + * With asserts built into the library, users can choose how to handle each + * error inside the callback. + * + * @{ + */ + +/** + * Callback called upon failed assertion. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] errorCode Value passed in by the calling assertion API indicating + * the RAIL error that is indicated by the failing assertion. + */ +void RAILCb_AssertFailed(RAIL_Handle_t railHandle, + RAIL_AssertErrorCodes_t errorCode); + +/** @} */ // end of group Assertions + +/****************************************************************************** + * External_Thermistor + *****************************************************************************/ +/** + * @addtogroup External_Thermistor External Thermistor + * @brief APIs to measure temperature using an external thermistor + * + * This feature allows reading the temperature via an external thermistor on + * chips that support it. This will require connecting the necessary components + * and configuring the pins as required. + * + * @{ + */ + +/** + * Start a thermistor measurement. To get the thermistor impedance, call the + * function \ref RAIL_GetThermistorImpedance. On platforms having + * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR, this function reconfigures + * GPIO_THMSW_EN_PIN located in GPIO_THMSW_EN_PORT. + * To locate this pin, refer to the data sheet or appropriate header files + * of the device. For proper operation, \ref RAIL_Init must be called before + * using this function. + * + * @note This function is not designed for safe usage in multiprotocol + * applications. + * @note When an EFF is attached, this function must not be called during + * transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * Returns RAIL_STATUS_INVALID_STATE if the thermistor is started while the + * radio is transmitting. + */ +RAIL_Status_t RAIL_StartThermistorMeasurement(RAIL_Handle_t railHandle); + +/** + * Get the thermistor impedance measurement and return \ref + * RAIL_INVALID_THERMISTOR_VALUE if the thermistor is not properly + * configured or the thermistor measurement is not ready. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] thermistorImpedance Current thermistor impedance measurement in + * Ohms. + * @return Status code indicating success of the function call. + * + * @note This function is already called in \ref RAIL_CalibrateHFXO(). + * It does not need to be manually called during the compensation sequence. + */ +RAIL_Status_t RAIL_GetThermistorImpedance(RAIL_Handle_t railHandle, + uint32_t *thermistorImpedance); + +/** + * Convert the thermistor impedance into temperature, in Celsius. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] thermistorImpedance Current thermistor impedance measurement in + * Ohms. + * @param[out] thermistorTemperatureC Pointer to current thermistor temperature + * in eighth of Celsius degree + * @return Status code indicating success of the function call. + * + * A version of this function is provided in the \ref rail_util_thermistor + * plugin for Silicon Labs radio boards. For custom boards this function can be + * modified and re-implemented as needed. + * + * The variable railHandle is only used to indicate to the user from where the + * function was called, so it is okay to use either a real protocol handle, + * or one of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. + * + * @note This plugin is mandatory on EFR32xG25 platform. + */ +RAIL_Status_t RAIL_ConvertThermistorImpedance(RAIL_Handle_t railHandle, + uint32_t thermistorImpedance, + int16_t *thermistorTemperatureC); + +/** + * Compute the crystal PPM deviation from the thermistor temperature. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] crystalTemperatureC Current crystal temperature. + * @param[out] crystalPPMError Pointer to current ppm error. + * @return Status code indicating success of the function call. + * + * This function is provided in the rail_util_thermistor plugin to get + * accurate values from our boards thermistor. For a custom board, this + * function could be modified and re-implemented for other needs. + * The variable railHandle is only used to indicate to the user from where the + * function was called, so it is okay to use either a real protocol handle, + * or one of the chip-specific ones, such as \ref RAIL_EFR32_HANDLE. + * + * @note This plugin is mandatory on EFR32xG25 platform. + */ +RAIL_Status_t RAIL_ComputeHFXOPPMError(RAIL_Handle_t railHandle, + int16_t crystalTemperatureC, + int8_t *crystalPPMError); + +/** + * Configure the GPIO for thermistor usage. + * + * @param railHandle A RAIL instance handle. + * @param[in] pHfxoThermistorConfig The thermistor configuration pointing to + * the GPIO port and pin to access. + * @return Status code indicating the result of the function call. + * + * @note The port and pin that must be passed in \ref RAIL_HFXOThermistorConfig_t + * are GPIO_THMSW_EN_PORT and GPIO_THMSW_EN_PIN respectively. + */ +RAIL_Status_t RAIL_ConfigHFXOThermistor(RAIL_Handle_t railHandle, + const RAIL_HFXOThermistorConfig_t *pHfxoThermistorConfig); + +/** + * Configure the temperature parameters for HFXO compensation. + * + * @param railHandle A RAIL instance handle. + * @param[in] pHfxoCompensationConfig HFXO compensation parameters pointing to the + * temperature variations used to trigger a compensation. + * @return Status code indicating the result of the function call. + * + * @note This function must be called after \ref RAIL_ConfigHFXOThermistor to succeed. + * + * In \ref RAIL_HFXOCompensationConfig_t, deltaNominal and deltaCritical define + * the temperature variation triggering a new compensation. + * The field zoneTemperatureC defines the temperature separating + * the nominal case (below) from the critical one (above). + * + * When enabled and either deltaNominal or deltaCritical are exceeded, RAIL raises + * event \ref RAIL_EVENT_CAL_NEEDED with \ref RAIL_CAL_TEMP_HFXO bit set. + * The API \ref RAIL_StartThermistorMeasurement() must be called afterwards. + * The latter will raise RAIL_EVENT_THERMISTOR_DONE with calibration bit + * \ref RAIL_CAL_COMPENSATE_HFXO set and RAIL_CalibrateHFXO() must follow. + * + * @note Set deltaNominal and deltaCritical to 0 to perform compensation after + * each transmit. + */ +RAIL_Status_t RAIL_ConfigHFXOCompensation(RAIL_Handle_t railHandle, + const RAIL_HFXOCompensationConfig_t *pHfxoCompensationConfig); + +/** + * Get the temperature parameters for HFXO compensation. + * + * @param railHandle A RAIL instance handle. + * @param pHfxoCompensationConfig HFXO compensation parameters pointing to the + * temperature variations used to trigger a compensation. + * @return Status code indicating the result of the function call. + */ +RAIL_Status_t RAIL_GetHFXOCompensationConfig(RAIL_Handle_t railHandle, + RAIL_HFXOCompensationConfig_t *pHfxoCompensationConfig); + +/** + * Compute a frequency offset and compensate HFXO accordingly. + * + * @param railHandle A RAIL instance handle. + * @param crystalPPMError The current ppm error. Positive values indicate the HFXO + * frequency is too high; negative values indicate it's too low. + * @return Status code indicating success of the function call. + * + * @note This function only works for platforms having + * \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR alongside \ref RAIL_SUPPORTS_HFXO_COMPENSATION. + */ +RAIL_Status_t RAIL_CompensateHFXO(RAIL_Handle_t railHandle, int8_t crystalPPMError); +/** @} */ // end of group External_Thermistor + +/** + * @addtogroup Features + * @{ + */ + +/** + * Indicate whether RAIL supports 2.4 GHz band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 2.4 GHz band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_2P4GHZ_BAND. + */ +bool RAIL_Supports2p4GHzBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports SubGHz band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the SubGHz band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SUBGHZ_BAND. + */ +bool RAIL_SupportsSubGHzBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports dual 2.4 GHz and SubGHz band operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the dual band is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_BAND. + */ +bool RAIL_SupportsDualBand(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports bit masked address filtering. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if bit masked address filtering is supported; false otherwise. + * + * Runtime refinement of compile-time + * \ref RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK. + */ +bool RAIL_SupportsAddrFilterAddressBitMask(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports address filter mask information + * for incoming packets in + * \ref RAIL_RxPacketInfo_t::filterMask and + * \ref RAIL_IEEE802154_Address_t::filterMask. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if address filter information is supported; false otherwise + * (in which case \ref RAIL_RxPacketInfo_t::filterMask value is undefined). + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. + */ +bool RAIL_SupportsAddrFilterMask(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports alternate TX power settings. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if alternate TX power settings are supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_ALTERNATE_TX_POWER. + */ +bool RAIL_SupportsAlternateTxPower(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports antenna diversity. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if antenna diversity is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. + * + * @note Certain radio configurations may not support this feature even + * if the chip in general claims to support it. + */ +bool RAIL_SupportsAntennaDiversity(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports AUXADC measurements on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if AUXADC measurements are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_AUXADC. + */ +bool RAIL_SupportsAuxAdc(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports channel hopping on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if channel hopping is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_CHANNEL_HOPPING. + */ +bool RAIL_SupportsChannelHopping(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports direct mode. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_DIRECT_MODE. + */ +bool RAIL_SupportsDirectMode(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports dual sync words. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if dual sync words are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_DUAL_SYNC_WORDS. + * + * @note Certain radio configurations may not support this feature even + * if the chip in general claims to support it. + */ +bool RAIL_SupportsDualSyncWords(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports start to start TX repeats. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if start to start TX repeats are supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_TX_REPEAT_START_TO_START. + */ +bool RAIL_SupportsTxRepeatStartToStart(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports EFF. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if EFF identifier is supported; false otherwise. + */ +bool RAIL_SupportsEff(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports thermistor measurements on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if thermistor measurements are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. + */ +bool RAIL_SupportsExternalThermistor(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports HFXO compensation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if HFXO compensation is supported and + * \ref RAIL_ConfigHFXOThermistor() has been successfully called; + * false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_HFXO_COMPENSATION. + */ +bool RAIL_SupportsHFXOCompensation(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports MFM protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if MFM protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_MFM. + */ +bool RAIL_SupportsMfm(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports OFDM band operation on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if OFDM operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_OFDM_PA. + */ +bool RAIL_SupportsOFDMPA(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports a high-precision LFRCO. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if high-precision LFRCO is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PRECISION_LFRCO. + */ +bool RAIL_SupportsPrecisionLFRCO(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports radio entropy. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if radio entropy is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RADIO_ENTROPY. + */ +bool RAIL_SupportsRadioEntropy(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports RFSENSE Energy Detection Mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RFSENSE Energy Detection Mode is supported; false otherwise. + * + * Runtime refinement of compile-time + * \ref RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION. + */ +bool RAIL_SupportsRfSenseEnergyDetection(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports RFSENSE Selective(OOK) Mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if RFSENSE Selective(OOK) Mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. + */ +bool RAIL_SupportsRfSenseSelectiveOok(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports configurable RSSI threshold + * set by \ref RAIL_SetRssiDetectThreshold(). + * + * @param[in] railHandle A RAIL instance handle. + * @return true if setting configurable RSSI is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD. + */ +bool RAIL_SupportsRssiDetectThreshold(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports RX direct mode data to FIFO. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode data to FIFO is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO. + */ +bool RAIL_SupportsRxDirectModeDataToFifo(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports raw RX data + * sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if direct mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_RX_RAW_DATA. + */ +bool RAIL_SupportsRxRawData(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports SQ-based PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the SQ-based PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_SQ_PHY. + */ +bool RAIL_SupportsSQPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports a particular power mode (PA). + * @note Consider using \ref RAIL_SupportsTxPowerModeAlt to also get the power + * mode's lowest allowed power level. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] powerMode The power mode to check if supported. + * @param[out] pMaxPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that + * if non-NULL will be filled in with the power mode's highest power level + * allowed if this function returns true. + * @return true if the powerMode is supported; false otherwise. + * + * This function has no compile-time equivalent. + */ +bool RAIL_SupportsTxPowerMode(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t powerMode, + RAIL_TxPowerLevel_t *pMaxPowerLevel); + +/** + * Indicate whether this chip supports a particular power mode (PA) and + * provides the maximum and minimum power level for that power mode + * if supported by the chip. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] powerMode A pointer to PA power mode to check if supported. + * For platforms that support \ref RAIL_TX_POWER_MODE_2P4_HIGHEST or + * \ref RAIL_TX_POWER_MODE_SUBGIG_HIGHEST the powerMode is updated + * to the highest corresponding PA available on the chip. + * @param[out] maxPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that + * if non-NULL will be filled in with the power mode's highest power level + * allowed if this function returns true. + * @param[out] minPowerLevel A pointer to a \ref RAIL_TxPowerLevel_t that + * if non-NULL will be filled in with the power mode's lowest power level + * allowed if this function returns true. + * @return true if powerMode is supported; false otherwise. + */ +bool RAIL_SupportsTxPowerModeAlt(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t *powerMode, + RAIL_TxPowerLevel_t *maxPowerLevel, + RAIL_TxPowerLevel_t *minPowerLevel); + +/** + * Indicate whether this chip supports automatic TX to TX transitions. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if TX to TX transitions are supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_TX_TO_TX. + */ +bool RAIL_SupportsTxToTx(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports the BLE protocol on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_BLE. + */ +bool RAIL_SupportsProtocolBLE(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps Non-Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps Non-Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI. + */ +bool RAIL_BLE_Supports1MbpsNonViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI. + */ +bool RAIL_BLE_Supports1MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 1Mbps operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 1Mbps operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_1MBPS. + */ +static inline +bool RAIL_BLE_Supports1Mbps(RAIL_Handle_t railHandle) +{ + bool temp = RAIL_BLE_Supports1MbpsViterbi(railHandle); // Required for MISRA compliance + return (RAIL_BLE_Supports1MbpsNonViterbi(railHandle) + || temp); +} + +/** + * Indicate whether this chip supports BLE 2Mbps Non-Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps Non-Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI. + */ +bool RAIL_BLE_Supports2MbpsNonViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 2Mbps Viterbi PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps Viterbi is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI. + */ +bool RAIL_BLE_Supports2MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE 2Mbps operation. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE 2Mbps operation is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_2MBPS. + */ +static inline +bool RAIL_BLE_Supports2Mbps(RAIL_Handle_t railHandle) +{ + bool temp = RAIL_BLE_Supports2MbpsViterbi(railHandle); // Required for MISRA compliance + return (RAIL_BLE_Supports2MbpsNonViterbi(railHandle) + || temp); +} + +/** + * Indicate whether this chip supports BLE Antenna Switching needed for + * Angle-of-Arrival receives or Angle-of-Departure transmits. + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Antenna Switching is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING. + */ +bool RAIL_BLE_SupportsAntennaSwitching(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE Coded PHY used for Long-Range. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Coded PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CODED_PHY. + */ +bool RAIL_BLE_SupportsCodedPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE CTE (Constant Tone Extension) + * needed for Angle-of-Arrival/Departure transmits. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE CTE is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_CTE. + */ +bool RAIL_BLE_SupportsCte(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Indicate whether this chip supports BLE HADM. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE HADM is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_HADM. + */ +bool RAIL_BLE_SupportsHadm(RAIL_Handle_t railHandle); +#endif + +/** + * Indicate whether this chip supports BLE IQ Sampling needed for + * Angle-of-Arrival/Departure receives. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE IQ Sampling is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_IQ_SAMPLING. + */ +bool RAIL_BLE_SupportsIQSampling(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE PHY switch to RX + * functionality, which is used to switch BLE PHYs at a specific time + * to receive auxiliary packets. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE PHY switch to RX is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. + */ +bool RAIL_BLE_SupportsPhySwitchToRx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Quuppa PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Quuppa is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_QUUPPA. + */ +bool RAIL_BLE_SupportsQuuppa(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE signal identifier. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if signal identifier is supported; false otherwise. + */ +bool RAIL_BLE_SupportsSignalIdentifier(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports BLE Simulscan PHY used for simultaneous + * BLE 1Mbps and Coded PHY reception. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if BLE Simulscan PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY. + */ +bool RAIL_BLE_SupportsSimulscanPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154. + */ +bool RAIL_SupportsProtocolIEEE802154(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Indicate whether this chip supports the IEEE 802.15.4 2Mbps PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 2Mbps PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY. + */ +bool RAIL_IEEE802154_Supports2MbpsPhy(RAIL_Handle_t railHandle); +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Indicate whether this chip supports the IEEE 802.15.4 Wi-Fi Coexistence PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 COEX PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. + */ +bool RAIL_IEEE802154_SupportsCoexPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 2.4 GHz band variant. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if IEEE 802.15.4 2.4 GHz band variant is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_IEEE802154_BAND_2P4. + */ +bool RAIL_SupportsIEEE802154Band2P4(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the thermal protection. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if thermal protection is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_THERMAL_PROTECTION. + */ +bool RAIL_SupportsThermalProtection(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 2.4 RX channel switching. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if IEEE 802.15.4 2.4 GHz RX channel switching is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING. + */ +bool RAIL_IEEE802154_SupportsRxChannelSwitching(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 PHY with custom settings. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the 802.15.4 PHY with custom settings is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY. + */ +bool RAIL_IEEE802154_SupportsCustom1Phy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4 + * front end module optimized PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if a front end module is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY. + */ +bool RAIL_IEEE802154_SupportsFemPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports canceling the frame-pending lookup + * event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND when the radio + * transitions to a state that renders the the reporting of this event moot + * (i.e., too late for the stack to influence the outgoing ACK). + * + * @param[in] railHandle A RAIL instance handle. + * @return true if canceling the lookup event is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. + */ +bool RAIL_IEEE802154_SupportsCancelFramePendingLookup(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports early triggering of the frame-pending + * lookup event \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND + * just after MAC address fields have been received. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if early triggering is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. + */ +bool RAIL_IEEE802154_SupportsEarlyFramePendingLookup(RAIL_Handle_t railHandle); + +/** + * Indicate whether RAIL supports dual PA mode on this chip. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the dual PA mode is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG. + */ +bool RAIL_IEEE802154_SupportsDualPaConfig(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4E-2012 Enhanced ACKing. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4E Enhanced ACKing is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. + */ +bool RAIL_IEEE802154_SupportsEEnhancedAck(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4E-2012 Multipurpose frame + * reception. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Multipurpose frame reception is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. + */ +bool RAIL_IEEE802154_SupportsEMultipurposeFrames(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the IEEE 802.15.4E-2012 feature + * subset needed for Zigbee R22 GB868. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4E GB868 subset is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. + */ +bool RAIL_IEEE802154_SupportsESubsetGB868(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 reception and + * transmission of frames with 4-byte CRC. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G 4-byte CRC is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. + */ +bool RAIL_IEEE802154_SupportsG4ByteCrc(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G dynamic FEC. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if dynamic FEC is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_DYNFEC. + */ +bool RAIL_IEEE802154_SupportsGDynFec(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Wi-SUN. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Wi-SUN is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_SUPPORTS_PROTOCOL_WI_SUN. + */ +bool RAIL_SupportsProtocolWiSUN(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Wi-SUN mode switching. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Wi-SUN mode switching is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_MODESWITCH. + */ +bool RAIL_IEEE802154_SupportsGModeSwitch(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 feature + * subset needed for Zigbee R22 GB868. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G GB868 subset is supported; false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. + */ +bool RAIL_IEEE802154_SupportsGSubsetGB868(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 reception + * of unwhitened frames. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G unwhitened frame reception is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. + */ +bool RAIL_IEEE802154_SupportsGUnwhitenedRx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4G-2012 transmission + * of unwhitened frames. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if 802.15.4G unwhitened frame transmit is supported; + * false otherwise. + * + * Runtime refinement of compile-time \ref + * RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. + */ +bool RAIL_IEEE802154_SupportsGUnwhitenedTx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports WMBUS simultaneous M2O RX of T and C modes. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the WMBUS simultaneous M2O RX of T and C modes is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX. + */ +bool RAIL_WMBUS_SupportsSimultaneousTCRx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. + */ +bool RAIL_SupportsProtocolZWave(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave concurrent PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave concurrent PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_CONC_PHY. + */ +bool RAIL_ZWAVE_SupportsConcPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports the Z-Wave energy detect PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if the Z-Wave energy detect PHY is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_ED_PHY. + */ +bool RAIL_ZWAVE_SupportsEnergyDetectPhy(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Z-Wave Region in PTI. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if ZWAVE Region in PTI is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. + */ +bool RAIL_ZWAVE_SupportsRegionPti(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports IEEE 802.15.4 signal identifier. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if signal identifier is supported; false otherwise. + */ +bool RAIL_IEEE802154_SupportsSignalIdentifier(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports fast RX2RX. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if fast RX2RX is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_FAST_RX2RX. + */ +bool RAIL_SupportsFastRx2Rx(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports collision detection. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if collision detection is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_COLLISION_DETECTION. + */ +bool RAIL_SupportsCollisionDetection(RAIL_Handle_t railHandle); + +/** + * Indicate whether this chip supports Sidewalk protocol. + * + * @param[in] railHandle A RAIL instance handle. + * @return true if Sidewalk protocol is supported; false otherwise. + * + * Runtime refinement of compile-time \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK. + */ +bool RAIL_SupportsProtocolSidewalk(RAIL_Handle_t railHandle); + +/** @} */ // end of group Features + +/** @} */ // end of group RAIL_API + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_assert_error_codes.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_assert_error_codes.h index a4383cc..893acf3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_assert_error_codes.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_assert_error_codes.h @@ -1,437 +1,437 @@ -/***************************************************************************//** - * @file - * @brief Definition of error codes that occur in rail for use in - * RAILCb_AssertFailed. This file is purely informational and optional - - * it need not be included even if rail_assert libraries are included. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_ASSERT_ERROR_CODES_H__ -#define __RAIL_ASSERT_ERROR_CODES_H__ - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup Assertions - * @{ - */ - -/** - * Enumeration of all possible error codes from RAIL_ASSERT - */ -RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) -{ - /** Appended info missing from RX packet. */ - RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING = 0, - /** Receive FIFO too small for IR calibration. */ - RAIL_ASSERT_FAILED_RX_FIFO_BYTES = 1, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_2 = 2, - /** Receive FIFO entry has invalid status. */ - RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS = 3, - /** Receive FIFO entry bad packet length. */ - RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH = 4, - /** Unable to configure radio for IR calibration. */ - RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR = 5, - /** Reached unexpected state while handling RX FIFO events. */ - RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO = 6, - /** Reached unexpected state while handling RXLEN FIFO events. */ - RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO = 7, - /** Reached unexpected state while handling TX FIFO events. */ - RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8, - /** Reached unexpected state while handling TX ACK FIFO events. */ - RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_10 = 10, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_11 = 11, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_12 = 12, - /** Error synchronizing the RAIL timebase after sleep. */ - RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP = 13, - /** VCO frequency outside supported range. */ - RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY = 14, - /** Radio active while changing channels. */ - RAIL_ASSERT_FAILED_RAC_STATE = 15, - /** Invalid Synth VCOCTRL field calculation. */ - RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL = 16, - /** Nested attempt to lock the sequencer. */ - RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK = 17, - /** RSSI averaging enabled without a valid callback. */ - RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE = 18, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_19 = 19, - /** Unable to seed radio pseudo random number generator. */ - RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED = 20, - /** Timeout exceeds EFR32XG1 register size. */ - RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE = 21, - /** Invalid timer channel specified. */ - RAIL_ASSERT_FAILED_PROTIMER_CHANNEL = 22, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_23 = 23, - /** LBT config exceeds EFR32XG1 register size. */ - RAIL_ASSERT_FAILED_BASECNTTOP = 24, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_25 = 25, - /** Could not synchronize RAIL timebase with the RTC. */ - RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED = 26, - /** Clock source not ready. */ - RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY = 27, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_28 = 28, - /** NULL was supplied as a RAIL_Handle_t argument. */ - RAIL_ASSERT_NULL_HANDLE = 29, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_30 = 30, - /** API improperly called while protocol inactive. */ - RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG = 31, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_32 = 32, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_33 = 33, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_34 = 34, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_35 = 35, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_36 = 36, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_37 = 37, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_38 = 38, - /** This function is deprecated and must not be called. */ - RAIL_ASSERT_DEPRECATED_FUNCTION = 39, - /** Multiprotocol task started with no event to run. */ - RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT = 40, - /** Invalid interrupt enabled. */ - RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED = 41, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_42 = 42, - /** Division by zero. */ - RAIL_ASSERT_DIVISION_BY_ZERO = 43, - /** Function cannot be called without access to the hardware. */ - RAIL_ASSERT_CANT_USE_HARDWARE = 44, - /** Pointer parameter was passed as NULL. */ - RAIL_ASSERT_NULL_PARAMETER = 45, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_46 = 46, - /** Synth radio config buffer for channel hopping too small. */ - RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47, - /** Buffer provided for RX Channel Hopping is too small. */ - RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT = 48, - /** Invalid action was attempted on a module. */ - RAIL_ASSERT_INVALID_MODULE_ACTION = 49, - /** The radio config for this channel is not compatible with channel hopping. */ - RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG = 50, - /** Channel change failed. */ - RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51, - /** Attempted to read invalid register. */ - RAIL_ASSERT_INVALID_REGISTER = 52, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_53 = 53, - /** DMP radio config caching failed. */ - RAIL_ASSERT_CACHE_CONFIG_FAILED = 54, - /** NULL was supplied as a RAIL_StateTransitions_t argument. */ - RAIL_ASSERT_NULL_TRANSITIONS = 55, - /** LDMA transfer failed. */ - RAIL_ASSERT_BAD_LDMA_TRANSFER = 56, - /** Attempted to wake up with invalid RTCC sync data. */ - RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES = 57, - /** Radio sequencer hit a fault condition. */ - RAIL_ASSERT_SEQUENCER_FAULT = 58, - /** Bus fault. */ - RAIL_ASSERT_BUS_ERROR = 59, - /** The current radio config cannot be used with packet filtering. */ - RAIL_ASSERT_INVALID_FILTERING_CONFIG = 60, - /** Retiming configuration error. */ - RAIL_ASSERT_RETIMING_CONFIG = 61, - /** TX CRC configuration is corrupt. */ - RAIL_ASSERT_FAILED_TX_CRC_CONFIG = 62, - /** The current PA config does not allow for this operation. */ - RAIL_ASSERT_INVALID_PA_OPERATION = 63, - /** The sequencer selected an invalid PA. */ - RAIL_ASSERT_SEQ_INVALID_PA_SELECTED = 64, - /** Invalid/unsupported channel config. */ - RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG = 65, - /** Radio Calculator configuration HFXO frequency mismatch with chip */ - RAIL_ASSERT_INVALID_XTAL_FREQUENCY = 66, - /** Invalid assert, no longer used. */ - RAIL_ASSERT_UNUSED_67 = 67, - /** Software modem image does not support requested modulation */ - RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION = 68, - /** Failed to disable RTCC synchronization. */ - RAIL_ASSERT_FAILED_RTCC_SYNC_STOP = 69, - /** Multitimer linked list corrupted. */ - RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT = 70, - /** Unable to configure radio for temperature calibration. */ - RAIL_ASSERT_FAILED_TEMPCAL_ERROR = 71, - /** Invalid EFF configuration. */ - RAIL_ASSERT_INVALID_EFF_CONFIGURATION = 72, - /** Invalid RFFPLL configuration. */ - RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION = 73, - /** Secure access fault. */ - RAIL_ASSERT_SECURE_ACCESS_FAULT = 74, - /** SYSRTC0 not running. */ - RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING = 75, - /** Radio Configurator not updated. */ - RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE = 76, - /** Failed to set the event for configurable RSSI threshold. */ - RAIL_ASSERT_FAILED_RSSI_THRESHOLD = 77, - /** Intended and actual Z-Wave region configuration mismatch. */ - RAIL_ASSERT_INCORRECT_ZWAVE_REGION = 78, - /** Attempted to sleep with stale RTCC synchronization data */ - RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA = 79, - /** Attempted to clear LOG2X4 with a DEC1 value not equal to 0 */ - RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION = 80, - /** Failed to complete DMA write */ - RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE = 81, - /** RAIL does not support this Radio Calculator configuration */ - RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED = 82, - /** Invalid binary image was loaded onto the sequencer */ - RAIL_ASSERT_INVALID_SEQUENCER_IMAGE = 83, - /** No common or protocol image selected to be loaded onto the sequencer */ - RAIL_ASSERT_MISSING_SEQUENCER_IMAGE = 84, - /** Software modem image invalid or missing */ - RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE = 85, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING) -#define RAIL_ASSERT_FAILED_RX_FIFO_BYTES ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RX_FIFO_BYTES) -#define RAIL_ASSERT_UNUSED_2 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_2) -#define RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS) -#define RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH) -#define RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR) -#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO) -#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO) -#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO) -#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO) -#define RAIL_ASSERT_UNUSED_10 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_10) -#define RAIL_ASSERT_UNUSED_11 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_11) -#define RAIL_ASSERT_UNUSED_12 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_12) -#define RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP) -#define RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY) -#define RAIL_ASSERT_FAILED_RAC_STATE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RAC_STATE) -#define RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL) -#define RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK) -#define RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE) -#define RAIL_ASSERT_UNUSED_19 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_19) -#define RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED) -#define RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE) -#define RAIL_ASSERT_FAILED_PROTIMER_CHANNEL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_CHANNEL) -#define RAIL_ASSERT_UNUSED_23 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_23) -#define RAIL_ASSERT_FAILED_BASECNTTOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BASECNTTOP) -#define RAIL_ASSERT_UNUSED_25 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_25) -#define RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED) -#define RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY) -#define RAIL_ASSERT_UNUSED_28 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_28) -#define RAIL_ASSERT_NULL_HANDLE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_HANDLE) -#define RAIL_ASSERT_UNUSED_30 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_30) -#define RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG) -#define RAIL_ASSERT_UNUSED_32 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_32) -#define RAIL_ASSERT_UNUSED_33 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_33) -#define RAIL_ASSERT_UNUSED_34 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_34) -#define RAIL_ASSERT_UNUSED_35 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_35) -#define RAIL_ASSERT_UNUSED_36 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_36) -#define RAIL_ASSERT_UNUSED_37 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_37) -#define RAIL_ASSERT_UNUSED_38 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_38) -#define RAIL_ASSERT_DEPRECATED_FUNCTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DEPRECATED_FUNCTION) -#define RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT) -#define RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED) -#define RAIL_ASSERT_UNUSED_42 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_42) -#define RAIL_ASSERT_DIVISION_BY_ZERO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DIVISION_BY_ZERO) -#define RAIL_ASSERT_CANT_USE_HARDWARE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CANT_USE_HARDWARE) -#define RAIL_ASSERT_NULL_PARAMETER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_PARAMETER) -#define RAIL_ASSERT_UNUSED_46 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_46) -#define RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER) -#define RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT) -#define RAIL_ASSERT_INVALID_MODULE_ACTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MODULE_ACTION) -#define RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG) -#define RAIL_ASSERT_CHANNEL_CHANGE_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED) -#define RAIL_ASSERT_INVALID_REGISTER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_REGISTER) -#define RAIL_ASSERT_UNUSED_53 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_53) -#define RAIL_ASSERT_CACHE_CONFIG_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CACHE_CONFIG_FAILED) -#define RAIL_ASSERT_NULL_TRANSITIONS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_TRANSITIONS) -#define RAIL_ASSERT_BAD_LDMA_TRANSFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BAD_LDMA_TRANSFER) -#define RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES) -#define RAIL_ASSERT_SEQUENCER_FAULT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQUENCER_FAULT) -#define RAIL_ASSERT_BUS_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BUS_ERROR) -#define RAIL_ASSERT_INVALID_FILTERING_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_FILTERING_CONFIG) -#define RAIL_ASSERT_RETIMING_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RETIMING_CONFIG) -#define RAIL_ASSERT_FAILED_TX_CRC_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TX_CRC_CONFIG) -#define RAIL_ASSERT_INVALID_PA_OPERATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_PA_OPERATION) -#define RAIL_ASSERT_SEQ_INVALID_PA_SELECTED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQ_INVALID_PA_SELECTED) -#define RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG) -#define RAIL_ASSERT_INVALID_XTAL_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_XTAL_FREQUENCY) -#define RAIL_ASSERT_UNUSED_67 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_67) -#define RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION) -#define RAIL_ASSERT_FAILED_RTCC_SYNC_STOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STOP) -#define RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT) -#define RAIL_ASSERT_FAILED_TEMPCAL_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TEMPCAL_ERROR) -#define RAIL_ASSERT_INVALID_EFF_CONFIGURATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_EFF_CONFIGURATION) -#define RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION) -#define RAIL_ASSERT_SECURE_ACCESS_FAULT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SECURE_ACCESS_FAULT) -#define RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING) -#define RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE) -#define RAIL_ASSERT_FAILED_RSSI_THRESHOLD ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_THRESHOLD) -#define RAIL_ASSERT_INCORRECT_ZWAVE_REGION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INCORRECT_ZWAVE_REGION) -#define RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA) -#define RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION) -#define RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE) -#define RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED) -#define RAIL_ASSERT_INVALID_SEQUENCER_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_SEQUENCER_IMAGE) -#define RAIL_ASSERT_MISSING_SEQUENCER_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MISSING_SEQUENCER_IMAGE) -#define RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/// Use this define to create an array of error messages that map to the codes -/// in \ref RAIL_AssertErrorCodes_t. You can use these to print slightly more -/// detailed error strings related to a particular assert error code if desired. -/// For example, you could implement your assert failed callback as follows to -/// make use of this. -/// -/// @code{.c} -/// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode) -/// { -/// static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES; -/// const char *errorMessage = "Unknown"; -/// -/// // If this error code is within the range of known error messages then use -/// // the appropriate error message. -/// if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) { -/// errorMessage = railErrorMessages[errorCode]; -/// } -/// printf(errorMessage); -/// -/// // Reset the chip since an assert is a fatal error -/// NVIC_SystemReset(); -/// } -/// @endcode -/// -#define RAIL_ASSERT_ERROR_MESSAGES { \ - /* 0*/ "Appended info missing from RX packet", \ - /* 1*/ "Receive FIFO too small for IR calibration", \ - /* 2*/ "Invalid assert, no longer used", \ - /* 3*/ "Receive FIFO entry has invalid status", \ - /* 4*/ "Receive FIFO entry bad packet length", \ - /* 5*/ "Unable to configure radio for IR calibration", \ - /* 6*/ "Reached unexpected state while handling RX FIFO events", \ - /* 7*/ "Reached unexpected state while handling RXLEN FIFO events", \ - /* 8*/ "Reached unexpected state while handling TX FIFO events", \ - /* 9*/ "Reached unexpected state while handling TX ACK FIFO events", \ - /*10*/ "Invalid assert, no longer used", \ - /*11*/ "Invalid assert, no longer used", \ - /*12*/ "Invalid assert, no longer used", \ - /*13*/ "Error synchronizing the RAIL timebase after sleep", \ - /*14*/ "VCO frequency outside supported range", \ - /*15*/ "Radio active while changing channels", \ - /*16*/ "Invalid Synth VCOCTRL field calculation", \ - /*17*/ "Nested attempt to lock the sequencer", \ - /*18*/ "RSSI averaging enabled without a valid callback", \ - /*19*/ "Invalid assert, no longer used", \ - /*20*/ "Unable to seed radio pseudo random number generator", \ - /*21*/ "Timeout exceeds EFR32XG1 register size", \ - /*22*/ "Invalid timer channel specified", \ - /*23*/ "Invalid assert, no longer used", \ - /*24*/ "LBT config exceeds EFR32XG1 register size", \ - /*25*/ "Invalid assert, no longer used", \ - /*26*/ "Could not synchronize RAIL timebase with the RTC", \ - /*27*/ "Clock source not ready", \ - /*28*/ "Invalid assert, no longer used", \ - /*29*/ "NULL was supplied as a RAIL_Handle_t argument", \ - /*30*/ "Invalid assert, no longer used", \ - /*31*/ "API improperly called while protocol inactive", \ - /*32*/ "Invalid assert, no longer used", \ - /*33*/ "Invalid assert, no longer used", \ - /*34*/ "Invalid assert, no longer used", \ - /*35*/ "Invalid assert, no longer used", \ - /*36*/ "Invalid assert, no longer used", \ - /*37*/ "Invalid assert, no longer used", \ - /*38*/ "Invalid assert, no longer used", \ - /*39*/ "This function is deprecated and must not be called", \ - /*40*/ "Multiprotocol task started with no event to run", \ - /*41*/ "Invalid interrupt enabled", \ - /*42*/ "Invalid assert, no longer used", \ - /*43*/ "Division by zero", \ - /*44*/ "Function cannot be called without access to the hardware", \ - /*45*/ "Pointer parameter was passed as NULL", \ - /*46*/ "Invalid assert, no longer used", \ - /*47*/ "Synth radio config buffer for channel hopping too small", \ - /*48*/ "Buffer provided for RX Channel Hopping is too small", \ - /*49*/ "Invalid action was attempted on a module", \ - /*50*/ "The radio config for this channel is not compatible with channel hopping", \ - /*51*/ "Channel change failed", \ - /*52*/ "Attempted to read invalid register", \ - /*53*/ "Invalid assert, no longer used", \ - /*54*/ "DMP radio config caching failed", \ - /*55*/ "NULL was supplied as a RAIL_StateTransitions_t argument", \ - /*56*/ "LDMA transfer failed", \ - /*57*/ "Attempted to wake up with invalid RTCC sync data", \ - /*58*/ "Radio sequencer hit a fault condition", \ - /*59*/ "Bus fault", \ - /*60*/ "The current radio config cannot be used with packet filtering", \ - /*61*/ "Retiming configuration error", \ - /*62*/ "TX CRC configuration is corrupt", \ - /*63*/ "The current PA config does not allow for this operation", \ - /*64*/ "The sequencer selected an invalid PA", \ - /*65*/ "Invalid/unsupported channel config", \ - /*66*/ "Radio Calculator configuration HFXO frequency mismatch with chip", \ - /*67*/ "Invalid assert, no longer used", \ - /*68*/ "Software modem image does not support requested modulation", \ - /*69*/ "Failed to disable RTCC synchronization", \ - /*70*/ "Multitimer linked list corrupted", \ - /*71*/ "Unable to configure radio for temperature calibration", \ - /*72*/ "Invalid EFF configuration", \ - /*73*/ "PHY and System RFFPLL settings do not match", \ - /*74*/ "Secure access fault", \ - /*75*/ "SYSRTC0 not running", \ - /*76*/ "Radio Configurator not updated", \ - /*77*/ "Failed to set the event for configurable RSSI threshold", \ - /*78*/ "Intended and actual Z-Wave region configuration mismatch", \ - /*79*/ "Attempted to sleep with stale RTCC synchronization data", \ - /*80*/ "Attempted to clear LOG2X4 with a DEC1 value not equal to 0", \ - /*81*/ "Failed to complete DMA write", \ - /*82*/ "RAIL does not support this Radio Calculator configuration", \ - /*83*/ "Invalid binary image loaded on sequencer", \ - /*84*/ "No common or protocol image selected to be loaded onto the sequencer", \ - /*85*/ "Software modem image invalid or missing", \ -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_ASSERT_ERROR_CODES_H__ +/***************************************************************************//** + * @file + * @brief Definition of error codes that occur in rail for use in + * RAILCb_AssertFailed. This file is purely informational and optional - + * it need not be included even if rail_assert libraries are included. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_ASSERT_ERROR_CODES_H__ +#define __RAIL_ASSERT_ERROR_CODES_H__ + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup Assertions + * @{ + */ + +/** + * Enumeration of all possible error codes from RAIL_ASSERT + */ +RAIL_ENUM_GENERIC(RAIL_AssertErrorCodes_t, uint32_t) +{ + /** Appended info missing from RX packet. */ + RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING = 0, + /** Receive FIFO too small for IR calibration. */ + RAIL_ASSERT_FAILED_RX_FIFO_BYTES = 1, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_2 = 2, + /** Receive FIFO entry has invalid status. */ + RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS = 3, + /** Receive FIFO entry bad packet length. */ + RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH = 4, + /** Unable to configure radio for IR calibration. */ + RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR = 5, + /** Reached unexpected state while handling RX FIFO events. */ + RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO = 6, + /** Reached unexpected state while handling RXLEN FIFO events. */ + RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO = 7, + /** Reached unexpected state while handling TX FIFO events. */ + RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO = 8, + /** Reached unexpected state while handling TX ACK FIFO events. */ + RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO = 9, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_10 = 10, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_11 = 11, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_12 = 12, + /** Error synchronizing the RAIL timebase after sleep. */ + RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP = 13, + /** VCO frequency outside supported range. */ + RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY = 14, + /** Radio active while changing channels. */ + RAIL_ASSERT_FAILED_RAC_STATE = 15, + /** Invalid Synth VCOCTRL field calculation. */ + RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL = 16, + /** Nested attempt to lock the sequencer. */ + RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK = 17, + /** RSSI averaging enabled without a valid callback. */ + RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE = 18, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_19 = 19, + /** Unable to seed radio pseudo random number generator. */ + RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED = 20, + /** Timeout exceeds EFR32XG1 register size. */ + RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE = 21, + /** Invalid timer channel specified. */ + RAIL_ASSERT_FAILED_PROTIMER_CHANNEL = 22, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_23 = 23, + /** LBT config exceeds EFR32XG1 register size. */ + RAIL_ASSERT_FAILED_BASECNTTOP = 24, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_25 = 25, + /** Could not synchronize RAIL timebase with the RTC. */ + RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED = 26, + /** Clock source not ready. */ + RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY = 27, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_28 = 28, + /** NULL was supplied as a RAIL_Handle_t argument. */ + RAIL_ASSERT_NULL_HANDLE = 29, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_30 = 30, + /** API improperly called while protocol inactive. */ + RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG = 31, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_32 = 32, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_33 = 33, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_34 = 34, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_35 = 35, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_36 = 36, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_37 = 37, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_38 = 38, + /** This function is deprecated and must not be called. */ + RAIL_ASSERT_DEPRECATED_FUNCTION = 39, + /** Multiprotocol task started with no event to run. */ + RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT = 40, + /** Invalid interrupt enabled. */ + RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED = 41, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_42 = 42, + /** Division by zero. */ + RAIL_ASSERT_DIVISION_BY_ZERO = 43, + /** Function cannot be called without access to the hardware. */ + RAIL_ASSERT_CANT_USE_HARDWARE = 44, + /** Pointer parameter was passed as NULL. */ + RAIL_ASSERT_NULL_PARAMETER = 45, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_46 = 46, + /** Synth radio config buffer for channel hopping too small. */ + RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER = 47, + /** Buffer provided for RX Channel Hopping is too small. */ + RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT = 48, + /** Invalid action was attempted on a module. */ + RAIL_ASSERT_INVALID_MODULE_ACTION = 49, + /** The radio config for this channel is not compatible with channel hopping. */ + RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG = 50, + /** Channel change failed. */ + RAIL_ASSERT_CHANNEL_CHANGE_FAILED = 51, + /** Attempted to read invalid register. */ + RAIL_ASSERT_INVALID_REGISTER = 52, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_53 = 53, + /** DMP radio config caching failed. */ + RAIL_ASSERT_CACHE_CONFIG_FAILED = 54, + /** NULL was supplied as a RAIL_StateTransitions_t argument. */ + RAIL_ASSERT_NULL_TRANSITIONS = 55, + /** LDMA transfer failed. */ + RAIL_ASSERT_BAD_LDMA_TRANSFER = 56, + /** Attempted to wake up with invalid RTCC sync data. */ + RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES = 57, + /** Radio sequencer hit a fault condition. */ + RAIL_ASSERT_SEQUENCER_FAULT = 58, + /** Bus fault. */ + RAIL_ASSERT_BUS_ERROR = 59, + /** The current radio config cannot be used with packet filtering. */ + RAIL_ASSERT_INVALID_FILTERING_CONFIG = 60, + /** Retiming configuration error. */ + RAIL_ASSERT_RETIMING_CONFIG = 61, + /** TX CRC configuration is corrupt. */ + RAIL_ASSERT_FAILED_TX_CRC_CONFIG = 62, + /** The current PA config does not allow for this operation. */ + RAIL_ASSERT_INVALID_PA_OPERATION = 63, + /** The sequencer selected an invalid PA. */ + RAIL_ASSERT_SEQ_INVALID_PA_SELECTED = 64, + /** Invalid/unsupported channel config. */ + RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG = 65, + /** Radio Calculator configuration HFXO frequency mismatch with chip */ + RAIL_ASSERT_INVALID_XTAL_FREQUENCY = 66, + /** Invalid assert, no longer used. */ + RAIL_ASSERT_UNUSED_67 = 67, + /** Software modem image does not support requested modulation */ + RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION = 68, + /** Failed to disable RTCC synchronization. */ + RAIL_ASSERT_FAILED_RTCC_SYNC_STOP = 69, + /** Multitimer linked list corrupted. */ + RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT = 70, + /** Unable to configure radio for temperature calibration. */ + RAIL_ASSERT_FAILED_TEMPCAL_ERROR = 71, + /** Invalid EFF configuration. */ + RAIL_ASSERT_INVALID_EFF_CONFIGURATION = 72, + /** Invalid RFFPLL configuration. */ + RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION = 73, + /** Secure access fault. */ + RAIL_ASSERT_SECURE_ACCESS_FAULT = 74, + /** SYSRTC0 not running. */ + RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING = 75, + /** Radio Configurator not updated. */ + RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE = 76, + /** Failed to set the event for configurable RSSI threshold. */ + RAIL_ASSERT_FAILED_RSSI_THRESHOLD = 77, + /** Intended and actual Z-Wave region configuration mismatch. */ + RAIL_ASSERT_INCORRECT_ZWAVE_REGION = 78, + /** Attempted to sleep with stale RTCC synchronization data */ + RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA = 79, + /** Attempted to clear LOG2X4 with a DEC1 value not equal to 0 */ + RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION = 80, + /** Failed to complete DMA write */ + RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE = 81, + /** RAIL does not support this Radio Calculator configuration */ + RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED = 82, + /** Invalid binary image was loaded onto the sequencer */ + RAIL_ASSERT_INVALID_SEQUENCER_IMAGE = 83, + /** No common or protocol image selected to be loaded onto the sequencer */ + RAIL_ASSERT_MISSING_SEQUENCER_IMAGE = 84, + /** Software modem image invalid or missing */ + RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE = 85, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_APPENDED_INFO_MISSING) +#define RAIL_ASSERT_FAILED_RX_FIFO_BYTES ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RX_FIFO_BYTES) +#define RAIL_ASSERT_UNUSED_2 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_2) +#define RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_ILLEGAL_RXLEN_ENTRY_STATUS) +#define RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BAD_PACKET_LENGTH) +#define RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_DIVCTRL_ENUM_CONVERSION_ERROR) +#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO) +#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RXLEN_FIFO) +#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TX_FIFO) +#define RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_UNEXPECTED_STATE_TXACK_FIFO) +#define RAIL_ASSERT_UNUSED_10 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_10) +#define RAIL_ASSERT_UNUSED_11 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_11) +#define RAIL_ASSERT_UNUSED_12 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_12) +#define RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_POST_WAKEUP) +#define RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_VCO_FREQUENCY) +#define RAIL_ASSERT_FAILED_RAC_STATE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RAC_STATE) +#define RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYNTH_INVALID_VCOCTRL) +#define RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NESTED_SEQUENCER_LOCK) +#define RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_AVERAGE_DONE) +#define RAIL_ASSERT_UNUSED_19 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_19) +#define RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_RANDOM_SEED) +#define RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_EFR32XG1_REGISTER_SIZE) +#define RAIL_ASSERT_FAILED_PROTIMER_CHANNEL ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_PROTIMER_CHANNEL) +#define RAIL_ASSERT_UNUSED_23 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_23) +#define RAIL_ASSERT_FAILED_BASECNTTOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_BASECNTTOP) +#define RAIL_ASSERT_UNUSED_25 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_25) +#define RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_MISSED) +#define RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_CLOCK_SOURCE_NOT_READY) +#define RAIL_ASSERT_UNUSED_28 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_28) +#define RAIL_ASSERT_NULL_HANDLE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_HANDLE) +#define RAIL_ASSERT_UNUSED_30 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_30) +#define RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_NO_ACTIVE_CONFIG) +#define RAIL_ASSERT_UNUSED_32 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_32) +#define RAIL_ASSERT_UNUSED_33 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_33) +#define RAIL_ASSERT_UNUSED_34 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_34) +#define RAIL_ASSERT_UNUSED_35 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_35) +#define RAIL_ASSERT_UNUSED_36 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_36) +#define RAIL_ASSERT_UNUSED_37 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_37) +#define RAIL_ASSERT_UNUSED_38 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_38) +#define RAIL_ASSERT_DEPRECATED_FUNCTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DEPRECATED_FUNCTION) +#define RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MULTIPROTOCOL_NO_EVENT) +#define RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_INTERRUPT_ENABLED) +#define RAIL_ASSERT_UNUSED_42 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_42) +#define RAIL_ASSERT_DIVISION_BY_ZERO ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_DIVISION_BY_ZERO) +#define RAIL_ASSERT_CANT_USE_HARDWARE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CANT_USE_HARDWARE) +#define RAIL_ASSERT_NULL_PARAMETER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_PARAMETER) +#define RAIL_ASSERT_UNUSED_46 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_46) +#define RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SMALL_SYNTH_RADIO_CONFIG_BUFFER) +#define RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT) +#define RAIL_ASSERT_INVALID_MODULE_ACTION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_MODULE_ACTION) +#define RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_HOPPING_INVALID_RADIO_CONFIG) +#define RAIL_ASSERT_CHANNEL_CHANGE_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CHANNEL_CHANGE_FAILED) +#define RAIL_ASSERT_INVALID_REGISTER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_REGISTER) +#define RAIL_ASSERT_UNUSED_53 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_53) +#define RAIL_ASSERT_CACHE_CONFIG_FAILED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CACHE_CONFIG_FAILED) +#define RAIL_ASSERT_NULL_TRANSITIONS ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_NULL_TRANSITIONS) +#define RAIL_ASSERT_BAD_LDMA_TRANSFER ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BAD_LDMA_TRANSFER) +#define RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RTCC_SYNC_VALUES) +#define RAIL_ASSERT_SEQUENCER_FAULT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQUENCER_FAULT) +#define RAIL_ASSERT_BUS_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_BUS_ERROR) +#define RAIL_ASSERT_INVALID_FILTERING_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_FILTERING_CONFIG) +#define RAIL_ASSERT_RETIMING_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RETIMING_CONFIG) +#define RAIL_ASSERT_FAILED_TX_CRC_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TX_CRC_CONFIG) +#define RAIL_ASSERT_INVALID_PA_OPERATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_PA_OPERATION) +#define RAIL_ASSERT_SEQ_INVALID_PA_SELECTED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SEQ_INVALID_PA_SELECTED) +#define RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_INVALID_CHANNEL_CONFIG) +#define RAIL_ASSERT_INVALID_XTAL_FREQUENCY ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_XTAL_FREQUENCY) +#define RAIL_ASSERT_UNUSED_67 ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNUSED_67) +#define RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_UNSUPPORTED_SOFTWARE_MODEM_MODULATION) +#define RAIL_ASSERT_FAILED_RTCC_SYNC_STOP ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STOP) +#define RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_MULTITIMER_CORRUPT) +#define RAIL_ASSERT_FAILED_TEMPCAL_ERROR ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_TEMPCAL_ERROR) +#define RAIL_ASSERT_INVALID_EFF_CONFIGURATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_EFF_CONFIGURATION) +#define RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_RFFPLL_CONFIGURATION) +#define RAIL_ASSERT_SECURE_ACCESS_FAULT ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_SECURE_ACCESS_FAULT) +#define RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_SYSRTC0_NOT_RUNNING) +#define RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_RADIO_CONFIG_NOT_UP_TO_DATE) +#define RAIL_ASSERT_FAILED_RSSI_THRESHOLD ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RSSI_THRESHOLD) +#define RAIL_ASSERT_INCORRECT_ZWAVE_REGION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INCORRECT_ZWAVE_REGION) +#define RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_RTCC_SYNC_STALE_DATA) +#define RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_LOG2X4_CLEAR_CONDITION) +#define RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_FAILED_DMA_WRITE_INCOMPLETE) +#define RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_CALCULATOR_NOT_SUPPORTED) +#define RAIL_ASSERT_INVALID_SEQUENCER_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_SEQUENCER_IMAGE) +#define RAIL_ASSERT_MISSING_SEQUENCER_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_MISSING_SEQUENCER_IMAGE) +#define RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE ((RAIL_AssertErrorCodes_t) RAIL_ASSERT_INVALID_OR_MISSING_SOFTWARE_MODEM_IMAGE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/// Use this define to create an array of error messages that map to the codes +/// in \ref RAIL_AssertErrorCodes_t. You can use these to print slightly more +/// detailed error strings related to a particular assert error code if desired. +/// For example, you could implement your assert failed callback as follows to +/// make use of this. +/// +/// @code{.c} +/// void RAILCb_AssertFailed(RAIL_Handle_t railHandle, uint32_t errorCode) +/// { +/// static const char* railErrorMessages[] = RAIL_ASSERT_ERROR_MESSAGES; +/// const char *errorMessage = "Unknown"; +/// +/// // If this error code is within the range of known error messages then use +/// // the appropriate error message. +/// if (errorCode < (sizeof(railErrorMessages) / sizeof(char*))) { +/// errorMessage = railErrorMessages[errorCode]; +/// } +/// printf(errorMessage); +/// +/// // Reset the chip since an assert is a fatal error +/// NVIC_SystemReset(); +/// } +/// @endcode +/// +#define RAIL_ASSERT_ERROR_MESSAGES { \ + /* 0*/ "Appended info missing from RX packet", \ + /* 1*/ "Receive FIFO too small for IR calibration", \ + /* 2*/ "Invalid assert, no longer used", \ + /* 3*/ "Receive FIFO entry has invalid status", \ + /* 4*/ "Receive FIFO entry bad packet length", \ + /* 5*/ "Unable to configure radio for IR calibration", \ + /* 6*/ "Reached unexpected state while handling RX FIFO events", \ + /* 7*/ "Reached unexpected state while handling RXLEN FIFO events", \ + /* 8*/ "Reached unexpected state while handling TX FIFO events", \ + /* 9*/ "Reached unexpected state while handling TX ACK FIFO events", \ + /*10*/ "Invalid assert, no longer used", \ + /*11*/ "Invalid assert, no longer used", \ + /*12*/ "Invalid assert, no longer used", \ + /*13*/ "Error synchronizing the RAIL timebase after sleep", \ + /*14*/ "VCO frequency outside supported range", \ + /*15*/ "Radio active while changing channels", \ + /*16*/ "Invalid Synth VCOCTRL field calculation", \ + /*17*/ "Nested attempt to lock the sequencer", \ + /*18*/ "RSSI averaging enabled without a valid callback", \ + /*19*/ "Invalid assert, no longer used", \ + /*20*/ "Unable to seed radio pseudo random number generator", \ + /*21*/ "Timeout exceeds EFR32XG1 register size", \ + /*22*/ "Invalid timer channel specified", \ + /*23*/ "Invalid assert, no longer used", \ + /*24*/ "LBT config exceeds EFR32XG1 register size", \ + /*25*/ "Invalid assert, no longer used", \ + /*26*/ "Could not synchronize RAIL timebase with the RTC", \ + /*27*/ "Clock source not ready", \ + /*28*/ "Invalid assert, no longer used", \ + /*29*/ "NULL was supplied as a RAIL_Handle_t argument", \ + /*30*/ "Invalid assert, no longer used", \ + /*31*/ "API improperly called while protocol inactive", \ + /*32*/ "Invalid assert, no longer used", \ + /*33*/ "Invalid assert, no longer used", \ + /*34*/ "Invalid assert, no longer used", \ + /*35*/ "Invalid assert, no longer used", \ + /*36*/ "Invalid assert, no longer used", \ + /*37*/ "Invalid assert, no longer used", \ + /*38*/ "Invalid assert, no longer used", \ + /*39*/ "This function is deprecated and must not be called", \ + /*40*/ "Multiprotocol task started with no event to run", \ + /*41*/ "Invalid interrupt enabled", \ + /*42*/ "Invalid assert, no longer used", \ + /*43*/ "Division by zero", \ + /*44*/ "Function cannot be called without access to the hardware", \ + /*45*/ "Pointer parameter was passed as NULL", \ + /*46*/ "Invalid assert, no longer used", \ + /*47*/ "Synth radio config buffer for channel hopping too small", \ + /*48*/ "Buffer provided for RX Channel Hopping is too small", \ + /*49*/ "Invalid action was attempted on a module", \ + /*50*/ "The radio config for this channel is not compatible with channel hopping", \ + /*51*/ "Channel change failed", \ + /*52*/ "Attempted to read invalid register", \ + /*53*/ "Invalid assert, no longer used", \ + /*54*/ "DMP radio config caching failed", \ + /*55*/ "NULL was supplied as a RAIL_StateTransitions_t argument", \ + /*56*/ "LDMA transfer failed", \ + /*57*/ "Attempted to wake up with invalid RTCC sync data", \ + /*58*/ "Radio sequencer hit a fault condition", \ + /*59*/ "Bus fault", \ + /*60*/ "The current radio config cannot be used with packet filtering", \ + /*61*/ "Retiming configuration error", \ + /*62*/ "TX CRC configuration is corrupt", \ + /*63*/ "The current PA config does not allow for this operation", \ + /*64*/ "The sequencer selected an invalid PA", \ + /*65*/ "Invalid/unsupported channel config", \ + /*66*/ "Radio Calculator configuration HFXO frequency mismatch with chip", \ + /*67*/ "Invalid assert, no longer used", \ + /*68*/ "Software modem image does not support requested modulation", \ + /*69*/ "Failed to disable RTCC synchronization", \ + /*70*/ "Multitimer linked list corrupted", \ + /*71*/ "Unable to configure radio for temperature calibration", \ + /*72*/ "Invalid EFF configuration", \ + /*73*/ "PHY and System RFFPLL settings do not match", \ + /*74*/ "Secure access fault", \ + /*75*/ "SYSRTC0 not running", \ + /*76*/ "Radio Configurator not updated", \ + /*77*/ "Failed to set the event for configurable RSSI threshold", \ + /*78*/ "Intended and actual Z-Wave region configuration mismatch", \ + /*79*/ "Attempted to sleep with stale RTCC synchronization data", \ + /*80*/ "Attempted to clear LOG2X4 with a DEC1 value not equal to 0", \ + /*81*/ "Failed to complete DMA write", \ + /*82*/ "RAIL does not support this Radio Calculator configuration", \ + /*83*/ "Invalid binary image loaded on sequencer", \ + /*84*/ "No common or protocol image selected to be loaded onto the sequencer", \ + /*85*/ "Software modem image invalid or missing", \ +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_ASSERT_ERROR_CODES_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_features.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_features.h index 3b2847d..be1bfdb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_features.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_features.h @@ -1,867 +1,867 @@ -/***************************************************************************//** - * @file - * @brief Auxiliary header for the RAIL library. Includes consistent definitions - * of features available across different chips. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_FEATURES_H__ -#define __RAIL_FEATURES_H__ - -#include "em_device.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup RAIL_API RAIL API - * @{ - */ - -/****************************************************************************** - * RAIL Features - *****************************************************************************/ -/** - * @addtogroup Features - * @brief Overview of support for various features across hardware platforms. - * These defines can be used at compile time to determine which - * features are available on your platform. However, keep in mind that - * these defines hold true for chip families. Your specific part - * may have further restrictions (band limitations, power amplifier - * restrictions, and so on) on top of those listed below, for which - * runtime RAIL_Supports*() APIs can be used to check availability - * on a particular chip (after \ref RAIL_Init() has been called). - * In general, an attempt to call an API that is not supported on your - * chip family as listed below will result in a - * \ref RAIL_STATUS_INVALID_CALL. - * @{ - */ - -/// Boolean to indicate whether the selected chip supports both SubGHz and 2.4 GHz bands. -/// See also runtime refinement \ref RAIL_SupportsDualBand(). -#if ((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ - || ((FEAT_RF_2G4 == 1) && (FEAT_RF_SUBG == 1))) -#define RAIL_SUPPORTS_DUAL_BAND 1 -#else -#define RAIL_SUPPORTS_DUAL_BAND 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_DUAL_BAND. -#define RAIL_FEAT_DUAL_BAND_RADIO RAIL_SUPPORTS_DUAL_BAND - -/// Boolean to indicate whether the selected chip supports the 2.4 GHz band. -/// See also runtime refinement \ref RAIL_Supports2p4GHzBand(). -#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ - || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_2G4HZ)) \ - || (FEAT_RF_2G4 == 1)) -#define RAIL_SUPPORTS_2P4GHZ_BAND 1 -#else -#define RAIL_SUPPORTS_2P4GHZ_BAND 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_2P4GHZ_BAND. -#define RAIL_FEAT_2G4_RADIO RAIL_SUPPORTS_2P4GHZ_BAND - -/// Boolean to indicate whether the selected chip supports SubGHz bands. -/// See also runtime refinement \ref RAIL_SupportsSubGHzBand(). -#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ - || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_SUBGHZ)) \ - || (FEAT_RF_SUBG == 1)) -#define RAIL_SUPPORTS_SUBGHZ_BAND 1 -#else -#define RAIL_SUPPORTS_SUBGHZ_BAND 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_SUBGHZ_BAND. -#define RAIL_FEAT_SUBGIG_RADIO RAIL_SUPPORTS_SUBGHZ_BAND - -/// Boolean to indicate whether the selected chip supports OFDM PA. -/// See also runtime refinement \ref RAIL_SupportsOFDMPA(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_SUPPORTS_OFDM_PA 1 -#else -#define RAIL_SUPPORTS_OFDM_PA 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// bit masked address filtering. -/// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) -#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 1 -#else -#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// address filter mask information for incoming packets in -/// \ref RAIL_RxPacketInfo_t::filterMask and -/// \ref RAIL_IEEE802154_Address_t::filterMask. -/// See also runtime refinement \ref RAIL_SupportsAddrFilterMask(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_SUPPORTS_ADDR_FILTER_MASK 1 -#else -#define RAIL_SUPPORTS_ADDR_FILTER_MASK 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// alternate power settings for the Power Amplifier. -/// See also runtime refinement \ref RAIL_SupportsAlternateTxPower(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 1 -#else -#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ALTERNATE_TX_POWER. -#define RAIL_FEAT_ALTERNATE_POWER_TX_SUPPORTED RAIL_SUPPORTS_ALTERNATE_TX_POWER - -/// Boolean to indicate whether the selected chip supports antenna diversity. -/// See also runtime refinement \ref RAIL_SupportsAntennaDiversity(). -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \ - || (_SILICON_LABS_32B_SERIES == 2)) -#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 1 -#else -#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. -#define RAIL_FEAT_ANTENNA_DIVERSITY RAIL_SUPPORTS_ANTENNA_DIVERSITY - -/// Boolean to indicate whether the selected chip supports path diversity. -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_SUPPORTS_PATH_DIVERSITY 1 -#else -#define RAIL_SUPPORTS_PATH_DIVERSITY 0 -#endif - -/// Boolean to indicate whether the selected chip supports channel hopping. -/// See also runtime refinement \ref RAIL_SupportsChannelHopping(). -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1)) -#define RAIL_SUPPORTS_CHANNEL_HOPPING 1 -#else -#define RAIL_SUPPORTS_CHANNEL_HOPPING 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_CHANNEL_HOPPING. -#define RAIL_FEAT_CHANNEL_HOPPING RAIL_SUPPORTS_CHANNEL_HOPPING - -/// Boolean to indicate whether the selected chip supports dual sync words. -/// See also runtime refinement \ref RAIL_SupportsDualSyncWords(). -#if 1 -#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 1 -#else -#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 0 -#endif - -/// Boolean to indicate whether the selected chip supports automatic transitions -/// from TX to TX. -/// See also runtime refinement \ref RAIL_SupportsTxToTx(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_SUPPORTS_TX_TO_TX 1 -#else -#define RAIL_SUPPORTS_TX_TO_TX 0 -#endif - -/// Boolean to indicate whether the selected chip supports \ref RAIL_TX_REPEAT_OPTION_START_TO_START. -/// See also runtime refinement \ref RAIL_SupportsTxRepeatStartToStart(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) -#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START RAIL_SUPPORTS_TX_TO_TX -#else -#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START 0 -#endif - -/// Boolean to indicate whether the selected chip supports thermistor measurements. -/// See also runtime refinement \ref RAIL_SupportsExternalThermistor(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 1 -#else -#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. -#define RAIL_FEAT_EXTERNAL_THERMISTOR RAIL_SUPPORTS_EXTERNAL_THERMISTOR - -/// Boolean to indicate whether the selected chip supports HFXO compensation. -/// See also runtime refinement \ref RAIL_SupportsHFXOCompensation(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_SUPPORTS_HFXO_COMPENSATION RAIL_SUPPORTS_EXTERNAL_THERMISTOR -#else -#define RAIL_SUPPORTS_HFXO_COMPENSATION 0 -#endif - -/// Boolean to indicate whether the selected chip supports AUXADC measurements. -/// See also runtime refinement \ref RAIL_SupportsAuxAdc(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_SUPPORTS_AUXADC 1 -#else -#define RAIL_SUPPORTS_AUXADC 0 -#endif - -/// Boolean to indicate whether the selected chip supports a high-precision -/// LFRCO. -/// Best to use the runtime refinement \ref RAIL_SupportsPrecisionLFRCO() -/// because some chip revisions do not support it. -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_SUPPORTS_PRECISION_LFRCO 1 -#else -#define RAIL_SUPPORTS_PRECISION_LFRCO 0 -#endif - -/// Boolean to indicate whether the selected chip supports radio entropy. -/// See also runtime refinement \ref RAIL_SupportsRadioEntropy(). -#if 1 -#define RAIL_SUPPORTS_RADIO_ENTROPY 1 -#else -#define RAIL_SUPPORTS_RADIO_ENTROPY 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// RFSENSE Energy Detection Mode. -/// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection(). -#if ((_SILICON_LABS_32B_SERIES == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 1 -#else -#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// RFSENSE Selective(OOK) Mode. -/// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 1 -#else -#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. -#define RAIL_FEAT_RFSENSE_SELECTIVE_OOK_MODE_SUPPORTED \ - RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK - -/// Boolean to indicate whether the selected chip supports the Energy Friendly -/// Front End Module (EFF). -/// See also runtime refinement \ref RAIL_SupportsEff(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_SUPPORTS_EFF 1 -#else -#define RAIL_SUPPORTS_EFF 0 -#endif - -// BLE features -// Some features may not be available on all platforms -// due to radio hardware limitations. - -/// Boolean to indicate whether the selected chip supports BLE. -/// See also runtime refinement \ref RAIL_SupportsProtocolBLE(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 4) -#define RAIL_SUPPORTS_PROTOCOL_BLE RAIL_SUPPORTS_2P4GHZ_BAND -#else -#define RAIL_SUPPORTS_PROTOCOL_BLE 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE 1Mbps -/// Non-Viterbi PHY. -/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsNonViterbi(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 1) -#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE 1Mbps Viterbi -/// PHY. -/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsViterbi(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE 1Mbps operation. -/// See also runtime refinement \ref RAIL_BLE_Supports1Mbps(). -#define RAIL_BLE_SUPPORTS_1MBPS \ - (RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_1MBPS_VITERBI) - -/// Boolean to indicate whether the selected chip supports BLE 2Mbps -/// Non-Viterbi PHY. -/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsNonViterbi(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) -#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE 2Mbps Viterbi -/// PHY. -/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsViterbi(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE 2Mbps operation. -/// See also runtime refinement \ref RAIL_BLE_Supports2Mbps(). -#define RAIL_BLE_SUPPORTS_2MBPS \ - (RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_2MBPS_VITERBI) - -/// Boolean to indicate whether the selected chip supports BLE -/// Antenna Switching needed for Angle-of-Arrival receives or -/// Angle-of-Departure transmits. -/// See also runtime refinement \ref RAIL_BLE_SupportsAntennaSwitching(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) -#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0 -#endif - -/// Boolean to indicate whether the selected chip supports the BLE Coded PHY -/// used for Long-Range. -/// See also runtime refinement \ref RAIL_BLE_SupportsCodedPhy(). -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_BLE_SUPPORTS_CODED_PHY RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_CODED_PHY 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_CODED_PHY. -#define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY - -/// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY -/// used for simultaneous BLE 1Mbps and Coded PHY reception. -/// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE -/// CTE (Constant Tone Extension) needed for Angle-of-Arrival/Departure -/// transmits. -/// See also runtime refinement \ref RAIL_BLE_SupportsCte(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_BLE_SUPPORTS_CTE RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_CTE 0 -#endif - -/// Boolean to indicate whether the selected chip supports the -/// Quuppa PHY. -/// See also runtime refinement \ref RAIL_BLE_SupportsQuuppa(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) -#define RAIL_BLE_SUPPORTS_QUUPPA RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_QUUPPA 0 -#endif - -/// Boolean to indicate whether the selected chip supports BLE -/// IQ Sampling needed for Angle-of-Arrival/Departure receives. -/// See also runtime refinement \ref RAIL_BLE_SupportsIQSampling(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) -#define RAIL_BLE_SUPPORTS_IQ_SAMPLING RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0 -#endif - -/// Boolean to indicate whether the selected chip supports some BLE AOX -/// features. -#define RAIL_BLE_SUPPORTS_AOX \ - (RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING \ - || RAIL_BLE_SUPPORTS_IQ_SAMPLING \ - || RAIL_BLE_SUPPORTS_CTE) - -/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_AOX -#define RAIL_FEAT_BLE_AOX_SUPPORTED RAIL_BLE_SUPPORTS_AOX - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/// Boolean to indicate whether the selected chip supports BLE -/// HADM (high accuracy distance measurements). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -#define RAIL_BLE_SUPPORTS_HADM RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_HADM 0 -#endif - -/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_HADM. -#define RAIL_FEAT_BLE_HADM_SUPPORTED RAIL_BLE_SUPPORTS_HADM -#endif - -/// Boolean to indicate whether the selected chip supports BLE PHY switch to RX -/// functionality, which is used to switch BLE PHYs at a specific time -/// to receive auxiliary packets. -/// See also runtime refinement \ref RAIL_BLE_SupportsPhySwitchToRx(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX RAIL_SUPPORTS_PROTOCOL_BLE -#else -#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. -#define RAIL_FEAT_BLE_PHY_SWITCH_TO_RX RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX - -// IEEE 802.15.4 features -// Some features may not be available on all platforms -// due to radio hardware limitations. - -/// Boolean to indicate whether the selected chip supports IEEE 802.15.4. -/// See also runtime refinement \ref RAIL_SupportsProtocolIEEE802154(). -#if 1 -#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 1 -#else -#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 0 -#endif - -/// Boolean to indicate whether the selected chip supports the -/// 802.15.4 Wi-Fi Coexistence PHY. -/// See also runtime refinement \ref RAIL_IEEE802154_SupportsCoexPhy(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) -#define RAIL_IEEE802154_SUPPORTS_COEX_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) -#else -#define RAIL_IEEE802154_SUPPORTS_COEX_PHY 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. -#define RAIL_FEAT_802154_COEX_PHY RAIL_IEEE802154_SUPPORTS_COEX_PHY - -/// Boolean to indicate whether the selected chip supports -/// the IEEE 802.15.4 2.4 GHz band variant. -/// See also runtime refinement \ref RAIL_SupportsIEEE802154Band2P4(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3) -#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) -#else -#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// the IEEE 802.15.4 2.4 RX channel switching. -/// See also runtime refinement \ref RAIL_IEEE802154_SupportsRxChannelSwitching(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) -#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING (RAIL_SUPPORTS_IEEE802154_BAND_2P4) -#else -#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING 0 -#endif - -/// Boolean to indicate whether the selected chip supports a front end module. -/// See also runtime refinement \ref RAIL_IEEE802154_SupportsFemPhy(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 8) -#define RAIL_IEEE802154_SUPPORTS_FEM_PHY (RAIL_SUPPORTS_IEEE802154_BAND_2P4) -#else -#define RAIL_IEEE802154_SUPPORTS_FEM_PHY 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4E-2012 feature subset needed for Zigbee R22 GB868. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsESubsetGB868(). -#if 1 -#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 RAIL_SUPPORTS_PROTOCOL_IEEE802154 -#else -#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. -#define RAIL_FEAT_IEEE802154_E_GB868_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4E-2012 Enhanced ACKing. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsEEnhancedAck(). -#if 1 -#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 -#else -#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. -#define RAIL_FEAT_IEEE802154_E_ENH_ACK_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK - -/// Boolean to indicate whether the selected chip supports -/// receiving IEEE 802.15.4E-2012 Multipurpose frames. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsEMultipurposeFrames(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 -#else -#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. -#define RAIL_FEAT_IEEE802154_MULTIPURPOSE_FRAME_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4G-2012 feature subset needed for Zigbee R22 GB868. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsGSubsetGB868(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3) -#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 \ - ((RAIL_SUPPORTS_PROTOCOL_IEEE802154 != 0) && (RAIL_SUPPORTS_SUBGHZ_BAND != 0)) -#else -#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. -#define RAIL_FEAT_IEEE802154_G_GB868_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 - -/// Boolean to indicate whether the selected chip supports -/// dynamic FEC -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsGDynFec(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 2) -#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC \ - RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now -#else -#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// Wi-SUN mode switching -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsGModeSwitch(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH \ - RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now -#else -#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4G-2012 reception and transmission of frames -/// with 4-byte CRC. -/// See also runtime refinement \ref RAIL_IEEE802154_SupportsG4ByteCrc(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 -#else -#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. -#define RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4G-2012 reception of unwhitened frames. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsGUnwhitenedRx(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 -#else -#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. -#define RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX - -/// Boolean to indicate whether the selected chip supports -/// IEEE 802.15.4G-2012 transmission of unwhitened frames. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsGUnwhitenedTx(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) -#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 -#else -#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. -#define RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX - -/// Boolean to indicate whether the selected chip supports -/// canceling the frame-pending lookup event -/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND -/// when the radio transitions to a state that renders the -/// the reporting of this event moot (i.e., too late for -/// the stack to influence the outgoing ACK). -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsCancelFramePendingLookup(). -#if 1 -#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154 -#else -#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. -#define RAIL_FEAT_IEEE802154_CANCEL_FP_LOOKUP_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP - -/// Boolean to indicate whether the selected chip supports -/// early triggering of the frame-pending lookup event -/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND -/// just after MAC address fields have been received. -/// See also runtime refinement \ref -/// RAIL_IEEE802154_SupportsEarlyFramePendingLookup(). -#if 1 -#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154 -#else -#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP 0 -#endif -/// Backwards-compatible synonym of \ref -/// RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. -#define RAIL_FEAT_IEEE802154_EARLY_FP_LOOKUP_SUPPORTED \ - RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP - -/// Boolean to indicate whether the selected chip supports dual PA configs for mode switch -/// or concurrent mode. -/// See also runtime refinement \ref RAIL_IEEE802154_SupportsDualPaConfig(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 1 -#else -#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 0 -#endif - -/// Boolean to indicate whether the selected chip supports the pa power setting table. -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 1 -#else -#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 0 -#endif - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/// Boolean to indicate whether the selected chip supports -/// IEEE802.15.4 2.4 GHz at 2 Mbps -/// See also runtime refinement \ref -/// RAIL_IEEE802154_Supports2MbpsPhy(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY \ - (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) -#else -#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY 0 -#endif -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY -/// with custom settings -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3)) -#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) -#else -#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0 -#endif - -// Wi_SUN features - -/// Boolean to indicate whether the selected chip supports -/// Wi-SUN -/// See also runtime refinement \ref -/// RAIL_SupportsProtocolWiSUN(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 1 -#else -#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 0 -#endif - -// WMBUS features - -/// Boolean to indicate whether the selected chip supports WMBUS simultaneous -/// M2O RX of T and C modes set by \ref RAIL_WMBUS_Config(). -/// See also runtime refinement \ref RAIL_WMBUS_SupportsSimultaneousTCRx(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 1 -#else -#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 0 -#endif - -// Z-Wave features -// Some features may not be available on all platforms -// due to radio hardware limitations. - -/// Boolean to indicate whether the selected chip supports Z-Wave. -/// See also runtime refinement \ref RAIL_SupportsProtocolZWave(). -#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_SUPPORTS_PROTOCOL_ZWAVE RAIL_SUPPORTS_SUBGHZ_BAND -#else -#define RAIL_SUPPORTS_PROTOCOL_ZWAVE 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. -#define RAIL_FEAT_ZWAVE_SUPPORTED RAIL_SUPPORTS_PROTOCOL_ZWAVE - -/// Boolean to indicate whether the selected chip supports energy detect PHY. -/// See also runtime refinement \ref RAIL_ZWAVE_SupportsEnergyDetectPhy(). -#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) -#define RAIL_ZWAVE_SUPPORTS_ED_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE -#else -#define RAIL_ZWAVE_SUPPORTS_ED_PHY 0 -#endif - -/// Boolean to indicate whether the selected chip supports concurrent PHY. -/// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_ZWAVE_SUPPORTS_CONC_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE -#else -#define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0 -#endif - -/// Boolean to indicate whether the selected chip supports SQ-based PHY. -/// See also runtime refinement \ref RAIL_SupportsSQPhy(). -#if ((_SILICON_LABS_32B_SERIES_2_CONFIG >= 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 7)) - -#define RAIL_SUPPORTS_SQ_PHY 1 -#else -#define RAIL_SUPPORTS_SQ_PHY 0 -#endif - -/// Boolean to indicate whether the code supports Z-Wave -/// region information in PTI and -/// newer RAIL_ZWAVE_RegionConfig_t structure -/// See also runtime refinement \ref RAIL_ZWAVE_SupportsRegionPti(). -#if 1 -#define RAIL_ZWAVE_SUPPORTS_REGION_PTI RAIL_SUPPORTS_PROTOCOL_ZWAVE -#else -#define RAIL_ZWAVE_SUPPORTS_REGION_PTI 0 -#endif -/// Backwards-compatible synonym of \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. -#define RAIL_FEAT_ZWAVE_REGION_PTI RAIL_ZWAVE_SUPPORTS_REGION_PTI - -/// Boolean to indicate whether the selected chip supports raw RX data -/// sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. -/// See also runtime refinement \ref RAIL_SupportsRxRawData(). -#if 1 -#define RAIL_SUPPORTS_RX_RAW_DATA 1 -#else -#define RAIL_SUPPORTS_RX_RAW_DATA 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// direct mode. -/// See also runtime refinement \ref RAIL_SupportsDirectMode(). -#if ((_SILICON_LABS_32B_SERIES == 1) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) -#define RAIL_SUPPORTS_DIRECT_MODE 1 -#else -#define RAIL_SUPPORTS_DIRECT_MODE 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// RX direct mode data to FIFO. -/// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 1 -#else -#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// MFM protocol. -/// See also runtime refinement \ref RAIL_SupportsMfm(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define RAIL_SUPPORTS_MFM 1 -#else -#define RAIL_SUPPORTS_MFM 0 -#endif - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -/// Boolean to indicate whether the selected chip supports -/// 802.15.4 signal detection - #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_IEEE802154) -/// Boolean to indicate whether the selected chip supports -/// BLE signal detection - #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_BLE) -#else -/// Boolean to indicate whether the selected chip supports -/// 802.15.4 signal detection - #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER 0 -/// Boolean to indicate whether the selected chip supports -/// BLE signal detection - #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0 -#endif - -/// Boolean to indicate whether the selected chip supports -/// configurable RSSI threshold set by \ref RAIL_SetRssiDetectThreshold(). -/// See also runtime refinement \ref RAIL_SupportsRssiDetectThreshold(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (1U) -#else -#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (0U) -#endif - -/// Boolean to indicate whether the selected chip supports -/// thermal protection set by \ref RAIL_ConfigThermalProtection(). -/// See also runtime refinement \ref RAIL_SupportsThermalProtection(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) - #define RAIL_SUPPORTS_THERMAL_PROTECTION (1U) -#else - #define RAIL_SUPPORTS_THERMAL_PROTECTION (0U) -#endif - -/// Boolean to indicate whether the selected chip supports fast RX2RX enabled by -/// \ref RAIL_RX_OPTION_FAST_RX2RX. -/// See also runtime refinement \ref RAIL_SupportsFastRx2Rx(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) - #define RAIL_SUPPORTS_FAST_RX2RX (1U) -#else - #define RAIL_SUPPORTS_FAST_RX2RX (0U) -#endif - -/// Boolean to indicate whether the selected chip supports collision detection -/// enabled by RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION -/// See also runtime refinement \ref RAIL_SupportsCollisionDetection(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) - #define RAIL_SUPPORTS_COLLISION_DETECTION (1U) -#else - #define RAIL_SUPPORTS_COLLISION_DETECTION (0U) -#endif - -/// Boolean to indicate whether the selected chip supports Sidewalk protocol. -/// See also runtime refinement \ref RAIL_SupportsProtocolSidewalk(). -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ - || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) - #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (1U) -#else - #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (0U) -#endif - -/** @} */ // end of group Features - -/** @} */ // end of group RAIL_API - -#ifdef __cplusplus -} -#endif - -#ifdef RAIL_INTERNAL_BUILD -#include "rail_features_internal.h" -#endif - -#endif // __RAIL_FEATURES_H__ +/***************************************************************************//** + * @file + * @brief Auxiliary header for the RAIL library. Includes consistent definitions + * of features available across different chips. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_FEATURES_H__ +#define __RAIL_FEATURES_H__ + +#include "em_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup RAIL_API RAIL API + * @{ + */ + +/****************************************************************************** + * RAIL Features + *****************************************************************************/ +/** + * @addtogroup Features + * @brief Overview of support for various features across hardware platforms. + * These defines can be used at compile time to determine which + * features are available on your platform. However, keep in mind that + * these defines hold true for chip families. Your specific part + * may have further restrictions (band limitations, power amplifier + * restrictions, and so on) on top of those listed below, for which + * runtime RAIL_Supports*() APIs can be used to check availability + * on a particular chip (after \ref RAIL_Init() has been called). + * In general, an attempt to call an API that is not supported on your + * chip family as listed below will result in a + * \ref RAIL_STATUS_INVALID_CALL. + * @{ + */ + +/// Boolean to indicate whether the selected chip supports both SubGHz and 2.4 GHz bands. +/// See also runtime refinement \ref RAIL_SupportsDualBand(). +#if ((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ + || ((FEAT_RF_2G4 == 1) && (FEAT_RF_SUBG == 1))) +#define RAIL_SUPPORTS_DUAL_BAND 1 +#else +#define RAIL_SUPPORTS_DUAL_BAND 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_DUAL_BAND. +#define RAIL_FEAT_DUAL_BAND_RADIO RAIL_SUPPORTS_DUAL_BAND + +/// Boolean to indicate whether the selected chip supports the 2.4 GHz band. +/// See also runtime refinement \ref RAIL_Supports2p4GHzBand(). +#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ + || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_2G4HZ)) \ + || (FEAT_RF_2G4 == 1)) +#define RAIL_SUPPORTS_2P4GHZ_BAND 1 +#else +#define RAIL_SUPPORTS_2P4GHZ_BAND 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_2P4GHZ_BAND. +#define RAIL_FEAT_2G4_RADIO RAIL_SUPPORTS_2P4GHZ_BAND + +/// Boolean to indicate whether the selected chip supports SubGHz bands. +/// See also runtime refinement \ref RAIL_SupportsSubGHzBand(). +#if (((_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_DUALBAND) \ + || (_SILICON_LABS_EFR32_RADIO_TYPE == _SILICON_LABS_EFR32_RADIO_SUBGHZ)) \ + || (FEAT_RF_SUBG == 1)) +#define RAIL_SUPPORTS_SUBGHZ_BAND 1 +#else +#define RAIL_SUPPORTS_SUBGHZ_BAND 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_SUBGHZ_BAND. +#define RAIL_FEAT_SUBGIG_RADIO RAIL_SUPPORTS_SUBGHZ_BAND + +/// Boolean to indicate whether the selected chip supports OFDM PA. +/// See also runtime refinement \ref RAIL_SupportsOFDMPA(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_SUPPORTS_OFDM_PA 1 +#else +#define RAIL_SUPPORTS_OFDM_PA 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// bit masked address filtering. +/// See also runtime refinement \ref RAIL_SupportsAddrFilterAddressBitMask(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 1 +#else +#define RAIL_SUPPORTS_ADDR_FILTER_ADDRESS_BIT_MASK 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// address filter mask information for incoming packets in +/// \ref RAIL_RxPacketInfo_t::filterMask and +/// \ref RAIL_IEEE802154_Address_t::filterMask. +/// See also runtime refinement \ref RAIL_SupportsAddrFilterMask(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_SUPPORTS_ADDR_FILTER_MASK 1 +#else +#define RAIL_SUPPORTS_ADDR_FILTER_MASK 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// alternate power settings for the Power Amplifier. +/// See also runtime refinement \ref RAIL_SupportsAlternateTxPower(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 1 +#else +#define RAIL_SUPPORTS_ALTERNATE_TX_POWER 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ALTERNATE_TX_POWER. +#define RAIL_FEAT_ALTERNATE_POWER_TX_SUPPORTED RAIL_SUPPORTS_ALTERNATE_TX_POWER + +/// Boolean to indicate whether the selected chip supports antenna diversity. +/// See also runtime refinement \ref RAIL_SupportsAntennaDiversity(). +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) \ + || (_SILICON_LABS_32B_SERIES == 2)) +#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 1 +#else +#define RAIL_SUPPORTS_ANTENNA_DIVERSITY 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY. +#define RAIL_FEAT_ANTENNA_DIVERSITY RAIL_SUPPORTS_ANTENNA_DIVERSITY + +/// Boolean to indicate whether the selected chip supports path diversity. +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_SUPPORTS_PATH_DIVERSITY 1 +#else +#define RAIL_SUPPORTS_PATH_DIVERSITY 0 +#endif + +/// Boolean to indicate whether the selected chip supports channel hopping. +/// See also runtime refinement \ref RAIL_SupportsChannelHopping(). +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG >= 1)) +#define RAIL_SUPPORTS_CHANNEL_HOPPING 1 +#else +#define RAIL_SUPPORTS_CHANNEL_HOPPING 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_CHANNEL_HOPPING. +#define RAIL_FEAT_CHANNEL_HOPPING RAIL_SUPPORTS_CHANNEL_HOPPING + +/// Boolean to indicate whether the selected chip supports dual sync words. +/// See also runtime refinement \ref RAIL_SupportsDualSyncWords(). +#if 1 +#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 1 +#else +#define RAIL_SUPPORTS_DUAL_SYNC_WORDS 0 +#endif + +/// Boolean to indicate whether the selected chip supports automatic transitions +/// from TX to TX. +/// See also runtime refinement \ref RAIL_SupportsTxToTx(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_SUPPORTS_TX_TO_TX 1 +#else +#define RAIL_SUPPORTS_TX_TO_TX 0 +#endif + +/// Boolean to indicate whether the selected chip supports \ref RAIL_TX_REPEAT_OPTION_START_TO_START. +/// See also runtime refinement \ref RAIL_SupportsTxRepeatStartToStart(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) +#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START RAIL_SUPPORTS_TX_TO_TX +#else +#define RAIL_SUPPORTS_TX_REPEAT_START_TO_START 0 +#endif + +/// Boolean to indicate whether the selected chip supports thermistor measurements. +/// See also runtime refinement \ref RAIL_SupportsExternalThermistor(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 1 +#else +#define RAIL_SUPPORTS_EXTERNAL_THERMISTOR 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_EXTERNAL_THERMISTOR. +#define RAIL_FEAT_EXTERNAL_THERMISTOR RAIL_SUPPORTS_EXTERNAL_THERMISTOR + +/// Boolean to indicate whether the selected chip supports HFXO compensation. +/// See also runtime refinement \ref RAIL_SupportsHFXOCompensation(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_SUPPORTS_HFXO_COMPENSATION RAIL_SUPPORTS_EXTERNAL_THERMISTOR +#else +#define RAIL_SUPPORTS_HFXO_COMPENSATION 0 +#endif + +/// Boolean to indicate whether the selected chip supports AUXADC measurements. +/// See also runtime refinement \ref RAIL_SupportsAuxAdc(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_SUPPORTS_AUXADC 1 +#else +#define RAIL_SUPPORTS_AUXADC 0 +#endif + +/// Boolean to indicate whether the selected chip supports a high-precision +/// LFRCO. +/// Best to use the runtime refinement \ref RAIL_SupportsPrecisionLFRCO() +/// because some chip revisions do not support it. +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_SUPPORTS_PRECISION_LFRCO 1 +#else +#define RAIL_SUPPORTS_PRECISION_LFRCO 0 +#endif + +/// Boolean to indicate whether the selected chip supports radio entropy. +/// See also runtime refinement \ref RAIL_SupportsRadioEntropy(). +#if 1 +#define RAIL_SUPPORTS_RADIO_ENTROPY 1 +#else +#define RAIL_SUPPORTS_RADIO_ENTROPY 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// RFSENSE Energy Detection Mode. +/// See also runtime refinement \ref RAIL_SupportsRfSenseEnergyDetection(). +#if ((_SILICON_LABS_32B_SERIES == 1) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 1 +#else +#define RAIL_SUPPORTS_RFSENSE_ENERGY_DETECTION 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// RFSENSE Selective(OOK) Mode. +/// See also runtime refinement \ref RAIL_SupportsRfSenseSelectiveOok(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 1 +#else +#define RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK. +#define RAIL_FEAT_RFSENSE_SELECTIVE_OOK_MODE_SUPPORTED \ + RAIL_SUPPORTS_RFSENSE_SELECTIVE_OOK + +/// Boolean to indicate whether the selected chip supports the Energy Friendly +/// Front End Module (EFF). +/// See also runtime refinement \ref RAIL_SupportsEff(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_SUPPORTS_EFF 1 +#else +#define RAIL_SUPPORTS_EFF 0 +#endif + +// BLE features +// Some features may not be available on all platforms +// due to radio hardware limitations. + +/// Boolean to indicate whether the selected chip supports BLE. +/// See also runtime refinement \ref RAIL_SupportsProtocolBLE(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 4) +#define RAIL_SUPPORTS_PROTOCOL_BLE RAIL_SUPPORTS_2P4GHZ_BAND +#else +#define RAIL_SUPPORTS_PROTOCOL_BLE 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE 1Mbps +/// Non-Viterbi PHY. +/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsNonViterbi(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 1) +#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE 1Mbps Viterbi +/// PHY. +/// See also runtime refinement \ref RAIL_BLE_Supports1MbpsViterbi(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_1MBPS_VITERBI 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE 1Mbps operation. +/// See also runtime refinement \ref RAIL_BLE_Supports1Mbps(). +#define RAIL_BLE_SUPPORTS_1MBPS \ + (RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_1MBPS_VITERBI) + +/// Boolean to indicate whether the selected chip supports BLE 2Mbps +/// Non-Viterbi PHY. +/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsNonViterbi(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 2) +#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE 2Mbps Viterbi +/// PHY. +/// See also runtime refinement \ref RAIL_BLE_Supports2MbpsViterbi(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_2MBPS_VITERBI 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE 2Mbps operation. +/// See also runtime refinement \ref RAIL_BLE_Supports2Mbps(). +#define RAIL_BLE_SUPPORTS_2MBPS \ + (RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI || RAIL_BLE_SUPPORTS_2MBPS_VITERBI) + +/// Boolean to indicate whether the selected chip supports BLE +/// Antenna Switching needed for Angle-of-Arrival receives or +/// Angle-of-Departure transmits. +/// See also runtime refinement \ref RAIL_BLE_SupportsAntennaSwitching(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) +#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING 0 +#endif + +/// Boolean to indicate whether the selected chip supports the BLE Coded PHY +/// used for Long-Range. +/// See also runtime refinement \ref RAIL_BLE_SupportsCodedPhy(). +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_BLE_SUPPORTS_CODED_PHY RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_CODED_PHY 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_CODED_PHY. +#define RAIL_FEAT_BLE_CODED RAIL_BLE_SUPPORTS_CODED_PHY + +/// Boolean to indicate whether the selected chip supports the BLE Simulscan PHY +/// used for simultaneous BLE 1Mbps and Coded PHY reception. +/// See also runtime refinement \ref RAIL_BLE_SupportsSimulscanPhy(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_SIMULSCAN_PHY 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE +/// CTE (Constant Tone Extension) needed for Angle-of-Arrival/Departure +/// transmits. +/// See also runtime refinement \ref RAIL_BLE_SupportsCte(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_BLE_SUPPORTS_CTE RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_CTE 0 +#endif + +/// Boolean to indicate whether the selected chip supports the +/// Quuppa PHY. +/// See also runtime refinement \ref RAIL_BLE_SupportsQuuppa(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) +#define RAIL_BLE_SUPPORTS_QUUPPA RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_QUUPPA 0 +#endif + +/// Boolean to indicate whether the selected chip supports BLE +/// IQ Sampling needed for Angle-of-Arrival/Departure receives. +/// See also runtime refinement \ref RAIL_BLE_SupportsIQSampling(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) +#define RAIL_BLE_SUPPORTS_IQ_SAMPLING RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_IQ_SAMPLING 0 +#endif + +/// Boolean to indicate whether the selected chip supports some BLE AOX +/// features. +#define RAIL_BLE_SUPPORTS_AOX \ + (RAIL_BLE_SUPPORTS_ANTENNA_SWITCHING \ + || RAIL_BLE_SUPPORTS_IQ_SAMPLING \ + || RAIL_BLE_SUPPORTS_CTE) + +/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_AOX +#define RAIL_FEAT_BLE_AOX_SUPPORTED RAIL_BLE_SUPPORTS_AOX + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/// Boolean to indicate whether the selected chip supports BLE +/// HADM (high accuracy distance measurements). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +#define RAIL_BLE_SUPPORTS_HADM RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_HADM 0 +#endif + +/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_HADM. +#define RAIL_FEAT_BLE_HADM_SUPPORTED RAIL_BLE_SUPPORTS_HADM +#endif + +/// Boolean to indicate whether the selected chip supports BLE PHY switch to RX +/// functionality, which is used to switch BLE PHYs at a specific time +/// to receive auxiliary packets. +/// See also runtime refinement \ref RAIL_BLE_SupportsPhySwitchToRx(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX RAIL_SUPPORTS_PROTOCOL_BLE +#else +#define RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX. +#define RAIL_FEAT_BLE_PHY_SWITCH_TO_RX RAIL_BLE_SUPPORTS_PHY_SWITCH_TO_RX + +// IEEE 802.15.4 features +// Some features may not be available on all platforms +// due to radio hardware limitations. + +/// Boolean to indicate whether the selected chip supports IEEE 802.15.4. +/// See also runtime refinement \ref RAIL_SupportsProtocolIEEE802154(). +#if 1 +#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 1 +#else +#define RAIL_SUPPORTS_PROTOCOL_IEEE802154 0 +#endif + +/// Boolean to indicate whether the selected chip supports the +/// 802.15.4 Wi-Fi Coexistence PHY. +/// See also runtime refinement \ref RAIL_IEEE802154_SupportsCoexPhy(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG > 1) +#define RAIL_IEEE802154_SUPPORTS_COEX_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) +#else +#define RAIL_IEEE802154_SUPPORTS_COEX_PHY 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY. +#define RAIL_FEAT_802154_COEX_PHY RAIL_IEEE802154_SUPPORTS_COEX_PHY + +/// Boolean to indicate whether the selected chip supports +/// the IEEE 802.15.4 2.4 GHz band variant. +/// See also runtime refinement \ref RAIL_SupportsIEEE802154Band2P4(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3) +#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) +#else +#define RAIL_SUPPORTS_IEEE802154_BAND_2P4 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// the IEEE 802.15.4 2.4 RX channel switching. +/// See also runtime refinement \ref RAIL_IEEE802154_SupportsRxChannelSwitching(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 4)) +#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING (RAIL_SUPPORTS_IEEE802154_BAND_2P4) +#else +#define RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING 0 +#endif + +/// Boolean to indicate whether the selected chip supports a front end module. +/// See also runtime refinement \ref RAIL_IEEE802154_SupportsFemPhy(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 8) +#define RAIL_IEEE802154_SUPPORTS_FEM_PHY (RAIL_SUPPORTS_IEEE802154_BAND_2P4) +#else +#define RAIL_IEEE802154_SUPPORTS_FEM_PHY 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4E-2012 feature subset needed for Zigbee R22 GB868. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsESubsetGB868(). +#if 1 +#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 RAIL_SUPPORTS_PROTOCOL_IEEE802154 +#else +#define RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868. +#define RAIL_FEAT_IEEE802154_E_GB868_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4E-2012 Enhanced ACKing. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsEEnhancedAck(). +#if 1 +#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 +#else +#define RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. +#define RAIL_FEAT_IEEE802154_E_ENH_ACK_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK + +/// Boolean to indicate whether the selected chip supports +/// receiving IEEE 802.15.4E-2012 Multipurpose frames. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsEMultipurposeFrames(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES RAIL_IEEE802154_SUPPORTS_E_SUBSET_GB868 +#else +#define RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES. +#define RAIL_FEAT_IEEE802154_MULTIPURPOSE_FRAME_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_E_MULTIPURPOSE_FRAMES + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4G-2012 feature subset needed for Zigbee R22 GB868. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsGSubsetGB868(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG != 3) +#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 \ + ((RAIL_SUPPORTS_PROTOCOL_IEEE802154 != 0) && (RAIL_SUPPORTS_SUBGHZ_BAND != 0)) +#else +#define RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868. +#define RAIL_FEAT_IEEE802154_G_GB868_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 + +/// Boolean to indicate whether the selected chip supports +/// dynamic FEC +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsGDynFec(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG > 1) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 2) +#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC \ + RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now +#else +#define RAIL_IEEE802154_SUPPORTS_G_DYNFEC 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// Wi-SUN mode switching +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsGModeSwitch(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH \ + RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 // limit to SUBGHZ for now +#else +#define RAIL_IEEE802154_SUPPORTS_G_MODESWITCH 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4G-2012 reception and transmission of frames +/// with 4-byte CRC. +/// See also runtime refinement \ref RAIL_IEEE802154_SupportsG4ByteCrc(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 +#else +#define RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC. +#define RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_G_4BYTE_CRC + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4G-2012 reception of unwhitened frames. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsGUnwhitenedRx(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 +#else +#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX. +#define RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_RX + +/// Boolean to indicate whether the selected chip supports +/// IEEE 802.15.4G-2012 transmission of unwhitened frames. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsGUnwhitenedTx(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG != 1) +#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 +#else +#define RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX. +#define RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_G_UNWHITENED_TX + +/// Boolean to indicate whether the selected chip supports +/// canceling the frame-pending lookup event +/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND +/// when the radio transitions to a state that renders the +/// the reporting of this event moot (i.e., too late for +/// the stack to influence the outgoing ACK). +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsCancelFramePendingLookup(). +#if 1 +#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154 +#else +#define RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP. +#define RAIL_FEAT_IEEE802154_CANCEL_FP_LOOKUP_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_CANCEL_FRAME_PENDING_LOOKUP + +/// Boolean to indicate whether the selected chip supports +/// early triggering of the frame-pending lookup event +/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND +/// just after MAC address fields have been received. +/// See also runtime refinement \ref +/// RAIL_IEEE802154_SupportsEarlyFramePendingLookup(). +#if 1 +#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP RAIL_SUPPORTS_PROTOCOL_IEEE802154 +#else +#define RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP 0 +#endif +/// Backwards-compatible synonym of \ref +/// RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP. +#define RAIL_FEAT_IEEE802154_EARLY_FP_LOOKUP_SUPPORTED \ + RAIL_IEEE802154_SUPPORTS_EARLY_FRAME_PENDING_LOOKUP + +/// Boolean to indicate whether the selected chip supports dual PA configs for mode switch +/// or concurrent mode. +/// See also runtime refinement \ref RAIL_IEEE802154_SupportsDualPaConfig(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 1 +#else +#define RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG 0 +#endif + +/// Boolean to indicate whether the selected chip supports the pa power setting table. +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 1 +#else +#define RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE 0 +#endif + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/// Boolean to indicate whether the selected chip supports +/// IEEE802.15.4 2.4 GHz at 2 Mbps +/// See also runtime refinement \ref +/// RAIL_IEEE802154_Supports2MbpsPhy(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY \ + (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) +#else +#define RAIL_IEEE802154_SUPPORTS_2MBPS_PHY 0 +#endif +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/// Boolean to indicate whether the selected chip supports IEEE 802.15.4 PHY +/// with custom settings +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_1_CONFIG == 3)) +#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY (RAIL_SUPPORTS_PROTOCOL_IEEE802154 && RAIL_SUPPORTS_2P4GHZ_BAND) +#else +#define RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY 0 +#endif + +// Wi_SUN features + +/// Boolean to indicate whether the selected chip supports +/// Wi-SUN +/// See also runtime refinement \ref +/// RAIL_SupportsProtocolWiSUN(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 5) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 1 +#else +#define RAIL_SUPPORTS_PROTOCOL_WI_SUN 0 +#endif + +// WMBUS features + +/// Boolean to indicate whether the selected chip supports WMBUS simultaneous +/// M2O RX of T and C modes set by \ref RAIL_WMBUS_Config(). +/// See also runtime refinement \ref RAIL_WMBUS_SupportsSimultaneousTCRx(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 1 +#else +#define RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX 0 +#endif + +// Z-Wave features +// Some features may not be available on all platforms +// due to radio hardware limitations. + +/// Boolean to indicate whether the selected chip supports Z-Wave. +/// See also runtime refinement \ref RAIL_SupportsProtocolZWave(). +#if ((_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_SUPPORTS_PROTOCOL_ZWAVE RAIL_SUPPORTS_SUBGHZ_BAND +#else +#define RAIL_SUPPORTS_PROTOCOL_ZWAVE 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_SUPPORTS_PROTOCOL_ZWAVE. +#define RAIL_FEAT_ZWAVE_SUPPORTED RAIL_SUPPORTS_PROTOCOL_ZWAVE + +/// Boolean to indicate whether the selected chip supports energy detect PHY. +/// See also runtime refinement \ref RAIL_ZWAVE_SupportsEnergyDetectPhy(). +#if (_SILICON_LABS_32B_SERIES_1_CONFIG >= 3) +#define RAIL_ZWAVE_SUPPORTS_ED_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE +#else +#define RAIL_ZWAVE_SUPPORTS_ED_PHY 0 +#endif + +/// Boolean to indicate whether the selected chip supports concurrent PHY. +/// See also runtime refinement \ref RAIL_ZWAVE_SupportsConcPhy(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_ZWAVE_SUPPORTS_CONC_PHY RAIL_SUPPORTS_PROTOCOL_ZWAVE +#else +#define RAIL_ZWAVE_SUPPORTS_CONC_PHY 0 +#endif + +/// Boolean to indicate whether the selected chip supports SQ-based PHY. +/// See also runtime refinement \ref RAIL_SupportsSQPhy(). +#if ((_SILICON_LABS_32B_SERIES_2_CONFIG >= 3) && (_SILICON_LABS_32B_SERIES_2_CONFIG != 7)) + +#define RAIL_SUPPORTS_SQ_PHY 1 +#else +#define RAIL_SUPPORTS_SQ_PHY 0 +#endif + +/// Boolean to indicate whether the code supports Z-Wave +/// region information in PTI and +/// newer RAIL_ZWAVE_RegionConfig_t structure +/// See also runtime refinement \ref RAIL_ZWAVE_SupportsRegionPti(). +#if 1 +#define RAIL_ZWAVE_SUPPORTS_REGION_PTI RAIL_SUPPORTS_PROTOCOL_ZWAVE +#else +#define RAIL_ZWAVE_SUPPORTS_REGION_PTI 0 +#endif +/// Backwards-compatible synonym of \ref RAIL_ZWAVE_SUPPORTS_REGION_PTI. +#define RAIL_FEAT_ZWAVE_REGION_PTI RAIL_ZWAVE_SUPPORTS_REGION_PTI + +/// Boolean to indicate whether the selected chip supports raw RX data +/// sources other than \ref RAIL_RxDataSource_t::RX_PACKET_DATA. +/// See also runtime refinement \ref RAIL_SupportsRxRawData(). +#if 1 +#define RAIL_SUPPORTS_RX_RAW_DATA 1 +#else +#define RAIL_SUPPORTS_RX_RAW_DATA 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// direct mode. +/// See also runtime refinement \ref RAIL_SupportsDirectMode(). +#if ((_SILICON_LABS_32B_SERIES == 1) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) +#define RAIL_SUPPORTS_DIRECT_MODE 1 +#else +#define RAIL_SUPPORTS_DIRECT_MODE 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// RX direct mode data to FIFO. +/// See also runtime refinement \ref RAIL_SupportsRxDirectModeDataToFifo(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 1 +#else +#define RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// MFM protocol. +/// See also runtime refinement \ref RAIL_SupportsMfm(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define RAIL_SUPPORTS_MFM 1 +#else +#define RAIL_SUPPORTS_MFM 0 +#endif + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +/// Boolean to indicate whether the selected chip supports +/// 802.15.4 signal detection + #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_IEEE802154) +/// Boolean to indicate whether the selected chip supports +/// BLE signal detection + #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER (RAIL_SUPPORTS_PROTOCOL_BLE) +#else +/// Boolean to indicate whether the selected chip supports +/// 802.15.4 signal detection + #define RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER 0 +/// Boolean to indicate whether the selected chip supports +/// BLE signal detection + #define RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER 0 +#endif + +/// Boolean to indicate whether the selected chip supports +/// configurable RSSI threshold set by \ref RAIL_SetRssiDetectThreshold(). +/// See also runtime refinement \ref RAIL_SupportsRssiDetectThreshold(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (1U) +#else +#define RAIL_SUPPORTS_RSSI_DETECT_THRESHOLD (0U) +#endif + +/// Boolean to indicate whether the selected chip supports +/// thermal protection set by \ref RAIL_ConfigThermalProtection(). +/// See also runtime refinement \ref RAIL_SupportsThermalProtection(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) + #define RAIL_SUPPORTS_THERMAL_PROTECTION (1U) +#else + #define RAIL_SUPPORTS_THERMAL_PROTECTION (0U) +#endif + +/// Boolean to indicate whether the selected chip supports fast RX2RX enabled by +/// \ref RAIL_RX_OPTION_FAST_RX2RX. +/// See also runtime refinement \ref RAIL_SupportsFastRx2Rx(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2) + #define RAIL_SUPPORTS_FAST_RX2RX (1U) +#else + #define RAIL_SUPPORTS_FAST_RX2RX (0U) +#endif + +/// Boolean to indicate whether the selected chip supports collision detection +/// enabled by RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION +/// See also runtime refinement \ref RAIL_SupportsCollisionDetection(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) + #define RAIL_SUPPORTS_COLLISION_DETECTION (1U) +#else + #define RAIL_SUPPORTS_COLLISION_DETECTION (0U) +#endif + +/// Boolean to indicate whether the selected chip supports Sidewalk protocol. +/// See also runtime refinement \ref RAIL_SupportsProtocolSidewalk(). +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) \ + || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) + #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (1U) +#else + #define RAIL_SUPPORTS_PROTOCOL_SIDEWALK (0U) +#endif + +/** @} */ // end of group Features + +/** @} */ // end of group RAIL_API + +#ifdef __cplusplus +} +#endif + +#ifdef RAIL_INTERNAL_BUILD +#include "rail_features_internal.h" +#endif + +#endif // __RAIL_FEATURES_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_mfm.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_mfm.h index 3f8c318..4aad5ae 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_mfm.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_mfm.h @@ -1,193 +1,193 @@ -/***************************************************************************//** - * @file - * @brief The MFM specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_MFM_H__ -#define __RAIL_MFM_H__ - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @addtogroup MFM Multi-Level Frequency Modulation -/// @ingroup Protocol_Specific -/// @brief MFM configuration routines -/// Note that this feature is only supported on EFR32xG23 devices. -/// -/// This feature can be used to directly control the TX interpolation filter -/// input to allow for a more flexible frequency modulation scheme than the -/// standard MODEM. When doing this, the MFM buffer is treated as an array -/// of 8-bit signed data used as normalized frequency deviation to the SYNTH -/// frequency to directly control the interpolation filter input. -/// No support for frame handling, coding, nor shaping is supported. -/// Only compatible with FSK modulations. -/// -/// The functions in this group configure RAIL Multi-Level Frequency Modulation (MFM) -/// hardware acceleration features. -/// -/// To configure MFM functionality, the application must first set up -/// a RAIL instance with \ref RAIL_Init() and other setup functions. -/// Before enabling MFM, a ping-pong buffer (called buffer0 and buffer1 -/// below) must be configured via \ref RAIL_SetMfmPingPongFifo() and -/// populated with the initial buffer content. -/// MFM is enabled by setting \ref RAIL_TxDataSource_t::TX_MFM_DATA using -/// \ref RAIL_ConfigData() and is activated when transmit is started by -/// \ref RAIL_StartTx(). Once transmitting the data in the ping-pong buffers, -/// RAIL will manage them so it looks like a continuous transmission to the -/// receiver. Every time one of the ping-ping buffers has been transmitted, -/// \ref RAIL_EVENT_MFM_TX_BUFFER_DONE is triggered so the application can -/// update the data in that buffer without the need to start/stop the -/// transmission. \ref RAIL_EVENT_MFM_TX_BUFFER_DONE can be enable with \ref -/// RAIL_ConfigEvents(). -/// Use \ref RAIL_StopTx() to finish transmitting. -/// -/// @code{.c} -/// -/// uint8_t txCount = 0; -/// -/// typedef struct RAIL_MFM_Config_App { -/// RAIL_MFM_PingPongBufferConfig_t buffer; -/// RAIL_StateTiming_t timings; -/// } RAIL_MFM_Config_App_t; -/// -/// // Main RAIL_EVENT callback -/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) -/// { -/// // Increment TX counter -/// if (events & RAIL_EVENT_MFM_BUF_DONE) { -/// txCount++; -/// return; -/// } -/// } -/// } -/// -/// static const RAIL_MFM_Config_App_t mfmConfig = { -/// .buffer = { -/// .pBuffer0 = (&channelHoppingBufferSpace[0]), -/// .pBuffer1 = (&channelHoppingBufferSpace[MFM_RAW_BUF_SZ_BYTES / 4]), -/// .bufferSizeWords = (MFM_RAW_BUF_SZ_BYTES / 4) -/// }, -/// .timings = { -/// .idleToTx = 100, -/// .idleToRx = 0, -/// .rxToTx = 0, -/// .txToRx = 0, -/// .rxSearchTimeout = 0, -/// .txToRxSearchTimeout = 0 -/// }; -/// -/// RAIL_Status_t mfmInit(void) -/// { -/// // initialize MFM -/// uint32_t idx; -/// uint32_t *pDst0 = mfmConfig.pBuffer0; -/// uint32_t *pDst1 = mfmConfig.pBuffer1; -/// RAIL_Status_t status; -/// for (idx = 0; idx < (MFM_RAW_BUF_SZ_BYTES / 16); idx++) { -/// pDst0[4 * idx + 0] = 0x755A3100; -/// pDst1[4 * idx + 0] = 0x755A3100; -/// pDst0[4 * idx + 1] = 0x315A757F; -/// pDst1[4 * idx + 1] = 0x315A757F; -/// pDst0[4 * idx + 2] = 0x8BA6CF00; -/// pDst1[4 * idx + 2] = 0x8BA6CF00; -/// pDst0[4 * idx + 3] = 0xCFA68B81; -/// pDst1[4 * idx + 3] = 0xCFA68B81; -/// } -/// -/// RAIL_Status_t status; -/// railDataConfig.txSource = TX_MFM_DATA; -/// status = RAIL_SetMfmPingPongFifo(railHandle, -/// &(config->buffer)); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } -/// -/// -/// status = RAIL_ConfigData(railHandle, &railDataConfig); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } -/// -/// status = RAIL_SetStateTiming(railHandle, &(config->timings)); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } -/// -/// // start transmitting -/// return (RAIL_StartTx(railHandle, 0, 0, &schedulerInfo)); -/// } -/// -/// RAIL_Status_t mfmDeInit(void) -/// { -/// RAIL_Status_t status; -/// status = RAIL_StopTx(railHandle, RAIL_STOP_MODES_ALL); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return (status); -/// } -/// -/// railDataConfig.txSource = TX_PACKET_DATA; -/// return (RAIL_ConfigData(railHandle, &railDataConfig)); -/// } -/// @endcode -/// -/// @{ - -/** - * @struct RAIL_MFM_PingPongBufferConfig_t - * @brief A configuration structure for MFM Ping-pong buffer in RAIL. - */ -typedef struct RAIL_MFM_PingPongBufferConfig { - /** pointer to buffer0. Must be 32-bit aligned. */ - uint32_t *pBuffer0; - /** pointer to buffer1. Must be 32-bit aligned. */ - uint32_t *pBuffer1; - /** size of each buffer A and B in 32-bit words. */ - uint32_t bufferSizeWords; -} RAIL_MFM_PingPongBufferConfig_t; - -/** - * Set MFM ping-pong buffer. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] config A MFM ping-pong buffer configuration structure. - * @return A status code indicating success of the function call. - * - */ -RAIL_Status_t RAIL_SetMfmPingPongFifo(RAIL_Handle_t railHandle, - const RAIL_MFM_PingPongBufferConfig_t *config); - -/** @} */ // end of MFM - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_MFM_H__ +/***************************************************************************//** + * @file + * @brief The MFM specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_MFM_H__ +#define __RAIL_MFM_H__ + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @addtogroup MFM Multi-Level Frequency Modulation +/// @ingroup Protocol_Specific +/// @brief MFM configuration routines +/// Note that this feature is only supported on EFR32xG23 devices. +/// +/// This feature can be used to directly control the TX interpolation filter +/// input to allow for a more flexible frequency modulation scheme than the +/// standard MODEM. When doing this, the MFM buffer is treated as an array +/// of 8-bit signed data used as normalized frequency deviation to the SYNTH +/// frequency to directly control the interpolation filter input. +/// No support for frame handling, coding, nor shaping is supported. +/// Only compatible with FSK modulations. +/// +/// The functions in this group configure RAIL Multi-Level Frequency Modulation (MFM) +/// hardware acceleration features. +/// +/// To configure MFM functionality, the application must first set up +/// a RAIL instance with \ref RAIL_Init() and other setup functions. +/// Before enabling MFM, a ping-pong buffer (called buffer0 and buffer1 +/// below) must be configured via \ref RAIL_SetMfmPingPongFifo() and +/// populated with the initial buffer content. +/// MFM is enabled by setting \ref RAIL_TxDataSource_t::TX_MFM_DATA using +/// \ref RAIL_ConfigData() and is activated when transmit is started by +/// \ref RAIL_StartTx(). Once transmitting the data in the ping-pong buffers, +/// RAIL will manage them so it looks like a continuous transmission to the +/// receiver. Every time one of the ping-ping buffers has been transmitted, +/// \ref RAIL_EVENT_MFM_TX_BUFFER_DONE is triggered so the application can +/// update the data in that buffer without the need to start/stop the +/// transmission. \ref RAIL_EVENT_MFM_TX_BUFFER_DONE can be enable with \ref +/// RAIL_ConfigEvents(). +/// Use \ref RAIL_StopTx() to finish transmitting. +/// +/// @code{.c} +/// +/// uint8_t txCount = 0; +/// +/// typedef struct RAIL_MFM_Config_App { +/// RAIL_MFM_PingPongBufferConfig_t buffer; +/// RAIL_StateTiming_t timings; +/// } RAIL_MFM_Config_App_t; +/// +/// // Main RAIL_EVENT callback +/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) +/// { +/// // Increment TX counter +/// if (events & RAIL_EVENT_MFM_BUF_DONE) { +/// txCount++; +/// return; +/// } +/// } +/// } +/// +/// static const RAIL_MFM_Config_App_t mfmConfig = { +/// .buffer = { +/// .pBuffer0 = (&channelHoppingBufferSpace[0]), +/// .pBuffer1 = (&channelHoppingBufferSpace[MFM_RAW_BUF_SZ_BYTES / 4]), +/// .bufferSizeWords = (MFM_RAW_BUF_SZ_BYTES / 4) +/// }, +/// .timings = { +/// .idleToTx = 100, +/// .idleToRx = 0, +/// .rxToTx = 0, +/// .txToRx = 0, +/// .rxSearchTimeout = 0, +/// .txToRxSearchTimeout = 0 +/// }; +/// +/// RAIL_Status_t mfmInit(void) +/// { +/// // initialize MFM +/// uint32_t idx; +/// uint32_t *pDst0 = mfmConfig.pBuffer0; +/// uint32_t *pDst1 = mfmConfig.pBuffer1; +/// RAIL_Status_t status; +/// for (idx = 0; idx < (MFM_RAW_BUF_SZ_BYTES / 16); idx++) { +/// pDst0[4 * idx + 0] = 0x755A3100; +/// pDst1[4 * idx + 0] = 0x755A3100; +/// pDst0[4 * idx + 1] = 0x315A757F; +/// pDst1[4 * idx + 1] = 0x315A757F; +/// pDst0[4 * idx + 2] = 0x8BA6CF00; +/// pDst1[4 * idx + 2] = 0x8BA6CF00; +/// pDst0[4 * idx + 3] = 0xCFA68B81; +/// pDst1[4 * idx + 3] = 0xCFA68B81; +/// } +/// +/// RAIL_Status_t status; +/// railDataConfig.txSource = TX_MFM_DATA; +/// status = RAIL_SetMfmPingPongFifo(railHandle, +/// &(config->buffer)); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return (status); +/// } +/// +/// +/// status = RAIL_ConfigData(railHandle, &railDataConfig); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return (status); +/// } +/// +/// status = RAIL_SetStateTiming(railHandle, &(config->timings)); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return (status); +/// } +/// +/// // start transmitting +/// return (RAIL_StartTx(railHandle, 0, 0, &schedulerInfo)); +/// } +/// +/// RAIL_Status_t mfmDeInit(void) +/// { +/// RAIL_Status_t status; +/// status = RAIL_StopTx(railHandle, RAIL_STOP_MODES_ALL); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return (status); +/// } +/// +/// railDataConfig.txSource = TX_PACKET_DATA; +/// return (RAIL_ConfigData(railHandle, &railDataConfig)); +/// } +/// @endcode +/// +/// @{ + +/** + * @struct RAIL_MFM_PingPongBufferConfig_t + * @brief A configuration structure for MFM Ping-pong buffer in RAIL. + */ +typedef struct RAIL_MFM_PingPongBufferConfig { + /** pointer to buffer0. Must be 32-bit aligned. */ + uint32_t *pBuffer0; + /** pointer to buffer1. Must be 32-bit aligned. */ + uint32_t *pBuffer1; + /** size of each buffer A and B in 32-bit words. */ + uint32_t bufferSizeWords; +} RAIL_MFM_PingPongBufferConfig_t; + +/** + * Set MFM ping-pong buffer. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] config A MFM ping-pong buffer configuration structure. + * @return A status code indicating success of the function call. + * + */ +RAIL_Status_t RAIL_SetMfmPingPongFifo(RAIL_Handle_t railHandle, + const RAIL_MFM_PingPongBufferConfig_t *config); + +/** @} */ // end of MFM + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_MFM_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_types.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_types.h index d3b67e2..5bb72ae 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/common/rail_types.h @@ -1,5866 +1,5866 @@ -/***************************************************************************//** - * @file - * @brief This file contains the type definitions for RAIL structures, enums, - * and other types. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_TYPES_H__ -#define __RAIL_TYPES_H__ - -// Include standard type headers to help define structures -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef DOXYGEN_SHOULD_SKIP_THIS -/// The RAIL library does not use enumerations because the ARM EABI leaves their -/// size ambiguous, which causes problems if the application is built -/// with different flags than the library. Instead, uint8_t typedefs -/// are used in compiled code for all enumerations. For documentation purposes, this is -/// converted to an actual enumeration since it's much easier to read in Doxygen. -#define RAIL_ENUM(name) enum name -/// This macro is a more generic version of the \ref RAIL_ENUM() macro that -/// allows the size of the type to be overridden instead of forcing the use of -/// a uint8_t. See \ref RAIL_ENUM() for more information. -#define RAIL_ENUM_GENERIC(name, type) enum name -#else -/// Define used for the RAIL library, which sets each enumeration to a uint8_t -/// typedef and creates a named enumeration structure for the enumeration values. -#define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum -#define RAIL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum -// For debugging, use the following define to turn this back into a proper enumeration -// #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum -#endif - -/** - * @addtogroup RAIL_API - * @{ - */ - -/****************************************************************************** - * General Structures - *****************************************************************************/ -/** - * @addtogroup General - * @{ - */ - -/** - * @struct RAIL_Version_t - * @brief Contains RAIL Library Version Information. - * It is filled in by RAIL_GetVersion(). - */ -typedef struct RAIL_Version { - uint32_t hash; /**< Git hash */ - uint8_t major; /**< Major number */ - uint8_t minor; /**< Minor number */ - uint8_t rev; /**< Revision number */ - uint8_t build; /**< Build number */ - uint8_t flags; /**< Build flags */ - /** Boolean to indicate whether this is a multiprotocol library or not. */ - bool multiprotocol; -} RAIL_Version_t; - -/** - * @typedef RAIL_Handle_t - * @brief A generic handle to a particular radio (e.g. RAIL_EFR32_HANDLE), - * or a real handle of a RAIL instance, as returned from RAIL_Init(). - * - * Generic handles should be used for certain RAIL APIs that are called - * prior to RAIL initialization. However, once RAIL has been initialized, - * the real handle returned by RAIL_Init() should be used instead. - */ -typedef void *RAIL_Handle_t; - -/** - * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle - * is not recommended. As a result, another value that can't be de-referenced - * is used. - * - * This generic handle can and should be used for RAIL APIs that are called - * prior to RAIL initialization. - */ -#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL) - -/** - * @enum RAIL_Status_t - * @brief A status returned by many RAIL API calls indicating their success or - * failure. - */ -RAIL_ENUM(RAIL_Status_t) { - RAIL_STATUS_NO_ERROR, /**< RAIL function reports no error. */ - RAIL_STATUS_INVALID_PARAMETER, /**< Call to RAIL function threw an error - because of an invalid parameter. */ - RAIL_STATUS_INVALID_STATE, /**< Call to RAIL function threw an error - because it was called during an invalid - radio state. */ - RAIL_STATUS_INVALID_CALL, /**< RAIL function is called in an invalid order. */ - RAIL_STATUS_SUSPENDED, /**< RAIL function did not finish in the allotted - time. */ - RAIL_STATUS_SCHED_ERROR, /**< RAIL function could not be scheduled - by the Radio scheduler. Only issued when - using a Multiprotocol application. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_STATUS_NO_ERROR ((RAIL_Status_t) RAIL_STATUS_NO_ERROR) -#define RAIL_STATUS_INVALID_PARAMETER ((RAIL_Status_t) RAIL_STATUS_INVALID_PARAMETER) -#define RAIL_STATUS_INVALID_STATE ((RAIL_Status_t) RAIL_STATUS_INVALID_STATE) -#define RAIL_STATUS_INVALID_CALL ((RAIL_Status_t) RAIL_STATUS_INVALID_CALL) -#define RAIL_STATUS_SUSPENDED ((RAIL_Status_t) RAIL_STATUS_SUSPENDED) -#define RAIL_STATUS_SCHED_ERROR ((RAIL_Status_t) RAIL_STATUS_SCHED_ERROR) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * A pointer to init complete callback function - * - * @param[in] railHandle The initialized RAIL instance handle. - * - */ -typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle); - -/** A value to signal that RAIL should not use DMA. */ -#define RAIL_DMA_INVALID (0xFFU) - -/** - * @struct RAILSched_Config_t - * @brief Provided for backwards compatibility. - */ -typedef struct RAILSched_Config { - uint8_t buffer[1]; /**< Dummy buffer no longer used. */ -} RAILSched_Config_t; - -/** - * @typedef RAIL_StateBuffer_t - * @brief Provided for backwards compatibility. - */ -typedef uint8_t RAIL_StateBuffer_t[1]; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/** - * A linked list structure for RAIL state buffers which \ref RAIL_Init() - * utilizes for managing internal RAIL state. - */ -typedef struct RAIL_StateBufferEntry { - struct RAIL_StateBufferEntry *next; /**< pointer to next buffer in linked list */ - uint32_t bufferBytes; /**< size of the buffer */ - uint64_t *buffer; /**< pointer to the buffer in RAM */ -} RAIL_StateBufferEntry_t; - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group General - -/****************************************************************************** - * System Timing Structures - *****************************************************************************/ -/** - * @addtogroup System_Timing - * @{ - */ - -/** - * @typedef RAIL_Time_t - * @brief Time in microseconds - */ -typedef uint32_t RAIL_Time_t; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * @typedef RAIL_TimerTick_t - * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. - * - * @note \ref RAIL_TimerTick_t does not use the full 32-bit range since we also - * account for fractional error drift on timebase overflow. This counts up - * to ~17 minutes before wrapping. - * - * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between - * two \ref RAIL_TimerTick_t values to microseconds. - */ -typedef uint32_t RAIL_TimerTick_t; -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * A pointer to the callback called when the RAIL timer expires. - * - * @param[in] cbArg The argument passed to the callback. - */ -typedef void (*RAIL_TimerCallback_t)(RAIL_Handle_t cbArg); - -/** - * @enum RAIL_TimeMode_t - * @brief Specify a time offset in RAIL APIs. - * - * Different APIs use the same constants and may provide more specifics about - * how they're used but the general use for each is described below. - */ -RAIL_ENUM(RAIL_TimeMode_t) { - /** - * The time specified is an exact time in the RAIL timebase. The given - * event should happen at exactly that time. If this time is already in the - * past, an error is returned. Because the RAIL timebase wraps at 32 - * bits, there is no real 'past'. Instead, any event greater than - * 3/4 of the way into the future is considered to be in the past. - */ - RAIL_TIME_ABSOLUTE, - /** - * The time specified is relative to the current time. The event should occur - * that many ticks in the future. Delays are only guaranteed at least as long - * as the value specified. An overhead may occur between the time when the - * API is called and when the delay starts. As a result, using this for - * operations that must happen at an exact given time is not recommended. - * For that, you must use \ref RAIL_TIME_ABSOLUTE delays. - * - * Note that, if you specify a delay 0, that event is triggered as soon as - * possible. This is different than specifying an absolute time of now which - * would return an error unless it was possible. - */ - RAIL_TIME_DELAY, - /** - * The specified time is invalid and should be ignored. For some APIs this - * can also indicate that any previously stored delay should be invalidated - * and disabled. - */ - RAIL_TIME_DISABLED, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_TIME_ABSOLUTE ((RAIL_TimeMode_t) RAIL_TIME_ABSOLUTE) -#define RAIL_TIME_DELAY ((RAIL_TimeMode_t) RAIL_TIME_DELAY) -#define RAIL_TIME_DISABLED ((RAIL_TimeMode_t) RAIL_TIME_DISABLED) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/// Forward declaration of RAIL_MultiTimer -struct RAIL_MultiTimer; - -/** - * @typedef RAIL_MultiTimerCallback_t - * @brief Callback fired when timer expires. - * - * @param[in] tmr A pointer to an expired timer. - * @param[in] expectedTimeOfEvent An absolute time event fired. - * @param[in] cbArg A user-supplied callback argument. - */ -typedef void (*RAIL_MultiTimerCallback_t)(struct RAIL_MultiTimer *tmr, - RAIL_Time_t expectedTimeOfEvent, - void *cbArg); - -/** - * @struct RAIL_MultiTimer_t - * @brief RAIL timer state structure - * - * This structure is filled out and maintained internally only. - * The user/application should not alter any elements of this structure. - */ -typedef struct RAIL_MultiTimer { - RAIL_Time_t absOffset; /**< Absolute time before the next event. */ - RAIL_Time_t relPeriodic; /**< Relative, periodic time between events; 0 = timer is oneshot. */ - RAIL_MultiTimerCallback_t callback; /**< A user callback. */ - void *cbArg; /**< A user callback argument. */ - struct RAIL_MultiTimer *next; /**< A pointer to the next soft timer structure. */ - uint8_t priority; /**< A priority of the callback; 0 = highest priority; 255 = lowest. */ - bool isRunning; /**< Indicates the timer is currently running. */ - bool doCallback; /**< Indicates the callback needs to run. */ -} RAIL_MultiTimer_t; - -/** - * @enum RAIL_PacketTimePosition_t - * @brief The available packet timestamp position choices - */ -RAIL_ENUM(RAIL_PacketTimePosition_t) { - /** - * Indicate that a timestamp is not to be or was not provided. - * It is useful if the application doesn't care about packet timestamps - * and doesn't want RAIL to spend time calculating one. - */ - RAIL_PACKET_TIME_INVALID = 0, - /** - * Request the choice most expedient for RAIL to calculate, - * which may depend on the radio and/or its configuration. - * The actual choice would always be reflected in the timePosition - * field of \ref RAIL_RxPacketDetails_t or \ref RAIL_TxPacketDetails_t - * returned and would never be one of the _USED_TOTAL values. - */ - RAIL_PACKET_TIME_DEFAULT = 1, - /** - * Request the timestamp corresponding to the first preamble bit - * sent or received. - * Indicate that timestamp did not require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_PREAMBLE_START = 2, - /** - * Request the timestamp corresponding to the first preamble bit - * sent or received. - * Indicate that timestamp did require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL = 3, - /** - * Request the timestamp corresponding to right after its last - * SYNC word bit has been sent or received. - * Indicate that timestamp did not require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_SYNC_END = 4, - /** - * Request the timestamp corresponding to right after its last - * SYNC word bit has been sent or received. - * Indicate that timestamp did require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL = 5, - /** - * Request the timestamp corresponding to right after its last - * bit has been sent or received. - * Indicate that timestamp did not require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_PACKET_END = 6, - /** - * Request the timestamp corresponding to right after its last - * bit has been sent or received. - * Indicate that timestamp did require using totalPacketBytes. - */ - RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL = 7, - RAIL_PACKET_TIME_COUNT /**< A count of the choices in this enumeration. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_PACKET_TIME_INVALID ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_INVALID) -#define RAIL_PACKET_TIME_DEFAULT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_DEFAULT) -#define RAIL_PACKET_TIME_AT_PREAMBLE_START ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START) -#define RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL) -#define RAIL_PACKET_TIME_AT_SYNC_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END) -#define RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL) -#define RAIL_PACKET_TIME_AT_PACKET_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END) -#define RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL) -#define RAIL_PACKET_TIME_COUNT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_PacketTimeStamp_t - * @brief Information for calculating and representing a packet timestamp. - */ -typedef struct RAIL_PacketTimeStamp { - /** - * Timestamp of the packet in the RAIL timebase. - */ - RAIL_Time_t packetTime; - /** - * A value specifying the total length in bytes of the packet - * used when calculating the packetTime requested by the timePosition - * field. This should account for all bytes sent over the air after - * the Preamble and Sync word(s) including CRC bytes. - */ - uint16_t totalPacketBytes; - /** - * A RAIL_PacketTimePosition_t value specifying the packet position - * to return in the packetTime field. - * If this is \ref RAIL_PACKET_TIME_DEFAULT, this field will be - * updated with the actual position corresponding to the packetTime - * value filled in by a call using this structure. - */ - RAIL_PacketTimePosition_t timePosition; - /** - * In RX for EFR32xG25 only : - * A value specifying the on-air duration of the data packet, - * starting with the first bit of the PHR (i.e. end of sync word). - * Preamble and sync word duration are hence excluded. - * - * In Tx for all EFR32 Series 2 except EFR32xG21 : - * A value specifying the on-air duration of the data packet, - * starting at the preamble (i.e. includes preamble, sync word, PHR, payload and FCS). - * This value can be use to compute duty cycles. - * - * At the present time, this field is set to zero for all EFR32 Series 1 and EFR32xG21, - * and also for transmission of auto-ack. - */ - RAIL_Time_t packetDurationUs; -} RAIL_PacketTimeStamp_t; - -/** @} */ // end of group System_Timing - -/****************************************************************************** - * Sleep Structures - *****************************************************************************/ -/** - * @addtogroup Sleep - * @{ - */ - -/** - * @enum RAIL_SleepConfig_t - * @brief The configuration - */ -RAIL_ENUM(RAIL_SleepConfig_t) { - RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, /**< Disable timer sync before and after sleep. */ - RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, /**< Enable timer sync before and after sleep. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED) -#define RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_TimerSyncConfig_t - * @brief Channel values used to perform timer sync before and after sleep. - * - * The default value of this structure is provided in the - * \ref RAIL_TIMER_SYNC_DEFAULT macro. - */ -typedef struct RAIL_TimerSyncConfig { - /** - * PRS Channel used for timer sync operations. - */ - uint8_t prsChannel; - /** - * RTCC Channel used for timer sync operations - */ - uint8_t rtccChannel; - /** - * Whether to sync the timer before and after sleeping - */ - RAIL_SleepConfig_t sleep; -} RAIL_TimerSyncConfig_t; - -/** @} */ // end of group Sleep - -/****************************************************************************** - * Multiprotocol Structures - *****************************************************************************/ -/** - * @addtogroup Multiprotocol - * @{ - */ - -/** - * @struct RAIL_SchedulerInfo_t - * @brief A structure to hold information used by the scheduler. - * - * For multiprotocol versions of RAIL, this can be used to control how a receive - * or transmit operation is run. It's not necessary in single-protocol applications. - */ -typedef struct RAIL_SchedulerInfo { - /** - * The scheduler priority to use for this operation. This priority is used to - * preempt a long running lower-priority task to ensure higher-priority - * operations complete in time. A lower numerical value represents a higher - * logical priority meaning 0 is the highest priority and 255 is the lowest. - */ - uint8_t priority; - /** - * The amount of time in us that this operation can slip by into the future - * and still be run. This time is relative to the start time which may be - * the current time for relative transmits. If the scheduler can't start the - * operation by this time, it will be considered a failure. - */ - RAIL_Time_t slipTime; - /** - * The transaction time in us for this operation. Since transaction times may - * not be known exactly, use a minimum or an expected - * guess for this time. The scheduler will use the value entered here to look - * for overlaps between low-priority and high-priority tasks and attempt to - * find a schedule where all tasks get to run. - */ - RAIL_Time_t transactionTime; -} RAIL_SchedulerInfo_t; - -/** Radio Scheduler Status mask*/ -#define RAIL_SCHEDULER_STATUS_MASK 0x0FU -/** Radio Scheduler Status shift*/ -#define RAIL_SCHEDULER_STATUS_SHIFT 0 - -/** Radio Scheduler Task mask*/ -#define RAIL_SCHEDULER_TASK_MASK 0xF0U -/** Radio Scheduler Task shift*/ -#define RAIL_SCHEDULER_TASK_SHIFT 4 -/** - * @enum RAIL_SchedulerStatus_t - * @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus(). - * - * \ref Multiprotocol scheduler status is a combination of the upper 4 bits which - * constitute the type of scheduler task and the lower 4 bits which constitute - * the type of scheduler error. - */ -RAIL_ENUM(RAIL_SchedulerStatus_t) { - /** Lower 4 bits of uint8_t capture the different Radio Scheduler errors */ - /** Multiprotocol scheduler reports no error. */ - RAIL_SCHEDULER_STATUS_NO_ERROR = (0U << RAIL_SCHEDULER_STATUS_SHIFT), - /** - * The scheduler is disabled or the requested scheduler operation is - * unsupported. - */ - RAIL_SCHEDULER_STATUS_UNSUPPORTED = (1U << RAIL_SCHEDULER_STATUS_SHIFT), - /** - * The scheduled task was started but was interrupted by a higher-priority - * event before it could be completed. - */ - RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED = (2U << RAIL_SCHEDULER_STATUS_SHIFT), - /** - * Scheduled task could not be scheduled given its priority and the other - * tasks running on the system. - */ - RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL = (3U << RAIL_SCHEDULER_STATUS_SHIFT), - /** - * Calling the RAIL API associated with the Radio scheduler task returned - * an error code. See \ref RAIL_GetSchedulerStatus or \ref RAIL_GetSchedulerStatusAlt - * for more information about \ref RAIL_Status_t status. - */ - RAIL_SCHEDULER_STATUS_TASK_FAIL = (4U << RAIL_SCHEDULER_STATUS_SHIFT), - /** - * An internal error occurred in scheduler data structures, which should - * not happen and indicates a problem. - */ - RAIL_SCHEDULER_STATUS_INTERNAL_ERROR = (5U << RAIL_SCHEDULER_STATUS_SHIFT), - - /** Upper 4 bits of uint8_t capture the different Radio Scheduler tasks */ - RAIL_SCHEDULER_TASK_EMPTY = (0U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_ScheduleRx(). */ - RAIL_SCHEDULER_TASK_SCHEDULED_RX = (1U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartScheduledTx(). */ - RAIL_SCHEDULER_TASK_SCHEDULED_TX = (2U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartTx(). */ - RAIL_SCHEDULER_TASK_SINGLE_TX = (3U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartCcaCsmaTx(). */ - RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX = (4U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartCcaLbtTx(). */ - RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX = (5U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartScheduledCcaCsmaTx(). */ - RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX = (6U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartScheduledCcaLbtTx(). */ - RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX = (7U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartTxStream(). */ - RAIL_SCHEDULER_TASK_TX_STREAM = (8U << RAIL_SCHEDULER_TASK_SHIFT), - /** Radio scheduler calls \ref RAIL_StartAverageRssi(). */ - RAIL_SCHEDULER_TASK_AVERAGE_RSSI = (9U << RAIL_SCHEDULER_TASK_SHIFT), - - /** \ref RAIL_StartScheduledTx() returned error status. */ - RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_StartTx() returned error status. */ - RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_StartCcaCsmaTx() returned error status. */ - RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_StartCcaLbtTx() returned error status. */ - RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_ScheduleRx() returned error status. */ - RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_RX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_StartTxStream() returned error status. */ - RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL = (RAIL_SCHEDULER_TASK_TX_STREAM - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** \ref RAIL_StartAverageRssi() returned error status. */ - RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - - /** Multiprotocol scheduled receive function internal error. */ - RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol scheduled receive scheduling error. */ - RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_ScheduleRx() operation interrupted */ - RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_RX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol scheduled TX internal error. */ - RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol scheduled TX scheduling error. */ - RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledTx() operation interrupted */ - RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol instantaneous TX internal error. */ - RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol instantaneous TX scheduling error. */ - RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartTx() operation interrupted */ - RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol single CSMA transmit function internal error. */ - RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol single CSMA transmit scheduling error. */ - RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartCcaCsmaTx() operation interrupted */ - RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol single LBT transmit function internal error. */ - RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol single LBT transmit scheduling error. */ - RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartCcaLbtTx() operation interrupted */ - RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol scheduled CSMA transmit function internal error. */ - RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** \ref RAIL_StartScheduledCcaCsmaTx() returned error status. */ - RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** Multiprotocol scheduled CSMA transmit scheduling error. */ - RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledCcaCsmaTx() operation interrupted */ - RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol scheduled LBT transmit function internal error. */ - RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** \ref RAIL_StartScheduledCcaLbtTx() returned error status. */ - RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_TASK_FAIL), - /** Multiprotocol scheduled LBT transmit scheduling error. */ - RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartScheduledCcaLbtTx() operation interrupted */ - RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol stream transmit function internal error. */ - RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol stream transmit scheduling error. */ - RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartTxStream() operation interrupted */ - RAIL_SCHEDULER_TX_STREAM_INTERRUPTED = (RAIL_SCHEDULER_TASK_TX_STREAM - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), - - /** Multiprotocol RSSI averaging function internal error. */ - RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI - | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), - /** Multiprotocol RSSI average scheduling error. */ - RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI - | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), - /** \ref RAIL_StartAverageRssi() operation interrupted */ - RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI - | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR) -#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED) -#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED) -#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL) -#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL) -#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL) -#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL) -#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL) -#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR) - -#define RAIL_SCHEDULER_TASK_EMPTY ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_EMPTY) -#define RAIL_SCHEDULER_TASK_SCHEDULED_RX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_RX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX) -#define RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX) -#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX) -#define RAIL_SCHEDULER_TASK_TX_STREAM ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_TX_STREAM) -#define RAIL_SCHEDULER_TASK_AVERAGE_RSSI ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_AVERAGE_RSSI) - -#define RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED) -#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED) -#define RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED) -#define RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR) -#define RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_TX_STREAM_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERRUPTED) -#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR) -#define RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR) -#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_TaskType_t - * @brief Multiprotocol radio operation task types, used with - * RAIL_SetTaskPriority. - */ -RAIL_ENUM(RAIL_TaskType_t) { - /** Indicate a task started using RAIL_StartRx */ - RAIL_TASK_TYPE_START_RX, - /** Indicate a task started functions other than RAIL_StartRx */ - RAIL_TASK_TYPE_OTHER, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_TASK_TYPE_START_RX ((RAIL_TaskType_t) RAIL_TASK_TYPE_START_RX) -#define RAIL_TASK_TYPE_OTHER ((RAIL_TaskType_t) RAIL_TASK_TYPE_OTHER) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group Multiprotocol - -/****************************************************************************** - * Event Structures - *****************************************************************************/ -/** - * @addtogroup Events - * @{ - */ - -/** - * @enum RAIL_Events_t - * @brief RAIL events passed to the event callback. More than one event may be - * indicated due to interrupt latency. - */ -RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { - // RX Event Bit Shifts - - /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit */ - RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT = 0, - /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit */ - RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit */ - RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit */ - RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_LOST bit */ - RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit */ - RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit */ - RAIL_EVENT_RX_SYNC1_DETECT_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit */ - RAIL_EVENT_RX_SYNC2_DETECT_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit */ - RAIL_EVENT_RX_FRAME_ERROR_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_FULL bit */ - RAIL_EVENT_RX_FIFO_FULL_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit */ - RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit */ - RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit */ - RAIL_EVENT_RX_TIMEOUT_SHIFT, - /** Shift position of \ref RAIL_EVENT_SCHEDULED_RX_STARTED bit */ - RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit */ - RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_MISSED bit */ - RAIL_EVENT_RX_SCHEDULED_RX_MISSED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit */ - RAIL_EVENT_RX_PACKET_ABORTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit */ - RAIL_EVENT_RX_FILTER_PASSED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit */ - RAIL_EVENT_RX_TIMING_LOST_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit */ - RAIL_EVENT_RX_TIMING_DETECT_SHIFT, - /** Shift position of \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE bit */ - RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT, - /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */ - RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, - -// TX Event Bit Shifts - - /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */ - RAIL_EVENT_ZWAVE_BEAM_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */ - RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */ - RAIL_EVENT_TX_PACKET_SENT_SHIFT, - /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit */ - RAIL_EVENT_TXACK_PACKET_SENT_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit */ - RAIL_EVENT_TX_ABORTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit */ - RAIL_EVENT_TXACK_ABORTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit */ - RAIL_EVENT_TX_BLOCKED_SHIFT, - /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit */ - RAIL_EVENT_TXACK_BLOCKED_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit */ - RAIL_EVENT_TX_UNDERFLOW_SHIFT, - /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit */ - RAIL_EVENT_TXACK_UNDERFLOW_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit */ - RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit */ - RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit */ - RAIL_EVENT_TX_CCA_RETRY_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit */ - RAIL_EVENT_TX_START_CCA_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_STARTED bit */ - RAIL_EVENT_TX_STARTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_SCHEDULED_TX_MISSED bit */ - RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT, - - // Scheduler Event Bit Shifts - - /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit */ - RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT, - /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit */ - RAIL_EVENT_CONFIG_SCHEDULED_SHIFT, - /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit */ - RAIL_EVENT_SCHEDULER_STATUS_SHIFT, - - // Other Event Bit Shifts - - /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */ - RAIL_EVENT_CAL_NEEDED_SHIFT, - /** Shift position of \ref RAIL_EVENT_RF_SENSED bit */ - RAIL_EVENT_RF_SENSED_SHIFT, - /** Shift position of \ref RAIL_EVENT_PA_PROTECTION bit */ - RAIL_EVENT_PA_PROTECTION_SHIFT, - /** Shift position of \ref RAIL_EVENT_SIGNAL_DETECTED bit */ - RAIL_EVENT_SIGNAL_DETECTED_SHIFT, - /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_START bit */ - RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT, - /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_END bit */ - RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT, - /** Shift position of \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD bit */ - RAIL_EVENT_DETECT_RSSI_THRESHOLD_SHIFT, - /** Shift position of \ref RAIL_EVENT_THERMISTOR_DONE bit */ - RAIL_EVENT_THERMISTOR_DONE_SHIFT, - /** Shift position of \ref RAIL_EVENT_TX_BLOCKED_TOO_HOT bit */ - RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT, - /** Shift position of \ref RAIL_EVENT_TEMPERATURE_TOO_HOT bit */ - RAIL_EVENT_TEMPERATURE_TOO_HOT_SHIFT, - /** Shift position of \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN bit */ - RAIL_EVENT_TEMPERATURE_COOL_DOWN_SHIFT, -}; - -/** Shift position of \ref RAIL_EVENT_SCHEDULED_TX_STARTED bit */ -#define RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT -/** Shift position of \ref RAIL_EVENT_RX_DUTY_CYCLE_RX_END bit */ -#define RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT -/** Shift position of \ref RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT bit */ -#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT -/** Shift position of \ref RAIL_EVENT_MFM_TX_BUFFER_DONE bit */ -#define RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT - -// RAIL_Event_t bitmasks - -/** A value representing no events */ -#define RAIL_EVENTS_NONE 0ULL - -/** - * Occurs when the hardware-averaged RSSI is done in response to - * RAIL_StartAverageRssi() to indicate that the hardware has completed - * averaging. - * - * Call RAIL_GetAverageRssi() to get the result. - */ -#define RAIL_EVENT_RSSI_AVERAGE_DONE (1ULL << RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT) - -/** - * Occurs when the ACK timeout expires while waiting to receive the - * sync word of an expected ACK. If the timeout occurs within packet - * reception, this event won't be signaled until after packet - * completion has determined the packet wasn't the expected ACK. - * See \ref RAIL_RxPacketDetails_t::isAck for the definition of an - * expected ACK. - * - * This event only occurs after calling RAIL_ConfigAutoAck() and after - * transmitting a packet with \ref RAIL_TX_OPTION_WAIT_FOR_ACK set. - */ -#define RAIL_EVENT_RX_ACK_TIMEOUT (1ULL << RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT) - -/** - * Keeps occurring as long as the number of bytes in the receive FIFO - * exceeds the configured threshold value. - * - * Call RAIL_GetRxFifoBytesAvailable() to get the number of - * bytes available. When using this event, the threshold should be set via - * RAIL_SetRxFifoThreshold(). - * - * How to avoid sticking in the event handler (even in idle state): - * 1. Disable the event (via the config events API or the - * \ref RAIL_FIFO_THRESHOLD_DISABLED parameter) - * 2. Increase FIFO threshold - * 3. Read the FIFO (that's not an option in - * \ref RAIL_DataMethod_t::PACKET_MODE) in the event handler - */ -#define RAIL_EVENT_RX_FIFO_ALMOST_FULL (1ULL << RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT) - -/** - * Occurs whenever a packet is received with \ref RAIL_RX_PACKET_READY_SUCCESS - * or \ref RAIL_RX_PACKET_READY_CRC_ERROR. - * - * Call RAIL_GetRxPacketInfo() to get - * basic information about the packet along with a handle to this packet for - * subsequent use with RAIL_PeekRxPacket(), RAIL_GetRxPacketDetails(), - * RAIL_HoldRxPacket(), and RAIL_ReleaseRxPacket() as needed. - */ -#define RAIL_EVENT_RX_PACKET_RECEIVED (1ULL << RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT) - -/** - * Occurs when the radio has lost a preamble. - * - * This event can occur multiple - * times while searching for a packet and is generally used for diagnostic - * purposes. It can only occur after a - * \ref RAIL_EVENT_RX_PREAMBLE_DETECT event has already occurred. - * - * @note See warning for \ref RAIL_EVENT_RX_PREAMBLE_DETECT. - */ -#define RAIL_EVENT_RX_PREAMBLE_LOST (1ULL << RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT) - -/** - * Occurs when the radio has detected a preamble. - * - * This event can occur multiple - * times while searching for a packet and is generally used for diagnostic - * purposes. It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT - * event has already occurred. - * - * @warning This event, along with \ref RAIL_EVENT_RX_PREAMBLE_LOST, - * may not work on some demodulators. Some demodulators usurped the signals - * on which these events are based for another purpose. These demodulators - * in particular are available on the EFR32xG23, EFR32xG25, and the EFR32xG28 - * platforms. Enabling these events on these platforms may cause the - * events to fire infinitely and possibly freeze the application. - */ -#define RAIL_EVENT_RX_PREAMBLE_DETECT (1ULL << RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT) - -/** - * Occurs when the first sync word is detected. - * - * After this event occurs, one of - * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. - */ -#define RAIL_EVENT_RX_SYNC1_DETECT (1ULL << RAIL_EVENT_RX_SYNC1_DETECT_SHIFT) - -/** - * Occurs when the second sync word is detected. - * - * After this event occurs, one of - * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. - */ -#define RAIL_EVENT_RX_SYNC2_DETECT (1ULL << RAIL_EVENT_RX_SYNC2_DETECT_SHIFT) - -/** - * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_CRC_ERROR - * which only happens after any filtering has passed. - * - * For EFR32 parts, this event includes CRC errors, block decoding errors, - * and illegal frame length -- when detected after filtering. (When such - * errors are detected during filtering, they're signaled as \ref - * RAIL_EVENT_RX_PACKET_ABORTED instead.) - * - * If \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, this event will not - * occur for CRC errors, but could still occur for the other errors. - */ -#define RAIL_EVENT_RX_FRAME_ERROR (1ULL << RAIL_EVENT_RX_FRAME_ERROR_SHIFT) - -/** - * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event - * occurs coincident to a receive packet completion event in which the - * receive FIFO or any supplemental packet metadata FIFO (see \ref - * Data_Management) are full and further packet reception is jeopardized. - * - * It signals that an overflow is imminent (and may already have occurred) - * telling the application it should release the oldest packet(s) as soon - * as possible. This event may may be posted multiple times with subsequent - * receive completion events if the FIFO(s) remain full, and should also - * occur coincident with \ref RAIL_EVENT_RX_FIFO_OVERFLOW. - * - * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event - * is not tied to packet completion and will occur coincident with - * \ref RAIL_EVENT_RX_FIFO_OVERFLOW when the receive FIFO has filled and - * overflowed. The application should consume receive FIFO data via - * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data. - */ -#define RAIL_EVENT_RX_FIFO_FULL (1ULL << RAIL_EVENT_RX_FIFO_FULL_SHIFT) - -/** - * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event - * occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_OVERFLOW - * due to overflowing the receive FIFO or any supplemental packet metadata - * FIFO (see \ref Data_Management). - * - * The radio suspends receiving packets until this event is posted and - * the receive FIFO(s) have been fully processed (drained and released - * or reset). It is not guaranteed that a \ref RAIL_EVENT_RX_FIFO_FULL - * will precede this event, but both events should be coincident. - * - * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event - * is not tied to packet completion and will occur coincident with - * \ref RAIL_EVENT_RX_FIFO_FULL when the receive FIFO has filled and - * overflowed. The application should consume receive FIFO data via - * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data. - */ -#define RAIL_EVENT_RX_FIFO_OVERFLOW (1ULL << RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT) - -/** - * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_FILTERED - * because its address does not match the filtering settings. - * - * This event can only occur after calling RAIL_EnableAddressFilter(). - */ -#define RAIL_EVENT_RX_ADDRESS_FILTERED (1ULL << RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT) - -/** - * Occurs when an RX event times out. - * - * This event can only occur if the - * RAIL_StateTiming_t::rxSearchTimeout passed to RAIL_SetStateTiming() is - * not zero. - */ -#define RAIL_EVENT_RX_TIMEOUT (1ULL << RAIL_EVENT_RX_TIMEOUT_SHIFT) - -/** - * Occurs when a scheduled RX begins turning on the receiver. - * This event has the same numerical value as RAIL_EVENT_SCHEDULED_TX_STARTED - * because one cannot schedule both RX and TX simultaneously. - */ -#define RAIL_EVENT_SCHEDULED_RX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT) - -/** - * Occurs when a scheduled TX begins turning on the transmitter. - * This event has the same numerical value as RAIL_EVENT_SCHEDULED_RX_STARTED - * because one cannot schedule both RX and TX simultaneously. - */ -#define RAIL_EVENT_SCHEDULED_TX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT) - -/** - * Occurs when the scheduled RX window ends. - * - * This event only occurs in response - * to a scheduled receive timeout after calling RAIL_ScheduleRx(). If - * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as false, - * this event will occur unless the receive is aborted (due to a call to - * RAIL_Idle() or a scheduler preemption, for instance). If - * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as true, - * any of the \ref RAIL_EVENTS_RX_COMPLETION events occurring will also cause - * this event not to occur, since the scheduled receive will end with the - * transition at the end of the packet. However, if the application has not - * enabled the specific \ref RAIL_EVENTS_RX_COMPLETION event which implicitly - * ended the scheduled receive, this event will be posted instead. - */ -#define RAIL_EVENT_RX_SCHEDULED_RX_END (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT) - -/** - * Occurs when start of a scheduled receive is missed - * - * This can occur if the radio is put to sleep and not woken up with enough time - * to configure the scheduled receive event. - */ -#define RAIL_EVENT_RX_SCHEDULED_RX_MISSED (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_MISSED_SHIFT) - -/** - * Occurs when a receive is aborted during filtering with - * \ref RAIL_RX_PACKET_ABORT_FORMAT or after filtering with - * \ref RAIL_RX_PACKET_ABORT_ABORTED for reasons other than address - * filtering mismatch (which triggers \ref RAIL_EVENT_RX_ADDRESS_FILTERED - * instead). - * - * For EFR32 parts, this event includes CRC errors, block decoding errors, - * illegal frame length, and other RAIL built-in protocol-specific packet - * content errors -- when detected during filtering. (When such errors - * are detected after filtering, they're signaled as \ref - * RAIL_EVENT_RX_FRAME_ERROR instead.) It also includes application or - * multiprotocol scheduler aborting a receive after filtering has passed. - */ -#define RAIL_EVENT_RX_PACKET_ABORTED (1ULL << RAIL_EVENT_RX_PACKET_ABORTED_SHIFT) - -/** - * Occurs when the packet has passed any configured address and frame - * filtering options. - * - * This event will only occur between the start of the - * packet, indicated by \ref RAIL_EVENT_RX_SYNC1_DETECT or - * \ref RAIL_EVENT_RX_SYNC2_DETECT and one of the events in the - * \ref RAIL_EVENTS_RX_COMPLETION mask. It will always occur before or - * concurrently with \ref RAIL_EVENT_RX_PACKET_RECEIVED. If IEEE 802.15.4 frame - * and address filtering are enabled, this event will occur immediately after - * destination address filtering. - */ -#define RAIL_EVENT_RX_FILTER_PASSED (1ULL << RAIL_EVENT_RX_FILTER_PASSED_SHIFT) - -/** - * Occurs when the modem timing is lost. - * - * This event can occur multiple times - * while searching for a packet and is generally used for diagnostic purposes. - * It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT event has - * already occurred. - * - * @note See warning for \ref RAIL_EVENT_RX_TIMING_DETECT. - */ -#define RAIL_EVENT_RX_TIMING_LOST (1ULL << RAIL_EVENT_RX_TIMING_LOST_SHIFT) - -/** - * Occurs when the modem timing is detected. - * - * This event can occur multiple times - * while searching for a packet and is generally used for diagnostic purposes. - * - * @warning This event, along with \ref RAIL_EVENT_RX_TIMING_LOST, - * may not work on some demodulators. Some demodulators usurped the signals - * on which these events are based for another purpose. These demodulators - * in particular are available on the EFR32xG23, EFR32xG25, and the EFR32xG28 - * platforms. Enabling these events on these platforms may cause the - * events to fire infinitely and possibly freeze the application. - */ -#define RAIL_EVENT_RX_TIMING_DETECT (1ULL << RAIL_EVENT_RX_TIMING_DETECT_SHIFT) - -/** - * Occurs when RX Channel Hopping is enabled and channel hopping finishes - * receiving on the last channel in its sequence. - * - * The intent behind this event - * is to allow the user to keep the radio on for as short a time as possible. - * That is, once the channel sequence is complete, the application will receive - * this event and can trigger a sleep/idle until it is necessary to cycle - * through the channels again. If this event is left on indefinitely and not - * handled it will likely be a fairly noisy event, as it continues to fire - * each time the hopping algorithm cycles through the channel sequence. - * - * @warning This event currently does not occur when using \ref - * RAIL_RxChannelHoppingMode_t::RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL. - * As a workaround, an application can monitor the current hop channel - * with \ref RAIL_GetChannelAlt(). - */ -#define RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE (1ULL << RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT) - -/** - * Occurs during RX duty cycle mode when the radio finishes its time in - * receive mode. - * - * The application can then trigger a sleep/idle until it - * needs to listen again. - */ -#define RAIL_EVENT_RX_DUTY_CYCLE_RX_END (1ULL << RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT) - -/** - * Indicate a Data Request is received when using IEEE 802.15.4 - * functionality. - * - * It occurs when the command byte of an incoming ACK-requesting MAC Control - * frame is for a data request. This callback is called before - * the packet is fully received to allow the node to have more time to decide - * whether to indicate a frame is pending in the outgoing ACK. This event only - * occurs if the RAIL IEEE 802.15.4 functionality is enabled, but will never - * occur if promiscuous mode is enabled via - * RAIL_IEEE802154_SetPromiscuousMode(). - * - * Call RAIL_IEEE802154_GetAddress() to get the source address of the packet. - */ -#define RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND (1ULL << RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT) - -/** - * Indicate a Z-Wave Beam Request relevant to the node was received. - * - * This event only occurs if the RAIL Z-Wave functionality is enabled - * and its \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. - * This event is used in lieu of \ref RAIL_EVENT_RX_PACKET_RECEIVED, - * which is reserved for Z-Wave packets other than Beams. - * - * Call RAIL_ZWAVE_GetBeamNodeId() to get the NodeId to which the Beam was - * targeted, which would be either the broadcast id 0xFF or the node's own - * single-cast id. - * - * @note All Z-Wave Beam requests are generally discarded, triggering - * \ref RAIL_EVENT_RX_PACKET_ABORTED. - */ -#define RAIL_EVENT_ZWAVE_BEAM (1ULL << RAIL_EVENT_ZWAVE_BEAM_SHIFT) - -/** - * Indicate a MFM buffer has completely transmitted. - * - * This event only occurs if the RAIL MFM functionality is enabled - * and a MFM buffer has completely transmitted. - * - * Following this event, the application can update the MFM buffer - * that has transmitted to be used for the next transmission. - */ -#define RAIL_EVENT_MFM_TX_BUFFER_DONE (1ULL << RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT) - -/** - * Indicate a request for populating Z-Wave LR ACK packet. - * This event only occurs if the RAIL Z-Wave functionality is enabled. - * - * Following this event, the application must call \ref RAIL_ZWAVE_SetLrAckData() - * to populate noise floor, TX power and receive RSSI fields of the Z-Wave - * Long Range ACK packet. - */ -#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND (1ULL << RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT) - -/** - * The mask representing all events that determine the end of a received - * packet. - * - * After a \ref RAIL_EVENT_RX_SYNC1_DETECT or a - * \ref RAIL_EVENT_RX_SYNC2_DETECT, - * exactly one of the following events will occur. When one of these events - * occurs, a state transition will take place based on the parameter passed to - * RAIL_SetRxTransitions(). The RAIL_StateTransitions_t::success transition - * will be followed only if the \ref RAIL_EVENT_RX_PACKET_RECEIVED event occurs. - * Any of the other events will trigger the RAIL_StateTransitions_t::error - * transition. - */ -#define RAIL_EVENTS_RX_COMPLETION (RAIL_EVENT_RX_PACKET_RECEIVED \ - | RAIL_EVENT_RX_PACKET_ABORTED \ - | RAIL_EVENT_RX_FRAME_ERROR \ - | RAIL_EVENT_RX_FIFO_OVERFLOW \ - | RAIL_EVENT_RX_ADDRESS_FILTERED \ - | RAIL_EVENT_RX_SCHEDULED_RX_MISSED) - -// TX Event Bitmasks - -/** - * Occurs when the number of bytes in the transmit FIFO falls below the - * configured threshold value. - * - * This event does not occur on initialization or after resetting the transmit - * FIFO with RAIL_ResetFifo(). - * - * Call RAIL_GetTxFifoSpaceAvailable() to get the - * number of bytes available in the transmit FIFO at the time of the callback - * dispatch. When using this event, the threshold should be set via - * RAIL_SetTxFifoThreshold(). - */ -#define RAIL_EVENT_TX_FIFO_ALMOST_EMPTY (1ULL << RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT) - -/** - * Occurs after a packet has been transmitted. - * - * Call RAIL_GetTxPacketDetails() - * to get information about the packet that was transmitted. - * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. - */ -#define RAIL_EVENT_TX_PACKET_SENT (1ULL << RAIL_EVENT_TX_PACKET_SENT_SHIFT) - -/** - * Occurs after an ACK packet has been transmitted. - * - * Call RAIL_GetTxPacketDetails() - * to get information about the packet that was transmitted. This event can only occur - * after calling RAIL_ConfigAutoAck(). - * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. - */ -#define RAIL_EVENT_TXACK_PACKET_SENT (1ULL << RAIL_EVENT_TXACK_PACKET_SENT_SHIFT) - -/** - * Occurs when a transmit is aborted by the user. - * - * This can happen due to calling RAIL_Idle() or due to a scheduler - * preemption. - * - * @note The Transmit FIFO is left in an indeterminate state and should be - * reset prior to reuse for sending a new packet. Contrast this - * with \ref RAIL_EVENT_TX_BLOCKED. - */ -#define RAIL_EVENT_TX_ABORTED (1ULL << RAIL_EVENT_TX_ABORTED_SHIFT) - -/** - * Occurs when an ACK transmit is aborted by the user. - * - * This event can only - * occur after calling RAIL_ConfigAutoAck(), which can happen due to calling - * RAIL_Idle() or due to a scheduler preemption. - */ -#define RAIL_EVENT_TXACK_ABORTED (1ULL << RAIL_EVENT_TXACK_ABORTED_SHIFT) - -/** - * Occurs when a transmit is blocked from occurring because - * RAIL_EnableTxHoldOff() was called. - * - * @note Since the transmit never started, the Transmit FIFO remains intact - * after this event -- no packet data was consumed from it. Contrast this - * with \ref RAIL_EVENT_TX_ABORTED. - */ -#define RAIL_EVENT_TX_BLOCKED (1ULL << RAIL_EVENT_TX_BLOCKED_SHIFT) - -/** - * Occurs when an ACK transmit is blocked from occurring because - * RAIL_EnableTxHoldOff() was called. - * - * This event can only occur after calling RAIL_ConfigAutoAck(). - */ -#define RAIL_EVENT_TXACK_BLOCKED (1ULL << RAIL_EVENT_TXACK_BLOCKED_SHIFT) - -/** - * Occurs when the transmit buffer underflows. - * - * This can happen due to the - * transmitted packet specifying an unintended length based on the current - * radio configuration or due to RAIL_WriteTxFifo() calls not keeping up with - * the transmit rate if the entire packet isn't loaded at once. - * - * @note The Transmit FIFO is left in an indeterminate state and should be - * reset prior to reuse for sending a new packet. Contrast this - * with \ref RAIL_EVENT_TX_BLOCKED. - */ -#define RAIL_EVENT_TX_UNDERFLOW (1ULL << RAIL_EVENT_TX_UNDERFLOW_SHIFT) - -/** - * Occurs when the ACK transmit buffer underflows. - * - * This can happen due to the - * transmitted packet specifying an unintended length based on the current - * radio configuration or due to RAIL_WriteAutoAckFifo() not being called at - * all before an ACK transmit. - * - * This event can only occur after calling RAIL_ConfigAutoAck(). - */ -#define RAIL_EVENT_TXACK_UNDERFLOW (1ULL << RAIL_EVENT_TXACK_UNDERFLOW_SHIFT) - -/** - * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) - * succeeds. - * - * This event can only happen after calling RAIL_StartCcaCsmaTx() or - * RAIL_StartCcaLbtTx(). - */ -#define RAIL_EVENT_TX_CHANNEL_CLEAR (1ULL << RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT) - -/** - * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) - * fails. - * - * This event can only happen after calling RAIL_StartCcaCsmaTx() or - * RAIL_StartCcaLbtTx(). - * - * @note Since the transmit never started, the Transmit FIFO remains intact - * after this event -- no packet data was consumed from it. - */ -#define RAIL_EVENT_TX_CHANNEL_BUSY (1ULL << RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT) - -/** - * Occurs during CSMA or LBT when an individual Clear Channel Assessment (CCA) - * check fails, but there are more tries needed before the overall operation - * completes. - * - * This event can occur multiple times based on the configuration - * of the ongoing CSMA or LBT transmission. It can only happen after - * calling RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(). - */ -#define RAIL_EVENT_TX_CCA_RETRY (1ULL << RAIL_EVENT_TX_CCA_RETRY_SHIFT) - -/** - * Occurs when the receiver is activated to perform a Clear Channel Assessment - * (CCA) check. - * - * This event generally precedes the actual start of a CCA check by roughly - * the \ref RAIL_StateTiming_t::idleToRx time (subject to - * \ref RAIL_MINIMUM_TRANSITION_US). It can - * occur multiple times based on the configuration of the ongoing CSMA or LBT - * transmission. It can only happen after calling RAIL_StartCcaCsmaTx() - * or RAIL_StartCcaLbtTx(). - */ -#define RAIL_EVENT_TX_START_CCA (1ULL << RAIL_EVENT_TX_START_CCA_SHIFT) - -/** - * Occurs when the radio starts transmitting a normal packet on the air. - * - * A start-of-transmit timestamp is captured for this event. It can be - * retrieved by calling \ref RAIL_GetTxTimePreambleStart() passing \ref - * RAIL_TX_STARTED_BYTES for its totalPacketBytes parameter. - * - * @note This event does not apply to ACK transmits. Currently there - * is no equivalent event or timestamp captured for the start of an - * ACK transmit. - */ -#define RAIL_EVENT_TX_STARTED (1ULL << RAIL_EVENT_TX_STARTED_SHIFT) - -/** - * A value to pass as \ref RAIL_GetTxTimePreambleStart() totalPacketBytes - * parameter to retrieve the \ref RAIL_EVENT_TX_STARTED timestamp. - */ -#define RAIL_TX_STARTED_BYTES 0U - -/** - * Occurs when the start of a scheduled transmit is missed - * - * This can occur if the radio is put to sleep and not woken up with enough time - * to configure the scheduled transmit event. - * - * @note Since the transmit never started, the Transmit FIFO remains intact - * after this event -- no packet data was consumed from it. - */ -#define RAIL_EVENT_TX_SCHEDULED_TX_MISSED (1ULL << RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT) - -/** - * A mask representing all events that determine the end of a transmitted - * packet. After a \ref RAIL_STATUS_NO_ERROR return value - * from one of the transmit functions, exactly one of the following - * events will occur. When one of these events occurs, a state transition - * takes place based on the parameter passed to RAIL_SetTxTransitions(). - * The RAIL_StateTransitions_t::success transition will be followed only - * if the \ref RAIL_EVENT_TX_PACKET_SENT event occurs. Any of the other - * events will trigger the RAIL_StateTransitions_t::error transition. - */ -#define RAIL_EVENTS_TX_COMPLETION (RAIL_EVENT_TX_PACKET_SENT \ - | RAIL_EVENT_TX_ABORTED \ - | RAIL_EVENT_TX_BLOCKED \ - | RAIL_EVENT_TX_UNDERFLOW \ - | RAIL_EVENT_TX_CHANNEL_BUSY \ - | RAIL_EVENT_TX_SCHEDULED_TX_MISSED) - -/** - * A mask representing all events that determine the end of a transmitted - * ACK packet. After an ACK-requesting receive, exactly one of the - * following events will occur. When one of these events occurs, a state - * transition takes place based on the RAIL_AutoAckConfig_t::rxTransitions - * passed to RAIL_ConfigAutoAck(). The receive transitions are used because the - * transmitted ACK packet is considered a part of the ACK-requesting received - * packet. The RAIL_StateTransitions_t::success transition will be followed - * only if the \ref RAIL_EVENT_TXACK_PACKET_SENT event occurs. Any of the other - * events will trigger the RAIL_StateTransitions_t::error transition. - */ -#define RAIL_EVENTS_TXACK_COMPLETION (RAIL_EVENT_TXACK_PACKET_SENT \ - | RAIL_EVENT_TXACK_ABORTED \ - | RAIL_EVENT_TXACK_BLOCKED \ - | RAIL_EVENT_TXACK_UNDERFLOW) - -// Scheduler Event Bitmasks - -/** - * Occurs when the scheduler switches away from this configuration. - * - * This event will occur in dynamic multiprotocol scenarios each - * time a protocol is shutting down. When it does occur, it will be - * the only event passed to RAIL_Config_t::eventsCallback. Therefore, - * to optimize protocol switch time, this event should be handled - * among the first in that callback, and then the application can return - * immediately. - * - * @note: To minimize protocol switch time, Silicon Labs recommends this event - * event being turned off unless it is used. - */ -#define RAIL_EVENT_CONFIG_UNSCHEDULED (1ULL << RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT) - -/** - * Occurs when the scheduler switches to this configuration. - * - * This event will occur in dynamic multiprotocol scenarios each time - * a protocol is starting up. When it does occur, it will - * be the only event passed to RAIL_Config_t::eventsCallback. Therefore, in - * order to optimize protocol switch time, this event should be handled among - * the first in that callback, and then the application can return immediately. - * - * @note: To minimize protocol switch time, Silicon Labs recommends this event - * event being turned off unless it is used. - */ -#define RAIL_EVENT_CONFIG_SCHEDULED (1ULL << RAIL_EVENT_CONFIG_SCHEDULED_SHIFT) - -/** - * Occurs when the scheduler has a status to report. - * - * The exact status can be found with RAIL_GetSchedulerStatus(). - * See \ref RAIL_SchedulerStatus_t for more details. When this event - * does occur, it will be the only event passed to RAIL_Config_t::eventsCallback. - * Therefore, to optimize protocol switch time, this event should - * be handled among the first in that callback, and then the application - * can return immediately. - * - * @note RAIL_GetSchedulerStatus() is only valid to call during the time frame - * of the RAIL_Config_t::eventsCallback. - * - * @note: To minimize protocol switch time, Silicon Labs recommends this event - * event being turned off unless it is used. - */ -#define RAIL_EVENT_SCHEDULER_STATUS (1ULL << RAIL_EVENT_SCHEDULER_STATUS_SHIFT) - -// Other Event Bitmasks - -/** - * Occurs when the application needs to run a calibration, as - * determined by the RAIL library. - * - * The application determines the opportune time to call RAIL_Calibrate(). - */ -#define RAIL_EVENT_CAL_NEEDED (1ULL << RAIL_EVENT_CAL_NEEDED_SHIFT) - -/** - * Occurs when RF energy is sensed from the radio. This event can be used as - * an alternative to the callback passed as \ref RAIL_RfSense_CallbackPtr_t. - * - * Alternatively, the application can poll using \ref RAIL_IsRfSensed(). - * - * @note This event will not occur when waking up from EM4. Prefer - * \ref RAIL_IsRfSensed() when waking from EM4. - */ -#define RAIL_EVENT_RF_SENSED (1ULL << RAIL_EVENT_RF_SENSED_SHIFT) - -/** - * Occurs when PA protection circuit kicks in. - */ -#define RAIL_EVENT_PA_PROTECTION (1ULL << RAIL_EVENT_PA_PROTECTION_SHIFT) - -/** - * Occurs after enabling the signal detection using \ref RAIL_BLE_EnableSignalDetection - * or \ref RAIL_IEEE802154_EnableSignalDetection when a signal is detected. - * This is only used on platforms that support signal identifier, where - * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER or - * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER is true. - */ -#define RAIL_EVENT_SIGNAL_DETECTED (1ULL << RAIL_EVENT_SIGNAL_DETECTED_SHIFT) - -/** - * Occurs when a Wi-SUN mode switch packet has been received, after switching to the new PHY. - * - * It doesn't occur when a mode switch packet is transmitted. - * - * IEEE 802.15.4 option \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH must be enabled for this event to occur. - * - * Only available on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. - */ -#define RAIL_EVENT_IEEE802154_MODESWITCH_START (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT) - -/** - * Occurs when switching back to the original base PHY in effect prior to the Wi-SUN mode switch reception. - * - * This typically occurs if no packet is seen within some timeframe after the mode switch packet was received - * or if the first packet received in the new PHY is aborted, filtered, or fails CRC. - * - * IEEE 802.15.4 option \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH must be enabled for this event to occur. - * - * Only available on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. - */ -#define RAIL_EVENT_IEEE802154_MODESWITCH_END (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT) - -/** - * Occurs when the sampled RSSI is above the threshold set by - * \ref RAIL_SetRssiDetectThreshold(). - */ -#define RAIL_EVENT_DETECT_RSSI_THRESHOLD (1ULL << RAIL_EVENT_DETECT_RSSI_THRESHOLD_SHIFT) - -/** - * Occurs when the thermistor has finished its measurement in response to - * \ref RAIL_StartThermistorMeasurement(). - */ -#define RAIL_EVENT_THERMISTOR_DONE (1ULL << RAIL_EVENT_THERMISTOR_DONE_SHIFT) - -/** - * Occurs when a Tx has been blocked because of temperature exceeding - * the safety threshold. - * - * Only occurs on platforms where \ref RAIL_SUPPORTS_EFF is true, - * and only when also reporting \ref RAIL_EVENT_TX_BLOCKED. - */ -#define RAIL_EVENT_TX_BLOCKED_TOO_HOT (1ULL << RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT) - -/** - * Occurs when die internal temperature exceeds the temperature threshold subtracted - * by the cool down parameter from \ref RAIL_ChipTempConfig_t. - * Transmits are blocked until temperature has cooled enough, indicated by - * \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN. - * - * Only occurs on platforms where \ref RAIL_SUPPORTS_THERMAL_PROTECTION is true. - */ -#define RAIL_EVENT_TEMPERATURE_TOO_HOT (1ULL << RAIL_EVENT_TEMPERATURE_TOO_HOT_SHIFT) - -/** - * Occurs when die internal temperature falls below the temperature threshold subtracted - * by the cool down parameter from \ref RAIL_ChipTempConfig_t. - * Transmits are no longer blocked by temperature limitation, indicated by - * \ref RAIL_EVENT_TEMPERATURE_TOO_HOT. - * - * Only occurs on platforms where \ref RAIL_SUPPORTS_THERMAL_PROTECTION is true. - */ -#define RAIL_EVENT_TEMPERATURE_COOL_DOWN (1ULL << RAIL_EVENT_TEMPERATURE_COOL_DOWN_SHIFT) - -/** A value representing all possible events */ -#define RAIL_EVENTS_ALL 0xFFFFFFFFFFFFFFFFULL - -/** @} */ // end of group Events - -/****************************************************************************** - * General Structures (part 2) - *****************************************************************************/ -/** - * @addtogroup General - * @{ - */ - -/** - * @struct RAIL_Config_t - * @brief RAIL configuration structure. - */ -typedef struct RAIL_Config { - /** - * A pointer to a function, which is called whenever a RAIL event occurs. - * - * @param[in] railHandle A handle for a RAIL instance. - * @param[in] events A bit mask of RAIL events. - * - * See the \ref RAIL_Events_t documentation for the list of RAIL events. - */ - void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events); - /** - * Provided for backwards compatibility. Ignored. - */ - void *protocol; - /** - * Provided for backwards compatibility. Ignored. - */ - RAILSched_Config_t *scheduler; - /** - * Provided for backwards compatibility. Ignored. - */ - RAIL_StateBuffer_t buffer; -} RAIL_Config_t; - -/** @} */ // end of group General - -/****************************************************************************** - * PA Power Amplifier Structures - *****************************************************************************/ -/** - * @addtogroup PA Power Amplifier (PA) - * @ingroup Transmit - * @{ - */ - -/** - * The transmit power in deci-dBm units (e.g., 4.5 dBm -> 45 deci-dBm). These - * values are used by the conversion functions to convert a \ref - * RAIL_TxPowerLevel_t to deci-dBm for the application consumption. On EFR32, - * they can range from \ref RAIL_TX_POWER_MIN to \ref RAIL_TX_POWER_MAX. - */ -typedef int16_t RAIL_TxPower_t; - -/** The maximum valid value for a \ref RAIL_TxPower_t. */ -#define RAIL_TX_POWER_MAX ((RAIL_TxPower_t)0x7FFF) -/** The minimum valid value for a \ref RAIL_TxPower_t. */ -#define RAIL_TX_POWER_MIN ((RAIL_TxPower_t)0x8000) - -/** The maximum power in deci-dBm the curve supports */ -#define RAIL_TX_POWER_CURVE_DEFAULT_MAX ((RAIL_TxPower_t)200) -/** The increment step in deci-dBm for calculating power level*/ -#define RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT ((RAIL_TxPower_t)40) - -/// mV are used for all TX power voltage values. -/// TX power voltages take and return voltages multiplied by this factor. -#define RAIL_TX_POWER_VOLTAGE_SCALING_FACTOR 1000 - -/// deci-dBm are used for all TX power dBm values. -/// All dBm inputs to TX power functions take dBm power times this factor. -#define RAIL_TX_POWER_DBM_SCALING_FACTOR 10 - -/** - * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher - * numerical value corresponds to a higher output power. These are referred to - * as 'raw (values/units)'. On EFR32, they can range from one of \ref - * RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MIN, or - * \ref RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN to one of \ref - * RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MAX, and \ref - * RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, respectively, depending on the selected \ref - * RAIL_TxPowerMode_t. - */ -typedef uint8_t RAIL_TxPowerLevel_t; - -/** - * Invalid RAIL_TxPowerLevel_t value returned when an error occurs - * with RAIL_GetTxPower. - */ -#define RAIL_TX_POWER_LEVEL_INVALID (255U) - -/** - * Sentinel value that can be passed to RAIL_SetTxPower to set - * the highest power level available on the current PA, regardless - * of which one is selected. - */ -#define RAIL_TX_POWER_LEVEL_MAX (254U) - -/** - * PA power setting used directly by the \ref RAIL_GetPaPowerSetting() and - * \ref RAIL_SetPaPowerSetting() APIs which is decoded to the actual - * hardware register value(s). - */ -typedef uint32_t RAIL_PaPowerSetting_t; - -/** - * Returned by \ref RAIL_GetPaPowerSetting when the device does - * not support the dBm to power setting mapping table. - */ -#define RAIL_TX_PA_POWER_SETTING_UNSUPPORTED (0U) - -/** - * @enum RAIL_TxPowerMode_t - * @brief An enumeration of the EFR32 power modes. - * - * The power modes on the EFR32 correspond to the different on-chip PAs that - * are available. For more information about the power and performance - * characteristics of a given amplifier, see the data sheet. - */ -RAIL_ENUM(RAIL_TxPowerMode_t) { - /** - * High-power 2.4 GHz amplifier - * EFR32xG1X: up to 20 dBm, raw values: 0-252 - * EFR32xG21: up to 20 dBm, raw values: 1-180 - * EFR32xG22: up to 6 dBm, raw values: 1-128 - * EFR32xG24: up to 20 dBm, raw values: 0-180, or - * up to 10 dBm, raw values: 0-90 - * EFR32xG26: same as EFR32xG24 - * EFR32xG27: up to 6 dBm, raw values: 1-128 - * EFR32xG28: up to 10 dBm, raw values: 0-240 - * Not supported on other platforms. - */ - RAIL_TX_POWER_MODE_2P4GIG_HP = 0U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HP instead. */ - RAIL_TX_POWER_MODE_2P4_HP = RAIL_TX_POWER_MODE_2P4GIG_HP, - /** - * Mid-power 2.4 GHz amplifier - * EFR32xG21: up to 10 dBm, raw values: 1-90 - * Not supported on other platforms. - */ - RAIL_TX_POWER_MODE_2P4GIG_MP = 1U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_MP instead. */ - RAIL_TX_POWER_MODE_2P4_MP = RAIL_TX_POWER_MODE_2P4GIG_MP, - /** - * Low-power 2.4 GHz amplifier - * EFR32xG1x: up to 0 dBm, raw values: 1-7 - * EFR32xG21: up to 0 dBm, raw values: 1-64 - * EFR32xG22: up to 0 dBm, raw values: 1-16 - * EFR32xG24: up to 0 dBm, raw values: 1-16 - * EFR32xG26: same as EFR32xG24 - * EFR32xG27: up to 0 dBm, raw values: 1-16 - * Not supported on other platforms. - */ - RAIL_TX_POWER_MODE_2P4GIG_LP = 2U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_LP instead. */ - RAIL_TX_POWER_MODE_2P4_LP = RAIL_TX_POWER_MODE_2P4GIG_LP, - /** - * Low-Low-power 2.4 GHz amplifier - * Not currently supported on any EFR32 platform. - */ - RAIL_TX_POWER_MODE_2P4GIG_LLP = 3U, - /** - * Select the highest 2.4 GHz power PA available on the current chip. - * Only supported on EFR32 Series-2 platforms and not Series-1. - */ - RAIL_TX_POWER_MODE_2P4GIG_HIGHEST = 4U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST instead. */ - RAIL_TX_POWER_MODE_2P4_HIGHEST = RAIL_TX_POWER_MODE_2P4GIG_HIGHEST, - /** - * PA for all Sub-GHz dBm values in range, using \ref - * RAIL_PaPowerSetting_t table. - * Only supported on platforms with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE (e.g. EFR32xG25). - */ - RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE = 5U, - /** - * High-power Sub-GHz amplifier (Class D mode) - * EFR32xG1x: up to 20 dBm, raw values: 0-248 - * Also supported on FR32xG23 and EFR32xG28. - * Not supported other Sub-GHz-incapable platforms or those with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. - */ - RAIL_TX_POWER_MODE_SUBGIG_HP = 6U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_SUBGIG_HP instead. */ - RAIL_TX_POWER_MODE_SUBGIG = RAIL_TX_POWER_MODE_SUBGIG_HP, - /** - * Mid-power Sub-GHz amplifier - * Supported only on EFR32xG23 and EFR32xG28. - * Not supported other Sub-GHz-incapable platforms or those with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. - */ - RAIL_TX_POWER_MODE_SUBGIG_MP = 7U, - /** - * Low-power Sub-GHz amplifier - * Supported only on EFR32xG23 and EFR32xG28. - * Not supported other Sub-GHz-incapable platforms or those with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. - */ - RAIL_TX_POWER_MODE_SUBGIG_LP = 8U, - /** - * Low-Low-power Sub-GHz amplifier - * Supported only on EFR32xG23 and EFR32xG28. - * Not supported other Sub-GHz-incapable platforms or those with \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. - */ - RAIL_TX_POWER_MODE_SUBGIG_LLP = 9U, - /** - * Select the highest Sub-GHz power PA available on the current chip. - * Only supported on EFR32 Series-2 platforms and not Series-1. - */ - RAIL_TX_POWER_MODE_SUBGIG_HIGHEST = 10U, - /** - * PA for all OFDM Sub-GHz dBm values in range, using \ref - * RAIL_PaPowerSetting_t table. - * Supported only on platforms with both \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE and \ref - * RAIL_SUPPORTS_OFDM_PA (e.g. EFR32xG25). - */ - RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE = 11U, - /** @deprecated Please use \ref RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE instead. */ - RAIL_TX_POWER_MODE_OFDM_PA = RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE, -#ifndef DOXYGEN_SHOULD_SKIP_THIS - /** - * PA for all Sub-GHz dBm values in range for Front-End-Module, using \ref - * RAIL_PaPowerSetting_t table. - * Supported only on platforms with both - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE and \ref - * RAIL_SUPPORTS_EFF. - */ - RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE = 12U, - /** - * PA for all OFDM Sub-GHz dBm values in range for Front-End-Module, using \ref - * RAIL_PaPowerSetting_t table. - * Supported only on platforms with all of \ref - * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE, \ref - * RAIL_SUPPORTS_OFDM_PA, and \ref - * RAIL_SUPPORTS_EFF. - */ - RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE = 13U, -#endif//DOXYGEN_SHOULD_SKIP_THIS - /** Invalid amplifier Selection */ - RAIL_TX_POWER_MODE_NONE // Must be last -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -// Refer to rail_chip_specific.h for per-platform defines of supported ones. -#define RAIL_TX_POWER_MODE_NONE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_NONE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_TX_POWER_MODE_NAMES - * @brief The names of the TX power modes - * - * A list of the names for the TX power modes on EFR32 parts. This - * macro is useful for test applications and debugging output. - */ -#define RAIL_TX_POWER_MODE_NAMES { \ - "RAIL_TX_POWER_MODE_2P4GIG_HP", \ - "RAIL_TX_POWER_MODE_2P4GIG_MP", \ - "RAIL_TX_POWER_MODE_2P4GIG_LP", \ - "RAIL_TX_POWER_MODE_2P4GIG_LLP", \ - "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", \ - "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE", \ - "RAIL_TX_POWER_MODE_SUBGIG_HP", \ - "RAIL_TX_POWER_MODE_SUBGIG_MP", \ - "RAIL_TX_POWER_MODE_SUBGIG_LP", \ - "RAIL_TX_POWER_MODE_SUBGIG_LLP", \ - "RAIL_TX_POWER_MODE_SUBGIG_HIGHEST", \ - "RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE", \ - "RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE", \ - "RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE", \ - "RAIL_TX_POWER_MODE_NONE" \ -} - -/** - * @struct RAIL_TxPowerConfig_t - * - * @brief A structure containing values used to initialize the power amplifiers. - */ -typedef struct RAIL_TxPowerConfig { - /** TX power mode */ - RAIL_TxPowerMode_t mode; - /** Power amplifier supply voltage in mV, generally: - * DCDC supply ~ 1800 mV (1.8 V) - * Battery supply ~ 3300 mV (3.3 V) - */ - uint16_t voltage; - /** The amount of time to spend ramping for TX in uS. */ - uint16_t rampTime; -} RAIL_TxPowerConfig_t; - -/** Convenience macro for any EFF power mode. */ -#define RAIL_POWER_MODE_IS_ANY_EFF(x) \ - (((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)) -/** Convenience macro for any OFDM mapping table mode. */ -#define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) \ - (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE)) -/** Convenience macro for any Sub-GHz mapping table mode. */ -#define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_SUBGIG(x) \ - (((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) -/** Convenience macro for any mapping table mode. */ -#define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ - (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) \ - || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)) -/** Convenience macro for any OFDM mode. */ -#define RAIL_POWER_MODE_IS_ANY_OFDM(x) \ - RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) - -/** @} */ // PA Power Amplifier (PA) - -/****************************************************************************** - * Radio Configuration Structures - *****************************************************************************/ -/** - * @addtogroup Radio_Configuration - * @{ - */ - -/** - * @brief Pointer to a radio configuration array. - * - * The radio configuration properly configures the - * radio for operation on a protocol. These configurations are very - * chip-specific should not be created or edited by hand. - */ -typedef const uint32_t *RAIL_RadioConfig_t; - -/** - * @struct RAIL_FrameType_t - * @brief Configures if there is a frame type in your frame and the lengths of - * each frame. The number of bits set in the mask determines the number of - * elements in frameLen. A maximum of 8 different frame types may be specified. - */ -typedef struct RAIL_FrameType { - /** - * A pointer to an array of frame lengths for each frame type. The length of this - * array should be equal to the number of frame types. The array that - * frameLen points to should not change location or be modified. - */ - uint16_t *frameLen; - /** - * Zero-indexed location of the byte containing the frame type field. - */ - uint8_t offset; - /** - * A bitmask of the frame type field, which determines a number of frames expected - * based on the number of bits set. No more than 3 bits can be set in the mask and - * they must be contiguous ones. For example, if the highest three bits of the byte - * specified by offset constitute the frame type, then mask should be 0xE0, - * which has 3 bits set, indicating 8 possible frame types. - */ - uint8_t mask; - /** - * A bitmask that marks if each frame is valid or should be filtered. Frame type - * 0 corresponds to the lowest bit in isValid. If the frame is filtered, a - * RAIL_EVENT_RX_PACKET_ABORTED will be raised. - */ - uint8_t isValid; - /** - * A bitmask that marks if each frame should have the address filter applied. - * Frame type 0 corresponds to the least significant bit in addressFilter. - */ - uint8_t addressFilter; -} RAIL_FrameType_t; - -/** - * @def RAIL_SETFIXEDLENGTH_INVALID - * @brief An invalid return value when calling RAIL_SetFixedLength(). - * - * An invalid return value when calling RAIL_SetFixedLength() while the radio is - * not in fixed-length mode. - */ -#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFFU) - -/** - * @struct RAIL_ChannelConfigEntryAttr_t - * @brief A channel configuration entry attribute structure. Items listed - * are designed to be altered and updated during run-time. - */ -typedef struct RAIL_ChannelConfigEntryAttr RAIL_ChannelConfigEntryAttr_t; - -/** - * @enum RAIL_ChannelConfigEntryType_t - * @brief Define if the channel support using concurrent PHY during channel - * hopping. RAIL_RX_CHANNEL_HOPPING_MODE_CONC and RAIL_RX_CHANNEL_HOPPING_MODE_VT - * can only be used if the channel supports it. - */ -RAIL_ENUM(RAIL_ChannelConfigEntryType_t) { - RAIL_CH_TYPE_NORMAL, /**< Not a concurrent PHY. */ - RAIL_CH_TYPE_CONC_BASE, /**< Base concurrent PHY. */ - RAIL_CH_TYPE_CONC_VIRTUAL, /**< Virtual concurrent PHY. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_CH_TYPE_NORMAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_NORMAL) -#define RAIL_CH_TYPE_CONC_BASE ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_BASE) -#define RAIL_CH_TYPE_CONC_VIRTUAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_VIRTUAL) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RADIO_CONFIG_ENABLE_CONC_PHY - * @brief Indicates this version of RAIL supports concurrent PHY information in - * radio configurator output. Needed for backwards compatibility. - */ -#define RADIO_CONFIG_ENABLE_CONC_PHY 1 - -/** - * @def RADIO_CONFIG_ENABLE_STACK_INFO - * @brief Indicates this version of RAIL supports stack info feature in - * radio configurator output. Needed for backwards compatibility. - */ -#define RADIO_CONFIG_ENABLE_STACK_INFO - -/** - * @struct RAIL_AlternatePhy_t - * @brief Alternate PHY configuration entry structure, which gathers some info - * on the alternate PHY in the context of concurrent mode. - */ -typedef struct RAIL_AlternatePhy { - uint32_t baseFrequency; /**< A base frequency in Hz of this channel set. */ - uint32_t channelSpacing; /**< A channel spacing in Hz of this channel set. */ - uint16_t numberOfChannels; /**< The number of channels (and not the channel number !) */ - uint16_t minIf_kHz; /**< minimum IF for the alternate PHY in kHz. */ - uint16_t minBaseIf_kHz; /**< minimum IF for the base PHY in kHz. */ - bool isOfdmModem; /**< Indicates that OFDM modem is used by this alternate PHY. */ - uint32_t rateInfo; /**< rate Info of the alternate PHY. */ -} RAIL_AlternatePhy_t; - -/** - * @struct RAIL_ChannelConfigEntry_t - * @brief A channel configuration entry structure, which defines a channel range - * and parameters across which a corresponding radio configuration is valid. - * - * operating frequency = baseFrequency - * + channelSpacing * (channel - physicalChannelOffset); - */ -typedef struct RAIL_ChannelConfigEntry { - RAIL_RadioConfig_t phyConfigDeltaAdd; /**< The minimum radio configuration to apply to the base - configuration for this channel set. */ - uint32_t baseFrequency; /**< A base frequency in Hz of this channel set. */ - uint32_t channelSpacing; /**< A channel spacing in Hz of this channel set. */ - uint16_t physicalChannelOffset; /**< The offset to subtract from the logical - channel to align them with the zero - based physical channels which are - relative to baseFrequency. - (i.e., By default ch 0 = base freq, but - if offset = 11, ch 11 = base freq.) */ - uint16_t channelNumberStart; /**< The first valid RAIL channel number for this - channel set. */ - uint16_t channelNumberEnd; /**< The last valid RAIL channel number for this - channel set. */ - RAIL_TxPower_t maxPower; /**< The maximum power allowed in this channel set. */ - RAIL_ChannelConfigEntryAttr_t *attr; /**< A pointer to a structure containing - attributes specific to this - channel set. */ - RAIL_ChannelConfigEntryType_t entryType; /**< Indicates channel config type. */ - uint8_t reserved[3]; /**< to align to 32-bit boundary. */ - const uint8_t *stackInfo; /**< Array containing information according to the protocolId value, - first byte of this array. - The first 2 fields are common to all protocols and accessible by RAIL, - others are ignored by RAIL and only used by the application. - Common fields are listed in RAIL_StackInfoCommon_t. */ - RAIL_AlternatePhy_t *alternatePhy; /**< Pointer to alternate PHY. */ -} RAIL_ChannelConfigEntry_t; - -/// @struct RAIL_ChannelConfig_t -/// @brief A channel configuration structure, which defines the channel meaning -/// when a channel number is passed into a RAIL function, e.g., RAIL_StartTx() -/// and RAIL_StartRx(). -/// -/// A RAIL_ChannelConfig_t structure defines the channel scheme that an -/// application uses when registered in RAIL_ConfigChannels(). -/// -/// These are a few examples of different channel configurations: -/// @code{.c} -/// // 21 channels starting at 2.45 GHz with channel spacing of 1 MHz -/// // ... generated by Simplicity Studio (i.e., rail_config.c) ... -/// const uint32_t generated[] = { ... }; -/// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; -/// const RAIL_ChannelConfigEntry_t generated_channels[] = { -/// { -/// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated_entryAttr -/// }, -/// }; -/// const RAIL_ChannelConfig_t generated_channelConfig = { -/// .phyConfigBase = generated, // Default radio configuration for all entries -/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration -/// .configs = generated_channels, -/// .length = 1 // There are this many channel configuration entries -/// }; -/// const RAIL_ChannelConfig_t *channelConfigs[] = { -/// &generated_channelConfig, -/// NULL -/// }; -/// // ... in main code ... -/// // Associate a specific channel configuration with a particular RAIL instance. -/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); -/// -/// // 4 nonlinear channels -/// // ... in rail_config.c ... -/// const uint32_t generated[] = { ... }; -/// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; -/// const RAIL_ChannelConfigEntry_t generated_channels[] = { -/// { -/// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry -/// .baseFrequency = 910123456, -/// .channelSpacing = 0, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 0, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated_entryAttr -/// }, -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 911654789, -/// .channelSpacing = 0, -/// .physicalChannelOffset = 0, // Since ch spacing = 0, offset can be 0 -/// .channelNumberStart = 1, -/// .channelNumberEnd = 1, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated_entryAttr -/// }, -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 912321456, -/// .channelSpacing = 100000, -/// .physicalChannelOffset = 2, // Since ch spacing != 0, offset = 2 -/// .channelNumberStart = 2, // ch 2 = baseFrequency -/// .channelNumberEnd = 2, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated_entryAttr -/// }, -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 913147852, -/// .channelSpacing = 0, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 3, -/// .channelNumberEnd = 3, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated_entryAttr -/// }, -/// }; -/// const RAIL_ChannelConfig_t generated_channelConfig = { -/// .phyConfigBase = generated, // Default radio configuration for all entries -/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration -/// .configs = generated_channels, -/// .length = 4 // There are this many channel configuration entries -/// }; -/// const RAIL_ChannelConfig_t *channelConfigs[] = { -/// &generated_channelConfig, -/// NULL -/// }; -/// // ... in main code ... -/// // Associate a specific channel configuration with a particular RAIL instance. -/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); -/// -/// // Multiple radio configurations -/// // ... in rail_config.c ... -/// const uint32_t generated0[] = { ... }; -/// RAIL_ChannelConfigEntryAttr_t generated0_entryAttr = { ... }; -/// const RAIL_ChannelConfigEntry_t generated0_channels[] = { -/// { -/// .phyConfigDeltaAdd = NULL, // Add this to the default configuration for this entry -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated0_entryAttr -/// }, -/// }; -/// const RAIL_ChannelConfig_t generated0_channelConfig = { -/// .phyConfigBase = generated0, // Default radio configuration for all entries -/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore default configuration -/// .configs = generated0_channels, -/// .length = 1 // There are this many channel configuration entries -/// }; -/// const uint32_t generated1[] = { ... }; -/// RAIL_ChannelConfigEntryAttr_t generated1_entryAttr = { ... }; -/// const RAIL_ChannelConfigEntry_t generated1_channels[] = { -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = -100, // Use this entry when TX power <= -10dBm -/// .attr = &generated1_entryAttr -/// }, -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = 15, // Use this entry when TX power > -10dBm -/// // and TX power <= 1.5dBm -/// .attr = &generated1_entryAttr -/// }, -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = RAIL_TX_POWER_MAX, // Use this entry when TX power > 1.5dBm -/// .attr = &generated1_entryAttr -/// }, -/// }; -/// const RAIL_ChannelConfig_t generated1_channelConfig = { -/// .phyConfigBase = generated1, -/// .phyConfigDeltaSubtract = NULL, -/// .configs = generated1_channels, -/// .length = 3 -/// }; -/// const uint32_t generated2[] = { ... }; -/// RAIL_ChannelConfigEntryAttr_t generated2_entryAttr = { ... }; -/// const RAIL_ChannelConfigEntry_t generated2_channels[] = { -/// { -/// .phyConfigDeltaAdd = NULL, -/// .baseFrequency = 2450000000, -/// .channelSpacing = 1000000, -/// .physicalChannelOffset = 0, -/// .channelNumberStart = 0, -/// .channelNumberEnd = 20, -/// .maxPower = RAIL_TX_POWER_MAX, -/// .attr = &generated2_entryAttr -/// }, -/// }; -/// const RAIL_ChannelConfig_t generated2_channelConfig = { -/// .phyConfigBase = generated2, -/// .phyConfigDeltaSubtract = NULL, -/// .configs = generated2_channels, -/// .length = 1 -/// }; -/// const RAIL_ChannelConfig_t *channelConfigs[] = { -/// &generated0_channelConfig, -/// &generated1_channelConfig, -/// &generated2_channelConfig, -/// NULL -/// }; -/// // ... in main code ... -/// // Create a unique RAIL handle for each unique channel configuration. -/// railHandle0 = RAIL_Init(&railCfg0, &RAILCb_RfReady0); -/// railHandle1 = RAIL_Init(&railCfg1, &RAILCb_RfReady1); -/// railHandle2 = RAIL_Init(&railCfg2, &RAILCb_RfReady2); -/// // Associate each channel configuration with its corresponding RAIL handle. -/// RAIL_ConfigChannels(railHandle0, channelConfigs[0]); -/// RAIL_ConfigChannels(railHandle1, channelConfigs[1]); -/// RAIL_ConfigChannels(railHandle2, channelConfigs[2]); -/// // Use a RAIL handle and channel to access the desired channel configuration entry. -/// RAIL_SetTxPowerDbm(railHandle1, 100); // set 10.0 dBm TX power -/// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[2] -/// RAIL_SetTxPowerDbm(railHandle1, 0); // set 0 dBm TX power -/// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[1] -/// RAIL_StartRx(railHandle2, 0, &schedInfo); // RX using generated2_channels[0] -/// @endcode - -typedef struct RAIL_ChannelConfig { - RAIL_RadioConfig_t phyConfigBase; /**< Base radio configuration for the corresponding - channel configuration entries. */ - RAIL_RadioConfig_t phyConfigDeltaSubtract; /**< Minimum radio configuration to restore - channel entries back to base - configuration. */ - const RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of - RAIL_ChannelConfigEntry_t - entries. */ - uint32_t length; /**< Number of RAIL_ChannelConfigEntry_t entries. */ - uint32_t signature; /**< Signature for this structure. Only used on modules. */ - uint32_t xtalFrequencyHz; /**< Crystal Frequency for the channel config. */ -} RAIL_ChannelConfig_t; - -/** - * @struct RAIL_ChannelMetadata_t - * @brief Container for individual channel metadata. - */ -typedef struct RAIL_ChannelMetadata { - uint16_t channel; /**< Channel number */ - uint16_t reserved; /**< Word alignment */ - uint32_t frequency; /**< Channel frequency, in Hz */ -} RAIL_ChannelMetadata_t; - -/** - * @struct RAIL_StackInfoCommon_t - * @brief StackInfo fields common to all protocols. - */ -typedef struct RAIL_StackInfoCommon { - uint8_t protocolId; /**< Same as RAIL_PtiProtocol_t */ - uint8_t phyId; /**< PHY Id depending on the protocol_id value */ -} RAIL_StackInfoCommon_t; - -/** - * @typedef RAIL_RadioConfigChangedCallback_t - * @brief A pointer to a function called whenever a radio configuration change occurs. - * - * @param[in] railHandle A handle for RAIL instance. - * @param[in] entry The radio configuration entry being changed to. - */ -typedef void (*RAIL_RadioConfigChangedCallback_t)(RAIL_Handle_t railHandle, - const RAIL_ChannelConfigEntry_t *entry); - -/** @} */ // end of group Radio_Configuration - -/****************************************************************************** - * Packet Trace Interface (PTI) Structures - *****************************************************************************/ -/** - * @addtogroup PTI - * @{ - * - * These enumerations and structures are used with RAIL PTI API. EFR32 supports - * SPI and UART PTI and is configurable in terms of baud rates and PTI - * pin locations. - */ - -/** A channel type enumeration. */ -RAIL_ENUM(RAIL_PtiMode_t) { - /** Turn PTI off entirely. */ - RAIL_PTI_MODE_DISABLED, - /** 8-bit SPI mode. */ - RAIL_PTI_MODE_SPI, - /** 8-bit UART mode. */ - RAIL_PTI_MODE_UART, - /** 9-bit UART mode. */ - RAIL_PTI_MODE_UART_ONEWIRE, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_PTI_MODE_DISABLED ((RAIL_PtiMode_t) RAIL_PTI_MODE_DISABLED) -#define RAIL_PTI_MODE_SPI ((RAIL_PtiMode_t) RAIL_PTI_MODE_SPI) -#define RAIL_PTI_MODE_UART ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART) -#define RAIL_PTI_MODE_UART_ONEWIRE ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART_ONEWIRE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_PtiConfig_t - * @brief A configuration for PTI. - */ -typedef struct RAIL_PtiConfig { - /** Packet Trace mode (UART or SPI). */ - RAIL_PtiMode_t mode; - /** Output baudrate for PTI in Hz. */ - uint32_t baud; - /** Data output (DOUT) location for doutPort/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t doutLoc; - /** Data output (DOUT) GPIO port. */ - uint8_t doutPort; - /** Data output (DOUT) GPIO pin. */ - uint8_t doutPin; - /** Data clock (DCLK) location for dclkPort/Pin. Only used in SPI mode. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t dclkLoc; - /** Data clock (DCLK) GPIO port. Only used in SPI mode. */ - uint8_t dclkPort; - /** Data clock (DCLK) GPIO pin. Only used in SPI mode. */ - uint8_t dclkPin; - /** Data frame (DFRAME) location for dframePort/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t dframeLoc; - /** Data frame (DFRAME) GPIO port. */ - uint8_t dframePort; - /** Data frame (DFRAME) GPIO pin. */ - uint8_t dframePin; -} RAIL_PtiConfig_t; - -/** - * @enum RAIL_PtiProtocol_t - * @brief The protocol that RAIL outputs via the Packet Trace Interface (PTI). - */ -RAIL_ENUM(RAIL_PtiProtocol_t) { - RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol. */ - RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol. */ - RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol. */ - RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol. */ - RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol. */ - RAIL_PTI_PROTOCOL_ZWAVE = 6, /**< PTI output for the Z-Wave protocol. */ - RAIL_PTI_PROTOCOL_WISUN = 7, /**< PTI output for the Wi-SUN protocol. */ - RAIL_PTI_PROTOCOL_802154 = 8, /**< PTI output for a custom protocol using a built-in 802.15.4 radio config. */ - RAIL_PTI_PROTOCOL_SIDEWALK = 9, /** < PTI output for Sidewalk protocol. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_PTI_PROTOCOL_CUSTOM ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CUSTOM) -#define RAIL_PTI_PROTOCOL_THREAD ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_THREAD) -#define RAIL_PTI_PROTOCOL_BLE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_BLE) -#define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT) -#define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE) -#define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE) -#define RAIL_PTI_PROTOCOL_802154 ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_802154) -#define RAIL_PTI_PROTOCOL_SIDEWALK ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_SIDEWALK) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group PTI - -/****************************************************************************** - * Data Management Structures - *****************************************************************************/ -/** - * @addtogroup Data_Management - * @{ - */ - -/// Fixed-width type indicating the needed alignment for RX and TX FIFOs. -#define RAIL_FIFO_ALIGNMENT_TYPE uint32_t - -/// Alignment that is needed for the RX and TX FIFOs. -#define RAIL_FIFO_ALIGNMENT (sizeof(RAIL_FIFO_ALIGNMENT_TYPE)) - -/** - * @enum RAIL_TxDataSource_t - * @brief Transmit data sources supported by RAIL. - */ -RAIL_ENUM(RAIL_TxDataSource_t) { - TX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ - /** Uses the multi-level frequency modulation data. - * @note This is only supported on devices where \ref RAIL_SUPPORTS_MFM - * or \ref RAIL_SupportsMfm() are true. - * @note This feature cannot be used with built-in protocols (802.15.4, BLE, - * Z-Wave). - */ - TX_MFM_DATA, - /** A count of the choices in this enumeration. */ - RAIL_TX_DATA_SOURCE_COUNT // Must be last -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define TX_PACKET_DATA ((RAIL_TxDataSource_t) TX_PACKET_DATA) -#define TX_MFM_DATA ((RAIL_TxDataSource_t) TX_MFM_DATA) -#define RAIL_TX_DATA_SOURCE_COUNT ((RAIL_TxDataSource_t) RAIL_TX_DATA_SOURCE_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_RxDataSource_t - * @brief Receive data sources supported by RAIL. - * - * @note Data sources other than \ref RX_PACKET_DATA require use of - * \ref RAIL_DataMethod_t::FIFO_MODE. - */ -RAIL_ENUM(RAIL_RxDataSource_t) { - RX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ - RX_DEMOD_DATA, /**< Gets 8-bit data output from the demodulator. */ - RX_IQDATA_FILTLSB, /**< Gets lower 16 bits of I/Q data provided to the - demodulator. */ - RX_IQDATA_FILTMSB, /**< Gets highest 16 bits of I/Q data provided to the - demodulator. */ - RX_DIRECT_MODE_DATA, /**< Gets RX direct mode data output from the demodulator. - BCRDEMOD captures bcr_dmod_rawd at the sample rate - (faster than the bit rate by the OSR), specifically - the demod_samp_rate trigger. - Only supported if - \ref RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO - is true. */ - RX_DIRECT_SYNCHRONOUS_MODE_DATA, /**< Gets synchronous RX direct mode data - output from the demodulator. - BCRDEMOD_SYNCHRONOUS captures - bcr_dmod_rxd_ext at the bit - rate (bcr_dmod_bitclk_ext trigger). - Only supported if - \ref RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO - is true. - Only efr32xg23, efr32xg25, or efr32xg28 - have this mode.*/ - /** A count of the choices in this enumeration. */ - RAIL_RX_DATA_SOURCE_COUNT // Must be last -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RX_PACKET_DATA ((RAIL_RxDataSource_t) RX_PACKET_DATA) -#define RX_DEMOD_DATA ((RAIL_RxDataSource_t) RX_DEMOD_DATA) -#define RX_IQDATA_FILTLSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTLSB) -#define RX_IQDATA_FILTMSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTMSB) -#define RX_DIRECT_MODE_DATA ((RAIL_RxDataSource_t) RX_DIRECT_MODE_DATA) -#define RX_DIRECT_SYNCHRONOUS_MODE_DATA ((RAIL_RxDataSource_t) RX_DIRECT_SYNCHRONOUS_MODE_DATA) -#define RAIL_RX_DATA_SOURCE_COUNT ((RAIL_RxDataSource_t) RAIL_RX_DATA_SOURCE_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_DataMethod_t - * @brief Methods for the application to provide and retrieve data from RAIL. - * - * For Transmit the distinction between \ref RAIL_DataMethod_t::PACKET_MODE - * and \ref RAIL_DataMethod_t::FIFO_MODE has become more cosmetic than - * functional, as the RAIL_WriteTxFifo() and RAIL_SetTxFifoThreshold() APIs - * and related \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event can be used in - * either mode. For Receive the distinction is functionally important because - * in \ref RAIL_DataMethod_t::PACKET_MODE rollback occurs automatically for - * unsuccessfully-received packets (\ref RAIL_RxPacketStatus_t ABORT statuses), - * flushing their data. In \ref RAIL_DataMethod_t::FIFO_MODE rollback is - * prevented, leaving the data from unsuccessfully-received packets in the - * receive FIFO for the application to deal with. This allows for packets - * larger than the receive FIFO size where automatic rollback would corrupt - * the receive FIFO. - */ -RAIL_ENUM(RAIL_DataMethod_t) { - PACKET_MODE, /**< Packet-based data method. */ - FIFO_MODE, /**< FIFO-based data method. */ - /** A count of the choices in this enumeration. */ - RAIL_DATA_METHOD_COUNT // Must be last -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define PACKET_MODE ((RAIL_DataMethod_t) PACKET_MODE) -#define FIFO_MODE ((RAIL_DataMethod_t) FIFO_MODE) -#define RAIL_DATA_METHOD_COUNT ((RAIL_DataMethod_t) RAIL_DATA_METHOD_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_FIFO_THRESHOLD_DISABLED - * @brief A FIFO threshold value that disables the threshold. - */ -#define RAIL_FIFO_THRESHOLD_DISABLED 0xFFFFU - -/** - * @struct RAIL_DataConfig_t - * @brief RAIL data configuration structure - * - * Select the transmit/receive data sources and the - * method the application uses to provide/retrieve data from RAIL. - */ -typedef struct { - RAIL_TxDataSource_t txSource; /**< Source of TX Data. */ - RAIL_RxDataSource_t rxSource; /**< Source of RX Data. */ - RAIL_DataMethod_t txMethod; /**< Method of providing transmit data. */ - RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data. */ -} RAIL_DataConfig_t; - -/** @} */ // end of group Data Management - -/****************************************************************************** - * State Transitions - *****************************************************************************/ -/** - * @addtogroup State_Transitions - * @{ - */ - -/** - * @typedef RAIL_TransitionTime_t - * @brief Suitable type for the supported transition time range. - * - * Refer to platform-specific \ref RAIL_MINIMUM_TRANSITION_US and - * \ref RAIL_MAXIMUM_TRANSITION_US for the valid range of this type. - */ -typedef uint32_t RAIL_TransitionTime_t; - -/** - * @def RAIL_TRANSITION_TIME_KEEP - * @brief A value to use in \ref RAIL_StateTiming_t fields when - * calling \ref RAIL_SetStateTiming() to keep that timing - * parameter at it current setting. - */ -#define RAIL_TRANSITION_TIME_KEEP ((RAIL_TransitionTime_t) -1) - -/** - * @struct RAIL_StateTiming_t - * @brief A timing configuration structure for the RAIL State Machine. - * - * Configure the timings of the radio state transitions for common situations. - * All of the listed timings are in microseconds. Transitions from an active - * radio state to idle are not configurable, and will always happen as fast - * as possible. - * No timing value can exceed platform-specific \ref RAIL_MAXIMUM_TRANSITION_US. - * Use \ref RAIL_TRANSITION_TIME_KEEP to keep an existing setting. - * - * For idleToRx, idleToTx, rxToTx, txToRx, and txToTx a value of 0 for the - * transition time means that the specified transition should happen as fast - * as possible, even if the timing cannot be as consistent. Otherwise, the - * timing value cannot be below the platform-specific \ref RAIL_MINIMUM_TRANSITION_US. - * - * For idleToTx, rxToTx, and txToTx setting a longer \ref - * RAIL_TxPowerConfig_t::rampTime may result in a larger minimum value. - * - * For rxSearchTimeout and txToRxSearchTimeout, there is no minimum value. A - * value of 0 disables the feature, functioning as an infinite timeout. - */ -typedef struct RAIL_StateTiming { - RAIL_TransitionTime_t idleToRx; /**< Transition time from IDLE to RX. */ - RAIL_TransitionTime_t txToRx; /**< Transition time from TX to RX. */ - RAIL_TransitionTime_t idleToTx; /**< Transition time from IDLE to TX. */ - RAIL_TransitionTime_t rxToTx; /**< Transition time from RX packet to TX. */ - RAIL_TransitionTime_t rxSearchTimeout; /**< Length of time the radio will search for a - packet when coming from idle or RX. */ - RAIL_TransitionTime_t txToRxSearchTimeout; /**< Length of time the radio will search for a - packet when coming from TX. */ - RAIL_TransitionTime_t txToTx; /**< Transition time from TX packet to TX. */ -} RAIL_StateTiming_t; - -/** - * @enum RAIL_RadioState_t - * @brief The state of the radio. - */ -RAIL_ENUM(RAIL_RadioState_t) { - RAIL_RF_STATE_INACTIVE = 0u, /**< Radio is inactive. */ - RAIL_RF_STATE_ACTIVE = (1u << 0), /**< Radio is either idle or, - in combination with the RX and TX states, - receiving or transmitting a frame.*/ - RAIL_RF_STATE_RX = (1u << 1), /**< Radio is in receive. */ - RAIL_RF_STATE_TX = (1u << 2), /**< Radio is in transmit. */ - RAIL_RF_STATE_IDLE = (RAIL_RF_STATE_ACTIVE), /**< Radio is idle. */ - /** Radio is actively receiving a frame. */ - RAIL_RF_STATE_RX_ACTIVE = (RAIL_RF_STATE_RX | RAIL_RF_STATE_ACTIVE), - /** Radio is actively transmitting a frame. */ - RAIL_RF_STATE_TX_ACTIVE = (RAIL_RF_STATE_TX | RAIL_RF_STATE_ACTIVE) -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RF_STATE_INACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_INACTIVE) -#define RAIL_RF_STATE_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_ACTIVE) -#define RAIL_RF_STATE_RX ((RAIL_RadioState_t) RAIL_RF_STATE_RX) -#define RAIL_RF_STATE_TX ((RAIL_RadioState_t) RAIL_RF_STATE_TX) -#define RAIL_RF_STATE_IDLE ((RAIL_RadioState_t) RAIL_RF_STATE_IDLE) -#define RAIL_RF_STATE_RX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_RX_ACTIVE) -#define RAIL_RF_STATE_TX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_TX_ACTIVE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * @enum RAIL_RadioStateEfr32_t - * @brief Detailed EFR32 Radio state machine statuses. - */ -RAIL_ENUM(RAIL_RadioStateEfr32_t) { - RAIL_RAC_STATE_OFF, /**< Radio is off. */ - RAIL_RAC_STATE_RXWARM, /**< Radio is enabling the receiver. */ - RAIL_RAC_STATE_RXSEARCH, /**< Radio is listening for incoming frames. */ - RAIL_RAC_STATE_RXFRAME, /**< Radio is receiving a frame. */ - RAIL_RAC_STATE_RXPD, /**< Radio is powering down receiver and going to - OFF state. */ - RAIL_RAC_STATE_RX2RX, /**< Radio is going back to receive mode after - receiving a frame. */ - RAIL_RAC_STATE_RXOVERFLOW, /**< Received data was lost due to full receive - buffer. */ - RAIL_RAC_STATE_RX2TX, /**< Radio is disabling receiver and enabling - transmitter. */ - RAIL_RAC_STATE_TXWARM, /**< Radio is enabling transmitter. */ - RAIL_RAC_STATE_TX, /**< Radio is transmitting data. */ - RAIL_RAC_STATE_TXPD, /**< Radio is powering down transmitter and going - to OFF state. */ - RAIL_RAC_STATE_TX2RX, /**< Radio is disabling transmitter and enabling - reception. */ - RAIL_RAC_STATE_TX2TX, /**< Radio is preparing a transmission after the - previous transmission was ended. */ - RAIL_RAC_STATE_SHUTDOWN, /**< Radio is powering down receiver and going to - OFF state. */ - RAIL_RAC_STATE_POR, /**< Radio power-on-reset state (EFR32xG22 and later) */ - RAIL_RAC_STATE_NONE /**< Invalid Radio state, must be the last entry. */ -}; -#endif//DOXYGEN_SHOULD_SKIP_THIS - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF) -#define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM) -#define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH) -#define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME) -#define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD) -#define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX) -#define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW) -#define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX) -#define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM) -#define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX) -#define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD) -#define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX) -#define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX) -#define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN) -#define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_StateTransitions_t - * @brief Used to specify radio states to transition to on success or failure. - */ -typedef struct RAIL_StateTransitions { - /** - * Indicate the state the radio should return to after a successful action. - */ - RAIL_RadioState_t success; - /** - * Indicate the state the radio should return to after an error. - */ - RAIL_RadioState_t error; -} RAIL_StateTransitions_t; - -/** - * @enum RAIL_RadioStateDetail_t - * @brief The detailed state of the radio. - * - * The three radio state bits \ref RAIL_RF_STATE_DETAIL_IDLE_STATE, \ref - * RAIL_RF_STATE_DETAIL_RX_STATE, and \ref RAIL_RF_STATE_DETAIL_TX_STATE - * comprise a set of mutually exclusive core radio states. Only one (or none) - * of these bits can be set at a time. Otherwise, the value is invalid. - * - * The precise meaning of each of these three core bits, when set, depends on - * the value of the two bits \ref RAIL_RF_STATE_DETAIL_TRANSITION and \ref - * RAIL_RF_STATE_DETAIL_ACTIVE. When \ref RAIL_RF_STATE_DETAIL_TRANSITION is - * set, the radio is transitioning into the core radio state corresponding - * to the set state bit. When it is clear, the radio is already in the core - * radio state that corresponds to the set state bit. When \ref - * RAIL_RF_STATE_DETAIL_ACTIVE is set, the radio is actively transmitting or - * receiving. When it is clear, the radio is not actively transmitting or receiving. - * This bit will always be clear when \ref RAIL_RF_STATE_DETAIL_IDLE_STATE is - * set, and will always be set when \ref RAIL_RF_STATE_DETAIL_TX_STATE is set. - * Otherwise, the value is invalid. - * - * The bit \ref RAIL_RF_STATE_DETAIL_NO_FRAMES is set if the radio is currently - * operating with frame detection disabled, and clear otherwise. The bit \ref - * RAIL_RF_STATE_DETAIL_LBT_SHIFT is set if an LBT/CSMA operation - * (e.g., performing CCA) is currently ongoing, and clear otherwise. - */ -RAIL_ENUM(RAIL_RadioStateDetail_t) { - /** Shift position of \ref RAIL_RF_STATE_DETAIL_IDLE_STATE bit */ - RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT = 0u, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_RX_STATE bit */ - RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_TX_STATE bit */ - RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_TRANSITION bit */ - RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_ACTIVE bit */ - RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_NO_FRAMES bit */ - RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT, - /** Shift position of \ref RAIL_RF_STATE_DETAIL_LBT bit */ - RAIL_RF_STATE_DETAIL_LBT_SHIFT, -}; - -/** Radio is inactive. */ -#define RAIL_RF_STATE_DETAIL_INACTIVE (0U) -/** Radio is in or headed to the idle state. */ -#define RAIL_RF_STATE_DETAIL_IDLE_STATE (1U << RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT) -/** Radio is in or headed to the receive state. */ -#define RAIL_RF_STATE_DETAIL_RX_STATE (1U << RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT) -/** Radio is in or headed to the transmit state. */ -#define RAIL_RF_STATE_DETAIL_TX_STATE (1U << RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT) -/** Radio is headed to the idle, receive, or transmit state. */ -#define RAIL_RF_STATE_DETAIL_TRANSITION (1U << RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT) -/** Radio is actively transmitting or receiving. */ -#define RAIL_RF_STATE_DETAIL_ACTIVE (1U << RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT) -/** Radio has frame detect disabled. */ -#define RAIL_RF_STATE_DETAIL_NO_FRAMES (1U << RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT) -/** LBT/CSMA operation is currently ongoing. */ -#define RAIL_RF_STATE_DETAIL_LBT (1U << RAIL_RF_STATE_DETAIL_LBT_SHIFT) -/** Mask for core radio state bits. */ -#define RAIL_RF_STATE_DETAIL_CORE_STATE_MASK (RAIL_RF_STATE_DETAIL_IDLE_STATE \ - | RAIL_RF_STATE_DETAIL_RX_STATE \ - | RAIL_RF_STATE_DETAIL_TX_STATE) - -/** - * @enum RAIL_IdleMode_t - * @brief An enumeration for the different types of supported idle modes. These - * vary how quickly and destructively they put the radio into idle. - */ -RAIL_ENUM(RAIL_IdleMode_t) { - /** - * Idle the radio by turning off receive and canceling any future scheduled - * receive or transmit operations. It does not abort a receive or - * transmit in progress. - */ - RAIL_IDLE, - /** - * Idle the radio by turning off receive and any scheduled events. It - * also aborts any receive, transmit, or scheduled events in progress. - */ - RAIL_IDLE_ABORT, - /** - * Force the radio into a shutdown mode by stopping whatever state is in - * progress. This is a more destructive shutdown than \ref RAIL_IDLE or - * \ref RAIL_IDLE_ABORT and can be useful in certain situations when directed - * by the support team or for debugging. Note that this method may corrupt - * receive and transmit buffers so it requires a more thorough cleanup - * and any held packets will be lost. - */ - RAIL_IDLE_FORCE_SHUTDOWN, - /** - * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command, however, it will also - * clear any pending RAIL events related to receive and transmit. - */ - RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IDLE ((RAIL_IdleMode_t) RAIL_IDLE) -#define RAIL_IDLE_ABORT ((RAIL_IdleMode_t) RAIL_IDLE_ABORT) -#define RAIL_IDLE_FORCE_SHUTDOWN ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN) -#define RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of group State_Transitions - -/****************************************************************************** - * TX Channel Hopping - *****************************************************************************/ -/** - * @addtogroup Tx_Channel_Hopping TX Channel Hopping - * @{ - */ - -/** - * @struct RAIL_TxChannelHoppingConfigEntry_t - * @brief Structure that represents one of the channels that is part of a - * \ref RAIL_TxChannelHoppingConfig_t sequence of channels used in - * channel hopping. - */ -typedef struct RAIL_TxChannelHoppingConfigEntry { - /** - * The channel number to be used for this entry in the channel hopping - * sequence. If this is an invalid channel for the current PHY, the - * call to \ref RAIL_SetNextTxRepeat() will fail. - */ - uint16_t channel; - /** - * Pad bytes reserved for future use and currently ignored. - */ - uint8_t reserved[2]; - /** - * Idle time in microseconds to wait before transmitting on the channel - * indicated by this entry. - */ - uint32_t delay; -} RAIL_TxChannelHoppingConfigEntry_t; - -/** - * @struct RAIL_TxChannelHoppingConfig_t - * @brief Wrapper struct that will contain the sequence of - * \ref RAIL_TxChannelHoppingConfigEntry_t that represents the channel - * sequence to use during TX Channel Hopping. - */ -typedef struct RAIL_TxChannelHoppingConfig { - /** - * Pointer to contiguous global read-write memory that will be used - * by RAIL to store channel hopping information throughout its operation. - * It need not be initialized and applications should never write - * data anywhere in this buffer. - * - * @note the size of this buffer must be at least as large as - * 3 + \ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * numberOfChannels, - * plus the sum of the sizes of the - * radioConfigDeltaAdd's of the required channels, plus the size of the - * radioConfigDeltaSubtract. In the case that one channel - * appears two or more times in your channel sequence - * (e.g., 1, 2, 3, 2), you must account for the radio configuration - * size that number of times (i.e., need to count channel 2's - * radio configuration size twice for the given example). The buffer is - * for internal use to the library. - */ - uint32_t *buffer; - /** - * This parameter must be set to the length of the buffer array, in 32 bit - * words. This way, during configuration, the software can confirm it's - * writing within the bounds of the buffer. The configuration API will return - * an error or trigger \ref RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT if - * bufferLength is insufficient. - */ - uint16_t bufferLength; - /** - * The number of channels in the channel hopping sequence, which is the - * number of elements in the array that entries points to. - */ - uint8_t numberOfChannels; - /** - * Pad byte reserved for future use and currently ignored. - */ - uint8_t reserved; - /** - * A pointer to the first element of an array of \ref - * RAIL_TxChannelHoppingConfigEntry_t that represents the channels - * used during channel hopping. The length of this array must be - * numberOfChannels. - */ - RAIL_TxChannelHoppingConfigEntry_t *entries; -} RAIL_TxChannelHoppingConfig_t; - -/// The worst-case platform-agnostic static amount of memory needed per -/// channel for channel hopping, measured in 32 bit words, regardless of -/// the size of radio configuration structures. -#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE (65U) - -/** @} */ // end of group Tx_Channel_Hopping - -/****************************************************************************** - * TX/RX Configuration Structures - *****************************************************************************/ -/** - * @addtogroup Transmit - * @{ - */ - -/** - * @enum RAIL_StopMode_t - * @brief Stop radio operation options bit mask - */ -RAIL_ENUM(RAIL_StopMode_t) { - /** Shift position of \ref RAIL_STOP_MODE_ACTIVE bit */ - RAIL_STOP_MODE_ACTIVE_SHIFT = 0, - /** Shift position of \ref RAIL_STOP_MODE_PENDING bit */ - RAIL_STOP_MODE_PENDING_SHIFT = 1 -}; - -/** Do not stop any radio operations */ -#define RAIL_STOP_MODES_NONE (0U) -/** Stop active radio operations only */ -#define RAIL_STOP_MODE_ACTIVE (1U << RAIL_STOP_MODE_ACTIVE_SHIFT) -/** Stop pending radio operations */ -#define RAIL_STOP_MODE_PENDING (1U << RAIL_STOP_MODE_PENDING_SHIFT) -/** Stop all radio operations */ -#define RAIL_STOP_MODES_ALL (0xFFU) - -/** - * @enum RAIL_TxOptions_t - * @brief Transmit options, in reality a bitmask. - */ -RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { - /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit */ - RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT = 0, - /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit */ - RAIL_TX_OPTION_REMOVE_CRC_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit */ - RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_ANTENNA0 bit */ - RAIL_TX_OPTION_ANTENNA0_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_ANTENNA1 bit */ - RAIL_TX_OPTION_ANTENNA1_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN bit */ - RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_CCA_PEAK_RSSI bit */ - RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_CCA_ONLY bit */ - RAIL_TX_OPTION_CCA_ONLY_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_RESEND bit */ - RAIL_TX_OPTION_RESEND_SHIFT, - /** Shift position of \ref RAIL_TX_OPTION_CONCURRENT_PHY_ID bit */ - RAIL_TX_OPTION_CONCURRENT_PHY_ID_SHIFT, - /** A count of the choices in this enumeration. */ - RAIL_TX_OPTIONS_COUNT // Must be last -}; - -/** A value representing no options enabled. */ -#define RAIL_TX_OPTIONS_NONE 0UL -/** All options disabled by default. This is the fastest TX option to apply. */ -#define RAIL_TX_OPTIONS_DEFAULT RAIL_TX_OPTIONS_NONE -/** - * An option to configure whether or not the TXing node will listen for an ACK. - * If this is false, the isAck flag in RAIL_RxPacketDetails_t of a received - * packet will always be false. - */ -#define RAIL_TX_OPTION_WAIT_FOR_ACK (1UL << RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT) -/** - * An option to remove CRC bytes from TX packets. To receive packets when the - * sender has this option set true, set \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS - * on the receive side. - */ -#define RAIL_TX_OPTION_REMOVE_CRC (1UL << RAIL_TX_OPTION_REMOVE_CRC_SHIFT) -/** - * An option to select which sync word is used during the transmission. - * When two sync words are configured by the PHY or \ref RAIL_ConfigSyncWords() - * enabling this option selects SYNC2 rather than SYNC1 for the upcoming transmit. - * - * This option should not be used when only one sync word has been configured. - * - * @note There are a few special radio configurations (e.g. BLE Viterbi) that do - * not support transmitting different sync words. - */ -#define RAIL_TX_OPTION_SYNC_WORD_ID (1UL << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT) -/** - * An option to select antenna 0 for transmission. If the antenna selection - * option is not set or if both antenna options are set, then the transmit - * will occur on either antenna depending on the last receive or transmit - * selection. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). - * - * @note These TX antenna options do not control the antenna used for - * \ref Auto_Ack transmissions, which always occur on the same antenna - * used to receive the packet being acknowledged. - */ -#define RAIL_TX_OPTION_ANTENNA0 (1UL << RAIL_TX_OPTION_ANTENNA0_SHIFT) -/** - * An option to select antenna 1 for transmission. If the antenna selection - * option is not set or if both antenna options are set, then the transmit - * will occur on either antenna depending on the last receive or transmit - * selection. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). - * - * @note These TX antenna options do not control the antenna used for - * \ref Auto_Ack transmissions, which always occur on the same antenna - * used to receive the packet being acknowledged. - */ -#define RAIL_TX_OPTION_ANTENNA1 (1UL << RAIL_TX_OPTION_ANTENNA1_SHIFT) -/** - * An option to use the alternate preamble length established - * by \ref RAIL_SetTxAltPreambleLength() for the transmission. - * When not set, the PHY configuration's preamble length is used. - */ -#define RAIL_TX_OPTION_ALT_PREAMBLE_LEN (1UL << RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT) -/** - * An option to use peak rather than average RSSI energy detected during - * CSMA's RAIL_CsmaConfig_t::ccaDuration or LBT's - * RAIL_LbtConfig_t::lbtDuration to determine whether the channel is clear - * or busy. This option is only valid when calling one of the CCA transmit - * routines: \ref RAIL_StartCcaCsmaTx, \ref RAIL_StartCcaLbtTx, \ref - * RAIL_StartScheduledCcaCsmaTx, or \ref RAIL_StartScheduledCcaLbtTx. - * - * @note This option does nothing on platforms like EFR32XG1 that lack - * support for capturing peak RSSI energy. - */ -#define RAIL_TX_OPTION_CCA_PEAK_RSSI (1UL << RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT) -/** - * An option to only perform the CCA (CSMA/LBT) operation but *not* - * automatically transmit if the channel is clear. This option is only valid - * when calling one of the CCA transmit routines: \ref RAIL_StartCcaCsmaTx, - * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, or \ref - * RAIL_StartScheduledCcaLbtTx. - * - * Application can then use the \ref RAIL_EVENT_TX_CHANNEL_CLEAR to - * initiate transmit manually, e.g., giving it the opportunity to adjust - * outgoing packet data before the packet goes out. - * - * @note Configured state transitions to Rx or Idle are suspended during - * this CSMA/LBT operation. If packet reception occurs, the radio will - * return to the state it was in just prior to the CSMA/LBT operation - * when that reception (including any AutoACK response) is complete. - */ -#define RAIL_TX_OPTION_CCA_ONLY (1UL << RAIL_TX_OPTION_CCA_ONLY_SHIFT) - -/** - * An option to resend packet at the beginning of the Transmit FIFO. - * - * The packet to be resent must have been previously provided by - * \ref RAIL_SetTxFifo() or \ref RAIL_WriteTxFifo() passing true for - * the latter's reset parameter. It works by setting the - * transmit FIFO's read offset to the beginning of the FIFO while - * leaving its write offset intact. For this to work, - * \ref RAIL_DataConfig_t::txMethod must be RAIL_DataMethod_t::PACKET_MODE - * (i.e., the packet can't exceed the Transmit FIFO's size), otherwise - * undefined behavior will result. - * - * This option can also be used with \ref RAIL_SetNextTxRepeat() to cause - * the repeated packet(s) to all be the same as the first. - */ -#define RAIL_TX_OPTION_RESEND (1UL << RAIL_TX_OPTION_RESEND_SHIFT) - -/** - * An option to specify which PHY is used to transmit in the case of concurrent mode. - * Concurrent mode is only allowed on EFR32xG25 for some predefined combinations of Wi-SUN PHYs. - * When set/unset, the alternate/base PHY is used to transmit. - */ -#define RAIL_TX_OPTION_CONCURRENT_PHY_ID (1UL << RAIL_TX_OPTION_CONCURRENT_PHY_ID_SHIFT) - -/** A value representing all possible options. */ -#define RAIL_TX_OPTIONS_ALL 0xFFFFFFFFUL - -/** - * @struct RAIL_TxPacketDetails_t - * @brief Detailed information requested about the packet that was just, - * or is currently being, transmitted. - */ -typedef struct RAIL_TxPacketDetails { - /** - * The timestamp of the transmitted packet in the RAIL timebase, - * filled in by RAIL_GetTxPacketDetails(). - */ - RAIL_PacketTimeStamp_t timeSent; - /** - * Indicate whether the transmitted packet was an automatic ACK. In a generic - * sense, an automatic ACK is defined as a packet sent in response to a - * received ACK-requesting frame when auto-ACK is enabled. In a protocol - * specific sense this definition may be more or less restrictive to match the - * specification and you should refer to that protocol's documentation. - */ - bool isAck; -} RAIL_TxPacketDetails_t; - -/** - * @enum RAIL_ScheduledTxDuringRx_t - * @brief Enumerates the possible outcomes of what will occur if a - * scheduled TX ends up firing during RX. Because RX and TX can't - * happen at the same time, it is up to the user how the TX should be - * handled. This enumeration is passed into RAIL_StartScheduledTx() - * as part of \ref RAIL_ScheduleTxConfig_t. - */ -RAIL_ENUM(RAIL_ScheduledTxDuringRx_t) { - /** - * The scheduled TX will be postponed until RX completes and then sent. - */ - RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX, - /** - * The scheduled TX will be aborted and a - * \ref RAIL_EVENT_TX_BLOCKED event will fire. - */ - RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX) -#define RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_ScheduleTxConfig_t - * @brief A configuration structure for a scheduled transmit. - */ -typedef struct RAIL_ScheduleTxConfig { - /** - * The time when to transmit this packet. The exact interpretation of - * this value depends on the mode specified below. - */ - RAIL_Time_t when; - /** - * The type of delay. See the \ref RAIL_TimeMode_t documentation for - * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for - * time-critical protocols. - */ - RAIL_TimeMode_t mode; - /** - * Indicate which action to take with a scheduled TX if it occurs during RX. - * See \ref RAIL_ScheduledTxDuringRx_t structure for more information on - * potential options. - */ - RAIL_ScheduledTxDuringRx_t txDuringRx; -} RAIL_ScheduleTxConfig_t; - -/** - * @def RAIL_MAX_LBT_TRIES - * @brief The maximum number of LBT/CSMA retries supported. - */ -#define RAIL_MAX_LBT_TRIES (15U) - -/** - * @def RAIL_MAX_CSMA_EXPONENT - * @brief The maximum power-of-2 exponent for CSMA backoffs. - */ -#define RAIL_MAX_CSMA_EXPONENT (8U) - -/// -/// @struct RAIL_CsmaConfig_t -/// @brief A configuration structure for the CSMA transmit algorithm. -/// -/// One of RAIL's schemes for polite spectrum access is an implementation of -/// a Carrier-Sense Multiple Access (CSMA) algorithm based on IEEE 802.15.4 -/// (unslotted). -/// \n In pseudo-code it works like this, showing relevant event notifications: -/// @code{.c} -/// // Return true to transmit packet, false to not transmit packet. -/// bool performCsma(const RAIL_CsmaConfig_t *csmaConfig) -/// { -/// bool isFixedBackoff = ((csmaConfig->csmaMinBoExp == 0) -/// && (csmaConfig->csmaMaxBoExp == 0)); -/// int backoffExp = csmaConfig->csmaMinBoExp; // Initial backoff exponent -/// int backoffMultiplier = 1; // Assume fixed backoff -/// int try; -/// -/// // Special-case tries == 0 to transmit immediately without backoff+CCA -/// if (csmaConfig->csmaTries == 0) { -/// return true; -/// } -/// -/// // Start overall timeout if specified: -/// if (csmaConfig->csmaTimeout > 0) { -/// StartAbortTimer(csmaConfig->csmaTimeout, RAIL_EVENT_TX_CHANNEL_BUSY); -/// // If timeout occurs, abort and signal the indicated event. -/// } -/// -/// for (try = 0; try < csmaConfig->csmaTries; try++) { -/// if (try > 0) { -/// signalEvent(RAIL_EVENT_TX_CCA_RETRY); -/// } -/// // Determine the backoff multipler for this try: -/// if (isFixedBackoff) { -/// // backoffMultiplier already set to 1 for fixed backoff -/// } else { -/// // Start with the backoff exponent for this try: -/// if (try > 0) { -/// backoffExp++; -/// if (backoffExp > csmaConfig->csmaMaxBoExp) { -/// backoffExp = csmaConfig->csmaMaxBoExp; -/// } -/// } -/// // Pick random multiplier between 0 and 2^backoffExp - 1 inclusive: -/// backoffMultiplier = pickRandomInteger(0, (1 << backoffExp) - 1); -/// } -/// // Perform the backoff: -/// delayMicroseconds(backoffMultiplier * csmaConfig->ccaBackoff); -/// // Perform the Clear-Channel Assessment (CCA): -/// // Channel is considered busy if radio is actively receiving or -/// // transmitting, or the average energy detected across duration -/// // is above the threshold. -/// signalEvent(RAIL_EVENT_TX_START_CCA); -/// if (performCca(csmaConfig->ccaDuration, csmaConfig->ccaThreshold)) { -/// // CCA (and CSMA) success: Transmit after RX-to-TX turnaround -/// StopAbortTimer(); -/// signalEvent(RAIL_EVENT_TX_CHANNEL_CLEAR); -/// return true; -/// } else { -/// // CCA failed: loop to try again, or exit if out of tries -/// } -/// } -/// // Overall CSMA failure: Don't transmit -/// StopAbortTimer(); -/// signalEvent(RAIL_EVENT_TX_CHANNEL_BUSY); -/// return false; -/// } -/// @endcode -/// -typedef struct RAIL_CsmaConfig { - /** - * The minimum (starting) exponent for CSMA random backoff (2^exp - 1). - * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT. - * - * @warning On EFR32, due to a hardware limitation, this can only be 0 - * if \ref csmaMaxBoExp is also 0 specifying a non-random fixed backoff. - * \ref RAIL_STATUS_INVALID_PARAMETER will result otherwise. - * If you really want CSMA's first iteration to have no backoff prior to - * CCA, with subsequent iterations having random backoff as the exponent - * is increased, you must do a fixed backoff of 0 operation first - * (\ref csmaMinBoExp = 0, \ref csmaMaxBoExp = 0, \ref ccaBackoff = 0, - * \ref csmaTries = 1), and if that fails (\ref RAIL_EVENT_TX_CHANNEL_BUSY), - * follow up with a random backoff operation starting at \ref csmaMinBoExp - * = 1 for the remaining iterations. - */ - uint8_t csmaMinBoExp; - /** - * The maximum exponent for CSMA random backoff (2^exp - 1). - * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT and must be greater - * than or equal to \ref csmaMinBoExp. - * \n If both exponents are 0, a non-random fixed backoff of \ref ccaBackoff - * duration results. - */ - uint8_t csmaMaxBoExp; - /** - * The number of backoff-then-CCA iterations that can fail before reporting - * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref - * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always - * transmits immediately without performing CSMA, similar to calling - * RAIL_StartTx(). - */ - uint8_t csmaTries; - /** - * The CCA RSSI threshold, in dBm, above which the channel is - * considered 'busy'. - */ - int8_t ccaThreshold; - /** - * The backoff unit period in RAIL's microsecond time base. It is - * multiplied by the random backoff exponential controlled by \ref - * csmaMinBoExp and \ref csmaMaxBoExp to determine the overall backoff - * period. For random backoffs, any value above 511 microseconds will - * be truncated. For fixed backoffs it can go up to 65535 microseconds. - */ - uint16_t ccaBackoff; - /** - * The minimum desired CCA check duration in microseconds. The RSSI is - * averaged over this duration by default but can be set to use the peak RSSI, - * on supported platforms, using the \ref RAIL_TX_OPTION_CCA_PEAK_RSSI option. - * - * @note Depending on the radio configuration, due to hardware constraints, - * the actual duration may be longer. Also, if the requested duration - * is too large for the radio to accommodate, RAIL_StartCcaCsmaTx() - * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. - */ - uint16_t ccaDuration; - /** - * An overall timeout, in RAIL's microsecond time base, for the operation. - * If the transmission doesn't start before this timeout expires, the - * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. - * A value 0 means no timeout is imposed. - */ - RAIL_Time_t csmaTimeout; -} RAIL_CsmaConfig_t; - -/** - * @def RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA - * @brief RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003 - * on 2.4 GHz OSPSK, commonly used by ZigBee. - */ -#define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \ - /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \ - /* csmaMinBoExp */ 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \ - /* csmaMaxBoExp */ 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \ - /* csmaTries */ 5, /* 5 tries overall (4 re-tries) */ \ - /* ccaThreshold */ -75, /* 10 dB above sensitivity */ \ - /* ccaBackoff */ 320, /* 20 symbols at 16 us/symbol */ \ - /* ccaDuration */ 128, /* 8 symbols at 16 us/symbol */ \ - /* csmaTimeout */ 0, /* No timeout */ \ -} - -/** - * @def RAIL_CSMA_CONFIG_SINGLE_CCA - * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX. - * It can be used to as a basis for implementing other channel access schemes - * with custom backoff delays. Users can override ccaBackoff with a fixed - * delay on each use. - */ -#define RAIL_CSMA_CONFIG_SINGLE_CCA { \ - /* Perform a single CCA after 'fixed' delay */ \ - /* csmaMinBoExp */ 0, /* Used for fixed backoff */ \ - /* csmaMaxBoExp */ 0, /* Used for fixed backoff */ \ - /* csmaTries */ 1, /* Single try */ \ - /* ccaThreshold */ -75, /* Override if not desired choice */ \ - /* ccaBackoff */ 0, /* No backoff (override with fixed value) */ \ - /* ccaDuration */ 128, /* Override if not desired length */ \ - /* csmaTimeout */ 0, /* no timeout */ \ -} - -/// -/// @struct RAIL_LbtConfig_t -/// @brief A configuration structure for the LBT transmit algorithm. -/// -/// One of RAIL's schemes for polite spectrum access is an implementation of -/// a Listen-Before-Talk (LBT) algorithm, loosely based on ETSI 300 220-1. -/// \n Currently, however, it is constrained by the EFR32's CSMA-oriented hardware -/// so is turned into an equivalent \ref RAIL_CsmaConfig_t configuration and -/// passed to the CSMA engine: -/// @code{.c} -/// if (lbtMaxBoRand == lbtMinBoRand) { -/// // Fixed backoff -/// csmaMinBoExp = csmaMaxBoExp = 0; -/// if (lbtMinBoRand == 0) { -/// ccaBackoff = lbtBackoff; -/// } else { -/// ccaBackoff = lbtMinBoRand * lbtBackoff; -/// } -/// ccaDuration = lbtDuration; -/// } else { -/// // Random backoff: map to random range 0 .. (lbtMaxBoRand - lbtMinBoRand) -/// csmaMinBoExp = csmaMaxBoExp = ceiling(log2(lbtMaxBoRand - lbtMinBoRand)); -/// ccaBackoff = round((lbtBackoff * (lbtMaxBoRand - lbtMinBoRand)) -/// / (1 << csmaMinBoExp)); -/// ccaDuration = lbtDuration + (lbtMinBoRand * lbtBackoff); -/// } -/// csmaTries = lbtTries; -/// ccaThreshold = lbtThreshold; -/// csmaTimeout = lbtTimeout; -/// @endcode -/// -typedef struct RAIL_LbtConfig { - /** - * The minimum backoff random multiplier. - */ - uint8_t lbtMinBoRand; - /** - * The maximum backoff random multiplier. - * It must be greater than or equal to \ref lbtMinBoRand. - * \n If both backoff multipliers are identical, a non-random fixed backoff - * of \ref lbtBackoff times the multiplier (minimum 1) duration results. - */ - uint8_t lbtMaxBoRand; - /** - * The number of LBT iterations that can fail before reporting - * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref - * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always - * transmits immediately without performing LBT, similar to calling - * RAIL_StartTx(). - */ - uint8_t lbtTries; - /** - * The LBT RSSI threshold, in dBm, above which the channel is - * considered 'busy'. - */ - int8_t lbtThreshold; - /** - * The backoff unit period, in RAIL's microsecond time base. It is - * multiplied by the random backoff multiplier controlled by \ref - * lbtMinBoRand and \ref lbtMaxBoRand to determine the overall backoff - * period. For random backoffs, any value above 511 microseconds will - * be truncated. For fixed backoffs, it can go up to 65535 microseconds. - */ - uint16_t lbtBackoff; - /** - * The minimum desired LBT check duration in microseconds. - * - * @note Depending on the radio configuration, due to hardware constraints, - * the actual duration may be longer. Also, if the requested duration - * is too large for the radio to accommodate, RAIL_StartCcaLbtTx() - * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. - */ - uint16_t lbtDuration; - /** - * An overall timeout, in RAIL's microsecond time base, for the operation. - * If the transmission doesn't start before this timeout expires, the - * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. - * This is important for limiting LBT due to LBT's unbounded requirement - * that if the channel is busy, the next try must wait for the channel to - * clear. A value 0 means no timeout is imposed. - */ - RAIL_Time_t lbtTimeout; -} RAIL_LbtConfig_t; - -/** - * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 - * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 - * V2.4.1 for a typical Sub-GHz band. To be practical, users should override - * lbtTries and/or lbtTimeout so channel access failure will be reported in a - * reasonable time frame rather than the unbounded time frame ETSI defined. - */ -#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 { \ - /* LBT per ETSI 300 220-1 V2.4.1 */ \ - /* LBT time = random backoff of 0-5 ms in .5 ms increments plus 5 ms fixed */ \ - /* lbtMinBoRand */ 0, /* */ \ - /* lbtMaxBoRand */ 10, /* */ \ - /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \ - /* lbtThreshold */ -87, /* */ \ - /* lbtBackoff */ 500, /* 0.5 ms */ \ - /* lbtDuration */ 5000, /* 5 ms */ \ - /* lbtTimeout */ 0, /* No timeout (recommend user override) */ \ -} - -/** - * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V3_1_0 - * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 - * V3.1.0 for a typical Sub-GHz band. To be practical, users should override - * lbtTries and/or lbtTimeout so channel access failure will be reported in a - * reasonable time frame rather than the unbounded time frame ETSI defined. - */ -#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V3_1_0 { \ - /* LBT per ETSI 300 220-1 V3.1.0 */ \ - /* LBT time = random backoff of 160-4960 us in 160 us increments */ \ - /* lbtMinBoRand */ 1, /* */ \ - /* lbtMaxBoRand */ 31, /* app-chosen; 31*lbtBackoff = 4960 us */ \ - /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \ - /* lbtThreshold */ -85, /* 15 dB above Rx sensitivity per Table 45 */ \ - /* lbtBackoff */ 160, /* 160 us per Table 48 Minimum CCA interval */ \ - /* lbtDuration */ 160, /* 160 us per Table 48 Minimum deferral period */ \ - /* lbtTimeout */ 0, /* No timeout (recommend user override) */ \ -} - -/** - * @struct RAIL_SyncWordConfig_t - * @brief RAIL sync words and length configuration. - * - */ -typedef struct RAIL_SyncWordConfig { - /** Sync word length in bits, between 2 and 32, inclusive.*/ - uint8_t syncWordBits; - /** - * Sync Word1 - * @note Only @ref syncWordBits number of LS bits are used, which are sent or received on air LSB first. - */ - uint32_t syncWord1; - /** - * Sync Word2 - * @note Only @ref syncWordBits number of LS bits are used, which are sent or received on air LSB first. - */ - uint32_t syncWord2; -} RAIL_SyncWordConfig_t; - -/** - * @enum RAIL_TxRepeatOptions_t - * @brief Transmit repeat options, in reality a bitmask. - */ -RAIL_ENUM_GENERIC(RAIL_TxRepeatOptions_t, uint16_t) { - /** Shift position of \ref RAIL_TX_REPEAT_OPTION_HOP bit */ - RAIL_TX_REPEAT_OPTION_HOP_SHIFT = 0, - /** Shift position of the \ref RAIL_TX_REPEAT_OPTION_START_TO_START bit */ - RAIL_TX_REPEAT_OPTION_START_TO_START_SHIFT = 1, -}; - -/** A value representing no repeat options enabled. */ -#define RAIL_TX_REPEAT_OPTIONS_NONE 0U -/** All repeat options disabled by default. */ -#define RAIL_TX_REPEAT_OPTIONS_DEFAULT RAIL_TX_REPEAT_OPTIONS_NONE -/** - * An option to configure whether or not to channel-hop before each - * repeated transmit. - */ -#define RAIL_TX_REPEAT_OPTION_HOP (1U << RAIL_TX_REPEAT_OPTION_HOP_SHIFT) - -/** - * An option to configure the delay between transmissions to be from start to start - * instead of end to start. Delay must be long enough to cover the prior transmit's time. - */ -#define RAIL_TX_REPEAT_OPTION_START_TO_START (1 << RAIL_TX_REPEAT_OPTION_START_TO_START_SHIFT) - -/// @struct RAIL_TxRepeatConfig_t -/// @brief A configuration structure for repeated transmits -/// -/// @note The PA will always be ramped down and up in between transmits so -/// there will always be some minimum delay between transmits depending on the -/// ramp time configuration. -typedef struct RAIL_TxRepeatConfig { - /** - * The number of repeated transmits to run. A total of (iterations + 1) - * transmits will go on-air in the absence of errors. - */ - uint16_t iterations; - /** - * Repeat option(s) to apply. - */ - RAIL_TxRepeatOptions_t repeatOptions; - /** - * Per-repeat delay or hopping configuration, depending on repeatOptions. - */ - union { - /** - * When \ref RAIL_TX_REPEAT_OPTION_HOP is not set, specifies - * the delay time between each repeated transmit. Specify \ref - * RAIL_TRANSITION_TIME_KEEP to use the current \ref - * RAIL_StateTiming_t::txToTx transition time setting. - * When using \ref RAIL_TX_REPEAT_OPTION_START_TO_START the delay - * must be long enough to cover the prior transmit's time. - */ - RAIL_TransitionTime_t delay; - /** - * When \ref RAIL_TX_REPEAT_OPTION_HOP is set, this specifies - * the channel hopping configuration to use when hopping between - * repeated transmits. Per-hop delays are configured within each - * \ref RAIL_TxChannelHoppingConfigEntry_t::delay rather than - * this union's delay field. - * When using \ref RAIL_TX_REPEAT_OPTION_START_TO_START the hop delay - * must be long enough to cover the prior transmit's time. - */ - RAIL_TxChannelHoppingConfig_t channelHopping; - } delayOrHop; -} RAIL_TxRepeatConfig_t; - -/// RAIL_TxRepeatConfig_t::iterations initializer configuring infinite -/// repeated transmissions. -#define RAIL_TX_REPEAT_INFINITE_ITERATIONS (0xFFFFU) - -/** @} */ // end of group Transmit - -/****************************************************************************** - * Receive Structures - *****************************************************************************/ -/** - * @addtogroup Receive - * @{ - */ - -/** - * @addtogroup Address_Filtering - * @{ - */ - -/// A default address filtering match table for configurations that use only one -/// address field. The truth table for address matching is shown below. -/// -/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | -/// |----------------|----------|-----------|-----------|-----------|-----------| -/// | __No Match__ | 0 | 1 | 1 | 1 | 1 | -/// | __Address 0__ | 1 | 1 | 1 | 1 | 1 | -/// | __Address 1__ | 1 | 1 | 1 | 1 | 1 | -/// | __Address 2__ | 1 | 1 | 1 | 1 | 1 | -/// | __Address 3__ | 1 | 1 | 1 | 1 | 1 | -/// -#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1FFFFFE) -/// A default address filtering match table for configurations that use two -/// address fields and want to match the same index in each. The truth -/// table for address matching is shown below. -/// -/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | -/// |----------------|----------|-----------|-----------|-----------|-----------| -/// | __No Match__ | 0 | 0 | 0 | 0 | 0 | -/// | __Address 0__ | 0 | 1 | 0 | 0 | 0 | -/// | __Address 1__ | 0 | 0 | 1 | 0 | 0 | -/// | __Address 2__ | 0 | 0 | 0 | 1 | 0 | -/// | __Address 3__ | 0 | 0 | 0 | 0 | 1 | -#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040) - -/// The maximum number of address fields that can be used by the address -/// filtering logic. -#define ADDRCONFIG_MAX_ADDRESS_FIELDS (2) - -/** - * @struct RAIL_AddrConfig_t - * @brief A structure to configure the address filtering functionality in RAIL. - */ -typedef struct RAIL_AddrConfig { - /** - * A list of the start offsets for each field. - * - * These offsets are specified relative to the previous field's end. - * For the first field, it is relative to either the beginning of the packet - * or the end of the frame type byte if frame type decoding is enabled. If a - * field is unused, it's offset should be set to 0. - */ - uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS]; - - /** - * A list of the address field sizes. - * - * These sizes are specified in bytes from 0 to 8. If you choose a - * size of 0, this field is effectively disabled. - */ - uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS]; - - /** - * The truth table to determine how the two fields combine to create a match. - * - * For detailed information about how this truth table is formed, see the - * detailed description of \ref Address_Filtering. - * - * For simple predefined configurations use the following defines. - * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD - * - For filtering that only uses a single address field. - * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you - * - For filtering that uses two address fields in a configurations where - * you want the following logic `((Field0, Index0) && (Field1, Index0)) - * || ((Field0, Index1) && (Field1, Index1)) || ...` - */ - uint32_t matchTable; -} RAIL_AddrConfig_t; - -/** - * @brief A bitmask representation of which 4 filters passed for each - * \ref ADDRCONFIG_MAX_ADDRESS_FIELDS when filtering has completed - * successfully. - * - * It's layout is: - * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | - * |--------+--------+--------+--------+--------+--------+--------+--------| - * | Second Address Field Nibble | First Address Field Nibble | - * | Addr 3 | Addr 2 | Addr 1 | Addr 0 | Addr 3 | Addr 2 | Addr 1 | Addr 0 | - * | match | match | match | match | match | match | match | match | - * |--------+--------+--------+--------+--------+--------+--------+--------| - * - * @note This information is valid in \ref RAIL_IEEE802154_Address_t on all - * platforms, but is only valid in \ref RAIL_RxPacketInfo_t on platforms - * where \ref RAIL_SUPPORTS_ADDR_FILTER_MASK is true. - */ -typedef uint8_t RAIL_AddrFilterMask_t; - -/** @} */ // end of group Address_Filtering - -/** - * @enum RAIL_RxOptions_t - * @brief Receive options, in reality a bitmask. - */ -RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { - /** Shift position of \ref RAIL_RX_OPTION_STORE_CRC bit. */ - RAIL_RX_OPTION_STORE_CRC_SHIFT = 0, - /** Shift position of \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS bit. */ - RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_ENABLE_DUALSYNC bit. */ - RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_TRACK_ABORTED_FRAMES bit. */ - RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO bit. */ - RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_ANTENNA0 bit. */ - RAIL_RX_OPTION_ANTENNA0_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_ANTENNA1 bit. */ - RAIL_RX_OPTION_ANTENNA1_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_DISABLE_FRAME_DETECTION bit. */ - RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT, - #ifndef DOXYGEN_SHOULD_SKIP_THIS - /** Shift position of \ref RAIL_RX_OPTION_SKIP_DC_CAL bit. */ - RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_SKIP_SYNTH_CAL bit. */ - RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT, - #endif //DOXYGEN_SHOULD_SKIP_THIS - /** Shift position of \ref RAIL_RX_OPTION_CHANNEL_SWITCHING bit. */ - RAIL_RX_OPTION_CHANNEL_SWITCHING_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_FAST_RX2RX bit. */ - RAIL_RX_OPTION_FAST_RX2RX_SHIFT, - /** Shift position of \ref RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION bit. */ - RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION_SHIFT, -}; - -/** A value representing no options enabled. */ -#define RAIL_RX_OPTIONS_NONE 0 -/** All options are disabled by default. */ -#define RAIL_RX_OPTIONS_DEFAULT RAIL_RX_OPTIONS_NONE - -/** - * An option to configure whether the CRC portion of the packet is included in - * the packet payload exposed to the app on packet reception. - * Defaults to false. - */ -#define RAIL_RX_OPTION_STORE_CRC (1UL << RAIL_RX_OPTION_STORE_CRC_SHIFT) -/** - * An option to configure whether CRC errors will be ignored. - * If this is set, RX will still be successful, even if - * the CRC does not pass the check. Defaults to false. - * - * @note An expected ACK that fails CRC with this option set - * will still be considered the expected ACK, terminating - * the RAIL_AutoAckConfig_t::ackTimeout period. - */ -#define RAIL_RX_OPTION_IGNORE_CRC_ERRORS (1UL << RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT) - -/** - * An option to control which sync words will be accepted. Setting it to - * 0 (default) will cause the receiver to listen for SYNC1 only. Setting it to - * 1 causes the receiver to listen for either SYNC1 or SYNC2. RX appended info - * will contain which sync word was detected. Note, this only affects which - * sync word(s) are received, but not what each of the sync words actually are. - * This feature may not be available on some combinations of chips, PHYs, and - * protocols. Use the compile time symbol RAIL_SUPPORTS_DUAL_SYNC_WORDS or - * the runtime call RAIL_SupportsDualSyncWords() to check whether the - * platform supports this feature. Also, DUALSYNC may be incompatible - * with certain radio configurations. In these cases, setting this bit will - * be ignored. See the data sheet or support team for more details. - */ -#define RAIL_RX_OPTION_ENABLE_DUALSYNC (1UL << RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT) - -/** - * An option to configure whether frames which are aborted during reception - * should continue to be tracked. Setting this option allows viewing Packet - * Trace information for frames which get discarded. Defaults to false. - * - * This option is ignored when doing a \ref RAIL_IDLE_FORCE_SHUTDOWN or - * \ref RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS. - * - * @note This option should not be used with coded PHYs since packet data - * received after the abort will not be decoded properly. - */ -#define RAIL_RX_OPTION_TRACK_ABORTED_FRAMES (1UL << RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT) - -/** - * An option to suppress capturing the appended information after - * received frames. Defaults to false. When suppressed, certain - * \ref RAIL_RxPacketDetails_t details will not be available for received - * packets whose \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ - * set. - * - * @warning This option should be changed only when the radio is idle - * and the receive FIFO is empty or has been reset, - * otherwise \ref RAIL_GetRxPacketInfo() and \ref RAIL_GetRxPacketDetails() - * may think appended info is packet data or vice-versa. - */ -#define RAIL_RX_OPTION_REMOVE_APPENDED_INFO (1UL << RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT) - -/** - * An option to select the use of antenna 0 during receive (including - * \ref Auto_Ack receive). If no antenna option is selected, the packet - * will be received on the last antenna used for receive or transmit. - * Defaults to false. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). - */ -#define RAIL_RX_OPTION_ANTENNA0 (1UL << RAIL_RX_OPTION_ANTENNA0_SHIFT) - -/** - * An option to select the use of antenna 1 during receive (including - * \ref Auto_Ack receive). If no antenna option is selected, the packet - * will be received on the last antenna used for receive or transmit. - * Defaults to false. This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). - */ -#define RAIL_RX_OPTION_ANTENNA1 (1UL << RAIL_RX_OPTION_ANTENNA1_SHIFT) - -/** - * An option combination to automatically choose an antenna during receive - * (including \ref Auto_Ack receive). If both antenna 0 and antenna 1 - * options are set, the radio will dynamically switch between antennas - * during packet detection and choose the best one for completing the - * reception. This option is only valid when the antenna diversity - * field is properly configured via Simplicity Studio. - * This option is only valid on platforms that support - * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). - */ -#define RAIL_RX_OPTION_ANTENNA_AUTO (RAIL_RX_OPTION_ANTENNA0 | RAIL_RX_OPTION_ANTENNA1) - -/** - * An option to disable frame detection. This can be useful for doing energy - * detection without risking packet reception. Enabling this will abort any - * frame currently being received in addition to preventing further frames - * from being received. Defaults to false. - */ -#define RAIL_RX_OPTION_DISABLE_FRAME_DETECTION (1UL << RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT) - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * An option to skip DC calibration when transitioning from RX to RX. This can be - * useful for reducing the state transition time, but risks impacting - * receive capability. Enabling this bypasses DC calibration (like - * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL) - * Defaults to false. - */ -#define RAIL_RX_OPTION_SKIP_DC_CAL (1UL << RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT) - -/** - * An option to skip synth calibration when transitioning from RX to RX. This can - * be useful for reducing the state transition time, but risks impacting receive - * capability. Enabling this bypasses synth calibration (like - * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL) - * Defaults to false. - */ -#define RAIL_RX_OPTION_SKIP_SYNTH_CAL (1U << RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * An option to enable IEEE 802.15.4 RX channel switching. - * See \ref RAIL_IEEE802154_ConfigRxChannelSwitching() for more information. - * Defaults to false. - * - * @note This option is only supported on specific chips where - * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is true. - * - * @note This option overrides \ref RAIL_RX_OPTION_ANTENNA0, - * \ref RAIL_RX_OPTION_ANTENNA1 and \ref RAIL_RX_OPTION_ANTENNA_AUTO antenna - * selection options. - */ -#define RAIL_RX_OPTION_CHANNEL_SWITCHING (1U << RAIL_RX_OPTION_CHANNEL_SWITCHING_SHIFT) - -/** - * An option to enable fast RX2RX state transition. - * - * Once enabled, the sequencer will send the radio to RXSEARCH and get ready to - * receive the next packet while still processing the previous one. This will - * reduce RX to RX state transition time but risks impacting receive capability. - * - * @note This option is only supported on specific chips where - * \ref RAIL_SUPPORTS_FAST_RX2RX is true. - */ -#define RAIL_RX_OPTION_FAST_RX2RX (1U << RAIL_RX_OPTION_FAST_RX2RX_SHIFT) - -/** - * An option to enable collision detection. - * - * Once enabled, when a collision with a strong enough packet is detected, the demod - * will stop the current packet decoding and try to detect the preamble of the incoming - * packet. - * - * @note This option is only supported on specific chips where - * \ref RAIL_SUPPORTS_COLLISION_DETECTION is true. - */ -#define RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION (1U << RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION_SHIFT) - -/** A value representing all possible options. */ -#define RAIL_RX_OPTIONS_ALL 0xFFFFFFFFUL - -/** The value returned by RAIL for an invalid RSSI, in dBm. */ -#define RAIL_RSSI_INVALID_DBM (-128) -/** The value returned by RAIL for an invalid RSSI: in quarter dBm. */ -#define RAIL_RSSI_INVALID ((int16_t)(RAIL_RSSI_INVALID_DBM * 4)) -/** The lowest RSSI value returned by RAIL: in quarter dBm. */ -#define RAIL_RSSI_LOWEST ((int16_t)(RAIL_RSSI_INVALID + 1)) - -/** Maximum absolute value for RSSI offset */ -#define RAIL_RSSI_OFFSET_MAX 35 - -/** A sentinel value to indicate waiting for a valid RSSI without a timeout. */ -#define RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT ((RAIL_Time_t)0xFFFFFFFFU) -/** A sentinel value to indicate no waiting for a valid RSSI. */ -#define RAIL_GET_RSSI_NO_WAIT ((RAIL_Time_t)0U) - -/** - * @struct RAIL_ScheduleRxConfig_t - * @brief Configures the scheduled RX algorithm. - * - * Defines the start and end times of the receive window created - * for a scheduled receive. If either start or end times are disabled, they - * will be ignored. - */ -typedef struct RAIL_ScheduleRxConfig { - /** - * The time to start receive. See startMode for more information about the - * types of start times that you can specify. - */ - RAIL_Time_t start; - /** - * How to interpret the time value specified in the start parameter. See the - * \ref RAIL_TimeMode_t documentation for more information. Use - * \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times - * relative to the current time and \ref RAIL_TIME_DISABLED to ignore the - * start time. - */ - RAIL_TimeMode_t startMode; - /** - * The time to end receive. See endMode for more information about the types - * of end times you can specify. - */ - RAIL_Time_t end; - /** - * How to interpret the time value specified in the end parameter. See the - * \ref RAIL_TimeMode_t documentation for more information. Note that, in - * this API, if you specify a \ref RAIL_TIME_DELAY, it is relative to the - * start time if given and relative to now if none is specified. Also, using - * \ref RAIL_TIME_DISABLED means that this window will not end unless you - * explicitly call \ref RAIL_Idle() or add an end event through a future - * update to this configuration. - */ - RAIL_TimeMode_t endMode; - /** - * While in scheduled RX, you can still control the radio state via - * state transitions. This option configures whether a transition - * to RX goes back to scheduled RX or to the normal RX state. Once in the - * normal RX state, you will effectively end the scheduled RX window and can - * continue to receive indefinitely depending on the state transitions. Set - * to 1 to transition to normal RX and 0 to stay in the scheduled RX. - * - * This setting also influences the posting of - * \ref RAIL_EVENT_RX_SCHEDULED_RX_END when the scheduled Rx window is - * implicitly ended by a packet receive (any of the - * \ref RAIL_EVENTS_RX_COMPLETION events). See that event for details. - * - * @note An Rx transition to Idle state will always terminate the - * scheduled Rx window, regardless of this setting. This can be used - * to ensure Scheduled RX terminates on the first packet received - * (or first successful packet if the RX error transition is to Rx - * while the Rx success transition is to Idle). - */ - uint8_t rxTransitionEndSchedule; - /** - * This setting tells RAIL what to do with a packet being received - * when the window end event occurs. If set to 0, such a packet - * will be allowed to complete. Any other setting will cause that - * packet to be aborted. In either situation, any posting of - * \ref RAIL_EVENT_RX_SCHEDULED_RX_END is deferred briefly to when - * the packet's corresponding \ref RAIL_EVENTS_RX_COMPLETION occurs. - */ - uint8_t hardWindowEnd; -} RAIL_ScheduleRxConfig_t; - -/** - * @enum RAIL_RxPacketStatus_t - * @brief The packet status code associated with a packet received or - * currently being received. - * - * @note RECEIVING implies some packet data may be available, but - * is untrustworthy (not CRC-verified) and might disappear if the packet - * is rolled back on error. No packet details are yet available. - * @note In RX \ref RAIL_DataMethod_t::FIFO_MODE, ABORT statuses imply some - * packet data may be available, but it's incomplete and not trustworthy. - */ -RAIL_ENUM(RAIL_RxPacketStatus_t) { - /** - * The radio is idle or searching for a packet. - */ - RAIL_RX_PACKET_NONE = 0, - /** - * The packet was aborted during filtering because of illegal frame length, - * CRC or block decoding errors, other RAIL built-in protocol-specific - * packet content errors, or by the application or multiprotocol scheduler - * idling the radio with \ref RAIL_IDLE_ABORT or higher. - * - * Corresponding \ref RAIL_EVENT_RX_PACKET_ABORTED is triggered. - */ - RAIL_RX_PACKET_ABORT_FORMAT, - /** - * The packet failed address filtering. - * - * Corresponding \ref RAIL_EVENT_RX_ADDRESS_FILTERED is triggered. - */ - RAIL_RX_PACKET_ABORT_FILTERED, - /** - * The packet passed any filtering but was aborted by the application - * or multiprotocol scheduler idling the radio with \ref RAIL_IDLE_ABORT - * or higher. - * - * Corresponding \ref RAIL_EVENT_RX_PACKET_ABORTED is triggered. - */ - RAIL_RX_PACKET_ABORT_ABORTED, - /** - * The packet overflowed the receive buffer. - * - * Corresponding \ref RAIL_EVENT_RX_FIFO_OVERFLOW is triggered. - */ - RAIL_RX_PACKET_ABORT_OVERFLOW, - /** - * The packet passed any filtering but subsequently failed CRC check(s) - * block decoding, or illegal frame length, and was aborted. - * - * Corresponding \ref RAIL_EVENT_RX_FRAME_ERROR is triggered. - */ - RAIL_RX_PACKET_ABORT_CRC_ERROR, - /** - * The packet passed any filtering but subsequently failed CRC check(s) - * with \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS in effect. Can also occur - * when the packet prematurely ended successfully during filtering, - * and either the \ref RAIL_EVENT_RX_PACKET_ABORTED or - * \ref RAIL_EVENT_RX_ADDRESS_FILTERED events had been enabled - * requesting notification of such packets. - * - * Corresponding \ref RAIL_EVENT_RX_PACKET_RECEIVED is triggered. - */ - RAIL_RX_PACKET_READY_CRC_ERROR, - /** - * The packet was successfully received, passing CRC check(s). - * - * Corresponding \ref RAIL_EVENT_RX_PACKET_RECEIVED is triggered. - */ - RAIL_RX_PACKET_READY_SUCCESS, - /** - * A packet is being received and is not yet complete. - */ - RAIL_RX_PACKET_RECEIVING, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RX_PACKET_NONE ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_NONE) -#define RAIL_RX_PACKET_ABORT_FORMAT ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FORMAT) -#define RAIL_RX_PACKET_ABORT_FILTERED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FILTERED) -#define RAIL_RX_PACKET_ABORT_ABORTED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_ABORTED) -#define RAIL_RX_PACKET_ABORT_OVERFLOW ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_OVERFLOW) -#define RAIL_RX_PACKET_ABORT_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_CRC_ERROR) -#define RAIL_RX_PACKET_READY_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_CRC_ERROR) -#define RAIL_RX_PACKET_READY_SUCCESS ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_SUCCESS) -#define RAIL_RX_PACKET_RECEIVING ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_RECEIVING) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @typedef RAIL_RxPacketHandle_t - * @brief A handle used to reference a packet during reception processing. - * There are several sentinel handle values that pertain to certain - * circumstances: \ref RAIL_RX_PACKET_HANDLE_INVALID, \ref - * RAIL_RX_PACKET_HANDLE_OLDEST, \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE - * and \ref RAIL_RX_PACKET_HANDLE_NEWEST. - */ -typedef const void *RAIL_RxPacketHandle_t; - -/** An invalid RX packet handle value. */ -#define RAIL_RX_PACKET_HANDLE_INVALID (NULL) - -/** A special RX packet handle to refer to the oldest unreleased packet. - * This includes the newest unread packet which is possibly incomplete or not - * yet started. - * This handle is used implicitly by \ref RAIL_ReadRxFifo(). - */ -#define RAIL_RX_PACKET_HANDLE_OLDEST ((RAIL_RxPacketHandle_t) 1) - -/** A special RX packet handle to refer to the oldest unreleased - * complete packet. This never includes incomplete or unstarted packets. - * (Using \ref RAIL_RX_PACKET_HANDLE_OLDEST is inappropriate for this - * purpose because it can refer to an unstarted, incomplete, or - * unheld packet which are inappropriate to be consumed by the application.) - */ -#define RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE ((RAIL_RxPacketHandle_t) 2) - -/** A special RX packet handle to refer to the newest unreleased packet - * when in callback context. For a callback involving a completed - * receive event, this refers to the packet just completed. For - * other callback events, this refers to the next packet to be - * completed, which might be in-progress or might not have even - * started yet. - */ -#define RAIL_RX_PACKET_HANDLE_NEWEST ((RAIL_RxPacketHandle_t) 3) - -/** - * @struct RAIL_RxPacketInfo_t - * @brief Basic information about a packet being received or already - * completed and awaiting processing, including memory pointers to - * its data in the circular receive FIFO buffer. This packet information - * refers to remaining packet data that has not already been consumed - * by RAIL_ReadRxFifo(). - * @note Because the receive FIFO buffer is circular, a packet might start - * near the end of the buffer and wrap around to the beginning of - * the buffer to finish, hence the distinction between the first - * and last portions. Packets that fit without wrapping only have - * a first portion (firstPortionBytes == packetBytes and lastPortionData - * will be NULL). - */ -typedef struct RAIL_RxPacketInfo { - RAIL_RxPacketStatus_t packetStatus; /**< The packet status of this packet. */ - uint16_t packetBytes; /**< The number of packet data bytes - available to read in this packet. */ - uint16_t firstPortionBytes; /**< The number of bytes in the first portion. */ - uint8_t *firstPortionData; /**< The pointer to the first portion of packet - data containing firstPortionBytes - number of bytes. */ - uint8_t *lastPortionData; /**< The pointer to the last portion of a - packet, if any; NULL otherwise. The - number of bytes in this portion is - packetBytes - firstPortionBytes. */ - RAIL_AddrFilterMask_t filterMask; /**< A bitmask representing which address - filter(s) this packet has passed. - Will be 0 when not filtering or if - packet info is retrieved before - filtering has completed. It's - undefined on platforms lacking \ref - RAIL_SUPPORTS_ADDR_FILTER_MASK */ -} RAIL_RxPacketInfo_t; - -/** - * @struct RAIL_RxPacketDetails_t - * @brief Received packet details obtained via RAIL_GetRxPacketDetails() - * or RAIL_GetRxPacketDetailsAlt(). - * - * @note Certain details are always available, while others are only available - * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO - * option is not in effect and the received packet's - * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. - * Each detail's description indicates its availability. - * - */ -typedef struct RAIL_RxPacketDetails { - /** - * The timestamp of the received packet in the RAIL timebase. - * - * When not available it will be \ref RAIL_PACKET_TIME_INVALID. - */ - RAIL_PacketTimeStamp_t timeReceived; - /** - * Indicates whether the CRC passed or failed for the received packet. - * It is true for \ref RAIL_RX_PACKET_READY_SUCCESS packets and false - * for all others. - * - * It is always available. - */ - bool crcPassed; - /** - * Indicate whether the received packet was the expected ACK. - * It is true for the expected ACK and false otherwise. - * - * It is always available. - * - * An expected ACK is defined as a protocol-correct ACK packet - * successfully-received (\ref RAIL_RX_PACKET_READY_SUCCESS or - * \ref RAIL_RX_PACKET_READY_CRC_ERROR) and whose sync word was - * detected within the - * RAIL_AutoAckConfig_t::ackTimeout period following a transmit - * which specified \ref RAIL_TX_OPTION_WAIT_FOR_ACK, requested - * an ACK, and auto-ACK is enabled. When true, the ackTimeout - * period was terminated so no \ref RAIL_EVENT_RX_ACK_TIMEOUT - * will be subsequently posted for the transmit. - * - * A "protocol-correct ACK" applies to the 802.15.4 or Z-Wave - * protocols for which RAIL can discern the frame type and match - * the ACK's sequence number with that of the transmitted frame. - * For other protocols, the first packet successfully-received - * whose sync word was detected within the ackTimeout period is - * considered the expected ACK; upper layers are responsible for - * confirming this. - */ - bool isAck; - /** - * RSSI of the received packet in integer dBm. This RSSI measurement is - * started as soon as the sync word is detected. The duration of the - * measurement is PHY-specific. - * - * When not available it will be \ref RAIL_RSSI_INVALID_DBM. - */ - int8_t rssi; - /** - * The link quality indicator of the received packet. A zero would - * indicate a very low quality packet while a 255 would indicate a very - * high quality packet. - * - * When not available it will be 0. - */ - uint8_t lqi; - /** - * For radios and PHY configurations that support multiple sync words, this - * number is the ID of the sync word that was used for this packet. - * - * It is always available. - */ - uint8_t syncWordId; - /** - * In configurations where the radio has the option of receiving a given - * packet in multiple ways, indicates which of the sub-PHY options - * was used to receive the packet. Most radio configurations do not have - * this ability and the subPhyId is set to 0. - * - * Currently, this field is used by the BLE Coded PHY, the BLE Simulscan PHY - * and the SUN OFDM PHYs. - * In BLE cases, a value of 0 marks a 500 kbps packet, a value of 1 marks a 125 - * kbps packet, and a value of 2 marks a 1 Mbps packet. - * Also, see \ref RAIL_BLE_ConfigPhyCoded and \ref RAIL_BLE_ConfigPhySimulscan. - * - * In SUN OFDM cases, the value corresponds to the numerical value of the - * Modulation and Coding Scheme (MCS) level of the last received packet. - * The packet bitrate depends on the MCS value, as well as the OFDM option. - * Packets bitrates for SUN OFDM PHYs can be found in 802.15.4-2020 specification, - * chapter 20.3, table 20-10. - * Ex: Packet bitrate for OFDM option 1 MCS0 is 100kb/s and 2400kb/s for MCS6. - * - * In WMBUS cases, when using PHY_wMbus_ModeTC_M2O_100k_frameA with simultaneous - * RX of T and C modes enabled (\ref RAIL_WMBUS_Config()), the value corresponds - * to \ref RAIL_WMBUS_Phy_t. - * - * It is always available. - */ - uint8_t subPhyId; - /** - * For \ref Antenna_Control configurations where the device has multiple - * antennas, this indicates which antenna received the packet. When there - * is only one antenna, this will be set to the default of 0. - * - * It is always available. - */ - uint8_t antennaId; - /** - * When channel hopping is enabled, this field will contain the index - * of the channel in \ref RAIL_RxChannelHoppingConfig_t::entries on which - * this packet was received, or a sentinel value. On EFR32XG1 parts, - * on which channel hopping is not supported, this value is still part - * of the structure, but will be a meaningless value. - * - * It is always available. - */ - uint8_t channelHoppingChannelIndex; - /** - * The channel on which the packet was received. - * - * It is always available. - * - * @note It is best to fully process (empty or clear) the receive FIFO - * before changing channel configurations (\ref RAIL_ConfigChannels() - * or a built-in configuration) as unprocessed packets' channel - * could reflect the wrong configuration. On EFR32xG1 only this - * advice also applies when changing channels for receive or transmit - * where unprocessed packets' channel could reflect the new channel. - */ - uint16_t channel; -} RAIL_RxPacketDetails_t; - -/** - * @typedef RAIL_ConvertLqiCallback_t - * @brief A pointer to a function called before LQI is copied into the - * \ref RAIL_RxPacketDetails_t structure. - * - * @param[in] lqi The LQI value obtained by hardware and being readied for - * application consumption. This LQI value is in integral units ranging from - * 0 to 255. - * @param[in] rssi The RSSI value corresponding to the packet from which the - * hardware LQI value was obtained. This RSSI value is in integral dBm units. - * @return uint8_t The converted LQI value that will be loaded into the - * \ref RAIL_RxPacketDetails_t structure in preparation for application - * consumption. This value should likewise be in integral units ranging from - * 0 to 255. - */ -typedef uint8_t (*RAIL_ConvertLqiCallback_t)(uint8_t lqi, - int8_t rssi); - -/** @} */ // end of group Receive - -/****************************************************************************** - * Auto-ACK Structures - *****************************************************************************/ -/** - * @addtogroup Auto_Ack - * @{ - */ -/** - * @struct RAIL_AutoAckConfig_t - * @brief Enable/disable the auto-ACK algorithm, based on "enable". - * - * The structure provides a default state (the "success" of tx/rxTransitions - * when ACKing is enabled) for the radio to return to after an ACK - * operation occurs (transmitting or attempting to receive an ACK), or normal - * state transitions to return to in the case ACKing is - * disabled. Regardless whether the ACK operation was successful, the - * radio returns to the specified success state. - * - * ackTimeout specifies how long to stay in receive and wait for an ACK - * to start (sync detected) before issuing a RAIL_EVENT_RX_ACK_TIMEOUT - * event and return to the default state. - */ -typedef struct RAIL_AutoAckConfig { - /** - * Indicate whether auto-ACKing should be enabled or disabled. - */ - bool enable; - /** - * Define the RX ACK timeout duration in microseconds up to 65535 - * microseconds maximum. Only applied when auto-ACKing is enabled. - * The ACK timeout timer starts at the completion of a \ref - * RAIL_TX_OPTION_WAIT_FOR_ACK transmit and expires only while waiting - * for a packet (prior to SYNC detect), triggering \ref - * RAIL_EVENT_RX_ACK_TIMEOUT. During packet reception that event is - * held off until packet completion and suppressed entirely if the - * received packet is the expected ACK. - */ - uint16_t ackTimeout; - /** - * State transitions to do after receiving a packet. When auto-ACKing is - * enabled, the "error" transition is always ignored and the radio will - * return to the "success" state after any ACKing sequence - * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). - * See \ref RAIL_ConfigAutoAck for more details on this. - */ - RAIL_StateTransitions_t rxTransitions; - /** - * State transitions to do after transmitting a packet. When auto-ACKing is - * enabled, the "error" transition is always ignored and the radio will - * return to the "success" state after any ACKing sequence - * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). - * See \ref RAIL_ConfigAutoAck for more details on this. - */ - RAIL_StateTransitions_t txTransitions; -} RAIL_AutoAckConfig_t; - -/// Acknowledgment packets cannot be longer than 64 bytes. -#define RAIL_AUTOACK_MAX_LENGTH (64U) - -/** @} */ // end of group Auto_Ack - -/****************************************************************************** - * Antenna Control - *****************************************************************************/ -/** - * @addtogroup Antenna_Control - * @{ - * - * These enumerations and structures are used with RAIL Antenna Control API. - * EFR32 supports up to two antennas with configurable pin locations. - */ - -/** Antenna path Selection enumeration. */ -RAIL_ENUM(RAIL_AntennaSel_t) { - /** Enum for antenna path 0. */ - RAIL_ANTENNA_0 = 0, - /** Enum for antenna path 1. */ - RAIL_ANTENNA_1 = 1, - /** Enum for antenna path auto. */ - RAIL_ANTENNA_AUTO = 255, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0) -#define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1) -#define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_AntennaConfig_t - * @brief A configuration for antenna selection. - */ -typedef struct RAIL_AntennaConfig { - /** Antenna 0 Pin Enable */ - bool ant0PinEn; - /** Antenna 1 Pin Enable */ - bool ant1PinEn; - /** - * Antenna 0 location for ant0Port/Pin on EFR32 Series 1 - * and on EFR32 Series 2 this field is called \ref defaultPath - * (see define and usage below). - */ - uint8_t ant0Loc; - /** Antenna 0 output GPIO port */ - uint8_t ant0Port; - /** Antenna 0 output GPIO pin */ - uint8_t ant0Pin; - /** Antenna 1 location for ant1Port/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t ant1Loc; - /** Antenna 1 output GPIO port */ - uint8_t ant1Port; - /** Antenna 1 output GPIO pin */ - uint8_t ant1Pin; -} RAIL_AntennaConfig_t; - -/** - * Maps EFR32 Series 2 defaultPath onto Series 1 ant0Loc field. - * For EFR32 Series 2, defaultPath should be a \ref RAIL_AntennaSel_t - * value specifying the internal default RF path. It is ignored - * on EFR32 Series 2 parts that have only one RF path bonded - * out and on EFR32xG28 dual-band OPNs where the appropriate - * RF path is automatically set by RAIL to 0 for 2.4GHZ band - * and 1 for SubGHz band PHYs. On EFR32xG23 and EFR32xG28 - * single-band OPNs where both RF paths are bonded out this can - * be set to \ref RAIL_ANTENNA_AUTO to effect internal RF path - * diversity on PHYs supporting diversity. This avoids the need - * for an external RF switch and the associated GPIO(s) needed - * to control its antenna selection. - */ -#define defaultPath ant0Loc - -/** @} */ // end of group Antenna_Control - -/****************************************************************************** - * External_Thermistor Structures - *****************************************************************************/ -/** - * @addtogroup External_Thermistor - * @{ - */ - -/// A sentinel value to indicate an invalid thermistor measurement value. -#define RAIL_INVALID_THERMISTOR_VALUE (0xFFFFFFFFU) -/// A sentinel value to indicate an invalid PPM calculation value. -#define RAIL_INVALID_PPM_VALUE (-128) - -/** - * @struct RAIL_HFXOThermistorConfig_t - * @brief Configure the port and pin of the thermistor. - * @note This configuration is OPN dependent. - */ -typedef struct RAIL_HFXOThermistorConfig { - /** - * The GPIO port to access the thermistor. - */ - uint8_t port; - /** - * The GPIO pin to set the thermistor. - */ - uint8_t pin; -} RAIL_HFXOThermistorConfig_t; - -/** - * @struct RAIL_HFXOCompensationConfig_t - * @brief Set compensation specific parameters - */ -typedef struct RAIL_HFXOCompensationConfig { - /** - * Indicates whether the HFXO compensation in temperature is activated. - */ - bool enableCompensation; - /** - * The temperature reference delimiting the nominal zone from the critical one. - * This field is relevant if enableCompensation is set to true. - */ - int8_t zoneTemperatureC; - /** - * The temperature shift used to start a new compensation, in the nominal zone. - * This field is relevant if enableCompensation is set to true. - */ - uint8_t deltaNominal; - /** - * The temperature shift used to start a new compensation, in the critical zone. - * This field is relevant if enableCompensation is set to true. - */ - uint8_t deltaCritical; -} RAIL_HFXOCompensationConfig_t; -/** @} */ // end of group External_Thermistor - -/****************************************************************************** - * Calibration Structures - *****************************************************************************/ -/** - * @addtogroup Calibration - * @{ - * - * The EFR32 supports the Image Rejection (IR) - * calibration and a temperature-dependent calibration. The IR calibration - * can be computed once and stored off or computed each time at - * startup. Because it is PHY-specific and provides sensitivity improvements, - * it is highly recommended. The IR calibration should only be run when the - * radio is IDLE. - * - * The temperature-dependent calibrations are used to recalibrate the synth if - * the temperature crosses 0C or the temperature delta since the last - * calibration exceeds 70C while in receive. RAIL will run the VCO calibration - * automatically upon entering receive or transmit states, so the application - * can omit this calibration if the stack re-enters receive or transmit with - * enough frequency to avoid reaching the temperature delta. If the application - * does not calibrate for temperature, it's possible to miss receive packets due - * to a drift in the carrier frequency. - */ - -/** - * @typedef RAIL_CalMask_t - * @brief A calibration mask type - * - * This type is a bitmask of different RAIL calibration values. The exact - * meaning of these bits depends on what a particular chip supports. - */ -typedef uint32_t RAIL_CalMask_t; - -/** EFR32-specific temperature calibration bit. */ -#define RAIL_CAL_TEMP_VCO (0x00000001U) -/** EFR32-specific HFXO temperature check bit. - * (Ignored if platform lacks \ref RAIL_SUPPORTS_HFXO_COMPENSATION.) */ -#define RAIL_CAL_TEMP_HFXO (0x00000002U) -/** EFR32-specific HFXO compensation bit. - * (Ignored if platform lacks \ref RAIL_SUPPORTS_HFXO_COMPENSATION.) */ -#define RAIL_CAL_COMPENSATE_HFXO (0x00000004U) -/** EFR32-specific IR calibration bit */ -#define RAIL_CAL_RX_IRCAL (0x00010000U) -/** EFR32-specific Tx IR calibration bit. - * (Ignored if platform lacks \ref RAIL_SUPPORTS_OFDM_PA.) */ -#define RAIL_CAL_OFDM_TX_IRCAL (0x00100000U) - -/** A mask to run EFR32-specific IR calibrations. */ -#define RAIL_CAL_ONETIME_IRCAL (RAIL_CAL_RX_IRCAL | RAIL_CAL_OFDM_TX_IRCAL) -/** A mask to run temperature-dependent calibrations. */ -#define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO | RAIL_CAL_TEMP_HFXO | RAIL_CAL_COMPENSATE_HFXO) -/** A mask to run one-time calibrations. */ -#define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL) -/** A mask to run optional performance calibrations. */ -#define RAIL_CAL_PERF (0) -/** A mask for calibrations that require the radio to be off. */ -#define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL) -/** A mask to run all possible calibrations for this chip. */ -#define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME) -/** A mask to run all pending calibrations. */ -#define RAIL_CAL_ALL_PENDING (0x00000000U) -/** An invalid calibration value. */ -#define RAIL_CAL_INVALID_VALUE (0xFFFFFFFFU) - -/** - * @def RAIL_MAX_RF_PATHS - * @brief Indicates the maximum number of RF Paths supported across all - * platforms. - */ -#define RAIL_MAX_RF_PATHS 2 - -/** - * RAIL_RxIrCalValues_t - * @brief RX IR calibration values. - * - * Platforms with fewer \ref RAIL_RF_PATHS than \ref RAIL_MAX_RF_PATHS - * will only respect and update \ref RAIL_RF_PATHS indices and ignore - * the rest. - */ -typedef uint32_t RAIL_RxIrCalValues_t[RAIL_MAX_RF_PATHS]; - -/** - * A define to set all RAIL_RxIrCalValues_t values to uninitialized. - * - * This define can be used when you have no data to pass to the calibration - * routines but wish to compute and save all possible calibrations. - */ -#define RAIL_IRCALVALUES_RX_UNINIT { \ - [0 ... RAIL_MAX_RF_PATHS - 1] = RAIL_CAL_INVALID_VALUE, \ -} - -/** - * @struct RAIL_TxIrCalValues_t - * @brief A Tx IR calibration value structure. - * - * This definition contains the set of persistent calibration values for - * OFDM on EFR32. You can set these beforehand and apply them at startup - * to save the time required to compute them. Any of these values may be - * set to RAIL_IRCAL_INVALID_VALUE to force the code to compute that - * calibration value. - * - * Only supported on platforms with \ref RAIL_SUPPORTS_OFDM_PA enabled. - */ -typedef struct RAIL_TxIrCalValues { - uint32_t dcOffsetIQ; /**< TXIRCAL result */ - uint32_t phiEpsilon; /**< TXIRCAL result */ -} RAIL_TxIrCalValues_t; - -/** - * A define to set all RAIL_TxIrCalValues_t values to uninitialized. - * - * This define can be used when you have no data to pass to the calibration - * routines but wish to compute and save all possible calibrations. - */ -#define RAIL_IRCALVALUES_TX_UNINIT { \ - RAIL_CAL_INVALID_VALUE, \ - RAIL_CAL_INVALID_VALUE, \ -} - -/** - * @struct RAIL_IrCalValues_t - * @brief An IR calibration value structure. - * - * This definition contains the set of persistent calibration values for - * EFR32. You can set these beforehand and apply them at startup to save the - * time required to compute them. Any of these values may be set to - * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value. - */ -typedef struct RAIL_IrCalValues { - RAIL_RxIrCalValues_t rxIrCalValues; /**< RX Image Rejection (IR) calibration value */ - RAIL_TxIrCalValues_t txIrCalValues; /**< TX Image Rejection (IR) calibration value for OFDM */ -} RAIL_IrCalValues_t; - -/** - * A define to set all RAIL_IrCalValues_t values to uninitialized. - * - * This define can be used when you have no data to pass to the calibration - * routines but wish to compute and save all possible calibrations. - */ -#define RAIL_IRCALVALUES_UNINIT { \ - RAIL_IRCALVALUES_RX_UNINIT, \ - RAIL_IRCALVALUES_TX_UNINIT, \ -} - -/** - * A define allowing Rx calibration value access compatibility - * between non-OFDM and OFDM platforms. - */ -#define RAIL_IRCALVAL(irCalStruct, rfPath) \ - (((RAIL_IrCalValues_t *)(&(irCalStruct)))->rxIrCalValues[(rfPath)]) - -/** - * @typedef RAIL_CalValues_t - * @brief A calibration value structure. - * - * This structure contains the set of persistent calibration values for - * EFR32. You can set these beforehand and apply them at startup to save the - * time required to compute them. Any of these values may be set to - * RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value. - */ -typedef RAIL_IrCalValues_t RAIL_CalValues_t; - -/** - * A define to set all RAIL_CalValues_t values to uninitialized. - * - * This define can be used when you have no data to pass to the calibration - * routines but wish to compute and save all possible calibrations. - */ -#define RAIL_CALVALUES_UNINIT RAIL_IRCALVALUES_UNINIT - -/// Use this value with either TX or RX values in RAIL_SetPaCTune -/// to use whatever value is already set and do no update. This -/// value is provided to provide consistency across EFR32 chips, -/// but technically speaking, all PA capacitance tuning values are -/// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported -/// on those parts. -#define RAIL_PACTUNE_IGNORE (255U) - -/** @} */ // end of group Calibration - -/****************************************************************************** - * RF Sense Structures - *****************************************************************************/ -/** - * @addtogroup Rf_Sense - * @{ - */ - -/** - * A pointer to an RF Sense callback function. - * - * Consider using the event \ref RAIL_EVENT_RF_SENSED as an alternative. - */ -typedef void (*RAIL_RfSense_CallbackPtr_t)(void); - -/** - * RF Sense low sensitivity offset. - */ -#define RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET (0x20U) - -/** - * @enum RAIL_RfSenseBand_t - * @brief An enumeration for specifying the RF Sense frequency band. - */ -RAIL_ENUM(RAIL_RfSenseBand_t) { - RAIL_RFSENSE_OFF, /**< RF Sense is disabled. */ - RAIL_RFSENSE_2_4GHZ, /**< RF Sense is in 2.4 G band. */ - RAIL_RFSENSE_SUBGHZ, /**< RF Sense is in subgig band. */ - RAIL_RFSENSE_ANY, /**< RF Sense is in both bands. */ - RAIL_RFSENSE_MAX, // Must be last before sensitivity options. - RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_2_4GHZ, /**< RF Sense is in low sensitivity 2.4 G band */ - RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_SUBGHZ, /**< RF Sense is in low sensitivity subgig band */ - RAIL_RFENSE_ANY_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_ANY /**< RF Sense is in low sensitivity for both bands. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RFSENSE_OFF ((RAIL_RfSenseBand_t) RAIL_RFSENSE_OFF) -#define RAIL_RFSENSE_2_4GHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_2_4GHZ) -#define RAIL_RFSENSE_SUBGHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_SUBGHZ) -#define RAIL_RFSENSE_ANY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_ANY) -#define RAIL_RFSENSE_MAX ((RAIL_RfSenseBand_t) RAIL_RFSENSE_MAX) -#define RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY) -#define RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY) -#define RAIL_RFENSE_ANY_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFENSE_ANY_LOW_SENSITIVITY) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * Use the MODEM default sync word. - */ -#define RAIL_RFSENSE_USE_HW_SYNCWORD (0U) - -/** - * @struct RAIL_RfSenseSelectiveOokConfig_t - * @brief Structure to configure RFSENSE Selective(OOK) mode. - */ -typedef struct RAIL_RfSenseSelectiveOokConfig { - /** - * The frequency band(s) on which to sense the - * RF energy. To stop RF Sense, specify \ref RAIL_RFSENSE_OFF. - */ - RAIL_RfSenseBand_t band; - /** - * Syncword Length in bytes, 1-4 bytes. - * @note When \ref syncWord is set to use \ref RAIL_RFSENSE_USE_HW_SYNCWORD, - * the \ref syncWordNumBytes value will be ignored since we rely on the - * HW default settings for sync word. - */ - uint8_t syncWordNumBytes; - /** - * Sync Word Value. - * To use HW default sync word, set to \ref RAIL_RFSENSE_USE_HW_SYNCWORD. - */ - uint32_t syncWord; - /** - * The callback function, called when RF is sensed. - */ - RAIL_RfSense_CallbackPtr_t cb; -} RAIL_RfSenseSelectiveOokConfig_t; - -/** @} */ // end of group Rf_Sense - -/****************************************************************************** - * RX Channel Hopping - *****************************************************************************/ -/** - * @addtogroup Rx_Channel_Hopping RX Channel Hopping - * @{ - */ - -/** - * @enum RAIL_RxChannelHoppingMode_t - * @brief Modes by which RAIL can determine when to proceed to the next - * channel during channel hopping - */ -RAIL_ENUM(RAIL_RxChannelHoppingMode_t) { - /** - * Switch to the next channel each time the radio re-enters RX after - * packet reception or a transmit based on the corresponding \ref - * State_Transitions. A hop can also be manually triggered by calling - * \ref RAIL_CalibrateTemp() while the radio is listening. - * - * @warning This mode currently does not issue \ref - * RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE when hopping out of - * the last channel in the hop sequence. - * As a workaround, an application can monitor the current hop channel - * with \ref RAIL_GetChannelAlt(). - */ - RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL, - /** - * Switch to the next channel after a certain amount of time passes. - * The time should be specified in microseconds in \ref - * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less - * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT, - /** - * Listen in receive RX for at least a specified timeout. If, - * by the end of the timeout, the radio has packet timing, - * remain in the current channel until the radio loses it. The - * timeout should be specified in microseconds in \ref - * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less - * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE, - /** - * Listen in receive RX for at least a specified timeout. If, - * by the end of the timeout, the radio has a packet preamble, - * remain in the current channel until the radio loses it. The - * timeout should be specified in microseconds in \ref - * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less - * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE, - /** - * Placeholder for a reserved hopping mode that is not supported. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1, - /** - * A mode that combines modes TIMING_SENSE, PREAMBLE_SENSE, and - * TIMEOUT (sync detect) all running in parallel. Refer to \ref - * RAIL_RxChannelHoppingConfigMultiMode_t for further details. - * A pointer to that structure, allocated in global read-write - * memory and initialized to the desired configuration values, is - * specified as the \ref RAIL_RxChannelHoppingConfigEntry_t::parameter - * or \ref RAIL_RxDutyCycleConfig_t::parameter, cast appropriately: - * @code{.c} - * .parameter = (uint32_t)(void *)&hoppingConfigMultiMode, - * @endcode - * - * @note RAIL will overwrite the contents of the \ref - * RAIL_RxChannelHoppingConfigMultiMode_t during operation so it - * must be reinitialized with the desired configuration prior to - * every call to \ref RAIL_ConfigRxChannelHopping() or - * \ref RAIL_ConfigRxDutyCycle(). - * - * @note Multiple \ref RAIL_RxChannelHoppingConfigEntry_t entries may - * share the same \ref RAIL_RxChannelHoppingConfigMultiMode_t if their - * settings are identical, otherwise a separate \ref - * RAIL_RxChannelHoppingConfigMultiMode_t is needed for each - * \ref RAIL_RxChannelHoppingConfigEntry_t that uses this mode. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE, - /** - * Switch to the next channel based on the demodulation settings in the PHY - * config. This mode is PHY and chip dependent. The - * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter is ignored, and should - * be set to 0 for future compatibility. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_SQ, - /** - * Marks that the channel is concurrent with another channel, and otherwise - * behaves identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_CONC, - /** - * Indicates that this channel is a virtual channel that is concurrently - * detected with the channel indicated by the - * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter. Otherwise behaves - * identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ. - */ - RAIL_RX_CHANNEL_HOPPING_MODE_VT, - /** - * This is the transmit channel used for auto-ACK if the regular channel, - * specified in RAIL_RxChannelHoppingConfigEntry::parameter, is - * optimized for RX which may degrade some TX performance - */ - RAIL_RX_CHANNEL_HOPPING_MODE_TX, - /** - * A count of the basic choices in this enumeration. - */ - RAIL_RX_CHANNEL_HOPPING_MODES_COUNT, // Must be last before _WITH_OPTIONS twins - - /** - * The start of equivalent modes requiring non-default \ref - * RAIL_RxDutyCycleConfig_t::options, needed for backwards-compatibility - * with earlier \ref RAIL_RxDutyCycleConfig_t format. Non-default options - * are supported with \ref RAIL_RxChannelHoppingConfigEntry_t in all modes. - */ - RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE = 0x80, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS - = RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1 with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_CONC with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_VT with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS, - /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TX with options. */ - RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE) -#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE) -#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1 ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1) -#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE) -#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ) -#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC) -#define RAIL_RX_CHANNEL_HOPPING_MODE_VT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TX ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX) -#define RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE) -#define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS) -#define RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * The maximum sense time supported for those \ref RAIL_RxChannelHoppingMode_t - * modes whose parameter(s) specify a sensing time. - */ -#define RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US 0x08000000UL - -/** - * @enum RAIL_RxChannelHoppingDelayMode_t - * @deprecated Set only to RAIL_RX_CHANNEL_DELAY_MODE_STATIC - */ -RAIL_ENUM(RAIL_RxChannelHoppingDelayMode_t) { - /** - * Always delay for exactly the amount of time specified - * in the delay parameter, regardless of how other channel - * hopping channels were extended via preamble sense or other means. - */ - RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC, -}; - -/** - * @typedef RAIL_RxChannelHoppingParameter_t - * @brief Rx channel hopping on-channel time - */ -typedef uint32_t RAIL_RxChannelHoppingParameter_t; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC ((RAIL_RxChannelHoppingDelayMode_t) RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_RxChannelHoppingOptions_t - * @brief Options that can customize channel hopping behavior - * on a per-hop basis. - */ -RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) { - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL bit */ - RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL_SHIFT, - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL bit */ - RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT, - /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit */ - RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT, - /** Stop hopping on this hop. */ - RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT, - /** A count of the choices in this enumeration. */ - RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT // Must be last -}; - -/** A value representing no options enabled. */ -#define RAIL_RX_CHANNEL_HOPPING_OPTIONS_NONE 0U -/** - * All options disabled by default. - * Channel hopping will behave as described by other - * parameters as it did in RAIL 2.7 and earlier. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT RAIL_RX_CHANNEL_HOPPING_OPTIONS_NONE -/** - * @deprecated Please use \ref RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT instead. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTION_DEFAULT RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT -/** - * An option to skip synth calibration while *hopping into* the channel - * specified in the current entry. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL_SHIFT) -/** - * An option to skip DC calibration while *hopping into* the channel - * specified in the current entry. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT) -/** - * An option to check RSSI after *hopping into* the channel specified - * in the current entry and hop if that RSSI is below the threshold - * specified in \ref RAIL_RxChannelHoppingConfigEntry_t::rssiThresholdDbm. - * This check runs in parallel with the \ref RAIL_RxChannelHoppingMode_t - * specified and may cause a hop sooner than that mode otherwise would. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT) -/** - * An option to stop the hopping sequence at this entry in the hop - * table. - */ -#define RAIL_RX_CHANNEL_HOPPING_OPTION_STOP (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT) - -/// @struct RAIL_RxChannelHoppingConfigMultiMode_t -/// @brief Structure that parameterizes \ref -/// RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE. -/// -/// Every \ref RAIL_RxChannelHoppingConfigEntry_t or -/// \ref RAIL_RxDutyCycleConfig_t that uses \ref -/// RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE must allocate one of these -/// structures in global read-write memory to provide the settings -/// for this mode and for RAIL to use during hopping or duty cycling. -/// A pointer to this structure, cast appropriately, is what is passed -/// in the corresponding \ref RAIL_RxChannelHoppingConfigEntry_t::parameter -/// or \ref RAIL_RxDutyCycleConfig_t::parameter. -/// -/// The contents of this structure must be initialized prior to each -/// \ref RAIL_ConfigRxChannelHopping() or \ref RAIL_ConfigRxDutyCycle() -/// call and must not be touched thereafter until the next such call. -/// RAIL may change these contents during configuration or operation. -/// -/// This mode of operation functions algorithmically like this pseudocode: -/// @code{.c} -/// extern bool channelHopping; // true if channel hopping, false if duty cycling -/// extern RAIL_RxChannelHoppingConfigEntry_t *hopConfigEntry; // current channel -/// -/// static RAIL_RxChannelHoppingConfigMultiMode_t *multiParams; -/// static RAIL_Time_t rxStartTime; -/// static bool preambleSensed; -/// -/// static void hopOrSuspendRx(uint32_t delay) -/// { -/// disableDemodEvents(); -/// disableTimerEvents(); -/// stopTimer(); -/// if (channelHopping) { -/// hopToNextChannel(delay, &hopConfigEntry); // updates hopConfigEntry -/// } else { -/// suspendRx(delay); -/// } -/// onStartRx(); // resume receive after delay (on new channel if hopping) -/// } -/// -/// void onStartRx(void) // called upon entry to receive -/// { -/// rxStartTime = RAIL_GetTime(); -/// multiParams = (RAIL_RxChannelHoppingConfigMultiMode_t *) -/// (void *)hopConfigEntry->parameter; -/// startTimer(rxStartTime + multiParams->timingSense); -/// preambleSensed = false; -/// enableTimerEvents(); // timer will trigger onTimerEvent() handler -/// enableDemodEvents(); // demod will trigger onDemodEvent() handler -/// } -/// -/// void onTimerEvent(void) // called when timer expires -/// { -/// hopOrSuspendRx(hopConfigEntry->delay); -/// } -/// -/// void onDemodEvent(void) // called when demodulator state changes -/// { -/// if (DEMOD_TIMING_SENSED) { -/// stopTimer(); -/// startTimer(rxStartTime + multiParams->syncDetect); -/// } -/// if (DEMOD_TIMING_LOST) { -/// stopTimer(); -/// uint32_t newTimeout = RAIL_GetTime() + multiParams->timingReSense; -/// uint32_t limitTimeout; -/// if (preambleSensed) { -/// limitTimeout = rxStartTime + multiParams->syncDetect; -/// } else { -/// limitTimeout = rxStartTime + multiParams->preambleSense; -/// } -/// if (newTimeout > limitTimeout) { -/// newTimeout = limitTimeout; -/// } -/// if (newTimeout > RAIL_GetTime()) { -/// startTimer(newTimeout); -/// } else { -/// hopOrSuspendRx(hopConfigEntry->delay); -/// } -/// } -/// if (DEMOD_PREAMBLE_SENSED) { -/// preambleSensed = true; -/// } -/// if (DEMOD_PREAMBLE_LOST) { -/// preambleSensed = false; -/// } -/// if (DEMOD_SYNC_DETECTED) { -/// disableDemodEvents(); -/// disableTimerEvents(); -/// stopTimer(); -/// receivePacket(); // stay on channel to receive frame -/// hopOrSuspendRx(0); // continue RX per state transitions with no delay -/// } -/// } -/// @endcode - -typedef struct RAIL_RxChannelHoppingConfigMultiMode { - /** - * Switch to the next channel if sync is not detected before - * this time, in microseconds, measured from entry to Rx. - * This must be greater than preambleSense and less than - * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - uint32_t syncDetect; - /** - * Switch to the next channel if timing was sensed but then - * lost after this time, in microseconds, measured from entry - * to Rx -- unless preamble had been sensed in which case any - * switching is deferred to timingReSense and, if timing is - * regained, to syncDetect. This must be greater than timingSense - * and less than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - uint32_t preambleSense; - /** - * Switch to the next channel if timing is not sensed before - * this time, in microseconds, measured from entry to Rx. This - * must be greater than 2 and less than - * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - uint32_t timingSense; - /** - * Switch to the next channel if timing was sensed but then - * lost and not regained before this time, in microseconds, - * measured from when timing was lost. This must be less than - * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. - */ - uint32_t timingReSense; - /** - * Set this to 0. This field, along with the others, may be - * used internally by RAIL during configuration or operation. - */ - uint32_t status; -} RAIL_RxChannelHoppingConfigMultiMode_t; - -/** - * @struct RAIL_RxChannelHoppingConfigEntry_t - * @brief Structure that represents one of the channels that is part of a - * \ref RAIL_RxChannelHoppingConfig_t sequence of channels used in - * channel hopping. - */ -typedef struct RAIL_RxChannelHoppingConfigEntry { - /** - * The channel number to be used for this entry in the channel hopping - * sequence. If this is an invalid channel for the current PHY, the - * call to \ref RAIL_ConfigRxChannelHopping() will fail. - */ - uint16_t channel; - /** The mode by which RAIL determines when to hop to the next channel. */ - RAIL_RxChannelHoppingMode_t mode; - // Unnamed 'uint8_t reserved1[1]' pad byte field here. - /** - * Depending on the 'mode' parameter that was specified, this member - * is used to parameterize that mode. See the comments on each value of - * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. - */ - RAIL_RxChannelHoppingParameter_t parameter; - /** - * Idle time in microseconds to wait before hopping into the - * channel indicated by this entry. - */ - uint32_t delay; - /** @deprecated Set delayMode to RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */ - RAIL_RxChannelHoppingDelayMode_t delayMode; - /** - * Bitmask of various options that can be applied to the current - * channel hop. - */ - RAIL_RxChannelHoppingOptions_t options; - /** - * The RSSI threshold (in dBm) below which a hop will occur in - * any mode when \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD is - * specified. - */ - int8_t rssiThresholdDbm; - /** - * Pad bytes reserved for future use and currently ignored. - */ - uint8_t reserved2[1]; -} RAIL_RxChannelHoppingConfigEntry_t; - -/** - * @struct RAIL_RxChannelHoppingConfig_t - * @brief Wrapper struct that will contain the sequence of - * \ref RAIL_RxChannelHoppingConfigEntry_t that represents the channel - * sequence to use during RX Channel Hopping. - */ -typedef struct RAIL_RxChannelHoppingConfig { - /** - * Pointer to contiguous global read-write memory that will be used - * by RAIL to store channel hopping information throughout its operation. - * It need not be initialized and applications should never write - * data anywhere in this buffer. - * - * @note the size of this buffer must be at least as large as - * 3 + \ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * numberOfChannels, - * plus the sum of the sizes of the - * radioConfigDeltaAdd's of the required channels, plus the size of the - * radioConfigDeltaSubtract. In the case that one channel - * appears two or more times in your channel sequence - * (e.g., 1, 2, 3, 2), you must account for the radio configuration - * size that number of times (i.e., need to count channel 2's - * radio configuration size twice for the given example). The buffer is - * for internal use to the library. - */ - uint32_t *buffer; - /** - * This parameter must be set to the length of the buffer array, in 32 bit - * words. This way, during configuration, the software can confirm it's - * writing within the bounds of the buffer. The configuration API will return - * an error or trigger \ref RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT if - * bufferLength is insufficient. - */ - uint16_t bufferLength; - /** - * The number of channels in the channel hopping sequence, which is the - * number of elements in the array that entries points to. - */ - uint8_t numberOfChannels; - /** - * A pointer to the first element of an array of \ref - * RAIL_RxChannelHoppingConfigEntry_t that represents the channels - * used during channel hopping. The length of this array must be - * numberOfChannels. - */ - RAIL_RxChannelHoppingConfigEntry_t *entries; -} RAIL_RxChannelHoppingConfig_t; - -/** - * @struct RAIL_RxDutyCycleConfig_t - * @brief Structure to configure duty cycled receive mode. - */ -typedef struct RAIL_RxDutyCycleConfig { - /** The mode by which RAIL determines when to exit RX. */ - RAIL_RxChannelHoppingMode_t mode; - /** - * Depending on the 'mode' parameter that was specified, this member - * is used to parameterize that mode. See the comments on each value of - * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. - */ - // Unnamed 'uint8_t reserved[3]' pad byte field here. - RAIL_RxChannelHoppingParameter_t parameter; - /** - * Idle time in microseconds to wait before re-entering RX. - */ - uint32_t delay; - /** - * Indicate how the timing specified in 'delay' should be applied. - */ - RAIL_RxChannelHoppingDelayMode_t delayMode; - /** - * Bitmask of various options that can be applied to the current - * duty cycle operation when the mode is >= \ref - * RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS (ignored otherwise). - */ - RAIL_RxChannelHoppingOptions_t options; - /** - * The RSSI threshold (in dBm) below which Rx will end in - * any mode when \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD - * is specified. - */ - int8_t rssiThresholdDbm; - /** - * Pad bytes reserved for future use and currently ignored. - */ - uint8_t reserved2[1]; -} RAIL_RxDutyCycleConfig_t; - -/// A sentinel value to flag an invalid channel hopping index. -#define RAIL_CHANNEL_HOPPING_INVALID_INDEX (0xFEU) - -/** @} */ // end of group Rx_Channel_Hopping - -/****************************************************************************** - * Diagnostic Structures - *****************************************************************************/ -/** - * @addtogroup Diagnostic - * @{ - */ - -/** - * @typedef RAIL_FrequencyOffset_t - * @brief Type that represents the number of Frequency Offset - * units. It is used with \ref RAIL_GetRxFreqOffset() and - * \ref RAIL_SetFreqOffset(). - * - * The units are chip-specific. For EFR32 they are radio synthesizer - * resolution steps (synthTicks) and is limited to 15 bits. - * A value of \ref RAIL_FREQUENCY_OFFSET_INVALID - * means that this value is invalid. - */ -typedef int16_t RAIL_FrequencyOffset_t; - -/** - * The maximum frequency offset value supported. - */ -#define RAIL_FREQUENCY_OFFSET_MAX ((RAIL_FrequencyOffset_t) 0x3FFF) - -/** - * The minimum frequency offset value supported. - */ -#define RAIL_FREQUENCY_OFFSET_MIN ((RAIL_FrequencyOffset_t) -RAIL_FREQUENCY_OFFSET_MAX) - -/** - * Specify an invalid frequency offset value. This will be returned if you - * call \ref RAIL_GetRxFreqOffset() at an invalid time. - */ -#define RAIL_FREQUENCY_OFFSET_INVALID ((RAIL_FrequencyOffset_t) 0x8000) - -/** - * @struct RAIL_DirectModeConfig_t - * @brief Allows the user to specify direct mode - * parameters using \ref RAIL_ConfigDirectMode(). - */ -typedef struct RAIL_DirectModeConfig { - /** Enable synchronous RX DOUT using DCLK vs. asynchronous RX DOUT. */ - bool syncRx; - /** Enable synchronous TX DIN using DCLK vs. asynchronous TX DIN. */ - bool syncTx; - - /** RX Data output (DOUT) GPIO port */ - uint8_t doutPort; - /** RX Data output (DOUT) GPIO pin */ - uint8_t doutPin; - - /** Data clock (DCLK) GPIO port. Only used in synchronous mode */ - uint8_t dclkPort; - /** Data clock (DCLK) GPIO pin. Only used in synchronous mode */ - uint8_t dclkPin; - - /** TX Data input (DIN) GPIO port */ - uint8_t dinPort; - /** TX Data input (DIN) GPIO pin */ - uint8_t dinPin; - - /** RX Data output (DOUT) location for doutPort/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t doutLoc; - /** Data clock (DCLK) location for dclkPort/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t dclkLoc; - /** TX Data input (DIN) location for tdinPort/Pin. - * Only needed on EFR32 Series 1; ignored on other platforms. */ - uint8_t dinLoc; -} RAIL_DirectModeConfig_t; - -/** - * @enum RAIL_StreamMode_t - * @brief Possible stream output modes. - */ -RAIL_ENUM(RAIL_StreamMode_t) { - RAIL_STREAM_CARRIER_WAVE = 0, /**< An unmodulated carrier wave. */ - RAIL_STREAM_PN9_STREAM = 1, /**< PN9 byte sequence. */ - RAIL_STREAM_10_STREAM = 2, /**< 101010 sequence. */ - RAIL_STREAM_CARRIER_WAVE_PHASENOISE = 3, /**< An unmodulated carrier wave with no change to PLL BW. For EFR32 Series 2, same as RAIL_STREAM_CARRIER_WAVE */ - RAIL_STREAM_RAMP_STREAM = 4, /**< ramp sequence starting at a different offset for consecutive packets. Only available for some modulations. Fall back to RAIL_STREAM_PN9_STREAM if not available. */ - RAIL_STREAM_CARRIER_WAVE_SHIFTED = 5, /**< An unmodulated carrier wave not centered on DC but shifted roughly by channel_bandwidth/6 allowing an easy check of the residual DC. Only available for OFDM PA. Fall back to RAIL_STREAM_CARRIER_WAVE_PHASENOISE if not available. */ - RAIL_STREAM_MODES_COUNT /**< A count of the choices in this enumeration. Must be last. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_STREAM_CARRIER_WAVE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE) -#define RAIL_STREAM_PN9_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_PN9_STREAM) -#define RAIL_STREAM_10_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_10_STREAM) -#define RAIL_STREAM_CARRIER_WAVE_PHASENOISE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_PHASENOISE) -#define RAIL_STREAM_RAMP_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_RAMP_STREAM) -#define RAIL_STREAM_CARRIER_WAVE_SHIFTED ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_SHIFTED) -#define RAIL_STREAM_MODES_COUNT ((RAIL_StreamMode_t) RAIL_STREAM_MODES_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_VERIFY_DURATION_MAX - * @brief This radio state verification duration indicates to RAIL that - * all memory contents should be verified by RAIL before returning to the - * application. - */ -#define RAIL_VERIFY_DURATION_MAX 0xFFFFFFFFUL - -/** - * A pointer to a verification callback function. This will be called by the - * radio state verification feature built into RAIL when a verified memory - * value is different from its reference value. - * - * @param[in] address The address of the data in question. - * @param[in] expectedValue The expected value of the data in question. - * @param[in] actualValue The actual value of the data in question. - * @return bool True indicates a data value difference is acceptable. False - * indicates a data value difference in unacceptable. - * - * @note This callback will be issued when an address' value is different from - * its reference value and either of the following conditions are met: - * 1) The default radio configuration provided by the radio configurator is used - * for verification purposes (i.e., a custom radio configuration is not supplied - * as an input to \ref RAIL_ConfigVerification()), and the radio - * configurator has flagged the address under question as being verifiable. - * 2) A custom radio configuration is provided to the verification API (i.e., - * a custom radio configuration is supplied as an input to \ref - * RAIL_ConfigVerification()). When providing a custom radio configuration for - * verification purposes, all addresses in that configuration will be verified, - * regardless of whether or not the addresses are flagged as verifiable. - */ -typedef bool (*RAIL_VerifyCallbackPtr_t)(uint32_t address, - uint32_t expectedValue, - uint32_t actualValue); - -/** - * @struct RAIL_VerifyConfig_t - * @brief The configuration array provided to RAIL for use by the radio state - * verification feature. This structure will be populated with appropriate - * values by calling \ref RAIL_ConfigVerification(). The application should - * not set or alter any of these structure elements. - */ -typedef struct RAIL_VerifyConfig { - /** Internal verification tracking information. */ - RAIL_Handle_t correspondingHandle; - /** Internal verification tracking information. */ - uint32_t nextIndexToVerify; - /** Internal verification tracking information. */ - RAIL_RadioConfig_t override; - /** Internal verification tracking information. */ - RAIL_VerifyCallbackPtr_t cb; -} RAIL_VerifyConfig_t; - -/** @} */ // end of group Diagnostic - -/****************************************************************************** - * Energy Friendly Front End Module (EFF) - *****************************************************************************/ -/** - * @addtogroup EFF - * @{ - */ - -/** - * @enum RAIL_EffDevice_t - * @brief EFF part numbers. - * - * The part number of the attached EFF device is passed to - * \ref RAIL_ConfigEff() as \ref RAIL_EffConfig_t.device. - * The \ref rail_util_eff configures and controls - * the EFF based on the capabilities of the attached EFF. - */ -RAIL_ENUM(RAIL_EffDevice_t) { - RAIL_EFF_DEVICE_NONE = 0, /**< No EFF device attached. */ - RAIL_EFF_DEVICE_EFF01A11NMFA0, /**< +30 dBm, LNA, QFN24, +105C max ambient */ - RAIL_EFF_DEVICE_EFF01B11NMFA0, /**< PA Bypass, LNA, QFN24, +105C max ambient */ - RAIL_EFF_DEVICE_EFF01A11IMFB0, /**< +30 dBm, LNA, QFN24, +125C max ambient */ - RAIL_EFF_DEVICE_EFF01B11IMFB0, /**< PA Bypass, LNA, QFN24, +125C max ambient */ - RAIL_EFF_DEVICE_COUNT, /**< A count of the choices in this enumeration. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_EFF_DEVICE_NONE ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_NONE) -#define RAIL_EFF_DEVICE_EFF01A11NMFA0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01A11NMFA0) -#define RAIL_EFF_DEVICE_EFF01B11NMFA0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01B11NMFA0) -#define RAIL_EFF_DEVICE_EFF01A11IMFB0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01A11IMFB0) -#define RAIL_EFF_DEVICE_EFF01B11IMFB0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01B11IMFB0) -#define RAIL_EFF_DEVICE_COUNT ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_EFF_SUPPORTS_TRANSMIT(x) - * @brief A macro that checks for EFFxx devices that support high power transmit - */ -#define RAIL_EFF_SUPPORTS_TRANSMIT(x) ( ((x) == RAIL_EFF_DEVICE_EFF01A11NMFA0) \ - || ((x) == RAIL_EFF_DEVICE_EFF01A11IMFB0) \ - ) -/** - * @def RAIL_EFF_SUPPORTS_RECEIVE(x) - * @brief A macro that checks for EFFxx devices that support receive - */ -#define RAIL_EFF_SUPPORTS_RECEIVE(x) ( ((x) == RAIL_EFF_DEVICE_EFF01A11NMFA0) \ - || ((x) == RAIL_EFF_DEVICE_EFF01B11NMFA0) \ - || ((x) == RAIL_EFF_DEVICE_EFF01A11IMFB0) \ - || ((x) == RAIL_EFF_DEVICE_EFF01B11IMFB0) \ - ) - -/** Maximum EFF internal temperature in Kelvin, allowing transmissions when - * \ref RAIL_SUPPORTS_EFF is enabled. - */ -#define RAIL_EFF_TEMP_THRESHOLD_MAX (383U) - -/** - * @enum RAIL_EffLnaMode_t - * @brief EFF LNA Modes. - * - * The enabled EFF LNA modes are passed to\ref RAIL_ConfigEff() as the - * \ref RAIL_EffConfig_t.enabledLnaModes. - * The \ref rail_util_eff dynamically transitions between enabled LNA modes to - * maximize receive performance. - */ -RAIL_ENUM(RAIL_EffLnaMode_t) { - RAIL_EFF_LNA_MODE_RURAL = (0x01U << 0), /**< Rural LNA Mode. */ - RAIL_EFF_LNA_MODE_URBAN = (0x01U << 1), /**< Urban LNA Mode. */ - RAIL_EFF_LNA_MODE_BYPASS = (0x01U << 2), /**< Bypass LNA Mode. */ - RAIL_EFF_LNA_MODE_COUNT = (0x01U << 3), /**< A count of the choices in this enumeration. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_EFF_LNA_MODE_RURAL ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_RURAL) -#define RAIL_EFF_LNA_MODE_URBAN ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_URBAN) -#define RAIL_EFF_LNA_MODE_BYPASS ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_BYPASS) -#define RAIL_EFF_LNA_MODE_COUNT ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_ClpcEnable_t - * @brief EFF Closed Loop Power Control (CLPC) Enable states. - * - * The EFF CLPC Enable state is passed to \ref RAIL_ConfigEff() as the - * \ref RAIL_EffConfig_t.clpcEnable. - * The \ref rail_util_eff uses advanced power controls to tune EFF output to match - * Surface Acoustic Wave (SAW) filter losses and antenna performance. - */ -RAIL_ENUM(RAIL_ClpcEnable_t) { - RAIL_EFF_CLPC_DISABLED = 0, /**< CLPC actions are completely disabled. EFF will output but CLPC will not change modes, take power measurements or tune power output. Temperature measurements are taken.*/ - RAIL_EFF_CLPC_MODE_CHANGE = 1, /**< CLPC actions are completely disabled. EFF will output, change modes, and take measurements, but not tune power output. */ - RAIL_EFF_CLPC_POWER_SLOW = 2, /**< CLPC actions allows Slow Loop. EFF will output, change modes, and take measurements, and tune power output based on slow loop. */ - RAIL_EFF_CLPC_POWER_FAST = 3, /**< CLPC actions allows Fast Loop. EFF will output, change modes, and take measurements, and tune power output based on fast loop. */ - RAIL_EFF_CLPC_POWER_BOTH = 4, /**< CLPC actions are completely enabled. EFF will output, change modes, take measurements, and tune power output based on slow and fast loops. Default state. */ - RAIL_EFF_CLPC_POWER_SLOW_STOPPED = 5, /**< CLPC actions allows Slow Loop. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ - RAIL_EFF_CLPC_POWER_FAST_STOPPED = 6, /**< CLPC actions allows Fast Loop. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ - RAIL_EFF_CLPC_POWER_BOTH_STOPPED = 7, /**< CLPC actions are completely enabled. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ - RAIL_EFF_CLPC_COUNT = 8 /**< A count of the choices in this enumeration. Must be last. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_EFF_CLPC_DISABLED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_DISABLED) -#define RAIL_EFF_CLPC_MODE_CHANGE ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_MODE_CHANGE) -#define RAIL_EFF_CLPC_POWER_SLOW ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_SLOW) -#define RAIL_EFF_CLPC_POWER_FAST ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_FAST) -#define RAIL_EFF_CLPC_POWER_BOTH ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_BOTH) -#define RAIL_EFF_CLPC_POWER_SLOW_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_SLOW_STOPPED) -#define RAIL_EFF_CLPC_POWER_FAST_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_FAST_STOPPED) -#define RAIL_EFF_CLPC_POWER_BOTH_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_BOTH_STOPPED) -#define RAIL_EFF_CLPC_COUNT ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_EffModeSensor_t - * @brief EFF Closed Loop Power Control (CLPC) Mode Sensor Indices - * - * The mode sensor indices are used to access specific settings with CLPC. - */ -RAIL_ENUM(RAIL_EffModeSensor_t) { - RAIL_EFF_MODE_SENSOR_FSK_ANTV = 0, /**< CLPC FSK ANTV Sensor. */ - RAIL_EFF_MODE_SENSOR_FSK_SAW2 = 1, /**< CLPC FSK SAW2 Sensor. */ - RAIL_EFF_MODE_SENSOR_OFDM_ANTV = 2, /**< CLPC OFDM ANTV power calibration entry 1. */ - RAIL_EFF_MODE_SENSOR_OFDM_SAW2 = 3, /**< CLPC OFDM SAW2 power calibration entry 1. */ - RAIL_EFF_MODE_SENSOR_COUNT /**< A count of the choices in this enumeration. Must be last. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_EFF_MODE_SENSOR_FSK_ANTV ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_FSK_ANTV) -#define RAIL_EFF_MODE_SENSOR_FSK_SAW2 ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_FSK_SAW2) -#define RAIL_EFF_MODE_SENSOR_OFDM_ANTV ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_OFDM_ANTV) -#define RAIL_EFF_MODE_SENSOR_OFDM_SAW2 ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_OFDM_SAW2) -#define RAIL_EFF_MODE_SENSOR_COUNT ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_COUNT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @def RAIL_EFF_MODE_SENSOR_ENUM_NAMES - * @brief A macro that is string versions of the calibration enums. - */ -#define RAIL_EFF_MODE_SENSOR_ENUM_NAMES { \ - "RAIL_EFF_MODE_SENSOR_FSK_ANTV", \ - "RAIL_EFF_MODE_SENSOR_FSK_SAW2", \ - "RAIL_EFF_MODE_SENSOR_OFDM_ANTV", \ - "RAIL_EFF_MODE_SENSOR_OFDM_SAW2", \ -} - -/** - * @def RAIL_EFF_CLPC_ENABLE_ENUM_NAMES - * @brief A macro that is string versions of the calibration enums. - */ -#define RAIL_EFF_CLPC_ENABLE_ENUM_NAMES { \ - "RAIL_EFF_CLPC_DISABLED", \ - "RAIL_EFF_CLPC_MODE_CHANGE", \ - "RAIL_EFF_CLPC_POWER_SLOW", \ - "RAIL_EFF_CLPC_POWER_FAST", \ - "RAIL_EFF_CLPC_POWER_BOTH", \ - "RAIL_EFF_CLPC_POWER_SLOW_STOPPED", \ - "RAIL_EFF_CLPC_POWER_FAST_STOPPED", \ - "RAIL_EFF_CLPC_POWER_BOTH_STOPPED", \ - "RAIL_EFF_CLPC_COUNT", \ -} - -/** @struct RAIL_EffCalConfig_t - * - * @brief Calibration data for CLPC in a specific mode. - */ -typedef struct RAIL_EffCalConfig { - RAIL_TxPower_t cal1Ddbm; /**< Measured Output Power for CAL1 (nominally 270 ddBm) */ - uint16_t cal1Mv; /**< Measured Output Voltage using sensor at CAL1 ddBm */ - RAIL_TxPower_t cal2Ddbm; /**< Measured Output Power for CAL2 (nominally at 290 ddBm) */ - uint16_t cal2Mv; /**< Measured Output Voltage using sensor at CAL2 ddBm */ -} RAIL_EffCalConfig_t; - -/** @struct RAIL_EffClpcSensorConfig_t - * - * @brief Configuration data for a CLPC sensor. - * - * A structure of type \ref RAIL_EffClpcSensorConfig_t stores curve and calibration information for a CLPC sensor. - */ -typedef struct RAIL_EffClpcSensorConfig { - int64_t coefA; /**< Coefficient A for Sensor Voltage curve. Multiplied by 1e7. */ - int64_t coefB; /**< Coefficient B for Sensor Voltage curve. Multiplied by 1e7. */ - int64_t coefC; /**< Coefficient C for Sensor Voltage curve. Multiplied by 1e7. */ - int64_t coefD; /**< Coefficient D for Sensor Voltage curve. Multiplied by 1e7. */ - RAIL_EffCalConfig_t calData; /**< Calibration data for Sensor for this mode */ - int16_t slope1e1MvPerDdbm; /**< Calculated slope * 10 for Sensor calibration, measured in mV/ddBm */ - int16_t offset290Ddbm; /**< Calculated effective offset at 290 ddBm for Sensor calibration */ -} RAIL_EffClpcSensorConfig_t; - -/** @struct RAIL_EffClpcConfig_t - * - * @brief Configuration data for CLPC in a specific mode. - * - * A structure of type \ref RAIL_EffClpcConfig_t stores calibration information for each sensor in a specific mode. - */ -typedef struct RAIL_EffClpcConfig { - RAIL_EffClpcSensorConfig_t antv; /**< ANTV sensor configuration */ - RAIL_EffClpcSensorConfig_t saw2; /**< SAW2 sensor configuration */ -} RAIL_EffClpcConfig_t; - -/** @struct RAIL_EffClpcResults_t - * - * @brief Structure for passing information from the CLPC. - * - * A structure of type \ref RAIL_EffClpcResults_t returns the measurements and decisions from the - * Closed Loop Power Control back to the application side. - */ -typedef struct RAIL_EffClpcResults { - int8_t rawShift; /**< CLPC shift directly from formula */ - int8_t clampedShift; /**< Shift after clamping to maximum allowed for this pass */ - uint8_t currIndex; /**< Powersetting table index before shifting */ - uint8_t newIndex; /**< Power table index after shifting */ -} RAIL_EffClpcResults_t; - -/** - * @struct RAIL_EffConfig_t - * - * @brief Configuration data for the attached EFF device. - * - * A structure of type \ref RAIL_EffConfig_t is passed to \ref RAIL_ConfigEff(). - */ -typedef struct RAIL_EffConfig { - RAIL_EffDevice_t device; /**< EFF Device Type */ - uint8_t testPort; /**< TEST output GPIO port */ - uint8_t testPin; /**< TEST output GPIO pin */ - RAIL_EffLnaMode_t enabledLnaModes; /**< LNA modes enable bitmask **/ - uint16_t ruralUrbanMv; /**< Trip point from rural to urban mode, in millivolts */ - uint16_t urbanBypassMv; /**< Trip point from urban to bypass mode, in millivolts */ - uint16_t lnaReserved; /**< Reserved for future use */ - uint32_t urbanDwellTimeMs; /**< Time to stay in urban mode before transitioning to rural mode, in milliseconds */ - uint32_t bypassDwellTimeMs; /**< Time to stay in bypass mode before transitioning to urban or rural mode, in milliseconds */ - RAIL_EffClpcConfig_t fskClpcConfig; /**< Config Structure for FSK CLPC settings */ - RAIL_EffClpcConfig_t ofdmClpcConfig;/**< Config Structure for OFDM CLPC settings */ - uint8_t clpcReserved; /**< Reserved for future use */ - RAIL_ClpcEnable_t clpcEnable; /**< Select CLPC mode */ - bool advProtectionEnable; /**< Indicates whether the advanced thermal protection is enabled */ - uint8_t reservedByte; /**< Word alignment */ - uint16_t tempThresholdK; /**< Temperature of EFF above which transmit - is not allowed, in degrees Kelvin */ -} RAIL_EffConfig_t; - -/** @} */ // end of group EFF - -/****************************************************************************** - * Thermal Protection - *****************************************************************************/ -/** - * @addtogroup Thermal_Protection Thermal Protection - * @{ - */ - -/** Maximum junction temperature in Kelvin. A margin is subtracted before using it when - * \ref RAIL_SUPPORTS_THERMAL_PROTECTION is enabled. - */ -#define RAIL_CHIP_TEMP_THRESHOLD_MAX (398U) - -/** - * Default number of Kelvin degrees below threshold needed to allow transmissions. - */ -#define RAIL_CHIP_TEMP_COOLDOWN_DEFAULT (7U) - -/** - * @struct RAIL_ChipTempConfig_t - * - * @brief Configuration parameters for thermal protection. - */ -typedef struct RAIL_ChipTempConfig { - bool enable; /**< Indicates whether the protection is enabled */ - uint8_t coolDownK; /**< Mandatory temperature cool down when the threshold is exceeded, - in degrees Kelvin */ - uint16_t thresholdK; /**< Temperature above which transmit is blocked, - in degrees Kelvin */ -} RAIL_ChipTempConfig_t; - -/** Number of temperature values provided for the chip thermal protection */ -#define RAIL_CHIP_TEMP_MEASURE_COUNT (3U) - -/** - * @struct RAIL_ChipTempMetrics_t - * - * @brief Data used for thermal protection. - * - */ -typedef struct RAIL_ChipTempMetrics { - uint16_t tempK; /**< Store chip temperature for metrics */ - uint16_t minTempK; /**< Minimum temperature recorded */ - uint16_t maxTempK; /**< Maximum temperature recorded */ - bool resetPending; /**< Indicates if data should be reset */ - uint8_t reservedChipTemp; /**< Reserved for future use */ -} RAIL_ChipTempMetrics_t; - -/** @} */ // end of group Thermal_Protection - -// ----------------------------------------------------------------------------- -// Retiming -// ----------------------------------------------------------------------------- -/** - * @addtogroup Retiming Retiming - * @{ - * @brief EFR32-specific retiming capability. - * @ingroup RAIL_API - * - * The EFR product families have many digital and analog modules that can run - * in parallel with a radio. These combinations can cause interference and - * degradation on the radio RX sensitivity. Retiming can - * modify the clocking of the digital modules to reduce the interference. - */ - -/** - * @enum RAIL_RetimeOptions_t - * @brief Retiming options bit shifts. - */ -RAIL_ENUM(RAIL_RetimeOptions_t) { - /** Shift position of \ref RAIL_RETIME_OPTION_HFXO bit. */ - RAIL_RETIME_OPTION_HFXO_SHIFT = 0, - /** Shift position of \ref RAIL_RETIME_OPTION_HFRCO bit. */ - RAIL_RETIME_OPTION_HFRCO_SHIFT, - /** Shift position of \ref RAIL_RETIME_OPTION_DCDC bit. */ - RAIL_RETIME_OPTION_DCDC_SHIFT, - /** Shift position of \ref RAIL_RETIME_OPTION_LCD bit. */ - RAIL_RETIME_OPTION_LCD_SHIFT, -}; - -// RAIL_RetimeOptions_t bitmasks -/** - * An option to configure HFXO retiming. - */ -#define RAIL_RETIME_OPTION_HFXO \ - (1U << RAIL_RETIME_OPTION_HFXO_SHIFT) - -/** - * An option to configure HFRCO retiming. - */ -#define RAIL_RETIME_OPTION_HFRCO \ - (1U << RAIL_RETIME_OPTION_HFRCO_SHIFT) - -/** - * An option to configure DCDC retiming. - * Ignored on platforms that lack DCDC. - */ -#define RAIL_RETIME_OPTION_DCDC \ - (1U << RAIL_RETIME_OPTION_DCDC_SHIFT) - -/** - * An option to configure LCD retiming. - * Ignored on platforms that lack LCD. - */ -#define RAIL_RETIME_OPTION_LCD \ - (1U << RAIL_RETIME_OPTION_LCD_SHIFT) - -/** A value representing no retiming options. */ -#define RAIL_RETIME_OPTIONS_NONE 0x0U - -/** A value representing all retiming options. */ -#define RAIL_RETIME_OPTIONS_ALL 0xFFU - -/** - * Configure retiming options. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] mask A bitmask containing which options should be modified. - * @param[in] options A bitmask containing desired configuration settings. - * Bit positions for each option are found in the \ref RAIL_RetimeOptions_t. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ConfigRetimeOptions(RAIL_Handle_t railHandle, - RAIL_RetimeOptions_t mask, - RAIL_RetimeOptions_t options); - -/** - * Get the currently configured retiming option. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pOptions A pointer to configured retiming options - bitmask indicating which are enabled. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_GetRetimeOptions(RAIL_Handle_t railHandle, - RAIL_RetimeOptions_t *pOptions); - -/** - * Indicate that the DCDC peripheral bus clock enable has changed allowing - * RAIL to react accordingly. - * - * @note This should be called after DCDC has been enabled or disabled. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ChangedDcdc(void); - -/** @} */ // end of group Retiming_EFR32 - -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -/****************************************************************************** - * Debug Structures - *****************************************************************************/ -/** - * @addtogroup Debug - * @{ - */ - -/** - * @def RAIL_DEBUG_MODE_FREQ_OVERRIDE - * @brief A bitmask to enable the frequency override debug mode to - * manually tune to a specified frequency. Note that this should only be used - * for testing and is not as tuned as frequencies from the calculator. - */ -#define RAIL_DEBUG_MODE_FREQ_OVERRIDE 0x00000001UL - -/** - * @def RAIL_DEBUG_MODE_VALID_MASK - * @brief Any debug mode bits outside of this mask are invalid and ignored. - */ -#define RAIL_DEBUG_MODE_VALID_MASK (~(RAIL_DEBUG_MODE_FREQ_OVERRIDE)) - -/** @} */ // end of group Debug - -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** @} */ // end of RAIL_API - -#ifdef __cplusplus -} -#endif - -// Define SLI_LIBRARY_BUILD to build a library that does not include -// chip-dependent defines. This may limit functionality but allows building -// generic libraries that are not tied to any given chip. -#ifdef SLI_LIBRARY_BUILD -#ifndef DOXYGEN_SHOULD_SKIP_THIS - -// Platform-agnostic worst-case settings and types - -#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ - RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE - -struct RAIL_ChannelConfigEntryAttr { - RAIL_RxIrCalValues_t calValues; - RAIL_TxIrCalValues_t txCalValues; // placeholder for size -}; - -#endif//DOXYGEN_SHOULD_SKIP_THIS -#else//!SLI_LIBRARY_BUILD - -// Include appropriate chip-specific types and APIs *after* common types, and -// *before* types that depend on chip-specific types. -#include "rail_chip_specific.h" - -// (Currently no types depend on chip-specific types.) - -#endif //SLI_LIBRARY_BUILD - -#endif // __RAIL_TYPES_H__ +/***************************************************************************//** + * @file + * @brief This file contains the type definitions for RAIL structures, enums, + * and other types. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_TYPES_H__ +#define __RAIL_TYPES_H__ + +// Include standard type headers to help define structures +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef DOXYGEN_SHOULD_SKIP_THIS +/// The RAIL library does not use enumerations because the ARM EABI leaves their +/// size ambiguous, which causes problems if the application is built +/// with different flags than the library. Instead, uint8_t typedefs +/// are used in compiled code for all enumerations. For documentation purposes, this is +/// converted to an actual enumeration since it's much easier to read in Doxygen. +#define RAIL_ENUM(name) enum name +/// This macro is a more generic version of the \ref RAIL_ENUM() macro that +/// allows the size of the type to be overridden instead of forcing the use of +/// a uint8_t. See \ref RAIL_ENUM() for more information. +#define RAIL_ENUM_GENERIC(name, type) enum name +#else +/// Define used for the RAIL library, which sets each enumeration to a uint8_t +/// typedef and creates a named enumeration structure for the enumeration values. +#define RAIL_ENUM(name) typedef uint8_t name; enum name##_enum +#define RAIL_ENUM_GENERIC(name, type) typedef type name; enum name##_enum +// For debugging, use the following define to turn this back into a proper enumeration +// #define RAIL_ENUM(name) typedef enum name##_enum name; enum name##_enum +#endif + +/** + * @addtogroup RAIL_API + * @{ + */ + +/****************************************************************************** + * General Structures + *****************************************************************************/ +/** + * @addtogroup General + * @{ + */ + +/** + * @struct RAIL_Version_t + * @brief Contains RAIL Library Version Information. + * It is filled in by RAIL_GetVersion(). + */ +typedef struct RAIL_Version { + uint32_t hash; /**< Git hash */ + uint8_t major; /**< Major number */ + uint8_t minor; /**< Minor number */ + uint8_t rev; /**< Revision number */ + uint8_t build; /**< Build number */ + uint8_t flags; /**< Build flags */ + /** Boolean to indicate whether this is a multiprotocol library or not. */ + bool multiprotocol; +} RAIL_Version_t; + +/** + * @typedef RAIL_Handle_t + * @brief A generic handle to a particular radio (e.g. RAIL_EFR32_HANDLE), + * or a real handle of a RAIL instance, as returned from RAIL_Init(). + * + * Generic handles should be used for certain RAIL APIs that are called + * prior to RAIL initialization. However, once RAIL has been initialized, + * the real handle returned by RAIL_Init() should be used instead. + */ +typedef void *RAIL_Handle_t; + +/** + * A placeholder for a chip-specific RAIL handle. Using NULL as a RAIL handle + * is not recommended. As a result, another value that can't be de-referenced + * is used. + * + * This generic handle can and should be used for RAIL APIs that are called + * prior to RAIL initialization. + */ +#define RAIL_EFR32_HANDLE ((RAIL_Handle_t)0xFFFFFFFFUL) + +/** + * @enum RAIL_Status_t + * @brief A status returned by many RAIL API calls indicating their success or + * failure. + */ +RAIL_ENUM(RAIL_Status_t) { + RAIL_STATUS_NO_ERROR, /**< RAIL function reports no error. */ + RAIL_STATUS_INVALID_PARAMETER, /**< Call to RAIL function threw an error + because of an invalid parameter. */ + RAIL_STATUS_INVALID_STATE, /**< Call to RAIL function threw an error + because it was called during an invalid + radio state. */ + RAIL_STATUS_INVALID_CALL, /**< RAIL function is called in an invalid order. */ + RAIL_STATUS_SUSPENDED, /**< RAIL function did not finish in the allotted + time. */ + RAIL_STATUS_SCHED_ERROR, /**< RAIL function could not be scheduled + by the Radio scheduler. Only issued when + using a Multiprotocol application. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_STATUS_NO_ERROR ((RAIL_Status_t) RAIL_STATUS_NO_ERROR) +#define RAIL_STATUS_INVALID_PARAMETER ((RAIL_Status_t) RAIL_STATUS_INVALID_PARAMETER) +#define RAIL_STATUS_INVALID_STATE ((RAIL_Status_t) RAIL_STATUS_INVALID_STATE) +#define RAIL_STATUS_INVALID_CALL ((RAIL_Status_t) RAIL_STATUS_INVALID_CALL) +#define RAIL_STATUS_SUSPENDED ((RAIL_Status_t) RAIL_STATUS_SUSPENDED) +#define RAIL_STATUS_SCHED_ERROR ((RAIL_Status_t) RAIL_STATUS_SCHED_ERROR) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * A pointer to init complete callback function + * + * @param[in] railHandle The initialized RAIL instance handle. + * + */ +typedef void (*RAIL_InitCompleteCallbackPtr_t)(RAIL_Handle_t railHandle); + +/** A value to signal that RAIL should not use DMA. */ +#define RAIL_DMA_INVALID (0xFFU) + +/** + * @struct RAILSched_Config_t + * @brief Provided for backwards compatibility. + */ +typedef struct RAILSched_Config { + uint8_t buffer[1]; /**< Dummy buffer no longer used. */ +} RAILSched_Config_t; + +/** + * @typedef RAIL_StateBuffer_t + * @brief Provided for backwards compatibility. + */ +typedef uint8_t RAIL_StateBuffer_t[1]; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/** + * A linked list structure for RAIL state buffers which \ref RAIL_Init() + * utilizes for managing internal RAIL state. + */ +typedef struct RAIL_StateBufferEntry { + struct RAIL_StateBufferEntry *next; /**< pointer to next buffer in linked list */ + uint32_t bufferBytes; /**< size of the buffer */ + uint64_t *buffer; /**< pointer to the buffer in RAM */ +} RAIL_StateBufferEntry_t; + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group General + +/****************************************************************************** + * System Timing Structures + *****************************************************************************/ +/** + * @addtogroup System_Timing + * @{ + */ + +/** + * @typedef RAIL_Time_t + * @brief Time in microseconds + */ +typedef uint32_t RAIL_Time_t; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * @typedef RAIL_TimerTick_t + * @brief Internal RAIL hardware timer tick that drives the RAIL timebase. + * + * @note \ref RAIL_TimerTick_t does not use the full 32-bit range since we also + * account for fractional error drift on timebase overflow. This counts up + * to ~17 minutes before wrapping. + * + * @note \ref RAIL_TimerTicksToUs() can be used to convert the delta between + * two \ref RAIL_TimerTick_t values to microseconds. + */ +typedef uint32_t RAIL_TimerTick_t; +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * A pointer to the callback called when the RAIL timer expires. + * + * @param[in] cbArg The argument passed to the callback. + */ +typedef void (*RAIL_TimerCallback_t)(RAIL_Handle_t cbArg); + +/** + * @enum RAIL_TimeMode_t + * @brief Specify a time offset in RAIL APIs. + * + * Different APIs use the same constants and may provide more specifics about + * how they're used but the general use for each is described below. + */ +RAIL_ENUM(RAIL_TimeMode_t) { + /** + * The time specified is an exact time in the RAIL timebase. The given + * event should happen at exactly that time. If this time is already in the + * past, an error is returned. Because the RAIL timebase wraps at 32 + * bits, there is no real 'past'. Instead, any event greater than + * 3/4 of the way into the future is considered to be in the past. + */ + RAIL_TIME_ABSOLUTE, + /** + * The time specified is relative to the current time. The event should occur + * that many ticks in the future. Delays are only guaranteed at least as long + * as the value specified. An overhead may occur between the time when the + * API is called and when the delay starts. As a result, using this for + * operations that must happen at an exact given time is not recommended. + * For that, you must use \ref RAIL_TIME_ABSOLUTE delays. + * + * Note that, if you specify a delay 0, that event is triggered as soon as + * possible. This is different than specifying an absolute time of now which + * would return an error unless it was possible. + */ + RAIL_TIME_DELAY, + /** + * The specified time is invalid and should be ignored. For some APIs this + * can also indicate that any previously stored delay should be invalidated + * and disabled. + */ + RAIL_TIME_DISABLED, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_TIME_ABSOLUTE ((RAIL_TimeMode_t) RAIL_TIME_ABSOLUTE) +#define RAIL_TIME_DELAY ((RAIL_TimeMode_t) RAIL_TIME_DELAY) +#define RAIL_TIME_DISABLED ((RAIL_TimeMode_t) RAIL_TIME_DISABLED) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/// Forward declaration of RAIL_MultiTimer +struct RAIL_MultiTimer; + +/** + * @typedef RAIL_MultiTimerCallback_t + * @brief Callback fired when timer expires. + * + * @param[in] tmr A pointer to an expired timer. + * @param[in] expectedTimeOfEvent An absolute time event fired. + * @param[in] cbArg A user-supplied callback argument. + */ +typedef void (*RAIL_MultiTimerCallback_t)(struct RAIL_MultiTimer *tmr, + RAIL_Time_t expectedTimeOfEvent, + void *cbArg); + +/** + * @struct RAIL_MultiTimer_t + * @brief RAIL timer state structure + * + * This structure is filled out and maintained internally only. + * The user/application should not alter any elements of this structure. + */ +typedef struct RAIL_MultiTimer { + RAIL_Time_t absOffset; /**< Absolute time before the next event. */ + RAIL_Time_t relPeriodic; /**< Relative, periodic time between events; 0 = timer is oneshot. */ + RAIL_MultiTimerCallback_t callback; /**< A user callback. */ + void *cbArg; /**< A user callback argument. */ + struct RAIL_MultiTimer *next; /**< A pointer to the next soft timer structure. */ + uint8_t priority; /**< A priority of the callback; 0 = highest priority; 255 = lowest. */ + bool isRunning; /**< Indicates the timer is currently running. */ + bool doCallback; /**< Indicates the callback needs to run. */ +} RAIL_MultiTimer_t; + +/** + * @enum RAIL_PacketTimePosition_t + * @brief The available packet timestamp position choices + */ +RAIL_ENUM(RAIL_PacketTimePosition_t) { + /** + * Indicate that a timestamp is not to be or was not provided. + * It is useful if the application doesn't care about packet timestamps + * and doesn't want RAIL to spend time calculating one. + */ + RAIL_PACKET_TIME_INVALID = 0, + /** + * Request the choice most expedient for RAIL to calculate, + * which may depend on the radio and/or its configuration. + * The actual choice would always be reflected in the timePosition + * field of \ref RAIL_RxPacketDetails_t or \ref RAIL_TxPacketDetails_t + * returned and would never be one of the _USED_TOTAL values. + */ + RAIL_PACKET_TIME_DEFAULT = 1, + /** + * Request the timestamp corresponding to the first preamble bit + * sent or received. + * Indicate that timestamp did not require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_PREAMBLE_START = 2, + /** + * Request the timestamp corresponding to the first preamble bit + * sent or received. + * Indicate that timestamp did require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL = 3, + /** + * Request the timestamp corresponding to right after its last + * SYNC word bit has been sent or received. + * Indicate that timestamp did not require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_SYNC_END = 4, + /** + * Request the timestamp corresponding to right after its last + * SYNC word bit has been sent or received. + * Indicate that timestamp did require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL = 5, + /** + * Request the timestamp corresponding to right after its last + * bit has been sent or received. + * Indicate that timestamp did not require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_PACKET_END = 6, + /** + * Request the timestamp corresponding to right after its last + * bit has been sent or received. + * Indicate that timestamp did require using totalPacketBytes. + */ + RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL = 7, + RAIL_PACKET_TIME_COUNT /**< A count of the choices in this enumeration. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_PACKET_TIME_INVALID ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_INVALID) +#define RAIL_PACKET_TIME_DEFAULT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_DEFAULT) +#define RAIL_PACKET_TIME_AT_PREAMBLE_START ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START) +#define RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PREAMBLE_START_USED_TOTAL) +#define RAIL_PACKET_TIME_AT_SYNC_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END) +#define RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_SYNC_END_USED_TOTAL) +#define RAIL_PACKET_TIME_AT_PACKET_END ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END) +#define RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_AT_PACKET_END_USED_TOTAL) +#define RAIL_PACKET_TIME_COUNT ((RAIL_PacketTimePosition_t) RAIL_PACKET_TIME_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_PacketTimeStamp_t + * @brief Information for calculating and representing a packet timestamp. + */ +typedef struct RAIL_PacketTimeStamp { + /** + * Timestamp of the packet in the RAIL timebase. + */ + RAIL_Time_t packetTime; + /** + * A value specifying the total length in bytes of the packet + * used when calculating the packetTime requested by the timePosition + * field. This should account for all bytes sent over the air after + * the Preamble and Sync word(s) including CRC bytes. + */ + uint16_t totalPacketBytes; + /** + * A RAIL_PacketTimePosition_t value specifying the packet position + * to return in the packetTime field. + * If this is \ref RAIL_PACKET_TIME_DEFAULT, this field will be + * updated with the actual position corresponding to the packetTime + * value filled in by a call using this structure. + */ + RAIL_PacketTimePosition_t timePosition; + /** + * In RX for EFR32xG25 only : + * A value specifying the on-air duration of the data packet, + * starting with the first bit of the PHR (i.e. end of sync word). + * Preamble and sync word duration are hence excluded. + * + * In Tx for all EFR32 Series 2 except EFR32xG21 : + * A value specifying the on-air duration of the data packet, + * starting at the preamble (i.e. includes preamble, sync word, PHR, payload and FCS). + * This value can be use to compute duty cycles. + * + * At the present time, this field is set to zero for all EFR32 Series 1 and EFR32xG21, + * and also for transmission of auto-ack. + */ + RAIL_Time_t packetDurationUs; +} RAIL_PacketTimeStamp_t; + +/** @} */ // end of group System_Timing + +/****************************************************************************** + * Sleep Structures + *****************************************************************************/ +/** + * @addtogroup Sleep + * @{ + */ + +/** + * @enum RAIL_SleepConfig_t + * @brief The configuration + */ +RAIL_ENUM(RAIL_SleepConfig_t) { + RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED, /**< Disable timer sync before and after sleep. */ + RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, /**< Enable timer sync before and after sleep. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_DISABLED) +#define RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED ((RAIL_SleepConfig_t) RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_TimerSyncConfig_t + * @brief Channel values used to perform timer sync before and after sleep. + * + * The default value of this structure is provided in the + * \ref RAIL_TIMER_SYNC_DEFAULT macro. + */ +typedef struct RAIL_TimerSyncConfig { + /** + * PRS Channel used for timer sync operations. + */ + uint8_t prsChannel; + /** + * RTCC Channel used for timer sync operations + */ + uint8_t rtccChannel; + /** + * Whether to sync the timer before and after sleeping + */ + RAIL_SleepConfig_t sleep; +} RAIL_TimerSyncConfig_t; + +/** @} */ // end of group Sleep + +/****************************************************************************** + * Multiprotocol Structures + *****************************************************************************/ +/** + * @addtogroup Multiprotocol + * @{ + */ + +/** + * @struct RAIL_SchedulerInfo_t + * @brief A structure to hold information used by the scheduler. + * + * For multiprotocol versions of RAIL, this can be used to control how a receive + * or transmit operation is run. It's not necessary in single-protocol applications. + */ +typedef struct RAIL_SchedulerInfo { + /** + * The scheduler priority to use for this operation. This priority is used to + * preempt a long running lower-priority task to ensure higher-priority + * operations complete in time. A lower numerical value represents a higher + * logical priority meaning 0 is the highest priority and 255 is the lowest. + */ + uint8_t priority; + /** + * The amount of time in us that this operation can slip by into the future + * and still be run. This time is relative to the start time which may be + * the current time for relative transmits. If the scheduler can't start the + * operation by this time, it will be considered a failure. + */ + RAIL_Time_t slipTime; + /** + * The transaction time in us for this operation. Since transaction times may + * not be known exactly, use a minimum or an expected + * guess for this time. The scheduler will use the value entered here to look + * for overlaps between low-priority and high-priority tasks and attempt to + * find a schedule where all tasks get to run. + */ + RAIL_Time_t transactionTime; +} RAIL_SchedulerInfo_t; + +/** Radio Scheduler Status mask*/ +#define RAIL_SCHEDULER_STATUS_MASK 0x0FU +/** Radio Scheduler Status shift*/ +#define RAIL_SCHEDULER_STATUS_SHIFT 0 + +/** Radio Scheduler Task mask*/ +#define RAIL_SCHEDULER_TASK_MASK 0xF0U +/** Radio Scheduler Task shift*/ +#define RAIL_SCHEDULER_TASK_SHIFT 4 +/** + * @enum RAIL_SchedulerStatus_t + * @brief Multiprotocol scheduler status returned by RAIL_GetSchedulerStatus(). + * + * \ref Multiprotocol scheduler status is a combination of the upper 4 bits which + * constitute the type of scheduler task and the lower 4 bits which constitute + * the type of scheduler error. + */ +RAIL_ENUM(RAIL_SchedulerStatus_t) { + /** Lower 4 bits of uint8_t capture the different Radio Scheduler errors */ + /** Multiprotocol scheduler reports no error. */ + RAIL_SCHEDULER_STATUS_NO_ERROR = (0U << RAIL_SCHEDULER_STATUS_SHIFT), + /** + * The scheduler is disabled or the requested scheduler operation is + * unsupported. + */ + RAIL_SCHEDULER_STATUS_UNSUPPORTED = (1U << RAIL_SCHEDULER_STATUS_SHIFT), + /** + * The scheduled task was started but was interrupted by a higher-priority + * event before it could be completed. + */ + RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED = (2U << RAIL_SCHEDULER_STATUS_SHIFT), + /** + * Scheduled task could not be scheduled given its priority and the other + * tasks running on the system. + */ + RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL = (3U << RAIL_SCHEDULER_STATUS_SHIFT), + /** + * Calling the RAIL API associated with the Radio scheduler task returned + * an error code. See \ref RAIL_GetSchedulerStatus or \ref RAIL_GetSchedulerStatusAlt + * for more information about \ref RAIL_Status_t status. + */ + RAIL_SCHEDULER_STATUS_TASK_FAIL = (4U << RAIL_SCHEDULER_STATUS_SHIFT), + /** + * An internal error occurred in scheduler data structures, which should + * not happen and indicates a problem. + */ + RAIL_SCHEDULER_STATUS_INTERNAL_ERROR = (5U << RAIL_SCHEDULER_STATUS_SHIFT), + + /** Upper 4 bits of uint8_t capture the different Radio Scheduler tasks */ + RAIL_SCHEDULER_TASK_EMPTY = (0U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_ScheduleRx(). */ + RAIL_SCHEDULER_TASK_SCHEDULED_RX = (1U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartScheduledTx(). */ + RAIL_SCHEDULER_TASK_SCHEDULED_TX = (2U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartTx(). */ + RAIL_SCHEDULER_TASK_SINGLE_TX = (3U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartCcaCsmaTx(). */ + RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX = (4U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartCcaLbtTx(). */ + RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX = (5U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartScheduledCcaCsmaTx(). */ + RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX = (6U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartScheduledCcaLbtTx(). */ + RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX = (7U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartTxStream(). */ + RAIL_SCHEDULER_TASK_TX_STREAM = (8U << RAIL_SCHEDULER_TASK_SHIFT), + /** Radio scheduler calls \ref RAIL_StartAverageRssi(). */ + RAIL_SCHEDULER_TASK_AVERAGE_RSSI = (9U << RAIL_SCHEDULER_TASK_SHIFT), + + /** \ref RAIL_StartScheduledTx() returned error status. */ + RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_StartTx() returned error status. */ + RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_StartCcaCsmaTx() returned error status. */ + RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_StartCcaLbtTx() returned error status. */ + RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_ScheduleRx() returned error status. */ + RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_RX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_StartTxStream() returned error status. */ + RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL = (RAIL_SCHEDULER_TASK_TX_STREAM + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** \ref RAIL_StartAverageRssi() returned error status. */ + RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + + /** Multiprotocol scheduled receive function internal error. */ + RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol scheduled receive scheduling error. */ + RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_RX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_ScheduleRx() operation interrupted */ + RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_RX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol scheduled TX internal error. */ + RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol scheduled TX scheduling error. */ + RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartScheduledTx() operation interrupted */ + RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol instantaneous TX internal error. */ + RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol instantaneous TX scheduling error. */ + RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartTx() operation interrupted */ + RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol single CSMA transmit function internal error. */ + RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol single CSMA transmit scheduling error. */ + RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartCcaCsmaTx() operation interrupted */ + RAIL_SCHEDULER_SINGLE_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol single LBT transmit function internal error. */ + RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol single LBT transmit scheduling error. */ + RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartCcaLbtTx() operation interrupted */ + RAIL_SCHEDULER_SINGLE_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol scheduled CSMA transmit function internal error. */ + RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** \ref RAIL_StartScheduledCcaCsmaTx() returned error status. */ + RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** Multiprotocol scheduled CSMA transmit scheduling error. */ + RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartScheduledCcaCsmaTx() operation interrupted */ + RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol scheduled LBT transmit function internal error. */ + RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** \ref RAIL_StartScheduledCcaLbtTx() returned error status. */ + RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_TASK_FAIL), + /** Multiprotocol scheduled LBT transmit scheduling error. */ + RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartScheduledCcaLbtTx() operation interrupted */ + RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED = (RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol stream transmit function internal error. */ + RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol stream transmit scheduling error. */ + RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_TX_STREAM + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartTxStream() operation interrupted */ + RAIL_SCHEDULER_TX_STREAM_INTERRUPTED = (RAIL_SCHEDULER_TASK_TX_STREAM + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), + + /** Multiprotocol RSSI averaging function internal error. */ + RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI + | RAIL_SCHEDULER_STATUS_INTERNAL_ERROR), + /** Multiprotocol RSSI average scheduling error. */ + RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI + | RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL), + /** \ref RAIL_StartAverageRssi() operation interrupted */ + RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED = (RAIL_SCHEDULER_TASK_AVERAGE_RSSI + | RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED), +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_SCHEDULER_STATUS_NO_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_NO_ERROR) +#define RAIL_SCHEDULER_STATUS_UNSUPPORTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_UNSUPPORTED) +#define RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_EVENT_INTERRUPTED) +#define RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULE_FAIL) +#define RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SINGLE_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_CSMA_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_CCA_LBT_TX_FAIL) +#define RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_SCHEDULED_RX_FAIL) +#define RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_TX_STREAM_FAIL) +#define RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_AVERAGE_RSSI_FAIL) +#define RAIL_SCHEDULER_STATUS_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_STATUS_INTERNAL_ERROR) + +#define RAIL_SCHEDULER_TASK_EMPTY ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_EMPTY) +#define RAIL_SCHEDULER_TASK_SCHEDULED_RX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_RX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_CSMA_TX) +#define RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SINGLE_CCA_LBT_TX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_CSMA_TX) +#define RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_SCHEDULED_CCA_LBT_TX) +#define RAIL_SCHEDULER_TASK_TX_STREAM ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_TX_STREAM) +#define RAIL_SCHEDULER_TASK_AVERAGE_RSSI ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TASK_AVERAGE_RSSI) + +#define RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_RX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SINGLE_TX_INTERRUPTED) +#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_CSMA_TX_INTERRUPTED) +#define RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_CCA_LBT_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_FAIL) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_CSMA_TX_INTERRUPTED) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERNAL_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_FAIL) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_SCHEDULED_CCA_LBT_TX_INTERRUPTED) +#define RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERNAL_ERROR) +#define RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_TX_STREAM_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_TX_STREAM_INTERRUPTED) +#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERNAL_ERROR) +#define RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_SCHEDULING_ERROR) +#define RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED ((RAIL_SchedulerStatus_t) RAIL_SCHEDULER_AVERAGE_RSSI_INTERRUPTED) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_TaskType_t + * @brief Multiprotocol radio operation task types, used with + * RAIL_SetTaskPriority. + */ +RAIL_ENUM(RAIL_TaskType_t) { + /** Indicate a task started using RAIL_StartRx */ + RAIL_TASK_TYPE_START_RX, + /** Indicate a task started functions other than RAIL_StartRx */ + RAIL_TASK_TYPE_OTHER, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_TASK_TYPE_START_RX ((RAIL_TaskType_t) RAIL_TASK_TYPE_START_RX) +#define RAIL_TASK_TYPE_OTHER ((RAIL_TaskType_t) RAIL_TASK_TYPE_OTHER) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group Multiprotocol + +/****************************************************************************** + * Event Structures + *****************************************************************************/ +/** + * @addtogroup Events + * @{ + */ + +/** + * @enum RAIL_Events_t + * @brief RAIL events passed to the event callback. More than one event may be + * indicated due to interrupt latency. + */ +RAIL_ENUM_GENERIC(RAIL_Events_t, uint64_t) { + // RX Event Bit Shifts + + /** Shift position of \ref RAIL_EVENT_RSSI_AVERAGE_DONE bit */ + RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT = 0, + /** Shift position of \ref RAIL_EVENT_RX_ACK_TIMEOUT bit */ + RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_FIFO_ALMOST_FULL bit */ + RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_PACKET_RECEIVED bit */ + RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_LOST bit */ + RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_PREAMBLE_DETECT bit */ + RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_SYNC1_DETECT bit */ + RAIL_EVENT_RX_SYNC1_DETECT_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_SYNC2_DETECT bit */ + RAIL_EVENT_RX_SYNC2_DETECT_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_FRAME_ERROR bit */ + RAIL_EVENT_RX_FRAME_ERROR_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_FIFO_FULL bit */ + RAIL_EVENT_RX_FIFO_FULL_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_FIFO_OVERFLOW bit */ + RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_ADDRESS_FILTERED bit */ + RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_TIMEOUT bit */ + RAIL_EVENT_RX_TIMEOUT_SHIFT, + /** Shift position of \ref RAIL_EVENT_SCHEDULED_RX_STARTED bit */ + RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_END bit */ + RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_SCHEDULED_RX_MISSED bit */ + RAIL_EVENT_RX_SCHEDULED_RX_MISSED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_PACKET_ABORTED bit */ + RAIL_EVENT_RX_PACKET_ABORTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_FILTER_PASSED bit */ + RAIL_EVENT_RX_FILTER_PASSED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_TIMING_LOST bit */ + RAIL_EVENT_RX_TIMING_LOST_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_TIMING_DETECT bit */ + RAIL_EVENT_RX_TIMING_DETECT_SHIFT, + /** Shift position of \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE bit */ + RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT, + /** Shift position of \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND bit */ + RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT, + +// TX Event Bit Shifts + + /** Shift position of \ref RAIL_EVENT_ZWAVE_BEAM bit */ + RAIL_EVENT_ZWAVE_BEAM_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY bit */ + RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_PACKET_SENT bit */ + RAIL_EVENT_TX_PACKET_SENT_SHIFT, + /** Shift position of \ref RAIL_EVENT_TXACK_PACKET_SENT bit */ + RAIL_EVENT_TXACK_PACKET_SENT_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_ABORTED bit */ + RAIL_EVENT_TX_ABORTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TXACK_ABORTED bit */ + RAIL_EVENT_TXACK_ABORTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_BLOCKED bit */ + RAIL_EVENT_TX_BLOCKED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TXACK_BLOCKED bit */ + RAIL_EVENT_TXACK_BLOCKED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_UNDERFLOW bit */ + RAIL_EVENT_TX_UNDERFLOW_SHIFT, + /** Shift position of \ref RAIL_EVENT_TXACK_UNDERFLOW bit */ + RAIL_EVENT_TXACK_UNDERFLOW_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_CLEAR bit */ + RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_CHANNEL_BUSY bit */ + RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_CCA_RETRY bit */ + RAIL_EVENT_TX_CCA_RETRY_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_START_CCA bit */ + RAIL_EVENT_TX_START_CCA_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_STARTED bit */ + RAIL_EVENT_TX_STARTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_SCHEDULED_TX_MISSED bit */ + RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT, + + // Scheduler Event Bit Shifts + + /** Shift position of \ref RAIL_EVENT_CONFIG_UNSCHEDULED bit */ + RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT, + /** Shift position of \ref RAIL_EVENT_CONFIG_SCHEDULED bit */ + RAIL_EVENT_CONFIG_SCHEDULED_SHIFT, + /** Shift position of \ref RAIL_EVENT_SCHEDULER_STATUS bit */ + RAIL_EVENT_SCHEDULER_STATUS_SHIFT, + + // Other Event Bit Shifts + + /** Shift position of \ref RAIL_EVENT_CAL_NEEDED bit */ + RAIL_EVENT_CAL_NEEDED_SHIFT, + /** Shift position of \ref RAIL_EVENT_RF_SENSED bit */ + RAIL_EVENT_RF_SENSED_SHIFT, + /** Shift position of \ref RAIL_EVENT_PA_PROTECTION bit */ + RAIL_EVENT_PA_PROTECTION_SHIFT, + /** Shift position of \ref RAIL_EVENT_SIGNAL_DETECTED bit */ + RAIL_EVENT_SIGNAL_DETECTED_SHIFT, + /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_START bit */ + RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT, + /** Shift position of \ref RAIL_EVENT_IEEE802154_MODESWITCH_END bit */ + RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT, + /** Shift position of \ref RAIL_EVENT_DETECT_RSSI_THRESHOLD bit */ + RAIL_EVENT_DETECT_RSSI_THRESHOLD_SHIFT, + /** Shift position of \ref RAIL_EVENT_THERMISTOR_DONE bit */ + RAIL_EVENT_THERMISTOR_DONE_SHIFT, + /** Shift position of \ref RAIL_EVENT_TX_BLOCKED_TOO_HOT bit */ + RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT, + /** Shift position of \ref RAIL_EVENT_TEMPERATURE_TOO_HOT bit */ + RAIL_EVENT_TEMPERATURE_TOO_HOT_SHIFT, + /** Shift position of \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN bit */ + RAIL_EVENT_TEMPERATURE_COOL_DOWN_SHIFT, +}; + +/** Shift position of \ref RAIL_EVENT_SCHEDULED_TX_STARTED bit */ +#define RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT +/** Shift position of \ref RAIL_EVENT_RX_DUTY_CYCLE_RX_END bit */ +#define RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT +/** Shift position of \ref RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT bit */ +#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT +/** Shift position of \ref RAIL_EVENT_MFM_TX_BUFFER_DONE bit */ +#define RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT + +// RAIL_Event_t bitmasks + +/** A value representing no events */ +#define RAIL_EVENTS_NONE 0ULL + +/** + * Occurs when the hardware-averaged RSSI is done in response to + * RAIL_StartAverageRssi() to indicate that the hardware has completed + * averaging. + * + * Call RAIL_GetAverageRssi() to get the result. + */ +#define RAIL_EVENT_RSSI_AVERAGE_DONE (1ULL << RAIL_EVENT_RSSI_AVERAGE_DONE_SHIFT) + +/** + * Occurs when the ACK timeout expires while waiting to receive the + * sync word of an expected ACK. If the timeout occurs within packet + * reception, this event won't be signaled until after packet + * completion has determined the packet wasn't the expected ACK. + * See \ref RAIL_RxPacketDetails_t::isAck for the definition of an + * expected ACK. + * + * This event only occurs after calling RAIL_ConfigAutoAck() and after + * transmitting a packet with \ref RAIL_TX_OPTION_WAIT_FOR_ACK set. + */ +#define RAIL_EVENT_RX_ACK_TIMEOUT (1ULL << RAIL_EVENT_RX_ACK_TIMEOUT_SHIFT) + +/** + * Keeps occurring as long as the number of bytes in the receive FIFO + * exceeds the configured threshold value. + * + * Call RAIL_GetRxFifoBytesAvailable() to get the number of + * bytes available. When using this event, the threshold should be set via + * RAIL_SetRxFifoThreshold(). + * + * How to avoid sticking in the event handler (even in idle state): + * 1. Disable the event (via the config events API or the + * \ref RAIL_FIFO_THRESHOLD_DISABLED parameter) + * 2. Increase FIFO threshold + * 3. Read the FIFO (that's not an option in + * \ref RAIL_DataMethod_t::PACKET_MODE) in the event handler + */ +#define RAIL_EVENT_RX_FIFO_ALMOST_FULL (1ULL << RAIL_EVENT_RX_FIFO_ALMOST_FULL_SHIFT) + +/** + * Occurs whenever a packet is received with \ref RAIL_RX_PACKET_READY_SUCCESS + * or \ref RAIL_RX_PACKET_READY_CRC_ERROR. + * + * Call RAIL_GetRxPacketInfo() to get + * basic information about the packet along with a handle to this packet for + * subsequent use with RAIL_PeekRxPacket(), RAIL_GetRxPacketDetails(), + * RAIL_HoldRxPacket(), and RAIL_ReleaseRxPacket() as needed. + */ +#define RAIL_EVENT_RX_PACKET_RECEIVED (1ULL << RAIL_EVENT_RX_PACKET_RECEIVED_SHIFT) + +/** + * Occurs when the radio has lost a preamble. + * + * This event can occur multiple + * times while searching for a packet and is generally used for diagnostic + * purposes. It can only occur after a + * \ref RAIL_EVENT_RX_PREAMBLE_DETECT event has already occurred. + * + * @note See warning for \ref RAIL_EVENT_RX_PREAMBLE_DETECT. + */ +#define RAIL_EVENT_RX_PREAMBLE_LOST (1ULL << RAIL_EVENT_RX_PREAMBLE_LOST_SHIFT) + +/** + * Occurs when the radio has detected a preamble. + * + * This event can occur multiple + * times while searching for a packet and is generally used for diagnostic + * purposes. It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT + * event has already occurred. + * + * @warning This event, along with \ref RAIL_EVENT_RX_PREAMBLE_LOST, + * may not work on some demodulators. Some demodulators usurped the signals + * on which these events are based for another purpose. These demodulators + * in particular are available on the EFR32xG23, EFR32xG25, and the EFR32xG28 + * platforms. Enabling these events on these platforms may cause the + * events to fire infinitely and possibly freeze the application. + */ +#define RAIL_EVENT_RX_PREAMBLE_DETECT (1ULL << RAIL_EVENT_RX_PREAMBLE_DETECT_SHIFT) + +/** + * Occurs when the first sync word is detected. + * + * After this event occurs, one of + * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. + */ +#define RAIL_EVENT_RX_SYNC1_DETECT (1ULL << RAIL_EVENT_RX_SYNC1_DETECT_SHIFT) + +/** + * Occurs when the second sync word is detected. + * + * After this event occurs, one of + * the events in the \ref RAIL_EVENTS_RX_COMPLETION mask will occur. + */ +#define RAIL_EVENT_RX_SYNC2_DETECT (1ULL << RAIL_EVENT_RX_SYNC2_DETECT_SHIFT) + +/** + * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_CRC_ERROR + * which only happens after any filtering has passed. + * + * For EFR32 parts, this event includes CRC errors, block decoding errors, + * and illegal frame length -- when detected after filtering. (When such + * errors are detected during filtering, they're signaled as \ref + * RAIL_EVENT_RX_PACKET_ABORTED instead.) + * + * If \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS is set, this event will not + * occur for CRC errors, but could still occur for the other errors. + */ +#define RAIL_EVENT_RX_FRAME_ERROR (1ULL << RAIL_EVENT_RX_FRAME_ERROR_SHIFT) + +/** + * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event + * occurs coincident to a receive packet completion event in which the + * receive FIFO or any supplemental packet metadata FIFO (see \ref + * Data_Management) are full and further packet reception is jeopardized. + * + * It signals that an overflow is imminent (and may already have occurred) + * telling the application it should release the oldest packet(s) as soon + * as possible. This event may may be posted multiple times with subsequent + * receive completion events if the FIFO(s) remain full, and should also + * occur coincident with \ref RAIL_EVENT_RX_FIFO_OVERFLOW. + * + * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event + * is not tied to packet completion and will occur coincident with + * \ref RAIL_EVENT_RX_FIFO_OVERFLOW when the receive FIFO has filled and + * overflowed. The application should consume receive FIFO data via + * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data. + */ +#define RAIL_EVENT_RX_FIFO_FULL (1ULL << RAIL_EVENT_RX_FIFO_FULL_SHIFT) + +/** + * When using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event + * occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_OVERFLOW + * due to overflowing the receive FIFO or any supplemental packet metadata + * FIFO (see \ref Data_Management). + * + * The radio suspends receiving packets until this event is posted and + * the receive FIFO(s) have been fully processed (drained and released + * or reset). It is not guaranteed that a \ref RAIL_EVENT_RX_FIFO_FULL + * will precede this event, but both events should be coincident. + * + * When not using \ref RAIL_RxDataSource_t::RX_PACKET_DATA this event + * is not tied to packet completion and will occur coincident with + * \ref RAIL_EVENT_RX_FIFO_FULL when the receive FIFO has filled and + * overflowed. The application should consume receive FIFO data via + * \ref RAIL_ReadRxFifo() as soon as possible to minimize lost raw data. + */ +#define RAIL_EVENT_RX_FIFO_OVERFLOW (1ULL << RAIL_EVENT_RX_FIFO_OVERFLOW_SHIFT) + +/** + * Occurs when a receive is aborted with \ref RAIL_RX_PACKET_ABORT_FILTERED + * because its address does not match the filtering settings. + * + * This event can only occur after calling RAIL_EnableAddressFilter(). + */ +#define RAIL_EVENT_RX_ADDRESS_FILTERED (1ULL << RAIL_EVENT_RX_ADDRESS_FILTERED_SHIFT) + +/** + * Occurs when an RX event times out. + * + * This event can only occur if the + * RAIL_StateTiming_t::rxSearchTimeout passed to RAIL_SetStateTiming() is + * not zero. + */ +#define RAIL_EVENT_RX_TIMEOUT (1ULL << RAIL_EVENT_RX_TIMEOUT_SHIFT) + +/** + * Occurs when a scheduled RX begins turning on the receiver. + * This event has the same numerical value as RAIL_EVENT_SCHEDULED_TX_STARTED + * because one cannot schedule both RX and TX simultaneously. + */ +#define RAIL_EVENT_SCHEDULED_RX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_RX_STARTED_SHIFT) + +/** + * Occurs when a scheduled TX begins turning on the transmitter. + * This event has the same numerical value as RAIL_EVENT_SCHEDULED_RX_STARTED + * because one cannot schedule both RX and TX simultaneously. + */ +#define RAIL_EVENT_SCHEDULED_TX_STARTED (1ULL << RAIL_EVENT_SCHEDULED_TX_STARTED_SHIFT) + +/** + * Occurs when the scheduled RX window ends. + * + * This event only occurs in response + * to a scheduled receive timeout after calling RAIL_ScheduleRx(). If + * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as false, + * this event will occur unless the receive is aborted (due to a call to + * RAIL_Idle() or a scheduler preemption, for instance). If + * RAIL_ScheduleRxConfig_t::rxTransitionEndSchedule was passed as true, + * any of the \ref RAIL_EVENTS_RX_COMPLETION events occurring will also cause + * this event not to occur, since the scheduled receive will end with the + * transition at the end of the packet. However, if the application has not + * enabled the specific \ref RAIL_EVENTS_RX_COMPLETION event which implicitly + * ended the scheduled receive, this event will be posted instead. + */ +#define RAIL_EVENT_RX_SCHEDULED_RX_END (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_END_SHIFT) + +/** + * Occurs when start of a scheduled receive is missed + * + * This can occur if the radio is put to sleep and not woken up with enough time + * to configure the scheduled receive event. + */ +#define RAIL_EVENT_RX_SCHEDULED_RX_MISSED (1ULL << RAIL_EVENT_RX_SCHEDULED_RX_MISSED_SHIFT) + +/** + * Occurs when a receive is aborted during filtering with + * \ref RAIL_RX_PACKET_ABORT_FORMAT or after filtering with + * \ref RAIL_RX_PACKET_ABORT_ABORTED for reasons other than address + * filtering mismatch (which triggers \ref RAIL_EVENT_RX_ADDRESS_FILTERED + * instead). + * + * For EFR32 parts, this event includes CRC errors, block decoding errors, + * illegal frame length, and other RAIL built-in protocol-specific packet + * content errors -- when detected during filtering. (When such errors + * are detected after filtering, they're signaled as \ref + * RAIL_EVENT_RX_FRAME_ERROR instead.) It also includes application or + * multiprotocol scheduler aborting a receive after filtering has passed. + */ +#define RAIL_EVENT_RX_PACKET_ABORTED (1ULL << RAIL_EVENT_RX_PACKET_ABORTED_SHIFT) + +/** + * Occurs when the packet has passed any configured address and frame + * filtering options. + * + * This event will only occur between the start of the + * packet, indicated by \ref RAIL_EVENT_RX_SYNC1_DETECT or + * \ref RAIL_EVENT_RX_SYNC2_DETECT and one of the events in the + * \ref RAIL_EVENTS_RX_COMPLETION mask. It will always occur before or + * concurrently with \ref RAIL_EVENT_RX_PACKET_RECEIVED. If IEEE 802.15.4 frame + * and address filtering are enabled, this event will occur immediately after + * destination address filtering. + */ +#define RAIL_EVENT_RX_FILTER_PASSED (1ULL << RAIL_EVENT_RX_FILTER_PASSED_SHIFT) + +/** + * Occurs when the modem timing is lost. + * + * This event can occur multiple times + * while searching for a packet and is generally used for diagnostic purposes. + * It can only occur after a \ref RAIL_EVENT_RX_TIMING_DETECT event has + * already occurred. + * + * @note See warning for \ref RAIL_EVENT_RX_TIMING_DETECT. + */ +#define RAIL_EVENT_RX_TIMING_LOST (1ULL << RAIL_EVENT_RX_TIMING_LOST_SHIFT) + +/** + * Occurs when the modem timing is detected. + * + * This event can occur multiple times + * while searching for a packet and is generally used for diagnostic purposes. + * + * @warning This event, along with \ref RAIL_EVENT_RX_TIMING_LOST, + * may not work on some demodulators. Some demodulators usurped the signals + * on which these events are based for another purpose. These demodulators + * in particular are available on the EFR32xG23, EFR32xG25, and the EFR32xG28 + * platforms. Enabling these events on these platforms may cause the + * events to fire infinitely and possibly freeze the application. + */ +#define RAIL_EVENT_RX_TIMING_DETECT (1ULL << RAIL_EVENT_RX_TIMING_DETECT_SHIFT) + +/** + * Occurs when RX Channel Hopping is enabled and channel hopping finishes + * receiving on the last channel in its sequence. + * + * The intent behind this event + * is to allow the user to keep the radio on for as short a time as possible. + * That is, once the channel sequence is complete, the application will receive + * this event and can trigger a sleep/idle until it is necessary to cycle + * through the channels again. If this event is left on indefinitely and not + * handled it will likely be a fairly noisy event, as it continues to fire + * each time the hopping algorithm cycles through the channel sequence. + * + * @warning This event currently does not occur when using \ref + * RAIL_RxChannelHoppingMode_t::RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL. + * As a workaround, an application can monitor the current hop channel + * with \ref RAIL_GetChannelAlt(). + */ +#define RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE (1ULL << RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE_SHIFT) + +/** + * Occurs during RX duty cycle mode when the radio finishes its time in + * receive mode. + * + * The application can then trigger a sleep/idle until it + * needs to listen again. + */ +#define RAIL_EVENT_RX_DUTY_CYCLE_RX_END (1ULL << RAIL_EVENT_RX_DUTY_CYCLE_RX_END_SHIFT) + +/** + * Indicate a Data Request is received when using IEEE 802.15.4 + * functionality. + * + * It occurs when the command byte of an incoming ACK-requesting MAC Control + * frame is for a data request. This callback is called before + * the packet is fully received to allow the node to have more time to decide + * whether to indicate a frame is pending in the outgoing ACK. This event only + * occurs if the RAIL IEEE 802.15.4 functionality is enabled, but will never + * occur if promiscuous mode is enabled via + * RAIL_IEEE802154_SetPromiscuousMode(). + * + * Call RAIL_IEEE802154_GetAddress() to get the source address of the packet. + */ +#define RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND (1ULL << RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND_SHIFT) + +/** + * Indicate a Z-Wave Beam Request relevant to the node was received. + * + * This event only occurs if the RAIL Z-Wave functionality is enabled + * and its \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. + * This event is used in lieu of \ref RAIL_EVENT_RX_PACKET_RECEIVED, + * which is reserved for Z-Wave packets other than Beams. + * + * Call RAIL_ZWAVE_GetBeamNodeId() to get the NodeId to which the Beam was + * targeted, which would be either the broadcast id 0xFF or the node's own + * single-cast id. + * + * @note All Z-Wave Beam requests are generally discarded, triggering + * \ref RAIL_EVENT_RX_PACKET_ABORTED. + */ +#define RAIL_EVENT_ZWAVE_BEAM (1ULL << RAIL_EVENT_ZWAVE_BEAM_SHIFT) + +/** + * Indicate a MFM buffer has completely transmitted. + * + * This event only occurs if the RAIL MFM functionality is enabled + * and a MFM buffer has completely transmitted. + * + * Following this event, the application can update the MFM buffer + * that has transmitted to be used for the next transmission. + */ +#define RAIL_EVENT_MFM_TX_BUFFER_DONE (1ULL << RAIL_EVENT_MFM_TX_BUFFER_DONE_SHIFT) + +/** + * Indicate a request for populating Z-Wave LR ACK packet. + * This event only occurs if the RAIL Z-Wave functionality is enabled. + * + * Following this event, the application must call \ref RAIL_ZWAVE_SetLrAckData() + * to populate noise floor, TX power and receive RSSI fields of the Z-Wave + * Long Range ACK packet. + */ +#define RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND (1ULL << RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND_SHIFT) + +/** + * The mask representing all events that determine the end of a received + * packet. + * + * After a \ref RAIL_EVENT_RX_SYNC1_DETECT or a + * \ref RAIL_EVENT_RX_SYNC2_DETECT, + * exactly one of the following events will occur. When one of these events + * occurs, a state transition will take place based on the parameter passed to + * RAIL_SetRxTransitions(). The RAIL_StateTransitions_t::success transition + * will be followed only if the \ref RAIL_EVENT_RX_PACKET_RECEIVED event occurs. + * Any of the other events will trigger the RAIL_StateTransitions_t::error + * transition. + */ +#define RAIL_EVENTS_RX_COMPLETION (RAIL_EVENT_RX_PACKET_RECEIVED \ + | RAIL_EVENT_RX_PACKET_ABORTED \ + | RAIL_EVENT_RX_FRAME_ERROR \ + | RAIL_EVENT_RX_FIFO_OVERFLOW \ + | RAIL_EVENT_RX_ADDRESS_FILTERED \ + | RAIL_EVENT_RX_SCHEDULED_RX_MISSED) + +// TX Event Bitmasks + +/** + * Occurs when the number of bytes in the transmit FIFO falls below the + * configured threshold value. + * + * This event does not occur on initialization or after resetting the transmit + * FIFO with RAIL_ResetFifo(). + * + * Call RAIL_GetTxFifoSpaceAvailable() to get the + * number of bytes available in the transmit FIFO at the time of the callback + * dispatch. When using this event, the threshold should be set via + * RAIL_SetTxFifoThreshold(). + */ +#define RAIL_EVENT_TX_FIFO_ALMOST_EMPTY (1ULL << RAIL_EVENT_TX_FIFO_ALMOST_EMPTY_SHIFT) + +/** + * Occurs after a packet has been transmitted. + * + * Call RAIL_GetTxPacketDetails() + * to get information about the packet that was transmitted. + * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame + * of the RAIL_Config_t::eventsCallback. + */ +#define RAIL_EVENT_TX_PACKET_SENT (1ULL << RAIL_EVENT_TX_PACKET_SENT_SHIFT) + +/** + * Occurs after an ACK packet has been transmitted. + * + * Call RAIL_GetTxPacketDetails() + * to get information about the packet that was transmitted. This event can only occur + * after calling RAIL_ConfigAutoAck(). + * @note RAIL_GetTxPacketDetails() is only valid to call during the time frame + * of the RAIL_Config_t::eventsCallback. + */ +#define RAIL_EVENT_TXACK_PACKET_SENT (1ULL << RAIL_EVENT_TXACK_PACKET_SENT_SHIFT) + +/** + * Occurs when a transmit is aborted by the user. + * + * This can happen due to calling RAIL_Idle() or due to a scheduler + * preemption. + * + * @note The Transmit FIFO is left in an indeterminate state and should be + * reset prior to reuse for sending a new packet. Contrast this + * with \ref RAIL_EVENT_TX_BLOCKED. + */ +#define RAIL_EVENT_TX_ABORTED (1ULL << RAIL_EVENT_TX_ABORTED_SHIFT) + +/** + * Occurs when an ACK transmit is aborted by the user. + * + * This event can only + * occur after calling RAIL_ConfigAutoAck(), which can happen due to calling + * RAIL_Idle() or due to a scheduler preemption. + */ +#define RAIL_EVENT_TXACK_ABORTED (1ULL << RAIL_EVENT_TXACK_ABORTED_SHIFT) + +/** + * Occurs when a transmit is blocked from occurring because + * RAIL_EnableTxHoldOff() was called. + * + * @note Since the transmit never started, the Transmit FIFO remains intact + * after this event -- no packet data was consumed from it. Contrast this + * with \ref RAIL_EVENT_TX_ABORTED. + */ +#define RAIL_EVENT_TX_BLOCKED (1ULL << RAIL_EVENT_TX_BLOCKED_SHIFT) + +/** + * Occurs when an ACK transmit is blocked from occurring because + * RAIL_EnableTxHoldOff() was called. + * + * This event can only occur after calling RAIL_ConfigAutoAck(). + */ +#define RAIL_EVENT_TXACK_BLOCKED (1ULL << RAIL_EVENT_TXACK_BLOCKED_SHIFT) + +/** + * Occurs when the transmit buffer underflows. + * + * This can happen due to the + * transmitted packet specifying an unintended length based on the current + * radio configuration or due to RAIL_WriteTxFifo() calls not keeping up with + * the transmit rate if the entire packet isn't loaded at once. + * + * @note The Transmit FIFO is left in an indeterminate state and should be + * reset prior to reuse for sending a new packet. Contrast this + * with \ref RAIL_EVENT_TX_BLOCKED. + */ +#define RAIL_EVENT_TX_UNDERFLOW (1ULL << RAIL_EVENT_TX_UNDERFLOW_SHIFT) + +/** + * Occurs when the ACK transmit buffer underflows. + * + * This can happen due to the + * transmitted packet specifying an unintended length based on the current + * radio configuration or due to RAIL_WriteAutoAckFifo() not being called at + * all before an ACK transmit. + * + * This event can only occur after calling RAIL_ConfigAutoAck(). + */ +#define RAIL_EVENT_TXACK_UNDERFLOW (1ULL << RAIL_EVENT_TXACK_UNDERFLOW_SHIFT) + +/** + * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) + * succeeds. + * + * This event can only happen after calling RAIL_StartCcaCsmaTx() or + * RAIL_StartCcaLbtTx(). + */ +#define RAIL_EVENT_TX_CHANNEL_CLEAR (1ULL << RAIL_EVENT_TX_CHANNEL_CLEAR_SHIFT) + +/** + * Occurs when Carrier Sense Multiple Access (CSMA) or Listen Before Talk (LBT) + * fails. + * + * This event can only happen after calling RAIL_StartCcaCsmaTx() or + * RAIL_StartCcaLbtTx(). + * + * @note Since the transmit never started, the Transmit FIFO remains intact + * after this event -- no packet data was consumed from it. + */ +#define RAIL_EVENT_TX_CHANNEL_BUSY (1ULL << RAIL_EVENT_TX_CHANNEL_BUSY_SHIFT) + +/** + * Occurs during CSMA or LBT when an individual Clear Channel Assessment (CCA) + * check fails, but there are more tries needed before the overall operation + * completes. + * + * This event can occur multiple times based on the configuration + * of the ongoing CSMA or LBT transmission. It can only happen after + * calling RAIL_StartCcaCsmaTx() or RAIL_StartCcaLbtTx(). + */ +#define RAIL_EVENT_TX_CCA_RETRY (1ULL << RAIL_EVENT_TX_CCA_RETRY_SHIFT) + +/** + * Occurs when the receiver is activated to perform a Clear Channel Assessment + * (CCA) check. + * + * This event generally precedes the actual start of a CCA check by roughly + * the \ref RAIL_StateTiming_t::idleToRx time (subject to + * \ref RAIL_MINIMUM_TRANSITION_US). It can + * occur multiple times based on the configuration of the ongoing CSMA or LBT + * transmission. It can only happen after calling RAIL_StartCcaCsmaTx() + * or RAIL_StartCcaLbtTx(). + */ +#define RAIL_EVENT_TX_START_CCA (1ULL << RAIL_EVENT_TX_START_CCA_SHIFT) + +/** + * Occurs when the radio starts transmitting a normal packet on the air. + * + * A start-of-transmit timestamp is captured for this event. It can be + * retrieved by calling \ref RAIL_GetTxTimePreambleStart() passing \ref + * RAIL_TX_STARTED_BYTES for its totalPacketBytes parameter. + * + * @note This event does not apply to ACK transmits. Currently there + * is no equivalent event or timestamp captured for the start of an + * ACK transmit. + */ +#define RAIL_EVENT_TX_STARTED (1ULL << RAIL_EVENT_TX_STARTED_SHIFT) + +/** + * A value to pass as \ref RAIL_GetTxTimePreambleStart() totalPacketBytes + * parameter to retrieve the \ref RAIL_EVENT_TX_STARTED timestamp. + */ +#define RAIL_TX_STARTED_BYTES 0U + +/** + * Occurs when the start of a scheduled transmit is missed + * + * This can occur if the radio is put to sleep and not woken up with enough time + * to configure the scheduled transmit event. + * + * @note Since the transmit never started, the Transmit FIFO remains intact + * after this event -- no packet data was consumed from it. + */ +#define RAIL_EVENT_TX_SCHEDULED_TX_MISSED (1ULL << RAIL_EVENT_TX_SCHEDULED_TX_MISSED_SHIFT) + +/** + * A mask representing all events that determine the end of a transmitted + * packet. After a \ref RAIL_STATUS_NO_ERROR return value + * from one of the transmit functions, exactly one of the following + * events will occur. When one of these events occurs, a state transition + * takes place based on the parameter passed to RAIL_SetTxTransitions(). + * The RAIL_StateTransitions_t::success transition will be followed only + * if the \ref RAIL_EVENT_TX_PACKET_SENT event occurs. Any of the other + * events will trigger the RAIL_StateTransitions_t::error transition. + */ +#define RAIL_EVENTS_TX_COMPLETION (RAIL_EVENT_TX_PACKET_SENT \ + | RAIL_EVENT_TX_ABORTED \ + | RAIL_EVENT_TX_BLOCKED \ + | RAIL_EVENT_TX_UNDERFLOW \ + | RAIL_EVENT_TX_CHANNEL_BUSY \ + | RAIL_EVENT_TX_SCHEDULED_TX_MISSED) + +/** + * A mask representing all events that determine the end of a transmitted + * ACK packet. After an ACK-requesting receive, exactly one of the + * following events will occur. When one of these events occurs, a state + * transition takes place based on the RAIL_AutoAckConfig_t::rxTransitions + * passed to RAIL_ConfigAutoAck(). The receive transitions are used because the + * transmitted ACK packet is considered a part of the ACK-requesting received + * packet. The RAIL_StateTransitions_t::success transition will be followed + * only if the \ref RAIL_EVENT_TXACK_PACKET_SENT event occurs. Any of the other + * events will trigger the RAIL_StateTransitions_t::error transition. + */ +#define RAIL_EVENTS_TXACK_COMPLETION (RAIL_EVENT_TXACK_PACKET_SENT \ + | RAIL_EVENT_TXACK_ABORTED \ + | RAIL_EVENT_TXACK_BLOCKED \ + | RAIL_EVENT_TXACK_UNDERFLOW) + +// Scheduler Event Bitmasks + +/** + * Occurs when the scheduler switches away from this configuration. + * + * This event will occur in dynamic multiprotocol scenarios each + * time a protocol is shutting down. When it does occur, it will be + * the only event passed to RAIL_Config_t::eventsCallback. Therefore, + * to optimize protocol switch time, this event should be handled + * among the first in that callback, and then the application can return + * immediately. + * + * @note: To minimize protocol switch time, Silicon Labs recommends this event + * event being turned off unless it is used. + */ +#define RAIL_EVENT_CONFIG_UNSCHEDULED (1ULL << RAIL_EVENT_CONFIG_UNSCHEDULED_SHIFT) + +/** + * Occurs when the scheduler switches to this configuration. + * + * This event will occur in dynamic multiprotocol scenarios each time + * a protocol is starting up. When it does occur, it will + * be the only event passed to RAIL_Config_t::eventsCallback. Therefore, in + * order to optimize protocol switch time, this event should be handled among + * the first in that callback, and then the application can return immediately. + * + * @note: To minimize protocol switch time, Silicon Labs recommends this event + * event being turned off unless it is used. + */ +#define RAIL_EVENT_CONFIG_SCHEDULED (1ULL << RAIL_EVENT_CONFIG_SCHEDULED_SHIFT) + +/** + * Occurs when the scheduler has a status to report. + * + * The exact status can be found with RAIL_GetSchedulerStatus(). + * See \ref RAIL_SchedulerStatus_t for more details. When this event + * does occur, it will be the only event passed to RAIL_Config_t::eventsCallback. + * Therefore, to optimize protocol switch time, this event should + * be handled among the first in that callback, and then the application + * can return immediately. + * + * @note RAIL_GetSchedulerStatus() is only valid to call during the time frame + * of the RAIL_Config_t::eventsCallback. + * + * @note: To minimize protocol switch time, Silicon Labs recommends this event + * event being turned off unless it is used. + */ +#define RAIL_EVENT_SCHEDULER_STATUS (1ULL << RAIL_EVENT_SCHEDULER_STATUS_SHIFT) + +// Other Event Bitmasks + +/** + * Occurs when the application needs to run a calibration, as + * determined by the RAIL library. + * + * The application determines the opportune time to call RAIL_Calibrate(). + */ +#define RAIL_EVENT_CAL_NEEDED (1ULL << RAIL_EVENT_CAL_NEEDED_SHIFT) + +/** + * Occurs when RF energy is sensed from the radio. This event can be used as + * an alternative to the callback passed as \ref RAIL_RfSense_CallbackPtr_t. + * + * Alternatively, the application can poll using \ref RAIL_IsRfSensed(). + * + * @note This event will not occur when waking up from EM4. Prefer + * \ref RAIL_IsRfSensed() when waking from EM4. + */ +#define RAIL_EVENT_RF_SENSED (1ULL << RAIL_EVENT_RF_SENSED_SHIFT) + +/** + * Occurs when PA protection circuit kicks in. + */ +#define RAIL_EVENT_PA_PROTECTION (1ULL << RAIL_EVENT_PA_PROTECTION_SHIFT) + +/** + * Occurs after enabling the signal detection using \ref RAIL_BLE_EnableSignalDetection + * or \ref RAIL_IEEE802154_EnableSignalDetection when a signal is detected. + * This is only used on platforms that support signal identifier, where + * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER or + * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER is true. + */ +#define RAIL_EVENT_SIGNAL_DETECTED (1ULL << RAIL_EVENT_SIGNAL_DETECTED_SHIFT) + +/** + * Occurs when a Wi-SUN mode switch packet has been received, after switching to the new PHY. + * + * It doesn't occur when a mode switch packet is transmitted. + * + * IEEE 802.15.4 option \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH must be enabled for this event to occur. + * + * Only available on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. + */ +#define RAIL_EVENT_IEEE802154_MODESWITCH_START (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_START_SHIFT) + +/** + * Occurs when switching back to the original base PHY in effect prior to the Wi-SUN mode switch reception. + * + * This typically occurs if no packet is seen within some timeframe after the mode switch packet was received + * or if the first packet received in the new PHY is aborted, filtered, or fails CRC. + * + * IEEE 802.15.4 option \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH must be enabled for this event to occur. + * + * Only available on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. + */ +#define RAIL_EVENT_IEEE802154_MODESWITCH_END (1ULL << RAIL_EVENT_IEEE802154_MODESWITCH_END_SHIFT) + +/** + * Occurs when the sampled RSSI is above the threshold set by + * \ref RAIL_SetRssiDetectThreshold(). + */ +#define RAIL_EVENT_DETECT_RSSI_THRESHOLD (1ULL << RAIL_EVENT_DETECT_RSSI_THRESHOLD_SHIFT) + +/** + * Occurs when the thermistor has finished its measurement in response to + * \ref RAIL_StartThermistorMeasurement(). + */ +#define RAIL_EVENT_THERMISTOR_DONE (1ULL << RAIL_EVENT_THERMISTOR_DONE_SHIFT) + +/** + * Occurs when a Tx has been blocked because of temperature exceeding + * the safety threshold. + * + * Only occurs on platforms where \ref RAIL_SUPPORTS_EFF is true, + * and only when also reporting \ref RAIL_EVENT_TX_BLOCKED. + */ +#define RAIL_EVENT_TX_BLOCKED_TOO_HOT (1ULL << RAIL_EVENT_TX_BLOCKED_TOO_HOT_SHIFT) + +/** + * Occurs when die internal temperature exceeds the temperature threshold subtracted + * by the cool down parameter from \ref RAIL_ChipTempConfig_t. + * Transmits are blocked until temperature has cooled enough, indicated by + * \ref RAIL_EVENT_TEMPERATURE_COOL_DOWN. + * + * Only occurs on platforms where \ref RAIL_SUPPORTS_THERMAL_PROTECTION is true. + */ +#define RAIL_EVENT_TEMPERATURE_TOO_HOT (1ULL << RAIL_EVENT_TEMPERATURE_TOO_HOT_SHIFT) + +/** + * Occurs when die internal temperature falls below the temperature threshold subtracted + * by the cool down parameter from \ref RAIL_ChipTempConfig_t. + * Transmits are no longer blocked by temperature limitation, indicated by + * \ref RAIL_EVENT_TEMPERATURE_TOO_HOT. + * + * Only occurs on platforms where \ref RAIL_SUPPORTS_THERMAL_PROTECTION is true. + */ +#define RAIL_EVENT_TEMPERATURE_COOL_DOWN (1ULL << RAIL_EVENT_TEMPERATURE_COOL_DOWN_SHIFT) + +/** A value representing all possible events */ +#define RAIL_EVENTS_ALL 0xFFFFFFFFFFFFFFFFULL + +/** @} */ // end of group Events + +/****************************************************************************** + * General Structures (part 2) + *****************************************************************************/ +/** + * @addtogroup General + * @{ + */ + +/** + * @struct RAIL_Config_t + * @brief RAIL configuration structure. + */ +typedef struct RAIL_Config { + /** + * A pointer to a function, which is called whenever a RAIL event occurs. + * + * @param[in] railHandle A handle for a RAIL instance. + * @param[in] events A bit mask of RAIL events. + * + * See the \ref RAIL_Events_t documentation for the list of RAIL events. + */ + void (*eventsCallback)(RAIL_Handle_t railHandle, RAIL_Events_t events); + /** + * Provided for backwards compatibility. Ignored. + */ + void *protocol; + /** + * Provided for backwards compatibility. Ignored. + */ + RAILSched_Config_t *scheduler; + /** + * Provided for backwards compatibility. Ignored. + */ + RAIL_StateBuffer_t buffer; +} RAIL_Config_t; + +/** @} */ // end of group General + +/****************************************************************************** + * PA Power Amplifier Structures + *****************************************************************************/ +/** + * @addtogroup PA Power Amplifier (PA) + * @ingroup Transmit + * @{ + */ + +/** + * The transmit power in deci-dBm units (e.g., 4.5 dBm -> 45 deci-dBm). These + * values are used by the conversion functions to convert a \ref + * RAIL_TxPowerLevel_t to deci-dBm for the application consumption. On EFR32, + * they can range from \ref RAIL_TX_POWER_MIN to \ref RAIL_TX_POWER_MAX. + */ +typedef int16_t RAIL_TxPower_t; + +/** The maximum valid value for a \ref RAIL_TxPower_t. */ +#define RAIL_TX_POWER_MAX ((RAIL_TxPower_t)0x7FFF) +/** The minimum valid value for a \ref RAIL_TxPower_t. */ +#define RAIL_TX_POWER_MIN ((RAIL_TxPower_t)0x8000) + +/** The maximum power in deci-dBm the curve supports */ +#define RAIL_TX_POWER_CURVE_DEFAULT_MAX ((RAIL_TxPower_t)200) +/** The increment step in deci-dBm for calculating power level*/ +#define RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT ((RAIL_TxPower_t)40) + +/// mV are used for all TX power voltage values. +/// TX power voltages take and return voltages multiplied by this factor. +#define RAIL_TX_POWER_VOLTAGE_SCALING_FACTOR 1000 + +/// deci-dBm are used for all TX power dBm values. +/// All dBm inputs to TX power functions take dBm power times this factor. +#define RAIL_TX_POWER_DBM_SCALING_FACTOR 10 + +/** + * Raw power levels used directly by the RAIL_Get/SetTxPower API where a higher + * numerical value corresponds to a higher output power. These are referred to + * as 'raw (values/units)'. On EFR32, they can range from one of \ref + * RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MIN, or + * \ref RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN to one of \ref + * RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ref RAIL_TX_POWER_LEVEL_2P4_HP_MAX, and \ref + * RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, respectively, depending on the selected \ref + * RAIL_TxPowerMode_t. + */ +typedef uint8_t RAIL_TxPowerLevel_t; + +/** + * Invalid RAIL_TxPowerLevel_t value returned when an error occurs + * with RAIL_GetTxPower. + */ +#define RAIL_TX_POWER_LEVEL_INVALID (255U) + +/** + * Sentinel value that can be passed to RAIL_SetTxPower to set + * the highest power level available on the current PA, regardless + * of which one is selected. + */ +#define RAIL_TX_POWER_LEVEL_MAX (254U) + +/** + * PA power setting used directly by the \ref RAIL_GetPaPowerSetting() and + * \ref RAIL_SetPaPowerSetting() APIs which is decoded to the actual + * hardware register value(s). + */ +typedef uint32_t RAIL_PaPowerSetting_t; + +/** + * Returned by \ref RAIL_GetPaPowerSetting when the device does + * not support the dBm to power setting mapping table. + */ +#define RAIL_TX_PA_POWER_SETTING_UNSUPPORTED (0U) + +/** + * @enum RAIL_TxPowerMode_t + * @brief An enumeration of the EFR32 power modes. + * + * The power modes on the EFR32 correspond to the different on-chip PAs that + * are available. For more information about the power and performance + * characteristics of a given amplifier, see the data sheet. + */ +RAIL_ENUM(RAIL_TxPowerMode_t) { + /** + * High-power 2.4 GHz amplifier + * EFR32xG1X: up to 20 dBm, raw values: 0-252 + * EFR32xG21: up to 20 dBm, raw values: 1-180 + * EFR32xG22: up to 6 dBm, raw values: 1-128 + * EFR32xG24: up to 20 dBm, raw values: 0-180, or + * up to 10 dBm, raw values: 0-90 + * EFR32xG26: same as EFR32xG24 + * EFR32xG27: up to 6 dBm, raw values: 1-128 + * EFR32xG28: up to 10 dBm, raw values: 0-240 + * Not supported on other platforms. + */ + RAIL_TX_POWER_MODE_2P4GIG_HP = 0U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HP instead. */ + RAIL_TX_POWER_MODE_2P4_HP = RAIL_TX_POWER_MODE_2P4GIG_HP, + /** + * Mid-power 2.4 GHz amplifier + * EFR32xG21: up to 10 dBm, raw values: 1-90 + * Not supported on other platforms. + */ + RAIL_TX_POWER_MODE_2P4GIG_MP = 1U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_MP instead. */ + RAIL_TX_POWER_MODE_2P4_MP = RAIL_TX_POWER_MODE_2P4GIG_MP, + /** + * Low-power 2.4 GHz amplifier + * EFR32xG1x: up to 0 dBm, raw values: 1-7 + * EFR32xG21: up to 0 dBm, raw values: 1-64 + * EFR32xG22: up to 0 dBm, raw values: 1-16 + * EFR32xG24: up to 0 dBm, raw values: 1-16 + * EFR32xG26: same as EFR32xG24 + * EFR32xG27: up to 0 dBm, raw values: 1-16 + * Not supported on other platforms. + */ + RAIL_TX_POWER_MODE_2P4GIG_LP = 2U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_LP instead. */ + RAIL_TX_POWER_MODE_2P4_LP = RAIL_TX_POWER_MODE_2P4GIG_LP, + /** + * Low-Low-power 2.4 GHz amplifier + * Not currently supported on any EFR32 platform. + */ + RAIL_TX_POWER_MODE_2P4GIG_LLP = 3U, + /** + * Select the highest 2.4 GHz power PA available on the current chip. + * Only supported on EFR32 Series-2 platforms and not Series-1. + */ + RAIL_TX_POWER_MODE_2P4GIG_HIGHEST = 4U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_2P4GIG_HIGHEST instead. */ + RAIL_TX_POWER_MODE_2P4_HIGHEST = RAIL_TX_POWER_MODE_2P4GIG_HIGHEST, + /** + * PA for all Sub-GHz dBm values in range, using \ref + * RAIL_PaPowerSetting_t table. + * Only supported on platforms with \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE (e.g. EFR32xG25). + */ + RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE = 5U, + /** + * High-power Sub-GHz amplifier (Class D mode) + * EFR32xG1x: up to 20 dBm, raw values: 0-248 + * Also supported on FR32xG23 and EFR32xG28. + * Not supported other Sub-GHz-incapable platforms or those with \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. + */ + RAIL_TX_POWER_MODE_SUBGIG_HP = 6U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_SUBGIG_HP instead. */ + RAIL_TX_POWER_MODE_SUBGIG = RAIL_TX_POWER_MODE_SUBGIG_HP, + /** + * Mid-power Sub-GHz amplifier + * Supported only on EFR32xG23 and EFR32xG28. + * Not supported other Sub-GHz-incapable platforms or those with \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. + */ + RAIL_TX_POWER_MODE_SUBGIG_MP = 7U, + /** + * Low-power Sub-GHz amplifier + * Supported only on EFR32xG23 and EFR32xG28. + * Not supported other Sub-GHz-incapable platforms or those with \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. + */ + RAIL_TX_POWER_MODE_SUBGIG_LP = 8U, + /** + * Low-Low-power Sub-GHz amplifier + * Supported only on EFR32xG23 and EFR32xG28. + * Not supported other Sub-GHz-incapable platforms or those with \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE. + */ + RAIL_TX_POWER_MODE_SUBGIG_LLP = 9U, + /** + * Select the highest Sub-GHz power PA available on the current chip. + * Only supported on EFR32 Series-2 platforms and not Series-1. + */ + RAIL_TX_POWER_MODE_SUBGIG_HIGHEST = 10U, + /** + * PA for all OFDM Sub-GHz dBm values in range, using \ref + * RAIL_PaPowerSetting_t table. + * Supported only on platforms with both \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE and \ref + * RAIL_SUPPORTS_OFDM_PA (e.g. EFR32xG25). + */ + RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE = 11U, + /** @deprecated Please use \ref RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE instead. */ + RAIL_TX_POWER_MODE_OFDM_PA = RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE, +#ifndef DOXYGEN_SHOULD_SKIP_THIS + /** + * PA for all Sub-GHz dBm values in range for Front-End-Module, using \ref + * RAIL_PaPowerSetting_t table. + * Supported only on platforms with both + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE and \ref + * RAIL_SUPPORTS_EFF. + */ + RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE = 12U, + /** + * PA for all OFDM Sub-GHz dBm values in range for Front-End-Module, using \ref + * RAIL_PaPowerSetting_t table. + * Supported only on platforms with all of \ref + * RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE, \ref + * RAIL_SUPPORTS_OFDM_PA, and \ref + * RAIL_SUPPORTS_EFF. + */ + RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE = 13U, +#endif//DOXYGEN_SHOULD_SKIP_THIS + /** Invalid amplifier Selection */ + RAIL_TX_POWER_MODE_NONE // Must be last +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +// Refer to rail_chip_specific.h for per-platform defines of supported ones. +#define RAIL_TX_POWER_MODE_NONE ((RAIL_TxPowerMode_t) RAIL_TX_POWER_MODE_NONE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_TX_POWER_MODE_NAMES + * @brief The names of the TX power modes + * + * A list of the names for the TX power modes on EFR32 parts. This + * macro is useful for test applications and debugging output. + */ +#define RAIL_TX_POWER_MODE_NAMES { \ + "RAIL_TX_POWER_MODE_2P4GIG_HP", \ + "RAIL_TX_POWER_MODE_2P4GIG_MP", \ + "RAIL_TX_POWER_MODE_2P4GIG_LP", \ + "RAIL_TX_POWER_MODE_2P4GIG_LLP", \ + "RAIL_TX_POWER_MODE_2P4GIG_HIGHEST", \ + "RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE", \ + "RAIL_TX_POWER_MODE_SUBGIG_HP", \ + "RAIL_TX_POWER_MODE_SUBGIG_MP", \ + "RAIL_TX_POWER_MODE_SUBGIG_LP", \ + "RAIL_TX_POWER_MODE_SUBGIG_LLP", \ + "RAIL_TX_POWER_MODE_SUBGIG_HIGHEST", \ + "RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE", \ + "RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE", \ + "RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE", \ + "RAIL_TX_POWER_MODE_NONE" \ +} + +/** + * @struct RAIL_TxPowerConfig_t + * + * @brief A structure containing values used to initialize the power amplifiers. + */ +typedef struct RAIL_TxPowerConfig { + /** TX power mode */ + RAIL_TxPowerMode_t mode; + /** Power amplifier supply voltage in mV, generally: + * DCDC supply ~ 1800 mV (1.8 V) + * Battery supply ~ 3300 mV (3.3 V) + */ + uint16_t voltage; + /** The amount of time to spend ramping for TX in uS. */ + uint16_t rampTime; +} RAIL_TxPowerConfig_t; + +/** Convenience macro for any EFF power mode. */ +#define RAIL_POWER_MODE_IS_ANY_EFF(x) \ + (((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)) +/** Convenience macro for any OFDM mapping table mode. */ +#define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) \ + (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE)) +/** Convenience macro for any Sub-GHz mapping table mode. */ +#define RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_SUBGIG(x) \ + (((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE)) +/** Convenience macro for any mapping table mode. */ +#define RAIL_POWER_MODE_IS_ANY_DBM_POWERSETTING_MAPPING_TABLE(x) \ + (((x) == RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_OFDM_PA_EFF_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_SUBGIG_POWERSETTING_TABLE) \ + || ((x) == RAIL_TX_POWER_MODE_SUBGIG_EFF_POWERSETTING_TABLE)) +/** Convenience macro for any OFDM mode. */ +#define RAIL_POWER_MODE_IS_ANY_OFDM(x) \ + RAIL_POWER_MODE_IS_DBM_POWERSETTING_MAPPING_TABLE_OFDM(x) + +/** @} */ // PA Power Amplifier (PA) + +/****************************************************************************** + * Radio Configuration Structures + *****************************************************************************/ +/** + * @addtogroup Radio_Configuration + * @{ + */ + +/** + * @brief Pointer to a radio configuration array. + * + * The radio configuration properly configures the + * radio for operation on a protocol. These configurations are very + * chip-specific should not be created or edited by hand. + */ +typedef const uint32_t *RAIL_RadioConfig_t; + +/** + * @struct RAIL_FrameType_t + * @brief Configures if there is a frame type in your frame and the lengths of + * each frame. The number of bits set in the mask determines the number of + * elements in frameLen. A maximum of 8 different frame types may be specified. + */ +typedef struct RAIL_FrameType { + /** + * A pointer to an array of frame lengths for each frame type. The length of this + * array should be equal to the number of frame types. The array that + * frameLen points to should not change location or be modified. + */ + uint16_t *frameLen; + /** + * Zero-indexed location of the byte containing the frame type field. + */ + uint8_t offset; + /** + * A bitmask of the frame type field, which determines a number of frames expected + * based on the number of bits set. No more than 3 bits can be set in the mask and + * they must be contiguous ones. For example, if the highest three bits of the byte + * specified by offset constitute the frame type, then mask should be 0xE0, + * which has 3 bits set, indicating 8 possible frame types. + */ + uint8_t mask; + /** + * A bitmask that marks if each frame is valid or should be filtered. Frame type + * 0 corresponds to the lowest bit in isValid. If the frame is filtered, a + * RAIL_EVENT_RX_PACKET_ABORTED will be raised. + */ + uint8_t isValid; + /** + * A bitmask that marks if each frame should have the address filter applied. + * Frame type 0 corresponds to the least significant bit in addressFilter. + */ + uint8_t addressFilter; +} RAIL_FrameType_t; + +/** + * @def RAIL_SETFIXEDLENGTH_INVALID + * @brief An invalid return value when calling RAIL_SetFixedLength(). + * + * An invalid return value when calling RAIL_SetFixedLength() while the radio is + * not in fixed-length mode. + */ +#define RAIL_SETFIXEDLENGTH_INVALID (0xFFFFU) + +/** + * @struct RAIL_ChannelConfigEntryAttr_t + * @brief A channel configuration entry attribute structure. Items listed + * are designed to be altered and updated during run-time. + */ +typedef struct RAIL_ChannelConfigEntryAttr RAIL_ChannelConfigEntryAttr_t; + +/** + * @enum RAIL_ChannelConfigEntryType_t + * @brief Define if the channel support using concurrent PHY during channel + * hopping. RAIL_RX_CHANNEL_HOPPING_MODE_CONC and RAIL_RX_CHANNEL_HOPPING_MODE_VT + * can only be used if the channel supports it. + */ +RAIL_ENUM(RAIL_ChannelConfigEntryType_t) { + RAIL_CH_TYPE_NORMAL, /**< Not a concurrent PHY. */ + RAIL_CH_TYPE_CONC_BASE, /**< Base concurrent PHY. */ + RAIL_CH_TYPE_CONC_VIRTUAL, /**< Virtual concurrent PHY. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_CH_TYPE_NORMAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_NORMAL) +#define RAIL_CH_TYPE_CONC_BASE ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_BASE) +#define RAIL_CH_TYPE_CONC_VIRTUAL ((RAIL_ChannelConfigEntryType_t) RAIL_CH_TYPE_CONC_VIRTUAL) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RADIO_CONFIG_ENABLE_CONC_PHY + * @brief Indicates this version of RAIL supports concurrent PHY information in + * radio configurator output. Needed for backwards compatibility. + */ +#define RADIO_CONFIG_ENABLE_CONC_PHY 1 + +/** + * @def RADIO_CONFIG_ENABLE_STACK_INFO + * @brief Indicates this version of RAIL supports stack info feature in + * radio configurator output. Needed for backwards compatibility. + */ +#define RADIO_CONFIG_ENABLE_STACK_INFO + +/** + * @struct RAIL_AlternatePhy_t + * @brief Alternate PHY configuration entry structure, which gathers some info + * on the alternate PHY in the context of concurrent mode. + */ +typedef struct RAIL_AlternatePhy { + uint32_t baseFrequency; /**< A base frequency in Hz of this channel set. */ + uint32_t channelSpacing; /**< A channel spacing in Hz of this channel set. */ + uint16_t numberOfChannels; /**< The number of channels (and not the channel number !) */ + uint16_t minIf_kHz; /**< minimum IF for the alternate PHY in kHz. */ + uint16_t minBaseIf_kHz; /**< minimum IF for the base PHY in kHz. */ + bool isOfdmModem; /**< Indicates that OFDM modem is used by this alternate PHY. */ + uint32_t rateInfo; /**< rate Info of the alternate PHY. */ +} RAIL_AlternatePhy_t; + +/** + * @struct RAIL_ChannelConfigEntry_t + * @brief A channel configuration entry structure, which defines a channel range + * and parameters across which a corresponding radio configuration is valid. + * + * operating frequency = baseFrequency + * + channelSpacing * (channel - physicalChannelOffset); + */ +typedef struct RAIL_ChannelConfigEntry { + RAIL_RadioConfig_t phyConfigDeltaAdd; /**< The minimum radio configuration to apply to the base + configuration for this channel set. */ + uint32_t baseFrequency; /**< A base frequency in Hz of this channel set. */ + uint32_t channelSpacing; /**< A channel spacing in Hz of this channel set. */ + uint16_t physicalChannelOffset; /**< The offset to subtract from the logical + channel to align them with the zero + based physical channels which are + relative to baseFrequency. + (i.e., By default ch 0 = base freq, but + if offset = 11, ch 11 = base freq.) */ + uint16_t channelNumberStart; /**< The first valid RAIL channel number for this + channel set. */ + uint16_t channelNumberEnd; /**< The last valid RAIL channel number for this + channel set. */ + RAIL_TxPower_t maxPower; /**< The maximum power allowed in this channel set. */ + RAIL_ChannelConfigEntryAttr_t *attr; /**< A pointer to a structure containing + attributes specific to this + channel set. */ + RAIL_ChannelConfigEntryType_t entryType; /**< Indicates channel config type. */ + uint8_t reserved[3]; /**< to align to 32-bit boundary. */ + const uint8_t *stackInfo; /**< Array containing information according to the protocolId value, + first byte of this array. + The first 2 fields are common to all protocols and accessible by RAIL, + others are ignored by RAIL and only used by the application. + Common fields are listed in RAIL_StackInfoCommon_t. */ + RAIL_AlternatePhy_t *alternatePhy; /**< Pointer to alternate PHY. */ +} RAIL_ChannelConfigEntry_t; + +/// @struct RAIL_ChannelConfig_t +/// @brief A channel configuration structure, which defines the channel meaning +/// when a channel number is passed into a RAIL function, e.g., RAIL_StartTx() +/// and RAIL_StartRx(). +/// +/// A RAIL_ChannelConfig_t structure defines the channel scheme that an +/// application uses when registered in RAIL_ConfigChannels(). +/// +/// These are a few examples of different channel configurations: +/// @code{.c} +/// // 21 channels starting at 2.45 GHz with channel spacing of 1 MHz +/// // ... generated by Simplicity Studio (i.e., rail_config.c) ... +/// const uint32_t generated[] = { ... }; +/// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; +/// const RAIL_ChannelConfigEntry_t generated_channels[] = { +/// { +/// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated_entryAttr +/// }, +/// }; +/// const RAIL_ChannelConfig_t generated_channelConfig = { +/// .phyConfigBase = generated, // Default radio configuration for all entries +/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration +/// .configs = generated_channels, +/// .length = 1 // There are this many channel configuration entries +/// }; +/// const RAIL_ChannelConfig_t *channelConfigs[] = { +/// &generated_channelConfig, +/// NULL +/// }; +/// // ... in main code ... +/// // Associate a specific channel configuration with a particular RAIL instance. +/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); +/// +/// // 4 nonlinear channels +/// // ... in rail_config.c ... +/// const uint32_t generated[] = { ... }; +/// RAIL_ChannelConfigEntryAttr_t generated_entryAttr = { ... }; +/// const RAIL_ChannelConfigEntry_t generated_channels[] = { +/// { +/// .phyConfigDeltaAdd = NULL, // Add this to default configuration for this entry +/// .baseFrequency = 910123456, +/// .channelSpacing = 0, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 0, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated_entryAttr +/// }, +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 911654789, +/// .channelSpacing = 0, +/// .physicalChannelOffset = 0, // Since ch spacing = 0, offset can be 0 +/// .channelNumberStart = 1, +/// .channelNumberEnd = 1, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated_entryAttr +/// }, +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 912321456, +/// .channelSpacing = 100000, +/// .physicalChannelOffset = 2, // Since ch spacing != 0, offset = 2 +/// .channelNumberStart = 2, // ch 2 = baseFrequency +/// .channelNumberEnd = 2, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated_entryAttr +/// }, +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 913147852, +/// .channelSpacing = 0, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 3, +/// .channelNumberEnd = 3, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated_entryAttr +/// }, +/// }; +/// const RAIL_ChannelConfig_t generated_channelConfig = { +/// .phyConfigBase = generated, // Default radio configuration for all entries +/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore the default configuration +/// .configs = generated_channels, +/// .length = 4 // There are this many channel configuration entries +/// }; +/// const RAIL_ChannelConfig_t *channelConfigs[] = { +/// &generated_channelConfig, +/// NULL +/// }; +/// // ... in main code ... +/// // Associate a specific channel configuration with a particular RAIL instance. +/// RAIL_ConfigChannels(railHandle, channelConfigs[0]); +/// +/// // Multiple radio configurations +/// // ... in rail_config.c ... +/// const uint32_t generated0[] = { ... }; +/// RAIL_ChannelConfigEntryAttr_t generated0_entryAttr = { ... }; +/// const RAIL_ChannelConfigEntry_t generated0_channels[] = { +/// { +/// .phyConfigDeltaAdd = NULL, // Add this to the default configuration for this entry +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated0_entryAttr +/// }, +/// }; +/// const RAIL_ChannelConfig_t generated0_channelConfig = { +/// .phyConfigBase = generated0, // Default radio configuration for all entries +/// .phyConfigDeltaSubtract = NULL, // Subtract this to restore default configuration +/// .configs = generated0_channels, +/// .length = 1 // There are this many channel configuration entries +/// }; +/// const uint32_t generated1[] = { ... }; +/// RAIL_ChannelConfigEntryAttr_t generated1_entryAttr = { ... }; +/// const RAIL_ChannelConfigEntry_t generated1_channels[] = { +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = -100, // Use this entry when TX power <= -10dBm +/// .attr = &generated1_entryAttr +/// }, +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = 15, // Use this entry when TX power > -10dBm +/// // and TX power <= 1.5dBm +/// .attr = &generated1_entryAttr +/// }, +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = RAIL_TX_POWER_MAX, // Use this entry when TX power > 1.5dBm +/// .attr = &generated1_entryAttr +/// }, +/// }; +/// const RAIL_ChannelConfig_t generated1_channelConfig = { +/// .phyConfigBase = generated1, +/// .phyConfigDeltaSubtract = NULL, +/// .configs = generated1_channels, +/// .length = 3 +/// }; +/// const uint32_t generated2[] = { ... }; +/// RAIL_ChannelConfigEntryAttr_t generated2_entryAttr = { ... }; +/// const RAIL_ChannelConfigEntry_t generated2_channels[] = { +/// { +/// .phyConfigDeltaAdd = NULL, +/// .baseFrequency = 2450000000, +/// .channelSpacing = 1000000, +/// .physicalChannelOffset = 0, +/// .channelNumberStart = 0, +/// .channelNumberEnd = 20, +/// .maxPower = RAIL_TX_POWER_MAX, +/// .attr = &generated2_entryAttr +/// }, +/// }; +/// const RAIL_ChannelConfig_t generated2_channelConfig = { +/// .phyConfigBase = generated2, +/// .phyConfigDeltaSubtract = NULL, +/// .configs = generated2_channels, +/// .length = 1 +/// }; +/// const RAIL_ChannelConfig_t *channelConfigs[] = { +/// &generated0_channelConfig, +/// &generated1_channelConfig, +/// &generated2_channelConfig, +/// NULL +/// }; +/// // ... in main code ... +/// // Create a unique RAIL handle for each unique channel configuration. +/// railHandle0 = RAIL_Init(&railCfg0, &RAILCb_RfReady0); +/// railHandle1 = RAIL_Init(&railCfg1, &RAILCb_RfReady1); +/// railHandle2 = RAIL_Init(&railCfg2, &RAILCb_RfReady2); +/// // Associate each channel configuration with its corresponding RAIL handle. +/// RAIL_ConfigChannels(railHandle0, channelConfigs[0]); +/// RAIL_ConfigChannels(railHandle1, channelConfigs[1]); +/// RAIL_ConfigChannels(railHandle2, channelConfigs[2]); +/// // Use a RAIL handle and channel to access the desired channel configuration entry. +/// RAIL_SetTxPowerDbm(railHandle1, 100); // set 10.0 dBm TX power +/// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[2] +/// RAIL_SetTxPowerDbm(railHandle1, 0); // set 0 dBm TX power +/// RAIL_StartRx(railHandle1, 0, &schedInfo); // RX using generated1_channels[1] +/// RAIL_StartRx(railHandle2, 0, &schedInfo); // RX using generated2_channels[0] +/// @endcode + +typedef struct RAIL_ChannelConfig { + RAIL_RadioConfig_t phyConfigBase; /**< Base radio configuration for the corresponding + channel configuration entries. */ + RAIL_RadioConfig_t phyConfigDeltaSubtract; /**< Minimum radio configuration to restore + channel entries back to base + configuration. */ + const RAIL_ChannelConfigEntry_t *configs; /**< Pointer to an array of + RAIL_ChannelConfigEntry_t + entries. */ + uint32_t length; /**< Number of RAIL_ChannelConfigEntry_t entries. */ + uint32_t signature; /**< Signature for this structure. Only used on modules. */ + uint32_t xtalFrequencyHz; /**< Crystal Frequency for the channel config. */ +} RAIL_ChannelConfig_t; + +/** + * @struct RAIL_ChannelMetadata_t + * @brief Container for individual channel metadata. + */ +typedef struct RAIL_ChannelMetadata { + uint16_t channel; /**< Channel number */ + uint16_t reserved; /**< Word alignment */ + uint32_t frequency; /**< Channel frequency, in Hz */ +} RAIL_ChannelMetadata_t; + +/** + * @struct RAIL_StackInfoCommon_t + * @brief StackInfo fields common to all protocols. + */ +typedef struct RAIL_StackInfoCommon { + uint8_t protocolId; /**< Same as RAIL_PtiProtocol_t */ + uint8_t phyId; /**< PHY Id depending on the protocol_id value */ +} RAIL_StackInfoCommon_t; + +/** + * @typedef RAIL_RadioConfigChangedCallback_t + * @brief A pointer to a function called whenever a radio configuration change occurs. + * + * @param[in] railHandle A handle for RAIL instance. + * @param[in] entry The radio configuration entry being changed to. + */ +typedef void (*RAIL_RadioConfigChangedCallback_t)(RAIL_Handle_t railHandle, + const RAIL_ChannelConfigEntry_t *entry); + +/** @} */ // end of group Radio_Configuration + +/****************************************************************************** + * Packet Trace Interface (PTI) Structures + *****************************************************************************/ +/** + * @addtogroup PTI + * @{ + * + * These enumerations and structures are used with RAIL PTI API. EFR32 supports + * SPI and UART PTI and is configurable in terms of baud rates and PTI + * pin locations. + */ + +/** A channel type enumeration. */ +RAIL_ENUM(RAIL_PtiMode_t) { + /** Turn PTI off entirely. */ + RAIL_PTI_MODE_DISABLED, + /** 8-bit SPI mode. */ + RAIL_PTI_MODE_SPI, + /** 8-bit UART mode. */ + RAIL_PTI_MODE_UART, + /** 9-bit UART mode. */ + RAIL_PTI_MODE_UART_ONEWIRE, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_PTI_MODE_DISABLED ((RAIL_PtiMode_t) RAIL_PTI_MODE_DISABLED) +#define RAIL_PTI_MODE_SPI ((RAIL_PtiMode_t) RAIL_PTI_MODE_SPI) +#define RAIL_PTI_MODE_UART ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART) +#define RAIL_PTI_MODE_UART_ONEWIRE ((RAIL_PtiMode_t) RAIL_PTI_MODE_UART_ONEWIRE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_PtiConfig_t + * @brief A configuration for PTI. + */ +typedef struct RAIL_PtiConfig { + /** Packet Trace mode (UART or SPI). */ + RAIL_PtiMode_t mode; + /** Output baudrate for PTI in Hz. */ + uint32_t baud; + /** Data output (DOUT) location for doutPort/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t doutLoc; + /** Data output (DOUT) GPIO port. */ + uint8_t doutPort; + /** Data output (DOUT) GPIO pin. */ + uint8_t doutPin; + /** Data clock (DCLK) location for dclkPort/Pin. Only used in SPI mode. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t dclkLoc; + /** Data clock (DCLK) GPIO port. Only used in SPI mode. */ + uint8_t dclkPort; + /** Data clock (DCLK) GPIO pin. Only used in SPI mode. */ + uint8_t dclkPin; + /** Data frame (DFRAME) location for dframePort/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t dframeLoc; + /** Data frame (DFRAME) GPIO port. */ + uint8_t dframePort; + /** Data frame (DFRAME) GPIO pin. */ + uint8_t dframePin; +} RAIL_PtiConfig_t; + +/** + * @enum RAIL_PtiProtocol_t + * @brief The protocol that RAIL outputs via the Packet Trace Interface (PTI). + */ +RAIL_ENUM(RAIL_PtiProtocol_t) { + RAIL_PTI_PROTOCOL_CUSTOM = 0, /**< PTI output for a custom protocol. */ + RAIL_PTI_PROTOCOL_THREAD = 2, /**< PTI output for the Thread protocol. */ + RAIL_PTI_PROTOCOL_BLE = 3, /**< PTI output for the Bluetooth Smart protocol. */ + RAIL_PTI_PROTOCOL_CONNECT = 4, /**< PTI output for the Connect protocol. */ + RAIL_PTI_PROTOCOL_ZIGBEE = 5, /**< PTI output for the Zigbee protocol. */ + RAIL_PTI_PROTOCOL_ZWAVE = 6, /**< PTI output for the Z-Wave protocol. */ + RAIL_PTI_PROTOCOL_WISUN = 7, /**< PTI output for the Wi-SUN protocol. */ + RAIL_PTI_PROTOCOL_802154 = 8, /**< PTI output for a custom protocol using a built-in 802.15.4 radio config. */ + RAIL_PTI_PROTOCOL_SIDEWALK = 9, /** < PTI output for Sidewalk protocol. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_PTI_PROTOCOL_CUSTOM ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CUSTOM) +#define RAIL_PTI_PROTOCOL_THREAD ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_THREAD) +#define RAIL_PTI_PROTOCOL_BLE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_BLE) +#define RAIL_PTI_PROTOCOL_CONNECT ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_CONNECT) +#define RAIL_PTI_PROTOCOL_ZIGBEE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZIGBEE) +#define RAIL_PTI_PROTOCOL_ZWAVE ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_ZWAVE) +#define RAIL_PTI_PROTOCOL_802154 ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_802154) +#define RAIL_PTI_PROTOCOL_SIDEWALK ((RAIL_PtiProtocol_t) RAIL_PTI_PROTOCOL_SIDEWALK) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group PTI + +/****************************************************************************** + * Data Management Structures + *****************************************************************************/ +/** + * @addtogroup Data_Management + * @{ + */ + +/// Fixed-width type indicating the needed alignment for RX and TX FIFOs. +#define RAIL_FIFO_ALIGNMENT_TYPE uint32_t + +/// Alignment that is needed for the RX and TX FIFOs. +#define RAIL_FIFO_ALIGNMENT (sizeof(RAIL_FIFO_ALIGNMENT_TYPE)) + +/** + * @enum RAIL_TxDataSource_t + * @brief Transmit data sources supported by RAIL. + */ +RAIL_ENUM(RAIL_TxDataSource_t) { + TX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ + /** Uses the multi-level frequency modulation data. + * @note This is only supported on devices where \ref RAIL_SUPPORTS_MFM + * or \ref RAIL_SupportsMfm() are true. + * @note This feature cannot be used with built-in protocols (802.15.4, BLE, + * Z-Wave). + */ + TX_MFM_DATA, + /** A count of the choices in this enumeration. */ + RAIL_TX_DATA_SOURCE_COUNT // Must be last +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define TX_PACKET_DATA ((RAIL_TxDataSource_t) TX_PACKET_DATA) +#define TX_MFM_DATA ((RAIL_TxDataSource_t) TX_MFM_DATA) +#define RAIL_TX_DATA_SOURCE_COUNT ((RAIL_TxDataSource_t) RAIL_TX_DATA_SOURCE_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_RxDataSource_t + * @brief Receive data sources supported by RAIL. + * + * @note Data sources other than \ref RX_PACKET_DATA require use of + * \ref RAIL_DataMethod_t::FIFO_MODE. + */ +RAIL_ENUM(RAIL_RxDataSource_t) { + RX_PACKET_DATA, /**< Uses the frame hardware to packetize data. */ + RX_DEMOD_DATA, /**< Gets 8-bit data output from the demodulator. */ + RX_IQDATA_FILTLSB, /**< Gets lower 16 bits of I/Q data provided to the + demodulator. */ + RX_IQDATA_FILTMSB, /**< Gets highest 16 bits of I/Q data provided to the + demodulator. */ + RX_DIRECT_MODE_DATA, /**< Gets RX direct mode data output from the demodulator. + BCRDEMOD captures bcr_dmod_rawd at the sample rate + (faster than the bit rate by the OSR), specifically + the demod_samp_rate trigger. + Only supported if + \ref RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO + is true. */ + RX_DIRECT_SYNCHRONOUS_MODE_DATA, /**< Gets synchronous RX direct mode data + output from the demodulator. + BCRDEMOD_SYNCHRONOUS captures + bcr_dmod_rxd_ext at the bit + rate (bcr_dmod_bitclk_ext trigger). + Only supported if + \ref RAIL_SUPPORTS_RX_DIRECT_MODE_DATA_TO_FIFO + is true. + Only efr32xg23, efr32xg25, or efr32xg28 + have this mode.*/ + /** A count of the choices in this enumeration. */ + RAIL_RX_DATA_SOURCE_COUNT // Must be last +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RX_PACKET_DATA ((RAIL_RxDataSource_t) RX_PACKET_DATA) +#define RX_DEMOD_DATA ((RAIL_RxDataSource_t) RX_DEMOD_DATA) +#define RX_IQDATA_FILTLSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTLSB) +#define RX_IQDATA_FILTMSB ((RAIL_RxDataSource_t) RX_IQDATA_FILTMSB) +#define RX_DIRECT_MODE_DATA ((RAIL_RxDataSource_t) RX_DIRECT_MODE_DATA) +#define RX_DIRECT_SYNCHRONOUS_MODE_DATA ((RAIL_RxDataSource_t) RX_DIRECT_SYNCHRONOUS_MODE_DATA) +#define RAIL_RX_DATA_SOURCE_COUNT ((RAIL_RxDataSource_t) RAIL_RX_DATA_SOURCE_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_DataMethod_t + * @brief Methods for the application to provide and retrieve data from RAIL. + * + * For Transmit the distinction between \ref RAIL_DataMethod_t::PACKET_MODE + * and \ref RAIL_DataMethod_t::FIFO_MODE has become more cosmetic than + * functional, as the RAIL_WriteTxFifo() and RAIL_SetTxFifoThreshold() APIs + * and related \ref RAIL_EVENT_TX_FIFO_ALMOST_EMPTY event can be used in + * either mode. For Receive the distinction is functionally important because + * in \ref RAIL_DataMethod_t::PACKET_MODE rollback occurs automatically for + * unsuccessfully-received packets (\ref RAIL_RxPacketStatus_t ABORT statuses), + * flushing their data. In \ref RAIL_DataMethod_t::FIFO_MODE rollback is + * prevented, leaving the data from unsuccessfully-received packets in the + * receive FIFO for the application to deal with. This allows for packets + * larger than the receive FIFO size where automatic rollback would corrupt + * the receive FIFO. + */ +RAIL_ENUM(RAIL_DataMethod_t) { + PACKET_MODE, /**< Packet-based data method. */ + FIFO_MODE, /**< FIFO-based data method. */ + /** A count of the choices in this enumeration. */ + RAIL_DATA_METHOD_COUNT // Must be last +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define PACKET_MODE ((RAIL_DataMethod_t) PACKET_MODE) +#define FIFO_MODE ((RAIL_DataMethod_t) FIFO_MODE) +#define RAIL_DATA_METHOD_COUNT ((RAIL_DataMethod_t) RAIL_DATA_METHOD_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_FIFO_THRESHOLD_DISABLED + * @brief A FIFO threshold value that disables the threshold. + */ +#define RAIL_FIFO_THRESHOLD_DISABLED 0xFFFFU + +/** + * @struct RAIL_DataConfig_t + * @brief RAIL data configuration structure + * + * Select the transmit/receive data sources and the + * method the application uses to provide/retrieve data from RAIL. + */ +typedef struct { + RAIL_TxDataSource_t txSource; /**< Source of TX Data. */ + RAIL_RxDataSource_t rxSource; /**< Source of RX Data. */ + RAIL_DataMethod_t txMethod; /**< Method of providing transmit data. */ + RAIL_DataMethod_t rxMethod; /**< Method of retrieving receive data. */ +} RAIL_DataConfig_t; + +/** @} */ // end of group Data Management + +/****************************************************************************** + * State Transitions + *****************************************************************************/ +/** + * @addtogroup State_Transitions + * @{ + */ + +/** + * @typedef RAIL_TransitionTime_t + * @brief Suitable type for the supported transition time range. + * + * Refer to platform-specific \ref RAIL_MINIMUM_TRANSITION_US and + * \ref RAIL_MAXIMUM_TRANSITION_US for the valid range of this type. + */ +typedef uint32_t RAIL_TransitionTime_t; + +/** + * @def RAIL_TRANSITION_TIME_KEEP + * @brief A value to use in \ref RAIL_StateTiming_t fields when + * calling \ref RAIL_SetStateTiming() to keep that timing + * parameter at it current setting. + */ +#define RAIL_TRANSITION_TIME_KEEP ((RAIL_TransitionTime_t) -1) + +/** + * @struct RAIL_StateTiming_t + * @brief A timing configuration structure for the RAIL State Machine. + * + * Configure the timings of the radio state transitions for common situations. + * All of the listed timings are in microseconds. Transitions from an active + * radio state to idle are not configurable, and will always happen as fast + * as possible. + * No timing value can exceed platform-specific \ref RAIL_MAXIMUM_TRANSITION_US. + * Use \ref RAIL_TRANSITION_TIME_KEEP to keep an existing setting. + * + * For idleToRx, idleToTx, rxToTx, txToRx, and txToTx a value of 0 for the + * transition time means that the specified transition should happen as fast + * as possible, even if the timing cannot be as consistent. Otherwise, the + * timing value cannot be below the platform-specific \ref RAIL_MINIMUM_TRANSITION_US. + * + * For idleToTx, rxToTx, and txToTx setting a longer \ref + * RAIL_TxPowerConfig_t::rampTime may result in a larger minimum value. + * + * For rxSearchTimeout and txToRxSearchTimeout, there is no minimum value. A + * value of 0 disables the feature, functioning as an infinite timeout. + */ +typedef struct RAIL_StateTiming { + RAIL_TransitionTime_t idleToRx; /**< Transition time from IDLE to RX. */ + RAIL_TransitionTime_t txToRx; /**< Transition time from TX to RX. */ + RAIL_TransitionTime_t idleToTx; /**< Transition time from IDLE to TX. */ + RAIL_TransitionTime_t rxToTx; /**< Transition time from RX packet to TX. */ + RAIL_TransitionTime_t rxSearchTimeout; /**< Length of time the radio will search for a + packet when coming from idle or RX. */ + RAIL_TransitionTime_t txToRxSearchTimeout; /**< Length of time the radio will search for a + packet when coming from TX. */ + RAIL_TransitionTime_t txToTx; /**< Transition time from TX packet to TX. */ +} RAIL_StateTiming_t; + +/** + * @enum RAIL_RadioState_t + * @brief The state of the radio. + */ +RAIL_ENUM(RAIL_RadioState_t) { + RAIL_RF_STATE_INACTIVE = 0u, /**< Radio is inactive. */ + RAIL_RF_STATE_ACTIVE = (1u << 0), /**< Radio is either idle or, + in combination with the RX and TX states, + receiving or transmitting a frame.*/ + RAIL_RF_STATE_RX = (1u << 1), /**< Radio is in receive. */ + RAIL_RF_STATE_TX = (1u << 2), /**< Radio is in transmit. */ + RAIL_RF_STATE_IDLE = (RAIL_RF_STATE_ACTIVE), /**< Radio is idle. */ + /** Radio is actively receiving a frame. */ + RAIL_RF_STATE_RX_ACTIVE = (RAIL_RF_STATE_RX | RAIL_RF_STATE_ACTIVE), + /** Radio is actively transmitting a frame. */ + RAIL_RF_STATE_TX_ACTIVE = (RAIL_RF_STATE_TX | RAIL_RF_STATE_ACTIVE) +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RF_STATE_INACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_INACTIVE) +#define RAIL_RF_STATE_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_ACTIVE) +#define RAIL_RF_STATE_RX ((RAIL_RadioState_t) RAIL_RF_STATE_RX) +#define RAIL_RF_STATE_TX ((RAIL_RadioState_t) RAIL_RF_STATE_TX) +#define RAIL_RF_STATE_IDLE ((RAIL_RadioState_t) RAIL_RF_STATE_IDLE) +#define RAIL_RF_STATE_RX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_RX_ACTIVE) +#define RAIL_RF_STATE_TX_ACTIVE ((RAIL_RadioState_t) RAIL_RF_STATE_TX_ACTIVE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * @enum RAIL_RadioStateEfr32_t + * @brief Detailed EFR32 Radio state machine statuses. + */ +RAIL_ENUM(RAIL_RadioStateEfr32_t) { + RAIL_RAC_STATE_OFF, /**< Radio is off. */ + RAIL_RAC_STATE_RXWARM, /**< Radio is enabling the receiver. */ + RAIL_RAC_STATE_RXSEARCH, /**< Radio is listening for incoming frames. */ + RAIL_RAC_STATE_RXFRAME, /**< Radio is receiving a frame. */ + RAIL_RAC_STATE_RXPD, /**< Radio is powering down receiver and going to + OFF state. */ + RAIL_RAC_STATE_RX2RX, /**< Radio is going back to receive mode after + receiving a frame. */ + RAIL_RAC_STATE_RXOVERFLOW, /**< Received data was lost due to full receive + buffer. */ + RAIL_RAC_STATE_RX2TX, /**< Radio is disabling receiver and enabling + transmitter. */ + RAIL_RAC_STATE_TXWARM, /**< Radio is enabling transmitter. */ + RAIL_RAC_STATE_TX, /**< Radio is transmitting data. */ + RAIL_RAC_STATE_TXPD, /**< Radio is powering down transmitter and going + to OFF state. */ + RAIL_RAC_STATE_TX2RX, /**< Radio is disabling transmitter and enabling + reception. */ + RAIL_RAC_STATE_TX2TX, /**< Radio is preparing a transmission after the + previous transmission was ended. */ + RAIL_RAC_STATE_SHUTDOWN, /**< Radio is powering down receiver and going to + OFF state. */ + RAIL_RAC_STATE_POR, /**< Radio power-on-reset state (EFR32xG22 and later) */ + RAIL_RAC_STATE_NONE /**< Invalid Radio state, must be the last entry. */ +}; +#endif//DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RAC_STATE_OFF ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_OFF) +#define RAIL_RAC_STATE_RXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXWARM) +#define RAIL_RAC_STATE_RXSEARCH ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXSEARCH) +#define RAIL_RAC_STATE_RXFRAME ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXFRAME) +#define RAIL_RAC_STATE_RXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXPD) +#define RAIL_RAC_STATE_RX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2RX) +#define RAIL_RAC_STATE_RXOVERFLOW ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RXOVERFLOW) +#define RAIL_RAC_STATE_RX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_RX2TX) +#define RAIL_RAC_STATE_TXWARM ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXWARM) +#define RAIL_RAC_STATE_TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX) +#define RAIL_RAC_STATE_TXPD ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TXPD) +#define RAIL_RAC_STATE_TX2RX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2RX) +#define RAIL_RAC_STATE_TX2TX ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_TX2TX) +#define RAIL_RAC_STATE_SHUTDOWN ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_SHUTDOWN) +#define RAIL_RAC_STATE_NONE ((RAIL_RadioStateEfr32_t) RAIL_RAC_STATE_NONE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_StateTransitions_t + * @brief Used to specify radio states to transition to on success or failure. + */ +typedef struct RAIL_StateTransitions { + /** + * Indicate the state the radio should return to after a successful action. + */ + RAIL_RadioState_t success; + /** + * Indicate the state the radio should return to after an error. + */ + RAIL_RadioState_t error; +} RAIL_StateTransitions_t; + +/** + * @enum RAIL_RadioStateDetail_t + * @brief The detailed state of the radio. + * + * The three radio state bits \ref RAIL_RF_STATE_DETAIL_IDLE_STATE, \ref + * RAIL_RF_STATE_DETAIL_RX_STATE, and \ref RAIL_RF_STATE_DETAIL_TX_STATE + * comprise a set of mutually exclusive core radio states. Only one (or none) + * of these bits can be set at a time. Otherwise, the value is invalid. + * + * The precise meaning of each of these three core bits, when set, depends on + * the value of the two bits \ref RAIL_RF_STATE_DETAIL_TRANSITION and \ref + * RAIL_RF_STATE_DETAIL_ACTIVE. When \ref RAIL_RF_STATE_DETAIL_TRANSITION is + * set, the radio is transitioning into the core radio state corresponding + * to the set state bit. When it is clear, the radio is already in the core + * radio state that corresponds to the set state bit. When \ref + * RAIL_RF_STATE_DETAIL_ACTIVE is set, the radio is actively transmitting or + * receiving. When it is clear, the radio is not actively transmitting or receiving. + * This bit will always be clear when \ref RAIL_RF_STATE_DETAIL_IDLE_STATE is + * set, and will always be set when \ref RAIL_RF_STATE_DETAIL_TX_STATE is set. + * Otherwise, the value is invalid. + * + * The bit \ref RAIL_RF_STATE_DETAIL_NO_FRAMES is set if the radio is currently + * operating with frame detection disabled, and clear otherwise. The bit \ref + * RAIL_RF_STATE_DETAIL_LBT_SHIFT is set if an LBT/CSMA operation + * (e.g., performing CCA) is currently ongoing, and clear otherwise. + */ +RAIL_ENUM(RAIL_RadioStateDetail_t) { + /** Shift position of \ref RAIL_RF_STATE_DETAIL_IDLE_STATE bit */ + RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT = 0u, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_RX_STATE bit */ + RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_TX_STATE bit */ + RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_TRANSITION bit */ + RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_ACTIVE bit */ + RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_NO_FRAMES bit */ + RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT, + /** Shift position of \ref RAIL_RF_STATE_DETAIL_LBT bit */ + RAIL_RF_STATE_DETAIL_LBT_SHIFT, +}; + +/** Radio is inactive. */ +#define RAIL_RF_STATE_DETAIL_INACTIVE (0U) +/** Radio is in or headed to the idle state. */ +#define RAIL_RF_STATE_DETAIL_IDLE_STATE (1U << RAIL_RF_STATE_DETAIL_IDLE_STATE_SHIFT) +/** Radio is in or headed to the receive state. */ +#define RAIL_RF_STATE_DETAIL_RX_STATE (1U << RAIL_RF_STATE_DETAIL_RX_STATE_SHIFT) +/** Radio is in or headed to the transmit state. */ +#define RAIL_RF_STATE_DETAIL_TX_STATE (1U << RAIL_RF_STATE_DETAIL_TX_STATE_SHIFT) +/** Radio is headed to the idle, receive, or transmit state. */ +#define RAIL_RF_STATE_DETAIL_TRANSITION (1U << RAIL_RF_STATE_DETAIL_TRANSITION_SHIFT) +/** Radio is actively transmitting or receiving. */ +#define RAIL_RF_STATE_DETAIL_ACTIVE (1U << RAIL_RF_STATE_DETAIL_ACTIVE_SHIFT) +/** Radio has frame detect disabled. */ +#define RAIL_RF_STATE_DETAIL_NO_FRAMES (1U << RAIL_RF_STATE_DETAIL_NO_FRAMES_SHIFT) +/** LBT/CSMA operation is currently ongoing. */ +#define RAIL_RF_STATE_DETAIL_LBT (1U << RAIL_RF_STATE_DETAIL_LBT_SHIFT) +/** Mask for core radio state bits. */ +#define RAIL_RF_STATE_DETAIL_CORE_STATE_MASK (RAIL_RF_STATE_DETAIL_IDLE_STATE \ + | RAIL_RF_STATE_DETAIL_RX_STATE \ + | RAIL_RF_STATE_DETAIL_TX_STATE) + +/** + * @enum RAIL_IdleMode_t + * @brief An enumeration for the different types of supported idle modes. These + * vary how quickly and destructively they put the radio into idle. + */ +RAIL_ENUM(RAIL_IdleMode_t) { + /** + * Idle the radio by turning off receive and canceling any future scheduled + * receive or transmit operations. It does not abort a receive or + * transmit in progress. + */ + RAIL_IDLE, + /** + * Idle the radio by turning off receive and any scheduled events. It + * also aborts any receive, transmit, or scheduled events in progress. + */ + RAIL_IDLE_ABORT, + /** + * Force the radio into a shutdown mode by stopping whatever state is in + * progress. This is a more destructive shutdown than \ref RAIL_IDLE or + * \ref RAIL_IDLE_ABORT and can be useful in certain situations when directed + * by the support team or for debugging. Note that this method may corrupt + * receive and transmit buffers so it requires a more thorough cleanup + * and any held packets will be lost. + */ + RAIL_IDLE_FORCE_SHUTDOWN, + /** + * Similar to the \ref RAIL_IDLE_FORCE_SHUTDOWN command, however, it will also + * clear any pending RAIL events related to receive and transmit. + */ + RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_IDLE ((RAIL_IdleMode_t) RAIL_IDLE) +#define RAIL_IDLE_ABORT ((RAIL_IdleMode_t) RAIL_IDLE_ABORT) +#define RAIL_IDLE_FORCE_SHUTDOWN ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN) +#define RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS ((RAIL_IdleMode_t) RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of group State_Transitions + +/****************************************************************************** + * TX Channel Hopping + *****************************************************************************/ +/** + * @addtogroup Tx_Channel_Hopping TX Channel Hopping + * @{ + */ + +/** + * @struct RAIL_TxChannelHoppingConfigEntry_t + * @brief Structure that represents one of the channels that is part of a + * \ref RAIL_TxChannelHoppingConfig_t sequence of channels used in + * channel hopping. + */ +typedef struct RAIL_TxChannelHoppingConfigEntry { + /** + * The channel number to be used for this entry in the channel hopping + * sequence. If this is an invalid channel for the current PHY, the + * call to \ref RAIL_SetNextTxRepeat() will fail. + */ + uint16_t channel; + /** + * Pad bytes reserved for future use and currently ignored. + */ + uint8_t reserved[2]; + /** + * Idle time in microseconds to wait before transmitting on the channel + * indicated by this entry. + */ + uint32_t delay; +} RAIL_TxChannelHoppingConfigEntry_t; + +/** + * @struct RAIL_TxChannelHoppingConfig_t + * @brief Wrapper struct that will contain the sequence of + * \ref RAIL_TxChannelHoppingConfigEntry_t that represents the channel + * sequence to use during TX Channel Hopping. + */ +typedef struct RAIL_TxChannelHoppingConfig { + /** + * Pointer to contiguous global read-write memory that will be used + * by RAIL to store channel hopping information throughout its operation. + * It need not be initialized and applications should never write + * data anywhere in this buffer. + * + * @note the size of this buffer must be at least as large as + * 3 + \ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * numberOfChannels, + * plus the sum of the sizes of the + * radioConfigDeltaAdd's of the required channels, plus the size of the + * radioConfigDeltaSubtract. In the case that one channel + * appears two or more times in your channel sequence + * (e.g., 1, 2, 3, 2), you must account for the radio configuration + * size that number of times (i.e., need to count channel 2's + * radio configuration size twice for the given example). The buffer is + * for internal use to the library. + */ + uint32_t *buffer; + /** + * This parameter must be set to the length of the buffer array, in 32 bit + * words. This way, during configuration, the software can confirm it's + * writing within the bounds of the buffer. The configuration API will return + * an error or trigger \ref RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT if + * bufferLength is insufficient. + */ + uint16_t bufferLength; + /** + * The number of channels in the channel hopping sequence, which is the + * number of elements in the array that entries points to. + */ + uint8_t numberOfChannels; + /** + * Pad byte reserved for future use and currently ignored. + */ + uint8_t reserved; + /** + * A pointer to the first element of an array of \ref + * RAIL_TxChannelHoppingConfigEntry_t that represents the channels + * used during channel hopping. The length of this array must be + * numberOfChannels. + */ + RAIL_TxChannelHoppingConfigEntry_t *entries; +} RAIL_TxChannelHoppingConfig_t; + +/// The worst-case platform-agnostic static amount of memory needed per +/// channel for channel hopping, measured in 32 bit words, regardless of +/// the size of radio configuration structures. +#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE (65U) + +/** @} */ // end of group Tx_Channel_Hopping + +/****************************************************************************** + * TX/RX Configuration Structures + *****************************************************************************/ +/** + * @addtogroup Transmit + * @{ + */ + +/** + * @enum RAIL_StopMode_t + * @brief Stop radio operation options bit mask + */ +RAIL_ENUM(RAIL_StopMode_t) { + /** Shift position of \ref RAIL_STOP_MODE_ACTIVE bit */ + RAIL_STOP_MODE_ACTIVE_SHIFT = 0, + /** Shift position of \ref RAIL_STOP_MODE_PENDING bit */ + RAIL_STOP_MODE_PENDING_SHIFT = 1 +}; + +/** Do not stop any radio operations */ +#define RAIL_STOP_MODES_NONE (0U) +/** Stop active radio operations only */ +#define RAIL_STOP_MODE_ACTIVE (1U << RAIL_STOP_MODE_ACTIVE_SHIFT) +/** Stop pending radio operations */ +#define RAIL_STOP_MODE_PENDING (1U << RAIL_STOP_MODE_PENDING_SHIFT) +/** Stop all radio operations */ +#define RAIL_STOP_MODES_ALL (0xFFU) + +/** + * @enum RAIL_TxOptions_t + * @brief Transmit options, in reality a bitmask. + */ +RAIL_ENUM_GENERIC(RAIL_TxOptions_t, uint32_t) { + /** Shift position of \ref RAIL_TX_OPTION_WAIT_FOR_ACK bit */ + RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT = 0, + /** Shift position of \ref RAIL_TX_OPTION_REMOVE_CRC bit */ + RAIL_TX_OPTION_REMOVE_CRC_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_SYNC_WORD_ID bit */ + RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_ANTENNA0 bit */ + RAIL_TX_OPTION_ANTENNA0_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_ANTENNA1 bit */ + RAIL_TX_OPTION_ANTENNA1_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_ALT_PREAMBLE_LEN bit */ + RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_CCA_PEAK_RSSI bit */ + RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_CCA_ONLY bit */ + RAIL_TX_OPTION_CCA_ONLY_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_RESEND bit */ + RAIL_TX_OPTION_RESEND_SHIFT, + /** Shift position of \ref RAIL_TX_OPTION_CONCURRENT_PHY_ID bit */ + RAIL_TX_OPTION_CONCURRENT_PHY_ID_SHIFT, + /** A count of the choices in this enumeration. */ + RAIL_TX_OPTIONS_COUNT // Must be last +}; + +/** A value representing no options enabled. */ +#define RAIL_TX_OPTIONS_NONE 0UL +/** All options disabled by default. This is the fastest TX option to apply. */ +#define RAIL_TX_OPTIONS_DEFAULT RAIL_TX_OPTIONS_NONE +/** + * An option to configure whether or not the TXing node will listen for an ACK. + * If this is false, the isAck flag in RAIL_RxPacketDetails_t of a received + * packet will always be false. + */ +#define RAIL_TX_OPTION_WAIT_FOR_ACK (1UL << RAIL_TX_OPTION_WAIT_FOR_ACK_SHIFT) +/** + * An option to remove CRC bytes from TX packets. To receive packets when the + * sender has this option set true, set \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS + * on the receive side. + */ +#define RAIL_TX_OPTION_REMOVE_CRC (1UL << RAIL_TX_OPTION_REMOVE_CRC_SHIFT) +/** + * An option to select which sync word is used during the transmission. + * When two sync words are configured by the PHY or \ref RAIL_ConfigSyncWords() + * enabling this option selects SYNC2 rather than SYNC1 for the upcoming transmit. + * + * This option should not be used when only one sync word has been configured. + * + * @note There are a few special radio configurations (e.g. BLE Viterbi) that do + * not support transmitting different sync words. + */ +#define RAIL_TX_OPTION_SYNC_WORD_ID (1UL << RAIL_TX_OPTION_SYNC_WORD_ID_SHIFT) +/** + * An option to select antenna 0 for transmission. If the antenna selection + * option is not set or if both antenna options are set, then the transmit + * will occur on either antenna depending on the last receive or transmit + * selection. This option is only valid on platforms that support + * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * + * @note These TX antenna options do not control the antenna used for + * \ref Auto_Ack transmissions, which always occur on the same antenna + * used to receive the packet being acknowledged. + */ +#define RAIL_TX_OPTION_ANTENNA0 (1UL << RAIL_TX_OPTION_ANTENNA0_SHIFT) +/** + * An option to select antenna 1 for transmission. If the antenna selection + * option is not set or if both antenna options are set, then the transmit + * will occur on either antenna depending on the last receive or transmit + * selection. This option is only valid on platforms that support + * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + * + * @note These TX antenna options do not control the antenna used for + * \ref Auto_Ack transmissions, which always occur on the same antenna + * used to receive the packet being acknowledged. + */ +#define RAIL_TX_OPTION_ANTENNA1 (1UL << RAIL_TX_OPTION_ANTENNA1_SHIFT) +/** + * An option to use the alternate preamble length established + * by \ref RAIL_SetTxAltPreambleLength() for the transmission. + * When not set, the PHY configuration's preamble length is used. + */ +#define RAIL_TX_OPTION_ALT_PREAMBLE_LEN (1UL << RAIL_TX_OPTION_ALT_PREAMBLE_LEN_SHIFT) +/** + * An option to use peak rather than average RSSI energy detected during + * CSMA's RAIL_CsmaConfig_t::ccaDuration or LBT's + * RAIL_LbtConfig_t::lbtDuration to determine whether the channel is clear + * or busy. This option is only valid when calling one of the CCA transmit + * routines: \ref RAIL_StartCcaCsmaTx, \ref RAIL_StartCcaLbtTx, \ref + * RAIL_StartScheduledCcaCsmaTx, or \ref RAIL_StartScheduledCcaLbtTx. + * + * @note This option does nothing on platforms like EFR32XG1 that lack + * support for capturing peak RSSI energy. + */ +#define RAIL_TX_OPTION_CCA_PEAK_RSSI (1UL << RAIL_TX_OPTION_CCA_PEAK_RSSI_SHIFT) +/** + * An option to only perform the CCA (CSMA/LBT) operation but *not* + * automatically transmit if the channel is clear. This option is only valid + * when calling one of the CCA transmit routines: \ref RAIL_StartCcaCsmaTx, + * \ref RAIL_StartCcaLbtTx, \ref RAIL_StartScheduledCcaCsmaTx, or \ref + * RAIL_StartScheduledCcaLbtTx. + * + * Application can then use the \ref RAIL_EVENT_TX_CHANNEL_CLEAR to + * initiate transmit manually, e.g., giving it the opportunity to adjust + * outgoing packet data before the packet goes out. + * + * @note Configured state transitions to Rx or Idle are suspended during + * this CSMA/LBT operation. If packet reception occurs, the radio will + * return to the state it was in just prior to the CSMA/LBT operation + * when that reception (including any AutoACK response) is complete. + */ +#define RAIL_TX_OPTION_CCA_ONLY (1UL << RAIL_TX_OPTION_CCA_ONLY_SHIFT) + +/** + * An option to resend packet at the beginning of the Transmit FIFO. + * + * The packet to be resent must have been previously provided by + * \ref RAIL_SetTxFifo() or \ref RAIL_WriteTxFifo() passing true for + * the latter's reset parameter. It works by setting the + * transmit FIFO's read offset to the beginning of the FIFO while + * leaving its write offset intact. For this to work, + * \ref RAIL_DataConfig_t::txMethod must be RAIL_DataMethod_t::PACKET_MODE + * (i.e., the packet can't exceed the Transmit FIFO's size), otherwise + * undefined behavior will result. + * + * This option can also be used with \ref RAIL_SetNextTxRepeat() to cause + * the repeated packet(s) to all be the same as the first. + */ +#define RAIL_TX_OPTION_RESEND (1UL << RAIL_TX_OPTION_RESEND_SHIFT) + +/** + * An option to specify which PHY is used to transmit in the case of concurrent mode. + * Concurrent mode is only allowed on EFR32xG25 for some predefined combinations of Wi-SUN PHYs. + * When set/unset, the alternate/base PHY is used to transmit. + */ +#define RAIL_TX_OPTION_CONCURRENT_PHY_ID (1UL << RAIL_TX_OPTION_CONCURRENT_PHY_ID_SHIFT) + +/** A value representing all possible options. */ +#define RAIL_TX_OPTIONS_ALL 0xFFFFFFFFUL + +/** + * @struct RAIL_TxPacketDetails_t + * @brief Detailed information requested about the packet that was just, + * or is currently being, transmitted. + */ +typedef struct RAIL_TxPacketDetails { + /** + * The timestamp of the transmitted packet in the RAIL timebase, + * filled in by RAIL_GetTxPacketDetails(). + */ + RAIL_PacketTimeStamp_t timeSent; + /** + * Indicate whether the transmitted packet was an automatic ACK. In a generic + * sense, an automatic ACK is defined as a packet sent in response to a + * received ACK-requesting frame when auto-ACK is enabled. In a protocol + * specific sense this definition may be more or less restrictive to match the + * specification and you should refer to that protocol's documentation. + */ + bool isAck; +} RAIL_TxPacketDetails_t; + +/** + * @enum RAIL_ScheduledTxDuringRx_t + * @brief Enumerates the possible outcomes of what will occur if a + * scheduled TX ends up firing during RX. Because RX and TX can't + * happen at the same time, it is up to the user how the TX should be + * handled. This enumeration is passed into RAIL_StartScheduledTx() + * as part of \ref RAIL_ScheduleTxConfig_t. + */ +RAIL_ENUM(RAIL_ScheduledTxDuringRx_t) { + /** + * The scheduled TX will be postponed until RX completes and then sent. + */ + RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX, + /** + * The scheduled TX will be aborted and a + * \ref RAIL_EVENT_TX_BLOCKED event will fire. + */ + RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_POSTPONE_TX) +#define RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX ((RAIL_ScheduledTxDuringRx_t) RAIL_SCHEDULED_TX_DURING_RX_ABORT_TX) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_ScheduleTxConfig_t + * @brief A configuration structure for a scheduled transmit. + */ +typedef struct RAIL_ScheduleTxConfig { + /** + * The time when to transmit this packet. The exact interpretation of + * this value depends on the mode specified below. + */ + RAIL_Time_t when; + /** + * The type of delay. See the \ref RAIL_TimeMode_t documentation for + * more information. Be sure to use \ref RAIL_TIME_ABSOLUTE delays for + * time-critical protocols. + */ + RAIL_TimeMode_t mode; + /** + * Indicate which action to take with a scheduled TX if it occurs during RX. + * See \ref RAIL_ScheduledTxDuringRx_t structure for more information on + * potential options. + */ + RAIL_ScheduledTxDuringRx_t txDuringRx; +} RAIL_ScheduleTxConfig_t; + +/** + * @def RAIL_MAX_LBT_TRIES + * @brief The maximum number of LBT/CSMA retries supported. + */ +#define RAIL_MAX_LBT_TRIES (15U) + +/** + * @def RAIL_MAX_CSMA_EXPONENT + * @brief The maximum power-of-2 exponent for CSMA backoffs. + */ +#define RAIL_MAX_CSMA_EXPONENT (8U) + +/// +/// @struct RAIL_CsmaConfig_t +/// @brief A configuration structure for the CSMA transmit algorithm. +/// +/// One of RAIL's schemes for polite spectrum access is an implementation of +/// a Carrier-Sense Multiple Access (CSMA) algorithm based on IEEE 802.15.4 +/// (unslotted). +/// \n In pseudo-code it works like this, showing relevant event notifications: +/// @code{.c} +/// // Return true to transmit packet, false to not transmit packet. +/// bool performCsma(const RAIL_CsmaConfig_t *csmaConfig) +/// { +/// bool isFixedBackoff = ((csmaConfig->csmaMinBoExp == 0) +/// && (csmaConfig->csmaMaxBoExp == 0)); +/// int backoffExp = csmaConfig->csmaMinBoExp; // Initial backoff exponent +/// int backoffMultiplier = 1; // Assume fixed backoff +/// int try; +/// +/// // Special-case tries == 0 to transmit immediately without backoff+CCA +/// if (csmaConfig->csmaTries == 0) { +/// return true; +/// } +/// +/// // Start overall timeout if specified: +/// if (csmaConfig->csmaTimeout > 0) { +/// StartAbortTimer(csmaConfig->csmaTimeout, RAIL_EVENT_TX_CHANNEL_BUSY); +/// // If timeout occurs, abort and signal the indicated event. +/// } +/// +/// for (try = 0; try < csmaConfig->csmaTries; try++) { +/// if (try > 0) { +/// signalEvent(RAIL_EVENT_TX_CCA_RETRY); +/// } +/// // Determine the backoff multipler for this try: +/// if (isFixedBackoff) { +/// // backoffMultiplier already set to 1 for fixed backoff +/// } else { +/// // Start with the backoff exponent for this try: +/// if (try > 0) { +/// backoffExp++; +/// if (backoffExp > csmaConfig->csmaMaxBoExp) { +/// backoffExp = csmaConfig->csmaMaxBoExp; +/// } +/// } +/// // Pick random multiplier between 0 and 2^backoffExp - 1 inclusive: +/// backoffMultiplier = pickRandomInteger(0, (1 << backoffExp) - 1); +/// } +/// // Perform the backoff: +/// delayMicroseconds(backoffMultiplier * csmaConfig->ccaBackoff); +/// // Perform the Clear-Channel Assessment (CCA): +/// // Channel is considered busy if radio is actively receiving or +/// // transmitting, or the average energy detected across duration +/// // is above the threshold. +/// signalEvent(RAIL_EVENT_TX_START_CCA); +/// if (performCca(csmaConfig->ccaDuration, csmaConfig->ccaThreshold)) { +/// // CCA (and CSMA) success: Transmit after RX-to-TX turnaround +/// StopAbortTimer(); +/// signalEvent(RAIL_EVENT_TX_CHANNEL_CLEAR); +/// return true; +/// } else { +/// // CCA failed: loop to try again, or exit if out of tries +/// } +/// } +/// // Overall CSMA failure: Don't transmit +/// StopAbortTimer(); +/// signalEvent(RAIL_EVENT_TX_CHANNEL_BUSY); +/// return false; +/// } +/// @endcode +/// +typedef struct RAIL_CsmaConfig { + /** + * The minimum (starting) exponent for CSMA random backoff (2^exp - 1). + * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT. + * + * @warning On EFR32, due to a hardware limitation, this can only be 0 + * if \ref csmaMaxBoExp is also 0 specifying a non-random fixed backoff. + * \ref RAIL_STATUS_INVALID_PARAMETER will result otherwise. + * If you really want CSMA's first iteration to have no backoff prior to + * CCA, with subsequent iterations having random backoff as the exponent + * is increased, you must do a fixed backoff of 0 operation first + * (\ref csmaMinBoExp = 0, \ref csmaMaxBoExp = 0, \ref ccaBackoff = 0, + * \ref csmaTries = 1), and if that fails (\ref RAIL_EVENT_TX_CHANNEL_BUSY), + * follow up with a random backoff operation starting at \ref csmaMinBoExp + * = 1 for the remaining iterations. + */ + uint8_t csmaMinBoExp; + /** + * The maximum exponent for CSMA random backoff (2^exp - 1). + * It can range from 0 to \ref RAIL_MAX_CSMA_EXPONENT and must be greater + * than or equal to \ref csmaMinBoExp. + * \n If both exponents are 0, a non-random fixed backoff of \ref ccaBackoff + * duration results. + */ + uint8_t csmaMaxBoExp; + /** + * The number of backoff-then-CCA iterations that can fail before reporting + * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref + * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always + * transmits immediately without performing CSMA, similar to calling + * RAIL_StartTx(). + */ + uint8_t csmaTries; + /** + * The CCA RSSI threshold, in dBm, above which the channel is + * considered 'busy'. + */ + int8_t ccaThreshold; + /** + * The backoff unit period in RAIL's microsecond time base. It is + * multiplied by the random backoff exponential controlled by \ref + * csmaMinBoExp and \ref csmaMaxBoExp to determine the overall backoff + * period. For random backoffs, any value above 511 microseconds will + * be truncated. For fixed backoffs it can go up to 65535 microseconds. + */ + uint16_t ccaBackoff; + /** + * The minimum desired CCA check duration in microseconds. The RSSI is + * averaged over this duration by default but can be set to use the peak RSSI, + * on supported platforms, using the \ref RAIL_TX_OPTION_CCA_PEAK_RSSI option. + * + * @note Depending on the radio configuration, due to hardware constraints, + * the actual duration may be longer. Also, if the requested duration + * is too large for the radio to accommodate, RAIL_StartCcaCsmaTx() + * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. + */ + uint16_t ccaDuration; + /** + * An overall timeout, in RAIL's microsecond time base, for the operation. + * If the transmission doesn't start before this timeout expires, the + * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. + * A value 0 means no timeout is imposed. + */ + RAIL_Time_t csmaTimeout; +} RAIL_CsmaConfig_t; + +/** + * @def RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA + * @brief RAIL_CsmaConfig_t initializer configuring CSMA per IEEE 802.15.4-2003 + * on 2.4 GHz OSPSK, commonly used by ZigBee. + */ +#define RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA { \ + /* CSMA per 802.15.4-2003 on 2.4 GHz OSPSK, commonly used by ZigBee */ \ + /* csmaMinBoExp */ 3, /* 2^3-1 for 0..7 backoffs on 1st try */ \ + /* csmaMaxBoExp */ 5, /* 2^5-1 for 0..31 backoffs on 3rd+ tries */ \ + /* csmaTries */ 5, /* 5 tries overall (4 re-tries) */ \ + /* ccaThreshold */ -75, /* 10 dB above sensitivity */ \ + /* ccaBackoff */ 320, /* 20 symbols at 16 us/symbol */ \ + /* ccaDuration */ 128, /* 8 symbols at 16 us/symbol */ \ + /* csmaTimeout */ 0, /* No timeout */ \ +} + +/** + * @def RAIL_CSMA_CONFIG_SINGLE_CCA + * @brief RAIL_CsmaConfig_t initializer configuring a single CCA prior to TX. + * It can be used to as a basis for implementing other channel access schemes + * with custom backoff delays. Users can override ccaBackoff with a fixed + * delay on each use. + */ +#define RAIL_CSMA_CONFIG_SINGLE_CCA { \ + /* Perform a single CCA after 'fixed' delay */ \ + /* csmaMinBoExp */ 0, /* Used for fixed backoff */ \ + /* csmaMaxBoExp */ 0, /* Used for fixed backoff */ \ + /* csmaTries */ 1, /* Single try */ \ + /* ccaThreshold */ -75, /* Override if not desired choice */ \ + /* ccaBackoff */ 0, /* No backoff (override with fixed value) */ \ + /* ccaDuration */ 128, /* Override if not desired length */ \ + /* csmaTimeout */ 0, /* no timeout */ \ +} + +/// +/// @struct RAIL_LbtConfig_t +/// @brief A configuration structure for the LBT transmit algorithm. +/// +/// One of RAIL's schemes for polite spectrum access is an implementation of +/// a Listen-Before-Talk (LBT) algorithm, loosely based on ETSI 300 220-1. +/// \n Currently, however, it is constrained by the EFR32's CSMA-oriented hardware +/// so is turned into an equivalent \ref RAIL_CsmaConfig_t configuration and +/// passed to the CSMA engine: +/// @code{.c} +/// if (lbtMaxBoRand == lbtMinBoRand) { +/// // Fixed backoff +/// csmaMinBoExp = csmaMaxBoExp = 0; +/// if (lbtMinBoRand == 0) { +/// ccaBackoff = lbtBackoff; +/// } else { +/// ccaBackoff = lbtMinBoRand * lbtBackoff; +/// } +/// ccaDuration = lbtDuration; +/// } else { +/// // Random backoff: map to random range 0 .. (lbtMaxBoRand - lbtMinBoRand) +/// csmaMinBoExp = csmaMaxBoExp = ceiling(log2(lbtMaxBoRand - lbtMinBoRand)); +/// ccaBackoff = round((lbtBackoff * (lbtMaxBoRand - lbtMinBoRand)) +/// / (1 << csmaMinBoExp)); +/// ccaDuration = lbtDuration + (lbtMinBoRand * lbtBackoff); +/// } +/// csmaTries = lbtTries; +/// ccaThreshold = lbtThreshold; +/// csmaTimeout = lbtTimeout; +/// @endcode +/// +typedef struct RAIL_LbtConfig { + /** + * The minimum backoff random multiplier. + */ + uint8_t lbtMinBoRand; + /** + * The maximum backoff random multiplier. + * It must be greater than or equal to \ref lbtMinBoRand. + * \n If both backoff multipliers are identical, a non-random fixed backoff + * of \ref lbtBackoff times the multiplier (minimum 1) duration results. + */ + uint8_t lbtMaxBoRand; + /** + * The number of LBT iterations that can fail before reporting + * \ref RAIL_EVENT_TX_CHANNEL_BUSY. Typically ranges from 1 to \ref + * RAIL_MAX_LBT_TRIES; higher values are disallowed. A value 0 always + * transmits immediately without performing LBT, similar to calling + * RAIL_StartTx(). + */ + uint8_t lbtTries; + /** + * The LBT RSSI threshold, in dBm, above which the channel is + * considered 'busy'. + */ + int8_t lbtThreshold; + /** + * The backoff unit period, in RAIL's microsecond time base. It is + * multiplied by the random backoff multiplier controlled by \ref + * lbtMinBoRand and \ref lbtMaxBoRand to determine the overall backoff + * period. For random backoffs, any value above 511 microseconds will + * be truncated. For fixed backoffs, it can go up to 65535 microseconds. + */ + uint16_t lbtBackoff; + /** + * The minimum desired LBT check duration in microseconds. + * + * @note Depending on the radio configuration, due to hardware constraints, + * the actual duration may be longer. Also, if the requested duration + * is too large for the radio to accommodate, RAIL_StartCcaLbtTx() + * will fail returning \ref RAIL_STATUS_INVALID_PARAMETER. + */ + uint16_t lbtDuration; + /** + * An overall timeout, in RAIL's microsecond time base, for the operation. + * If the transmission doesn't start before this timeout expires, the + * transmission will fail with \ref RAIL_EVENT_TX_CHANNEL_BUSY. + * This is important for limiting LBT due to LBT's unbounded requirement + * that if the channel is busy, the next try must wait for the channel to + * clear. A value 0 means no timeout is imposed. + */ + RAIL_Time_t lbtTimeout; +} RAIL_LbtConfig_t; + +/** + * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 + * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 + * V2.4.1 for a typical Sub-GHz band. To be practical, users should override + * lbtTries and/or lbtTimeout so channel access failure will be reported in a + * reasonable time frame rather than the unbounded time frame ETSI defined. + */ +#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V2_4_1 { \ + /* LBT per ETSI 300 220-1 V2.4.1 */ \ + /* LBT time = random backoff of 0-5 ms in .5 ms increments plus 5 ms fixed */ \ + /* lbtMinBoRand */ 0, /* */ \ + /* lbtMaxBoRand */ 10, /* */ \ + /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \ + /* lbtThreshold */ -87, /* */ \ + /* lbtBackoff */ 500, /* 0.5 ms */ \ + /* lbtDuration */ 5000, /* 5 ms */ \ + /* lbtTimeout */ 0, /* No timeout (recommend user override) */ \ +} + +/** + * @def RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V3_1_0 + * @brief RAIL_LbtConfig_t initializer configuring LBT per ETSI 300 220-1 + * V3.1.0 for a typical Sub-GHz band. To be practical, users should override + * lbtTries and/or lbtTimeout so channel access failure will be reported in a + * reasonable time frame rather than the unbounded time frame ETSI defined. + */ +#define RAIL_LBT_CONFIG_ETSI_EN_300_220_1_V3_1_0 { \ + /* LBT per ETSI 300 220-1 V3.1.0 */ \ + /* LBT time = random backoff of 160-4960 us in 160 us increments */ \ + /* lbtMinBoRand */ 1, /* */ \ + /* lbtMaxBoRand */ 31, /* app-chosen; 31*lbtBackoff = 4960 us */ \ + /* lbtTries */ RAIL_MAX_LBT_TRIES, /* the maximum supported */ \ + /* lbtThreshold */ -85, /* 15 dB above Rx sensitivity per Table 45 */ \ + /* lbtBackoff */ 160, /* 160 us per Table 48 Minimum CCA interval */ \ + /* lbtDuration */ 160, /* 160 us per Table 48 Minimum deferral period */ \ + /* lbtTimeout */ 0, /* No timeout (recommend user override) */ \ +} + +/** + * @struct RAIL_SyncWordConfig_t + * @brief RAIL sync words and length configuration. + * + */ +typedef struct RAIL_SyncWordConfig { + /** Sync word length in bits, between 2 and 32, inclusive.*/ + uint8_t syncWordBits; + /** + * Sync Word1 + * @note Only @ref syncWordBits number of LS bits are used, which are sent or received on air LSB first. + */ + uint32_t syncWord1; + /** + * Sync Word2 + * @note Only @ref syncWordBits number of LS bits are used, which are sent or received on air LSB first. + */ + uint32_t syncWord2; +} RAIL_SyncWordConfig_t; + +/** + * @enum RAIL_TxRepeatOptions_t + * @brief Transmit repeat options, in reality a bitmask. + */ +RAIL_ENUM_GENERIC(RAIL_TxRepeatOptions_t, uint16_t) { + /** Shift position of \ref RAIL_TX_REPEAT_OPTION_HOP bit */ + RAIL_TX_REPEAT_OPTION_HOP_SHIFT = 0, + /** Shift position of the \ref RAIL_TX_REPEAT_OPTION_START_TO_START bit */ + RAIL_TX_REPEAT_OPTION_START_TO_START_SHIFT = 1, +}; + +/** A value representing no repeat options enabled. */ +#define RAIL_TX_REPEAT_OPTIONS_NONE 0U +/** All repeat options disabled by default. */ +#define RAIL_TX_REPEAT_OPTIONS_DEFAULT RAIL_TX_REPEAT_OPTIONS_NONE +/** + * An option to configure whether or not to channel-hop before each + * repeated transmit. + */ +#define RAIL_TX_REPEAT_OPTION_HOP (1U << RAIL_TX_REPEAT_OPTION_HOP_SHIFT) + +/** + * An option to configure the delay between transmissions to be from start to start + * instead of end to start. Delay must be long enough to cover the prior transmit's time. + */ +#define RAIL_TX_REPEAT_OPTION_START_TO_START (1 << RAIL_TX_REPEAT_OPTION_START_TO_START_SHIFT) + +/// @struct RAIL_TxRepeatConfig_t +/// @brief A configuration structure for repeated transmits +/// +/// @note The PA will always be ramped down and up in between transmits so +/// there will always be some minimum delay between transmits depending on the +/// ramp time configuration. +typedef struct RAIL_TxRepeatConfig { + /** + * The number of repeated transmits to run. A total of (iterations + 1) + * transmits will go on-air in the absence of errors. + */ + uint16_t iterations; + /** + * Repeat option(s) to apply. + */ + RAIL_TxRepeatOptions_t repeatOptions; + /** + * Per-repeat delay or hopping configuration, depending on repeatOptions. + */ + union { + /** + * When \ref RAIL_TX_REPEAT_OPTION_HOP is not set, specifies + * the delay time between each repeated transmit. Specify \ref + * RAIL_TRANSITION_TIME_KEEP to use the current \ref + * RAIL_StateTiming_t::txToTx transition time setting. + * When using \ref RAIL_TX_REPEAT_OPTION_START_TO_START the delay + * must be long enough to cover the prior transmit's time. + */ + RAIL_TransitionTime_t delay; + /** + * When \ref RAIL_TX_REPEAT_OPTION_HOP is set, this specifies + * the channel hopping configuration to use when hopping between + * repeated transmits. Per-hop delays are configured within each + * \ref RAIL_TxChannelHoppingConfigEntry_t::delay rather than + * this union's delay field. + * When using \ref RAIL_TX_REPEAT_OPTION_START_TO_START the hop delay + * must be long enough to cover the prior transmit's time. + */ + RAIL_TxChannelHoppingConfig_t channelHopping; + } delayOrHop; +} RAIL_TxRepeatConfig_t; + +/// RAIL_TxRepeatConfig_t::iterations initializer configuring infinite +/// repeated transmissions. +#define RAIL_TX_REPEAT_INFINITE_ITERATIONS (0xFFFFU) + +/** @} */ // end of group Transmit + +/****************************************************************************** + * Receive Structures + *****************************************************************************/ +/** + * @addtogroup Receive + * @{ + */ + +/** + * @addtogroup Address_Filtering + * @{ + */ + +/// A default address filtering match table for configurations that use only one +/// address field. The truth table for address matching is shown below. +/// +/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | +/// |----------------|----------|-----------|-----------|-----------|-----------| +/// | __No Match__ | 0 | 1 | 1 | 1 | 1 | +/// | __Address 0__ | 1 | 1 | 1 | 1 | 1 | +/// | __Address 1__ | 1 | 1 | 1 | 1 | 1 | +/// | __Address 2__ | 1 | 1 | 1 | 1 | 1 | +/// | __Address 3__ | 1 | 1 | 1 | 1 | 1 | +/// +#define ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD (0x1FFFFFE) +/// A default address filtering match table for configurations that use two +/// address fields and want to match the same index in each. The truth +/// table for address matching is shown below. +/// +/// | | No Match | Address 0 | Address 1 | Address 2 | Address 3 | +/// |----------------|----------|-----------|-----------|-----------|-----------| +/// | __No Match__ | 0 | 0 | 0 | 0 | 0 | +/// | __Address 0__ | 0 | 1 | 0 | 0 | 0 | +/// | __Address 1__ | 0 | 0 | 1 | 0 | 0 | +/// | __Address 2__ | 0 | 0 | 0 | 1 | 0 | +/// | __Address 3__ | 0 | 0 | 0 | 0 | 1 | +#define ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD (0x1041040) + +/// The maximum number of address fields that can be used by the address +/// filtering logic. +#define ADDRCONFIG_MAX_ADDRESS_FIELDS (2) + +/** + * @struct RAIL_AddrConfig_t + * @brief A structure to configure the address filtering functionality in RAIL. + */ +typedef struct RAIL_AddrConfig { + /** + * A list of the start offsets for each field. + * + * These offsets are specified relative to the previous field's end. + * For the first field, it is relative to either the beginning of the packet + * or the end of the frame type byte if frame type decoding is enabled. If a + * field is unused, it's offset should be set to 0. + */ + uint8_t offsets[ADDRCONFIG_MAX_ADDRESS_FIELDS]; + + /** + * A list of the address field sizes. + * + * These sizes are specified in bytes from 0 to 8. If you choose a + * size of 0, this field is effectively disabled. + */ + uint8_t sizes[ADDRCONFIG_MAX_ADDRESS_FIELDS]; + + /** + * The truth table to determine how the two fields combine to create a match. + * + * For detailed information about how this truth table is formed, see the + * detailed description of \ref Address_Filtering. + * + * For simple predefined configurations use the following defines. + * - ADDRCONFIG_MATCH_TABLE_SINGLE_FIELD + * - For filtering that only uses a single address field. + * - ADDRCONFIG_MATCH_TABLE_DOUBLE_FIELD for two field filtering where you + * - For filtering that uses two address fields in a configurations where + * you want the following logic `((Field0, Index0) && (Field1, Index0)) + * || ((Field0, Index1) && (Field1, Index1)) || ...` + */ + uint32_t matchTable; +} RAIL_AddrConfig_t; + +/** + * @brief A bitmask representation of which 4 filters passed for each + * \ref ADDRCONFIG_MAX_ADDRESS_FIELDS when filtering has completed + * successfully. + * + * It's layout is: + * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | + * |--------+--------+--------+--------+--------+--------+--------+--------| + * | Second Address Field Nibble | First Address Field Nibble | + * | Addr 3 | Addr 2 | Addr 1 | Addr 0 | Addr 3 | Addr 2 | Addr 1 | Addr 0 | + * | match | match | match | match | match | match | match | match | + * |--------+--------+--------+--------+--------+--------+--------+--------| + * + * @note This information is valid in \ref RAIL_IEEE802154_Address_t on all + * platforms, but is only valid in \ref RAIL_RxPacketInfo_t on platforms + * where \ref RAIL_SUPPORTS_ADDR_FILTER_MASK is true. + */ +typedef uint8_t RAIL_AddrFilterMask_t; + +/** @} */ // end of group Address_Filtering + +/** + * @enum RAIL_RxOptions_t + * @brief Receive options, in reality a bitmask. + */ +RAIL_ENUM_GENERIC(RAIL_RxOptions_t, uint32_t) { + /** Shift position of \ref RAIL_RX_OPTION_STORE_CRC bit. */ + RAIL_RX_OPTION_STORE_CRC_SHIFT = 0, + /** Shift position of \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS bit. */ + RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_ENABLE_DUALSYNC bit. */ + RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_TRACK_ABORTED_FRAMES bit. */ + RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO bit. */ + RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_ANTENNA0 bit. */ + RAIL_RX_OPTION_ANTENNA0_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_ANTENNA1 bit. */ + RAIL_RX_OPTION_ANTENNA1_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_DISABLE_FRAME_DETECTION bit. */ + RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT, + #ifndef DOXYGEN_SHOULD_SKIP_THIS + /** Shift position of \ref RAIL_RX_OPTION_SKIP_DC_CAL bit. */ + RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_SKIP_SYNTH_CAL bit. */ + RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT, + #endif //DOXYGEN_SHOULD_SKIP_THIS + /** Shift position of \ref RAIL_RX_OPTION_CHANNEL_SWITCHING bit. */ + RAIL_RX_OPTION_CHANNEL_SWITCHING_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_FAST_RX2RX bit. */ + RAIL_RX_OPTION_FAST_RX2RX_SHIFT, + /** Shift position of \ref RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION bit. */ + RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION_SHIFT, +}; + +/** A value representing no options enabled. */ +#define RAIL_RX_OPTIONS_NONE 0 +/** All options are disabled by default. */ +#define RAIL_RX_OPTIONS_DEFAULT RAIL_RX_OPTIONS_NONE + +/** + * An option to configure whether the CRC portion of the packet is included in + * the packet payload exposed to the app on packet reception. + * Defaults to false. + */ +#define RAIL_RX_OPTION_STORE_CRC (1UL << RAIL_RX_OPTION_STORE_CRC_SHIFT) +/** + * An option to configure whether CRC errors will be ignored. + * If this is set, RX will still be successful, even if + * the CRC does not pass the check. Defaults to false. + * + * @note An expected ACK that fails CRC with this option set + * will still be considered the expected ACK, terminating + * the RAIL_AutoAckConfig_t::ackTimeout period. + */ +#define RAIL_RX_OPTION_IGNORE_CRC_ERRORS (1UL << RAIL_RX_OPTION_IGNORE_CRC_ERRORS_SHIFT) + +/** + * An option to control which sync words will be accepted. Setting it to + * 0 (default) will cause the receiver to listen for SYNC1 only. Setting it to + * 1 causes the receiver to listen for either SYNC1 or SYNC2. RX appended info + * will contain which sync word was detected. Note, this only affects which + * sync word(s) are received, but not what each of the sync words actually are. + * This feature may not be available on some combinations of chips, PHYs, and + * protocols. Use the compile time symbol RAIL_SUPPORTS_DUAL_SYNC_WORDS or + * the runtime call RAIL_SupportsDualSyncWords() to check whether the + * platform supports this feature. Also, DUALSYNC may be incompatible + * with certain radio configurations. In these cases, setting this bit will + * be ignored. See the data sheet or support team for more details. + */ +#define RAIL_RX_OPTION_ENABLE_DUALSYNC (1UL << RAIL_RX_OPTION_ENABLE_DUALSYNC_SHIFT) + +/** + * An option to configure whether frames which are aborted during reception + * should continue to be tracked. Setting this option allows viewing Packet + * Trace information for frames which get discarded. Defaults to false. + * + * This option is ignored when doing a \ref RAIL_IDLE_FORCE_SHUTDOWN or + * \ref RAIL_IDLE_FORCE_SHUTDOWN_CLEAR_FLAGS. + * + * @note This option should not be used with coded PHYs since packet data + * received after the abort will not be decoded properly. + */ +#define RAIL_RX_OPTION_TRACK_ABORTED_FRAMES (1UL << RAIL_RX_OPTION_TRACK_ABORTED_FRAMES_SHIFT) + +/** + * An option to suppress capturing the appended information after + * received frames. Defaults to false. When suppressed, certain + * \ref RAIL_RxPacketDetails_t details will not be available for received + * packets whose \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ + * set. + * + * @warning This option should be changed only when the radio is idle + * and the receive FIFO is empty or has been reset, + * otherwise \ref RAIL_GetRxPacketInfo() and \ref RAIL_GetRxPacketDetails() + * may think appended info is packet data or vice-versa. + */ +#define RAIL_RX_OPTION_REMOVE_APPENDED_INFO (1UL << RAIL_RX_OPTION_REMOVE_APPENDED_INFO_SHIFT) + +/** + * An option to select the use of antenna 0 during receive (including + * \ref Auto_Ack receive). If no antenna option is selected, the packet + * will be received on the last antenna used for receive or transmit. + * Defaults to false. This option is only valid on platforms that support + * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + */ +#define RAIL_RX_OPTION_ANTENNA0 (1UL << RAIL_RX_OPTION_ANTENNA0_SHIFT) + +/** + * An option to select the use of antenna 1 during receive (including + * \ref Auto_Ack receive). If no antenna option is selected, the packet + * will be received on the last antenna used for receive or transmit. + * Defaults to false. This option is only valid on platforms that support + * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + */ +#define RAIL_RX_OPTION_ANTENNA1 (1UL << RAIL_RX_OPTION_ANTENNA1_SHIFT) + +/** + * An option combination to automatically choose an antenna during receive + * (including \ref Auto_Ack receive). If both antenna 0 and antenna 1 + * options are set, the radio will dynamically switch between antennas + * during packet detection and choose the best one for completing the + * reception. This option is only valid when the antenna diversity + * field is properly configured via Simplicity Studio. + * This option is only valid on platforms that support + * \ref Antenna_Control and have been configured via RAIL_ConfigAntenna(). + */ +#define RAIL_RX_OPTION_ANTENNA_AUTO (RAIL_RX_OPTION_ANTENNA0 | RAIL_RX_OPTION_ANTENNA1) + +/** + * An option to disable frame detection. This can be useful for doing energy + * detection without risking packet reception. Enabling this will abort any + * frame currently being received in addition to preventing further frames + * from being received. Defaults to false. + */ +#define RAIL_RX_OPTION_DISABLE_FRAME_DETECTION (1UL << RAIL_RX_OPTION_DISABLE_FRAME_DETECTION_SHIFT) + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * An option to skip DC calibration when transitioning from RX to RX. This can be + * useful for reducing the state transition time, but risks impacting + * receive capability. Enabling this bypasses DC calibration (like + * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL) + * Defaults to false. + */ +#define RAIL_RX_OPTION_SKIP_DC_CAL (1UL << RAIL_RX_OPTION_SKIP_DC_CAL_SHIFT) + +/** + * An option to skip synth calibration when transitioning from RX to RX. This can + * be useful for reducing the state transition time, but risks impacting receive + * capability. Enabling this bypasses synth calibration (like + * \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL) + * Defaults to false. + */ +#define RAIL_RX_OPTION_SKIP_SYNTH_CAL (1U << RAIL_RX_OPTION_SKIP_SYNTH_CAL_SHIFT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * An option to enable IEEE 802.15.4 RX channel switching. + * See \ref RAIL_IEEE802154_ConfigRxChannelSwitching() for more information. + * Defaults to false. + * + * @note This option is only supported on specific chips where + * \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is true. + * + * @note This option overrides \ref RAIL_RX_OPTION_ANTENNA0, + * \ref RAIL_RX_OPTION_ANTENNA1 and \ref RAIL_RX_OPTION_ANTENNA_AUTO antenna + * selection options. + */ +#define RAIL_RX_OPTION_CHANNEL_SWITCHING (1U << RAIL_RX_OPTION_CHANNEL_SWITCHING_SHIFT) + +/** + * An option to enable fast RX2RX state transition. + * + * Once enabled, the sequencer will send the radio to RXSEARCH and get ready to + * receive the next packet while still processing the previous one. This will + * reduce RX to RX state transition time but risks impacting receive capability. + * + * @note This option is only supported on specific chips where + * \ref RAIL_SUPPORTS_FAST_RX2RX is true. + */ +#define RAIL_RX_OPTION_FAST_RX2RX (1U << RAIL_RX_OPTION_FAST_RX2RX_SHIFT) + +/** + * An option to enable collision detection. + * + * Once enabled, when a collision with a strong enough packet is detected, the demod + * will stop the current packet decoding and try to detect the preamble of the incoming + * packet. + * + * @note This option is only supported on specific chips where + * \ref RAIL_SUPPORTS_COLLISION_DETECTION is true. + */ +#define RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION (1U << RAIL_RX_OPTION_ENABLE_COLLISION_DETECTION_SHIFT) + +/** A value representing all possible options. */ +#define RAIL_RX_OPTIONS_ALL 0xFFFFFFFFUL + +/** The value returned by RAIL for an invalid RSSI, in dBm. */ +#define RAIL_RSSI_INVALID_DBM (-128) +/** The value returned by RAIL for an invalid RSSI: in quarter dBm. */ +#define RAIL_RSSI_INVALID ((int16_t)(RAIL_RSSI_INVALID_DBM * 4)) +/** The lowest RSSI value returned by RAIL: in quarter dBm. */ +#define RAIL_RSSI_LOWEST ((int16_t)(RAIL_RSSI_INVALID + 1)) + +/** Maximum absolute value for RSSI offset */ +#define RAIL_RSSI_OFFSET_MAX 35 + +/** A sentinel value to indicate waiting for a valid RSSI without a timeout. */ +#define RAIL_GET_RSSI_WAIT_WITHOUT_TIMEOUT ((RAIL_Time_t)0xFFFFFFFFU) +/** A sentinel value to indicate no waiting for a valid RSSI. */ +#define RAIL_GET_RSSI_NO_WAIT ((RAIL_Time_t)0U) + +/** + * @struct RAIL_ScheduleRxConfig_t + * @brief Configures the scheduled RX algorithm. + * + * Defines the start and end times of the receive window created + * for a scheduled receive. If either start or end times are disabled, they + * will be ignored. + */ +typedef struct RAIL_ScheduleRxConfig { + /** + * The time to start receive. See startMode for more information about the + * types of start times that you can specify. + */ + RAIL_Time_t start; + /** + * How to interpret the time value specified in the start parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Use + * \ref RAIL_TIME_ABSOLUTE for absolute times, \ref RAIL_TIME_DELAY for times + * relative to the current time and \ref RAIL_TIME_DISABLED to ignore the + * start time. + */ + RAIL_TimeMode_t startMode; + /** + * The time to end receive. See endMode for more information about the types + * of end times you can specify. + */ + RAIL_Time_t end; + /** + * How to interpret the time value specified in the end parameter. See the + * \ref RAIL_TimeMode_t documentation for more information. Note that, in + * this API, if you specify a \ref RAIL_TIME_DELAY, it is relative to the + * start time if given and relative to now if none is specified. Also, using + * \ref RAIL_TIME_DISABLED means that this window will not end unless you + * explicitly call \ref RAIL_Idle() or add an end event through a future + * update to this configuration. + */ + RAIL_TimeMode_t endMode; + /** + * While in scheduled RX, you can still control the radio state via + * state transitions. This option configures whether a transition + * to RX goes back to scheduled RX or to the normal RX state. Once in the + * normal RX state, you will effectively end the scheduled RX window and can + * continue to receive indefinitely depending on the state transitions. Set + * to 1 to transition to normal RX and 0 to stay in the scheduled RX. + * + * This setting also influences the posting of + * \ref RAIL_EVENT_RX_SCHEDULED_RX_END when the scheduled Rx window is + * implicitly ended by a packet receive (any of the + * \ref RAIL_EVENTS_RX_COMPLETION events). See that event for details. + * + * @note An Rx transition to Idle state will always terminate the + * scheduled Rx window, regardless of this setting. This can be used + * to ensure Scheduled RX terminates on the first packet received + * (or first successful packet if the RX error transition is to Rx + * while the Rx success transition is to Idle). + */ + uint8_t rxTransitionEndSchedule; + /** + * This setting tells RAIL what to do with a packet being received + * when the window end event occurs. If set to 0, such a packet + * will be allowed to complete. Any other setting will cause that + * packet to be aborted. In either situation, any posting of + * \ref RAIL_EVENT_RX_SCHEDULED_RX_END is deferred briefly to when + * the packet's corresponding \ref RAIL_EVENTS_RX_COMPLETION occurs. + */ + uint8_t hardWindowEnd; +} RAIL_ScheduleRxConfig_t; + +/** + * @enum RAIL_RxPacketStatus_t + * @brief The packet status code associated with a packet received or + * currently being received. + * + * @note RECEIVING implies some packet data may be available, but + * is untrustworthy (not CRC-verified) and might disappear if the packet + * is rolled back on error. No packet details are yet available. + * @note In RX \ref RAIL_DataMethod_t::FIFO_MODE, ABORT statuses imply some + * packet data may be available, but it's incomplete and not trustworthy. + */ +RAIL_ENUM(RAIL_RxPacketStatus_t) { + /** + * The radio is idle or searching for a packet. + */ + RAIL_RX_PACKET_NONE = 0, + /** + * The packet was aborted during filtering because of illegal frame length, + * CRC or block decoding errors, other RAIL built-in protocol-specific + * packet content errors, or by the application or multiprotocol scheduler + * idling the radio with \ref RAIL_IDLE_ABORT or higher. + * + * Corresponding \ref RAIL_EVENT_RX_PACKET_ABORTED is triggered. + */ + RAIL_RX_PACKET_ABORT_FORMAT, + /** + * The packet failed address filtering. + * + * Corresponding \ref RAIL_EVENT_RX_ADDRESS_FILTERED is triggered. + */ + RAIL_RX_PACKET_ABORT_FILTERED, + /** + * The packet passed any filtering but was aborted by the application + * or multiprotocol scheduler idling the radio with \ref RAIL_IDLE_ABORT + * or higher. + * + * Corresponding \ref RAIL_EVENT_RX_PACKET_ABORTED is triggered. + */ + RAIL_RX_PACKET_ABORT_ABORTED, + /** + * The packet overflowed the receive buffer. + * + * Corresponding \ref RAIL_EVENT_RX_FIFO_OVERFLOW is triggered. + */ + RAIL_RX_PACKET_ABORT_OVERFLOW, + /** + * The packet passed any filtering but subsequently failed CRC check(s) + * block decoding, or illegal frame length, and was aborted. + * + * Corresponding \ref RAIL_EVENT_RX_FRAME_ERROR is triggered. + */ + RAIL_RX_PACKET_ABORT_CRC_ERROR, + /** + * The packet passed any filtering but subsequently failed CRC check(s) + * with \ref RAIL_RX_OPTION_IGNORE_CRC_ERRORS in effect. Can also occur + * when the packet prematurely ended successfully during filtering, + * and either the \ref RAIL_EVENT_RX_PACKET_ABORTED or + * \ref RAIL_EVENT_RX_ADDRESS_FILTERED events had been enabled + * requesting notification of such packets. + * + * Corresponding \ref RAIL_EVENT_RX_PACKET_RECEIVED is triggered. + */ + RAIL_RX_PACKET_READY_CRC_ERROR, + /** + * The packet was successfully received, passing CRC check(s). + * + * Corresponding \ref RAIL_EVENT_RX_PACKET_RECEIVED is triggered. + */ + RAIL_RX_PACKET_READY_SUCCESS, + /** + * A packet is being received and is not yet complete. + */ + RAIL_RX_PACKET_RECEIVING, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RX_PACKET_NONE ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_NONE) +#define RAIL_RX_PACKET_ABORT_FORMAT ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FORMAT) +#define RAIL_RX_PACKET_ABORT_FILTERED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_FILTERED) +#define RAIL_RX_PACKET_ABORT_ABORTED ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_ABORTED) +#define RAIL_RX_PACKET_ABORT_OVERFLOW ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_OVERFLOW) +#define RAIL_RX_PACKET_ABORT_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_ABORT_CRC_ERROR) +#define RAIL_RX_PACKET_READY_CRC_ERROR ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_CRC_ERROR) +#define RAIL_RX_PACKET_READY_SUCCESS ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_READY_SUCCESS) +#define RAIL_RX_PACKET_RECEIVING ((RAIL_RxPacketStatus_t) RAIL_RX_PACKET_RECEIVING) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @typedef RAIL_RxPacketHandle_t + * @brief A handle used to reference a packet during reception processing. + * There are several sentinel handle values that pertain to certain + * circumstances: \ref RAIL_RX_PACKET_HANDLE_INVALID, \ref + * RAIL_RX_PACKET_HANDLE_OLDEST, \ref RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE + * and \ref RAIL_RX_PACKET_HANDLE_NEWEST. + */ +typedef const void *RAIL_RxPacketHandle_t; + +/** An invalid RX packet handle value. */ +#define RAIL_RX_PACKET_HANDLE_INVALID (NULL) + +/** A special RX packet handle to refer to the oldest unreleased packet. + * This includes the newest unread packet which is possibly incomplete or not + * yet started. + * This handle is used implicitly by \ref RAIL_ReadRxFifo(). + */ +#define RAIL_RX_PACKET_HANDLE_OLDEST ((RAIL_RxPacketHandle_t) 1) + +/** A special RX packet handle to refer to the oldest unreleased + * complete packet. This never includes incomplete or unstarted packets. + * (Using \ref RAIL_RX_PACKET_HANDLE_OLDEST is inappropriate for this + * purpose because it can refer to an unstarted, incomplete, or + * unheld packet which are inappropriate to be consumed by the application.) + */ +#define RAIL_RX_PACKET_HANDLE_OLDEST_COMPLETE ((RAIL_RxPacketHandle_t) 2) + +/** A special RX packet handle to refer to the newest unreleased packet + * when in callback context. For a callback involving a completed + * receive event, this refers to the packet just completed. For + * other callback events, this refers to the next packet to be + * completed, which might be in-progress or might not have even + * started yet. + */ +#define RAIL_RX_PACKET_HANDLE_NEWEST ((RAIL_RxPacketHandle_t) 3) + +/** + * @struct RAIL_RxPacketInfo_t + * @brief Basic information about a packet being received or already + * completed and awaiting processing, including memory pointers to + * its data in the circular receive FIFO buffer. This packet information + * refers to remaining packet data that has not already been consumed + * by RAIL_ReadRxFifo(). + * @note Because the receive FIFO buffer is circular, a packet might start + * near the end of the buffer and wrap around to the beginning of + * the buffer to finish, hence the distinction between the first + * and last portions. Packets that fit without wrapping only have + * a first portion (firstPortionBytes == packetBytes and lastPortionData + * will be NULL). + */ +typedef struct RAIL_RxPacketInfo { + RAIL_RxPacketStatus_t packetStatus; /**< The packet status of this packet. */ + uint16_t packetBytes; /**< The number of packet data bytes + available to read in this packet. */ + uint16_t firstPortionBytes; /**< The number of bytes in the first portion. */ + uint8_t *firstPortionData; /**< The pointer to the first portion of packet + data containing firstPortionBytes + number of bytes. */ + uint8_t *lastPortionData; /**< The pointer to the last portion of a + packet, if any; NULL otherwise. The + number of bytes in this portion is + packetBytes - firstPortionBytes. */ + RAIL_AddrFilterMask_t filterMask; /**< A bitmask representing which address + filter(s) this packet has passed. + Will be 0 when not filtering or if + packet info is retrieved before + filtering has completed. It's + undefined on platforms lacking \ref + RAIL_SUPPORTS_ADDR_FILTER_MASK */ +} RAIL_RxPacketInfo_t; + +/** + * @struct RAIL_RxPacketDetails_t + * @brief Received packet details obtained via RAIL_GetRxPacketDetails() + * or RAIL_GetRxPacketDetailsAlt(). + * + * @note Certain details are always available, while others are only available + * if the \ref RAIL_RxOptions_t \ref RAIL_RX_OPTION_REMOVE_APPENDED_INFO + * option is not in effect and the received packet's + * \ref RAIL_RxPacketStatus_t is among the RAIL_RX_PACKET_READY_ set. + * Each detail's description indicates its availability. + * + */ +typedef struct RAIL_RxPacketDetails { + /** + * The timestamp of the received packet in the RAIL timebase. + * + * When not available it will be \ref RAIL_PACKET_TIME_INVALID. + */ + RAIL_PacketTimeStamp_t timeReceived; + /** + * Indicates whether the CRC passed or failed for the received packet. + * It is true for \ref RAIL_RX_PACKET_READY_SUCCESS packets and false + * for all others. + * + * It is always available. + */ + bool crcPassed; + /** + * Indicate whether the received packet was the expected ACK. + * It is true for the expected ACK and false otherwise. + * + * It is always available. + * + * An expected ACK is defined as a protocol-correct ACK packet + * successfully-received (\ref RAIL_RX_PACKET_READY_SUCCESS or + * \ref RAIL_RX_PACKET_READY_CRC_ERROR) and whose sync word was + * detected within the + * RAIL_AutoAckConfig_t::ackTimeout period following a transmit + * which specified \ref RAIL_TX_OPTION_WAIT_FOR_ACK, requested + * an ACK, and auto-ACK is enabled. When true, the ackTimeout + * period was terminated so no \ref RAIL_EVENT_RX_ACK_TIMEOUT + * will be subsequently posted for the transmit. + * + * A "protocol-correct ACK" applies to the 802.15.4 or Z-Wave + * protocols for which RAIL can discern the frame type and match + * the ACK's sequence number with that of the transmitted frame. + * For other protocols, the first packet successfully-received + * whose sync word was detected within the ackTimeout period is + * considered the expected ACK; upper layers are responsible for + * confirming this. + */ + bool isAck; + /** + * RSSI of the received packet in integer dBm. This RSSI measurement is + * started as soon as the sync word is detected. The duration of the + * measurement is PHY-specific. + * + * When not available it will be \ref RAIL_RSSI_INVALID_DBM. + */ + int8_t rssi; + /** + * The link quality indicator of the received packet. A zero would + * indicate a very low quality packet while a 255 would indicate a very + * high quality packet. + * + * When not available it will be 0. + */ + uint8_t lqi; + /** + * For radios and PHY configurations that support multiple sync words, this + * number is the ID of the sync word that was used for this packet. + * + * It is always available. + */ + uint8_t syncWordId; + /** + * In configurations where the radio has the option of receiving a given + * packet in multiple ways, indicates which of the sub-PHY options + * was used to receive the packet. Most radio configurations do not have + * this ability and the subPhyId is set to 0. + * + * Currently, this field is used by the BLE Coded PHY, the BLE Simulscan PHY + * and the SUN OFDM PHYs. + * In BLE cases, a value of 0 marks a 500 kbps packet, a value of 1 marks a 125 + * kbps packet, and a value of 2 marks a 1 Mbps packet. + * Also, see \ref RAIL_BLE_ConfigPhyCoded and \ref RAIL_BLE_ConfigPhySimulscan. + * + * In SUN OFDM cases, the value corresponds to the numerical value of the + * Modulation and Coding Scheme (MCS) level of the last received packet. + * The packet bitrate depends on the MCS value, as well as the OFDM option. + * Packets bitrates for SUN OFDM PHYs can be found in 802.15.4-2020 specification, + * chapter 20.3, table 20-10. + * Ex: Packet bitrate for OFDM option 1 MCS0 is 100kb/s and 2400kb/s for MCS6. + * + * In WMBUS cases, when using PHY_wMbus_ModeTC_M2O_100k_frameA with simultaneous + * RX of T and C modes enabled (\ref RAIL_WMBUS_Config()), the value corresponds + * to \ref RAIL_WMBUS_Phy_t. + * + * It is always available. + */ + uint8_t subPhyId; + /** + * For \ref Antenna_Control configurations where the device has multiple + * antennas, this indicates which antenna received the packet. When there + * is only one antenna, this will be set to the default of 0. + * + * It is always available. + */ + uint8_t antennaId; + /** + * When channel hopping is enabled, this field will contain the index + * of the channel in \ref RAIL_RxChannelHoppingConfig_t::entries on which + * this packet was received, or a sentinel value. On EFR32XG1 parts, + * on which channel hopping is not supported, this value is still part + * of the structure, but will be a meaningless value. + * + * It is always available. + */ + uint8_t channelHoppingChannelIndex; + /** + * The channel on which the packet was received. + * + * It is always available. + * + * @note It is best to fully process (empty or clear) the receive FIFO + * before changing channel configurations (\ref RAIL_ConfigChannels() + * or a built-in configuration) as unprocessed packets' channel + * could reflect the wrong configuration. On EFR32xG1 only this + * advice also applies when changing channels for receive or transmit + * where unprocessed packets' channel could reflect the new channel. + */ + uint16_t channel; +} RAIL_RxPacketDetails_t; + +/** + * @typedef RAIL_ConvertLqiCallback_t + * @brief A pointer to a function called before LQI is copied into the + * \ref RAIL_RxPacketDetails_t structure. + * + * @param[in] lqi The LQI value obtained by hardware and being readied for + * application consumption. This LQI value is in integral units ranging from + * 0 to 255. + * @param[in] rssi The RSSI value corresponding to the packet from which the + * hardware LQI value was obtained. This RSSI value is in integral dBm units. + * @return uint8_t The converted LQI value that will be loaded into the + * \ref RAIL_RxPacketDetails_t structure in preparation for application + * consumption. This value should likewise be in integral units ranging from + * 0 to 255. + */ +typedef uint8_t (*RAIL_ConvertLqiCallback_t)(uint8_t lqi, + int8_t rssi); + +/** @} */ // end of group Receive + +/****************************************************************************** + * Auto-ACK Structures + *****************************************************************************/ +/** + * @addtogroup Auto_Ack + * @{ + */ +/** + * @struct RAIL_AutoAckConfig_t + * @brief Enable/disable the auto-ACK algorithm, based on "enable". + * + * The structure provides a default state (the "success" of tx/rxTransitions + * when ACKing is enabled) for the radio to return to after an ACK + * operation occurs (transmitting or attempting to receive an ACK), or normal + * state transitions to return to in the case ACKing is + * disabled. Regardless whether the ACK operation was successful, the + * radio returns to the specified success state. + * + * ackTimeout specifies how long to stay in receive and wait for an ACK + * to start (sync detected) before issuing a RAIL_EVENT_RX_ACK_TIMEOUT + * event and return to the default state. + */ +typedef struct RAIL_AutoAckConfig { + /** + * Indicate whether auto-ACKing should be enabled or disabled. + */ + bool enable; + /** + * Define the RX ACK timeout duration in microseconds up to 65535 + * microseconds maximum. Only applied when auto-ACKing is enabled. + * The ACK timeout timer starts at the completion of a \ref + * RAIL_TX_OPTION_WAIT_FOR_ACK transmit and expires only while waiting + * for a packet (prior to SYNC detect), triggering \ref + * RAIL_EVENT_RX_ACK_TIMEOUT. During packet reception that event is + * held off until packet completion and suppressed entirely if the + * received packet is the expected ACK. + */ + uint16_t ackTimeout; + /** + * State transitions to do after receiving a packet. When auto-ACKing is + * enabled, the "error" transition is always ignored and the radio will + * return to the "success" state after any ACKing sequence + * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). + * See \ref RAIL_ConfigAutoAck for more details on this. + */ + RAIL_StateTransitions_t rxTransitions; + /** + * State transitions to do after transmitting a packet. When auto-ACKing is + * enabled, the "error" transition is always ignored and the radio will + * return to the "success" state after any ACKing sequence + * (\ref RAIL_RF_STATE_RX or \ref RAIL_RF_STATE_IDLE). + * See \ref RAIL_ConfigAutoAck for more details on this. + */ + RAIL_StateTransitions_t txTransitions; +} RAIL_AutoAckConfig_t; + +/// Acknowledgment packets cannot be longer than 64 bytes. +#define RAIL_AUTOACK_MAX_LENGTH (64U) + +/** @} */ // end of group Auto_Ack + +/****************************************************************************** + * Antenna Control + *****************************************************************************/ +/** + * @addtogroup Antenna_Control + * @{ + * + * These enumerations and structures are used with RAIL Antenna Control API. + * EFR32 supports up to two antennas with configurable pin locations. + */ + +/** Antenna path Selection enumeration. */ +RAIL_ENUM(RAIL_AntennaSel_t) { + /** Enum for antenna path 0. */ + RAIL_ANTENNA_0 = 0, + /** Enum for antenna path 1. */ + RAIL_ANTENNA_1 = 1, + /** Enum for antenna path auto. */ + RAIL_ANTENNA_AUTO = 255, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ANTENNA_0 ((RAIL_AntennaSel_t) RAIL_ANTENNA_0) +#define RAIL_ANTENNA_1 ((RAIL_AntennaSel_t) RAIL_ANTENNA_1) +#define RAIL_ANTENNA_AUTO ((RAIL_AntennaSel_t) RAIL_ANTENNA_AUTO) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_AntennaConfig_t + * @brief A configuration for antenna selection. + */ +typedef struct RAIL_AntennaConfig { + /** Antenna 0 Pin Enable */ + bool ant0PinEn; + /** Antenna 1 Pin Enable */ + bool ant1PinEn; + /** + * Antenna 0 location for ant0Port/Pin on EFR32 Series 1 + * and on EFR32 Series 2 this field is called \ref defaultPath + * (see define and usage below). + */ + uint8_t ant0Loc; + /** Antenna 0 output GPIO port */ + uint8_t ant0Port; + /** Antenna 0 output GPIO pin */ + uint8_t ant0Pin; + /** Antenna 1 location for ant1Port/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t ant1Loc; + /** Antenna 1 output GPIO port */ + uint8_t ant1Port; + /** Antenna 1 output GPIO pin */ + uint8_t ant1Pin; +} RAIL_AntennaConfig_t; + +/** + * Maps EFR32 Series 2 defaultPath onto Series 1 ant0Loc field. + * For EFR32 Series 2, defaultPath should be a \ref RAIL_AntennaSel_t + * value specifying the internal default RF path. It is ignored + * on EFR32 Series 2 parts that have only one RF path bonded + * out and on EFR32xG28 dual-band OPNs where the appropriate + * RF path is automatically set by RAIL to 0 for 2.4GHZ band + * and 1 for SubGHz band PHYs. On EFR32xG23 and EFR32xG28 + * single-band OPNs where both RF paths are bonded out this can + * be set to \ref RAIL_ANTENNA_AUTO to effect internal RF path + * diversity on PHYs supporting diversity. This avoids the need + * for an external RF switch and the associated GPIO(s) needed + * to control its antenna selection. + */ +#define defaultPath ant0Loc + +/** @} */ // end of group Antenna_Control + +/****************************************************************************** + * External_Thermistor Structures + *****************************************************************************/ +/** + * @addtogroup External_Thermistor + * @{ + */ + +/// A sentinel value to indicate an invalid thermistor measurement value. +#define RAIL_INVALID_THERMISTOR_VALUE (0xFFFFFFFFU) +/// A sentinel value to indicate an invalid PPM calculation value. +#define RAIL_INVALID_PPM_VALUE (-128) + +/** + * @struct RAIL_HFXOThermistorConfig_t + * @brief Configure the port and pin of the thermistor. + * @note This configuration is OPN dependent. + */ +typedef struct RAIL_HFXOThermistorConfig { + /** + * The GPIO port to access the thermistor. + */ + uint8_t port; + /** + * The GPIO pin to set the thermistor. + */ + uint8_t pin; +} RAIL_HFXOThermistorConfig_t; + +/** + * @struct RAIL_HFXOCompensationConfig_t + * @brief Set compensation specific parameters + */ +typedef struct RAIL_HFXOCompensationConfig { + /** + * Indicates whether the HFXO compensation in temperature is activated. + */ + bool enableCompensation; + /** + * The temperature reference delimiting the nominal zone from the critical one. + * This field is relevant if enableCompensation is set to true. + */ + int8_t zoneTemperatureC; + /** + * The temperature shift used to start a new compensation, in the nominal zone. + * This field is relevant if enableCompensation is set to true. + */ + uint8_t deltaNominal; + /** + * The temperature shift used to start a new compensation, in the critical zone. + * This field is relevant if enableCompensation is set to true. + */ + uint8_t deltaCritical; +} RAIL_HFXOCompensationConfig_t; +/** @} */ // end of group External_Thermistor + +/****************************************************************************** + * Calibration Structures + *****************************************************************************/ +/** + * @addtogroup Calibration + * @{ + * + * The EFR32 supports the Image Rejection (IR) + * calibration and a temperature-dependent calibration. The IR calibration + * can be computed once and stored off or computed each time at + * startup. Because it is PHY-specific and provides sensitivity improvements, + * it is highly recommended. The IR calibration should only be run when the + * radio is IDLE. + * + * The temperature-dependent calibrations are used to recalibrate the synth if + * the temperature crosses 0C or the temperature delta since the last + * calibration exceeds 70C while in receive. RAIL will run the VCO calibration + * automatically upon entering receive or transmit states, so the application + * can omit this calibration if the stack re-enters receive or transmit with + * enough frequency to avoid reaching the temperature delta. If the application + * does not calibrate for temperature, it's possible to miss receive packets due + * to a drift in the carrier frequency. + */ + +/** + * @typedef RAIL_CalMask_t + * @brief A calibration mask type + * + * This type is a bitmask of different RAIL calibration values. The exact + * meaning of these bits depends on what a particular chip supports. + */ +typedef uint32_t RAIL_CalMask_t; + +/** EFR32-specific temperature calibration bit. */ +#define RAIL_CAL_TEMP_VCO (0x00000001U) +/** EFR32-specific HFXO temperature check bit. + * (Ignored if platform lacks \ref RAIL_SUPPORTS_HFXO_COMPENSATION.) */ +#define RAIL_CAL_TEMP_HFXO (0x00000002U) +/** EFR32-specific HFXO compensation bit. + * (Ignored if platform lacks \ref RAIL_SUPPORTS_HFXO_COMPENSATION.) */ +#define RAIL_CAL_COMPENSATE_HFXO (0x00000004U) +/** EFR32-specific IR calibration bit */ +#define RAIL_CAL_RX_IRCAL (0x00010000U) +/** EFR32-specific Tx IR calibration bit. + * (Ignored if platform lacks \ref RAIL_SUPPORTS_OFDM_PA.) */ +#define RAIL_CAL_OFDM_TX_IRCAL (0x00100000U) + +/** A mask to run EFR32-specific IR calibrations. */ +#define RAIL_CAL_ONETIME_IRCAL (RAIL_CAL_RX_IRCAL | RAIL_CAL_OFDM_TX_IRCAL) +/** A mask to run temperature-dependent calibrations. */ +#define RAIL_CAL_TEMP (RAIL_CAL_TEMP_VCO | RAIL_CAL_TEMP_HFXO | RAIL_CAL_COMPENSATE_HFXO) +/** A mask to run one-time calibrations. */ +#define RAIL_CAL_ONETIME (RAIL_CAL_ONETIME_IRCAL) +/** A mask to run optional performance calibrations. */ +#define RAIL_CAL_PERF (0) +/** A mask for calibrations that require the radio to be off. */ +#define RAIL_CAL_OFFLINE (RAIL_CAL_ONETIME_IRCAL) +/** A mask to run all possible calibrations for this chip. */ +#define RAIL_CAL_ALL (RAIL_CAL_TEMP | RAIL_CAL_ONETIME) +/** A mask to run all pending calibrations. */ +#define RAIL_CAL_ALL_PENDING (0x00000000U) +/** An invalid calibration value. */ +#define RAIL_CAL_INVALID_VALUE (0xFFFFFFFFU) + +/** + * @def RAIL_MAX_RF_PATHS + * @brief Indicates the maximum number of RF Paths supported across all + * platforms. + */ +#define RAIL_MAX_RF_PATHS 2 + +/** + * RAIL_RxIrCalValues_t + * @brief RX IR calibration values. + * + * Platforms with fewer \ref RAIL_RF_PATHS than \ref RAIL_MAX_RF_PATHS + * will only respect and update \ref RAIL_RF_PATHS indices and ignore + * the rest. + */ +typedef uint32_t RAIL_RxIrCalValues_t[RAIL_MAX_RF_PATHS]; + +/** + * A define to set all RAIL_RxIrCalValues_t values to uninitialized. + * + * This define can be used when you have no data to pass to the calibration + * routines but wish to compute and save all possible calibrations. + */ +#define RAIL_IRCALVALUES_RX_UNINIT { \ + [0 ... RAIL_MAX_RF_PATHS - 1] = RAIL_CAL_INVALID_VALUE, \ +} + +/** + * @struct RAIL_TxIrCalValues_t + * @brief A Tx IR calibration value structure. + * + * This definition contains the set of persistent calibration values for + * OFDM on EFR32. You can set these beforehand and apply them at startup + * to save the time required to compute them. Any of these values may be + * set to RAIL_IRCAL_INVALID_VALUE to force the code to compute that + * calibration value. + * + * Only supported on platforms with \ref RAIL_SUPPORTS_OFDM_PA enabled. + */ +typedef struct RAIL_TxIrCalValues { + uint32_t dcOffsetIQ; /**< TXIRCAL result */ + uint32_t phiEpsilon; /**< TXIRCAL result */ +} RAIL_TxIrCalValues_t; + +/** + * A define to set all RAIL_TxIrCalValues_t values to uninitialized. + * + * This define can be used when you have no data to pass to the calibration + * routines but wish to compute and save all possible calibrations. + */ +#define RAIL_IRCALVALUES_TX_UNINIT { \ + RAIL_CAL_INVALID_VALUE, \ + RAIL_CAL_INVALID_VALUE, \ +} + +/** + * @struct RAIL_IrCalValues_t + * @brief An IR calibration value structure. + * + * This definition contains the set of persistent calibration values for + * EFR32. You can set these beforehand and apply them at startup to save the + * time required to compute them. Any of these values may be set to + * RAIL_IRCAL_INVALID_VALUE to force the code to compute that calibration value. + */ +typedef struct RAIL_IrCalValues { + RAIL_RxIrCalValues_t rxIrCalValues; /**< RX Image Rejection (IR) calibration value */ + RAIL_TxIrCalValues_t txIrCalValues; /**< TX Image Rejection (IR) calibration value for OFDM */ +} RAIL_IrCalValues_t; + +/** + * A define to set all RAIL_IrCalValues_t values to uninitialized. + * + * This define can be used when you have no data to pass to the calibration + * routines but wish to compute and save all possible calibrations. + */ +#define RAIL_IRCALVALUES_UNINIT { \ + RAIL_IRCALVALUES_RX_UNINIT, \ + RAIL_IRCALVALUES_TX_UNINIT, \ +} + +/** + * A define allowing Rx calibration value access compatibility + * between non-OFDM and OFDM platforms. + */ +#define RAIL_IRCALVAL(irCalStruct, rfPath) \ + (((RAIL_IrCalValues_t *)(&(irCalStruct)))->rxIrCalValues[(rfPath)]) + +/** + * @typedef RAIL_CalValues_t + * @brief A calibration value structure. + * + * This structure contains the set of persistent calibration values for + * EFR32. You can set these beforehand and apply them at startup to save the + * time required to compute them. Any of these values may be set to + * RAIL_CAL_INVALID_VALUE to force the code to compute that calibration value. + */ +typedef RAIL_IrCalValues_t RAIL_CalValues_t; + +/** + * A define to set all RAIL_CalValues_t values to uninitialized. + * + * This define can be used when you have no data to pass to the calibration + * routines but wish to compute and save all possible calibrations. + */ +#define RAIL_CALVALUES_UNINIT RAIL_IRCALVALUES_UNINIT + +/// Use this value with either TX or RX values in RAIL_SetPaCTune +/// to use whatever value is already set and do no update. This +/// value is provided to provide consistency across EFR32 chips, +/// but technically speaking, all PA capacitance tuning values are +/// invalid on EFR32XG21 parts, as RAIL_SetPaCTune is not supported +/// on those parts. +#define RAIL_PACTUNE_IGNORE (255U) + +/** @} */ // end of group Calibration + +/****************************************************************************** + * RF Sense Structures + *****************************************************************************/ +/** + * @addtogroup Rf_Sense + * @{ + */ + +/** + * A pointer to an RF Sense callback function. + * + * Consider using the event \ref RAIL_EVENT_RF_SENSED as an alternative. + */ +typedef void (*RAIL_RfSense_CallbackPtr_t)(void); + +/** + * RF Sense low sensitivity offset. + */ +#define RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET (0x20U) + +/** + * @enum RAIL_RfSenseBand_t + * @brief An enumeration for specifying the RF Sense frequency band. + */ +RAIL_ENUM(RAIL_RfSenseBand_t) { + RAIL_RFSENSE_OFF, /**< RF Sense is disabled. */ + RAIL_RFSENSE_2_4GHZ, /**< RF Sense is in 2.4 G band. */ + RAIL_RFSENSE_SUBGHZ, /**< RF Sense is in subgig band. */ + RAIL_RFSENSE_ANY, /**< RF Sense is in both bands. */ + RAIL_RFSENSE_MAX, // Must be last before sensitivity options. + RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_2_4GHZ, /**< RF Sense is in low sensitivity 2.4 G band */ + RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_SUBGHZ, /**< RF Sense is in low sensitivity subgig band */ + RAIL_RFENSE_ANY_LOW_SENSITIVITY = RAIL_RFSENSE_LOW_SENSITIVITY_OFFSET + RAIL_RFSENSE_ANY /**< RF Sense is in low sensitivity for both bands. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RFSENSE_OFF ((RAIL_RfSenseBand_t) RAIL_RFSENSE_OFF) +#define RAIL_RFSENSE_2_4GHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_2_4GHZ) +#define RAIL_RFSENSE_SUBGHZ ((RAIL_RfSenseBand_t) RAIL_RFSENSE_SUBGHZ) +#define RAIL_RFSENSE_ANY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_ANY) +#define RAIL_RFSENSE_MAX ((RAIL_RfSenseBand_t) RAIL_RFSENSE_MAX) +#define RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_2_4GHZ_LOW_SENSITIVITY) +#define RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFSENSE_SUBGHZ_LOW_SENSITIVITY) +#define RAIL_RFENSE_ANY_LOW_SENSITIVITY ((RAIL_RfSenseBand_t) RAIL_RFENSE_ANY_LOW_SENSITIVITY) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * Use the MODEM default sync word. + */ +#define RAIL_RFSENSE_USE_HW_SYNCWORD (0U) + +/** + * @struct RAIL_RfSenseSelectiveOokConfig_t + * @brief Structure to configure RFSENSE Selective(OOK) mode. + */ +typedef struct RAIL_RfSenseSelectiveOokConfig { + /** + * The frequency band(s) on which to sense the + * RF energy. To stop RF Sense, specify \ref RAIL_RFSENSE_OFF. + */ + RAIL_RfSenseBand_t band; + /** + * Syncword Length in bytes, 1-4 bytes. + * @note When \ref syncWord is set to use \ref RAIL_RFSENSE_USE_HW_SYNCWORD, + * the \ref syncWordNumBytes value will be ignored since we rely on the + * HW default settings for sync word. + */ + uint8_t syncWordNumBytes; + /** + * Sync Word Value. + * To use HW default sync word, set to \ref RAIL_RFSENSE_USE_HW_SYNCWORD. + */ + uint32_t syncWord; + /** + * The callback function, called when RF is sensed. + */ + RAIL_RfSense_CallbackPtr_t cb; +} RAIL_RfSenseSelectiveOokConfig_t; + +/** @} */ // end of group Rf_Sense + +/****************************************************************************** + * RX Channel Hopping + *****************************************************************************/ +/** + * @addtogroup Rx_Channel_Hopping RX Channel Hopping + * @{ + */ + +/** + * @enum RAIL_RxChannelHoppingMode_t + * @brief Modes by which RAIL can determine when to proceed to the next + * channel during channel hopping + */ +RAIL_ENUM(RAIL_RxChannelHoppingMode_t) { + /** + * Switch to the next channel each time the radio re-enters RX after + * packet reception or a transmit based on the corresponding \ref + * State_Transitions. A hop can also be manually triggered by calling + * \ref RAIL_CalibrateTemp() while the radio is listening. + * + * @warning This mode currently does not issue \ref + * RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE when hopping out of + * the last channel in the hop sequence. + * As a workaround, an application can monitor the current hop channel + * with \ref RAIL_GetChannelAlt(). + */ + RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL, + /** + * Switch to the next channel after a certain amount of time passes. + * The time should be specified in microseconds in \ref + * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less + * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT, + /** + * Listen in receive RX for at least a specified timeout. If, + * by the end of the timeout, the radio has packet timing, + * remain in the current channel until the radio loses it. The + * timeout should be specified in microseconds in \ref + * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less + * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE, + /** + * Listen in receive RX for at least a specified timeout. If, + * by the end of the timeout, the radio has a packet preamble, + * remain in the current channel until the radio loses it. The + * timeout should be specified in microseconds in \ref + * RAIL_RxChannelHoppingConfigEntry_t::parameter, and must be less + * than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE, + /** + * Placeholder for a reserved hopping mode that is not supported. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1, + /** + * A mode that combines modes TIMING_SENSE, PREAMBLE_SENSE, and + * TIMEOUT (sync detect) all running in parallel. Refer to \ref + * RAIL_RxChannelHoppingConfigMultiMode_t for further details. + * A pointer to that structure, allocated in global read-write + * memory and initialized to the desired configuration values, is + * specified as the \ref RAIL_RxChannelHoppingConfigEntry_t::parameter + * or \ref RAIL_RxDutyCycleConfig_t::parameter, cast appropriately: + * @code{.c} + * .parameter = (uint32_t)(void *)&hoppingConfigMultiMode, + * @endcode + * + * @note RAIL will overwrite the contents of the \ref + * RAIL_RxChannelHoppingConfigMultiMode_t during operation so it + * must be reinitialized with the desired configuration prior to + * every call to \ref RAIL_ConfigRxChannelHopping() or + * \ref RAIL_ConfigRxDutyCycle(). + * + * @note Multiple \ref RAIL_RxChannelHoppingConfigEntry_t entries may + * share the same \ref RAIL_RxChannelHoppingConfigMultiMode_t if their + * settings are identical, otherwise a separate \ref + * RAIL_RxChannelHoppingConfigMultiMode_t is needed for each + * \ref RAIL_RxChannelHoppingConfigEntry_t that uses this mode. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE, + /** + * Switch to the next channel based on the demodulation settings in the PHY + * config. This mode is PHY and chip dependent. The + * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter is ignored, and should + * be set to 0 for future compatibility. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_SQ, + /** + * Marks that the channel is concurrent with another channel, and otherwise + * behaves identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_CONC, + /** + * Indicates that this channel is a virtual channel that is concurrently + * detected with the channel indicated by the + * \ref RAIL_RxChannelHoppingConfigEntry_t::parameter. Otherwise behaves + * identically to \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ. + */ + RAIL_RX_CHANNEL_HOPPING_MODE_VT, + /** + * This is the transmit channel used for auto-ACK if the regular channel, + * specified in RAIL_RxChannelHoppingConfigEntry::parameter, is + * optimized for RX which may degrade some TX performance + */ + RAIL_RX_CHANNEL_HOPPING_MODE_TX, + /** + * A count of the basic choices in this enumeration. + */ + RAIL_RX_CHANNEL_HOPPING_MODES_COUNT, // Must be last before _WITH_OPTIONS twins + + /** + * The start of equivalent modes requiring non-default \ref + * RAIL_RxDutyCycleConfig_t::options, needed for backwards-compatibility + * with earlier \ref RAIL_RxDutyCycleConfig_t format. Non-default options + * are supported with \ref RAIL_RxChannelHoppingConfigEntry_t in all modes. + */ + RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE = 0x80, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS + = RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1 with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_SQ with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_CONC with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_VT with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS, + /** Variant of \ref RAIL_RX_CHANNEL_HOPPING_MODE_TX with options. */ + RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE) +#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE) +#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1 ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1) +#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE) +#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ) +#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC) +#define RAIL_RX_CHANNEL_HOPPING_MODE_VT ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TX ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX) +#define RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODES_WITH_OPTIONS_BASE) +#define RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMEOUT_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TIMING_SENSE_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_PREAMBLE_SENSE_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_RESERVED1_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_SQ_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_CONC_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_VT_WITH_OPTIONS) +#define RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS ((RAIL_RxChannelHoppingMode_t) RAIL_RX_CHANNEL_HOPPING_MODE_TX_WITH_OPTIONS) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * The maximum sense time supported for those \ref RAIL_RxChannelHoppingMode_t + * modes whose parameter(s) specify a sensing time. + */ +#define RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US 0x08000000UL + +/** + * @enum RAIL_RxChannelHoppingDelayMode_t + * @deprecated Set only to RAIL_RX_CHANNEL_DELAY_MODE_STATIC + */ +RAIL_ENUM(RAIL_RxChannelHoppingDelayMode_t) { + /** + * Always delay for exactly the amount of time specified + * in the delay parameter, regardless of how other channel + * hopping channels were extended via preamble sense or other means. + */ + RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC, +}; + +/** + * @typedef RAIL_RxChannelHoppingParameter_t + * @brief Rx channel hopping on-channel time + */ +typedef uint32_t RAIL_RxChannelHoppingParameter_t; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC ((RAIL_RxChannelHoppingDelayMode_t) RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_RxChannelHoppingOptions_t + * @brief Options that can customize channel hopping behavior + * on a per-hop basis. + */ +RAIL_ENUM(RAIL_RxChannelHoppingOptions_t) { + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL bit */ + RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL_SHIFT, + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL bit */ + RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT, + /** Shift position of \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD bit */ + RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT, + /** Stop hopping on this hop. */ + RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT, + /** A count of the choices in this enumeration. */ + RAIL_RX_CHANNEL_HOPPING_OPTIONS_COUNT // Must be last +}; + +/** A value representing no options enabled. */ +#define RAIL_RX_CHANNEL_HOPPING_OPTIONS_NONE 0U +/** + * All options disabled by default. + * Channel hopping will behave as described by other + * parameters as it did in RAIL 2.7 and earlier. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT RAIL_RX_CHANNEL_HOPPING_OPTIONS_NONE +/** + * @deprecated Please use \ref RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT instead. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTION_DEFAULT RAIL_RX_CHANNEL_HOPPING_OPTIONS_DEFAULT +/** + * An option to skip synth calibration while *hopping into* the channel + * specified in the current entry. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_SYNTH_CAL_SHIFT) +/** + * An option to skip DC calibration while *hopping into* the channel + * specified in the current entry. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_SKIP_DC_CAL_SHIFT) +/** + * An option to check RSSI after *hopping into* the channel specified + * in the current entry and hop if that RSSI is below the threshold + * specified in \ref RAIL_RxChannelHoppingConfigEntry_t::rssiThresholdDbm. + * This check runs in parallel with the \ref RAIL_RxChannelHoppingMode_t + * specified and may cause a hop sooner than that mode otherwise would. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD_SHIFT) +/** + * An option to stop the hopping sequence at this entry in the hop + * table. + */ +#define RAIL_RX_CHANNEL_HOPPING_OPTION_STOP (1U << RAIL_RX_CHANNEL_HOPPING_OPTION_STOP_SHIFT) + +/// @struct RAIL_RxChannelHoppingConfigMultiMode_t +/// @brief Structure that parameterizes \ref +/// RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE. +/// +/// Every \ref RAIL_RxChannelHoppingConfigEntry_t or +/// \ref RAIL_RxDutyCycleConfig_t that uses \ref +/// RAIL_RX_CHANNEL_HOPPING_MODE_MULTI_SENSE must allocate one of these +/// structures in global read-write memory to provide the settings +/// for this mode and for RAIL to use during hopping or duty cycling. +/// A pointer to this structure, cast appropriately, is what is passed +/// in the corresponding \ref RAIL_RxChannelHoppingConfigEntry_t::parameter +/// or \ref RAIL_RxDutyCycleConfig_t::parameter. +/// +/// The contents of this structure must be initialized prior to each +/// \ref RAIL_ConfigRxChannelHopping() or \ref RAIL_ConfigRxDutyCycle() +/// call and must not be touched thereafter until the next such call. +/// RAIL may change these contents during configuration or operation. +/// +/// This mode of operation functions algorithmically like this pseudocode: +/// @code{.c} +/// extern bool channelHopping; // true if channel hopping, false if duty cycling +/// extern RAIL_RxChannelHoppingConfigEntry_t *hopConfigEntry; // current channel +/// +/// static RAIL_RxChannelHoppingConfigMultiMode_t *multiParams; +/// static RAIL_Time_t rxStartTime; +/// static bool preambleSensed; +/// +/// static void hopOrSuspendRx(uint32_t delay) +/// { +/// disableDemodEvents(); +/// disableTimerEvents(); +/// stopTimer(); +/// if (channelHopping) { +/// hopToNextChannel(delay, &hopConfigEntry); // updates hopConfigEntry +/// } else { +/// suspendRx(delay); +/// } +/// onStartRx(); // resume receive after delay (on new channel if hopping) +/// } +/// +/// void onStartRx(void) // called upon entry to receive +/// { +/// rxStartTime = RAIL_GetTime(); +/// multiParams = (RAIL_RxChannelHoppingConfigMultiMode_t *) +/// (void *)hopConfigEntry->parameter; +/// startTimer(rxStartTime + multiParams->timingSense); +/// preambleSensed = false; +/// enableTimerEvents(); // timer will trigger onTimerEvent() handler +/// enableDemodEvents(); // demod will trigger onDemodEvent() handler +/// } +/// +/// void onTimerEvent(void) // called when timer expires +/// { +/// hopOrSuspendRx(hopConfigEntry->delay); +/// } +/// +/// void onDemodEvent(void) // called when demodulator state changes +/// { +/// if (DEMOD_TIMING_SENSED) { +/// stopTimer(); +/// startTimer(rxStartTime + multiParams->syncDetect); +/// } +/// if (DEMOD_TIMING_LOST) { +/// stopTimer(); +/// uint32_t newTimeout = RAIL_GetTime() + multiParams->timingReSense; +/// uint32_t limitTimeout; +/// if (preambleSensed) { +/// limitTimeout = rxStartTime + multiParams->syncDetect; +/// } else { +/// limitTimeout = rxStartTime + multiParams->preambleSense; +/// } +/// if (newTimeout > limitTimeout) { +/// newTimeout = limitTimeout; +/// } +/// if (newTimeout > RAIL_GetTime()) { +/// startTimer(newTimeout); +/// } else { +/// hopOrSuspendRx(hopConfigEntry->delay); +/// } +/// } +/// if (DEMOD_PREAMBLE_SENSED) { +/// preambleSensed = true; +/// } +/// if (DEMOD_PREAMBLE_LOST) { +/// preambleSensed = false; +/// } +/// if (DEMOD_SYNC_DETECTED) { +/// disableDemodEvents(); +/// disableTimerEvents(); +/// stopTimer(); +/// receivePacket(); // stay on channel to receive frame +/// hopOrSuspendRx(0); // continue RX per state transitions with no delay +/// } +/// } +/// @endcode + +typedef struct RAIL_RxChannelHoppingConfigMultiMode { + /** + * Switch to the next channel if sync is not detected before + * this time, in microseconds, measured from entry to Rx. + * This must be greater than preambleSense and less than + * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + uint32_t syncDetect; + /** + * Switch to the next channel if timing was sensed but then + * lost after this time, in microseconds, measured from entry + * to Rx -- unless preamble had been sensed in which case any + * switching is deferred to timingReSense and, if timing is + * regained, to syncDetect. This must be greater than timingSense + * and less than \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + uint32_t preambleSense; + /** + * Switch to the next channel if timing is not sensed before + * this time, in microseconds, measured from entry to Rx. This + * must be greater than 2 and less than + * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + uint32_t timingSense; + /** + * Switch to the next channel if timing was sensed but then + * lost and not regained before this time, in microseconds, + * measured from when timing was lost. This must be less than + * \ref RAIL_RX_CHANNEL_HOPPING_MAX_SENSE_TIME_US. + */ + uint32_t timingReSense; + /** + * Set this to 0. This field, along with the others, may be + * used internally by RAIL during configuration or operation. + */ + uint32_t status; +} RAIL_RxChannelHoppingConfigMultiMode_t; + +/** + * @struct RAIL_RxChannelHoppingConfigEntry_t + * @brief Structure that represents one of the channels that is part of a + * \ref RAIL_RxChannelHoppingConfig_t sequence of channels used in + * channel hopping. + */ +typedef struct RAIL_RxChannelHoppingConfigEntry { + /** + * The channel number to be used for this entry in the channel hopping + * sequence. If this is an invalid channel for the current PHY, the + * call to \ref RAIL_ConfigRxChannelHopping() will fail. + */ + uint16_t channel; + /** The mode by which RAIL determines when to hop to the next channel. */ + RAIL_RxChannelHoppingMode_t mode; + // Unnamed 'uint8_t reserved1[1]' pad byte field here. + /** + * Depending on the 'mode' parameter that was specified, this member + * is used to parameterize that mode. See the comments on each value of + * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. + */ + RAIL_RxChannelHoppingParameter_t parameter; + /** + * Idle time in microseconds to wait before hopping into the + * channel indicated by this entry. + */ + uint32_t delay; + /** @deprecated Set delayMode to RAIL_RX_CHANNEL_HOPPING_DELAY_MODE_STATIC. */ + RAIL_RxChannelHoppingDelayMode_t delayMode; + /** + * Bitmask of various options that can be applied to the current + * channel hop. + */ + RAIL_RxChannelHoppingOptions_t options; + /** + * The RSSI threshold (in dBm) below which a hop will occur in + * any mode when \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD is + * specified. + */ + int8_t rssiThresholdDbm; + /** + * Pad bytes reserved for future use and currently ignored. + */ + uint8_t reserved2[1]; +} RAIL_RxChannelHoppingConfigEntry_t; + +/** + * @struct RAIL_RxChannelHoppingConfig_t + * @brief Wrapper struct that will contain the sequence of + * \ref RAIL_RxChannelHoppingConfigEntry_t that represents the channel + * sequence to use during RX Channel Hopping. + */ +typedef struct RAIL_RxChannelHoppingConfig { + /** + * Pointer to contiguous global read-write memory that will be used + * by RAIL to store channel hopping information throughout its operation. + * It need not be initialized and applications should never write + * data anywhere in this buffer. + * + * @note the size of this buffer must be at least as large as + * 3 + \ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL * numberOfChannels, + * plus the sum of the sizes of the + * radioConfigDeltaAdd's of the required channels, plus the size of the + * radioConfigDeltaSubtract. In the case that one channel + * appears two or more times in your channel sequence + * (e.g., 1, 2, 3, 2), you must account for the radio configuration + * size that number of times (i.e., need to count channel 2's + * radio configuration size twice for the given example). The buffer is + * for internal use to the library. + */ + uint32_t *buffer; + /** + * This parameter must be set to the length of the buffer array, in 32 bit + * words. This way, during configuration, the software can confirm it's + * writing within the bounds of the buffer. The configuration API will return + * an error or trigger \ref RAIL_ASSERT_CHANNEL_HOPPING_BUFFER_TOO_SHORT if + * bufferLength is insufficient. + */ + uint16_t bufferLength; + /** + * The number of channels in the channel hopping sequence, which is the + * number of elements in the array that entries points to. + */ + uint8_t numberOfChannels; + /** + * A pointer to the first element of an array of \ref + * RAIL_RxChannelHoppingConfigEntry_t that represents the channels + * used during channel hopping. The length of this array must be + * numberOfChannels. + */ + RAIL_RxChannelHoppingConfigEntry_t *entries; +} RAIL_RxChannelHoppingConfig_t; + +/** + * @struct RAIL_RxDutyCycleConfig_t + * @brief Structure to configure duty cycled receive mode. + */ +typedef struct RAIL_RxDutyCycleConfig { + /** The mode by which RAIL determines when to exit RX. */ + RAIL_RxChannelHoppingMode_t mode; + /** + * Depending on the 'mode' parameter that was specified, this member + * is used to parameterize that mode. See the comments on each value of + * \ref RAIL_RxChannelHoppingMode_t to learn what to specify here. + */ + // Unnamed 'uint8_t reserved[3]' pad byte field here. + RAIL_RxChannelHoppingParameter_t parameter; + /** + * Idle time in microseconds to wait before re-entering RX. + */ + uint32_t delay; + /** + * Indicate how the timing specified in 'delay' should be applied. + */ + RAIL_RxChannelHoppingDelayMode_t delayMode; + /** + * Bitmask of various options that can be applied to the current + * duty cycle operation when the mode is >= \ref + * RAIL_RX_CHANNEL_HOPPING_MODE_MANUAL_WITH_OPTIONS (ignored otherwise). + */ + RAIL_RxChannelHoppingOptions_t options; + /** + * The RSSI threshold (in dBm) below which Rx will end in + * any mode when \ref RAIL_RX_CHANNEL_HOPPING_OPTION_RSSI_THRESHOLD + * is specified. + */ + int8_t rssiThresholdDbm; + /** + * Pad bytes reserved for future use and currently ignored. + */ + uint8_t reserved2[1]; +} RAIL_RxDutyCycleConfig_t; + +/// A sentinel value to flag an invalid channel hopping index. +#define RAIL_CHANNEL_HOPPING_INVALID_INDEX (0xFEU) + +/** @} */ // end of group Rx_Channel_Hopping + +/****************************************************************************** + * Diagnostic Structures + *****************************************************************************/ +/** + * @addtogroup Diagnostic + * @{ + */ + +/** + * @typedef RAIL_FrequencyOffset_t + * @brief Type that represents the number of Frequency Offset + * units. It is used with \ref RAIL_GetRxFreqOffset() and + * \ref RAIL_SetFreqOffset(). + * + * The units are chip-specific. For EFR32 they are radio synthesizer + * resolution steps (synthTicks) and is limited to 15 bits. + * A value of \ref RAIL_FREQUENCY_OFFSET_INVALID + * means that this value is invalid. + */ +typedef int16_t RAIL_FrequencyOffset_t; + +/** + * The maximum frequency offset value supported. + */ +#define RAIL_FREQUENCY_OFFSET_MAX ((RAIL_FrequencyOffset_t) 0x3FFF) + +/** + * The minimum frequency offset value supported. + */ +#define RAIL_FREQUENCY_OFFSET_MIN ((RAIL_FrequencyOffset_t) -RAIL_FREQUENCY_OFFSET_MAX) + +/** + * Specify an invalid frequency offset value. This will be returned if you + * call \ref RAIL_GetRxFreqOffset() at an invalid time. + */ +#define RAIL_FREQUENCY_OFFSET_INVALID ((RAIL_FrequencyOffset_t) 0x8000) + +/** + * @struct RAIL_DirectModeConfig_t + * @brief Allows the user to specify direct mode + * parameters using \ref RAIL_ConfigDirectMode(). + */ +typedef struct RAIL_DirectModeConfig { + /** Enable synchronous RX DOUT using DCLK vs. asynchronous RX DOUT. */ + bool syncRx; + /** Enable synchronous TX DIN using DCLK vs. asynchronous TX DIN. */ + bool syncTx; + + /** RX Data output (DOUT) GPIO port */ + uint8_t doutPort; + /** RX Data output (DOUT) GPIO pin */ + uint8_t doutPin; + + /** Data clock (DCLK) GPIO port. Only used in synchronous mode */ + uint8_t dclkPort; + /** Data clock (DCLK) GPIO pin. Only used in synchronous mode */ + uint8_t dclkPin; + + /** TX Data input (DIN) GPIO port */ + uint8_t dinPort; + /** TX Data input (DIN) GPIO pin */ + uint8_t dinPin; + + /** RX Data output (DOUT) location for doutPort/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t doutLoc; + /** Data clock (DCLK) location for dclkPort/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t dclkLoc; + /** TX Data input (DIN) location for tdinPort/Pin. + * Only needed on EFR32 Series 1; ignored on other platforms. */ + uint8_t dinLoc; +} RAIL_DirectModeConfig_t; + +/** + * @enum RAIL_StreamMode_t + * @brief Possible stream output modes. + */ +RAIL_ENUM(RAIL_StreamMode_t) { + RAIL_STREAM_CARRIER_WAVE = 0, /**< An unmodulated carrier wave. */ + RAIL_STREAM_PN9_STREAM = 1, /**< PN9 byte sequence. */ + RAIL_STREAM_10_STREAM = 2, /**< 101010 sequence. */ + RAIL_STREAM_CARRIER_WAVE_PHASENOISE = 3, /**< An unmodulated carrier wave with no change to PLL BW. For EFR32 Series 2, same as RAIL_STREAM_CARRIER_WAVE */ + RAIL_STREAM_RAMP_STREAM = 4, /**< ramp sequence starting at a different offset for consecutive packets. Only available for some modulations. Fall back to RAIL_STREAM_PN9_STREAM if not available. */ + RAIL_STREAM_CARRIER_WAVE_SHIFTED = 5, /**< An unmodulated carrier wave not centered on DC but shifted roughly by channel_bandwidth/6 allowing an easy check of the residual DC. Only available for OFDM PA. Fall back to RAIL_STREAM_CARRIER_WAVE_PHASENOISE if not available. */ + RAIL_STREAM_MODES_COUNT /**< A count of the choices in this enumeration. Must be last. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_STREAM_CARRIER_WAVE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE) +#define RAIL_STREAM_PN9_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_PN9_STREAM) +#define RAIL_STREAM_10_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_10_STREAM) +#define RAIL_STREAM_CARRIER_WAVE_PHASENOISE ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_PHASENOISE) +#define RAIL_STREAM_RAMP_STREAM ((RAIL_StreamMode_t) RAIL_STREAM_RAMP_STREAM) +#define RAIL_STREAM_CARRIER_WAVE_SHIFTED ((RAIL_StreamMode_t) RAIL_STREAM_CARRIER_WAVE_SHIFTED) +#define RAIL_STREAM_MODES_COUNT ((RAIL_StreamMode_t) RAIL_STREAM_MODES_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_VERIFY_DURATION_MAX + * @brief This radio state verification duration indicates to RAIL that + * all memory contents should be verified by RAIL before returning to the + * application. + */ +#define RAIL_VERIFY_DURATION_MAX 0xFFFFFFFFUL + +/** + * A pointer to a verification callback function. This will be called by the + * radio state verification feature built into RAIL when a verified memory + * value is different from its reference value. + * + * @param[in] address The address of the data in question. + * @param[in] expectedValue The expected value of the data in question. + * @param[in] actualValue The actual value of the data in question. + * @return bool True indicates a data value difference is acceptable. False + * indicates a data value difference in unacceptable. + * + * @note This callback will be issued when an address' value is different from + * its reference value and either of the following conditions are met: + * 1) The default radio configuration provided by the radio configurator is used + * for verification purposes (i.e., a custom radio configuration is not supplied + * as an input to \ref RAIL_ConfigVerification()), and the radio + * configurator has flagged the address under question as being verifiable. + * 2) A custom radio configuration is provided to the verification API (i.e., + * a custom radio configuration is supplied as an input to \ref + * RAIL_ConfigVerification()). When providing a custom radio configuration for + * verification purposes, all addresses in that configuration will be verified, + * regardless of whether or not the addresses are flagged as verifiable. + */ +typedef bool (*RAIL_VerifyCallbackPtr_t)(uint32_t address, + uint32_t expectedValue, + uint32_t actualValue); + +/** + * @struct RAIL_VerifyConfig_t + * @brief The configuration array provided to RAIL for use by the radio state + * verification feature. This structure will be populated with appropriate + * values by calling \ref RAIL_ConfigVerification(). The application should + * not set or alter any of these structure elements. + */ +typedef struct RAIL_VerifyConfig { + /** Internal verification tracking information. */ + RAIL_Handle_t correspondingHandle; + /** Internal verification tracking information. */ + uint32_t nextIndexToVerify; + /** Internal verification tracking information. */ + RAIL_RadioConfig_t override; + /** Internal verification tracking information. */ + RAIL_VerifyCallbackPtr_t cb; +} RAIL_VerifyConfig_t; + +/** @} */ // end of group Diagnostic + +/****************************************************************************** + * Energy Friendly Front End Module (EFF) + *****************************************************************************/ +/** + * @addtogroup EFF + * @{ + */ + +/** + * @enum RAIL_EffDevice_t + * @brief EFF part numbers. + * + * The part number of the attached EFF device is passed to + * \ref RAIL_ConfigEff() as \ref RAIL_EffConfig_t.device. + * The \ref rail_util_eff configures and controls + * the EFF based on the capabilities of the attached EFF. + */ +RAIL_ENUM(RAIL_EffDevice_t) { + RAIL_EFF_DEVICE_NONE = 0, /**< No EFF device attached. */ + RAIL_EFF_DEVICE_EFF01A11NMFA0, /**< +30 dBm, LNA, QFN24, +105C max ambient */ + RAIL_EFF_DEVICE_EFF01B11NMFA0, /**< PA Bypass, LNA, QFN24, +105C max ambient */ + RAIL_EFF_DEVICE_EFF01A11IMFB0, /**< +30 dBm, LNA, QFN24, +125C max ambient */ + RAIL_EFF_DEVICE_EFF01B11IMFB0, /**< PA Bypass, LNA, QFN24, +125C max ambient */ + RAIL_EFF_DEVICE_COUNT, /**< A count of the choices in this enumeration. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_EFF_DEVICE_NONE ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_NONE) +#define RAIL_EFF_DEVICE_EFF01A11NMFA0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01A11NMFA0) +#define RAIL_EFF_DEVICE_EFF01B11NMFA0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01B11NMFA0) +#define RAIL_EFF_DEVICE_EFF01A11IMFB0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01A11IMFB0) +#define RAIL_EFF_DEVICE_EFF01B11IMFB0 ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_EFF01B11IMFB0) +#define RAIL_EFF_DEVICE_COUNT ((RAIL_EffDevice_t) RAIL_EFF_DEVICE_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_EFF_SUPPORTS_TRANSMIT(x) + * @brief A macro that checks for EFFxx devices that support high power transmit + */ +#define RAIL_EFF_SUPPORTS_TRANSMIT(x) ( ((x) == RAIL_EFF_DEVICE_EFF01A11NMFA0) \ + || ((x) == RAIL_EFF_DEVICE_EFF01A11IMFB0) \ + ) +/** + * @def RAIL_EFF_SUPPORTS_RECEIVE(x) + * @brief A macro that checks for EFFxx devices that support receive + */ +#define RAIL_EFF_SUPPORTS_RECEIVE(x) ( ((x) == RAIL_EFF_DEVICE_EFF01A11NMFA0) \ + || ((x) == RAIL_EFF_DEVICE_EFF01B11NMFA0) \ + || ((x) == RAIL_EFF_DEVICE_EFF01A11IMFB0) \ + || ((x) == RAIL_EFF_DEVICE_EFF01B11IMFB0) \ + ) + +/** Maximum EFF internal temperature in Kelvin, allowing transmissions when + * \ref RAIL_SUPPORTS_EFF is enabled. + */ +#define RAIL_EFF_TEMP_THRESHOLD_MAX (383U) + +/** + * @enum RAIL_EffLnaMode_t + * @brief EFF LNA Modes. + * + * The enabled EFF LNA modes are passed to\ref RAIL_ConfigEff() as the + * \ref RAIL_EffConfig_t.enabledLnaModes. + * The \ref rail_util_eff dynamically transitions between enabled LNA modes to + * maximize receive performance. + */ +RAIL_ENUM(RAIL_EffLnaMode_t) { + RAIL_EFF_LNA_MODE_RURAL = (0x01U << 0), /**< Rural LNA Mode. */ + RAIL_EFF_LNA_MODE_URBAN = (0x01U << 1), /**< Urban LNA Mode. */ + RAIL_EFF_LNA_MODE_BYPASS = (0x01U << 2), /**< Bypass LNA Mode. */ + RAIL_EFF_LNA_MODE_COUNT = (0x01U << 3), /**< A count of the choices in this enumeration. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_EFF_LNA_MODE_RURAL ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_RURAL) +#define RAIL_EFF_LNA_MODE_URBAN ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_URBAN) +#define RAIL_EFF_LNA_MODE_BYPASS ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_BYPASS) +#define RAIL_EFF_LNA_MODE_COUNT ((RAIL_EffLnaMode_t) RAIL_EFF_LNA_MODE_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_ClpcEnable_t + * @brief EFF Closed Loop Power Control (CLPC) Enable states. + * + * The EFF CLPC Enable state is passed to \ref RAIL_ConfigEff() as the + * \ref RAIL_EffConfig_t.clpcEnable. + * The \ref rail_util_eff uses advanced power controls to tune EFF output to match + * Surface Acoustic Wave (SAW) filter losses and antenna performance. + */ +RAIL_ENUM(RAIL_ClpcEnable_t) { + RAIL_EFF_CLPC_DISABLED = 0, /**< CLPC actions are completely disabled. EFF will output but CLPC will not change modes, take power measurements or tune power output. Temperature measurements are taken.*/ + RAIL_EFF_CLPC_MODE_CHANGE = 1, /**< CLPC actions are completely disabled. EFF will output, change modes, and take measurements, but not tune power output. */ + RAIL_EFF_CLPC_POWER_SLOW = 2, /**< CLPC actions allows Slow Loop. EFF will output, change modes, and take measurements, and tune power output based on slow loop. */ + RAIL_EFF_CLPC_POWER_FAST = 3, /**< CLPC actions allows Fast Loop. EFF will output, change modes, and take measurements, and tune power output based on fast loop. */ + RAIL_EFF_CLPC_POWER_BOTH = 4, /**< CLPC actions are completely enabled. EFF will output, change modes, take measurements, and tune power output based on slow and fast loops. Default state. */ + RAIL_EFF_CLPC_POWER_SLOW_STOPPED = 5, /**< CLPC actions allows Slow Loop. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ + RAIL_EFF_CLPC_POWER_FAST_STOPPED = 6, /**< CLPC actions allows Fast Loop. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ + RAIL_EFF_CLPC_POWER_BOTH_STOPPED = 7, /**< CLPC actions are completely enabled. EFF will output, change modes, and take measurements, but not tune power output because requested output power is less than max. Internal only state. */ + RAIL_EFF_CLPC_COUNT = 8 /**< A count of the choices in this enumeration. Must be last. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_EFF_CLPC_DISABLED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_DISABLED) +#define RAIL_EFF_CLPC_MODE_CHANGE ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_MODE_CHANGE) +#define RAIL_EFF_CLPC_POWER_SLOW ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_SLOW) +#define RAIL_EFF_CLPC_POWER_FAST ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_FAST) +#define RAIL_EFF_CLPC_POWER_BOTH ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_BOTH) +#define RAIL_EFF_CLPC_POWER_SLOW_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_SLOW_STOPPED) +#define RAIL_EFF_CLPC_POWER_FAST_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_FAST_STOPPED) +#define RAIL_EFF_CLPC_POWER_BOTH_STOPPED ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_POWER_BOTH_STOPPED) +#define RAIL_EFF_CLPC_COUNT ((RAIL_ClpcEnable_t) RAIL_EFF_CLPC_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_EffModeSensor_t + * @brief EFF Closed Loop Power Control (CLPC) Mode Sensor Indices + * + * The mode sensor indices are used to access specific settings with CLPC. + */ +RAIL_ENUM(RAIL_EffModeSensor_t) { + RAIL_EFF_MODE_SENSOR_FSK_ANTV = 0, /**< CLPC FSK ANTV Sensor. */ + RAIL_EFF_MODE_SENSOR_FSK_SAW2 = 1, /**< CLPC FSK SAW2 Sensor. */ + RAIL_EFF_MODE_SENSOR_OFDM_ANTV = 2, /**< CLPC OFDM ANTV power calibration entry 1. */ + RAIL_EFF_MODE_SENSOR_OFDM_SAW2 = 3, /**< CLPC OFDM SAW2 power calibration entry 1. */ + RAIL_EFF_MODE_SENSOR_COUNT /**< A count of the choices in this enumeration. Must be last. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_EFF_MODE_SENSOR_FSK_ANTV ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_FSK_ANTV) +#define RAIL_EFF_MODE_SENSOR_FSK_SAW2 ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_FSK_SAW2) +#define RAIL_EFF_MODE_SENSOR_OFDM_ANTV ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_OFDM_ANTV) +#define RAIL_EFF_MODE_SENSOR_OFDM_SAW2 ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_OFDM_SAW2) +#define RAIL_EFF_MODE_SENSOR_COUNT ((RAIL_EffModeSensor_t) RAIL_EFF_MODE_SENSOR_COUNT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @def RAIL_EFF_MODE_SENSOR_ENUM_NAMES + * @brief A macro that is string versions of the calibration enums. + */ +#define RAIL_EFF_MODE_SENSOR_ENUM_NAMES { \ + "RAIL_EFF_MODE_SENSOR_FSK_ANTV", \ + "RAIL_EFF_MODE_SENSOR_FSK_SAW2", \ + "RAIL_EFF_MODE_SENSOR_OFDM_ANTV", \ + "RAIL_EFF_MODE_SENSOR_OFDM_SAW2", \ +} + +/** + * @def RAIL_EFF_CLPC_ENABLE_ENUM_NAMES + * @brief A macro that is string versions of the calibration enums. + */ +#define RAIL_EFF_CLPC_ENABLE_ENUM_NAMES { \ + "RAIL_EFF_CLPC_DISABLED", \ + "RAIL_EFF_CLPC_MODE_CHANGE", \ + "RAIL_EFF_CLPC_POWER_SLOW", \ + "RAIL_EFF_CLPC_POWER_FAST", \ + "RAIL_EFF_CLPC_POWER_BOTH", \ + "RAIL_EFF_CLPC_POWER_SLOW_STOPPED", \ + "RAIL_EFF_CLPC_POWER_FAST_STOPPED", \ + "RAIL_EFF_CLPC_POWER_BOTH_STOPPED", \ + "RAIL_EFF_CLPC_COUNT", \ +} + +/** @struct RAIL_EffCalConfig_t + * + * @brief Calibration data for CLPC in a specific mode. + */ +typedef struct RAIL_EffCalConfig { + RAIL_TxPower_t cal1Ddbm; /**< Measured Output Power for CAL1 (nominally 270 ddBm) */ + uint16_t cal1Mv; /**< Measured Output Voltage using sensor at CAL1 ddBm */ + RAIL_TxPower_t cal2Ddbm; /**< Measured Output Power for CAL2 (nominally at 290 ddBm) */ + uint16_t cal2Mv; /**< Measured Output Voltage using sensor at CAL2 ddBm */ +} RAIL_EffCalConfig_t; + +/** @struct RAIL_EffClpcSensorConfig_t + * + * @brief Configuration data for a CLPC sensor. + * + * A structure of type \ref RAIL_EffClpcSensorConfig_t stores curve and calibration information for a CLPC sensor. + */ +typedef struct RAIL_EffClpcSensorConfig { + int64_t coefA; /**< Coefficient A for Sensor Voltage curve. Multiplied by 1e7. */ + int64_t coefB; /**< Coefficient B for Sensor Voltage curve. Multiplied by 1e7. */ + int64_t coefC; /**< Coefficient C for Sensor Voltage curve. Multiplied by 1e7. */ + int64_t coefD; /**< Coefficient D for Sensor Voltage curve. Multiplied by 1e7. */ + RAIL_EffCalConfig_t calData; /**< Calibration data for Sensor for this mode */ + int16_t slope1e1MvPerDdbm; /**< Calculated slope * 10 for Sensor calibration, measured in mV/ddBm */ + int16_t offset290Ddbm; /**< Calculated effective offset at 290 ddBm for Sensor calibration */ +} RAIL_EffClpcSensorConfig_t; + +/** @struct RAIL_EffClpcConfig_t + * + * @brief Configuration data for CLPC in a specific mode. + * + * A structure of type \ref RAIL_EffClpcConfig_t stores calibration information for each sensor in a specific mode. + */ +typedef struct RAIL_EffClpcConfig { + RAIL_EffClpcSensorConfig_t antv; /**< ANTV sensor configuration */ + RAIL_EffClpcSensorConfig_t saw2; /**< SAW2 sensor configuration */ +} RAIL_EffClpcConfig_t; + +/** @struct RAIL_EffClpcResults_t + * + * @brief Structure for passing information from the CLPC. + * + * A structure of type \ref RAIL_EffClpcResults_t returns the measurements and decisions from the + * Closed Loop Power Control back to the application side. + */ +typedef struct RAIL_EffClpcResults { + int8_t rawShift; /**< CLPC shift directly from formula */ + int8_t clampedShift; /**< Shift after clamping to maximum allowed for this pass */ + uint8_t currIndex; /**< Powersetting table index before shifting */ + uint8_t newIndex; /**< Power table index after shifting */ +} RAIL_EffClpcResults_t; + +/** + * @struct RAIL_EffConfig_t + * + * @brief Configuration data for the attached EFF device. + * + * A structure of type \ref RAIL_EffConfig_t is passed to \ref RAIL_ConfigEff(). + */ +typedef struct RAIL_EffConfig { + RAIL_EffDevice_t device; /**< EFF Device Type */ + uint8_t testPort; /**< TEST output GPIO port */ + uint8_t testPin; /**< TEST output GPIO pin */ + RAIL_EffLnaMode_t enabledLnaModes; /**< LNA modes enable bitmask **/ + uint16_t ruralUrbanMv; /**< Trip point from rural to urban mode, in millivolts */ + uint16_t urbanBypassMv; /**< Trip point from urban to bypass mode, in millivolts */ + uint16_t lnaReserved; /**< Reserved for future use */ + uint32_t urbanDwellTimeMs; /**< Time to stay in urban mode before transitioning to rural mode, in milliseconds */ + uint32_t bypassDwellTimeMs; /**< Time to stay in bypass mode before transitioning to urban or rural mode, in milliseconds */ + RAIL_EffClpcConfig_t fskClpcConfig; /**< Config Structure for FSK CLPC settings */ + RAIL_EffClpcConfig_t ofdmClpcConfig;/**< Config Structure for OFDM CLPC settings */ + uint8_t clpcReserved; /**< Reserved for future use */ + RAIL_ClpcEnable_t clpcEnable; /**< Select CLPC mode */ + bool advProtectionEnable; /**< Indicates whether the advanced thermal protection is enabled */ + uint8_t reservedByte; /**< Word alignment */ + uint16_t tempThresholdK; /**< Temperature of EFF above which transmit + is not allowed, in degrees Kelvin */ +} RAIL_EffConfig_t; + +/** @} */ // end of group EFF + +/****************************************************************************** + * Thermal Protection + *****************************************************************************/ +/** + * @addtogroup Thermal_Protection Thermal Protection + * @{ + */ + +/** Maximum junction temperature in Kelvin. A margin is subtracted before using it when + * \ref RAIL_SUPPORTS_THERMAL_PROTECTION is enabled. + */ +#define RAIL_CHIP_TEMP_THRESHOLD_MAX (398U) + +/** + * Default number of Kelvin degrees below threshold needed to allow transmissions. + */ +#define RAIL_CHIP_TEMP_COOLDOWN_DEFAULT (7U) + +/** + * @struct RAIL_ChipTempConfig_t + * + * @brief Configuration parameters for thermal protection. + */ +typedef struct RAIL_ChipTempConfig { + bool enable; /**< Indicates whether the protection is enabled */ + uint8_t coolDownK; /**< Mandatory temperature cool down when the threshold is exceeded, + in degrees Kelvin */ + uint16_t thresholdK; /**< Temperature above which transmit is blocked, + in degrees Kelvin */ +} RAIL_ChipTempConfig_t; + +/** Number of temperature values provided for the chip thermal protection */ +#define RAIL_CHIP_TEMP_MEASURE_COUNT (3U) + +/** + * @struct RAIL_ChipTempMetrics_t + * + * @brief Data used for thermal protection. + * + */ +typedef struct RAIL_ChipTempMetrics { + uint16_t tempK; /**< Store chip temperature for metrics */ + uint16_t minTempK; /**< Minimum temperature recorded */ + uint16_t maxTempK; /**< Maximum temperature recorded */ + bool resetPending; /**< Indicates if data should be reset */ + uint8_t reservedChipTemp; /**< Reserved for future use */ +} RAIL_ChipTempMetrics_t; + +/** @} */ // end of group Thermal_Protection + +// ----------------------------------------------------------------------------- +// Retiming +// ----------------------------------------------------------------------------- +/** + * @addtogroup Retiming Retiming + * @{ + * @brief EFR32-specific retiming capability. + * @ingroup RAIL_API + * + * The EFR product families have many digital and analog modules that can run + * in parallel with a radio. These combinations can cause interference and + * degradation on the radio RX sensitivity. Retiming can + * modify the clocking of the digital modules to reduce the interference. + */ + +/** + * @enum RAIL_RetimeOptions_t + * @brief Retiming options bit shifts. + */ +RAIL_ENUM(RAIL_RetimeOptions_t) { + /** Shift position of \ref RAIL_RETIME_OPTION_HFXO bit. */ + RAIL_RETIME_OPTION_HFXO_SHIFT = 0, + /** Shift position of \ref RAIL_RETIME_OPTION_HFRCO bit. */ + RAIL_RETIME_OPTION_HFRCO_SHIFT, + /** Shift position of \ref RAIL_RETIME_OPTION_DCDC bit. */ + RAIL_RETIME_OPTION_DCDC_SHIFT, + /** Shift position of \ref RAIL_RETIME_OPTION_LCD bit. */ + RAIL_RETIME_OPTION_LCD_SHIFT, +}; + +// RAIL_RetimeOptions_t bitmasks +/** + * An option to configure HFXO retiming. + */ +#define RAIL_RETIME_OPTION_HFXO \ + (1U << RAIL_RETIME_OPTION_HFXO_SHIFT) + +/** + * An option to configure HFRCO retiming. + */ +#define RAIL_RETIME_OPTION_HFRCO \ + (1U << RAIL_RETIME_OPTION_HFRCO_SHIFT) + +/** + * An option to configure DCDC retiming. + * Ignored on platforms that lack DCDC. + */ +#define RAIL_RETIME_OPTION_DCDC \ + (1U << RAIL_RETIME_OPTION_DCDC_SHIFT) + +/** + * An option to configure LCD retiming. + * Ignored on platforms that lack LCD. + */ +#define RAIL_RETIME_OPTION_LCD \ + (1U << RAIL_RETIME_OPTION_LCD_SHIFT) + +/** A value representing no retiming options. */ +#define RAIL_RETIME_OPTIONS_NONE 0x0U + +/** A value representing all retiming options. */ +#define RAIL_RETIME_OPTIONS_ALL 0xFFU + +/** + * Configure retiming options. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] mask A bitmask containing which options should be modified. + * @param[in] options A bitmask containing desired configuration settings. + * Bit positions for each option are found in the \ref RAIL_RetimeOptions_t. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ConfigRetimeOptions(RAIL_Handle_t railHandle, + RAIL_RetimeOptions_t mask, + RAIL_RetimeOptions_t options); + +/** + * Get the currently configured retiming option. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pOptions A pointer to configured retiming options + bitmask indicating which are enabled. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_GetRetimeOptions(RAIL_Handle_t railHandle, + RAIL_RetimeOptions_t *pOptions); + +/** + * Indicate that the DCDC peripheral bus clock enable has changed allowing + * RAIL to react accordingly. + * + * @note This should be called after DCDC has been enabled or disabled. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ChangedDcdc(void); + +/** @} */ // end of group Retiming_EFR32 + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +/****************************************************************************** + * Debug Structures + *****************************************************************************/ +/** + * @addtogroup Debug + * @{ + */ + +/** + * @def RAIL_DEBUG_MODE_FREQ_OVERRIDE + * @brief A bitmask to enable the frequency override debug mode to + * manually tune to a specified frequency. Note that this should only be used + * for testing and is not as tuned as frequencies from the calculator. + */ +#define RAIL_DEBUG_MODE_FREQ_OVERRIDE 0x00000001UL + +/** + * @def RAIL_DEBUG_MODE_VALID_MASK + * @brief Any debug mode bits outside of this mask are invalid and ignored. + */ +#define RAIL_DEBUG_MODE_VALID_MASK (~(RAIL_DEBUG_MODE_FREQ_OVERRIDE)) + +/** @} */ // end of group Debug + +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** @} */ // end of RAIL_API + +#ifdef __cplusplus +} +#endif + +// Define SLI_LIBRARY_BUILD to build a library that does not include +// chip-dependent defines. This may limit functionality but allows building +// generic libraries that are not tied to any given chip. +#ifdef SLI_LIBRARY_BUILD +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +// Platform-agnostic worst-case settings and types + +#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL \ + RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL_WORST_CASE + +struct RAIL_ChannelConfigEntryAttr { + RAIL_RxIrCalValues_t calValues; + RAIL_TxIrCalValues_t txCalValues; // placeholder for size +}; + +#endif//DOXYGEN_SHOULD_SKIP_THIS +#else//!SLI_LIBRARY_BUILD + +// Include appropriate chip-specific types and APIs *after* common types, and +// *before* types that depend on chip-specific types. +#include "rail_chip_specific.h" + +// (Currently no types depend on chip-specific types.) + +#endif //SLI_LIBRARY_BUILD + +#endif // __RAIL_TYPES_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22/sl_rail_util_pa_curves.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22/sl_rail_util_pa_curves.h index d307fa0..f68e0ea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22/sl_rail_util_pa_curves.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22/sl_rail_util_pa_curves.h @@ -1,117 +1,117 @@ -/***************************************************************************//** - * @file - * @brief PA power conversion curves used by Silicon Labs PA power conversion - * functions. - * @details This file contains the curves needed convert PA power levels to - * dBm powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __PA_CURVES_H_ -#define __PA_CURVES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#define RAIL_PA_CURVES_PIECEWISE_SEGMENTS (9U) -#define RAIL_PA_CURVES_LP_VALUES (16U) - -#define RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER 85 -#define RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER -275 -//Curve is generated by Max power (in dBm) = 10, increment(in dBm) = 3, segments = 8 -#define RAIL_PA_CURVES_2P4_HP_VBAT_CURVES \ - { { 255, 100, 30 }, \ - { 127, 3355, -171056 }, \ - { 54, 951, -9651 }, \ - { 28, 345, 14060 }, \ - { 17, 189, 15304 }, \ - { 11, 113, 13588 }, \ - { 7, 73, 11317 }, \ - { 5, 55, 9733 }, \ - { 3, 20, 5375 } } - -#define RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER 0 -#define RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER -163 -#define RAIL_PA_CURVES_2P4_LP_VBAT_CURVES \ - { \ - -287, /*! Power Level 0 */ \ - -167, /*! Power Level 1 */ \ - -113, /*! Power Level 2 */ \ - -83, /*! Power Level 3 */ \ - -63, /*! Power Level 4 */ \ - -48, /*! Power Level 5 */ \ - -36, /*! Power Level 6 */ \ - -28, /*! Power Level 7 */ \ - -21, /*! Power Level 8 */ \ - -14, /*! Power Level 9 */ \ - -10, /*! Power Level 10 */ \ - -6, /*! Power Level 11 */ \ - -3, /*! Power Level 12 */ \ - 0, /*! Power Level 13 */ \ - 3, /*! Power Level 14 */ \ - 5, /*! Power Level 15 */ \ - } -// *INDENT-OFF* -// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in -// RAIL_InitTxPowerCurves, assuming battery powered operation -#define RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT \ - static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHp = { \ - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, \ - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, \ - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, \ - }; \ - static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = \ - RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; -// *INDENT-OFF* - -#define RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT \ - { \ - .curves = { \ - { \ - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, \ - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, \ - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, \ - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, \ - .conversion = { .powerCurve = &RAIL_piecewiseDataHp }, \ - }, \ - { \ - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, \ - .segments = 0U, \ - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, \ - }, \ - } \ - } -// *INDENT-OFF* - -#ifdef __cplusplus -} -#endif - -#endif +/***************************************************************************//** + * @file + * @brief PA power conversion curves used by Silicon Labs PA power conversion + * functions. + * @details This file contains the curves needed convert PA power levels to + * dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __PA_CURVES_H_ +#define __PA_CURVES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define RAIL_PA_CURVES_PIECEWISE_SEGMENTS (9U) +#define RAIL_PA_CURVES_LP_VALUES (16U) + +#define RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER 85 +#define RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER -275 +//Curve is generated by Max power (in dBm) = 10, increment(in dBm) = 3, segments = 8 +#define RAIL_PA_CURVES_2P4_HP_VBAT_CURVES \ + { { 255, 100, 30 }, \ + { 127, 3355, -171056 }, \ + { 54, 951, -9651 }, \ + { 28, 345, 14060 }, \ + { 17, 189, 15304 }, \ + { 11, 113, 13588 }, \ + { 7, 73, 11317 }, \ + { 5, 55, 9733 }, \ + { 3, 20, 5375 } } + +#define RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER 0 +#define RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER -163 +#define RAIL_PA_CURVES_2P4_LP_VBAT_CURVES \ + { \ + -287, /*! Power Level 0 */ \ + -167, /*! Power Level 1 */ \ + -113, /*! Power Level 2 */ \ + -83, /*! Power Level 3 */ \ + -63, /*! Power Level 4 */ \ + -48, /*! Power Level 5 */ \ + -36, /*! Power Level 6 */ \ + -28, /*! Power Level 7 */ \ + -21, /*! Power Level 8 */ \ + -14, /*! Power Level 9 */ \ + -10, /*! Power Level 10 */ \ + -6, /*! Power Level 11 */ \ + -3, /*! Power Level 12 */ \ + 0, /*! Power Level 13 */ \ + 3, /*! Power Level 14 */ \ + 5, /*! Power Level 15 */ \ + } +// *INDENT-OFF* +// Macro to declare the variables needed to initialize RAIL_TxPowerCurvesConfig_t for use in +// RAIL_InitTxPowerCurves, assuming battery powered operation +#define RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT \ + static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHp = { \ + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, \ + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, \ + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, \ + }; \ + static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = \ + RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; +// *INDENT-OFF* + +#define RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT \ + { \ + .curves = { \ + { \ + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, \ + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, \ + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, \ + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, \ + .conversion = { .powerCurve = &RAIL_piecewiseDataHp }, \ + }, \ + { \ + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, \ + .segments = 0U, \ + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, \ + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, \ + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, \ + }, \ + } \ + } +// *INDENT-OFF* + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c index 6375b67..19f6097 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c @@ -1,746 +1,746 @@ -/***************************************************************************//** - * @file - * @brief PA power conversion functions provided to the customer as source for - * highest level of customization. - * @details This file contains the curves and logic that convert PA power - * levels to dBm powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -// For details on how to use this plugin, see -// https://www.silabs.com/documents/public/application-notes/an1127-power-amplifier-power-conversion-functions.pdf - -#include "em_device.h" -#include "em_cmu.h" -#include "pa_conversions_efr32.h" -#include "rail.h" - -#define MAX(a, b) ((a) > (b) ? (a) : (b)) - -static RAIL_TxPowerCurvesConfigAlt_t powerCurvesState; - -// Make sure SUPPORTED_PA_INDICES match the per-platform PA curves -// provided by RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT and resulting -// RAIL_TxPowerCurvesConfigAlt_t! -#ifndef SUPPORTED_PA_INDICES -#if defined(_SILICON_LABS_32B_SERIES_1) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - 1U, /* 2P4GIG_LP */ \ - RAIL_NUM_PA, /* 2P4GIG_LLP */ \ - RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ - RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ - 2U, /* SUBGIG_HP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - 1U, /* 2P4GIG_MP */ \ - 2U, /* 2P4GIG_LP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - 1U, /* 2P4GIG_LP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) -#define SUPPORTED_PA_INDICES { \ - RAIL_NUM_PA, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - RAIL_NUM_PA, /* 2P4GIG_LP */ \ - RAIL_NUM_PA, /* 2P4GIG_LLP */ \ - RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ - RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ - 0U, /* SUBGIG_HP */ \ - 1U, /* SUBGIG_MP */ \ - 2U, /* SUBGIG_LP */ \ - 3U, /* SUBGIG_LLP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - 1U, /* 2P4GIG_LP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) -#define SUPPORTED_PA_INDICES { \ - RAIL_NUM_PA, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - RAIL_NUM_PA, /* 2P4GIG_LP */ \ - RAIL_NUM_PA, /* 2P4GIG_LLP */ \ - RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ - 0U, /* SUBGIG_POWERSETTING_TABLE */ \ - RAIL_NUM_PA, /* SUBGIG_HP */ \ - RAIL_NUM_PA, /* SUBGIG_MP */ \ - RAIL_NUM_PA, /* SUBGIG_LP */ \ - RAIL_NUM_PA, /* SUBGIG_LLP */ \ - RAIL_NUM_PA, /* SUBGIG_HIGHEST */ \ - 1U, /* OFDM_PA_POWERSETTING_TABLE */ \ - 2U, /* SUBGIG_EFF_POWERSETTING_TABLE */ \ - 3U, /* OFDM_PA_EFF_POWERSETTING_TABLE */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - 1U, /* 2P4GIG_LP */ \ - /* The rest are unsupported */ \ -} -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#define SUPPORTED_PA_INDICES { \ - 0U, /* 2P4GIG_HP */ \ - RAIL_NUM_PA, /* 2P4GIG_MP */ \ - RAIL_NUM_PA, /* 2P4GIG_LP */ \ - RAIL_NUM_PA, /* 2P4GIG_LLP */ \ - RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ - RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ - 1U, /* SUBGIG_HP */ \ - 2U, /* SUBGIG_MP */ \ - 3U, /* SUBGIG_LP */ \ - 4U, /* SUBGIG_LLP */ \ - /* The rest are unsupported */ \ -} -#else -#error "unknown platform" -#endif -#endif - -static const uint8_t supportedPaIndices[] = SUPPORTED_PA_INDICES; - -#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - #define PA_CONVERSION_MINIMUM_PWRLVL 1U -#else - #define PA_CONVERSION_MINIMUM_PWRLVL 0U -#endif - -// This macro is defined when Silicon Labs builds this into the library as WEAK -// to ensure it can be overriden by customer versions of these functions. The macro -// should *not* be defined in a customer build. -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurves_t *RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode) -{ - static RAIL_TxPowerCurves_t powerCurves; - RAIL_TxPowerLevel_t maxPowerLevel, minPowerLevel; - if (RAIL_SupportsTxPowerModeAlt(RAIL_EFR32_HANDLE, - &mode, - &maxPowerLevel, - &minPowerLevel) - && (mode < sizeof(supportedPaIndices)) - && (supportedPaIndices[mode] < RAIL_NUM_PA)) { - const RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - const RAIL_TxPowerCurveAlt_t *curve = modeInfo->conversion.powerCurve; - // Check for an invalid power curve - if (curve == NULL) { - return NULL; - } - -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { - powerCurves.maxPower = modeInfo->maxPowerDbm; - powerCurves.minPower = modeInfo->minPowerDbm; - // Mapping table does not have RAIL_TxPowerCurveSegment_t segments - powerCurves.powerParams = NULL; - } else -#endif - { - powerCurves.maxPower = curve->maxPower; - powerCurves.minPower = curve->minPower; - powerCurves.powerParams = &curve->powerParams[0]; - } - return &powerCurves; - } - return NULL; -} - -// This function will not be supported for any parts after efr32xg1x -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config) -{ -#ifdef _SILICON_LABS_32B_SERIES_1 - // First PA is 2.4 GHz high power, using a piecewise fit - RAIL_PaDescriptor_t *current = &powerCurvesState.curves[0]; - current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR; - current->segments = config->piecewiseSegments; - current->min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN; - current->max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX; - static RAIL_TxPowerCurveAlt_t txPower2p4 = { - .minPower = 0U, - .maxPower = 0U, - .powerParams = { // The current max number of piecewise segments is 8 - { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, - { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, - } - }; - txPower2p4.maxPower = config->txPowerSgCurves->maxPower; - txPower2p4.minPower = config->txPowerSgCurves->minPower; - (void) memcpy(&txPower2p4.powerParams[0], - config->txPowerSgCurves->powerParams, - config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t)); - current->conversion.powerCurve = &txPower2p4; - - // Second PA is 2.4 GHz low power, using a mapping table - current = &powerCurvesState.curves[1]; - current->algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE; - current->segments = 0U; - current->min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN; - current->max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX; - current->conversion.mappingTable = config->txPower24LpCurves; - - // Third and final PA is Sub-GHz, using a piecewise fit - current = &powerCurvesState.curves[2]; - current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR; - current->segments = config->piecewiseSegments; - current->min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN; - current->max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX; - static RAIL_TxPowerCurveAlt_t txPowerSubGig = { - .minPower = 0U, - .maxPower = 0U, - .powerParams = { // The current max number of piecewise segments is 8 - { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, - { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, - } - }; - txPowerSubGig.maxPower = config->txPowerSgCurves->maxPower; - txPowerSubGig.minPower = config->txPowerSgCurves->minPower; - (void) memcpy(&txPowerSubGig.powerParams[0], - config->txPowerSgCurves->powerParams, - config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t)); - current->conversion.powerCurve = &txPowerSubGig; - - return RAIL_STATUS_NO_ERROR; -#else - (void) config; - return RAIL_STATUS_INVALID_CALL; -#endif -} - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config) -{ - RAIL_VerifyTxPowerCurves(config); - - powerCurvesState = *config; - - return RAIL_STATUS_NO_ERROR; -} - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, - RAIL_TxPower_t *minPower, RAIL_TxPower_t *maxPower, - RAIL_TxPowerLevel_t *step) -{ - (void)railHandle; -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - if ((mode < sizeof(supportedPaIndices)) - && (supportedPaIndices[mode] < RAIL_NUM_PA)) { - RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - *minPower = modeInfo->minPowerDbm; - *maxPower = modeInfo->maxPowerDbm; - *step = modeInfo->step; - return (RAIL_PaPowerSetting_t*)(modeInfo->conversion.mappingTable); - } - return NULL; -#else - (void)mode; - (void)minPower; - (void)maxPower; - (void)step; - return NULL; -#endif -} - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPower_t power) -{ - (void)railHandle; - // This function is called internally from the RAIL library, - // so if the user never calls RAIL_InitTxPowerCurves - even - // if they never intend to use dBm values in their code - - // they'll always hit the assert below. Give the user a way - // to not have to call RAIL_InitTxPowerCurves if they don't - // care about dBm values by picking a dBm value that returns the - // highest RAIL_TxPowerLevel_t possible. In other words, when - // a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX - // is converted to raw units, the max RAIL_TxPowerLevel_t will be - // returned. When compared to the current power level of the PA, - // it will always be greater, indicating that no power coercion - // is necessary to comply with channel limitations. - if (power >= RAIL_TX_POWER_MAX) { - return 255U; - } - - if ((mode < sizeof(supportedPaIndices)) - && (supportedPaIndices[mode] < RAIL_NUM_PA)) { - RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { - RAIL_TxPower_t minPower = modeInfo->minPowerDbm; - RAIL_TxPower_t maxPower = modeInfo->maxPowerDbm; - RAIL_TxPowerLevel_t step = modeInfo->step; - - // Cap the power to within the range of the mapping table - if (power < minPower) { - power = minPower; - } else if (power > maxPower) { - power = maxPower; - } else { - // Power level is within bounds (MISRA required else) - } - - uint32_t powerIndex = (power - minPower) / step; - RAIL_SetPaPowerSetting(railHandle, modeInfo->conversion.mappingTable[powerIndex], minPower, maxPower, power); - return 0U; - } -#endif - - // If we're in low power mode, just use the simple lookup table - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { - // Binary search through the lookup table to find the closest power level - // without going over. - uint32_t lower = 0U; - // Track the high side of the estimate - uint32_t powerIndex = modeInfo->max - minPowerLevel; - - while (lower < powerIndex) { - // Calculate the midpoint of the current range - uint32_t index = powerIndex - (powerIndex - lower) / 2U; - if (power < modeInfo->conversion.mappingTable[index]) { - powerIndex = index - 1U; - } else { - lower = index; - } - } - return (RAIL_TxPowerLevel_t)(powerIndex + minPowerLevel); - } - - // Here we know we're using the piecewise linear conversion - RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve; - // Check for valid paParams before using them - if (paParams == NULL) { - return 0U; - } - - // Cap the power based on the PA settings. - if (power > paParams->maxPower) { - // If we go above the maximum dbm the chip supports - // Then provide maximum powerLevel - power = paParams->maxPower; - } else if (power < paParams->minPower) { - // If we go below the minimum we want included in the curve fit, force it. - power = paParams->minPower; - } else { - // Do nothing, power is OK - } - // Map the power value to a 0 - 7 curveIndex value - //There are 8 segments of step size of RAIL_TX_POWER_CURVE_INCREMENT in deci dBm - //starting from maximum RAIL_TX_POWER_CURVE_MAX in deci dBm - // These are just starting points to give the code - // a rough idea of which segment to use, based on - // how they were fit. Adjustments are made later on - // if this turns out to be incorrect. - RAIL_TxPower_t txPowerMax = RAIL_TX_POWER_CURVE_DEFAULT_MAX; - RAIL_TxPower_t txPowerIncrement = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT; - int16_t curveIndex = 0; - // if the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID - //It is an extra curve segment to depict the maxpower and increment - // (in deci-dBm) used while generating the curves. - // The extra segment is only present when curve segment is generated by - //using values different than the default - RAIL_TX_POWER_CURVE_DEFAULT_MAX - // and RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT. - if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { - curveIndex += 1; - txPowerMax = (RAIL_TxPower_t) paParams->powerParams[0].slope; - txPowerIncrement = (RAIL_TxPower_t) paParams->powerParams[0].intercept; - } - - curveIndex += (txPowerMax - power) / txPowerIncrement; - if ((curveIndex > ((int16_t)modeInfo->segments - 1)) - || (curveIndex < 0)) { - curveIndex = ((int16_t)modeInfo->segments - 1); - } - - uint32_t powerLevel; - do { - // Select the correct piecewise segment to use for conversion. - RAIL_TxPowerCurveSegment_t const *powerParams = - &paParams->powerParams[curveIndex]; - - // powerLevel can only go down to 0. - int32_t powerLevelInt = powerParams->intercept + ((int32_t)powerParams->slope * (int32_t)power); - if (powerLevelInt < 0) { - powerLevel = 0U; - } else { - powerLevel = (uint32_t) powerLevelInt; - } - // RAIL_LIB-8330: Modified from adding 500 to adding 92, this was tested on xg21 as being the highest - // number we can use without exceeding the requested power in dBm - powerLevel = ((powerLevel + 92U) / 1000U); - - // In case it turns out the resultant power level was too low and we have - // to recalculate with the next curve... - curveIndex++; - } while ((curveIndex < (int16_t)modeInfo->segments) - && (powerLevel <= paParams->powerParams[curveIndex].maxPowerLevel)); - - // We already know that curveIndex is at most modeInfo->segments - if (powerLevel > paParams->powerParams[curveIndex - 1].maxPowerLevel) { - powerLevel = paParams->powerParams[curveIndex - 1].maxPowerLevel; - } - - // If we go below the minimum we want included in the curve fit, force it. - if (powerLevel < minPowerLevel) { - powerLevel = minPowerLevel; - } - - return (RAIL_TxPowerLevel_t)powerLevel; - } - return 0U; -} - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPowerLevel_t powerLevel) -{ - (void)railHandle; - - if ((mode < sizeof(supportedPaIndices)) - && (supportedPaIndices[mode] < RAIL_NUM_PA)) { - RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { - // Limit the max power level - if (powerLevel > modeInfo->max) { - powerLevel = modeInfo->max; - } - - // We 1-index low power PA power levels, but of course arrays are 0 indexed - powerLevel -= MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); - - //If the index calculation above underflowed, then provide the lowest array index. - if (powerLevel > (modeInfo->max - modeInfo->min)) { - powerLevel = 0U; - } - return modeInfo->conversion.mappingTable[powerLevel]; - } else { -#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - // Although 0 is a legitimate power on non-2.4 LP PA's and can be set via - // "RAIL_SetTxPower(railHandle, 0)" it is MUCH lower than power - // level 1 (approximately -50 dBm). Including it in the piecewise - // linear fit would skew the curve substantially, so we exclude it - // from the conversion. - if (powerLevel == 0U) { - return -500; - } -#endif - - RAIL_TxPowerCurveAlt_t const *powerCurve = modeInfo->conversion.powerCurve; - // Check for a valid powerCurve pointer before using it - if (powerCurve == NULL) { - return RAIL_TX_POWER_MIN; - } - - RAIL_TxPowerCurveSegment_t const *powerParams = powerCurve->powerParams; - - // Hard code the extremes (i.e. don't use the curve fit) in order - // to make it clear that we are reaching the extent of the chip's - // capabilities - if (powerLevel <= modeInfo->min) { - return powerCurve->minPower; - } else if (powerLevel >= modeInfo->max) { - return powerCurve->maxPower; - } else { - // Power level is within bounds (MISRA required else) - } - - // Figure out which parameter to use based on the power level - uint8_t x = 0; - uint8_t upperBound = modeInfo->segments - 1U; - - // If the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID, - // then it is an additional curve segment that stores maxpower and increment - // (in deci-dBm) used to generate the curves. - // The extra info segment is present only if the curves were generated using - // values other than default - RAIL_TX_POWER_CURVE_DEFAULT_MAX and - // RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT. - if ((powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { - x = 1U; // skip over the first entry - } - - for (; x < upperBound; x++) { - if (powerParams[x + 1U].maxPowerLevel < powerLevel) { - break; - } - } - int32_t power; - power = ((1000 * (int32_t)(powerLevel)) - powerParams[x].intercept); - power = ((power + ((int32_t)powerParams[x].slope / 2)) / (int32_t)powerParams[x].slope); - - if (power > powerCurve->maxPower) { - return powerCurve->maxPower; - } else if (power < powerCurve->minPower) { - return powerCurve->minPower; - } else { - return (RAIL_TxPower_t)power; - } - } - } - return RAIL_TX_POWER_MIN; -} - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPower_t *maxPower, - RAIL_TxPower_t *increment) -{ - (void)railHandle; - if ((mode < sizeof(supportedPaIndices)) - && (supportedPaIndices[mode] < RAIL_NUM_PA)) { - RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { - *maxPower = modeInfo->maxPowerDbm; - *increment = modeInfo->step; - return RAIL_STATUS_NO_ERROR; - } -#endif - - //The power max info only for available Linear fit - if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { - return RAIL_STATUS_INVALID_CALL; - } - *maxPower = RAIL_TX_POWER_CURVE_DEFAULT_MAX; - *increment = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT; - RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve; - if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { - *maxPower = paParams->powerParams[0].slope; - *increment = (RAIL_TxPower_t)paParams->powerParams[0].intercept; - } - return RAIL_STATUS_NO_ERROR; - } - return RAIL_STATUS_INVALID_PARAMETER; -} - -// This macro is defined when Silicon Labs builds curves into the library as WEAK -// to ensure it can be overriden by customer versions of these functions. It -// should *not* be defined in a customer build. -#if !defined(RAIL_PA_CONVERSIONS_WEAK) && !defined(HAL_CONFIG) - -#include "sl_rail_util_pa_config.h" - -void sl_rail_util_pa_init(void) -{ -#if SL_RAIL_UTIL_PA_VOLTAGE_MV > 1800 - (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesVbat); -#else - (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesDcdc); -#endif -#if SL_RAIL_UTIL_PA_CALIBRATION_ENABLE - RAIL_EnablePaCal(true); -#endif -} - -#if RAIL_SUPPORTS_2P4GHZ_BAND -static RAIL_TxPowerConfig_t txPowerConfig2p4Ghz = { - .mode = SL_RAIL_UTIL_PA_SELECTION_2P4GHZ, - .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, - .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US, -}; -#endif -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void) -{ -#if RAIL_SUPPORTS_2P4GHZ_BAND - return &txPowerConfig2p4Ghz; -#else - return NULL; -#endif -} - -#if RAIL_SUPPORTS_SUBGHZ_BAND -static RAIL_TxPowerConfig_t txPowerConfigSubGhz = { - .mode = SL_RAIL_UTIL_PA_SELECTION_SUBGHZ, - .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, - .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US, -}; -#endif -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void) -{ -#if RAIL_SUPPORTS_SUBGHZ_BAND - return &txPowerConfigSubGhz; -#else - return NULL; -#endif -} - -#if RAIL_SUPPORTS_OFDM_PA -#ifndef SL_RAIL_UTIL_PA_SELECTION_OFDM -#define SL_RAIL_UTIL_PA_SELECTION_OFDM RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE -#endif -static RAIL_TxPowerConfig_t txPowerConfigOFDM = { - .mode = SL_RAIL_UTIL_PA_SELECTION_OFDM, - .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, -}; -#endif // RAIL_SUPPORTS_OFDM_PA -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void) -{ -#if RAIL_SUPPORTS_OFDM_PA - return &txPowerConfigOFDM; -#else - return NULL; -#endif // RAIL_SUPPORTS_OFDM_PA -} - -void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, - const RAIL_ChannelConfigEntry_t *entry) -{ - if (!RAIL_IsPaAutoModeEnabled(rail_handle)) { - RAIL_TxPowerConfig_t currentTxPowerConfig; - RAIL_TxPowerConfig_t *newTxPowerConfigPtr; - RAIL_Status_t status; - - // Get current TX Power Config. - status = RAIL_GetTxPowerConfig(rail_handle, ¤tTxPowerConfig); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't get TX Power Config - } - -#if RAIL_SUPPORTS_DUAL_BAND - // Determine new TX Power Config. - if (entry->baseFrequency < 1000000000UL) { - newTxPowerConfigPtr = &txPowerConfigSubGhz; - } else { - newTxPowerConfigPtr = &txPowerConfig2p4Ghz; - } -#else - (void) entry; -#if RAIL_SUPPORTS_2P4GHZ_BAND - newTxPowerConfigPtr = &txPowerConfig2p4Ghz; -#else - newTxPowerConfigPtr = &txPowerConfigSubGhz; -#endif -#endif - -#if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG - if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) { -#if RAIL_SUPPORTS_OFDM_PA - if (RAIL_SupportsTxPowerMode(rail_handle, - txPowerConfigOFDM.mode, - NULL)) { - // Apply OFDM Power Config. - status = RAIL_ConfigTxPower(rail_handle, &txPowerConfigOFDM); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power Config - } - // Set default TX power after RAIL_ConfigTxPower. - status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power - } - } -#endif // RAIL_SUPPORTS_OFDM_PA - // Apply FSK Power Config. - status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power Config - } - // Set default TX power after RAIL_ConfigTxPower. - status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power - } - } -#else - // Call RAIL_ConfigTxPower only if TX Power Config mode has changed. - if (currentTxPowerConfig.mode != newTxPowerConfigPtr->mode) { - // Save current TX power before RAIL_ConfigTxPower (because not preserved). - RAIL_TxPower_t txPowerDeciDbm; - if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) { - txPowerDeciDbm = SL_RAIL_UTIL_PA_POWER_DECI_DBM; - } else { - txPowerDeciDbm = RAIL_GetTxPowerDbm(rail_handle); - } - - // Apply new TX Power Config. - status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power Config - } - // Restore TX power after RAIL_ConfigTxPower. - status = RAIL_SetTxPowerDbm(rail_handle, txPowerDeciDbm); - if (status != RAIL_STATUS_NO_ERROR) { - while (true) { - } // Error: Can't set TX Power - } - // If requested a HIGHEST setting, update it with the real one selected - // to short-circuit the next time through here since HIGHEST never - // matches the real PA returned by RAIL_GetTxPowerConfig(), causing - // reconfiguration of the same PA on every callback. - if (false - #ifdef RAIL_TX_POWER_MODE_2P4GIG_HIGHEST - || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) - #endif - #ifdef RAIL_TX_POWER_MODE_SUBGIG_HIGHEST - || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_SUBGIG_HIGHEST) - #endif - ) { - (void) RAIL_GetTxPowerConfig(rail_handle, ¤tTxPowerConfig); - newTxPowerConfigPtr->mode = currentTxPowerConfig.mode; - } - } -#endif - } // !RAIL_IsPaAutoModeEnabled -} -#endif // !RAIL_PA_CONVERSIONS_WEAK +/***************************************************************************//** + * @file + * @brief PA power conversion functions provided to the customer as source for + * highest level of customization. + * @details This file contains the curves and logic that convert PA power + * levels to dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +// For details on how to use this plugin, see +// https://www.silabs.com/documents/public/application-notes/an1127-power-amplifier-power-conversion-functions.pdf + +#include "em_device.h" +#include "em_cmu.h" +#include "pa_conversions_efr32.h" +#include "rail.h" + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +static RAIL_TxPowerCurvesConfigAlt_t powerCurvesState; + +// Make sure SUPPORTED_PA_INDICES match the per-platform PA curves +// provided by RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT and resulting +// RAIL_TxPowerCurvesConfigAlt_t! +#ifndef SUPPORTED_PA_INDICES +#if defined(_SILICON_LABS_32B_SERIES_1) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + 1U, /* 2P4GIG_LP */ \ + RAIL_NUM_PA, /* 2P4GIG_LLP */ \ + RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ + RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ + 2U, /* SUBGIG_HP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + 1U, /* 2P4GIG_MP */ \ + 2U, /* 2P4GIG_LP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 2) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + 1U, /* 2P4GIG_LP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) +#define SUPPORTED_PA_INDICES { \ + RAIL_NUM_PA, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + RAIL_NUM_PA, /* 2P4GIG_LP */ \ + RAIL_NUM_PA, /* 2P4GIG_LLP */ \ + RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ + RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ + 0U, /* SUBGIG_HP */ \ + 1U, /* SUBGIG_MP */ \ + 2U, /* SUBGIG_LP */ \ + 3U, /* SUBGIG_LLP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + 1U, /* 2P4GIG_LP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 5) +#define SUPPORTED_PA_INDICES { \ + RAIL_NUM_PA, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + RAIL_NUM_PA, /* 2P4GIG_LP */ \ + RAIL_NUM_PA, /* 2P4GIG_LLP */ \ + RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ + 0U, /* SUBGIG_POWERSETTING_TABLE */ \ + RAIL_NUM_PA, /* SUBGIG_HP */ \ + RAIL_NUM_PA, /* SUBGIG_MP */ \ + RAIL_NUM_PA, /* SUBGIG_LP */ \ + RAIL_NUM_PA, /* SUBGIG_LLP */ \ + RAIL_NUM_PA, /* SUBGIG_HIGHEST */ \ + 1U, /* OFDM_PA_POWERSETTING_TABLE */ \ + 2U, /* SUBGIG_EFF_POWERSETTING_TABLE */ \ + 3U, /* OFDM_PA_EFF_POWERSETTING_TABLE */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + 1U, /* 2P4GIG_LP */ \ + /* The rest are unsupported */ \ +} +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#define SUPPORTED_PA_INDICES { \ + 0U, /* 2P4GIG_HP */ \ + RAIL_NUM_PA, /* 2P4GIG_MP */ \ + RAIL_NUM_PA, /* 2P4GIG_LP */ \ + RAIL_NUM_PA, /* 2P4GIG_LLP */ \ + RAIL_NUM_PA, /* 2P4GIG_HIGHEST */ \ + RAIL_NUM_PA, /* SUBGIG_POWERSETTING_TABLE */ \ + 1U, /* SUBGIG_HP */ \ + 2U, /* SUBGIG_MP */ \ + 3U, /* SUBGIG_LP */ \ + 4U, /* SUBGIG_LLP */ \ + /* The rest are unsupported */ \ +} +#else +#error "unknown platform" +#endif +#endif + +static const uint8_t supportedPaIndices[] = SUPPORTED_PA_INDICES; + +#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + #define PA_CONVERSION_MINIMUM_PWRLVL 1U +#else + #define PA_CONVERSION_MINIMUM_PWRLVL 0U +#endif + +// This macro is defined when Silicon Labs builds this into the library as WEAK +// to ensure it can be overriden by customer versions of these functions. The macro +// should *not* be defined in a customer build. +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurves_t *RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode) +{ + static RAIL_TxPowerCurves_t powerCurves; + RAIL_TxPowerLevel_t maxPowerLevel, minPowerLevel; + if (RAIL_SupportsTxPowerModeAlt(RAIL_EFR32_HANDLE, + &mode, + &maxPowerLevel, + &minPowerLevel) + && (mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + const RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; + const RAIL_TxPowerCurveAlt_t *curve = modeInfo->conversion.powerCurve; + // Check for an invalid power curve + if (curve == NULL) { + return NULL; + } + +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { + powerCurves.maxPower = modeInfo->maxPowerDbm; + powerCurves.minPower = modeInfo->minPowerDbm; + // Mapping table does not have RAIL_TxPowerCurveSegment_t segments + powerCurves.powerParams = NULL; + } else +#endif + { + powerCurves.maxPower = curve->maxPower; + powerCurves.minPower = curve->minPower; + powerCurves.powerParams = &curve->powerParams[0]; + } + return &powerCurves; + } + return NULL; +} + +// This function will not be supported for any parts after efr32xg1x +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config) +{ +#ifdef _SILICON_LABS_32B_SERIES_1 + // First PA is 2.4 GHz high power, using a piecewise fit + RAIL_PaDescriptor_t *current = &powerCurvesState.curves[0]; + current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR; + current->segments = config->piecewiseSegments; + current->min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN; + current->max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX; + static RAIL_TxPowerCurveAlt_t txPower2p4 = { + .minPower = 0U, + .maxPower = 0U, + .powerParams = { // The current max number of piecewise segments is 8 + { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, + { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, + } + }; + txPower2p4.maxPower = config->txPowerSgCurves->maxPower; + txPower2p4.minPower = config->txPowerSgCurves->minPower; + (void) memcpy(&txPower2p4.powerParams[0], + config->txPowerSgCurves->powerParams, + config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t)); + current->conversion.powerCurve = &txPower2p4; + + // Second PA is 2.4 GHz low power, using a mapping table + current = &powerCurvesState.curves[1]; + current->algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE; + current->segments = 0U; + current->min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN; + current->max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX; + current->conversion.mappingTable = config->txPower24LpCurves; + + // Third and final PA is Sub-GHz, using a piecewise fit + current = &powerCurvesState.curves[2]; + current->algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR; + current->segments = config->piecewiseSegments; + current->min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN; + current->max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX; + static RAIL_TxPowerCurveAlt_t txPowerSubGig = { + .minPower = 0U, + .maxPower = 0U, + .powerParams = { // The current max number of piecewise segments is 8 + { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, + { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, { 0U, 0U, 0U }, + } + }; + txPowerSubGig.maxPower = config->txPowerSgCurves->maxPower; + txPowerSubGig.minPower = config->txPowerSgCurves->minPower; + (void) memcpy(&txPowerSubGig.powerParams[0], + config->txPowerSgCurves->powerParams, + config->piecewiseSegments * sizeof(RAIL_TxPowerCurveSegment_t)); + current->conversion.powerCurve = &txPowerSubGig; + + return RAIL_STATUS_NO_ERROR; +#else + (void) config; + return RAIL_STATUS_INVALID_CALL; +#endif +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config) +{ + RAIL_VerifyTxPowerCurves(config); + + powerCurvesState = *config; + + return RAIL_STATUS_NO_ERROR; +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_PaPowerSetting_t *RAIL_GetPowerSettingTable(RAIL_Handle_t railHandle, RAIL_TxPowerMode_t mode, + RAIL_TxPower_t *minPower, RAIL_TxPower_t *maxPower, + RAIL_TxPowerLevel_t *step) +{ + (void)railHandle; +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + if ((mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + RAIL_PaDescriptor_t *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; + *minPower = modeInfo->minPowerDbm; + *maxPower = modeInfo->maxPowerDbm; + *step = modeInfo->step; + return (RAIL_PaPowerSetting_t*)(modeInfo->conversion.mappingTable); + } + return NULL; +#else + (void)mode; + (void)minPower; + (void)maxPower; + (void)step; + return NULL; +#endif +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +RAIL_TxPowerLevel_t RAIL_ConvertDbmToRaw(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t power) +{ + (void)railHandle; + // This function is called internally from the RAIL library, + // so if the user never calls RAIL_InitTxPowerCurves - even + // if they never intend to use dBm values in their code - + // they'll always hit the assert below. Give the user a way + // to not have to call RAIL_InitTxPowerCurves if they don't + // care about dBm values by picking a dBm value that returns the + // highest RAIL_TxPowerLevel_t possible. In other words, when + // a channel dBm limitation greater than or equal to \ref RAIL_TX_POWER_MAX + // is converted to raw units, the max RAIL_TxPowerLevel_t will be + // returned. When compared to the current power level of the PA, + // it will always be greater, indicating that no power coercion + // is necessary to comply with channel limitations. + if (power >= RAIL_TX_POWER_MAX) { + return 255U; + } + + if ((mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; + uint32_t minPowerLevel = MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { + RAIL_TxPower_t minPower = modeInfo->minPowerDbm; + RAIL_TxPower_t maxPower = modeInfo->maxPowerDbm; + RAIL_TxPowerLevel_t step = modeInfo->step; + + // Cap the power to within the range of the mapping table + if (power < minPower) { + power = minPower; + } else if (power > maxPower) { + power = maxPower; + } else { + // Power level is within bounds (MISRA required else) + } + + uint32_t powerIndex = (power - minPower) / step; + RAIL_SetPaPowerSetting(railHandle, modeInfo->conversion.mappingTable[powerIndex], minPower, maxPower, power); + return 0U; + } +#endif + + // If we're in low power mode, just use the simple lookup table + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { + // Binary search through the lookup table to find the closest power level + // without going over. + uint32_t lower = 0U; + // Track the high side of the estimate + uint32_t powerIndex = modeInfo->max - minPowerLevel; + + while (lower < powerIndex) { + // Calculate the midpoint of the current range + uint32_t index = powerIndex - (powerIndex - lower) / 2U; + if (power < modeInfo->conversion.mappingTable[index]) { + powerIndex = index - 1U; + } else { + lower = index; + } + } + return (RAIL_TxPowerLevel_t)(powerIndex + minPowerLevel); + } + + // Here we know we're using the piecewise linear conversion + RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve; + // Check for valid paParams before using them + if (paParams == NULL) { + return 0U; + } + + // Cap the power based on the PA settings. + if (power > paParams->maxPower) { + // If we go above the maximum dbm the chip supports + // Then provide maximum powerLevel + power = paParams->maxPower; + } else if (power < paParams->minPower) { + // If we go below the minimum we want included in the curve fit, force it. + power = paParams->minPower; + } else { + // Do nothing, power is OK + } + // Map the power value to a 0 - 7 curveIndex value + //There are 8 segments of step size of RAIL_TX_POWER_CURVE_INCREMENT in deci dBm + //starting from maximum RAIL_TX_POWER_CURVE_MAX in deci dBm + // These are just starting points to give the code + // a rough idea of which segment to use, based on + // how they were fit. Adjustments are made later on + // if this turns out to be incorrect. + RAIL_TxPower_t txPowerMax = RAIL_TX_POWER_CURVE_DEFAULT_MAX; + RAIL_TxPower_t txPowerIncrement = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT; + int16_t curveIndex = 0; + // if the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID + //It is an extra curve segment to depict the maxpower and increment + // (in deci-dBm) used while generating the curves. + // The extra segment is only present when curve segment is generated by + //using values different than the default - RAIL_TX_POWER_CURVE_DEFAULT_MAX + // and RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT. + if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { + curveIndex += 1; + txPowerMax = (RAIL_TxPower_t) paParams->powerParams[0].slope; + txPowerIncrement = (RAIL_TxPower_t) paParams->powerParams[0].intercept; + } + + curveIndex += (txPowerMax - power) / txPowerIncrement; + if ((curveIndex > ((int16_t)modeInfo->segments - 1)) + || (curveIndex < 0)) { + curveIndex = ((int16_t)modeInfo->segments - 1); + } + + uint32_t powerLevel; + do { + // Select the correct piecewise segment to use for conversion. + RAIL_TxPowerCurveSegment_t const *powerParams = + &paParams->powerParams[curveIndex]; + + // powerLevel can only go down to 0. + int32_t powerLevelInt = powerParams->intercept + ((int32_t)powerParams->slope * (int32_t)power); + if (powerLevelInt < 0) { + powerLevel = 0U; + } else { + powerLevel = (uint32_t) powerLevelInt; + } + // RAIL_LIB-8330: Modified from adding 500 to adding 92, this was tested on xg21 as being the highest + // number we can use without exceeding the requested power in dBm + powerLevel = ((powerLevel + 92U) / 1000U); + + // In case it turns out the resultant power level was too low and we have + // to recalculate with the next curve... + curveIndex++; + } while ((curveIndex < (int16_t)modeInfo->segments) + && (powerLevel <= paParams->powerParams[curveIndex].maxPowerLevel)); + + // We already know that curveIndex is at most modeInfo->segments + if (powerLevel > paParams->powerParams[curveIndex - 1].maxPowerLevel) { + powerLevel = paParams->powerParams[curveIndex - 1].maxPowerLevel; + } + + // If we go below the minimum we want included in the curve fit, force it. + if (powerLevel < minPowerLevel) { + powerLevel = minPowerLevel; + } + + return (RAIL_TxPowerLevel_t)powerLevel; + } + return 0U; +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +RAIL_TxPower_t RAIL_ConvertRawToDbm(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPowerLevel_t powerLevel) +{ + (void)railHandle; + + if ((mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { + // Limit the max power level + if (powerLevel > modeInfo->max) { + powerLevel = modeInfo->max; + } + + // We 1-index low power PA power levels, but of course arrays are 0 indexed + powerLevel -= MAX(modeInfo->min, PA_CONVERSION_MINIMUM_PWRLVL); + + //If the index calculation above underflowed, then provide the lowest array index. + if (powerLevel > (modeInfo->max - modeInfo->min)) { + powerLevel = 0U; + } + return modeInfo->conversion.mappingTable[powerLevel]; + } else { +#if defined(_SILICON_LABS_32B_SERIES_1) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + // Although 0 is a legitimate power on non-2.4 LP PA's and can be set via + // "RAIL_SetTxPower(railHandle, 0)" it is MUCH lower than power + // level 1 (approximately -50 dBm). Including it in the piecewise + // linear fit would skew the curve substantially, so we exclude it + // from the conversion. + if (powerLevel == 0U) { + return -500; + } +#endif + + RAIL_TxPowerCurveAlt_t const *powerCurve = modeInfo->conversion.powerCurve; + // Check for a valid powerCurve pointer before using it + if (powerCurve == NULL) { + return RAIL_TX_POWER_MIN; + } + + RAIL_TxPowerCurveSegment_t const *powerParams = powerCurve->powerParams; + + // Hard code the extremes (i.e. don't use the curve fit) in order + // to make it clear that we are reaching the extent of the chip's + // capabilities + if (powerLevel <= modeInfo->min) { + return powerCurve->minPower; + } else if (powerLevel >= modeInfo->max) { + return powerCurve->maxPower; + } else { + // Power level is within bounds (MISRA required else) + } + + // Figure out which parameter to use based on the power level + uint8_t x = 0; + uint8_t upperBound = modeInfo->segments - 1U; + + // If the first curve segment starts with RAIL_TX_POWER_LEVEL_INVALID, + // then it is an additional curve segment that stores maxpower and increment + // (in deci-dBm) used to generate the curves. + // The extra info segment is present only if the curves were generated using + // values other than default - RAIL_TX_POWER_CURVE_DEFAULT_MAX and + // RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT. + if ((powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { + x = 1U; // skip over the first entry + } + + for (; x < upperBound; x++) { + if (powerParams[x + 1U].maxPowerLevel < powerLevel) { + break; + } + } + int32_t power; + power = ((1000 * (int32_t)(powerLevel)) - powerParams[x].intercept); + power = ((power + ((int32_t)powerParams[x].slope / 2)) / (int32_t)powerParams[x].slope); + + if (power > powerCurve->maxPower) { + return powerCurve->maxPower; + } else if (power < powerCurve->minPower) { + return powerCurve->minPower; + } else { + return (RAIL_TxPower_t)power; + } + } + } + return RAIL_TX_POWER_MIN; +} + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t *maxPower, + RAIL_TxPower_t *increment) +{ + (void)railHandle; + if ((mode < sizeof(supportedPaIndices)) + && (supportedPaIndices[mode] < RAIL_NUM_PA)) { + RAIL_PaDescriptor_t const *modeInfo = &powerCurvesState.curves[supportedPaIndices[mode]]; +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) { + *maxPower = modeInfo->maxPowerDbm; + *increment = modeInfo->step; + return RAIL_STATUS_NO_ERROR; + } +#endif + + //The power max info only for available Linear fit + if (modeInfo->algorithm == RAIL_PA_ALGORITHM_MAPPING_TABLE) { + return RAIL_STATUS_INVALID_CALL; + } + *maxPower = RAIL_TX_POWER_CURVE_DEFAULT_MAX; + *increment = RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT; + RAIL_TxPowerCurveAlt_t const *paParams = modeInfo->conversion.powerCurve; + if ((paParams->powerParams[0].maxPowerLevel) == RAIL_TX_POWER_LEVEL_INVALID) { + *maxPower = paParams->powerParams[0].slope; + *increment = (RAIL_TxPower_t)paParams->powerParams[0].intercept; + } + return RAIL_STATUS_NO_ERROR; + } + return RAIL_STATUS_INVALID_PARAMETER; +} + +// This macro is defined when Silicon Labs builds curves into the library as WEAK +// to ensure it can be overriden by customer versions of these functions. It +// should *not* be defined in a customer build. +#if !defined(RAIL_PA_CONVERSIONS_WEAK) && !defined(HAL_CONFIG) + +#include "sl_rail_util_pa_config.h" + +void sl_rail_util_pa_init(void) +{ +#if SL_RAIL_UTIL_PA_VOLTAGE_MV > 1800 + (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesVbat); +#else + (void)RAIL_InitTxPowerCurvesAlt(&RAIL_TxPowerCurvesDcdc); +#endif +#if SL_RAIL_UTIL_PA_CALIBRATION_ENABLE + RAIL_EnablePaCal(true); +#endif +} + +#if RAIL_SUPPORTS_2P4GHZ_BAND +static RAIL_TxPowerConfig_t txPowerConfig2p4Ghz = { + .mode = SL_RAIL_UTIL_PA_SELECTION_2P4GHZ, + .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, + .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US, +}; +#endif +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void) +{ +#if RAIL_SUPPORTS_2P4GHZ_BAND + return &txPowerConfig2p4Ghz; +#else + return NULL; +#endif +} + +#if RAIL_SUPPORTS_SUBGHZ_BAND +static RAIL_TxPowerConfig_t txPowerConfigSubGhz = { + .mode = SL_RAIL_UTIL_PA_SELECTION_SUBGHZ, + .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, + .rampTime = SL_RAIL_UTIL_PA_RAMP_TIME_US, +}; +#endif +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void) +{ +#if RAIL_SUPPORTS_SUBGHZ_BAND + return &txPowerConfigSubGhz; +#else + return NULL; +#endif +} + +#if RAIL_SUPPORTS_OFDM_PA +#ifndef SL_RAIL_UTIL_PA_SELECTION_OFDM +#define SL_RAIL_UTIL_PA_SELECTION_OFDM RAIL_TX_POWER_MODE_OFDM_PA_POWERSETTING_TABLE +#endif +static RAIL_TxPowerConfig_t txPowerConfigOFDM = { + .mode = SL_RAIL_UTIL_PA_SELECTION_OFDM, + .voltage = SL_RAIL_UTIL_PA_VOLTAGE_MV, +}; +#endif // RAIL_SUPPORTS_OFDM_PA +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void) +{ +#if RAIL_SUPPORTS_OFDM_PA + return &txPowerConfigOFDM; +#else + return NULL; +#endif // RAIL_SUPPORTS_OFDM_PA +} + +void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry) +{ + if (!RAIL_IsPaAutoModeEnabled(rail_handle)) { + RAIL_TxPowerConfig_t currentTxPowerConfig; + RAIL_TxPowerConfig_t *newTxPowerConfigPtr; + RAIL_Status_t status; + + // Get current TX Power Config. + status = RAIL_GetTxPowerConfig(rail_handle, ¤tTxPowerConfig); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't get TX Power Config + } + +#if RAIL_SUPPORTS_DUAL_BAND + // Determine new TX Power Config. + if (entry->baseFrequency < 1000000000UL) { + newTxPowerConfigPtr = &txPowerConfigSubGhz; + } else { + newTxPowerConfigPtr = &txPowerConfig2p4Ghz; + } +#else + (void) entry; +#if RAIL_SUPPORTS_2P4GHZ_BAND + newTxPowerConfigPtr = &txPowerConfig2p4Ghz; +#else + newTxPowerConfigPtr = &txPowerConfigSubGhz; +#endif +#endif + +#if RAIL_IEEE802154_SUPPORTS_DUAL_PA_CONFIG + if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) { +#if RAIL_SUPPORTS_OFDM_PA + if (RAIL_SupportsTxPowerMode(rail_handle, + txPowerConfigOFDM.mode, + NULL)) { + // Apply OFDM Power Config. + status = RAIL_ConfigTxPower(rail_handle, &txPowerConfigOFDM); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power Config + } + // Set default TX power after RAIL_ConfigTxPower. + status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power + } + } +#endif // RAIL_SUPPORTS_OFDM_PA + // Apply FSK Power Config. + status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power Config + } + // Set default TX power after RAIL_ConfigTxPower. + status = RAIL_SetTxPowerDbm(rail_handle, SL_RAIL_UTIL_PA_POWER_DECI_DBM); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power + } + } +#else + // Call RAIL_ConfigTxPower only if TX Power Config mode has changed. + if (currentTxPowerConfig.mode != newTxPowerConfigPtr->mode) { + // Save current TX power before RAIL_ConfigTxPower (because not preserved). + RAIL_TxPower_t txPowerDeciDbm; + if (currentTxPowerConfig.mode == RAIL_TX_POWER_MODE_NONE) { + txPowerDeciDbm = SL_RAIL_UTIL_PA_POWER_DECI_DBM; + } else { + txPowerDeciDbm = RAIL_GetTxPowerDbm(rail_handle); + } + + // Apply new TX Power Config. + status = RAIL_ConfigTxPower(rail_handle, newTxPowerConfigPtr); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power Config + } + // Restore TX power after RAIL_ConfigTxPower. + status = RAIL_SetTxPowerDbm(rail_handle, txPowerDeciDbm); + if (status != RAIL_STATUS_NO_ERROR) { + while (true) { + } // Error: Can't set TX Power + } + // If requested a HIGHEST setting, update it with the real one selected + // to short-circuit the next time through here since HIGHEST never + // matches the real PA returned by RAIL_GetTxPowerConfig(), causing + // reconfiguration of the same PA on every callback. + if (false + #ifdef RAIL_TX_POWER_MODE_2P4GIG_HIGHEST + || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_2P4GIG_HIGHEST) + #endif + #ifdef RAIL_TX_POWER_MODE_SUBGIG_HIGHEST + || (newTxPowerConfigPtr->mode == RAIL_TX_POWER_MODE_SUBGIG_HIGHEST) + #endif + ) { + (void) RAIL_GetTxPowerConfig(rail_handle, ¤tTxPowerConfig); + newTxPowerConfigPtr->mode = currentTxPowerConfig.mode; + } + } +#endif + } // !RAIL_IsPaAutoModeEnabled +} +#endif // !RAIL_PA_CONVERSIONS_WEAK diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h index 07dfc1e..2ca354d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.h @@ -1,190 +1,190 @@ -/***************************************************************************//** - * @file - * @brief PA power conversion functions provided to the customer as source for - * highest level of customization. - * @details This file contains the curves and logic that convert PA power - * levels to dBm powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef PA_CONVERSIONS_EFR32_H -#define PA_CONVERSIONS_EFR32_H - -#include "rail_types.h" - -// This macro is defined when Silicon Labs builds curves into the library as WEAK -// to ensure it can be overriden by customer versions of these functions. It -// should *not* be defined in a customer build. -#if !defined(RAIL_PA_CONVERSIONS_WEAK) -#ifdef SL_RAIL_UTIL_PA_CONFIG_HEADER -#include SL_RAIL_UTIL_PA_CONFIG_HEADER -#else -#include "sl_rail_util_pa_conversions_efr32_config.h" -#endif -#endif - -#ifdef HAL_CONFIG -#include "hal-config.h" -#ifdef HAL_PA_CURVE_HEADER -#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER -#undef SL_RAIL_UTIL_PA_CURVE_HEADER -#endif -#define SL_RAIL_UTIL_PA_CURVE_HEADER HAL_PA_CURVE_HEADER -#endif -#endif - -#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER -#include SL_RAIL_UTIL_PA_CURVE_HEADER -#else -#include "pa_curves_efr32.h" -#endif - -#ifdef SL_RAIL_UTIL_PA_CURVE_TYPES -#include SL_RAIL_UTIL_PA_CURVE_TYPES -#else -#include "pa_curve_types_efr32.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/// The curves to be used when battery voltage powers transmission -extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat; - -/// The curves to be used when the DC-DC converter powers transmission -extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc; - -/** - * Initialize TxPower curves. - * - * @param[in] txPowerCurvesConfig Struct containing pointers to custom - * tx power curves. - * @return RAIL_Status_t indicating success or an error. - * - * @deprecated function will no longer be supported - * for any chips released after EFRXG1X parts. Please use - * RAIL_InitTxPowerCurvesAlt instead. - */ -RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config); - -/** - * Initialize TxPower curves. - * - * @param[in] txPowerCurvesConfig Struct containing pointers to custom - * tx power curves. - * @return RAIL_Status_t indicating success or an error. - * - */ -RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config); - -/** - * Gets the curve that should be used for conversion functions based on the - * current PA configuration. - * - * @param[in] mode PA mode whose curves are needed. - * @return RAIL_TxPowerCurves_t that should be used for conversion functions. - * - * @note: If the mode is not supported by the the chip, - * then NULL will be returned. - */ -RAIL_TxPowerCurves_t const * RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode); - -/** - * Gets the maximum power in deci-dBm that should be used for calculating - * the segments and to find right curve segment to convert Dbm to raw power - * level for a specific PA. - * For the PAs with \ref RAIL_PaConversionAlgorithm_t - * \ref RAIL_PA_ALGORITHM_PIECEWISE_LINEAR , if the curves are generated with - * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and - * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first - * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to - * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the - * maxPower and increment in deci-dBm respectively. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] mode PA mode whose curves are needed. - * @param[in] maxpower A pointer to memory allocated to hold the maxpower in - * deci-dBm used in calculation of curve segments . - * A NULL configuration will produce undefined behavior. - * @param[in] increment A pointer to memory allocated to hold the increment in - * deci-dBm used in calculation of curve segments. - * A NULL configuration will produce undefined behavior. - * @return RAIL_Status_t indicating success or an error. - * - */ -RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle, - RAIL_TxPowerMode_t mode, - RAIL_TxPower_t *maxpower, - RAIL_TxPower_t *increment); - -/** - * Initialize PA TX Curves - * - */ -void sl_rail_util_pa_init(void); - -/** - * Get a pointer to the TX Power Config 2.4 GHz structure. - * - * @return a pointer to the TX Power Config stucture. - * - */ -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void); - -/** - * Get a pointer to the TX Power Config Sub-GHz structure. - * - * @return a pointer to the TX Power Config stucture. - * - */ -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void); - -/** - * Get a pointer to the TX Power Config OFDM structure. - * - * @return a pointer to the TX Power Config stucture. - * - */ -RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void); - -/** - * Provide a channel config change callback capable of configuring the PA - * correctly. - * - * @param[in] rail_handle The RAIL handle being passed into this callback. - * @param[in] entry The channel config entry being switched to by hardware. - * - */ -void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, - const RAIL_ChannelConfigEntry_t *entry); - -#ifdef __cplusplus -} -#endif - -#endif // PA_CONVERSIONS_EFR32_H +/***************************************************************************//** + * @file + * @brief PA power conversion functions provided to the customer as source for + * highest level of customization. + * @details This file contains the curves and logic that convert PA power + * levels to dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PA_CONVERSIONS_EFR32_H +#define PA_CONVERSIONS_EFR32_H + +#include "rail_types.h" + +// This macro is defined when Silicon Labs builds curves into the library as WEAK +// to ensure it can be overriden by customer versions of these functions. It +// should *not* be defined in a customer build. +#if !defined(RAIL_PA_CONVERSIONS_WEAK) +#ifdef SL_RAIL_UTIL_PA_CONFIG_HEADER +#include SL_RAIL_UTIL_PA_CONFIG_HEADER +#else +#include "sl_rail_util_pa_conversions_efr32_config.h" +#endif +#endif + +#ifdef HAL_CONFIG +#include "hal-config.h" +#ifdef HAL_PA_CURVE_HEADER +#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER +#undef SL_RAIL_UTIL_PA_CURVE_HEADER +#endif +#define SL_RAIL_UTIL_PA_CURVE_HEADER HAL_PA_CURVE_HEADER +#endif +#endif + +#ifdef SL_RAIL_UTIL_PA_CURVE_HEADER +#include SL_RAIL_UTIL_PA_CURVE_HEADER +#else +#include "pa_curves_efr32.h" +#endif + +#ifdef SL_RAIL_UTIL_PA_CURVE_TYPES +#include SL_RAIL_UTIL_PA_CURVE_TYPES +#else +#include "pa_curve_types_efr32.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/// The curves to be used when battery voltage powers transmission +extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat; + +/// The curves to be used when the DC-DC converter powers transmission +extern const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc; + +/** + * Initialize TxPower curves. + * + * @param[in] txPowerCurvesConfig Struct containing pointers to custom + * tx power curves. + * @return RAIL_Status_t indicating success or an error. + * + * @deprecated function will no longer be supported + * for any chips released after EFRXG1X parts. Please use + * RAIL_InitTxPowerCurvesAlt instead. + */ +RAIL_Status_t RAIL_InitTxPowerCurves(const RAIL_TxPowerCurvesConfig_t *config); + +/** + * Initialize TxPower curves. + * + * @param[in] txPowerCurvesConfig Struct containing pointers to custom + * tx power curves. + * @return RAIL_Status_t indicating success or an error. + * + */ +RAIL_Status_t RAIL_InitTxPowerCurvesAlt(const RAIL_TxPowerCurvesConfigAlt_t *config); + +/** + * Gets the curve that should be used for conversion functions based on the + * current PA configuration. + * + * @param[in] mode PA mode whose curves are needed. + * @return RAIL_TxPowerCurves_t that should be used for conversion functions. + * + * @note: If the mode is not supported by the the chip, + * then NULL will be returned. + */ +RAIL_TxPowerCurves_t const * RAIL_GetTxPowerCurve(RAIL_TxPowerMode_t mode); + +/** + * Gets the maximum power in deci-dBm that should be used for calculating + * the segments and to find right curve segment to convert Dbm to raw power + * level for a specific PA. + * For the PAs with \ref RAIL_PaConversionAlgorithm_t + * \ref RAIL_PA_ALGORITHM_PIECEWISE_LINEAR , if the curves are generated with + * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and + * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first + * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to + * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the + * maxPower and increment in deci-dBm respectively. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] mode PA mode whose curves are needed. + * @param[in] maxpower A pointer to memory allocated to hold the maxpower in + * deci-dBm used in calculation of curve segments . + * A NULL configuration will produce undefined behavior. + * @param[in] increment A pointer to memory allocated to hold the increment in + * deci-dBm used in calculation of curve segments. + * A NULL configuration will produce undefined behavior. + * @return RAIL_Status_t indicating success or an error. + * + */ +RAIL_Status_t RAIL_GetTxPowerCurveLimits(RAIL_Handle_t railHandle, + RAIL_TxPowerMode_t mode, + RAIL_TxPower_t *maxpower, + RAIL_TxPower_t *increment); + +/** + * Initialize PA TX Curves + * + */ +void sl_rail_util_pa_init(void); + +/** + * Get a pointer to the TX Power Config 2.4 GHz structure. + * + * @return a pointer to the TX Power Config stucture. + * + */ +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_2p4ghz(void); + +/** + * Get a pointer to the TX Power Config Sub-GHz structure. + * + * @return a pointer to the TX Power Config stucture. + * + */ +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_subghz(void); + +/** + * Get a pointer to the TX Power Config OFDM structure. + * + * @return a pointer to the TX Power Config stucture. + * + */ +RAIL_TxPowerConfig_t *sl_rail_util_pa_get_tx_power_config_ofdm(void); + +/** + * Provide a channel config change callback capable of configuring the PA + * correctly. + * + * @param[in] rail_handle The RAIL handle being passed into this callback. + * @param[in] entry The channel config entry being switched to by hardware. + * + */ +void sl_rail_util_pa_on_channel_config_change(RAIL_Handle_t rail_handle, + const RAIL_ChannelConfigEntry_t *entry); + +#ifdef __cplusplus +} +#endif + +#endif // PA_CONVERSIONS_EFR32_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h index 0bf9e22..ba2cb9f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curve_types_efr32.h @@ -1,236 +1,236 @@ -/***************************************************************************//** - * @file - * @brief PA power conversion curve types used by Silicon Labs PA power - * conversion functions. - * @details This file contains the curve types needed convert PA power levels - * to dBm powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef PA_CURVE_TYPES_EFR32_H -#define PA_CURVE_TYPES_EFR32_H - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @struct RAIL_TxPowerCurves - * - * @brief Structure containing data defining each segment of the - * power (deci-dBm) to powerLevel mapping curve fits. - * - * Note, these used in an equation of the form: - * - * powerLevel * 1000 = slope * power + intercept - * - * powerLevel is the 0-252/0-248/1-7 values used in the RAIL_Get/SetTxPower - * functions, and power is the actual output power of the PA, specified - * in deci-dBm. - * - * @note If the curves are generated with - * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and - * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first - * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to - * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the - * maxPower and increment in deci-dBm respectively. - */ -typedef struct RAIL_TxPowerCurveSegment { - /** The highest power level that this segment will be used to convert */ - uint16_t maxPowerLevel; - /** slope of the line */ - int16_t slope; - /** y-intercept of the line */ - int32_t intercept; -} RAIL_TxPowerCurveSegment_t; - -/** - * @struct RAIL_TxPowerCurves - * - * @brief Structure containing the min and max values for a given - * PA and voltage supply combination (in deci-dBm). - */ -typedef struct RAIL_TxPowerCurves { - /** max deci-dBm value */ - int16_t maxPower; - /** min deci-dBm value */ - int16_t minPower; - /** - * Pointer to "piecewiseSegments"-length array of - * RAIL_TxPowerCurveSegment_t of power (deci-dBm) to - * powerLevel conversion fits. - */ - const RAIL_TxPowerCurveSegment_t *powerParams; -} RAIL_TxPowerCurves_t; - -/** - * @struct RAIL_TxPowerCurvesConfig - * - * @brief Structure containing curve fit information and other metadata - * required to properly use the WEAK versions of RAIL_ConvertRawToDb - * and RAIL_ConvertDbmToRaw - */ -typedef struct RAIL_TxPowerCurvesConfig { - /** - * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments - * of curves that map power level to power in dBm for the 2.4 GHz high power - * PA. - * - * @note By the default conversion implementation, segments must be specified - * in decreasing power order. That is, the 0th entry of this array should be - * used to convert the highest power (levels). Segment at position n is valid - * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - - * 1) to maxPowerLevel of segment n, inclusive. - */ - const RAIL_TxPowerCurves_t *txPower24HpCurves; - - /** - * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments - * of curves that map power level to power in dBm for the subgig PA. - * - * @note By the default conversion implementation, segments must be specified - * in decreasing power order. That is, the 0th entry of this array should be - * used to convert the highest power (levels). Segment at position n is valid - * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - - * 1) to maxPowerLevel of segment n, inclusive. - */ - const RAIL_TxPowerCurves_t *txPowerSgCurves; - - /** - * Look up table for each of the power levels of the 2.4GHz low power - * amplifier and their equivalent deci-dB value. - */ - const int16_t *txPower24LpCurves; - /** - * The number of piecewise segments provided to the PA in each of the four - * conversion curve fits. The default is 8, but regardless of the number, it - * must be the same for all curves. - */ - uint8_t piecewiseSegments; -} RAIL_TxPowerCurvesConfig_t; - -/// PA conversion algorithms types for converting between dBm and power levels -RAIL_ENUM(RAIL_PaConversionAlgorithm_t) { - RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, /** Piecewise linear fit */ - RAIL_PA_ALGORITHM_MAPPING_TABLE, /** Mapping table between quantities */ - RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE, /** Mapping table between pa power settings and dBm values */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_PA_ALGORITHM_PIECEWISE_LINEAR ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_PIECEWISE_LINEAR) -#define RAIL_PA_ALGORITHM_MAPPING_TABLE ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_MAPPING_TABLE) -#define RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_TxPowerCurvesAlt - * - * @brief Structure containing the min and max values for a given - * PA and voltage supply combination (in deci-dBm). - */ -typedef struct RAIL_TxPowerCurveAlt { - /** max deci-dBm value */ - int16_t maxPower; - /** min deci-dBm value */ - int16_t minPower; - /** - * "piecewiseSegments"-length array of RAIL_TxPowerCurveSegment_t - * of power (deci-dBm) to powerLevel conversion fits. - */ -//Array does not have a size since it can be various sizes. -//No further fields allowed after this one. - RAIL_TxPowerCurveSegment_t powerParams[]; -} RAIL_TxPowerCurveAlt_t; - -typedef union RAIL_PowerConversion { - /** - * Pointer to a powerCurve containing line segment data for the curves - * corresponding to a specific PA. - * - * @note By the default conversion implementation, segments must be specified - * in decreasing power order. That is, the 0th entry of this array should be - * used to convert the highest power (levels). Segment at position n is valid - * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - - * 1) to maxPowerLevel of segment n, inclusive. - */ - const RAIL_TxPowerCurveAlt_t *powerCurve; - /** - * Lookup table for PA's which use the mapping table algorithm for converting - * between deci-dBm and power levels. - */ -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - const int32_t *mappingTable; -#else - const int16_t *mappingTable; -#endif -} RAIL_PowerConversion_t; - -/// PA descriptor as used in the PA conversion functions -typedef struct RAIL_PaDescriptor { - /** Algorithm used to map dBm to power levels for this PA */ - RAIL_PaConversionAlgorithm_t algorithm; - /** - * The number of piecewise segments provided to the PA in a piecewise linear - * curve fit. The default is 8. Should be set to 0 when not using the - * piecewise linear algorithm. - */ - uint8_t segments; - /** Min power level for this PA */ - RAIL_TxPowerLevel_t min; - /** Max power level for this PA */ - RAIL_TxPowerLevel_t max; -#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE - RAIL_TxPowerLevel_t step; /** step size in deci-dBm between entries in table */ - uint8_t padding; - uint16_t padding2; - RAIL_TxPower_t minPowerDbm; /** Min power in deci-dBm for this PA */ - RAIL_TxPower_t maxPowerDbm; /** Max power in deci-dBm for this PA */ -#endif - /** Union containing a pointer to algorithm-specific conversion data. */ - RAIL_PowerConversion_t conversion; -} RAIL_PaDescriptor_t; - -/** - * @typedef RAIL_TxPowerCurvesConfigAlt_t - * - * @brief More generic structure containing information about - * piecewise linear curves and mapping tables, instead of specific PA's. - */ -typedef struct RAIL_TxPowerCurvesConfigAlt { - RAIL_PaDescriptor_t curves[RAIL_NUM_PA]; - uint32_t signature; - uint16_t paVoltage; -} RAIL_TxPowerCurvesConfigAlt_t; - -#ifdef __cplusplus -} -#endif - -#endif // PA_CURVE_TYPES_EFR32_H +/***************************************************************************//** + * @file + * @brief PA power conversion curve types used by Silicon Labs PA power + * conversion functions. + * @details This file contains the curve types needed convert PA power levels + * to dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PA_CURVE_TYPES_EFR32_H +#define PA_CURVE_TYPES_EFR32_H + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @struct RAIL_TxPowerCurves + * + * @brief Structure containing data defining each segment of the + * power (deci-dBm) to powerLevel mapping curve fits. + * + * Note, these used in an equation of the form: + * + * powerLevel * 1000 = slope * power + intercept + * + * powerLevel is the 0-252/0-248/1-7 values used in the RAIL_Get/SetTxPower + * functions, and power is the actual output power of the PA, specified + * in deci-dBm. + * + * @note If the curves are generated with + * maxPower and increment other than \ref RAIL_TX_POWER_CURVE_DEFAULT_MAX and + * \ref RAIL_TX_POWER_CURVE_DEFAULT_INCREMENT respectively, then the first + * \ref RAIL_TxPowerCurveSegment_t has its maxPowerLevel equal to + * \ref RAIL_TX_POWER_LEVEL_INVALID and its slope and intercept stores the + * maxPower and increment in deci-dBm respectively. + */ +typedef struct RAIL_TxPowerCurveSegment { + /** The highest power level that this segment will be used to convert */ + uint16_t maxPowerLevel; + /** slope of the line */ + int16_t slope; + /** y-intercept of the line */ + int32_t intercept; +} RAIL_TxPowerCurveSegment_t; + +/** + * @struct RAIL_TxPowerCurves + * + * @brief Structure containing the min and max values for a given + * PA and voltage supply combination (in deci-dBm). + */ +typedef struct RAIL_TxPowerCurves { + /** max deci-dBm value */ + int16_t maxPower; + /** min deci-dBm value */ + int16_t minPower; + /** + * Pointer to "piecewiseSegments"-length array of + * RAIL_TxPowerCurveSegment_t of power (deci-dBm) to + * powerLevel conversion fits. + */ + const RAIL_TxPowerCurveSegment_t *powerParams; +} RAIL_TxPowerCurves_t; + +/** + * @struct RAIL_TxPowerCurvesConfig + * + * @brief Structure containing curve fit information and other metadata + * required to properly use the WEAK versions of RAIL_ConvertRawToDb + * and RAIL_ConvertDbmToRaw + */ +typedef struct RAIL_TxPowerCurvesConfig { + /** + * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments + * of curves that map power level to power in dBm for the 2.4 GHz high power + * PA. + * + * @note By the default conversion implementation, segments must be specified + * in decreasing power order. That is, the 0th entry of this array should be + * used to convert the highest power (levels). Segment at position n is valid + * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - + * 1) to maxPowerLevel of segment n, inclusive. + */ + const RAIL_TxPowerCurves_t *txPower24HpCurves; + + /** + * Pointer a RAIL_TxPowerCurves_t representing the piecewise linear segments + * of curves that map power level to power in dBm for the subgig PA. + * + * @note By the default conversion implementation, segments must be specified + * in decreasing power order. That is, the 0th entry of this array should be + * used to convert the highest power (levels). Segment at position n is valid + * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - + * 1) to maxPowerLevel of segment n, inclusive. + */ + const RAIL_TxPowerCurves_t *txPowerSgCurves; + + /** + * Look up table for each of the power levels of the 2.4GHz low power + * amplifier and their equivalent deci-dB value. + */ + const int16_t *txPower24LpCurves; + /** + * The number of piecewise segments provided to the PA in each of the four + * conversion curve fits. The default is 8, but regardless of the number, it + * must be the same for all curves. + */ + uint8_t piecewiseSegments; +} RAIL_TxPowerCurvesConfig_t; + +/// PA conversion algorithms types for converting between dBm and power levels +RAIL_ENUM(RAIL_PaConversionAlgorithm_t) { + RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, /** Piecewise linear fit */ + RAIL_PA_ALGORITHM_MAPPING_TABLE, /** Mapping table between quantities */ + RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE, /** Mapping table between pa power settings and dBm values */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_PA_ALGORITHM_PIECEWISE_LINEAR ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_PIECEWISE_LINEAR) +#define RAIL_PA_ALGORITHM_MAPPING_TABLE ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_MAPPING_TABLE) +#define RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE ((RAIL_PaConversionAlgorithm_t) RAIL_PA_ALGORITHM_DBM_POWERSETTING_MAPPING_TABLE) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_TxPowerCurvesAlt + * + * @brief Structure containing the min and max values for a given + * PA and voltage supply combination (in deci-dBm). + */ +typedef struct RAIL_TxPowerCurveAlt { + /** max deci-dBm value */ + int16_t maxPower; + /** min deci-dBm value */ + int16_t minPower; + /** + * "piecewiseSegments"-length array of RAIL_TxPowerCurveSegment_t + * of power (deci-dBm) to powerLevel conversion fits. + */ +//Array does not have a size since it can be various sizes. +//No further fields allowed after this one. + RAIL_TxPowerCurveSegment_t powerParams[]; +} RAIL_TxPowerCurveAlt_t; + +typedef union RAIL_PowerConversion { + /** + * Pointer to a powerCurve containing line segment data for the curves + * corresponding to a specific PA. + * + * @note By the default conversion implementation, segments must be specified + * in decreasing power order. That is, the 0th entry of this array should be + * used to convert the highest power (levels). Segment at position n is valid + * from maxPowerLevel+1 from the segment at n+1 (or 0 if n is array length - + * 1) to maxPowerLevel of segment n, inclusive. + */ + const RAIL_TxPowerCurveAlt_t *powerCurve; + /** + * Lookup table for PA's which use the mapping table algorithm for converting + * between deci-dBm and power levels. + */ +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + const int32_t *mappingTable; +#else + const int16_t *mappingTable; +#endif +} RAIL_PowerConversion_t; + +/// PA descriptor as used in the PA conversion functions +typedef struct RAIL_PaDescriptor { + /** Algorithm used to map dBm to power levels for this PA */ + RAIL_PaConversionAlgorithm_t algorithm; + /** + * The number of piecewise segments provided to the PA in a piecewise linear + * curve fit. The default is 8. Should be set to 0 when not using the + * piecewise linear algorithm. + */ + uint8_t segments; + /** Min power level for this PA */ + RAIL_TxPowerLevel_t min; + /** Max power level for this PA */ + RAIL_TxPowerLevel_t max; +#if RAIL_SUPPORTS_DBM_POWERSETTING_MAPPING_TABLE + RAIL_TxPowerLevel_t step; /** step size in deci-dBm between entries in table */ + uint8_t padding; + uint16_t padding2; + RAIL_TxPower_t minPowerDbm; /** Min power in deci-dBm for this PA */ + RAIL_TxPower_t maxPowerDbm; /** Max power in deci-dBm for this PA */ +#endif + /** Union containing a pointer to algorithm-specific conversion data. */ + RAIL_PowerConversion_t conversion; +} RAIL_PaDescriptor_t; + +/** + * @typedef RAIL_TxPowerCurvesConfigAlt_t + * + * @brief More generic structure containing information about + * piecewise linear curves and mapping tables, instead of specific PA's. + */ +typedef struct RAIL_TxPowerCurvesConfigAlt { + RAIL_PaDescriptor_t curves[RAIL_NUM_PA]; + uint32_t signature; + uint16_t paVoltage; +} RAIL_TxPowerCurvesConfigAlt_t; + +#ifdef __cplusplus +} +#endif + +#endif // PA_CURVE_TYPES_EFR32_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c index b6b013c..7e16c92 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c @@ -1,435 +1,435 @@ -/***************************************************************************//** - * @file - * @brief Default PA power conversion structures with curves calibrated by the - * RAIL team. - * @details This file contains the curves that convert PA power levels to dBm - * powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// This entire file should never be used on FCC pre-certified modules -#ifndef _SILICON_LABS_MODULE - -#include "em_device.h" -#include "pa_conversions_efr32.h" - -#if defined(_SILICON_LABS_32B_SERIES_1) - -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES -}; -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgVbat = { - RAIL_PA_CURVES_SG_VBAT_MAX_POWER, - RAIL_PA_CURVES_SG_VBAT_MIN_POWER, - RAIL_PA_CURVES_SG_VBAT_CURVES -}; -static const int16_t RAIL_curves24LpVbat[RAIL_PA_CURVES_LP_VALUES] = - RAIL_PA_CURVES_2P4_LP; - -// This macro is defined when Silicon Labs builds this into the library as WEAK -// to ensure it can be overriden by customer versions of these functions. It -// should *not* be defined in a customer build. -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24LpVbat[0] }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN, - .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataSgVbat }, - }, - }, -}; - -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { - RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_CURVES -}; -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgDcdc = { - RAIL_PA_CURVES_SG_DCDC_MAX_POWER, - RAIL_PA_CURVES_SG_DCDC_MIN_POWER, - RAIL_PA_CURVES_SG_DCDC_CURVES -}; -static const int16_t RAIL_curves24LpDcdc[RAIL_PA_CURVES_LP_VALUES] = - RAIL_PA_CURVES_2P4_LP; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24LpDcdc[0] }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN, - .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataSgDcdc }, - }, - }, -}; - -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) - -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, -}; -static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = - RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; - -#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) - -RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT; - -// This chip has the same curve for Vbat and DCDC -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - -static const int32_t RAIL_curvesOFDM[RAIL_PA_CURVES_OFDM_CURVES_NUM_VALUES] = - RAIL_PA_CURVES_OFDM_CURVES; - -static const int32_t RAIL_curvesEffOFDM[RAIL_PA_CURVES_EFF_OFDM_CURVES_NUM_VALUES] = - RAIL_PA_CURVES_EFF_OFDM_CURVES; - -static const int32_t RAIL_curvesSubgig[RAIL_PA_CURVES_SUBGIG_CURVES_NUM_VALUES] = - RAIL_PA_CURVES_SUBGIG_CURVES; - -static const int32_t RAIL_curvesEffSubgig[RAIL_PA_CURVES_EFF_SUBGIG_CURVES_NUM_VALUES] = - RAIL_PA_CURVES_EFF_SUBGIG_CURVES; - -// This chip has the same curve for Vbat and DCDC -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, -}; -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataMpVbat = { - RAIL_PA_CURVES_2P4_MP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_MP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_MP_VBAT_CURVES, -}; -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataLpVbat = { - RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_LP, -}; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_MP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_MP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat }, - }, - } -}; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_MP_MIN, - .max = RAIL_TX_POWER_LEVEL_MP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_LP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat }, - }, - } -}; -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, -}; - -#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { - RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_CURVES, -}; -#endif - -static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = - RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, -#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) - .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, -#else - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, -#endif - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; - -#else -#ifdef RAIL_INTERNAL_BUILD -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { - RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, -}; - -#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) -static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { - RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, - RAIL_PA_CURVES_2P4_HP_DCDC_CURVES, -}; -#endif - -static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = - RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; - -#ifdef RAIL_PA_CONVERSIONS_WEAK -__WEAK -#endif -const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { - .curves = { - { - .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, - .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, - .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, -#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) - .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, -#else - .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, -#endif - }, - { - .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, - .segments = 0U, - .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, - .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, - .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, - }, - } -}; -#else -#error "Unsupported platform!" -#endif -#endif - -#endif //_SILICON_LABS_MODULE +/***************************************************************************//** + * @file + * @brief Default PA power conversion structures with curves calibrated by the + * RAIL team. + * @details This file contains the curves that convert PA power levels to dBm + * powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// This entire file should never be used on FCC pre-certified modules +#ifndef _SILICON_LABS_MODULE + +#include "em_device.h" +#include "pa_conversions_efr32.h" + +#if defined(_SILICON_LABS_32B_SERIES_1) + +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES +}; +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgVbat = { + RAIL_PA_CURVES_SG_VBAT_MAX_POWER, + RAIL_PA_CURVES_SG_VBAT_MIN_POWER, + RAIL_PA_CURVES_SG_VBAT_CURVES +}; +static const int16_t RAIL_curves24LpVbat[RAIL_PA_CURVES_LP_VALUES] = + RAIL_PA_CURVES_2P4_LP; + +// This macro is defined when Silicon Labs builds this into the library as WEAK +// to ensure it can be overriden by customer versions of these functions. It +// should *not* be defined in a customer build. +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24LpVbat[0] }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN, + .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataSgVbat }, + }, + }, +}; + +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { + RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_CURVES +}; +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataSgDcdc = { + RAIL_PA_CURVES_SG_DCDC_MAX_POWER, + RAIL_PA_CURVES_SG_DCDC_MIN_POWER, + RAIL_PA_CURVES_SG_DCDC_CURVES +}; +static const int16_t RAIL_curves24LpDcdc[RAIL_PA_CURVES_LP_VALUES] = + RAIL_PA_CURVES_2P4_LP; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24LpDcdc[0] }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_2P4_HP_SG_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_SUBGIG_MIN, + .max = RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataSgDcdc }, + }, + }, +}; + +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 2) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 7)) + +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, +}; +static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = + RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; + +#elif ((_SILICON_LABS_32B_SERIES_2_CONFIG == 3) || (_SILICON_LABS_32B_SERIES_2_CONFIG == 8)) + +RAIL_DECLARE_TX_POWER_VBAT_CURVES_ALT; + +// This chip has the same curve for Vbat and DCDC +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + +static const int32_t RAIL_curvesOFDM[RAIL_PA_CURVES_OFDM_CURVES_NUM_VALUES] = + RAIL_PA_CURVES_OFDM_CURVES; + +static const int32_t RAIL_curvesEffOFDM[RAIL_PA_CURVES_EFF_OFDM_CURVES_NUM_VALUES] = + RAIL_PA_CURVES_EFF_OFDM_CURVES; + +static const int32_t RAIL_curvesSubgig[RAIL_PA_CURVES_SUBGIG_CURVES_NUM_VALUES] = + RAIL_PA_CURVES_SUBGIG_CURVES; + +static const int32_t RAIL_curvesEffSubgig[RAIL_PA_CURVES_EFF_SUBGIG_CURVES_NUM_VALUES] = + RAIL_PA_CURVES_EFF_SUBGIG_CURVES; + +// This chip has the same curve for Vbat and DCDC +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = RAIL_DECLARE_TX_POWER_CURVES_CONFIG_ALT; + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, +}; +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataMpVbat = { + RAIL_PA_CURVES_2P4_MP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_MP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_MP_VBAT_CURVES, +}; +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataLpVbat = { + RAIL_PA_CURVES_2P4_LP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_LP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_LP, +}; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_MP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_MP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat }, + }, + } +}; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_MP_MIN, + .max = RAIL_TX_POWER_LEVEL_MP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataMpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_LP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataLpVbat }, + }, + } +}; +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, +}; + +#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { + RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_CURVES, +}; +#endif + +static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = + RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, +#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) + .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, +#else + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, +#endif + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; + +#else +#ifdef RAIL_INTERNAL_BUILD +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpVbat = { + RAIL_PA_CURVES_2P4_HP_VBAT_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_VBAT_CURVES, +}; + +#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) +static const RAIL_TxPowerCurveAlt_t RAIL_piecewiseDataHpDcdc = { + RAIL_PA_CURVES_2P4_HP_DCDC_MAX_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_MIN_POWER, + RAIL_PA_CURVES_2P4_HP_DCDC_CURVES, +}; +#endif + +static const int16_t RAIL_curves24Lp[RAIL_PA_CURVES_LP_VALUES] = + RAIL_PA_CURVES_2P4_LP_VBAT_CURVES; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesVbat = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; + +#ifdef RAIL_PA_CONVERSIONS_WEAK +__WEAK +#endif +const RAIL_TxPowerCurvesConfigAlt_t RAIL_TxPowerCurvesDcdc = { + .curves = { + { + .algorithm = RAIL_PA_ALGORITHM_PIECEWISE_LINEAR, + .segments = RAIL_PA_CURVES_PIECEWISE_SEGMENTS, + .min = RAIL_TX_POWER_LEVEL_2P4_HP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_HP_MAX, +#if defined(RAIL_DECLARE_TX_POWER_DCDC_CURVES_ALT) + .conversion = { .powerCurve = &RAIL_piecewiseDataHpDcdc }, +#else + .conversion = { .powerCurve = &RAIL_piecewiseDataHpVbat }, +#endif + }, + { + .algorithm = RAIL_PA_ALGORITHM_MAPPING_TABLE, + .segments = 0U, + .min = RAIL_TX_POWER_LEVEL_2P4_LP_MIN, + .max = RAIL_TX_POWER_LEVEL_2P4_LP_MAX, + .conversion = { .mappingTable = &RAIL_curves24Lp[0] }, + }, + } +}; +#else +#error "Unsupported platform!" +#endif +#endif + +#endif //_SILICON_LABS_MODULE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h index 45db912..186f4a0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.h @@ -1,114 +1,114 @@ -/***************************************************************************//** - * @file - * @brief PA power conversion curves used by Silicon Labs PA power conversion - * functions. - * @details This file contains the curves needed convert PA power levels to - * dBm powers. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef PA_CURVES_EFR32_H -#define PA_CURVES_EFR32_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "em_device.h" - -#ifdef _SILICON_LABS_32B_SERIES_1 -#include "efr32xg1x/sl_rail_util_pa_curves.h" -#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_1) -#include "efr32xg21/sl_rail_util_pa_curves.h" -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) -#include "efr32xg22/sl_rail_util_pa_curves.h" -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) -#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT) - #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20) - #include "efr32xg23/sl_rail_util_pa_curves_20dbm.h" - #elif (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 10) - #include "efr32xg23/sl_rail_util_pa_curves_10dbm_434M.h" - #else - #include "efr32xg23/sl_rail_util_pa_curves_14dbm.h" - #endif -#else -#error "No valid PA available for selected chip." -#endif -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) -#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT) - #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20) - #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868) - #include "efr32xg28/sl_rail_util_pa_curves_20dbm_868M.h" - #else - #include "efr32xg28/sl_rail_util_pa_curves_20dbm_915M.h" - #endif - #else - #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868) - #include "efr32xg28/sl_rail_util_pa_curves_14dbm_868M.h" - #else - #include "efr32xg28/sl_rail_util_pa_curves_14dbm_915M.h" - #endif - #endif -#else -#error "No valid PA available for selected chip." -#endif -#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_4) - #if defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ - && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) - #include "efr32xg24/sl_rail_util_pa_curves_20dbm.h" - #else - #include "efr32xg24/sl_rail_util_pa_curves_10dbm.h" - #endif -#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_5) -#include "efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_eff.h" -#include "efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table.h" -#include "efr32xg25/sl_rail_util_pa_curves.h" -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) -// EFR32XG27 boards come in two different packaging -- CSP and QFN -// These packages have different matching circuits which leads -// to different PA curves. -// CSP packages have _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM -// = 4 whereas for QFN package it is 6 or 8dBm, so this parameter -// is used to differentiate it. - #if (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM < 6) - #include "efr32xg27/sl_rail_util_pa_curves_CSP.h" - #else - #include "efr32xg27/sl_rail_util_pa_curves_QFN.h" - #endif -#else -#ifdef RAIL_INTERNAL_BUILD -#include "pa_curves_efr32_internal.h" -#else -#error "Unsupported platform!" -#endif -#endif - -#ifdef __cplusplus -} -#endif - -#endif // PA_CURVES_EFR32_H +/***************************************************************************//** + * @file + * @brief PA power conversion curves used by Silicon Labs PA power conversion + * functions. + * @details This file contains the curves needed convert PA power levels to + * dBm powers. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef PA_CURVES_EFR32_H +#define PA_CURVES_EFR32_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "em_device.h" + +#ifdef _SILICON_LABS_32B_SERIES_1 +#include "efr32xg1x/sl_rail_util_pa_curves.h" +#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_1) +#include "efr32xg21/sl_rail_util_pa_curves.h" +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) +#include "efr32xg22/sl_rail_util_pa_curves.h" +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 3) +#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT) + #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20) + #include "efr32xg23/sl_rail_util_pa_curves_20dbm.h" + #elif (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 10) + #include "efr32xg23/sl_rail_util_pa_curves_10dbm_434M.h" + #else + #include "efr32xg23/sl_rail_util_pa_curves_14dbm.h" + #endif +#else +#error "No valid PA available for selected chip." +#endif +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 8) +#if defined(_SILICON_LABS_EFR32_SUBGHZ_HP_PA_PRESENT) + #if (_SILICON_LABS_EFR32_SUBGHZ_HP_PA_MAX_OUTPUT_DBM == 20) + #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868) + #include "efr32xg28/sl_rail_util_pa_curves_20dbm_868M.h" + #else + #include "efr32xg28/sl_rail_util_pa_curves_20dbm_915M.h" + #endif + #else + #if defined(HARDWARE_BOARD_SUPPORTS_RF_BAND_868) + #include "efr32xg28/sl_rail_util_pa_curves_14dbm_868M.h" + #else + #include "efr32xg28/sl_rail_util_pa_curves_14dbm_915M.h" + #endif + #endif +#else +#error "No valid PA available for selected chip." +#endif +#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_4) + #if defined(_SILICON_LABS_EFR32_2G4HZ_HP_PA_PRESENT) \ + && (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM > 10) + #include "efr32xg24/sl_rail_util_pa_curves_20dbm.h" + #else + #include "efr32xg24/sl_rail_util_pa_curves_10dbm.h" + #endif +#elif defined (_SILICON_LABS_32B_SERIES_2_CONFIG_5) +#include "efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table_eff.h" +#include "efr32xg25/sl_rail_util_pa_dbm_powersetting_mapping_table.h" +#include "efr32xg25/sl_rail_util_pa_curves.h" +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 7) +// EFR32XG27 boards come in two different packaging -- CSP and QFN +// These packages have different matching circuits which leads +// to different PA curves. +// CSP packages have _SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM +// = 4 whereas for QFN package it is 6 or 8dBm, so this parameter +// is used to differentiate it. + #if (_SILICON_LABS_EFR32_2G4HZ_HP_PA_MAX_OUTPUT_DBM < 6) + #include "efr32xg27/sl_rail_util_pa_curves_CSP.h" + #else + #include "efr32xg27/sl_rail_util_pa_curves_QFN.h" + #endif +#else +#ifdef RAIL_INTERNAL_BUILD +#include "pa_curves_efr32_internal.h" +#else +#error "Unsupported platform!" +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif // PA_CURVES_EFR32_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c index e07b61b..53ff132 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c @@ -1,89 +1,89 @@ -/***************************************************************************//** - * @file - * @brief - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "rail.h" -#include "rail_ble.h" -#include "sl_rail_util_aox.h" -#include "sl_rail_util_aox_config.h" -#include "em_gpio.h" - -#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT -static RAIL_BLE_AoxAntennaPortPins_t antennaPortPin[] = { -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT -#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT - { - .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT, - .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PIN - }, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT -}; -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT - -static RAIL_BLE_AoxAntennaConfig_t antennaConfig = { -#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT - // If no AoX antenna pins are selected CTE can be received/transmitted on the default antenna - .antPortPin = antennaPortPin, -#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT - .antCount = SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT -}; - -void sl_rail_util_aox_init(void) -{ - (void) RAIL_BLE_ConfigAoxAntenna(RAIL_EFR32_HANDLE, &antennaConfig); -} +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "rail.h" +#include "rail_ble.h" +#include "sl_rail_util_aox.h" +#include "sl_rail_util_aox_config.h" +#include "em_gpio.h" + +#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT +static RAIL_BLE_AoxAntennaPortPins_t antennaPortPin[] = { +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN0_PORT +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN1_PORT +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN2_PORT +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN3_PORT +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN4_PORT +#ifdef SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT + { + .antPort = (uint8_t)SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT, + .antPin = SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PIN + }, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN5_PORT +}; +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT + +static RAIL_BLE_AoxAntennaConfig_t antennaConfig = { +#if SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT + // If no AoX antenna pins are selected CTE can be received/transmitted on the default antenna + .antPortPin = antennaPortPin, +#endif //SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT + .antCount = SL_RAIL_UTIL_AOX_ANTENNA_PIN_COUNT +}; + +void sl_rail_util_aox_init(void) +{ + (void) RAIL_BLE_ConfigAoxAntenna(RAIL_EFR32_HANDLE, &antennaConfig); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.h index 7d41f73..f0170e0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.h @@ -1,51 +1,51 @@ -/***************************************************************************//** - * @file - * @brief - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_AOX_H -#define SL_RAIL_UTIL_AOX_H - -#include "rail.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize the AoX(angle of arrival/departure) Utility. - * - * @note: This function should be called during application initialization. - */ -void sl_rail_util_aox_init(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_RAIL_UTIL_AOX_H +/***************************************************************************//** + * @file + * @brief + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_AOX_H +#define SL_RAIL_UTIL_AOX_H + +#include "rail.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize the AoX(angle of arrival/departure) Utility. + * + * @note: This function should be called during application initialization. + */ +void sl_rail_util_aox_init(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_RAIL_UTIL_AOX_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c index 628a8ca..f8bcbe7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c @@ -1,39 +1,39 @@ -/***************************************************************************//** - * @file - * @brief Initialize RAIL power manager - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "rail.h" -#include "sl_rail_util_power_manager_init.h" -#include "sl_rail_util_power_manager_init_config.h" - -void sl_rail_util_power_manager_init(void) -{ -#if SL_RAIL_UTIL_RAIL_POWER_MANAGER_INIT == 1 - RAIL_InitPowerManager(); -#endif -} +/***************************************************************************//** + * @file + * @brief Initialize RAIL power manager + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "rail.h" +#include "sl_rail_util_power_manager_init.h" +#include "sl_rail_util_power_manager_init_config.h" + +void sl_rail_util_power_manager_init(void) +{ +#if SL_RAIL_UTIL_RAIL_POWER_MANAGER_INIT == 1 + RAIL_InitPowerManager(); +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.h index ee5e279..06ca07b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.h @@ -1,50 +1,50 @@ -/***************************************************************************//** - * @file - * @brief Initialize RAIL power manager - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_RAIL_UTIL_POWER_MANAGER_INIT_H -#define SL_RAIL_UTIL_POWER_MANAGER_INIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize RAIL power manager - * - * @note: This function should be called during application initialization, - * after sl_power_manager_init function has been called. - */ -void sl_rail_util_power_manager_init(void); - -#ifdef __cplusplus -} -#endif - -#endif // SL_RAIL_UTIL_POWER_MANAGER_INIT_H +/***************************************************************************//** + * @file + * @brief Initialize RAIL power manager + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_RAIL_UTIL_POWER_MANAGER_INIT_H +#define SL_RAIL_UTIL_POWER_MANAGER_INIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize RAIL power manager + * + * @note: This function should be called during application initialization, + * after sl_power_manager_init function has been called. + */ +void sl_rail_util_power_manager_init(void); + +#ifdef __cplusplus +} +#endif + +#endif // SL_RAIL_UTIL_POWER_MANAGER_INIT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ble/rail_ble.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ble/rail_ble.h index 19b4c5a..0004f34 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ble/rail_ble.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ble/rail_ble.h @@ -1,1681 +1,1681 @@ -/***************************************************************************//** - * @file - * @brief The BLE specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_BLE_H__ -#define __RAIL_BLE_H__ - -// Get the standard include types -#include -#include - -// Get the RAIL specific structures and types -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @addtogroup BLE -/// @ingroup Protocol_Specific -/// Accelerator routines for Bluetooth Low Energy (BLE). -/// -/// The APIs in this module configure the radio for BLE -/// operation and provide additional helper routines necessary for -/// normal BLE send/receive that aren't available directly in RAIL. -/// RAIL APIs should be used to set up the application. However, -/// RAIL_ConfigChannels() and RAIL_ConfigRadio() should not be called to set up -/// the PHY. Instead, RAIL_BLE_Config* APIs should be used to set up the -/// 1 Mbps, 2 Mbps, or Coded PHY configurations needed by the application. These -/// APIs will configure the hardware and also configure the set of valid BLE -/// channels. -/// -/// To implement a standard BLE link layer, you will also need to handle tight -/// turnaround times and send packets at specific instants. This can all be -/// managed through general RAIL functions, such as RAIL_ScheduleTx(), -/// RAIL_ScheduleRx(), and RAIL_SetStateTiming(). See RAIL APIs for more -/// useful functions. -/// -/// A simple example to set up the application to be in BLE mode is shown -/// below. Note that this will put the radio on the first advertising channel -/// with the advertising Access Address. In any full-featured BLE application you -/// will need to use the RAIL_BLE_ConfigChannelRadioParams() function to change -/// the sync word and other parameters as needed based on your connection. -/// -/// @code{.c} -/// -/// // RAIL Handle set at initialization time. -/// static RAIL_Handle_t gRailHandle = NULL; -/// -/// static void radioEventHandler(RAIL_Handle_t railHandle, -/// RAIL_Events_t events) -/// { -/// // ... handle RAIL events, e.g., receive and transmit completion -/// } -/// -/// #if MULTIPROTOCOL -/// // Allocate memory for RAIL to hold BLE-specific state information -/// static RAIL_BLE_State_t bleState; // Must never be const -/// static RAILSched_Config_t schedCfg; // Must never be const -/// static RAIL_Config_t railCfg = { // Must never be const -/// .eventsCallback = &radioEventHandler, -/// .protocol = &bleState, // For BLE, RAIL needs additional state memory -/// .scheduler = &schedCfg, // For MultiProtocol, additional scheduler memory -/// }; -/// #else -/// static RAIL_Config_t railCfg = { // Must never be const -/// .eventsCallback = &radioEventHandler, -/// .protocol = NULL, -/// .scheduler = NULL, -/// }; -/// #endif -/// -/// // Set the radio to receive on the first BLE advertising channel. -/// int bleAdvertiseEnable(void) -/// { -/// // Initializes the RAIL library and any internal state it requires. -/// gRailHandle = RAIL_Init(&railCfg, NULL); -/// -/// // Calls the BLE initialization function to load the right radio configuration. -/// RAIL_BLE_Init(gRailHandle); -/// -/// // Always choose the Viterbi PHY configuration if available on your chip -/// // for performance reasons. -/// RAIL_BLE_ConfigPhy1MbpsViterbi(gRailHandle); -/// -/// // Configures us for the first advertising channel (Physical: 0, Logical: 37). -/// // The CRC init value and Access Address come from the BLE specification. -/// RAIL_BLE_ConfigChannelRadioParams(gRailHandle, -/// 0x555555, -/// 0x8E89BED6, -/// 37, -/// false); -/// -/// // Starts receiving on physical channel 0 (logical channel 37). -/// RAIL_StartRx(gRailHandle, 0, NULL); -/// } -/// @endcode -/// -/// @{ - -/** - * @enum RAIL_BLE_Coding_t - * @brief The variant of the BLE Coded PHY. - */ -RAIL_ENUM(RAIL_BLE_Coding_t) { - /** Enables the 125 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coding_125kbps = 0, - /** @deprecated Will be removed in a future version of RAIL */ - RAIL_BLE_Coding_125kbps_DSA = 1, - /** Enables the 500 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coding_500kbps = 2, - /** @deprecated Will be removed in a future version of RAIL */ - RAIL_BLE_Coding_500kbps_DSA = 3, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_BLE_Coding_125kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps) -#define RAIL_BLE_Coding_125kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps_DSA) -#define RAIL_BLE_Coding_500kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps) -#define RAIL_BLE_Coding_500kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps_DSA) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_BLE_Phy_t - * @brief The variant of the BLE PHY. - */ -RAIL_ENUM(RAIL_BLE_Phy_t) { - /** Use the standard BLE 1Mbps PHY */ - RAIL_BLE_1Mbps, - /** Use the high data rate BLE 2Mbps PHY */ - RAIL_BLE_2Mbps, - /** Enables the 125 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coded125kbps, - /** Enables the 500 kbps variant of the BLE Coded PHY */ - RAIL_BLE_Coded500kbps, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_BLE_1Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_1Mbps) -#define RAIL_BLE_2Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_2Mbps) -#define RAIL_BLE_Coded125kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded125kbps) -#define RAIL_BLE_Coded500kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded500kbps) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/// @addtogroup BLE_PHY BLE Radio Configurations -/// Radio configurations for the RAIL BLE Accelerator -/// -/// These radio configurations are used to configure BLE when a function such -/// as \ref RAIL_BLE_ConfigPhy1MbpsViterbi() is called. Each radio -/// configuration listed below is compiled into the RAIL library as a weak -/// symbol that will take into account per-die defaults. If the board -/// configuration in use has different settings than the default, such as a -/// different radio subsystem clock frequency, these radio configurations can -/// be overriden to account for those settings. -/// @{ - -/** - * Default PHY to use for BLE 1M non-Viterbi. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps; - -/** - * Default PHY to use for BLE 2M non-Viterbi. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps; - -/** - * Default PHY to use for BLE 1M Viterbi. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi; - -/** - * Default PHY to use for BLE 2M Viterbi. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Default PHY to use for BLE 1M Viterbi HADM. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_HADM is 0. On EFR32XG24, this will also - * be NULL for non 40MHz HFXO frequencies. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiHadm; - -/** - * Default PHY to use for BLE 2M Viterbi HADM. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_HADM is 0. On EFR32XG24, this will also - * be NULL for non 40MHz HFXO frequencies. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiHadm; -#endif - -/** - * PHY to use for BLE 2M with AoX functionality. Will be NULL if either - * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI or \ref RAIL_BLE_SUPPORTS_AOX is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox; - -/** - * Default PHY to use for BLE Coded 125kbps. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both - * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps; - -/** - * Default PHY to use for BLE Coded 500kbps. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both - * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps; - -/** - * Default PHY to use for BLE Simulscan. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY is 0. This PHY can receive on 1Mbps - * as well as 125kbps and 500kbps BLE Coded, but will only transmit at 1Mbps. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan; - -/** - * Default 1Mbps Quuppa PHY. Will be NULL if - * \ref RAIL_BLE_SUPPORTS_QUUPPA is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhyQuuppa; - -/// @} // End of group BLE_PHY - -// Defines for subPhyID field in RAIL_RxPacketDetails_t -/** subPhyId indicating a 500kbps packet */ -#define RAIL_BLE_RX_SUBPHY_ID_500K (0U) -/** subPhyId indicating a 125kbps packet */ -#define RAIL_BLE_RX_SUBPHY_ID_125K (1U) -/** subPhyId value indicating a 1Mbps packet */ -#define RAIL_BLE_RX_SUBPHY_ID_1M (2U) -/** Invalid subPhyId value */ -#define RAIL_BLE_RX_SUBPHY_ID_INVALID (3U) -/** subPhyId indicating the total count */ -#define RAIL_BLE_RX_SUBPHY_COUNT (4U) - -/** - * @enum RAIL_BLE_SignalIdentifierMode_t - * @brief Available Signal Identifier modes. - */ -RAIL_ENUM(RAIL_BLE_SignalIdentifierMode_t) { - /* Disable signal detection mode. */ - RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, - /* BLE 1Mbps (GFSK) detection mode. */ - RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS, - /* BLE 2Mbps (GFSK) detection mode. */ - RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE) -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS) -#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS) -#endif - -/** - * @struct RAIL_BLE_State_t - * @brief A state structure for BLE. - * - * This structure must be allocated in application global read-write memory - * that persists for the duration of BLE usage. It cannot be allocated - * in read-only memory or on the call stack. - */ -typedef struct RAIL_BLE_State { - uint32_t crcInit; /**< The value used to initialize the CRC algorithm. */ - uint32_t accessAddress; /**< The access address used for the connection. */ - uint16_t channel; /**< The logical channel used. */ - bool disableWhitening; /**< Indicates whether the whitening engine should be off. */ - uint16_t whiteInit; /**< The value used to initialize the whitening algorithm */ -} RAIL_BLE_State_t; - -/** - * Configure RAIL to run in BLE mode. - * - * @param[in] railHandle A handle for RAIL instance. - * This function changes your radio, channel configuration, and other - * parameters to match what is needed for BLE. To switch back to a - * default RAIL mode, call RAIL_BLE_Deinit() first. This function - * will configure the protocol output on PTI to \ref RAIL_PTI_PROTOCOL_BLE. - * - * @note BLE may not be enabled while Auto-ACKing is enabled. - */ -void RAIL_BLE_Init(RAIL_Handle_t railHandle); - -/** - * Take RAIL out of BLE mode. - * - * @param[in] railHandle A handle for RAIL instance. - * This function will undo some of the configuration that happens when you call - * RAIL_BLE_Init(). After this you can safely run your normal radio - * initialization code to use a non-BLE configuration. This function does \b - * not change back your radio or channel configurations so you must do this by - * manually reinitializing. This also resets the protocol output on PTI to \ref - * RAIL_PTI_PROTOCOL_CUSTOM. - */ -void RAIL_BLE_Deinit(RAIL_Handle_t railHandle); - -/** - * Determine whether BLE mode is enabled or not. - * - * @param[in] railHandle A handle for RAIL instance. - * @return True if BLE mode is enabled and false otherwise. - * This function returns the current status of RAIL's BLE mode. It is enabled by - * a call to RAIL_BLE_Init() and disabled by a call to RAIL_BLE_Deinit(). - */ -bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle); - -/** - * Switch to the 1 Mbps Quuppa PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return Status code indicating success of the function call. - * - * You can use this function to switch to the Quuppa PHY. - * - * @note Not all chips support the 1Mbps Quuppa PHY. This API should return RAIL_STATUS_INVALID_CALL if - * unsupported by the hardware we're building for. - */ -RAIL_Status_t RAIL_BLE_ConfigPhyQuuppa(RAIL_Handle_t railHandle); - -/** - * Switch to the Viterbi 1 Mbps BLE PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to the default BLE 1 Mbps PHY if you - * have switched to the 2 Mbps or another configuration. You may only call this - * function after initializing BLE and while the radio is idle. - * - * @note The EFR32XG1 family does not support BLE Viterbi PHYs. However, calls - * to this function from that family will be silently redirected to the legacy - * \ref RAIL_BLE_ConfigPhy1Mbps(). - */ -RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsViterbi(RAIL_Handle_t railHandle); - -/** - * Switch to the legacy non-Viterbi 1 Mbps BLE PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to the legacy BLE 1 Mbps PHY if you - * have switched to the 2 Mbps or another configuration. You may only call this - * function after initializing BLE and while the radio is idle. - * - * @note The EFR32XG2x family does not support BLE non-Viterbi PHYs. - */ -RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle); - -/** - * Switch to the Viterbi 2 Mbps BLE PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to the BLE 2 Mbps PHY from the - * default 1 Mbps option. You may only call this function after initializing BLE - * and while the radio is idle. - * - * @note The EFR32XG1 family does not support BLE Viterbi PHYs. - */ -RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsViterbi(RAIL_Handle_t railHandle); - -/** - * Switch to the legacy non-Viterbi 2 Mbps BLE PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to legacy BLE 2Mbps PHY from the - * default 1 Mbps option. You may only call this function after initializing BLE - * and while the radio is idle. - * - * @note The EFR32XG1 and EFR32XG2x families do not support BLE non-Viterbi - * 2 Mbps PHY. - */ -RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle); - -/** - * Switch to the BLE Coded PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @param[in] bleCoding The RAIL_BLE_Coding_t to use - * @return A status code indicating success of the function call. - * - * Use this function to switch back to BLE Coded PHY from the default - * 1 Mbps option. You may only call this function after initializing BLE and - * while the radio is idle. When using a BLE Coded PHY, the \ref - * RAIL_RxPacketDetails_t::subPhyId marks the coding of the received packet. - * A subPhyId of 0 marks a 500 kbps packet, and a subPhyId of 1 marks a 125 - * kbps packet. - * - * @note The EFR32XG1, EFR32XG12, and EFR32XG14 families do not support BLE - * Coded PHYs. - */ -RAIL_Status_t RAIL_BLE_ConfigPhyCoded(RAIL_Handle_t railHandle, - RAIL_BLE_Coding_t bleCoding); - -/** - * Switch to the Simulscan PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch to the BLE Simulscan PHY. You may only - * call this function after initializing BLE and while the radio is idle. - * When using Simulscan PHY, the \ref RAIL_RxPacketDetails_t::subPhyId - * marks the coding of the received packet. A subPhyId of 0 marks a - * 500 kbps packet, a subPhyId of 1 marks a 125 kbps packet, and a - * subPhyId of 2 marks a 1 Mbps packet. - * - * @note: The Simulscan PHY is supported only on some 2.4 GHz Series-2 parts. - * The preprocessor symbol \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY and the - * runtime function \ref RAIL_BLE_SupportsSimulscanPhy() may be used to - * test for support of the Simulscan PHY. - */ -RAIL_Status_t RAIL_BLE_ConfigPhySimulscan(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Switch to the 1 Mbps BLE PHY for HADM. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to the BLE 1 Mbps HADM PHY from - * another configuration. You may only call this - * function after initializing BLE and while the radio is idle. - * - * @note This PHY is only supported when \ref RAIL_BLE_SUPPORTS_HADM is not 0. - */ -RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsHadm(RAIL_Handle_t railHandle); - -/** - * Switch to the 2 Mbps BLE PHY for HADM. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch back to the BLE 2 Mbps HADM PHY from - * another configuration. You may only call this - * function after initializing BLE and while the radio is idle. - * - * @note This PHY is only supported when \ref RAIL_BLE_SUPPORTS_HADM is not 0. - */ -RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsHadm(RAIL_Handle_t railHandle); -#endif - -/** - * Change BLE radio parameters. - * - * @param[in] railHandle A handle for RAIL instance. - * @param[in] crcInit The value to use for CRC initialization. - * @param[in] accessAddress The access address to use for the connection. The - * bits of this parameter are transmitted or received LSB first. - * @param[in] channel The logical channel that you're changing to, which - * initializes the whitener if used. - * @param[in] disableWhitening This can turn off the whitening engine and is useful - * for sending BLE test mode packets that don't have this turned on. - * @return A status code indicating success of the function call. - * - * This function can be used to switch radio parameters on every connection - * and/or channel change. It is BLE-aware and will set the access address, - * preamble, CRC initialization value, and whitening configuration without - * requiring you to load a new radio configuration. This function should not be - * called while the radio is active. - */ -RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, - uint32_t crcInit, - uint32_t accessAddress, - uint16_t channel, - bool disableWhitening); - -/** - * Change the current BLE PHY and go into receive. - * - * @param[in] railHandle A handle for RAIL instance. - * @param[in] phy Indicates which PHY to receive on - * @param[in] railChannel Which channel of the given PHY to receive on - * @param[in] startRxTime When to enter RX - * @param[in] crcInit The value to use for CRC initialization. - * @param[in] accessAddress The access address to use for the connection. The - * bits of this parameter are transmitted or received LSB first. - * @param[in] logicalChannel The logical channel that you're changing to, which - * initializes the whitener if used. - * @param[in] disableWhitening This can turn off the whitening engine and is useful - * for sending BLE test mode packets that don't have this turned on. - * @return A status code indicating success of the function call. - * - * This function is used to implement auxiliary packet reception, as defined in - * the BLE specification. The radio will be put into IDLE, the PHY and channel - * will be changed, and then receive will be entered at the start time given. - * The new receive will have a timeout of 30 us, which means that this function - * should only be called if the offset unit is 30 us. - * - * This function is extremely time-sensitive, and may only be called within the - * interrupt context of a \ref RAIL_EVENT_RX_PACKET_RECEIVED event. - */ -RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, - RAIL_BLE_Phy_t phy, - uint16_t railChannel, - uint32_t startRxTime, - uint32_t crcInit, - uint32_t accessAddress, - uint16_t logicalChannel, - bool disableWhitening); - -/** - * Configure and enable signal identifier for BLE signal detection. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] signalIdentifierMode Mode of signal identifier operation. - * - * This features allows detection of BLE signal on air based on the mode. - * This function must be called once before \ref RAIL_BLE_EnableSignalDetection - * to configure and enable signal identifier. - * - * To enable event for signal detection \ref RAIL_ConfigEvents() must be called - * for enabling \ref RAIL_EVENT_SIGNAL_DETECTED. - * - * This function is only supported by chips where - * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and - * \ref RAIL_BLE_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_BLE_ConfigSignalIdentifier(RAIL_Handle_t railHandle, - RAIL_BLE_SignalIdentifierMode_t signalIdentifierMode); - -/** - * Enable or disable signal identifier interrupt for BLE signal detection. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Signal detection is enabled if true, disabled if false. - * - * \ref RAIL_BLE_ConfigSignalIdentifier must be called once before calling this - * function to configure and enable signal identifier. - * Once a signal is detected signal detection will be turned off and this - * function should be called to re-enable the signal detection without needing - * to call \ref RAIL_BLE_ConfigSignalIdentifier if the signal identifier - * is already configured and enabled. - * - * This function is only supported by chips where - * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and - * \ref RAIL_BLE_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_BLE_EnableSignalDetection(RAIL_Handle_t railHandle, - bool enable); - -/** - * @brief Backward compatible name for the \ref - * RAIL_BLE_EnableSignalDetection API. - */ -#define RAIL_BLE_EnableSignalIdentifier RAIL_BLE_EnableSignalDetection - -/****************************************************************************** - * Angle of Arrival/Departure (AoX) - *****************************************************************************/ -/** - * @addtogroup AoX Angle of Arrival/Departure - * @{ - * @brief These APIs are to a stack implementing BLE's angle of arrival and - * angle of departure functionality. - * - * They are designed for use by the Silicon Labs BLE stack only at this time and - * may cause problems if accessed directly. - */ - -/** - * - * The maximum number of GPIO pins used for AoX Antenna switching. - * - * If the user configures more pins using - * \ref RAIL_BLE_ConfigAoxAntenna than allowed - * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then - * \ref RAIL_STATUS_INVALID_PARAMETER status will be returned. - * - * \ref RAIL_STATUS_INVALID_CALL is returned if : - * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is set to 0 or - * The user configures no pins. - * - * The maximum value \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT can take depends on - * number of Antenna route pins , a chip provides. - * For EFR32XG22, the maximum value of \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is 6. - * If the user configures fewer pins than \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, - * then only number of pins asked by user will be configured with - * \ref RAIL_STATUS_NO_ERROR. - * - */ -#define RAIL_BLE_AOX_ANTENNA_PIN_COUNT (6U) - -/** - * @enum RAIL_BLE_AoxOptions_t - * @brief Angle of Arrival/Departure options bit fields - */ -RAIL_ENUM_GENERIC(RAIL_BLE_AoxOptions_t, uint16_t) { - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE bit */ - RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT = 0, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONNLESS bit */ - RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT = 1, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONN bit */ - RAIL_BLE_AOX_OPTIONS_CONN_SHIFT = 2, - /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK bit */ - RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT = 3, -}; - -/** - * @deprecated Obsolete AOX option - */ -#define RAIL_BLE_AOX_OPTIONS_DO_SWITCH (0U) -/** - * @deprecated Obsolete AOX option - */ -#define RAIL_BLE_AOX_OPTIONS_TX_ENABLED (0U) -/** - * @deprecated Obsolete AOX option - */ -#define RAIL_BLE_AOX_OPTIONS_RX_ENABLED (0U) -/** - * @deprecated Please use \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT instead. - */ -#define RAIL_BLE_AOX_OPTIONS_LOCK_CTE_BUFFER_SHIFT RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT - -/** - * Disable the AoX feature. - */ -#define RAIL_BLE_AOX_OPTIONS_DISABLED (0U) -/** - * Sets one of the two AoX sampling/switching modes: 1 us or 2 us window. - */ -#define RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE (1U << RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT) -/** - * Enables connectionless AoX Rx packets. - */ -#define RAIL_BLE_AOX_OPTIONS_CONNLESS (1U << RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT) -/** - * Enables connection based AoX Rx packets. - */ -#define RAIL_BLE_AOX_OPTIONS_CONN (1U << RAIL_BLE_AOX_OPTIONS_CONN_SHIFT) -/** - * Disables CTE buffer lock. - */ -#define RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK (1U << RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT) -/** - * Enables connection based or connectionless AoX Rx packets. - */ -#define RAIL_BLE_AOX_OPTIONS_ENABLED (RAIL_BLE_AOX_OPTIONS_CONN | RAIL_BLE_AOX_OPTIONS_CONNLESS) - -/** - * @struct RAIL_BLE_AoxConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigAox function. - */ -typedef struct RAIL_BLE_AoxConfig { - /** - * See RAIL_BLE_AOX_OPTIONS_* for bitfield defines for different AoX features. - */ - RAIL_BLE_AoxOptions_t aoxOptions; - /** - * Size of the raw AoX CTE (continuous tone extension) data capture buffer in - * bytes. Note this value should be a multiple of 4 as each IQ sample - * requires 4 bytes. - */ - uint16_t cteBuffSize; - /** - * Address to where the received CTE is written. Buffer must be 32-bit - * aligned. - */ - uint32_t * cteBuffAddr; - /** - * Address to first element of antenna pattern array. Array must be in RAM. - * Each element of the array contains an antenna number. The switching pattern - * is defined by the order of antennas in this array. - */ - uint8_t * antArrayAddr; - /** - * Size of the antenna pattern array. - */ - uint8_t antArraySize; -} RAIL_BLE_AoxConfig_t; - -/** - * @struct RAIL_BLE_AoxAntennaPortPins_t - * @brief Contains elements of \ref RAIL_BLE_AoxAntennaConfig_t struct. - */ -typedef struct RAIL_BLE_AoxAntennaPortPins { - /** - * The port which is used for AoX antenna switching - */ - uint8_t antPort; - /** - * The pin which is used for AoX antenna switching - */ - uint8_t antPin; -} RAIL_BLE_AoxAntennaPortPins_t; - -/** - * @struct RAIL_BLE_AoxAntennaConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigAoxAntenna function for - * EFR32XG22. - */ -typedef struct RAIL_BLE_AoxAntennaConfig { - /** - * A pointer to an array containing struct of port and pin used for - * AoX antenna switching - */ - RAIL_BLE_AoxAntennaPortPins_t *antPortPin; - /** - * Number of antenna pins to be configured. - */ - uint8_t antCount; -} RAIL_BLE_AoxAntennaConfig_t; - -/** - * Lock/unlock the CTE buffer from the application's perspective. The radio - * will write to the buffer only if the bit is NOT set at the beginning of the - * sampling period. The radio will set the bit once the sampling period starts - * to indicate that some CTE data has been collected, which will not be - * overwritten during the next sampling period, unless the buffer is unlocked by - * the application. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] lock Lock the CTE buffer if true and unlock it if false. - * @return True if the CTE buffer is locked after the call, otherwise false. - */ -bool RAIL_BLE_LockCteBuffer(RAIL_Handle_t railHandle, bool lock); - -/** - * Determine whether the CTE buffer is currently locked or not. - * - * @param[in] railHandle A handle for RAIL instance. - * @return True if CTE buffer is locked and false otherwise. - */ -bool RAIL_BLE_CteBufferIsLocked(RAIL_Handle_t railHandle); - -/** - * Get the offset into CTE sample of CTE data. - * - * @param[in] railHandle A handle for RAIL instance. - * @return The offset of CTE data in a CTE sample in bytes. - * On unsupported platforms this returns 0. - */ -uint8_t RAIL_BLE_GetCteSampleOffset(RAIL_Handle_t railHandle); - -/** - * Get the effective sample rate used by the ADC to capture the CTE samples. - * - * @param[in] railHandle A handle for RAIL instance. - * @return The actual sample rate used to capture the CTE in samples per second. - * On unsupported platforms this returns 0. - */ -uint32_t RAIL_BLE_GetCteSampleRate(RAIL_Handle_t railHandle); - -/** - * Configure Angle of Arrival/Departure (AoX) functionality. AoX is a method - * of radio localization which infers angle of arrival/departure of the signal - * based on different phases of the raw I/Q signal from different antennas by - * controlling external RF switch during the continuous tone extension (CTE). - * Connection based AoX packets are different than normal BLE packets in that - * they have 3 header bytes instead of 2 and they have CTE appended after the - * payload's CRC. 3rd byte or CTE info contains CTE length. Connectionless AoX - * packets have 2 header bytes and CTE info is part of the payload. AoX is - * supported on EFR32XG12/13/14 only on legacy 1Mbps BLE PHY. - * Note that calling \ref RAIL_GetRadioEntropy during AoX reception may break - * receiving packets. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] aoxConfig Configuration options for AoX - * @return RAIL_Status_t indicating success or failure of the call. - */ -RAIL_Status_t RAIL_BLE_ConfigAox(RAIL_Handle_t railHandle, - const RAIL_BLE_AoxConfig_t *aoxConfig); -/** - * Perform one time initialization of AoX registers. - * This function must be called before \ref RAIL_BLE_ConfigAox - * and before configuring the BLE PHY. - * - * @param[in] railHandle A RAIL instance handle. - * @return RAIL_Status_t indicating success or failure of the call. - */ -RAIL_Status_t RAIL_BLE_InitCte(RAIL_Handle_t railHandle); - -/** - * Perform initialization of AoX antenna GPIO pins. - * This function must be called before calls to \ref RAIL_BLE_InitCte - * and \ref RAIL_BLE_ConfigAox, and before configuring the BLE PHY, - * else a \ref RAIL_STATUS_INVALID_CALL is returned. - * - * If user configures more pins, i.e., antCount in - * \ref RAIL_BLE_AoxAntennaConfig_t, than allowed - * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the API returns - * \ref RAIL_STATUS_INVALID_PARAMETER. - * - * If user configures lesser than or equal to number of pins allowed by - * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the requested number of pins - * are configured and \ref RAIL_STATUS_NO_ERROR is returned. - * - * If AoX antenna switching is inactive, non-AoX transmits and receives - * will occur on the first antenna specified by the antenna pattern or - * on the default antenna if no antenna pattern is provided. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] antennaConfig structure to hold the set of ports and pins to - * configure Antenna pins for AoX Antenna switching. - * @return RAIL_Status_t indicating success or failure of the call. - */ -RAIL_Status_t RAIL_BLE_ConfigAoxAntenna(RAIL_Handle_t railHandle, - RAIL_BLE_AoxAntennaConfig_t *antennaConfig); - -/** @} */ // end of group AoX - - #ifndef DOXYGEN_SHOULD_SKIP_THIS -/****************************************************************************** - * High Accuracy Distance Measurement (HADM) - *****************************************************************************/ -/** - * @addtogroup HADM High Accuracy Distance Measurement - * @{ - * @brief These APIs are to a stack implementing BLE's high accuracy distance - * measurement functionality. - * - * They are designed for use by the Silicon Labs BLE stack only at this time and - * may cause problems if accessed directly. - */ - -/** - * @enum RAIL_BLE_HadmRole_t - * @brief The device role during HADM events. - */ -RAIL_ENUM(RAIL_BLE_HadmRole_t) { - /** Device cannot perform HADM events. */ - RAIL_BLE_HADM_ROLE_UNASSIGNED = 0, - /** Device is an initiator during HADM events */ - RAIL_BLE_HADM_ROLE_INITIATOR = 1, - /** Device is a reflector during HADM events */ - RAIL_BLE_HADM_ROLE_REFLECTOR = 2, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_BLE_HADM_ROLE_UNASSIGNED ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_UNASSIGNED) -#define RAIL_BLE_HADM_ROLE_INITIATOR ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_INITIATOR) -#define RAIL_BLE_HADM_ROLE_REFLECTOR ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_REFLECTOR) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_BLE_HadmResults_t - * @brief Contains measurement results from HADM step - */ -typedef struct { - uint32_t result[7]; /**< HADM measurement data for a particular step. */ -} RAIL_BLE_HadmResults_t; - -/** - * @enum RAIL_BLE_HadmRttType_t - * @brief HADM RTT Types. - */ -RAIL_ENUM(RAIL_BLE_HadmRttType_t) { - /** Coarse cost function engine method RTT. */ - RAIL_BLE_HADM_RTT_AA_ONLY = 0U, - /** 32 bit sounding sequence method RTT. */ - RAIL_BLE_HADM_RTT_32B_SS = 1U, - /** 96 bit sounding sequence method RTT. */ - RAIL_BLE_HADM_RTT_96B_SS = 2U, -}; - -/** - * The minimum size in 32 bit words for the IQ buffer. This value guarantees - * all IQ samples for a single 1mbps HADM step can be stored. - */ -#define RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE 600 - -/** - * @struct RAIL_BLE_HadmConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigHadm function. - */ -typedef struct RAIL_BLE_HadmConfig { - RAIL_BLE_HadmRole_t role; /**< The device role during HADM event. */ - uint16_t hadmSqteSteps; /**< Number of steps in HADM event. */ - /** Pointer to HADM measurements. Set to NULL if unused. */ - RAIL_BLE_HadmResults_t *pHadmDataOutput; - uint16_t t_fcs; /**< Frequency change spacing (in us). */ - uint16_t t_ip1; /**< Interlude period for mode 0 & 1 steps (in us). */ - uint16_t t_ip2; /**< Interlude period for mode 2 steps (in us). */ - uint16_t t_pm; /**< Phase measurement time (in us). */ - /** - * Pointer to buffer where IQ data will be written. Buffer must be 32-bit - * aligned. - */ - uint32_t *pIqBuffer; - /** - * Size of IQ buffer in 32 bit words. Must be at least \ref - * RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE or else an error will be - * returned by \ref RAIL_BLE_ConfigHadm. - */ - uint16_t iqBufferSize; - /** - * Step Index to perform the event calibration. This index must correspond - * to a mode 0 step or else the event calibration won't occur. - */ - uint8_t eventCalStepIndex; - RAIL_BLE_HadmRttType_t rttType; /**< RTT type returned during mode 1 step. */ - /** - * A pointer to the selected HADM event gain index. This field will be - * populated after \ref eventCalStepIndex has been reached. - */ - uint8_t *pEventGainIndex; - /** - * A pointer to the selected HADM event Fractional Frequency Offset - * (FFO) * 100. This field will be populated after \ref eventCalStepIndex - * has been reached. - */ - int16_t *pEventFfo; - bool disableRttGdComp; /**< Debug flag to disable RTT GD compensation. */ - bool disablePbrDcComp; /**< Debug flag to disable PBR DC compensation. */ - bool disablePbrGdComp; /**< Debug flag to disable PBR GD compensation. */ - bool forceAgcGain; /**< Debug flag to force event gain for calibration. */ - uint32_t forcedAgcStatus0; /**< Equivalent AGC status0 register to force. */ -} RAIL_BLE_HadmConfig_t; - -/** The maximum number of HADM steps allowed during a HADM event */ -#define RAIL_BLE_HADM_MAX_SQTE_STEPS 512 - -/** - * @enum RAIL_BLE_HadmStepState_t - * @brief The current HADM step state. - */ -RAIL_ENUM(RAIL_BLE_HadmStepState_t) { - /** HADM step state idle */ - RAIL_BLE_HADM_STATE_IDLE = 0, - /** HADM step state initiator initiator transmit mode 0 */ - RAIL_BLE_HADM_STATE_I_TX_MODE0 = 1, - /** HADM step state initiator reflector transmit mode 0 */ - RAIL_BLE_HADM_STATE_R_TX_MODE0 = 2, - /** HADM step state initiator initiator transmit mode 1 */ - RAIL_BLE_HADM_STATE_I_TX_MODE1 = 3, - /** HADM step state initiator reflector transmit mode 1 */ - RAIL_BLE_HADM_STATE_R_TX_MODE1 = 4, - /** HADM step state initiator initiator transmit mode 2 */ - RAIL_BLE_HADM_STATE_R_TX_MODE2 = 6, - /** HADM step state initiator reflector transmit mode 2 */ - RAIL_BLE_HADM_STATE_I_TX_MODE2 = 7, -}; - -/** - * First step state for HADM mode 0. - */ -#define RAIL_BLE_HADM_STEP_MODE0 RAIL_BLE_HADM_STATE_I_TX_MODE0 - -/** - * First step state for HADM mode 1. - */ -#define RAIL_BLE_HADM_STEP_MODE1 RAIL_BLE_HADM_STATE_I_TX_MODE1 - -/** - * First step state for HADM mode 2. - */ -#define RAIL_BLE_HADM_STEP_MODE2 RAIL_BLE_HADM_STATE_I_TX_MODE2 - -/** - * @enum RAIL_BLE_HadmStepMode_t - * @brief The HADM step mode. - */ -RAIL_ENUM(RAIL_BLE_HadmStepMode_t) { - RAIL_BLE_HADM_MODE_0, /**< HADM step mode 0. */ - RAIL_BLE_HADM_MODE_1, /**< HADM step mode 1. */ - RAIL_BLE_HADM_MODE_2, /**< HADM step mode 2. */ - RAIL_BLE_HADM_MODE_3, /**< HADM step mode 3. */ -}; - -/** - * @enum RAIL_BLE_HadmAntennaId_t - * @brief The HADM antenna ID. - */ -RAIL_ENUM(RAIL_BLE_HadmAntennaId_t) { - RAIL_BLE_HADM_ANTENNA_1 = 0, /**< HADM antenna ID 1. */ - RAIL_BLE_HADM_ANTENNA_2, /**< HADM antenna ID 2. */ - RAIL_BLE_HADM_ANTENNA_3, /**< HADM antenna ID 3. */ - RAIL_BLE_HADM_ANTENNA_4, /**< HADM antenna ID 4. */ -}; - -/** - * @enum RAIL_BLE_HadmRttPacketQuality_t - * @brief HADM RTT packet quality. - */ -RAIL_ENUM(RAIL_BLE_HadmRttPacketQuality_t) { - /** Access address check succeeded. */ - RAIL_BLE_HADM_RTT_AA_SUCCESS = 0U, - /** Access address had one or more bit errors. */ - RAIL_BLE_HADM_RTT_AA_BIT_ERRORS = 1U, - /** Access address not found. */ - RAIL_BLE_HADM_RTT_AA_NOT_FOUND = 2U, -}; - -/** - * @struct RAIL_BLE_HadmMode0Results_t - * @brief Contains HADM mode 0 step measurement results. - */ -typedef struct RAIL_BLE_HadmMode0Results { - /** Mode of HADM step. */ - uint8_t mode; - /** Antenna ID. */ - RAIL_BLE_HadmAntennaId_t antenna; - /** RSSI during step in integer dBm. */ - int8_t rssi; - /** Packet quality */ - uint8_t packetQuality; - /** Reserved */ - uint16_t reserved; - /** Fractional Frequency Offset (FFO) * 100 */ - int16_t hadmFfo; - /** The gain setting. */ - uint32_t stepGainSetting; - /** Reserved */ - uint32_t reserved1; -} RAIL_BLE_HadmMode0Results_t; - -/** - * A sentinel value to indicate an invalid rtt time value in - * \ref RAIL_BLE_HadmMode1Results_t::rttHalfNs - */ -#define RAIL_BLE_HADM_INVALID_RTT_VALUE ((int16_t)0x8000) - -/** - * @struct RAIL_BLE_HadmMode1Results_t - * @brief Contains HADM mode 1 step measurement results. - */ -typedef struct RAIL_BLE_HadmMode1Results { - /** Mode of HADM step. */ - uint8_t mode; - /** Antenna ID. */ - RAIL_BLE_HadmAntennaId_t antenna; - /** RSSI during step in integer dBm. */ - int8_t rssi; - /** Packet quality */ - uint8_t packetQuality; - /** - * For the initiator, this is the time (in 0.5 ns units) between time of - * departure and time of arrival excluding known offsets such as interlude - * period and packet length. - * For the reflector, this is the time (in 0.5 ns units) between time of - * arrival and time of departure excluding known offsets such as interlude - * period and packet length. - */ - int16_t rttHalfNs; - /** Flag used to indicate whether we have missed FCAL during calibration */ - uint8_t missedFcal; - /** Reserved */ - uint8_t reserved1; - /** Reserved */ - uint32_t reserved2[2]; -} RAIL_BLE_HadmMode1Results_t; - -/** - * @enum RAIL_BLE_HadmToneQuality_t - * @brief HADM tone quality. - */ -RAIL_ENUM(RAIL_BLE_HadmToneQuality_t) { - /** Good quality HADM mode 2 tone. */ - RAIL_BLE_HADM_TONE_QUALITY_GOOD = 0U, - /** Medium quality HADM mode 2 tone. */ - RAIL_BLE_HADM_TONE_QUALITY_MEDIUM = 1U, - /** Low quality HADM mode 2 tone. */ - RAIL_BLE_HADM_TONE_QUALITY_LOW = 2U, - /** HADM mode 2 tone quality indication unavailable. */ - RAIL_BLE_HADM_TONE_QUALITY_UNAVAILABLE = 3U, -}; - -/** - * @struct RAIL_BLE_HadmMode2Results_t - * @brief Contains HADM mode 2 step measurement results. - */ -typedef struct RAIL_BLE_HadmMode2Results { - /** Mode of HADM step. */ - uint8_t mode; - /** Antenna ID. */ - RAIL_BLE_HadmAntennaId_t antenna; - /** Flag used to indicate whether we have missed FCAL during calibration */ - uint8_t missedFcal; - /** Reserved */ - uint8_t reserved1; - /** PCT i value */ - int16_t pctI; - /** PCT q value */ - int16_t pctQ; - /** Tone extension PCT i value */ - int16_t pctToneExtI; - /** Tone extension PCT q value */ - int16_t pctToneExtQ; - /** Tone quality indicator */ - RAIL_BLE_HadmToneQuality_t tqi; - /** Tone quality indicator for tone extension */ - RAIL_BLE_HadmToneQuality_t tqiToneExt; - /** Reserved */ - uint16_t reserved2; -} RAIL_BLE_HadmMode2Results_t; - -/** - * @struct RAIL_BLE_HadmStepResults_t - * @brief Generic HADM step mode result structure. Based on the value of the - * mode field, this structure can be type cast to the appropriate mode - * specific structure \ref RAIL_BLE_HadmMode0Results_t, - * \ref RAIL_BLE_HadmMode1Results_t, or RAIL_BLE_HadmMode2Results_t. - */ -typedef struct RAIL_BLE_HadmStepResults { - /** Mode of HADM step. */ - uint8_t mode; - /** Reserved */ - uint8_t reserved0; - /** Reserved */ - uint16_t reserved1; - /** Reserved */ - uint32_t reserved2[3]; -} RAIL_BLE_HadmStepResults_t; - -/** - * @struct RAIL_BLE_HadmMode0DebugResults_t - * @brief Contains HADM mode 0 step measurement debug results. - */ -typedef struct RAIL_BLE_HadmMode0DebugResults { - /** Highest recorded RSSI up to and including the current mode 0 step. */ - int16_t highestRssi; - /** - * FFO of the Mode 0 step with the highest recorded RSSI - * up to and including the current Mode 0 step. - */ - int16_t hadmFfo; - /** - * AGC gain value of the Mode 0 step with the highest recorded - * RSSI up to and including the current Mode 0 step. - */ - uint32_t agcStatus0; - /** - * For devices configured as an initiator, the measured frequency offset - * in Hz between the two devices during a HADM mode 0 step. For devices - * configured as a reflector, this value will always be 0. - */ - int32_t freqOffHz; - /** - * Estimated coarse frequency offset in internal units. - */ - int32_t hwFreqOffEst; - /** Reserved */ - uint32_t reserved[3]; -} RAIL_BLE_HadmMode0DebugResults_t; - -/** - * @struct RAIL_BLE_HadmMode1DebugResults_t - * @brief Contains HADM mode 1 step measurement debug results. - */ -typedef struct RAIL_BLE_HadmMode1DebugResults { - uint16_t toxClks; - int16_t fracRttHalfNs; - uint32_t coarseRttHalfNs; - int32_t gdCompRttHalfNs; - int32_t toxWithOffsetsRttHalfNs; - uint32_t hadmstatus3; - uint32_t hadmstatus4; - uint32_t hadmstatus5; -} RAIL_BLE_HadmMode1DebugResults_t; - -/** - * @struct RAIL_BLE_HadmMode2DebugResults_t - * @brief Contains HADM mode 2 step measurement debug results. - */ -typedef struct RAIL_BLE_HadmMode2DebugResults { - /** DCCOMP i value */ - int16_t dcCompI; - /** DCCOMP q value */ - int16_t dcCompQ; - /** GDCOMP i value */ - int16_t gdCompI; - /** GDCOMP q value */ - int16_t gdCompQ; - /** Raw tone quality value */ - uint16_t tqiRaw; - /** Raw tone quality tone extension value */ - uint16_t tqiToneExtRaw; - /** FCAL value from SYNTH_VCOTUNING */ - uint16_t fcal; - /** Reserved */ - uint16_t reserved; - /** Reserved */ - uint32_t reserved1[3]; -} RAIL_BLE_HadmMode2DebugResults_t; - -/** - * @struct RAIL_BLE_HadmStepDebugResults_t - * @brief Generic HADM step mode debug result structure. Based on the value of - * the mode field, this structure can be type cast to the appropriate mode - * specific structure \ref RAIL_BLE_HadmMode0DebugResults_t, - * \ref RAIL_BLE_HadmMode1DebugResults_t, or RAIL_BLE_HadmMode2DebugResults_t. - */ -typedef struct RAIL_BLE_HadmStepDebugResults { - uint32_t reserved; - uint32_t reserved1; - uint32_t reserved2; - uint32_t reserved3; - uint32_t reserved4; - uint32_t reserved5; - uint32_t reserved6; -} RAIL_BLE_HadmStepDebugResults_t; - -/** - * @struct RAIL_BLE_HadmStepConfig_t - * @brief Contains arguments for \ref RAIL_BLE_SetNextHadmStep. - */ -typedef struct RAIL_BLE_HadmStepConfig { - /** Sets the HADM step state. */ - RAIL_BLE_HadmStepState_t stepState; - /** Indicates whether this is final step in HADM event. */ - bool lastStep; - /** - * Transmit tone during tone extension slot in mode 2 packet. - * This field is ignored during RX and for all non mode 2 packets. - */ - bool transmitToneExtension; - /** Sets the HADM step logical channel. */ - uint16_t channel; - /** - * Length of packet payload in bytes. Should not include trailer, guard, - * or UC bits. Only used for mode 1 steps, ignored otherwise. - */ - uint16_t packetLength; - /** The initiator (first) access address during step. */ - uint32_t initAccessAddress; - /** The reflector (second) access address during step. */ - uint32_t reflAccessAddress; - /** Pointer to TX data to be transmitted. Ignored for mode 0 and 2 steps. */ - uint8_t *pTxData; - /** RTT marker bit position. Ignored for mode 0 and 2 steps. */ - uint8_t rttMarkerBitPosition[2]; - /** - * A pointer to an array of HADM step results. These results will be - * populated after the completion of the HADM step. This array can be cast to - * \ref RAIL_BLE_HadmMode0Results_t, \ref RAIL_BLE_HadmMode1Results_t, or - * \ref RAIL_BLE_HadmMode2Results_t as appropriate to read mode specific - * results. - */ - RAIL_BLE_HadmStepResults_t *pResults; - /** - * A pointer to an array of HADM step debug results. These results will be - * populated after the completion of the HADM step. This array can be cast to - * \ref RAIL_BLE_HadmMode0DebugResults_t, \ref - * RAIL_BLE_HadmMode1DebugResults_t, or \ref RAIL_BLE_HadmMode2DebugResults_t - * as appropriate to read mode specific debug results. - * - * Setting this pointer to NULL means no debug data will be collected. - */ - RAIL_BLE_HadmStepDebugResults_t *pDebugResults; - /** - * Pointer to contiguous global read-write memory that will be used - * by RAIL to store channel switching information. - * It need not be initialized and applications should never write - * data anywhere in this buffer. - * - * @note the size in words of this buffer must be at least as large as - * 3 + /ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL. This buffer - * is for internal use to the library. - */ - uint32_t *pBuffer; - /** - * This parameter must be set to the length of the buffer array. This way, - * during configuration, the software can confirm it's writing within the - * range of the buffer. The configuration API will return an error - * if bufferLength is insufficient. - */ - uint16_t bufferLength; - /** Reserved */ - uint16_t reserved0; - /** - * A pointer to the start of captured IQ data for this step. This pointer - * will be populated after the completion of the HADM step. - */ - uint32_t **pIqBuffer; - /** - * A pointer to captured IQ data size in 32 bit words. This pointer will be - * populated after the completion of the HADM step. - */ - uint16_t *pIqBufferSize; - /** - * A pointer to a boolean to indicate whether to preserve IQ data for this - * step. If this is the final step of the event, IQ data will automatically - * be preserved regardless of how this boolean is set. For other steps, if - * this boolean is set true, and there are at least \ref - * RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE unused 32 bit words still - * available in the event IQ buffer, this step's IQ data will be preserved - * and not be overwritten by IQ data from a subsequent step. Otherwise, this - * step's IQ data will not be preserved and may be overwritten. This boolean - * will be updated after completion of the HADM step to indicate whether the - * IQ data from that step was actually preserved. - */ - bool *pSaveIqData; -} RAIL_BLE_HadmStepConfig_t; - -/** - * @struct RAIL_BLE_HadmAntennaConfig_t - * @brief Contains arguments for \ref RAIL_BLE_ConfigHadmAntenna function. - */ -typedef struct RAIL_BLE_HadmAntennaConfig { - int8_t antennaCount; /**< Total number of antenna elements. */ - const int16_t *pAntennaOffsetCm; /**< Pointer to antenna offsets in cm units. */ -} RAIL_BLE_HadmAntennaConfig_t; - -/** The maximum number of antennas supported. */ -#define RAIL_BLE_HADM_MAX_ANTENNAS 4 - -/** - * @struct RAIL_BLE_HadmGdCompTables_t - * @brief Contains pointers to HADM group delay compensation tables. - */ -typedef struct RAIL_BLE_HadmGdCompTables { - /** Pointer to PBR phase LSB group delay compensation table. */ - const int16_t *pPbrPhaseLsb; - /** Pointer to RTT slope group delay compensation table. */ - const int16_t *pRttSlope; - /** Pointer to RTT offset group delay compensation table. */ - const int16_t *pRttOffset; - /** Common length for each table in units of int16_t. */ - uint8_t length; -} RAIL_BLE_HadmGdCompTables_t; - -/** - * Configure High Accuracy Distance Measurement (HADM) functionality. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] hadmConfig Configuration options for HADM. - * @return RAIL_Status_t indicating success or failure of the call. - * - * @warning This API is not safe to use in a multiprotocol app. - */ -RAIL_Status_t RAIL_BLE_ConfigHadm(RAIL_Handle_t railHandle, - const RAIL_BLE_HadmConfig_t *hadmConfig); - -/** - * Enable High Accuracy Distance Measurement (HADM) functionality. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Enable or disable HADM functionality. - * @return RAIL_Status_t indicating success or failure of the call. - * - * @warning This API is not safe to use in a multiprotocol app. - */ -RAIL_Status_t RAIL_BLE_EnableHadm(RAIL_Handle_t railHandle, - bool enable); - -/** - * Set up the next HADM step. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] hadmStepConfig Configuration options for next HADM step. - * @param[in] pend If true, apply configuration at next appropriate radio - * transition (i.e. at Rx2Tx for an initiator, or Tx2Rx for a reflector). - * Otherwise, apply configuration immediately. - * @return RAIL_Status_t indicating success or failure of the call. - * - * @note When the next HADM step is to be pended, the specified step in - * hadmStepConfig must be the initial step state for a particular mode (e.g. - * \ref RAIL_BLE_HADM_STEP_MODE0, \ref RAIL_BLE_HADM_STEP_MODE1, or \ref - * RAIL_BLE_HADM_STEP_MODE2). Otherwise this API will return \ref - * RAIL_STATUS_INVALID_PARAMETER. - * - * @warning This API is not safe to use in a multiprotocol app. - */ -RAIL_Status_t RAIL_BLE_SetNextHadmStep(RAIL_Handle_t railHandle, - const RAIL_BLE_HadmStepConfig_t *hadmStepConfig, - bool pend); - -/** - * Configure antennas for HADM event. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] pAntennaConfig A pointer to the antenna config - * @return RAIL_Status_t indicating success or failure of the call. - */ -RAIL_Status_t RAIL_BLE_ConfigHadmAntenna(RAIL_Handle_t railHandle, - RAIL_BLE_HadmAntennaConfig_t *pAntennaConfig); - -/** - * Loads the HADM RTT and PBR group delay compensation tables for a - * particular PA mode. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] pTables Pointer to group delay compensation lookup tables. - * @param[in] powerMode The PA mode for which to load compensation tables. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_BLE_LoadHadmCompTables(RAIL_Handle_t railHandle, - const RAIL_BLE_HadmGdCompTables_t *pTables, - RAIL_TxPowerMode_t powerMode); - -/** - * Callback used to load HADM group delay compensation tables for all PA modes - * supported by device during \ref RAIL_BLE_EnableHadm when enable is true. - * This function is optional to implement. - * - * @return Status code indicating success of the function call. - * - * @note If this callback function is not implemented, unneeded tables may not - * be dead stripped, resulting in larger overall code size. The API \ref - * RAIL_BLE_LoadHadmCompTables should be used within this callback to load the - * appropriate tables for each supported PA mode. - */ -RAIL_Status_t RAILCb_BLE_HadmGdCompTableLoad(void); - -/** @} */ // end of group HADM -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/// @addtogroup BLETX2TX BLE TX Channel Hopping -/// @{ -/// @code{.c} -/// -/// // Configuration to send one additional packet -/// static RAIL_BLE_TxChannelHoppingConfigEntry_t entry[1]; -/// static uint32_t buffer[BUFFER_SIZE]; -/// static RAIL_BLE_TxRepeatConfig_t repeat = { -/// .iterations = 1, -/// .repeatOptions = RAIL_TX_REPEAT_OPTION_HOP, -/// .delayOrHop.channelHopping = { -/// .buffer = buffer, -/// .bufferLength = BUFFER_SIZE, -/// .numberOfChannels = 1, -/// .entries = &entry[0], -/// }, -/// }; -/// -/// // Send a normal packet on the current channel, then a packet on a new channel -/// int bleSendThenAdvertise(uint8_t *firstPacket, uint8_t *secondPacket) -/// { -/// // Load both packets into the FIFO -/// RAIL_WriteTxFifo(railHandle, firstPacket, FIRST_PACKET_LEN, true); -/// RAIL_WriteTxFifo(railHandle, secondPacket, SECOND_PACKET_LEN, false); -/// -/// // Configure a 300 us turnaround between transmits -/// entry[0].delayMode = RAIL_CHANNEL_HOPPING_DELAY_MODE_STATIC; -/// entry[0].delay = 300; // microseconds -/// -/// // Use default advertising parameters -/// entry[0].disableWhitening = false; -/// entry[0].crcInit = 0x00555555; -/// entry[0].accessAddress = 0x8E89BED6; -/// -/// // Transmit the repeated packet on the first advertising channel -/// entry[0].phy = RAIL_BLE_1Mbps; -/// entry[0].railChannel = 0; -/// entry[0].logicalChannel = 37; -/// -/// // Configure repeated transmit in RAIL, then transmit, sending both packets -/// RAIL_BLE_SetNextTxRepeat(railHandle, &repeat); -/// RAIL_StartTx(railHandle, currentChannel, RAIL_TX_OPTIONS_DEFAULT, NULL); -/// } -/// @endcode - -/** - * @struct RAIL_BLE_TxChannelHoppingConfigEntry_t - * @brief Structure that represents one of the channels that is part of a - * \ref RAIL_BLE_TxChannelHoppingConfig_t sequence of channels used in - * channel hopping. - */ -typedef struct RAIL_BLE_TxChannelHoppingConfigEntry { - /** - * Idle time in microseconds to wait before hopping into the - * channel indicated by this entry. - */ - uint32_t delay; - /** - * The BLE PHY to use for this hop's transmit. - */ - RAIL_BLE_Phy_t phy; - /** - * The logical channel to use for this hop's transmit. The whitener will - * be reinitialized if used. - */ - uint8_t logicalChannel; - /** - * The channel number to be used for this hop's transmit. If this is an - * invalid channel for the chosen PHY, the call to \ref RAIL_SetNextTxRepeat() - * will fail. - */ - uint8_t railChannel; - /** - * This can turn off the whitening engine and is useful for sending BLE test - * mode packets that don't have this turned on. - */ - bool disableWhitening; - /** - * The value to use for CRC initialization. - */ - uint32_t crcInit; - /** - * The access address to use for the connection. - */ - uint32_t accessAddress; -} RAIL_BLE_TxChannelHoppingConfigEntry_t; - -/** - * @struct RAIL_BLE_TxChannelHoppingConfig_t - * @brief Wrapper struct that will contain the sequence of - * \ref RAIL_BLE_TxChannelHoppingConfigEntry_t that represents the channel - * sequence to use during TX Channel Hopping. - */ -typedef struct RAIL_BLE_TxChannelHoppingConfig { - /** - * Pointer to contiguous global read-write memory that will be used - * by RAIL to store channel hopping information throughout its operation. - * It need not be initialized and applications should never write - * data anywhere in this buffer. - */ - uint32_t *buffer; - /** - * This parameter must be set to the length of the buffer array. This way, - * during configuration, the software can confirm it's writing within the - * range of the buffer. The configuration API will return an error - * if bufferLength is insufficient. - */ - uint16_t bufferLength; - /** The number of channels that is in the channel hopping sequence. */ - uint8_t numberOfChannels; - /** - * Pad bytes reserved for future use and currently ignored. - */ - uint8_t reserved; - /** - * A pointer to the first element of an array of \ref - * RAIL_BLE_TxChannelHoppingConfigEntry_t that represents the channels - * used during channel hopping. The length of this array must be - * numberOfChannels. - */ - RAIL_BLE_TxChannelHoppingConfigEntry_t *entries; -} RAIL_BLE_TxChannelHoppingConfig_t; - -/// @struct RAIL_BLE_TxRepeatConfig_t -/// @brief A configuration structure for repeated transmits -/// -typedef struct RAIL_BLE_TxRepeatConfig { - /** - * The number of repeated transmits to run. A total of (iterations + 1) - * transmits will go on-air in the absence of errors. - */ - uint16_t iterations; - /** - * Repeat option(s) to apply. - */ - RAIL_TxRepeatOptions_t repeatOptions; - /** - * Per-repeat delay or hopping configuration, depending on repeatOptions. - */ - union { - /** - * When \ref RAIL_TX_REPEAT_OPTION_HOP is not set, this specifies - * the delay time between each repeated transmit. Specify \ref - * RAIL_TRANSITION_TIME_KEEP to use the current \ref - * RAIL_StateTiming_t::txToTx transition time setting. - */ - RAIL_TransitionTime_t delay; - /** - * When \ref RAIL_TX_REPEAT_OPTION_HOP is set, this specifies - * the channel hopping configuration to use when hopping between - * repeated transmits. Per-hop delays are configured within each - * \ref RAIL_BLE_TxChannelHoppingConfigEntry_t::delay rather than - * this union's delay field. - */ - RAIL_BLE_TxChannelHoppingConfig_t channelHopping; - } delayOrHop; -} RAIL_BLE_TxRepeatConfig_t; - -/** - * Set up automatic repeated transmits after the next transmit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] repeatConfig The configuration structure for repeated transmits. - * @return Status code indicating a success of the function call. - * - * Repeated transmits will occur after an application-initiated transmit caused - * by calling one of the \ref Packet_TX APIs. The repetition will only occur - * after the first application-initiated transmit after this function is - * called. Future repeated transmits must be requested by calling this function - * again. - * - * Each repeated transmit that occurs will have full \ref PTI information and - * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. - * - * If a TX error occurs during the repetition, the process will abort and the - * TX error transition from \ref RAIL_SetTxTransitions will be used. If the - * repetition completes successfully, the TX success transition from - * \ref RAIL_SetTxTransitions will be used. - * - * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending - * repeated transmits. The state will also be cleared by another call to this - * function. To clear the repeated transmits before they've started without - * stopping other radio actions, call this function with a \ref - * RAIL_BLE_TxRepeatConfig_t::iterations count of 0. A DMP switch will clear this - * state only if the initial transmit triggering the repeated transmits has - * started. - * - * The application is responsible for populating the transmit data to be used - * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. - * Data will be transmitted from the TX FIFO. If the TX FIFO does not have - * sufficient data to transmit, a TX error and a \ref - * RAIL_EVENT_TX_UNDERFLOW will occur. To avoid an underflow, the - * application should queue data to be transmitted as early as possible. - * - * This function will fail to configure the repetition if a transmit of any - * kind is ongoing, including during the time between an initial transmit and - * the end of a previously-configured repetition. - * - * @note This feature/API is not supported on the EFR32XG1 family of chips. - * Use the compile time symbol \ref RAIL_SUPPORTS_TX_TO_TX or the runtime - * call \ref RAIL_SupportsTxToTx() to check whether the platform supports - * this feature. - */ -RAIL_Status_t RAIL_BLE_SetNextTxRepeat(RAIL_Handle_t railHandle, - const RAIL_BLE_TxRepeatConfig_t *repeatConfig); - -/** @} */ // end of group BLETX2TX - -/** @} */ // end of BLE - -/// @addtogroup Calibration -/// @brief Bluetooth protocol-specific APIs for calibrating the radio. -/// @{ - -/** - * Calibrate image rejection for Bluetooth Low Energy. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. - * - * Some chips have protocol-specific image rejection calibrations programmed - * into their flash. This function will either get the value from flash and - * apply it, or run the image rejection algorithm to find the value. - */ -RAIL_Status_t RAIL_BLE_CalibrateIr(RAIL_Handle_t railHandle, - uint32_t *imageRejection); - -/// @} // End of group Calibration - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_BLE_H__ +/***************************************************************************//** + * @file + * @brief The BLE specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_BLE_H__ +#define __RAIL_BLE_H__ + +// Get the standard include types +#include +#include + +// Get the RAIL specific structures and types +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @addtogroup BLE +/// @ingroup Protocol_Specific +/// Accelerator routines for Bluetooth Low Energy (BLE). +/// +/// The APIs in this module configure the radio for BLE +/// operation and provide additional helper routines necessary for +/// normal BLE send/receive that aren't available directly in RAIL. +/// RAIL APIs should be used to set up the application. However, +/// RAIL_ConfigChannels() and RAIL_ConfigRadio() should not be called to set up +/// the PHY. Instead, RAIL_BLE_Config* APIs should be used to set up the +/// 1 Mbps, 2 Mbps, or Coded PHY configurations needed by the application. These +/// APIs will configure the hardware and also configure the set of valid BLE +/// channels. +/// +/// To implement a standard BLE link layer, you will also need to handle tight +/// turnaround times and send packets at specific instants. This can all be +/// managed through general RAIL functions, such as RAIL_ScheduleTx(), +/// RAIL_ScheduleRx(), and RAIL_SetStateTiming(). See RAIL APIs for more +/// useful functions. +/// +/// A simple example to set up the application to be in BLE mode is shown +/// below. Note that this will put the radio on the first advertising channel +/// with the advertising Access Address. In any full-featured BLE application you +/// will need to use the RAIL_BLE_ConfigChannelRadioParams() function to change +/// the sync word and other parameters as needed based on your connection. +/// +/// @code{.c} +/// +/// // RAIL Handle set at initialization time. +/// static RAIL_Handle_t gRailHandle = NULL; +/// +/// static void radioEventHandler(RAIL_Handle_t railHandle, +/// RAIL_Events_t events) +/// { +/// // ... handle RAIL events, e.g., receive and transmit completion +/// } +/// +/// #if MULTIPROTOCOL +/// // Allocate memory for RAIL to hold BLE-specific state information +/// static RAIL_BLE_State_t bleState; // Must never be const +/// static RAILSched_Config_t schedCfg; // Must never be const +/// static RAIL_Config_t railCfg = { // Must never be const +/// .eventsCallback = &radioEventHandler, +/// .protocol = &bleState, // For BLE, RAIL needs additional state memory +/// .scheduler = &schedCfg, // For MultiProtocol, additional scheduler memory +/// }; +/// #else +/// static RAIL_Config_t railCfg = { // Must never be const +/// .eventsCallback = &radioEventHandler, +/// .protocol = NULL, +/// .scheduler = NULL, +/// }; +/// #endif +/// +/// // Set the radio to receive on the first BLE advertising channel. +/// int bleAdvertiseEnable(void) +/// { +/// // Initializes the RAIL library and any internal state it requires. +/// gRailHandle = RAIL_Init(&railCfg, NULL); +/// +/// // Calls the BLE initialization function to load the right radio configuration. +/// RAIL_BLE_Init(gRailHandle); +/// +/// // Always choose the Viterbi PHY configuration if available on your chip +/// // for performance reasons. +/// RAIL_BLE_ConfigPhy1MbpsViterbi(gRailHandle); +/// +/// // Configures us for the first advertising channel (Physical: 0, Logical: 37). +/// // The CRC init value and Access Address come from the BLE specification. +/// RAIL_BLE_ConfigChannelRadioParams(gRailHandle, +/// 0x555555, +/// 0x8E89BED6, +/// 37, +/// false); +/// +/// // Starts receiving on physical channel 0 (logical channel 37). +/// RAIL_StartRx(gRailHandle, 0, NULL); +/// } +/// @endcode +/// +/// @{ + +/** + * @enum RAIL_BLE_Coding_t + * @brief The variant of the BLE Coded PHY. + */ +RAIL_ENUM(RAIL_BLE_Coding_t) { + /** Enables the 125 kbps variant of the BLE Coded PHY */ + RAIL_BLE_Coding_125kbps = 0, + /** @deprecated Will be removed in a future version of RAIL */ + RAIL_BLE_Coding_125kbps_DSA = 1, + /** Enables the 500 kbps variant of the BLE Coded PHY */ + RAIL_BLE_Coding_500kbps = 2, + /** @deprecated Will be removed in a future version of RAIL */ + RAIL_BLE_Coding_500kbps_DSA = 3, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_Coding_125kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps) +#define RAIL_BLE_Coding_125kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_125kbps_DSA) +#define RAIL_BLE_Coding_500kbps ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps) +#define RAIL_BLE_Coding_500kbps_DSA ((RAIL_BLE_Coding_t) RAIL_BLE_Coding_500kbps_DSA) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_BLE_Phy_t + * @brief The variant of the BLE PHY. + */ +RAIL_ENUM(RAIL_BLE_Phy_t) { + /** Use the standard BLE 1Mbps PHY */ + RAIL_BLE_1Mbps, + /** Use the high data rate BLE 2Mbps PHY */ + RAIL_BLE_2Mbps, + /** Enables the 125 kbps variant of the BLE Coded PHY */ + RAIL_BLE_Coded125kbps, + /** Enables the 500 kbps variant of the BLE Coded PHY */ + RAIL_BLE_Coded500kbps, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_1Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_1Mbps) +#define RAIL_BLE_2Mbps ((RAIL_BLE_Phy_t) RAIL_BLE_2Mbps) +#define RAIL_BLE_Coded125kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded125kbps) +#define RAIL_BLE_Coded500kbps ((RAIL_BLE_Phy_t) RAIL_BLE_Coded500kbps) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/// @addtogroup BLE_PHY BLE Radio Configurations +/// Radio configurations for the RAIL BLE Accelerator +/// +/// These radio configurations are used to configure BLE when a function such +/// as \ref RAIL_BLE_ConfigPhy1MbpsViterbi() is called. Each radio +/// configuration listed below is compiled into the RAIL library as a weak +/// symbol that will take into account per-die defaults. If the board +/// configuration in use has different settings than the default, such as a +/// different radio subsystem clock frequency, these radio configurations can +/// be overriden to account for those settings. +/// @{ + +/** + * Default PHY to use for BLE 1M non-Viterbi. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_1MBPS_NON_VITERBI is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1Mbps; + +/** + * Default PHY to use for BLE 2M non-Viterbi. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_2MBPS_NON_VITERBI is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2Mbps; + +/** + * Default PHY to use for BLE 1M Viterbi. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_1MBPS_VITERBI is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbi; + +/** + * Default PHY to use for BLE 2M Viterbi. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbi; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Default PHY to use for BLE 1M Viterbi HADM. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_HADM is 0. On EFR32XG24, this will also + * be NULL for non 40MHz HFXO frequencies. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy1MbpsViterbiHadm; + +/** + * Default PHY to use for BLE 2M Viterbi HADM. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_HADM is 0. On EFR32XG24, this will also + * be NULL for non 40MHz HFXO frequencies. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsViterbiHadm; +#endif + +/** + * PHY to use for BLE 2M with AoX functionality. Will be NULL if either + * \ref RAIL_BLE_SUPPORTS_2MBPS_VITERBI or \ref RAIL_BLE_SUPPORTS_AOX is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy2MbpsAox; + +/** + * Default PHY to use for BLE Coded 125kbps. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both + * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy125kbps; + +/** + * Default PHY to use for BLE Coded 500kbps. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_CODED_PHY is 0. This PHY can receive on both + * 125kbps and 500kbps BLE Coded, but will only transmit at 125kbps. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_Phy500kbps; + +/** + * Default PHY to use for BLE Simulscan. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY is 0. This PHY can receive on 1Mbps + * as well as 125kbps and 500kbps BLE Coded, but will only transmit at 1Mbps. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhySimulscan; + +/** + * Default 1Mbps Quuppa PHY. Will be NULL if + * \ref RAIL_BLE_SUPPORTS_QUUPPA is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_BLE_PhyQuuppa; + +/// @} // End of group BLE_PHY + +// Defines for subPhyID field in RAIL_RxPacketDetails_t +/** subPhyId indicating a 500kbps packet */ +#define RAIL_BLE_RX_SUBPHY_ID_500K (0U) +/** subPhyId indicating a 125kbps packet */ +#define RAIL_BLE_RX_SUBPHY_ID_125K (1U) +/** subPhyId value indicating a 1Mbps packet */ +#define RAIL_BLE_RX_SUBPHY_ID_1M (2U) +/** Invalid subPhyId value */ +#define RAIL_BLE_RX_SUBPHY_ID_INVALID (3U) +/** subPhyId indicating the total count */ +#define RAIL_BLE_RX_SUBPHY_COUNT (4U) + +/** + * @enum RAIL_BLE_SignalIdentifierMode_t + * @brief Available Signal Identifier modes. + */ +RAIL_ENUM(RAIL_BLE_SignalIdentifierMode_t) { + /* Disable signal detection mode. */ + RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, + /* BLE 1Mbps (GFSK) detection mode. */ + RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS, + /* BLE 2Mbps (GFSK) detection mode. */ + RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_DISABLE) +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_1MBPS) +#define RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS ((RAIL_BLE_SignalIdentifierMode_t)RAIL_BLE_SIGNAL_IDENTIFIER_MODE_2MBPS) +#endif + +/** + * @struct RAIL_BLE_State_t + * @brief A state structure for BLE. + * + * This structure must be allocated in application global read-write memory + * that persists for the duration of BLE usage. It cannot be allocated + * in read-only memory or on the call stack. + */ +typedef struct RAIL_BLE_State { + uint32_t crcInit; /**< The value used to initialize the CRC algorithm. */ + uint32_t accessAddress; /**< The access address used for the connection. */ + uint16_t channel; /**< The logical channel used. */ + bool disableWhitening; /**< Indicates whether the whitening engine should be off. */ + uint16_t whiteInit; /**< The value used to initialize the whitening algorithm */ +} RAIL_BLE_State_t; + +/** + * Configure RAIL to run in BLE mode. + * + * @param[in] railHandle A handle for RAIL instance. + * This function changes your radio, channel configuration, and other + * parameters to match what is needed for BLE. To switch back to a + * default RAIL mode, call RAIL_BLE_Deinit() first. This function + * will configure the protocol output on PTI to \ref RAIL_PTI_PROTOCOL_BLE. + * + * @note BLE may not be enabled while Auto-ACKing is enabled. + */ +void RAIL_BLE_Init(RAIL_Handle_t railHandle); + +/** + * Take RAIL out of BLE mode. + * + * @param[in] railHandle A handle for RAIL instance. + * This function will undo some of the configuration that happens when you call + * RAIL_BLE_Init(). After this you can safely run your normal radio + * initialization code to use a non-BLE configuration. This function does \b + * not change back your radio or channel configurations so you must do this by + * manually reinitializing. This also resets the protocol output on PTI to \ref + * RAIL_PTI_PROTOCOL_CUSTOM. + */ +void RAIL_BLE_Deinit(RAIL_Handle_t railHandle); + +/** + * Determine whether BLE mode is enabled or not. + * + * @param[in] railHandle A handle for RAIL instance. + * @return True if BLE mode is enabled and false otherwise. + * This function returns the current status of RAIL's BLE mode. It is enabled by + * a call to RAIL_BLE_Init() and disabled by a call to RAIL_BLE_Deinit(). + */ +bool RAIL_BLE_IsEnabled(RAIL_Handle_t railHandle); + +/** + * Switch to the 1 Mbps Quuppa PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return Status code indicating success of the function call. + * + * You can use this function to switch to the Quuppa PHY. + * + * @note Not all chips support the 1Mbps Quuppa PHY. This API should return RAIL_STATUS_INVALID_CALL if + * unsupported by the hardware we're building for. + */ +RAIL_Status_t RAIL_BLE_ConfigPhyQuuppa(RAIL_Handle_t railHandle); + +/** + * Switch to the Viterbi 1 Mbps BLE PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to the default BLE 1 Mbps PHY if you + * have switched to the 2 Mbps or another configuration. You may only call this + * function after initializing BLE and while the radio is idle. + * + * @note The EFR32XG1 family does not support BLE Viterbi PHYs. However, calls + * to this function from that family will be silently redirected to the legacy + * \ref RAIL_BLE_ConfigPhy1Mbps(). + */ +RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Switch to the legacy non-Viterbi 1 Mbps BLE PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to the legacy BLE 1 Mbps PHY if you + * have switched to the 2 Mbps or another configuration. You may only call this + * function after initializing BLE and while the radio is idle. + * + * @note The EFR32XG2x family does not support BLE non-Viterbi PHYs. + */ +RAIL_Status_t RAIL_BLE_ConfigPhy1Mbps(RAIL_Handle_t railHandle); + +/** + * Switch to the Viterbi 2 Mbps BLE PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to the BLE 2 Mbps PHY from the + * default 1 Mbps option. You may only call this function after initializing BLE + * and while the radio is idle. + * + * @note The EFR32XG1 family does not support BLE Viterbi PHYs. + */ +RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsViterbi(RAIL_Handle_t railHandle); + +/** + * Switch to the legacy non-Viterbi 2 Mbps BLE PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to legacy BLE 2Mbps PHY from the + * default 1 Mbps option. You may only call this function after initializing BLE + * and while the radio is idle. + * + * @note The EFR32XG1 and EFR32XG2x families do not support BLE non-Viterbi + * 2 Mbps PHY. + */ +RAIL_Status_t RAIL_BLE_ConfigPhy2Mbps(RAIL_Handle_t railHandle); + +/** + * Switch to the BLE Coded PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @param[in] bleCoding The RAIL_BLE_Coding_t to use + * @return A status code indicating success of the function call. + * + * Use this function to switch back to BLE Coded PHY from the default + * 1 Mbps option. You may only call this function after initializing BLE and + * while the radio is idle. When using a BLE Coded PHY, the \ref + * RAIL_RxPacketDetails_t::subPhyId marks the coding of the received packet. + * A subPhyId of 0 marks a 500 kbps packet, and a subPhyId of 1 marks a 125 + * kbps packet. + * + * @note The EFR32XG1, EFR32XG12, and EFR32XG14 families do not support BLE + * Coded PHYs. + */ +RAIL_Status_t RAIL_BLE_ConfigPhyCoded(RAIL_Handle_t railHandle, + RAIL_BLE_Coding_t bleCoding); + +/** + * Switch to the Simulscan PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch to the BLE Simulscan PHY. You may only + * call this function after initializing BLE and while the radio is idle. + * When using Simulscan PHY, the \ref RAIL_RxPacketDetails_t::subPhyId + * marks the coding of the received packet. A subPhyId of 0 marks a + * 500 kbps packet, a subPhyId of 1 marks a 125 kbps packet, and a + * subPhyId of 2 marks a 1 Mbps packet. + * + * @note: The Simulscan PHY is supported only on some 2.4 GHz Series-2 parts. + * The preprocessor symbol \ref RAIL_BLE_SUPPORTS_SIMULSCAN_PHY and the + * runtime function \ref RAIL_BLE_SupportsSimulscanPhy() may be used to + * test for support of the Simulscan PHY. + */ +RAIL_Status_t RAIL_BLE_ConfigPhySimulscan(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Switch to the 1 Mbps BLE PHY for HADM. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to the BLE 1 Mbps HADM PHY from + * another configuration. You may only call this + * function after initializing BLE and while the radio is idle. + * + * @note This PHY is only supported when \ref RAIL_BLE_SUPPORTS_HADM is not 0. + */ +RAIL_Status_t RAIL_BLE_ConfigPhy1MbpsHadm(RAIL_Handle_t railHandle); + +/** + * Switch to the 2 Mbps BLE PHY for HADM. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch back to the BLE 2 Mbps HADM PHY from + * another configuration. You may only call this + * function after initializing BLE and while the radio is idle. + * + * @note This PHY is only supported when \ref RAIL_BLE_SUPPORTS_HADM is not 0. + */ +RAIL_Status_t RAIL_BLE_ConfigPhy2MbpsHadm(RAIL_Handle_t railHandle); +#endif + +/** + * Change BLE radio parameters. + * + * @param[in] railHandle A handle for RAIL instance. + * @param[in] crcInit The value to use for CRC initialization. + * @param[in] accessAddress The access address to use for the connection. The + * bits of this parameter are transmitted or received LSB first. + * @param[in] channel The logical channel that you're changing to, which + * initializes the whitener if used. + * @param[in] disableWhitening This can turn off the whitening engine and is useful + * for sending BLE test mode packets that don't have this turned on. + * @return A status code indicating success of the function call. + * + * This function can be used to switch radio parameters on every connection + * and/or channel change. It is BLE-aware and will set the access address, + * preamble, CRC initialization value, and whitening configuration without + * requiring you to load a new radio configuration. This function should not be + * called while the radio is active. + */ +RAIL_Status_t RAIL_BLE_ConfigChannelRadioParams(RAIL_Handle_t railHandle, + uint32_t crcInit, + uint32_t accessAddress, + uint16_t channel, + bool disableWhitening); + +/** + * Change the current BLE PHY and go into receive. + * + * @param[in] railHandle A handle for RAIL instance. + * @param[in] phy Indicates which PHY to receive on + * @param[in] railChannel Which channel of the given PHY to receive on + * @param[in] startRxTime When to enter RX + * @param[in] crcInit The value to use for CRC initialization. + * @param[in] accessAddress The access address to use for the connection. The + * bits of this parameter are transmitted or received LSB first. + * @param[in] logicalChannel The logical channel that you're changing to, which + * initializes the whitener if used. + * @param[in] disableWhitening This can turn off the whitening engine and is useful + * for sending BLE test mode packets that don't have this turned on. + * @return A status code indicating success of the function call. + * + * This function is used to implement auxiliary packet reception, as defined in + * the BLE specification. The radio will be put into IDLE, the PHY and channel + * will be changed, and then receive will be entered at the start time given. + * The new receive will have a timeout of 30 us, which means that this function + * should only be called if the offset unit is 30 us. + * + * This function is extremely time-sensitive, and may only be called within the + * interrupt context of a \ref RAIL_EVENT_RX_PACKET_RECEIVED event. + */ +RAIL_Status_t RAIL_BLE_PhySwitchToRx(RAIL_Handle_t railHandle, + RAIL_BLE_Phy_t phy, + uint16_t railChannel, + uint32_t startRxTime, + uint32_t crcInit, + uint32_t accessAddress, + uint16_t logicalChannel, + bool disableWhitening); + +/** + * Configure and enable signal identifier for BLE signal detection. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] signalIdentifierMode Mode of signal identifier operation. + * + * This features allows detection of BLE signal on air based on the mode. + * This function must be called once before \ref RAIL_BLE_EnableSignalDetection + * to configure and enable signal identifier. + * + * To enable event for signal detection \ref RAIL_ConfigEvents() must be called + * for enabling \ref RAIL_EVENT_SIGNAL_DETECTED. + * + * This function is only supported by chips where + * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and + * \ref RAIL_BLE_SupportsSignalIdentifier() are true. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_BLE_ConfigSignalIdentifier(RAIL_Handle_t railHandle, + RAIL_BLE_SignalIdentifierMode_t signalIdentifierMode); + +/** + * Enable or disable signal identifier interrupt for BLE signal detection. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Signal detection is enabled if true, disabled if false. + * + * \ref RAIL_BLE_ConfigSignalIdentifier must be called once before calling this + * function to configure and enable signal identifier. + * Once a signal is detected signal detection will be turned off and this + * function should be called to re-enable the signal detection without needing + * to call \ref RAIL_BLE_ConfigSignalIdentifier if the signal identifier + * is already configured and enabled. + * + * This function is only supported by chips where + * \ref RAIL_BLE_SUPPORTS_SIGNAL_IDENTIFIER and + * \ref RAIL_BLE_SupportsSignalIdentifier() are true. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_BLE_EnableSignalDetection(RAIL_Handle_t railHandle, + bool enable); + +/** + * @brief Backward compatible name for the \ref + * RAIL_BLE_EnableSignalDetection API. + */ +#define RAIL_BLE_EnableSignalIdentifier RAIL_BLE_EnableSignalDetection + +/****************************************************************************** + * Angle of Arrival/Departure (AoX) + *****************************************************************************/ +/** + * @addtogroup AoX Angle of Arrival/Departure + * @{ + * @brief These APIs are to a stack implementing BLE's angle of arrival and + * angle of departure functionality. + * + * They are designed for use by the Silicon Labs BLE stack only at this time and + * may cause problems if accessed directly. + */ + +/** + * + * The maximum number of GPIO pins used for AoX Antenna switching. + * + * If the user configures more pins using + * \ref RAIL_BLE_ConfigAoxAntenna than allowed + * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then + * \ref RAIL_STATUS_INVALID_PARAMETER status will be returned. + * + * \ref RAIL_STATUS_INVALID_CALL is returned if : + * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is set to 0 or + * The user configures no pins. + * + * The maximum value \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT can take depends on + * number of Antenna route pins , a chip provides. + * For EFR32XG22, the maximum value of \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT is 6. + * If the user configures fewer pins than \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, + * then only number of pins asked by user will be configured with + * \ref RAIL_STATUS_NO_ERROR. + * + */ +#define RAIL_BLE_AOX_ANTENNA_PIN_COUNT (6U) + +/** + * @enum RAIL_BLE_AoxOptions_t + * @brief Angle of Arrival/Departure options bit fields + */ +RAIL_ENUM_GENERIC(RAIL_BLE_AoxOptions_t, uint16_t) { + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE bit */ + RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT = 0, + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONNLESS bit */ + RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT = 1, + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_CONN bit */ + RAIL_BLE_AOX_OPTIONS_CONN_SHIFT = 2, + /** Shift position of \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK bit */ + RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT = 3, +}; + +/** + * @deprecated Obsolete AOX option + */ +#define RAIL_BLE_AOX_OPTIONS_DO_SWITCH (0U) +/** + * @deprecated Obsolete AOX option + */ +#define RAIL_BLE_AOX_OPTIONS_TX_ENABLED (0U) +/** + * @deprecated Obsolete AOX option + */ +#define RAIL_BLE_AOX_OPTIONS_RX_ENABLED (0U) +/** + * @deprecated Please use \ref RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT instead. + */ +#define RAIL_BLE_AOX_OPTIONS_LOCK_CTE_BUFFER_SHIFT RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT + +/** + * Disable the AoX feature. + */ +#define RAIL_BLE_AOX_OPTIONS_DISABLED (0U) +/** + * Sets one of the two AoX sampling/switching modes: 1 us or 2 us window. + */ +#define RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE (1U << RAIL_BLE_AOX_OPTIONS_SAMPLE_MODE_SHIFT) +/** + * Enables connectionless AoX Rx packets. + */ +#define RAIL_BLE_AOX_OPTIONS_CONNLESS (1U << RAIL_BLE_AOX_OPTIONS_CONNLESS_SHIFT) +/** + * Enables connection based AoX Rx packets. + */ +#define RAIL_BLE_AOX_OPTIONS_CONN (1U << RAIL_BLE_AOX_OPTIONS_CONN_SHIFT) +/** + * Disables CTE buffer lock. + */ +#define RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK (1U << RAIL_BLE_AOX_OPTIONS_DISABLE_BUFFER_LOCK_SHIFT) +/** + * Enables connection based or connectionless AoX Rx packets. + */ +#define RAIL_BLE_AOX_OPTIONS_ENABLED (RAIL_BLE_AOX_OPTIONS_CONN | RAIL_BLE_AOX_OPTIONS_CONNLESS) + +/** + * @struct RAIL_BLE_AoxConfig_t + * @brief Contains arguments for \ref RAIL_BLE_ConfigAox function. + */ +typedef struct RAIL_BLE_AoxConfig { + /** + * See RAIL_BLE_AOX_OPTIONS_* for bitfield defines for different AoX features. + */ + RAIL_BLE_AoxOptions_t aoxOptions; + /** + * Size of the raw AoX CTE (continuous tone extension) data capture buffer in + * bytes. Note this value should be a multiple of 4 as each IQ sample + * requires 4 bytes. + */ + uint16_t cteBuffSize; + /** + * Address to where the received CTE is written. Buffer must be 32-bit + * aligned. + */ + uint32_t * cteBuffAddr; + /** + * Address to first element of antenna pattern array. Array must be in RAM. + * Each element of the array contains an antenna number. The switching pattern + * is defined by the order of antennas in this array. + */ + uint8_t * antArrayAddr; + /** + * Size of the antenna pattern array. + */ + uint8_t antArraySize; +} RAIL_BLE_AoxConfig_t; + +/** + * @struct RAIL_BLE_AoxAntennaPortPins_t + * @brief Contains elements of \ref RAIL_BLE_AoxAntennaConfig_t struct. + */ +typedef struct RAIL_BLE_AoxAntennaPortPins { + /** + * The port which is used for AoX antenna switching + */ + uint8_t antPort; + /** + * The pin which is used for AoX antenna switching + */ + uint8_t antPin; +} RAIL_BLE_AoxAntennaPortPins_t; + +/** + * @struct RAIL_BLE_AoxAntennaConfig_t + * @brief Contains arguments for \ref RAIL_BLE_ConfigAoxAntenna function for + * EFR32XG22. + */ +typedef struct RAIL_BLE_AoxAntennaConfig { + /** + * A pointer to an array containing struct of port and pin used for + * AoX antenna switching + */ + RAIL_BLE_AoxAntennaPortPins_t *antPortPin; + /** + * Number of antenna pins to be configured. + */ + uint8_t antCount; +} RAIL_BLE_AoxAntennaConfig_t; + +/** + * Lock/unlock the CTE buffer from the application's perspective. The radio + * will write to the buffer only if the bit is NOT set at the beginning of the + * sampling period. The radio will set the bit once the sampling period starts + * to indicate that some CTE data has been collected, which will not be + * overwritten during the next sampling period, unless the buffer is unlocked by + * the application. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] lock Lock the CTE buffer if true and unlock it if false. + * @return True if the CTE buffer is locked after the call, otherwise false. + */ +bool RAIL_BLE_LockCteBuffer(RAIL_Handle_t railHandle, bool lock); + +/** + * Determine whether the CTE buffer is currently locked or not. + * + * @param[in] railHandle A handle for RAIL instance. + * @return True if CTE buffer is locked and false otherwise. + */ +bool RAIL_BLE_CteBufferIsLocked(RAIL_Handle_t railHandle); + +/** + * Get the offset into CTE sample of CTE data. + * + * @param[in] railHandle A handle for RAIL instance. + * @return The offset of CTE data in a CTE sample in bytes. + * On unsupported platforms this returns 0. + */ +uint8_t RAIL_BLE_GetCteSampleOffset(RAIL_Handle_t railHandle); + +/** + * Get the effective sample rate used by the ADC to capture the CTE samples. + * + * @param[in] railHandle A handle for RAIL instance. + * @return The actual sample rate used to capture the CTE in samples per second. + * On unsupported platforms this returns 0. + */ +uint32_t RAIL_BLE_GetCteSampleRate(RAIL_Handle_t railHandle); + +/** + * Configure Angle of Arrival/Departure (AoX) functionality. AoX is a method + * of radio localization which infers angle of arrival/departure of the signal + * based on different phases of the raw I/Q signal from different antennas by + * controlling external RF switch during the continuous tone extension (CTE). + * Connection based AoX packets are different than normal BLE packets in that + * they have 3 header bytes instead of 2 and they have CTE appended after the + * payload's CRC. 3rd byte or CTE info contains CTE length. Connectionless AoX + * packets have 2 header bytes and CTE info is part of the payload. AoX is + * supported on EFR32XG12/13/14 only on legacy 1Mbps BLE PHY. + * Note that calling \ref RAIL_GetRadioEntropy during AoX reception may break + * receiving packets. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] aoxConfig Configuration options for AoX + * @return RAIL_Status_t indicating success or failure of the call. + */ +RAIL_Status_t RAIL_BLE_ConfigAox(RAIL_Handle_t railHandle, + const RAIL_BLE_AoxConfig_t *aoxConfig); +/** + * Perform one time initialization of AoX registers. + * This function must be called before \ref RAIL_BLE_ConfigAox + * and before configuring the BLE PHY. + * + * @param[in] railHandle A RAIL instance handle. + * @return RAIL_Status_t indicating success or failure of the call. + */ +RAIL_Status_t RAIL_BLE_InitCte(RAIL_Handle_t railHandle); + +/** + * Perform initialization of AoX antenna GPIO pins. + * This function must be called before calls to \ref RAIL_BLE_InitCte + * and \ref RAIL_BLE_ConfigAox, and before configuring the BLE PHY, + * else a \ref RAIL_STATUS_INVALID_CALL is returned. + * + * If user configures more pins, i.e., antCount in + * \ref RAIL_BLE_AoxAntennaConfig_t, than allowed + * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the API returns + * \ref RAIL_STATUS_INVALID_PARAMETER. + * + * If user configures lesser than or equal to number of pins allowed by + * \ref RAIL_BLE_AOX_ANTENNA_PIN_COUNT, then the requested number of pins + * are configured and \ref RAIL_STATUS_NO_ERROR is returned. + * + * If AoX antenna switching is inactive, non-AoX transmits and receives + * will occur on the first antenna specified by the antenna pattern or + * on the default antenna if no antenna pattern is provided. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] antennaConfig structure to hold the set of ports and pins to + * configure Antenna pins for AoX Antenna switching. + * @return RAIL_Status_t indicating success or failure of the call. + */ +RAIL_Status_t RAIL_BLE_ConfigAoxAntenna(RAIL_Handle_t railHandle, + RAIL_BLE_AoxAntennaConfig_t *antennaConfig); + +/** @} */ // end of group AoX + + #ifndef DOXYGEN_SHOULD_SKIP_THIS +/****************************************************************************** + * High Accuracy Distance Measurement (HADM) + *****************************************************************************/ +/** + * @addtogroup HADM High Accuracy Distance Measurement + * @{ + * @brief These APIs are to a stack implementing BLE's high accuracy distance + * measurement functionality. + * + * They are designed for use by the Silicon Labs BLE stack only at this time and + * may cause problems if accessed directly. + */ + +/** + * @enum RAIL_BLE_HadmRole_t + * @brief The device role during HADM events. + */ +RAIL_ENUM(RAIL_BLE_HadmRole_t) { + /** Device cannot perform HADM events. */ + RAIL_BLE_HADM_ROLE_UNASSIGNED = 0, + /** Device is an initiator during HADM events */ + RAIL_BLE_HADM_ROLE_INITIATOR = 1, + /** Device is a reflector during HADM events */ + RAIL_BLE_HADM_ROLE_REFLECTOR = 2, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_BLE_HADM_ROLE_UNASSIGNED ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_UNASSIGNED) +#define RAIL_BLE_HADM_ROLE_INITIATOR ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_INITIATOR) +#define RAIL_BLE_HADM_ROLE_REFLECTOR ((RAIL_BLE_HadmRole_t) RAIL_BLE_HADM_ROLE_REFLECTOR) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_BLE_HadmResults_t + * @brief Contains measurement results from HADM step + */ +typedef struct { + uint32_t result[7]; /**< HADM measurement data for a particular step. */ +} RAIL_BLE_HadmResults_t; + +/** + * @enum RAIL_BLE_HadmRttType_t + * @brief HADM RTT Types. + */ +RAIL_ENUM(RAIL_BLE_HadmRttType_t) { + /** Coarse cost function engine method RTT. */ + RAIL_BLE_HADM_RTT_AA_ONLY = 0U, + /** 32 bit sounding sequence method RTT. */ + RAIL_BLE_HADM_RTT_32B_SS = 1U, + /** 96 bit sounding sequence method RTT. */ + RAIL_BLE_HADM_RTT_96B_SS = 2U, +}; + +/** + * The minimum size in 32 bit words for the IQ buffer. This value guarantees + * all IQ samples for a single 1mbps HADM step can be stored. + */ +#define RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE 600 + +/** + * @struct RAIL_BLE_HadmConfig_t + * @brief Contains arguments for \ref RAIL_BLE_ConfigHadm function. + */ +typedef struct RAIL_BLE_HadmConfig { + RAIL_BLE_HadmRole_t role; /**< The device role during HADM event. */ + uint16_t hadmSqteSteps; /**< Number of steps in HADM event. */ + /** Pointer to HADM measurements. Set to NULL if unused. */ + RAIL_BLE_HadmResults_t *pHadmDataOutput; + uint16_t t_fcs; /**< Frequency change spacing (in us). */ + uint16_t t_ip1; /**< Interlude period for mode 0 & 1 steps (in us). */ + uint16_t t_ip2; /**< Interlude period for mode 2 steps (in us). */ + uint16_t t_pm; /**< Phase measurement time (in us). */ + /** + * Pointer to buffer where IQ data will be written. Buffer must be 32-bit + * aligned. + */ + uint32_t *pIqBuffer; + /** + * Size of IQ buffer in 32 bit words. Must be at least \ref + * RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE or else an error will be + * returned by \ref RAIL_BLE_ConfigHadm. + */ + uint16_t iqBufferSize; + /** + * Step Index to perform the event calibration. This index must correspond + * to a mode 0 step or else the event calibration won't occur. + */ + uint8_t eventCalStepIndex; + RAIL_BLE_HadmRttType_t rttType; /**< RTT type returned during mode 1 step. */ + /** + * A pointer to the selected HADM event gain index. This field will be + * populated after \ref eventCalStepIndex has been reached. + */ + uint8_t *pEventGainIndex; + /** + * A pointer to the selected HADM event Fractional Frequency Offset + * (FFO) * 100. This field will be populated after \ref eventCalStepIndex + * has been reached. + */ + int16_t *pEventFfo; + bool disableRttGdComp; /**< Debug flag to disable RTT GD compensation. */ + bool disablePbrDcComp; /**< Debug flag to disable PBR DC compensation. */ + bool disablePbrGdComp; /**< Debug flag to disable PBR GD compensation. */ + bool forceAgcGain; /**< Debug flag to force event gain for calibration. */ + uint32_t forcedAgcStatus0; /**< Equivalent AGC status0 register to force. */ +} RAIL_BLE_HadmConfig_t; + +/** The maximum number of HADM steps allowed during a HADM event */ +#define RAIL_BLE_HADM_MAX_SQTE_STEPS 512 + +/** + * @enum RAIL_BLE_HadmStepState_t + * @brief The current HADM step state. + */ +RAIL_ENUM(RAIL_BLE_HadmStepState_t) { + /** HADM step state idle */ + RAIL_BLE_HADM_STATE_IDLE = 0, + /** HADM step state initiator initiator transmit mode 0 */ + RAIL_BLE_HADM_STATE_I_TX_MODE0 = 1, + /** HADM step state initiator reflector transmit mode 0 */ + RAIL_BLE_HADM_STATE_R_TX_MODE0 = 2, + /** HADM step state initiator initiator transmit mode 1 */ + RAIL_BLE_HADM_STATE_I_TX_MODE1 = 3, + /** HADM step state initiator reflector transmit mode 1 */ + RAIL_BLE_HADM_STATE_R_TX_MODE1 = 4, + /** HADM step state initiator initiator transmit mode 2 */ + RAIL_BLE_HADM_STATE_R_TX_MODE2 = 6, + /** HADM step state initiator reflector transmit mode 2 */ + RAIL_BLE_HADM_STATE_I_TX_MODE2 = 7, +}; + +/** + * First step state for HADM mode 0. + */ +#define RAIL_BLE_HADM_STEP_MODE0 RAIL_BLE_HADM_STATE_I_TX_MODE0 + +/** + * First step state for HADM mode 1. + */ +#define RAIL_BLE_HADM_STEP_MODE1 RAIL_BLE_HADM_STATE_I_TX_MODE1 + +/** + * First step state for HADM mode 2. + */ +#define RAIL_BLE_HADM_STEP_MODE2 RAIL_BLE_HADM_STATE_I_TX_MODE2 + +/** + * @enum RAIL_BLE_HadmStepMode_t + * @brief The HADM step mode. + */ +RAIL_ENUM(RAIL_BLE_HadmStepMode_t) { + RAIL_BLE_HADM_MODE_0, /**< HADM step mode 0. */ + RAIL_BLE_HADM_MODE_1, /**< HADM step mode 1. */ + RAIL_BLE_HADM_MODE_2, /**< HADM step mode 2. */ + RAIL_BLE_HADM_MODE_3, /**< HADM step mode 3. */ +}; + +/** + * @enum RAIL_BLE_HadmAntennaId_t + * @brief The HADM antenna ID. + */ +RAIL_ENUM(RAIL_BLE_HadmAntennaId_t) { + RAIL_BLE_HADM_ANTENNA_1 = 0, /**< HADM antenna ID 1. */ + RAIL_BLE_HADM_ANTENNA_2, /**< HADM antenna ID 2. */ + RAIL_BLE_HADM_ANTENNA_3, /**< HADM antenna ID 3. */ + RAIL_BLE_HADM_ANTENNA_4, /**< HADM antenna ID 4. */ +}; + +/** + * @enum RAIL_BLE_HadmRttPacketQuality_t + * @brief HADM RTT packet quality. + */ +RAIL_ENUM(RAIL_BLE_HadmRttPacketQuality_t) { + /** Access address check succeeded. */ + RAIL_BLE_HADM_RTT_AA_SUCCESS = 0U, + /** Access address had one or more bit errors. */ + RAIL_BLE_HADM_RTT_AA_BIT_ERRORS = 1U, + /** Access address not found. */ + RAIL_BLE_HADM_RTT_AA_NOT_FOUND = 2U, +}; + +/** + * @struct RAIL_BLE_HadmMode0Results_t + * @brief Contains HADM mode 0 step measurement results. + */ +typedef struct RAIL_BLE_HadmMode0Results { + /** Mode of HADM step. */ + uint8_t mode; + /** Antenna ID. */ + RAIL_BLE_HadmAntennaId_t antenna; + /** RSSI during step in integer dBm. */ + int8_t rssi; + /** Packet quality */ + uint8_t packetQuality; + /** Reserved */ + uint16_t reserved; + /** Fractional Frequency Offset (FFO) * 100 */ + int16_t hadmFfo; + /** The gain setting. */ + uint32_t stepGainSetting; + /** Reserved */ + uint32_t reserved1; +} RAIL_BLE_HadmMode0Results_t; + +/** + * A sentinel value to indicate an invalid rtt time value in + * \ref RAIL_BLE_HadmMode1Results_t::rttHalfNs + */ +#define RAIL_BLE_HADM_INVALID_RTT_VALUE ((int16_t)0x8000) + +/** + * @struct RAIL_BLE_HadmMode1Results_t + * @brief Contains HADM mode 1 step measurement results. + */ +typedef struct RAIL_BLE_HadmMode1Results { + /** Mode of HADM step. */ + uint8_t mode; + /** Antenna ID. */ + RAIL_BLE_HadmAntennaId_t antenna; + /** RSSI during step in integer dBm. */ + int8_t rssi; + /** Packet quality */ + uint8_t packetQuality; + /** + * For the initiator, this is the time (in 0.5 ns units) between time of + * departure and time of arrival excluding known offsets such as interlude + * period and packet length. + * For the reflector, this is the time (in 0.5 ns units) between time of + * arrival and time of departure excluding known offsets such as interlude + * period and packet length. + */ + int16_t rttHalfNs; + /** Flag used to indicate whether we have missed FCAL during calibration */ + uint8_t missedFcal; + /** Reserved */ + uint8_t reserved1; + /** Reserved */ + uint32_t reserved2[2]; +} RAIL_BLE_HadmMode1Results_t; + +/** + * @enum RAIL_BLE_HadmToneQuality_t + * @brief HADM tone quality. + */ +RAIL_ENUM(RAIL_BLE_HadmToneQuality_t) { + /** Good quality HADM mode 2 tone. */ + RAIL_BLE_HADM_TONE_QUALITY_GOOD = 0U, + /** Medium quality HADM mode 2 tone. */ + RAIL_BLE_HADM_TONE_QUALITY_MEDIUM = 1U, + /** Low quality HADM mode 2 tone. */ + RAIL_BLE_HADM_TONE_QUALITY_LOW = 2U, + /** HADM mode 2 tone quality indication unavailable. */ + RAIL_BLE_HADM_TONE_QUALITY_UNAVAILABLE = 3U, +}; + +/** + * @struct RAIL_BLE_HadmMode2Results_t + * @brief Contains HADM mode 2 step measurement results. + */ +typedef struct RAIL_BLE_HadmMode2Results { + /** Mode of HADM step. */ + uint8_t mode; + /** Antenna ID. */ + RAIL_BLE_HadmAntennaId_t antenna; + /** Flag used to indicate whether we have missed FCAL during calibration */ + uint8_t missedFcal; + /** Reserved */ + uint8_t reserved1; + /** PCT i value */ + int16_t pctI; + /** PCT q value */ + int16_t pctQ; + /** Tone extension PCT i value */ + int16_t pctToneExtI; + /** Tone extension PCT q value */ + int16_t pctToneExtQ; + /** Tone quality indicator */ + RAIL_BLE_HadmToneQuality_t tqi; + /** Tone quality indicator for tone extension */ + RAIL_BLE_HadmToneQuality_t tqiToneExt; + /** Reserved */ + uint16_t reserved2; +} RAIL_BLE_HadmMode2Results_t; + +/** + * @struct RAIL_BLE_HadmStepResults_t + * @brief Generic HADM step mode result structure. Based on the value of the + * mode field, this structure can be type cast to the appropriate mode + * specific structure \ref RAIL_BLE_HadmMode0Results_t, + * \ref RAIL_BLE_HadmMode1Results_t, or RAIL_BLE_HadmMode2Results_t. + */ +typedef struct RAIL_BLE_HadmStepResults { + /** Mode of HADM step. */ + uint8_t mode; + /** Reserved */ + uint8_t reserved0; + /** Reserved */ + uint16_t reserved1; + /** Reserved */ + uint32_t reserved2[3]; +} RAIL_BLE_HadmStepResults_t; + +/** + * @struct RAIL_BLE_HadmMode0DebugResults_t + * @brief Contains HADM mode 0 step measurement debug results. + */ +typedef struct RAIL_BLE_HadmMode0DebugResults { + /** Highest recorded RSSI up to and including the current mode 0 step. */ + int16_t highestRssi; + /** + * FFO of the Mode 0 step with the highest recorded RSSI + * up to and including the current Mode 0 step. + */ + int16_t hadmFfo; + /** + * AGC gain value of the Mode 0 step with the highest recorded + * RSSI up to and including the current Mode 0 step. + */ + uint32_t agcStatus0; + /** + * For devices configured as an initiator, the measured frequency offset + * in Hz between the two devices during a HADM mode 0 step. For devices + * configured as a reflector, this value will always be 0. + */ + int32_t freqOffHz; + /** + * Estimated coarse frequency offset in internal units. + */ + int32_t hwFreqOffEst; + /** Reserved */ + uint32_t reserved[3]; +} RAIL_BLE_HadmMode0DebugResults_t; + +/** + * @struct RAIL_BLE_HadmMode1DebugResults_t + * @brief Contains HADM mode 1 step measurement debug results. + */ +typedef struct RAIL_BLE_HadmMode1DebugResults { + uint16_t toxClks; + int16_t fracRttHalfNs; + uint32_t coarseRttHalfNs; + int32_t gdCompRttHalfNs; + int32_t toxWithOffsetsRttHalfNs; + uint32_t hadmstatus3; + uint32_t hadmstatus4; + uint32_t hadmstatus5; +} RAIL_BLE_HadmMode1DebugResults_t; + +/** + * @struct RAIL_BLE_HadmMode2DebugResults_t + * @brief Contains HADM mode 2 step measurement debug results. + */ +typedef struct RAIL_BLE_HadmMode2DebugResults { + /** DCCOMP i value */ + int16_t dcCompI; + /** DCCOMP q value */ + int16_t dcCompQ; + /** GDCOMP i value */ + int16_t gdCompI; + /** GDCOMP q value */ + int16_t gdCompQ; + /** Raw tone quality value */ + uint16_t tqiRaw; + /** Raw tone quality tone extension value */ + uint16_t tqiToneExtRaw; + /** FCAL value from SYNTH_VCOTUNING */ + uint16_t fcal; + /** Reserved */ + uint16_t reserved; + /** Reserved */ + uint32_t reserved1[3]; +} RAIL_BLE_HadmMode2DebugResults_t; + +/** + * @struct RAIL_BLE_HadmStepDebugResults_t + * @brief Generic HADM step mode debug result structure. Based on the value of + * the mode field, this structure can be type cast to the appropriate mode + * specific structure \ref RAIL_BLE_HadmMode0DebugResults_t, + * \ref RAIL_BLE_HadmMode1DebugResults_t, or RAIL_BLE_HadmMode2DebugResults_t. + */ +typedef struct RAIL_BLE_HadmStepDebugResults { + uint32_t reserved; + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; + uint32_t reserved4; + uint32_t reserved5; + uint32_t reserved6; +} RAIL_BLE_HadmStepDebugResults_t; + +/** + * @struct RAIL_BLE_HadmStepConfig_t + * @brief Contains arguments for \ref RAIL_BLE_SetNextHadmStep. + */ +typedef struct RAIL_BLE_HadmStepConfig { + /** Sets the HADM step state. */ + RAIL_BLE_HadmStepState_t stepState; + /** Indicates whether this is final step in HADM event. */ + bool lastStep; + /** + * Transmit tone during tone extension slot in mode 2 packet. + * This field is ignored during RX and for all non mode 2 packets. + */ + bool transmitToneExtension; + /** Sets the HADM step logical channel. */ + uint16_t channel; + /** + * Length of packet payload in bytes. Should not include trailer, guard, + * or UC bits. Only used for mode 1 steps, ignored otherwise. + */ + uint16_t packetLength; + /** The initiator (first) access address during step. */ + uint32_t initAccessAddress; + /** The reflector (second) access address during step. */ + uint32_t reflAccessAddress; + /** Pointer to TX data to be transmitted. Ignored for mode 0 and 2 steps. */ + uint8_t *pTxData; + /** RTT marker bit position. Ignored for mode 0 and 2 steps. */ + uint8_t rttMarkerBitPosition[2]; + /** + * A pointer to an array of HADM step results. These results will be + * populated after the completion of the HADM step. This array can be cast to + * \ref RAIL_BLE_HadmMode0Results_t, \ref RAIL_BLE_HadmMode1Results_t, or + * \ref RAIL_BLE_HadmMode2Results_t as appropriate to read mode specific + * results. + */ + RAIL_BLE_HadmStepResults_t *pResults; + /** + * A pointer to an array of HADM step debug results. These results will be + * populated after the completion of the HADM step. This array can be cast to + * \ref RAIL_BLE_HadmMode0DebugResults_t, \ref + * RAIL_BLE_HadmMode1DebugResults_t, or \ref RAIL_BLE_HadmMode2DebugResults_t + * as appropriate to read mode specific debug results. + * + * Setting this pointer to NULL means no debug data will be collected. + */ + RAIL_BLE_HadmStepDebugResults_t *pDebugResults; + /** + * Pointer to contiguous global read-write memory that will be used + * by RAIL to store channel switching information. + * It need not be initialized and applications should never write + * data anywhere in this buffer. + * + * @note the size in words of this buffer must be at least as large as + * 3 + /ref RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL. This buffer + * is for internal use to the library. + */ + uint32_t *pBuffer; + /** + * This parameter must be set to the length of the buffer array. This way, + * during configuration, the software can confirm it's writing within the + * range of the buffer. The configuration API will return an error + * if bufferLength is insufficient. + */ + uint16_t bufferLength; + /** Reserved */ + uint16_t reserved0; + /** + * A pointer to the start of captured IQ data for this step. This pointer + * will be populated after the completion of the HADM step. + */ + uint32_t **pIqBuffer; + /** + * A pointer to captured IQ data size in 32 bit words. This pointer will be + * populated after the completion of the HADM step. + */ + uint16_t *pIqBufferSize; + /** + * A pointer to a boolean to indicate whether to preserve IQ data for this + * step. If this is the final step of the event, IQ data will automatically + * be preserved regardless of how this boolean is set. For other steps, if + * this boolean is set true, and there are at least \ref + * RAIL_BLE_HADM_1MBPS_MINIMUM_IQ_BUFFER_SIZE unused 32 bit words still + * available in the event IQ buffer, this step's IQ data will be preserved + * and not be overwritten by IQ data from a subsequent step. Otherwise, this + * step's IQ data will not be preserved and may be overwritten. This boolean + * will be updated after completion of the HADM step to indicate whether the + * IQ data from that step was actually preserved. + */ + bool *pSaveIqData; +} RAIL_BLE_HadmStepConfig_t; + +/** + * @struct RAIL_BLE_HadmAntennaConfig_t + * @brief Contains arguments for \ref RAIL_BLE_ConfigHadmAntenna function. + */ +typedef struct RAIL_BLE_HadmAntennaConfig { + int8_t antennaCount; /**< Total number of antenna elements. */ + const int16_t *pAntennaOffsetCm; /**< Pointer to antenna offsets in cm units. */ +} RAIL_BLE_HadmAntennaConfig_t; + +/** The maximum number of antennas supported. */ +#define RAIL_BLE_HADM_MAX_ANTENNAS 4 + +/** + * @struct RAIL_BLE_HadmGdCompTables_t + * @brief Contains pointers to HADM group delay compensation tables. + */ +typedef struct RAIL_BLE_HadmGdCompTables { + /** Pointer to PBR phase LSB group delay compensation table. */ + const int16_t *pPbrPhaseLsb; + /** Pointer to RTT slope group delay compensation table. */ + const int16_t *pRttSlope; + /** Pointer to RTT offset group delay compensation table. */ + const int16_t *pRttOffset; + /** Common length for each table in units of int16_t. */ + uint8_t length; +} RAIL_BLE_HadmGdCompTables_t; + +/** + * Configure High Accuracy Distance Measurement (HADM) functionality. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] hadmConfig Configuration options for HADM. + * @return RAIL_Status_t indicating success or failure of the call. + * + * @warning This API is not safe to use in a multiprotocol app. + */ +RAIL_Status_t RAIL_BLE_ConfigHadm(RAIL_Handle_t railHandle, + const RAIL_BLE_HadmConfig_t *hadmConfig); + +/** + * Enable High Accuracy Distance Measurement (HADM) functionality. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Enable or disable HADM functionality. + * @return RAIL_Status_t indicating success or failure of the call. + * + * @warning This API is not safe to use in a multiprotocol app. + */ +RAIL_Status_t RAIL_BLE_EnableHadm(RAIL_Handle_t railHandle, + bool enable); + +/** + * Set up the next HADM step. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] hadmStepConfig Configuration options for next HADM step. + * @param[in] pend If true, apply configuration at next appropriate radio + * transition (i.e. at Rx2Tx for an initiator, or Tx2Rx for a reflector). + * Otherwise, apply configuration immediately. + * @return RAIL_Status_t indicating success or failure of the call. + * + * @note When the next HADM step is to be pended, the specified step in + * hadmStepConfig must be the initial step state for a particular mode (e.g. + * \ref RAIL_BLE_HADM_STEP_MODE0, \ref RAIL_BLE_HADM_STEP_MODE1, or \ref + * RAIL_BLE_HADM_STEP_MODE2). Otherwise this API will return \ref + * RAIL_STATUS_INVALID_PARAMETER. + * + * @warning This API is not safe to use in a multiprotocol app. + */ +RAIL_Status_t RAIL_BLE_SetNextHadmStep(RAIL_Handle_t railHandle, + const RAIL_BLE_HadmStepConfig_t *hadmStepConfig, + bool pend); + +/** + * Configure antennas for HADM event. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] pAntennaConfig A pointer to the antenna config + * @return RAIL_Status_t indicating success or failure of the call. + */ +RAIL_Status_t RAIL_BLE_ConfigHadmAntenna(RAIL_Handle_t railHandle, + RAIL_BLE_HadmAntennaConfig_t *pAntennaConfig); + +/** + * Loads the HADM RTT and PBR group delay compensation tables for a + * particular PA mode. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] pTables Pointer to group delay compensation lookup tables. + * @param[in] powerMode The PA mode for which to load compensation tables. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_BLE_LoadHadmCompTables(RAIL_Handle_t railHandle, + const RAIL_BLE_HadmGdCompTables_t *pTables, + RAIL_TxPowerMode_t powerMode); + +/** + * Callback used to load HADM group delay compensation tables for all PA modes + * supported by device during \ref RAIL_BLE_EnableHadm when enable is true. + * This function is optional to implement. + * + * @return Status code indicating success of the function call. + * + * @note If this callback function is not implemented, unneeded tables may not + * be dead stripped, resulting in larger overall code size. The API \ref + * RAIL_BLE_LoadHadmCompTables should be used within this callback to load the + * appropriate tables for each supported PA mode. + */ +RAIL_Status_t RAILCb_BLE_HadmGdCompTableLoad(void); + +/** @} */ // end of group HADM +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/// @addtogroup BLETX2TX BLE TX Channel Hopping +/// @{ +/// @code{.c} +/// +/// // Configuration to send one additional packet +/// static RAIL_BLE_TxChannelHoppingConfigEntry_t entry[1]; +/// static uint32_t buffer[BUFFER_SIZE]; +/// static RAIL_BLE_TxRepeatConfig_t repeat = { +/// .iterations = 1, +/// .repeatOptions = RAIL_TX_REPEAT_OPTION_HOP, +/// .delayOrHop.channelHopping = { +/// .buffer = buffer, +/// .bufferLength = BUFFER_SIZE, +/// .numberOfChannels = 1, +/// .entries = &entry[0], +/// }, +/// }; +/// +/// // Send a normal packet on the current channel, then a packet on a new channel +/// int bleSendThenAdvertise(uint8_t *firstPacket, uint8_t *secondPacket) +/// { +/// // Load both packets into the FIFO +/// RAIL_WriteTxFifo(railHandle, firstPacket, FIRST_PACKET_LEN, true); +/// RAIL_WriteTxFifo(railHandle, secondPacket, SECOND_PACKET_LEN, false); +/// +/// // Configure a 300 us turnaround between transmits +/// entry[0].delayMode = RAIL_CHANNEL_HOPPING_DELAY_MODE_STATIC; +/// entry[0].delay = 300; // microseconds +/// +/// // Use default advertising parameters +/// entry[0].disableWhitening = false; +/// entry[0].crcInit = 0x00555555; +/// entry[0].accessAddress = 0x8E89BED6; +/// +/// // Transmit the repeated packet on the first advertising channel +/// entry[0].phy = RAIL_BLE_1Mbps; +/// entry[0].railChannel = 0; +/// entry[0].logicalChannel = 37; +/// +/// // Configure repeated transmit in RAIL, then transmit, sending both packets +/// RAIL_BLE_SetNextTxRepeat(railHandle, &repeat); +/// RAIL_StartTx(railHandle, currentChannel, RAIL_TX_OPTIONS_DEFAULT, NULL); +/// } +/// @endcode + +/** + * @struct RAIL_BLE_TxChannelHoppingConfigEntry_t + * @brief Structure that represents one of the channels that is part of a + * \ref RAIL_BLE_TxChannelHoppingConfig_t sequence of channels used in + * channel hopping. + */ +typedef struct RAIL_BLE_TxChannelHoppingConfigEntry { + /** + * Idle time in microseconds to wait before hopping into the + * channel indicated by this entry. + */ + uint32_t delay; + /** + * The BLE PHY to use for this hop's transmit. + */ + RAIL_BLE_Phy_t phy; + /** + * The logical channel to use for this hop's transmit. The whitener will + * be reinitialized if used. + */ + uint8_t logicalChannel; + /** + * The channel number to be used for this hop's transmit. If this is an + * invalid channel for the chosen PHY, the call to \ref RAIL_SetNextTxRepeat() + * will fail. + */ + uint8_t railChannel; + /** + * This can turn off the whitening engine and is useful for sending BLE test + * mode packets that don't have this turned on. + */ + bool disableWhitening; + /** + * The value to use for CRC initialization. + */ + uint32_t crcInit; + /** + * The access address to use for the connection. + */ + uint32_t accessAddress; +} RAIL_BLE_TxChannelHoppingConfigEntry_t; + +/** + * @struct RAIL_BLE_TxChannelHoppingConfig_t + * @brief Wrapper struct that will contain the sequence of + * \ref RAIL_BLE_TxChannelHoppingConfigEntry_t that represents the channel + * sequence to use during TX Channel Hopping. + */ +typedef struct RAIL_BLE_TxChannelHoppingConfig { + /** + * Pointer to contiguous global read-write memory that will be used + * by RAIL to store channel hopping information throughout its operation. + * It need not be initialized and applications should never write + * data anywhere in this buffer. + */ + uint32_t *buffer; + /** + * This parameter must be set to the length of the buffer array. This way, + * during configuration, the software can confirm it's writing within the + * range of the buffer. The configuration API will return an error + * if bufferLength is insufficient. + */ + uint16_t bufferLength; + /** The number of channels that is in the channel hopping sequence. */ + uint8_t numberOfChannels; + /** + * Pad bytes reserved for future use and currently ignored. + */ + uint8_t reserved; + /** + * A pointer to the first element of an array of \ref + * RAIL_BLE_TxChannelHoppingConfigEntry_t that represents the channels + * used during channel hopping. The length of this array must be + * numberOfChannels. + */ + RAIL_BLE_TxChannelHoppingConfigEntry_t *entries; +} RAIL_BLE_TxChannelHoppingConfig_t; + +/// @struct RAIL_BLE_TxRepeatConfig_t +/// @brief A configuration structure for repeated transmits +/// +typedef struct RAIL_BLE_TxRepeatConfig { + /** + * The number of repeated transmits to run. A total of (iterations + 1) + * transmits will go on-air in the absence of errors. + */ + uint16_t iterations; + /** + * Repeat option(s) to apply. + */ + RAIL_TxRepeatOptions_t repeatOptions; + /** + * Per-repeat delay or hopping configuration, depending on repeatOptions. + */ + union { + /** + * When \ref RAIL_TX_REPEAT_OPTION_HOP is not set, this specifies + * the delay time between each repeated transmit. Specify \ref + * RAIL_TRANSITION_TIME_KEEP to use the current \ref + * RAIL_StateTiming_t::txToTx transition time setting. + */ + RAIL_TransitionTime_t delay; + /** + * When \ref RAIL_TX_REPEAT_OPTION_HOP is set, this specifies + * the channel hopping configuration to use when hopping between + * repeated transmits. Per-hop delays are configured within each + * \ref RAIL_BLE_TxChannelHoppingConfigEntry_t::delay rather than + * this union's delay field. + */ + RAIL_BLE_TxChannelHoppingConfig_t channelHopping; + } delayOrHop; +} RAIL_BLE_TxRepeatConfig_t; + +/** + * Set up automatic repeated transmits after the next transmit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] repeatConfig The configuration structure for repeated transmits. + * @return Status code indicating a success of the function call. + * + * Repeated transmits will occur after an application-initiated transmit caused + * by calling one of the \ref Packet_TX APIs. The repetition will only occur + * after the first application-initiated transmit after this function is + * called. Future repeated transmits must be requested by calling this function + * again. + * + * Each repeated transmit that occurs will have full \ref PTI information and + * will receive events such as \ref RAIL_EVENT_TX_PACKET_SENT as normal. + * + * If a TX error occurs during the repetition, the process will abort and the + * TX error transition from \ref RAIL_SetTxTransitions will be used. If the + * repetition completes successfully, the TX success transition from + * \ref RAIL_SetTxTransitions will be used. + * + * Any call to \ref RAIL_Idle or \ref RAIL_StopTx will clear the pending + * repeated transmits. The state will also be cleared by another call to this + * function. To clear the repeated transmits before they've started without + * stopping other radio actions, call this function with a \ref + * RAIL_BLE_TxRepeatConfig_t::iterations count of 0. A DMP switch will clear this + * state only if the initial transmit triggering the repeated transmits has + * started. + * + * The application is responsible for populating the transmit data to be used + * by the repeated transmits via \ref RAIL_SetTxFifo or \ref RAIL_WriteTxFifo. + * Data will be transmitted from the TX FIFO. If the TX FIFO does not have + * sufficient data to transmit, a TX error and a \ref + * RAIL_EVENT_TX_UNDERFLOW will occur. To avoid an underflow, the + * application should queue data to be transmitted as early as possible. + * + * This function will fail to configure the repetition if a transmit of any + * kind is ongoing, including during the time between an initial transmit and + * the end of a previously-configured repetition. + * + * @note This feature/API is not supported on the EFR32XG1 family of chips. + * Use the compile time symbol \ref RAIL_SUPPORTS_TX_TO_TX or the runtime + * call \ref RAIL_SupportsTxToTx() to check whether the platform supports + * this feature. + */ +RAIL_Status_t RAIL_BLE_SetNextTxRepeat(RAIL_Handle_t railHandle, + const RAIL_BLE_TxRepeatConfig_t *repeatConfig); + +/** @} */ // end of group BLETX2TX + +/** @} */ // end of BLE + +/// @addtogroup Calibration +/// @brief Bluetooth protocol-specific APIs for calibrating the radio. +/// @{ + +/** + * Calibrate image rejection for Bluetooth Low Energy. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] imageRejection The result of the image rejection calibration. + * @return A status code indicating success of the function call. + * + * Some chips have protocol-specific image rejection calibrations programmed + * into their flash. This function will either get the value from flash and + * apply it, or run the image rejection algorithm to find the value. + */ +RAIL_Status_t RAIL_BLE_CalibrateIr(RAIL_Handle_t railHandle, + uint32_t *imageRejection); + +/// @} // End of group Calibration + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_BLE_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h index 2e26c99..364e5e6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/ieee802154/rail_ieee802154.h @@ -1,1767 +1,1767 @@ -/***************************************************************************//** - * @file - * @brief The IEEE 802.15.4 specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_IEEE802154_H__ -#define __RAIL_IEEE802154_H__ - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @addtogroup IEEE802_15_4 IEEE 802.15.4 -/// @ingroup Protocol_Specific -/// @brief IEEE 802.15.4 configuration routines -/// -/// The functions in this group configure RAIL IEEE 802.15.4 hardware -/// acceleration which includes IEEE 802.15.4 format filtering, address -/// filtering, ACKing, and filtering based on the frame type. -/// -/// To configure IEEE 802.15.4 functionality, the application must first set up -/// a RAIL instance with RAIL_Init() and other setup functions. -/// Instead of RAIL_ConfigChannels(), however, an -/// application may use RAIL_IEEE802154_Config2p4GHzRadio() to set up the -/// official IEEE 2.4 GHz 802.15.4 PHY. This configuration is shown below. -/// -/// 802.15.4 defines its macAckWaitDuration from the end of the transmitted -/// packet to complete reception of the ACK. RAIL's ackTimeout only covers -/// sync word detection of the ACK. Therefore, subtract the ACK's -/// PHY header and payload time to get RAIL's ackTimeout setting. -/// For 2.4 GHz OQPSK, macAckWaitDuration is specified as 54 symbols; -/// subtracting 2-symbol PHY header and 10-symbol payload yields a RAIL -/// ackTimeout of 42 symbols or 672 microseconds at 16 microseconds/symbol. -/// -/// @code{.c} -/// static RAIL_Handle_t railHandle = NULL; // Initialized somewhere else. -/// -/// static const RAIL_IEEE802154_Config_t rail154Config = { -/// .addresses = NULL, -/// .ackConfig = { -/// .enable = true, // Turn on auto ACK for IEEE 802.15.4. -/// .ackTimeout = 672, // See note above: 54-12 sym * 16 us/sym = 672 us. -/// .rxTransitions = { -/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing -/// .error = RAIL_RF_STATE_RX, // Ignored -/// }, -/// .txTransitions = { -/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing -/// .error = RAIL_RF_STATE_RX, // Ignored -/// }, -/// }, -/// .timings = { -/// .idleToRx = 100, -/// .idleToTx = 100, -/// .rxToTx = 192, // 12 symbols * 16 us/symbol = 192 us -/// .txToRx = 192, // 12 symbols * 16 us/symbol = 192 us -/// .rxSearchTimeout = 0, // Not used -/// .txToRxSearchTimeout = 0, // Not used -/// }, -/// .framesMask = RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES, -/// .promiscuousMode = false, // Enable format and address filtering. -/// .isPanCoordinator = false, -/// .defaultFramePendingInOutgoingAcks = false, -/// }; -/// -/// void config154(void) -/// { -/// // Configure the radio and channels for 2.4 GHz IEEE 802.15.4. -/// RAIL_IEEE802154_Config2p4GHzRadio(railHandle); -/// // Initialize the IEEE 802.15.4 configuration using the static configuration above. -/// RAIL_IEEE802154_Init(railHandle, &rail154Config); -/// } -/// @endcode -/// -/// To configure address filtering, call -/// RAIL_IEEE802154_SetAddresses() with a structure containing all addresses or -/// call the individual RAIL_IEEE802154_SetPanId(), -/// RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress() -/// APIs. RAIL supports \ref RAIL_IEEE802154_MAX_ADDRESSES number of address -/// pairs to receive packets from multiple IEEE -/// 802.15.4 networks at the same time. Broadcast addresses are supported by -/// default without any additional configuration so they do not consume one of -/// these slots. If the application does not require all address pairs, be sure -/// to set unused ones to the proper disabled value for each type. These can -/// be found in the \ref RAIL_IEEE802154_AddrConfig_t documentation. Below is -/// an example of setting filtering for one set of addresses. -/// -/// @code{.c} -/// // PanID OTA value of 0x34 0x12. -/// // Short Address OTA byte order of 0x78 0x56. -/// // Long address with OTA byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88. -/// -/// // Set up all addresses simultaneously. -/// RAIL_Status_t setup1(void) -/// { -/// RAIL_IEEE802154_AddrConfig_t nodeAddress = { -/// { 0x1234, 0xFFFF, 0xFFFF }, -/// { 0x5678, 0xFFFF, 0xFFFF }, -/// { { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }, -/// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, -/// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } -/// }; -/// return RAIL_IEEE802154_SetAddresses(railHandle, &nodeAddress); -/// } -/// -/// // Alternatively, the addresses can be set up individually as follows: -/// RAIL_Status_t setup2(void) -/// { -/// RAIL_Status_t status; -/// const uint8_t longAddress[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }; -/// -/// status = RAIL_IEEE802154_SetPanId(railHandle, 0x1234, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } -/// status = RAIL_IEEE802154_SetShortAddress(railHandle, 0x5678, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } -/// status = RAIL_IEEE802154_SetLongAddress(railHandle, longAddress, 0); -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status -/// } -/// -/// return RAIL_STATUS_NO_ERROR; -/// } -/// @endcode -/// -/// Address filtering will be enabled except when in promiscuous mode, which can -/// be set with RAIL_IEEE802154_SetPromiscuousMode(). The addresses may be -/// changed at runtime. However, if you are receiving a packet while -/// reconfiguring the address filters, you may get undesired behavior so it's -/// safest to do this while not in receive. -/// -/// Auto ACK is controlled by the ackConfig and timings fields passed to -/// RAIL_IEEE802154_Init(). After initialization, they may be controlled -/// using the normal \ref Auto_Ack and \ref State_Transitions APIs. When in IEEE -/// 802.15.4 mode, the ACK will generally have a 5 byte length, its Frame Type -/// will be ACK, its Frame Version 0 (2003), and its Frame Pending bit will be -/// false unless the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event is -/// triggered in which case it will default to the -/// \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks setting. -/// If the default Frame Pending setting is incorrect, -/// the app must call \ref RAIL_IEEE802154_ToggleFramePending -/// (formerly \ref RAIL_IEEE802154_SetFramePending) while handling the -/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. -/// -/// This event must be turned on by the user and will fire whenever a data -/// request is being received so that the stack can determine if there -/// is pending data. Note that if the default Frame Pending bit needs to -/// be changed, it must be done quickly. Otherwise, the ACK may already -/// have been transmitted with the default setting. Check the return code of -/// RAIL_IEEE802154_ToggleFramePending() to be sure that the bit was changed -/// in time. -/// -/// Transmit and receive operations are done using the standard RAIL APIs in -/// IEEE 802.15.4 mode. To send packets using the correct CSMA configuration, -/// use \ref RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA define -/// that can initialize the csmaConfig structure passed to \ref -/// RAIL_StartCcaCsmaTx(). -/// @{ - -/** - * @enum RAIL_IEEE802154_AddressLength_t - * @brief Different lengths that an 802.15.4 address can have - */ -RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) { - RAIL_IEEE802154_ShortAddress = 2, /**< 2 byte short address. */ - RAIL_IEEE802154_LongAddress = 3, /**< 8 byte extended address. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_ShortAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_ShortAddress) -#define RAIL_IEEE802154_LongAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_LongAddress) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_IEEE802154_Address_t - * @brief Representation of 802.15.4 address - * This structure is only used for received source address information - * needed to perform Frame Pending lookup. - */ -typedef struct RAIL_IEEE802154_Address{ - /** Convenient storage for different address types. */ - union { - uint16_t shortAddress; /**< Present for 2 byte addresses. */ - uint8_t longAddress[8]; /**< Present for 8 byte addresses. */ - }; - /** - * Enumeration of the received address length. - */ - RAIL_IEEE802154_AddressLength_t length; - /** - * A bitmask representing which address filter(s) this packet has passed. - * It is undefined on platforms lacking \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. - */ - RAIL_AddrFilterMask_t filterMask; -} RAIL_IEEE802154_Address_t; - -/** The maximum number of allowed addresses of each type. */ -#define RAIL_IEEE802154_MAX_ADDRESSES (3U) - -/** - * @struct RAIL_IEEE802154_AddrConfig_t - * @brief A configuration structure for IEEE 802.15.4 Address Filtering. The - * broadcast addresses are handled separately and do not need to be specified - * here. Any address to be ignored should be set with all bits high. - * - * This structure allows configuration of multi-PAN functionality by specifying - * multiple PAN IDs and short addresses. A packet will be received if it matches - * an address and its corresponding PAN ID. Long address 0 and short address 0 - * match against PAN ID 0, etc. The broadcast PAN ID and address will work with - * any address or PAN ID, respectively. - */ -typedef struct RAIL_IEEE802154_AddrConfig{ - /** - * PAN IDs for destination filtering. All must be specified. - * To disable a PAN ID, set it to the broadcast value, 0xFFFF. - */ - uint16_t panId[RAIL_IEEE802154_MAX_ADDRESSES]; - /** - * A short network addresses for destination filtering. All must be specified. - * To disable a short address, set it to the broadcast value, 0xFFFF. - */ - uint16_t shortAddr[RAIL_IEEE802154_MAX_ADDRESSES]; - /** - * A 64-bit address for destination filtering. All must be specified. - * This field is parsed in over-the-air (OTA) byte order. To disable a long - * address, set it to the reserved value of 0x00 00 00 00 00 00 00 00. - */ - uint8_t longAddr[RAIL_IEEE802154_MAX_ADDRESSES][8]; -} RAIL_IEEE802154_AddrConfig_t; - -/** - * @struct RAIL_IEEE802154_Config_t - * @brief A configuration structure for IEEE 802.15.4 in RAIL. - * - * @note 802.15.4 radio configurations with Forward Error Correction (FEC) - * enabled are incompatible with 802.15.4 filtering and AutoACK on - * EFR32xG1 platforms. - * AutoACK should be disabled and promiscuous mode enabled when using such - * a configuration. This is enforced implicitly on EFR32xG1 platforms with - * \ref RAIL_IEEE802154_SUPPORTS_G_DYNFEC true when - * \ref RAIL_IEEE802154_ConfigGOptions() is called to enable any G options. - */ -typedef struct RAIL_IEEE802154_Config { - /** - * Configure the RAIL Address Filter to allow the given destination - * addresses. If this pointer is NULL, defer destination address configuration. - * If a member of addresses is NULL, defer configuration of just that member. - * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the - * individual members can be changed via RAIL_IEEE802154_SetPanId(), - * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress(). - */ - const RAIL_IEEE802154_AddrConfig_t *addresses; - /** - * Define the ACKing configuration for the IEEE 802.15.4 implementation. - */ - RAIL_AutoAckConfig_t ackConfig; - /** - * Define state timings for the IEEE 802.15.4 implementation. - */ - RAIL_StateTiming_t timings; - /** - * Set which 802.15.4 frame types will be received, of Beacon, Data, ACK, and - * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames(). - */ - uint8_t framesMask; - /** - * Enable promiscuous mode during configuration. This can be overridden via - * RAIL_IEEE802154_SetPromiscuousMode() afterwards. - */ - bool promiscuousMode; - /** - * Set whether the device is a PAN Coordinator during configuration. This can - * be overridden via RAIL_IEEE802154_SetPanCoordinator() afterwards. - */ - bool isPanCoordinator; - /** - * The default value for the Frame Pending bit in outgoing ACKs for packets - * that triggered the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. - * Such an ACK's Frame Pending bit can be inverted if necessary during the - * handling of that event by calling \ref RAIL_IEEE802154_ToggleFramePending - * (formerly \ref RAIL_IEEE802154_SetFramePending). - */ - bool defaultFramePendingInOutgoingAcks; -} RAIL_IEEE802154_Config_t; - -/** RX channel switching buffer size, in bytes. */ -#ifdef SLI_LIBRARY_BUILD -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (704U) // largest of below -#else//!SLI_LIBRARY_BUILD -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (704U) -#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (640U) -#else// RX channel switching not supported -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (0U) -#endif -#endif//SLI_LIBRARY_BUILD - -/** Fixed-width type indicating the needed alignment for RX channel switching buffer. */ -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE uint32_t - -/** Alignment that is needed for RX channel switching buffer. */ -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT (sizeof(RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE)) - -/** Maximum numbers of channels supported for RX channel switching */ -#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_NUM_CHANNELS (2U) - -/** - * @struct RAIL_IEEE802154_RxChannelSwitchingCfg_t - * @brief A configuration structure for RX channel switching. - */ -typedef struct RAIL_IEEE802154_RxChannelSwitchingCfg { - /** - * Pointer to contiguous global read-write memory that will be used - * by RAIL to store channel specific settings for concurrent listening. - * It need not be initialized and applications should never write - * data anywhere in this buffer. - * - * @note the size of this buffer must be at least as large as the - * \ref RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES and needs to be word - * aligned. - */ - RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE *buffer; - /** - * This parameter must be set to the length of the buffer array, in bytes. - * This way, during configuration, the software can confirm it's - * writing within the range of the buffer. The configuration API will return - * an error if bufferBytes is insufficient. - */ - uint16_t bufferBytes; - /** - * Array to hold the channel numbers for RX channel switching. - * @note Radio will switch between the exact channels specified, and not - * across an inclusive range of channels between the specified channels. - */ - uint16_t channels[RAIL_IEEE802154_RX_CHANNEL_SWITCHING_NUM_CHANNELS]; -} RAIL_IEEE802154_RxChannelSwitchingCfg_t; - -/// @addtogroup IEEE802154_PHY IEEE 802.15.4 Radio Configurations -/// Radio configurations for the RAIL 802.15.4 Accelerator -/// -/// These radio configurations are used to configure 802.15.4 when a function -/// such as \ref RAIL_IEEE802154_Config2p4GHzRadio() is called. Each radio -/// configuration listed below is compiled into the RAIL library as a weak -/// symbol that will take into account per-die defaults. If the board -/// configuration in use has different settings than the default, such as a -/// different radio subsystem clock frequency, these radio configurations can -/// be overridden to account for those settings. -/// @{ - -/** - * Default PHY to use for 2.4 GHz 802.15.4. Will be NULL if - * \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154 or \ref RAIL_SUPPORTS_2P4GHZ_BAND - * is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Default PHY to use for 1Mbps 2.4 GHz 802.15.4 with forward error correction. - * Will be NULL if \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec; - -/** - * Default PHY to use for 2Mbps 2.4 GHz 802.15.4. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps; -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with antenna diversity. Will be NULL - * if \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154, \ref RAIL_SUPPORTS_2P4GHZ_BAND, or - * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDiv; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 optimized for coexistence. Will be - * NULL if \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoex; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 optimized for coexistence, while - * supporting antenna diversity. Will be NULL if - * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY or - * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoex; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a - * front-end module. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzFem; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a - * front-end module and antenna diversity. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY or \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY - * is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivFem; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a - * front-end module and is optimized for radio coexistence. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY or - * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoexFem; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a - * front-end module and antenna diversity, and is optimized for radio - * coexistence. Will be NULL if \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY, - * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY, or - * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with custom settings. Will be NULL - * if \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCustom1; - -/** - * Default PHY to use for 863MHz GB868 802.15.4. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB863MHz; - -/** - * Default PHY to use for 915MHz GB868 802.15.4. Will be NULL if - * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB915MHz; - -/** - * Default PHY to use for 2.4 GHz 802.15.4 with RX channel switching. Will be - * NULL if \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching; - -/// @} // End of group IEEE802154_PHY - -/** - * Initialize RAIL for IEEE802.15.4 features. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] config An IEEE802154 configuration structure. - * @return A status code indicating success of the function call. - * - * This function calls the following RAIL functions to configure the radio for - * IEEE802.15.4 features. - * - * Initializes the following: - * - Enables IEEE802154 hardware acceleration - * - Configures RAIL Auto ACK functionality - * - Configures RAIL Address Filter for 802.15.4 address filtering - * - * It saves having to call the following functions individually: - * - RAIL_ConfigAutoAck() - * - RAIL_SetRxTransitions() - * - RAIL_SetTxTransitions() - * - RAIL_WriteAutoAckFifo() - * - RAIL_SetStateTiming() - * - RAIL_ConfigAddressFilter() - * - RAIL_EnableAddressFilter() - * - * It must be called before most of RAIL_IEEE802154_* function. - */ -RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle, - const RAIL_IEEE802154_Config_t *config); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports antenna diversity. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDiv(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity - * optimized for radio coexistence. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports antenna diversity optimized for radio coexistence. It takes - * the place of calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports radio coexistence. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoex(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with a front end module. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioFem(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity - * optimized for a front end module. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports antenna diversity and a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivFem(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence - * and a front end module. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports radio coexistence and a front end module. It takes the place of - * calling \ref RAIL_ConfigChannels. After this call, - * channels 11-26 will be available, giving the frequencies of those channels - * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoexFem(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity - * optimized for radio coexistence and a front end module. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation, but with a configuration - * that supports antenna diversity, radio coexistence and a front end module. - * It takes the place of calling \ref RAIL_ConfigChannels. - * After this call, channels 11-26 will be available, giving the frequencies of - * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoexFem(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/2Mbps operation. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz high speed operation. - * It takes the place of calling \ref RAIL_ConfigChannels. - * After this call, channels 11-26 will be available, giving the frequencies of - * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 - * at 250kbps. - * Channels 11-26 will support transmitting and receiving using dual sync words. - * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 2Mbps. - * Auto-ack and address filtering are disabled when channels 27-42 are selected. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio2Mbps(RAIL_Handle_t railHandle); - -/** - * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/1Mbps forward error correction - * operation. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz high speed operation. - * It takes the place of calling \ref RAIL_ConfigChannels. - * After this call, channels 11-26 will be available, giving the frequencies of - * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 - * at 250kbps. - * Channels 11-26 will support transmitting and receiving using dual sync words. - * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 1Mbps. - * Auto-ack and address filtering are disabled when channels 27-42 are selected. - * - * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio1MbpsFec(RAIL_Handle_t railHandle); - -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Configure the radio for 2.4 GHz 802.15.4 operation with custom - * settings. It enables better interoperability with some proprietary - * PHYs, but doesn't guarantee data sheet performance. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for 2.4 GHz operation with - * custom settings. It replaces needing to call - * \ref RAIL_ConfigChannels. - * Do not call this function unless instructed by Silicon Labs. - * - * @note This feature is only available on platforms where - * \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY is true. - */ -RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCustom1(RAIL_Handle_t railHandle); - -/** - * Configure the radio for SubGHz GB868 863 MHz 802.15.4 operation. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for SubGHz GB868 863 MHz operation. It takes the - * place of calling \ref RAIL_ConfigChannels. - * After this call, GB868 channels in the 863 MHz band (channel pages 28, 29, - * and 30 -- logical channels 0x80..0x9A, 0xA0..0xA8, 0xC0..0xDA, respectively) - * will be available, as defined by Rev 22 of the Zigbee Specification, 2017 - * document 05-3474-22, section D.10.2.1.3.2. - * - * @note This call implicitly enables \ref RAIL_IEEE802154_G_OPTION_GB868. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigGB863MHzRadio(RAIL_Handle_t railHandle); - -/** - * Configure the radio for SubGHz GB868 915 MHz 802.15.4 operation. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * This initializes the radio for SubGHz GB868 915 MHz operation. It takes the - * place of calling \ref RAIL_ConfigChannels. - * After this call, GB868 channels in the 915 MHz band (channel page 31 -- - * logical channels 0xE0..0xFA) will be available, as defined by Rev 22 of - * the Zigbee Specification, 2017 document 05-3474-22, section D.10.2.1.3.2. - * - * @note This call implicitly enables \ref RAIL_IEEE802154_G_OPTION_GB868. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigGB915MHzRadio(RAIL_Handle_t railHandle); - -/** - * De-initialize IEEE802.15.4 hardware acceleration. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * Disables and resets all IEE802.15.4 hardware acceleration features. This - * function should only be called when the radio is IDLE. This calls the - * following: - * - RAIL_SetStateTiming(), to reset all timings to 100 us - * - RAIL_EnableAddressFilter(false) - * - RAIL_ResetAddressFilter() - */ -RAIL_Status_t RAIL_IEEE802154_Deinit(RAIL_Handle_t railHandle); - -/** - * Return whether IEEE802.15.4 hardware acceleration is currently enabled. - * - * @param[in] railHandle A handle of RAIL instance. - * @return True if IEEE802.15.4 hardware acceleration was enabled to start with - * and false otherwise. - */ -bool RAIL_IEEE802154_IsEnabled(RAIL_Handle_t railHandle); - -/** - * @enum RAIL_IEEE802154_PtiRadioConfig_t - * @brief 802.15.4 PTI radio configuration mode - */ -RAIL_ENUM_GENERIC(RAIL_IEEE802154_PtiRadioConfig_t, uint16_t) { - /** - * Built-in 2.4 GHz 802.15.4 radio configuration. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ = 0x00U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration - * with RX antenna diversity support. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV = 0x01U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration - * optimized for radio coexistence. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX = 0x02U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration with - * RX antenna diversity support optimized for radio coexistence. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX = 0x03U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration - * optimized for front end modules. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM = 0x08U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration - * with RX antenna diversity support optimized for - * front end modules. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_ANTDIV = 0x09U, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration - * optimized for radio coexistence and front end modules. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_COEX = 0x0AU, - /** - * Built-in 2.4 GHz 802.15.4 radio configuration with - * RX antenna diversity support optimized for radio coexistence - * and front end modules. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_ANTDIV_COEX = 0x0BU, - /** - * Built-in 863 MHz GB868 802.15.4 radio configuration. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 = 0x85U, - /** - * Built-in 915 MHz GB868 802.15.4 radio configuration. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 = 0x86U, - /** - * External 915 MHz Zigbee R23 802.15.4 NA radio configuration. - */ - RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT = 0x97U, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868) -#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT) -#endif//DOXYGEN_SHOULD_SKIP_THIS - -/** - * Return IEEE802.15.4 PTI radio config. - * - * @param[in] railHandle A handle of RAIL instance. - * @return PTI (Packet Trace Information) radio config ID. - */ -RAIL_IEEE802154_PtiRadioConfig_t RAIL_IEEE802154_GetPtiRadioConfig(RAIL_Handle_t railHandle); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Set IEEE802.15.4 PTI radio config (for Silicon Labs internal use only). - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] ptiRadioConfig PTI (Packet Trace Information) radio config ID. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_IEEE802154_SetPtiRadioConfig(RAIL_Handle_t railHandle, - RAIL_IEEE802154_PtiRadioConfig_t ptiRadioConfigId); -#endif - -/** - * Configure the RAIL Address Filter for 802.15.4 filtering. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] addresses The address information that should be used. - * @return A status code indicating success of the function call. If this returns - * an error, the 802.15.4 address filter is in an undefined state. - * - * Set up the 802.15.4 address filter to accept messages to the given - * addresses. This will return false if any of the addresses failed to be set. - * If NULL is passed in for addresses, all addresses will be set to their - * reset value. - */ -RAIL_Status_t RAIL_IEEE802154_SetAddresses(RAIL_Handle_t railHandle, - const RAIL_IEEE802154_AddrConfig_t *addresses); - -/** - * Set a PAN ID for 802.15.4 address filtering. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] panId The 16-bit PAN ID information. - * This will be matched against the destination PAN ID of incoming messages. - * The PAN ID is sent little endian over the air, meaning panId[7:0] is first in - * the payload followed by panId[15:8]. Set to 0xFFFF to disable for this index. - * @param[in] index Indicates which PAN ID to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. - * - * Set up the 802.15.4 address filter to accept messages to the given PAN ID. - */ -RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle, - uint16_t panId, - uint8_t index); - -/** - * Set a short address for 802.15.4 address filtering. - * - * @param[in] railHandle A handle of RAIL instance - * @param[in] shortAddr 16 bit short address value. This will be matched against the - * destination short address of incoming messages. The short address is sent - * little endian over the air meaning shortAddr[7:0] is first in the payload - * followed by shortAddr[15:8]. Set to 0xFFFF to disable for this index. - * @param[in] index Which short address to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. - * - * Set up the 802.15.4 address filter to accept messages to the given short - * address. - */ -RAIL_Status_t RAIL_IEEE802154_SetShortAddress(RAIL_Handle_t railHandle, - uint16_t shortAddr, - uint8_t index); - -/** - * Set a long address for 802.15.4 address filtering. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] longAddr A pointer to an 8-byte array containing the long address - * information. The long address must be in over-the-air byte order. This will - * be matched against the destination long address of incoming messages. Set to - * 0x00 00 00 00 00 00 00 00 to disable for this index. - * @param[in] index Indicates which long address to set. Must be below - * RAIL_IEEE802154_MAX_ADDRESSES. - * @return A status code indicating success of the function call. - * - * Set up the 802.15.4 address filter to accept messages to the given long - * address. - */ -RAIL_Status_t RAIL_IEEE802154_SetLongAddress(RAIL_Handle_t railHandle, - const uint8_t *longAddr, - uint8_t index); - -/** - * Set whether the current node is a PAN coordinator. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] isPanCoordinator True if this device is a PAN coordinator. - * @return A status code indicating success of the function call. - * - * If the device is a PAN Coordinator, it will accept data and command - * frames with no destination address. This function will fail if 802.15.4 - * hardware acceleration is not currently enabled by calling - * \ref RAIL_IEEE802154_Init(). This setting may be changed - * at any time when 802.15.4 hardware acceleration is enabled. - */ -RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(RAIL_Handle_t railHandle, - bool isPanCoordinator); - -/** - * Set whether to enable 802.15.4 promiscuous mode. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] enable True if all frames and addresses should be accepted. - * @return A status code indicating success of the function call. - * - * If promiscuous mode is enabled, no frame or address filtering steps - * will be performed other than checking the CRC. This function will fail if - * 802.15.4 hardware acceleration is not currently enabled by calling - * \ref RAIL_IEEE802154_Init(). This setting may be changed at any time when - * 802.15.4 hardware acceleration is enabled. - */ -RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(RAIL_Handle_t railHandle, - bool enable); - -/** - * @enum RAIL_IEEE802154_EOptions_t - * @brief 802.15.4E-2012 options, in reality a bitmask. - */ -RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { - /** Shift position of \ref RAIL_IEEE802154_E_OPTION_GB868 bit. */ - RAIL_IEEE802154_E_OPTION_GB868_SHIFT = 0, - RAIL_IEEE802154_E_OPTION_ENH_ACK_SHIFT, - RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST_SHIFT, -}; - -/** A value representing no options enabled. */ -#define RAIL_IEEE802154_E_OPTIONS_NONE 0UL -/** All options disabled by default . */ -#define RAIL_IEEE802154_E_OPTIONS_DEFAULT RAIL_IEEE802154_E_OPTIONS_NONE - -/** - * An option to enable/disable 802.15.4E-2012 features needed for GB868. - * When not promiscuous, RAIL normally accepts only 802.15.4 MAC frames - * whose MAC header Frame Version is 0 (802.15.4-2003) or 1 (802.15.4-2006), - * filtering out higher Frame Version packets (as \ref - * RAIL_RX_PACKET_ABORT_FORMAT). - * Enabling this feature additionally allows Frame Version 2 (802.15.4E-2012 / - * 802.15.4-2015) packets to be accepted and passed to the application. - * - * @note Enabling this feature also automatically enables \ref - * RAIL_IEEE802154_E_OPTION_ENH_ACK on platforms that support - * that feature. - * - * @note This feature does not automatically enable receiving Multipurpose - * frames; that can be enabled via RAIL_IEEE802154_AcceptFrames()'s - * \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES. - */ -#define RAIL_IEEE802154_E_OPTION_GB868 (1UL << RAIL_IEEE802154_E_OPTION_GB868_SHIFT) - -/** - * An option to enable/disable 802.15.4E-2012 features needed for Enhanced ACKs. - * This option requires that \ref RAIL_IEEE802154_E_OPTION_GB868 also be - * enabled, and is enabled automatically on platforms that support this - * feature. It exists as a separate flag to allow runtime detection of whether - * the platform supports this feature or not. - * - * When enabled, only an Enhanced ACK is expected in response to a transmitted - * ACK-requesting 802.15.4E Version 2 frame. RAIL only knows how to construct - * 802.15.4 Immediate ACKs but not Enhanced ACKs. - * - * This option causes \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND to be - * issued for ACK-requesting Version 2 MAC Command frames, Data frames - * (if \ref RAIL_IEEE802154_EnableDataFramePending() is enabled), and - * Multipurpose Frames (if \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES - * is enabled). - * - * The application is expected to handle this event by calling \ref - * RAIL_GetRxIncomingPacketInfo() and parsing the partly-received incoming - * frame to determine the type of ACK needed: - * - If an Immediate ACK, determine Frame Pending needs based on the packet - * type and addressing information and call \ref - * RAIL_IEEE802154_ToggleFramePending() if necessary; - * - If an Enhanced ACK, generate the complete payload of the Enhanced ACK - * including any Frame Pending information and call \ref - * RAIL_IEEE802154_WriteEnhAck() in time for that Enhanced ACK to - * be sent. If not called in time, \ref RAIL_EVENT_TXACK_UNDERFLOW will - * likely result. - * Note that if 802.15.4 MAC-level encryption is used with Version 2 - * frames, the application should decrypt the MAC Command byte in a - * MAC Command frame to determine whether it is a Data Request or other - * MAC Command. - * - * An application can also enable \ref - * RAIL_IEEE802154_EnableEarlyFramePending() if the protocol doesn't - * need to examine the MAC Command byte of MAC Command frames but can - * infer it to be a Data Request. - * - * On 802.15.4E GB868 platforms that lack this support, legacy Immediate ACKs - * are sent/expected for received/transmitted ACK-requesting 802.15.4E Frame - * Version 2 frames; calls to \ref RAIL_IEEE802154_WriteEnhAck() have no - * effect. Attempting to use this feature via \ref - * RAIL_IEEE802154_ConfigEOptions() returns an error. - */ -#define RAIL_IEEE802154_E_OPTION_ENH_ACK (1UL << RAIL_IEEE802154_E_OPTION_ENH_ACK_SHIFT) - -/** - * An option to enable/disable 802.15.4E-2012 macImplicitBroadcast feature. - * - * When enabled, received Frame Version 2 frames without a destination - * PAN ID or destination address are treated as though they are addressed - * to the broadcast PAN ID and broadcast short address. When disabled, such - * frames are filtered unless the device is the PAN coordinator and - * appropriate source addressing information exists in the packet - */ -#define RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST (1UL << RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST_SHIFT) - -/** A value representing all possible options. */ -#define RAIL_IEEE802154_E_OPTIONS_ALL 0xFFFFFFFFUL - -/** - * Configure certain 802.15.4E-2012 / 802.15.4-2015 Frame Version 2 features. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] mask A bitmask containing which options should be modified. - * @param[in] options A bitmask containing desired options settings. - * Bit positions for each option are found in the \ref - * RAIL_IEEE802154_EOptions_t. - * @return A status code indicating success of the function call. - * - * This function will fail if 802.15.4 hardware acceleration is not - * currently enabled by calling \ref RAIL_IEEE802154_Init() or the platform - * does not support the feature(s). - * These settings may be changed at any time when 802.15.4 hardware - * acceleration is enabled. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigEOptions(RAIL_Handle_t railHandle, - RAIL_IEEE802154_EOptions_t mask, - RAIL_IEEE802154_EOptions_t options); - -/** - * @enum RAIL_IEEE802154_GOptions_t - * @brief 802.15.4G-2012 options, in reality a bitmask. - */ -RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { - /** Shift position of \ref RAIL_IEEE802154_G_OPTION_GB868 bit. */ - RAIL_IEEE802154_G_OPTION_GB868_SHIFT = 0, - /** Shift position of \ref RAIL_IEEE802154_G_OPTION_DYNFEC bit. */ - RAIL_IEEE802154_G_OPTION_DYNFEC_SHIFT, - /** Shift position of \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH bit. */ - RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH_SHIFT, -}; - -/** A value representing no options enabled. */ -#define RAIL_IEEE802154_G_OPTIONS_NONE 0UL -/** All options disabled by default . */ -#define RAIL_IEEE802154_G_OPTIONS_DEFAULT RAIL_IEEE802154_G_OPTIONS_NONE - -/** - * An option to enable/disable 802.15.4G-2012 features needed for GB868. - * Normally RAIL supports 802.15.4-2003 and -2006 radio configurations - * that have the single-byte PHY header allowing frames up to 128 bytes - * in size. This feature must be enabled for 802.15.4G-2012 or - * 802.15.4-2015 SUN PHY radio configurations with the two-byte - * bit-reversed-length PHY header format. - * - * While GB868 only supports whitened non-FEC non-mode-switch frames - * up to 129 bytes including 2-byte CRC, this option also enables: - * - On platforms where \ref RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED - * is true: automatic per-packet 2/4-byte Frame Check Sequence (FCS) - * reception and transmission based on the FCS Type bit in the - * received/transmitted PHY header. This includes ACK reception - * and automatically-generated ACKs reflect the CRC size of the - * incoming frame being acknowledged (i.e., their MAC payload will be - * increased to 7 bytes when sending 4-byte FCS). - * On other platforms, only the 2-byte FCS is supported. - * - On platforms where \ref RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED - * and/or \ref RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED are true: - * automatic per-packet whitened/unwhitened reception and transmission, - * respectively, based on the Data Whitening bit in the received/transmitted - * PHY header. This includes ACK reception and automatically-generated ACKs - * which reflect the whitening of the incoming frame being acknowledged. - * On other platforms, only whitened frames are supported. - * - Support for frames up to 2049 bytes per the radio configuration's - * maximum packet length setting. - * - * @note Sending/receiving whitened frames assumes the radio configuration - * has established an appropriate 802.15.4-compliant whitening algorithm. - * RAIL does not itself override the radio configuration's whitening - * settings other than to enable/disable it per-packet based on the - * packet's PHY header Data Whitening flag. - */ -#define RAIL_IEEE802154_G_OPTION_GB868 (1UL << RAIL_IEEE802154_G_OPTION_GB868_SHIFT) -/** - * An option to enable/disable 802.15.4G dynamic FEC feature (SUN FSK only). - * The syncWord, called start-of-frame delimiter (SFD) in the 15.4 spec, indicates whether - * the rest of the packet is FEC encoded or not. This feature requires per-packet - * dual syncWord detection and specific receiver pausing. - * Note that this feature is only available on platforms where - * \ref RAIL_IEEE802154_SUPPORTS_G_DYNFEC is true. - * - * This option is only valid for SUN PHYs that have the FEC configured and enabled. - * - * The syncWord used during transmit is selected with \ref RAIL_TX_OPTION_SYNC_WORD_ID. - * - * The syncWord corresponding to the FEC encoded mode must be SYNC1, with SYNC2 indicating non-FEC. - * SyncWords are set appropriately in all Sun FEC-enabled PHYs so there should - * never be a need to call \ref RAIL_ConfigSyncWords() when this option is enabled. - * - * Also, dual syncWord detection is set in all SUN FEC enabled PHYs, then there is no need - * to change \ref RAIL_RX_OPTION_ENABLE_DUALSYNC . - * - * @note EFR32xG12 support for 802.15.4 FEC-capable PHYs and dynamic FEC - * are incompatible with 802.15.4 filtering and AutoACK. - * \ref RAIL_IEEE802154_Config_t::promiscuousMode must be true and \ref - * RAIL_IEEE802154_Config_t::ackConfig's \ref RAIL_AutoAckConfig_t.enable - * must be false on these platforms when using a FEC-capable PHY. - */ -#define RAIL_IEEE802154_G_OPTION_DYNFEC (1UL << RAIL_IEEE802154_G_OPTION_DYNFEC_SHIFT) -/** - * An option to enable/disable Wi-SUN Mode Switch feature. - * This feature consists in switching to a new PHY mode with a higher rate typically - * by sending/receiving a specific Mode Switch packet that indicates the incoming new PHY mode. - * The Mode Switch packet is an FSK-modulated 2-byte PHY header with no payload. - * Because this feature relies on specific receiver pausing, note that it is only available - * on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. - */ -#define RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH (1UL << RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH_SHIFT) - -/** A value representing all possible options. */ -#define RAIL_IEEE802154_G_OPTIONS_ALL 0xFFFFFFFFUL - -/** - * Configure certain 802.15.4G-2012 / 802.15.4-2015 SUN PHY features - * (only for radio configurations designed accordingly). - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] mask A bitmask containing which options should be modified. - * @param[in] options A bitmask containing desired options settings. - * Bit positions for each option are found in the \ref - * RAIL_IEEE802154_GOptions_t. - * @return A status code indicating success of the function call. - * - * This function will fail if 802.15.4 hardware acceleration is not - * currently enabled by calling \ref RAIL_IEEE802154_Init(), the platform does - * not support the feature(s), the radio configuration is not appropriate, - * or the radio is not idle. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigGOptions(RAIL_Handle_t railHandle, - RAIL_IEEE802154_GOptions_t mask, - RAIL_IEEE802154_GOptions_t options); - -/** - * @struct RAIL_IEEE802154_ModeSwitchPhr_t - * @brief A structure containing the PHYModeID value and the corresponding mode - * switch PHR as defined in Wi-SUN spec. - * These structures are usually generated by the radio configurator. - */ -typedef struct RAIL_IEEE802154_ModeSwitchPhr { - uint8_t phyModeId; /**< PHY mode Id */ - uint16_t phr; /**< Corresponding Mode Switch PHY header */ -} RAIL_IEEE802154_ModeSwitchPhr_t; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** When filtering PhyModeId, this is the minimum OFDM value */ -#define MIN_OFDM_PHY_MODE_ID (0x20U) -/** When filtering PhyModeId, this is the maximum OFDM value */ -#define MAX_OFDM_PHY_MODE_ID (0x5FU) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Compute channel to switch to given a targeted PhyMode ID - * in the context of Wi-SUN mode switching. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] newPhyModeId A targeted PhyMode ID. - * @param[out] pChannel A pointer to the channel to switch to. - * @return A status code indicating success of the function call. - * - * This function will fail if: - * - the targeted PhyModeID is the same as the current PhyMode ID - * - called on a platform that lacks \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH - * - called on a platform that doesn't have 802154G options enabled - * by \ref RAIL_IEEE802154_ConfigGOptions(). - * For newPhyModeId associated with a FSK FEC_off PHY, if dynamic FEC is - * activated (see \ref RAIL_IEEE802154_G_OPTION_DYNFEC), the returned - * channel can correspond to the associated FSK FEC_on PHY corresponding - * then to PhyModeID = newPhyModeId + 16 - */ -RAIL_Status_t RAIL_IEEE802154_ComputeChannelFromPhyModeId(RAIL_Handle_t railHandle, - uint8_t newPhyModeId, - uint16_t *pChannel); - -/** - * Manage forbidden channels during mode switch. - * - * @param[in] currentBaseFreq The current frequency of the base channel. - * @param[in] newPhyModeId A targeted PhyMode ID. - * @param[in] configEntryNewPhyModeId A pointer to \ref RAIL_ChannelConfigEntry_t - * structure corresponding to the new PHY configEntry. - * @param[in, out] pChannel A pointer to the channel to switch to. If channel - * is valid, the function must just return. If channel is forbidden, the - * function must update it with the closest valid channel. The highest - * channel must be selected in case of two valid channels being equidistant - * to a forbidden channel. - * @return A status code indicating success of the function call. It must - * return RAIL_STATUS_INVALID_PARAMETER for failure or RAIL_STATUS_NO_ERROR - * for success. - * - * This function must fail if no valid channel has been found. If so, RAIL will - * abort the mode switch. - * - * @note This callback will only be called on platforms where - * \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true, \ref - * RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH was successfully enabled, - * and a valid mode switch PHY header is received. - */ -RAIL_Status_t RAILCb_IEEE802154_IsModeSwitchNewChannelValid(uint32_t currentBaseFreq, - uint8_t newPhyModeId, - const RAIL_ChannelConfigEntry_t *configEntryNewPhyModeId, - uint16_t *pChannel); - -/// When receiving packets, accept 802.15.4 BEACON frame types. -#define RAIL_IEEE802154_ACCEPT_BEACON_FRAMES (0x01) -/// When receiving packets, accept 802.15.4 DATA frame types. -#define RAIL_IEEE802154_ACCEPT_DATA_FRAMES (0x02) -/// When receiving packets, accept 802.15.4 ACK frame types. -/// @note Expected ACK frame types will still be accepted regardless -/// of this setting when waiting for an ACK after a transmit that -/// used \ref RAIL_TX_OPTION_WAIT_FOR_ACK and auto-ACK is enabled. -#define RAIL_IEEE802154_ACCEPT_ACK_FRAMES (0x04) -/// When receiving packets, accept 802.15.4 COMMAND frame types. -#define RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES (0x08) -// Reserved for possible future use: (0x10) -/// When receiving packets, accept 802.15.4-2015 Multipurpose frame types. -/// (Not supported on EFR32XG1.) -#define RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES (0x20) - -/// In standard operation, accept BEACON, DATA and COMMAND frames. -/// Don't receive ACK frames unless waiting for ACK (i.e., only -/// receive expected ACKs). -#define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES \ - | RAIL_IEEE802154_ACCEPT_DATA_FRAMES \ - | RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES) - -/** - * Set which 802.15.4 frame types to accept. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] framesMask A mask containing which 802.15.4 frame types to receive. - * @return A status code indicating success of the function call. - * - * This function will fail if 802.15.4 hardware acceleration is not currently - * enabled by calling \ref RAIL_IEEE802154_Init() or framesMask requests an - * unsupported frame type. - * This setting may be changed at any time when 802.15.4 hardware - * acceleration is enabled. Only Beacon, Data, ACK, Command, and Multipurpose - * (except on EFR32XG1) frames may be received. - * The RAIL_IEEE802154_ACCEPT_XXX_FRAMES defines may be combined to create a - * bitmask to pass into this function. - * - * \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES behaves slightly different than the - * other defines. If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is set, the radio - * will accept an ACK frame during normal packet reception, but only a - * truly expected ACK will have its \ref RAIL_RxPacketDetails_t::isAck true. - * If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, ACK frames will be - * filtered unless they're expected when the radio is waiting for an ACK. - */ -RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, - uint8_t framesMask); - -/** - * Enable early Frame Pending lookup event notification - * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND). - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] enable True to enable, false to disable. - * @return A status code indicating success of the function call. - * - * Normally, \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered after - * receiving the entire MAC header and MAC command byte for an ACK-requesting - * MAC command frame. Version 0/1 frames also require that command to be a - * Data Request for this event to occur. - * Enabling this feature causes this event to be triggered earlier to allow for - * more time to determine the type of ACK needed (Immediate or Enhanced) and/or - * perform frame pending lookup to influence the outgoing ACK by using \ref - * RAIL_IEEE802154_WriteEnhAck() or \ref RAIL_IEEE802154_ToggleFramePending(). - * - * For Frame Version 0/1 packets and for Frame Version 2 packets when \ref - * RAIL_IEEE802154_E_OPTION_ENH_ACK is not in use, "early" means right - * after receiving the source address information in the MAC header. - * - * For Frame Version 2 packets when \ref RAIL_IEEE802154_E_OPTION_ENH_ACK - * is in use, "early" means right after receiving any Auxiliary Security - * header which follows the source address information in the MAC header. - * - * This feature is useful when the protocol knows an ACK-requesting MAC - * Command must be a data poll without needing to receive the MAC Command - * byte, giving it a bit more time to adjust Frame Pending or generate an - * Enhanced ACK. - * - * This function will fail if 802.15.4 hardware acceleration is not - * currently enabled by calling \ref RAIL_IEEE802154_Init(), - * or on platforms that do not support this feature. - * This setting may be changed at any time when 802.15.4 hardware - * acceleration is enabled. - */ -RAIL_Status_t RAIL_IEEE802154_EnableEarlyFramePending(RAIL_Handle_t railHandle, - bool enable); - -/** - * Enable Frame Pending lookup event notification - * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND) for MAC Data frames. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] enable True to enable, false to disable. - * @return A status code indicating success of the function call. - * - * Normally \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered only - * for ACK-requesting MAC command frames. - * Enabling this feature causes this event to also be triggered for MAC data - * frames, at the same point in the packet as \ref - * RAIL_IEEE802154_EnableEarlyFramePending() would trigger. - * This feature is necessary to support the Thread Basil-Hayden Enhanced - * Frame Pending feature in Version 0/1 frames, and to support Version 2 - * Data frames which require an Enhanced ACK. - * - * This function will fail if 802.15.4 hardware acceleration is not - * currently enabled by calling \ref RAIL_IEEE802154_Init(). - * This setting may be changed at any time when 802.15.4 hardware acceleration - * is enabled. - */ -RAIL_Status_t RAIL_IEEE802154_EnableDataFramePending(RAIL_Handle_t railHandle, - bool enable); - -/** - * Alternate naming for function \ref RAIL_IEEE802154_SetFramePending - * to depict it is used for changing the default setting specified by - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks in - * an outgoing ACK. - */ - #define RAIL_IEEE802154_ToggleFramePending RAIL_IEEE802154_SetFramePending - -/** - * Change the Frame Pending bit on the outgoing legacy Immediate ACK from - * the default specified by - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. - * @param[in] railHandle A handle of RAIL instance - * @return A status code indicating success of the function call. - * - * This function must only be called while processing the \ref - * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND if the ACK - * for this packet should go out with its Frame Pending bit set differently - * than what was specified by - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. - * - * It's intended only for use with 802.15.4 legacy immediate ACKs and - * not 802.15.4E enhanced ACKs. - * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * modify the outgoing Immediate ACK. - - * @note This function is used to set the Frame Pending bit but its meaning - * depends on the value of - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * while transmitting ACK. - * If \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is not set, then Frame Pending bit is set in outgoing ACK. - * Whereas, if \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is set, then Frame Pending bit is cleared in outgoing ACK. - * - * Therefore, this function is to be called if the frame is pending when - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is not set or if there is no frame pending when - * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks - * is set. - */ -RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle); - -/** - * Get the source address of the incoming data request. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] pAddress A pointer to \ref RAIL_IEEE802154_Address_t structure - * to populate with source address information. - * @return A status code indicating success of the function call. - * - * This function must only be called when handling the \ref - * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. This will return - * \ref RAIL_STATUS_INVALID_STATE if the address information is stale - * (i.e., it is too late to affect the outgoing ACK). - */ -RAIL_Status_t RAIL_IEEE802154_GetAddress(RAIL_Handle_t railHandle, - RAIL_IEEE802154_Address_t *pAddress); - -/** - * Write the AutoACK FIFO for the next outgoing 802.15.4E Enhanced ACK. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] ackData Pointer to ACK data to transmit - * This may be NULL, in which case it's assumed the data has already - * been emplaced into the ACK buffer and RAIL just needs to be told - * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get - * the address of RAIL's AutoACK buffer in RAM and its size. - * @param[in] ackDataLen Length of ACK data, in bytes. - * If this exceeds \ref RAIL_AUTOACK_MAX_LENGTH the function - * will return \ref RAIL_STATUS_INVALID_PARAMETER. - * @return A status code indicating success of the function call. - * - * This function sets the AutoACK data to use in acknowledging the frame - * being received. It must only be called while processing the \ref - * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND, and is intended for use - * when packet information from \ref RAIL_GetRxIncomingPacketInfo() - * indicates an 802.15.4E Enhanced ACK must be sent instead of a legacy - * Immediate ACK. \ref RAIL_IEEE802154_ToggleFramePending() should not be - * called for an Enhanced ACK; instead the Enhanced ACK's Frame Control - * Field should have the Frame Pending bit set appropriately in its ackData. - * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * write the outgoing ACK -- a situation that will likely trigger - * a \ref RAIL_EVENT_TXACK_UNDERFLOW event. When successful, the Enhanced - * ackData will only be sent once. Subsequent packets needing an Enhanced - * ACK will each need to call this function to write their ACK information. - */ -RAIL_Status_t RAIL_IEEE802154_WriteEnhAck(RAIL_Handle_t railHandle, - const uint8_t *ackData, - uint8_t ackDataLen); - -/** - * Set a separate RX packet to TX state transition turnaround time for - * sending an Enhanced ACK. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in,out] pRxToEnhAckTx Pointer to the turnaround transition requested - * for Enhanced ACKs. It will be updated with the actual time set. - * Requesting a time of 0 will sync the Enhanced ACK turnaround time with - * that used for immediate ACKs (and output 0). Requesting a time of \ref - * RAIL_TRANSITION_TIME_KEEP will output the current Enhanced ACK timing - * parameter (0 if it is the same as that used for Immediate ACKs). - * @return Status code indicating a success of the function call. - * An error will not update the pRxToEnhAckTx output parameter. - * - * Normally Immediate and Enhanced ACKs are both sent using the - * \ref RAIL_IEEE802154_Config_t::timings rxToTx turnaround time. - * If the stack needs more time to prepare an Enhanced ACK, it can - * call this function after \ref RAIL_IEEE802154_Init() to set a - * longer turnaround time used just for Enhanced ACK transmits. - * - * This function will fail on platforms that lack - * \ref RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. - */ -RAIL_Status_t RAIL_IEEE802154_SetRxToEnhAckTx(RAIL_Handle_t railHandle, - RAIL_TransitionTime_t *pRxToEnhAckTx); - -/** - * Convert RSSI into 802.15.4 Link Quality Indication (LQI) metric - * compatible with the Silicon Labs Zigbee stack. - * - * @param[in] origLqi The original LQI, for example from - * \ref RAIL_RxPacketDetails_t::lqi. - * This parameter is not currently used but may be used in the future. - * @param[in] rssiDbm The RSSI in dBm, for example from - * \ref RAIL_RxPacketDetails_t::rssi. - * @return An LQI value (range 0..255 but not all intermediate values are - * possible) based on the rssiDbm and the chip's RSSI sensitivity range. - * - * This function is compatible with \ref RAIL_ConvertLqiCallback_t and - * is suitable to pass to \ref RAIL_ConvertLqi(). - */ -uint8_t RAIL_IEEE802154_ConvertRssiToLqi(uint8_t origLqi, int8_t rssiDbm); - -/** - * Convert RSSI into 802.15.4 Energy Detection (ED) metric - * compatible with the Silicon Labs Zigbee stack. - * - * @param[in] rssiDbm The RSSI in dBm, for example from - * \ref RAIL_RxPacketDetails_t::rssi. - * @return An Energy Detect value (range 0..255 but not all intermediate - * values are possible) based on the rssiDbm and the chip's RSSI - * sensitivity range. - */ -uint8_t RAIL_IEEE802154_ConvertRssiToEd(int8_t rssiDbm); - -/** - * @enum RAIL_IEEE802154_CcaMode_t - * @brief Available CCA modes. - */ -RAIL_ENUM(RAIL_IEEE802154_CcaMode_t) { - /** - * RSSI-based CCA. CCA reports a busy medium upon detecting any energy - * above \ref RAIL_CsmaConfig_t.ccaThreshold. - */ - RAIL_IEEE802154_CCA_MODE_RSSI = 0, - /** - * Signal Identifier-based CCA. CCA reports a busy medium only upon the - * detection of a signal compliant with this standard with the same modulation - * and spreading characteristics of the PHY that is currently in use. - */ - RAIL_IEEE802154_CCA_MODE_SIGNAL, - /** - * RSSI or signal identifier-based CCA. CCA reports a busy medium on - * either detecting any energy above \ref RAIL_CsmaConfig_t.ccaThreshold - * or detection of a signal compliant with this standard with the same - * modulation and spreading characteristics of the PHY that is currently in use. - */ - RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI, - /** - * RSSI and signal identifier-based CCA. CCA reports a busy medium only - * on detecting any energy above \ref RAIL_CsmaConfig_t.ccaThreshold of a - * signal compliant with this standard with the same modulation and spreading - * characteristics of the PHY that is currently in use. - */ - RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI, - /** - * ALOHA. Always transmit CCA=1. CCA always reports an idle medium. - */ - RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT, - /** - * Number of CCA modes. - */ - RAIL_IEEE802154_CCA_MODE_COUNT -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_CCA_MODE_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_RSSI) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI) -#define RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI) -#define RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT) -#define RAIL_IEEE802154_CCA_MODE_COUNT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_COUNT) -#endif - -/** - * @enum RAIL_IEEE802154_SignalIdentifierMode_t - * @brief Available Signal identifier modes. - */ -RAIL_ENUM(RAIL_IEEE802154_SignalIdentifierMode_t) { - /* Disable signal detection mode. */ - RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, - /* 2.4Ghz 802.15.4 signal detection mode. */ - RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE) -#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154) -#endif - -/** - * Configure signal identifier for 802.15.4 signal detection. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] signalIdentifierMode Mode of signal identifier operation. - * - * This features allows detection of 2.4Ghz 802.15.4 signal on air. This - * function must be called once before \ref RAIL_IEEE802154_EnableSignalDetection - * to configure and enable signal identifier. - * - * To enable event for signal detection \ref RAIL_ConfigEvents() must be called - * for enabling \ref RAIL_EVENT_SIGNAL_DETECTED. - * - * This function is only supported by chips where - * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and - * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigSignalIdentifier(RAIL_Handle_t railHandle, - RAIL_IEEE802154_SignalIdentifierMode_t signalIdentifierMode); - -/** - * Enable or disable signal identifier for 802.15.4 signal detection. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enable Signal detection is enabled if true, disabled if false. - * - * \ref RAIL_IEEE802154_ConfigSignalIdentifier must be called once before calling - * this function to configure and enable signal identifier. - * Once a signal is detected signal detection will be turned off and this - * function should be called to re-enable the signal detection without needing - * to call \ref RAIL_IEEE802154_ConfigSignalIdentifier if the signal identifier - * is already configured and enabled. - * - * This function is only supported by chips where - * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and - * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_IEEE802154_EnableSignalDetection(RAIL_Handle_t railHandle, - bool enable); - -/** - * @brief Backward compatible name for the \ref - * RAIL_IEEE802154_EnableSignalDetection API. - */ -#define RAIL_IEEE802154_EnableSignalIdentifier RAIL_IEEE802154_EnableSignalDetection - -/** - * Set 802.15.4 CCA mode. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] ccaMode Mode of CCA operation. - * - * This function sets the CCA mode \ref RAIL_IEEE802154_CcaMode_t. - * If not called, RAIL_IEEE802154_CCA_MODE_RSSI (RSSI-based CCA) is used for CCA. - * - * In RAIL_IEEE802154_CCA_MODE_SIGNAL, RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI and - * RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI signal identifier is enabled - * for the duration of LBT. If previously enabled by - * \ref RAIL_IEEE802154_ConfigSignalIdentifier, the signal identifier will remain - * active until triggered. - * - * This function is only supported by chips where - * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and - * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. - * - * @return Status code indicating success of the function call. - * An error should be returned if ccaMode is unsuppported on a given device. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigCcaMode(RAIL_Handle_t railHandle, - RAIL_IEEE802154_CcaMode_t ccaMode); - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * Allow certain malformed MAC Header frames to be received. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] enable True to enable, false to disable. - * @return A status code indicating success of the function call. - * - * When allowed, certain MAC header formats that 802.15.4 deems - * illegal will be received rather than filtered. This is to - * support interoperablity with an old spec-violating 802.15.4 - * peer and is only supported on certain Series-2 platforms. - * - * @note \ref RAIL_IEEE802154_SetPanCoordinator() must also be - * enabled to receive malformed frames lacking destination - * address information. - */ -RAIL_Status_t RAIL_IEEE802154_AllowMalformed(RAIL_Handle_t railHandle, - bool allow); -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Configure RX channel switching for 802.15.4. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] pConfig A pointer to \ref RAIL_IEEE802154_RxChannelSwitchingCfg_t - * structure. Use NULL to disable any switching previously set up. - * @return Status code indicating success of the function call. - * - * This function configures RX channel switching, allowing reception of 2.4Ghz - * 802.15.4 signals on two different radio channels within the same PHY. - * (If the two channels are same, the function behaves the same as if - * pConfig was NULL.) - * This function should be - * called once before \ref RAIL_StartRx and/or enabling - * \ref RAIL_RX_OPTION_CHANNEL_SWITCHING. - * - * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is enabled, - * channel switching will occur during normal listening but is suspended - * (and the radio is idled) when starting any kind of transmit, including - * scheduled or CSMA transmits. It remains suspended after a \ref - * RAIL_TX_OPTION_WAIT_FOR_ACK transmit until the ACK is received or - * times out. - * - * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is disabled after switching - * has been active, the radio could be left listening on either channel, - * so the application should call \ref RAIL_StartRx() to put it on the - * desired non-switching channel. - * - * @note IEEE 802.15.4 must be enabled via \ref RAIL_IEEE802154_Init, and the - * radio must be in the idle state when configuring RX channel switching. - * A DMA channel must be allocated with \ref RAIL_UseDma; otherwise this API - * will return \ref RAIL_STATUS_INVALID_CALL. - * This feature also requires a PRS channel, internally allocated by the RAIL - * library, to use and hold onto for future use. If no PRS channel is - * available, the function returns \ref RAIL_STATUS_INVALID_PARAMETER. - * - * @note When RX channel switching is active, receive sensitivity and performance - * are slightly impacted. - * - * @note This function internally uses \ref RAIL_EnableCacheSynthCal to - * enable/disable the sequencer cache to store the synth calibration value. - * - * @note Switching is cancelled on any PHY change, so this function would - * need to be re-called to reestablish switching after such a change. - */ -RAIL_Status_t RAIL_IEEE802154_ConfigRxChannelSwitching(RAIL_Handle_t railHandle, - const RAIL_IEEE802154_RxChannelSwitchingCfg_t *pConfig); - -/** @} */ // end of IEEE802.15.4 - -/// @addtogroup Calibration -/// @brief IEEE802154 protocol-specific APIs for calibrating the radio. -/// @{ - -/** - * Calibrate image rejection for IEEE 802.15.4 2.4 GHz. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. - * - * Some chips have protocol-specific image rejection calibrations programmed - * into their flash. This function will either get the value from flash and - * apply it, or run the image rejection algorithm to find the value. - */ -RAIL_Status_t RAIL_IEEE802154_CalibrateIr2p4Ghz(RAIL_Handle_t railHandle, - uint32_t *imageRejection); - -/** - * Calibrate image rejection for IEEE 802.15.4 915 MHz and 868 MHz. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] imageRejection The result of the image rejection calibration. - * @return A status code indicating success of the function call. - * - * Some chips have protocol-specific image rejection calibrations programmed - * into their flash. This function will either get the value from flash and - * apply it, or run the image rejection algorithm to find the value. - * - * @deprecated Please use \ref RAIL_CalibrateIrAlt instead. - */ -RAIL_Status_t RAIL_IEEE802154_CalibrateIrSubGhz(RAIL_Handle_t railHandle, - uint32_t *imageRejection); - -/// @} // End of group Calibration - -#ifdef __cplusplus -} -#endif - -#ifdef RAIL_INTERNAL_BUILD -#include "rail_ieee802154_internal.h" -#endif - -#endif // __RAIL_IEEE802154_H__ +/***************************************************************************//** + * @file + * @brief The IEEE 802.15.4 specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_IEEE802154_H__ +#define __RAIL_IEEE802154_H__ + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @addtogroup IEEE802_15_4 IEEE 802.15.4 +/// @ingroup Protocol_Specific +/// @brief IEEE 802.15.4 configuration routines +/// +/// The functions in this group configure RAIL IEEE 802.15.4 hardware +/// acceleration which includes IEEE 802.15.4 format filtering, address +/// filtering, ACKing, and filtering based on the frame type. +/// +/// To configure IEEE 802.15.4 functionality, the application must first set up +/// a RAIL instance with RAIL_Init() and other setup functions. +/// Instead of RAIL_ConfigChannels(), however, an +/// application may use RAIL_IEEE802154_Config2p4GHzRadio() to set up the +/// official IEEE 2.4 GHz 802.15.4 PHY. This configuration is shown below. +/// +/// 802.15.4 defines its macAckWaitDuration from the end of the transmitted +/// packet to complete reception of the ACK. RAIL's ackTimeout only covers +/// sync word detection of the ACK. Therefore, subtract the ACK's +/// PHY header and payload time to get RAIL's ackTimeout setting. +/// For 2.4 GHz OQPSK, macAckWaitDuration is specified as 54 symbols; +/// subtracting 2-symbol PHY header and 10-symbol payload yields a RAIL +/// ackTimeout of 42 symbols or 672 microseconds at 16 microseconds/symbol. +/// +/// @code{.c} +/// static RAIL_Handle_t railHandle = NULL; // Initialized somewhere else. +/// +/// static const RAIL_IEEE802154_Config_t rail154Config = { +/// .addresses = NULL, +/// .ackConfig = { +/// .enable = true, // Turn on auto ACK for IEEE 802.15.4. +/// .ackTimeout = 672, // See note above: 54-12 sym * 16 us/sym = 672 us. +/// .rxTransitions = { +/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing +/// .error = RAIL_RF_STATE_RX, // Ignored +/// }, +/// .txTransitions = { +/// .success = RAIL_RF_STATE_RX, // Return to RX after ACK processing +/// .error = RAIL_RF_STATE_RX, // Ignored +/// }, +/// }, +/// .timings = { +/// .idleToRx = 100, +/// .idleToTx = 100, +/// .rxToTx = 192, // 12 symbols * 16 us/symbol = 192 us +/// .txToRx = 192, // 12 symbols * 16 us/symbol = 192 us +/// .rxSearchTimeout = 0, // Not used +/// .txToRxSearchTimeout = 0, // Not used +/// }, +/// .framesMask = RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES, +/// .promiscuousMode = false, // Enable format and address filtering. +/// .isPanCoordinator = false, +/// .defaultFramePendingInOutgoingAcks = false, +/// }; +/// +/// void config154(void) +/// { +/// // Configure the radio and channels for 2.4 GHz IEEE 802.15.4. +/// RAIL_IEEE802154_Config2p4GHzRadio(railHandle); +/// // Initialize the IEEE 802.15.4 configuration using the static configuration above. +/// RAIL_IEEE802154_Init(railHandle, &rail154Config); +/// } +/// @endcode +/// +/// To configure address filtering, call +/// RAIL_IEEE802154_SetAddresses() with a structure containing all addresses or +/// call the individual RAIL_IEEE802154_SetPanId(), +/// RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress() +/// APIs. RAIL supports \ref RAIL_IEEE802154_MAX_ADDRESSES number of address +/// pairs to receive packets from multiple IEEE +/// 802.15.4 networks at the same time. Broadcast addresses are supported by +/// default without any additional configuration so they do not consume one of +/// these slots. If the application does not require all address pairs, be sure +/// to set unused ones to the proper disabled value for each type. These can +/// be found in the \ref RAIL_IEEE802154_AddrConfig_t documentation. Below is +/// an example of setting filtering for one set of addresses. +/// +/// @code{.c} +/// // PanID OTA value of 0x34 0x12. +/// // Short Address OTA byte order of 0x78 0x56. +/// // Long address with OTA byte order of 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88. +/// +/// // Set up all addresses simultaneously. +/// RAIL_Status_t setup1(void) +/// { +/// RAIL_IEEE802154_AddrConfig_t nodeAddress = { +/// { 0x1234, 0xFFFF, 0xFFFF }, +/// { 0x5678, 0xFFFF, 0xFFFF }, +/// { { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }, +/// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, +/// { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } } +/// }; +/// return RAIL_IEEE802154_SetAddresses(railHandle, &nodeAddress); +/// } +/// +/// // Alternatively, the addresses can be set up individually as follows: +/// RAIL_Status_t setup2(void) +/// { +/// RAIL_Status_t status; +/// const uint8_t longAddress[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 }; +/// +/// status = RAIL_IEEE802154_SetPanId(railHandle, 0x1234, 0); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return status +/// } +/// status = RAIL_IEEE802154_SetShortAddress(railHandle, 0x5678, 0); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return status +/// } +/// status = RAIL_IEEE802154_SetLongAddress(railHandle, longAddress, 0); +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return status +/// } +/// +/// return RAIL_STATUS_NO_ERROR; +/// } +/// @endcode +/// +/// Address filtering will be enabled except when in promiscuous mode, which can +/// be set with RAIL_IEEE802154_SetPromiscuousMode(). The addresses may be +/// changed at runtime. However, if you are receiving a packet while +/// reconfiguring the address filters, you may get undesired behavior so it's +/// safest to do this while not in receive. +/// +/// Auto ACK is controlled by the ackConfig and timings fields passed to +/// RAIL_IEEE802154_Init(). After initialization, they may be controlled +/// using the normal \ref Auto_Ack and \ref State_Transitions APIs. When in IEEE +/// 802.15.4 mode, the ACK will generally have a 5 byte length, its Frame Type +/// will be ACK, its Frame Version 0 (2003), and its Frame Pending bit will be +/// false unless the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event is +/// triggered in which case it will default to the +/// \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks setting. +/// If the default Frame Pending setting is incorrect, +/// the app must call \ref RAIL_IEEE802154_ToggleFramePending +/// (formerly \ref RAIL_IEEE802154_SetFramePending) while handling the +/// \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. +/// +/// This event must be turned on by the user and will fire whenever a data +/// request is being received so that the stack can determine if there +/// is pending data. Note that if the default Frame Pending bit needs to +/// be changed, it must be done quickly. Otherwise, the ACK may already +/// have been transmitted with the default setting. Check the return code of +/// RAIL_IEEE802154_ToggleFramePending() to be sure that the bit was changed +/// in time. +/// +/// Transmit and receive operations are done using the standard RAIL APIs in +/// IEEE 802.15.4 mode. To send packets using the correct CSMA configuration, +/// use \ref RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA define +/// that can initialize the csmaConfig structure passed to \ref +/// RAIL_StartCcaCsmaTx(). +/// @{ + +/** + * @enum RAIL_IEEE802154_AddressLength_t + * @brief Different lengths that an 802.15.4 address can have + */ +RAIL_ENUM(RAIL_IEEE802154_AddressLength_t) { + RAIL_IEEE802154_ShortAddress = 2, /**< 2 byte short address. */ + RAIL_IEEE802154_LongAddress = 3, /**< 8 byte extended address. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_IEEE802154_ShortAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_ShortAddress) +#define RAIL_IEEE802154_LongAddress ((RAIL_IEEE802154_AddressLength_t) RAIL_IEEE802154_LongAddress) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_IEEE802154_Address_t + * @brief Representation of 802.15.4 address + * This structure is only used for received source address information + * needed to perform Frame Pending lookup. + */ +typedef struct RAIL_IEEE802154_Address{ + /** Convenient storage for different address types. */ + union { + uint16_t shortAddress; /**< Present for 2 byte addresses. */ + uint8_t longAddress[8]; /**< Present for 8 byte addresses. */ + }; + /** + * Enumeration of the received address length. + */ + RAIL_IEEE802154_AddressLength_t length; + /** + * A bitmask representing which address filter(s) this packet has passed. + * It is undefined on platforms lacking \ref RAIL_SUPPORTS_ADDR_FILTER_MASK. + */ + RAIL_AddrFilterMask_t filterMask; +} RAIL_IEEE802154_Address_t; + +/** The maximum number of allowed addresses of each type. */ +#define RAIL_IEEE802154_MAX_ADDRESSES (3U) + +/** + * @struct RAIL_IEEE802154_AddrConfig_t + * @brief A configuration structure for IEEE 802.15.4 Address Filtering. The + * broadcast addresses are handled separately and do not need to be specified + * here. Any address to be ignored should be set with all bits high. + * + * This structure allows configuration of multi-PAN functionality by specifying + * multiple PAN IDs and short addresses. A packet will be received if it matches + * an address and its corresponding PAN ID. Long address 0 and short address 0 + * match against PAN ID 0, etc. The broadcast PAN ID and address will work with + * any address or PAN ID, respectively. + */ +typedef struct RAIL_IEEE802154_AddrConfig{ + /** + * PAN IDs for destination filtering. All must be specified. + * To disable a PAN ID, set it to the broadcast value, 0xFFFF. + */ + uint16_t panId[RAIL_IEEE802154_MAX_ADDRESSES]; + /** + * A short network addresses for destination filtering. All must be specified. + * To disable a short address, set it to the broadcast value, 0xFFFF. + */ + uint16_t shortAddr[RAIL_IEEE802154_MAX_ADDRESSES]; + /** + * A 64-bit address for destination filtering. All must be specified. + * This field is parsed in over-the-air (OTA) byte order. To disable a long + * address, set it to the reserved value of 0x00 00 00 00 00 00 00 00. + */ + uint8_t longAddr[RAIL_IEEE802154_MAX_ADDRESSES][8]; +} RAIL_IEEE802154_AddrConfig_t; + +/** + * @struct RAIL_IEEE802154_Config_t + * @brief A configuration structure for IEEE 802.15.4 in RAIL. + * + * @note 802.15.4 radio configurations with Forward Error Correction (FEC) + * enabled are incompatible with 802.15.4 filtering and AutoACK on + * EFR32xG1 platforms. + * AutoACK should be disabled and promiscuous mode enabled when using such + * a configuration. This is enforced implicitly on EFR32xG1 platforms with + * \ref RAIL_IEEE802154_SUPPORTS_G_DYNFEC true when + * \ref RAIL_IEEE802154_ConfigGOptions() is called to enable any G options. + */ +typedef struct RAIL_IEEE802154_Config { + /** + * Configure the RAIL Address Filter to allow the given destination + * addresses. If this pointer is NULL, defer destination address configuration. + * If a member of addresses is NULL, defer configuration of just that member. + * This can be overridden via RAIL_IEEE802154_SetAddresses(), or the + * individual members can be changed via RAIL_IEEE802154_SetPanId(), + * RAIL_IEEE802154_SetShortAddress(), and RAIL_IEEE802154_SetLongAddress(). + */ + const RAIL_IEEE802154_AddrConfig_t *addresses; + /** + * Define the ACKing configuration for the IEEE 802.15.4 implementation. + */ + RAIL_AutoAckConfig_t ackConfig; + /** + * Define state timings for the IEEE 802.15.4 implementation. + */ + RAIL_StateTiming_t timings; + /** + * Set which 802.15.4 frame types will be received, of Beacon, Data, ACK, and + * Command. This setting can be overridden via RAIL_IEEE802154_AcceptFrames(). + */ + uint8_t framesMask; + /** + * Enable promiscuous mode during configuration. This can be overridden via + * RAIL_IEEE802154_SetPromiscuousMode() afterwards. + */ + bool promiscuousMode; + /** + * Set whether the device is a PAN Coordinator during configuration. This can + * be overridden via RAIL_IEEE802154_SetPanCoordinator() afterwards. + */ + bool isPanCoordinator; + /** + * The default value for the Frame Pending bit in outgoing ACKs for packets + * that triggered the \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. + * Such an ACK's Frame Pending bit can be inverted if necessary during the + * handling of that event by calling \ref RAIL_IEEE802154_ToggleFramePending + * (formerly \ref RAIL_IEEE802154_SetFramePending). + */ + bool defaultFramePendingInOutgoingAcks; +} RAIL_IEEE802154_Config_t; + +/** RX channel switching buffer size, in bytes. */ +#ifdef SLI_LIBRARY_BUILD +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (704U) // largest of below +#else//!SLI_LIBRARY_BUILD +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (704U) +#elif (_SILICON_LABS_32B_SERIES_2_CONFIG == 4) +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (640U) +#else// RX channel switching not supported +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES (0U) +#endif +#endif//SLI_LIBRARY_BUILD + +/** Fixed-width type indicating the needed alignment for RX channel switching buffer. */ +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE uint32_t + +/** Alignment that is needed for RX channel switching buffer. */ +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT (sizeof(RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE)) + +/** Maximum numbers of channels supported for RX channel switching */ +#define RAIL_IEEE802154_RX_CHANNEL_SWITCHING_NUM_CHANNELS (2U) + +/** + * @struct RAIL_IEEE802154_RxChannelSwitchingCfg_t + * @brief A configuration structure for RX channel switching. + */ +typedef struct RAIL_IEEE802154_RxChannelSwitchingCfg { + /** + * Pointer to contiguous global read-write memory that will be used + * by RAIL to store channel specific settings for concurrent listening. + * It need not be initialized and applications should never write + * data anywhere in this buffer. + * + * @note the size of this buffer must be at least as large as the + * \ref RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_BYTES and needs to be word + * aligned. + */ + RAIL_IEEE802154_RX_CHANNEL_SWITCHING_BUF_ALIGNMENT_TYPE *buffer; + /** + * This parameter must be set to the length of the buffer array, in bytes. + * This way, during configuration, the software can confirm it's + * writing within the range of the buffer. The configuration API will return + * an error if bufferBytes is insufficient. + */ + uint16_t bufferBytes; + /** + * Array to hold the channel numbers for RX channel switching. + * @note Radio will switch between the exact channels specified, and not + * across an inclusive range of channels between the specified channels. + */ + uint16_t channels[RAIL_IEEE802154_RX_CHANNEL_SWITCHING_NUM_CHANNELS]; +} RAIL_IEEE802154_RxChannelSwitchingCfg_t; + +/// @addtogroup IEEE802154_PHY IEEE 802.15.4 Radio Configurations +/// Radio configurations for the RAIL 802.15.4 Accelerator +/// +/// These radio configurations are used to configure 802.15.4 when a function +/// such as \ref RAIL_IEEE802154_Config2p4GHzRadio() is called. Each radio +/// configuration listed below is compiled into the RAIL library as a weak +/// symbol that will take into account per-die defaults. If the board +/// configuration in use has different settings than the default, such as a +/// different radio subsystem clock frequency, these radio configurations can +/// be overridden to account for those settings. +/// @{ + +/** + * Default PHY to use for 2.4 GHz 802.15.4. Will be NULL if + * \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154 or \ref RAIL_SUPPORTS_2P4GHZ_BAND + * is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Default PHY to use for 1Mbps 2.4 GHz 802.15.4 with forward error correction. + * Will be NULL if \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz1MbpsFec; + +/** + * Default PHY to use for 2Mbps 2.4 GHz 802.15.4. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_2MBPS_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHz2Mbps; +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with antenna diversity. Will be NULL + * if \ref RAIL_SUPPORTS_PROTOCOL_IEEE802154, \ref RAIL_SUPPORTS_2P4GHZ_BAND, or + * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDiv; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 optimized for coexistence. Will be + * NULL if \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoex; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 optimized for coexistence, while + * supporting antenna diversity. Will be NULL if + * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY or + * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoex; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a + * front-end module. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzFem; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a + * front-end module and antenna diversity. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY or \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY + * is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivFem; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a + * front-end module and is optimized for radio coexistence. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY or + * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCoexFem; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with a configuration that supports a + * front-end module and antenna diversity, and is optimized for radio + * coexistence. Will be NULL if \ref RAIL_IEEE802154_SUPPORTS_FEM_PHY, + * \ref RAIL_IEEE802154_SUPPORTS_COEX_PHY, or + * \ref RAIL_SUPPORTS_ANTENNA_DIVERSITY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzAntDivCoexFem; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with custom settings. Will be NULL + * if \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzCustom1; + +/** + * Default PHY to use for 863MHz GB868 802.15.4. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB863MHz; + +/** + * Default PHY to use for 915MHz GB868 802.15.4. Will be NULL if + * \ref RAIL_IEEE802154_SUPPORTS_G_SUBSET_GB868 is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_PhyGB915MHz; + +/** + * Default PHY to use for 2.4 GHz 802.15.4 with RX channel switching. Will be + * NULL if \ref RAIL_IEEE802154_SUPPORTS_RX_CHANNEL_SWITCHING is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_IEEE802154_Phy2p4GHzRxChSwitching; + +/// @} // End of group IEEE802154_PHY + +/** + * Initialize RAIL for IEEE802.15.4 features. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] config An IEEE802154 configuration structure. + * @return A status code indicating success of the function call. + * + * This function calls the following RAIL functions to configure the radio for + * IEEE802.15.4 features. + * + * Initializes the following: + * - Enables IEEE802154 hardware acceleration + * - Configures RAIL Auto ACK functionality + * - Configures RAIL Address Filter for 802.15.4 address filtering + * + * It saves having to call the following functions individually: + * - RAIL_ConfigAutoAck() + * - RAIL_SetRxTransitions() + * - RAIL_SetTxTransitions() + * - RAIL_WriteAutoAckFifo() + * - RAIL_SetStateTiming() + * - RAIL_ConfigAddressFilter() + * - RAIL_EnableAddressFilter() + * + * It must be called before most of RAIL_IEEE802154_* function. + */ +RAIL_Status_t RAIL_IEEE802154_Init(RAIL_Handle_t railHandle, + const RAIL_IEEE802154_Config_t *config); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports antenna diversity. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDiv(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity + * optimized for radio coexistence. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports antenna diversity optimized for radio coexistence. It takes + * the place of calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoex(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports radio coexistence. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoex(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with a front end module. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports a front end module. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioFem(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity + * optimized for a front end module. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports antenna diversity and a front end module. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivFem(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation optimized for radio coexistence + * and a front end module. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports radio coexistence and a front end module. It takes the place of + * calling \ref RAIL_ConfigChannels. After this call, + * channels 11-26 will be available, giving the frequencies of those channels + * on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCoexFem(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with antenna diversity + * optimized for radio coexistence and a front end module. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation, but with a configuration + * that supports antenna diversity, radio coexistence and a front end module. + * It takes the place of calling \ref RAIL_ConfigChannels. + * After this call, channels 11-26 will be available, giving the frequencies of + * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioAntDivCoexFem(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/2Mbps operation. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz high speed operation. + * It takes the place of calling \ref RAIL_ConfigChannels. + * After this call, channels 11-26 will be available, giving the frequencies of + * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 + * at 250kbps. + * Channels 11-26 will support transmitting and receiving using dual sync words. + * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 2Mbps. + * Auto-ack and address filtering are disabled when channels 27-42 are selected. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio2Mbps(RAIL_Handle_t railHandle); + +/** + * Configure the radio for 2.4 GHz 802.15.4 for 250kbps/1Mbps forward error correction + * operation. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz high speed operation. + * It takes the place of calling \ref RAIL_ConfigChannels. + * After this call, channels 11-26 will be available, giving the frequencies of + * those channels on channel page 0, as defined by IEEE 802.15.4-2011 section 8.1.2.2 + * at 250kbps. + * Channels 11-26 will support transmitting and receiving using dual sync words. + * Channels 27-42 will transmit and receive on the frequency of [channel - 16] at 1Mbps. + * Auto-ack and address filtering are disabled when channels 27-42 are selected. + * + * @note This call implicitly disables all \ref RAIL_IEEE802154_GOptions_t. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadio1MbpsFec(RAIL_Handle_t railHandle); + +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Configure the radio for 2.4 GHz 802.15.4 operation with custom + * settings. It enables better interoperability with some proprietary + * PHYs, but doesn't guarantee data sheet performance. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for 2.4 GHz operation with + * custom settings. It replaces needing to call + * \ref RAIL_ConfigChannels. + * Do not call this function unless instructed by Silicon Labs. + * + * @note This feature is only available on platforms where + * \ref RAIL_IEEE802154_SUPPORTS_CUSTOM1_PHY is true. + */ +RAIL_Status_t RAIL_IEEE802154_Config2p4GHzRadioCustom1(RAIL_Handle_t railHandle); + +/** + * Configure the radio for SubGHz GB868 863 MHz 802.15.4 operation. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for SubGHz GB868 863 MHz operation. It takes the + * place of calling \ref RAIL_ConfigChannels. + * After this call, GB868 channels in the 863 MHz band (channel pages 28, 29, + * and 30 -- logical channels 0x80..0x9A, 0xA0..0xA8, 0xC0..0xDA, respectively) + * will be available, as defined by Rev 22 of the Zigbee Specification, 2017 + * document 05-3474-22, section D.10.2.1.3.2. + * + * @note This call implicitly enables \ref RAIL_IEEE802154_G_OPTION_GB868. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigGB863MHzRadio(RAIL_Handle_t railHandle); + +/** + * Configure the radio for SubGHz GB868 915 MHz 802.15.4 operation. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * This initializes the radio for SubGHz GB868 915 MHz operation. It takes the + * place of calling \ref RAIL_ConfigChannels. + * After this call, GB868 channels in the 915 MHz band (channel page 31 -- + * logical channels 0xE0..0xFA) will be available, as defined by Rev 22 of + * the Zigbee Specification, 2017 document 05-3474-22, section D.10.2.1.3.2. + * + * @note This call implicitly enables \ref RAIL_IEEE802154_G_OPTION_GB868. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigGB915MHzRadio(RAIL_Handle_t railHandle); + +/** + * De-initialize IEEE802.15.4 hardware acceleration. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * Disables and resets all IEE802.15.4 hardware acceleration features. This + * function should only be called when the radio is IDLE. This calls the + * following: + * - RAIL_SetStateTiming(), to reset all timings to 100 us + * - RAIL_EnableAddressFilter(false) + * - RAIL_ResetAddressFilter() + */ +RAIL_Status_t RAIL_IEEE802154_Deinit(RAIL_Handle_t railHandle); + +/** + * Return whether IEEE802.15.4 hardware acceleration is currently enabled. + * + * @param[in] railHandle A handle of RAIL instance. + * @return True if IEEE802.15.4 hardware acceleration was enabled to start with + * and false otherwise. + */ +bool RAIL_IEEE802154_IsEnabled(RAIL_Handle_t railHandle); + +/** + * @enum RAIL_IEEE802154_PtiRadioConfig_t + * @brief 802.15.4 PTI radio configuration mode + */ +RAIL_ENUM_GENERIC(RAIL_IEEE802154_PtiRadioConfig_t, uint16_t) { + /** + * Built-in 2.4 GHz 802.15.4 radio configuration. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ = 0x00U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration + * with RX antenna diversity support. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV = 0x01U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration + * optimized for radio coexistence. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX = 0x02U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration with + * RX antenna diversity support optimized for radio coexistence. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX = 0x03U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration + * optimized for front end modules. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM = 0x08U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration + * with RX antenna diversity support optimized for + * front end modules. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_ANTDIV = 0x09U, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration + * optimized for radio coexistence and front end modules. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_COEX = 0x0AU, + /** + * Built-in 2.4 GHz 802.15.4 radio configuration with + * RX antenna diversity support optimized for radio coexistence + * and front end modules. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_FEM_ANTDIV_COEX = 0x0BU, + /** + * Built-in 863 MHz GB868 802.15.4 radio configuration. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 = 0x85U, + /** + * Built-in 915 MHz GB868 802.15.4 radio configuration. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 = 0x86U, + /** + * External 915 MHz Zigbee R23 802.15.4 NA radio configuration. + */ + RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT = 0x97U, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_COEX) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_2P4GHZ_ANTDIV_COEX) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_863MHZ_GB868) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868 ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_GB868) +#define RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT ((RAIL_IEEE802154_PtiRadioConfig_t) RAIL_IEEE802154_PTI_RADIO_CONFIG_915MHZ_R23_NA_EXT) +#endif//DOXYGEN_SHOULD_SKIP_THIS + +/** + * Return IEEE802.15.4 PTI radio config. + * + * @param[in] railHandle A handle of RAIL instance. + * @return PTI (Packet Trace Information) radio config ID. + */ +RAIL_IEEE802154_PtiRadioConfig_t RAIL_IEEE802154_GetPtiRadioConfig(RAIL_Handle_t railHandle); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Set IEEE802.15.4 PTI radio config (for Silicon Labs internal use only). + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] ptiRadioConfig PTI (Packet Trace Information) radio config ID. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_IEEE802154_SetPtiRadioConfig(RAIL_Handle_t railHandle, + RAIL_IEEE802154_PtiRadioConfig_t ptiRadioConfigId); +#endif + +/** + * Configure the RAIL Address Filter for 802.15.4 filtering. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] addresses The address information that should be used. + * @return A status code indicating success of the function call. If this returns + * an error, the 802.15.4 address filter is in an undefined state. + * + * Set up the 802.15.4 address filter to accept messages to the given + * addresses. This will return false if any of the addresses failed to be set. + * If NULL is passed in for addresses, all addresses will be set to their + * reset value. + */ +RAIL_Status_t RAIL_IEEE802154_SetAddresses(RAIL_Handle_t railHandle, + const RAIL_IEEE802154_AddrConfig_t *addresses); + +/** + * Set a PAN ID for 802.15.4 address filtering. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] panId The 16-bit PAN ID information. + * This will be matched against the destination PAN ID of incoming messages. + * The PAN ID is sent little endian over the air, meaning panId[7:0] is first in + * the payload followed by panId[15:8]. Set to 0xFFFF to disable for this index. + * @param[in] index Indicates which PAN ID to set. Must be below + * RAIL_IEEE802154_MAX_ADDRESSES. + * @return A status code indicating success of the function call. + * + * Set up the 802.15.4 address filter to accept messages to the given PAN ID. + */ +RAIL_Status_t RAIL_IEEE802154_SetPanId(RAIL_Handle_t railHandle, + uint16_t panId, + uint8_t index); + +/** + * Set a short address for 802.15.4 address filtering. + * + * @param[in] railHandle A handle of RAIL instance + * @param[in] shortAddr 16 bit short address value. This will be matched against the + * destination short address of incoming messages. The short address is sent + * little endian over the air meaning shortAddr[7:0] is first in the payload + * followed by shortAddr[15:8]. Set to 0xFFFF to disable for this index. + * @param[in] index Which short address to set. Must be below + * RAIL_IEEE802154_MAX_ADDRESSES. + * @return A status code indicating success of the function call. + * + * Set up the 802.15.4 address filter to accept messages to the given short + * address. + */ +RAIL_Status_t RAIL_IEEE802154_SetShortAddress(RAIL_Handle_t railHandle, + uint16_t shortAddr, + uint8_t index); + +/** + * Set a long address for 802.15.4 address filtering. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] longAddr A pointer to an 8-byte array containing the long address + * information. The long address must be in over-the-air byte order. This will + * be matched against the destination long address of incoming messages. Set to + * 0x00 00 00 00 00 00 00 00 to disable for this index. + * @param[in] index Indicates which long address to set. Must be below + * RAIL_IEEE802154_MAX_ADDRESSES. + * @return A status code indicating success of the function call. + * + * Set up the 802.15.4 address filter to accept messages to the given long + * address. + */ +RAIL_Status_t RAIL_IEEE802154_SetLongAddress(RAIL_Handle_t railHandle, + const uint8_t *longAddr, + uint8_t index); + +/** + * Set whether the current node is a PAN coordinator. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] isPanCoordinator True if this device is a PAN coordinator. + * @return A status code indicating success of the function call. + * + * If the device is a PAN Coordinator, it will accept data and command + * frames with no destination address. This function will fail if 802.15.4 + * hardware acceleration is not currently enabled by calling + * \ref RAIL_IEEE802154_Init(). This setting may be changed + * at any time when 802.15.4 hardware acceleration is enabled. + */ +RAIL_Status_t RAIL_IEEE802154_SetPanCoordinator(RAIL_Handle_t railHandle, + bool isPanCoordinator); + +/** + * Set whether to enable 802.15.4 promiscuous mode. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] enable True if all frames and addresses should be accepted. + * @return A status code indicating success of the function call. + * + * If promiscuous mode is enabled, no frame or address filtering steps + * will be performed other than checking the CRC. This function will fail if + * 802.15.4 hardware acceleration is not currently enabled by calling + * \ref RAIL_IEEE802154_Init(). This setting may be changed at any time when + * 802.15.4 hardware acceleration is enabled. + */ +RAIL_Status_t RAIL_IEEE802154_SetPromiscuousMode(RAIL_Handle_t railHandle, + bool enable); + +/** + * @enum RAIL_IEEE802154_EOptions_t + * @brief 802.15.4E-2012 options, in reality a bitmask. + */ +RAIL_ENUM_GENERIC(RAIL_IEEE802154_EOptions_t, uint32_t) { + /** Shift position of \ref RAIL_IEEE802154_E_OPTION_GB868 bit. */ + RAIL_IEEE802154_E_OPTION_GB868_SHIFT = 0, + RAIL_IEEE802154_E_OPTION_ENH_ACK_SHIFT, + RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST_SHIFT, +}; + +/** A value representing no options enabled. */ +#define RAIL_IEEE802154_E_OPTIONS_NONE 0UL +/** All options disabled by default . */ +#define RAIL_IEEE802154_E_OPTIONS_DEFAULT RAIL_IEEE802154_E_OPTIONS_NONE + +/** + * An option to enable/disable 802.15.4E-2012 features needed for GB868. + * When not promiscuous, RAIL normally accepts only 802.15.4 MAC frames + * whose MAC header Frame Version is 0 (802.15.4-2003) or 1 (802.15.4-2006), + * filtering out higher Frame Version packets (as \ref + * RAIL_RX_PACKET_ABORT_FORMAT). + * Enabling this feature additionally allows Frame Version 2 (802.15.4E-2012 / + * 802.15.4-2015) packets to be accepted and passed to the application. + * + * @note Enabling this feature also automatically enables \ref + * RAIL_IEEE802154_E_OPTION_ENH_ACK on platforms that support + * that feature. + * + * @note This feature does not automatically enable receiving Multipurpose + * frames; that can be enabled via RAIL_IEEE802154_AcceptFrames()'s + * \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES. + */ +#define RAIL_IEEE802154_E_OPTION_GB868 (1UL << RAIL_IEEE802154_E_OPTION_GB868_SHIFT) + +/** + * An option to enable/disable 802.15.4E-2012 features needed for Enhanced ACKs. + * This option requires that \ref RAIL_IEEE802154_E_OPTION_GB868 also be + * enabled, and is enabled automatically on platforms that support this + * feature. It exists as a separate flag to allow runtime detection of whether + * the platform supports this feature or not. + * + * When enabled, only an Enhanced ACK is expected in response to a transmitted + * ACK-requesting 802.15.4E Version 2 frame. RAIL only knows how to construct + * 802.15.4 Immediate ACKs but not Enhanced ACKs. + * + * This option causes \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND to be + * issued for ACK-requesting Version 2 MAC Command frames, Data frames + * (if \ref RAIL_IEEE802154_EnableDataFramePending() is enabled), and + * Multipurpose Frames (if \ref RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES + * is enabled). + * + * The application is expected to handle this event by calling \ref + * RAIL_GetRxIncomingPacketInfo() and parsing the partly-received incoming + * frame to determine the type of ACK needed: + * - If an Immediate ACK, determine Frame Pending needs based on the packet + * type and addressing information and call \ref + * RAIL_IEEE802154_ToggleFramePending() if necessary; + * - If an Enhanced ACK, generate the complete payload of the Enhanced ACK + * including any Frame Pending information and call \ref + * RAIL_IEEE802154_WriteEnhAck() in time for that Enhanced ACK to + * be sent. If not called in time, \ref RAIL_EVENT_TXACK_UNDERFLOW will + * likely result. + * Note that if 802.15.4 MAC-level encryption is used with Version 2 + * frames, the application should decrypt the MAC Command byte in a + * MAC Command frame to determine whether it is a Data Request or other + * MAC Command. + * + * An application can also enable \ref + * RAIL_IEEE802154_EnableEarlyFramePending() if the protocol doesn't + * need to examine the MAC Command byte of MAC Command frames but can + * infer it to be a Data Request. + * + * On 802.15.4E GB868 platforms that lack this support, legacy Immediate ACKs + * are sent/expected for received/transmitted ACK-requesting 802.15.4E Frame + * Version 2 frames; calls to \ref RAIL_IEEE802154_WriteEnhAck() have no + * effect. Attempting to use this feature via \ref + * RAIL_IEEE802154_ConfigEOptions() returns an error. + */ +#define RAIL_IEEE802154_E_OPTION_ENH_ACK (1UL << RAIL_IEEE802154_E_OPTION_ENH_ACK_SHIFT) + +/** + * An option to enable/disable 802.15.4E-2012 macImplicitBroadcast feature. + * + * When enabled, received Frame Version 2 frames without a destination + * PAN ID or destination address are treated as though they are addressed + * to the broadcast PAN ID and broadcast short address. When disabled, such + * frames are filtered unless the device is the PAN coordinator and + * appropriate source addressing information exists in the packet + */ +#define RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST (1UL << RAIL_IEEE802154_E_OPTION_IMPLICIT_BROADCAST_SHIFT) + +/** A value representing all possible options. */ +#define RAIL_IEEE802154_E_OPTIONS_ALL 0xFFFFFFFFUL + +/** + * Configure certain 802.15.4E-2012 / 802.15.4-2015 Frame Version 2 features. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] mask A bitmask containing which options should be modified. + * @param[in] options A bitmask containing desired options settings. + * Bit positions for each option are found in the \ref + * RAIL_IEEE802154_EOptions_t. + * @return A status code indicating success of the function call. + * + * This function will fail if 802.15.4 hardware acceleration is not + * currently enabled by calling \ref RAIL_IEEE802154_Init() or the platform + * does not support the feature(s). + * These settings may be changed at any time when 802.15.4 hardware + * acceleration is enabled. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigEOptions(RAIL_Handle_t railHandle, + RAIL_IEEE802154_EOptions_t mask, + RAIL_IEEE802154_EOptions_t options); + +/** + * @enum RAIL_IEEE802154_GOptions_t + * @brief 802.15.4G-2012 options, in reality a bitmask. + */ +RAIL_ENUM_GENERIC(RAIL_IEEE802154_GOptions_t, uint32_t) { + /** Shift position of \ref RAIL_IEEE802154_G_OPTION_GB868 bit. */ + RAIL_IEEE802154_G_OPTION_GB868_SHIFT = 0, + /** Shift position of \ref RAIL_IEEE802154_G_OPTION_DYNFEC bit. */ + RAIL_IEEE802154_G_OPTION_DYNFEC_SHIFT, + /** Shift position of \ref RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH bit. */ + RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH_SHIFT, +}; + +/** A value representing no options enabled. */ +#define RAIL_IEEE802154_G_OPTIONS_NONE 0UL +/** All options disabled by default . */ +#define RAIL_IEEE802154_G_OPTIONS_DEFAULT RAIL_IEEE802154_G_OPTIONS_NONE + +/** + * An option to enable/disable 802.15.4G-2012 features needed for GB868. + * Normally RAIL supports 802.15.4-2003 and -2006 radio configurations + * that have the single-byte PHY header allowing frames up to 128 bytes + * in size. This feature must be enabled for 802.15.4G-2012 or + * 802.15.4-2015 SUN PHY radio configurations with the two-byte + * bit-reversed-length PHY header format. + * + * While GB868 only supports whitened non-FEC non-mode-switch frames + * up to 129 bytes including 2-byte CRC, this option also enables: + * - On platforms where \ref RAIL_FEAT_IEEE802154_G_4BYTE_CRC_SUPPORTED + * is true: automatic per-packet 2/4-byte Frame Check Sequence (FCS) + * reception and transmission based on the FCS Type bit in the + * received/transmitted PHY header. This includes ACK reception + * and automatically-generated ACKs reflect the CRC size of the + * incoming frame being acknowledged (i.e., their MAC payload will be + * increased to 7 bytes when sending 4-byte FCS). + * On other platforms, only the 2-byte FCS is supported. + * - On platforms where \ref RAIL_FEAT_IEEE802154_G_UNWHITENED_RX_SUPPORTED + * and/or \ref RAIL_FEAT_IEEE802154_G_UNWHITENED_TX_SUPPORTED are true: + * automatic per-packet whitened/unwhitened reception and transmission, + * respectively, based on the Data Whitening bit in the received/transmitted + * PHY header. This includes ACK reception and automatically-generated ACKs + * which reflect the whitening of the incoming frame being acknowledged. + * On other platforms, only whitened frames are supported. + * - Support for frames up to 2049 bytes per the radio configuration's + * maximum packet length setting. + * + * @note Sending/receiving whitened frames assumes the radio configuration + * has established an appropriate 802.15.4-compliant whitening algorithm. + * RAIL does not itself override the radio configuration's whitening + * settings other than to enable/disable it per-packet based on the + * packet's PHY header Data Whitening flag. + */ +#define RAIL_IEEE802154_G_OPTION_GB868 (1UL << RAIL_IEEE802154_G_OPTION_GB868_SHIFT) +/** + * An option to enable/disable 802.15.4G dynamic FEC feature (SUN FSK only). + * The syncWord, called start-of-frame delimiter (SFD) in the 15.4 spec, indicates whether + * the rest of the packet is FEC encoded or not. This feature requires per-packet + * dual syncWord detection and specific receiver pausing. + * Note that this feature is only available on platforms where + * \ref RAIL_IEEE802154_SUPPORTS_G_DYNFEC is true. + * + * This option is only valid for SUN PHYs that have the FEC configured and enabled. + * + * The syncWord used during transmit is selected with \ref RAIL_TX_OPTION_SYNC_WORD_ID. + * + * The syncWord corresponding to the FEC encoded mode must be SYNC1, with SYNC2 indicating non-FEC. + * SyncWords are set appropriately in all Sun FEC-enabled PHYs so there should + * never be a need to call \ref RAIL_ConfigSyncWords() when this option is enabled. + * + * Also, dual syncWord detection is set in all SUN FEC enabled PHYs, then there is no need + * to change \ref RAIL_RX_OPTION_ENABLE_DUALSYNC . + * + * @note EFR32xG12 support for 802.15.4 FEC-capable PHYs and dynamic FEC + * are incompatible with 802.15.4 filtering and AutoACK. + * \ref RAIL_IEEE802154_Config_t::promiscuousMode must be true and \ref + * RAIL_IEEE802154_Config_t::ackConfig's \ref RAIL_AutoAckConfig_t.enable + * must be false on these platforms when using a FEC-capable PHY. + */ +#define RAIL_IEEE802154_G_OPTION_DYNFEC (1UL << RAIL_IEEE802154_G_OPTION_DYNFEC_SHIFT) +/** + * An option to enable/disable Wi-SUN Mode Switch feature. + * This feature consists in switching to a new PHY mode with a higher rate typically + * by sending/receiving a specific Mode Switch packet that indicates the incoming new PHY mode. + * The Mode Switch packet is an FSK-modulated 2-byte PHY header with no payload. + * Because this feature relies on specific receiver pausing, note that it is only available + * on platforms where \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true. + */ +#define RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH (1UL << RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH_SHIFT) + +/** A value representing all possible options. */ +#define RAIL_IEEE802154_G_OPTIONS_ALL 0xFFFFFFFFUL + +/** + * Configure certain 802.15.4G-2012 / 802.15.4-2015 SUN PHY features + * (only for radio configurations designed accordingly). + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] mask A bitmask containing which options should be modified. + * @param[in] options A bitmask containing desired options settings. + * Bit positions for each option are found in the \ref + * RAIL_IEEE802154_GOptions_t. + * @return A status code indicating success of the function call. + * + * This function will fail if 802.15.4 hardware acceleration is not + * currently enabled by calling \ref RAIL_IEEE802154_Init(), the platform does + * not support the feature(s), the radio configuration is not appropriate, + * or the radio is not idle. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigGOptions(RAIL_Handle_t railHandle, + RAIL_IEEE802154_GOptions_t mask, + RAIL_IEEE802154_GOptions_t options); + +/** + * @struct RAIL_IEEE802154_ModeSwitchPhr_t + * @brief A structure containing the PHYModeID value and the corresponding mode + * switch PHR as defined in Wi-SUN spec. + * These structures are usually generated by the radio configurator. + */ +typedef struct RAIL_IEEE802154_ModeSwitchPhr { + uint8_t phyModeId; /**< PHY mode Id */ + uint16_t phr; /**< Corresponding Mode Switch PHY header */ +} RAIL_IEEE802154_ModeSwitchPhr_t; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** When filtering PhyModeId, this is the minimum OFDM value */ +#define MIN_OFDM_PHY_MODE_ID (0x20U) +/** When filtering PhyModeId, this is the maximum OFDM value */ +#define MAX_OFDM_PHY_MODE_ID (0x5FU) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Compute channel to switch to given a targeted PhyMode ID + * in the context of Wi-SUN mode switching. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] newPhyModeId A targeted PhyMode ID. + * @param[out] pChannel A pointer to the channel to switch to. + * @return A status code indicating success of the function call. + * + * This function will fail if: + * - the targeted PhyModeID is the same as the current PhyMode ID + * - called on a platform that lacks \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH + * - called on a platform that doesn't have 802154G options enabled + * by \ref RAIL_IEEE802154_ConfigGOptions(). + * For newPhyModeId associated with a FSK FEC_off PHY, if dynamic FEC is + * activated (see \ref RAIL_IEEE802154_G_OPTION_DYNFEC), the returned + * channel can correspond to the associated FSK FEC_on PHY corresponding + * then to PhyModeID = newPhyModeId + 16 + */ +RAIL_Status_t RAIL_IEEE802154_ComputeChannelFromPhyModeId(RAIL_Handle_t railHandle, + uint8_t newPhyModeId, + uint16_t *pChannel); + +/** + * Manage forbidden channels during mode switch. + * + * @param[in] currentBaseFreq The current frequency of the base channel. + * @param[in] newPhyModeId A targeted PhyMode ID. + * @param[in] configEntryNewPhyModeId A pointer to \ref RAIL_ChannelConfigEntry_t + * structure corresponding to the new PHY configEntry. + * @param[in, out] pChannel A pointer to the channel to switch to. If channel + * is valid, the function must just return. If channel is forbidden, the + * function must update it with the closest valid channel. The highest + * channel must be selected in case of two valid channels being equidistant + * to a forbidden channel. + * @return A status code indicating success of the function call. It must + * return RAIL_STATUS_INVALID_PARAMETER for failure or RAIL_STATUS_NO_ERROR + * for success. + * + * This function must fail if no valid channel has been found. If so, RAIL will + * abort the mode switch. + * + * @note This callback will only be called on platforms where + * \ref RAIL_IEEE802154_SUPPORTS_G_MODESWITCH is true, \ref + * RAIL_IEEE802154_G_OPTION_WISUN_MODESWITCH was successfully enabled, + * and a valid mode switch PHY header is received. + */ +RAIL_Status_t RAILCb_IEEE802154_IsModeSwitchNewChannelValid(uint32_t currentBaseFreq, + uint8_t newPhyModeId, + const RAIL_ChannelConfigEntry_t *configEntryNewPhyModeId, + uint16_t *pChannel); + +/// When receiving packets, accept 802.15.4 BEACON frame types. +#define RAIL_IEEE802154_ACCEPT_BEACON_FRAMES (0x01) +/// When receiving packets, accept 802.15.4 DATA frame types. +#define RAIL_IEEE802154_ACCEPT_DATA_FRAMES (0x02) +/// When receiving packets, accept 802.15.4 ACK frame types. +/// @note Expected ACK frame types will still be accepted regardless +/// of this setting when waiting for an ACK after a transmit that +/// used \ref RAIL_TX_OPTION_WAIT_FOR_ACK and auto-ACK is enabled. +#define RAIL_IEEE802154_ACCEPT_ACK_FRAMES (0x04) +/// When receiving packets, accept 802.15.4 COMMAND frame types. +#define RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES (0x08) +// Reserved for possible future use: (0x10) +/// When receiving packets, accept 802.15.4-2015 Multipurpose frame types. +/// (Not supported on EFR32XG1.) +#define RAIL_IEEE802154_ACCEPT_MULTIPURPOSE_FRAMES (0x20) + +/// In standard operation, accept BEACON, DATA and COMMAND frames. +/// Don't receive ACK frames unless waiting for ACK (i.e., only +/// receive expected ACKs). +#define RAIL_IEEE802154_ACCEPT_STANDARD_FRAMES (RAIL_IEEE802154_ACCEPT_BEACON_FRAMES \ + | RAIL_IEEE802154_ACCEPT_DATA_FRAMES \ + | RAIL_IEEE802154_ACCEPT_COMMAND_FRAMES) + +/** + * Set which 802.15.4 frame types to accept. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] framesMask A mask containing which 802.15.4 frame types to receive. + * @return A status code indicating success of the function call. + * + * This function will fail if 802.15.4 hardware acceleration is not currently + * enabled by calling \ref RAIL_IEEE802154_Init() or framesMask requests an + * unsupported frame type. + * This setting may be changed at any time when 802.15.4 hardware + * acceleration is enabled. Only Beacon, Data, ACK, Command, and Multipurpose + * (except on EFR32XG1) frames may be received. + * The RAIL_IEEE802154_ACCEPT_XXX_FRAMES defines may be combined to create a + * bitmask to pass into this function. + * + * \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES behaves slightly different than the + * other defines. If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is set, the radio + * will accept an ACK frame during normal packet reception, but only a + * truly expected ACK will have its \ref RAIL_RxPacketDetails_t::isAck true. + * If \ref RAIL_IEEE802154_ACCEPT_ACK_FRAMES is not set, ACK frames will be + * filtered unless they're expected when the radio is waiting for an ACK. + */ +RAIL_Status_t RAIL_IEEE802154_AcceptFrames(RAIL_Handle_t railHandle, + uint8_t framesMask); + +/** + * Enable early Frame Pending lookup event notification + * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND). + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] enable True to enable, false to disable. + * @return A status code indicating success of the function call. + * + * Normally, \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered after + * receiving the entire MAC header and MAC command byte for an ACK-requesting + * MAC command frame. Version 0/1 frames also require that command to be a + * Data Request for this event to occur. + * Enabling this feature causes this event to be triggered earlier to allow for + * more time to determine the type of ACK needed (Immediate or Enhanced) and/or + * perform frame pending lookup to influence the outgoing ACK by using \ref + * RAIL_IEEE802154_WriteEnhAck() or \ref RAIL_IEEE802154_ToggleFramePending(). + * + * For Frame Version 0/1 packets and for Frame Version 2 packets when \ref + * RAIL_IEEE802154_E_OPTION_ENH_ACK is not in use, "early" means right + * after receiving the source address information in the MAC header. + * + * For Frame Version 2 packets when \ref RAIL_IEEE802154_E_OPTION_ENH_ACK + * is in use, "early" means right after receiving any Auxiliary Security + * header which follows the source address information in the MAC header. + * + * This feature is useful when the protocol knows an ACK-requesting MAC + * Command must be a data poll without needing to receive the MAC Command + * byte, giving it a bit more time to adjust Frame Pending or generate an + * Enhanced ACK. + * + * This function will fail if 802.15.4 hardware acceleration is not + * currently enabled by calling \ref RAIL_IEEE802154_Init(), + * or on platforms that do not support this feature. + * This setting may be changed at any time when 802.15.4 hardware + * acceleration is enabled. + */ +RAIL_Status_t RAIL_IEEE802154_EnableEarlyFramePending(RAIL_Handle_t railHandle, + bool enable); + +/** + * Enable Frame Pending lookup event notification + * (\ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND) for MAC Data frames. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] enable True to enable, false to disable. + * @return A status code indicating success of the function call. + * + * Normally \ref RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND is triggered only + * for ACK-requesting MAC command frames. + * Enabling this feature causes this event to also be triggered for MAC data + * frames, at the same point in the packet as \ref + * RAIL_IEEE802154_EnableEarlyFramePending() would trigger. + * This feature is necessary to support the Thread Basil-Hayden Enhanced + * Frame Pending feature in Version 0/1 frames, and to support Version 2 + * Data frames which require an Enhanced ACK. + * + * This function will fail if 802.15.4 hardware acceleration is not + * currently enabled by calling \ref RAIL_IEEE802154_Init(). + * This setting may be changed at any time when 802.15.4 hardware acceleration + * is enabled. + */ +RAIL_Status_t RAIL_IEEE802154_EnableDataFramePending(RAIL_Handle_t railHandle, + bool enable); + +/** + * Alternate naming for function \ref RAIL_IEEE802154_SetFramePending + * to depict it is used for changing the default setting specified by + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks in + * an outgoing ACK. + */ + #define RAIL_IEEE802154_ToggleFramePending RAIL_IEEE802154_SetFramePending + +/** + * Change the Frame Pending bit on the outgoing legacy Immediate ACK from + * the default specified by + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. + * @param[in] railHandle A handle of RAIL instance + * @return A status code indicating success of the function call. + * + * This function must only be called while processing the \ref + * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND if the ACK + * for this packet should go out with its Frame Pending bit set differently + * than what was specified by + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks. + * + * It's intended only for use with 802.15.4 legacy immediate ACKs and + * not 802.15.4E enhanced ACKs. + * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to + * modify the outgoing Immediate ACK. + + * @note This function is used to set the Frame Pending bit but its meaning + * depends on the value of + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks + * while transmitting ACK. + * If \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks + * is not set, then Frame Pending bit is set in outgoing ACK. + * Whereas, if \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks + * is set, then Frame Pending bit is cleared in outgoing ACK. + * + * Therefore, this function is to be called if the frame is pending when + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks + * is not set or if there is no frame pending when + * \ref RAIL_IEEE802154_Config_t::defaultFramePendingInOutgoingAcks + * is set. + */ +RAIL_Status_t RAIL_IEEE802154_SetFramePending(RAIL_Handle_t railHandle); + +/** + * Get the source address of the incoming data request. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] pAddress A pointer to \ref RAIL_IEEE802154_Address_t structure + * to populate with source address information. + * @return A status code indicating success of the function call. + * + * This function must only be called when handling the \ref + * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND event. This will return + * \ref RAIL_STATUS_INVALID_STATE if the address information is stale + * (i.e., it is too late to affect the outgoing ACK). + */ +RAIL_Status_t RAIL_IEEE802154_GetAddress(RAIL_Handle_t railHandle, + RAIL_IEEE802154_Address_t *pAddress); + +/** + * Write the AutoACK FIFO for the next outgoing 802.15.4E Enhanced ACK. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] ackData Pointer to ACK data to transmit + * This may be NULL, in which case it's assumed the data has already + * been emplaced into the ACK buffer and RAIL just needs to be told + * how many bytes are there. Use \ref RAIL_GetAutoAckFifo() to get + * the address of RAIL's AutoACK buffer in RAM and its size. + * @param[in] ackDataLen Length of ACK data, in bytes. + * If this exceeds \ref RAIL_AUTOACK_MAX_LENGTH the function + * will return \ref RAIL_STATUS_INVALID_PARAMETER. + * @return A status code indicating success of the function call. + * + * This function sets the AutoACK data to use in acknowledging the frame + * being received. It must only be called while processing the \ref + * RAIL_EVENT_IEEE802154_DATA_REQUEST_COMMAND, and is intended for use + * when packet information from \ref RAIL_GetRxIncomingPacketInfo() + * indicates an 802.15.4E Enhanced ACK must be sent instead of a legacy + * Immediate ACK. \ref RAIL_IEEE802154_ToggleFramePending() should not be + * called for an Enhanced ACK; instead the Enhanced ACK's Frame Control + * Field should have the Frame Pending bit set appropriately in its ackData. + * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to + * write the outgoing ACK -- a situation that will likely trigger + * a \ref RAIL_EVENT_TXACK_UNDERFLOW event. When successful, the Enhanced + * ackData will only be sent once. Subsequent packets needing an Enhanced + * ACK will each need to call this function to write their ACK information. + */ +RAIL_Status_t RAIL_IEEE802154_WriteEnhAck(RAIL_Handle_t railHandle, + const uint8_t *ackData, + uint8_t ackDataLen); + +/** + * Set a separate RX packet to TX state transition turnaround time for + * sending an Enhanced ACK. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in,out] pRxToEnhAckTx Pointer to the turnaround transition requested + * for Enhanced ACKs. It will be updated with the actual time set. + * Requesting a time of 0 will sync the Enhanced ACK turnaround time with + * that used for immediate ACKs (and output 0). Requesting a time of \ref + * RAIL_TRANSITION_TIME_KEEP will output the current Enhanced ACK timing + * parameter (0 if it is the same as that used for Immediate ACKs). + * @return Status code indicating a success of the function call. + * An error will not update the pRxToEnhAckTx output parameter. + * + * Normally Immediate and Enhanced ACKs are both sent using the + * \ref RAIL_IEEE802154_Config_t::timings rxToTx turnaround time. + * If the stack needs more time to prepare an Enhanced ACK, it can + * call this function after \ref RAIL_IEEE802154_Init() to set a + * longer turnaround time used just for Enhanced ACK transmits. + * + * This function will fail on platforms that lack + * \ref RAIL_IEEE802154_SUPPORTS_E_ENHANCED_ACK. + */ +RAIL_Status_t RAIL_IEEE802154_SetRxToEnhAckTx(RAIL_Handle_t railHandle, + RAIL_TransitionTime_t *pRxToEnhAckTx); + +/** + * Convert RSSI into 802.15.4 Link Quality Indication (LQI) metric + * compatible with the Silicon Labs Zigbee stack. + * + * @param[in] origLqi The original LQI, for example from + * \ref RAIL_RxPacketDetails_t::lqi. + * This parameter is not currently used but may be used in the future. + * @param[in] rssiDbm The RSSI in dBm, for example from + * \ref RAIL_RxPacketDetails_t::rssi. + * @return An LQI value (range 0..255 but not all intermediate values are + * possible) based on the rssiDbm and the chip's RSSI sensitivity range. + * + * This function is compatible with \ref RAIL_ConvertLqiCallback_t and + * is suitable to pass to \ref RAIL_ConvertLqi(). + */ +uint8_t RAIL_IEEE802154_ConvertRssiToLqi(uint8_t origLqi, int8_t rssiDbm); + +/** + * Convert RSSI into 802.15.4 Energy Detection (ED) metric + * compatible with the Silicon Labs Zigbee stack. + * + * @param[in] rssiDbm The RSSI in dBm, for example from + * \ref RAIL_RxPacketDetails_t::rssi. + * @return An Energy Detect value (range 0..255 but not all intermediate + * values are possible) based on the rssiDbm and the chip's RSSI + * sensitivity range. + */ +uint8_t RAIL_IEEE802154_ConvertRssiToEd(int8_t rssiDbm); + +/** + * @enum RAIL_IEEE802154_CcaMode_t + * @brief Available CCA modes. + */ +RAIL_ENUM(RAIL_IEEE802154_CcaMode_t) { + /** + * RSSI-based CCA. CCA reports a busy medium upon detecting any energy + * above \ref RAIL_CsmaConfig_t.ccaThreshold. + */ + RAIL_IEEE802154_CCA_MODE_RSSI = 0, + /** + * Signal Identifier-based CCA. CCA reports a busy medium only upon the + * detection of a signal compliant with this standard with the same modulation + * and spreading characteristics of the PHY that is currently in use. + */ + RAIL_IEEE802154_CCA_MODE_SIGNAL, + /** + * RSSI or signal identifier-based CCA. CCA reports a busy medium on + * either detecting any energy above \ref RAIL_CsmaConfig_t.ccaThreshold + * or detection of a signal compliant with this standard with the same + * modulation and spreading characteristics of the PHY that is currently in use. + */ + RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI, + /** + * RSSI and signal identifier-based CCA. CCA reports a busy medium only + * on detecting any energy above \ref RAIL_CsmaConfig_t.ccaThreshold of a + * signal compliant with this standard with the same modulation and spreading + * characteristics of the PHY that is currently in use. + */ + RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI, + /** + * ALOHA. Always transmit CCA=1. CCA always reports an idle medium. + */ + RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT, + /** + * Number of CCA modes. + */ + RAIL_IEEE802154_CCA_MODE_COUNT +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_IEEE802154_CCA_MODE_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_RSSI) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI) +#define RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI) +#define RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_ALWAYS_TRANSMIT) +#define RAIL_IEEE802154_CCA_MODE_COUNT ((RAIL_IEEE802154_CcaMode_t)RAIL_IEEE802154_CCA_MODE_COUNT) +#endif + +/** + * @enum RAIL_IEEE802154_SignalIdentifierMode_t + * @brief Available Signal identifier modes. + */ +RAIL_ENUM(RAIL_IEEE802154_SignalIdentifierMode_t) { + /* Disable signal detection mode. */ + RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE = 0, + /* 2.4Ghz 802.15.4 signal detection mode. */ + RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_DISABLE) +#define RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154 ((RAIL_IEEE802154_SignalIdentifierMode_t)RAIL_IEEE802154_SIGNAL_IDENTIFIER_MODE_154) +#endif + +/** + * Configure signal identifier for 802.15.4 signal detection. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] signalIdentifierMode Mode of signal identifier operation. + * + * This features allows detection of 2.4Ghz 802.15.4 signal on air. This + * function must be called once before \ref RAIL_IEEE802154_EnableSignalDetection + * to configure and enable signal identifier. + * + * To enable event for signal detection \ref RAIL_ConfigEvents() must be called + * for enabling \ref RAIL_EVENT_SIGNAL_DETECTED. + * + * This function is only supported by chips where + * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and + * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigSignalIdentifier(RAIL_Handle_t railHandle, + RAIL_IEEE802154_SignalIdentifierMode_t signalIdentifierMode); + +/** + * Enable or disable signal identifier for 802.15.4 signal detection. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enable Signal detection is enabled if true, disabled if false. + * + * \ref RAIL_IEEE802154_ConfigSignalIdentifier must be called once before calling + * this function to configure and enable signal identifier. + * Once a signal is detected signal detection will be turned off and this + * function should be called to re-enable the signal detection without needing + * to call \ref RAIL_IEEE802154_ConfigSignalIdentifier if the signal identifier + * is already configured and enabled. + * + * This function is only supported by chips where + * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and + * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. + * + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_IEEE802154_EnableSignalDetection(RAIL_Handle_t railHandle, + bool enable); + +/** + * @brief Backward compatible name for the \ref + * RAIL_IEEE802154_EnableSignalDetection API. + */ +#define RAIL_IEEE802154_EnableSignalIdentifier RAIL_IEEE802154_EnableSignalDetection + +/** + * Set 802.15.4 CCA mode. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] ccaMode Mode of CCA operation. + * + * This function sets the CCA mode \ref RAIL_IEEE802154_CcaMode_t. + * If not called, RAIL_IEEE802154_CCA_MODE_RSSI (RSSI-based CCA) is used for CCA. + * + * In RAIL_IEEE802154_CCA_MODE_SIGNAL, RAIL_IEEE802154_CCA_MODE_SIGNAL_OR_RSSI and + * RAIL_IEEE802154_CCA_MODE_SIGNAL_AND_RSSI signal identifier is enabled + * for the duration of LBT. If previously enabled by + * \ref RAIL_IEEE802154_ConfigSignalIdentifier, the signal identifier will remain + * active until triggered. + * + * This function is only supported by chips where + * \ref RAIL_IEEE802154_SUPPORTS_SIGNAL_IDENTIFIER and + * \ref RAIL_IEEE802154_SupportsSignalIdentifier() are true. + * + * @return Status code indicating success of the function call. + * An error should be returned if ccaMode is unsuppported on a given device. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigCcaMode(RAIL_Handle_t railHandle, + RAIL_IEEE802154_CcaMode_t ccaMode); + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * Allow certain malformed MAC Header frames to be received. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] enable True to enable, false to disable. + * @return A status code indicating success of the function call. + * + * When allowed, certain MAC header formats that 802.15.4 deems + * illegal will be received rather than filtered. This is to + * support interoperablity with an old spec-violating 802.15.4 + * peer and is only supported on certain Series-2 platforms. + * + * @note \ref RAIL_IEEE802154_SetPanCoordinator() must also be + * enabled to receive malformed frames lacking destination + * address information. + */ +RAIL_Status_t RAIL_IEEE802154_AllowMalformed(RAIL_Handle_t railHandle, + bool allow); +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Configure RX channel switching for 802.15.4. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] pConfig A pointer to \ref RAIL_IEEE802154_RxChannelSwitchingCfg_t + * structure. Use NULL to disable any switching previously set up. + * @return Status code indicating success of the function call. + * + * This function configures RX channel switching, allowing reception of 2.4Ghz + * 802.15.4 signals on two different radio channels within the same PHY. + * (If the two channels are same, the function behaves the same as if + * pConfig was NULL.) + * This function should be + * called once before \ref RAIL_StartRx and/or enabling + * \ref RAIL_RX_OPTION_CHANNEL_SWITCHING. + * + * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is enabled, + * channel switching will occur during normal listening but is suspended + * (and the radio is idled) when starting any kind of transmit, including + * scheduled or CSMA transmits. It remains suspended after a \ref + * RAIL_TX_OPTION_WAIT_FOR_ACK transmit until the ACK is received or + * times out. + * + * When \ref RAIL_RX_OPTION_CHANNEL_SWITCHING is disabled after switching + * has been active, the radio could be left listening on either channel, + * so the application should call \ref RAIL_StartRx() to put it on the + * desired non-switching channel. + * + * @note IEEE 802.15.4 must be enabled via \ref RAIL_IEEE802154_Init, and the + * radio must be in the idle state when configuring RX channel switching. + * A DMA channel must be allocated with \ref RAIL_UseDma; otherwise this API + * will return \ref RAIL_STATUS_INVALID_CALL. + * This feature also requires a PRS channel, internally allocated by the RAIL + * library, to use and hold onto for future use. If no PRS channel is + * available, the function returns \ref RAIL_STATUS_INVALID_PARAMETER. + * + * @note When RX channel switching is active, receive sensitivity and performance + * are slightly impacted. + * + * @note This function internally uses \ref RAIL_EnableCacheSynthCal to + * enable/disable the sequencer cache to store the synth calibration value. + * + * @note Switching is cancelled on any PHY change, so this function would + * need to be re-called to reestablish switching after such a change. + */ +RAIL_Status_t RAIL_IEEE802154_ConfigRxChannelSwitching(RAIL_Handle_t railHandle, + const RAIL_IEEE802154_RxChannelSwitchingCfg_t *pConfig); + +/** @} */ // end of IEEE802.15.4 + +/// @addtogroup Calibration +/// @brief IEEE802154 protocol-specific APIs for calibrating the radio. +/// @{ + +/** + * Calibrate image rejection for IEEE 802.15.4 2.4 GHz. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] imageRejection The result of the image rejection calibration. + * @return A status code indicating success of the function call. + * + * Some chips have protocol-specific image rejection calibrations programmed + * into their flash. This function will either get the value from flash and + * apply it, or run the image rejection algorithm to find the value. + */ +RAIL_Status_t RAIL_IEEE802154_CalibrateIr2p4Ghz(RAIL_Handle_t railHandle, + uint32_t *imageRejection); + +/** + * Calibrate image rejection for IEEE 802.15.4 915 MHz and 868 MHz. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] imageRejection The result of the image rejection calibration. + * @return A status code indicating success of the function call. + * + * Some chips have protocol-specific image rejection calibrations programmed + * into their flash. This function will either get the value from flash and + * apply it, or run the image rejection algorithm to find the value. + * + * @deprecated Please use \ref RAIL_CalibrateIrAlt instead. + */ +RAIL_Status_t RAIL_IEEE802154_CalibrateIrSubGhz(RAIL_Handle_t railHandle, + uint32_t *imageRejection); + +/// @} // End of group Calibration + +#ifdef __cplusplus +} +#endif + +#ifdef RAIL_INTERNAL_BUILD +#include "rail_ieee802154_internal.h" +#endif + +#endif // __RAIL_IEEE802154_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h index 1491a03..1e346a2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/sidewalk/rail_sidewalk.h @@ -1,85 +1,85 @@ -/***************************************************************************//** - * @file - * @brief The Sidewalk specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef RAIL_SIDEWALK_H -#define RAIL_SIDEWALK_H - -#ifdef __cplusplus -extern "C" { -#endif - -// Get the standard include types -#include -#include - -// Get the RAIL specific structures and types -#include "rail_types.h" - -/// @addtogroup SIDEWALK_PHY Sidewalk Radio Configurations -/// @ingroup Protocol_Specific -/// Radio configurations for the RAIL Sidewalk Accelerator -/// -/// These radio configurations are used to configure Sidewalk when a function -/// such as \ref RAIL_Sidewalk_ConfigPhy2GFSK50kbps() is called. Each radio -/// configuration listed below is compiled into the RAIL library as a weak -/// symbol that will take into account per-die defaults. If the board -/// configuration in use has different settings than the default, such as a -/// different radio subsystem clock frequency, these radio configurations can -/// be overriden to account for those settings. -/// @{ - -/** - * Default PHY to use for Sidewalk 2GFSK 50kbps. Will be NULL if - * \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK is 0. - */ -extern const RAIL_ChannelConfig_t *const RAIL_Sidewalk_Phy2GFSK50kbps; - -/** - * Switch to the 2GFSK 50kbps Sidewalk PHY. - * - * @param[in] railHandle A handle for RAIL instance. - * @return A status code indicating success of the function call. - * - * Use this function to switch to the 2GFSK 50kbps Sidewalk PHY. - * - * @note The Sidewalk PHY is supported only on some parts. - * The preprocessor symbol \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK and the - * runtime function \ref RAIL_SupportsProtocolSidewalk() may be used to - * test for support of the Sidewalk PHY. - */ -RAIL_Status_t RAIL_Sidewalk_ConfigPhy2GFSK50kbps(RAIL_Handle_t railHandle); - -/// @} // End of group SIDEWALK_PHY - -#ifdef __cplusplus -} -#endif - -#endif // RAIL_SIDEWALK_H +/***************************************************************************//** + * @file + * @brief The Sidewalk specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef RAIL_SIDEWALK_H +#define RAIL_SIDEWALK_H + +#ifdef __cplusplus +extern "C" { +#endif + +// Get the standard include types +#include +#include + +// Get the RAIL specific structures and types +#include "rail_types.h" + +/// @addtogroup SIDEWALK_PHY Sidewalk Radio Configurations +/// @ingroup Protocol_Specific +/// Radio configurations for the RAIL Sidewalk Accelerator +/// +/// These radio configurations are used to configure Sidewalk when a function +/// such as \ref RAIL_Sidewalk_ConfigPhy2GFSK50kbps() is called. Each radio +/// configuration listed below is compiled into the RAIL library as a weak +/// symbol that will take into account per-die defaults. If the board +/// configuration in use has different settings than the default, such as a +/// different radio subsystem clock frequency, these radio configurations can +/// be overriden to account for those settings. +/// @{ + +/** + * Default PHY to use for Sidewalk 2GFSK 50kbps. Will be NULL if + * \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK is 0. + */ +extern const RAIL_ChannelConfig_t *const RAIL_Sidewalk_Phy2GFSK50kbps; + +/** + * Switch to the 2GFSK 50kbps Sidewalk PHY. + * + * @param[in] railHandle A handle for RAIL instance. + * @return A status code indicating success of the function call. + * + * Use this function to switch to the 2GFSK 50kbps Sidewalk PHY. + * + * @note The Sidewalk PHY is supported only on some parts. + * The preprocessor symbol \ref RAIL_SUPPORTS_PROTOCOL_SIDEWALK and the + * runtime function \ref RAIL_SupportsProtocolSidewalk() may be used to + * test for support of the Sidewalk PHY. + */ +RAIL_Status_t RAIL_Sidewalk_ConfigPhy2GFSK50kbps(RAIL_Handle_t railHandle); + +/// @} // End of group SIDEWALK_PHY + +#ifdef __cplusplus +} +#endif + +#endif // RAIL_SIDEWALK_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h index 066ced7..9727aa9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/wmbus/rail_wmbus.h @@ -1,91 +1,91 @@ -/***************************************************************************//** - * @file - * @brief The WMBUS specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_WMBUS_H__ -#define __RAIL_WMBUS_H__ - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @addtogroup WMBUS Wireless M-Bus -/// @ingroup Protocol_Specific -/// @brief Wireless M-Bus (WMBUS) configuration -/// @{ - -/** - * @enum RAIL_WMBUS_Phy_t - * @brief The RX variant of the WMBUS T+C PHY. - */ -RAIL_ENUM(RAIL_WMBUS_Phy_t) { - /** subPhyId indicating a mode T frame A packet */ - RAIL_WMBUS_ModeTFrameA = 0U, - /** subPhyId indicating a mode C frame A packet */ - RAIL_WMBUS_ModeCFrameA = 2U, - /** subPhyId indicating a mode C frame B packet */ - RAIL_WMBUS_ModeCFrameB = 3U, -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_WMBUS_ModeTFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeTFrameA) -#define RAIL_WMBUS_ModeCFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameA) -#define RAIL_WMBUS_ModeCFrameB ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameB) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Configure WMBUS simultaneous M2O RX of T and C modes feature. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] enableSimultaneousTCRx True to enable WMBUS simultaneous M2O RX of T and C modes. - * @return Status code indicating success of the function call. - * - * If simultaneous M2O RX of T and C modes is enabled, when - * PHY_wMbus_ModeTC_M2O_100k_frameA is loaded, mode T Frame A and mode C frame - * A/B can be received. The mode and frame type of the last received packet is - * available in \ref RAIL_RxPacketDetails_t::subPhyId. - * - * @note This WMBUS feature is supported only on some parts. - * The preprocessor symbol \ref RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX and the - * runtime function \ref RAIL_WMBUS_SupportsSimultaneousTCRx() may be used to - * test for support. - */ -RAIL_Status_t RAIL_WMBUS_Config(RAIL_Handle_t railHandle, - bool enableSimultaneousTCRx); - -/// @} // End of group WMBUS - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_WMBUS_H__ +/***************************************************************************//** + * @file + * @brief The WMBUS specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_WMBUS_H__ +#define __RAIL_WMBUS_H__ + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @addtogroup WMBUS Wireless M-Bus +/// @ingroup Protocol_Specific +/// @brief Wireless M-Bus (WMBUS) configuration +/// @{ + +/** + * @enum RAIL_WMBUS_Phy_t + * @brief The RX variant of the WMBUS T+C PHY. + */ +RAIL_ENUM(RAIL_WMBUS_Phy_t) { + /** subPhyId indicating a mode T frame A packet */ + RAIL_WMBUS_ModeTFrameA = 0U, + /** subPhyId indicating a mode C frame A packet */ + RAIL_WMBUS_ModeCFrameA = 2U, + /** subPhyId indicating a mode C frame B packet */ + RAIL_WMBUS_ModeCFrameB = 3U, +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_WMBUS_ModeTFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeTFrameA) +#define RAIL_WMBUS_ModeCFrameA ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameA) +#define RAIL_WMBUS_ModeCFrameB ((RAIL_WMBUS_Phy_t) RAIL_WMBUS_ModeCFrameB) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Configure WMBUS simultaneous M2O RX of T and C modes feature. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] enableSimultaneousTCRx True to enable WMBUS simultaneous M2O RX of T and C modes. + * @return Status code indicating success of the function call. + * + * If simultaneous M2O RX of T and C modes is enabled, when + * PHY_wMbus_ModeTC_M2O_100k_frameA is loaded, mode T Frame A and mode C frame + * A/B can be received. The mode and frame type of the last received packet is + * available in \ref RAIL_RxPacketDetails_t::subPhyId. + * + * @note This WMBUS feature is supported only on some parts. + * The preprocessor symbol \ref RAIL_WMBUS_SUPPORTS_SIMULTANEOUS_T_C_RX and the + * runtime function \ref RAIL_WMBUS_SupportsSimultaneousTCRx() may be used to + * test for support. + */ +RAIL_Status_t RAIL_WMBUS_Config(RAIL_Handle_t railHandle, + bool enableSimultaneousTCRx); + +/// @} // End of group WMBUS + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_WMBUS_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/zwave/rail_zwave.h b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/zwave/rail_zwave.h index e37c82e..a72ef78 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/zwave/rail_zwave.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/radio/rail_lib/protocol/zwave/rail_zwave.h @@ -1,949 +1,949 @@ -/***************************************************************************//** - * @file - * @brief The Z-Wave specific header file for the RAIL library. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef __RAIL_ZWAVE_H__ -#define __RAIL_ZWAVE_H__ - -#include "rail_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/// @addtogroup Z_Wave Z-Wave -/// @ingroup Protocol_Specific -/// @brief Z-Wave configuration routines -/// -/// The functions in this group configure RAIL Z-Wave hardware -/// acceleration features. -/// -/// To configure Z-Wave functionality, the application must first set up -/// a RAIL instance with RAIL_Init() and other setup functions. -/// -/// @code{.c} -/// -/// RAIL_ZWAVE_NodeId_t gRecentBeamNodeId; -/// uint8_t gRecentBeamChannelIndex; -/// -/// // Main RAIL_EVENT callback -/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) -/// { -/// // Get beamNodeId and channel index from beam packet -/// if (events & RAIL_EVENT_ZWAVE_BEAM) { -/// if (RAIL_ZWAVE_IsEnabled(railHandle)) { -/// if ((RAIL_ZWAVE_GetBeamNodeId(railHandle, &gRecentBeamNodeId) -/// != RAIL_STATUS_NO_ERROR) -/// || (RAIL_ZWAVE_GetBeamChannelIndex(railHandle, &gRecentBeamChannelIndex) -/// != RAIL_STATUS_NO_ERROR)) { -/// return; -/// } -/// } -/// } -/// } -/// -/// static const RAIL_ZWAVE_Config_t zwaveConfig = { -/// .options = RAIL_ZWAVE_OPTIONS_DEFAULT -/// }; -/// -/// RAIL_Status_t zwaveInit(void) -/// { -/// // initialize Z-Wave -/// RAIL_Status_t status = RAIL_ZWAVE_Init(railHandle, &zwaveConfig); -/// -/// if (status != RAIL_STATUS_NO_ERROR) { -/// return status; -/// } -/// -/// uint8_t myHomeId[4] = { 0xDE, 0xAD, 0xBE, 0xEF }; -/// RAIL_ZWAVE_SetNodeId(railHandle, RAIL_ZWAVE_NODE_ID_DEFAULT); -/// RAIL_ZWAVE_SetHomeId(railHandle, myHomeId, RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE); -/// -/// // configure region to EU(European Union) -/// return RAIL_ZWAVE_ConfigRegion(railHandle, RAIL_ZWAVE_REGION_EU); -/// } -/// @endcode -/// -/// @{ - -/** - * @enum RAIL_ZWAVE_Options_t - * @brief Z-Wave options. - */ -RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { - // Z-Wave Option Bit Shifts - - /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE bit */ - RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT = 0, - /** Shift position of \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES bit */ - RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT, - /** Shift position of \ref RAIL_ZWAVE_OPTION_NODE_ID_FILTERING bit */ - RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT, - /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE bit */ - RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT, -}; - -// RAIL_ZWAVE_Options_t bitmasks - -/** A value representing no options */ -#define RAIL_ZWAVE_OPTIONS_NONE 0U - -/** All options are disabled by default. */ -#define RAIL_ZWAVE_OPTIONS_DEFAULT RAIL_ZWAVE_OPTIONS_NONE - -/** - * An option to configure promiscuous mode, accepting non-beam packets - * regardless of their HomeId. By default packets are filtered by their HomeId. - * When true, such filtering is disabled. - */ -#define RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE \ - (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT) - -/** - * An option to filter non-beam packets based on their NodeId when - * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is disabled. - * - * @note This option has no effect when - * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is enabled. - */ -#define RAIL_ZWAVE_OPTION_NODE_ID_FILTERING \ - (1u << RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT) - -/** - * An option to configure beam frame recognition. By default beams are not - * considered special and will be received as if they were normal Z-Wave - * frames, assuredly triggering \ref RAIL_EVENT_RX_FRAME_ERROR. - * When true, beam frames that are broadcast or match the NodeId and - * HomeIdHash values will trigger \ref RAIL_EVENT_ZWAVE_BEAM event. - * (All beams additionally trigger \ref RAIL_EVENT_RX_PACKET_ABORTED - * regardless of NodeId / HomeIdHash values.) - * - * @note This option takes precedence over \ref - * RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE when receiving a beam frame. - * For promiscuous beam handling see related - * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE option. - */ -#define RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES \ - (1u << RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT) - -/** - * An option to receive all beams promiscuously when \ref - * RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. - * When true, beam frames are received regardless of their NodeId or HomeIdHash - * resulting in \ref RAIL_EVENT_ZWAVE_BEAM (and also \ref - * RAIL_EVENT_RX_PACKET_ABORTED) for each beam frame. - * - * @note This option has no effect when - * \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is disabled. - */ -#define RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE \ - (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT) - -/** A value representing all options */ -#define RAIL_ZWAVE_OPTIONS_ALL 0xFFFFFFFFU - -/** - * @enum RAIL_ZWAVE_NodeId_t - * @brief A Z-Wave Node ID. - * - * This data type is 12 bits wide when using the ZWave Long Range PHY, and - * 8 bits wide otherwise. - * - * @note When using the Long Range PHY, values 0xFA1..0xFFE are reserved. - * Otherwise, values 0xE9..0xFE are reserved. - */ -RAIL_ENUM_GENERIC(RAIL_ZWAVE_NodeId_t, uint16_t) { - /** The unknown NodeId for uninitialized nodes. */ - RAIL_ZWAVE_NODE_ID_NONE = 0x00U, - /** The broadcast NodeId. */ - RAIL_ZWAVE_NODE_ID_BROADCAST = 0xFFU, - /** Default to the broadcast NodeId. */ - RAIL_ZWAVE_NODE_ID_DEFAULT = RAIL_ZWAVE_NODE_ID_BROADCAST, - // All other values between 0x00 and 0xFE are valid node IDs normally - /** The Long Range broadcast NodeId. */ - RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE = 0xFFFU, - /** Default to the Long Range broadcast NodeId. */ - RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE = RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE, - // All values from 0x001 to 0xFA1 are valid node IDs with a Long Range PHY. -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_NODE_ID_NONE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_NONE) -#define RAIL_ZWAVE_NODE_ID_BROADCAST ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST) -#define RAIL_ZWAVE_NODE_ID_DEFAULT ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** Defines for subPhyID field in RAIL_RxPacketDetails_t */ -#define RAIL_ZWAVE_RX_SUBPHY_ID_0 (0U) -#define RAIL_ZWAVE_RX_SUBPHY_ID_1 (1U) -#define RAIL_ZWAVE_RX_SUBPHY_ID_2 (2U) -#define RAIL_ZWAVE_RX_SUBPHY_ID_3 (3U) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_ZWAVE_HomeId_t - * @brief A Z-Wave Home ID. - * - * @note Home IDs in the range 0x54000000..0x55FFFFFF are illegal. - */ -RAIL_ENUM_GENERIC(RAIL_ZWAVE_HomeId_t, uint32_t) { - RAIL_ZWAVE_HOME_ID_UNKNOWN = 0x00000000U, /**< The unknown HomeId. */ - RAIL_ZWAVE_HOME_ID_DEFAULT = 0x54545454U, /**< An impossible and unlikely HomeId. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_HOME_ID_UNKNOWN ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_UNKNOWN) -#define RAIL_ZWAVE_HOME_ID_DEFAULT ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_DEFAULT) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_ZWAVE_HomeIdHash_t - * @brief A Z-Wave Home ID hash. - * - * @note Certain values (as shown) are illegal. - */ -RAIL_ENUM(RAIL_ZWAVE_HomeIdHash_t) { - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 = 0x0AU, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 = 0x4AU, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 = 0x55U, /**< An illegal HomeIdHash value. */ - RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE = 0x55U, /**< Illegal HomeIdHash value that - suppresses checking the - HomeIdHash field of beam - packets. */ - RAIL_ZWAVE_HOME_ID_HASH_DEFAULT - = RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, /**< Default to don't care. */ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1) -#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2) -#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3) -#define RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE) -#define RAIL_ZWAVE_HOME_ID_HASH_DEFAULT ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DEFAULT) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * @struct RAIL_ZWAVE_Config_t - * @brief A configuration structure for Z-Wave in RAIL. - */ -typedef struct RAIL_ZWAVE_Config { - /** - * Defines Z-Wave options. - */ - RAIL_ZWAVE_Options_t options; - /** - * Defines Z-Wave ACKing configuration. - */ - RAIL_AutoAckConfig_t ackConfig; - /** - * Defines state timings for Z-Wave. - */ - RAIL_StateTiming_t timings; -} RAIL_ZWAVE_Config_t; - -/** - * @enum RAIL_ZWAVE_Baud_t - * @brief Z-Wave supported baudrates or PHYs. - */ -RAIL_ENUM(RAIL_ZWAVE_Baud_t) { - RAIL_ZWAVE_BAUD_9600, /**< 9.6kbps baudrate*/ - RAIL_ZWAVE_BAUD_40K, /**< 40kbps baudrate*/ - RAIL_ZWAVE_BAUD_100K, /**< 100kbps baudrate*/ - RAIL_ZWAVE_LR, /**< Long Range PHY*/ - RAIL_ZWAVE_ENERGY_DETECT = RAIL_ZWAVE_LR, /**< Energy detection PHY*/ - RAIL_ZWAVE_BAUD_INVALID /**< Sentinel value for invalid baud rate*/ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -/** - * @enum RAIL_ZWAVE_RegionOptions_t - * @brief Region Specific Physical - */ - -RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) -{ - /** Bit shift for US Long Range End Devices */ - RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT = 0, - /** Bit shift for special low side config, mostly for Japan and Korea */ - RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT = 1, - /** Bit shift for US long range range configurations */ - RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT = 2, -}; - -/** - * RAIL_ZWAVE_RegionOptions_t bitmasks - */ -/** A value representing US Long Range regions */ -#define RAIL_ZWAVE_REGION_LONG_RANGE_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT) -/** A value representing lowside configurations: For Series 2: JP and KR, for Series 1: KR */ -#define RAIL_ZWAVE_REGION_LOW_SIDE_MASK (1u << RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT) -/** A value representing Long Range End Device region */ -#define RAIL_ZWAVE_REGION_LONG_RANGE_END_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT) -/** A value representing No bit to be enabled */ -#define RAIL_ZWAVE_REGION_SPECIFIC_NONE 0u -#endif // DOXYGEN SHOULD SKIP THIS - -/** - * Sentinel value to indicate that a channel (and thus its frequency) - * are invalid. - */ -#define RAIL_ZWAVE_FREQ_INVALID 0xFFFFFFFFUL - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_BAUD_9600 ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_9600) -#define RAIL_ZWAVE_BAUD_40K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_40K) -#define RAIL_ZWAVE_BAUD_100K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_100K) -#define RAIL_ZWAVE_LR ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_LR) -#define RAIL_ZWAVE_ENERGY_DETECT ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_ENERGY_DETECT) -#define RAIL_ZWAVE_INVALID ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_INVALID) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * @enum RAIL_ZWAVE_RegionId_t - * @brief Z-Wave region identifications. - */ -RAIL_ENUM(RAIL_ZWAVE_RegionId_t) { - RAIL_ZWAVE_REGIONID_UNKNOWN, /**< Unknown/Invalid*/ - RAIL_ZWAVE_REGIONID_EU, /**< European Union*/ - RAIL_ZWAVE_REGIONID_US, /**< United States*/ - RAIL_ZWAVE_REGIONID_ANZ, /**< Australia/New Zealand*/ - RAIL_ZWAVE_REGIONID_HK, /**< Hong Kong*/ - RAIL_ZWAVE_REGIONID_MY, /**< Malaysia*/ - RAIL_ZWAVE_REGIONID_IN, /**< India*/ - RAIL_ZWAVE_REGIONID_JP, /**< Japan*/ - RAIL_ZWAVE_REGIONID_RU, /**< Russian Federation*/ - RAIL_ZWAVE_REGIONID_IL, /**< Israel*/ - RAIL_ZWAVE_REGIONID_KR, /**< Korea*/ - RAIL_ZWAVE_REGIONID_CN, /**< China*/ - RAIL_ZWAVE_REGIONID_US_LR1, /**< United States, with first long range PHY*/ - RAIL_ZWAVE_REGIONID_US_LR2, /**< United States, with second long range PHY*/ - RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE, /**< United States long range end device PHY for both LR frequencies*/ - RAIL_ZWAVE_REGIONID_EU_LR1, /**< European Union, with first long range PHY*/ - RAIL_ZWAVE_REGIONID_EU_LR2, /**< European Union, with second long range PHY*/ - RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE, /**< European Union long range end device PHY for both LR frequencies*/ - RAIL_ZWAVE_REGIONID_COUNT /**< Count of known regions, must be last*/ -}; - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Self-referencing defines minimize compiler complaints when using RAIL_ENUM -#define RAIL_ZWAVE_REGIONID_UNKNOWN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_UNKNOWN) -#define RAIL_ZWAVE_REGIONID_EU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU) -#define RAIL_ZWAVE_REGIONID_US ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US) -#define RAIL_ZWAVE_REGIONID_ANZ ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_ANZ) -#define RAIL_ZWAVE_REGIONID_HK ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_HK) -#define RAIL_ZWAVE_REGIONID_MY ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_MY) -#define RAIL_ZWAVE_REGIONID_IN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IN) -#define RAIL_ZWAVE_REGIONID_JP ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_JP) -#define RAIL_ZWAVE_REGIONID_RU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_RU) -#define RAIL_ZWAVE_REGIONID_IL ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IL) -#define RAIL_ZWAVE_REGIONID_KR ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_KR) -#define RAIL_ZWAVE_REGIONID_CN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_CN) -#define RAIL_ZWAVE_REGIONID_US_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR1) -#define RAIL_ZWAVE_REGIONID_US_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR2) -#define RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE) -#define RAIL_ZWAVE_REGIONID_EU_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR1) -#define RAIL_ZWAVE_REGIONID_EU_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR2) -#define RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE) -#define RAIL_ZWAVE_REGIONID_COUNT ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_COUNT) -#endif //DOXYGEN_SHOULD_SKIP_THIS - -#ifndef DOXYGEN_SHOULD_SKIP_THIS -// Largest ACK timeout period based on -// aPhyTurnaroundTimeRxTx (1 ms max)+ (aMacTransferAckTimeTX (168 bits)* (1/data rate)) -// For slowest Data Rate R1 (19.6 kbit/s) -#define RAIL_ZWAVE_MAX_ACK_TIMEOUT_US (9600U) - -// Defines for Transition timing -#define RAIL_ZWAVE_TIME_IDLE_TO_RX_US (100U) -#define RAIL_ZWAVE_TIME_TX_TO_RX_US (0U) -#define RAIL_ZWAVE_TIME_IDLE_TO_TX_US (0U) -#define RAIL_ZWAVE_TIME_RX_TO_TX_US (1000U) - -#endif //DOXYGEN_SHOULD_SKIP_THIS - -/** - * Invalid beam TX power value returned when \ref RAIL_ZWAVE_GetLrBeamTxPower - * is called after receiving a regular non-long-range beam. - */ -#define RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID (0xFFU) - -/** - * @struct RAIL_ZWAVE_LrAckData_t - * @brief Configuration structure for Z-Wave Long Range ACK. - */ -typedef struct RAIL_ZWAVE_LrAckData { - /// Radio noise level measured on the channel the frame is transmitted on. - int8_t noiseFloorDbm; - /// Transmit power used to transmit the ongoing Z-Wave Long Range ACK. - int8_t txPowerDbm; - /// Signal strength measured while receiving the Z-Wave Long Range frame. - int8_t receiveRssiDbm; -} RAIL_ZWAVE_LrAckData_t; - -/** - * @struct RAIL_ZWAVE_BeamRxConfig_t - * @brief Configuration structure for Z-Wave beam detection. - * This structure should not be used without direct instruction - * by Silicon Labs. Appropriate defaults for this are built into - * the RAIL library. - */ -typedef struct RAIL_ZWAVE_BeamRxConfig { - /// Channel hopping pattern to use for beam detection. - RAIL_RxChannelHoppingConfig_t channelHoppingConfig; - /// Amount of time to spend trying to receive a beam once detected. - /// 100kbps only - RAIL_RxDutyCycleConfig_t receiveConfig_100; - /// Amount of time to spend trying to receive a beam once detected. - /// 40kbps only - RAIL_RxDutyCycleConfig_t receiveConfig_40; -} RAIL_ZWAVE_BeamRxConfig_t; - -/** - * Number of channels in each of Z-Wave's region-based PHYs - */ -#define RAIL_NUM_ZWAVE_CHANNELS (4U) - -/** - * @struct RAIL_ZWAVE_RegionConfig_t - * @brief Each Z-Wave region supports 3 channels. - */ -typedef struct RAIL_ZWAVE_RegionConfig { - uint32_t frequency[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel frequency in hertz*/ - RAIL_TxPower_t maxPower[RAIL_NUM_ZWAVE_CHANNELS]; /**< The maximum power allowed on the channel*/ - RAIL_ZWAVE_Baud_t baudRate[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel baud rate index*/ - RAIL_ZWAVE_RegionId_t regionId; /**< Identification number for the region*/ - RAIL_ZWAVE_RegionOptions_t regionSpecific; /**< Encapsulates region specific data*/ -} RAIL_ZWAVE_RegionConfig_t; - -/** - * @struct RAIL_ZWAVE_IrcalVal_t - * @brief Structure for Z-Wave Image Rejection Calibration. - * - * @note Index 0 will hold the low side image rejection calibration value (channel 0), - * while index 1 will hold the high side image rejection value (channel 1). - */ -typedef struct RAIL_ZWAVE_IrcalVal { - RAIL_IrCalValues_t imageRejection[2]; /**< Low side and high side image rejection values*/ -} RAIL_ZWAVE_IrcalVal_t; - -/** - * @typedef RAIL_RxChannelHoppingParameters_t - * @brief Rx channel hopping on-channel time for all Z-Wave channels in a region - */ -typedef RAIL_RxChannelHoppingParameter_t RAIL_RxChannelHoppingParameters_t[RAIL_NUM_ZWAVE_CHANNELS]; - -/** - * Switch the Z-Wave region. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] regionCfg Z-Wave channel configuration for the selected region - * @return Status code indicating success of the function call. - * - * @note Setting a new Z-Wave Region will default any Low Power values to - * Normal Power values for the region. - * Z-Wave Region configuration must always be followed by a Low Power setup - * in case one desires to have the Low Power ACKing functionality. - */ -RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle, - const RAIL_ZWAVE_RegionConfig_t *regionCfg); - -/** - * Perform image rejection calibration on all valid channels of a - * Z-Wave region. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in, out] pIrCalVals An application-provided pointer of - * type \ref RAIL_ZWAVE_IrcalVal_t. This is populated with image rejection - * calibration values, if not NULL or initialized with - * \ref RAIL_CAL_INVALID_VALUE or if forceIrcal is true. - * @param[in] forceIrcal If true, will always perform image rejection calibration - * and not use previously cached values. - * @return Status code indicating success of the function call. - * - * Note: This function also calibrates for beam detection and should be - * called before \ref RAIL_ZWAVE_ReceiveBeam() and after the Z-Wave region - * has been configured via \ref RAIL_ZWAVE_ConfigRegion(). - * Channel hopping must be disabled otherwise this function will return - * \ref RAIL_STATUS_INVALID_CALL. - */ -RAIL_Status_t RAIL_ZWAVE_PerformIrcal(RAIL_Handle_t railHandle, - RAIL_ZWAVE_IrcalVal_t *pIrCalVals, - bool forceIrcal); -/** - * Initialize RAIL for Z-Wave features. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] config A Z-Wave configuration structure. - * @return A status code indicating success of the function call. - * - * This function is the entry point for working with Z-Wave within - * RAIL. It sets up relevant hardware acceleration for Z-Wave-specific - * features, such as HomeId filtering and beam packets (as - * specified in the configuration) and allows users to select the - * relevant Z-Wave region-specific PHY via \ref RAIL_ZWAVE_ConfigRegion. - */ -RAIL_Status_t RAIL_ZWAVE_Init(RAIL_Handle_t railHandle, - const RAIL_ZWAVE_Config_t *config); - -/** - * De-initialize Z-Wave hardware acceleration. - * - * @param[in] railHandle A handle of RAIL instance. - * @return A status code indicating success of the function call. - * - * Disables and resets all Z-Wave hardware acceleration features. This - * function should only be called when the radio is IDLE. - */ -RAIL_Status_t RAIL_ZWAVE_Deinit(RAIL_Handle_t railHandle); - -/** - * Return whether Z-Wave hardware acceleration is currently enabled. - * - * @param[in] railHandle A handle of RAIL instance. - * @return True if Z-Wave hardware acceleration was enabled to start with - * and false otherwise. - */ -bool RAIL_ZWAVE_IsEnabled(RAIL_Handle_t railHandle); - -/** - * Configure Z-Wave options. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] mask A bitmask containing which options should be modified. - * @param[in] options A bitmask containing desired configuration settings. - * Bit positions for each option are found in the \ref RAIL_ZWAVE_Options_t. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ZWAVE_ConfigOptions(RAIL_Handle_t railHandle, - RAIL_ZWAVE_Options_t mask, - RAIL_ZWAVE_Options_t options); - -/** - * Inform RAIL of the Z-Wave node's NodeId for receive filtering. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] nodeId A Z-Wave Node ID. - * @return Status code indicating success of the function call. - * - * @note Until this API is called, RAIL will assume the NodeId is - * \ref RAIL_ZWAVE_NODE_ID_DEFAULT. - */ -RAIL_Status_t RAIL_ZWAVE_SetNodeId(RAIL_Handle_t railHandle, - RAIL_ZWAVE_NodeId_t nodeId); - -/** - * Inform RAIL of the Z-Wave node's HomeId and its hash for receive filtering - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] homeId A Z-Wave HomeId. - * @param[in] homeIdHash The hash of the HomeId expected in beam frames. - * If this is \ref RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, beam frame detection - * will not check the HomeIdHash in a received beam frame at all, and - * \ref RAIL_EVENT_ZWAVE_BEAM will trigger based solely on the NodeId - * in the beam frame. - * @return Status code indicating success of the function call. - * - * @note Until this API is called, RAIL will assume the HomeId is an - * illegal one of \ref RAIL_ZWAVE_HOME_ID_DEFAULT, and its hash is \ref - * RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE. - */ -RAIL_Status_t RAIL_ZWAVE_SetHomeId(RAIL_Handle_t railHandle, - RAIL_ZWAVE_HomeId_t homeId, - RAIL_ZWAVE_HomeIdHash_t homeIdHash); - -/** - * Get the NodeId of the most recently seen beam frame that triggered - * \ref RAIL_EVENT_ZWAVE_BEAM. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pNodeId A pointer to \ref RAIL_ZWAVE_NodeId_t to populate. - * @return Status code indicating success of the function call. - * - * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent beam's NodeId - * is provided. - */ -RAIL_Status_t RAIL_ZWAVE_GetBeamNodeId(RAIL_Handle_t railHandle, - RAIL_ZWAVE_NodeId_t *pNodeId); - -/** - * Get the HomeIdHash of the most recently seen beam frame that triggered - * \ref RAIL_EVENT_ZWAVE_BEAM. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pBeamHomeIdHash A pointer to \ref RAIL_ZWAVE_HomeIdHash_t to populate. - * @return Status code indicating success of the function call. - * - * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent beam's HomeIdHash - * is provided. - */ -RAIL_Status_t RAIL_ZWAVE_GetBeamHomeIdHash(RAIL_Handle_t railHandle, - RAIL_ZWAVE_HomeIdHash_t *pBeamHomeIdHash); - -/** - * Get the channel hopping index of the most recently seen beam frame that - * triggered \ref RAIL_EVENT_ZWAVE_BEAM. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pChannelIndex A pointer to a uint8_t to populate with - * the channel hopping index. If channel-hopping was off at the time - * the beam packet was received, \ref RAIL_CHANNEL_HOPPING_INVALID_INDEX - * is provided. - * @return Status code indicating success of the function call. - * - * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent beam's - * channel hopping index is provided. - */ -RAIL_Status_t RAIL_ZWAVE_GetBeamChannelIndex(RAIL_Handle_t railHandle, - uint8_t *pChannelIndex); - -/** - * Get the TX power used by the transmitter of the most recently seen - * long range beam frame that triggered \ref RAIL_EVENT_ZWAVE_BEAM. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pLrBeamTxPower An application provided pointer to a uint8_t to - * be populated with the TX power of the latest long range beam. This will - * be set to \ref RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID if this API is called - * after receiving a regular non-long-range beam. - * @return Status code indicating success of the function call. This function - * will return \ref RAIL_STATUS_INVALID_STATE if called after receiving a - * regular (non-long-range) beam. - * - * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent long range - * beam's TX power is provided. - * - * @note The following table shows long range beam TX power value to dBm - * value mapping: - * - * - *
Tx Power Value Description - *
0 -6dBm - *
1 -2dBm - *
2 +2dBm - *
3 +6dBm - *
4 +10dBm - *
5 +13dBm - *
6 +16dBm - *
7 +19dBm - *
8 +21dBm - *
9 +23Bm - *
10 +25dBm - *
11 +26dBm - *
12 +27dBm - *
13 +28dBm - *
14 +29dBm - *
15 +30dBm - *
- */ -RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle, - uint8_t *pLrBeamTxPower); - -/** - * Get the RSSI of the received beam frame. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[out] pBeamRssi An application provided pointer to a int8_t to - * be populated with the latest beam's RSSI, in dBm. - * @return Status code indicating success of the function call. This function - * will return \ref RAIL_STATUS_INVALID_STATE if called without ever - * having received a beam. - * - * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM - * event; if multiple beams are received only the most recent beam's - * RSSI is provided. - */ -RAIL_Status_t RAIL_ZWAVE_GetBeamRssi(RAIL_Handle_t railHandle, - int8_t *pBeamRssi); -/** - * Set the Raw Low Power settings. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] powerLevel Desired low power raw level. - * @return Status code indicating success of the function call. - * - * Low Power settings are required during ACK transmissions when - * the Low Power Bit is set. This setting is only valid for one - * subsequent transmission, after which all transmissions will be - * at the nominal power setting, until re-invoked. - */ - -RAIL_Status_t RAIL_ZWAVE_SetTxLowPower(RAIL_Handle_t railHandle, - uint8_t powerLevel); - -/** - * Set the Low Power settings in dBm. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] powerLevel Desired low power level dBm. - * @return Status code indicating success of the function call. - * - * Low Power settings are required during ACK transmissions when - * the Low Power Bit is set. This setting is only valid for one - * subsequent transmission, after which all transmissions will be - * at the nominal power setting, until re-invoked. - */ -RAIL_Status_t RAIL_ZWAVE_SetTxLowPowerDbm(RAIL_Handle_t railHandle, - RAIL_TxPower_t powerLevel); - -/** - * Get the TX low power in raw units (see \ref rail_chip_specific.h for - * value ranges). - * - * @param[in] railHandle A RAIL instance handle. - * @return The chip-specific \ref RAIL_TxPowerLevel_t raw value of the low - * transmit power. - * - * This API returns the low raw power value that was set by - * \ref RAIL_ZWAVE_SetTxLowPower. - * - * Calling this function before configuring the Low Power PA - * (i.e., before a successful - * call to \ref RAIL_ZWAVE_SetTxLowPowerDbm or \ref RAIL_ZWAVE_SetTxLowPower) - * will return the low power value same as the nominal power. - * Also, calling this function before configuring the PA - * (i.e., before a successful call to \ref RAIL_ConfigTxPower) will return an error - * (RAIL_TX_POWER_LEVEL_INVALID). - */ -RAIL_TxPowerLevel_t RAIL_ZWAVE_GetTxLowPower(RAIL_Handle_t railHandle); - -/** - * Get the TX low power in terms of deci-dBm instead of raw power level. - * - * @param[in] railHandle A RAIL instance handle. - * @return The chip-specific \ref RAIL_TxPower_t value of the low - * transmit power in deci-dBm. - */ -RAIL_TxPower_t RAIL_ZWAVE_GetTxLowPowerDbm(RAIL_Handle_t railHandle); - -/** - * Implement beam detection and reception algorithms. - * It will take care of all configuration and radio setup to - * detect and receive beams in the current Z-Wave region. - * If a beam is detected, RAIL will provide - * the usual \ref RAIL_EVENT_ZWAVE_BEAM event during which time users can - * process the beam as expected. However, normal packets may also be - * received during this time (also triggering \ref RAIL_EVENTS_RX_COMPLETION - * events), in which case, this API may need to be re-called to receive - * a beam. Users should also listen for - * \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE, which will indicate - * that no beam is heard. At that point, the radio will be automatically idled. - * Until one of these events is received, users should not try to - * reconfigure radio settings or start another radio operation. If an application - * needs to do some other operation or configuration, it must first call - * \ref RAIL_Idle and wait for the radio to idle. - * - * @note: The radio must be idle before calling this function. - * - * @note: \ref RAIL_ConfigRxChannelHopping must have been called successfully - * in Z-Wave before this function is called to provide a valid memory buffer - * for internal use (see \ref RAIL_RxChannelHoppingConfig_t::buffer). - * - * @note: This function alters radio functionality substantially. After calling - * it, the user should call \ref RAIL_ZWAVE_ConfigRegion, - * \ref RAIL_ConfigRxChannelHopping, \ref RAIL_EnableRxChannelHopping, - * and \ref RAIL_SetRxTransitions to reset these parameters to whatever - * behaviors were desired before calling this function. Additionally, - * this function will idle the radio upon on exit. - * - * @param[in] railHandle A RAIL instance handle. - * @param[out] beamDetectIndex Indicator of whether or not a beam was detected - * at all, regardless of if it was received, generally for use only by instruction - * from Silicon Labs. Can be NULL. - * @param[out] schedulerInfo While Z-Wave is currently not supported in - * RAIL Multiprotocol, this scheduler info is added to future proof - * against any future version of multiprotocol which may support it. For now, - * this argument can be NULL. - * - * @return status indicating whether or not the radio was able to configure - * beam packet detection/reception. Reasons for failure include an un-idled - * radio or a non-Japan non-Korea region configured before calling this function. - */ -RAIL_Status_t RAIL_ZWAVE_ReceiveBeam(RAIL_Handle_t railHandle, - uint8_t *beamDetectIndex, - const RAIL_SchedulerInfo_t *schedulerInfo); - -/** - * Configure the receive algorithm used in \ref RAIL_ZWAVE_ReceiveBeam. - * This function should not be used without direct instruction by Silicon Labs. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in] config Configuration for beam detection algorithm. - * @return Status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle, RAIL_ZWAVE_BeamRxConfig_t *config); - -/** - * Set the default RX beam configuration. - * - * @param[in] railHandle A RAIL instance handle. - * @return Status code indicating success of the function call. - * - * @note This function resets any changes made to the beam configuration via - * \ref RAIL_ZWAVE_ConfigBeamRx and the default beam configuration will be in effect - * on subsequent call(s) to \ref RAIL_ZWAVE_ReceiveBeam. - */ -RAIL_Status_t RAIL_ZWAVE_SetDefaultRxBeamConfig(RAIL_Handle_t railHandle); - -/** - * Get the current RX beam configuration. - * - * @param[out] pConfig A pointer to \ref RAIL_ZWAVE_BeamRxConfig_t to be - * populated with the current beam configuration. - * @return A status code indicating success of the function call. - */ -RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig); - -/** - * Configure the channel hop timings for use in Z-Wave RX channel hop configuration. - * This function should not be used without direct instruction by Silicon Labs. - * - * @param[in] railHandle A RAIL instance handle. - * @param[in, out] config Configuration for Z-Wave RX channel hopping. - * This structure must be allocated in application global read-write memory. - * RAIL will populate fields within or referenced by this structure during its - * operation. Be sure to allocate \ref RAIL_RxChannelHoppingConfigEntry_t - * entries[] for \ref RAIL_NUM_ZWAVE_CHANNELS. Be sure to set \ref - * RAIL_RxChannelHoppingConfig_t::numberOfChannels to the desired number of - * channels. - * @return Status code indicating success of the function call. - * - * @note: This API must be called before \ref RAIL_EnableRxChannelHopping(). This - * API must never be called while the radio is on with RX Duty Cycle or Channel - * Hopping enabled. - */ -RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_RxChannelHoppingConfig_t *config); - -/** - * Get the Z-Wave region. - * - * @param[in] railHandle A RAIL instance handle. - * @return The \ref RAIL_ZWAVE_RegionId_t value - * - * @note: \ref RAIL_ZWAVE_ConfigRegion must have been called successfully - * before this function is called. Otherwise, \ref RAIL_ZWAVE_REGIONID_UNKNOWN - * is returned. - */ -RAIL_ZWAVE_RegionId_t RAIL_ZWAVE_GetRegion(RAIL_Handle_t railHandle); - -/** - * Write the AutoACK FIFO for the next outgoing Z-Wave Long Range ACK. - * - * @param[in] railHandle A handle of RAIL instance. - * @param[in] pLrAckData An application provided pointer to a const - * \ref RAIL_ZWAVE_LrAckData_t to populate the noise floor, TX power and receive - * rssi bytes of the outgoing Z-Wave Long Range ACK packet. - * @return A status code indicating success of the function call. - * - * This function sets the AutoACK data to use in acknowledging the frame - * being received. It must only be called while processing the \ref - * RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND. - * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to - * write the outgoing ACK. When successful, the ackData will - * only be sent once. Subsequent packets needing an Z-Wave Long Range ACK will - * each need to call this function to write the ACK information. - */ -RAIL_Status_t RAIL_ZWAVE_SetLrAckData(RAIL_Handle_t railHandle, - const RAIL_ZWAVE_LrAckData_t *pLrAckData); - -/** EU-European Union, RAIL_ZWAVE_REGION_EU */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU; - -/** US-United States, RAIL_ZWAVE_REGION_US */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US; - -/** ANZ-Australia/New Zealand, RAIL_ZWAVE_REGION_ANZ */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_ANZ; - -/** HK-Hong Kong, RAIL_ZWAVE_REGION_HK */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_HK; - -/** MY-Malaysia, RAIL_ZWAVE_REGION_MY */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_MY; - -/** IN-India, RAIL_ZWAVE_REGION_IN */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IN; - -/** JP-Japan, RAIL_ZWAVE_REGION_JP */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JP; - -/** JP-Japan, RAIL_ZWAVE_REGION_JP */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JPED; - -/** RU-Russia, RAIL_ZWAVE_REGION_RU */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_RU; - -/** IL-Israel, RAIL_ZWAVE_REGION_IL */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IL; - -/** KR-Korea, RAIL_ZWAVE_REGION_KR */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KR; - -/** KR-Korea, RAIL_ZWAVE_REGION_KR */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KRED; - -/** CN-China, RAIL_ZWAVE_REGION_CN */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_CN; - -/** US-Long Range 1, RAIL_ZWAVE_REGION_US_LR1 */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR1; - -/** US-Long Range 2, RAIL_ZWAVE_REGION_US_LR2 */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR2; - -/** US-Long Range End Device, RAIL_ZWAVE_REGION_US_LR_END_DEVICE */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR_END_DEVICE; - -/** EU-Long Range 1, RAIL_ZWAVE_REGION_EU_LR1 */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR1; - -/** EU-Long Range 2, RAIL_ZWAVE_REGION_EU_LR2 */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR2; - -/** EU-Long Range End Device, RAIL_ZWAVE_REGION_EU_LR_END_DEVICE */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR_END_DEVICE; - -/** Invalid Region */ -extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_INVALID; - -/** @} */ // end of Z_Wave - -#ifdef __cplusplus -} -#endif - -#endif // __RAIL_ZWAVE_H__ +/***************************************************************************//** + * @file + * @brief The Z-Wave specific header file for the RAIL library. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef __RAIL_ZWAVE_H__ +#define __RAIL_ZWAVE_H__ + +#include "rail_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/// @addtogroup Z_Wave Z-Wave +/// @ingroup Protocol_Specific +/// @brief Z-Wave configuration routines +/// +/// The functions in this group configure RAIL Z-Wave hardware +/// acceleration features. +/// +/// To configure Z-Wave functionality, the application must first set up +/// a RAIL instance with RAIL_Init() and other setup functions. +/// +/// @code{.c} +/// +/// RAIL_ZWAVE_NodeId_t gRecentBeamNodeId; +/// uint8_t gRecentBeamChannelIndex; +/// +/// // Main RAIL_EVENT callback +/// static void RAILCb_Event(RAIL_Handle_t railHandle, RAIL_Events_t events) +/// { +/// // Get beamNodeId and channel index from beam packet +/// if (events & RAIL_EVENT_ZWAVE_BEAM) { +/// if (RAIL_ZWAVE_IsEnabled(railHandle)) { +/// if ((RAIL_ZWAVE_GetBeamNodeId(railHandle, &gRecentBeamNodeId) +/// != RAIL_STATUS_NO_ERROR) +/// || (RAIL_ZWAVE_GetBeamChannelIndex(railHandle, &gRecentBeamChannelIndex) +/// != RAIL_STATUS_NO_ERROR)) { +/// return; +/// } +/// } +/// } +/// } +/// +/// static const RAIL_ZWAVE_Config_t zwaveConfig = { +/// .options = RAIL_ZWAVE_OPTIONS_DEFAULT +/// }; +/// +/// RAIL_Status_t zwaveInit(void) +/// { +/// // initialize Z-Wave +/// RAIL_Status_t status = RAIL_ZWAVE_Init(railHandle, &zwaveConfig); +/// +/// if (status != RAIL_STATUS_NO_ERROR) { +/// return status; +/// } +/// +/// uint8_t myHomeId[4] = { 0xDE, 0xAD, 0xBE, 0xEF }; +/// RAIL_ZWAVE_SetNodeId(railHandle, RAIL_ZWAVE_NODE_ID_DEFAULT); +/// RAIL_ZWAVE_SetHomeId(railHandle, myHomeId, RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE); +/// +/// // configure region to EU(European Union) +/// return RAIL_ZWAVE_ConfigRegion(railHandle, RAIL_ZWAVE_REGION_EU); +/// } +/// @endcode +/// +/// @{ + +/** + * @enum RAIL_ZWAVE_Options_t + * @brief Z-Wave options. + */ +RAIL_ENUM_GENERIC(RAIL_ZWAVE_Options_t, uint32_t) { + // Z-Wave Option Bit Shifts + + /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE bit */ + RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT = 0, + /** Shift position of \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES bit */ + RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT, + /** Shift position of \ref RAIL_ZWAVE_OPTION_NODE_ID_FILTERING bit */ + RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT, + /** Shift position of \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE bit */ + RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT, +}; + +// RAIL_ZWAVE_Options_t bitmasks + +/** A value representing no options */ +#define RAIL_ZWAVE_OPTIONS_NONE 0U + +/** All options are disabled by default. */ +#define RAIL_ZWAVE_OPTIONS_DEFAULT RAIL_ZWAVE_OPTIONS_NONE + +/** + * An option to configure promiscuous mode, accepting non-beam packets + * regardless of their HomeId. By default packets are filtered by their HomeId. + * When true, such filtering is disabled. + */ +#define RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE \ + (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE_SHIFT) + +/** + * An option to filter non-beam packets based on their NodeId when + * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is disabled. + * + * @note This option has no effect when + * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE is enabled. + */ +#define RAIL_ZWAVE_OPTION_NODE_ID_FILTERING \ + (1u << RAIL_ZWAVE_OPTION_NODE_ID_FILTERING_SHIFT) + +/** + * An option to configure beam frame recognition. By default beams are not + * considered special and will be received as if they were normal Z-Wave + * frames, assuredly triggering \ref RAIL_EVENT_RX_FRAME_ERROR. + * When true, beam frames that are broadcast or match the NodeId and + * HomeIdHash values will trigger \ref RAIL_EVENT_ZWAVE_BEAM event. + * (All beams additionally trigger \ref RAIL_EVENT_RX_PACKET_ABORTED + * regardless of NodeId / HomeIdHash values.) + * + * @note This option takes precedence over \ref + * RAIL_ZWAVE_OPTION_PROMISCUOUS_MODE when receiving a beam frame. + * For promiscuous beam handling see related + * \ref RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE option. + */ +#define RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES \ + (1u << RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES_SHIFT) + +/** + * An option to receive all beams promiscuously when \ref + * RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is enabled. + * When true, beam frames are received regardless of their NodeId or HomeIdHash + * resulting in \ref RAIL_EVENT_ZWAVE_BEAM (and also \ref + * RAIL_EVENT_RX_PACKET_ABORTED) for each beam frame. + * + * @note This option has no effect when + * \ref RAIL_ZWAVE_OPTION_DETECT_BEAM_FRAMES is disabled. + */ +#define RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE \ + (1u << RAIL_ZWAVE_OPTION_PROMISCUOUS_BEAM_MODE_SHIFT) + +/** A value representing all options */ +#define RAIL_ZWAVE_OPTIONS_ALL 0xFFFFFFFFU + +/** + * @enum RAIL_ZWAVE_NodeId_t + * @brief A Z-Wave Node ID. + * + * This data type is 12 bits wide when using the ZWave Long Range PHY, and + * 8 bits wide otherwise. + * + * @note When using the Long Range PHY, values 0xFA1..0xFFE are reserved. + * Otherwise, values 0xE9..0xFE are reserved. + */ +RAIL_ENUM_GENERIC(RAIL_ZWAVE_NodeId_t, uint16_t) { + /** The unknown NodeId for uninitialized nodes. */ + RAIL_ZWAVE_NODE_ID_NONE = 0x00U, + /** The broadcast NodeId. */ + RAIL_ZWAVE_NODE_ID_BROADCAST = 0xFFU, + /** Default to the broadcast NodeId. */ + RAIL_ZWAVE_NODE_ID_DEFAULT = RAIL_ZWAVE_NODE_ID_BROADCAST, + // All other values between 0x00 and 0xFE are valid node IDs normally + /** The Long Range broadcast NodeId. */ + RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE = 0xFFFU, + /** Default to the Long Range broadcast NodeId. */ + RAIL_ZWAVE_NODE_ID_DEFAULT_LONGRANGE = RAIL_ZWAVE_NODE_ID_BROADCAST_LONGRANGE, + // All values from 0x001 to 0xFA1 are valid node IDs with a Long Range PHY. +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_NODE_ID_NONE ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_NONE) +#define RAIL_ZWAVE_NODE_ID_BROADCAST ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_BROADCAST) +#define RAIL_ZWAVE_NODE_ID_DEFAULT ((RAIL_ZWAVE_NodeId_t) RAIL_ZWAVE_NODE_ID_DEFAULT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** Defines for subPhyID field in RAIL_RxPacketDetails_t */ +#define RAIL_ZWAVE_RX_SUBPHY_ID_0 (0U) +#define RAIL_ZWAVE_RX_SUBPHY_ID_1 (1U) +#define RAIL_ZWAVE_RX_SUBPHY_ID_2 (2U) +#define RAIL_ZWAVE_RX_SUBPHY_ID_3 (3U) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_ZWAVE_HomeId_t + * @brief A Z-Wave Home ID. + * + * @note Home IDs in the range 0x54000000..0x55FFFFFF are illegal. + */ +RAIL_ENUM_GENERIC(RAIL_ZWAVE_HomeId_t, uint32_t) { + RAIL_ZWAVE_HOME_ID_UNKNOWN = 0x00000000U, /**< The unknown HomeId. */ + RAIL_ZWAVE_HOME_ID_DEFAULT = 0x54545454U, /**< An impossible and unlikely HomeId. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_HOME_ID_UNKNOWN ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_UNKNOWN) +#define RAIL_ZWAVE_HOME_ID_DEFAULT ((RAIL_ZWAVE_HomeId_t) RAIL_ZWAVE_HOME_ID_DEFAULT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_ZWAVE_HomeIdHash_t + * @brief A Z-Wave Home ID hash. + * + * @note Certain values (as shown) are illegal. + */ +RAIL_ENUM(RAIL_ZWAVE_HomeIdHash_t) { + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 = 0x0AU, /**< An illegal HomeIdHash value. */ + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 = 0x4AU, /**< An illegal HomeIdHash value. */ + RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 = 0x55U, /**< An illegal HomeIdHash value. */ + RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE = 0x55U, /**< Illegal HomeIdHash value that + suppresses checking the + HomeIdHash field of beam + packets. */ + RAIL_ZWAVE_HOME_ID_HASH_DEFAULT + = RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, /**< Default to don't care. */ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_1) +#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_2) +#define RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3 ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_ILLEGAL_3) +#define RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE) +#define RAIL_ZWAVE_HOME_ID_HASH_DEFAULT ((RAIL_ZWAVE_HomeIdHash_t) RAIL_ZWAVE_HOME_ID_HASH_DEFAULT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * @struct RAIL_ZWAVE_Config_t + * @brief A configuration structure for Z-Wave in RAIL. + */ +typedef struct RAIL_ZWAVE_Config { + /** + * Defines Z-Wave options. + */ + RAIL_ZWAVE_Options_t options; + /** + * Defines Z-Wave ACKing configuration. + */ + RAIL_AutoAckConfig_t ackConfig; + /** + * Defines state timings for Z-Wave. + */ + RAIL_StateTiming_t timings; +} RAIL_ZWAVE_Config_t; + +/** + * @enum RAIL_ZWAVE_Baud_t + * @brief Z-Wave supported baudrates or PHYs. + */ +RAIL_ENUM(RAIL_ZWAVE_Baud_t) { + RAIL_ZWAVE_BAUD_9600, /**< 9.6kbps baudrate*/ + RAIL_ZWAVE_BAUD_40K, /**< 40kbps baudrate*/ + RAIL_ZWAVE_BAUD_100K, /**< 100kbps baudrate*/ + RAIL_ZWAVE_LR, /**< Long Range PHY*/ + RAIL_ZWAVE_ENERGY_DETECT = RAIL_ZWAVE_LR, /**< Energy detection PHY*/ + RAIL_ZWAVE_BAUD_INVALID /**< Sentinel value for invalid baud rate*/ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +/** + * @enum RAIL_ZWAVE_RegionOptions_t + * @brief Region Specific Physical + */ + +RAIL_ENUM(RAIL_ZWAVE_RegionOptions_t) +{ + /** Bit shift for US Long Range End Devices */ + RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT = 0, + /** Bit shift for special low side config, mostly for Japan and Korea */ + RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT = 1, + /** Bit shift for US long range range configurations */ + RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT = 2, +}; + +/** + * RAIL_ZWAVE_RegionOptions_t bitmasks + */ +/** A value representing US Long Range regions */ +#define RAIL_ZWAVE_REGION_LONG_RANGE_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_SHIFT) +/** A value representing lowside configurations: For Series 2: JP and KR, for Series 1: KR */ +#define RAIL_ZWAVE_REGION_LOW_SIDE_MASK (1u << RAIL_ZWAVE_REGION_LOW_SIDE_SHIFT) +/** A value representing Long Range End Device region */ +#define RAIL_ZWAVE_REGION_LONG_RANGE_END_MASK (1u << RAIL_ZWAVE_REGION_LONG_RANGE_END_SHIFT) +/** A value representing No bit to be enabled */ +#define RAIL_ZWAVE_REGION_SPECIFIC_NONE 0u +#endif // DOXYGEN SHOULD SKIP THIS + +/** + * Sentinel value to indicate that a channel (and thus its frequency) + * are invalid. + */ +#define RAIL_ZWAVE_FREQ_INVALID 0xFFFFFFFFUL + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_BAUD_9600 ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_9600) +#define RAIL_ZWAVE_BAUD_40K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_40K) +#define RAIL_ZWAVE_BAUD_100K ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_BAUD_100K) +#define RAIL_ZWAVE_LR ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_LR) +#define RAIL_ZWAVE_ENERGY_DETECT ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_ENERGY_DETECT) +#define RAIL_ZWAVE_INVALID ((RAIL_ZWAVE_Baud_t) RAIL_ZWAVE_INVALID) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * @enum RAIL_ZWAVE_RegionId_t + * @brief Z-Wave region identifications. + */ +RAIL_ENUM(RAIL_ZWAVE_RegionId_t) { + RAIL_ZWAVE_REGIONID_UNKNOWN, /**< Unknown/Invalid*/ + RAIL_ZWAVE_REGIONID_EU, /**< European Union*/ + RAIL_ZWAVE_REGIONID_US, /**< United States*/ + RAIL_ZWAVE_REGIONID_ANZ, /**< Australia/New Zealand*/ + RAIL_ZWAVE_REGIONID_HK, /**< Hong Kong*/ + RAIL_ZWAVE_REGIONID_MY, /**< Malaysia*/ + RAIL_ZWAVE_REGIONID_IN, /**< India*/ + RAIL_ZWAVE_REGIONID_JP, /**< Japan*/ + RAIL_ZWAVE_REGIONID_RU, /**< Russian Federation*/ + RAIL_ZWAVE_REGIONID_IL, /**< Israel*/ + RAIL_ZWAVE_REGIONID_KR, /**< Korea*/ + RAIL_ZWAVE_REGIONID_CN, /**< China*/ + RAIL_ZWAVE_REGIONID_US_LR1, /**< United States, with first long range PHY*/ + RAIL_ZWAVE_REGIONID_US_LR2, /**< United States, with second long range PHY*/ + RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE, /**< United States long range end device PHY for both LR frequencies*/ + RAIL_ZWAVE_REGIONID_EU_LR1, /**< European Union, with first long range PHY*/ + RAIL_ZWAVE_REGIONID_EU_LR2, /**< European Union, with second long range PHY*/ + RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE, /**< European Union long range end device PHY for both LR frequencies*/ + RAIL_ZWAVE_REGIONID_COUNT /**< Count of known regions, must be last*/ +}; + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Self-referencing defines minimize compiler complaints when using RAIL_ENUM +#define RAIL_ZWAVE_REGIONID_UNKNOWN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_UNKNOWN) +#define RAIL_ZWAVE_REGIONID_EU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU) +#define RAIL_ZWAVE_REGIONID_US ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US) +#define RAIL_ZWAVE_REGIONID_ANZ ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_ANZ) +#define RAIL_ZWAVE_REGIONID_HK ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_HK) +#define RAIL_ZWAVE_REGIONID_MY ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_MY) +#define RAIL_ZWAVE_REGIONID_IN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IN) +#define RAIL_ZWAVE_REGIONID_JP ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_JP) +#define RAIL_ZWAVE_REGIONID_RU ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_RU) +#define RAIL_ZWAVE_REGIONID_IL ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_IL) +#define RAIL_ZWAVE_REGIONID_KR ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_KR) +#define RAIL_ZWAVE_REGIONID_CN ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_CN) +#define RAIL_ZWAVE_REGIONID_US_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR1) +#define RAIL_ZWAVE_REGIONID_US_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR2) +#define RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_US_LR_END_DEVICE) +#define RAIL_ZWAVE_REGIONID_EU_LR1 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR1) +#define RAIL_ZWAVE_REGIONID_EU_LR2 ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR2) +#define RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_EU_LR_END_DEVICE) +#define RAIL_ZWAVE_REGIONID_COUNT ((RAIL_ZWAVE_RegionId_t) RAIL_ZWAVE_REGIONID_COUNT) +#endif //DOXYGEN_SHOULD_SKIP_THIS + +#ifndef DOXYGEN_SHOULD_SKIP_THIS +// Largest ACK timeout period based on +// aPhyTurnaroundTimeRxTx (1 ms max)+ (aMacTransferAckTimeTX (168 bits)* (1/data rate)) +// For slowest Data Rate R1 (19.6 kbit/s) +#define RAIL_ZWAVE_MAX_ACK_TIMEOUT_US (9600U) + +// Defines for Transition timing +#define RAIL_ZWAVE_TIME_IDLE_TO_RX_US (100U) +#define RAIL_ZWAVE_TIME_TX_TO_RX_US (0U) +#define RAIL_ZWAVE_TIME_IDLE_TO_TX_US (0U) +#define RAIL_ZWAVE_TIME_RX_TO_TX_US (1000U) + +#endif //DOXYGEN_SHOULD_SKIP_THIS + +/** + * Invalid beam TX power value returned when \ref RAIL_ZWAVE_GetLrBeamTxPower + * is called after receiving a regular non-long-range beam. + */ +#define RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID (0xFFU) + +/** + * @struct RAIL_ZWAVE_LrAckData_t + * @brief Configuration structure for Z-Wave Long Range ACK. + */ +typedef struct RAIL_ZWAVE_LrAckData { + /// Radio noise level measured on the channel the frame is transmitted on. + int8_t noiseFloorDbm; + /// Transmit power used to transmit the ongoing Z-Wave Long Range ACK. + int8_t txPowerDbm; + /// Signal strength measured while receiving the Z-Wave Long Range frame. + int8_t receiveRssiDbm; +} RAIL_ZWAVE_LrAckData_t; + +/** + * @struct RAIL_ZWAVE_BeamRxConfig_t + * @brief Configuration structure for Z-Wave beam detection. + * This structure should not be used without direct instruction + * by Silicon Labs. Appropriate defaults for this are built into + * the RAIL library. + */ +typedef struct RAIL_ZWAVE_BeamRxConfig { + /// Channel hopping pattern to use for beam detection. + RAIL_RxChannelHoppingConfig_t channelHoppingConfig; + /// Amount of time to spend trying to receive a beam once detected. + /// 100kbps only + RAIL_RxDutyCycleConfig_t receiveConfig_100; + /// Amount of time to spend trying to receive a beam once detected. + /// 40kbps only + RAIL_RxDutyCycleConfig_t receiveConfig_40; +} RAIL_ZWAVE_BeamRxConfig_t; + +/** + * Number of channels in each of Z-Wave's region-based PHYs + */ +#define RAIL_NUM_ZWAVE_CHANNELS (4U) + +/** + * @struct RAIL_ZWAVE_RegionConfig_t + * @brief Each Z-Wave region supports 3 channels. + */ +typedef struct RAIL_ZWAVE_RegionConfig { + uint32_t frequency[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel frequency in hertz*/ + RAIL_TxPower_t maxPower[RAIL_NUM_ZWAVE_CHANNELS]; /**< The maximum power allowed on the channel*/ + RAIL_ZWAVE_Baud_t baudRate[RAIL_NUM_ZWAVE_CHANNELS]; /**< Channel baud rate index*/ + RAIL_ZWAVE_RegionId_t regionId; /**< Identification number for the region*/ + RAIL_ZWAVE_RegionOptions_t regionSpecific; /**< Encapsulates region specific data*/ +} RAIL_ZWAVE_RegionConfig_t; + +/** + * @struct RAIL_ZWAVE_IrcalVal_t + * @brief Structure for Z-Wave Image Rejection Calibration. + * + * @note Index 0 will hold the low side image rejection calibration value (channel 0), + * while index 1 will hold the high side image rejection value (channel 1). + */ +typedef struct RAIL_ZWAVE_IrcalVal { + RAIL_IrCalValues_t imageRejection[2]; /**< Low side and high side image rejection values*/ +} RAIL_ZWAVE_IrcalVal_t; + +/** + * @typedef RAIL_RxChannelHoppingParameters_t + * @brief Rx channel hopping on-channel time for all Z-Wave channels in a region + */ +typedef RAIL_RxChannelHoppingParameter_t RAIL_RxChannelHoppingParameters_t[RAIL_NUM_ZWAVE_CHANNELS]; + +/** + * Switch the Z-Wave region. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] regionCfg Z-Wave channel configuration for the selected region + * @return Status code indicating success of the function call. + * + * @note Setting a new Z-Wave Region will default any Low Power values to + * Normal Power values for the region. + * Z-Wave Region configuration must always be followed by a Low Power setup + * in case one desires to have the Low Power ACKing functionality. + */ +RAIL_Status_t RAIL_ZWAVE_ConfigRegion(RAIL_Handle_t railHandle, + const RAIL_ZWAVE_RegionConfig_t *regionCfg); + +/** + * Perform image rejection calibration on all valid channels of a + * Z-Wave region. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in, out] pIrCalVals An application-provided pointer of + * type \ref RAIL_ZWAVE_IrcalVal_t. This is populated with image rejection + * calibration values, if not NULL or initialized with + * \ref RAIL_CAL_INVALID_VALUE or if forceIrcal is true. + * @param[in] forceIrcal If true, will always perform image rejection calibration + * and not use previously cached values. + * @return Status code indicating success of the function call. + * + * Note: This function also calibrates for beam detection and should be + * called before \ref RAIL_ZWAVE_ReceiveBeam() and after the Z-Wave region + * has been configured via \ref RAIL_ZWAVE_ConfigRegion(). + * Channel hopping must be disabled otherwise this function will return + * \ref RAIL_STATUS_INVALID_CALL. + */ +RAIL_Status_t RAIL_ZWAVE_PerformIrcal(RAIL_Handle_t railHandle, + RAIL_ZWAVE_IrcalVal_t *pIrCalVals, + bool forceIrcal); +/** + * Initialize RAIL for Z-Wave features. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] config A Z-Wave configuration structure. + * @return A status code indicating success of the function call. + * + * This function is the entry point for working with Z-Wave within + * RAIL. It sets up relevant hardware acceleration for Z-Wave-specific + * features, such as HomeId filtering and beam packets (as + * specified in the configuration) and allows users to select the + * relevant Z-Wave region-specific PHY via \ref RAIL_ZWAVE_ConfigRegion. + */ +RAIL_Status_t RAIL_ZWAVE_Init(RAIL_Handle_t railHandle, + const RAIL_ZWAVE_Config_t *config); + +/** + * De-initialize Z-Wave hardware acceleration. + * + * @param[in] railHandle A handle of RAIL instance. + * @return A status code indicating success of the function call. + * + * Disables and resets all Z-Wave hardware acceleration features. This + * function should only be called when the radio is IDLE. + */ +RAIL_Status_t RAIL_ZWAVE_Deinit(RAIL_Handle_t railHandle); + +/** + * Return whether Z-Wave hardware acceleration is currently enabled. + * + * @param[in] railHandle A handle of RAIL instance. + * @return True if Z-Wave hardware acceleration was enabled to start with + * and false otherwise. + */ +bool RAIL_ZWAVE_IsEnabled(RAIL_Handle_t railHandle); + +/** + * Configure Z-Wave options. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] mask A bitmask containing which options should be modified. + * @param[in] options A bitmask containing desired configuration settings. + * Bit positions for each option are found in the \ref RAIL_ZWAVE_Options_t. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ZWAVE_ConfigOptions(RAIL_Handle_t railHandle, + RAIL_ZWAVE_Options_t mask, + RAIL_ZWAVE_Options_t options); + +/** + * Inform RAIL of the Z-Wave node's NodeId for receive filtering. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] nodeId A Z-Wave Node ID. + * @return Status code indicating success of the function call. + * + * @note Until this API is called, RAIL will assume the NodeId is + * \ref RAIL_ZWAVE_NODE_ID_DEFAULT. + */ +RAIL_Status_t RAIL_ZWAVE_SetNodeId(RAIL_Handle_t railHandle, + RAIL_ZWAVE_NodeId_t nodeId); + +/** + * Inform RAIL of the Z-Wave node's HomeId and its hash for receive filtering + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] homeId A Z-Wave HomeId. + * @param[in] homeIdHash The hash of the HomeId expected in beam frames. + * If this is \ref RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE, beam frame detection + * will not check the HomeIdHash in a received beam frame at all, and + * \ref RAIL_EVENT_ZWAVE_BEAM will trigger based solely on the NodeId + * in the beam frame. + * @return Status code indicating success of the function call. + * + * @note Until this API is called, RAIL will assume the HomeId is an + * illegal one of \ref RAIL_ZWAVE_HOME_ID_DEFAULT, and its hash is \ref + * RAIL_ZWAVE_HOME_ID_HASH_DONT_CARE. + */ +RAIL_Status_t RAIL_ZWAVE_SetHomeId(RAIL_Handle_t railHandle, + RAIL_ZWAVE_HomeId_t homeId, + RAIL_ZWAVE_HomeIdHash_t homeIdHash); + +/** + * Get the NodeId of the most recently seen beam frame that triggered + * \ref RAIL_EVENT_ZWAVE_BEAM. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pNodeId A pointer to \ref RAIL_ZWAVE_NodeId_t to populate. + * @return Status code indicating success of the function call. + * + * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM + * event; if multiple beams are received only the most recent beam's NodeId + * is provided. + */ +RAIL_Status_t RAIL_ZWAVE_GetBeamNodeId(RAIL_Handle_t railHandle, + RAIL_ZWAVE_NodeId_t *pNodeId); + +/** + * Get the HomeIdHash of the most recently seen beam frame that triggered + * \ref RAIL_EVENT_ZWAVE_BEAM. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pBeamHomeIdHash A pointer to \ref RAIL_ZWAVE_HomeIdHash_t to populate. + * @return Status code indicating success of the function call. + * + * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM + * event; if multiple beams are received only the most recent beam's HomeIdHash + * is provided. + */ +RAIL_Status_t RAIL_ZWAVE_GetBeamHomeIdHash(RAIL_Handle_t railHandle, + RAIL_ZWAVE_HomeIdHash_t *pBeamHomeIdHash); + +/** + * Get the channel hopping index of the most recently seen beam frame that + * triggered \ref RAIL_EVENT_ZWAVE_BEAM. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pChannelIndex A pointer to a uint8_t to populate with + * the channel hopping index. If channel-hopping was off at the time + * the beam packet was received, \ref RAIL_CHANNEL_HOPPING_INVALID_INDEX + * is provided. + * @return Status code indicating success of the function call. + * + * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM + * event; if multiple beams are received only the most recent beam's + * channel hopping index is provided. + */ +RAIL_Status_t RAIL_ZWAVE_GetBeamChannelIndex(RAIL_Handle_t railHandle, + uint8_t *pChannelIndex); + +/** + * Get the TX power used by the transmitter of the most recently seen + * long range beam frame that triggered \ref RAIL_EVENT_ZWAVE_BEAM. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pLrBeamTxPower An application provided pointer to a uint8_t to + * be populated with the TX power of the latest long range beam. This will + * be set to \ref RAIL_ZWAVE_LR_BEAM_TX_POWER_INVALID if this API is called + * after receiving a regular non-long-range beam. + * @return Status code indicating success of the function call. This function + * will return \ref RAIL_STATUS_INVALID_STATE if called after receiving a + * regular (non-long-range) beam. + * + * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM + * event; if multiple beams are received only the most recent long range + * beam's TX power is provided. + * + * @note The following table shows long range beam TX power value to dBm + * value mapping: + * + * + *
Tx Power Value Description + *
0 -6dBm + *
1 -2dBm + *
2 +2dBm + *
3 +6dBm + *
4 +10dBm + *
5 +13dBm + *
6 +16dBm + *
7 +19dBm + *
8 +21dBm + *
9 +23Bm + *
10 +25dBm + *
11 +26dBm + *
12 +27dBm + *
13 +28dBm + *
14 +29dBm + *
15 +30dBm + *
+ */ +RAIL_Status_t RAIL_ZWAVE_GetLrBeamTxPower(RAIL_Handle_t railHandle, + uint8_t *pLrBeamTxPower); + +/** + * Get the RSSI of the received beam frame. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[out] pBeamRssi An application provided pointer to a int8_t to + * be populated with the latest beam's RSSI, in dBm. + * @return Status code indicating success of the function call. This function + * will return \ref RAIL_STATUS_INVALID_STATE if called without ever + * having received a beam. + * + * @note This is best called while handling the \ref RAIL_EVENT_ZWAVE_BEAM + * event; if multiple beams are received only the most recent beam's + * RSSI is provided. + */ +RAIL_Status_t RAIL_ZWAVE_GetBeamRssi(RAIL_Handle_t railHandle, + int8_t *pBeamRssi); +/** + * Set the Raw Low Power settings. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] powerLevel Desired low power raw level. + * @return Status code indicating success of the function call. + * + * Low Power settings are required during ACK transmissions when + * the Low Power Bit is set. This setting is only valid for one + * subsequent transmission, after which all transmissions will be + * at the nominal power setting, until re-invoked. + */ + +RAIL_Status_t RAIL_ZWAVE_SetTxLowPower(RAIL_Handle_t railHandle, + uint8_t powerLevel); + +/** + * Set the Low Power settings in dBm. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] powerLevel Desired low power level dBm. + * @return Status code indicating success of the function call. + * + * Low Power settings are required during ACK transmissions when + * the Low Power Bit is set. This setting is only valid for one + * subsequent transmission, after which all transmissions will be + * at the nominal power setting, until re-invoked. + */ +RAIL_Status_t RAIL_ZWAVE_SetTxLowPowerDbm(RAIL_Handle_t railHandle, + RAIL_TxPower_t powerLevel); + +/** + * Get the TX low power in raw units (see \ref rail_chip_specific.h for + * value ranges). + * + * @param[in] railHandle A RAIL instance handle. + * @return The chip-specific \ref RAIL_TxPowerLevel_t raw value of the low + * transmit power. + * + * This API returns the low raw power value that was set by + * \ref RAIL_ZWAVE_SetTxLowPower. + * + * Calling this function before configuring the Low Power PA + * (i.e., before a successful + * call to \ref RAIL_ZWAVE_SetTxLowPowerDbm or \ref RAIL_ZWAVE_SetTxLowPower) + * will return the low power value same as the nominal power. + * Also, calling this function before configuring the PA + * (i.e., before a successful call to \ref RAIL_ConfigTxPower) will return an error + * (RAIL_TX_POWER_LEVEL_INVALID). + */ +RAIL_TxPowerLevel_t RAIL_ZWAVE_GetTxLowPower(RAIL_Handle_t railHandle); + +/** + * Get the TX low power in terms of deci-dBm instead of raw power level. + * + * @param[in] railHandle A RAIL instance handle. + * @return The chip-specific \ref RAIL_TxPower_t value of the low + * transmit power in deci-dBm. + */ +RAIL_TxPower_t RAIL_ZWAVE_GetTxLowPowerDbm(RAIL_Handle_t railHandle); + +/** + * Implement beam detection and reception algorithms. + * It will take care of all configuration and radio setup to + * detect and receive beams in the current Z-Wave region. + * If a beam is detected, RAIL will provide + * the usual \ref RAIL_EVENT_ZWAVE_BEAM event during which time users can + * process the beam as expected. However, normal packets may also be + * received during this time (also triggering \ref RAIL_EVENTS_RX_COMPLETION + * events), in which case, this API may need to be re-called to receive + * a beam. Users should also listen for + * \ref RAIL_EVENT_RX_CHANNEL_HOPPING_COMPLETE, which will indicate + * that no beam is heard. At that point, the radio will be automatically idled. + * Until one of these events is received, users should not try to + * reconfigure radio settings or start another radio operation. If an application + * needs to do some other operation or configuration, it must first call + * \ref RAIL_Idle and wait for the radio to idle. + * + * @note: The radio must be idle before calling this function. + * + * @note: \ref RAIL_ConfigRxChannelHopping must have been called successfully + * in Z-Wave before this function is called to provide a valid memory buffer + * for internal use (see \ref RAIL_RxChannelHoppingConfig_t::buffer). + * + * @note: This function alters radio functionality substantially. After calling + * it, the user should call \ref RAIL_ZWAVE_ConfigRegion, + * \ref RAIL_ConfigRxChannelHopping, \ref RAIL_EnableRxChannelHopping, + * and \ref RAIL_SetRxTransitions to reset these parameters to whatever + * behaviors were desired before calling this function. Additionally, + * this function will idle the radio upon on exit. + * + * @param[in] railHandle A RAIL instance handle. + * @param[out] beamDetectIndex Indicator of whether or not a beam was detected + * at all, regardless of if it was received, generally for use only by instruction + * from Silicon Labs. Can be NULL. + * @param[out] schedulerInfo While Z-Wave is currently not supported in + * RAIL Multiprotocol, this scheduler info is added to future proof + * against any future version of multiprotocol which may support it. For now, + * this argument can be NULL. + * + * @return status indicating whether or not the radio was able to configure + * beam packet detection/reception. Reasons for failure include an un-idled + * radio or a non-Japan non-Korea region configured before calling this function. + */ +RAIL_Status_t RAIL_ZWAVE_ReceiveBeam(RAIL_Handle_t railHandle, + uint8_t *beamDetectIndex, + const RAIL_SchedulerInfo_t *schedulerInfo); + +/** + * Configure the receive algorithm used in \ref RAIL_ZWAVE_ReceiveBeam. + * This function should not be used without direct instruction by Silicon Labs. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in] config Configuration for beam detection algorithm. + * @return Status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ZWAVE_ConfigBeamRx(RAIL_Handle_t railHandle, RAIL_ZWAVE_BeamRxConfig_t *config); + +/** + * Set the default RX beam configuration. + * + * @param[in] railHandle A RAIL instance handle. + * @return Status code indicating success of the function call. + * + * @note This function resets any changes made to the beam configuration via + * \ref RAIL_ZWAVE_ConfigBeamRx and the default beam configuration will be in effect + * on subsequent call(s) to \ref RAIL_ZWAVE_ReceiveBeam. + */ +RAIL_Status_t RAIL_ZWAVE_SetDefaultRxBeamConfig(RAIL_Handle_t railHandle); + +/** + * Get the current RX beam configuration. + * + * @param[out] pConfig A pointer to \ref RAIL_ZWAVE_BeamRxConfig_t to be + * populated with the current beam configuration. + * @return A status code indicating success of the function call. + */ +RAIL_Status_t RAIL_ZWAVE_GetRxBeamConfig(RAIL_ZWAVE_BeamRxConfig_t *pConfig); + +/** + * Configure the channel hop timings for use in Z-Wave RX channel hop configuration. + * This function should not be used without direct instruction by Silicon Labs. + * + * @param[in] railHandle A RAIL instance handle. + * @param[in, out] config Configuration for Z-Wave RX channel hopping. + * This structure must be allocated in application global read-write memory. + * RAIL will populate fields within or referenced by this structure during its + * operation. Be sure to allocate \ref RAIL_RxChannelHoppingConfigEntry_t + * entries[] for \ref RAIL_NUM_ZWAVE_CHANNELS. Be sure to set \ref + * RAIL_RxChannelHoppingConfig_t::numberOfChannels to the desired number of + * channels. + * @return Status code indicating success of the function call. + * + * @note: This API must be called before \ref RAIL_EnableRxChannelHopping(). This + * API must never be called while the radio is on with RX Duty Cycle or Channel + * Hopping enabled. + */ +RAIL_Status_t RAIL_ZWAVE_ConfigRxChannelHopping(RAIL_Handle_t railHandle, RAIL_RxChannelHoppingConfig_t *config); + +/** + * Get the Z-Wave region. + * + * @param[in] railHandle A RAIL instance handle. + * @return The \ref RAIL_ZWAVE_RegionId_t value + * + * @note: \ref RAIL_ZWAVE_ConfigRegion must have been called successfully + * before this function is called. Otherwise, \ref RAIL_ZWAVE_REGIONID_UNKNOWN + * is returned. + */ +RAIL_ZWAVE_RegionId_t RAIL_ZWAVE_GetRegion(RAIL_Handle_t railHandle); + +/** + * Write the AutoACK FIFO for the next outgoing Z-Wave Long Range ACK. + * + * @param[in] railHandle A handle of RAIL instance. + * @param[in] pLrAckData An application provided pointer to a const + * \ref RAIL_ZWAVE_LrAckData_t to populate the noise floor, TX power and receive + * rssi bytes of the outgoing Z-Wave Long Range ACK packet. + * @return A status code indicating success of the function call. + * + * This function sets the AutoACK data to use in acknowledging the frame + * being received. It must only be called while processing the \ref + * RAIL_EVENT_ZWAVE_LR_ACK_REQUEST_COMMAND. + * This will return \ref RAIL_STATUS_INVALID_STATE if it is too late to + * write the outgoing ACK. When successful, the ackData will + * only be sent once. Subsequent packets needing an Z-Wave Long Range ACK will + * each need to call this function to write the ACK information. + */ +RAIL_Status_t RAIL_ZWAVE_SetLrAckData(RAIL_Handle_t railHandle, + const RAIL_ZWAVE_LrAckData_t *pLrAckData); + +/** EU-European Union, RAIL_ZWAVE_REGION_EU */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU; + +/** US-United States, RAIL_ZWAVE_REGION_US */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US; + +/** ANZ-Australia/New Zealand, RAIL_ZWAVE_REGION_ANZ */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_ANZ; + +/** HK-Hong Kong, RAIL_ZWAVE_REGION_HK */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_HK; + +/** MY-Malaysia, RAIL_ZWAVE_REGION_MY */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_MY; + +/** IN-India, RAIL_ZWAVE_REGION_IN */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IN; + +/** JP-Japan, RAIL_ZWAVE_REGION_JP */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JP; + +/** JP-Japan, RAIL_ZWAVE_REGION_JP */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_JPED; + +/** RU-Russia, RAIL_ZWAVE_REGION_RU */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_RU; + +/** IL-Israel, RAIL_ZWAVE_REGION_IL */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_IL; + +/** KR-Korea, RAIL_ZWAVE_REGION_KR */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KR; + +/** KR-Korea, RAIL_ZWAVE_REGION_KR */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_KRED; + +/** CN-China, RAIL_ZWAVE_REGION_CN */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_CN; + +/** US-Long Range 1, RAIL_ZWAVE_REGION_US_LR1 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR1; + +/** US-Long Range 2, RAIL_ZWAVE_REGION_US_LR2 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR2; + +/** US-Long Range End Device, RAIL_ZWAVE_REGION_US_LR_END_DEVICE */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_US_LR_END_DEVICE; + +/** EU-Long Range 1, RAIL_ZWAVE_REGION_EU_LR1 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR1; + +/** EU-Long Range 2, RAIL_ZWAVE_REGION_EU_LR2 */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR2; + +/** EU-Long Range End Device, RAIL_ZWAVE_REGION_EU_LR_END_DEVICE */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_EU_LR_END_DEVICE; + +/** Invalid Region */ +extern const RAIL_ZWAVE_RegionConfig_t RAIL_ZWAVE_REGION_INVALID; + +/** @} */ // end of Z_Wave + +#ifdef __cplusplus +} +#endif + +#endif // __RAIL_ZWAVE_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager.h index e091ad6..c44b026 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager.h @@ -1,472 +1,472 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_H -#define SL_SE_MANAGER_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -/***************************************************************************//** - * @addtogroup sl_se_manager Secure Engine Manager - * - * @note The APIs are thread-safe. - * - * @{ - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup sl_se_manager_core Core - * - * @brief - * Secure Engine Manager Core API - * - * @details - * API for initialization of SE Manager and SE command context with yield - * attribute. - * - * @{ - ******************************************************************************/ - -#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - #include "sl_se_manager_key_handling.h" - #include "sl_se_manager_cipher.h" -#endif // SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT -#include "sl_se_manager_types.h" - -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Initialize the SE Manager. - * - * @details - * Initialize the SE Manager by checking hardware availability and setting up - * internal module specific resources like mutexes etc. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_init(void); - -/***************************************************************************//** - * @brief - * Denitialize the SE Manager. - * - * @details - * Free resources held by the SE Manager. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_deinit(void); - -#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) -/***************************************************************************//** - * @brief - * Set the yield attribute of the SE command context object. - * - * @param[in,out] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] yield - * The user may set this parameter to true in order to tell the SE Manager - * to yield the cpu core while waiting for the SE mailbox command to complete. - * If false, the SE Manager will busy-wait, by polling the SE mailbox response - * register until the SE mailbox command completes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx, - bool yield); -#endif // !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT - -#if defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) -/***************************************************************************//** - * @brief - * From VSE mailbox read which command, if any, was executed. - * - * @param[in,out] cmd_ctx - * Pointer to an SE command context object. If this function returns - * SL_STATUS_OK the command word of the SE command context object will be set. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_read_executed_command(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Acknowledge and get status and output data of a completed command. - * - * @details - * This function acknowledges and gets the status and output data of a - * completed mailbox command. The acknowledge operation invalidates the - * contents of the output mailbox. The output data is copied into the linked - * list of output buffers pointed to in the given command data structure. - * - * @param[in,out] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_ack_command(sl_se_command_context_t *cmd_ctx); -#endif //defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -/***************************************************************************//** - * @brief - * Initialize an SE command context object - * - * @details - * Initialize an SE command context which can be used in subsequent calls to - * the SE Manager API in order to execute SE mailbox commands. - * - * @param[in,out] cmd_ctx - * Pointer to an SE command context object to be initialized. This context - * object should be used in subsequent calls to the SE Manager API in order - * to execute SE mailbox commands. The same command context object cannot be - * used concurrently, e.g. by two different threads. However a command context - * object may be reused for the next and any subsequent mailbox operatons, - * except when streaming commands are in progress in which case only streaming - * commands of the same operation type is allowed until the streaming operation - * is finished (i.e. the corresponding sl_se_xxx_finish is called). - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_init_command_context(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * De-initialize an SE command context - * - * @details - * De-initialize an SE command context object. - * - * @param[in,out] cmd_ctx - * Pointer to an SE command context object to deinitialize. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_deinit_command_context(sl_se_command_context_t *cmd_ctx); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_core) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_H - -// THE REST OF THE FILE IS DOCUMENTATION ONLY -/// @addtogroup sl_se_manager Secure Engine Manager API -/// @brief Silicon Labs Secure Engine Manager -/// @{ -/// -/// @details -/// # Introduction -/// -/// The Secure Engine (SE) Manager provides thread-safe APIs for the Secure Engine's mailbox interface. Note that PSA Crypto is the main device independant crypto API and should be used -/// whenever possible. Visit the Mbed TLS & PSA Crypto documentation hub for more details. The SE manager APIs can be used directly -/// for performance or space constrained applications. -/// -/// Available functionality will vary between devices: device management, such as secure firmware upgrade, secure boot and secure debug implementation, is available on all series 2 devices. -/// Devices with the SE subsystem includes a low level crypto API where the SE Manager will use the SE hardware peripherals to accelerate cryptographic operations. Finally, Vault High -/// devices also include secure key storage functionality, anti-tamper protection, advanced crypto API and attestation. -/// -/// @note Below are some of the useful application notes linked with Secure Engine Manager:\n -/// AN1190: Series 2 Secure Debug\n -/// AN1247: Anti-Tamper Protection Configuration and Use\n -/// AN1268: Authenticating Silicon Labs Devices Using Device Certificates\n -/// AN1271: Secure Key Storage\n -/// AN1218: Series 2 Secure Boot with RTSL\n -/// -/// # Functionality -/// -/// The functionality of the SE Manager includes -/// -/// - Core API, inititalizing of SE Manager and SE command context (@ref sl_se_manager_core) -/// - Secure key storage (@ref sl_se_manager_key_handling) -/// - Key wrapping -/// - Storing keys in the SE volatile storage -/// - Using key by reference -/// - Configuration of tamper responses (@ref sl_se_manager_util) -/// - The available signals include core hard-fault, glitch detectors, PRS, and failed authenticated commands, -/// while the responses vary from triggering an interrupt to the hardware autonomously erasing the one-time-programmable (OTP) memory -/// - Block ciphers (@ref sl_se_manager_cipher) -/// - Supports AES-ECB, AES-CBC, AES-CFB128, AES-CFB8, AES-CTR, AES-CCM, AES-GCM, CMAC, HMAC and ChaCha20/Poly1305 -/// - The cipher operations can be performed using plaintext keys, wrapped keys or referencing a key in the SE -/// - Streaming operations are supported for AES-GCM and CMAC -/// - Block and streaming hash operations (@ref sl_se_manager_hash) -/// - Supports SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 -/// - True Random Number Generator (@ref sl_se_manager_entropy) -/// - Hardware block inside the SE used for generating random numbers. Can be used as a source of entropy, or to securely generate keys inside the SE -/// - Elliptic Curve Signature operation (@ref sl_se_manager_signature) -/// - ECDSA and EDDSA -/// - Key agreement (@ref sl_se_manager_key_derivation) -/// - Perform Elliptic Curve Diffie-Hellman and J-PAKE key agreement operations inside the SE -/// - Key derivation functions (@ref sl_se_manager_key_derivation) -/// - Perform HKDF and PBKDF2 key derivation functions inside the SE -/// - Device configuration and utilities (@ref sl_se_manager_util) -/// - Write to user data stored inside the SE -/// - Configuration of debug locks -/// - Configuration of secure boot -/// - Configuration of flash lock -/// - Read SE OTP contents -/// - Read SE firmware version -/// - Read provisioned certificates -/// - Multi-thread safe APIs for MicriumOS and FreeRTOS -/// - Retrieveing attestation tokens (@ref sl_se_manager_attestation) -/// -/// ## Key Storage and Use of SE Wrapped Keys -/// -/// The way keys are stored and operated on depends on the options set in the key descriptor used (@ref sl_se_key_descriptor_t). -/// Each key descriptor is initialized with a storage location, a key type, and length of the key (some key types have a known length, and it is not required to be set). -/// The storage location can either be application memory or inside the SE, for more details, see @ref sl_se_storage_method_t. -/// Depending on the use-case, the key descriptors will also store the pointer to a key and an SE key slot, see @ref sl_se_key_slot_t for the list of available internal SE key slots. -/// -/// For more information on the key handling APIs see @ref sl_se_manager_key_handling. -/// -/// ### Supported Key Types -/// Symmetric keys -/// - AES-128 (16 bytes) -/// - AES-192 (24 bytes) -/// - AES-256 (32 bytes) -/// - ChaCha20 (32 bytes) -/// -/// Asymmetric keys for ECC -/// - NIST P-192 -/// - NIST P-256 -/// - NIST P-384 -/// - NIST P-521 -/// - Curve25519 -/// - Curve448 -/// -/// Custom Weierstrass Prime curves are also supported (@ref sl_se_custom_weierstrass_prime_domain_t). -/// -/// ### Example Usage of Keys -/// -/// @code{.c} -/// #define WRAPPED_KEY_OVERHEAD (12UL + 16UL) -/// #define AES_256_KEY_SIZE 32UL -/// -/// uint8_t key_buffer[AES_256_KEY_SIZE]; -/// uint8_t wrapped_key_buffer[AES_256_KEY_SIZE + WRAPPED_KEY_OVERHEAD]; -/// -/// void demo_se_create_key_in_slot(void) { -/// sl_se_key_descriptor_t new_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, -/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, -/// }; -/// sl_se_generate_key(&new_key); -/// } -/// -/// void demo_se_create_plaintext_key(void) { -/// sl_se_key_descriptor_t new_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, -/// }; -/// new_key.storage.location.buffer.pointer = key_buffer; -/// new_key.storage.location.buffer.size = sizeof(key_buffer); -/// sl_se_generate_key(&new_key); -/// } -/// -/// void demo_se_create_wrapped_key(void) { -/// sl_se_key_descriptor_t new_wrapped_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, -/// }; -/// new_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer; -/// new_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer); -/// sl_se_generate_key(&new_wrapped_key); -/// } -/// -/// void demo_se_wrapped_key_to_volatile_slot(void) { -/// sl_se_key_descriptor_t existing_wrapped_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, -/// }; -/// existing_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer; -/// existing_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer); -/// sl_se_key_descriptor_t key_in_slot = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, -/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, -/// }; -/// sl_se_import_key(&existing_wrapped_key, &key_in_slot); -/// } -/// -/// void demo_se_volatile_slot_to_wrapped_key(void) { -/// sl_se_key_descriptor_t existing_volatile_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, -/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, -/// }; -/// sl_se_key_descriptor_t wrapped_key_out = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, -/// }; -/// wrapped_key_out.storage.location.buffer.pointer = wrapped_key_buffer; -/// wrapped_key_out.storage.location.buffer.size = sizeof(wrapped_key_buffer); -/// sl_se_export_key(&existing_volatile_key, &wrapped_key_out); -/// } -/// -/// void demo_se_delete_from_volatile_slot(void) { -/// sl_se_key_descriptor_t existing_volatile_key = { -/// .type = SL_SE_KEY_TYPE_AES_256, -/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, -/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, -/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, -/// }; -/// sl_se_delete_key(&existing_volatile_key); -/// } -/// @endcode -/// -/// ## Tamper -/// -/// The Secure Engine (SE) tamper module connects a number of hardware and software-driven tamper signals to a set of configurable hardware and software responses. -/// This can be used to program the device to automatically respond to external events that could signal that someone is trying to tamper with the device, -/// and very rapidly remove secrets stored in the SE. The available tamper signals range from signals based on failed authentication and secure boot to specialized glitch detectors. -/// When any of these signals fire, the tamper block can be configured to trigger several different responses, -/// ranging from triggering an interrupt to erasing the one-time-programmable (OTP) memory, removing all SE secrets and resulting in a permanently destroyed device. -/// -/// A tamper signal can lead to a series of different autonomous responses from the tamper module. These responses are listed in the table below. -/// | | Response | Description | -/// | ----: | :----: | :---- | -/// | 0 | Ignore | No action is taken. | -/// | 1 | Interrupt | The SETAMPERHOST interrupt on the host is triggered. | -/// | 2 | Filter | A counter in the tamper filter is increased. | -/// | 4 | Reset | The device is reset. | -/// | 7 | Erase OTP | Erases the OTP configuration of the device. | -/// -/// These responses are cumulative, meaning that if a filter response is triggered, an interrupt will also be triggered. For a full overview of the tamper signals, see @ref sl_se_manager_defines.h. -/// -/// The tamper configuration is one-time-programmable, and is done using the initialise OTP command to the SE (see @ref sl_se_init_otp). -/// This means that tamper settings must be written together with secure boot settings, and are immutable after they are written. -/// After tamper has been initialized, it is possible to temporarily disable one or several tamper signals using an authenticated command, -/// similar to secure debug unlock. This is only possible if the debug public key has been installed on the device. -/// It is only possible to disable the customer enabled response. The default response to a signal cannot be disabled. -/// -/// Tamper is configured by providing the following: -/// -/// -///
Tamper configuration table
Setting Description -///
Tamper response levels A response level for each tamper signal.\n\n It is not possible to degrade the default response level of a tamper signal, so if a response is set to a lower level than the default response level listed in the table in the Signals section, this won't have any effect. -///
Filter settings The tamper filter counter has two settings: -///
    -///
  • Reset period -///
  • Trigger threshold -///
-/// These options can be set to the values given in the tables in the Response Filter section. Please see the examples section for a suggested use of the tamper filter signal. -///
Flags The tamper flags is used to configure two options: -///
    -///
  • Digital Glitch Detector Always On – This option will keep the digital glitch detector running even while the SE is not performing any operations. This leads to increased energy consumption. -///
  • Keep Tamper Alive During Sleep (not available on EFR32xG21B devices) – If set, the tamper module keeps running at sleep mode (down to EM3). -///
-///
Reset threshold The number of consecutive tamper resets before the the part enters debug mode.\n\n -/// If the threshold is set to 0, the part will never enter the debug mode due to tamper reset. -///
-/// -/// ### Example Usage -/// -/// The glitch detectors can see spurious activations, and should typically not be used to directly drive a serious tamper response. -/// Instead they should feed their signals into a tamper interrupt (to handle the response logic on the M33), or into the tamper filter counter, -/// which can be used to activate a high level response if a number of incidents occur in a short time window. -/// The time period and counter threshold must be tuned to the use case. In the following example the device will erase OTP and become inoperable if 4 glitch signals is seen in a 1 minute time period. -/// -/// Since you can only configure tamper once for each device, please make sure that this is the configuration you actually want before you execute this example on actual device. -/// -/// @code{.c} -/// sl_se_otp_init_t otp_settings_init = SL_SE_OTP_INIT_DEFAULT; -/// -/// // Configure tamper levels -/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_FILTER] = SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP; -/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHFALLING] = SL_SE_TAMPER_LEVEL_FILTER; -/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHRISING] = SL_SE_TAMPER_LEVEL_FILTER; -/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_DGLITCH] = SL_SE_TAMPER_LEVEL_FILTER; -/// -/// -/// // Configure tamper filter options -/// otp_settings_init.tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_1MIN; -/// otp_settings_init.tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4; -/// -/// -/// // Commit OTP settings. This command is only available once! -/// sl_se_init_otp(&otp_settings_init); -/// @endcode -/// -/// ## RTOS Mode and Multi-Thread Safety -/// -/// @note The SE Manager API is multi-thread safe, but does not support preemption. -/// This means the API cannot be called from ISR or critical/atomic sections when running in an RTOS thread. -/// When using the SE Manager API in a bare-metal application, it is the application developer's responsibility -/// to not call the SE Manager APIs when another operation is in progress. -/// -/// The SE Manager supports multi-thread safe APIs for MicriumOS and FreeRTOS interfacing with CMSIS RTOS2 APIs. -/// -/// For MicriumOS support the user application must define the compile time option SL_CATALOG_MICRIUMOS_KERNEL_PRESENT. -/// For FreeRTOS support the user application must define the compile time option SL_CATALOG_FREERTOS_KERNEL_PRESENT. -/// For bare metal mode (non-RTOS) the user must not define SL_CATALOG_MICRIUMOS_KERNEL_PRESENT or SL_CATALOG_FREERTOS_KERNEL_PRESENT. -/// -/// Applications created using Simplicity Studio 5 need to include the header file called _sl_component_catalog.h_ which will include a macro define for one of the abovementioned RTOSes if present. -/// -/// In the cases with SL_CATALOG_MICRIUMOS_KERNEL_PRESENT or SL_CATALOG_FREERTOS_KERNEL_PRESENT defined (RTOS-mode), the SE Manager will be configured with threading and yield support. -/// Configure ::sl_se_command_context_t with ::sl_se_set_yield to yield the CPU core when the SE Manager is waiting for the Secure Engine to complete a mailbox command. -/// -/// For threading support the SE Manager applies an SE lock mechanism to protect the Secure Engine Mailbox interface from being accessed by more than one thread, -/// ensuring multi-thread safety. For yielding the CPU core while waiting for the SE, the SE Manager APIs that invoke -/// SE mailbox commands will wait on a semaphore which is signaled in the ISR that handles the SE mailbox completion interrupt. -/// Hence other threads may run on the CPU core while the SE is processing the mailbox command. -/// -/// @} (end addtogroup sl_se_manager) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_H +#define SL_SE_MANAGER_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +/***************************************************************************//** + * @addtogroup sl_se_manager Secure Engine Manager + * + * @note The APIs are thread-safe. + * + * @{ + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sl_se_manager_core Core + * + * @brief + * Secure Engine Manager Core API + * + * @details + * API for initialization of SE Manager and SE command context with yield + * attribute. + * + * @{ + ******************************************************************************/ + +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + #include "sl_se_manager_key_handling.h" + #include "sl_se_manager_cipher.h" +#endif // SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT +#include "sl_se_manager_types.h" + +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Initialize the SE Manager. + * + * @details + * Initialize the SE Manager by checking hardware availability and setting up + * internal module specific resources like mutexes etc. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_init(void); + +/***************************************************************************//** + * @brief + * Denitialize the SE Manager. + * + * @details + * Free resources held by the SE Manager. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_deinit(void); + +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) +/***************************************************************************//** + * @brief + * Set the yield attribute of the SE command context object. + * + * @param[in,out] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] yield + * The user may set this parameter to true in order to tell the SE Manager + * to yield the cpu core while waiting for the SE mailbox command to complete. + * If false, the SE Manager will busy-wait, by polling the SE mailbox response + * register until the SE mailbox command completes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx, + bool yield); +#endif // !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT + +#if defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @brief + * From VSE mailbox read which command, if any, was executed. + * + * @param[in,out] cmd_ctx + * Pointer to an SE command context object. If this function returns + * SL_STATUS_OK the command word of the SE command context object will be set. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_read_executed_command(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Acknowledge and get status and output data of a completed command. + * + * @details + * This function acknowledges and gets the status and output data of a + * completed mailbox command. The acknowledge operation invalidates the + * contents of the output mailbox. The output data is copied into the linked + * list of output buffers pointed to in the given command data structure. + * + * @param[in,out] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_ack_command(sl_se_command_context_t *cmd_ctx); +#endif //defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +/***************************************************************************//** + * @brief + * Initialize an SE command context object + * + * @details + * Initialize an SE command context which can be used in subsequent calls to + * the SE Manager API in order to execute SE mailbox commands. + * + * @param[in,out] cmd_ctx + * Pointer to an SE command context object to be initialized. This context + * object should be used in subsequent calls to the SE Manager API in order + * to execute SE mailbox commands. The same command context object cannot be + * used concurrently, e.g. by two different threads. However a command context + * object may be reused for the next and any subsequent mailbox operatons, + * except when streaming commands are in progress in which case only streaming + * commands of the same operation type is allowed until the streaming operation + * is finished (i.e. the corresponding sl_se_xxx_finish is called). + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_init_command_context(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * De-initialize an SE command context + * + * @details + * De-initialize an SE command context object. + * + * @param[in,out] cmd_ctx + * Pointer to an SE command context object to deinitialize. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_deinit_command_context(sl_se_command_context_t *cmd_ctx); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_core) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_H + +// THE REST OF THE FILE IS DOCUMENTATION ONLY +/// @addtogroup sl_se_manager Secure Engine Manager API +/// @brief Silicon Labs Secure Engine Manager +/// @{ +/// +/// @details +/// # Introduction +/// +/// The Secure Engine (SE) Manager provides thread-safe APIs for the Secure Engine's mailbox interface. Note that PSA Crypto is the main device independant crypto API and should be used +/// whenever possible. Visit the Mbed TLS & PSA Crypto documentation hub for more details. The SE manager APIs can be used directly +/// for performance or space constrained applications. +/// +/// Available functionality will vary between devices: device management, such as secure firmware upgrade, secure boot and secure debug implementation, is available on all series 2 devices. +/// Devices with the SE subsystem includes a low level crypto API where the SE Manager will use the SE hardware peripherals to accelerate cryptographic operations. Finally, Vault High +/// devices also include secure key storage functionality, anti-tamper protection, advanced crypto API and attestation. +/// +/// @note Below are some of the useful application notes linked with Secure Engine Manager:\n +/// AN1190: Series 2 Secure Debug\n +/// AN1247: Anti-Tamper Protection Configuration and Use\n +/// AN1268: Authenticating Silicon Labs Devices Using Device Certificates\n +/// AN1271: Secure Key Storage\n +/// AN1218: Series 2 Secure Boot with RTSL\n +/// +/// # Functionality +/// +/// The functionality of the SE Manager includes +/// +/// - Core API, inititalizing of SE Manager and SE command context (@ref sl_se_manager_core) +/// - Secure key storage (@ref sl_se_manager_key_handling) +/// - Key wrapping +/// - Storing keys in the SE volatile storage +/// - Using key by reference +/// - Configuration of tamper responses (@ref sl_se_manager_util) +/// - The available signals include core hard-fault, glitch detectors, PRS, and failed authenticated commands, +/// while the responses vary from triggering an interrupt to the hardware autonomously erasing the one-time-programmable (OTP) memory +/// - Block ciphers (@ref sl_se_manager_cipher) +/// - Supports AES-ECB, AES-CBC, AES-CFB128, AES-CFB8, AES-CTR, AES-CCM, AES-GCM, CMAC, HMAC and ChaCha20/Poly1305 +/// - The cipher operations can be performed using plaintext keys, wrapped keys or referencing a key in the SE +/// - Streaming operations are supported for AES-GCM and CMAC +/// - Block and streaming hash operations (@ref sl_se_manager_hash) +/// - Supports SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 +/// - True Random Number Generator (@ref sl_se_manager_entropy) +/// - Hardware block inside the SE used for generating random numbers. Can be used as a source of entropy, or to securely generate keys inside the SE +/// - Elliptic Curve Signature operation (@ref sl_se_manager_signature) +/// - ECDSA and EDDSA +/// - Key agreement (@ref sl_se_manager_key_derivation) +/// - Perform Elliptic Curve Diffie-Hellman and J-PAKE key agreement operations inside the SE +/// - Key derivation functions (@ref sl_se_manager_key_derivation) +/// - Perform HKDF and PBKDF2 key derivation functions inside the SE +/// - Device configuration and utilities (@ref sl_se_manager_util) +/// - Write to user data stored inside the SE +/// - Configuration of debug locks +/// - Configuration of secure boot +/// - Configuration of flash lock +/// - Read SE OTP contents +/// - Read SE firmware version +/// - Read provisioned certificates +/// - Multi-thread safe APIs for MicriumOS and FreeRTOS +/// - Retrieveing attestation tokens (@ref sl_se_manager_attestation) +/// +/// ## Key Storage and Use of SE Wrapped Keys +/// +/// The way keys are stored and operated on depends on the options set in the key descriptor used (@ref sl_se_key_descriptor_t). +/// Each key descriptor is initialized with a storage location, a key type, and length of the key (some key types have a known length, and it is not required to be set). +/// The storage location can either be application memory or inside the SE, for more details, see @ref sl_se_storage_method_t. +/// Depending on the use-case, the key descriptors will also store the pointer to a key and an SE key slot, see @ref sl_se_key_slot_t for the list of available internal SE key slots. +/// +/// For more information on the key handling APIs see @ref sl_se_manager_key_handling. +/// +/// ### Supported Key Types +/// Symmetric keys +/// - AES-128 (16 bytes) +/// - AES-192 (24 bytes) +/// - AES-256 (32 bytes) +/// - ChaCha20 (32 bytes) +/// +/// Asymmetric keys for ECC +/// - NIST P-192 +/// - NIST P-256 +/// - NIST P-384 +/// - NIST P-521 +/// - Curve25519 +/// - Curve448 +/// +/// Custom Weierstrass Prime curves are also supported (@ref sl_se_custom_weierstrass_prime_domain_t). +/// +/// ### Example Usage of Keys +/// +/// @code{.c} +/// #define WRAPPED_KEY_OVERHEAD (12UL + 16UL) +/// #define AES_256_KEY_SIZE 32UL +/// +/// uint8_t key_buffer[AES_256_KEY_SIZE]; +/// uint8_t wrapped_key_buffer[AES_256_KEY_SIZE + WRAPPED_KEY_OVERHEAD]; +/// +/// void demo_se_create_key_in_slot(void) { +/// sl_se_key_descriptor_t new_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, +/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, +/// }; +/// sl_se_generate_key(&new_key); +/// } +/// +/// void demo_se_create_plaintext_key(void) { +/// sl_se_key_descriptor_t new_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, +/// }; +/// new_key.storage.location.buffer.pointer = key_buffer; +/// new_key.storage.location.buffer.size = sizeof(key_buffer); +/// sl_se_generate_key(&new_key); +/// } +/// +/// void demo_se_create_wrapped_key(void) { +/// sl_se_key_descriptor_t new_wrapped_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, +/// }; +/// new_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer; +/// new_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer); +/// sl_se_generate_key(&new_wrapped_key); +/// } +/// +/// void demo_se_wrapped_key_to_volatile_slot(void) { +/// sl_se_key_descriptor_t existing_wrapped_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, +/// }; +/// existing_wrapped_key.storage.location.buffer.pointer = wrapped_key_buffer; +/// existing_wrapped_key.storage.location.buffer.size = sizeof(wrapped_key_buffer); +/// sl_se_key_descriptor_t key_in_slot = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, +/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, +/// }; +/// sl_se_import_key(&existing_wrapped_key, &key_in_slot); +/// } +/// +/// void demo_se_volatile_slot_to_wrapped_key(void) { +/// sl_se_key_descriptor_t existing_volatile_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, +/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, +/// }; +/// sl_se_key_descriptor_t wrapped_key_out = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, +/// }; +/// wrapped_key_out.storage.location.buffer.pointer = wrapped_key_buffer; +/// wrapped_key_out.storage.location.buffer.size = sizeof(wrapped_key_buffer); +/// sl_se_export_key(&existing_volatile_key, &wrapped_key_out); +/// } +/// +/// void demo_se_delete_from_volatile_slot(void) { +/// sl_se_key_descriptor_t existing_volatile_key = { +/// .type = SL_SE_KEY_TYPE_AES_256, +/// .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, +/// .storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE, +/// .storage.location.slot = SL_SE_KEY_SLOT_VOLATILE_0, +/// }; +/// sl_se_delete_key(&existing_volatile_key); +/// } +/// @endcode +/// +/// ## Tamper +/// +/// The Secure Engine (SE) tamper module connects a number of hardware and software-driven tamper signals to a set of configurable hardware and software responses. +/// This can be used to program the device to automatically respond to external events that could signal that someone is trying to tamper with the device, +/// and very rapidly remove secrets stored in the SE. The available tamper signals range from signals based on failed authentication and secure boot to specialized glitch detectors. +/// When any of these signals fire, the tamper block can be configured to trigger several different responses, +/// ranging from triggering an interrupt to erasing the one-time-programmable (OTP) memory, removing all SE secrets and resulting in a permanently destroyed device. +/// +/// A tamper signal can lead to a series of different autonomous responses from the tamper module. These responses are listed in the table below. +/// | | Response | Description | +/// | ----: | :----: | :---- | +/// | 0 | Ignore | No action is taken. | +/// | 1 | Interrupt | The SETAMPERHOST interrupt on the host is triggered. | +/// | 2 | Filter | A counter in the tamper filter is increased. | +/// | 4 | Reset | The device is reset. | +/// | 7 | Erase OTP | Erases the OTP configuration of the device. | +/// +/// These responses are cumulative, meaning that if a filter response is triggered, an interrupt will also be triggered. For a full overview of the tamper signals, see @ref sl_se_manager_defines.h. +/// +/// The tamper configuration is one-time-programmable, and is done using the initialise OTP command to the SE (see @ref sl_se_init_otp). +/// This means that tamper settings must be written together with secure boot settings, and are immutable after they are written. +/// After tamper has been initialized, it is possible to temporarily disable one or several tamper signals using an authenticated command, +/// similar to secure debug unlock. This is only possible if the debug public key has been installed on the device. +/// It is only possible to disable the customer enabled response. The default response to a signal cannot be disabled. +/// +/// Tamper is configured by providing the following: +/// +/// +///
Tamper configuration table
Setting Description +///
Tamper response levels A response level for each tamper signal.\n\n It is not possible to degrade the default response level of a tamper signal, so if a response is set to a lower level than the default response level listed in the table in the Signals section, this won't have any effect. +///
Filter settings The tamper filter counter has two settings: +///
    +///
  • Reset period +///
  • Trigger threshold +///
+/// These options can be set to the values given in the tables in the Response Filter section. Please see the examples section for a suggested use of the tamper filter signal. +///
Flags The tamper flags is used to configure two options: +///
    +///
  • Digital Glitch Detector Always On – This option will keep the digital glitch detector running even while the SE is not performing any operations. This leads to increased energy consumption. +///
  • Keep Tamper Alive During Sleep (not available on EFR32xG21B devices) – If set, the tamper module keeps running at sleep mode (down to EM3). +///
+///
Reset threshold The number of consecutive tamper resets before the the part enters debug mode.\n\n +/// If the threshold is set to 0, the part will never enter the debug mode due to tamper reset. +///
+/// +/// ### Example Usage +/// +/// The glitch detectors can see spurious activations, and should typically not be used to directly drive a serious tamper response. +/// Instead they should feed their signals into a tamper interrupt (to handle the response logic on the M33), or into the tamper filter counter, +/// which can be used to activate a high level response if a number of incidents occur in a short time window. +/// The time period and counter threshold must be tuned to the use case. In the following example the device will erase OTP and become inoperable if 4 glitch signals is seen in a 1 minute time period. +/// +/// Since you can only configure tamper once for each device, please make sure that this is the configuration you actually want before you execute this example on actual device. +/// +/// @code{.c} +/// sl_se_otp_init_t otp_settings_init = SL_SE_OTP_INIT_DEFAULT; +/// +/// // Configure tamper levels +/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_FILTER] = SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP; +/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHFALLING] = SL_SE_TAMPER_LEVEL_FILTER; +/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHRISING] = SL_SE_TAMPER_LEVEL_FILTER; +/// otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_DGLITCH] = SL_SE_TAMPER_LEVEL_FILTER; +/// +/// +/// // Configure tamper filter options +/// otp_settings_init.tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_1MIN; +/// otp_settings_init.tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4; +/// +/// +/// // Commit OTP settings. This command is only available once! +/// sl_se_init_otp(&otp_settings_init); +/// @endcode +/// +/// ## RTOS Mode and Multi-Thread Safety +/// +/// @note The SE Manager API is multi-thread safe, but does not support preemption. +/// This means the API cannot be called from ISR or critical/atomic sections when running in an RTOS thread. +/// When using the SE Manager API in a bare-metal application, it is the application developer's responsibility +/// to not call the SE Manager APIs when another operation is in progress. +/// +/// The SE Manager supports multi-thread safe APIs for MicriumOS and FreeRTOS interfacing with CMSIS RTOS2 APIs. +/// +/// For MicriumOS support the user application must define the compile time option SL_CATALOG_MICRIUMOS_KERNEL_PRESENT. +/// For FreeRTOS support the user application must define the compile time option SL_CATALOG_FREERTOS_KERNEL_PRESENT. +/// For bare metal mode (non-RTOS) the user must not define SL_CATALOG_MICRIUMOS_KERNEL_PRESENT or SL_CATALOG_FREERTOS_KERNEL_PRESENT. +/// +/// Applications created using Simplicity Studio 5 need to include the header file called _sl_component_catalog.h_ which will include a macro define for one of the abovementioned RTOSes if present. +/// +/// In the cases with SL_CATALOG_MICRIUMOS_KERNEL_PRESENT or SL_CATALOG_FREERTOS_KERNEL_PRESENT defined (RTOS-mode), the SE Manager will be configured with threading and yield support. +/// Configure ::sl_se_command_context_t with ::sl_se_set_yield to yield the CPU core when the SE Manager is waiting for the Secure Engine to complete a mailbox command. +/// +/// For threading support the SE Manager applies an SE lock mechanism to protect the Secure Engine Mailbox interface from being accessed by more than one thread, +/// ensuring multi-thread safety. For yielding the CPU core while waiting for the SE, the SE Manager APIs that invoke +/// SE mailbox commands will wait on a semaphore which is signaled in the ISR that handles the SE mailbox completion interrupt. +/// Hence other threads may run on the CPU core while the SE is processing the mailbox command. +/// +/// @} (end addtogroup sl_se_manager) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_attestation.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_attestation.h index 85c8d07..2ad3179 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_attestation.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_attestation.h @@ -1,209 +1,209 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_ATTESTATION_H -#define SL_SE_MANAGER_ATTESTATION_H - -#include "sli_se_manager_features.h" - -#if (defined(SLI_MAILBOX_COMMAND_SUPPORTED) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_attestation Attestation - * - * @brief - * System and configuration attestation - * - * @details - * API for retrieveing attestation tokens from the SE. - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -/// 32 byte challenge size -#define SL_SE_ATTESTATION_CHALLENGE_SIZE_32 (32U) -/// 48 byte challenge size -#define SL_SE_ATTESTATION_CHALLENGE_SIZE_48 (48U) -/// 64 byte challenge size -#define SL_SE_ATTESTATION_CHALLENGE_SIZE_64 (64U) - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Get the PSA initial attest token from the SE - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] auth_challenge - * Buffer with a challenge object selected by the caller. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be either 32, 48 or 64. - * - * @param[out] token_buf - * Buffer where the output token will be stored. - * - * @param[in] token_buf_size - * Size of token_buf in bytes. Must be at least the size found by calling - * \ref sl_se_attestation_get_psa_iat_token_size with equivalent arguments, - * and padded to word alignment. - * - * @param[out] token_size - * Number of bytes actually used in token_buf. - * - * @warning - * Once a nonce/challenge has been used, the same challenge should not be used - * ever again, to prevent replay attacks. - * - * @warning - * The output will be length-extended to the next word-multiple. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_attestation_get_psa_iat_token(sl_se_command_context_t *cmd_ctx, - const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size); - -/***************************************************************************//** - * @brief - * Get the size of a PSA initial attest token with the given nonce - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be either 32, 48 or 64. - * - * @param[out] token_size - * Pointer to output word. Result is stored here. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_attestation_get_psa_iat_token_size(sl_se_command_context_t *cmd_ctx, - size_t challenge_size, - size_t *token_size); - -/***************************************************************************//** - * @brief - * Get an attested (signed) security configuration token from the SE - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] auth_challenge - * Buffer with a challenge object selected by the caller. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be 32. - * - * @param[out] token_buf - * Buffer where the output token will be stored. - * - * @param[in] token_buf_size - * Size of token_buf in bytes. Must be at least the size found by calling - * \ref sl_se_attestation_get_config_token_size with equivalent arguments, - * and padded to word alignment. - * - * @param[out] token_size - * Number of bytes actually used in token_buf. - * - * @warning - * Once a nonce/challenge has been used, the same challenge should not be used - * ever again, to prevent replay attacks. - * - * @warning - * The output will be length-extended to the next word-multiple. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_attestation_get_config_token(sl_se_command_context_t *cmd_ctx, - const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size); - -/***************************************************************************//** - * @brief - * Get the size of a security configuration token - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be 32. - * - * @param[out] token_size - * Pointer to output word. Result is stored here. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd_ctx, - size_t challenge_size, - size_t *token_size); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_attestation) -/// @} (end addtogroup sl_se_manager) - -#endif // SLI_MAILBOX_COMMAND_SUPPORTED && VAULT - -#endif // SL_SE_MANAGER_ATTESTATION_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_ATTESTATION_H +#define SL_SE_MANAGER_ATTESTATION_H + +#include "sli_se_manager_features.h" + +#if (defined(SLI_MAILBOX_COMMAND_SUPPORTED) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_attestation Attestation + * + * @brief + * System and configuration attestation + * + * @details + * API for retrieveing attestation tokens from the SE. + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +/// 32 byte challenge size +#define SL_SE_ATTESTATION_CHALLENGE_SIZE_32 (32U) +/// 48 byte challenge size +#define SL_SE_ATTESTATION_CHALLENGE_SIZE_48 (48U) +/// 64 byte challenge size +#define SL_SE_ATTESTATION_CHALLENGE_SIZE_64 (64U) + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Get the PSA initial attest token from the SE + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] auth_challenge + * Buffer with a challenge object selected by the caller. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be either 32, 48 or 64. + * + * @param[out] token_buf + * Buffer where the output token will be stored. + * + * @param[in] token_buf_size + * Size of token_buf in bytes. Must be at least the size found by calling + * \ref sl_se_attestation_get_psa_iat_token_size with equivalent arguments, + * and padded to word alignment. + * + * @param[out] token_size + * Number of bytes actually used in token_buf. + * + * @warning + * Once a nonce/challenge has been used, the same challenge should not be used + * ever again, to prevent replay attacks. + * + * @warning + * The output will be length-extended to the next word-multiple. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_attestation_get_psa_iat_token(sl_se_command_context_t *cmd_ctx, + const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size); + +/***************************************************************************//** + * @brief + * Get the size of a PSA initial attest token with the given nonce + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be either 32, 48 or 64. + * + * @param[out] token_size + * Pointer to output word. Result is stored here. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_attestation_get_psa_iat_token_size(sl_se_command_context_t *cmd_ctx, + size_t challenge_size, + size_t *token_size); + +/***************************************************************************//** + * @brief + * Get an attested (signed) security configuration token from the SE + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] auth_challenge + * Buffer with a challenge object selected by the caller. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be 32. + * + * @param[out] token_buf + * Buffer where the output token will be stored. + * + * @param[in] token_buf_size + * Size of token_buf in bytes. Must be at least the size found by calling + * \ref sl_se_attestation_get_config_token_size with equivalent arguments, + * and padded to word alignment. + * + * @param[out] token_size + * Number of bytes actually used in token_buf. + * + * @warning + * Once a nonce/challenge has been used, the same challenge should not be used + * ever again, to prevent replay attacks. + * + * @warning + * The output will be length-extended to the next word-multiple. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_attestation_get_config_token(sl_se_command_context_t *cmd_ctx, + const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size); + +/***************************************************************************//** + * @brief + * Get the size of a security configuration token + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be 32. + * + * @param[out] token_size + * Pointer to output word. Result is stored here. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd_ctx, + size_t challenge_size, + size_t *token_size); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_attestation) +/// @} (end addtogroup sl_se_manager) + +#endif // SLI_MAILBOX_COMMAND_SUPPORTED && VAULT + +#endif // SL_SE_MANAGER_ATTESTATION_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_check_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_check_config.h index d52832e..b66025b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_check_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_check_config.h @@ -1,61 +1,61 @@ -/**************************************************************************/ /** - * @file - * @brief Consistency checks for SE Manager configuration options - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SE_MANAGER_CHECK_CONFIG_H -#define SL_SE_MANAGER_CHECK_CONFIG_H - -#if defined (SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_SE_MANAGER_THREADING) \ - && !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ - && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) -#error "Yield when waiting for SE commands to finish is currently required in RTOS mode." -#endif -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ - && !defined(SL_SE_MANAGER_THREADING) -#error "Yield when waiting for SE commands to finish currently requires RTOS mode. I.e. yield support is not available in bare metal mode." -#endif - -#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \ - && !defined(SL_SE_MANAGER_THREADING) -#error "RTOS requires threading mode." -#endif - -#if (defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) && defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION)) -#error "Yield support is not available on EFR32xG22 devices" -#endif - -#if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED != 1) -#error "Using multiple blocks for key stream computation is not supported" -#endif - -#endif // SL_SE_MANAGER_CHECK_CONFIG_H +/**************************************************************************/ /** + * @file + * @brief Consistency checks for SE Manager configuration options + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SE_MANAGER_CHECK_CONFIG_H +#define SL_SE_MANAGER_CHECK_CONFIG_H + +#if defined (SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_SE_MANAGER_THREADING) \ + && !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ + && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +#error "Yield when waiting for SE commands to finish is currently required in RTOS mode." +#endif +#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) \ + && !defined(SL_SE_MANAGER_THREADING) +#error "Yield when waiting for SE commands to finish currently requires RTOS mode. I.e. yield support is not available in bare metal mode." +#endif + +#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \ + && !defined(SL_SE_MANAGER_THREADING) +#error "RTOS requires threading mode." +#endif + +#if (defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) && defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION)) +#error "Yield support is not available on EFR32xG22 devices" +#endif + +#if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED != 1) +#error "Using multiple blocks for key stream computation is not supported" +#endif + +#endif // SL_SE_MANAGER_CHECK_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h index e6284cf..8c7523f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_cipher.h @@ -1,1113 +1,1113 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_CIPHER_H -#define SL_SE_MANAGER_CIPHER_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_cipher Cipher - * - * @brief - * Symmetric encryption, AEAD and MAC. - * - * @details - * API for performing symmetric encryption, Authenticated Encryption and - * Additional Data (AEAD) operations, and computing Message Authentication - * Codes (MACs) using the Secure Engine. - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * AES-ECB block encryption/decryption. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - * @param[in] length - * Length of the input data. - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_ecb(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * AES-CBC buffer encryption/decryption. - * - * @note - * Length should be a multiple of the block size (16 bytes). - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - * @param[in] length - * Length of the input data. - * - * @param[in,out] iv - * Initialization vector (updated after use). - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cbc(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * AES-CFB128 buffer encryption/decryption. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - * @param[in] length - * Length of the input data. - * - * @param[in,out] iv_off - * Offset in IV (updated after use). - * - * @param[in,out] iv - * Initialization vector (updated after use). - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cfb128(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - uint32_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * AES-CFB8 buffer encryption/decryption. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - * @param[in] length - * Length of the input data. - * - * @param[in,out] iv - * Initialization vector (updated after use). - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cfb8(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * AES-CTR buffer encryption/decryption. - * - * @warning - * Avoid passing in the same buffer for nonce_counter and - * stream_block as the incrementation operation of - * nonce_counter can lead to corruption of the ciphertext - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * Length of the input data. - * - * @param[in] nc_off - * The offset in the current stream_block (for resuming - * within current cipher stream). The offset pointer to - * should be 0 at the start of a stream. - * - * @param[in,out] nonce_counter - * The 128-bit nonce and counter. - * - * @param[in,out] stream_block - * The saved stream-block for resuming (updated after use). - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_ctr(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - uint32_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE], - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * AES-CCM buffer encryption. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the input data in Bytes. - * - * @param[in] iv - * Initialization vector (nonce). - * - * @param[in] iv_len - * The length of the IV in Bytes: 7, 8, 9, 10, 11, 12, or 13. - * - * @param[in] add - * The additional data field. - * - * @param[in] add_len - * The length of additional data in Bytes. - * - * @param[in] input - * The buffer holding the input data. - * - * @param[out] output - * The buffer holding the output data. Must be at least @p length Bytes wide. - * - * @param[in,out] tag - * The buffer holding the tag. - * - * @param[in] tag_len - * The length of the tag to generate in Bytes: 4, 6, 8, 10, 12, 14 or 16. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_ccm_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - unsigned char *tag, size_t tag_len); - -/***************************************************************************//** - * @brief - * AES-CCM buffer decryption. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the input data in Bytes. - * - * @param[in] iv - * Initialization vector. - * - * @param[in] iv_len - * The length of the IV in Bytes: 7, 8, 9, 10, 11, 12, or 13. - * - * @param[in] add - * The additional data field. - * - * @param[in] add_len - * The length of additional data in Bytes. - * - * @param[in] input - * The buffer holding the input data. - * - * @param[out] output - * The buffer holding the output data. Must be at least @p length Bytes wide. - * - * @param[in] tag - * The buffer holding the tag. - * - * @param[in] tag_len - * The length of the tag in Bytes. Must be 4, 6, 8, 10, 12, 14 or 16. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - const unsigned char *tag, size_t tag_len); - -/***************************************************************************//** - * @brief - * Prepare a CCM streaming command context object. - * - * @details - * Prepare a CCM streaming command context object to be used in subsequent - * CCM streaming function calls. - * - * @param[in] ccm_ctx - * Pointer to a CCM streaming context object. - * - * @param[in] cmd_ctx - * Pointer to a SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * The operation to perform: SL_SE_ENCRYPT or SL_SE_DECRYPT. - * - * @param[in] total_message_length - * The total length of the text to encrypt/decrypt - * - * @param[in] iv - * The initialization vector (commonly referred to as nonce for CCM). - * - * @param[in] iv_len - * The length of the IV. - * - * @param[in] add - * The buffer holding the additional data. - * - * @param[in] add_len - * The length of the additional data. - * - * @param[in] tag_len - * Encryption: The length of the tag to generate. Must be 0, 4, 6, 8, 10, 12, 14 or 16. - * Decryption: The length of the tag to authenticate. Must be 0, 4, 6, 8, 10, 12, 14 or 16. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - uint32_t total_message_length, - const uint8_t *iv, - size_t iv_len, - const uint8_t *add, - size_t add_len, - size_t tag_len); - -/***************************************************************************//** - * @brief - * This function feeds an input buffer into an ongoing CCM computation. - * - * It is called between sl_se_ccm_multipart_starts() and sl_se_ccm_multipart_finish(). - * Can be called repeatedly. - * - * @param[in] ccm_ctx - * Pointer to a CCM streaming context object. - * - * @param[in] cmd_ctx - * Pointer to a SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the input data. This must be a multiple of 16 except in - * the last call before sl_se_ccm_multipart_finish(). - * - * @param[in] input - * Buffer holding the input data, must be at least @p length bytes wide. - * - * @param[out] output - * Buffer for holding the output data, must be at least @p length bytes wide. - * - * @param[out] output_length - * Length of data that has been encrypted/decrypted. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ - -sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length); - -/***************************************************************************//** - * @brief - * Finish a CCM streaming operation and return the resulting CCM tag. - * - * It is called after sl_se_ccm_multipart_update(). - * - * @param[in] ccm_ctx - * Pointer to a CCM streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in, out] tag - * Encryption: The buffer for holding the tag. - * Decryption: The tag to authenticate. - * - * @param[in] tag_size - * The size of the tag buffer. Must be equal or greater to the length of the expected tag. - * - * @param[out] output - * Buffer for holding the output data. - * - * @param[in] output_size - * Output buffer size. Must be equal or greater to the stored data from - * sl_se_ccm_multipart_update (maximum 16 bytes). - * - * @param[out] output_length - * Length of data that has been encrypted/decrypted. - * - * @return - * Returns SL_SE_INVALID_SIGNATURE if authentication step fails. - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *tag, - uint8_t tag_size, - uint8_t *output, - uint8_t output_size, - uint8_t *output_length); - -/***************************************************************************//** - * @brief - * This function performs GCM encryption or decryption of a buffer. - * - * @note - * For encryption, the output buffer can be the same as the input buffer. - * For decryption, the output buffer cannot be the same as input buffer. - * If the buffers overlap, the output buffer must trail at least 8 bytes - * behind the input buffer. - * - * @warning - * When this function performs a decryption, it outputs the authentication - * tag and does not verify that the data is authentic. You should use this - * function to perform encryption only. For decryption, use - * sl_se_gcm_auth_decrypt() instead. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - SL_SE_ENCRYPT: The ciphertext is written to @p output and the - * authentication tag is written to @p tag. - * - SL_SE_DECRYPT: The plaintext is written to @p output and the - * authentication tag is written to @p tag. - * Note that this mode is not recommended, because it does - * not verify the authenticity of the data. For this - * reason, you should use sl_se_gcm_auth_decrypt() instead. - * - * @param[in] length - * The length of the input data, which is equal to the length of the output - * data. - * - * @param[in] iv - * The initialization vector. - * - * @param[in] iv_len - * The length of the iv. Must be @b 12 bytes. - * - * @param[in] add - * The buffer holding the additional data. - * - * @param[in] add_len - * The length of the additional data in bytes. - * - * @param[in] input - * The buffer holding the input data. Its size is @b length bytes. - * - * @param[out] output - * The buffer for holding the output data. It must have room for @b length - * bytes. - * - * @param[in] tag_len - * The length of the tag to generate (in bytes). - * - * @param[out] tag - * The buffer for holding the tag. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_gcm_crypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - unsigned char *tag); - -/***************************************************************************//** - * @brief - * This function performs a GCM authenticated decryption of a buffer. - * - * @note - * The output buffer cannot be the same as input buffer. If the buffers - * overlap, the output buffer must trail at least 8 bytes behind the input - * buffer. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the ciphertext to decrypt, which is also the length of the - * decrypted plaintext. - * - * @param[in] iv - * The initialization vector. - * - * @param[in] iv_len - * The length of the iv. Must be @b 12 bytes. - * - * @param[in] add - * The buffer holding the additional data. - * - * @param[in] add_len - * The length of the additional data in bytes. - * - * @param[in] tag - * The buffer holding the tag to verify. - * - * @param[in] tag_len - * The length of the tag to verify (in bytes). - * - * @param[in] input - * The buffer holding the ciphertext. Its size is @b length bytes. - * - * @param[out] output - * The buffer for holding the decrypted plaintext. It must have room for - * @b length bytes. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_gcm_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - const unsigned char *tag); - -/***************************************************************************//** - * @brief - * This function calculates the full generic CMAC on the input buffer with - * the provided key. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] input - * Buffer holding the input data, must be at least @p input_len bytes wide. - * - * @param[in] input_len - * The length of the input data in bytes. - * - * @param[out] output - * Buffer holding the 16-byte output data, must be at least 16 bytes wide. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_cmac(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - const unsigned char *input, - size_t input_len, - unsigned char *output); - -/***************************************************************************//** - * @brief - * Prepare a CMAC streaming command context object. - * - * @details - * Prepare a CMAC streaming command context object to be used in subsequent - * CMAC streaming function calls. - * - * @param[in] cmac_ctx - * Pointer to a CMAC streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_starts(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key); - -/***************************************************************************//** - * @brief - * This function feeds an input buffer into an ongoing CMAC computation. - * - * @details - * It is called between sl_se_cmac_multipart_starts() and sl_se_cmac_multipart_finish(). - * Can be called repeatedly. - * - * @param[in,out] cmac_ctx - * Pointer to a CMAC streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] input - * Buffer holding the input data, must be at least @p input_len bytes wide. - * - * @param[in] input_len - * The length of the input data in bytes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_update(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - const uint8_t *input, - size_t input_len); - -/***************************************************************************//** - * @brief - * Finish a CMAC streaming operation and return the resulting CMAC tag. - * - * @details - * It is called after sl_se_cmac_multipart_update(). - * - * @param[in,out] cmac_ctx - * Pointer to a CMAC streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[out] output - * Buffer holding the 16-byte CMAC tag, must be at least 16 bytes wide. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_finish(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *output); - -/***************************************************************************//** - * @brief - * Prepare a GCM streaming command context object. - * - * @details - * Prepare a GCM streaming command context object to be used in subsequent - * GCM streaming function calls. - * - * @param[in, out] gcm_ctx - * Pointer to a GCM streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] mode - * The operation to perform: SL_SE_ENCRYPT or SL_SE_DECRYPT. - * - * @param[in] iv - * The initialization vector. - * - * @param[in] iv_len - * The length of the IV. - * - * @param[in] add - * The buffer holding the additional data, or NULL if @p add_len is 0. - * - * @param[in] add_len - * The length of the additional data. If 0, @p add is NULL. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - const uint8_t *iv, - size_t iv_len, - const uint8_t *add, - size_t add_len); - -/***************************************************************************//** - * @brief - * This function feeds an input buffer into an ongoing GCM computation. - * - * It is called between sl_se_gcm_multipart_starts() and sl_se_gcm_multiapart_finish(). - * Can be called repeatedly. - * - * @param[in, out] gcm_ctx - * Pointer to a GCM streaming context object. - * - * @param[in] length - * The length of the input data. - * - * @param[in] input - * Buffer holding the input data, must be at least @p length bytes wide. - * - * @param[out] output - * Buffer for holding the output data, must be at least @p length bytes wide. - * - * @param[out] output_length - * Length of data that has been encrypted/decrypted. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length); - -/***************************************************************************//** - * @brief - * Finish a GCM streaming operation and return the resulting GCM tag. - * - * It is called after sl_se_gcm_multipart_update(). - * - * @param[in, out] gcm_ctx - * Pointer to a GCM streaming context object. - * - * @param[in, out] tag - * Encryption: The buffer for holding the tag. - * Decryption: The tag to authenticate. - * - * @param[in] tag_length - * Encryption: Length of the output tag. - * Decryption: Length of tag to verify - * - * @param[out] output - * Buffer for holding the output data. - * - * @param[in] output_size - * Output buffer size. Must be equal or greater to the stored data from - * sl_se_gcm_multipart_update (stored data is maximum 16 bytes). - * - * @param[out] output_length - * Length of data that has been encrypted/decrypted. - * - * @return - * Returns SL_SE_INVALID_SIGNATURE if authentication step fails. - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_finish(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *tag, - uint8_t tag_length, - uint8_t *output, - uint8_t output_size, - uint8_t *output_length); - -/***************************************************************************//** - * @brief - * Compute a HMAC on a full message. - * - * @details - * This function computes a Keyed-Hashed Message Authentication Code (HMAC) - * for the given input message. HMAC can be used with any iterative - * cryptographic hash function, e.g., SHA-1 in combination with a - * secret shared key. The cryptographic strength of HMAC depends on the - * properties of the underlying hash function. For instance, if the algorithm - * is chosen to be SHA-256, it will generate a 32 bytes HMAC. - * This function supports SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512. - * The key can be of any length. If the key is shorter than the block size - * of the hash function the SE will append zeros to the key so the key size - * matches the block size of the hash function. If the key is longer than the - * block size of the hash function the key will be hashed to - * produce a key digest, then append zeros so the resulting 'hashed' key size - * matches the block size of the hash function. In any case the minimal - * recommended key length is the digest size of the hash function. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure specifying the key to use in - * the HMAC computation. - * - * @param[in] hash_type - * Which hashing algorithm to use. - * - * @param[in] message - * Pointer to the message buffer to compute the hash/digest from. - * - * @param[in] message_len - * Number of bytes in message. - * - * @param[out] output - * Pointer to memory buffer to store the final HMAC output. - * - * @param[in] output_len - * The length of the HMAC output memory buffer, must be at least the size - * of the corresponding hash type. - * - * @return Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hmac(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_type, - const uint8_t *message, - size_t message_len, - uint8_t *output, - size_t output_len); - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * @brief - * ChaCha20 buffer encryption/decryption, as defined by RFC8439 section 2.4. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] mode - * Crypto operation type (encryption or decryption). - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * Length of the input data. - * - * @param[in] initial_counter - * The initial counter value as defined in RFC8439 section 2.4. - * - * @param[in] nonce - * The nonce, also called initialisation vector, as defined in RFC8439 section - * 2.4. - * - * @param[in] input - * Buffer holding the input data. - * - * @param[out] output - * Buffer holding the output data. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_chacha20_crypt(sl_se_command_context_t *cmd_ctx, - sl_se_cipher_operation_t mode, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char initial_counter[4], - const unsigned char nonce[12], - const unsigned char *input, - unsigned char *output); - -/***************************************************************************//** - * @brief - * ChaCha20-Poly1305 authenticated encryption with additional data, as defined - * by RFC8439 section 2.8. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the input data in bytes. - * - * @param[in] nonce - * The nonce, also called initialisation vector, as defined in RFC8439 section - * 2.8. - * - * @param[in] add - * The buffer holding additional authenticated data. Can be NULL if @p add_len - * equals 0. - * - * @param[in] add_len - * The length of the additional authenticated data in bytes. - * - * @param[in] input - * The buffer holding the plaintext input. - * - * @param[out] output - * The buffer holding the ciphertext output. Can be NULL, in which case the - * generated ciphertext will be discarded. Must be at least @p length bytes - * wide. - * - * @param[out] tag - * The buffer holding the tag. This function will produce a 128-bit tag, so - * this buffer must be at least 16 bytes wide. Can be NULL, in which case the - * generated tag will be discarded. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_chacha20_poly1305_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - unsigned char *tag); - -/***************************************************************************//** - * @brief - * ChaCha20-Poly1305 authenticated decryption with additional data, as defined - * by RFC8439 section 2.8. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] length - * The length of the input data in Bytes. - * - * @param[in] nonce - * The nonce, also called initialisation vector, as defined in RFC8439 section - * 2.8. - * - * @param[in] add - * The buffer holding additional authenticated data. Can be NULL if @p add_len - * equals 0. - * - * @param[in] add_len - * The length of the additional authenticated data in bytes. - * - * @param[in] input - * The buffer holding the ciphertext to decrypt. Can be NULL if @p length - * equals 0. - * - * @param[out] output - * The buffer holding the plaintext output. Can be NULL, in which case the - * decrypted plaintext will be discarded, or when @p length equals 0. Must be - * at least @p length bytes wide. - * - * @param[in] tag - * The buffer holding the tag to verify. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_chacha20_poly1305_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - const unsigned char tag[16]); - -/***************************************************************************//** - * @brief - * Generate a Poly1305 MAC (message authentication code) for a given message - * using an ephemeral key derived using ChaCha20. - * - * @note - * This function first derives a Poly1305 key based on a ChaCha20 key and - * nonce, which are input to this function. The key derivation adheres to - * RFC8439 section 2.6. The derived key is then used to calculate a MAC of the - * input data, according to RFC8439 section 2.5. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure containing a ChaCha20 key. - * - * @param[in] length - * The length of the input data in Bytes. - * - * @param[in] nonce - * The nonce, also called initialisation vector, as defined in RFC8439 section - * 2.6. - * - * @param[in] input - * The buffer holding the input data. - * - * @param[out] tag - * The buffer holding the tag. This function will produce a 128-bit tag, so - * this buffer must be at least 16 bytes wide. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *input, - unsigned char *tag); - -#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_cipher) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_CIPHER_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_CIPHER_H +#define SL_SE_MANAGER_CIPHER_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_cipher Cipher + * + * @brief + * Symmetric encryption, AEAD and MAC. + * + * @details + * API for performing symmetric encryption, Authenticated Encryption and + * Additional Data (AEAD) operations, and computing Message Authentication + * Codes (MACs) using the Secure Engine. + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * AES-ECB block encryption/decryption. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * + * @param[in] length + * Length of the input data. + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_ecb(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * AES-CBC buffer encryption/decryption. + * + * @note + * Length should be a multiple of the block size (16 bytes). + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * + * @param[in] length + * Length of the input data. + * + * @param[in,out] iv + * Initialization vector (updated after use). + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cbc(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * AES-CFB128 buffer encryption/decryption. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * + * @param[in] length + * Length of the input data. + * + * @param[in,out] iv_off + * Offset in IV (updated after use). + * + * @param[in,out] iv + * Initialization vector (updated after use). + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cfb128(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + uint32_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * AES-CFB8 buffer encryption/decryption. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * + * @param[in] length + * Length of the input data. + * + * @param[in,out] iv + * Initialization vector (updated after use). + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cfb8(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * AES-CTR buffer encryption/decryption. + * + * @warning + * Avoid passing in the same buffer for nonce_counter and + * stream_block as the incrementation operation of + * nonce_counter can lead to corruption of the ciphertext + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * Length of the input data. + * + * @param[in] nc_off + * The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * + * @param[in,out] nonce_counter + * The 128-bit nonce and counter. + * + * @param[in,out] stream_block + * The saved stream-block for resuming (updated after use). + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_ctr(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + uint32_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE], + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * AES-CCM buffer encryption. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the input data in Bytes. + * + * @param[in] iv + * Initialization vector (nonce). + * + * @param[in] iv_len + * The length of the IV in Bytes: 7, 8, 9, 10, 11, 12, or 13. + * + * @param[in] add + * The additional data field. + * + * @param[in] add_len + * The length of additional data in Bytes. + * + * @param[in] input + * The buffer holding the input data. + * + * @param[out] output + * The buffer holding the output data. Must be at least @p length Bytes wide. + * + * @param[in,out] tag + * The buffer holding the tag. + * + * @param[in] tag_len + * The length of the tag to generate in Bytes: 4, 6, 8, 10, 12, 14 or 16. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_ccm_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + unsigned char *tag, size_t tag_len); + +/***************************************************************************//** + * @brief + * AES-CCM buffer decryption. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the input data in Bytes. + * + * @param[in] iv + * Initialization vector. + * + * @param[in] iv_len + * The length of the IV in Bytes: 7, 8, 9, 10, 11, 12, or 13. + * + * @param[in] add + * The additional data field. + * + * @param[in] add_len + * The length of additional data in Bytes. + * + * @param[in] input + * The buffer holding the input data. + * + * @param[out] output + * The buffer holding the output data. Must be at least @p length Bytes wide. + * + * @param[in] tag + * The buffer holding the tag. + * + * @param[in] tag_len + * The length of the tag in Bytes. Must be 4, 6, 8, 10, 12, 14 or 16. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + const unsigned char *tag, size_t tag_len); + +/***************************************************************************//** + * @brief + * Prepare a CCM streaming command context object. + * + * @details + * Prepare a CCM streaming command context object to be used in subsequent + * CCM streaming function calls. + * + * @param[in] ccm_ctx + * Pointer to a CCM streaming context object. + * + * @param[in] cmd_ctx + * Pointer to a SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * The operation to perform: SL_SE_ENCRYPT or SL_SE_DECRYPT. + * + * @param[in] total_message_length + * The total length of the text to encrypt/decrypt + * + * @param[in] iv + * The initialization vector (commonly referred to as nonce for CCM). + * + * @param[in] iv_len + * The length of the IV. + * + * @param[in] add + * The buffer holding the additional data. + * + * @param[in] add_len + * The length of the additional data. + * + * @param[in] tag_len + * Encryption: The length of the tag to generate. Must be 0, 4, 6, 8, 10, 12, 14 or 16. + * Decryption: The length of the tag to authenticate. Must be 0, 4, 6, 8, 10, 12, 14 or 16. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + uint32_t total_message_length, + const uint8_t *iv, + size_t iv_len, + const uint8_t *add, + size_t add_len, + size_t tag_len); + +/***************************************************************************//** + * @brief + * This function feeds an input buffer into an ongoing CCM computation. + * + * It is called between sl_se_ccm_multipart_starts() and sl_se_ccm_multipart_finish(). + * Can be called repeatedly. + * + * @param[in] ccm_ctx + * Pointer to a CCM streaming context object. + * + * @param[in] cmd_ctx + * Pointer to a SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the input data. This must be a multiple of 16 except in + * the last call before sl_se_ccm_multipart_finish(). + * + * @param[in] input + * Buffer holding the input data, must be at least @p length bytes wide. + * + * @param[out] output + * Buffer for holding the output data, must be at least @p length bytes wide. + * + * @param[out] output_length + * Length of data that has been encrypted/decrypted. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ + +sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length); + +/***************************************************************************//** + * @brief + * Finish a CCM streaming operation and return the resulting CCM tag. + * + * It is called after sl_se_ccm_multipart_update(). + * + * @param[in] ccm_ctx + * Pointer to a CCM streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in, out] tag + * Encryption: The buffer for holding the tag. + * Decryption: The tag to authenticate. + * + * @param[in] tag_size + * The size of the tag buffer. Must be equal or greater to the length of the expected tag. + * + * @param[out] output + * Buffer for holding the output data. + * + * @param[in] output_size + * Output buffer size. Must be equal or greater to the stored data from + * sl_se_ccm_multipart_update (maximum 16 bytes). + * + * @param[out] output_length + * Length of data that has been encrypted/decrypted. + * + * @return + * Returns SL_SE_INVALID_SIGNATURE if authentication step fails. + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_size, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length); + +/***************************************************************************//** + * @brief + * This function performs GCM encryption or decryption of a buffer. + * + * @note + * For encryption, the output buffer can be the same as the input buffer. + * For decryption, the output buffer cannot be the same as input buffer. + * If the buffers overlap, the output buffer must trail at least 8 bytes + * behind the input buffer. + * + * @warning + * When this function performs a decryption, it outputs the authentication + * tag and does not verify that the data is authentic. You should use this + * function to perform encryption only. For decryption, use + * sl_se_gcm_auth_decrypt() instead. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * - SL_SE_ENCRYPT: The ciphertext is written to @p output and the + * authentication tag is written to @p tag. + * - SL_SE_DECRYPT: The plaintext is written to @p output and the + * authentication tag is written to @p tag. + * Note that this mode is not recommended, because it does + * not verify the authenticity of the data. For this + * reason, you should use sl_se_gcm_auth_decrypt() instead. + * + * @param[in] length + * The length of the input data, which is equal to the length of the output + * data. + * + * @param[in] iv + * The initialization vector. + * + * @param[in] iv_len + * The length of the iv. Must be @b 12 bytes. + * + * @param[in] add + * The buffer holding the additional data. + * + * @param[in] add_len + * The length of the additional data in bytes. + * + * @param[in] input + * The buffer holding the input data. Its size is @b length bytes. + * + * @param[out] output + * The buffer for holding the output data. It must have room for @b length + * bytes. + * + * @param[in] tag_len + * The length of the tag to generate (in bytes). + * + * @param[out] tag + * The buffer for holding the tag. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_gcm_crypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag); + +/***************************************************************************//** + * @brief + * This function performs a GCM authenticated decryption of a buffer. + * + * @note + * The output buffer cannot be the same as input buffer. If the buffers + * overlap, the output buffer must trail at least 8 bytes behind the input + * buffer. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the ciphertext to decrypt, which is also the length of the + * decrypted plaintext. + * + * @param[in] iv + * The initialization vector. + * + * @param[in] iv_len + * The length of the iv. Must be @b 12 bytes. + * + * @param[in] add + * The buffer holding the additional data. + * + * @param[in] add_len + * The length of the additional data in bytes. + * + * @param[in] tag + * The buffer holding the tag to verify. + * + * @param[in] tag_len + * The length of the tag to verify (in bytes). + * + * @param[in] input + * The buffer holding the ciphertext. Its size is @b length bytes. + * + * @param[out] output + * The buffer for holding the decrypted plaintext. It must have room for + * @b length bytes. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_gcm_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + const unsigned char *tag); + +/***************************************************************************//** + * @brief + * This function calculates the full generic CMAC on the input buffer with + * the provided key. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] input + * Buffer holding the input data, must be at least @p input_len bytes wide. + * + * @param[in] input_len + * The length of the input data in bytes. + * + * @param[out] output + * Buffer holding the 16-byte output data, must be at least 16 bytes wide. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_cmac(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + const unsigned char *input, + size_t input_len, + unsigned char *output); + +/***************************************************************************//** + * @brief + * Prepare a CMAC streaming command context object. + * + * @details + * Prepare a CMAC streaming command context object to be used in subsequent + * CMAC streaming function calls. + * + * @param[in] cmac_ctx + * Pointer to a CMAC streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_starts(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key); + +/***************************************************************************//** + * @brief + * This function feeds an input buffer into an ongoing CMAC computation. + * + * @details + * It is called between sl_se_cmac_multipart_starts() and sl_se_cmac_multipart_finish(). + * Can be called repeatedly. + * + * @param[in,out] cmac_ctx + * Pointer to a CMAC streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] input + * Buffer holding the input data, must be at least @p input_len bytes wide. + * + * @param[in] input_len + * The length of the input data in bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_update(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + const uint8_t *input, + size_t input_len); + +/***************************************************************************//** + * @brief + * Finish a CMAC streaming operation and return the resulting CMAC tag. + * + * @details + * It is called after sl_se_cmac_multipart_update(). + * + * @param[in,out] cmac_ctx + * Pointer to a CMAC streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[out] output + * Buffer holding the 16-byte CMAC tag, must be at least 16 bytes wide. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_finish(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *output); + +/***************************************************************************//** + * @brief + * Prepare a GCM streaming command context object. + * + * @details + * Prepare a GCM streaming command context object to be used in subsequent + * GCM streaming function calls. + * + * @param[in, out] gcm_ctx + * Pointer to a GCM streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] mode + * The operation to perform: SL_SE_ENCRYPT or SL_SE_DECRYPT. + * + * @param[in] iv + * The initialization vector. + * + * @param[in] iv_len + * The length of the IV. + * + * @param[in] add + * The buffer holding the additional data, or NULL if @p add_len is 0. + * + * @param[in] add_len + * The length of the additional data. If 0, @p add is NULL. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + const uint8_t *iv, + size_t iv_len, + const uint8_t *add, + size_t add_len); + +/***************************************************************************//** + * @brief + * This function feeds an input buffer into an ongoing GCM computation. + * + * It is called between sl_se_gcm_multipart_starts() and sl_se_gcm_multiapart_finish(). + * Can be called repeatedly. + * + * @param[in, out] gcm_ctx + * Pointer to a GCM streaming context object. + * + * @param[in] length + * The length of the input data. + * + * @param[in] input + * Buffer holding the input data, must be at least @p length bytes wide. + * + * @param[out] output + * Buffer for holding the output data, must be at least @p length bytes wide. + * + * @param[out] output_length + * Length of data that has been encrypted/decrypted. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length); + +/***************************************************************************//** + * @brief + * Finish a GCM streaming operation and return the resulting GCM tag. + * + * It is called after sl_se_gcm_multipart_update(). + * + * @param[in, out] gcm_ctx + * Pointer to a GCM streaming context object. + * + * @param[in, out] tag + * Encryption: The buffer for holding the tag. + * Decryption: The tag to authenticate. + * + * @param[in] tag_length + * Encryption: Length of the output tag. + * Decryption: Length of tag to verify + * + * @param[out] output + * Buffer for holding the output data. + * + * @param[in] output_size + * Output buffer size. Must be equal or greater to the stored data from + * sl_se_gcm_multipart_update (stored data is maximum 16 bytes). + * + * @param[out] output_length + * Length of data that has been encrypted/decrypted. + * + * @return + * Returns SL_SE_INVALID_SIGNATURE if authentication step fails. + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_finish(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_length, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length); + +/***************************************************************************//** + * @brief + * Compute a HMAC on a full message. + * + * @details + * This function computes a Keyed-Hashed Message Authentication Code (HMAC) + * for the given input message. HMAC can be used with any iterative + * cryptographic hash function, e.g., SHA-1 in combination with a + * secret shared key. The cryptographic strength of HMAC depends on the + * properties of the underlying hash function. For instance, if the algorithm + * is chosen to be SHA-256, it will generate a 32 bytes HMAC. + * This function supports SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512. + * The key can be of any length. If the key is shorter than the block size + * of the hash function the SE will append zeros to the key so the key size + * matches the block size of the hash function. If the key is longer than the + * block size of the hash function the key will be hashed to + * produce a key digest, then append zeros so the resulting 'hashed' key size + * matches the block size of the hash function. In any case the minimal + * recommended key length is the digest size of the hash function. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure specifying the key to use in + * the HMAC computation. + * + * @param[in] hash_type + * Which hashing algorithm to use. + * + * @param[in] message + * Pointer to the message buffer to compute the hash/digest from. + * + * @param[in] message_len + * Number of bytes in message. + * + * @param[out] output + * Pointer to memory buffer to store the final HMAC output. + * + * @param[in] output_len + * The length of the HMAC output memory buffer, must be at least the size + * of the corresponding hash type. + * + * @return Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hmac(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *output, + size_t output_len); + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief + * ChaCha20 buffer encryption/decryption, as defined by RFC8439 section 2.4. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] mode + * Crypto operation type (encryption or decryption). + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * Length of the input data. + * + * @param[in] initial_counter + * The initial counter value as defined in RFC8439 section 2.4. + * + * @param[in] nonce + * The nonce, also called initialisation vector, as defined in RFC8439 section + * 2.4. + * + * @param[in] input + * Buffer holding the input data. + * + * @param[out] output + * Buffer holding the output data. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_chacha20_crypt(sl_se_command_context_t *cmd_ctx, + sl_se_cipher_operation_t mode, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char initial_counter[4], + const unsigned char nonce[12], + const unsigned char *input, + unsigned char *output); + +/***************************************************************************//** + * @brief + * ChaCha20-Poly1305 authenticated encryption with additional data, as defined + * by RFC8439 section 2.8. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the input data in bytes. + * + * @param[in] nonce + * The nonce, also called initialisation vector, as defined in RFC8439 section + * 2.8. + * + * @param[in] add + * The buffer holding additional authenticated data. Can be NULL if @p add_len + * equals 0. + * + * @param[in] add_len + * The length of the additional authenticated data in bytes. + * + * @param[in] input + * The buffer holding the plaintext input. + * + * @param[out] output + * The buffer holding the ciphertext output. Can be NULL, in which case the + * generated ciphertext will be discarded. Must be at least @p length bytes + * wide. + * + * @param[out] tag + * The buffer holding the tag. This function will produce a 128-bit tag, so + * this buffer must be at least 16 bytes wide. Can be NULL, in which case the + * generated tag will be discarded. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_chacha20_poly1305_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + unsigned char *tag); + +/***************************************************************************//** + * @brief + * ChaCha20-Poly1305 authenticated decryption with additional data, as defined + * by RFC8439 section 2.8. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] length + * The length of the input data in Bytes. + * + * @param[in] nonce + * The nonce, also called initialisation vector, as defined in RFC8439 section + * 2.8. + * + * @param[in] add + * The buffer holding additional authenticated data. Can be NULL if @p add_len + * equals 0. + * + * @param[in] add_len + * The length of the additional authenticated data in bytes. + * + * @param[in] input + * The buffer holding the ciphertext to decrypt. Can be NULL if @p length + * equals 0. + * + * @param[out] output + * The buffer holding the plaintext output. Can be NULL, in which case the + * decrypted plaintext will be discarded, or when @p length equals 0. Must be + * at least @p length bytes wide. + * + * @param[in] tag + * The buffer holding the tag to verify. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_chacha20_poly1305_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + const unsigned char tag[16]); + +/***************************************************************************//** + * @brief + * Generate a Poly1305 MAC (message authentication code) for a given message + * using an ephemeral key derived using ChaCha20. + * + * @note + * This function first derives a Poly1305 key based on a ChaCha20 key and + * nonce, which are input to this function. The key derivation adheres to + * RFC8439 section 2.6. The derived key is then used to calculate a MAC of the + * input data, according to RFC8439 section 2.5. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure containing a ChaCha20 key. + * + * @param[in] length + * The length of the input data in Bytes. + * + * @param[in] nonce + * The nonce, also called initialisation vector, as defined in RFC8439 section + * 2.6. + * + * @param[in] input + * The buffer holding the input data. + * + * @param[out] tag + * The buffer holding the tag. This function will produce a 128-bit tag, so + * this buffer must be at least 16 bytes wide. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *input, + unsigned char *tag); + +#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_cipher) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_CIPHER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_config.h index ba5014b..8a473a6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_config.h @@ -1,63 +1,63 @@ -/**************************************************************************/ /** - * @file - * @brief SE Manager configuration options - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SE_MANAGER_CONFIG_H -#define SL_SE_MANAGER_CONFIG_H - -/// This file include the configuration options of the SE Manager. -/// For the time being the user should not change the default settings -/// of the configuration options in this file. - -#if defined (SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) -// Threading support (as opposed to API calls only from a single thread) -// is currently required in RTOS mode. - #define SL_SE_MANAGER_THREADING - - #if !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) -// Enable yield support. Configure sl_se_command_context_t to yield CPU while waiting for SE commands. -// This is not supported on EFR32xG22. - #define SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION - #endif -#endif - -#ifndef SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED - #define SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED 1 -#endif - -// Check consistency of configuration options. -// Always include se_manager_check_config.h in order to assert that the -// configuration options dependencies and restrictions are ok. -#include "sl_se_manager_check_config.h" - -#endif // SL_SE_MANAGER_CONFIG_H +/**************************************************************************/ /** + * @file + * @brief SE Manager configuration options + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SE_MANAGER_CONFIG_H +#define SL_SE_MANAGER_CONFIG_H + +/// This file include the configuration options of the SE Manager. +/// For the time being the user should not change the default settings +/// of the configuration options in this file. + +#if defined (SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT) +// Threading support (as opposed to API calls only from a single thread) +// is currently required in RTOS mode. + #define SL_SE_MANAGER_THREADING + + #if !defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) && !defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +// Enable yield support. Configure sl_se_command_context_t to yield CPU while waiting for SE commands. +// This is not supported on EFR32xG22. + #define SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION + #endif +#endif + +#ifndef SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED + #define SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED 1 +#endif + +// Check consistency of configuration options. +// Always include se_manager_check_config.h in order to assert that the +// configuration options dependencies and restrictions are ok. +#include "sl_se_manager_check_config.h" + +#endif // SL_SE_MANAGER_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h index 56b60d9..f212778 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_defines.h @@ -1,505 +1,505 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API definitions - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_DEFINES_H -#define SL_SE_MANAGER_DEFINES_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) -#if !defined(SL_TRUSTZONE_NONSECURE) -#if !defined(SE_MANAGER_CONFIG_FILE) -#include "sl_se_manager_config.h" -#else -#include SE_MANAGER_CONFIG_FILE -#endif // SE_MANAGER_CONFIG_FILE -#endif // SL_TRUSTZONE_NONSECURE -#endif // SLI_SE_MANAGER_HOST_SYSTEM - -#if defined (SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -/// @addtogroup sl_se_manager -/// @{ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -/// @addtogroup sl_se_manager_util -/// @{ - -/// Default configuration for OTP initialisation structure. -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define SL_SE_OTP_INIT_DEFAULT \ - { \ - .enable_secure_boot = false, \ - .verify_secure_boot_certificate = false, \ - .enable_anti_rollback = false, \ - .secure_boot_page_lock_narrow = false, \ - .secure_boot_page_lock_full = false, \ - .tamper_levels = { 0 }, \ - .tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_2MIN, \ - .tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4, \ - .tamper_flags = 0, \ - .tamper_reset_threshold = 5 \ - } -#else - #define SL_SE_OTP_INIT_DEFAULT \ - { \ - .enable_secure_boot = false, \ - .verify_secure_boot_certificate = false, \ - .enable_anti_rollback = false, \ - .secure_boot_page_lock_narrow = false, \ - .secure_boot_page_lock_full = false \ - } -#endif - -/// @} (end addtogroup sl_se_manager_util) - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -// ------------------------------- -// Defines for SE functionality - -/// @addtogroup sl_se_manager_key_handling -/// @{ - -/// Asymmetric key can only be used for signing (not key exchange) -#define SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY (1UL << 10) -/// Described key belongs to a custom ECC domain -#define SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN (1UL << 12) -/// Storage buffer contains public part of an asymmetric key -#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY (1UL << 13) -/// Storage buffer contains private part of an asymmetric key -#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY (1UL << 14) -/// Allow usage of this key by other bus masters or TrustZone levels than the -/// one which created/imported the key -#define SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS (1UL << 15) -/// Old definition. Retained for backwards compatibility. -#define SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY \ - (SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY) - -/// Do not allow exporting the key to plaintext -#define SL_SE_KEY_FLAG_NON_EXPORTABLE (1UL << 24) -/// Indicate that the key has been generated by this device. This flag is only -/// valid when using the SE to generate a key and makes it non-exportable. -#define SL_SE_KEY_FLAG_IS_DEVICE_GENERATED (1UL << 25) -/// Indicate that the key can only be used to sign SE generated content. This -/// flag is only valid when using the SE to generate a key and makes it -/// non-exportable. -#define SL_SE_KEY_FLAG_IS_RESTRICTED (1UL << 25 | 1UL << 24) - -/// Mask for algorithm field in key type -#define SL_SE_KEY_TYPE_ALGORITHM_MASK 0xf0000000 -/// Offset of algorithm field in key type -#define SL_SE_KEY_TYPE_ALGORITHM_OFFSET 28 -/// Mask for attributes field in key type -#define SL_SE_KEY_TYPE_ATTRIBUTES_MASK 0x00007fff -/// Offset of attributes field in key type -#define SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET 0 - -/// Symmetric key type -#define SL_SE_KEY_TYPE_SYMMETRIC 0x00000000 -/// Symmetric key type for AES-128 (16 byte key) -#define SL_SE_KEY_TYPE_AES_128 0x00000010 -/// Symmetric key type for AES-192 (24 byte key) -#define SL_SE_KEY_TYPE_AES_192 0x00000018 -/// Symmetric key type for AES-256 (32 byte key) -#define SL_SE_KEY_TYPE_AES_256 0x00000020 - -/// ECC Weierstrass Prime key type -#define SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM (0x8U << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) -/// ECC Montgomery key type -#define SL_SE_KEY_TYPE_ECC_MONTGOMERY (0xbU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) -/// EDDSA key type -#define SL_SE_KEY_TYPE_ECC_EDDSA (0xcU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) - -/// ECC NIST P-192 -#define SL_SE_KEY_TYPE_ECC_P192 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x18)) -/// ECC NIST P-224 -#define SL_SE_KEY_TYPE_ECC_P224 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x1C)) -/// ECC NIST P-256 -#define SL_SE_KEY_TYPE_ECC_P256 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x20)) - -/// ECC Ed25519 key for EdDSA -#define SL_SE_KEY_TYPE_ECC_ED25519 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x20)) - -/// ECC X25519 key for ECDH -#define SL_SE_KEY_TYPE_ECC_X25519 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x20)) - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Symmetric key type for ChaCha20 - #define SL_SE_KEY_TYPE_CHACHA20 0x00000020 - -/// ECC NIST P-384 - #define SL_SE_KEY_TYPE_ECC_P384 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x30)) -/// ECC NIST P-521 - #define SL_SE_KEY_TYPE_ECC_P521 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x42)) - -/// ECC X448 key for ECDH - #define SL_SE_KEY_TYPE_ECC_X448 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x38)) - -/// ECC Ed448 key for EdDSA - #define SL_SE_KEY_TYPE_ECC_ED448 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x38)) - -#endif - -/// Key storage methods - -/// Key is stored in a plaintext buffer in application memory. Application -/// can save its in-memory buffer to non-volatile memory as needed to -/// provide key persistence. -#define SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT 0x00 -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Key is stored encrypted in application memory. This ensures the key in -/// wrapped form is only usable on a specific device. If the key -/// additionally needs to be prevented from ever being output as plaintext, -/// also set the corresponding permission bit. Application can save its -/// in-memory buffer to non-volatile memory as needed to provide key -/// persistence. -/// Keys stored in this way should use the flag -/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access -/// the key value outside the SE. - #define SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED 0x01 -/// Key is stored inside the SE, and will persist until system reset or -/// explicitly deleted. -/// Keys stored in this way should use the flag -/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access -/// the key value outside the SE. - #define SL_SE_KEY_STORAGE_INTERNAL_VOLATILE 0x02 -#endif -/// Key is one of the pre-defined keys (pre-loaded or write-once) available -/// in the SE. See documentation for a list of available keys. -#define SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE 0x03 - -/// List of available internal SE key slots -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define SL_SE_KEY_SLOT_VOLATILE_0 0x00 ///< Internal volatile slot 0 - #define SL_SE_KEY_SLOT_VOLATILE_1 0x01 ///< Internal volatile slot 1 - #define SL_SE_KEY_SLOT_VOLATILE_2 0x02 ///< Internal volatile slot 2 - #define SL_SE_KEY_SLOT_VOLATILE_3 0x03 ///< Internal volatile slot 3 -#endif - -/// Minimum key slot value for internal keys -#define SL_SE_KEY_SLOT_INTERNAL_MIN 0xF7 - -/// Internal TrustZone root key -#define SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY 0xF7 -/// Internal immutable application secure debug key -#define SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY 0xF8 -/// Internal immutable application AES-128 key (bootloader key) -#define SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY 0xFA -/// Internal immutable application secure boot key -#define SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY 0xFC -/// Internal immutable application attestation key -#define SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY 0xFE -/// Internal immutable SE attestation key -#define SL_SE_KEY_SLOT_SE_ATTESTATION_KEY 0xFF - -/// Size overhead for wrapped keys -#define SLI_SE_WRAPPED_KEY_OVERHEAD (12 + 16) -/// @} (end addtogroup sl_se_manager_key_handling) - -/// @addtogroup sl_se_manager_key_derivation -/// @{ - -/// Defines mapping the PBKDF2 PRFs to corresponding sl_se_hash_type_t values. -#define SL_SE_PRF_AES_CMAC_128 SL_SE_HASH_NONE ///< CMAC-AES-128 -#define SL_SE_PRF_HMAC_SHA1 SL_SE_HASH_SHA1 ///< HMAC-SHA-1 -#define SL_SE_PRF_HMAC_SHA224 SL_SE_HASH_SHA224 ///< HMAC-SHA-224 -#define SL_SE_PRF_HMAC_SHA256 SL_SE_HASH_SHA256 ///< HMAC-SHA-256 -#define SL_SE_PRF_HMAC_SHA384 SL_SE_HASH_SHA384 ///< HMAC-SHA-384 -#define SL_SE_PRF_HMAC_SHA512 SL_SE_HASH_SHA512 ///< HMAC-SHA-512 - -/// @} (end addtogroup sl_se_manager_key_derivation) - -/// @addtogroup sl_se_manager_util -/// @{ - -/// SE Challenge size -#define SL_SE_CHALLENGE_SIZE 16 - -/// Certificate key size -#define SL_SE_CERT_KEY_SIZE 64 - -/// Certificate signature size -#define SL_SE_CERT_SIGN_SIZE 64 - -/// Batch ID certificate -#define SL_SE_CERT_BATCH 0x01 -/// SE ID certificate -#define SL_SE_CERT_DEVICE_SE 0x02 -/// Host ID certificate -#define SL_SE_CERT_DEVICE_HOST 0x03 - -/// @addtogroup sl_se_manager_util_tamper Tamper options -/// @brief -/// Tamper configuration options. Levels, signals and filter options. -/// @{ - -// SE tamper signal levels -#define SL_SE_TAMPER_LEVEL_IGNORE 0 ///< No action taken -#define SL_SE_TAMPER_LEVEL_INTERRUPT 1 ///< Generate interrupt -#define SL_SE_TAMPER_LEVEL_FILTER 2 ///< Increment filter counter -#define SL_SE_TAMPER_LEVEL_RESET 4 ///< System reset -#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP 7 ///< Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL! - -// SE tamper signals -#if defined(SLI_SE_MAJOR_VERSION_ONE) - -#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold -#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout -#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_RAM_CRC 0x4 ///< SE RAM CRC parity error -#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault -#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert -#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed -#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed -#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface -#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface -#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated -#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected -#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy -#define SL_SE_TAMPER_SIGNAL_PRS0 0x10 ///< PRS channel 0 asserted -#define SL_SE_TAMPER_SIGNAL_PRS1 0x11 ///< PRS channel 1 asserted -#define SL_SE_TAMPER_SIGNAL_PRS2 0x12 ///< PRS channel 2 asserted -#define SL_SE_TAMPER_SIGNAL_PRS3 0x13 ///< PRS channel 3 asserted -#define SL_SE_TAMPER_SIGNAL_PRS4 0x14 ///< PRS channel 4 asserted -#define SL_SE_TAMPER_SIGNAL_PRS5 0x15 ///< PRS channel 5 asserted -#define SL_SE_TAMPER_SIGNAL_PRS6 0x16 ///< PRS channel 6 asserted -#define SL_SE_TAMPER_SIGNAL_PRS7 0x17 ///< PRS channel 7 asserted -#define SL_SE_TAMPER_SIGNAL_DECOUPLE_BOD 0x18 ///< Decouple brown-out-detector threshold alert -#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x19 ///< On-device temperature sensor detects operation outside datasheet specification -#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_FALLING 0x1A ///< Voltage glitch detector detected falling glitch -#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_RISING 0x1B ///< Voltage glitch detector detected rising glitch -#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x1C ///< Debug lock internal logic check failed -#define SL_SE_TAMPER_SIGNAL_SE_DEBUG_GRANTED 0x1D ///< SE debug granted -#define SL_SE_TAMPER_SIGNAL_DIGITAL_GLITCH 0x1E ///< Digital glitch detector detected an event -#define SL_SE_TAMPER_SIGNAL_SE_ICACHE_ERROR 0x1F ///< SE ICACHE checksum error -#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals - -#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) - -// SE tamper signals for xG25, with ETAMPDET signal included. -#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold -#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout -#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4 ///< SE RAM 2-bit ECC error -#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault -#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert -#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed -#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed -#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface -#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface -#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated -#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected -#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy -#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10 ///< Debug lock internal logic check failed -#define SL_SE_TAMPER_ATAMPDET_EMPGD 0x11 ///< Electromagnetic pulse glitch detector -#define SL_SE_TAMPER_ATAMPDET_SUPGD 0x12 ///< Supply glitch detector -#define SL_SE_TAMPER_SE_ICACHE_ERROR 0x13 ///< SE ICache RAM error -#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14 ///< SE RAM 1-bit ECC error -#define SL_SE_TAMPER_SIGNAL_BOD 0x15 ///< Brown-out-detector threshold alert -#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16 ///< On-device temperature sensor -#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW 0x17 ///< DPLL lock fail low -#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH 0x18 ///< DPLL lock fail high -#define SL_SE_TAMPER_SIGNAL_ETAMPDET 0x19 ///< External tamper detect -#define SL_SE_TAMPER_SIGNAL_PRS0 0x1a ///< PRS channel 0 asserted -#define SL_SE_TAMPER_SIGNAL_PRS1 0x1b ///< PRS channel 1 asserted -#define SL_SE_TAMPER_SIGNAL_PRS2 0x1c ///< PRS channel 2 asserted -#define SL_SE_TAMPER_SIGNAL_PRS3 0x1d ///< PRS channel 3 asserted -#define SL_SE_TAMPER_SIGNAL_PRS4 0x1e ///< PRS channel 4 asserted -#define SL_SE_TAMPER_SIGNAL_PRS5 0x1f ///< PRS channel 5 asserted -#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals - -#else - -// SE tamper signals -#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold -#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout -#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4 ///< SE RAM 2-bit ECC error -#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault -#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert -#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed -#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed -#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface -#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface -#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated -#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal -#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected -#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy -#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10 ///< Debug lock internal logic check failed -#define SL_SE_TAMPER_ATAMPDET_EMPGD 0x11 ///< Electromagnetic pulse glitch detector -#define SL_SE_TAMPER_ATAMPDET_SUPGD 0x12 ///< Supply glitch detector -#define SL_SE_TAMPER_SE_ICACHE_ERROR 0x13 ///< SE ICache RAM error -#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14 ///< SE RAM 1-bit ECC error -#define SL_SE_TAMPER_SIGNAL_BOD 0x15 ///< Brown-out-detector threshold alert -#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16 ///< On-device temperature sensor -#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW 0x17 ///< DPLL lock fail low -#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH 0x18 ///< DPLL lock fail high -#define SL_SE_TAMPER_SIGNAL_PRS0 0x19 ///< PRS channel 0 asserted -#define SL_SE_TAMPER_SIGNAL_PRS1 0x1a ///< PRS channel 1 asserted -#define SL_SE_TAMPER_SIGNAL_PRS2 0x1b ///< PRS channel 2 asserted -#define SL_SE_TAMPER_SIGNAL_PRS3 0x1c ///< PRS channel 3 asserted -#define SL_SE_TAMPER_SIGNAL_PRS4 0x1d ///< PRS channel 4 asserted -#define SL_SE_TAMPER_SIGNAL_PRS5 0x1e ///< PRS channel 5 asserted -#define SL_SE_TAMPER_SIGNAL_PRS6 0x1f ///< PRS channel 6 asserted -#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals - -#endif - -// SE tamper filter timeout period. -#define SL_SE_TAMPER_FILTER_PERIOD_32MS 0x0 ///< Timeout ~32ms -#define SL_SE_TAMPER_FILTER_PERIOD_64MS 0x1 ///< Timeout ~64ms -#define SL_SE_TAMPER_FILTER_PERIOD_128MS 0x2 ///< Timeout ~128ms -#define SL_SE_TAMPER_FILTER_PERIOD_256MS 0x3 ///< Timeout ~256ms -#define SL_SE_TAMPER_FILTER_PERIOD_512MS 0x4 ///< Timeout ~512ms -#define SL_SE_TAMPER_FILTER_PERIOD_1S 0x5 ///< Timeout ~1s -#define SL_SE_TAMPER_FILTER_PERIOD_2S 0x6 ///< Timeout ~2s -#define SL_SE_TAMPER_FILTER_PERIOD_4S 0x7 ///< Timeout ~4.1s -#define SL_SE_TAMPER_FILTER_PERIOD_8S 0x8 ///< Timeout ~8.2s -#define SL_SE_TAMPER_FILTER_PERIOD_16S 0x9 ///< Timeout ~16.4s -#define SL_SE_TAMPER_FILTER_PERIOD_33S 0xA ///< Timeout ~32.8s -#define SL_SE_TAMPER_FILTER_PERIOD_1MIN 0xB ///< Timeout ~1.1min -#define SL_SE_TAMPER_FILTER_PERIOD_2MIN 0xC ///< Timeout ~2.2min -#define SL_SE_TAMPER_FILTER_PERIOD_4MIN 0xD ///< Timeout ~4.4min -#define SL_SE_TAMPER_FILTER_PERIOD_9MIN 0xE ///< Timeout ~8.7min -#define SL_SE_TAMPER_FILTER_PERIOD_18MIN 0xF ///< Timeout ~17.5min -#define SL_SE_TAMPER_FILTER_PERIOD_35MIN 0x10 ///< Timeout ~35min -#define SL_SE_TAMPER_FILTER_PERIOD_1H 0x11 ///< Timeout ~1.2h -#define SL_SE_TAMPER_FILTER_PERIOD_2H 0x12 ///< Timeout ~2.3h -#define SL_SE_TAMPER_FILTER_PERIOD_5H 0x13 ///< Timeout ~4.7h -#define SL_SE_TAMPER_FILTER_PERIOD_9H 0x14 ///< Timeout ~9.3h -#define SL_SE_TAMPER_FILTER_PERIOD_19H 0x15 ///< Timeout ~18.6h -#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS 0x16 ///< Timeout ~1.6days -#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS 0x17 ///< Timeout ~3.1days -#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS 0x18 ///< Timeout ~6.2days -#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS 0x19 ///< Timeout ~12.4days -#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS 0x1A ///< Timeout ~24.9days -#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS 0x1B ///< Timeout ~49.7days -#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS 0x1C ///< Timeout ~99.4days -#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS 0x1D ///< Timeout ~198.8days -#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS 0x1E ///< Timeout ~397.7days -#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS 0x1F ///< Timeout ~795.4days - -// Number of tamper counts to trigger the filter signal. -#define SL_SE_TAMPER_FILTER_THRESHOLD_2 0x7 ///< Counter threshold 2 -#define SL_SE_TAMPER_FILTER_THRESHOLD_4 0x6 ///< Counter threshold 4 -#define SL_SE_TAMPER_FILTER_THRESHOLD_8 0x5 ///< Counter threshold 8 -#define SL_SE_TAMPER_FILTER_THRESHOLD_16 0x4 ///< Counter threshold 16 -#define SL_SE_TAMPER_FILTER_THRESHOLD_32 0x3 ///< Counter threshold 32 -#define SL_SE_TAMPER_FILTER_THRESHOLD_64 0x2 ///< Counter threshold 64 -#define SL_SE_TAMPER_FILTER_THRESHOLD_128 0x1 ///< Counter threshold 128 -#define SL_SE_TAMPER_FILTER_THRESHOLD_256 0x0 ///< Counter threshold 256 - -/// Tamper flags. -#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1) /// Digital glitch detector always on -#define SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2) /// Tamper is kept alive during sleep (down to EM3) - -/// @} (end addtogroup sl_se_manager_util_tamper) - -/// @} (end addtogroup sl_se_manager_util) - -/// @addtogroup sl_se_manager_core -/// @{ - -/// Context initialization values. Some of the context values are not fully -/// initialized. The user will need to call the corresponding initialization -/// function in order to fully initialize the context objects for further use -/// in the SE Manager API. The purpose of these initialization values is to set -/// the context objects to a known safe state initially when the context object -/// is declared. -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) -#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0), false } -#else -#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0) } -#endif - -/// @} (end addtogroup sl_se_manager_core) - -/// @addtogroup sl_se_manager_cipher -/// @{ - -/// Initial values for CMAC streaming context struct @ref sl_se_cmac_streaming_context_t -#define SL_SE_CMAC_STREAMING_INIT_DEFAULT { NULL, { 0 }, { 0 }, 0 } - -/// Initial values for AES-GCM streaming context struct @ref sl_se_gcm_streaming_context_t -#define SL_SE_GCM_STREAMING_INIT_DEFAULT { NULL, 0, 0, { 0 }, { 0 }, \ - { 0 }, 0, 0 } - -/// Block size for the AES -#define SL_SE_AES_BLOCK_SIZE (16u) - -/// @} (end addtogroup sl_se_manager_cipher) - -/// @addtogroup sl_se_manager_hash -/// @{ -#define SL_SE_HASH_STREAMING_INIT_DEFAULT { NULL, 0, 0, NULL } ///< Default streaming hash context -#define SL_SE_SHA1_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA1 streaming hash context -#define SL_SE_SHA224_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA224 streaming hash context -#define SL_SE_SHA256_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA256 streaming hash context -#define SL_SE_SHA384_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA384 streaming hash context -#define SL_SE_SHA512_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA512 streaming hash context -/// @} (end addtogroup sl_se_manager_hash) - -#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) // defined(SLI_MAILBOX_COMMAND_SUPPORTED) -// ------------------------------- -// Defines for Root code functionality - -#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0) } -#define SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT 16U - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#endif // SE_MANAGER_DEFINES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API definitions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_DEFINES_H +#define SL_SE_MANAGER_DEFINES_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) +#if !defined(SL_TRUSTZONE_NONSECURE) +#if !defined(SE_MANAGER_CONFIG_FILE) +#include "sl_se_manager_config.h" +#else +#include SE_MANAGER_CONFIG_FILE +#endif // SE_MANAGER_CONFIG_FILE +#endif // SL_TRUSTZONE_NONSECURE +#endif // SLI_SE_MANAGER_HOST_SYSTEM + +#if defined (SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +/// @addtogroup sl_se_manager +/// @{ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +/// @addtogroup sl_se_manager_util +/// @{ + +/// Default configuration for OTP initialisation structure. +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SL_SE_OTP_INIT_DEFAULT \ + { \ + .enable_secure_boot = false, \ + .verify_secure_boot_certificate = false, \ + .enable_anti_rollback = false, \ + .secure_boot_page_lock_narrow = false, \ + .secure_boot_page_lock_full = false, \ + .tamper_levels = { 0 }, \ + .tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_2MIN, \ + .tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4, \ + .tamper_flags = 0, \ + .tamper_reset_threshold = 5 \ + } +#else + #define SL_SE_OTP_INIT_DEFAULT \ + { \ + .enable_secure_boot = false, \ + .verify_secure_boot_certificate = false, \ + .enable_anti_rollback = false, \ + .secure_boot_page_lock_narrow = false, \ + .secure_boot_page_lock_full = false \ + } +#endif + +/// @} (end addtogroup sl_se_manager_util) + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +// ------------------------------- +// Defines for SE functionality + +/// @addtogroup sl_se_manager_key_handling +/// @{ + +/// Asymmetric key can only be used for signing (not key exchange) +#define SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY (1UL << 10) +/// Described key belongs to a custom ECC domain +#define SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN (1UL << 12) +/// Storage buffer contains public part of an asymmetric key +#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY (1UL << 13) +/// Storage buffer contains private part of an asymmetric key +#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY (1UL << 14) +/// Allow usage of this key by other bus masters or TrustZone levels than the +/// one which created/imported the key +#define SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS (1UL << 15) +/// Old definition. Retained for backwards compatibility. +#define SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY \ + (SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY) + +/// Do not allow exporting the key to plaintext +#define SL_SE_KEY_FLAG_NON_EXPORTABLE (1UL << 24) +/// Indicate that the key has been generated by this device. This flag is only +/// valid when using the SE to generate a key and makes it non-exportable. +#define SL_SE_KEY_FLAG_IS_DEVICE_GENERATED (1UL << 25) +/// Indicate that the key can only be used to sign SE generated content. This +/// flag is only valid when using the SE to generate a key and makes it +/// non-exportable. +#define SL_SE_KEY_FLAG_IS_RESTRICTED (1UL << 25 | 1UL << 24) + +/// Mask for algorithm field in key type +#define SL_SE_KEY_TYPE_ALGORITHM_MASK 0xf0000000 +/// Offset of algorithm field in key type +#define SL_SE_KEY_TYPE_ALGORITHM_OFFSET 28 +/// Mask for attributes field in key type +#define SL_SE_KEY_TYPE_ATTRIBUTES_MASK 0x00007fff +/// Offset of attributes field in key type +#define SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET 0 + +/// Symmetric key type +#define SL_SE_KEY_TYPE_SYMMETRIC 0x00000000 +/// Symmetric key type for AES-128 (16 byte key) +#define SL_SE_KEY_TYPE_AES_128 0x00000010 +/// Symmetric key type for AES-192 (24 byte key) +#define SL_SE_KEY_TYPE_AES_192 0x00000018 +/// Symmetric key type for AES-256 (32 byte key) +#define SL_SE_KEY_TYPE_AES_256 0x00000020 + +/// ECC Weierstrass Prime key type +#define SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM (0x8U << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) +/// ECC Montgomery key type +#define SL_SE_KEY_TYPE_ECC_MONTGOMERY (0xbU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) +/// EDDSA key type +#define SL_SE_KEY_TYPE_ECC_EDDSA (0xcU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET) + +/// ECC NIST P-192 +#define SL_SE_KEY_TYPE_ECC_P192 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x18)) +/// ECC NIST P-224 +#define SL_SE_KEY_TYPE_ECC_P224 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x1C)) +/// ECC NIST P-256 +#define SL_SE_KEY_TYPE_ECC_P256 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x20)) + +/// ECC Ed25519 key for EdDSA +#define SL_SE_KEY_TYPE_ECC_ED25519 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x20)) + +/// ECC X25519 key for ECDH +#define SL_SE_KEY_TYPE_ECC_X25519 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x20)) + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Symmetric key type for ChaCha20 + #define SL_SE_KEY_TYPE_CHACHA20 0x00000020 + +/// ECC NIST P-384 + #define SL_SE_KEY_TYPE_ECC_P384 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x30)) +/// ECC NIST P-521 + #define SL_SE_KEY_TYPE_ECC_P521 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x42)) + +/// ECC X448 key for ECDH + #define SL_SE_KEY_TYPE_ECC_X448 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x38)) + +/// ECC Ed448 key for EdDSA + #define SL_SE_KEY_TYPE_ECC_ED448 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x38)) + +#endif + +/// Key storage methods + +/// Key is stored in a plaintext buffer in application memory. Application +/// can save its in-memory buffer to non-volatile memory as needed to +/// provide key persistence. +#define SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT 0x00 +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Key is stored encrypted in application memory. This ensures the key in +/// wrapped form is only usable on a specific device. If the key +/// additionally needs to be prevented from ever being output as plaintext, +/// also set the corresponding permission bit. Application can save its +/// in-memory buffer to non-volatile memory as needed to provide key +/// persistence. +/// Keys stored in this way should use the flag +/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access +/// the key value outside the SE. + #define SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED 0x01 +/// Key is stored inside the SE, and will persist until system reset or +/// explicitly deleted. +/// Keys stored in this way should use the flag +/// SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access +/// the key value outside the SE. + #define SL_SE_KEY_STORAGE_INTERNAL_VOLATILE 0x02 +#endif +/// Key is one of the pre-defined keys (pre-loaded or write-once) available +/// in the SE. See documentation for a list of available keys. +#define SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE 0x03 + +/// List of available internal SE key slots +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SL_SE_KEY_SLOT_VOLATILE_0 0x00 ///< Internal volatile slot 0 + #define SL_SE_KEY_SLOT_VOLATILE_1 0x01 ///< Internal volatile slot 1 + #define SL_SE_KEY_SLOT_VOLATILE_2 0x02 ///< Internal volatile slot 2 + #define SL_SE_KEY_SLOT_VOLATILE_3 0x03 ///< Internal volatile slot 3 +#endif + +/// Minimum key slot value for internal keys +#define SL_SE_KEY_SLOT_INTERNAL_MIN 0xF7 + +/// Internal TrustZone root key +#define SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY 0xF7 +/// Internal immutable application secure debug key +#define SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY 0xF8 +/// Internal immutable application AES-128 key (bootloader key) +#define SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY 0xFA +/// Internal immutable application secure boot key +#define SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY 0xFC +/// Internal immutable application attestation key +#define SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY 0xFE +/// Internal immutable SE attestation key +#define SL_SE_KEY_SLOT_SE_ATTESTATION_KEY 0xFF + +/// Size overhead for wrapped keys +#define SLI_SE_WRAPPED_KEY_OVERHEAD (12 + 16) +/// @} (end addtogroup sl_se_manager_key_handling) + +/// @addtogroup sl_se_manager_key_derivation +/// @{ + +/// Defines mapping the PBKDF2 PRFs to corresponding sl_se_hash_type_t values. +#define SL_SE_PRF_AES_CMAC_128 SL_SE_HASH_NONE ///< CMAC-AES-128 +#define SL_SE_PRF_HMAC_SHA1 SL_SE_HASH_SHA1 ///< HMAC-SHA-1 +#define SL_SE_PRF_HMAC_SHA224 SL_SE_HASH_SHA224 ///< HMAC-SHA-224 +#define SL_SE_PRF_HMAC_SHA256 SL_SE_HASH_SHA256 ///< HMAC-SHA-256 +#define SL_SE_PRF_HMAC_SHA384 SL_SE_HASH_SHA384 ///< HMAC-SHA-384 +#define SL_SE_PRF_HMAC_SHA512 SL_SE_HASH_SHA512 ///< HMAC-SHA-512 + +/// @} (end addtogroup sl_se_manager_key_derivation) + +/// @addtogroup sl_se_manager_util +/// @{ + +/// SE Challenge size +#define SL_SE_CHALLENGE_SIZE 16 + +/// Certificate key size +#define SL_SE_CERT_KEY_SIZE 64 + +/// Certificate signature size +#define SL_SE_CERT_SIGN_SIZE 64 + +/// Batch ID certificate +#define SL_SE_CERT_BATCH 0x01 +/// SE ID certificate +#define SL_SE_CERT_DEVICE_SE 0x02 +/// Host ID certificate +#define SL_SE_CERT_DEVICE_HOST 0x03 + +/// @addtogroup sl_se_manager_util_tamper Tamper options +/// @brief +/// Tamper configuration options. Levels, signals and filter options. +/// @{ + +// SE tamper signal levels +#define SL_SE_TAMPER_LEVEL_IGNORE 0 ///< No action taken +#define SL_SE_TAMPER_LEVEL_INTERRUPT 1 ///< Generate interrupt +#define SL_SE_TAMPER_LEVEL_FILTER 2 ///< Increment filter counter +#define SL_SE_TAMPER_LEVEL_RESET 4 ///< System reset +#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP 7 ///< Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL! + +// SE tamper signals +#if defined(SLI_SE_MAJOR_VERSION_ONE) + +#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold +#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout +#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_RAM_CRC 0x4 ///< SE RAM CRC parity error +#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault +#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert +#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed +#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed +#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface +#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface +#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated +#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected +#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy +#define SL_SE_TAMPER_SIGNAL_PRS0 0x10 ///< PRS channel 0 asserted +#define SL_SE_TAMPER_SIGNAL_PRS1 0x11 ///< PRS channel 1 asserted +#define SL_SE_TAMPER_SIGNAL_PRS2 0x12 ///< PRS channel 2 asserted +#define SL_SE_TAMPER_SIGNAL_PRS3 0x13 ///< PRS channel 3 asserted +#define SL_SE_TAMPER_SIGNAL_PRS4 0x14 ///< PRS channel 4 asserted +#define SL_SE_TAMPER_SIGNAL_PRS5 0x15 ///< PRS channel 5 asserted +#define SL_SE_TAMPER_SIGNAL_PRS6 0x16 ///< PRS channel 6 asserted +#define SL_SE_TAMPER_SIGNAL_PRS7 0x17 ///< PRS channel 7 asserted +#define SL_SE_TAMPER_SIGNAL_DECOUPLE_BOD 0x18 ///< Decouple brown-out-detector threshold alert +#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x19 ///< On-device temperature sensor detects operation outside datasheet specification +#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_FALLING 0x1A ///< Voltage glitch detector detected falling glitch +#define SL_SE_TAMPER_SIGNAL_VOLTAGE_GLITCH_RISING 0x1B ///< Voltage glitch detector detected rising glitch +#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x1C ///< Debug lock internal logic check failed +#define SL_SE_TAMPER_SIGNAL_SE_DEBUG_GRANTED 0x1D ///< SE debug granted +#define SL_SE_TAMPER_SIGNAL_DIGITAL_GLITCH 0x1E ///< Digital glitch detector detected an event +#define SL_SE_TAMPER_SIGNAL_SE_ICACHE_ERROR 0x1F ///< SE ICACHE checksum error +#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals + +#elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) + +// SE tamper signals for xG25, with ETAMPDET signal included. +#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold +#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout +#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4 ///< SE RAM 2-bit ECC error +#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault +#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert +#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed +#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed +#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface +#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface +#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated +#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected +#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy +#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10 ///< Debug lock internal logic check failed +#define SL_SE_TAMPER_ATAMPDET_EMPGD 0x11 ///< Electromagnetic pulse glitch detector +#define SL_SE_TAMPER_ATAMPDET_SUPGD 0x12 ///< Supply glitch detector +#define SL_SE_TAMPER_SE_ICACHE_ERROR 0x13 ///< SE ICache RAM error +#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14 ///< SE RAM 1-bit ECC error +#define SL_SE_TAMPER_SIGNAL_BOD 0x15 ///< Brown-out-detector threshold alert +#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16 ///< On-device temperature sensor +#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW 0x17 ///< DPLL lock fail low +#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH 0x18 ///< DPLL lock fail high +#define SL_SE_TAMPER_SIGNAL_ETAMPDET 0x19 ///< External tamper detect +#define SL_SE_TAMPER_SIGNAL_PRS0 0x1a ///< PRS channel 0 asserted +#define SL_SE_TAMPER_SIGNAL_PRS1 0x1b ///< PRS channel 1 asserted +#define SL_SE_TAMPER_SIGNAL_PRS2 0x1c ///< PRS channel 2 asserted +#define SL_SE_TAMPER_SIGNAL_PRS3 0x1d ///< PRS channel 3 asserted +#define SL_SE_TAMPER_SIGNAL_PRS4 0x1e ///< PRS channel 4 asserted +#define SL_SE_TAMPER_SIGNAL_PRS5 0x1f ///< PRS channel 5 asserted +#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals + +#else + +// SE tamper signals +#define SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1 ///< Filter counter exceeds threshold +#define SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2 ///< SE watchdog timeout +#define SL_SE_TAMPER_SIGNAL_RESERVED_2 0x3 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4 ///< SE RAM 2-bit ECC error +#define SL_SE_TAMPER_SIGNAL_SE_HARDFAULT 0x5 ///< SE CPU hardfault +#define SL_SE_TAMPER_SIGNAL_RESERVED_3 0x6 ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0x7 ///< SE software triggers an assert +#define SL_SE_TAMPER_SIGNAL_SE_SECURE_BOOT_FAILED 0x8 ///< Secure boot of SE firmware failed +#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9 ///< Secure boot of user code failed +#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA ///< Unauthorised command received over the Mailbox interface +#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB ///< Unauthorised command received over the DCI interface +#define SL_SE_TAMPER_SIGNAL_FLASH_INTEGRITY_ERROR 0xC ///< Flash content couldn't be properly authenticated +#define SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD ///< Reserved tamper signal +#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE ///< Integrity error of internal storage is detected +#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF ///< TRNG monitor detected lack of entropy +#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10 ///< Debug lock internal logic check failed +#define SL_SE_TAMPER_ATAMPDET_EMPGD 0x11 ///< Electromagnetic pulse glitch detector +#define SL_SE_TAMPER_ATAMPDET_SUPGD 0x12 ///< Supply glitch detector +#define SL_SE_TAMPER_SE_ICACHE_ERROR 0x13 ///< SE ICache RAM error +#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14 ///< SE RAM 1-bit ECC error +#define SL_SE_TAMPER_SIGNAL_BOD 0x15 ///< Brown-out-detector threshold alert +#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16 ///< On-device temperature sensor +#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_LOW 0x17 ///< DPLL lock fail low +#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL_HIGH 0x18 ///< DPLL lock fail high +#define SL_SE_TAMPER_SIGNAL_PRS0 0x19 ///< PRS channel 0 asserted +#define SL_SE_TAMPER_SIGNAL_PRS1 0x1a ///< PRS channel 1 asserted +#define SL_SE_TAMPER_SIGNAL_PRS2 0x1b ///< PRS channel 2 asserted +#define SL_SE_TAMPER_SIGNAL_PRS3 0x1c ///< PRS channel 3 asserted +#define SL_SE_TAMPER_SIGNAL_PRS4 0x1d ///< PRS channel 4 asserted +#define SL_SE_TAMPER_SIGNAL_PRS5 0x1e ///< PRS channel 5 asserted +#define SL_SE_TAMPER_SIGNAL_PRS6 0x1f ///< PRS channel 6 asserted +#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20 ///< Number of tamper signals + +#endif + +// SE tamper filter timeout period. +#define SL_SE_TAMPER_FILTER_PERIOD_32MS 0x0 ///< Timeout ~32ms +#define SL_SE_TAMPER_FILTER_PERIOD_64MS 0x1 ///< Timeout ~64ms +#define SL_SE_TAMPER_FILTER_PERIOD_128MS 0x2 ///< Timeout ~128ms +#define SL_SE_TAMPER_FILTER_PERIOD_256MS 0x3 ///< Timeout ~256ms +#define SL_SE_TAMPER_FILTER_PERIOD_512MS 0x4 ///< Timeout ~512ms +#define SL_SE_TAMPER_FILTER_PERIOD_1S 0x5 ///< Timeout ~1s +#define SL_SE_TAMPER_FILTER_PERIOD_2S 0x6 ///< Timeout ~2s +#define SL_SE_TAMPER_FILTER_PERIOD_4S 0x7 ///< Timeout ~4.1s +#define SL_SE_TAMPER_FILTER_PERIOD_8S 0x8 ///< Timeout ~8.2s +#define SL_SE_TAMPER_FILTER_PERIOD_16S 0x9 ///< Timeout ~16.4s +#define SL_SE_TAMPER_FILTER_PERIOD_33S 0xA ///< Timeout ~32.8s +#define SL_SE_TAMPER_FILTER_PERIOD_1MIN 0xB ///< Timeout ~1.1min +#define SL_SE_TAMPER_FILTER_PERIOD_2MIN 0xC ///< Timeout ~2.2min +#define SL_SE_TAMPER_FILTER_PERIOD_4MIN 0xD ///< Timeout ~4.4min +#define SL_SE_TAMPER_FILTER_PERIOD_9MIN 0xE ///< Timeout ~8.7min +#define SL_SE_TAMPER_FILTER_PERIOD_18MIN 0xF ///< Timeout ~17.5min +#define SL_SE_TAMPER_FILTER_PERIOD_35MIN 0x10 ///< Timeout ~35min +#define SL_SE_TAMPER_FILTER_PERIOD_1H 0x11 ///< Timeout ~1.2h +#define SL_SE_TAMPER_FILTER_PERIOD_2H 0x12 ///< Timeout ~2.3h +#define SL_SE_TAMPER_FILTER_PERIOD_5H 0x13 ///< Timeout ~4.7h +#define SL_SE_TAMPER_FILTER_PERIOD_9H 0x14 ///< Timeout ~9.3h +#define SL_SE_TAMPER_FILTER_PERIOD_19H 0x15 ///< Timeout ~18.6h +#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS 0x16 ///< Timeout ~1.6days +#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS 0x17 ///< Timeout ~3.1days +#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS 0x18 ///< Timeout ~6.2days +#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS 0x19 ///< Timeout ~12.4days +#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS 0x1A ///< Timeout ~24.9days +#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS 0x1B ///< Timeout ~49.7days +#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS 0x1C ///< Timeout ~99.4days +#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS 0x1D ///< Timeout ~198.8days +#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS 0x1E ///< Timeout ~397.7days +#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS 0x1F ///< Timeout ~795.4days + +// Number of tamper counts to trigger the filter signal. +#define SL_SE_TAMPER_FILTER_THRESHOLD_2 0x7 ///< Counter threshold 2 +#define SL_SE_TAMPER_FILTER_THRESHOLD_4 0x6 ///< Counter threshold 4 +#define SL_SE_TAMPER_FILTER_THRESHOLD_8 0x5 ///< Counter threshold 8 +#define SL_SE_TAMPER_FILTER_THRESHOLD_16 0x4 ///< Counter threshold 16 +#define SL_SE_TAMPER_FILTER_THRESHOLD_32 0x3 ///< Counter threshold 32 +#define SL_SE_TAMPER_FILTER_THRESHOLD_64 0x2 ///< Counter threshold 64 +#define SL_SE_TAMPER_FILTER_THRESHOLD_128 0x1 ///< Counter threshold 128 +#define SL_SE_TAMPER_FILTER_THRESHOLD_256 0x0 ///< Counter threshold 256 + +/// Tamper flags. +#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1) /// Digital glitch detector always on +#define SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2) /// Tamper is kept alive during sleep (down to EM3) + +/// @} (end addtogroup sl_se_manager_util_tamper) + +/// @} (end addtogroup sl_se_manager_util) + +/// @addtogroup sl_se_manager_core +/// @{ + +/// Context initialization values. Some of the context values are not fully +/// initialized. The user will need to call the corresponding initialization +/// function in order to fully initialize the context objects for further use +/// in the SE Manager API. The purpose of these initialization values is to set +/// the context objects to a known safe state initially when the context object +/// is declared. +#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) +#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0), false } +#else +#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0) } +#endif + +/// @} (end addtogroup sl_se_manager_core) + +/// @addtogroup sl_se_manager_cipher +/// @{ + +/// Initial values for CMAC streaming context struct @ref sl_se_cmac_streaming_context_t +#define SL_SE_CMAC_STREAMING_INIT_DEFAULT { NULL, { 0 }, { 0 }, 0 } + +/// Initial values for AES-GCM streaming context struct @ref sl_se_gcm_streaming_context_t +#define SL_SE_GCM_STREAMING_INIT_DEFAULT { NULL, 0, 0, { 0 }, { 0 }, \ + { 0 }, 0, 0 } + +/// Block size for the AES +#define SL_SE_AES_BLOCK_SIZE (16u) + +/// @} (end addtogroup sl_se_manager_cipher) + +/// @addtogroup sl_se_manager_hash +/// @{ +#define SL_SE_HASH_STREAMING_INIT_DEFAULT { NULL, 0, 0, NULL } ///< Default streaming hash context +#define SL_SE_SHA1_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA1 streaming hash context +#define SL_SE_SHA224_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA224 streaming hash context +#define SL_SE_SHA256_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA256 streaming hash context +#define SL_SE_SHA384_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA384 streaming hash context +#define SL_SE_SHA512_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } } ///< SHA512 streaming hash context +/// @} (end addtogroup sl_se_manager_hash) + +#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +// ------------------------------- +// Defines for Root code functionality + +#define SL_SE_COMMAND_CONTEXT_INIT { SE_COMMAND_DEFAULT(0) } +#define SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT 16U + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#endif // SE_MANAGER_DEFINES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_entropy.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_entropy.h index 9ed79f5..0368564 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_entropy.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_entropy.h @@ -1,97 +1,97 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_ENTROPY_H -#define SL_SE_MANAGER_ENTROPY_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_entropy Entropy - * - * @brief - * Random number generators - * @details - * - * API for getting randomness from the Secure Engine True Random Number - * Generator (TRNG). - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Get random data from hardware TRNG. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] data - * Random data from TRNG. - * - * @param[in] num_bytes - * Length of data request. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_get_random(sl_se_command_context_t *cmd_ctx, - void *data, - uint32_t num_bytes); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_entropy) -/// @} (end addtogroup sl_se) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_ENTROPY_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_ENTROPY_H +#define SL_SE_MANAGER_ENTROPY_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_entropy Entropy + * + * @brief + * Random number generators + * @details + * + * API for getting randomness from the Secure Engine True Random Number + * Generator (TRNG). + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Get random data from hardware TRNG. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] data + * Random data from TRNG. + * + * @param[in] num_bytes + * Length of data request. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_get_random(sl_se_command_context_t *cmd_ctx, + void *data, + uint32_t num_bytes); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_entropy) +/// @} (end addtogroup sl_se) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_ENTROPY_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_hash.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_hash.h index 7927fdb..b29430e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_hash.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_hash.h @@ -1,308 +1,308 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_HASH_H -#define SL_SE_MANAGER_HASH_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_hash Hashing - * - * @brief - * Provides cryptographic hash functions (SHA-1, SHA-224, SHA-256, SHA-384, - * SHA-512). - * - * @details - * Provides API for one-way hashing functions. - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Produce a message digest (a hash block) using the input data. - * - * @details - * This function generates a message digest adhering to the given inputs. - * For instance, if the algorithm is chosen to be SHA-256, it will generate - * a 32 bytes message digest computed based on the input message. - * This function supports SHA-1, SHA-256 and SHA-512 algorithms. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] hash_type - * Which hashing algorithm to use. - * - * @param[in] message - * Pointer to the message buffer to compute the hash/digest from. - * - * @param[in] message_size - * Number of bytes in message. - * - * @param[out] digest - * Pointer to block of memory to store the final digest. - * - * @param[in] digest_len - * The length of the message digest (hash), must be at least the size of the - * corresponding hash type. - * - * @return Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash(sl_se_command_context_t *cmd_ctx, - sl_se_hash_type_t hash_type, - const uint8_t *message, - unsigned int message_size, - uint8_t* digest, - size_t digest_len); - -/***************************************************************************//** - * @brief - * Prepare a SHA1 hash streaming command context object. - * - * @details - * Prepare a SHA1 hash streaming command context object to be used in - * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and - * sl_se_hash_multipart_finish(). - * - * @param[in] sha1_ctx - * Pointer to a SHA1 streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_sha1_multipart_starts(sl_se_sha1_multipart_context_t *sha1_ctx, - sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Prepare a SHA224 hash streaming command context object. - * - * @details - * Prepare a SHA224 hash streaming command context object to be used in - * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and - * sl_se_hash_multipart_finish(). - * - * @param[in] sha224_ctx - * Pointer to a SHA224 streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_sha224_multipart_starts(sl_se_sha224_multipart_context_t *sha224_ctx, - sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Prepare a SHA256 hash streaming command context object. - * - * @details - * Prepare a SHA256 hash streaming command context object to be used in - * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and - * sl_se_hash_multipart_finish(). - * - * @param[in] sha256_ctx - * Pointer to a SHA256 streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_sha256_multipart_starts(sl_se_sha256_multipart_context_t *sha256_ctx, - sl_se_command_context_t *cmd_ctx); - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * @brief - * Prepare a SHA384 streaming command context object. - * - * @details - * Prepare a SHA384 hash streaming command context object to be used in - * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and - * sl_se_hash_multipart_finish(). - * - * @param[in] sha384_ctx - * Pointer to a SHA384 streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_sha384_multipart_starts(sl_se_sha384_multipart_context_t *sha384_ctx, - sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Prepare a SHA512 streaming command context object. - * - * @details - * Prepare a SHA512 hash streaming command context object to be used in - * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and - * sl_se_hash_multipart_finish(). - * - * @param[in] sha512_ctx - * Pointer to a SHA512 streaming context object. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_sha512_multipart_starts(sl_se_sha512_multipart_context_t *sha512_ctx, - sl_se_command_context_t *cmd_ctx); - -#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -/***************************************************************************//** - * @brief - * Prepare a hash streaming command context object. - * - * @details - * Prepare a hash (message digest) streaming command context object to be - * used in subsequent calls to hash streaming functions sl_se_hash_multipart_update() - * and sl_se_hash_multipart_finish(). - * - * @param[in] hash_type_ctx - * Pointer to a hash streaming context object specific to the hash type - * specified by @p hash_type. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] hash_type - * Type of hash algoritm - * - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_starts(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - sl_se_hash_type_t hash_type); - -/***************************************************************************//** - * @brief - * Feeds an input buffer into an ongoing hash computation. - * - * This function is called between @ref sl_se_hash_multipart_starts() and - * @ref sl_se_hash_multipart_finish(). - * This function can be called repeatedly. - * - * @param[in] hash_type_ctx - * Pointer to a hash streaming context object specific to the hash type - * specified by @p hash_type. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] input - * Buffer holding the input data, must be at least @p ilen bytes wide. - * - * @param[in] input_len - * The length of the input data in bytes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_update(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - const uint8_t *input, - size_t input_len); - -/***************************************************************************//** - * @brief - * Finish a hash streaming operation and return the resulting hash digest. - * - * This function is called after sl_se_hash_multipart_update(). - * - * @param[in] hash_type_ctx - * Pointer to a hash streaming context object specific to the hash type - * specified by @p hash_type. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] digest_out - * Buffer for holding the message digest (hash), must be at least the size - * of the corresponding message digest type. - * - * @param[in] digest_len - * The length of the message digest (hash), must be at least the size of the - * corresponding hash type. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_finish(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - uint8_t *digest_out, - size_t digest_len); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_hash) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_HASH_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_HASH_H +#define SL_SE_MANAGER_HASH_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_hash Hashing + * + * @brief + * Provides cryptographic hash functions (SHA-1, SHA-224, SHA-256, SHA-384, + * SHA-512). + * + * @details + * Provides API for one-way hashing functions. + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Produce a message digest (a hash block) using the input data. + * + * @details + * This function generates a message digest adhering to the given inputs. + * For instance, if the algorithm is chosen to be SHA-256, it will generate + * a 32 bytes message digest computed based on the input message. + * This function supports SHA-1, SHA-256 and SHA-512 algorithms. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] hash_type + * Which hashing algorithm to use. + * + * @param[in] message + * Pointer to the message buffer to compute the hash/digest from. + * + * @param[in] message_size + * Number of bytes in message. + * + * @param[out] digest + * Pointer to block of memory to store the final digest. + * + * @param[in] digest_len + * The length of the message digest (hash), must be at least the size of the + * corresponding hash type. + * + * @return Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash(sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type, + const uint8_t *message, + unsigned int message_size, + uint8_t* digest, + size_t digest_len); + +/***************************************************************************//** + * @brief + * Prepare a SHA1 hash streaming command context object. + * + * @details + * Prepare a SHA1 hash streaming command context object to be used in + * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and + * sl_se_hash_multipart_finish(). + * + * @param[in] sha1_ctx + * Pointer to a SHA1 streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_sha1_multipart_starts(sl_se_sha1_multipart_context_t *sha1_ctx, + sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Prepare a SHA224 hash streaming command context object. + * + * @details + * Prepare a SHA224 hash streaming command context object to be used in + * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and + * sl_se_hash_multipart_finish(). + * + * @param[in] sha224_ctx + * Pointer to a SHA224 streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_sha224_multipart_starts(sl_se_sha224_multipart_context_t *sha224_ctx, + sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Prepare a SHA256 hash streaming command context object. + * + * @details + * Prepare a SHA256 hash streaming command context object to be used in + * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and + * sl_se_hash_multipart_finish(). + * + * @param[in] sha256_ctx + * Pointer to a SHA256 streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_sha256_multipart_starts(sl_se_sha256_multipart_context_t *sha256_ctx, + sl_se_command_context_t *cmd_ctx); + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief + * Prepare a SHA384 streaming command context object. + * + * @details + * Prepare a SHA384 hash streaming command context object to be used in + * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and + * sl_se_hash_multipart_finish(). + * + * @param[in] sha384_ctx + * Pointer to a SHA384 streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_sha384_multipart_starts(sl_se_sha384_multipart_context_t *sha384_ctx, + sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Prepare a SHA512 streaming command context object. + * + * @details + * Prepare a SHA512 hash streaming command context object to be used in + * subsequent calls to hash streaming functions sl_se_hash_multipart_update() and + * sl_se_hash_multipart_finish(). + * + * @param[in] sha512_ctx + * Pointer to a SHA512 streaming context object. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_sha512_multipart_starts(sl_se_sha512_multipart_context_t *sha512_ctx, + sl_se_command_context_t *cmd_ctx); + +#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +/***************************************************************************//** + * @brief + * Prepare a hash streaming command context object. + * + * @details + * Prepare a hash (message digest) streaming command context object to be + * used in subsequent calls to hash streaming functions sl_se_hash_multipart_update() + * and sl_se_hash_multipart_finish(). + * + * @param[in] hash_type_ctx + * Pointer to a hash streaming context object specific to the hash type + * specified by @p hash_type. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] hash_type + * Type of hash algoritm + * + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_starts(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type); + +/***************************************************************************//** + * @brief + * Feeds an input buffer into an ongoing hash computation. + * + * This function is called between @ref sl_se_hash_multipart_starts() and + * @ref sl_se_hash_multipart_finish(). + * This function can be called repeatedly. + * + * @param[in] hash_type_ctx + * Pointer to a hash streaming context object specific to the hash type + * specified by @p hash_type. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] input + * Buffer holding the input data, must be at least @p ilen bytes wide. + * + * @param[in] input_len + * The length of the input data in bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_update(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + const uint8_t *input, + size_t input_len); + +/***************************************************************************//** + * @brief + * Finish a hash streaming operation and return the resulting hash digest. + * + * This function is called after sl_se_hash_multipart_update(). + * + * @param[in] hash_type_ctx + * Pointer to a hash streaming context object specific to the hash type + * specified by @p hash_type. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] digest_out + * Buffer for holding the message digest (hash), must be at least the size + * of the corresponding message digest type. + * + * @param[in] digest_len + * The length of the message digest (hash), must be at least the size of the + * corresponding hash type. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_finish(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + uint8_t *digest_out, + size_t digest_len); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_hash) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_HASH_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_internal_keys.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_internal_keys.h index 7aee05a..9533bd5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_internal_keys.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_internal_keys.h @@ -1,143 +1,143 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager Internal key defines - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_INTERNAL_KEYS -#define SL_SE_MANAGER_INTERNAL_KEYS - -#include "sli_se_manager_features.h" -#include "sl_se_manager_defines.h" - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -#if defined(SLI_SE_MAJOR_VERSION_ONE) -/// Key descriptor for internal application attestation key - #define SL_SE_APPLICATION_ATTESTATION_KEY \ - { \ - .type = SL_SE_KEY_TYPE_ECC_P256, \ - .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE \ - | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ - | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ - | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY, \ - }, \ - }, \ - } -#else -/// Key descriptor for internal application attestation key - #define SL_SE_APPLICATION_ATTESTATION_KEY \ - { \ - .type = SL_SE_KEY_TYPE_ECC_P256, \ - .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ - | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ - | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY, \ - }, \ - }, \ - } -#endif - -/// Key descriptor for internal SE attestation key -/// @note: Can only be used to get the public part - #define SL_SE_SYSTEM_ATTESTATION_KEY \ - { \ - .type = SL_SE_KEY_TYPE_ECC_P256, \ - .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE \ - | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ - | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ - | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_SE_ATTESTATION_KEY, \ - }, \ - }, \ - } - -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - -/// Key descriptor for secure boot public key -#define SL_SE_APPLICATION_SECURE_BOOT_KEY \ - { \ - .type = SL_SE_KEY_TYPE_ECC_P256, \ - .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \ - | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY, \ - }, \ - }, \ - } - -/// Key descriptor for secure debug public key -#define SL_SE_APPLICATION_SECURE_DEBUG_KEY \ - { \ - .type = SL_SE_KEY_TYPE_ECC_P256, \ - .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \ - | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY, \ - }, \ - }, \ - } - -/// Key descriptor for application AES-128 key -#define SL_SE_APPLICATION_AES_128_KEY \ - { \ - .type = SL_SE_KEY_TYPE_AES_128, \ - .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY, \ - }, \ - }, \ - } - -/// Key descriptor for TrustZone root key -#define SL_SE_TRUSTZONE_ROOT_KEY \ - { \ - .type = SL_SE_KEY_TYPE_AES_256, \ - .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED, \ - .storage = { \ - .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ - .location = { \ - .slot = SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY, \ - }, \ - }, \ - } -#endif // SL_SE_MANAGER_INTERNAL_KEYS +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager Internal key defines + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_INTERNAL_KEYS +#define SL_SE_MANAGER_INTERNAL_KEYS + +#include "sli_se_manager_features.h" +#include "sl_se_manager_defines.h" + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +#if defined(SLI_SE_MAJOR_VERSION_ONE) +/// Key descriptor for internal application attestation key + #define SL_SE_APPLICATION_ATTESTATION_KEY \ + { \ + .type = SL_SE_KEY_TYPE_ECC_P256, \ + .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE \ + | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ + | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ + | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY, \ + }, \ + }, \ + } +#else +/// Key descriptor for internal application attestation key + #define SL_SE_APPLICATION_ATTESTATION_KEY \ + { \ + .type = SL_SE_KEY_TYPE_ECC_P256, \ + .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ + | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ + | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY, \ + }, \ + }, \ + } +#endif + +/// Key descriptor for internal SE attestation key +/// @note: Can only be used to get the public part + #define SL_SE_SYSTEM_ATTESTATION_KEY \ + { \ + .type = SL_SE_KEY_TYPE_ECC_P256, \ + .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE \ + | SL_SE_KEY_FLAG_IS_DEVICE_GENERATED \ + | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY \ + | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_SE_ATTESTATION_KEY, \ + }, \ + }, \ + } + +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + +/// Key descriptor for secure boot public key +#define SL_SE_APPLICATION_SECURE_BOOT_KEY \ + { \ + .type = SL_SE_KEY_TYPE_ECC_P256, \ + .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \ + | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY, \ + }, \ + }, \ + } + +/// Key descriptor for secure debug public key +#define SL_SE_APPLICATION_SECURE_DEBUG_KEY \ + { \ + .type = SL_SE_KEY_TYPE_ECC_P256, \ + .flags = SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY \ + | SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY, \ + }, \ + }, \ + } + +/// Key descriptor for application AES-128 key +#define SL_SE_APPLICATION_AES_128_KEY \ + { \ + .type = SL_SE_KEY_TYPE_AES_128, \ + .flags = SL_SE_KEY_FLAG_NON_EXPORTABLE, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY, \ + }, \ + }, \ + } + +/// Key descriptor for TrustZone root key +#define SL_SE_TRUSTZONE_ROOT_KEY \ + { \ + .type = SL_SE_KEY_TYPE_AES_256, \ + .flags = SL_SE_KEY_FLAG_IS_DEVICE_GENERATED, \ + .storage = { \ + .method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE, \ + .location = { \ + .slot = SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY, \ + }, \ + }, \ + } +#endif // SL_SE_MANAGER_INTERNAL_KEYS diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_derivation.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_derivation.h index 16d8f45..6c4c35e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_derivation.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_derivation.h @@ -1,436 +1,436 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_KEY_DERIVATION_H -#define SL_SE_MANAGER_KEY_DERIVATION_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_key_derivation Key derivation - * - * @brief - * API for key derivation and key agreement (ECDH, EC J-PAKE, HKDF, PBKDF2). - * - * @details - * Contains key derivation functions (HKDF, PBKDF2) and key agreement - * functions (ECDH, ECJPAKE). - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -// ------------------------------- -// Elliptic-curve Diffie–Hellman - -/***************************************************************************//** - * @brief - * This function computes the shared secret with Elliptic Curve Diffie Hellman - * (ECDH) algorithm - * - * @details - * Performs Elliptic Curve Diffie Hellman shared secret computation. - * - * @note - * P-521 Elliptic Curve based Elliptic Curve Diffie Hellman (ECDH) expects - * a 544 bits (68 bytes) buffer for storing private keys, and - * a 1088 bits (136 bytes) buffer for storing public keys and shared secret. - * The first 23 bits of d, Qx, Qy and shared secret are padding bits to comply - * word-aligned addressing. The padding bits are ignored in the computation. - * - * This function does not implement the value-checking of the shared secret - * as described in RFC7748 when using Montgomery keys. - * - * In case of using custom domain curves, \p key_in_priv defines the domain - * parameters. Moreover, \p key_in_pub should always contain a public key. - * If key_in_pub contains a private key, sl_se_export_public_key() can be - * used to export the public key. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_in_priv - * Our private key. - * - * @param[in] key_in_pub - * Their public key. - * - * @param[out] key_out - * Shared secret key. Montgomery curve result is one single coordinate. - * Other curve types result in one pair of coordinate. - * - * @return - * SL_STATUS_INVALID_KEY if \p key_in_pub does not contain a public key - * when using custom domain curves, otherwise an appropriate error code - * (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecdh_compute_shared_secret(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in_priv, - const sl_se_key_descriptor_t *key_in_pub, - const sl_se_key_descriptor_t *key_out); - -// ------------------------------- -// EC J-PAKE - -/***************************************************************************//** - * @brief - * Check if an EC J-PAKE context is ready for use. - * - * @param[in] ctx - * The EC J-PAKE context to check. This must be initialized. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_check(const sl_se_ecjpake_context_t *ctx); - -/***************************************************************************//** - * @brief - * Derive the shared secret (TLS: Pre-Master Secret). - * - * @param[in] ctx - * The EC J-PAKE context to use. This must be initialized, set up and have - * performed both round one and two. - * - * @param[out] buf - * The buffer to write the derived secret to. This must be a writable buffer - * of length @p len bytes. - * - * @param[in] len - * The length of @p buf in bytes. - * - * @param[out] olen - * The address at which to store the total number of bytes written to @p buf. - * This must not be @c NULL. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_derive_secret(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen); - -/***************************************************************************//** - * @brief - * This clears an EC J-PAKE context and frees any embedded data structure. - * - * @param[in] ctx - * The EC J-PAKE context to free. This may be @c NULL, in which case this - * function does nothing. If it is not @c NULL, it must point to an - * initialized EC J-PAKE context. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_free(sl_se_ecjpake_context_t *ctx); - -/***************************************************************************//** - * @brief - * Initialize an EC J-PAKE context. - * - * @param[in] ctx - * The EC J-PAKE context to initialize. This must not be @c NULL. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_init(sl_se_ecjpake_context_t *ctx, - sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Read and process the first round message (TLS: contents of the - * Client/ServerHello extension, excluding extension type and length bytes). - * - * @param[in] ctx - * The EC J-PAKE context to use. This must be initialized and set up. - * - * @param[in] buf - * The buffer holding the first round message. This must be a readable buffer - * of length @p len bytes. - * - * @param[in] len - * The length in bytes of @p buf. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_read_round_one(sl_se_ecjpake_context_t *ctx, - const unsigned char *buf, - size_t len); - -/***************************************************************************//** - * @brief - * Read and process the second round message (TLS: contents of the - * Client/ServerKeyExchange). - * - * @param[in] ctx - * The EC J-PAKE context to use. This must be initialized and set up and already - * have performed round one. - * - * @param[in] buf - * The buffer holding the second round message. This must be a readable buffer - * of length @p len bytes. - * - * @param[in] len - * The length in bytes of @p buf. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_read_round_two(sl_se_ecjpake_context_t *ctx, - const unsigned char *buf, - size_t len); - -/***************************************************************************//** - * @brief - * Set up an EC J-PAKE context for use. - * - * @note - * Currently the only values for hash/curve allowed by the standard are - * @ref SL_SE_HASH_SHA256 / @ref SL_SE_KEY_TYPE_ECC_P256. - * - * @param[in] ctx - * The EC J-PAKE context to set up. This must be initialized. - * - * @param[in] role - * The role of the caller. This must be either @ref SL_SE_ECJPAKE_CLIENT or - * @ref SL_SE_ECJPAKE_SERVER. - * - * @param[in] hash - * The identifier of the hash function to use, for example - * @ref SL_SE_HASH_SHA256. - * - * @param[in] curve - * The identifier of the elliptic curve to use, for example - * @ref SL_SE_KEY_TYPE_ECC_P256. - * - * @param[in] secret - * The pre-shared secret (passphrase). This must be a readable buffer of - * length @p len bytes. It need only be valid for the duration of this call. - * - * @param[in] len - * The length of the pre-shared secret @p secret. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_setup(sl_se_ecjpake_context_t *ctx, - sl_se_ecjpake_role_t role, - sl_se_hash_type_t hash, - uint32_t curve, - const unsigned char *secret, - size_t len); - -/***************************************************************************//** - * @brief - * Generate and write the first round message (TLS: contents of the - * Client/ServerHello extension, excluding extension type and length bytes). - * - * @param[in] ctx - * The EC J-PAKE context to use. This must be initialized and set up. - * - * @param[out] buf - * The buffer to write the contents to. This must be a writable buffer of - * length @p len bytes. - * - * @param[in] len - * The length of @p buf in bytes. - * - * @param[out] olen - * The address at which to store the total number of bytes written to @p buf. - * This must not be @c NULL. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_write_round_one(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen); - -/***************************************************************************//** - * @brief - * Generate and write the second round message (TLS: contents of the - * Client/ServerKeyExchange). - * - * @param[in] ctx - * The EC J-PAKE context to use. This must be initialized, set up, and already - * have performed round one. - * - * @param[out] buf - * The buffer to write the round two contents to. This must be a writable - * buffer of length @p len bytes. - * - * @param[in] len - * The size of @p buf in bytes. - * - * @param[out] olen - * The address at which to store the total number of bytes written to @p buf. - * This must not be @c NULL. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecjpake_write_round_two(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen); - -// ------------------------------- -// Key derivation functions - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * @brief - * Derive a pseudorandom key from the input key material using HKDF. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] in_key - * Pointer to the input key material. - * - * @param[in] hash - * Which hashing algorithm to use. - * - * @param[in] salt - * An optional salt value (a non-secret random value). - * - * @param[in] salt_len - * The length of the salt. - * - * @param[in] info - * An optional context and application specific information string. - * - * @param[in] info_len - * The length of info. - * - * @param[in,out] out_key - * Pointer to the generated key material. The length member of out_key is - * used to request a given length of the generated key. - * - * @return - * SL_STATUS_OK if the signature is successfully verified, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_derive_key_hkdf(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *in_key, - sl_se_hash_type_t hash, - const unsigned char *salt, - size_t salt_len, - const unsigned char *info, - size_t info_len, - sl_se_key_descriptor_t *out_key); - -/***************************************************************************//** - * @brief - * Derive a pseudorandom key from the input key material using PBKDF2. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] in_key - * Pointer to the input key material. - * - * @param[in] prf - * The underlying psuedorandom function (PRF) to use in the algorithm. The - * most common choice of HMAC-SHA-{1, 224, 256, 384, 512} is supported on all - * Series-2 devices (with Vault High Security). Newer chips, EFR32xG23 and - * later, also support usage of AES-CMAC-PRF-128. - * - * @param[in] salt - * An optional salt value (a non-secret random value). - * - * @param[in] salt_len - * The length of the salt. - * - * @param[in] iterations - * The number of iterations to use. Up to 16384 iterations is supported. - * - * @param[in,out] out_key - * Pointer to the generated key material. The length member of out_key is - * used to request a given length of the generated key. - * - * @return - * SL_STATUS_OK if the signature is successfully verified, otherwise an - * appropriate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_derive_key_pbkdf2(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *in_key, - sl_se_pbkdf2_prf_type_t prf, - const unsigned char *salt, - size_t salt_len, - uint32_t iterations, - sl_se_key_descriptor_t *out_key); - -#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_key_derivation) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_KEY_DERIVATION_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_KEY_DERIVATION_H +#define SL_SE_MANAGER_KEY_DERIVATION_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_key_derivation Key derivation + * + * @brief + * API for key derivation and key agreement (ECDH, EC J-PAKE, HKDF, PBKDF2). + * + * @details + * Contains key derivation functions (HKDF, PBKDF2) and key agreement + * functions (ECDH, ECJPAKE). + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +// ------------------------------- +// Elliptic-curve Diffie–Hellman + +/***************************************************************************//** + * @brief + * This function computes the shared secret with Elliptic Curve Diffie Hellman + * (ECDH) algorithm + * + * @details + * Performs Elliptic Curve Diffie Hellman shared secret computation. + * + * @note + * P-521 Elliptic Curve based Elliptic Curve Diffie Hellman (ECDH) expects + * a 544 bits (68 bytes) buffer for storing private keys, and + * a 1088 bits (136 bytes) buffer for storing public keys and shared secret. + * The first 23 bits of d, Qx, Qy and shared secret are padding bits to comply + * word-aligned addressing. The padding bits are ignored in the computation. + * + * This function does not implement the value-checking of the shared secret + * as described in RFC7748 when using Montgomery keys. + * + * In case of using custom domain curves, \p key_in_priv defines the domain + * parameters. Moreover, \p key_in_pub should always contain a public key. + * If key_in_pub contains a private key, sl_se_export_public_key() can be + * used to export the public key. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_in_priv + * Our private key. + * + * @param[in] key_in_pub + * Their public key. + * + * @param[out] key_out + * Shared secret key. Montgomery curve result is one single coordinate. + * Other curve types result in one pair of coordinate. + * + * @return + * SL_STATUS_INVALID_KEY if \p key_in_pub does not contain a public key + * when using custom domain curves, otherwise an appropriate error code + * (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecdh_compute_shared_secret(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in_priv, + const sl_se_key_descriptor_t *key_in_pub, + const sl_se_key_descriptor_t *key_out); + +// ------------------------------- +// EC J-PAKE + +/***************************************************************************//** + * @brief + * Check if an EC J-PAKE context is ready for use. + * + * @param[in] ctx + * The EC J-PAKE context to check. This must be initialized. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_check(const sl_se_ecjpake_context_t *ctx); + +/***************************************************************************//** + * @brief + * Derive the shared secret (TLS: Pre-Master Secret). + * + * @param[in] ctx + * The EC J-PAKE context to use. This must be initialized, set up and have + * performed both round one and two. + * + * @param[out] buf + * The buffer to write the derived secret to. This must be a writable buffer + * of length @p len bytes. + * + * @param[in] len + * The length of @p buf in bytes. + * + * @param[out] olen + * The address at which to store the total number of bytes written to @p buf. + * This must not be @c NULL. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_derive_secret(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen); + +/***************************************************************************//** + * @brief + * This clears an EC J-PAKE context and frees any embedded data structure. + * + * @param[in] ctx + * The EC J-PAKE context to free. This may be @c NULL, in which case this + * function does nothing. If it is not @c NULL, it must point to an + * initialized EC J-PAKE context. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_free(sl_se_ecjpake_context_t *ctx); + +/***************************************************************************//** + * @brief + * Initialize an EC J-PAKE context. + * + * @param[in] ctx + * The EC J-PAKE context to initialize. This must not be @c NULL. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_init(sl_se_ecjpake_context_t *ctx, + sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Read and process the first round message (TLS: contents of the + * Client/ServerHello extension, excluding extension type and length bytes). + * + * @param[in] ctx + * The EC J-PAKE context to use. This must be initialized and set up. + * + * @param[in] buf + * The buffer holding the first round message. This must be a readable buffer + * of length @p len bytes. + * + * @param[in] len + * The length in bytes of @p buf. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_read_round_one(sl_se_ecjpake_context_t *ctx, + const unsigned char *buf, + size_t len); + +/***************************************************************************//** + * @brief + * Read and process the second round message (TLS: contents of the + * Client/ServerKeyExchange). + * + * @param[in] ctx + * The EC J-PAKE context to use. This must be initialized and set up and already + * have performed round one. + * + * @param[in] buf + * The buffer holding the second round message. This must be a readable buffer + * of length @p len bytes. + * + * @param[in] len + * The length in bytes of @p buf. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_read_round_two(sl_se_ecjpake_context_t *ctx, + const unsigned char *buf, + size_t len); + +/***************************************************************************//** + * @brief + * Set up an EC J-PAKE context for use. + * + * @note + * Currently the only values for hash/curve allowed by the standard are + * @ref SL_SE_HASH_SHA256 / @ref SL_SE_KEY_TYPE_ECC_P256. + * + * @param[in] ctx + * The EC J-PAKE context to set up. This must be initialized. + * + * @param[in] role + * The role of the caller. This must be either @ref SL_SE_ECJPAKE_CLIENT or + * @ref SL_SE_ECJPAKE_SERVER. + * + * @param[in] hash + * The identifier of the hash function to use, for example + * @ref SL_SE_HASH_SHA256. + * + * @param[in] curve + * The identifier of the elliptic curve to use, for example + * @ref SL_SE_KEY_TYPE_ECC_P256. + * + * @param[in] secret + * The pre-shared secret (passphrase). This must be a readable buffer of + * length @p len bytes. It need only be valid for the duration of this call. + * + * @param[in] len + * The length of the pre-shared secret @p secret. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_setup(sl_se_ecjpake_context_t *ctx, + sl_se_ecjpake_role_t role, + sl_se_hash_type_t hash, + uint32_t curve, + const unsigned char *secret, + size_t len); + +/***************************************************************************//** + * @brief + * Generate and write the first round message (TLS: contents of the + * Client/ServerHello extension, excluding extension type and length bytes). + * + * @param[in] ctx + * The EC J-PAKE context to use. This must be initialized and set up. + * + * @param[out] buf + * The buffer to write the contents to. This must be a writable buffer of + * length @p len bytes. + * + * @param[in] len + * The length of @p buf in bytes. + * + * @param[out] olen + * The address at which to store the total number of bytes written to @p buf. + * This must not be @c NULL. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_write_round_one(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen); + +/***************************************************************************//** + * @brief + * Generate and write the second round message (TLS: contents of the + * Client/ServerKeyExchange). + * + * @param[in] ctx + * The EC J-PAKE context to use. This must be initialized, set up, and already + * have performed round one. + * + * @param[out] buf + * The buffer to write the round two contents to. This must be a writable + * buffer of length @p len bytes. + * + * @param[in] len + * The size of @p buf in bytes. + * + * @param[out] olen + * The address at which to store the total number of bytes written to @p buf. + * This must not be @c NULL. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecjpake_write_round_two(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen); + +// ------------------------------- +// Key derivation functions + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief + * Derive a pseudorandom key from the input key material using HKDF. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] in_key + * Pointer to the input key material. + * + * @param[in] hash + * Which hashing algorithm to use. + * + * @param[in] salt + * An optional salt value (a non-secret random value). + * + * @param[in] salt_len + * The length of the salt. + * + * @param[in] info + * An optional context and application specific information string. + * + * @param[in] info_len + * The length of info. + * + * @param[in,out] out_key + * Pointer to the generated key material. The length member of out_key is + * used to request a given length of the generated key. + * + * @return + * SL_STATUS_OK if the signature is successfully verified, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_derive_key_hkdf(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *in_key, + sl_se_hash_type_t hash, + const unsigned char *salt, + size_t salt_len, + const unsigned char *info, + size_t info_len, + sl_se_key_descriptor_t *out_key); + +/***************************************************************************//** + * @brief + * Derive a pseudorandom key from the input key material using PBKDF2. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] in_key + * Pointer to the input key material. + * + * @param[in] prf + * The underlying psuedorandom function (PRF) to use in the algorithm. The + * most common choice of HMAC-SHA-{1, 224, 256, 384, 512} is supported on all + * Series-2 devices (with Vault High Security). Newer chips, EFR32xG23 and + * later, also support usage of AES-CMAC-PRF-128. + * + * @param[in] salt + * An optional salt value (a non-secret random value). + * + * @param[in] salt_len + * The length of the salt. + * + * @param[in] iterations + * The number of iterations to use. Up to 16384 iterations is supported. + * + * @param[in,out] out_key + * Pointer to the generated key material. The length member of out_key is + * used to request a given length of the generated key. + * + * @return + * SL_STATUS_OK if the signature is successfully verified, otherwise an + * appropriate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_derive_key_pbkdf2(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *in_key, + sl_se_pbkdf2_prf_type_t prf, + const unsigned char *salt, + size_t salt_len, + uint32_t iterations, + sl_se_key_descriptor_t *out_key); + +#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_key_derivation) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_KEY_DERIVATION_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_handling.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_handling.h index ecda48c..05acd9e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_handling.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_key_handling.h @@ -1,258 +1,258 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager key handling. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_KEY_HANDLING_H -#define SL_SE_MANAGER_KEY_HANDLING_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -#include "sl_se_manager_types.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * \addtogroup sl_se_manager_key_handling Key handling - * - * \brief Secure Engine key handling API. - * - * \details - * API for using cryptographic keys with the SE. Contains functionality to - * generate, import and export keys to and from protected types like wrapped - * or volatile keys. - * - * \{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Validate key descriptor. - * - * @details - * Takes a key descriptor and checks if all required properties have been set - * for the specific key type. - * - * @param[in] key - * The key to validate. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_validate_key(const sl_se_key_descriptor_t *key); - -/***************************************************************************//** - * @brief - * Generate a random key adhering to the given key descriptor - * - * @details - * The SE takes a key descriptor and generates a key with the given properties - * in the location specified by the descriptor. - * - * If the key size is not aligned to a multiple of words the key - * representation is padded in front of the key. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_out - * Description of the key to generate. Sets key parameters and describes the - * storage location for the key. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_generate_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_out); - -/***************************************************************************//** - * @brief - * Import a key using the SE - * - * @details - * Protect a key using the SE. Import a plaintext key and store it either in a - * volatile slot or as a wrapped key. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_in - * A plaintext key. - * - * @param[in] key_out - * Either a volatile or a wrapped key with similar properties as key_in. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_import_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out); - -/***************************************************************************//** - * @brief - * Export a volatile or wrapped key back to plaintext - * - * @details - * Attempt to have the SE export a volatile or wrapped key back to plaintext - * if allowed. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_in - * Either a volatile or a wrapped key with similar properties as key_out. - * - * @param[in] key_out - * The exported key in plaintext. - * - * @return - * Status code, @ref sl_status.h. - * SL_STATUS_INVALID_PARAMETER if key does not exist. - ******************************************************************************/ -sl_status_t sl_se_export_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out); - -/***************************************************************************//** - * @brief - * Transfer a volatile or wrapped key to another protected storage. - * - * @details - * Attempt to have the SE transfer a volatile or wrapped key if allowed. - * - * @note - * The key stored in the source protected storage will not be deleted. - * - * Transferring a key between the same volatile slot is not allowed. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_in - * Either a volatile or a wrapped key with similar properties as key_out. - * - * @param[in] key_out - * Either a volatile or a wrapped key with similar properties as key_in. - * - * @return - * Status code, @ref sl_status.h. - * SL_STATUS_INVALID_PARAMETER if key does not exist. - ******************************************************************************/ -sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out); - -/***************************************************************************//** - * @brief - * Export the public part of an ECC keypair - * - * @details - * The output key must be specified to only contain a public key. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_in - * An asymmetric key with either a private or public part. - * - * @param[out] key_out - * Describes output key parameters. Should only be set to contain the public - * part of the key. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_export_public_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out); - -/***************************************************************************//** - * @brief - * Delete a key from a volatile SE storage slot - * - * @details - * The given key will be removed from the SE. The key descriptor is not - * modified and can be used to generate a new key without any updates. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Key to delete. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_delete_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key); - -/***************************************************************************//** - * @brief - * Returns the required storage size for the given key - * - * @details - * Finds the total storage size required for a given key. This includes - * storage for the public and private part of asymmetric keys, as well as - * overhead for wrapping keys. - * - * @param[in] key - * The sl_se_key_descriptor_t to find the required storage size for. - * - * @param[out] storage_size - * The required storage size in bytes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_get_storage_size(const sl_se_key_descriptor_t *key, - uint32_t *storage_size); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup sl_se_key) */ -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_KEY_HANDLING_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager key handling. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_KEY_HANDLING_H +#define SL_SE_MANAGER_KEY_HANDLING_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +#include "sl_se_manager_types.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * \addtogroup sl_se_manager_key_handling Key handling + * + * \brief Secure Engine key handling API. + * + * \details + * API for using cryptographic keys with the SE. Contains functionality to + * generate, import and export keys to and from protected types like wrapped + * or volatile keys. + * + * \{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Validate key descriptor. + * + * @details + * Takes a key descriptor and checks if all required properties have been set + * for the specific key type. + * + * @param[in] key + * The key to validate. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_validate_key(const sl_se_key_descriptor_t *key); + +/***************************************************************************//** + * @brief + * Generate a random key adhering to the given key descriptor + * + * @details + * The SE takes a key descriptor and generates a key with the given properties + * in the location specified by the descriptor. + * + * If the key size is not aligned to a multiple of words the key + * representation is padded in front of the key. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_out + * Description of the key to generate. Sets key parameters and describes the + * storage location for the key. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_generate_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_out); + +/***************************************************************************//** + * @brief + * Import a key using the SE + * + * @details + * Protect a key using the SE. Import a plaintext key and store it either in a + * volatile slot or as a wrapped key. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_in + * A plaintext key. + * + * @param[in] key_out + * Either a volatile or a wrapped key with similar properties as key_in. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_import_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out); + +/***************************************************************************//** + * @brief + * Export a volatile or wrapped key back to plaintext + * + * @details + * Attempt to have the SE export a volatile or wrapped key back to plaintext + * if allowed. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_in + * Either a volatile or a wrapped key with similar properties as key_out. + * + * @param[in] key_out + * The exported key in plaintext. + * + * @return + * Status code, @ref sl_status.h. + * SL_STATUS_INVALID_PARAMETER if key does not exist. + ******************************************************************************/ +sl_status_t sl_se_export_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out); + +/***************************************************************************//** + * @brief + * Transfer a volatile or wrapped key to another protected storage. + * + * @details + * Attempt to have the SE transfer a volatile or wrapped key if allowed. + * + * @note + * The key stored in the source protected storage will not be deleted. + * + * Transferring a key between the same volatile slot is not allowed. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_in + * Either a volatile or a wrapped key with similar properties as key_out. + * + * @param[in] key_out + * Either a volatile or a wrapped key with similar properties as key_in. + * + * @return + * Status code, @ref sl_status.h. + * SL_STATUS_INVALID_PARAMETER if key does not exist. + ******************************************************************************/ +sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out); + +/***************************************************************************//** + * @brief + * Export the public part of an ECC keypair + * + * @details + * The output key must be specified to only contain a public key. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_in + * An asymmetric key with either a private or public part. + * + * @param[out] key_out + * Describes output key parameters. Should only be set to contain the public + * part of the key. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_export_public_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out); + +/***************************************************************************//** + * @brief + * Delete a key from a volatile SE storage slot + * + * @details + * The given key will be removed from the SE. The key descriptor is not + * modified and can be used to generate a new key without any updates. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Key to delete. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_delete_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key); + +/***************************************************************************//** + * @brief + * Returns the required storage size for the given key + * + * @details + * Finds the total storage size required for a given key. This includes + * storage for the public and private part of asymmetric keys, as well as + * overhead for wrapping keys. + * + * @param[in] key + * The sl_se_key_descriptor_t to find the required storage size for. + * + * @param[out] storage_size + * The required storage size in bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_get_storage_size(const sl_se_key_descriptor_t *key, + uint32_t *storage_size); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup sl_se_key) */ +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_KEY_HANDLING_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_signature.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_signature.h index 67149a9..adaf32a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_signature.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_signature.h @@ -1,185 +1,185 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_SIGNATURE_H -#define SL_SE_MANAGER_SIGNATURE_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_signature Signature - * - * @brief - * Digital Signature Algorithms (ECDSA, EdDSA). - * - * @details - * API for using digital signatures with the SE. - * - * @{ - ******************************************************************************/ - -#include "sl_se_manager_key_handling.h" -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * This function computes Elliptic-Curve Cryptography (ECC) digital signatures - * of a message. - * - * @note - * Edwards-curve Digital Signature Algorithm (EdDSA) generates a message digest - * using the input message for computing signatures. The input parameters - * \p hash_alg and \p hashed_message do not apply for EdDSA. - * - * P-521 Elliptic Curve for Elliptic Curve Digital Signature Algorithm (ECDSA) - * expects a 544 bits (68 bytes) buffer for storing private keys, - * and a 1088 bits (136 bytes) buffer for storing public keys and signatures. - * The first 23 bits of d, Qx, Qy, R and S are padding bits to comply - * word-aligned addressing. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] hash_alg - * Which hashing algorithm to use. Ignored for EdDSA keys, since EdDSA always - * uses SHA-512 for Ed25519 and SHA-3 for Ed448. - * - * @param[in] hashed_message - * The input message is a message digest. Ignored for EdDSA keys, and treated - * as false. - * - * @param[in] message - * The message to be used to compute the signature. - * - * @param[in] message_len - * The length of message. - * - * @param[out] signature - * The computed signature. - * - * @param[in] signature_len - * The length of the computed signature. - * - * @return - * SL_STATUS_OK when the command was executed successfully, otherwise an - * appropiate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecc_sign(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_alg, - bool hashed_message, - const unsigned char *message, - size_t message_len, - unsigned char *signature, - size_t signature_len); - -/***************************************************************************//** - * @brief - * This function verifies Elliptic-Curve Cryptography (ECC) digital signatures - * of a message. - * - * @note - * The input parameters \p hash_alg and \p hashed_message do not apply for - * Edwards-curve Digital Signature Algorithm (EdDSA). - * - * P-521 Elliptic Curve for Elliptic Curve Digital Signature Algorithm (ECDSA) - * expects a 544 bits (68 bytes) buffer for storing private keys, - * and a 1088 bits (136 bytes) buffer for storing public keys and signatures. - * The first 23 bits of d, Qx, Qy, R and S are padding bits to comply - * word-aligned addressing. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure. - * - * @param[in] hash_alg - * Which hashing algorithm to use. Ignored for EdDSA keys, since EdDSA always - * uses SHA-512 for Ed25519 and SHA-3 for Ed448. - * - * @param[in] hashed_message - * The input message is a message digest. Ignored for EdDSA keys, and treated - * as false. - * - * @param[in] message - * The message to be used to compute signatures. - * - * @param[in] message_len - * The length of message. - * - * @param[in] signature - * The signature to be verified. - * - * @param[in] signature_len - * The length of signature. - * - * @return - * SL_STATUS_OK if the signature is successfully verified, otherwise an - * appropiate error code (@ref sl_status.h). - ******************************************************************************/ -sl_status_t sl_se_ecc_verify(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_alg, - bool hashed_message, - const unsigned char *message, - size_t message_len, - const unsigned char *signature, - size_t signature_len); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_signature) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_SIGNATURE_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_SIGNATURE_H +#define SL_SE_MANAGER_SIGNATURE_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_signature Signature + * + * @brief + * Digital Signature Algorithms (ECDSA, EdDSA). + * + * @details + * API for using digital signatures with the SE. + * + * @{ + ******************************************************************************/ + +#include "sl_se_manager_key_handling.h" +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * This function computes Elliptic-Curve Cryptography (ECC) digital signatures + * of a message. + * + * @note + * Edwards-curve Digital Signature Algorithm (EdDSA) generates a message digest + * using the input message for computing signatures. The input parameters + * \p hash_alg and \p hashed_message do not apply for EdDSA. + * + * P-521 Elliptic Curve for Elliptic Curve Digital Signature Algorithm (ECDSA) + * expects a 544 bits (68 bytes) buffer for storing private keys, + * and a 1088 bits (136 bytes) buffer for storing public keys and signatures. + * The first 23 bits of d, Qx, Qy, R and S are padding bits to comply + * word-aligned addressing. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] hash_alg + * Which hashing algorithm to use. Ignored for EdDSA keys, since EdDSA always + * uses SHA-512 for Ed25519 and SHA-3 for Ed448. + * + * @param[in] hashed_message + * The input message is a message digest. Ignored for EdDSA keys, and treated + * as false. + * + * @param[in] message + * The message to be used to compute the signature. + * + * @param[in] message_len + * The length of message. + * + * @param[out] signature + * The computed signature. + * + * @param[in] signature_len + * The length of the computed signature. + * + * @return + * SL_STATUS_OK when the command was executed successfully, otherwise an + * appropiate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecc_sign(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_alg, + bool hashed_message, + const unsigned char *message, + size_t message_len, + unsigned char *signature, + size_t signature_len); + +/***************************************************************************//** + * @brief + * This function verifies Elliptic-Curve Cryptography (ECC) digital signatures + * of a message. + * + * @note + * The input parameters \p hash_alg and \p hashed_message do not apply for + * Edwards-curve Digital Signature Algorithm (EdDSA). + * + * P-521 Elliptic Curve for Elliptic Curve Digital Signature Algorithm (ECDSA) + * expects a 544 bits (68 bytes) buffer for storing private keys, + * and a 1088 bits (136 bytes) buffer for storing public keys and signatures. + * The first 23 bits of d, Qx, Qy, R and S are padding bits to comply + * word-aligned addressing. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure. + * + * @param[in] hash_alg + * Which hashing algorithm to use. Ignored for EdDSA keys, since EdDSA always + * uses SHA-512 for Ed25519 and SHA-3 for Ed448. + * + * @param[in] hashed_message + * The input message is a message digest. Ignored for EdDSA keys, and treated + * as false. + * + * @param[in] message + * The message to be used to compute signatures. + * + * @param[in] message_len + * The length of message. + * + * @param[in] signature + * The signature to be verified. + * + * @param[in] signature_len + * The length of signature. + * + * @return + * SL_STATUS_OK if the signature is successfully verified, otherwise an + * appropiate error code (@ref sl_status.h). + ******************************************************************************/ +sl_status_t sl_se_ecc_verify(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_alg, + bool hashed_message, + const unsigned char *message, + size_t message_len, + const unsigned char *signature, + size_t signature_len); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_signature) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_SIGNATURE_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h index 69af82d..3f3ae21 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_types.h @@ -1,495 +1,495 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API types - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_TYPES_H -#define SL_SE_MANAGER_TYPES_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -#include "sl_se_manager_defines.h" -#include "em_se.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Typedefs - -/// @addtogroup sl_se_manager_util -/// @{ - -/// OTP key types -typedef enum { - SL_SE_KEY_TYPE_IMMUTABLE_BOOT = 0, - SL_SE_KEY_TYPE_IMMUTABLE_AUTH, -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - SL_SE_KEY_TYPE_IMMUTABLE_AES_128, -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - SL_SE_KEY_TYPE_IMMUTABLE_ATTESTATION, - SL_SE_KEY_TYPE_IMMUTABLE_SE_ATTESTATION, -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT -#endif // SLI_MAILBOX_COMMAND_SUPPORTED -} sl_se_device_key_type_t; - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// SE tamper signal levels -typedef uint8_t sl_se_tamper_level_t; - -/// SE tamper signals -typedef uint32_t sl_se_tamper_signals_t; - -/// SE tamper filter timeout period -typedef uint8_t sl_se_tamper_filter_period_t; - -/// Number of tamper counts to trigger the filter signal -typedef uint8_t sl_se_tamper_filter_threshold_t; -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - -/// Certificate size data structure -typedef struct { - uint32_t batch_id_size; ///< size in bytes of the Batch certificate - uint32_t se_id_size; ///< size in bytes of the SE ID certificate - uint32_t host_id_size; ///< size in bytes of the Host ID certificate -} sl_se_cert_size_type_t; - -/// SE certificate types -typedef uint8_t sl_se_cert_type_t; - -/// OTP initialization data structure -typedef struct { - /// Enable secure boot for the host. - bool enable_secure_boot; - /// Require certificate based secure boot signing. - bool verify_secure_boot_certificate; - /// Enable anti-rollback for host application upgrades. - bool enable_anti_rollback; - /// Set flag to enable locking down all flash pages that cover the - /// secure-booted image, except the last page if end of signature is not - /// page-aligned. - bool secure_boot_page_lock_narrow; - /// Set flag to enable locking down all flash pages that cover the - /// secure-booted image, including the last page if end of signature is not - /// page-aligned. - bool secure_boot_page_lock_full; -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - /// List of tamper levels to configure for the different tamper sources. - sl_se_tamper_level_t tamper_levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS]; - /// Reset period for the tamper filter counter. - sl_se_tamper_filter_period_t tamper_filter_period; - /// Activation threshold for the tamper filter. - sl_se_tamper_filter_threshold_t tamper_filter_threshold; - /// Tamper flags. - uint8_t tamper_flags; - /// Tamper reset halt threshold. - uint8_t tamper_reset_threshold; -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT -} sl_se_otp_init_t; - -/// @} (end addtogroup sl_se_manager_util) - -/// @addtogroup sl_se_manager_core -/// @{ - -/***************************************************************************//** - * @brief SE mailbox command context - * - * @details - * This structure defines the common SE mailbox command context used for - * all SE Manager API functions that execute SE mailbox commands. The - * members of this context structure should be considered internal to the - * SE Manager and should not be read or written directly by the user - * application. For members that are relevant for the user, the user can - * access them via corresponding set and get API functions, e.g. - * sl_se_set_yield(). - ******************************************************************************/ -typedef struct sl_se_command_context_t { - SE_Command_t command; ///< SE mailbox command struct -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - bool yield; ///< If true, yield the CPU core while - ///< waiting for the SE mailbox command - ///< to complete. If false, busy-wait, by - ///< polling the SE mailbox response - ///< register. -#endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION -} sl_se_command_context_t; - -/// @} (end addtogroup sl_se_manager_core) - -/// @addtogroup sl_se_manager_util -/// @{ - -/// SE Debug lock flags -typedef uint32_t sl_se_debug_flags_t; - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -/// Debug lock options -typedef struct { - /// Non-Secure, Invasive debug access enabled if true. If false, it is not - /// possible to debug the non-secure state in a way that is intrusive to - /// program execution (DBGLOCK locked). - bool non_secure_invasive_debug; - /// Non-Secure, Non-Invasive debug access enabled if true. If false, it is - /// not possible to debug the non-secure state in a way that is intrusive to - /// program execution (NIDLOCK locked). - bool non_secure_non_invasive_debug; - /// Secure, Invasive debug access enabled if true. If false, it is not - /// possible to debug the secure TrustZone state in a way that is intrusive - /// to program execution (SPIDLOCK locked). - bool secure_invasive_debug; - /// Secure, Non-Invasive debug access enabled if true. If false, it is not - /// possible to observe the secure TrustZone state using trace. - /// (SPNIDLOCK is locked. However if SPIDLOCK is open, SPNIDLOCK will also - /// remain open.) - bool secure_non_invasive_debug; -} sl_se_debug_options_t; -#endif - -/// Debug status -typedef struct { - /// Whether device erase is enabled - bool device_erase_enabled; - /// Whether secure debug is enabled with @ref sl_se_enable_secure_debug(). - bool secure_debug_enabled; - /// Whether the debug port has been locked with @ref sl_se_apply_debug_lock(). - /// This parameter does not indicate if the debug port has been unlocked by - /// calling @ref sl_se_open_debug(). - bool debug_port_lock_applied; - /// Current state of the debug port. - /// True if locked with @ref sl_se_apply_debug_lock(). - /// False if new clean, erased or unlocked with @ref sl_se_open_debug(). - bool debug_port_lock_state; - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - /// Debug option configuration as set by @ref sl_se_set_debug_options(). - sl_se_debug_options_t options_config; - /// Current state of debug options, locked by @ref sl_se_set_debug_options() and - /// unlocked by @ref sl_se_open_debug(). - sl_se_debug_options_t options_state; - #endif -} sl_se_debug_status_t; - -/// @} (end addtogroup sl_se_manager_util) - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager_key_handling -/// @{ - -/// Supported key types -typedef uint32_t sl_se_key_type_t; - -/// Key storage method. Can have one of @ref SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, -/// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, -/// @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or -/// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. -typedef uint32_t sl_se_storage_method_t; - -/// Internal SE key slot -typedef uint32_t sl_se_key_slot_t; - -/// Describes where the key is or should be stored -typedef struct { - uint8_t* pointer; ///< Pointer to a key buffer. - uint32_t size; ///< Size of buffer. -} sl_se_buffer_t; - -/// Describes the storage location of keys -typedef struct { - /// Key storage method. Sets meaning of data in location. - sl_se_storage_method_t method; - /// Describes key storage location. @ref sl_se_buffer_t is used if @ref sl_se_key_storage_t.method is - /// @ref SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT or - /// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, while @ref sl_se_key_slot_t is - /// used for @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or - /// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. - union { - sl_se_buffer_t buffer; - sl_se_key_slot_t slot; - } location; -} sl_se_key_storage_t; - -/// Contains a full description of a key used by an SE command. -typedef struct { - /// Key type - sl_se_key_type_t type; - /// Key size, applicable if key_type == SYMMETRIC - size_t size; - /// Flags describing restrictions, permissions and attributes of the key. - uint32_t flags; - /// Storage location for this key - sl_se_key_storage_t storage; - /// Optional password for key usage (8 bytes). If no password is provided - /// (NULL pointer), any key not stored as plaintext will be stored with a - /// password of all-zero bytes. - uint8_t* password; - /// Pointer to domain descriptor if this key contains an asymmetric key on a - /// custom domain The reason for pointing instead of containing is to make - /// it possible to have the parameters in ROM. - const void* domain; -} sl_se_key_descriptor_t; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Custom Weierstrass curve structure. -typedef struct { - /// Domain size in bytes. - const size_t size; - /// Modulus p (zero-padded from MSB, right-adjusted to extend to 32-bit - /// alignment up from domain size) - const uint8_t* p; - /// Order N (zero-padded from MSB, right-adjusted to extend to 32-bit - /// alignment up from domain size) - const uint8_t* N; - /// Generator X-coordinate (zero-padded from MSB, right-adjusted to extend - /// to 32-bit alignment up from domain size) - const uint8_t* Gx; - /// Generator Y-coordinate (zero-padded from MSB, right-adjusted to extend - /// to 32-bit alignment up from domain size) - const uint8_t* Gy; - /// Parameter a (zero-padded from MSB, right-adjusted to extend to 32-bit - /// alignment up from domain size) - const uint8_t* a; - /// Parameter b (zero-padded from MSB, right-adjusted to extend to 32-bit - /// alignment up from domain size) - const uint8_t* b; - /// Set if a equals 0 - bool a_is_zero; - /// Set if a equals -3 - bool a_is_minus_three; -} sl_se_custom_weierstrass_prime_domain_t; -#endif - -/// @} (end addtogroup sl_se_manager_key_handling) - -/// @addtogroup sl_se_manager_util -/// @{ - -/// SE challenge storage -typedef uint8_t sl_se_challenge_t[SL_SE_CHALLENGE_SIZE]; - -/// SE status -typedef struct { - /// Boot status code / error code (Bits [7:0]). - uint32_t boot_status; - /// SE firmware version. - uint32_t se_fw_version; - /// Host firmware version (if available). - uint32_t host_fw_version; - /// Debug lock status. - sl_se_debug_status_t debug_status; - /// Secure boot enabled. - bool secure_boot_enabled; - /// Active mode enabled. - bool active_mode_enabled; - /// Recorded tamper status. Reset on status read. - uint32_t tamper_status; - /// Currently active tamper sources. - uint32_t tamper_status_raw; -} sl_se_status_t; - -/// @} (end addtogroup sl_se_manager_util) - -/// @addtogroup sl_se_manager_cipher -/// @{ - -/// Cipher operation types -typedef enum { - SL_SE_ENCRYPT, - SL_SE_DECRYPT -} sl_se_cipher_operation_t; - -/// CMAC streaming context -typedef struct { - uint8_t state[16]; ///< CMAC state - uint8_t data_in[16]; ///< Unprocessed data - uint8_t data_out[16]; ///< Last 16 bytes of cipher-text - size_t length; ///< Length of all processed and unprocessed data -} sl_se_cmac_multipart_context_t; - -/// CCM streaming context. -typedef struct { - uint32_t processed_message_length;///< Current length of the encrypted/decrypted data - uint32_t total_message_length; ///< Total length of data to be encrypted/decrypted - uint8_t iv[13]; ///< Nonce (MAX size is 13 bytes) - uint32_t tag_len; ///< Tag length - sl_se_cipher_operation_t mode;///< CCM mode (decrypt or encrypt) - #if defined(SLI_SE_MAJOR_VERSION_ONE) - uint8_t nonce_counter[16]; ///< Counter to keep CTR state - uint8_t iv_len; ///< Nonce length - uint8_t cbc_mac_state[16]; ///< State of authenication/MAC - uint8_t final_data[16]; ///< Input data saved for finish operation - #else - uint8_t se_ctx[32]; ///< SE encryption state - union { - uint8_t tagbuf[16]; ///< Tag - uint8_t final_data[16]; ///< Input data saved for finish operation - } mode_specific_buffer; - #endif - uint8_t final_data_length; ///< Length of data saved -} sl_se_ccm_multipart_context_t; - -typedef struct { - uint64_t len; ///< Total length of the encrypted data - uint64_t add_len; ///< Total length of the additional data - #if defined(SLI_SE_MAJOR_VERSION_ONE) - uint8_t tagbuf[16]; ///< Tag - uint8_t previous_se_ctx[32]; ///< SE state from previous operation - #endif - uint8_t se_ctx[32]; ///< SE state - uint8_t final_data[16]; ///< Input data saved for finish operation - uint8_t final_data_length; ///< Length of data saved - sl_se_cipher_operation_t mode;///< GCM mode - bool first_operation; ///< First operation -} sl_se_gcm_multipart_context_t; - -/// @} (end addtogroup sl_se_manager_cipher) - -/// @addtogroup sl_se_manager_hash -/// @{ - -/// Hash algorithms -typedef enum { - SL_SE_HASH_NONE, ///< No hash - SL_SE_HASH_SHA1, ///< SHA-1 - SL_SE_HASH_SHA224, ///< SHA-224 - SL_SE_HASH_SHA256, ///< SHA-256 -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - SL_SE_HASH_SHA384, ///< SHA-384 - SL_SE_HASH_SHA512, ///< SHA-512 -#endif -} sl_se_hash_type_t; - -/// SHA-1 streaming context. -typedef struct { - sl_se_hash_type_t hash_type; ///< Hash streaming context - uint32_t total[2]; ///< number of bytes processed - uint8_t state[32]; ///< intermediate digest state - uint8_t buffer[64]; ///< data block being processed -} sl_se_sha1_multipart_context_t; - -/// SHA-224 streaming context. -typedef struct { - sl_se_hash_type_t hash_type; ///< Hash streaming context - uint32_t total[2]; ///< Number of bytes processed - uint8_t state[32]; ///< Intermediate digest state - uint8_t buffer[64]; ///< Data block being processed -} sl_se_sha224_multipart_context_t; - -/// SHA-256 streaming context. -typedef struct { - sl_se_hash_type_t hash_type; ///< Hash streaming context - uint32_t total[2]; ///< Number of bytes processed - uint8_t state[32]; ///< Intermediate digest state - uint8_t buffer[64]; ///< Data block being processed -} sl_se_sha256_multipart_context_t; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// SHA-384 streaming context. -typedef struct { - sl_se_hash_type_t hash_type; ///< Hash streaming context - uint32_t total[4]; ///< Number of bytes processed - uint8_t state[64]; ///< Intermediate digest state - uint8_t buffer[128]; ///< Data block being processed -} sl_se_sha384_multipart_context_t; - -/// SHA-512 streaming context. -typedef struct { - sl_se_hash_type_t hash_type; ///< Hash streaming context - uint32_t total[4]; ///< Number of bytes processed - uint8_t state[64]; ///< Intermediate digest state - uint8_t buffer[128]; ///< Data block being processed -} sl_se_sha512_multipart_context_t; - -#endif - -/// @} (end addtogroup sl_se_manager_hash) - -/// @addtogroup sl_se_manager_key_derivation -/// @{ - -/// Roles in the EC J-PAKE exchange -typedef enum { - SL_SE_ECJPAKE_CLIENT = 0, ///< Client - SL_SE_ECJPAKE_SERVER, ///< Server -} sl_se_ecjpake_role_t; - -/**************************************************************************//** - * EC J-PAKE context structure. - * - * J-PAKE is a symmetric protocol, except for the identifiers used in - * Zero-Knowledge Proofs, and the serialization of the second message - * (KeyExchange) as defined by the Thread spec. - * - * In order to benefit from this symmetry, we choose a different naming - * convention from the Thread v1.0 spec. Correspondance is indicated in the - * description as a pair C: client name, S: server name - *****************************************************************************/ -typedef struct { - sl_se_command_context_t *cmd_ctx; ///< Pointer to command context object - uint32_t curve_flags; ///< Curve flags to use - sl_se_ecjpake_role_t role; ///< Are we client or server? - - char pwd[32]; ///< J-PAKE password - size_t pwd_len; ///< J-PAKE password length - - uint8_t r[32]; ///< Random scalar for exchange - uint8_t Xm1[64]; ///< Our point 1 (round 1) - uint8_t Xm2[64]; ///< Our point 2 (round 1) - uint8_t Xp1[64]; ///< Their point 1 (round 1) - uint8_t Xp2[64]; ///< Their point 2 (round 1) - uint8_t Xp[64]; ///< Their point (round 2) -} sl_se_ecjpake_context_t; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Typedef sl_se_pbkdf2_prf_type_t to sl_se_hash_type_t in order to maintain -/// backward compatibility. Defines for mapping the PRF identifiers to the -/// underlying hash enum values exists in sl_se_manager_defines.h. -typedef sl_se_hash_type_t sl_se_pbkdf2_prf_type_t; -#endif - -/// @} (end addtogroup sl_se_manager_key_derivation) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_TYPES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API types + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_TYPES_H +#define SL_SE_MANAGER_TYPES_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +#include "sl_se_manager_defines.h" +#include "em_se.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Typedefs + +/// @addtogroup sl_se_manager_util +/// @{ + +/// OTP key types +typedef enum { + SL_SE_KEY_TYPE_IMMUTABLE_BOOT = 0, + SL_SE_KEY_TYPE_IMMUTABLE_AUTH, +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + SL_SE_KEY_TYPE_IMMUTABLE_AES_128, +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + SL_SE_KEY_TYPE_IMMUTABLE_ATTESTATION, + SL_SE_KEY_TYPE_IMMUTABLE_SE_ATTESTATION, +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT +#endif // SLI_MAILBOX_COMMAND_SUPPORTED +} sl_se_device_key_type_t; + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// SE tamper signal levels +typedef uint8_t sl_se_tamper_level_t; + +/// SE tamper signals +typedef uint32_t sl_se_tamper_signals_t; + +/// SE tamper filter timeout period +typedef uint8_t sl_se_tamper_filter_period_t; + +/// Number of tamper counts to trigger the filter signal +typedef uint8_t sl_se_tamper_filter_threshold_t; +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + +/// Certificate size data structure +typedef struct { + uint32_t batch_id_size; ///< size in bytes of the Batch certificate + uint32_t se_id_size; ///< size in bytes of the SE ID certificate + uint32_t host_id_size; ///< size in bytes of the Host ID certificate +} sl_se_cert_size_type_t; + +/// SE certificate types +typedef uint8_t sl_se_cert_type_t; + +/// OTP initialization data structure +typedef struct { + /// Enable secure boot for the host. + bool enable_secure_boot; + /// Require certificate based secure boot signing. + bool verify_secure_boot_certificate; + /// Enable anti-rollback for host application upgrades. + bool enable_anti_rollback; + /// Set flag to enable locking down all flash pages that cover the + /// secure-booted image, except the last page if end of signature is not + /// page-aligned. + bool secure_boot_page_lock_narrow; + /// Set flag to enable locking down all flash pages that cover the + /// secure-booted image, including the last page if end of signature is not + /// page-aligned. + bool secure_boot_page_lock_full; +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + /// List of tamper levels to configure for the different tamper sources. + sl_se_tamper_level_t tamper_levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS]; + /// Reset period for the tamper filter counter. + sl_se_tamper_filter_period_t tamper_filter_period; + /// Activation threshold for the tamper filter. + sl_se_tamper_filter_threshold_t tamper_filter_threshold; + /// Tamper flags. + uint8_t tamper_flags; + /// Tamper reset halt threshold. + uint8_t tamper_reset_threshold; +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT +} sl_se_otp_init_t; + +/// @} (end addtogroup sl_se_manager_util) + +/// @addtogroup sl_se_manager_core +/// @{ + +/***************************************************************************//** + * @brief SE mailbox command context + * + * @details + * This structure defines the common SE mailbox command context used for + * all SE Manager API functions that execute SE mailbox commands. The + * members of this context structure should be considered internal to the + * SE Manager and should not be read or written directly by the user + * application. For members that are relevant for the user, the user can + * access them via corresponding set and get API functions, e.g. + * sl_se_set_yield(). + ******************************************************************************/ +typedef struct sl_se_command_context_t { + SE_Command_t command; ///< SE mailbox command struct +#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + bool yield; ///< If true, yield the CPU core while + ///< waiting for the SE mailbox command + ///< to complete. If false, busy-wait, by + ///< polling the SE mailbox response + ///< register. +#endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION +} sl_se_command_context_t; + +/// @} (end addtogroup sl_se_manager_core) + +/// @addtogroup sl_se_manager_util +/// @{ + +/// SE Debug lock flags +typedef uint32_t sl_se_debug_flags_t; + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/// Debug lock options +typedef struct { + /// Non-Secure, Invasive debug access enabled if true. If false, it is not + /// possible to debug the non-secure state in a way that is intrusive to + /// program execution (DBGLOCK locked). + bool non_secure_invasive_debug; + /// Non-Secure, Non-Invasive debug access enabled if true. If false, it is + /// not possible to debug the non-secure state in a way that is intrusive to + /// program execution (NIDLOCK locked). + bool non_secure_non_invasive_debug; + /// Secure, Invasive debug access enabled if true. If false, it is not + /// possible to debug the secure TrustZone state in a way that is intrusive + /// to program execution (SPIDLOCK locked). + bool secure_invasive_debug; + /// Secure, Non-Invasive debug access enabled if true. If false, it is not + /// possible to observe the secure TrustZone state using trace. + /// (SPNIDLOCK is locked. However if SPIDLOCK is open, SPNIDLOCK will also + /// remain open.) + bool secure_non_invasive_debug; +} sl_se_debug_options_t; +#endif + +/// Debug status +typedef struct { + /// Whether device erase is enabled + bool device_erase_enabled; + /// Whether secure debug is enabled with @ref sl_se_enable_secure_debug(). + bool secure_debug_enabled; + /// Whether the debug port has been locked with @ref sl_se_apply_debug_lock(). + /// This parameter does not indicate if the debug port has been unlocked by + /// calling @ref sl_se_open_debug(). + bool debug_port_lock_applied; + /// Current state of the debug port. + /// True if locked with @ref sl_se_apply_debug_lock(). + /// False if new clean, erased or unlocked with @ref sl_se_open_debug(). + bool debug_port_lock_state; + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + /// Debug option configuration as set by @ref sl_se_set_debug_options(). + sl_se_debug_options_t options_config; + /// Current state of debug options, locked by @ref sl_se_set_debug_options() and + /// unlocked by @ref sl_se_open_debug(). + sl_se_debug_options_t options_state; + #endif +} sl_se_debug_status_t; + +/// @} (end addtogroup sl_se_manager_util) + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager_key_handling +/// @{ + +/// Supported key types +typedef uint32_t sl_se_key_type_t; + +/// Key storage method. Can have one of @ref SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT, +/// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, +/// @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or +/// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. +typedef uint32_t sl_se_storage_method_t; + +/// Internal SE key slot +typedef uint32_t sl_se_key_slot_t; + +/// Describes where the key is or should be stored +typedef struct { + uint8_t* pointer; ///< Pointer to a key buffer. + uint32_t size; ///< Size of buffer. +} sl_se_buffer_t; + +/// Describes the storage location of keys +typedef struct { + /// Key storage method. Sets meaning of data in location. + sl_se_storage_method_t method; + /// Describes key storage location. @ref sl_se_buffer_t is used if @ref sl_se_key_storage_t.method is + /// @ref SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT or + /// @ref SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED, while @ref sl_se_key_slot_t is + /// used for @ref SL_SE_KEY_STORAGE_INTERNAL_VOLATILE or + /// @ref SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE. + union { + sl_se_buffer_t buffer; + sl_se_key_slot_t slot; + } location; +} sl_se_key_storage_t; + +/// Contains a full description of a key used by an SE command. +typedef struct { + /// Key type + sl_se_key_type_t type; + /// Key size, applicable if key_type == SYMMETRIC + size_t size; + /// Flags describing restrictions, permissions and attributes of the key. + uint32_t flags; + /// Storage location for this key + sl_se_key_storage_t storage; + /// Optional password for key usage (8 bytes). If no password is provided + /// (NULL pointer), any key not stored as plaintext will be stored with a + /// password of all-zero bytes. + uint8_t* password; + /// Pointer to domain descriptor if this key contains an asymmetric key on a + /// custom domain The reason for pointing instead of containing is to make + /// it possible to have the parameters in ROM. + const void* domain; +} sl_se_key_descriptor_t; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Custom Weierstrass curve structure. +typedef struct { + /// Domain size in bytes. + const size_t size; + /// Modulus p (zero-padded from MSB, right-adjusted to extend to 32-bit + /// alignment up from domain size) + const uint8_t* p; + /// Order N (zero-padded from MSB, right-adjusted to extend to 32-bit + /// alignment up from domain size) + const uint8_t* N; + /// Generator X-coordinate (zero-padded from MSB, right-adjusted to extend + /// to 32-bit alignment up from domain size) + const uint8_t* Gx; + /// Generator Y-coordinate (zero-padded from MSB, right-adjusted to extend + /// to 32-bit alignment up from domain size) + const uint8_t* Gy; + /// Parameter a (zero-padded from MSB, right-adjusted to extend to 32-bit + /// alignment up from domain size) + const uint8_t* a; + /// Parameter b (zero-padded from MSB, right-adjusted to extend to 32-bit + /// alignment up from domain size) + const uint8_t* b; + /// Set if a equals 0 + bool a_is_zero; + /// Set if a equals -3 + bool a_is_minus_three; +} sl_se_custom_weierstrass_prime_domain_t; +#endif + +/// @} (end addtogroup sl_se_manager_key_handling) + +/// @addtogroup sl_se_manager_util +/// @{ + +/// SE challenge storage +typedef uint8_t sl_se_challenge_t[SL_SE_CHALLENGE_SIZE]; + +/// SE status +typedef struct { + /// Boot status code / error code (Bits [7:0]). + uint32_t boot_status; + /// SE firmware version. + uint32_t se_fw_version; + /// Host firmware version (if available). + uint32_t host_fw_version; + /// Debug lock status. + sl_se_debug_status_t debug_status; + /// Secure boot enabled. + bool secure_boot_enabled; + /// Active mode enabled. + bool active_mode_enabled; + /// Recorded tamper status. Reset on status read. + uint32_t tamper_status; + /// Currently active tamper sources. + uint32_t tamper_status_raw; +} sl_se_status_t; + +/// @} (end addtogroup sl_se_manager_util) + +/// @addtogroup sl_se_manager_cipher +/// @{ + +/// Cipher operation types +typedef enum { + SL_SE_ENCRYPT, + SL_SE_DECRYPT +} sl_se_cipher_operation_t; + +/// CMAC streaming context +typedef struct { + uint8_t state[16]; ///< CMAC state + uint8_t data_in[16]; ///< Unprocessed data + uint8_t data_out[16]; ///< Last 16 bytes of cipher-text + size_t length; ///< Length of all processed and unprocessed data +} sl_se_cmac_multipart_context_t; + +/// CCM streaming context. +typedef struct { + uint32_t processed_message_length;///< Current length of the encrypted/decrypted data + uint32_t total_message_length; ///< Total length of data to be encrypted/decrypted + uint8_t iv[13]; ///< Nonce (MAX size is 13 bytes) + uint32_t tag_len; ///< Tag length + sl_se_cipher_operation_t mode;///< CCM mode (decrypt or encrypt) + #if defined(SLI_SE_MAJOR_VERSION_ONE) + uint8_t nonce_counter[16]; ///< Counter to keep CTR state + uint8_t iv_len; ///< Nonce length + uint8_t cbc_mac_state[16]; ///< State of authenication/MAC + uint8_t final_data[16]; ///< Input data saved for finish operation + #else + uint8_t se_ctx[32]; ///< SE encryption state + union { + uint8_t tagbuf[16]; ///< Tag + uint8_t final_data[16]; ///< Input data saved for finish operation + } mode_specific_buffer; + #endif + uint8_t final_data_length; ///< Length of data saved +} sl_se_ccm_multipart_context_t; + +typedef struct { + uint64_t len; ///< Total length of the encrypted data + uint64_t add_len; ///< Total length of the additional data + #if defined(SLI_SE_MAJOR_VERSION_ONE) + uint8_t tagbuf[16]; ///< Tag + uint8_t previous_se_ctx[32]; ///< SE state from previous operation + #endif + uint8_t se_ctx[32]; ///< SE state + uint8_t final_data[16]; ///< Input data saved for finish operation + uint8_t final_data_length; ///< Length of data saved + sl_se_cipher_operation_t mode;///< GCM mode + bool first_operation; ///< First operation +} sl_se_gcm_multipart_context_t; + +/// @} (end addtogroup sl_se_manager_cipher) + +/// @addtogroup sl_se_manager_hash +/// @{ + +/// Hash algorithms +typedef enum { + SL_SE_HASH_NONE, ///< No hash + SL_SE_HASH_SHA1, ///< SHA-1 + SL_SE_HASH_SHA224, ///< SHA-224 + SL_SE_HASH_SHA256, ///< SHA-256 +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + SL_SE_HASH_SHA384, ///< SHA-384 + SL_SE_HASH_SHA512, ///< SHA-512 +#endif +} sl_se_hash_type_t; + +/// SHA-1 streaming context. +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash streaming context + uint32_t total[2]; ///< number of bytes processed + uint8_t state[32]; ///< intermediate digest state + uint8_t buffer[64]; ///< data block being processed +} sl_se_sha1_multipart_context_t; + +/// SHA-224 streaming context. +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash streaming context + uint32_t total[2]; ///< Number of bytes processed + uint8_t state[32]; ///< Intermediate digest state + uint8_t buffer[64]; ///< Data block being processed +} sl_se_sha224_multipart_context_t; + +/// SHA-256 streaming context. +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash streaming context + uint32_t total[2]; ///< Number of bytes processed + uint8_t state[32]; ///< Intermediate digest state + uint8_t buffer[64]; ///< Data block being processed +} sl_se_sha256_multipart_context_t; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// SHA-384 streaming context. +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash streaming context + uint32_t total[4]; ///< Number of bytes processed + uint8_t state[64]; ///< Intermediate digest state + uint8_t buffer[128]; ///< Data block being processed +} sl_se_sha384_multipart_context_t; + +/// SHA-512 streaming context. +typedef struct { + sl_se_hash_type_t hash_type; ///< Hash streaming context + uint32_t total[4]; ///< Number of bytes processed + uint8_t state[64]; ///< Intermediate digest state + uint8_t buffer[128]; ///< Data block being processed +} sl_se_sha512_multipart_context_t; + +#endif + +/// @} (end addtogroup sl_se_manager_hash) + +/// @addtogroup sl_se_manager_key_derivation +/// @{ + +/// Roles in the EC J-PAKE exchange +typedef enum { + SL_SE_ECJPAKE_CLIENT = 0, ///< Client + SL_SE_ECJPAKE_SERVER, ///< Server +} sl_se_ecjpake_role_t; + +/**************************************************************************//** + * EC J-PAKE context structure. + * + * J-PAKE is a symmetric protocol, except for the identifiers used in + * Zero-Knowledge Proofs, and the serialization of the second message + * (KeyExchange) as defined by the Thread spec. + * + * In order to benefit from this symmetry, we choose a different naming + * convention from the Thread v1.0 spec. Correspondance is indicated in the + * description as a pair C: client name, S: server name + *****************************************************************************/ +typedef struct { + sl_se_command_context_t *cmd_ctx; ///< Pointer to command context object + uint32_t curve_flags; ///< Curve flags to use + sl_se_ecjpake_role_t role; ///< Are we client or server? + + char pwd[32]; ///< J-PAKE password + size_t pwd_len; ///< J-PAKE password length + + uint8_t r[32]; ///< Random scalar for exchange + uint8_t Xm1[64]; ///< Our point 1 (round 1) + uint8_t Xm2[64]; ///< Our point 2 (round 1) + uint8_t Xp1[64]; ///< Their point 1 (round 1) + uint8_t Xp2[64]; ///< Their point 2 (round 1) + uint8_t Xp[64]; ///< Their point (round 2) +} sl_se_ecjpake_context_t; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Typedef sl_se_pbkdf2_prf_type_t to sl_se_hash_type_t in order to maintain +/// backward compatibility. Defines for mapping the PRF identifiers to the +/// underlying hash enum values exists in sl_se_manager_defines.h. +typedef sl_se_hash_type_t sl_se_pbkdf2_prf_type_t; +#endif + +/// @} (end addtogroup sl_se_manager_key_derivation) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_TYPES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h index e2b5f56..8597bda 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sl_se_manager_util.h @@ -1,825 +1,825 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SE_MANAGER_UTIL_H -#define SL_SE_MANAGER_UTIL_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -/// @addtogroup sl_se_manager -/// @{ - -/***************************************************************************//** - * @addtogroup sl_se_manager_util Utilities - * - * @brief - * Device initialisation, debug lock, upgrade functionality, user data... - * - * @details - * API for managing the Secure Engine or Root code on a device. Upload and - * read device configuration. - * - * @{ - ******************************************************************************/ - -#if !defined(SL_TRUSTZONE_NONSECURE) -#include "sl_se_manager_key_handling.h" -#endif -#include "sl_se_manager_types.h" -#include "em_se.h" -#include "sl_status.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * @brief - * Validate SE firmware image. - * - * @details - * Validate SE firmware image located at given address. This function is - * typically used before calling sl_se_apply_se_image. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] image_addr - * Pointer to SE image to validate. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, - void *image_addr); - -/***************************************************************************//** - * @brief - * Apply SE firmware image. - * - * @details - * Apply SE firmware image located at given address. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] image_addr - * Pointer to SE image to apply. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, - void *image_addr); - -/***************************************************************************//** - * @brief - * Get upgrade status of SE firmware image. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] status - * Pointer to 32-bit word where to return upgrade status. - * - * @param[in] prev_version - * Pointer to 32-bit word where to return previous version. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, - uint32_t *status, - uint32_t *prev_version); - -/***************************************************************************//** - * @brief - * Validate Host firmware image. - * - * @details - * Validate Host firmware image located at given address. This function is - * typically used before calling @ref sl_se_apply_host_image. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] image_addr - * Pointer to Host image to validate. - * - * @param[in] size - * Size of Host image to validate. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, - void *image_addr, - uint32_t size); - -/***************************************************************************//** - * @brief - * Apply Host firmware image. - * - * @details - * Apply Host firmware image located at given address. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] image_addr - * Pointer to Host image to apply. - * - * @param[in] size - * Size of Host image to apply. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, - void *image_addr, - uint32_t size); - -/***************************************************************************//** - * @brief - * Get upgrade status of Host firmware image. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] status - * Pointer to 32-bit word where to return upgrade status. - * - * @param[in] prev_version - * Pointer to 32-bit word where to return previous version. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t -sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, - uint32_t *status, - uint32_t *prev_version); - -/***************************************************************************//** - * @brief - * Initialize key to be stored in the SE OTP flash. - * - * @details - * Initialize key stored in the SE. The command can be used to write (@ref sl_se_device_key_type_t): - * * SL_SE_KEY_TYPE_IMMUTABLE_BOOT - * * SL_SE_KEY_TYPE_IMMUTABLE_AUTH - * * SL_SE_KEY_TYPE_IMMUTABLE_AES_128 - * - * @note - * These keys can not be overwritten, so this command can only be issued once - * per key per part. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_type - * ID of key type to initialize. - * - * @param[in] key - * Pointer to a buffer that contains the key. - * Public keys must be word aligned and have a length of 64 bytes. - * AES-128 keys must be word aligned and have length of 16 bytes. - * - * @param[in] num_bytes - * Length of key buffer in bytes (16 or 64 bytes). - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, - sl_se_device_key_type_t key_type, - void *key, - uint32_t num_bytes); - -/***************************************************************************//** - * @brief - * Read a public key stored in the SE. - * - * @details - * Read out a public key stored in the SE. The command can be used to read (@ref sl_se_device_key_type_t): - * * SL_SE_KEY_TYPE_IMMUTABLE_BOOT - * * SL_SE_KEY_TYPE_IMMUTABLE_AUTH - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] key_type - * ID of key type to read. - * - * @param[out] key - * Pointer to a buffer to contain the returned public key. - * Must be word aligned and have a length of 64 bytes. - * - * @param[in] num_bytes - * Length of pubkey buffer (64 bytes). - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, - sl_se_device_key_type_t key_type, - void *key, - uint32_t num_bytes); - -/***************************************************************************//** - * @brief - * Initialize SE OTP configuration. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] otp_init - * Pointer to OTP initialization structure. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_ABORT when the operation is not attempted. - ******************************************************************************/ -sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_init); - -/***************************************************************************//** - * @brief - * Read the OTP firmware version of the SE module. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] version - * Pointer to uint32_t word where version shall be returned. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, - uint32_t *version); - -/***************************************************************************//** - * @brief - * Read SE OTP configuration. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] otp_settings - * Pointer to OTP initialization structure. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_COMMAND if OTP configuration isn't initialized - * @retval SL_STATUS_ABORT when the operation is not attempted. - ******************************************************************************/ -sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_settings); - -/***************************************************************************//** - * @brief - * Read the SE firmware version. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] version - * Pointer to uint32_t word where version shall be returned. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_OWNERSHIP when the ownership is already taken - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, - uint32_t *version); - -/***************************************************************************//** - * @brief - * Returns the current debug lock configuration. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] status - * Pointer to sl_se_debug_status_t structure to be filled out with the - * current status of the debug configuration. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, - sl_se_debug_status_t *status); - -/***************************************************************************//** - * @brief - * Enables the debug lock for the part. - * - * @details - * The debug port will be closed and the only way to open it is through - * device erase (if enabled) or through secure debug unlock (if enabled). - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx); - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -/***************************************************************************//** - * @brief - * Writes data to User Data section in MTP. Write data must be aligned to - * word size and contain a number of bytes that is divisable by four. - * @note - * It is recommended to erase the flash page before performing a write. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * @param[in] offset - * Offset to the flash word to write to. Must be aligned to words. - * @param[in] data - * Data to write to flash. - * @param[in] num_bytes - * Number of bytes to write to flash. NB: Must be divisable by four. - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, - uint32_t offset, - void *data, - uint32_t num_bytes); - -/***************************************************************************//** - * @brief - * Erases User Data section in MTP. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Returns the current boot status, versions and system configuration. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] status - * SE_Status_t containing current SE status. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK upon command completion. Errors are encoded in the - * different parts of the returned status object. - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, - sl_se_status_t *status); - -/***************************************************************************//** - * @brief - * Read the serial number of the SE module. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] serial - * Pointer to array of size 16 bytes. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, - void *serial); - -#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) -/***************************************************************************//** - * @brief - * Read the EMU->RSTCAUSE after a tamper reset. This function should be called - * if EMU->RSTCAUSE has been cleared upon boot. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] reset_cause - * Pointer to uint32_t word where reset cause shall be returned. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - ******************************************************************************/ -sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, - uint32_t *reset_cause); -#endif - -#if defined(SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE) -/***************************************************************************//** - * @brief - * Read the latest cached tamper reset cause. The returned value is the index - * of the tamper source that caused a reset. - * Requires SE version 2.2.1 or above. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] was_tamper_reset - * Pointer to bool that indicates if a tamper event occurred. If the cached - * value is 0 this will be false, true otherwise. - * - * @param[out] reset_cause - * Pointer to a uint32_t where the cached reset cause value should - * be returned. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_PARAMETER when cmd_ctx or reset_cause is NULL - ******************************************************************************/ -sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, - bool *was_tamper_reset, - uint32_t *reset_cause); -#endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE - -/***************************************************************************//** - * @brief - * Enables the secure debug functionality. - * - * @details - * Enables the secure debug functionality that can be used to open a locked - * debug port through the Get challenge and Open debug commands. This command - * can only be executed before the debug port is locked, and after a secure - * debug public key has been installed in the SE. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Disables the secure debug functionality. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @details - * Disables the secure debug functionality that can be used to open a - * locked debug port. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************/ /** - * @brief - * Set debug options. - * - * @details - * This function makes it possible to configure the Trust-Zone access - * permissions of the debug interface. For details please refer to - * @ref sl_se_debug_options_t. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] debug_options - * Pointer to debug options structure. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, - const sl_se_debug_options_t *debug_options); - -/***************************************************************************//** - * @brief - * Performs a device mass erase and debug unlock. - * - * @details - * Performs a device mass erase and resets the debug configuration to its - * initial unlocked state. Only available before DEVICE_ERASE_DISABLE has - * been executed. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @note - * This command clears and verifies the complete flash and ram of the - * system, excluding the user data pages and one-time programmable - * commissioning information in the secure engine. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_COMMAND if device erase is disabled. - ******************************************************************************/ -sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx); - -/****************************************************************q***********//** - * @brief - * Disabled device erase functionality. - * - * @details - * This command disables the device erase command. It does not lock the - * debug interface to the part, but it is a permanent action for the part. - * If device erase is disabled and the device is debug locked, there is no - * way to permanently unlock the part. If secure debug unlock is enabled, - * secure debug unlock can still be used to temporarily open the debug port. - * - * @warning - * This command permanently disables the device erase functionality! - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Request challenge from SE which can be used to open debug access. - * - * @details - * This command requests a challenge (16 bytes) which can be used to generate - * a certificate in order to open debug access, @ref sl_se_open_debug. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[out] challenge - * SE challenge storage. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, - sl_se_challenge_t challenge); - -/***************************************************************************//** - * @brief - * Invalidate current challenge and make a new challenge. - * - * @details - * This command requests the SE to invalidate it's current challenge (16bytes) - * and generate a new challenge. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - ******************************************************************************/ -sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Unlock debug access using certificate and signed challenge. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] cert - * Certificate for debug unlock and signed challenge. - * - * @param[in] len - * Length of certificate in number of bytes. - * - * @param[in] debug_options - * Debug options to open/unlock. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, - void *cert, - uint32_t len, - const sl_se_debug_options_t *debug_options); - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * @brief - * Temporarily disable tamper configuration using certificate and signed - * challenge. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] cert - * Certificate for disabling tamper and signed challenge. - * - * @param[in] len - * Length of certificate in number of bytes. - * - * @param[in] tamper_signals - * Tamper signals to disable. Each signal represented by a bit. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized - * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - ******************************************************************************/ -sl_status_t sl_se_disable_tamper(sl_se_command_context_t *cmd_ctx, - void *cert, - uint32_t len, - sl_se_tamper_signals_t tamper_signals); - -#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -/***************************************************************************//** - * @brief - * Read size of stored certificates in SE. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in,out] cert_size - * Size of the certificates stored in SE. - - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_read_cert_size(sl_se_command_context_t *cmd_ctx, - sl_se_cert_size_type_t *cert_size); - -/***************************************************************************//** - * @brief - * Read stored certificates in SE. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @param[in] cert_type - * Type of the certificate stored in SE. - * - * @param[in,out] cert - * Buffer to read certificate. - * - * @param[in] num_bytes - * Length of certificate in number of bytes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, - sl_se_cert_type_t cert_type, - void *cert, - uint32_t num_bytes); - -/***************************************************************************//** - * @brief - * Enter SE active mode. - * - * @details - * SE will enter active mode. This will ensure SE is not powered down between - * operations, at the expense of increased power consumption. - * - * @warning - * Active mode will prevent entry to EM2/3/4. To allow energy mode entry, exit - * active mode through @ref sl_se_exit_active_mode(). - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_COMMAND_IS_INVALID when already in active mode - ******************************************************************************/ -sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx); - -/***************************************************************************//** - * @brief - * Exit SE active mode. - * - * @details - * SE will exit active mode. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * One of the following sl_status_t codes: - * @retval SL_STATUS_OK when the command was executed successfully - * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed - * @retval SL_STATUS_COMMAND_IS_INVALID when already not in active mode - ******************************************************************************/ -sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx); - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sl_se_manager_util) -/// @} (end addtogroup sl_se_manager) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#endif // SL_SE_MANAGER_UTIL_H +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SE_MANAGER_UTIL_H +#define SL_SE_MANAGER_UTIL_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +/// @addtogroup sl_se_manager +/// @{ + +/***************************************************************************//** + * @addtogroup sl_se_manager_util Utilities + * + * @brief + * Device initialisation, debug lock, upgrade functionality, user data... + * + * @details + * API for managing the Secure Engine or Root code on a device. Upload and + * read device configuration. + * + * @{ + ******************************************************************************/ + +#if !defined(SL_TRUSTZONE_NONSECURE) +#include "sl_se_manager_key_handling.h" +#endif +#include "sl_se_manager_types.h" +#include "em_se.h" +#include "sl_status.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * @brief + * Validate SE firmware image. + * + * @details + * Validate SE firmware image located at given address. This function is + * typically used before calling sl_se_apply_se_image. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] image_addr + * Pointer to SE image to validate. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, + void *image_addr); + +/***************************************************************************//** + * @brief + * Apply SE firmware image. + * + * @details + * Apply SE firmware image located at given address. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] image_addr + * Pointer to SE image to apply. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, + void *image_addr); + +/***************************************************************************//** + * @brief + * Get upgrade status of SE firmware image. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] status + * Pointer to 32-bit word where to return upgrade status. + * + * @param[in] prev_version + * Pointer to 32-bit word where to return previous version. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, + uint32_t *status, + uint32_t *prev_version); + +/***************************************************************************//** + * @brief + * Validate Host firmware image. + * + * @details + * Validate Host firmware image located at given address. This function is + * typically used before calling @ref sl_se_apply_host_image. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] image_addr + * Pointer to Host image to validate. + * + * @param[in] size + * Size of Host image to validate. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, + void *image_addr, + uint32_t size); + +/***************************************************************************//** + * @brief + * Apply Host firmware image. + * + * @details + * Apply Host firmware image located at given address. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] image_addr + * Pointer to Host image to apply. + * + * @param[in] size + * Size of Host image to apply. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, + void *image_addr, + uint32_t size); + +/***************************************************************************//** + * @brief + * Get upgrade status of Host firmware image. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] status + * Pointer to 32-bit word where to return upgrade status. + * + * @param[in] prev_version + * Pointer to 32-bit word where to return previous version. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t +sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, + uint32_t *status, + uint32_t *prev_version); + +/***************************************************************************//** + * @brief + * Initialize key to be stored in the SE OTP flash. + * + * @details + * Initialize key stored in the SE. The command can be used to write (@ref sl_se_device_key_type_t): + * * SL_SE_KEY_TYPE_IMMUTABLE_BOOT + * * SL_SE_KEY_TYPE_IMMUTABLE_AUTH + * * SL_SE_KEY_TYPE_IMMUTABLE_AES_128 + * + * @note + * These keys can not be overwritten, so this command can only be issued once + * per key per part. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_type + * ID of key type to initialize. + * + * @param[in] key + * Pointer to a buffer that contains the key. + * Public keys must be word aligned and have a length of 64 bytes. + * AES-128 keys must be word aligned and have length of 16 bytes. + * + * @param[in] num_bytes + * Length of key buffer in bytes (16 or 64 bytes). + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, + sl_se_device_key_type_t key_type, + void *key, + uint32_t num_bytes); + +/***************************************************************************//** + * @brief + * Read a public key stored in the SE. + * + * @details + * Read out a public key stored in the SE. The command can be used to read (@ref sl_se_device_key_type_t): + * * SL_SE_KEY_TYPE_IMMUTABLE_BOOT + * * SL_SE_KEY_TYPE_IMMUTABLE_AUTH + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] key_type + * ID of key type to read. + * + * @param[out] key + * Pointer to a buffer to contain the returned public key. + * Must be word aligned and have a length of 64 bytes. + * + * @param[in] num_bytes + * Length of pubkey buffer (64 bytes). + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, + sl_se_device_key_type_t key_type, + void *key, + uint32_t num_bytes); + +/***************************************************************************//** + * @brief + * Initialize SE OTP configuration. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] otp_init + * Pointer to OTP initialization structure. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * @retval SL_STATUS_ABORT when the operation is not attempted. + ******************************************************************************/ +sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_init); + +/***************************************************************************//** + * @brief + * Read the OTP firmware version of the SE module. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] version + * Pointer to uint32_t word where version shall be returned. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version); + +/***************************************************************************//** + * @brief + * Read SE OTP configuration. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] otp_settings + * Pointer to OTP initialization structure. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_COMMAND if OTP configuration isn't initialized + * @retval SL_STATUS_ABORT when the operation is not attempted. + ******************************************************************************/ +sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_settings); + +/***************************************************************************//** + * @brief + * Read the SE firmware version. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] version + * Pointer to uint32_t word where version shall be returned. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_OWNERSHIP when the ownership is already taken + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version); + +/***************************************************************************//** + * @brief + * Returns the current debug lock configuration. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] status + * Pointer to sl_se_debug_status_t structure to be filled out with the + * current status of the debug configuration. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, + sl_se_debug_status_t *status); + +/***************************************************************************//** + * @brief + * Enables the debug lock for the part. + * + * @details + * The debug port will be closed and the only way to open it is through + * device erase (if enabled) or through secure debug unlock (if enabled). + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx); + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @brief + * Writes data to User Data section in MTP. Write data must be aligned to + * word size and contain a number of bytes that is divisable by four. + * @note + * It is recommended to erase the flash page before performing a write. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * @param[in] offset + * Offset to the flash word to write to. Must be aligned to words. + * @param[in] data + * Data to write to flash. + * @param[in] num_bytes + * Number of bytes to write to flash. NB: Must be divisable by four. + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, + uint32_t offset, + void *data, + uint32_t num_bytes); + +/***************************************************************************//** + * @brief + * Erases User Data section in MTP. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Returns the current boot status, versions and system configuration. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] status + * SE_Status_t containing current SE status. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK upon command completion. Errors are encoded in the + * different parts of the returned status object. + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, + sl_se_status_t *status); + +/***************************************************************************//** + * @brief + * Read the serial number of the SE module. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] serial + * Pointer to array of size 16 bytes. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, + void *serial); + +#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) +/***************************************************************************//** + * @brief + * Read the EMU->RSTCAUSE after a tamper reset. This function should be called + * if EMU->RSTCAUSE has been cleared upon boot. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] reset_cause + * Pointer to uint32_t word where reset cause shall be returned. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + ******************************************************************************/ +sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, + uint32_t *reset_cause); +#endif + +#if defined(SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE) +/***************************************************************************//** + * @brief + * Read the latest cached tamper reset cause. The returned value is the index + * of the tamper source that caused a reset. + * Requires SE version 2.2.1 or above. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] was_tamper_reset + * Pointer to bool that indicates if a tamper event occurred. If the cached + * value is 0 this will be false, true otherwise. + * + * @param[out] reset_cause + * Pointer to a uint32_t where the cached reset cause value should + * be returned. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_PARAMETER when cmd_ctx or reset_cause is NULL + ******************************************************************************/ +sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, + bool *was_tamper_reset, + uint32_t *reset_cause); +#endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE + +/***************************************************************************//** + * @brief + * Enables the secure debug functionality. + * + * @details + * Enables the secure debug functionality that can be used to open a locked + * debug port through the Get challenge and Open debug commands. This command + * can only be executed before the debug port is locked, and after a secure + * debug public key has been installed in the SE. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Disables the secure debug functionality. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @details + * Disables the secure debug functionality that can be used to open a + * locked debug port. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************/ /** + * @brief + * Set debug options. + * + * @details + * This function makes it possible to configure the Trust-Zone access + * permissions of the debug interface. For details please refer to + * @ref sl_se_debug_options_t. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] debug_options + * Pointer to debug options structure. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, + const sl_se_debug_options_t *debug_options); + +/***************************************************************************//** + * @brief + * Performs a device mass erase and debug unlock. + * + * @details + * Performs a device mass erase and resets the debug configuration to its + * initial unlocked state. Only available before DEVICE_ERASE_DISABLE has + * been executed. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @note + * This command clears and verifies the complete flash and ram of the + * system, excluding the user data pages and one-time programmable + * commissioning information in the secure engine. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_COMMAND if device erase is disabled. + ******************************************************************************/ +sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx); + +/****************************************************************q***********//** + * @brief + * Disabled device erase functionality. + * + * @details + * This command disables the device erase command. It does not lock the + * debug interface to the part, but it is a permanent action for the part. + * If device erase is disabled and the device is debug locked, there is no + * way to permanently unlock the part. If secure debug unlock is enabled, + * secure debug unlock can still be used to temporarily open the debug port. + * + * @warning + * This command permanently disables the device erase functionality! + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Request challenge from SE which can be used to open debug access. + * + * @details + * This command requests a challenge (16 bytes) which can be used to generate + * a certificate in order to open debug access, @ref sl_se_open_debug. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[out] challenge + * SE challenge storage. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, + sl_se_challenge_t challenge); + +/***************************************************************************//** + * @brief + * Invalidate current challenge and make a new challenge. + * + * @details + * This command requests the SE to invalidate it's current challenge (16bytes) + * and generate a new challenge. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + ******************************************************************************/ +sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Unlock debug access using certificate and signed challenge. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] cert + * Certificate for debug unlock and signed challenge. + * + * @param[in] len + * Length of certificate in number of bytes. + * + * @param[in] debug_options + * Debug options to open/unlock. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, + void *cert, + uint32_t len, + const sl_se_debug_options_t *debug_options); + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * @brief + * Temporarily disable tamper configuration using certificate and signed + * challenge. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] cert + * Certificate for disabling tamper and signed challenge. + * + * @param[in] len + * Length of certificate in number of bytes. + * + * @param[in] tamper_signals + * Tamper signals to disable. Each signal represented by a bit. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_OPERATION when the SE command ID is not recognized + * @retval SL_STATUS_INVALID_CREDENTIALS when the command is not authorized + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + ******************************************************************************/ +sl_status_t sl_se_disable_tamper(sl_se_command_context_t *cmd_ctx, + void *cert, + uint32_t len, + sl_se_tamper_signals_t tamper_signals); + +#endif // (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +/***************************************************************************//** + * @brief + * Read size of stored certificates in SE. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in,out] cert_size + * Size of the certificates stored in SE. + + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_read_cert_size(sl_se_command_context_t *cmd_ctx, + sl_se_cert_size_type_t *cert_size); + +/***************************************************************************//** + * @brief + * Read stored certificates in SE. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @param[in] cert_type + * Type of the certificate stored in SE. + * + * @param[in,out] cert + * Buffer to read certificate. + * + * @param[in] num_bytes + * Length of certificate in number of bytes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, + sl_se_cert_type_t cert_type, + void *cert, + uint32_t num_bytes); + +/***************************************************************************//** + * @brief + * Enter SE active mode. + * + * @details + * SE will enter active mode. This will ensure SE is not powered down between + * operations, at the expense of increased power consumption. + * + * @warning + * Active mode will prevent entry to EM2/3/4. To allow energy mode entry, exit + * active mode through @ref sl_se_exit_active_mode(). + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * @retval SL_STATUS_COMMAND_IS_INVALID when already in active mode + ******************************************************************************/ +sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx); + +/***************************************************************************//** + * @brief + * Exit SE active mode. + * + * @details + * SE will exit active mode. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * One of the following sl_status_t codes: + * @retval SL_STATUS_OK when the command was executed successfully + * @retval SL_STATUS_INVALID_PARAMETER when an invalid parameter was passed + * @retval SL_STATUS_COMMAND_IS_INVALID when already not in active mode + ******************************************************************************/ +sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx); + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sl_se_manager_util) +/// @} (end addtogroup sl_se_manager) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#endif // SL_SE_MANAGER_UTIL_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h index 96034b3..19bc7ef 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_features.h @@ -1,133 +1,133 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs SE Manager macros representing features. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_SE_MANAGER_FEATURES_H -#define SLI_SE_MANAGER_FEATURES_H - -#if !defined(__linux__) - #include "em_device.h" -#endif // !__linux__ - -#if defined(DOXYGEN) - -#undef _SILICON_LABS_SECURITY_FEATURE // Allow doxygen to include the SVH only features - -#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT -#define SLI_MAILBOX_COMMAND_SUPPORTED -#define SLI_VSE_MAILBOX_COMMAND_SUPPORTED -#define SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION -#define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE -#define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE -#define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE - -#else // DOXYGEN - -#if defined(__linux__) -// ---------------------------- HOST ---------------------------- // - -// The header is being used on a host system with Linux running on it, -// assume that the endpoint attached to the host system is a SVH type. - -#define SLI_SE_MANAGER_HOST_SYSTEM -#define SLI_MAILBOX_COMMAND_SUPPORTED - -#define _SILICON_LABS_SECURITY_FEATURE_SE (0) -#define _SILICON_LABS_SECURITY_FEATURE_VAULT (1) -#define _SILICON_LABS_SECURITY_FEATURE_ROT (2) -#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT - -#define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE - -#if defined(SLI_SE_MAJOR_VERSION_ONE) - #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE - -// EFR32xG23+ doesn't require padding of curve elements or other keys - #define SLI_SE_KEY_PADDING_REQUIRED - #define SLI_SE_P521_PADDING_BYTES (2u) - - #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (0u) -#elif defined(SLI_SE_MAJOR_VERSION_TWO) - #define SLI_SE_P521_PADDING_BYTES (0u) -// PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. - #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE - #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (1u) -#endif - -// Define the helper macros needed for the host system -#define __REV(num) (((num & 0xFF000000) >> 24) \ - | ((num & 0x00FF0000) >> 8) \ - | ((num & 0x0000FF00) << 8) \ - | ((num & 0x000000FF) << 24)) - -#elif defined(SEMAILBOX_PRESENT) -// --------------------------------- HSE --------------------------------- // - -#define SLI_MAILBOX_COMMAND_SUPPORTED - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 3)) -// Reading the latest cached tamper reset cause requires SE version 2.2.1 or above. - #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE -// The option to keep the tamper alive during sleep is only configurable for SE with major version 2 - #define SLI_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_AVAILABLE -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - #define SLI_SE_MAJOR_VERSION_ONE -#else - #define SLI_SE_MAJOR_VERSION_TWO -#endif - -#if defined(SLI_SE_MAJOR_VERSION_ONE) - #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE - -// EFR32xG23+ doesn't require padding of curve elements or other keys - #define SLI_SE_KEY_PADDING_REQUIRED - #define SLI_SE_P521_PADDING_BYTES (2u) - - #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (0u) -#elif defined(SLI_SE_MAJOR_VERSION_TWO) - #define SLI_SE_P521_PADDING_BYTES (0u) -// PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. - #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE - #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (1u) -#endif - -#elif defined(CRYPTOACC_PRESENT) -// --------------------------------- VSE --------------------------------- // - -#define SLI_VSE_MAILBOX_COMMAND_SUPPORTED - -#endif // __linux__ - -#endif // DOXYGEN - -#endif // SLI_SE_MANAGER_FEATURES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs SE Manager macros representing features. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_MANAGER_FEATURES_H +#define SLI_SE_MANAGER_FEATURES_H + +#if !defined(__linux__) + #include "em_device.h" +#endif // !__linux__ + +#if defined(DOXYGEN) + +#undef _SILICON_LABS_SECURITY_FEATURE // Allow doxygen to include the SVH only features + +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT +#define SLI_MAILBOX_COMMAND_SUPPORTED +#define SLI_VSE_MAILBOX_COMMAND_SUPPORTED +#define SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION +#define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE +#define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE +#define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE + +#else // DOXYGEN + +#if defined(__linux__) +// ---------------------------- HOST ---------------------------- // + +// The header is being used on a host system with Linux running on it, +// assume that the endpoint attached to the host system is a SVH type. + +#define SLI_SE_MANAGER_HOST_SYSTEM +#define SLI_MAILBOX_COMMAND_SUPPORTED + +#define _SILICON_LABS_SECURITY_FEATURE_SE (0) +#define _SILICON_LABS_SECURITY_FEATURE_VAULT (1) +#define _SILICON_LABS_SECURITY_FEATURE_ROT (2) +#define _SILICON_LABS_SECURITY_FEATURE _SILICON_LABS_SECURITY_FEATURE_VAULT + +#define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE + +#if defined(SLI_SE_MAJOR_VERSION_ONE) + #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE + +// EFR32xG23+ doesn't require padding of curve elements or other keys + #define SLI_SE_KEY_PADDING_REQUIRED + #define SLI_SE_P521_PADDING_BYTES (2u) + + #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (0u) +#elif defined(SLI_SE_MAJOR_VERSION_TWO) + #define SLI_SE_P521_PADDING_BYTES (0u) +// PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. + #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE + #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (1u) +#endif + +// Define the helper macros needed for the host system +#define __REV(num) (((num & 0xFF000000) >> 24) \ + | ((num & 0x00FF0000) >> 8) \ + | ((num & 0x0000FF00) << 8) \ + | ((num & 0x000000FF) << 24)) + +#elif defined(SEMAILBOX_PRESENT) +// --------------------------------- HSE --------------------------------- // + +#define SLI_MAILBOX_COMMAND_SUPPORTED + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 3)) +// Reading the latest cached tamper reset cause requires SE version 2.2.1 or above. + #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE +// The option to keep the tamper alive during sleep is only configurable for SE with major version 2 + #define SLI_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_AVAILABLE +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + #define SLI_SE_MAJOR_VERSION_ONE +#else + #define SLI_SE_MAJOR_VERSION_TWO +#endif + +#if defined(SLI_SE_MAJOR_VERSION_ONE) + #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE + +// EFR32xG23+ doesn't require padding of curve elements or other keys + #define SLI_SE_KEY_PADDING_REQUIRED + #define SLI_SE_P521_PADDING_BYTES (2u) + + #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (0u) +#elif defined(SLI_SE_MAJOR_VERSION_TWO) + #define SLI_SE_P521_PADDING_BYTES (0u) +// PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. + #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE + #define SLI_MINIMUM_REQUIRED_NUMBER_PARAMS (1u) +#endif + +#elif defined(CRYPTOACC_PRESENT) +// --------------------------------- VSE --------------------------------- // + +#define SLI_VSE_MAILBOX_COMMAND_SUPPORTED + +#endif // __linux__ + +#endif // DOXYGEN + +#endif // SLI_SE_MANAGER_FEATURES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h index 7d64343..c1894cb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/inc/sli_se_manager_internal.h @@ -1,429 +1,429 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager internal API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SE_MANAGER_INTERNAL_H -#define SE_MANAGER_INTERNAL_H - -#include "sli_se_manager_features.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#include "sl_status.h" -#include "em_se.h" -#include "sl_se_manager.h" -#include "sl_se_manager_key_handling.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -// ------------------------------- -// SE status codes - -/// Response status codes for the Secure Engine -#define SLI_SE_RESPONSE_MASK 0x000F0000UL -/// Command executed successfully or signature was successfully validated. -#define SLI_SE_RESPONSE_OK 0x00000000UL - -/// Command was not recognized as a valid command, or is not allowed in the -/// current context. -#define SLI_SE_RESPONSE_INVALID_COMMAND 0x00010000UL -/// User did not provide the required credentials to be allowed to execute the -/// command. -#define SLI_SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL -/// Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to -/// verify the given signature as being correct. -#define SLI_SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL -/// A command started in non-secure mode is trying to access secure memory. -#define SLI_SE_RESPONSE_BUS_ERROR 0x00040000UL -/// Internal error -#define SLI_SE_RESPONSE_INTERNAL_ERROR 0x00050000UL -/// An internal error was raised and the command did not execute. -#define SLI_SE_RESPONSE_CRYPTO_ERROR 0x00060000UL -/// One of the passed parameters is deemed invalid (e.g. out of bounds). -#define SLI_SE_RESPONSE_INVALID_PARAMETER 0x00070000UL -/// Failure while checking the host for secure boot -#define SLI_SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL -/// Failure during selftest -#define SLI_SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL -/// Feature/item not initialized or not present -#define SLI_SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL -/// Abort status code is given when no operation is attempted. -#define SLI_SE_RESPONSE_ABORT 0x00FF0000UL -#if defined(CRYPTOACC_PRESENT) -/// Root Code Mailbox is invalid. -#define SLI_SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL -#endif // CRYPTOACC_PRESENT - -// ------------------------------- -// SE command words -// Commands are grouped based on availability - -#define SLI_SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL -#define SLI_SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL -#define SLI_SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL -#define SLI_SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL -#define SLI_SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL -#define SLI_SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL - -#define SLI_SE_COMMAND_READ_OTP 0xFE040000UL - -#define SLI_SE_COMMAND_INIT_OTP 0xFF000001UL -#define SLI_SE_COMMAND_INIT_PUBKEY 0xFF070001UL -#define SLI_SE_COMMAND_READ_PUBKEY 0xFF080001UL - -#define SLI_SE_COMMAND_READ_PUBKEY 0xFF080001UL -#define SLI_SE_COMMAND_READ_OTP 0xFE040000UL - -#define SLI_SE_COMMAND_DBG_LOCK_APPLY 0x430C0000UL - -// Commands limited to SE devices -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - #define SLI_SE_COMMAND_CREATE_KEY 0x02000000UL - #define SLI_SE_COMMAND_READPUB_KEY 0x02010000UL - - #define SLI_SE_COMMAND_HASH 0x03000000UL - #define SLI_SE_COMMAND_HASHUPDATE 0x03010000UL - #define SLI_SE_COMMAND_HMAC 0x03020000UL - #define SLI_SE_COMMAND_HASHFINISH 0x03030000UL - - #define SLI_SE_COMMAND_AES_ENCRYPT 0x04000000UL - #define SLI_SE_COMMAND_AES_DECRYPT 0x04010000UL - #define SLI_SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL - #define SLI_SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL - #define SLI_SE_COMMAND_AES_CMAC 0x04040000UL - #define SLI_SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL - #define SLI_SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL - - #define SLI_SE_COMMAND_SIGNATURE_SIGN 0x06000000UL - #define SLI_SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL - #define SLI_SE_COMMAND_EDDSA_SIGN 0x06020000UL - #define SLI_SE_COMMAND_EDDSA_VERIFY 0x06030000UL - - #define SLI_SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL - - #define SLI_SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL - #define SLI_SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL - #define SLI_SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL - #define SLI_SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL - #define SLI_SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL - - #define SLI_SE_COMMAND_DH 0x0E000000UL - - #define SLI_SE_COMMAND_STATUS_SE_VERSION 0x43080000UL - #define SLI_SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL - #define SLI_SE_COMMAND_WRITE_USER_DATA 0x43090000UL - #define SLI_SE_COMMAND_ERASE_USER_DATA 0x430A0000UL - #define SLI_SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000UL - #define SLI_SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000UL - #define SLI_SE_COMMAND_DEVICE_ERASE 0x430F0000UL - #define SLI_SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000UL - #define SLI_SE_COMMAND_DBG_LOCK_STATUS 0x43110000UL - #define SLI_SE_COMMAND_DBG_SET_RESTRICTIONS 0x43120000UL - #define SLI_SE_COMMAND_PROTECTED_REGISTER 0x43210000UL -#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) -// SLI_SE_COMMAND_STATUS_READ_RSTCAUSE is only available on xG21 devices (series-2-config-1) - #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE 0x43220000UL -#endif // SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE - #define SLI_SE_COMMAND_READ_USER_CERT_SIZE 0x43FA0000UL - #define SLI_SE_COMMAND_READ_USER_CERT 0x43FB0000UL - - #define SLI_SE_COMMAND_ENTER_ACTIVE_MODE 0x45000000UL - #define SLI_SE_COMMAND_EXIT_ACTIVE_MODE 0x45010000UL - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define SLI_SE_COMMAND_ATTEST_PSA_IAT 0x0A030000UL - #define SLI_SE_COMMAND_ATTEST_CONFIG 0x0A040000UL -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT) - - #define SLI_SE_COMMAND_GET_CHALLENGE 0xFD000001UL - #define SLI_SE_COMMAND_ROLL_CHALLENGE 0xFD000101UL - #define SLI_SE_COMMAND_OPEN_DEBUG 0xFD010001UL - - #define SLI_SE_COMMAND_READ_SERIAL 0xFE000000UL - #define SLI_SE_COMMAND_GET_STATUS 0xFE010000UL - #define SLI_SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL - #define SLI_SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL - #define SLI_SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL - #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE 0xFE050000UL - - #define SLI_SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL - #define SLI_SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL - #define SLI_SE_COMMAND_INIT_AES_128_KEY 0xFF0B0001UL -#endif // SLI_MAILBOX_COMMAND_SUPPORTED - -// Commands limited to SE Vault High devices -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define SLI_SE_COMMAND_WRAP_KEY 0x01000000UL - #define SLI_SE_COMMAND_UNWRAP_KEY 0x01020000UL - #define SLI_SE_COMMAND_DELETE_KEY 0x01050000UL - #define SLI_SE_COMMAND_TRANSFER_KEY 0x01060000UL - - #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC 0x02020002UL - #define SLI_SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL - #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC 0x02020010UL - - #define SLI_SE_COMMAND_CHACHAPOLY_ENCRYPT 0x0C000000UL - #define SLI_SE_COMMAND_CHACHAPOLY_DECRYPT 0x0C010000UL - #define SLI_SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL - #define SLI_SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL - #define SLI_SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL - - #define SLI_SE_COMMAND_DISABLE_TAMPER 0xFD020001UL -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - -// ------------------------------- -// SE command options -// Commands are grouped based on availability - -/// Secure boot pubkey -#define SLI_SE_KEY_TYPE_BOOT 0x00000100UL -/// Secure authorization (debug) pubkey -#define SLI_SE_KEY_TYPE_AUTH 0x00000200UL - -// Options limited to SE devices -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -/// Root pubkey - #define SLI_SE_KEY_TYPE_ROOT 0x00000300UL -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Attestation pubkey - #define SLI_SE_KEY_TYPE_ATTEST 0x00000400UL -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT -/// BGL encryption key - #define SLI_SE_IMMUTABLE_KEY_TYPE_AES_128 0x00000500UL - -/// Use MD5 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_MD5 0x00000100UL -/// Use SHA1 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL -/// Use SHA224 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL -/// Use SHA256 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL - -/// Execute algorithm in ECB mode - #define SLI_SE_COMMAND_OPTION_MODE_ECB 0x00000100UL -/// Execute algorithm in CBC mode - #define SLI_SE_COMMAND_OPTION_MODE_CBC 0x00000200UL -/// Execute algorithm in CTR mode - #define SLI_SE_COMMAND_OPTION_MODE_CTR 0x00000300UL -/// Execute algorithm in CFB mode - #define SLI_SE_COMMAND_OPTION_MODE_CFB 0x00000400UL - -/// Run the whole algorithm, all data present - #define SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL -/// Start the algorithm, but get a context to later add more data - #define SLI_SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL -/// End the algorithm, get the result - #define SLI_SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL -/// Add more data input to the algorithm. Need to supply previous context, -/// and get a context back - #define SLI_SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL - -/// Magic paramater for deleting user data - #define SLI_SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL - #define SLI_SE_COMMAND_CERT_BATCH 0x00000100UL - #define SLI_SE_COMMAND_CERT_SE 0x00000200UL - #define SLI_SE_COMMAND_CERT_HOST 0x00000300UL - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/// Use SHA384 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL -/// Use SHA512 as hash algorithm - #define SLI_SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT -#endif // SLI_MAILBOX_COMMAND_SUPPORTED - -// ------------------------------- -// Other defines - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -// Due to a problem with the countermeasures applied to -// accelerated point multiplication over elliptic curves, -// it is possible that random errors are encountered (this -// is extremely unilkely for truly random keys). -// As a workaround for this, the affected commands will -// retry the operation in order to reduce the probability -// that the error code was returned incorrectly. This helps -// lower the error probability further when using purposely -// small or large scalars, for example during testing. -#define SLI_SE_MAX_POINT_MULT_RETRIES 3U -#endif - -// ------------------------------- -// Function-like macros - -/***************************************************************************//** - * @brief - * Helper macro to init/reset the SE command struct of an SE command context - * - * @param[in] cmd_ctx - * Pointer to SE context containing the command to initialize/reset - * - * @param[out] command_word - * Command word to set in the SE command. - * - ******************************************************************************/ -#define sli_se_command_init(cmd_ctx, command_word) \ - cmd_ctx->command.command = command_word; \ - cmd_ctx->command.data_in = NULL; \ - cmd_ctx->command.data_out = NULL; \ - cmd_ctx->command.num_parameters = 0; - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -/***************************************************************************//** - * @brief - * Helper macros to add key parameters and input/output blocks to SE commands - * - * @param[in] cmd_ctx - * Pointer to SE context - * @param[in] key - * Pointer to sl_se_key_descriptor_t structure - * @param[out] status - * SL_Status_T - * - ******************************************************************************/ - -// Add keyspec to command for given key -#define sli_add_key_parameters(cmd_ctx, key, status) { \ - uint32_t keyspec; \ - (status) = sli_se_key_to_keyspec((key), &keyspec); \ - if ((status) != SL_STATUS_OK) { \ - return (status); \ - } \ - SE_addParameter(&cmd_ctx->command, keyspec); \ -} - -// Add key metadata buffers to command for given key -#define sli_add_key_metadata(cmd_ctx, key, status) \ - /* Auth data */ \ - SE_DataTransfer_t auth_buffer; \ - (status) = sli_se_get_auth_buffer((key), &auth_buffer); \ - if ((status) != SL_STATUS_OK) { \ - return (status); \ - } \ - SE_addDataInput(&cmd_ctx->command, &auth_buffer); - -// Add key metadata buffers with custom auth buffer to command for given key -#define sli_add_key_metadata_custom(cmd_ctx, auth_data_buf, key, status) \ - /* Auth data */ \ - SE_DataTransfer_t auth_data_buf; \ - (status) = sli_se_get_auth_buffer((key), &auth_data_buf); \ - if ((status) != SL_STATUS_OK) { \ - return (status); \ - } \ - SE_addDataInput(&cmd_ctx->command, &auth_data_buf); - -// Add key input buffer to given command -#define sli_add_key_input(cmd_ctx, key, status) \ - SE_DataTransfer_t key_input_buffer; \ - (status) = sli_se_get_key_input_output((key), &key_input_buffer); \ - if ((status) != SL_STATUS_OK) { \ - return (status); \ - } \ - SE_addDataInput(&cmd_ctx->command, &key_input_buffer); - -// Add Key output buffer to given command -#define sli_add_key_output(cmd_ctx, key, status) \ - SE_DataTransfer_t key_output_buffer; \ - (status) = sli_se_get_key_input_output((key), &key_output_buffer); \ - if ((status) != SL_STATUS_OK) { \ - return (status); \ - } \ - SE_addDataOutput(&cmd_ctx->command, &key_output_buffer); -#endif // SLI_MAILBOX_COMMAND_SUPPORTED - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -sl_status_t sli_se_to_sl_status(SE_Response_t res); - -/***************************************************************************//** - * @brief - * Take the SE lock in order to synchronize multiple threads calling into - * the SE Manager API concurrently. - * - * @return - * SL_STATUS_OK when successful, or else error code. - ******************************************************************************/ -sl_status_t sli_se_lock_acquire(void); - -/***************************************************************************//** - * @brief - * Give the SE lock in order to synchronize multiple threads calling into - * the SE Manager API concurrently. - * - * @return - * SL_STATUS_OK when successful, or else error code. - ******************************************************************************/ -sl_status_t sli_se_lock_release(void); - -/***************************************************************************//** - * @brief - * Execute and wait for mailbox command to complete. - * - * @param[in] cmd_ctx - * Pointer to an SE command context object. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx); - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -// Key handling helper functions -sl_status_t sli_key_get_storage_size(const sl_se_key_descriptor_t* key, - uint32_t *storage_size); -sl_status_t sli_key_get_size(const sl_se_key_descriptor_t* key, uint32_t* size); -sl_status_t sli_key_check_equivalent(const sl_se_key_descriptor_t* key_1, - const sl_se_key_descriptor_t* key_2, - bool check_key_flag, - bool public_export); - -sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t* key, - uint32_t* keyspec); -sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, - sl_se_key_descriptor_t* key); -sl_status_t sli_se_get_auth_buffer(const sl_se_key_descriptor_t* key, - SE_DataTransfer_t* auth_buffer); -sl_status_t sli_se_get_key_input_output(const sl_se_key_descriptor_t* key, - SE_DataTransfer_t* buffer); -#endif // SLI_MAILBOX_COMMAND_SUPPORTED - -#ifdef __cplusplus -} -#endif - -#endif /* defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) */ - -#endif /* SE_MANAGER_INTERNAL_H */ +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager internal API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SE_MANAGER_INTERNAL_H +#define SE_MANAGER_INTERNAL_H + +#include "sli_se_manager_features.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#include "sl_status.h" +#include "em_se.h" +#include "sl_se_manager.h" +#include "sl_se_manager_key_handling.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +// ------------------------------- +// SE status codes + +/// Response status codes for the Secure Engine +#define SLI_SE_RESPONSE_MASK 0x000F0000UL +/// Command executed successfully or signature was successfully validated. +#define SLI_SE_RESPONSE_OK 0x00000000UL + +/// Command was not recognized as a valid command, or is not allowed in the +/// current context. +#define SLI_SE_RESPONSE_INVALID_COMMAND 0x00010000UL +/// User did not provide the required credentials to be allowed to execute the +/// command. +#define SLI_SE_RESPONSE_AUTHORIZATION_ERROR 0x00020000UL +/// Signature validation command (e.g. SE_COMMAND_SIGNATURE_VERIFY) failed to +/// verify the given signature as being correct. +#define SLI_SE_RESPONSE_INVALID_SIGNATURE 0x00030000UL +/// A command started in non-secure mode is trying to access secure memory. +#define SLI_SE_RESPONSE_BUS_ERROR 0x00040000UL +/// Internal error +#define SLI_SE_RESPONSE_INTERNAL_ERROR 0x00050000UL +/// An internal error was raised and the command did not execute. +#define SLI_SE_RESPONSE_CRYPTO_ERROR 0x00060000UL +/// One of the passed parameters is deemed invalid (e.g. out of bounds). +#define SLI_SE_RESPONSE_INVALID_PARAMETER 0x00070000UL +/// Failure while checking the host for secure boot +#define SLI_SE_RESPONSE_SECUREBOOT_ERROR 0x00090000UL +/// Failure during selftest +#define SLI_SE_RESPONSE_SELFTEST_ERROR 0x000A0000UL +/// Feature/item not initialized or not present +#define SLI_SE_RESPONSE_NOT_INITIALIZED 0x000B0000UL +/// Abort status code is given when no operation is attempted. +#define SLI_SE_RESPONSE_ABORT 0x00FF0000UL +#if defined(CRYPTOACC_PRESENT) +/// Root Code Mailbox is invalid. +#define SLI_SE_RESPONSE_MAILBOX_INVALID 0x00FE0000UL +#endif // CRYPTOACC_PRESENT + +// ------------------------------- +// SE command words +// Commands are grouped based on availability + +#define SLI_SE_COMMAND_CHECK_SE_IMAGE 0x43020000UL +#define SLI_SE_COMMAND_APPLY_SE_IMAGE 0x43030000UL +#define SLI_SE_COMMAND_STATUS_SE_IMAGE 0x43040000UL +#define SLI_SE_COMMAND_CHECK_HOST_IMAGE 0x43050001UL +#define SLI_SE_COMMAND_APPLY_HOST_IMAGE 0x43060001UL +#define SLI_SE_COMMAND_STATUS_HOST_IMAGE 0x43070000UL + +#define SLI_SE_COMMAND_READ_OTP 0xFE040000UL + +#define SLI_SE_COMMAND_INIT_OTP 0xFF000001UL +#define SLI_SE_COMMAND_INIT_PUBKEY 0xFF070001UL +#define SLI_SE_COMMAND_READ_PUBKEY 0xFF080001UL + +#define SLI_SE_COMMAND_READ_PUBKEY 0xFF080001UL +#define SLI_SE_COMMAND_READ_OTP 0xFE040000UL + +#define SLI_SE_COMMAND_DBG_LOCK_APPLY 0x430C0000UL + +// Commands limited to SE devices +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + #define SLI_SE_COMMAND_CREATE_KEY 0x02000000UL + #define SLI_SE_COMMAND_READPUB_KEY 0x02010000UL + + #define SLI_SE_COMMAND_HASH 0x03000000UL + #define SLI_SE_COMMAND_HASHUPDATE 0x03010000UL + #define SLI_SE_COMMAND_HMAC 0x03020000UL + #define SLI_SE_COMMAND_HASHFINISH 0x03030000UL + + #define SLI_SE_COMMAND_AES_ENCRYPT 0x04000000UL + #define SLI_SE_COMMAND_AES_DECRYPT 0x04010000UL + #define SLI_SE_COMMAND_AES_GCM_ENCRYPT 0x04020000UL + #define SLI_SE_COMMAND_AES_GCM_DECRYPT 0x04030000UL + #define SLI_SE_COMMAND_AES_CMAC 0x04040000UL + #define SLI_SE_COMMAND_AES_CCM_ENCRYPT 0x04050000UL + #define SLI_SE_COMMAND_AES_CCM_DECRYPT 0x04060000UL + + #define SLI_SE_COMMAND_SIGNATURE_SIGN 0x06000000UL + #define SLI_SE_COMMAND_SIGNATURE_VERIFY 0x06010000UL + #define SLI_SE_COMMAND_EDDSA_SIGN 0x06020000UL + #define SLI_SE_COMMAND_EDDSA_VERIFY 0x06030000UL + + #define SLI_SE_COMMAND_TRNG_GET_RANDOM 0x07000000UL + + #define SLI_SE_COMMAND_JPAKE_R1_GENERATE 0x0B000000UL + #define SLI_SE_COMMAND_JPAKE_R1_VERIFY 0x0B000100UL + #define SLI_SE_COMMAND_JPAKE_R2_GENERATE 0x0B010000UL + #define SLI_SE_COMMAND_JPAKE_R2_VERIFY 0x0B010100UL + #define SLI_SE_COMMAND_JPAKE_GEN_SESSIONKEY 0x0B020000UL + + #define SLI_SE_COMMAND_DH 0x0E000000UL + + #define SLI_SE_COMMAND_STATUS_SE_VERSION 0x43080000UL + #define SLI_SE_COMMAND_STATUS_OTP_VERSION 0x43080100UL + #define SLI_SE_COMMAND_WRITE_USER_DATA 0x43090000UL + #define SLI_SE_COMMAND_ERASE_USER_DATA 0x430A0000UL + #define SLI_SE_COMMAND_DBG_LOCK_ENABLE_SECURE 0x430D0000UL + #define SLI_SE_COMMAND_DBG_LOCK_DISABLE_SECURE 0x430E0000UL + #define SLI_SE_COMMAND_DEVICE_ERASE 0x430F0000UL + #define SLI_SE_COMMAND_DEVICE_ERASE_DISABLE 0x43100000UL + #define SLI_SE_COMMAND_DBG_LOCK_STATUS 0x43110000UL + #define SLI_SE_COMMAND_DBG_SET_RESTRICTIONS 0x43120000UL + #define SLI_SE_COMMAND_PROTECTED_REGISTER 0x43210000UL +#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) +// SLI_SE_COMMAND_STATUS_READ_RSTCAUSE is only available on xG21 devices (series-2-config-1) + #define SLI_SE_COMMAND_STATUS_READ_RSTCAUSE 0x43220000UL +#endif // SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE + #define SLI_SE_COMMAND_READ_USER_CERT_SIZE 0x43FA0000UL + #define SLI_SE_COMMAND_READ_USER_CERT 0x43FB0000UL + + #define SLI_SE_COMMAND_ENTER_ACTIVE_MODE 0x45000000UL + #define SLI_SE_COMMAND_EXIT_ACTIVE_MODE 0x45010000UL + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SLI_SE_COMMAND_ATTEST_PSA_IAT 0x0A030000UL + #define SLI_SE_COMMAND_ATTEST_CONFIG 0x0A040000UL +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT) + + #define SLI_SE_COMMAND_GET_CHALLENGE 0xFD000001UL + #define SLI_SE_COMMAND_ROLL_CHALLENGE 0xFD000101UL + #define SLI_SE_COMMAND_OPEN_DEBUG 0xFD010001UL + + #define SLI_SE_COMMAND_READ_SERIAL 0xFE000000UL + #define SLI_SE_COMMAND_GET_STATUS 0xFE010000UL + #define SLI_SE_COMMAND_READ_PUBKEYBOOT 0xFE020001UL + #define SLI_SE_COMMAND_SET_UPGRADEFLAG_SE 0xFE030000UL + #define SLI_SE_COMMAND_SET_UPGRADEFLAG_HOST 0xFE030001UL + #define SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE 0xFE050000UL + + #define SLI_SE_COMMAND_INIT_PUBKEY_SIGNATURE 0xFF090001UL + #define SLI_SE_COMMAND_READ_PUBKEY_SIGNATURE 0xFF0A0001UL + #define SLI_SE_COMMAND_INIT_AES_128_KEY 0xFF0B0001UL +#endif // SLI_MAILBOX_COMMAND_SUPPORTED + +// Commands limited to SE Vault High devices +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SLI_SE_COMMAND_WRAP_KEY 0x01000000UL + #define SLI_SE_COMMAND_UNWRAP_KEY 0x01020000UL + #define SLI_SE_COMMAND_DELETE_KEY 0x01050000UL + #define SLI_SE_COMMAND_TRANSFER_KEY 0x01060000UL + + #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC 0x02020002UL + #define SLI_SE_COMMAND_DERIVE_KEY_HKDF 0x02020003UL + #define SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC 0x02020010UL + + #define SLI_SE_COMMAND_CHACHAPOLY_ENCRYPT 0x0C000000UL + #define SLI_SE_COMMAND_CHACHAPOLY_DECRYPT 0x0C010000UL + #define SLI_SE_COMMAND_CHACHA20_ENCRYPT 0x0C020000UL + #define SLI_SE_COMMAND_CHACHA20_DECRYPT 0x0C030000UL + #define SLI_SE_COMMAND_POLY1305_KEY_MAC 0x0C040000UL + + #define SLI_SE_COMMAND_DISABLE_TAMPER 0xFD020001UL +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + +// ------------------------------- +// SE command options +// Commands are grouped based on availability + +/// Secure boot pubkey +#define SLI_SE_KEY_TYPE_BOOT 0x00000100UL +/// Secure authorization (debug) pubkey +#define SLI_SE_KEY_TYPE_AUTH 0x00000200UL + +// Options limited to SE devices +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/// Root pubkey + #define SLI_SE_KEY_TYPE_ROOT 0x00000300UL +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Attestation pubkey + #define SLI_SE_KEY_TYPE_ATTEST 0x00000400UL +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT +/// BGL encryption key + #define SLI_SE_IMMUTABLE_KEY_TYPE_AES_128 0x00000500UL + +/// Use MD5 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_MD5 0x00000100UL +/// Use SHA1 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_SHA1 0x00000200UL +/// Use SHA224 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_SHA224 0x00000300UL +/// Use SHA256 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_SHA256 0x00000400UL + +/// Execute algorithm in ECB mode + #define SLI_SE_COMMAND_OPTION_MODE_ECB 0x00000100UL +/// Execute algorithm in CBC mode + #define SLI_SE_COMMAND_OPTION_MODE_CBC 0x00000200UL +/// Execute algorithm in CTR mode + #define SLI_SE_COMMAND_OPTION_MODE_CTR 0x00000300UL +/// Execute algorithm in CFB mode + #define SLI_SE_COMMAND_OPTION_MODE_CFB 0x00000400UL + +/// Run the whole algorithm, all data present + #define SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE 0x00000000UL +/// Start the algorithm, but get a context to later add more data + #define SLI_SE_COMMAND_OPTION_CONTEXT_START 0x00000001UL +/// End the algorithm, get the result + #define SLI_SE_COMMAND_OPTION_CONTEXT_END 0x00000002UL +/// Add more data input to the algorithm. Need to supply previous context, +/// and get a context back + #define SLI_SE_COMMAND_OPTION_CONTEXT_ADD 0x00000003UL + +/// Magic paramater for deleting user data + #define SLI_SE_COMMAND_OPTION_ERASE_UD 0xDE1E7EADUL + #define SLI_SE_COMMAND_CERT_BATCH 0x00000100UL + #define SLI_SE_COMMAND_CERT_SE 0x00000200UL + #define SLI_SE_COMMAND_CERT_HOST 0x00000300UL + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/// Use SHA384 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_SHA384 0x00000500UL +/// Use SHA512 as hash algorithm + #define SLI_SE_COMMAND_OPTION_HASH_SHA512 0x00000600UL +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT +#endif // SLI_MAILBOX_COMMAND_SUPPORTED + +// ------------------------------- +// Other defines + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +// Due to a problem with the countermeasures applied to +// accelerated point multiplication over elliptic curves, +// it is possible that random errors are encountered (this +// is extremely unilkely for truly random keys). +// As a workaround for this, the affected commands will +// retry the operation in order to reduce the probability +// that the error code was returned incorrectly. This helps +// lower the error probability further when using purposely +// small or large scalars, for example during testing. +#define SLI_SE_MAX_POINT_MULT_RETRIES 3U +#endif + +// ------------------------------- +// Function-like macros + +/***************************************************************************//** + * @brief + * Helper macro to init/reset the SE command struct of an SE command context + * + * @param[in] cmd_ctx + * Pointer to SE context containing the command to initialize/reset + * + * @param[out] command_word + * Command word to set in the SE command. + * + ******************************************************************************/ +#define sli_se_command_init(cmd_ctx, command_word) \ + cmd_ctx->command.command = command_word; \ + cmd_ctx->command.data_in = NULL; \ + cmd_ctx->command.data_out = NULL; \ + cmd_ctx->command.num_parameters = 0; + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @brief + * Helper macros to add key parameters and input/output blocks to SE commands + * + * @param[in] cmd_ctx + * Pointer to SE context + * @param[in] key + * Pointer to sl_se_key_descriptor_t structure + * @param[out] status + * SL_Status_T + * + ******************************************************************************/ + +// Add keyspec to command for given key +#define sli_add_key_parameters(cmd_ctx, key, status) { \ + uint32_t keyspec; \ + (status) = sli_se_key_to_keyspec((key), &keyspec); \ + if ((status) != SL_STATUS_OK) { \ + return (status); \ + } \ + SE_addParameter(&cmd_ctx->command, keyspec); \ +} + +// Add key metadata buffers to command for given key +#define sli_add_key_metadata(cmd_ctx, key, status) \ + /* Auth data */ \ + SE_DataTransfer_t auth_buffer; \ + (status) = sli_se_get_auth_buffer((key), &auth_buffer); \ + if ((status) != SL_STATUS_OK) { \ + return (status); \ + } \ + SE_addDataInput(&cmd_ctx->command, &auth_buffer); + +// Add key metadata buffers with custom auth buffer to command for given key +#define sli_add_key_metadata_custom(cmd_ctx, auth_data_buf, key, status) \ + /* Auth data */ \ + SE_DataTransfer_t auth_data_buf; \ + (status) = sli_se_get_auth_buffer((key), &auth_data_buf); \ + if ((status) != SL_STATUS_OK) { \ + return (status); \ + } \ + SE_addDataInput(&cmd_ctx->command, &auth_data_buf); + +// Add key input buffer to given command +#define sli_add_key_input(cmd_ctx, key, status) \ + SE_DataTransfer_t key_input_buffer; \ + (status) = sli_se_get_key_input_output((key), &key_input_buffer); \ + if ((status) != SL_STATUS_OK) { \ + return (status); \ + } \ + SE_addDataInput(&cmd_ctx->command, &key_input_buffer); + +// Add Key output buffer to given command +#define sli_add_key_output(cmd_ctx, key, status) \ + SE_DataTransfer_t key_output_buffer; \ + (status) = sli_se_get_key_input_output((key), &key_output_buffer); \ + if ((status) != SL_STATUS_OK) { \ + return (status); \ + } \ + SE_addDataOutput(&cmd_ctx->command, &key_output_buffer); +#endif // SLI_MAILBOX_COMMAND_SUPPORTED + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +sl_status_t sli_se_to_sl_status(SE_Response_t res); + +/***************************************************************************//** + * @brief + * Take the SE lock in order to synchronize multiple threads calling into + * the SE Manager API concurrently. + * + * @return + * SL_STATUS_OK when successful, or else error code. + ******************************************************************************/ +sl_status_t sli_se_lock_acquire(void); + +/***************************************************************************//** + * @brief + * Give the SE lock in order to synchronize multiple threads calling into + * the SE Manager API concurrently. + * + * @return + * SL_STATUS_OK when successful, or else error code. + ******************************************************************************/ +sl_status_t sli_se_lock_release(void); + +/***************************************************************************//** + * @brief + * Execute and wait for mailbox command to complete. + * + * @param[in] cmd_ctx + * Pointer to an SE command context object. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx); + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +// Key handling helper functions +sl_status_t sli_key_get_storage_size(const sl_se_key_descriptor_t* key, + uint32_t *storage_size); +sl_status_t sli_key_get_size(const sl_se_key_descriptor_t* key, uint32_t* size); +sl_status_t sli_key_check_equivalent(const sl_se_key_descriptor_t* key_1, + const sl_se_key_descriptor_t* key_2, + bool check_key_flag, + bool public_export); + +sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t* key, + uint32_t* keyspec); +sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, + sl_se_key_descriptor_t* key); +sl_status_t sli_se_get_auth_buffer(const sl_se_key_descriptor_t* key, + SE_DataTransfer_t* auth_buffer); +sl_status_t sli_se_get_key_input_output(const sl_se_key_descriptor_t* key, + SE_DataTransfer_t* buffer); +#endif // SLI_MAILBOX_COMMAND_SUPPORTED + +#ifdef __cplusplus +} +#endif + +#endif /* defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) */ + +#endif /* SE_MANAGER_INTERNAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager.c index 5fd167f..d13cf93 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager.c @@ -1,516 +1,516 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) -#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include "sl_assert.h" -#if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) -#include "em_bus.h" -#endif -#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) -#include "sli_se_manager_osal.h" -#endif - -#include - -/// @addtogroup sl_se_managers -/// @{ - -// ----------------------------------------------------------------------------- -// Locals - -#if defined(SL_SE_MANAGER_THREADING) \ - || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - -// Flag to indicate that the SE Manager is initialized or not. -static volatile bool se_manager_initialized = false; - - #if defined(SL_SE_MANAGER_THREADING) -// Lock mutex for synchronizing multiple threads calling into the -// SE Manager API. -static se_manager_osal_mutex_t se_lock = { 0 }; - - #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START \ - int32_t kernel_lock_state = 0; \ - osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); \ - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ - kernel_lock_state = se_manager_osal_kernel_lock(); \ - if (kernel_lock_state < 0) { \ - return SL_STATUS_FAIL; \ - } \ - } - - #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END \ - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ - if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { \ - return SL_STATUS_FAIL; \ - } \ - } - - #endif // SL_SE_MANAGER_THREADING - - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) -// SE command completion. -static se_manager_osal_completion_t se_command_completion; -// SE mailbox command response code. This value is read from the SEMAILBOX -// in ISR in order to clear the command complete interrupt condition. -static SE_Response_t se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; - #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION - -#endif // #if defined (SL_SE_MANAGER_THREADING) -// || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - -// ----------------------------------------------------------------------------- -// Global functions - -/***************************************************************************//** - * Initialize the SE Manager. - ******************************************************************************/ -sl_status_t sl_se_init(void) -{ - sl_status_t ret = SL_STATUS_OK; - #if defined (SL_SE_MANAGER_THREADING) \ - || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START - #endif - - if ( !se_manager_initialized ) { - #if defined(SL_SE_MANAGER_THREADING) - // Initialize SE lock - ret = se_manager_osal_init_mutex(&se_lock); - #endif - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - if (ret == SL_STATUS_OK) { - // Initialize command completion object. - ret = se_manager_osal_init_completion(&se_command_completion); - if (ret == SL_STATUS_OK) { - // Enable SE RX mailbox interrupt in NVIC, but not in SEMAILBOX - // which will be enabled if the yield parameter in - // sli_se_execute_and_wait is true. - NVIC_SetPriority(SEMBRX_IRQn, SE_MANAGER_SEMBRX_IRQ_PRIORITY); - NVIC_EnableIRQ(SEMBRX_IRQn); - } - } - #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION - if (ret == SL_STATUS_OK) { - se_manager_initialized = true; - } - } - - #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END - #endif - - #endif // #if defined (SL_SE_MANAGER_THREADING) - // || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - return ret; -} - -/***************************************************************************//** - * Denitialize the SE Manager. - ******************************************************************************/ -sl_status_t sl_se_deinit(void) -{ - sl_status_t ret = SL_STATUS_OK; - - #if defined (SL_SE_MANAGER_THREADING) \ - || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START - #endif - - if ( se_manager_initialized ) { - // We need to exit the critical section in case the SE lock is held by a - // thread, and we want to take it before de-initializing. - #if defined(SL_SE_MANAGER_THREADING) - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END - #endif - - // Acquire the SE lock to make sure no thread is executing SE commands - // when we de-initialize. - ret = sli_se_lock_acquire(); - if (ret != SL_STATUS_OK) { - return ret; - } - - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - // Disable SE RX mailbox interrupt in NVIC. - NVIC_ClearPendingIRQ(SEMBRX_IRQn); - NVIC_DisableIRQ(SEMBRX_IRQn); - // Free command completion object. - ret = se_manager_osal_free_completion(&se_command_completion); - #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION - - #if defined(SL_SE_MANAGER_THREADING) - if (ret == SL_STATUS_OK) { - // Free the SE lock mutex - ret = se_manager_osal_free_mutex(&se_lock); - } - #endif - - // Mark the SE Manager as un-initialized. - se_manager_initialized = false; - } - #if defined(SL_SE_MANAGER_THREADING) - else { - SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END - } - #endif - - #endif // #if defined (SL_SE_MANAGER_THREADING) - // || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - return ret; -} - -/***************************************************************************//** - * @brief - * Translate SE response codes to sl_status_t codes. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sli_se_to_sl_status(SE_Response_t res) -{ - switch (res) { - case SLI_SE_RESPONSE_OK: - return SL_STATUS_OK; - case SLI_SE_RESPONSE_INVALID_COMMAND: - return SL_STATUS_COMMAND_IS_INVALID; - case SLI_SE_RESPONSE_AUTHORIZATION_ERROR: - return SL_STATUS_INVALID_CREDENTIALS; - case SLI_SE_RESPONSE_INVALID_SIGNATURE: - return SL_STATUS_INVALID_SIGNATURE; - case SLI_SE_RESPONSE_BUS_ERROR: - return SL_STATUS_BUS_ERROR; - case SLI_SE_RESPONSE_INTERNAL_ERROR: - return SL_STATUS_FAIL; - case SLI_SE_RESPONSE_CRYPTO_ERROR: - return SL_STATUS_FAIL; - case SLI_SE_RESPONSE_INVALID_PARAMETER: - return SL_STATUS_INVALID_PARAMETER; - case SLI_SE_RESPONSE_ABORT: - return SL_STATUS_ABORT; - case SLI_SE_RESPONSE_SELFTEST_ERROR: - return SL_STATUS_INITIALIZATION; - case SLI_SE_RESPONSE_NOT_INITIALIZED: - return SL_STATUS_NOT_INITIALIZED; -#if defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - case SLI_SE_RESPONSE_MAILBOX_INVALID: - return SL_STATUS_COMMAND_IS_INVALID; -#endif - default: - // Assert we do not get a bad SE response code. - EFM_ASSERT(false); - return SL_STATUS_FAIL; - } -} - -/***************************************************************************//** - * Acquire the SE lock for exclusive access if necessary (thread mode). - * Enable the SEMAILBOX clock if necessary. - ******************************************************************************/ -sl_status_t sli_se_lock_acquire(void) -{ - #if defined(SL_SE_MANAGER_THREADING) - sl_status_t status = se_manager_osal_take_mutex(&se_lock); - #else - sl_status_t status = SL_STATUS_OK; - #endif - #if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) - if (status == SL_STATUS_OK) { - BUS_RegBitWrite(&CMU->CLKEN1, _CMU_CLKEN1_SEMAILBOXHOST_SHIFT, 1); - } - #endif - return status; -} - -/***************************************************************************//** - * Release the SE lock if necessary (thread mode). - * Disable the SEMAILBOX clock if necessary. - ******************************************************************************/ -sl_status_t sli_se_lock_release(void) -{ - #if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) - BUS_RegBitWrite(&CMU->CLKEN1, _CMU_CLKEN1_SEMAILBOXHOST_SHIFT, 0); - #endif - #if defined(SL_SE_MANAGER_THREADING) - return se_manager_osal_give_mutex(&se_lock); - #else - return SL_STATUS_OK; - #endif -} - -#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - -/***************************************************************************//** - * @brief - * SE Mailbox Interrupt Service Routine - ******************************************************************************/ -void SEMBRX_IRQHandler(void) -{ - sl_status_t status; - // Check if the SE mailbox is the source of the interrupt. - if (SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT) { - // Signal SE mailbox completion. - status = se_manager_osal_complete(&se_command_completion); - EFM_ASSERT(status == SL_STATUS_OK); - } - // Get command response (clears interrupt condition in SEMAILBOX) - se_manager_command_response = SE_readCommandResponse(); - // Clear interrupt condition in NVIC - NVIC_ClearPendingIRQ(SEMBRX_IRQn); -} - -#endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - -/***************************************************************************//** - * Set the yield attribute of the SE command context object. - ******************************************************************************/ -sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx, - bool yield) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - cmd_ctx->yield = yield; - return SL_STATUS_OK; - #else - if (yield) { - return SL_STATUS_NOT_AVAILABLE; - } else { - (void) cmd_ctx; - return SL_STATUS_OK; - } - #endif -} - -/***************************************************************************//** - * @brief - * Execute and wait for SE mailbox command to complete. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && !defined(SLI_SE_MANAGER_HOST_SYSTEM) -sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) -{ - sl_status_t status; - SE_Response_t command_response; - - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Execute SE mailbox command - SE_executeCommand(&cmd_ctx->command); - - #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - if (cmd_ctx->yield) { - // Enable SEMAILBOX RXINT interrupt - SE_enableInterrupt(SEMAILBOX_CONFIGURATION_RXINTEN); - - // Yield and Wait for the command completion signal - status = se_manager_osal_wait_completion(&se_command_completion, - SE_MANAGER_OSAL_WAIT_FOREVER); - - // Disable SEMAILBOX RXINT interrupt. - SE_disableInterrupt(SEMAILBOX_CONFIGURATION_RXINTEN); - - if (status != SL_STATUS_OK) { - return status; - } - - // Get response which is read in the ISR to clear interrupt condition. - command_response = se_manager_command_response; - // Default to an error. - se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; - } else { - // Wait for command completion and get command response - command_response = SE_readCommandResponse(); - } - - #else // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - // Wait for command completion and get command response - command_response = SE_readCommandResponse(); - - #endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) - - // Release SE lock - status = sli_se_lock_release(); - - // Return sl_status_t code. - if (command_response == SLI_SE_RESPONSE_OK) { - return status; - } else { - // Convert from SE_Response_t to sl_status_t code and return. - return sli_se_to_sl_status(command_response); - } -} - -#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) // SLI_MAILBOX_COMMAND_SUPPORTED - -sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) -{ - sl_status_t status; - - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Execute SE mailbox command - SE_executeCommand(&cmd_ctx->command); - - return SL_STATUS_FAIL; // Should never get to this point -} - -/***************************************************************************//** - * From VSE mailbox read which command, if any, was executed. - ******************************************************************************/ -sl_status_t sl_se_read_executed_command(sl_se_command_context_t *cmd_ctx) -{ - sl_status_t status; - - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Read command - cmd_ctx->command.command = SE_readExecutedCommand(); - - // Release SE lock - status = sli_se_lock_release(); - - // Return sl_status_t code. - if (cmd_ctx->command.command == SE_RESPONSE_MAILBOX_INVALID) { - // Convert from SE_Response_t to sl_status_t code and return. - return sli_se_to_sl_status(SE_RESPONSE_MAILBOX_INVALID); - } else { - return status; - } -} - -/***************************************************************************//** - * Acknowledge and get status and output data of a completed command. - ******************************************************************************/ -sl_status_t sl_se_ack_command(sl_se_command_context_t *cmd_ctx) -{ - sl_status_t status; - SE_Response_t command_response; - - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Acknowledge VSE mailbox command - command_response = SE_ackCommand(&cmd_ctx->command); - - // Release SE lock - status = sli_se_lock_release(); - - // Return sl_status_t code. - if (command_response == SLI_SE_RESPONSE_OK) { - return status; - } else { - // Convert from SE_Response_t to sl_status_t code and return. - return sli_se_to_sl_status(command_response); - } -} - -#endif // SLI_VSE_MAILBOX_COMMAND_SUPPORTED - -#endif // !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT - -/***************************************************************************//** - * Initialize an SE command context object - ******************************************************************************/ -sl_status_t sl_se_init_command_context(sl_se_command_context_t *cmd_ctx) -{ - sl_se_command_context_t v = SL_SE_COMMAND_CONTEXT_INIT; - - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - *cmd_ctx = v; - return SL_STATUS_OK; -} - -/***************************************************************************//** - * De-initialize an SE command context object - ******************************************************************************/ -sl_status_t sl_se_deinit_command_context(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - return sl_se_init_command_context(cmd_ctx); -} - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +#if !defined(SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include "sl_assert.h" +#if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) +#include "em_bus.h" +#endif +#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) +#include "sli_se_manager_osal.h" +#endif + +#include + +/// @addtogroup sl_se_managers +/// @{ + +// ----------------------------------------------------------------------------- +// Locals + +#if defined(SL_SE_MANAGER_THREADING) \ + || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + +// Flag to indicate that the SE Manager is initialized or not. +static volatile bool se_manager_initialized = false; + + #if defined(SL_SE_MANAGER_THREADING) +// Lock mutex for synchronizing multiple threads calling into the +// SE Manager API. +static se_manager_osal_mutex_t se_lock = { 0 }; + + #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START \ + int32_t kernel_lock_state = 0; \ + osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); \ + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ + kernel_lock_state = se_manager_osal_kernel_lock(); \ + if (kernel_lock_state < 0) { \ + return SL_STATUS_FAIL; \ + } \ + } + + #define SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END \ + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { \ + if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { \ + return SL_STATUS_FAIL; \ + } \ + } + + #endif // SL_SE_MANAGER_THREADING + + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) +// SE command completion. +static se_manager_osal_completion_t se_command_completion; +// SE mailbox command response code. This value is read from the SEMAILBOX +// in ISR in order to clear the command complete interrupt condition. +static SE_Response_t se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; + #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION + +#endif // #if defined (SL_SE_MANAGER_THREADING) +// || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + +// ----------------------------------------------------------------------------- +// Global functions + +/***************************************************************************//** + * Initialize the SE Manager. + ******************************************************************************/ +sl_status_t sl_se_init(void) +{ + sl_status_t ret = SL_STATUS_OK; + #if defined (SL_SE_MANAGER_THREADING) \ + || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + #if defined(SL_SE_MANAGER_THREADING) + SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START + #endif + + if ( !se_manager_initialized ) { + #if defined(SL_SE_MANAGER_THREADING) + // Initialize SE lock + ret = se_manager_osal_init_mutex(&se_lock); + #endif + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + if (ret == SL_STATUS_OK) { + // Initialize command completion object. + ret = se_manager_osal_init_completion(&se_command_completion); + if (ret == SL_STATUS_OK) { + // Enable SE RX mailbox interrupt in NVIC, but not in SEMAILBOX + // which will be enabled if the yield parameter in + // sli_se_execute_and_wait is true. + NVIC_SetPriority(SEMBRX_IRQn, SE_MANAGER_SEMBRX_IRQ_PRIORITY); + NVIC_EnableIRQ(SEMBRX_IRQn); + } + } + #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION + if (ret == SL_STATUS_OK) { + se_manager_initialized = true; + } + } + + #if defined(SL_SE_MANAGER_THREADING) + SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + #endif + + #endif // #if defined (SL_SE_MANAGER_THREADING) + // || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + return ret; +} + +/***************************************************************************//** + * Denitialize the SE Manager. + ******************************************************************************/ +sl_status_t sl_se_deinit(void) +{ + sl_status_t ret = SL_STATUS_OK; + + #if defined (SL_SE_MANAGER_THREADING) \ + || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + #if defined(SL_SE_MANAGER_THREADING) + SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_START + #endif + + if ( se_manager_initialized ) { + // We need to exit the critical section in case the SE lock is held by a + // thread, and we want to take it before de-initializing. + #if defined(SL_SE_MANAGER_THREADING) + SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + #endif + + // Acquire the SE lock to make sure no thread is executing SE commands + // when we de-initialize. + ret = sli_se_lock_acquire(); + if (ret != SL_STATUS_OK) { + return ret; + } + + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + // Disable SE RX mailbox interrupt in NVIC. + NVIC_ClearPendingIRQ(SEMBRX_IRQn); + NVIC_DisableIRQ(SEMBRX_IRQn); + // Free command completion object. + ret = se_manager_osal_free_completion(&se_command_completion); + #endif // SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION + + #if defined(SL_SE_MANAGER_THREADING) + if (ret == SL_STATUS_OK) { + // Free the SE lock mutex + ret = se_manager_osal_free_mutex(&se_lock); + } + #endif + + // Mark the SE Manager as un-initialized. + se_manager_initialized = false; + } + #if defined(SL_SE_MANAGER_THREADING) + else { + SLI_SE_MANAGER_KERNEL_CRITICAL_SECTION_END + } + #endif + + #endif // #if defined (SL_SE_MANAGER_THREADING) + // || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + return ret; +} + +/***************************************************************************//** + * @brief + * Translate SE response codes to sl_status_t codes. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sli_se_to_sl_status(SE_Response_t res) +{ + switch (res) { + case SLI_SE_RESPONSE_OK: + return SL_STATUS_OK; + case SLI_SE_RESPONSE_INVALID_COMMAND: + return SL_STATUS_COMMAND_IS_INVALID; + case SLI_SE_RESPONSE_AUTHORIZATION_ERROR: + return SL_STATUS_INVALID_CREDENTIALS; + case SLI_SE_RESPONSE_INVALID_SIGNATURE: + return SL_STATUS_INVALID_SIGNATURE; + case SLI_SE_RESPONSE_BUS_ERROR: + return SL_STATUS_BUS_ERROR; + case SLI_SE_RESPONSE_INTERNAL_ERROR: + return SL_STATUS_FAIL; + case SLI_SE_RESPONSE_CRYPTO_ERROR: + return SL_STATUS_FAIL; + case SLI_SE_RESPONSE_INVALID_PARAMETER: + return SL_STATUS_INVALID_PARAMETER; + case SLI_SE_RESPONSE_ABORT: + return SL_STATUS_ABORT; + case SLI_SE_RESPONSE_SELFTEST_ERROR: + return SL_STATUS_INITIALIZATION; + case SLI_SE_RESPONSE_NOT_INITIALIZED: + return SL_STATUS_NOT_INITIALIZED; +#if defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + case SLI_SE_RESPONSE_MAILBOX_INVALID: + return SL_STATUS_COMMAND_IS_INVALID; +#endif + default: + // Assert we do not get a bad SE response code. + EFM_ASSERT(false); + return SL_STATUS_FAIL; + } +} + +/***************************************************************************//** + * Acquire the SE lock for exclusive access if necessary (thread mode). + * Enable the SEMAILBOX clock if necessary. + ******************************************************************************/ +sl_status_t sli_se_lock_acquire(void) +{ + #if defined(SL_SE_MANAGER_THREADING) + sl_status_t status = se_manager_osal_take_mutex(&se_lock); + #else + sl_status_t status = SL_STATUS_OK; + #endif + #if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) + if (status == SL_STATUS_OK) { + BUS_RegBitWrite(&CMU->CLKEN1, _CMU_CLKEN1_SEMAILBOXHOST_SHIFT, 1); + } + #endif + return status; +} + +/***************************************************************************//** + * Release the SE lock if necessary (thread mode). + * Disable the SEMAILBOX clock if necessary. + ******************************************************************************/ +sl_status_t sli_se_lock_release(void) +{ + #if defined(_CMU_CLKEN1_SEMAILBOXHOST_MASK) + BUS_RegBitWrite(&CMU->CLKEN1, _CMU_CLKEN1_SEMAILBOXHOST_SHIFT, 0); + #endif + #if defined(SL_SE_MANAGER_THREADING) + return se_manager_osal_give_mutex(&se_lock); + #else + return SL_STATUS_OK; + #endif +} + +#if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + +/***************************************************************************//** + * @brief + * SE Mailbox Interrupt Service Routine + ******************************************************************************/ +void SEMBRX_IRQHandler(void) +{ + sl_status_t status; + // Check if the SE mailbox is the source of the interrupt. + if (SEMAILBOX_HOST->RX_STATUS & SEMAILBOX_RX_STATUS_RXINT) { + // Signal SE mailbox completion. + status = se_manager_osal_complete(&se_command_completion); + EFM_ASSERT(status == SL_STATUS_OK); + } + // Get command response (clears interrupt condition in SEMAILBOX) + se_manager_command_response = SE_readCommandResponse(); + // Clear interrupt condition in NVIC + NVIC_ClearPendingIRQ(SEMBRX_IRQn); +} + +#endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + +/***************************************************************************//** + * Set the yield attribute of the SE command context object. + ******************************************************************************/ +sl_status_t sl_se_set_yield(sl_se_command_context_t *cmd_ctx, + bool yield) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + cmd_ctx->yield = yield; + return SL_STATUS_OK; + #else + if (yield) { + return SL_STATUS_NOT_AVAILABLE; + } else { + (void) cmd_ctx; + return SL_STATUS_OK; + } + #endif +} + +/***************************************************************************//** + * @brief + * Execute and wait for SE mailbox command to complete. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && !defined(SLI_SE_MANAGER_HOST_SYSTEM) +sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) +{ + sl_status_t status; + SE_Response_t command_response; + + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Execute SE mailbox command + SE_executeCommand(&cmd_ctx->command); + + #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + if (cmd_ctx->yield) { + // Enable SEMAILBOX RXINT interrupt + SE_enableInterrupt(SEMAILBOX_CONFIGURATION_RXINTEN); + + // Yield and Wait for the command completion signal + status = se_manager_osal_wait_completion(&se_command_completion, + SE_MANAGER_OSAL_WAIT_FOREVER); + + // Disable SEMAILBOX RXINT interrupt. + SE_disableInterrupt(SEMAILBOX_CONFIGURATION_RXINTEN); + + if (status != SL_STATUS_OK) { + return status; + } + + // Get response which is read in the ISR to clear interrupt condition. + command_response = se_manager_command_response; + // Default to an error. + se_manager_command_response = SLI_SE_RESPONSE_INTERNAL_ERROR; + } else { + // Wait for command completion and get command response + command_response = SE_readCommandResponse(); + } + + #else // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + // Wait for command completion and get command response + command_response = SE_readCommandResponse(); + + #endif // #if defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION) + + // Release SE lock + status = sli_se_lock_release(); + + // Return sl_status_t code. + if (command_response == SLI_SE_RESPONSE_OK) { + return status; + } else { + // Convert from SE_Response_t to sl_status_t code and return. + return sli_se_to_sl_status(command_response); + } +} + +#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) // SLI_MAILBOX_COMMAND_SUPPORTED + +sl_status_t sli_se_execute_and_wait(sl_se_command_context_t *cmd_ctx) +{ + sl_status_t status; + + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Execute SE mailbox command + SE_executeCommand(&cmd_ctx->command); + + return SL_STATUS_FAIL; // Should never get to this point +} + +/***************************************************************************//** + * From VSE mailbox read which command, if any, was executed. + ******************************************************************************/ +sl_status_t sl_se_read_executed_command(sl_se_command_context_t *cmd_ctx) +{ + sl_status_t status; + + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Read command + cmd_ctx->command.command = SE_readExecutedCommand(); + + // Release SE lock + status = sli_se_lock_release(); + + // Return sl_status_t code. + if (cmd_ctx->command.command == SE_RESPONSE_MAILBOX_INVALID) { + // Convert from SE_Response_t to sl_status_t code and return. + return sli_se_to_sl_status(SE_RESPONSE_MAILBOX_INVALID); + } else { + return status; + } +} + +/***************************************************************************//** + * Acknowledge and get status and output data of a completed command. + ******************************************************************************/ +sl_status_t sl_se_ack_command(sl_se_command_context_t *cmd_ctx) +{ + sl_status_t status; + SE_Response_t command_response; + + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Acknowledge VSE mailbox command + command_response = SE_ackCommand(&cmd_ctx->command); + + // Release SE lock + status = sli_se_lock_release(); + + // Return sl_status_t code. + if (command_response == SLI_SE_RESPONSE_OK) { + return status; + } else { + // Convert from SE_Response_t to sl_status_t code and return. + return sli_se_to_sl_status(command_response); + } +} + +#endif // SLI_VSE_MAILBOX_COMMAND_SUPPORTED + +#endif // !SL_CATALOG_TZ_SECURE_KEY_LIBRARY_NS_PRESENT + +/***************************************************************************//** + * Initialize an SE command context object + ******************************************************************************/ +sl_status_t sl_se_init_command_context(sl_se_command_context_t *cmd_ctx) +{ + sl_se_command_context_t v = SL_SE_COMMAND_CONTEXT_INIT; + + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + *cmd_ctx = v; + return SL_STATUS_OK; +} + +/***************************************************************************//** + * De-initialize an SE command context object + ******************************************************************************/ +sl_status_t sl_se_deinit_command_context(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + return sl_se_init_command_context(cmd_ctx); +} + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c index 5b63280..cf2b41f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c @@ -1,296 +1,296 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - -#include "sl_se_manager.h" -#include "sli_se_manager_internal.h" -#include "sl_se_manager_attestation.h" -#include "em_se.h" - -/// @addtogroup sl_se_manager -/// @{ - -// ----------------------------------------------------------------------------- -// Static Functions - -/***************************************************************************//** - * @brief - * Validate the command word, challenge size and update command word with - * option flags - * - * @param[in, out] command_word - * The command word to send to the SE. Will be modified to reflect challenge - * size. - * - * @param challenge_size - * Size of the challenge to be used. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -static sl_status_t validate_and_update_command_word(uint32_t *command_word, - size_t challenge_size) -{ - // Check supported challenge sizes - uint32_t command_id = *command_word & 0xFFFF0000UL; - if (command_id == SLI_SE_COMMAND_ATTEST_PSA_IAT) { - switch (challenge_size) { - case SL_SE_ATTESTATION_CHALLENGE_SIZE_32: - *command_word |= 0x01 << 8; - break; - case SL_SE_ATTESTATION_CHALLENGE_SIZE_48: - *command_word |= 0x02 << 8; - break; - case SL_SE_ATTESTATION_CHALLENGE_SIZE_64: - *command_word |= 0x03 << 8; - break; - default: - return SL_STATUS_INVALID_PARAMETER; - } - } else if (command_id == SLI_SE_COMMAND_ATTEST_CONFIG) { - if (challenge_size != SL_SE_ATTESTATION_CHALLENGE_SIZE_32) { - return SL_STATUS_INVALID_PARAMETER; - } - // No need to do anything with the command word - } else { - // Unknown command ID - return SL_STATUS_INVALID_PARAMETER; - } - // All the checks passed - return SL_STATUS_OK; -} - -/***************************************************************************//** - * @brief - * Get the PSA initial attest token from the SE - * - * @param[in] cmd_ctx - * SE command context struct. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be either 32, 48 or 64. - * - * @param[out] token_size - * Number of bytes actually used in token_buf. - * - * @param[in] command_word - * The command word to send to the SE, to differentiat between token types - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -static sl_status_t get_attestation_token_size(sl_se_command_context_t *cmd_ctx, - size_t challenge_size, - size_t *token_size, - uint32_t command_word) -{ - // Parameter check - if (cmd_ctx == NULL || token_size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check command word and challenge size - sl_status_t status = validate_and_update_command_word(&command_word, - challenge_size); - if (status != SL_STATUS_OK) { - return status; - } - - // Use a dummy nonce since the SE requires nonce input even if we just - // want to find the token length - uint8_t dummy_nonce[SL_SE_ATTESTATION_CHALLENGE_SIZE_64] = { 0 }; - - // Build and execute the command - SE_Command_t *se_cmd = &cmd_ctx->command; - // Or comman word with 0x01 to enable length output only - sli_se_command_init(cmd_ctx, command_word | 0x01UL); - SE_DataTransfer_t noncedata = - SE_DATATRANSFER_DEFAULT(dummy_nonce, challenge_size); - SE_addDataInput(se_cmd, &noncedata); - SE_DataTransfer_t sizedata = - SE_DATATRANSFER_DEFAULT(token_size, sizeof(*token_size)); - SE_addDataOutput(se_cmd, &sizedata); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * @brief - * Get an attestation token from the SE - * - * @param[in] cmd_ctx - * SE command context struct. - * - * @param[in] auth_challenge - * Buffer with a challenge object selected by the caller. - * - * @param[in] challenge_size - * Size of the challenge object in bytes. Must be either 32, 48 or 64. - * - * @param[out] token_buf - * Buffer where the output token will be stored. - * - * @param[in] token_buf_size - * Size of token_buf in bytes. - * - * @param[out] token_size - * Number of bytes actually used in token_buf. - * - * @param[in] command_word - * The command word to send to the SE, to differentiat between token types - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -static sl_status_t get_attestation_token(sl_se_command_context_t *cmd_ctx, - const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size, - uint32_t command_word) -{ - // Parameter check - if (cmd_ctx == NULL - || auth_challenge == NULL - || token_buf == NULL - || token_size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check supported challenge sizes - sl_status_t status = validate_and_update_command_word(&command_word, - challenge_size); - if (status != SL_STATUS_OK) { - return status; - } - - // Check that buffer is sufficiently large - status = get_attestation_token_size(cmd_ctx, - challenge_size, - token_size, - command_word); - if (status != SL_STATUS_OK) { - return status; - } - if (((*token_size + 0x3) & ~0x3) > token_buf_size) { - return SL_STATUS_WOULD_OVERFLOW; - } - - // Build and execute the command - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, command_word); - SE_DataTransfer_t noncedata = - SE_DATATRANSFER_DEFAULT(auth_challenge, challenge_size); - SE_addDataInput(se_cmd, &noncedata); - SE_DataTransfer_t sizedata = - SE_DATATRANSFER_DEFAULT(token_size, sizeof(*token_size)); - SE_addDataOutput(se_cmd, &sizedata); - SE_DataTransfer_t tokendata = - SE_DATATRANSFER_DEFAULT(token_buf, ((*token_size + 0x3) & ~0x3)); - SE_addDataOutput(se_cmd, &tokendata); - - return sli_se_execute_and_wait(cmd_ctx); -} - -// ----------------------------------------------------------------------------- -// Global Functions - -/***************************************************************************//** - * Get the PSA initial attest token from the SE - ******************************************************************************/ -sl_status_t sl_se_attestation_get_psa_iat_token(sl_se_command_context_t *cmd_ctx, - const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size) -{ - return get_attestation_token(cmd_ctx, - auth_challenge, - challenge_size, - token_buf, - token_buf_size, - token_size, - SLI_SE_COMMAND_ATTEST_PSA_IAT); -} - -/***************************************************************************//** - * Get the size of a PSA initial attest token with the given nonce - ******************************************************************************/ -sl_status_t sl_se_attestation_get_psa_iat_token_size(sl_se_command_context_t *cmd_ctx, - size_t challenge_size, - size_t *token_size) -{ - return get_attestation_token_size(cmd_ctx, - challenge_size, - token_size, - SLI_SE_COMMAND_ATTEST_PSA_IAT); -} - -/***************************************************************************//** - * Get an attested (signed) security configuration token from the SE - ******************************************************************************/ -sl_status_t sl_se_attestation_get_config_token(sl_se_command_context_t *cmd_ctx, - const uint8_t *auth_challenge, - size_t challenge_size, - uint8_t *token_buf, - size_t token_buf_size, - size_t *token_size) -{ - return get_attestation_token(cmd_ctx, - auth_challenge, - challenge_size, - token_buf, - token_buf_size, - token_size, - SLI_SE_COMMAND_ATTEST_CONFIG); -} - -/***************************************************************************//** - * Get the size of a security configuration token - ******************************************************************************/ -sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd_ctx, - size_t challenge_size, - size_t *token_size) -{ - return get_attestation_token_size(cmd_ctx, - challenge_size, - token_size, - SLI_SE_COMMAND_ATTEST_CONFIG); -} - -/** @} (end addtogroup sl_se_manager) */ - -#endif // SLI_MAILBOX_COMMAND_SUPPORTED && VAULT +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + +#include "sl_se_manager.h" +#include "sli_se_manager_internal.h" +#include "sl_se_manager_attestation.h" +#include "em_se.h" + +/// @addtogroup sl_se_manager +/// @{ + +// ----------------------------------------------------------------------------- +// Static Functions + +/***************************************************************************//** + * @brief + * Validate the command word, challenge size and update command word with + * option flags + * + * @param[in, out] command_word + * The command word to send to the SE. Will be modified to reflect challenge + * size. + * + * @param challenge_size + * Size of the challenge to be used. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +static sl_status_t validate_and_update_command_word(uint32_t *command_word, + size_t challenge_size) +{ + // Check supported challenge sizes + uint32_t command_id = *command_word & 0xFFFF0000UL; + if (command_id == SLI_SE_COMMAND_ATTEST_PSA_IAT) { + switch (challenge_size) { + case SL_SE_ATTESTATION_CHALLENGE_SIZE_32: + *command_word |= 0x01 << 8; + break; + case SL_SE_ATTESTATION_CHALLENGE_SIZE_48: + *command_word |= 0x02 << 8; + break; + case SL_SE_ATTESTATION_CHALLENGE_SIZE_64: + *command_word |= 0x03 << 8; + break; + default: + return SL_STATUS_INVALID_PARAMETER; + } + } else if (command_id == SLI_SE_COMMAND_ATTEST_CONFIG) { + if (challenge_size != SL_SE_ATTESTATION_CHALLENGE_SIZE_32) { + return SL_STATUS_INVALID_PARAMETER; + } + // No need to do anything with the command word + } else { + // Unknown command ID + return SL_STATUS_INVALID_PARAMETER; + } + // All the checks passed + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief + * Get the PSA initial attest token from the SE + * + * @param[in] cmd_ctx + * SE command context struct. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be either 32, 48 or 64. + * + * @param[out] token_size + * Number of bytes actually used in token_buf. + * + * @param[in] command_word + * The command word to send to the SE, to differentiat between token types + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +static sl_status_t get_attestation_token_size(sl_se_command_context_t *cmd_ctx, + size_t challenge_size, + size_t *token_size, + uint32_t command_word) +{ + // Parameter check + if (cmd_ctx == NULL || token_size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check command word and challenge size + sl_status_t status = validate_and_update_command_word(&command_word, + challenge_size); + if (status != SL_STATUS_OK) { + return status; + } + + // Use a dummy nonce since the SE requires nonce input even if we just + // want to find the token length + uint8_t dummy_nonce[SL_SE_ATTESTATION_CHALLENGE_SIZE_64] = { 0 }; + + // Build and execute the command + SE_Command_t *se_cmd = &cmd_ctx->command; + // Or comman word with 0x01 to enable length output only + sli_se_command_init(cmd_ctx, command_word | 0x01UL); + SE_DataTransfer_t noncedata = + SE_DATATRANSFER_DEFAULT(dummy_nonce, challenge_size); + SE_addDataInput(se_cmd, &noncedata); + SE_DataTransfer_t sizedata = + SE_DATATRANSFER_DEFAULT(token_size, sizeof(*token_size)); + SE_addDataOutput(se_cmd, &sizedata); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * @brief + * Get an attestation token from the SE + * + * @param[in] cmd_ctx + * SE command context struct. + * + * @param[in] auth_challenge + * Buffer with a challenge object selected by the caller. + * + * @param[in] challenge_size + * Size of the challenge object in bytes. Must be either 32, 48 or 64. + * + * @param[out] token_buf + * Buffer where the output token will be stored. + * + * @param[in] token_buf_size + * Size of token_buf in bytes. + * + * @param[out] token_size + * Number of bytes actually used in token_buf. + * + * @param[in] command_word + * The command word to send to the SE, to differentiat between token types + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +static sl_status_t get_attestation_token(sl_se_command_context_t *cmd_ctx, + const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size, + uint32_t command_word) +{ + // Parameter check + if (cmd_ctx == NULL + || auth_challenge == NULL + || token_buf == NULL + || token_size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check supported challenge sizes + sl_status_t status = validate_and_update_command_word(&command_word, + challenge_size); + if (status != SL_STATUS_OK) { + return status; + } + + // Check that buffer is sufficiently large + status = get_attestation_token_size(cmd_ctx, + challenge_size, + token_size, + command_word); + if (status != SL_STATUS_OK) { + return status; + } + if (((*token_size + 0x3) & ~0x3) > token_buf_size) { + return SL_STATUS_WOULD_OVERFLOW; + } + + // Build and execute the command + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, command_word); + SE_DataTransfer_t noncedata = + SE_DATATRANSFER_DEFAULT(auth_challenge, challenge_size); + SE_addDataInput(se_cmd, &noncedata); + SE_DataTransfer_t sizedata = + SE_DATATRANSFER_DEFAULT(token_size, sizeof(*token_size)); + SE_addDataOutput(se_cmd, &sizedata); + SE_DataTransfer_t tokendata = + SE_DATATRANSFER_DEFAULT(token_buf, ((*token_size + 0x3) & ~0x3)); + SE_addDataOutput(se_cmd, &tokendata); + + return sli_se_execute_and_wait(cmd_ctx); +} + +// ----------------------------------------------------------------------------- +// Global Functions + +/***************************************************************************//** + * Get the PSA initial attest token from the SE + ******************************************************************************/ +sl_status_t sl_se_attestation_get_psa_iat_token(sl_se_command_context_t *cmd_ctx, + const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size) +{ + return get_attestation_token(cmd_ctx, + auth_challenge, + challenge_size, + token_buf, + token_buf_size, + token_size, + SLI_SE_COMMAND_ATTEST_PSA_IAT); +} + +/***************************************************************************//** + * Get the size of a PSA initial attest token with the given nonce + ******************************************************************************/ +sl_status_t sl_se_attestation_get_psa_iat_token_size(sl_se_command_context_t *cmd_ctx, + size_t challenge_size, + size_t *token_size) +{ + return get_attestation_token_size(cmd_ctx, + challenge_size, + token_size, + SLI_SE_COMMAND_ATTEST_PSA_IAT); +} + +/***************************************************************************//** + * Get an attested (signed) security configuration token from the SE + ******************************************************************************/ +sl_status_t sl_se_attestation_get_config_token(sl_se_command_context_t *cmd_ctx, + const uint8_t *auth_challenge, + size_t challenge_size, + uint8_t *token_buf, + size_t token_buf_size, + size_t *token_size) +{ + return get_attestation_token(cmd_ctx, + auth_challenge, + challenge_size, + token_buf, + token_buf_size, + token_size, + SLI_SE_COMMAND_ATTEST_CONFIG); +} + +/***************************************************************************//** + * Get the size of a security configuration token + ******************************************************************************/ +sl_status_t sl_se_attestation_get_config_token_size(sl_se_command_context_t *cmd_ctx, + size_t challenge_size, + size_t *token_size) +{ + return get_attestation_token_size(cmd_ctx, + challenge_size, + token_size, + SLI_SE_COMMAND_ATTEST_CONFIG); +} + +/** @} (end addtogroup sl_se_manager) */ + +#endif // SLI_MAILBOX_COMMAND_SUPPORTED && VAULT diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c index f10680e..bfc0620 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c @@ -1,2883 +1,2883 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include "sl_assert.h" -#include - -/// @addtogroup sl_se_manager -/// @{ - -uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size) -{ - //Don't try to optimise this function for performance, it's time constant for security reasons - uint32_t diff = 0; - uint32_t i = 0; - for (i = 0; i < size; i++) { - diff |= (*(in1 + i) ^ (*(in2 + i))); - } - - return (diff > 0); -} - -// ----------------------------------------------------------------------------- -// Global Functions - -/***************************************************************************//** - * AES-ECB block encryption/decryption. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_ecb(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - const unsigned char *input, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL - || (length & 0xFU) != 0U) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - sli_se_command_init(cmd_ctx, - (mode == SL_SE_ENCRYPT - ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) - | SLI_SE_COMMAND_OPTION_MODE_ECB - | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &in); - - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); - SE_addDataOutput(se_cmd, &out); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * AES-CBC buffer encryption/decryption. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cbc(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL - || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - // Input length must be a multiple of 16 bytes which is the AES block length - if (length & 0xf) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, - (mode == SL_SE_ENCRYPT - ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) - | SLI_SE_COMMAND_OPTION_MODE_CBC - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, 16); - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &in); - - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); - SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(iv, 16); - SE_addDataOutput(se_cmd, &out); - SE_addDataOutput(se_cmd, &iv_out); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * AES-CFB128 buffer encryption/decryption. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cfb128(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - uint32_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL - || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t n = iv_off ? *iv_off : 0; - uint32_t processed = 0; - sl_status_t command_status = SL_STATUS_OK; - - while (processed < length) { - if (n > 0) { - // start by filling up the IV - if (mode == SL_SE_ENCRYPT) { - iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); - } else { - int c = input[processed]; - output[processed] = (unsigned char)(c ^ iv[n]); - iv[n] = (unsigned char) c; - } - n = (n + 1) & 0x0F; - processed++; - } else { - // process one ore more blocks of data - uint32_t iterations = (length - processed) / 16; - - if (iterations > 0) { - sli_se_command_init(cmd_ctx, - (mode == SL_SE_ENCRYPT - ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) - | SLI_SE_COMMAND_OPTION_MODE_CFB - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, command_status); - // Message size (number of bytes) - SE_addParameter(se_cmd, iterations * 16); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, command_status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, command_status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, 16); - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(&input[processed], iterations * 16); - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &in); - - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(&output[processed], iterations * 16); - SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(iv, 16); - SE_addDataOutput(se_cmd, &out); - SE_addDataOutput(se_cmd, &iv_out); - - command_status = sli_se_execute_and_wait(cmd_ctx); - processed += iterations * 16; - if (command_status != SL_STATUS_OK) { - return command_status; - } - } - - while ((length - processed) > 0) { - if (n == 0) { - // Need to update the IV but don't have a full block of input to pass - // to the SE. - command_status = sl_se_aes_crypt_ecb(cmd_ctx, key, SL_SE_ENCRYPT, 16U, iv, iv); - if (command_status != SL_STATUS_OK) { - return command_status; - } - } - // Save remainder to IV - if (mode == SL_SE_ENCRYPT) { - iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); - } else { - int c = input[processed]; - output[processed] = (unsigned char)(c ^ iv[n]); - iv[n] = (unsigned char) c; - } - n = (n + 1) & 0x0F; - processed++; - } - } - } - - if ( iv_off ) { - *iv_off = n; - } - - return command_status; -} - -/***************************************************************************//** - * AES-CFB8 buffer encryption/decryption. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_cfb8(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - unsigned char c; - unsigned char ov[17]; - sl_status_t ret = SL_STATUS_OK; - - if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL - || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - while (length--) { - memcpy(ov, iv, 16U); - if ((ret = sl_se_aes_crypt_ecb(cmd_ctx, key, SL_SE_ENCRYPT, 16U, iv, iv)) - != SL_STATUS_OK) { - return ret; - } - - if (mode == SL_SE_DECRYPT) { - ov[16] = *input; - } - - c = *output++ = (unsigned char)(iv[0] ^ *input++); - - if (mode == SL_SE_ENCRYPT) { - ov[16] = c; - } - - memcpy(iv, ov + 1, 16U); - } - - return ret; -} - -/***************************************************************************//** - * Increment the input nonce counter by one - ******************************************************************************/ -static void increment_nonce_counter(uint8_t block_end, unsigned char nonce_counter[]) -{ - for (size_t i = 0u; i < SL_SE_AES_BLOCK_SIZE; i++) { - nonce_counter[block_end - i] = nonce_counter[block_end - i] + 1u; - if (nonce_counter[block_end - i] != 0u) { - // did not overflow so no need to increment the value at next index - break; - } - } -} - -#if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1) -/***************************************************************************//** - * Prepare the SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE byte - * wide stream block buffer that will be used as nonce counter for - * encryption/decryption. - ******************************************************************************/ -static void prepare_nonce_counter(unsigned char nonce_counter[], - unsigned char stream_block[]) -{ - uint8_t no_of_blocks = ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) / SL_SE_AES_BLOCK_SIZE); - // place the most recent counter in the first stream block - memcpy(stream_block, - nonce_counter, - SL_SE_AES_BLOCK_SIZE); - - for (size_t i = 0; i < no_of_blocks - 1u; i++) { - // Use the first block's reference counter to update the other - // blocks since it holds the most recent counter information. - memcpy(&stream_block[i * SL_SE_AES_BLOCK_SIZE + SL_SE_AES_BLOCK_SIZE], - &stream_block[i * SL_SE_AES_BLOCK_SIZE], - SL_SE_AES_BLOCK_SIZE); - increment_nonce_counter(((i + 2u) * SL_SE_AES_BLOCK_SIZE) - 1u, stream_block); - } - - // Store the largest counter back in the nonce counter buffer - memcpy(nonce_counter, - &stream_block[(no_of_blocks - 1u) * SL_SE_AES_BLOCK_SIZE], - SL_SE_AES_BLOCK_SIZE); -} -#endif // SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1 - -/***************************************************************************//** - * AES-CTR buffer encryption/decryption. - ******************************************************************************/ -sl_status_t sl_se_aes_crypt_ctr(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - uint32_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE], - const unsigned char *input, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL - || (length != 0 && (input == NULL || output == NULL)) - || nonce_counter == NULL || stream_block == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t n = nc_off ? *nc_off : 0; - uint32_t processed = 0; - sl_status_t command_status = SL_STATUS_OK; - - while (processed < length) { - if (n > 0) { - // start by filling up the IV - output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); - n = (n + 1) & ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) - 1u); - processed++; - } else { - // process one or more blocks of data - uint32_t iterations = (length - processed) / SL_SE_AES_BLOCK_SIZE; - - if (iterations > 0) { - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_ENCRYPT - | SLI_SE_COMMAND_OPTION_MODE_CTR - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, command_status); - // Message size (number of bytes) - SE_addParameter(se_cmd, iterations * SL_SE_AES_BLOCK_SIZE); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, command_status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, command_status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(nonce_counter, SL_SE_AES_BLOCK_SIZE); - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(&input[processed], iterations * SL_SE_AES_BLOCK_SIZE); - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &in); - - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(&output[processed], iterations * SL_SE_AES_BLOCK_SIZE); - SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(nonce_counter, SL_SE_AES_BLOCK_SIZE); - SE_addDataOutput(se_cmd, &out); - SE_addDataOutput(se_cmd, &iv_out); - - command_status = sli_se_execute_and_wait(cmd_ctx); - processed += iterations * SL_SE_AES_BLOCK_SIZE; - if (command_status != SL_STATUS_OK) { - return command_status; - } - } - - while ((length - processed) > 0) { - if (n == 0) { - // Get a new stream block - unsigned char *counter_ptr = NULL; - #if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1) - // Use the nonce counter buffer as the reference to create nonce counter blocks - // needed to compute the key stream blocks. Also, update the nonce counter buffer - // to store the latest block. - prepare_nonce_counter(nonce_counter, stream_block); - // The key stream buffer now holds the nonce counter - counter_ptr = stream_block; - #else - counter_ptr = nonce_counter; - #endif // SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1 - - command_status = sl_se_aes_crypt_ecb(cmd_ctx, - key, - SL_SE_ENCRYPT, - SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE, - counter_ptr, - stream_block); - if (command_status != SL_STATUS_OK) { - return command_status; - } - increment_nonce_counter(SL_SE_AES_BLOCK_SIZE - 1u, nonce_counter); - } - // Save remainder to IV - output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); - n = (n + 1) & ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) - 1u); - processed++; - } - } - } - - if ( nc_off ) { - *nc_off = n; - } - - return command_status; -} - -/***************************************************************************//** - * AES-CCM buffer encryption. - ******************************************************************************/ -sl_status_t sl_se_ccm_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - unsigned char *tag, size_t tag_len) -{ - if (cmd_ctx == NULL || key == NULL || (tag_len > 0 && tag == NULL) || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (add_len > 0 && add == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (length > 0 && (input == NULL || output == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - unsigned char q; - sl_status_t command_status = SL_STATUS_OK; - - // Test for invalid (too long) message length. This test is included here because - // the SE does not implement the test. When the SE ultimately implements the test - // the following test can be removed. - q = 16 - 1 - (unsigned char) iv_len; - if ((q < sizeof(length)) && (length >= (1UL << (q * 8)))) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Also implies q is within bounds - if (iv_len < 7 || iv_len > 13) { - return SL_STATUS_INVALID_PARAMETER; - } - -#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) - if ((uint32_t)output + length > RAM_MEM_END) { - return SL_STATUS_INVALID_PARAMETER; - } -#endif // SLI_SE_MANAGER_HOST_SYSTEM - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CCM_ENCRYPT); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, command_status); - // Message size (number of bytes) - SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, command_status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, command_status); - - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, length); - SE_DataTransfer_t in_add = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t in_nonce = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_addDataInput(se_cmd, &in_nonce); - SE_addDataInput(se_cmd, &in_add); - SE_addDataInput(se_cmd, &in_data); - - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, length); - SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(tag, tag_len); - SE_addDataOutput(se_cmd, &out_data); - SE_addDataOutput(se_cmd, &out_tag); - - command_status = sli_se_execute_and_wait(cmd_ctx); - return command_status; -} - -/***************************************************************************//** - * AES-CCM buffer decryption. - ******************************************************************************/ -sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - const unsigned char *tag, size_t tag_len) -{ - if (cmd_ctx == NULL || key == NULL || tag == NULL || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (add_len > 0 && add == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (length > 0 && (input == NULL || output == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - unsigned char q; - sl_status_t command_status = SL_STATUS_OK; - - // Test for invalid (too long) message length. This test is included here because - // the SE does not implement the test. When the SE ultimately implements the test - // the following test can be removed. - q = 16 - 1 - (unsigned char) iv_len; - if ((q < sizeof(length)) && (length >= (1UL << (q * 8)))) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_len == 2 || tag_len == 0 || tag_len > 16 || tag_len % 2 != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Also implies q is within bounds */ - if (iv_len < 7 || iv_len > 13) { - return SL_STATUS_INVALID_PARAMETER; - } - -#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) - if ((uint32_t)output + length > RAM_MEM_END) { - return SL_STATUS_INVALID_PARAMETER; - } -#endif // SLI_SE_MANAGER_HOST_SYSTEM - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CCM_DECRYPT); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, command_status); - // Message size (number of bytes) - SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, command_status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, command_status); - - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, length); - SE_DataTransfer_t in_add = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t in_nonce = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_addDataInput(se_cmd, &in_nonce); - SE_addDataInput(se_cmd, &in_add); - SE_addDataInput(se_cmd, &in_data); - - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, length); - SE_addDataOutput(se_cmd, &out_data); - SE_DataTransfer_t in_tag = SE_DATATRANSFER_DEFAULT(tag, tag_len); - SE_addDataInput(se_cmd, &in_tag); - - command_status = sli_se_execute_and_wait(cmd_ctx); - if (command_status == SL_STATUS_OK) { - return SL_STATUS_OK; - } else { - memset(output, 0, length); - return command_status; - } -} - -#if defined(SLI_SE_MAJOR_VERSION_ONE) -sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - uint32_t total_message_length, - const uint8_t *iv, - size_t iv_len, - const uint8_t *aad, - size_t aad_len, - size_t tag_len) -{ - sl_status_t status = SL_STATUS_OK; - uint8_t q; - uint8_t b[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint8_t tag_out[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint8_t cbc_mac_state[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint8_t nonce_counter[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint32_t len_left; - - //Check input parameters - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (aad_len > 0 && aad == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (iv_len < 7 || iv_len > 13) { - return SL_STATUS_INVALID_PARAMETER; - } - - // q is the the octet length of Q which again is a bit string representation of - // the octet length of the payload. - q = 16 - 1 - (uint8_t) iv_len; - - // The parameter q determines the maximum length of the payload: by definition, p<2^(8*q), - // where p is payload. - if ((q < sizeof(total_message_length)) && (total_message_length >= (1UL << (q * 8)))) { - return SL_STATUS_INVALID_PARAMETER; - } - memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); - - // Format first input block B_O according to the formatting function: - - // 0 .. 0 flags - // 1 .. iv_len nonce (aka iv) - // iv_len+1 .. 15 length - // - // With flags as (bits): - // 7 0 - // 6 add present? - // 5 .. 3 (t - 2) / 2 - // 2 .. 0 q - 1 - - b[0] = 0; - b[0] |= (aad_len > 0) << 6; - b[0] |= ((tag_len - 2) / 2) << 3; - b[0] |= q - 1; - - memcpy(b + 1, iv, iv_len); - - len_left = total_message_length; - for (uint32_t i = 0; i < q; i++, len_left >>= 8) { - b[15 - i] = (unsigned char)(len_left & 0xFF); - } - - ccm_ctx->mode = mode; - ccm_ctx->processed_message_length = 0; - ccm_ctx->total_message_length = total_message_length; - ccm_ctx->tag_len = tag_len; - ccm_ctx->mode = mode; - ccm_ctx->iv_len = iv_len; - memcpy(ccm_ctx->iv, iv, iv_len); - - status = sl_se_aes_crypt_cbc(cmd_ctx, - key, - SL_SE_ENCRYPT, - SL_SE_AES_BLOCK_SIZE, - cbc_mac_state, - b, - tag_out); - - if (status != SL_STATUS_OK) { - return status; - } - - // If there is additional data, update using CBC. Must be done - // blockwise to achieve the same behaviour as CBC-MAC. - if (aad_len > 0) { - uint8_t use_len; - len_left = aad_len; - memset(b, 0, sizeof(b)); - // First block. - b[0] = (unsigned char)((aad_len >> 8) & 0xFF); - b[1] = (unsigned char)((aad_len) & 0xFF); - use_len = len_left < SL_SE_AES_BLOCK_SIZE - 2 ? len_left : 16 - 2; - memcpy(b + 2, aad, use_len); - len_left -= use_len; - aad += use_len; - - status = sl_se_aes_crypt_cbc(cmd_ctx, - key, - SL_SE_ENCRYPT, - SL_SE_AES_BLOCK_SIZE, - cbc_mac_state, - b, - tag_out); - if (status != SL_STATUS_OK) { - return status; - } - - while (len_left) { - use_len = len_left > 16 ? 16 : len_left; - - memset(b, 0, sizeof(b)); - memcpy(b, aad, use_len); - status = sl_se_aes_crypt_cbc(cmd_ctx, - key, - SL_SE_ENCRYPT, - SL_SE_AES_BLOCK_SIZE, - cbc_mac_state, - b, - tag_out); - - if (status != SL_STATUS_OK) { - return status; - } - len_left -= use_len; - aad += use_len; - } - } - - memcpy(ccm_ctx->cbc_mac_state, cbc_mac_state, sizeof(cbc_mac_state)); - - // Prepare nonce counter for encryption/decryption operation. - nonce_counter[0] = q - 1; - memcpy(nonce_counter + 1, iv, iv_len); - memset(nonce_counter + 1 + iv_len, 0, q); - nonce_counter[15] = 1; - - memcpy(ccm_ctx->nonce_counter, nonce_counter, sizeof(ccm_ctx->nonce_counter)); - - return SL_STATUS_OK; -} - -sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length) -{ - sl_status_t status = SL_STATUS_OK; - *output_length = 0; - - uint8_t out_buf[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint8_t empty[SL_SE_AES_BLOCK_SIZE * SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED] = { 0 }; - uint8_t b[SL_SE_AES_BLOCK_SIZE] = { 0 }; - - size_t len_left; - - // Check input parameters. - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (length == 0) { - return SL_STATUS_OK; - } - - // Check variable overflow - if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (length > 0 && (input == NULL || output == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((uint32_t)output + length > RAM_MEM_END) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Support partial overlap. - if ((output > input) && (output < (input + length))) { - memmove(output, input, length); - input = output; - } - - if (length + ccm_ctx->final_data_length < SL_SE_AES_BLOCK_SIZE && length < SL_SE_AES_BLOCK_SIZE && ccm_ctx->processed_message_length + length != ccm_ctx->total_message_length ) { - if (ccm_ctx->final_data_length > SL_SE_AES_BLOCK_SIZE) { - // Context is not valid. - return SL_STATUS_INVALID_PARAMETER; - } - memcpy(ccm_ctx->final_data + ccm_ctx->final_data_length, input, length); - ccm_ctx->final_data_length += length; - *output_length = 0; - return SL_STATUS_OK; - } - - len_left = length + ccm_ctx->final_data_length; - - // Authenticate and {en,de}crypt the message. - - // The only difference between encryption and decryption is - // the respective order of authentication and {en,de}cryption. - while (len_left > 0 ) { - uint8_t use_len = len_left > SL_SE_AES_BLOCK_SIZE ? SL_SE_AES_BLOCK_SIZE : len_left; - - memset(b, 0, sizeof(b)); - - // Process data stored in context first. - if (ccm_ctx->final_data_length > 0) { - if (ccm_ctx->final_data_length > SL_SE_AES_BLOCK_SIZE) { - // Context is not valid. - return SL_STATUS_INVALID_PARAMETER; - } - memcpy(b, ccm_ctx->final_data, ccm_ctx->final_data_length); - memcpy(b + ccm_ctx->final_data_length, input, SL_SE_AES_BLOCK_SIZE - ccm_ctx->final_data_length); - input += SL_SE_AES_BLOCK_SIZE - ccm_ctx->final_data_length; - ccm_ctx->final_data_length = 0; - } else { - memcpy(b, input, use_len); - input += use_len; - } - if (ccm_ctx->mode == SL_SE_ENCRYPT) { - // Authenticate input. - status = sl_se_aes_crypt_cbc(cmd_ctx, - key, - SL_SE_ENCRYPT, - SL_SE_AES_BLOCK_SIZE, - ccm_ctx->cbc_mac_state, - b, - out_buf); - - if (status != SL_STATUS_OK) { - return status; - } - } - // Encrypt/decrypt data with CTR. - status = sl_se_aes_crypt_ctr(cmd_ctx, - key, - use_len, - NULL, - ccm_ctx->nonce_counter, - empty, - b, - output); - - if (ccm_ctx->mode == SL_SE_DECRYPT) { - // Authenticate output. - memset(b, 0, sizeof(b)); - memcpy(b, output, use_len); - status = sl_se_aes_crypt_cbc(cmd_ctx, - key, - SL_SE_ENCRYPT, - SL_SE_AES_BLOCK_SIZE, - ccm_ctx->cbc_mac_state, - b, - out_buf); - - if (status != SL_STATUS_OK) { - return status; - } - } - ccm_ctx->processed_message_length += use_len; - *output_length += use_len; - len_left -= use_len; - output += use_len; - - if (len_left < SL_SE_AES_BLOCK_SIZE && ((ccm_ctx->processed_message_length + len_left) != ccm_ctx->total_message_length)) { - memcpy(ccm_ctx->final_data, input, len_left); - ccm_ctx->final_data_length = len_left; - break; - } - } - - if (status != SL_STATUS_OK) { - return status; - } - - return SL_STATUS_OK; -} - -sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *tag, - uint8_t tag_size, - uint8_t *output, - uint8_t output_size, - uint8_t *output_length) -{ - (void)output; - uint8_t q; - uint8_t ctr[SL_SE_AES_BLOCK_SIZE] = { 0 }; - uint8_t out_tag[SL_SE_AES_BLOCK_SIZE] = { 0 }; - //Check input parameters - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || tag == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_size < ccm_ctx->tag_len || output_size < ccm_ctx->final_data_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - sl_status_t status = SL_STATUS_OK; - - // Reset CTR counter. - q = 16 - 1 - (unsigned char) ccm_ctx->iv_len; - - ctr[0] = q - 1; - memcpy(ctr + 1, ccm_ctx->iv, ccm_ctx->iv_len); - - // Encrypt the tag with CTR. - uint8_t empty[SL_SE_AES_BLOCK_SIZE * SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED] = { 0 }; - status = sl_se_aes_crypt_ctr(cmd_ctx, - key, - ccm_ctx->tag_len, - NULL, - ctr, - empty, - ccm_ctx->cbc_mac_state, - out_tag); - - if (status != SL_STATUS_OK) { - memset(out_tag, 0, sizeof(out_tag)); - return status; - } - - if (ccm_ctx->mode == SL_SE_DECRYPT) { - if (memcmp_time_cst(tag, out_tag, ccm_ctx->tag_len) != 0) { - memset(tag, 0, ccm_ctx->tag_len); - return SL_STATUS_INVALID_SIGNATURE; - } - } else { - memcpy(tag, out_tag, ccm_ctx->tag_len); - } - - *output_length = 0; - return SL_STATUS_OK; -} -#endif // SLI_SE_MAJOR_VERSION_ONE - -#if defined(SLI_SE_MAJOR_VERSION_TWO) -/***************************************************************************//** - * Prepare a CCM streaming command context object to be used in subsequent - * CCM streaming function calls. - ******************************************************************************/ -sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - uint32_t total_message_length, - const uint8_t *iv, - size_t iv_len, - const uint8_t *add, - size_t add_len, - size_t tag_len) - -{ - sl_status_t status = SL_STATUS_OK; - uint8_t q; - - //Check input parameters - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (add_len > 0 && add == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (iv_len < 7 || iv_len > 13) { - return SL_STATUS_INVALID_PARAMETER; - } - - q = 16 - 1 - (unsigned char) iv_len; - if ((q < sizeof(ccm_ctx->total_message_length)) && (ccm_ctx->total_message_length >= (1UL << (q * 8)))) { - return SL_STATUS_INVALID_PARAMETER; - } - - memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); - - ccm_ctx->mode = mode; - ccm_ctx->processed_message_length = 0; - ccm_ctx->total_message_length = total_message_length; - ccm_ctx->tag_len = tag_len; - memcpy(ccm_ctx->iv, iv, iv_len); - - SE_Command_t *se_cmd = &cmd_ctx->command; - - if (total_message_length == 0) { - // The first encryption precomputes the tag in the event there is no more data. - // For decryption, the pre-computed is compared to the input tag in - // sl_se_ccm_multipart_finish. - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t tag_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.tagbuf, - tag_len); - - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_CCM_ENCRYPT - | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, 0); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &add_in); - - SE_addDataOutput(se_cmd, &tag_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(ccm_ctx->mode_specific_buffer.tagbuf, 0, sizeof(ccm_ctx->mode_specific_buffer.tagbuf)); - } - return status; - } - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - SE_DataTransfer_t message_length_in = SE_DATATRANSFER_DEFAULT(&total_message_length, sizeof(uint32_t)); - - sli_se_command_init(cmd_ctx, - ((ccm_ctx->mode == SL_SE_DECRYPT) - ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_START); - - sli_add_key_parameters(cmd_ctx, key, status); - - SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, 0); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &message_length_in); - - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &add_in); - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); - return status; - } - - return status; -} -#endif - -/***************************************************************************//** - * This function feeds an input buffer into an ongoing CCM computation. - * It is called between sl_se_ccm_multipart_starts() and sl_se_ccm_multipart_finish(). - * Can be called repeatedly. - ******************************************************************************/ -#if defined(SLI_SE_MAJOR_VERSION_TWO) -sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length) -{ - sl_status_t status = SL_STATUS_OK; - - // Check input parameters. - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (length == 0) { - return SL_STATUS_OK; - } - - if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check variable overflow - if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (length > 0 && (input == NULL || output == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - -#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) - if ((uint32_t)output + length > RAM_MEM_END) { - return SL_STATUS_INVALID_PARAMETER; - } -#endif // SLI_SE_MANAGER_HOST_SYSTEM - - SE_Command_t *se_cmd = &cmd_ctx->command; - *output_length = 0; - - // Approach: - // Encrypt or decrypt regularly with context store. The crypto DMA must have input data in the 'END' operation, thus, - // some data must be saved in the context. - - if ((ccm_ctx->final_data_length + length) < 16 && length < 16) { - if (ccm_ctx->final_data_length > 16) { - // Context is not valid. - return SL_STATUS_INVALID_PARAMETER; - } - - memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, length); - ccm_ctx->final_data_length += length; - return SL_STATUS_OK; - } - - // If there is data in final_data, this must be processed first - if (ccm_ctx->final_data_length) { - if (ccm_ctx->final_data_length > 16) { - // Context is not valid. - return SL_STATUS_INVALID_PARAMETER; - } - - // Fill up the remainder of the buffer. - memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, 16 - ccm_ctx->final_data_length); - - if (ccm_ctx->processed_message_length + 16 == ccm_ctx->total_message_length ) { - // The finish operation must have some data or the SE fails. - ccm_ctx->final_data_length = 16; - return SL_STATUS_OK; - } - - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.final_data, 16); - SE_DataTransfer_t data_out = - SE_DATATRANSFER_DEFAULT(output, 16); - - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - ((ccm_ctx->mode == SL_SE_DECRYPT) - ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - sli_add_key_parameters(cmd_ctx, key, status); - - SE_addParameter(se_cmd, 16); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(output, 0, length); - memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); - *output_length = 0; - return status; - } - ccm_ctx->processed_message_length += 16; - output += 16; - length -= (16 - ccm_ctx->final_data_length); - input += (16 - ccm_ctx->final_data_length); - ccm_ctx->final_data_length = 0; - *output_length += 16; - } - - if (length < 16) { - memcpy(ccm_ctx->mode_specific_buffer.final_data, input, length); - ccm_ctx->final_data_length += length; - return SL_STATUS_OK; - } - - // Run only multiples of 16 and store residue data in context - if (length % 16 != 0) { - uint8_t residue_data_length = length % 16; - memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - residue_data_length), residue_data_length); - length -= residue_data_length; - ccm_ctx->final_data_length = residue_data_length; - } - - if ((ccm_ctx->total_message_length == ccm_ctx->processed_message_length + length) && !ccm_ctx->final_data_length) { - // The finish operation must have some data or the SE fails. - memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - 16), 16); - ccm_ctx->final_data_length = 16; - length -= 16; - if (!length) { - return SL_STATUS_OK; - } - } - - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(input, length); - SE_DataTransfer_t data_out = - SE_DATATRANSFER_DEFAULT(output, length); - - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - ((ccm_ctx->mode == SL_SE_DECRYPT) - ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - sli_add_key_parameters(cmd_ctx, key, status); - - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(output, 0, length); - memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); - return status; - } - - *output_length += length; - ccm_ctx->processed_message_length += length; - - return status; -} -#endif - -/***************************************************************************//** - * Finish a CCM streaming operation and return the resulting CCM tag. - * It is called after sl_se_ccm_multipart_update(). - ******************************************************************************/ -#if defined(SLI_SE_MAJOR_VERSION_TWO) -sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *tag, - uint8_t tag_size, - uint8_t *output, - uint8_t output_size, - uint8_t *output_length) -{ - //Check input parameters - if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || tag == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (tag_size < ccm_ctx->tag_len || output_size < ccm_ctx->final_data_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - sl_status_t status = SL_STATUS_OK; - - if (ccm_ctx->total_message_length == 0) { - if (ccm_ctx->mode == SL_SE_DECRYPT) { - if (memcmp_time_cst(tag, ccm_ctx->mode_specific_buffer.tagbuf, ccm_ctx->tag_len) != 0) { - memset(tag, 0, ccm_ctx->tag_len); - return SL_STATUS_INVALID_SIGNATURE; - } - } else { - memcpy(tag, ccm_ctx->mode_specific_buffer.tagbuf, ccm_ctx->tag_len); - } - return SL_STATUS_OK; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.final_data, ccm_ctx->final_data_length); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, ccm_ctx->final_data_length); - SE_DataTransfer_t tag_buf = SE_DATATRANSFER_DEFAULT(tag, - ccm_ctx->tag_len); - - sli_se_command_init(cmd_ctx, - ((ccm_ctx->mode == SL_SE_DECRYPT) - ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_END); - - sli_add_key_parameters(cmd_ctx, key, status); - - SE_addParameter(se_cmd, (ccm_ctx->tag_len & 0xFFFF)); - - SE_addParameter(se_cmd, ccm_ctx->final_data_length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - if (ccm_ctx->mode == SL_SE_DECRYPT) { - SE_addDataInput(se_cmd, &tag_buf); - } else { - SE_addDataOutput(se_cmd, &tag_buf); - } - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(tag, 0, ccm_ctx->tag_len); - *output_length = 0; - return status; - } - - *output_length = ccm_ctx->final_data_length; - - return SL_STATUS_OK; -} -#endif - -/***************************************************************************//** - * This function calculates the full generic CMAC on the input buffer with - * the provided key. - ******************************************************************************/ -sl_status_t sl_se_cmac(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - const unsigned char *input, - size_t input_len, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status = SL_STATUS_OK; - - switch (key->type) { - case SL_SE_KEY_TYPE_AES_128: - case SL_SE_KEY_TYPE_AES_192: - case SL_SE_KEY_TYPE_AES_256: - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CMAC); - - // Add key parameter to command. - sli_add_key_parameters(cmd_ctx, key, status); - - // Message size parameter. - SE_addParameter(se_cmd, input_len); - - // Key metadata. - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - // Data input. - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, input_len); - SE_addDataInput(se_cmd, &in_data); - - // Data output. - SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(output, 16); - SE_addDataOutput(se_cmd, &out_tag); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Finish a CMAC streaming operation and return the resulting CMAC tag. - * It is called after sl_se_cmac_update(). - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_finish(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *output) -{ - sl_status_t status = SL_STATUS_OK; - - if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL || output == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (cmac_ctx->length >= 16U) { - // Compute previous input block by decryption of current data. - status = sl_se_aes_crypt_ecb(cmd_ctx, - key, - SL_SE_DECRYPT, - 16U, - cmac_ctx->data_out, - cmac_ctx->state); // Keep decrypted data in 'state' - } - - if (status == SL_STATUS_OK) { - // Feed previous block and unprocessed data (if any) to CMAC, - // or on data < 16 just use accumulated data in context. - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CMAC); - - // Add key parameter to command. - sli_add_key_parameters(cmd_ctx, key, status); - - // Message size parameter. - if (cmac_ctx->length >= 16U) { - SE_addParameter(se_cmd, 16U + (cmac_ctx->length & 0xFU)); - } else { - SE_addParameter(se_cmd, cmac_ctx->length); - } - - // Key metadata. - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t in_data1 = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); - SE_DataTransfer_t in_data2 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, - cmac_ctx->length & 0xFU); - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, - cmac_ctx->length); - // Data input. - if (cmac_ctx->length >= 16U) { - // Collect data from two sources. - in_data1.length &= ~SE_DATATRANSFER_REALIGN; - SE_addDataInput(se_cmd, &in_data1); - SE_addDataInput(se_cmd, &in_data2); - } else { - SE_addDataInput(se_cmd, &in_data); - } - - // Data output. - SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(output, 16U); - SE_addDataOutput(se_cmd, &out_tag); - - status = sli_se_execute_and_wait(cmd_ctx); - } - return status; -} - -/***************************************************************************//** - * Prepare a CMAC streaming command context object to be used in subsequent - * CMAC streaming function calls. - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_starts(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key) -{ - if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (key->type) { - case SL_SE_KEY_TYPE_AES_128: - case SL_SE_KEY_TYPE_AES_192: - case SL_SE_KEY_TYPE_AES_256: - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - memset(cmac_ctx, 0, sizeof(sl_se_cmac_multipart_context_t)); - return SL_STATUS_OK; -} - -/***************************************************************************//** - * This function feeds an input buffer into an ongoing CMAC computation. - * It is called between sl_se_cmac_starts() and sl_se_cmac_finish(). - * Can be called repeatedly. - ******************************************************************************/ -sl_status_t sl_se_cmac_multipart_update(sl_se_cmac_multipart_context_t *cmac_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - const uint8_t *input, - size_t input_len) -{ - sl_status_t status = SL_STATUS_OK; - - if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL || input == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - size_t pending = cmac_ctx->length & 0xFU; - - if ((cmac_ctx->length / 16U) != ((cmac_ctx->length + input_len) / 16U)) { - // Process one or more 16 byte blocks. - size_t bytes_to_process = (pending + input_len) & 0xFFFFFFF0U; - - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_ENCRYPT - | SLI_SE_COMMAND_OPTION_MODE_CBC - | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); - - // Add key parameters to command. - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, bytes_to_process); - - // Add key metadata block to command. - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command. - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); - SE_addDataInput(se_cmd, &iv_in); - - // Data input, collect data from two sources. - SE_DataTransfer_t in1 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, pending); - SE_DataTransfer_t in2 = SE_DATATRANSFER_DEFAULT(input, bytes_to_process - pending); - in1.length &= ~SE_DATATRANSFER_REALIGN; - SE_addDataInput(se_cmd, &in1); - SE_addDataInput(se_cmd, &in2); - - // Data output, discard everything except the last 16 bytes. - SE_DataTransfer_t out1 = SE_DATATRANSFER_DEFAULT(NULL, bytes_to_process - 16U); - SE_DataTransfer_t out2 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_out, 16U); - out1.length |= SE_DATATRANSFER_DISCARD; - out1.length &= ~SE_DATATRANSFER_REALIGN; - SE_addDataOutput(se_cmd, &out1); - SE_addDataOutput(se_cmd, &out2); - - SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); - SE_addDataOutput(se_cmd, &iv_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - // Store leftover data. - size_t leftover = pending + input_len - bytes_to_process; - memcpy(cmac_ctx->data_in, input + input_len - leftover, leftover); - } else { - // Not a complete 16 byte block yet, save input data for later. - memcpy(cmac_ctx->data_in + pending, input, input_len); - } - cmac_ctx->length += input_len; - return status; -} - -/***************************************************************************//** - * Compute a HMAC on a full message. - ******************************************************************************/ -sl_status_t sl_se_hmac(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_type, - const uint8_t *message, - size_t message_len, - uint8_t *output, - size_t output_len) -{ - if (cmd_ctx == NULL || key == NULL || message == NULL || output == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status = SL_STATUS_OK; - uint32_t command_word; - size_t hmac_len; - - switch (hash_type) { - case SL_SE_HASH_SHA1: - command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA1; - // SHA1 digest size is 20 bytes - hmac_len = 20; - break; - - case SL_SE_HASH_SHA224: - command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA224; - // SHA224 digest size is 28 bytes - hmac_len = 28; - break; - - case SL_SE_HASH_SHA256: - command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA256; - // SHA256 digest size is 32 bytes - hmac_len = 32; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA384; - // SHA384 digest size is 48 bytes - hmac_len = 48; - break; - - case SL_SE_HASH_SHA512: - command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA512; - // SHA512 digest size is 64 bytes - hmac_len = 64; - break; - -#endif - default: - return SL_STATUS_INVALID_PARAMETER; - } - - if (output_len < hmac_len) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, command_word); - - // Add key parameter to command. - sli_add_key_parameters(cmd_ctx, key, status); - - // Message size parameter. - SE_addParameter(se_cmd, message_len); - - // Key metadata. - sli_add_key_metadata(cmd_ctx, key, status); - - sli_add_key_input(cmd_ctx, key, status); - - // Data input. - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(message, message_len); - SE_addDataInput(se_cmd, &in_data); - - // Data output. - SE_DataTransfer_t out_hmac = SE_DATATRANSFER_DEFAULT(output, hmac_len); - SE_addDataOutput(se_cmd, &out_hmac); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * GCM buffer encryption or decryption. - ******************************************************************************/ -sl_status_t sl_se_gcm_crypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - unsigned char *tag) -{ - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || iv == NULL || tag == NULL - || ((add_len > 0) && (add == NULL)) - || ((length > 0) && (input == NULL || output == NULL)) - || ((tag_len < 4) || (tag_len > 16))) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint8_t tagbuf[16]; - sl_status_t status = SL_STATUS_OK; - - if (// IV length is required to be 96 bits for SE. - (iv_len != 96 / 8) - // AD is limited to 2^64 bits, so 2^61 bytes. - // However, on 32 bit platforms, that amount of continous data cannot be - // available. - // || (((uint64_t)add_len) >> 61 != 0) - ) { - return SL_STATUS_INVALID_PARAMETER; - } - switch (key->type) { - case SL_SE_KEY_TYPE_AES_128: - case SL_SE_KEY_TYPE_AES_192: - case SL_SE_KEY_TYPE_AES_256: - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - if (mode == SL_SE_DECRYPT) { - // Extract plaintext first. - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_addDataInput(se_cmd, &iv_in); - - SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_addDataInput(se_cmd, &aad_in); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &data_in); - - SE_DataTransfer_t tag_in = SE_DATATRANSFER_DEFAULT(tag, tag_len); - SE_addDataInput(se_cmd, &tag_in); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (output == NULL) { - data_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &data_out); - - // Execute GCM operation. - status = sli_se_execute_and_wait(cmd_ctx); - if ((status != SL_STATUS_OK) && (status != SL_STATUS_INVALID_SIGNATURE)) { - memset(output, 0, length); - return status; - } - - // Re-encrypt the extracted plaintext to generate the tag to match. - input = output; - output = NULL; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_GCM_ENCRYPT); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_addDataInput(se_cmd, &iv_in); - - SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_addDataInput(se_cmd, &aad_in); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &data_in); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (output == NULL) { - data_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &data_out); - - SE_DataTransfer_t mac_out = SE_DATATRANSFER_DEFAULT(tagbuf, sizeof(tagbuf)); - SE_addDataOutput(se_cmd, &mac_out); - - // Execute GCM operation. - status = sli_se_execute_and_wait(cmd_ctx); - if (status == SL_STATUS_OK) { - // For encryption, copy requested tag size to output tag buffer. - memcpy(tag, tagbuf, tag_len); - } else { - memset(output, 0, length); - } - - return status; -} - -/***************************************************************************//** - * GCM buffer decryption and authentication. - ******************************************************************************/ -sl_status_t sl_se_gcm_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - const unsigned char *tag) -{ - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || iv == NULL || tag == NULL - || ((add_len > 0) && (add == NULL)) - || ((length > 0) && (input == NULL || output == NULL)) - || ((tag_len < 4) || (tag_len > 16))) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status = SL_STATUS_OK; - - if (// IV length is required to be 96 bits for SE. - (iv_len != 96 / 8) - // AD is limited to 2^64 bits, so 2^61 bytes. - // However, on 32 bit platforms, that amount of continous data cannot be - // available. - // || (((uint64_t)add_len) >> 61 != 0) - ) { - return SL_STATUS_INVALID_PARAMETER; - } - switch (key->type) { - case SL_SE_KEY_TYPE_AES_128: // Fallthrough - case SL_SE_KEY_TYPE_AES_192: // Fallthrough - case SL_SE_KEY_TYPE_AES_256: - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_addDataInput(se_cmd, &iv_in); - - SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_addDataInput(se_cmd, &aad_in); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &data_in); - - SE_DataTransfer_t tag_in = SE_DATATRANSFER_DEFAULT(tag, tag_len); - SE_addDataInput(se_cmd, &tag_in); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (output == NULL) { - data_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &data_out); - - // Execute GCM operation. - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(output, 0, length); - } - - return status; -} - -#if defined(SLI_SE_MAJOR_VERSION_TWO) -/***************************************************************************//** - * GCM multipart encryption/decryption, initial stage. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - const uint8_t *iv, - size_t iv_len, - const uint8_t *add, - size_t add_len) -{ - sl_status_t status = SL_STATUS_OK; - - // Check input parameters. - if (gcm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL - || (add_len > 0 && add == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - if ((iv_len != 12) - // AD are limited to 2^64 bits, so 2^61 bytes. - // However, on 32 bit platforms, that amount of continous data cannot be - // available. - // || (((uint64_t)add_len) >> 61 != 0) - ) { - return SL_STATUS_INVALID_PARAMETER; - } - - memset(gcm_ctx, 0, sizeof(sl_se_gcm_multipart_context_t)); - - gcm_ctx->mode = mode; - gcm_ctx->len = 0; - gcm_ctx->add_len = add_len; - - SE_Command_t *se_cmd = &cmd_ctx->command; - - // The start context requires some data, either additional data or input data. - // Case add_len > 0: Run start command with additonal data to create ctx_out. - // Case add_len = 0: Store iv in gcm_ctx and run start function with input data - // in sl_se_gcm_multipart_update. In the case of zero input data or - // input data < 16 run sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in - // sl_se_gcm_multipart_finish. - if ( add_len > 0 ) { - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t ctx_out = - SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_START); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, 0); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &add_in); - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - gcm_ctx->first_operation = false; - } else { - memcpy(gcm_ctx->se_ctx, iv, iv_len); - gcm_ctx->first_operation = true; - } - return SL_STATUS_OK; -} - -#else -/***************************************************************************//** - * GCM multipart encryption/decryption, initial stage. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_cipher_operation_t mode, - const uint8_t *iv, - size_t iv_len, - const uint8_t *add, - size_t add_len) -{ - sl_status_t status = SL_STATUS_OK; - - // Check input parameters. - if (gcm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL - || (add_len > 0 && add == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - if ((iv_len != 12) - // AD are limited to 2^64 bits, so 2^61 bytes. - // However, on 32 bit platforms, that amount of continous data cannot be - // available. - // || (((uint64_t)add_len) >> 61 != 0) - ) { - return SL_STATUS_INVALID_PARAMETER; - } - - memset(gcm_ctx, 0, sizeof(sl_se_gcm_multipart_context_t)); - - gcm_ctx->mode = mode; - gcm_ctx->len = 0; - gcm_ctx->add_len = add_len; - - // The start context requires some data, either additional data or input data. - // Case add_len > 0: Run start command with additonal data to create ctx_out. - // Case add_len = 0: Store iv in gcm_ctx and run start function with input data - // in sl_se_gcm_multipart_update. In the case of zero input data or - // input data < 16 run sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in - // sl_se_gcm_multipart_finish. - if ( add_len > 0 ) { - // Encrypt: Compute tag and store it in context and output tag in finish. - // Decrypt: Compute tag and store it in context and compare it to the - // input tag in finish to verify it. - - // Explanation:The end-context in finish is currently not supporting 0 input data - // for this config. For add_len = 0 and input_length = 0 we can run - // sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in finish, so this is only - // an issue for 0 input data and add_len != 0. - SE_Command_t *se_cmd = &cmd_ctx->command; - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); - SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_DataTransfer_t tag_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->tagbuf, - sizeof(gcm_ctx->tagbuf)); - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_AES_GCM_ENCRYPT - | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, 0); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &add_in); - SE_addDataOutput(se_cmd, &tag_out); - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(gcm_ctx->tagbuf, 0, sizeof(gcm_ctx->tagbuf)); - return status; - } - - SE_DataTransfer_t ctx_out = - SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - - // Reuse the values of the command context object from the previous - // operation, and only update the command word and the output data pointer. - cmd_ctx->command.command = - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_START; - - cmd_ctx->command.data_out = &ctx_out; - - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - gcm_ctx->first_operation = false; - } else { - memcpy(gcm_ctx->se_ctx, iv, iv_len); - gcm_ctx->first_operation = true; - } - return SL_STATUS_OK; -} -#endif - -#if defined(SLI_SE_MAJOR_VERSION_TWO) -/***************************************************************************//** - * GCM multipart encryption/decryption, update stage. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length) -{ - sl_status_t status = SL_STATUS_OK; - uint8_t stored_res_length = 0; - - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (length == 0) { - return SL_STATUS_OK; - } - if (length > 0 && (input == NULL || output == NULL || output_length == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - *output_length = 0; - - // Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes. - // Also check for possible overflow. - if (gcm_ctx->len + length < gcm_ctx->len - || (uint64_t)gcm_ctx->len + length > 0xFFFFFFFE0ULL) { - return SL_STATUS_INVALID_PARAMETER; - } - SE_Command_t *se_cmd = &cmd_ctx->command; - - // The update context only support an input length as a multiple of 16. Hence, there - // there is a few cases that can happen. - - // Always: - // Case length = 0: Return SL_STATUS_OK - - // If there is no data in gcm_ctx->final_data: - // Case length < 16: Store data in gcm_ctx->final_data and return SL_STATUS_OK - // Case length == 16: Run update as normal - // Case length > 16 and length is a multiple of 16: Run update as normal - // Case length > 16 and length is not a multiple of 16: Run update as normal on the largest multiple - // and save the residue bytes in gcm_ctx->final_data. - - // If there is data in gcm_ctx->final_data: - // Case final_data_length + length < 16: Store input data in gcm_ctx and return SL_STATUS_OKAY - // Case final_data_length + length > 16: Add data to fill up the gcm_ctx->final_data-buffer, run update - // on the gcm_ctx->final_data-buffer and finally run update as explained above on the rest of the data. - - if (gcm_ctx->final_data_length) { - if ((gcm_ctx->final_data_length + length) < 16) { - memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, length); - gcm_ctx->final_data_length += length; - *output_length = 0; - return SL_STATUS_OK; - } - stored_res_length = 16 - gcm_ctx->final_data_length; - memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, stored_res_length); - - //The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, 16); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, 16); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, 16); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - gcm_ctx->first_operation = false; - gcm_ctx->len += 16; - output += 16; - - if ((length - stored_res_length) < 16) { - memcpy(gcm_ctx->final_data, input + stored_res_length, length - stored_res_length); - gcm_ctx->final_data_length = length - stored_res_length; - *output_length = 16; - return SL_STATUS_OK; - } - - length -= stored_res_length; - gcm_ctx->final_data_length = 0; - *output_length += 16; - } - if (length % 16 != 0) { - if (length > 16) { - // Input length is larger than, and a non multiple of, 16 - memcpy(gcm_ctx->final_data, input + stored_res_length + (length - (length % 16)), length % 16); - gcm_ctx->final_data_length = length % 16; - length -= length % 16; - } else { - // Input length is not a multiple of 16 - memcpy(gcm_ctx->final_data, input + stored_res_length, length); - gcm_ctx->final_data_length = length; - *output_length = 0; - return SL_STATUS_OK; - } - } - gcm_ctx->len += length; - - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(input + stored_res_length, length); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - *output_length += length; - gcm_ctx->first_operation = false; - return SL_STATUS_OK; -} - -#else // SLI_SE_MAJOR_VERSION_ONE -/***************************************************************************//** - * GCM multipart encryption/decryption, update stage. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const uint8_t *input, - uint8_t *output, - size_t *output_length) -{ - sl_status_t status = SL_STATUS_OK; - uint8_t stored_res_length = 0; - - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (length == 0) { - return SL_STATUS_OK; - } - if (length > 0 && (input == NULL || output == NULL || output_length == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - *output_length = 0; - - // Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes. - // Also check for possible overflow. - if (gcm_ctx->len + length < gcm_ctx->len - || (uint64_t)gcm_ctx->len + length > 0xFFFFFFFE0ULL) { - return SL_STATUS_INVALID_PARAMETER; - } - SE_Command_t *se_cmd = &cmd_ctx->command; - - // The finish command will return the wrong tag or INVALID SIGNATURE if there is no - // input data. There is no way to know when sl_se_gcm_multipart_update is called for the last time, so there must - // always be data stored. - // The update context only support an input length as a multiple of 16. Hence, there - // there is a few cases that can happen. - - // Always: - // Case length = 0: Return SL_STATUS_OK - - // If there is no data in gcm_ctx->final_data - // Case length < 16: Store data in gcm_ctx->final_data and return SL_STATUS_OK - // Case length > 16 and length is not a multiple of 16: Run update as normal on the largest multiple - // and save the residue bytes in gcm_ctx->final_data. - // Case length == 16: store the current se_ctx in gcm_ctx->previous_se_ctx and store input data in final_data, - // then run update as normal on the input data. - // Case length > 16 and length is a multible of 16: run update twice, one with all input data and one with - // all input data except the last 16 bytes. The out_ctx from each run are stored in gcm_ctx->se_ctx and - // gcm_ctx->previous_se_ctx respectively. The last 16 bytes are then stored in final_data. - // NOTE:output_length will include all encrypted/decrypted data. - - // If there is data in gcm_ctx->final_data - // Case final_data_length + length < 16: Store input data in gcm_ctx and return SL_STATUS_OKAY - // Case final_data_length + length > 16: Add data to fill up the gcm_ctx->final_data-buffer, run update - // on the gcm_ctx->final_data-buffer and finally run update as explained above on the rest of the data. - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((output > input) && (output < (input + length))) { - memmove(output, input, length); - input = output; - } - - // Check for data in final_data_length. - if (gcm_ctx->final_data_length && gcm_ctx->final_data_length != 16) { - if ((gcm_ctx->final_data_length + length) < 16) { - memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, length); - gcm_ctx->final_data_length += length; - *output_length = 0; - return SL_STATUS_OK; - } - - if ((gcm_ctx->final_data_length + length) == 16) { - memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - } - stored_res_length = 16 - gcm_ctx->final_data_length; - memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, stored_res_length); - - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, 16); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, 16); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, 16); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - gcm_ctx->first_operation = false; - gcm_ctx->len += 16; - output += 16; - - if ((gcm_ctx->final_data_length + length) == 16) { - gcm_ctx->final_data_length = 16; - *output_length = 16; - return SL_STATUS_OK; - } - - if ((length - stored_res_length) < 16) { - memcpy(gcm_ctx->final_data, input + stored_res_length, length - stored_res_length); - gcm_ctx->final_data_length = length - stored_res_length; - *output_length = 16; - return SL_STATUS_OK; - } - - length -= stored_res_length; - gcm_ctx->final_data_length = 0; - *output_length += 16; - } - if (length % 16 != 0) { - if (length > 16) { - //Input length is larger than, and a non multiple of, 16 - memcpy(gcm_ctx->final_data, input + stored_res_length + (length - (length % 16)), length % 16); - gcm_ctx->final_data_length = length % 16; - length -= length % 16; - } else { - //Input length is not a multiple of 16 - memcpy(gcm_ctx->final_data, input + stored_res_length, length); - gcm_ctx->final_data_length = length; - *output_length = 0; - return SL_STATUS_OK; - } - } else { - if (length > 16) { - //If length is larger than, and a multiple of, 16, we must compute a context without the last 16 bytes - //and store it as the previous context in case there is no more data. - memcpy(gcm_ctx->final_data, input + stored_res_length + (length - 16), 16); - gcm_ctx->final_data_length = 16; - - //The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(input + stored_res_length, length - 16); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length - 16); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, length - 16); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - - // Only process the last 16 bytes in the last operation. - output += (length - 16); - input += (length - 16); - gcm_ctx->first_operation = false; - gcm_ctx->len += (length - 16); - *output_length += (length - 16); - - length = 16; - - memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - } else { - memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - memcpy(gcm_ctx->final_data, input + stored_res_length, length); - gcm_ctx->final_data_length = length; - } - } - gcm_ctx->len += length; - - // The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(input + stored_res_length, length); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, - sizeof(gcm_ctx->se_ctx)); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - - SE_addDataOutput(se_cmd, &data_out); - - SE_addDataOutput(se_cmd, &ctx_out); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); - return status; - } - *output_length += length; - gcm_ctx->first_operation = false; - return SL_STATUS_OK; -} -#endif - -/***************************************************************************//** - * GCM multipart encryption/decryption, finish stage. - ******************************************************************************/ -sl_status_t sl_se_gcm_multipart_finish(sl_se_gcm_multipart_context_t *gcm_ctx, - sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - uint8_t *tag, - uint8_t tag_length, - uint8_t *output, - uint8_t output_size, - uint8_t *output_length) -{ - sl_status_t status = SL_STATUS_OK; - uint32_t tmpbuf[4]; - uint8_t length; - if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL || tag == NULL || tag_length < 4 || tag_length > 16) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((gcm_ctx->final_data_length != 16) - && (output_size < gcm_ctx->final_data_length)) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - length = gcm_ctx->final_data_length; - gcm_ctx->len += ((length % 16 != 0) ? length : 0); - - #if defined(SLI_SE_MAJOR_VERSION_ONE) - if ((gcm_ctx->add_len > 0) && (gcm_ctx->len == 0)) { - if (gcm_ctx->mode == SL_SE_DECRYPT) { - if (memcmp_time_cst(tag, gcm_ctx->tagbuf, tag_length)) { - memset(tag, 0, tag_length); - return SL_STATUS_INVALID_SIGNATURE; - } - } else { - memcpy(tag, gcm_ctx->tagbuf, tag_length); - } - return SL_STATUS_OK; - } - #endif - -#if defined(SLI_SE_MAJOR_VERSION_ONE) - // For xG21 devices, since the multipart finish command cannot handle cases without - // more data being passed as part of the finish call, there are two cases for which - // a finish call can condense into a one-shot operation: - // 1. The 'first operation' flag is set, meaning no multipart context has been started - // 2. There was no AAD input and the total input length equals 16 bytes. In such a case, - // all information needed for a one-shot operation is still present in the context, - // being the 16 bytes of input in the lookback buffer. In such a case, be careful to - // not return ciphertext/plaintext to the user a second time, since it has already - // been returned as part of the initial call to `_update`. - if (gcm_ctx->first_operation || (gcm_ctx->add_len == 0 && gcm_ctx->len == 16)) { -#else - // Devices xG23 or newer support a finish call without data, so the only case for - // condensing a multipart finish operation into a one-shot operation is when the - // 'first operation' flag is set, meaning no multipart context has been started - if (gcm_ctx->first_operation) { -#endif - if (gcm_ctx->mode == SL_SE_ENCRYPT) { - status = sl_se_gcm_crypt_and_tag(cmd_ctx, - key, - gcm_ctx->mode, - length, - gcm_ctx->se_ctx, //iv - 12, //iv_len - NULL, - 0, - gcm_ctx->final_data, - (length < 16 ? output : (unsigned char*)tmpbuf), - tag_length, - tag); - } else { - status = sl_se_gcm_auth_decrypt(cmd_ctx, - key, - length, - gcm_ctx->se_ctx, //iv - 12, //iv_len - NULL, - 0, - gcm_ctx->final_data, - (length < 16 ? output : (unsigned char*)tmpbuf), - tag_length, - tag); - } - if (status != SL_STATUS_OK) { - *output_length = 0; - memset(tag, 0, tag_length); - return status; - } - if (length < 16) { - *output_length = length; - } else { - *output_length = 0; - } - return SL_STATUS_OK; - } - - // Construct GCM LenA || LenC block into temporary buffer - tmpbuf[0] = __REV(gcm_ctx->add_len >> 29); - tmpbuf[1] = __REV((gcm_ctx->add_len << 3) & 0xFFFFFFFFUL); - tmpbuf[2] = __REV(gcm_ctx->len >> 29); - tmpbuf[3] = __REV((gcm_ctx->len << 3) & 0xFFFFFFFFUL); - - SE_DataTransfer_t data_in = - SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, length); - - #if defined(SLI_SE_MAJOR_VERSION_ONE) - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT((length % 16 != 0 || length == 0) ? gcm_ctx->se_ctx : gcm_ctx->previous_se_ctx, sizeof(gcm_ctx->previous_se_ctx)); - #else - SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); - #endif - - SE_DataTransfer_t lenalenc_in = SE_DATATRANSFER_DEFAULT(&tmpbuf[0], - sizeof(tmpbuf)); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (length == 16) { - data_out.data = NULL; - data_out.length |= SE_DATATRANSFER_DISCARD; - } - - SE_DataTransfer_t gcm_tag = SE_DATATRANSFER_DEFAULT(tag, tag_length); - - sli_se_command_init(cmd_ctx, - (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT - : SLI_SE_COMMAND_AES_GCM_ENCRYPT) - | tag_length << 8 | SLI_SE_COMMAND_OPTION_CONTEXT_END); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, 0); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_addDataInput(se_cmd, &iv_ctx_in); - SE_addDataInput(se_cmd, &data_in); - SE_addDataInput(se_cmd, &lenalenc_in); - - if (gcm_ctx->mode == SL_SE_DECRYPT) { - SE_addDataInput(se_cmd, &gcm_tag); - } - - SE_addDataOutput(se_cmd, &data_out); - - if (gcm_ctx->mode == SL_SE_ENCRYPT) { - SE_addDataOutput(se_cmd, &gcm_tag); - } - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - if (gcm_ctx->mode == SL_SE_ENCRYPT) { - memset(tag, 0, tag_length); - } - *output_length = 0; - return status; - } - - if (length < 16) { - *output_length = length; - } else { - *output_length = 0; - } - - return SL_STATUS_OK; -} - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -/***************************************************************************//** - * ChaCha20 buffer encryption/decryption, as defined by RFC8439 section 2.4. - ******************************************************************************/ -sl_status_t sl_se_chacha20_crypt(sl_se_command_context_t *cmd_ctx, - sl_se_cipher_operation_t mode, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char initial_counter[4], - const unsigned char nonce[12], - const unsigned char *input, - unsigned char *output) -{ - if (cmd_ctx == NULL || key == NULL || initial_counter == NULL || nonce == NULL - || input == NULL || output == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (key->type != SL_SE_KEY_TYPE_CHACHA20) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - sli_se_command_init(cmd_ctx, - (mode == SL_SE_ENCRYPT - ? SLI_SE_COMMAND_CHACHA20_ENCRYPT - : SLI_SE_COMMAND_CHACHA20_DECRYPT) - | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - // Add initial counter to command - SE_DataTransfer_t counter = SE_DATATRANSFER_DEFAULT(initial_counter, 4); - SE_addDataInput(se_cmd, &counter); - - // Add nonce/IV to command - SE_DataTransfer_t iv = SE_DATATRANSFER_DEFAULT(nonce, 12); - SE_addDataInput(se_cmd, &iv); - - // Add input data to command - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &in); - - // Request output data from command - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); - SE_addDataOutput(se_cmd, &out); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * ChaCha20-Poly1305 authenticated encryption with additional data, as defined - * by RFC8439 section 2.8. - ******************************************************************************/ -sl_status_t sl_se_chacha20_poly1305_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - unsigned char *tag) -{ - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || nonce == NULL - || ((add_len > 0) && (add == NULL)) - || ((length > 0) && (input == NULL))) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - if (key->type != SL_SE_KEY_TYPE_CHACHA20) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHACHAPOLY_ENCRYPT); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t nonce_in = SE_DATATRANSFER_DEFAULT(nonce, 12); - SE_addDataInput(se_cmd, &nonce_in); - - SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_addDataInput(se_cmd, &aad_in); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &data_in); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (output == NULL) { - data_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &data_out); - - SE_DataTransfer_t mac_out = SE_DATATRANSFER_DEFAULT(tag, 16); - if (tag == NULL) { - mac_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &mac_out); - - // Execute AEAD operation. - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * ChaCha20-Poly1305 authenticated decryption with additional data, as defined - * by RFC8439 section 2.8. - ******************************************************************************/ -sl_status_t sl_se_chacha20_poly1305_auth_decrypt(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *add, size_t add_len, - const unsigned char *input, - unsigned char *output, - const unsigned char tag[16]) -{ - // Check input parameters. - if (cmd_ctx == NULL || key == NULL || nonce == NULL || tag == NULL - || ((add_len > 0) && (add == NULL)) - || ((length > 0) && (input == NULL))) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - if (key->type != SL_SE_KEY_TYPE_CHACHA20) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHACHAPOLY_DECRYPT); - - sli_add_key_parameters(cmd_ctx, key, status); - SE_addParameter(se_cmd, add_len); - SE_addParameter(se_cmd, length); - - sli_add_key_metadata(cmd_ctx, key, status); - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t nonce_in = SE_DATATRANSFER_DEFAULT(nonce, 12); - SE_addDataInput(se_cmd, &nonce_in); - - SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); - SE_addDataInput(se_cmd, &aad_in); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &data_in); - - SE_DataTransfer_t mac_in = SE_DATATRANSFER_DEFAULT(tag, 16); - SE_addDataInput(se_cmd, &mac_in); - - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); - if (output == NULL) { - data_out.length |= SE_DATATRANSFER_DISCARD; - } - SE_addDataOutput(se_cmd, &data_out); - - // Execute AEAD operation. - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Generate a MAC (message authentication code) for a given message, according - * to RFC8439 section 2.8 but bypassing the encryption step. - ******************************************************************************/ -sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - size_t length, - const unsigned char nonce[12], - const unsigned char *input, - unsigned char *tag) -{ - if (cmd_ctx == NULL || key == NULL || nonce == NULL || tag == NULL - || ((length > 0) && (input == NULL))) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (key->type != SL_SE_KEY_TYPE_CHACHA20) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_POLY1305_KEY_MAC); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, length); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - // Add nonce/IV to command - SE_DataTransfer_t iv = SE_DATATRANSFER_DEFAULT(nonce, 12); - SE_addDataInput(se_cmd, &iv); - - // Add input data to command - SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); - SE_addDataInput(se_cmd, &in); - - // Request tag from command - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(tag, 16); - SE_addDataOutput(se_cmd, &out); - - return sli_se_execute_and_wait(cmd_ctx); -} -#endif - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include "sl_assert.h" +#include + +/// @addtogroup sl_se_manager +/// @{ + +uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size) +{ + //Don't try to optimise this function for performance, it's time constant for security reasons + uint32_t diff = 0; + uint32_t i = 0; + for (i = 0; i < size; i++) { + diff |= (*(in1 + i) ^ (*(in2 + i))); + } + + return (diff > 0); +} + +// ----------------------------------------------------------------------------- +// Global Functions + +/***************************************************************************//** + * AES-ECB block encryption/decryption. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_ecb(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + const unsigned char *input, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL + || (length & 0xFU) != 0U) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + sli_se_command_init(cmd_ctx, + (mode == SL_SE_ENCRYPT + ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) + | SLI_SE_COMMAND_OPTION_MODE_ECB + | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &in); + + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); + SE_addDataOutput(se_cmd, &out); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * AES-CBC buffer encryption/decryption. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cbc(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL + || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + // Input length must be a multiple of 16 bytes which is the AES block length + if (length & 0xf) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, + (mode == SL_SE_ENCRYPT + ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) + | SLI_SE_COMMAND_OPTION_MODE_CBC + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, 16); + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &in); + + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); + SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(iv, 16); + SE_addDataOutput(se_cmd, &out); + SE_addDataOutput(se_cmd, &iv_out); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * AES-CFB128 buffer encryption/decryption. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cfb128(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + uint32_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL + || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t n = iv_off ? *iv_off : 0; + uint32_t processed = 0; + sl_status_t command_status = SL_STATUS_OK; + + while (processed < length) { + if (n > 0) { + // start by filling up the IV + if (mode == SL_SE_ENCRYPT) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } else { + // process one ore more blocks of data + uint32_t iterations = (length - processed) / 16; + + if (iterations > 0) { + sli_se_command_init(cmd_ctx, + (mode == SL_SE_ENCRYPT + ? SLI_SE_COMMAND_AES_ENCRYPT : SLI_SE_COMMAND_AES_DECRYPT) + | SLI_SE_COMMAND_OPTION_MODE_CFB + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, command_status); + // Message size (number of bytes) + SE_addParameter(se_cmd, iterations * 16); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, command_status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, command_status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, 16); + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(&input[processed], iterations * 16); + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &in); + + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(&output[processed], iterations * 16); + SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(iv, 16); + SE_addDataOutput(se_cmd, &out); + SE_addDataOutput(se_cmd, &iv_out); + + command_status = sli_se_execute_and_wait(cmd_ctx); + processed += iterations * 16; + if (command_status != SL_STATUS_OK) { + return command_status; + } + } + + while ((length - processed) > 0) { + if (n == 0) { + // Need to update the IV but don't have a full block of input to pass + // to the SE. + command_status = sl_se_aes_crypt_ecb(cmd_ctx, key, SL_SE_ENCRYPT, 16U, iv, iv); + if (command_status != SL_STATUS_OK) { + return command_status; + } + } + // Save remainder to IV + if (mode == SL_SE_ENCRYPT) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( iv_off ) { + *iv_off = n; + } + + return command_status; +} + +/***************************************************************************//** + * AES-CFB8 buffer encryption/decryption. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_cfb8(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + unsigned char c; + unsigned char ov[17]; + sl_status_t ret = SL_STATUS_OK; + + if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL + || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + while (length--) { + memcpy(ov, iv, 16U); + if ((ret = sl_se_aes_crypt_ecb(cmd_ctx, key, SL_SE_ENCRYPT, 16U, iv, iv)) + != SL_STATUS_OK) { + return ret; + } + + if (mode == SL_SE_DECRYPT) { + ov[16] = *input; + } + + c = *output++ = (unsigned char)(iv[0] ^ *input++); + + if (mode == SL_SE_ENCRYPT) { + ov[16] = c; + } + + memcpy(iv, ov + 1, 16U); + } + + return ret; +} + +/***************************************************************************//** + * Increment the input nonce counter by one + ******************************************************************************/ +static void increment_nonce_counter(uint8_t block_end, unsigned char nonce_counter[]) +{ + for (size_t i = 0u; i < SL_SE_AES_BLOCK_SIZE; i++) { + nonce_counter[block_end - i] = nonce_counter[block_end - i] + 1u; + if (nonce_counter[block_end - i] != 0u) { + // did not overflow so no need to increment the value at next index + break; + } + } +} + +#if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1) +/***************************************************************************//** + * Prepare the SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE byte + * wide stream block buffer that will be used as nonce counter for + * encryption/decryption. + ******************************************************************************/ +static void prepare_nonce_counter(unsigned char nonce_counter[], + unsigned char stream_block[]) +{ + uint8_t no_of_blocks = ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) / SL_SE_AES_BLOCK_SIZE); + // place the most recent counter in the first stream block + memcpy(stream_block, + nonce_counter, + SL_SE_AES_BLOCK_SIZE); + + for (size_t i = 0; i < no_of_blocks - 1u; i++) { + // Use the first block's reference counter to update the other + // blocks since it holds the most recent counter information. + memcpy(&stream_block[i * SL_SE_AES_BLOCK_SIZE + SL_SE_AES_BLOCK_SIZE], + &stream_block[i * SL_SE_AES_BLOCK_SIZE], + SL_SE_AES_BLOCK_SIZE); + increment_nonce_counter(((i + 2u) * SL_SE_AES_BLOCK_SIZE) - 1u, stream_block); + } + + // Store the largest counter back in the nonce counter buffer + memcpy(nonce_counter, + &stream_block[(no_of_blocks - 1u) * SL_SE_AES_BLOCK_SIZE], + SL_SE_AES_BLOCK_SIZE); +} +#endif // SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1 + +/***************************************************************************//** + * AES-CTR buffer encryption/decryption. + ******************************************************************************/ +sl_status_t sl_se_aes_crypt_ctr(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + uint32_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE], + const unsigned char *input, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL + || (length != 0 && (input == NULL || output == NULL)) + || nonce_counter == NULL || stream_block == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t n = nc_off ? *nc_off : 0; + uint32_t processed = 0; + sl_status_t command_status = SL_STATUS_OK; + + while (processed < length) { + if (n > 0) { + // start by filling up the IV + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) - 1u); + processed++; + } else { + // process one or more blocks of data + uint32_t iterations = (length - processed) / SL_SE_AES_BLOCK_SIZE; + + if (iterations > 0) { + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_ENCRYPT + | SLI_SE_COMMAND_OPTION_MODE_CTR + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, command_status); + // Message size (number of bytes) + SE_addParameter(se_cmd, iterations * SL_SE_AES_BLOCK_SIZE); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, command_status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, command_status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(nonce_counter, SL_SE_AES_BLOCK_SIZE); + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(&input[processed], iterations * SL_SE_AES_BLOCK_SIZE); + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &in); + + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(&output[processed], iterations * SL_SE_AES_BLOCK_SIZE); + SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(nonce_counter, SL_SE_AES_BLOCK_SIZE); + SE_addDataOutput(se_cmd, &out); + SE_addDataOutput(se_cmd, &iv_out); + + command_status = sli_se_execute_and_wait(cmd_ctx); + processed += iterations * SL_SE_AES_BLOCK_SIZE; + if (command_status != SL_STATUS_OK) { + return command_status; + } + } + + while ((length - processed) > 0) { + if (n == 0) { + // Get a new stream block + unsigned char *counter_ptr = NULL; + #if (SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1) + // Use the nonce counter buffer as the reference to create nonce counter blocks + // needed to compute the key stream blocks. Also, update the nonce counter buffer + // to store the latest block. + prepare_nonce_counter(nonce_counter, stream_block); + // The key stream buffer now holds the nonce counter + counter_ptr = stream_block; + #else + counter_ptr = nonce_counter; + #endif // SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED > 1 + + command_status = sl_se_aes_crypt_ecb(cmd_ctx, + key, + SL_SE_ENCRYPT, + SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE, + counter_ptr, + stream_block); + if (command_status != SL_STATUS_OK) { + return command_status; + } + increment_nonce_counter(SL_SE_AES_BLOCK_SIZE - 1u, nonce_counter); + } + // Save remainder to IV + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & ((SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED * SL_SE_AES_BLOCK_SIZE) - 1u); + processed++; + } + } + } + + if ( nc_off ) { + *nc_off = n; + } + + return command_status; +} + +/***************************************************************************//** + * AES-CCM buffer encryption. + ******************************************************************************/ +sl_status_t sl_se_ccm_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + unsigned char *tag, size_t tag_len) +{ + if (cmd_ctx == NULL || key == NULL || (tag_len > 0 && tag == NULL) || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (add_len > 0 && add == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (length > 0 && (input == NULL || output == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + unsigned char q; + sl_status_t command_status = SL_STATUS_OK; + + // Test for invalid (too long) message length. This test is included here because + // the SE does not implement the test. When the SE ultimately implements the test + // the following test can be removed. + q = 16 - 1 - (unsigned char) iv_len; + if ((q < sizeof(length)) && (length >= (1UL << (q * 8)))) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Also implies q is within bounds + if (iv_len < 7 || iv_len > 13) { + return SL_STATUS_INVALID_PARAMETER; + } + +#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) + if ((uint32_t)output + length > RAM_MEM_END) { + return SL_STATUS_INVALID_PARAMETER; + } +#endif // SLI_SE_MANAGER_HOST_SYSTEM + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CCM_ENCRYPT); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, command_status); + // Message size (number of bytes) + SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, command_status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, command_status); + + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, length); + SE_DataTransfer_t in_add = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t in_nonce = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_addDataInput(se_cmd, &in_nonce); + SE_addDataInput(se_cmd, &in_add); + SE_addDataInput(se_cmd, &in_data); + + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, length); + SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(tag, tag_len); + SE_addDataOutput(se_cmd, &out_data); + SE_addDataOutput(se_cmd, &out_tag); + + command_status = sli_se_execute_and_wait(cmd_ctx); + return command_status; +} + +/***************************************************************************//** + * AES-CCM buffer decryption. + ******************************************************************************/ +sl_status_t sl_se_ccm_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + const unsigned char *tag, size_t tag_len) +{ + if (cmd_ctx == NULL || key == NULL || tag == NULL || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (add_len > 0 && add == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (length > 0 && (input == NULL || output == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + unsigned char q; + sl_status_t command_status = SL_STATUS_OK; + + // Test for invalid (too long) message length. This test is included here because + // the SE does not implement the test. When the SE ultimately implements the test + // the following test can be removed. + q = 16 - 1 - (unsigned char) iv_len; + if ((q < sizeof(length)) && (length >= (1UL << (q * 8)))) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_len == 2 || tag_len == 0 || tag_len > 16 || tag_len % 2 != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Also implies q is within bounds */ + if (iv_len < 7 || iv_len > 13) { + return SL_STATUS_INVALID_PARAMETER; + } + +#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) + if ((uint32_t)output + length > RAM_MEM_END) { + return SL_STATUS_INVALID_PARAMETER; + } +#endif // SLI_SE_MANAGER_HOST_SYSTEM + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CCM_DECRYPT); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, command_status); + // Message size (number of bytes) + SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, command_status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, command_status); + + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, length); + SE_DataTransfer_t in_add = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t in_nonce = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_addDataInput(se_cmd, &in_nonce); + SE_addDataInput(se_cmd, &in_add); + SE_addDataInput(se_cmd, &in_data); + + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, length); + SE_addDataOutput(se_cmd, &out_data); + SE_DataTransfer_t in_tag = SE_DATATRANSFER_DEFAULT(tag, tag_len); + SE_addDataInput(se_cmd, &in_tag); + + command_status = sli_se_execute_and_wait(cmd_ctx); + if (command_status == SL_STATUS_OK) { + return SL_STATUS_OK; + } else { + memset(output, 0, length); + return command_status; + } +} + +#if defined(SLI_SE_MAJOR_VERSION_ONE) +sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + uint32_t total_message_length, + const uint8_t *iv, + size_t iv_len, + const uint8_t *aad, + size_t aad_len, + size_t tag_len) +{ + sl_status_t status = SL_STATUS_OK; + uint8_t q; + uint8_t b[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint8_t tag_out[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint8_t cbc_mac_state[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint8_t nonce_counter[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint32_t len_left; + + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (aad_len > 0 && aad == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (iv_len < 7 || iv_len > 13) { + return SL_STATUS_INVALID_PARAMETER; + } + + // q is the the octet length of Q which again is a bit string representation of + // the octet length of the payload. + q = 16 - 1 - (uint8_t) iv_len; + + // The parameter q determines the maximum length of the payload: by definition, p<2^(8*q), + // where p is payload. + if ((q < sizeof(total_message_length)) && (total_message_length >= (1UL << (q * 8)))) { + return SL_STATUS_INVALID_PARAMETER; + } + memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); + + // Format first input block B_O according to the formatting function: + + // 0 .. 0 flags + // 1 .. iv_len nonce (aka iv) + // iv_len+1 .. 15 length + // + // With flags as (bits): + // 7 0 + // 6 add present? + // 5 .. 3 (t - 2) / 2 + // 2 .. 0 q - 1 + + b[0] = 0; + b[0] |= (aad_len > 0) << 6; + b[0] |= ((tag_len - 2) / 2) << 3; + b[0] |= q - 1; + + memcpy(b + 1, iv, iv_len); + + len_left = total_message_length; + for (uint32_t i = 0; i < q; i++, len_left >>= 8) { + b[15 - i] = (unsigned char)(len_left & 0xFF); + } + + ccm_ctx->mode = mode; + ccm_ctx->processed_message_length = 0; + ccm_ctx->total_message_length = total_message_length; + ccm_ctx->tag_len = tag_len; + ccm_ctx->mode = mode; + ccm_ctx->iv_len = iv_len; + memcpy(ccm_ctx->iv, iv, iv_len); + + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + SL_SE_AES_BLOCK_SIZE, + cbc_mac_state, + b, + tag_out); + + if (status != SL_STATUS_OK) { + return status; + } + + // If there is additional data, update using CBC. Must be done + // blockwise to achieve the same behaviour as CBC-MAC. + if (aad_len > 0) { + uint8_t use_len; + len_left = aad_len; + memset(b, 0, sizeof(b)); + // First block. + b[0] = (unsigned char)((aad_len >> 8) & 0xFF); + b[1] = (unsigned char)((aad_len) & 0xFF); + use_len = len_left < SL_SE_AES_BLOCK_SIZE - 2 ? len_left : 16 - 2; + memcpy(b + 2, aad, use_len); + len_left -= use_len; + aad += use_len; + + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + SL_SE_AES_BLOCK_SIZE, + cbc_mac_state, + b, + tag_out); + if (status != SL_STATUS_OK) { + return status; + } + + while (len_left) { + use_len = len_left > 16 ? 16 : len_left; + + memset(b, 0, sizeof(b)); + memcpy(b, aad, use_len); + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + SL_SE_AES_BLOCK_SIZE, + cbc_mac_state, + b, + tag_out); + + if (status != SL_STATUS_OK) { + return status; + } + len_left -= use_len; + aad += use_len; + } + } + + memcpy(ccm_ctx->cbc_mac_state, cbc_mac_state, sizeof(cbc_mac_state)); + + // Prepare nonce counter for encryption/decryption operation. + nonce_counter[0] = q - 1; + memcpy(nonce_counter + 1, iv, iv_len); + memset(nonce_counter + 1 + iv_len, 0, q); + nonce_counter[15] = 1; + + memcpy(ccm_ctx->nonce_counter, nonce_counter, sizeof(ccm_ctx->nonce_counter)); + + return SL_STATUS_OK; +} + +sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + *output_length = 0; + + uint8_t out_buf[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint8_t empty[SL_SE_AES_BLOCK_SIZE * SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED] = { 0 }; + uint8_t b[SL_SE_AES_BLOCK_SIZE] = { 0 }; + + size_t len_left; + + // Check input parameters. + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length == 0) { + return SL_STATUS_OK; + } + + // Check variable overflow + if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length > 0 && (input == NULL || output == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((uint32_t)output + length > RAM_MEM_END) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Support partial overlap. + if ((output > input) && (output < (input + length))) { + memmove(output, input, length); + input = output; + } + + if (length + ccm_ctx->final_data_length < SL_SE_AES_BLOCK_SIZE && length < SL_SE_AES_BLOCK_SIZE && ccm_ctx->processed_message_length + length != ccm_ctx->total_message_length ) { + if (ccm_ctx->final_data_length > SL_SE_AES_BLOCK_SIZE) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + memcpy(ccm_ctx->final_data + ccm_ctx->final_data_length, input, length); + ccm_ctx->final_data_length += length; + *output_length = 0; + return SL_STATUS_OK; + } + + len_left = length + ccm_ctx->final_data_length; + + // Authenticate and {en,de}crypt the message. + + // The only difference between encryption and decryption is + // the respective order of authentication and {en,de}cryption. + while (len_left > 0 ) { + uint8_t use_len = len_left > SL_SE_AES_BLOCK_SIZE ? SL_SE_AES_BLOCK_SIZE : len_left; + + memset(b, 0, sizeof(b)); + + // Process data stored in context first. + if (ccm_ctx->final_data_length > 0) { + if (ccm_ctx->final_data_length > SL_SE_AES_BLOCK_SIZE) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + memcpy(b, ccm_ctx->final_data, ccm_ctx->final_data_length); + memcpy(b + ccm_ctx->final_data_length, input, SL_SE_AES_BLOCK_SIZE - ccm_ctx->final_data_length); + input += SL_SE_AES_BLOCK_SIZE - ccm_ctx->final_data_length; + ccm_ctx->final_data_length = 0; + } else { + memcpy(b, input, use_len); + input += use_len; + } + if (ccm_ctx->mode == SL_SE_ENCRYPT) { + // Authenticate input. + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + SL_SE_AES_BLOCK_SIZE, + ccm_ctx->cbc_mac_state, + b, + out_buf); + + if (status != SL_STATUS_OK) { + return status; + } + } + // Encrypt/decrypt data with CTR. + status = sl_se_aes_crypt_ctr(cmd_ctx, + key, + use_len, + NULL, + ccm_ctx->nonce_counter, + empty, + b, + output); + + if (ccm_ctx->mode == SL_SE_DECRYPT) { + // Authenticate output. + memset(b, 0, sizeof(b)); + memcpy(b, output, use_len); + status = sl_se_aes_crypt_cbc(cmd_ctx, + key, + SL_SE_ENCRYPT, + SL_SE_AES_BLOCK_SIZE, + ccm_ctx->cbc_mac_state, + b, + out_buf); + + if (status != SL_STATUS_OK) { + return status; + } + } + ccm_ctx->processed_message_length += use_len; + *output_length += use_len; + len_left -= use_len; + output += use_len; + + if (len_left < SL_SE_AES_BLOCK_SIZE && ((ccm_ctx->processed_message_length + len_left) != ccm_ctx->total_message_length)) { + memcpy(ccm_ctx->final_data, input, len_left); + ccm_ctx->final_data_length = len_left; + break; + } + } + + if (status != SL_STATUS_OK) { + return status; + } + + return SL_STATUS_OK; +} + +sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_size, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length) +{ + (void)output; + uint8_t q; + uint8_t ctr[SL_SE_AES_BLOCK_SIZE] = { 0 }; + uint8_t out_tag[SL_SE_AES_BLOCK_SIZE] = { 0 }; + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || tag == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_size < ccm_ctx->tag_len || output_size < ccm_ctx->final_data_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status = SL_STATUS_OK; + + // Reset CTR counter. + q = 16 - 1 - (unsigned char) ccm_ctx->iv_len; + + ctr[0] = q - 1; + memcpy(ctr + 1, ccm_ctx->iv, ccm_ctx->iv_len); + + // Encrypt the tag with CTR. + uint8_t empty[SL_SE_AES_BLOCK_SIZE * SLI_SE_AES_CTR_NUM_BLOCKS_BUFFERED] = { 0 }; + status = sl_se_aes_crypt_ctr(cmd_ctx, + key, + ccm_ctx->tag_len, + NULL, + ctr, + empty, + ccm_ctx->cbc_mac_state, + out_tag); + + if (status != SL_STATUS_OK) { + memset(out_tag, 0, sizeof(out_tag)); + return status; + } + + if (ccm_ctx->mode == SL_SE_DECRYPT) { + if (memcmp_time_cst(tag, out_tag, ccm_ctx->tag_len) != 0) { + memset(tag, 0, ccm_ctx->tag_len); + return SL_STATUS_INVALID_SIGNATURE; + } + } else { + memcpy(tag, out_tag, ccm_ctx->tag_len); + } + + *output_length = 0; + return SL_STATUS_OK; +} +#endif // SLI_SE_MAJOR_VERSION_ONE + +#if defined(SLI_SE_MAJOR_VERSION_TWO) +/***************************************************************************//** + * Prepare a CCM streaming command context object to be used in subsequent + * CCM streaming function calls. + ******************************************************************************/ +sl_status_t sl_se_ccm_multipart_starts(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + uint32_t total_message_length, + const uint8_t *iv, + size_t iv_len, + const uint8_t *add, + size_t add_len, + size_t tag_len) + +{ + sl_status_t status = SL_STATUS_OK; + uint8_t q; + + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (add_len > 0 && add == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_len == 2 || tag_len > 16 || tag_len % 2 != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (iv_len < 7 || iv_len > 13) { + return SL_STATUS_INVALID_PARAMETER; + } + + q = 16 - 1 - (unsigned char) iv_len; + if ((q < sizeof(ccm_ctx->total_message_length)) && (ccm_ctx->total_message_length >= (1UL << (q * 8)))) { + return SL_STATUS_INVALID_PARAMETER; + } + + memset(ccm_ctx, 0, sizeof(sl_se_ccm_multipart_context_t)); + + ccm_ctx->mode = mode; + ccm_ctx->processed_message_length = 0; + ccm_ctx->total_message_length = total_message_length; + ccm_ctx->tag_len = tag_len; + memcpy(ccm_ctx->iv, iv, iv_len); + + SE_Command_t *se_cmd = &cmd_ctx->command; + + if (total_message_length == 0) { + // The first encryption precomputes the tag in the event there is no more data. + // For decryption, the pre-computed is compared to the input tag in + // sl_se_ccm_multipart_finish. + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t tag_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.tagbuf, + tag_len); + + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_CCM_ENCRYPT + | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, 0); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &add_in); + + SE_addDataOutput(se_cmd, &tag_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(ccm_ctx->mode_specific_buffer.tagbuf, 0, sizeof(ccm_ctx->mode_specific_buffer.tagbuf)); + } + return status; + } + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + SE_DataTransfer_t message_length_in = SE_DATATRANSFER_DEFAULT(&total_message_length, sizeof(uint32_t)); + + sli_se_command_init(cmd_ctx, + ((ccm_ctx->mode == SL_SE_DECRYPT) + ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_START); + + sli_add_key_parameters(cmd_ctx, key, status); + + SE_addParameter(se_cmd, ((iv_len & 0xFFFF) << 16) | (tag_len & 0xFFFF)); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, 0); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &message_length_in); + + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &add_in); + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); + return status; + } + + return status; +} +#endif + +/***************************************************************************//** + * This function feeds an input buffer into an ongoing CCM computation. + * It is called between sl_se_ccm_multipart_starts() and sl_se_ccm_multipart_finish(). + * Can be called repeatedly. + ******************************************************************************/ +#if defined(SLI_SE_MAJOR_VERSION_TWO) +sl_status_t sl_se_ccm_multipart_update(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + + // Check input parameters. + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length == 0) { + return SL_STATUS_OK; + } + + if (ccm_ctx->processed_message_length + length > ccm_ctx->total_message_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check variable overflow + if (ccm_ctx->processed_message_length > 0xFFFFFFFF - length) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (length > 0 && (input == NULL || output == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + +#if !defined(SLI_SE_MANAGER_HOST_SYSTEM) + if ((uint32_t)output + length > RAM_MEM_END) { + return SL_STATUS_INVALID_PARAMETER; + } +#endif // SLI_SE_MANAGER_HOST_SYSTEM + + SE_Command_t *se_cmd = &cmd_ctx->command; + *output_length = 0; + + // Approach: + // Encrypt or decrypt regularly with context store. The crypto DMA must have input data in the 'END' operation, thus, + // some data must be saved in the context. + + if ((ccm_ctx->final_data_length + length) < 16 && length < 16) { + if (ccm_ctx->final_data_length > 16) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + + memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, length); + ccm_ctx->final_data_length += length; + return SL_STATUS_OK; + } + + // If there is data in final_data, this must be processed first + if (ccm_ctx->final_data_length) { + if (ccm_ctx->final_data_length > 16) { + // Context is not valid. + return SL_STATUS_INVALID_PARAMETER; + } + + // Fill up the remainder of the buffer. + memcpy(ccm_ctx->mode_specific_buffer.final_data + ccm_ctx->final_data_length, input, 16 - ccm_ctx->final_data_length); + + if (ccm_ctx->processed_message_length + 16 == ccm_ctx->total_message_length ) { + // The finish operation must have some data or the SE fails. + ccm_ctx->final_data_length = 16; + return SL_STATUS_OK; + } + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.final_data, 16); + SE_DataTransfer_t data_out = + SE_DATATRANSFER_DEFAULT(output, 16); + + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + ((ccm_ctx->mode == SL_SE_DECRYPT) + ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + sli_add_key_parameters(cmd_ctx, key, status); + + SE_addParameter(se_cmd, 16); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(output, 0, length); + memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); + *output_length = 0; + return status; + } + ccm_ctx->processed_message_length += 16; + output += 16; + length -= (16 - ccm_ctx->final_data_length); + input += (16 - ccm_ctx->final_data_length); + ccm_ctx->final_data_length = 0; + *output_length += 16; + } + + if (length < 16) { + memcpy(ccm_ctx->mode_specific_buffer.final_data, input, length); + ccm_ctx->final_data_length += length; + return SL_STATUS_OK; + } + + // Run only multiples of 16 and store residue data in context + if (length % 16 != 0) { + uint8_t residue_data_length = length % 16; + memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - residue_data_length), residue_data_length); + length -= residue_data_length; + ccm_ctx->final_data_length = residue_data_length; + } + + if ((ccm_ctx->total_message_length == ccm_ctx->processed_message_length + length) && !ccm_ctx->final_data_length) { + // The finish operation must have some data or the SE fails. + memcpy(ccm_ctx->mode_specific_buffer.final_data, input + (length - 16), 16); + ccm_ctx->final_data_length = 16; + length -= 16; + if (!length) { + return SL_STATUS_OK; + } + } + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(input, length); + SE_DataTransfer_t data_out = + SE_DATATRANSFER_DEFAULT(output, length); + + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + ((ccm_ctx->mode == SL_SE_DECRYPT) + ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + sli_add_key_parameters(cmd_ctx, key, status); + + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(output, 0, length); + memset(ccm_ctx->se_ctx, 0, sizeof(ccm_ctx->se_ctx)); + return status; + } + + *output_length += length; + ccm_ctx->processed_message_length += length; + + return status; +} +#endif + +/***************************************************************************//** + * Finish a CCM streaming operation and return the resulting CCM tag. + * It is called after sl_se_ccm_multipart_update(). + ******************************************************************************/ +#if defined(SLI_SE_MAJOR_VERSION_TWO) +sl_status_t sl_se_ccm_multipart_finish(sl_se_ccm_multipart_context_t *ccm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_size, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length) +{ + //Check input parameters + if (ccm_ctx == NULL || cmd_ctx == NULL || key == NULL || tag == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (tag_size < ccm_ctx->tag_len || output_size < ccm_ctx->final_data_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_status_t status = SL_STATUS_OK; + + if (ccm_ctx->total_message_length == 0) { + if (ccm_ctx->mode == SL_SE_DECRYPT) { + if (memcmp_time_cst(tag, ccm_ctx->mode_specific_buffer.tagbuf, ccm_ctx->tag_len) != 0) { + memset(tag, 0, ccm_ctx->tag_len); + return SL_STATUS_INVALID_SIGNATURE; + } + } else { + memcpy(tag, ccm_ctx->mode_specific_buffer.tagbuf, ccm_ctx->tag_len); + } + return SL_STATUS_OK; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(ccm_ctx->se_ctx, sizeof(ccm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(ccm_ctx->mode_specific_buffer.final_data, ccm_ctx->final_data_length); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, ccm_ctx->final_data_length); + SE_DataTransfer_t tag_buf = SE_DATATRANSFER_DEFAULT(tag, + ccm_ctx->tag_len); + + sli_se_command_init(cmd_ctx, + ((ccm_ctx->mode == SL_SE_DECRYPT) + ? SLI_SE_COMMAND_AES_CCM_DECRYPT : SLI_SE_COMMAND_AES_CCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_END); + + sli_add_key_parameters(cmd_ctx, key, status); + + SE_addParameter(se_cmd, (ccm_ctx->tag_len & 0xFFFF)); + + SE_addParameter(se_cmd, ccm_ctx->final_data_length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + if (ccm_ctx->mode == SL_SE_DECRYPT) { + SE_addDataInput(se_cmd, &tag_buf); + } else { + SE_addDataOutput(se_cmd, &tag_buf); + } + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(tag, 0, ccm_ctx->tag_len); + *output_length = 0; + return status; + } + + *output_length = ccm_ctx->final_data_length; + + return SL_STATUS_OK; +} +#endif + +/***************************************************************************//** + * This function calculates the full generic CMAC on the input buffer with + * the provided key. + ******************************************************************************/ +sl_status_t sl_se_cmac(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + const unsigned char *input, + size_t input_len, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL || input == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status = SL_STATUS_OK; + + switch (key->type) { + case SL_SE_KEY_TYPE_AES_128: + case SL_SE_KEY_TYPE_AES_192: + case SL_SE_KEY_TYPE_AES_256: + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CMAC); + + // Add key parameter to command. + sli_add_key_parameters(cmd_ctx, key, status); + + // Message size parameter. + SE_addParameter(se_cmd, input_len); + + // Key metadata. + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + // Data input. + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(input, input_len); + SE_addDataInput(se_cmd, &in_data); + + // Data output. + SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(output, 16); + SE_addDataOutput(se_cmd, &out_tag); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Finish a CMAC streaming operation and return the resulting CMAC tag. + * It is called after sl_se_cmac_update(). + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_finish(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *output) +{ + sl_status_t status = SL_STATUS_OK; + + if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (cmac_ctx->length >= 16U) { + // Compute previous input block by decryption of current data. + status = sl_se_aes_crypt_ecb(cmd_ctx, + key, + SL_SE_DECRYPT, + 16U, + cmac_ctx->data_out, + cmac_ctx->state); // Keep decrypted data in 'state' + } + + if (status == SL_STATUS_OK) { + // Feed previous block and unprocessed data (if any) to CMAC, + // or on data < 16 just use accumulated data in context. + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_CMAC); + + // Add key parameter to command. + sli_add_key_parameters(cmd_ctx, key, status); + + // Message size parameter. + if (cmac_ctx->length >= 16U) { + SE_addParameter(se_cmd, 16U + (cmac_ctx->length & 0xFU)); + } else { + SE_addParameter(se_cmd, cmac_ctx->length); + } + + // Key metadata. + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t in_data1 = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); + SE_DataTransfer_t in_data2 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, + cmac_ctx->length & 0xFU); + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, + cmac_ctx->length); + // Data input. + if (cmac_ctx->length >= 16U) { + // Collect data from two sources. + in_data1.length &= ~SE_DATATRANSFER_REALIGN; + SE_addDataInput(se_cmd, &in_data1); + SE_addDataInput(se_cmd, &in_data2); + } else { + SE_addDataInput(se_cmd, &in_data); + } + + // Data output. + SE_DataTransfer_t out_tag = SE_DATATRANSFER_DEFAULT(output, 16U); + SE_addDataOutput(se_cmd, &out_tag); + + status = sli_se_execute_and_wait(cmd_ctx); + } + return status; +} + +/***************************************************************************//** + * Prepare a CMAC streaming command context object to be used in subsequent + * CMAC streaming function calls. + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_starts(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key) +{ + if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (key->type) { + case SL_SE_KEY_TYPE_AES_128: + case SL_SE_KEY_TYPE_AES_192: + case SL_SE_KEY_TYPE_AES_256: + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + memset(cmac_ctx, 0, sizeof(sl_se_cmac_multipart_context_t)); + return SL_STATUS_OK; +} + +/***************************************************************************//** + * This function feeds an input buffer into an ongoing CMAC computation. + * It is called between sl_se_cmac_starts() and sl_se_cmac_finish(). + * Can be called repeatedly. + ******************************************************************************/ +sl_status_t sl_se_cmac_multipart_update(sl_se_cmac_multipart_context_t *cmac_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + const uint8_t *input, + size_t input_len) +{ + sl_status_t status = SL_STATUS_OK; + + if (cmac_ctx == NULL || cmd_ctx == NULL || key == NULL || input == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + size_t pending = cmac_ctx->length & 0xFU; + + if ((cmac_ctx->length / 16U) != ((cmac_ctx->length + input_len) / 16U)) { + // Process one or more 16 byte blocks. + size_t bytes_to_process = (pending + input_len) & 0xFFFFFFF0U; + + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_ENCRYPT + | SLI_SE_COMMAND_OPTION_MODE_CBC + | SLI_SE_COMMAND_OPTION_CONTEXT_ADD); + + // Add key parameters to command. + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, bytes_to_process); + + // Add key metadata block to command. + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command. + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); + SE_addDataInput(se_cmd, &iv_in); + + // Data input, collect data from two sources. + SE_DataTransfer_t in1 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_in, pending); + SE_DataTransfer_t in2 = SE_DATATRANSFER_DEFAULT(input, bytes_to_process - pending); + in1.length &= ~SE_DATATRANSFER_REALIGN; + SE_addDataInput(se_cmd, &in1); + SE_addDataInput(se_cmd, &in2); + + // Data output, discard everything except the last 16 bytes. + SE_DataTransfer_t out1 = SE_DATATRANSFER_DEFAULT(NULL, bytes_to_process - 16U); + SE_DataTransfer_t out2 = SE_DATATRANSFER_DEFAULT(cmac_ctx->data_out, 16U); + out1.length |= SE_DATATRANSFER_DISCARD; + out1.length &= ~SE_DATATRANSFER_REALIGN; + SE_addDataOutput(se_cmd, &out1); + SE_addDataOutput(se_cmd, &out2); + + SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(cmac_ctx->state, 16U); + SE_addDataOutput(se_cmd, &iv_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + // Store leftover data. + size_t leftover = pending + input_len - bytes_to_process; + memcpy(cmac_ctx->data_in, input + input_len - leftover, leftover); + } else { + // Not a complete 16 byte block yet, save input data for later. + memcpy(cmac_ctx->data_in + pending, input, input_len); + } + cmac_ctx->length += input_len; + return status; +} + +/***************************************************************************//** + * Compute a HMAC on a full message. + ******************************************************************************/ +sl_status_t sl_se_hmac(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_type, + const uint8_t *message, + size_t message_len, + uint8_t *output, + size_t output_len) +{ + if (cmd_ctx == NULL || key == NULL || message == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status = SL_STATUS_OK; + uint32_t command_word; + size_t hmac_len; + + switch (hash_type) { + case SL_SE_HASH_SHA1: + command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA1; + // SHA1 digest size is 20 bytes + hmac_len = 20; + break; + + case SL_SE_HASH_SHA224: + command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA224; + // SHA224 digest size is 28 bytes + hmac_len = 28; + break; + + case SL_SE_HASH_SHA256: + command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA256; + // SHA256 digest size is 32 bytes + hmac_len = 32; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA384; + // SHA384 digest size is 48 bytes + hmac_len = 48; + break; + + case SL_SE_HASH_SHA512: + command_word = SLI_SE_COMMAND_HMAC | SLI_SE_COMMAND_OPTION_HASH_SHA512; + // SHA512 digest size is 64 bytes + hmac_len = 64; + break; + +#endif + default: + return SL_STATUS_INVALID_PARAMETER; + } + + if (output_len < hmac_len) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + // Add key parameter to command. + sli_add_key_parameters(cmd_ctx, key, status); + + // Message size parameter. + SE_addParameter(se_cmd, message_len); + + // Key metadata. + sli_add_key_metadata(cmd_ctx, key, status); + + sli_add_key_input(cmd_ctx, key, status); + + // Data input. + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(message, message_len); + SE_addDataInput(se_cmd, &in_data); + + // Data output. + SE_DataTransfer_t out_hmac = SE_DATATRANSFER_DEFAULT(output, hmac_len); + SE_addDataOutput(se_cmd, &out_hmac); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * GCM buffer encryption or decryption. + ******************************************************************************/ +sl_status_t sl_se_gcm_crypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag) +{ + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || iv == NULL || tag == NULL + || ((add_len > 0) && (add == NULL)) + || ((length > 0) && (input == NULL || output == NULL)) + || ((tag_len < 4) || (tag_len > 16))) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint8_t tagbuf[16]; + sl_status_t status = SL_STATUS_OK; + + if (// IV length is required to be 96 bits for SE. + (iv_len != 96 / 8) + // AD is limited to 2^64 bits, so 2^61 bytes. + // However, on 32 bit platforms, that amount of continous data cannot be + // available. + // || (((uint64_t)add_len) >> 61 != 0) + ) { + return SL_STATUS_INVALID_PARAMETER; + } + switch (key->type) { + case SL_SE_KEY_TYPE_AES_128: + case SL_SE_KEY_TYPE_AES_192: + case SL_SE_KEY_TYPE_AES_256: + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + if (mode == SL_SE_DECRYPT) { + // Extract plaintext first. + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_addDataInput(se_cmd, &iv_in); + + SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_addDataInput(se_cmd, &aad_in); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &data_in); + + SE_DataTransfer_t tag_in = SE_DATATRANSFER_DEFAULT(tag, tag_len); + SE_addDataInput(se_cmd, &tag_in); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &data_out); + + // Execute GCM operation. + status = sli_se_execute_and_wait(cmd_ctx); + if ((status != SL_STATUS_OK) && (status != SL_STATUS_INVALID_SIGNATURE)) { + memset(output, 0, length); + return status; + } + + // Re-encrypt the extracted plaintext to generate the tag to match. + input = output; + output = NULL; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_AES_GCM_ENCRYPT); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_addDataInput(se_cmd, &iv_in); + + SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_addDataInput(se_cmd, &aad_in); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &data_in); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &data_out); + + SE_DataTransfer_t mac_out = SE_DATATRANSFER_DEFAULT(tagbuf, sizeof(tagbuf)); + SE_addDataOutput(se_cmd, &mac_out); + + // Execute GCM operation. + status = sli_se_execute_and_wait(cmd_ctx); + if (status == SL_STATUS_OK) { + // For encryption, copy requested tag size to output tag buffer. + memcpy(tag, tagbuf, tag_len); + } else { + memset(output, 0, length); + } + + return status; +} + +/***************************************************************************//** + * GCM buffer decryption and authentication. + ******************************************************************************/ +sl_status_t sl_se_gcm_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + const unsigned char *tag) +{ + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || iv == NULL || tag == NULL + || ((add_len > 0) && (add == NULL)) + || ((length > 0) && (input == NULL || output == NULL)) + || ((tag_len < 4) || (tag_len > 16))) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status = SL_STATUS_OK; + + if (// IV length is required to be 96 bits for SE. + (iv_len != 96 / 8) + // AD is limited to 2^64 bits, so 2^61 bytes. + // However, on 32 bit platforms, that amount of continous data cannot be + // available. + // || (((uint64_t)add_len) >> 61 != 0) + ) { + return SL_STATUS_INVALID_PARAMETER; + } + switch (key->type) { + case SL_SE_KEY_TYPE_AES_128: // Fallthrough + case SL_SE_KEY_TYPE_AES_192: // Fallthrough + case SL_SE_KEY_TYPE_AES_256: + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_GCM_DECRYPT | ((tag_len & 0xFF) << 8)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_addDataInput(se_cmd, &iv_in); + + SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_addDataInput(se_cmd, &aad_in); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &data_in); + + SE_DataTransfer_t tag_in = SE_DATATRANSFER_DEFAULT(tag, tag_len); + SE_addDataInput(se_cmd, &tag_in); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &data_out); + + // Execute GCM operation. + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(output, 0, length); + } + + return status; +} + +#if defined(SLI_SE_MAJOR_VERSION_TWO) +/***************************************************************************//** + * GCM multipart encryption/decryption, initial stage. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + const uint8_t *iv, + size_t iv_len, + const uint8_t *add, + size_t add_len) +{ + sl_status_t status = SL_STATUS_OK; + + // Check input parameters. + if (gcm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL + || (add_len > 0 && add == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((iv_len != 12) + // AD are limited to 2^64 bits, so 2^61 bytes. + // However, on 32 bit platforms, that amount of continous data cannot be + // available. + // || (((uint64_t)add_len) >> 61 != 0) + ) { + return SL_STATUS_INVALID_PARAMETER; + } + + memset(gcm_ctx, 0, sizeof(sl_se_gcm_multipart_context_t)); + + gcm_ctx->mode = mode; + gcm_ctx->len = 0; + gcm_ctx->add_len = add_len; + + SE_Command_t *se_cmd = &cmd_ctx->command; + + // The start context requires some data, either additional data or input data. + // Case add_len > 0: Run start command with additonal data to create ctx_out. + // Case add_len = 0: Store iv in gcm_ctx and run start function with input data + // in sl_se_gcm_multipart_update. In the case of zero input data or + // input data < 16 run sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in + // sl_se_gcm_multipart_finish. + if ( add_len > 0 ) { + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t ctx_out = + SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_START); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, 0); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &add_in); + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + gcm_ctx->first_operation = false; + } else { + memcpy(gcm_ctx->se_ctx, iv, iv_len); + gcm_ctx->first_operation = true; + } + return SL_STATUS_OK; +} + +#else +/***************************************************************************//** + * GCM multipart encryption/decryption, initial stage. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_starts(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_cipher_operation_t mode, + const uint8_t *iv, + size_t iv_len, + const uint8_t *add, + size_t add_len) +{ + sl_status_t status = SL_STATUS_OK; + + // Check input parameters. + if (gcm_ctx == NULL || cmd_ctx == NULL || key == NULL || iv == NULL + || (add_len > 0 && add == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((iv_len != 12) + // AD are limited to 2^64 bits, so 2^61 bytes. + // However, on 32 bit platforms, that amount of continous data cannot be + // available. + // || (((uint64_t)add_len) >> 61 != 0) + ) { + return SL_STATUS_INVALID_PARAMETER; + } + + memset(gcm_ctx, 0, sizeof(sl_se_gcm_multipart_context_t)); + + gcm_ctx->mode = mode; + gcm_ctx->len = 0; + gcm_ctx->add_len = add_len; + + // The start context requires some data, either additional data or input data. + // Case add_len > 0: Run start command with additonal data to create ctx_out. + // Case add_len = 0: Store iv in gcm_ctx and run start function with input data + // in sl_se_gcm_multipart_update. In the case of zero input data or + // input data < 16 run sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in + // sl_se_gcm_multipart_finish. + if ( add_len > 0 ) { + // Encrypt: Compute tag and store it in context and output tag in finish. + // Decrypt: Compute tag and store it in context and compare it to the + // input tag in finish to verify it. + + // Explanation:The end-context in finish is currently not supporting 0 input data + // for this config. For add_len = 0 and input_length = 0 we can run + // sl_se_gcm_auth_decrypt()/sl_se_gcm_crypt_and_tag() in finish, so this is only + // an issue for 0 input data and add_len != 0. + SE_Command_t *se_cmd = &cmd_ctx->command; + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(iv, iv_len); + SE_DataTransfer_t add_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_DataTransfer_t tag_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->tagbuf, + sizeof(gcm_ctx->tagbuf)); + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_AES_GCM_ENCRYPT + | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, 0); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &add_in); + SE_addDataOutput(se_cmd, &tag_out); + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(gcm_ctx->tagbuf, 0, sizeof(gcm_ctx->tagbuf)); + return status; + } + + SE_DataTransfer_t ctx_out = + SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + + // Reuse the values of the command context object from the previous + // operation, and only update the command word and the output data pointer. + cmd_ctx->command.command = + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_START; + + cmd_ctx->command.data_out = &ctx_out; + + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + gcm_ctx->first_operation = false; + } else { + memcpy(gcm_ctx->se_ctx, iv, iv_len); + gcm_ctx->first_operation = true; + } + return SL_STATUS_OK; +} +#endif + +#if defined(SLI_SE_MAJOR_VERSION_TWO) +/***************************************************************************//** + * GCM multipart encryption/decryption, update stage. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + uint8_t stored_res_length = 0; + + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (length == 0) { + return SL_STATUS_OK; + } + if (length > 0 && (input == NULL || output == NULL || output_length == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + *output_length = 0; + + // Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes. + // Also check for possible overflow. + if (gcm_ctx->len + length < gcm_ctx->len + || (uint64_t)gcm_ctx->len + length > 0xFFFFFFFE0ULL) { + return SL_STATUS_INVALID_PARAMETER; + } + SE_Command_t *se_cmd = &cmd_ctx->command; + + // The update context only support an input length as a multiple of 16. Hence, there + // there is a few cases that can happen. + + // Always: + // Case length = 0: Return SL_STATUS_OK + + // If there is no data in gcm_ctx->final_data: + // Case length < 16: Store data in gcm_ctx->final_data and return SL_STATUS_OK + // Case length == 16: Run update as normal + // Case length > 16 and length is a multiple of 16: Run update as normal + // Case length > 16 and length is not a multiple of 16: Run update as normal on the largest multiple + // and save the residue bytes in gcm_ctx->final_data. + + // If there is data in gcm_ctx->final_data: + // Case final_data_length + length < 16: Store input data in gcm_ctx and return SL_STATUS_OKAY + // Case final_data_length + length > 16: Add data to fill up the gcm_ctx->final_data-buffer, run update + // on the gcm_ctx->final_data-buffer and finally run update as explained above on the rest of the data. + + if (gcm_ctx->final_data_length) { + if ((gcm_ctx->final_data_length + length) < 16) { + memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, length); + gcm_ctx->final_data_length += length; + *output_length = 0; + return SL_STATUS_OK; + } + stored_res_length = 16 - gcm_ctx->final_data_length; + memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, stored_res_length); + + //The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, 16); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, 16); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, 16); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + gcm_ctx->first_operation = false; + gcm_ctx->len += 16; + output += 16; + + if ((length - stored_res_length) < 16) { + memcpy(gcm_ctx->final_data, input + stored_res_length, length - stored_res_length); + gcm_ctx->final_data_length = length - stored_res_length; + *output_length = 16; + return SL_STATUS_OK; + } + + length -= stored_res_length; + gcm_ctx->final_data_length = 0; + *output_length += 16; + } + if (length % 16 != 0) { + if (length > 16) { + // Input length is larger than, and a non multiple of, 16 + memcpy(gcm_ctx->final_data, input + stored_res_length + (length - (length % 16)), length % 16); + gcm_ctx->final_data_length = length % 16; + length -= length % 16; + } else { + // Input length is not a multiple of 16 + memcpy(gcm_ctx->final_data, input + stored_res_length, length); + gcm_ctx->final_data_length = length; + *output_length = 0; + return SL_STATUS_OK; + } + } + gcm_ctx->len += length; + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(input + stored_res_length, length); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + *output_length += length; + gcm_ctx->first_operation = false; + return SL_STATUS_OK; +} + +#else // SLI_SE_MAJOR_VERSION_ONE +/***************************************************************************//** + * GCM multipart encryption/decryption, update stage. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_update(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const uint8_t *input, + uint8_t *output, + size_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + uint8_t stored_res_length = 0; + + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (length == 0) { + return SL_STATUS_OK; + } + if (length > 0 && (input == NULL || output == NULL || output_length == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + *output_length = 0; + + // Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes. + // Also check for possible overflow. + if (gcm_ctx->len + length < gcm_ctx->len + || (uint64_t)gcm_ctx->len + length > 0xFFFFFFFE0ULL) { + return SL_STATUS_INVALID_PARAMETER; + } + SE_Command_t *se_cmd = &cmd_ctx->command; + + // The finish command will return the wrong tag or INVALID SIGNATURE if there is no + // input data. There is no way to know when sl_se_gcm_multipart_update is called for the last time, so there must + // always be data stored. + // The update context only support an input length as a multiple of 16. Hence, there + // there is a few cases that can happen. + + // Always: + // Case length = 0: Return SL_STATUS_OK + + // If there is no data in gcm_ctx->final_data + // Case length < 16: Store data in gcm_ctx->final_data and return SL_STATUS_OK + // Case length > 16 and length is not a multiple of 16: Run update as normal on the largest multiple + // and save the residue bytes in gcm_ctx->final_data. + // Case length == 16: store the current se_ctx in gcm_ctx->previous_se_ctx and store input data in final_data, + // then run update as normal on the input data. + // Case length > 16 and length is a multible of 16: run update twice, one with all input data and one with + // all input data except the last 16 bytes. The out_ctx from each run are stored in gcm_ctx->se_ctx and + // gcm_ctx->previous_se_ctx respectively. The last 16 bytes are then stored in final_data. + // NOTE:output_length will include all encrypted/decrypted data. + + // If there is data in gcm_ctx->final_data + // Case final_data_length + length < 16: Store input data in gcm_ctx and return SL_STATUS_OKAY + // Case final_data_length + length > 16: Add data to fill up the gcm_ctx->final_data-buffer, run update + // on the gcm_ctx->final_data-buffer and finally run update as explained above on the rest of the data. + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + length))) { + memmove(output, input, length); + input = output; + } + + // Check for data in final_data_length. + if (gcm_ctx->final_data_length && gcm_ctx->final_data_length != 16) { + if ((gcm_ctx->final_data_length + length) < 16) { + memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, length); + gcm_ctx->final_data_length += length; + *output_length = 0; + return SL_STATUS_OK; + } + + if ((gcm_ctx->final_data_length + length) == 16) { + memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + } + stored_res_length = 16 - gcm_ctx->final_data_length; + memcpy(gcm_ctx->final_data + gcm_ctx->final_data_length, input, stored_res_length); + + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, 16); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, 16); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, 16); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + gcm_ctx->first_operation = false; + gcm_ctx->len += 16; + output += 16; + + if ((gcm_ctx->final_data_length + length) == 16) { + gcm_ctx->final_data_length = 16; + *output_length = 16; + return SL_STATUS_OK; + } + + if ((length - stored_res_length) < 16) { + memcpy(gcm_ctx->final_data, input + stored_res_length, length - stored_res_length); + gcm_ctx->final_data_length = length - stored_res_length; + *output_length = 16; + return SL_STATUS_OK; + } + + length -= stored_res_length; + gcm_ctx->final_data_length = 0; + *output_length += 16; + } + if (length % 16 != 0) { + if (length > 16) { + //Input length is larger than, and a non multiple of, 16 + memcpy(gcm_ctx->final_data, input + stored_res_length + (length - (length % 16)), length % 16); + gcm_ctx->final_data_length = length % 16; + length -= length % 16; + } else { + //Input length is not a multiple of 16 + memcpy(gcm_ctx->final_data, input + stored_res_length, length); + gcm_ctx->final_data_length = length; + *output_length = 0; + return SL_STATUS_OK; + } + } else { + if (length > 16) { + //If length is larger than, and a multiple of, 16, we must compute a context without the last 16 bytes + //and store it as the previous context in case there is no more data. + memcpy(gcm_ctx->final_data, input + stored_res_length + (length - 16), 16); + gcm_ctx->final_data_length = 16; + + //The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(input + stored_res_length, length - 16); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length - 16); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, length - 16); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + + // Only process the last 16 bytes in the last operation. + output += (length - 16); + input += (length - 16); + gcm_ctx->first_operation = false; + gcm_ctx->len += (length - 16); + *output_length += (length - 16); + + length = 16; + + memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + } else { + memcpy(gcm_ctx->previous_se_ctx, gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + memcpy(gcm_ctx->final_data, input + stored_res_length, length); + gcm_ctx->final_data_length = length; + } + } + gcm_ctx->len += length; + + // The gcm_ctx->se_ctx buffer contain iv data with length 12 if gcm_ctx->first_operation = true + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + gcm_ctx->first_operation ? 12 : sizeof(gcm_ctx->se_ctx)); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(input + stored_res_length, length); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + SE_DataTransfer_t ctx_out = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, + sizeof(gcm_ctx->se_ctx)); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | (gcm_ctx->first_operation ? SLI_SE_COMMAND_OPTION_CONTEXT_START : SLI_SE_COMMAND_OPTION_CONTEXT_ADD)); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + + SE_addDataOutput(se_cmd, &data_out); + + SE_addDataOutput(se_cmd, &ctx_out); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + memset(gcm_ctx->se_ctx, 0, sizeof(gcm_ctx->se_ctx)); + return status; + } + *output_length += length; + gcm_ctx->first_operation = false; + return SL_STATUS_OK; +} +#endif + +/***************************************************************************//** + * GCM multipart encryption/decryption, finish stage. + ******************************************************************************/ +sl_status_t sl_se_gcm_multipart_finish(sl_se_gcm_multipart_context_t *gcm_ctx, + sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + uint8_t *tag, + uint8_t tag_length, + uint8_t *output, + uint8_t output_size, + uint8_t *output_length) +{ + sl_status_t status = SL_STATUS_OK; + uint32_t tmpbuf[4]; + uint8_t length; + if (cmd_ctx == NULL || key == NULL || gcm_ctx == NULL || tag == NULL || tag_length < 4 || tag_length > 16) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((gcm_ctx->final_data_length != 16) + && (output_size < gcm_ctx->final_data_length)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + length = gcm_ctx->final_data_length; + gcm_ctx->len += ((length % 16 != 0) ? length : 0); + + #if defined(SLI_SE_MAJOR_VERSION_ONE) + if ((gcm_ctx->add_len > 0) && (gcm_ctx->len == 0)) { + if (gcm_ctx->mode == SL_SE_DECRYPT) { + if (memcmp_time_cst(tag, gcm_ctx->tagbuf, tag_length)) { + memset(tag, 0, tag_length); + return SL_STATUS_INVALID_SIGNATURE; + } + } else { + memcpy(tag, gcm_ctx->tagbuf, tag_length); + } + return SL_STATUS_OK; + } + #endif + +#if defined(SLI_SE_MAJOR_VERSION_ONE) + // For xG21 devices, since the multipart finish command cannot handle cases without + // more data being passed as part of the finish call, there are two cases for which + // a finish call can condense into a one-shot operation: + // 1. The 'first operation' flag is set, meaning no multipart context has been started + // 2. There was no AAD input and the total input length equals 16 bytes. In such a case, + // all information needed for a one-shot operation is still present in the context, + // being the 16 bytes of input in the lookback buffer. In such a case, be careful to + // not return ciphertext/plaintext to the user a second time, since it has already + // been returned as part of the initial call to `_update`. + if (gcm_ctx->first_operation || (gcm_ctx->add_len == 0 && gcm_ctx->len == 16)) { +#else + // Devices xG23 or newer support a finish call without data, so the only case for + // condensing a multipart finish operation into a one-shot operation is when the + // 'first operation' flag is set, meaning no multipart context has been started + if (gcm_ctx->first_operation) { +#endif + if (gcm_ctx->mode == SL_SE_ENCRYPT) { + status = sl_se_gcm_crypt_and_tag(cmd_ctx, + key, + gcm_ctx->mode, + length, + gcm_ctx->se_ctx, //iv + 12, //iv_len + NULL, + 0, + gcm_ctx->final_data, + (length < 16 ? output : (unsigned char*)tmpbuf), + tag_length, + tag); + } else { + status = sl_se_gcm_auth_decrypt(cmd_ctx, + key, + length, + gcm_ctx->se_ctx, //iv + 12, //iv_len + NULL, + 0, + gcm_ctx->final_data, + (length < 16 ? output : (unsigned char*)tmpbuf), + tag_length, + tag); + } + if (status != SL_STATUS_OK) { + *output_length = 0; + memset(tag, 0, tag_length); + return status; + } + if (length < 16) { + *output_length = length; + } else { + *output_length = 0; + } + return SL_STATUS_OK; + } + + // Construct GCM LenA || LenC block into temporary buffer + tmpbuf[0] = __REV(gcm_ctx->add_len >> 29); + tmpbuf[1] = __REV((gcm_ctx->add_len << 3) & 0xFFFFFFFFUL); + tmpbuf[2] = __REV(gcm_ctx->len >> 29); + tmpbuf[3] = __REV((gcm_ctx->len << 3) & 0xFFFFFFFFUL); + + SE_DataTransfer_t data_in = + SE_DATATRANSFER_DEFAULT(gcm_ctx->final_data, length); + + #if defined(SLI_SE_MAJOR_VERSION_ONE) + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT((length % 16 != 0 || length == 0) ? gcm_ctx->se_ctx : gcm_ctx->previous_se_ctx, sizeof(gcm_ctx->previous_se_ctx)); + #else + SE_DataTransfer_t iv_ctx_in = SE_DATATRANSFER_DEFAULT(gcm_ctx->se_ctx, sizeof(gcm_ctx->se_ctx)); + #endif + + SE_DataTransfer_t lenalenc_in = SE_DATATRANSFER_DEFAULT(&tmpbuf[0], + sizeof(tmpbuf)); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (length == 16) { + data_out.data = NULL; + data_out.length |= SE_DATATRANSFER_DISCARD; + } + + SE_DataTransfer_t gcm_tag = SE_DATATRANSFER_DEFAULT(tag, tag_length); + + sli_se_command_init(cmd_ctx, + (gcm_ctx->mode == SL_SE_DECRYPT ? SLI_SE_COMMAND_AES_GCM_DECRYPT + : SLI_SE_COMMAND_AES_GCM_ENCRYPT) + | tag_length << 8 | SLI_SE_COMMAND_OPTION_CONTEXT_END); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, 0); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_addDataInput(se_cmd, &iv_ctx_in); + SE_addDataInput(se_cmd, &data_in); + SE_addDataInput(se_cmd, &lenalenc_in); + + if (gcm_ctx->mode == SL_SE_DECRYPT) { + SE_addDataInput(se_cmd, &gcm_tag); + } + + SE_addDataOutput(se_cmd, &data_out); + + if (gcm_ctx->mode == SL_SE_ENCRYPT) { + SE_addDataOutput(se_cmd, &gcm_tag); + } + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + if (gcm_ctx->mode == SL_SE_ENCRYPT) { + memset(tag, 0, tag_length); + } + *output_length = 0; + return status; + } + + if (length < 16) { + *output_length = length; + } else { + *output_length = 0; + } + + return SL_STATUS_OK; +} + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +/***************************************************************************//** + * ChaCha20 buffer encryption/decryption, as defined by RFC8439 section 2.4. + ******************************************************************************/ +sl_status_t sl_se_chacha20_crypt(sl_se_command_context_t *cmd_ctx, + sl_se_cipher_operation_t mode, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char initial_counter[4], + const unsigned char nonce[12], + const unsigned char *input, + unsigned char *output) +{ + if (cmd_ctx == NULL || key == NULL || initial_counter == NULL || nonce == NULL + || input == NULL || output == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (key->type != SL_SE_KEY_TYPE_CHACHA20) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + sli_se_command_init(cmd_ctx, + (mode == SL_SE_ENCRYPT + ? SLI_SE_COMMAND_CHACHA20_ENCRYPT + : SLI_SE_COMMAND_CHACHA20_DECRYPT) + | SLI_SE_COMMAND_OPTION_CONTEXT_WHOLE); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + // Add initial counter to command + SE_DataTransfer_t counter = SE_DATATRANSFER_DEFAULT(initial_counter, 4); + SE_addDataInput(se_cmd, &counter); + + // Add nonce/IV to command + SE_DataTransfer_t iv = SE_DATATRANSFER_DEFAULT(nonce, 12); + SE_addDataInput(se_cmd, &iv); + + // Add input data to command + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &in); + + // Request output data from command + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(output, length); + SE_addDataOutput(se_cmd, &out); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * ChaCha20-Poly1305 authenticated encryption with additional data, as defined + * by RFC8439 section 2.8. + ******************************************************************************/ +sl_status_t sl_se_chacha20_poly1305_encrypt_and_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + unsigned char *tag) +{ + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || nonce == NULL + || ((add_len > 0) && (add == NULL)) + || ((length > 0) && (input == NULL))) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + if (key->type != SL_SE_KEY_TYPE_CHACHA20) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHACHAPOLY_ENCRYPT); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t nonce_in = SE_DATATRANSFER_DEFAULT(nonce, 12); + SE_addDataInput(se_cmd, &nonce_in); + + SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_addDataInput(se_cmd, &aad_in); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &data_in); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &data_out); + + SE_DataTransfer_t mac_out = SE_DATATRANSFER_DEFAULT(tag, 16); + if (tag == NULL) { + mac_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &mac_out); + + // Execute AEAD operation. + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * ChaCha20-Poly1305 authenticated decryption with additional data, as defined + * by RFC8439 section 2.8. + ******************************************************************************/ +sl_status_t sl_se_chacha20_poly1305_auth_decrypt(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *add, size_t add_len, + const unsigned char *input, + unsigned char *output, + const unsigned char tag[16]) +{ + // Check input parameters. + if (cmd_ctx == NULL || key == NULL || nonce == NULL || tag == NULL + || ((add_len > 0) && (add == NULL)) + || ((length > 0) && (input == NULL))) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + if (key->type != SL_SE_KEY_TYPE_CHACHA20) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHACHAPOLY_DECRYPT); + + sli_add_key_parameters(cmd_ctx, key, status); + SE_addParameter(se_cmd, add_len); + SE_addParameter(se_cmd, length); + + sli_add_key_metadata(cmd_ctx, key, status); + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t nonce_in = SE_DATATRANSFER_DEFAULT(nonce, 12); + SE_addDataInput(se_cmd, &nonce_in); + + SE_DataTransfer_t aad_in = SE_DATATRANSFER_DEFAULT(add, add_len); + SE_addDataInput(se_cmd, &aad_in); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &data_in); + + SE_DataTransfer_t mac_in = SE_DATATRANSFER_DEFAULT(tag, 16); + SE_addDataInput(se_cmd, &mac_in); + + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(output, length); + if (output == NULL) { + data_out.length |= SE_DATATRANSFER_DISCARD; + } + SE_addDataOutput(se_cmd, &data_out); + + // Execute AEAD operation. + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Generate a MAC (message authentication code) for a given message, according + * to RFC8439 section 2.8 but bypassing the encryption step. + ******************************************************************************/ +sl_status_t sl_se_poly1305_genkey_tag(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + size_t length, + const unsigned char nonce[12], + const unsigned char *input, + unsigned char *tag) +{ + if (cmd_ctx == NULL || key == NULL || nonce == NULL || tag == NULL + || ((length > 0) && (input == NULL))) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (key->type != SL_SE_KEY_TYPE_CHACHA20) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_POLY1305_KEY_MAC); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, length); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + // Add nonce/IV to command + SE_DataTransfer_t iv = SE_DATATRANSFER_DEFAULT(nonce, 12); + SE_addDataInput(se_cmd, &iv); + + // Add input data to command + SE_DataTransfer_t in = SE_DATATRANSFER_DEFAULT(input, length); + SE_addDataInput(se_cmd, &in); + + // Request tag from command + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(tag, 16); + SE_addDataOutput(se_cmd, &out); + + return sli_se_execute_and_wait(cmd_ctx); +} +#endif + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c index 2846e57..597e274 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c @@ -1,103 +1,103 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include - -/// @addtogroup sl_se_manager -/// @{ - -// ----------------------------------------------------------------------------- -// Global Functions - -/***************************************************************************//** - * Get random data from hardware TRNG. - ******************************************************************************/ -sl_status_t sl_se_get_random(sl_se_command_context_t *cmd_ctx, - void * data, - uint32_t num_bytes) -{ - SE_Command_t *se_cmd; - sl_status_t ret; - uint32_t surplus_bytes, i; - uint32_t surplus_word = 0; - - if (cmd_ctx == NULL || (num_bytes != 0 && data == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - se_cmd = &cmd_ctx->command; - surplus_bytes = num_bytes & 0x3U; - num_bytes &= ~0x3U; - - if (num_bytes > 0U) { - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRNG_GET_RANDOM); - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(data, num_bytes); - - SE_addDataOutput(se_cmd, &data_out); - SE_addParameter(se_cmd, num_bytes); - - // Execute and wait - if ((ret = sli_se_execute_and_wait(cmd_ctx)) != SL_STATUS_OK) { - memset(data, 0, num_bytes); - return ret; - } - } - - if (surplus_bytes > 0) { - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRNG_GET_RANDOM); - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(&surplus_word, 4); - - SE_addDataOutput(se_cmd, &data_out); - SE_addParameter(se_cmd, 4); - - // Execute and wait - if ((ret = sli_se_execute_and_wait(cmd_ctx)) != SL_STATUS_OK) { - memset(data, 0, num_bytes + surplus_bytes); - return ret; - } - - uint8_t *output = (uint8_t*)data + num_bytes; - for (i = 0; i < surplus_bytes; i++) { - output[i] = (surplus_word >> (i * 8U)) & 0xFFU; - } - } - - return SL_STATUS_OK; -} - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include + +/// @addtogroup sl_se_manager +/// @{ + +// ----------------------------------------------------------------------------- +// Global Functions + +/***************************************************************************//** + * Get random data from hardware TRNG. + ******************************************************************************/ +sl_status_t sl_se_get_random(sl_se_command_context_t *cmd_ctx, + void * data, + uint32_t num_bytes) +{ + SE_Command_t *se_cmd; + sl_status_t ret; + uint32_t surplus_bytes, i; + uint32_t surplus_word = 0; + + if (cmd_ctx == NULL || (num_bytes != 0 && data == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + se_cmd = &cmd_ctx->command; + surplus_bytes = num_bytes & 0x3U; + num_bytes &= ~0x3U; + + if (num_bytes > 0U) { + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRNG_GET_RANDOM); + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(data, num_bytes); + + SE_addDataOutput(se_cmd, &data_out); + SE_addParameter(se_cmd, num_bytes); + + // Execute and wait + if ((ret = sli_se_execute_and_wait(cmd_ctx)) != SL_STATUS_OK) { + memset(data, 0, num_bytes); + return ret; + } + } + + if (surplus_bytes > 0) { + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRNG_GET_RANDOM); + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(&surplus_word, 4); + + SE_addDataOutput(se_cmd, &data_out); + SE_addParameter(se_cmd, 4); + + // Execute and wait + if ((ret = sli_se_execute_and_wait(cmd_ctx)) != SL_STATUS_OK) { + memset(data, 0, num_bytes + surplus_bytes); + return ret; + } + + uint8_t *output = (uint8_t*)data + num_bytes; + for (i = 0; i < surplus_bytes; i++) { + output[i] = (surplus_word >> (i * 8U)) & 0xFFU; + } + } + + return SL_STATUS_OK; +} + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c index 7f1a4fc..3ec541d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c @@ -1,673 +1,673 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include "sl_assert.h" -#include - -/***************************************************************************//** - * \addtogroup sl_se Secure Engine Manager API - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Global functions - -/***************************************************************************//** - * Start a SHA1 stream operation. - ******************************************************************************/ -sl_status_t sl_se_hash_sha1_multipart_starts(sl_se_sha1_multipart_context_t *sha1_ctx, - sl_se_command_context_t *cmd_ctx) -{ - static const uint8_t init_state_sha1[32] = { - 0x67, 0x45, 0x23, 0x01, - 0xEF, 0xCD, 0xAB, 0x89, - 0x98, 0xBA, 0xDC, 0xFE, - 0x10, 0x32, 0x54, 0x76, - 0xC3, 0xD2, 0xE1, 0xF0, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 - }; - - if (cmd_ctx == NULL || sha1_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sha1_ctx->total[0] = 0; - sha1_ctx->total[1] = 0; - memcpy(sha1_ctx->state, init_state_sha1, sizeof(sha1_ctx->state)); - - sha1_ctx->hash_type = SL_SE_HASH_SHA1; - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Start a SHA224 stream operation. - ******************************************************************************/ -sl_status_t -sl_se_hash_sha224_multipart_starts(sl_se_sha224_multipart_context_t *sha224_ctx, - sl_se_command_context_t *cmd_ctx) -{ - static const uint8_t init_state_sha224[32] = { - 0xC1, 0x05, 0x9E, 0xD8, - 0x36, 0x7C, 0xD5, 0x07, - 0x30, 0x70, 0xDD, 0x17, - 0xF7, 0x0E, 0x59, 0x39, - 0xFF, 0xC0, 0x0B, 0x31, - 0x68, 0x58, 0x15, 0x11, - 0x64, 0xF9, 0x8F, 0xA7, - 0xBE, 0xFA, 0x4F, 0xA4 - }; - - if (cmd_ctx == NULL || sha224_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sha224_ctx->total[0] = 0; - sha224_ctx->total[1] = 0; - memcpy(sha224_ctx->state, init_state_sha224, sizeof(sha224_ctx->state)); - - sha224_ctx->hash_type = SL_SE_HASH_SHA224; - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Start a SHA256 stream operation. - ******************************************************************************/ -sl_status_t -sl_se_hash_sha256_multipart_starts(sl_se_sha256_multipart_context_t *sha256_ctx, - sl_se_command_context_t *cmd_ctx) -{ - static const uint8_t init_state_sha256[32] = { - 0x6A, 0x09, 0xE6, 0x67, - 0xBB, 0x67, 0xAE, 0x85, - 0x3C, 0x6E, 0xF3, 0x72, - 0xA5, 0x4F, 0xF5, 0x3A, - 0x51, 0x0E, 0x52, 0x7F, - 0x9B, 0x05, 0x68, 0x8C, - 0x1F, 0x83, 0xD9, 0xAB, - 0x5B, 0xE0, 0xCD, 0x19 - }; - - if (cmd_ctx == NULL || sha256_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sha256_ctx->total[0] = 0; - sha256_ctx->total[1] = 0; - memcpy(sha256_ctx->state, init_state_sha256, sizeof(sha256_ctx->state)); - - sha256_ctx->hash_type = SL_SE_HASH_SHA256; - - return SL_STATUS_OK; -} - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * Start a SHA384 stream operation. - ******************************************************************************/ -sl_status_t -sl_se_hash_sha384_multipart_starts(sl_se_sha384_multipart_context_t *sha384_ctx, - sl_se_command_context_t *cmd_ctx) -{ - static const uint8_t init_state_sha384[64] = { - 0xCB, 0xBB, 0x9D, 0x5D, 0xC1, 0x05, 0x9E, 0xD8, - 0x62, 0x9A, 0x29, 0x2A, 0x36, 0x7C, 0xD5, 0x07, - 0x91, 0x59, 0x01, 0x5A, 0x30, 0x70, 0xDD, 0x17, - 0x15, 0x2F, 0xEC, 0xD8, 0xF7, 0x0E, 0x59, 0x39, - 0x67, 0x33, 0x26, 0x67, 0xFF, 0xC0, 0x0B, 0x31, - 0x8E, 0xB4, 0x4A, 0x87, 0x68, 0x58, 0x15, 0x11, - 0xDB, 0x0C, 0x2E, 0x0D, 0x64, 0xF9, 0x8F, 0xA7, - 0x47, 0xB5, 0x48, 0x1D, 0xBE, 0xFA, 0x4F, 0xA4 - }; - - if (cmd_ctx == NULL || sha384_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sha384_ctx->total[0] = 0; - sha384_ctx->total[1] = 0; - sha384_ctx->total[2] = 0; - sha384_ctx->total[3] = 0; - memcpy(sha384_ctx->state, init_state_sha384, sizeof(sha384_ctx->state)); - - sha384_ctx->hash_type = SL_SE_HASH_SHA384; - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Start a SHA512 stream operation. - ******************************************************************************/ -sl_status_t -sl_se_hash_sha512_multipart_starts(sl_se_sha512_multipart_context_t *sha512_ctx, sl_se_command_context_t *cmd_ctx) -{ - static const uint8_t init_state_sha512[64] = { - 0x6A, 0x09, 0xE6, 0x67, 0xF3, 0xBC, 0xC9, 0x08, - 0xBB, 0x67, 0xAE, 0x85, 0x84, 0xCA, 0xA7, 0x3B, - 0x3C, 0x6E, 0xF3, 0x72, 0xFE, 0x94, 0xF8, 0x2B, - 0xA5, 0x4F, 0xF5, 0x3A, 0x5F, 0x1D, 0x36, 0xF1, - 0x51, 0x0E, 0x52, 0x7F, 0xAD, 0xE6, 0x82, 0xD1, - 0x9B, 0x05, 0x68, 0x8C, 0x2B, 0x3E, 0x6C, 0x1F, - 0x1F, 0x83, 0xD9, 0xAB, 0xFB, 0x41, 0xBD, 0x6B, - 0x5B, 0xE0, 0xCD, 0x19, 0x13, 0x7E, 0x21, 0x79 - }; - - if (cmd_ctx == NULL || sha512_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sha512_ctx->total[0] = 0; - sha512_ctx->total[1] = 0; - sha512_ctx->total[2] = 0; - sha512_ctx->total[3] = 0; - memcpy(sha512_ctx->state, init_state_sha512, sizeof(sha512_ctx->state)); - - sha512_ctx->hash_type = SL_SE_HASH_SHA512; - - return SL_STATUS_OK; -} - -#endif - -/***************************************************************************//** - * Start a hash stream operation. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_starts(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - sl_se_hash_type_t hash_type) -{ - if (cmd_ctx == NULL || hash_type_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (hash_type) { - case SL_SE_HASH_SHA1: - return sl_se_hash_sha1_multipart_starts((sl_se_sha1_multipart_context_t*) - hash_type_ctx, cmd_ctx); - - case SL_SE_HASH_SHA224: - return sl_se_hash_sha224_multipart_starts((sl_se_sha224_multipart_context_t*) - hash_type_ctx, cmd_ctx); - - case SL_SE_HASH_SHA256: - return sl_se_hash_sha256_multipart_starts((sl_se_sha256_multipart_context_t*) - hash_type_ctx, cmd_ctx); - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - return sl_se_hash_sha384_multipart_starts((sl_se_sha384_multipart_context_t*) - hash_type_ctx, - cmd_ctx); - - case SL_SE_HASH_SHA512: - return sl_se_hash_sha512_multipart_starts((sl_se_sha512_multipart_context_t*) - hash_type_ctx, cmd_ctx); -#endif - - default: - return SL_STATUS_INVALID_PARAMETER; - } -} - -/***************************************************************************//** - * Feeds an input block into an ongoing hash computation. - ******************************************************************************/ -static sl_status_t se_cmd_hash_multipart_update(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - const uint8_t *input, - uint32_t num_blocks) -{ - SE_Command_t *se_cmd = &cmd_ctx->command; - uint8_t *state; - uint32_t command_word = SLI_SE_COMMAND_HASHUPDATE; - size_t state_len, blocksize; - - switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { - case SL_SE_HASH_SHA1: - state = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->state; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; - state_len = 20; - blocksize = 64; - break; - case SL_SE_HASH_SHA224: - state = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->state; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; - state_len = 32; - blocksize = 64; - break; - case SL_SE_HASH_SHA256: - state = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->state; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; - state_len = 32; - blocksize = 64; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - state = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->state; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; - state_len = 64; - blocksize = 128; - break; - case SL_SE_HASH_SHA512: - state = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->state; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; - state_len = 64; - blocksize = 128; - break; -#endif - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, command_word); - - size_t ilen = blocksize * num_blocks; - SE_addParameter(se_cmd, ilen); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, ilen); - SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(state, state_len); - SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(state, state_len); - - SE_addDataInput(se_cmd, &iv_in); - SE_addDataInput(se_cmd, &data_in); - SE_addDataOutput(se_cmd, &iv_out); - - // Execute and wait - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Feeds an input buffer into an ongoing hash computation. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_update(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - const uint8_t *input, - size_t input_len) -{ - size_t blocks, fill, left, blocksize, countersize; - sl_status_t status; - uint8_t *buffer; - uint32_t *counter; - - if ( input_len == 0 ) { - return SL_STATUS_OK; - } - - if (hash_type_ctx == NULL || cmd_ctx == NULL || input == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { - case SL_SE_HASH_SHA1: - counter = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->total; - buffer = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->buffer; - blocksize = 64; - break; - case SL_SE_HASH_SHA224: - counter = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->total; - buffer = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->buffer; - blocksize = 64; - break; - case SL_SE_HASH_SHA256: - counter = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->total; - buffer = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->buffer; - blocksize = 64; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - counter = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->total; - buffer = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->buffer; - blocksize = 128; - break; - case SL_SE_HASH_SHA512: - counter = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->total; - buffer = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->buffer; - blocksize = 128; - break; -#endif - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - countersize = blocksize / 32; - left = (counter[0] & (blocksize - 1)); - fill = blocksize - left; - - counter[0] += input_len; - - // ripple counter - if ( counter[0] < input_len ) { - counter[1] += 1; -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - for (size_t i = 1; i < (countersize - 1); i++) { - if ( counter[i] == 0 ) { - counter[i + 1]++; - } - } -#else - (void)countersize; -#endif - } - - // We only support hashing up to 4 GB data - // so if anything but counter[0] is set, return NOT_SUPPORTED -#if defined(SLI_SE_MAJOR_VERSION_TWO) - for (size_t i = 1; i < countersize; i++) { - if (counter[i] != 0) { - return SL_STATUS_NOT_SUPPORTED; - } - } -#endif - - if ( (left > 0) && (input_len >= fill) ) { - memcpy( (void *) (buffer + left), input, fill); - status = se_cmd_hash_multipart_update(hash_type_ctx, cmd_ctx, buffer, 1); - if (status != SL_STATUS_OK) { - return status; - } - input += fill; - input_len -= fill; - left = 0; - } - - if ( input_len >= blocksize ) { - blocks = input_len / blocksize; - status = se_cmd_hash_multipart_update(hash_type_ctx, cmd_ctx, input, blocks); - if (status != SL_STATUS_OK) { - return status; - } - input += blocksize * blocks; - input_len -= blocksize * blocks; - } - - if ( input_len > 0 ) { - memcpy( (void *) (buffer + left), input, input_len); - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Finish an ongoing hash streaming computation. - ******************************************************************************/ -sl_status_t sl_se_hash_multipart_finish(void *hash_type_ctx, - sl_se_command_context_t *cmd_ctx, - uint8_t *digest_out, - size_t digest_len) -{ - sl_status_t status; - size_t countersize, blocksize, outputsize; - uint8_t *state; - uint32_t *counter; -#if defined(SLI_SE_MAJOR_VERSION_TWO) - uint32_t command_word = SLI_SE_COMMAND_HASHFINISH; - uint8_t *buffer; - size_t state_len; -#else - size_t last_data_byte, num_pad_bytes; - uint8_t msglen[16]; - // Define padding as largest padding we might need - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - static const unsigned char sha_padding[128] = { - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - }; - #else - static const unsigned char sha_padding[64] = { - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - }; - #endif -#endif - if (hash_type_ctx == NULL || cmd_ctx == NULL || digest_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { - case SL_SE_HASH_SHA1: - state = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->state; - counter = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->total; - outputsize = 20; - blocksize = 64; - #if defined(SLI_SE_MAJOR_VERSION_TWO) - state_len = 20; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; - buffer = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->buffer; - #endif - break; - case SL_SE_HASH_SHA224: - state = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->state; - counter = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->total; - outputsize = 28; - blocksize = 64; - #if defined(SLI_SE_MAJOR_VERSION_TWO) - state_len = 32; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; - buffer = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->buffer; - #endif - break; - case SL_SE_HASH_SHA256: - state = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->state; - counter = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->total; - outputsize = 32; - blocksize = 64; - #if defined(SLI_SE_MAJOR_VERSION_TWO) - state_len = 32; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; - buffer = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->buffer; - #endif - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - state = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->state; - counter = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->total; - outputsize = 48; - blocksize = 128; - #if defined(SLI_SE_MAJOR_VERSION_TWO) - state_len = 64; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; - buffer = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->buffer; - #endif - break; - case SL_SE_HASH_SHA512: - state = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->state; - counter = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->total; - outputsize = 64; - blocksize = 128; - #if defined(SLI_SE_MAJOR_VERSION_TWO) - state_len = 64; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; - buffer = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->buffer; - #endif - break; -#endif - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - if ( digest_len < outputsize ) { - return SL_STATUS_INVALID_PARAMETER; - } - - countersize = blocksize / 32; -#if defined(SLI_SE_MAJOR_VERSION_TWO) - - // We only support hashing up to 4 GB data - // so if anything but counter[0] is set, return NOT_SUPPORTED - for (size_t i = 1; i < countersize; i++) { - if (counter[i] != 0) { - return SL_STATUS_NOT_SUPPORTED; - } - } - // Remaining bytes in buffer - size_t rem_bytes = (counter[0] & (blocksize - 1)); - - SE_Command_t *se_cmd = &cmd_ctx->command; - - sli_se_command_init(cmd_ctx, command_word); - - SE_addParameter(se_cmd, rem_bytes); - SE_addParameter(se_cmd, counter[0]); - - SE_DataTransfer_t in_0 = SE_DATATRANSFER_DEFAULT(state, state_len); - SE_DataTransfer_t in_1 = SE_DATATRANSFER_DEFAULT(buffer, rem_bytes); - SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(digest_out, outputsize); - - SE_addDataInput(se_cmd, &in_0); - SE_addDataInput(se_cmd, &in_1); - SE_addDataOutput(se_cmd, &out); - - // Execute and wait - status = sli_se_execute_and_wait(cmd_ctx); -#else - - /* Convert counter value to bits, and put in big-endian array */ - uint8_t residual = 0; - for (size_t i = 0; i < countersize; i++) { - size_t msglen_index = ( (countersize - i) * sizeof(uint32_t) ) - 1; - - msglen[msglen_index - 0] = ((counter[i] << 3) + residual) & 0xFF; - msglen[msglen_index - 1] = (counter[i] >> 5) & 0xFF; - msglen[msglen_index - 2] = (counter[i] >> 13) & 0xFF; - msglen[msglen_index - 3] = (counter[i] >> 21) & 0xFF; - - residual = (counter[i] >> 29) & 0xFF; - } - - last_data_byte = (counter[0] & (blocksize - 1) ); - num_pad_bytes = (last_data_byte < (blocksize - (countersize * 4)) ) - ? ( (blocksize - (countersize * 4)) - last_data_byte) - : ( ((2 * blocksize) - (countersize * 4)) - last_data_byte); - - status = sl_se_hash_multipart_update(hash_type_ctx, cmd_ctx, sha_padding, num_pad_bytes); - - if (status == SL_STATUS_OK) { - status = sl_se_hash_multipart_update(hash_type_ctx, cmd_ctx, msglen, countersize * 4); - } - - if (status == SL_STATUS_OK) { - memcpy(digest_out, state, outputsize); - } -#endif // SLI_SE_MAJOR_VERSION_TWO - return status; -} - -/***************************************************************************//** - * Produce a message digest (a hash block) using the input data. - ******************************************************************************/ -sl_status_t sl_se_hash(sl_se_command_context_t *cmd_ctx, - sl_se_hash_type_t hash_type, - const uint8_t *message, - unsigned int message_size, - uint8_t* digest, - size_t digest_len) -{ - if (cmd_ctx == NULL - || digest == NULL - || (message == NULL - && message_size != 0)) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t command_word = SLI_SE_COMMAND_HASH; - uint32_t digest_size = 0; - - switch (hash_type) { - case SL_SE_HASH_SHA1: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; - digest_size = 20; - break; - case SL_SE_HASH_SHA224: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; - digest_size = 28; - break; - case SL_SE_HASH_SHA256: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; - digest_size = 32; - break; -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; - digest_size = 48; - break; - case SL_SE_HASH_SHA512: - digest_size = 64; - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; - break; -#endif - default: - return SL_STATUS_INVALID_PARAMETER; - } - - if ( digest_len < digest_size ) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, command_word); - - SE_addParameter(se_cmd, message_size); - - SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(message, message_size); - SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(digest, digest_size); - - SE_addDataInput(se_cmd, &data_in); - SE_addDataOutput(se_cmd, &data_out); - - // Execute and wait - return sli_se_execute_and_wait(cmd_ctx); -} - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include "sl_assert.h" +#include + +/***************************************************************************//** + * \addtogroup sl_se Secure Engine Manager API + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Global functions + +/***************************************************************************//** + * Start a SHA1 stream operation. + ******************************************************************************/ +sl_status_t sl_se_hash_sha1_multipart_starts(sl_se_sha1_multipart_context_t *sha1_ctx, + sl_se_command_context_t *cmd_ctx) +{ + static const uint8_t init_state_sha1[32] = { + 0x67, 0x45, 0x23, 0x01, + 0xEF, 0xCD, 0xAB, 0x89, + 0x98, 0xBA, 0xDC, 0xFE, + 0x10, 0x32, 0x54, 0x76, + 0xC3, 0xD2, 0xE1, 0xF0, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + }; + + if (cmd_ctx == NULL || sha1_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sha1_ctx->total[0] = 0; + sha1_ctx->total[1] = 0; + memcpy(sha1_ctx->state, init_state_sha1, sizeof(sha1_ctx->state)); + + sha1_ctx->hash_type = SL_SE_HASH_SHA1; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Start a SHA224 stream operation. + ******************************************************************************/ +sl_status_t +sl_se_hash_sha224_multipart_starts(sl_se_sha224_multipart_context_t *sha224_ctx, + sl_se_command_context_t *cmd_ctx) +{ + static const uint8_t init_state_sha224[32] = { + 0xC1, 0x05, 0x9E, 0xD8, + 0x36, 0x7C, 0xD5, 0x07, + 0x30, 0x70, 0xDD, 0x17, + 0xF7, 0x0E, 0x59, 0x39, + 0xFF, 0xC0, 0x0B, 0x31, + 0x68, 0x58, 0x15, 0x11, + 0x64, 0xF9, 0x8F, 0xA7, + 0xBE, 0xFA, 0x4F, 0xA4 + }; + + if (cmd_ctx == NULL || sha224_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sha224_ctx->total[0] = 0; + sha224_ctx->total[1] = 0; + memcpy(sha224_ctx->state, init_state_sha224, sizeof(sha224_ctx->state)); + + sha224_ctx->hash_type = SL_SE_HASH_SHA224; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Start a SHA256 stream operation. + ******************************************************************************/ +sl_status_t +sl_se_hash_sha256_multipart_starts(sl_se_sha256_multipart_context_t *sha256_ctx, + sl_se_command_context_t *cmd_ctx) +{ + static const uint8_t init_state_sha256[32] = { + 0x6A, 0x09, 0xE6, 0x67, + 0xBB, 0x67, 0xAE, 0x85, + 0x3C, 0x6E, 0xF3, 0x72, + 0xA5, 0x4F, 0xF5, 0x3A, + 0x51, 0x0E, 0x52, 0x7F, + 0x9B, 0x05, 0x68, 0x8C, + 0x1F, 0x83, 0xD9, 0xAB, + 0x5B, 0xE0, 0xCD, 0x19 + }; + + if (cmd_ctx == NULL || sha256_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sha256_ctx->total[0] = 0; + sha256_ctx->total[1] = 0; + memcpy(sha256_ctx->state, init_state_sha256, sizeof(sha256_ctx->state)); + + sha256_ctx->hash_type = SL_SE_HASH_SHA256; + + return SL_STATUS_OK; +} + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * Start a SHA384 stream operation. + ******************************************************************************/ +sl_status_t +sl_se_hash_sha384_multipart_starts(sl_se_sha384_multipart_context_t *sha384_ctx, + sl_se_command_context_t *cmd_ctx) +{ + static const uint8_t init_state_sha384[64] = { + 0xCB, 0xBB, 0x9D, 0x5D, 0xC1, 0x05, 0x9E, 0xD8, + 0x62, 0x9A, 0x29, 0x2A, 0x36, 0x7C, 0xD5, 0x07, + 0x91, 0x59, 0x01, 0x5A, 0x30, 0x70, 0xDD, 0x17, + 0x15, 0x2F, 0xEC, 0xD8, 0xF7, 0x0E, 0x59, 0x39, + 0x67, 0x33, 0x26, 0x67, 0xFF, 0xC0, 0x0B, 0x31, + 0x8E, 0xB4, 0x4A, 0x87, 0x68, 0x58, 0x15, 0x11, + 0xDB, 0x0C, 0x2E, 0x0D, 0x64, 0xF9, 0x8F, 0xA7, + 0x47, 0xB5, 0x48, 0x1D, 0xBE, 0xFA, 0x4F, 0xA4 + }; + + if (cmd_ctx == NULL || sha384_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sha384_ctx->total[0] = 0; + sha384_ctx->total[1] = 0; + sha384_ctx->total[2] = 0; + sha384_ctx->total[3] = 0; + memcpy(sha384_ctx->state, init_state_sha384, sizeof(sha384_ctx->state)); + + sha384_ctx->hash_type = SL_SE_HASH_SHA384; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Start a SHA512 stream operation. + ******************************************************************************/ +sl_status_t +sl_se_hash_sha512_multipart_starts(sl_se_sha512_multipart_context_t *sha512_ctx, sl_se_command_context_t *cmd_ctx) +{ + static const uint8_t init_state_sha512[64] = { + 0x6A, 0x09, 0xE6, 0x67, 0xF3, 0xBC, 0xC9, 0x08, + 0xBB, 0x67, 0xAE, 0x85, 0x84, 0xCA, 0xA7, 0x3B, + 0x3C, 0x6E, 0xF3, 0x72, 0xFE, 0x94, 0xF8, 0x2B, + 0xA5, 0x4F, 0xF5, 0x3A, 0x5F, 0x1D, 0x36, 0xF1, + 0x51, 0x0E, 0x52, 0x7F, 0xAD, 0xE6, 0x82, 0xD1, + 0x9B, 0x05, 0x68, 0x8C, 0x2B, 0x3E, 0x6C, 0x1F, + 0x1F, 0x83, 0xD9, 0xAB, 0xFB, 0x41, 0xBD, 0x6B, + 0x5B, 0xE0, 0xCD, 0x19, 0x13, 0x7E, 0x21, 0x79 + }; + + if (cmd_ctx == NULL || sha512_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sha512_ctx->total[0] = 0; + sha512_ctx->total[1] = 0; + sha512_ctx->total[2] = 0; + sha512_ctx->total[3] = 0; + memcpy(sha512_ctx->state, init_state_sha512, sizeof(sha512_ctx->state)); + + sha512_ctx->hash_type = SL_SE_HASH_SHA512; + + return SL_STATUS_OK; +} + +#endif + +/***************************************************************************//** + * Start a hash stream operation. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_starts(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type) +{ + if (cmd_ctx == NULL || hash_type_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (hash_type) { + case SL_SE_HASH_SHA1: + return sl_se_hash_sha1_multipart_starts((sl_se_sha1_multipart_context_t*) + hash_type_ctx, cmd_ctx); + + case SL_SE_HASH_SHA224: + return sl_se_hash_sha224_multipart_starts((sl_se_sha224_multipart_context_t*) + hash_type_ctx, cmd_ctx); + + case SL_SE_HASH_SHA256: + return sl_se_hash_sha256_multipart_starts((sl_se_sha256_multipart_context_t*) + hash_type_ctx, cmd_ctx); + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + return sl_se_hash_sha384_multipart_starts((sl_se_sha384_multipart_context_t*) + hash_type_ctx, + cmd_ctx); + + case SL_SE_HASH_SHA512: + return sl_se_hash_sha512_multipart_starts((sl_se_sha512_multipart_context_t*) + hash_type_ctx, cmd_ctx); +#endif + + default: + return SL_STATUS_INVALID_PARAMETER; + } +} + +/***************************************************************************//** + * Feeds an input block into an ongoing hash computation. + ******************************************************************************/ +static sl_status_t se_cmd_hash_multipart_update(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + const uint8_t *input, + uint32_t num_blocks) +{ + SE_Command_t *se_cmd = &cmd_ctx->command; + uint8_t *state; + uint32_t command_word = SLI_SE_COMMAND_HASHUPDATE; + size_t state_len, blocksize; + + switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { + case SL_SE_HASH_SHA1: + state = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->state; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; + state_len = 20; + blocksize = 64; + break; + case SL_SE_HASH_SHA224: + state = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->state; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; + state_len = 32; + blocksize = 64; + break; + case SL_SE_HASH_SHA256: + state = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->state; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; + state_len = 32; + blocksize = 64; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + state = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->state; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; + state_len = 64; + blocksize = 128; + break; + case SL_SE_HASH_SHA512: + state = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->state; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; + state_len = 64; + blocksize = 128; + break; +#endif + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + size_t ilen = blocksize * num_blocks; + SE_addParameter(se_cmd, ilen); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(input, ilen); + SE_DataTransfer_t iv_in = SE_DATATRANSFER_DEFAULT(state, state_len); + SE_DataTransfer_t iv_out = SE_DATATRANSFER_DEFAULT(state, state_len); + + SE_addDataInput(se_cmd, &iv_in); + SE_addDataInput(se_cmd, &data_in); + SE_addDataOutput(se_cmd, &iv_out); + + // Execute and wait + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Feeds an input buffer into an ongoing hash computation. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_update(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + const uint8_t *input, + size_t input_len) +{ + size_t blocks, fill, left, blocksize, countersize; + sl_status_t status; + uint8_t *buffer; + uint32_t *counter; + + if ( input_len == 0 ) { + return SL_STATUS_OK; + } + + if (hash_type_ctx == NULL || cmd_ctx == NULL || input == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { + case SL_SE_HASH_SHA1: + counter = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->total; + buffer = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->buffer; + blocksize = 64; + break; + case SL_SE_HASH_SHA224: + counter = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->total; + buffer = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->buffer; + blocksize = 64; + break; + case SL_SE_HASH_SHA256: + counter = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->total; + buffer = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->buffer; + blocksize = 64; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + counter = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->total; + buffer = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->buffer; + blocksize = 128; + break; + case SL_SE_HASH_SHA512: + counter = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->total; + buffer = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->buffer; + blocksize = 128; + break; +#endif + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + countersize = blocksize / 32; + left = (counter[0] & (blocksize - 1)); + fill = blocksize - left; + + counter[0] += input_len; + + // ripple counter + if ( counter[0] < input_len ) { + counter[1] += 1; +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + for (size_t i = 1; i < (countersize - 1); i++) { + if ( counter[i] == 0 ) { + counter[i + 1]++; + } + } +#else + (void)countersize; +#endif + } + + // We only support hashing up to 4 GB data + // so if anything but counter[0] is set, return NOT_SUPPORTED +#if defined(SLI_SE_MAJOR_VERSION_TWO) + for (size_t i = 1; i < countersize; i++) { + if (counter[i] != 0) { + return SL_STATUS_NOT_SUPPORTED; + } + } +#endif + + if ( (left > 0) && (input_len >= fill) ) { + memcpy( (void *) (buffer + left), input, fill); + status = se_cmd_hash_multipart_update(hash_type_ctx, cmd_ctx, buffer, 1); + if (status != SL_STATUS_OK) { + return status; + } + input += fill; + input_len -= fill; + left = 0; + } + + if ( input_len >= blocksize ) { + blocks = input_len / blocksize; + status = se_cmd_hash_multipart_update(hash_type_ctx, cmd_ctx, input, blocks); + if (status != SL_STATUS_OK) { + return status; + } + input += blocksize * blocks; + input_len -= blocksize * blocks; + } + + if ( input_len > 0 ) { + memcpy( (void *) (buffer + left), input, input_len); + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Finish an ongoing hash streaming computation. + ******************************************************************************/ +sl_status_t sl_se_hash_multipart_finish(void *hash_type_ctx, + sl_se_command_context_t *cmd_ctx, + uint8_t *digest_out, + size_t digest_len) +{ + sl_status_t status; + size_t countersize, blocksize, outputsize; + uint8_t *state; + uint32_t *counter; +#if defined(SLI_SE_MAJOR_VERSION_TWO) + uint32_t command_word = SLI_SE_COMMAND_HASHFINISH; + uint8_t *buffer; + size_t state_len; +#else + size_t last_data_byte, num_pad_bytes; + uint8_t msglen[16]; + // Define padding as largest padding we might need + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + static const unsigned char sha_padding[128] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + #else + static const unsigned char sha_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + #endif +#endif + if (hash_type_ctx == NULL || cmd_ctx == NULL || digest_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (((sl_se_sha1_multipart_context_t*)hash_type_ctx)->hash_type) { + case SL_SE_HASH_SHA1: + state = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->state; + counter = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->total; + outputsize = 20; + blocksize = 64; + #if defined(SLI_SE_MAJOR_VERSION_TWO) + state_len = 20; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; + buffer = ((sl_se_sha1_multipart_context_t*)hash_type_ctx)->buffer; + #endif + break; + case SL_SE_HASH_SHA224: + state = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->state; + counter = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->total; + outputsize = 28; + blocksize = 64; + #if defined(SLI_SE_MAJOR_VERSION_TWO) + state_len = 32; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; + buffer = ((sl_se_sha224_multipart_context_t*)hash_type_ctx)->buffer; + #endif + break; + case SL_SE_HASH_SHA256: + state = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->state; + counter = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->total; + outputsize = 32; + blocksize = 64; + #if defined(SLI_SE_MAJOR_VERSION_TWO) + state_len = 32; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; + buffer = ((sl_se_sha256_multipart_context_t*)hash_type_ctx)->buffer; + #endif + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + state = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->state; + counter = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->total; + outputsize = 48; + blocksize = 128; + #if defined(SLI_SE_MAJOR_VERSION_TWO) + state_len = 64; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; + buffer = ((sl_se_sha384_multipart_context_t*)hash_type_ctx)->buffer; + #endif + break; + case SL_SE_HASH_SHA512: + state = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->state; + counter = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->total; + outputsize = 64; + blocksize = 128; + #if defined(SLI_SE_MAJOR_VERSION_TWO) + state_len = 64; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; + buffer = ((sl_se_sha512_multipart_context_t*)hash_type_ctx)->buffer; + #endif + break; +#endif + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + if ( digest_len < outputsize ) { + return SL_STATUS_INVALID_PARAMETER; + } + + countersize = blocksize / 32; +#if defined(SLI_SE_MAJOR_VERSION_TWO) + + // We only support hashing up to 4 GB data + // so if anything but counter[0] is set, return NOT_SUPPORTED + for (size_t i = 1; i < countersize; i++) { + if (counter[i] != 0) { + return SL_STATUS_NOT_SUPPORTED; + } + } + // Remaining bytes in buffer + size_t rem_bytes = (counter[0] & (blocksize - 1)); + + SE_Command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, command_word); + + SE_addParameter(se_cmd, rem_bytes); + SE_addParameter(se_cmd, counter[0]); + + SE_DataTransfer_t in_0 = SE_DATATRANSFER_DEFAULT(state, state_len); + SE_DataTransfer_t in_1 = SE_DATATRANSFER_DEFAULT(buffer, rem_bytes); + SE_DataTransfer_t out = SE_DATATRANSFER_DEFAULT(digest_out, outputsize); + + SE_addDataInput(se_cmd, &in_0); + SE_addDataInput(se_cmd, &in_1); + SE_addDataOutput(se_cmd, &out); + + // Execute and wait + status = sli_se_execute_and_wait(cmd_ctx); +#else + + /* Convert counter value to bits, and put in big-endian array */ + uint8_t residual = 0; + for (size_t i = 0; i < countersize; i++) { + size_t msglen_index = ( (countersize - i) * sizeof(uint32_t) ) - 1; + + msglen[msglen_index - 0] = ((counter[i] << 3) + residual) & 0xFF; + msglen[msglen_index - 1] = (counter[i] >> 5) & 0xFF; + msglen[msglen_index - 2] = (counter[i] >> 13) & 0xFF; + msglen[msglen_index - 3] = (counter[i] >> 21) & 0xFF; + + residual = (counter[i] >> 29) & 0xFF; + } + + last_data_byte = (counter[0] & (blocksize - 1) ); + num_pad_bytes = (last_data_byte < (blocksize - (countersize * 4)) ) + ? ( (blocksize - (countersize * 4)) - last_data_byte) + : ( ((2 * blocksize) - (countersize * 4)) - last_data_byte); + + status = sl_se_hash_multipart_update(hash_type_ctx, cmd_ctx, sha_padding, num_pad_bytes); + + if (status == SL_STATUS_OK) { + status = sl_se_hash_multipart_update(hash_type_ctx, cmd_ctx, msglen, countersize * 4); + } + + if (status == SL_STATUS_OK) { + memcpy(digest_out, state, outputsize); + } +#endif // SLI_SE_MAJOR_VERSION_TWO + return status; +} + +/***************************************************************************//** + * Produce a message digest (a hash block) using the input data. + ******************************************************************************/ +sl_status_t sl_se_hash(sl_se_command_context_t *cmd_ctx, + sl_se_hash_type_t hash_type, + const uint8_t *message, + unsigned int message_size, + uint8_t* digest, + size_t digest_len) +{ + if (cmd_ctx == NULL + || digest == NULL + || (message == NULL + && message_size != 0)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t command_word = SLI_SE_COMMAND_HASH; + uint32_t digest_size = 0; + + switch (hash_type) { + case SL_SE_HASH_SHA1: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; + digest_size = 20; + break; + case SL_SE_HASH_SHA224: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; + digest_size = 28; + break; + case SL_SE_HASH_SHA256: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; + digest_size = 32; + break; +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; + digest_size = 48; + break; + case SL_SE_HASH_SHA512: + digest_size = 64; + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; + break; +#endif + default: + return SL_STATUS_INVALID_PARAMETER; + } + + if ( digest_len < digest_size ) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, command_word); + + SE_addParameter(se_cmd, message_size); + + SE_DataTransfer_t data_in = SE_DATATRANSFER_DEFAULT(message, message_size); + SE_DataTransfer_t data_out = SE_DATATRANSFER_DEFAULT(digest, digest_size); + + SE_addDataInput(se_cmd, &data_in); + SE_addDataOutput(se_cmd, &data_out); + + // Execute and wait + return sli_se_execute_and_wait(cmd_ctx); +} + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c index d00a27e..c0af1e3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c @@ -1,1084 +1,1084 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include - -/***************************************************************************//** - * \addtogroup sl_se Secure Engine Manager API - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Defines - -#define KEYSPEC_DH_RESERVED 0x00000780U -// Constant from RFC 4492. -#define SL_SE_ECP_TLS_NAMED_CURVE 3 ///< ECCurveType's named_curve -#define SL_SE_TLSID_ECC_P256 23 ///< Named curve value for SECP256R1 - -// ----------------------------------------------------------------------------- -// Locals - -// ECJPAKE role -static const char * const ecjpake_id[] = { - "client", - "server" -}; - -// ----------------------------------------------------------------------------- -// Global Functions - -// ------------------------------- -// Elliptic-curve Diffie–Hellman - -/***************************************************************************//** - * ECDH shared secret computation. - ******************************************************************************/ -sl_status_t sl_se_ecdh_compute_shared_secret(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in_priv, - const sl_se_key_descriptor_t *key_in_pub, - const sl_se_key_descriptor_t *key_out) -{ - sl_status_t status; - uint32_t keyspec_out; - uint32_t keyspec_in; - uint32_t key_pubkey_size; - SE_DataTransfer_t pubkey_input_buffer; - SE_DataTransfer_t auth_buffer_out; - - if (cmd_ctx == NULL - || key_in_priv == NULL || key_in_pub == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - status = sli_key_check_equivalent(key_in_priv, key_in_pub, false, false); - if (status != SL_STATUS_OK) { - return status; - } - status = sli_key_get_size(key_in_pub, &key_pubkey_size); - if (status != SL_STATUS_OK) { - return status; - } - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - // The key out buffer size needs be large enough for non-volatile keys - if (key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { - if (key_in_priv->type == SL_SE_KEY_TYPE_ECC_X25519 - || key_in_priv->type == SL_SE_KEY_TYPE_ECC_X448) { - if (key_pubkey_size > key_out->storage.location.buffer.size) { - return SL_STATUS_INVALID_PARAMETER; - } - } else { - if ((key_pubkey_size * 2) > key_out->storage.location.buffer.size) { - return SL_STATUS_INVALID_PARAMETER; - } - } - } - #else - if (key_in_priv->type == SL_SE_KEY_TYPE_ECC_X25519) { - if (key_pubkey_size > key_out->storage.location.buffer.size) { - return SL_STATUS_INVALID_PARAMETER; - } - } else { - if ((key_pubkey_size * 2) > key_out->storage.location.buffer.size) { - return SL_STATUS_INVALID_PARAMETER; - } - } - #endif - - // Output of DH must be in RAW format - if (key_out->type != SL_SE_KEY_TYPE_SYMMETRIC) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DH); - - // Add key parameters to command - status = sli_se_key_to_keyspec(key_in_priv, &keyspec_in); - if (status != SL_STATUS_OK) { - return status; - } - keyspec_in = keyspec_in & ~KEYSPEC_DH_RESERVED; - SE_addParameter(&cmd_ctx->command, keyspec_in); - - status = sli_se_key_to_keyspec(key_out, &keyspec_out); - if (status != SL_STATUS_OK) { - return status; - } - SE_addParameter(&cmd_ctx->command, keyspec_out); - - // Add key input metadata block to command - sli_add_key_metadata(cmd_ctx, key_in_priv, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key_in_priv, status); - - if (key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { - // Add key output metadata block to command - status = sli_se_get_auth_buffer(key_out, &auth_buffer_out); - if (status != SL_STATUS_OK) { - return status; - } - SE_addDataInput(&cmd_ctx->command, &auth_buffer_out); - } - // Add key of other party - status = sli_se_get_key_input_output(key_in_pub, &pubkey_input_buffer); - if (status != SL_STATUS_OK) { - return status; - } - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (key_in_pub->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) { - if (key_in_pub->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) { - // If using custom domain, the key buffer stores domain parameters, - // however when computing the shared secret only the key is of interest. - uint32_t domain_size = ((sl_se_custom_weierstrass_prime_domain_t*)key_in_pub->domain)->size; - pubkey_input_buffer.data = &key_in_pub->storage.location.buffer.pointer[domain_size * 6]; - pubkey_input_buffer.length = (domain_size * 2) | SE_DATATRANSFER_REALIGN; - } else { - // Does not contain a public key. - return SL_STATUS_INVALID_KEY; - } - } - #endif - - SE_addDataInput(&cmd_ctx->command, &pubkey_input_buffer); - - // Add key output block to command - sli_add_key_output(cmd_ctx, key_out, status); - - // Execute command. - // The retries are necessary in order to reduce the risk of random failures - // in the accelerated point multiplication. This mainly affects very small or - // large scalars, which in this case would be the private key. - for (size_t i = 0; i < SLI_SE_MAX_POINT_MULT_RETRIES; ++i) { - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_FAIL) { - break; - } - } - return status; -} - -// ------------------------------- -// ECJPAKE - -/***************************************************************************//** - * Parse a ECJPAKE TLS point. - ******************************************************************************/ -static sl_status_t ecjpake_parse_tls_point(const uint8_t **ibuf, - size_t *ilen, - size_t *rlen, - uint8_t **obuf, size_t *olen) -{ - if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (*ilen == 0 || *ibuf == NULL || *obuf == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Consume first byte, length of what follows. - size_t field_length = **ibuf; - *ibuf += 1; - *ilen -= 1; - if (rlen != NULL) { - *rlen += 1; - } - - if (field_length > *ilen) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Consume second byte, point type. - uint8_t point_type = **ibuf; - size_t point_length = field_length - 1; - *ibuf += 1; - *ilen -= 1; - - switch (point_type) { - case 0x0: - // Why would we ever get a zero-point? - return SL_STATUS_INVALID_KEY; - case 0x04: - break; - case 0x05: - // We don't support compressed points... - return SL_STATUS_NOT_SUPPORTED; - default: - return SL_STATUS_INVALID_PARAMETER; - } - - // Copy out binary point. - if (point_length > *olen) { - return SL_STATUS_INVALID_PARAMETER; - } - - memcpy(*obuf, *ibuf, point_length); - *ibuf += point_length; - *ilen -= point_length; - *obuf += point_length; - *olen -= point_length; - if (rlen != NULL) { - *rlen += field_length; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Parse a ECJPAKE TLS zkp. - ******************************************************************************/ -static sl_status_t ecjpake_parse_tls_zkp(const uint8_t **ibuf, - size_t *ilen, - size_t *rlen, - uint8_t **obuf, - size_t *olen) -{ - if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (*ilen == 0 || *ibuf == NULL || *obuf == NULL || *olen < 96) { - return SL_STATUS_INVALID_PARAMETER; - } - - int ret = ecjpake_parse_tls_point(ibuf, ilen, rlen, obuf, olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - if (*ilen < 1) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Consume first byte, length of what follows. - size_t field_length = **ibuf; - *ibuf += 1; - *ilen -= 1; - if (rlen != NULL) { - *rlen += 1; - } - - if (field_length > *ilen || field_length > *olen) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (field_length == 0) { - // Scalar cannot be zero. - return SL_STATUS_INVALID_KEY; - } - - // Right-adjust. - size_t adjust_length = 32 - field_length; - memset(*obuf, 0, adjust_length); - *obuf += adjust_length; - *olen -= adjust_length; - - // Consume field. - memcpy(*obuf, *ibuf, field_length); - *obuf += field_length; - *olen -= field_length; - *ibuf += field_length; - *ilen -= field_length; - - if (rlen != NULL) { - *rlen += field_length; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Write a ECJPAKE TLS point. - ******************************************************************************/ -static sl_status_t ecjpake_write_tls_point(uint8_t **obuf, - size_t *olen, - size_t *wlen, - const uint8_t **ibuf, - size_t *ilen, - size_t point_length) -{ - if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (*obuf == NULL || *ibuf == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // We can only output uncompressed points here. - if (*olen < point_length + 2) { - return SL_STATUS_WOULD_OVERFLOW; - } - - if (*ilen < point_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - **obuf = point_length + 1; - *obuf += 1; - *olen -= 1; - - **obuf = 0x04; - *obuf += 1; - *olen -= 1; - - memcpy(*obuf, *ibuf, point_length); - - *obuf += point_length; - *olen -= point_length; - *ibuf += point_length; - *ilen -= point_length; - - if (wlen != NULL) { - *wlen += point_length + 2; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Write a ECJPAKE TLS zkp. - ******************************************************************************/ -static sl_status_t ecjpake_write_tls_zkp(uint8_t **obuf, - size_t *olen, - size_t *wlen, - const uint8_t **ibuf, - size_t *ilen, - size_t point_length) -{ - sl_status_t ret = SL_STATUS_OK; - - if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (*obuf == NULL || *ibuf == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - ret = ecjpake_write_tls_point(obuf, olen, wlen, ibuf, ilen, point_length); - - if (ret != SL_STATUS_OK) { - return ret; - } - - size_t zkp_length = 32; - - if (*olen < zkp_length + 1 || *ilen < zkp_length) { - return SL_STATUS_INVALID_PARAMETER; - } - - **obuf = zkp_length; - *obuf += 1; - *olen -= 1; - - memcpy(*obuf, *ibuf, zkp_length); - - *obuf += zkp_length; - *olen -= zkp_length; - *ibuf += zkp_length; - *ilen -= zkp_length; - - if (wlen != NULL) { - *wlen += zkp_length + 1; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Check if an ECJPAKE context is ready for use. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_check(const sl_se_ecjpake_context_t *ctx) -{ - if (ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (ctx->curve_flags == 0) { - return SL_STATUS_INVALID_PARAMETER; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Derive the shared secret. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_derive_secret(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen) -{ - sl_se_command_context_t *cmd_ctx; - SE_Command_t *se_cmd; - - if (ctx == NULL || buf == NULL || olen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (len < 32) { - return SL_STATUS_WOULD_OVERFLOW; - } - - cmd_ctx = ctx->cmd_ctx; - se_cmd = &ctx->cmd_ctx->command; - - // Generated session key needs to come out unprotected. - uint32_t gen_key_flags = 32; - - // SE command structures. - sli_se_command_init(cmd_ctx, - SLI_SE_COMMAND_JPAKE_GEN_SESSIONKEY - | SLI_SE_COMMAND_OPTION_HASH_SHA256); - SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); - SE_DataTransfer_t pwd_in = SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); - SE_DataTransfer_t r_in = SE_DATATRANSFER_DEFAULT(ctx->r, 32); - SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); - SE_DataTransfer_t Xp_in = SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); - SE_DataTransfer_t key_out = SE_DATATRANSFER_DEFAULT(buf, 32); - - SE_addDataInput(se_cmd, &domain_in); - SE_addDataInput(se_cmd, &pwd_in); - SE_addDataInput(se_cmd, &r_in); - SE_addDataInput(se_cmd, &Xp2_in); - SE_addDataInput(se_cmd, &Xp_in); - - SE_addDataOutput(se_cmd, &key_out); - - SE_addParameter(se_cmd, ctx->curve_flags); - SE_addParameter(se_cmd, ctx->pwd_len); - SE_addParameter(se_cmd, gen_key_flags); - - sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - *olen = 32; - } else { - *olen = 0; - } - return ret; -} - -/***************************************************************************//** - * This clears an ECJPAKE context. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_free(sl_se_ecjpake_context_t *ctx) -{ - if (ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - memset(ctx, 0, sizeof(*ctx)); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Initialize an ECJPAKE context. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_init(sl_se_ecjpake_context_t *ctx, - sl_se_command_context_t *cmd_ctx) -{ - if (ctx == NULL || cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - memset(ctx, 0, sizeof(*ctx)); - - // store pointer to command context object - ctx->cmd_ctx = cmd_ctx; - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Read and process the first round message. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_read_round_one(sl_se_ecjpake_context_t *ctx, - const unsigned char *buf, - size_t len) -{ - sl_status_t ret = SL_STATUS_OK; - - if (ctx == NULL || buf == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; - SE_Command_t *se_cmd = &ctx->cmd_ctx->command; - - // We should receive 2 binary points and 2 ZKP's. - - // Local storage for ZKP's. - uint8_t zkp1[32 + 64] = { 0 }; - uint8_t zkp2[32 + 64] = { 0 }; - - uint8_t *obuf = ctx->Xp1; - size_t olen = 64; - - // Parse structures. - ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - obuf = zkp1; - olen = 96; - ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - obuf = ctx->Xp2; - olen = 64; - ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - obuf = zkp2; - olen = 96; - ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - if (len > 0) { - // Too much input. - return SL_STATUS_WOULD_OVERFLOW; - } - - // SE command structures. - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R1_VERIFY); - SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); - SE_DataTransfer_t userid_mine = SE_DATATRANSFER_DEFAULT( - (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); - SE_DataTransfer_t userid_peer = SE_DATATRANSFER_DEFAULT( - (void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); - SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); - SE_DataTransfer_t zkp1_in = SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); - SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); - SE_DataTransfer_t zkp2_in = SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); - - SE_addDataInput(se_cmd, &domain_in); - SE_addDataInput(se_cmd, &userid_mine); - SE_addDataInput(se_cmd, &userid_peer); - SE_addDataInput(se_cmd, &Xp1_in); - SE_addDataInput(se_cmd, &zkp1_in); - SE_addDataInput(se_cmd, &Xp2_in); - SE_addDataInput(se_cmd, &zkp2_in); - - SE_addParameter(se_cmd, ctx->curve_flags); - SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); - SE_addParameter(se_cmd, strlen(ecjpake_id[1 - ctx->role])); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read and process the second round message. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_read_round_two(sl_se_ecjpake_context_t *ctx, - const unsigned char *buf, - size_t len) -{ - if (ctx == NULL || buf == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; - SE_Command_t *se_cmd = &ctx->cmd_ctx->command; - sl_status_t ret = SL_STATUS_OK; - - // Local storage for ZKP. - uint8_t zkpB[32 + 64]; - - if (ctx->role == SL_SE_ECJPAKE_CLIENT) { - uint16_t tls_id; - - if (len < 3) { - return SL_STATUS_INVALID_PARAMETER; - } - - // First byte is curve_type; only named_curve is handled. - if (*(buf++) != SL_SE_ECP_TLS_NAMED_CURVE) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Next two bytes are the namedcurve value. - tls_id = *(buf++); - tls_id <<= 8; - tls_id |= *(buf++); - - // We support only one curve. - if (tls_id != SL_SE_TLSID_ECC_P256) { - return SL_STATUS_NOT_SUPPORTED; - } - - len -= 3; - } - - // We should receive 1 binary point and 1 ZKP. - uint8_t *obuf = ctx->Xp; - size_t olen = 64; - - // Parse structures. - ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - obuf = zkpB; - olen = sizeof(zkpB); - ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); - if (ret != SL_STATUS_OK) { - return ret; - } - - if (len > 0) { - // Too much input. - return SL_STATUS_WOULD_OVERFLOW; - } - - // SE command structures. - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R2_VERIFY); - SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); - SE_DataTransfer_t userid_peer = SE_DATATRANSFER_DEFAULT( - (void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); - SE_DataTransfer_t Xm1_in = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); - SE_DataTransfer_t Xm2_in = SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); - SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); - SE_DataTransfer_t Xp_in = SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); - SE_DataTransfer_t zkpB_in = SE_DATATRANSFER_DEFAULT(zkpB, sizeof(zkpB)); - - SE_addDataInput(se_cmd, &domain_in); - SE_addDataInput(se_cmd, &userid_peer); - SE_addDataInput(se_cmd, &Xm1_in); - SE_addDataInput(se_cmd, &Xm2_in); - SE_addDataInput(se_cmd, &Xp1_in); - SE_addDataInput(se_cmd, &Xp_in); - SE_addDataInput(se_cmd, &zkpB_in); - - SE_addParameter(se_cmd, ctx->curve_flags); - SE_addParameter(se_cmd, strlen(ecjpake_id[1 - ctx->role])); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Set up an ECJPAKE context for use. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_setup(sl_se_ecjpake_context_t *ctx, - sl_se_ecjpake_role_t role, - sl_se_hash_type_t hash, - uint32_t curve, - const unsigned char *secret, - size_t len) -{ - if (ctx == NULL || (len > 0 && secret == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE only supports passphrases of maximum 32 bytes. - if (len > sizeof(ctx->pwd)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE currently only supports SHA256 as JPAKE hashing mechanism. - if (hash != SL_SE_HASH_SHA256) { - return SL_STATUS_NOT_SUPPORTED; - } - - // SE currently only supports ECDSA secp256r1 as curve. - if (curve != SL_SE_KEY_TYPE_ECC_P256) { - return SL_STATUS_NOT_SUPPORTED; - } - - ctx->curve_flags = 0x8000001FUL; - ctx->role = role; - ctx->pwd_len = len; - memcpy(ctx->pwd, secret, len); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Generate and write the first round message. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_write_round_one(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen) -{ - sl_status_t ret = SL_STATUS_OK; - - if (ctx == NULL || buf == NULL || olen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; - SE_Command_t *se_cmd = &ctx->cmd_ctx->command; - *olen = 0; - - // Local storage for ZKP's. - uint8_t zkp1[32 + 64]; - uint8_t zkp2[32 + 64]; - - // SE command structures. - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R1_GENERATE); - SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); - SE_DataTransfer_t userid = SE_DATATRANSFER_DEFAULT( - (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); - SE_DataTransfer_t r_out = SE_DATATRANSFER_DEFAULT(ctx->r, 32); - SE_DataTransfer_t Xm1_out = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); - SE_DataTransfer_t zkp1_out = SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); - SE_DataTransfer_t Xm2_out = SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); - SE_DataTransfer_t zkp2_out = SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); - - SE_addDataInput(se_cmd, &domain_in); - SE_addDataInput(se_cmd, &userid); - - SE_addDataOutput(se_cmd, &r_out); - SE_addDataOutput(se_cmd, &Xm1_out); - SE_addDataOutput(se_cmd, &zkp1_out); - SE_addDataOutput(se_cmd, &Xm2_out); - SE_addDataOutput(se_cmd, &zkp2_out); - - SE_addParameter(se_cmd, ctx->curve_flags); - SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); - - ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - // To write TLS structures of ECJ-PAKE, we need to write: - // Xm1, zkp1, Xm2 and zkp2. - uint8_t *obuf = buf; - const uint8_t *ibuf = ctx->Xm1; - size_t ilen = 64; - - ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); - if (ret != SL_STATUS_OK) { - return ret; - } - - ibuf = zkp1; - ilen = 96; - ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); - if (ret != SL_STATUS_OK) { - return ret; - } - - ibuf = ctx->Xm2; - ilen = 64; - ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); - if (ret != SL_STATUS_OK) { - return ret; - } - - ibuf = zkp2; - ilen = 96; - ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); - } - return ret; -} - -/***************************************************************************//** - * Generate and write the second round message. - ******************************************************************************/ -sl_status_t sl_se_ecjpake_write_round_two(sl_se_ecjpake_context_t *ctx, - unsigned char *buf, - size_t len, - size_t *olen) -{ - sl_status_t ret = SL_STATUS_OK; - - if (ctx == NULL || buf == NULL || olen == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; - SE_Command_t *se_cmd = &ctx->cmd_ctx->command; - - *olen = 0; - - uint8_t zkpA[32 + 64]; - uint8_t xA[64]; - - // SE command structures. - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R2_GENERATE); - SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); - SE_DataTransfer_t pwd_in = SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); - SE_DataTransfer_t userid = SE_DATATRANSFER_DEFAULT( - (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); - SE_DataTransfer_t r_in = SE_DATATRANSFER_DEFAULT(ctx->r, 32); - SE_DataTransfer_t Xm1_in = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); - SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); - SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); - SE_DataTransfer_t xA_out = SE_DATATRANSFER_DEFAULT(xA, sizeof(xA)); - SE_DataTransfer_t zkpA_out = SE_DATATRANSFER_DEFAULT(zkpA, sizeof(zkpA)); - - SE_addDataInput(se_cmd, &domain_in); - SE_addDataInput(se_cmd, &pwd_in); - SE_addDataInput(se_cmd, &userid); - SE_addDataInput(se_cmd, &r_in); - SE_addDataInput(se_cmd, &Xm1_in); - SE_addDataInput(se_cmd, &Xp1_in); - SE_addDataInput(se_cmd, &Xp2_in); - - SE_addDataOutput(se_cmd, &xA_out); - SE_addDataOutput(se_cmd, &zkpA_out); - - SE_addParameter(se_cmd, ctx->curve_flags); - SE_addParameter(se_cmd, ctx->pwd_len); - SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); - - ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SLI_SE_RESPONSE_OK) { - // If we are the server, we need to write out the ECParams. - if (ctx->role == SL_SE_ECJPAKE_SERVER) { - if (len < 3 + 66 + 66 + 33) { - return SL_STATUS_WOULD_OVERFLOW; - } - // First byte is curve_type, always named_curve. - *(buf++) = SL_SE_ECP_TLS_NAMED_CURVE; - - // Next two bytes are the namedcurve value, we only support one. - *(buf++) = SL_SE_TLSID_ECC_P256 >> 8; - *(buf++) = SL_SE_TLSID_ECC_P256 & 0xFF; - - *olen += 3; - len -= 3; - } - - // To write TLS structures of ECJ-PAKE, we need to write: - // xA in uncompressed form and zkpA in uncompressed form - uint8_t *obuf = buf; - const uint8_t *ibuf = xA; - size_t ilen = 64; - - ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); - if (ret != SL_STATUS_OK) { - return ret; - } - - ibuf = zkpA; - ilen = 96; - ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); - } - - return ret; -} - -// ------------------------------- -// Key derivation functions - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -/***************************************************************************//** - * HKDF key derivation. - ******************************************************************************/ -sl_status_t sl_se_derive_key_hkdf(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *in_key, - sl_se_hash_type_t hash, - const unsigned char *salt, - size_t salt_len, - const unsigned char *info, - size_t info_len, - sl_se_key_descriptor_t *out_key) -{ - uint32_t hash_mask; - sl_status_t status = SL_STATUS_OK; - - if ((cmd_ctx == NULL) || (in_key == NULL) || (out_key == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - if ((salt == NULL) && (salt_len != 0U)) { - return SL_STATUS_INVALID_PARAMETER; - } - if ((info == NULL) && (info_len != 0U)) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (hash) { - case SL_SE_HASH_SHA1: - hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA1; - break; - - case SL_SE_HASH_SHA224: - hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA224; - break; - - case SL_SE_HASH_SHA256: - hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA256; - break; - - case SL_SE_HASH_SHA384: - hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA384; - break; - - case SL_SE_HASH_SHA512: - hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA512; - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } - - // SE command structures. - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DERIVE_KEY_HKDF | hash_mask); - - sli_add_key_parameters(cmd_ctx, in_key, status); - SE_addParameter(se_cmd, salt_len); - SE_addParameter(se_cmd, info_len); - sli_add_key_parameters(cmd_ctx, out_key, status); - - sli_add_key_metadata(cmd_ctx, in_key, status); - sli_add_key_input(cmd_ctx, in_key, status); - - sli_add_key_metadata_custom(cmd_ctx, auth_data, out_key, status); - - SE_DataTransfer_t salt_in = SE_DATATRANSFER_DEFAULT(salt, salt_len); - SE_addDataInput(se_cmd, &salt_in); - - SE_DataTransfer_t info_in = SE_DATATRANSFER_DEFAULT(info, info_len); - SE_addDataInput(se_cmd, &info_in); - - sli_add_key_output(cmd_ctx, out_key, status); - - status = sli_se_execute_and_wait(cmd_ctx); - - return status; -} -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - -#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ - && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) -/***************************************************************************//** - * PBKDF2 key derivation. - ******************************************************************************/ -sl_status_t sl_se_derive_key_pbkdf2(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *in_key, - sl_se_pbkdf2_prf_type_t prf, - const unsigned char *salt, - size_t salt_len, - uint32_t iterations, - sl_se_key_descriptor_t *out_key) -{ - sl_status_t status = SL_STATUS_OK; - uint32_t command_word = 0U; - - if ((cmd_ctx == NULL) || (in_key == NULL) || (out_key == NULL)) { - return SL_STATUS_INVALID_PARAMETER; - } - if ((salt == NULL) && (salt_len != 0U)) { - return SL_STATUS_INVALID_PARAMETER; - } - // Too many iterations will trigger SE watchdog. - if ((iterations == 0U) || (iterations > 16384U)) { - return SL_STATUS_INVALID_PARAMETER; - } - - switch (prf) { - case SL_SE_PRF_HMAC_SHA1: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC - | SLI_SE_COMMAND_OPTION_HASH_SHA1; - break; - - case SL_SE_PRF_HMAC_SHA224: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC - | SLI_SE_COMMAND_OPTION_HASH_SHA224; - break; - - case SL_SE_PRF_HMAC_SHA256: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC - | SLI_SE_COMMAND_OPTION_HASH_SHA256; - break; - - case SL_SE_PRF_HMAC_SHA384: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC - | SLI_SE_COMMAND_OPTION_HASH_SHA384; - break; - - case SL_SE_PRF_HMAC_SHA512: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC - | SLI_SE_COMMAND_OPTION_HASH_SHA512; - break; - -#if defined(SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE) - // PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. - case SL_SE_PRF_AES_CMAC_128: - command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC; - break; -#endif - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } - - // SE command structures. - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, command_word); - - sli_add_key_parameters(cmd_ctx, in_key, status); - SE_addParameter(se_cmd, salt_len); - SE_addParameter(se_cmd, iterations); - sli_add_key_parameters(cmd_ctx, out_key, status); - - sli_add_key_metadata(cmd_ctx, in_key, status); - sli_add_key_input(cmd_ctx, in_key, status); - - sli_add_key_metadata_custom(cmd_ctx, auth_data, out_key, status); - - SE_DataTransfer_t salt_in = SE_DATATRANSFER_DEFAULT(salt, salt_len); - SE_addDataInput(se_cmd, &salt_in); - - sli_add_key_output(cmd_ctx, out_key, status); - - status = sli_se_execute_and_wait(cmd_ctx); - - return status; -} -#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include + +/***************************************************************************//** + * \addtogroup sl_se Secure Engine Manager API + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +#define KEYSPEC_DH_RESERVED 0x00000780U +// Constant from RFC 4492. +#define SL_SE_ECP_TLS_NAMED_CURVE 3 ///< ECCurveType's named_curve +#define SL_SE_TLSID_ECC_P256 23 ///< Named curve value for SECP256R1 + +// ----------------------------------------------------------------------------- +// Locals + +// ECJPAKE role +static const char * const ecjpake_id[] = { + "client", + "server" +}; + +// ----------------------------------------------------------------------------- +// Global Functions + +// ------------------------------- +// Elliptic-curve Diffie–Hellman + +/***************************************************************************//** + * ECDH shared secret computation. + ******************************************************************************/ +sl_status_t sl_se_ecdh_compute_shared_secret(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in_priv, + const sl_se_key_descriptor_t *key_in_pub, + const sl_se_key_descriptor_t *key_out) +{ + sl_status_t status; + uint32_t keyspec_out; + uint32_t keyspec_in; + uint32_t key_pubkey_size; + SE_DataTransfer_t pubkey_input_buffer; + SE_DataTransfer_t auth_buffer_out; + + if (cmd_ctx == NULL + || key_in_priv == NULL || key_in_pub == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + status = sli_key_check_equivalent(key_in_priv, key_in_pub, false, false); + if (status != SL_STATUS_OK) { + return status; + } + status = sli_key_get_size(key_in_pub, &key_pubkey_size); + if (status != SL_STATUS_OK) { + return status; + } + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + // The key out buffer size needs be large enough for non-volatile keys + if (key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { + if (key_in_priv->type == SL_SE_KEY_TYPE_ECC_X25519 + || key_in_priv->type == SL_SE_KEY_TYPE_ECC_X448) { + if (key_pubkey_size > key_out->storage.location.buffer.size) { + return SL_STATUS_INVALID_PARAMETER; + } + } else { + if ((key_pubkey_size * 2) > key_out->storage.location.buffer.size) { + return SL_STATUS_INVALID_PARAMETER; + } + } + } + #else + if (key_in_priv->type == SL_SE_KEY_TYPE_ECC_X25519) { + if (key_pubkey_size > key_out->storage.location.buffer.size) { + return SL_STATUS_INVALID_PARAMETER; + } + } else { + if ((key_pubkey_size * 2) > key_out->storage.location.buffer.size) { + return SL_STATUS_INVALID_PARAMETER; + } + } + #endif + + // Output of DH must be in RAW format + if (key_out->type != SL_SE_KEY_TYPE_SYMMETRIC) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DH); + + // Add key parameters to command + status = sli_se_key_to_keyspec(key_in_priv, &keyspec_in); + if (status != SL_STATUS_OK) { + return status; + } + keyspec_in = keyspec_in & ~KEYSPEC_DH_RESERVED; + SE_addParameter(&cmd_ctx->command, keyspec_in); + + status = sli_se_key_to_keyspec(key_out, &keyspec_out); + if (status != SL_STATUS_OK) { + return status; + } + SE_addParameter(&cmd_ctx->command, keyspec_out); + + // Add key input metadata block to command + sli_add_key_metadata(cmd_ctx, key_in_priv, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key_in_priv, status); + + if (key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + // Add key output metadata block to command + status = sli_se_get_auth_buffer(key_out, &auth_buffer_out); + if (status != SL_STATUS_OK) { + return status; + } + SE_addDataInput(&cmd_ctx->command, &auth_buffer_out); + } + // Add key of other party + status = sli_se_get_key_input_output(key_in_pub, &pubkey_input_buffer); + if (status != SL_STATUS_OK) { + return status; + } + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (key_in_pub->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) { + if (key_in_pub->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) { + // If using custom domain, the key buffer stores domain parameters, + // however when computing the shared secret only the key is of interest. + uint32_t domain_size = ((sl_se_custom_weierstrass_prime_domain_t*)key_in_pub->domain)->size; + pubkey_input_buffer.data = &key_in_pub->storage.location.buffer.pointer[domain_size * 6]; + pubkey_input_buffer.length = (domain_size * 2) | SE_DATATRANSFER_REALIGN; + } else { + // Does not contain a public key. + return SL_STATUS_INVALID_KEY; + } + } + #endif + + SE_addDataInput(&cmd_ctx->command, &pubkey_input_buffer); + + // Add key output block to command + sli_add_key_output(cmd_ctx, key_out, status); + + // Execute command. + // The retries are necessary in order to reduce the risk of random failures + // in the accelerated point multiplication. This mainly affects very small or + // large scalars, which in this case would be the private key. + for (size_t i = 0; i < SLI_SE_MAX_POINT_MULT_RETRIES; ++i) { + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_FAIL) { + break; + } + } + return status; +} + +// ------------------------------- +// ECJPAKE + +/***************************************************************************//** + * Parse a ECJPAKE TLS point. + ******************************************************************************/ +static sl_status_t ecjpake_parse_tls_point(const uint8_t **ibuf, + size_t *ilen, + size_t *rlen, + uint8_t **obuf, size_t *olen) +{ + if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (*ilen == 0 || *ibuf == NULL || *obuf == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Consume first byte, length of what follows. + size_t field_length = **ibuf; + *ibuf += 1; + *ilen -= 1; + if (rlen != NULL) { + *rlen += 1; + } + + if (field_length > *ilen) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Consume second byte, point type. + uint8_t point_type = **ibuf; + size_t point_length = field_length - 1; + *ibuf += 1; + *ilen -= 1; + + switch (point_type) { + case 0x0: + // Why would we ever get a zero-point? + return SL_STATUS_INVALID_KEY; + case 0x04: + break; + case 0x05: + // We don't support compressed points... + return SL_STATUS_NOT_SUPPORTED; + default: + return SL_STATUS_INVALID_PARAMETER; + } + + // Copy out binary point. + if (point_length > *olen) { + return SL_STATUS_INVALID_PARAMETER; + } + + memcpy(*obuf, *ibuf, point_length); + *ibuf += point_length; + *ilen -= point_length; + *obuf += point_length; + *olen -= point_length; + if (rlen != NULL) { + *rlen += field_length; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Parse a ECJPAKE TLS zkp. + ******************************************************************************/ +static sl_status_t ecjpake_parse_tls_zkp(const uint8_t **ibuf, + size_t *ilen, + size_t *rlen, + uint8_t **obuf, + size_t *olen) +{ + if (ilen == NULL || ibuf == NULL || obuf == NULL || olen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (*ilen == 0 || *ibuf == NULL || *obuf == NULL || *olen < 96) { + return SL_STATUS_INVALID_PARAMETER; + } + + int ret = ecjpake_parse_tls_point(ibuf, ilen, rlen, obuf, olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + if (*ilen < 1) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Consume first byte, length of what follows. + size_t field_length = **ibuf; + *ibuf += 1; + *ilen -= 1; + if (rlen != NULL) { + *rlen += 1; + } + + if (field_length > *ilen || field_length > *olen) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (field_length == 0) { + // Scalar cannot be zero. + return SL_STATUS_INVALID_KEY; + } + + // Right-adjust. + size_t adjust_length = 32 - field_length; + memset(*obuf, 0, adjust_length); + *obuf += adjust_length; + *olen -= adjust_length; + + // Consume field. + memcpy(*obuf, *ibuf, field_length); + *obuf += field_length; + *olen -= field_length; + *ibuf += field_length; + *ilen -= field_length; + + if (rlen != NULL) { + *rlen += field_length; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Write a ECJPAKE TLS point. + ******************************************************************************/ +static sl_status_t ecjpake_write_tls_point(uint8_t **obuf, + size_t *olen, + size_t *wlen, + const uint8_t **ibuf, + size_t *ilen, + size_t point_length) +{ + if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (*obuf == NULL || *ibuf == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // We can only output uncompressed points here. + if (*olen < point_length + 2) { + return SL_STATUS_WOULD_OVERFLOW; + } + + if (*ilen < point_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + **obuf = point_length + 1; + *obuf += 1; + *olen -= 1; + + **obuf = 0x04; + *obuf += 1; + *olen -= 1; + + memcpy(*obuf, *ibuf, point_length); + + *obuf += point_length; + *olen -= point_length; + *ibuf += point_length; + *ilen -= point_length; + + if (wlen != NULL) { + *wlen += point_length + 2; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Write a ECJPAKE TLS zkp. + ******************************************************************************/ +static sl_status_t ecjpake_write_tls_zkp(uint8_t **obuf, + size_t *olen, + size_t *wlen, + const uint8_t **ibuf, + size_t *ilen, + size_t point_length) +{ + sl_status_t ret = SL_STATUS_OK; + + if (ibuf == NULL || obuf == NULL || olen == NULL || ilen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (*obuf == NULL || *ibuf == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + ret = ecjpake_write_tls_point(obuf, olen, wlen, ibuf, ilen, point_length); + + if (ret != SL_STATUS_OK) { + return ret; + } + + size_t zkp_length = 32; + + if (*olen < zkp_length + 1 || *ilen < zkp_length) { + return SL_STATUS_INVALID_PARAMETER; + } + + **obuf = zkp_length; + *obuf += 1; + *olen -= 1; + + memcpy(*obuf, *ibuf, zkp_length); + + *obuf += zkp_length; + *olen -= zkp_length; + *ibuf += zkp_length; + *ilen -= zkp_length; + + if (wlen != NULL) { + *wlen += zkp_length + 1; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Check if an ECJPAKE context is ready for use. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_check(const sl_se_ecjpake_context_t *ctx) +{ + if (ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (ctx->curve_flags == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Derive the shared secret. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_derive_secret(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen) +{ + sl_se_command_context_t *cmd_ctx; + SE_Command_t *se_cmd; + + if (ctx == NULL || buf == NULL || olen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (len < 32) { + return SL_STATUS_WOULD_OVERFLOW; + } + + cmd_ctx = ctx->cmd_ctx; + se_cmd = &ctx->cmd_ctx->command; + + // Generated session key needs to come out unprotected. + uint32_t gen_key_flags = 32; + + // SE command structures. + sli_se_command_init(cmd_ctx, + SLI_SE_COMMAND_JPAKE_GEN_SESSIONKEY + | SLI_SE_COMMAND_OPTION_HASH_SHA256); + SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); + SE_DataTransfer_t pwd_in = SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); + SE_DataTransfer_t r_in = SE_DATATRANSFER_DEFAULT(ctx->r, 32); + SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + SE_DataTransfer_t Xp_in = SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); + SE_DataTransfer_t key_out = SE_DATATRANSFER_DEFAULT(buf, 32); + + SE_addDataInput(se_cmd, &domain_in); + SE_addDataInput(se_cmd, &pwd_in); + SE_addDataInput(se_cmd, &r_in); + SE_addDataInput(se_cmd, &Xp2_in); + SE_addDataInput(se_cmd, &Xp_in); + + SE_addDataOutput(se_cmd, &key_out); + + SE_addParameter(se_cmd, ctx->curve_flags); + SE_addParameter(se_cmd, ctx->pwd_len); + SE_addParameter(se_cmd, gen_key_flags); + + sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + *olen = 32; + } else { + *olen = 0; + } + return ret; +} + +/***************************************************************************//** + * This clears an ECJPAKE context. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_free(sl_se_ecjpake_context_t *ctx) +{ + if (ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + memset(ctx, 0, sizeof(*ctx)); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Initialize an ECJPAKE context. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_init(sl_se_ecjpake_context_t *ctx, + sl_se_command_context_t *cmd_ctx) +{ + if (ctx == NULL || cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + memset(ctx, 0, sizeof(*ctx)); + + // store pointer to command context object + ctx->cmd_ctx = cmd_ctx; + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Read and process the first round message. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_read_round_one(sl_se_ecjpake_context_t *ctx, + const unsigned char *buf, + size_t len) +{ + sl_status_t ret = SL_STATUS_OK; + + if (ctx == NULL || buf == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; + SE_Command_t *se_cmd = &ctx->cmd_ctx->command; + + // We should receive 2 binary points and 2 ZKP's. + + // Local storage for ZKP's. + uint8_t zkp1[32 + 64] = { 0 }; + uint8_t zkp2[32 + 64] = { 0 }; + + uint8_t *obuf = ctx->Xp1; + size_t olen = 64; + + // Parse structures. + ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + obuf = zkp1; + olen = 96; + ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + obuf = ctx->Xp2; + olen = 64; + ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + obuf = zkp2; + olen = 96; + ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + if (len > 0) { + // Too much input. + return SL_STATUS_WOULD_OVERFLOW; + } + + // SE command structures. + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R1_VERIFY); + SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); + SE_DataTransfer_t userid_mine = SE_DATATRANSFER_DEFAULT( + (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + SE_DataTransfer_t userid_peer = SE_DATATRANSFER_DEFAULT( + (void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); + SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + SE_DataTransfer_t zkp1_in = SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); + SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + SE_DataTransfer_t zkp2_in = SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); + + SE_addDataInput(se_cmd, &domain_in); + SE_addDataInput(se_cmd, &userid_mine); + SE_addDataInput(se_cmd, &userid_peer); + SE_addDataInput(se_cmd, &Xp1_in); + SE_addDataInput(se_cmd, &zkp1_in); + SE_addDataInput(se_cmd, &Xp2_in); + SE_addDataInput(se_cmd, &zkp2_in); + + SE_addParameter(se_cmd, ctx->curve_flags); + SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); + SE_addParameter(se_cmd, strlen(ecjpake_id[1 - ctx->role])); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read and process the second round message. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_read_round_two(sl_se_ecjpake_context_t *ctx, + const unsigned char *buf, + size_t len) +{ + if (ctx == NULL || buf == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; + SE_Command_t *se_cmd = &ctx->cmd_ctx->command; + sl_status_t ret = SL_STATUS_OK; + + // Local storage for ZKP. + uint8_t zkpB[32 + 64]; + + if (ctx->role == SL_SE_ECJPAKE_CLIENT) { + uint16_t tls_id; + + if (len < 3) { + return SL_STATUS_INVALID_PARAMETER; + } + + // First byte is curve_type; only named_curve is handled. + if (*(buf++) != SL_SE_ECP_TLS_NAMED_CURVE) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Next two bytes are the namedcurve value. + tls_id = *(buf++); + tls_id <<= 8; + tls_id |= *(buf++); + + // We support only one curve. + if (tls_id != SL_SE_TLSID_ECC_P256) { + return SL_STATUS_NOT_SUPPORTED; + } + + len -= 3; + } + + // We should receive 1 binary point and 1 ZKP. + uint8_t *obuf = ctx->Xp; + size_t olen = 64; + + // Parse structures. + ret = ecjpake_parse_tls_point(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + obuf = zkpB; + olen = sizeof(zkpB); + ret = ecjpake_parse_tls_zkp(&buf, &len, NULL, &obuf, &olen); + if (ret != SL_STATUS_OK) { + return ret; + } + + if (len > 0) { + // Too much input. + return SL_STATUS_WOULD_OVERFLOW; + } + + // SE command structures. + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R2_VERIFY); + SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); + SE_DataTransfer_t userid_peer = SE_DATATRANSFER_DEFAULT( + (void*)ecjpake_id[1 - ctx->role], strlen(ecjpake_id[1 - ctx->role])); + SE_DataTransfer_t Xm1_in = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + SE_DataTransfer_t Xm2_in = SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); + SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + SE_DataTransfer_t Xp_in = SE_DATATRANSFER_DEFAULT(ctx->Xp, 64); + SE_DataTransfer_t zkpB_in = SE_DATATRANSFER_DEFAULT(zkpB, sizeof(zkpB)); + + SE_addDataInput(se_cmd, &domain_in); + SE_addDataInput(se_cmd, &userid_peer); + SE_addDataInput(se_cmd, &Xm1_in); + SE_addDataInput(se_cmd, &Xm2_in); + SE_addDataInput(se_cmd, &Xp1_in); + SE_addDataInput(se_cmd, &Xp_in); + SE_addDataInput(se_cmd, &zkpB_in); + + SE_addParameter(se_cmd, ctx->curve_flags); + SE_addParameter(se_cmd, strlen(ecjpake_id[1 - ctx->role])); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Set up an ECJPAKE context for use. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_setup(sl_se_ecjpake_context_t *ctx, + sl_se_ecjpake_role_t role, + sl_se_hash_type_t hash, + uint32_t curve, + const unsigned char *secret, + size_t len) +{ + if (ctx == NULL || (len > 0 && secret == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE only supports passphrases of maximum 32 bytes. + if (len > sizeof(ctx->pwd)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE currently only supports SHA256 as JPAKE hashing mechanism. + if (hash != SL_SE_HASH_SHA256) { + return SL_STATUS_NOT_SUPPORTED; + } + + // SE currently only supports ECDSA secp256r1 as curve. + if (curve != SL_SE_KEY_TYPE_ECC_P256) { + return SL_STATUS_NOT_SUPPORTED; + } + + ctx->curve_flags = 0x8000001FUL; + ctx->role = role; + ctx->pwd_len = len; + memcpy(ctx->pwd, secret, len); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Generate and write the first round message. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_write_round_one(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen) +{ + sl_status_t ret = SL_STATUS_OK; + + if (ctx == NULL || buf == NULL || olen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; + SE_Command_t *se_cmd = &ctx->cmd_ctx->command; + *olen = 0; + + // Local storage for ZKP's. + uint8_t zkp1[32 + 64]; + uint8_t zkp2[32 + 64]; + + // SE command structures. + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R1_GENERATE); + SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); + SE_DataTransfer_t userid = SE_DATATRANSFER_DEFAULT( + (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + SE_DataTransfer_t r_out = SE_DATATRANSFER_DEFAULT(ctx->r, 32); + SE_DataTransfer_t Xm1_out = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + SE_DataTransfer_t zkp1_out = SE_DATATRANSFER_DEFAULT(zkp1, sizeof(zkp1)); + SE_DataTransfer_t Xm2_out = SE_DATATRANSFER_DEFAULT(ctx->Xm2, 64); + SE_DataTransfer_t zkp2_out = SE_DATATRANSFER_DEFAULT(zkp2, sizeof(zkp2)); + + SE_addDataInput(se_cmd, &domain_in); + SE_addDataInput(se_cmd, &userid); + + SE_addDataOutput(se_cmd, &r_out); + SE_addDataOutput(se_cmd, &Xm1_out); + SE_addDataOutput(se_cmd, &zkp1_out); + SE_addDataOutput(se_cmd, &Xm2_out); + SE_addDataOutput(se_cmd, &zkp2_out); + + SE_addParameter(se_cmd, ctx->curve_flags); + SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); + + ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + // To write TLS structures of ECJ-PAKE, we need to write: + // Xm1, zkp1, Xm2 and zkp2. + uint8_t *obuf = buf; + const uint8_t *ibuf = ctx->Xm1; + size_t ilen = 64; + + ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != SL_STATUS_OK) { + return ret; + } + + ibuf = zkp1; + ilen = 96; + ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != SL_STATUS_OK) { + return ret; + } + + ibuf = ctx->Xm2; + ilen = 64; + ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != SL_STATUS_OK) { + return ret; + } + + ibuf = zkp2; + ilen = 96; + ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + } + return ret; +} + +/***************************************************************************//** + * Generate and write the second round message. + ******************************************************************************/ +sl_status_t sl_se_ecjpake_write_round_two(sl_se_ecjpake_context_t *ctx, + unsigned char *buf, + size_t len, + size_t *olen) +{ + sl_status_t ret = SL_STATUS_OK; + + if (ctx == NULL || buf == NULL || olen == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + sl_se_command_context_t *cmd_ctx = ctx->cmd_ctx; + SE_Command_t *se_cmd = &ctx->cmd_ctx->command; + + *olen = 0; + + uint8_t zkpA[32 + 64]; + uint8_t xA[64]; + + // SE command structures. + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_JPAKE_R2_GENERATE); + SE_DataTransfer_t domain_in = SE_DATATRANSFER_DEFAULT(NULL, 0); + SE_DataTransfer_t pwd_in = SE_DATATRANSFER_DEFAULT(ctx->pwd, ctx->pwd_len); + SE_DataTransfer_t userid = SE_DATATRANSFER_DEFAULT( + (void*)ecjpake_id[ctx->role], strlen(ecjpake_id[ctx->role])); + SE_DataTransfer_t r_in = SE_DATATRANSFER_DEFAULT(ctx->r, 32); + SE_DataTransfer_t Xm1_in = SE_DATATRANSFER_DEFAULT(ctx->Xm1, 64); + SE_DataTransfer_t Xp1_in = SE_DATATRANSFER_DEFAULT(ctx->Xp1, 64); + SE_DataTransfer_t Xp2_in = SE_DATATRANSFER_DEFAULT(ctx->Xp2, 64); + SE_DataTransfer_t xA_out = SE_DATATRANSFER_DEFAULT(xA, sizeof(xA)); + SE_DataTransfer_t zkpA_out = SE_DATATRANSFER_DEFAULT(zkpA, sizeof(zkpA)); + + SE_addDataInput(se_cmd, &domain_in); + SE_addDataInput(se_cmd, &pwd_in); + SE_addDataInput(se_cmd, &userid); + SE_addDataInput(se_cmd, &r_in); + SE_addDataInput(se_cmd, &Xm1_in); + SE_addDataInput(se_cmd, &Xp1_in); + SE_addDataInput(se_cmd, &Xp2_in); + + SE_addDataOutput(se_cmd, &xA_out); + SE_addDataOutput(se_cmd, &zkpA_out); + + SE_addParameter(se_cmd, ctx->curve_flags); + SE_addParameter(se_cmd, ctx->pwd_len); + SE_addParameter(se_cmd, strlen(ecjpake_id[ctx->role])); + + ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SLI_SE_RESPONSE_OK) { + // If we are the server, we need to write out the ECParams. + if (ctx->role == SL_SE_ECJPAKE_SERVER) { + if (len < 3 + 66 + 66 + 33) { + return SL_STATUS_WOULD_OVERFLOW; + } + // First byte is curve_type, always named_curve. + *(buf++) = SL_SE_ECP_TLS_NAMED_CURVE; + + // Next two bytes are the namedcurve value, we only support one. + *(buf++) = SL_SE_TLSID_ECC_P256 >> 8; + *(buf++) = SL_SE_TLSID_ECC_P256 & 0xFF; + + *olen += 3; + len -= 3; + } + + // To write TLS structures of ECJ-PAKE, we need to write: + // xA in uncompressed form and zkpA in uncompressed form + uint8_t *obuf = buf; + const uint8_t *ibuf = xA; + size_t ilen = 64; + + ret = ecjpake_write_tls_point(&obuf, &len, olen, &ibuf, &ilen, 64); + if (ret != SL_STATUS_OK) { + return ret; + } + + ibuf = zkpA; + ilen = 96; + ret = ecjpake_write_tls_zkp(&obuf, &len, olen, &ibuf, &ilen, 64); + } + + return ret; +} + +// ------------------------------- +// Key derivation functions + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +/***************************************************************************//** + * HKDF key derivation. + ******************************************************************************/ +sl_status_t sl_se_derive_key_hkdf(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *in_key, + sl_se_hash_type_t hash, + const unsigned char *salt, + size_t salt_len, + const unsigned char *info, + size_t info_len, + sl_se_key_descriptor_t *out_key) +{ + uint32_t hash_mask; + sl_status_t status = SL_STATUS_OK; + + if ((cmd_ctx == NULL) || (in_key == NULL) || (out_key == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((salt == NULL) && (salt_len != 0U)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((info == NULL) && (info_len != 0U)) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (hash) { + case SL_SE_HASH_SHA1: + hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA1; + break; + + case SL_SE_HASH_SHA224: + hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA224; + break; + + case SL_SE_HASH_SHA256: + hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA256; + break; + + case SL_SE_HASH_SHA384: + hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA384; + break; + + case SL_SE_HASH_SHA512: + hash_mask = SLI_SE_COMMAND_OPTION_HASH_SHA512; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + + // SE command structures. + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DERIVE_KEY_HKDF | hash_mask); + + sli_add_key_parameters(cmd_ctx, in_key, status); + SE_addParameter(se_cmd, salt_len); + SE_addParameter(se_cmd, info_len); + sli_add_key_parameters(cmd_ctx, out_key, status); + + sli_add_key_metadata(cmd_ctx, in_key, status); + sli_add_key_input(cmd_ctx, in_key, status); + + sli_add_key_metadata_custom(cmd_ctx, auth_data, out_key, status); + + SE_DataTransfer_t salt_in = SE_DATATRANSFER_DEFAULT(salt, salt_len); + SE_addDataInput(se_cmd, &salt_in); + + SE_DataTransfer_t info_in = SE_DATATRANSFER_DEFAULT(info, info_len); + SE_addDataInput(se_cmd, &info_in); + + sli_add_key_output(cmd_ctx, out_key, status); + + status = sli_se_execute_and_wait(cmd_ctx); + + return status; +} +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + +#if (defined(_SILICON_LABS_SECURITY_FEATURE) \ + && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT)) +/***************************************************************************//** + * PBKDF2 key derivation. + ******************************************************************************/ +sl_status_t sl_se_derive_key_pbkdf2(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *in_key, + sl_se_pbkdf2_prf_type_t prf, + const unsigned char *salt, + size_t salt_len, + uint32_t iterations, + sl_se_key_descriptor_t *out_key) +{ + sl_status_t status = SL_STATUS_OK; + uint32_t command_word = 0U; + + if ((cmd_ctx == NULL) || (in_key == NULL) || (out_key == NULL)) { + return SL_STATUS_INVALID_PARAMETER; + } + if ((salt == NULL) && (salt_len != 0U)) { + return SL_STATUS_INVALID_PARAMETER; + } + // Too many iterations will trigger SE watchdog. + if ((iterations == 0U) || (iterations > 16384U)) { + return SL_STATUS_INVALID_PARAMETER; + } + + switch (prf) { + case SL_SE_PRF_HMAC_SHA1: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC + | SLI_SE_COMMAND_OPTION_HASH_SHA1; + break; + + case SL_SE_PRF_HMAC_SHA224: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC + | SLI_SE_COMMAND_OPTION_HASH_SHA224; + break; + + case SL_SE_PRF_HMAC_SHA256: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC + | SLI_SE_COMMAND_OPTION_HASH_SHA256; + break; + + case SL_SE_PRF_HMAC_SHA384: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC + | SLI_SE_COMMAND_OPTION_HASH_SHA384; + break; + + case SL_SE_PRF_HMAC_SHA512: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_HMAC + | SLI_SE_COMMAND_OPTION_HASH_SHA512; + break; + +#if defined(SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC_AVAILABLE) + // PBKDF2 with CMAC as the PRF was first supported on EFR32xG23. + case SL_SE_PRF_AES_CMAC_128: + command_word = SLI_SE_COMMAND_DERIVE_KEY_PBKDF2_CMAC; + break; +#endif + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + + // SE command structures. + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, command_word); + + sli_add_key_parameters(cmd_ctx, in_key, status); + SE_addParameter(se_cmd, salt_len); + SE_addParameter(se_cmd, iterations); + sli_add_key_parameters(cmd_ctx, out_key, status); + + sli_add_key_metadata(cmd_ctx, in_key, status); + sli_add_key_input(cmd_ctx, in_key, status); + + sli_add_key_metadata_custom(cmd_ctx, auth_data, out_key, status); + + SE_DataTransfer_t salt_in = SE_DATATRANSFER_DEFAULT(salt, salt_len); + SE_addDataInput(se_cmd, &salt_in); + + sli_add_key_output(cmd_ctx, out_key, status); + + status = sli_se_execute_and_wait(cmd_ctx); + + return status; +} +#endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c index 8634934..58245f0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c @@ -1,1192 +1,1192 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager key handling. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "sl_se_manager_key_handling.h" - -/***************************************************************************//** - * \addtogroup sl_se_key SE key handling API - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Defines - -#define KEYSPEC_TYPE_MASK 0xf0000000 -#define KEYSPEC_TYPE_OFFSET 28 -#define KEYSPEC_TYPE_RAW (uint32_t)(0x0UL << KEYSPEC_TYPE_OFFSET) - -#define KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME (uint32_t)(0x8UL << KEYSPEC_TYPE_OFFSET) - -#define KEYSPEC_MODE_MASK 0x0c000000 -#define KEYSPEC_MODE_OFFSET 26 -#define KEYSPEC_MODE_UNPROTECTED (0UL << KEYSPEC_MODE_OFFSET) -#define KEYSPEC_MODE_VOLATILE (1UL << KEYSPEC_MODE_OFFSET) - -#define KEYSPEC_RESTRICTION_MASK 0x03000000U -#define KEYSPEC_RESTRICTION_OFFSET 24U - -#define KEYSPEC_RESTRICTION_UNLOCKED (0U << KEYSPEC_RESTRICTION_OFFSET) - -#define KEYSPEC_INDEX_MASK 0x00ff0000U -#define KEYSPEC_INDEX_OFFSET 16U - -#define KEYSPEC_TRANSFER_MODE_MASK 0x00000300U -#define KEYSPEC_TRANSFER_MODE_OFFSET 8U -#define KEYSPEC_TRANSFER_INDEX_MASK 0x000000ffU -#define KEYSPEC_TRANSFER_INDEX_OFFSET 0U -#define KEYSPEC_TRANSFER_PROT_BIT_MASK 0xffe00000U -#define KEYSPEC_TRANSFER_PROT_BIT_OFFSET 21U - -#define KEYSPEC_NOPROT_MASK 0x00008000U -#define KEYSPEC_NOPROT_OFFSET 15U - -#define KEYSPEC_ATTRIBUTES_MASK 0x00007fffU -#define KEYSPEC_ATTRIBUTES_OFFSET 0U - -#define KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK (1U << 14) -#define KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK (1U << 13) -#define KEYSPEC_ATTRIBUTES_ECC_DOMAIN (1U << 12) -#define KEYSPEC_ATTRIBUTES_ECC_SIGN (1U << 10) -#define KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK 0x0000007fU - -#define KEYSPEC_TYPE_ECC_EDWARDS ((uint32_t)(0xaUL << KEYSPEC_TYPE_OFFSET)) -#define KEYSPEC_TYPE_ECC_MONTGOMERY ((uint32_t)(0xbUL << KEYSPEC_TYPE_OFFSET)) -#define KEYSPEC_TYPE_ECC_EDDSA ((uint32_t)(0xcUL << KEYSPEC_TYPE_OFFSET)) - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - - #define KEYSPEC_MODE_WRAPPED \ - (2UL << KEYSPEC_MODE_OFFSET) - - #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_ZERO \ - (1U << 9) - #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_MINUS_THREE \ - (1U << 8) - -#endif - -#define KEYSPEC_RESTRICTION_LOCKED (1UL << KEYSPEC_RESTRICTION_OFFSET) -#define KEYSPEC_RESTRICTION_INTERNAL (2UL << KEYSPEC_RESTRICTION_OFFSET) -#define KEYSPEC_RESTRICTION_RESTRICTED (3UL << KEYSPEC_RESTRICTION_OFFSET) - -// ----------------------------------------------------------------------------- -// Local Functions - -sl_status_t sli_key_get_storage_size(const sl_se_key_descriptor_t* key, - uint32_t *storage_size) -{ - if (key == NULL || storage_size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t key_size = 0; - sl_status_t status = sli_key_get_size(key, &key_size); - if (status != SL_STATUS_OK) { - return status; - } - - uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); - - #if defined(SLI_SE_KEY_PADDING_REQUIRED) - // Round up to word length - key_size = (key_size + 3U) & ~0x03U; - #endif - - if (key_type == KEYSPEC_TYPE_RAW) { - *storage_size = key_size; - return SL_STATUS_OK; - } - - bool has_private_key = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) != 0); - bool has_public_key = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) != 0); - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - bool has_custom_curve = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); - #else - bool has_custom_curve = false; - #endif - - if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME)) { - *storage_size = key_size * (1 * has_private_key + 2 * has_public_key + 6 * has_custom_curve); - } else if (key_type == KEYSPEC_TYPE_ECC_EDWARDS) { - *storage_size = key_size * (has_private_key + has_public_key + 5 * has_custom_curve); - } else if ((key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) - || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { - *storage_size = key_size * (has_private_key + has_public_key); - } else { - return SL_STATUS_INVALID_PARAMETER; - } - - return SL_STATUS_OK; -} - -#if defined(SLI_SE_KEY_PADDING_REQUIRED) -/***************************************************************************//** - * @brief - * Clear the additional bytes of a key that is not word-aligned. - * Does nothing for aligned or asymmetric keys, or non-plaintext keys. - * - * @param key - * Key descriptor for the key. - * - * @returns - * Status code, @ref sl_status.h. - ******************************************************************************/ -static sl_status_t clear_padding(const sl_se_key_descriptor_t *key) -{ - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT - && (key->type & KEYSPEC_TYPE_MASK) == KEYSPEC_TYPE_RAW) { - uint32_t key_size = 0; - if (sli_key_get_size(key, &key_size) != SL_STATUS_OK) { - return SL_STATUS_INVALID_PARAMETER; - } - if (key_size & 0x03) { - if (key_size > key->storage.location.buffer.size) { - return SL_STATUS_WOULD_OVERFLOW; - } - uint8_t *padding_ptr = key->storage.location.buffer.pointer + key_size; - uint32_t padding_size = (key->storage.location.buffer.size - key_size) & 0x3; - memset(padding_ptr, 0, padding_size); - } - } - return SL_STATUS_OK; -} -#endif - -// ----------------------------------------------------------------------------- -// Global Functions - -sl_status_t sli_key_get_size(const sl_se_key_descriptor_t *key, uint32_t *size) -{ - if (key == NULL || size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Find size from key_type - uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); - if (key_type == KEYSPEC_TYPE_RAW) { - *size = (key->type & KEYSPEC_ATTRIBUTES_MASK); - } else if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) - || (key_type == KEYSPEC_TYPE_ECC_EDWARDS) - || (key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) - || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - bool has_custom_curve = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); -#endif - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (has_custom_curve) { - if (key->domain == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (key->type & SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { - sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key->domain; - *size = domain->size; - } else { - return SL_STATUS_NOT_SUPPORTED; - } - } else -#endif - { - *size = (key->type & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK); - } - } else { - return SL_STATUS_INVALID_PARAMETER; - } - -// If the key type didn't contain a size, use the one in the dedicated size -// field - if (*size == 0) { - if (key->size == 0) { - return SL_STATUS_INVALID_PARAMETER; - } - *size = key->size; - } - - return SL_STATUS_OK; -} - -sl_status_t sli_key_check_equivalent(const sl_se_key_descriptor_t *key_1, - const sl_se_key_descriptor_t *key_2, - bool check_key_flag, - bool public_export) -{ - sl_status_t status; - - if (key_1 == NULL || key_2 == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (key_1->type != key_2->type) { - // The type fields are different, but this may be due to one of the keys - // not containing the size in the type, but rather in the size field. - if (((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - == SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) - || ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - == SL_SE_KEY_TYPE_ECC_EDDSA)) { - if ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - == (key_2->type & SL_SE_KEY_TYPE_ALGORITHM_MASK)) { - // Assume that the sizes are equal for now (this will be checked later) - uint32_t key_size = 0; - if (sli_key_get_size(key_1, &key_size) == SL_STATUS_OK) { - // Add the key sizes to both key types, and check for equality then - sl_se_key_type_t type_1 = key_1->type | (SL_SE_KEY_TYPE_ATTRIBUTES_MASK & key_size); - sl_se_key_type_t type_2 = key_2->type | (SL_SE_KEY_TYPE_ATTRIBUTES_MASK & key_size); - if (type_1 != type_2) { - return SL_STATUS_INVALID_PARAMETER; - } - } else { - return SL_STATUS_INVALID_PARAMETER; - } - } - } else { - return SL_STATUS_INVALID_PARAMETER; - } - } - - // Verify asymmetry flags - if ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { - uint32_t consistent_flags = - (public_export) ? SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN - : (SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY - | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY - | SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN); - if (check_key_flag && (key_1->flags & consistent_flags) ^ (key_2->flags & consistent_flags)) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (public_export - && (!(key_2->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY))) { - return SL_STATUS_INVALID_PARAMETER; - } - } - - // Verify key sizes - uint32_t key_1_size = 0; - status = sli_key_get_size(key_1, &key_1_size); - if (status != SL_STATUS_OK) { - return status; - } - uint32_t key_2_size = 0; - status = sli_key_get_size(key_2, &key_2_size); - if (status != SL_STATUS_OK) { - return status; - } - - if (key_1_size != key_2_size) { - return SL_STATUS_INVALID_PARAMETER; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * @brief - * Convert key descriptor struct to a 32-bit keyspec value to pass into an SE - * command. - * - * @return - * Status code, @ref sl_status.h. - ******************************************************************************/ -sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t *key, - uint32_t *keyspec) -{ - if (key == NULL || keyspec == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Clear output - *keyspec = 0; - - // --------------------- - // Key type [31-28] - - *keyspec = (key->type & KEYSPEC_TYPE_MASK); - - // --------------------- - // Key mode [27-26] - - switch (key->storage.method) { - case SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT: - *keyspec |= KEYSPEC_MODE_UNPROTECTED; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED: - *keyspec |= KEYSPEC_MODE_WRAPPED; - break; - - case SL_SE_KEY_STORAGE_INTERNAL_VOLATILE: - *keyspec |= KEYSPEC_MODE_VOLATILE; - break; -#endif - - case SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE: - *keyspec |= KEYSPEC_MODE_VOLATILE; - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - } - - // --------------------- - // Key restriction [25-24] - - uint32_t keyspec_restriction = 0; - if (key->flags & SL_SE_KEY_FLAG_NON_EXPORTABLE) { - keyspec_restriction = KEYSPEC_RESTRICTION_LOCKED; - } - if (key->flags & SL_SE_KEY_FLAG_IS_DEVICE_GENERATED) { - keyspec_restriction = KEYSPEC_RESTRICTION_INTERNAL; - } - if ((key->flags & SL_SE_KEY_FLAG_IS_RESTRICTED) == SL_SE_KEY_FLAG_IS_RESTRICTED) { - keyspec_restriction = KEYSPEC_RESTRICTION_RESTRICTED; - } - // Key restrictions are only applicable to volatile and wrapped keys - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { - if (keyspec_restriction != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - } - - *keyspec = (*keyspec & ~KEYSPEC_RESTRICTION_MASK) - | (keyspec_restriction & KEYSPEC_RESTRICTION_MASK); - - // --------------------- - // Key index [23-16] - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { - if (key->storage.location.slot > SL_SE_KEY_SLOT_VOLATILE_3) { - return SL_STATUS_INVALID_PARAMETER; - } - *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) - | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) - & KEYSPEC_INDEX_MASK); - } -#endif - - if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { - if (key->storage.location.slot - < SL_SE_KEY_SLOT_INTERNAL_MIN) { - return SL_STATUS_INVALID_PARAMETER; - } - *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) - | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) - & KEYSPEC_INDEX_MASK); - } - - // --------------------- - // Key NoProt [15] - - if (key->flags & SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS) { - *keyspec = (*keyspec & ~KEYSPEC_NOPROT_MASK) | (1 << KEYSPEC_NOPROT_OFFSET); - } - - // --------------------- - // Key attributes [14-0] - - // Set general properties from key->type - if (key->storage.method != SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { - *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_MASK) - | (key->type & KEYSPEC_ATTRIBUTES_MASK); - } - - // Set public/private flags - bool has_private_key = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) != 0); - bool has_public_key = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) != 0); -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - bool has_custom_curve = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); -#endif - bool signing_only = - ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY) != 0); - - if ((key->type & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { - if (has_private_key) { - *keyspec |= KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK; - } - if (has_public_key) { - *keyspec |= KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK; - } - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (has_custom_curve) { - *keyspec |= KEYSPEC_ATTRIBUTES_ECC_DOMAIN; - } - #endif - if (!(has_private_key || has_public_key)) { - return SL_STATUS_INVALID_PARAMETER; - } - } - - if ((key->type & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME - && (key->type & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_EDDSA) { - if (signing_only) { - *keyspec |= KEYSPEC_ATTRIBUTES_ECC_SIGN; - } - } - - // Ensure that symmetric keys don't have asymmetric flags - if ((key->type & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { - if (has_private_key || has_public_key || signing_only) { - return SL_STATUS_INVALID_PARAMETER; - } - } - - // Set or adjust the key attributes for different key types - uint32_t size = 0; - sl_status_t status; - status = sli_key_get_size(key, &size); - if (status != SL_STATUS_OK) { - return status; - } - - // Symmetric and raw keys - uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); - if (key_type == KEYSPEC_TYPE_RAW) { - *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_MASK) - | (size & KEYSPEC_ATTRIBUTES_MASK); - } else if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) - || (key_type == KEYSPEC_TYPE_ECC_EDWARDS) - || (key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) - || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { - *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK) - | ((size - 1) & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK); - } else { - return SL_STATUS_INVALID_PARAMETER; - } - - // Custom domain -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (has_custom_curve) { - if (key->domain == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - if (key_type == SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { - sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key->domain; - if (domain->a_is_zero && signing_only) { - *keyspec |= KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_ZERO; - } - if (domain->a_is_minus_three && signing_only) { - *keyspec |= KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_MINUS_THREE; - } - } else { - return SL_STATUS_NOT_SUPPORTED; - } - } -#endif - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * @brief - * Convert a 32-bit SE compatible keyspec value to a key descriptor struct. - ******************************************************************************/ -sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, - sl_se_key_descriptor_t* key) -{ - if (key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Clear output - key->type = 0; - key->storage.method = 0; - key->storage.location.slot = 0; - key->size = 0; - key->flags = 0; - - // --------------------- - // Key type [31-28] - key->type = keyspec & KEYSPEC_TYPE_MASK; - - // --------------------- - // Key mode [27-26] and key index [23-16] - - if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_UNPROTECTED) { - key->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; - } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - else if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_WRAPPED) { - key->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED; - } -#endif - else if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_VOLATILE) { - // Volatile can mean either internal-volatile or internal-immutable - // Check which is which based on key index - uint32_t key_index = (keyspec & KEYSPEC_INDEX_MASK) >> KEYSPEC_INDEX_OFFSET; -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (key_index <= SL_SE_KEY_SLOT_VOLATILE_3) { - key->storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE; - } else -#endif - if ((key_index <= SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY) - && (key_index >= SL_SE_KEY_SLOT_INTERNAL_MIN)) { - key->storage.method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE; - } else { - return SL_STATUS_INVALID_PARAMETER; - } - key->storage.location.slot = key_index; - } else { - return SL_STATUS_INVALID_PARAMETER; - } - - // --------------------- - // Key restriction [25-24] - - uint32_t keyspec_restriction = (keyspec & KEYSPEC_RESTRICTION_MASK); - if (keyspec_restriction == KEYSPEC_RESTRICTION_LOCKED) { - key->flags |= SL_SE_KEY_FLAG_NON_EXPORTABLE; - } else if (keyspec_restriction == KEYSPEC_RESTRICTION_UNLOCKED) { - // no-op - } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - else if (keyspec_restriction == KEYSPEC_RESTRICTION_INTERNAL) { - key->flags |= SL_SE_KEY_FLAG_IS_DEVICE_GENERATED; - } else if (keyspec_restriction == KEYSPEC_RESTRICTION_RESTRICTED) { - key->flags |= SL_SE_KEY_FLAG_IS_RESTRICTED; - } -#endif - else { - return SL_STATUS_INVALID_PARAMETER; - } - - // Key restrictions are only applicable to volatile and wrapped keys - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { - if (keyspec_restriction != 0) { - return SL_STATUS_INVALID_PARAMETER; - } - } - - // --------------------- - // Key NoProt [15] - - if ((keyspec & KEYSPEC_NOPROT_MASK) == (1 << KEYSPEC_NOPROT_OFFSET)) { - key->flags |= SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS; - } - - // --------------------- - // Key attributes [14-0] - - // Set public/private flags - bool has_private_key = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK) != 0); - bool has_public_key = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK) != 0); -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - bool has_custom_curve = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_DOMAIN) != 0); -#endif - bool signing_only = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_SIGN) != 0); - - if ((keyspec & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { - if (has_private_key) { - key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; - } - if (has_public_key) { - key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; - } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (has_custom_curve) { - key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN; - - // TODO: custom curve parameter injection? - return SL_STATUS_NOT_SUPPORTED; - } -#endif - if (!(has_private_key || has_public_key)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // For ECC keys, their length is encoded in the type - key->type = (key->type & ~SL_SE_KEY_TYPE_ATTRIBUTES_MASK) | ((keyspec & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK) + 1); - } - - if ((keyspec & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME - && (keyspec & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_EDDSA) { - if (signing_only) { - key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY; - } - } - - // Ensure that symmetric keys don't have asymmetric flags - if ((keyspec & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { - if (has_private_key || has_public_key || signing_only) { - return SL_STATUS_INVALID_PARAMETER; - } - - key->size = keyspec & KEYSPEC_ATTRIBUTES_MASK; - - switch ((keyspec & KEYSPEC_ATTRIBUTES_MASK)) { - case SL_SE_KEY_TYPE_AES_128: - case SL_SE_KEY_TYPE_AES_192: - case SL_SE_KEY_TYPE_AES_256: - key->type = keyspec & (KEYSPEC_TYPE_MASK | KEYSPEC_ATTRIBUTES_MASK); - break; - default: - break; - } - } - - return SL_STATUS_OK; -} - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -static const uint32_t default_auth_data[2] = { 0 }; -#endif - -sl_status_t sli_se_get_auth_buffer(const sl_se_key_descriptor_t *key, - SE_DataTransfer_t *auth_buffer) -{ - if (key == NULL || auth_buffer == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - auth_buffer->next = (void*)SE_DATATRANSFER_STOP; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) - || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED)) { - if (key->password) { - auth_buffer->data = key->password; - auth_buffer->length = sizeof(default_auth_data) | SE_DATATRANSFER_REALIGN; - } else { - auth_buffer->data = (void*)default_auth_data; - auth_buffer->length = sizeof(default_auth_data) | SE_DATATRANSFER_REALIGN; - } - } else { - auth_buffer->length = 0 | SE_DATATRANSFER_REALIGN; - } -#else - (void)key; - auth_buffer->length = 0 | SE_DATATRANSFER_REALIGN; -#endif - - return SL_STATUS_OK; -} - -sl_status_t sli_se_get_key_input_output(const sl_se_key_descriptor_t *key, - SE_DataTransfer_t *buffer) -{ - if (key == NULL || buffer == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - buffer->next = (void*)SE_DATATRANSFER_STOP; - - if ((key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) -#endif - ) { - // Set or adjust the key attributes for different key types - uint32_t storage_size = 0; - sl_status_t status = sli_key_get_storage_size(key, &storage_size); - if (status != SL_STATUS_OK) { - return status; - } - - uint32_t total_storage_size = 0; - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { - total_storage_size = storage_size; - } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - else if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) { - total_storage_size = storage_size + SLI_SE_WRAPPED_KEY_OVERHEAD; - } -#endif - - if (total_storage_size > key->storage.location.buffer.size) { - return SL_STATUS_WOULD_OVERFLOW; - } - - buffer->data = key->storage.location.buffer.pointer; - buffer->length = total_storage_size | SE_DATATRANSFER_REALIGN; - } else if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) -#endif - ) { - buffer->length = 0; - } else { - return SL_STATUS_INVALID_PARAMETER; - } - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Validate key descriptor. - ******************************************************************************/ -sl_status_t sl_se_validate_key(const sl_se_key_descriptor_t *key) -{ - sl_status_t status = SL_STATUS_OK; - uint32_t keyspec = 0; - - if (key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - status = sli_se_key_to_keyspec(key, &keyspec); - if (status != SL_STATUS_OK) { - return status; - } - - SE_DataTransfer_t auth_buffer; - status = sli_se_get_auth_buffer(key, &auth_buffer); - if (status != SL_STATUS_OK) { - return status; - } - - SE_DataTransfer_t key_buffer; - status = sli_se_get_key_input_output(key, &key_buffer); - if (status != SL_STATUS_OK) { - return status; - } - - return status; -} - -/***************************************************************************//** - * Generate a random key adhering to the given key descriptor - ******************************************************************************/ -sl_status_t sl_se_generate_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_out) -{ - sl_status_t status; - - if (cmd_ctx == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CREATE_KEY); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key_out, status); - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - SE_Command_t *se_cmd = &cmd_ctx->command; - // Custom curve domain - SE_DataTransfer_t domain_p_buffer; - SE_DataTransfer_t domain_N_buffer; - SE_DataTransfer_t domain_Gx_buffer; - SE_DataTransfer_t domain_Gy_buffer; - SE_DataTransfer_t domain_a_buffer; - SE_DataTransfer_t domain_b_buffer; - - if (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) { - if (key_out->type & SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { - sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key_out->domain; - uint32_t domain_size = domain->size; - - domain_p_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_p_buffer.data = (void*)domain->p; - domain_p_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_p_buffer); - - domain_N_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_N_buffer.data = (void*)domain->N; - domain_N_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_N_buffer); - - domain_Gx_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_Gx_buffer.data = (void*)domain->Gx; - domain_Gx_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_Gx_buffer); - - domain_Gy_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_Gy_buffer.data = (void*)domain->Gy; - domain_Gy_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_Gy_buffer); - - domain_a_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_a_buffer.data = (void*)domain->a; - domain_a_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_a_buffer); - - domain_b_buffer.next = (void*)SE_DATATRANSFER_STOP; - domain_b_buffer.data = (void*)domain->b; - domain_b_buffer.length = domain_size; - SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_b_buffer); - } else { - return SL_STATUS_NOT_SUPPORTED; - } - } -#endif - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key_out, status); - // Add key output block to command - sli_add_key_output(cmd_ctx, key_out, status); - - // Execute command - status = sli_se_execute_and_wait(cmd_ctx); - - #if defined(SLI_SE_KEY_PADDING_REQUIRED) - // Clear padding for plaintext keys upon success - if (status == SL_STATUS_OK) { - status = clear_padding(key_out); - } - #endif - - return status; -} - -/***************************************************************************//** - * Export the public key of an ECC keypair - ******************************************************************************/ -sl_status_t sl_se_export_public_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out) -{ - if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - // Check input/output key type and size relationship - status = sli_key_check_equivalent(key_in, key_out, true, true); - if (status != SL_STATUS_OK) { - return status; - } - - // Check that the input key has a private or public key - if (!(key_in->flags & (SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY - | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY))) { - return SL_STATUS_INVALID_PARAMETER; - } - if (!(key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) - || (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READPUB_KEY); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key_in, status); - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key_in, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key_in, status); - - // Pubkey buffer - // Check for correct storage and flags - if ((key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) - || (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) - || !(key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY)) { - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t required_storage_size; - status = sli_key_get_storage_size(key_out, &required_storage_size); - if (status != SL_STATUS_OK) { - return status; - } - - if (required_storage_size > key_out->storage.location.buffer.size) { - return SL_STATUS_WOULD_OVERFLOW; - } - - SE_DataTransfer_t pubkey_buffer = SE_DATATRANSFER_DEFAULT( - key_out->storage.location.buffer.pointer, required_storage_size); - SE_addDataOutput(se_cmd, &pubkey_buffer); - - // Execute command. - // The retries are necessary in order to reduce the risk of random failures - // in the accelerated point multiplication. This mainly affects very small or - // large scalars, which in this case would be the private key. - for (size_t i = 0; i < SLI_SE_MAX_POINT_MULT_RETRIES; ++i) { - status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_FAIL) { - break; - } - } - return status; -} - -/***************************************************************************//** - * Returns the required storage size for the given key - ******************************************************************************/ -sl_status_t sl_se_get_storage_size(const sl_se_key_descriptor_t *key, uint32_t *storage_size) -{ - if (key == NULL || storage_size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if ((key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) -#endif - ) { - // Set or adjust the key attributes for different key types - sl_status_t status = sli_key_get_storage_size(key, storage_size); - if (status != SL_STATUS_OK) { - return status; - } -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) { - *storage_size = *storage_size + SLI_SE_WRAPPED_KEY_OVERHEAD; - } -#endif - } else if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) -#endif - ) { - *storage_size = 0; - } else { - return SL_STATUS_INVALID_PARAMETER; - } - - return SL_STATUS_OK; -} - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * Protect a plaintext key using the SE - ******************************************************************************/ -sl_status_t sl_se_import_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out) -{ - sl_status_t status; - - if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check input/output key type and size relationship - status = sli_key_check_equivalent(key_in, key_out, true, false); - if (status != SL_STATUS_OK) { - return status; - } - - if ((key_in->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) - || ((key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) - && (key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED))) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_WRAP_KEY); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key_out, status); - - // Add key input block to command - sli_add_key_input(cmd_ctx, key_in, status); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key_out, status); - - // Add key output block to command - sli_add_key_output(cmd_ctx, key_out, status); - - status = sli_se_execute_and_wait(cmd_ctx); - return status; -} - -/***************************************************************************//** - * Export a volatile or wrapped key back to plaintext if allowed - ******************************************************************************/ -sl_status_t sl_se_export_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out) -{ - sl_status_t status; - - if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Check input/output key type and size relationship - status = sli_key_check_equivalent(key_in, key_out, true, false); - if (status != SL_STATUS_OK) { - return status; - } - - if ((key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) - || ((key_in->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) - && (key_in->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED))) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_UNWRAP_KEY); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key_in, status); - - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key_in, status); - - // Add key input block to command - sli_add_key_input(cmd_ctx, key_in, status); - - // Add key output block to command - sli_add_key_output(cmd_ctx, key_out, status); - - status = sli_se_execute_and_wait(cmd_ctx); - - #if defined(SLI_SE_KEY_PADDING_REQUIRED) - // The SE will only output word-aligned data. Clear the extra padding before - // returning - if (status == SL_STATUS_OK) { - status = clear_padding(key_out); - } - #endif - - return status; -} - -/***************************************************************************//** - * Transfer a protected (volatile/wrapped) key - ******************************************************************************/ -sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key_in, - const sl_se_key_descriptor_t *key_out) -{ - if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - SE_DataTransfer_t auth_buffer_out; - uint32_t key_update_index; - uint32_t key_update_mode; - - // Check input/output key type and size relationship - status = sli_key_check_equivalent(key_in, key_out, true, false); - if (status != SL_STATUS_OK) { - return status; - } - - if ((key_in->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) - || (key_in->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) - || (key_out->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) - || (key_out->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Create command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRANSFER_KEY); - - // Add key input parameters to command - sli_add_key_parameters(cmd_ctx, key_in, status); - - // Add key update parameters to command - uint32_t keyspec_out; - status = sli_se_key_to_keyspec(key_out, &keyspec_out); - if (status != SL_STATUS_OK) { - return status; - } - key_update_index = ((keyspec_out & KEYSPEC_INDEX_MASK) >> KEYSPEC_INDEX_OFFSET); - key_update_mode = ((keyspec_out & KEYSPEC_MODE_MASK) >> KEYSPEC_MODE_OFFSET); - keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_INDEX_MASK) - | ((key_update_index << KEYSPEC_TRANSFER_INDEX_OFFSET) - & KEYSPEC_TRANSFER_INDEX_MASK); - keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_MODE_MASK) - | ((key_update_mode << KEYSPEC_TRANSFER_MODE_OFFSET) - & KEYSPEC_TRANSFER_MODE_MASK); - keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_PROT_BIT_MASK); - SE_addParameter(se_cmd, keyspec_out); - - // Add key input metadata block to command - sli_add_key_metadata(cmd_ctx, key_in, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key_in, status); - - // Add key output metadata block to command - status = sli_se_get_auth_buffer(key_out, &auth_buffer_out); - if (status != SL_STATUS_OK) { - return status; - } - SE_addDataInput(se_cmd, &auth_buffer_out); - - // Add key output block to command - sli_add_key_output(cmd_ctx, key_out, status); - - status = sli_se_execute_and_wait(cmd_ctx); - - #if defined(SLI_SE_KEY_PADDING_REQUIRED) - // Clear padding bytes for plaintext keys upon success - if (status == SL_STATUS_OK) { - status = clear_padding(key_out); - } - #endif - - return status; -} - -/***************************************************************************//** - * Delete a key a volatile SE storage slot - ******************************************************************************/ -sl_status_t sl_se_delete_key(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key) -{ - sl_status_t status; - - if (cmd_ctx == NULL || key == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Initialize command - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DELETE_KEY); - - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - - // Execute command - status = sli_se_execute_and_wait(cmd_ctx); - return status; -} -#endif - -/** @} (end addtogroup sl_se_key) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager key handling. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "sl_se_manager_key_handling.h" + +/***************************************************************************//** + * \addtogroup sl_se_key SE key handling API + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +#define KEYSPEC_TYPE_MASK 0xf0000000 +#define KEYSPEC_TYPE_OFFSET 28 +#define KEYSPEC_TYPE_RAW (uint32_t)(0x0UL << KEYSPEC_TYPE_OFFSET) + +#define KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME (uint32_t)(0x8UL << KEYSPEC_TYPE_OFFSET) + +#define KEYSPEC_MODE_MASK 0x0c000000 +#define KEYSPEC_MODE_OFFSET 26 +#define KEYSPEC_MODE_UNPROTECTED (0UL << KEYSPEC_MODE_OFFSET) +#define KEYSPEC_MODE_VOLATILE (1UL << KEYSPEC_MODE_OFFSET) + +#define KEYSPEC_RESTRICTION_MASK 0x03000000U +#define KEYSPEC_RESTRICTION_OFFSET 24U + +#define KEYSPEC_RESTRICTION_UNLOCKED (0U << KEYSPEC_RESTRICTION_OFFSET) + +#define KEYSPEC_INDEX_MASK 0x00ff0000U +#define KEYSPEC_INDEX_OFFSET 16U + +#define KEYSPEC_TRANSFER_MODE_MASK 0x00000300U +#define KEYSPEC_TRANSFER_MODE_OFFSET 8U +#define KEYSPEC_TRANSFER_INDEX_MASK 0x000000ffU +#define KEYSPEC_TRANSFER_INDEX_OFFSET 0U +#define KEYSPEC_TRANSFER_PROT_BIT_MASK 0xffe00000U +#define KEYSPEC_TRANSFER_PROT_BIT_OFFSET 21U + +#define KEYSPEC_NOPROT_MASK 0x00008000U +#define KEYSPEC_NOPROT_OFFSET 15U + +#define KEYSPEC_ATTRIBUTES_MASK 0x00007fffU +#define KEYSPEC_ATTRIBUTES_OFFSET 0U + +#define KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK (1U << 14) +#define KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK (1U << 13) +#define KEYSPEC_ATTRIBUTES_ECC_DOMAIN (1U << 12) +#define KEYSPEC_ATTRIBUTES_ECC_SIGN (1U << 10) +#define KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK 0x0000007fU + +#define KEYSPEC_TYPE_ECC_EDWARDS ((uint32_t)(0xaUL << KEYSPEC_TYPE_OFFSET)) +#define KEYSPEC_TYPE_ECC_MONTGOMERY ((uint32_t)(0xbUL << KEYSPEC_TYPE_OFFSET)) +#define KEYSPEC_TYPE_ECC_EDDSA ((uint32_t)(0xcUL << KEYSPEC_TYPE_OFFSET)) + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + + #define KEYSPEC_MODE_WRAPPED \ + (2UL << KEYSPEC_MODE_OFFSET) + + #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_ZERO \ + (1U << 9) + #define KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_MINUS_THREE \ + (1U << 8) + +#endif + +#define KEYSPEC_RESTRICTION_LOCKED (1UL << KEYSPEC_RESTRICTION_OFFSET) +#define KEYSPEC_RESTRICTION_INTERNAL (2UL << KEYSPEC_RESTRICTION_OFFSET) +#define KEYSPEC_RESTRICTION_RESTRICTED (3UL << KEYSPEC_RESTRICTION_OFFSET) + +// ----------------------------------------------------------------------------- +// Local Functions + +sl_status_t sli_key_get_storage_size(const sl_se_key_descriptor_t* key, + uint32_t *storage_size) +{ + if (key == NULL || storage_size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t key_size = 0; + sl_status_t status = sli_key_get_size(key, &key_size); + if (status != SL_STATUS_OK) { + return status; + } + + uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Round up to word length + key_size = (key_size + 3U) & ~0x03U; + #endif + + if (key_type == KEYSPEC_TYPE_RAW) { + *storage_size = key_size; + return SL_STATUS_OK; + } + + bool has_private_key = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) != 0); + bool has_public_key = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) != 0); + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + bool has_custom_curve = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); + #else + bool has_custom_curve = false; + #endif + + if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME)) { + *storage_size = key_size * (1 * has_private_key + 2 * has_public_key + 6 * has_custom_curve); + } else if (key_type == KEYSPEC_TYPE_ECC_EDWARDS) { + *storage_size = key_size * (has_private_key + has_public_key + 5 * has_custom_curve); + } else if ((key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) + || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { + *storage_size = key_size * (has_private_key + has_public_key); + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +#if defined(SLI_SE_KEY_PADDING_REQUIRED) +/***************************************************************************//** + * @brief + * Clear the additional bytes of a key that is not word-aligned. + * Does nothing for aligned or asymmetric keys, or non-plaintext keys. + * + * @param key + * Key descriptor for the key. + * + * @returns + * Status code, @ref sl_status.h. + ******************************************************************************/ +static sl_status_t clear_padding(const sl_se_key_descriptor_t *key) +{ + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT + && (key->type & KEYSPEC_TYPE_MASK) == KEYSPEC_TYPE_RAW) { + uint32_t key_size = 0; + if (sli_key_get_size(key, &key_size) != SL_STATUS_OK) { + return SL_STATUS_INVALID_PARAMETER; + } + if (key_size & 0x03) { + if (key_size > key->storage.location.buffer.size) { + return SL_STATUS_WOULD_OVERFLOW; + } + uint8_t *padding_ptr = key->storage.location.buffer.pointer + key_size; + uint32_t padding_size = (key->storage.location.buffer.size - key_size) & 0x3; + memset(padding_ptr, 0, padding_size); + } + } + return SL_STATUS_OK; +} +#endif + +// ----------------------------------------------------------------------------- +// Global Functions + +sl_status_t sli_key_get_size(const sl_se_key_descriptor_t *key, uint32_t *size) +{ + if (key == NULL || size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Find size from key_type + uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); + if (key_type == KEYSPEC_TYPE_RAW) { + *size = (key->type & KEYSPEC_ATTRIBUTES_MASK); + } else if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) + || (key_type == KEYSPEC_TYPE_ECC_EDWARDS) + || (key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) + || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + bool has_custom_curve = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); +#endif + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (has_custom_curve) { + if (key->domain == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (key->type & SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { + sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key->domain; + *size = domain->size; + } else { + return SL_STATUS_NOT_SUPPORTED; + } + } else +#endif + { + *size = (key->type & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK); + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } + +// If the key type didn't contain a size, use the one in the dedicated size +// field + if (*size == 0) { + if (key->size == 0) { + return SL_STATUS_INVALID_PARAMETER; + } + *size = key->size; + } + + return SL_STATUS_OK; +} + +sl_status_t sli_key_check_equivalent(const sl_se_key_descriptor_t *key_1, + const sl_se_key_descriptor_t *key_2, + bool check_key_flag, + bool public_export) +{ + sl_status_t status; + + if (key_1 == NULL || key_2 == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (key_1->type != key_2->type) { + // The type fields are different, but this may be due to one of the keys + // not containing the size in the type, but rather in the size field. + if (((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + == SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) + || ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + == SL_SE_KEY_TYPE_ECC_EDDSA)) { + if ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + == (key_2->type & SL_SE_KEY_TYPE_ALGORITHM_MASK)) { + // Assume that the sizes are equal for now (this will be checked later) + uint32_t key_size = 0; + if (sli_key_get_size(key_1, &key_size) == SL_STATUS_OK) { + // Add the key sizes to both key types, and check for equality then + sl_se_key_type_t type_1 = key_1->type | (SL_SE_KEY_TYPE_ATTRIBUTES_MASK & key_size); + sl_se_key_type_t type_2 = key_2->type | (SL_SE_KEY_TYPE_ATTRIBUTES_MASK & key_size); + if (type_1 != type_2) { + return SL_STATUS_INVALID_PARAMETER; + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } + } + + // Verify asymmetry flags + if ((key_1->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { + uint32_t consistent_flags = + (public_export) ? SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN + : (SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY + | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY + | SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN); + if (check_key_flag && (key_1->flags & consistent_flags) ^ (key_2->flags & consistent_flags)) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (public_export + && (!(key_2->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY))) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + // Verify key sizes + uint32_t key_1_size = 0; + status = sli_key_get_size(key_1, &key_1_size); + if (status != SL_STATUS_OK) { + return status; + } + uint32_t key_2_size = 0; + status = sli_key_get_size(key_2, &key_2_size); + if (status != SL_STATUS_OK) { + return status; + } + + if (key_1_size != key_2_size) { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief + * Convert key descriptor struct to a 32-bit keyspec value to pass into an SE + * command. + * + * @return + * Status code, @ref sl_status.h. + ******************************************************************************/ +sl_status_t sli_se_key_to_keyspec(const sl_se_key_descriptor_t *key, + uint32_t *keyspec) +{ + if (key == NULL || keyspec == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Clear output + *keyspec = 0; + + // --------------------- + // Key type [31-28] + + *keyspec = (key->type & KEYSPEC_TYPE_MASK); + + // --------------------- + // Key mode [27-26] + + switch (key->storage.method) { + case SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT: + *keyspec |= KEYSPEC_MODE_UNPROTECTED; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED: + *keyspec |= KEYSPEC_MODE_WRAPPED; + break; + + case SL_SE_KEY_STORAGE_INTERNAL_VOLATILE: + *keyspec |= KEYSPEC_MODE_VOLATILE; + break; +#endif + + case SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE: + *keyspec |= KEYSPEC_MODE_VOLATILE; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + } + + // --------------------- + // Key restriction [25-24] + + uint32_t keyspec_restriction = 0; + if (key->flags & SL_SE_KEY_FLAG_NON_EXPORTABLE) { + keyspec_restriction = KEYSPEC_RESTRICTION_LOCKED; + } + if (key->flags & SL_SE_KEY_FLAG_IS_DEVICE_GENERATED) { + keyspec_restriction = KEYSPEC_RESTRICTION_INTERNAL; + } + if ((key->flags & SL_SE_KEY_FLAG_IS_RESTRICTED) == SL_SE_KEY_FLAG_IS_RESTRICTED) { + keyspec_restriction = KEYSPEC_RESTRICTION_RESTRICTED; + } + // Key restrictions are only applicable to volatile and wrapped keys + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + if (keyspec_restriction != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + *keyspec = (*keyspec & ~KEYSPEC_RESTRICTION_MASK) + | (keyspec_restriction & KEYSPEC_RESTRICTION_MASK); + + // --------------------- + // Key index [23-16] + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) { + if (key->storage.location.slot > SL_SE_KEY_SLOT_VOLATILE_3) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) + | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) + & KEYSPEC_INDEX_MASK); + } +#endif + + if (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { + if (key->storage.location.slot + < SL_SE_KEY_SLOT_INTERNAL_MIN) { + return SL_STATUS_INVALID_PARAMETER; + } + *keyspec = (*keyspec & ~KEYSPEC_INDEX_MASK) + | ((key->storage.location.slot << KEYSPEC_INDEX_OFFSET) + & KEYSPEC_INDEX_MASK); + } + + // --------------------- + // Key NoProt [15] + + if (key->flags & SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS) { + *keyspec = (*keyspec & ~KEYSPEC_NOPROT_MASK) | (1 << KEYSPEC_NOPROT_OFFSET); + } + + // --------------------- + // Key attributes [14-0] + + // Set general properties from key->type + if (key->storage.method != SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) { + *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_MASK) + | (key->type & KEYSPEC_ATTRIBUTES_MASK); + } + + // Set public/private flags + bool has_private_key = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) != 0); + bool has_public_key = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) != 0); +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + bool has_custom_curve = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) != 0); +#endif + bool signing_only = + ((key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY) != 0); + + if ((key->type & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { + if (has_private_key) { + *keyspec |= KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK; + } + if (has_public_key) { + *keyspec |= KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK; + } + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (has_custom_curve) { + *keyspec |= KEYSPEC_ATTRIBUTES_ECC_DOMAIN; + } + #endif + if (!(has_private_key || has_public_key)) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + if ((key->type & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME + && (key->type & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_EDDSA) { + if (signing_only) { + *keyspec |= KEYSPEC_ATTRIBUTES_ECC_SIGN; + } + } + + // Ensure that symmetric keys don't have asymmetric flags + if ((key->type & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { + if (has_private_key || has_public_key || signing_only) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + // Set or adjust the key attributes for different key types + uint32_t size = 0; + sl_status_t status; + status = sli_key_get_size(key, &size); + if (status != SL_STATUS_OK) { + return status; + } + + // Symmetric and raw keys + uint32_t key_type = (key->type & KEYSPEC_TYPE_MASK); + if (key_type == KEYSPEC_TYPE_RAW) { + *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_MASK) + | (size & KEYSPEC_ATTRIBUTES_MASK); + } else if ((key_type == KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) + || (key_type == KEYSPEC_TYPE_ECC_EDWARDS) + || (key_type == KEYSPEC_TYPE_ECC_MONTGOMERY) + || (key_type == KEYSPEC_TYPE_ECC_EDDSA)) { + *keyspec = (*keyspec & ~KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK) + | ((size - 1) & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK); + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + // Custom domain +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (has_custom_curve) { + if (key->domain == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + if (key_type == SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { + sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key->domain; + if (domain->a_is_zero && signing_only) { + *keyspec |= KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_ZERO; + } + if (domain->a_is_minus_three && signing_only) { + *keyspec |= KEYSPEC_ECC_WEIERSTRASS_PRIME_A_IS_MINUS_THREE; + } + } else { + return SL_STATUS_NOT_SUPPORTED; + } + } +#endif + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * @brief + * Convert a 32-bit SE compatible keyspec value to a key descriptor struct. + ******************************************************************************/ +sl_status_t sli_se_keyspec_to_key(const uint32_t keyspec, + sl_se_key_descriptor_t* key) +{ + if (key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Clear output + key->type = 0; + key->storage.method = 0; + key->storage.location.slot = 0; + key->size = 0; + key->flags = 0; + + // --------------------- + // Key type [31-28] + key->type = keyspec & KEYSPEC_TYPE_MASK; + + // --------------------- + // Key mode [27-26] and key index [23-16] + + if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_UNPROTECTED) { + key->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT; + } +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + else if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_WRAPPED) { + key->storage.method = SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED; + } +#endif + else if ((keyspec & KEYSPEC_MODE_MASK) == KEYSPEC_MODE_VOLATILE) { + // Volatile can mean either internal-volatile or internal-immutable + // Check which is which based on key index + uint32_t key_index = (keyspec & KEYSPEC_INDEX_MASK) >> KEYSPEC_INDEX_OFFSET; +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (key_index <= SL_SE_KEY_SLOT_VOLATILE_3) { + key->storage.method = SL_SE_KEY_STORAGE_INTERNAL_VOLATILE; + } else +#endif + if ((key_index <= SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY) + && (key_index >= SL_SE_KEY_SLOT_INTERNAL_MIN)) { + key->storage.method = SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE; + } else { + return SL_STATUS_INVALID_PARAMETER; + } + key->storage.location.slot = key_index; + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + // --------------------- + // Key restriction [25-24] + + uint32_t keyspec_restriction = (keyspec & KEYSPEC_RESTRICTION_MASK); + if (keyspec_restriction == KEYSPEC_RESTRICTION_LOCKED) { + key->flags |= SL_SE_KEY_FLAG_NON_EXPORTABLE; + } else if (keyspec_restriction == KEYSPEC_RESTRICTION_UNLOCKED) { + // no-op + } +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + else if (keyspec_restriction == KEYSPEC_RESTRICTION_INTERNAL) { + key->flags |= SL_SE_KEY_FLAG_IS_DEVICE_GENERATED; + } else if (keyspec_restriction == KEYSPEC_RESTRICTION_RESTRICTED) { + key->flags |= SL_SE_KEY_FLAG_IS_RESTRICTED; + } +#endif + else { + return SL_STATUS_INVALID_PARAMETER; + } + + // Key restrictions are only applicable to volatile and wrapped keys + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + if (keyspec_restriction != 0) { + return SL_STATUS_INVALID_PARAMETER; + } + } + + // --------------------- + // Key NoProt [15] + + if ((keyspec & KEYSPEC_NOPROT_MASK) == (1 << KEYSPEC_NOPROT_OFFSET)) { + key->flags |= SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS; + } + + // --------------------- + // Key attributes [14-0] + + // Set public/private flags + bool has_private_key = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_PRIVATE_MASK) != 0); + bool has_public_key = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_PUBLIC_MASK) != 0); +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + bool has_custom_curve = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_DOMAIN) != 0); +#endif + bool signing_only = ((keyspec & KEYSPEC_ATTRIBUTES_ECC_SIGN) != 0); + + if ((keyspec & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { + if (has_private_key) { + key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY; + } + if (has_public_key) { + key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY; + } +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (has_custom_curve) { + key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN; + + // TODO: custom curve parameter injection? + return SL_STATUS_NOT_SUPPORTED; + } +#endif + if (!(has_private_key || has_public_key)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // For ECC keys, their length is encoded in the type + key->type = (key->type & ~SL_SE_KEY_TYPE_ATTRIBUTES_MASK) | ((keyspec & KEYSPEC_ATTRIBUTES_ECC_SIZE_MASK) + 1); + } + + if ((keyspec & KEYSPEC_TYPE_MASK) >= KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME + && (keyspec & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_EDDSA) { + if (signing_only) { + key->flags |= SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY; + } + } + + // Ensure that symmetric keys don't have asymmetric flags + if ((keyspec & KEYSPEC_TYPE_MASK) < KEYSPEC_TYPE_ECC_WEIERSTRASS_PRIME) { + if (has_private_key || has_public_key || signing_only) { + return SL_STATUS_INVALID_PARAMETER; + } + + key->size = keyspec & KEYSPEC_ATTRIBUTES_MASK; + + switch ((keyspec & KEYSPEC_ATTRIBUTES_MASK)) { + case SL_SE_KEY_TYPE_AES_128: + case SL_SE_KEY_TYPE_AES_192: + case SL_SE_KEY_TYPE_AES_256: + key->type = keyspec & (KEYSPEC_TYPE_MASK | KEYSPEC_ATTRIBUTES_MASK); + break; + default: + break; + } + } + + return SL_STATUS_OK; +} + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +static const uint32_t default_auth_data[2] = { 0 }; +#endif + +sl_status_t sli_se_get_auth_buffer(const sl_se_key_descriptor_t *key, + SE_DataTransfer_t *auth_buffer) +{ + if (key == NULL || auth_buffer == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + auth_buffer->next = (void*)SE_DATATRANSFER_STOP; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) + || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED)) { + if (key->password) { + auth_buffer->data = key->password; + auth_buffer->length = sizeof(default_auth_data) | SE_DATATRANSFER_REALIGN; + } else { + auth_buffer->data = (void*)default_auth_data; + auth_buffer->length = sizeof(default_auth_data) | SE_DATATRANSFER_REALIGN; + } + } else { + auth_buffer->length = 0 | SE_DATATRANSFER_REALIGN; + } +#else + (void)key; + auth_buffer->length = 0 | SE_DATATRANSFER_REALIGN; +#endif + + return SL_STATUS_OK; +} + +sl_status_t sli_se_get_key_input_output(const sl_se_key_descriptor_t *key, + SE_DataTransfer_t *buffer) +{ + if (key == NULL || buffer == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + buffer->next = (void*)SE_DATATRANSFER_STOP; + + if ((key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) +#endif + ) { + // Set or adjust the key attributes for different key types + uint32_t storage_size = 0; + sl_status_t status = sli_key_get_storage_size(key, &storage_size); + if (status != SL_STATUS_OK) { + return status; + } + + uint32_t total_storage_size = 0; + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) { + total_storage_size = storage_size; + } +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + else if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) { + total_storage_size = storage_size + SLI_SE_WRAPPED_KEY_OVERHEAD; + } +#endif + + if (total_storage_size > key->storage.location.buffer.size) { + return SL_STATUS_WOULD_OVERFLOW; + } + + buffer->data = key->storage.location.buffer.pointer; + buffer->length = total_storage_size | SE_DATATRANSFER_REALIGN; + } else if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) +#endif + ) { + buffer->length = 0; + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Validate key descriptor. + ******************************************************************************/ +sl_status_t sl_se_validate_key(const sl_se_key_descriptor_t *key) +{ + sl_status_t status = SL_STATUS_OK; + uint32_t keyspec = 0; + + if (key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + status = sli_se_key_to_keyspec(key, &keyspec); + if (status != SL_STATUS_OK) { + return status; + } + + SE_DataTransfer_t auth_buffer; + status = sli_se_get_auth_buffer(key, &auth_buffer); + if (status != SL_STATUS_OK) { + return status; + } + + SE_DataTransfer_t key_buffer; + status = sli_se_get_key_input_output(key, &key_buffer); + if (status != SL_STATUS_OK) { + return status; + } + + return status; +} + +/***************************************************************************//** + * Generate a random key adhering to the given key descriptor + ******************************************************************************/ +sl_status_t sl_se_generate_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_out) +{ + sl_status_t status; + + if (cmd_ctx == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CREATE_KEY); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key_out, status); + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + SE_Command_t *se_cmd = &cmd_ctx->command; + // Custom curve domain + SE_DataTransfer_t domain_p_buffer; + SE_DataTransfer_t domain_N_buffer; + SE_DataTransfer_t domain_Gx_buffer; + SE_DataTransfer_t domain_Gy_buffer; + SE_DataTransfer_t domain_a_buffer; + SE_DataTransfer_t domain_b_buffer; + + if (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN) { + if (key_out->type & SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM) { + sl_se_custom_weierstrass_prime_domain_t *domain = (sl_se_custom_weierstrass_prime_domain_t*)key_out->domain; + uint32_t domain_size = domain->size; + + domain_p_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_p_buffer.data = (void*)domain->p; + domain_p_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_p_buffer); + + domain_N_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_N_buffer.data = (void*)domain->N; + domain_N_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_N_buffer); + + domain_Gx_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_Gx_buffer.data = (void*)domain->Gx; + domain_Gx_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_Gx_buffer); + + domain_Gy_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_Gy_buffer.data = (void*)domain->Gy; + domain_Gy_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_Gy_buffer); + + domain_a_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_a_buffer.data = (void*)domain->a; + domain_a_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_a_buffer); + + domain_b_buffer.next = (void*)SE_DATATRANSFER_STOP; + domain_b_buffer.data = (void*)domain->b; + domain_b_buffer.length = domain_size; + SE_addDataInput(se_cmd, (SE_DataTransfer_t*)&domain_b_buffer); + } else { + return SL_STATUS_NOT_SUPPORTED; + } + } +#endif + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key_out, status); + // Add key output block to command + sli_add_key_output(cmd_ctx, key_out, status); + + // Execute command + status = sli_se_execute_and_wait(cmd_ctx); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Clear padding for plaintext keys upon success + if (status == SL_STATUS_OK) { + status = clear_padding(key_out); + } + #endif + + return status; +} + +/***************************************************************************//** + * Export the public key of an ECC keypair + ******************************************************************************/ +sl_status_t sl_se_export_public_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out) +{ + if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + // Check input/output key type and size relationship + status = sli_key_check_equivalent(key_in, key_out, true, true); + if (status != SL_STATUS_OK) { + return status; + } + + // Check that the input key has a private or public key + if (!(key_in->flags & (SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY + | SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY))) { + return SL_STATUS_INVALID_PARAMETER; + } + if (!(key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY) + || (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READPUB_KEY); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key_in, status); + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key_in, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key_in, status); + + // Pubkey buffer + // Check for correct storage and flags + if ((key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) + || (key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY) + || !(key_out->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY)) { + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t required_storage_size; + status = sli_key_get_storage_size(key_out, &required_storage_size); + if (status != SL_STATUS_OK) { + return status; + } + + if (required_storage_size > key_out->storage.location.buffer.size) { + return SL_STATUS_WOULD_OVERFLOW; + } + + SE_DataTransfer_t pubkey_buffer = SE_DATATRANSFER_DEFAULT( + key_out->storage.location.buffer.pointer, required_storage_size); + SE_addDataOutput(se_cmd, &pubkey_buffer); + + // Execute command. + // The retries are necessary in order to reduce the risk of random failures + // in the accelerated point multiplication. This mainly affects very small or + // large scalars, which in this case would be the private key. + for (size_t i = 0; i < SLI_SE_MAX_POINT_MULT_RETRIES; ++i) { + status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_FAIL) { + break; + } + } + return status; +} + +/***************************************************************************//** + * Returns the required storage size for the given key + ******************************************************************************/ +sl_status_t sl_se_get_storage_size(const sl_se_key_descriptor_t *key, uint32_t *storage_size) +{ + if (key == NULL || storage_size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if ((key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + || (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) +#endif + ) { + // Set or adjust the key attributes for different key types + sl_status_t status = sli_key_get_storage_size(key, storage_size); + if (status != SL_STATUS_OK) { + return status; + } +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + if (key->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED) { + *storage_size = *storage_size + SLI_SE_WRAPPED_KEY_OVERHEAD; + } +#endif + } else if ((key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + || (key->storage.method == SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) +#endif + ) { + *storage_size = 0; + } else { + return SL_STATUS_INVALID_PARAMETER; + } + + return SL_STATUS_OK; +} + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * Protect a plaintext key using the SE + ******************************************************************************/ +sl_status_t sl_se_import_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out) +{ + sl_status_t status; + + if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check input/output key type and size relationship + status = sli_key_check_equivalent(key_in, key_out, true, false); + if (status != SL_STATUS_OK) { + return status; + } + + if ((key_in->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) + || ((key_out->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) + && (key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED))) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_WRAP_KEY); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key_out, status); + + // Add key input block to command + sli_add_key_input(cmd_ctx, key_in, status); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key_out, status); + + // Add key output block to command + sli_add_key_output(cmd_ctx, key_out, status); + + status = sli_se_execute_and_wait(cmd_ctx); + return status; +} + +/***************************************************************************//** + * Export a volatile or wrapped key back to plaintext if allowed + ******************************************************************************/ +sl_status_t sl_se_export_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out) +{ + sl_status_t status; + + if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Check input/output key type and size relationship + status = sli_key_check_equivalent(key_in, key_out, true, false); + if (status != SL_STATUS_OK) { + return status; + } + + if ((key_out->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) + || ((key_in->storage.method != SL_SE_KEY_STORAGE_INTERNAL_VOLATILE) + && (key_in->storage.method != SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED))) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_UNWRAP_KEY); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key_in, status); + + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key_in, status); + + // Add key input block to command + sli_add_key_input(cmd_ctx, key_in, status); + + // Add key output block to command + sli_add_key_output(cmd_ctx, key_out, status); + + status = sli_se_execute_and_wait(cmd_ctx); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // The SE will only output word-aligned data. Clear the extra padding before + // returning + if (status == SL_STATUS_OK) { + status = clear_padding(key_out); + } + #endif + + return status; +} + +/***************************************************************************//** + * Transfer a protected (volatile/wrapped) key + ******************************************************************************/ +sl_status_t sl_se_transfer_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key_in, + const sl_se_key_descriptor_t *key_out) +{ + if (cmd_ctx == NULL || key_in == NULL || key_out == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + SE_DataTransfer_t auth_buffer_out; + uint32_t key_update_index; + uint32_t key_update_mode; + + // Check input/output key type and size relationship + status = sli_key_check_equivalent(key_in, key_out, true, false); + if (status != SL_STATUS_OK) { + return status; + } + + if ((key_in->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) + || (key_in->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE) + || (key_out->storage.method == SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT) + || (key_out->storage.method == SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Create command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_TRANSFER_KEY); + + // Add key input parameters to command + sli_add_key_parameters(cmd_ctx, key_in, status); + + // Add key update parameters to command + uint32_t keyspec_out; + status = sli_se_key_to_keyspec(key_out, &keyspec_out); + if (status != SL_STATUS_OK) { + return status; + } + key_update_index = ((keyspec_out & KEYSPEC_INDEX_MASK) >> KEYSPEC_INDEX_OFFSET); + key_update_mode = ((keyspec_out & KEYSPEC_MODE_MASK) >> KEYSPEC_MODE_OFFSET); + keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_INDEX_MASK) + | ((key_update_index << KEYSPEC_TRANSFER_INDEX_OFFSET) + & KEYSPEC_TRANSFER_INDEX_MASK); + keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_MODE_MASK) + | ((key_update_mode << KEYSPEC_TRANSFER_MODE_OFFSET) + & KEYSPEC_TRANSFER_MODE_MASK); + keyspec_out = (keyspec_out & ~KEYSPEC_TRANSFER_PROT_BIT_MASK); + SE_addParameter(se_cmd, keyspec_out); + + // Add key input metadata block to command + sli_add_key_metadata(cmd_ctx, key_in, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key_in, status); + + // Add key output metadata block to command + status = sli_se_get_auth_buffer(key_out, &auth_buffer_out); + if (status != SL_STATUS_OK) { + return status; + } + SE_addDataInput(se_cmd, &auth_buffer_out); + + // Add key output block to command + sli_add_key_output(cmd_ctx, key_out, status); + + status = sli_se_execute_and_wait(cmd_ctx); + + #if defined(SLI_SE_KEY_PADDING_REQUIRED) + // Clear padding bytes for plaintext keys upon success + if (status == SL_STATUS_OK) { + status = clear_padding(key_out); + } + #endif + + return status; +} + +/***************************************************************************//** + * Delete a key a volatile SE storage slot + ******************************************************************************/ +sl_status_t sl_se_delete_key(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key) +{ + sl_status_t status; + + if (cmd_ctx == NULL || key == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Initialize command + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DELETE_KEY); + + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + + // Execute command + status = sli_se_execute_and_wait(cmd_ctx); + return status; +} +#endif + +/** @} (end addtogroup sl_se_key) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c index 1f1f956..7de58c3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c @@ -1,212 +1,212 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -#include "sl_se_manager.h" -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include - -/// @addtogroup sl_se_manager -/// @{ - -// ----------------------------------------------------------------------------- -// Global Functions - -/***************************************************************************//** - * ECC signature generation. - ******************************************************************************/ -sl_status_t sl_se_ecc_sign(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_alg, - bool hashed_message, - const unsigned char *message, - size_t message_len, - unsigned char *signature, - size_t signature_len) -{ - if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - uint32_t command_word = SLI_SE_COMMAND_SIGNATURE_SIGN; - - if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - == SL_SE_KEY_TYPE_ECC_EDDSA) { - command_word = SLI_SE_COMMAND_EDDSA_SIGN; - } else { - if (hashed_message == false) { - switch (hash_alg) { - case SL_SE_HASH_SHA1: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; - break; - - case SL_SE_HASH_SHA224: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; - break; - - case SL_SE_HASH_SHA256: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; - break; - - case SL_SE_HASH_SHA512: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; - break; -#endif - default: - return SL_STATUS_INVALID_PARAMETER; - } - } - } - - // Setup SE command and parameters - sli_se_command_init(cmd_ctx, command_word); - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, message_len); - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t message_buffer = SE_DATATRANSFER_DEFAULT(message, message_len); - SE_addDataInput(se_cmd, &message_buffer); - - // EdDSA requires the message twice - SE_DataTransfer_t repeated_message_buffer = SE_DATATRANSFER_DEFAULT(message, message_len); - if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) == SL_SE_KEY_TYPE_ECC_EDDSA) { - SE_addDataInput(se_cmd, &repeated_message_buffer); - } - - SE_DataTransfer_t signature_buffer = SE_DATATRANSFER_DEFAULT(signature, signature_len); - SE_addDataOutput(se_cmd, &signature_buffer); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * ECC signature verification. - ******************************************************************************/ -sl_status_t sl_se_ecc_verify(sl_se_command_context_t *cmd_ctx, - const sl_se_key_descriptor_t *key, - sl_se_hash_type_t hash_alg, - bool hashed_message, - const unsigned char *message, - size_t message_len, - const unsigned char *signature, - size_t signature_len) -{ - if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - // Key needs to contain public key in order to verify signatures - if (!(key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY)) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - uint32_t command_word = SLI_SE_COMMAND_SIGNATURE_VERIFY; - - if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) - == SL_SE_KEY_TYPE_ECC_EDDSA) { - command_word = SLI_SE_COMMAND_EDDSA_VERIFY; - } else { - if (hashed_message == false) { - switch (hash_alg) { - case SL_SE_HASH_SHA1: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; - break; - - case SL_SE_HASH_SHA224: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; - break; - - case SL_SE_HASH_SHA256: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; - break; - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_HASH_SHA384: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; - break; - - case SL_SE_HASH_SHA512: - command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; - break; - -#endif - default: - return SL_STATUS_INVALID_PARAMETER; - } - } - } - - // Setup SE command and parameters - sli_se_command_init(cmd_ctx, command_word); - // Add key parameters to command - sli_add_key_parameters(cmd_ctx, key, status); - // Message size (number of bytes) - SE_addParameter(se_cmd, message_len); - // Add key metadata block to command - sli_add_key_metadata(cmd_ctx, key, status); - // Add key input block to command - sli_add_key_input(cmd_ctx, key, status); - - SE_DataTransfer_t message_buffer = SE_DATATRANSFER_DEFAULT(message, - message_len); - SE_DataTransfer_t signature_buffer = SE_DATATRANSFER_DEFAULT(signature, - signature_len); - - if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) == SL_SE_KEY_TYPE_ECC_EDDSA) { - SE_addDataInput(se_cmd, &signature_buffer); - SE_addDataInput(se_cmd, &message_buffer); - } else { - SE_addDataInput(se_cmd, &message_buffer); - SE_addDataInput(se_cmd, &signature_buffer); - } - - return sli_se_execute_and_wait(cmd_ctx); -} - -/** @} (end addtogroup sl_se) */ - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +#include "sl_se_manager.h" +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include + +/// @addtogroup sl_se_manager +/// @{ + +// ----------------------------------------------------------------------------- +// Global Functions + +/***************************************************************************//** + * ECC signature generation. + ******************************************************************************/ +sl_status_t sl_se_ecc_sign(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_alg, + bool hashed_message, + const unsigned char *message, + size_t message_len, + unsigned char *signature, + size_t signature_len) +{ + if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + uint32_t command_word = SLI_SE_COMMAND_SIGNATURE_SIGN; + + if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + == SL_SE_KEY_TYPE_ECC_EDDSA) { + command_word = SLI_SE_COMMAND_EDDSA_SIGN; + } else { + if (hashed_message == false) { + switch (hash_alg) { + case SL_SE_HASH_SHA1: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; + break; + + case SL_SE_HASH_SHA224: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; + break; + + case SL_SE_HASH_SHA256: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; + break; + + case SL_SE_HASH_SHA512: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; + break; +#endif + default: + return SL_STATUS_INVALID_PARAMETER; + } + } + } + + // Setup SE command and parameters + sli_se_command_init(cmd_ctx, command_word); + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, message_len); + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t message_buffer = SE_DATATRANSFER_DEFAULT(message, message_len); + SE_addDataInput(se_cmd, &message_buffer); + + // EdDSA requires the message twice + SE_DataTransfer_t repeated_message_buffer = SE_DATATRANSFER_DEFAULT(message, message_len); + if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) == SL_SE_KEY_TYPE_ECC_EDDSA) { + SE_addDataInput(se_cmd, &repeated_message_buffer); + } + + SE_DataTransfer_t signature_buffer = SE_DATATRANSFER_DEFAULT(signature, signature_len); + SE_addDataOutput(se_cmd, &signature_buffer); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * ECC signature verification. + ******************************************************************************/ +sl_status_t sl_se_ecc_verify(sl_se_command_context_t *cmd_ctx, + const sl_se_key_descriptor_t *key, + sl_se_hash_type_t hash_alg, + bool hashed_message, + const unsigned char *message, + size_t message_len, + const unsigned char *signature, + size_t signature_len) +{ + if (cmd_ctx == NULL || key == NULL || message == NULL || signature == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + // Key needs to contain public key in order to verify signatures + if (!(key->flags & SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY)) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + uint32_t command_word = SLI_SE_COMMAND_SIGNATURE_VERIFY; + + if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) + == SL_SE_KEY_TYPE_ECC_EDDSA) { + command_word = SLI_SE_COMMAND_EDDSA_VERIFY; + } else { + if (hashed_message == false) { + switch (hash_alg) { + case SL_SE_HASH_SHA1: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA1; + break; + + case SL_SE_HASH_SHA224: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA224; + break; + + case SL_SE_HASH_SHA256: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA256; + break; + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_HASH_SHA384: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA384; + break; + + case SL_SE_HASH_SHA512: + command_word |= SLI_SE_COMMAND_OPTION_HASH_SHA512; + break; + +#endif + default: + return SL_STATUS_INVALID_PARAMETER; + } + } + } + + // Setup SE command and parameters + sli_se_command_init(cmd_ctx, command_word); + // Add key parameters to command + sli_add_key_parameters(cmd_ctx, key, status); + // Message size (number of bytes) + SE_addParameter(se_cmd, message_len); + // Add key metadata block to command + sli_add_key_metadata(cmd_ctx, key, status); + // Add key input block to command + sli_add_key_input(cmd_ctx, key, status); + + SE_DataTransfer_t message_buffer = SE_DATATRANSFER_DEFAULT(message, + message_len); + SE_DataTransfer_t signature_buffer = SE_DATATRANSFER_DEFAULT(signature, + signature_len); + + if ((key->type & SL_SE_KEY_TYPE_ALGORITHM_MASK) == SL_SE_KEY_TYPE_ECC_EDDSA) { + SE_addDataInput(se_cmd, &signature_buffer); + SE_addDataInput(se_cmd, &message_buffer); + } else { + SE_addDataInput(se_cmd, &message_buffer); + SE_addDataInput(se_cmd, &signature_buffer); + } + + return sli_se_execute_and_wait(cmd_ctx); +} + +/** @} (end addtogroup sl_se) */ + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_util.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_util.c index ccc7d1a..530ccf6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_util.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sl_se_manager_util.c @@ -1,1331 +1,1331 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs Secure Engine Manager API. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_se_manager_util.h" - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -#include "sli_se_manager_internal.h" -#include "em_se.h" -#include "sl_assert.h" - -#if defined(SLI_SE_MAJOR_VERSION_ONE) - #include "em_system.h" -#endif - -/// @addtogroup sl_se_manager -/// @{ - -// ----------------------------------------------------------------------------- -// Defines - -// OTP initialization structure defines. -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) -#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) - -// ----------------------------------------------------------------------------- -// Local Functions - -/***************************************************************************//** - * @brief - * Decode debug status word (as received from the SE). - * - * @return N/A - ******************************************************************************/ -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) -static void decode_debug_status(sl_se_debug_status_t *debug_status, - uint32_t status_word) -{ - debug_status->debug_port_lock_applied = status_word & (1 << 0); - debug_status->device_erase_enabled = status_word & (1 << 1); - debug_status->secure_debug_enabled = status_word & (1 << 2); - debug_status->debug_port_lock_state = status_word & (1 << 5); - debug_status->options_state.non_secure_invasive_debug = - (status_word & (1 << 6)) == 0; - debug_status->options_state.non_secure_non_invasive_debug = - (status_word & (1 << 7)) == 0; - debug_status->options_state.secure_invasive_debug = - (status_word & (1 << 8)) == 0; - debug_status->options_state.secure_non_invasive_debug = - (status_word & (1 << 9)) == 0; - debug_status->options_config.non_secure_invasive_debug = - (status_word & (1 << 10)) == 0; - debug_status->options_config.non_secure_non_invasive_debug = - (status_word & (1 << 11)) == 0; - debug_status->options_config.secure_invasive_debug = - (status_word & (1 << 12)) == 0; - debug_status->options_config.secure_non_invasive_debug = - (status_word & (1 << 13)) == 0; -} -#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) -static void decode_debug_status(sl_se_debug_status_t *debug_status, - uint32_t status_word) -{ - debug_status->debug_port_lock_applied = status_word & (1 << 10); - debug_status->device_erase_enabled = status_word & (1 << 11); - debug_status->secure_debug_enabled = status_word & (1 << 12); - debug_status->debug_port_lock_state = status_word & (1 << 15); -} -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -// ----------------------------------------------------------------------------- -// Global Functions - -/***************************************************************************//** - * Validate SE firmware image. - ******************************************************************************/ -sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, - void *image_addr) -{ - if (cmd_ctx == NULL || image_addr == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHECK_SE_IMAGE); - - SE_addParameter(se_cmd, (uint32_t)image_addr); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Apply SE firmware image. - ******************************************************************************/ -sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, - void *image_addr) -{ - if (cmd_ctx == NULL || image_addr == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_APPLY_SE_IMAGE); - - SE_addParameter(se_cmd, (uint32_t)image_addr); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Get upgrade status of SE firmware image. - ******************************************************************************/ -sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, - uint32_t *status, - uint32_t *prev_version) -{ - if (cmd_ctx == NULL || status == NULL || prev_version == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_SE_IMAGE); - - volatile uint32_t out_buf[2]; - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(out_buf, - sizeof(out_buf)); - SE_addDataOutput(se_cmd, &out_data); - - sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - *status = out_buf[0]; - *prev_version = out_buf[1]; - } - - return ret; -} - -/***************************************************************************//** - * Validate Host firmware image. - ******************************************************************************/ -sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, - void *image_addr, - uint32_t size) -{ - if (cmd_ctx == NULL || image_addr == NULL || size == 0UL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHECK_HOST_IMAGE); - - SE_addParameter(se_cmd, (uint32_t)image_addr); - SE_addParameter(se_cmd, size); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Apply Host firmware image. - ******************************************************************************/ -sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, - void *image_addr, - uint32_t size) -{ - if (cmd_ctx == NULL || image_addr == NULL || size == 0UL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_APPLY_HOST_IMAGE); - - SE_addParameter(se_cmd, (uint32_t)image_addr); - SE_addParameter(se_cmd, size); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Get upgrade status of Host firmware image. - ******************************************************************************/ -sl_status_t -sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, - uint32_t *status, - uint32_t *prev_version) -{ - if (cmd_ctx == NULL || status == NULL || prev_version == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_HOST_IMAGE); - - volatile uint32_t out_buf[2]; - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(out_buf, - sizeof(out_buf)); - SE_addDataOutput(se_cmd, &out_data); - - sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - *status = out_buf[0]; - *prev_version = out_buf[1]; - } - - return ret; -} - -/***************************************************************************//** - * Initialize key to be stored in the SE OTP flash. - ******************************************************************************/ -sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, - sl_se_device_key_type_t key_type, - void *key, - uint32_t num_bytes) -{ - if (cmd_ctx == NULL || key == NULL || num_bytes == 0UL || (size_t)key & 3U) { - return SL_STATUS_INVALID_PARAMETER; - } - - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - if (key_type == SL_SE_KEY_TYPE_IMMUTABLE_AES_128) { - if (num_bytes != 16UL) { - return SL_STATUS_INVALID_PARAMETER; - } - } else { - if (num_bytes != 64UL) { - return SL_STATUS_INVALID_PARAMETER; - } - } - #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - if (num_bytes != 64UL) { - return SL_STATUS_INVALID_PARAMETER; - } - #endif - - uint32_t command_word; - SE_Command_t *se_cmd = &cmd_ctx->command; - - uint32_t se_key_type; - switch (key_type) { - case SL_SE_KEY_TYPE_IMMUTABLE_BOOT: - se_key_type = SLI_SE_KEY_TYPE_BOOT; - break; - - case SL_SE_KEY_TYPE_IMMUTABLE_AUTH: - se_key_type = SLI_SE_KEY_TYPE_AUTH; - break; - - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - case SL_SE_KEY_TYPE_IMMUTABLE_AES_128: - se_key_type = SLI_SE_IMMUTABLE_KEY_TYPE_AES_128; - break; - #endif // SLI_MAILBOX_COMMAND_SUPPORTED - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } - - // Find parity word - volatile uint32_t parity = 0; - for (size_t i = 0; i < num_bytes / 4; i++) { - parity = parity ^ ((uint32_t *)key)[i]; - } - - // SE command structures - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - command_word = key_type == SL_SE_KEY_TYPE_IMMUTABLE_AES_128 - ? SLI_SE_COMMAND_INIT_AES_128_KEY : SLI_SE_COMMAND_INIT_PUBKEY; - #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - command_word = SLI_SE_COMMAND_INIT_PUBKEY; - #endif - - sli_se_command_init(cmd_ctx, (command_word | se_key_type)); - - SE_DataTransfer_t parity_data = SE_DATATRANSFER_DEFAULT(&parity, 4); - SE_addDataInput(se_cmd, &parity_data); - - SE_DataTransfer_t key_data = SE_DATATRANSFER_DEFAULT(key, num_bytes); - SE_addDataInput(se_cmd, &key_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read a public key stored in the SE. - ******************************************************************************/ -sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, - sl_se_device_key_type_t key_type, - void *key, - uint32_t num_bytes) -{ - if (cmd_ctx == NULL || key == NULL || num_bytes != 64UL || (size_t)key & 3U) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t se_key_type; - uint32_t command_word = SLI_SE_COMMAND_READ_PUBKEY; - switch (key_type) { - case SL_SE_KEY_TYPE_IMMUTABLE_BOOT: - se_key_type = SLI_SE_KEY_TYPE_BOOT; - break; - - case SL_SE_KEY_TYPE_IMMUTABLE_AUTH: - se_key_type = SLI_SE_KEY_TYPE_AUTH; - break; - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - case SL_SE_KEY_TYPE_IMMUTABLE_SE_ATTESTATION: - command_word = command_word & ~0x1; - // Intentional fallthrough - case SL_SE_KEY_TYPE_IMMUTABLE_ATTESTATION: - se_key_type = SLI_SE_KEY_TYPE_ATTEST; - break; - #endif // _SILICON_LABS_SECURITY_FEATURE_VAULT - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } - - // SE command structures - sli_se_command_init(cmd_ctx, command_word | se_key_type); - - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(key, num_bytes); - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read the SE firmware version. - ******************************************************************************/ -sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, - uint32_t *version) -{ - if (cmd_ctx == NULL || version == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_SE_VERSION); - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); - - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); - - #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - - sl_status_t status = SL_STATUS_OK; - SE_Response_t command_response; - - // Try to acquire SE lock. - // Need to protect VSE mailbox from being written by e.g. SE_ackCommand() - status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Read SE version from VSE mailbox. - command_response = SE_getVersion(version); - - // Release SE lock - status = sli_se_lock_release(); - - // Return sl_status_t code. - if (command_response == SLI_SE_RESPONSE_OK) { - return status; - } else { - // Convert from SE_Response_t to sl_status_t code and return. - return sli_se_to_sl_status(command_response); - } - - #endif -} - -/***************************************************************************//** - * Enables the debug lock for the part. - ******************************************************************************/ -sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_APPLY); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Returns the current debug lock configuration. - ******************************************************************************/ -sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, - sl_se_debug_status_t *debug_status) -{ - if (cmd_ctx == NULL || debug_status == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - SE_Command_t *se_cmd = &cmd_ctx->command; - volatile uint32_t status_word = 0; - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(&status_word, 4); - - // Initialize SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_STATUS); - SE_addDataOutput(se_cmd, &out_data); - - sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - decode_debug_status(debug_status, status_word); - } - - return ret; - #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - uint32_t vse_version = 0; - uint32_t debug_lock_flags = 0; - - // Try to acquire SE lock - sl_status_t status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - // Read SE version from VSE mailbox. - SE_Response_t vse_mbx_status = SE_getVersion(&vse_version); - - // Reading debug lock status is not supported on VSE with versions <= 1.2.2. - if ((vse_version <= 0x1010202UL) || (vse_mbx_status != SE_RESPONSE_OK)) { - sli_se_lock_release(); - return SL_STATUS_COMMAND_IS_INVALID; - } - - vse_mbx_status = SE_getConfigStatusBits(&debug_lock_flags); - // Release SE lock - status = sli_se_lock_release(); - - if (vse_mbx_status != SE_RESPONSE_OK) { - return sli_se_to_sl_status(vse_mbx_status); - } else if (status != SL_STATUS_OK) { - return status; - } - - decode_debug_status(debug_status, debug_lock_flags); - - return SL_STATUS_OK; - #endif -} - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/***************************************************************************//** - * Initialize SE OTP configuration. - ******************************************************************************/ -sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_init) -{ - if (cmd_ctx == NULL || otp_init == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t mcu_settings_flags = 0; - - sl_status_t status; - - if (otp_init->enable_secure_boot) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; - - // Check for installed boot pubkey before OTP initialization - uint8_t pubkey[64]; - status = - sl_se_read_pubkey(cmd_ctx, SL_SE_KEY_TYPE_IMMUTABLE_BOOT, &pubkey, 64); - if (status != SL_STATUS_OK) { - return SL_STATUS_ABORT; - } - } - if (otp_init->verify_secure_boot_certificate) { - mcu_settings_flags |= - SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; - } - if (otp_init->enable_anti_rollback) { - // Verify firmware compatibility before enabling anti-rollback - #if defined(SLI_SE_MAJOR_VERSION_ONE) - uint16_t part_number = SYSTEM_GetPartNumber(); - if (part_number == 1010 || part_number == 1020) { - if (SYSTEM_GetProdRev() < 16) { - sl_se_status_t se_status; - status = sl_se_get_status(cmd_ctx, &se_status); - if ((status != SL_STATUS_OK) - || (se_status.se_fw_version < 0x00010201)) { - // If the following error is returned, the SE firmware version - // needs to be upgraded to v1.2.1 or higher before enabling - // anti-rollback. - EFM_ASSERT(false); - return SL_STATUS_ABORT; - } - } - } - #endif - - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; - } - if (otp_init->secure_boot_page_lock_narrow) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; - } - if (otp_init->secure_boot_page_lock_full) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; - } - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - static struct { - uint8_t levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS / 2]; - uint8_t period; - uint8_t threshold; - uint8_t flags; - uint8_t reset_threshold; - } otp_tamper_settings; - - // Check for reserved sources - if ((otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_1] != SL_SE_TAMPER_LEVEL_IGNORE) - || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_2] != SL_SE_TAMPER_LEVEL_IGNORE) - || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_3] != SL_SE_TAMPER_LEVEL_IGNORE) - || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_4] != SL_SE_TAMPER_LEVEL_IGNORE)) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Combine tamper levels, two per byte - for (size_t i = 0; i < SL_SE_TAMPER_SIGNAL_NUM_SIGNALS; i += 2) { - // Check for reserved levels - for (size_t offset = 0; offset < 2; ++offset) { - switch (otp_init->tamper_levels[i + offset]) { - case SL_SE_TAMPER_LEVEL_IGNORE: - case SL_SE_TAMPER_LEVEL_INTERRUPT: - case SL_SE_TAMPER_LEVEL_FILTER: - case SL_SE_TAMPER_LEVEL_RESET: - case SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP: - break; - default: - return SL_STATUS_INVALID_PARAMETER; - } - } - - otp_tamper_settings.levels[i / 2] = (otp_init->tamper_levels[i] & 0x7) - | ((otp_init->tamper_levels[i + 1] & 0x7) << 4); - } - // Limit period and threshold input - otp_tamper_settings.period = otp_init->tamper_filter_period & 0x1f; - otp_tamper_settings.threshold = otp_init->tamper_filter_threshold & 0x7; - - #if !defined(SLI_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_AVAILABLE) - if ((otp_init->tamper_flags & SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP) - == SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP) { - return SL_STATUS_INVALID_PARAMETER; - } - #endif - otp_tamper_settings.flags = otp_init->tamper_flags; - otp_tamper_settings.reset_threshold = otp_init->tamper_reset_threshold; - #else - static struct otp_tamper_settings { - uint8_t reserved1[16]; - uint8_t reserved2[2]; - uint8_t reserved3[2]; - } otp_tamper_settings = { - { 0x00 }, - { 0xFF, 0xFF }, - { 0x00 } - }; - #endif - - // Find parity word - volatile uint32_t parity = 0; - parity = parity ^ mcu_settings_flags; - for (size_t i = 0; i < 5; i++) { - parity = parity ^ ((uint32_t*)(&otp_tamper_settings))[i]; - } - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_INIT_OTP); - - volatile uint32_t parameters[2] = { - parity, - sizeof(mcu_settings_flags) - + sizeof(otp_tamper_settings) - }; - SE_DataTransfer_t parameters_data = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(se_cmd, ¶meters_data); - - SE_DataTransfer_t mcu_settings_flags_data = - SE_DATATRANSFER_DEFAULT((volatile void *)&mcu_settings_flags, sizeof(mcu_settings_flags)); - SE_addDataInput(se_cmd, &mcu_settings_flags_data); - - SE_DataTransfer_t tamper_settings_data = - SE_DATATRANSFER_DEFAULT((volatile void *)&otp_tamper_settings, sizeof(otp_tamper_settings)); - SE_addDataInput(se_cmd, &tamper_settings_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read SE OTP configuration. - ******************************************************************************/ -sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_settings) -{ - if (cmd_ctx == NULL || otp_settings == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - sl_status_t status; - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - volatile struct { - uint32_t mcu_settings_flags; - uint8_t levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS / 2]; - uint8_t period; - uint8_t threshold; - uint8_t flags; - uint8_t reset_threshold; - } otp_raw; - #else - volatile struct { - uint32_t mcu_settings_flags; - uint8_t reserved1[16]; - uint8_t reserved2[2]; - uint8_t reserved3[2]; - } otp_raw; - #endif - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_OTP); - - SE_DataTransfer_t otp_raw_data = - SE_DATATRANSFER_DEFAULT(&otp_raw, sizeof(otp_raw)); - SE_addDataOutput(se_cmd, &otp_raw_data); - - status = sli_se_execute_and_wait(cmd_ctx); - - if (status != SL_STATUS_OK) { - return status; - } - - otp_settings->enable_secure_boot = - (otp_raw.mcu_settings_flags - & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE); - otp_settings->verify_secure_boot_certificate = - (otp_raw.mcu_settings_flags - & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE); - otp_settings->enable_anti_rollback = - (otp_raw.mcu_settings_flags - & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK); - otp_settings->secure_boot_page_lock_narrow = - (otp_raw.mcu_settings_flags - & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW); - otp_settings->secure_boot_page_lock_full = - (otp_raw.mcu_settings_flags - & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL); - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - // Split levels - for (size_t i = 0; i < sizeof(otp_raw.levels); i++) { - otp_settings->tamper_levels[2 * i] = (otp_raw.levels[i]) & 0x7; - otp_settings->tamper_levels[2 * i + 1] = (otp_raw.levels[i] >> 4) & 0x7; - } - - otp_settings->tamper_filter_period = otp_raw.period; - otp_settings->tamper_filter_threshold = otp_raw.threshold; - - otp_settings->tamper_flags = otp_raw.flags; - otp_settings->tamper_reset_threshold = otp_raw.reset_threshold; - #endif - - return SL_STATUS_OK; -} - -#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) - -sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_init) -{ - if (cmd_ctx == NULL || otp_init == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - volatile uint32_t mcu_settings_flags = 0; - - if (otp_init->enable_secure_boot) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; - } - if (otp_init->verify_secure_boot_certificate) { - mcu_settings_flags |= - SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; - } - if (otp_init->enable_anti_rollback) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; - } - if (otp_init->secure_boot_page_lock_narrow) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; - } - if (otp_init->secure_boot_page_lock_full) { - mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; - } - - // Find parity word - uint32_t parity = 0; - parity = parity ^ mcu_settings_flags; - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_INIT_OTP); - - volatile uint32_t parameters[2] = { - parity, - sizeof(mcu_settings_flags) - }; - SE_DataTransfer_t parameters_data = SE_DATATRANSFER_DEFAULT(¶meters, 8); - SE_addDataInput(se_cmd, ¶meters_data); - - SE_DataTransfer_t mcu_settings_flags_data = - SE_DATATRANSFER_DEFAULT(&mcu_settings_flags, sizeof(mcu_settings_flags)); - SE_addDataInput(se_cmd, &mcu_settings_flags_data); - - SE_executeCommand(se_cmd); - return SL_STATUS_FAIL; // Should never get to this point -} - -/***************************************************************************//** - * Read the OTP firmware version of the SE module. - ******************************************************************************/ -sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, - uint32_t *version) -{ - if (cmd_ctx == NULL || version == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - sl_status_t lock_status = sli_se_lock_acquire(); - if (lock_status != SL_STATUS_OK) { - return lock_status; - } - - SE_Response_t otp_status = SE_getOTPVersion(version); - - // Release SE lock - sli_se_lock_release(); - - if (otp_status == SE_RESPONSE_OK) { - return SL_STATUS_OK; - } - - return SL_STATUS_NOT_SUPPORTED; -} - -sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, - sl_se_otp_init_t *otp_settings) -{ - if (cmd_ctx == NULL || otp_settings == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Try to acquire SE lock - sl_status_t status = sli_se_lock_acquire(); - if (status != SL_STATUS_OK) { - return status; - } - - uint32_t mcu_settings_flags = 0; - SE_Response_t vse_mbx_status = SE_getConfigStatusBits(&mcu_settings_flags); - - // Release SE lock - status = sli_se_lock_release(); - - if (vse_mbx_status != SE_RESPONSE_OK) { - return sli_se_to_sl_status(vse_mbx_status); - } else if (status != SL_STATUS_OK) { - return status; - } - - otp_settings->enable_secure_boot = - (mcu_settings_flags - & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); - otp_settings->verify_secure_boot_certificate = - (mcu_settings_flags - & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); - otp_settings->enable_anti_rollback = - (mcu_settings_flags - & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); - otp_settings->secure_boot_page_lock_narrow = - (mcu_settings_flags - & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); - otp_settings->secure_boot_page_lock_full = - (mcu_settings_flags - & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); - - return SL_STATUS_OK; -} -#endif - -#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/***************************************************************************//** - * Writes data to User Data section in MTP. Write data must be aligned to - * word size and contain a number of bytes that is divisable by four. - ******************************************************************************/ -sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, - uint32_t offset, - void *data, - uint32_t num_bytes) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - if (data == NULL && num_bytes > 0UL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Setup SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(data, num_bytes); - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_WRITE_USER_DATA); - SE_addDataInput(se_cmd, &in_data); - - SE_addParameter(se_cmd, offset); - SE_addParameter(se_cmd, num_bytes); - - // Execute and wait - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Erases User Data section in MTP. - ******************************************************************************/ -sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ERASE_USER_DATA); - - SE_addParameter(se_cmd, SLI_SE_COMMAND_OPTION_ERASE_UD); - - // Execute and wait. - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Returns the current boot status, versions and system configuration. - ******************************************************************************/ -sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, - sl_se_status_t *status) -{ - if (cmd_ctx == NULL || status == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - volatile uint32_t output[9] = { 0 }; - SE_Command_t *se_cmd = &cmd_ctx->command; - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_STATUS); - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, 4 * 9); - - SE_addDataOutput(se_cmd, &out_data); - - sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); - - if (ret == SL_STATUS_OK) { - // Tamper status - status->tamper_status = output[0]; - status->tamper_status_raw = output[2]; - - // Update status object - status->boot_status = output[4]; - status->se_fw_version = output[5]; - status->host_fw_version = output[6]; - - // Decode debug status - decode_debug_status(&status->debug_status, output[7]); - - // Decode secure boot mode - status->secure_boot_enabled = - ((output[8] & 0x1U) && ((output[8] & ~0x1U) == 0)); - -#if (_SILICON_LABS_32B_SERIES_2_CONFIG < 3) - uint32_t active_mode_shift = 16; -#else - uint32_t active_mode_shift = 8; -#endif - status->active_mode_enabled = - (status->boot_status >> active_mode_shift) & 0x1; - } - - return ret; -} - -/***************************************************************************//** - * Read the serial number of the SE module. - ******************************************************************************/ -sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, - void *serial) -{ - if (cmd_ctx == NULL || serial == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_SERIAL); - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(serial, 16); - - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read the OTP firmware version of the SE module. - ******************************************************************************/ -sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, - uint32_t *version) -{ - if (cmd_ctx == NULL || version == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_OTP_VERSION); - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); - - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) -/***************************************************************************//** - * Read the EMU->RSTCAUSE after a tamper reset. This function should be called - * if EMU->RSTCAUSE has been cleared upon boot. - ******************************************************************************/ -sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, - uint32_t *reset_cause) -{ - if (cmd_ctx == NULL || reset_cause == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_READ_RSTCAUSE); - SE_DataTransfer_t out_data = - SE_DATATRANSFER_DEFAULT(reset_cause, sizeof(uint32_t)); - SE_addDataOutput(se_cmd, &out_data); - return sli_se_execute_and_wait(cmd_ctx); -} -#endif // SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE - -#if defined(SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE) -/***************************************************************************//** - * Read the cached value of the EMU->TAMPERRSTCAUSE register after a tamper - * reset. This function should be called if EMU->TAMPERRSTCAUSE has been cleared - * upon boot. - ******************************************************************************/ -sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, - bool *was_tamper_reset, - uint32_t *reset_cause) -{ - if (cmd_ctx == NULL || reset_cause == NULL || was_tamper_reset == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Use a local cache to convert from bitfield to integer - uint32_t tamper_cause_ret = 0; - - // SE command structures - SE_Command_t *se_cmd = &cmd_ctx->command; - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE); - SE_DataTransfer_t out_data = - SE_DATATRANSFER_DEFAULT(&tamper_cause_ret, sizeof(uint32_t)); - SE_addDataOutput(se_cmd, &out_data); - sl_status_t status = sli_se_execute_and_wait(cmd_ctx); - if (status != SL_STATUS_OK) { - return status; - } - - // Update indication if the reset was because of a tamper event or not. - *was_tamper_reset = tamper_cause_ret > 0 ? true : false; - - // If there is a tamper cause the returned value(tamper_cause_ret) has a - // single bit set at the position of the tamper cause. - // Find the position of the set bit and return it. - uint32_t set_bit_position = 0; - while (tamper_cause_ret > 1) { - tamper_cause_ret >>= 1; - set_bit_position++; - } - - *reset_cause = set_bit_position; - return status; -} -#endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE - -/***************************************************************************//** - * Enables the secure debug functionality. - ******************************************************************************/ -sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_ENABLE_SECURE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Disables the secure debug functionality. - ******************************************************************************/ -sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_DISABLE_SECURE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Set options on the debug interface. - ******************************************************************************/ -sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, - const sl_se_debug_options_t *debug_options) -{ - if (cmd_ctx == NULL || debug_options == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t restriction_bits = 0x0; - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_SET_RESTRICTIONS); - - /// Encode restricted debug options parameter. - restriction_bits |= debug_options->non_secure_invasive_debug ? 0 : 1UL << 0; - restriction_bits |= debug_options->non_secure_non_invasive_debug ? 0 : 1UL << 1; - restriction_bits |= debug_options->secure_invasive_debug ? 0 : 1UL << 2; - restriction_bits |= debug_options->secure_non_invasive_debug ? 0 : 1UL << 3; - - SE_addParameter(se_cmd, restriction_bits); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Performs a device mass erase and debug unlock. - ******************************************************************************/ -sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DEVICE_ERASE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Disabled device erase functionality. - ******************************************************************************/ -sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DEVICE_ERASE_DISABLE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Request challenge from SE which can be used to open debug access. - ******************************************************************************/ -sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, - sl_se_challenge_t challenge) -{ - if (cmd_ctx == NULL || challenge == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - SE_DataTransfer_t out_data = - SE_DATATRANSFER_DEFAULT(challenge, sizeof(sl_se_challenge_t)); - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_CHALLENGE); - - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Invalidate current challenge and make a new challenge. - ******************************************************************************/ -sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx) -{ - sl_se_challenge_t new_challenge; - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_DataTransfer_t out_data = - SE_DATATRANSFER_DEFAULT(new_challenge, sizeof(sl_se_challenge_t)); - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ROLL_CHALLENGE); - SE_addDataOutput(&cmd_ctx->command, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Unlock debug access using certificate signed with challenge. - ******************************************************************************/ -sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, - void *cert, uint32_t len, - const sl_se_debug_options_t *debug_options) -{ - if (cmd_ctx == NULL || cert == NULL || debug_options == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cert, len); - uint32_t unlock_bits = 1UL << 1; // Always request to unlock debug access port - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_OPEN_DEBUG); - - SE_addDataInput(se_cmd, &in_data); - - /** Encode parameter that holds debug options to unlock. */ - unlock_bits |= debug_options->non_secure_invasive_debug ? 1UL << 2 : 0; - unlock_bits |= debug_options->non_secure_non_invasive_debug ? 1UL << 3 : 0; - unlock_bits |= debug_options->secure_invasive_debug ? 1UL << 4 : 0; - unlock_bits |= debug_options->secure_non_invasive_debug ? 1UL << 5 : 0; - - SE_addParameter(se_cmd, unlock_bits); - - return sli_se_execute_and_wait(cmd_ctx); -} - -#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) -/***************************************************************************//** - * Temporarily disable tamper configuration using certificate signed with - * challenge. - ******************************************************************************/ -sl_status_t sl_se_disable_tamper(sl_se_command_context_t *cmd_ctx, - void *cert, - uint32_t len, - sl_se_tamper_signals_t tamper_signals) -{ - if (cmd_ctx == NULL || cert == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - SE_Command_t *se_cmd = &cmd_ctx->command; - SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cert, len); - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DISABLE_TAMPER); - - SE_addDataInput(se_cmd, &in_data); - - SE_addParameter(se_cmd, tamper_signals); - - return sli_se_execute_and_wait(cmd_ctx); -} - -#endif - -/***************************************************************************//** - * Read size of stored certificates in SE. - ******************************************************************************/ -sl_status_t sl_se_read_cert_size(sl_se_command_context_t *cmd_ctx, - sl_se_cert_size_type_t *cert_size) -{ - if (cmd_ctx == NULL || cert_size == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - SE_Command_t *se_cmd = &cmd_ctx->command; - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_USER_CERT_SIZE); - - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(cert_size, 12UL); - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Read stored certificates in SE. - ******************************************************************************/ -sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, - sl_se_cert_type_t cert_type, - void *cert, - uint32_t num_bytes) -{ - if (cmd_ctx == NULL || cert == NULL || num_bytes == 0UL) { - return SL_STATUS_INVALID_PARAMETER; - } - SE_Command_t *se_cmd = &cmd_ctx->command; - uint32_t se_cert_type; - - switch (cert_type) { - case SL_SE_CERT_BATCH: - se_cert_type = SLI_SE_COMMAND_CERT_BATCH; - break; - - case SL_SE_CERT_DEVICE_SE: - se_cert_type = SLI_SE_COMMAND_CERT_SE; - break; - - case SL_SE_CERT_DEVICE_HOST: - se_cert_type = SLI_SE_COMMAND_CERT_HOST; - break; - - default: - return SL_STATUS_INVALID_PARAMETER; - break; - } - - // SE command structures - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_USER_CERT | se_cert_type); - -#if SLI_MINIMUM_REQUIRED_NUMBER_PARAMS == 1 - // One parameter is required, but has no effect - SE_addParameter(se_cmd, 0); -#endif - - SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(cert, num_bytes); - SE_addDataOutput(se_cmd, &out_data); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Enter active mode. - ******************************************************************************/ -sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ENTER_ACTIVE_MODE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -/***************************************************************************//** - * Exit active mode. - ******************************************************************************/ -sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx) -{ - if (cmd_ctx == NULL) { - return SL_STATUS_INVALID_PARAMETER; - } - - sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_EXIT_ACTIVE_MODE); - - return sli_se_execute_and_wait(cmd_ctx); -} - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) - -/// @} (end addtogroup sl_se) - -#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +/***************************************************************************//** + * @file + * @brief Silicon Labs Secure Engine Manager API. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_se_manager_util.h" + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +#include "sli_se_manager_internal.h" +#include "em_se.h" +#include "sl_assert.h" + +#if defined(SLI_SE_MAJOR_VERSION_ONE) + #include "em_system.h" +#endif + +/// @addtogroup sl_se_manager +/// @{ + +// ----------------------------------------------------------------------------- +// Defines + +// OTP initialization structure defines. +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE (1 << 16) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE (1 << 17) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK (1 << 18) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW (1 << 19) +#define SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL (1 << 20) + +// ----------------------------------------------------------------------------- +// Local Functions + +/***************************************************************************//** + * @brief + * Decode debug status word (as received from the SE). + * + * @return N/A + ******************************************************************************/ +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) +static void decode_debug_status(sl_se_debug_status_t *debug_status, + uint32_t status_word) +{ + debug_status->debug_port_lock_applied = status_word & (1 << 0); + debug_status->device_erase_enabled = status_word & (1 << 1); + debug_status->secure_debug_enabled = status_word & (1 << 2); + debug_status->debug_port_lock_state = status_word & (1 << 5); + debug_status->options_state.non_secure_invasive_debug = + (status_word & (1 << 6)) == 0; + debug_status->options_state.non_secure_non_invasive_debug = + (status_word & (1 << 7)) == 0; + debug_status->options_state.secure_invasive_debug = + (status_word & (1 << 8)) == 0; + debug_status->options_state.secure_non_invasive_debug = + (status_word & (1 << 9)) == 0; + debug_status->options_config.non_secure_invasive_debug = + (status_word & (1 << 10)) == 0; + debug_status->options_config.non_secure_non_invasive_debug = + (status_word & (1 << 11)) == 0; + debug_status->options_config.secure_invasive_debug = + (status_word & (1 << 12)) == 0; + debug_status->options_config.secure_non_invasive_debug = + (status_word & (1 << 13)) == 0; +} +#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) +static void decode_debug_status(sl_se_debug_status_t *debug_status, + uint32_t status_word) +{ + debug_status->debug_port_lock_applied = status_word & (1 << 10); + debug_status->device_erase_enabled = status_word & (1 << 11); + debug_status->secure_debug_enabled = status_word & (1 << 12); + debug_status->debug_port_lock_state = status_word & (1 << 15); +} +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +// ----------------------------------------------------------------------------- +// Global Functions + +/***************************************************************************//** + * Validate SE firmware image. + ******************************************************************************/ +sl_status_t sl_se_check_se_image(sl_se_command_context_t *cmd_ctx, + void *image_addr) +{ + if (cmd_ctx == NULL || image_addr == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHECK_SE_IMAGE); + + SE_addParameter(se_cmd, (uint32_t)image_addr); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Apply SE firmware image. + ******************************************************************************/ +sl_status_t sl_se_apply_se_image(sl_se_command_context_t *cmd_ctx, + void *image_addr) +{ + if (cmd_ctx == NULL || image_addr == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_APPLY_SE_IMAGE); + + SE_addParameter(se_cmd, (uint32_t)image_addr); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Get upgrade status of SE firmware image. + ******************************************************************************/ +sl_status_t sl_se_get_upgrade_status_se_image(sl_se_command_context_t *cmd_ctx, + uint32_t *status, + uint32_t *prev_version) +{ + if (cmd_ctx == NULL || status == NULL || prev_version == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_SE_IMAGE); + + volatile uint32_t out_buf[2]; + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(out_buf, + sizeof(out_buf)); + SE_addDataOutput(se_cmd, &out_data); + + sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + *status = out_buf[0]; + *prev_version = out_buf[1]; + } + + return ret; +} + +/***************************************************************************//** + * Validate Host firmware image. + ******************************************************************************/ +sl_status_t sl_se_check_host_image(sl_se_command_context_t *cmd_ctx, + void *image_addr, + uint32_t size) +{ + if (cmd_ctx == NULL || image_addr == NULL || size == 0UL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_CHECK_HOST_IMAGE); + + SE_addParameter(se_cmd, (uint32_t)image_addr); + SE_addParameter(se_cmd, size); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Apply Host firmware image. + ******************************************************************************/ +sl_status_t sl_se_apply_host_image(sl_se_command_context_t *cmd_ctx, + void *image_addr, + uint32_t size) +{ + if (cmd_ctx == NULL || image_addr == NULL || size == 0UL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_APPLY_HOST_IMAGE); + + SE_addParameter(se_cmd, (uint32_t)image_addr); + SE_addParameter(se_cmd, size); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Get upgrade status of Host firmware image. + ******************************************************************************/ +sl_status_t +sl_se_get_upgrade_status_host_image(sl_se_command_context_t *cmd_ctx, + uint32_t *status, + uint32_t *prev_version) +{ + if (cmd_ctx == NULL || status == NULL || prev_version == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_HOST_IMAGE); + + volatile uint32_t out_buf[2]; + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(out_buf, + sizeof(out_buf)); + SE_addDataOutput(se_cmd, &out_data); + + sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + *status = out_buf[0]; + *prev_version = out_buf[1]; + } + + return ret; +} + +/***************************************************************************//** + * Initialize key to be stored in the SE OTP flash. + ******************************************************************************/ +sl_status_t sl_se_init_otp_key(sl_se_command_context_t *cmd_ctx, + sl_se_device_key_type_t key_type, + void *key, + uint32_t num_bytes) +{ + if (cmd_ctx == NULL || key == NULL || num_bytes == 0UL || (size_t)key & 3U) { + return SL_STATUS_INVALID_PARAMETER; + } + + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + if (key_type == SL_SE_KEY_TYPE_IMMUTABLE_AES_128) { + if (num_bytes != 16UL) { + return SL_STATUS_INVALID_PARAMETER; + } + } else { + if (num_bytes != 64UL) { + return SL_STATUS_INVALID_PARAMETER; + } + } + #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + if (num_bytes != 64UL) { + return SL_STATUS_INVALID_PARAMETER; + } + #endif + + uint32_t command_word; + SE_Command_t *se_cmd = &cmd_ctx->command; + + uint32_t se_key_type; + switch (key_type) { + case SL_SE_KEY_TYPE_IMMUTABLE_BOOT: + se_key_type = SLI_SE_KEY_TYPE_BOOT; + break; + + case SL_SE_KEY_TYPE_IMMUTABLE_AUTH: + se_key_type = SLI_SE_KEY_TYPE_AUTH; + break; + + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + case SL_SE_KEY_TYPE_IMMUTABLE_AES_128: + se_key_type = SLI_SE_IMMUTABLE_KEY_TYPE_AES_128; + break; + #endif // SLI_MAILBOX_COMMAND_SUPPORTED + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + + // Find parity word + volatile uint32_t parity = 0; + for (size_t i = 0; i < num_bytes / 4; i++) { + parity = parity ^ ((uint32_t *)key)[i]; + } + + // SE command structures + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + command_word = key_type == SL_SE_KEY_TYPE_IMMUTABLE_AES_128 + ? SLI_SE_COMMAND_INIT_AES_128_KEY : SLI_SE_COMMAND_INIT_PUBKEY; + #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + command_word = SLI_SE_COMMAND_INIT_PUBKEY; + #endif + + sli_se_command_init(cmd_ctx, (command_word | se_key_type)); + + SE_DataTransfer_t parity_data = SE_DATATRANSFER_DEFAULT(&parity, 4); + SE_addDataInput(se_cmd, &parity_data); + + SE_DataTransfer_t key_data = SE_DATATRANSFER_DEFAULT(key, num_bytes); + SE_addDataInput(se_cmd, &key_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read a public key stored in the SE. + ******************************************************************************/ +sl_status_t sl_se_read_pubkey(sl_se_command_context_t *cmd_ctx, + sl_se_device_key_type_t key_type, + void *key, + uint32_t num_bytes) +{ + if (cmd_ctx == NULL || key == NULL || num_bytes != 64UL || (size_t)key & 3U) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t se_key_type; + uint32_t command_word = SLI_SE_COMMAND_READ_PUBKEY; + switch (key_type) { + case SL_SE_KEY_TYPE_IMMUTABLE_BOOT: + se_key_type = SLI_SE_KEY_TYPE_BOOT; + break; + + case SL_SE_KEY_TYPE_IMMUTABLE_AUTH: + se_key_type = SLI_SE_KEY_TYPE_AUTH; + break; + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + case SL_SE_KEY_TYPE_IMMUTABLE_SE_ATTESTATION: + command_word = command_word & ~0x1; + // Intentional fallthrough + case SL_SE_KEY_TYPE_IMMUTABLE_ATTESTATION: + se_key_type = SLI_SE_KEY_TYPE_ATTEST; + break; + #endif // _SILICON_LABS_SECURITY_FEATURE_VAULT + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + + // SE command structures + sli_se_command_init(cmd_ctx, command_word | se_key_type); + + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(key, num_bytes); + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read the SE firmware version. + ******************************************************************************/ +sl_status_t sl_se_get_se_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version) +{ + if (cmd_ctx == NULL || version == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_SE_VERSION); + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); + + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); + + #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + + sl_status_t status = SL_STATUS_OK; + SE_Response_t command_response; + + // Try to acquire SE lock. + // Need to protect VSE mailbox from being written by e.g. SE_ackCommand() + status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Read SE version from VSE mailbox. + command_response = SE_getVersion(version); + + // Release SE lock + status = sli_se_lock_release(); + + // Return sl_status_t code. + if (command_response == SLI_SE_RESPONSE_OK) { + return status; + } else { + // Convert from SE_Response_t to sl_status_t code and return. + return sli_se_to_sl_status(command_response); + } + + #endif +} + +/***************************************************************************//** + * Enables the debug lock for the part. + ******************************************************************************/ +sl_status_t sl_se_apply_debug_lock(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_APPLY); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Returns the current debug lock configuration. + ******************************************************************************/ +sl_status_t sl_se_get_debug_lock_status(sl_se_command_context_t *cmd_ctx, + sl_se_debug_status_t *debug_status) +{ + if (cmd_ctx == NULL || debug_status == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + #if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + SE_Command_t *se_cmd = &cmd_ctx->command; + volatile uint32_t status_word = 0; + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(&status_word, 4); + + // Initialize SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_STATUS); + SE_addDataOutput(se_cmd, &out_data); + + sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + decode_debug_status(debug_status, status_word); + } + + return ret; + #elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + uint32_t vse_version = 0; + uint32_t debug_lock_flags = 0; + + // Try to acquire SE lock + sl_status_t status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + // Read SE version from VSE mailbox. + SE_Response_t vse_mbx_status = SE_getVersion(&vse_version); + + // Reading debug lock status is not supported on VSE with versions <= 1.2.2. + if ((vse_version <= 0x1010202UL) || (vse_mbx_status != SE_RESPONSE_OK)) { + sli_se_lock_release(); + return SL_STATUS_COMMAND_IS_INVALID; + } + + vse_mbx_status = SE_getConfigStatusBits(&debug_lock_flags); + // Release SE lock + status = sli_se_lock_release(); + + if (vse_mbx_status != SE_RESPONSE_OK) { + return sli_se_to_sl_status(vse_mbx_status); + } else if (status != SL_STATUS_OK) { + return status; + } + + decode_debug_status(debug_status, debug_lock_flags); + + return SL_STATUS_OK; + #endif +} + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/***************************************************************************//** + * Initialize SE OTP configuration. + ******************************************************************************/ +sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_init) +{ + if (cmd_ctx == NULL || otp_init == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t mcu_settings_flags = 0; + + sl_status_t status; + + if (otp_init->enable_secure_boot) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; + + // Check for installed boot pubkey before OTP initialization + uint8_t pubkey[64]; + status = + sl_se_read_pubkey(cmd_ctx, SL_SE_KEY_TYPE_IMMUTABLE_BOOT, &pubkey, 64); + if (status != SL_STATUS_OK) { + return SL_STATUS_ABORT; + } + } + if (otp_init->verify_secure_boot_certificate) { + mcu_settings_flags |= + SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; + } + if (otp_init->enable_anti_rollback) { + // Verify firmware compatibility before enabling anti-rollback + #if defined(SLI_SE_MAJOR_VERSION_ONE) + uint16_t part_number = SYSTEM_GetPartNumber(); + if (part_number == 1010 || part_number == 1020) { + if (SYSTEM_GetProdRev() < 16) { + sl_se_status_t se_status; + status = sl_se_get_status(cmd_ctx, &se_status); + if ((status != SL_STATUS_OK) + || (se_status.se_fw_version < 0x00010201)) { + // If the following error is returned, the SE firmware version + // needs to be upgraded to v1.2.1 or higher before enabling + // anti-rollback. + EFM_ASSERT(false); + return SL_STATUS_ABORT; + } + } + } + #endif + + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; + } + if (otp_init->secure_boot_page_lock_narrow) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; + } + if (otp_init->secure_boot_page_lock_full) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; + } + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + static struct { + uint8_t levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS / 2]; + uint8_t period; + uint8_t threshold; + uint8_t flags; + uint8_t reset_threshold; + } otp_tamper_settings; + + // Check for reserved sources + if ((otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_1] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_2] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_3] != SL_SE_TAMPER_LEVEL_IGNORE) + || (otp_init->tamper_levels[SL_SE_TAMPER_SIGNAL_RESERVED_4] != SL_SE_TAMPER_LEVEL_IGNORE)) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Combine tamper levels, two per byte + for (size_t i = 0; i < SL_SE_TAMPER_SIGNAL_NUM_SIGNALS; i += 2) { + // Check for reserved levels + for (size_t offset = 0; offset < 2; ++offset) { + switch (otp_init->tamper_levels[i + offset]) { + case SL_SE_TAMPER_LEVEL_IGNORE: + case SL_SE_TAMPER_LEVEL_INTERRUPT: + case SL_SE_TAMPER_LEVEL_FILTER: + case SL_SE_TAMPER_LEVEL_RESET: + case SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP: + break; + default: + return SL_STATUS_INVALID_PARAMETER; + } + } + + otp_tamper_settings.levels[i / 2] = (otp_init->tamper_levels[i] & 0x7) + | ((otp_init->tamper_levels[i + 1] & 0x7) << 4); + } + // Limit period and threshold input + otp_tamper_settings.period = otp_init->tamper_filter_period & 0x1f; + otp_tamper_settings.threshold = otp_init->tamper_filter_threshold & 0x7; + + #if !defined(SLI_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_AVAILABLE) + if ((otp_init->tamper_flags & SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP) + == SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP) { + return SL_STATUS_INVALID_PARAMETER; + } + #endif + otp_tamper_settings.flags = otp_init->tamper_flags; + otp_tamper_settings.reset_threshold = otp_init->tamper_reset_threshold; + #else + static struct otp_tamper_settings { + uint8_t reserved1[16]; + uint8_t reserved2[2]; + uint8_t reserved3[2]; + } otp_tamper_settings = { + { 0x00 }, + { 0xFF, 0xFF }, + { 0x00 } + }; + #endif + + // Find parity word + volatile uint32_t parity = 0; + parity = parity ^ mcu_settings_flags; + for (size_t i = 0; i < 5; i++) { + parity = parity ^ ((uint32_t*)(&otp_tamper_settings))[i]; + } + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_INIT_OTP); + + volatile uint32_t parameters[2] = { + parity, + sizeof(mcu_settings_flags) + + sizeof(otp_tamper_settings) + }; + SE_DataTransfer_t parameters_data = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(se_cmd, ¶meters_data); + + SE_DataTransfer_t mcu_settings_flags_data = + SE_DATATRANSFER_DEFAULT((volatile void *)&mcu_settings_flags, sizeof(mcu_settings_flags)); + SE_addDataInput(se_cmd, &mcu_settings_flags_data); + + SE_DataTransfer_t tamper_settings_data = + SE_DATATRANSFER_DEFAULT((volatile void *)&otp_tamper_settings, sizeof(otp_tamper_settings)); + SE_addDataInput(se_cmd, &tamper_settings_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read SE OTP configuration. + ******************************************************************************/ +sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_settings) +{ + if (cmd_ctx == NULL || otp_settings == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + sl_status_t status; + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + volatile struct { + uint32_t mcu_settings_flags; + uint8_t levels[SL_SE_TAMPER_SIGNAL_NUM_SIGNALS / 2]; + uint8_t period; + uint8_t threshold; + uint8_t flags; + uint8_t reset_threshold; + } otp_raw; + #else + volatile struct { + uint32_t mcu_settings_flags; + uint8_t reserved1[16]; + uint8_t reserved2[2]; + uint8_t reserved3[2]; + } otp_raw; + #endif + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_OTP); + + SE_DataTransfer_t otp_raw_data = + SE_DATATRANSFER_DEFAULT(&otp_raw, sizeof(otp_raw)); + SE_addDataOutput(se_cmd, &otp_raw_data); + + status = sli_se_execute_and_wait(cmd_ctx); + + if (status != SL_STATUS_OK) { + return status; + } + + otp_settings->enable_secure_boot = + (otp_raw.mcu_settings_flags + & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE); + otp_settings->verify_secure_boot_certificate = + (otp_raw.mcu_settings_flags + & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE); + otp_settings->enable_anti_rollback = + (otp_raw.mcu_settings_flags + & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK); + otp_settings->secure_boot_page_lock_narrow = + (otp_raw.mcu_settings_flags + & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW); + otp_settings->secure_boot_page_lock_full = + (otp_raw.mcu_settings_flags + & SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL); + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + // Split levels + for (size_t i = 0; i < sizeof(otp_raw.levels); i++) { + otp_settings->tamper_levels[2 * i] = (otp_raw.levels[i]) & 0x7; + otp_settings->tamper_levels[2 * i + 1] = (otp_raw.levels[i] >> 4) & 0x7; + } + + otp_settings->tamper_filter_period = otp_raw.period; + otp_settings->tamper_filter_threshold = otp_raw.threshold; + + otp_settings->tamper_flags = otp_raw.flags; + otp_settings->tamper_reset_threshold = otp_raw.reset_threshold; + #endif + + return SL_STATUS_OK; +} + +#elif defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) + +sl_status_t sl_se_init_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_init) +{ + if (cmd_ctx == NULL || otp_init == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + volatile uint32_t mcu_settings_flags = 0; + + if (otp_init->enable_secure_boot) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE; + } + if (otp_init->verify_secure_boot_certificate) { + mcu_settings_flags |= + SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE; + } + if (otp_init->enable_anti_rollback) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK; + } + if (otp_init->secure_boot_page_lock_narrow) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW; + } + if (otp_init->secure_boot_page_lock_full) { + mcu_settings_flags |= SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL; + } + + // Find parity word + uint32_t parity = 0; + parity = parity ^ mcu_settings_flags; + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_INIT_OTP); + + volatile uint32_t parameters[2] = { + parity, + sizeof(mcu_settings_flags) + }; + SE_DataTransfer_t parameters_data = SE_DATATRANSFER_DEFAULT(¶meters, 8); + SE_addDataInput(se_cmd, ¶meters_data); + + SE_DataTransfer_t mcu_settings_flags_data = + SE_DATATRANSFER_DEFAULT(&mcu_settings_flags, sizeof(mcu_settings_flags)); + SE_addDataInput(se_cmd, &mcu_settings_flags_data); + + SE_executeCommand(se_cmd); + return SL_STATUS_FAIL; // Should never get to this point +} + +/***************************************************************************//** + * Read the OTP firmware version of the SE module. + ******************************************************************************/ +sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version) +{ + if (cmd_ctx == NULL || version == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + sl_status_t lock_status = sli_se_lock_acquire(); + if (lock_status != SL_STATUS_OK) { + return lock_status; + } + + SE_Response_t otp_status = SE_getOTPVersion(version); + + // Release SE lock + sli_se_lock_release(); + + if (otp_status == SE_RESPONSE_OK) { + return SL_STATUS_OK; + } + + return SL_STATUS_NOT_SUPPORTED; +} + +sl_status_t sl_se_read_otp(sl_se_command_context_t *cmd_ctx, + sl_se_otp_init_t *otp_settings) +{ + if (cmd_ctx == NULL || otp_settings == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Try to acquire SE lock + sl_status_t status = sli_se_lock_acquire(); + if (status != SL_STATUS_OK) { + return status; + } + + uint32_t mcu_settings_flags = 0; + SE_Response_t vse_mbx_status = SE_getConfigStatusBits(&mcu_settings_flags); + + // Release SE lock + status = sli_se_lock_release(); + + if (vse_mbx_status != SE_RESPONSE_OK) { + return sli_se_to_sl_status(vse_mbx_status); + } else if (status != SL_STATUS_OK) { + return status; + } + + otp_settings->enable_secure_boot = + (mcu_settings_flags + & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ENABLE >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); + otp_settings->verify_secure_boot_certificate = + (mcu_settings_flags + & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_VERIFY_CERTIFICATE >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); + otp_settings->enable_anti_rollback = + (mcu_settings_flags + & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_ANTI_ROLLBACK >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); + otp_settings->secure_boot_page_lock_narrow = + (mcu_settings_flags + & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_NARROW >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); + otp_settings->secure_boot_page_lock_full = + (mcu_settings_flags + & (SE_OTP_MCU_SETTINGS_FLAG_SECURE_BOOT_PAGE_LOCK_FULL >> SL_SE_ROOT_CONFIG_MCU_SETTINGS_SHIFT)); + + return SL_STATUS_OK; +} +#endif + +#if defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/***************************************************************************//** + * Writes data to User Data section in MTP. Write data must be aligned to + * word size and contain a number of bytes that is divisable by four. + ******************************************************************************/ +sl_status_t sl_se_write_user_data(sl_se_command_context_t *cmd_ctx, + uint32_t offset, + void *data, + uint32_t num_bytes) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + if (data == NULL && num_bytes > 0UL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Setup SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(data, num_bytes); + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_WRITE_USER_DATA); + SE_addDataInput(se_cmd, &in_data); + + SE_addParameter(se_cmd, offset); + SE_addParameter(se_cmd, num_bytes); + + // Execute and wait + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Erases User Data section in MTP. + ******************************************************************************/ +sl_status_t sl_se_erase_user_data(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ERASE_USER_DATA); + + SE_addParameter(se_cmd, SLI_SE_COMMAND_OPTION_ERASE_UD); + + // Execute and wait. + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Returns the current boot status, versions and system configuration. + ******************************************************************************/ +sl_status_t sl_se_get_status(sl_se_command_context_t *cmd_ctx, + sl_se_status_t *status) +{ + if (cmd_ctx == NULL || status == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + volatile uint32_t output[9] = { 0 }; + SE_Command_t *se_cmd = &cmd_ctx->command; + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_STATUS); + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(output, 4 * 9); + + SE_addDataOutput(se_cmd, &out_data); + + sl_status_t ret = sli_se_execute_and_wait(cmd_ctx); + + if (ret == SL_STATUS_OK) { + // Tamper status + status->tamper_status = output[0]; + status->tamper_status_raw = output[2]; + + // Update status object + status->boot_status = output[4]; + status->se_fw_version = output[5]; + status->host_fw_version = output[6]; + + // Decode debug status + decode_debug_status(&status->debug_status, output[7]); + + // Decode secure boot mode + status->secure_boot_enabled = + ((output[8] & 0x1U) && ((output[8] & ~0x1U) == 0)); + +#if (_SILICON_LABS_32B_SERIES_2_CONFIG < 3) + uint32_t active_mode_shift = 16; +#else + uint32_t active_mode_shift = 8; +#endif + status->active_mode_enabled = + (status->boot_status >> active_mode_shift) & 0x1; + } + + return ret; +} + +/***************************************************************************//** + * Read the serial number of the SE module. + ******************************************************************************/ +sl_status_t sl_se_get_serialnumber(sl_se_command_context_t *cmd_ctx, + void *serial) +{ + if (cmd_ctx == NULL || serial == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_SERIAL); + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(serial, 16); + + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read the OTP firmware version of the SE module. + ******************************************************************************/ +sl_status_t sl_se_get_otp_version(sl_se_command_context_t *cmd_ctx, + uint32_t *version) +{ + if (cmd_ctx == NULL || version == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_OTP_VERSION); + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(version, sizeof(uint32_t)); + + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#if defined(SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE) +/***************************************************************************//** + * Read the EMU->RSTCAUSE after a tamper reset. This function should be called + * if EMU->RSTCAUSE has been cleared upon boot. + ******************************************************************************/ +sl_status_t sl_se_get_reset_cause(sl_se_command_context_t *cmd_ctx, + uint32_t *reset_cause) +{ + if (cmd_ctx == NULL || reset_cause == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_STATUS_READ_RSTCAUSE); + SE_DataTransfer_t out_data = + SE_DATATRANSFER_DEFAULT(reset_cause, sizeof(uint32_t)); + SE_addDataOutput(se_cmd, &out_data); + return sli_se_execute_and_wait(cmd_ctx); +} +#endif // SLI_SE_COMMAND_STATUS_READ_RSTCAUSE_AVAILABLE + +#if defined(SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE) +/***************************************************************************//** + * Read the cached value of the EMU->TAMPERRSTCAUSE register after a tamper + * reset. This function should be called if EMU->TAMPERRSTCAUSE has been cleared + * upon boot. + ******************************************************************************/ +sl_status_t sl_se_get_tamper_reset_cause(sl_se_command_context_t *cmd_ctx, + bool *was_tamper_reset, + uint32_t *reset_cause) +{ + if (cmd_ctx == NULL || reset_cause == NULL || was_tamper_reset == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Use a local cache to convert from bitfield to integer + uint32_t tamper_cause_ret = 0; + + // SE command structures + SE_Command_t *se_cmd = &cmd_ctx->command; + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE); + SE_DataTransfer_t out_data = + SE_DATATRANSFER_DEFAULT(&tamper_cause_ret, sizeof(uint32_t)); + SE_addDataOutput(se_cmd, &out_data); + sl_status_t status = sli_se_execute_and_wait(cmd_ctx); + if (status != SL_STATUS_OK) { + return status; + } + + // Update indication if the reset was because of a tamper event or not. + *was_tamper_reset = tamper_cause_ret > 0 ? true : false; + + // If there is a tamper cause the returned value(tamper_cause_ret) has a + // single bit set at the position of the tamper cause. + // Find the position of the set bit and return it. + uint32_t set_bit_position = 0; + while (tamper_cause_ret > 1) { + tamper_cause_ret >>= 1; + set_bit_position++; + } + + *reset_cause = set_bit_position; + return status; +} +#endif // SLI_SE_COMMAND_READ_TAMPER_RESET_CAUSE_AVAILABLE + +/***************************************************************************//** + * Enables the secure debug functionality. + ******************************************************************************/ +sl_status_t sl_se_enable_secure_debug(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_ENABLE_SECURE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Disables the secure debug functionality. + ******************************************************************************/ +sl_status_t sl_se_disable_secure_debug(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_LOCK_DISABLE_SECURE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Set options on the debug interface. + ******************************************************************************/ +sl_status_t sl_se_set_debug_options(sl_se_command_context_t *cmd_ctx, + const sl_se_debug_options_t *debug_options) +{ + if (cmd_ctx == NULL || debug_options == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t restriction_bits = 0x0; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DBG_SET_RESTRICTIONS); + + /// Encode restricted debug options parameter. + restriction_bits |= debug_options->non_secure_invasive_debug ? 0 : 1UL << 0; + restriction_bits |= debug_options->non_secure_non_invasive_debug ? 0 : 1UL << 1; + restriction_bits |= debug_options->secure_invasive_debug ? 0 : 1UL << 2; + restriction_bits |= debug_options->secure_non_invasive_debug ? 0 : 1UL << 3; + + SE_addParameter(se_cmd, restriction_bits); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Performs a device mass erase and debug unlock. + ******************************************************************************/ +sl_status_t sl_se_erase_device(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DEVICE_ERASE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Disabled device erase functionality. + ******************************************************************************/ +sl_status_t sl_se_disable_device_erase(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DEVICE_ERASE_DISABLE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Request challenge from SE which can be used to open debug access. + ******************************************************************************/ +sl_status_t sl_se_get_challenge(sl_se_command_context_t *cmd_ctx, + sl_se_challenge_t challenge) +{ + if (cmd_ctx == NULL || challenge == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + SE_DataTransfer_t out_data = + SE_DATATRANSFER_DEFAULT(challenge, sizeof(sl_se_challenge_t)); + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_GET_CHALLENGE); + + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Invalidate current challenge and make a new challenge. + ******************************************************************************/ +sl_status_t sl_se_roll_challenge(sl_se_command_context_t *cmd_ctx) +{ + sl_se_challenge_t new_challenge; + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_DataTransfer_t out_data = + SE_DATATRANSFER_DEFAULT(new_challenge, sizeof(sl_se_challenge_t)); + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ROLL_CHALLENGE); + SE_addDataOutput(&cmd_ctx->command, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Unlock debug access using certificate signed with challenge. + ******************************************************************************/ +sl_status_t sl_se_open_debug(sl_se_command_context_t *cmd_ctx, + void *cert, uint32_t len, + const sl_se_debug_options_t *debug_options) +{ + if (cmd_ctx == NULL || cert == NULL || debug_options == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cert, len); + uint32_t unlock_bits = 1UL << 1; // Always request to unlock debug access port + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_OPEN_DEBUG); + + SE_addDataInput(se_cmd, &in_data); + + /** Encode parameter that holds debug options to unlock. */ + unlock_bits |= debug_options->non_secure_invasive_debug ? 1UL << 2 : 0; + unlock_bits |= debug_options->non_secure_non_invasive_debug ? 1UL << 3 : 0; + unlock_bits |= debug_options->secure_invasive_debug ? 1UL << 4 : 0; + unlock_bits |= debug_options->secure_non_invasive_debug ? 1UL << 5 : 0; + + SE_addParameter(se_cmd, unlock_bits); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) +/***************************************************************************//** + * Temporarily disable tamper configuration using certificate signed with + * challenge. + ******************************************************************************/ +sl_status_t sl_se_disable_tamper(sl_se_command_context_t *cmd_ctx, + void *cert, + uint32_t len, + sl_se_tamper_signals_t tamper_signals) +{ + if (cmd_ctx == NULL || cert == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + SE_Command_t *se_cmd = &cmd_ctx->command; + SE_DataTransfer_t in_data = SE_DATATRANSFER_DEFAULT(cert, len); + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_DISABLE_TAMPER); + + SE_addDataInput(se_cmd, &in_data); + + SE_addParameter(se_cmd, tamper_signals); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#endif + +/***************************************************************************//** + * Read size of stored certificates in SE. + ******************************************************************************/ +sl_status_t sl_se_read_cert_size(sl_se_command_context_t *cmd_ctx, + sl_se_cert_size_type_t *cert_size) +{ + if (cmd_ctx == NULL || cert_size == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + SE_Command_t *se_cmd = &cmd_ctx->command; + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_USER_CERT_SIZE); + + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(cert_size, 12UL); + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Read stored certificates in SE. + ******************************************************************************/ +sl_status_t sl_se_read_cert(sl_se_command_context_t *cmd_ctx, + sl_se_cert_type_t cert_type, + void *cert, + uint32_t num_bytes) +{ + if (cmd_ctx == NULL || cert == NULL || num_bytes == 0UL) { + return SL_STATUS_INVALID_PARAMETER; + } + SE_Command_t *se_cmd = &cmd_ctx->command; + uint32_t se_cert_type; + + switch (cert_type) { + case SL_SE_CERT_BATCH: + se_cert_type = SLI_SE_COMMAND_CERT_BATCH; + break; + + case SL_SE_CERT_DEVICE_SE: + se_cert_type = SLI_SE_COMMAND_CERT_SE; + break; + + case SL_SE_CERT_DEVICE_HOST: + se_cert_type = SLI_SE_COMMAND_CERT_HOST; + break; + + default: + return SL_STATUS_INVALID_PARAMETER; + break; + } + + // SE command structures + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_READ_USER_CERT | se_cert_type); + +#if SLI_MINIMUM_REQUIRED_NUMBER_PARAMS == 1 + // One parameter is required, but has no effect + SE_addParameter(se_cmd, 0); +#endif + + SE_DataTransfer_t out_data = SE_DATATRANSFER_DEFAULT(cert, num_bytes); + SE_addDataOutput(se_cmd, &out_data); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Enter active mode. + ******************************************************************************/ +sl_status_t sl_se_enter_active_mode(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_ENTER_ACTIVE_MODE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +/***************************************************************************//** + * Exit active mode. + ******************************************************************************/ +sl_status_t sl_se_exit_active_mode(sl_se_command_context_t *cmd_ctx) +{ + if (cmd_ctx == NULL) { + return SL_STATUS_INVALID_PARAMETER; + } + + sli_se_command_init(cmd_ctx, SLI_SE_COMMAND_EXIT_ACTIVE_MODE); + + return sli_se_execute_and_wait(cmd_ctx); +} + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) + +/// @} (end addtogroup sl_se) + +#endif // defined(SLI_MAILBOX_COMMAND_SUPPORTED) || defined(SLI_VSE_MAILBOX_COMMAND_SUPPORTED) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h index c92b948..fbb4060 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal.h @@ -1,166 +1,166 @@ -/**************************************************************************/ /** - * @file - * @brief OS abstraction layer primitives for the SE Manager - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SE_MANAGER_OSAL_H -#define SE_MANAGER_OSAL_H - -#if !defined(SE_MANAGER_CONFIG_FILE) - #include "sl_se_manager_config.h" -#else - #include SE_MANAGER_CONFIG_FILE -#endif - -#if defined (SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -#include "sl_status.h" - -#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \ - && (defined(SL_SE_MANAGER_THREADING) \ - || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION)) -// Include CMSIS RTOS2 kernel abstraction layer: - #include "sli_se_manager_osal_cmsis_rtos2.h" -#else -// Include bare metal abstraction layer: - #include "sli_se_manager_osal_baremetal.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(SL_SE_MANAGER_THREADING) - -/***************************************************************************//** - * @brief Initialize a given mutex - * - * @param mutex Pointer to the mutex needing initialization - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_init_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Free a given mutex - * - * @param mutex Pointer to the mutex being freed - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_free_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Pend on a mutex - * - * @param mutex Pointer to the mutex being pended on - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_take_mutex(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Try to own a mutex without waiting - * - * @param mutex Pointer to the mutex being tested - * - * @return SL_STATUS_OK on success (= mutex successfully owned), error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_take_mutex_non_blocking(se_manager_osal_mutex_t *mutex); - -/***************************************************************************//** - * @brief Release a mutex - * - * @param mutex Pointer to the mutex being released - * - * @return SL_STATUS_OK on success, error code otherwise. - *****************************************************************************/ -__STATIC_INLINE sl_status_t se_manager_osal_give_mutex(se_manager_osal_mutex_t *mutex); - -#endif // SL_SE_MANAGER_THREADING - -/***************************************************************************//** - * @brief Initialize a completion object. - * - * @param p_comp Pointer to an se_manager_osal_completion_t object allocated - * by the user. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp); - -/***************************************************************************//** - * @brief Free a completion object. - * - * @param p_comp Pointer to an se_manager_osal_completion_t object. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp); - -/***************************************************************************//** - * @brief Wait for completion event. - * - * @param p_comp Pointer to completion object which must be initialized by - * calling se_manager_osal_completion_init before calling this - * function. - * - * @param ticks Ticks to wait for the completion. - * Pass a value of SE_MANAGER_OSAL_WAIT_FOREVER in order to - * wait forever. - * Pass a value of SE_MANAGER_OSAL_NON_BLOCKING in order to - * return immediately. - * - * @return Status code, @ref sl_status.h. Typcally SL_STATUS_OK if success, - * or SL_STATUS_TIMEOUT if no completion within the given ticks. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, - int ticks); - -/***************************************************************************//** - * @brief Signal completion. - * - * @param p_comp Pointer to completion object which must be initialized by - * calling se_manager_osal_completion_init before calling this - * function. - * - * @return Status code, @ref sl_status.h. - *****************************************************************************/ -__STATIC_INLINE sl_status_t -se_manager_osal_complete(se_manager_osal_completion_t *p_comp); - -#ifdef __cplusplus -} -#endif - -#endif // SE_MANAGER_OSAL_H +/**************************************************************************/ /** + * @file + * @brief OS abstraction layer primitives for the SE Manager + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SE_MANAGER_OSAL_H +#define SE_MANAGER_OSAL_H + +#if !defined(SE_MANAGER_CONFIG_FILE) + #include "sl_se_manager_config.h" +#else + #include SE_MANAGER_CONFIG_FILE +#endif + +#if defined (SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#include "sl_status.h" + +#if (defined(SL_CATALOG_MICRIUMOS_KERNEL_PRESENT) || defined(SL_CATALOG_FREERTOS_KERNEL_PRESENT)) \ + && (defined(SL_SE_MANAGER_THREADING) \ + || defined(SL_SE_MANAGER_YIELD_WHILE_WAITING_FOR_COMMAND_COMPLETION)) +// Include CMSIS RTOS2 kernel abstraction layer: + #include "sli_se_manager_osal_cmsis_rtos2.h" +#else +// Include bare metal abstraction layer: + #include "sli_se_manager_osal_baremetal.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(SL_SE_MANAGER_THREADING) + +/***************************************************************************//** + * @brief Initialize a given mutex + * + * @param mutex Pointer to the mutex needing initialization + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t se_manager_osal_init_mutex(se_manager_osal_mutex_t *mutex); + +/***************************************************************************//** + * @brief Free a given mutex + * + * @param mutex Pointer to the mutex being freed + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t se_manager_osal_free_mutex(se_manager_osal_mutex_t *mutex); + +/***************************************************************************//** + * @brief Pend on a mutex + * + * @param mutex Pointer to the mutex being pended on + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t se_manager_osal_take_mutex(se_manager_osal_mutex_t *mutex); + +/***************************************************************************//** + * @brief Try to own a mutex without waiting + * + * @param mutex Pointer to the mutex being tested + * + * @return SL_STATUS_OK on success (= mutex successfully owned), error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t se_manager_osal_take_mutex_non_blocking(se_manager_osal_mutex_t *mutex); + +/***************************************************************************//** + * @brief Release a mutex + * + * @param mutex Pointer to the mutex being released + * + * @return SL_STATUS_OK on success, error code otherwise. + *****************************************************************************/ +__STATIC_INLINE sl_status_t se_manager_osal_give_mutex(se_manager_osal_mutex_t *mutex); + +#endif // SL_SE_MANAGER_THREADING + +/***************************************************************************//** + * @brief Initialize a completion object. + * + * @param p_comp Pointer to an se_manager_osal_completion_t object allocated + * by the user. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp); + +/***************************************************************************//** + * @brief Free a completion object. + * + * @param p_comp Pointer to an se_manager_osal_completion_t object. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp); + +/***************************************************************************//** + * @brief Wait for completion event. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling se_manager_osal_completion_init before calling this + * function. + * + * @param ticks Ticks to wait for the completion. + * Pass a value of SE_MANAGER_OSAL_WAIT_FOREVER in order to + * wait forever. + * Pass a value of SE_MANAGER_OSAL_NON_BLOCKING in order to + * return immediately. + * + * @return Status code, @ref sl_status.h. Typcally SL_STATUS_OK if success, + * or SL_STATUS_TIMEOUT if no completion within the given ticks. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, + int ticks); + +/***************************************************************************//** + * @brief Signal completion. + * + * @param p_comp Pointer to completion object which must be initialized by + * calling se_manager_osal_completion_init before calling this + * function. + * + * @return Status code, @ref sl_status.h. + *****************************************************************************/ +__STATIC_INLINE sl_status_t +se_manager_osal_complete(se_manager_osal_completion_t *p_comp); + +#ifdef __cplusplus +} +#endif + +#endif // SE_MANAGER_OSAL_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h index 2088003..77d7f67 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/se_manager/src/sli_se_manager_osal_baremetal.h @@ -1,136 +1,136 @@ -/**************************************************************************/ /** - * @file - * @brief OS abstraction primitives for the SE Manager for bare metal apps - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SE_MANAGER_OSAL_BAREMETAL_H -#define SE_MANAGER_OSAL_BAREMETAL_H - -#include "sli_se_manager_features.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// ----------------------------------------------------------------------------- -// Defines - -/// In order to wait forever in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_WAIT_FOREVER (-1) -/// In order to return immediately in blocking functions the user can pass the -/// following value. -#define SE_MANAGER_OSAL_NON_BLOCKING (0) - -/// Priority to use for SEMBRX IRQ -#if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY -#else - #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (0) -#endif - -// ----------------------------------------------------------------------------- -// Typedefs - -/// Completion type used to wait for and signal end of operation. -typedef volatile unsigned int se_manager_osal_completion_t; - -/// SE manager mutex definition for Baremetal. -typedef volatile unsigned int se_manager_osal_mutex_t; - -// ----------------------------------------------------------------------------- -// Globals - -#if defined(SE_MANAGER_OSAL_TEST) -/// Global variable to keep track of ticks in bare metal test apps. -extern unsigned int sli_se_manager_test_ticks; -#endif - -// ----------------------------------------------------------------------------- -// Functions - -/// Initialize a completion object. -__STATIC_INLINE -sl_status_t se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp) -{ - *p_comp = 0; - return SL_STATUS_OK; -} - -/// Free a completion object. -__STATIC_INLINE -sl_status_t se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp) -{ - *p_comp = 0; - return SL_STATUS_OK; -} - -/// Wait for completion event. -__STATIC_INLINE sl_status_t -se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, int ticks) -{ - int ret; - if (ticks == SE_MANAGER_OSAL_WAIT_FOREVER) { - while ( *p_comp == 0 ) { -#if defined(SE_MANAGER_OSAL_TEST) - sli_se_manager_test_ticks++; -#endif - } - *p_comp = 0; - ret = 0; - } else { - while ((*p_comp == 0) && (ticks > 0)) { - ticks--; -#if defined(SE_MANAGER_OSAL_TEST) - sli_se_manager_test_ticks++; -#endif - } - if (*p_comp == 1) { - *p_comp = 0; - ret = 0; - } else { - ret = SL_STATUS_TIMEOUT; - } - } - - return ret; -} - -/// Signal completion event. -__STATIC_INLINE -sl_status_t se_manager_osal_complete(se_manager_osal_completion_t* p_comp) -{ - *p_comp = 1; - return SL_STATUS_OK; -} - -#ifdef __cplusplus -} -#endif - -#endif // SE_MANAGER_OSAL_BAREMETAL_H +/**************************************************************************/ /** + * @file + * @brief OS abstraction primitives for the SE Manager for bare metal apps + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SE_MANAGER_OSAL_BAREMETAL_H +#define SE_MANAGER_OSAL_BAREMETAL_H + +#include "sli_se_manager_features.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ----------------------------------------------------------------------------- +// Defines + +/// In order to wait forever in blocking functions the user can pass the +/// following value. +#define SE_MANAGER_OSAL_WAIT_FOREVER (-1) +/// In order to return immediately in blocking functions the user can pass the +/// following value. +#define SE_MANAGER_OSAL_NON_BLOCKING (0) + +/// Priority to use for SEMBRX IRQ +#if defined(SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY) + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY SE_MANAGER_USER_SEMBRX_IRQ_PRIORITY +#else + #define SE_MANAGER_SEMBRX_IRQ_PRIORITY (0) +#endif + +// ----------------------------------------------------------------------------- +// Typedefs + +/// Completion type used to wait for and signal end of operation. +typedef volatile unsigned int se_manager_osal_completion_t; + +/// SE manager mutex definition for Baremetal. +typedef volatile unsigned int se_manager_osal_mutex_t; + +// ----------------------------------------------------------------------------- +// Globals + +#if defined(SE_MANAGER_OSAL_TEST) +/// Global variable to keep track of ticks in bare metal test apps. +extern unsigned int sli_se_manager_test_ticks; +#endif + +// ----------------------------------------------------------------------------- +// Functions + +/// Initialize a completion object. +__STATIC_INLINE +sl_status_t se_manager_osal_init_completion(se_manager_osal_completion_t *p_comp) +{ + *p_comp = 0; + return SL_STATUS_OK; +} + +/// Free a completion object. +__STATIC_INLINE +sl_status_t se_manager_osal_free_completion(se_manager_osal_completion_t *p_comp) +{ + *p_comp = 0; + return SL_STATUS_OK; +} + +/// Wait for completion event. +__STATIC_INLINE sl_status_t +se_manager_osal_wait_completion(se_manager_osal_completion_t *p_comp, int ticks) +{ + int ret; + if (ticks == SE_MANAGER_OSAL_WAIT_FOREVER) { + while ( *p_comp == 0 ) { +#if defined(SE_MANAGER_OSAL_TEST) + sli_se_manager_test_ticks++; +#endif + } + *p_comp = 0; + ret = 0; + } else { + while ((*p_comp == 0) && (ticks > 0)) { + ticks--; +#if defined(SE_MANAGER_OSAL_TEST) + sli_se_manager_test_ticks++; +#endif + } + if (*p_comp == 1) { + *p_comp = 0; + ret = 0; + } else { + ret = SL_STATUS_TIMEOUT; + } + } + + return ret; +} + +/// Signal completion event. +__STATIC_INLINE +sl_status_t se_manager_osal_complete(se_manager_osal_completion_t* p_comp) +{ + *p_comp = 1; + return SL_STATUS_OK; +} + +#ifdef __cplusplus +} +#endif + +#endif // SE_MANAGER_OSAL_BAREMETAL_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/compiler_extentions.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/compiler_extentions.h index a207fd7..81a1423 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/compiler_extentions.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/compiler_extentions.h @@ -1,15 +1,15 @@ -#ifndef COMPILER_EXTENTIONS_H -#define COMPILER_EXTENTIONS_H - -/** @brief Macro extending C99 to force warning when function result is unused. */ -#ifndef CHECK_RESULT -#if defined(__GNUC__) && (__GNUC__ >= 4) -#define CHECK_RESULT __attribute__ ((warn_unused_result)) -#elif defined(_MSC_VER) && (_MSC_VER >= 1700) -#define CHECK_RESULT _Check_return_ -#else -#define CHECK_RESULT -#endif -#endif - +#ifndef COMPILER_EXTENTIONS_H +#define COMPILER_EXTENTIONS_H + +/** @brief Macro extending C99 to force warning when function result is unused. */ +#ifndef CHECK_RESULT +#if defined(__GNUC__) && (__GNUC__ >= 4) +#define CHECK_RESULT __attribute__ ((warn_unused_result)) +#elif defined(_MSC_VER) && (_MSC_VER >= 1700) +#define CHECK_RESULT _Check_return_ +#else +#define CHECK_RESULT +#endif +#endif + #endif \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_def.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_def.h index ca55172..b7712fa 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_def.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_def.h @@ -1,158 +1,158 @@ - -#ifndef CRYPTOLIB_DEF_H -#define CRYPTOLIB_DEF_H - -#include "em_device.h" - -/* Define 'uint8_t', 'uint32_t'... */ -#include - -/* Define 'bool' */ -#include - -/* Define 'NULL' */ -#include - -/* Define 'CHECK_RESULT' macro (from cryptolib) */ -#include "compiler_extentions.h" - -/* Define 'block_t' (from cryptolib) */ -#include "cryptolib_types.h" - -/* Define 'memcpy_*' functions (from cryptolib) */ -#include "sx_memcpy.h" - -/* Define 'memcmp*' functions (from cryptolib) */ -#include "sx_memcmp.h" - -/***************************************************************************** - ** Address map - *****************************************************************************/ - -#ifndef ADDR_CRYPTOWRAP -#define ADDR_CRYPTOWRAP CRYPTOACC_BASE -#endif - -#define ADDR_CRYPTOMASTER_REGS (ADDR_CRYPTOWRAP+0x00000000) -#define ADDR_BA431_REGS (ADDR_CRYPTOWRAP+0x00001000) -#define ADDR_BA414EP_REGS (ADDR_CRYPTOWRAP+0x00002000) -#define ADDR_BA431_FIFO (ADDR_CRYPTOWRAP+0x00004000) -#define ADDR_BA414EP_CRYPTORAM (ADDR_CRYPTOWRAP+0x00008000) -#define ADDR_BA414EP_UCODE (ADDR_CRYPTOWRAP+0x0000C000) - -#define ADDR_INCL_IPS_HW_CFG (ADDR_CRYPTOWRAP+0x00000400) -#define ADDR_BA411E_HW_CFG_1 (ADDR_CRYPTOWRAP+0x00000404) -#define ADDR_BA411E_HW_CFG_2 (ADDR_CRYPTOWRAP+0x00000408) -#define ADDR_BA413_HW_CFG (ADDR_CRYPTOWRAP+0x0000040C) -#define ADDR_BA418_HW_CFG (ADDR_CRYPTOWRAP+0x00000410) -#define ADDR_BA419_HW_CFG (ADDR_CRYPTOWRAP+0x00000414) -#define ADDR_BA424_HW_CFG (ADDR_CRYPTOWRAP+0x00000418) - -/***************************************************************************** - ** Enable polling defines - *****************************************************************************/ - -#define WAIT_CRYPTOMASTER_WITH_REGISTER_POLLING (1) -#define WAIT_RNG_WITH_REGISTER_POLLING (1) -#define WAIT_PK_WITH_REGISTER_POLLING (1) - -/***************************************************************************** - ** Bus error handling - *****************************************************************************/ - -/** @brief Trigger hardfault by access to invalid memory address */ -static inline void trigger_hardfault(void) { - uint32_t *bad_mem_addr = (uint32_t*) 0x3FFFFFFC; - *bad_mem_addr = 1; -} - -#define TRIGGER_HARDFAULT_FCT() trigger_hardfault(); - -/***************************************************************************** - ** Debug - *****************************************************************************/ - -#define DEBUG_ENABLED (1) - -#define CRYPTOLIB_PRINTF(...) {} -#define CRYPTOLIB_ASSERT(cond, msg) {} -#define CRYPTOLIB_ASSERT_NM(cond) {} -#define CRYPTOLIB_ASSERT_VAR(cond, ...) {} - -/***************************************************************************** - ** Crypto DMA - *****************************************************************************/ - -#define BLK_MEMCPY_MIN_DMA_SIZE (16UL) - -/***************************************************************************** - ** Supported algorithms - *****************************************************************************/ - -#define DH_MODP_ENABLED (0) -#define AIS31_ENABLED (1) - -#ifdef _SILICON_LABS_32B_SERIES_2_CONFIG_2 - #define JPAKE_ENABLED (0) -#else - #define JPAKE_ENABLED (1) -#endif - -/***************************************************************************** - ** Max sizes - *****************************************************************************/ - -#define PRIME_MAX_SIZE ((4096 / 8) / 2) -#define ECC_MAX_KEY_SIZE (256/8) -#define DERIV_MAX_SALT_SIZE (512) -#define DERIV_MAX_INFO_SIZE (512) - -/***************************************************************************** - ** RNG settings - *****************************************************************************/ - -// Control subsampling at output of ring oscillators (ring sampling -// frequency = ClkSec frequency / (RNG_CLKDIV+1)). -#define RNG_CLKDIV (7) - -// Number of clock cycles after FIFO being full until TRNG goes to sleep. -// A negative value will keep the ring oscillators always running. -#define RNG_OFF_TIMER_VAL (0) - -// When the FIFO level (number of 128-bit block) becomes smaller or equal -// to RNG_FIFO_WAKEUP_LVL, the TRNG is restarted. -#define RNG_FIFO_WAKEUP_LVL (8) - -// Number of clock cycles to wait after startup before sampling data from -// the noise source. -#define RNG_INIT_WAIT_VAL (512) - -// Number of 128-bit blocks of data from the noise source that are used -// as input to the conditioning function. -#define RNG_NB_128BIT_BLOCKS (8) - -/***************************************************************************** - ** Countermeasures - *****************************************************************************/ - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - #define PK_CM_ENABLED (0) -#else - #define PK_CM_ENABLED (1) -#endif - -#if PK_CM_ENABLED - // PK_CM_RAND_SIZE sets the byte size of the random number that is used for - // side channel countermeasures. Maximum allowable size is dependent on the - // maximum supported curve size: - // * 256 bit: 0 < rand < 2^16 => 2 bytes - // * 521 bit: 0 < rand < 2^23 => still 2 bytes (3 bytes could lead to 2^24-1) - #define PK_CM_RAND_SIZE (2) - - #define PK_CM_RAND_PROJ (1) - #define PK_CM_RAND_SCALAR (1) - #define PK_CM_RAND_MODULUS (0) // Only relevant for RSA/DSA/SRP - #define PK_CM_RAND_EXPONENT (0) // Only relevant for RSA/DSA/SRP -#endif - -#endif + +#ifndef CRYPTOLIB_DEF_H +#define CRYPTOLIB_DEF_H + +#include "em_device.h" + +/* Define 'uint8_t', 'uint32_t'... */ +#include + +/* Define 'bool' */ +#include + +/* Define 'NULL' */ +#include + +/* Define 'CHECK_RESULT' macro (from cryptolib) */ +#include "compiler_extentions.h" + +/* Define 'block_t' (from cryptolib) */ +#include "cryptolib_types.h" + +/* Define 'memcpy_*' functions (from cryptolib) */ +#include "sx_memcpy.h" + +/* Define 'memcmp*' functions (from cryptolib) */ +#include "sx_memcmp.h" + +/***************************************************************************** + ** Address map + *****************************************************************************/ + +#ifndef ADDR_CRYPTOWRAP +#define ADDR_CRYPTOWRAP CRYPTOACC_BASE +#endif + +#define ADDR_CRYPTOMASTER_REGS (ADDR_CRYPTOWRAP+0x00000000) +#define ADDR_BA431_REGS (ADDR_CRYPTOWRAP+0x00001000) +#define ADDR_BA414EP_REGS (ADDR_CRYPTOWRAP+0x00002000) +#define ADDR_BA431_FIFO (ADDR_CRYPTOWRAP+0x00004000) +#define ADDR_BA414EP_CRYPTORAM (ADDR_CRYPTOWRAP+0x00008000) +#define ADDR_BA414EP_UCODE (ADDR_CRYPTOWRAP+0x0000C000) + +#define ADDR_INCL_IPS_HW_CFG (ADDR_CRYPTOWRAP+0x00000400) +#define ADDR_BA411E_HW_CFG_1 (ADDR_CRYPTOWRAP+0x00000404) +#define ADDR_BA411E_HW_CFG_2 (ADDR_CRYPTOWRAP+0x00000408) +#define ADDR_BA413_HW_CFG (ADDR_CRYPTOWRAP+0x0000040C) +#define ADDR_BA418_HW_CFG (ADDR_CRYPTOWRAP+0x00000410) +#define ADDR_BA419_HW_CFG (ADDR_CRYPTOWRAP+0x00000414) +#define ADDR_BA424_HW_CFG (ADDR_CRYPTOWRAP+0x00000418) + +/***************************************************************************** + ** Enable polling defines + *****************************************************************************/ + +#define WAIT_CRYPTOMASTER_WITH_REGISTER_POLLING (1) +#define WAIT_RNG_WITH_REGISTER_POLLING (1) +#define WAIT_PK_WITH_REGISTER_POLLING (1) + +/***************************************************************************** + ** Bus error handling + *****************************************************************************/ + +/** @brief Trigger hardfault by access to invalid memory address */ +static inline void trigger_hardfault(void) { + uint32_t *bad_mem_addr = (uint32_t*) 0x3FFFFFFC; + *bad_mem_addr = 1; +} + +#define TRIGGER_HARDFAULT_FCT() trigger_hardfault(); + +/***************************************************************************** + ** Debug + *****************************************************************************/ + +#define DEBUG_ENABLED (1) + +#define CRYPTOLIB_PRINTF(...) {} +#define CRYPTOLIB_ASSERT(cond, msg) {} +#define CRYPTOLIB_ASSERT_NM(cond) {} +#define CRYPTOLIB_ASSERT_VAR(cond, ...) {} + +/***************************************************************************** + ** Crypto DMA + *****************************************************************************/ + +#define BLK_MEMCPY_MIN_DMA_SIZE (16UL) + +/***************************************************************************** + ** Supported algorithms + *****************************************************************************/ + +#define DH_MODP_ENABLED (0) +#define AIS31_ENABLED (1) + +#ifdef _SILICON_LABS_32B_SERIES_2_CONFIG_2 + #define JPAKE_ENABLED (0) +#else + #define JPAKE_ENABLED (1) +#endif + +/***************************************************************************** + ** Max sizes + *****************************************************************************/ + +#define PRIME_MAX_SIZE ((4096 / 8) / 2) +#define ECC_MAX_KEY_SIZE (256/8) +#define DERIV_MAX_SALT_SIZE (512) +#define DERIV_MAX_INFO_SIZE (512) + +/***************************************************************************** + ** RNG settings + *****************************************************************************/ + +// Control subsampling at output of ring oscillators (ring sampling +// frequency = ClkSec frequency / (RNG_CLKDIV+1)). +#define RNG_CLKDIV (7) + +// Number of clock cycles after FIFO being full until TRNG goes to sleep. +// A negative value will keep the ring oscillators always running. +#define RNG_OFF_TIMER_VAL (0) + +// When the FIFO level (number of 128-bit block) becomes smaller or equal +// to RNG_FIFO_WAKEUP_LVL, the TRNG is restarted. +#define RNG_FIFO_WAKEUP_LVL (8) + +// Number of clock cycles to wait after startup before sampling data from +// the noise source. +#define RNG_INIT_WAIT_VAL (512) + +// Number of 128-bit blocks of data from the noise source that are used +// as input to the conditioning function. +#define RNG_NB_128BIT_BLOCKS (8) + +/***************************************************************************** + ** Countermeasures + *****************************************************************************/ + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + #define PK_CM_ENABLED (0) +#else + #define PK_CM_ENABLED (1) +#endif + +#if PK_CM_ENABLED + // PK_CM_RAND_SIZE sets the byte size of the random number that is used for + // side channel countermeasures. Maximum allowable size is dependent on the + // maximum supported curve size: + // * 256 bit: 0 < rand < 2^16 => 2 bytes + // * 521 bit: 0 < rand < 2^23 => still 2 bytes (3 bytes could lead to 2^24-1) + #define PK_CM_RAND_SIZE (2) + + #define PK_CM_RAND_PROJ (1) + #define PK_CM_RAND_SCALAR (1) + #define PK_CM_RAND_MODULUS (0) // Only relevant for RSA/DSA/SRP + #define PK_CM_RAND_EXPONENT (0) // Only relevant for RSA/DSA/SRP +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_types.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_types.h index 0640c95..42d84a8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/cryptolib_types.h @@ -1,117 +1,117 @@ -/** - * @file - * @brief Provide types, helper macros and functions used everywhere. - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#ifndef CRYPTOLIB_TYPES_H -#define CRYPTOLIB_TYPES_H - -#include - -/** -* @brief Array-like data abstraction handling both contiguous memory and hardware FIFO. -* -* Embedding side by side the data pointer and only the data length provides an -* abstraction which does not cover data coming from/to a hardware FIFO (data always -* read/written at the same address). The block_t structure embeds an additional -* field carrying enough information to work in both array mode (2 different words -* are stored at 2 different addresses) and FIFO mode (2 different words are loaded -* from the same address). -* -* A set of dedicated functions is provided to handle the basic operations -* (using a similar interface to memcpy/memset/memcmp). -*/ -typedef struct block_s -{ - uint8_t *addr; /**< Start address of the data (FIFO or contiguous memory) */ - uint32_t len; /**< Length of data expressed in bytes */ - uint32_t flags; /**< Flags equals to ::BLOCK_S_CONST_ADDR or ::BLOCK_S_INCR_ADDR */ -} block_t; - -/** - * @brief Provide a default block_t initializer - * - * with - * - NULL base address - * - zero length, - * - contiguous memory addressing with discarding flag - * in case of DMA transfer (see ::DMA_AXI_DESCR_DISCARD) - */ -extern const block_t NULL_blk; - -/** - * Get the nth bit value of a uint8_t - * @param offset the bit number (LSB) - * @param var Variable containing the boolean - * @return The bit value (on an uint32_t) - */ -#define SX_GETBOOL(var, offset) (((var) >> (offset)) & 1) - - -/** - * Swap bytes of a 32-bit word - * @param word The 32-bit word to byte-swap - * @return The byte-swapped value - */ -#define SX_SWAPBYTES32(word) ((((word) & 0xFF000000) >> 24) | (((word) & 0x00FF0000) >> 8) | (((word) & 0x0000FF00) << 8) | (((word) & 0x000000FF) << 24)) - -/** @brief Align on word boundary */ -#define SX_ALIGNED __attribute__((aligned(0x4))) - - -/** @brief value of ::block_s.flags to set addressing in constant mode (pointing to a FIFO) */ -#define BLOCK_S_CONST_ADDR 0x10000000 -/** @brief value of ::block_s.flags to set addressing in increment mode (pointing to a contiguous data array) */ -#define BLOCK_S_INCR_ADDR 0x00000000 -/** @brief mask for ::block_s.flags to only get DMA-related options */ -#define BLOCK_S_FLAG_MASK_DMA_PROPS 0x70000000 - -/** - * @brief Convert a pair of array address and length to a block_t - * @param array Array address. It does not support FIFO addresses. - * @param length Length of data expressed in bytes - * @return block_t - */ -static inline block_t block_t_convert(const volatile void *array, uint32_t length) -{ - block_t blk = {(uint8_t *)array, length, BLOCK_S_INCR_ADDR}; - return blk; -} - -#define BLK_LITARRAY(literal) (block_t){(uint8_t *)(literal), sizeof(literal), BLOCK_S_INCR_ADDR} - -#define CST_BLK_LITARRAY(literal) {(uint8_t *)(literal), sizeof(literal), BLOCK_S_INCR_ADDR} - -/** - * Round-up integer to next 32-bit multiple - * @param value The value to round - * @return The rounded value - */ -#define roundup_32(value) (((value) + 3) & ~3) - - -/** - * Round-up the length of a block_t to 32-bit if the address is a FIFO - * @param blk A pointer to the block_t to adapt - */ -static inline void block_t_adapt_len(block_t * blk) -{ - if (blk->flags & BLOCK_S_CONST_ADDR) - blk->len = roundup_32(blk->len); -} - -/** @brief Inline function for minimum value between 2 numbers */ -static inline uint32_t SX_MIN(uint32_t a, uint32_t b) -{ - if(a + +/** +* @brief Array-like data abstraction handling both contiguous memory and hardware FIFO. +* +* Embedding side by side the data pointer and only the data length provides an +* abstraction which does not cover data coming from/to a hardware FIFO (data always +* read/written at the same address). The block_t structure embeds an additional +* field carrying enough information to work in both array mode (2 different words +* are stored at 2 different addresses) and FIFO mode (2 different words are loaded +* from the same address). +* +* A set of dedicated functions is provided to handle the basic operations +* (using a similar interface to memcpy/memset/memcmp). +*/ +typedef struct block_s +{ + uint8_t *addr; /**< Start address of the data (FIFO or contiguous memory) */ + uint32_t len; /**< Length of data expressed in bytes */ + uint32_t flags; /**< Flags equals to ::BLOCK_S_CONST_ADDR or ::BLOCK_S_INCR_ADDR */ +} block_t; + +/** + * @brief Provide a default block_t initializer + * + * with + * - NULL base address + * - zero length, + * - contiguous memory addressing with discarding flag + * in case of DMA transfer (see ::DMA_AXI_DESCR_DISCARD) + */ +extern const block_t NULL_blk; + +/** + * Get the nth bit value of a uint8_t + * @param offset the bit number (LSB) + * @param var Variable containing the boolean + * @return The bit value (on an uint32_t) + */ +#define SX_GETBOOL(var, offset) (((var) >> (offset)) & 1) + + +/** + * Swap bytes of a 32-bit word + * @param word The 32-bit word to byte-swap + * @return The byte-swapped value + */ +#define SX_SWAPBYTES32(word) ((((word) & 0xFF000000) >> 24) | (((word) & 0x00FF0000) >> 8) | (((word) & 0x0000FF00) << 8) | (((word) & 0x000000FF) << 24)) + +/** @brief Align on word boundary */ +#define SX_ALIGNED __attribute__((aligned(0x4))) + + +/** @brief value of ::block_s.flags to set addressing in constant mode (pointing to a FIFO) */ +#define BLOCK_S_CONST_ADDR 0x10000000 +/** @brief value of ::block_s.flags to set addressing in increment mode (pointing to a contiguous data array) */ +#define BLOCK_S_INCR_ADDR 0x00000000 +/** @brief mask for ::block_s.flags to only get DMA-related options */ +#define BLOCK_S_FLAG_MASK_DMA_PROPS 0x70000000 + +/** + * @brief Convert a pair of array address and length to a block_t + * @param array Array address. It does not support FIFO addresses. + * @param length Length of data expressed in bytes + * @return block_t + */ +static inline block_t block_t_convert(const volatile void *array, uint32_t length) +{ + block_t blk = {(uint8_t *)array, length, BLOCK_S_INCR_ADDR}; + return blk; +} + +#define BLK_LITARRAY(literal) (block_t){(uint8_t *)(literal), sizeof(literal), BLOCK_S_INCR_ADDR} + +#define CST_BLK_LITARRAY(literal) {(uint8_t *)(literal), sizeof(literal), BLOCK_S_INCR_ADDR} + +/** + * Round-up integer to next 32-bit multiple + * @param value The value to round + * @return The rounded value + */ +#define roundup_32(value) (((value) + 3) & ~3) + + +/** + * Round-up the length of a block_t to 32-bit if the address is a FIFO + * @param blk A pointer to the block_t to adapt + */ +static inline void block_t_adapt_len(block_t * blk) +{ + if (blk->flags & BLOCK_S_CONST_ADDR) + blk->len = roundup_32(blk->len); +} + +/** @brief Inline function for minimum value between 2 numbers */ +static inline uint32_t SX_MIN(uint32_t a, uint32_t b) +{ + if(a -#include "compiler_extentions.h" -#include "cryptolib_types.h" -#include "sx_blk_cipher_common.h" - -/** @brief Size for IV in all modes except GCM */ -#define AES_IV_SIZE (BLK_CIPHER_IV_SIZE) -/** @brief Size for IV in GCM mode */ -#define AES_IV_GCM_SIZE (BLK_CIPHER_IV_GCM_SIZE) -/** @brief Size of a GCM/GMAC/CMAC message authentification code (MAC) - * or maximum size of a CCM MAC */ -#define AES_MAC_SIZE (BLK_CIPHER_MAC_SIZE) -/** @brief Size for Context in GCM and CCM modes */ -#define AES_CTX_xCM_SIZE (BLK_CIPHER_CTX_xCM_SIZE) -/** @brief Size for Context in all modes except GCM and CCM */ -#define AES_CTX_SIZE (BLK_CIPHER_CTX_SIZE) - -/** @brief Size in bytes for AES-128 key */ -#define AES_KEYSIZE_128 16 -/** @brief Size in bytes for AES-192 key */ -#define AES_KEYSIZE_192 24 -/** @brief Size in bytes for AES-256 key */ -#define AES_KEYSIZE_256 32 -/** - * @brief Dummy variables to use hardware keys Key1 and Key2 - * - * @note They are declared \c extern for internal reasons, user should \e not - * use them because they may disappear in future release. - */ -extern uint8_t aes_hw_key2; -extern uint8_t aes_hw_key1; - -/** - * @brief First Hardware Key (of 128bits) - * - * Two secret hardware keys may be wired directly into to AES module, preventing - * the CPU to read them back. This block_t provides an abstraction to pass them - * as input (user should not use them for anything else as input) in the same way - * that user AES keys. - */ -#define AES_KEY1_128 block_t_convert(&aes_hw_key1, 128/8) -/** @brief First Hardware Key of 256b (for description, see ::AES_KEY1_128) */ -#define AES_KEY1_256 block_t_convert(&aes_hw_key1, 256/8) -/** @brief Second Hardware Key of 128b (for description, see ::AES_KEY1_128) */ -#define AES_KEY2_128 block_t_convert(&aes_hw_key2, 128/8) -/** @brief Second Hardware Key of 256b (for description, see ::AES_KEY1_128) */ -#define AES_KEY2_256 block_t_convert(&aes_hw_key2, 256/8) - -/** Encryption operation using AES-ECB - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ecb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext); - -/** Decryption operation using AES-ECB - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ecb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext); - -/** Encryption operation using AES-CBC - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv); - -/** Decryption operation using AES-CBC - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv); - -/** Start (init) encryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cbc_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out); - -/** Start (init) decryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cbc_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out); - - -/** Continue (update) encryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cbc_encrypt_update or to ::sx_aes_cbc_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cbc_decrypt_update or to ::sx_aes_cbc_decrypt_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in); - -/** Finish (final) decryption operation using AES-CBC in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cbc_decrypt_init or from ::sx_aes_cbc_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cbc_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in); - -/** Encryption operation using AES-CTR - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv); - -/** Decryption operation using AES-CTR - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv); - -/** Start (init) encryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ctr_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out); - -/** Start (init) decryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ctr_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out); - -/** Continue (update) encryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ctr_encrypt_update or to ::sx_aes_ctr_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ctr_encrypt_update or to ::sx_aes_ctr_decrypt_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to decrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in); - -/** Finish (final) decryption operation using AES-CTR in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ctr_decrypt_init or from ::sx_aes_ctr_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ctr_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in); - -/** Encryption operation using AES-CFB - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv); - -/** Decryption operation using AES-CFB - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv); - -/** Start (init) encryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cfb_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out); - -/** Start (init) decryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cfb_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out); - -/** Continue (update) encryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cfb_encrypt_update or to ::sx_aes_cfb_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cfb_encrypt_update or to ::sx_aes_cfb_decrypt_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to decrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in); - -/** Finish (final) decryption operation using AES-CFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cfb_decrypt_init or from ::sx_aes_cfb_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cfb_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in); - -/** Encryption operation using AES-OFB - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv); - -/** Decryption operation using AES-OFB - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv); - -/** Start (init) encryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ofb_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out); - -/** Start (init) decryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ofb_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out); - -/** Continue (update) encryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ofb_encrypt_update or to ::sx_aes_ofb_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ofb_encrypt_update or to ::sx_aes_ofb_decrypt_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_encrypt_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in); - -/** Finish (final) decryption operation using AES-OFB in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ofb_decrypt_init or from ::sx_aes_ofb_decrypt_update - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ofb_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in); - -/** Encryption operation using AES-XTS - * - * @param key is the key involved to encrypt the plaintext - * @param plaintext is the input data to encrypt - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - const block_t *key_xts); - -/** Decryption operation using AES-XTS - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *key_xts); - -/** Start (init) encryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_xts_encrypt_update - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts); - -/** Start (init) decryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_xts_decrypt_update - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts); - -/** Continue (update) encryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param ciphertext is the input data to encrypt - * @param plaintext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_xts_encrypt_update or to ::sx_aes_xts_encrypt_final - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts); - -/** Continue (update) decryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_xts_encrypt_update or to ::sx_aes_xts_decrypt_final - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts); - -/** Finish (final) encryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to encrypt the plaintext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_encrypt_update - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - const block_t *key_xts); - -/** Finish (final) decryption operation using AES-XTS in Init-Update-Final model - * - * @param key is the key involved to decrypt the ciphertext - * @param ciphertext is the input data to decrypt - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_xts_decrypt_init or from ::sx_aes_xts_decrypt_update - * @param key_xts is the "tweak" key involved in AES-XTS - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_xts_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *key_xts); - -/** Encryption and authentication operation using AES-GCM - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param mac is the output Message Authentication Code of the plaintext and aad - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * @note If one only needs authentication, this function may be used as GMAC - * and user has to only keep the \c plaintext and the \c mac - */ -uint32_t sx_aes_gcm_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *mac, - const block_t *aad); - -/** Decryption and authentication operation using AES-GCM - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param mac is the output Message Authentication Code of the ciphertext and aad - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_gcm_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *mac, - const block_t *aad); - -/** Decryption, authentication and verification operation using AES-GCM - * - * By opposition to ::sx_aes_gcm_decrypt, this function does not output the MAC - * but uses an input reference to internally check if it maches the recomputed - * one. By only checking the returned value of the function, caller knows - * if the input data (\ciphertext) are tampered or not. - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param mac is an input Message Authentication Code as reference for verification - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_gcm_decrypt_verify( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *mac, - const block_t *aad); - -/** Start (init) encryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input dat to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_gcm_encrypt_update (expected size is 32B) - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_gcm_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out, - const block_t *aad); - -/** Start (init) decryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_gcm_decrypt_update (expected size is 32B) - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_gcm_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out, - const block_t *aad); - -/** Continue (update) encryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_gcm_encrypt_update or to ::sx_aes_gcm_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_aes_gcm_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_gcm_decrypt_update or to ::sx_aes_gcm_decrypt_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_aes_gcm_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_encrypt_update - * @param mac is the output Message Authentication Code of the plaintext and aad - * @param len_a_c are length of both \c plaintext and \c aad as described in - * NIST SP800-38D at 7.GCM Specification - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_aes_gcm_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c); - -/** Finish (final) decryption and authentication operation using AES-GCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_gcm_decrypt_init or from ::sx_aes_gcm_decrypt_update - * @param mac is the output Message Authentication Code of the ciphertext and aad - * @param len_a_c are length of both \c ciphertext and \c aad as described in - * NIST SP800-38D at 7.GCM Specification - * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_aes_gcm_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c); - -/** Finish (final) decryption, authentication and verification operation using - * AES-GCM in Init-Update-Final model - * - * By opposition to ::sx_aes_gcm_decrypt_final, this function does not output - * the MAC but uses an input reference to internally check if it maches the - * recomputed one. By only checking the returned value of the function, caller - * knows if the input data (\ciphertext) are tampered or not. - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_gcm_decrypt_init or from ::sx_aes_gcm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @param len_a_c are length of both \c ciphertext and \c aad as described in - * NIST SP800-38D at 7.GCM Specification - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_aes_gcm_decrypt_verify_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac, - const block_t *len_a_c); - -/** Encryption and authentication operation using AES-CCM - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is the output Message Authentication Code of the plaintext and aad, - * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to - * CCM* described in B.4 Specification of generic CCM* mode of operation - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ccm_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *mac, - const block_t *aad); - -/** Decryption and authentication operation using AES-CCM - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is the output Message Authentication Code - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ccm_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - block_t *mac, - const block_t *aad); - -/** Decryption, authentication and verification operation using AES-CCM - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is an input Message Authentication Code as reference for verification, - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ccm_decrypt_verify( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - const block_t *mac, - const block_t *aad); - -/** Start (init) encryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input dat to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param nonce is the input number to use once - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ccm_encrypt_update (expected size is 32B) - * @param aad are additional data passed aside the plaintext to compute the MAC - * @param mac_len is the length of the mac to output. In IUF, it is mandatory - * to provide it during init step as this length is required to compute - * CCM headers. - * @param total_length total length of data going to be input in IUF - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ccm_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length); - -/** Start (init) decryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param nonce is the input number to use once - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ccm_decrypt_update (expected size is 32B) - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @param mac_len is the length of the mac to output. In IUF, it is mandatory - * to provide it during init step as this length is required to compute - * CCM headers. - * @param total_length total length of data going to be input in IUF - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_ccm_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length); - -/** Continue (update) encryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_encrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ccm_encrypt_update or to ::sx_aes_ccm_encrypt_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_aes_ccm_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Continue (update) decryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_decrypt_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_ccm_decrypt_update or to ::sx_aes_ccm_decrypt_verify_final - * @return ::CRYPTOLIB_SUCCESS if decryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_aes_ccm_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_encrypt_update - * @param mac is the output Message Authentication Code of the plaintext and aad - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_aes_ccm_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) decryption and authentication operation using AES-CCM in - * Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ccm_decrypt_init or from ::sx_aes_ccm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_aes_ccm_decrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) decryption, authentication and verification operation using - * AES-CCM in Init-Update-Final model - * - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_ccm_decrypt_init or from ::sx_aes_ccm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_aes_ccm_decrypt_verify_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - const block_t *mac); - -/** Authentication operation using CMAC - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param mac is the output Message Authentication Code - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_generate( - const block_t *key, - const block_t *message, - block_t *mac); - -/** Authentication verification operation using CMAC - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate and verify - * @param mac is an input Message Authentication Code used as reference - * @return ::CRYPTOLIB_SUCCESS if authentication verifiation succeeded - * ::CRYPTOLIB_INVALID_SIGN_ERR if authentication verification failed - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_verify( - const block_t *key, - const block_t *message, - const block_t *mac); - -/** Start (init) authentication operation using CMAC in Init-Update-Final model - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cmac_generate_update - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_generate_init( - const block_t *key, - const block_t *message, - block_t *ctx_out); - -/** Continue (update) authentication operation using CMAC in - * Init-Update-Final model - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_aes_cmac_generate_update - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_generate_update( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) authentication operation using CMAC in - * Init-Update-Final model - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update - * @param mac is the output Message Authentication Code of the message - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_generate_final( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) authentication verification operation using CMAC in - * Init-Update-Final model - * - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if authentication verification succeeded - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_aes_cmac_generate_verify_final( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - const block_t *mac); - -/** - * @brief Reload random used in the AES counter-measures. - * - * When enabled in HW, counter-measures are available for the AES - * (See the Technical Report: "Secure and Efficient Masking of AES - A Mission - * Impossible?", June 2004) - * - * \warning It is under the user responsibility to call it after system boot - * (not automatically called). - * - * @param value new random value used to reload counter-measures - */ -void sx_aes_load_mask(uint32_t value); - -#endif +/** + * @file + * @brief Defines the procedures to make operations with + * the BA411 AES function + * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved + */ + +#ifndef SX_AES_H +#define SX_AES_H + +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" +#include "sx_blk_cipher_common.h" + +/** @brief Size for IV in all modes except GCM */ +#define AES_IV_SIZE (BLK_CIPHER_IV_SIZE) +/** @brief Size for IV in GCM mode */ +#define AES_IV_GCM_SIZE (BLK_CIPHER_IV_GCM_SIZE) +/** @brief Size of a GCM/GMAC/CMAC message authentification code (MAC) + * or maximum size of a CCM MAC */ +#define AES_MAC_SIZE (BLK_CIPHER_MAC_SIZE) +/** @brief Size for Context in GCM and CCM modes */ +#define AES_CTX_xCM_SIZE (BLK_CIPHER_CTX_xCM_SIZE) +/** @brief Size for Context in all modes except GCM and CCM */ +#define AES_CTX_SIZE (BLK_CIPHER_CTX_SIZE) + +/** @brief Size in bytes for AES-128 key */ +#define AES_KEYSIZE_128 16 +/** @brief Size in bytes for AES-192 key */ +#define AES_KEYSIZE_192 24 +/** @brief Size in bytes for AES-256 key */ +#define AES_KEYSIZE_256 32 +/** + * @brief Dummy variables to use hardware keys Key1 and Key2 + * + * @note They are declared \c extern for internal reasons, user should \e not + * use them because they may disappear in future release. + */ +extern uint8_t aes_hw_key2; +extern uint8_t aes_hw_key1; + +/** + * @brief First Hardware Key (of 128bits) + * + * Two secret hardware keys may be wired directly into to AES module, preventing + * the CPU to read them back. This block_t provides an abstraction to pass them + * as input (user should not use them for anything else as input) in the same way + * that user AES keys. + */ +#define AES_KEY1_128 block_t_convert(&aes_hw_key1, 128/8) +/** @brief First Hardware Key of 256b (for description, see ::AES_KEY1_128) */ +#define AES_KEY1_256 block_t_convert(&aes_hw_key1, 256/8) +/** @brief Second Hardware Key of 128b (for description, see ::AES_KEY1_128) */ +#define AES_KEY2_128 block_t_convert(&aes_hw_key2, 128/8) +/** @brief Second Hardware Key of 256b (for description, see ::AES_KEY1_128) */ +#define AES_KEY2_256 block_t_convert(&aes_hw_key2, 256/8) + +/** Encryption operation using AES-ECB + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ecb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext); + +/** Decryption operation using AES-ECB + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ecb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext); + +/** Encryption operation using AES-CBC + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv); + +/** Decryption operation using AES-CBC + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv); + +/** Start (init) encryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cbc_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out); + +/** Start (init) decryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cbc_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out); + + +/** Continue (update) encryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cbc_encrypt_update or to ::sx_aes_cbc_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cbc_decrypt_update or to ::sx_aes_cbc_decrypt_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cbc_encrypt_init or from ::sx_aes_cbc_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in); + +/** Finish (final) decryption operation using AES-CBC in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cbc_decrypt_init or from ::sx_aes_cbc_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cbc_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in); + +/** Encryption operation using AES-CTR + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv); + +/** Decryption operation using AES-CTR + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv); + +/** Start (init) encryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ctr_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out); + +/** Start (init) decryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ctr_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out); + +/** Continue (update) encryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ctr_encrypt_update or to ::sx_aes_ctr_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ctr_encrypt_update or to ::sx_aes_ctr_decrypt_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to decrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ctr_encrypt_init or from ::sx_aes_ctr_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in); + +/** Finish (final) decryption operation using AES-CTR in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ctr_decrypt_init or from ::sx_aes_ctr_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ctr_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in); + +/** Encryption operation using AES-CFB + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv); + +/** Decryption operation using AES-CFB + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv); + +/** Start (init) encryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cfb_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out); + +/** Start (init) decryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cfb_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out); + +/** Continue (update) encryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cfb_encrypt_update or to ::sx_aes_cfb_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cfb_encrypt_update or to ::sx_aes_cfb_decrypt_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to decrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cfb_encrypt_init or from ::sx_aes_cfb_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in); + +/** Finish (final) decryption operation using AES-CFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cfb_decrypt_init or from ::sx_aes_cfb_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cfb_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in); + +/** Encryption operation using AES-OFB + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv); + +/** Decryption operation using AES-OFB + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv); + +/** Start (init) encryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ofb_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out); + +/** Start (init) decryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ofb_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out); + +/** Continue (update) encryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ofb_encrypt_update or to ::sx_aes_ofb_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ofb_encrypt_update or to ::sx_aes_ofb_decrypt_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ofb_encrypt_init or from ::sx_aes_ofb_encrypt_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in); + +/** Finish (final) decryption operation using AES-OFB in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ofb_decrypt_init or from ::sx_aes_ofb_decrypt_update + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ofb_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in); + +/** Encryption operation using AES-XTS + * + * @param key is the key involved to encrypt the plaintext + * @param plaintext is the input data to encrypt + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + const block_t *key_xts); + +/** Decryption operation using AES-XTS + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *key_xts); + +/** Start (init) encryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_xts_encrypt_update + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts); + +/** Start (init) decryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_xts_decrypt_update + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts); + +/** Continue (update) encryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param ciphertext is the input data to encrypt + * @param plaintext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_xts_encrypt_update or to ::sx_aes_xts_encrypt_final + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts); + +/** Continue (update) decryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_xts_encrypt_update or to ::sx_aes_xts_decrypt_final + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts); + +/** Finish (final) encryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to encrypt the plaintext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_xts_encrypt_init or from ::sx_aes_xts_encrypt_update + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + const block_t *key_xts); + +/** Finish (final) decryption operation using AES-XTS in Init-Update-Final model + * + * @param key is the key involved to decrypt the ciphertext + * @param ciphertext is the input data to decrypt + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_xts_decrypt_init or from ::sx_aes_xts_decrypt_update + * @param key_xts is the "tweak" key involved in AES-XTS + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_xts_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *key_xts); + +/** Encryption and authentication operation using AES-GCM + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param mac is the output Message Authentication Code of the plaintext and aad + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * @note If one only needs authentication, this function may be used as GMAC + * and user has to only keep the \c plaintext and the \c mac + */ +uint32_t sx_aes_gcm_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *mac, + const block_t *aad); + +/** Decryption and authentication operation using AES-GCM + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param mac is the output Message Authentication Code of the ciphertext and aad + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_gcm_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *mac, + const block_t *aad); + +/** Decryption, authentication and verification operation using AES-GCM + * + * By opposition to ::sx_aes_gcm_decrypt, this function does not output the MAC + * but uses an input reference to internally check if it maches the recomputed + * one. By only checking the returned value of the function, caller knows + * if the input data (\ciphertext) are tampered or not. + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param mac is an input Message Authentication Code as reference for verification + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_gcm_decrypt_verify( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *mac, + const block_t *aad); + +/** Start (init) encryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input dat to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_gcm_encrypt_update (expected size is 32B) + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_gcm_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out, + const block_t *aad); + +/** Start (init) decryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_gcm_decrypt_update (expected size is 32B) + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_gcm_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out, + const block_t *aad); + +/** Continue (update) encryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_gcm_encrypt_update or to ::sx_aes_gcm_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_aes_gcm_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_gcm_decrypt_update or to ::sx_aes_gcm_decrypt_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_aes_gcm_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_gcm_encrypt_init or from ::sx_aes_gcm_encrypt_update + * @param mac is the output Message Authentication Code of the plaintext and aad + * @param len_a_c are length of both \c plaintext and \c aad as described in + * NIST SP800-38D at 7.GCM Specification + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_aes_gcm_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c); + +/** Finish (final) decryption and authentication operation using AES-GCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_gcm_decrypt_init or from ::sx_aes_gcm_decrypt_update + * @param mac is the output Message Authentication Code of the ciphertext and aad + * @param len_a_c are length of both \c ciphertext and \c aad as described in + * NIST SP800-38D at 7.GCM Specification + * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_aes_gcm_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c); + +/** Finish (final) decryption, authentication and verification operation using + * AES-GCM in Init-Update-Final model + * + * By opposition to ::sx_aes_gcm_decrypt_final, this function does not output + * the MAC but uses an input reference to internally check if it maches the + * recomputed one. By only checking the returned value of the function, caller + * knows if the input data (\ciphertext) are tampered or not. + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_gcm_decrypt_init or from ::sx_aes_gcm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @param len_a_c are length of both \c ciphertext and \c aad as described in + * NIST SP800-38D at 7.GCM Specification + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_aes_gcm_decrypt_verify_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac, + const block_t *len_a_c); + +/** Encryption and authentication operation using AES-CCM + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is the output Message Authentication Code of the plaintext and aad, + * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to + * CCM* described in B.4 Specification of generic CCM* mode of operation + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ccm_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *mac, + const block_t *aad); + +/** Decryption and authentication operation using AES-CCM + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is the output Message Authentication Code + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ccm_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + block_t *mac, + const block_t *aad); + +/** Decryption, authentication and verification operation using AES-CCM + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is an input Message Authentication Code as reference for verification, + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ccm_decrypt_verify( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + const block_t *mac, + const block_t *aad); + +/** Start (init) encryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input dat to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param nonce is the input number to use once + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ccm_encrypt_update (expected size is 32B) + * @param aad are additional data passed aside the plaintext to compute the MAC + * @param mac_len is the length of the mac to output. In IUF, it is mandatory + * to provide it during init step as this length is required to compute + * CCM headers. + * @param total_length total length of data going to be input in IUF + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ccm_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length); + +/** Start (init) decryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param nonce is the input number to use once + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ccm_decrypt_update (expected size is 32B) + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @param mac_len is the length of the mac to output. In IUF, it is mandatory + * to provide it during init step as this length is required to compute + * CCM headers. + * @param total_length total length of data going to be input in IUF + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_ccm_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length); + +/** Continue (update) encryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_encrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ccm_encrypt_update or to ::sx_aes_ccm_encrypt_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_aes_ccm_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Continue (update) decryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_decrypt_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_ccm_decrypt_update or to ::sx_aes_ccm_decrypt_verify_final + * @return ::CRYPTOLIB_SUCCESS if decryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_aes_ccm_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ccm_encrypt_init or from ::sx_aes_ccm_encrypt_update + * @param mac is the output Message Authentication Code of the plaintext and aad + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_aes_ccm_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) decryption and authentication operation using AES-CCM in + * Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ccm_decrypt_init or from ::sx_aes_ccm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_aes_ccm_decrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) decryption, authentication and verification operation using + * AES-CCM in Init-Update-Final model + * + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_ccm_decrypt_init or from ::sx_aes_ccm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_aes_ccm_decrypt_verify_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + const block_t *mac); + +/** Authentication operation using CMAC + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param mac is the output Message Authentication Code + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_generate( + const block_t *key, + const block_t *message, + block_t *mac); + +/** Authentication verification operation using CMAC + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate and verify + * @param mac is an input Message Authentication Code used as reference + * @return ::CRYPTOLIB_SUCCESS if authentication verifiation succeeded + * ::CRYPTOLIB_INVALID_SIGN_ERR if authentication verification failed + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_verify( + const block_t *key, + const block_t *message, + const block_t *mac); + +/** Start (init) authentication operation using CMAC in Init-Update-Final model + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cmac_generate_update + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_generate_init( + const block_t *key, + const block_t *message, + block_t *ctx_out); + +/** Continue (update) authentication operation using CMAC in + * Init-Update-Final model + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_aes_cmac_generate_update + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_generate_update( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) authentication operation using CMAC in + * Init-Update-Final model + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update + * @param mac is the output Message Authentication Code of the message + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_generate_final( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) authentication verification operation using CMAC in + * Init-Update-Final model + * + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_aes_cmac_generate_init or from ::sx_aes_cmac_generate_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if authentication verification succeeded + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_aes_cmac_generate_verify_final( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + const block_t *mac); + +/** + * @brief Reload random used in the AES counter-measures. + * + * When enabled in HW, counter-measures are available for the AES + * (See the Technical Report: "Secure and Efficient Masking of AES - A Mission + * Impossible?", June 2004) + * + * \warning It is under the user responsibility to call it after system boot + * (not automatically called). + * + * @param value new random value used to reload counter-measures + */ +void sx_aes_load_mask(uint32_t value); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_blk_cipher_common.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_blk_cipher_common.h index 501a3d9..88837ad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_blk_cipher_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_blk_cipher_common.h @@ -1,25 +1,25 @@ -/** - * @file - * @brief Defines common macros used by block ciphers for configure input/output - * data, used in AES, SM4 and ARIA - * @copyright Copyright (c) 2019 Silex Insight. All Rights reserved - */ - -#ifndef BLK_CIPHER_COMMON_H -#define BLK_CIPHER_COMMON_H - -/** @brief Block data size for block cipher */ -#define BLK_CIPHER_BLOCK_SIZE 16 -/** @brief Size for block cipher IV in GCM mode */ -#define BLK_CIPHER_IV_GCM_SIZE 12 -/** @brief Size for block cipher IV in all modes except GCM */ -#define BLK_CIPHER_IV_SIZE 16 -/** @brief Size for block cipher Context in GCM and CCM modes */ -#define BLK_CIPHER_CTX_xCM_SIZE 32 -/** @brief Size for block cipher Context in all modes except GCM and CCM */ -#define BLK_CIPHER_CTX_SIZE 16 -/** @brief Size of a GCM/GMAC/CMAC block cipher message authentification - * code (MAC) or maximum size of a CCM MAC */ -#define BLK_CIPHER_MAC_SIZE 16 - -#endif +/** + * @file + * @brief Defines common macros used by block ciphers for configure input/output + * data, used in AES, SM4 and ARIA + * @copyright Copyright (c) 2019 Silex Insight. All Rights reserved + */ + +#ifndef BLK_CIPHER_COMMON_H +#define BLK_CIPHER_COMMON_H + +/** @brief Block data size for block cipher */ +#define BLK_CIPHER_BLOCK_SIZE 16 +/** @brief Size for block cipher IV in GCM mode */ +#define BLK_CIPHER_IV_GCM_SIZE 12 +/** @brief Size for block cipher IV in all modes except GCM */ +#define BLK_CIPHER_IV_SIZE 16 +/** @brief Size for block cipher Context in GCM and CCM modes */ +#define BLK_CIPHER_CTX_xCM_SIZE 32 +/** @brief Size for block cipher Context in all modes except GCM and CCM */ +#define BLK_CIPHER_CTX_SIZE 16 +/** @brief Size of a GCM/GMAC/CMAC block cipher message authentification + * code (MAC) or maximum size of a CCM MAC */ +#define BLK_CIPHER_MAC_SIZE 16 + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dh_alg.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dh_alg.h index 925e57c..4af95f0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dh_alg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dh_alg.h @@ -1,83 +1,83 @@ -/** - * @file - * @brief Defines the procedures to make DH operations with - * the BA414EP pub key - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_DH_ALG_H -#define SX_DH_ALG_H - -#include -#include "compiler_extentions.h" -#include "cryptolib_def.h" -#include "cryptolib_types.h" -#if (DH_MODP_ENABLED) - -/** - * @brief Compute a Diffie Hellman shared key in modular arithmetic - * - * It computes this shared key based on a public, a private key and - * the known generator (see RFC 2631) - * @param mod Modulus of the domain - * @param priv Private key - * @param pub Other party public key - * @param shared Secret shared key (big integer) - * @param size Size in bytes of one parameter - * @return CRYPTOLIB_SUCCESS if no error - * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE - */ -uint32_t dh_shared_key_modp( - block_t mod, - block_t priv, - block_t pub, - block_t shared, - uint32_t size) CHECK_RESULT; - -#endif - - -/** - * @brief Compute a Diffie Hellman shared key using ECC-Edwards and both - * ECC-Weierstrass prime and binary - * - * @param domain Domain of the key - * @param priv Private key - * @param pub Other party public key - * @param shared Shared key (coordinates of a point) - * @param size Size in bytes of one parameter - * @param curve_flags Curve acceleration parameters - * @return CRYPTOLIB_SUCCESS if no error - * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE - */ -uint32_t dh_shared_key_ecdh( - block_t domain, - block_t priv, - block_t pub, - block_t shared, - uint32_t size, - uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Compute a Diffie Hellman shared key using ECC-Montgomery - * - * @param domain Domain of the key - * @param priv Private key - * @param pub Other party public key - * @param shared Shared key (only one coordinate) - * @param size Size in bytes of one parameter - * @param curve_flags Curve acceleration parameters - * @return CRYPTOLIB_SUCCESS if no error - * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE - */ -uint32_t dh_shared_montgomery_key_ecdh( - block_t domain, - block_t priv, - block_t pub, - block_t shared, - uint32_t size, - uint32_t curve_flags); - - -#endif +/** + * @file + * @brief Defines the procedures to make DH operations with + * the BA414EP pub key + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_DH_ALG_H +#define SX_DH_ALG_H + +#include +#include "compiler_extentions.h" +#include "cryptolib_def.h" +#include "cryptolib_types.h" +#if (DH_MODP_ENABLED) + +/** + * @brief Compute a Diffie Hellman shared key in modular arithmetic + * + * It computes this shared key based on a public, a private key and + * the known generator (see RFC 2631) + * @param mod Modulus of the domain + * @param priv Private key + * @param pub Other party public key + * @param shared Secret shared key (big integer) + * @param size Size in bytes of one parameter + * @return CRYPTOLIB_SUCCESS if no error + * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE + */ +uint32_t dh_shared_key_modp( + block_t mod, + block_t priv, + block_t pub, + block_t shared, + uint32_t size) CHECK_RESULT; + +#endif + + +/** + * @brief Compute a Diffie Hellman shared key using ECC-Edwards and both + * ECC-Weierstrass prime and binary + * + * @param domain Domain of the key + * @param priv Private key + * @param pub Other party public key + * @param shared Shared key (coordinates of a point) + * @param size Size in bytes of one parameter + * @param curve_flags Curve acceleration parameters + * @return CRYPTOLIB_SUCCESS if no error + * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE + */ +uint32_t dh_shared_key_ecdh( + block_t domain, + block_t priv, + block_t pub, + block_t shared, + uint32_t size, + uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Compute a Diffie Hellman shared key using ECC-Montgomery + * + * @param domain Domain of the key + * @param priv Private key + * @param pub Other party public key + * @param shared Shared key (only one coordinate) + * @param size Size in bytes of one parameter + * @param curve_flags Curve acceleration parameters + * @return CRYPTOLIB_SUCCESS if no error + * CRYPTOLIB_UNSUPPORTED_ERR if size is bigger than DH_MAX_KEY_SIZE + */ +uint32_t dh_shared_montgomery_key_ecdh( + block_t domain, + block_t priv, + block_t pub, + block_t shared, + uint32_t size, + uint32_t curve_flags); + + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dma.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dma.h index 3380ace..d12ac71 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dma.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_dma.h @@ -1,189 +1,189 @@ -/** - * @file - * @brief Describes the DMA registers - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_DMA_H -#define SX_DMA_H - -#include -#include "cryptolib_def.h" -/** -* @brief Defines for accessing DMA registers -*/ -#define ADDR_DMA_FETCH_ADDR (ADDR_CRYPTOMASTER_REGS + 0x0000) /**< Start address of data block */ -#define ADDR_DMA_FETCH_LEN (ADDR_CRYPTOMASTER_REGS + 0x0008) /**< Length of data block */ -#define ADDR_DMA_FETCH_TAG (ADDR_CRYPTOMASTER_REGS + 0x000C) /**< User tag */ -#define ADDR_DMA_PUSH_ADDR (ADDR_CRYPTOMASTER_REGS + 0x0010) /**< Start address of data block */ -#define ADDR_DMA_PUSH_LEN (ADDR_CRYPTOMASTER_REGS + 0x0018) /**< Length of data block */ -#define ADDR_DMA_INT_EN (ADDR_CRYPTOMASTER_REGS + 0x001C) /**< Interrupt enable */ -#define ADDR_DMA_INT_EN_SET (ADDR_CRYPTOMASTER_REGS + 0x0020) /**< Interrupt enable set */ -#define ADDR_DMA_INT_EN_CLR (ADDR_CRYPTOMASTER_REGS + 0x0024) /**< Interrupt enable clear */ -#define ADDR_DMA_INT_STAT_RAW (ADDR_CRYPTOMASTER_REGS + 0x0028) /**< Interrupt raw status */ -#define ADDR_DMA_INT_STAT (ADDR_CRYPTOMASTER_REGS + 0x002C) /**< Interrupt status */ -#define ADDR_DMA_INT_STAT_CLR (ADDR_CRYPTOMASTER_REGS + 0x0030) /**< Interrupt status clear */ -#define ADDR_DMA_CONFIG (ADDR_CRYPTOMASTER_REGS + 0x0034) /**< Configuration */ -#define ADDR_DMA_START (ADDR_CRYPTOMASTER_REGS + 0x0038) /**< Start fetch & push */ -#define ADDR_DMA_STATUS (ADDR_CRYPTOMASTER_REGS + 0x003C) /**< Status */ - -/** -* @brief Structure that represent a descriptor for the DMA module (in scatter-gather mode). -*/ -struct dma_sg_descr_s { - volatile void * volatile addr; /**< Address of the first byte of data to be fetched/pushed */ - volatile struct dma_sg_descr_s * volatile next_descr; /**< Pointer to the next valid - descriptor or indicates - that the current descriptor - is the last. - - \c next_descr[31:2] address of next descriptor, they are ignored on - last descriptor.\n The 2 LSB are always zero as DMA handles 32 bits word - - \c next_descr[1] is not used - - \c next_descr[0] is the stop bit. If high, the DMA will not fetch - another descriptor, the stop indicates the last descriptor */ - volatile uint32_t length_irq; /**< length and flags associated to a descriptor. - - \c length_irq[31] is not used - - \c length_irq[30] allows data discarding. When high, data is fetched - but not written to the destination - - \c length_irq[29] allows data realignment on 32 bits when high.\n Padding is discarded - from output data. \n The realignment \e must be used: - - with the last descriptor of a list of descriptors - - to realign different items in a list of descriptors - . - The realignment must not be used when a message is split in - multiple unaligned blocks to concatenate on output. - - \c length_irq[28] indicates if data are coming from FIFO - (does not increment address between words) or not. - - \c length_irq[27-0] is the length of the data expressed in bytes. - */ - - volatile uint32_t tag; /**< Indicates the engine to select. - Could be any of ::dma_sg_EngineSelect_e */ -}; - -/** @brief value of ::dma_sg_regs_s.config to disable fecther's scatter/gather mode */ -#define DMA_AXI_CONFIGREG_FETCHER_DIRECT 0x00000000 - -/** @brief value of ::dma_sg_regs_s.config to disable pusher's scatter/gather mode */ -#define DMA_AXI_CONFIGREG_PUSHER_DIRECT 0x00000000 - -/** @brief value of ::dma_sg_regs_s.config to enable fecther's scatter/gather mode */ -#define DMA_AXI_CONFIGREG_FETCHER_INDIRECT 0x00000001 - -/** @brief value of ::dma_sg_regs_s.config to enable pusher's scatter/gather mode */ -#define DMA_AXI_CONFIGREG_PUSHER_INDIRECT 0x00000002 - -/** @brief value of ::dma_sg_regs_s.config to stop pusher at the end of the current block */ -#define DMA_AXI_CONFIGREG_STOP_FETCHER 0x00000004 - -/** @brief value of ::dma_sg_regs_s.config to stop pusher at the end of the current block */ -#define DMA_AXI_CONFIGREG_STOP_PUSHER 0x00000008 - -/** @brief value of ::dma_sg_regs_s.config to softreset the processing module */ -#define DMA_AXI_CONFIGREG_SOFTRESET 0x00000010 - - -/** @brief value of ::dma_sg_regs_s.config to enable pusher's scatter/gather mode */ -#define DMA_AXI_CONFIGREG_INDIRECT 0x00000002 - - -/** @brief value of ::dma_sg_regs_s.start to start fetcher */ -#define DMA_AXI_STARTREG_FETCH 0x00000001 - -/** @brief value of ::dma_sg_regs_s.start to start pusher */ -#define DMA_AXI_STARTREG_PUSH 0x00000002 - - -/** @brief ::dma_sg_regs_s.status mask for fetcher busy bit */ -#define DMA_AXI_STATUSREG_MASK_FETCHER_BUSY 0x00000001 - -/** @brief ::dma_sg_regs_s.status mask for pusher busy bit */ -#define DMA_AXI_STATUSREG_MASK_PUSHER_BUSY 0x00000002 - -/** @brief ::dma_sg_regs_s.status mask for input fifo almost full bit */ -#define DMA_AXI_STATUSREG_MASK_FIFOIN_AF 0x00000004 - -/** @brief ::dma_sg_regs_s.status mask for core module busy bit */ -#define DMA_AXI_STATUSREG_MASK_CORE_BUSY 0x00000008 - -/** @brief ::dma_sg_regs_s.status mask for input fifo not empty bit */ -#define DMA_AXI_STATUSREG_MASK_FIFOIN_NOT_EMPTY 0x00000010 - -/** @brief ::dma_sg_regs_s.status mask for pusher waiting FIFO bit */ -#define DMA_AXI_STATUSREG_MASK_PUSHER_WAIT 0x00000020 - -/** @brief ::dma_sg_regs_s.status mask for soft reset bit */ -#define DMA_AXI_STATUSREG_MASK_SOFT_RESET 0x00000040 - -/** @brief ::dma_sg_regs_s.status mask for number of data in output fifo */ -#define DMA_AXI_STATUSREG_MASK_FIFOOUT_NDATA 0xFFFF0000 - -/** @brief ::dma_sg_regs_s.status right shift for number of data in output fifo */ -#define DMA_AXI_STATUSREG_LSB_FIFOOUT_NDATA 16 - - -/** @brief ::dma_sg_regs_s.Rawstatus mask for fetcher error bit */ -#define DMA_AXI_RAWSTATREG_MASK_FETCHER_ERROR 0x00000004 - -/** @brief ::dma_sg_regs_s.Rawstatus mask for pusher error bit */ -#define DMA_AXI_RAWSTATREG_MASK_PUSHER_ERROR 0x00000020 - - -/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered at the end of each block (if enabled in the descriptor - scatter-gather only) - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_FETCHER_ENDOFBLOCK_EN 0X00000001 - -/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered when reaching a block with Stop=1 (or end of direct transfer) - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_FETCHER_STOPPED_EN 0X00000002 - -/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered when an error response is received from AXI - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_FETCHER_ERROR_EN 0X00000004 - -/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered at the end of each block (if enabled in the descriptor - scatter-gather only) - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_PUSHER_ENDBLOCK_EN 0X00000008 - -/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered when reaching a block with Stop=1 (or end of direct transfer) - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_PUSHER_STOPPED_EN 0X00000010 - -/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered when an error response is received from AXI - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_PUSHER_ERROR_EN 0X00000020 - -/** @brief value of ::dma_sg_regs_s.int_en to enable all the enable lines - Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr -*/ -#define DMA_AXI_INTENSETREG_ALL_EN 0X0000003F - - - -/** @brief ::dma_axi_descr_t.length_irq mask for data length */ -#define DMA_AXI_DESCR_MASK_LENGTH 0x0FFFFFFF - -/** @brief ::dma_axi_descr_t.length_irq right shift for data length */ -#define DMA_AXI_DESCR_LSB_LENGTH 0 - - -/** @brief Indicates to the DMA that addressing in constant mode (pointing to a FIFO) */ -#define DMA_AXI_DESCR_CONST_ADDR 0x10000000 -/** @brief Indicates to the DMA to realign data on 32 bits words */ -#define DMA_AXI_DESCR_REALIGN 0x20000000 -/** @brief Indicates to the DMA to discard fetched data */ -#define DMA_AXI_DESCR_DISCARD 0x40000000 -#define DMA_AXI_DESCR_INT_ENABLE 0x80000000 -#define DMA_AXI_DESCR_INT_DISABLE 0x00000000 - -/** @brief Indicates to the DMA to not fetch another descriptor */ -#define DMA_AXI_DESCR_NEXT_STOP ((struct dma_sg_descr_s*)0x00000001) - -#endif /* DMA_SG_CONFIG_H */ +/** + * @file + * @brief Describes the DMA registers + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_DMA_H +#define SX_DMA_H + +#include +#include "cryptolib_def.h" +/** +* @brief Defines for accessing DMA registers +*/ +#define ADDR_DMA_FETCH_ADDR (ADDR_CRYPTOMASTER_REGS + 0x0000) /**< Start address of data block */ +#define ADDR_DMA_FETCH_LEN (ADDR_CRYPTOMASTER_REGS + 0x0008) /**< Length of data block */ +#define ADDR_DMA_FETCH_TAG (ADDR_CRYPTOMASTER_REGS + 0x000C) /**< User tag */ +#define ADDR_DMA_PUSH_ADDR (ADDR_CRYPTOMASTER_REGS + 0x0010) /**< Start address of data block */ +#define ADDR_DMA_PUSH_LEN (ADDR_CRYPTOMASTER_REGS + 0x0018) /**< Length of data block */ +#define ADDR_DMA_INT_EN (ADDR_CRYPTOMASTER_REGS + 0x001C) /**< Interrupt enable */ +#define ADDR_DMA_INT_EN_SET (ADDR_CRYPTOMASTER_REGS + 0x0020) /**< Interrupt enable set */ +#define ADDR_DMA_INT_EN_CLR (ADDR_CRYPTOMASTER_REGS + 0x0024) /**< Interrupt enable clear */ +#define ADDR_DMA_INT_STAT_RAW (ADDR_CRYPTOMASTER_REGS + 0x0028) /**< Interrupt raw status */ +#define ADDR_DMA_INT_STAT (ADDR_CRYPTOMASTER_REGS + 0x002C) /**< Interrupt status */ +#define ADDR_DMA_INT_STAT_CLR (ADDR_CRYPTOMASTER_REGS + 0x0030) /**< Interrupt status clear */ +#define ADDR_DMA_CONFIG (ADDR_CRYPTOMASTER_REGS + 0x0034) /**< Configuration */ +#define ADDR_DMA_START (ADDR_CRYPTOMASTER_REGS + 0x0038) /**< Start fetch & push */ +#define ADDR_DMA_STATUS (ADDR_CRYPTOMASTER_REGS + 0x003C) /**< Status */ + +/** +* @brief Structure that represent a descriptor for the DMA module (in scatter-gather mode). +*/ +struct dma_sg_descr_s { + volatile void * volatile addr; /**< Address of the first byte of data to be fetched/pushed */ + volatile struct dma_sg_descr_s * volatile next_descr; /**< Pointer to the next valid + descriptor or indicates + that the current descriptor + is the last. + - \c next_descr[31:2] address of next descriptor, they are ignored on + last descriptor.\n The 2 LSB are always zero as DMA handles 32 bits word + - \c next_descr[1] is not used + - \c next_descr[0] is the stop bit. If high, the DMA will not fetch + another descriptor, the stop indicates the last descriptor */ + volatile uint32_t length_irq; /**< length and flags associated to a descriptor. + - \c length_irq[31] is not used + - \c length_irq[30] allows data discarding. When high, data is fetched + but not written to the destination + - \c length_irq[29] allows data realignment on 32 bits when high.\n Padding is discarded + from output data. \n The realignment \e must be used: + - with the last descriptor of a list of descriptors + - to realign different items in a list of descriptors + . + The realignment must not be used when a message is split in + multiple unaligned blocks to concatenate on output. + - \c length_irq[28] indicates if data are coming from FIFO + (does not increment address between words) or not. + - \c length_irq[27-0] is the length of the data expressed in bytes. + */ + + volatile uint32_t tag; /**< Indicates the engine to select. + Could be any of ::dma_sg_EngineSelect_e */ +}; + +/** @brief value of ::dma_sg_regs_s.config to disable fecther's scatter/gather mode */ +#define DMA_AXI_CONFIGREG_FETCHER_DIRECT 0x00000000 + +/** @brief value of ::dma_sg_regs_s.config to disable pusher's scatter/gather mode */ +#define DMA_AXI_CONFIGREG_PUSHER_DIRECT 0x00000000 + +/** @brief value of ::dma_sg_regs_s.config to enable fecther's scatter/gather mode */ +#define DMA_AXI_CONFIGREG_FETCHER_INDIRECT 0x00000001 + +/** @brief value of ::dma_sg_regs_s.config to enable pusher's scatter/gather mode */ +#define DMA_AXI_CONFIGREG_PUSHER_INDIRECT 0x00000002 + +/** @brief value of ::dma_sg_regs_s.config to stop pusher at the end of the current block */ +#define DMA_AXI_CONFIGREG_STOP_FETCHER 0x00000004 + +/** @brief value of ::dma_sg_regs_s.config to stop pusher at the end of the current block */ +#define DMA_AXI_CONFIGREG_STOP_PUSHER 0x00000008 + +/** @brief value of ::dma_sg_regs_s.config to softreset the processing module */ +#define DMA_AXI_CONFIGREG_SOFTRESET 0x00000010 + + +/** @brief value of ::dma_sg_regs_s.config to enable pusher's scatter/gather mode */ +#define DMA_AXI_CONFIGREG_INDIRECT 0x00000002 + + +/** @brief value of ::dma_sg_regs_s.start to start fetcher */ +#define DMA_AXI_STARTREG_FETCH 0x00000001 + +/** @brief value of ::dma_sg_regs_s.start to start pusher */ +#define DMA_AXI_STARTREG_PUSH 0x00000002 + + +/** @brief ::dma_sg_regs_s.status mask for fetcher busy bit */ +#define DMA_AXI_STATUSREG_MASK_FETCHER_BUSY 0x00000001 + +/** @brief ::dma_sg_regs_s.status mask for pusher busy bit */ +#define DMA_AXI_STATUSREG_MASK_PUSHER_BUSY 0x00000002 + +/** @brief ::dma_sg_regs_s.status mask for input fifo almost full bit */ +#define DMA_AXI_STATUSREG_MASK_FIFOIN_AF 0x00000004 + +/** @brief ::dma_sg_regs_s.status mask for core module busy bit */ +#define DMA_AXI_STATUSREG_MASK_CORE_BUSY 0x00000008 + +/** @brief ::dma_sg_regs_s.status mask for input fifo not empty bit */ +#define DMA_AXI_STATUSREG_MASK_FIFOIN_NOT_EMPTY 0x00000010 + +/** @brief ::dma_sg_regs_s.status mask for pusher waiting FIFO bit */ +#define DMA_AXI_STATUSREG_MASK_PUSHER_WAIT 0x00000020 + +/** @brief ::dma_sg_regs_s.status mask for soft reset bit */ +#define DMA_AXI_STATUSREG_MASK_SOFT_RESET 0x00000040 + +/** @brief ::dma_sg_regs_s.status mask for number of data in output fifo */ +#define DMA_AXI_STATUSREG_MASK_FIFOOUT_NDATA 0xFFFF0000 + +/** @brief ::dma_sg_regs_s.status right shift for number of data in output fifo */ +#define DMA_AXI_STATUSREG_LSB_FIFOOUT_NDATA 16 + + +/** @brief ::dma_sg_regs_s.Rawstatus mask for fetcher error bit */ +#define DMA_AXI_RAWSTATREG_MASK_FETCHER_ERROR 0x00000004 + +/** @brief ::dma_sg_regs_s.Rawstatus mask for pusher error bit */ +#define DMA_AXI_RAWSTATREG_MASK_PUSHER_ERROR 0x00000020 + + +/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered at the end of each block (if enabled in the descriptor - scatter-gather only) + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_FETCHER_ENDOFBLOCK_EN 0X00000001 + +/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered when reaching a block with Stop=1 (or end of direct transfer) + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_FETCHER_STOPPED_EN 0X00000002 + +/** @brief value of ::dma_sg_regs_s.int_en to enable the fetcher triggered when an error response is received from AXI + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_FETCHER_ERROR_EN 0X00000004 + +/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered at the end of each block (if enabled in the descriptor - scatter-gather only) + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_PUSHER_ENDBLOCK_EN 0X00000008 + +/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered when reaching a block with Stop=1 (or end of direct transfer) + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_PUSHER_STOPPED_EN 0X00000010 + +/** @brief value of ::dma_sg_regs_s.int_en to enable the pusher triggered when an error response is received from AXI + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_PUSHER_ERROR_EN 0X00000020 + +/** @brief value of ::dma_sg_regs_s.int_en to enable all the enable lines + Must be set via ::dma_sg_regs_s.int_en_set and clear via ::dma_sg_regs_s.int_en_clr +*/ +#define DMA_AXI_INTENSETREG_ALL_EN 0X0000003F + + + +/** @brief ::dma_axi_descr_t.length_irq mask for data length */ +#define DMA_AXI_DESCR_MASK_LENGTH 0x0FFFFFFF + +/** @brief ::dma_axi_descr_t.length_irq right shift for data length */ +#define DMA_AXI_DESCR_LSB_LENGTH 0 + + +/** @brief Indicates to the DMA that addressing in constant mode (pointing to a FIFO) */ +#define DMA_AXI_DESCR_CONST_ADDR 0x10000000 +/** @brief Indicates to the DMA to realign data on 32 bits words */ +#define DMA_AXI_DESCR_REALIGN 0x20000000 +/** @brief Indicates to the DMA to discard fetched data */ +#define DMA_AXI_DESCR_DISCARD 0x40000000 +#define DMA_AXI_DESCR_INT_ENABLE 0x80000000 +#define DMA_AXI_DESCR_INT_DISABLE 0x00000000 + +/** @brief Indicates to the DMA to not fetch another descriptor */ +#define DMA_AXI_DESCR_NEXT_STOP ((struct dma_sg_descr_s*)0x00000001) + +#endif /* DMA_SG_CONFIG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_curves.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_curves.h index cd29821..f3309ad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_curves.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_curves.h @@ -1,100 +1,100 @@ -/** - * @file - * @brief This file contains the hard-coded curve parameters - * for common ECC - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_ECC_CURVES_H -#define SX_ECC_CURVES_H - -#include -#include -#include "cryptolib_types.h" - - -/** @brief The (mathematical) implemented fields used for ECC */ -typedef enum sx_ecc_curve_type -{ - sx_ecc_curve_prime, /**< Prime field curve*/ - sx_ecc_curve_binary, /**< Binary field curve*/ - sx_ecc_curve_edwards, /**< Edwards curve */ - sx_ecc_curve_unspecified /**< If user does not care the field */ -} sx_ecc_curve_type; - -/** - * @brief Build the ::sx_ecc_curve_t.pk_flags for a user-defined curve - * - * The ECC PK engine is expecting a few flags to be set by the caller (i.e. - * the field to use for computation). - * These flags are correctly set for predefined curves but not for user-defined - * curves. To allow customers to use their own curves, this function is provided. - * (see BA414EP_PKE_Datasheet.pdf for the different flag meanings). - * - * \param curve_type curve type used to do the ecc computation (see ::sx_ecc_curve_type) - * - * \return a \p flags value which may be used for ECC operation - */ -uint32_t sx_ecc_build_pk_flags(enum sx_ecc_curve_type curve_type); - - -/** - * @brief Define the default case when no specific BA414EP flags are required - * (see ::sx_ecc_build_pk_flags) - */ -#define SX_ECC_DEFAULT_PK_FLAGS (sx_ecc_build_pk_flags(sx_ecc_curve_unspecified)) - -/** @brief ECC structure for ECC curve definition */ -typedef struct sx_ecc_curve_t { - block_t params; /**< points to predefined curve params - formatted as {q, n, Gx, Gy, a, b} and - represented in big number array of uint8 (big endian). - The fileds are: - - q, the modulus (or the reduction polynomial for ECC Weierstrass binary) - - n, the order of the curve - - Gx, Gy, the x and y coordinates of the generator - - a, b (or d for Edwards curve), the coefficients defining the ECC curve*/ - uint32_t pk_flags; /**< required flags for the PK engine*/ - uint32_t bytesize; /**< size expressed in bytes */ -} sx_ecc_curve_t; - - -/** - * @brief Get size of \p curve in bytes - * @param curve is a pointer to a ::sx_ecc_curve_t structure describing the curve - */ -uint32_t sx_ecc_curve_bytesize(const sx_ecc_curve_t *curve); - -extern const sx_ecc_curve_t sx_ecc_curve_p192; -extern const sx_ecc_curve_t sx_ecc_curve_p224; -extern const sx_ecc_curve_t sx_ecc_curve_p256; -extern const sx_ecc_curve_t sx_ecc_curve_p384; -extern const sx_ecc_curve_t sx_ecc_curve_p521; -extern const sx_ecc_curve_t sx_ecc_curve_p256k1; -extern const sx_ecc_curve_t sx_ecc_curve_b163; -extern const sx_ecc_curve_t sx_ecc_curve_b233; -extern const sx_ecc_curve_t sx_ecc_curve_b283; -extern const sx_ecc_curve_t sx_ecc_curve_b409; -extern const sx_ecc_curve_t sx_ecc_curve_b571; -extern const sx_ecc_curve_t sx_ecc_curve_k163; -extern const sx_ecc_curve_t sx_ecc_curve_k233; -extern const sx_ecc_curve_t sx_ecc_curve_k283; -extern const sx_ecc_curve_t sx_ecc_curve_k409; -extern const sx_ecc_curve_t sx_ecc_curve_k571; -extern const sx_ecc_curve_t sx_ecc_curve_e521; -extern const sx_ecc_curve_t sx_ecc_curve_curve25519; -extern const sx_ecc_curve_t sx_ecc_curve_curve448; -extern const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v1; -extern const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v2; -extern const sx_ecc_curve_t sx_ecc_curve_sm2_fm257; -extern const sx_ecc_curve_t sx_ecc_brainpoolP160r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP192r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP224r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP256r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP320r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP384r1; -extern const sx_ecc_curve_t sx_ecc_brainpoolP512r1; - - -#endif +/** + * @file + * @brief This file contains the hard-coded curve parameters + * for common ECC + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_ECC_CURVES_H +#define SX_ECC_CURVES_H + +#include +#include +#include "cryptolib_types.h" + + +/** @brief The (mathematical) implemented fields used for ECC */ +typedef enum sx_ecc_curve_type +{ + sx_ecc_curve_prime, /**< Prime field curve*/ + sx_ecc_curve_binary, /**< Binary field curve*/ + sx_ecc_curve_edwards, /**< Edwards curve */ + sx_ecc_curve_unspecified /**< If user does not care the field */ +} sx_ecc_curve_type; + +/** + * @brief Build the ::sx_ecc_curve_t.pk_flags for a user-defined curve + * + * The ECC PK engine is expecting a few flags to be set by the caller (i.e. + * the field to use for computation). + * These flags are correctly set for predefined curves but not for user-defined + * curves. To allow customers to use their own curves, this function is provided. + * (see BA414EP_PKE_Datasheet.pdf for the different flag meanings). + * + * \param curve_type curve type used to do the ecc computation (see ::sx_ecc_curve_type) + * + * \return a \p flags value which may be used for ECC operation + */ +uint32_t sx_ecc_build_pk_flags(enum sx_ecc_curve_type curve_type); + + +/** + * @brief Define the default case when no specific BA414EP flags are required + * (see ::sx_ecc_build_pk_flags) + */ +#define SX_ECC_DEFAULT_PK_FLAGS (sx_ecc_build_pk_flags(sx_ecc_curve_unspecified)) + +/** @brief ECC structure for ECC curve definition */ +typedef struct sx_ecc_curve_t { + block_t params; /**< points to predefined curve params + formatted as {q, n, Gx, Gy, a, b} and + represented in big number array of uint8 (big endian). + The fileds are: + - q, the modulus (or the reduction polynomial for ECC Weierstrass binary) + - n, the order of the curve + - Gx, Gy, the x and y coordinates of the generator + - a, b (or d for Edwards curve), the coefficients defining the ECC curve*/ + uint32_t pk_flags; /**< required flags for the PK engine*/ + uint32_t bytesize; /**< size expressed in bytes */ +} sx_ecc_curve_t; + + +/** + * @brief Get size of \p curve in bytes + * @param curve is a pointer to a ::sx_ecc_curve_t structure describing the curve + */ +uint32_t sx_ecc_curve_bytesize(const sx_ecc_curve_t *curve); + +extern const sx_ecc_curve_t sx_ecc_curve_p192; +extern const sx_ecc_curve_t sx_ecc_curve_p224; +extern const sx_ecc_curve_t sx_ecc_curve_p256; +extern const sx_ecc_curve_t sx_ecc_curve_p384; +extern const sx_ecc_curve_t sx_ecc_curve_p521; +extern const sx_ecc_curve_t sx_ecc_curve_p256k1; +extern const sx_ecc_curve_t sx_ecc_curve_b163; +extern const sx_ecc_curve_t sx_ecc_curve_b233; +extern const sx_ecc_curve_t sx_ecc_curve_b283; +extern const sx_ecc_curve_t sx_ecc_curve_b409; +extern const sx_ecc_curve_t sx_ecc_curve_b571; +extern const sx_ecc_curve_t sx_ecc_curve_k163; +extern const sx_ecc_curve_t sx_ecc_curve_k233; +extern const sx_ecc_curve_t sx_ecc_curve_k283; +extern const sx_ecc_curve_t sx_ecc_curve_k409; +extern const sx_ecc_curve_t sx_ecc_curve_k571; +extern const sx_ecc_curve_t sx_ecc_curve_e521; +extern const sx_ecc_curve_t sx_ecc_curve_curve25519; +extern const sx_ecc_curve_t sx_ecc_curve_curve448; +extern const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v1; +extern const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v2; +extern const sx_ecc_curve_t sx_ecc_curve_sm2_fm257; +extern const sx_ecc_curve_t sx_ecc_brainpoolP160r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP192r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP224r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP256r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP320r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP384r1; +extern const sx_ecc_curve_t sx_ecc_brainpoolP512r1; + + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_keygen_alg.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_keygen_alg.h index c7364ae..8dd3f30 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_keygen_alg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecc_keygen_alg.h @@ -1,147 +1,147 @@ -/** - * @file - * @brief Generate ECC key - * - * Default format for ECC is big array of uint8_t (big endian) for both - * private and public key. Public key is represented as the concatenation - * of x and y coordinate for all but Montgomery and EdDSA. - * - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef ECC_KEYGEN_ALG -#define ECC_KEYGEN_ALG - -#include -#include "compiler_extentions.h" -#include "cryptolib_types.h" -#include "sx_rng.h" - -/** - * @brief Validates the ECC public key is a point on the curve - * (valid for Weierstrass prime, binary or Edwards) - * - * @param domain Curve parameters - * @param pub Public key to validate - * @param size Size of one element (expressed in bytes) - * @param curve_flags Curve acceleration parameters - * @return ::CRYPTOLIB_SUCCESS if public key is valid - * @return ::CRYPTOLIB_CRYPTO_ERR if public key is invalid - * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecc_validate_public_key( - block_t domain, - block_t pub, - uint32_t size, - uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Generates an ECC key pair (private and public key) - * (valid for Weierstrass prime, binary or Edwards) - * - * @param domain Curve parameters (domain) - * @param pub Public key to be generated - * @param priv Private key to be generated - * @param size Size of one element (expressed in bytes) - * @param curve_flags Curve acceleration parameters - * @param rng Random number generator used - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE - */ - uint32_t ecc_generate_keypair( - block_t domain, - block_t pub, - block_t priv, - uint32_t size, - uint32_t curve_flags, - struct sx_rng rng) CHECK_RESULT; - -/** - * @brief Generates an ECC private key - * (valid for Weierstrass prime, binary or Edwards) - * - * @param n Order coming from the curve parameters - * @param priv Private key to be generated - * @param rng Random number generator used - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if modulus length is bigger - * than ::ECC_MAX_KEY_SIZE - */ - uint32_t ecc_generate_private_key( - block_t n, - block_t priv, - struct sx_rng rng) CHECK_RESULT; - -/** - * @brief Generates a ECC public key - * (Weierstrass prime, binary or Edwards) - * based on the curve and a given private key. - * - * @param curve Curve parameters (domain) - * @param pub Public key to be generated - * @param priv Private key for which public key is desired - * @param size Size of one element (expressed in bytes) - * @param curve_flags curve acceleration parameters - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecc_generate_public_key( - block_t curve, - block_t pub, - block_t priv, - uint32_t size, - uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Generates a key pair for ECC Montgomery curve \p curve - * - * @param domain Curve parameters (domain) - * @param pub Public key to be generated - * @param priv Private key to be generated - * @param size Size of one element (expressed in bytes) - * @param curve_flags Curve acceleration parameters - * @param rng Used random number generator - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecc_montgomery_generate_keypair( - block_t domain, - block_t pub, - block_t priv, - uint32_t size, - uint32_t curve_flags, - struct sx_rng rng) CHECK_RESULT; - -/** - * @brief Generates a Montgomery ECC private key - * - * @param priv Private key to be generated - * @param rng Used random number generator - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if private key length is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecc_montgomery_generate_private_key( - block_t priv, - struct sx_rng rng); - -/** - * @brief Generates a Montgomery ECC public key - * based on the curve and a given private key. - * - * @param curve Curve parameters (domain) - * @param pub Public key to be generated - * @param priv Private key for which public key is desired - * @param size Size of one element (expressed in bytes) - * @param curve_flags Curve acceleration parameters - * @return ::CRYPTOLIB_SUCCESS if no error - * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecc_montgomery_generate_public_key( - block_t curve, - block_t pub, - block_t priv, - uint32_t size, - uint32_t curve_flags) CHECK_RESULT; - -#endif +/** + * @file + * @brief Generate ECC key + * + * Default format for ECC is big array of uint8_t (big endian) for both + * private and public key. Public key is represented as the concatenation + * of x and y coordinate for all but Montgomery and EdDSA. + * + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef ECC_KEYGEN_ALG +#define ECC_KEYGEN_ALG + +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" +#include "sx_rng.h" + +/** + * @brief Validates the ECC public key is a point on the curve + * (valid for Weierstrass prime, binary or Edwards) + * + * @param domain Curve parameters + * @param pub Public key to validate + * @param size Size of one element (expressed in bytes) + * @param curve_flags Curve acceleration parameters + * @return ::CRYPTOLIB_SUCCESS if public key is valid + * @return ::CRYPTOLIB_CRYPTO_ERR if public key is invalid + * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecc_validate_public_key( + block_t domain, + block_t pub, + uint32_t size, + uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Generates an ECC key pair (private and public key) + * (valid for Weierstrass prime, binary or Edwards) + * + * @param domain Curve parameters (domain) + * @param pub Public key to be generated + * @param priv Private key to be generated + * @param size Size of one element (expressed in bytes) + * @param curve_flags Curve acceleration parameters + * @param rng Random number generator used + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE + */ + uint32_t ecc_generate_keypair( + block_t domain, + block_t pub, + block_t priv, + uint32_t size, + uint32_t curve_flags, + struct sx_rng rng) CHECK_RESULT; + +/** + * @brief Generates an ECC private key + * (valid for Weierstrass prime, binary or Edwards) + * + * @param n Order coming from the curve parameters + * @param priv Private key to be generated + * @param rng Random number generator used + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if modulus length is bigger + * than ::ECC_MAX_KEY_SIZE + */ + uint32_t ecc_generate_private_key( + block_t n, + block_t priv, + struct sx_rng rng) CHECK_RESULT; + +/** + * @brief Generates a ECC public key + * (Weierstrass prime, binary or Edwards) + * based on the curve and a given private key. + * + * @param curve Curve parameters (domain) + * @param pub Public key to be generated + * @param priv Private key for which public key is desired + * @param size Size of one element (expressed in bytes) + * @param curve_flags curve acceleration parameters + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecc_generate_public_key( + block_t curve, + block_t pub, + block_t priv, + uint32_t size, + uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Generates a key pair for ECC Montgomery curve \p curve + * + * @param domain Curve parameters (domain) + * @param pub Public key to be generated + * @param priv Private key to be generated + * @param size Size of one element (expressed in bytes) + * @param curve_flags Curve acceleration parameters + * @param rng Used random number generator + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecc_montgomery_generate_keypair( + block_t domain, + block_t pub, + block_t priv, + uint32_t size, + uint32_t curve_flags, + struct sx_rng rng) CHECK_RESULT; + +/** + * @brief Generates a Montgomery ECC private key + * + * @param priv Private key to be generated + * @param rng Used random number generator + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if private key length is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecc_montgomery_generate_private_key( + block_t priv, + struct sx_rng rng); + +/** + * @brief Generates a Montgomery ECC public key + * based on the curve and a given private key. + * + * @param curve Curve parameters (domain) + * @param pub Public key to be generated + * @param priv Private key for which public key is desired + * @param size Size of one element (expressed in bytes) + * @param curve_flags Curve acceleration parameters + * @return ::CRYPTOLIB_SUCCESS if no error + * ::CRYPTOLIB_UNSUPPORTED_ERR if \p size is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecc_montgomery_generate_public_key( + block_t curve, + block_t pub, + block_t priv, + uint32_t size, + uint32_t curve_flags) CHECK_RESULT; + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecdsa_alg.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecdsa_alg.h index b83a36e..96f7dee 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecdsa_alg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_ecdsa_alg.h @@ -1,175 +1,175 @@ -/** - * @file - * @brief Defines the procedures to make ECDSA operations with - * the BA414EP pub key - * - * Default format for ECC is big array of uint8_t (big endian) for both - * private and public key. Public key is represented as the concatenation - * of x and y coordinate for all but Montgomery and EdDSA. - * - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_ECDSA_ALG_H -#define SX_ECDSA_ALG_H - -#include -#include "cryptolib_types.h" -#include "sx_ecc_curves.h" -#include "sx_hash.h" -#include "sx_rng.h" - - -/** - * @brief Validates curve parameters when given by the host \p curve - * - * The checks done over the curve parameters are described in BA414EP_PKE_DataSheet - * Section Elliptic Curve Digital Signature Algorithm - * @param curve the ECC curve to validate - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * ::CRYPTOLIB_CRYPTO_ERR if there is an issue with the parameters - */ -uint32_t ecdsa_validate_domain (const sx_ecc_curve_t *curve); - -/** - * @brief Verify an ECDSA signature from a \p formatted_digest - * - * @param curve Selects the ECC curve - * @param formatted_digest Digest to verify against \p signature. - * @param key ECC public key - * @param signature Signature to verify against the \p formatted_digest - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * ::CRYPTOLIB_INVALID_SIGN_ERR if verification failed - * - * \note the \p formatted_digest corresponds to the digest truncated if required - * to match the ecc curve element size and also right shifted if required - * (left padded with zeros) - */ -uint32_t ecdsa_verify_signature_digest( - const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key, - block_t signature); - -/** - * @brief Configure hardware for signature generation. - * - * Load the curve parameters, the key and formatted_digest. Those are - * needed once before attempting to generate signatures. - * @param curve Selects the ECC curve - * @param formatted_digest Digest to generate the signature. - * @param key ECC private key - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * - * \note the \p formatted_digest corresponds to the digest truncated if required - * to match the ecc curve element size and also right shifted if required - * (left padded with zeros) - */ -uint32_t sx_ecdsa_configure_signature( - const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key); - -/** - * @brief Attempt to compute an ECDSA signature - * - * This function tries to generate a signature and gives up immediately in case - * of error. It is under the caller responsibility to attempt again to generate - * a signature. - * @param curve Selects the ECC curve - * @param signature Output signature of the \p formatted_digest - * @param rng Used random number generator - * @return ::CRYPTOLIB_SUCCESS if the signature is generated and valid, - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * ::CRYPTOLIB_INVALID_SIGN_ERR if the generated signature is not valid - * - * \warning The digest and the key must be already loaded (i.e: by calling - * ::sx_ecdsa_configure_signature first) - * \warning It is required to call ::sx_ecdsa_configure_signature \e before - * attempting to generate a signature as a few parameters have to be - * loaded. - */ -uint32_t sx_ecdsa_attempt_signature( - const sx_ecc_curve_t *curve, - block_t signature, - struct sx_rng rng); - -/** - * @brief Verifies a given signature corresponds to a given message - * - * @param curve Selects the ECC curve - * @param message Message to hash and verify against \p signature - * @param key ECC public key - * @param signature Signature to check - * @param hash_fct Select hash algorithm to use on \p message - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * ::CRYPTOLIB_INVALID_SIGN_ERR if signature verification failed - */ -uint32_t ecdsa_verify_signature( - const sx_ecc_curve_t *curve, - block_t message, - block_t key, - block_t signature, - sx_hash_fct_t hash_fct); - -/** - * @brief Compute a ECDSA signature for a given digest - * - * Unlike ::sx_ecdsa_attempt_signature, this function will retry in case of - * invalid generated signature and both the formatted_digest and the key are - * internally loaded. - * - * @param curve Selects the ECC curve - * @param formatted_digest Digest to use to generate \p signature. - * @param key ECC private key - * @param signature Output signature of the \p formatted_digest - * @param rng Used random number generator - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - * ::CRYPTOLIB_INVALID_SIGN_ERR if signature verification failed - * - * \note the \p formatted_digest corresponds to the digest truncated if required - * to match the ecc curve element size and also right shifted if required - * (left padded with zeros) - */ - -uint32_t ecdsa_generate_signature_digest( - const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key, - block_t signature, - struct sx_rng rng); - -/** - * @brief Generates an ECDSA signature from a \p message - * - * @param curve Selects the ECC curve - * @param message Message to sign with ECDSA - * @param key ECC Private key - * @param signature Location to store the signature - * @param hash_fct Select hash algorithm to use on \p message - * @param rng Used random number generator - * @return ::CRYPTOLIB_SUCCESS if successful - * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve - * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE - */ -uint32_t ecdsa_generate_signature( - const sx_ecc_curve_t *curve, - block_t message, - block_t key, - block_t signature, - sx_hash_fct_t hash_fct, - struct sx_rng rng); - -#endif +/** + * @file + * @brief Defines the procedures to make ECDSA operations with + * the BA414EP pub key + * + * Default format for ECC is big array of uint8_t (big endian) for both + * private and public key. Public key is represented as the concatenation + * of x and y coordinate for all but Montgomery and EdDSA. + * + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_ECDSA_ALG_H +#define SX_ECDSA_ALG_H + +#include +#include "cryptolib_types.h" +#include "sx_ecc_curves.h" +#include "sx_hash.h" +#include "sx_rng.h" + + +/** + * @brief Validates curve parameters when given by the host \p curve + * + * The checks done over the curve parameters are described in BA414EP_PKE_DataSheet + * Section Elliptic Curve Digital Signature Algorithm + * @param curve the ECC curve to validate + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * ::CRYPTOLIB_CRYPTO_ERR if there is an issue with the parameters + */ +uint32_t ecdsa_validate_domain (const sx_ecc_curve_t *curve); + +/** + * @brief Verify an ECDSA signature from a \p formatted_digest + * + * @param curve Selects the ECC curve + * @param formatted_digest Digest to verify against \p signature. + * @param key ECC public key + * @param signature Signature to verify against the \p formatted_digest + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * ::CRYPTOLIB_INVALID_SIGN_ERR if verification failed + * + * \note the \p formatted_digest corresponds to the digest truncated if required + * to match the ecc curve element size and also right shifted if required + * (left padded with zeros) + */ +uint32_t ecdsa_verify_signature_digest( + const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key, + block_t signature); + +/** + * @brief Configure hardware for signature generation. + * + * Load the curve parameters, the key and formatted_digest. Those are + * needed once before attempting to generate signatures. + * @param curve Selects the ECC curve + * @param formatted_digest Digest to generate the signature. + * @param key ECC private key + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * + * \note the \p formatted_digest corresponds to the digest truncated if required + * to match the ecc curve element size and also right shifted if required + * (left padded with zeros) + */ +uint32_t sx_ecdsa_configure_signature( + const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key); + +/** + * @brief Attempt to compute an ECDSA signature + * + * This function tries to generate a signature and gives up immediately in case + * of error. It is under the caller responsibility to attempt again to generate + * a signature. + * @param curve Selects the ECC curve + * @param signature Output signature of the \p formatted_digest + * @param rng Used random number generator + * @return ::CRYPTOLIB_SUCCESS if the signature is generated and valid, + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * ::CRYPTOLIB_INVALID_SIGN_ERR if the generated signature is not valid + * + * \warning The digest and the key must be already loaded (i.e: by calling + * ::sx_ecdsa_configure_signature first) + * \warning It is required to call ::sx_ecdsa_configure_signature \e before + * attempting to generate a signature as a few parameters have to be + * loaded. + */ +uint32_t sx_ecdsa_attempt_signature( + const sx_ecc_curve_t *curve, + block_t signature, + struct sx_rng rng); + +/** + * @brief Verifies a given signature corresponds to a given message + * + * @param curve Selects the ECC curve + * @param message Message to hash and verify against \p signature + * @param key ECC public key + * @param signature Signature to check + * @param hash_fct Select hash algorithm to use on \p message + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * ::CRYPTOLIB_INVALID_SIGN_ERR if signature verification failed + */ +uint32_t ecdsa_verify_signature( + const sx_ecc_curve_t *curve, + block_t message, + block_t key, + block_t signature, + sx_hash_fct_t hash_fct); + +/** + * @brief Compute a ECDSA signature for a given digest + * + * Unlike ::sx_ecdsa_attempt_signature, this function will retry in case of + * invalid generated signature and both the formatted_digest and the key are + * internally loaded. + * + * @param curve Selects the ECC curve + * @param formatted_digest Digest to use to generate \p signature. + * @param key ECC private key + * @param signature Output signature of the \p formatted_digest + * @param rng Used random number generator + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + * ::CRYPTOLIB_INVALID_SIGN_ERR if signature verification failed + * + * \note the \p formatted_digest corresponds to the digest truncated if required + * to match the ecc curve element size and also right shifted if required + * (left padded with zeros) + */ + +uint32_t ecdsa_generate_signature_digest( + const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key, + block_t signature, + struct sx_rng rng); + +/** + * @brief Generates an ECDSA signature from a \p message + * + * @param curve Selects the ECC curve + * @param message Message to sign with ECDSA + * @param key ECC Private key + * @param signature Location to store the signature + * @param hash_fct Select hash algorithm to use on \p message + * @param rng Used random number generator + * @return ::CRYPTOLIB_SUCCESS if successful + * ::CRYPTOLIB_UNSUPPORTED_ERR if the size of one element curve + * (\c curve->bytesize) is bigger than ::ECC_MAX_KEY_SIZE + */ +uint32_t ecdsa_generate_signature( + const sx_ecc_curve_t *curve, + block_t message, + block_t key, + block_t signature, + sx_hash_fct_t hash_fct, + struct sx_rng rng); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_errors.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_errors.h index f9fb7f6..3fcec74 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_errors.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_errors.h @@ -1,71 +1,71 @@ -/** - * @file - * @brief Defines the return codes for the CryptoSoC functions - * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_ERRORS_H -#define SX_ERRORS_H - -#include - -// TODO Push all of this in a enumeration - -/** @brief Operation (whatever the kind of operation) terminated nicely */ -#define CRYPTOLIB_SUCCESS 0 - -/** - * @brief Operation involving a parameter which does not respect - * the system limitations - * - * (i.e. trying to store a byte string bigger than the reserved memory) - */ -#define CRYPTOLIB_UNSUPPORTED_ERR 1 - -/** - * @brief Operation involving a signature verification which is failing - * - * Algorithms involving signature (i.e. DSA, ECDSA, ...) may return this code - */ -#define CRYPTOLIB_INVALID_SIGN_ERR 3 - -/** - * @brief Operation failing to to data transfer over the DMA bus - * - * For instance, it can be due to too much/not enough data transferred. - */ -#define CRYPTOLIB_DMA_ERR 4 - -/** @brief Operation involving a invalid ECC point (i.e. not on a curve) */ -#define CRYPTOLIB_INVALID_POINT 5 - -/** - * @brief Operation which didn't terminate nicely and not due to any other listed error. - * - * i.e. due to a crypto engine error - */ -#define CRYPTOLIB_CRYPTO_ERR 6 - -/** @brief Operation involving a parameter detected as invalid - * - * (i.e. out of range value) - */ -#define CRYPTOLIB_INVALID_PARAM 7 - -/** - * @brief DRBG random generation can't complete - * because new entropy should be reseeded in the DRBG - */ -#define CRYPTOLIB_DRBG_RESEED_NEEDED 8 - -/** - * @brief Operation involving a signature is failing because the signature - * is not invertible. - * - * Issuing a new operation with slightly different parameters - * (i.e. random if present) may solve this issue - */ -#define CRYPTOLIB_NON_INVERT_SIGN 9 - -#endif +/** + * @file + * @brief Defines the return codes for the CryptoSoC functions + * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_ERRORS_H +#define SX_ERRORS_H + +#include + +// TODO Push all of this in a enumeration + +/** @brief Operation (whatever the kind of operation) terminated nicely */ +#define CRYPTOLIB_SUCCESS 0 + +/** + * @brief Operation involving a parameter which does not respect + * the system limitations + * + * (i.e. trying to store a byte string bigger than the reserved memory) + */ +#define CRYPTOLIB_UNSUPPORTED_ERR 1 + +/** + * @brief Operation involving a signature verification which is failing + * + * Algorithms involving signature (i.e. DSA, ECDSA, ...) may return this code + */ +#define CRYPTOLIB_INVALID_SIGN_ERR 3 + +/** + * @brief Operation failing to to data transfer over the DMA bus + * + * For instance, it can be due to too much/not enough data transferred. + */ +#define CRYPTOLIB_DMA_ERR 4 + +/** @brief Operation involving a invalid ECC point (i.e. not on a curve) */ +#define CRYPTOLIB_INVALID_POINT 5 + +/** + * @brief Operation which didn't terminate nicely and not due to any other listed error. + * + * i.e. due to a crypto engine error + */ +#define CRYPTOLIB_CRYPTO_ERR 6 + +/** @brief Operation involving a parameter detected as invalid + * + * (i.e. out of range value) + */ +#define CRYPTOLIB_INVALID_PARAM 7 + +/** + * @brief DRBG random generation can't complete + * because new entropy should be reseeded in the DRBG + */ +#define CRYPTOLIB_DRBG_RESEED_NEEDED 8 + +/** + * @brief Operation involving a signature is failing because the signature + * is not invertible. + * + * Issuing a new operation with slightly different parameters + * (i.e. random if present) may solve this issue + */ +#define CRYPTOLIB_NON_INVERT_SIGN 9 + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hash.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hash.h index 56bcaa1..872d7b2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hash.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hash.h @@ -1,225 +1,225 @@ -/** - * @file - * @brief Declares the constants and functions to make operations - * with the BA413 hash function - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_HASH_H -#define SX_HASH_H - -#include -#include "compiler_extentions.h" -#include "cryptolib_types.h" - -/** @brief Size of MD5 data block in bytes */ -#define MD5_BLOCKSIZE 64 -/** @brief Size of MD5 initialization value in bytes */ -#define MD5_INITSIZE 16 -/** @brief Size of MD5 digest in bytes */ -#define MD5_DIGESTSIZE 16 -/** @brief Size of SHA1 data block in bytes */ -#define SHA1_BLOCKSIZE 64 -/** @brief Size of SHA1 state in bytes */ -#define SHA1_STATESIZE 20 -/** @brief Size of SHA1 digest in bytes */ -#define SHA1_DIGESTSIZE 20 -/** @brief Size of SHA224 data block in bytes */ -#define SHA224_BLOCKSIZE 64 -/** @brief Size of SHA224 state in bytes */ -#define SHA224_STATESIZE 32 -/** @brief Size of SHA224 digest in bytes */ -#define SHA224_DIGESTSIZE 28 -/** @brief Size of SHA256 data block in bytes */ -#define SHA256_BLOCKSIZE 64 -/** @brief Size of SHA256 state in bytes */ -#define SHA256_STATESIZE 32 -/** @brief Size of SHA256 digest in bytes */ -#define SHA256_DIGESTSIZE 32 -/** @brief Size of SHA384 data block in bytes */ -#define SHA384_BLOCKSIZE 128 -/** @brief Size of SHA384 state in bytes */ -#define SHA384_STATESIZE 64 -/** @brief Size of SHA384 digest in bytes */ -#define SHA384_DIGESTSIZE 48 -/** @brief Size of SHA512 data block in bytes */ -#define SHA512_BLOCKSIZE 128 -/** @brief Size of SHA512 state in bytes */ -#define SHA512_STATESIZE 64 -/** @brief Size of SHA512 digest in bytes */ -#define SHA512_DIGESTSIZE 64 -/** @brief Size of SM3 digest in bytes */ -#define SM3_BLOCKSIZE 64 -/** @brief Size of SM3 initialization value in bytes */ -#define SM3_INITSIZE 32 -/** @brief Size of SM3 digest in bytes */ -#define SM3_DIGESTSIZE 32 -/** @brief Maximum block size to be supported */ -#define MAX_BLOCKSIZE SHA512_BLOCKSIZE -/** @brief Maximum digest size to be supported */ -#define MAX_DIGESTSIZE SHA512_DIGESTSIZE -/** @brief Maximum number of entries in sx_hash_array_blk and sx_hmac_array_blk */ -#define SX_HASH_ARRAY_MAX_ENTRIES 8 - -/** -* @brief Enumeration of the supported hash algorithms -*/ -typedef enum sx_hash_fct_e -{ - e_MD5 = 1, /**< MD5 */ - e_SHA1 = 2, /**< SHA1 */ - e_SHA224 = 3, /**< SHA224 */ - e_SHA256 = 4, /**< SHA256 */ - e_SHA384 = 5, /**< SHA384 */ - e_SHA512 = 6, /**< SHA512 */ - e_SM3 = 7 /**< SM3 */ -} sx_hash_fct_t; - -/** - * @brief: Initialization vector for SM3 context - * https://tools.ietf.org/id/draft-oscca-cfrg-sm3-01.html#rfc.section.4.1 - */ -extern const uint8_t sx_sm3_iv[SM3_DIGESTSIZE]; - -/** - * @brief: Initial value for SHA-1 - * http://dx.doi.org/10.6028/NIST.FIPS.180-4 - */ -extern const uint8_t sx_sha1_initial_value[SHA1_STATESIZE]; - -/** - * @brief: Initial value for SHA-224 - * http://dx.doi.org/10.6028/NIST.FIPS.180-4 - */ -extern const uint8_t sx_sha224_initial_value[SHA224_STATESIZE]; - -/** - * @brief: Initial value for SHA-256 - * http://dx.doi.org/10.6028/NIST.FIPS.180-4 - */ -extern const uint8_t sx_sha256_initial_value[SHA256_STATESIZE]; - -/** - * @brief: Initial value for SHA-384 - * http://dx.doi.org/10.6028/NIST.FIPS.180-4 - */ -extern const uint8_t sx_sha384_initial_value[SHA384_STATESIZE]; - -/** - * @brief: Initial value for SHA-512 - * http://dx.doi.org/10.6028/NIST.FIPS.180-4 - */ -extern const uint8_t sx_sha512_initial_value[SHA512_STATESIZE]; - -/** - * @brief Get digest size in bytes for the given \p hash_fct - * @param hash_fct hash function. See ::sx_hash_fct_t. - * @return digest size in bytes, or 0 if invalid \p hash_fct - */ -uint32_t sx_hash_get_digest_size(sx_hash_fct_t hash_fct) CHECK_RESULT; - -/** - * @brief Get block size in bytes for the given \p hash_fct - * @param hash_fct hash function. See ::sx_hash_fct_t. - * @return block size in bytes, or 0 if invalid \p hash_fct - */ -uint32_t sx_hash_get_block_size(sx_hash_fct_t hash_fct) CHECK_RESULT; - -/** - * @brief Get state size in bytes for the given \p hash_fct - * @param hash_fct hash function. See ::sx_hash_fct_t. - * @return state size in bytes, or 0 if invalid \p hash_fct - */ -uint32_t sx_hash_get_state_size(sx_hash_fct_t hash_fct) CHECK_RESULT; - -/** - * @brief Compute hash digest of the content of \p data_in and write the result in \p data_out. - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param data_in array of input data to process - * @param entries length of array \p data_in - * @param data_out output digest - * @return CRYPTOLIB_SUCCESS if execution was successful - */ - uint32_t sx_hash_array_blk( - sx_hash_fct_t hash_fct, - block_t data_in[], - const unsigned int entries, - block_t data_out) CHECK_RESULT; - -/** - * @brief Compute HMAC of the content of \p data_in and write the result in \p data_out. - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param key HMAC key to use - * @param data_in array of input data to process - * @param entries length of array \p data_in - * @param data_out output digest - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t sx_hmac_array_blk( - sx_hash_fct_t hash_fct, - block_t key, - block_t data_in[], - const unsigned int - entries, - block_t data_out) CHECK_RESULT; - -/** - * @brief Compute hash digest of the content of \p data_in and write the result in \p data_out. - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param data_in input data to process - * @param data_out output digest - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t sx_hash_blk( - sx_hash_fct_t hash_fct, - block_t data_in, - block_t data_out) CHECK_RESULT; - -/** - * @brief Compute HMAC of the content of \p data_in and write the result in \p data_out. - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param key HMAC key to use - * @param data_in input data to process - * @param data_out output digest - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t sx_hmac_blk( - sx_hash_fct_t hash_fct, - block_t key, - block_t data_in, - block_t data_out) CHECK_RESULT; - -/** - * @brief Compute hash block operation with \p state and \p data input, and write result back to \p state. - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param state input and output state required in context switching. - * Size must be equal to state size of \p hash_fct, - * if it's the first operation must be filled with initialization values. - * @param data input data to process. Size must be multiple of the block size of \p hash_fct - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t sx_hash_update_blk( - sx_hash_fct_t hash_fct, - block_t state, - block_t data) CHECK_RESULT; - -/** - * @brief Finish a hash operation after zero or more update operations after doing necessary padding - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param state input and output state required in context switching. - * Size must be equal to state size of \p hash_fct, - * if it's the first operation must be filled with initialization values. - * @param data_in input data to process , can be of any length. - * @param data_out output of hashing the padded input - * @param total_len length of all data hashed including the data hashed before using update and length of data_in - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t sx_hash_finish_blk( - sx_hash_fct_t hash_fct, - block_t state, - block_t data_in, - block_t data_out, - uint32_t total_len); - -#endif +/** + * @file + * @brief Declares the constants and functions to make operations + * with the BA413 hash function + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_HASH_H +#define SX_HASH_H + +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" + +/** @brief Size of MD5 data block in bytes */ +#define MD5_BLOCKSIZE 64 +/** @brief Size of MD5 initialization value in bytes */ +#define MD5_INITSIZE 16 +/** @brief Size of MD5 digest in bytes */ +#define MD5_DIGESTSIZE 16 +/** @brief Size of SHA1 data block in bytes */ +#define SHA1_BLOCKSIZE 64 +/** @brief Size of SHA1 state in bytes */ +#define SHA1_STATESIZE 20 +/** @brief Size of SHA1 digest in bytes */ +#define SHA1_DIGESTSIZE 20 +/** @brief Size of SHA224 data block in bytes */ +#define SHA224_BLOCKSIZE 64 +/** @brief Size of SHA224 state in bytes */ +#define SHA224_STATESIZE 32 +/** @brief Size of SHA224 digest in bytes */ +#define SHA224_DIGESTSIZE 28 +/** @brief Size of SHA256 data block in bytes */ +#define SHA256_BLOCKSIZE 64 +/** @brief Size of SHA256 state in bytes */ +#define SHA256_STATESIZE 32 +/** @brief Size of SHA256 digest in bytes */ +#define SHA256_DIGESTSIZE 32 +/** @brief Size of SHA384 data block in bytes */ +#define SHA384_BLOCKSIZE 128 +/** @brief Size of SHA384 state in bytes */ +#define SHA384_STATESIZE 64 +/** @brief Size of SHA384 digest in bytes */ +#define SHA384_DIGESTSIZE 48 +/** @brief Size of SHA512 data block in bytes */ +#define SHA512_BLOCKSIZE 128 +/** @brief Size of SHA512 state in bytes */ +#define SHA512_STATESIZE 64 +/** @brief Size of SHA512 digest in bytes */ +#define SHA512_DIGESTSIZE 64 +/** @brief Size of SM3 digest in bytes */ +#define SM3_BLOCKSIZE 64 +/** @brief Size of SM3 initialization value in bytes */ +#define SM3_INITSIZE 32 +/** @brief Size of SM3 digest in bytes */ +#define SM3_DIGESTSIZE 32 +/** @brief Maximum block size to be supported */ +#define MAX_BLOCKSIZE SHA512_BLOCKSIZE +/** @brief Maximum digest size to be supported */ +#define MAX_DIGESTSIZE SHA512_DIGESTSIZE +/** @brief Maximum number of entries in sx_hash_array_blk and sx_hmac_array_blk */ +#define SX_HASH_ARRAY_MAX_ENTRIES 8 + +/** +* @brief Enumeration of the supported hash algorithms +*/ +typedef enum sx_hash_fct_e +{ + e_MD5 = 1, /**< MD5 */ + e_SHA1 = 2, /**< SHA1 */ + e_SHA224 = 3, /**< SHA224 */ + e_SHA256 = 4, /**< SHA256 */ + e_SHA384 = 5, /**< SHA384 */ + e_SHA512 = 6, /**< SHA512 */ + e_SM3 = 7 /**< SM3 */ +} sx_hash_fct_t; + +/** + * @brief: Initialization vector for SM3 context + * https://tools.ietf.org/id/draft-oscca-cfrg-sm3-01.html#rfc.section.4.1 + */ +extern const uint8_t sx_sm3_iv[SM3_DIGESTSIZE]; + +/** + * @brief: Initial value for SHA-1 + * http://dx.doi.org/10.6028/NIST.FIPS.180-4 + */ +extern const uint8_t sx_sha1_initial_value[SHA1_STATESIZE]; + +/** + * @brief: Initial value for SHA-224 + * http://dx.doi.org/10.6028/NIST.FIPS.180-4 + */ +extern const uint8_t sx_sha224_initial_value[SHA224_STATESIZE]; + +/** + * @brief: Initial value for SHA-256 + * http://dx.doi.org/10.6028/NIST.FIPS.180-4 + */ +extern const uint8_t sx_sha256_initial_value[SHA256_STATESIZE]; + +/** + * @brief: Initial value for SHA-384 + * http://dx.doi.org/10.6028/NIST.FIPS.180-4 + */ +extern const uint8_t sx_sha384_initial_value[SHA384_STATESIZE]; + +/** + * @brief: Initial value for SHA-512 + * http://dx.doi.org/10.6028/NIST.FIPS.180-4 + */ +extern const uint8_t sx_sha512_initial_value[SHA512_STATESIZE]; + +/** + * @brief Get digest size in bytes for the given \p hash_fct + * @param hash_fct hash function. See ::sx_hash_fct_t. + * @return digest size in bytes, or 0 if invalid \p hash_fct + */ +uint32_t sx_hash_get_digest_size(sx_hash_fct_t hash_fct) CHECK_RESULT; + +/** + * @brief Get block size in bytes for the given \p hash_fct + * @param hash_fct hash function. See ::sx_hash_fct_t. + * @return block size in bytes, or 0 if invalid \p hash_fct + */ +uint32_t sx_hash_get_block_size(sx_hash_fct_t hash_fct) CHECK_RESULT; + +/** + * @brief Get state size in bytes for the given \p hash_fct + * @param hash_fct hash function. See ::sx_hash_fct_t. + * @return state size in bytes, or 0 if invalid \p hash_fct + */ +uint32_t sx_hash_get_state_size(sx_hash_fct_t hash_fct) CHECK_RESULT; + +/** + * @brief Compute hash digest of the content of \p data_in and write the result in \p data_out. + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param data_in array of input data to process + * @param entries length of array \p data_in + * @param data_out output digest + * @return CRYPTOLIB_SUCCESS if execution was successful + */ + uint32_t sx_hash_array_blk( + sx_hash_fct_t hash_fct, + block_t data_in[], + const unsigned int entries, + block_t data_out) CHECK_RESULT; + +/** + * @brief Compute HMAC of the content of \p data_in and write the result in \p data_out. + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param key HMAC key to use + * @param data_in array of input data to process + * @param entries length of array \p data_in + * @param data_out output digest + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t sx_hmac_array_blk( + sx_hash_fct_t hash_fct, + block_t key, + block_t data_in[], + const unsigned int + entries, + block_t data_out) CHECK_RESULT; + +/** + * @brief Compute hash digest of the content of \p data_in and write the result in \p data_out. + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param data_in input data to process + * @param data_out output digest + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t sx_hash_blk( + sx_hash_fct_t hash_fct, + block_t data_in, + block_t data_out) CHECK_RESULT; + +/** + * @brief Compute HMAC of the content of \p data_in and write the result in \p data_out. + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param key HMAC key to use + * @param data_in input data to process + * @param data_out output digest + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t sx_hmac_blk( + sx_hash_fct_t hash_fct, + block_t key, + block_t data_in, + block_t data_out) CHECK_RESULT; + +/** + * @brief Compute hash block operation with \p state and \p data input, and write result back to \p state. + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param state input and output state required in context switching. + * Size must be equal to state size of \p hash_fct, + * if it's the first operation must be filled with initialization values. + * @param data input data to process. Size must be multiple of the block size of \p hash_fct + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t sx_hash_update_blk( + sx_hash_fct_t hash_fct, + block_t state, + block_t data) CHECK_RESULT; + +/** + * @brief Finish a hash operation after zero or more update operations after doing necessary padding + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param state input and output state required in context switching. + * Size must be equal to state size of \p hash_fct, + * if it's the first operation must be filled with initialization values. + * @param data_in input data to process , can be of any length. + * @param data_out output of hashing the padded input + * @param total_len length of all data hashed including the data hashed before using update and length of data_in + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t sx_hash_finish_blk( + sx_hash_fct_t hash_fct, + block_t state, + block_t data_in, + block_t data_out, + uint32_t total_len); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hw_cfg.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hw_cfg.h index bf313da..403595f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hw_cfg.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_hw_cfg.h @@ -1,41 +1,41 @@ -/** - * @file - * @brief Defines macros to be used to retrieve the hardware configuration - * of CryptoMaster, i.e. what IPs are included. - * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved - */ - -#ifndef SX_HW_CFG_H -#define SX_HW_CFG_H -#include "cryptolib_def.h" - -#define CRYPTOSOC_INCL_IPS_HW_CFG (*((const volatile uint32_t*) ADDR_INCL_IPS_HW_CFG)) - -#define CRYPTOSOC_HW_CFG_AES_IP_INCLUDED_LSB 0 -#define CRYPTOSOC_HW_CFG_AES_IP_INCLUDED_MASK (1L< -#include -#include -#include "cryptolib_types.h" - -/** - * @brief Transform a 64-bit unsigned integer into a byte arrays. - * @param in input value - * @param out result destination. 8 bytes will be written. - * @param endian endianness of data (see ::sx_endianness) - */ -void sx_math_u64_to_u8array(uint64_t in, uint8_t *out, enum sx_endianness endian); - -/** - * @brief Verify if a byte array is different than 0. - * @param in input value - * @param length length of the array - * @return 1 if the array is not all zeroes, 0 otherwise - */ -uint32_t sx_math_array_is_not_null(uint8_t *in, uint32_t length); - - -/** - * @brief Get bit size of a value in an array of bytes - * @param a array of bytes - * @param length length of the \p a - * @return number of bits in \p a - */ -uint32_t sx_math_array_nbits(uint8_t *a, const size_t length); - -/** - * @brief a = a + value (value can be positive or negative). - * Increment (time constant) of an unsigned value stored as byte array a. - * @param a unsigned integer to increment, stored as a big endian byte array - * @param length size of \p a - * @param value the value to add to \p a - */ -int32_t sx_math_array_incr(uint8_t *a, const size_t length, int8_t value); - -/** - * @brief A = A + B. Add two unsigned values stored as byte arrays. - * @param a unsigned integer to add, as a big endian byte array. Result will be placed here. - * @param alen size of \p a. - * @param b unsigned integer to add, as a big endian byte array. - * @param blen size of \p b. Must be smaller or equal to \p alen. - */ -void sx_math_array_add(uint8_t *a, const size_t alen, - const uint8_t *b, const size_t blen); - - -/** - * @brief Determine if a \c lhs (representing a big number) is less than \c rhs - * @param lhs Big number to compare - * @param rhs Big number against to compare - * @param len length size of both \c lhs and \c rhs - * @param endian endianness of data (see ::sx_endianness) - * @return true if \c lhs is inferior to \c rhs, otherwise false - * - * @warning This function is NOT constant time ! - */ -bool sx_math_less_than( - const uint8_t *lhs, - const uint8_t *rhs, - const size_t len); - -/** - * @brief Compute the absolute difference of two big numbers: result = abs(a - b) - * @param a unsigned integer as a big endian byte array - * @param b unsigned integer as a big endian byte array - * @param result unsigned integer as a big endian byte array - * @param size size of \p a, \p b and \p result. - */ -void sx_math_abs_diff( - const uint8_t *a, - const uint8_t *b, - uint8_t *result, - size_t size); - -#endif +/** + * @file + * @brief Mathematic functions + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_MATH_H +#define SX_MATH_H + +#include +#include +#include +#include "cryptolib_types.h" + +/** + * @brief Transform a 64-bit unsigned integer into a byte arrays. + * @param in input value + * @param out result destination. 8 bytes will be written. + * @param endian endianness of data (see ::sx_endianness) + */ +void sx_math_u64_to_u8array(uint64_t in, uint8_t *out, enum sx_endianness endian); + +/** + * @brief Verify if a byte array is different than 0. + * @param in input value + * @param length length of the array + * @return 1 if the array is not all zeroes, 0 otherwise + */ +uint32_t sx_math_array_is_not_null(uint8_t *in, uint32_t length); + + +/** + * @brief Get bit size of a value in an array of bytes + * @param a array of bytes + * @param length length of the \p a + * @return number of bits in \p a + */ +uint32_t sx_math_array_nbits(uint8_t *a, const size_t length); + +/** + * @brief a = a + value (value can be positive or negative). + * Increment (time constant) of an unsigned value stored as byte array a. + * @param a unsigned integer to increment, stored as a big endian byte array + * @param length size of \p a + * @param value the value to add to \p a + */ +int32_t sx_math_array_incr(uint8_t *a, const size_t length, int8_t value); + +/** + * @brief A = A + B. Add two unsigned values stored as byte arrays. + * @param a unsigned integer to add, as a big endian byte array. Result will be placed here. + * @param alen size of \p a. + * @param b unsigned integer to add, as a big endian byte array. + * @param blen size of \p b. Must be smaller or equal to \p alen. + */ +void sx_math_array_add(uint8_t *a, const size_t alen, + const uint8_t *b, const size_t blen); + + +/** + * @brief Determine if a \c lhs (representing a big number) is less than \c rhs + * @param lhs Big number to compare + * @param rhs Big number against to compare + * @param len length size of both \c lhs and \c rhs + * @param endian endianness of data (see ::sx_endianness) + * @return true if \c lhs is inferior to \c rhs, otherwise false + * + * @warning This function is NOT constant time ! + */ +bool sx_math_less_than( + const uint8_t *lhs, + const uint8_t *rhs, + const size_t len); + +/** + * @brief Compute the absolute difference of two big numbers: result = abs(a - b) + * @param a unsigned integer as a big endian byte array + * @param b unsigned integer as a big endian byte array + * @param result unsigned integer as a big endian byte array + * @param size size of \p a, \p b and \p result. + */ +void sx_math_abs_diff( + const uint8_t *a, + const uint8_t *b, + uint8_t *result, + size_t size); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcmp.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcmp.h index f38e741..f6a044f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcmp.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcmp.h @@ -1,32 +1,32 @@ -/** - * @file - * @brief Provides a family of memcmp functions showing constant-time operation - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef MEMCMP_H -#define MEMCMP_H - -#include -#include "cryptolib_types.h" - -/** - * Compares two buffer in time constant - * @param in1 pointer to the first buffer - * @param in2 pointer to the second buffer - * @param size Size to compare - * @return 0 if the two buffers are the same 1 otherwise - */ -uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size); - -/** - * Compares two block_t in time constant on 32-bit words. Supports - * constant addresses (FIFO) - * @param in1 block_t of first buffer - * @param in2 block_t of second buffer - * @param size Size to compare in bytes - * @return 0 if the two buffers are the same 1 otherwise - */ -uint32_t memcmp32_blk_time_cst(block_t in1, block_t in2, uint32_t size); -#endif +/** + * @file + * @brief Provides a family of memcmp functions showing constant-time operation + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef MEMCMP_H +#define MEMCMP_H + +#include +#include "cryptolib_types.h" + +/** + * Compares two buffer in time constant + * @param in1 pointer to the first buffer + * @param in2 pointer to the second buffer + * @param size Size to compare + * @return 0 if the two buffers are the same 1 otherwise + */ +uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size); + +/** + * Compares two block_t in time constant on 32-bit words. Supports + * constant addresses (FIFO) + * @param in1 block_t of first buffer + * @param in2 block_t of second buffer + * @param size Size to compare in bytes + * @return 0 if the two buffers are the same 1 otherwise + */ +uint32_t memcmp32_blk_time_cst(block_t in1, block_t in2, uint32_t size); +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcpy.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcpy.h index 328078b..71a42a3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcpy.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_memcpy.h @@ -1,70 +1,70 @@ -/** - * @file - * @brief Provides a family of memcpy functions accelerated by the cryptoDMA - * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved - */ - -#ifndef CRYPTODMA_H -#define CRYPTODMA_H - -#include -#include "cryptolib_types.h" - -/** - * Copy length bytes from the src block_t to the dest block_t - * - * This function speeds up the data transfer by using the internal DMA - * @param src block_t to the source data to transfer - * @param dest block_t to the destination location - * @param length the length in bytes to transfer (from src to dest) - */ -void memcpy_blk(block_t dest, block_t src, uint32_t length); - -/** - * Copy length bytes from src to the block_t defined by dest - * - * This function speeds up the data transfer by using the internal DMA - * @param dest block_t to the destination location - * @param src input buffer - * @param length length of the data to copy - */ -void memcpy_blkOut(block_t dest, const volatile void * src, uint32_t length); - -/** - * Copy length bytes from the src block_t to the dest buffer - * - * This function speeds up the data transfer by using the internal DMA - * @param dest output buffer - * @param src input block_t - * @param length length of the data to copy - */ -void memcpy_blkIn(volatile void * dest, block_t src, uint32_t length); - -/** - * Copy length bytes from the src array to the dest array - * - * This function speeds up the data transfer by using the internal DMA - * @param dest output array - * @param src input array - * @param length length of the data to copy - */ -void memcpy_array(volatile void * dest, const volatile void * src, uint32_t length); - -/** - * Copy length bytes from the src buffer to the dest buffer - * - * @param src pointer to the source data to transfer - * @param dest pointer to the destination location - * @param length the number bytes to transfer (from src to dest) - */ -void sx_memcpy(void* dest, void* src, size_t length); - -/** - * Set length bytes in the src with pattern - * - * @param src pointer to the source data to transfer - * @param pattern pattern used to set the memory - * @param length the number bytes to set with pattern - */ -void sx_memset(void* src, int8_t pattern, size_t length); -#endif +/** + * @file + * @brief Provides a family of memcpy functions accelerated by the cryptoDMA + * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved + */ + +#ifndef CRYPTODMA_H +#define CRYPTODMA_H + +#include +#include "cryptolib_types.h" + +/** + * Copy length bytes from the src block_t to the dest block_t + * + * This function speeds up the data transfer by using the internal DMA + * @param src block_t to the source data to transfer + * @param dest block_t to the destination location + * @param length the length in bytes to transfer (from src to dest) + */ +void memcpy_blk(block_t dest, block_t src, uint32_t length); + +/** + * Copy length bytes from src to the block_t defined by dest + * + * This function speeds up the data transfer by using the internal DMA + * @param dest block_t to the destination location + * @param src input buffer + * @param length length of the data to copy + */ +void memcpy_blkOut(block_t dest, const volatile void * src, uint32_t length); + +/** + * Copy length bytes from the src block_t to the dest buffer + * + * This function speeds up the data transfer by using the internal DMA + * @param dest output buffer + * @param src input block_t + * @param length length of the data to copy + */ +void memcpy_blkIn(volatile void * dest, block_t src, uint32_t length); + +/** + * Copy length bytes from the src array to the dest array + * + * This function speeds up the data transfer by using the internal DMA + * @param dest output array + * @param src input array + * @param length length of the data to copy + */ +void memcpy_array(volatile void * dest, const volatile void * src, uint32_t length); + +/** + * Copy length bytes from the src buffer to the dest buffer + * + * @param src pointer to the source data to transfer + * @param dest pointer to the destination location + * @param length the number bytes to transfer (from src to dest) + */ +void sx_memcpy(void* dest, void* src, size_t length); + +/** + * Set length bytes in the src with pattern + * + * @param src pointer to the source data to transfer + * @param pattern pattern used to set the memory + * @param length the number bytes to set with pattern + */ +void sx_memset(void* src, int8_t pattern, size_t length); +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_primitives.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_primitives.h index 08cf1ce..899e5d2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_primitives.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_primitives.h @@ -1,288 +1,288 @@ -/** - * @file - * @brief Defines the procedures to make primitive operations with the BA414EP - * Public Key Engine - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef PRIMITIVES_H -#define PRIMITIVES_H - -#include -#include "compiler_extentions.h" -#include "cryptolib_types.h" - - -/** @brief Modular Addition: C = (A + B) mod P - * @param a is a pointer to the first operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to - * a location in the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_addition( - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Subtraction: C = (A - B) mod P - * @param a is a pointer to the first operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_substraction( - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Multiplication: C = (A * B) mod P - * @param a is a pointer to the first operand (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_multiplication( - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Reduction: C = A mod P - * @param a is a pointer to the first operand (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to a location in - * the System Memory, not in the CryptoRAM), must be odd. - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_reduction( - const uint8_t *a, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Division: C = (A/B) mod P - * @param a is a pointer to the first operand (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_division( - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Inversion: C = (1/A) mod P - * @param a is a pointer to the first operand (this must point to a location - * in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t modular_inversion( - const uint8_t *a, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Multiplication: C = A * B - * @param a is a pointer to the first operand (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand of the Multiplication (this must - * point to a location in the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ -uint32_t multiplication( - const uint8_t *a, - const uint8_t *b, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Exponentiation: result = (A ^ B) mod P - * @param a is a pointer to the first operand (this must point to a location in - * the System Memory, not in the CryptoRAM). - * @param b is a pointer to the key of the modular exponentiation (this must - * point to a location in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo of the modular exponentiation (this - * must point to a location in the System Memory, not in the - * CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the size of the operands in bytes. - * @return CRYPTOLIB_SUCCESS when no error occurs. - */ - uint32_t modular_exponentiation( - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) CHECK_RESULT; - -/** @brief Modular Exponentiation: C = (A ^ B) mod P using block_t operands -* @param a is a pointer to the first operand (this must point to a location in -* the System Memory, not in the CryptoRAM). -* @param b is a pointer to the second operand (this must point to a location in -* the System Memory, not in the CryptoRAM). -* @param modulo is a pointer to the modulo (this must point to a location in -* the System Memory, not in the CryptoRAM). -* @param result is a pointer where the result has to be copied (this must point -* to a location in the System Memory, not in the CryptoRAM). -* @param size represents the size of the operands in bytes. -* @return CRYPTOLIB_SUCCESS when no error occurs. -*/ -uint32_t modular_exponentiation_blk(block_t a, block_t b, block_t modulo, - block_t result, uint32_t size) CHECK_RESULT; - -/** @brief Montgomery point multiplication - * @param curve domain of the curve to use - * @param curve_flags flags of the curve to use - * @param size curve size in bytes - * @param scalar input - * @param point input. - * If set to ::NULL_blk, generator provided in \p curve will be used - * @param result output - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_montgomery_mult(block_t curve, uint32_t curve_flags, uint32_t size, - block_t scalar, block_t point, block_t result) CHECK_RESULT; - -/** @brief ECC point inversion - * @param curve domain of the curve to use [input] - * @param point point to be inverted [input] - * @param result the inverted point [output] - * @param size curve size in bytes [input] - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_point_inverse(block_t curve, block_t point, block_t result, - uint32_t size) CHECK_RESULT; - -/** @brief ECC point decompression - * @param curve domain of the curve to use [input] - * @param point_x X coordinate of the compressed point [input] - * @param y_bit least significant bit of Y coordinate of the point [input] - * @param point_y Y coordinate after decompression [output] - * @param size curve size in bytes [input] - * @param curve_flags flags of the curve to use [input] - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_point_decompress(block_t curve, block_t point_x, uint8_t y_bit, - block_t point_y, uint32_t size, uint32_t curve_flags) CHECK_RESULT; - -/** @brief solving Y^2 in accordance to the equation y^2 = x^3 + ax + b mod p - * @param curve domain of the curve to use [input] - * @param point_x X coordinate of the compressed point [input] - * @param point_y2 Y^2 the output of the equation as described (y^2 = x^3 + ax + b mod p) [output] - * @param size curve size in bytes [input] - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_point_compute_y2(block_t curve, block_t point_x, block_t point_y2, - uint32_t size) CHECK_RESULT; - -/** @brief ECC point multiplication (result = scalar * point) - * @param curve domain of the curve to use [input] - * @param scalar integer value to be multiplied by the point [input] - * @param point point on the curve to be multiplied with [input] - * @param result output of the multiplication operation [output] - * @param size curve size in bytes [input] - * @param curve_flags flags of the curve to use [input] - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_point_mul(block_t curve, block_t scalar, block_t point, - block_t result, uint32_t size, uint32_t curve_flags) CHECK_RESULT; - -/** @brief ECC point addition (result = point_a + point_b) - * @param curve domain of the curve to use [input] - * @param point_a the first point summand of the equation [input] - * @param point_b the second point summand of the equation [input] - * @param result output of the point addition operation [output] - * @param size curve size in bytes [input] - * @param curve_flags flags of the curve to use [input] - * @return CRYPTOLIB_SUCCESS if successful, error code otherwise - */ -uint32_t ecc_point_add(block_t curve, block_t point_a, block_t point_b, - block_t result, uint32_t size, uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Validates if an ECC point is on the curve - * @param curve Curve parameters [input] - * @param point ECC point to check if it lies on the curve [input] - * @param size curve size in bytes [input] - * @param curve_flags flags of the curve to use [input] - * @return CRYPTOLIB_SUCCESS if point lies on the curve - * @return CRYPTOLIB_CRYPTO_ERR if thr point does not lie on the curve - */ -uint32_t ecc_is_point_on_curve(block_t curve, block_t point, uint32_t size, - uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Multiply and add ECC Weierstrass points - * \p result = \p scalar_m * \p point1 + \p scalar_n * \p point2 - * - * @param curve ECC curve on which to compute point addition - * @param scalar_m will mutliply the first point - * @param point1 the first point to multiply and add - * @param scalar_n will mutliply the second point - * @param point2 the second point to multiply and add - * @param result the result of the mutliply/add operation - * @param size size of one element (expressed in bytes) - * @param curve_flags curve acceleration parameters - * @return CRYPTOLIB_SUCCESS if no error - */ -uint32_t ecc_pt_muladd( - block_t curve, - block_t scalar_m, - block_t point1, - block_t scalar_n, - block_t point2, - block_t result, - uint32_t size, - uint32_t curve_flags); - - -#endif +/** + * @file + * @brief Defines the procedures to make primitive operations with the BA414EP + * Public Key Engine + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef PRIMITIVES_H +#define PRIMITIVES_H + +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" + + +/** @brief Modular Addition: C = (A + B) mod P + * @param a is a pointer to the first operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to + * a location in the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_addition( + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Subtraction: C = (A - B) mod P + * @param a is a pointer to the first operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_substraction( + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Multiplication: C = (A * B) mod P + * @param a is a pointer to the first operand (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_multiplication( + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Reduction: C = A mod P + * @param a is a pointer to the first operand (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to a location in + * the System Memory, not in the CryptoRAM), must be odd. + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_reduction( + const uint8_t *a, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Division: C = (A/B) mod P + * @param a is a pointer to the first operand (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_division( + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Inversion: C = (1/A) mod P + * @param a is a pointer to the first operand (this must point to a location + * in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t modular_inversion( + const uint8_t *a, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Multiplication: C = A * B + * @param a is a pointer to the first operand (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand of the Multiplication (this must + * point to a location in the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ +uint32_t multiplication( + const uint8_t *a, + const uint8_t *b, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Exponentiation: result = (A ^ B) mod P + * @param a is a pointer to the first operand (this must point to a location in + * the System Memory, not in the CryptoRAM). + * @param b is a pointer to the key of the modular exponentiation (this must + * point to a location in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo of the modular exponentiation (this + * must point to a location in the System Memory, not in the + * CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the size of the operands in bytes. + * @return CRYPTOLIB_SUCCESS when no error occurs. + */ + uint32_t modular_exponentiation( + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) CHECK_RESULT; + +/** @brief Modular Exponentiation: C = (A ^ B) mod P using block_t operands +* @param a is a pointer to the first operand (this must point to a location in +* the System Memory, not in the CryptoRAM). +* @param b is a pointer to the second operand (this must point to a location in +* the System Memory, not in the CryptoRAM). +* @param modulo is a pointer to the modulo (this must point to a location in +* the System Memory, not in the CryptoRAM). +* @param result is a pointer where the result has to be copied (this must point +* to a location in the System Memory, not in the CryptoRAM). +* @param size represents the size of the operands in bytes. +* @return CRYPTOLIB_SUCCESS when no error occurs. +*/ +uint32_t modular_exponentiation_blk(block_t a, block_t b, block_t modulo, + block_t result, uint32_t size) CHECK_RESULT; + +/** @brief Montgomery point multiplication + * @param curve domain of the curve to use + * @param curve_flags flags of the curve to use + * @param size curve size in bytes + * @param scalar input + * @param point input. + * If set to ::NULL_blk, generator provided in \p curve will be used + * @param result output + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_montgomery_mult(block_t curve, uint32_t curve_flags, uint32_t size, + block_t scalar, block_t point, block_t result) CHECK_RESULT; + +/** @brief ECC point inversion + * @param curve domain of the curve to use [input] + * @param point point to be inverted [input] + * @param result the inverted point [output] + * @param size curve size in bytes [input] + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_point_inverse(block_t curve, block_t point, block_t result, + uint32_t size) CHECK_RESULT; + +/** @brief ECC point decompression + * @param curve domain of the curve to use [input] + * @param point_x X coordinate of the compressed point [input] + * @param y_bit least significant bit of Y coordinate of the point [input] + * @param point_y Y coordinate after decompression [output] + * @param size curve size in bytes [input] + * @param curve_flags flags of the curve to use [input] + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_point_decompress(block_t curve, block_t point_x, uint8_t y_bit, + block_t point_y, uint32_t size, uint32_t curve_flags) CHECK_RESULT; + +/** @brief solving Y^2 in accordance to the equation y^2 = x^3 + ax + b mod p + * @param curve domain of the curve to use [input] + * @param point_x X coordinate of the compressed point [input] + * @param point_y2 Y^2 the output of the equation as described (y^2 = x^3 + ax + b mod p) [output] + * @param size curve size in bytes [input] + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_point_compute_y2(block_t curve, block_t point_x, block_t point_y2, + uint32_t size) CHECK_RESULT; + +/** @brief ECC point multiplication (result = scalar * point) + * @param curve domain of the curve to use [input] + * @param scalar integer value to be multiplied by the point [input] + * @param point point on the curve to be multiplied with [input] + * @param result output of the multiplication operation [output] + * @param size curve size in bytes [input] + * @param curve_flags flags of the curve to use [input] + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_point_mul(block_t curve, block_t scalar, block_t point, + block_t result, uint32_t size, uint32_t curve_flags) CHECK_RESULT; + +/** @brief ECC point addition (result = point_a + point_b) + * @param curve domain of the curve to use [input] + * @param point_a the first point summand of the equation [input] + * @param point_b the second point summand of the equation [input] + * @param result output of the point addition operation [output] + * @param size curve size in bytes [input] + * @param curve_flags flags of the curve to use [input] + * @return CRYPTOLIB_SUCCESS if successful, error code otherwise + */ +uint32_t ecc_point_add(block_t curve, block_t point_a, block_t point_b, + block_t result, uint32_t size, uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Validates if an ECC point is on the curve + * @param curve Curve parameters [input] + * @param point ECC point to check if it lies on the curve [input] + * @param size curve size in bytes [input] + * @param curve_flags flags of the curve to use [input] + * @return CRYPTOLIB_SUCCESS if point lies on the curve + * @return CRYPTOLIB_CRYPTO_ERR if thr point does not lie on the curve + */ +uint32_t ecc_is_point_on_curve(block_t curve, block_t point, uint32_t size, + uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Multiply and add ECC Weierstrass points + * \p result = \p scalar_m * \p point1 + \p scalar_n * \p point2 + * + * @param curve ECC curve on which to compute point addition + * @param scalar_m will mutliply the first point + * @param point1 the first point to multiply and add + * @param scalar_n will mutliply the second point + * @param point2 the second point to multiply and add + * @param result the result of the mutliply/add operation + * @param size size of one element (expressed in bytes) + * @param curve_flags curve acceleration parameters + * @return CRYPTOLIB_SUCCESS if no error + */ +uint32_t ecc_pt_muladd( + block_t curve, + block_t scalar_m, + block_t point1, + block_t scalar_n, + block_t point2, + block_t result, + uint32_t size, + uint32_t curve_flags); + + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_rng.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_rng.h index d27f2e6..9617e42 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_rng.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_rng.h @@ -1,87 +1,87 @@ -/** - * @brief Random Number Generator Abstraction for CryptoSoC - * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved - * @file - * - * By using the sx_rng structure defined in this file different RNG - * implementations can be provided as parameter to functions which require - * generation of random vales. - * - * Examples: - * a. Using a Hash DRBG - * @code - * #include "sx_drbg_hash.h" - * - * struct sx_drbg_hash_ctx_s drbg_context; - * - * void drbg_get_rand_blk(void *param, block_t result) - * { - * struct sx_drbg_hash_ctx_s* drbg_context = (struct sx_drbg_hash_ctx_s*) - * param; - * - * uint32_t r = sx_drbg_hash_generate(drbg_context, result); - * - * if (r == CRYPTOLIB_DRBG_RESEED_NEEDED) { - * sx_drbg_hash_reseed(drbg_context, ...) - * } - * - * r = sx_drbg_hash_generate(drbg_context, result); - * CRYPTOLIB_ASSERT(r == CRYPTOLIB_SUCCESS, "DRBG failed") * - * } - * - * struct sx_rng drbg_rng = { - * .param = (void*)(&drbg_context), - * .get_rand_blk = drbg_get_rand_blk - * }; - * - * ... - * - * sx_rng_get_rand_lt_n_blk(dst, n, drbg_rng); - * @endcode - * - * b. Using the TRNG - * - * @code - * #include "sx_trng.h" - * - * struct sx_rng trng = { - * .param = NULL, - * .get_rand_blk = sx_trng_fill_blk - * }; - * - * ... - * - * sx_rng_get_rand_lt_n_blk(dst, n, trng); - * @endcode - */ -#ifndef SX_RNG_H -#define SX_RNG_H - -#include "cryptolib_types.h" -#include "compiler_extentions.h" - -/** - * @brief Structure used for passing a random number generator as a parameter to - * functions which require one. - */ -struct sx_rng { - void *param; /**< Pointer to the RNG state or any other element needed - * by the get_rand_blk() function. - */ - void (*get_rand_blk) (void *param, block_t result); /**< Pointer to the - * function that will be called when a random data block is required. - */ -}; - - -/** -* @brief Generate a random number k with 1 <= k < n. -* Implementation compliant with the FIPS 186-4 guideline. -* @param dst Pointer to store generated random number k (should be buffer) -* @param n Pointer to upper limit n (should be buffer) -* @param rng Used random number generator -* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_INVALID_PARAM -*/ -uint32_t sx_rng_get_rand_lt_n_blk(block_t dst, block_t n, struct sx_rng rng) -CHECK_RESULT; -#endif +/** + * @brief Random Number Generator Abstraction for CryptoSoC + * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved + * @file + * + * By using the sx_rng structure defined in this file different RNG + * implementations can be provided as parameter to functions which require + * generation of random vales. + * + * Examples: + * a. Using a Hash DRBG + * @code + * #include "sx_drbg_hash.h" + * + * struct sx_drbg_hash_ctx_s drbg_context; + * + * void drbg_get_rand_blk(void *param, block_t result) + * { + * struct sx_drbg_hash_ctx_s* drbg_context = (struct sx_drbg_hash_ctx_s*) + * param; + * + * uint32_t r = sx_drbg_hash_generate(drbg_context, result); + * + * if (r == CRYPTOLIB_DRBG_RESEED_NEEDED) { + * sx_drbg_hash_reseed(drbg_context, ...) + * } + * + * r = sx_drbg_hash_generate(drbg_context, result); + * CRYPTOLIB_ASSERT(r == CRYPTOLIB_SUCCESS, "DRBG failed") * + * } + * + * struct sx_rng drbg_rng = { + * .param = (void*)(&drbg_context), + * .get_rand_blk = drbg_get_rand_blk + * }; + * + * ... + * + * sx_rng_get_rand_lt_n_blk(dst, n, drbg_rng); + * @endcode + * + * b. Using the TRNG + * + * @code + * #include "sx_trng.h" + * + * struct sx_rng trng = { + * .param = NULL, + * .get_rand_blk = sx_trng_fill_blk + * }; + * + * ... + * + * sx_rng_get_rand_lt_n_blk(dst, n, trng); + * @endcode + */ +#ifndef SX_RNG_H +#define SX_RNG_H + +#include "cryptolib_types.h" +#include "compiler_extentions.h" + +/** + * @brief Structure used for passing a random number generator as a parameter to + * functions which require one. + */ +struct sx_rng { + void *param; /**< Pointer to the RNG state or any other element needed + * by the get_rand_blk() function. + */ + void (*get_rand_blk) (void *param, block_t result); /**< Pointer to the + * function that will be called when a random data block is required. + */ +}; + + +/** +* @brief Generate a random number k with 1 <= k < n. +* Implementation compliant with the FIPS 186-4 guideline. +* @param dst Pointer to store generated random number k (should be buffer) +* @param n Pointer to upper limit n (should be buffer) +* @param rng Used random number generator +* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_INVALID_PARAM +*/ +uint32_t sx_rng_get_rand_lt_n_blk(block_t dst, block_t n, struct sx_rng rng) +CHECK_RESULT; +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_trng.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_trng.h index 1c89a8d..b443b51 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_trng.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/include/sx_trng.h @@ -1,193 +1,193 @@ -/** - * @file - * @brief Defines the procedures to make operations with - * the BA431 (N)DRNG - * (see BA431_NDRNG_DataSheet.pdf) - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_TRNG_H -#define SX_TRNG_H - -#include -#include -#include "compiler_extentions.h" -#include "cryptolib_types.h" - -typedef enum sx_trng_test { - TRNG_REP_TEST, /**< Repetition count test. */ - TRNG_PROP_TEST, /**< Adaptive proportion test. */ - TRNG_PREALM_TEST, /**< AIS31 preliminary noise alarm */ - TRNG_ALM_TEST, /**< AIS31 noise alarm. */ -} sx_trng_test_t; - -/** @brief structure used in save/restore TRNG state. Should be considered opaque */ -struct sx_trng_internal_state -{ - uint32_t control; - uint32_t key[4]; - uint32_t wakeup_lvl; - uint32_t swoff_timer; - uint32_t clk_divider; - uint32_t init_wait_cnt; -}; - -/** -* @brief TRNG initialization -* @param cond_test_en When not zero, conditioning test is executed first -* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR -*/ -uint32_t sx_trng_init(uint32_t cond_test_en) CHECK_RESULT; - -/** -* @brief First part of TRNG initialization -* For boot time optimization, the TRNG init can be split into 2 parts. The first -* part executes the conditioning test, makes some configurations and switches on -* the oscillator rings. After that it returns, allowing to call other functions -* while the TRNG FIFO is filling up in the background. -* @param cond_test_en When not zero, conditioning test is executed -* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR -*/ -uint32_t sx_trng_init_part1(uint32_t cond_test_en) CHECK_RESULT; - -/** -* @brief Second part of TRNG initialization -* For boot time optimization, the TRNG init can be split into 2 parts. The -* second part checks that startup tests were successful, once the TRNG FIFO is -* fully filled. Then it programs a random key for the conditioning function, -* resets the TRNG and returns. Note that the FIFO should be fully filled again -* and startup tests successful before reading the first piece of random data. -* This can be assured by using ::sx_trng_set_startup_chk_flag after TRNG init. -* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR -*/ -uint32_t sx_trng_init_part2(void) CHECK_RESULT; - -/** -* @brief Indicate whether conditioning or startup test failed during init. -* Only valid during bootloader and diagnostic mode! -* If false is returned, true randomness can't be warranted and user must react -* (i.e. raising tamper) -* @return boolean -*/ -bool sx_trng_startup_failed(void); - -/** -* @brief Sets a flag that tells the TRNG software module to wait for TRNG -* startup tests to be finished successfully before reading random data from the -* TRNG FIFO.This needs to be done after explicitly calling the ba431_softreset() -* in interrupt context and after TRNG initialization. -* -* The TRNG startup test will wait until the TRNG FIFO is filled with data and -* then check that the data is sufficiently random. If it is, the startup test is -* passed. The BA431 datasheet specifies that we shouldn't use data from the TRNG -* FIFO before it has been confirmed to be sufficiently random. -*/ -void sx_trng_set_startup_chk_flag(void); - -/** - * @brief Returns a 32-bit word containing the TRNG status register where all - * the bits have been zeroed out except the ones representing the repetition - * count test interrupt status, the adaptive proportion test interrupt status - * and (if enabled) the AIS31 noise alarm status. - * - * Bit 4 is the repetition count test interrupt status, bit 5 is the adaptive - * proportion test interrupt status and bit 9 is the AIS31 noise alarm status. - * If any of these bits is set, the corresponding test has failed. - */ -uint32_t sx_trng_critical_raised(void); - -/** -* @brief Applies a soft reset on the random generator and sets a flag that tells -* the TRNG software module to wait for TRNG startup tests to be finished -* successfully before reading random data from the TRNG FIFO. -* -* The TRNG startup test will wait until the TRNG FIFO is filled with data and -* then check that the data is sufficiently random. If it is, the startup test is -* passed. The BA431 datasheet specifies that we shouldn't use data from the TRNG -* FIFO before it has been confirmed to be sufficiently random. -*/ - -void sx_trng_apply_soft_reset(void); - -/** -* @brief Generate random data (block_t) -* @param dest Output location for the generated random data. -*/ -void sx_trng_get_rand_blk(block_t dest); - -/** -* @brief Get an array of random values -* @param dst Pointer to the array where the random values are stored -* @param size Number of random bytes to be generate -*/ -void sx_trng_get_rand(uint8_t *dst, uint32_t size); - -/** -* @brief Returns a random 32-bit word -* @return 32-bit random value -*/ -uint32_t sx_trng_get_word(void); - -/** -* @brief Generate a random block of data by the TRNG. Defined to match the -* prototype of the struct sx_rng get_rand_blk() -* @param param Should be set to NULL -* @param result block_t for the generated values -*/ -void sx_trng_fill_blk(void *param, block_t result); - -#ifdef UNITTESTS -uint32_t sx_trng_conditioning_test(void); -uint32_t sx_trng_wait_startup(void); -#endif - -/** - * @brief Return if the TRNG module is facing an error state - * - * This error could be due to start-up tests (NIST-800-90B Start-up Test or - * AIS31 Start-up Test) or due to online test (Adaptive Proportion Test or - * AIS31 Online Test) - */ - -bool sx_trng_is_error_detected(void); - -/** -* @brief Cause a TRNG to fail (on health tests) -* For test failure confirmation the TRNG interrupt needs to be checked. -* -* \note This test will wait until a ::BA431_STAT_MASK_PROP_FAIL even if other -* kind of BA431 failure is generated before. -*/ -void sx_trng_trigger_failure(void); - -/** -* @brief Cause a TRNG self test to fail for a specified test -* For test failure confirmation the TRNG status and/or interrupt needs to be -* checked. -* @param test Chosen TRNG self test -* @return CRYPTOLIB_SUCCESS if the TRNG was successfully configured for causing -* the test failure -*/ -uint32_t sx_trng_trigger_test_failure(sx_trng_test_t test); - -/** - * @brief Save a local copy of the TRNG internal configuration state - * @param copy is structure which will contain the internal state required to - * reconfigure the BA431 with specifics parameters - */ -void sx_trng_save_state(struct sx_trng_internal_state *copy); - -/** - * @brief Restore to the TRNG the internal configuration state - * @param source is a structure containing the config to restore to the TRNG - */ -void sx_trng_restore_state(struct sx_trng_internal_state *source); - -/** -* @brief TRNG initialization in order to provide RAW data -* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR -*/ -uint32_t sx_trng_raw_init(void); - -#endif /* SX_TRNG_H */ +/** + * @file + * @brief Defines the procedures to make operations with + * the BA431 (N)DRNG + * (see BA431_NDRNG_DataSheet.pdf) + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_TRNG_H +#define SX_TRNG_H + +#include +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" + +typedef enum sx_trng_test { + TRNG_REP_TEST, /**< Repetition count test. */ + TRNG_PROP_TEST, /**< Adaptive proportion test. */ + TRNG_PREALM_TEST, /**< AIS31 preliminary noise alarm */ + TRNG_ALM_TEST, /**< AIS31 noise alarm. */ +} sx_trng_test_t; + +/** @brief structure used in save/restore TRNG state. Should be considered opaque */ +struct sx_trng_internal_state +{ + uint32_t control; + uint32_t key[4]; + uint32_t wakeup_lvl; + uint32_t swoff_timer; + uint32_t clk_divider; + uint32_t init_wait_cnt; +}; + +/** +* @brief TRNG initialization +* @param cond_test_en When not zero, conditioning test is executed first +* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR +*/ +uint32_t sx_trng_init(uint32_t cond_test_en) CHECK_RESULT; + +/** +* @brief First part of TRNG initialization +* For boot time optimization, the TRNG init can be split into 2 parts. The first +* part executes the conditioning test, makes some configurations and switches on +* the oscillator rings. After that it returns, allowing to call other functions +* while the TRNG FIFO is filling up in the background. +* @param cond_test_en When not zero, conditioning test is executed +* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR +*/ +uint32_t sx_trng_init_part1(uint32_t cond_test_en) CHECK_RESULT; + +/** +* @brief Second part of TRNG initialization +* For boot time optimization, the TRNG init can be split into 2 parts. The +* second part checks that startup tests were successful, once the TRNG FIFO is +* fully filled. Then it programs a random key for the conditioning function, +* resets the TRNG and returns. Note that the FIFO should be fully filled again +* and startup tests successful before reading the first piece of random data. +* This can be assured by using ::sx_trng_set_startup_chk_flag after TRNG init. +* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR +*/ +uint32_t sx_trng_init_part2(void) CHECK_RESULT; + +/** +* @brief Indicate whether conditioning or startup test failed during init. +* Only valid during bootloader and diagnostic mode! +* If false is returned, true randomness can't be warranted and user must react +* (i.e. raising tamper) +* @return boolean +*/ +bool sx_trng_startup_failed(void); + +/** +* @brief Sets a flag that tells the TRNG software module to wait for TRNG +* startup tests to be finished successfully before reading random data from the +* TRNG FIFO.This needs to be done after explicitly calling the ba431_softreset() +* in interrupt context and after TRNG initialization. +* +* The TRNG startup test will wait until the TRNG FIFO is filled with data and +* then check that the data is sufficiently random. If it is, the startup test is +* passed. The BA431 datasheet specifies that we shouldn't use data from the TRNG +* FIFO before it has been confirmed to be sufficiently random. +*/ +void sx_trng_set_startup_chk_flag(void); + +/** + * @brief Returns a 32-bit word containing the TRNG status register where all + * the bits have been zeroed out except the ones representing the repetition + * count test interrupt status, the adaptive proportion test interrupt status + * and (if enabled) the AIS31 noise alarm status. + * + * Bit 4 is the repetition count test interrupt status, bit 5 is the adaptive + * proportion test interrupt status and bit 9 is the AIS31 noise alarm status. + * If any of these bits is set, the corresponding test has failed. + */ +uint32_t sx_trng_critical_raised(void); + +/** +* @brief Applies a soft reset on the random generator and sets a flag that tells +* the TRNG software module to wait for TRNG startup tests to be finished +* successfully before reading random data from the TRNG FIFO. +* +* The TRNG startup test will wait until the TRNG FIFO is filled with data and +* then check that the data is sufficiently random. If it is, the startup test is +* passed. The BA431 datasheet specifies that we shouldn't use data from the TRNG +* FIFO before it has been confirmed to be sufficiently random. +*/ + +void sx_trng_apply_soft_reset(void); + +/** +* @brief Generate random data (block_t) +* @param dest Output location for the generated random data. +*/ +void sx_trng_get_rand_blk(block_t dest); + +/** +* @brief Get an array of random values +* @param dst Pointer to the array where the random values are stored +* @param size Number of random bytes to be generate +*/ +void sx_trng_get_rand(uint8_t *dst, uint32_t size); + +/** +* @brief Returns a random 32-bit word +* @return 32-bit random value +*/ +uint32_t sx_trng_get_word(void); + +/** +* @brief Generate a random block of data by the TRNG. Defined to match the +* prototype of the struct sx_rng get_rand_blk() +* @param param Should be set to NULL +* @param result block_t for the generated values +*/ +void sx_trng_fill_blk(void *param, block_t result); + +#ifdef UNITTESTS +uint32_t sx_trng_conditioning_test(void); +uint32_t sx_trng_wait_startup(void); +#endif + +/** + * @brief Return if the TRNG module is facing an error state + * + * This error could be due to start-up tests (NIST-800-90B Start-up Test or + * AIS31 Start-up Test) or due to online test (Adaptive Proportion Test or + * AIS31 Online Test) + */ + +bool sx_trng_is_error_detected(void); + +/** +* @brief Cause a TRNG to fail (on health tests) +* For test failure confirmation the TRNG interrupt needs to be checked. +* +* \note This test will wait until a ::BA431_STAT_MASK_PROP_FAIL even if other +* kind of BA431 failure is generated before. +*/ +void sx_trng_trigger_failure(void); + +/** +* @brief Cause a TRNG self test to fail for a specified test +* For test failure confirmation the TRNG status and/or interrupt needs to be +* checked. +* @param test Chosen TRNG self test +* @return CRYPTOLIB_SUCCESS if the TRNG was successfully configured for causing +* the test failure +*/ +uint32_t sx_trng_trigger_test_failure(sx_trng_test_t test); + +/** + * @brief Save a local copy of the TRNG internal configuration state + * @param copy is structure which will contain the internal state required to + * reconfigure the BA431 with specifics parameters + */ +void sx_trng_save_state(struct sx_trng_internal_state *copy); + +/** + * @brief Restore to the TRNG the internal configuration state + * @param source is a structure containing the config to restore to the TRNG + */ +void sx_trng_restore_state(struct sx_trng_internal_state *source); + +/** +* @brief TRNG initialization in order to provide RAW data +* @return CRYPTOLIB_SUCCESS or CRYPTOLIB_CRYPTO_ERR +*/ +uint32_t sx_trng_raw_init(void); + +#endif /* SX_TRNG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba411e_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba411e_config.h index fc7c188..46f0852 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba411e_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba411e_config.h @@ -1,125 +1,125 @@ -/** - * @file - * @brief Defines macros to be used for the configuration of the BA411E AES - * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved - */ - - -#ifndef BA411E_CONFIG_H -#define BA411E_CONFIG_H -#include -#include - -#include "sx_blk_cipher_common.h" -#include "sx_blk_cipher.h" - -/** @brief BA411E Mode Register mask for hardware key 1 & 2*/ -#define AES_MODEID_KEYX_MASK 0x000000C0 - -/* AES hardware configuration - register 1*/ -#define AES_HW_CFG_ECB_SUPPORTED_LSB 0 -#define AES_HW_CFG_ECB_SUPPORTED_MASK (1L<is_ecb_supported) -#define AES_HW_CFG_CBC_SUPPORTED (sx_aes_engine_get_config()->is_cbc_supported) -#define AES_HW_CFG_CTR_SUPPORTED (sx_aes_engine_get_config()->is_ctr_supported) -#define AES_HW_CFG_CFB_SUPPORTED (sx_aes_engine_get_config()->is_cfb_supported) -#define AES_HW_CFG_OFB_SUPPORTED (sx_aes_engine_get_config()->is_ofb_supported) -#define AES_HW_CFG_CCM_SUPPORTED (sx_aes_engine_get_config()->is_ccm_supported) -#define AES_HW_CFG_GCM_SUPPORTED (sx_aes_engine_get_config()->is_gcm_supported) -#define AES_HW_CFG_XTS_SUPPORTED (sx_aes_engine_get_config()->is_xts_supported) -#define AES_HW_CFG_CMAC_SUPPORTED (sx_aes_engine_get_config()->is_cmac_supported) -#define AES_HW_CFG_CS_EN (sx_aes_engine_get_config()->is_cipher_stealing_enabled) -#define AES_HW_CFG_CM_EN (sx_aes_engine_get_config()->is_coutermeasure_enabled) -#define AES_HW_CFG_KEY_SIZE_128_SUPPORTED (sx_aes_engine_get_config()->is_key_128b_supported) -#define AES_HW_CFG_KEY_SIZE_192_SUPPORTED (sx_aes_engine_get_config()->is_key_192b_supported) -#define AES_HW_CFG_KEY_SIZE_256_SUPPORTED (sx_aes_engine_get_config()->is_key_256b_supported) - -#else - -#define AES_HW_CFG_ECB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_ECB_SUPPORTED_MASK) -#define AES_HW_CFG_CBC_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CBC_SUPPORTED_MASK) -#define AES_HW_CFG_CTR_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CTR_SUPPORTED_MASK) -#define AES_HW_CFG_CFB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CFB_SUPPORTED_MASK) -#define AES_HW_CFG_OFB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_OFB_SUPPORTED_MASK) -#define AES_HW_CFG_CCM_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CCM_SUPPORTED_MASK) -#define AES_HW_CFG_GCM_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_GCM_SUPPORTED_MASK) -#define AES_HW_CFG_XTS_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_XTS_SUPPORTED_MASK) -#define AES_HW_CFG_CMAC_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CMAC_SUPPORTED_MASK) -#define AES_HW_CFG_CS_EN (BA411E_HW_CFG_1 & AES_HW_CFG_CS_EN_MASK) -#define AES_HW_CFG_CM_EN (BA411E_HW_CFG_1 & AES_HW_CFG_CM_EN_MASK) -#define AES_HW_CFG_KEY_SIZE_128_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_128_SUPPORTED_MASK) -#define AES_HW_CFG_KEY_SIZE_192_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_192_SUPPORTED_MASK) -#define AES_HW_CFG_KEY_SIZE_256_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_256_SUPPORTED_MASK) - -#endif +/** + * @file + * @brief Defines macros to be used for the configuration of the BA411E AES + * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved + */ + + +#ifndef BA411E_CONFIG_H +#define BA411E_CONFIG_H +#include +#include + +#include "sx_blk_cipher_common.h" +#include "sx_blk_cipher.h" + +/** @brief BA411E Mode Register mask for hardware key 1 & 2*/ +#define AES_MODEID_KEYX_MASK 0x000000C0 + +/* AES hardware configuration - register 1*/ +#define AES_HW_CFG_ECB_SUPPORTED_LSB 0 +#define AES_HW_CFG_ECB_SUPPORTED_MASK (1L<is_ecb_supported) +#define AES_HW_CFG_CBC_SUPPORTED (sx_aes_engine_get_config()->is_cbc_supported) +#define AES_HW_CFG_CTR_SUPPORTED (sx_aes_engine_get_config()->is_ctr_supported) +#define AES_HW_CFG_CFB_SUPPORTED (sx_aes_engine_get_config()->is_cfb_supported) +#define AES_HW_CFG_OFB_SUPPORTED (sx_aes_engine_get_config()->is_ofb_supported) +#define AES_HW_CFG_CCM_SUPPORTED (sx_aes_engine_get_config()->is_ccm_supported) +#define AES_HW_CFG_GCM_SUPPORTED (sx_aes_engine_get_config()->is_gcm_supported) +#define AES_HW_CFG_XTS_SUPPORTED (sx_aes_engine_get_config()->is_xts_supported) +#define AES_HW_CFG_CMAC_SUPPORTED (sx_aes_engine_get_config()->is_cmac_supported) +#define AES_HW_CFG_CS_EN (sx_aes_engine_get_config()->is_cipher_stealing_enabled) +#define AES_HW_CFG_CM_EN (sx_aes_engine_get_config()->is_coutermeasure_enabled) +#define AES_HW_CFG_KEY_SIZE_128_SUPPORTED (sx_aes_engine_get_config()->is_key_128b_supported) +#define AES_HW_CFG_KEY_SIZE_192_SUPPORTED (sx_aes_engine_get_config()->is_key_192b_supported) +#define AES_HW_CFG_KEY_SIZE_256_SUPPORTED (sx_aes_engine_get_config()->is_key_256b_supported) + +#else + +#define AES_HW_CFG_ECB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_ECB_SUPPORTED_MASK) +#define AES_HW_CFG_CBC_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CBC_SUPPORTED_MASK) +#define AES_HW_CFG_CTR_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CTR_SUPPORTED_MASK) +#define AES_HW_CFG_CFB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CFB_SUPPORTED_MASK) +#define AES_HW_CFG_OFB_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_OFB_SUPPORTED_MASK) +#define AES_HW_CFG_CCM_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CCM_SUPPORTED_MASK) +#define AES_HW_CFG_GCM_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_GCM_SUPPORTED_MASK) +#define AES_HW_CFG_XTS_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_XTS_SUPPORTED_MASK) +#define AES_HW_CFG_CMAC_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_CMAC_SUPPORTED_MASK) +#define AES_HW_CFG_CS_EN (BA411E_HW_CFG_1 & AES_HW_CFG_CS_EN_MASK) +#define AES_HW_CFG_CM_EN (BA411E_HW_CFG_1 & AES_HW_CFG_CM_EN_MASK) +#define AES_HW_CFG_KEY_SIZE_128_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_128_SUPPORTED_MASK) +#define AES_HW_CFG_KEY_SIZE_192_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_192_SUPPORTED_MASK) +#define AES_HW_CFG_KEY_SIZE_256_SUPPORTED (BA411E_HW_CFG_1 & AES_HW_CFG_KEY_SIZE_256_SUPPORTED_MASK) + +#endif #endif \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba413_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba413_config.h index 2e7b79f..771d084 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba413_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba413_config.h @@ -1,124 +1,124 @@ -/** - * @file - * @brief Defines the procedures to make operations with - * the BA413 hash function - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef BA413_CONFIG_H -#define BA413_CONFIG_H - -#include -#include -#include "sx_hw_cfg.h" - -struct ba413_regs_s { - volatile uint32_t config; -}; - - -/** @brief Value for ::ba413_regs_s.config, set mode to MD5 */ -#define BA413_CONF_MODE_MD5 0x00000001 -/** @brief Value for ::ba413_regs_s.config, set mode to SHA1 */ -#define BA413_CONF_MODE_SHA1 0x00000002 -/** @brief Value for ::ba413_regs_s.config, set mode to SHA224 */ -#define BA413_CONF_MODE_SHA224 0x00000004 -/** @brief Value for ::ba413_regs_s.config, set mode to SHA256 */ -#define BA413_CONF_MODE_SHA256 0x00000008 -/** @brief Value for ::ba413_regs_s.config, set mode to SHA384 */ -#define BA413_CONF_MODE_SHA384 0X00000010 -/** @brief Value for ::ba413_regs_s.config, set mode to SHA512 */ -#define BA413_CONF_MODE_SHA512 0x00000020 -/** @brief Value for ::ba413_regs_s.config, set mode to SM3 */ -#define BA413_CONF_MODE_SM3 0x00000040 - -/** @brief Value for ::ba413_regs_s.config, enable HMAC */ -#define BA413_CONF_HMAC 0x00000100 -/** @brief Value for ::ba413_regs_s.config, enable padding in hardware */ -#define BA413_CONF_HWPAD 0x00000200 -/** @brief Value for ::ba413_regs_s.config, set as final (return digest and not state) */ -#define BA413_CONF_FINAL 0x00000400 - -/* Hardware configuration register. */ -#define BA413_HW_CFG_MD5_SUPPORTED_LSB 0 -#define BA413_HW_CFG_MD5_SUPPORTED_MASK (1L<is_md5_enabled) -#define BA413_HW_CFG_SHA1_SUPPORTED (sx_hash_engine_get_config()->is_sha1_enabled) -#define BA413_HW_CFG_SHA224_SUPPORTED (sx_hash_engine_get_config()->is_sha224_enabled) -#define BA413_HW_CFG_SHA256_SUPPORTED (sx_hash_engine_get_config()->is_sha256_enabled) -#define BA413_HW_CFG_SHA384_SUPPORTED (sx_hash_engine_get_config()->is_sha384_enabled) -#define BA413_HW_CFG_SHA512_SUPPORTED (sx_hash_engine_get_config()->is_sha512_enabled) -#define BA413_HW_CFG_SM3_SUPPORTED (sx_hash_engine_get_config()->is_sm3_enabled) -#define BA413_HW_CFG_PADDING_SUPPORTED (sx_hash_engine_get_config()->is_padding_enabled) -#define BA413_HW_CFG_HMAC_SUPPORTED (sx_hash_engine_get_config()->is_hmac_enabled) -#define BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED (sx_hash_engine_get_config()->is_verify_digest_enabled) - -#else - -#define BA413_HW_CFG_MD5_SUPPORTED (BA413_HW_CFG_MD5_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SHA1_SUPPORTED (BA413_HW_CFG_SHA1_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SHA224_SUPPORTED (BA413_HW_CFG_SHA224_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SHA256_SUPPORTED (BA413_HW_CFG_SHA256_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SHA384_SUPPORTED (BA413_HW_CFG_SHA384_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SHA512_SUPPORTED (BA413_HW_CFG_SHA512_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_SM3_SUPPORTED (BA413_HW_CFG_SM3_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_PADDING_SUPPORTED (BA413_HW_CFG_PADDING_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_HMAC_SUPPORTED (BA413_HW_CFG_HMAC_SUPPORTED_MASK & BA413_HW_CFG) -#define BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED (BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED_MASK & BA413_HW_CFG) - -#endif - -#endif +/** + * @file + * @brief Defines the procedures to make operations with + * the BA413 hash function + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef BA413_CONFIG_H +#define BA413_CONFIG_H + +#include +#include +#include "sx_hw_cfg.h" + +struct ba413_regs_s { + volatile uint32_t config; +}; + + +/** @brief Value for ::ba413_regs_s.config, set mode to MD5 */ +#define BA413_CONF_MODE_MD5 0x00000001 +/** @brief Value for ::ba413_regs_s.config, set mode to SHA1 */ +#define BA413_CONF_MODE_SHA1 0x00000002 +/** @brief Value for ::ba413_regs_s.config, set mode to SHA224 */ +#define BA413_CONF_MODE_SHA224 0x00000004 +/** @brief Value for ::ba413_regs_s.config, set mode to SHA256 */ +#define BA413_CONF_MODE_SHA256 0x00000008 +/** @brief Value for ::ba413_regs_s.config, set mode to SHA384 */ +#define BA413_CONF_MODE_SHA384 0X00000010 +/** @brief Value for ::ba413_regs_s.config, set mode to SHA512 */ +#define BA413_CONF_MODE_SHA512 0x00000020 +/** @brief Value for ::ba413_regs_s.config, set mode to SM3 */ +#define BA413_CONF_MODE_SM3 0x00000040 + +/** @brief Value for ::ba413_regs_s.config, enable HMAC */ +#define BA413_CONF_HMAC 0x00000100 +/** @brief Value for ::ba413_regs_s.config, enable padding in hardware */ +#define BA413_CONF_HWPAD 0x00000200 +/** @brief Value for ::ba413_regs_s.config, set as final (return digest and not state) */ +#define BA413_CONF_FINAL 0x00000400 + +/* Hardware configuration register. */ +#define BA413_HW_CFG_MD5_SUPPORTED_LSB 0 +#define BA413_HW_CFG_MD5_SUPPORTED_MASK (1L<is_md5_enabled) +#define BA413_HW_CFG_SHA1_SUPPORTED (sx_hash_engine_get_config()->is_sha1_enabled) +#define BA413_HW_CFG_SHA224_SUPPORTED (sx_hash_engine_get_config()->is_sha224_enabled) +#define BA413_HW_CFG_SHA256_SUPPORTED (sx_hash_engine_get_config()->is_sha256_enabled) +#define BA413_HW_CFG_SHA384_SUPPORTED (sx_hash_engine_get_config()->is_sha384_enabled) +#define BA413_HW_CFG_SHA512_SUPPORTED (sx_hash_engine_get_config()->is_sha512_enabled) +#define BA413_HW_CFG_SM3_SUPPORTED (sx_hash_engine_get_config()->is_sm3_enabled) +#define BA413_HW_CFG_PADDING_SUPPORTED (sx_hash_engine_get_config()->is_padding_enabled) +#define BA413_HW_CFG_HMAC_SUPPORTED (sx_hash_engine_get_config()->is_hmac_enabled) +#define BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED (sx_hash_engine_get_config()->is_verify_digest_enabled) + +#else + +#define BA413_HW_CFG_MD5_SUPPORTED (BA413_HW_CFG_MD5_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SHA1_SUPPORTED (BA413_HW_CFG_SHA1_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SHA224_SUPPORTED (BA413_HW_CFG_SHA224_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SHA256_SUPPORTED (BA413_HW_CFG_SHA256_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SHA384_SUPPORTED (BA413_HW_CFG_SHA384_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SHA512_SUPPORTED (BA413_HW_CFG_SHA512_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_SM3_SUPPORTED (BA413_HW_CFG_SM3_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_PADDING_SUPPORTED (BA413_HW_CFG_PADDING_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_HMAC_SUPPORTED (BA413_HW_CFG_HMAC_SUPPORTED_MASK & BA413_HW_CFG) +#define BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED (BA413_HW_CFG_VERIFY_DIGEST_SUPPORTED_MASK & BA413_HW_CFG) + +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c index e2afbec..d9274f8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c @@ -1,514 +1,514 @@ -/** - * @file - * @brief This file contains useful functions to configure registers of the BA4414E - * PointerReg, CommandReg, ControlReg, StatusReg - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#include "ba414ep_config.h" -#include -#include -#include "sxregs.h" -#include "cryptodma_internal.h" -#include "sx_memcpy.h" -#include "sx_math.h" -#include "sx_rng.h" -#include "sx_errors.h" -#include "sx_hw_cfg.h" - -static BA414EPRegs_t * const BA414EP_REGS = (BA414EPRegs_t *)ADDR_BA414EP_REGS; -const volatile uint32_t * const ADDR_BA414EP_HW_CFG = &(((BA414EPRegs_t *)ADDR_BA414EP_REGS)->HwConfigReg); - - -// #define PK_DEBUG_ENABLED - -#ifdef PK_DEBUG_ENABLED -static void CRYPTOLIB_PRINT_BLK(block_t blk) -{ - if (blk.flags & BLOCK_S_CONST_ADDR) - return; - for (uint32_t i = 0; i < blk.len; i++) { - if ((i != 0) && (i % 16 == 0)) - CRYPTOLIB_PRINTF("\n"); - CRYPTOLIB_PRINTF("0x%02x, ", blk.addr[i]); - } - CRYPTOLIB_PRINTF("\n"); -} -#endif - -#if PK_CM_ENABLED -struct sx_rng pk_rng = { - .param= NULL, - .get_rand_blk = NULL -}; - -void ba414ep_set_rng(struct sx_rng rng) -{ - pk_rng = rng; -} -#endif - - -/** @brief This function starts the given PK - * @return The start bit of the CommandReg of the given BA414EP struct has been set - * to appropriate value. - */ -static void ba414ep_start(void){ - uint32_t DataReg = 0x1<ControlReg, DataReg ); -} - - -/** - * @brief Function is used to get the full contents of the BA414EP status register - * @return the contents oft he status register as uint32_t. - */ -static CHECK_RESULT uint32_t ba414ep_get_status(void) -{ - return RD_REG32(&BA414EP_REGS->StatusReg); -} - - -/** @brief: Function tells if a given Public Key is Busy or not (checking its status register) - * @return 1 when given pub key is busy, 0 otherwise - */ -#if WAIT_PK_WITH_REGISTER_POLLING -static CHECK_RESULT int ba414ep_is_busy(void) -{ - uint32_t status = ba414ep_get_status(); - return ((status >> (BA414EP_STS_BUSY_LSB)) & 0x1); -} -#endif - - -/** - * @brief Function is used to wait for an interrupt, and read & return the status register - * @return the contents of the status register as uint32_t. - */ -static CHECK_RESULT uint32_t ba414ep_wait_status(void) -{ - #if WAIT_PK_WITH_REGISTER_POLLING - while(ba414ep_is_busy()); - #else - PK_WAITIRQ_FCT(); - #endif - - - return (ba414ep_get_status() & BA414EP_STS_ERROR_MASK); -} - - -void ba414ep_set_config(uint32_t PtrA, uint32_t PtrB, uint32_t PtrC, uint32_t PtrN) -{ - uint32_t DataReg = 0x00000000; - DataReg = ((PtrC<PointerReg, DataReg); -} - -uint32_t ba414ep_set_command(uint32_t op, uint32_t operandsize, uint32_t swap, uint32_t curve_flags) -{ - uint32_t DataReg = 0x80000000; - uint32_t NumberOfBytes; - - if (operandsize > 0) { - NumberOfBytes = operandsize - 1; - } else { - NumberOfBytes = 0; - } - - // Check that the operand size encoding does not exceed the max allocated size. - if (NumberOfBytes > (BA414EP_CMD_OPSIZE_MASK >> BA414EP_CMD_OPSIZE_LSB)) { - return CRYPTOLIB_UNSUPPORTED_ERR; - } - - // Data ram is erased automatically after reset in PK engine. - // Wait until erasing is finished before writing any data - // (this routine is called before any data transfer) - #if WAIT_PK_WITH_REGISTER_POLLING - while(ba414ep_is_busy()); - #else - PK_WAITIRQ_FCT(); - #endif - - DataReg = DataReg | op; - DataReg = DataReg | BA414EP_CMD_OPSIZE(NumberOfBytes); - #if PK_CM_ENABLED - // Counter-Measures for the Public Key - if (BA414EP_IS_OP_WITH_PTMUL_CM(op)) { - // ECC operation - DataReg = DataReg | (BA414EP_CMD_RANDPR(PK_CM_RAND_PROJ)); - DataReg = DataReg | (BA414EP_CMD_RANDKE(PK_CM_RAND_SCALAR)); - } else if (BA414EP_IS_OP_WITH_EXPO_CM(op)) { - // Modular operations - DataReg = DataReg | (BA414EP_CMD_RANDMOD(PK_CM_RAND_MODULUS)); - DataReg = DataReg | (BA414EP_CMD_RANDKE(PK_CM_RAND_EXPONENT)); - } - #endif - DataReg = DataReg | (BA414EP_CMD_SWAP_MASK & (swap << BA414EP_CMD_SWAP_LSB)); - DataReg = DataReg | curve_flags; - - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Set command PK %08x\n", DataReg); - #endif - - WR_REG32(&BA414EP_REGS->CommandReg, DataReg ); - - - #if PK_CM_ENABLED - CRYPTOLIB_ASSERT_NM(pk_rng.get_rand_blk != NULL); - // Copy random value in the CryptoRAM for the counter-measures - if ((BA414EP_IS_OP_WITH_PTMUL_CM(op) && (PK_CM_RAND_SCALAR || PK_CM_RAND_PROJ)) || - (BA414EP_IS_OP_WITH_EXPO_CM(op) && (PK_CM_RAND_EXPONENT || PK_CM_RAND_MODULUS))) { - uint8_t pk_cm_rand[8] = { 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5 }; - block_t rnd_blk = block_t_convert(pk_cm_rand, PK_CM_RAND_SIZE); - - // Generate non-null random value - do { - pk_rng.get_rand_blk(pk_rng.param, rnd_blk); - } while(!sx_math_array_is_not_null(rnd_blk.addr, PK_CM_RAND_SIZE)); - - // Random has to be odd - if (BA414EP_IS_OP_WITH_EXPO_CM(op) && PK_CM_RAND_MODULUS) { - pk_cm_rand[PK_CM_RAND_SIZE-1] |= 1; - } - - // Copy random to cryptoRAM (pad with 0 if smaller than operandsize) - if (swap) { - mem2CryptoRAM_rev(rnd_blk, roundup_32(operandsize), BA414EP_MEMLOC_15); - } else { - mem2CryptoRAM(rnd_blk, roundup_32(operandsize), BA414EP_MEMLOC_15); - } - } - #endif - return CRYPTOLIB_SUCCESS; -} - - -void mem2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset) -{ - if(src.len > size) { - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("mem2CryptoRAM_rev: Src longer (=%d) than size (=%d) (cutting) !\n", - src.len, size); - #endif - - src.len = size; - } - - if(!src.len || !size){ - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("mem2CryptoRAM_rev: Src or size is null (skip) !\n"); - #endif - - return; - } - - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Write (rev) %d bytes padded to %d to loc %d:\n", src.len, size, offset); - #endif - - block_t dst; - dst.flags = BLOCK_S_INCR_ADDR; - dst.len = size; - dst.addr = BA414EP_ADDR_MEMLOC(offset, src.len); - memcpy_blk(dst, src, src.len); - - if(src.len < size) { - dst.addr = BA414EP_ADDR_MEMLOC(offset, size); - sx_memset(dst.addr, 0, size - src.len); - } - #ifdef PK_DEBUG_ENABLED - dst.addr = BA414EP_ADDR_MEMLOC(offset, size); - CRYPTOLIB_PRINT_BLK(dst); - #endif -} - -void point2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset) { - struct dma_sg_descr_s desc_from; - struct dma_sg_descr_s desc_to[2]; - -#ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: DMA transfer point (rev): " - "%d bytes to loc %d & %d with operand size = %d\n", - src.len, offset, offset+1, size); -#endif - CRYPTOLIB_ASSERT((src.len >= size*2), "source length less then point size."); - - write_desc( - &desc_from, - src.addr, - (src.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(src.len) : 2 * size), //XXX the source length can be bigger then the transfer size - src.flags, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_from); - - write_desc( - &desc_to[0], - BA414EP_ADDR_MEMLOC(offset, size), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - - write_desc( - &desc_to[1], - BA414EP_ADDR_MEMLOC(offset + 1, size), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_to[1]); - - cryptodma_run_sg(&desc_from, desc_to); - - #ifdef PK_DEBUG_ENABLED - block_t dbg; - dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); - dbg.len = size; - dbg.flags = BLOCK_S_INCR_ADDR; - CRYPTOLIB_PRINT_BLK(dbg); - dbg.addr = BA414EP_ADDR_MEMLOC(offset+1, size); - CRYPTOLIB_PRINT_BLK(dbg); - #endif -} - -void point2CryptoRAM(block_t src, uint32_t size, uint32_t offset) { - struct dma_sg_descr_s desc_from; - struct dma_sg_descr_s desc_to[2]; - -#ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: DMA transfer point: " - "%d bytes to loc %d & %d with operand size = %d\n", - src.len, offset, offset + 1, size); -#endif - CRYPTOLIB_ASSERT((src.len >= size*2), "source length less then point size."); - - write_desc( - &desc_from, - src.addr, - (src.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(src.len) : 2 * size), //XXX the source length can be bigger then the transfer size - src.flags, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_from); - - write_desc( - &desc_to[0], - BA414EP_ADDR_MEMLOC(offset - 1, 0), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - - write_desc( - &desc_to[1], - BA414EP_ADDR_MEMLOC(offset, 0), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_to[1]); - - cryptodma_run_sg(&desc_from, desc_to); -} - -void CryptoRAM2point_rev(block_t dst, uint32_t size, uint32_t offset) { - struct dma_sg_descr_s desc_from[2]; - struct dma_sg_descr_s desc_to; - -#ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Read point (rev): @Address: %p ," - "%d bytes from loc %d & %d with operand size = %d\n", - dst.addr, dst.len, offset, offset+1, size); - block_t dbg; - dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); - dbg.len = size; - dbg.flags = BLOCK_S_INCR_ADDR; - CRYPTOLIB_PRINT_BLK(dbg); - dbg.addr = BA414EP_ADDR_MEMLOC(offset + 1, size); - CRYPTOLIB_PRINT_BLK(dbg); -#endif - CRYPTOLIB_ASSERT((dst.len >= size*2), "destination length smaller then point size."); - - write_desc( - &desc_from[0], - BA414EP_ADDR_MEMLOC(offset, size), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - - write_desc( - &desc_from[1], - BA414EP_ADDR_MEMLOC(offset + 1, size), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_from[1]); - - write_desc( - &desc_to, - dst.addr, - (dst.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(dst.len) : 2 * size), //XXX the destination length can be bigger then the transfer size - dst.flags, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_to); - - cryptodma_run_sg(desc_from, &desc_to); -} - -void CryptoRAM2point(block_t dst, uint32_t size, uint32_t offset) { - struct dma_sg_descr_s desc_from[2]; - struct dma_sg_descr_s desc_to; - -#ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Read point: " - "%d bytes from loc %d & %d with operand size = %d\n", - dst.len, offset, offset+1, size); - block_t dbg; - dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); - dbg.len = size; - dbg.flags = BLOCK_S_INCR_ADDR; - CRYPTOLIB_PRINT_BLK(dbg); - dbg.addr = BA414EP_ADDR_MEMLOC(offset + 1, size); - CRYPTOLIB_PRINT_BLK(dbg); -#endif - CRYPTOLIB_ASSERT((dst.len >= size*2), "destination length smaller then point size."); - - write_desc( - &desc_from[0], - BA414EP_ADDR_MEMLOC(offset - 1, 0), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - - write_desc( - &desc_from[1], - BA414EP_ADDR_MEMLOC(offset, 0), - size, - BLOCK_S_INCR_ADDR, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_from[1]); - - write_desc( - &desc_to, - dst.addr, - (dst.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(dst.len) : 2 * size), //XXX the destination length can be bigger then the transfer size - dst.flags, - DMA_SG_ENGINESELECT_BYPASS); - set_last_desc(&desc_to); - - cryptodma_run_sg(desc_from, &desc_to); -} - - -void CryptoRAM2mem_rev(block_t dst, uint32_t size, uint32_t offset) -{ - block_t src; - - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Read mem (rev): @Address: %p, %d bytes " - "from loc %d:\n", dst.addr, size, offset); - block_t dbg; - dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); - dbg.len = size; - dbg.flags = BLOCK_S_INCR_ADDR; - CRYPTOLIB_PRINT_BLK(dbg); - #endif - - src.addr = BA414EP_ADDR_MEMLOC(offset, size); - src.len = size; - src.flags = BLOCK_S_INCR_ADDR; - memcpy_blk(dst, src, size); -} - -void mem2CryptoRAM(block_t src, uint32_t size, uint32_t offset) -{ - block_t dst; - - dst.addr = BA414EP_ADDR_MEMLOC(offset - 1, 0); - dst.len = size; - dst.flags = BLOCK_S_INCR_ADDR; - memcpy_blk(dst, src, size); - - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Write %d bytes to loc %d:\n", size, offset); - CRYPTOLIB_PRINT_BLK(dst); - #endif -} - -void CryptoRAM2mem(block_t dst, uint32_t size, uint32_t offset) -{ - block_t src; - - src.addr = BA414EP_ADDR_MEMLOC(offset - 1, 0); - src.len = size; - src.flags = BLOCK_S_INCR_ADDR; - memcpy_blk(dst, src, size); - - #ifdef PK_DEBUG_ENABLED - CRYPTOLIB_PRINTF("Debug BA414EP: Read %d bytes from loc %d:\n", size, offset); - CRYPTOLIB_PRINT_BLK(src); - #endif -} - - -uint32_t ba414ep_start_wait_status(void) -{ - uint32_t status; - ba414ep_start(); - status = ba414ep_wait_status(); -#ifdef PK_DEBUG_ENABLED - if(status) { -#else - if (status&~(BA414EP_STS_BADSIGNATURE_MASK|BA414EP_STS_NOTPRIME_MASK|BA414EP_STS_NOTINVERTIBLE_MASK)) { -#endif - CRYPTOLIB_PRINTF("BA414EP: error status: %08X\n", status); - } - return status; -} - - -void ba414ep_load_curve( - block_t curve, - uint32_t size, - uint32_t byte_swap, - uint32_t gen) -{ - uint32_t i; - - block_t param; - param.addr = curve.addr; - param.len = size; - param.flags = curve.flags; - - /* Load ECC parameters */ - for (i=0; i * size < curve.len; i++) { - if (gen || (i != 2 && i != 3)) { - if (byte_swap) - mem2CryptoRAM_rev(param, size, i); - else - mem2CryptoRAM(param, size, i); - } - - if (!(param.flags & BLOCK_S_CONST_ADDR)) - param.addr += param.len; - } -} - - - -uint32_t ba414ep_load_and_modN(uint8_t outloc, uint8_t nloc, uint32_t size, block_t in, block_t out, uint32_t flags) -{ - uint32_t result = ba414ep_set_command(BA414EP_OPTYPE_MOD_RED_ODD, size, BA414EP_BIGEND, flags); - if (result) - return result; - - ba414ep_set_config(outloc, outloc, outloc, nloc); - mem2CryptoRAM_rev(in, size, outloc); - if(ba414ep_start_wait_status()) - return CRYPTOLIB_CRYPTO_ERR; - - CryptoRAM2mem_rev(out, size, outloc); - - return CRYPTOLIB_SUCCESS; -} +/** + * @file + * @brief This file contains useful functions to configure registers of the BA4414E + * PointerReg, CommandReg, ControlReg, StatusReg + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include "ba414ep_config.h" +#include +#include +#include "sxregs.h" +#include "cryptodma_internal.h" +#include "sx_memcpy.h" +#include "sx_math.h" +#include "sx_rng.h" +#include "sx_errors.h" +#include "sx_hw_cfg.h" + +static BA414EPRegs_t * const BA414EP_REGS = (BA414EPRegs_t *)ADDR_BA414EP_REGS; +const volatile uint32_t * const ADDR_BA414EP_HW_CFG = &(((BA414EPRegs_t *)ADDR_BA414EP_REGS)->HwConfigReg); + + +// #define PK_DEBUG_ENABLED + +#ifdef PK_DEBUG_ENABLED +static void CRYPTOLIB_PRINT_BLK(block_t blk) +{ + if (blk.flags & BLOCK_S_CONST_ADDR) + return; + for (uint32_t i = 0; i < blk.len; i++) { + if ((i != 0) && (i % 16 == 0)) + CRYPTOLIB_PRINTF("\n"); + CRYPTOLIB_PRINTF("0x%02x, ", blk.addr[i]); + } + CRYPTOLIB_PRINTF("\n"); +} +#endif + +#if PK_CM_ENABLED +struct sx_rng pk_rng = { + .param= NULL, + .get_rand_blk = NULL +}; + +void ba414ep_set_rng(struct sx_rng rng) +{ + pk_rng = rng; +} +#endif + + +/** @brief This function starts the given PK + * @return The start bit of the CommandReg of the given BA414EP struct has been set + * to appropriate value. + */ +static void ba414ep_start(void){ + uint32_t DataReg = 0x1<ControlReg, DataReg ); +} + + +/** + * @brief Function is used to get the full contents of the BA414EP status register + * @return the contents oft he status register as uint32_t. + */ +static CHECK_RESULT uint32_t ba414ep_get_status(void) +{ + return RD_REG32(&BA414EP_REGS->StatusReg); +} + + +/** @brief: Function tells if a given Public Key is Busy or not (checking its status register) + * @return 1 when given pub key is busy, 0 otherwise + */ +#if WAIT_PK_WITH_REGISTER_POLLING +static CHECK_RESULT int ba414ep_is_busy(void) +{ + uint32_t status = ba414ep_get_status(); + return ((status >> (BA414EP_STS_BUSY_LSB)) & 0x1); +} +#endif + + +/** + * @brief Function is used to wait for an interrupt, and read & return the status register + * @return the contents of the status register as uint32_t. + */ +static CHECK_RESULT uint32_t ba414ep_wait_status(void) +{ + #if WAIT_PK_WITH_REGISTER_POLLING + while(ba414ep_is_busy()); + #else + PK_WAITIRQ_FCT(); + #endif + + + return (ba414ep_get_status() & BA414EP_STS_ERROR_MASK); +} + + +void ba414ep_set_config(uint32_t PtrA, uint32_t PtrB, uint32_t PtrC, uint32_t PtrN) +{ + uint32_t DataReg = 0x00000000; + DataReg = ((PtrC<PointerReg, DataReg); +} + +uint32_t ba414ep_set_command(uint32_t op, uint32_t operandsize, uint32_t swap, uint32_t curve_flags) +{ + uint32_t DataReg = 0x80000000; + uint32_t NumberOfBytes; + + if (operandsize > 0) { + NumberOfBytes = operandsize - 1; + } else { + NumberOfBytes = 0; + } + + // Check that the operand size encoding does not exceed the max allocated size. + if (NumberOfBytes > (BA414EP_CMD_OPSIZE_MASK >> BA414EP_CMD_OPSIZE_LSB)) { + return CRYPTOLIB_UNSUPPORTED_ERR; + } + + // Data ram is erased automatically after reset in PK engine. + // Wait until erasing is finished before writing any data + // (this routine is called before any data transfer) + #if WAIT_PK_WITH_REGISTER_POLLING + while(ba414ep_is_busy()); + #else + PK_WAITIRQ_FCT(); + #endif + + DataReg = DataReg | op; + DataReg = DataReg | BA414EP_CMD_OPSIZE(NumberOfBytes); + #if PK_CM_ENABLED + // Counter-Measures for the Public Key + if (BA414EP_IS_OP_WITH_PTMUL_CM(op)) { + // ECC operation + DataReg = DataReg | (BA414EP_CMD_RANDPR(PK_CM_RAND_PROJ)); + DataReg = DataReg | (BA414EP_CMD_RANDKE(PK_CM_RAND_SCALAR)); + } else if (BA414EP_IS_OP_WITH_EXPO_CM(op)) { + // Modular operations + DataReg = DataReg | (BA414EP_CMD_RANDMOD(PK_CM_RAND_MODULUS)); + DataReg = DataReg | (BA414EP_CMD_RANDKE(PK_CM_RAND_EXPONENT)); + } + #endif + DataReg = DataReg | (BA414EP_CMD_SWAP_MASK & (swap << BA414EP_CMD_SWAP_LSB)); + DataReg = DataReg | curve_flags; + + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Set command PK %08x\n", DataReg); + #endif + + WR_REG32(&BA414EP_REGS->CommandReg, DataReg ); + + + #if PK_CM_ENABLED + CRYPTOLIB_ASSERT_NM(pk_rng.get_rand_blk != NULL); + // Copy random value in the CryptoRAM for the counter-measures + if ((BA414EP_IS_OP_WITH_PTMUL_CM(op) && (PK_CM_RAND_SCALAR || PK_CM_RAND_PROJ)) || + (BA414EP_IS_OP_WITH_EXPO_CM(op) && (PK_CM_RAND_EXPONENT || PK_CM_RAND_MODULUS))) { + uint8_t pk_cm_rand[8] = { 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5, 0xb5 }; + block_t rnd_blk = block_t_convert(pk_cm_rand, PK_CM_RAND_SIZE); + + // Generate non-null random value + do { + pk_rng.get_rand_blk(pk_rng.param, rnd_blk); + } while(!sx_math_array_is_not_null(rnd_blk.addr, PK_CM_RAND_SIZE)); + + // Random has to be odd + if (BA414EP_IS_OP_WITH_EXPO_CM(op) && PK_CM_RAND_MODULUS) { + pk_cm_rand[PK_CM_RAND_SIZE-1] |= 1; + } + + // Copy random to cryptoRAM (pad with 0 if smaller than operandsize) + if (swap) { + mem2CryptoRAM_rev(rnd_blk, roundup_32(operandsize), BA414EP_MEMLOC_15); + } else { + mem2CryptoRAM(rnd_blk, roundup_32(operandsize), BA414EP_MEMLOC_15); + } + } + #endif + return CRYPTOLIB_SUCCESS; +} + + +void mem2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset) +{ + if(src.len > size) { + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("mem2CryptoRAM_rev: Src longer (=%d) than size (=%d) (cutting) !\n", + src.len, size); + #endif + + src.len = size; + } + + if(!src.len || !size){ + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("mem2CryptoRAM_rev: Src or size is null (skip) !\n"); + #endif + + return; + } + + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Write (rev) %d bytes padded to %d to loc %d:\n", src.len, size, offset); + #endif + + block_t dst; + dst.flags = BLOCK_S_INCR_ADDR; + dst.len = size; + dst.addr = BA414EP_ADDR_MEMLOC(offset, src.len); + memcpy_blk(dst, src, src.len); + + if(src.len < size) { + dst.addr = BA414EP_ADDR_MEMLOC(offset, size); + sx_memset(dst.addr, 0, size - src.len); + } + #ifdef PK_DEBUG_ENABLED + dst.addr = BA414EP_ADDR_MEMLOC(offset, size); + CRYPTOLIB_PRINT_BLK(dst); + #endif +} + +void point2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset) { + struct dma_sg_descr_s desc_from; + struct dma_sg_descr_s desc_to[2]; + +#ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: DMA transfer point (rev): " + "%d bytes to loc %d & %d with operand size = %d\n", + src.len, offset, offset+1, size); +#endif + CRYPTOLIB_ASSERT((src.len >= size*2), "source length less then point size."); + + write_desc( + &desc_from, + src.addr, + (src.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(src.len) : 2 * size), //XXX the source length can be bigger then the transfer size + src.flags, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_from); + + write_desc( + &desc_to[0], + BA414EP_ADDR_MEMLOC(offset, size), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + + write_desc( + &desc_to[1], + BA414EP_ADDR_MEMLOC(offset + 1, size), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_to[1]); + + cryptodma_run_sg(&desc_from, desc_to); + + #ifdef PK_DEBUG_ENABLED + block_t dbg; + dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); + dbg.len = size; + dbg.flags = BLOCK_S_INCR_ADDR; + CRYPTOLIB_PRINT_BLK(dbg); + dbg.addr = BA414EP_ADDR_MEMLOC(offset+1, size); + CRYPTOLIB_PRINT_BLK(dbg); + #endif +} + +void point2CryptoRAM(block_t src, uint32_t size, uint32_t offset) { + struct dma_sg_descr_s desc_from; + struct dma_sg_descr_s desc_to[2]; + +#ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: DMA transfer point: " + "%d bytes to loc %d & %d with operand size = %d\n", + src.len, offset, offset + 1, size); +#endif + CRYPTOLIB_ASSERT((src.len >= size*2), "source length less then point size."); + + write_desc( + &desc_from, + src.addr, + (src.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(src.len) : 2 * size), //XXX the source length can be bigger then the transfer size + src.flags, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_from); + + write_desc( + &desc_to[0], + BA414EP_ADDR_MEMLOC(offset - 1, 0), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + + write_desc( + &desc_to[1], + BA414EP_ADDR_MEMLOC(offset, 0), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_to[1]); + + cryptodma_run_sg(&desc_from, desc_to); +} + +void CryptoRAM2point_rev(block_t dst, uint32_t size, uint32_t offset) { + struct dma_sg_descr_s desc_from[2]; + struct dma_sg_descr_s desc_to; + +#ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Read point (rev): @Address: %p ," + "%d bytes from loc %d & %d with operand size = %d\n", + dst.addr, dst.len, offset, offset+1, size); + block_t dbg; + dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); + dbg.len = size; + dbg.flags = BLOCK_S_INCR_ADDR; + CRYPTOLIB_PRINT_BLK(dbg); + dbg.addr = BA414EP_ADDR_MEMLOC(offset + 1, size); + CRYPTOLIB_PRINT_BLK(dbg); +#endif + CRYPTOLIB_ASSERT((dst.len >= size*2), "destination length smaller then point size."); + + write_desc( + &desc_from[0], + BA414EP_ADDR_MEMLOC(offset, size), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + + write_desc( + &desc_from[1], + BA414EP_ADDR_MEMLOC(offset + 1, size), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_from[1]); + + write_desc( + &desc_to, + dst.addr, + (dst.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(dst.len) : 2 * size), //XXX the destination length can be bigger then the transfer size + dst.flags, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_to); + + cryptodma_run_sg(desc_from, &desc_to); +} + +void CryptoRAM2point(block_t dst, uint32_t size, uint32_t offset) { + struct dma_sg_descr_s desc_from[2]; + struct dma_sg_descr_s desc_to; + +#ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Read point: " + "%d bytes from loc %d & %d with operand size = %d\n", + dst.len, offset, offset+1, size); + block_t dbg; + dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); + dbg.len = size; + dbg.flags = BLOCK_S_INCR_ADDR; + CRYPTOLIB_PRINT_BLK(dbg); + dbg.addr = BA414EP_ADDR_MEMLOC(offset + 1, size); + CRYPTOLIB_PRINT_BLK(dbg); +#endif + CRYPTOLIB_ASSERT((dst.len >= size*2), "destination length smaller then point size."); + + write_desc( + &desc_from[0], + BA414EP_ADDR_MEMLOC(offset - 1, 0), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + + write_desc( + &desc_from[1], + BA414EP_ADDR_MEMLOC(offset, 0), + size, + BLOCK_S_INCR_ADDR, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_from[1]); + + write_desc( + &desc_to, + dst.addr, + (dst.flags & DMA_AXI_DESCR_CONST_ADDR ? roundup_32(dst.len) : 2 * size), //XXX the destination length can be bigger then the transfer size + dst.flags, + DMA_SG_ENGINESELECT_BYPASS); + set_last_desc(&desc_to); + + cryptodma_run_sg(desc_from, &desc_to); +} + + +void CryptoRAM2mem_rev(block_t dst, uint32_t size, uint32_t offset) +{ + block_t src; + + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Read mem (rev): @Address: %p, %d bytes " + "from loc %d:\n", dst.addr, size, offset); + block_t dbg; + dbg.addr = BA414EP_ADDR_MEMLOC(offset, size); + dbg.len = size; + dbg.flags = BLOCK_S_INCR_ADDR; + CRYPTOLIB_PRINT_BLK(dbg); + #endif + + src.addr = BA414EP_ADDR_MEMLOC(offset, size); + src.len = size; + src.flags = BLOCK_S_INCR_ADDR; + memcpy_blk(dst, src, size); +} + +void mem2CryptoRAM(block_t src, uint32_t size, uint32_t offset) +{ + block_t dst; + + dst.addr = BA414EP_ADDR_MEMLOC(offset - 1, 0); + dst.len = size; + dst.flags = BLOCK_S_INCR_ADDR; + memcpy_blk(dst, src, size); + + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Write %d bytes to loc %d:\n", size, offset); + CRYPTOLIB_PRINT_BLK(dst); + #endif +} + +void CryptoRAM2mem(block_t dst, uint32_t size, uint32_t offset) +{ + block_t src; + + src.addr = BA414EP_ADDR_MEMLOC(offset - 1, 0); + src.len = size; + src.flags = BLOCK_S_INCR_ADDR; + memcpy_blk(dst, src, size); + + #ifdef PK_DEBUG_ENABLED + CRYPTOLIB_PRINTF("Debug BA414EP: Read %d bytes from loc %d:\n", size, offset); + CRYPTOLIB_PRINT_BLK(src); + #endif +} + + +uint32_t ba414ep_start_wait_status(void) +{ + uint32_t status; + ba414ep_start(); + status = ba414ep_wait_status(); +#ifdef PK_DEBUG_ENABLED + if(status) { +#else + if (status&~(BA414EP_STS_BADSIGNATURE_MASK|BA414EP_STS_NOTPRIME_MASK|BA414EP_STS_NOTINVERTIBLE_MASK)) { +#endif + CRYPTOLIB_PRINTF("BA414EP: error status: %08X\n", status); + } + return status; +} + + +void ba414ep_load_curve( + block_t curve, + uint32_t size, + uint32_t byte_swap, + uint32_t gen) +{ + uint32_t i; + + block_t param; + param.addr = curve.addr; + param.len = size; + param.flags = curve.flags; + + /* Load ECC parameters */ + for (i=0; i * size < curve.len; i++) { + if (gen || (i != 2 && i != 3)) { + if (byte_swap) + mem2CryptoRAM_rev(param, size, i); + else + mem2CryptoRAM(param, size, i); + } + + if (!(param.flags & BLOCK_S_CONST_ADDR)) + param.addr += param.len; + } +} + + + +uint32_t ba414ep_load_and_modN(uint8_t outloc, uint8_t nloc, uint32_t size, block_t in, block_t out, uint32_t flags) +{ + uint32_t result = ba414ep_set_command(BA414EP_OPTYPE_MOD_RED_ODD, size, BA414EP_BIGEND, flags); + if (result) + return result; + + ba414ep_set_config(outloc, outloc, outloc, nloc); + mem2CryptoRAM_rev(in, size, outloc); + if(ba414ep_start_wait_status()) + return CRYPTOLIB_CRYPTO_ERR; + + CryptoRAM2mem_rev(out, size, outloc); + + return CRYPTOLIB_SUCCESS; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.h index 12a6bd5..13bf093 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.h @@ -1,540 +1,540 @@ -/** - * @file - * @brief This file provides an interface to the BA414EP module - * - * A generic high level PK operation will require to: - * - Select the operation to issue, with a chosen size of element, endianness - * thanks to ::ba414ep_set_command - * - If allowed, select the memory locations thanks to ::ba414ep_set_config - * - If required (by ECC), load curve parameter thanks to ::ba414ep_load_curve - * - Move required inputs in the PK memory thanks to ::mem2CryptoRAM family - * - Start the PK computation with ::ba414ep_start_wait_status() - * - Read back the computed value if expected thanks to ::CryptoRAM2mem - * - * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved - */ - - -#ifndef BA414EP_CONFIG_H -#define BA414EP_CONFIG_H - -#include -#include -#include "compiler_extentions.h" -#include "cryptolib_def.h" -#include "cryptolib_types.h" -#include "sx_errors.h" -#if PK_CM_ENABLED -#include "sx_rng.h" -#endif - - -/** @struct BA414EPRegs_t - * @brief This structure represents the accessible registers of a BA414EP entity. - * See BA414EP's datasheet for details. - */ -typedef struct BA414EPRegs_t -{ - volatile uint32_t PointerReg; /* BASE_ADDR + 0x0000 */ - volatile uint32_t CommandReg; /* BASE_ADDR + 0x0004 */ - volatile uint32_t ControlReg; /* BASE_ADDR + 0x0008 */ - volatile uint32_t StatusReg; /* BASE_ADDR + 0x000C */ - volatile uint32_t VersionReg; /* BASE_ADDR + 0x0010 */ - volatile uint32_t TimerReg; /* BASE_ADDR + 0x0014 */ - volatile uint32_t HwConfigReg; /* BASE_ADDR + 0x0018 */ -} BA414EPRegs_t; - -/** - * The following addresses are derived from the PK engine data sheet, - * the micro code memory overview. - */ - -/** - * ucode content: memory size (4096) - redundancy value size (2) - */ -#define BA414EP_UCODE_MAX_LENGTH 4094 - -/** - * Memory address where the microcode size is stored (16 bits). - */ -#define BA414EP_UCODE_SIZE_ADDR ((ADDR_BA414EP_UCODE) + 2 * 128) - -/** - * Memory address where the available microcode feature bitmap is stored (64 bits). - */ -#define BA414EP_UCODE_AVAILABLE_FEATURES_ADDR ((ADDR_BA414EP_UCODE) + 2 * 128 + 4) -#define BA414EP_MAX_FEAT_ID 63 - -#define BA414EP_UCODE_DIGEST_SIZE 4 - - -struct cryptolib_status forward_error_to_cryptosoc(uint16_t ba414ep_error); - -/** - * @brief This function configures the BA414EP memory locations to use in the - * primitives arithmetic operations - * @param PtrA is the memory location of operand A - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - * @param PtrB is the memory location of operand B - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - * @param PtrC is the memory location of operand C - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - * @param PtrN is the memory location of operand N - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - */ -void ba414ep_set_config(uint32_t PtrA, uint32_t PtrB, uint32_t PtrC, uint32_t PtrN); - -/** - * @brief This function configure the BA414EP to issue one PK operation. - * - * @param op The PK operation to issue. Should be one of \c BA414EP_OPTYPE_* family - * @param operandsize the operands size in bytes (up to 2^10 bytes) - * @param swap swap the bytes on AHB/AXI4 interface (endianness conversion). - * Should be ::BA414EP_BIGEND or ::BA414EP_LITTLEEND - * @param curve_flags enable accelerator for specific curve modulus - * @return CRYPTOLIB_UNSUPPORTED_ERR if the operand size encoding exceeds the allocated bits in the - * command register; CRYPTOLIB_SUCCESS otherwise. - */ -uint32_t ba414ep_set_command(uint32_t op, uint32_t operandsize, uint32_t swap, uint32_t curve_flags) CHECK_RESULT; - -/** - * @brief Transfer data from memory to the end of a CryptoRAM location. - * Should be used when big-endianness is considered. - * Data from src are padded from src.len to size with zeros. - * @param src is a data block of the source that has to be copied (byte-addressing) - * @param size is the size of the data to copy expressed in bytes - * @param offset is the offset of the memory location that has to be copied - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - */ -void mem2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset); - -/** - * @brief Transfer data from the end of a CryptoRAM location to memory. - * Should be used when big-endianness is considered. - * @param dst is a block_t where the source has to be copied to (byte-addressing) - * @param size is the size of the data to copy expressed in bytes - * @param offset is the offset of the memory location that has to be copied - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - */ -void CryptoRAM2mem_rev(block_t dst, uint32_t size, uint32_t offset); - -/** - * @brief Transfer data from memory to CryptoRAM starting at the beginning of - * the CryptoRAM location. Should be used when little endianness is - * considered. - * @param src is a data block of the source that has to be copied (byte-addressing) - * @param size is a the size of the data to copy expressed in bytes - * @param offset is the offset of the memory location that has to be copied - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - */ -void mem2CryptoRAM(block_t src, uint32_t size, uint32_t offset); - -/** - * @brief Function transferring data from CryptoRAM to memory starting from the - * beginning of the CryptoRAM location. Should be used when little endianness is - * considered. - * @param dst is a block_t where the source has to be copied to (byte-addressing) - * @param size is the size of the data to copy expressed in bytes - * @param offset is the offset of the memory location that has to be copied - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) - */ -void CryptoRAM2mem(block_t dst, uint32_t size, uint32_t offset); - -/** - * @brief Function is used to start the PK, wait for completion, - * read and return the status register value - * @return the contents of the status register as uint32_t. - */ -uint32_t ba414ep_start_wait_status(void) CHECK_RESULT; - -/** - * Copy the BA414EP ECC curve parameters to CryptoRAM - * @param curve ecc curve to copy to the cryptoRAM (See ::sx_ecc_curve_t.params) - * @param size Size of an element of the curve expressed in bytes - * @param byte_swap 1 if byte_swap enabled in BA414EP (for AHB/AXI4 endianness), 0 otherwise - * @param gen 1 if we want to load the generator from the curve parameters - */ -void ba414ep_load_curve(block_t curve, uint32_t size, uint32_t byte_swap, uint32_t gen); - - -/** - * @brief Compute \p out = \p in mod N. - * - * The modulo will be copied back in \p out but also let in \p outloc memory location - * for further PK operations. - * - * \warning N must be already loaded in \p nloc - * @param outloc memory location to place \p out - * @param nloc memory location for modulo N - * @param size size of \p in expressed in bytes - * @param in input value - * @param out block_t containing the computed modulo - * @param curve_flags enable accelerator for specific curve modulus - @return CRYPTOLIB_SUCCESS if successful - */ -uint32_t ba414ep_load_and_modN( - uint8_t outloc, - uint8_t nloc, - uint32_t size, - block_t in, - block_t out, - uint32_t curve_flags) CHECK_RESULT; - -#if PK_CM_ENABLED -/** - * Set the random number generator to be used for the PK countermeasures. - * @param rng a structure containing a pointer to a function to generate - the mandatory random for the countermeasures. - */ -void ba414ep_set_rng(struct sx_rng rng); -#endif - -/** - * Copy an ECC point (X and Y coordinates) to CryptoRAM at two consecutive - * locations. The last \p size bytes from each of the two CryptoRAM locations - * will be written. Should be used when big-endianness is considered. - * - * @param src point on the curve: X coordinate followed by Y coordinate, - * each having \p size bytes - * @param size size of the operand/coordinate in bytes - * @param offset position of the first coordinate in cryptoRAM where the - * X coordinate will be copied; the Y coordinate will be - * written at location offset + 1 - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) - */ -void point2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset); - -/** - * Copy ECC point (X and Y coordinates) from two consecutive locations in the - * CryptoRAM. The last \p size bytes from each of the two memory locations will - * be transferred. Should be used when big-endianness is considered. - * - * @param dst location where the X coordinate followed by the Y coordinate will - * be stored - * @param size size of the operand/coordinate in bytes - * @param offset position of the first coordinate in cryptoRAM where the X - * coordinate is stored; the Y coordinate will be copied from - * the location offset + 1 - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) - */ -void CryptoRAM2point_rev(block_t dst, uint32_t size, uint32_t offset); - -/** - * Copy an ECC point (X and Y coordinates) to two consecutive CryptoRAM - * locations. The first \p size bytes of each location will be written. Should - * be used when little-endianness is considered. - * - * @param src point on the curve: X coordinate followed by Y coordinate, - * each having \p size bytes - * @param size size of the operand/coordinate in bytes - * @param offset position of the first coordinate in cryptoRAM where the - * X coordinate will be copied; the Y coordinate will be - * written at location offset + 1 - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) - */ -void point2CryptoRAM(block_t src, uint32_t size, uint32_t offset); - -/** - * Copy ECC point (X and Y coordinates) from two consecutive locations in the - * CryptoRAM. The first \p size bytes of the two memory locations will be - * transferred. Should be used when little-endianness is considered. - * - * @param dst location where the X coordinate followed by the Y coordinate will - * be stored - * @param size size of the operand/coordinate in bytes - * @param offset position of the first coordinate in cryptoRAM where the X - * coordinate is stored; the Y coordinate will be copied from - * the location offset + 1 - * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) - */ -void CryptoRAM2point(block_t dst, uint32_t size, uint32_t offset); - - -/* For register CFG */ -#define BA414EP_PTR_OPPTRN_LSB (24) -#define BA414EP_PTR_OPPTRN_MASK (0x0F000000) -#define BA414EP_PTR_OPPTRC_LSB (16) -#define BA414EP_PTR_OPPTRC_MASK (0x000F0000) -#define BA414EP_PTR_OPPTRB_LSB (8) -#define BA414EP_PTR_OPPTRB_MASK (0x00000F00) -#define BA414EP_PTR_OPPTRA_LSB (0) -#define BA414EP_PTR_OPPTRA_MASK (0x0000000F) - -/* For register CMD */ -#define BA414EP_CMD_CALCR2_LSB (31) -#define BA414EP_CMD_FLAGB_LSB (30) -#define BA414EP_CMD_FLAGA_LSB (29) -#define BA414EP_CMD_SWAP_LSB (28) -#define BA414EP_CMD_EDWARDS_LSB (26) -#define BA414EP_CMD_RANDPR_LSB (25) -#define BA414EP_CMD_RANDKE_LSB (24) -#define BA414EP_CMD_SELCUR_LSB (20) -#define BA414EP_CMD_RANDMOD_LSB (19) -#define BA414EP_CMD_OPSIZE_LSB (8) -#define BA414EP_CMD_OPFLD_LSB (7) -#define BA414EP_CMD_OPTYPE_LSB (0) -#define BA414EP_CMD_CALCR2_MASK (0x80000000) -#define BA414EP_CMD_FLAGB_MASK (0x40000000) -#define BA414EP_CMD_FLAGA_MASK (0x20000000) -#define BA414EP_CMD_SWAP_MASK (0x10000000) -#define BA414EP_CMD_EDWARDS_MASK (0x04000000) -#define BA414EP_CMD_RANDPR_MASK (0x02000000) -#define BA414EP_CMD_RANDKE_MASK (0x01000000) -#define BA414EP_CMD_SELCUR_MASK (0x00F00000) -#define BA414EP_CMD_RANDMOD_MASK (0x00080000) -#define BA414EP_CMD_OPSIZE_MASK (0x0003FF00) -#define BA414EP_CMD_OPFLD_MASK (0x00000080) -#define BA414EP_CMD_OPTYPE_MASK (0x0000007F) - -#define BA414EP_CMD_CALCR2(v) (((v) << BA414EP_CMD_CALCR2_LSB)& BA414EP_CMD_CALCR2_MASK) -#define BA414EP_CMD_FLAGB(v) (((v) << BA414EP_CMD_FLAGB_LSB)& BA414EP_CMD_FLAGB_MASK) -#define BA414EP_CMD_FLAGA(v) (((v) << BA414EP_CMD_FLAGA_LSB)& BA414EP_CMD_FLAGA_MASK) -#define BA414EP_CMD_SWAP(v) (((v) << BA414EP_CMD_SWAP_LSB)& BA414EP_CMD_SWAP_MASK) -#define BA414EP_CMD_EDWARDS(v) (((v) << BA414EP_CMD_EDWARDS_LSB)&BA414EP_CMD_EDWARDS_MASK) -#define BA414EP_CMD_RANDPR(v) (((v) << BA414EP_CMD_RANDPR_LSB)& BA414EP_CMD_RANDPR_MASK) -#define BA414EP_CMD_RANDKE(v) (((v) << BA414EP_CMD_RANDKE_LSB)& BA414EP_CMD_RANDKE_MASK) -#define BA414EP_CMD_RANDMOD(v) (((v) << BA414EP_CMD_RANDMOD_LSB)&BA414EP_CMD_RANDMOD_MASK) -#define BA414EP_CMD_OPSIZE(v) (((v) << BA414EP_CMD_OPSIZE_LSB)& BA414EP_CMD_OPSIZE_MASK) -#define BA414EP_CMD_OPFLD(v) (((v) << BA414EP_CMD_OPFLD_LSB)& BA414EP_CMD_OPFLD_MASK) -#define BA414EP_CMD_OPTYPE(v) (((v) << BA414EP_CMD_OPTYPE_LSB)& BA414EP_CMD_OPTYPE_MASK) - - -/* For operation type */ -/*--- Primitive arithmetic operations GF(p) and GF(2^m) ---*/ -/** @brief BA414EP operation type: modular addition */ -#define BA414EP_OPTYPE_MOD_ADD (0x01) /**< A+B mod N */ -/** @brief BA414EP operation type: modular subtraction */ -#define BA414EP_OPTYPE_MOD_SUB (0x02) /**< A-B mod N */ -/** @brief BA414EP operation type: modular multiplication (odd N) */ -#define BA414EP_OPTYPE_MOD_MULT_ODD (0x03) /**< A*B mod N */ -/** @brief BA414EP operation type: modular reduction (odd N) */ -#define BA414EP_OPTYPE_MOD_RED_ODD (0x04) /**< B mod N */ -/** @brief BA414EP operation type: modular division (odd N) */ -#define BA414EP_OPTYPE_MOD_DIV_ODD (0x05) /**< A/B mod N */ -/** @brief BA414EP operation type: modular inversion (odd N) */ -#define BA414EP_OPTYPE_MOD_INV_ODD (0x06) /**< 1/B mod N */ -/** @brief BA414EP operation type: multiplication */ -#define BA414EP_OPTYPE_MULT (0x08) /**< A*B */ -/** @brief BA414EP operation type: modular inversion (even N and GF(p) only) */ -#define BA414EP_OPTYPE_MOD_INV_EVEN (0x09) /**< 1/B mod N */ -/** @brief BA414EP operation type: modular reduction (even N and GF(p) only) */ -#define BA414EP_OPTYPE_MOD_RED_EVEN (0x0A) /**< B mod N */ -/** @brief BA414EP operation type: clear data memory */ -#define BA414EP_OPTYPE_CLEAR_MEM (0x0F) - -/*--- High-level RSA, CRT & DSA Operations - GF(p) only ---*/ -/** @brief BA414EP operation type: modular exponentiation */ -#define BA414EP_OPTYPE_MOD_EXP (0x10) -/** @brief BA414EP operation type: RSA priv key generation */ -#define BA414EP_OPTYPE_RSA_PK_GEN (0x11) -/** @brief BA414EP operation type: RSA CRT key parameter generation */ -#define BA414EP_OPTYPE_RSA_CRT_GEN (0x12) -/** @brief BA414EP operation type: RSA CRT decryption */ -#define BA414EP_OPTYPE_RSA_CRT_DEC (0x13) -/** @brief BA414EP operation type: RSA encryption */ -#define BA414EP_OPTYPE_RSA_ENC (0x14) -/** @brief BA414EP operation type: RSA decryption */ -#define BA414EP_OPTYPE_RSA_DEC (0x15) -/** @brief BA414EP operation type: RSA signature generation */ -#define BA414EP_OPTYPE_RSA_SIGN_GEN (0x16) -/** @brief BA414EP operation type: RSA signature verification */ -#define BA414EP_OPTYPE_RSA_SIGN_VERIF (0x17) -/** @brief BA414EP operation type: DSA key generation */ -#define BA414EP_OPTYPE_DSA_KEY_GEN (0x18) -/** @brief BA414EP operation type: DSA signature generation */ -#define BA414EP_OPTYPE_DSA_SIGN_GEN (0x19) -/** @brief BA414EP operation type: DSA signature verification */ -#define BA414EP_OPTYPE_DSA_SIGN_VERIF (0x1A) -/** @brief BA414EP operation type: SRP server session key */ -#define BA414EP_OPTYPE_SRP_SERVER_KEY (0x1B) -/** @brief BA414EP operation type: SRP client session key */ -#define BA414EP_OPTYPE_SRP_CLIENT_KEY (0x1C) -/** @brief BA414EP operation type: RSA half CRT recombination */ -#define BA414EP_OPTYPE_RSA_HALFCRT_RECOMBI (0x1D) -/** @brief BA414EP operation type: SRP server pub key */ -#define BA414EP_OPTYPE_SRP_SERVER_PK (0x1E) -/** @brief BA414EP operation type: RSA half CRT decryption */ -#define BA414EP_OPTYPE_RSA_HALFCRT_DEC (0x1F) - -/*--- Primitive ECC & Check Point Operations GF(p) & GF(2m) ---*/ -/** @brief BA414EP operation type: ECC point doubling */ -#define BA414EP_OPTYPE_ECC_POINT_DOUBLE (0x20) -/** @brief BA414EP operation type: ECC point addition */ -#define BA414EP_OPTYPE_ECC_POINT_ADD (0x21) -/** @brief BA414EP operation type: ECC point multiplication */ -#define BA414EP_OPTYPE_ECC_POINT_MULT (0x22) -/** @brief BA414EP operation type: ECC check a & b */ -#define BA414EP_OPTYPE_ECC_CHECK_AB (0x23) -/** @brief BA414EP operation type: ECC check n!=q */ -#define BA414EP_OPTYPE_ECC_CHECK_NNOTQ (0x24) -/** @brief BA414EP operation type: ECC check x +#include +#include "compiler_extentions.h" +#include "cryptolib_def.h" +#include "cryptolib_types.h" +#include "sx_errors.h" +#if PK_CM_ENABLED +#include "sx_rng.h" +#endif + + +/** @struct BA414EPRegs_t + * @brief This structure represents the accessible registers of a BA414EP entity. + * See BA414EP's datasheet for details. + */ +typedef struct BA414EPRegs_t +{ + volatile uint32_t PointerReg; /* BASE_ADDR + 0x0000 */ + volatile uint32_t CommandReg; /* BASE_ADDR + 0x0004 */ + volatile uint32_t ControlReg; /* BASE_ADDR + 0x0008 */ + volatile uint32_t StatusReg; /* BASE_ADDR + 0x000C */ + volatile uint32_t VersionReg; /* BASE_ADDR + 0x0010 */ + volatile uint32_t TimerReg; /* BASE_ADDR + 0x0014 */ + volatile uint32_t HwConfigReg; /* BASE_ADDR + 0x0018 */ +} BA414EPRegs_t; + +/** + * The following addresses are derived from the PK engine data sheet, + * the micro code memory overview. + */ + +/** + * ucode content: memory size (4096) - redundancy value size (2) + */ +#define BA414EP_UCODE_MAX_LENGTH 4094 + +/** + * Memory address where the microcode size is stored (16 bits). + */ +#define BA414EP_UCODE_SIZE_ADDR ((ADDR_BA414EP_UCODE) + 2 * 128) + +/** + * Memory address where the available microcode feature bitmap is stored (64 bits). + */ +#define BA414EP_UCODE_AVAILABLE_FEATURES_ADDR ((ADDR_BA414EP_UCODE) + 2 * 128 + 4) +#define BA414EP_MAX_FEAT_ID 63 + +#define BA414EP_UCODE_DIGEST_SIZE 4 + + +struct cryptolib_status forward_error_to_cryptosoc(uint16_t ba414ep_error); + +/** + * @brief This function configures the BA414EP memory locations to use in the + * primitives arithmetic operations + * @param PtrA is the memory location of operand A + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + * @param PtrB is the memory location of operand B + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + * @param PtrC is the memory location of operand C + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + * @param PtrN is the memory location of operand N + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + */ +void ba414ep_set_config(uint32_t PtrA, uint32_t PtrB, uint32_t PtrC, uint32_t PtrN); + +/** + * @brief This function configure the BA414EP to issue one PK operation. + * + * @param op The PK operation to issue. Should be one of \c BA414EP_OPTYPE_* family + * @param operandsize the operands size in bytes (up to 2^10 bytes) + * @param swap swap the bytes on AHB/AXI4 interface (endianness conversion). + * Should be ::BA414EP_BIGEND or ::BA414EP_LITTLEEND + * @param curve_flags enable accelerator for specific curve modulus + * @return CRYPTOLIB_UNSUPPORTED_ERR if the operand size encoding exceeds the allocated bits in the + * command register; CRYPTOLIB_SUCCESS otherwise. + */ +uint32_t ba414ep_set_command(uint32_t op, uint32_t operandsize, uint32_t swap, uint32_t curve_flags) CHECK_RESULT; + +/** + * @brief Transfer data from memory to the end of a CryptoRAM location. + * Should be used when big-endianness is considered. + * Data from src are padded from src.len to size with zeros. + * @param src is a data block of the source that has to be copied (byte-addressing) + * @param size is the size of the data to copy expressed in bytes + * @param offset is the offset of the memory location that has to be copied + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + */ +void mem2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset); + +/** + * @brief Transfer data from the end of a CryptoRAM location to memory. + * Should be used when big-endianness is considered. + * @param dst is a block_t where the source has to be copied to (byte-addressing) + * @param size is the size of the data to copy expressed in bytes + * @param offset is the offset of the memory location that has to be copied + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + */ +void CryptoRAM2mem_rev(block_t dst, uint32_t size, uint32_t offset); + +/** + * @brief Transfer data from memory to CryptoRAM starting at the beginning of + * the CryptoRAM location. Should be used when little endianness is + * considered. + * @param src is a data block of the source that has to be copied (byte-addressing) + * @param size is a the size of the data to copy expressed in bytes + * @param offset is the offset of the memory location that has to be copied + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + */ +void mem2CryptoRAM(block_t src, uint32_t size, uint32_t offset); + +/** + * @brief Function transferring data from CryptoRAM to memory starting from the + * beginning of the CryptoRAM location. Should be used when little endianness is + * considered. + * @param dst is a block_t where the source has to be copied to (byte-addressing) + * @param size is the size of the data to copy expressed in bytes + * @param offset is the offset of the memory location that has to be copied + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_15) + */ +void CryptoRAM2mem(block_t dst, uint32_t size, uint32_t offset); + +/** + * @brief Function is used to start the PK, wait for completion, + * read and return the status register value + * @return the contents of the status register as uint32_t. + */ +uint32_t ba414ep_start_wait_status(void) CHECK_RESULT; + +/** + * Copy the BA414EP ECC curve parameters to CryptoRAM + * @param curve ecc curve to copy to the cryptoRAM (See ::sx_ecc_curve_t.params) + * @param size Size of an element of the curve expressed in bytes + * @param byte_swap 1 if byte_swap enabled in BA414EP (for AHB/AXI4 endianness), 0 otherwise + * @param gen 1 if we want to load the generator from the curve parameters + */ +void ba414ep_load_curve(block_t curve, uint32_t size, uint32_t byte_swap, uint32_t gen); + + +/** + * @brief Compute \p out = \p in mod N. + * + * The modulo will be copied back in \p out but also let in \p outloc memory location + * for further PK operations. + * + * \warning N must be already loaded in \p nloc + * @param outloc memory location to place \p out + * @param nloc memory location for modulo N + * @param size size of \p in expressed in bytes + * @param in input value + * @param out block_t containing the computed modulo + * @param curve_flags enable accelerator for specific curve modulus + @return CRYPTOLIB_SUCCESS if successful + */ +uint32_t ba414ep_load_and_modN( + uint8_t outloc, + uint8_t nloc, + uint32_t size, + block_t in, + block_t out, + uint32_t curve_flags) CHECK_RESULT; + +#if PK_CM_ENABLED +/** + * Set the random number generator to be used for the PK countermeasures. + * @param rng a structure containing a pointer to a function to generate + the mandatory random for the countermeasures. + */ +void ba414ep_set_rng(struct sx_rng rng); +#endif + +/** + * Copy an ECC point (X and Y coordinates) to CryptoRAM at two consecutive + * locations. The last \p size bytes from each of the two CryptoRAM locations + * will be written. Should be used when big-endianness is considered. + * + * @param src point on the curve: X coordinate followed by Y coordinate, + * each having \p size bytes + * @param size size of the operand/coordinate in bytes + * @param offset position of the first coordinate in cryptoRAM where the + * X coordinate will be copied; the Y coordinate will be + * written at location offset + 1 + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) + */ +void point2CryptoRAM_rev(block_t src, uint32_t size, uint32_t offset); + +/** + * Copy ECC point (X and Y coordinates) from two consecutive locations in the + * CryptoRAM. The last \p size bytes from each of the two memory locations will + * be transferred. Should be used when big-endianness is considered. + * + * @param dst location where the X coordinate followed by the Y coordinate will + * be stored + * @param size size of the operand/coordinate in bytes + * @param offset position of the first coordinate in cryptoRAM where the X + * coordinate is stored; the Y coordinate will be copied from + * the location offset + 1 + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) + */ +void CryptoRAM2point_rev(block_t dst, uint32_t size, uint32_t offset); + +/** + * Copy an ECC point (X and Y coordinates) to two consecutive CryptoRAM + * locations. The first \p size bytes of each location will be written. Should + * be used when little-endianness is considered. + * + * @param src point on the curve: X coordinate followed by Y coordinate, + * each having \p size bytes + * @param size size of the operand/coordinate in bytes + * @param offset position of the first coordinate in cryptoRAM where the + * X coordinate will be copied; the Y coordinate will be + * written at location offset + 1 + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) + */ +void point2CryptoRAM(block_t src, uint32_t size, uint32_t offset); + +/** + * Copy ECC point (X and Y coordinates) from two consecutive locations in the + * CryptoRAM. The first \p size bytes of the two memory locations will be + * transferred. Should be used when little-endianness is considered. + * + * @param dst location where the X coordinate followed by the Y coordinate will + * be stored + * @param size size of the operand/coordinate in bytes + * @param offset position of the first coordinate in cryptoRAM where the X + * coordinate is stored; the Y coordinate will be copied from + * the location offset + 1 + * (from ::BA414EP_MEMLOC_0 to ::BA414EP_MEMLOC_14) + */ +void CryptoRAM2point(block_t dst, uint32_t size, uint32_t offset); + + +/* For register CFG */ +#define BA414EP_PTR_OPPTRN_LSB (24) +#define BA414EP_PTR_OPPTRN_MASK (0x0F000000) +#define BA414EP_PTR_OPPTRC_LSB (16) +#define BA414EP_PTR_OPPTRC_MASK (0x000F0000) +#define BA414EP_PTR_OPPTRB_LSB (8) +#define BA414EP_PTR_OPPTRB_MASK (0x00000F00) +#define BA414EP_PTR_OPPTRA_LSB (0) +#define BA414EP_PTR_OPPTRA_MASK (0x0000000F) + +/* For register CMD */ +#define BA414EP_CMD_CALCR2_LSB (31) +#define BA414EP_CMD_FLAGB_LSB (30) +#define BA414EP_CMD_FLAGA_LSB (29) +#define BA414EP_CMD_SWAP_LSB (28) +#define BA414EP_CMD_EDWARDS_LSB (26) +#define BA414EP_CMD_RANDPR_LSB (25) +#define BA414EP_CMD_RANDKE_LSB (24) +#define BA414EP_CMD_SELCUR_LSB (20) +#define BA414EP_CMD_RANDMOD_LSB (19) +#define BA414EP_CMD_OPSIZE_LSB (8) +#define BA414EP_CMD_OPFLD_LSB (7) +#define BA414EP_CMD_OPTYPE_LSB (0) +#define BA414EP_CMD_CALCR2_MASK (0x80000000) +#define BA414EP_CMD_FLAGB_MASK (0x40000000) +#define BA414EP_CMD_FLAGA_MASK (0x20000000) +#define BA414EP_CMD_SWAP_MASK (0x10000000) +#define BA414EP_CMD_EDWARDS_MASK (0x04000000) +#define BA414EP_CMD_RANDPR_MASK (0x02000000) +#define BA414EP_CMD_RANDKE_MASK (0x01000000) +#define BA414EP_CMD_SELCUR_MASK (0x00F00000) +#define BA414EP_CMD_RANDMOD_MASK (0x00080000) +#define BA414EP_CMD_OPSIZE_MASK (0x0003FF00) +#define BA414EP_CMD_OPFLD_MASK (0x00000080) +#define BA414EP_CMD_OPTYPE_MASK (0x0000007F) + +#define BA414EP_CMD_CALCR2(v) (((v) << BA414EP_CMD_CALCR2_LSB)& BA414EP_CMD_CALCR2_MASK) +#define BA414EP_CMD_FLAGB(v) (((v) << BA414EP_CMD_FLAGB_LSB)& BA414EP_CMD_FLAGB_MASK) +#define BA414EP_CMD_FLAGA(v) (((v) << BA414EP_CMD_FLAGA_LSB)& BA414EP_CMD_FLAGA_MASK) +#define BA414EP_CMD_SWAP(v) (((v) << BA414EP_CMD_SWAP_LSB)& BA414EP_CMD_SWAP_MASK) +#define BA414EP_CMD_EDWARDS(v) (((v) << BA414EP_CMD_EDWARDS_LSB)&BA414EP_CMD_EDWARDS_MASK) +#define BA414EP_CMD_RANDPR(v) (((v) << BA414EP_CMD_RANDPR_LSB)& BA414EP_CMD_RANDPR_MASK) +#define BA414EP_CMD_RANDKE(v) (((v) << BA414EP_CMD_RANDKE_LSB)& BA414EP_CMD_RANDKE_MASK) +#define BA414EP_CMD_RANDMOD(v) (((v) << BA414EP_CMD_RANDMOD_LSB)&BA414EP_CMD_RANDMOD_MASK) +#define BA414EP_CMD_OPSIZE(v) (((v) << BA414EP_CMD_OPSIZE_LSB)& BA414EP_CMD_OPSIZE_MASK) +#define BA414EP_CMD_OPFLD(v) (((v) << BA414EP_CMD_OPFLD_LSB)& BA414EP_CMD_OPFLD_MASK) +#define BA414EP_CMD_OPTYPE(v) (((v) << BA414EP_CMD_OPTYPE_LSB)& BA414EP_CMD_OPTYPE_MASK) + + +/* For operation type */ +/*--- Primitive arithmetic operations GF(p) and GF(2^m) ---*/ +/** @brief BA414EP operation type: modular addition */ +#define BA414EP_OPTYPE_MOD_ADD (0x01) /**< A+B mod N */ +/** @brief BA414EP operation type: modular subtraction */ +#define BA414EP_OPTYPE_MOD_SUB (0x02) /**< A-B mod N */ +/** @brief BA414EP operation type: modular multiplication (odd N) */ +#define BA414EP_OPTYPE_MOD_MULT_ODD (0x03) /**< A*B mod N */ +/** @brief BA414EP operation type: modular reduction (odd N) */ +#define BA414EP_OPTYPE_MOD_RED_ODD (0x04) /**< B mod N */ +/** @brief BA414EP operation type: modular division (odd N) */ +#define BA414EP_OPTYPE_MOD_DIV_ODD (0x05) /**< A/B mod N */ +/** @brief BA414EP operation type: modular inversion (odd N) */ +#define BA414EP_OPTYPE_MOD_INV_ODD (0x06) /**< 1/B mod N */ +/** @brief BA414EP operation type: multiplication */ +#define BA414EP_OPTYPE_MULT (0x08) /**< A*B */ +/** @brief BA414EP operation type: modular inversion (even N and GF(p) only) */ +#define BA414EP_OPTYPE_MOD_INV_EVEN (0x09) /**< 1/B mod N */ +/** @brief BA414EP operation type: modular reduction (even N and GF(p) only) */ +#define BA414EP_OPTYPE_MOD_RED_EVEN (0x0A) /**< B mod N */ +/** @brief BA414EP operation type: clear data memory */ +#define BA414EP_OPTYPE_CLEAR_MEM (0x0F) + +/*--- High-level RSA, CRT & DSA Operations - GF(p) only ---*/ +/** @brief BA414EP operation type: modular exponentiation */ +#define BA414EP_OPTYPE_MOD_EXP (0x10) +/** @brief BA414EP operation type: RSA priv key generation */ +#define BA414EP_OPTYPE_RSA_PK_GEN (0x11) +/** @brief BA414EP operation type: RSA CRT key parameter generation */ +#define BA414EP_OPTYPE_RSA_CRT_GEN (0x12) +/** @brief BA414EP operation type: RSA CRT decryption */ +#define BA414EP_OPTYPE_RSA_CRT_DEC (0x13) +/** @brief BA414EP operation type: RSA encryption */ +#define BA414EP_OPTYPE_RSA_ENC (0x14) +/** @brief BA414EP operation type: RSA decryption */ +#define BA414EP_OPTYPE_RSA_DEC (0x15) +/** @brief BA414EP operation type: RSA signature generation */ +#define BA414EP_OPTYPE_RSA_SIGN_GEN (0x16) +/** @brief BA414EP operation type: RSA signature verification */ +#define BA414EP_OPTYPE_RSA_SIGN_VERIF (0x17) +/** @brief BA414EP operation type: DSA key generation */ +#define BA414EP_OPTYPE_DSA_KEY_GEN (0x18) +/** @brief BA414EP operation type: DSA signature generation */ +#define BA414EP_OPTYPE_DSA_SIGN_GEN (0x19) +/** @brief BA414EP operation type: DSA signature verification */ +#define BA414EP_OPTYPE_DSA_SIGN_VERIF (0x1A) +/** @brief BA414EP operation type: SRP server session key */ +#define BA414EP_OPTYPE_SRP_SERVER_KEY (0x1B) +/** @brief BA414EP operation type: SRP client session key */ +#define BA414EP_OPTYPE_SRP_CLIENT_KEY (0x1C) +/** @brief BA414EP operation type: RSA half CRT recombination */ +#define BA414EP_OPTYPE_RSA_HALFCRT_RECOMBI (0x1D) +/** @brief BA414EP operation type: SRP server pub key */ +#define BA414EP_OPTYPE_SRP_SERVER_PK (0x1E) +/** @brief BA414EP operation type: RSA half CRT decryption */ +#define BA414EP_OPTYPE_RSA_HALFCRT_DEC (0x1F) + +/*--- Primitive ECC & Check Point Operations GF(p) & GF(2m) ---*/ +/** @brief BA414EP operation type: ECC point doubling */ +#define BA414EP_OPTYPE_ECC_POINT_DOUBLE (0x20) +/** @brief BA414EP operation type: ECC point addition */ +#define BA414EP_OPTYPE_ECC_POINT_ADD (0x21) +/** @brief BA414EP operation type: ECC point multiplication */ +#define BA414EP_OPTYPE_ECC_POINT_MULT (0x22) +/** @brief BA414EP operation type: ECC check a & b */ +#define BA414EP_OPTYPE_ECC_CHECK_AB (0x23) +/** @brief BA414EP operation type: ECC check n!=q */ +#define BA414EP_OPTYPE_ECC_CHECK_NNOTQ (0x24) +/** @brief BA414EP operation type: ECC check xFIFOLevelReg); -} - -uint32_t ba431_read_status(void) -{ - return RD_REG32(&BA431_REGS->StatusReg); -} - -uint32_t ba431_read_controlreg(void) -{ - return RD_REG32(&BA431_REGS->ControlReg); -} - -void ba431_write_controlreg(uint32_t control) -{ - CRYPTOLIB_ASSERT_NM(!(control & 0xFFF00000)); - WR_REG32(&BA431_REGS->ControlReg, control); -} - -uint32_t ba431_read_fifo_wakeup_threshold(void) -{ - return RD_REG32(&BA431_REGS->FIFOThresholdReg); -} -void ba431_write_fifo_wakeup_threshold(uint32_t fifo_threshold) -{ - WR_REG32(&BA431_REGS->FIFOThresholdReg, fifo_threshold); -} - - -uint32_t ba431_read_switch_off_timer(void) -{ - return RD_REG32(&BA431_REGS->SwOffTmrValReg); -} - - -void ba431_write_switch_off_timer(uint32_t sw_off_timer_val) -{ - CRYPTOLIB_ASSERT_NM(!(sw_off_timer_val & 0xFFFF0000)); - WR_REG32(&BA431_REGS->SwOffTmrValReg, sw_off_timer_val); -} - - -uint32_t ba431_read_clk_div(void) -{ - return RD_REG32(&BA431_REGS->ClkDivReg); -} - -void ba431_write_clk_div(uint8_t clk_div) -{ - WR_REG32(&BA431_REGS->ClkDivReg, clk_div); -} - - -uint32_t ba431_read_init_wait(void) -{ - return RD_REG32(&BA431_REGS->InitWaitReg); -} - - -void ba431_write_init_wait(uint32_t init_wait_val) -{ - CRYPTOLIB_ASSERT_NM(!(init_wait_val & 0xFFFF0000)); - WR_REG32(&BA431_REGS->InitWaitReg, init_wait_val); -} - - -void ba431_clear_ctrl(void) -{ - WR_REG32(&BA431_REGS->ControlReg, 0); -} - - -void ba431_enable_ndrng(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_NDRNG_ENABLE); -} - - -void ba431_disable_ndrng(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_NDRNG_ENABLE); -} - - -void ba431_enable_test_mode(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_TEST_ENABLE); -} - - -void ba431_disable_test_mode(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_TEST_ENABLE); -} - - -void ba431_set_cond_test_mode(void) -{ - WR_REG32(&BA431_REGS->ControlReg, BA431_CTRL_TEST_ENABLE | BA431_CTRL_BYPASS_AIS31_TEST | BA431_CTRL_BYPASS_HEALTH_TEST); -} - - -void ba431_enable_health_test_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_REP_EN | BA431_CTRL_INT_PROP_EN); -} - - -void ba431_disable_health_test_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~(BA431_CTRL_INT_REP_EN | BA431_CTRL_INT_PROP_EN)); -} - - -void ba431_enable_fifofull_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_FIFOFULL_EN); -} - - -void ba431_disable_fifofull_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_INT_FIFOFULL_EN); -} - - -void ba431_softreset(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_SOFTRESET); - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_SOFTRESET); -} - - -void ba431_enable_AIS31_test_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_ALM_EN); -} - - -void ba431_force_run(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_FORCE_RUN); -} - - -void ba431_disable_AIS31_test_irq(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_INT_ALM_EN); -} - - -void ba431_set_nb128bitblocks(uint8_t nb128bitblocks) -{ - CRYPTOLIB_ASSERT_NM(!(nb128bitblocks & 0xF0)); - WR_REG32(&BA431_REGS->ControlReg, (ba431_read_controlreg() & ~BA431_CTRL_MASK_NB_128BIT_BLOCKS) - | (nb128bitblocks << BA431_CTRL_OFFSET_NB_128BIT_BLOCKS)); -} - - -void ba431_read_conditioning_key(uint32_t *key) -{ - key[0] = RD_REG32(&BA431_REGS->Key0Reg); - key[1] = RD_REG32(&BA431_REGS->Key1Reg); - key[2] = RD_REG32(&BA431_REGS->Key2Reg); - key[3] = RD_REG32(&BA431_REGS->Key3Reg); -} - - -void ba431_write_conditioning_key(const uint32_t * key) -{ - WR_REG32(&BA431_REGS->Key0Reg, key[0]); - WR_REG32(&BA431_REGS->Key1Reg, key[1]); - WR_REG32(&BA431_REGS->Key2Reg, key[2]); - WR_REG32(&BA431_REGS->Key3Reg, key[3]); -} - - -void ba431_write_test_data(uint32_t test_data) -{ - /*Wait for previous data to be processed*/ - while(ba431_read_status() & BA431_STAT_MASK_TESTDATA_BUSY); - /*Write data*/ - WR_REG32(&BA431_REGS->TestDataReg,test_data); -} - - -ba431_state_t ba431_get_state(void) -{ - return (ba431_state_t) (ba431_read_status() & BA431_STAT_MASK_STATE); -} - -void ba431_set_raw_mode(void) -{ - WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_COND_BYPASS | - BA431_CTRL_BYPASS_HEALTH_TEST | BA431_CTRL_BYPASS_AIS31_TEST); -} +/** + * @file + * @brief Defines BA431 Random generator registers and fields + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include "ba431_config.h" +#include "sxregs.h" +#include "cryptolib_def.h" + +uint32_t ba431_read_fifovalue(void) +{ + return RD_REG32(CRYPTOLIB_BA431_FIFO); +} + +uint32_t ba431_read_fifolevel(void) +{ + return RD_REG32(&BA431_REGS->FIFOLevelReg); +} + +uint32_t ba431_read_status(void) +{ + return RD_REG32(&BA431_REGS->StatusReg); +} + +uint32_t ba431_read_controlreg(void) +{ + return RD_REG32(&BA431_REGS->ControlReg); +} + +void ba431_write_controlreg(uint32_t control) +{ + CRYPTOLIB_ASSERT_NM(!(control & 0xFFF00000)); + WR_REG32(&BA431_REGS->ControlReg, control); +} + +uint32_t ba431_read_fifo_wakeup_threshold(void) +{ + return RD_REG32(&BA431_REGS->FIFOThresholdReg); +} +void ba431_write_fifo_wakeup_threshold(uint32_t fifo_threshold) +{ + WR_REG32(&BA431_REGS->FIFOThresholdReg, fifo_threshold); +} + + +uint32_t ba431_read_switch_off_timer(void) +{ + return RD_REG32(&BA431_REGS->SwOffTmrValReg); +} + + +void ba431_write_switch_off_timer(uint32_t sw_off_timer_val) +{ + CRYPTOLIB_ASSERT_NM(!(sw_off_timer_val & 0xFFFF0000)); + WR_REG32(&BA431_REGS->SwOffTmrValReg, sw_off_timer_val); +} + + +uint32_t ba431_read_clk_div(void) +{ + return RD_REG32(&BA431_REGS->ClkDivReg); +} + +void ba431_write_clk_div(uint8_t clk_div) +{ + WR_REG32(&BA431_REGS->ClkDivReg, clk_div); +} + + +uint32_t ba431_read_init_wait(void) +{ + return RD_REG32(&BA431_REGS->InitWaitReg); +} + + +void ba431_write_init_wait(uint32_t init_wait_val) +{ + CRYPTOLIB_ASSERT_NM(!(init_wait_val & 0xFFFF0000)); + WR_REG32(&BA431_REGS->InitWaitReg, init_wait_val); +} + + +void ba431_clear_ctrl(void) +{ + WR_REG32(&BA431_REGS->ControlReg, 0); +} + + +void ba431_enable_ndrng(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_NDRNG_ENABLE); +} + + +void ba431_disable_ndrng(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_NDRNG_ENABLE); +} + + +void ba431_enable_test_mode(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_TEST_ENABLE); +} + + +void ba431_disable_test_mode(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_TEST_ENABLE); +} + + +void ba431_set_cond_test_mode(void) +{ + WR_REG32(&BA431_REGS->ControlReg, BA431_CTRL_TEST_ENABLE | BA431_CTRL_BYPASS_AIS31_TEST | BA431_CTRL_BYPASS_HEALTH_TEST); +} + + +void ba431_enable_health_test_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_REP_EN | BA431_CTRL_INT_PROP_EN); +} + + +void ba431_disable_health_test_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~(BA431_CTRL_INT_REP_EN | BA431_CTRL_INT_PROP_EN)); +} + + +void ba431_enable_fifofull_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_FIFOFULL_EN); +} + + +void ba431_disable_fifofull_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_INT_FIFOFULL_EN); +} + + +void ba431_softreset(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_SOFTRESET); + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_SOFTRESET); +} + + +void ba431_enable_AIS31_test_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_INT_ALM_EN); +} + + +void ba431_force_run(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_FORCE_RUN); +} + + +void ba431_disable_AIS31_test_irq(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() & ~BA431_CTRL_INT_ALM_EN); +} + + +void ba431_set_nb128bitblocks(uint8_t nb128bitblocks) +{ + CRYPTOLIB_ASSERT_NM(!(nb128bitblocks & 0xF0)); + WR_REG32(&BA431_REGS->ControlReg, (ba431_read_controlreg() & ~BA431_CTRL_MASK_NB_128BIT_BLOCKS) + | (nb128bitblocks << BA431_CTRL_OFFSET_NB_128BIT_BLOCKS)); +} + + +void ba431_read_conditioning_key(uint32_t *key) +{ + key[0] = RD_REG32(&BA431_REGS->Key0Reg); + key[1] = RD_REG32(&BA431_REGS->Key1Reg); + key[2] = RD_REG32(&BA431_REGS->Key2Reg); + key[3] = RD_REG32(&BA431_REGS->Key3Reg); +} + + +void ba431_write_conditioning_key(const uint32_t * key) +{ + WR_REG32(&BA431_REGS->Key0Reg, key[0]); + WR_REG32(&BA431_REGS->Key1Reg, key[1]); + WR_REG32(&BA431_REGS->Key2Reg, key[2]); + WR_REG32(&BA431_REGS->Key3Reg, key[3]); +} + + +void ba431_write_test_data(uint32_t test_data) +{ + /*Wait for previous data to be processed*/ + while(ba431_read_status() & BA431_STAT_MASK_TESTDATA_BUSY); + /*Write data*/ + WR_REG32(&BA431_REGS->TestDataReg,test_data); +} + + +ba431_state_t ba431_get_state(void) +{ + return (ba431_state_t) (ba431_read_status() & BA431_STAT_MASK_STATE); +} + +void ba431_set_raw_mode(void) +{ + WR_REG32(&BA431_REGS->ControlReg, ba431_read_controlreg() | BA431_CTRL_COND_BYPASS | + BA431_CTRL_BYPASS_HEALTH_TEST | BA431_CTRL_BYPASS_AIS31_TEST); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.h index 6715a85..785640f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.h @@ -1,345 +1,345 @@ -/** - * @file - * @brief Defines BA431 Random generator registers and fields - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#include -#include "cryptolib_def.h" - -#ifndef BA431_CONFIG_H -#define BA431_CONFIG_H - -#include -#include "cryptolib_def.h" - -/** -* @brief Structure that represent the register map of the BA431 -*/ -typedef struct BA431Regs_s -{ - volatile uint32_t ControlReg; /**< (0x00) Control register */ - volatile uint32_t FIFOLevelReg; /**< (0x04) FIFO Level: number of 32-bit - * words of random in the FIFO */ - volatile uint32_t FIFOThresholdReg; /**< (0x08) FIFO threshold: number of - * 32-bit words of random in the FIFO that - * causes BA431 to wake up */ - volatile uint32_t FIFODepthReg; /**< (0x0C) FIFO Depth : maximum number - * of 32-bit words in the FIFO */ - volatile uint32_t Key0Reg; /**< (0x10) Key[0] */ - volatile uint32_t Key1Reg; /**< (0x14) Key[1] */ - volatile uint32_t Key2Reg; /**< (0x18) Key[2] */ - volatile uint32_t Key3Reg; /**< (0x1C) Key[3] */ - volatile uint32_t TestDataReg; /**< (0x20) Test Data register */ - volatile uint32_t RepThresReg; /**< (0x24) Repetition Count Threshold */ - volatile uint32_t P1ThresReg; /**< (0x28) Adaptive Proportion Threshold 1 (64-sample window) */ - volatile uint32_t P2ThresReg; /**< (0x2C) Adaptive Proportion Threshold 2 (4096-sample window) */ - volatile uint32_t StatusReg; /**< (0x30) Status register */ - volatile uint32_t InitWaitReg; /**< (0x34) Initial Wait Counter value: - * number of clock cycles to wait before - * sampling data from the noise source */ - volatile uint32_t DisableOsc0Reg; /**< (0x38) Disable bits for oscillators 0-31 */ - volatile uint32_t DisableOsc1Reg; /**< (0x3C) Disable bits for oscillators 32-63 */ - volatile uint32_t SwOffTmrValReg; /**< (0x40) Switch Off Timer value: - * number of clock cycles to wait after - * FIFO is full before going to sleep */ - volatile uint32_t ClkDivReg; /**< (0x44) Clock Divider register: - * determines sample frequency */ - volatile uint32_t AIS31Conf0Reg; /**< (0x48) AIS31 Configuration register 0 */ - volatile uint32_t AIS31Conf1Reg; /**< (0x4C) AIS31 Configuration register 1 */ - volatile uint32_t AIS31Conf2Reg; /**< (0x50) AIS31 Configuration register 2 */ - volatile uint32_t AIS31StatusReg; /**< (0x54) AIS31 Status register */ - volatile uint32_t HwConfig; /**< (0x58) Hardware configuration register */ -} BA431Regs_t; - - -#define BA431_REGS ((struct BA431Regs_s *) ADDR_BA431_REGS) -#define CRYPTOLIB_BA431_FIFO ((volatile uint32_t *) ADDR_BA431_FIFO) - - -/** @brief mask for ::BA431Regs_t.StatusReg TestData register busy*/ -#define BA431_STAT_MASK_TESTDATA_BUSY 0x00000001 -/** @brief mask for ::BA431Regs_t.StatusReg BA431 state*/ -#define BA431_STAT_MASK_STATE 0x0000000E -/** @brief mask for ::BA431Regs_t.StatusReg repetition count test interrupt status */ -#define BA431_STAT_MASK_REP_FAIL 0x00000010 -/** @brief mask for ::BA431Regs_t.StatusReg adaptive proportion test (1024-sample window) - * interrupt status */ -#define BA431_STAT_MASK_PROP_FAIL 0x00000020 -/** @brief mask for ::BA431Regs_t.StatusReg FIFO full interrupt status */ -#define BA431_STAT_MASK_FULL_INT 0x00000080 -/** @brief mask for ::BA431Regs_t.StatusReg AIS31 preliminary noise alarm status */ -#define BA431_STAT_MASK_PREALM_INT 0x00000100 -/** @brief mask for ::BA431Regs_t.StatusReg AIS31 noise alarm status */ -#define BA431_STAT_MASK_ALM_INT 0x00000200 -/** @brief mask for ::BA431Regs_t.StatusReg startup tests failure*/ -#define BA431_STAT_MASK_STARTUP_FAIL 0x00000400 - -/** @brief value of ::BA431Regs_t.ControlReg to enable NDRNG*/ -#define BA431_CTRL_NDRNG_ENABLE 0x00000001 -/** @brief value of ::BA431Regs_t.ControlReg to enable pseudo-random generator - * for simulation*/ -#define BA431_CTRL_SYNC_MODE 0x00000002 -/** @brief value of ::BA431Regs_t.ControlReg to enable conditioning function test mode*/ -#define BA431_CTRL_TEST_ENABLE 0x00000004 -/** @brief value of ::BA431Regs_t.ControlReg to bypass conditioning function*/ -#define BA431_CTRL_COND_BYPASS 0x00000008 -/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for repetition - * count test failure*/ -#define BA431_CTRL_INT_REP_EN 0x00000010 -/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for adaptive - * proportion test failure (1024-sample window)*/ -#define BA431_CTRL_INT_PROP_EN 0x00000020 -/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for FIFO full*/ -#define BA431_CTRL_INT_FIFOFULL_EN 0x00000080 -/** @brief value of ::BA431Regs_t.ControlReg to do software reset*/ -#define BA431_CTRL_SOFTRESET 0x00000100 -/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for AIS31 preliminary noise alarm*/ -#define BA431_CTRL_INT_PREALM_EN 0x00000200 -/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for AIS31 noise alarm*/ -#define BA431_CTRL_INT_ALM_EN 0x00000400 -/** @brief value of ::BA431Regs_t.ControlReg to force oscillators to run when FIFO is full*/ -#define BA431_CTRL_FORCE_RUN 0x00000800 -/** @brief value of ::BA431Regs_t.ControlReg to bypass NIST startup test*/ -#define BA431_CTRL_BYPASS_HEALTH_TEST 0x00001000 -/** @brief value of ::BA431Regs_t.ControlReg to bypass AIS31 startup test*/ -#define BA431_CTRL_BYPASS_AIS31_TEST 0x00002000 -/** @brief value of ::BA431Regs_t.ControlReg to use conditioning as input to the - * health test module instead of the noise source */ -#define BA431_CTRL_HEALTH_TEST_SEL 0x00004000 -/** @brief value of ::BA431Regs_t.ControlReg to use conditioning as input to the - * AIS31 test module instead of the noise source */ -#define BA431_CTRL_AIS31_TEST_SEL 0x00008000 -/** @brief mask for ::BA431Regs_t.ControlReg, for the setting that controls the - * amount of 128-bit blocks of data that are used as input to the conditioning function*/ -#define BA431_CTRL_MASK_NB_128BIT_BLOCKS 0x000F0000 -/** @brief offset for ::BA431Regs_t.ControlReg, for the setting that controls the - * amount of 128-bit blocks of data that are used as input to the conditioning function*/ -#define BA431_CTRL_OFFSET_NB_128BIT_BLOCKS 16 - -/* Macros to be used on the HwConfig register of the BA431 TRNG */ -#define BA431_HW_CONF_NUM_RINGS_LSB 0 -#define BA431_HW_CONF_NUM_RINGS_MASK (0xFF<HwConfig) - - -/** -* @brief Enumeration of possible BA431 states. -*/ -typedef enum ba431_state_e -{ -BA431_STATE_RESET = 0x00000000, /**< Reset */ -BA431_STATE_STARTUP = 0x00000002, /**< Start-up */ -BA431_STATE_FIFOFULLON = 0x00000004, /**< FIFO full - on */ -BA431_STATE_FIFOFULLOFF = 0x00000006, /**< FIFO full - off */ -BA431_STATE_RUNNING = 0x00000008, /**< Running */ -BA431_STATE_ERROR = 0x0000000A /**< Error */ -} ba431_state_t; - - -/** -* @brief Returns random word from FIFO -* @return 32-bit random value -*/ -uint32_t ba431_read_fifovalue(void); - - -/** -* @brief Returns the current BA431 fifolevel -* @return fifolevel value -*/ -uint32_t ba431_read_fifolevel(void); - - -/** -* @brief Returns the current BA431 status -* @return BA431 status -*/ -uint32_t ba431_read_status(void); - -/** -* @brief Write an user-defined value to the BA431 control register -* @return BA431 ControlReg -*/ -void ba431_write_controlreg(uint32_t control); - -/** -* @brief Returns the current BA431 ControlReg -* @return BA431 ControlReg -*/ -uint32_t ba431_read_controlreg(void); - -/** - * @brief Read the fifo level at which BA431 should wake up - * @return threshold fifo value - */ -uint32_t ba431_read_fifo_wakeup_threshold(void); - -/** -* @brief Writes the fifo level at which BA431 should wake up -* @param fifo_threshold -*/ -void ba431_write_fifo_wakeup_threshold(uint32_t fifo_threshold); - -/** -* @brief Read the current number of cycles before the ring will switch off -* when the fifo becomes full. -* @return the timer values (expressed in cycles) -*/ -uint32_t ba431_read_switch_off_timer(void); - -/** -* @brief Writes switch off timer value -* @param sw_off_timer_val -*/ -void ba431_write_switch_off_timer(uint32_t sw_off_timer_val); - -/** - * @brief Read the current clock divider (Fsampling = Fclock / ClkDiv + 1) - * @return the current clock divider value - */ -uint32_t ba431_read_clk_div(void); - -/** -* @brief Writes clock divider for the sampling frequency -* @param clk_div -*/ -void ba431_write_clk_div(uint8_t clk_div); - -/** - * @brief Read the number of cycles to wait before sampling the noise source - * @return the number of cycles - */ -uint32_t ba431_read_init_wait(void); - -/** -* @brief Writes number of clock cycles to wait before sampling data from the noise source -* @param init_wait_val -*/ -void ba431_write_init_wait(uint32_t init_wait_val); - - -/** -* @brief Clear BA431 control register -*/ -void ba431_clear_ctrl(void); - - -/** -* @brief Enable BA431 configured as NDRNG source -*/ -void ba431_enable_ndrng(void); - - -/** -* @brief Disable BA431 configured as NDRNG source -*/ -void ba431_disable_ndrng(void); - - -/** -* @brief Enable BA431 configured in test mode -*/ -void ba431_enable_test_mode(void); - - -/** -* @brief Disable BA431 configured in test mode -*/ -void ba431_disable_test_mode(void); - - -/** -* @brief Configure BA431 for conditioning test -*/ -void ba431_set_cond_test_mode(void); - - -/** -* @brief Enable BA431 IRQ for health test failures -*/ -void ba431_enable_health_test_irq(void); - - -/** -* @brief Disable BA431 IRQ for healths test failures -*/ -void ba431_disable_health_test_irq(void); - - -/** -* @brief Enable BA431 IRQ when FIFO is full -*/ -void ba431_enable_fifofull_irq(void); - - -/** -* @brief Disable BA431 IRQ when FIFO is full -*/ -void ba431_disable_fifofull_irq(void); - - -/** -* @brief Software reset of the BA431 -*/ -void ba431_softreset(void); - - -/** -* @brief Enable BA431 IRQ for AIS31 test failures -*/ -void ba431_enable_AIS31_test_irq(void); - - -/** -* @brief Force oscillators to run even when FIFO is full -*/ -void ba431_force_run(void); - - -/** -* @brief Disable BA431 IRQ for AIS31 test failures -*/ -void ba431_disable_AIS31_test_irq(void); - -/** -* @brief Set length of input data of AES-CBCMAC post-processing -*/ -void ba431_set_nb128bitblocks(uint8_t nb128bitblocks); - -/** - * @brief Read the current conditioning key - * @param key pointer to an array of 4 32b words - */ -void ba431_read_conditioning_key(uint32_t *key); - -/** -* @brief BA431 write conditioning key -* @param key points to 4x32-bit words containing the key to use -*/ -void ba431_write_conditioning_key(const uint32_t * key); - -/** -* @brief Write test data to BA431 -* @param test_data word to write -*/ -void ba431_write_test_data(uint32_t test_data); - -/** -* @brief Get the current state of BA431 -*/ -ba431_state_t ba431_get_state(void); - -/** -* @brief Sets BA431 to RAW mode. This mode is achieved by setting CondBypass, - HealthTestBypass and AIS31Bypass flags in Control register. -*/ -void ba431_set_raw_mode(void); - -#endif /* BA431_CONFIG_H */ +/** + * @file + * @brief Defines BA431 Random generator registers and fields + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include +#include "cryptolib_def.h" + +#ifndef BA431_CONFIG_H +#define BA431_CONFIG_H + +#include +#include "cryptolib_def.h" + +/** +* @brief Structure that represent the register map of the BA431 +*/ +typedef struct BA431Regs_s +{ + volatile uint32_t ControlReg; /**< (0x00) Control register */ + volatile uint32_t FIFOLevelReg; /**< (0x04) FIFO Level: number of 32-bit + * words of random in the FIFO */ + volatile uint32_t FIFOThresholdReg; /**< (0x08) FIFO threshold: number of + * 32-bit words of random in the FIFO that + * causes BA431 to wake up */ + volatile uint32_t FIFODepthReg; /**< (0x0C) FIFO Depth : maximum number + * of 32-bit words in the FIFO */ + volatile uint32_t Key0Reg; /**< (0x10) Key[0] */ + volatile uint32_t Key1Reg; /**< (0x14) Key[1] */ + volatile uint32_t Key2Reg; /**< (0x18) Key[2] */ + volatile uint32_t Key3Reg; /**< (0x1C) Key[3] */ + volatile uint32_t TestDataReg; /**< (0x20) Test Data register */ + volatile uint32_t RepThresReg; /**< (0x24) Repetition Count Threshold */ + volatile uint32_t P1ThresReg; /**< (0x28) Adaptive Proportion Threshold 1 (64-sample window) */ + volatile uint32_t P2ThresReg; /**< (0x2C) Adaptive Proportion Threshold 2 (4096-sample window) */ + volatile uint32_t StatusReg; /**< (0x30) Status register */ + volatile uint32_t InitWaitReg; /**< (0x34) Initial Wait Counter value: + * number of clock cycles to wait before + * sampling data from the noise source */ + volatile uint32_t DisableOsc0Reg; /**< (0x38) Disable bits for oscillators 0-31 */ + volatile uint32_t DisableOsc1Reg; /**< (0x3C) Disable bits for oscillators 32-63 */ + volatile uint32_t SwOffTmrValReg; /**< (0x40) Switch Off Timer value: + * number of clock cycles to wait after + * FIFO is full before going to sleep */ + volatile uint32_t ClkDivReg; /**< (0x44) Clock Divider register: + * determines sample frequency */ + volatile uint32_t AIS31Conf0Reg; /**< (0x48) AIS31 Configuration register 0 */ + volatile uint32_t AIS31Conf1Reg; /**< (0x4C) AIS31 Configuration register 1 */ + volatile uint32_t AIS31Conf2Reg; /**< (0x50) AIS31 Configuration register 2 */ + volatile uint32_t AIS31StatusReg; /**< (0x54) AIS31 Status register */ + volatile uint32_t HwConfig; /**< (0x58) Hardware configuration register */ +} BA431Regs_t; + + +#define BA431_REGS ((struct BA431Regs_s *) ADDR_BA431_REGS) +#define CRYPTOLIB_BA431_FIFO ((volatile uint32_t *) ADDR_BA431_FIFO) + + +/** @brief mask for ::BA431Regs_t.StatusReg TestData register busy*/ +#define BA431_STAT_MASK_TESTDATA_BUSY 0x00000001 +/** @brief mask for ::BA431Regs_t.StatusReg BA431 state*/ +#define BA431_STAT_MASK_STATE 0x0000000E +/** @brief mask for ::BA431Regs_t.StatusReg repetition count test interrupt status */ +#define BA431_STAT_MASK_REP_FAIL 0x00000010 +/** @brief mask for ::BA431Regs_t.StatusReg adaptive proportion test (1024-sample window) + * interrupt status */ +#define BA431_STAT_MASK_PROP_FAIL 0x00000020 +/** @brief mask for ::BA431Regs_t.StatusReg FIFO full interrupt status */ +#define BA431_STAT_MASK_FULL_INT 0x00000080 +/** @brief mask for ::BA431Regs_t.StatusReg AIS31 preliminary noise alarm status */ +#define BA431_STAT_MASK_PREALM_INT 0x00000100 +/** @brief mask for ::BA431Regs_t.StatusReg AIS31 noise alarm status */ +#define BA431_STAT_MASK_ALM_INT 0x00000200 +/** @brief mask for ::BA431Regs_t.StatusReg startup tests failure*/ +#define BA431_STAT_MASK_STARTUP_FAIL 0x00000400 + +/** @brief value of ::BA431Regs_t.ControlReg to enable NDRNG*/ +#define BA431_CTRL_NDRNG_ENABLE 0x00000001 +/** @brief value of ::BA431Regs_t.ControlReg to enable pseudo-random generator + * for simulation*/ +#define BA431_CTRL_SYNC_MODE 0x00000002 +/** @brief value of ::BA431Regs_t.ControlReg to enable conditioning function test mode*/ +#define BA431_CTRL_TEST_ENABLE 0x00000004 +/** @brief value of ::BA431Regs_t.ControlReg to bypass conditioning function*/ +#define BA431_CTRL_COND_BYPASS 0x00000008 +/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for repetition + * count test failure*/ +#define BA431_CTRL_INT_REP_EN 0x00000010 +/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for adaptive + * proportion test failure (1024-sample window)*/ +#define BA431_CTRL_INT_PROP_EN 0x00000020 +/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for FIFO full*/ +#define BA431_CTRL_INT_FIFOFULL_EN 0x00000080 +/** @brief value of ::BA431Regs_t.ControlReg to do software reset*/ +#define BA431_CTRL_SOFTRESET 0x00000100 +/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for AIS31 preliminary noise alarm*/ +#define BA431_CTRL_INT_PREALM_EN 0x00000200 +/** @brief value of ::BA431Regs_t.ControlReg to enable interrupt for AIS31 noise alarm*/ +#define BA431_CTRL_INT_ALM_EN 0x00000400 +/** @brief value of ::BA431Regs_t.ControlReg to force oscillators to run when FIFO is full*/ +#define BA431_CTRL_FORCE_RUN 0x00000800 +/** @brief value of ::BA431Regs_t.ControlReg to bypass NIST startup test*/ +#define BA431_CTRL_BYPASS_HEALTH_TEST 0x00001000 +/** @brief value of ::BA431Regs_t.ControlReg to bypass AIS31 startup test*/ +#define BA431_CTRL_BYPASS_AIS31_TEST 0x00002000 +/** @brief value of ::BA431Regs_t.ControlReg to use conditioning as input to the + * health test module instead of the noise source */ +#define BA431_CTRL_HEALTH_TEST_SEL 0x00004000 +/** @brief value of ::BA431Regs_t.ControlReg to use conditioning as input to the + * AIS31 test module instead of the noise source */ +#define BA431_CTRL_AIS31_TEST_SEL 0x00008000 +/** @brief mask for ::BA431Regs_t.ControlReg, for the setting that controls the + * amount of 128-bit blocks of data that are used as input to the conditioning function*/ +#define BA431_CTRL_MASK_NB_128BIT_BLOCKS 0x000F0000 +/** @brief offset for ::BA431Regs_t.ControlReg, for the setting that controls the + * amount of 128-bit blocks of data that are used as input to the conditioning function*/ +#define BA431_CTRL_OFFSET_NB_128BIT_BLOCKS 16 + +/* Macros to be used on the HwConfig register of the BA431 TRNG */ +#define BA431_HW_CONF_NUM_RINGS_LSB 0 +#define BA431_HW_CONF_NUM_RINGS_MASK (0xFF<HwConfig) + + +/** +* @brief Enumeration of possible BA431 states. +*/ +typedef enum ba431_state_e +{ +BA431_STATE_RESET = 0x00000000, /**< Reset */ +BA431_STATE_STARTUP = 0x00000002, /**< Start-up */ +BA431_STATE_FIFOFULLON = 0x00000004, /**< FIFO full - on */ +BA431_STATE_FIFOFULLOFF = 0x00000006, /**< FIFO full - off */ +BA431_STATE_RUNNING = 0x00000008, /**< Running */ +BA431_STATE_ERROR = 0x0000000A /**< Error */ +} ba431_state_t; + + +/** +* @brief Returns random word from FIFO +* @return 32-bit random value +*/ +uint32_t ba431_read_fifovalue(void); + + +/** +* @brief Returns the current BA431 fifolevel +* @return fifolevel value +*/ +uint32_t ba431_read_fifolevel(void); + + +/** +* @brief Returns the current BA431 status +* @return BA431 status +*/ +uint32_t ba431_read_status(void); + +/** +* @brief Write an user-defined value to the BA431 control register +* @return BA431 ControlReg +*/ +void ba431_write_controlreg(uint32_t control); + +/** +* @brief Returns the current BA431 ControlReg +* @return BA431 ControlReg +*/ +uint32_t ba431_read_controlreg(void); + +/** + * @brief Read the fifo level at which BA431 should wake up + * @return threshold fifo value + */ +uint32_t ba431_read_fifo_wakeup_threshold(void); + +/** +* @brief Writes the fifo level at which BA431 should wake up +* @param fifo_threshold +*/ +void ba431_write_fifo_wakeup_threshold(uint32_t fifo_threshold); + +/** +* @brief Read the current number of cycles before the ring will switch off +* when the fifo becomes full. +* @return the timer values (expressed in cycles) +*/ +uint32_t ba431_read_switch_off_timer(void); + +/** +* @brief Writes switch off timer value +* @param sw_off_timer_val +*/ +void ba431_write_switch_off_timer(uint32_t sw_off_timer_val); + +/** + * @brief Read the current clock divider (Fsampling = Fclock / ClkDiv + 1) + * @return the current clock divider value + */ +uint32_t ba431_read_clk_div(void); + +/** +* @brief Writes clock divider for the sampling frequency +* @param clk_div +*/ +void ba431_write_clk_div(uint8_t clk_div); + +/** + * @brief Read the number of cycles to wait before sampling the noise source + * @return the number of cycles + */ +uint32_t ba431_read_init_wait(void); + +/** +* @brief Writes number of clock cycles to wait before sampling data from the noise source +* @param init_wait_val +*/ +void ba431_write_init_wait(uint32_t init_wait_val); + + +/** +* @brief Clear BA431 control register +*/ +void ba431_clear_ctrl(void); + + +/** +* @brief Enable BA431 configured as NDRNG source +*/ +void ba431_enable_ndrng(void); + + +/** +* @brief Disable BA431 configured as NDRNG source +*/ +void ba431_disable_ndrng(void); + + +/** +* @brief Enable BA431 configured in test mode +*/ +void ba431_enable_test_mode(void); + + +/** +* @brief Disable BA431 configured in test mode +*/ +void ba431_disable_test_mode(void); + + +/** +* @brief Configure BA431 for conditioning test +*/ +void ba431_set_cond_test_mode(void); + + +/** +* @brief Enable BA431 IRQ for health test failures +*/ +void ba431_enable_health_test_irq(void); + + +/** +* @brief Disable BA431 IRQ for healths test failures +*/ +void ba431_disable_health_test_irq(void); + + +/** +* @brief Enable BA431 IRQ when FIFO is full +*/ +void ba431_enable_fifofull_irq(void); + + +/** +* @brief Disable BA431 IRQ when FIFO is full +*/ +void ba431_disable_fifofull_irq(void); + + +/** +* @brief Software reset of the BA431 +*/ +void ba431_softreset(void); + + +/** +* @brief Enable BA431 IRQ for AIS31 test failures +*/ +void ba431_enable_AIS31_test_irq(void); + + +/** +* @brief Force oscillators to run even when FIFO is full +*/ +void ba431_force_run(void); + + +/** +* @brief Disable BA431 IRQ for AIS31 test failures +*/ +void ba431_disable_AIS31_test_irq(void); + +/** +* @brief Set length of input data of AES-CBCMAC post-processing +*/ +void ba431_set_nb128bitblocks(uint8_t nb128bitblocks); + +/** + * @brief Read the current conditioning key + * @param key pointer to an array of 4 32b words + */ +void ba431_read_conditioning_key(uint32_t *key); + +/** +* @brief BA431 write conditioning key +* @param key points to 4x32-bit words containing the key to use +*/ +void ba431_write_conditioning_key(const uint32_t * key); + +/** +* @brief Write test data to BA431 +* @param test_data word to write +*/ +void ba431_write_test_data(uint32_t test_data); + +/** +* @brief Get the current state of BA431 +*/ +ba431_state_t ba431_get_state(void); + +/** +* @brief Sets BA431 to RAW mode. This mode is achieved by setting CondBypass, + HealthTestBypass and AIS31Bypass flags in Control register. +*/ +void ba431_set_raw_mode(void); + +#endif /* BA431_CONFIG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c index f9a6be3..fdc911c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c @@ -1,220 +1,220 @@ -/** - * @file - * @brief Provides the API to access the cryptographic engine through the cryptoDMA - * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved - */ - -#include "cryptodma_internal.h" -#include "sxregs.h" -#include "cryptolib_def.h" -#include "sx_errors.h" -#include // for size_t - -/** - * @brief This function is used for writing registers that hold addresses. - * It works on both 32 and 64 bit platform - * - * @param dst Address of destination register - * @param src Address of the source - */ -static inline void write_register_address(void* dst, void* src) -{ - for (size_t i = 0; i < sizeof(void *) / sizeof(uint32_t); i++){ - ((volatile uint32_t*) dst)[i] = ((size_t)src >> 32*i ) & 0xFFFFFFFF; - } -} - -void cryptodma_config_sg( - struct dma_sg_descr_s * first_fetch_descriptor, - struct dma_sg_descr_s * first_push_descriptor) -{ - write_register_address((void *)ADDR_DMA_FETCH_ADDR, (void *) first_fetch_descriptor); - write_register_address((void *)ADDR_DMA_PUSH_ADDR, (void *) first_push_descriptor); - WR_REG32(ADDR_DMA_CONFIG, DMA_AXI_CONFIGREG_FETCHER_INDIRECT|DMA_AXI_CONFIGREG_PUSHER_INDIRECT); -} - -void cryptodma_config_direct(block_t dest, block_t src, uint32_t length) -{ - uint32_t transfer_len = dest.len50) { - TRIGGER_HARDFAULT_FCT(); - } - CRYPTOLIB_PRINTF("desc #%02d @%p: %p %p %08X %08X\n", i, desc_ptr, desc_ptr->addr, desc_ptr->next_descr, desc_ptr->length_irq, desc_ptr->tag); - desc_ptr = desc_ptr->next_descr; - i++; - } - CRYPTOLIB_PRINTF("-------------------------------------------------------\n"); -} -#endif - -#ifndef MAP_DESCRIPTOR_HOOKS - -void map_descriptors(struct dma_sg_descr_s *first_fetch_descriptor, - struct dma_sg_descr_s *first_push_descriptor, - struct dma_sg_descr_s **mapped_in, - struct dma_sg_descr_s **mapped_out) -{ - *mapped_in = first_fetch_descriptor; - *mapped_out = first_push_descriptor; -} - -void unmap_descriptors(struct dma_sg_descr_s *out_descs) -{ - (void)out_descs; -} -#endif - -void cryptodma_run_sg(struct dma_sg_descr_s * first_fetch_descriptor, struct dma_sg_descr_s * first_push_descriptor) -{ - struct dma_sg_descr_s *mapped_in, *mapped_out; - #if DMA_SG_DEBUG - debug_print_sg(first_fetch_descriptor); - debug_print_sg(first_push_descriptor); - #endif - - map_descriptors(first_fetch_descriptor, first_push_descriptor, &mapped_in, &mapped_out); - cryptodma_config_sg(mapped_in, mapped_out); - cryptodma_start(); - cryptodma_wait(); - cryptodma_check_status(); - unmap_descriptors(first_push_descriptor); -} - -struct dma_sg_descr_s* write_desc_always( - struct dma_sg_descr_s *descr, - volatile void *addr, - const uint32_t length, - const uint32_t flags, - const uint32_t tag) -{ - struct dma_sg_descr_s *nextdescr = descr + 1; - descr->next_descr = nextdescr; - descr->addr = addr; - - // Build flags[31:28] and length[27:0] - descr->length_irq = length & DMA_AXI_DESCR_MASK_LENGTH; - if(addr) - descr->length_irq |= (flags & ~DMA_AXI_DESCR_MASK_LENGTH); - else - descr->length_irq |= DMA_AXI_DESCR_DISCARD; - - descr->tag = tag; - return nextdescr; -} - -void realign_desc(struct dma_sg_descr_s * d) -{ - d->length_irq |= DMA_AXI_DESCR_REALIGN; -} - -void set_last_desc(struct dma_sg_descr_s * d) -{ - d->next_descr = DMA_AXI_DESCR_NEXT_STOP; - d->tag |= DMA_SG_TAG_ISLAST; - d->length_irq |= DMA_AXI_DESCR_REALIGN; -} - -void set_desc_invalid_bytes( - struct dma_sg_descr_s *d, - const uint32_t n_bytes) -{ - // Check it is the last data descriptor - CRYPTOLIB_ASSERT(!(d->tag & DMA_SG_TAG_ISCONFIG) && - (d->tag & DMA_SG_TAG_ISLAST), "Descriptor is not tagged as last data"); - - // Check the engine supports padding - switch(d->tag & DMA_SG_ENGINESELECT_MASK) { - case DMA_SG_ENGINESELECT_BA411E: - case DMA_SG_ENGINESELECT_BA413: - case DMA_SG_ENGINESELECT_BA417: - { - uint32_t pad = (n_bytes & DMA_SG_TAG_PADDING_MASK); - d->tag |= pad << DMA_SG_TAG_PADDING_OFFSET; - d->length_irq += pad; - break; - } - default: - CRYPTOLIB_ASSERT(0, "Crypto engine does not support invalid bytes/ is not implemented"); - break; - } -} - +/** + * @file + * @brief Provides the API to access the cryptographic engine through the cryptoDMA + * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved + */ + +#include "cryptodma_internal.h" +#include "sxregs.h" +#include "cryptolib_def.h" +#include "sx_errors.h" +#include // for size_t + +/** + * @brief This function is used for writing registers that hold addresses. + * It works on both 32 and 64 bit platform + * + * @param dst Address of destination register + * @param src Address of the source + */ +static inline void write_register_address(void* dst, void* src) +{ + for (size_t i = 0; i < sizeof(void *) / sizeof(uint32_t); i++){ + ((volatile uint32_t*) dst)[i] = ((size_t)src >> 32*i ) & 0xFFFFFFFF; + } +} + +void cryptodma_config_sg( + struct dma_sg_descr_s * first_fetch_descriptor, + struct dma_sg_descr_s * first_push_descriptor) +{ + write_register_address((void *)ADDR_DMA_FETCH_ADDR, (void *) first_fetch_descriptor); + write_register_address((void *)ADDR_DMA_PUSH_ADDR, (void *) first_push_descriptor); + WR_REG32(ADDR_DMA_CONFIG, DMA_AXI_CONFIGREG_FETCHER_INDIRECT|DMA_AXI_CONFIGREG_PUSHER_INDIRECT); +} + +void cryptodma_config_direct(block_t dest, block_t src, uint32_t length) +{ + uint32_t transfer_len = dest.len50) { + TRIGGER_HARDFAULT_FCT(); + } + CRYPTOLIB_PRINTF("desc #%02d @%p: %p %p %08X %08X\n", i, desc_ptr, desc_ptr->addr, desc_ptr->next_descr, desc_ptr->length_irq, desc_ptr->tag); + desc_ptr = desc_ptr->next_descr; + i++; + } + CRYPTOLIB_PRINTF("-------------------------------------------------------\n"); +} +#endif + +#ifndef MAP_DESCRIPTOR_HOOKS + +void map_descriptors(struct dma_sg_descr_s *first_fetch_descriptor, + struct dma_sg_descr_s *first_push_descriptor, + struct dma_sg_descr_s **mapped_in, + struct dma_sg_descr_s **mapped_out) +{ + *mapped_in = first_fetch_descriptor; + *mapped_out = first_push_descriptor; +} + +void unmap_descriptors(struct dma_sg_descr_s *out_descs) +{ + (void)out_descs; +} +#endif + +void cryptodma_run_sg(struct dma_sg_descr_s * first_fetch_descriptor, struct dma_sg_descr_s * first_push_descriptor) +{ + struct dma_sg_descr_s *mapped_in, *mapped_out; + #if DMA_SG_DEBUG + debug_print_sg(first_fetch_descriptor); + debug_print_sg(first_push_descriptor); + #endif + + map_descriptors(first_fetch_descriptor, first_push_descriptor, &mapped_in, &mapped_out); + cryptodma_config_sg(mapped_in, mapped_out); + cryptodma_start(); + cryptodma_wait(); + cryptodma_check_status(); + unmap_descriptors(first_push_descriptor); +} + +struct dma_sg_descr_s* write_desc_always( + struct dma_sg_descr_s *descr, + volatile void *addr, + const uint32_t length, + const uint32_t flags, + const uint32_t tag) +{ + struct dma_sg_descr_s *nextdescr = descr + 1; + descr->next_descr = nextdescr; + descr->addr = addr; + + // Build flags[31:28] and length[27:0] + descr->length_irq = length & DMA_AXI_DESCR_MASK_LENGTH; + if(addr) + descr->length_irq |= (flags & ~DMA_AXI_DESCR_MASK_LENGTH); + else + descr->length_irq |= DMA_AXI_DESCR_DISCARD; + + descr->tag = tag; + return nextdescr; +} + +void realign_desc(struct dma_sg_descr_s * d) +{ + d->length_irq |= DMA_AXI_DESCR_REALIGN; +} + +void set_last_desc(struct dma_sg_descr_s * d) +{ + d->next_descr = DMA_AXI_DESCR_NEXT_STOP; + d->tag |= DMA_SG_TAG_ISLAST; + d->length_irq |= DMA_AXI_DESCR_REALIGN; +} + +void set_desc_invalid_bytes( + struct dma_sg_descr_s *d, + const uint32_t n_bytes) +{ + // Check it is the last data descriptor + CRYPTOLIB_ASSERT(!(d->tag & DMA_SG_TAG_ISCONFIG) && + (d->tag & DMA_SG_TAG_ISLAST), "Descriptor is not tagged as last data"); + + // Check the engine supports padding + switch(d->tag & DMA_SG_ENGINESELECT_MASK) { + case DMA_SG_ENGINESELECT_BA411E: + case DMA_SG_ENGINESELECT_BA413: + case DMA_SG_ENGINESELECT_BA417: + { + uint32_t pad = (n_bytes & DMA_SG_TAG_PADDING_MASK); + d->tag |= pad << DMA_SG_TAG_PADDING_OFFSET; + d->length_irq += pad; + break; + } + default: + CRYPTOLIB_ASSERT(0, "Crypto engine does not support invalid bytes/ is not implemented"); + break; + } +} + diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.h index 33da9f4..e5b3a22 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.h @@ -1,274 +1,274 @@ -/** - * @file - * @brief Provides the API to access the cryptographic engine through the cryptoDMA - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#ifndef CRYPTODMA_INTERNAL_H -#define CRYPTODMA_INTERNAL_H -#include "sx_dma.h" -#include "cryptolib_types.h" - -/** -* @brief Select which core the DMA will use. To set in descriptor ::dma_sg_descr_s.tag. -*/ -enum dma_sg_EngineSelect_e -{ - DMA_SG_ENGINESELECT_BYPASS = 0x00, /**< direct bypass from input to output */ - DMA_SG_ENGINESELECT_BA411E = 0x01, /**< data flow through BA411E AES */ - DMA_SG_ENGINESELECT_BA412 = 0x02, /**< data flow through BA412 DES */ - DMA_SG_ENGINESELECT_BA413 = 0x03, /**< data flow through BA413 Hash */ - DMA_SG_ENGINESELECT_BA417 = 0x04, /**< data flow through BA417 ChaChaPoly */ - DMA_SG_ENGINESELECT_BA418 = 0x05, /**< data flow through BA418 SHA3 */ - - DMA_SG_ENGINESELECT_BA419 = 0x0B, /**< data flow through BA419 SM4 */ - DMA_SG_ENGINESELECT_BA424 = 0x0F, /**< data flow through BA424 ARIA */ - - - DMA_SG_ENGINESELECT_MASK = 0xF /**< Mask on the engine */ -}; - -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, to direct data to parameters */ -#define DMA_SG_TAG_ISCONFIG 0x00000010 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, to direct data to processing */ -#define DMA_SG_TAG_ISDATA 0x00000000 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag,specifying data as last */ -#define DMA_SG_TAG_ISLAST 0x00000020 - -/** @brief macro to set the offset in the configuration for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag */ -#define DMA_SG_TAG_SETCFGOFFSET(a) ((((a)&0xFF)<<8)) - -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to message */ -#define DMA_SG_TAG_DATATYPE_HASHMSG 0x00000000 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to initialization state */ -#define DMA_SG_TAG_DATATYPE_HASHINIT 0x00000040 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to HMAC key */ -#define DMA_SG_TAG_DATATYPE_HASHKEY 0x00000080 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type payload (will be encrypted/decrypted and authenticated) */ -#define DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD 0x00000000 -/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type header (will only be authenticated, not encrypted/decrypted) */ -#define DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER 0x00000040 - -#define DMA_SG_TAG_PADDING_MASK 0x1F -#define DMA_SG_TAG_PADDING_OFFSET 8 - /** @brief macro to set the amount of invalid bytes in for ::dma_sg_descr_s.tag or ::dma_sg_regs_t.fetch_tag */ -#define DMA_SG_TAG_SETINVALIDBYTES(a) ((((a) & DMA_SG_TAG_PADDING_MASK) \ - << DMA_SG_TAG_PADDING_OFFSET)) - -/** - * @brief Configure fetch and push operations in scatter-gather mode on internal DMA - * @param first_fetch_descriptor physical address of the first fetcher descriptor to be configured - * @param first_push_descriptor physical address of the first pusher descriptor to be configured - */ -void cryptodma_config_sg( - struct dma_sg_descr_s * first_fetch_descriptor, - struct dma_sg_descr_s * first_push_descriptor); - -/** - * @brief Configure fetch and push operations in direct mode on internal DMA - * @param src block_t to the source data to transfer - * @param dest block_t to the destination location - * @param length the length in bytes to transfer (from src to dest) - */ -void cryptodma_config_direct(block_t dest, block_t src, uint32_t length); - -/** - * @brief Check cryptodma status - * Trigger a hardfault if any error occured - */ -void cryptodma_check_status(void) ; - -/** @brief Reset the internal DMA */ -void cryptodma_reset(void); - -/** @brief Start internal DMA transfer */ -void cryptodma_start(void); - -/** @brief Wait until internal DMA is done */ -void cryptodma_wait(void); - -/** - * @brief Check cryptodma error flag - * @return CRYPTOLIB_DMA_ERR if fifo's are not empty, CRYPTOLIB_SUCCESS otherwise - */ -uint32_t cryptodma_check_bus_error(void); - -/** - * @brief Issues an internal DMA transfer command in indirect mode - * - * It configures the internal DMA to issue a data transfer in indirect mode. - * After that, it waits for the completion (interrupt or polling) and in case - * of errors on the bus will trigger an hard fault. - * - * @param first_fetch_descriptor list of descriptors to fetch from - * @param first_push_descriptor list of descriptors to push to - */ -void cryptodma_run_sg(struct dma_sg_descr_s * first_fetch_descriptor, struct dma_sg_descr_s * first_push_descriptor); - - -/** - * @brief Map software descriptors and buffers to the hardware - * - * \warning \c unmap_descriptors should be called to uninitialize after transfer. - * - * @param first_fetch_descriptor DMA input descriptors list - * @param first_push_descriptor DMA output descriptors list - * @param mapped_in Pointer to the address of the mapped input descriptors list - * @param mapped_out Pointer to the address of the mapped output descriptors list - */ -void map_descriptors(struct dma_sg_descr_s *first_fetch_descriptor, - struct dma_sg_descr_s *first_push_descriptor, - struct dma_sg_descr_s **mapped_in, - struct dma_sg_descr_s **mapped_out); - -/** @brief Unmap descriptors and buffers to the hardware - * @param out_descs Output DMA descriptors list - */ -void unmap_descriptors(struct dma_sg_descr_s *out_descs); - -/** - * @brief Write a descriptor and return the next updated address - * - * Fill the descriptor (even in case of null length) with the address to - * fetch/push data, the amount of bytes to fetch/push, the additional flags - * required by the DMA (like fetch in a fifo mode or discard data) and the tag - * which selects the crypto engine and extra flags for this specific - * crypto engine. - * - * @param descr pointer to a descriptor to fill with others parameters - * @param addr the address where data will be fetched/pushed - * @param length amount of bytes to fetch/push - * @param flags the extra flags describing if data are coming read like - * from a fifo (::DMA_AXI_DESCR_CONST_ADDR), if it is needed - * to realign on the width of the DMA bus - * (::DMA_AXI_DESCR_REALIGN) or if data can be discarded - * (::DMA_AXI_DESCR_DISCARD) - * @param tag contains the engine from/to fetch/push data - * (see ::dma_sg_EngineSelect_e), indicates - * if descriptor contains data or configuration is the last - * and specific additional information per crypto-engine. - * - * @return the address of the next descriptor available (it supposes a large - * enough array of descriptors is passed as first parameter). - */ -struct dma_sg_descr_s* write_desc_always( - struct dma_sg_descr_s *descr, - volatile void *addr, - const uint32_t length, - const uint32_t flags, - const uint32_t tag); - - /** - * @brief Write a descriptor and returns the next updated address only if required - * - * Works like ::write_desc_always but start first by checking if there is any - * data to fetch/push (length > 0). If not, does not fill the descriptor - * - * @param descr pointer to a descriptor to fill with others parameters - * @param addr the address where data will be fetched/pushed - * @param length amount of bytes to fetch/push - * @param flags the extra flags like realign/const address, discard - * @param tag contains crypto engines, is last or not, config or data, ... - * - * @return the address of the next descriptor available (it supposes a large - * enough array of descriptors is passed as first parameter). It could - * be the same as ::descr - */ -static inline struct dma_sg_descr_s* write_desc( - struct dma_sg_descr_s *descr, - volatile void *addr, - const uint32_t length, - const uint32_t flags, - const uint32_t tag) -{ - if (length) - return write_desc_always(descr, addr, length, flags, tag); - return descr; -} - - -/** - * @brief Write a descriptor and returns the next updated address - * - * Works like ::write_desc_always but dedicated for block_t - * - * @param descr pointer to a descriptor to fill with others parameters - * @param blk a ::block_t containing an address, a length and flags - * @param flags the extra flags like realign or discard - * @param tag contains crypto engines, is last or not, config or data, ... - * - * @return the address of the next descriptor available - */ -static inline struct dma_sg_descr_s *write_desc_always_blk( - struct dma_sg_descr_s *descr, - const block_t *blk, - const uint32_t flags, - const uint32_t tag) -{ - return write_desc_always( - descr, - blk->addr, - blk->len, - blk->flags | flags, - tag); -} - -/** - * @brief Write a descriptor and returns the next updated address - * - * Works like ::write_desc but dedicated for block_t - * - * @param descr pointer to a descriptor to fill with others parameters - * @param blk a ::block_t containing an address, a length and flags - * @param flags the extra flags like realign or discard - * @param tag contains crypto engines, is last or not, config or data, ... - * - * @return the address of the next descriptor available (could be the same is ::descr) - */ -static inline struct dma_sg_descr_s *write_desc_blk( - struct dma_sg_descr_s *descr, - const block_t *blk, - const uint32_t flags, - const uint32_t tag) -{ - return write_desc( - descr, - blk->addr, - blk->len, - blk->flags | flags, - tag); -} - -/** - * @brief Mark input descriptor as needing to be realigned by the DMA - * @param d address of descriptor - */ -void realign_desc(struct dma_sg_descr_s * d); - -/** - * @brief Mark input descriptor as last of a list of descriptors - * @param d address of last descriptor - */ -void set_last_desc(struct dma_sg_descr_s * d); - -/** - * @brief Update the last data descriptor with the extra invalid bytes. - * - * For the currently supported engines in software (AES, ChaCha, SHA(1-2-3)), - * the corresponding HW field holds invalid bytes, meaning padding after - * the last data (see the CryptoMaster Datasheet, Table 13). - * - * This function ensures that the invalid bytes are set on a descriptor \d - * already marked as ::DMA_SG_TAG_ISLAST, ::DMA_SG_TAG_ISDATA and also - * verifies that the selected engine is currently supported before updating - * the descriptor. - * - * @param d the descriptor to update - * @param n_bytes the extra padding to append ( < 32, 5 bits in HW). - */ -void set_desc_invalid_bytes( - struct dma_sg_descr_s *d, - const uint32_t n_bytes); - - -#endif +/** + * @file + * @brief Provides the API to access the cryptographic engine through the cryptoDMA + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + +#ifndef CRYPTODMA_INTERNAL_H +#define CRYPTODMA_INTERNAL_H +#include "sx_dma.h" +#include "cryptolib_types.h" + +/** +* @brief Select which core the DMA will use. To set in descriptor ::dma_sg_descr_s.tag. +*/ +enum dma_sg_EngineSelect_e +{ + DMA_SG_ENGINESELECT_BYPASS = 0x00, /**< direct bypass from input to output */ + DMA_SG_ENGINESELECT_BA411E = 0x01, /**< data flow through BA411E AES */ + DMA_SG_ENGINESELECT_BA412 = 0x02, /**< data flow through BA412 DES */ + DMA_SG_ENGINESELECT_BA413 = 0x03, /**< data flow through BA413 Hash */ + DMA_SG_ENGINESELECT_BA417 = 0x04, /**< data flow through BA417 ChaChaPoly */ + DMA_SG_ENGINESELECT_BA418 = 0x05, /**< data flow through BA418 SHA3 */ + + DMA_SG_ENGINESELECT_BA419 = 0x0B, /**< data flow through BA419 SM4 */ + DMA_SG_ENGINESELECT_BA424 = 0x0F, /**< data flow through BA424 ARIA */ + + + DMA_SG_ENGINESELECT_MASK = 0xF /**< Mask on the engine */ +}; + +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, to direct data to parameters */ +#define DMA_SG_TAG_ISCONFIG 0x00000010 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, to direct data to processing */ +#define DMA_SG_TAG_ISDATA 0x00000000 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag,specifying data as last */ +#define DMA_SG_TAG_ISLAST 0x00000020 + +/** @brief macro to set the offset in the configuration for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag */ +#define DMA_SG_TAG_SETCFGOFFSET(a) ((((a)&0xFF)<<8)) + +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to message */ +#define DMA_SG_TAG_DATATYPE_HASHMSG 0x00000000 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to initialization state */ +#define DMA_SG_TAG_DATATYPE_HASHINIT 0x00000040 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type to HMAC key */ +#define DMA_SG_TAG_DATATYPE_HASHKEY 0x00000080 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type payload (will be encrypted/decrypted and authenticated) */ +#define DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD 0x00000000 +/** @brief value for ::dma_sg_descr_s.tag or ::dma_sg_regs32_t.fetch_tag, specifying data type header (will only be authenticated, not encrypted/decrypted) */ +#define DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER 0x00000040 + +#define DMA_SG_TAG_PADDING_MASK 0x1F +#define DMA_SG_TAG_PADDING_OFFSET 8 + /** @brief macro to set the amount of invalid bytes in for ::dma_sg_descr_s.tag or ::dma_sg_regs_t.fetch_tag */ +#define DMA_SG_TAG_SETINVALIDBYTES(a) ((((a) & DMA_SG_TAG_PADDING_MASK) \ + << DMA_SG_TAG_PADDING_OFFSET)) + +/** + * @brief Configure fetch and push operations in scatter-gather mode on internal DMA + * @param first_fetch_descriptor physical address of the first fetcher descriptor to be configured + * @param first_push_descriptor physical address of the first pusher descriptor to be configured + */ +void cryptodma_config_sg( + struct dma_sg_descr_s * first_fetch_descriptor, + struct dma_sg_descr_s * first_push_descriptor); + +/** + * @brief Configure fetch and push operations in direct mode on internal DMA + * @param src block_t to the source data to transfer + * @param dest block_t to the destination location + * @param length the length in bytes to transfer (from src to dest) + */ +void cryptodma_config_direct(block_t dest, block_t src, uint32_t length); + +/** + * @brief Check cryptodma status + * Trigger a hardfault if any error occured + */ +void cryptodma_check_status(void) ; + +/** @brief Reset the internal DMA */ +void cryptodma_reset(void); + +/** @brief Start internal DMA transfer */ +void cryptodma_start(void); + +/** @brief Wait until internal DMA is done */ +void cryptodma_wait(void); + +/** + * @brief Check cryptodma error flag + * @return CRYPTOLIB_DMA_ERR if fifo's are not empty, CRYPTOLIB_SUCCESS otherwise + */ +uint32_t cryptodma_check_bus_error(void); + +/** + * @brief Issues an internal DMA transfer command in indirect mode + * + * It configures the internal DMA to issue a data transfer in indirect mode. + * After that, it waits for the completion (interrupt or polling) and in case + * of errors on the bus will trigger an hard fault. + * + * @param first_fetch_descriptor list of descriptors to fetch from + * @param first_push_descriptor list of descriptors to push to + */ +void cryptodma_run_sg(struct dma_sg_descr_s * first_fetch_descriptor, struct dma_sg_descr_s * first_push_descriptor); + + +/** + * @brief Map software descriptors and buffers to the hardware + * + * \warning \c unmap_descriptors should be called to uninitialize after transfer. + * + * @param first_fetch_descriptor DMA input descriptors list + * @param first_push_descriptor DMA output descriptors list + * @param mapped_in Pointer to the address of the mapped input descriptors list + * @param mapped_out Pointer to the address of the mapped output descriptors list + */ +void map_descriptors(struct dma_sg_descr_s *first_fetch_descriptor, + struct dma_sg_descr_s *first_push_descriptor, + struct dma_sg_descr_s **mapped_in, + struct dma_sg_descr_s **mapped_out); + +/** @brief Unmap descriptors and buffers to the hardware + * @param out_descs Output DMA descriptors list + */ +void unmap_descriptors(struct dma_sg_descr_s *out_descs); + +/** + * @brief Write a descriptor and return the next updated address + * + * Fill the descriptor (even in case of null length) with the address to + * fetch/push data, the amount of bytes to fetch/push, the additional flags + * required by the DMA (like fetch in a fifo mode or discard data) and the tag + * which selects the crypto engine and extra flags for this specific + * crypto engine. + * + * @param descr pointer to a descriptor to fill with others parameters + * @param addr the address where data will be fetched/pushed + * @param length amount of bytes to fetch/push + * @param flags the extra flags describing if data are coming read like + * from a fifo (::DMA_AXI_DESCR_CONST_ADDR), if it is needed + * to realign on the width of the DMA bus + * (::DMA_AXI_DESCR_REALIGN) or if data can be discarded + * (::DMA_AXI_DESCR_DISCARD) + * @param tag contains the engine from/to fetch/push data + * (see ::dma_sg_EngineSelect_e), indicates + * if descriptor contains data or configuration is the last + * and specific additional information per crypto-engine. + * + * @return the address of the next descriptor available (it supposes a large + * enough array of descriptors is passed as first parameter). + */ +struct dma_sg_descr_s* write_desc_always( + struct dma_sg_descr_s *descr, + volatile void *addr, + const uint32_t length, + const uint32_t flags, + const uint32_t tag); + + /** + * @brief Write a descriptor and returns the next updated address only if required + * + * Works like ::write_desc_always but start first by checking if there is any + * data to fetch/push (length > 0). If not, does not fill the descriptor + * + * @param descr pointer to a descriptor to fill with others parameters + * @param addr the address where data will be fetched/pushed + * @param length amount of bytes to fetch/push + * @param flags the extra flags like realign/const address, discard + * @param tag contains crypto engines, is last or not, config or data, ... + * + * @return the address of the next descriptor available (it supposes a large + * enough array of descriptors is passed as first parameter). It could + * be the same as ::descr + */ +static inline struct dma_sg_descr_s* write_desc( + struct dma_sg_descr_s *descr, + volatile void *addr, + const uint32_t length, + const uint32_t flags, + const uint32_t tag) +{ + if (length) + return write_desc_always(descr, addr, length, flags, tag); + return descr; +} + + +/** + * @brief Write a descriptor and returns the next updated address + * + * Works like ::write_desc_always but dedicated for block_t + * + * @param descr pointer to a descriptor to fill with others parameters + * @param blk a ::block_t containing an address, a length and flags + * @param flags the extra flags like realign or discard + * @param tag contains crypto engines, is last or not, config or data, ... + * + * @return the address of the next descriptor available + */ +static inline struct dma_sg_descr_s *write_desc_always_blk( + struct dma_sg_descr_s *descr, + const block_t *blk, + const uint32_t flags, + const uint32_t tag) +{ + return write_desc_always( + descr, + blk->addr, + blk->len, + blk->flags | flags, + tag); +} + +/** + * @brief Write a descriptor and returns the next updated address + * + * Works like ::write_desc but dedicated for block_t + * + * @param descr pointer to a descriptor to fill with others parameters + * @param blk a ::block_t containing an address, a length and flags + * @param flags the extra flags like realign or discard + * @param tag contains crypto engines, is last or not, config or data, ... + * + * @return the address of the next descriptor available (could be the same is ::descr) + */ +static inline struct dma_sg_descr_s *write_desc_blk( + struct dma_sg_descr_s *descr, + const block_t *blk, + const uint32_t flags, + const uint32_t tag) +{ + return write_desc( + descr, + blk->addr, + blk->len, + blk->flags | flags, + tag); +} + +/** + * @brief Mark input descriptor as needing to be realigned by the DMA + * @param d address of descriptor + */ +void realign_desc(struct dma_sg_descr_s * d); + +/** + * @brief Mark input descriptor as last of a list of descriptors + * @param d address of last descriptor + */ +void set_last_desc(struct dma_sg_descr_s * d); + +/** + * @brief Update the last data descriptor with the extra invalid bytes. + * + * For the currently supported engines in software (AES, ChaCha, SHA(1-2-3)), + * the corresponding HW field holds invalid bytes, meaning padding after + * the last data (see the CryptoMaster Datasheet, Table 13). + * + * This function ensures that the invalid bytes are set on a descriptor \d + * already marked as ::DMA_SG_TAG_ISLAST, ::DMA_SG_TAG_ISDATA and also + * verifies that the selected engine is currently supported before updating + * the descriptor. + * + * @param d the descriptor to update + * @param n_bytes the extra padding to append ( < 32, 5 bits in HW). + */ +void set_desc_invalid_bytes( + struct dma_sg_descr_s *d, + const uint32_t n_bytes); + + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c index 3f4ad51..ed50d40 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c @@ -1,15 +1,15 @@ -/** - * @file - * @brief Provide the value when user wants a default block_t - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#include -#include "cryptolib_types.h" -#include "sx_dma.h" - -const block_t NULL_blk = { - .addr = NULL, - .len = 0, - .flags = BLOCK_S_INCR_ADDR | DMA_AXI_DESCR_DISCARD // FIXME we are mixing BLOCK_S_ with DMA_AXI_ -}; +/** + * @file + * @brief Provide the value when user wants a default block_t + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + +#include +#include "cryptolib_types.h" +#include "sx_dma.h" + +const block_t NULL_blk = { + .addr = NULL, + .len = 0, + .flags = BLOCK_S_INCR_ADDR | DMA_AXI_DESCR_DISCARD // FIXME we are mixing BLOCK_S_ with DMA_AXI_ +}; diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/padding.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/padding.h index d6e5dd0..4b9fd69 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/padding.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/padding.h @@ -1,31 +1,31 @@ -/** - * @file - * @brief Handles zero padding - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SX_PAD_H -#define SX_PAD_H - -#include -#include -#include "cryptolib_types.h" - -/** - * Pads the hash of hashLen to EM of emLen. MSBs are set to 0 - * @param EM Destination buffer (pointer) - * @param emLen Length of the destination buffer (bytes) - * @param hash Input to pad - * @param hashLen Length of the input - */ -void pad_zeros(uint8_t *EM, size_t emLen, uint8_t *hash, size_t hashLen); - -/** - * Pads with zeroes for blk - * @param out block_t to the output buffer - * @param in inside block_t - */ -void pad_zeros_blk(block_t out, block_t in); - -#endif +/** + * @file + * @brief Handles zero padding + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SX_PAD_H +#define SX_PAD_H + +#include +#include +#include "cryptolib_types.h" + +/** + * Pads the hash of hashLen to EM of emLen. MSBs are set to 0 + * @param EM Destination buffer (pointer) + * @param emLen Length of the destination buffer (bytes) + * @param hash Input to pad + * @param hashLen Length of the input + */ +void pad_zeros(uint8_t *EM, size_t emLen, uint8_t *hash, size_t hashLen); + +/** + * Pads with zeroes for blk + * @param out block_t to the output buffer + * @param in inside block_t + */ +void pad_zeros_blk(block_t out, block_t in); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c index 518c4f3..d9bb788 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c @@ -1,1026 +1,1026 @@ -/** - * @file - * @brief Defines the procedures to make operations with - * the BA411E AES - * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved - */ - - -#include -#include -#include //for memset -#include "sx_aes.h" -#include "cryptolib_def.h" -#include "cryptodma_internal.h" -#include "sx_memcpy.h" -#include "sx_memcmp.h" -#include "ba411e_config.h" -#include "sx_math.h" -#include "sx_trng.h" -#include "sx_errors.h" -#include "sx_blk_cipher.h" - -uint8_t aes_hw_key1; -uint8_t aes_hw_key2; - -/** @brief This function is called in sx_blk_cipher.c - * Update fields related to the key characteristics for block cipher - * operation - * - * The block cipher engines have a 32b configuration register with many fields. - * A few of them depends of the block cipher key itself. The function set these - * fields only and let the others unchanged. It allows to decouple key related - * configuration with the algorithm (CBC/ECB,...) and the operation - * (encryption/decryption, ...) - * - * @param key block cipher key involved. - * @param config A 32b word to update based on the \c key characteristics - * @return CRYPTOLIB_SUCCESS if key length is recognised (128 ,192 or 256b) and - * supported. - * CRYPTOLIB_UNSUPPORTED_ERR if key length is recognized but not supported - * CRYPTOLIB_INVALID_PARAM if key length is not recognised. - */ -uint32_t sx_aes_set_hw_config_for_key(block_t *key, uint32_t *config) -{ - // Check and configure for key length - switch(key->len) { - case 16: - if (!AES_HW_CFG_KEY_SIZE_128_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - *config |= SX_BLK_CIPHER_MODEID_128; - break; - case 24: - if (!AES_HW_CFG_KEY_SIZE_192_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - *config |= SX_BLK_CIPHER_MODEID_192; - break; - case 32: - if (!AES_HW_CFG_KEY_SIZE_256_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - *config |= SX_BLK_CIPHER_MODEID_256; - break; - default: - return CRYPTOLIB_INVALID_PARAM; - } - - // Configure to use HW keys - if (key->addr == &aes_hw_key1) { - *config |= SX_BLK_CIPHER_MODEID_KEY1; - key->len = 0; // We don't need to transfer key content when using HW ones - } - else if (key->addr == &aes_hw_key2) { - *config |= SX_BLK_CIPHER_MODEID_KEY2; - key->len = 0; // We don't need to transfer key content when using HW ones - } - return CRYPTOLIB_SUCCESS; -} - -// AES-ECB -// ----------------------------------------------------------------------------- -uint32_t sx_aes_ecb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext) -{ - if (!AES_HW_CFG_ECB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ecb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext); -} - -uint32_t sx_aes_ecb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext) -{ - if (!AES_HW_CFG_ECB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ecb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext); -} - -// AES-CBC -// ----------------------------------------------------------------------------- -uint32_t sx_aes_cbc_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv); -} -uint32_t sx_aes_cbc_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv); -} - -uint32_t sx_aes_cbc_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CBC, key, plaintext, - ciphertext, iv, ctx_out); -} - -uint32_t sx_aes_cbc_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CBC, key, ciphertext, - plaintext, iv, ctx_out); -} - -uint32_t sx_aes_cbc_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CBC, key, plaintext, - ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_cbc_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CBC, key, ciphertext, - plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_cbc_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in); -} - -uint32_t sx_aes_cbc_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CBC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in); -} - -// AES-CTR -// ----------------------------------------------------------------------------- -uint32_t sx_aes_ctr_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ctr(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv); -} - -uint32_t sx_aes_ctr_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ctr(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv); -} - -uint32_t sx_aes_ctr_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CTR, key, plaintext, - ciphertext, iv, ctx_out); -} - -uint32_t sx_aes_ctr_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CTR, key, ciphertext, - plaintext, iv, ctx_out); -} - -uint32_t sx_aes_ctr_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CTR, key, plaintext, - ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ctr_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CTR, key, ciphertext, - plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ctr_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ctr_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in); -} - -uint32_t sx_aes_ctr_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CTR_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ctr_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in); -} - -// AES-CFB -// ----------------------------------------------------------------------------- -uint32_t sx_aes_cfb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - SX_BLK_CIPHER_MODE_CFB, key, plaintext, ciphertext, iv); -} - -uint32_t sx_aes_cfb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - SX_BLK_CIPHER_MODE_CFB, key, ciphertext, plaintext, iv); -} - -uint32_t sx_aes_cfb_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CFB, key, plaintext, - ciphertext, iv, ctx_out); -} - -uint32_t sx_aes_cfb_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CFB, key, ciphertext, - plaintext, iv, ctx_out); -} - -uint32_t sx_aes_cfb_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CFB, key, plaintext, - ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_cfb_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CFB, key, ciphertext, - plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_cfb_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - SX_BLK_CIPHER_MODE_CFB, key, plaintext, ciphertext, ctx_in); -} - -uint32_t sx_aes_cfb_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_CFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - SX_BLK_CIPHER_MODE_CFB, key, ciphertext, plaintext, ctx_in); -} - -// AES-OFB -// ----------------------------------------------------------------------------- -uint32_t sx_aes_ofb_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - SX_BLK_CIPHER_MODE_OFB, key, plaintext, ciphertext, iv); -} - -uint32_t sx_aes_ofb_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - SX_BLK_CIPHER_MODE_OFB, key, ciphertext, plaintext, iv); -} - -uint32_t sx_aes_ofb_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_OFB, key, plaintext, - ciphertext, iv, ctx_out); -} - -uint32_t sx_aes_ofb_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_OFB, key, ciphertext, - plaintext, iv, ctx_out); -} - -uint32_t sx_aes_ofb_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_OFB, key, plaintext, - ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ofb_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_OFB, key, ciphertext, - plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ofb_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - SX_BLK_CIPHER_MODE_OFB, key, plaintext, ciphertext, ctx_in); -} - -uint32_t sx_aes_ofb_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in) -{ - if (!AES_HW_CFG_OFB_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - SX_BLK_CIPHER_MODE_OFB, key, ciphertext, plaintext, ctx_in); -} - -// AES-XTS -// ----------------------------------------------------------------------------- -uint32_t sx_aes_xts_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv, key_xts); -} - -uint32_t sx_aes_xts_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv, key_xts); -} - -uint32_t sx_aes_xts_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv, ctx_out, - key_xts); -} - -uint32_t sx_aes_xts_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv, ctx_out, - key_xts); -} - -uint32_t sx_aes_xts_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in, ctx_out, - key_xts); -} - -uint32_t sx_aes_xts_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in, ctx_out, - key_xts); -} - -uint32_t sx_aes_xts_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in, key_xts); -} - -uint32_t sx_aes_xts_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *key_xts) -{ - if (!AES_HW_CFG_XTS_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_xts_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in, key_xts); -} - -// AES-GCM -// ----------------------------------------------------------------------------- -uint32_t sx_aes_gcm_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv, mac, aad); -} - -uint32_t sx_aes_gcm_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv, mac, aad); -} - -uint32_t sx_aes_gcm_decrypt_verify( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_decrypt_verify(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, key, ciphertext, - plaintext, iv, mac, aad); -} - -uint32_t sx_aes_gcm_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *iv, - block_t *ctx_out, - const block_t *aad) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, iv, ctx_out, aad); - -} - -uint32_t sx_aes_gcm_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - block_t *ctx_out, - const block_t *aad) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, iv, ctx_out, aad); -} - -uint32_t sx_aes_gcm_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_gcm_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_gcm_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in, mac, - len_a_c); -} - -uint32_t sx_aes_gcm_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in, mac, - len_a_c); -} - -uint32_t sx_aes_gcm_decrypt_verify_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac, - const block_t *len_a_c) -{ - if (!AES_HW_CFG_GCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_gcm_decrypt_verify_final(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, key, ciphertext, - plaintext, ctx_in, mac, len_a_c); -} - -// AES-CCM -// ----------------------------------------------------------------------------- -uint32_t sx_aes_ccm_encrypt( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_encrypt(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, nonce, mac, aad); -} - -uint32_t sx_aes_ccm_decrypt( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_decrypt(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, nonce, mac, aad); -} - -uint32_t sx_aes_ccm_decrypt_verify( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - const block_t *mac, - const block_t *aad) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_decrypt_verify(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, key, ciphertext, - plaintext, nonce, mac, aad); -} - -uint32_t sx_aes_ccm_encrypt_init( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, nonce, ctx_out, - aad, mac_len, total_length); -} - -uint32_t sx_aes_ccm_decrypt_init( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, nonce, ctx_out, - aad, mac_len, total_length); -} - - -uint32_t sx_aes_ccm_encrypt_update( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, - key, plaintext, ciphertext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ccm_decrypt_update( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, - key, ciphertext, plaintext, ctx_in, ctx_out); -} - -uint32_t sx_aes_ccm_encrypt_final( - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_encrypt_final(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_ENCRYPT, key, plaintext, - ciphertext, ctx_in, mac); -} - -uint32_t sx_aes_ccm_decrypt_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *mac) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_decrypt_final(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, key, ciphertext, - plaintext, ctx_in, mac); -} - -uint32_t sx_aes_ccm_decrypt_verify_final( - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac) -{ - if (!AES_HW_CFG_CCM_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_ccm_decrypt_verify_final(SX_BLK_CIPHER_AES, - SX_BLK_CIPHER_DECRYPT, key, ciphertext, - plaintext, ctx_in, mac); -} - -// AES-CMAC -// ----------------------------------------------------------------------------- -// Whole -uint32_t sx_aes_cmac_generate( - const block_t *key, - const block_t *message, - block_t *mac) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_generate(SX_BLK_CIPHER_AES, key, message, mac); -} - -uint32_t sx_aes_cmac_verify( - const block_t *key, - const block_t *message, - const block_t *mac) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_verify(SX_BLK_CIPHER_AES, key, message, mac); -} - -// Init -uint32_t sx_aes_cmac_generate_init( - const block_t *key, - const block_t *message, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_generate_init(SX_BLK_CIPHER_AES, key, message, - ctx_out); -} - -// Update -uint32_t sx_aes_cmac_generate_update( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *ctx_out) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_generate_update(SX_BLK_CIPHER_AES, key, message, - ctx_in, ctx_out); -} - -// Final -uint32_t sx_aes_cmac_generate_final( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *mac) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_generate_final(SX_BLK_CIPHER_AES, key, message, - ctx_in, mac); -} - -uint32_t sx_aes_cmac_generate_verify_final( - const block_t *key, - const block_t *message, - const block_t *ctx_in, - const block_t *mac) -{ - if (!AES_HW_CFG_CMAC_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_blk_cipher_cmac_generate_verify_final(SX_BLK_CIPHER_AES, key, - message, ctx_in, mac); -} - -void sx_aes_load_mask(uint32_t value) -{ - struct dma_sg_descr_s desc_to; - struct dma_sg_descr_s desc_fr; - - // Fetcher descriptor to store random in AES - write_desc( - &desc_to, - &value, - sizeof(value), - DMA_AXI_DESCR_REALIGN, - DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | - DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_MASK)); - set_last_desc(&desc_to); - - // Dummy pusher descriptor - write_desc_always(&desc_fr, NULL, 0, DMA_AXI_DESCR_REALIGN, 0); - set_last_desc(&desc_fr); - - // RUN - cryptodma_run_sg(&desc_to, &desc_fr); -} +/** + * @file + * @brief Defines the procedures to make operations with + * the BA411E AES + * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved + */ + + +#include +#include +#include //for memset +#include "sx_aes.h" +#include "cryptolib_def.h" +#include "cryptodma_internal.h" +#include "sx_memcpy.h" +#include "sx_memcmp.h" +#include "ba411e_config.h" +#include "sx_math.h" +#include "sx_trng.h" +#include "sx_errors.h" +#include "sx_blk_cipher.h" + +uint8_t aes_hw_key1; +uint8_t aes_hw_key2; + +/** @brief This function is called in sx_blk_cipher.c + * Update fields related to the key characteristics for block cipher + * operation + * + * The block cipher engines have a 32b configuration register with many fields. + * A few of them depends of the block cipher key itself. The function set these + * fields only and let the others unchanged. It allows to decouple key related + * configuration with the algorithm (CBC/ECB,...) and the operation + * (encryption/decryption, ...) + * + * @param key block cipher key involved. + * @param config A 32b word to update based on the \c key characteristics + * @return CRYPTOLIB_SUCCESS if key length is recognised (128 ,192 or 256b) and + * supported. + * CRYPTOLIB_UNSUPPORTED_ERR if key length is recognized but not supported + * CRYPTOLIB_INVALID_PARAM if key length is not recognised. + */ +uint32_t sx_aes_set_hw_config_for_key(block_t *key, uint32_t *config) +{ + // Check and configure for key length + switch(key->len) { + case 16: + if (!AES_HW_CFG_KEY_SIZE_128_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + *config |= SX_BLK_CIPHER_MODEID_128; + break; + case 24: + if (!AES_HW_CFG_KEY_SIZE_192_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + *config |= SX_BLK_CIPHER_MODEID_192; + break; + case 32: + if (!AES_HW_CFG_KEY_SIZE_256_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + *config |= SX_BLK_CIPHER_MODEID_256; + break; + default: + return CRYPTOLIB_INVALID_PARAM; + } + + // Configure to use HW keys + if (key->addr == &aes_hw_key1) { + *config |= SX_BLK_CIPHER_MODEID_KEY1; + key->len = 0; // We don't need to transfer key content when using HW ones + } + else if (key->addr == &aes_hw_key2) { + *config |= SX_BLK_CIPHER_MODEID_KEY2; + key->len = 0; // We don't need to transfer key content when using HW ones + } + return CRYPTOLIB_SUCCESS; +} + +// AES-ECB +// ----------------------------------------------------------------------------- +uint32_t sx_aes_ecb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext) +{ + if (!AES_HW_CFG_ECB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ecb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext); +} + +uint32_t sx_aes_ecb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext) +{ + if (!AES_HW_CFG_ECB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ecb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext); +} + +// AES-CBC +// ----------------------------------------------------------------------------- +uint32_t sx_aes_cbc_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv); +} +uint32_t sx_aes_cbc_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv); +} + +uint32_t sx_aes_cbc_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CBC, key, plaintext, + ciphertext, iv, ctx_out); +} + +uint32_t sx_aes_cbc_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CBC, key, ciphertext, + plaintext, iv, ctx_out); +} + +uint32_t sx_aes_cbc_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CBC, key, plaintext, + ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_cbc_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CBC, key, ciphertext, + plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_cbc_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in); +} + +uint32_t sx_aes_cbc_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CBC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in); +} + +// AES-CTR +// ----------------------------------------------------------------------------- +uint32_t sx_aes_ctr_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ctr(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv); +} + +uint32_t sx_aes_ctr_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ctr(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv); +} + +uint32_t sx_aes_ctr_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CTR, key, plaintext, + ciphertext, iv, ctx_out); +} + +uint32_t sx_aes_ctr_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CTR, key, ciphertext, + plaintext, iv, ctx_out); +} + +uint32_t sx_aes_ctr_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CTR, key, plaintext, + ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ctr_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CTR, key, ciphertext, + plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ctr_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ctr_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in); +} + +uint32_t sx_aes_ctr_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CTR_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ctr_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in); +} + +// AES-CFB +// ----------------------------------------------------------------------------- +uint32_t sx_aes_cfb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + SX_BLK_CIPHER_MODE_CFB, key, plaintext, ciphertext, iv); +} + +uint32_t sx_aes_cfb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + SX_BLK_CIPHER_MODE_CFB, key, ciphertext, plaintext, iv); +} + +uint32_t sx_aes_cfb_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CFB, key, plaintext, + ciphertext, iv, ctx_out); +} + +uint32_t sx_aes_cfb_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CFB, key, ciphertext, + plaintext, iv, ctx_out); +} + +uint32_t sx_aes_cfb_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_CFB, key, plaintext, + ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_cfb_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_CFB, key, ciphertext, + plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_cfb_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + SX_BLK_CIPHER_MODE_CFB, key, plaintext, ciphertext, ctx_in); +} + +uint32_t sx_aes_cfb_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_CFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + SX_BLK_CIPHER_MODE_CFB, key, ciphertext, plaintext, ctx_in); +} + +// AES-OFB +// ----------------------------------------------------------------------------- +uint32_t sx_aes_ofb_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + SX_BLK_CIPHER_MODE_OFB, key, plaintext, ciphertext, iv); +} + +uint32_t sx_aes_ofb_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + SX_BLK_CIPHER_MODE_OFB, key, ciphertext, plaintext, iv); +} + +uint32_t sx_aes_ofb_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_OFB, key, plaintext, + ciphertext, iv, ctx_out); +} + +uint32_t sx_aes_ofb_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_init(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_OFB, key, ciphertext, + plaintext, iv, ctx_out); +} + +uint32_t sx_aes_ofb_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, SX_BLK_CIPHER_MODE_OFB, key, plaintext, + ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ofb_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cbc_ctr_ofb_cfb_update(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, SX_BLK_CIPHER_MODE_OFB, key, ciphertext, + plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ofb_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + SX_BLK_CIPHER_MODE_OFB, key, plaintext, ciphertext, ctx_in); +} + +uint32_t sx_aes_ofb_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in) +{ + if (!AES_HW_CFG_OFB_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cfb_ofb_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + SX_BLK_CIPHER_MODE_OFB, key, ciphertext, plaintext, ctx_in); +} + +// AES-XTS +// ----------------------------------------------------------------------------- +uint32_t sx_aes_xts_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv, key_xts); +} + +uint32_t sx_aes_xts_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv, key_xts); +} + +uint32_t sx_aes_xts_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv, ctx_out, + key_xts); +} + +uint32_t sx_aes_xts_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv, ctx_out, + key_xts); +} + +uint32_t sx_aes_xts_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in, ctx_out, + key_xts); +} + +uint32_t sx_aes_xts_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in, ctx_out, + key_xts); +} + +uint32_t sx_aes_xts_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in, key_xts); +} + +uint32_t sx_aes_xts_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *key_xts) +{ + if (!AES_HW_CFG_XTS_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_xts_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in, key_xts); +} + +// AES-GCM +// ----------------------------------------------------------------------------- +uint32_t sx_aes_gcm_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv, mac, aad); +} + +uint32_t sx_aes_gcm_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv, mac, aad); +} + +uint32_t sx_aes_gcm_decrypt_verify( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_decrypt_verify(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, key, ciphertext, + plaintext, iv, mac, aad); +} + +uint32_t sx_aes_gcm_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *iv, + block_t *ctx_out, + const block_t *aad) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, iv, ctx_out, aad); + +} + +uint32_t sx_aes_gcm_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + block_t *ctx_out, + const block_t *aad) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, iv, ctx_out, aad); +} + +uint32_t sx_aes_gcm_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_gcm_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_gcm_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in, mac, + len_a_c); +} + +uint32_t sx_aes_gcm_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_final(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in, mac, + len_a_c); +} + +uint32_t sx_aes_gcm_decrypt_verify_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac, + const block_t *len_a_c) +{ + if (!AES_HW_CFG_GCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_gcm_decrypt_verify_final(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, key, ciphertext, + plaintext, ctx_in, mac, len_a_c); +} + +// AES-CCM +// ----------------------------------------------------------------------------- +uint32_t sx_aes_ccm_encrypt( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_encrypt(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, nonce, mac, aad); +} + +uint32_t sx_aes_ccm_decrypt( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_decrypt(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, nonce, mac, aad); +} + +uint32_t sx_aes_ccm_decrypt_verify( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + const block_t *mac, + const block_t *aad) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_decrypt_verify(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, key, ciphertext, + plaintext, nonce, mac, aad); +} + +uint32_t sx_aes_ccm_encrypt_init( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, nonce, ctx_out, + aad, mac_len, total_length); +} + +uint32_t sx_aes_ccm_decrypt_init( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_init(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, nonce, ctx_out, + aad, mac_len, total_length); +} + + +uint32_t sx_aes_ccm_encrypt_update( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_ENCRYPT, + key, plaintext, ciphertext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ccm_decrypt_update( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_update(SX_BLK_CIPHER_AES, SX_BLK_CIPHER_DECRYPT, + key, ciphertext, plaintext, ctx_in, ctx_out); +} + +uint32_t sx_aes_ccm_encrypt_final( + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_encrypt_final(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_ENCRYPT, key, plaintext, + ciphertext, ctx_in, mac); +} + +uint32_t sx_aes_ccm_decrypt_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *mac) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_decrypt_final(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, key, ciphertext, + plaintext, ctx_in, mac); +} + +uint32_t sx_aes_ccm_decrypt_verify_final( + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac) +{ + if (!AES_HW_CFG_CCM_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_ccm_decrypt_verify_final(SX_BLK_CIPHER_AES, + SX_BLK_CIPHER_DECRYPT, key, ciphertext, + plaintext, ctx_in, mac); +} + +// AES-CMAC +// ----------------------------------------------------------------------------- +// Whole +uint32_t sx_aes_cmac_generate( + const block_t *key, + const block_t *message, + block_t *mac) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_generate(SX_BLK_CIPHER_AES, key, message, mac); +} + +uint32_t sx_aes_cmac_verify( + const block_t *key, + const block_t *message, + const block_t *mac) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_verify(SX_BLK_CIPHER_AES, key, message, mac); +} + +// Init +uint32_t sx_aes_cmac_generate_init( + const block_t *key, + const block_t *message, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_generate_init(SX_BLK_CIPHER_AES, key, message, + ctx_out); +} + +// Update +uint32_t sx_aes_cmac_generate_update( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *ctx_out) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_generate_update(SX_BLK_CIPHER_AES, key, message, + ctx_in, ctx_out); +} + +// Final +uint32_t sx_aes_cmac_generate_final( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *mac) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_generate_final(SX_BLK_CIPHER_AES, key, message, + ctx_in, mac); +} + +uint32_t sx_aes_cmac_generate_verify_final( + const block_t *key, + const block_t *message, + const block_t *ctx_in, + const block_t *mac) +{ + if (!AES_HW_CFG_CMAC_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_blk_cipher_cmac_generate_verify_final(SX_BLK_CIPHER_AES, key, + message, ctx_in, mac); +} + +void sx_aes_load_mask(uint32_t value) +{ + struct dma_sg_descr_s desc_to; + struct dma_sg_descr_s desc_fr; + + // Fetcher descriptor to store random in AES + write_desc( + &desc_to, + &value, + sizeof(value), + DMA_AXI_DESCR_REALIGN, + DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | + DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_MASK)); + set_last_desc(&desc_to); + + // Dummy pusher descriptor + write_desc_always(&desc_fr, NULL, 0, DMA_AXI_DESCR_REALIGN, 0); + set_last_desc(&desc_fr); + + // RUN + cryptodma_run_sg(&desc_to, &desc_fr); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c index ff0335b..a8c32a5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c @@ -1,1387 +1,1387 @@ -/** - * @file - * @brief Defines the procedures to make operations with block ciphers engines: - * BA411E-AES - * @copyright Copyright (c) 2019-2020 Silex Insight. All Rights reserved - */ - -#include -#include //for memset -#include -#include "sx_aes.h" -#include "ba411e_config.h" -#include "cryptolib_def.h" -#include "cryptodma_internal.h" -#include "sx_memcpy.h" -#include "sx_memcmp.h" -#include "sx_math.h" -#include "sx_trng.h" -#include "sx_errors.h" -#include "sx_blk_cipher.h" - -extern uint32_t sx_aes_set_hw_config_for_key(block_t *key, uint32_t *config); - -const uint32_t engine_select[SX_NUM_BLK_CIPHER_ENGINES] = { - DMA_SG_ENGINESELECT_BA411E, -}; - -const uint32_t operation_select[SX_NUM_BLK_CIPHER_OPERATIONS] = { - SX_BLK_CIPHER_MODEID_ENCRYPT, - SX_BLK_CIPHER_MODEID_DECRYPT}; - -const uint32_t mode_select[SX_NUM_BLK_CIPHER_MODES] = { - SX_BLK_CIPHER_MODEID_ECB, - SX_BLK_CIPHER_MODEID_CBC, - SX_BLK_CIPHER_MODEID_CTR, - SX_BLK_CIPHER_MODEID_CFB, - SX_BLK_CIPHER_MODEID_OFB, - SX_BLK_CIPHER_MODEID_CCM, - SX_BLK_CIPHER_MODEID_GCM, - SX_BLK_CIPHER_MODEID_XTS, - SX_BLK_CIPHER_MODEID_CMA}; - -/* Number of descriptors used for pushing data to block cipher engine */ -#define DESC_N_TO_ENGINE 8 - -/* Number of descriptors used for fetching data from block cipher engine */ -#define DESC_N_FROM_ENGINE 6 - -uint32_t generate_ccm_header( - block_t nonce, - uint32_t aad_len, - uint32_t data_len, - uint32_t tag_len, - block_t *header); - -static uint32_t sx_blk_cipher_build_descr( - enum sx_blk_cipher_engine_select engine, - uint32_t hw_config, - const block_t *key, - const block_t *xtskey, - const block_t *iv, - const block_t *datain, - block_t *dataout, - const block_t *aad1, - const block_t *aad2, - const block_t *extrain, - block_t *tag_out, - block_t *ctx_ptr); - -bool is_len_valid_for_cbc_xts(enum sx_blk_cipher_engine_select engine, uint32_t len) -{ - if(SX_BLK_CIPHER_AES == engine) - if (AES_HW_CFG_CS_EN) - return len >= BLK_CIPHER_BLOCK_SIZE; - return !(len % BLK_CIPHER_BLOCK_SIZE) && (len > 0); -} - -// ECB -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_ecb( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout) -{ - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len)) - return CRYPTOLIB_INVALID_PARAM; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_ECB; - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -// CBC -CTR -OFB -CFB -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv, - block_t *ctx_out) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); - uint32_t config = operation_select[operation] | mode_select[mode] - | SX_BLK_CIPHER_MODEID_CX_SAVE; - - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (iv->len != BLK_CIPHER_IV_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - block_t *ctx_out) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); - uint32_t config = operation_select[operation] | mode_select[mode] - | SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -// CBC -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_cbc( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv) -{ - if (!is_len_valid_for_cbc_xts(engine, datain->len) || - (dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CBC; - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -uint32_t sx_blk_cipher_cbc_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CBC | - SX_BLK_CIPHER_MODEID_CX_LOAD; - if (!is_len_valid_for_cbc_xts(engine, datain->len) || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -// CTR -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_ctr( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CTR; - - if (!datain->len || dataout->len != datain->len || iv->len != BLK_CIPHER_IV_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - - -uint32_t sx_blk_cipher_ctr_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CTR | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if (! datain->len || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -// CFB-OFB -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_cfb_ofb( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv) -{ - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (iv->len != BLK_CIPHER_IV_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); - uint32_t config = operation_select[operation] | mode_select[mode]; - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -uint32_t sx_blk_cipher_cfb_ofb_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); - uint32_t config = operation_select[operation] | mode_select[mode] - | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -// XTS -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_xts( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv, - const block_t *key_xts) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS; - - if (!is_len_valid_for_cbc_xts(engine, datain->len) || - dataout->len != datain->len || (iv->len != BLK_CIPHER_IV_SIZE) || - (key->len != key_xts->len)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - key_xts, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -uint32_t sx_blk_cipher_xts_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | - SX_BLK_CIPHER_MODEID_CX_SAVE; - - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (iv->len != BLK_CIPHER_IV_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE) || - (key->len != key_xts->len)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - key_xts, - iv, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_xts_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | - SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE) || - (key->len != key_xts->len)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - key_xts, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_xts_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - const block_t *key_xts) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if (!is_len_valid_for_cbc_xts(engine, datain->len) || (dataout->len != datain->len) || - (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (key->len != key_xts->len)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - key_xts, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, &dummy); -} - -// GCM -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_gcm( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv, - block_t *mac, - const block_t *aad) -{ - if ((dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_GCM_SIZE) || - (mac->len != BLK_CIPHER_MAC_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM; - - // Compute len(AAD) + len(data) - uint8_t len_a_c_buff[16]; - block_t len_a_c = BLK_LITARRAY(len_a_c_buff); - sx_math_u64_to_u8array(aad->len << 3, &len_a_c_buff[0], sx_big_endian); - sx_math_u64_to_u8array(datain->len << 3, &len_a_c_buff[8], sx_big_endian); - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, - aad, - &len_a_c, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_gcm_decrypt_verify( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *mac, - const block_t *aad) -{ - if ((mac->len < 4) || (mac->len > BLK_CIPHER_MAC_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t mac_recomputed_buf[BLK_CIPHER_MAC_SIZE] = {0}; - block_t mac_recomputed = block_t_convert( - mac_recomputed_buf, sizeof(mac_recomputed_buf)); - uint32_t status = sx_blk_cipher_gcm(engine, operation, key, ciphertext, - plaintext, iv, &mac_recomputed, aad); - if (status) - return status; - - if (memcmp_time_cst(mac->addr, mac_recomputed_buf, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -uint32_t sx_blk_cipher_gcm_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *iv, - block_t *ctx_out, - const block_t *aad) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | - SX_BLK_CIPHER_MODEID_CX_SAVE; - - if ((dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_GCM_SIZE) || - (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - iv, - datain, - dataout, - &dummy, - aad, - &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_gcm_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - block_t *ctx_out) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | - SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((dataout->len != datain->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || - (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_gcm_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((dataout->len != datain->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || - (mac->len != BLK_CIPHER_MAC_SIZE) || (len_a_c->len != 16)) // TODO Use nice names - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, - len_a_c, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_gcm_decrypt_verify_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac, - const block_t *len_a_c) -{ - if ((mac->len < 4) || (mac->len > BLK_CIPHER_MAC_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t mac_recomputed_buf[BLK_CIPHER_MAC_SIZE] = {0}; - block_t mac_recomputed = block_t_convert( - mac_recomputed_buf, sizeof(mac_recomputed_buf)); - - uint32_t status = sx_blk_cipher_gcm_final( - engine, - operation, - key, - ciphertext, - plaintext, - ctx_in, - &mac_recomputed, - len_a_c); - if (status) - return status; - - if (memcmp_time_cst(mac->addr, mac_recomputed_buf, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -// CCM -// ----------------------------------------------------------------------------- -uint32_t sx_blk_cipher_ccm_encrypt( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *mac, - const block_t *aad) -{ - if (plaintext->len != ciphertext->len) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t header_generated[22]; // Maximum header size (excluding aad which will be transferred directly) - block_t header = BLK_LITARRAY(header_generated); - uint32_t status = generate_ccm_header(*nonce, aad->len, plaintext->len, mac->len, &header); - if (status) - return status; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM; - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - plaintext, - ciphertext, - &header, - aad, - &dummy, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_ccm_decrypt( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - block_t *mac, - const block_t *aad) -{ - if (ciphertext->len != plaintext->len) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t header_generated[22]; // Maximum header size (excluding aad2 which will be transferred directly) - block_t header = BLK_LITARRAY(header_generated); - uint32_t status = generate_ccm_header(*nonce, aad->len, ciphertext->len, - mac->len, &header); - if (status) - return status; - - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM; - block_t dummy = NULL_blk; - - /* In BA411E, CCM is implemented in a different way than GCM; it is not - * possible to directly read back the recomputed MAC from the BA411E. - * The reference MAC is xor-ed internally with the recomputed one. - * Sending 0,...,0 in place of the reference will return the recomputed MAC - * as A xor 0 = A. - */ - uint8_t zeroes_buf[BLK_CIPHER_MAC_SIZE] = {0}; - block_t zeroes = block_t_convert(zeroes_buf, mac->len); - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - ciphertext, - plaintext, - &header, - aad, - &zeroes, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_ccm_decrypt_verify( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - const block_t *mac, - const block_t *aad) -{ - uint8_t mac_buf[BLK_CIPHER_MAC_SIZE]; - block_t mac_recomputed = block_t_convert(mac_buf, mac->len); - uint32_t status = sx_blk_cipher_ccm_decrypt( - engine, - operation, - key, - ciphertext, - plaintext, - nonce, - &mac_recomputed, - aad); - if (status) - return status; - - if (memcmp_time_cst(mac->addr, mac_buf, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -uint32_t sx_blk_cipher_ccm_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | - SX_BLK_CIPHER_MODEID_CX_SAVE; - - if ((datain->len != dataout->len) || (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t header_generated[22]; // Maximum header size (excluding aad which will be transferred directly) - block_t header = BLK_LITARRAY(header_generated); - uint32_t status = generate_ccm_header(*nonce, aad->len, total_length, mac_len, &header); - if (status) - return status; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - datain, - dataout, - &header, - aad, - &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_ccm_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in, - block_t *ctx_out) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | - SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((datain->len != dataout->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || - (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - datain, - dataout, - &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -uint32_t sx_blk_cipher_ccm_encrypt_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((plaintext->len != ciphertext->len) || - (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - /* Variant of CCM with disabled authenticity is supported: CCM* - * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see - * https://tools.ietf.org/html/rfc3610 for CCM and - * B.4 Specification of generic CCM* mode of operation from - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * for CCM* - */ - if ((mac->len % 2 != 0) || (mac->len == 2) || mac->len > BLK_CIPHER_MAC_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - plaintext, - ciphertext, - &dummy, &dummy, &dummy, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_ccm_decrypt_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - block_t *mac) -{ - CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); - uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((plaintext->len != ciphertext->len) || - (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - /* Variant of CCM with disabled authenticity is supported: CCM* - * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see - * https://tools.ietf.org/html/rfc3610 for CCM and - * B.4 Specification of generic CCM* mode of operation from - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * for CCM* - */ - if ((mac->len % 2 != 0) || (mac->len == 2) || mac->len > BLK_CIPHER_MAC_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - /* CCM is implemented in a different way that GCM; it is not possible to - * directly read back the recomputed MAC from the BA411E. - * The reference MAC is xor-ed internally with the recomputed one. - * Sending 0,...,0 in place of the reference will return the recomputed MAC - * as A xor 0 = A. - */ - uint8_t zeroes_buf[BLK_CIPHER_MAC_SIZE] = {0}; - block_t zeroes = block_t_convert(zeroes_buf, mac->len); - block_t dummy = NULL_blk; - block_t extrain = dummy; - if (engine == SX_BLK_CIPHER_AES) - extrain = zeroes; - - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - ciphertext, - plaintext, - &dummy, &dummy, - &extrain, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_ccm_decrypt_verify_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac) -{ - uint8_t mac_buf[BLK_CIPHER_MAC_SIZE]; - block_t mac_recomputed = block_t_convert(mac_buf, mac->len); - uint32_t status = sx_blk_cipher_ccm_decrypt_final( - engine, - operation, - key, - ciphertext, - plaintext, - ctx_in, - &mac_recomputed); - if (status) - return status; - - if (memcmp_time_cst(mac->addr, mac_buf, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -// CMAC -// ----------------------------------------------------------------------------- -// Whole -uint32_t sx_blk_cipher_cmac_generate( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - block_t *mac) -{ - if (mac->len != BLK_CIPHER_MAC_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT; - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - message, - &dummy, &dummy, &dummy, &dummy, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_cmac_verify( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *mac) -{ - if (mac->len > BLK_CIPHER_MAC_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t recomputed_buf[BLK_CIPHER_MAC_SIZE]; - block_t recomputed = BLK_LITARRAY(recomputed_buf); - - uint32_t status = sx_blk_cipher_cmac_generate(engine, key, message, - &recomputed); - if (status) - return status; - - if (memcmp_time_cst(recomputed_buf, mac->addr, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -// Init -uint32_t sx_blk_cipher_cmac_generate_init( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - block_t *ctx_out) -{ - uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | - SX_BLK_CIPHER_MODEID_CX_SAVE; - - if (ctx_out->len != BLK_CIPHER_CTX_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, &dummy, - message, - &dummy, &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -// Update -uint32_t sx_blk_cipher_cmac_generate_update( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *ctx_out) -{ - uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | - SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((ctx_in->len != BLK_CIPHER_CTX_SIZE) || - (ctx_out->len != BLK_CIPHER_CTX_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - message, - &dummy, &dummy, &dummy, &dummy, &dummy, - ctx_out); -} - -// Final -uint32_t sx_blk_cipher_cmac_generate_final( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *mac) -{ - uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | - SX_BLK_CIPHER_MODEID_CX_LOAD; - - if ((ctx_in->len != BLK_CIPHER_CTX_SIZE) || (mac->len != BLK_CIPHER_MAC_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - block_t dummy = NULL_blk; - return sx_blk_cipher_build_descr( - engine, - config, - key, - &dummy, - ctx_in, - message, - &dummy, &dummy, &dummy, &dummy, - mac, - &dummy); -} - -uint32_t sx_blk_cipher_cmac_generate_verify_final( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - const block_t *mac) -{ - if (mac->len != BLK_CIPHER_MAC_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t recomputed_buf[BLK_CIPHER_MAC_SIZE]; - block_t recomputed = BLK_LITARRAY(recomputed_buf); - - uint32_t status = sx_blk_cipher_cmac_generate_final(engine, key, message, - ctx_in, &recomputed); - if (status) - return status; - - if (memcmp_time_cst(recomputed_buf, mac->addr, mac->len)) - return CRYPTOLIB_INVALID_SIGN_ERR; - return CRYPTOLIB_SUCCESS; -} - -/** - * @brief block cipher generate CCM header - * Create the header of CCM data based on lengths, nonce & aad2 - * - * @param nonce The Nonce - * @param aad_len The length of additional data to authenticate - * @param data_len The length of the data (plaintext or cipher) in bytes - * @param tag_len The length of the MAC in bytes - * @param header Pointer to the output header block - * @return CRYPTOLIB_SUCCESS if execution was successful - */ -uint32_t generate_ccm_header(block_t nonce, uint32_t aad_len, uint32_t data_len, - uint32_t tag_len, block_t *header) -{ - uint32_t flags; - uint32_t m, l; - uint32_t i; - - /* RFC3610 paragraph 2.2 defines the formatting of the first block. - * Thee first block contains: - * byte [0] the flags byte (see below) - * bytes [1,1+nonce.len] nonce - * bytes [2+nonce.len, 16] message length - * - * The flags byte has the following bit fields: - * [6:7] = 0 - * [3:5] = authentication tag size, encoded as (tag_len-2)/2 - * only multiples of 2 between 2 and 16 are allowed. - * [0:2] = length field size minus 1. Is the same as (15 - nonce.len - 1) - * between 2 and 8. - **/ - - /* Verify input parameters - * - * Variant of CCM with disabled authenticity is supported: CCM* - * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see - * https://tools.ietf.org/html/rfc3610 for CCM and - * B.4 Specification of generic CCM* mode of operation from - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * for CCM* - */ - if ((tag_len & 1) || (tag_len == 2) || (tag_len > BLK_CIPHER_MAC_SIZE)) - return CRYPTOLIB_INVALID_PARAM; - - /* The conditions below translate into (l > 8) || (l < 2) which match the - * specification "The parameter L can take on the values from 2 to 8" - */ - if ((nonce.len < 7) || (nonce.len > 13)) - return CRYPTOLIB_INVALID_PARAM; - - flags = (aad_len > 0) ? (1 << 6) : 0; - /* Authentication tag size encoding. A tag_len = 0 is accepted by CCM* and - * that will be encoded as a 0. */ - m = (tag_len > 0) ? (tag_len-2)/2 : 0; - flags |= (m & 0x7) << 3; - l = 15 - nonce.len; - flags |= ((l-1) & 0x7); - header->addr[0] = flags; - - /* If l >= 4, data_len will always fit as it is an uint32_t, we need to - * check only in case l < 4: */ - if (l < 4U && data_len >= (1U << (l * 8))) { - /* message too long to encode the size in the CCM header */ - return CRYPTOLIB_INVALID_PARAM; - } - - memcpy_blkIn(&header->addr[1], nonce, nonce.len); - - /* append message length in big endian format encoded l octets*/ - memset(&(header->addr[1 + nonce.len]), 0, l); - for (i = 0; i < sizeof(data_len); i++) { - if (data_len >= (1U << (i * 8))) - header->addr[15 - i] = (data_len >> (i * 8)) & 0xff; - else - break; - } - - /* if there's additional authentication data (or aad2), - * encode the size: - * - * 0 < aad_len < 0xFF00 => 2 bytes in big endian format. - * 0xFF00 < aad_len < 2^32 => 0xff, 0xfe, and four bytes in big endian format. - * eSecure currently does not support sizes bigger than 2^32. - */ - if (aad_len > 0) { - if (aad_len < 0xFF00) { - header->addr[16] = aad_len >> 8; - header->addr[17] = aad_len & 0xff; - header->len = 18; - } else { - // TODO: Test following case - header->addr[16] = 0xFF; - header->addr[17] = 0xFE; - header->addr[18] = aad_len >> 24; - header->addr[19] = (aad_len >> 16) & 0xff; - header->addr[20] = (aad_len >> 8) & 0xff; - header->addr[21] = aad_len & 0xff; - header->len = 22; - } - } else { - header->len = 16; - } - - return CRYPTOLIB_SUCCESS; -} - -/** - * @brief Get block cipher padding length (realign on block cipher block size) - * @param input_length input length - * @return length of padding - */ -uint32_t get_pad_len(uint32_t input_length) -{ - return (16-input_length)&15; -} - -/** - * @brief Build descriptors and call cryptoDMA for block cipher operation - * @param engine selected engine to be used as block cipher - * @param config value for cfg mode register - * @param key block cipher key - * @param xtskey XTS key. - * @param iv initialization vector - * @param datain input data (plaintext or ciphertext) - * @param dataout output data (ciphertext or plaintext) - * @param aad1 additional authenticated data part #1 - * @param aad2 additional authenticated data part #2 - * @param extrain additional input data expected by ::GCM or ::CCM - * @param tag_out authentication tag input for ::CCM, ::GCM & ::CMAC - * @param ctx_ptr block cipher context output - * @return CRYPTOLIB_SUCCESS when execution was successful - */ -static uint32_t sx_blk_cipher_build_descr( - enum sx_blk_cipher_engine_select engine, - uint32_t hw_config, - const block_t *key, - const block_t *xtskey, - const block_t *iv, - const block_t *datain, - block_t *dataout, - const block_t *aad1, - const block_t *aad2, - const block_t *extrain, - block_t *tag_out, - block_t *ctx_ptr) -{ - block_t config = block_t_convert(&hw_config, sizeof(hw_config)); - block_t keyb = *key; - CRYPTOLIB_ASSERT(engine < SX_NUM_BLK_CIPHER_ENGINES, "Invalid engine"); - uint32_t status = sx_aes_set_hw_config_for_key(&keyb, &hw_config); - if (status) - return status; - - struct dma_sg_descr_s desc_to[DESC_N_TO_ENGINE]; //could be reduces as no use case where all inputs are used, but safer like this - struct dma_sg_descr_s desc_fr[DESC_N_FROM_ENGINE]; - struct dma_sg_descr_s *d; // pointer to current descriptor - block_t datainb = *datain; - // input padding - uint32_t aad_zeropad_len = get_pad_len(aad1->len + aad2->len); - uint32_t datain_zeropad_len = get_pad_len(datain->len); - uint32_t extrain_zeropad_len = get_pad_len(extrain->len); - - // handle alignment for data out - if(dataout->flags & DMA_AXI_DESCR_CONST_ADDR) - dataout->len = roundup_32(dataout->len); - - if(tag_out->flags & DMA_AXI_DESCR_CONST_ADDR) - tag_out->len = roundup_32(tag_out->len); - - // output discards - block_t aads_discard = block_t_convert(NULL, aad1->len + aad2->len + aad_zeropad_len); - block_t dataout_discard = block_t_convert(NULL, get_pad_len(dataout->len)); - block_t tagout_discard = block_t_convert(NULL, get_pad_len(tag_out->len)); - - // no input provided, -> empty input = 1 block of zero padding (i.e. for CMAC) - uint8_t zeroes[16] = {0}; - if (!datain->len && !extrain->len && !aad1->len && !aad2->len ) { - datain_zeropad_len = 16; - datainb = block_t_convert(zeroes, datain_zeropad_len); - } - - // fetcher descriptors - d = desc_to; - // Config - d = write_desc_blk( - d, - &config, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISCONFIG | - DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_CFG)); - - // Symmetric key - d = write_desc_blk( - d, - &keyb, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISCONFIG | - DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_KEY)); - - // IV or context (if existing) - d = write_desc_blk( - d, - iv, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISCONFIG | - DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_IV)); - - // XTS key (if existing) - d = write_desc_blk( - d, - xtskey, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISCONFIG | - DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_KEY2)); - - // authentication data (if existing) - d = write_desc_blk( - d, - aad1, - 0, - engine_select[engine] | DMA_SG_TAG_ISDATA | - DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER); - d = write_desc_blk( - d, - aad2, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISDATA | - DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER | - DMA_SG_TAG_SETINVALIDBYTES(aad_zeropad_len)); - - // Input data (if existing) - d = write_desc_blk( - d, - &datainb, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISDATA | - DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD | - DMA_SG_TAG_SETINVALIDBYTES(datain_zeropad_len)); - - // Additional input data (may be tag_in for CCM or len_a_c for GCM) - d = write_desc_blk( - d, - extrain, - DMA_AXI_DESCR_REALIGN, - engine_select[engine] | DMA_SG_TAG_ISDATA | - DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD | - DMA_SG_TAG_SETINVALIDBYTES(extrain_zeropad_len)); - - set_last_desc(d - 1); - - // pusher descriptors - d = desc_fr; - - // discard output aad and associated padding - d = write_desc_blk(d, &aads_discard, 0, 0); - - // Output data - d = write_desc_blk(d, dataout, 0, 0); - d = write_desc_blk(d, &dataout_discard, 0, 0); - - // Output tag (if existing) - d = write_desc_blk(d, tag_out, 0, 0); - d = write_desc_blk(d, &tagout_discard, 0, 0); - - // Output context (if existing) - d = write_desc_blk(d, ctx_ptr, 0, 0); - - set_last_desc(d - 1); - - // launch cryptodma - cryptodma_run_sg(desc_to, desc_fr); - - return CRYPTOLIB_SUCCESS; -} +/** + * @file + * @brief Defines the procedures to make operations with block ciphers engines: + * BA411E-AES + * @copyright Copyright (c) 2019-2020 Silex Insight. All Rights reserved + */ + +#include +#include //for memset +#include +#include "sx_aes.h" +#include "ba411e_config.h" +#include "cryptolib_def.h" +#include "cryptodma_internal.h" +#include "sx_memcpy.h" +#include "sx_memcmp.h" +#include "sx_math.h" +#include "sx_trng.h" +#include "sx_errors.h" +#include "sx_blk_cipher.h" + +extern uint32_t sx_aes_set_hw_config_for_key(block_t *key, uint32_t *config); + +const uint32_t engine_select[SX_NUM_BLK_CIPHER_ENGINES] = { + DMA_SG_ENGINESELECT_BA411E, +}; + +const uint32_t operation_select[SX_NUM_BLK_CIPHER_OPERATIONS] = { + SX_BLK_CIPHER_MODEID_ENCRYPT, + SX_BLK_CIPHER_MODEID_DECRYPT}; + +const uint32_t mode_select[SX_NUM_BLK_CIPHER_MODES] = { + SX_BLK_CIPHER_MODEID_ECB, + SX_BLK_CIPHER_MODEID_CBC, + SX_BLK_CIPHER_MODEID_CTR, + SX_BLK_CIPHER_MODEID_CFB, + SX_BLK_CIPHER_MODEID_OFB, + SX_BLK_CIPHER_MODEID_CCM, + SX_BLK_CIPHER_MODEID_GCM, + SX_BLK_CIPHER_MODEID_XTS, + SX_BLK_CIPHER_MODEID_CMA}; + +/* Number of descriptors used for pushing data to block cipher engine */ +#define DESC_N_TO_ENGINE 8 + +/* Number of descriptors used for fetching data from block cipher engine */ +#define DESC_N_FROM_ENGINE 6 + +uint32_t generate_ccm_header( + block_t nonce, + uint32_t aad_len, + uint32_t data_len, + uint32_t tag_len, + block_t *header); + +static uint32_t sx_blk_cipher_build_descr( + enum sx_blk_cipher_engine_select engine, + uint32_t hw_config, + const block_t *key, + const block_t *xtskey, + const block_t *iv, + const block_t *datain, + block_t *dataout, + const block_t *aad1, + const block_t *aad2, + const block_t *extrain, + block_t *tag_out, + block_t *ctx_ptr); + +bool is_len_valid_for_cbc_xts(enum sx_blk_cipher_engine_select engine, uint32_t len) +{ + if(SX_BLK_CIPHER_AES == engine) + if (AES_HW_CFG_CS_EN) + return len >= BLK_CIPHER_BLOCK_SIZE; + return !(len % BLK_CIPHER_BLOCK_SIZE) && (len > 0); +} + +// ECB +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_ecb( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout) +{ + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len)) + return CRYPTOLIB_INVALID_PARAM; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_ECB; + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +// CBC -CTR -OFB -CFB +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv, + block_t *ctx_out) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); + uint32_t config = operation_select[operation] | mode_select[mode] + | SX_BLK_CIPHER_MODEID_CX_SAVE; + + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (iv->len != BLK_CIPHER_IV_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + block_t *ctx_out) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); + uint32_t config = operation_select[operation] | mode_select[mode] + | SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +// CBC +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_cbc( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv) +{ + if (!is_len_valid_for_cbc_xts(engine, datain->len) || + (dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CBC; + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +uint32_t sx_blk_cipher_cbc_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CBC | + SX_BLK_CIPHER_MODEID_CX_LOAD; + if (!is_len_valid_for_cbc_xts(engine, datain->len) || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +// CTR +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_ctr( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CTR; + + if (!datain->len || dataout->len != datain->len || iv->len != BLK_CIPHER_IV_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + + +uint32_t sx_blk_cipher_ctr_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CTR | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if (! datain->len || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +// CFB-OFB +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_cfb_ofb( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv) +{ + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (iv->len != BLK_CIPHER_IV_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); + uint32_t config = operation_select[operation] | mode_select[mode]; + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +uint32_t sx_blk_cipher_cfb_ofb_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + CRYPTOLIB_ASSERT_NM(mode < SX_NUM_BLK_CIPHER_MODES); + uint32_t config = operation_select[operation] | mode_select[mode] + | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +// XTS +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_xts( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv, + const block_t *key_xts) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS; + + if (!is_len_valid_for_cbc_xts(engine, datain->len) || + dataout->len != datain->len || (iv->len != BLK_CIPHER_IV_SIZE) || + (key->len != key_xts->len)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + key_xts, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +uint32_t sx_blk_cipher_xts_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | + SX_BLK_CIPHER_MODEID_CX_SAVE; + + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (iv->len != BLK_CIPHER_IV_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE) || + (key->len != key_xts->len)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + key_xts, + iv, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_xts_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | + SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((datain->len % 16) || !datain->len || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (ctx_out->len != BLK_CIPHER_CTX_SIZE) || + (key->len != key_xts->len)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + key_xts, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_xts_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + const block_t *key_xts) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_XTS | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if (!is_len_valid_for_cbc_xts(engine, datain->len) || (dataout->len != datain->len) || + (ctx_in->len != BLK_CIPHER_CTX_SIZE) || (key->len != key_xts->len)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + key_xts, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, &dummy); +} + +// GCM +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_gcm( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv, + block_t *mac, + const block_t *aad) +{ + if ((dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_GCM_SIZE) || + (mac->len != BLK_CIPHER_MAC_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM; + + // Compute len(AAD) + len(data) + uint8_t len_a_c_buff[16]; + block_t len_a_c = BLK_LITARRAY(len_a_c_buff); + sx_math_u64_to_u8array(aad->len << 3, &len_a_c_buff[0], sx_big_endian); + sx_math_u64_to_u8array(datain->len << 3, &len_a_c_buff[8], sx_big_endian); + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, + aad, + &len_a_c, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_gcm_decrypt_verify( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *mac, + const block_t *aad) +{ + if ((mac->len < 4) || (mac->len > BLK_CIPHER_MAC_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t mac_recomputed_buf[BLK_CIPHER_MAC_SIZE] = {0}; + block_t mac_recomputed = block_t_convert( + mac_recomputed_buf, sizeof(mac_recomputed_buf)); + uint32_t status = sx_blk_cipher_gcm(engine, operation, key, ciphertext, + plaintext, iv, &mac_recomputed, aad); + if (status) + return status; + + if (memcmp_time_cst(mac->addr, mac_recomputed_buf, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +uint32_t sx_blk_cipher_gcm_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *iv, + block_t *ctx_out, + const block_t *aad) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | + SX_BLK_CIPHER_MODEID_CX_SAVE; + + if ((dataout->len != datain->len) || (iv->len != BLK_CIPHER_IV_GCM_SIZE) || + (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + iv, + datain, + dataout, + &dummy, + aad, + &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_gcm_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + block_t *ctx_out) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | + SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((dataout->len != datain->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || + (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_gcm_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_GCM | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((dataout->len != datain->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || + (mac->len != BLK_CIPHER_MAC_SIZE) || (len_a_c->len != 16)) // TODO Use nice names + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, + len_a_c, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_gcm_decrypt_verify_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac, + const block_t *len_a_c) +{ + if ((mac->len < 4) || (mac->len > BLK_CIPHER_MAC_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t mac_recomputed_buf[BLK_CIPHER_MAC_SIZE] = {0}; + block_t mac_recomputed = block_t_convert( + mac_recomputed_buf, sizeof(mac_recomputed_buf)); + + uint32_t status = sx_blk_cipher_gcm_final( + engine, + operation, + key, + ciphertext, + plaintext, + ctx_in, + &mac_recomputed, + len_a_c); + if (status) + return status; + + if (memcmp_time_cst(mac->addr, mac_recomputed_buf, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +// CCM +// ----------------------------------------------------------------------------- +uint32_t sx_blk_cipher_ccm_encrypt( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *mac, + const block_t *aad) +{ + if (plaintext->len != ciphertext->len) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t header_generated[22]; // Maximum header size (excluding aad which will be transferred directly) + block_t header = BLK_LITARRAY(header_generated); + uint32_t status = generate_ccm_header(*nonce, aad->len, plaintext->len, mac->len, &header); + if (status) + return status; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM; + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + plaintext, + ciphertext, + &header, + aad, + &dummy, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_ccm_decrypt( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + block_t *mac, + const block_t *aad) +{ + if (ciphertext->len != plaintext->len) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t header_generated[22]; // Maximum header size (excluding aad2 which will be transferred directly) + block_t header = BLK_LITARRAY(header_generated); + uint32_t status = generate_ccm_header(*nonce, aad->len, ciphertext->len, + mac->len, &header); + if (status) + return status; + + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM; + block_t dummy = NULL_blk; + + /* In BA411E, CCM is implemented in a different way than GCM; it is not + * possible to directly read back the recomputed MAC from the BA411E. + * The reference MAC is xor-ed internally with the recomputed one. + * Sending 0,...,0 in place of the reference will return the recomputed MAC + * as A xor 0 = A. + */ + uint8_t zeroes_buf[BLK_CIPHER_MAC_SIZE] = {0}; + block_t zeroes = block_t_convert(zeroes_buf, mac->len); + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + ciphertext, + plaintext, + &header, + aad, + &zeroes, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_ccm_decrypt_verify( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + const block_t *mac, + const block_t *aad) +{ + uint8_t mac_buf[BLK_CIPHER_MAC_SIZE]; + block_t mac_recomputed = block_t_convert(mac_buf, mac->len); + uint32_t status = sx_blk_cipher_ccm_decrypt( + engine, + operation, + key, + ciphertext, + plaintext, + nonce, + &mac_recomputed, + aad); + if (status) + return status; + + if (memcmp_time_cst(mac->addr, mac_buf, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +uint32_t sx_blk_cipher_ccm_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | + SX_BLK_CIPHER_MODEID_CX_SAVE; + + if ((datain->len != dataout->len) || (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t header_generated[22]; // Maximum header size (excluding aad which will be transferred directly) + block_t header = BLK_LITARRAY(header_generated); + uint32_t status = generate_ccm_header(*nonce, aad->len, total_length, mac_len, &header); + if (status) + return status; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + datain, + dataout, + &header, + aad, + &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_ccm_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in, + block_t *ctx_out) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | + SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((datain->len != dataout->len) || (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE) || + (ctx_out->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + datain, + dataout, + &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +uint32_t sx_blk_cipher_ccm_encrypt_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((plaintext->len != ciphertext->len) || + (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + /* Variant of CCM with disabled authenticity is supported: CCM* + * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see + * https://tools.ietf.org/html/rfc3610 for CCM and + * B.4 Specification of generic CCM* mode of operation from + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * for CCM* + */ + if ((mac->len % 2 != 0) || (mac->len == 2) || mac->len > BLK_CIPHER_MAC_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + plaintext, + ciphertext, + &dummy, &dummy, &dummy, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_ccm_decrypt_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + block_t *mac) +{ + CRYPTOLIB_ASSERT_NM(operation < SX_NUM_BLK_CIPHER_OPERATIONS); + uint32_t config = operation_select[operation] | SX_BLK_CIPHER_MODEID_CCM | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((plaintext->len != ciphertext->len) || + (ctx_in->len != BLK_CIPHER_CTX_xCM_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + /* Variant of CCM with disabled authenticity is supported: CCM* + * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see + * https://tools.ietf.org/html/rfc3610 for CCM and + * B.4 Specification of generic CCM* mode of operation from + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * for CCM* + */ + if ((mac->len % 2 != 0) || (mac->len == 2) || mac->len > BLK_CIPHER_MAC_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + /* CCM is implemented in a different way that GCM; it is not possible to + * directly read back the recomputed MAC from the BA411E. + * The reference MAC is xor-ed internally with the recomputed one. + * Sending 0,...,0 in place of the reference will return the recomputed MAC + * as A xor 0 = A. + */ + uint8_t zeroes_buf[BLK_CIPHER_MAC_SIZE] = {0}; + block_t zeroes = block_t_convert(zeroes_buf, mac->len); + block_t dummy = NULL_blk; + block_t extrain = dummy; + if (engine == SX_BLK_CIPHER_AES) + extrain = zeroes; + + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + ciphertext, + plaintext, + &dummy, &dummy, + &extrain, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_ccm_decrypt_verify_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac) +{ + uint8_t mac_buf[BLK_CIPHER_MAC_SIZE]; + block_t mac_recomputed = block_t_convert(mac_buf, mac->len); + uint32_t status = sx_blk_cipher_ccm_decrypt_final( + engine, + operation, + key, + ciphertext, + plaintext, + ctx_in, + &mac_recomputed); + if (status) + return status; + + if (memcmp_time_cst(mac->addr, mac_buf, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +// CMAC +// ----------------------------------------------------------------------------- +// Whole +uint32_t sx_blk_cipher_cmac_generate( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + block_t *mac) +{ + if (mac->len != BLK_CIPHER_MAC_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT; + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + message, + &dummy, &dummy, &dummy, &dummy, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_cmac_verify( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *mac) +{ + if (mac->len > BLK_CIPHER_MAC_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t recomputed_buf[BLK_CIPHER_MAC_SIZE]; + block_t recomputed = BLK_LITARRAY(recomputed_buf); + + uint32_t status = sx_blk_cipher_cmac_generate(engine, key, message, + &recomputed); + if (status) + return status; + + if (memcmp_time_cst(recomputed_buf, mac->addr, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +// Init +uint32_t sx_blk_cipher_cmac_generate_init( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + block_t *ctx_out) +{ + uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | + SX_BLK_CIPHER_MODEID_CX_SAVE; + + if (ctx_out->len != BLK_CIPHER_CTX_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, &dummy, + message, + &dummy, &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +// Update +uint32_t sx_blk_cipher_cmac_generate_update( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *ctx_out) +{ + uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | + SX_BLK_CIPHER_MODEID_CX_SAVE | SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((ctx_in->len != BLK_CIPHER_CTX_SIZE) || + (ctx_out->len != BLK_CIPHER_CTX_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + message, + &dummy, &dummy, &dummy, &dummy, &dummy, + ctx_out); +} + +// Final +uint32_t sx_blk_cipher_cmac_generate_final( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *mac) +{ + uint32_t config = SX_BLK_CIPHER_MODEID_CMA | SX_BLK_CIPHER_MODEID_ENCRYPT | + SX_BLK_CIPHER_MODEID_CX_LOAD; + + if ((ctx_in->len != BLK_CIPHER_CTX_SIZE) || (mac->len != BLK_CIPHER_MAC_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + block_t dummy = NULL_blk; + return sx_blk_cipher_build_descr( + engine, + config, + key, + &dummy, + ctx_in, + message, + &dummy, &dummy, &dummy, &dummy, + mac, + &dummy); +} + +uint32_t sx_blk_cipher_cmac_generate_verify_final( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + const block_t *mac) +{ + if (mac->len != BLK_CIPHER_MAC_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t recomputed_buf[BLK_CIPHER_MAC_SIZE]; + block_t recomputed = BLK_LITARRAY(recomputed_buf); + + uint32_t status = sx_blk_cipher_cmac_generate_final(engine, key, message, + ctx_in, &recomputed); + if (status) + return status; + + if (memcmp_time_cst(recomputed_buf, mac->addr, mac->len)) + return CRYPTOLIB_INVALID_SIGN_ERR; + return CRYPTOLIB_SUCCESS; +} + +/** + * @brief block cipher generate CCM header + * Create the header of CCM data based on lengths, nonce & aad2 + * + * @param nonce The Nonce + * @param aad_len The length of additional data to authenticate + * @param data_len The length of the data (plaintext or cipher) in bytes + * @param tag_len The length of the MAC in bytes + * @param header Pointer to the output header block + * @return CRYPTOLIB_SUCCESS if execution was successful + */ +uint32_t generate_ccm_header(block_t nonce, uint32_t aad_len, uint32_t data_len, + uint32_t tag_len, block_t *header) +{ + uint32_t flags; + uint32_t m, l; + uint32_t i; + + /* RFC3610 paragraph 2.2 defines the formatting of the first block. + * Thee first block contains: + * byte [0] the flags byte (see below) + * bytes [1,1+nonce.len] nonce + * bytes [2+nonce.len, 16] message length + * + * The flags byte has the following bit fields: + * [6:7] = 0 + * [3:5] = authentication tag size, encoded as (tag_len-2)/2 + * only multiples of 2 between 2 and 16 are allowed. + * [0:2] = length field size minus 1. Is the same as (15 - nonce.len - 1) + * between 2 and 8. + **/ + + /* Verify input parameters + * + * Variant of CCM with disabled authenticity is supported: CCM* + * CCM* MAC length is one of {0,4,6,8,10,12,14,16}, see + * https://tools.ietf.org/html/rfc3610 for CCM and + * B.4 Specification of generic CCM* mode of operation from + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * for CCM* + */ + if ((tag_len & 1) || (tag_len == 2) || (tag_len > BLK_CIPHER_MAC_SIZE)) + return CRYPTOLIB_INVALID_PARAM; + + /* The conditions below translate into (l > 8) || (l < 2) which match the + * specification "The parameter L can take on the values from 2 to 8" + */ + if ((nonce.len < 7) || (nonce.len > 13)) + return CRYPTOLIB_INVALID_PARAM; + + flags = (aad_len > 0) ? (1 << 6) : 0; + /* Authentication tag size encoding. A tag_len = 0 is accepted by CCM* and + * that will be encoded as a 0. */ + m = (tag_len > 0) ? (tag_len-2)/2 : 0; + flags |= (m & 0x7) << 3; + l = 15 - nonce.len; + flags |= ((l-1) & 0x7); + header->addr[0] = flags; + + /* If l >= 4, data_len will always fit as it is an uint32_t, we need to + * check only in case l < 4: */ + if (l < 4U && data_len >= (1U << (l * 8))) { + /* message too long to encode the size in the CCM header */ + return CRYPTOLIB_INVALID_PARAM; + } + + memcpy_blkIn(&header->addr[1], nonce, nonce.len); + + /* append message length in big endian format encoded l octets*/ + memset(&(header->addr[1 + nonce.len]), 0, l); + for (i = 0; i < sizeof(data_len); i++) { + if (data_len >= (1U << (i * 8))) + header->addr[15 - i] = (data_len >> (i * 8)) & 0xff; + else + break; + } + + /* if there's additional authentication data (or aad2), + * encode the size: + * + * 0 < aad_len < 0xFF00 => 2 bytes in big endian format. + * 0xFF00 < aad_len < 2^32 => 0xff, 0xfe, and four bytes in big endian format. + * eSecure currently does not support sizes bigger than 2^32. + */ + if (aad_len > 0) { + if (aad_len < 0xFF00) { + header->addr[16] = aad_len >> 8; + header->addr[17] = aad_len & 0xff; + header->len = 18; + } else { + // TODO: Test following case + header->addr[16] = 0xFF; + header->addr[17] = 0xFE; + header->addr[18] = aad_len >> 24; + header->addr[19] = (aad_len >> 16) & 0xff; + header->addr[20] = (aad_len >> 8) & 0xff; + header->addr[21] = aad_len & 0xff; + header->len = 22; + } + } else { + header->len = 16; + } + + return CRYPTOLIB_SUCCESS; +} + +/** + * @brief Get block cipher padding length (realign on block cipher block size) + * @param input_length input length + * @return length of padding + */ +uint32_t get_pad_len(uint32_t input_length) +{ + return (16-input_length)&15; +} + +/** + * @brief Build descriptors and call cryptoDMA for block cipher operation + * @param engine selected engine to be used as block cipher + * @param config value for cfg mode register + * @param key block cipher key + * @param xtskey XTS key. + * @param iv initialization vector + * @param datain input data (plaintext or ciphertext) + * @param dataout output data (ciphertext or plaintext) + * @param aad1 additional authenticated data part #1 + * @param aad2 additional authenticated data part #2 + * @param extrain additional input data expected by ::GCM or ::CCM + * @param tag_out authentication tag input for ::CCM, ::GCM & ::CMAC + * @param ctx_ptr block cipher context output + * @return CRYPTOLIB_SUCCESS when execution was successful + */ +static uint32_t sx_blk_cipher_build_descr( + enum sx_blk_cipher_engine_select engine, + uint32_t hw_config, + const block_t *key, + const block_t *xtskey, + const block_t *iv, + const block_t *datain, + block_t *dataout, + const block_t *aad1, + const block_t *aad2, + const block_t *extrain, + block_t *tag_out, + block_t *ctx_ptr) +{ + block_t config = block_t_convert(&hw_config, sizeof(hw_config)); + block_t keyb = *key; + CRYPTOLIB_ASSERT(engine < SX_NUM_BLK_CIPHER_ENGINES, "Invalid engine"); + uint32_t status = sx_aes_set_hw_config_for_key(&keyb, &hw_config); + if (status) + return status; + + struct dma_sg_descr_s desc_to[DESC_N_TO_ENGINE]; //could be reduces as no use case where all inputs are used, but safer like this + struct dma_sg_descr_s desc_fr[DESC_N_FROM_ENGINE]; + struct dma_sg_descr_s *d; // pointer to current descriptor + block_t datainb = *datain; + // input padding + uint32_t aad_zeropad_len = get_pad_len(aad1->len + aad2->len); + uint32_t datain_zeropad_len = get_pad_len(datain->len); + uint32_t extrain_zeropad_len = get_pad_len(extrain->len); + + // handle alignment for data out + if(dataout->flags & DMA_AXI_DESCR_CONST_ADDR) + dataout->len = roundup_32(dataout->len); + + if(tag_out->flags & DMA_AXI_DESCR_CONST_ADDR) + tag_out->len = roundup_32(tag_out->len); + + // output discards + block_t aads_discard = block_t_convert(NULL, aad1->len + aad2->len + aad_zeropad_len); + block_t dataout_discard = block_t_convert(NULL, get_pad_len(dataout->len)); + block_t tagout_discard = block_t_convert(NULL, get_pad_len(tag_out->len)); + + // no input provided, -> empty input = 1 block of zero padding (i.e. for CMAC) + uint8_t zeroes[16] = {0}; + if (!datain->len && !extrain->len && !aad1->len && !aad2->len ) { + datain_zeropad_len = 16; + datainb = block_t_convert(zeroes, datain_zeropad_len); + } + + // fetcher descriptors + d = desc_to; + // Config + d = write_desc_blk( + d, + &config, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISCONFIG | + DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_CFG)); + + // Symmetric key + d = write_desc_blk( + d, + &keyb, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISCONFIG | + DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_KEY)); + + // IV or context (if existing) + d = write_desc_blk( + d, + iv, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISCONFIG | + DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_IV)); + + // XTS key (if existing) + d = write_desc_blk( + d, + xtskey, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISCONFIG | + DMA_SG_TAG_SETCFGOFFSET(SX_BLK_CIPHER_OFFSET_KEY2)); + + // authentication data (if existing) + d = write_desc_blk( + d, + aad1, + 0, + engine_select[engine] | DMA_SG_TAG_ISDATA | + DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER); + d = write_desc_blk( + d, + aad2, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISDATA | + DMA_SG_TAG_DATATYPE_BLK_CIPHER_HEADER | + DMA_SG_TAG_SETINVALIDBYTES(aad_zeropad_len)); + + // Input data (if existing) + d = write_desc_blk( + d, + &datainb, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISDATA | + DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD | + DMA_SG_TAG_SETINVALIDBYTES(datain_zeropad_len)); + + // Additional input data (may be tag_in for CCM or len_a_c for GCM) + d = write_desc_blk( + d, + extrain, + DMA_AXI_DESCR_REALIGN, + engine_select[engine] | DMA_SG_TAG_ISDATA | + DMA_SG_TAG_DATATYPE_BLK_CIPHER_PAYLOAD | + DMA_SG_TAG_SETINVALIDBYTES(extrain_zeropad_len)); + + set_last_desc(d - 1); + + // pusher descriptors + d = desc_fr; + + // discard output aad and associated padding + d = write_desc_blk(d, &aads_discard, 0, 0); + + // Output data + d = write_desc_blk(d, dataout, 0, 0); + d = write_desc_blk(d, &dataout_discard, 0, 0); + + // Output tag (if existing) + d = write_desc_blk(d, tag_out, 0, 0); + d = write_desc_blk(d, &tagout_discard, 0, 0); + + // Output context (if existing) + d = write_desc_blk(d, ctx_ptr, 0, 0); + + set_last_desc(d - 1); + + // launch cryptodma + cryptodma_run_sg(desc_to, desc_fr); + + return CRYPTOLIB_SUCCESS; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.h index ca0c57c..c49f6bd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.h @@ -1,871 +1,871 @@ -/** - * @file - * @brief Defines the procedures to make operations with block ciphers engines: - * BA411E-AES - * @copyright Copyright (c) 2019-2020 Silex Insight. All Rights reserved - */ - -#ifndef SX_BLK_CIPHER_H -#define SX_BLK_CIPHER_H - -#include -#include -#include "compiler_extentions.h" -#include "cryptolib_types.h" -#include "cryptodma_internal.h" - -enum sx_blk_cipher_engine_select -{ - SX_BLK_CIPHER_AES, /**< block cipher AES */ - SX_NUM_BLK_CIPHER_ENGINES /**< number of supported block cipher engines */ -}; - -enum sx_blk_cipher_mode_select -{ - SX_BLK_CIPHER_MODE_ECB, /**< block cipher mode ECB */ - SX_BLK_CIPHER_MODE_CBC, /**< block cipher mode CBC */ - SX_BLK_CIPHER_MODE_CTR, /**< block cipher mode CTR */ - SX_BLK_CIPHER_MODE_CFB, /**< block cipher mode CFB */ - SX_BLK_CIPHER_MODE_OFB, /**< block cipher mode OFB */ - SX_BLK_CIPHER_MODE_CCM, /**< block cipher mode CCM */ - SX_BLK_CIPHER_MODE_GCM, /**< block cipher mode GCM */ - SX_BLK_CIPHER_MODE_XTS, /**< block cipher mode XTS */ - SX_BLK_CIPHER_MODE_CMA, /**< block cipher mode CMAC */ - SX_NUM_BLK_CIPHER_MODES /**< number of supported modes */ -}; - -enum sx_blk_cipher_operation -{ - SX_BLK_CIPHER_ENCRYPT, /**< block cipher encrypt */ - SX_BLK_CIPHER_DECRYPT, /**< block cipher decrypt */ - SX_NUM_BLK_CIPHER_OPERATIONS /**< number of supported block cipher operations */ -}; - -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_CFG 0 -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_KEY 8 -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_IV 40 -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_IV2 56 -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_KEY2 72 -/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ -#define SX_BLK_CIPHER_OFFSET_MASK 104 - -/** @brief Block cipher Mode Register value for ECB mode of operation */ -#define SX_BLK_CIPHER_MODEID_ECB 0x00000100 -/** @brief Block cipher Mode Register value for CBC mode of operation */ -#define SX_BLK_CIPHER_MODEID_CBC 0x00000200 -/** @brief Block cipher Mode Register value for CTR mode of operation */ -#define SX_BLK_CIPHER_MODEID_CTR 0x00000400 -/** @brief Block cipher Mode Register value for CFB mode of operation */ -#define SX_BLK_CIPHER_MODEID_CFB 0x00000800 -/** @brief Block cipher Mode Register value for OFB mode of operation */ -#define SX_BLK_CIPHER_MODEID_OFB 0x00001000 -/** @brief Block cipher Mode Register value for CCM mode of operation */ -#define SX_BLK_CIPHER_MODEID_CCM 0x00002000 -/** @brief Block cipher Mode Register value for GCM mode of operation */ -#define SX_BLK_CIPHER_MODEID_GCM 0x00004000 -/** @brief Block cipher Mode Register value for XTS mode of operation */ -#define SX_BLK_CIPHER_MODEID_XTS 0x00008000 -/** @brief Block cipher Mode Register value for CMAC mode of operation */ -#define SX_BLK_CIPHER_MODEID_CMA 0x00010000 - -/** @brief Block cipher Mode Register value for encryption mode */ -#define SX_BLK_CIPHER_MODEID_ENCRYPT 0x00000000 -/** @brief Block cipher Mode Register value for decryption mode */ -#define SX_BLK_CIPHER_MODEID_DECRYPT 0x00000001 - -/** @brief Mode Register value for context saving */ -#define SX_BLK_CIPHER_MODEID_CX_SAVE 0x00000020 -/** @brief Mode Register value for context loading */ -#define SX_BLK_CIPHER_MODEID_CX_LOAD 0x00000010 -/** @brief Mode Register value for no context */ -#define SX_BLK_CIPHER_MODEID_NO_CX 0x00000000 -/** @brief Mode Register value for keysize of 128 bits */ -#define SX_BLK_CIPHER_MODEID_128 0x00000000 -/** @brief Mode Register value for keysize of 192 bits */ -#define SX_BLK_CIPHER_MODEID_192 0x00000008 -/** @brief Mode Register value for keysize of 256 bits */ -#define SX_BLK_CIPHER_MODEID_256 0x00000004 -/** @brief Mode Register value to use Key1 */ -#define SX_BLK_CIPHER_MODEID_KEY1 0x00000040 -/** @brief Mode Register value to use Key2 */ -#define SX_BLK_CIPHER_MODEID_KEY2 0x00000080 - -/** Encryption operation with mode ECB - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ecb( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output); - -/** Encryption operation with mode CBC - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cbc( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv); - -/** Finish (final) encryption operation with modes CBC - * in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_cbc_init or from ::sx_cbc_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cbc_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *datain, - block_t *dataout, - const block_t *ctx_in); - -/** Start (init) encryption operation with modes CBC, CTR, OFB, and CFB - * in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param mode is the mode used in block cipher - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_cbc_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv, - block_t *ctx_out); - -/** Continue (update) encryption operation with modes CBC, CTR, OFB, and CFB - * in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param mode is the mode used in block cipher - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_cbc_init or from ::sx_cbc_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_ctr_update or to ::sx_ctr_final - * @param is_mode_supported is the flag that specifies if mode is supported - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption operation with modes CBC, CTR, OFB, and CFB - * in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param mode is the mode used in block cipher - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_cbc_init or from ::sx_cbc_update - * @param is_mode_supported is the flag that specifies if mode is supported - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cfb_ofb_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in); - -/** Encryption operation with mode CTR - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ctr( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv); - -/** Finish (final) encryption operation with mode CTR in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_ctr_init or from ::sx_ctr_update - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ctr_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in); - - -/** Encryption operation with mode CFB or OFB - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param mode is the mode used in block cipher - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cfb_ofb( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - enum sx_blk_cipher_mode_select mode, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv); - -/** Encryption operation with mode XTS - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @param key_xts is the "tweak" key involved in block cipher XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_xts( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv, - const block_t *key_xts); - -/** Start (init) encryption operation with mode XTS in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_xts_update - * @param key_xts is the "tweak" key involved in block cipher XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_xts_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv, - block_t *ctx_out, - const block_t *key_xts); - -/** Continue (update) encryption operation with mode XTS in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_xts_init or from ::sx_xts_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_xts_update or to ::sx_xts_final - * @param key_xts is the "tweak" key involved in block cipher XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_xts_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - block_t *ctx_out, - const block_t *key_xts); - - -/** Finish (final) encryption operation with mode XTS in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt the input data - * @param input is the input data to be encrypted/decrypted - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_xts_init or from ::sx_xts_update - * @param key_xts is the "tweak" key involved in block cipher XTS - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_xts_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - const block_t *key_xts); - -/** Encryption and authentication operation with mode GCM - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @param mac is the output Message Authentication Code of the plaintext and aad - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * @note If one only needs authentication, this function may be used as GMAC - * and user has to only keep the \c plaintext and the \c mac - */ -uint32_t sx_blk_cipher_gcm( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv, - block_t *mac, - const block_t *aad); - -/** Decryption, authentication and verification operation with mode GCM - * - * By opposition to ::sx_gcm_decrypt, this function does not output the MAC - * but uses an input reference to internally check if it maches the recomputed - * one. By only checking the returned value of the function, caller knows - * if the input data (\ciphertext) are tampered or not. - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param iv is the input initialization vector - * @param mac is an input Message Authentication Code as reference for verification - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_gcm_decrypt_verify( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *iv, - const block_t *mac, - const block_t *aad); - -/** Start (init) encryption and authentication operation with mode GCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param iv is the input initialization vector - * @param ctx_out is the output intermediate context to forward to - * ::sx_gcm_update (expected size is 32B) - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_gcm_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *iv, - block_t *ctx_out, - const block_t *aad); - -/** Continue (update) encryption and authentication operation with mode GCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_gcm_init or from ::sx_gcm_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_gcm_update or to ::sx_gcm_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * @note the expected size for GCM context is 32B - */ -uint32_t sx_blk_cipher_gcm_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption and authentication operation with mode GCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_gcm_init or from ::sx_gcm_update - * @param mac is the output Message Authentication Code of the plaintext and aad - * @param len_a_c are length of both \c plaintext and \c aad as described in - * NIST SP800-38D at 7.GCM Specification - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * @note the expected size for GCM context is 32B - */ -uint32_t sx_blk_cipher_gcm_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - block_t *mac, - const block_t *len_a_c); - -/** Finish (final) decryption, authentication and verification operation using - * block cipher GCM in Init-Update-Final model - * - * By opposition to ::sx_gcm_decrypt_final, this function does not output - * the MAC but uses an input reference to internally check if it maches the - * recomputed one. By only checking the returned value of the function, caller - * knows if the input data (\ciphertext) are tampered or not. - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_gcm_decrypt_init or from ::sx_gcm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @param len_a_c are length of both \c ciphertext and \c aad as described in - * NIST SP800-38D at 7.GCM Specification - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for GCM context is 32B - */ -uint32_t sx_blk_cipher_gcm_decrypt_verify_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac, - const block_t *len_a_c); - -/** Encryption and authentication operation with mode CCM - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is the output Message Authentication Code of the plaintext and aad, - * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to - * CCM* described in B.4 Specification of generic CCM* mode of operation - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ccm_encrypt( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *mac, - const block_t *aad); - -/** Decryption and authentication operation with mode CCM - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is the output Message Authentication Code of the plaintext and aad, - * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to - * CCM* described in B.4 Specification of generic CCM* mode of operation - * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf - * @param aad are additional data passed aside the plaintext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ccm_decrypt( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *nonce, - block_t *mac, - const block_t *aad); - -/** Decryption, authentication and verification operation with mode CCM - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) - * @param mac is an input Message Authentication Code as reference for verification, - * @param aad are additional data passed aside the ciphertext to compute the MAC - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ccm_decrypt_verify( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *nonce, - const block_t *mac, - const block_t *aad); - -/** Start (init) encryption and authentication operation with mode CCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param nonce is the input number to use once - * @param ctx_out is the output intermediate context to forward to - * ::sx_ccm_update (expected size is 32B) - * @param aad are additional data passed aside the plaintext to compute the MAC - * @param mac_len is the length of the mac to output. In IUF, it is mandatory - * to provide it during init step as this length is required to compute - * CCM headers. - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_ccm_init( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *nonce, - block_t *ctx_out, - const block_t *aad, - uint32_t mac_len, - uint32_t total_length); - -/** Continue (update) encryption and authentication operation with mode CCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt/decrypt and authenticate the input data - * @param input is the input data to be encrypted/decrypted and authenticate - * @param output is the output encrypted/decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_ccm_init or from ::sx_ccm_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_ccm_update or to ::sx_ccm_final - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_blk_cipher_ccm_update( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *input, - block_t *output, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) encryption and authentication operation with mode CCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to encrypt and authenticate the plaintext - * @param plaintext is the input data to encrypt and authenticate - * @param ciphertext is the output encrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_ccm_init or from ::sx_ccm_update - * @param mac is the output Message Authentication Code of the plaintext and aad - * @return ::CRYPTOLIB_SUCCESS if encryption succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_blk_cipher_ccm_encrypt_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) decryption and authentication operation with mode CCM in - * Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_ccm_decrypt_init or from ::sx_ccm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @note the expected size for CCM context is 32B - */ -uint32_t sx_blk_cipher_ccm_decrypt_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *plaintext, - block_t *ciphertext, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) decryption, authentication and verification operation using - * block cipher CCM in Init-Update-Final model - * - * @param engine is the engine used - * @param operation holds engine operation: encrypt or decrypt - * @param key is the key involved to decrypt and authenticate the ciphertext - * @param ciphertext is the input data to decrypt and authenticate - * @param plaintext is the output decrypted data - * @param ctx_in is the input intermediate context outputted from - * ::sx_ccm_decrypt_init or from ::sx_ccm_decrypt_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - * - * @note the expected size for CCM context is 32B - */ -uint32_t sx_blk_cipher_ccm_decrypt_verify_final( - enum sx_blk_cipher_engine_select engine, - enum sx_blk_cipher_operation operation, - const block_t *key, - const block_t *ciphertext, - block_t *plaintext, - const block_t *ctx_in, - const block_t *mac); - -/** Authentication operation using CMAC - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param mac is the output Message Authentication Code - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_generate( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - block_t *mac); - -/** Authentication verification operation using CMAC - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate and verify - * @param mac is an input Message Authentication Code used as reference - * @return ::CRYPTOLIB_SUCCESS if authentication verifiation succeeded - * ::CRYPTOLIB_INVALID_SIGN_ERR if authentication verification failed - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_verify( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *mac); - -/** Start (init) authentication operation using CMAC in Init-Update-Final model - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_out is the output intermediate context to forward to - * ::sx_cmac_generate_update - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_generate_init( - enum sx_blk_cipher_engine_select engine, - - const block_t *key, - const block_t *message, - block_t *ctx_out); - -/** Continue (update) authentication operation using CMAC in - * Init-Update-Final model - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_cmac_generate_init or from ::sx_cmac_generate_update - * @param ctx_out is the output intermediate context to forward to - * ::sx_cmac_generate_update - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_generate_update( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *ctx_out); - -/** Finish (final) authentication operation using CMAC in - * Init-Update-Final model - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_cmac_generate_init or from ::sx_cmac_generate_update - * @param mac is the output Message Authentication Code of the message - * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_generate_final( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - block_t *mac); - -/** Finish (final) authentication verification operation using CMAC in - * Init-Update-Final model - * - * @param engine is the engine used - * @param key is the key involved in authentication of a message - * @param message is the message to authenticate - * @param ctx_in is the input intermediate context outputted from - * ::sx_cmac_generate_init or from ::sx_cmac_generate_update - * @param mac is an input Message Authentication Code as reference for verification - * @return ::CRYPTOLIB_SUCCESS if authentication verification succeeded - * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match - * recomputed one - * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported - */ -uint32_t sx_blk_cipher_cmac_generate_verify_final( - enum sx_blk_cipher_engine_select engine, - const block_t *key, - const block_t *message, - const block_t *ctx_in, - const block_t *mac); -#endif +/** + * @file + * @brief Defines the procedures to make operations with block ciphers engines: + * BA411E-AES + * @copyright Copyright (c) 2019-2020 Silex Insight. All Rights reserved + */ + +#ifndef SX_BLK_CIPHER_H +#define SX_BLK_CIPHER_H + +#include +#include +#include "compiler_extentions.h" +#include "cryptolib_types.h" +#include "cryptodma_internal.h" + +enum sx_blk_cipher_engine_select +{ + SX_BLK_CIPHER_AES, /**< block cipher AES */ + SX_NUM_BLK_CIPHER_ENGINES /**< number of supported block cipher engines */ +}; + +enum sx_blk_cipher_mode_select +{ + SX_BLK_CIPHER_MODE_ECB, /**< block cipher mode ECB */ + SX_BLK_CIPHER_MODE_CBC, /**< block cipher mode CBC */ + SX_BLK_CIPHER_MODE_CTR, /**< block cipher mode CTR */ + SX_BLK_CIPHER_MODE_CFB, /**< block cipher mode CFB */ + SX_BLK_CIPHER_MODE_OFB, /**< block cipher mode OFB */ + SX_BLK_CIPHER_MODE_CCM, /**< block cipher mode CCM */ + SX_BLK_CIPHER_MODE_GCM, /**< block cipher mode GCM */ + SX_BLK_CIPHER_MODE_XTS, /**< block cipher mode XTS */ + SX_BLK_CIPHER_MODE_CMA, /**< block cipher mode CMAC */ + SX_NUM_BLK_CIPHER_MODES /**< number of supported modes */ +}; + +enum sx_blk_cipher_operation +{ + SX_BLK_CIPHER_ENCRYPT, /**< block cipher encrypt */ + SX_BLK_CIPHER_DECRYPT, /**< block cipher decrypt */ + SX_NUM_BLK_CIPHER_OPERATIONS /**< number of supported block cipher operations */ +}; + +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_CFG 0 +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_KEY 8 +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_IV 40 +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_IV2 56 +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_KEY2 72 +/** @brief Offset for Configuration word in DMA Scatter-Gather Tag */ +#define SX_BLK_CIPHER_OFFSET_MASK 104 + +/** @brief Block cipher Mode Register value for ECB mode of operation */ +#define SX_BLK_CIPHER_MODEID_ECB 0x00000100 +/** @brief Block cipher Mode Register value for CBC mode of operation */ +#define SX_BLK_CIPHER_MODEID_CBC 0x00000200 +/** @brief Block cipher Mode Register value for CTR mode of operation */ +#define SX_BLK_CIPHER_MODEID_CTR 0x00000400 +/** @brief Block cipher Mode Register value for CFB mode of operation */ +#define SX_BLK_CIPHER_MODEID_CFB 0x00000800 +/** @brief Block cipher Mode Register value for OFB mode of operation */ +#define SX_BLK_CIPHER_MODEID_OFB 0x00001000 +/** @brief Block cipher Mode Register value for CCM mode of operation */ +#define SX_BLK_CIPHER_MODEID_CCM 0x00002000 +/** @brief Block cipher Mode Register value for GCM mode of operation */ +#define SX_BLK_CIPHER_MODEID_GCM 0x00004000 +/** @brief Block cipher Mode Register value for XTS mode of operation */ +#define SX_BLK_CIPHER_MODEID_XTS 0x00008000 +/** @brief Block cipher Mode Register value for CMAC mode of operation */ +#define SX_BLK_CIPHER_MODEID_CMA 0x00010000 + +/** @brief Block cipher Mode Register value for encryption mode */ +#define SX_BLK_CIPHER_MODEID_ENCRYPT 0x00000000 +/** @brief Block cipher Mode Register value for decryption mode */ +#define SX_BLK_CIPHER_MODEID_DECRYPT 0x00000001 + +/** @brief Mode Register value for context saving */ +#define SX_BLK_CIPHER_MODEID_CX_SAVE 0x00000020 +/** @brief Mode Register value for context loading */ +#define SX_BLK_CIPHER_MODEID_CX_LOAD 0x00000010 +/** @brief Mode Register value for no context */ +#define SX_BLK_CIPHER_MODEID_NO_CX 0x00000000 +/** @brief Mode Register value for keysize of 128 bits */ +#define SX_BLK_CIPHER_MODEID_128 0x00000000 +/** @brief Mode Register value for keysize of 192 bits */ +#define SX_BLK_CIPHER_MODEID_192 0x00000008 +/** @brief Mode Register value for keysize of 256 bits */ +#define SX_BLK_CIPHER_MODEID_256 0x00000004 +/** @brief Mode Register value to use Key1 */ +#define SX_BLK_CIPHER_MODEID_KEY1 0x00000040 +/** @brief Mode Register value to use Key2 */ +#define SX_BLK_CIPHER_MODEID_KEY2 0x00000080 + +/** Encryption operation with mode ECB + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ecb( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output); + +/** Encryption operation with mode CBC + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cbc( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv); + +/** Finish (final) encryption operation with modes CBC + * in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_cbc_init or from ::sx_cbc_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cbc_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *datain, + block_t *dataout, + const block_t *ctx_in); + +/** Start (init) encryption operation with modes CBC, CTR, OFB, and CFB + * in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param mode is the mode used in block cipher + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_cbc_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv, + block_t *ctx_out); + +/** Continue (update) encryption operation with modes CBC, CTR, OFB, and CFB + * in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param mode is the mode used in block cipher + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_cbc_init or from ::sx_cbc_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_ctr_update or to ::sx_ctr_final + * @param is_mode_supported is the flag that specifies if mode is supported + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cbc_ctr_ofb_cfb_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption operation with modes CBC, CTR, OFB, and CFB + * in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param mode is the mode used in block cipher + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_cbc_init or from ::sx_cbc_update + * @param is_mode_supported is the flag that specifies if mode is supported + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cfb_ofb_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in); + +/** Encryption operation with mode CTR + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ctr( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv); + +/** Finish (final) encryption operation with mode CTR in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_ctr_init or from ::sx_ctr_update + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ctr_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in); + + +/** Encryption operation with mode CFB or OFB + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param mode is the mode used in block cipher + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cfb_ofb( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + enum sx_blk_cipher_mode_select mode, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv); + +/** Encryption operation with mode XTS + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @param key_xts is the "tweak" key involved in block cipher XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_xts( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv, + const block_t *key_xts); + +/** Start (init) encryption operation with mode XTS in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_xts_update + * @param key_xts is the "tweak" key involved in block cipher XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_xts_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv, + block_t *ctx_out, + const block_t *key_xts); + +/** Continue (update) encryption operation with mode XTS in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_xts_init or from ::sx_xts_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_xts_update or to ::sx_xts_final + * @param key_xts is the "tweak" key involved in block cipher XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_xts_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + block_t *ctx_out, + const block_t *key_xts); + + +/** Finish (final) encryption operation with mode XTS in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt the input data + * @param input is the input data to be encrypted/decrypted + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_xts_init or from ::sx_xts_update + * @param key_xts is the "tweak" key involved in block cipher XTS + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_xts_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + const block_t *key_xts); + +/** Encryption and authentication operation with mode GCM + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @param mac is the output Message Authentication Code of the plaintext and aad + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * @note If one only needs authentication, this function may be used as GMAC + * and user has to only keep the \c plaintext and the \c mac + */ +uint32_t sx_blk_cipher_gcm( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv, + block_t *mac, + const block_t *aad); + +/** Decryption, authentication and verification operation with mode GCM + * + * By opposition to ::sx_gcm_decrypt, this function does not output the MAC + * but uses an input reference to internally check if it maches the recomputed + * one. By only checking the returned value of the function, caller knows + * if the input data (\ciphertext) are tampered or not. + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param iv is the input initialization vector + * @param mac is an input Message Authentication Code as reference for verification + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_gcm_decrypt_verify( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *iv, + const block_t *mac, + const block_t *aad); + +/** Start (init) encryption and authentication operation with mode GCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param iv is the input initialization vector + * @param ctx_out is the output intermediate context to forward to + * ::sx_gcm_update (expected size is 32B) + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_gcm_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *iv, + block_t *ctx_out, + const block_t *aad); + +/** Continue (update) encryption and authentication operation with mode GCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_gcm_init or from ::sx_gcm_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_gcm_update or to ::sx_gcm_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * @note the expected size for GCM context is 32B + */ +uint32_t sx_blk_cipher_gcm_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption and authentication operation with mode GCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_gcm_init or from ::sx_gcm_update + * @param mac is the output Message Authentication Code of the plaintext and aad + * @param len_a_c are length of both \c plaintext and \c aad as described in + * NIST SP800-38D at 7.GCM Specification + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * @note the expected size for GCM context is 32B + */ +uint32_t sx_blk_cipher_gcm_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + block_t *mac, + const block_t *len_a_c); + +/** Finish (final) decryption, authentication and verification operation using + * block cipher GCM in Init-Update-Final model + * + * By opposition to ::sx_gcm_decrypt_final, this function does not output + * the MAC but uses an input reference to internally check if it maches the + * recomputed one. By only checking the returned value of the function, caller + * knows if the input data (\ciphertext) are tampered or not. + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_gcm_decrypt_init or from ::sx_gcm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @param len_a_c are length of both \c ciphertext and \c aad as described in + * NIST SP800-38D at 7.GCM Specification + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for GCM context is 32B + */ +uint32_t sx_blk_cipher_gcm_decrypt_verify_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac, + const block_t *len_a_c); + +/** Encryption and authentication operation with mode CCM + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is the output Message Authentication Code of the plaintext and aad, + * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to + * CCM* described in B.4 Specification of generic CCM* mode of operation + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ccm_encrypt( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *mac, + const block_t *aad); + +/** Decryption and authentication operation with mode CCM + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is the output Message Authentication Code of the plaintext and aad, + * expected size may be 0, 4, 6, 8, 10, 12, 14, 16B. 0B corresponds to + * CCM* described in B.4 Specification of generic CCM* mode of operation + * http://ecee.colorado.edu/~liue/teaching/comm_standards/2015S_zigbee/802.15.4-2011.pdf + * @param aad are additional data passed aside the plaintext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if encryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ccm_decrypt( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *nonce, + block_t *mac, + const block_t *aad); + +/** Decryption, authentication and verification operation with mode CCM + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param nonce is the input number to use once (expected size is bewteen 7 and 13B) + * @param mac is an input Message Authentication Code as reference for verification, + * @param aad are additional data passed aside the ciphertext to compute the MAC + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ccm_decrypt_verify( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *nonce, + const block_t *mac, + const block_t *aad); + +/** Start (init) encryption and authentication operation with mode CCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param nonce is the input number to use once + * @param ctx_out is the output intermediate context to forward to + * ::sx_ccm_update (expected size is 32B) + * @param aad are additional data passed aside the plaintext to compute the MAC + * @param mac_len is the length of the mac to output. In IUF, it is mandatory + * to provide it during init step as this length is required to compute + * CCM headers. + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_ccm_init( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *nonce, + block_t *ctx_out, + const block_t *aad, + uint32_t mac_len, + uint32_t total_length); + +/** Continue (update) encryption and authentication operation with mode CCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt/decrypt and authenticate the input data + * @param input is the input data to be encrypted/decrypted and authenticate + * @param output is the output encrypted/decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_ccm_init or from ::sx_ccm_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_ccm_update or to ::sx_ccm_final + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_blk_cipher_ccm_update( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *input, + block_t *output, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) encryption and authentication operation with mode CCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to encrypt and authenticate the plaintext + * @param plaintext is the input data to encrypt and authenticate + * @param ciphertext is the output encrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_ccm_init or from ::sx_ccm_update + * @param mac is the output Message Authentication Code of the plaintext and aad + * @return ::CRYPTOLIB_SUCCESS if encryption succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_blk_cipher_ccm_encrypt_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) decryption and authentication operation with mode CCM in + * Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_ccm_decrypt_init or from ::sx_ccm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if decryption and authentication succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @note the expected size for CCM context is 32B + */ +uint32_t sx_blk_cipher_ccm_decrypt_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *plaintext, + block_t *ciphertext, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) decryption, authentication and verification operation using + * block cipher CCM in Init-Update-Final model + * + * @param engine is the engine used + * @param operation holds engine operation: encrypt or decrypt + * @param key is the key involved to decrypt and authenticate the ciphertext + * @param ciphertext is the input data to decrypt and authenticate + * @param plaintext is the output decrypted data + * @param ctx_in is the input intermediate context outputted from + * ::sx_ccm_decrypt_init or from ::sx_ccm_decrypt_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if reference MAC matches recomputed one + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + * + * @note the expected size for CCM context is 32B + */ +uint32_t sx_blk_cipher_ccm_decrypt_verify_final( + enum sx_blk_cipher_engine_select engine, + enum sx_blk_cipher_operation operation, + const block_t *key, + const block_t *ciphertext, + block_t *plaintext, + const block_t *ctx_in, + const block_t *mac); + +/** Authentication operation using CMAC + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param mac is the output Message Authentication Code + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_generate( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + block_t *mac); + +/** Authentication verification operation using CMAC + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate and verify + * @param mac is an input Message Authentication Code used as reference + * @return ::CRYPTOLIB_SUCCESS if authentication verifiation succeeded + * ::CRYPTOLIB_INVALID_SIGN_ERR if authentication verification failed + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_verify( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *mac); + +/** Start (init) authentication operation using CMAC in Init-Update-Final model + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_out is the output intermediate context to forward to + * ::sx_cmac_generate_update + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_generate_init( + enum sx_blk_cipher_engine_select engine, + + const block_t *key, + const block_t *message, + block_t *ctx_out); + +/** Continue (update) authentication operation using CMAC in + * Init-Update-Final model + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_cmac_generate_init or from ::sx_cmac_generate_update + * @param ctx_out is the output intermediate context to forward to + * ::sx_cmac_generate_update + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_generate_update( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *ctx_out); + +/** Finish (final) authentication operation using CMAC in + * Init-Update-Final model + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_cmac_generate_init or from ::sx_cmac_generate_update + * @param mac is the output Message Authentication Code of the message + * @return ::CRYPTOLIB_SUCCESS if authentication generation succeeded + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_generate_final( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + block_t *mac); + +/** Finish (final) authentication verification operation using CMAC in + * Init-Update-Final model + * + * @param engine is the engine used + * @param key is the key involved in authentication of a message + * @param message is the message to authenticate + * @param ctx_in is the input intermediate context outputted from + * ::sx_cmac_generate_init or from ::sx_cmac_generate_update + * @param mac is an input Message Authentication Code as reference for verification + * @return ::CRYPTOLIB_SUCCESS if authentication verification succeeded + * ::CRYPTOLIB_INVALID_SIGN_ERR if reference MAC does not match + * recomputed one + * ::CRYPTOLIB_UNSUPPORTED_ERR if the key length is not supported + */ +uint32_t sx_blk_cipher_cmac_generate_verify_final( + enum sx_blk_cipher_engine_select engine, + const block_t *key, + const block_t *message, + const block_t *ctx_in, + const block_t *mac); +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c index 7131376..cfd48eb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c @@ -1,96 +1,96 @@ -/** - * @file - * @brief Defines the shared key generation for DH protocoles - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#include "sx_dh_alg.h" -#include "cryptolib_def.h" -#include "sx_memcpy.h" -#include "ba414ep_config.h" -#include "sx_primitives.h" -#include "sx_errors.h" - - -#if (DH_MODP_ENABLED) - -uint32_t dh_shared_key_modp(block_t mod, block_t priv, block_t pub, block_t shared, uint32_t size) -{ - if (size > DH_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (mod.len != size || - priv.len != size || - pub.len != size || - shared.len != size) - return CRYPTOLIB_INVALID_PARAM; - return modular_exponentiation_blk(pub, priv, mod, shared, size); -} - -#endif - -uint32_t dh_shared_key_ecdh(block_t curve, block_t priv, block_t pub, block_t shared, uint32_t size, uint32_t curve_flags) -{ - uint32_t error; - - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if ((curve.len != 5 * size && curve.len != 6 * size) || - priv.len != size || - pub.len != 2 * size || - shared.len != 2 * size) - return CRYPTOLIB_INVALID_PARAM; - - // Set command to enable byte-swap - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - - /* Set Configuration register */ - ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); - // Load parameters - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - - // Location 14 -> Private key - mem2CryptoRAM_rev(priv, size, BA414EP_MEMLOC_14); - // Location 12 -> Public key x, Location 13 -> Public key y - point2CryptoRAM_rev(pub, size, BA414EP_MEMLOC_12); - - // Silabs patch - { - BA414EPRegs_t * const BA414EP_REGS = (BA414EPRegs_t *)ADDR_BA414EP_REGS; - - BA414EP_REGS->CommandReg = (BA414EP_REGS->CommandReg & ~BA414EP_CMD_OPTYPE_MASK) | BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE; - - // Check point on curve - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - // The public key is a point on curve: continue with multiplication - BA414EP_REGS->CommandReg = (BA414EP_REGS->CommandReg & ~BA414EP_CMD_OPTYPE_MASK) | BA414EP_OPTYPE_ECC_POINT_MULT; - } - - // Start BA414EP - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - // Fetch the results - CryptoRAM2point_rev(shared, size, BA414EP_MEMLOC_6); - - return CRYPTOLIB_SUCCESS; -} - - - -uint32_t dh_shared_montgomery_key_ecdh(block_t curve, block_t priv, block_t pub, block_t shared, uint32_t size, uint32_t curve_flags) -{ - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (curve.len != 3 * size || - priv.len != size || - pub.len != size || - shared.len != size) - return CRYPTOLIB_INVALID_PARAM; - return ecc_montgomery_mult(curve, curve_flags, size, priv, pub, shared); -} +/** + * @file + * @brief Defines the shared key generation for DH protocoles + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + +#include "sx_dh_alg.h" +#include "cryptolib_def.h" +#include "sx_memcpy.h" +#include "ba414ep_config.h" +#include "sx_primitives.h" +#include "sx_errors.h" + + +#if (DH_MODP_ENABLED) + +uint32_t dh_shared_key_modp(block_t mod, block_t priv, block_t pub, block_t shared, uint32_t size) +{ + if (size > DH_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (mod.len != size || + priv.len != size || + pub.len != size || + shared.len != size) + return CRYPTOLIB_INVALID_PARAM; + return modular_exponentiation_blk(pub, priv, mod, shared, size); +} + +#endif + +uint32_t dh_shared_key_ecdh(block_t curve, block_t priv, block_t pub, block_t shared, uint32_t size, uint32_t curve_flags) +{ + uint32_t error; + + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if ((curve.len != 5 * size && curve.len != 6 * size) || + priv.len != size || + pub.len != 2 * size || + shared.len != 2 * size) + return CRYPTOLIB_INVALID_PARAM; + + // Set command to enable byte-swap + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + + /* Set Configuration register */ + ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); + // Load parameters + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + + // Location 14 -> Private key + mem2CryptoRAM_rev(priv, size, BA414EP_MEMLOC_14); + // Location 12 -> Public key x, Location 13 -> Public key y + point2CryptoRAM_rev(pub, size, BA414EP_MEMLOC_12); + + // Silabs patch + { + BA414EPRegs_t * const BA414EP_REGS = (BA414EPRegs_t *)ADDR_BA414EP_REGS; + + BA414EP_REGS->CommandReg = (BA414EP_REGS->CommandReg & ~BA414EP_CMD_OPTYPE_MASK) | BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE; + + // Check point on curve + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + // The public key is a point on curve: continue with multiplication + BA414EP_REGS->CommandReg = (BA414EP_REGS->CommandReg & ~BA414EP_CMD_OPTYPE_MASK) | BA414EP_OPTYPE_ECC_POINT_MULT; + } + + // Start BA414EP + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + // Fetch the results + CryptoRAM2point_rev(shared, size, BA414EP_MEMLOC_6); + + return CRYPTOLIB_SUCCESS; +} + + + +uint32_t dh_shared_montgomery_key_ecdh(block_t curve, block_t priv, block_t pub, block_t shared, uint32_t size, uint32_t curve_flags) +{ + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (curve.len != 3 * size || + priv.len != size || + pub.len != size || + shared.len != size) + return CRYPTOLIB_INVALID_PARAM; + return ecc_montgomery_mult(curve, curve_flags, size, priv, pub, shared); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c index 3c530a1..d99a0e5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c @@ -1,444 +1,444 @@ -/** - * @file - * @brief This file contains the hard-coded curve parameters - * for common ECC - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - - -#include "sx_ecc_curves.h" -#include "ba414ep_config.h" - - -uint32_t sx_ecc_build_pk_flags(enum sx_ecc_curve_type curve_type) -{ - uint32_t flags = BA414EP_SELCUR_NO_ACCELERATOR; - - if (curve_type == sx_ecc_curve_prime) - flags |= BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME); - else if (curve_type == sx_ecc_curve_binary) - flags |= BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY); - else if (curve_type == sx_ecc_curve_edwards) - flags |= BA414EP_CMD_EDWARDS(1); - else if (curve_type != sx_ecc_curve_unspecified) - CRYPTOLIB_ASSERT(0, "Not a recognized field option"); - - return flags; -} - -uint32_t sx_ecc_curve_bytesize(const sx_ecc_curve_t *curve) -{ - return curve->bytesize; -} - - -static const SX_ALIGNED uint8_t ecc_p192_params[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x99, 0xde, 0xf8, 0x36, 0x14, 0x6b, 0xc9, 0xb1, 0xb4, 0xd2, 0x28, 0x31, //n - 0x18, 0x8d, 0xa8, 0x0e, 0xb0, 0x30, 0x90, 0xf6, 0x7c, 0xbf, 0x20, 0xeb, 0x43, 0xa1, 0x88, 0x00, 0xf4, 0xff, 0x0a, 0xfd, 0x82, 0xff, 0x10, 0x12, //gx - 0x07, 0x19, 0x2b, 0x95, 0xff, 0xc8, 0xda, 0x78, 0x63, 0x10, 0x11, 0xed, 0x6b, 0x24, 0xcd, 0xd5, 0x73, 0xf9, 0x77, 0xa1, 0x1e, 0x79, 0x48, 0x11, //gy - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a - 0x64, 0x21, 0x05, 0x19, 0xe5, 0x9c, 0x80, 0xe7, 0x0f, 0xa7, 0xe9, 0xab, 0x72, 0x24, 0x30, 0x49, 0xfe, 0xb8, 0xde, 0xec, 0xc1, 0x46, 0xb9, 0xb1 }; //b -const sx_ecc_curve_t sx_ecc_curve_p192 = { - .params = CST_BLK_LITARRAY(ecc_p192_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P192, - .bytesize = 24, -}; - - -static const SX_ALIGNED uint8_t ecc_p224_params[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x16, 0xa2, 0xe0, 0xb8, 0xf0, 0x3e, 0x13, 0xdd, 0x29, 0x45, 0x5c, 0x5c, 0x2a, 0x3d, //n - 0xb7, 0x0e, 0x0c, 0xbd, 0x6b, 0xb4, 0xbf, 0x7f, 0x32, 0x13, 0x90, 0xb9, 0x4a, 0x03, 0xc1, 0xd3, 0x56, 0xc2, 0x11, 0x22, 0x34, 0x32, 0x80, 0xd6, 0x11, 0x5c, 0x1d, 0x21, //gx - 0xbd, 0x37, 0x63, 0x88, 0xb5, 0xf7, 0x23, 0xfb, 0x4c, 0x22, 0xdf, 0xe6, 0xcd, 0x43, 0x75, 0xa0, 0x5a, 0x07, 0x47, 0x64, 0x44, 0xd5, 0x81, 0x99, 0x85, 0x00, 0x7e, 0x34, //gy - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, //a - 0xb4, 0x05, 0x0a, 0x85, 0x0c, 0x04, 0xb3, 0xab, 0xf5, 0x41, 0x32, 0x56, 0x50, 0x44, 0xb0, 0xb7, 0xd7, 0xbf, 0xd8, 0xba, 0x27, 0x0b, 0x39, 0x43, 0x23, 0x55, 0xff, 0xb4 }; //b -const sx_ecc_curve_t sx_ecc_curve_p224 = { - .params = CST_BLK_LITARRAY(ecc_p224_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 28, -}; - - -static const SX_ALIGNED uint8_t ecc_p256_params[] = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51, //n - 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96, //gx - 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5, //gy - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a - 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b }; //b -const sx_ecc_curve_t sx_ecc_curve_p256 = { - .params = CST_BLK_LITARRAY(ecc_p256_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P256, - .bytesize = 32, -}; - - -static const SX_ALIGNED uint8_t ecc_p384_params[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, //q - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x63, 0x4d, 0x81, 0xf4, 0x37, 0x2d, 0xdf, 0x58, 0x1a, 0x0d, 0xb2, 0x48, 0xb0, 0xa7, 0x7a, 0xec, 0xec, 0x19, 0x6a, 0xcc, 0xc5, 0x29, 0x73, //n - 0xaa, 0x87, 0xca, 0x22, 0xbe, 0x8b, 0x05, 0x37, 0x8e, 0xb1, 0xc7, 0x1e, 0xf3, 0x20, 0xad, 0x74, 0x6e, 0x1d, 0x3b, 0x62, 0x8b, 0xa7, 0x9b, 0x98, 0x59, 0xf7, 0x41, 0xe0, 0x82, 0x54, 0x2a, 0x38, 0x55, 0x02, 0xf2, 0x5d, 0xbf, 0x55, 0x29, 0x6c, 0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xb7, //gx - 0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x5d, 0x9e, 0x98, 0xbf, 0x92, 0x92, 0xdc, 0x29, 0xf8, 0xf4, 0x1d, 0xbd, 0x28, 0x9a, 0x14, 0x7c, 0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0x0a, 0x60, 0xb1, 0xce, 0x1d, 0x7e, 0x81, 0x9d, 0x7a, 0x43, 0x1d, 0x7c, 0x90, 0xea, 0x0e, 0x5f, //gy - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfc, //a - 0xb3, 0x31, 0x2f, 0xa7, 0xe2, 0x3e, 0xe7, 0xe4, 0x98, 0x8e, 0x05, 0x6b, 0xe3, 0xf8, 0x2d, 0x19, 0x18, 0x1d, 0x9c, 0x6e, 0xfe, 0x81, 0x41, 0x12, 0x03, 0x14, 0x08, 0x8f, 0x50, 0x13, 0x87, 0x5a, 0xc6, 0x56, 0x39, 0x8d, 0x8a, 0x2e, 0xd1, 0x9d, 0x2a, 0x85, 0xc8, 0xed, 0xd3, 0xec, 0x2a, 0xef }; //b -const sx_ecc_curve_t sx_ecc_curve_p384 = { - .params = CST_BLK_LITARRAY(ecc_p384_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P384, - .bytesize = 48, -}; - - -static const SX_ALIGNED uint8_t ecc_p521_params[] = { - 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q - 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x51, 0x86, 0x87, 0x83, 0xbf, 0x2f, 0x96, 0x6b, 0x7f, 0xcc, 0x01, 0x48, 0xf7, 0x09, 0xa5, 0xd0, 0x3b, 0xb5, 0xc9, 0xb8, 0x89, 0x9c, 0x47, 0xae, 0xbb, 0x6f, 0xb7, 0x1e, 0x91, 0x38, 0x64, 0x09, //n - 0x00, 0xc6, 0x85, 0x8e, 0x06, 0xb7, 0x04, 0x04, 0xe9, 0xcd, 0x9e, 0x3e, 0xcb, 0x66, 0x23, 0x95, 0xb4, 0x42, 0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 0xb5, 0x21, 0xf8, 0x28, 0xaf, 0x60, 0x6b, 0x4d, 0x3d, 0xba, 0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28, 0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde, 0x33, 0x48, 0xb3, 0xc1, 0x85, 0x6a, 0x42, 0x9b, 0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66, //gx - 0x01, 0x18, 0x39, 0x29, 0x6a, 0x78, 0x9a, 0x3b, 0xc0, 0x04, 0x5c, 0x8a, 0x5f, 0xb4, 0x2c, 0x7d, 0x1b, 0xd9, 0x98, 0xf5, 0x44, 0x49, 0x57, 0x9b, 0x44, 0x68, 0x17, 0xaf, 0xbd, 0x17, 0x27, 0x3e, 0x66, 0x2c, 0x97, 0xee, 0x72, 0x99, 0x5e, 0xf4, 0x26, 0x40, 0xc5, 0x50, 0xb9, 0x01, 0x3f, 0xad, 0x07, 0x61, 0x35, 0x3c, 0x70, 0x86, 0xa2, 0x72, 0xc2, 0x40, 0x88, 0xbe, 0x94, 0x76, 0x9f, 0xd1, 0x66, 0x50, //gy - 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a - 0x00, 0x51, 0x95, 0x3e, 0xb9, 0x61, 0x8e, 0x1c, 0x9a, 0x1f, 0x92, 0x9a, 0x21, 0xa0, 0xb6, 0x85, 0x40, 0xee, 0xa2, 0xda, 0x72, 0x5b, 0x99, 0xb3, 0x15, 0xf3, 0xb8, 0xb4, 0x89, 0x91, 0x8e, 0xf1, 0x09, 0xe1, 0x56, 0x19, 0x39, 0x51, 0xec, 0x7e, 0x93, 0x7b, 0x16, 0x52, 0xc0, 0xbd, 0x3b, 0xb1, 0xbf, 0x07, 0x35, 0x73, 0xdf, 0x88, 0x3d, 0x2c, 0x34, 0xf1, 0xef, 0x45, 0x1f, 0xd4, 0x6b, 0x50, 0x3f, 0x00 }; //b -const sx_ecc_curve_t sx_ecc_curve_p521 = { - .params = CST_BLK_LITARRAY(ecc_p521_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P521, - .bytesize = 66, -}; - - -static const SX_ALIGNED uint8_t ecc_p256k1_params[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xfc, 0x2f, //q - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xba, 0xae, 0xdc, 0xe6, 0xaf, 0x48, 0xa0, 0x3b, 0xbf, 0xd2, 0x5e, 0x8c, 0xd0, 0x36, 0x41, 0x41, //n - 0x79, 0xbe, 0x66, 0x7e, 0xf9, 0xdc, 0xbb, 0xac, 0x55, 0xa0, 0x62, 0x95, 0xce, 0x87, 0x0b, 0x07, 0x02, 0x9b, 0xfc, 0xdb, 0x2d, 0xce, 0x28, 0xd9, 0x59, 0xf2, 0x81, 0x5b, 0x16, 0xf8, 0x17, 0x98, //gx - 0x48, 0x3a, 0xda, 0x77, 0x26, 0xa3, 0xc4, 0x65, 0x5d, 0xa4, 0xfb, 0xfc, 0x0e, 0x11, 0x08, 0xa8, 0xfd, 0x17, 0xb4, 0x48, 0xa6, 0x85, 0x54, 0x19, 0x9c, 0x47, 0xd0, 0x8f, 0xfb, 0x10, 0xd4, 0xb8, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 }; //b -const sx_ecc_curve_t sx_ecc_curve_p256k1 = { - .params = CST_BLK_LITARRAY(ecc_p256k1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 32, -}; - - -static const SX_ALIGNED uint8_t ecc_b163_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, //q - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x92, 0xfe, 0x77, 0xe7, 0x0c, 0x12, 0xa4, 0x23, 0x4c, 0x33, //n - 0x03, 0xf0, 0xeb, 0xa1, 0x62, 0x86, 0xa2, 0xd5, 0x7e, 0xa0, 0x99, 0x11, 0x68, 0xd4, 0x99, 0x46, 0x37, 0xe8, 0x34, 0x3e, 0x36, //gx - 0x00, 0xd5, 0x1f, 0xbc, 0x6c, 0x71, 0xa0, 0x09, 0x4f, 0xa2, 0xcd, 0xd5, 0x45, 0xb1, 0x1c, 0x5c, 0x0c, 0x79, 0x73, 0x24, 0xf1, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x02, 0x0a, 0x60, 0x19, 0x07, 0xb8, 0xc9, 0x53, 0xca, 0x14, 0x81, 0xeb, 0x10, 0x51, 0x2f, 0x78, 0x74, 0x4a, 0x32, 0x05, 0xfd }; //b -const sx_ecc_curve_t sx_ecc_curve_b163 = { - .params = CST_BLK_LITARRAY(ecc_b163_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 21, -}; - - -static const SX_ALIGNED uint8_t ecc_b233_params[] = { - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0xe9, 0x74, 0xe7, 0x2f, 0x8a, 0x69, 0x22, 0x03, 0x1d, 0x26, 0x03, 0xcf, 0xe0, 0xd7, //n - 0x00, 0xfa, 0xc9, 0xdf, 0xcb, 0xac, 0x83, 0x13, 0xbb, 0x21, 0x39, 0xf1, 0xbb, 0x75, 0x5f, 0xef, 0x65, 0xbc, 0x39, 0x1f, 0x8b, 0x36, 0xf8, 0xf8, 0xeb, 0x73, 0x71, 0xfd, 0x55, 0x8b, //gx - 0x01, 0x00, 0x6a, 0x08, 0xa4, 0x19, 0x03, 0x35, 0x06, 0x78, 0xe5, 0x85, 0x28, 0xbe, 0xbf, 0x8a, 0x0b, 0xef, 0xf8, 0x67, 0xa7, 0xca, 0x36, 0x71, 0x6f, 0x7e, 0x01, 0xf8, 0x10, 0x52, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x00, 0x66, 0x64, 0x7e, 0xde, 0x6c, 0x33, 0x2c, 0x7f, 0x8c, 0x09, 0x23, 0xbb, 0x58, 0x21, 0x3b, 0x33, 0x3b, 0x20, 0xe9, 0xce, 0x42, 0x81, 0xfe, 0x11, 0x5f, 0x7d, 0x8f, 0x90, 0xad }; //b -const sx_ecc_curve_t sx_ecc_curve_b233 = { - .params = CST_BLK_LITARRAY(ecc_b233_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 30, -}; - - -static const SX_ALIGNED uint8_t ecc_b283_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xa1, //q - 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x90, 0x39, 0x96, 0x60, 0xfc, 0x93, 0x8a, 0x90, 0x16, 0x5b, 0x04, 0x2a, 0x7c, 0xef, 0xad, 0xb3, 0x07, //n - 0x05, 0xf9, 0x39, 0x25, 0x8d, 0xb7, 0xdd, 0x90, 0xe1, 0x93, 0x4f, 0x8c, 0x70, 0xb0, 0xdf, 0xec, 0x2e, 0xed, 0x25, 0xb8, 0x55, 0x7e, 0xac, 0x9c, 0x80, 0xe2, 0xe1, 0x98, 0xf8, 0xcd, 0xbe, 0xcd, 0x86, 0xb1, 0x20, 0x53, //gx - 0x03, 0x67, 0x68, 0x54, 0xfe, 0x24, 0x14, 0x1c, 0xb9, 0x8f, 0xe6, 0xd4, 0xb2, 0x0d, 0x02, 0xb4, 0x51, 0x6f, 0xf7, 0x02, 0x35, 0x0e, 0xdd, 0xb0, 0x82, 0x67, 0x79, 0xc8, 0x13, 0xf0, 0xdf, 0x45, 0xbe, 0x81, 0x12, 0xf4, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x02, 0x7b, 0x68, 0x0a, 0xc8, 0xb8, 0x59, 0x6d, 0xa5, 0xa4, 0xaf, 0x8a, 0x19, 0xa0, 0x30, 0x3f, 0xca, 0x97, 0xfd, 0x76, 0x45, 0x30, 0x9f, 0xa2, 0xa5, 0x81, 0x48, 0x5a, 0xf6, 0x26, 0x3e, 0x31, 0x3b, 0x79, 0xa2, 0xf5 }; //b -const sx_ecc_curve_t sx_ecc_curve_b283 = { - .params = CST_BLK_LITARRAY(ecc_b283_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 36, -}; - - -static const SX_ALIGNED uint8_t ecc_b409_params[] = { - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe2, 0xaa, 0xd6, 0xa6, 0x12, 0xf3, 0x33, 0x07, 0xbe, 0x5f, 0xa4, 0x7c, 0x3c, 0x9e, 0x05, 0x2f, 0x83, 0x81, 0x64, 0xcd, 0x37, 0xd9, 0xa2, 0x11, 0x73, //n - 0x01, 0x5d, 0x48, 0x60, 0xd0, 0x88, 0xdd, 0xb3, 0x49, 0x6b, 0x0c, 0x60, 0x64, 0x75, 0x62, 0x60, 0x44, 0x1c, 0xde, 0x4a, 0xf1, 0x77, 0x1d, 0x4d, 0xb0, 0x1f, 0xfe, 0x5b, 0x34, 0xe5, 0x97, 0x03, 0xdc, 0x25, 0x5a, 0x86, 0x8a, 0x11, 0x80, 0x51, 0x56, 0x03, 0xae, 0xab, 0x60, 0x79, 0x4e, 0x54, 0xbb, 0x79, 0x96, 0xa7, //gx - 0x00, 0x61, 0xb1, 0xcf, 0xab, 0x6b, 0xe5, 0xf3, 0x2b, 0xbf, 0xa7, 0x83, 0x24, 0xed, 0x10, 0x6a, 0x76, 0x36, 0xb9, 0xc5, 0xa7, 0xbd, 0x19, 0x8d, 0x01, 0x58, 0xaa, 0x4f, 0x54, 0x88, 0xd0, 0x8f, 0x38, 0x51, 0x4f, 0x1f, 0xdf, 0x4b, 0x4f, 0x40, 0xd2, 0x18, 0x1b, 0x36, 0x81, 0xc3, 0x64, 0xba, 0x02, 0x73, 0xc7, 0x06, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x00, 0x21, 0xa5, 0xc2, 0xc8, 0xee, 0x9f, 0xeb, 0x5c, 0x4b, 0x9a, 0x75, 0x3b, 0x7b, 0x47, 0x6b, 0x7f, 0xd6, 0x42, 0x2e, 0xf1, 0xf3, 0xdd, 0x67, 0x47, 0x61, 0xfa, 0x99, 0xd6, 0xac, 0x27, 0xc8, 0xa9, 0xa1, 0x97, 0xb2, 0x72, 0x82, 0x2f, 0x6c, 0xd5, 0x7a, 0x55, 0xaa, 0x4f, 0x50, 0xae, 0x31, 0x7b, 0x13, 0x54, 0x5f }; //b -const sx_ecc_curve_t sx_ecc_curve_b409 = { - .params = CST_BLK_LITARRAY(ecc_b409_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 52, -}; - - -static const SX_ALIGNED uint8_t ecc_b571_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25, //q - 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0x61, 0xce, 0x18, 0xff, 0x55, 0x98, 0x73, 0x08, 0x05, 0x9b, 0x18, 0x68, 0x23, 0x85, 0x1e, 0xc7, 0xdd, 0x9c, 0xa1, 0x16, 0x1d, 0xe9, 0x3d, 0x51, 0x74, 0xd6, 0x6e, 0x83, 0x82, 0xe9, 0xbb, 0x2f, 0xe8, 0x4e, 0x47, //n - 0x03, 0x03, 0x00, 0x1d, 0x34, 0xb8, 0x56, 0x29, 0x6c, 0x16, 0xc0, 0xd4, 0x0d, 0x3c, 0xd7, 0x75, 0x0a, 0x93, 0xd1, 0xd2, 0x95, 0x5f, 0xa8, 0x0a, 0xa5, 0xf4, 0x0f, 0xc8, 0xdb, 0x7b, 0x2a, 0xbd, 0xbd, 0xe5, 0x39, 0x50, 0xf4, 0xc0, 0xd2, 0x93, 0xcd, 0xd7, 0x11, 0xa3, 0x5b, 0x67, 0xfb, 0x14, 0x99, 0xae, 0x60, 0x03, 0x86, 0x14, 0xf1, 0x39, 0x4a, 0xbf, 0xa3, 0xb4, 0xc8, 0x50, 0xd9, 0x27, 0xe1, 0xe7, 0x76, 0x9c, 0x8e, 0xec, 0x2d, 0x19, //gx - 0x03, 0x7b, 0xf2, 0x73, 0x42, 0xda, 0x63, 0x9b, 0x6d, 0xcc, 0xff, 0xfe, 0xb7, 0x3d, 0x69, 0xd7, 0x8c, 0x6c, 0x27, 0xa6, 0x00, 0x9c, 0xbb, 0xca, 0x19, 0x80, 0xf8, 0x53, 0x39, 0x21, 0xe8, 0xa6, 0x84, 0x42, 0x3e, 0x43, 0xba, 0xb0, 0x8a, 0x57, 0x62, 0x91, 0xaf, 0x8f, 0x46, 0x1b, 0xb2, 0xa8, 0xb3, 0x53, 0x1d, 0x2f, 0x04, 0x85, 0xc1, 0x9b, 0x16, 0xe2, 0xf1, 0x51, 0x6e, 0x23, 0xdd, 0x3c, 0x1a, 0x48, 0x27, 0xaf, 0x1b, 0x8a, 0xc1, 0x5b, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x02, 0xf4, 0x0e, 0x7e, 0x22, 0x21, 0xf2, 0x95, 0xde, 0x29, 0x71, 0x17, 0xb7, 0xf3, 0xd6, 0x2f, 0x5c, 0x6a, 0x97, 0xff, 0xcb, 0x8c, 0xef, 0xf1, 0xcd, 0x6b, 0xa8, 0xce, 0x4a, 0x9a, 0x18, 0xad, 0x84, 0xff, 0xab, 0xbd, 0x8e, 0xfa, 0x59, 0x33, 0x2b, 0xe7, 0xad, 0x67, 0x56, 0xa6, 0x6e, 0x29, 0x4a, 0xfd, 0x18, 0x5a, 0x78, 0xff, 0x12, 0xaa, 0x52, 0x0e, 0x4d, 0xe7, 0x39, 0xba, 0xca, 0x0c, 0x7f, 0xfe, 0xff, 0x7f, 0x29, 0x55, 0x72, 0x7a }; //b -const sx_ecc_curve_t sx_ecc_curve_b571 = { - .params = CST_BLK_LITARRAY(ecc_b571_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 72, -}; - - -static const SX_ALIGNED uint8_t ecc_k163_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, //q - 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x08, 0xa2, 0xe0, 0xcc, 0x0d, 0x99, 0xf8, 0xa5, 0xef, //n - 0x02, 0xfe, 0x13, 0xc0, 0x53, 0x7b, 0xbc, 0x11, 0xac, 0xaa, 0x07, 0xd7, 0x93, 0xde, 0x4e, 0x6d, 0x5e, 0x5c, 0x94, 0xee, 0xe8, //gx - 0x02, 0x89, 0x07, 0x0f, 0xb0, 0x5d, 0x38, 0xff, 0x58, 0x32, 0x1f, 0x2e, 0x80, 0x05, 0x36, 0xd5, 0x38, 0xcc, 0xda, 0xa3, 0xd9, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b -const sx_ecc_curve_t sx_ecc_curve_k163 = { - .params = CST_BLK_LITARRAY(ecc_k163_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 21, -}; - - -static const SX_ALIGNED uint8_t ecc_k233_params[] = { - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x9D, 0x5B, 0xB9, 0x15, 0xBC, 0xD4, 0x6E, 0xFB, 0x1A, 0xD5, 0xF1, 0x73, 0xAB, 0xDF, //n - 0x01, 0x72, 0x32, 0xba, 0x85, 0x3a, 0x7e, 0x73, 0x1a, 0xf1, 0x29, 0xf2, 0x2f, 0xf4, 0x14, 0x95, 0x63, 0xa4, 0x19, 0xc2, 0x6b, 0xf5, 0x0a, 0x4c, 0x9d, 0x6e, 0xef, 0xad, 0x61, 0x26, //gx - 0x01, 0xdb, 0x53, 0x7d, 0xec, 0xe8, 0x19, 0xb7, 0xf7, 0x0f, 0x55, 0x5a, 0x67, 0xc4, 0x27, 0xa8, 0xcd, 0x9b, 0xf1, 0x8a, 0xeb, 0x9b, 0x56, 0xe0, 0xc1, 0x10, 0x56, 0xfa, 0xe6, 0xa3, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b -const sx_ecc_curve_t sx_ecc_curve_k233 = { - .params = CST_BLK_LITARRAY(ecc_k233_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 30, -}; - - -static const SX_ALIGNED uint8_t ecc_k283_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xa1, //q - 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE9, 0xAE, 0x2E, 0xD0, 0x75, 0x77, 0x26, 0x5D, 0xFF, 0x7F, 0x94, 0x45, 0x1E, 0x06, 0x1E, 0x16, 0x3C, 0x61, //n - 0x05, 0x03, 0x21, 0x3f, 0x78, 0xca, 0x44, 0x88, 0x3f, 0x1a, 0x3b, 0x81, 0x62, 0xf1, 0x88, 0xe5, 0x53, 0xcd, 0x26, 0x5f, 0x23, 0xc1, 0x56, 0x7a, 0x16, 0x87, 0x69, 0x13, 0xb0, 0xc2, 0xac, 0x24, 0x58, 0x49, 0x28, 0x36, //a - 0x01, 0xcc, 0xda, 0x38, 0x0f, 0x1c, 0x9e, 0x31, 0x8d, 0x90, 0xf9, 0x5d, 0x07, 0xe5, 0x42, 0x6f, 0xe8, 0x7e, 0x45, 0xc0, 0xe8, 0x18, 0x46, 0x98, 0xe4, 0x59, 0x62, 0x36, 0x4e, 0x34, 0x11, 0x61, 0x77, 0xdd, 0x22, 0x59, //b - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //gx - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //gy -const sx_ecc_curve_t sx_ecc_curve_k283 = { - .params = CST_BLK_LITARRAY(ecc_k283_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 36, -}; - - -static const SX_ALIGNED uint8_t ecc_k409_params[] = { - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q - 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x5F, 0x83, 0xB2, 0xD4, 0xEA, 0x20, 0x40, 0x0E, 0xC4, 0x55, 0x7D, 0x5E, 0xD3, 0xE3, 0xE7, 0xCA, 0x5B, 0x4B, 0x5C, 0x83, 0xB8, 0xE0, 0x1E, 0x5F, 0xCF, //n - 0x00, 0x60, 0xf0, 0x5f, 0x65, 0x8f, 0x49, 0xc1, 0xad, 0x3a, 0xb1, 0x89, 0x0f, 0x71, 0x84, 0x21, 0x0e, 0xfd, 0x09, 0x87, 0xe3, 0x07, 0xc8, 0x4c, 0x27, 0xac, 0xcf, 0xb8, 0xf9, 0xf6, 0x7c, 0xc2, 0xc4, 0x60, 0x18, 0x9e, 0xb5, 0xaa, 0xaa, 0x62, 0xee, 0x22, 0x2e, 0xb1, 0xb3, 0x55, 0x40, 0xcf, 0xe9, 0x02, 0x37, 0x46, //gx - 0x01, 0xe3, 0x69, 0x05, 0x0b, 0x7c, 0x4e, 0x42, 0xac, 0xba, 0x1d, 0xac, 0xbf, 0x04, 0x29, 0x9c, 0x34, 0x60, 0x78, 0x2f, 0x91, 0x8e, 0xa4, 0x27, 0xe6, 0x32, 0x51, 0x65, 0xe9, 0xea, 0x10, 0xe3, 0xda, 0x5f, 0x6c, 0x42, 0xe9, 0xc5, 0x52, 0x15, 0xaa, 0x9c, 0xa2, 0x7a, 0x58, 0x63, 0xec, 0x48, 0xd8, 0xe0, 0x28, 0x6b, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b -const sx_ecc_curve_t sx_ecc_curve_k409 = { - .params = CST_BLK_LITARRAY(ecc_k409_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 52, -}; - - -static const SX_ALIGNED uint8_t ecc_k571_params[] = { - 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25, //q - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x18, 0x50, 0xE1, 0xF1, 0x9A, 0x63, 0xE4, 0xB3, 0x91, 0xA8, 0xDB, 0x91, 0x7F, 0x41, 0x38, 0xB6, 0x30, 0xD8, 0x4B, 0xE5, 0xD6, 0x39, 0x38, 0x1E, 0x91, 0xDE, 0xB4, 0x5C, 0xFE, 0x77, 0x8F, 0x63, 0x7C, 0x10, 0x01, //n - 0x02, 0x6e, 0xb7, 0xa8, 0x59, 0x92, 0x3f, 0xbc, 0x82, 0x18, 0x96, 0x31, 0xf8, 0x10, 0x3f, 0xe4, 0xac, 0x9c, 0xa2, 0x97, 0x00, 0x12, 0xd5, 0xd4, 0x60, 0x24, 0x80, 0x48, 0x01, 0x84, 0x1c, 0xa4, 0x43, 0x70, 0x95, 0x84, 0x93, 0xb2, 0x05, 0xe6, 0x47, 0xda, 0x30, 0x4d, 0xb4, 0xce, 0xb0, 0x8c, 0xbb, 0xd1, 0xba, 0x39, 0x49, 0x47, 0x76, 0xfb, 0x98, 0x8b, 0x47, 0x17, 0x4d, 0xca, 0x88, 0xc7, 0xe2, 0x94, 0x52, 0x83, 0xa0, 0x1c, 0x89, 0x72, //gx - 0x03, 0x49, 0xdc, 0x80, 0x7f, 0x4f, 0xbf, 0x37, 0x4f, 0x4a, 0xea, 0xde, 0x3b, 0xca, 0x95, 0x31, 0x4d, 0xd5, 0x8c, 0xec, 0x9f, 0x30, 0x7a, 0x54, 0xff, 0xc6, 0x1e, 0xfc, 0x00, 0x6d, 0x8a, 0x2c, 0x9d, 0x49, 0x79, 0xc0, 0xac, 0x44, 0xae, 0xa7, 0x4f, 0xbe, 0xbb, 0xb9, 0xf7, 0x72, 0xae, 0xdc, 0xb6, 0x20, 0xb0, 0x1a, 0x7b, 0xa7, 0xaf, 0x1b, 0x32, 0x04, 0x30, 0xc8, 0x59, 0x19, 0x84, 0xf6, 0x01, 0xcd, 0x4c, 0x14, 0x3e, 0xf1, 0xc7, 0xa3, //gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b -const sx_ecc_curve_t sx_ecc_curve_k571 = { - .params = CST_BLK_LITARRAY(ecc_k571_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 72, -}; - - -static const SX_ALIGNED uint8_t ecc_e521_params[] = { - 0x01, 0xff, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q - 0x00, 0x7f, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x15, 0xb6, 0xc6, 0x47, 0x46, 0xfc, 0x85, 0xf7, 0x36, 0xb8, 0xaf, 0x5e, 0x7e, 0xc5, 0x3f, 0x04, 0xfb, 0xd8, 0xc4, 0x56, 0x9a, 0x8f, 0x1f, 0x45, 0x40, 0xea, 0x24, 0x35, 0xf5, 0x18, 0x0d, 0x6b, //n - 0x00, 0x75, 0x2c, 0xb4,0x5c, 0x48, 0x64, 0x8b, 0x18, 0x9d, 0xf9, 0x0c, 0xb2, 0x29, 0x6b, 0x28, 0x78, 0xa3, 0xbf, 0xd9, 0xf4, 0x2f, 0xc6, 0xc8, 0x18, 0xec, 0x8b, 0xf3, 0xc9, 0xc0, 0xc6, 0x20, 0x39, 0x13, 0xf6, 0xec, 0xc5, 0xcc, 0xc7, 0x24, 0x34, 0xb1, 0xae, 0x94, 0x9d, 0x56, 0x8f, 0xc9, 0x9c, 0x60, 0x59, 0xd0, 0xfb, 0x13, 0x36, 0x48, 0x38, 0xaa, 0x30, 0x2a, 0x94, 0x0a, 0x2f, 0x19, 0xba, 0x6c, //gx - 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, //gy - 0x01, 0xff, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x43, 0x31 }; //d -const sx_ecc_curve_t sx_ecc_curve_e521 = { - .params = CST_BLK_LITARRAY(ecc_e521_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_CMD_EDWARDS(1) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 66, -}; - -/********************************************************** -** Curve25519 - (Little-endian) -**********************************************************/ -static const SX_ALIGNED uint8_t ecc_curve25519_params[] = { - 0xED, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, // p - 0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // a - 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; // x -const sx_ecc_curve_t sx_ecc_curve_curve25519 = { - .params = CST_BLK_LITARRAY(ecc_curve25519_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_X25519, - .bytesize = 32, -}; - -/********************************************************** -** Curve448 - (Little-endian) -**********************************************************/ - -static const SX_ALIGNED uint8_t ecc_curve448_params[] = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, //p - 0xA6, 0x62, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; //x -const sx_ecc_curve_t sx_ecc_curve_curve448 = { - .params = CST_BLK_LITARRAY(ecc_curve448_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 56, -}; - -/********************************************************** -** Curve SM2 - Fp-256 v1 -**********************************************************/ -static const SX_ALIGNED uint8_t ecc_sm2_p256_params_v1[] = { - 0x85, 0x42, 0xd6, 0x9e, 0x4c, 0x04, 0x4f, 0x18, 0xe8, 0xb9, 0x24, 0x35, 0xbf, 0x6f, 0xf7, 0xde, 0x45, 0x72, 0x83, 0x91, 0x5c, 0x45, 0x51, 0x7d, 0x72, 0x2e, 0xdb, 0x8b, 0x08, 0xf1, 0xdf, 0xc3, //p - 0x85, 0x42, 0xd6, 0x9e, 0x4c, 0x04, 0x4f, 0x18, 0xe8, 0xb9, 0x24, 0x35, 0xbf, 0x6f, 0xf7, 0xdd, 0x29, 0x77, 0x20, 0x63, 0x04, 0x85, 0x62, 0x8d, 0x5a, 0xe7, 0x4e, 0xe7, 0xc3, 0x2e, 0x79, 0xb7, //n - 0x42, 0x1d, 0xeb, 0xd6, 0x1b, 0x62, 0xea, 0xb6, 0x74, 0x64, 0x34, 0xeb, 0xc3, 0xcc, 0x31, 0x5e, 0x32, 0x22, 0x0b, 0x3b, 0xad, 0xd5, 0x0b, 0xdc, 0x4c, 0x4e, 0x6c, 0x14, 0x7f, 0xed, 0xd4, 0x3d, //Gx - 0x06, 0x80, 0x51, 0x2b, 0xcb, 0xb4, 0x2c, 0x07, 0xd4, 0x73, 0x49, 0xd2, 0x15, 0x3b, 0x70, 0xc4, 0xe5, 0xd7, 0xfd, 0xfc, 0xbf, 0xa3, 0x6e, 0xa1, 0xa8, 0x58, 0x41, 0xb9, 0xe4, 0x6e, 0x09, 0xa2, //Gy - 0x78, 0x79, 0x68, 0xb4, 0xfa, 0x32, 0xc3, 0xfd, 0x24, 0x17, 0x84, 0x2e, 0x73, 0xbb, 0xfe, 0xff, 0x2f, 0x3c, 0x84, 0x8b, 0x68, 0x31, 0xd7, 0xe0, 0xec, 0x65, 0x22, 0x8b, 0x39, 0x37, 0xe4, 0x98, //a - 0x63, 0xe4, 0xc6, 0xd3, 0xb2, 0x3b, 0x0c, 0x84, 0x9c, 0xf8, 0x42, 0x41, 0x48, 0x4b, 0xfe, 0x48, 0xf6, 0x1d, 0x59, 0xa5, 0xb1, 0x6b, 0xa0, 0x6e, 0x6e, 0x12, 0xd1, 0xda, 0x27, 0xc5, 0x24, 0x9a //b -}; -const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v1 = { - .params = CST_BLK_LITARRAY(ecc_sm2_p256_params_v1), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 32, -}; - -/********************************************************** -** Curve SM2 - Fp-256 v2 -**********************************************************/ -static const SX_ALIGNED uint8_t ecc_sm2_p256_params_v2[] = { - 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //p - 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x72, 0x03, 0xdf, 0x6b, 0x21, 0xc6, 0x05, 0x2b, 0x53, 0xbb, 0xf4, 0x09, 0x39, 0xd5, 0x41, 0x23, //n - 0x32, 0xc4, 0xae, 0x2c, 0x1f, 0x19, 0x81, 0x19, 0x5f, 0x99, 0x04, 0x46, 0x6a, 0x39, 0xc9, 0x94, 0x8f, 0xe3, 0x0b, 0xbf, 0xf2, 0x66, 0x0b, 0xe1, 0x71, 0x5a, 0x45, 0x89, 0x33, 0x4c, 0x74, 0xc7, //Gx - 0xbc, 0x37, 0x36, 0xa2, 0xf4, 0xf6, 0x77, 0x9c, 0x59, 0xbd, 0xce, 0xe3, 0x6b, 0x69, 0x21, 0x53, 0xd0, 0xa9, 0x87, 0x7c, 0xc6, 0x2a, 0x47, 0x40, 0x02, 0xdf, 0x32, 0xe5, 0x21, 0x39, 0xf0, 0xa0, //Gy - 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a - 0x28, 0xe9, 0xfa, 0x9e, 0x9d, 0x9f, 0x5e, 0x34, 0x4d, 0x5a, 0x9e, 0x4b, 0xcf, 0x65, 0x09, 0xa7, 0xf3, 0x97, 0x89, 0xf5, 0x15, 0xab, 0x8f, 0x92, 0xdd, 0xbc, 0xbd, 0x41, 0x4d, 0x94, 0x0e, 0x93 //b -}; -const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v2 = { - .params = CST_BLK_LITARRAY(ecc_sm2_p256_params_v2), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 32, -}; - -/********************************************************** -** Curve SM2 - F^m-257 -**********************************************************/ -static const SX_ALIGNED uint8_t ecc_sm2_fm257_params[] = { - 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, //q - 0x00, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbc, 0x97, 0x2c, 0xf7, 0xe6, 0xb6, 0xf9, 0x00, 0x94, 0x5b, 0x3c, 0x6a, 0x0c, 0xf6, 0x16, 0x1d, //n - 0x00, 0xcd, 0xb9, 0xca, 0x7f, 0x1e, 0x6b, 0x04, 0x41, 0xf6, 0x58, 0x34, 0x3f, 0x4b, 0x10, 0x29, 0x7c, 0x0e, 0xf9, 0xb6, 0x49, 0x10, 0x82, 0x40, 0x0a, 0x62, 0xe7, 0xa7, 0x48, 0x57, 0x35, 0xfa, 0xdd, //Gx - 0x01, 0x3d, 0xe7, 0x4d, 0xa6, 0x59, 0x51, 0xc4, 0xd7, 0x6d, 0xc8, 0x92, 0x20, 0xd5, 0xf7, 0x77, 0x7a, 0x61, 0x1b, 0x1c, 0x38, 0xba, 0xe2, 0x60, 0xb1, 0x75, 0x95, 0x1d, 0xc8, 0x06, 0x0c, 0x2b, 0x3e, //Gy - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a - 0x00, 0xe7, 0x8b, 0xcd, 0x09, 0x74, 0x6c, 0x20, 0x23, 0x78, 0xa7, 0xe7, 0x2b, 0x12, 0xbc, 0xe0, 0x02, 0x66, 0xb9, 0x62, 0x7e, 0xcb, 0x0b, 0x5a, 0x25, 0x36, 0x7a, 0xd1, 0xad, 0x4c, 0xc6, 0x24, 0x2b //b -}; -const sx_ecc_curve_t sx_ecc_curve_sm2_fm257 = { - .params = CST_BLK_LITARRAY(ecc_sm2_fm257_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, - .bytesize = 33, -}; - -/********************************************************** -** Brainpool curves -** refrence: https://tools.ietf.org/html/rfc5639#section-3.1 -**********************************************************/ - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP160r1_params[] = { - 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, 0x60, 0xDF, 0xC7, 0xAD, 0x95, 0xB3, 0xD8, 0x13, 0x95, 0x15, 0x62, 0x0F, //q - 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, 0x60, 0xDF, 0x59, 0x91, 0xD4, 0x50, 0x29, 0x40, 0x9E, 0x60, 0xFC, 0x09, //n - 0xBE, 0xD5, 0xAF, 0x16, 0xEA, 0x3F, 0x6A, 0x4F, 0x62, 0x93, 0x8C, 0x46, 0x31, 0xEB, 0x5A, 0xF7, 0xBD, 0xBC, 0xDB, 0xC3, //gx - 0x16, 0x67, 0xCB, 0x47, 0x7A, 0x1A, 0x8E, 0xC3, 0x38, 0xF9, 0x47, 0x41, 0x66, 0x9C, 0x97, 0x63, 0x16, 0xDA, 0x63, 0x21, //gy - 0x34, 0x0E, 0x7B, 0xE2, 0xA2, 0x80, 0xEB, 0x74, 0xE2, 0xBE, 0x61, 0xBA, 0xDA, 0x74, 0x5D, 0x97, 0xE8, 0xF7, 0xC3, 0x00, //a - 0x1E, 0x58, 0x9A, 0x85, 0x95, 0x42, 0x34, 0x12, 0x13, 0x4F, 0xAA, 0x2D, 0xBD, 0xEC, 0x95, 0xC8, 0xD8, 0x67, 0x5E, 0x58, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP160r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP160r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 20, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP192r1_params[] = { - 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, 0xA7, 0xA3, 0x46, 0x30, 0x93, 0xD1, 0x8D, 0xB7, 0x8F, 0xCE, 0x47, 0x6D, 0xE1, 0xA8, 0x62, 0x97, //q - 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, 0xA7, 0xA3, 0x46, 0x2F, 0x9E, 0x9E, 0x91, 0x6B, 0x5B, 0xE8, 0xF1, 0x02, 0x9A, 0xC4, 0xAC, 0xC1, //n - 0xC0, 0xA0, 0x64, 0x7E, 0xAA, 0xB6, 0xA4, 0x87, 0x53, 0xB0, 0x33, 0xC5, 0x6C, 0xB0, 0xF0, 0x90, 0x0A, 0x2F, 0x5C, 0x48, 0x53, 0x37, 0x5F, 0xD6, //gx - 0x14, 0xB6, 0x90, 0x86, 0x6A, 0xBD, 0x5B, 0xB8, 0x8B, 0x5F, 0x48, 0x28, 0xC1, 0x49, 0x00, 0x02, 0xE6, 0x77, 0x3F, 0xA2, 0xFA, 0x29, 0x9B, 0x8F, //gy - 0x6A, 0x91, 0x17, 0x40, 0x76, 0xB1, 0xE0, 0xE1, 0x9C, 0x39, 0xC0, 0x31, 0xFE, 0x86, 0x85, 0xC1, 0xCA, 0xE0, 0x40, 0xE5, 0xC6, 0x9A, 0x28, 0xEF, //a - 0x46, 0x9A, 0x28, 0xEF, 0x7C, 0x28, 0xCC, 0xA3, 0xDC, 0x72, 0x1D, 0x04, 0x4F, 0x44, 0x96, 0xBC, 0xCA, 0x7E, 0xF4, 0x14, 0x6F, 0xBF, 0x25, 0xC9, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP192r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP192r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 24, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP224r1_params[] = { - 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD1, 0xD7, 0x87, 0xB0, 0x9F, 0x07, 0x57, 0x97, 0xDA, 0x89, 0xF5, 0x7E, 0xC8, 0xC0, 0xFF, //q - 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD0, 0xFB, 0x98, 0xD1, 0x16, 0xBC, 0x4B, 0x6D, 0xDE, 0xBC, 0xA3, 0xA5, 0xA7, 0x93, 0x9F, //n - 0x0D, 0x90, 0x29, 0xAD, 0x2C, 0x7E, 0x5C, 0xF4, 0x34, 0x08, 0x23, 0xB2, 0xA8, 0x7D, 0xC6, 0x8C, 0x9E, 0x4C, 0xE3, 0x17, 0x4C, 0x1E, 0x6E, 0xFD, 0xEE, 0x12, 0xC0, 0x7D, //gx - 0x58, 0xAA, 0x56, 0xF7, 0x72, 0xC0, 0x72, 0x6F, 0x24, 0xC6, 0xB8, 0x9E, 0x4E, 0xCD, 0xAC, 0x24, 0x35, 0x4B, 0x9E, 0x99, 0xCA, 0xA3, 0xF6, 0xD3, 0x76, 0x14, 0x02, 0xCD, //gy - 0x68, 0xA5, 0xE6, 0x2C, 0xA9, 0xCE, 0x6C, 0x1C, 0x29, 0x98, 0x03, 0xA6, 0xC1, 0x53, 0x0B, 0x51, 0x4E, 0x18, 0x2A, 0xD8, 0xB0, 0x04, 0x2A, 0x59, 0xCA, 0xD2, 0x9F, 0x43, //a - 0x25, 0x80, 0xF6, 0x3C, 0xCF, 0xE4, 0x41, 0x38, 0x87, 0x07, 0x13, 0xB1, 0xA9, 0x23, 0x69, 0xE3, 0x3E, 0x21, 0x35, 0xD2, 0x66, 0xDB, 0xB3, 0x72, 0x38, 0x6C, 0x40, 0x0B, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP224r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP224r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 28, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP256r1_params[] = { - 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77, //q - 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7, //n - 0x8B, 0xD2, 0xAE, 0xB9, 0xCB, 0x7E, 0x57, 0xCB, 0x2C, 0x4B, 0x48, 0x2F, 0xFC, 0x81, 0xB7, 0xAF, 0xB9, 0xDE, 0x27, 0xE1, 0xE3, 0xBD, 0x23, 0xC2, 0x3A, 0x44, 0x53, 0xBD, 0x9A, 0xCE, 0x32, 0x62, //gx - 0x54, 0x7E, 0xF8, 0x35, 0xC3, 0xDA, 0xC4, 0xFD, 0x97, 0xF8, 0x46, 0x1A, 0x14, 0x61, 0x1D, 0xC9, 0xC2, 0x77, 0x45, 0x13, 0x2D, 0xED, 0x8E, 0x54, 0x5C, 0x1D, 0x54, 0xC7, 0x2F, 0x04, 0x69, 0x97, //gy - 0x7D, 0x5A, 0x09, 0x75, 0xFC, 0x2C, 0x30, 0x57, 0xEE, 0xF6, 0x75, 0x30, 0x41, 0x7A, 0xFF, 0xE7, 0xFB, 0x80, 0x55, 0xC1, 0x26, 0xDC, 0x5C, 0x6C, 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9, //a - 0x26, 0xDC, 0x5C, 0x6C, 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9, 0xBB, 0xD7, 0x7C, 0xBF, 0x95, 0x84, 0x16, 0x29, 0x5C, 0xF7, 0xE1, 0xCE, 0x6B, 0xCC, 0xDC, 0x18, 0xFF, 0x8C, 0x07, 0xB6, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP256r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP256r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 32, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP320r1_params[] = { - 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, 0xF9, 0x8F, 0xCF, 0xA6, 0xF6, 0xF4, 0x0D, 0xEF, 0x4F, 0x92, 0xB9, 0xEC, 0x78, 0x93, 0xEC, 0x28, 0xFC, 0xD4, 0x12, 0xB1, 0xF1, 0xB3, 0x2E, 0x27, //q - 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, 0xF9, 0x8F, 0xCF, 0xA5, 0xB6, 0x8F, 0x12, 0xA3, 0x2D, 0x48, 0x2E, 0xC7, 0xEE, 0x86, 0x58, 0xE9, 0x86, 0x91, 0x55, 0x5B, 0x44, 0xC5, 0x93, 0x11, //n - 0x43, 0xBD, 0x7E, 0x9A, 0xFB, 0x53, 0xD8, 0xB8, 0x52, 0x89, 0xBC, 0xC4, 0x8E, 0xE5, 0xBF, 0xE6, 0xF2, 0x01, 0x37, 0xD1, 0x0A, 0x08, 0x7E, 0xB6, 0xE7, 0x87, 0x1E, 0x2A, 0x10, 0xA5, 0x99, 0xC7, 0x10, 0xAF, 0x8D, 0x0D, 0x39, 0xE2, 0x06, 0x11, //gx - 0x14, 0xFD, 0xD0, 0x55, 0x45, 0xEC, 0x1C, 0xC8, 0xAB, 0x40, 0x93, 0x24, 0x7F, 0x77, 0x27, 0x5E, 0x07, 0x43, 0xFF, 0xED, 0x11, 0x71, 0x82, 0xEA, 0xA9, 0xC7, 0x78, 0x77, 0xAA, 0xAC, 0x6A, 0xC7, 0xD3, 0x52, 0x45, 0xD1, 0x69, 0x2E, 0x8E, 0xE1, //gy - 0x3E, 0xE3, 0x0B, 0x56, 0x8F, 0xBA, 0xB0, 0xF8, 0x83, 0xCC, 0xEB, 0xD4, 0x6D, 0x3F, 0x3B, 0xB8, 0xA2, 0xA7, 0x35, 0x13, 0xF5, 0xEB, 0x79, 0xDA, 0x66, 0x19, 0x0E, 0xB0, 0x85, 0xFF, 0xA9, 0xF4, 0x92, 0xF3, 0x75, 0xA9, 0x7D, 0x86, 0x0E, 0xB4, //a - 0x52, 0x08, 0x83, 0x94, 0x9D, 0xFD, 0xBC, 0x42, 0xD3, 0xAD, 0x19, 0x86, 0x40, 0x68, 0x8A, 0x6F, 0xE1, 0x3F, 0x41, 0x34, 0x95, 0x54, 0xB4, 0x9A, 0xCC, 0x31, 0xDC, 0xCD, 0x88, 0x45, 0x39, 0x81, 0x6F, 0x5E, 0xB4, 0xAC, 0x8F, 0xB1, 0xF1, 0xA6, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP320r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP320r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 40, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP384r1_params[] = { - 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB4, 0x12, 0xB1, 0xDA, 0x19, 0x7F, 0xB7, 0x11, 0x23, 0xAC, 0xD3, 0xA7, 0x29, 0x90, 0x1D, 0x1A, 0x71, 0x87, 0x47, 0x00, 0x13, 0x31, 0x07, 0xEC, 0x53, //q - 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB3, 0x1F, 0x16, 0x6E, 0x6C, 0xAC, 0x04, 0x25, 0xA7, 0xCF, 0x3A, 0xB6, 0xAF, 0x6B, 0x7F, 0xC3, 0x10, 0x3B, 0x88, 0x32, 0x02, 0xE9, 0x04, 0x65, 0x65, //n - 0x1D, 0x1C, 0x64, 0xF0, 0x68, 0xCF, 0x45, 0xFF, 0xA2, 0xA6, 0x3A, 0x81, 0xB7, 0xC1, 0x3F, 0x6B, 0x88, 0x47, 0xA3, 0xE7, 0x7E, 0xF1, 0x4F, 0xE3, 0xDB, 0x7F, 0xCA, 0xFE, 0x0C, 0xBD, 0x10, 0xE8, 0xE8, 0x26, 0xE0, 0x34, 0x36, 0xD6, 0x46, 0xAA, 0xEF, 0x87, 0xB2, 0xE2, 0x47, 0xD4, 0xAF, 0x1E, //gx - 0x8A, 0xBE, 0x1D, 0x75, 0x20, 0xF9, 0xC2, 0xA4, 0x5C, 0xB1, 0xEB, 0x8E, 0x95, 0xCF, 0xD5, 0x52, 0x62, 0xB7, 0x0B, 0x29, 0xFE, 0xEC, 0x58, 0x64, 0xE1, 0x9C, 0x05, 0x4F, 0xF9, 0x91, 0x29, 0x28, 0x0E, 0x46, 0x46, 0x21, 0x77, 0x91, 0x81, 0x11, 0x42, 0x82, 0x03, 0x41, 0x26, 0x3C, 0x53, 0x15, //gy - 0x7B, 0xC3, 0x82, 0xC6, 0x3D, 0x8C, 0x15, 0x0C, 0x3C, 0x72, 0x08, 0x0A, 0xCE, 0x05, 0xAF, 0xA0, 0xC2, 0xBE, 0xA2, 0x8E, 0x4F, 0xB2, 0x27, 0x87, 0x13, 0x91, 0x65, 0xEF, 0xBA, 0x91, 0xF9, 0x0F, 0x8A, 0xA5, 0x81, 0x4A, 0x50, 0x3A, 0xD4, 0xEB, 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26, //a - 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26, 0x8B, 0x39, 0xB5, 0x54, 0x16, 0xF0, 0x44, 0x7C, 0x2F, 0xB7, 0x7D, 0xE1, 0x07, 0xDC, 0xD2, 0xA6, 0x2E, 0x88, 0x0E, 0xA5, 0x3E, 0xEB, 0x62, 0xD5, 0x7C, 0xB4, 0x39, 0x02, 0x95, 0xDB, 0xC9, 0x94, 0x3A, 0xB7, 0x86, 0x96, 0xFA, 0x50, 0x4C, 0x11, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP384r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP384r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 48, -}; - -static const SX_ALIGNED uint8_t sx_ecc_brainpoolP512r1_params[] = { - 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x71, 0x7D, 0x4D, 0x9B, 0x00, 0x9B, 0xC6, 0x68, 0x42, 0xAE, 0xCD, 0xA1, 0x2A, 0xE6, 0xA3, 0x80, 0xE6, 0x28, 0x81, 0xFF, 0x2F, 0x2D, 0x82, 0xC6, 0x85, 0x28, 0xAA, 0x60, 0x56, 0x58, 0x3A, 0x48, 0xF3, //q - 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x70, 0x55, 0x3E, 0x5C, 0x41, 0x4C, 0xA9, 0x26, 0x19, 0x41, 0x86, 0x61, 0x19, 0x7F, 0xAC, 0x10, 0x47, 0x1D, 0xB1, 0xD3, 0x81, 0x08, 0x5D, 0xDA, 0xDD, 0xB5, 0x87, 0x96, 0x82, 0x9C, 0xA9, 0x00, 0x69, //n - 0x81, 0xAE, 0xE4, 0xBD, 0xD8, 0x2E, 0xD9, 0x64, 0x5A, 0x21, 0x32, 0x2E, 0x9C, 0x4C, 0x6A, 0x93, 0x85, 0xED, 0x9F, 0x70, 0xB5, 0xD9, 0x16, 0xC1, 0xB4, 0x3B, 0x62, 0xEE, 0xF4, 0xD0, 0x09, 0x8E, 0xFF, 0x3B, 0x1F, 0x78, 0xE2, 0xD0, 0xD4, 0x8D, 0x50, 0xD1, 0x68, 0x7B, 0x93, 0xB9, 0x7D, 0x5F, 0x7C, 0x6D, 0x50, 0x47, 0x40, 0x6A, 0x5E, 0x68, 0x8B, 0x35, 0x22, 0x09, 0xBC, 0xB9, 0xF8, 0x22, //gx - 0x7D, 0xDE, 0x38, 0x5D, 0x56, 0x63, 0x32, 0xEC, 0xC0, 0xEA, 0xBF, 0xA9, 0xCF, 0x78, 0x22, 0xFD, 0xF2, 0x09, 0xF7, 0x00, 0x24, 0xA5, 0x7B, 0x1A, 0xA0, 0x00, 0xC5, 0x5B, 0x88, 0x1F, 0x81, 0x11, 0xB2, 0xDC, 0xDE, 0x49, 0x4A, 0x5F, 0x48, 0x5E, 0x5B, 0xCA, 0x4B, 0xD8, 0x8A, 0x27, 0x63, 0xAE, 0xD1, 0xCA, 0x2B, 0x2F, 0xA8, 0xF0, 0x54, 0x06, 0x78, 0xCD, 0x1E, 0x0F, 0x3A, 0xD8, 0x08, 0x92, //gy - 0x78, 0x30, 0xA3, 0x31, 0x8B, 0x60, 0x3B, 0x89, 0xE2, 0x32, 0x71, 0x45, 0xAC, 0x23, 0x4C, 0xC5, 0x94, 0xCB, 0xDD, 0x8D, 0x3D, 0xF9, 0x16, 0x10, 0xA8, 0x34, 0x41, 0xCA, 0xEA, 0x98, 0x63, 0xBC, 0x2D, 0xED, 0x5D, 0x5A, 0xA8, 0x25, 0x3A, 0xA1, 0x0A, 0x2E, 0xF1, 0xC9, 0x8B, 0x9A, 0xC8, 0xB5, 0x7F, 0x11, 0x17, 0xA7, 0x2B, 0xF2, 0xC7, 0xB9, 0xE7, 0xC1, 0xAC, 0x4D, 0x77, 0xFC, 0x94, 0xCA, //a - 0x3D, 0xF9, 0x16, 0x10, 0xA8, 0x34, 0x41, 0xCA, 0xEA, 0x98, 0x63, 0xBC, 0x2D, 0xED, 0x5D, 0x5A, 0xA8, 0x25, 0x3A, 0xA1, 0x0A, 0x2E, 0xF1, 0xC9, 0x8B, 0x9A, 0xC8, 0xB5, 0x7F, 0x11, 0x17, 0xA7, 0x2B, 0xF2, 0xC7, 0xB9, 0xE7, 0xC1, 0xAC, 0x4D, 0x77, 0xFC, 0x94, 0xCA, 0xDC, 0x08, 0x3E, 0x67, 0x98, 0x40, 0x50, 0xB7, 0x5E, 0xBA, 0xE5, 0xDD, 0x28, 0x09, 0xBD, 0x63, 0x80, 0x16, 0xF7, 0x23, }; //b -const sx_ecc_curve_t sx_ecc_brainpoolP512r1 = { - .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP512r1_params), - .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), - .bytesize = 64, +/** + * @file + * @brief This file contains the hard-coded curve parameters + * for common ECC + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + + +#include "sx_ecc_curves.h" +#include "ba414ep_config.h" + + +uint32_t sx_ecc_build_pk_flags(enum sx_ecc_curve_type curve_type) +{ + uint32_t flags = BA414EP_SELCUR_NO_ACCELERATOR; + + if (curve_type == sx_ecc_curve_prime) + flags |= BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME); + else if (curve_type == sx_ecc_curve_binary) + flags |= BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY); + else if (curve_type == sx_ecc_curve_edwards) + flags |= BA414EP_CMD_EDWARDS(1); + else if (curve_type != sx_ecc_curve_unspecified) + CRYPTOLIB_ASSERT(0, "Not a recognized field option"); + + return flags; +} + +uint32_t sx_ecc_curve_bytesize(const sx_ecc_curve_t *curve) +{ + return curve->bytesize; +} + + +static const SX_ALIGNED uint8_t ecc_p192_params[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x99, 0xde, 0xf8, 0x36, 0x14, 0x6b, 0xc9, 0xb1, 0xb4, 0xd2, 0x28, 0x31, //n + 0x18, 0x8d, 0xa8, 0x0e, 0xb0, 0x30, 0x90, 0xf6, 0x7c, 0xbf, 0x20, 0xeb, 0x43, 0xa1, 0x88, 0x00, 0xf4, 0xff, 0x0a, 0xfd, 0x82, 0xff, 0x10, 0x12, //gx + 0x07, 0x19, 0x2b, 0x95, 0xff, 0xc8, 0xda, 0x78, 0x63, 0x10, 0x11, 0xed, 0x6b, 0x24, 0xcd, 0xd5, 0x73, 0xf9, 0x77, 0xa1, 0x1e, 0x79, 0x48, 0x11, //gy + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a + 0x64, 0x21, 0x05, 0x19, 0xe5, 0x9c, 0x80, 0xe7, 0x0f, 0xa7, 0xe9, 0xab, 0x72, 0x24, 0x30, 0x49, 0xfe, 0xb8, 0xde, 0xec, 0xc1, 0x46, 0xb9, 0xb1 }; //b +const sx_ecc_curve_t sx_ecc_curve_p192 = { + .params = CST_BLK_LITARRAY(ecc_p192_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P192, + .bytesize = 24, +}; + + +static const SX_ALIGNED uint8_t ecc_p224_params[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x16, 0xa2, 0xe0, 0xb8, 0xf0, 0x3e, 0x13, 0xdd, 0x29, 0x45, 0x5c, 0x5c, 0x2a, 0x3d, //n + 0xb7, 0x0e, 0x0c, 0xbd, 0x6b, 0xb4, 0xbf, 0x7f, 0x32, 0x13, 0x90, 0xb9, 0x4a, 0x03, 0xc1, 0xd3, 0x56, 0xc2, 0x11, 0x22, 0x34, 0x32, 0x80, 0xd6, 0x11, 0x5c, 0x1d, 0x21, //gx + 0xbd, 0x37, 0x63, 0x88, 0xb5, 0xf7, 0x23, 0xfb, 0x4c, 0x22, 0xdf, 0xe6, 0xcd, 0x43, 0x75, 0xa0, 0x5a, 0x07, 0x47, 0x64, 0x44, 0xd5, 0x81, 0x99, 0x85, 0x00, 0x7e, 0x34, //gy + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, //a + 0xb4, 0x05, 0x0a, 0x85, 0x0c, 0x04, 0xb3, 0xab, 0xf5, 0x41, 0x32, 0x56, 0x50, 0x44, 0xb0, 0xb7, 0xd7, 0xbf, 0xd8, 0xba, 0x27, 0x0b, 0x39, 0x43, 0x23, 0x55, 0xff, 0xb4 }; //b +const sx_ecc_curve_t sx_ecc_curve_p224 = { + .params = CST_BLK_LITARRAY(ecc_p224_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 28, +}; + + +static const SX_ALIGNED uint8_t ecc_p256_params[] = { + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51, //n + 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96, //gx + 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5, //gy + 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a + 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b }; //b +const sx_ecc_curve_t sx_ecc_curve_p256 = { + .params = CST_BLK_LITARRAY(ecc_p256_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P256, + .bytesize = 32, +}; + + +static const SX_ALIGNED uint8_t ecc_p384_params[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, //q + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc7, 0x63, 0x4d, 0x81, 0xf4, 0x37, 0x2d, 0xdf, 0x58, 0x1a, 0x0d, 0xb2, 0x48, 0xb0, 0xa7, 0x7a, 0xec, 0xec, 0x19, 0x6a, 0xcc, 0xc5, 0x29, 0x73, //n + 0xaa, 0x87, 0xca, 0x22, 0xbe, 0x8b, 0x05, 0x37, 0x8e, 0xb1, 0xc7, 0x1e, 0xf3, 0x20, 0xad, 0x74, 0x6e, 0x1d, 0x3b, 0x62, 0x8b, 0xa7, 0x9b, 0x98, 0x59, 0xf7, 0x41, 0xe0, 0x82, 0x54, 0x2a, 0x38, 0x55, 0x02, 0xf2, 0x5d, 0xbf, 0x55, 0x29, 0x6c, 0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xb7, //gx + 0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x5d, 0x9e, 0x98, 0xbf, 0x92, 0x92, 0xdc, 0x29, 0xf8, 0xf4, 0x1d, 0xbd, 0x28, 0x9a, 0x14, 0x7c, 0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0x0a, 0x60, 0xb1, 0xce, 0x1d, 0x7e, 0x81, 0x9d, 0x7a, 0x43, 0x1d, 0x7c, 0x90, 0xea, 0x0e, 0x5f, //gy + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfc, //a + 0xb3, 0x31, 0x2f, 0xa7, 0xe2, 0x3e, 0xe7, 0xe4, 0x98, 0x8e, 0x05, 0x6b, 0xe3, 0xf8, 0x2d, 0x19, 0x18, 0x1d, 0x9c, 0x6e, 0xfe, 0x81, 0x41, 0x12, 0x03, 0x14, 0x08, 0x8f, 0x50, 0x13, 0x87, 0x5a, 0xc6, 0x56, 0x39, 0x8d, 0x8a, 0x2e, 0xd1, 0x9d, 0x2a, 0x85, 0xc8, 0xed, 0xd3, 0xec, 0x2a, 0xef }; //b +const sx_ecc_curve_t sx_ecc_curve_p384 = { + .params = CST_BLK_LITARRAY(ecc_p384_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P384, + .bytesize = 48, +}; + + +static const SX_ALIGNED uint8_t ecc_p521_params[] = { + 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q + 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x51, 0x86, 0x87, 0x83, 0xbf, 0x2f, 0x96, 0x6b, 0x7f, 0xcc, 0x01, 0x48, 0xf7, 0x09, 0xa5, 0xd0, 0x3b, 0xb5, 0xc9, 0xb8, 0x89, 0x9c, 0x47, 0xae, 0xbb, 0x6f, 0xb7, 0x1e, 0x91, 0x38, 0x64, 0x09, //n + 0x00, 0xc6, 0x85, 0x8e, 0x06, 0xb7, 0x04, 0x04, 0xe9, 0xcd, 0x9e, 0x3e, 0xcb, 0x66, 0x23, 0x95, 0xb4, 0x42, 0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 0xb5, 0x21, 0xf8, 0x28, 0xaf, 0x60, 0x6b, 0x4d, 0x3d, 0xba, 0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28, 0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde, 0x33, 0x48, 0xb3, 0xc1, 0x85, 0x6a, 0x42, 0x9b, 0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66, //gx + 0x01, 0x18, 0x39, 0x29, 0x6a, 0x78, 0x9a, 0x3b, 0xc0, 0x04, 0x5c, 0x8a, 0x5f, 0xb4, 0x2c, 0x7d, 0x1b, 0xd9, 0x98, 0xf5, 0x44, 0x49, 0x57, 0x9b, 0x44, 0x68, 0x17, 0xaf, 0xbd, 0x17, 0x27, 0x3e, 0x66, 0x2c, 0x97, 0xee, 0x72, 0x99, 0x5e, 0xf4, 0x26, 0x40, 0xc5, 0x50, 0xb9, 0x01, 0x3f, 0xad, 0x07, 0x61, 0x35, 0x3c, 0x70, 0x86, 0xa2, 0x72, 0xc2, 0x40, 0x88, 0xbe, 0x94, 0x76, 0x9f, 0xd1, 0x66, 0x50, //gy + 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a + 0x00, 0x51, 0x95, 0x3e, 0xb9, 0x61, 0x8e, 0x1c, 0x9a, 0x1f, 0x92, 0x9a, 0x21, 0xa0, 0xb6, 0x85, 0x40, 0xee, 0xa2, 0xda, 0x72, 0x5b, 0x99, 0xb3, 0x15, 0xf3, 0xb8, 0xb4, 0x89, 0x91, 0x8e, 0xf1, 0x09, 0xe1, 0x56, 0x19, 0x39, 0x51, 0xec, 0x7e, 0x93, 0x7b, 0x16, 0x52, 0xc0, 0xbd, 0x3b, 0xb1, 0xbf, 0x07, 0x35, 0x73, 0xdf, 0x88, 0x3d, 0x2c, 0x34, 0xf1, 0xef, 0x45, 0x1f, 0xd4, 0x6b, 0x50, 0x3f, 0x00 }; //b +const sx_ecc_curve_t sx_ecc_curve_p521 = { + .params = CST_BLK_LITARRAY(ecc_p521_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_P521, + .bytesize = 66, +}; + + +static const SX_ALIGNED uint8_t ecc_p256k1_params[] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xfc, 0x2f, //q + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xba, 0xae, 0xdc, 0xe6, 0xaf, 0x48, 0xa0, 0x3b, 0xbf, 0xd2, 0x5e, 0x8c, 0xd0, 0x36, 0x41, 0x41, //n + 0x79, 0xbe, 0x66, 0x7e, 0xf9, 0xdc, 0xbb, 0xac, 0x55, 0xa0, 0x62, 0x95, 0xce, 0x87, 0x0b, 0x07, 0x02, 0x9b, 0xfc, 0xdb, 0x2d, 0xce, 0x28, 0xd9, 0x59, 0xf2, 0x81, 0x5b, 0x16, 0xf8, 0x17, 0x98, //gx + 0x48, 0x3a, 0xda, 0x77, 0x26, 0xa3, 0xc4, 0x65, 0x5d, 0xa4, 0xfb, 0xfc, 0x0e, 0x11, 0x08, 0xa8, 0xfd, 0x17, 0xb4, 0x48, 0xa6, 0x85, 0x54, 0x19, 0x9c, 0x47, 0xd0, 0x8f, 0xfb, 0x10, 0xd4, 0xb8, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 }; //b +const sx_ecc_curve_t sx_ecc_curve_p256k1 = { + .params = CST_BLK_LITARRAY(ecc_p256k1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 32, +}; + + +static const SX_ALIGNED uint8_t ecc_b163_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, //q + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x92, 0xfe, 0x77, 0xe7, 0x0c, 0x12, 0xa4, 0x23, 0x4c, 0x33, //n + 0x03, 0xf0, 0xeb, 0xa1, 0x62, 0x86, 0xa2, 0xd5, 0x7e, 0xa0, 0x99, 0x11, 0x68, 0xd4, 0x99, 0x46, 0x37, 0xe8, 0x34, 0x3e, 0x36, //gx + 0x00, 0xd5, 0x1f, 0xbc, 0x6c, 0x71, 0xa0, 0x09, 0x4f, 0xa2, 0xcd, 0xd5, 0x45, 0xb1, 0x1c, 0x5c, 0x0c, 0x79, 0x73, 0x24, 0xf1, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x02, 0x0a, 0x60, 0x19, 0x07, 0xb8, 0xc9, 0x53, 0xca, 0x14, 0x81, 0xeb, 0x10, 0x51, 0x2f, 0x78, 0x74, 0x4a, 0x32, 0x05, 0xfd }; //b +const sx_ecc_curve_t sx_ecc_curve_b163 = { + .params = CST_BLK_LITARRAY(ecc_b163_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 21, +}; + + +static const SX_ALIGNED uint8_t ecc_b233_params[] = { + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0xe9, 0x74, 0xe7, 0x2f, 0x8a, 0x69, 0x22, 0x03, 0x1d, 0x26, 0x03, 0xcf, 0xe0, 0xd7, //n + 0x00, 0xfa, 0xc9, 0xdf, 0xcb, 0xac, 0x83, 0x13, 0xbb, 0x21, 0x39, 0xf1, 0xbb, 0x75, 0x5f, 0xef, 0x65, 0xbc, 0x39, 0x1f, 0x8b, 0x36, 0xf8, 0xf8, 0xeb, 0x73, 0x71, 0xfd, 0x55, 0x8b, //gx + 0x01, 0x00, 0x6a, 0x08, 0xa4, 0x19, 0x03, 0x35, 0x06, 0x78, 0xe5, 0x85, 0x28, 0xbe, 0xbf, 0x8a, 0x0b, 0xef, 0xf8, 0x67, 0xa7, 0xca, 0x36, 0x71, 0x6f, 0x7e, 0x01, 0xf8, 0x10, 0x52, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x00, 0x66, 0x64, 0x7e, 0xde, 0x6c, 0x33, 0x2c, 0x7f, 0x8c, 0x09, 0x23, 0xbb, 0x58, 0x21, 0x3b, 0x33, 0x3b, 0x20, 0xe9, 0xce, 0x42, 0x81, 0xfe, 0x11, 0x5f, 0x7d, 0x8f, 0x90, 0xad }; //b +const sx_ecc_curve_t sx_ecc_curve_b233 = { + .params = CST_BLK_LITARRAY(ecc_b233_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 30, +}; + + +static const SX_ALIGNED uint8_t ecc_b283_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xa1, //q + 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0x90, 0x39, 0x96, 0x60, 0xfc, 0x93, 0x8a, 0x90, 0x16, 0x5b, 0x04, 0x2a, 0x7c, 0xef, 0xad, 0xb3, 0x07, //n + 0x05, 0xf9, 0x39, 0x25, 0x8d, 0xb7, 0xdd, 0x90, 0xe1, 0x93, 0x4f, 0x8c, 0x70, 0xb0, 0xdf, 0xec, 0x2e, 0xed, 0x25, 0xb8, 0x55, 0x7e, 0xac, 0x9c, 0x80, 0xe2, 0xe1, 0x98, 0xf8, 0xcd, 0xbe, 0xcd, 0x86, 0xb1, 0x20, 0x53, //gx + 0x03, 0x67, 0x68, 0x54, 0xfe, 0x24, 0x14, 0x1c, 0xb9, 0x8f, 0xe6, 0xd4, 0xb2, 0x0d, 0x02, 0xb4, 0x51, 0x6f, 0xf7, 0x02, 0x35, 0x0e, 0xdd, 0xb0, 0x82, 0x67, 0x79, 0xc8, 0x13, 0xf0, 0xdf, 0x45, 0xbe, 0x81, 0x12, 0xf4, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x02, 0x7b, 0x68, 0x0a, 0xc8, 0xb8, 0x59, 0x6d, 0xa5, 0xa4, 0xaf, 0x8a, 0x19, 0xa0, 0x30, 0x3f, 0xca, 0x97, 0xfd, 0x76, 0x45, 0x30, 0x9f, 0xa2, 0xa5, 0x81, 0x48, 0x5a, 0xf6, 0x26, 0x3e, 0x31, 0x3b, 0x79, 0xa2, 0xf5 }; //b +const sx_ecc_curve_t sx_ecc_curve_b283 = { + .params = CST_BLK_LITARRAY(ecc_b283_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 36, +}; + + +static const SX_ALIGNED uint8_t ecc_b409_params[] = { + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe2, 0xaa, 0xd6, 0xa6, 0x12, 0xf3, 0x33, 0x07, 0xbe, 0x5f, 0xa4, 0x7c, 0x3c, 0x9e, 0x05, 0x2f, 0x83, 0x81, 0x64, 0xcd, 0x37, 0xd9, 0xa2, 0x11, 0x73, //n + 0x01, 0x5d, 0x48, 0x60, 0xd0, 0x88, 0xdd, 0xb3, 0x49, 0x6b, 0x0c, 0x60, 0x64, 0x75, 0x62, 0x60, 0x44, 0x1c, 0xde, 0x4a, 0xf1, 0x77, 0x1d, 0x4d, 0xb0, 0x1f, 0xfe, 0x5b, 0x34, 0xe5, 0x97, 0x03, 0xdc, 0x25, 0x5a, 0x86, 0x8a, 0x11, 0x80, 0x51, 0x56, 0x03, 0xae, 0xab, 0x60, 0x79, 0x4e, 0x54, 0xbb, 0x79, 0x96, 0xa7, //gx + 0x00, 0x61, 0xb1, 0xcf, 0xab, 0x6b, 0xe5, 0xf3, 0x2b, 0xbf, 0xa7, 0x83, 0x24, 0xed, 0x10, 0x6a, 0x76, 0x36, 0xb9, 0xc5, 0xa7, 0xbd, 0x19, 0x8d, 0x01, 0x58, 0xaa, 0x4f, 0x54, 0x88, 0xd0, 0x8f, 0x38, 0x51, 0x4f, 0x1f, 0xdf, 0x4b, 0x4f, 0x40, 0xd2, 0x18, 0x1b, 0x36, 0x81, 0xc3, 0x64, 0xba, 0x02, 0x73, 0xc7, 0x06, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x00, 0x21, 0xa5, 0xc2, 0xc8, 0xee, 0x9f, 0xeb, 0x5c, 0x4b, 0x9a, 0x75, 0x3b, 0x7b, 0x47, 0x6b, 0x7f, 0xd6, 0x42, 0x2e, 0xf1, 0xf3, 0xdd, 0x67, 0x47, 0x61, 0xfa, 0x99, 0xd6, 0xac, 0x27, 0xc8, 0xa9, 0xa1, 0x97, 0xb2, 0x72, 0x82, 0x2f, 0x6c, 0xd5, 0x7a, 0x55, 0xaa, 0x4f, 0x50, 0xae, 0x31, 0x7b, 0x13, 0x54, 0x5f }; //b +const sx_ecc_curve_t sx_ecc_curve_b409 = { + .params = CST_BLK_LITARRAY(ecc_b409_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 52, +}; + + +static const SX_ALIGNED uint8_t ecc_b571_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25, //q + 0x03, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe6, 0x61, 0xce, 0x18, 0xff, 0x55, 0x98, 0x73, 0x08, 0x05, 0x9b, 0x18, 0x68, 0x23, 0x85, 0x1e, 0xc7, 0xdd, 0x9c, 0xa1, 0x16, 0x1d, 0xe9, 0x3d, 0x51, 0x74, 0xd6, 0x6e, 0x83, 0x82, 0xe9, 0xbb, 0x2f, 0xe8, 0x4e, 0x47, //n + 0x03, 0x03, 0x00, 0x1d, 0x34, 0xb8, 0x56, 0x29, 0x6c, 0x16, 0xc0, 0xd4, 0x0d, 0x3c, 0xd7, 0x75, 0x0a, 0x93, 0xd1, 0xd2, 0x95, 0x5f, 0xa8, 0x0a, 0xa5, 0xf4, 0x0f, 0xc8, 0xdb, 0x7b, 0x2a, 0xbd, 0xbd, 0xe5, 0x39, 0x50, 0xf4, 0xc0, 0xd2, 0x93, 0xcd, 0xd7, 0x11, 0xa3, 0x5b, 0x67, 0xfb, 0x14, 0x99, 0xae, 0x60, 0x03, 0x86, 0x14, 0xf1, 0x39, 0x4a, 0xbf, 0xa3, 0xb4, 0xc8, 0x50, 0xd9, 0x27, 0xe1, 0xe7, 0x76, 0x9c, 0x8e, 0xec, 0x2d, 0x19, //gx + 0x03, 0x7b, 0xf2, 0x73, 0x42, 0xda, 0x63, 0x9b, 0x6d, 0xcc, 0xff, 0xfe, 0xb7, 0x3d, 0x69, 0xd7, 0x8c, 0x6c, 0x27, 0xa6, 0x00, 0x9c, 0xbb, 0xca, 0x19, 0x80, 0xf8, 0x53, 0x39, 0x21, 0xe8, 0xa6, 0x84, 0x42, 0x3e, 0x43, 0xba, 0xb0, 0x8a, 0x57, 0x62, 0x91, 0xaf, 0x8f, 0x46, 0x1b, 0xb2, 0xa8, 0xb3, 0x53, 0x1d, 0x2f, 0x04, 0x85, 0xc1, 0x9b, 0x16, 0xe2, 0xf1, 0x51, 0x6e, 0x23, 0xdd, 0x3c, 0x1a, 0x48, 0x27, 0xaf, 0x1b, 0x8a, 0xc1, 0x5b, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x02, 0xf4, 0x0e, 0x7e, 0x22, 0x21, 0xf2, 0x95, 0xde, 0x29, 0x71, 0x17, 0xb7, 0xf3, 0xd6, 0x2f, 0x5c, 0x6a, 0x97, 0xff, 0xcb, 0x8c, 0xef, 0xf1, 0xcd, 0x6b, 0xa8, 0xce, 0x4a, 0x9a, 0x18, 0xad, 0x84, 0xff, 0xab, 0xbd, 0x8e, 0xfa, 0x59, 0x33, 0x2b, 0xe7, 0xad, 0x67, 0x56, 0xa6, 0x6e, 0x29, 0x4a, 0xfd, 0x18, 0x5a, 0x78, 0xff, 0x12, 0xaa, 0x52, 0x0e, 0x4d, 0xe7, 0x39, 0xba, 0xca, 0x0c, 0x7f, 0xfe, 0xff, 0x7f, 0x29, 0x55, 0x72, 0x7a }; //b +const sx_ecc_curve_t sx_ecc_curve_b571 = { + .params = CST_BLK_LITARRAY(ecc_b571_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 72, +}; + + +static const SX_ALIGNED uint8_t ecc_k163_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc9, //q + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x01, 0x08, 0xa2, 0xe0, 0xcc, 0x0d, 0x99, 0xf8, 0xa5, 0xef, //n + 0x02, 0xfe, 0x13, 0xc0, 0x53, 0x7b, 0xbc, 0x11, 0xac, 0xaa, 0x07, 0xd7, 0x93, 0xde, 0x4e, 0x6d, 0x5e, 0x5c, 0x94, 0xee, 0xe8, //gx + 0x02, 0x89, 0x07, 0x0f, 0xb0, 0x5d, 0x38, 0xff, 0x58, 0x32, 0x1f, 0x2e, 0x80, 0x05, 0x36, 0xd5, 0x38, 0xcc, 0xda, 0xa3, 0xd9, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //a + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b +const sx_ecc_curve_t sx_ecc_curve_k163 = { + .params = CST_BLK_LITARRAY(ecc_k163_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 21, +}; + + +static const SX_ALIGNED uint8_t ecc_k233_params[] = { + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x9D, 0x5B, 0xB9, 0x15, 0xBC, 0xD4, 0x6E, 0xFB, 0x1A, 0xD5, 0xF1, 0x73, 0xAB, 0xDF, //n + 0x01, 0x72, 0x32, 0xba, 0x85, 0x3a, 0x7e, 0x73, 0x1a, 0xf1, 0x29, 0xf2, 0x2f, 0xf4, 0x14, 0x95, 0x63, 0xa4, 0x19, 0xc2, 0x6b, 0xf5, 0x0a, 0x4c, 0x9d, 0x6e, 0xef, 0xad, 0x61, 0x26, //gx + 0x01, 0xdb, 0x53, 0x7d, 0xec, 0xe8, 0x19, 0xb7, 0xf7, 0x0f, 0x55, 0x5a, 0x67, 0xc4, 0x27, 0xa8, 0xcd, 0x9b, 0xf1, 0x8a, 0xeb, 0x9b, 0x56, 0xe0, 0xc1, 0x10, 0x56, 0xfa, 0xe6, 0xa3, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b +const sx_ecc_curve_t sx_ecc_curve_k233 = { + .params = CST_BLK_LITARRAY(ecc_k233_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 30, +}; + + +static const SX_ALIGNED uint8_t ecc_k283_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xa1, //q + 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xE9, 0xAE, 0x2E, 0xD0, 0x75, 0x77, 0x26, 0x5D, 0xFF, 0x7F, 0x94, 0x45, 0x1E, 0x06, 0x1E, 0x16, 0x3C, 0x61, //n + 0x05, 0x03, 0x21, 0x3f, 0x78, 0xca, 0x44, 0x88, 0x3f, 0x1a, 0x3b, 0x81, 0x62, 0xf1, 0x88, 0xe5, 0x53, 0xcd, 0x26, 0x5f, 0x23, 0xc1, 0x56, 0x7a, 0x16, 0x87, 0x69, 0x13, 0xb0, 0xc2, 0xac, 0x24, 0x58, 0x49, 0x28, 0x36, //a + 0x01, 0xcc, 0xda, 0x38, 0x0f, 0x1c, 0x9e, 0x31, 0x8d, 0x90, 0xf9, 0x5d, 0x07, 0xe5, 0x42, 0x6f, 0xe8, 0x7e, 0x45, 0xc0, 0xe8, 0x18, 0x46, 0x98, 0xe4, 0x59, 0x62, 0x36, 0x4e, 0x34, 0x11, 0x61, 0x77, 0xdd, 0x22, 0x59, //b + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //gx + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //gy +const sx_ecc_curve_t sx_ecc_curve_k283 = { + .params = CST_BLK_LITARRAY(ecc_k283_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 36, +}; + + +static const SX_ALIGNED uint8_t ecc_k409_params[] = { + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, //q + 0x00, 0x7F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x5F, 0x83, 0xB2, 0xD4, 0xEA, 0x20, 0x40, 0x0E, 0xC4, 0x55, 0x7D, 0x5E, 0xD3, 0xE3, 0xE7, 0xCA, 0x5B, 0x4B, 0x5C, 0x83, 0xB8, 0xE0, 0x1E, 0x5F, 0xCF, //n + 0x00, 0x60, 0xf0, 0x5f, 0x65, 0x8f, 0x49, 0xc1, 0xad, 0x3a, 0xb1, 0x89, 0x0f, 0x71, 0x84, 0x21, 0x0e, 0xfd, 0x09, 0x87, 0xe3, 0x07, 0xc8, 0x4c, 0x27, 0xac, 0xcf, 0xb8, 0xf9, 0xf6, 0x7c, 0xc2, 0xc4, 0x60, 0x18, 0x9e, 0xb5, 0xaa, 0xaa, 0x62, 0xee, 0x22, 0x2e, 0xb1, 0xb3, 0x55, 0x40, 0xcf, 0xe9, 0x02, 0x37, 0x46, //gx + 0x01, 0xe3, 0x69, 0x05, 0x0b, 0x7c, 0x4e, 0x42, 0xac, 0xba, 0x1d, 0xac, 0xbf, 0x04, 0x29, 0x9c, 0x34, 0x60, 0x78, 0x2f, 0x91, 0x8e, 0xa4, 0x27, 0xe6, 0x32, 0x51, 0x65, 0xe9, 0xea, 0x10, 0xe3, 0xda, 0x5f, 0x6c, 0x42, 0xe9, 0xc5, 0x52, 0x15, 0xaa, 0x9c, 0xa2, 0x7a, 0x58, 0x63, 0xec, 0x48, 0xd8, 0xe0, 0x28, 0x6b, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b +const sx_ecc_curve_t sx_ecc_curve_k409 = { + .params = CST_BLK_LITARRAY(ecc_k409_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 52, +}; + + +static const SX_ALIGNED uint8_t ecc_k571_params[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x25, //q + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x18, 0x50, 0xE1, 0xF1, 0x9A, 0x63, 0xE4, 0xB3, 0x91, 0xA8, 0xDB, 0x91, 0x7F, 0x41, 0x38, 0xB6, 0x30, 0xD8, 0x4B, 0xE5, 0xD6, 0x39, 0x38, 0x1E, 0x91, 0xDE, 0xB4, 0x5C, 0xFE, 0x77, 0x8F, 0x63, 0x7C, 0x10, 0x01, //n + 0x02, 0x6e, 0xb7, 0xa8, 0x59, 0x92, 0x3f, 0xbc, 0x82, 0x18, 0x96, 0x31, 0xf8, 0x10, 0x3f, 0xe4, 0xac, 0x9c, 0xa2, 0x97, 0x00, 0x12, 0xd5, 0xd4, 0x60, 0x24, 0x80, 0x48, 0x01, 0x84, 0x1c, 0xa4, 0x43, 0x70, 0x95, 0x84, 0x93, 0xb2, 0x05, 0xe6, 0x47, 0xda, 0x30, 0x4d, 0xb4, 0xce, 0xb0, 0x8c, 0xbb, 0xd1, 0xba, 0x39, 0x49, 0x47, 0x76, 0xfb, 0x98, 0x8b, 0x47, 0x17, 0x4d, 0xca, 0x88, 0xc7, 0xe2, 0x94, 0x52, 0x83, 0xa0, 0x1c, 0x89, 0x72, //gx + 0x03, 0x49, 0xdc, 0x80, 0x7f, 0x4f, 0xbf, 0x37, 0x4f, 0x4a, 0xea, 0xde, 0x3b, 0xca, 0x95, 0x31, 0x4d, 0xd5, 0x8c, 0xec, 0x9f, 0x30, 0x7a, 0x54, 0xff, 0xc6, 0x1e, 0xfc, 0x00, 0x6d, 0x8a, 0x2c, 0x9d, 0x49, 0x79, 0xc0, 0xac, 0x44, 0xae, 0xa7, 0x4f, 0xbe, 0xbb, 0xb9, 0xf7, 0x72, 0xae, 0xdc, 0xb6, 0x20, 0xb0, 0x1a, 0x7b, 0xa7, 0xaf, 0x1b, 0x32, 0x04, 0x30, 0xc8, 0x59, 0x19, 0x84, 0xf6, 0x01, 0xcd, 0x4c, 0x14, 0x3e, 0xf1, 0xc7, 0xa3, //gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; //b +const sx_ecc_curve_t sx_ecc_curve_k571 = { + .params = CST_BLK_LITARRAY(ecc_k571_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 72, +}; + + +static const SX_ALIGNED uint8_t ecc_e521_params[] = { + 0x01, 0xff, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //q + 0x00, 0x7f, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfd, 0x15, 0xb6, 0xc6, 0x47, 0x46, 0xfc, 0x85, 0xf7, 0x36, 0xb8, 0xaf, 0x5e, 0x7e, 0xc5, 0x3f, 0x04, 0xfb, 0xd8, 0xc4, 0x56, 0x9a, 0x8f, 0x1f, 0x45, 0x40, 0xea, 0x24, 0x35, 0xf5, 0x18, 0x0d, 0x6b, //n + 0x00, 0x75, 0x2c, 0xb4,0x5c, 0x48, 0x64, 0x8b, 0x18, 0x9d, 0xf9, 0x0c, 0xb2, 0x29, 0x6b, 0x28, 0x78, 0xa3, 0xbf, 0xd9, 0xf4, 0x2f, 0xc6, 0xc8, 0x18, 0xec, 0x8b, 0xf3, 0xc9, 0xc0, 0xc6, 0x20, 0x39, 0x13, 0xf6, 0xec, 0xc5, 0xcc, 0xc7, 0x24, 0x34, 0xb1, 0xae, 0x94, 0x9d, 0x56, 0x8f, 0xc9, 0x9c, 0x60, 0x59, 0xd0, 0xfb, 0x13, 0x36, 0x48, 0x38, 0xaa, 0x30, 0x2a, 0x94, 0x0a, 0x2f, 0x19, 0xba, 0x6c, //gx + 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, //gy + 0x01, 0xff, 0xff, 0xff,0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfa, 0x43, 0x31 }; //d +const sx_ecc_curve_t sx_ecc_curve_e521 = { + .params = CST_BLK_LITARRAY(ecc_e521_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_CMD_EDWARDS(1) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 66, +}; + +/********************************************************** +** Curve25519 - (Little-endian) +**********************************************************/ +static const SX_ALIGNED uint8_t ecc_curve25519_params[] = { + 0xED, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, // p + 0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // a + 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; // x +const sx_ecc_curve_t sx_ecc_curve_curve25519 = { + .params = CST_BLK_LITARRAY(ecc_curve25519_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_ACCEL_X25519, + .bytesize = 32, +}; + +/********************************************************** +** Curve448 - (Little-endian) +**********************************************************/ + +static const SX_ALIGNED uint8_t ecc_curve448_params[] = { + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, //p + 0xA6, 0x62, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; //x +const sx_ecc_curve_t sx_ecc_curve_curve448 = { + .params = CST_BLK_LITARRAY(ecc_curve448_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 56, +}; + +/********************************************************** +** Curve SM2 - Fp-256 v1 +**********************************************************/ +static const SX_ALIGNED uint8_t ecc_sm2_p256_params_v1[] = { + 0x85, 0x42, 0xd6, 0x9e, 0x4c, 0x04, 0x4f, 0x18, 0xe8, 0xb9, 0x24, 0x35, 0xbf, 0x6f, 0xf7, 0xde, 0x45, 0x72, 0x83, 0x91, 0x5c, 0x45, 0x51, 0x7d, 0x72, 0x2e, 0xdb, 0x8b, 0x08, 0xf1, 0xdf, 0xc3, //p + 0x85, 0x42, 0xd6, 0x9e, 0x4c, 0x04, 0x4f, 0x18, 0xe8, 0xb9, 0x24, 0x35, 0xbf, 0x6f, 0xf7, 0xdd, 0x29, 0x77, 0x20, 0x63, 0x04, 0x85, 0x62, 0x8d, 0x5a, 0xe7, 0x4e, 0xe7, 0xc3, 0x2e, 0x79, 0xb7, //n + 0x42, 0x1d, 0xeb, 0xd6, 0x1b, 0x62, 0xea, 0xb6, 0x74, 0x64, 0x34, 0xeb, 0xc3, 0xcc, 0x31, 0x5e, 0x32, 0x22, 0x0b, 0x3b, 0xad, 0xd5, 0x0b, 0xdc, 0x4c, 0x4e, 0x6c, 0x14, 0x7f, 0xed, 0xd4, 0x3d, //Gx + 0x06, 0x80, 0x51, 0x2b, 0xcb, 0xb4, 0x2c, 0x07, 0xd4, 0x73, 0x49, 0xd2, 0x15, 0x3b, 0x70, 0xc4, 0xe5, 0xd7, 0xfd, 0xfc, 0xbf, 0xa3, 0x6e, 0xa1, 0xa8, 0x58, 0x41, 0xb9, 0xe4, 0x6e, 0x09, 0xa2, //Gy + 0x78, 0x79, 0x68, 0xb4, 0xfa, 0x32, 0xc3, 0xfd, 0x24, 0x17, 0x84, 0x2e, 0x73, 0xbb, 0xfe, 0xff, 0x2f, 0x3c, 0x84, 0x8b, 0x68, 0x31, 0xd7, 0xe0, 0xec, 0x65, 0x22, 0x8b, 0x39, 0x37, 0xe4, 0x98, //a + 0x63, 0xe4, 0xc6, 0xd3, 0xb2, 0x3b, 0x0c, 0x84, 0x9c, 0xf8, 0x42, 0x41, 0x48, 0x4b, 0xfe, 0x48, 0xf6, 0x1d, 0x59, 0xa5, 0xb1, 0x6b, 0xa0, 0x6e, 0x6e, 0x12, 0xd1, 0xda, 0x27, 0xc5, 0x24, 0x9a //b +}; +const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v1 = { + .params = CST_BLK_LITARRAY(ecc_sm2_p256_params_v1), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 32, +}; + +/********************************************************** +** Curve SM2 - Fp-256 v2 +**********************************************************/ +static const SX_ALIGNED uint8_t ecc_sm2_p256_params_v2[] = { + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, //p + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x72, 0x03, 0xdf, 0x6b, 0x21, 0xc6, 0x05, 0x2b, 0x53, 0xbb, 0xf4, 0x09, 0x39, 0xd5, 0x41, 0x23, //n + 0x32, 0xc4, 0xae, 0x2c, 0x1f, 0x19, 0x81, 0x19, 0x5f, 0x99, 0x04, 0x46, 0x6a, 0x39, 0xc9, 0x94, 0x8f, 0xe3, 0x0b, 0xbf, 0xf2, 0x66, 0x0b, 0xe1, 0x71, 0x5a, 0x45, 0x89, 0x33, 0x4c, 0x74, 0xc7, //Gx + 0xbc, 0x37, 0x36, 0xa2, 0xf4, 0xf6, 0x77, 0x9c, 0x59, 0xbd, 0xce, 0xe3, 0x6b, 0x69, 0x21, 0x53, 0xd0, 0xa9, 0x87, 0x7c, 0xc6, 0x2a, 0x47, 0x40, 0x02, 0xdf, 0x32, 0xe5, 0x21, 0x39, 0xf0, 0xa0, //Gy + 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfc, //a + 0x28, 0xe9, 0xfa, 0x9e, 0x9d, 0x9f, 0x5e, 0x34, 0x4d, 0x5a, 0x9e, 0x4b, 0xcf, 0x65, 0x09, 0xa7, 0xf3, 0x97, 0x89, 0xf5, 0x15, 0xab, 0x8f, 0x92, 0xdd, 0xbc, 0xbd, 0x41, 0x4d, 0x94, 0x0e, 0x93 //b +}; +const sx_ecc_curve_t sx_ecc_curve_sm2_p256_v2 = { + .params = CST_BLK_LITARRAY(ecc_sm2_p256_params_v2), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 32, +}; + +/********************************************************** +** Curve SM2 - F^m-257 +**********************************************************/ +static const SX_ALIGNED uint8_t ecc_sm2_fm257_params[] = { + 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, //q + 0x00, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbc, 0x97, 0x2c, 0xf7, 0xe6, 0xb6, 0xf9, 0x00, 0x94, 0x5b, 0x3c, 0x6a, 0x0c, 0xf6, 0x16, 0x1d, //n + 0x00, 0xcd, 0xb9, 0xca, 0x7f, 0x1e, 0x6b, 0x04, 0x41, 0xf6, 0x58, 0x34, 0x3f, 0x4b, 0x10, 0x29, 0x7c, 0x0e, 0xf9, 0xb6, 0x49, 0x10, 0x82, 0x40, 0x0a, 0x62, 0xe7, 0xa7, 0x48, 0x57, 0x35, 0xfa, 0xdd, //Gx + 0x01, 0x3d, 0xe7, 0x4d, 0xa6, 0x59, 0x51, 0xc4, 0xd7, 0x6d, 0xc8, 0x92, 0x20, 0xd5, 0xf7, 0x77, 0x7a, 0x61, 0x1b, 0x1c, 0x38, 0xba, 0xe2, 0x60, 0xb1, 0x75, 0x95, 0x1d, 0xc8, 0x06, 0x0c, 0x2b, 0x3e, //Gy + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //a + 0x00, 0xe7, 0x8b, 0xcd, 0x09, 0x74, 0x6c, 0x20, 0x23, 0x78, 0xa7, 0xe7, 0x2b, 0x12, 0xbc, 0xe0, 0x02, 0x66, 0xb9, 0x62, 0x7e, 0xcb, 0x0b, 0x5a, 0x25, 0x36, 0x7a, 0xd1, 0xad, 0x4c, 0xc6, 0x24, 0x2b //b +}; +const sx_ecc_curve_t sx_ecc_curve_sm2_fm257 = { + .params = CST_BLK_LITARRAY(ecc_sm2_fm257_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_BINARY) | BA414EP_SELCUR_NO_ACCELERATOR, + .bytesize = 33, +}; + +/********************************************************** +** Brainpool curves +** refrence: https://tools.ietf.org/html/rfc5639#section-3.1 +**********************************************************/ + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP160r1_params[] = { + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, 0x60, 0xDF, 0xC7, 0xAD, 0x95, 0xB3, 0xD8, 0x13, 0x95, 0x15, 0x62, 0x0F, //q + 0xE9, 0x5E, 0x4A, 0x5F, 0x73, 0x70, 0x59, 0xDC, 0x60, 0xDF, 0x59, 0x91, 0xD4, 0x50, 0x29, 0x40, 0x9E, 0x60, 0xFC, 0x09, //n + 0xBE, 0xD5, 0xAF, 0x16, 0xEA, 0x3F, 0x6A, 0x4F, 0x62, 0x93, 0x8C, 0x46, 0x31, 0xEB, 0x5A, 0xF7, 0xBD, 0xBC, 0xDB, 0xC3, //gx + 0x16, 0x67, 0xCB, 0x47, 0x7A, 0x1A, 0x8E, 0xC3, 0x38, 0xF9, 0x47, 0x41, 0x66, 0x9C, 0x97, 0x63, 0x16, 0xDA, 0x63, 0x21, //gy + 0x34, 0x0E, 0x7B, 0xE2, 0xA2, 0x80, 0xEB, 0x74, 0xE2, 0xBE, 0x61, 0xBA, 0xDA, 0x74, 0x5D, 0x97, 0xE8, 0xF7, 0xC3, 0x00, //a + 0x1E, 0x58, 0x9A, 0x85, 0x95, 0x42, 0x34, 0x12, 0x13, 0x4F, 0xAA, 0x2D, 0xBD, 0xEC, 0x95, 0xC8, 0xD8, 0x67, 0x5E, 0x58, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP160r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP160r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 20, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP192r1_params[] = { + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, 0xA7, 0xA3, 0x46, 0x30, 0x93, 0xD1, 0x8D, 0xB7, 0x8F, 0xCE, 0x47, 0x6D, 0xE1, 0xA8, 0x62, 0x97, //q + 0xC3, 0x02, 0xF4, 0x1D, 0x93, 0x2A, 0x36, 0xCD, 0xA7, 0xA3, 0x46, 0x2F, 0x9E, 0x9E, 0x91, 0x6B, 0x5B, 0xE8, 0xF1, 0x02, 0x9A, 0xC4, 0xAC, 0xC1, //n + 0xC0, 0xA0, 0x64, 0x7E, 0xAA, 0xB6, 0xA4, 0x87, 0x53, 0xB0, 0x33, 0xC5, 0x6C, 0xB0, 0xF0, 0x90, 0x0A, 0x2F, 0x5C, 0x48, 0x53, 0x37, 0x5F, 0xD6, //gx + 0x14, 0xB6, 0x90, 0x86, 0x6A, 0xBD, 0x5B, 0xB8, 0x8B, 0x5F, 0x48, 0x28, 0xC1, 0x49, 0x00, 0x02, 0xE6, 0x77, 0x3F, 0xA2, 0xFA, 0x29, 0x9B, 0x8F, //gy + 0x6A, 0x91, 0x17, 0x40, 0x76, 0xB1, 0xE0, 0xE1, 0x9C, 0x39, 0xC0, 0x31, 0xFE, 0x86, 0x85, 0xC1, 0xCA, 0xE0, 0x40, 0xE5, 0xC6, 0x9A, 0x28, 0xEF, //a + 0x46, 0x9A, 0x28, 0xEF, 0x7C, 0x28, 0xCC, 0xA3, 0xDC, 0x72, 0x1D, 0x04, 0x4F, 0x44, 0x96, 0xBC, 0xCA, 0x7E, 0xF4, 0x14, 0x6F, 0xBF, 0x25, 0xC9, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP192r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP192r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 24, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP224r1_params[] = { + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD1, 0xD7, 0x87, 0xB0, 0x9F, 0x07, 0x57, 0x97, 0xDA, 0x89, 0xF5, 0x7E, 0xC8, 0xC0, 0xFF, //q + 0xD7, 0xC1, 0x34, 0xAA, 0x26, 0x43, 0x66, 0x86, 0x2A, 0x18, 0x30, 0x25, 0x75, 0xD0, 0xFB, 0x98, 0xD1, 0x16, 0xBC, 0x4B, 0x6D, 0xDE, 0xBC, 0xA3, 0xA5, 0xA7, 0x93, 0x9F, //n + 0x0D, 0x90, 0x29, 0xAD, 0x2C, 0x7E, 0x5C, 0xF4, 0x34, 0x08, 0x23, 0xB2, 0xA8, 0x7D, 0xC6, 0x8C, 0x9E, 0x4C, 0xE3, 0x17, 0x4C, 0x1E, 0x6E, 0xFD, 0xEE, 0x12, 0xC0, 0x7D, //gx + 0x58, 0xAA, 0x56, 0xF7, 0x72, 0xC0, 0x72, 0x6F, 0x24, 0xC6, 0xB8, 0x9E, 0x4E, 0xCD, 0xAC, 0x24, 0x35, 0x4B, 0x9E, 0x99, 0xCA, 0xA3, 0xF6, 0xD3, 0x76, 0x14, 0x02, 0xCD, //gy + 0x68, 0xA5, 0xE6, 0x2C, 0xA9, 0xCE, 0x6C, 0x1C, 0x29, 0x98, 0x03, 0xA6, 0xC1, 0x53, 0x0B, 0x51, 0x4E, 0x18, 0x2A, 0xD8, 0xB0, 0x04, 0x2A, 0x59, 0xCA, 0xD2, 0x9F, 0x43, //a + 0x25, 0x80, 0xF6, 0x3C, 0xCF, 0xE4, 0x41, 0x38, 0x87, 0x07, 0x13, 0xB1, 0xA9, 0x23, 0x69, 0xE3, 0x3E, 0x21, 0x35, 0xD2, 0x66, 0xDB, 0xB3, 0x72, 0x38, 0x6C, 0x40, 0x0B, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP224r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP224r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 28, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP256r1_params[] = { + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x72, 0x6E, 0x3B, 0xF6, 0x23, 0xD5, 0x26, 0x20, 0x28, 0x20, 0x13, 0x48, 0x1D, 0x1F, 0x6E, 0x53, 0x77, //q + 0xA9, 0xFB, 0x57, 0xDB, 0xA1, 0xEE, 0xA9, 0xBC, 0x3E, 0x66, 0x0A, 0x90, 0x9D, 0x83, 0x8D, 0x71, 0x8C, 0x39, 0x7A, 0xA3, 0xB5, 0x61, 0xA6, 0xF7, 0x90, 0x1E, 0x0E, 0x82, 0x97, 0x48, 0x56, 0xA7, //n + 0x8B, 0xD2, 0xAE, 0xB9, 0xCB, 0x7E, 0x57, 0xCB, 0x2C, 0x4B, 0x48, 0x2F, 0xFC, 0x81, 0xB7, 0xAF, 0xB9, 0xDE, 0x27, 0xE1, 0xE3, 0xBD, 0x23, 0xC2, 0x3A, 0x44, 0x53, 0xBD, 0x9A, 0xCE, 0x32, 0x62, //gx + 0x54, 0x7E, 0xF8, 0x35, 0xC3, 0xDA, 0xC4, 0xFD, 0x97, 0xF8, 0x46, 0x1A, 0x14, 0x61, 0x1D, 0xC9, 0xC2, 0x77, 0x45, 0x13, 0x2D, 0xED, 0x8E, 0x54, 0x5C, 0x1D, 0x54, 0xC7, 0x2F, 0x04, 0x69, 0x97, //gy + 0x7D, 0x5A, 0x09, 0x75, 0xFC, 0x2C, 0x30, 0x57, 0xEE, 0xF6, 0x75, 0x30, 0x41, 0x7A, 0xFF, 0xE7, 0xFB, 0x80, 0x55, 0xC1, 0x26, 0xDC, 0x5C, 0x6C, 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9, //a + 0x26, 0xDC, 0x5C, 0x6C, 0xE9, 0x4A, 0x4B, 0x44, 0xF3, 0x30, 0xB5, 0xD9, 0xBB, 0xD7, 0x7C, 0xBF, 0x95, 0x84, 0x16, 0x29, 0x5C, 0xF7, 0xE1, 0xCE, 0x6B, 0xCC, 0xDC, 0x18, 0xFF, 0x8C, 0x07, 0xB6, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP256r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP256r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 32, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP320r1_params[] = { + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, 0xF9, 0x8F, 0xCF, 0xA6, 0xF6, 0xF4, 0x0D, 0xEF, 0x4F, 0x92, 0xB9, 0xEC, 0x78, 0x93, 0xEC, 0x28, 0xFC, 0xD4, 0x12, 0xB1, 0xF1, 0xB3, 0x2E, 0x27, //q + 0xD3, 0x5E, 0x47, 0x20, 0x36, 0xBC, 0x4F, 0xB7, 0xE1, 0x3C, 0x78, 0x5E, 0xD2, 0x01, 0xE0, 0x65, 0xF9, 0x8F, 0xCF, 0xA5, 0xB6, 0x8F, 0x12, 0xA3, 0x2D, 0x48, 0x2E, 0xC7, 0xEE, 0x86, 0x58, 0xE9, 0x86, 0x91, 0x55, 0x5B, 0x44, 0xC5, 0x93, 0x11, //n + 0x43, 0xBD, 0x7E, 0x9A, 0xFB, 0x53, 0xD8, 0xB8, 0x52, 0x89, 0xBC, 0xC4, 0x8E, 0xE5, 0xBF, 0xE6, 0xF2, 0x01, 0x37, 0xD1, 0x0A, 0x08, 0x7E, 0xB6, 0xE7, 0x87, 0x1E, 0x2A, 0x10, 0xA5, 0x99, 0xC7, 0x10, 0xAF, 0x8D, 0x0D, 0x39, 0xE2, 0x06, 0x11, //gx + 0x14, 0xFD, 0xD0, 0x55, 0x45, 0xEC, 0x1C, 0xC8, 0xAB, 0x40, 0x93, 0x24, 0x7F, 0x77, 0x27, 0x5E, 0x07, 0x43, 0xFF, 0xED, 0x11, 0x71, 0x82, 0xEA, 0xA9, 0xC7, 0x78, 0x77, 0xAA, 0xAC, 0x6A, 0xC7, 0xD3, 0x52, 0x45, 0xD1, 0x69, 0x2E, 0x8E, 0xE1, //gy + 0x3E, 0xE3, 0x0B, 0x56, 0x8F, 0xBA, 0xB0, 0xF8, 0x83, 0xCC, 0xEB, 0xD4, 0x6D, 0x3F, 0x3B, 0xB8, 0xA2, 0xA7, 0x35, 0x13, 0xF5, 0xEB, 0x79, 0xDA, 0x66, 0x19, 0x0E, 0xB0, 0x85, 0xFF, 0xA9, 0xF4, 0x92, 0xF3, 0x75, 0xA9, 0x7D, 0x86, 0x0E, 0xB4, //a + 0x52, 0x08, 0x83, 0x94, 0x9D, 0xFD, 0xBC, 0x42, 0xD3, 0xAD, 0x19, 0x86, 0x40, 0x68, 0x8A, 0x6F, 0xE1, 0x3F, 0x41, 0x34, 0x95, 0x54, 0xB4, 0x9A, 0xCC, 0x31, 0xDC, 0xCD, 0x88, 0x45, 0x39, 0x81, 0x6F, 0x5E, 0xB4, 0xAC, 0x8F, 0xB1, 0xF1, 0xA6, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP320r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP320r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 40, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP384r1_params[] = { + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB4, 0x12, 0xB1, 0xDA, 0x19, 0x7F, 0xB7, 0x11, 0x23, 0xAC, 0xD3, 0xA7, 0x29, 0x90, 0x1D, 0x1A, 0x71, 0x87, 0x47, 0x00, 0x13, 0x31, 0x07, 0xEC, 0x53, //q + 0x8C, 0xB9, 0x1E, 0x82, 0xA3, 0x38, 0x6D, 0x28, 0x0F, 0x5D, 0x6F, 0x7E, 0x50, 0xE6, 0x41, 0xDF, 0x15, 0x2F, 0x71, 0x09, 0xED, 0x54, 0x56, 0xB3, 0x1F, 0x16, 0x6E, 0x6C, 0xAC, 0x04, 0x25, 0xA7, 0xCF, 0x3A, 0xB6, 0xAF, 0x6B, 0x7F, 0xC3, 0x10, 0x3B, 0x88, 0x32, 0x02, 0xE9, 0x04, 0x65, 0x65, //n + 0x1D, 0x1C, 0x64, 0xF0, 0x68, 0xCF, 0x45, 0xFF, 0xA2, 0xA6, 0x3A, 0x81, 0xB7, 0xC1, 0x3F, 0x6B, 0x88, 0x47, 0xA3, 0xE7, 0x7E, 0xF1, 0x4F, 0xE3, 0xDB, 0x7F, 0xCA, 0xFE, 0x0C, 0xBD, 0x10, 0xE8, 0xE8, 0x26, 0xE0, 0x34, 0x36, 0xD6, 0x46, 0xAA, 0xEF, 0x87, 0xB2, 0xE2, 0x47, 0xD4, 0xAF, 0x1E, //gx + 0x8A, 0xBE, 0x1D, 0x75, 0x20, 0xF9, 0xC2, 0xA4, 0x5C, 0xB1, 0xEB, 0x8E, 0x95, 0xCF, 0xD5, 0x52, 0x62, 0xB7, 0x0B, 0x29, 0xFE, 0xEC, 0x58, 0x64, 0xE1, 0x9C, 0x05, 0x4F, 0xF9, 0x91, 0x29, 0x28, 0x0E, 0x46, 0x46, 0x21, 0x77, 0x91, 0x81, 0x11, 0x42, 0x82, 0x03, 0x41, 0x26, 0x3C, 0x53, 0x15, //gy + 0x7B, 0xC3, 0x82, 0xC6, 0x3D, 0x8C, 0x15, 0x0C, 0x3C, 0x72, 0x08, 0x0A, 0xCE, 0x05, 0xAF, 0xA0, 0xC2, 0xBE, 0xA2, 0x8E, 0x4F, 0xB2, 0x27, 0x87, 0x13, 0x91, 0x65, 0xEF, 0xBA, 0x91, 0xF9, 0x0F, 0x8A, 0xA5, 0x81, 0x4A, 0x50, 0x3A, 0xD4, 0xEB, 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26, //a + 0x04, 0xA8, 0xC7, 0xDD, 0x22, 0xCE, 0x28, 0x26, 0x8B, 0x39, 0xB5, 0x54, 0x16, 0xF0, 0x44, 0x7C, 0x2F, 0xB7, 0x7D, 0xE1, 0x07, 0xDC, 0xD2, 0xA6, 0x2E, 0x88, 0x0E, 0xA5, 0x3E, 0xEB, 0x62, 0xD5, 0x7C, 0xB4, 0x39, 0x02, 0x95, 0xDB, 0xC9, 0x94, 0x3A, 0xB7, 0x86, 0x96, 0xFA, 0x50, 0x4C, 0x11, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP384r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP384r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 48, +}; + +static const SX_ALIGNED uint8_t sx_ecc_brainpoolP512r1_params[] = { + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x71, 0x7D, 0x4D, 0x9B, 0x00, 0x9B, 0xC6, 0x68, 0x42, 0xAE, 0xCD, 0xA1, 0x2A, 0xE6, 0xA3, 0x80, 0xE6, 0x28, 0x81, 0xFF, 0x2F, 0x2D, 0x82, 0xC6, 0x85, 0x28, 0xAA, 0x60, 0x56, 0x58, 0x3A, 0x48, 0xF3, //q + 0xAA, 0xDD, 0x9D, 0xB8, 0xDB, 0xE9, 0xC4, 0x8B, 0x3F, 0xD4, 0xE6, 0xAE, 0x33, 0xC9, 0xFC, 0x07, 0xCB, 0x30, 0x8D, 0xB3, 0xB3, 0xC9, 0xD2, 0x0E, 0xD6, 0x63, 0x9C, 0xCA, 0x70, 0x33, 0x08, 0x70, 0x55, 0x3E, 0x5C, 0x41, 0x4C, 0xA9, 0x26, 0x19, 0x41, 0x86, 0x61, 0x19, 0x7F, 0xAC, 0x10, 0x47, 0x1D, 0xB1, 0xD3, 0x81, 0x08, 0x5D, 0xDA, 0xDD, 0xB5, 0x87, 0x96, 0x82, 0x9C, 0xA9, 0x00, 0x69, //n + 0x81, 0xAE, 0xE4, 0xBD, 0xD8, 0x2E, 0xD9, 0x64, 0x5A, 0x21, 0x32, 0x2E, 0x9C, 0x4C, 0x6A, 0x93, 0x85, 0xED, 0x9F, 0x70, 0xB5, 0xD9, 0x16, 0xC1, 0xB4, 0x3B, 0x62, 0xEE, 0xF4, 0xD0, 0x09, 0x8E, 0xFF, 0x3B, 0x1F, 0x78, 0xE2, 0xD0, 0xD4, 0x8D, 0x50, 0xD1, 0x68, 0x7B, 0x93, 0xB9, 0x7D, 0x5F, 0x7C, 0x6D, 0x50, 0x47, 0x40, 0x6A, 0x5E, 0x68, 0x8B, 0x35, 0x22, 0x09, 0xBC, 0xB9, 0xF8, 0x22, //gx + 0x7D, 0xDE, 0x38, 0x5D, 0x56, 0x63, 0x32, 0xEC, 0xC0, 0xEA, 0xBF, 0xA9, 0xCF, 0x78, 0x22, 0xFD, 0xF2, 0x09, 0xF7, 0x00, 0x24, 0xA5, 0x7B, 0x1A, 0xA0, 0x00, 0xC5, 0x5B, 0x88, 0x1F, 0x81, 0x11, 0xB2, 0xDC, 0xDE, 0x49, 0x4A, 0x5F, 0x48, 0x5E, 0x5B, 0xCA, 0x4B, 0xD8, 0x8A, 0x27, 0x63, 0xAE, 0xD1, 0xCA, 0x2B, 0x2F, 0xA8, 0xF0, 0x54, 0x06, 0x78, 0xCD, 0x1E, 0x0F, 0x3A, 0xD8, 0x08, 0x92, //gy + 0x78, 0x30, 0xA3, 0x31, 0x8B, 0x60, 0x3B, 0x89, 0xE2, 0x32, 0x71, 0x45, 0xAC, 0x23, 0x4C, 0xC5, 0x94, 0xCB, 0xDD, 0x8D, 0x3D, 0xF9, 0x16, 0x10, 0xA8, 0x34, 0x41, 0xCA, 0xEA, 0x98, 0x63, 0xBC, 0x2D, 0xED, 0x5D, 0x5A, 0xA8, 0x25, 0x3A, 0xA1, 0x0A, 0x2E, 0xF1, 0xC9, 0x8B, 0x9A, 0xC8, 0xB5, 0x7F, 0x11, 0x17, 0xA7, 0x2B, 0xF2, 0xC7, 0xB9, 0xE7, 0xC1, 0xAC, 0x4D, 0x77, 0xFC, 0x94, 0xCA, //a + 0x3D, 0xF9, 0x16, 0x10, 0xA8, 0x34, 0x41, 0xCA, 0xEA, 0x98, 0x63, 0xBC, 0x2D, 0xED, 0x5D, 0x5A, 0xA8, 0x25, 0x3A, 0xA1, 0x0A, 0x2E, 0xF1, 0xC9, 0x8B, 0x9A, 0xC8, 0xB5, 0x7F, 0x11, 0x17, 0xA7, 0x2B, 0xF2, 0xC7, 0xB9, 0xE7, 0xC1, 0xAC, 0x4D, 0x77, 0xFC, 0x94, 0xCA, 0xDC, 0x08, 0x3E, 0x67, 0x98, 0x40, 0x50, 0xB7, 0x5E, 0xBA, 0xE5, 0xDD, 0x28, 0x09, 0xBD, 0x63, 0x80, 0x16, 0xF7, 0x23, }; //b +const sx_ecc_curve_t sx_ecc_brainpoolP512r1 = { + .params = CST_BLK_LITARRAY(sx_ecc_brainpoolP512r1_params), + .pk_flags = BA414EP_CMD_OPFLD(BA414EP_OPFLD_PRIME), + .bytesize = 64, }; \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c index bc29533..28f8da4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c @@ -1,120 +1,120 @@ -/** - * @file - * @brief Defines ECC keygen functions - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#include "sx_ecc_keygen_alg.h" -#include "cryptolib_def.h" -#include "sx_memcpy.h" -#include "ba414ep_config.h" -#include "sx_rng.h" -#include "sx_primitives.h" -#include "sx_errors.h" - -uint32_t ecc_validate_public_key(block_t domain, block_t pub, uint32_t size, uint32_t curve_flags) -{ - uint32_t status; - - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (pub.len != 2 * size || (domain.len != 6 * size && domain.len != 5 * size)) - return CRYPTOLIB_INVALID_PARAM; - - status = ba414ep_set_command(BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE, size, BA414EP_BIGEND, curve_flags); - if (status) - return status; - ba414ep_load_curve(domain, size, BA414EP_BIGEND, 1); - point2CryptoRAM_rev(pub, size , BA414EP_MEMLOC_6); - - ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_6, BA414EP_MEMLOC_6, 0x0); - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_generate_keypair(block_t domain, block_t pub, block_t priv, uint32_t size, - uint32_t curve_flags, struct sx_rng rng) -{ - // Get random number < n -> private key - block_t n = block_t_convert(domain.addr + size, size); - uint32_t status = ecc_generate_private_key(n, priv, rng); - if (status) - return status; - - //Point mult for Public key - return ecc_generate_public_key(domain, pub, priv, size, curve_flags); -} - -uint32_t ecc_generate_private_key(block_t n, block_t priv, struct sx_rng rng) -{ - if (n.len > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - return sx_rng_get_rand_lt_n_blk(priv, n, rng); -} - - -uint32_t ecc_generate_public_key(block_t curve, block_t pub, block_t priv, uint32_t size, uint32_t curve_flags) -{ - uint32_t status; - - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - // Only domain of 5,6 parameters are supported (Weierstrass p/b and Edwards) - if (pub.len != 2 * size || priv.len != size || - (curve.len != 6 * size && curve.len != 5 * size)) - return CRYPTOLIB_INVALID_PARAM; - - // Set command to enable byte-swap - status = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - if (status) - return status; - - // Load parameters - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - - // Location 14 -> Private key - mem2CryptoRAM_rev(priv, priv.len, BA414EP_MEMLOC_14); - - /* Set Configuration register */ - ba414ep_set_config(BA414EP_MEMLOC_2, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); - - /* Start ECC Point Mult */ - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - - // Fetch the results - CryptoRAM2point_rev(pub, size, BA414EP_MEMLOC_6); - - return CRYPTOLIB_SUCCESS; -} - - -uint32_t ecc_montgomery_generate_keypair(block_t curve, block_t pub, block_t priv, - uint32_t size, uint32_t curve_flags, struct sx_rng rng) -{ - // Get random private key - ecc_montgomery_generate_private_key(priv, rng); - - // Point mult for Public key - return ecc_montgomery_mult(curve, curve_flags, size, priv, NULL_blk, pub); -} - -uint32_t ecc_montgomery_generate_private_key(block_t priv, struct sx_rng rng) -{ - if (priv.len > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_INVALID_PARAM; - - rng.get_rand_blk(rng.param, priv); - return CRYPTOLIB_SUCCESS; - -} - -uint32_t ecc_montgomery_generate_public_key(block_t curve, block_t pub, block_t priv, uint32_t size, uint32_t curve_flags) -{ - // All the required tests are internally handled by ecc_montgomery_mult - return ecc_montgomery_mult(curve, curve_flags, size, priv, NULL_blk, pub); -} +/** + * @file + * @brief Defines ECC keygen functions + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include "sx_ecc_keygen_alg.h" +#include "cryptolib_def.h" +#include "sx_memcpy.h" +#include "ba414ep_config.h" +#include "sx_rng.h" +#include "sx_primitives.h" +#include "sx_errors.h" + +uint32_t ecc_validate_public_key(block_t domain, block_t pub, uint32_t size, uint32_t curve_flags) +{ + uint32_t status; + + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (pub.len != 2 * size || (domain.len != 6 * size && domain.len != 5 * size)) + return CRYPTOLIB_INVALID_PARAM; + + status = ba414ep_set_command(BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE, size, BA414EP_BIGEND, curve_flags); + if (status) + return status; + ba414ep_load_curve(domain, size, BA414EP_BIGEND, 1); + point2CryptoRAM_rev(pub, size , BA414EP_MEMLOC_6); + + ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_6, BA414EP_MEMLOC_6, 0x0); + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_generate_keypair(block_t domain, block_t pub, block_t priv, uint32_t size, + uint32_t curve_flags, struct sx_rng rng) +{ + // Get random number < n -> private key + block_t n = block_t_convert(domain.addr + size, size); + uint32_t status = ecc_generate_private_key(n, priv, rng); + if (status) + return status; + + //Point mult for Public key + return ecc_generate_public_key(domain, pub, priv, size, curve_flags); +} + +uint32_t ecc_generate_private_key(block_t n, block_t priv, struct sx_rng rng) +{ + if (n.len > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + return sx_rng_get_rand_lt_n_blk(priv, n, rng); +} + + +uint32_t ecc_generate_public_key(block_t curve, block_t pub, block_t priv, uint32_t size, uint32_t curve_flags) +{ + uint32_t status; + + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + // Only domain of 5,6 parameters are supported (Weierstrass p/b and Edwards) + if (pub.len != 2 * size || priv.len != size || + (curve.len != 6 * size && curve.len != 5 * size)) + return CRYPTOLIB_INVALID_PARAM; + + // Set command to enable byte-swap + status = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + if (status) + return status; + + // Load parameters + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + + // Location 14 -> Private key + mem2CryptoRAM_rev(priv, priv.len, BA414EP_MEMLOC_14); + + /* Set Configuration register */ + ba414ep_set_config(BA414EP_MEMLOC_2, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); + + /* Start ECC Point Mult */ + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + + // Fetch the results + CryptoRAM2point_rev(pub, size, BA414EP_MEMLOC_6); + + return CRYPTOLIB_SUCCESS; +} + + +uint32_t ecc_montgomery_generate_keypair(block_t curve, block_t pub, block_t priv, + uint32_t size, uint32_t curve_flags, struct sx_rng rng) +{ + // Get random private key + ecc_montgomery_generate_private_key(priv, rng); + + // Point mult for Public key + return ecc_montgomery_mult(curve, curve_flags, size, priv, NULL_blk, pub); +} + +uint32_t ecc_montgomery_generate_private_key(block_t priv, struct sx_rng rng) +{ + if (priv.len > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_INVALID_PARAM; + + rng.get_rand_blk(rng.param, priv); + return CRYPTOLIB_SUCCESS; + +} + +uint32_t ecc_montgomery_generate_public_key(block_t curve, block_t pub, block_t priv, uint32_t size, uint32_t curve_flags) +{ + // All the required tests are internally handled by ecc_montgomery_mult + return ecc_montgomery_mult(curve, curve_flags, size, priv, NULL_blk, pub); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c index 72c236c..0c420f8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c @@ -1,274 +1,274 @@ -/** - * @file - * @brief Implements the procedures to make ECDSA operations with - * the BA414EP pub key - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#include "sx_ecdsa_alg.h" -#include "sx_memcpy.h" -#include "ba414ep_config.h" -#include "sx_hash.h" -#include "sx_rng.h" -#include "sx_errors.h" -#include "sx_math.h" - -uint32_t ecdsa_validate_domain(const sx_ecc_curve_t *curve) -{ - uint32_t status; - - const uint32_t size = sx_ecc_curve_bytesize(curve); - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (curve->params.len != 5 * size && curve->params.len != 6 * size) - return CRYPTOLIB_INVALID_PARAM; - - status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_PARAM_EVAL, size, BA414EP_BIGEND, curve->pk_flags); - if (status) - return status; - ba414ep_load_curve(curve->params, size, BA414EP_BIGEND, 1); - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - - return CRYPTOLIB_SUCCESS; -} - -uint32_t sx_ecdsa_configure_signature(const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key) -{ - uint32_t status; - const uint32_t size = sx_ecc_curve_bytesize(curve); - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || - key.len != size) - return CRYPTOLIB_INVALID_PARAM; - - // Set command to enable byte-swap - status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_SIGN_GEN, size, BA414EP_BIGEND, curve->pk_flags); - if (status) - return status; - - // Load parameters - ba414ep_load_curve(curve->params, size, BA414EP_BIGEND, 1); - - /* Load ECDSA parameters */ - mem2CryptoRAM_rev(key, size, BA414EP_MEMLOC_6); - mem2CryptoRAM_rev(formatted_digest, size, BA414EP_MEMLOC_12); - - return CRYPTOLIB_SUCCESS; -} - -uint32_t sx_ecdsa_attempt_signature( - const sx_ecc_curve_t *curve, - block_t signature, - struct sx_rng rng) -{ - const uint32_t size = sx_ecc_curve_bytesize(curve); - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || - signature.len != 2 * size) - return CRYPTOLIB_INVALID_PARAM; - - uint8_t rnd_buff[ECC_MAX_KEY_SIZE] = {0}; - block_t rnd = block_t_convert(rnd_buff, size); - block_t curve_order = block_t_convert(curve->params.addr + size, size); - uint32_t status = sx_rng_get_rand_lt_n_blk(rnd, curve_order, rng); - if (status) - return status; - mem2CryptoRAM_rev(rnd, rnd.len, BA414EP_MEMLOC_7); - - /* ECDSA signature generation */ - status = ba414ep_set_command( - BA414EP_OPTYPE_ECDSA_SIGN_GEN, - size, - BA414EP_BIGEND, - curve->pk_flags); - if (status) - return status; - status = ba414ep_start_wait_status(); - - if (status & BA414EP_STS_BADSIGNATURE_MASK) - return CRYPTOLIB_INVALID_SIGN_ERR; - else if (status) - return CRYPTOLIB_CRYPTO_ERR; - - // Fetch the results - CryptoRAM2point_rev(signature, size, BA414EP_MEMLOC_10); - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecdsa_generate_signature_digest(const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key, - block_t signature, - struct sx_rng rng) -{ - uint32_t ctr = 0; - uint32_t status = sx_ecdsa_configure_signature(curve, formatted_digest, key); - if (status != CRYPTOLIB_SUCCESS) - return status; - - do { - status = sx_ecdsa_attempt_signature(curve, signature, rng); - } while((status == CRYPTOLIB_INVALID_SIGN_ERR) && (ctr < 10)); - if (status) - return status; - - return CRYPTOLIB_SUCCESS; -} - - - - -uint32_t ecdsa_verify_signature_digest(const sx_ecc_curve_t *curve, - block_t formatted_digest, - block_t key, - block_t signature) -{ - uint32_t status; - const uint32_t size = sx_ecc_curve_bytesize(curve); - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || - key.len != 2 * size || - signature.len != 2 * size) - return CRYPTOLIB_INVALID_PARAM; - - status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_SIGN_VERIF, size, BA414EP_BIGEND, curve->pk_flags); - if (status) - return status; - ba414ep_load_curve(curve->params, size, 1, 1); //TODO FIX ENDIAN - - /* Load ECDSA parameters */ - point2CryptoRAM_rev(key, size, BA414EP_MEMLOC_8); - mem2CryptoRAM_rev(formatted_digest, size, BA414EP_MEMLOC_12); - - // Fetch the signature - point2CryptoRAM_rev(signature, size, BA414EP_MEMLOC_10); - - /* ECDSA signature verification */ - if(ba414ep_start_wait_status()) - return CRYPTOLIB_INVALID_SIGN_ERR; - - return CRYPTOLIB_SUCCESS; -} - - -/** - * @brief perform a bit shift to the right of a large value stored in a byte array - * @param array value to shift (input and output) - * @param len length of the \p array - * @param shift size of the bit shift (between 0 and 7) - */ -//TODO Move this to some "includable" module ? -static void sx_bitshift(uint8_t *array, uint8_t len, uint8_t shift) -{ - if(shift) - { - uint8_t prev, val; - int i; - prev = 0; - for(i = 0; i < len; i++) - { - val = ((array[i] >> shift)&0xFF) | prev; - prev = array[i] << (8-shift); - array[i] = val; - } - } -} - - -/** - * @brief perform digest computation used for signing or verification - * @param curve ECDSA curve to use - * @param message message to sign or verify - * @param hash_fct algorithm to use for hash - * @param digest_blk computed digest - * @return CRYPTOLIB_INVALID_PARAM when there is not enough space in the - * digest_blk to compute the digest - * CRYPTOLIB_SUCCESS otherwise - */ -static uint32_t ecdsa_generate_digest(const sx_ecc_curve_t *curve, - block_t message, - sx_hash_fct_t hash_fct, - block_t *digest_blk) -{ - uint32_t status; - uint32_t dgst_local_len; - uint8_t extra_bits; - - uint32_t curve_bytesize = sx_ecc_curve_bytesize(curve); - uint32_t curve_order_bitsize = sx_math_array_nbits( - curve->params.addr + curve_bytesize, curve_bytesize); - uint32_t curve_order_bytesize = (curve_order_bitsize + 7) / 8; - - if (curve_bytesize > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (curve->params.len != 5 * curve_bytesize && - curve->params.len != 6 * curve_bytesize) - return CRYPTOLIB_INVALID_PARAM; - if (digest_blk->len < sx_hash_get_digest_size(hash_fct)) - return CRYPTOLIB_UNSUPPORTED_ERR; - - /* Call hash fct to get digest. */ - status = sx_hash_blk(hash_fct, message, *digest_blk); - if (status) - return status; - - /* Define digest size. This only take the most significant bytes when curve - * is smaller than hash. If it's greater, leading zeroes will be inserted - * within ecdsa_signature_* functions. - */ - dgst_local_len = SX_MIN(curve_order_bytesize, sx_hash_get_digest_size(hash_fct)); - - /* Shorten the digest to match the expected length */ - digest_blk->len = dgst_local_len; - - /* Bitshift if needed, for curve smaller than digest and with order N not on - * bytes boundaries. - */ - extra_bits = (curve_order_bitsize & 0x7); - if (extra_bits && (sx_hash_get_digest_size(hash_fct) * 8 > curve_order_bitsize)) - sx_bitshift(digest_blk->addr, dgst_local_len, 8-extra_bits); - - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecdsa_generate_signature(const sx_ecc_curve_t *curve, - block_t message, - block_t key, - block_t signature, - sx_hash_fct_t hash_fct, - struct sx_rng rng) -{ - uint8_t digest[MAX_DIGESTSIZE]; - block_t digest_blk = BLK_LITARRAY(digest); - uint32_t status; - - status = ecdsa_generate_digest(curve, message, hash_fct, &digest_blk); - if (status != CRYPTOLIB_SUCCESS) - return status; - return ecdsa_generate_signature_digest(curve, digest_blk, key, signature, - rng); -} - -uint32_t ecdsa_verify_signature(const sx_ecc_curve_t *curve, - block_t message, - block_t key, - block_t signature, - sx_hash_fct_t hash_fct ) -{ - uint8_t digest[MAX_DIGESTSIZE]; - block_t digest_blk = BLK_LITARRAY(digest); - uint32_t status; - - status = ecdsa_generate_digest(curve, message, hash_fct, &digest_blk); - if (status != CRYPTOLIB_SUCCESS) - return status; - return ecdsa_verify_signature_digest(curve, digest_blk, key, signature); -} +/** + * @file + * @brief Implements the procedures to make ECDSA operations with + * the BA414EP pub key + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include "sx_ecdsa_alg.h" +#include "sx_memcpy.h" +#include "ba414ep_config.h" +#include "sx_hash.h" +#include "sx_rng.h" +#include "sx_errors.h" +#include "sx_math.h" + +uint32_t ecdsa_validate_domain(const sx_ecc_curve_t *curve) +{ + uint32_t status; + + const uint32_t size = sx_ecc_curve_bytesize(curve); + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (curve->params.len != 5 * size && curve->params.len != 6 * size) + return CRYPTOLIB_INVALID_PARAM; + + status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_PARAM_EVAL, size, BA414EP_BIGEND, curve->pk_flags); + if (status) + return status; + ba414ep_load_curve(curve->params, size, BA414EP_BIGEND, 1); + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + + return CRYPTOLIB_SUCCESS; +} + +uint32_t sx_ecdsa_configure_signature(const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key) +{ + uint32_t status; + const uint32_t size = sx_ecc_curve_bytesize(curve); + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || + key.len != size) + return CRYPTOLIB_INVALID_PARAM; + + // Set command to enable byte-swap + status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_SIGN_GEN, size, BA414EP_BIGEND, curve->pk_flags); + if (status) + return status; + + // Load parameters + ba414ep_load_curve(curve->params, size, BA414EP_BIGEND, 1); + + /* Load ECDSA parameters */ + mem2CryptoRAM_rev(key, size, BA414EP_MEMLOC_6); + mem2CryptoRAM_rev(formatted_digest, size, BA414EP_MEMLOC_12); + + return CRYPTOLIB_SUCCESS; +} + +uint32_t sx_ecdsa_attempt_signature( + const sx_ecc_curve_t *curve, + block_t signature, + struct sx_rng rng) +{ + const uint32_t size = sx_ecc_curve_bytesize(curve); + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || + signature.len != 2 * size) + return CRYPTOLIB_INVALID_PARAM; + + uint8_t rnd_buff[ECC_MAX_KEY_SIZE] = {0}; + block_t rnd = block_t_convert(rnd_buff, size); + block_t curve_order = block_t_convert(curve->params.addr + size, size); + uint32_t status = sx_rng_get_rand_lt_n_blk(rnd, curve_order, rng); + if (status) + return status; + mem2CryptoRAM_rev(rnd, rnd.len, BA414EP_MEMLOC_7); + + /* ECDSA signature generation */ + status = ba414ep_set_command( + BA414EP_OPTYPE_ECDSA_SIGN_GEN, + size, + BA414EP_BIGEND, + curve->pk_flags); + if (status) + return status; + status = ba414ep_start_wait_status(); + + if (status & BA414EP_STS_BADSIGNATURE_MASK) + return CRYPTOLIB_INVALID_SIGN_ERR; + else if (status) + return CRYPTOLIB_CRYPTO_ERR; + + // Fetch the results + CryptoRAM2point_rev(signature, size, BA414EP_MEMLOC_10); + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecdsa_generate_signature_digest(const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key, + block_t signature, + struct sx_rng rng) +{ + uint32_t ctr = 0; + uint32_t status = sx_ecdsa_configure_signature(curve, formatted_digest, key); + if (status != CRYPTOLIB_SUCCESS) + return status; + + do { + status = sx_ecdsa_attempt_signature(curve, signature, rng); + } while((status == CRYPTOLIB_INVALID_SIGN_ERR) && (ctr < 10)); + if (status) + return status; + + return CRYPTOLIB_SUCCESS; +} + + + + +uint32_t ecdsa_verify_signature_digest(const sx_ecc_curve_t *curve, + block_t formatted_digest, + block_t key, + block_t signature) +{ + uint32_t status; + const uint32_t size = sx_ecc_curve_bytesize(curve); + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if ((curve->params.len != 5 * size && curve->params.len != 6 * size) || + key.len != 2 * size || + signature.len != 2 * size) + return CRYPTOLIB_INVALID_PARAM; + + status = ba414ep_set_command(BA414EP_OPTYPE_ECDSA_SIGN_VERIF, size, BA414EP_BIGEND, curve->pk_flags); + if (status) + return status; + ba414ep_load_curve(curve->params, size, 1, 1); //TODO FIX ENDIAN + + /* Load ECDSA parameters */ + point2CryptoRAM_rev(key, size, BA414EP_MEMLOC_8); + mem2CryptoRAM_rev(formatted_digest, size, BA414EP_MEMLOC_12); + + // Fetch the signature + point2CryptoRAM_rev(signature, size, BA414EP_MEMLOC_10); + + /* ECDSA signature verification */ + if(ba414ep_start_wait_status()) + return CRYPTOLIB_INVALID_SIGN_ERR; + + return CRYPTOLIB_SUCCESS; +} + + +/** + * @brief perform a bit shift to the right of a large value stored in a byte array + * @param array value to shift (input and output) + * @param len length of the \p array + * @param shift size of the bit shift (between 0 and 7) + */ +//TODO Move this to some "includable" module ? +static void sx_bitshift(uint8_t *array, uint8_t len, uint8_t shift) +{ + if(shift) + { + uint8_t prev, val; + int i; + prev = 0; + for(i = 0; i < len; i++) + { + val = ((array[i] >> shift)&0xFF) | prev; + prev = array[i] << (8-shift); + array[i] = val; + } + } +} + + +/** + * @brief perform digest computation used for signing or verification + * @param curve ECDSA curve to use + * @param message message to sign or verify + * @param hash_fct algorithm to use for hash + * @param digest_blk computed digest + * @return CRYPTOLIB_INVALID_PARAM when there is not enough space in the + * digest_blk to compute the digest + * CRYPTOLIB_SUCCESS otherwise + */ +static uint32_t ecdsa_generate_digest(const sx_ecc_curve_t *curve, + block_t message, + sx_hash_fct_t hash_fct, + block_t *digest_blk) +{ + uint32_t status; + uint32_t dgst_local_len; + uint8_t extra_bits; + + uint32_t curve_bytesize = sx_ecc_curve_bytesize(curve); + uint32_t curve_order_bitsize = sx_math_array_nbits( + curve->params.addr + curve_bytesize, curve_bytesize); + uint32_t curve_order_bytesize = (curve_order_bitsize + 7) / 8; + + if (curve_bytesize > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (curve->params.len != 5 * curve_bytesize && + curve->params.len != 6 * curve_bytesize) + return CRYPTOLIB_INVALID_PARAM; + if (digest_blk->len < sx_hash_get_digest_size(hash_fct)) + return CRYPTOLIB_UNSUPPORTED_ERR; + + /* Call hash fct to get digest. */ + status = sx_hash_blk(hash_fct, message, *digest_blk); + if (status) + return status; + + /* Define digest size. This only take the most significant bytes when curve + * is smaller than hash. If it's greater, leading zeroes will be inserted + * within ecdsa_signature_* functions. + */ + dgst_local_len = SX_MIN(curve_order_bytesize, sx_hash_get_digest_size(hash_fct)); + + /* Shorten the digest to match the expected length */ + digest_blk->len = dgst_local_len; + + /* Bitshift if needed, for curve smaller than digest and with order N not on + * bytes boundaries. + */ + extra_bits = (curve_order_bitsize & 0x7); + if (extra_bits && (sx_hash_get_digest_size(hash_fct) * 8 > curve_order_bitsize)) + sx_bitshift(digest_blk->addr, dgst_local_len, 8-extra_bits); + + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecdsa_generate_signature(const sx_ecc_curve_t *curve, + block_t message, + block_t key, + block_t signature, + sx_hash_fct_t hash_fct, + struct sx_rng rng) +{ + uint8_t digest[MAX_DIGESTSIZE]; + block_t digest_blk = BLK_LITARRAY(digest); + uint32_t status; + + status = ecdsa_generate_digest(curve, message, hash_fct, &digest_blk); + if (status != CRYPTOLIB_SUCCESS) + return status; + return ecdsa_generate_signature_digest(curve, digest_blk, key, signature, + rng); +} + +uint32_t ecdsa_verify_signature(const sx_ecc_curve_t *curve, + block_t message, + block_t key, + block_t signature, + sx_hash_fct_t hash_fct ) +{ + uint8_t digest[MAX_DIGESTSIZE]; + block_t digest_blk = BLK_LITARRAY(digest); + uint32_t status; + + status = ecdsa_generate_digest(curve, message, hash_fct, &digest_blk); + if (status != CRYPTOLIB_SUCCESS) + return status; + return ecdsa_verify_signature_digest(curve, digest_blk, key, signature); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c index fde5894..76b5e40 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c @@ -1,421 +1,421 @@ -/** - * @file - * @brief Defines the procedures to make operations with - * the BA413 hash function - * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved - */ - - -#include "sx_hash.h" -#include -#include -#include "cryptolib_def.h" -#include "cryptodma_internal.h" -#include "sx_memcpy.h" -#include "ba413_config.h" -#include "sx_errors.h" - -const uint8_t sx_sm3_iv[SM3_DIGESTSIZE] = - {0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9, 0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00, - 0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa, 0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e}; - -const uint8_t sx_sha1_initial_value[SHA1_STATESIZE] = - {0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 0x89, 0x98, 0xba, - 0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0}; - -const uint8_t sx_sha224_initial_value[SHA224_STATESIZE] = - {0xc1, 0x05, 0x9e, 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39, - 0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 0xfa, 0x4f, 0xa4}; - -const uint8_t sx_sha256_initial_value[SHA256_STATESIZE] = - {0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 0x85, 0x3c, 0x6e, 0xf3, 0x72, 0xa5, 0x4f, 0xf5, 0x3a, - 0x51, 0x0e, 0x52, 0x7f, 0x9b, 0x05, 0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19}; - -const uint8_t sx_sha384_initial_value[SHA384_STATESIZE] = - {0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29, 0x2a, 0x36, 0x7c, 0xd5, 0x07, - 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17, 0x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, - 0x67, 0x33, 0x26, 0x67, 0xff, 0xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11, - 0xdb, 0x0c, 0x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 0xa4}; - -const uint8_t sx_sha512_initial_value[SHA512_STATESIZE] = - {0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 0x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b, - 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 0xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, - 0x51, 0x0e, 0x52, 0x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f, - 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79}; - -/* Internal functions */ - -#define OP_FULL_HASH 1 -#define OP_FULL_HMAC 2 -#define OP_PART_HASH 3 - -/** - * @brief internal function for hash operation - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param extra_in input K for OP_FULL_HMAC, or state for OP_PART_HASH, unused for OP_FULL_HASH - * @param operation_type define type of operation to perform - * @param data_in array of input data to process - * @param entries length of array \p data_in - * @param data_out output digest or state - * @return ::CRYPTOLIB_SUCCESS when execution was successful - */ -static uint32_t sx_hash_internal(sx_hash_fct_t hash_fct, - block_t extra_in, - uint8_t operation_type, - block_t data_in[], - const unsigned int entries, - block_t data_out) -{ - uint32_t total_len; - uint32_t ign_bytes; - uint32_t extra_in_tag; - struct ba413_regs_s info; - struct dma_sg_descr_s desc_in[SX_HASH_ARRAY_MAX_ENTRIES + 2]; - struct dma_sg_descr_s desc_out[2]; - struct dma_sg_descr_s *current_desc; - uint32_t genlen, outlen; - block_t extra = extra_in; - -#ifndef CACHED_HW_CONFIG - if (!CRYPTOSOC_HW_CFG_HASH_IP_INCLUDED) - return CRYPTOLIB_UNSUPPORTED_ERR; -#endif - - CRYPTOLIB_ASSERT(entries <= SX_HASH_ARRAY_MAX_ENTRIES, "Too many entries in data array"); - - switch (hash_fct) { - case e_MD5: - if (!BA413_HW_CFG_MD5_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_MD5; - break; - case e_SHA1: - if (!BA413_HW_CFG_SHA1_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SHA1; - break; - case e_SHA224: - if (!BA413_HW_CFG_SHA224_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SHA224; - break; - case e_SHA256: - if (!BA413_HW_CFG_SHA256_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SHA256; - break; - case e_SHA384: - if (!BA413_HW_CFG_SHA384_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SHA384; - break; - case e_SHA512: - if (!BA413_HW_CFG_SHA512_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SHA512; - break; - case e_SM3: - if (!BA413_HW_CFG_SM3_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config = BA413_CONF_MODE_SM3; - break; - default: - return CRYPTOLIB_INVALID_PARAM; - } - - // Could be 4B for padding but due to both enabled stack protection and - // -Werror, it has to be 8B minimum. - uint8_t discarded_buf[8] = {0}; - switch (operation_type) { - // complete hash operation: no need to load extra info, enable padding in - // hardware, output will be digest - case OP_FULL_HASH: - if (!BA413_HW_CFG_PADDING_SUPPORTED) - return CRYPTOLIB_UNSUPPORTED_ERR; - info.config |= BA413_CONF_HWPAD | BA413_CONF_FINAL; - extra_in.len = 0; - extra_in_tag = DMA_SG_ENGINESELECT_BA413; - genlen = sx_hash_get_digest_size(hash_fct); - break; - - // complete hmac operation: need to load extra info K, enable padding in - // hardware, output will be digest - case OP_FULL_HMAC: - { - if (!(BA413_HW_CFG_PADDING_SUPPORTED && BA413_HW_CFG_HMAC_SUPPORTED)) - return CRYPTOLIB_UNSUPPORTED_ERR; - - uint32_t extra_ign_bytes; - if (extra_in.len) { - extra_ign_bytes = -extra_in.len & 0x3; - } else { - extra_ign_bytes = 4; - // In case of null key (which may come from a FIFO), we provide a local - // buffer to the DMA with appropriate extra_ign_bytes - extra = block_t_convert(discarded_buf, extra_ign_bytes); - } - info.config |= BA413_CONF_HMAC | BA413_CONF_HWPAD | BA413_CONF_FINAL; - extra_in_tag = DMA_SG_TAG_DATATYPE_HASHKEY | DMA_SG_ENGINESELECT_BA413 | - DMA_SG_TAG_ISDATA | DMA_SG_TAG_ISLAST | - DMA_SG_TAG_SETINVALIDBYTES(extra_ign_bytes); - genlen = sx_hash_get_digest_size(hash_fct); - break; - } - - // partial hash operation: need to load initial state, don't enable padding in - // hardware, output will be state - case OP_PART_HASH: - default: - extra_in_tag = DMA_SG_TAG_DATATYPE_HASHINIT | DMA_SG_ENGINESELECT_BA413 | - DMA_SG_TAG_ISDATA | DMA_SG_TAG_ISLAST; - genlen = sx_hash_get_state_size(hash_fct); - } - - // configuration (to register) - current_desc = &desc_in[0]; - current_desc = write_desc( - current_desc, - &info, - sizeof(info), - DMA_AXI_DESCR_REALIGN, - DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISCONFIG); - - // K or init value - current_desc = write_desc_always_blk( - current_desc, - &extra, - DMA_AXI_DESCR_REALIGN, - extra_in_tag); - - // datas - uint32_t i = 0; - total_len = 0; - for (i = 0; i < entries; i++) { - total_len += data_in[i].len; - current_desc = write_desc_blk( - current_desc, - &data_in[i], - 0, - DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_HASHMSG); - } - - // The block size is always a power of 2. We use masking with - // (block_size - 1) instead of doing the time consuming % block_size - // operation. - if (operation_type == OP_PART_HASH) { - uint32_t state_size = sx_hash_get_state_size(hash_fct); - uint32_t block_size = sx_hash_get_block_size(hash_fct); - if ((extra.len != state_size) || (total_len & (block_size - 1))) - return CRYPTOLIB_INVALID_PARAM; - } - - if (total_len == 0) { - // The hardware always expects some data. In case of empty message, - // 4 dummy bytes must be sent (data size must be aligned on 32 bits). - // With the following statement, set_desc_invalid_bytes will extended - // the data length in the last descriptor and mark those additional - // bytes as invalid. - ign_bytes = 4; - // Those 4 additional dummy bytes will be read by the DMA at the address - // given in the descriptor. We want to avoid using the address given - // by the user as it might have side effect (for example if the address - // points to a FIFO or if the address is invalid). Therefore we - // provide a local buffer (in an extra descriptor). This also allows - // supporting empty data_in list (entries=0). - current_desc = write_desc_always( - current_desc, - discarded_buf, - 0, - 0, - DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_HASHMSG); - } else if (total_len & 0x3) // not word aligned - ign_bytes = (4 - (total_len & 0x3)); - else - ign_bytes = 0; - - // last descriptor - --current_desc; - set_last_desc(current_desc); - set_desc_invalid_bytes(current_desc, ign_bytes); - - // ouput digest or state - outlen = SX_MIN(genlen, data_out.len); - current_desc = &desc_out[0]; - current_desc = write_desc( // Can we speculate on outlen value ? - desc_out, - data_out.addr, - outlen, - data_out.flags, - 0); - - // discard unused - current_desc = write_desc( - current_desc, - NULL, - (genlen - outlen), - 0, - 0); - set_last_desc(current_desc-1); - - // launch cryptodma operation - cryptodma_run_sg(desc_in, desc_out); - // if error occurs, hardfault should be trigger - - return CRYPTOLIB_SUCCESS; -} - -/** - * @brief internal function for SHA2 message padding - * @param hash_fct hash function to use. See ::sx_hash_fct_t. - * @param data_len length of the input message to be padded - * @param total_len length of all data hashed including the data hashed before using update and including data_len - * @param padding output for padding, length must be equal or bigger than padding length - * @return padsize length of the padding to be added - */ -static uint32_t sx_hash_pad(sx_hash_fct_t hash_fct, uint32_t data_len, size_t total_len, block_t padding) -{ - uint32_t block_size = sx_hash_get_block_size(hash_fct); - uint32_t length_field_size = (hash_fct >= e_SHA384) ? 16 : 8; - uint32_t padsize; - - /* As block_size is a power of 2, the modulo computation has been converted - * into a binary and operation. This avoids a division operation which can - * be very slow on some chips. */ - padsize = block_size - (data_len & (block_size-1)); - if (padsize < (length_field_size + 1)) - padsize += block_size; - if (padding.len < padsize) - return 0; - /* first bit of padding should be 1 */ - padding.addr[0] = 0x80; - /* followed by zeros until the length field. */ - for (size_t i = 1; i < padsize; i++) - padding.addr[i] = 0; - /* write number of bits at end of padding in big endian order */ - size_t start = length_field_size; - if (start > sizeof(total_len)) - start = sizeof(total_len); - for (size_t i = start; i; i--) { - padding.addr[padsize - i - 1] = (total_len >> (i * 8 - 3)) & 0xFF; - } - padding.addr[padsize - 1] = (total_len & 0x1F) << 3; - - return padsize; -} - -/* Public functions: properties */ -uint32_t sx_hash_get_digest_size(sx_hash_fct_t hash_fct) -{ - switch (hash_fct) { - case e_MD5: - return MD5_DIGESTSIZE; - case e_SHA1: - return SHA1_DIGESTSIZE; - case e_SHA224: - return SHA224_DIGESTSIZE; - case e_SHA256: - return SHA256_DIGESTSIZE; - case e_SHA384: - return SHA384_DIGESTSIZE; - case e_SHA512: - return SHA512_DIGESTSIZE; - case e_SM3: - return SM3_DIGESTSIZE; - default: - return 0; - } -} - -uint32_t sx_hash_get_block_size(sx_hash_fct_t hash_fct) -{ - switch (hash_fct) { - case e_MD5: - return MD5_BLOCKSIZE; - case e_SHA1: - return SHA1_BLOCKSIZE; - case e_SHA224: - return SHA224_BLOCKSIZE; - case e_SHA256: - return SHA256_BLOCKSIZE; - case e_SHA384: - return SHA384_BLOCKSIZE; - case e_SHA512: - return SHA512_BLOCKSIZE; - case e_SM3: - return SM3_BLOCKSIZE; - default: - return 0; - } -} - -uint32_t sx_hash_get_state_size(sx_hash_fct_t hash_fct) -{ - - switch (hash_fct) { - case e_MD5: - return MD5_INITSIZE; - case e_SHA1: - return SHA1_STATESIZE; - case e_SHA224: - return SHA224_STATESIZE; - case e_SHA256: - return SHA256_STATESIZE; - case e_SHA384: - return SHA384_STATESIZE; - case e_SHA512: - return SHA512_STATESIZE; - case e_SM3: - return SM3_INITSIZE; - default: - return 0; - } -} - -/* Public functions: process arrays of blocks */ -uint32_t sx_hash_array_blk(sx_hash_fct_t hash_fct, - block_t data_in[], - const unsigned int entries, - block_t data_out) -{ - return sx_hash_internal(hash_fct, block_t_convert(NULL, 0), OP_FULL_HASH, - data_in, entries, data_out); -} - -uint32_t sx_hmac_array_blk(sx_hash_fct_t hash_fct, - block_t key, - block_t data_in[], - const unsigned int entries, - block_t data_out) -{ - return sx_hash_internal(hash_fct, key, OP_FULL_HMAC, data_in, entries, - data_out); -} - -/* Public functions: process blocks */ -uint32_t sx_hash_update_blk(sx_hash_fct_t hash_fct, block_t state, block_t data) -{ - return sx_hash_internal(hash_fct, state, OP_PART_HASH, &data, 1, state); -} - -uint32_t sx_hash_finish_blk(sx_hash_fct_t hash_fct, block_t state, block_t data_in, block_t data_out, uint32_t total_len) -{ - uint8_t padding[MAX_BLOCKSIZE+16+1]; - block_t padding_blk = BLK_LITARRAY(padding); - - uint32_t padding_len = sx_hash_pad(hash_fct, data_in.len, total_len, padding_blk); - padding_blk.len = padding_len; - - block_t input_padding[] = {data_in, padding_blk}; - - return sx_hash_internal(hash_fct, state, OP_PART_HASH, input_padding, 2, data_out); -} -uint32_t sx_hash_blk(sx_hash_fct_t hash_fct, block_t data_in, block_t data_out) -{ - return sx_hash_array_blk(hash_fct, &data_in, 1, data_out); -} - -uint32_t sx_hmac_blk(sx_hash_fct_t hash_fct, block_t key, block_t data_in, block_t data_out) -{ - return sx_hmac_array_blk(hash_fct, key, &data_in, 1, data_out); -} - +/** + * @file + * @brief Defines the procedures to make operations with + * the BA413 hash function + * @copyright Copyright (c) 2016-2020 Silex Insight. All Rights reserved + */ + + +#include "sx_hash.h" +#include +#include +#include "cryptolib_def.h" +#include "cryptodma_internal.h" +#include "sx_memcpy.h" +#include "ba413_config.h" +#include "sx_errors.h" + +const uint8_t sx_sm3_iv[SM3_DIGESTSIZE] = + {0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9, 0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00, + 0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa, 0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e}; + +const uint8_t sx_sha1_initial_value[SHA1_STATESIZE] = + {0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 0x89, 0x98, 0xba, + 0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0}; + +const uint8_t sx_sha224_initial_value[SHA224_STATESIZE] = + {0xc1, 0x05, 0x9e, 0xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39, + 0xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 0xfa, 0x4f, 0xa4}; + +const uint8_t sx_sha256_initial_value[SHA256_STATESIZE] = + {0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 0x85, 0x3c, 0x6e, 0xf3, 0x72, 0xa5, 0x4f, 0xf5, 0x3a, + 0x51, 0x0e, 0x52, 0x7f, 0x9b, 0x05, 0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19}; + +const uint8_t sx_sha384_initial_value[SHA384_STATESIZE] = + {0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29, 0x2a, 0x36, 0x7c, 0xd5, 0x07, + 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17, 0x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, + 0x67, 0x33, 0x26, 0x67, 0xff, 0xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11, + 0xdb, 0x0c, 0x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 0xa4}; + +const uint8_t sx_sha512_initial_value[SHA512_STATESIZE] = + {0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 0x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b, + 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 0xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, + 0x51, 0x0e, 0x52, 0x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f, + 0x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79}; + +/* Internal functions */ + +#define OP_FULL_HASH 1 +#define OP_FULL_HMAC 2 +#define OP_PART_HASH 3 + +/** + * @brief internal function for hash operation + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param extra_in input K for OP_FULL_HMAC, or state for OP_PART_HASH, unused for OP_FULL_HASH + * @param operation_type define type of operation to perform + * @param data_in array of input data to process + * @param entries length of array \p data_in + * @param data_out output digest or state + * @return ::CRYPTOLIB_SUCCESS when execution was successful + */ +static uint32_t sx_hash_internal(sx_hash_fct_t hash_fct, + block_t extra_in, + uint8_t operation_type, + block_t data_in[], + const unsigned int entries, + block_t data_out) +{ + uint32_t total_len; + uint32_t ign_bytes; + uint32_t extra_in_tag; + struct ba413_regs_s info; + struct dma_sg_descr_s desc_in[SX_HASH_ARRAY_MAX_ENTRIES + 2]; + struct dma_sg_descr_s desc_out[2]; + struct dma_sg_descr_s *current_desc; + uint32_t genlen, outlen; + block_t extra = extra_in; + +#ifndef CACHED_HW_CONFIG + if (!CRYPTOSOC_HW_CFG_HASH_IP_INCLUDED) + return CRYPTOLIB_UNSUPPORTED_ERR; +#endif + + CRYPTOLIB_ASSERT(entries <= SX_HASH_ARRAY_MAX_ENTRIES, "Too many entries in data array"); + + switch (hash_fct) { + case e_MD5: + if (!BA413_HW_CFG_MD5_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_MD5; + break; + case e_SHA1: + if (!BA413_HW_CFG_SHA1_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SHA1; + break; + case e_SHA224: + if (!BA413_HW_CFG_SHA224_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SHA224; + break; + case e_SHA256: + if (!BA413_HW_CFG_SHA256_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SHA256; + break; + case e_SHA384: + if (!BA413_HW_CFG_SHA384_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SHA384; + break; + case e_SHA512: + if (!BA413_HW_CFG_SHA512_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SHA512; + break; + case e_SM3: + if (!BA413_HW_CFG_SM3_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config = BA413_CONF_MODE_SM3; + break; + default: + return CRYPTOLIB_INVALID_PARAM; + } + + // Could be 4B for padding but due to both enabled stack protection and + // -Werror, it has to be 8B minimum. + uint8_t discarded_buf[8] = {0}; + switch (operation_type) { + // complete hash operation: no need to load extra info, enable padding in + // hardware, output will be digest + case OP_FULL_HASH: + if (!BA413_HW_CFG_PADDING_SUPPORTED) + return CRYPTOLIB_UNSUPPORTED_ERR; + info.config |= BA413_CONF_HWPAD | BA413_CONF_FINAL; + extra_in.len = 0; + extra_in_tag = DMA_SG_ENGINESELECT_BA413; + genlen = sx_hash_get_digest_size(hash_fct); + break; + + // complete hmac operation: need to load extra info K, enable padding in + // hardware, output will be digest + case OP_FULL_HMAC: + { + if (!(BA413_HW_CFG_PADDING_SUPPORTED && BA413_HW_CFG_HMAC_SUPPORTED)) + return CRYPTOLIB_UNSUPPORTED_ERR; + + uint32_t extra_ign_bytes; + if (extra_in.len) { + extra_ign_bytes = -extra_in.len & 0x3; + } else { + extra_ign_bytes = 4; + // In case of null key (which may come from a FIFO), we provide a local + // buffer to the DMA with appropriate extra_ign_bytes + extra = block_t_convert(discarded_buf, extra_ign_bytes); + } + info.config |= BA413_CONF_HMAC | BA413_CONF_HWPAD | BA413_CONF_FINAL; + extra_in_tag = DMA_SG_TAG_DATATYPE_HASHKEY | DMA_SG_ENGINESELECT_BA413 | + DMA_SG_TAG_ISDATA | DMA_SG_TAG_ISLAST | + DMA_SG_TAG_SETINVALIDBYTES(extra_ign_bytes); + genlen = sx_hash_get_digest_size(hash_fct); + break; + } + + // partial hash operation: need to load initial state, don't enable padding in + // hardware, output will be state + case OP_PART_HASH: + default: + extra_in_tag = DMA_SG_TAG_DATATYPE_HASHINIT | DMA_SG_ENGINESELECT_BA413 | + DMA_SG_TAG_ISDATA | DMA_SG_TAG_ISLAST; + genlen = sx_hash_get_state_size(hash_fct); + } + + // configuration (to register) + current_desc = &desc_in[0]; + current_desc = write_desc( + current_desc, + &info, + sizeof(info), + DMA_AXI_DESCR_REALIGN, + DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISCONFIG); + + // K or init value + current_desc = write_desc_always_blk( + current_desc, + &extra, + DMA_AXI_DESCR_REALIGN, + extra_in_tag); + + // datas + uint32_t i = 0; + total_len = 0; + for (i = 0; i < entries; i++) { + total_len += data_in[i].len; + current_desc = write_desc_blk( + current_desc, + &data_in[i], + 0, + DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_HASHMSG); + } + + // The block size is always a power of 2. We use masking with + // (block_size - 1) instead of doing the time consuming % block_size + // operation. + if (operation_type == OP_PART_HASH) { + uint32_t state_size = sx_hash_get_state_size(hash_fct); + uint32_t block_size = sx_hash_get_block_size(hash_fct); + if ((extra.len != state_size) || (total_len & (block_size - 1))) + return CRYPTOLIB_INVALID_PARAM; + } + + if (total_len == 0) { + // The hardware always expects some data. In case of empty message, + // 4 dummy bytes must be sent (data size must be aligned on 32 bits). + // With the following statement, set_desc_invalid_bytes will extended + // the data length in the last descriptor and mark those additional + // bytes as invalid. + ign_bytes = 4; + // Those 4 additional dummy bytes will be read by the DMA at the address + // given in the descriptor. We want to avoid using the address given + // by the user as it might have side effect (for example if the address + // points to a FIFO or if the address is invalid). Therefore we + // provide a local buffer (in an extra descriptor). This also allows + // supporting empty data_in list (entries=0). + current_desc = write_desc_always( + current_desc, + discarded_buf, + 0, + 0, + DMA_SG_ENGINESELECT_BA413 | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_HASHMSG); + } else if (total_len & 0x3) // not word aligned + ign_bytes = (4 - (total_len & 0x3)); + else + ign_bytes = 0; + + // last descriptor + --current_desc; + set_last_desc(current_desc); + set_desc_invalid_bytes(current_desc, ign_bytes); + + // ouput digest or state + outlen = SX_MIN(genlen, data_out.len); + current_desc = &desc_out[0]; + current_desc = write_desc( // Can we speculate on outlen value ? + desc_out, + data_out.addr, + outlen, + data_out.flags, + 0); + + // discard unused + current_desc = write_desc( + current_desc, + NULL, + (genlen - outlen), + 0, + 0); + set_last_desc(current_desc-1); + + // launch cryptodma operation + cryptodma_run_sg(desc_in, desc_out); + // if error occurs, hardfault should be trigger + + return CRYPTOLIB_SUCCESS; +} + +/** + * @brief internal function for SHA2 message padding + * @param hash_fct hash function to use. See ::sx_hash_fct_t. + * @param data_len length of the input message to be padded + * @param total_len length of all data hashed including the data hashed before using update and including data_len + * @param padding output for padding, length must be equal or bigger than padding length + * @return padsize length of the padding to be added + */ +static uint32_t sx_hash_pad(sx_hash_fct_t hash_fct, uint32_t data_len, size_t total_len, block_t padding) +{ + uint32_t block_size = sx_hash_get_block_size(hash_fct); + uint32_t length_field_size = (hash_fct >= e_SHA384) ? 16 : 8; + uint32_t padsize; + + /* As block_size is a power of 2, the modulo computation has been converted + * into a binary and operation. This avoids a division operation which can + * be very slow on some chips. */ + padsize = block_size - (data_len & (block_size-1)); + if (padsize < (length_field_size + 1)) + padsize += block_size; + if (padding.len < padsize) + return 0; + /* first bit of padding should be 1 */ + padding.addr[0] = 0x80; + /* followed by zeros until the length field. */ + for (size_t i = 1; i < padsize; i++) + padding.addr[i] = 0; + /* write number of bits at end of padding in big endian order */ + size_t start = length_field_size; + if (start > sizeof(total_len)) + start = sizeof(total_len); + for (size_t i = start; i; i--) { + padding.addr[padsize - i - 1] = (total_len >> (i * 8 - 3)) & 0xFF; + } + padding.addr[padsize - 1] = (total_len & 0x1F) << 3; + + return padsize; +} + +/* Public functions: properties */ +uint32_t sx_hash_get_digest_size(sx_hash_fct_t hash_fct) +{ + switch (hash_fct) { + case e_MD5: + return MD5_DIGESTSIZE; + case e_SHA1: + return SHA1_DIGESTSIZE; + case e_SHA224: + return SHA224_DIGESTSIZE; + case e_SHA256: + return SHA256_DIGESTSIZE; + case e_SHA384: + return SHA384_DIGESTSIZE; + case e_SHA512: + return SHA512_DIGESTSIZE; + case e_SM3: + return SM3_DIGESTSIZE; + default: + return 0; + } +} + +uint32_t sx_hash_get_block_size(sx_hash_fct_t hash_fct) +{ + switch (hash_fct) { + case e_MD5: + return MD5_BLOCKSIZE; + case e_SHA1: + return SHA1_BLOCKSIZE; + case e_SHA224: + return SHA224_BLOCKSIZE; + case e_SHA256: + return SHA256_BLOCKSIZE; + case e_SHA384: + return SHA384_BLOCKSIZE; + case e_SHA512: + return SHA512_BLOCKSIZE; + case e_SM3: + return SM3_BLOCKSIZE; + default: + return 0; + } +} + +uint32_t sx_hash_get_state_size(sx_hash_fct_t hash_fct) +{ + + switch (hash_fct) { + case e_MD5: + return MD5_INITSIZE; + case e_SHA1: + return SHA1_STATESIZE; + case e_SHA224: + return SHA224_STATESIZE; + case e_SHA256: + return SHA256_STATESIZE; + case e_SHA384: + return SHA384_STATESIZE; + case e_SHA512: + return SHA512_STATESIZE; + case e_SM3: + return SM3_INITSIZE; + default: + return 0; + } +} + +/* Public functions: process arrays of blocks */ +uint32_t sx_hash_array_blk(sx_hash_fct_t hash_fct, + block_t data_in[], + const unsigned int entries, + block_t data_out) +{ + return sx_hash_internal(hash_fct, block_t_convert(NULL, 0), OP_FULL_HASH, + data_in, entries, data_out); +} + +uint32_t sx_hmac_array_blk(sx_hash_fct_t hash_fct, + block_t key, + block_t data_in[], + const unsigned int entries, + block_t data_out) +{ + return sx_hash_internal(hash_fct, key, OP_FULL_HMAC, data_in, entries, + data_out); +} + +/* Public functions: process blocks */ +uint32_t sx_hash_update_blk(sx_hash_fct_t hash_fct, block_t state, block_t data) +{ + return sx_hash_internal(hash_fct, state, OP_PART_HASH, &data, 1, state); +} + +uint32_t sx_hash_finish_blk(sx_hash_fct_t hash_fct, block_t state, block_t data_in, block_t data_out, uint32_t total_len) +{ + uint8_t padding[MAX_BLOCKSIZE+16+1]; + block_t padding_blk = BLK_LITARRAY(padding); + + uint32_t padding_len = sx_hash_pad(hash_fct, data_in.len, total_len, padding_blk); + padding_blk.len = padding_len; + + block_t input_padding[] = {data_in, padding_blk}; + + return sx_hash_internal(hash_fct, state, OP_PART_HASH, input_padding, 2, data_out); +} +uint32_t sx_hash_blk(sx_hash_fct_t hash_fct, block_t data_in, block_t data_out) +{ + return sx_hash_array_blk(hash_fct, &data_in, 1, data_out); +} + +uint32_t sx_hmac_blk(sx_hash_fct_t hash_fct, block_t key, block_t data_in, block_t data_out) +{ + return sx_hmac_array_blk(hash_fct, key, &data_in, 1, data_out); +} + diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c index dae8ec9..0bd9d00 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c @@ -1,134 +1,134 @@ -/** - * @file - * @brief Math functions - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#include "sx_math.h" -#include "cryptolib_def.h" -#include "sx_errors.h" - -void sx_math_u64_to_u8array(uint64_t in, uint8_t *out, enum sx_endianness endian) -{ - uint32_t i = 0; - if (endian == sx_little_endian) { - for(i = 0; i < 8; i++) out[i] = (in >> 8*i)&0xFF; - } else { - for(i = 0; i < 8; i++) out[7-i] = (in >> 8*i)&0xFF; - } -} - -uint32_t sx_math_array_is_not_null(uint8_t *in, uint32_t length) -{ - uint32_t i; - uint32_t is_null = 1; - - for(i = 0; i < length-1; i++) { - is_null &= (in[i] == 0); - } - - return !is_null; -} - - - -uint32_t sx_math_array_nbits(uint8_t *a, const size_t length) -{ - CRYPTOLIB_ASSERT_NM(a); - - uint32_t i,j; - uint32_t nbits = 8*length; - - for(i=0;i0;j--) { - if(a[i]>>j) - break; - else - nbits--; - } - break; - } - } - return nbits; -} - - -int32_t sx_math_array_incr(uint8_t *a, const size_t length, int8_t value) -{ - CRYPTOLIB_ASSERT_NM(a); - CRYPTOLIB_ASSERT_NM(length >= 1); - - int32_t carry = value; - /* The LSB are at the end of the array so start there. */ - for (int i = length - 1; i >= 0; i--) { - int32_t byte = a[i]; - int32_t sum = byte + carry; - a[i] = (uint8_t) (sum & 0xFF); - carry = sum >> 8; - } - return carry; -} - -void sx_math_array_add(uint8_t *a, const size_t alen, const uint8_t *b, const size_t blen) -{ - CRYPTOLIB_ASSERT_NM(a); - CRYPTOLIB_ASSERT_NM(alen >= 1); - CRYPTOLIB_ASSERT_NM(b); - CRYPTOLIB_ASSERT_NM(blen >= 1); - - uint32_t tmp = 0; - size_t i = 0; - - for(; i < blen; i++) { - tmp += a[alen - i - 1] + b[blen - i - 1]; - a[alen - i - 1] = tmp & 0xFF; - tmp >>= 8; - } - - for (; tmp != 0 && i < alen; i++) { - tmp += a[alen - i - 1] ; - a[alen - i - 1] = tmp & 0xFF; - tmp >>= 8; - } -} - -bool sx_math_less_than( - const uint8_t *lhs, - const uint8_t *rhs, - const size_t len) -{ - // lhs < rhs <=> lhs - rhs < 0 - int32_t carry = 0; - for (int i = len - 1; i >= 0; i--) { - carry = (carry + lhs[i] - rhs[i]) >> 8; - } - return carry < 0; -} - -void sx_math_abs_diff( - const uint8_t *a, - const uint8_t *b, - uint8_t *result, - size_t size) -{ - // Compute result = a - b - int32_t tmp = 0; - for (int i = size - 1; i >= 0; i--) { - tmp += a[i] - b[i]; - result[i] = tmp & 0xFF; - tmp >>= 8; - } - // At this step: - // - if tmp=0 => result>=0 => result=result => tmp=0, inv=0 - // - if tmp=-1 => result<0 => result=-result => tmp=1, inv=0xFF - int32_t inv = tmp & 0xFF; - tmp = -tmp; - for (int i = size - 1; i >= 0; i--) { - tmp += result[i] ^ inv; - result[i] = tmp & 0xFF; - tmp >>= 8; - } -} +/** + * @file + * @brief Math functions + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + +#include "sx_math.h" +#include "cryptolib_def.h" +#include "sx_errors.h" + +void sx_math_u64_to_u8array(uint64_t in, uint8_t *out, enum sx_endianness endian) +{ + uint32_t i = 0; + if (endian == sx_little_endian) { + for(i = 0; i < 8; i++) out[i] = (in >> 8*i)&0xFF; + } else { + for(i = 0; i < 8; i++) out[7-i] = (in >> 8*i)&0xFF; + } +} + +uint32_t sx_math_array_is_not_null(uint8_t *in, uint32_t length) +{ + uint32_t i; + uint32_t is_null = 1; + + for(i = 0; i < length-1; i++) { + is_null &= (in[i] == 0); + } + + return !is_null; +} + + + +uint32_t sx_math_array_nbits(uint8_t *a, const size_t length) +{ + CRYPTOLIB_ASSERT_NM(a); + + uint32_t i,j; + uint32_t nbits = 8*length; + + for(i=0;i0;j--) { + if(a[i]>>j) + break; + else + nbits--; + } + break; + } + } + return nbits; +} + + +int32_t sx_math_array_incr(uint8_t *a, const size_t length, int8_t value) +{ + CRYPTOLIB_ASSERT_NM(a); + CRYPTOLIB_ASSERT_NM(length >= 1); + + int32_t carry = value; + /* The LSB are at the end of the array so start there. */ + for (int i = length - 1; i >= 0; i--) { + int32_t byte = a[i]; + int32_t sum = byte + carry; + a[i] = (uint8_t) (sum & 0xFF); + carry = sum >> 8; + } + return carry; +} + +void sx_math_array_add(uint8_t *a, const size_t alen, const uint8_t *b, const size_t blen) +{ + CRYPTOLIB_ASSERT_NM(a); + CRYPTOLIB_ASSERT_NM(alen >= 1); + CRYPTOLIB_ASSERT_NM(b); + CRYPTOLIB_ASSERT_NM(blen >= 1); + + uint32_t tmp = 0; + size_t i = 0; + + for(; i < blen; i++) { + tmp += a[alen - i - 1] + b[blen - i - 1]; + a[alen - i - 1] = tmp & 0xFF; + tmp >>= 8; + } + + for (; tmp != 0 && i < alen; i++) { + tmp += a[alen - i - 1] ; + a[alen - i - 1] = tmp & 0xFF; + tmp >>= 8; + } +} + +bool sx_math_less_than( + const uint8_t *lhs, + const uint8_t *rhs, + const size_t len) +{ + // lhs < rhs <=> lhs - rhs < 0 + int32_t carry = 0; + for (int i = len - 1; i >= 0; i--) { + carry = (carry + lhs[i] - rhs[i]) >> 8; + } + return carry < 0; +} + +void sx_math_abs_diff( + const uint8_t *a, + const uint8_t *b, + uint8_t *result, + size_t size) +{ + // Compute result = a - b + int32_t tmp = 0; + for (int i = size - 1; i >= 0; i--) { + tmp += a[i] - b[i]; + result[i] = tmp & 0xFF; + tmp >>= 8; + } + // At this step: + // - if tmp=0 => result>=0 => result=result => tmp=0, inv=0 + // - if tmp=-1 => result<0 => result=-result => tmp=1, inv=0xFF + int32_t inv = tmp & 0xFF; + tmp = -tmp; + for (int i = size - 1; i >= 0; i--) { + tmp += result[i] ^ inv; + result[i] = tmp & 0xFF; + tmp >>= 8; + } +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c index 46196bf..bcb3879 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c @@ -1,38 +1,38 @@ -#include "sx_memcmp.h" -#include "sx_memcpy.h" - - -uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size) -{ - //Don't try to optimise this function for performance, it's time constant for security reasons - uint32_t diff = 0; - uint32_t i = 0; - for(i = 0; i < size; i++) { - diff |= (*(in1 + i)^(*(in2 + i))); - } - - return (diff > 0); -} - -uint32_t memcmp32_blk_time_cst(block_t in1, block_t in2, uint32_t size) -{ - //Don't try to optimise this function for performance, it's time constant for security reasons - uint32_t diff = 0; - uint32_t in1_value, in2_value; - uint32_t i = 0; - for(i = 0; i < size/4; i++) { - if (in1.flags & BLOCK_S_CONST_ADDR) { - in1_value = *(volatile uint32_t *) in1.addr; - } else { - in1_value = *(volatile uint32_t *) (in1.addr + 4*i); - } - if (in2.flags & BLOCK_S_CONST_ADDR) { - in2_value = *(volatile uint32_t *) in2.addr; - } else { - in2_value = *(volatile uint32_t *) (in2.addr + 4*i); - } - diff |= in1_value ^ in2_value; - } - - return (diff > 0); -} +#include "sx_memcmp.h" +#include "sx_memcpy.h" + + +uint32_t memcmp_time_cst(uint8_t *in1, uint8_t *in2, uint32_t size) +{ + //Don't try to optimise this function for performance, it's time constant for security reasons + uint32_t diff = 0; + uint32_t i = 0; + for(i = 0; i < size; i++) { + diff |= (*(in1 + i)^(*(in2 + i))); + } + + return (diff > 0); +} + +uint32_t memcmp32_blk_time_cst(block_t in1, block_t in2, uint32_t size) +{ + //Don't try to optimise this function for performance, it's time constant for security reasons + uint32_t diff = 0; + uint32_t in1_value, in2_value; + uint32_t i = 0; + for(i = 0; i < size/4; i++) { + if (in1.flags & BLOCK_S_CONST_ADDR) { + in1_value = *(volatile uint32_t *) in1.addr; + } else { + in1_value = *(volatile uint32_t *) (in1.addr + 4*i); + } + if (in2.flags & BLOCK_S_CONST_ADDR) { + in2_value = *(volatile uint32_t *) in2.addr; + } else { + in2_value = *(volatile uint32_t *) (in2.addr + 4*i); + } + diff |= in1_value ^ in2_value; + } + + return (diff > 0); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c index 2a80303..30a3a04 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c @@ -1,102 +1,102 @@ -/** - * @file - * @brief defines DMA configuration functions - * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved - */ - -#include -#include -#include "sx_memcpy.h" -#include "cryptodma_internal.h" -#include "cryptolib_def.h" - -#ifndef BLK_MEMCPY_MIN_DMA_SIZE -#define BLK_MEMCPY_MIN_DMA_SIZE 0U -#endif - - -void sx_memcpy(void* dst, void* src, size_t length) -{ -#ifdef __aarch64__ - if(((((uint64_t) dst) & 0x7) == 0) && - ((((uint64_t) src) & 0x7) == 0)) { - size_t i; - for (i = 0; i < (length >> 3); i++) - ((uint64_t*) dst)[i] = ((uint64_t*) src)[i]; - for (i = i * 8; i < length; i++) - ((uint8_t*) dst)[i] = ((uint8_t*) src)[i]; - } else - for (size_t i = 0; i < length; i++) - ((uint8_t*) dst)[i] = ((uint8_t*) src)[i]; -#else - memcpy(dst, src, length); -#endif -} - -void sx_memset(void* src, int8_t pattern, size_t length) -{ -#ifdef __aarch64__ - for(size_t i = 0; i < length; i++) - ((uint8_t *) src)[i] = pattern; -#else - memset(src, pattern, length); -#endif -} - -void memcpy_blk(block_t dest, block_t src, uint32_t length) -{ - if (dest.flags & DMA_AXI_DESCR_DISCARD) { - return; - } - - if (dest.len < length) { - length = dest.len; - } - if (!(src.flags & BLOCK_S_CONST_ADDR) && (src.len < length)) { - length = src.len; - } - if (!length) - return; - /* Declaring a local variable to avoid the error: - * comparison is always true due to limited range of data type [-Werror=type-limits] - * when BLK_MEMCPY_MIN_DMA_SIZE = 0 and -Wextra compile option is used. - */ - uint32_t min_dma_size = BLK_MEMCPY_MIN_DMA_SIZE; - if (length >= min_dma_size) { - cryptodma_config_direct(dest, src, length); - cryptodma_start(); - cryptodma_wait(); - cryptodma_check_status(); - } else { - if (src.flags & BLOCK_S_CONST_ADDR) { - for (uint32_t i = 0; i < length; i+=4) { - uint32_t v = *(volatile uint32_t*)src.addr; - size_t len = (dest.len-i) < 4 ? (dest.len-i): 4; - sx_memcpy(dest.addr + i, &v, len); - } - } else { - sx_memcpy(dest.addr, src.addr, length); - } - } -} - - - -void memcpy_blkOut(block_t dest, const volatile void * src, uint32_t length) -{ - block_t s = {(uint8_t*)src, length, BLOCK_S_INCR_ADDR}; - memcpy_blk(dest, s, length); -} - -void memcpy_blkIn(volatile void * dest, block_t src, uint32_t length) -{ - block_t d = {(uint8_t*)dest, length, BLOCK_S_INCR_ADDR}; - memcpy_blk(d, src, length); -} - -void memcpy_array(volatile void * dest, const volatile void * src, uint32_t length) -{ - block_t s = {(uint8_t*)src, length, BLOCK_S_INCR_ADDR}; - block_t d = {(uint8_t*)dest, length, BLOCK_S_INCR_ADDR}; - memcpy_blk(d, s, length); -} +/** + * @file + * @brief defines DMA configuration functions + * @copyright Copyright (c) 2016-2019 Silex Insight. All Rights reserved + */ + +#include +#include +#include "sx_memcpy.h" +#include "cryptodma_internal.h" +#include "cryptolib_def.h" + +#ifndef BLK_MEMCPY_MIN_DMA_SIZE +#define BLK_MEMCPY_MIN_DMA_SIZE 0U +#endif + + +void sx_memcpy(void* dst, void* src, size_t length) +{ +#ifdef __aarch64__ + if(((((uint64_t) dst) & 0x7) == 0) && + ((((uint64_t) src) & 0x7) == 0)) { + size_t i; + for (i = 0; i < (length >> 3); i++) + ((uint64_t*) dst)[i] = ((uint64_t*) src)[i]; + for (i = i * 8; i < length; i++) + ((uint8_t*) dst)[i] = ((uint8_t*) src)[i]; + } else + for (size_t i = 0; i < length; i++) + ((uint8_t*) dst)[i] = ((uint8_t*) src)[i]; +#else + memcpy(dst, src, length); +#endif +} + +void sx_memset(void* src, int8_t pattern, size_t length) +{ +#ifdef __aarch64__ + for(size_t i = 0; i < length; i++) + ((uint8_t *) src)[i] = pattern; +#else + memset(src, pattern, length); +#endif +} + +void memcpy_blk(block_t dest, block_t src, uint32_t length) +{ + if (dest.flags & DMA_AXI_DESCR_DISCARD) { + return; + } + + if (dest.len < length) { + length = dest.len; + } + if (!(src.flags & BLOCK_S_CONST_ADDR) && (src.len < length)) { + length = src.len; + } + if (!length) + return; + /* Declaring a local variable to avoid the error: + * comparison is always true due to limited range of data type [-Werror=type-limits] + * when BLK_MEMCPY_MIN_DMA_SIZE = 0 and -Wextra compile option is used. + */ + uint32_t min_dma_size = BLK_MEMCPY_MIN_DMA_SIZE; + if (length >= min_dma_size) { + cryptodma_config_direct(dest, src, length); + cryptodma_start(); + cryptodma_wait(); + cryptodma_check_status(); + } else { + if (src.flags & BLOCK_S_CONST_ADDR) { + for (uint32_t i = 0; i < length; i+=4) { + uint32_t v = *(volatile uint32_t*)src.addr; + size_t len = (dest.len-i) < 4 ? (dest.len-i): 4; + sx_memcpy(dest.addr + i, &v, len); + } + } else { + sx_memcpy(dest.addr, src.addr, length); + } + } +} + + + +void memcpy_blkOut(block_t dest, const volatile void * src, uint32_t length) +{ + block_t s = {(uint8_t*)src, length, BLOCK_S_INCR_ADDR}; + memcpy_blk(dest, s, length); +} + +void memcpy_blkIn(volatile void * dest, block_t src, uint32_t length) +{ + block_t d = {(uint8_t*)dest, length, BLOCK_S_INCR_ADDR}; + memcpy_blk(d, src, length); +} + +void memcpy_array(volatile void * dest, const volatile void * src, uint32_t length) +{ + block_t s = {(uint8_t*)src, length, BLOCK_S_INCR_ADDR}; + block_t d = {(uint8_t*)dest, length, BLOCK_S_INCR_ADDR}; + memcpy_blk(d, s, length); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c index ec1ba92..323b2fc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c @@ -1,537 +1,537 @@ -/** - * @file - * @brief Implements the procedures to make primitive operations with - * the BA414EP pub key - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#include "sx_primitives.h" -#include -#include "cryptolib_def.h" -#include "sx_memcpy.h" -#include "ba414ep_config.h" -#include "sx_ecc_curves.h" -#include "sx_errors.h" -#include "string.h" - -/* PRIMITIVE OPERATIONS */ -static uint32_t primitive_operation(uint32_t op, - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size, - uint32_t PtrA, - uint32_t PtrB, - uint32_t PtrN, - uint32_t PtrC); - - -/* Modular Addition: C = A + B mod N */ -uint32_t modular_addition(const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_ADD , a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Modular Subtraction: C = A - B mod N */ -uint32_t modular_substraction(const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_SUB, a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Modular Multiplication: C = A * B mod N */ -uint32_t modular_multiplication(const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_MULT_ODD, a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Modular Reduction: C = A mod N */ -uint32_t modular_reduction(const uint8_t *a, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_RED_ODD, NULL, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Modular Division: C = A/B mod N */ -uint32_t modular_division(const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_DIV_ODD, b, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Modular Inversion: C = 1/A mod N */ -uint32_t modular_inversion(const uint8_t *a, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_INV_ODD , NULL, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - -/* Multiplication: C = A * B */ -uint32_t multiplication(const uint8_t *a, - const uint8_t *b, - uint8_t *result, - uint32_t size) -{ - return primitive_operation((uint8_t) BA414EP_OPTYPE_MULT, a, b, NULL, result, size, 0xA, 0x8, 0x0, 0x6); -} - - -/* Modular Exponentiation C = B^A mod N */ -uint32_t modular_exponentiation(const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size) -{ - - return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_EXP, b, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); -} - - -/** @brief Generic function to load the Public Key to compute primitive - * arithmetic operations. It is reserved for internal use and SHOULD NOT be used - * via the API as it can corrupt the CryptoRAM. - * - * @param op is the [6:0] bits of the CommandReg register, describing the - * operation asked to the Public Key - * @param a is a pointer to the first operand of the operation (this must point - * to a location in the System Memory, not in the CryptoRAM). - * @param b is a pointer to the second operand of the operation (this must - * point to a location in the System Memory, not in the CryptoRAM). - * @param modulo is a pointer to the modulo of the operation (this must point - * to a location in the System Memory, not in the CryptoRAM). - * @param result is a pointer where the result has to be copied (this must - * point to a location in the System Memory, not in the - * CryptoRAM). - * @param size represents the operands size in bytes. - * @param PtrA is a memory location of the CryptoRAM where the first operand - * has to be copied - * @param PtrB is a memory location of the CryptoRAM where the second operand - * has to be copied - * @param PtrC is a memory location of the CryptoRAM from where the result has - * to be copied - * @param PtrN is a memory location of the CryptoRAM from where the modulo has - * to be copied - * @return CRYPTOLIB_SUCCESS when no error occurs - */ -static uint32_t primitive_operation(uint32_t op, - const uint8_t *a, - const uint8_t *b, - const uint8_t *modulo, - uint8_t *result, - uint32_t size, - uint32_t PtrA, - uint32_t PtrB, - uint32_t PtrN, - uint32_t PtrC){ - uint32_t status; - - /* Set command register with operation, operand size, swap and field - * This is done before transferring data into cryptoRAM because - * endianness needs to be known before transferring data */ - status = ba414ep_set_command(op, size, BA414EP_BIGEND, BA414EP_SELCUR_NO_ACCELERATOR); - if (status) - return status; - - if(modulo != NULL) { - mem2CryptoRAM_rev(block_t_convert(modulo, size), size, PtrN); - } - - if(a != NULL) { - mem2CryptoRAM_rev(block_t_convert(a, size), size, PtrA); - } - - if(b != NULL) { - mem2CryptoRAM_rev(block_t_convert(b, size), size, PtrB); - } - - ba414ep_set_config(PtrA, PtrB, PtrC, PtrN); - - /* Start BA414EP */ - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - - CryptoRAM2mem_rev(block_t_convert(result, size), size, PtrC); - - return CRYPTOLIB_SUCCESS; -} - - -#if (PK_CM_ENABLED && PK_CM_RAND_SCALAR) -/*@Brief Define used to set number of retries for point multiplication when - * counter measures are enabled */ -#define POINT_MULT_CM_RETRIES 10 - -/** @brief Checks if the block does not have only zeros. - * - * @param block Block_t to be verified - * @return 0 - All bits are 0 - * > 0 - Not all bits are 0 - * */ -static uint8_t is_blk_not_zero(block_t block) -{ - uint8_t status = 0; - for (uint32_t i = 0; i < block.len; i++) - status |= block.addr[i]; - return status; -} -#endif - - -/* Modular Exponentiation C = B^A mod N */ -uint32_t modular_exponentiation_blk(block_t a, - block_t b, - block_t modulo, - block_t result, - uint32_t size) -{ - uint32_t status; - - status = ba414ep_set_command(BA414EP_OPTYPE_MOD_EXP, size, BA414EP_BIGEND, BA414EP_SELCUR_NO_ACCELERATOR); - if (status) - return status; - - ba414ep_set_config(BA414EP_MEMLOC_10, BA414EP_MEMLOC_11, BA414EP_MEMLOC_12, BA414EP_MEMLOC_0); - - mem2CryptoRAM_rev(modulo, size, BA414EP_MEMLOC_0); - mem2CryptoRAM_rev(a, size, BA414EP_MEMLOC_10); - mem2CryptoRAM_rev(b, size, BA414EP_MEMLOC_11); - - /* Start BA414EP */ - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - - CryptoRAM2mem_rev(result, size, BA414EP_MEMLOC_12); - - return CRYPTOLIB_SUCCESS; -} - - - -uint32_t ecc_montgomery_mult(block_t curve, uint32_t curve_flags, uint32_t size, block_t scalar, block_t point, block_t result) -{ - uint32_t status; - uint8_t buffer_sc[ECC_MAX_KEY_SIZE]; - uint8_t buffer_pt[ECC_MAX_KEY_SIZE]; - - if (size > ECC_MAX_KEY_SIZE) - return CRYPTOLIB_UNSUPPORTED_ERR; - if (curve.len != 3 * size || - scalar.len != size || - (point.len && point.len != size) || - result.len != size) - return CRYPTOLIB_INVALID_PARAM; - - if(point.addr == NULL_blk.addr) - point = block_t_convert(curve.addr + 2*size, size); - - /* copy and process keys */ - memcpy_blkIn(buffer_pt, point, point.len); - memcpy_blkIn(buffer_sc, scalar, scalar.len); - if(curve.addr == sx_ecc_curve_curve25519.params.addr) - { - buffer_pt[size - 1] &= 127; //decodeUCoordinate - buffer_sc[0] &= 248; //decodeScalar25519 (clamp) - buffer_sc[size - 1] &= 127; //decodeScalar25519 (clamp) - buffer_sc[size - 1] |= 64; //decodeScalar25519 (clamp) - } - else if(curve.addr == sx_ecc_curve_curve448.params.addr) - { - buffer_sc[0] &= 252; //decodeScalar448 (clamp) - buffer_sc[size - 1] |= 128; //decodeScalar448 (clamp) - } - else - { - return CRYPTOLIB_INVALID_PARAM; - } - - - /* Set Command register - size 32 bytes - G(p) field */ - status = ba414ep_set_command(BA414EP_OPTYPE_MONTGOMERY_POINT_MULT, size, BA414EP_LITTLEEND, curve_flags); - if (status) - return status; - mem2CryptoRAM(block_t_convert(buffer_pt, ECC_MAX_KEY_SIZE), size, BA414EP_MEMLOC_2); - mem2CryptoRAM(block_t_convert(buffer_sc, ECC_MAX_KEY_SIZE), size, BA414EP_MEMLOC_3); - - /* Load parameters */ - mem2CryptoRAM(curve, size, BA414EP_MEMLOC_0); - if(!(curve.flags & BLOCK_S_CONST_ADDR)) curve.addr += size; - mem2CryptoRAM(curve, size, BA414EP_MEMLOC_1); - - /* Set Configuration register */ - ba414ep_set_config(BA414EP_MEMLOC_2, BA414EP_MEMLOC_3, BA414EP_MEMLOC_4, 0x0); - - // Start BA414EP & get status when finished - status = ba414ep_start_wait_status(); - if (status) - return CRYPTOLIB_CRYPTO_ERR; - - CryptoRAM2mem(result, size, BA414EP_MEMLOC_4); - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_point_inverse(block_t curve, block_t point, block_t result, - uint32_t size) -{ - uint32_t error; - - if (point.len != size * 2 || result.len != size * 2) - return CRYPTOLIB_INVALID_PARAM; - // result = (x, -y) - // take the opposite value of y coordinate - error = modular_substraction(curve.addr, point.addr + size, curve.addr, result.addr + size, - size); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - // copy x coordinate - memcpy(result.addr, point.addr, size); - - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_point_decompress(block_t curve, block_t point_x, uint8_t y_bit, - block_t point_y, uint32_t size, uint32_t curve_flags) -{ - uint32_t error; - if (y_bit != 0 && y_bit != 1) - return CRYPTOLIB_INVALID_PARAM; - curve_flags |= BA414EP_CMD_FLAGA(y_bit); - - if (point_x.len != size || point_y.len != size) - return CRYPTOLIB_INVALID_PARAM; - - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_DECOMP, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_set_config(BA414EP_MEMLOC_6, 0x00, BA414EP_MEMLOC_7, 0x00); - - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - - mem2CryptoRAM_rev(point_x, size, BA414EP_MEMLOC_6); - - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - CryptoRAM2mem_rev(point_y, size, BA414EP_MEMLOC_7); - - return CRYPTOLIB_SUCCESS; -} - - -uint32_t ecc_point_compute_y2(block_t curve, block_t point_x, block_t point_y2, - uint32_t size) -{ - uint32_t error; - - if (point_x.len != size || point_y2.len != size) - return CRYPTOLIB_INVALID_PARAM; - - // Y^2 = x^3 + ax + b = (x * x + a) * x + b - // Y^2 = (x * x) - error = modular_multiplication(point_x.addr, point_x.addr, curve.addr, point_y2.addr, size); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - // Y^2 = (x * x) + a - error = modular_addition(point_y2.addr, curve.addr + (4*size), curve.addr, point_y2.addr, size); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - // Y^2 = ((x * x) + a) * x - error = modular_multiplication(point_y2.addr, point_x.addr, curve.addr, point_y2.addr, size); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - // Y^2 = ((x * x) + a) * x + b - error = modular_addition(point_y2.addr, curve.addr + (5*size), curve.addr, point_y2.addr, size); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_point_mul(block_t curve, block_t scalar, block_t point, - block_t result, uint32_t size, uint32_t curve_flags) -{ - uint32_t error; - - if (point.len != size * 2 || result.len != size * 2) - return CRYPTOLIB_INVALID_PARAM; - - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); - - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - - mem2CryptoRAM_rev(scalar, scalar.len, BA414EP_MEMLOC_14); - - point2CryptoRAM_rev(point, size, BA414EP_MEMLOC_12); - -#if (PK_CM_ENABLED && PK_CM_RAND_SCALAR) - /* - * Weierstrass point addition formula does not provide the correct result - * in some exceptional cases (P+P, P+(-P), P+0, 0+P). - * With counter-measure enabled it is possible to hit one of those cases - * during the point multiplication operation. If that case, the PK engine - * will return NotInvertible flag (point at infinity) - although the correct - * final result is not the point at infinity. - * When using a random scalar value, this will happen with extremely low - * probability. However this can happen with test vectors which use very - * small scalar value (k<=32) or very large scalar value (k>=n-32). - */ - - uint8_t i; - for (i = 0; i < POINT_MULT_CM_RETRIES; i++) { - /* - * For the first iteration, the commands was set before entering the for loop - */ - error = ba414ep_start_wait_status(); - if ((error & BA414EP_STS_NOTINVERTIBLE_MASK) && is_blk_not_zero(scalar)) { - /* - * The command needs to be reset before retrying, in order to generate another random. - */ - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - continue; - } - else - break; - } - if (error) { - if (i == POINT_MULT_CM_RETRIES) - CRYPTOLIB_PRINTF("ecc_point_mul: exceeded number of retries\n"); - return CRYPTOLIB_CRYPTO_ERR; - } -#else - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; -#endif - CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_6); - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_point_add(block_t curve, block_t point_a, block_t point_b, - block_t result, uint32_t size, uint32_t curve_flags) -{ - uint32_t error; - - if (point_a.len != size * 2 || point_b.len != size * 2 || result.len != size * 2) - return CRYPTOLIB_INVALID_PARAM; - - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_ADD, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_8, BA414EP_MEMLOC_10, 0x0); - - // Load curve parameters - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - - point2CryptoRAM_rev(point_a, size, BA414EP_MEMLOC_6); - point2CryptoRAM_rev(point_b, size, BA414EP_MEMLOC_8); - - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - // Fetch the results - CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_10); - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_is_point_on_curve(block_t curve, block_t point, uint32_t size, - uint32_t curve_flags) -{ - uint32_t error; - if (point.len != size * 2) - return CRYPTOLIB_INVALID_PARAM; - - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - point2CryptoRAM_rev(point, size , BA414EP_MEMLOC_6); - - ba414ep_set_config(BA414EP_MEMLOC_6, 0x00, 0x00, 0x0); - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_INVALID_POINT; - return CRYPTOLIB_SUCCESS; -} - -uint32_t ecc_pt_muladd(block_t curve, block_t scalar_m, block_t point1, - block_t scalar_n, block_t point2, block_t result, uint32_t size, uint32_t curve_flags) -{ - uint32_t error; - - /* first multiply 'point1' with the 'scalar_m' */ - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); - // Load curve parameters - ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); - // Location 14 -> scalar_m - mem2CryptoRAM_rev(scalar_m, size, BA414EP_MEMLOC_14); - // Location 12 -> point1 x, Location 13 -> point1 y - point2CryptoRAM_rev(point1, size, BA414EP_MEMLOC_12); - // Start BA414EP - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - /* next multiply 'point2' with the 'scalar_m' */ - // Already done: ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); - ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_8, 0x0); - // Location 14 -> scalar_n - mem2CryptoRAM_rev(scalar_n, size, BA414EP_MEMLOC_14); - // Location 12 -> point2 x, Location 13 -> point2 y - point2CryptoRAM_rev(point2, size, BA414EP_MEMLOC_12); - // Start BA414EP - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - /* Add the results of the 2 products*/ - error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_ADD, size, BA414EP_BIGEND, curve_flags); - if (error) - return error; - ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_8, BA414EP_MEMLOC_10, 0x0); - // Start BA414EP - error = ba414ep_start_wait_status(); - if (error) - return CRYPTOLIB_CRYPTO_ERR; - - // Fetch the results - CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_10); - - return CRYPTOLIB_SUCCESS; -} +/** + * @file + * @brief Implements the procedures to make primitive operations with + * the BA414EP pub key + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#include "sx_primitives.h" +#include +#include "cryptolib_def.h" +#include "sx_memcpy.h" +#include "ba414ep_config.h" +#include "sx_ecc_curves.h" +#include "sx_errors.h" +#include "string.h" + +/* PRIMITIVE OPERATIONS */ +static uint32_t primitive_operation(uint32_t op, + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size, + uint32_t PtrA, + uint32_t PtrB, + uint32_t PtrN, + uint32_t PtrC); + + +/* Modular Addition: C = A + B mod N */ +uint32_t modular_addition(const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_ADD , a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Modular Subtraction: C = A - B mod N */ +uint32_t modular_substraction(const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_SUB, a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Modular Multiplication: C = A * B mod N */ +uint32_t modular_multiplication(const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_MULT_ODD, a, b, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Modular Reduction: C = A mod N */ +uint32_t modular_reduction(const uint8_t *a, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_RED_ODD, NULL, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Modular Division: C = A/B mod N */ +uint32_t modular_division(const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_DIV_ODD, b, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Modular Inversion: C = 1/A mod N */ +uint32_t modular_inversion(const uint8_t *a, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_INV_ODD , NULL, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + +/* Multiplication: C = A * B */ +uint32_t multiplication(const uint8_t *a, + const uint8_t *b, + uint8_t *result, + uint32_t size) +{ + return primitive_operation((uint8_t) BA414EP_OPTYPE_MULT, a, b, NULL, result, size, 0xA, 0x8, 0x0, 0x6); +} + + +/* Modular Exponentiation C = B^A mod N */ +uint32_t modular_exponentiation(const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size) +{ + + return primitive_operation((uint8_t) BA414EP_OPTYPE_MOD_EXP, b, a, modulo, result, size, 0xA, 0x8, 0x0, 0x6); +} + + +/** @brief Generic function to load the Public Key to compute primitive + * arithmetic operations. It is reserved for internal use and SHOULD NOT be used + * via the API as it can corrupt the CryptoRAM. + * + * @param op is the [6:0] bits of the CommandReg register, describing the + * operation asked to the Public Key + * @param a is a pointer to the first operand of the operation (this must point + * to a location in the System Memory, not in the CryptoRAM). + * @param b is a pointer to the second operand of the operation (this must + * point to a location in the System Memory, not in the CryptoRAM). + * @param modulo is a pointer to the modulo of the operation (this must point + * to a location in the System Memory, not in the CryptoRAM). + * @param result is a pointer where the result has to be copied (this must + * point to a location in the System Memory, not in the + * CryptoRAM). + * @param size represents the operands size in bytes. + * @param PtrA is a memory location of the CryptoRAM where the first operand + * has to be copied + * @param PtrB is a memory location of the CryptoRAM where the second operand + * has to be copied + * @param PtrC is a memory location of the CryptoRAM from where the result has + * to be copied + * @param PtrN is a memory location of the CryptoRAM from where the modulo has + * to be copied + * @return CRYPTOLIB_SUCCESS when no error occurs + */ +static uint32_t primitive_operation(uint32_t op, + const uint8_t *a, + const uint8_t *b, + const uint8_t *modulo, + uint8_t *result, + uint32_t size, + uint32_t PtrA, + uint32_t PtrB, + uint32_t PtrN, + uint32_t PtrC){ + uint32_t status; + + /* Set command register with operation, operand size, swap and field + * This is done before transferring data into cryptoRAM because + * endianness needs to be known before transferring data */ + status = ba414ep_set_command(op, size, BA414EP_BIGEND, BA414EP_SELCUR_NO_ACCELERATOR); + if (status) + return status; + + if(modulo != NULL) { + mem2CryptoRAM_rev(block_t_convert(modulo, size), size, PtrN); + } + + if(a != NULL) { + mem2CryptoRAM_rev(block_t_convert(a, size), size, PtrA); + } + + if(b != NULL) { + mem2CryptoRAM_rev(block_t_convert(b, size), size, PtrB); + } + + ba414ep_set_config(PtrA, PtrB, PtrC, PtrN); + + /* Start BA414EP */ + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + + CryptoRAM2mem_rev(block_t_convert(result, size), size, PtrC); + + return CRYPTOLIB_SUCCESS; +} + + +#if (PK_CM_ENABLED && PK_CM_RAND_SCALAR) +/*@Brief Define used to set number of retries for point multiplication when + * counter measures are enabled */ +#define POINT_MULT_CM_RETRIES 10 + +/** @brief Checks if the block does not have only zeros. + * + * @param block Block_t to be verified + * @return 0 - All bits are 0 + * > 0 - Not all bits are 0 + * */ +static uint8_t is_blk_not_zero(block_t block) +{ + uint8_t status = 0; + for (uint32_t i = 0; i < block.len; i++) + status |= block.addr[i]; + return status; +} +#endif + + +/* Modular Exponentiation C = B^A mod N */ +uint32_t modular_exponentiation_blk(block_t a, + block_t b, + block_t modulo, + block_t result, + uint32_t size) +{ + uint32_t status; + + status = ba414ep_set_command(BA414EP_OPTYPE_MOD_EXP, size, BA414EP_BIGEND, BA414EP_SELCUR_NO_ACCELERATOR); + if (status) + return status; + + ba414ep_set_config(BA414EP_MEMLOC_10, BA414EP_MEMLOC_11, BA414EP_MEMLOC_12, BA414EP_MEMLOC_0); + + mem2CryptoRAM_rev(modulo, size, BA414EP_MEMLOC_0); + mem2CryptoRAM_rev(a, size, BA414EP_MEMLOC_10); + mem2CryptoRAM_rev(b, size, BA414EP_MEMLOC_11); + + /* Start BA414EP */ + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + + CryptoRAM2mem_rev(result, size, BA414EP_MEMLOC_12); + + return CRYPTOLIB_SUCCESS; +} + + + +uint32_t ecc_montgomery_mult(block_t curve, uint32_t curve_flags, uint32_t size, block_t scalar, block_t point, block_t result) +{ + uint32_t status; + uint8_t buffer_sc[ECC_MAX_KEY_SIZE]; + uint8_t buffer_pt[ECC_MAX_KEY_SIZE]; + + if (size > ECC_MAX_KEY_SIZE) + return CRYPTOLIB_UNSUPPORTED_ERR; + if (curve.len != 3 * size || + scalar.len != size || + (point.len && point.len != size) || + result.len != size) + return CRYPTOLIB_INVALID_PARAM; + + if(point.addr == NULL_blk.addr) + point = block_t_convert(curve.addr + 2*size, size); + + /* copy and process keys */ + memcpy_blkIn(buffer_pt, point, point.len); + memcpy_blkIn(buffer_sc, scalar, scalar.len); + if(curve.addr == sx_ecc_curve_curve25519.params.addr) + { + buffer_pt[size - 1] &= 127; //decodeUCoordinate + buffer_sc[0] &= 248; //decodeScalar25519 (clamp) + buffer_sc[size - 1] &= 127; //decodeScalar25519 (clamp) + buffer_sc[size - 1] |= 64; //decodeScalar25519 (clamp) + } + else if(curve.addr == sx_ecc_curve_curve448.params.addr) + { + buffer_sc[0] &= 252; //decodeScalar448 (clamp) + buffer_sc[size - 1] |= 128; //decodeScalar448 (clamp) + } + else + { + return CRYPTOLIB_INVALID_PARAM; + } + + + /* Set Command register - size 32 bytes - G(p) field */ + status = ba414ep_set_command(BA414EP_OPTYPE_MONTGOMERY_POINT_MULT, size, BA414EP_LITTLEEND, curve_flags); + if (status) + return status; + mem2CryptoRAM(block_t_convert(buffer_pt, ECC_MAX_KEY_SIZE), size, BA414EP_MEMLOC_2); + mem2CryptoRAM(block_t_convert(buffer_sc, ECC_MAX_KEY_SIZE), size, BA414EP_MEMLOC_3); + + /* Load parameters */ + mem2CryptoRAM(curve, size, BA414EP_MEMLOC_0); + if(!(curve.flags & BLOCK_S_CONST_ADDR)) curve.addr += size; + mem2CryptoRAM(curve, size, BA414EP_MEMLOC_1); + + /* Set Configuration register */ + ba414ep_set_config(BA414EP_MEMLOC_2, BA414EP_MEMLOC_3, BA414EP_MEMLOC_4, 0x0); + + // Start BA414EP & get status when finished + status = ba414ep_start_wait_status(); + if (status) + return CRYPTOLIB_CRYPTO_ERR; + + CryptoRAM2mem(result, size, BA414EP_MEMLOC_4); + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_point_inverse(block_t curve, block_t point, block_t result, + uint32_t size) +{ + uint32_t error; + + if (point.len != size * 2 || result.len != size * 2) + return CRYPTOLIB_INVALID_PARAM; + // result = (x, -y) + // take the opposite value of y coordinate + error = modular_substraction(curve.addr, point.addr + size, curve.addr, result.addr + size, + size); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + // copy x coordinate + memcpy(result.addr, point.addr, size); + + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_point_decompress(block_t curve, block_t point_x, uint8_t y_bit, + block_t point_y, uint32_t size, uint32_t curve_flags) +{ + uint32_t error; + if (y_bit != 0 && y_bit != 1) + return CRYPTOLIB_INVALID_PARAM; + curve_flags |= BA414EP_CMD_FLAGA(y_bit); + + if (point_x.len != size || point_y.len != size) + return CRYPTOLIB_INVALID_PARAM; + + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_DECOMP, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_set_config(BA414EP_MEMLOC_6, 0x00, BA414EP_MEMLOC_7, 0x00); + + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + + mem2CryptoRAM_rev(point_x, size, BA414EP_MEMLOC_6); + + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + CryptoRAM2mem_rev(point_y, size, BA414EP_MEMLOC_7); + + return CRYPTOLIB_SUCCESS; +} + + +uint32_t ecc_point_compute_y2(block_t curve, block_t point_x, block_t point_y2, + uint32_t size) +{ + uint32_t error; + + if (point_x.len != size || point_y2.len != size) + return CRYPTOLIB_INVALID_PARAM; + + // Y^2 = x^3 + ax + b = (x * x + a) * x + b + // Y^2 = (x * x) + error = modular_multiplication(point_x.addr, point_x.addr, curve.addr, point_y2.addr, size); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + // Y^2 = (x * x) + a + error = modular_addition(point_y2.addr, curve.addr + (4*size), curve.addr, point_y2.addr, size); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + // Y^2 = ((x * x) + a) * x + error = modular_multiplication(point_y2.addr, point_x.addr, curve.addr, point_y2.addr, size); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + // Y^2 = ((x * x) + a) * x + b + error = modular_addition(point_y2.addr, curve.addr + (5*size), curve.addr, point_y2.addr, size); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_point_mul(block_t curve, block_t scalar, block_t point, + block_t result, uint32_t size, uint32_t curve_flags) +{ + uint32_t error; + + if (point.len != size * 2 || result.len != size * 2) + return CRYPTOLIB_INVALID_PARAM; + + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); + + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + + mem2CryptoRAM_rev(scalar, scalar.len, BA414EP_MEMLOC_14); + + point2CryptoRAM_rev(point, size, BA414EP_MEMLOC_12); + +#if (PK_CM_ENABLED && PK_CM_RAND_SCALAR) + /* + * Weierstrass point addition formula does not provide the correct result + * in some exceptional cases (P+P, P+(-P), P+0, 0+P). + * With counter-measure enabled it is possible to hit one of those cases + * during the point multiplication operation. If that case, the PK engine + * will return NotInvertible flag (point at infinity) - although the correct + * final result is not the point at infinity. + * When using a random scalar value, this will happen with extremely low + * probability. However this can happen with test vectors which use very + * small scalar value (k<=32) or very large scalar value (k>=n-32). + */ + + uint8_t i; + for (i = 0; i < POINT_MULT_CM_RETRIES; i++) { + /* + * For the first iteration, the commands was set before entering the for loop + */ + error = ba414ep_start_wait_status(); + if ((error & BA414EP_STS_NOTINVERTIBLE_MASK) && is_blk_not_zero(scalar)) { + /* + * The command needs to be reset before retrying, in order to generate another random. + */ + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + continue; + } + else + break; + } + if (error) { + if (i == POINT_MULT_CM_RETRIES) + CRYPTOLIB_PRINTF("ecc_point_mul: exceeded number of retries\n"); + return CRYPTOLIB_CRYPTO_ERR; + } +#else + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; +#endif + CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_6); + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_point_add(block_t curve, block_t point_a, block_t point_b, + block_t result, uint32_t size, uint32_t curve_flags) +{ + uint32_t error; + + if (point_a.len != size * 2 || point_b.len != size * 2 || result.len != size * 2) + return CRYPTOLIB_INVALID_PARAM; + + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_ADD, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_8, BA414EP_MEMLOC_10, 0x0); + + // Load curve parameters + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + + point2CryptoRAM_rev(point_a, size, BA414EP_MEMLOC_6); + point2CryptoRAM_rev(point_b, size, BA414EP_MEMLOC_8); + + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + // Fetch the results + CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_10); + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_is_point_on_curve(block_t curve, block_t point, uint32_t size, + uint32_t curve_flags) +{ + uint32_t error; + if (point.len != size * 2) + return CRYPTOLIB_INVALID_PARAM; + + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_CHECK_POINTONCURVE, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + point2CryptoRAM_rev(point, size , BA414EP_MEMLOC_6); + + ba414ep_set_config(BA414EP_MEMLOC_6, 0x00, 0x00, 0x0); + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_INVALID_POINT; + return CRYPTOLIB_SUCCESS; +} + +uint32_t ecc_pt_muladd(block_t curve, block_t scalar_m, block_t point1, + block_t scalar_n, block_t point2, block_t result, uint32_t size, uint32_t curve_flags) +{ + uint32_t error; + + /* first multiply 'point1' with the 'scalar_m' */ + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_6, 0x0); + // Load curve parameters + ba414ep_load_curve(curve, size, BA414EP_BIGEND, 1); + // Location 14 -> scalar_m + mem2CryptoRAM_rev(scalar_m, size, BA414EP_MEMLOC_14); + // Location 12 -> point1 x, Location 13 -> point1 y + point2CryptoRAM_rev(point1, size, BA414EP_MEMLOC_12); + // Start BA414EP + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + /* next multiply 'point2' with the 'scalar_m' */ + // Already done: ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_MULT, size, BA414EP_BIGEND, curve_flags); + ba414ep_set_config(BA414EP_MEMLOC_12, BA414EP_MEMLOC_14, BA414EP_MEMLOC_8, 0x0); + // Location 14 -> scalar_n + mem2CryptoRAM_rev(scalar_n, size, BA414EP_MEMLOC_14); + // Location 12 -> point2 x, Location 13 -> point2 y + point2CryptoRAM_rev(point2, size, BA414EP_MEMLOC_12); + // Start BA414EP + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + /* Add the results of the 2 products*/ + error = ba414ep_set_command(BA414EP_OPTYPE_ECC_POINT_ADD, size, BA414EP_BIGEND, curve_flags); + if (error) + return error; + ba414ep_set_config(BA414EP_MEMLOC_6, BA414EP_MEMLOC_8, BA414EP_MEMLOC_10, 0x0); + // Start BA414EP + error = ba414ep_start_wait_status(); + if (error) + return CRYPTOLIB_CRYPTO_ERR; + + // Fetch the results + CryptoRAM2point_rev(result, size, BA414EP_MEMLOC_10); + + return CRYPTOLIB_SUCCESS; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c index b47537d..09efa6b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c @@ -1,121 +1,121 @@ -#include -#include -#include "sx_math.h" -#include "sx_rng.h" -#include "sx_errors.h" -#include "cryptolib_def.h" -/** - * @brief Random Number Generator Abstraction for CryptoSoC - * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved - * @file - */ - -/* This function implements one of the methods approved by FIPS 186-4 to - * generate a random number k with 1 <= k < n. - * - * Get a random value rnd of the appropriate length. - * If rnd > n -2 - * Try another value - * Else - * k = rnd + 1 - */ -uint32_t sx_rng_get_rand_lt_n_blk(block_t dst, block_t n, struct sx_rng rng) -{ - CRYPTOLIB_ASSERT_NM(dst.flags == BLOCK_S_INCR_ADDR); - CRYPTOLIB_ASSERT_NM(n.flags == BLOCK_S_INCR_ADDR); - - if ((dst.len != n.len) || !(n.addr[n.len - 1] & 0x01)) /* n must be odd */ - return CRYPTOLIB_INVALID_PARAM; - - bool rnd_invalid; - - /* Check what is the most significant bit of n and compute an index of and a - * mask for the most significant byte that can be used to remove the leading - * zeros. - */ - uint32_t index; - uint8_t msb_mask; - for (index = 0; !n.addr[index]; index++); /* since n is odd, at minimum the - * least significant byte should be - * different from 0 */ - for (msb_mask = 0xFF; n.addr[index] & msb_mask; msb_mask <<= 1); - - /* Create container for random value from RNG, pointing to the same buffer as - * dst but referring only to [MSB-1:0] instead of [len-1:0]. - * Force the leading, non-significant bytes to zero. - */ - memset(dst.addr, 0, index); - block_t rnd = block_t_convert(dst.addr + index, dst.len - index); - - do { - /* Get a random value */ - rng.get_rand_blk(rng.param, rnd); - - /* Mask off the leading non-significant bits. Keep only the bits that are - * relevant according to msb_mask. This is done to speed up the process of - * finding a proper random value. - * For example: - * If the highest byte of n is 0x06, the chance that we get a random with - * a highest byte <= 0x06 is only 7/256 without masking. - * With the masking process (msb_mask = 0xF8, ~msb_mask = 0x07) we - * significantly increase the chances of immediately finding a suitable - * random. - */ - dst.addr[index] &= ~msb_mask; /*Note that dst.addr[index] = rnd.addr[0]*/ - - /* Check if rnd > n-2 (constant time comparison) */ - bool gt = false; - bool eq = true; - bool n_gt_1 = false; - - for (uint32_t i = 0; i < dst.len; i++) { - uint32_t leftop = dst.addr[i]; - uint32_t rightop = n.addr[i]; - - /* We rephrase rnd > n-2 as rnd >= n-1. Since n is odd, n-1 is obtained - * by masking 1 bit. - */ - if (i == dst.len - 1) { - rightop &= 0xFE; - } - - /* We use a trick to determine whether leftop >= rightop to avoid - * possible time dependency in the implementations of ">", "<" and "==". - * If leftop > rightop then (rightop - leftop) will be 0xFFFFFFxx. - * If leftop <= rightop then (rightop - leftop) will be 0x000000xx. - * By shifting out the xx, we can determine the relation between left - * and right. - * - * A similar trick is used to determine whether leftop == rightop. - * If leftop == rightop then (rightop ^ leftop) - 1 will be 0xFFFFFFFF. - * If leftop != rightop then (rightop ^ leftop) - 1 will be 0x000000xx. - * - * By muxing eq with eq, we ensure that eq will be zero from the first - * different byte onwards. - * By muxing the leftop >= rightop check with eq, we ensure that it - * only has an effect when executed on the first most significant byte - * that is different between the arrays. - */ - gt |= (bool) ((rightop - leftop) >> 8) & eq; - eq &= (bool) (((rightop ^ leftop) - 1) >> 8); - - /* We check that the number is greather than 1 (n_gt_1 ) in the loop - * to avoid to have a big buffer with a value equal to one - * (ex : 0x000001). - * Using this loop instead of create another loop for this check - * allow to not lose time for a check that should very rarely passed. - */ - n_gt_1 |= (bool)rightop; - } - if (n_gt_1 == false) - return CRYPTOLIB_INVALID_PARAM; - - rnd_invalid = gt | eq; - - } while (rnd_invalid); - - /* Compute k = rnd + 1 (constant time increment) */ - sx_math_array_incr(dst.addr, dst.len, 1); - - return CRYPTOLIB_SUCCESS; -} +#include +#include +#include "sx_math.h" +#include "sx_rng.h" +#include "sx_errors.h" +#include "cryptolib_def.h" +/** + * @brief Random Number Generator Abstraction for CryptoSoC + * @copyright Copyright (c) 2018 Silex Insight. All Rights reserved + * @file + */ + +/* This function implements one of the methods approved by FIPS 186-4 to + * generate a random number k with 1 <= k < n. + * + * Get a random value rnd of the appropriate length. + * If rnd > n -2 + * Try another value + * Else + * k = rnd + 1 + */ +uint32_t sx_rng_get_rand_lt_n_blk(block_t dst, block_t n, struct sx_rng rng) +{ + CRYPTOLIB_ASSERT_NM(dst.flags == BLOCK_S_INCR_ADDR); + CRYPTOLIB_ASSERT_NM(n.flags == BLOCK_S_INCR_ADDR); + + if ((dst.len != n.len) || !(n.addr[n.len - 1] & 0x01)) /* n must be odd */ + return CRYPTOLIB_INVALID_PARAM; + + bool rnd_invalid; + + /* Check what is the most significant bit of n and compute an index of and a + * mask for the most significant byte that can be used to remove the leading + * zeros. + */ + uint32_t index; + uint8_t msb_mask; + for (index = 0; !n.addr[index]; index++); /* since n is odd, at minimum the + * least significant byte should be + * different from 0 */ + for (msb_mask = 0xFF; n.addr[index] & msb_mask; msb_mask <<= 1); + + /* Create container for random value from RNG, pointing to the same buffer as + * dst but referring only to [MSB-1:0] instead of [len-1:0]. + * Force the leading, non-significant bytes to zero. + */ + memset(dst.addr, 0, index); + block_t rnd = block_t_convert(dst.addr + index, dst.len - index); + + do { + /* Get a random value */ + rng.get_rand_blk(rng.param, rnd); + + /* Mask off the leading non-significant bits. Keep only the bits that are + * relevant according to msb_mask. This is done to speed up the process of + * finding a proper random value. + * For example: + * If the highest byte of n is 0x06, the chance that we get a random with + * a highest byte <= 0x06 is only 7/256 without masking. + * With the masking process (msb_mask = 0xF8, ~msb_mask = 0x07) we + * significantly increase the chances of immediately finding a suitable + * random. + */ + dst.addr[index] &= ~msb_mask; /*Note that dst.addr[index] = rnd.addr[0]*/ + + /* Check if rnd > n-2 (constant time comparison) */ + bool gt = false; + bool eq = true; + bool n_gt_1 = false; + + for (uint32_t i = 0; i < dst.len; i++) { + uint32_t leftop = dst.addr[i]; + uint32_t rightop = n.addr[i]; + + /* We rephrase rnd > n-2 as rnd >= n-1. Since n is odd, n-1 is obtained + * by masking 1 bit. + */ + if (i == dst.len - 1) { + rightop &= 0xFE; + } + + /* We use a trick to determine whether leftop >= rightop to avoid + * possible time dependency in the implementations of ">", "<" and "==". + * If leftop > rightop then (rightop - leftop) will be 0xFFFFFFxx. + * If leftop <= rightop then (rightop - leftop) will be 0x000000xx. + * By shifting out the xx, we can determine the relation between left + * and right. + * + * A similar trick is used to determine whether leftop == rightop. + * If leftop == rightop then (rightop ^ leftop) - 1 will be 0xFFFFFFFF. + * If leftop != rightop then (rightop ^ leftop) - 1 will be 0x000000xx. + * + * By muxing eq with eq, we ensure that eq will be zero from the first + * different byte onwards. + * By muxing the leftop >= rightop check with eq, we ensure that it + * only has an effect when executed on the first most significant byte + * that is different between the arrays. + */ + gt |= (bool) ((rightop - leftop) >> 8) & eq; + eq &= (bool) (((rightop ^ leftop) - 1) >> 8); + + /* We check that the number is greather than 1 (n_gt_1 ) in the loop + * to avoid to have a big buffer with a value equal to one + * (ex : 0x000001). + * Using this loop instead of create another loop for this check + * allow to not lose time for a check that should very rarely passed. + */ + n_gt_1 |= (bool)rightop; + } + if (n_gt_1 == false) + return CRYPTOLIB_INVALID_PARAM; + + rnd_invalid = gt | eq; + + } while (rnd_invalid); + + /* Compute k = rnd + 1 (constant time increment) */ + sx_math_array_incr(dst.addr, dst.len, 1); + + return CRYPTOLIB_SUCCESS; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c index 8e2bf65..4367618 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c @@ -1,374 +1,374 @@ -/** - * @file - * @brief Defines the procedures to make operations with - * the BA431 (N)DRNG - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - -#include "sx_trng.h" -#include "cryptolib_def.h" -#include "sx_memcpy.h" -#include "ba431_config.h" -#include "ba414ep_config.h" -#include -#include "sx_errors.h" - - -static bool rng_startup_failed = false; -static bool rng_needs_startup_chk = false; - -#ifndef UNITTESTS - -/** -* @brief Verify the conditioning function of the BA431 against test patterns. -* @return CRYPTOLIB_SUCCESS if successful CRYPTOLIB_CRYPTO_ERR otherwise -*/ -static uint32_t sx_trng_conditioning_test(void) -{ - const uint32_t test_data[16] = {0xE1BCC06B, 0x9199452A, 0x1A7434E1, 0x25199E7F, - 0x578A2DAE, 0x9CAC031E, 0xAC6FB79E, 0x518EAF45, - 0x461CC830, 0x11E45CA3, 0x19C1FBE5, 0xEF520A1A, - 0x45249FF6, 0x179B4FDF, 0x7B412BAD, 0x10376CE6}; - const uint32_t known_answer[4] = {0xA1CAF13F, 0x09AC1F68,0x30CA0E12, 0xA7E18675}; - const uint32_t test_key[4] = {0x16157E2B, 0xA6D2AE28,0x8815F7AB, 0x3C4FCF09}; - - uint32_t i; - uint32_t error = 0; - - /*Soft reset*/ - ba431_softreset(); - - /*Enable test mode*/ - ba431_set_nb128bitblocks(4); - ba431_set_cond_test_mode(); - - /*Write key*/ - ba431_write_conditioning_key(test_key); - - /*Write test data input*/ - for(i=0;i wait for return data to appear in FIFO*/ - while(ba431_read_fifolevel()<4); - - /*Clear control register*/ - ba431_clear_ctrl(); - - /*Compare results to known answer*/ - for(i=0;iControlReg |= ctrl_reg; - -#if AIS31_ENABLED - /*Make sure that startup test is passed for AIS31. - *That requires 4 truly random words to be present in the FIFO. - *Writing them here.*/ - if ((test == TRNG_PREALM_TEST) || (test == TRNG_ALM_TEST)) { - ba431_write_test_data(0x6EA3EE32); - ba431_write_test_data(0x507E68A4); - ba431_write_test_data(0x4D61C5C5); - ba431_write_test_data(0xAD2C4AD8); - } -#endif - - /*Trigger error*/ - for (i = 0; i < size; i++) { - ba431_write_test_data(0); - } - - /*Restore settings*/ - BA431_REGS->ControlReg &= ~ctrl_reg; - ba431_enable_ndrng(); - ba431_enable_health_test_irq(); -#if AIS31_ENABLED - ba431_enable_AIS31_test_irq(); -#endif - - return CRYPTOLIB_SUCCESS; -} - -void sx_trng_save_state(struct sx_trng_internal_state *copy) -{ - copy->control = ba431_read_controlreg(); - ba431_read_conditioning_key(copy->key); - copy->wakeup_lvl = ba431_read_fifo_wakeup_threshold(); - copy->swoff_timer = ba431_read_switch_off_timer(); - copy->clk_divider = ba431_read_clk_div(); - copy->init_wait_cnt = ba431_read_init_wait(); -} - -void sx_trng_restore_state(struct sx_trng_internal_state *source) -{ - ba431_write_init_wait(source->init_wait_cnt); - ba431_write_clk_div(source->clk_divider); - ba431_write_switch_off_timer(source->swoff_timer); - ba431_write_fifo_wakeup_threshold(source->wakeup_lvl); - ba431_write_conditioning_key(source->key); - ba431_write_controlreg(source->control); -} - -uint32_t sx_trng_raw_init(void) - { - /*Clear control register*/ - ba431_clear_ctrl(); - - /*Soft reset*/ - ba431_softreset(); - - /*Program powerdown and clock settings*/ - ba431_write_fifo_wakeup_threshold(RNG_FIFO_WAKEUP_LVL); - if (RNG_OFF_TIMER_VAL < 0) { - ba431_force_run(); - } else { - ba431_write_switch_off_timer(RNG_OFF_TIMER_VAL); - } - ba431_write_clk_div(RNG_CLKDIV); - ba431_write_init_wait(RNG_INIT_WAIT_VAL); - - /*Enable random raw mode*/ - ba431_set_raw_mode(); - - /*Enable NDRNG*/ - ba431_enable_ndrng(); - - uint32_t status = sx_trng_wait_startup(); - if (status) { - rng_startup_failed = true; - return CRYPTOLIB_CRYPTO_ERR; - } - - return status; -} +/** + * @file + * @brief Defines the procedures to make operations with + * the BA431 (N)DRNG + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + +#include "sx_trng.h" +#include "cryptolib_def.h" +#include "sx_memcpy.h" +#include "ba431_config.h" +#include "ba414ep_config.h" +#include +#include "sx_errors.h" + + +static bool rng_startup_failed = false; +static bool rng_needs_startup_chk = false; + +#ifndef UNITTESTS + +/** +* @brief Verify the conditioning function of the BA431 against test patterns. +* @return CRYPTOLIB_SUCCESS if successful CRYPTOLIB_CRYPTO_ERR otherwise +*/ +static uint32_t sx_trng_conditioning_test(void) +{ + const uint32_t test_data[16] = {0xE1BCC06B, 0x9199452A, 0x1A7434E1, 0x25199E7F, + 0x578A2DAE, 0x9CAC031E, 0xAC6FB79E, 0x518EAF45, + 0x461CC830, 0x11E45CA3, 0x19C1FBE5, 0xEF520A1A, + 0x45249FF6, 0x179B4FDF, 0x7B412BAD, 0x10376CE6}; + const uint32_t known_answer[4] = {0xA1CAF13F, 0x09AC1F68,0x30CA0E12, 0xA7E18675}; + const uint32_t test_key[4] = {0x16157E2B, 0xA6D2AE28,0x8815F7AB, 0x3C4FCF09}; + + uint32_t i; + uint32_t error = 0; + + /*Soft reset*/ + ba431_softreset(); + + /*Enable test mode*/ + ba431_set_nb128bitblocks(4); + ba431_set_cond_test_mode(); + + /*Write key*/ + ba431_write_conditioning_key(test_key); + + /*Write test data input*/ + for(i=0;i wait for return data to appear in FIFO*/ + while(ba431_read_fifolevel()<4); + + /*Clear control register*/ + ba431_clear_ctrl(); + + /*Compare results to known answer*/ + for(i=0;iControlReg |= ctrl_reg; + +#if AIS31_ENABLED + /*Make sure that startup test is passed for AIS31. + *That requires 4 truly random words to be present in the FIFO. + *Writing them here.*/ + if ((test == TRNG_PREALM_TEST) || (test == TRNG_ALM_TEST)) { + ba431_write_test_data(0x6EA3EE32); + ba431_write_test_data(0x507E68A4); + ba431_write_test_data(0x4D61C5C5); + ba431_write_test_data(0xAD2C4AD8); + } +#endif + + /*Trigger error*/ + for (i = 0; i < size; i++) { + ba431_write_test_data(0); + } + + /*Restore settings*/ + BA431_REGS->ControlReg &= ~ctrl_reg; + ba431_enable_ndrng(); + ba431_enable_health_test_irq(); +#if AIS31_ENABLED + ba431_enable_AIS31_test_irq(); +#endif + + return CRYPTOLIB_SUCCESS; +} + +void sx_trng_save_state(struct sx_trng_internal_state *copy) +{ + copy->control = ba431_read_controlreg(); + ba431_read_conditioning_key(copy->key); + copy->wakeup_lvl = ba431_read_fifo_wakeup_threshold(); + copy->swoff_timer = ba431_read_switch_off_timer(); + copy->clk_divider = ba431_read_clk_div(); + copy->init_wait_cnt = ba431_read_init_wait(); +} + +void sx_trng_restore_state(struct sx_trng_internal_state *source) +{ + ba431_write_init_wait(source->init_wait_cnt); + ba431_write_clk_div(source->clk_divider); + ba431_write_switch_off_timer(source->swoff_timer); + ba431_write_fifo_wakeup_threshold(source->wakeup_lvl); + ba431_write_conditioning_key(source->key); + ba431_write_controlreg(source->control); +} + +uint32_t sx_trng_raw_init(void) + { + /*Clear control register*/ + ba431_clear_ctrl(); + + /*Soft reset*/ + ba431_softreset(); + + /*Program powerdown and clock settings*/ + ba431_write_fifo_wakeup_threshold(RNG_FIFO_WAKEUP_LVL); + if (RNG_OFF_TIMER_VAL < 0) { + ba431_force_run(); + } else { + ba431_write_switch_off_timer(RNG_OFF_TIMER_VAL); + } + ba431_write_clk_div(RNG_CLKDIV); + ba431_write_init_wait(RNG_INIT_WAIT_VAL); + + /*Enable random raw mode*/ + ba431_set_raw_mode(); + + /*Enable NDRNG*/ + ba431_enable_ndrng(); + + uint32_t status = sx_trng_wait_startup(); + if (status) { + rng_startup_failed = true; + return CRYPTOLIB_CRYPTO_ERR; + } + + return status; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sxregs.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sxregs.h index 4b5ab8e..47eec6a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sxregs.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_cryptoacc_library/src/sxregs.h @@ -1,17 +1,17 @@ -/** - * @file - * @brief Implement the register access API declared in "sxregs.h" - * for baremetal - * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved - */ - - -#ifndef SXREGS_H -#define SXREGS_H - -#include - -#define WR_REG32(reg, value) (*((volatile uint32_t *) (reg))) = (value) -#define RD_REG32(reg) (*((volatile uint32_t *)(reg))) - -#endif +/** + * @file + * @brief Implement the register access API declared in "sxregs.h" + * for baremetal + * @copyright Copyright (c) 2016-2018 Silex Insight. All Rights reserved + */ + + +#ifndef SXREGS_H +#define SXREGS_H + +#include + +#define WR_REG32(reg, value) (*((volatile uint32_t *) (reg))) = (value) +#define RD_REG32(reg) (*((volatile uint32_t *)(reg))) + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h index 4aa8d2e..402a9d7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_acceleration.h @@ -1,524 +1,524 @@ -/***************************************************************************//** - * @file - * @brief Mbed TLS device acceleration capabilities. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_MBEDTLS_ACCELERATION_H -#define SLI_MBEDTLS_ACCELERATION_H - -// This condition makes it possible to disable alt-plugins for the classic -// Mbed TLS APIs (overriding the user-exposed config option). This is notably -// used on the NS side of TrustZone-enabled applications. -#if !defined(NO_CRYPTO_ACCELERATION) - -#if defined(SEMAILBOX_PRESENT) - #include "em_se.h" -#endif - -// ----------------------------------------------------------------------------- -// Acceleration enabling defines - -/** \def MBEDTLS_PSA_CRYPTO_DRIVERS - * - * Enable support for the experimental PSA crypto driver interface. - * - * Requires: \ref MBEDTLS_PSA_CRYPTO_C. - * - * \warning This interface is experimental and may change or be removed - * without notice. - */ -#if defined(MBEDTLS_PSA_CRYPTO_C) - #define MBEDTLS_PSA_CRYPTO_DRIVERS -#endif - -/** - * \def MBEDTLS_AES_ALT - * - * Enable hardware acceleration for the AES block cipher modes through - * the mbed TLS APIs. - * - * Module: sl_mbedtls_support/src/crypto_aes.c for devices with CRYPTO, - * sl_mbedtls_support/src/se_aes.c for devices with HSE, - * sl_mbedtls_support/src/cryptoacc_aes.c for devices with CRYPTOACC, - * sl_mbedtls_support/src/aes_aes.c for devices with AES - * - * See \ref MBEDTLS_AES_C for more information. - */ -#if defined(_SILICON_LABS_32B_SERIES) - #define MBEDTLS_AES_ALT -#endif -#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) - #define AES_192_SUPPORTED -#endif - -/** - * \def MBEDTLS_CCM_ALT - * - * Enable hardware acceleration of CCM through mbed TLS APIs. - * Not enabled when PSA Crypto is present in the build together with the PSA driver for CCM, - * as that would preclude software fallback for cases where the hardware capabilites do not - * cover the full potential usage of the PSA Driver API - * - * Module: sl_mbedtls_support/src/mbedtls_ccm.c for all devices, plus: - * - sl_psa_driver/src/sli_se_transparent_driver_aead.c and sl_psa_driver/src/sli_se_driver_aead.c for devices with HSE, - * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c for devices with CRYPTOACC - * - sl_psa_driver/src/sli_crypto_transparent_driver_aead.c for devices with CRYPTO - * - * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See MBEDTLS_CCM_C for more information. - */ -#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ - || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_CCM_ENCRYPT) && defined(SE_COMMAND_AES_CCM_DECRYPT) ) -// Remove this when full multipart support is present in the CCM ALT driver -// Todo: remove guard when [PSEC-1954][PSEC-2109][PSEC-3133] are done - #if !(defined(MBEDTLS_PSA_CRYPTO_DRIVERS)) - #define MBEDTLS_CCM_ALT - #endif -#endif - -/** - * \def MBEDTLS_CMAC_ALT - * - * Enable hardware acceleration CMAC through mbed TLS APIs. - * - * Module: sl_mbedtls_support/src/mbedtls_cmac.c for all devices, plus: - * - sl_psa_driver/src/sli_se_transparent_driver_mac.c and sl_psa_driver/src/sli_se_driver_mac.c for devices with HSE, - * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c for devices with CRYPTOACC - * - * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CMAC_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See MBEDTLS_CMAC_C for more information. - */ -#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ - || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_CMAC)) - #define MBEDTLS_CMAC_ALT -#endif - -/** - * \def MBEDTLS_GCM_ALT - * - * Enable hardware acceleration GCM. - * - * Module: sl_mbedtls_support/src/se_gcm.c for devices with HSE, - * sl_mbedtls_support/src/cryptoacc_gcm.c for devices with CRYPTOACC - * - * Requires: \ref MBEDTLS_GCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See MBEDTLS_GCM_C for more information. - */ -#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ - || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_GCM_ENCRYPT) && defined(SE_COMMAND_AES_GCM_ENCRYPT) ) - #define MBEDTLS_GCM_ALT -#endif - -/** - * \def MBEDTLS_SHA1_ALT - * - * Enable hardware acceleration for the SHA1 cryptographic hash algorithm - * through the mbed TLS APIs. - * - * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: - * - sl_psa_driver/src/sli_crypto_transparent_driver_hash.c for devices with CRYPTO, - * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, - * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC - * - * Caller: library/mbedtls_md.c - * library/ssl_cli.c - * library/ssl_srv.c - * library/ssl_tls.c - * library/x509write_crt.c - * - * Requires: \ref MBEDTLS_SHA1_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See MBEDTLS_SHA1_C for more information. - */ -#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ - || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_OPTION_HASH_SHA1)) - #define MBEDTLS_SHA1_ALT -#endif - -/** - * \def MBEDTLS_SHA256_ALT - * - * Enable hardware acceleration for the SHA-224 and SHA-256 cryptographic - * hash algorithms through the mbed TLS APIs. - * - * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: - * - sl_psa_driver/src/sli_crypto_transparent_driver_hash.c for devices with CRYPTO, - * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, - * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC - * - * Caller: library/entropy.c - * library/mbedtls_md.c - * library/ssl_cli.c - * library/ssl_srv.c - * library/ssl_tls.c - * - * Requires: \ref MBEDTLS_SHA256_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See MBEDTLS_SHA256_C for more information. - */ -#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ - || (defined(SEMAILBOX_PRESENT) \ - && (defined(SE_COMMAND_OPTION_HASH_SHA256) || defined(SE_COMMAND_OPTION_HASH_SHA224) ) ) - #define MBEDTLS_SHA256_ALT -#endif - -/** - * \def MBEDTLS_SHA512_ALT - * - * Enable hardware acceleration for the SHA-384 and SHA-512 cryptographic - * hash algorithms through the mbed TLS APIs. - * - * Module: sl_mbedtls_support/src/mbedtls_sha.c - * sl_psa_driver/src/sli_se_transparent_driver_hash.c - * - * Requires: \ref MBEDTLS_SHA512_C - * - * See MBEDTLS_SHA512_C for more information. - */ -#if defined(SEMAILBOX_PRESENT) \ - && (defined(SE_COMMAND_OPTION_HASH_SHA512) || defined(SE_COMMAND_OPTION_HASH_SHA384) ) - #define MBEDTLS_SHA512_ALT -#endif - -/** - * \def MBEDTLS_ECP_INTERNAL_ALT - * \def ECP_SHORTWEIERSTRASS - * \def MBEDTLS_ECP_ADD_MIXED_ALT - * \def MBEDTLS_ECP_DOUBLE_JAC_ALT - * \def MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT - * \def MBEDTLS_ECP_NORMALIZE_JAC_ALT - * - * Enable hardware acceleration for the elliptic curve over GF(p) library - * in mbed TLS. This accelerates the raw arithmetic operations. - * - * Module: sl_mbedtls_support/src/crypto_ecp.c - * - * Caller: library/ecp.c - * - * Requires: \ref MBEDTLS_BIGNUM_C, \ref MBEDTLS_ECP_C and at least one - * MBEDTLS_ECP_DP_XXX_ENABLED and CRYPTO_PRESENT - */ -#if defined(CRYPTO_PRESENT) \ - && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED)) - #define MBEDTLS_ECP_INTERNAL_ALT - #define ECP_SHORTWEIERSTRASS - #define MBEDTLS_ECP_ADD_MIXED_ALT - #define MBEDTLS_ECP_DOUBLE_JAC_ALT - #define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT - #define MBEDTLS_ECP_NORMALIZE_JAC_ALT - #define MBEDTLS_ECP_RANDOMIZE_JAC_ALT -#endif - -/** - * \def MBEDTLS_ECDH_COMPUTE_SHARED_ALT - * \def MBEDTLS_ECDH_GEN_PUBLIC_ALT - * \def MBEDTLS_ECDSA_GENKEY_ALT - * \def MBEDTLS_ECDSA_SIGN_ALT - * \def MBEDTLS_ECDSA_VERIFY_ALT - * - * Enable hardware acceleration for certain ECC operations. - * - * Module: sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c for all devices, plus: - * - sl_psa_driver/src/sli_se_driver_signature.c and sl_psa_driver/src/sli_se_driver_key_management.c for devices with HSE, - * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c and sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c for devices with CRYPTOACC - * - * Requires: \ref MBEDTLS_ECP_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) - * - * See \ref MBEDTLS_ECP_C for more information. - */ -#if defined(CRYPTOACC_PRESENT) -#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ - || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) - #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT - #define MBEDTLS_ECDH_GEN_PUBLIC_ALT -#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... - -#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) ) - #define MBEDTLS_ECDSA_GENKEY_ALT - #define MBEDTLS_ECDSA_VERIFY_ALT - #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) - #define MBEDTLS_ECDSA_SIGN_ALT - #endif -#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... - -#endif /* CRYPTOACC */ - -#if defined(SEMAILBOX_PRESENT) - -#if !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ - && !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) - -/* Do not enable the ECDH and/or ECDSA ALT implementations when one or more - * non-accelerated curves are included, then the application needs to - * use the standard mbedTLS library. */ - - #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ - && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) - #if defined(SE_COMMAND_CREATE_KEY) - #define MBEDTLS_ECDH_GEN_PUBLIC_ALT - #endif - #if defined(SE_COMMAND_DH) - #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT - #endif - #endif - - #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ - && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) ) ) - #if defined(SE_COMMAND_CREATE_KEY) - #define MBEDTLS_ECDSA_GENKEY_ALT - #endif - #if defined(SE_COMMAND_SIGNATURE_SIGN) - #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) - #define MBEDTLS_ECDSA_SIGN_ALT - #endif - #endif - #if defined(SE_COMMAND_SIGNATURE_VERIFY) - #define MBEDTLS_ECDSA_VERIFY_ALT - #endif - #endif - -#endif // #if !defined(MBEDTLS_ECP_DP_XXXX_ENABLED) && ... - -#if defined(SE_COMMAND_JPAKE_GEN_SESSIONKEY) -/** - * \def MBEDTLS_ECJPAKE_ALT - * - * Enable hardware acceleration JPAKE. - * - * Module: sl_mbedtls_support/src/se_jpake.c - * - * Requires: \ref MBEDTLS_ECJPAKE_C (SEMAILBOX_PRESENT) - * - * See \ref MBEDTLS_ECJPAKE_C for more information. - */ -#define MBEDTLS_ECJPAKE_ALT -#endif - -#endif /* SEMAILBOX_PRESENT */ - -/** - * \def MBEDTLS_ENTROPY_ADC_PRESENT - * - * Decode if device supports retrieving entropy data from the ADC - * incorporated on devices from Silicon Labs. - * - * Requires ADC_PRESENT && _ADC_SINGLECTRLX_VREFSEL_VENTROPY && - * _SILICON_LABS_32B_SERIES_1 - */ -#if defined(ADC_PRESENT) \ - && defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY) \ - && defined(_SILICON_LABS_32B_SERIES_1) -#define MBEDTLS_ENTROPY_ADC_PRESENT -#endif - -/** - * \def MBEDTLS_TRNG_PRESENT - * - * Determine whether mbedTLS supports the TRNG (if present) on the device. - * - * Requires TRNG_PRESENT and not _SILICON_LABS_GECKO_INTERNAL_SDID_95 (xg14) - */ -#if defined(TRNG_PRESENT) \ - && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) -#undef MBEDTLS_TRNG_PRESENT -#define MBEDTLS_TRNG_PRESENT -#endif - -/** - * \def MBEDTLS_ENTROPY_RAIL_PRESENT - * - * Determine whether mbedTLS supports RAIL entropy on the device. - * This is currently only available on a few series-1 devices - * where there is no functional TRNG. - * - * Requires _EFR_DEVICE and one of - * _SILICON_LABS_GECKO_INTERNAL_SDID_80 - * _SILICON_LABS_GECKO_INTERNAL_SDID_89 - * _SILICON_LABS_GECKO_INTERNAL_SDID_95 - */ -#if defined(_EFR_DEVICE) \ - && (defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ - || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) ) -#if defined(SL_CATALOG_RAIL_LIB_PRESENT) -#undef MBEDTLS_ENTROPY_RAIL_PRESENT -#define MBEDTLS_ENTROPY_RAIL_PRESENT -#endif -#endif - -/* Default ECC configuration for Silicon Labs devices: */ - -/* Save RAM by adjusting to our exact needs */ -#ifndef MBEDTLS_MPI_MAX_SIZE -#define MBEDTLS_MPI_MAX_SIZE 32 // 384 bits is 48 bytes -#endif - -/* - Set MBEDTLS_ECP_WINDOW_SIZE to configure - ECC point multiplication window size, see ecp.h: - 2 = Save RAM at the expense of speed - 3 = Improve speed at the expense of RAM - 4 = Optimize speed at the expense of RAM - */ -#define MBEDTLS_ECP_WINDOW_SIZE 2 -#define MBEDTLS_ECP_FIXED_POINT_OPTIM 0 - -#if defined(MBEDTLS_ECP_C) -/* First section: devices with ECP hardware acceleration enabled */ -#if defined(MBEDTLS_ECP_INTERNAL_ALT) -/* When the internal ECP implementation is overridden, apply optimisation - * only when it benefits us for curves we can't accelerate. */ -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -#define MBEDTLS_ECP_NIST_OPTIM -#endif /* Non-accelerated SECP R1 curves requested */ -/* If only accelerated curves are requested, and no non-accelerated ones, - * we can turn on the NO_FALLBACK flag to dead-strip a whole lot of ECC - * math software implementation. */ -#if (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) ) \ - && !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ - || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED)) -#define MBEDTLS_ECP_NO_FALLBACK -#endif /* Only ECP-hardware-accelerated curves requested */ -/* Second section: devices with ECDSA / ECDH hardware acceleration (without ECP) */ -#elif defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ - || defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ - || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ - || defined(MBEDTLS_ECDSA_SIGN_ALT) \ - || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ -/* When the upper layers calling into ECP_C are overridden, apply optimisation - * only when it benefits us for curves we can't accelerate. */ -#if (defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) ) \ - || defined(CRYPTOACC_PRESENT) -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ - || (defined(MBEDTLS_ECDSA_DETERMINISTIC) \ - && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) -#define MBEDTLS_ECP_NIST_OPTIM -#endif /* Non-accelerated SECP R1 curves requested */ -#endif /* Devices not implementing the full suite of SECP R1 curves */ -/* Third section: configurations without any ECP/ECC acceleration at all */ -#else -/* When there's no ECC acceleration at all, apply optimisation always when - * applicable curves are present. */ -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ - || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -#define MBEDTLS_ECP_NIST_OPTIM -#endif /* Software-optimisable curve requested */ -#endif /* Different acceleration constellations */ -#endif /* MBEDTLS_ECP_C */ - -/* - Set max CTR-DRBG seed input size to reasonable default in order to reduce - stack usage when using CTR-DRBG. - NOTE: - Due to existing dependencies we need to keep the setting of - MBEDTLS_CTR_DRBG_MAX_SEED_INPUT here. However this is subject to be moved - later, to sl_mbedtls_config.h or mbedtls_config_autogen.h in order to be more - practical for configuration. - */ -#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) -#if !(defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ - && defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ - && defined(MBEDTLS_ECDSA_GENKEY_ALT) \ - && defined(MBEDTLS_ECDSA_SIGN_ALT) \ - && defined(MBEDTLS_ECDSA_VERIFY_ALT)) -/* - If any of ECDH and/or ECDSA ALT is/are not enabled, then the ecp_mul_xxx() - functions will seed the internal drbg (for randomization of projective - coordinates) with the private key of size corresponding to the curve - hence we will need to adjust: - */ -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -// For key size 521 bits (=66 bytes) add 66 - 32 (256bits default) = 34 bytes -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 66 - 32) -#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) -// For key size 512 bits (=64 bytes) add 64 - 32 (256bits default) = 32 bytes -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 64 - 32) -#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) -// For key size 448 bits (=56 bytes) add 56 - 32 (256bits default) = 24 bytes -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 56 - 32) -#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) -// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) -#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) -// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) -#else -// Default value to support curve sizes up to 256 bits ( 32 bytes ) -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2) -#endif -#endif -#endif - -#endif // !NO_CRYPTO_ACCELERATION - -#endif // SLI_MBEDTLS_ACCELERATION_H +/***************************************************************************//** + * @file + * @brief Mbed TLS device acceleration capabilities. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MBEDTLS_ACCELERATION_H +#define SLI_MBEDTLS_ACCELERATION_H + +// This condition makes it possible to disable alt-plugins for the classic +// Mbed TLS APIs (overriding the user-exposed config option). This is notably +// used on the NS side of TrustZone-enabled applications. +#if !defined(NO_CRYPTO_ACCELERATION) + +#if defined(SEMAILBOX_PRESENT) + #include "em_se.h" +#endif + +// ----------------------------------------------------------------------------- +// Acceleration enabling defines + +/** \def MBEDTLS_PSA_CRYPTO_DRIVERS + * + * Enable support for the experimental PSA crypto driver interface. + * + * Requires: \ref MBEDTLS_PSA_CRYPTO_C. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +#if defined(MBEDTLS_PSA_CRYPTO_C) + #define MBEDTLS_PSA_CRYPTO_DRIVERS +#endif + +/** + * \def MBEDTLS_AES_ALT + * + * Enable hardware acceleration for the AES block cipher modes through + * the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/crypto_aes.c for devices with CRYPTO, + * sl_mbedtls_support/src/se_aes.c for devices with HSE, + * sl_mbedtls_support/src/cryptoacc_aes.c for devices with CRYPTOACC, + * sl_mbedtls_support/src/aes_aes.c for devices with AES + * + * See \ref MBEDTLS_AES_C for more information. + */ +#if defined(_SILICON_LABS_32B_SERIES) + #define MBEDTLS_AES_ALT +#endif +#if defined(CRYPTOACC_PRESENT) || defined(SEMAILBOX_PRESENT) + #define AES_192_SUPPORTED +#endif + +/** + * \def MBEDTLS_CCM_ALT + * + * Enable hardware acceleration of CCM through mbed TLS APIs. + * Not enabled when PSA Crypto is present in the build together with the PSA driver for CCM, + * as that would preclude software fallback for cases where the hardware capabilites do not + * cover the full potential usage of the PSA Driver API + * + * Module: sl_mbedtls_support/src/mbedtls_ccm.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_aead.c and sl_psa_driver/src/sli_se_driver_aead.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c for devices with CRYPTOACC + * - sl_psa_driver/src/sli_crypto_transparent_driver_aead.c for devices with CRYPTO + * + * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_CCM_C for more information. + */ +#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ + || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_CCM_ENCRYPT) && defined(SE_COMMAND_AES_CCM_DECRYPT) ) +// Remove this when full multipart support is present in the CCM ALT driver +// Todo: remove guard when [PSEC-1954][PSEC-2109][PSEC-3133] are done + #if !(defined(MBEDTLS_PSA_CRYPTO_DRIVERS)) + #define MBEDTLS_CCM_ALT + #endif +#endif + +/** + * \def MBEDTLS_CMAC_ALT + * + * Enable hardware acceleration CMAC through mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_cmac.c for all devices, plus: + * - sl_psa_driver/src/sli_se_transparent_driver_mac.c and sl_psa_driver/src/sli_se_driver_mac.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_AES_C and \ref MBEDTLS_CMAC_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_CMAC_C for more information. + */ +#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ + || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_CMAC)) + #define MBEDTLS_CMAC_ALT +#endif + +/** + * \def MBEDTLS_GCM_ALT + * + * Enable hardware acceleration GCM. + * + * Module: sl_mbedtls_support/src/se_gcm.c for devices with HSE, + * sl_mbedtls_support/src/cryptoacc_gcm.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_GCM_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_GCM_C for more information. + */ +#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ + || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_AES_GCM_ENCRYPT) && defined(SE_COMMAND_AES_GCM_ENCRYPT) ) + #define MBEDTLS_GCM_ALT +#endif + +/** + * \def MBEDTLS_SHA1_ALT + * + * Enable hardware acceleration for the SHA1 cryptographic hash algorithm + * through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: + * - sl_psa_driver/src/sli_crypto_transparent_driver_hash.c for devices with CRYPTO, + * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC + * + * Caller: library/mbedtls_md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509write_crt.c + * + * Requires: \ref MBEDTLS_SHA1_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_SHA1_C for more information. + */ +#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ + || (defined(SEMAILBOX_PRESENT) && defined(SE_COMMAND_OPTION_HASH_SHA1)) + #define MBEDTLS_SHA1_ALT +#endif + +/** + * \def MBEDTLS_SHA256_ALT + * + * Enable hardware acceleration for the SHA-224 and SHA-256 cryptographic + * hash algorithms through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c for all devices, plus: + * - sl_psa_driver/src/sli_crypto_transparent_driver_hash.c for devices with CRYPTO, + * - sl_psa_driver/src/sli_se_transparent_driver_hash.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c for devices with CRYPTOACC + * + * Caller: library/entropy.c + * library/mbedtls_md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * Requires: \ref MBEDTLS_SHA256_C and (CRYPTO_PRESENT or CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See MBEDTLS_SHA256_C for more information. + */ +#if defined(CRYPTO_PRESENT) || defined(CRYPTOACC_PRESENT) \ + || (defined(SEMAILBOX_PRESENT) \ + && (defined(SE_COMMAND_OPTION_HASH_SHA256) || defined(SE_COMMAND_OPTION_HASH_SHA224) ) ) + #define MBEDTLS_SHA256_ALT +#endif + +/** + * \def MBEDTLS_SHA512_ALT + * + * Enable hardware acceleration for the SHA-384 and SHA-512 cryptographic + * hash algorithms through the mbed TLS APIs. + * + * Module: sl_mbedtls_support/src/mbedtls_sha.c + * sl_psa_driver/src/sli_se_transparent_driver_hash.c + * + * Requires: \ref MBEDTLS_SHA512_C + * + * See MBEDTLS_SHA512_C for more information. + */ +#if defined(SEMAILBOX_PRESENT) \ + && (defined(SE_COMMAND_OPTION_HASH_SHA512) || defined(SE_COMMAND_OPTION_HASH_SHA384) ) + #define MBEDTLS_SHA512_ALT +#endif + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * \def ECP_SHORTWEIERSTRASS + * \def MBEDTLS_ECP_ADD_MIXED_ALT + * \def MBEDTLS_ECP_DOUBLE_JAC_ALT + * \def MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT + * \def MBEDTLS_ECP_NORMALIZE_JAC_ALT + * + * Enable hardware acceleration for the elliptic curve over GF(p) library + * in mbed TLS. This accelerates the raw arithmetic operations. + * + * Module: sl_mbedtls_support/src/crypto_ecp.c + * + * Caller: library/ecp.c + * + * Requires: \ref MBEDTLS_BIGNUM_C, \ref MBEDTLS_ECP_C and at least one + * MBEDTLS_ECP_DP_XXX_ENABLED and CRYPTO_PRESENT + */ +#if defined(CRYPTO_PRESENT) \ + && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED)) + #define MBEDTLS_ECP_INTERNAL_ALT + #define ECP_SHORTWEIERSTRASS + #define MBEDTLS_ECP_ADD_MIXED_ALT + #define MBEDTLS_ECP_DOUBLE_JAC_ALT + #define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT + #define MBEDTLS_ECP_NORMALIZE_JAC_ALT + #define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +#endif + +/** + * \def MBEDTLS_ECDH_COMPUTE_SHARED_ALT + * \def MBEDTLS_ECDH_GEN_PUBLIC_ALT + * \def MBEDTLS_ECDSA_GENKEY_ALT + * \def MBEDTLS_ECDSA_SIGN_ALT + * \def MBEDTLS_ECDSA_VERIFY_ALT + * + * Enable hardware acceleration for certain ECC operations. + * + * Module: sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c for all devices, plus: + * - sl_psa_driver/src/sli_se_driver_signature.c and sl_psa_driver/src/sli_se_driver_key_management.c for devices with HSE, + * - sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c and sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c for devices with CRYPTOACC + * + * Requires: \ref MBEDTLS_ECP_C (CRYPTOACC_PRESENT or SEMAILBOX_PRESENT) + * + * See \ref MBEDTLS_ECP_C for more information. + */ +#if defined(CRYPTOACC_PRESENT) +#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) + #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT + #define MBEDTLS_ECDH_GEN_PUBLIC_ALT +#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... + +#if !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) ) + #define MBEDTLS_ECDSA_GENKEY_ALT + #define MBEDTLS_ECDSA_VERIFY_ALT + #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) + #define MBEDTLS_ECDSA_SIGN_ALT + #endif +#endif // #if !( defined(MBEDTLS_ECP_DP_XXX_ENABLED) ... + +#endif /* CRYPTOACC */ + +#if defined(SEMAILBOX_PRESENT) + +#if !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + && !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Do not enable the ECDH and/or ECDSA ALT implementations when one or more + * non-accelerated curves are included, then the application needs to + * use the standard mbedTLS library. */ + + #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ + && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) + #if defined(SE_COMMAND_CREATE_KEY) + #define MBEDTLS_ECDH_GEN_PUBLIC_ALT + #endif + #if defined(SE_COMMAND_DH) + #define MBEDTLS_ECDH_COMPUTE_SHARED_ALT + #endif + #endif + + #if !( (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) \ + && (defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) ) ) + #if defined(SE_COMMAND_CREATE_KEY) + #define MBEDTLS_ECDSA_GENKEY_ALT + #endif + #if defined(SE_COMMAND_SIGNATURE_SIGN) + #if !defined(MBEDTLS_ECDSA_DETERMINISTIC) + #define MBEDTLS_ECDSA_SIGN_ALT + #endif + #endif + #if defined(SE_COMMAND_SIGNATURE_VERIFY) + #define MBEDTLS_ECDSA_VERIFY_ALT + #endif + #endif + +#endif // #if !defined(MBEDTLS_ECP_DP_XXXX_ENABLED) && ... + +#if defined(SE_COMMAND_JPAKE_GEN_SESSIONKEY) +/** + * \def MBEDTLS_ECJPAKE_ALT + * + * Enable hardware acceleration JPAKE. + * + * Module: sl_mbedtls_support/src/se_jpake.c + * + * Requires: \ref MBEDTLS_ECJPAKE_C (SEMAILBOX_PRESENT) + * + * See \ref MBEDTLS_ECJPAKE_C for more information. + */ +#define MBEDTLS_ECJPAKE_ALT +#endif + +#endif /* SEMAILBOX_PRESENT */ + +/** + * \def MBEDTLS_ENTROPY_ADC_PRESENT + * + * Decode if device supports retrieving entropy data from the ADC + * incorporated on devices from Silicon Labs. + * + * Requires ADC_PRESENT && _ADC_SINGLECTRLX_VREFSEL_VENTROPY && + * _SILICON_LABS_32B_SERIES_1 + */ +#if defined(ADC_PRESENT) \ + && defined(_ADC_SINGLECTRLX_VREFSEL_VENTROPY) \ + && defined(_SILICON_LABS_32B_SERIES_1) +#define MBEDTLS_ENTROPY_ADC_PRESENT +#endif + +/** + * \def MBEDTLS_TRNG_PRESENT + * + * Determine whether mbedTLS supports the TRNG (if present) on the device. + * + * Requires TRNG_PRESENT and not _SILICON_LABS_GECKO_INTERNAL_SDID_95 (xg14) + */ +#if defined(TRNG_PRESENT) \ + && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) +#undef MBEDTLS_TRNG_PRESENT +#define MBEDTLS_TRNG_PRESENT +#endif + +/** + * \def MBEDTLS_ENTROPY_RAIL_PRESENT + * + * Determine whether mbedTLS supports RAIL entropy on the device. + * This is currently only available on a few series-1 devices + * where there is no functional TRNG. + * + * Requires _EFR_DEVICE and one of + * _SILICON_LABS_GECKO_INTERNAL_SDID_80 + * _SILICON_LABS_GECKO_INTERNAL_SDID_89 + * _SILICON_LABS_GECKO_INTERNAL_SDID_95 + */ +#if defined(_EFR_DEVICE) \ + && (defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) \ + || defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) ) +#if defined(SL_CATALOG_RAIL_LIB_PRESENT) +#undef MBEDTLS_ENTROPY_RAIL_PRESENT +#define MBEDTLS_ENTROPY_RAIL_PRESENT +#endif +#endif + +/* Default ECC configuration for Silicon Labs devices: */ + +/* Save RAM by adjusting to our exact needs */ +#ifndef MBEDTLS_MPI_MAX_SIZE +#define MBEDTLS_MPI_MAX_SIZE 32 // 384 bits is 48 bytes +#endif + +/* + Set MBEDTLS_ECP_WINDOW_SIZE to configure + ECC point multiplication window size, see ecp.h: + 2 = Save RAM at the expense of speed + 3 = Improve speed at the expense of RAM + 4 = Optimize speed at the expense of RAM + */ +#define MBEDTLS_ECP_WINDOW_SIZE 2 +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 0 + +#if defined(MBEDTLS_ECP_C) +/* First section: devices with ECP hardware acceleration enabled */ +#if defined(MBEDTLS_ECP_INTERNAL_ALT) +/* When the internal ECP implementation is overridden, apply optimisation + * only when it benefits us for curves we can't accelerate. */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Non-accelerated SECP R1 curves requested */ +/* If only accelerated curves are requested, and no non-accelerated ones, + * we can turn on the NO_FALLBACK flag to dead-strip a whole lot of ECC + * math software implementation. */ +#if (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) ) \ + && !(defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) \ + || defined(MBEDTLS_ECP_DP_CURVE448_ENABLED)) +#define MBEDTLS_ECP_NO_FALLBACK +#endif /* Only ECP-hardware-accelerated curves requested */ +/* Second section: devices with ECDSA / ECDH hardware acceleration (without ECP) */ +#elif defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + || defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + || defined(MBEDTLS_ECDSA_SIGN_ALT) \ + || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ +/* When the upper layers calling into ECP_C are overridden, apply optimisation + * only when it benefits us for curves we can't accelerate. */ +#if (defined(SEMAILBOX_PRESENT) && (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_SE) ) \ + || defined(CRYPTOACC_PRESENT) +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) \ + || (defined(MBEDTLS_ECDSA_DETERMINISTIC) \ + && (defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED))) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Non-accelerated SECP R1 curves requested */ +#endif /* Devices not implementing the full suite of SECP R1 curves */ +/* Third section: configurations without any ECP/ECC acceleration at all */ +#else +/* When there's no ECC acceleration at all, apply optimisation always when + * applicable curves are present. */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) \ + || defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_NIST_OPTIM +#endif /* Software-optimisable curve requested */ +#endif /* Different acceleration constellations */ +#endif /* MBEDTLS_ECP_C */ + +/* + Set max CTR-DRBG seed input size to reasonable default in order to reduce + stack usage when using CTR-DRBG. + NOTE: + Due to existing dependencies we need to keep the setting of + MBEDTLS_CTR_DRBG_MAX_SEED_INPUT here. However this is subject to be moved + later, to sl_mbedtls_config.h or mbedtls_config_autogen.h in order to be more + practical for configuration. + */ +#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) +#if !(defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + && defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + && defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + && defined(MBEDTLS_ECDSA_SIGN_ALT) \ + && defined(MBEDTLS_ECDSA_VERIFY_ALT)) +/* + If any of ECDH and/or ECDSA ALT is/are not enabled, then the ecp_mul_xxx() + functions will seed the internal drbg (for randomization of projective + coordinates) with the private key of size corresponding to the curve + hence we will need to adjust: + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +// For key size 521 bits (=66 bytes) add 66 - 32 (256bits default) = 34 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 66 - 32) +#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +// For key size 512 bits (=64 bytes) add 64 - 32 (256bits default) = 32 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 64 - 32) +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +// For key size 448 bits (=56 bytes) add 56 - 32 (256bits default) = 24 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 56 - 32) +#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) +#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +// For key size 384 bits (=48 bytes) add 48 - 32 (256bits default) = 16 bytes +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 + 48 - 32) +#else +// Default value to support curve sizes up to 256 bits ( 32 bytes ) +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT (MBEDTLS_CTR_DRBG_ENTROPY_LEN + MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2) +#endif +#endif +#endif + +#endif // !NO_CRYPTO_ACCELERATION + +#endif // SLI_MBEDTLS_ACCELERATION_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h index 0f3cd44..196baa3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_mbedtls_omnipresent.h @@ -1,141 +1,141 @@ -/***************************************************************************//** - * @file - * @brief Mbed TLS 'omnipresent' config content. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_MBEDTLS_OMIPRESENT_H -#define SLI_MBEDTLS_OMIPRESENT_H - -#if defined(SL_COMPONENT_CATALOG_PRESENT) - #include "sl_component_catalog.h" -#endif - -#if !defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) - #include "em_device.h" -#endif - -// ----------------------------------------------------------------------------- -// Non-volatile seed function headers - -#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) - -// Provide the NV seed function signatures since we have no specific header -// for them. - -#include - -int sli_nv_seed_read(unsigned char *buf, size_t buf_len); -int sli_nv_seed_write(unsigned char *buf, size_t buf_len); - -#endif // MBEDTLS_PLATFORM_NV_SEED_ALT - -// ----------------------------------------------------------------------------- -// Platform macros - -#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && defined(MBEDTLS_PLATFORM_FREE_MACRO) - -// By default MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO are -// defined in mbedtls_platform_dynamic_memory_allocation_config_default.slcc. -// Alternative implementations can configure MBEDTLS_PLATFORM_CALLOC_MACRO and -// MBEDTLS_PLATFORM_FREE_MACRO to use other platform specific implementations. -// Alternatively some use cases may select runtime initialisation in the -// application by explicitly calling mbedtls_platform_set_calloc_free() by -// selecting mbedtls_platform_dynamic_memory_allocation_config_init_runtime. - -#include - -extern void *MBEDTLS_PLATFORM_CALLOC_MACRO(size_t n, size_t size); -extern void MBEDTLS_PLATFORM_FREE_MACRO(void *ptr); - -#endif // MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO - -// ----------------------------------------------------------------------------- -// Device differentiation logic - -#if defined(CRYPTO_PRESENT) - - #define SLI_MBEDTLS_DEVICE_S1 - - #if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) - #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG - #endif - - #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) -// The TRNG may possibly not work depending on the die revision. - #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA - #endif - -#elif defined(SEMAILBOX_PRESENT) - - #define SLI_MBEDTLS_DEVICE_S2 - #define SLI_MBEDTLS_DEVICE_HSE - - #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - #define SLI_MBEDTLS_DEVICE_SE_V1 - #define SLI_MBEDTLS_DEVICE_HSE_V1 - #else - #define SLI_MBEDTLS_DEVICE_SE_V2 - #define SLI_MBEDTLS_DEVICE_HSE_V2 - #endif - - #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) - #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH - #else - #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID - #endif - -#elif defined(CRYPTOACC_PRESENT) - - #define SLI_MBEDTLS_DEVICE_S2 - #define SLI_MBEDTLS_DEVICE_VSE - - #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) - #define SLI_MBEDTLS_DEVICE_SE_V1 - #define SLI_MBEDTLS_DEVICE_VSE_V1 - #else - #define SLI_MBEDTLS_DEVICE_SE_V2 - #define SLI_MBEDTLS_DEVICE_VSE_V2 - #endif - -#elif defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) - - #define SLI_MBEDTLS_DEVICE_S2 - #define SLI_MBEDTLS_DEVICE_HSE - -// #define SLI_MBEDTLS_DEVICE_SE_V1 -// #define SLI_MBEDTLS_DEVICE_SE_V2 -// #define SLI_MBEDTLS_DEVICE_HSE_V1 -// #define SLI_MBEDTLS_DEVICE_HSE_V2 -// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH -// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID - -#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) - #define SLI_MBEDTLS_DEVICE_SI91X -#endif - -#endif // SLI_MBEDTLS_OMIPRESENT_H +/***************************************************************************//** + * @file + * @brief Mbed TLS 'omnipresent' config content. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_MBEDTLS_OMIPRESENT_H +#define SLI_MBEDTLS_OMIPRESENT_H + +#if defined(SL_COMPONENT_CATALOG_PRESENT) + #include "sl_component_catalog.h" +#endif + +#if !defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) + #include "em_device.h" +#endif + +// ----------------------------------------------------------------------------- +// Non-volatile seed function headers + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) + +// Provide the NV seed function signatures since we have no specific header +// for them. + +#include + +int sli_nv_seed_read(unsigned char *buf, size_t buf_len); +int sli_nv_seed_write(unsigned char *buf, size_t buf_len); + +#endif // MBEDTLS_PLATFORM_NV_SEED_ALT + +// ----------------------------------------------------------------------------- +// Platform macros + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && defined(MBEDTLS_PLATFORM_FREE_MACRO) + +// By default MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO are +// defined in mbedtls_platform_dynamic_memory_allocation_config_default.slcc. +// Alternative implementations can configure MBEDTLS_PLATFORM_CALLOC_MACRO and +// MBEDTLS_PLATFORM_FREE_MACRO to use other platform specific implementations. +// Alternatively some use cases may select runtime initialisation in the +// application by explicitly calling mbedtls_platform_set_calloc_free() by +// selecting mbedtls_platform_dynamic_memory_allocation_config_init_runtime. + +#include + +extern void *MBEDTLS_PLATFORM_CALLOC_MACRO(size_t n, size_t size); +extern void MBEDTLS_PLATFORM_FREE_MACRO(void *ptr); + +#endif // MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO + +// ----------------------------------------------------------------------------- +// Device differentiation logic + +#if defined(CRYPTO_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S1 + + #if !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95) + #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG + #endif + + #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89) +// The TRNG may possibly not work depending on the die revision. + #define SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA + #endif + +#elif defined(SEMAILBOX_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_HSE + + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + #define SLI_MBEDTLS_DEVICE_SE_V1 + #define SLI_MBEDTLS_DEVICE_HSE_V1 + #else + #define SLI_MBEDTLS_DEVICE_SE_V2 + #define SLI_MBEDTLS_DEVICE_HSE_V2 + #endif + + #if (_SILICON_LABS_SECURITY_FEATURE == _SILICON_LABS_SECURITY_FEATURE_VAULT) + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH + #else + #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID + #endif + +#elif defined(CRYPTOACC_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_VSE + + #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) + #define SLI_MBEDTLS_DEVICE_SE_V1 + #define SLI_MBEDTLS_DEVICE_VSE_V1 + #else + #define SLI_MBEDTLS_DEVICE_SE_V2 + #define SLI_MBEDTLS_DEVICE_VSE_V2 + #endif + +#elif defined(SL_CATALOG_SE_CPC_PRIMARY_PRESENT) + + #define SLI_MBEDTLS_DEVICE_S2 + #define SLI_MBEDTLS_DEVICE_HSE + +// #define SLI_MBEDTLS_DEVICE_SE_V1 +// #define SLI_MBEDTLS_DEVICE_SE_V2 +// #define SLI_MBEDTLS_DEVICE_HSE_V1 +// #define SLI_MBEDTLS_DEVICE_HSE_V2 +// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH +// #define SLI_MBEDTLS_DEVICE_HSE_VAULT_MID + +#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) + #define SLI_MBEDTLS_DEVICE_SI91X +#endif + +#endif // SLI_MBEDTLS_OMIPRESENT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h index 0f3559b..6c372b5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/config/sli_psa_acceleration.h @@ -1,135 +1,135 @@ -/***************************************************************************//** - * @file - * @brief PSA Crypto device acceleration capabilities. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_PSA_ACCELERATION_H -#define SLI_PSA_ACCELERATION_H - -// ------------------------------------- -// Hash - -#define MBEDTLS_PSA_ACCEL_ALG_SHA_1 -#define MBEDTLS_PSA_ACCEL_ALG_SHA_224 -#define MBEDTLS_PSA_ACCEL_ALG_SHA_256 - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined (SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_SHA_384 - #define MBEDTLS_PSA_ACCEL_ALG_SHA_512 -#endif - -// ------------------------------------- -// Cipher - -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_AES -#define MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING -#define MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING -#define MBEDTLS_PSA_ACCEL_ALG_CTR - -#if !defined(SLI_MBEDTLS_DEVICE_SI91X) -#define MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7 -#define MBEDTLS_PSA_ACCEL_ALG_CFB -#define MBEDTLS_PSA_ACCEL_ALG_OFB -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20 -#endif - -// ------------------------------------- -// AEAD - -#define MBEDTLS_PSA_ACCEL_ALG_GCM -#define MBEDTLS_PSA_ACCEL_ALG_CCM - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305 -#endif - -// ------------------------------------- -// MAC - -#if !defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_CMAC -#endif - -#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_HMAC -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) - #define MBEDTLS_PSA_ACCEL_ALG_CBC_MAC -#endif - -// ------------------------------------- -// Elliptic curves - -#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR - #define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY - #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192 - #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256 -#endif - -#if (defined(SLI_MBEDTLS_DEVICE_S2) && !defined(SLI_MBEDTLS_DEVICE_HSE_V1)) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224 -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384 - #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521 -#endif - -#if defined(SLI_MBEDTLS_DEVICE_VSE) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256 -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ - || defined(SLI_MBEDTLS_DEVICE_HSE_V2) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448 -#endif - -// ------------------------------------- -// Key agreement - -#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define MBEDTLS_PSA_ACCEL_ALG_ECDH -#endif - -// ------------------------------------- -// Signature - -#if defined(SLI_MBEDTLS_DEVICE_S2) - #define MBEDTLS_PSA_ACCEL_ALG_ECDSA -#endif - -#endif // SLI_PSA_ACCELERATION_H +/***************************************************************************//** + * @file + * @brief PSA Crypto device acceleration capabilities. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_ACCELERATION_H +#define SLI_PSA_ACCELERATION_H + +// ------------------------------------- +// Hash + +#define MBEDTLS_PSA_ACCEL_ALG_SHA_1 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_224 +#define MBEDTLS_PSA_ACCEL_ALG_SHA_256 + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined (SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_SHA_384 + #define MBEDTLS_PSA_ACCEL_ALG_SHA_512 +#endif + +// ------------------------------------- +// Cipher + +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_AES +#define MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING +#define MBEDTLS_PSA_ACCEL_ALG_CTR + +#if !defined(SLI_MBEDTLS_DEVICE_SI91X) +#define MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7 +#define MBEDTLS_PSA_ACCEL_ALG_CFB +#define MBEDTLS_PSA_ACCEL_ALG_OFB +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20 +#endif + +// ------------------------------------- +// AEAD + +#define MBEDTLS_PSA_ACCEL_ALG_GCM +#define MBEDTLS_PSA_ACCEL_ALG_CCM + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305 +#endif + +// ------------------------------------- +// MAC + +#if !defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_CMAC +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_HMAC +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define MBEDTLS_PSA_ACCEL_ALG_CBC_MAC +#endif + +// ------------------------------------- +// Elliptic curves + +#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR + #define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192 + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256 +#endif + +#if (defined(SLI_MBEDTLS_DEVICE_S2) && !defined(SLI_MBEDTLS_DEVICE_HSE_V1)) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384 + #define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_VSE) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_V1) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ + || defined(SLI_MBEDTLS_DEVICE_HSE_V2) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255 +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448 +#endif + +// ------------------------------------- +// Key agreement + +#if defined(SLI_MBEDTLS_DEVICE_S2) || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define MBEDTLS_PSA_ACCEL_ALG_ECDH +#endif + +// ------------------------------------- +// Signature + +#if defined(SLI_MBEDTLS_DEVICE_S2) + #define MBEDTLS_PSA_ACCEL_ALG_ECDSA +#endif + +#endif // SLI_PSA_ACCELERATION_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h index 61cba7e..f1dbd88 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/aes_alt.h @@ -1,81 +1,81 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS AES block cipher - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef AES_ALT_H -#define AES_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_aes Accelerated AES Block Cipher - * \brief Accelerated AES block cipher for the mbed TLS API using the AES, CRYPTO, - * CRYPTOACC or SE peripheral - * - * \{ - ******************************************************************************/ - -#if defined(MBEDTLS_AES_ALT) -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief AES context structure - */ -typedef struct { - unsigned int keybits; /*!< size of key */ - unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ -} -mbedtls_aes_context; - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -/** - * \brief The AES XTS context-type definition. - */ -typedef struct mbedtls_aes_xts_context{ - mbedtls_aes_context crypt; /*!< The AES context to use for AES block - encryption or decryption. */ - mbedtls_aes_context tweak; /*!< The AES context used for tweak - computation. */ -} mbedtls_aes_xts_context; -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_AES_ALT */ - -/** \} (end addtogroup sl_crypto_aes) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* AES_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS AES block cipher + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef AES_ALT_H +#define AES_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_aes Accelerated AES Block Cipher + * \brief Accelerated AES block cipher for the mbed TLS API using the AES, CRYPTO, + * CRYPTOACC or SE peripheral + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_AES_ALT) +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief AES context structure + */ +typedef struct { + unsigned int keybits; /*!< size of key */ + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ +} +mbedtls_aes_context; + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief The AES XTS context-type definition. + */ +typedef struct mbedtls_aes_xts_context{ + mbedtls_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + mbedtls_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} mbedtls_aes_xts_context; +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_AES_ALT */ + +/** \} (end addtogroup sl_crypto_aes) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* AES_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h index 4cc6a00..cad6e1c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/ccm_alt.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS AES-CCM AEAD cipher - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef CCM_ALT_H -#define CCM_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_ccm Accelerated AES-CCM AEAD Cipher - * \brief Accelerated AES-CCM AEAD cipher for the mbed TLS API using the CRYPTOACC - * or SE peripheral - * - * \{ - ******************************************************************************/ -#if defined(MBEDTLS_CCM_ALT) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief The CCM context-type definition. The CCM context is passed - * to the APIs called. - */ -typedef struct { - unsigned char key[32]; /*!< The key in use. */ - unsigned int keybits; -} -mbedtls_ccm_context; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CCM_ALT */ - -/** \} (end addtogroup sl_crypto_ccm) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* CCM_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS AES-CCM AEAD cipher + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef CCM_ALT_H +#define CCM_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_ccm Accelerated AES-CCM AEAD Cipher + * \brief Accelerated AES-CCM AEAD cipher for the mbed TLS API using the CRYPTOACC + * or SE peripheral + * + * \{ + ******************************************************************************/ +#if defined(MBEDTLS_CCM_ALT) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief The CCM context-type definition. The CCM context is passed + * to the APIs called. + */ +typedef struct { + unsigned char key[32]; /*!< The key in use. */ + unsigned int keybits; +} +mbedtls_ccm_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CCM_ALT */ + +/** \} (end addtogroup sl_crypto_ccm) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* CCM_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h index c105317..764e3f8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/cmac_alt.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS AES-CMAC cipher - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef CMAC_ALT_H -#define CMAC_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_cmac Accelerated AES-CMAC Cipher - * \brief Accelerated AES-CMAC cipher for the mbed TLS API using the CRYPTOACC or - * SE peripheral. This implementation builds on the PSA Crypto drivers - * (\ref sl_psa_drivers). - * - * \{ - ******************************************************************************/ -#if defined(MBEDTLS_CMAC_ALT) - -#ifdef __cplusplus -extern "C" { -#endif - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_types.h" -#define SL_MAC_OPERATION_CTX_TYPE sli_se_transparent_mac_operation_t -#elif defined(CRYPTO_PRESENT) -#include "sli_crypto_transparent_types.h" -#define SL_MAC_OPERATION_CTX_TYPE sli_crypto_transparent_mac_operation_t -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_types.h" -#define SL_MAC_OPERATION_CTX_TYPE sli_cryptoacc_transparent_mac_operation_t -#endif - -struct mbedtls_cmac_context_t { - SL_MAC_OPERATION_CTX_TYPE ctx; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CMAC_ALT */ - -/** \} (end addtogroup sl_crypto_cmac) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* CMAC_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS AES-CMAC cipher + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef CMAC_ALT_H +#define CMAC_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_cmac Accelerated AES-CMAC Cipher + * \brief Accelerated AES-CMAC cipher for the mbed TLS API using the CRYPTOACC or + * SE peripheral. This implementation builds on the PSA Crypto drivers + * (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ +#if defined(MBEDTLS_CMAC_ALT) + +#ifdef __cplusplus +extern "C" { +#endif + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_MAC_OPERATION_CTX_TYPE sli_se_transparent_mac_operation_t +#elif defined(CRYPTO_PRESENT) +#include "sli_crypto_transparent_types.h" +#define SL_MAC_OPERATION_CTX_TYPE sli_crypto_transparent_mac_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_MAC_OPERATION_CTX_TYPE sli_cryptoacc_transparent_mac_operation_t +#endif + +struct mbedtls_cmac_context_t { + SL_MAC_OPERATION_CTX_TYPE ctx; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CMAC_ALT */ + +/** \} (end addtogroup sl_crypto_cmac) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* CMAC_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h index dd291d3..f925549 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/gcm_alt.h @@ -1,121 +1,121 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS Galois/Counter Mode (GCM) for AES-128-bit block ciphers - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef GCM_ALT_H -#define GCM_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_gcm Accelerated GCM AES-128 Cipher - * \brief Accelerated AES-GCM-128 cipher for the mbed TLS API using the CRYPTOACC - * or SE peripheral - * - * \{ - * This module implements the GCM AES-128 cipher, as defined in - * D. McGrew, J. Viega, The Galois/Counter Mode of Operation - * (GCM), Natl. Inst. Stand. Technol. - * For more information on GCM, see NIST SP 800-38D: Recommendation for - * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. - * - ******************************************************************************/ - -#if defined(MBEDTLS_GCM_ALT) -/* SiliconLabs CRYPTO hardware acceleration implementation */ - -#include "em_device.h" - -#if defined(CRYPTO_PRESENT) -#include "em_crypto.h" -#elif defined(SEMAILBOX_PRESENT) -#include "em_se.h" -#elif defined(CRYPTOACC_PRESENT) -#include "sx_aes.h" -#include "sl_enum.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(CRYPTOACC_PRESENT) -SL_ENUM(sli_gcm_mode_t) { - SLI_GCM_ENC = 1, - SLI_GCM_DEC = 2, -}; -#endif - -/** - * \brief The GCM context structure. - */ -typedef struct { - unsigned int keybits; /*!< Size of key */ - uint64_t len; /*!< Total length of encrypted data. */ - uint64_t add_len; /*!< Total length of additional data. */ - -#if defined(CRYPTO_PRESENT) - - CRYPTO_DData_TypeDef key; /*!< AES key, 128 or 256 bits */ - int mode; /*!< Encryption or decryption */ - CRYPTO_TypeDef* device; /*!< CRYPTO device to use */ - CRYPTO_Data_TypeDef ghash_state; /*!< GHASH state */ - CRYPTO_Data_TypeDef gctr_state; /*!< GCTR counter value */ - CRYPTO_Data_TypeDef ghash_key; /*!< GHASH key (is a constant value - which is faster to restore than - to reconstruct each time). */ -#elif defined(SEMAILBOX_PRESENT) - unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ - int mode; /*!< Encryption or decryption */ - size_t iv_len; /*!< IV length */ - bool last_op; /*!< Last streaming block identified */ - uint8_t tagbuf[16]; /*!< Buffer for storing tag */ - uint8_t se_ctx_enc[32]; /*!< SE GCM encryption state */ - uint8_t se_ctx_dec[32]; /*!< SE GCM decryption state */ - -#elif defined(CRYPTOACC_PRESENT) - unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ - sli_gcm_mode_t dir; /*!< Encryption or decryption */ - uint8_t sx_ctx[AES_CTX_xCM_SIZE]; /*!< CRYPTOACC GCM state */ -#endif -} -mbedtls_gcm_context; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_GCM_ALT */ - -/** \} (end addtogroup sl_crypto_gcm) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* GCM_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS Galois/Counter Mode (GCM) for AES-128-bit block ciphers + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef GCM_ALT_H +#define GCM_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_gcm Accelerated GCM AES-128 Cipher + * \brief Accelerated AES-GCM-128 cipher for the mbed TLS API using the CRYPTOACC + * or SE peripheral + * + * \{ + * This module implements the GCM AES-128 cipher, as defined in + * D. McGrew, J. Viega, The Galois/Counter Mode of Operation + * (GCM), Natl. Inst. Stand. Technol. + * For more information on GCM, see NIST SP 800-38D: Recommendation for + * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. + * + ******************************************************************************/ + +#if defined(MBEDTLS_GCM_ALT) +/* SiliconLabs CRYPTO hardware acceleration implementation */ + +#include "em_device.h" + +#if defined(CRYPTO_PRESENT) +#include "em_crypto.h" +#elif defined(SEMAILBOX_PRESENT) +#include "em_se.h" +#elif defined(CRYPTOACC_PRESENT) +#include "sx_aes.h" +#include "sl_enum.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(CRYPTOACC_PRESENT) +SL_ENUM(sli_gcm_mode_t) { + SLI_GCM_ENC = 1, + SLI_GCM_DEC = 2, +}; +#endif + +/** + * \brief The GCM context structure. + */ +typedef struct { + unsigned int keybits; /*!< Size of key */ + uint64_t len; /*!< Total length of encrypted data. */ + uint64_t add_len; /*!< Total length of additional data. */ + +#if defined(CRYPTO_PRESENT) + + CRYPTO_DData_TypeDef key; /*!< AES key, 128 or 256 bits */ + int mode; /*!< Encryption or decryption */ + CRYPTO_TypeDef* device; /*!< CRYPTO device to use */ + CRYPTO_Data_TypeDef ghash_state; /*!< GHASH state */ + CRYPTO_Data_TypeDef gctr_state; /*!< GCTR counter value */ + CRYPTO_Data_TypeDef ghash_key; /*!< GHASH key (is a constant value + which is faster to restore than + to reconstruct each time). */ +#elif defined(SEMAILBOX_PRESENT) + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ + int mode; /*!< Encryption or decryption */ + size_t iv_len; /*!< IV length */ + bool last_op; /*!< Last streaming block identified */ + uint8_t tagbuf[16]; /*!< Buffer for storing tag */ + uint8_t se_ctx_enc[32]; /*!< SE GCM encryption state */ + uint8_t se_ctx_dec[32]; /*!< SE GCM decryption state */ + +#elif defined(CRYPTOACC_PRESENT) + unsigned char key[32]; /*!< AES key 128, 192 or 256 bits */ + sli_gcm_mode_t dir; /*!< Encryption or decryption */ + uint8_t sx_ctx[AES_CTX_xCM_SIZE]; /*!< CRYPTOACC GCM state */ +#endif +} +mbedtls_gcm_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_GCM_ALT */ + +/** \} (end addtogroup sl_crypto_gcm) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* GCM_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h index fbb9208..3e76ae6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha1_alt.h @@ -1,82 +1,82 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS SHA-1 cryptographic hash function - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SHA1_ALT_H -#define SHA1_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_sha1 Accelerated SHA-1 Hash Function - * \brief Accelerated mbed TLS SHA-1 cryptographic hash function for the mbed - * TLS API using Silicon Labs peripherals. This implementation builds on - * the PSA Crypto drivers (\ref sl_psa_drivers). - * - * \{ - ******************************************************************************/ - -#if defined(MBEDTLS_SHA1_ALT) - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t -#elif defined(CRYPTO_PRESENT) -#include "sli_crypto_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_crypto_transparent_hash_operation_t -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t -#endif - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SHA-1 context structure - */ -typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha1_context; - -#ifdef __cplusplus -} -#endif - -#endif /* #if defined(MBEDTLS_SHA1_ALT) */ - -/** \} (end addtogroup sl_crypto_sha1) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* SHA1_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-1 cryptographic hash function + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA1_ALT_H +#define SHA1_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_sha1 Accelerated SHA-1 Hash Function + * \brief Accelerated mbed TLS SHA-1 cryptographic hash function for the mbed + * TLS API using Silicon Labs peripherals. This implementation builds on + * the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA1_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#elif defined(CRYPTO_PRESENT) +#include "sli_crypto_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_crypto_transparent_hash_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t +#endif + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-1 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha1_context; + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA1_ALT) */ + +/** \} (end addtogroup sl_crypto_sha1) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* SHA1_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h index 9c2b8c3..4f8ce19 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha256_alt.h @@ -1,84 +1,84 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS SHA-224 and SHA-256 cryptographic hash functions - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SHA256_ALT_H -#define SHA256_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_sha256 Accelerated SHA-224/SHA-256 Hash Function - * \brief Accelerated mbed TLS SHA-224/SHA-256 cryptographic hash functions for - * the mbed TLS API using Silicon Labs peripherals. This implementation - * builds on the PSA Crypto drivers (\ref sl_psa_drivers). - * - * \{ - ******************************************************************************/ - -#if defined(MBEDTLS_SHA256_ALT) - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t -#elif defined(CRYPTO_PRESENT) -#include "sli_crypto_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_crypto_transparent_hash_operation_t -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t -#endif - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SHA-256 context structure - */ -typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha256_context; - -#ifdef __cplusplus -} -#endif - -#endif /* #if defined(MBEDTLS_SHA256_ALT) */ - -/** \} (end addtogroup sl_crypto_sha256) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* SHA256_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-224 and SHA-256 cryptographic hash functions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA256_ALT_H +#define SHA256_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_sha256 Accelerated SHA-224/SHA-256 Hash Function + * \brief Accelerated mbed TLS SHA-224/SHA-256 cryptographic hash functions for + * the mbed TLS API using Silicon Labs peripherals. This implementation + * builds on the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA256_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#elif defined(CRYPTO_PRESENT) +#include "sli_crypto_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_crypto_transparent_hash_operation_t +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_cryptoacc_transparent_hash_operation_t +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-256 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha256_context; + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA256_ALT) */ + +/** \} (end addtogroup sl_crypto_sha256) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* SHA256_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h index 3e6ef74..94ff600 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sha512_alt.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Accelerated mbed TLS SHA-384 and SHA-512 cryptographic hash functions - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SHA512_ALT_H -#define SHA512_ALT_H - -/***************************************************************************//** - * \addtogroup sl_crypto - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_crypto_sha512 Accelerated SHA-384/SHA-512 Hash Function - * \brief Accelerated mbed TLS SHA-384/SHA-512 cryptographic hash function for - * the mbed TLS API using Silicon Labs peripherals. This implementation - * builds on the PSA Crypto drivers (\ref sl_psa_drivers). - * - * \{ - ******************************************************************************/ - -#if defined(MBEDTLS_SHA512_ALT) - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_types.h" -#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t -#endif - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SHA-512 context structure - */ -typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha512_context; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_SHA512_ALT */ - -/** \} (end addtogroup sl_crypto_sha512) */ -/** \} (end addtogroup sl_crypto) */ - -#endif /* SHA512_ALT_H */ +/***************************************************************************//** + * @file + * @brief Accelerated mbed TLS SHA-384 and SHA-512 cryptographic hash functions + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SHA512_ALT_H +#define SHA512_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_sha512 Accelerated SHA-384/SHA-512 Hash Function + * \brief Accelerated mbed TLS SHA-384/SHA-512 cryptographic hash function for + * the mbed TLS API using Silicon Labs peripherals. This implementation + * builds on the PSA Crypto drivers (\ref sl_psa_drivers). + * + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA512_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_types.h" +#define SL_HASH_OPERATION_CTX_TYPE sli_se_transparent_hash_operation_t +#endif + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-512 context structure + */ +typedef SL_HASH_OPERATION_CTX_TYPE mbedtls_sha512_context; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SHA512_ALT */ + +/** \} (end addtogroup sl_crypto_sha512) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* SHA512_ALT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h index c543324..76aed7a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_mbedtls.h @@ -1,42 +1,42 @@ -/***************************************************************************//** - * @file - * @brief Silicon Laboratories platform integration for mbedTLS - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_MBEDTLS_H -#define SL_MBEDTLS_H - -/** - * Initialize the Silicon Labs platform integration of mbedTLS. - * - * This function must be called by an application before using any mbedTLS - * functions. This function will make sure that the platform hooks in mbedTLS - * are configured to ensure correct runtime behavior. - */ -void sl_mbedtls_init(void); - -#endif // SL_MBEDTLS_H +/***************************************************************************//** + * @file + * @brief Silicon Laboratories platform integration for mbedTLS + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_MBEDTLS_H +#define SL_MBEDTLS_H + +/** + * Initialize the Silicon Labs platform integration of mbedTLS. + * + * This function must be called by an application before using any mbedTLS + * functions. This function will make sure that the platform hooks in mbedTLS + * are configured to ensure correct runtime behavior. + */ +void sl_mbedtls_init(void); + +#endif // SL_MBEDTLS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h index badf1c9..452a71d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_crypto.h @@ -1,120 +1,120 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto utility functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_PSA_CRYPTO_H -#define SL_PSA_CRYPTO_H - -#include "psa/crypto.h" - -#include "sl_psa_values.h" - -#include - -// ----------------------------------------------------------------------------- -// Functions - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * \addtogroup psa_builtin_keys - * - * \brief Built-in key mechanism provides access to the keys stored in hardware. - * It can be accessed using key ID that is in the range - * [MBEDTLS_PSA_KEY_ID_BUILTIN_MIN, MBEDLTS_PSA_KEY_ID_BUILTIN_MAX]. - * - * - * \note Available builtin key IDs vary for different family of devices. - * For devices vith VSE see \ref sl_psa_drivers_cryptoacc_builtin_keys , - * and for devices with Secure Engine see \ref sl_psa_drivers_se_builtin_keys . - * \{ - ******************************************************************************/ -/** \} (end addtogroup psa_builtin_keys) */ - -/***************************************************************************//** - * \addtogroup key_derivation - * - * If single-shot key derivation is used (sl_psa_key_derivation_single_shot), - * following limitations have to be considered: - * -# PBKDF2-CMAC is not suported on xG21 - * -# PBKDF2-CMAC is only KDF supported for xG27 - * - * \{ - ******************************************************************************/ -/** \} (end addtogroup key_derivation) */ - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Set the location attribute of a key in PSA Crypto according to a given - * persistence level, and a preferred location. If the preferred location is - * not available, perhaps because the device does not support this location, - * the primary local storage (PSA_KEY_LOCATION_LOCAL_STORAGE) will be used. - * - * @param[out] attributes - * The attribute structure to write to. - * - * @param[in] persistence - * The persistence level of the key. If this is #PSA_KEY_PERSISTENCE_VOLATILE, - * the key will be volatile, and the key identifier attribute is reset to 0. - * - * @param[in] preferred_location - * The location of the key. Can be SL_PSA_KEY_LOCATION_WRAPPED, - * SL_PSA_KEY_LOCATION_BUILTIN, or PSA_KEY_LOCATION_LOCAL_STORAGE. - ******************************************************************************/ -void sl_psa_set_key_lifetime_with_location_preference( - psa_key_attributes_t *attributes, - psa_key_persistence_t persistence, - psa_key_location_t preferred_location); - -/***************************************************************************//** - * @brief - * Get the 'most secure' location attribute of a key usable in this - * implementation of PSA Crypto. - * - * @return - * The 'most secure' usable location of a key. In order of preference, the - * following values can be returned: SL_PSA_KEY_LOCATION_WRAPPED, - * or PSA_KEY_LOCATION_LOCAL_STORAGE. - ******************************************************************************/ -psa_key_location_t sl_psa_get_most_secure_key_location(void); - -/** \} (end addtogroup sl_psa_drivers) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_PSA_CRYPTO_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PSA_CRYPTO_H +#define SL_PSA_CRYPTO_H + +#include "psa/crypto.h" + +#include "sl_psa_values.h" + +#include + +// ----------------------------------------------------------------------------- +// Functions + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * \addtogroup psa_builtin_keys + * + * \brief Built-in key mechanism provides access to the keys stored in hardware. + * It can be accessed using key ID that is in the range + * [MBEDTLS_PSA_KEY_ID_BUILTIN_MIN, MBEDLTS_PSA_KEY_ID_BUILTIN_MAX]. + * + * + * \note Available builtin key IDs vary for different family of devices. + * For devices vith VSE see \ref sl_psa_drivers_cryptoacc_builtin_keys , + * and for devices with Secure Engine see \ref sl_psa_drivers_se_builtin_keys . + * \{ + ******************************************************************************/ +/** \} (end addtogroup psa_builtin_keys) */ + +/***************************************************************************//** + * \addtogroup key_derivation + * + * If single-shot key derivation is used (sl_psa_key_derivation_single_shot), + * following limitations have to be considered: + * -# PBKDF2-CMAC is not suported on xG21 + * -# PBKDF2-CMAC is only KDF supported for xG27 + * + * \{ + ******************************************************************************/ +/** \} (end addtogroup key_derivation) */ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * @brief + * Set the location attribute of a key in PSA Crypto according to a given + * persistence level, and a preferred location. If the preferred location is + * not available, perhaps because the device does not support this location, + * the primary local storage (PSA_KEY_LOCATION_LOCAL_STORAGE) will be used. + * + * @param[out] attributes + * The attribute structure to write to. + * + * @param[in] persistence + * The persistence level of the key. If this is #PSA_KEY_PERSISTENCE_VOLATILE, + * the key will be volatile, and the key identifier attribute is reset to 0. + * + * @param[in] preferred_location + * The location of the key. Can be SL_PSA_KEY_LOCATION_WRAPPED, + * SL_PSA_KEY_LOCATION_BUILTIN, or PSA_KEY_LOCATION_LOCAL_STORAGE. + ******************************************************************************/ +void sl_psa_set_key_lifetime_with_location_preference( + psa_key_attributes_t *attributes, + psa_key_persistence_t persistence, + psa_key_location_t preferred_location); + +/***************************************************************************//** + * @brief + * Get the 'most secure' location attribute of a key usable in this + * implementation of PSA Crypto. + * + * @return + * The 'most secure' usable location of a key. In order of preference, the + * following values can be returned: SL_PSA_KEY_LOCATION_WRAPPED, + * or PSA_KEY_LOCATION_LOCAL_STORAGE. + ******************************************************************************/ +psa_key_location_t sl_psa_get_most_secure_key_location(void); + +/** \} (end addtogroup sl_psa_drivers) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_PSA_CRYPTO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h index f38ffdc..cfd9318 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sl_psa_values.h @@ -1,196 +1,196 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Values. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_PSA_VALUES_H -#define SL_PSA_VALUES_H - -#include "sli_psa_driver_features.h" - -#if defined(SL_TRUSTZONE_NONSECURE) -// include path: trusted-firmware-m/interface/include - #include "psa/crypto.h" -#else -// include path: mbedtls/include - #include "psa/crypto_driver_common.h" -#endif - -//------------------------------------------------------------------------------ -// Device Agnostic Values - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/// Location value for keys to be stored encrypted with the device-unique secret. -/// Available on Vault-High devices. -#define SL_PSA_KEY_LOCATION_WRAPPED ((psa_key_location_t)0x000001UL) - -/// Location value for usage of built-in keys. -/// Available on Vault-Mid (and higher) devices with PUF-key support. -// Identical to SL_PSA_KEY_LOCATION_WRAPPED for implementation-related reasons. -#define SL_PSA_KEY_LOCATION_BUILTIN ((psa_key_location_t)0x000001UL) - -// #define SLE_PSA_KEY_LOCATION_SE_VOLATILE ((psa_key_location_t)0x800000UL) -// #define SLE_PSA_KEY_LOCATION_KSU ((psa_key_location_t)0x800001UL) - -/** \} (end addtogroup sl_psa_drivers) */ - -//------------------------------------------------------------------------------ -// Hardware Secure Engine - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_se Values for devices with a Hardware Secure Engine - * \{ - ******************************************************************************/ - -/// Location value for keys to be stored encrypted with the device-unique secret, -/// or for accessing the built-in keys on Vault-High devices. -#define PSA_KEY_LOCATION_SL_SE_OPAQUE (SL_PSA_KEY_LOCATION_WRAPPED) - -#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_se_builtin_keys Builtin keys on devices with Secure Engine - * \brief These key ID values belong to the builtin range of PSA, and allow access - * to the keys which respectively are and can be preprovisioned in Secure Engine - * devices. Refer to \ref psa_builtin_keys or AN1311 for more information on the - * usage of builtin keys through PSA Crypto. - * \{ - ******************************************************************************/ - -#if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) - #ifndef SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID -/// Vendor Key ID for the built-in application identity key on Vault High devices. - #define SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 5) - #endif - - #ifndef SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID -/// Vendor Key ID for the built-in SE identity key on Vault High devices. - #define SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 4) - #endif -#endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION - -#ifndef SL_SE_BUILTIN_KEY_SECUREBOOT_ID -/// Vendor Key ID for the Secure Boot verifying key provisioned to the Secure Engine. - #define SL_SE_BUILTIN_KEY_SECUREBOOT_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) -#endif - -#ifndef SL_SE_BUILTIN_KEY_SECUREDEBUG_ID -/// Vendor Key ID for the Secure Debug verifying key provisioned to the Secure Engine. - #define SL_SE_BUILTIN_KEY_SECUREDEBUG_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 2) -#endif - -#ifndef SL_SE_BUILTIN_KEY_AES128_ID -/// Vendor Key ID for AES-128 key provisioned to the Secure Engine. - #define SL_SE_BUILTIN_KEY_AES128_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 3) -#endif - -#ifndef SL_SE_BUILTIN_KEY_TRUSTZONE_ID -/// Vendor Key ID for the TrustZone root key. - #define SL_SE_BUILTIN_KEY_TRUSTZONE_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 6) -#endif - -#ifndef SL_SE_BUILTIN_KEY_AES128_ALG -/// Algorithm with which the #SL_SE_BUILTIN_KEY_AES128_ID key will be used. -// PSA Crypto only allows one specific usage algorithm per built-in key ID. - #define SL_SE_BUILTIN_KEY_AES128_ALG (SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG) -#endif - -/** \} (end addtogroup sl_psa_drivers_se_builtin_keys) */ - -#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE - -/** \} (end addtogroup sl_psa_drivers_se) */ -/** \} (end addtogroup sl_psa_drivers) */ - -#endif // SLI_MBEDTLS_DEVICE_HSE - -//------------------------------------------------------------------------------ -// Virtual Secure Engine - -#if defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_cryptoacc Values for devices with a Virtual Secure Engine - * \{ - ******************************************************************************/ - -/// Location value for built-in keys on VSE archtectures -#define PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE (SL_PSA_KEY_LOCATION_BUILTIN) - -#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_cryptoacc_builtin_keys Builtin keys on devices with a VSE - * \brief These key ID values belong to the builtin range of PSA, and allow access - * to the keys which respectively are and can be preprovisioned in (Virtual) - * Secure Engine devices. Refer to \ref psa_builtin_keys or AN1311 for more - * information on the usage of builtin keys through PSA Crypto. - * \{ - ******************************************************************************/ - -#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ID -/// Vendor Key ID for the PUF-derived hardware unique key. - #define SL_CRYPTOACC_BUILTIN_KEY_PUF_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) -#endif - -/// Internal ID for PUF-derived key. -#define SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT (SL_CRYPTOACC_BUILTIN_KEY_PUF_ID && 0xFF) - -/** \} (end addtogroup sl_psa_drivers_se_builtin_keys) */ - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/// Version of opaque header struct. -#define SLI_CRYPTOACC_OPAQUE_KEY_CONTEXT_VERSION (0x00) - -/// @endcond - -#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE - -/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ -/** \} (end addtogroup sl_psa_drivers) */ - -#endif // SLI_PSA_DRIVER_FEATURE_PUF_KEY - -#endif // SL_PSA_VALUES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Values. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_PSA_VALUES_H +#define SL_PSA_VALUES_H + +#include "sli_psa_driver_features.h" + +#if defined(SL_TRUSTZONE_NONSECURE) +// include path: trusted-firmware-m/interface/include + #include "psa/crypto.h" +#else +// include path: mbedtls/include + #include "psa/crypto_driver_common.h" +#endif + +//------------------------------------------------------------------------------ +// Device Agnostic Values + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/// Location value for keys to be stored encrypted with the device-unique secret. +/// Available on Vault-High devices. +#define SL_PSA_KEY_LOCATION_WRAPPED ((psa_key_location_t)0x000001UL) + +/// Location value for usage of built-in keys. +/// Available on Vault-Mid (and higher) devices with PUF-key support. +// Identical to SL_PSA_KEY_LOCATION_WRAPPED for implementation-related reasons. +#define SL_PSA_KEY_LOCATION_BUILTIN ((psa_key_location_t)0x000001UL) + +// #define SLE_PSA_KEY_LOCATION_SE_VOLATILE ((psa_key_location_t)0x800000UL) +// #define SLE_PSA_KEY_LOCATION_KSU ((psa_key_location_t)0x800001UL) + +/** \} (end addtogroup sl_psa_drivers) */ + +//------------------------------------------------------------------------------ +// Hardware Secure Engine + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se Values for devices with a Hardware Secure Engine + * \{ + ******************************************************************************/ + +/// Location value for keys to be stored encrypted with the device-unique secret, +/// or for accessing the built-in keys on Vault-High devices. +#define PSA_KEY_LOCATION_SL_SE_OPAQUE (SL_PSA_KEY_LOCATION_WRAPPED) + +#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_se_builtin_keys Builtin keys on devices with Secure Engine + * \brief These key ID values belong to the builtin range of PSA, and allow access + * to the keys which respectively are and can be preprovisioned in Secure Engine + * devices. Refer to \ref psa_builtin_keys or AN1311 for more information on the + * usage of builtin keys through PSA Crypto. + * \{ + ******************************************************************************/ + +#if defined(SLI_PSA_DRIVER_FEATURE_ATTESTATION) + #ifndef SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID +/// Vendor Key ID for the built-in application identity key on Vault High devices. + #define SL_SE_BUILTIN_KEY_APPLICATION_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 5) + #endif + + #ifndef SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID +/// Vendor Key ID for the built-in SE identity key on Vault High devices. + #define SL_SE_BUILTIN_KEY_SYSTEM_ATTESTATION_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 4) + #endif +#endif // SLI_PSA_DRIVER_FEATURE_ATTESTATION + +#ifndef SL_SE_BUILTIN_KEY_SECUREBOOT_ID +/// Vendor Key ID for the Secure Boot verifying key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_SECUREBOOT_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) +#endif + +#ifndef SL_SE_BUILTIN_KEY_SECUREDEBUG_ID +/// Vendor Key ID for the Secure Debug verifying key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_SECUREDEBUG_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 2) +#endif + +#ifndef SL_SE_BUILTIN_KEY_AES128_ID +/// Vendor Key ID for AES-128 key provisioned to the Secure Engine. + #define SL_SE_BUILTIN_KEY_AES128_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 3) +#endif + +#ifndef SL_SE_BUILTIN_KEY_TRUSTZONE_ID +/// Vendor Key ID for the TrustZone root key. + #define SL_SE_BUILTIN_KEY_TRUSTZONE_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 6) +#endif + +#ifndef SL_SE_BUILTIN_KEY_AES128_ALG +/// Algorithm with which the #SL_SE_BUILTIN_KEY_AES128_ID key will be used. +// PSA Crypto only allows one specific usage algorithm per built-in key ID. + #define SL_SE_BUILTIN_KEY_AES128_ALG (SL_SE_BUILTIN_KEY_AES128_ALG_CONFIG) +#endif + +/** \} (end addtogroup sl_psa_drivers_se_builtin_keys) */ + +#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE + +/** \} (end addtogroup sl_psa_drivers_se) */ +/** \} (end addtogroup sl_psa_drivers) */ + +#endif // SLI_MBEDTLS_DEVICE_HSE + +//------------------------------------------------------------------------------ +// Virtual Secure Engine + +#if defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc Values for devices with a Virtual Secure Engine + * \{ + ******************************************************************************/ + +/// Location value for built-in keys on VSE archtectures +#define PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE (SL_PSA_KEY_LOCATION_BUILTIN) + +#if defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) || defined(SL_TRUSTZONE_NONSECURE) + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc_builtin_keys Builtin keys on devices with a VSE + * \brief These key ID values belong to the builtin range of PSA, and allow access + * to the keys which respectively are and can be preprovisioned in (Virtual) + * Secure Engine devices. Refer to \ref psa_builtin_keys or AN1311 for more + * information on the usage of builtin keys through PSA Crypto. + * \{ + ******************************************************************************/ + +#ifndef SL_CRYPTOACC_BUILTIN_KEY_PUF_ID +/// Vendor Key ID for the PUF-derived hardware unique key. + #define SL_CRYPTOACC_BUILTIN_KEY_PUF_ID (MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + 1) +#endif + +/// Internal ID for PUF-derived key. +#define SLI_CRYPTOACC_BUILTIN_KEY_PUF_SLOT (SL_CRYPTOACC_BUILTIN_KEY_PUF_ID && 0xFF) + +/** \} (end addtogroup sl_psa_drivers_se_builtin_keys) */ + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/// Version of opaque header struct. +#define SLI_CRYPTOACC_OPAQUE_KEY_CONTEXT_VERSION (0x00) + +/// @endcond + +#endif // SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS || SL_TRUSTZONE_NONSECURE + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +#endif // SLI_PSA_DRIVER_FEATURE_PUF_KEY + +#endif // SL_PSA_VALUES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h index 0461d80..973029a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/inc/sli_psa_crypto.h @@ -1,155 +1,155 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs internal PSA Crypto utility functions. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_PSA_CRYPTO_H -#define SLI_PSA_CRYPTO_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include "psa/crypto.h" - -#include -#include - -// ----------------------------------------------------------------------------- -// Defines and Macros - -// Persistent key ID ranges. -#define SLI_PSA_KEY_ID_RANGE_THREAD_START (0x00020000) -#define SLI_PSA_KEY_ID_RANGE_THREAD_END (0x0002FFFF) -#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_START (0x00030000) -#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_END (0x0003FFFF) - -// Convert a type name into an enum entry name, since enum entries and type -// names share the same C namespace. -#define SLI_PSA_CONTEXT_ENUM_NAME(NAME) \ - NAME ## _e -#define SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME) \ - NAME ## _e - -// Convenience macros for getting the size of a context structure type -#define SLI_PSA_CONTEXT_GET_RUNTIME_SIZE(NAME) \ - (sli_psa_context_get_size(SLI_PSA_CONTEXT_ENUM_NAME(NAME))) -#define SLI_MBEDTLS_CONTEXT_GET_RUNTIME_SIZE(NAME) \ - (sli_mbedtls_context_get_size(SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME))) - -// ----------------------------------------------------------------------------- -// Type Definitions - -// Type names supported by sli_psa_context_get_size. -typedef enum { - SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t), - SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t) -} sli_psa_context_name_t; - -// Type names supported by sli_mbedtls_context_get_size. -typedef enum { - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx), - SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt) -} sli_mbedtls_context_name_t; - -// ----------------------------------------------------------------------------- -// Function Declarations - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @brief - * Get the size of a named PSA context structure. This is valuable for code - * shipping as precompiled libraries and needing to link with a source version - * of PSA Crypto, since the context structures can change in size based on - * configuration options which might not have been present at library - * compilation time. - * - * @param ctx_type - * Which context structure to get the size of. Use - * #SLI_PSA_CONTEXT_ENUM_NAME(psa_xxx_operation_t) as argument. - * - * @return - * Size (in bytes) of the context structure as expected by the current build. - ******************************************************************************/ -size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type); - -/***************************************************************************//** - * @brief - * Get the size of a named Mbed TLS context structure. This is valuable for - * code shipping as precompiled libraries and needing to link with a source - * version of PSA Crypto, since the context structures can change in size - * based on configuration options which might not have been present at library - * compilation time. - * - * @param ctx_type - * Which context structure to get the size of. Use - * #SLI_MBEDTLS_CONTEXT_ENUM_NAME() as argument. - * - * @return - * Size (in bytes) of the context structure as expected by the current build. - ******************************************************************************/ -size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type); - -/***************************************************************************//** - * @brief - * Check if a key is copyable even though the key attributes do not have the - * PSA_KEY_USAGE_COPY flag set. - * - * @param key_id - * The key ID of the key of interest. - * - * @return - * True if the key should be unconditionally copyable, otherwise false. - ******************************************************************************/ -bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id); - -#ifdef __cplusplus -} -#endif - -/// @endcond - -#endif // SLI_PSA_CRYPTO_H +/***************************************************************************//** + * @file + * @brief Silicon Labs internal PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_CRYPTO_H +#define SLI_PSA_CRYPTO_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "psa/crypto.h" + +#include +#include + +// ----------------------------------------------------------------------------- +// Defines and Macros + +// Persistent key ID ranges. +#define SLI_PSA_KEY_ID_RANGE_THREAD_START (0x00020000) +#define SLI_PSA_KEY_ID_RANGE_THREAD_END (0x0002FFFF) +#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_START (0x00030000) +#define SLI_PSA_KEY_ID_RANGE_ZIGBEE_END (0x0003FFFF) + +// Convert a type name into an enum entry name, since enum entries and type +// names share the same C namespace. +#define SLI_PSA_CONTEXT_ENUM_NAME(NAME) \ + NAME ## _e +#define SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME) \ + NAME ## _e + +// Convenience macros for getting the size of a context structure type +#define SLI_PSA_CONTEXT_GET_RUNTIME_SIZE(NAME) \ + (sli_psa_context_get_size(SLI_PSA_CONTEXT_ENUM_NAME(NAME))) +#define SLI_MBEDTLS_CONTEXT_GET_RUNTIME_SIZE(NAME) \ + (sli_mbedtls_context_get_size(SLI_MBEDTLS_CONTEXT_ENUM_NAME(NAME))) + +// ----------------------------------------------------------------------------- +// Type Definitions + +// Type names supported by sli_psa_context_get_size. +typedef enum { + SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t), + SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t) +} sli_psa_context_name_t; + +// Type names supported by sli_mbedtls_context_get_size. +typedef enum { + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx), + SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt) +} sli_mbedtls_context_name_t; + +// ----------------------------------------------------------------------------- +// Function Declarations + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @brief + * Get the size of a named PSA context structure. This is valuable for code + * shipping as precompiled libraries and needing to link with a source version + * of PSA Crypto, since the context structures can change in size based on + * configuration options which might not have been present at library + * compilation time. + * + * @param ctx_type + * Which context structure to get the size of. Use + * #SLI_PSA_CONTEXT_ENUM_NAME(psa_xxx_operation_t) as argument. + * + * @return + * Size (in bytes) of the context structure as expected by the current build. + ******************************************************************************/ +size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type); + +/***************************************************************************//** + * @brief + * Get the size of a named Mbed TLS context structure. This is valuable for + * code shipping as precompiled libraries and needing to link with a source + * version of PSA Crypto, since the context structures can change in size + * based on configuration options which might not have been present at library + * compilation time. + * + * @param ctx_type + * Which context structure to get the size of. Use + * #SLI_MBEDTLS_CONTEXT_ENUM_NAME() as argument. + * + * @return + * Size (in bytes) of the context structure as expected by the current build. + ******************************************************************************/ +size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type); + +/***************************************************************************//** + * @brief + * Check if a key is copyable even though the key attributes do not have the + * PSA_KEY_USAGE_COPY flag set. + * + * @param key_id + * The key ID of the key of interest. + * + * @return + * True if the key should be unconditionally copyable, otherwise false. + ******************************************************************************/ +bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id); + +#ifdef __cplusplus +} +#endif + +/// @endcond + +#endif // SLI_PSA_CRYPTO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c index 836ff16..b214243 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c @@ -1,834 +1,834 @@ -/***************************************************************************//** - * @file - * @brief AES abstraction based on CRYPTOACC - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/** - * This file includes alternative plugin implementations of various - * functions in aes.c using the cryptographic accelerator incorporated - * in Series-2 devices with CRYPTOACC from Silicon Laboratories. - */ - -/* - * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. - * - * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf - * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf - */ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include - -#if defined(MBEDTLS_AES_C) -#if defined(MBEDTLS_AES_ALT) -#include "cryptoacc_management.h" -#include "sx_aes.h" -#include "sx_errors.h" -#include "mbedtls/aes.h" -#include "mbedtls/platform.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/error.h" -#include - -/* Parameter validation macros based on platform_util.h */ -#define AES_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA) -#define AES_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - -/* - * Initialize AES context - */ -void mbedtls_aes_init(mbedtls_aes_context *ctx) -{ - AES_VALIDATE(ctx != NULL); - - memset(ctx, 0, sizeof(mbedtls_aes_context) ); -} - -/* - * Clear AES context - */ -void mbedtls_aes_free(mbedtls_aes_context *ctx) -{ - if ( ctx == NULL ) { - return; - } - - memset(ctx, 0, sizeof(mbedtls_aes_context) ); -} - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx) -{ - AES_VALIDATE(ctx != NULL); - - mbedtls_aes_init(&ctx->crypt); - mbedtls_aes_init(&ctx->tweak); -} - -void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) -{ - if ( ctx == NULL ) { - return; - } - - mbedtls_aes_free(&ctx->crypt); - mbedtls_aes_free(&ctx->tweak); -} - -static int mbedtls_aes_xts_decode_keys(const unsigned char *key, - unsigned int keybits, - const unsigned char **key1, - unsigned int *key1bits, - const unsigned char **key2, - unsigned int *key2bits) -{ - const unsigned int half_keybits = keybits / 2; - const unsigned int half_keybytes = half_keybits / 8; - - switch ( keybits ) { - case 256: break; - case 512: break; - default: return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - } - - *key1bits = half_keybits; - *key2bits = half_keybits; - *key1 = &key[0]; - *key2 = &key[half_keybytes]; - - return 0; -} - -int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, - const unsigned char *key, - unsigned int keybits) -{ - int ret; - const unsigned char *key1 = NULL; - const unsigned char *key2 = NULL; - unsigned int key1bits = 0; - unsigned int key2bits = 0; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(key != NULL); - - ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, - &key2, &key2bits); - if ( ret != 0 ) { - return(ret); - } - - /* Set the tweak key. Always set tweak key for the encryption mode. */ - ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); - if ( ret != 0 ) { - return(ret); - } - - /* Set crypt key for encryption. */ - return mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits); -} - -int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, - const unsigned char *key, - unsigned int keybits) -{ - int ret; - const unsigned char *key1 = NULL; - const unsigned char *key2 = NULL; - unsigned int key1bits = 0; - unsigned int key2bits = 0; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(key != NULL); - - ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, - &key2, &key2bits); - if ( ret != 0 ) { - return(ret); - } - - /* Set the tweak key. Always set tweak key for encryption. */ - ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); - if ( ret != 0 ) { - return(ret); - } - - /* Set crypt key for decryption. */ - return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); -} - -/* Endianess with 64 bits values */ -#ifndef GET_UINT64_LE -#define GET_UINT64_LE(n, b, i) \ - { \ - (n) = ( (uint64_t) (b)[(i) + 7] << 56) \ - | ( (uint64_t) (b)[(i) + 6] << 48) \ - | ( (uint64_t) (b)[(i) + 5] << 40) \ - | ( (uint64_t) (b)[(i) + 4] << 32) \ - | ( (uint64_t) (b)[(i) + 3] << 24) \ - | ( (uint64_t) (b)[(i) + 2] << 16) \ - | ( (uint64_t) (b)[(i) + 1] << 8) \ - | ( (uint64_t) (b)[(i)]); \ - } -#endif - -#ifndef PUT_UINT64_LE -#define PUT_UINT64_LE(n, b, i) \ - { \ - (b)[(i) + 7] = (unsigned char) ( (n) >> 56); \ - (b)[(i) + 6] = (unsigned char) ( (n) >> 48); \ - (b)[(i) + 5] = (unsigned char) ( (n) >> 40); \ - (b)[(i) + 4] = (unsigned char) ( (n) >> 32); \ - (b)[(i) + 3] = (unsigned char) ( (n) >> 24); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 16); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 8); \ - (b)[(i)] = (unsigned char) ( (n) ); \ - } -#endif - -typedef unsigned char mbedtls_be128[16]; - -/* - * GF(2^128) multiplication function - * - * This function multiplies a field element by x in the polynomial field - * representation. It uses 64-bit word operations to gain speed but compensates - * for machine endianess and hence works correctly on both big and little - * endian machines. - */ -static void mbedtls_gf128mul_x_ble(unsigned char r[16], - const unsigned char x[16]) -{ - uint64_t a, b, ra, rb; - - GET_UINT64_LE(a, x, 0); - GET_UINT64_LE(b, x, 8); - - ra = (a << 1) ^ 0x0087 >> (8 - ( (b >> 63) << 3) ); - rb = (a >> 63) | (b << 1); - - PUT_UINT64_LE(ra, r, 0); - PUT_UINT64_LE(rb, r, 8); -} - -/* - * AES-XTS buffer encryption/decryption - */ -int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, - int mode, - size_t length, - const unsigned char data_unit[16], - const unsigned char *input, - unsigned char *output) -{ - int ret; - size_t blocks = length / 16; - size_t leftover = length % 16; - unsigned char tweak[16]; - unsigned char prev_tweak[16]; - unsigned char tmp[16]; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(data_unit != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - /* Data units must be at least 16 bytes long. */ - if ( length < 16 ) { - return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; - } - - /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ - if ( length > (1 << 20) * 16 ) { - return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; - } - - /* Compute the tweak. */ - ret = mbedtls_aes_crypt_ecb(&ctx->tweak, MBEDTLS_AES_ENCRYPT, - data_unit, tweak); - if ( ret != 0 ) { - return(ret); - } - - while ( blocks-- ) { - size_t i; - - if ( leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0 ) { - /* We are on the last block in a decrypt operation that has - * leftover bytes, so we need to use the next tweak for this block, - * and this tweak for the lefover bytes. Save the current tweak for - * the leftovers and then update the current tweak for use on this, - * the last full block. */ - memcpy(prev_tweak, tweak, sizeof(tweak) ); - mbedtls_gf128mul_x_ble(tweak, tweak); - } - - for ( i = 0; i < 16; i++ ) { - tmp[i] = input[i] ^ tweak[i]; - } - - ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); - if ( ret != 0 ) { - return(ret); - } - - for ( i = 0; i < 16; i++ ) { - output[i] = tmp[i] ^ tweak[i]; - } - - /* Update the tweak for the next block. */ - mbedtls_gf128mul_x_ble(tweak, tweak); - - output += 16; - input += 16; - } - - if ( leftover ) { - /* If we are on the leftover bytes in a decrypt operation, we need to - * use the previous tweak for these bytes (as saved in prev_tweak). */ - unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; - - /* We are now on the final part of the data unit, which doesn't divide - * evenly by 16. It's time for ciphertext stealing. */ - size_t i; - unsigned char *prev_output = output - 16; - - /* Copy ciphertext bytes from the previous block to our output for each - * byte of cyphertext we won't steal. At the same time, copy the - * remainder of the input for this final round (since the loop bounds - * are the same). */ - for ( i = 0; i < leftover; i++ ) { - output[i] = prev_output[i]; - tmp[i] = input[i] ^ t[i]; - } - - /* Copy ciphertext bytes from the previous block for input in this - * round. */ - for (; i < 16; i++ ) { - tmp[i] = prev_output[i] ^ t[i]; - } - - ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); - if ( ret != 0 ) { - return ret; - } - - /* Write the result back to the previous block, overriding the previous - * output we copied. */ - for ( i = 0; i < 16; i++ ) { - prev_output[i] = tmp[i] ^ t[i]; - } - } - - return(0); -} -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -/* - * AES key schedule (encryption) - */ -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, - const unsigned char *key, - unsigned int keybits) -{ - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(key != NULL); - - memset(ctx, 0, sizeof(mbedtls_aes_context) ); - - if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { - /* Unsupported key size */ - return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); - } - - ctx->keybits = keybits; - memcpy(ctx->key, key, keybits / 8); - - return 0; -} - -/* - * AES key schedule (decryption) - */ -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, - const unsigned char *key, - unsigned int keybits) -{ - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(key != NULL); - - return mbedtls_aes_setkey_enc(ctx, key, keybits); -} - -/* - * AES-ECB block encryption/decryption - */ -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16]) -{ - int status; - uint32_t sx_ret; - block_t key; - block_t data_in; - block_t data_out; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - if ( ctx->keybits != 128UL - && ctx->keybits != 192UL - && ctx->keybits != 256UL ) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - data_in = block_t_convert(input, 16); - data_out = block_t_convert(output, 16); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - if (mode == MBEDTLS_AES_ENCRYPT) { - sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); - } else { - sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); - } - - if (cryptoacc_management_release() != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } else { - return 0; - } -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) - -/* - * AES-CBC buffer encryption/decryption - */ -int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - int status; - uint32_t sx_ret; - block_t key; - block_t iv_block; - block_t data_in; - block_t data_out; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(iv != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - /* Input length must be a multiple of 16 bytes which is the AES block - length. */ - if ( length & 0xf ) { - return(MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH); - } - - if ( ctx->keybits != 128UL - && ctx->keybits != 192UL - && ctx->keybits != 256UL) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - iv_block = block_t_convert(iv, 16); - data_in = block_t_convert(input, length); - data_out = block_t_convert(output, length); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - if (mode == MBEDTLS_AES_ENCRYPT) { - sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); - } else { - sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); - } - - if (cryptoacc_management_release() != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } else { - return 0; - } -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -/* - * AES-CFB128 buffer encryption/decryption - */ -int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - int status; - size_t n = iv_off ? *iv_off : 0; - size_t processed = 0; - uint32_t sx_ret; - block_t key; - block_t iv_block; - block_t data_in; - block_t data_out; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(iv_off != NULL); - AES_VALIDATE_RET(iv != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - if ( n > 15 ) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - if ( ctx->keybits != 128UL - && ctx->keybits != 192UL - && ctx->keybits != 256UL) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - iv_block = block_t_convert(iv, 16); - while ( processed < length ) { - if ( n > 0 ) { - /* start by filling up the IV */ - if ( mode == MBEDTLS_AES_ENCRYPT ) { - iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); - } else { - int c = input[processed]; - output[processed] = (unsigned char)(c ^ iv[n]); - iv[n] = (unsigned char) c; - } - n = (n + 1) & 0x0F; - processed++; - continue; - } else { - /* process one ore more blocks of data */ - size_t iterations = (length - processed) / 16; - - if ( iterations > 0 ) { - data_in = block_t_convert(&input[processed], iterations * 16); - data_out = block_t_convert(&output[processed], iterations * 16); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - if (mode == MBEDTLS_AES_ENCRYPT) { - sx_ret = sx_aes_cfb_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); - } else { - sx_ret = sx_aes_cfb_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); - } - - if (cryptoacc_management_release() != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - processed += iterations * 16; - } - - while ( length - processed > 0 ) { - if ( n == 0 ) { - // Need to update the IV but don't have a full block of input to pass to the SE - int ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); - if (ret != 0) { - return ret; - } - } - /* Save remainder to iv */ - if ( mode == MBEDTLS_AES_ENCRYPT ) { - iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); - } else { - int c = input[processed]; - output[processed] = (unsigned char)(c ^ iv[n]); - iv[n] = (unsigned char) c; - } - n = (n + 1) & 0x0F; - processed++; - } - } - } - - if ( iv_off ) { - *iv_off = n; - } - - return 0; -} - -/* - * AES-CFB8 buffer encryption/decryption - */ -int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - unsigned char c; - unsigned char ov[17]; - int ret = 0; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(iv != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { - return MBEDTLS_ERR_AES_BAD_INPUT_DATA; - } - - if ( ctx->keybits != 128UL - && ctx->keybits != 192UL - && ctx->keybits != 256UL) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - while ( length-- ) { - memcpy(ov, iv, 16); - if ( (ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv)) - != 0 ) { - return ret; - } - - if ( mode == MBEDTLS_AES_DECRYPT ) { - ov[16] = *input; - } - - c = *output++ = (unsigned char)(iv[0] ^ *input++); - - if ( mode == MBEDTLS_AES_ENCRYPT ) { - ov[16] = c; - } - - memcpy(iv, ov + 1, 16); - } - - return ret; -} -#endif /*MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -/* - * AES-CTR buffer encryption/decryption - */ -int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output) -{ - int status; - size_t n = nc_off ? *nc_off : 0; - size_t processed = 0; - uint32_t sx_ret; - block_t key; - block_t iv_block; - block_t data_in; - block_t data_out; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(nc_off != NULL); - AES_VALIDATE_RET(nonce_counter != NULL); - AES_VALIDATE_RET(stream_block != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - if ( ctx->keybits != 128UL - && ctx->keybits != 192UL - && ctx->keybits != 256UL) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - iv_block = block_t_convert(nonce_counter, 16); - - while ( processed < length ) { - if ( n > 0 ) { - /* start by filling up the IV */ - output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); - n = (n + 1) & 0x0F; - processed++; - } else { - /* process one or more blocks of data */ - size_t iterations = (length - processed) / 16; - - if ( iterations > 0 ) { - data_in = block_t_convert(&input[processed], iterations * 16); - data_out = block_t_convert(&output[processed], iterations * 16); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - // AES-CTR uses the only AES encrypt operation (for both encryption and decryption) - sx_ret = sx_aes_ctr_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); - - if (cryptoacc_management_release() != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - processed += iterations * 16; - } - - while ( length - processed > 0 ) { - if ( n == 0 ) { - // Get a new stream block - status = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, - nonce_counter, stream_block); - if (status != 0) { - return status; - } - // increment nonce counter... - for (size_t i = 0; i < 16; i++) { - nonce_counter[15 - i] = nonce_counter[15 - i] + 1; - if ( nonce_counter[15 - i] != 0 ) { - break; - } - } - } - /* Save remainder to iv */ - output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); - n = (n + 1) & 0x0F; - processed++; - } - } - } - - if ( nc_off ) { - *nc_off = n; - } - - return 0; -} -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_CIPHER_MODE_OFB) -/* - * AES-OFB (Output Feedback Mode) buffer encryption/decryption - */ -int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output) -{ - int ret = 0; - size_t n; - - AES_VALIDATE_RET(ctx != NULL); - AES_VALIDATE_RET(iv_off != NULL); - AES_VALIDATE_RET(iv != NULL); - AES_VALIDATE_RET(input != NULL); - AES_VALIDATE_RET(output != NULL); - - n = *iv_off; - - if ( n > 15 ) { - return(MBEDTLS_ERR_AES_BAD_INPUT_DATA); - } - - while ( length-- ) { - if ( n == 0 ) { - ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); - if ( ret != 0 ) { - goto exit; - } - } - *output++ = *input++ ^ iv[n]; - - n = (n + 1) & 0x0F; - } - - *iv_off = n; - - exit: - return(ret); -} -#endif /* MBEDTLS_CIPHER_MODE_OFB */ - -#endif /* MBEDTLS_AES_ALT */ - -#endif /* MBEDTLS_AES_C */ - -#endif /* CRYPTOACC_PRESENT */ +/***************************************************************************//** + * @file + * @brief AES abstraction based on CRYPTOACC + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes alternative plugin implementations of various + * functions in aes.c using the cryptographic accelerator incorporated + * in Series-2 devices with CRYPTOACC from Silicon Laboratories. + */ + +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include + +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) +#include "cryptoacc_management.h" +#include "sx_aes.h" +#include "sx_errors.h" +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include + +/* Parameter validation macros based on platform_util.h */ +#define AES_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA) +#define AES_VALIDATE(cond) \ + MBEDTLS_INTERNAL_VALIDATE(cond) + +/* + * Initialize AES context + */ +void mbedtls_aes_init(mbedtls_aes_context *ctx) +{ + AES_VALIDATE(ctx != NULL); + + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +/* + * Clear AES context + */ +void mbedtls_aes_free(mbedtls_aes_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_aes_context) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx) +{ + AES_VALIDATE(ctx != NULL); + + mbedtls_aes_init(&ctx->crypt); + mbedtls_aes_init(&ctx->tweak); +} + +void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + mbedtls_aes_free(&ctx->crypt); + mbedtls_aes_free(&ctx->tweak); +} + +static int mbedtls_aes_xts_decode_keys(const unsigned char *key, + unsigned int keybits, + const unsigned char **key1, + unsigned int *key1bits, + const unsigned char **key2, + unsigned int *key2bits) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch ( keybits ) { + case 256: break; + case 512: break; + default: return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + +int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(key != NULL); + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for encryption. */ + return mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits); +} + +int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1 = NULL; + const unsigned char *key2 = NULL; + unsigned int key1bits = 0; + unsigned int key2bits = 0; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(key != NULL); + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, + &key2, &key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if ( ret != 0 ) { + return(ret); + } + + /* Set crypt key for decryption. */ + return mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); +} + +/* Endianess with 64 bits values */ +#ifndef GET_UINT64_LE +#define GET_UINT64_LE(n, b, i) \ + { \ + (n) = ( (uint64_t) (b)[(i) + 7] << 56) \ + | ( (uint64_t) (b)[(i) + 6] << 48) \ + | ( (uint64_t) (b)[(i) + 5] << 40) \ + | ( (uint64_t) (b)[(i) + 4] << 32) \ + | ( (uint64_t) (b)[(i) + 3] << 24) \ + | ( (uint64_t) (b)[(i) + 2] << 16) \ + | ( (uint64_t) (b)[(i) + 1] << 8) \ + | ( (uint64_t) (b)[(i)]); \ + } +#endif + +#ifndef PUT_UINT64_LE +#define PUT_UINT64_LE(n, b, i) \ + { \ + (b)[(i) + 7] = (unsigned char) ( (n) >> 56); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 48); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 40); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 32); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 24); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 16); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 8); \ + (b)[(i)] = (unsigned char) ( (n) ); \ + } +#endif + +typedef unsigned char mbedtls_be128[16]; + +/* + * GF(2^128) multiplication function + * + * This function multiplies a field element by x in the polynomial field + * representation. It uses 64-bit word operations to gain speed but compensates + * for machine endianess and hence works correctly on both big and little + * endian machines. + */ +static void mbedtls_gf128mul_x_ble(unsigned char r[16], + const unsigned char x[16]) +{ + uint64_t a, b, ra, rb; + + GET_UINT64_LE(a, x, 0); + GET_UINT64_LE(b, x, 8); + + ra = (a << 1) ^ 0x0087 >> (8 - ( (b >> 63) << 3) ); + rb = (a >> 63) | (b << 1); + + PUT_UINT64_LE(ra, r, 0); + PUT_UINT64_LE(rb, r, 8); +} + +/* + * AES-XTS buffer encryption/decryption + */ +int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output) +{ + int ret; + size_t blocks = length / 16; + size_t leftover = length % 16; + unsigned char tweak[16]; + unsigned char prev_tweak[16]; + unsigned char tmp[16]; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(data_unit != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + /* Data units must be at least 16 bytes long. */ + if ( length < 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ + if ( length > (1 << 20) * 16 ) { + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + } + + /* Compute the tweak. */ + ret = mbedtls_aes_crypt_ecb(&ctx->tweak, MBEDTLS_AES_ENCRYPT, + data_unit, tweak); + if ( ret != 0 ) { + return(ret); + } + + while ( blocks-- ) { + size_t i; + + if ( leftover && (mode == MBEDTLS_AES_DECRYPT) && blocks == 0 ) { + /* We are on the last block in a decrypt operation that has + * leftover bytes, so we need to use the next tweak for this block, + * and this tweak for the lefover bytes. Save the current tweak for + * the leftovers and then update the current tweak for use on this, + * the last full block. */ + memcpy(prev_tweak, tweak, sizeof(tweak) ); + mbedtls_gf128mul_x_ble(tweak, tweak); + } + + for ( i = 0; i < 16; i++ ) { + tmp[i] = input[i] ^ tweak[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return(ret); + } + + for ( i = 0; i < 16; i++ ) { + output[i] = tmp[i] ^ tweak[i]; + } + + /* Update the tweak for the next block. */ + mbedtls_gf128mul_x_ble(tweak, tweak); + + output += 16; + input += 16; + } + + if ( leftover ) { + /* If we are on the leftover bytes in a decrypt operation, we need to + * use the previous tweak for these bytes (as saved in prev_tweak). */ + unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; + + /* We are now on the final part of the data unit, which doesn't divide + * evenly by 16. It's time for ciphertext stealing. */ + size_t i; + unsigned char *prev_output = output - 16; + + /* Copy ciphertext bytes from the previous block to our output for each + * byte of cyphertext we won't steal. At the same time, copy the + * remainder of the input for this final round (since the loop bounds + * are the same). */ + for ( i = 0; i < leftover; i++ ) { + output[i] = prev_output[i]; + tmp[i] = input[i] ^ t[i]; + } + + /* Copy ciphertext bytes from the previous block for input in this + * round. */ + for (; i < 16; i++ ) { + tmp[i] = prev_output[i] ^ t[i]; + } + + ret = mbedtls_aes_crypt_ecb(&ctx->crypt, mode, tmp, tmp); + if ( ret != 0 ) { + return ret; + } + + /* Write the result back to the previous block, overriding the previous + * output we copied. */ + for ( i = 0; i < 16; i++ ) { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + return(0); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(key != NULL); + + memset(ctx, 0, sizeof(mbedtls_aes_context) ); + + if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { + /* Unsupported key size */ + return(MBEDTLS_ERR_AES_INVALID_KEY_LENGTH); + } + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(key != NULL); + + return mbedtls_aes_setkey_enc(ctx, key, keybits); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t data_in; + block_t data_out; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL ) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + data_in = block_t_convert(input, 16); + data_out = block_t_convert(output, 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); + } else { + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, (const block_t*)&data_in, &data_out); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } else { + return 0; + } +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(iv != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + /* Input length must be a multiple of 16 bytes which is the AES block + length. */ + if ( length & 0xf ) { + return(MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH); + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(iv, 16); + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } else { + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } else { + return 0; + } +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + size_t n = iv_off ? *iv_off : 0; + size_t processed = 0; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(iv_off != NULL); + AES_VALIDATE_RET(iv != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( n > 15 ) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(iv, 16); + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + continue; + } else { + /* process one ore more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + data_in = block_t_convert(&input[processed], iterations * 16); + data_out = block_t_convert(&output[processed], iterations * 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (mode == MBEDTLS_AES_ENCRYPT) { + sx_ret = sx_aes_cfb_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } else { + sx_ret = sx_aes_cfb_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + } + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + processed += iterations * 16; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Need to update the IV but don't have a full block of input to pass to the SE + int ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if (ret != 0) { + return ret; + } + } + /* Save remainder to iv */ + if ( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)(iv[n] ^ input[processed]); + } else { + int c = input[processed]; + output[processed] = (unsigned char)(c ^ iv[n]); + iv[n] = (unsigned char) c; + } + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( iv_off ) { + *iv_off = n; + } + + return 0; +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + unsigned char c; + unsigned char ov[17]; + int ret = 0; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(iv != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ((mode != MBEDTLS_AES_ENCRYPT) && (mode != MBEDTLS_AES_DECRYPT)) { + return MBEDTLS_ERR_AES_BAD_INPUT_DATA; + } + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + while ( length-- ) { + memcpy(ov, iv, 16); + if ( (ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv)) + != 0 ) { + return ret; + } + + if ( mode == MBEDTLS_AES_DECRYPT ) { + ov[16] = *input; + } + + c = *output++ = (unsigned char)(iv[0] ^ *input++); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + ov[16] = c; + } + + memcpy(iv, ov + 1, 16); + } + + return ret; +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output) +{ + int status; + size_t n = nc_off ? *nc_off : 0; + size_t processed = 0; + uint32_t sx_ret; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(nc_off != NULL); + AES_VALIDATE_RET(nonce_counter != NULL); + AES_VALIDATE_RET(stream_block != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + if ( ctx->keybits != 128UL + && ctx->keybits != 192UL + && ctx->keybits != 256UL) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + iv_block = block_t_convert(nonce_counter, 16); + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } else { + /* process one or more blocks of data */ + size_t iterations = (length - processed) / 16; + + if ( iterations > 0 ) { + data_in = block_t_convert(&input[processed], iterations * 16); + data_out = block_t_convert(&output[processed], iterations * 16); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + // AES-CTR uses the only AES encrypt operation (for both encryption and decryption) + sx_ret = sx_aes_ctr_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, (const block_t *)&iv_block, &iv_block); + + if (cryptoacc_management_release() != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + processed += iterations * 16; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + // Get a new stream block + status = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, + nonce_counter, stream_block); + if (status != 0) { + return status; + } + // increment nonce counter... + for (size_t i = 0; i < 16; i++) { + nonce_counter[15 - i] = nonce_counter[15 - i] + 1; + if ( nonce_counter[15 - i] != 0 ) { + break; + } + } + } + /* Save remainder to iv */ + output[processed] = (unsigned char)(input[processed] ^ stream_block[n]); + n = (n + 1) & 0x0F; + processed++; + } + } + } + + if ( nc_off ) { + *nc_off = n; + } + + return 0; +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ +int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output) +{ + int ret = 0; + size_t n; + + AES_VALIDATE_RET(ctx != NULL); + AES_VALIDATE_RET(iv_off != NULL); + AES_VALIDATE_RET(iv != NULL); + AES_VALIDATE_RET(input != NULL); + AES_VALIDATE_RET(output != NULL); + + n = *iv_off; + + if ( n > 15 ) { + return(MBEDTLS_ERR_AES_BAD_INPUT_DATA); + } + + while ( length-- ) { + if ( n == 0 ) { + ret = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, iv, iv); + if ( ret != 0 ) { + goto exit; + } + } + *output++ = *input++ ^ iv[n]; + + n = (n + 1) & 0x0F; + } + + *iv_off = n; + + exit: + return(ret); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* MBEDTLS_AES_C */ + +#endif /* CRYPTOACC_PRESENT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c index 6920621..a7368a9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c @@ -1,510 +1,510 @@ -/***************************************************************************//** - * @file - * @brief AES-CMAC abstraction based on CRYPTOACC - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/** - * This file includes alternative plugin implementations of various - * functions in gmac.c using the cryptographic accelerator incorporated - * in Series-2 devices with CRYPTOACC from Silicon Laboratories. - */ - -/* - * http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf - * - * See also: - * [MGV] http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf - * - * We use the algorithm described as Shoup's method with 4-bit tables in - * [MGV] 4.1, pp. 12-13, to enhance speed without using too much memory. - */ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include - -#if defined(MBEDTLS_GCM_ALT) && defined(MBEDTLS_GCM_C) -#include "cryptoacc_management.h" -#include "mbedtls/gcm.h" -#include "mbedtls/aes.h" -#include "mbedtls/platform.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/error.h" -#include "sx_aes.h" -#include "sx_math.h" -#include "sx_errors.h" -#include "cryptolib_def.h" -#include - -/* Parameter validation macros */ -#define GCM_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_GCM_BAD_INPUT) -#define GCM_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - -/* Implementation that should never be optimized out by the compiler */ -static void mbedtls_zeroize(void *v, size_t n) -{ - volatile unsigned char *p = v; while ( n-- ) *p++ = 0; -} - -static int sli_validate_gcm_params(size_t tag_len, - size_t iv_len, - size_t add_len) -{ - // NOTE: tag lengths != 16 byte are only supported as of SE FW v1.2.0. - // Earlier firmware versions will return an error trying to verify non-16-byte - // tags using this function. - if ( tag_len < 4 || tag_len > 16 || iv_len == 0 ) { - return (MBEDTLS_ERR_GCM_BAD_INPUT); - } - - /* AD are limited to 2^64 bits, so 2^61 bytes. Since the length of AAD is - * limited by the mbedtls API to a size_t, length checking only needs to be - * done on 64-bit platforms. */ -#if SIZE_MAX > 0xFFFFFFFFUL - if (add_len >> 61 != 0) { - return MBEDTLS_ERR_GCM_BAD_INPUT; - } -#else - (void) add_len; -#endif /* 64-bit size_t */ - - /* Library does not support non-12-byte IVs */ - if (iv_len != AES_IV_GCM_SIZE) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - return 0; -} - -/* - * Initialize a context - */ -void mbedtls_gcm_init(mbedtls_gcm_context *ctx) -{ - GCM_VALIDATE(ctx != NULL); - - memset(ctx, 0, sizeof(mbedtls_gcm_context) ); -} - -// Set key -int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, - mbedtls_cipher_id_t cipher, - const unsigned char *key, - unsigned int keybits) -{ - (void) cipher; - - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(key != NULL); - GCM_VALIDATE_RET(cipher == MBEDTLS_CIPHER_ID_AES); - GCM_VALIDATE_RET(keybits == 128 || keybits == 192 || keybits == 256); - - /* Store key in gcm context */ - ctx->keybits = keybits; - memcpy(ctx->key, key, keybits / 8); - - return 0; -} - -int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, - int mode, - const unsigned char *iv, - size_t iv_len) -{ - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(iv != NULL); - - int status = sli_validate_gcm_params(16, iv_len, 0); - if (status) { - return status; - } - - /* Store input in context data structure. */ - ctx->dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; - ctx->add_len = 0; - ctx->len = 0; - - memcpy(ctx->sx_ctx, iv, AES_IV_GCM_SIZE); - return 0; -} - -int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, - const unsigned char *add, - size_t add_len) -{ - uint32_t sx_ret; - block_t key; - block_t aad; - block_t nonce; - block_t hw_ctx; - block_t dummy = NULL_blk; - - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(add_len == 0 || add != NULL); - int status = sli_validate_gcm_params(16, 12, add_len); - if (status) { - return status; - } - - if (add_len == 0) { - return 0; - } - - if (ctx->add_len > 0) { - // This accelerator does not support adding AD in chunks - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - ctx->add_len = add_len; - - key = block_t_convert(ctx->key, ctx->keybits / 8); - nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); - aad = block_t_convert(add, add_len); - hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - /* Execute GCM operation */ - if (ctx->dir == SLI_GCM_ENC) { - sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, - (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); - } else { - sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, - (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); - } - status = cryptoacc_management_release(); - - if (sx_ret == CRYPTOLIB_SUCCESS) { - return status; - } else { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } -} - -int mbedtls_gcm_update(mbedtls_gcm_context *ctx, - const unsigned char *input, size_t input_length, - unsigned char *output, size_t output_size, - size_t *output_length) -{ - int status; - uint32_t sx_ret; - block_t data_in; - block_t data_out; - block_t key; - block_t nonce; - block_t hw_ctx; - block_t dummy = NULL_blk; - - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(input_length == 0 || input != NULL); - GCM_VALIDATE_RET(input_length == 0 || output != NULL); - - *output_length = 0; - - if (input_length > output_size) { - return MBEDTLS_ERR_GCM_BAD_INPUT; - } - - if (input_length == 0) { - return 0; - } - - /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes - * Also check for possible overflow */ - if ( ctx->len + input_length < ctx->len - || (uint64_t) ctx->len + input_length > 0xFFFFFFFE0ull ) { - return(MBEDTLS_ERR_GCM_BAD_INPUT); - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(output, input_length); - hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); - - if (ctx->add_len == 0 && ctx->len == 0) { - /* If there were no additional authentcation data then - mbedtls_gcm_starts did not 'CTX_BEGIN' the GCM operation - in the CRYPTOACC, so we need to 'CTX_BEGIN' now. */ - nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - /* Execute GCM operation */ - if (ctx->dir == SLI_GCM_ENC) { - sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); - } else { - sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); - } - status = cryptoacc_management_release(); - } else { - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - /* Execute GCM operation */ - if (ctx->dir == SLI_GCM_ENC) { - sx_ret = sx_aes_gcm_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&hw_ctx, &hw_ctx); - } else { - sx_ret = sx_aes_gcm_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&hw_ctx, &hw_ctx); - } - status = cryptoacc_management_release(); - } - - ctx->len += input_length; - - if (sx_ret == CRYPTOLIB_SUCCESS) { - *output_length = input_length; - return status; - } else { - memset(output, 0, output_size); - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } -} - -int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, - unsigned char *output, size_t output_size, - size_t *output_length, - unsigned char *tag, - size_t tag_len) -{ - // Voiding these because our implementation does not support - // partial-block input (i.e. passing a partial block to - // update() will have caused the operation to finish already) - (void) output; - (void) output_size; - *output_length = 0; - - int status; - uint32_t sx_ret; - block_t key; - block_t _tag; - uint8_t tagbuf[16]; - uint8_t lena_lenc[16]; - block_t lena_lenc_blk = NULL_blk; - block_t dummy = NULL_blk; - block_t hw_ctx; - - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(tag != NULL); - - status = sli_validate_gcm_params(tag_len, 12, 16); - if (status) { - return status; - } - - if (ctx->add_len == 0 && ctx->len == 0) { - /* If there were no data and additional authentcation data then - mbedtls_gcm_starts and update did not start the GCM operation, - so we need to run the whole GCM now. */ - return mbedtls_gcm_crypt_and_tag(ctx, - ctx->dir == SLI_GCM_ENC ? MBEDTLS_GCM_ENCRYPT - : MBEDTLS_GCM_DECRYPT, - 0, ctx->sx_ctx, AES_IV_GCM_SIZE, 0, 0, 0, 0, - tag_len, tag); - } else { - key = block_t_convert(ctx->key, ctx->keybits / 8); - _tag = block_t_convert(tagbuf, 16); // CRYPTOACC supports only 128bits tags - hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); - - // build lena_lenc block as big endian byte array - sx_math_u64_to_u8array(ctx->add_len << 3, &lena_lenc[0], sx_big_endian); - sx_math_u64_to_u8array(ctx->len << 3, &lena_lenc[8], sx_big_endian); - lena_lenc_blk = block_t_convert(lena_lenc, 16); - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - if (ctx->dir == SLI_GCM_ENC) { - sx_ret = sx_aes_gcm_encrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, - (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); - } else { - sx_ret = sx_aes_gcm_decrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, - (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); - } - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); - } - - memcpy(tag, tagbuf, tag_len); - return(status); - } -} - -int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, - int mode, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - unsigned char *tag) -{ - int status; - uint32_t sx_ret; - sli_gcm_mode_t dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; - block_t key; - block_t aad; - block_t _tag; - block_t nonce; - block_t data_in; - block_t data_out; - uint8_t tagbuf[16]; - - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(iv != NULL); - GCM_VALIDATE_RET(add_len == 0 || add != NULL); - GCM_VALIDATE_RET(length == 0 || input != NULL); - GCM_VALIDATE_RET(length == 0 || output != NULL); - GCM_VALIDATE_RET(tag != NULL); - - status = sli_validate_gcm_params(tag_len, iv_len, add_len); - if (status) { - return status; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - nonce = block_t_convert(iv, iv_len); - aad = block_t_convert(add, add_len); - _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags - data_in = block_t_convert(input, length); - data_out = block_t_convert(output, length); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - /* Execute GCM operation */ - if (dir == SLI_GCM_ENC) { - sx_ret = sx_aes_gcm_encrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&nonce, &_tag, (const block_t *)&aad); - } else { - sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&nonce, &_tag, (const block_t *)&aad); - } - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - mbedtls_zeroize(output, length); - return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); - } - - memcpy(tag, tagbuf, tag_len); - return(status); -} - -int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *tag, - size_t tag_len, - const unsigned char *input, - unsigned char *output) -{ - int status; - uint32_t sx_ret; - block_t key; - block_t aad; - block_t _tag; - block_t nonce; - block_t data_in; - block_t data_out; - uint8_t tagbuf[16]; - - /* Check input parameters. */ - GCM_VALIDATE_RET(ctx != NULL); - GCM_VALIDATE_RET(iv != NULL); - GCM_VALIDATE_RET(add_len == 0 || add != NULL); - GCM_VALIDATE_RET(tag != NULL); - GCM_VALIDATE_RET(length == 0 || input != NULL); - GCM_VALIDATE_RET(length == 0 || output != NULL); - - status = sli_validate_gcm_params(tag_len, iv_len, add_len); - if (status) { - return status; - } - - key = block_t_convert(ctx->key, ctx->keybits / 8); - nonce = block_t_convert(iv, iv_len); - aad = block_t_convert(add, add_len); - _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags - data_in = block_t_convert(input, length); - data_out = block_t_convert(output, length); - - status = cryptoacc_management_acquire(); - if (status != 0) { - return status; - } - /* Execute GCM operation */ - sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, - (const block_t *)&nonce, &_tag, (const block_t *)&aad); - status = cryptoacc_management_release(); - - if (sx_ret == CRYPTOLIB_SUCCESS) { - if (memcmp_time_cst((uint8_t*)tag, tagbuf, tag_len) == 0) { - return(status); - } else { - mbedtls_zeroize(output, length); - return(MBEDTLS_ERR_GCM_AUTH_FAILED); - } - } else { - mbedtls_zeroize(output, length); - return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); - } -} - -void mbedtls_gcm_free(mbedtls_gcm_context *ctx) -{ - if ( ctx == NULL ) { - return; - } - mbedtls_zeroize(ctx, sizeof(mbedtls_gcm_context) ); -} - -#endif /* MBEDTLS_GCM_ALT && MBEDTLS_GCM_C */ - -#endif /* CRYPTOACC_PRESENT */ +/***************************************************************************//** + * @file + * @brief AES-CMAC abstraction based on CRYPTOACC + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes alternative plugin implementations of various + * functions in gmac.c using the cryptographic accelerator incorporated + * in Series-2 devices with CRYPTOACC from Silicon Laboratories. + */ + +/* + * http://csrc.nist.gov/publications/nistpubs/800-38D/SP-800-38D.pdf + * + * See also: + * [MGV] http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf + * + * We use the algorithm described as Shoup's method with 4-bit tables in + * [MGV] 4.1, pp. 12-13, to enhance speed without using too much memory. + */ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include + +#if defined(MBEDTLS_GCM_ALT) && defined(MBEDTLS_GCM_C) +#include "cryptoacc_management.h" +#include "mbedtls/gcm.h" +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include "sx_aes.h" +#include "sx_math.h" +#include "sx_errors.h" +#include "cryptolib_def.h" +#include + +/* Parameter validation macros */ +#define GCM_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_GCM_BAD_INPUT) +#define GCM_VALIDATE(cond) \ + MBEDTLS_INTERNAL_VALIDATE(cond) + +/* Implementation that should never be optimized out by the compiler */ +static void mbedtls_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = v; while ( n-- ) *p++ = 0; +} + +static int sli_validate_gcm_params(size_t tag_len, + size_t iv_len, + size_t add_len) +{ + // NOTE: tag lengths != 16 byte are only supported as of SE FW v1.2.0. + // Earlier firmware versions will return an error trying to verify non-16-byte + // tags using this function. + if ( tag_len < 4 || tag_len > 16 || iv_len == 0 ) { + return (MBEDTLS_ERR_GCM_BAD_INPUT); + } + + /* AD are limited to 2^64 bits, so 2^61 bytes. Since the length of AAD is + * limited by the mbedtls API to a size_t, length checking only needs to be + * done on 64-bit platforms. */ +#if SIZE_MAX > 0xFFFFFFFFUL + if (add_len >> 61 != 0) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } +#else + (void) add_len; +#endif /* 64-bit size_t */ + + /* Library does not support non-12-byte IVs */ + if (iv_len != AES_IV_GCM_SIZE) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + return 0; +} + +/* + * Initialize a context + */ +void mbedtls_gcm_init(mbedtls_gcm_context *ctx) +{ + GCM_VALIDATE(ctx != NULL); + + memset(ctx, 0, sizeof(mbedtls_gcm_context) ); +} + +// Set key +int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits) +{ + (void) cipher; + + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(key != NULL); + GCM_VALIDATE_RET(cipher == MBEDTLS_CIPHER_ID_AES); + GCM_VALIDATE_RET(keybits == 128 || keybits == 192 || keybits == 256); + + /* Store key in gcm context */ + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len) +{ + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(iv != NULL); + + int status = sli_validate_gcm_params(16, iv_len, 0); + if (status) { + return status; + } + + /* Store input in context data structure. */ + ctx->dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; + ctx->add_len = 0; + ctx->len = 0; + + memcpy(ctx->sx_ctx, iv, AES_IV_GCM_SIZE); + return 0; +} + +int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, + const unsigned char *add, + size_t add_len) +{ + uint32_t sx_ret; + block_t key; + block_t aad; + block_t nonce; + block_t hw_ctx; + block_t dummy = NULL_blk; + + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(add_len == 0 || add != NULL); + int status = sli_validate_gcm_params(16, 12, add_len); + if (status) { + return status; + } + + if (add_len == 0) { + return 0; + } + + if (ctx->add_len > 0) { + // This accelerator does not support adding AD in chunks + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + ctx->add_len = add_len; + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); + aad = block_t_convert(add, add_len); + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); + } else { + sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&aad); + } + status = cryptoacc_management_release(); + + if (sx_ret == CRYPTOLIB_SUCCESS) { + return status; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_gcm_update(mbedtls_gcm_context *ctx, + const unsigned char *input, size_t input_length, + unsigned char *output, size_t output_size, + size_t *output_length) +{ + int status; + uint32_t sx_ret; + block_t data_in; + block_t data_out; + block_t key; + block_t nonce; + block_t hw_ctx; + block_t dummy = NULL_blk; + + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(input_length == 0 || input != NULL); + GCM_VALIDATE_RET(input_length == 0 || output != NULL); + + *output_length = 0; + + if (input_length > output_size) { + return MBEDTLS_ERR_GCM_BAD_INPUT; + } + + if (input_length == 0) { + return 0; + } + + /* Total length is restricted to 2^39 - 256 bits, ie 2^36 - 2^5 bytes + * Also check for possible overflow */ + if ( ctx->len + input_length < ctx->len + || (uint64_t) ctx->len + input_length > 0xFFFFFFFE0ull ) { + return(MBEDTLS_ERR_GCM_BAD_INPUT); + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + if (ctx->add_len == 0 && ctx->len == 0) { + /* If there were no additional authentcation data then + mbedtls_gcm_starts did not 'CTX_BEGIN' the GCM operation + in the CRYPTOACC, so we need to 'CTX_BEGIN' now. */ + nonce = block_t_convert(ctx->sx_ctx, AES_IV_GCM_SIZE); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); + } else { + sx_ret = sx_aes_gcm_decrypt_init((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &hw_ctx, (const block_t *)&dummy); + } + status = cryptoacc_management_release(); + } else { + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&hw_ctx, &hw_ctx); + } else { + sx_ret = sx_aes_gcm_decrypt_update((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&hw_ctx, &hw_ctx); + } + status = cryptoacc_management_release(); + } + + ctx->len += input_length; + + if (sx_ret == CRYPTOLIB_SUCCESS) { + *output_length = input_length; + return status; + } else { + memset(output, 0, output_size); + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} + +int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, + unsigned char *output, size_t output_size, + size_t *output_length, + unsigned char *tag, + size_t tag_len) +{ + // Voiding these because our implementation does not support + // partial-block input (i.e. passing a partial block to + // update() will have caused the operation to finish already) + (void) output; + (void) output_size; + *output_length = 0; + + int status; + uint32_t sx_ret; + block_t key; + block_t _tag; + uint8_t tagbuf[16]; + uint8_t lena_lenc[16]; + block_t lena_lenc_blk = NULL_blk; + block_t dummy = NULL_blk; + block_t hw_ctx; + + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(tag != NULL); + + status = sli_validate_gcm_params(tag_len, 12, 16); + if (status) { + return status; + } + + if (ctx->add_len == 0 && ctx->len == 0) { + /* If there were no data and additional authentcation data then + mbedtls_gcm_starts and update did not start the GCM operation, + so we need to run the whole GCM now. */ + return mbedtls_gcm_crypt_and_tag(ctx, + ctx->dir == SLI_GCM_ENC ? MBEDTLS_GCM_ENCRYPT + : MBEDTLS_GCM_DECRYPT, + 0, ctx->sx_ctx, AES_IV_GCM_SIZE, 0, 0, 0, 0, + tag_len, tag); + } else { + key = block_t_convert(ctx->key, ctx->keybits / 8); + _tag = block_t_convert(tagbuf, 16); // CRYPTOACC supports only 128bits tags + hw_ctx = block_t_convert(ctx->sx_ctx, AES_CTX_xCM_SIZE); + + // build lena_lenc block as big endian byte array + sx_math_u64_to_u8array(ctx->add_len << 3, &lena_lenc[0], sx_big_endian); + sx_math_u64_to_u8array(ctx->len << 3, &lena_lenc[8], sx_big_endian); + lena_lenc_blk = block_t_convert(lena_lenc, 16); + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + if (ctx->dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); + } else { + sx_ret = sx_aes_gcm_decrypt_final((const block_t *)&key, (const block_t *)&dummy, &dummy, + (const block_t *)&hw_ctx, &_tag, (const block_t *)&lena_lenc_blk); + } + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } + + memcpy(tag, tagbuf, tag_len); + return(status); + } +} + +int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag) +{ + int status; + uint32_t sx_ret; + sli_gcm_mode_t dir = mode == MBEDTLS_AES_ENCRYPT ? SLI_GCM_ENC : SLI_GCM_DEC; + block_t key; + block_t aad; + block_t _tag; + block_t nonce; + block_t data_in; + block_t data_out; + uint8_t tagbuf[16]; + + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(iv != NULL); + GCM_VALIDATE_RET(add_len == 0 || add != NULL); + GCM_VALIDATE_RET(length == 0 || input != NULL); + GCM_VALIDATE_RET(length == 0 || output != NULL); + GCM_VALIDATE_RET(tag != NULL); + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(iv, iv_len); + aad = block_t_convert(add, add_len); + _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + if (dir == SLI_GCM_ENC) { + sx_ret = sx_aes_gcm_encrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + } else { + sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + } + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } + + memcpy(tag, tagbuf, tag_len); + return(status); +} + +int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output) +{ + int status; + uint32_t sx_ret; + block_t key; + block_t aad; + block_t _tag; + block_t nonce; + block_t data_in; + block_t data_out; + uint8_t tagbuf[16]; + + /* Check input parameters. */ + GCM_VALIDATE_RET(ctx != NULL); + GCM_VALIDATE_RET(iv != NULL); + GCM_VALIDATE_RET(add_len == 0 || add != NULL); + GCM_VALIDATE_RET(tag != NULL); + GCM_VALIDATE_RET(length == 0 || input != NULL); + GCM_VALIDATE_RET(length == 0 || output != NULL); + + status = sli_validate_gcm_params(tag_len, iv_len, add_len); + if (status) { + return status; + } + + key = block_t_convert(ctx->key, ctx->keybits / 8); + nonce = block_t_convert(iv, iv_len); + aad = block_t_convert(add, add_len); + _tag = block_t_convert(tagbuf, sizeof(tagbuf)); // CRYPTOACC supports only 128bits tags + data_in = block_t_convert(input, length); + data_out = block_t_convert(output, length); + + status = cryptoacc_management_acquire(); + if (status != 0) { + return status; + } + /* Execute GCM operation */ + sx_ret = sx_aes_gcm_decrypt((const block_t *)&key, (const block_t *)&data_in, &data_out, + (const block_t *)&nonce, &_tag, (const block_t *)&aad); + status = cryptoacc_management_release(); + + if (sx_ret == CRYPTOLIB_SUCCESS) { + if (memcmp_time_cst((uint8_t*)tag, tagbuf, tag_len) == 0) { + return(status); + } else { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_GCM_AUTH_FAILED); + } + } else { + mbedtls_zeroize(output, length); + return(MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED); + } +} + +void mbedtls_gcm_free(mbedtls_gcm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + mbedtls_zeroize(ctx, sizeof(mbedtls_gcm_context) ); +} + +#endif /* MBEDTLS_GCM_ALT && MBEDTLS_GCM_C */ + +#endif /* CRYPTOACC_PRESENT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c index e4bcb36..c20e03f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c @@ -1,349 +1,349 @@ -/***************************************************************************//** - * @file - * @brief AES-CCM abstraction based on PSA accelerators - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/** - * This file includes an alternative implementation of various functions in - * ccm.c, using the accelerators incorporated in devices from Silicon Labs. - * - * This alternative implementation calls the PSA Crypto drivers provided - * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. - */ - -#include - -#if defined(MBEDTLS_AES_C) && defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CCM_ALT) - -#include "mbedtls/ccm.h" -#include "mbedtls/error.h" - -#if defined(MBEDTLS_PLATFORM_C) -#include "mbedtls/platform.h" -#else -#include -#define mbedtls_calloc calloc -#define mbedtls_free free -#if defined(MBEDTLS_SELF_TEST) -#include -#define mbedtls_printf printf -#endif /* MBEDTLS_SELF_TEST */ -#endif /* MBEDTLS_PLATFORM_C */ - -#include "psa/crypto.h" - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_functions.h" -#define AEAD_IMPLEMENTATION_PRESENT -#define SLI_DEVICE_HAS_AES_192 -#define AEAD_ENCRYPT_TAG_FCT sli_se_driver_aead_encrypt_tag -#define AEAD_DECRYPT_TAG_FCT sli_se_driver_aead_decrypt_tag -#elif defined(CRYPTO_PRESENT) -#include "sli_crypto_transparent_functions.h" -#define AEAD_IMPLEMENTATION_PRESENT -#define AEAD_ENCRYPT_TAG_FCT sli_crypto_transparent_aead_encrypt_tag -#define AEAD_DECRYPT_TAG_FCT sli_crypto_transparent_aead_decrypt_tag -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_functions.h" -#define AEAD_IMPLEMENTATION_PRESENT -#define SLI_DEVICE_HAS_AES_192 -#define AEAD_ENCRYPT_TAG_FCT sli_cryptoacc_transparent_aead_encrypt_tag -#define AEAD_DECRYPT_TAG_FCT sli_cryptoacc_transparent_aead_decrypt_tag -#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) -#include "sli_si91x_crypto_driver_functions.h" -#define AEAD_IMPLEMENTATION_PRESENT -#define AEAD_ENCRYPT_TAG_FCT sl_si91x_crypto_aead_encrypt -#define AEAD_DECRYPT_TAG_FCT sl_si91x_crypto_aead_decrypt -#endif - -#if defined(AEAD_IMPLEMENTATION_PRESENT) - -#include - -static int psa_status_to_mbedtls(psa_status_t status) -{ - switch ( status ) { - case PSA_SUCCESS: - return 0; - case PSA_ERROR_INVALID_SIGNATURE: - return MBEDTLS_ERR_CCM_AUTH_FAILED; - case PSA_ERROR_HARDWARE_FAILURE: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - default: - return MBEDTLS_ERR_CCM_BAD_INPUT; - } -} - -/* - * Initialize CCM context - */ -void mbedtls_ccm_init(mbedtls_ccm_context *ctx) -{ - if ( ctx == NULL ) { - return; - } - - memset(ctx, 0, sizeof(mbedtls_ccm_context) ); -} - -/* - * Clear CCM context - */ -void mbedtls_ccm_free(mbedtls_ccm_context *ctx) -{ - if ( ctx == NULL ) { - return; - } - - memset(ctx, 0, sizeof(mbedtls_ccm_context) ); -} - -/* - * CCM key schedule - */ -int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, - mbedtls_cipher_id_t cipher, - const unsigned char *key, - unsigned int keybits) -{ - if (ctx == NULL || key == NULL) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - memset(ctx, 0, sizeof(mbedtls_ccm_context) ); - - if ( cipher != MBEDTLS_CIPHER_ID_AES ) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { - /* Unsupported key size */ - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - #if !defined(SLI_DEVICE_HAS_AES_192) - if (192UL == keybits) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - #endif - - ctx->keybits = keybits; - memcpy(ctx->key, key, keybits / 8); - - return 0; -} - -int mbedtls_ccm_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, - unsigned char *tag, size_t tag_len) -{ - // 'Regular' CCM always outputs a tag of at least 4 bytes - if (tag_len < 4) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - return mbedtls_ccm_star_encrypt_and_tag(ctx, length, iv, iv_len, add, add_len, - input, output, tag, tag_len); -} - -int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, - const unsigned char *tag, size_t tag_len) -{ - // 'Regular' CCM always verifies a tag of at least 4 bytes - if (tag_len < 4) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - return mbedtls_ccm_star_auth_decrypt(ctx, length, iv, iv_len, add, add_len, - input, output, tag, tag_len); -} - -int mbedtls_ccm_star_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, - unsigned char *tag, size_t tag_len) -{ - if ( ctx == NULL || iv == NULL || iv_len == 0 - || (add_len > 0 && add == NULL) || add_len >= 0xFF00 - || (length > 0 && input == NULL) || length >= 0xFF00 - || (length > 0 && output == NULL) - || (tag_len > 0 && tag == NULL) ) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - psa_status_t psa_status; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attr, ctx->keybits); - - if (tag_len > 0) { - psa_status = AEAD_ENCRYPT_TAG_FCT( - &attr, ctx->key, ctx->keybits / 8, - PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), - iv, iv_len, - add, add_len, - input, length, - output, length, &length, - tag, tag_len, &tag_len); - } else { - (void) tag; - uint8_t dummy_tag[4]; - psa_status = AEAD_ENCRYPT_TAG_FCT( - &attr, ctx->key, ctx->keybits / 8, - PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), - iv, iv_len, - add, add_len, - input, length, - output, length, &length, - dummy_tag, sizeof(dummy_tag), &tag_len); - } - - psa_reset_key_attributes(&attr); - return psa_status_to_mbedtls(psa_status); -} - -int mbedtls_ccm_star_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, - const unsigned char *tag, size_t tag_len) -{ - if ( ctx == NULL || iv == NULL || iv_len == 0 - || (add_len > 0 && add == NULL) || add_len >= 0xFF00 - || (length > 0 && input == NULL) || length >= 0xFF00 - || (length > 0 && output == NULL) - || (tag_len > 0 && tag == NULL) ) { - return MBEDTLS_ERR_CCM_BAD_INPUT; - } - - psa_status_t psa_status; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attr, ctx->keybits); - - if (tag_len > 0) { - psa_status = AEAD_DECRYPT_TAG_FCT( - &attr, ctx->key, ctx->keybits / 8, - PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), - iv, iv_len, - add, add_len, - input, length, - tag, tag_len, - output, length, &length); - } else { - // CCM(*) is symmetric in encryption/decryption of the data, so if we don't have - // to verify a tag we can transform ciphertext to plaintext by running an - // 'encrypt' operation and throwing away the tag. - (void) tag; - uint8_t dummy_tag[4]; - psa_status = AEAD_ENCRYPT_TAG_FCT( - &attr, ctx->key, ctx->keybits / 8, - PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), - iv, iv_len, - add, add_len, - input, length, - output, length, &length, - dummy_tag, sizeof(dummy_tag), &tag_len); - } - - psa_reset_key_attributes(&attr); - return psa_status_to_mbedtls(psa_status); -} - -/* Provide stubs for linkage purposes. To be implemented when implementing - * support for multipart AEAD in the PSA drivers, see [PSEC-3221] */ -int mbedtls_ccm_starts(mbedtls_ccm_context *ctx, - int mode, - const unsigned char *iv, - size_t iv_len) -{ - (void) ctx; - (void) mode; - (void) iv; - (void) iv_len; - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; -} - -int mbedtls_ccm_set_lengths(mbedtls_ccm_context *ctx, - size_t total_ad_len, - size_t plaintext_len, - size_t tag_len) -{ - (void) ctx; - (void) total_ad_len; - (void) plaintext_len; - (void) tag_len; - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; -} - -int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, - const unsigned char *ad, - size_t ad_len) -{ - (void) ctx; - (void) ad; - (void) ad_len; - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; -} - -int mbedtls_ccm_update(mbedtls_ccm_context *ctx, - const unsigned char *input, size_t input_len, - unsigned char *output, size_t output_size, - size_t *output_len) -{ - (void) ctx; - (void) input; - (void) input_len; - (void) output; - (void) output_size; - (void) output_len; - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; -} - -int mbedtls_ccm_finish(mbedtls_ccm_context *ctx, - unsigned char *tag, size_t tag_len) -{ - (void) ctx; - (void) tag; - (void) tag_len; - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; -} - -#endif /* AEAD_IMPLEMENTATION_PRESENT */ - -#endif /* MBEDTLS_AES_C && MBEDTLS_CCM_C && MBEDTLS_CCM_ALT */ +/***************************************************************************//** + * @file + * @brief AES-CCM abstraction based on PSA accelerators + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of various functions in + * ccm.c, using the accelerators incorporated in devices from Silicon Labs. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined(MBEDTLS_AES_C) && defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CCM_ALT) + +#include "mbedtls/ccm.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#if defined(MBEDTLS_SELF_TEST) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_SELF_TEST */ +#endif /* MBEDTLS_PLATFORM_C */ + +#include "psa/crypto.h" + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define SLI_DEVICE_HAS_AES_192 +#define AEAD_ENCRYPT_TAG_FCT sli_se_driver_aead_encrypt_tag +#define AEAD_DECRYPT_TAG_FCT sli_se_driver_aead_decrypt_tag +#elif defined(CRYPTO_PRESENT) +#include "sli_crypto_transparent_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define AEAD_ENCRYPT_TAG_FCT sli_crypto_transparent_aead_encrypt_tag +#define AEAD_DECRYPT_TAG_FCT sli_crypto_transparent_aead_decrypt_tag +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define SLI_DEVICE_HAS_AES_192 +#define AEAD_ENCRYPT_TAG_FCT sli_cryptoacc_transparent_aead_encrypt_tag +#define AEAD_DECRYPT_TAG_FCT sli_cryptoacc_transparent_aead_decrypt_tag +#elif defined(SLI_CRYPTOACC_PRESENT_SI91X) +#include "sli_si91x_crypto_driver_functions.h" +#define AEAD_IMPLEMENTATION_PRESENT +#define AEAD_ENCRYPT_TAG_FCT sl_si91x_crypto_aead_encrypt +#define AEAD_DECRYPT_TAG_FCT sl_si91x_crypto_aead_decrypt +#endif + +#if defined(AEAD_IMPLEMENTATION_PRESENT) + +#include + +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_INVALID_SIGNATURE: + return MBEDTLS_ERR_CCM_AUTH_FAILED; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_CCM_BAD_INPUT; + } +} + +/* + * Initialize CCM context + */ +void mbedtls_ccm_init(mbedtls_ccm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); +} + +/* + * Clear CCM context + */ +void mbedtls_ccm_free(mbedtls_ccm_context *ctx) +{ + if ( ctx == NULL ) { + return; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); +} + +/* + * CCM key schedule + */ +int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits) +{ + if (ctx == NULL || key == NULL) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + memset(ctx, 0, sizeof(mbedtls_ccm_context) ); + + if ( cipher != MBEDTLS_CIPHER_ID_AES ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + if ( (128UL != keybits) && (192UL != keybits) && (256UL != keybits) ) { + /* Unsupported key size */ + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + #if !defined(SLI_DEVICE_HAS_AES_192) + if (192UL == keybits) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + #endif + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits / 8); + + return 0; +} + +int mbedtls_ccm_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len) +{ + // 'Regular' CCM always outputs a tag of at least 4 bytes + if (tag_len < 4) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + return mbedtls_ccm_star_encrypt_and_tag(ctx, length, iv, iv_len, add, add_len, + input, output, tag, tag_len); +} + +int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len) +{ + // 'Regular' CCM always verifies a tag of at least 4 bytes + if (tag_len < 4) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + return mbedtls_ccm_star_auth_decrypt(ctx, length, iv, iv_len, add, add_len, + input, output, tag, tag_len); +} + +int mbedtls_ccm_star_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len) +{ + if ( ctx == NULL || iv == NULL || iv_len == 0 + || (add_len > 0 && add == NULL) || add_len >= 0xFF00 + || (length > 0 && input == NULL) || length >= 0xFF00 + || (length > 0 && output == NULL) + || (tag_len > 0 && tag == NULL) ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + psa_status_t psa_status; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, ctx->keybits); + + if (tag_len > 0) { + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + tag, tag_len, &tag_len); + } else { + (void) tag; + uint8_t dummy_tag[4]; + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + dummy_tag, sizeof(dummy_tag), &tag_len); + } + + psa_reset_key_attributes(&attr); + return psa_status_to_mbedtls(psa_status); +} + +int mbedtls_ccm_star_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *add, size_t add_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len) +{ + if ( ctx == NULL || iv == NULL || iv_len == 0 + || (add_len > 0 && add == NULL) || add_len >= 0xFF00 + || (length > 0 && input == NULL) || length >= 0xFF00 + || (length > 0 && output == NULL) + || (tag_len > 0 && tag == NULL) ) { + return MBEDTLS_ERR_CCM_BAD_INPUT; + } + + psa_status_t psa_status; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, ctx->keybits); + + if (tag_len > 0) { + psa_status = AEAD_DECRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, tag_len), + iv, iv_len, + add, add_len, + input, length, + tag, tag_len, + output, length, &length); + } else { + // CCM(*) is symmetric in encryption/decryption of the data, so if we don't have + // to verify a tag we can transform ciphertext to plaintext by running an + // 'encrypt' operation and throwing away the tag. + (void) tag; + uint8_t dummy_tag[4]; + psa_status = AEAD_ENCRYPT_TAG_FCT( + &attr, ctx->key, ctx->keybits / 8, + PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, sizeof(dummy_tag)), + iv, iv_len, + add, add_len, + input, length, + output, length, &length, + dummy_tag, sizeof(dummy_tag), &tag_len); + } + + psa_reset_key_attributes(&attr); + return psa_status_to_mbedtls(psa_status); +} + +/* Provide stubs for linkage purposes. To be implemented when implementing + * support for multipart AEAD in the PSA drivers, see [PSEC-3221] */ +int mbedtls_ccm_starts(mbedtls_ccm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len) +{ + (void) ctx; + (void) mode; + (void) iv; + (void) iv_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_set_lengths(mbedtls_ccm_context *ctx, + size_t total_ad_len, + size_t plaintext_len, + size_t tag_len) +{ + (void) ctx; + (void) total_ad_len; + (void) plaintext_len; + (void) tag_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, + const unsigned char *ad, + size_t ad_len) +{ + (void) ctx; + (void) ad; + (void) ad_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_update(mbedtls_ccm_context *ctx, + const unsigned char *input, size_t input_len, + unsigned char *output, size_t output_size, + size_t *output_len) +{ + (void) ctx; + (void) input; + (void) input_len; + (void) output; + (void) output_size; + (void) output_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +int mbedtls_ccm_finish(mbedtls_ccm_context *ctx, + unsigned char *tag, size_t tag_len) +{ + (void) ctx; + (void) tag; + (void) tag_len; + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; +} + +#endif /* AEAD_IMPLEMENTATION_PRESENT */ + +#endif /* MBEDTLS_AES_C && MBEDTLS_CCM_C && MBEDTLS_CCM_ALT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c index db343c6..c57e2a1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c @@ -1,414 +1,414 @@ -/***************************************************************************//** - * @file - * @brief AES-CMAC abstraction based on PSA accelerators - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/** - * This file includes an alternative implementation of various functions in - * cmac.c, using the accelerators incorporated in devices from Silicon Labs. - * - * This alternative implementation calls the PSA Crypto drivers provided - * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. - */ - -#include - -#if defined (MBEDTLS_CMAC_C) && defined(MBEDTLS_CMAC_ALT) - -#include "mbedtls/cmac.h" -#include "mbedtls/error.h" - -#if defined(MBEDTLS_PLATFORM_C) -#include "mbedtls/platform.h" -#else -#include -#define mbedtls_calloc calloc -#define mbedtls_free free -#if defined(MBEDTLS_SELF_TEST) -#include -#define mbedtls_printf printf -#endif /* MBEDTLS_SELF_TEST */ -#endif /* MBEDTLS_PLATFORM_C */ - -#include "psa/crypto.h" - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_functions.h" -#define SLI_DEVICE_HAS_AES_192 -#define MAC_IMPLEMENTATION_PRESENT -#define MAC_SETUP_EN_FCT sli_se_transparent_mac_sign_setup -#define MAC_SETUP_DE_FCT sli_se_transparent_mac_verify_setup -#define MAC_UPDATE_FCT sli_se_transparent_mac_update -#define MAC_FINISH_EN_FCT sli_se_transparent_mac_sign_finish -#define MAC_FINISH_DE_FCT sli_se_transparent_mac_verify_finish -#define MAC_ABORT_FCT sli_se_transparent_mac_abort -#define MAC_ONESHOT_EN_FCT sli_se_transparent_mac_compute -#define MAC_ONESHOT_DE_FCT sli_se_transparent_mac_verify - -#if defined(RADIOAES_PRESENT) -#include "sli_protocol_crypto.h" -#endif -#elif defined(CRYPTO_PRESENT) -#include "sli_crypto_transparent_functions.h" -#define MAC_IMPLEMENTATION_PRESENT -#define MAC_SETUP_EN_FCT sli_crypto_transparent_mac_sign_setup -#define MAC_SETUP_DE_FCT sli_crypto_transparent_mac_verify_setup -#define MAC_UPDATE_FCT sli_crypto_transparent_mac_update -#define MAC_FINISH_EN_FCT sli_crypto_transparent_mac_sign_finish -#define MAC_FINISH_DE_FCT sli_crypto_transparent_mac_verify_finish -#define MAC_ABORT_FCT sli_crypto_transparent_mac_abort -#define MAC_ONESHOT_EN_FCT sli_crypto_transparent_mac_compute -#define MAC_ONESHOT_DE_FCT sli_crypto_transparent_mac_verify -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_functions.h" -#define SLI_DEVICE_HAS_AES_192 -#define MAC_IMPLEMENTATION_PRESENT -#define MAC_SETUP_EN_FCT sli_cryptoacc_transparent_mac_sign_setup -#define MAC_SETUP_DE_FCT sli_cryptoacc_transparent_mac_verify_setup -#define MAC_UPDATE_FCT sli_cryptoacc_transparent_mac_update -#define MAC_FINISH_EN_FCT sli_cryptoacc_transparent_mac_sign_finish -#define MAC_FINISH_DE_FCT sli_cryptoacc_transparent_mac_verify_finish -#define MAC_ABORT_FCT sli_cryptoacc_transparent_mac_abort -#define MAC_ONESHOT_EN_FCT sli_cryptoacc_transparent_mac_compute -#define MAC_ONESHOT_DE_FCT sli_cryptoacc_transparent_mac_verify -#endif - -#if defined(MAC_IMPLEMENTATION_PRESENT) - -#include - -static int psa_status_to_mbedtls(psa_status_t status) -{ - switch ( status ) { - case PSA_SUCCESS: - return 0; - case PSA_ERROR_HARDWARE_FAILURE: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - default: - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } -} - -static inline void sl_psa_set_key_type(psa_key_attributes_t *attributes, - psa_key_type_t type) -{ - /* Common case: quick path */ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = type; -} - -int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, - const unsigned char *key, size_t keybits) -{ - mbedtls_cipher_type_t type; - mbedtls_cmac_context_t *cmac_ctx; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - - if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || key == NULL ) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - type = (mbedtls_cipher_type_t)ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(type); - - switch ( type ) { - case MBEDTLS_CIPHER_AES_128_ECB: - psa_set_key_bits(&attr, 128); - break; - case MBEDTLS_CIPHER_AES_192_ECB: - #if defined(SLI_DEVICE_HAS_AES_192) - psa_set_key_bits(&attr, 192); - #else - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - #endif - break; - case MBEDTLS_CIPHER_AES_256_ECB: - psa_set_key_bits(&attr, 256); - break; - default: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - - if ( ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { - /* Allocate CMAC context memory if it hasn't already been allocated */ - cmac_ctx = mbedtls_calloc(1, sizeof(struct mbedtls_cmac_context_t) ); - if ( cmac_ctx == NULL ) { - return(MBEDTLS_ERR_CIPHER_ALLOC_FAILED); - } - - ctx->MBEDTLS_PRIVATE(cmac_ctx) = cmac_ctx; - } else { - mbedtls_platform_zeroize(ctx->MBEDTLS_PRIVATE(cmac_ctx), sizeof(*ctx->MBEDTLS_PRIVATE(cmac_ctx)) ); - } - - return psa_status_to_mbedtls( - MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, - &attr, - key, - keybits / 8U, - PSA_ALG_CMAC) ); -} - -int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, - const unsigned char *input, size_t ilen) -{ - if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || input == NULL - || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { - return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); - } - - return psa_status_to_mbedtls( - MAC_UPDATE_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, - input, - ilen) ); -} - -int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, - unsigned char *output) -{ - if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL - || output == NULL ) { - return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); - } - - size_t olen = 0; - - return psa_status_to_mbedtls( - MAC_FINISH_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, - output, - MBEDTLS_AES_BLOCK_SIZE, - &olen) ); -} - -int mbedtls_cipher_cmac_reset(mbedtls_cipher_context_t *ctx) -{ - if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { - return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); - } - - uint8_t key[32]; - size_t key_len; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - - if ( ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len > sizeof(key) ) { - return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); - } - - /* Save the key to be able to restart the operation */ - memcpy(key, - ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key, - ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len); - key_len = ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len; - psa_set_key_bits(&attr, key_len * 8); - - /* Abort and restart with the same key */ - MAC_ABORT_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx); - return psa_status_to_mbedtls( - MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, - &attr, - key, - key_len, - PSA_ALG_CMAC) ); -} - -#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) -/* For speeding up PBKDF2-CMAC, which needs a lot of iterations with small-size - * CMAC operations, we can dispatch these to the RADIOAES instance if there is - * one available. - * - * Function limitations: can only be used with AES-128 or AES-256, and needs to - * have as short as possible execution time to not block other time-sensitive - * operations (such as BLE RPA). Will always output a full CMAC (16 bytes). - * - * \param key Raw key bytes, \p keylen bytes long - * \param keylen Length of \p key in bytes, either 16 (AES-128) or 32 (AES-256) - * \param input Data bytes to calculate the CMAC over, length \p ilen bytes - * \param ilen Length in bytes of \p input - * \param output Output buffer for the calculated CMAC tag (16 bytes) - * - * \return \c 0 on success, MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED on failure - */ -static int sli_short_cmac_operation(const unsigned char *key, size_t keylen, - const unsigned char *input, size_t ilen, - unsigned char *output) -{ - sl_status_t status = sli_aes_cmac_radio(key, - keylen, - input, - ilen, - output); - if (status == SL_STATUS_OK) { - return 0; - } else { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } -} -#endif - -int mbedtls_cipher_cmac(const mbedtls_cipher_info_t *cipher_info, - const unsigned char *key, size_t keylen, - const unsigned char *input, size_t ilen, - unsigned char *output) -{ - if ( cipher_info == NULL || key == NULL || input == NULL || output == NULL ) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { - case MBEDTLS_CIPHER_AES_128_ECB: - if ( keylen != 128UL ) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - break; - case MBEDTLS_CIPHER_AES_192_ECB: - #if defined(SLI_DEVICE_HAS_AES_192) - if ( keylen != 192UL ) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - break; - #else - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - #endif - case MBEDTLS_CIPHER_AES_256_ECB: - if ( keylen != 256UL ) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - break; - default: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - -#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) - /* Use the fast shortcut if available */ - if ( (keylen == 128UL || keylen == 256UL) && (ilen <= 2 * MBEDTLS_AES_BLOCK_SIZE) ) { - return sli_short_cmac_operation(key, keylen, - input, ilen, output); - } -#endif - - size_t olen = 0; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - - switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { - case MBEDTLS_CIPHER_AES_128_ECB: - psa_set_key_bits(&attr, 128); - break; - case MBEDTLS_CIPHER_AES_192_ECB: - psa_set_key_bits(&attr, 192); - break; - case MBEDTLS_CIPHER_AES_256_ECB: - psa_set_key_bits(&attr, 256); - break; - default: - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return psa_status_to_mbedtls( - MAC_ONESHOT_EN_FCT(&attr, - key, keylen / 8U, - PSA_ALG_CMAC, - input, ilen, - output, MBEDTLS_AES_BLOCK_SIZE, &olen) ); -} - -/* - * Implementation of AES-CMAC-PRF-128 defined in RFC 4615 - */ -int mbedtls_aes_cmac_prf_128(const unsigned char *key, size_t key_length, - const unsigned char *input, size_t in_len, - unsigned char output[16]) -{ - int ret; - unsigned char zero_key[MBEDTLS_AES_BLOCK_SIZE]; - unsigned char int_key[MBEDTLS_AES_BLOCK_SIZE]; - - if ( key == NULL || input == NULL || output == NULL ) { - return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); - } - - size_t olen = 0; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attr, 128); - - if ( key_length == MBEDTLS_AES_BLOCK_SIZE ) { - /* Use key as is */ - memcpy(int_key, key, MBEDTLS_AES_BLOCK_SIZE); - } else { - memset(zero_key, 0, MBEDTLS_AES_BLOCK_SIZE); - -#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) - /* Use the fast shortcut if available */ - if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { - ret = sli_short_cmac_operation(zero_key, MBEDTLS_AES_BLOCK_SIZE * 8, - key, key_length, int_key); - } else -#endif - { - ret = psa_status_to_mbedtls( - MAC_ONESHOT_EN_FCT(&attr, - zero_key, MBEDTLS_AES_BLOCK_SIZE, - PSA_ALG_CMAC, - key, key_length, - int_key, MBEDTLS_AES_BLOCK_SIZE, &olen) ); - } - if ( ret != 0 ) { - goto exit; - } - } - -#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) - /* Use the fast shortcut if available */ - if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { - ret = sli_short_cmac_operation(int_key, MBEDTLS_AES_BLOCK_SIZE * 8, - input, in_len, (uint8_t*)output); - } else -#endif - { - ret = psa_status_to_mbedtls( - MAC_ONESHOT_EN_FCT(&attr, - int_key, MBEDTLS_AES_BLOCK_SIZE, - PSA_ALG_CMAC, - input, in_len, - (uint8_t*)output, in_len, &olen) ); - } - - exit: - mbedtls_platform_zeroize(int_key, sizeof(int_key) ); - - return(ret); -} - -#endif /* MAC_IMPLEMENTATION_PRESENT */ - -#endif /* MBEDTLS_CMAC_C && MBEDTLS_CMAC_ALT */ +/***************************************************************************//** + * @file + * @brief AES-CMAC abstraction based on PSA accelerators + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of various functions in + * cmac.c, using the accelerators incorporated in devices from Silicon Labs. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined (MBEDTLS_CMAC_C) && defined(MBEDTLS_CMAC_ALT) + +#include "mbedtls/cmac.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#if defined(MBEDTLS_SELF_TEST) +#include +#define mbedtls_printf printf +#endif /* MBEDTLS_SELF_TEST */ +#endif /* MBEDTLS_PLATFORM_C */ + +#include "psa/crypto.h" + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define SLI_DEVICE_HAS_AES_192 +#define MAC_IMPLEMENTATION_PRESENT +#define MAC_SETUP_EN_FCT sli_se_transparent_mac_sign_setup +#define MAC_SETUP_DE_FCT sli_se_transparent_mac_verify_setup +#define MAC_UPDATE_FCT sli_se_transparent_mac_update +#define MAC_FINISH_EN_FCT sli_se_transparent_mac_sign_finish +#define MAC_FINISH_DE_FCT sli_se_transparent_mac_verify_finish +#define MAC_ABORT_FCT sli_se_transparent_mac_abort +#define MAC_ONESHOT_EN_FCT sli_se_transparent_mac_compute +#define MAC_ONESHOT_DE_FCT sli_se_transparent_mac_verify + +#if defined(RADIOAES_PRESENT) +#include "sli_protocol_crypto.h" +#endif +#elif defined(CRYPTO_PRESENT) +#include "sli_crypto_transparent_functions.h" +#define MAC_IMPLEMENTATION_PRESENT +#define MAC_SETUP_EN_FCT sli_crypto_transparent_mac_sign_setup +#define MAC_SETUP_DE_FCT sli_crypto_transparent_mac_verify_setup +#define MAC_UPDATE_FCT sli_crypto_transparent_mac_update +#define MAC_FINISH_EN_FCT sli_crypto_transparent_mac_sign_finish +#define MAC_FINISH_DE_FCT sli_crypto_transparent_mac_verify_finish +#define MAC_ABORT_FCT sli_crypto_transparent_mac_abort +#define MAC_ONESHOT_EN_FCT sli_crypto_transparent_mac_compute +#define MAC_ONESHOT_DE_FCT sli_crypto_transparent_mac_verify +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define SLI_DEVICE_HAS_AES_192 +#define MAC_IMPLEMENTATION_PRESENT +#define MAC_SETUP_EN_FCT sli_cryptoacc_transparent_mac_sign_setup +#define MAC_SETUP_DE_FCT sli_cryptoacc_transparent_mac_verify_setup +#define MAC_UPDATE_FCT sli_cryptoacc_transparent_mac_update +#define MAC_FINISH_EN_FCT sli_cryptoacc_transparent_mac_sign_finish +#define MAC_FINISH_DE_FCT sli_cryptoacc_transparent_mac_verify_finish +#define MAC_ABORT_FCT sli_cryptoacc_transparent_mac_abort +#define MAC_ONESHOT_EN_FCT sli_cryptoacc_transparent_mac_compute +#define MAC_ONESHOT_DE_FCT sli_cryptoacc_transparent_mac_verify +#endif + +#if defined(MAC_IMPLEMENTATION_PRESENT) + +#include + +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } +} + +static inline void sl_psa_set_key_type(psa_key_attributes_t *attributes, + psa_key_type_t type) +{ + /* Common case: quick path */ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = type; +} + +int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, + const unsigned char *key, size_t keybits) +{ + mbedtls_cipher_type_t type; + mbedtls_cmac_context_t *cmac_ctx; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || key == NULL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + type = (mbedtls_cipher_type_t)ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(type); + + switch ( type ) { + case MBEDTLS_CIPHER_AES_128_ECB: + psa_set_key_bits(&attr, 128); + break; + case MBEDTLS_CIPHER_AES_192_ECB: + #if defined(SLI_DEVICE_HAS_AES_192) + psa_set_key_bits(&attr, 192); + #else + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + break; + case MBEDTLS_CIPHER_AES_256_ECB: + psa_set_key_bits(&attr, 256); + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + if ( ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + /* Allocate CMAC context memory if it hasn't already been allocated */ + cmac_ctx = mbedtls_calloc(1, sizeof(struct mbedtls_cmac_context_t) ); + if ( cmac_ctx == NULL ) { + return(MBEDTLS_ERR_CIPHER_ALLOC_FAILED); + } + + ctx->MBEDTLS_PRIVATE(cmac_ctx) = cmac_ctx; + } else { + mbedtls_platform_zeroize(ctx->MBEDTLS_PRIVATE(cmac_ctx), sizeof(*ctx->MBEDTLS_PRIVATE(cmac_ctx)) ); + } + + return psa_status_to_mbedtls( + MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + &attr, + key, + keybits / 8U, + PSA_ALG_CMAC) ); +} + +int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, + const unsigned char *input, size_t ilen) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || input == NULL + || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + return psa_status_to_mbedtls( + MAC_UPDATE_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + input, + ilen) ); +} + +int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, + unsigned char *output) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL + || output == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + size_t olen = 0; + + return psa_status_to_mbedtls( + MAC_FINISH_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + output, + MBEDTLS_AES_BLOCK_SIZE, + &olen) ); +} + +int mbedtls_cipher_cmac_reset(mbedtls_cipher_context_t *ctx) +{ + if ( ctx == NULL || ctx->MBEDTLS_PRIVATE(cipher_info) == NULL || ctx->MBEDTLS_PRIVATE(cmac_ctx) == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + uint8_t key[32]; + size_t key_len; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + if ( ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len > sizeof(key) ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + /* Save the key to be able to restart the operation */ + memcpy(key, + ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key, + ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len); + key_len = ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx.cipher_mac.key_len; + psa_set_key_bits(&attr, key_len * 8); + + /* Abort and restart with the same key */ + MAC_ABORT_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx); + return psa_status_to_mbedtls( + MAC_SETUP_EN_FCT(&ctx->MBEDTLS_PRIVATE(cmac_ctx)->ctx, + &attr, + key, + key_len, + PSA_ALG_CMAC) ); +} + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) +/* For speeding up PBKDF2-CMAC, which needs a lot of iterations with small-size + * CMAC operations, we can dispatch these to the RADIOAES instance if there is + * one available. + * + * Function limitations: can only be used with AES-128 or AES-256, and needs to + * have as short as possible execution time to not block other time-sensitive + * operations (such as BLE RPA). Will always output a full CMAC (16 bytes). + * + * \param key Raw key bytes, \p keylen bytes long + * \param keylen Length of \p key in bytes, either 16 (AES-128) or 32 (AES-256) + * \param input Data bytes to calculate the CMAC over, length \p ilen bytes + * \param ilen Length in bytes of \p input + * \param output Output buffer for the calculated CMAC tag (16 bytes) + * + * \return \c 0 on success, MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED on failure + */ +static int sli_short_cmac_operation(const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output) +{ + sl_status_t status = sli_aes_cmac_radio(key, + keylen, + input, + ilen, + output); + if (status == SL_STATUS_OK) { + return 0; + } else { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} +#endif + +int mbedtls_cipher_cmac(const mbedtls_cipher_info_t *cipher_info, + const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output) +{ + if ( cipher_info == NULL || key == NULL || input == NULL || output == NULL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { + case MBEDTLS_CIPHER_AES_128_ECB: + if ( keylen != 128UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + case MBEDTLS_CIPHER_AES_192_ECB: + #if defined(SLI_DEVICE_HAS_AES_192) + if ( keylen != 192UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + #else + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + #endif + case MBEDTLS_CIPHER_AES_256_ECB: + if ( keylen != 256UL ) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( (keylen == 128UL || keylen == 256UL) && (ilen <= 2 * MBEDTLS_AES_BLOCK_SIZE) ) { + return sli_short_cmac_operation(key, keylen, + input, ilen, output); + } +#endif + + size_t olen = 0; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + + switch ( cipher_info->MBEDTLS_PRIVATE(type) ) { + case MBEDTLS_CIPHER_AES_128_ECB: + psa_set_key_bits(&attr, 128); + break; + case MBEDTLS_CIPHER_AES_192_ECB: + psa_set_key_bits(&attr, 192); + break; + case MBEDTLS_CIPHER_AES_256_ECB: + psa_set_key_bits(&attr, 256); + break; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + key, keylen / 8U, + PSA_ALG_CMAC, + input, ilen, + output, MBEDTLS_AES_BLOCK_SIZE, &olen) ); +} + +/* + * Implementation of AES-CMAC-PRF-128 defined in RFC 4615 + */ +int mbedtls_aes_cmac_prf_128(const unsigned char *key, size_t key_length, + const unsigned char *input, size_t in_len, + unsigned char output[16]) +{ + int ret; + unsigned char zero_key[MBEDTLS_AES_BLOCK_SIZE]; + unsigned char int_key[MBEDTLS_AES_BLOCK_SIZE]; + + if ( key == NULL || input == NULL || output == NULL ) { + return(MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA); + } + + size_t olen = 0; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + sl_psa_set_key_type(&attr, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attr, 128); + + if ( key_length == MBEDTLS_AES_BLOCK_SIZE ) { + /* Use key as is */ + memcpy(int_key, key, MBEDTLS_AES_BLOCK_SIZE); + } else { + memset(zero_key, 0, MBEDTLS_AES_BLOCK_SIZE); + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { + ret = sli_short_cmac_operation(zero_key, MBEDTLS_AES_BLOCK_SIZE * 8, + key, key_length, int_key); + } else +#endif + { + ret = psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + zero_key, MBEDTLS_AES_BLOCK_SIZE, + PSA_ALG_CMAC, + key, key_length, + int_key, MBEDTLS_AES_BLOCK_SIZE, &olen) ); + } + if ( ret != 0 ) { + goto exit; + } + } + +#if defined(RADIOAES_PRESENT) && defined(SEMAILBOX_PRESENT) + /* Use the fast shortcut if available */ + if ( key_length <= 2 * MBEDTLS_AES_BLOCK_SIZE ) { + ret = sli_short_cmac_operation(int_key, MBEDTLS_AES_BLOCK_SIZE * 8, + input, in_len, (uint8_t*)output); + } else +#endif + { + ret = psa_status_to_mbedtls( + MAC_ONESHOT_EN_FCT(&attr, + int_key, MBEDTLS_AES_BLOCK_SIZE, + PSA_ALG_CMAC, + input, in_len, + (uint8_t*)output, in_len, &olen) ); + } + + exit: + mbedtls_platform_zeroize(int_key, sizeof(int_key) ); + + return(ret); +} + +#endif /* MAC_IMPLEMENTATION_PRESENT */ + +#endif /* MBEDTLS_CMAC_C && MBEDTLS_CMAC_ALT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c index c7e2e46..625701f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c @@ -1,422 +1,422 @@ -/***************************************************************************//** - * @file - * @brief mbed TLS elliptic curve operations accelerated by PSA crypto drivers - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/** - * This file includes an alternative implementation of high-level ECDSA and ECDH - * functions from the mbed TLS API, using the relevant accelerators incorporated - * in devices from Silicon Labs. - * - * For Series-1 devices with a CRYPTO peripheral, see crypto_ecp.c. - * - * This alternative implementation calls the PSA Crypto drivers provided - * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. - */ - -#include - -#if defined(MBEDTLS_ECP_C) - -#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ - || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ - || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ - || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ - || defined(MBEDTLS_ECDSA_SIGN_ALT) - -#include "em_device.h" - -#if defined(SEMAILBOX_PRESENT) -#include "sli_se_transparent_functions.h" -#define ECC_IMPLEMENTATION_PRESENT -#define ECC_KEYGEN_FCT sli_se_transparent_generate_key -#define ECC_PUBKEY_FCT sli_se_transparent_export_public_key -#define ECDSA_SIGN_FCT sli_se_transparent_sign_hash -#define ECDSA_VERIFY_FCT sli_se_transparent_verify_hash -#define ECDH_DERIVE_FCT sli_se_transparent_key_agreement -#elif defined(CRYPTOACC_PRESENT) -#include "sli_cryptoacc_transparent_functions.h" -#define ECC_IMPLEMENTATION_PRESENT -#define ECC_KEYGEN_FCT sli_cryptoacc_transparent_generate_key -#define ECC_PUBKEY_FCT sli_cryptoacc_transparent_export_public_key -#define ECDSA_SIGN_FCT sli_cryptoacc_transparent_sign_hash -#define ECDSA_VERIFY_FCT sli_cryptoacc_transparent_verify_hash -#define ECDH_DERIVE_FCT sli_cryptoacc_transparent_key_agreement -#endif - -#include "mbedtls/ecdh.h" -#include "mbedtls/ecdsa.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/bignum.h" -#include "mbedtls/error.h" -#include "psa/crypto.h" - -// Parameter validation macros based on platform_util.h -#define ECDH_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) -#define ECDH_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - -#define ECDSA_VALIDATE_RET(cond) \ - MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) -#define ECDSA_VALIDATE(cond) \ - MBEDTLS_INTERNAL_VALIDATE(cond) - -#if defined(ECC_IMPLEMENTATION_PRESENT) -static int psa_status_to_mbedtls(psa_status_t status) -{ - switch ( status ) { - case PSA_SUCCESS: - return 0; - case PSA_ERROR_INVALID_SIGNATURE: - return MBEDTLS_ERR_ECP_VERIFY_FAILED; - case PSA_ERROR_HARDWARE_FAILURE: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - default: - return MBEDTLS_ERR_ERROR_GENERIC_ERROR; - } -} - -static int mbedtls_grp_to_psa_attr(mbedtls_ecp_group_id id, - psa_key_attributes_t *attr) -{ - switch (id) { - case MBEDTLS_ECP_DP_SECP192R1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); - psa_set_key_bits(attr, 192); - break; -#if defined(CRYPTOACC_PRESENT) - case MBEDTLS_ECP_DP_SECP224R1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); - psa_set_key_bits(attr, 224); - break; - case MBEDTLS_ECP_DP_SECP256K1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1); - psa_set_key_bits(attr, 256); - break; -#endif - case MBEDTLS_ECP_DP_SECP256R1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); - psa_set_key_bits(attr, 256); - break; - case MBEDTLS_ECP_DP_SECP384R1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); - psa_set_key_bits(attr, 384); - break; - case MBEDTLS_ECP_DP_SECP521R1: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); - psa_set_key_bits(attr, 521); - break; - case MBEDTLS_ECP_DP_CURVE25519: - attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_MONTGOMERY); - psa_set_key_bits(attr, 255); - break; - default: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } - return PSA_SUCCESS; -} -#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ - || defined(MBEDTLS_ECDSA_GENKEY_ALT) -static int ecc_keygen(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q) -{ - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - uint8_t keybuf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; - - psa_status_t status = psa_status_to_mbedtls( - mbedtls_grp_to_psa_attr(grp->id, &attr) ); - if ( status != PSA_SUCCESS ) { - return status; - } - - size_t keybytes; - status = psa_status_to_mbedtls( - ECC_KEYGEN_FCT(&attr, - keybuf, - sizeof(keybuf), - &keybytes) ); - - if ( status != PSA_SUCCESS ) { - return status; - } - - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { - mbedtls_mpi_read_binary_le(d, keybuf, keybytes); - } else { - mbedtls_mpi_read_binary(d, keybuf, keybytes); - } - - status = psa_status_to_mbedtls( - ECC_PUBKEY_FCT(&attr, - keybuf, - keybytes, - keybuf, - sizeof(keybuf), - &keybytes) ); - - if ( status != PSA_SUCCESS ) { - return status; - } - - if ( PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY ) { - mbedtls_mpi_read_binary_le(&Q->MBEDTLS_PRIVATE(X), keybuf, keybytes); - } else { - // The first byte is used to store uncompressed representation byte. - mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(X), keybuf + 1u, keybytes / 2); - mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(Y), keybuf + keybytes / 2 + 1u, keybytes / 2); - mbedtls_mpi_lset(&Q->MBEDTLS_PRIVATE(Z), 1); - } - - return status; -} -#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) - || defined(MBEDTLS_ECDSA_GENKEY_ALT) */ - -#if defined(MBEDTLS_ECDSA_GENKEY_ALT) -/* - * Generate key pair - */ -int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) -{ - /* PSA uses internal entropy */ - (void)f_rng; - (void)p_rng; - - ECDSA_VALIDATE_RET(ctx != NULL); - ECDSA_VALIDATE_RET(f_rng != NULL); - - mbedtls_ecp_group_load(&ctx->MBEDTLS_PRIVATE(grp), gid); - - return ecc_keygen(&ctx->MBEDTLS_PRIVATE(grp), &ctx->MBEDTLS_PRIVATE(d), &ctx->MBEDTLS_PRIVATE(Q)); -} -#endif /* MBEDTLS_ECDSA_GENKEY_ALT */ - -#if defined(MBEDTLS_ECDSA_SIGN_ALT) -int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, - const mbedtls_mpi *d, const unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) -{ - /* PSA uses internal entropy */ - (void)f_rng; - (void)p_rng; - - ECDSA_VALIDATE_RET(grp != NULL); - ECDSA_VALIDATE_RET(r != NULL); - ECDSA_VALIDATE_RET(s != NULL); - ECDSA_VALIDATE_RET(d != NULL); - ECDSA_VALIDATE_RET(f_rng != NULL); - ECDSA_VALIDATE_RET(buf != NULL || blen == 0); - - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - uint8_t key_signature_buf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; - - psa_status_t status = psa_status_to_mbedtls( - mbedtls_grp_to_psa_attr(grp->id, &attr)); - if ( status != PSA_SUCCESS ) { - return status; - } - psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_SIGN_HASH); - - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { - return PSA_ERROR_NOT_SUPPORTED; - } - - size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); - - // Make sure d is in range 1..n-1 - if ((mbedtls_mpi_cmp_int(d, 1) < 0) || (mbedtls_mpi_cmp_mpi(d, &grp->N) >= 0)) { - return MBEDTLS_ERR_ECP_INVALID_KEY; - } - - mbedtls_mpi_write_binary(d, key_signature_buf, keybytes); - - status = psa_status_to_mbedtls( - ECDSA_SIGN_FCT(&attr, - key_signature_buf, - keybytes, - PSA_ALG_ECDSA_ANY, - buf, - blen, - key_signature_buf, - sizeof(key_signature_buf), - &keybytes) ); - - if ( status != PSA_SUCCESS ) { - return status; - } - - mbedtls_mpi_read_binary(r, key_signature_buf, keybytes / 2); - mbedtls_mpi_read_binary(s, key_signature_buf + (keybytes / 2), keybytes / 2); - - return status; -} -#endif /* MBEDTLS_ECDSA_SIGN_ALT */ - -#if defined(MBEDTLS_ECDSA_VERIFY_ALT) -int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, - const unsigned char *buf, size_t blen, - const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s) -{ - ECDSA_VALIDATE_RET(grp != NULL); - ECDSA_VALIDATE_RET(Q != NULL); - ECDSA_VALIDATE_RET(r != NULL); - ECDSA_VALIDATE_RET(s != NULL); - ECDSA_VALIDATE_RET(buf != NULL || blen == 0); - - uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1] = { 0 }; - uint8_t signature[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - - psa_status_t status = psa_status_to_mbedtls( - mbedtls_grp_to_psa_attr(grp->id, &attr) ); - if ( status != PSA_SUCCESS ) { - return status; - } - psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_VERIFY_HASH); - - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { - return PSA_ERROR_NOT_SUPPORTED; - } - - attr.MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = - PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr))); - - size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); - - /* pull out signature info from mbedtls structures */ - mbedtls_mpi_write_binary(r, signature, keybytes); - mbedtls_mpi_write_binary(s, &signature[keybytes], keybytes); - - pub[0] = 0x04; // Uncompressed public key - mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), &pub[1u], keybytes); - mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), &pub[keybytes + 1u], keybytes); - - return psa_status_to_mbedtls( - ECDSA_VERIFY_FCT(&attr, - pub, - keybytes * 2 + 1u, - PSA_ALG_ECDSA_ANY, - buf, - blen, - signature, - keybytes * 2) ); -} -#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ - -#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) -int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng) -{ - /* PSA uses internal entropy */ - (void)f_rng; - (void)p_rng; - - ECDH_VALIDATE_RET(grp != NULL); - ECDH_VALIDATE_RET(d != NULL); - ECDH_VALIDATE_RET(Q != NULL); - ECDH_VALIDATE_RET(f_rng != NULL); - - return ecc_keygen(grp, d, Q); -} -#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) */ - -#if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) -int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, mbedtls_mpi *z, - const mbedtls_ecp_point *Q, const mbedtls_mpi *d, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng) -{ - /* PSA uses internal entropy */ - (void)f_rng; - (void)p_rng; - - ECDH_VALIDATE_RET(grp != NULL); - ECDH_VALIDATE_RET(Q != NULL); - ECDH_VALIDATE_RET(d != NULL); - ECDH_VALIDATE_RET(z != NULL); - - uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; - uint8_t priv[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; - psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; - - psa_status_t status = psa_status_to_mbedtls( - mbedtls_grp_to_psa_attr(grp->id, &attr) ); - if ( status != PSA_SUCCESS ) { - return status; - } - psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_DERIVE); - - size_t keylen = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); - size_t publen; - - /* pull out key info from mbedtls structures */ - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { - publen = keylen; - mbedtls_mpi_write_binary_le(d, priv, keylen); - mbedtls_mpi_write_binary_le(&Q->MBEDTLS_PRIVATE(X), pub, keylen); - } else { - publen = 2 * keylen + 1u; - mbedtls_mpi_write_binary(d, priv, keylen); - pub[0] = 0x04; // uncompressed public key - mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), pub + 1u, keylen); - mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), pub + keylen + 1u, keylen); - } - - status = psa_status_to_mbedtls( - ECDH_DERIVE_FCT(PSA_ALG_ECDH, - &attr, - priv, - keylen, - pub, - publen, - pub, - sizeof(pub), - &publen) ); - - if ( status != PSA_SUCCESS ) { - return status; - } - - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { - mbedtls_mpi_read_binary_le(z, pub, publen); - } else { - mbedtls_mpi_read_binary(z, pub, publen); - } - return status; -} -#endif /* #if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ - -#endif /* ECC_IMPLEMENTATION_PRESENT */ - -#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ - -#endif /* #if defined(MBEDTLS_ECP_C) */ +/***************************************************************************//** + * @file + * @brief mbed TLS elliptic curve operations accelerated by PSA crypto drivers + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/** + * This file includes an alternative implementation of high-level ECDSA and ECDH + * functions from the mbed TLS API, using the relevant accelerators incorporated + * in devices from Silicon Labs. + * + * For Series-1 devices with a CRYPTO peripheral, see crypto_ecp.c. + * + * This alternative implementation calls the PSA Crypto drivers provided + * by Silicon Labs. For details on these drivers, see \ref sl_psa_drivers. + */ + +#include + +#if defined(MBEDTLS_ECP_C) + +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) \ + || defined(MBEDTLS_ECDSA_VERIFY_ALT) \ + || defined(MBEDTLS_ECDSA_SIGN_ALT) + +#include "em_device.h" + +#if defined(SEMAILBOX_PRESENT) +#include "sli_se_transparent_functions.h" +#define ECC_IMPLEMENTATION_PRESENT +#define ECC_KEYGEN_FCT sli_se_transparent_generate_key +#define ECC_PUBKEY_FCT sli_se_transparent_export_public_key +#define ECDSA_SIGN_FCT sli_se_transparent_sign_hash +#define ECDSA_VERIFY_FCT sli_se_transparent_verify_hash +#define ECDH_DERIVE_FCT sli_se_transparent_key_agreement +#elif defined(CRYPTOACC_PRESENT) +#include "sli_cryptoacc_transparent_functions.h" +#define ECC_IMPLEMENTATION_PRESENT +#define ECC_KEYGEN_FCT sli_cryptoacc_transparent_generate_key +#define ECC_PUBKEY_FCT sli_cryptoacc_transparent_export_public_key +#define ECDSA_SIGN_FCT sli_cryptoacc_transparent_sign_hash +#define ECDSA_VERIFY_FCT sli_cryptoacc_transparent_verify_hash +#define ECDH_DERIVE_FCT sli_cryptoacc_transparent_key_agreement +#endif + +#include "mbedtls/ecdh.h" +#include "mbedtls/ecdsa.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/bignum.h" +#include "mbedtls/error.h" +#include "psa/crypto.h" + +// Parameter validation macros based on platform_util.h +#define ECDH_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) +#define ECDH_VALIDATE(cond) \ + MBEDTLS_INTERNAL_VALIDATE(cond) + +#define ECDSA_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET(cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA) +#define ECDSA_VALIDATE(cond) \ + MBEDTLS_INTERNAL_VALIDATE(cond) + +#if defined(ECC_IMPLEMENTATION_PRESENT) +static int psa_status_to_mbedtls(psa_status_t status) +{ + switch ( status ) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_INVALID_SIGNATURE: + return MBEDTLS_ERR_ECP_VERIFY_FAILED; + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + default: + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } +} + +static int mbedtls_grp_to_psa_attr(mbedtls_ecp_group_id id, + psa_key_attributes_t *attr) +{ + switch (id) { + case MBEDTLS_ECP_DP_SECP192R1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 192); + break; +#if defined(CRYPTOACC_PRESENT) + case MBEDTLS_ECP_DP_SECP224R1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 224); + break; + case MBEDTLS_ECP_DP_SECP256K1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1); + psa_set_key_bits(attr, 256); + break; +#endif + case MBEDTLS_ECP_DP_SECP256R1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 256); + break; + case MBEDTLS_ECP_DP_SECP384R1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 384); + break; + case MBEDTLS_ECP_DP_SECP521R1: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1); + psa_set_key_bits(attr, 521); + break; + case MBEDTLS_ECP_DP_CURVE25519: + attr->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_MONTGOMERY); + psa_set_key_bits(attr, 255); + break; + default: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + return PSA_SUCCESS; +} +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) \ + || defined(MBEDTLS_ECDSA_GENKEY_ALT) +static int ecc_keygen(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q) +{ + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + uint8_t keybuf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + + size_t keybytes; + status = psa_status_to_mbedtls( + ECC_KEYGEN_FCT(&attr, + keybuf, + sizeof(keybuf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + mbedtls_mpi_read_binary_le(d, keybuf, keybytes); + } else { + mbedtls_mpi_read_binary(d, keybuf, keybytes); + } + + status = psa_status_to_mbedtls( + ECC_PUBKEY_FCT(&attr, + keybuf, + keybytes, + keybuf, + sizeof(keybuf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if ( PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY ) { + mbedtls_mpi_read_binary_le(&Q->MBEDTLS_PRIVATE(X), keybuf, keybytes); + } else { + // The first byte is used to store uncompressed representation byte. + mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(X), keybuf + 1u, keybytes / 2); + mbedtls_mpi_read_binary(&Q->MBEDTLS_PRIVATE(Y), keybuf + keybytes / 2 + 1u, keybytes / 2); + mbedtls_mpi_lset(&Q->MBEDTLS_PRIVATE(Z), 1); + } + + return status; +} +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) + || defined(MBEDTLS_ECDSA_GENKEY_ALT) */ + +#if defined(MBEDTLS_ECDSA_GENKEY_ALT) +/* + * Generate key pair + */ +int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + ECDSA_VALIDATE_RET(ctx != NULL); + ECDSA_VALIDATE_RET(f_rng != NULL); + + mbedtls_ecp_group_load(&ctx->MBEDTLS_PRIVATE(grp), gid); + + return ecc_keygen(&ctx->MBEDTLS_PRIVATE(grp), &ctx->MBEDTLS_PRIVATE(d), &ctx->MBEDTLS_PRIVATE(Q)); +} +#endif /* MBEDTLS_ECDSA_GENKEY_ALT */ + +#if defined(MBEDTLS_ECDSA_SIGN_ALT) +int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + ECDSA_VALIDATE_RET(grp != NULL); + ECDSA_VALIDATE_RET(r != NULL); + ECDSA_VALIDATE_RET(s != NULL); + ECDSA_VALIDATE_RET(d != NULL); + ECDSA_VALIDATE_RET(f_rng != NULL); + ECDSA_VALIDATE_RET(buf != NULL || blen == 0); + + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + uint8_t key_signature_buf[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr)); + if ( status != PSA_SUCCESS ) { + return status; + } + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_SIGN_HASH); + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + return PSA_ERROR_NOT_SUPPORTED; + } + + size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + + // Make sure d is in range 1..n-1 + if ((mbedtls_mpi_cmp_int(d, 1) < 0) || (mbedtls_mpi_cmp_mpi(d, &grp->N) >= 0)) { + return MBEDTLS_ERR_ECP_INVALID_KEY; + } + + mbedtls_mpi_write_binary(d, key_signature_buf, keybytes); + + status = psa_status_to_mbedtls( + ECDSA_SIGN_FCT(&attr, + key_signature_buf, + keybytes, + PSA_ALG_ECDSA_ANY, + buf, + blen, + key_signature_buf, + sizeof(key_signature_buf), + &keybytes) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + mbedtls_mpi_read_binary(r, key_signature_buf, keybytes / 2); + mbedtls_mpi_read_binary(s, key_signature_buf + (keybytes / 2), keybytes / 2); + + return status; +} +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ + +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) +int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s) +{ + ECDSA_VALIDATE_RET(grp != NULL); + ECDSA_VALIDATE_RET(Q != NULL); + ECDSA_VALIDATE_RET(r != NULL); + ECDSA_VALIDATE_RET(s != NULL); + ECDSA_VALIDATE_RET(buf != NULL || blen == 0); + + uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1] = { 0 }; + uint8_t signature[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_VERIFY_HASH); + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + return PSA_ERROR_NOT_SUPPORTED; + } + + attr.MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = + PSA_KEY_TYPE_ECC_PUBLIC_KEY(PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr))); + + size_t keybytes = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + + /* pull out signature info from mbedtls structures */ + mbedtls_mpi_write_binary(r, signature, keybytes); + mbedtls_mpi_write_binary(s, &signature[keybytes], keybytes); + + pub[0] = 0x04; // Uncompressed public key + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), &pub[1u], keybytes); + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), &pub[keybytes + 1u], keybytes); + + return psa_status_to_mbedtls( + ECDSA_VERIFY_FCT(&attr, + pub, + keybytes * 2 + 1u, + PSA_ALG_ECDSA_ANY, + buf, + blen, + signature, + keybytes * 2) ); +} +#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ + +#if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) +int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + ECDH_VALIDATE_RET(grp != NULL); + ECDH_VALIDATE_RET(d != NULL); + ECDH_VALIDATE_RET(Q != NULL); + ECDH_VALIDATE_RET(f_rng != NULL); + + return ecc_keygen(grp, d, Q); +} +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) */ + +#if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) +int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng) +{ + /* PSA uses internal entropy */ + (void)f_rng; + (void)p_rng; + + ECDH_VALIDATE_RET(grp != NULL); + ECDH_VALIDATE_RET(Q != NULL); + ECDH_VALIDATE_RET(d != NULL); + ECDH_VALIDATE_RET(z != NULL); + + uint8_t pub[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2 + 1u] = { 0 }; + uint8_t priv[((((MBEDTLS_ECP_MAX_BYTES) +3) / 4) * 4) * 2] = { 0 }; + psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT; + + psa_status_t status = psa_status_to_mbedtls( + mbedtls_grp_to_psa_attr(grp->id, &attr) ); + if ( status != PSA_SUCCESS ) { + return status; + } + psa_set_key_usage_flags(&attr, PSA_KEY_USAGE_DERIVE); + + size_t keylen = PSA_BITS_TO_BYTES(psa_get_key_bits(&attr)); + size_t publen; + + /* pull out key info from mbedtls structures */ + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + publen = keylen; + mbedtls_mpi_write_binary_le(d, priv, keylen); + mbedtls_mpi_write_binary_le(&Q->MBEDTLS_PRIVATE(X), pub, keylen); + } else { + publen = 2 * keylen + 1u; + mbedtls_mpi_write_binary(d, priv, keylen); + pub[0] = 0x04; // uncompressed public key + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(X), pub + 1u, keylen); + mbedtls_mpi_write_binary(&Q->MBEDTLS_PRIVATE(Y), pub + keylen + 1u, keylen); + } + + status = psa_status_to_mbedtls( + ECDH_DERIVE_FCT(PSA_ALG_ECDH, + &attr, + priv, + keylen, + pub, + publen, + pub, + sizeof(pub), + &publen) ); + + if ( status != PSA_SUCCESS ) { + return status; + } + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(&attr)) == PSA_ECC_FAMILY_MONTGOMERY) { + mbedtls_mpi_read_binary_le(z, pub, publen); + } else { + mbedtls_mpi_read_binary(z, pub, publen); + } + return status; +} +#endif /* #if defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ + +#endif /* ECC_IMPLEMENTATION_PRESENT */ + +#endif /* #if defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) */ + +#endif /* #if defined(MBEDTLS_ECP_C) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c index f34c85e..aab9aa2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c @@ -1,117 +1,117 @@ -/***************************************************************************//** - * @file - * @brief Initialize the Silicon Labs platform integration of mbedTLS. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_mbedtls.h" -#include "sl_assert.h" -#include "mbedtls/build_info.h" -#if !defined(SL_TRUSTZONE_NONSECURE) -#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) -#include "sl_se_manager.h" -#endif -#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - #include "cryptoacc_management.h" -#endif -#endif // #if !defined(SL_TRUSTZONE_NONSECURE) - -#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#if defined(MBEDTLS_PSA_CRYPTO_C) -#include "cmsis_os2.h" -#include -static volatile bool mbedtls_psa_slots_mutex_inited = false; - -/** - * \brief Lock all task switches - * - * \return Previous lock state - * - */ -static inline int32_t lock_task_switches(void) -{ - int32_t kernel_lock_state = 0; - osKernelState_t kernel_state = osKernelGetState(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - kernel_lock_state = osKernelLock(); - } - return kernel_lock_state; -} - -/** - * \brief Restores the previous lock state - */ -static inline void restore_lock_state(int32_t kernel_lock_state) -{ - osKernelState_t kernel_state = osKernelGetState(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - if (osKernelRestoreLock(kernel_lock_state) < 0) { - EFM_ASSERT(false); - } - } -} - -#endif // defined(MBEDTLS_PSA_CRYPTO_C) -#endif // defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) - -void sl_mbedtls_init(void) -{ -#if !defined(SL_TRUSTZONE_NONSECURE) - -#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) - /* Initialize the SE Manager including the SE lock. - No need for critical region here since sl_se_init implements one. */ - sl_status_t ret; - ret = sl_se_init(); - EFM_ASSERT(ret == SL_STATUS_OK); -#endif - -#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) - // Set up SCA countermeasures in hardware - cryptoacc_initialize_countermeasures(); -#endif // SILICON_LABS_32B_SERIES_2_CONFIG > 2 - -#endif // #if !defined(SL_TRUSTZONE_NONSECURE) - -#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) - mbedtls_threading_set_alt(&THREADING_InitMutex, - &THREADING_FreeMutex, - &THREADING_TakeMutexBlocking, - &THREADING_GiveMutex); - #if defined(MBEDTLS_PSA_CRYPTO_C) - // Initialize mutex for PSA slot access in psa_crypto_slot_management.c - if (!mbedtls_psa_slots_mutex_inited) { - int32_t kernel_lock_state = lock_task_switches(); - if (!mbedtls_psa_slots_mutex_inited) { - mbedtls_mutex_init(&mbedtls_psa_slots_mutex); - mbedtls_psa_slots_mutex_inited = true; - } - restore_lock_state(kernel_lock_state); - } - #endif // #if defined(MBEDTLS_PSA_CRYPTO_C) -#endif // #if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) -} +/***************************************************************************//** + * @file + * @brief Initialize the Silicon Labs platform integration of mbedTLS. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_mbedtls.h" +#include "sl_assert.h" +#include "mbedtls/build_info.h" +#if !defined(SL_TRUSTZONE_NONSECURE) +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) +#include "sl_se_manager.h" +#endif +#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + #include "cryptoacc_management.h" +#endif +#endif // #if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#if defined(MBEDTLS_PSA_CRYPTO_C) +#include "cmsis_os2.h" +#include +static volatile bool mbedtls_psa_slots_mutex_inited = false; + +/** + * \brief Lock all task switches + * + * \return Previous lock state + * + */ +static inline int32_t lock_task_switches(void) +{ + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = osKernelLock(); + } + return kernel_lock_state; +} + +/** + * \brief Restores the previous lock state + */ +static inline void restore_lock_state(int32_t kernel_lock_state) +{ + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (osKernelRestoreLock(kernel_lock_state) < 0) { + EFM_ASSERT(false); + } + } +} + +#endif // defined(MBEDTLS_PSA_CRYPTO_C) +#endif // defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) + +void sl_mbedtls_init(void) +{ +#if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(SEMAILBOX_PRESENT) || defined(CRYPTOACC_PRESENT) + /* Initialize the SE Manager including the SE lock. + No need for critical region here since sl_se_init implements one. */ + sl_status_t ret; + ret = sl_se_init(); + EFM_ASSERT(ret == SL_STATUS_OK); +#endif + +#if defined(CRYPTOACC_PRESENT) && (_SILICON_LABS_32B_SERIES_2_CONFIG > 2) + // Set up SCA countermeasures in hardware + cryptoacc_initialize_countermeasures(); +#endif // SILICON_LABS_32B_SERIES_2_CONFIG > 2 + +#endif // #if !defined(SL_TRUSTZONE_NONSECURE) + +#if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) + mbedtls_threading_set_alt(&THREADING_InitMutex, + &THREADING_FreeMutex, + &THREADING_TakeMutexBlocking, + &THREADING_GiveMutex); + #if defined(MBEDTLS_PSA_CRYPTO_C) + // Initialize mutex for PSA slot access in psa_crypto_slot_management.c + if (!mbedtls_psa_slots_mutex_inited) { + int32_t kernel_lock_state = lock_task_switches(); + if (!mbedtls_psa_slots_mutex_inited) { + mbedtls_mutex_init(&mbedtls_psa_slots_mutex); + mbedtls_psa_slots_mutex_inited = true; + } + restore_lock_state(kernel_lock_state); + } + #endif // #if defined(MBEDTLS_PSA_CRYPTO_C) +#endif // #if defined(MBEDTLS_THREADING_ALT) && defined(MBEDTLS_THREADING_C) +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c index b366727..16ae53e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c @@ -1,77 +1,77 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto utility functions. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_psa_crypto.h" - -#include "sli_psa_driver_features.h" - -// ----------------------------------------------------------------------------- -// Global functions - -void sl_psa_set_key_lifetime_with_location_preference( - psa_key_attributes_t *attributes, - psa_key_persistence_t persistence, - psa_key_location_t preferred_location) -{ - psa_key_location_t selected_location = PSA_KEY_LOCATION_LOCAL_STORAGE; - - switch (preferred_location) { - // The underlying values for wrapped and built-in keys are the same. In - // order to avoid compiler errors, we therefore use #elif in order to make - // sure that we do not get identical switch labels. - #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) - case SL_PSA_KEY_LOCATION_WRAPPED: - selected_location = SL_PSA_KEY_LOCATION_WRAPPED; - break; - #elif defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) - case SL_PSA_KEY_LOCATION_BUILTIN: - selected_location = SL_PSA_KEY_LOCATION_BUILTIN; - break; - #endif - - default: - // Use the already set PSA_KEY_LOCATION_LOCAL_STORAGE. - break; - } - - psa_key_lifetime_t lifetime = - PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, - selected_location); - psa_set_key_lifetime(attributes, lifetime); -} - -psa_key_location_t sl_psa_get_most_secure_key_location(void) -{ - #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) - return SL_PSA_KEY_LOCATION_WRAPPED; - #else - return PSA_KEY_LOCATION_LOCAL_STORAGE; - #endif -} +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_psa_crypto.h" + +#include "sli_psa_driver_features.h" + +// ----------------------------------------------------------------------------- +// Global functions + +void sl_psa_set_key_lifetime_with_location_preference( + psa_key_attributes_t *attributes, + psa_key_persistence_t persistence, + psa_key_location_t preferred_location) +{ + psa_key_location_t selected_location = PSA_KEY_LOCATION_LOCAL_STORAGE; + + switch (preferred_location) { + // The underlying values for wrapped and built-in keys are the same. In + // order to avoid compiler errors, we therefore use #elif in order to make + // sure that we do not get identical switch labels. + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case SL_PSA_KEY_LOCATION_WRAPPED: + selected_location = SL_PSA_KEY_LOCATION_WRAPPED; + break; + #elif defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) + case SL_PSA_KEY_LOCATION_BUILTIN: + selected_location = SL_PSA_KEY_LOCATION_BUILTIN; + break; + #endif + + default: + // Use the already set PSA_KEY_LOCATION_LOCAL_STORAGE. + break; + } + + psa_key_lifetime_t lifetime = + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, + selected_location); + psa_set_key_lifetime(attributes, lifetime); +} + +psa_key_location_t sl_psa_get_most_secure_key_location(void) +{ + #if defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + return SL_PSA_KEY_LOCATION_WRAPPED; + #else + return PSA_KEY_LOCATION_LOCAL_STORAGE; + #endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c index 7d8cda6..36f3166 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c @@ -1,117 +1,117 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs internal PSA Crypto utility functions. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_crypto.h" - -#include "psa/crypto.h" - -#include "mbedtls/aes.h" -#include "mbedtls/ccm.h" -#include "mbedtls/cipher.h" -#include "mbedtls/ctr_drbg.h" -#include "mbedtls/entropy.h" -#include "mbedtls/md.h" -#include "mbedtls/nist_kw.h" -#include "mbedtls/pk.h" -#include "mbedtls/sha1.h" -#include "mbedtls/sha256.h" -#include "mbedtls/ssl.h" -#include "mbedtls/ssl_cookie.h" -#include "mbedtls/x509_crt.h" - -// ----------------------------------------------------------------------------- -// Public function definitions - -size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type) -{ - switch (ctx_type) { - case SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t): - return sizeof(psa_hash_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t): - return sizeof(psa_cipher_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t): - return sizeof(psa_mac_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t): - return sizeof(psa_aead_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t): - return sizeof(psa_key_derivation_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t): - return sizeof(psa_pake_operation_t); - case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t): - return sizeof(psa_key_attributes_t); - default: - return 0; - } -} - -size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type) -{ - switch (ctx_type) { - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context): - return sizeof(mbedtls_aes_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context): - return sizeof(mbedtls_ccm_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t): - return sizeof(mbedtls_cipher_context_t); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context): - return sizeof(mbedtls_ctr_drbg_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context): - return sizeof(mbedtls_entropy_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t): - return sizeof(mbedtls_md_context_t); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context): - return sizeof(mbedtls_nist_kw_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context): - return sizeof(mbedtls_pk_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context): - return sizeof(mbedtls_sha1_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context): - return sizeof(mbedtls_sha256_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config): - return sizeof(mbedtls_ssl_config); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context): - return sizeof(mbedtls_ssl_context); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx): - return sizeof(mbedtls_ssl_cookie_ctx); - case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt): - return sizeof(mbedtls_x509_crt); - default: - return 0; - } -} - -bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id) -{ - bool is_persistent_zigbee_key = key_id >= SLI_PSA_KEY_ID_RANGE_ZIGBEE_START - && key_id <= SLI_PSA_KEY_ID_RANGE_ZIGBEE_END; - bool is_persistent_thread_key = key_id >= SLI_PSA_KEY_ID_RANGE_THREAD_START - && key_id <= SLI_PSA_KEY_ID_RANGE_THREAD_END; - return (is_persistent_zigbee_key || is_persistent_thread_key); -} +/***************************************************************************//** + * @file + * @brief Silicon Labs internal PSA Crypto utility functions. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_crypto.h" + +#include "psa/crypto.h" + +#include "mbedtls/aes.h" +#include "mbedtls/ccm.h" +#include "mbedtls/cipher.h" +#include "mbedtls/ctr_drbg.h" +#include "mbedtls/entropy.h" +#include "mbedtls/md.h" +#include "mbedtls/nist_kw.h" +#include "mbedtls/pk.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/ssl.h" +#include "mbedtls/ssl_cookie.h" +#include "mbedtls/x509_crt.h" + +// ----------------------------------------------------------------------------- +// Public function definitions + +size_t sli_psa_context_get_size(sli_psa_context_name_t ctx_type) +{ + switch (ctx_type) { + case SLI_PSA_CONTEXT_ENUM_NAME(psa_hash_operation_t): + return sizeof(psa_hash_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_cipher_operation_t): + return sizeof(psa_cipher_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_mac_operation_t): + return sizeof(psa_mac_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_aead_operation_t): + return sizeof(psa_aead_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_derivation_operation_t): + return sizeof(psa_key_derivation_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_pake_operation_t): + return sizeof(psa_pake_operation_t); + case SLI_PSA_CONTEXT_ENUM_NAME(psa_key_attributes_t): + return sizeof(psa_key_attributes_t); + default: + return 0; + } +} + +size_t sli_mbedtls_context_get_size(sli_mbedtls_context_name_t ctx_type) +{ + switch (ctx_type) { + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_aes_context): + return sizeof(mbedtls_aes_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ccm_context): + return sizeof(mbedtls_ccm_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_cipher_context_t): + return sizeof(mbedtls_cipher_context_t); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ctr_drbg_context): + return sizeof(mbedtls_ctr_drbg_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_entropy_context): + return sizeof(mbedtls_entropy_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_md_context_t): + return sizeof(mbedtls_md_context_t); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_nist_kw_context): + return sizeof(mbedtls_nist_kw_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_pk_context): + return sizeof(mbedtls_pk_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha1_context): + return sizeof(mbedtls_sha1_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_sha256_context): + return sizeof(mbedtls_sha256_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_config): + return sizeof(mbedtls_ssl_config); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_context): + return sizeof(mbedtls_ssl_context); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_ssl_cookie_ctx): + return sizeof(mbedtls_ssl_cookie_ctx); + case SLI_MBEDTLS_CONTEXT_ENUM_NAME(mbedtls_x509_crt): + return sizeof(mbedtls_x509_crt); + default: + return 0; + } +} + +bool sli_psa_key_is_unconditionally_copyable(psa_key_id_t key_id) +{ + bool is_persistent_zigbee_key = key_id >= SLI_PSA_KEY_ID_RANGE_ZIGBEE_START + && key_id <= SLI_PSA_KEY_ID_RANGE_ZIGBEE_END; + bool is_persistent_thread_key = key_id >= SLI_PSA_KEY_ID_RANGE_THREAD_START + && key_id <= SLI_PSA_KEY_ID_RANGE_THREAD_END; + return (is_persistent_zigbee_key || is_persistent_thread_key); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h index 73a0eee..d5f6084 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto.h @@ -1,205 +1,205 @@ -/***************************************************************************//** - * @file - * @brief Accelerated cryptographic primitives using the CRYPTO and RADIOAES - * peripherals, for series-1 and series-2 respectively. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SLI_PROTOCOL_CRYPTO_H -#define SLI_PROTOCOL_CRYPTO_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/***************************************************************************//** - * @addtogroup sli_protocol_crypto - * @brief Accelerated cryptographic primitives using the CRYPTO and RADIOAES - * peripherals, for series-1 and series-2 respectively. - * @{ - ******************************************************************************/ - -#include "sl_status.h" -#include "em_device.h" -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @brief AES-CTR block encryption/decryption optimized for radio - * - * @param key AES key - * @param keybits must be 128 or 256 - * @param input 16-byte input block - * @param iv_in 16-byte counter/IV starting value - * @param iv_out 16-byte counter/IV output after block round - * @param output 16-byte output block - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, - unsigned int keybits, - const unsigned char input[16], - const unsigned char iv_in[16], - volatile unsigned char iv_out[16], - volatile unsigned char output[16]); - -/***************************************************************************//** - * @brief AES-ECB block encryption/decryption optimized for radio - * - * @param encrypt true for encryption, false for decryption - * @param key AES key - * @param keybits must be 128 or 256 - * @param input 16-byte input block - * @param output 16-byte output block - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, - const unsigned char *key, - unsigned int keybits, - const unsigned char input[16], - volatile unsigned char output[16]); - -#if defined(RADIOAES_PRESENT) -/***************************************************************************//** - * @brief AES-CMAC calculation optimized for radio - * - * @param key AES key - * @param keybits Must be 128 or 256 - * @param input Input buffer containing the message to be signed - * @param length Amount of bytes in the input buffer - * @param output 16-byte output block for calculated CMAC - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_aes_cmac_radio(const unsigned char *key, - unsigned int keybits, - const unsigned char *input, - unsigned int length, - volatile unsigned char output[16]); - -/***************************************************************************//** - * @brief Seeds the AES mask. It is recommended to call this function - during initialization in order to avoid taking the potential - hit of requesting RNG output in an IRQ context. - ******************************************************************************/ -void sli_aes_seed_mask(void); -#endif - -/***************************************************************************//** - * @brief CCM buffer authenticated decryption optimized for BLE - * - * @param data Input/output buffer of payload data of BLE packet - * @param length length of input data - * @param iv nonce (initialization vector) - * must be 13 bytes - * @param header header of BLE packet (1 byte) - * @param tag authentication tag of BLE packet (4 bytes) - * - * @return SL_STATUS_OK if successful and authenticated, - * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, - * relevant status code on other error - ******************************************************************************/ -sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, - size_t length, - const unsigned char *key, - const unsigned char *iv, - unsigned char header, - unsigned char *tag); - -/***************************************************************************//** - * @brief CCM buffer encryption optimized for BLE - * - * @param data Input/output buffer of payload data of BLE packet - * @param length length of input data - * @param iv nonce (initialization vector) - * must be 13 bytes - * @param header header of BLE packet (1 byte) - * @param tag buffer where the BLE packet tag (4 bytes) will be written - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, - size_t length, - const unsigned char *key, - const unsigned char *iv, - unsigned char header, - unsigned char *tag); - -/***************************************************************************//** - * @brief CCM buffer authenticated decryption optimized for Zigbee - * - * @param data Input/output buffer of payload data (decrypt-in-place) - * @param length length of input data - * @param iv nonce (initialization vector) - * must be 13 bytes - * @param aad Input buffer of Additional Authenticated Data - * @param aad_len Length of buffer @p aad - * @param tag authentication tag - * @param tag_len Length of authentication tag - * - * @return SL_STATUS_OK if successful and authenticated, - * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, - * relevant status code on other error - ******************************************************************************/ -sl_status_t sli_ccm_zigbee(bool encrypt, - const unsigned char *data_in, - unsigned char *data_out, - size_t length, - const unsigned char *key, - const unsigned char *iv, - const unsigned char *aad, - size_t aad_len, - unsigned char *tag, - size_t tag_len); - -/***************************************************************************//** - * @brief Process a table of BLE RPA device keys and look for a - * match against the supplied hash - * - * @param keytable Pointer to an array of AES-128 keys, corresponding to the - * per-device key in the BLE RPA process - * @param keymask Bitmask indicating with key indices in keytable are valid - * @param prand 24-bit BLE nonce to encrypt with each key and match against hash - * @param hash BLE RPA hash to match against (last 24 bits of AES result) - * - * @return 0-based index of matching key if a match is found, -1 for no match. - ******************************************************************************/ -int sli_process_ble_rpa(const unsigned char keytable[], - uint32_t keymask, - uint32_t prand, - uint32_t hash); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sli_protocol_crypto) -/// @endcond -#endif // SLI_PROTOCOL_CRYPTO_H +/***************************************************************************//** + * @file + * @brief Accelerated cryptographic primitives using the CRYPTO and RADIOAES + * peripherals, for series-1 and series-2 respectively. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_PROTOCOL_CRYPTO_H +#define SLI_PROTOCOL_CRYPTO_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * @addtogroup sli_protocol_crypto + * @brief Accelerated cryptographic primitives using the CRYPTO and RADIOAES + * peripherals, for series-1 and series-2 respectively. + * @{ + ******************************************************************************/ + +#include "sl_status.h" +#include "em_device.h" +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @brief AES-CTR block encryption/decryption optimized for radio + * + * @param key AES key + * @param keybits must be 128 or 256 + * @param input 16-byte input block + * @param iv_in 16-byte counter/IV starting value + * @param iv_out 16-byte counter/IV output after block round + * @param output 16-byte output block + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, + unsigned int keybits, + const unsigned char input[16], + const unsigned char iv_in[16], + volatile unsigned char iv_out[16], + volatile unsigned char output[16]); + +/***************************************************************************//** + * @brief AES-ECB block encryption/decryption optimized for radio + * + * @param encrypt true for encryption, false for decryption + * @param key AES key + * @param keybits must be 128 or 256 + * @param input 16-byte input block + * @param output 16-byte output block + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, + const unsigned char *key, + unsigned int keybits, + const unsigned char input[16], + volatile unsigned char output[16]); + +#if defined(RADIOAES_PRESENT) +/***************************************************************************//** + * @brief AES-CMAC calculation optimized for radio + * + * @param key AES key + * @param keybits Must be 128 or 256 + * @param input Input buffer containing the message to be signed + * @param length Amount of bytes in the input buffer + * @param output 16-byte output block for calculated CMAC + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_aes_cmac_radio(const unsigned char *key, + unsigned int keybits, + const unsigned char *input, + unsigned int length, + volatile unsigned char output[16]); + +/***************************************************************************//** + * @brief Seeds the AES mask. It is recommended to call this function + during initialization in order to avoid taking the potential + hit of requesting RNG output in an IRQ context. + ******************************************************************************/ +void sli_aes_seed_mask(void); +#endif + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for BLE + * + * @param data Input/output buffer of payload data of BLE packet + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param header header of BLE packet (1 byte) + * @param tag authentication tag of BLE packet (4 bytes) + * + * @return SL_STATUS_OK if successful and authenticated, + * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, + * relevant status code on other error + ******************************************************************************/ +sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, + size_t length, + const unsigned char *key, + const unsigned char *iv, + unsigned char header, + unsigned char *tag); + +/***************************************************************************//** + * @brief CCM buffer encryption optimized for BLE + * + * @param data Input/output buffer of payload data of BLE packet + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param header header of BLE packet (1 byte) + * @param tag buffer where the BLE packet tag (4 bytes) will be written + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, + size_t length, + const unsigned char *key, + const unsigned char *iv, + unsigned char header, + unsigned char *tag); + +/***************************************************************************//** + * @brief CCM buffer authenticated decryption optimized for Zigbee + * + * @param data Input/output buffer of payload data (decrypt-in-place) + * @param length length of input data + * @param iv nonce (initialization vector) + * must be 13 bytes + * @param aad Input buffer of Additional Authenticated Data + * @param aad_len Length of buffer @p aad + * @param tag authentication tag + * @param tag_len Length of authentication tag + * + * @return SL_STATUS_OK if successful and authenticated, + * SL_STATUS_INVALID_SIGNATURE if tag does not match payload, + * relevant status code on other error + ******************************************************************************/ +sl_status_t sli_ccm_zigbee(bool encrypt, + const unsigned char *data_in, + unsigned char *data_out, + size_t length, + const unsigned char *key, + const unsigned char *iv, + const unsigned char *aad, + size_t aad_len, + unsigned char *tag, + size_t tag_len); + +/***************************************************************************//** + * @brief Process a table of BLE RPA device keys and look for a + * match against the supplied hash + * + * @param keytable Pointer to an array of AES-128 keys, corresponding to the + * per-device key in the BLE RPA process + * @param keymask Bitmask indicating with key indices in keytable are valid + * @param prand 24-bit BLE nonce to encrypt with each key and match against hash + * @param hash BLE RPA hash to match against (last 24 bits of AES result) + * + * @return 0-based index of matching key if a match is found, -1 for no match. + ******************************************************************************/ +int sli_process_ble_rpa(const unsigned char keytable[], + uint32_t keymask, + uint32_t prand, + uint32_t hash); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sli_protocol_crypto) +/// @endcond +#endif // SLI_PROTOCOL_CRYPTO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c index 6e74ca7..4c63fb1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c @@ -1,864 +1,864 @@ -/***************************************************************************//** - * @file - * @brief Accelerated cryptographic primitives using the RADIOAES peripheral. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_device.h" - -#if defined(RADIOAES_PRESENT) -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include "sli_radioaes_management.h" -#include "sli_protocol_crypto.h" -#include "em_core.h" - -#define AES_BLOCK_BYTES 16U -#define AES_128_KEY_BYTES 16U -#define AES_256_KEY_BYTES 32U - -#define RADIOAES_CONFIG_BYTES 4U - -#ifndef RADIOAES_BLE_RPA_MAX_KEYS -#define RADIOAES_BLE_RPA_MAX_KEYS 32 -#endif - -/// value for sli_radioaes_dma_sg_descr.tag to direct data to parameters -#define DMA_SG_TAG_ISCONFIG 0x00000010 -/// value for sli_radioaes_dma_sg_descr.tag to direct data to processing -#define DMA_SG_TAG_ISDATA 0x00000000 -/// value for sli_radioaes_dma_sg_descr.tag specifying data as last -#define DMA_SG_TAG_ISLAST 0x00000020 - -/// macro to set the offset in the configuration for sli_radioaes_dma_sg_descr.tag -#define DMA_SG_TAG_SETCFGOFFSET(a) ((((a) & 0xFF) << 8)) - -/// value for sli_radioaes_dma_sg_descr.tag specifying data type payload (will be encrypted/decrypted and authenticated) -#define DMA_SG_TAG_DATATYPE_AESPAYLOAD 0x00000000 -/// value for sli_radioaes_dma_sg_descr.tag specifying data type header (will only be authenticated, not encrypted/decrypted) -#define DMA_SG_TAG_DATATYPE_AESHEADER 0x00000040 - -/// macro to set the amount of invalid bytes in for sli_radioaes_dma_sg_descr.tag -#define DMA_SG_TAG_SETINVALIDBYTES(a) ((((a) & 0x1F) << 8)) - -#define DMA_AXI_DESCR_CONST_ADDR 0x10000000 -#define DMA_AXI_DESCR_REALIGN 0x20000000 -#define DMA_AXI_DESCR_DISCARD 0x40000000 -#define DMA_AXI_DESCR_INT_ENABLE 0x80000000 -#define DMA_AXI_DESCR_INT_DISABLE 0x00000000 - -#define DMA_AXI_DESCR_NEXT_STOP 0x00000001 -#define DMA_AXI_DESCR_NEXT_CONTINUE 0x00000000 -#define DMA_AXI_DESCR_MASK_NEXT_ADD 0xFFFFFFFC - -/// value of flags to discard the data -#define BLOCK_S_DISCARD_DATA 0x40000000 -/// value of flags to realign the data -#define BLOCK_S_REALIGN_DATA 0x20000000 -/// value of flags to set addressing in constant mode (pointing to a FIFO) -#define BLOCK_S_CONST_ADDR 0x10000000 -/// value of flags to set addressing in increment mode (pointing to a buffer) -#define BLOCK_S_INCR_ADDR 0x00000000 -/// mask for flags to only get DMA-related options -#define BLOCK_S_FLAG_MASK_DMA_PROPS 0x70000000 -/// value of flags mask for fetcher location destination -#define BLOCK_S_MASK_LOC_DEST 0x00FFFFFF - -/// Config /// - -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_CFG 0 -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_KEY 8 -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_IV 40 -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_IV2 56 -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_KEY2 72 -/// BA411E offset for Configuration word in DMA Scatter-Gather Tag -#define AES_OFFSET_MASK 104 - -/// BA411E Mode Register value for ECB mode of operation -#define AES_MODEID_ECB 0x00000100 -/// BA411E Mode Register value for CBC mode of operation -#define AES_MODEID_CBC 0x00000200 -/// BA411E Mode Register value for CTR mode of operation -#define AES_MODEID_CTR 0x00000400 -/// BA411E Mode Register value for CCM mode of operation -#define AES_MODEID_CCM 0x00002000 -/// BA411E Mode Register value for CMAC mode of operation -#define AES_MODEID_CMA 0x00010000 - -/// BA411E Mode Register value for AES context saving -#define AES_MODEID_CX_SAVE 0x00000020 -/// BA411E Mode Register value for AES context loading -#define AES_MODEID_CX_LOAD 0x00000010 -/// BA411E Mode Register value for AES no context -#define AES_MODEID_NO_CX 0x00000000 - -/// BA411E Mode Register value for AES keysize of 128 bits -#define AES_MODEID_AES128 0x00000000 -/// BA411E Mode Register value for AES keysize of 256 bits -#define AES_MODEID_AES256 0x00000004 -/// BA411E Mode Register value for AES keysize of 192 bits -#define AES_MODEID_AES192 0x00000008 - -/// BA411E Mode Register value for encryption mode -#define AES_MODEID_ENCRYPT 0x00000000 -/// BA411E Mode Register value for decryption mode -#define AES_MODEID_DECRYPT 0x00000001 - -/// BA411E Size for IV in GCM mode -#define AES_IV_GCM_SIZE 12 -/// BA411E Size for IV in all modes except GCM -#define AES_IV_SIZE 16 -/// BA411E Size for Context in GCM and CCM modes -#define AES_CTX_xCM_SIZE 32 -/// BA411E Size for Context in all modes except GCM and CCM -#define AES_CTX_SIZE 16 - -/// -/// @brief Select which IP core the DMA will use. To set in descriptor sli_radioaes_dma_sg_descr.tag. -/// -typedef enum { - DMA_SG_ENGINESELECT_BYPASS = 0x00, ///< direct bypass from input to output - DMA_SG_ENGINESELECT_BA411E = 0x01, ///< data flow through BA411E AES - DMA_SG_ENGINESELECT_BA412 = 0x02, ///< data flow through BA412 DES - DMA_SG_ENGINESELECT_BA413 = 0x03, ///< data flow through BA413 Hash - DMA_SG_ENGINESELECT_BA417 = 0x04 ///< data flow through BA417 ChaChaPoly -} dma_engine_select_t; - -/// -/// @brief Structure that represent a descriptor for the DMA module -/// (in scatter-gather mode). -/// -typedef struct { - volatile uint32_t address; - volatile uint32_t nextDescr; - volatile uint32_t lengthAndIrq; - volatile uint32_t tag; -} sli_radioaes_dma_descr_t; - -#if defined(SLI_RADIOAES_REQUIRES_MASKING) -#define SLI_RADIOAES_MASK_DESCRIPTOR(next_descr_addr) \ - { \ - .address = (uint32_t) &sli_radioaes_mask, \ - .nextDescr = next_descr_addr, \ - .lengthAndIrq = 0x20000004UL, \ - .tag = 0x00006811UL \ - }; -#endif - -#define DMA_AXI_DESCR_END_POINTER ((sli_radioaes_dma_descr_t*) DMA_AXI_DESCR_NEXT_STOP) - -// Local CCM variables -static const uint32_t aes_ccm_config_encrypt = AES_MODEID_CCM - | AES_MODEID_NO_CX - | AES_MODEID_AES128 - | AES_MODEID_ENCRYPT; - -static const uint32_t aes_ccm_config_decrypt = AES_MODEID_CCM - | AES_MODEID_NO_CX - | AES_MODEID_AES128 - | AES_MODEID_DECRYPT; -static const uint32_t zeros = 0; - -static sl_status_t sli_radioaes_run_operation(sli_radioaes_dma_descr_t *first_fetch_descriptor, - sli_radioaes_dma_descr_t *first_push_descriptor) -{ - sli_radioaes_state_t aes_ctx; - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - sli_radioaes_dma_descr_t mask_descr = SLI_RADIOAES_MASK_DESCRIPTOR((uint32_t)first_fetch_descriptor); - #endif - - sl_status_t status = sli_radioaes_acquire(); - if (status == SL_STATUS_ISR) { - sli_radioaes_save_state(&aes_ctx); - } else if (status != SL_STATUS_OK) { - return status; - } - - RADIOAES->CTRL = AES_CTRL_FETCHERSCATTERGATHER | AES_CTRL_PUSHERSCATTERGATHER; - - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - RADIOAES->FETCHADDR = (uint32_t) &mask_descr; - #else - RADIOAES->FETCHADDR = (uint32_t) first_fetch_descriptor; - #endif - RADIOAES->PUSHADDR = (uint32_t) first_push_descriptor; - - RADIOAES->CMD = AES_CMD_STARTPUSHER | AES_CMD_STARTFETCHER; - while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY)) { - // Wait for completion - } - - if (status == SL_STATUS_ISR) { - sli_radioaes_restore_state(&aes_ctx); - } - - return sli_radioaes_release(); -} - -// CCM (and CCM-star) implementation -static sl_status_t aes_ccm_radio(bool encrypt, - const unsigned char *add_data, - size_t add_length, - const unsigned char *data_in, - unsigned char *data_out, - size_t length, - const unsigned char *key, - const unsigned char *header, - size_t header_length, - unsigned char *tag, - size_t tag_length) - -{ - // Assumptions: - // * There is always header input, but the header input may be block-aligned (BLE-CCM) - // * There may not always be ADD input (e.g. BLE-CCM) - // * There may not always be data input (e.g. CCM in authenticated-only mode) - // * The header input is pre-calculated by the caller of this function - // * Data output may be NULL (in which case it is discarded) - // * Tag length may be 0 (CCM-star), in which case the tag pointer is also allowed to be NULL - - // Setup ver_failed output buffer and initialize it in case of decryption to an invalid value - volatile uint8_t ver_failed[AES_BLOCK_BYTES] = {[0 ... AES_BLOCK_BYTES - 1] = 0xFF }; - - // Calculate padding bytes. Since the accelerator expects to see the AESPAYLOAD data type - // at least once during the operation, ensure that we're emitting a padding block in case - // no input data is present. - size_t header_pad_bytes = (AES_BLOCK_BYTES - ((header_length + add_length) % AES_BLOCK_BYTES)) % AES_BLOCK_BYTES; - size_t data_pad_bytes = (length > 0 ? (AES_BLOCK_BYTES - (length % AES_BLOCK_BYTES)) % AES_BLOCK_BYTES : 16); - - // Fetchers - - // Tag output. If used, always the last descriptor. Not used for CCM-* without tag, the - // accelerator actually looks at the header and figures out whether or not to take in - // tag input. - sli_radioaes_dma_descr_t ccm_desc_fetcher_tag = { - .address = (uint32_t) tag, - .nextDescr = (uint32_t) DMA_AXI_DESCR_END_POINTER, - .lengthAndIrq = (uint32_t) tag_length - | BLOCK_S_INCR_ADDR - | BLOCK_S_REALIGN_DATA, - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISDATA - | DMA_SG_TAG_ISLAST - | DMA_SG_TAG_DATATYPE_AESPAYLOAD - | DMA_SG_TAG_SETINVALIDBYTES(AES_BLOCK_BYTES - tag_length) - }; - - // Data input. Can be zero-length, in which case we'll issue a bogus descriptor instead. - sli_radioaes_dma_descr_t ccm_desc_fetcher_data = { - .address = (uint32_t) (length > 0 ? data_in : ver_failed), - .nextDescr = (uint32_t) ((encrypt || tag_length == 0) ? DMA_AXI_DESCR_END_POINTER : &ccm_desc_fetcher_tag), - .lengthAndIrq = (uint32_t) (length > 0 ? length : data_pad_bytes) - | BLOCK_S_INCR_ADDR - | BLOCK_S_REALIGN_DATA, - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISDATA - | DMA_SG_TAG_DATATYPE_AESPAYLOAD - | ((encrypt || tag_length == 0) ? DMA_SG_TAG_ISLAST : 0) - | DMA_SG_TAG_SETINVALIDBYTES(data_pad_bytes), - }; - - // Possible CCM AAD block (concatenated with the header). Can be zero-length, in which case - // this descriptor should not be referenced but rather bypassed to data. - sli_radioaes_dma_descr_t ccm_desc_fetcher_add = { - .address = (uint32_t) add_data, - .nextDescr = (uint32_t) &ccm_desc_fetcher_data, - .lengthAndIrq = (uint32_t) add_length - | BLOCK_S_INCR_ADDR - | BLOCK_S_REALIGN_DATA, - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISDATA - | DMA_SG_TAG_DATATYPE_AESHEADER - | DMA_SG_TAG_SETINVALIDBYTES(header_pad_bytes) - }; - - // Header input block. Always present. - sli_radioaes_dma_descr_t ccm_desc_fetcher_header = { - .address = (uint32_t) header, - .nextDescr = (uint32_t) (add_length > 0 ? &ccm_desc_fetcher_add : &ccm_desc_fetcher_data), - .lengthAndIrq = (uint32_t) header_length - | BLOCK_S_INCR_ADDR - | (add_length > 0 ? 0 : BLOCK_S_REALIGN_DATA), - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISDATA - | DMA_SG_TAG_DATATYPE_AESHEADER - | (add_length > 0 ? 0 : DMA_SG_TAG_SETINVALIDBYTES(header_pad_bytes)) - }; - - // Key input block. Always present. - sli_radioaes_dma_descr_t ccm_desc_fetcher_key = { - .address = (uint32_t) key, - .nextDescr = (uint32_t) &ccm_desc_fetcher_header, - .lengthAndIrq = (uint32_t) AES_128_KEY_BYTES - | BLOCK_S_INCR_ADDR - | BLOCK_S_REALIGN_DATA, - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISCONFIG - | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) - }; - - // Operation configuration word block. Always present. - sli_radioaes_dma_descr_t ccm_desc_fetcher_config = { - .address = (uint32_t) (encrypt ? &aes_ccm_config_encrypt : &aes_ccm_config_decrypt), - .nextDescr = (uint32_t) &ccm_desc_fetcher_key, - .lengthAndIrq = (uint32_t) RADIOAES_CONFIG_BYTES - | BLOCK_S_INCR_ADDR - | BLOCK_S_REALIGN_DATA, - .tag = DMA_SG_ENGINESELECT_BA411E - | DMA_SG_TAG_ISCONFIG - | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) - }; - - // Pushers - - // Tag / verification output padding, only if 0 < tag length < 16 bytes. - sli_radioaes_dma_descr_t ccm_desc_pusher_final_padding = { - .address = (uint32_t) NULL, - .nextDescr = (uint32_t) DMA_AXI_DESCR_END_POINTER, - .lengthAndIrq = (uint32_t) (AES_BLOCK_BYTES - tag_length) - | DMA_AXI_DESCR_DISCARD - }; - - // Tag output. Direct into tag buffer for encrypt, into local buffer for - // decrypt-and-verify. This descriptor is not referenced with tag_length == 0 (CCM-*) - sli_radioaes_dma_descr_t ccm_desc_pusher_tag = { - .address = (uint32_t) (encrypt ? tag : (unsigned char *)ver_failed), - .nextDescr = (uint32_t) ((AES_BLOCK_BYTES - tag_length) > 0 ? &ccm_desc_pusher_final_padding : DMA_AXI_DESCR_END_POINTER), - .lengthAndIrq = (uint32_t) tag_length - }; - - // Data padding output. There's guaranteed always at least one of data or data padding. - sli_radioaes_dma_descr_t ccm_desc_pusher_data_padding = { - .address = (uint32_t) NULL, - .nextDescr = (uint32_t) (tag_length > 0 ? &ccm_desc_pusher_tag : DMA_AXI_DESCR_END_POINTER), - .lengthAndIrq = (uint32_t) data_pad_bytes - | DMA_AXI_DESCR_DISCARD, - }; - - // Data (ciphertext/plaintext) output. Pointer can be NULL, in which case we tell the - // DMA to discard the data. - sli_radioaes_dma_descr_t ccm_desc_pusher_data = { - .address = (uint32_t) data_out, - .nextDescr = (uint32_t) (data_pad_bytes > 0 ? &ccm_desc_pusher_data_padding : (tag_length > 0 ? &ccm_desc_pusher_tag : DMA_AXI_DESCR_END_POINTER)), - .lengthAndIrq = (uint32_t) length - | (data_out == NULL ? DMA_AXI_DESCR_DISCARD : 0), - }; - - // Discard all AAD input (which is reflected back to the output). There's guaranteed always a header. - sli_radioaes_dma_descr_t ccm_desc_pusher_header_add = { - .address = (uint32_t) NULL, - .nextDescr = (uint32_t) (length > 0 ? &ccm_desc_pusher_data : &ccm_desc_pusher_data_padding), - .lengthAndIrq = (uint32_t) (header_length + add_length + header_pad_bytes) - | DMA_AXI_DESCR_DISCARD - }; - - sl_status_t status = sli_radioaes_run_operation(&ccm_desc_fetcher_config, &ccm_desc_pusher_header_add); - - if (status != SL_STATUS_OK) { - return status; - } - - // Check MIC - if (!encrypt) { - uint32_t accumulator = 0; - for (size_t i = 0; i < tag_length; i++) { - accumulator |= ver_failed[i]; - } - if (accumulator != 0) { - return SL_STATUS_INVALID_SIGNATURE; - } - } - return SL_STATUS_OK; -} - -// Perform a CCM encrypt/decrypt operation with BLE parameters and input. -// This means: -// * 13 bytes IV -// * 1 byte AAD (parameter 'header') -// * AES-128 key (16 byte key) -// * in-place encrypt/decrypt with variable length plain/ciphertext -// (up to 64 kB, uint16 overflow) -// * 4 byte tag -static sl_status_t aes_ccm_ble(bool encrypt, - unsigned char *data, - size_t length, - const unsigned char *key, - const unsigned char *iv, - unsigned char header, - unsigned char *tag) - -{ - uint8_t b0b1[19]; - - // Fill in B0 block according to BLE spec - b0b1[0] = 0x49U; - - // Copy in the 13 bytes of nonce - for (size_t i = 0; i < 13; i++) { - b0b1[i + 1] = iv[i]; - } - - b0b1[14] = (uint8_t) length >> 8; - b0b1[15] = (uint8_t) length; - b0b1[16] = 0; // upper octet of AAD length - b0b1[17] = 1; // lower octet of AAD length (BLE CCM always has only one byte of AAD) - b0b1[18] = header; // AAD - - return aes_ccm_radio(encrypt, - NULL, 0, - data, data, length, - key, - b0b1, sizeof(b0b1), - tag, 4); -} - -sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, - unsigned int keybits, - const unsigned char input[AES_BLOCK_BYTES], - const unsigned char iv_in[AES_BLOCK_BYTES], - volatile unsigned char iv_out[AES_BLOCK_BYTES], - volatile unsigned char output[AES_BLOCK_BYTES]) -{ - uint32_t aes_config; - static const uint32_t zero = 0; - - switch (keybits) { - case 256: - aes_config = AES_MODEID_CTR | AES_MODEID_CX_LOAD | (((uint32_t)iv_out != 0) ? AES_MODEID_CX_SAVE : 0) | AES_MODEID_AES256; - break; - case 192: - return SL_STATUS_NOT_SUPPORTED; - case 128: - aes_config = AES_MODEID_CTR | AES_MODEID_CX_LOAD | (((uint32_t)iv_out != 0) ? AES_MODEID_CX_SAVE : 0) | AES_MODEID_AES128; - break; - default: - return SL_STATUS_INVALID_KEY; - } - - sli_radioaes_dma_descr_t aes_desc_pusher_ctx = { - .address = (uint32_t) iv_out, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST - }; - - sli_radioaes_dma_descr_t aes_desc_pusher_data = { - .address = (uint32_t) output, - .nextDescr = (((uint32_t)iv_out != 0) ? (uint32_t) &aes_desc_pusher_ctx : DMA_AXI_DESCR_NEXT_STOP), - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISDATA - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_data = { - .address = (uint32_t) input, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_no_ctx = { - .address = (uint32_t) &zero, - .nextDescr = (uint32_t) &aes_desc_fetcher_data, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_CONST_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_IV) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_ctx = { - .address = (uint32_t) iv_in, - .nextDescr = (uint32_t) &aes_desc_fetcher_data, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_IV) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_config = { - .address = (uint32_t) &aes_config, - .nextDescr = (((uint32_t)iv_in != 0) ? (uint32_t) &aes_desc_fetcher_ctx : (uint32_t) &aes_desc_fetcher_no_ctx), - .lengthAndIrq = sizeof(aes_config), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_key = { - .address = (uint32_t) key, - .nextDescr = (uint32_t) &aes_desc_fetcher_config, - .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) - }; - - // Start operation - return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); -} - -sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, - const unsigned char *key, - unsigned int keybits, - const unsigned char input[AES_BLOCK_BYTES], - volatile unsigned char output[AES_BLOCK_BYTES]) -{ - uint32_t aes_config; - - switch (keybits) { - case 256: - aes_config = AES_MODEID_ECB | AES_MODEID_NO_CX | AES_MODEID_AES256; - break; - case 192: - return SL_STATUS_NOT_SUPPORTED; - case 128: - aes_config = AES_MODEID_ECB | AES_MODEID_NO_CX | AES_MODEID_AES128; - break; - default: - return SL_STATUS_INVALID_KEY; - } - - aes_config |= encrypt ? AES_MODEID_ENCRYPT : AES_MODEID_DECRYPT; - - sli_radioaes_dma_descr_t aes_desc_pusher_data = { - .address = (uint32_t) output, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_data = { - .address = (uint32_t) input, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_config = { - .address = (uint32_t) &aes_config, - .nextDescr = (uint32_t) &aes_desc_fetcher_data, - .lengthAndIrq = sizeof(aes_config), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_key = { - .address = (uint32_t) key, - .nextDescr = (uint32_t) &aes_desc_fetcher_config, - .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) - }; - - // Start operation - return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); -} - -sl_status_t sli_aes_cmac_radio(const unsigned char *key, - unsigned int keybits, - const unsigned char *input, - unsigned int length, - volatile unsigned char output[16]) -{ - uint32_t aes_config; - - switch (keybits) { - case 256: - aes_config = AES_MODEID_CMA | AES_MODEID_NO_CX | AES_MODEID_AES256 | AES_MODEID_ENCRYPT; - break; - case 192: - return SL_STATUS_NOT_SUPPORTED; - case 128: - aes_config = AES_MODEID_CMA | AES_MODEID_NO_CX | AES_MODEID_AES128 | AES_MODEID_ENCRYPT; - break; - default: - return SL_STATUS_INVALID_KEY; - } - - size_t pad_len = 16 - (length % 16); - if (pad_len == 16 && length > 0) { - pad_len = 0; - } - - if (length == 0) { - length = 16UL; - input = (const unsigned char *)&zeros; - } else { - length = (length + 15) & ~0xFUL; - } - - sli_radioaes_dma_descr_t aes_desc_pusher_data = { - .address = (uint32_t) output, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_data = { - .address = (uint32_t) input, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = length | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD | DMA_SG_TAG_SETINVALIDBYTES(pad_len) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_config = { - .address = (uint32_t) &aes_config, - .nextDescr = (uint32_t) &aes_desc_fetcher_data, - .lengthAndIrq = sizeof(aes_config), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_key = { - .address = (uint32_t) key, - .nextDescr = (uint32_t) &aes_desc_fetcher_config, - .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) - }; - - // Start operation - return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); -} - -// -// CCM buffer authenticated decryption optimized for BLE -// -sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, - size_t length, - const unsigned char *key, - const unsigned char *iv, - unsigned char header, - unsigned char *tag) -{ - return aes_ccm_ble(false, - data, - length, - key, - iv, - header, - (uint8_t *) tag); -} - -// -// CCM buffer encryption optimized for BLE -// -sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, - size_t length, - const unsigned char *key, - const unsigned char *iv, - unsigned char header, - unsigned char *tag) -{ - return aes_ccm_ble(true, - data, - length, - key, - iv, - header, - tag); -} - -sl_status_t sli_ccm_zigbee(bool encrypt, - const unsigned char *data_in, - unsigned char *data_out, - size_t length, - const unsigned char *key, - const unsigned char *iv, - const unsigned char *aad, - size_t aad_len, - unsigned char *tag, - size_t tag_len) -{ - // Validated assumption: for ZigBee, the authenticated data - // length will always fit into a 16-bit length field, meaning - // the header will always be either 16 or 18 bytes long. - uint8_t header[18]; - - // Start with the 'flags' byte. It encodes whether there is AAD, - // and the length of the tag fields - header[0] = 0x01 // always 2 bytes of message length - | ((aad_len > 0) ? 0x40 : 0x00) // Set 'aflag' bit if there is AAD - | ((tag_len >= 4) ? (((tag_len - 2) / 2) << 3) : 0); // Encode tag length - - for (size_t i = 0; i < 13; i++) { - header[i + 1] = iv[i]; - } - - header[14] = (uint8_t) length >> 8; - header[15] = (uint8_t) length; - if (aad_len > 0) { - header[16] = (uint8_t) aad_len >> 8; // upper octet of AAD length - header[17] = (uint8_t) aad_len; // lower octet of AAD length - } - - return aes_ccm_radio(encrypt, - aad, - aad_len, - data_in, - data_out, - length, - key, - header, - (aad_len > 0 ? 18 : 16), - tag, - tag_len); -} - -// -// Process a table of BLE RPA device keys and look for a -// match against the supplied hash. Algorithm is AES-128. -// -int sli_process_ble_rpa(const unsigned char keytable[], - uint32_t keymask, - uint32_t prand, - uint32_t hash) -{ - int block; - int previous_block = -1, result = -1; - static const uint32_t aes_rpa_config = AES_MODEID_ECB - | AES_MODEID_NO_CX - | AES_MODEID_AES128 - | AES_MODEID_ENCRYPT; - - uint32_t rpa_data_in[AES_BLOCK_BYTES / sizeof(uint32_t)] = { 0 }; - volatile uint32_t rpa_data_out[AES_BLOCK_BYTES / sizeof(uint32_t)]; - sli_radioaes_state_t aes_ctx; - CORE_DECLARE_IRQ_STATE; - - rpa_data_in[3] = __REV(prand); - - sli_radioaes_dma_descr_t aes_desc_pusher_data = { - .address = (uint32_t) rpa_data_out, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_data = { - .address = (uint32_t) rpa_data_in, - .nextDescr = DMA_AXI_DESCR_NEXT_STOP, - .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD - }; - - sli_radioaes_dma_descr_t aes_desc_fetcher_config = { - .address = (uint32_t) &aes_rpa_config, - .nextDescr = (uint32_t) &aes_desc_fetcher_data, - .lengthAndIrq = sizeof(aes_rpa_config), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) - }; - - volatile sli_radioaes_dma_descr_t aes_desc_fetcher_key = { - .address = (uint32_t) NULL, // Filled out in each round of RPA check - .nextDescr = (uint32_t) &aes_desc_fetcher_config, - .lengthAndIrq = (uint32_t) AES_128_KEY_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), - .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) - }; - - // Start operation - sl_status_t status = sli_radioaes_acquire(); - if (status == SL_STATUS_ISR) { - sli_radioaes_save_state(&aes_ctx); - } else if (status != SL_STATUS_OK) { - return -1; - } - - RADIOAES->CTRL = AES_CTRL_FETCHERSCATTERGATHER | AES_CTRL_PUSHERSCATTERGATHER; - - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - // Start with feeding the mask input - sli_radioaes_dma_descr_t mask_descr = SLI_RADIOAES_MASK_DESCRIPTOR(DMA_AXI_DESCR_NEXT_STOP); - RADIOAES->FETCHADDR = (uint32_t) &mask_descr; - RADIOAES->CMD = AES_CMD_STARTFETCHER; - #endif - - // Start a critical section to avoid preemption in-between loading of the RPA key - // and starting the corresponding data pusher. - CORE_ENTER_CRITICAL(); - - // Data output contains hash in the most significant word (WORD3). - // Descriptors for blocks that are not included in key mask will be skipped. - for (block = 0; block < RADIOAES_BLE_RPA_MAX_KEYS; block++) { - if ( keymask & (1U << block) ) { // Skip masked keys - // Handle pending interrupts while the peripheral is in 'preemptable' state - CORE_YIELD_CRITICAL(); - // Write key address and start operation - while (RADIOAES->STATUS & AES_STATUS_FETCHERBSY) { - // Wait for completion - } - aes_desc_fetcher_key.address = (uint32_t) &keytable[block * AES_128_KEY_BYTES]; - RADIOAES->FETCHADDR = (uint32_t) &aes_desc_fetcher_key; - - RADIOAES->CMD = AES_CMD_STARTFETCHER; - - // Wait for pusher from previous round to finish - while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { - // Wait for completion - } - RADIOAES->PUSHADDR = (uint32_t) &aes_desc_pusher_data; - - // Check previous results while AES is processing - if ((previous_block >= 0) && ((rpa_data_out[3] & 0xFFFFFF00) == __REV(hash)) ) { - // Make sure AES is finished before returning - RADIOAES->CMD = AES_CMD_STARTPUSHER; - result = previous_block; - break; - } - - // Start pusher so it is ready to push results when encryption is done - RADIOAES->CMD = AES_CMD_STARTPUSHER; - previous_block = block; - } - } - - CORE_EXIT_CRITICAL(); - - // Wait for last data and check it - while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { - // Wait for completion - } - - if (status == SL_STATUS_ISR) { - sli_radioaes_restore_state(&aes_ctx); - } - - sli_radioaes_release(); - - if (result >= 0) { - return result; - } - - if ((rpa_data_out[3] & 0xFFFFFF00) == __REV(hash) ) { - return previous_block; - } - - // No match - return -1; -} - -void sli_aes_seed_mask(void) -{ - // Acquiring and releasing the peripheral should ensure the mask is properly - // set. - (void) sli_radioaes_acquire(); - (void) sli_radioaes_release(); -} - -/// @endcond -#endif // defined(RADIOAES_PRESENT) +/***************************************************************************//** + * @file + * @brief Accelerated cryptographic primitives using the RADIOAES peripheral. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" + +#if defined(RADIOAES_PRESENT) +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "sli_radioaes_management.h" +#include "sli_protocol_crypto.h" +#include "em_core.h" + +#define AES_BLOCK_BYTES 16U +#define AES_128_KEY_BYTES 16U +#define AES_256_KEY_BYTES 32U + +#define RADIOAES_CONFIG_BYTES 4U + +#ifndef RADIOAES_BLE_RPA_MAX_KEYS +#define RADIOAES_BLE_RPA_MAX_KEYS 32 +#endif + +/// value for sli_radioaes_dma_sg_descr.tag to direct data to parameters +#define DMA_SG_TAG_ISCONFIG 0x00000010 +/// value for sli_radioaes_dma_sg_descr.tag to direct data to processing +#define DMA_SG_TAG_ISDATA 0x00000000 +/// value for sli_radioaes_dma_sg_descr.tag specifying data as last +#define DMA_SG_TAG_ISLAST 0x00000020 + +/// macro to set the offset in the configuration for sli_radioaes_dma_sg_descr.tag +#define DMA_SG_TAG_SETCFGOFFSET(a) ((((a) & 0xFF) << 8)) + +/// value for sli_radioaes_dma_sg_descr.tag specifying data type payload (will be encrypted/decrypted and authenticated) +#define DMA_SG_TAG_DATATYPE_AESPAYLOAD 0x00000000 +/// value for sli_radioaes_dma_sg_descr.tag specifying data type header (will only be authenticated, not encrypted/decrypted) +#define DMA_SG_TAG_DATATYPE_AESHEADER 0x00000040 + +/// macro to set the amount of invalid bytes in for sli_radioaes_dma_sg_descr.tag +#define DMA_SG_TAG_SETINVALIDBYTES(a) ((((a) & 0x1F) << 8)) + +#define DMA_AXI_DESCR_CONST_ADDR 0x10000000 +#define DMA_AXI_DESCR_REALIGN 0x20000000 +#define DMA_AXI_DESCR_DISCARD 0x40000000 +#define DMA_AXI_DESCR_INT_ENABLE 0x80000000 +#define DMA_AXI_DESCR_INT_DISABLE 0x00000000 + +#define DMA_AXI_DESCR_NEXT_STOP 0x00000001 +#define DMA_AXI_DESCR_NEXT_CONTINUE 0x00000000 +#define DMA_AXI_DESCR_MASK_NEXT_ADD 0xFFFFFFFC + +/// value of flags to discard the data +#define BLOCK_S_DISCARD_DATA 0x40000000 +/// value of flags to realign the data +#define BLOCK_S_REALIGN_DATA 0x20000000 +/// value of flags to set addressing in constant mode (pointing to a FIFO) +#define BLOCK_S_CONST_ADDR 0x10000000 +/// value of flags to set addressing in increment mode (pointing to a buffer) +#define BLOCK_S_INCR_ADDR 0x00000000 +/// mask for flags to only get DMA-related options +#define BLOCK_S_FLAG_MASK_DMA_PROPS 0x70000000 +/// value of flags mask for fetcher location destination +#define BLOCK_S_MASK_LOC_DEST 0x00FFFFFF + +/// Config /// + +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_CFG 0 +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_KEY 8 +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_IV 40 +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_IV2 56 +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_KEY2 72 +/// BA411E offset for Configuration word in DMA Scatter-Gather Tag +#define AES_OFFSET_MASK 104 + +/// BA411E Mode Register value for ECB mode of operation +#define AES_MODEID_ECB 0x00000100 +/// BA411E Mode Register value for CBC mode of operation +#define AES_MODEID_CBC 0x00000200 +/// BA411E Mode Register value for CTR mode of operation +#define AES_MODEID_CTR 0x00000400 +/// BA411E Mode Register value for CCM mode of operation +#define AES_MODEID_CCM 0x00002000 +/// BA411E Mode Register value for CMAC mode of operation +#define AES_MODEID_CMA 0x00010000 + +/// BA411E Mode Register value for AES context saving +#define AES_MODEID_CX_SAVE 0x00000020 +/// BA411E Mode Register value for AES context loading +#define AES_MODEID_CX_LOAD 0x00000010 +/// BA411E Mode Register value for AES no context +#define AES_MODEID_NO_CX 0x00000000 + +/// BA411E Mode Register value for AES keysize of 128 bits +#define AES_MODEID_AES128 0x00000000 +/// BA411E Mode Register value for AES keysize of 256 bits +#define AES_MODEID_AES256 0x00000004 +/// BA411E Mode Register value for AES keysize of 192 bits +#define AES_MODEID_AES192 0x00000008 + +/// BA411E Mode Register value for encryption mode +#define AES_MODEID_ENCRYPT 0x00000000 +/// BA411E Mode Register value for decryption mode +#define AES_MODEID_DECRYPT 0x00000001 + +/// BA411E Size for IV in GCM mode +#define AES_IV_GCM_SIZE 12 +/// BA411E Size for IV in all modes except GCM +#define AES_IV_SIZE 16 +/// BA411E Size for Context in GCM and CCM modes +#define AES_CTX_xCM_SIZE 32 +/// BA411E Size for Context in all modes except GCM and CCM +#define AES_CTX_SIZE 16 + +/// +/// @brief Select which IP core the DMA will use. To set in descriptor sli_radioaes_dma_sg_descr.tag. +/// +typedef enum { + DMA_SG_ENGINESELECT_BYPASS = 0x00, ///< direct bypass from input to output + DMA_SG_ENGINESELECT_BA411E = 0x01, ///< data flow through BA411E AES + DMA_SG_ENGINESELECT_BA412 = 0x02, ///< data flow through BA412 DES + DMA_SG_ENGINESELECT_BA413 = 0x03, ///< data flow through BA413 Hash + DMA_SG_ENGINESELECT_BA417 = 0x04 ///< data flow through BA417 ChaChaPoly +} dma_engine_select_t; + +/// +/// @brief Structure that represent a descriptor for the DMA module +/// (in scatter-gather mode). +/// +typedef struct { + volatile uint32_t address; + volatile uint32_t nextDescr; + volatile uint32_t lengthAndIrq; + volatile uint32_t tag; +} sli_radioaes_dma_descr_t; + +#if defined(SLI_RADIOAES_REQUIRES_MASKING) +#define SLI_RADIOAES_MASK_DESCRIPTOR(next_descr_addr) \ + { \ + .address = (uint32_t) &sli_radioaes_mask, \ + .nextDescr = next_descr_addr, \ + .lengthAndIrq = 0x20000004UL, \ + .tag = 0x00006811UL \ + }; +#endif + +#define DMA_AXI_DESCR_END_POINTER ((sli_radioaes_dma_descr_t*) DMA_AXI_DESCR_NEXT_STOP) + +// Local CCM variables +static const uint32_t aes_ccm_config_encrypt = AES_MODEID_CCM + | AES_MODEID_NO_CX + | AES_MODEID_AES128 + | AES_MODEID_ENCRYPT; + +static const uint32_t aes_ccm_config_decrypt = AES_MODEID_CCM + | AES_MODEID_NO_CX + | AES_MODEID_AES128 + | AES_MODEID_DECRYPT; +static const uint32_t zeros = 0; + +static sl_status_t sli_radioaes_run_operation(sli_radioaes_dma_descr_t *first_fetch_descriptor, + sli_radioaes_dma_descr_t *first_push_descriptor) +{ + sli_radioaes_state_t aes_ctx; + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + sli_radioaes_dma_descr_t mask_descr = SLI_RADIOAES_MASK_DESCRIPTOR((uint32_t)first_fetch_descriptor); + #endif + + sl_status_t status = sli_radioaes_acquire(); + if (status == SL_STATUS_ISR) { + sli_radioaes_save_state(&aes_ctx); + } else if (status != SL_STATUS_OK) { + return status; + } + + RADIOAES->CTRL = AES_CTRL_FETCHERSCATTERGATHER | AES_CTRL_PUSHERSCATTERGATHER; + + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + RADIOAES->FETCHADDR = (uint32_t) &mask_descr; + #else + RADIOAES->FETCHADDR = (uint32_t) first_fetch_descriptor; + #endif + RADIOAES->PUSHADDR = (uint32_t) first_push_descriptor; + + RADIOAES->CMD = AES_CMD_STARTPUSHER | AES_CMD_STARTFETCHER; + while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY)) { + // Wait for completion + } + + if (status == SL_STATUS_ISR) { + sli_radioaes_restore_state(&aes_ctx); + } + + return sli_radioaes_release(); +} + +// CCM (and CCM-star) implementation +static sl_status_t aes_ccm_radio(bool encrypt, + const unsigned char *add_data, + size_t add_length, + const unsigned char *data_in, + unsigned char *data_out, + size_t length, + const unsigned char *key, + const unsigned char *header, + size_t header_length, + unsigned char *tag, + size_t tag_length) + +{ + // Assumptions: + // * There is always header input, but the header input may be block-aligned (BLE-CCM) + // * There may not always be ADD input (e.g. BLE-CCM) + // * There may not always be data input (e.g. CCM in authenticated-only mode) + // * The header input is pre-calculated by the caller of this function + // * Data output may be NULL (in which case it is discarded) + // * Tag length may be 0 (CCM-star), in which case the tag pointer is also allowed to be NULL + + // Setup ver_failed output buffer and initialize it in case of decryption to an invalid value + volatile uint8_t ver_failed[AES_BLOCK_BYTES] = {[0 ... AES_BLOCK_BYTES - 1] = 0xFF }; + + // Calculate padding bytes. Since the accelerator expects to see the AESPAYLOAD data type + // at least once during the operation, ensure that we're emitting a padding block in case + // no input data is present. + size_t header_pad_bytes = (AES_BLOCK_BYTES - ((header_length + add_length) % AES_BLOCK_BYTES)) % AES_BLOCK_BYTES; + size_t data_pad_bytes = (length > 0 ? (AES_BLOCK_BYTES - (length % AES_BLOCK_BYTES)) % AES_BLOCK_BYTES : 16); + + // Fetchers + + // Tag output. If used, always the last descriptor. Not used for CCM-* without tag, the + // accelerator actually looks at the header and figures out whether or not to take in + // tag input. + sli_radioaes_dma_descr_t ccm_desc_fetcher_tag = { + .address = (uint32_t) tag, + .nextDescr = (uint32_t) DMA_AXI_DESCR_END_POINTER, + .lengthAndIrq = (uint32_t) tag_length + | BLOCK_S_INCR_ADDR + | BLOCK_S_REALIGN_DATA, + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISDATA + | DMA_SG_TAG_ISLAST + | DMA_SG_TAG_DATATYPE_AESPAYLOAD + | DMA_SG_TAG_SETINVALIDBYTES(AES_BLOCK_BYTES - tag_length) + }; + + // Data input. Can be zero-length, in which case we'll issue a bogus descriptor instead. + sli_radioaes_dma_descr_t ccm_desc_fetcher_data = { + .address = (uint32_t) (length > 0 ? data_in : ver_failed), + .nextDescr = (uint32_t) ((encrypt || tag_length == 0) ? DMA_AXI_DESCR_END_POINTER : &ccm_desc_fetcher_tag), + .lengthAndIrq = (uint32_t) (length > 0 ? length : data_pad_bytes) + | BLOCK_S_INCR_ADDR + | BLOCK_S_REALIGN_DATA, + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISDATA + | DMA_SG_TAG_DATATYPE_AESPAYLOAD + | ((encrypt || tag_length == 0) ? DMA_SG_TAG_ISLAST : 0) + | DMA_SG_TAG_SETINVALIDBYTES(data_pad_bytes), + }; + + // Possible CCM AAD block (concatenated with the header). Can be zero-length, in which case + // this descriptor should not be referenced but rather bypassed to data. + sli_radioaes_dma_descr_t ccm_desc_fetcher_add = { + .address = (uint32_t) add_data, + .nextDescr = (uint32_t) &ccm_desc_fetcher_data, + .lengthAndIrq = (uint32_t) add_length + | BLOCK_S_INCR_ADDR + | BLOCK_S_REALIGN_DATA, + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISDATA + | DMA_SG_TAG_DATATYPE_AESHEADER + | DMA_SG_TAG_SETINVALIDBYTES(header_pad_bytes) + }; + + // Header input block. Always present. + sli_radioaes_dma_descr_t ccm_desc_fetcher_header = { + .address = (uint32_t) header, + .nextDescr = (uint32_t) (add_length > 0 ? &ccm_desc_fetcher_add : &ccm_desc_fetcher_data), + .lengthAndIrq = (uint32_t) header_length + | BLOCK_S_INCR_ADDR + | (add_length > 0 ? 0 : BLOCK_S_REALIGN_DATA), + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISDATA + | DMA_SG_TAG_DATATYPE_AESHEADER + | (add_length > 0 ? 0 : DMA_SG_TAG_SETINVALIDBYTES(header_pad_bytes)) + }; + + // Key input block. Always present. + sli_radioaes_dma_descr_t ccm_desc_fetcher_key = { + .address = (uint32_t) key, + .nextDescr = (uint32_t) &ccm_desc_fetcher_header, + .lengthAndIrq = (uint32_t) AES_128_KEY_BYTES + | BLOCK_S_INCR_ADDR + | BLOCK_S_REALIGN_DATA, + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISCONFIG + | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) + }; + + // Operation configuration word block. Always present. + sli_radioaes_dma_descr_t ccm_desc_fetcher_config = { + .address = (uint32_t) (encrypt ? &aes_ccm_config_encrypt : &aes_ccm_config_decrypt), + .nextDescr = (uint32_t) &ccm_desc_fetcher_key, + .lengthAndIrq = (uint32_t) RADIOAES_CONFIG_BYTES + | BLOCK_S_INCR_ADDR + | BLOCK_S_REALIGN_DATA, + .tag = DMA_SG_ENGINESELECT_BA411E + | DMA_SG_TAG_ISCONFIG + | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) + }; + + // Pushers + + // Tag / verification output padding, only if 0 < tag length < 16 bytes. + sli_radioaes_dma_descr_t ccm_desc_pusher_final_padding = { + .address = (uint32_t) NULL, + .nextDescr = (uint32_t) DMA_AXI_DESCR_END_POINTER, + .lengthAndIrq = (uint32_t) (AES_BLOCK_BYTES - tag_length) + | DMA_AXI_DESCR_DISCARD + }; + + // Tag output. Direct into tag buffer for encrypt, into local buffer for + // decrypt-and-verify. This descriptor is not referenced with tag_length == 0 (CCM-*) + sli_radioaes_dma_descr_t ccm_desc_pusher_tag = { + .address = (uint32_t) (encrypt ? tag : (unsigned char *)ver_failed), + .nextDescr = (uint32_t) ((AES_BLOCK_BYTES - tag_length) > 0 ? &ccm_desc_pusher_final_padding : DMA_AXI_DESCR_END_POINTER), + .lengthAndIrq = (uint32_t) tag_length + }; + + // Data padding output. There's guaranteed always at least one of data or data padding. + sli_radioaes_dma_descr_t ccm_desc_pusher_data_padding = { + .address = (uint32_t) NULL, + .nextDescr = (uint32_t) (tag_length > 0 ? &ccm_desc_pusher_tag : DMA_AXI_DESCR_END_POINTER), + .lengthAndIrq = (uint32_t) data_pad_bytes + | DMA_AXI_DESCR_DISCARD, + }; + + // Data (ciphertext/plaintext) output. Pointer can be NULL, in which case we tell the + // DMA to discard the data. + sli_radioaes_dma_descr_t ccm_desc_pusher_data = { + .address = (uint32_t) data_out, + .nextDescr = (uint32_t) (data_pad_bytes > 0 ? &ccm_desc_pusher_data_padding : (tag_length > 0 ? &ccm_desc_pusher_tag : DMA_AXI_DESCR_END_POINTER)), + .lengthAndIrq = (uint32_t) length + | (data_out == NULL ? DMA_AXI_DESCR_DISCARD : 0), + }; + + // Discard all AAD input (which is reflected back to the output). There's guaranteed always a header. + sli_radioaes_dma_descr_t ccm_desc_pusher_header_add = { + .address = (uint32_t) NULL, + .nextDescr = (uint32_t) (length > 0 ? &ccm_desc_pusher_data : &ccm_desc_pusher_data_padding), + .lengthAndIrq = (uint32_t) (header_length + add_length + header_pad_bytes) + | DMA_AXI_DESCR_DISCARD + }; + + sl_status_t status = sli_radioaes_run_operation(&ccm_desc_fetcher_config, &ccm_desc_pusher_header_add); + + if (status != SL_STATUS_OK) { + return status; + } + + // Check MIC + if (!encrypt) { + uint32_t accumulator = 0; + for (size_t i = 0; i < tag_length; i++) { + accumulator |= ver_failed[i]; + } + if (accumulator != 0) { + return SL_STATUS_INVALID_SIGNATURE; + } + } + return SL_STATUS_OK; +} + +// Perform a CCM encrypt/decrypt operation with BLE parameters and input. +// This means: +// * 13 bytes IV +// * 1 byte AAD (parameter 'header') +// * AES-128 key (16 byte key) +// * in-place encrypt/decrypt with variable length plain/ciphertext +// (up to 64 kB, uint16 overflow) +// * 4 byte tag +static sl_status_t aes_ccm_ble(bool encrypt, + unsigned char *data, + size_t length, + const unsigned char *key, + const unsigned char *iv, + unsigned char header, + unsigned char *tag) + +{ + uint8_t b0b1[19]; + + // Fill in B0 block according to BLE spec + b0b1[0] = 0x49U; + + // Copy in the 13 bytes of nonce + for (size_t i = 0; i < 13; i++) { + b0b1[i + 1] = iv[i]; + } + + b0b1[14] = (uint8_t) length >> 8; + b0b1[15] = (uint8_t) length; + b0b1[16] = 0; // upper octet of AAD length + b0b1[17] = 1; // lower octet of AAD length (BLE CCM always has only one byte of AAD) + b0b1[18] = header; // AAD + + return aes_ccm_radio(encrypt, + NULL, 0, + data, data, length, + key, + b0b1, sizeof(b0b1), + tag, 4); +} + +sl_status_t sli_aes_crypt_ctr_radio(const unsigned char *key, + unsigned int keybits, + const unsigned char input[AES_BLOCK_BYTES], + const unsigned char iv_in[AES_BLOCK_BYTES], + volatile unsigned char iv_out[AES_BLOCK_BYTES], + volatile unsigned char output[AES_BLOCK_BYTES]) +{ + uint32_t aes_config; + static const uint32_t zero = 0; + + switch (keybits) { + case 256: + aes_config = AES_MODEID_CTR | AES_MODEID_CX_LOAD | (((uint32_t)iv_out != 0) ? AES_MODEID_CX_SAVE : 0) | AES_MODEID_AES256; + break; + case 192: + return SL_STATUS_NOT_SUPPORTED; + case 128: + aes_config = AES_MODEID_CTR | AES_MODEID_CX_LOAD | (((uint32_t)iv_out != 0) ? AES_MODEID_CX_SAVE : 0) | AES_MODEID_AES128; + break; + default: + return SL_STATUS_INVALID_KEY; + } + + sli_radioaes_dma_descr_t aes_desc_pusher_ctx = { + .address = (uint32_t) iv_out, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST + }; + + sli_radioaes_dma_descr_t aes_desc_pusher_data = { + .address = (uint32_t) output, + .nextDescr = (((uint32_t)iv_out != 0) ? (uint32_t) &aes_desc_pusher_ctx : DMA_AXI_DESCR_NEXT_STOP), + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISDATA + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_data = { + .address = (uint32_t) input, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_no_ctx = { + .address = (uint32_t) &zero, + .nextDescr = (uint32_t) &aes_desc_fetcher_data, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_CONST_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_IV) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_ctx = { + .address = (uint32_t) iv_in, + .nextDescr = (uint32_t) &aes_desc_fetcher_data, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_IV) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_config = { + .address = (uint32_t) &aes_config, + .nextDescr = (((uint32_t)iv_in != 0) ? (uint32_t) &aes_desc_fetcher_ctx : (uint32_t) &aes_desc_fetcher_no_ctx), + .lengthAndIrq = sizeof(aes_config), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_key = { + .address = (uint32_t) key, + .nextDescr = (uint32_t) &aes_desc_fetcher_config, + .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) + }; + + // Start operation + return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); +} + +sl_status_t sli_aes_crypt_ecb_radio(bool encrypt, + const unsigned char *key, + unsigned int keybits, + const unsigned char input[AES_BLOCK_BYTES], + volatile unsigned char output[AES_BLOCK_BYTES]) +{ + uint32_t aes_config; + + switch (keybits) { + case 256: + aes_config = AES_MODEID_ECB | AES_MODEID_NO_CX | AES_MODEID_AES256; + break; + case 192: + return SL_STATUS_NOT_SUPPORTED; + case 128: + aes_config = AES_MODEID_ECB | AES_MODEID_NO_CX | AES_MODEID_AES128; + break; + default: + return SL_STATUS_INVALID_KEY; + } + + aes_config |= encrypt ? AES_MODEID_ENCRYPT : AES_MODEID_DECRYPT; + + sli_radioaes_dma_descr_t aes_desc_pusher_data = { + .address = (uint32_t) output, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_data = { + .address = (uint32_t) input, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_config = { + .address = (uint32_t) &aes_config, + .nextDescr = (uint32_t) &aes_desc_fetcher_data, + .lengthAndIrq = sizeof(aes_config), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_key = { + .address = (uint32_t) key, + .nextDescr = (uint32_t) &aes_desc_fetcher_config, + .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) + }; + + // Start operation + return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); +} + +sl_status_t sli_aes_cmac_radio(const unsigned char *key, + unsigned int keybits, + const unsigned char *input, + unsigned int length, + volatile unsigned char output[16]) +{ + uint32_t aes_config; + + switch (keybits) { + case 256: + aes_config = AES_MODEID_CMA | AES_MODEID_NO_CX | AES_MODEID_AES256 | AES_MODEID_ENCRYPT; + break; + case 192: + return SL_STATUS_NOT_SUPPORTED; + case 128: + aes_config = AES_MODEID_CMA | AES_MODEID_NO_CX | AES_MODEID_AES128 | AES_MODEID_ENCRYPT; + break; + default: + return SL_STATUS_INVALID_KEY; + } + + size_t pad_len = 16 - (length % 16); + if (pad_len == 16 && length > 0) { + pad_len = 0; + } + + if (length == 0) { + length = 16UL; + input = (const unsigned char *)&zeros; + } else { + length = (length + 15) & ~0xFUL; + } + + sli_radioaes_dma_descr_t aes_desc_pusher_data = { + .address = (uint32_t) output, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_data = { + .address = (uint32_t) input, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = length | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD | DMA_SG_TAG_SETINVALIDBYTES(pad_len) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_config = { + .address = (uint32_t) &aes_config, + .nextDescr = (uint32_t) &aes_desc_fetcher_data, + .lengthAndIrq = sizeof(aes_config), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_key = { + .address = (uint32_t) key, + .nextDescr = (uint32_t) &aes_desc_fetcher_config, + .lengthAndIrq = (uint32_t) (keybits / 8) | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) + }; + + // Start operation + return sli_radioaes_run_operation(&aes_desc_fetcher_key, &aes_desc_pusher_data); +} + +// +// CCM buffer authenticated decryption optimized for BLE +// +sl_status_t sli_ccm_auth_decrypt_ble(unsigned char *data, + size_t length, + const unsigned char *key, + const unsigned char *iv, + unsigned char header, + unsigned char *tag) +{ + return aes_ccm_ble(false, + data, + length, + key, + iv, + header, + (uint8_t *) tag); +} + +// +// CCM buffer encryption optimized for BLE +// +sl_status_t sli_ccm_encrypt_and_tag_ble(unsigned char *data, + size_t length, + const unsigned char *key, + const unsigned char *iv, + unsigned char header, + unsigned char *tag) +{ + return aes_ccm_ble(true, + data, + length, + key, + iv, + header, + tag); +} + +sl_status_t sli_ccm_zigbee(bool encrypt, + const unsigned char *data_in, + unsigned char *data_out, + size_t length, + const unsigned char *key, + const unsigned char *iv, + const unsigned char *aad, + size_t aad_len, + unsigned char *tag, + size_t tag_len) +{ + // Validated assumption: for ZigBee, the authenticated data + // length will always fit into a 16-bit length field, meaning + // the header will always be either 16 or 18 bytes long. + uint8_t header[18]; + + // Start with the 'flags' byte. It encodes whether there is AAD, + // and the length of the tag fields + header[0] = 0x01 // always 2 bytes of message length + | ((aad_len > 0) ? 0x40 : 0x00) // Set 'aflag' bit if there is AAD + | ((tag_len >= 4) ? (((tag_len - 2) / 2) << 3) : 0); // Encode tag length + + for (size_t i = 0; i < 13; i++) { + header[i + 1] = iv[i]; + } + + header[14] = (uint8_t) length >> 8; + header[15] = (uint8_t) length; + if (aad_len > 0) { + header[16] = (uint8_t) aad_len >> 8; // upper octet of AAD length + header[17] = (uint8_t) aad_len; // lower octet of AAD length + } + + return aes_ccm_radio(encrypt, + aad, + aad_len, + data_in, + data_out, + length, + key, + header, + (aad_len > 0 ? 18 : 16), + tag, + tag_len); +} + +// +// Process a table of BLE RPA device keys and look for a +// match against the supplied hash. Algorithm is AES-128. +// +int sli_process_ble_rpa(const unsigned char keytable[], + uint32_t keymask, + uint32_t prand, + uint32_t hash) +{ + int block; + int previous_block = -1, result = -1; + static const uint32_t aes_rpa_config = AES_MODEID_ECB + | AES_MODEID_NO_CX + | AES_MODEID_AES128 + | AES_MODEID_ENCRYPT; + + uint32_t rpa_data_in[AES_BLOCK_BYTES / sizeof(uint32_t)] = { 0 }; + volatile uint32_t rpa_data_out[AES_BLOCK_BYTES / sizeof(uint32_t)]; + sli_radioaes_state_t aes_ctx; + CORE_DECLARE_IRQ_STATE; + + rpa_data_in[3] = __REV(prand); + + sli_radioaes_dma_descr_t aes_desc_pusher_data = { + .address = (uint32_t) rpa_data_out, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_data = { + .address = (uint32_t) rpa_data_in, + .nextDescr = DMA_AXI_DESCR_NEXT_STOP, + .lengthAndIrq = AES_BLOCK_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISLAST | DMA_SG_TAG_ISDATA | DMA_SG_TAG_DATATYPE_AESPAYLOAD + }; + + sli_radioaes_dma_descr_t aes_desc_fetcher_config = { + .address = (uint32_t) &aes_rpa_config, + .nextDescr = (uint32_t) &aes_desc_fetcher_data, + .lengthAndIrq = sizeof(aes_rpa_config), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_CFG) + }; + + volatile sli_radioaes_dma_descr_t aes_desc_fetcher_key = { + .address = (uint32_t) NULL, // Filled out in each round of RPA check + .nextDescr = (uint32_t) &aes_desc_fetcher_config, + .lengthAndIrq = (uint32_t) AES_128_KEY_BYTES | (BLOCK_S_INCR_ADDR & BLOCK_S_FLAG_MASK_DMA_PROPS), + .tag = DMA_SG_ENGINESELECT_BA411E | DMA_SG_TAG_ISCONFIG | DMA_SG_TAG_SETCFGOFFSET(AES_OFFSET_KEY) + }; + + // Start operation + sl_status_t status = sli_radioaes_acquire(); + if (status == SL_STATUS_ISR) { + sli_radioaes_save_state(&aes_ctx); + } else if (status != SL_STATUS_OK) { + return -1; + } + + RADIOAES->CTRL = AES_CTRL_FETCHERSCATTERGATHER | AES_CTRL_PUSHERSCATTERGATHER; + + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + // Start with feeding the mask input + sli_radioaes_dma_descr_t mask_descr = SLI_RADIOAES_MASK_DESCRIPTOR(DMA_AXI_DESCR_NEXT_STOP); + RADIOAES->FETCHADDR = (uint32_t) &mask_descr; + RADIOAES->CMD = AES_CMD_STARTFETCHER; + #endif + + // Start a critical section to avoid preemption in-between loading of the RPA key + // and starting the corresponding data pusher. + CORE_ENTER_CRITICAL(); + + // Data output contains hash in the most significant word (WORD3). + // Descriptors for blocks that are not included in key mask will be skipped. + for (block = 0; block < RADIOAES_BLE_RPA_MAX_KEYS; block++) { + if ( keymask & (1U << block) ) { // Skip masked keys + // Handle pending interrupts while the peripheral is in 'preemptable' state + CORE_YIELD_CRITICAL(); + // Write key address and start operation + while (RADIOAES->STATUS & AES_STATUS_FETCHERBSY) { + // Wait for completion + } + aes_desc_fetcher_key.address = (uint32_t) &keytable[block * AES_128_KEY_BYTES]; + RADIOAES->FETCHADDR = (uint32_t) &aes_desc_fetcher_key; + + RADIOAES->CMD = AES_CMD_STARTFETCHER; + + // Wait for pusher from previous round to finish + while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { + // Wait for completion + } + RADIOAES->PUSHADDR = (uint32_t) &aes_desc_pusher_data; + + // Check previous results while AES is processing + if ((previous_block >= 0) && ((rpa_data_out[3] & 0xFFFFFF00) == __REV(hash)) ) { + // Make sure AES is finished before returning + RADIOAES->CMD = AES_CMD_STARTPUSHER; + result = previous_block; + break; + } + + // Start pusher so it is ready to push results when encryption is done + RADIOAES->CMD = AES_CMD_STARTPUSHER; + previous_block = block; + } + } + + CORE_EXIT_CRITICAL(); + + // Wait for last data and check it + while (RADIOAES->STATUS & AES_STATUS_PUSHERBSY) { + // Wait for completion + } + + if (status == SL_STATUS_ISR) { + sli_radioaes_restore_state(&aes_ctx); + } + + sli_radioaes_release(); + + if (result >= 0) { + return result; + } + + if ((rpa_data_out[3] & 0xFFFFFF00) == __REV(hash) ) { + return previous_block; + } + + // No match + return -1; +} + +void sli_aes_seed_mask(void) +{ + // Acquiring and releasing the peripheral should ensure the mask is properly + // set. + (void) sli_radioaes_acquire(); + (void) sli_radioaes_release(); +} + +/// @endcond +#endif // defined(RADIOAES_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c index deb542c..ce81347 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c @@ -1,203 +1,203 @@ -/***************************************************************************//** - * @file - * @brief Threadsafe utilities for RADIOAES peripheral. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_device.h" - -#if defined(RADIOAES_PRESENT) -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include "sli_radioaes_management.h" -#include "sli_se_manager_osal.h" -#include "em_core.h" - -#if defined(SL_SE_MANAGER_THREADING) -static se_manager_osal_mutex_t radioaes_lock = { 0 }; -static volatile bool radioaes_lock_initialized = false; -#endif - -#if defined(SLI_RADIOAES_REQUIRES_MASKING) - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_PSA_CRYPTO_PRESENT) -// If the PSA Crypto core is present, use its randomness abstraction to get -// the initial mask seed. -#include "psa/crypto.h" -#else -// If the PSA Crypto core is not present, we need to target the TRNG driver -// directly to get the initial mask seed. We'll always have an external randomness -// provider function on devices containing a RADIOAES instance. -#include "sli_psa_driver_common.h" -#endif -#include "sl_assert.h" - -uint32_t sli_radioaes_mask = 0; - -static void sli_radioaes_update_mask(void) -{ - if (sli_radioaes_mask == 0) { - // Mask has not been initialized yet, get a random value to start -#if defined(SL_CATALOG_PSA_CRYPTO_PRESENT) - psa_status_t status = psa_generate_random((uint8_t*)&sli_radioaes_mask, sizeof(sli_radioaes_mask)); - EFM_ASSERT(status == PSA_SUCCESS); -#else - size_t out_len = 0; - psa_status_t status = mbedtls_psa_external_get_random(NULL, (uint8_t*)&sli_radioaes_mask, sizeof(sli_radioaes_mask), &out_len); - EFM_ASSERT(status == PSA_SUCCESS); - EFM_ASSERT(out_len == sizeof(sli_radioaes_mask)); -#endif - } - - // Use a different mask for each new operation - // The masking logic requires the upper mask bit to be set - sli_radioaes_mask = (sli_radioaes_mask + 1) | (1UL << 31); -} -#endif // SLI_RADIOAES_REQUIRES_MASKING - -sl_status_t sli_radioaes_acquire(void) -{ -#if defined(_CMU_CLKEN0_MASK) - CMU->CLKEN0 |= CMU_CLKEN0_RADIOAES; -#endif - CMU->RADIOCLKCTRL |= CMU_RADIOCLKCTRL_EN; - if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { - // IRQ: need to store & restore RADIOAES registers - while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { - // Wait for completion of the previous operation, since the RADIOAES - // peripheral does not support preemption of an operation in progress. - } - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - // The mask should have been initialized from non-ISR context by calling - // sl_mbedtls_init, before using the radioaes. - EFM_ASSERT(sli_radioaes_mask != 0); - #endif - return SL_STATUS_ISR; - } else { -#if defined(SL_SE_MANAGER_THREADING) - sl_status_t ret = SL_STATUS_OK; - - // Non-IRQ, RTOS available: take mutex - // Initialize mutex if that hasn't happened yet - - // Check flag first before going into a critical section, to avoid going into - // a critical section on every single acquire() call. Since the _initialized - // flag only transitions false -> true, we can in 99% of the calls avoid the - // critical section. - if (!radioaes_lock_initialized) { - int32_t kernel_lock_state = 0; - osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - kernel_lock_state = se_manager_osal_kernel_lock(); - if (kernel_lock_state < 0) { - return SL_STATUS_SUSPENDED; - } - } - - // Check the flag again after entering the critical section. Now that we're - // in the critical section, we can be sure that we are the only ones looking - // at the flag and no-one is interrupting us during its manipulation. - if (!radioaes_lock_initialized) { - ret = se_manager_osal_init_mutex(&radioaes_lock); - if (ret == SL_STATUS_OK) { - radioaes_lock_initialized = true; - } - } - - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { - return SL_STATUS_INVALID_STATE; - } - } - } - - if (ret == SL_STATUS_OK) { - ret = se_manager_osal_take_mutex(&radioaes_lock); - } - - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - if (ret == SL_STATUS_OK) { - sli_radioaes_update_mask(); - } - #endif - - return ret; -#else - // Non-IRQ, no RTOS: busywait - while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { - // Wait for completion - } - #if defined(SLI_RADIOAES_REQUIRES_MASKING) - sli_radioaes_update_mask(); - #endif - return SL_STATUS_OK; -#endif - } -} - -sl_status_t sli_radioaes_release(void) -{ - // IRQ: nothing to do - if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { - return SL_STATUS_OK; - } -#if defined(SL_SE_MANAGER_THREADING) - // Non-IRQ, RTOS available: free mutex - return se_manager_osal_give_mutex(&radioaes_lock); -#else - // Non-IRQ, no RTOS: nothing to do. - return SL_STATUS_OK; -#endif -} - -sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - ctx->FETCHADDR = RADIOAES->FETCHADDR; - ctx->PUSHADDR = RADIOAES->PUSHADDR; - - CORE_EXIT_CRITICAL(); - return SL_STATUS_OK; -} - -sl_status_t sli_radioaes_restore_state(sli_radioaes_state_t *ctx) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - RADIOAES->FETCHADDR = ctx->FETCHADDR; - RADIOAES->PUSHADDR = ctx->PUSHADDR; - - CORE_EXIT_CRITICAL(); - return SL_STATUS_OK; -} - -/// @endcond -#endif //defined(RADIOAES_PRESENT) +/***************************************************************************//** + * @file + * @brief Threadsafe utilities for RADIOAES peripheral. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" + +#if defined(RADIOAES_PRESENT) +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "sli_radioaes_management.h" +#include "sli_se_manager_osal.h" +#include "em_core.h" + +#if defined(SL_SE_MANAGER_THREADING) +static se_manager_osal_mutex_t radioaes_lock = { 0 }; +static volatile bool radioaes_lock_initialized = false; +#endif + +#if defined(SLI_RADIOAES_REQUIRES_MASKING) + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_PSA_CRYPTO_PRESENT) +// If the PSA Crypto core is present, use its randomness abstraction to get +// the initial mask seed. +#include "psa/crypto.h" +#else +// If the PSA Crypto core is not present, we need to target the TRNG driver +// directly to get the initial mask seed. We'll always have an external randomness +// provider function on devices containing a RADIOAES instance. +#include "sli_psa_driver_common.h" +#endif +#include "sl_assert.h" + +uint32_t sli_radioaes_mask = 0; + +static void sli_radioaes_update_mask(void) +{ + if (sli_radioaes_mask == 0) { + // Mask has not been initialized yet, get a random value to start +#if defined(SL_CATALOG_PSA_CRYPTO_PRESENT) + psa_status_t status = psa_generate_random((uint8_t*)&sli_radioaes_mask, sizeof(sli_radioaes_mask)); + EFM_ASSERT(status == PSA_SUCCESS); +#else + size_t out_len = 0; + psa_status_t status = mbedtls_psa_external_get_random(NULL, (uint8_t*)&sli_radioaes_mask, sizeof(sli_radioaes_mask), &out_len); + EFM_ASSERT(status == PSA_SUCCESS); + EFM_ASSERT(out_len == sizeof(sli_radioaes_mask)); +#endif + } + + // Use a different mask for each new operation + // The masking logic requires the upper mask bit to be set + sli_radioaes_mask = (sli_radioaes_mask + 1) | (1UL << 31); +} +#endif // SLI_RADIOAES_REQUIRES_MASKING + +sl_status_t sli_radioaes_acquire(void) +{ +#if defined(_CMU_CLKEN0_MASK) + CMU->CLKEN0 |= CMU_CLKEN0_RADIOAES; +#endif + CMU->RADIOCLKCTRL |= CMU_RADIOCLKCTRL_EN; + if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { + // IRQ: need to store & restore RADIOAES registers + while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { + // Wait for completion of the previous operation, since the RADIOAES + // peripheral does not support preemption of an operation in progress. + } + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + // The mask should have been initialized from non-ISR context by calling + // sl_mbedtls_init, before using the radioaes. + EFM_ASSERT(sli_radioaes_mask != 0); + #endif + return SL_STATUS_ISR; + } else { +#if defined(SL_SE_MANAGER_THREADING) + sl_status_t ret = SL_STATUS_OK; + + // Non-IRQ, RTOS available: take mutex + // Initialize mutex if that hasn't happened yet + + // Check flag first before going into a critical section, to avoid going into + // a critical section on every single acquire() call. Since the _initialized + // flag only transitions false -> true, we can in 99% of the calls avoid the + // critical section. + if (!radioaes_lock_initialized) { + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = se_manager_osal_kernel_get_state(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = se_manager_osal_kernel_lock(); + if (kernel_lock_state < 0) { + return SL_STATUS_SUSPENDED; + } + } + + // Check the flag again after entering the critical section. Now that we're + // in the critical section, we can be sure that we are the only ones looking + // at the flag and no-one is interrupting us during its manipulation. + if (!radioaes_lock_initialized) { + ret = se_manager_osal_init_mutex(&radioaes_lock); + if (ret == SL_STATUS_OK) { + radioaes_lock_initialized = true; + } + } + + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (se_manager_osal_kernel_restore_lock(kernel_lock_state) < 0) { + return SL_STATUS_INVALID_STATE; + } + } + } + + if (ret == SL_STATUS_OK) { + ret = se_manager_osal_take_mutex(&radioaes_lock); + } + + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + if (ret == SL_STATUS_OK) { + sli_radioaes_update_mask(); + } + #endif + + return ret; +#else + // Non-IRQ, no RTOS: busywait + while (RADIOAES->STATUS & (AES_STATUS_FETCHERBSY | AES_STATUS_PUSHERBSY | AES_STATUS_SOFTRSTBSY)) { + // Wait for completion + } + #if defined(SLI_RADIOAES_REQUIRES_MASKING) + sli_radioaes_update_mask(); + #endif + return SL_STATUS_OK; +#endif + } +} + +sl_status_t sli_radioaes_release(void) +{ + // IRQ: nothing to do + if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { + return SL_STATUS_OK; + } +#if defined(SL_SE_MANAGER_THREADING) + // Non-IRQ, RTOS available: free mutex + return se_manager_osal_give_mutex(&radioaes_lock); +#else + // Non-IRQ, no RTOS: nothing to do. + return SL_STATUS_OK; +#endif +} + +sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + ctx->FETCHADDR = RADIOAES->FETCHADDR; + ctx->PUSHADDR = RADIOAES->PUSHADDR; + + CORE_EXIT_CRITICAL(); + return SL_STATUS_OK; +} + +sl_status_t sli_radioaes_restore_state(sli_radioaes_state_t *ctx) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + RADIOAES->FETCHADDR = ctx->FETCHADDR; + RADIOAES->PUSHADDR = ctx->PUSHADDR; + + CORE_EXIT_CRITICAL(); + return SL_STATUS_OK; +} + +/// @endcond +#endif //defined(RADIOAES_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h index b07b98b..c6f941c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.h @@ -1,101 +1,101 @@ -/**************************************************************************/ /** - * @file - * @brief Threadsafe utilities for RADIOAES peripheral. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SLI_RADIOAES_MANAGEMENT_H -#define SLI_RADIOAES_MANAGEMENT_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include -#include "sl_status.h" - -#if defined(RADIOAES_PRESENT) - -/***************************************************************************//** - * @addtogroup sli_protocol_crypto - * @{ - ******************************************************************************/ - -/// -/// @brief Structure that represents the state of the RADIOAES peripheral -/// (in scatter-gather mode). -/// -typedef struct { - uint32_t FETCHADDR; ///< Fetcher Address - uint32_t PUSHADDR; ///< Pusher Address -} sli_radioaes_state_t; - -#if defined(SLI_RADIOAES_REQUIRES_MASKING) -/// Static variable containing the masking value for the RADIOAES -extern uint32_t sli_radioaes_mask; -#endif // SLI_RADIOAES_REQUIRES_MASKING - -/***************************************************************************//** - * @brief Acquire RADIOAES access - * - * @return SL_STATUS_OK if successful and resource is idle, - * SL_STATUS_ISR if successful but resource was preempted, in - * which case the caller is responsible for saving state, - * relevant status code on error - ******************************************************************************/ -sl_status_t sli_radioaes_acquire(void); - -/***************************************************************************//** - * @brief Release RADIOAES access - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_radioaes_release(void); - -/***************************************************************************//** - * @brief Save RADIOAES register state to RAM - * - * @param ctx Context struct to save register state into - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx); - -/***************************************************************************//** - * @brief Restore RADIOAES register state from RAM - * - * @param ctx Context struct to restore register state from - * - * @return SL_STATUS_OK if successful, relevant status code on error - ******************************************************************************/ -sl_status_t sli_radioaes_restore_state(sli_radioaes_state_t *ctx); - -#ifdef __cplusplus -} -#endif - -/// @} (end addtogroup sli_protocol_crypto) -#endif // RADIOAES_PRESENT -/// @endcond -#endif // SLI_RADIOAES_MANAGEMENT_H +/**************************************************************************/ /** + * @file + * @brief Threadsafe utilities for RADIOAES peripheral. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_RADIOAES_MANAGEMENT_H +#define SLI_RADIOAES_MANAGEMENT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include +#include "sl_status.h" + +#if defined(RADIOAES_PRESENT) + +/***************************************************************************//** + * @addtogroup sli_protocol_crypto + * @{ + ******************************************************************************/ + +/// +/// @brief Structure that represents the state of the RADIOAES peripheral +/// (in scatter-gather mode). +/// +typedef struct { + uint32_t FETCHADDR; ///< Fetcher Address + uint32_t PUSHADDR; ///< Pusher Address +} sli_radioaes_state_t; + +#if defined(SLI_RADIOAES_REQUIRES_MASKING) +/// Static variable containing the masking value for the RADIOAES +extern uint32_t sli_radioaes_mask; +#endif // SLI_RADIOAES_REQUIRES_MASKING + +/***************************************************************************//** + * @brief Acquire RADIOAES access + * + * @return SL_STATUS_OK if successful and resource is idle, + * SL_STATUS_ISR if successful but resource was preempted, in + * which case the caller is responsible for saving state, + * relevant status code on error + ******************************************************************************/ +sl_status_t sli_radioaes_acquire(void); + +/***************************************************************************//** + * @brief Release RADIOAES access + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_radioaes_release(void); + +/***************************************************************************//** + * @brief Save RADIOAES register state to RAM + * + * @param ctx Context struct to save register state into + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_radioaes_save_state(sli_radioaes_state_t *ctx); + +/***************************************************************************//** + * @brief Restore RADIOAES register state from RAM + * + * @param ctx Context struct to restore register state from + * + * @return SL_STATUS_OK if successful, relevant status code on error + ******************************************************************************/ +sl_status_t sli_radioaes_restore_state(sli_radioaes_state_t *ctx); + +#ifdef __cplusplus +} +#endif + +/// @} (end addtogroup sli_protocol_crypto) +#endif // RADIOAES_PRESENT +/// @endcond +#endif // SLI_RADIOAES_MANAGEMENT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h index d8410a9..412602c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/cryptoacc_management.h @@ -1,99 +1,99 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs CRYPTOACC device management interface. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef CRYPTOACC_MANAGEMENT_H -#define CRYPTOACC_MANAGEMENT_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/***************************************************************************//** - * \addtogroup sl_crypto_plugins - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_cryptoacc_management CRYPTOACC device instance management - * \brief Management functions for the CRYPTOACC. These functions take care - * of not having two 'owners' simultaneously for the same CRYPTOACC - * device, which could potentially be causing conflicts and system - * lock-up. - * \{ - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "psa/crypto.h" - -//------------------------------------------------------------------------------ -// Function Declarations - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Get ownership of the crypto device - * - * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error - */ -psa_status_t cryptoacc_management_acquire(void); - -/** - * \brief Release ownership of the crypto device - * - * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error - */ -psa_status_t cryptoacc_management_release(void); - -/** - * \brief Set up hardware SCA countermeasures - * - * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error - * - * \note Will try to set up CM even if errors are returned early on. - * In that case, the function will return the first error code that is - * encountered, but only after CM has been set up. - */ -psa_status_t cryptoacc_initialize_countermeasures(void); - -#ifdef __cplusplus -} -#endif - -#endif // SLI_MBEDTLS_DEVICE_VSE - -/** \} (end addtogroup sl_cryptoacc_management) */ -/** \} (end addtogroup sl_crypto_plugins) */ - -/// @endcond - -#endif // CRYPTOACC_MANAGEMENT_H +/***************************************************************************//** + * @file + * @brief Silicon Labs CRYPTOACC device management interface. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef CRYPTOACC_MANAGEMENT_H +#define CRYPTOACC_MANAGEMENT_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_crypto_plugins + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_cryptoacc_management CRYPTOACC device instance management + * \brief Management functions for the CRYPTOACC. These functions take care + * of not having two 'owners' simultaneously for the same CRYPTOACC + * device, which could potentially be causing conflicts and system + * lock-up. + * \{ + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +//------------------------------------------------------------------------------ +// Function Declarations + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get ownership of the crypto device + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + */ +psa_status_t cryptoacc_management_acquire(void); + +/** + * \brief Release ownership of the crypto device + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + */ +psa_status_t cryptoacc_management_release(void); + +/** + * \brief Set up hardware SCA countermeasures + * + * \return PSA_SUCCESS if successful, PSA_ERROR_HARDWARE_FAILURE on error + * + * \note Will try to set up CM even if errors are returned early on. + * In that case, the function will return the first error code that is + * encountered, but only after CM has been set up. + */ +psa_status_t cryptoacc_initialize_countermeasures(void); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_MBEDTLS_DEVICE_VSE + +/** \} (end addtogroup sl_cryptoacc_management) */ +/** \} (end addtogroup sl_crypto_plugins) */ + +/// @endcond + +#endif // CRYPTOACC_MANAGEMENT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/error.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/error.h index 7c1f84b..0285e2d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/error.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/error.h @@ -1,26 +1,26 @@ -/***************************************************************************//** - * # License - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. - * - ******************************************************************************/ - -#ifndef __SL_PSA_ERROR_H__ -#define __SL_PSA_ERROR_H__ - -// Supplementary error codes for the SPM and RoT Services as defined in PSA -// Firmware Framework v1.0, which are not present in crypto_values.h. For non- -// TrustZone SKL builds, this file does not include anything at all. This is -// because our driver implementations only uses error codes that already exist -// in crypto_values.h. -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - #include "trusted-firmware-m/interface/include/psa/error.h" -#endif - -#endif // __SL_PSA_ERROR_H__ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ + +#ifndef __SL_PSA_ERROR_H__ +#define __SL_PSA_ERROR_H__ + +// Supplementary error codes for the SPM and RoT Services as defined in PSA +// Firmware Framework v1.0, which are not present in crypto_values.h. For non- +// TrustZone SKL builds, this file does not include anything at all. This is +// because our driver implementations only uses error codes that already exist +// in crypto_values.h. +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + #include "trusted-firmware-m/interface/include/psa/error.h" +#endif + +#endif // __SL_PSA_ERROR_H__ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/internal_trusted_storage.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/internal_trusted_storage.h index 68b1505..bfb0085 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/internal_trusted_storage.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/internal_trusted_storage.h @@ -1,29 +1,29 @@ -/***************************************************************************//** - * # License - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. - * - ******************************************************************************/ -/** \file internal_trusted_storage.h - * \brief Interface and declarations of trusted storage. - */ - -#ifndef INTERNAL_TRUSTED_STORAGE_H -#define INTERNAL_TRUSTED_STORAGE_H - -// We need to add condition for TFM internal_trusted_storage.h, in case that -// -cp option is not selected. -#if defined(SL_TRUSTZONE_SECURE) -#include "trusted-firmware-m/interface/include/psa/internal_trusted_storage.h" -#else -#include "psa_crypto_its.h" -#include "sli_internal_trusted_storage.h" -#endif - -#endif /* INTERNAL_TRUSTED_STORAGE_H */ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ +/** \file internal_trusted_storage.h + * \brief Interface and declarations of trusted storage. + */ + +#ifndef INTERNAL_TRUSTED_STORAGE_H +#define INTERNAL_TRUSTED_STORAGE_H + +// We need to add condition for TFM internal_trusted_storage.h, in case that +// -cp option is not selected. +#if defined(SL_TRUSTZONE_SECURE) +#include "trusted-firmware-m/interface/include/psa/internal_trusted_storage.h" +#else +#include "psa_crypto_its.h" +#include "sli_internal_trusted_storage.h" +#endif + +#endif /* INTERNAL_TRUSTED_STORAGE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/sli_internal_trusted_storage.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/sli_internal_trusted_storage.h index 31d5869..66f9785 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/sli_internal_trusted_storage.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/psa/sli_internal_trusted_storage.h @@ -1,131 +1,131 @@ -/***************************************************************************//** - * # License - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is Third Party Software licensed by Silicon Labs from a third party - * and is governed by the sections of the MSLA applicable to Third Party - * Software and the additional terms set forth below. - * - ******************************************************************************/ -/** \file sli_internal_trusted_storage.h - * \brief Internal interface and declarations of trusted storage. - */ - -#ifndef SLI_INTERNAL_TRUSTED_STORAGE_H -#define SLI_INTERNAL_TRUSTED_STORAGE_H - -#include -#include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) -#define PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE (1 << 3) -#endif // TFM_CONFIG_SL_SECURE_LIBRARY - -psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, - mbedtls_svc_key_id_t new_id); - -/** - * \brief Check if the ITS encryption is enabled - * - * \details The function is added in order to support runtime checking - * needed by trustzone-agnostic libraries - * - * \retval PSA_SUCCESS ITS encryption is enabled - * \retval PSA_ERROR_NOT_SUPPORTED ITS encryption is not supported - */ -psa_status_t sli_psa_its_encrypted(void); - -#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) -/** - * \brief Set the root key to be used when deriving session keys for ITS encryption. - * - * \param[in] root_key Buffer containing the root key. - * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The key was successfully set. - * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. - * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. - */ -psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size); -#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) - -/* Magic values for ITS metadata versions */ -#define SLI_PSA_ITS_META_MAGIC_V1 (0x05E175D1UL) -#define SLI_PSA_ITS_META_MAGIC_V2 (0x5E175D10UL) - -/* Allocated range of NVM3 IDs for PSA ITS usage */ -#define SLI_PSA_ITS_NVM3_RANGE_SIZE (0x00400UL) -#if (SL_PSA_ITS_SUPPORT_V3_DRIVER) -#define SLI_PSA_ITS_NVM3_RANGE_END (0x87100UL) -#define SLI_PSA_ITS_NVM3_RANGE_START (SLI_PSA_ITS_NVM3_RANGE_END - SLI_PSA_ITS_NVM3_RANGE_SIZE) -#else -#define SLI_PSA_ITS_NVM3_RANGE_BASE (0x83100UL) -#endif - -#ifndef SL_PSA_ITS_MAX_FILES -#define SL_PSA_ITS_MAX_FILES SLI_PSA_ITS_NVM3_RANGE_SIZE -#endif - -#if (SL_PSA_ITS_SUPPORT_V3_DRIVER) - -#if !defined(SL_PSA_ITS_REMOVE_V1_HEADER_SUPPORT) && SL_PSA_ITS_SUPPORT_V1_DRIVER -#define SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL -#endif - -#if SL_PSA_ITS_SUPPORT_V2_DRIVER -#define SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER (0x83100UL) -#define SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER \ - SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER + SLI_PSA_ITS_NVM3_RANGE_SIZE -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) -// Define some cryptographic constants if not already set. This depends on the underlying -// crypto accelerator in use (CRYPTOACC has these defines, but not SEMAILBOX). -#define AES_GCM_MAC_SIZE 16 -#define AES_GCM_IV_SIZE (12) - -#define SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD (AES_GCM_IV_SIZE + AES_GCM_MAC_SIZE) -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// Due to alignment constraints on the 64-bit UID, the v2 header struct is -// serialized to 16 bytes instead of the 24 bytes the v1 header compiles to. -typedef struct { - uint32_t magic; - psa_storage_create_flags_t flags; - psa_storage_uid_t uid; -} sli_its_file_meta_v2_t; - -#if defined(SLI_PSA_ITS_ENCRYPTED) -typedef struct { - uint8_t iv[AES_GCM_IV_SIZE]; - // When encrypted & authenticated, MAC is stored at the end of the data array - uint8_t data[]; -} sli_its_encrypted_blob_t; -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) -psa_status_t sli_encrypt_its_file(sli_its_file_meta_v2_t *metadata, - uint8_t *plaintext, - size_t plaintext_size, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - size_t *blob_length); -#endif - -#endif // SL_PSA_ITS_SUPPORT_V3_DRIVER -#ifdef __cplusplus -} -#endif - -#endif /* SLI_INTERNAL_TRUSTED_STORAGE_H */ +/***************************************************************************//** + * # License + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is Third Party Software licensed by Silicon Labs from a third party + * and is governed by the sections of the MSLA applicable to Third Party + * Software and the additional terms set forth below. + * + ******************************************************************************/ +/** \file sli_internal_trusted_storage.h + * \brief Internal interface and declarations of trusted storage. + */ + +#ifndef SLI_INTERNAL_TRUSTED_STORAGE_H +#define SLI_INTERNAL_TRUSTED_STORAGE_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +#define PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE (1 << 3) +#endif // TFM_CONFIG_SL_SECURE_LIBRARY + +psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, + mbedtls_svc_key_id_t new_id); + +/** + * \brief Check if the ITS encryption is enabled + * + * \details The function is added in order to support runtime checking + * needed by trustzone-agnostic libraries + * + * \retval PSA_SUCCESS ITS encryption is enabled + * \retval PSA_ERROR_NOT_SUPPORTED ITS encryption is not supported + */ +psa_status_t sli_psa_its_encrypted(void); + +#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +/** + * \brief Set the root key to be used when deriving session keys for ITS encryption. + * + * \param[in] root_key Buffer containing the root key. + * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The key was successfully set. + * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. + * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. + */ +psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size); +#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) + +/* Magic values for ITS metadata versions */ +#define SLI_PSA_ITS_META_MAGIC_V1 (0x05E175D1UL) +#define SLI_PSA_ITS_META_MAGIC_V2 (0x5E175D10UL) + +/* Allocated range of NVM3 IDs for PSA ITS usage */ +#define SLI_PSA_ITS_NVM3_RANGE_SIZE (0x00400UL) +#if (SL_PSA_ITS_SUPPORT_V3_DRIVER) +#define SLI_PSA_ITS_NVM3_RANGE_END (0x87100UL) +#define SLI_PSA_ITS_NVM3_RANGE_START (SLI_PSA_ITS_NVM3_RANGE_END - SLI_PSA_ITS_NVM3_RANGE_SIZE) +#else +#define SLI_PSA_ITS_NVM3_RANGE_BASE (0x83100UL) +#endif + +#ifndef SL_PSA_ITS_MAX_FILES +#define SL_PSA_ITS_MAX_FILES SLI_PSA_ITS_NVM3_RANGE_SIZE +#endif + +#if (SL_PSA_ITS_SUPPORT_V3_DRIVER) + +#if !defined(SL_PSA_ITS_REMOVE_V1_HEADER_SUPPORT) && SL_PSA_ITS_SUPPORT_V1_DRIVER +#define SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL +#endif + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +#define SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER (0x83100UL) +#define SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER \ + SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER + SLI_PSA_ITS_NVM3_RANGE_SIZE +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// Define some cryptographic constants if not already set. This depends on the underlying +// crypto accelerator in use (CRYPTOACC has these defines, but not SEMAILBOX). +#define AES_GCM_MAC_SIZE 16 +#define AES_GCM_IV_SIZE (12) + +#define SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD (AES_GCM_IV_SIZE + AES_GCM_MAC_SIZE) +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// Due to alignment constraints on the 64-bit UID, the v2 header struct is +// serialized to 16 bytes instead of the 24 bytes the v1 header compiles to. +typedef struct { + uint32_t magic; + psa_storage_create_flags_t flags; + psa_storage_uid_t uid; +} sli_its_file_meta_v2_t; + +#if defined(SLI_PSA_ITS_ENCRYPTED) +typedef struct { + uint8_t iv[AES_GCM_IV_SIZE]; + // When encrypted & authenticated, MAC is stored at the end of the data array + uint8_t data[]; +} sli_its_encrypted_blob_t; +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) +psa_status_t sli_encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length); +#endif + +#endif // SL_PSA_ITS_SUPPORT_V3_DRIVER +#ifdef __cplusplus +} +#endif + +#endif /* SLI_INTERNAL_TRUSTED_STORAGE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h index b2c4784..117198f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_driver_trng.h @@ -1,87 +1,87 @@ -/******************************************************************************* - * @file - * @brief Silicon Labs PSA Crypto TRNG driver functions for VSE devices. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_CRYPTOACC_DRIVER_TRNG_H_ -#define SLI_CRYPTOACC_DRIVER_TRNG_H_ - -#include "psa/crypto.h" - -#include "stddef.h" - -#ifdef __cplusplus -extern "C" { -#endif - -//------------------------------------------------------------------------------ -// Global Variable Declarations - -/* - * \brief - * Global struct to be used by functions in the LibCryptoSoC library when - * generating randomness. - * - * \note - * The function pointed to by tis struct expects to the CRYPTOACC peripheral - * to be clocked before being called. - * - * \attention - * The use of this wrapper struct should __not__ be replaced by a naive struct - * containing a pointer to sx_trng_fill_blk(). - * - * \warning - * Since the function pointed to by this wrapper is not able (or expected) to - * return an error code, any errors are therefore handled by resetting the - * system. This is deemed appropriate since a failed randomness generation may - * have severe security implications. - */ -extern const struct sx_rng sli_cryptoacc_trng_wrapper; - -//------------------------------------------------------------------------------ -// Function Declarations - -/* - * \brief - * Function for getting random data from the TRNG. - * - * \note - * This function will make attempted reads until the requested amount of - * randomness has been collected. If the function returns successfully, it - * can be assumed that the full length of requested data has been written. - * - * \return - * PSA_SUCCESS if no error was encountered, else PSA_ERROR_HARDWARE_FAILURE. - */ -psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len); - -#ifdef __cplusplus -} -#endif - -#endif // SLI_CRYPTOACC_DRIVER_TRNG_H_ +/******************************************************************************* + * @file + * @brief Silicon Labs PSA Crypto TRNG driver functions for VSE devices. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_CRYPTOACC_DRIVER_TRNG_H_ +#define SLI_CRYPTOACC_DRIVER_TRNG_H_ + +#include "psa/crypto.h" + +#include "stddef.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//------------------------------------------------------------------------------ +// Global Variable Declarations + +/* + * \brief + * Global struct to be used by functions in the LibCryptoSoC library when + * generating randomness. + * + * \note + * The function pointed to by tis struct expects to the CRYPTOACC peripheral + * to be clocked before being called. + * + * \attention + * The use of this wrapper struct should __not__ be replaced by a naive struct + * containing a pointer to sx_trng_fill_blk(). + * + * \warning + * Since the function pointed to by this wrapper is not able (or expected) to + * return an error code, any errors are therefore handled by resetting the + * system. This is deemed appropriate since a failed randomness generation may + * have severe security implications. + */ +extern const struct sx_rng sli_cryptoacc_trng_wrapper; + +//------------------------------------------------------------------------------ +// Function Declarations + +/* + * \brief + * Function for getting random data from the TRNG. + * + * \note + * This function will make attempted reads until the requested amount of + * randomness has been collected. If the function returns successfully, it + * can be assumed that the full length of requested data has been written. + * + * \return + * PSA_SUCCESS if no error was encountered, else PSA_ERROR_HARDWARE_FAILURE. + */ +psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif // SLI_CRYPTOACC_DRIVER_TRNG_H_ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h index 7388156..9be12e6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_functions.h @@ -1,350 +1,350 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver functions for CRYPTOACC. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H -#define SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_cryptoacc CRYPTOACC transparent PSA driver - * \brief Driver plugin for Silicon Labs CRYPTOACC peripheral adhering to the - * PSA transparent accelerator specification. - * \{ - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sli_cryptoacc_transparent_types.h" -// Replace inclusion of crypto_driver_common.h with the new psa driver interface -// header file when it becomes available. -#include "psa/crypto_driver_common.h" - -/* NOTE: This header file will be autogenerated by PSA Crypto build system based on - * the definitions in sli_cryptoacc_transparent_driver.json. However, until such a system is - * in place, we rely on manually writing the file */ - -#ifdef __cplusplus -extern "C" { -#endif - -psa_status_t sli_cryptoacc_transparent_driver_init(void); - -psa_status_t sli_cryptoacc_transparent_driver_deinit(void); - -psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, - const uint8_t *input, - size_t input_length); - -psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation); - -psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, - sli_cryptoacc_transparent_hash_operation_t *target_operation); - -psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *iv, - size_t iv_length, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length); - -psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length); - -psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation); - -psa_status_t sli_cryptoacc_transparent_sign_hash(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); - -psa_status_t sli_cryptoacc_transparent_verify_hash(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length); - -psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, - const uint8_t *input, - size_t input_length); - -psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length); - -psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation); - -psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length); - -psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length); - -psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - const uint8_t* tag, - size_t tag_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length); - -psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length); - -psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *input, - size_t input_length); - -psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length); - -psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length); - -psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation); - -psa_status_t sli_cryptoacc_transparent_generate_key(const psa_key_attributes_t *attributes, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_length); - -psa_status_t sli_cryptoacc_transparent_export_public_key(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length); - -psa_status_t sli_cryptoacc_transparent_import_key(const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_buffer_length, - size_t *bits); - -psa_status_t sli_cryptoacc_transparent_key_agreement(psa_algorithm_t alg, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -#ifdef __cplusplus -} -#endif - -#endif // CRYPTOACC_PRESENT - -/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ -/** \} (end addtogroup sl_psa_drivers) */ - -/// @endcond - -#endif // SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver functions for CRYPTOACC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H +#define SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc CRYPTOACC transparent PSA driver + * \brief Driver plugin for Silicon Labs CRYPTOACC peripheral adhering to the + * PSA transparent accelerator specification. + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +/* NOTE: This header file will be autogenerated by PSA Crypto build system based on + * the definitions in sli_cryptoacc_transparent_driver.json. However, until such a system is + * in place, we rely on manually writing the file */ + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_cryptoacc_transparent_driver_init(void); + +psa_status_t sli_cryptoacc_transparent_driver_deinit(void); + +psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, + sli_cryptoacc_transparent_hash_operation_t *target_operation); + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_sign_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +psa_status_t sli_cryptoacc_transparent_verify_hash(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); + +psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length); + +psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation); + +psa_status_t sli_cryptoacc_transparent_generate_key(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_length); + +psa_status_t sli_cryptoacc_transparent_export_public_key(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +psa_status_t sli_cryptoacc_transparent_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits); + +psa_status_t sli_cryptoacc_transparent_key_agreement(psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#ifdef __cplusplus +} +#endif + +#endif // CRYPTOACC_PRESENT + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_CRYPTOACC_TRANSPARENT_FUNCTIONS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h index 6ddf0bd..4970c9f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_cryptoacc_transparent_types.h @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver API Types for CRYPTOACC. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SLI_CRYPTOACC_TRANSPARENT_TYPES_H -#define SLI_CRYPTOACC_TRANSPARENT_TYPES_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -/***************************************************************************//** - * \addtogroup sl_psa_drivers - * \{ - ******************************************************************************/ - -/***************************************************************************//** - * \addtogroup sl_psa_drivers_cryptoacc - * \{ - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sx_hash.h" -#include "sx_aes.h" -#include "sl_enum.h" -// Replace inclusion of crypto_driver_common.h with the new psa driver interface -// header file when it becomes available. -#include "psa/crypto_driver_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -SL_ENUM(sli_aes_mode_t) { - SLI_AES_ENC = 1, - SLI_AES_DEC = 2, -}; - -typedef struct { - sx_hash_fct_t hash_type; ///< Hash type - uint32_t total; ///< Number of bytes processed - uint8_t state[32]; ///< Intermediate digest state - uint8_t buffer[64]; ///< Data block being processed -} sli_cryptoacc_transparent_hash_operation_t; - -typedef struct { - sli_aes_mode_t direction; ///< Cipher direction (encrypt/decrypt) - psa_algorithm_t alg; ///< Algorithm (cipher and mode of operation) - uint8_t key[32]; ///< Key buffer - size_t key_len; ///< Length of key in bytes - uint8_t iv[16]; ///< IV buffer - size_t iv_len; ///< Length of IV in bytes - uint8_t streaming_block[16]; ///< Buffer for intermediate results - size_t processed_length; ///< Number of bytes processed -} sli_cryptoacc_transparent_cipher_operation_t; - -typedef union { - struct { - psa_algorithm_t alg; ///< MAC type - uint8_t key[32]; ///< key buffer - size_t key_len; ///< key length - uint8_t current_block[16]; ///< current and potentially last block - size_t current_block_len; ///< current number of bytes in current block - uint8_t cmac_ctx[BLK_CIPHER_CTX_SIZE]; ///< CMAC state context - } cipher_mac; - #if defined(PSA_WANT_ALG_HMAC) - struct { - psa_algorithm_t alg; ///< HMAC type - sli_cryptoacc_transparent_hash_operation_t hash_ctx; ///< Hash context for multipart HMAC - uint8_t opad[64]; ///< opad for use during finalisation - } hmac; - #endif -} sli_cryptoacc_transparent_mac_operation_t; - -typedef struct { - uint8_t nonce_length; ///< Nonce length - uint8_t nonce[16]; ///< Nonce buffer -} sli_cryptoacc_transparent_aead_preinit_t; - -typedef struct { - sli_aes_mode_t direction; ///< xCM mode - psa_algorithm_t alg; ///< Algorithm - uint8_t key[32]; ///< Key buffer - size_t key_len; ///< Key length - size_t ad_len; ///< Length of additional data - size_t processed_len; ///< Current encrypted/decrypted message length - #if defined(PSA_WANT_ALG_CCM) - size_t total_length; ///< Total message length (only used for ccm) - #endif - uint8_t final_data[16]; ///< Input data saved for finish operation - uint8_t final_data_length; ///< Length of data saved - union { - sli_cryptoacc_transparent_aead_preinit_t preinit; ///< Values needed for initiating a multipart process - uint8_t xcm_ctx[BLK_CIPHER_CTX_xCM_SIZE]; ///< xCM state context - uint8_t tag_buf[16]; ///< Tag (only need for CCM when total message length is zero) - } ctx; -} sli_cryptoacc_transparent_aead_operation_t; - -#ifdef __cplusplus -} -#endif - -#endif // CRYPTOACC_PRESENT - -/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ -/** \} (end addtogroup sl_psa_drivers) */ - -/// @endcond - -#endif // SLI_CRYPTOACC_TRANSPARENT_TYPES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver API Types for CRYPTOACC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SLI_CRYPTOACC_TRANSPARENT_TYPES_H +#define SLI_CRYPTOACC_TRANSPARENT_TYPES_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +/***************************************************************************//** + * \addtogroup sl_psa_drivers + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_psa_drivers_cryptoacc + * \{ + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sx_hash.h" +#include "sx_aes.h" +#include "sl_enum.h" +// Replace inclusion of crypto_driver_common.h with the new psa driver interface +// header file when it becomes available. +#include "psa/crypto_driver_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +SL_ENUM(sli_aes_mode_t) { + SLI_AES_ENC = 1, + SLI_AES_DEC = 2, +}; + +typedef struct { + sx_hash_fct_t hash_type; ///< Hash type + uint32_t total; ///< Number of bytes processed + uint8_t state[32]; ///< Intermediate digest state + uint8_t buffer[64]; ///< Data block being processed +} sli_cryptoacc_transparent_hash_operation_t; + +typedef struct { + sli_aes_mode_t direction; ///< Cipher direction (encrypt/decrypt) + psa_algorithm_t alg; ///< Algorithm (cipher and mode of operation) + uint8_t key[32]; ///< Key buffer + size_t key_len; ///< Length of key in bytes + uint8_t iv[16]; ///< IV buffer + size_t iv_len; ///< Length of IV in bytes + uint8_t streaming_block[16]; ///< Buffer for intermediate results + size_t processed_length; ///< Number of bytes processed +} sli_cryptoacc_transparent_cipher_operation_t; + +typedef union { + struct { + psa_algorithm_t alg; ///< MAC type + uint8_t key[32]; ///< key buffer + size_t key_len; ///< key length + uint8_t current_block[16]; ///< current and potentially last block + size_t current_block_len; ///< current number of bytes in current block + uint8_t cmac_ctx[BLK_CIPHER_CTX_SIZE]; ///< CMAC state context + } cipher_mac; + #if defined(PSA_WANT_ALG_HMAC) + struct { + psa_algorithm_t alg; ///< HMAC type + sli_cryptoacc_transparent_hash_operation_t hash_ctx; ///< Hash context for multipart HMAC + uint8_t opad[64]; ///< opad for use during finalisation + } hmac; + #endif +} sli_cryptoacc_transparent_mac_operation_t; + +typedef struct { + uint8_t nonce_length; ///< Nonce length + uint8_t nonce[16]; ///< Nonce buffer +} sli_cryptoacc_transparent_aead_preinit_t; + +typedef struct { + sli_aes_mode_t direction; ///< xCM mode + psa_algorithm_t alg; ///< Algorithm + uint8_t key[32]; ///< Key buffer + size_t key_len; ///< Key length + size_t ad_len; ///< Length of additional data + size_t processed_len; ///< Current encrypted/decrypted message length + #if defined(PSA_WANT_ALG_CCM) + size_t total_length; ///< Total message length (only used for ccm) + #endif + uint8_t final_data[16]; ///< Input data saved for finish operation + uint8_t final_data_length; ///< Length of data saved + union { + sli_cryptoacc_transparent_aead_preinit_t preinit; ///< Values needed for initiating a multipart process + uint8_t xcm_ctx[BLK_CIPHER_CTX_xCM_SIZE]; ///< xCM state context + uint8_t tag_buf[16]; ///< Tag (only need for CCM when total message length is zero) + } ctx; +} sli_cryptoacc_transparent_aead_operation_t; + +#ifdef __cplusplus +} +#endif + +#endif // CRYPTOACC_PRESENT + +/** \} (end addtogroup sl_psa_drivers_cryptoacc) */ +/** \} (end addtogroup sl_psa_drivers) */ + +/// @endcond + +#endif // SLI_CRYPTOACC_TRANSPARENT_TYPES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h index 75c73bf..6233375 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_common.h @@ -1,230 +1,230 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto common driver functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_PSA_DRIVER_COMMON_H -#define SLI_PSA_DRIVER_COMMON_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include "psa/crypto.h" - -#include - -// ----------------------------------------------------------------------------- -// Static inline functions - -/******************************************************************************* - * @brief - * Validate that a elliptic curve (in Weierstrass form) private key is valid. - * This fuction attempts to operate in constant time. - * - * @param[in] privkey - * A buffer containing the private key. - * - * @param padding_bytes - * A buffer containing the modulus (n) to compare the private key against. - * - * @return - * PSA_SUCCESS if the key is in [1, n-1], PSA_ERROR_INVALID_ARGUMENT otherwise. - ******************************************************************************/ -static inline psa_status_t sli_psa_validate_ecc_weierstrass_privkey( - const void *privkey, - const void *modulus, - size_t privkey_size) -{ - // Compare private key to maximum allowed value, n - 1, - // and also check that it is non-zero. - - // Initial values. - uint8_t non_zero_accumulator = 0; - int32_t memcmp_res = 0; - int32_t diff = 0; - - // Loop over every byte in the private key. We start from the end so that - // the final result we store reflects the first byte which differs between the - // two numbers (privkey and modulus). - for (size_t i = 0; i < privkey_size; ++i) { - // Partial non-zero check operation. - non_zero_accumulator |= ((uint8_t *)privkey)[privkey_size - 1 - i]; - - // Compute the difference between the current bytes being compared. - diff = ((uint8_t *)privkey)[privkey_size - 1 - i] - - ((uint8_t *)modulus)[privkey_size - 1 - i]; - - // This will only update memcmp_res if the difference is non-zero. - memcmp_res = (memcmp_res & - !diff) | diff; - } - - if ((non_zero_accumulator == 0) || (memcmp_res >= 0)) { - // We have either failed because the private key turned out to be empty, - // or because the result of the memcmp indicated that the privkey was not - // smaller than the modulus. - return PSA_ERROR_INVALID_ARGUMENT; - } else { - return PSA_SUCCESS; - } -} - -/***************************************************************************//** - * @brief - * Clear a memory location in a way that is guaranteed not be optimized away - * by the compiler. - * - * @param[in] v - * Pointer to memory location. - * - * @param[in] n - * Number of bytes to clear. - ******************************************************************************/ -static inline psa_status_t sli_psa_zeroize(void *v, size_t n) -{ - if (n == 0) { - return PSA_SUCCESS; - } - - volatile unsigned char *p = v; - while (n--) { - *p++ = 0; - } - return PSA_SUCCESS; -} - -/***************************************************************************//** - * @brief - * Perform a memcmp() in 'constant time'. - * - * @param[in] a - * Pointer to the first memory location. - * - * @param[in] a - * Pointer to the second memory location. - * - * @param[in] n - * Number of bytes to compare between the two memory locations. - * - * @return - * Zero if the buffer contents are equal, non-zero otherwise. - ******************************************************************************/ -static inline uint8_t sli_psa_safer_memcmp(const uint8_t *a, - const uint8_t *b, - size_t n) -{ - uint8_t diff = 0u; - - for (size_t i = 0; i < n; i++) { - diff |= a[i] ^ b[i]; - } - - return diff; -} - -// ----------------------------------------------------------------------------- -// Function declarations - -/******************************************************************************* - * @brief - * Validate the PKCS#7 padding contained in the final block of plaintext - * in certain block cipher modes of operation. Based on the get_pkcs_padding() - * implementation in Mbed TLS. - * - * @param[in] padded_data - * A buffer of (at least) size 16 containing the padded final block. - * - * @param padded_data_length - * The length of the paddad data (should be 16). Parameter is mainly kept used - * in order to make it harder for the compiler to optimize out some of the - * "time-constantness". - * - * @param[out] padding_bytes - * The amount of padding bytes that the data contains. - - * - * @return - * PSA_SUCCESS if the padding is valid, PSA_ERROR_INVALID_PADDING otherwise. - ******************************************************************************/ -psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, - size_t padded_data_length, - size_t *padding_bytes); - -/** - * \brief Initialize Galois field (2^128) multiplication table - * - * This function is used as part of a software-based GHASH (as defined in - * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c - * - * It takes the in the 'H' value for the GHASH operation (which is a block of - * zeroes encrypted using AES-ECB with the key to be used for GHASH/GCM), and - * converts it into a multiplication table for later use by the multiplication - * function. - * - * \param[in] Ek 'H' value for which to create the multiplication tables - * \param[out] HL Lower multiplication table for 'H' - * \param[out] HH Upper multiplication table for 'H' - */ -void sli_psa_software_ghash_setup(const uint8_t Ek[16], - uint64_t HL[16], - uint64_t HH[16]); - -/** - * \brief Galois field (2^128) multiplication operation - * - * This function is used as part of a software-based GHASH (as defined in - * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c - * - * This function takes in a 128-bit scalar and multiplies it with H (Galois - * field multiplication as defined in AES-GCM). H is not provided to this - * function directly. Instead, multiplication tables for the specific H need to - * be calculated first by \ref sli_psa_software_ghash_setup, and passed to this - * function. - * - * \param[in] HL Lower multiplication table for 'H' - * \param[in] HH Upper multiplication table for 'H' - * \param[out] output Output buffer for the multiplication result - * \param[in] input Input buffer for the scalar to multiply - */ -void sli_psa_software_ghash_multiply(const uint64_t HL[16], - const uint64_t HH[16], - uint8_t output[16], - const uint8_t input[16]); - -#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) \ - && !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - -// Declare the TRNG function prototype if it's not already declared by PSA -psa_status_t mbedtls_psa_external_get_random(void *context, - uint8_t *output, - size_t output_size, - size_t *output_length); - -#endif // MBEDTLS_ENTROPY_HARDWARE_ALT && MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG - -/// @endcond - -#endif // SLI_PSA_DRIVER_COMMON_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto common driver functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_DRIVER_COMMON_H +#define SLI_PSA_DRIVER_COMMON_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "psa/crypto.h" + +#include + +// ----------------------------------------------------------------------------- +// Static inline functions + +/******************************************************************************* + * @brief + * Validate that a elliptic curve (in Weierstrass form) private key is valid. + * This fuction attempts to operate in constant time. + * + * @param[in] privkey + * A buffer containing the private key. + * + * @param padding_bytes + * A buffer containing the modulus (n) to compare the private key against. + * + * @return + * PSA_SUCCESS if the key is in [1, n-1], PSA_ERROR_INVALID_ARGUMENT otherwise. + ******************************************************************************/ +static inline psa_status_t sli_psa_validate_ecc_weierstrass_privkey( + const void *privkey, + const void *modulus, + size_t privkey_size) +{ + // Compare private key to maximum allowed value, n - 1, + // and also check that it is non-zero. + + // Initial values. + uint8_t non_zero_accumulator = 0; + int32_t memcmp_res = 0; + int32_t diff = 0; + + // Loop over every byte in the private key. We start from the end so that + // the final result we store reflects the first byte which differs between the + // two numbers (privkey and modulus). + for (size_t i = 0; i < privkey_size; ++i) { + // Partial non-zero check operation. + non_zero_accumulator |= ((uint8_t *)privkey)[privkey_size - 1 - i]; + + // Compute the difference between the current bytes being compared. + diff = ((uint8_t *)privkey)[privkey_size - 1 - i] + - ((uint8_t *)modulus)[privkey_size - 1 - i]; + + // This will only update memcmp_res if the difference is non-zero. + memcmp_res = (memcmp_res & - !diff) | diff; + } + + if ((non_zero_accumulator == 0) || (memcmp_res >= 0)) { + // We have either failed because the private key turned out to be empty, + // or because the result of the memcmp indicated that the privkey was not + // smaller than the modulus. + return PSA_ERROR_INVALID_ARGUMENT; + } else { + return PSA_SUCCESS; + } +} + +/***************************************************************************//** + * @brief + * Clear a memory location in a way that is guaranteed not be optimized away + * by the compiler. + * + * @param[in] v + * Pointer to memory location. + * + * @param[in] n + * Number of bytes to clear. + ******************************************************************************/ +static inline psa_status_t sli_psa_zeroize(void *v, size_t n) +{ + if (n == 0) { + return PSA_SUCCESS; + } + + volatile unsigned char *p = v; + while (n--) { + *p++ = 0; + } + return PSA_SUCCESS; +} + +/***************************************************************************//** + * @brief + * Perform a memcmp() in 'constant time'. + * + * @param[in] a + * Pointer to the first memory location. + * + * @param[in] a + * Pointer to the second memory location. + * + * @param[in] n + * Number of bytes to compare between the two memory locations. + * + * @return + * Zero if the buffer contents are equal, non-zero otherwise. + ******************************************************************************/ +static inline uint8_t sli_psa_safer_memcmp(const uint8_t *a, + const uint8_t *b, + size_t n) +{ + uint8_t diff = 0u; + + for (size_t i = 0; i < n; i++) { + diff |= a[i] ^ b[i]; + } + + return diff; +} + +// ----------------------------------------------------------------------------- +// Function declarations + +/******************************************************************************* + * @brief + * Validate the PKCS#7 padding contained in the final block of plaintext + * in certain block cipher modes of operation. Based on the get_pkcs_padding() + * implementation in Mbed TLS. + * + * @param[in] padded_data + * A buffer of (at least) size 16 containing the padded final block. + * + * @param padded_data_length + * The length of the paddad data (should be 16). Parameter is mainly kept used + * in order to make it harder for the compiler to optimize out some of the + * "time-constantness". + * + * @param[out] padding_bytes + * The amount of padding bytes that the data contains. + + * + * @return + * PSA_SUCCESS if the padding is valid, PSA_ERROR_INVALID_PADDING otherwise. + ******************************************************************************/ +psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, + size_t padded_data_length, + size_t *padding_bytes); + +/** + * \brief Initialize Galois field (2^128) multiplication table + * + * This function is used as part of a software-based GHASH (as defined in + * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c + * + * It takes the in the 'H' value for the GHASH operation (which is a block of + * zeroes encrypted using AES-ECB with the key to be used for GHASH/GCM), and + * converts it into a multiplication table for later use by the multiplication + * function. + * + * \param[in] Ek 'H' value for which to create the multiplication tables + * \param[out] HL Lower multiplication table for 'H' + * \param[out] HH Upper multiplication table for 'H' + */ +void sli_psa_software_ghash_setup(const uint8_t Ek[16], + uint64_t HL[16], + uint64_t HH[16]); + +/** + * \brief Galois field (2^128) multiplication operation + * + * This function is used as part of a software-based GHASH (as defined in + * AES-GCM) algorithm, and originates from the mbed TLS implementation in gcm.c + * + * This function takes in a 128-bit scalar and multiplies it with H (Galois + * field multiplication as defined in AES-GCM). H is not provided to this + * function directly. Instead, multiplication tables for the specific H need to + * be calculated first by \ref sli_psa_software_ghash_setup, and passed to this + * function. + * + * \param[in] HL Lower multiplication table for 'H' + * \param[in] HH Upper multiplication table for 'H' + * \param[out] output Output buffer for the multiplication result + * \param[in] input Input buffer for the scalar to multiply + */ +void sli_psa_software_ghash_multiply(const uint64_t HL[16], + const uint64_t HH[16], + uint8_t output[16], + const uint8_t input[16]); + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) \ + && !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + +// Declare the TRNG function prototype if it's not already declared by PSA +psa_status_t mbedtls_psa_external_get_random(void *context, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#endif // MBEDTLS_ENTROPY_HARDWARE_ALT && MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +/// @endcond + +#endif // SLI_PSA_DRIVER_COMMON_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h index 32408c0..e2a8b8c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_psa_driver_features.h @@ -1,393 +1,393 @@ -/***************************************************************************//** - * @file - * @brief PSA Crypto driver feature enablement. - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_PSA_DRIVER_FEATURES_H -#define SLI_PSA_DRIVER_FEATURES_H - -#include "mbedtls/build_info.h" - -// ----------------------------------------------------------------------------- -// Feature inclusion (available AND requested) - -// ------------------------------------- -// Keys - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS - #define SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS -#endif - -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SEPUF_PRESENT) - #define SLI_PSA_DRIVER_FEATURE_PUF_KEY -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) \ - && (defined(SLI_MBEDTLS_DEVICE_HSE) || defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY)) - #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS - #define SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS -#endif - -// ------------------------------------- -// TRNG - -#if defined(SLI_MBEDTLS_DEVICE_HSE) \ - || defined(SLI_MBEDTLS_DEVICE_VSE) \ - || defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG) \ - || defined(SLI_MBEDTLS_DEVICE_SI91X) - #define SLI_PSA_DRIVER_FEATURE_TRNG -#endif - -#if defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA) - #define SLI_PSA_DRIVER_FEATURE_TRNG_ERRATA_HANDLING -#endif - -// ------------------------------------- -// Attestation - -#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_ATTESTATION -#endif - -// ------------------------------------- -// AEAD - -#if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) - #define SLI_PSA_DRIVER_FEATURE_AEAD - #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_CCM -#endif - -#if defined(PSA_WANT_ALG_GCM) && defined(MBEDTLS_PSA_ACCEL_ALG_GCM) - #define SLI_PSA_DRIVER_FEATURE_AEAD - #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_GCM - -// TODO: add public config option. - #if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) -// Can use software implementation in order to compute IVs. - #define SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION - #endif -#endif - -#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) && defined(MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305) - #define SLI_PSA_DRIVER_FEATURE_AEAD - #define SLI_PSA_DRIVER_FEATURE_CHACHAPOLY -#endif - -// ------------------------------------- -// Cipher - -#if defined(PSA_WANT_KEY_TYPE_AES) && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_AES) - - #define SLI_PSA_DRIVER_FEATURE_AES - - #if defined(PSA_WANT_ALG_ECB_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_ECB - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_CTR) && defined(MBEDTLS_PSA_ACCEL_ALG_CTR) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_CTR - #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_CFB) && defined(MBEDTLS_PSA_ACCEL_ALG_CFB) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_CFB - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_OFB) && defined(MBEDTLS_PSA_ACCEL_ALG_OFB) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_OFB - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG - #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_CBC_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING - #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - - #if defined(PSA_WANT_ALG_CBC_PKCS7) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER - #define SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7 - #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART - #endif - -#endif - -#if defined(PSA_WANT_KEY_TYPE_CHACHA20) && defined(PSA_WANT_ALG_STREAM_CIPHER) \ - && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20) - #define SLI_PSA_DRIVER_FEATURE_CIPHER - #define SLI_PSA_DRIVER_FEATURE_STREAM_CIPHER - #define SLI_PSA_DRIVER_FEATURE_CHACHA20 - #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART -#endif - -// ------------------------------------- -// Key derivation - -#if defined(PSA_WANT_ALG_HKDF) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_KDF - #define SLI_PSA_DRIVER_FEATURE_HKDF -#endif - -#if defined(PSA_WANT_ALG_PBKDF2_HMAC) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_KDF - #define SLI_PSA_DRIVER_FEATURE_PBKDF2 - #define SLI_PSA_DRIVER_FEATURE_PBKDF2_HMAC -#endif - -#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ - && defined(SLI_MBEDTLS_DEVICE_HSE_V2) - #define SLI_PSA_DRIVER_FEATURE_KDF - #define SLI_PSA_DRIVER_FEATURE_PBKDF2 - #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC -#endif - -#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) - #define SLI_PSA_DRIVER_FEATURE_KDF - #define SLI_PSA_DRIVER_FEATURE_PBKDF2 - #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC -#endif - -// ------------------------------------- -// Hash - -#if defined(PSA_WANT_ALG_SHA_1) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) - #define SLI_PSA_DRIVER_FEATURE_HASH - #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_SHA1 - #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 -#endif - -#if defined(PSA_WANT_ALG_SHA_224) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) - #define SLI_PSA_DRIVER_FEATURE_HASH - #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_SHA224 - #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 -#endif - -#if defined(PSA_WANT_ALG_SHA_256) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) - #define SLI_PSA_DRIVER_FEATURE_HASH - #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_SHA256 - #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 -#endif - -#if defined(PSA_WANT_ALG_SHA_384) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) - #define SLI_PSA_DRIVER_FEATURE_HASH - #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_SHA384 - #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 -#endif - -#if defined(PSA_WANT_ALG_SHA_512) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) - #define SLI_PSA_DRIVER_FEATURE_HASH - #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_SHA512 - #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 -#endif - -// ------------------------------------- -// MAC - -#if defined(PSA_WANT_ALG_HMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) - #define SLI_PSA_DRIVER_FEATURE_MAC - #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_HMAC -#endif - -#if defined(PSA_WANT_ALG_CMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) - #define SLI_PSA_DRIVER_FEATURE_MAC - #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_CMAC -#endif - -#if defined(PSA_WANT_ALG_CBC_MAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) - #define SLI_PSA_DRIVER_FEATURE_MAC - #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART - #define SLI_PSA_DRIVER_FEATURE_CBC_MAC -#endif - -// ------------------------------------- -// Elliptic curve cryptography - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_R1_192) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPR1 - #define SLI_PSA_DRIVER_FEATURE_P192R1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_R1_224) \ - && !defined(SLI_MBEDTLS_DEVICE_HSE_V1) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPR1 - #define SLI_PSA_DRIVER_FEATURE_P224R1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_R1_256) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPR1 - #define SLI_PSA_DRIVER_FEATURE_P256R1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_R1_384) \ - && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPR1 - #define SLI_PSA_DRIVER_FEATURE_P384R1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_R1_521) \ - && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPR1 - #define SLI_PSA_DRIVER_FEATURE_P521R1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_SECP_K1_256) \ - && defined(SLI_MBEDTLS_DEVICE_VSE) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_SECPK1 - #define SLI_PSA_DRIVER_FEATURE_P256K1 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_MONTGOMERY_255) \ - && defined(SLI_MBEDTLS_DEVICE_HSE) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY - #define SLI_PSA_DRIVER_FEATURE_CURVE25519 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_MONTGOMERY_448) \ - && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY - #define SLI_PSA_DRIVER_FEATURE_CURVE448 -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ - || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ - || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ - && defined(PSA_WANT_ECC_TWISTED_EDWARDS_255) \ - && defined(SLI_MBEDTLS_DEVICE_HSE) - #define SLI_PSA_DRIVER_FEATURE_ECC - #define SLI_PSA_DRIVER_FEATURE_EDWARDS - #define SLI_PSA_DRIVER_FEATURE_EDWARDS25519 -#endif - -// ------------------------------------- -// Key agreement - -#if defined(PSA_WANT_ALG_ECDH) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) \ - && defined(SLI_PSA_DRIVER_FEATURE_ECC) - #define SLI_PSA_DRIVER_FEATURE_KEY_AGREEMENT - #define SLI_PSA_DRIVER_FEATURE_ECDH -#endif - -// ------------------------------------- -// Signature - -#if defined(PSA_WANT_ALG_ECDSA) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) \ - && (defined(SLI_PSA_DRIVER_FEATURE_SECPR1) \ - || defined(SLI_PSA_DRIVER_FEATURE_SECPK1)) - #define SLI_PSA_DRIVER_FEATURE_SIGNATURE - #define SLI_PSA_DRIVER_FEATURE_ECDSA -#endif - -#if defined(PSA_WANT_ALG_EDDSA) && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) - #define SLI_PSA_DRIVER_FEATURE_SIGNATURE - #define SLI_PSA_DRIVER_FEATURE_EDDSA -#endif - -#endif // SLI_PSA_DRIVER_FEATURES_H +/***************************************************************************//** + * @file + * @brief PSA Crypto driver feature enablement. + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_PSA_DRIVER_FEATURES_H +#define SLI_PSA_DRIVER_FEATURES_H + +#include "mbedtls/build_info.h" + +// ----------------------------------------------------------------------------- +// Feature inclusion (available AND requested) + +// ------------------------------------- +// Keys + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + #define SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS +#endif + +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SEPUF_PRESENT) + #define SLI_PSA_DRIVER_FEATURE_PUF_KEY +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) \ + && (defined(SLI_MBEDTLS_DEVICE_HSE) || defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY)) + #define SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + #define SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS +#endif + +// ------------------------------------- +// TRNG + +#if defined(SLI_MBEDTLS_DEVICE_HSE) \ + || defined(SLI_MBEDTLS_DEVICE_VSE) \ + || defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG) \ + || defined(SLI_MBEDTLS_DEVICE_SI91X) + #define SLI_PSA_DRIVER_FEATURE_TRNG +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S1_WITH_TRNG_ERRATA) + #define SLI_PSA_DRIVER_FEATURE_TRNG_ERRATA_HANDLING +#endif + +// ------------------------------------- +// Attestation + +#if defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_ATTESTATION +#endif + +// ------------------------------------- +// AEAD + +#if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CCM +#endif + +#if defined(PSA_WANT_ALG_GCM) && defined(MBEDTLS_PSA_ACCEL_ALG_GCM) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_AEAD_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_GCM + +// TODO: add public config option. + #if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) +// Can use software implementation in order to compute IVs. + #define SLI_PSA_DRIVER_FEATURE_GCM_IV_CALCULATION + #endif +#endif + +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) && defined(MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305) + #define SLI_PSA_DRIVER_FEATURE_AEAD + #define SLI_PSA_DRIVER_FEATURE_CHACHAPOLY +#endif + +// ------------------------------------- +// Cipher + +#if defined(PSA_WANT_KEY_TYPE_AES) && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_AES) + + #define SLI_PSA_DRIVER_FEATURE_AES + + #if defined(PSA_WANT_ALG_ECB_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_ECB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CTR) && defined(MBEDTLS_PSA_ACCEL_ALG_CTR) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CTR + #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CFB) && defined(MBEDTLS_PSA_ACCEL_ALG_CFB) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CFB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_OFB) && defined(MBEDTLS_PSA_ACCEL_ALG_OFB) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_OFB + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CCM) && defined(MBEDTLS_PSA_ACCEL_ALG_CCM) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CCM_STAR_NO_TAG + #define SLI_PSA_DRIVER_FEATURE_AES_CTR_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CBC_NO_PADDING) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_NO_PADDING + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + + #if defined(PSA_WANT_ALG_CBC_PKCS7) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_BLOCK_CIPHER + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_PKCS7 + #define SLI_PSA_DRIVER_FEATURE_AES_CBC_VARIANT + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART + #endif + +#endif + +#if defined(PSA_WANT_KEY_TYPE_CHACHA20) && defined(PSA_WANT_ALG_STREAM_CIPHER) \ + && defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20) + #define SLI_PSA_DRIVER_FEATURE_CIPHER + #define SLI_PSA_DRIVER_FEATURE_STREAM_CIPHER + #define SLI_PSA_DRIVER_FEATURE_CHACHA20 + #define SLI_PSA_DRIVER_FEATURE_CIPHER_MULTIPART +#endif + +// ------------------------------------- +// Key derivation + +#if defined(PSA_WANT_ALG_HKDF) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_HKDF +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_HMAC) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_HMAC +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) \ + && defined(SLI_MBEDTLS_DEVICE_HSE_V2) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) && defined(SLI_PSA_DRIVER_FEATURE_PUF_KEY) + #define SLI_PSA_DRIVER_FEATURE_KDF + #define SLI_PSA_DRIVER_FEATURE_PBKDF2 + #define SLI_PSA_DRIVER_FEATURE_PBKDF2_CMAC +#endif + +// ------------------------------------- +// Hash + +#if defined(PSA_WANT_ALG_SHA_1) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA1 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_224) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA224 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_256) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA256 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_32 +#endif + +#if defined(PSA_WANT_ALG_SHA_384) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA384 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 +#endif + +#if defined(PSA_WANT_ALG_SHA_512) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) + #define SLI_PSA_DRIVER_FEATURE_HASH + #define SLI_PSA_DRIVER_FEATURE_HASH_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_SHA512 + #define SLI_PSA_DRIVER_FEATURE_HASH_STATE_64 +#endif + +// ------------------------------------- +// MAC + +#if defined(PSA_WANT_ALG_HMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_HMAC +#endif + +#if defined(PSA_WANT_ALG_CMAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CMAC +#endif + +#if defined(PSA_WANT_ALG_CBC_MAC) && defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) + #define SLI_PSA_DRIVER_FEATURE_MAC + #define SLI_PSA_DRIVER_FEATURE_MAC_MULTIPART + #define SLI_PSA_DRIVER_FEATURE_CBC_MAC +#endif + +// ------------------------------------- +// Elliptic curve cryptography + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_192) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P192R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_224) \ + && !defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P224R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_256) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P256R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_384) \ + && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P384R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_R1_521) \ + && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPR1 + #define SLI_PSA_DRIVER_FEATURE_P521R1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_SECP_K1_256) \ + && defined(SLI_MBEDTLS_DEVICE_VSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_SECPK1 + #define SLI_PSA_DRIVER_FEATURE_P256K1 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_MONTGOMERY_255) \ + && defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY + #define SLI_PSA_DRIVER_FEATURE_CURVE25519 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_MONTGOMERY_448) \ + && defined(SLI_MBEDTLS_DEVICE_HSE_VAULT_HIGH) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_MONTGOMERY + #define SLI_PSA_DRIVER_FEATURE_CURVE448 +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) \ + || defined (PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) \ + || defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) \ + && defined(PSA_WANT_ECC_TWISTED_EDWARDS_255) \ + && defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_PSA_DRIVER_FEATURE_ECC + #define SLI_PSA_DRIVER_FEATURE_EDWARDS + #define SLI_PSA_DRIVER_FEATURE_EDWARDS25519 +#endif + +// ------------------------------------- +// Key agreement + +#if defined(PSA_WANT_ALG_ECDH) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) \ + && defined(SLI_PSA_DRIVER_FEATURE_ECC) + #define SLI_PSA_DRIVER_FEATURE_KEY_AGREEMENT + #define SLI_PSA_DRIVER_FEATURE_ECDH +#endif + +// ------------------------------------- +// Signature + +#if defined(PSA_WANT_ALG_ECDSA) && defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) \ + && (defined(SLI_PSA_DRIVER_FEATURE_SECPR1) \ + || defined(SLI_PSA_DRIVER_FEATURE_SECPK1)) + #define SLI_PSA_DRIVER_FEATURE_SIGNATURE + #define SLI_PSA_DRIVER_FEATURE_ECDSA +#endif + +#if defined(PSA_WANT_ALG_EDDSA) && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS) + #define SLI_PSA_DRIVER_FEATURE_SIGNATURE + #define SLI_PSA_DRIVER_FEATURE_EDDSA +#endif + +#endif // SLI_PSA_DRIVER_FEATURES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h index 3552551..eda0f71 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/inc/sli_se_version_dependencies.h @@ -1,141 +1,141 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_SE_VERSION_DEPENDENCIES_H -#define SLI_SE_VERSION_DEPENDENCIES_H - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #include "psa/crypto.h" - #include "sl_se_manager_types.h" -#endif - -// ----------------------------------------------------------------------------- -// Version Constants - -// HSE specific constants -#if defined(SLI_MBEDTLS_DEVICE_HSE) -// The oldest firmware revision with support for checking the validity -// of public ECC keys. Also see SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 and -// SL_SE_ASSUME_FW_AT_LEAST_1_2_2. - #if !defined(SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) - #define SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION (0x00010202U) - #endif - -// The SE version that first introduced a regression related to Ed25519. See -// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. - #if !defined(SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) - #define SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519 (0x00010202U) - #endif - -// The final SE version containing a bug causing Ed25519 to be broken. See -// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. - #if !defined(SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519) - #define SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519 (0x00010208U) - #endif -#endif // SLI_MBEDTLS_DEVICE_HSE - -// Common HSE/VSE constants - -// The first SE version that supports TrustZone Storage Root Key (SRK) -#if !defined(SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) - #if defined(SLI_MBEDTLS_DEVICE_SE_V2) - #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x00020200) - #else - #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x0001020c) - #endif -#endif - -// ----------------------------------------------------------------------------- -// Preprocessor Guard Helper Defines - -// ------------------------------- -// ECDH - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #if !SL_SE_ASSUME_FW_AT_LEAST_1_2_2 && defined(SLI_MBEDTLS_DEVICE_HSE_V1) - #define SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN - #endif -#endif // SLI_MBEDTLS_DEVICE_HSE - -// ------------------------------- -// EdDSA - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #if !SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA \ - && defined(SLI_MBEDTLS_DEVICE_HSE_V1) - #define SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN - #endif - - #if defined(SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN) \ - && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) - #define SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED - #endif -#endif // SLI_MBEDTLS_DEVICE_HSE - -// ----------------------------------------------------------------------------- -// Version macros - -// HSE specific macros -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #define SLI_SE_VERSION_PUBKEY_VALIDATION_REQUIRED(se_version) \ - (se_version < SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) - - #define SLI_SE_VERSION_ED25519_BROKEN(se_version) \ - (!((se_version < SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) \ - || (se_version > SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519))) -#endif // SLI_MBEDTLS_DEVICE_HSE - -// Common HSE/VSE macros -#define SLI_VERSION_REMOVE_DIE_ID(version) ((version) & 0x00FFFFFFU) - -#define SLI_SE_VERSION_SUPPORTS_SRK(se_version) \ - (SLI_VERSION_REMOVE_DIE_ID(se_version) >= SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) - -// ----------------------------------------------------------------------------- -// Function declarations - -#ifdef __cplusplus -extern "C" { -#endif - -psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, - sl_se_command_context_t* cmd_ctx); - -#ifdef __cplusplus -} -#endif - -/// @endcond - -#endif // SLI_SE_VERSION_DEPENDENCIES_H +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SE_VERSION_DEPENDENCIES_H +#define SLI_SE_VERSION_DEPENDENCIES_H + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "psa/crypto.h" + #include "sl_se_manager_types.h" +#endif + +// ----------------------------------------------------------------------------- +// Version Constants + +// HSE specific constants +#if defined(SLI_MBEDTLS_DEVICE_HSE) +// The oldest firmware revision with support for checking the validity +// of public ECC keys. Also see SL_SE_SUPPORT_FW_PRIOR_TO_1_2_2 and +// SL_SE_ASSUME_FW_AT_LEAST_1_2_2. + #if !defined(SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) + #define SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION (0x00010202U) + #endif + +// The SE version that first introduced a regression related to Ed25519. See +// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. + #if !defined(SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) + #define SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519 (0x00010202U) + #endif + +// The final SE version containing a bug causing Ed25519 to be broken. See +// SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA. + #if !defined(SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519) + #define SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519 (0x00010208U) + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// Common HSE/VSE constants + +// The first SE version that supports TrustZone Storage Root Key (SRK) +#if !defined(SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) + #if defined(SLI_MBEDTLS_DEVICE_SE_V2) + #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x00020200) + #else + #define SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT (0x0001020c) + #endif +#endif + +// ----------------------------------------------------------------------------- +// Preprocessor Guard Helper Defines + +// ------------------------------- +// ECDH + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #if !SL_SE_ASSUME_FW_AT_LEAST_1_2_2 && defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_SE_VERSION_ECDH_PUBKEY_VALIDATION_UNCERTAIN + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ------------------------------- +// EdDSA + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #if !SL_SE_ASSUME_FW_UNAFFECTED_BY_ED25519_ERRATA \ + && defined(SLI_MBEDTLS_DEVICE_HSE_V1) + #define SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN + #endif + + #if defined(SLI_SE_VERSION_ED25519_ERRATA_UNCERTAIN) \ + && defined(SLI_PSA_DRIVER_FEATURE_EDWARDS25519) + #define SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + #endif +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ----------------------------------------------------------------------------- +// Version macros + +// HSE specific macros +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #define SLI_SE_VERSION_PUBKEY_VALIDATION_REQUIRED(se_version) \ + (se_version < SLI_SE_OLDEST_VERSION_WITH_PUBLIC_KEY_VALIDATION) + + #define SLI_SE_VERSION_ED25519_BROKEN(se_version) \ + (!((se_version < SLI_SE_FIRST_VERSION_WITH_BROKEN_ED25519) \ + || (se_version > SLI_SE_LAST_VERSION_WITH_BROKEN_ED25519))) +#endif // SLI_MBEDTLS_DEVICE_HSE + +// Common HSE/VSE macros +#define SLI_VERSION_REMOVE_DIE_ID(version) ((version) & 0x00FFFFFFU) + +#define SLI_SE_VERSION_SUPPORTS_SRK(se_version) \ + (SLI_VERSION_REMOVE_DIE_ID(se_version) >= SLI_SE_FIRST_VERSION_WITH_SRK_SUPPORT) + +// ----------------------------------------------------------------------------- +// Function declarations + +#ifdef __cplusplus +extern "C" { +#endif + +psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, + sl_se_command_context_t* cmd_ctx); + +#ifdef __cplusplus +} +#endif + +/// @endcond + +#endif // SLI_SE_VERSION_DEPENDENCIES_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c index 07ae44e..d70d6af 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs CRYPTOACC device management interface. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "psa/crypto.h" - -#include "sli_se_manager_internal.h" - -#include "sli_cryptoacc_driver_trng.h" - -#include "sx_aes.h" -#include "ba414ep_config.h" - -//------------------------------------------------------------------------------ -// RTOS Synchronization and Clocking Functions - -// Get ownership of an available CRYPTOACC device. -psa_status_t cryptoacc_management_acquire(void) -{ - #if defined(MBEDTLS_THREADING_C) - if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Take SE lock - wait/block if taken by another thread. - sl_status_t ret = sli_se_lock_acquire(); - if (ret != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - #endif - - CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; - CMU->CRYPTOACCCLKCTRL_SET = (CMU_CRYPTOACCCLKCTRL_PKEN - | CMU_CRYPTOACCCLKCTRL_AESEN); - - return PSA_SUCCESS; -} - -// Release ownership of a reserved CRYPTOACC device. -psa_status_t cryptoacc_management_release(void) -{ - CMU->CLKEN1_CLR = CMU_CLKEN1_CRYPTOACC; - CMU->CRYPTOACCCLKCTRL_CLR = (CMU_CRYPTOACCCLKCTRL_PKEN - | CMU_CRYPTOACCCLKCTRL_AESEN); - - #if defined(MBEDTLS_THREADING_C) - if (sli_se_lock_release() != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - #endif - - return PSA_SUCCESS; -} - -//------------------------------------------------------------------------------ -// Countermeasure Initialization Functions - -#if defined(SLI_MBEDTLS_DEVICE_VSE_V2) - -psa_status_t cryptoacc_initialize_countermeasures(void) -{ - // Set to true when CM has been initialized - static bool cm_inited = false; - - // Note on the error handling: we want to try and set up the countermeasures - // even if some of the steps fail. Hence, the first error code is stored and - // returned in the end if something goes wrong. - psa_status_t final_status = PSA_SUCCESS; - if (!cm_inited) { - // Set up the PK engine with a TRNG wrapper function to use for randomness - // generation. This will be used for future ECC operations as well, not only - // during the lifetime of this function. - ba414ep_set_rng(sli_cryptoacc_trng_wrapper); - - // Seed the AES engine with a random mask. The highest bit must be set due - // to hardware requirements. - uint32_t mask = 0; - psa_status_t temp_status = sli_cryptoacc_trng_get_random((uint8_t *)&mask, - sizeof(mask)); - if (temp_status != PSA_SUCCESS) { - final_status = temp_status; - } - mask |= (1U << 31); - - temp_status = cryptoacc_management_acquire(); - if (temp_status != PSA_SUCCESS) { - final_status = temp_status; - } - sx_aes_load_mask(mask); - temp_status = cryptoacc_management_release(); - if ((temp_status != PSA_SUCCESS) && (final_status == PSA_SUCCESS)) { - final_status = temp_status; - } - - // Only track that init was successful if no error codes popped up. - if (final_status == PSA_SUCCESS) { - cm_inited = true; - } - } - - return final_status; -} - -#endif // SLI_MBEDTLS_DEVICE_VSE_V2 - -#endif // SLI_MBEDTLS_DEVICE_VSE +/***************************************************************************//** + * @file + * @brief Silicon Labs CRYPTOACC device management interface. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "sli_se_manager_internal.h" + +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_aes.h" +#include "ba414ep_config.h" + +//------------------------------------------------------------------------------ +// RTOS Synchronization and Clocking Functions + +// Get ownership of an available CRYPTOACC device. +psa_status_t cryptoacc_management_acquire(void) +{ + #if defined(MBEDTLS_THREADING_C) + if ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0U) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Take SE lock - wait/block if taken by another thread. + sl_status_t ret = sli_se_lock_acquire(); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + #endif + + CMU->CLKEN1_SET = CMU_CLKEN1_CRYPTOACC; + CMU->CRYPTOACCCLKCTRL_SET = (CMU_CRYPTOACCCLKCTRL_PKEN + | CMU_CRYPTOACCCLKCTRL_AESEN); + + return PSA_SUCCESS; +} + +// Release ownership of a reserved CRYPTOACC device. +psa_status_t cryptoacc_management_release(void) +{ + CMU->CLKEN1_CLR = CMU_CLKEN1_CRYPTOACC; + CMU->CRYPTOACCCLKCTRL_CLR = (CMU_CRYPTOACCCLKCTRL_PKEN + | CMU_CRYPTOACCCLKCTRL_AESEN); + + #if defined(MBEDTLS_THREADING_C) + if (sli_se_lock_release() != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + #endif + + return PSA_SUCCESS; +} + +//------------------------------------------------------------------------------ +// Countermeasure Initialization Functions + +#if defined(SLI_MBEDTLS_DEVICE_VSE_V2) + +psa_status_t cryptoacc_initialize_countermeasures(void) +{ + // Set to true when CM has been initialized + static bool cm_inited = false; + + // Note on the error handling: we want to try and set up the countermeasures + // even if some of the steps fail. Hence, the first error code is stored and + // returned in the end if something goes wrong. + psa_status_t final_status = PSA_SUCCESS; + if (!cm_inited) { + // Set up the PK engine with a TRNG wrapper function to use for randomness + // generation. This will be used for future ECC operations as well, not only + // during the lifetime of this function. + ba414ep_set_rng(sli_cryptoacc_trng_wrapper); + + // Seed the AES engine with a random mask. The highest bit must be set due + // to hardware requirements. + uint32_t mask = 0; + psa_status_t temp_status = sli_cryptoacc_trng_get_random((uint8_t *)&mask, + sizeof(mask)); + if (temp_status != PSA_SUCCESS) { + final_status = temp_status; + } + mask |= (1U << 31); + + temp_status = cryptoacc_management_acquire(); + if (temp_status != PSA_SUCCESS) { + final_status = temp_status; + } + sx_aes_load_mask(mask); + temp_status = cryptoacc_management_release(); + if ((temp_status != PSA_SUCCESS) && (final_status == PSA_SUCCESS)) { + final_status = temp_status; + } + + // Only track that init was successful if no error codes popped up. + if (final_status == PSA_SUCCESS) { + cm_inited = true; + } + } + + return final_status; +} + +#endif // SLI_MBEDTLS_DEVICE_VSE_V2 + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c index 4dc0df9..682ecb6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c @@ -1,3302 +1,3302 @@ -/***************************************************************************//** - * @file - * @brief PSA ITS implementation based on Silicon Labs NVM3 - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -// The psa_driver_wrappers.h file that we're including here assumes that it has -// access to private struct members. Define this here in order to avoid -// compilation errors. -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - -// ------------------------------------- -// Includes - -#include - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && !defined(MBEDTLS_PSA_ITS_FILE_C) - -#include "psa/internal_trusted_storage.h" -#include "psa/sli_internal_trusted_storage.h" -#include "nvm3_default.h" -#include "mbedtls/platform.h" -#include -#include - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - #include - #include "psa/storage_common.h" -#endif // TFM_CONFIG_SL_SECURE_LIBRARY - -#if defined(SLI_PSA_ITS_ENCRYPTED) - #include "psa_crypto_core.h" - #include "psa_crypto_driver_wrappers.h" - #if defined(SEMAILBOX_PRESENT) - #include "psa/crypto_extra.h" - #include "sl_psa_values.h" - #include "sli_se_opaque_functions.h" - #endif // defined(SEMAILBOX_PRESENT) -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Threading support - -#if defined(MBEDTLS_THREADING_C) -#include "cmsis_os2.h" -#include "mbedtls/threading.h" - -// Mutex for protecting access to the ITS instance -static mbedtls_threading_mutex_t its_mutex; -static volatile bool its_mutex_inited = false; - -/** - * \brief Lock all task switches - * - * \return Previous lock state - * - */ -static inline int32_t lock_task_switches(void) -{ - int32_t kernel_lock_state = 0; - osKernelState_t kernel_state = osKernelGetState(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - kernel_lock_state = osKernelLock(); - } - return kernel_lock_state; -} - -/** - * \brief Restores the previous lock state - */ -static inline void restore_lock_state(int32_t kernel_lock_state) -{ - osKernelState_t kernel_state = osKernelGetState(); - if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { - if (osKernelRestoreLock(kernel_lock_state) < 0) { - EFM_ASSERT(false); - } - } -} - -#endif // defined(MBEDTLS_THREADING_C) - -/** - * \brief Pend on the ITS mutex - */ -void sli_its_acquire_mutex(void) -{ -#if defined(MBEDTLS_THREADING_C) - if (!its_mutex_inited) { - int32_t kernel_lock_state = lock_task_switches(); - if (!its_mutex_inited) { - mbedtls_mutex_init(&its_mutex); - its_mutex_inited = true; - } - restore_lock_state(kernel_lock_state); - } - if (mbedtls_mutex_lock(&its_mutex) != 0) { - EFM_ASSERT(false); - } -#endif -} - -/** - * \brief Free the ITS mutex. - */ -void sli_its_release_mutex(void) -{ -#if defined(MBEDTLS_THREADING_C) - if (its_mutex_inited) { - mbedtls_mutex_unlock(&its_mutex); - } -#endif -} - -// ------------------------------------- -// Defines - -#if (!SL_PSA_ITS_SUPPORT_V3_DRIVER) -#define SLI_PSA_ITS_NVM3_RANGE_START SLI_PSA_ITS_NVM3_RANGE_BASE -#define SLI_PSA_ITS_NVM3_RANGE_END SLI_PSA_ITS_NVM3_RANGE_START + SL_PSA_ITS_MAX_FILES - -#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) -#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) - -#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE -#error "Trying to store more ITS files then our NVM3 range allows for" -#endif - -#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 - -// Enable backwards-compatibility with keys stored with a v1 header unless disabled. -#if !defined(SL_PSA_ITS_REMOVE_V1_HEADER_SUPPORT) -#define SLI_PSA_ITS_SUPPORT_V1_FORMAT -#endif - -// Internal error codes local to this compile unit -#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) -#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) - -// SLI_STATIC_TESTABLE is used to expose otherwise-static variables during internal testing. -#if !defined(SLI_STATIC_TESTABLE) -#define SLI_STATIC_TESTABLE static -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) -// Define some cryptographic constants if not already set. This depends on the underlying -// crypto accelerator in use (CRYPTOACC has these defines, but not SEMAILBOX). -#if !defined(AES_MAC_SIZE) -#define AES_MAC_SIZE 16 -#endif - -#if !defined(AES_IV_GCM_SIZE) -#define AES_IV_GCM_SIZE 12 -#endif - -#define SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD (AES_IV_GCM_SIZE + AES_MAC_SIZE) -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Local global static variables - -SLI_STATIC_TESTABLE bool nvm3_uid_set_cache_initialized = false; -SLI_STATIC_TESTABLE uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; - -typedef struct { - psa_storage_uid_t uid; - nvm3_ObjectKey_t object_id; - bool set; -} previous_lookup_t; - -static previous_lookup_t previous_lookup = { - 0, 0, false -}; - -#if defined(SLI_PSA_ITS_ENCRYPTED) -// The root key is an AES-256 key, and is therefore 32 bytes. -#define ROOT_KEY_SIZE (32) -// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes -#define SESSION_KEY_SIZE (16) - -#if !defined(SEMAILBOX_PRESENT) -typedef struct { - bool initialized; - uint8_t data[ROOT_KEY_SIZE]; -} root_key_t; - -static root_key_t g_root_key = { - .initialized = false, - .data = { 0 }, -}; -#endif // !defined(SEMAILBOX_PRESENT) - -typedef struct { - bool active; - psa_storage_uid_t uid; - uint8_t data[SESSION_KEY_SIZE]; -} session_key_t; - -static session_key_t g_cached_session_key = { - .active = false, - .uid = 0, - .data = { 0 }, -}; -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Structs - -#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) -typedef struct { - uint32_t magic; - psa_storage_uid_t uid; - psa_storage_create_flags_t flags; -} sl_its_file_meta_v1_t; -#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) - -// Due to alignment constraints on the 64-bit UID, the v2 header struct is -// serialized to 16 bytes instead of the 24 bytes the v1 header compiles to. -typedef struct { - uint32_t magic; - psa_storage_create_flags_t flags; - psa_storage_uid_t uid; -} sli_its_file_meta_v2_t; - -#if defined(SLI_PSA_ITS_ENCRYPTED) -typedef struct { - uint8_t iv[AES_IV_GCM_SIZE]; - // When encrypted & authenticated, MAC is stored at the end of the data array - uint8_t data[]; -} sli_its_encrypted_blob_t; -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Local function prototypes - -static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot); -static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid); - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) -static inline bool object_lives_in_s(const void *object, size_t object_size); -#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) - -#if defined(SLI_PSA_ITS_ENCRYPTED) -static psa_status_t derive_session_key(uint8_t *iv, - size_t iv_size, - uint8_t *session_key, - size_t session_key_size); - -static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, - uint8_t *plaintext, - size_t plaintext_size, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - size_t *blob_length); - -static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, - psa_storage_uid_t *authenticated_uid); -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Local function definitions - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) -// If an object of given size is fully encapsulated in a region of -// secure domain the function returns true. -static inline bool object_lives_in_s(const void *object, size_t object_size) -{ - cmse_address_info_t cmse_flags; - - for (size_t i = 0u; i < object_size; i++) { - cmse_flags = cmse_TTA((uint32_t *)object + i); - if (!cmse_flags.flags.secure) { - return false; - } - } - - return true; -} -#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) - -static inline void cache_set(nvm3_ObjectKey_t key) -{ - uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; - uint32_t bin = i / 32; - uint32_t offset = i - 32 * bin; - nvm3_uid_set_cache[bin] |= (1 << offset); -} - -static inline void cache_clear(nvm3_ObjectKey_t key) -{ - uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; - uint32_t bin = i / 32; - uint32_t offset = i - 32 * bin; - nvm3_uid_set_cache[bin] ^= (1 << offset); -} - -static inline bool cache_lookup(nvm3_ObjectKey_t key) -{ - uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; - uint32_t bin = i / 32; - uint32_t offset = i - 32 * bin; - return (bool)((nvm3_uid_set_cache[bin] >> offset) & 0x1); -} - -static void init_cache(void) -{ - size_t num_keys_referenced_by_nvm3; - nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; - - for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; - range_start < SLI_PSA_ITS_NVM3_RANGE_END; - range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { - nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; - if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { - range_end = SLI_PSA_ITS_NVM3_RANGE_END; - } - - num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, - keys_referenced_by_nvm3, - sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), - range_start, - range_end - 1); - - for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { - cache_set(keys_referenced_by_nvm3[i]); - } - } - - nvm3_uid_set_cache_initialized = true; -} - -// Read the file metadata for a specific NVM3 ID -static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, - sli_its_file_meta_v2_t* metadata, - size_t* its_file_offset, - size_t* its_file_size) -{ - // Initialize output variables to safe default - if (its_file_offset != NULL) { - *its_file_offset = 0; - } - if (its_file_size != NULL) { - *its_file_size = 0; - } - - Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, - key, - metadata, - 0, - sizeof(sli_its_file_meta_v2_t)); - if (status != ECODE_NVM3_OK) { - return status; - } - -#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) - // Re-read in v1 header format and translate to the latest structure version - if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { - sl_its_file_meta_v1_t key_meta_v1 = { 0 }; - status = nvm3_readPartialData(nvm3_defaultHandle, - key, - &key_meta_v1, - 0, - sizeof(sl_its_file_meta_v1_t)); - - if (status != ECODE_NVM3_OK) { - return status; - } - - metadata->flags = key_meta_v1.flags; - metadata->uid = key_meta_v1.uid; - metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; - - if (its_file_offset != NULL) { - *its_file_offset = sizeof(sl_its_file_meta_v1_t); - } - - status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; - } else -#endif - { - if (its_file_offset != NULL) { - *its_file_offset = sizeof(sli_its_file_meta_v2_t); - } - } - - if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { - // No valid header found in this object - return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; - } - - if (its_file_offset != NULL && its_file_size != NULL) { - // Calculate the ITS file size if requested - uint32_t obj_type; - Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, - key, - &obj_type, - its_file_size); - if (info_status != ECODE_NVM3_OK) { - return info_status; - } - - *its_file_size = *its_file_size - *its_file_offset; - } - - return status; -} - -// Search through NVM3 for uid -static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot) -{ - Ecode_t status; - sli_its_file_meta_v2_t key_meta; - - if (find_empty_slot) { - for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { - if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { - return i + SLI_PSA_ITS_NVM3_RANGE_START; - } - } - } else { - if (previous_lookup.set) { - if (previous_lookup.uid == uid) { - return previous_lookup.object_id; - } - } - - for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { - if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { - continue; - } - nvm3_ObjectKey_t object_id = i + SLI_PSA_ITS_NVM3_RANGE_START; - - status = get_file_metadata(object_id, &key_meta, NULL, NULL); - - if (status == ECODE_NVM3_OK - || status == SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - if (key_meta.uid == uid) { - previous_lookup.set = true; - previous_lookup.object_id = object_id; - previous_lookup.uid = uid; - - return object_id; - } else { - continue; - } - } - - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER - || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { - // we don't expect any other data in our range then PSA ITS files. - // delete the file if the magic doesn't match or the object on disk - // is too small to even have full metadata. - status = nvm3_deleteObject(nvm3_defaultHandle, object_id); - if (status != ECODE_NVM3_OK) { - return SLI_PSA_ITS_NVM3_RANGE_END + 1U; - } - } - } - } - - return SLI_PSA_ITS_NVM3_RANGE_END + 1U; -} - -// Perform NVM3 open and fill the look-up table. -// Try to find the mapping NVM3 object ID with PSA ITS UID. -static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid) -{ -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that - // it has been opened (which is done on init) rather than actually doing the init. - if (!nvm3_defaultHandle->hasBeenOpened) { -#else - if (nvm3_initDefault() != ECODE_NVM3_OK) { -#endif - return SLI_PSA_ITS_NVM3_RANGE_END + 1U; - } - - if (nvm3_uid_set_cache_initialized == false) { - init_cache(); - } - - return get_nvm3_id(uid, false); -} - -#if defined(SLI_PSA_ITS_ENCRYPTED) -static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) -{ - // Cache the session key - memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); - g_cached_session_key.uid = uid; - g_cached_session_key.active = true; -} - -/** - * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. - * - * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. - * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). - * \param[out] session_key Pointer to array where derived session key shall be stored. - * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) -{ - if (iv == NULL - || iv_size != AES_IV_GCM_SIZE - || session_key == NULL - || session_key_size < SESSION_KEY_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - -#if defined(SEMAILBOX_PRESENT) - // For HSE devices, use the builtin TrustZone Root Key - psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); - - psa_key_lifetime_t reported_lifetime; - psa_drv_slot_number_t reported_slot; - status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), - &reported_lifetime, - &reported_slot); - - if (status != PSA_SUCCESS) { - return status; - } - - psa_set_key_lifetime(&attributes, reported_lifetime); - - uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; - size_t key_buffer_size; - status = sli_se_opaque_get_builtin_key(reported_slot, - &attributes, - key_buffer, - sizeof(key_buffer), - &key_buffer_size); - if (status != PSA_SUCCESS) { - return status; - } -#else // defined(SEMAILBOX_PRESENT) - // For VSE devices, use the previously initialized root key - if (!g_root_key.initialized) { - return PSA_ERROR_BAD_STATE; - } - - // Prepare root key attributes - psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); - - // Point the key buffer to the global root key - uint8_t *key_buffer = (uint8_t*)g_root_key.data; - size_t key_buffer_size = sizeof(g_root_key.data); -#endif // defined(SEMAILBOX_PRESENT) - - // Use CMAC as a key derivation function - size_t session_key_length; - status = psa_driver_wrapper_mac_compute( - &attributes, - key_buffer, - key_buffer_size, - PSA_ALG_CMAC, - iv, - iv_size, - session_key, - session_key_size, - &session_key_length); - - // Verify that the key derivation was successful before transferring the key to the caller - if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { - memset(session_key, 0, session_key_size); - return PSA_ERROR_HARDWARE_FAILURE; - } - - return status; -} - -/** - * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. - * - * \param[in] metadata ITS metadata to be used as authenticated additional data. - * \param[in] plaintext Pointer to array containing data to be encrypted. - * \param[in] plaintext_size Size of provided plaintext data array. - * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. - * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - * \param[out] blob_length Resulting size of the output blob. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, - uint8_t *plaintext, - size_t plaintext_size, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - size_t *blob_length) -{ - if (metadata == NULL - || (plaintext == NULL && plaintext_size > 0) - || blob == NULL - || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - || blob_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Generate IV - size_t iv_length = 0; - psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_IV_GCM_SIZE, &iv_length); - - if (psa_status != PSA_SUCCESS || iv_length != AES_IV_GCM_SIZE) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Prepare encryption key - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); - psa_set_key_algorithm(&attributes, PSA_ALG_GCM); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); - - uint8_t session_key[SESSION_KEY_SIZE]; - psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); - if (psa_status != PSA_SUCCESS) { - return psa_status; - } - - cache_session_key(session_key, metadata->uid); - - // Retrieve data to be encrypted - if (plaintext_size != 0U) { - memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); - } - - // Encrypt and authenticate blob - size_t output_length = 0; - psa_status = psa_driver_wrapper_aead_encrypt( - &attributes, - session_key, sizeof(session_key), - PSA_ALG_GCM, - blob->iv, sizeof(blob->iv), - (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD - blob->data, plaintext_size, - blob->data, plaintext_size + AES_MAC_SIZE, // output == input for in-place encryption - &output_length); - - // Clear the local session key immediately after we're done using it - memset(session_key, 0, sizeof(session_key)); - - if (psa_status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - if (output_length != plaintext_size + AES_MAC_SIZE) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *blob_length = output_length + AES_IV_GCM_SIZE; - - return PSA_SUCCESS; -} - -/** - * \brief Decrypt and authenticate encrypted ITS data. - * - * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. - * \param[in] blob Encrypted blob containing data to be decrypted. - * \param[in] blob_size Size of the encrypted blob in bytes. - * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. - * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_MAC_SIZE. - * \param[out] plaintext_length Resulting length of the decrypted plaintext. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length) -{ - if (metadata == NULL - || blob == NULL - || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - || (plaintext == NULL && plaintext_size > 0) - || plaintext_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Prepare decryption key - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); - psa_set_key_algorithm(&attributes, PSA_ALG_GCM); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); - - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t session_key[SESSION_KEY_SIZE]; - - if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { - // Use cached session key if it's already set and UID matches - memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); - } else { - psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); - if (psa_status != PSA_SUCCESS) { - return psa_status; - } - cache_session_key(session_key, metadata->uid); - } - - // Decrypt and authenticate blob - size_t output_length = 0; - psa_status = psa_driver_wrapper_aead_decrypt( - &attributes, - session_key, sizeof(session_key), - PSA_ALG_GCM, - blob->iv, sizeof(blob->iv), - (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD - blob->data, plaintext_size + AES_MAC_SIZE, - plaintext, plaintext_size, - &output_length); - - // Clear the session key immediately after we're done using it - memset(session_key, 0, sizeof(session_key)); - - // Invalid signature likely means that NVM data was tampered with - if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - if (psa_status != PSA_SUCCESS - || output_length != plaintext_size) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *plaintext_length = output_length; - - return PSA_SUCCESS; -} - -/** - * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. - * - * \details NOTE: This function will run decrypt_its_file() internally. The difference from the decrypt_its_file() - * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the - * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the - * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. - * - * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. - * \param[out] authenticated_uid UID for the authenticated ITS file. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, - psa_storage_uid_t *authenticated_uid) -{ - psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; - sli_its_file_meta_v2_t *its_file_meta = NULL; - sli_its_encrypted_blob_t *blob = NULL; - - uint32_t obj_type; - size_t its_file_size = 0; - Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, - nvm3_object_id, - &obj_type, - &its_file_size); - if (status != ECODE_NVM3_OK) { - return PSA_ERROR_STORAGE_FAILURE; - } - - uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memset(its_file_buffer, 0, its_file_size); - - status = nvm3_readData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, - its_file_size); - if (status != ECODE_NVM3_OK) { - ret = PSA_ERROR_STORAGE_FAILURE; - goto cleanup; - } - - its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; - blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); - - // Decrypt and authenticate blob - size_t plaintext_length; - ret = decrypt_its_file(its_file_meta, - blob, - its_file_size - sizeof(sli_its_file_meta_v2_t), - blob->data, - its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (ret != PSA_SUCCESS) { - goto cleanup; - } - - if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - ret = PSA_ERROR_INVALID_SIGNATURE; - goto cleanup; - } - - if (authenticated_uid != NULL) { - *authenticated_uid = its_file_meta->uid; - } - - ret = PSA_SUCCESS; - - cleanup: - - // Discard output, as we're only interested in whether the authentication check passed or not. - memset(its_file_buffer, 0, its_file_size); - mbedtls_free(its_file_buffer); - - return ret; -} -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Global function definitions - -/** - * \brief create a new or modify an existing uid/value pair - * - * \param[in] uid the identifier for the data - * \param[in] data_length The size in bytes of the data in `p_data` - * \param[in] p_data A buffer containing the data - * \param[in] create_flags The flags that the data will be stored with - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid - * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) - * is invalid, for example is `NULL` or references memory the caller cannot access - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -psa_status_t psa_its_set(psa_storage_uid_t uid, - uint32_t data_length, - const void *p_data, - psa_storage_create_flags_t create_flags) -{ - if (data_length > NVM3_MAX_OBJECT_SIZE) { - return PSA_ERROR_STORAGE_FAILURE; - } - if ((data_length != 0U) && (p_data == NULL)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE - && create_flags != PSA_STORAGE_FLAG_NONE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - return PSA_ERROR_NOT_SUPPORTED; - } - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) - && (!object_lives_in_s(p_data, data_length))) { - // The flag indicates that this data should not be set by the non-secure domain - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif - sli_its_acquire_mutex(); - nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); - Ecode_t status; - psa_status_t ret = PSA_SUCCESS; - sli_its_file_meta_v2_t* its_file_meta; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - psa_storage_uid_t authenticated_uid; - sli_its_encrypted_blob_t *blob = NULL; - size_t blob_length = 0u; - psa_status_t psa_status; - - size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#else - size_t its_file_size = data_length; -#endif - - uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); - if (its_file_buffer == NULL) { - ret = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - - its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - // ITS UID was not found. Request a new. - nvm3_object_id = get_nvm3_id(0ULL, true); - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - // The storage is full, or an error was returned during cleanup. - ret = PSA_ERROR_INSUFFICIENT_STORAGE; - } else { - its_file_meta->uid = uid; - its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; - } - } else { - // ITS UID was found. Read ITS meta data. - status = get_file_metadata(nvm3_object_id, its_file_meta, NULL, NULL); - - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - ret = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - - if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - ret = PSA_ERROR_NOT_PERMITTED; - goto exit; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. - ret = authenticate_its_file(nvm3_object_id, &authenticated_uid); - if (ret != PSA_SUCCESS) { - goto exit; - } - - if (authenticated_uid != uid) { - ret = PSA_ERROR_NOT_PERMITTED; - goto exit; - } -#endif - } - - its_file_meta->flags = create_flags; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Everything after the file metadata will make up the encrypted & authenticated blob - blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); - - // Encrypt and authenticate the provided data - psa_status = encrypt_its_file(its_file_meta, - (uint8_t*)p_data, - data_length, - blob, - its_file_size, - &blob_length); - - if (psa_status != PSA_SUCCESS) { - ret = psa_status; - goto exit; - } - - if (blob_length != its_file_size) { - ret = PSA_ERROR_HARDWARE_FAILURE; - goto exit; - } - -#else - if (data_length != 0U) { - memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); - } -#endif - - status = nvm3_writeData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); - - if (status == ECODE_NVM3_OK) { - // Power-loss might occur, however upon boot, the look-up table will be - // re-filled as long as the data has been successfully written to NVM3. - cache_set(nvm3_object_id); - } else { - ret = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - if (its_file_buffer != NULL) { - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - mbedtls_free(its_file_buffer); - } - sli_its_release_mutex(); - return ret; -} - -/** - * \brief Retrieve the value associated with a provided uid - * - * \param[in] uid The uid value - * \param[in] data_offset The starting offset of the data requested - * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) - * \param[out] p_data The buffer where the data will be placed upon successful completion - * \param[out] p_data_length The amount of data returned in the p_data buffer - * - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage - * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) - * is invalid. For example is `NULL` or references memory the caller cannot access. - * In addition, this can also happen if an invalid offset was provided. - */ -psa_status_t psa_its_get(psa_storage_uid_t uid, - uint32_t data_offset, - uint32_t data_length, - void *p_data, - size_t *p_data_length) -{ - psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; - - if ((data_length != 0U) && (p_data_length == NULL)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (data_length != 0U) { - // If the request amount of data is 0, allow invalid pointer of the output buffer. - if ((p_data == NULL) - || ((uint32_t)p_data < SRAM_BASE) - || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - sli_its_encrypted_blob_t *blob = NULL; - size_t plaintext_length; - psa_status_t psa_status; -#endif - size_t its_file_data_size = 0u; - Ecode_t status; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - - sli_its_acquire_mutex(); - nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - ret = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - - status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { - ret = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - ret = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE - && !object_lives_in_s(p_data, data_length)) { - // The flag indicates that this data should not be read back to the non-secure domain - ret = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Subtract IV and MAC from ITS file as the below checks concern the actual data size - its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#else - its_file_data_size = its_file_size; -#endif - - if (data_length != 0U) { - if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { - ret = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if ((its_file_data_size == 0U) && (data_offset != 0U)) { - ret = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - } else { - // Allow the offset at the data size boundary if the requested amount of data is zero. - if (data_offset > its_file_data_size) { - ret = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - } - - if (data_length > (its_file_data_size - data_offset)) { - *p_data_length = its_file_data_size - data_offset; - } else { - *p_data_length = data_length; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // its_file_size includes size of sli_its_encrypted_blob_t struct - blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); - if (blob == NULL) { - ret = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - memset(blob, 0, its_file_size); - - status = nvm3_readPartialData(nvm3_defaultHandle, - nvm3_object_id, - blob, - its_file_offset, - its_file_size); - if (status != ECODE_NVM3_OK) { - ret = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - - // Decrypt and authenticate blob - psa_status = decrypt_its_file(&its_file_meta, - blob, - its_file_size, - blob->data, - its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (psa_status != PSA_SUCCESS) { - ret = psa_status; - goto exit; - } - - if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - ret = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - - // Verify that the requested UID is equal to the retrieved and authenticated UID - if (uid != its_file_meta.uid) { - ret = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if (*p_data_length > 0) { - memcpy(p_data, blob->data + data_offset, *p_data_length); - } - ret = PSA_SUCCESS; - - exit: - if (blob != NULL) { - memset(blob, 0, its_file_size); - mbedtls_free(blob); - } - sli_its_release_mutex(); -#else - // If no encryption is used, just read out the data and write it directly to the output buffer - status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); - - if (status != ECODE_NVM3_OK) { - ret = PSA_ERROR_STORAGE_FAILURE; - } else { - ret = PSA_SUCCESS; - } - - exit: - sli_its_release_mutex(); -#endif - - return ret; -} - -/** - * \brief Retrieve the metadata about the provided uid - * - * \param[in] uid The uid value - * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) - * is invalid, for example is `NULL` or references memory the caller cannot access - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. - */ -psa_status_t psa_its_get_info(psa_storage_uid_t uid, - struct psa_storage_info_t *p_info) -{ - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - - if (p_info == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - Ecode_t status; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - - sli_its_acquire_mutex(); - nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - psa_status = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - - status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { - psa_status = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Authenticate the ITS file (both metadata and ciphertext) before returning the metadata. - // Note that this can potentially induce a significant performance hit. - psa_storage_uid_t authenticated_uid; - psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); - if (psa_status != PSA_SUCCESS) { - goto exit; - } - - if (authenticated_uid != uid) { - psa_status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } -#endif - - p_info->flags = its_file_meta.flags; - p_info->size = its_file_size; - - psa_status = PSA_SUCCESS; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Remove IV and MAC size from file size - p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#endif - exit: - sli_its_release_mutex(); - return psa_status; -} - -/** - * \brief Remove the provided key and its associated data from the storage - * - * \param[in] uid The uid value - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - */ -psa_status_t psa_its_remove(psa_storage_uid_t uid) -{ - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - Ecode_t status; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - - sli_its_acquire_mutex(); - nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - psa_status = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - - status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { - psa_status = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - - if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - || its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - psa_status = PSA_ERROR_NOT_PERMITTED; - goto exit; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. - psa_storage_uid_t authenticated_uid; - psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); - if (psa_status != PSA_SUCCESS) { - goto exit; - } - - if (authenticated_uid != uid) { - psa_status = PSA_ERROR_NOT_PERMITTED; - goto exit; - } -#endif - - status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); - - if (status == ECODE_NVM3_OK) { - // Power-loss might occur, however upon boot, the look-up table will be - // re-filled as long as the data has been successfully written to NVM3. - if (previous_lookup.set && previous_lookup.uid == uid) { - previous_lookup.set = false; - } - cache_clear(nvm3_object_id); - - psa_status = PSA_SUCCESS; - } else { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - sli_its_release_mutex(); - return psa_status; -} - -// ------------------------------------- -// Silicon Labs extensions -static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) -{ -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - // Encode the owner in the upper 32 bits. This means that if - // owner values are nonzero (as they are on a PSA platform), - // no key file will ever have a value less than 0x100000000, so - // the whole range 0..0xffffffff is available for non-key files. - uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); - return ((uint64_t)unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); -#else - // Use the key id directly as a file name. - // psa_is_key_id_valid() in psa_crypto_slot_management.c - // is responsible for ensuring that key identifiers do not have a - // value that is reserved for non-key files. - return key; -#endif -} - -psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, - mbedtls_svc_key_id_t new_id) -{ - psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); - psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); - Ecode_t status; - uint32_t obj_type; - size_t its_file_size = 0; - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - int8_t *its_file_buffer = NULL; - sli_its_file_meta_v2_t* metadata = NULL; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - sli_its_encrypted_blob_t *blob = NULL; - size_t plaintext_length; - size_t blob_length; - psa_status_t encrypt_status; - psa_status_t decrypt_status; -#endif - sli_its_acquire_mutex(); - - // Check whether the key to migrate exists on disk - nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(old_uid); - if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { - psa_status = PSA_ERROR_DOES_NOT_EXIST; - goto exit; - } - - // Get total length to allocate - status = nvm3_getObjectInfo(nvm3_defaultHandle, - nvm3_object_id, - &obj_type, - &its_file_size); - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - - // Allocate temporary buffer and cast it to the metadata format - its_file_buffer = mbedtls_calloc(1, its_file_size); - if (its_file_buffer == NULL) { - psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - metadata = (sli_its_file_meta_v2_t*) its_file_buffer; - - // Read contents of pre-existing key into the temporary buffer - status = nvm3_readData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, - its_file_size); - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Decrypt and authenticate blob - blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); - decrypt_status = decrypt_its_file(metadata, - blob, - its_file_size - sizeof(sli_its_file_meta_v2_t), - blob->data, - its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (decrypt_status != PSA_SUCCESS) { - psa_status = decrypt_status; - goto exit; - } - - if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - psa_status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } -#endif - - // Swap out the old UID for the new one -#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) - if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { - // Recast as v1 metadata - sl_its_file_meta_v1_t* metadata_v1 = (sl_its_file_meta_v1_t*) its_file_buffer; - if (metadata_v1->uid != old_uid) { - psa_status = PSA_ERROR_CORRUPTION_DETECTED; - goto exit; - } - metadata_v1->uid = new_uid; - } else -#endif - if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V2) { - if (metadata->uid != old_uid) { - psa_status = PSA_ERROR_CORRUPTION_DETECTED; - goto exit; - } - metadata->uid = new_uid; - } else { - psa_status = PSA_ERROR_CORRUPTION_DETECTED; - goto exit; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Encrypt and authenticate the modified data data - encrypt_status = encrypt_its_file(metadata, - blob->data, - plaintext_length, - blob, - its_file_size - sizeof(sli_its_file_meta_v2_t), - &blob_length); - - if (encrypt_status != PSA_SUCCESS) { - psa_status = encrypt_status; - goto exit; - } - - if (blob_length != (its_file_size - sizeof(sli_its_file_meta_v2_t))) { - psa_status = PSA_ERROR_HARDWARE_FAILURE; - goto exit; - } -#endif - - // Overwrite the NVM3 token with the changed buffer - status = nvm3_writeData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, - its_file_size); - if (status == ECODE_NVM3_OK) { - // Update last lookup and report success - if (previous_lookup.set) { - if (previous_lookup.uid == old_uid) { - previous_lookup.uid = new_uid; - } - } - psa_status = PSA_SUCCESS; - } else { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - if (its_file_buffer != NULL) { - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size); - mbedtls_free(its_file_buffer); - } - sli_its_release_mutex(); - return psa_status; -} - -/** - * \brief Check if the ITS encryption is enabled - */ -psa_status_t sli_psa_its_encrypted(void) -{ - #if defined(SLI_PSA_ITS_ENCRYPTED) - return PSA_SUCCESS; - #else - return PSA_ERROR_NOT_SUPPORTED; - #endif -} - -#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) -/** - * \brief Set the root key to be used when deriving session keys for ITS encryption. - * - * \param[in] root_key Buffer containing the root key. - * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The key was successfully set. - * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. - * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. - */ -psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) -{ - // Check that arguments are valid - if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check that the root key has not already been set - // (This is possibly too restrictive. For TrustZone usage this can be enforced by - // not exposing the function to NS instead.) - if (g_root_key.initialized) { - return PSA_ERROR_ALREADY_EXISTS; - } - - // Store the provided root key and mark it as initialized - memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); - g_root_key.initialized = true; - - return PSA_SUCCESS; -} -#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) - -#else // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) - -// ------------------------------------- -// Defines -#define SLI_PSA_ITS_V3_DRIVER (0x3A) -#define SLI_PSA_ITS_V2_DRIVER (0x74) -#define SLI_PSA_ITS_NOT_CHECKED (0xE8) -#define SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID (SLI_PSA_ITS_NVM3_RANGE_START - 1) -#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) -#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) - -#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE -#error "Trying to store more ITS files then our NVM3 range allows for" -#endif - -#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 - -// Internal error codes local to this compile unit -#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) -#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) - -// SLI_STATIC_TESTABLE is used to expose otherwise-static variables during internal testing. -#if !defined(SLI_STATIC_TESTABLE) -#define SLI_STATIC_TESTABLE static -#endif - -// ------------------------------------- -// Local global static variables - -SLI_STATIC_TESTABLE bool nvm3_uid_set_cache_initialized = false; -SLI_STATIC_TESTABLE uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; -SLI_STATIC_TESTABLE uint32_t nvm3_uid_tomb_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; -#if SL_PSA_ITS_SUPPORT_V2_DRIVER -SLI_STATIC_TESTABLE uint32_t its_driver_version = SLI_PSA_ITS_NOT_CHECKED; -#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER - -#if defined(SLI_PSA_ITS_ENCRYPTED) -// The root key is an AES-256 key, and is therefore 32 bytes. -#define ROOT_KEY_SIZE (32) -// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes -#define SESSION_KEY_SIZE (16) - -#if !defined(SEMAILBOX_PRESENT) -typedef struct { - bool initialized; - uint8_t data[ROOT_KEY_SIZE]; -} root_key_t; - -static root_key_t g_root_key = { - .initialized = false, - .data = { 0 }, -}; -#endif // !defined(SEMAILBOX_PRESENT) - -typedef struct { - bool active; - psa_storage_uid_t uid; - uint8_t data[SESSION_KEY_SIZE]; -} session_key_t; - -static session_key_t g_cached_session_key = { - .active = false, - .uid = 0, - .data = { 0 }, -}; -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Structs - -#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) -typedef struct { - uint32_t magic; - psa_storage_uid_t uid; - psa_storage_create_flags_t flags; -} sl_its_file_meta_v1_t; -#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) - -// ------------------------------------- -// Local function prototypes - -static psa_status_t find_nvm3_id(psa_storage_uid_t uid, - bool find_empty_slot, - sli_its_file_meta_v2_t* its_file_meta, - size_t* its_file_offset, - size_t* its_file_size, - nvm3_ObjectKey_t * output_nvm3_id); -static nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid); - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) -static inline bool object_lives_in_s(const void *object, size_t object_size); -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) -static psa_status_t derive_session_key(uint8_t *iv, - size_t iv_size, - uint8_t *session_key, - size_t session_key_size); - -static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, - psa_storage_uid_t *authenticated_uid); -#endif - -#if SL_PSA_ITS_SUPPORT_V2_DRIVER -static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, - sli_its_file_meta_v2_t* its_file_meta, - size_t its_file_size, - size_t its_file_offset, void *p_data); -static psa_status_t detect_legacy_versions(); -static psa_status_t upgrade_all_keys(); - -#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) -psa_status_t psa_its_set_v1(psa_storage_uid_t uid, - uint32_t data_length, - const void *p_data, - psa_storage_create_flags_t create_flags); -#endif // SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL -#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER - -// ------------------------------------- -// Local function definitions -static inline uint32_t get_index(nvm3_ObjectKey_t key) -{ - return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) / 32; -} - -static inline uint32_t get_offset(nvm3_ObjectKey_t key) -{ - return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) % 32; -} - -static inline void set_cache(nvm3_ObjectKey_t key) -{ - nvm3_uid_set_cache[get_index(key)] |= (1 << get_offset(key)); - nvm3_uid_tomb_cache[get_index(key)] &= ~(1 << get_offset(key)); -} - -static inline void set_tomb(nvm3_ObjectKey_t key) -{ - nvm3_uid_tomb_cache[get_index(key)] |= (1 << get_offset(key)); - - uint32_t cache_not_empty = 0; - for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { - cache_not_empty += nvm3_uid_set_cache[i]; - } - if (cache_not_empty == 0) { - for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { - nvm3_uid_tomb_cache[i] = 0; - } - } -} - -#if SL_PSA_ITS_SUPPORT_V2_DRIVER -static inline psa_status_t write_driver_v3() -{ - uint8_t driver_verison = SLI_PSA_ITS_V3_DRIVER; - Ecode_t status; - status = nvm3_writeData(nvm3_defaultHandle, - SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, - &driver_verison, sizeof(uint8_t)); - if ( status != ECODE_NVM3_OK ) { - return PSA_ERROR_STORAGE_FAILURE; - } - return PSA_SUCCESS; -} -#endif - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) -// If an object of given size is fully encapsulated in a region of -// secure domain the function returns true. -static inline bool object_lives_in_s(const void *object, size_t object_size) -{ - cmse_address_info_t cmse_flags; - - for (size_t i = 0u; i < object_size; i++) { - cmse_flags = cmse_TTA((uint32_t *)object + i); - if (!cmse_flags.flags.secure) { - return false; - } - } - - return true; -} -#endif - -static inline void clear_cache(nvm3_ObjectKey_t key) -{ - nvm3_uid_set_cache[get_index(key)] ^= (1 << get_offset(key)); -} - -static inline bool lookup_cache(nvm3_ObjectKey_t key) -{ - return (bool)((nvm3_uid_set_cache[get_index(key)] >> get_offset(key)) & 0x1); -} - -static inline bool lookup_tomb(nvm3_ObjectKey_t key) -{ - return (bool)((nvm3_uid_tomb_cache[get_index(key)] >> get_offset(key)) & 0x1); -} - -static inline nvm3_ObjectKey_t increment_obj_id(nvm3_ObjectKey_t id) -{ - return SLI_PSA_ITS_NVM3_RANGE_START + ((id - SLI_PSA_ITS_NVM3_RANGE_START + 1) - % SL_PSA_ITS_MAX_FILES); -} -static inline nvm3_ObjectKey_t prng(psa_storage_uid_t uid) -{ -// Squash uid down to a 32 bit word - nvm3_ObjectKey_t uid_32 = uid & 0xFFFFFFFF; - nvm3_ObjectKey_t xored_32 = (uid >> 32) ^ uid_32; - nvm3_ObjectKey_t temp; -// Accumulate all "entropy" towards the LSB, since that is where we need it - for ( size_t i = 1; i < 4; i++ ) { - temp = xored_32 ^ (xored_32 >> (8 * i)); - if ((temp & 0x3) != 0 ) { - temp = temp << 2; - } - uid_32 = (uid_32 + temp); - } - return uid_32; -} - -static inline nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid) -{ - return SLI_PSA_ITS_NVM3_RANGE_START + (prng(uid) % (SL_PSA_ITS_MAX_FILES)); -} - -static void init_cache(void) -{ - size_t num_keys_referenced_by_nvm3; - nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; - size_t num_del_keys_from_nvm3; - nvm3_ObjectKey_t deleted_keys_from_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; - for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; - range_start < SLI_PSA_ITS_NVM3_RANGE_END; - range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { - nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; - if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { - range_end = SLI_PSA_ITS_NVM3_RANGE_END; - } - - num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, - keys_referenced_by_nvm3, - sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), - range_start, - range_end - 1); - - for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { - set_cache(keys_referenced_by_nvm3[i]); - } - num_del_keys_from_nvm3 = nvm3_enumDeletedObjects(nvm3_defaultHandle, - deleted_keys_from_nvm3, - sizeof(deleted_keys_from_nvm3) / sizeof(nvm3_ObjectKey_t), - range_start, - range_end - 1); - for (size_t i = 0; i < num_del_keys_from_nvm3; i++) { - set_tomb(deleted_keys_from_nvm3[i]); - } - } - nvm3_uid_set_cache_initialized = true; -} - -// Read the file metadata for a specific NVM3 ID -static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, - sli_its_file_meta_v2_t* metadata, - size_t* its_file_offset, - size_t* its_file_size) -{ - // Initialize output variables to safe default - if (its_file_offset != NULL) { - *its_file_offset = 0; - } - if (its_file_size != NULL) { - *its_file_size = 0; - } - - Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, - key, - metadata, - 0, - sizeof(sli_its_file_meta_v2_t)); - if (status != ECODE_NVM3_OK) { - return status; - } - -#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) - // Re-read in v1 header format and translate to the latest structure version - if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { - sl_its_file_meta_v1_t key_meta_v1 = { 0 }; - status = nvm3_readPartialData(nvm3_defaultHandle, - key, - &key_meta_v1, - 0, - sizeof(sl_its_file_meta_v1_t)); - - if (status != ECODE_NVM3_OK) { - return status; - } - - metadata->flags = key_meta_v1.flags; - metadata->uid = key_meta_v1.uid; - metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; - - if (its_file_offset != NULL) { - *its_file_offset = sizeof(sl_its_file_meta_v1_t); - } - - status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; - } else -#endif - { - if (its_file_offset != NULL) { - *its_file_offset = sizeof(sli_its_file_meta_v2_t); - } - } - - if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { - // No valid header found in this object - return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; - } - - if (its_file_offset != NULL && its_file_size != NULL) { - // Calculate the ITS file size if requested - uint32_t obj_type; - Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, - key, - &obj_type, - its_file_size); - if (info_status != ECODE_NVM3_OK) { - return info_status; - } - - *its_file_size = *its_file_size - *its_file_offset; - } - - return status; -} - -#if SL_PSA_ITS_SUPPORT_V2_DRIVER -static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, - sli_its_file_meta_v2_t* its_file_meta, - size_t its_file_size, - size_t its_file_offset, - void *p_data) -{ - Ecode_t status; - if (its_file_size == 0) { - if (its_file_meta != NULL) { - return PSA_ERROR_DATA_INVALID; - } - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - sli_its_encrypted_blob_t *blob = NULL; - size_t plaintext_length; - - // its_file_size includes size of sli_its_encrypted_blob_t struct - blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); - if (blob == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memset(blob, 0, its_file_size); - - status = nvm3_readPartialData(nvm3_defaultHandle, - nvm3_object_id, - blob, - its_file_offset, - its_file_size); - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto cleanup; - } - - // Decrypt and authenticate blob - psa_status = sli_decrypt_its_file(its_file_meta, - blob, - its_file_size, - blob->data, - its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (psa_status != PSA_SUCCESS) { - goto cleanup; - } - - if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - psa_status = PSA_ERROR_INVALID_SIGNATURE; - goto cleanup; - } - - if (its_file_size + its_file_offset > 0) { - memcpy(p_data, blob->data, its_file_size + its_file_offset); - } - psa_status = PSA_SUCCESS; - - cleanup: - if (blob != NULL) { - memset(blob, 0, its_file_size); - mbedtls_free(blob); - } - return psa_status; -#else - // If no encryption is used, just read out the data and write it directly to the output buffer - status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, - its_file_offset, its_file_size); - - if (status != ECODE_NVM3_OK) { - return PSA_ERROR_STORAGE_FAILURE; - } else { - return PSA_SUCCESS; - } -#endif -} - -// Function sets detect the presence of v1 and v2 its driver. If there is something -// stored in v1/v2 driver range, it sets its_driver_version to SLI_PSA_ITS_V2_DRIVER. -static psa_status_t detect_legacy_versions() -{ - uint8_t driver_verison = 0; - Ecode_t status; - status = nvm3_readData(nvm3_defaultHandle, SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, - &driver_verison, sizeof(uint8_t)); - if ((status != ECODE_NVM3_OK) && (status != ECODE_NVM3_ERR_KEY_NOT_FOUND)) { - return PSA_ERROR_STORAGE_FAILURE; - } - if (driver_verison == SLI_PSA_ITS_V3_DRIVER) { - its_driver_version = SLI_PSA_ITS_V3_DRIVER; - return PSA_SUCCESS; - } - - size_t num_keys_referenced_by_nvm3; - - nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { - 0 - }; - - for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; - range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; - range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { - nvm3_ObjectKey_t range_end = - range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; - if (range_end > SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { - range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; - } - - num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, - keys_referenced_by_nvm3, - sizeof(keys_referenced_by_nvm3) - / sizeof(nvm3_ObjectKey_t), - range_start, - range_end - 1); - - if (num_keys_referenced_by_nvm3 > 0) { - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - status = get_file_metadata(keys_referenced_by_nvm3[0], - &its_file_meta, &its_file_offset, - &its_file_size); - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { - return PSA_ERROR_DOES_NOT_EXIST; - } - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - return PSA_ERROR_STORAGE_FAILURE; - } - - if ((its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) - || (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2)) { - its_driver_version = SLI_PSA_ITS_V2_DRIVER; - return PSA_SUCCESS; - } else { - return PSA_ERROR_STORAGE_FAILURE; - } - } - } - its_driver_version = SLI_PSA_ITS_V3_DRIVER; - return PSA_SUCCESS; -} - -static psa_status_t upgrade_all_keys() -{ - size_t num_keys_referenced_by_nvm3; - nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { - 0 - }; - Ecode_t status; - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_data_size; - uint8_t * its_file_buffer = NULL; - - size_t its_file_size = 0; - size_t its_file_offset; - - for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; - range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; - range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { - nvm3_ObjectKey_t range_end = - range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; - if (range_end >= SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { - range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; - } - - num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, - keys_referenced_by_nvm3, - sizeof(keys_referenced_by_nvm3) - / - sizeof(nvm3_ObjectKey_t), - range_start, - range_end - 1); - for ( size_t i = 0; i < num_keys_referenced_by_nvm3; i++ ) { - its_file_size = 0; - its_file_offset = 0; - status = get_file_metadata(keys_referenced_by_nvm3[i], - &(its_file_meta), &its_file_offset, - &its_file_size); - if ( status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { - return PSA_ERROR_DOES_NOT_EXIST; - } - if ( status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - return PSA_ERROR_STORAGE_FAILURE; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Subtract IV and MAC from ITS file as the below checks concern the actual data size - its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#else - its_file_data_size = its_file_size; -#endif - - if ((its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V2) - && (its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V1)) { - return PSA_ERROR_STORAGE_FAILURE; - } - its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } -#if defined(SLI_PSA_ITS_ENCRYPTED) - psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], - &(its_file_meta), - its_file_size, - its_file_offset, - its_file_buffer); -#else - psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], - NULL, - its_file_size, - its_file_offset, - its_file_buffer); -#endif - if (psa_status != PSA_SUCCESS) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - -#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) - if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) { - psa_status = psa_its_set_v1(its_file_meta.uid, its_file_data_size, - its_file_buffer, its_file_meta.flags); - } else if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2) -#endif - { - psa_status = psa_its_set(its_file_meta.uid, its_file_data_size, - its_file_buffer, its_file_meta.flags); - } - - if ((psa_status != PSA_SUCCESS) && (psa_status - != PSA_ERROR_NOT_PERMITTED)) { - goto exit; - } - status = nvm3_deleteObject(nvm3_defaultHandle, - keys_referenced_by_nvm3[i]); - - if ( status != ECODE_NVM3_OK ) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - mbedtls_free(its_file_buffer); - } - } - return PSA_SUCCESS; - - exit: - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - mbedtls_free(its_file_buffer); - return psa_status; -} - -#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) -psa_status_t psa_its_set_v1(psa_storage_uid_t uid, - uint32_t data_length, - const void *p_data, - psa_storage_create_flags_t create_flags) -{ - if ((data_length != 0U) && (p_data == NULL)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE - && create_flags != PSA_STORAGE_FLAG_NONE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - return PSA_ERROR_NOT_SUPPORTED; - } - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) - && (!object_lives_in_s(p_data, data_length))) { - // The flag indicates that this data should not be set by the non-secure domain - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif - - Ecode_t status; - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - sl_its_file_meta_v1_t* its_file_meta; - nvm3_ObjectKey_t nvm3_object_id = 0; - size_t its_file_size = data_length; - - uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sl_its_file_meta_v1_t)); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); - - its_file_meta = (sl_its_file_meta_v1_t *)its_file_buffer; - sli_its_file_meta_v2_t its_file_meta_v2; - - sli_its_acquire_mutex(); - psa_status = find_nvm3_id(uid, true, &its_file_meta_v2, NULL, NULL, - &nvm3_object_id); - if (psa_status != PSA_SUCCESS) { - if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { - psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; - } - goto exit; - } - - its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V1; - its_file_meta->uid = uid; - its_file_meta->flags = create_flags; - - if (data_length != 0U) { - memcpy(its_file_buffer + sizeof(sl_its_file_meta_v1_t), ((uint8_t*) - p_data), data_length); - } - - status = nvm3_writeData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, its_file_size + sizeof - (sl_its_file_meta_v1_t)); - - if (status == ECODE_NVM3_OK) { - // Power-loss might occur, however upon boot, the look-up table will be - // re-filled as long as the data has been successfully written to NVM3. - set_cache(nvm3_object_id); - } else { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); - mbedtls_free(its_file_buffer); - sli_its_release_mutex(); - return psa_status; -} -#endif //SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL -#endif //SL_PSA_ITS_SUPPORT_V1_DRIVER - -/** - * \brief Search through NVM3 for correct uid - * - * \param[in] uid UID under what we want to store the data - * \param[in] find_empty_slot Indicates whether we want to find existing data or empty space for storing new. - * \param[out] its_file_meta Meta information of ITS file - * \param[out] its_file_offset Offset of ITS file - * \param[out] its_file_size Size of ITS file - * \param[out] output_nvm3_id NVM3 ID corresponding to UID. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The data with this UID are not stored in NVM3 - * \retval PSA_ERROR_NOT_PERMITTED The requested operation is not permitted - */ -static psa_status_t find_nvm3_id(psa_storage_uid_t uid, - bool find_empty_slot, - sli_its_file_meta_v2_t* its_file_meta, - size_t* its_file_offset, - size_t* its_file_size, - nvm3_ObjectKey_t * output_nvm3_id) -{ - Ecode_t status; - nvm3_ObjectKey_t tmp_id = 0; - nvm3_ObjectKey_t nvm3_object_id = 0; - nvm3_object_id = derive_nvm3_id(uid); - - if (nvm3_uid_set_cache_initialized == false) { -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) \ - // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that - // it has been opened (which is done on init) rather than actually doing the init. - if (!nvm3_defaultHandle->hasBeenOpened) { -#else - if (nvm3_initDefault() != ECODE_NVM3_OK) { -#endif - return PSA_ERROR_STORAGE_FAILURE; - } - -#if SL_PSA_ITS_SUPPORT_V2_DRIVER - if ( its_driver_version == SLI_PSA_ITS_NOT_CHECKED ) { - if ( detect_legacy_versions() != PSA_SUCCESS ) { - return PSA_ERROR_STORAGE_FAILURE; - } - if ( its_driver_version == SLI_PSA_ITS_V2_DRIVER ) { - psa_status_t psa_status = upgrade_all_keys(); - if ( psa_status != PSA_SUCCESS ) { - return psa_status; - } - psa_status = write_driver_v3(); - if ( psa_status != PSA_SUCCESS ) { - return psa_status; - } - } else { - init_cache(); - } - } else { - init_cache(); - } -#else - init_cache(); -#endif - } - - for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; ++i ) { - if (!lookup_cache(nvm3_object_id)) { - // dont exist - if (lookup_tomb(nvm3_object_id)) { - // tombstone - if (tmp_id == 0 ) { - // mark first empty space - tmp_id = nvm3_object_id; - } - nvm3_object_id = increment_obj_id(nvm3_object_id); - continue; - } else { - // empty space - if (find_empty_slot) { - if (tmp_id != 0) { - *output_nvm3_id = tmp_id; - return PSA_SUCCESS; - } - *output_nvm3_id = nvm3_object_id; - return PSA_SUCCESS; - } else { - return PSA_ERROR_DOES_NOT_EXIST; - } - } - } - status = get_file_metadata(nvm3_object_id, its_file_meta, its_file_offset, - its_file_size); - - if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER - || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { - // we don't expect any other data in our range then PSA ITS files. - // delete the file if the magic doesn't match or the object on disk - // is too small to even have full metadata. - status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); - if (status != ECODE_NVM3_OK) { - return PSA_ERROR_DOES_NOT_EXIST; - } - } - - if (status != ECODE_NVM3_OK - && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { - return PSA_ERROR_STORAGE_FAILURE; - } - - if (its_file_meta->uid != uid) { - nvm3_object_id = increment_obj_id(nvm3_object_id); - } else { - if (find_empty_slot) { - if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - return PSA_ERROR_NOT_PERMITTED; - } - } -#if defined(SLI_PSA_ITS_ENCRYPTED) - // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. - // Note that this can potentially induce a significant performance hit. - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_storage_uid_t authenticated_uid = 0; - psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); - if (psa_status != PSA_SUCCESS) { - return psa_status; - } - - if (authenticated_uid != uid) { - return PSA_ERROR_INVALID_SIGNATURE; - } -#endif - *output_nvm3_id = nvm3_object_id; - return PSA_SUCCESS; - } - } - if (find_empty_slot) { - if (tmp_id != 0) { - *output_nvm3_id = tmp_id; - return PSA_SUCCESS; - } - } - return PSA_ERROR_DOES_NOT_EXIST; -} - -#if defined(SLI_PSA_ITS_ENCRYPTED) -static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) -{ - // Cache the session key - memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); - g_cached_session_key.uid = uid; - g_cached_session_key.active = true; -} - -/** - * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. - * - * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. - * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). - * \param[out] session_key Pointer to array where derived session key shall be stored. - * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) -{ - if (iv == NULL - || iv_size != AES_GCM_IV_SIZE - || session_key == NULL - || session_key_size < SESSION_KEY_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - -#if defined(SEMAILBOX_PRESENT) - // For HSE devices, use the builtin TrustZone Root Key - psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); - - psa_key_lifetime_t reported_lifetime; - psa_drv_slot_number_t reported_slot; - status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), - &reported_lifetime, - &reported_slot); - - if (status != PSA_SUCCESS) { - return status; - } - - psa_set_key_lifetime(&attributes, reported_lifetime); - - uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; - size_t key_buffer_size; - status = sli_se_opaque_get_builtin_key(reported_slot, - &attributes, - key_buffer, - sizeof(key_buffer), - &key_buffer_size); - if (status != PSA_SUCCESS) { - return status; - } -#else // defined(SEMAILBOX_PRESENT) - // For VSE devices, use the previously initialized root key - if (!g_root_key.initialized) { - return PSA_ERROR_BAD_STATE; - } - - // Prepare root key attributes - psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); - - // Point the key buffer to the global root key - uint8_t *key_buffer = (uint8_t*)g_root_key.data; - size_t key_buffer_size = sizeof(g_root_key.data); -#endif // defined(SEMAILBOX_PRESENT) - - // Use CMAC as a key derivation function - size_t session_key_length; - status = psa_driver_wrapper_mac_compute( - &attributes, - key_buffer, - key_buffer_size, - PSA_ALG_CMAC, - iv, - iv_size, - session_key, - session_key_size, - &session_key_length); - - // Verify that the key derivation was successful before transferring the key to the caller - if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { - memset(session_key, 0, session_key_size); - return PSA_ERROR_HARDWARE_FAILURE; - } - - return status; -} - -/** - * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. - * - * \param[in] metadata ITS metadata to be used as authenticated additional data. - * \param[in] plaintext Pointer to array containing data to be encrypted. - * \param[in] plaintext_size Size of provided plaintext data array. - * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. - * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - * \param[out] blob_length Resulting size of the output blob. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -psa_status_t sli_encrypt_its_file(sli_its_file_meta_v2_t *metadata, - uint8_t *plaintext, - size_t plaintext_size, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - size_t *blob_length) -{ - if (metadata == NULL - || (plaintext == NULL && plaintext_size > 0) - || blob == NULL - || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - || blob_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Generate IV - size_t iv_length = 0; - psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_GCM_IV_SIZE, &iv_length); - - if (psa_status != PSA_SUCCESS || iv_length != AES_GCM_IV_SIZE) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Prepare encryption key - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); - psa_set_key_algorithm(&attributes, PSA_ALG_GCM); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); - - uint8_t session_key[SESSION_KEY_SIZE]; - psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); - if (psa_status != PSA_SUCCESS) { - return psa_status; - } - - cache_session_key(session_key, metadata->uid); - - // Retrieve data to be encrypted - if (plaintext_size != 0U) { - memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); - } - - // Encrypt and authenticate blob - size_t output_length = 0; - psa_status = psa_driver_wrapper_aead_encrypt( - &attributes, - session_key, sizeof(session_key), - PSA_ALG_GCM, - blob->iv, sizeof(blob->iv), - (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD - blob->data, plaintext_size, - blob->data, plaintext_size + AES_GCM_MAC_SIZE, // output == input for in-place encryption - &output_length); - - // Clear the local session key immediately after we're done using it - memset(session_key, 0, sizeof(session_key)); - - if (psa_status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - if (output_length != plaintext_size + AES_GCM_MAC_SIZE) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *blob_length = output_length + AES_GCM_IV_SIZE; - - return PSA_SUCCESS; -} - -/** - * \brief Decrypt and authenticate encrypted ITS data. - * - * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. - * \param[in] blob Encrypted blob containing data to be decrypted. - * \param[in] blob_size Size of the encrypted blob in bytes. - * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. - * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_GCM_MAC_SIZE. - * \param[out] plaintext_length Resulting length of the decrypted plaintext. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, - sli_its_encrypted_blob_t *blob, - size_t blob_size, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length) -{ - if (metadata == NULL - || blob == NULL - || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD - || (plaintext == NULL && plaintext_size > 0) - || plaintext_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Prepare decryption key - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); - psa_set_key_algorithm(&attributes, PSA_ALG_GCM); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); - - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t session_key[SESSION_KEY_SIZE]; - - if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { - // Use cached session key if it's already set and UID matches - memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); - } else { - psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); - if (psa_status != PSA_SUCCESS) { - return psa_status; - } - cache_session_key(session_key, metadata->uid); - } - - // Decrypt and authenticate blob - size_t output_length = 0; - psa_status = psa_driver_wrapper_aead_decrypt( - &attributes, - session_key, sizeof(session_key), - PSA_ALG_GCM, - blob->iv, sizeof(blob->iv), - (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD - blob->data, plaintext_size + AES_GCM_MAC_SIZE, - plaintext, plaintext_size, - &output_length); - - // Clear the session key immediately after we're done using it - memset(session_key, 0, sizeof(session_key)); - - // Invalid signature likely means that NVM data was tampered with - if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - if (psa_status != PSA_SUCCESS - || output_length != plaintext_size) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *plaintext_length = output_length; - - return PSA_SUCCESS; -} - -/** - * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. - * - * \details NOTE: This function will run sli_decrypt_its_file() internally. The difference from the sli_decrypt_its_file() - * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the - * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the - * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. - * - * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. - * \param[out] authenticated_uid UID for the authenticated ITS file. - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. - * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - */ -static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, - psa_storage_uid_t *authenticated_uid) -{ - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - sli_its_file_meta_v2_t *its_file_meta = NULL; - sli_its_encrypted_blob_t *blob = NULL; - - uint32_t obj_type; - size_t its_file_size = 0; - Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, - nvm3_object_id, - &obj_type, - &its_file_size); - if (status != ECODE_NVM3_OK) { - return PSA_ERROR_STORAGE_FAILURE; - } - - uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memset(its_file_buffer, 0, its_file_size); - - status = nvm3_readData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, - its_file_size); - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto cleanup; - } - - its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; - blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); - - // Decrypt and authenticate blob - size_t plaintext_length; - psa_status = sli_decrypt_its_file(its_file_meta, - blob, - its_file_size - sizeof(sli_its_file_meta_v2_t), - blob->data, - its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (psa_status != PSA_SUCCESS) { - goto cleanup; - } - - if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - psa_status = PSA_ERROR_INVALID_SIGNATURE; - goto cleanup; - } - - if (authenticated_uid != NULL) { - *authenticated_uid = its_file_meta->uid; - } - - psa_status = PSA_SUCCESS; - - cleanup: - - // Discard output, as we're only interested in whether the authentication check passed or not. - memset(its_file_buffer, 0, its_file_size); - mbedtls_free(its_file_buffer); - - return psa_status; -} -#endif // defined(SLI_PSA_ITS_ENCRYPTED) - -// ------------------------------------- -// Global function definitions - -/** - * \brief create a new or modify an existing uid/value pair - * - * \param[in] uid the identifier for the data - * \param[in] data_length The size in bytes of the data in `p_data` - * \param[in] p_data A buffer containing the data - * \param[in] create_flags The flags that the data will be stored with - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid - * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) - * is invalid, for example is `NULL` or references memory the caller cannot access - * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. - * \retval PSA_ERROR_INVALID_SIGNATURE The operation failed because the provided `uid` doesnt match the autenticated uid from the storage - */ -psa_status_t psa_its_set(psa_storage_uid_t uid, - uint32_t data_length, - const void *p_data, - psa_storage_create_flags_t create_flags) -{ - if ((data_length != 0U) && (p_data == NULL)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if ((data_length > NVM3_MAX_OBJECT_SIZE)) { - return PSA_ERROR_STORAGE_FAILURE; - } - - if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE - && create_flags != PSA_STORAGE_FLAG_NONE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE -#endif - ) { - return PSA_ERROR_NOT_SUPPORTED; - } - -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) - && (!object_lives_in_s(p_data, data_length))) { - // The flag indicates that this data should not be set by the non-secure domain - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif - - Ecode_t status; - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - sli_its_file_meta_v2_t* its_file_meta; - nvm3_ObjectKey_t nvm3_object_id = 0; -#if defined(SLI_PSA_ITS_ENCRYPTED) - sli_its_encrypted_blob_t *blob = NULL; - size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; - size_t blob_length = 0u; -#else - size_t its_file_size = data_length; -#endif - - uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - - its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; - - sli_its_acquire_mutex(); - psa_status = find_nvm3_id(uid, true, its_file_meta, NULL, NULL, &nvm3_object_id); - if (psa_status != PSA_SUCCESS) { - if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { - psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; - } - goto exit; - } - - its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; - its_file_meta->uid = uid; - its_file_meta->flags = create_flags; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Everything after the the file metadata will make up the encrypted & authenticated blob - blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); - - // Encrypt and authenticate the provided data - psa_status = sli_encrypt_its_file(its_file_meta, - (uint8_t*)p_data, - data_length, - blob, - its_file_size, - &blob_length); - - if (psa_status != PSA_SUCCESS) { - goto exit; - } - - if (blob_length != its_file_size) { - psa_status = PSA_ERROR_HARDWARE_FAILURE; - goto exit; - } - -#else - if (data_length != 0U) { - memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); - } -#endif - - status = nvm3_writeData(nvm3_defaultHandle, - nvm3_object_id, - its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); - - if (status == ECODE_NVM3_OK) { - // Power-loss might occur, however upon boot, the look-up table will be - // re-filled as long as the data has been successfully written to NVM3. - set_cache(nvm3_object_id); - } else { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); - mbedtls_free(its_file_buffer); - sli_its_release_mutex(); - return psa_status; -} - -/** - * \brief Retrieve the value associated with a provided uid - * - * \param[in] uid The uid value - * \param[in] data_offset The starting offset of the data requested - * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) - * \param[out] p_data The buffer where the data will be placed upon successful completion - * \param[out] p_data_length The amount of data returned in the p_data buffer - * - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage - * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) - * is invalid. For example is `NULL` or references memory the caller cannot access. - * In addition, this can also happen if an invalid offset was provided. - */ -psa_status_t psa_its_get(psa_storage_uid_t uid, - uint32_t data_offset, - uint32_t data_length, - void *p_data, - size_t *p_data_length) -{ - if ((data_length != 0U) && (p_data_length == NULL)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (data_length != 0U) { - // If the request amount of data is 0, allow invalid pointer of the output buffer. - if ((p_data == NULL) - || ((uint32_t)p_data < SRAM_BASE) - || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - size_t plaintext_length; - sli_its_encrypted_blob_t *blob = NULL; -#endif - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - Ecode_t status; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0u; - size_t its_file_data_size = 0u; - size_t its_file_offset = 0u; - nvm3_ObjectKey_t nvm3_object_id; - - sli_its_acquire_mutex(); - psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); - if (psa_status != PSA_SUCCESS) { - goto exit; - } -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE - && !object_lives_in_s(p_data, data_length)) { - // The flag indicates that this data should not be read back to the non-secure domain - psa_status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } -#endif - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Subtract IV and MAC from ITS file as the below checks concern the actual data size - its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#else - its_file_data_size = its_file_size; -#endif - - if (data_length != 0U) { - if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { - psa_status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if ((its_file_data_size == 0U) && (data_offset != 0U)) { - psa_status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - } else { - // Allow the offset at the data size boundary if the requested amount of data is zero. - if (data_offset > its_file_data_size) { - psa_status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - } - - if (data_length > (its_file_data_size - data_offset)) { - *p_data_length = its_file_data_size - data_offset; - } else { - *p_data_length = data_length; - } - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // its_file_size includes size of sli_its_encrypted_blob_t struct - blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); - if (blob == NULL) { - psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - memset(blob, 0, its_file_size); - - status = nvm3_readPartialData(nvm3_defaultHandle, - nvm3_object_id, - blob, - its_file_offset, - its_file_size); - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - goto exit; - } - - // Decrypt and authenticate blob - psa_status = sli_decrypt_its_file(&its_file_meta, - blob, - its_file_size, - blob->data, - its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, - &plaintext_length); - - if (psa_status != PSA_SUCCESS) { - goto exit; - } - - if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { - psa_status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - - // Verify that the requested UID is equal to the retrieved and authenticated UID - if (uid != its_file_meta.uid) { - psa_status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if (*p_data_length > 0) { - memcpy(p_data, blob->data + data_offset, *p_data_length); - } - psa_status = PSA_SUCCESS; - - exit: - if (blob != NULL) { - memset(blob, 0, its_file_size); - mbedtls_free(blob); - } - sli_its_release_mutex(); -#else - // If no encryption is used, just read out the data and write it directly to the output buffer - status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); - - if (status != ECODE_NVM3_OK) { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } else { - psa_status = PSA_SUCCESS; - } - - exit: - sli_its_release_mutex(); -#endif - - return psa_status; -} - -/** - * \brief Retrieve the metadata about the provided uid - * - * \param[in] uid The uid value - * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) - * is invalid, for example is `NULL` or references memory the caller cannot access - * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. - */ -psa_status_t psa_its_get_info(psa_storage_uid_t uid, - struct psa_storage_info_t *p_info) -{ - if (p_info == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - nvm3_ObjectKey_t nvm3_object_id; - - sli_its_acquire_mutex(); - psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); - if (psa_status != PSA_SUCCESS) { - sli_its_release_mutex(); - return psa_status; - } - - p_info->flags = its_file_meta.flags; - p_info->size = its_file_size; - -#if defined(SLI_PSA_ITS_ENCRYPTED) - // Remove IV and MAC size from file size - p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; -#endif - sli_its_release_mutex(); - return PSA_SUCCESS; -} - -/** - * \brief Remove the provided key and its associated data from the storage - * - * \param[in] uid The uid value - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - */ -psa_status_t psa_its_remove(psa_storage_uid_t uid) -{ - psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; - Ecode_t status; - sli_its_file_meta_v2_t its_file_meta = { 0 }; - size_t its_file_size = 0; - size_t its_file_offset = 0; - nvm3_ObjectKey_t nvm3_object_id; - - sli_its_acquire_mutex(); - psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); - if (psa_status != PSA_SUCCESS) { - goto exit; - } - if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE -#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) - || (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) -#endif - ) { - psa_status = PSA_ERROR_NOT_PERMITTED; - goto exit; - } - status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); - if (status == ECODE_NVM3_OK) { - // Power-loss might occur, however upon boot, the look-up table will be - // re-filled as long as the data has been successfully written to NVM3. - clear_cache(nvm3_object_id); - set_tomb(nvm3_object_id); - psa_status = PSA_SUCCESS; - } else { - psa_status = PSA_ERROR_STORAGE_FAILURE; - } - - exit: - sli_its_release_mutex(); - return psa_status; -} - -// ------------------------------------- -// Silicon Labs extensions - -static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) -{ -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - /* Encode the owner in the upper 32 bits. This means that if - * owner values are nonzero (as they are on a PSA platform), - * no key file will ever have a value less than 0x100000000, so - * the whole range 0..0xffffffff is available for non-key files. */ - uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); - return ((uint64_t) unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); -#else - /* Use the key id directly as a file name. - * psa_is_key_id_valid() in psa_crypto_slot_management.c - * is responsible for ensuring that key identifiers do not have a - * value that is reserved for non-key files. */ - return key; -#endif -} - -psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, - mbedtls_svc_key_id_t new_id) -{ - psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); - psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); - size_t its_file_size = 0; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - if (old_id == new_id) { - return PSA_SUCCESS; - } - // Check whether the key to migrate exists on disk - struct psa_storage_info_t p_info; - status = psa_its_get_info(old_uid, &p_info); - if (status != PSA_SUCCESS) { - return status; - } - - // Allocate temporary buffer and cast it to the metadata format - uint8_t *its_file_buffer = mbedtls_calloc(1, p_info.size); - if (its_file_buffer == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - // Read contents of pre-existing key into the temporary buffer - status = psa_its_get(old_uid, 0, p_info.size, its_file_buffer, - &its_file_size); - - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_its_set(new_uid, its_file_size, its_file_buffer, - p_info.flags); - - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_its_remove(old_uid); - - if (status != PSA_SUCCESS) { - goto exit; - } - - exit: - // Clear and free key buffer before return. - memset(its_file_buffer, 0, its_file_size); - mbedtls_free(its_file_buffer); - return status; -} - -/** - * \brief Check if the ITS encryption is enabled - */ -psa_status_t sli_psa_its_encrypted(void) -{ -#if defined(SLI_PSA_ITS_ENCRYPTED) - return PSA_SUCCESS; -#else - return PSA_ERROR_NOT_SUPPORTED; -#endif -} - -#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) -/** - * \brief Set the root key to be used when deriving session keys for ITS encryption. - * - * \param[in] root_key Buffer containing the root key. - * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). - * - * \return A status indicating the success/failure of the operation - * - * \retval PSA_SUCCESS The key was successfully set. - * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. - * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. - */ -psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) -{ - // Check that arguments are valid - if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check that the root key has not already been set - // (This is possibly too restrictive. For TrustZone usage this can be enforced by - // not exposing the function to NS instead.) - if (g_root_key.initialized) { - return PSA_ERROR_ALREADY_EXISTS; - } - - // Store the provided root key and mark it as initialized - memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); - g_root_key.initialized = true; - - return PSA_SUCCESS; -} -#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) -#endif // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) -#endif // MBEDTLS_PSA_CRYPTO_STORAGE_C && !MBEDTLS_PSA_ITS_FILE_C +/***************************************************************************//** + * @file + * @brief PSA ITS implementation based on Silicon Labs NVM3 + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +// The psa_driver_wrappers.h file that we're including here assumes that it has +// access to private struct members. Define this here in order to avoid +// compilation errors. +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +// ------------------------------------- +// Includes + +#include + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && !defined(MBEDTLS_PSA_ITS_FILE_C) + +#include "psa/internal_trusted_storage.h" +#include "psa/sli_internal_trusted_storage.h" +#include "nvm3_default.h" +#include "mbedtls/platform.h" +#include +#include + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + #include + #include "psa/storage_common.h" +#endif // TFM_CONFIG_SL_SECURE_LIBRARY + +#if defined(SLI_PSA_ITS_ENCRYPTED) + #include "psa_crypto_core.h" + #include "psa_crypto_driver_wrappers.h" + #if defined(SEMAILBOX_PRESENT) + #include "psa/crypto_extra.h" + #include "sl_psa_values.h" + #include "sli_se_opaque_functions.h" + #endif // defined(SEMAILBOX_PRESENT) +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Threading support + +#if defined(MBEDTLS_THREADING_C) +#include "cmsis_os2.h" +#include "mbedtls/threading.h" + +// Mutex for protecting access to the ITS instance +static mbedtls_threading_mutex_t its_mutex; +static volatile bool its_mutex_inited = false; + +/** + * \brief Lock all task switches + * + * \return Previous lock state + * + */ +static inline int32_t lock_task_switches(void) +{ + int32_t kernel_lock_state = 0; + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + kernel_lock_state = osKernelLock(); + } + return kernel_lock_state; +} + +/** + * \brief Restores the previous lock state + */ +static inline void restore_lock_state(int32_t kernel_lock_state) +{ + osKernelState_t kernel_state = osKernelGetState(); + if (kernel_state != osKernelInactive && kernel_state != osKernelReady) { + if (osKernelRestoreLock(kernel_lock_state) < 0) { + EFM_ASSERT(false); + } + } +} + +#endif // defined(MBEDTLS_THREADING_C) + +/** + * \brief Pend on the ITS mutex + */ +void sli_its_acquire_mutex(void) +{ +#if defined(MBEDTLS_THREADING_C) + if (!its_mutex_inited) { + int32_t kernel_lock_state = lock_task_switches(); + if (!its_mutex_inited) { + mbedtls_mutex_init(&its_mutex); + its_mutex_inited = true; + } + restore_lock_state(kernel_lock_state); + } + if (mbedtls_mutex_lock(&its_mutex) != 0) { + EFM_ASSERT(false); + } +#endif +} + +/** + * \brief Free the ITS mutex. + */ +void sli_its_release_mutex(void) +{ +#if defined(MBEDTLS_THREADING_C) + if (its_mutex_inited) { + mbedtls_mutex_unlock(&its_mutex); + } +#endif +} + +// ------------------------------------- +// Defines + +#if (!SL_PSA_ITS_SUPPORT_V3_DRIVER) +#define SLI_PSA_ITS_NVM3_RANGE_START SLI_PSA_ITS_NVM3_RANGE_BASE +#define SLI_PSA_ITS_NVM3_RANGE_END SLI_PSA_ITS_NVM3_RANGE_START + SL_PSA_ITS_MAX_FILES + +#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) +#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) + +#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE +#error "Trying to store more ITS files then our NVM3 range allows for" +#endif + +#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 + +// Enable backwards-compatibility with keys stored with a v1 header unless disabled. +#if !defined(SL_PSA_ITS_REMOVE_V1_HEADER_SUPPORT) +#define SLI_PSA_ITS_SUPPORT_V1_FORMAT +#endif + +// Internal error codes local to this compile unit +#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) +#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) + +// SLI_STATIC_TESTABLE is used to expose otherwise-static variables during internal testing. +#if !defined(SLI_STATIC_TESTABLE) +#define SLI_STATIC_TESTABLE static +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// Define some cryptographic constants if not already set. This depends on the underlying +// crypto accelerator in use (CRYPTOACC has these defines, but not SEMAILBOX). +#if !defined(AES_MAC_SIZE) +#define AES_MAC_SIZE 16 +#endif + +#if !defined(AES_IV_GCM_SIZE) +#define AES_IV_GCM_SIZE 12 +#endif + +#define SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD (AES_IV_GCM_SIZE + AES_MAC_SIZE) +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local global static variables + +SLI_STATIC_TESTABLE bool nvm3_uid_set_cache_initialized = false; +SLI_STATIC_TESTABLE uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; + +typedef struct { + psa_storage_uid_t uid; + nvm3_ObjectKey_t object_id; + bool set; +} previous_lookup_t; + +static previous_lookup_t previous_lookup = { + 0, 0, false +}; + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// The root key is an AES-256 key, and is therefore 32 bytes. +#define ROOT_KEY_SIZE (32) +// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes +#define SESSION_KEY_SIZE (16) + +#if !defined(SEMAILBOX_PRESENT) +typedef struct { + bool initialized; + uint8_t data[ROOT_KEY_SIZE]; +} root_key_t; + +static root_key_t g_root_key = { + .initialized = false, + .data = { 0 }, +}; +#endif // !defined(SEMAILBOX_PRESENT) + +typedef struct { + bool active; + psa_storage_uid_t uid; + uint8_t data[SESSION_KEY_SIZE]; +} session_key_t; + +static session_key_t g_cached_session_key = { + .active = false, + .uid = 0, + .data = { 0 }, +}; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Structs + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) +typedef struct { + uint32_t magic; + psa_storage_uid_t uid; + psa_storage_create_flags_t flags; +} sl_its_file_meta_v1_t; +#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + +// Due to alignment constraints on the 64-bit UID, the v2 header struct is +// serialized to 16 bytes instead of the 24 bytes the v1 header compiles to. +typedef struct { + uint32_t magic; + psa_storage_create_flags_t flags; + psa_storage_uid_t uid; +} sli_its_file_meta_v2_t; + +#if defined(SLI_PSA_ITS_ENCRYPTED) +typedef struct { + uint8_t iv[AES_IV_GCM_SIZE]; + // When encrypted & authenticated, MAC is stored at the end of the data array + uint8_t data[]; +} sli_its_encrypted_blob_t; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local function prototypes + +static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot); +static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid); + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +static inline bool object_lives_in_s(const void *object, size_t object_size); +#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static psa_status_t derive_session_key(uint8_t *iv, + size_t iv_size, + uint8_t *session_key, + size_t session_key_size); + +static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length); + +static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid); +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Local function definitions + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// If an object of given size is fully encapsulated in a region of +// secure domain the function returns true. +static inline bool object_lives_in_s(const void *object, size_t object_size) +{ + cmse_address_info_t cmse_flags; + + for (size_t i = 0u; i < object_size; i++) { + cmse_flags = cmse_TTA((uint32_t *)object + i); + if (!cmse_flags.flags.secure) { + return false; + } + } + + return true; +} +#endif // defined(TFM_CONFIG_SL_SECURE_LIBRARY) + +static inline void cache_set(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + nvm3_uid_set_cache[bin] |= (1 << offset); +} + +static inline void cache_clear(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + nvm3_uid_set_cache[bin] ^= (1 << offset); +} + +static inline bool cache_lookup(nvm3_ObjectKey_t key) +{ + uint32_t i = key - SLI_PSA_ITS_NVM3_RANGE_START; + uint32_t bin = i / 32; + uint32_t offset = i - 32 * bin; + return (bool)((nvm3_uid_set_cache[bin] >> offset) & 0x1); +} + +static void init_cache(void) +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + + for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; + range_start < SLI_PSA_ITS_NVM3_RANGE_END; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { + nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { + cache_set(keys_referenced_by_nvm3[i]); + } + } + + nvm3_uid_set_cache_initialized = true; +} + +// Read the file metadata for a specific NVM3 ID +static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, + sli_its_file_meta_v2_t* metadata, + size_t* its_file_offset, + size_t* its_file_size) +{ + // Initialize output variables to safe default + if (its_file_offset != NULL) { + *its_file_offset = 0; + } + if (its_file_size != NULL) { + *its_file_size = 0; + } + + Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, + key, + metadata, + 0, + sizeof(sli_its_file_meta_v2_t)); + if (status != ECODE_NVM3_OK) { + return status; + } + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + // Re-read in v1 header format and translate to the latest structure version + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + sl_its_file_meta_v1_t key_meta_v1 = { 0 }; + status = nvm3_readPartialData(nvm3_defaultHandle, + key, + &key_meta_v1, + 0, + sizeof(sl_its_file_meta_v1_t)); + + if (status != ECODE_NVM3_OK) { + return status; + } + + metadata->flags = key_meta_v1.flags; + metadata->uid = key_meta_v1.uid; + metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; + + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sl_its_file_meta_v1_t); + } + + status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; + } else +#endif + { + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sli_its_file_meta_v2_t); + } + } + + if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { + // No valid header found in this object + return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; + } + + if (its_file_offset != NULL && its_file_size != NULL) { + // Calculate the ITS file size if requested + uint32_t obj_type; + Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, + key, + &obj_type, + its_file_size); + if (info_status != ECODE_NVM3_OK) { + return info_status; + } + + *its_file_size = *its_file_size - *its_file_offset; + } + + return status; +} + +// Search through NVM3 for uid +static nvm3_ObjectKey_t get_nvm3_id(psa_storage_uid_t uid, bool find_empty_slot) +{ + Ecode_t status; + sli_its_file_meta_v2_t key_meta; + + if (find_empty_slot) { + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { + if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { + return i + SLI_PSA_ITS_NVM3_RANGE_START; + } + } + } else { + if (previous_lookup.set) { + if (previous_lookup.uid == uid) { + return previous_lookup.object_id; + } + } + + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; i++) { + if (!cache_lookup(i + SLI_PSA_ITS_NVM3_RANGE_START)) { + continue; + } + nvm3_ObjectKey_t object_id = i + SLI_PSA_ITS_NVM3_RANGE_START; + + status = get_file_metadata(object_id, &key_meta, NULL, NULL); + + if (status == ECODE_NVM3_OK + || status == SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + if (key_meta.uid == uid) { + previous_lookup.set = true; + previous_lookup.object_id = object_id; + previous_lookup.uid = uid; + + return object_id; + } else { + continue; + } + } + + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER + || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { + // we don't expect any other data in our range then PSA ITS files. + // delete the file if the magic doesn't match or the object on disk + // is too small to even have full metadata. + status = nvm3_deleteObject(nvm3_defaultHandle, object_id); + if (status != ECODE_NVM3_OK) { + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; + } + } + } + } + + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; +} + +// Perform NVM3 open and fill the look-up table. +// Try to find the mapping NVM3 object ID with PSA ITS UID. +static nvm3_ObjectKey_t prepare_its_get_nvm3_id(psa_storage_uid_t uid) +{ +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that + // it has been opened (which is done on init) rather than actually doing the init. + if (!nvm3_defaultHandle->hasBeenOpened) { +#else + if (nvm3_initDefault() != ECODE_NVM3_OK) { +#endif + return SLI_PSA_ITS_NVM3_RANGE_END + 1U; + } + + if (nvm3_uid_set_cache_initialized == false) { + init_cache(); + } + + return get_nvm3_id(uid, false); +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) +{ + // Cache the session key + memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); + g_cached_session_key.uid = uid; + g_cached_session_key.active = true; +} + +/** + * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. + * + * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. + * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). + * \param[out] session_key Pointer to array where derived session key shall be stored. + * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) +{ + if (iv == NULL + || iv_size != AES_IV_GCM_SIZE + || session_key == NULL + || session_key_size < SESSION_KEY_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(SEMAILBOX_PRESENT) + // For HSE devices, use the builtin TrustZone Root Key + psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); + + psa_key_lifetime_t reported_lifetime; + psa_drv_slot_number_t reported_slot; + status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), + &reported_lifetime, + &reported_slot); + + if (status != PSA_SUCCESS) { + return status; + } + + psa_set_key_lifetime(&attributes, reported_lifetime); + + uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; + size_t key_buffer_size; + status = sli_se_opaque_get_builtin_key(reported_slot, + &attributes, + key_buffer, + sizeof(key_buffer), + &key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } +#else // defined(SEMAILBOX_PRESENT) + // For VSE devices, use the previously initialized root key + if (!g_root_key.initialized) { + return PSA_ERROR_BAD_STATE; + } + + // Prepare root key attributes + psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); + + // Point the key buffer to the global root key + uint8_t *key_buffer = (uint8_t*)g_root_key.data; + size_t key_buffer_size = sizeof(g_root_key.data); +#endif // defined(SEMAILBOX_PRESENT) + + // Use CMAC as a key derivation function + size_t session_key_length; + status = psa_driver_wrapper_mac_compute( + &attributes, + key_buffer, + key_buffer_size, + PSA_ALG_CMAC, + iv, + iv_size, + session_key, + session_key_size, + &session_key_length); + + // Verify that the key derivation was successful before transferring the key to the caller + if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { + memset(session_key, 0, session_key_size); + return PSA_ERROR_HARDWARE_FAILURE; + } + + return status; +} + +/** + * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. + * \param[in] plaintext Pointer to array containing data to be encrypted. + * \param[in] plaintext_size Size of provided plaintext data array. + * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. + * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + * \param[out] blob_length Resulting size of the output blob. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length) +{ + if (metadata == NULL + || (plaintext == NULL && plaintext_size > 0) + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || blob_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Generate IV + size_t iv_length = 0; + psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_IV_GCM_SIZE, &iv_length); + + if (psa_status != PSA_SUCCESS || iv_length != AES_IV_GCM_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Prepare encryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + uint8_t session_key[SESSION_KEY_SIZE]; + psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + cache_session_key(session_key, metadata->uid); + + // Retrieve data to be encrypted + if (plaintext_size != 0U) { + memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); + } + + // Encrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_encrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size, + blob->data, plaintext_size + AES_MAC_SIZE, // output == input for in-place encryption + &output_length); + + // Clear the local session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + if (psa_status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (output_length != plaintext_size + AES_MAC_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *blob_length = output_length + AES_IV_GCM_SIZE; + + return PSA_SUCCESS; +} + +/** + * \brief Decrypt and authenticate encrypted ITS data. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. + * \param[in] blob Encrypted blob containing data to be decrypted. + * \param[in] blob_size Size of the encrypted blob in bytes. + * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. + * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_MAC_SIZE. + * \param[out] plaintext_length Resulting length of the decrypted plaintext. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + if (metadata == NULL + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Prepare decryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t session_key[SESSION_KEY_SIZE]; + + if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { + // Use cached session key if it's already set and UID matches + memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); + } else { + psa_status = derive_session_key(blob->iv, AES_IV_GCM_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + cache_session_key(session_key, metadata->uid); + } + + // Decrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_decrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size + AES_MAC_SIZE, + plaintext, plaintext_size, + &output_length); + + // Clear the session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + // Invalid signature likely means that NVM data was tampered with + if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (psa_status != PSA_SUCCESS + || output_length != plaintext_size) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = output_length; + + return PSA_SUCCESS; +} + +/** + * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. + * + * \details NOTE: This function will run decrypt_its_file() internally. The difference from the decrypt_its_file() + * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the + * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the + * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. + * + * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. + * \param[out] authenticated_uid UID for the authenticated ITS file. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid) +{ + psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t *its_file_meta = NULL; + sli_its_encrypted_blob_t *blob = NULL; + + uint32_t obj_type; + size_t its_file_size = 0; + Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size); + + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Decrypt and authenticate blob + size_t plaintext_length; + ret = decrypt_its_file(its_file_meta, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (ret != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + ret = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (authenticated_uid != NULL) { + *authenticated_uid = its_file_meta->uid; + } + + ret = PSA_SUCCESS; + + cleanup: + + // Discard output, as we're only interested in whether the authentication check passed or not. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + + return ret; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Global function definitions + +/** + * \brief create a new or modify an existing uid/value pair + * + * \param[in] uid the identifier for the data + * \param[in] data_length The size in bytes of the data in `p_data` + * \param[in] p_data A buffer containing the data + * \param[in] create_flags The flags that the data will be stored with + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +psa_status_t psa_its_set(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if (data_length > NVM3_MAX_OBJECT_SIZE) { + return PSA_ERROR_STORAGE_FAILURE; + } + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + Ecode_t status; + psa_status_t ret = PSA_SUCCESS; + sli_its_file_meta_v2_t* its_file_meta; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_storage_uid_t authenticated_uid; + sli_its_encrypted_blob_t *blob = NULL; + size_t blob_length = 0u; + psa_status_t psa_status; + + size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + size_t its_file_size = data_length; +#endif + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + ret = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + // ITS UID was not found. Request a new. + nvm3_object_id = get_nvm3_id(0ULL, true); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + // The storage is full, or an error was returned during cleanup. + ret = PSA_ERROR_INSUFFICIENT_STORAGE; + } else { + its_file_meta->uid = uid; + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; + } + } else { + // ITS UID was found. Read ITS meta data. + status = get_file_metadata(nvm3_object_id, its_file_meta, NULL, NULL); + + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + ret = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + ret = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (ret != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + ret = PSA_ERROR_NOT_PERMITTED; + goto exit; + } +#endif + } + + its_file_meta->flags = create_flags; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Everything after the file metadata will make up the encrypted & authenticated blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Encrypt and authenticate the provided data + psa_status = encrypt_its_file(its_file_meta, + (uint8_t*)p_data, + data_length, + blob, + its_file_size, + &blob_length); + + if (psa_status != PSA_SUCCESS) { + ret = psa_status; + goto exit; + } + + if (blob_length != its_file_size) { + ret = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + +#else + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); + } +#endif + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + cache_set(nvm3_object_id); + } else { + ret = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + if (its_file_buffer != NULL) { + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + } + sli_its_release_mutex(); + return ret; +} + +/** + * \brief Retrieve the value associated with a provided uid + * + * \param[in] uid The uid value + * \param[in] data_offset The starting offset of the data requested + * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) + * \param[out] p_data The buffer where the data will be placed upon successful completion + * \param[out] p_data_length The amount of data returned in the p_data buffer + * + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * is invalid. For example is `NULL` or references memory the caller cannot access. + * In addition, this can also happen if an invalid offset was provided. + */ +psa_status_t psa_its_get(psa_storage_uid_t uid, + uint32_t data_offset, + uint32_t data_length, + void *p_data, + size_t *p_data_length) +{ + psa_status_t ret = PSA_ERROR_CORRUPTION_DETECTED; + + if ((data_length != 0U) && (p_data_length == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (data_length != 0U) { + // If the request amount of data is 0, allow invalid pointer of the output buffer. + if ((p_data == NULL) + || ((uint32_t)p_data < SRAM_BASE) + || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + psa_status_t psa_status; +#endif + size_t its_file_data_size = 0u; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + ret = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + ret = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE + && !object_lives_in_s(p_data, data_length)) { + // The flag indicates that this data should not be read back to the non-secure domain + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if (data_length != 0U) { + if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if ((its_file_data_size == 0U) && (data_offset != 0U)) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } else { + // Allow the offset at the data size boundary if the requested amount of data is zero. + if (data_offset > its_file_data_size) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } + + if (data_length > (its_file_data_size - data_offset)) { + *p_data_length = its_file_data_size - data_offset; + } else { + *p_data_length = data_length; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + ret = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Decrypt and authenticate blob + psa_status = decrypt_its_file(&its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + ret = psa_status; + goto exit; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + ret = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + // Verify that the requested UID is equal to the retrieved and authenticated UID + if (uid != its_file_meta.uid) { + ret = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (*p_data_length > 0) { + memcpy(p_data, blob->data + data_offset, *p_data_length); + } + ret = PSA_SUCCESS; + + exit: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + sli_its_release_mutex(); +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); + + if (status != ECODE_NVM3_OK) { + ret = PSA_ERROR_STORAGE_FAILURE; + } else { + ret = PSA_SUCCESS; + } + + exit: + sli_its_release_mutex(); +#endif + + return ret; +} + +/** + * \brief Retrieve the metadata about the provided uid + * + * \param[in] uid The uid value + * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. + */ +psa_status_t psa_its_get_info(psa_storage_uid_t uid, + struct psa_storage_info_t *p_info) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + if (p_info == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Authenticate the ITS file (both metadata and ciphertext) before returning the metadata. + // Note that this can potentially induce a significant performance hit. + psa_storage_uid_t authenticated_uid; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } +#endif + + p_info->flags = its_file_meta.flags; + p_info->size = its_file_size; + + psa_status = PSA_SUCCESS; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Remove IV and MAC size from file size + p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#endif + exit: + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Remove the provided key and its associated data from the storage + * + * \param[in] uid The uid value + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + */ +psa_status_t psa_its_remove(psa_storage_uid_t uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + + sli_its_acquire_mutex(); + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + status = get_file_metadata(nvm3_object_id, &its_file_meta, &its_file_offset, &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + psa_storage_uid_t authenticated_uid; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (authenticated_uid != uid) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } +#endif + + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + if (previous_lookup.set && previous_lookup.uid == uid) { + previous_lookup.set = false; + } + cache_clear(nvm3_object_id); + + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + sli_its_release_mutex(); + return psa_status; +} + +// ------------------------------------- +// Silicon Labs extensions +static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) +{ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + // Encode the owner in the upper 32 bits. This means that if + // owner values are nonzero (as they are on a PSA platform), + // no key file will ever have a value less than 0x100000000, so + // the whole range 0..0xffffffff is available for non-key files. + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); + return ((uint64_t)unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); +#else + // Use the key id directly as a file name. + // psa_is_key_id_valid() in psa_crypto_slot_management.c + // is responsible for ensuring that key identifiers do not have a + // value that is reserved for non-key files. + return key; +#endif +} + +psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, + mbedtls_svc_key_id_t new_id) +{ + psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); + psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); + Ecode_t status; + uint32_t obj_type; + size_t its_file_size = 0; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + int8_t *its_file_buffer = NULL; + sli_its_file_meta_v2_t* metadata = NULL; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + size_t blob_length; + psa_status_t encrypt_status; + psa_status_t decrypt_status; +#endif + sli_its_acquire_mutex(); + + // Check whether the key to migrate exists on disk + nvm3_ObjectKey_t nvm3_object_id = prepare_its_get_nvm3_id(old_uid); + if (nvm3_object_id > SLI_PSA_ITS_NVM3_RANGE_END) { + psa_status = PSA_ERROR_DOES_NOT_EXIST; + goto exit; + } + + // Get total length to allocate + status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Allocate temporary buffer and cast it to the metadata format + its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + metadata = (sli_its_file_meta_v2_t*) its_file_buffer; + + // Read contents of pre-existing key into the temporary buffer + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Decrypt and authenticate blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + decrypt_status = decrypt_its_file(metadata, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (decrypt_status != PSA_SUCCESS) { + psa_status = decrypt_status; + goto exit; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } +#endif + + // Swap out the old UID for the new one +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT) + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + // Recast as v1 metadata + sl_its_file_meta_v1_t* metadata_v1 = (sl_its_file_meta_v1_t*) its_file_buffer; + if (metadata_v1->uid != old_uid) { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + metadata_v1->uid = new_uid; + } else +#endif + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V2) { + if (metadata->uid != old_uid) { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + metadata->uid = new_uid; + } else { + psa_status = PSA_ERROR_CORRUPTION_DETECTED; + goto exit; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Encrypt and authenticate the modified data data + encrypt_status = encrypt_its_file(metadata, + blob->data, + plaintext_length, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + &blob_length); + + if (encrypt_status != PSA_SUCCESS) { + psa_status = encrypt_status; + goto exit; + } + + if (blob_length != (its_file_size - sizeof(sli_its_file_meta_v2_t))) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } +#endif + + // Overwrite the NVM3 token with the changed buffer + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status == ECODE_NVM3_OK) { + // Update last lookup and report success + if (previous_lookup.set) { + if (previous_lookup.uid == old_uid) { + previous_lookup.uid = new_uid; + } + } + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + if (its_file_buffer != NULL) { + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + } + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Check if the ITS encryption is enabled + */ +psa_status_t sli_psa_its_encrypted(void) +{ + #if defined(SLI_PSA_ITS_ENCRYPTED) + return PSA_SUCCESS; + #else + return PSA_ERROR_NOT_SUPPORTED; + #endif +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +/** + * \brief Set the root key to be used when deriving session keys for ITS encryption. + * + * \param[in] root_key Buffer containing the root key. + * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The key was successfully set. + * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. + * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. + */ +psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) +{ + // Check that arguments are valid + if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check that the root key has not already been set + // (This is possibly too restrictive. For TrustZone usage this can be enforced by + // not exposing the function to NS instead.) + if (g_root_key.initialized) { + return PSA_ERROR_ALREADY_EXISTS; + } + + // Store the provided root key and mark it as initialized + memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); + g_root_key.initialized = true; + + return PSA_SUCCESS; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) + +#else // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) + +// ------------------------------------- +// Defines +#define SLI_PSA_ITS_V3_DRIVER (0x3A) +#define SLI_PSA_ITS_V2_DRIVER (0x74) +#define SLI_PSA_ITS_NOT_CHECKED (0xE8) +#define SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID (SLI_PSA_ITS_NVM3_RANGE_START - 1) +#define SLI_PSA_ITS_NVM3_INVALID_KEY (0) +#define SLI_PSA_ITS_NVM3_UNKNOWN_KEY (1) + +#if SL_PSA_ITS_MAX_FILES > SLI_PSA_ITS_NVM3_RANGE_SIZE +#error "Trying to store more ITS files then our NVM3 range allows for" +#endif + +#define SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE 16 + +// Internal error codes local to this compile unit +#define SLI_PSA_ITS_ECODE_NO_VALID_HEADER (ECODE_EMDRV_NVM3_BASE - 1) +#define SLI_PSA_ITS_ECODE_NEEDS_UPGRADE (ECODE_EMDRV_NVM3_BASE - 2) + +// SLI_STATIC_TESTABLE is used to expose otherwise-static variables during internal testing. +#if !defined(SLI_STATIC_TESTABLE) +#define SLI_STATIC_TESTABLE static +#endif + +// ------------------------------------- +// Local global static variables + +SLI_STATIC_TESTABLE bool nvm3_uid_set_cache_initialized = false; +SLI_STATIC_TESTABLE uint32_t nvm3_uid_set_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; +SLI_STATIC_TESTABLE uint32_t nvm3_uid_tomb_cache[(SL_PSA_ITS_MAX_FILES + 31) / 32] = { 0 }; +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +SLI_STATIC_TESTABLE uint32_t its_driver_version = SLI_PSA_ITS_NOT_CHECKED; +#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER + +#if defined(SLI_PSA_ITS_ENCRYPTED) +// The root key is an AES-256 key, and is therefore 32 bytes. +#define ROOT_KEY_SIZE (32) +// The session key is derived from CMAC, which means it is equal to the AES block size, i.e. 16 bytes +#define SESSION_KEY_SIZE (16) + +#if !defined(SEMAILBOX_PRESENT) +typedef struct { + bool initialized; + uint8_t data[ROOT_KEY_SIZE]; +} root_key_t; + +static root_key_t g_root_key = { + .initialized = false, + .data = { 0 }, +}; +#endif // !defined(SEMAILBOX_PRESENT) + +typedef struct { + bool active; + psa_storage_uid_t uid; + uint8_t data[SESSION_KEY_SIZE]; +} session_key_t; + +static session_key_t g_cached_session_key = { + .active = false, + .uid = 0, + .data = { 0 }, +}; +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Structs + +#if defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +typedef struct { + uint32_t magic; + psa_storage_uid_t uid; + psa_storage_create_flags_t flags; +} sl_its_file_meta_v1_t; +#endif // defined(SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + +// ------------------------------------- +// Local function prototypes + +static psa_status_t find_nvm3_id(psa_storage_uid_t uid, + bool find_empty_slot, + sli_its_file_meta_v2_t* its_file_meta, + size_t* its_file_offset, + size_t* its_file_size, + nvm3_ObjectKey_t * output_nvm3_id); +static nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid); + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +static inline bool object_lives_in_s(const void *object, size_t object_size); +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static psa_status_t derive_session_key(uint8_t *iv, + size_t iv_size, + uint8_t *session_key, + size_t session_key_size); + +static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid); +#endif + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, + sli_its_file_meta_v2_t* its_file_meta, + size_t its_file_size, + size_t its_file_offset, void *p_data); +static psa_status_t detect_legacy_versions(); +static psa_status_t upgrade_all_keys(); + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +psa_status_t psa_its_set_v1(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags); +#endif // SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL +#endif // SL_PSA_ITS_SUPPORT_V2_DRIVER + +// ------------------------------------- +// Local function definitions +static inline uint32_t get_index(nvm3_ObjectKey_t key) +{ + return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) / 32; +} + +static inline uint32_t get_offset(nvm3_ObjectKey_t key) +{ + return (key - (SLI_PSA_ITS_NVM3_RANGE_START)) % 32; +} + +static inline void set_cache(nvm3_ObjectKey_t key) +{ + nvm3_uid_set_cache[get_index(key)] |= (1 << get_offset(key)); + nvm3_uid_tomb_cache[get_index(key)] &= ~(1 << get_offset(key)); +} + +static inline void set_tomb(nvm3_ObjectKey_t key) +{ + nvm3_uid_tomb_cache[get_index(key)] |= (1 << get_offset(key)); + + uint32_t cache_not_empty = 0; + for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { + cache_not_empty += nvm3_uid_set_cache[i]; + } + if (cache_not_empty == 0) { + for ( size_t i = 0; i < (((SL_PSA_ITS_MAX_FILES) +31) / 32); i++ ) { + nvm3_uid_tomb_cache[i] = 0; + } + } +} + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static inline psa_status_t write_driver_v3() +{ + uint8_t driver_verison = SLI_PSA_ITS_V3_DRIVER; + Ecode_t status; + status = nvm3_writeData(nvm3_defaultHandle, + SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, + &driver_verison, sizeof(uint8_t)); + if ( status != ECODE_NVM3_OK ) { + return PSA_ERROR_STORAGE_FAILURE; + } + return PSA_SUCCESS; +} +#endif + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) +// If an object of given size is fully encapsulated in a region of +// secure domain the function returns true. +static inline bool object_lives_in_s(const void *object, size_t object_size) +{ + cmse_address_info_t cmse_flags; + + for (size_t i = 0u; i < object_size; i++) { + cmse_flags = cmse_TTA((uint32_t *)object + i); + if (!cmse_flags.flags.secure) { + return false; + } + } + + return true; +} +#endif + +static inline void clear_cache(nvm3_ObjectKey_t key) +{ + nvm3_uid_set_cache[get_index(key)] ^= (1 << get_offset(key)); +} + +static inline bool lookup_cache(nvm3_ObjectKey_t key) +{ + return (bool)((nvm3_uid_set_cache[get_index(key)] >> get_offset(key)) & 0x1); +} + +static inline bool lookup_tomb(nvm3_ObjectKey_t key) +{ + return (bool)((nvm3_uid_tomb_cache[get_index(key)] >> get_offset(key)) & 0x1); +} + +static inline nvm3_ObjectKey_t increment_obj_id(nvm3_ObjectKey_t id) +{ + return SLI_PSA_ITS_NVM3_RANGE_START + ((id - SLI_PSA_ITS_NVM3_RANGE_START + 1) + % SL_PSA_ITS_MAX_FILES); +} +static inline nvm3_ObjectKey_t prng(psa_storage_uid_t uid) +{ +// Squash uid down to a 32 bit word + nvm3_ObjectKey_t uid_32 = uid & 0xFFFFFFFF; + nvm3_ObjectKey_t xored_32 = (uid >> 32) ^ uid_32; + nvm3_ObjectKey_t temp; +// Accumulate all "entropy" towards the LSB, since that is where we need it + for ( size_t i = 1; i < 4; i++ ) { + temp = xored_32 ^ (xored_32 >> (8 * i)); + if ((temp & 0x3) != 0 ) { + temp = temp << 2; + } + uid_32 = (uid_32 + temp); + } + return uid_32; +} + +static inline nvm3_ObjectKey_t derive_nvm3_id(psa_storage_uid_t uid) +{ + return SLI_PSA_ITS_NVM3_RANGE_START + (prng(uid) % (SL_PSA_ITS_MAX_FILES)); +} + +static void init_cache(void) +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + size_t num_del_keys_from_nvm3; + nvm3_ObjectKey_t deleted_keys_from_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { 0 }; + for (nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START; + range_start < SLI_PSA_ITS_NVM3_RANGE_END; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE) { + nvm3_ObjectKey_t range_end = range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + for (size_t i = 0; i < num_keys_referenced_by_nvm3; i++) { + set_cache(keys_referenced_by_nvm3[i]); + } + num_del_keys_from_nvm3 = nvm3_enumDeletedObjects(nvm3_defaultHandle, + deleted_keys_from_nvm3, + sizeof(deleted_keys_from_nvm3) / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + for (size_t i = 0; i < num_del_keys_from_nvm3; i++) { + set_tomb(deleted_keys_from_nvm3[i]); + } + } + nvm3_uid_set_cache_initialized = true; +} + +// Read the file metadata for a specific NVM3 ID +static Ecode_t get_file_metadata(nvm3_ObjectKey_t key, + sli_its_file_meta_v2_t* metadata, + size_t* its_file_offset, + size_t* its_file_size) +{ + // Initialize output variables to safe default + if (its_file_offset != NULL) { + *its_file_offset = 0; + } + if (its_file_size != NULL) { + *its_file_size = 0; + } + + Ecode_t status = nvm3_readPartialData(nvm3_defaultHandle, + key, + metadata, + 0, + sizeof(sli_its_file_meta_v2_t)); + if (status != ECODE_NVM3_OK) { + return status; + } + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + // Re-read in v1 header format and translate to the latest structure version + if (metadata->magic == SLI_PSA_ITS_META_MAGIC_V1) { + sl_its_file_meta_v1_t key_meta_v1 = { 0 }; + status = nvm3_readPartialData(nvm3_defaultHandle, + key, + &key_meta_v1, + 0, + sizeof(sl_its_file_meta_v1_t)); + + if (status != ECODE_NVM3_OK) { + return status; + } + + metadata->flags = key_meta_v1.flags; + metadata->uid = key_meta_v1.uid; + metadata->magic = SLI_PSA_ITS_META_MAGIC_V2; + + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sl_its_file_meta_v1_t); + } + + status = SLI_PSA_ITS_ECODE_NEEDS_UPGRADE; + } else +#endif + { + if (its_file_offset != NULL) { + *its_file_offset = sizeof(sli_its_file_meta_v2_t); + } + } + + if (metadata->magic != SLI_PSA_ITS_META_MAGIC_V2) { + // No valid header found in this object + return SLI_PSA_ITS_ECODE_NO_VALID_HEADER; + } + + if (its_file_offset != NULL && its_file_size != NULL) { + // Calculate the ITS file size if requested + uint32_t obj_type; + Ecode_t info_status = nvm3_getObjectInfo(nvm3_defaultHandle, + key, + &obj_type, + its_file_size); + if (info_status != ECODE_NVM3_OK) { + return info_status; + } + + *its_file_size = *its_file_size - *its_file_offset; + } + + return status; +} + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER +static psa_status_t psa_its_get_legacy(nvm3_ObjectKey_t nvm3_object_id, + sli_its_file_meta_v2_t* its_file_meta, + size_t its_file_size, + size_t its_file_offset, + void *p_data) +{ + Ecode_t status; + if (its_file_size == 0) { + if (its_file_meta != NULL) { + return PSA_ERROR_DATA_INVALID; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_encrypted_blob_t *blob = NULL; + size_t plaintext_length; + + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + // Decrypt and authenticate blob + psa_status = sli_decrypt_its_file(its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (its_file_size + its_file_offset > 0) { + memcpy(p_data, blob->data, its_file_size + its_file_offset); + } + psa_status = PSA_SUCCESS; + + cleanup: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + return psa_status; +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, + its_file_offset, its_file_size); + + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } else { + return PSA_SUCCESS; + } +#endif +} + +// Function sets detect the presence of v1 and v2 its driver. If there is something +// stored in v1/v2 driver range, it sets its_driver_version to SLI_PSA_ITS_V2_DRIVER. +static psa_status_t detect_legacy_versions() +{ + uint8_t driver_verison = 0; + Ecode_t status; + status = nvm3_readData(nvm3_defaultHandle, SLI_PSA_ITS_V2_DRIVER_FLAG_NVM3_ID, + &driver_verison, sizeof(uint8_t)); + if ((status != ECODE_NVM3_OK) && (status != ECODE_NVM3_ERR_KEY_NOT_FOUND)) { + return PSA_ERROR_STORAGE_FAILURE; + } + if (driver_verison == SLI_PSA_ITS_V3_DRIVER) { + its_driver_version = SLI_PSA_ITS_V3_DRIVER; + return PSA_SUCCESS; + } + + size_t num_keys_referenced_by_nvm3; + + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { + 0 + }; + + for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; + range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { + nvm3_ObjectKey_t range_end = + range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end > SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) + / sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + + if (num_keys_referenced_by_nvm3 > 0) { + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + status = get_file_metadata(keys_referenced_by_nvm3[0], + &its_file_meta, &its_file_offset, + &its_file_size); + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + return PSA_ERROR_DOES_NOT_EXIST; + } + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if ((its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) + || (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2)) { + its_driver_version = SLI_PSA_ITS_V2_DRIVER; + return PSA_SUCCESS; + } else { + return PSA_ERROR_STORAGE_FAILURE; + } + } + } + its_driver_version = SLI_PSA_ITS_V3_DRIVER; + return PSA_SUCCESS; +} + +static psa_status_t upgrade_all_keys() +{ + size_t num_keys_referenced_by_nvm3; + nvm3_ObjectKey_t keys_referenced_by_nvm3[SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE] = { + 0 + }; + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_data_size; + uint8_t * its_file_buffer = NULL; + + size_t its_file_size = 0; + size_t its_file_offset; + + for ( nvm3_ObjectKey_t range_start = SLI_PSA_ITS_NVM3_RANGE_START_V2_DRIVER; + range_start < SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + range_start += SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE ) { + nvm3_ObjectKey_t range_end = + range_start + SLI_PSA_ITS_CACHE_INIT_CHUNK_SIZE; + if (range_end >= SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER ) { + range_end = SLI_PSA_ITS_NVM3_RANGE_END_V2_DRIVER; + } + + num_keys_referenced_by_nvm3 = nvm3_enumObjects(nvm3_defaultHandle, + keys_referenced_by_nvm3, + sizeof(keys_referenced_by_nvm3) + / + sizeof(nvm3_ObjectKey_t), + range_start, + range_end - 1); + for ( size_t i = 0; i < num_keys_referenced_by_nvm3; i++ ) { + its_file_size = 0; + its_file_offset = 0; + status = get_file_metadata(keys_referenced_by_nvm3[i], + &(its_file_meta), &its_file_offset, + &its_file_size); + if ( status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER) { + return PSA_ERROR_DOES_NOT_EXIST; + } + if ( status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if ((its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V2) + && (its_file_meta.magic != SLI_PSA_ITS_META_MAGIC_V1)) { + return PSA_ERROR_STORAGE_FAILURE; + } + its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } +#if defined(SLI_PSA_ITS_ENCRYPTED) + psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], + &(its_file_meta), + its_file_size, + its_file_offset, + its_file_buffer); +#else + psa_status = psa_its_get_legacy(keys_referenced_by_nvm3[i], + NULL, + its_file_size, + its_file_offset, + its_file_buffer); +#endif + if (psa_status != PSA_SUCCESS) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) + if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V1) { + psa_status = psa_its_set_v1(its_file_meta.uid, its_file_data_size, + its_file_buffer, its_file_meta.flags); + } else if (its_file_meta.magic == SLI_PSA_ITS_META_MAGIC_V2) +#endif + { + psa_status = psa_its_set(its_file_meta.uid, its_file_data_size, + its_file_buffer, its_file_meta.flags); + } + + if ((psa_status != PSA_SUCCESS) && (psa_status + != PSA_ERROR_NOT_PERMITTED)) { + goto exit; + } + status = nvm3_deleteObject(nvm3_defaultHandle, + keys_referenced_by_nvm3[i]); + + if ( status != ECODE_NVM3_OK ) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + } + } + return PSA_SUCCESS; + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + return psa_status; +} + +#if defined (SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL) +psa_status_t psa_its_set_v1(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sl_its_file_meta_v1_t* its_file_meta; + nvm3_ObjectKey_t nvm3_object_id = 0; + size_t its_file_size = data_length; + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sl_its_file_meta_v1_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); + + its_file_meta = (sl_its_file_meta_v1_t *)its_file_buffer; + sli_its_file_meta_v2_t its_file_meta_v2; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, true, &its_file_meta_v2, NULL, NULL, + &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { + psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; + } + goto exit; + } + + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V1; + its_file_meta->uid = uid; + its_file_meta->flags = create_flags; + + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sl_its_file_meta_v1_t), ((uint8_t*) + p_data), data_length); + } + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof + (sl_its_file_meta_v1_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + set_cache(nvm3_object_id); + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sl_its_file_meta_v1_t)); + mbedtls_free(its_file_buffer); + sli_its_release_mutex(); + return psa_status; +} +#endif //SLI_PSA_ITS_SUPPORT_V1_FORMAT_INTERNAL +#endif //SL_PSA_ITS_SUPPORT_V1_DRIVER + +/** + * \brief Search through NVM3 for correct uid + * + * \param[in] uid UID under what we want to store the data + * \param[in] find_empty_slot Indicates whether we want to find existing data or empty space for storing new. + * \param[out] its_file_meta Meta information of ITS file + * \param[out] its_file_offset Offset of ITS file + * \param[out] its_file_size Size of ITS file + * \param[out] output_nvm3_id NVM3 ID corresponding to UID. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The data with this UID are not stored in NVM3 + * \retval PSA_ERROR_NOT_PERMITTED The requested operation is not permitted + */ +static psa_status_t find_nvm3_id(psa_storage_uid_t uid, + bool find_empty_slot, + sli_its_file_meta_v2_t* its_file_meta, + size_t* its_file_offset, + size_t* its_file_size, + nvm3_ObjectKey_t * output_nvm3_id) +{ + Ecode_t status; + nvm3_ObjectKey_t tmp_id = 0; + nvm3_ObjectKey_t nvm3_object_id = 0; + nvm3_object_id = derive_nvm3_id(uid); + + if (nvm3_uid_set_cache_initialized == false) { +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) \ + // With SKL the NVM3 instance must be initialized by the NS app. We therefore check that + // it has been opened (which is done on init) rather than actually doing the init. + if (!nvm3_defaultHandle->hasBeenOpened) { +#else + if (nvm3_initDefault() != ECODE_NVM3_OK) { +#endif + return PSA_ERROR_STORAGE_FAILURE; + } + +#if SL_PSA_ITS_SUPPORT_V2_DRIVER + if ( its_driver_version == SLI_PSA_ITS_NOT_CHECKED ) { + if ( detect_legacy_versions() != PSA_SUCCESS ) { + return PSA_ERROR_STORAGE_FAILURE; + } + if ( its_driver_version == SLI_PSA_ITS_V2_DRIVER ) { + psa_status_t psa_status = upgrade_all_keys(); + if ( psa_status != PSA_SUCCESS ) { + return psa_status; + } + psa_status = write_driver_v3(); + if ( psa_status != PSA_SUCCESS ) { + return psa_status; + } + } else { + init_cache(); + } + } else { + init_cache(); + } +#else + init_cache(); +#endif + } + + for (size_t i = 0; i < SL_PSA_ITS_MAX_FILES; ++i ) { + if (!lookup_cache(nvm3_object_id)) { + // dont exist + if (lookup_tomb(nvm3_object_id)) { + // tombstone + if (tmp_id == 0 ) { + // mark first empty space + tmp_id = nvm3_object_id; + } + nvm3_object_id = increment_obj_id(nvm3_object_id); + continue; + } else { + // empty space + if (find_empty_slot) { + if (tmp_id != 0) { + *output_nvm3_id = tmp_id; + return PSA_SUCCESS; + } + *output_nvm3_id = nvm3_object_id; + return PSA_SUCCESS; + } else { + return PSA_ERROR_DOES_NOT_EXIST; + } + } + } + status = get_file_metadata(nvm3_object_id, its_file_meta, its_file_offset, + its_file_size); + + if (status == SLI_PSA_ITS_ECODE_NO_VALID_HEADER + || status == ECODE_NVM3_ERR_READ_DATA_SIZE) { + // we don't expect any other data in our range then PSA ITS files. + // delete the file if the magic doesn't match or the object on disk + // is too small to even have full metadata. + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_DOES_NOT_EXIST; + } + } + + if (status != ECODE_NVM3_OK + && status != SLI_PSA_ITS_ECODE_NEEDS_UPGRADE) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if (its_file_meta->uid != uid) { + nvm3_object_id = increment_obj_id(nvm3_object_id); + } else { + if (find_empty_slot) { + if (its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || its_file_meta->flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_PERMITTED; + } + } +#if defined(SLI_PSA_ITS_ENCRYPTED) + // If the UID already exists, authenticate the existing value and make sure the stored UID is the same. + // Note that this can potentially induce a significant performance hit. + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_storage_uid_t authenticated_uid = 0; + psa_status = authenticate_its_file(nvm3_object_id, &authenticated_uid); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + if (authenticated_uid != uid) { + return PSA_ERROR_INVALID_SIGNATURE; + } +#endif + *output_nvm3_id = nvm3_object_id; + return PSA_SUCCESS; + } + } + if (find_empty_slot) { + if (tmp_id != 0) { + *output_nvm3_id = tmp_id; + return PSA_SUCCESS; + } + } + return PSA_ERROR_DOES_NOT_EXIST; +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) +static inline void cache_session_key(uint8_t *session_key, psa_storage_uid_t uid) +{ + // Cache the session key + memcpy(g_cached_session_key.data, session_key, sizeof(g_cached_session_key.data)); + g_cached_session_key.uid = uid; + g_cached_session_key.active = true; +} + +/** + * \brief Derive a session key for ITS file encryption from the initialized root key and provided IV. + * + * \param[in] iv Pointer to array containing the initialization vector to be used in the key derivation. + * \param[in] iv_size Size of the IV buffer in bytes. Must be 12 bytes (AES-GCM IV size). + * \param[out] session_key Pointer to array where derived session key shall be stored. + * \param[out] session_key_size Size of the derived session key output array. Must be at least 32 bytes (AES-256 key size). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because iv or session_key is NULL, or their sizes are incorrect. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t derive_session_key(uint8_t *iv, size_t iv_size, uint8_t *session_key, size_t session_key_size) +{ + if (iv == NULL + || iv_size != AES_GCM_IV_SIZE + || session_key == NULL + || session_key_size < SESSION_KEY_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(SEMAILBOX_PRESENT) + // For HSE devices, use the builtin TrustZone Root Key + psa_set_key_id(&attributes, SL_SE_BUILTIN_KEY_TRUSTZONE_ID); + + psa_key_lifetime_t reported_lifetime; + psa_drv_slot_number_t reported_slot; + status = mbedtls_psa_platform_get_builtin_key(psa_get_key_id(&attributes), + &reported_lifetime, + &reported_slot); + + if (status != PSA_SUCCESS) { + return status; + } + + psa_set_key_lifetime(&attributes, reported_lifetime); + + uint8_t key_buffer[sizeof(sli_se_opaque_key_context_header_t)]; + size_t key_buffer_size; + status = sli_se_opaque_get_builtin_key(reported_slot, + &attributes, + key_buffer, + sizeof(key_buffer), + &key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } +#else // defined(SEMAILBOX_PRESENT) + // For VSE devices, use the previously initialized root key + if (!g_root_key.initialized) { + return PSA_ERROR_BAD_STATE; + } + + // Prepare root key attributes + psa_set_key_algorithm(&attributes, PSA_ALG_CMAC); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, ROOT_KEY_SIZE * 8); + + // Point the key buffer to the global root key + uint8_t *key_buffer = (uint8_t*)g_root_key.data; + size_t key_buffer_size = sizeof(g_root_key.data); +#endif // defined(SEMAILBOX_PRESENT) + + // Use CMAC as a key derivation function + size_t session_key_length; + status = psa_driver_wrapper_mac_compute( + &attributes, + key_buffer, + key_buffer_size, + PSA_ALG_CMAC, + iv, + iv_size, + session_key, + session_key_size, + &session_key_length); + + // Verify that the key derivation was successful before transferring the key to the caller + if (status != PSA_SUCCESS || session_key_length != SESSION_KEY_SIZE) { + memset(session_key, 0, session_key_size); + return PSA_ERROR_HARDWARE_FAILURE; + } + + return status; +} + +/** + * \brief Encrypt and authenticate ITS data with AES-128-GCM, storing the result in an encrypted blob. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. + * \param[in] plaintext Pointer to array containing data to be encrypted. + * \param[in] plaintext_size Size of provided plaintext data array. + * \param[out] blob Pointer to array where the resulting encrypted blob shall be placed. + * \param[in] blob_size Size of the output array. Must be at least as big as plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + * \param[out] blob_length Resulting size of the output blob. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +psa_status_t sli_encrypt_its_file(sli_its_file_meta_v2_t *metadata, + uint8_t *plaintext, + size_t plaintext_size, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + size_t *blob_length) +{ + if (metadata == NULL + || (plaintext == NULL && plaintext_size > 0) + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || blob_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Generate IV + size_t iv_length = 0; + psa_status_t psa_status = mbedtls_psa_external_get_random(NULL, blob->iv, AES_GCM_IV_SIZE, &iv_length); + + if (psa_status != PSA_SUCCESS || iv_length != AES_GCM_IV_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Prepare encryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_ENCRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + uint8_t session_key[SESSION_KEY_SIZE]; + psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + + cache_session_key(session_key, metadata->uid); + + // Retrieve data to be encrypted + if (plaintext_size != 0U) { + memcpy(blob->data, ((uint8_t*)plaintext), plaintext_size); + } + + // Encrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_encrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size, + blob->data, plaintext_size + AES_GCM_MAC_SIZE, // output == input for in-place encryption + &output_length); + + // Clear the local session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + if (psa_status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (output_length != plaintext_size + AES_GCM_MAC_SIZE) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *blob_length = output_length + AES_GCM_IV_SIZE; + + return PSA_SUCCESS; +} + +/** + * \brief Decrypt and authenticate encrypted ITS data. + * + * \param[in] metadata ITS metadata to be used as authenticated additional data. Must be identical to the metadata used during encryption. + * \param[in] blob Encrypted blob containing data to be decrypted. + * \param[in] blob_size Size of the encrypted blob in bytes. + * \param[out] plaintext Pointer to array where the decrypted plaintext shall be placed. + * \param[in] plaintext_size Size of the plaintext array. Must be equal to sizeof(blob->data) - AES_GCM_MAC_SIZE. + * \param[out] plaintext_length Resulting length of the decrypted plaintext. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t sli_decrypt_its_file(sli_its_file_meta_v2_t *metadata, + sli_its_encrypted_blob_t *blob, + size_t blob_size, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + if (metadata == NULL + || blob == NULL + || blob_size < plaintext_size + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Prepare decryption key + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(&attributes, PSA_ALG_GCM); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, SESSION_KEY_SIZE * 8); + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t session_key[SESSION_KEY_SIZE]; + + if (g_cached_session_key.active && g_cached_session_key.uid == metadata->uid) { + // Use cached session key if it's already set and UID matches + memcpy(session_key, g_cached_session_key.data, sizeof(session_key)); + } else { + psa_status = derive_session_key(blob->iv, AES_GCM_IV_SIZE, session_key, sizeof(session_key)); + if (psa_status != PSA_SUCCESS) { + return psa_status; + } + cache_session_key(session_key, metadata->uid); + } + + // Decrypt and authenticate blob + size_t output_length = 0; + psa_status = psa_driver_wrapper_aead_decrypt( + &attributes, + session_key, sizeof(session_key), + PSA_ALG_GCM, + blob->iv, sizeof(blob->iv), + (uint8_t*)metadata, sizeof(sli_its_file_meta_v2_t), // metadata is AAD + blob->data, plaintext_size + AES_GCM_MAC_SIZE, + plaintext, plaintext_size, + &output_length); + + // Clear the session key immediately after we're done using it + memset(session_key, 0, sizeof(session_key)); + + // Invalid signature likely means that NVM data was tampered with + if (psa_status == PSA_ERROR_INVALID_SIGNATURE) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (psa_status != PSA_SUCCESS + || output_length != plaintext_size) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = output_length; + + return PSA_SUCCESS; +} + +/** + * \brief Authenticate encrypted ITS data and return the UID of the ITS file that was authenticated. + * + * \details NOTE: This function will run sli_decrypt_its_file() internally. The difference from the sli_decrypt_its_file() + * function is that authenticate_its_file() reads the NVM3 data, decrypts it in order to authenticate the + * stored data, and then discards the plaintext. This is needed since PSA Crypto doesn't support the + * GMAC primitive directly, which means we have to run a full GCM decrypt for authentication. + * + * \param[in] nvm3_object_id The NVM3 id corresponding to the stored ITS file. + * \param[out] authenticated_uid UID for the authenticated ITS file. + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the decrypted data failed. + * \retval PSA_ERROR_BAD_STATE The root key has not been initialized. + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one or more arguments are NULL or of invalid size. + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + */ +static psa_status_t authenticate_its_file(nvm3_ObjectKey_t nvm3_object_id, + psa_storage_uid_t *authenticated_uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t *its_file_meta = NULL; + sli_its_encrypted_blob_t *blob = NULL; + + uint32_t obj_type; + size_t its_file_size = 0; + Ecode_t status = nvm3_getObjectInfo(nvm3_defaultHandle, + nvm3_object_id, + &obj_type, + &its_file_size); + if (status != ECODE_NVM3_OK) { + return PSA_ERROR_STORAGE_FAILURE; + } + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size); + + status = nvm3_readData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto cleanup; + } + + its_file_meta = (sli_its_file_meta_v2_t*)its_file_buffer; + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Decrypt and authenticate blob + size_t plaintext_length; + psa_status = sli_decrypt_its_file(its_file_meta, + blob, + its_file_size - sizeof(sli_its_file_meta_v2_t), + blob->data, + its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto cleanup; + } + + if (plaintext_length != (its_file_size - sizeof(sli_its_file_meta_v2_t) - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + if (authenticated_uid != NULL) { + *authenticated_uid = its_file_meta->uid; + } + + psa_status = PSA_SUCCESS; + + cleanup: + + // Discard output, as we're only interested in whether the authentication check passed or not. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + + return psa_status; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) + +// ------------------------------------- +// Global function definitions + +/** + * \brief create a new or modify an existing uid/value pair + * + * \param[in] uid the identifier for the data + * \param[in] data_length The size in bytes of the data in `p_data` + * \param[in] p_data A buffer containing the data + * \param[in] create_flags The flags that the data will be stored with + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_HARDWARE_FAILURE The operation failed because an internal cryptographic operation failed. + * \retval PSA_ERROR_INVALID_SIGNATURE The operation failed because the provided `uid` doesnt match the autenticated uid from the storage + */ +psa_status_t psa_its_set(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags) +{ + if ((data_length != 0U) && (p_data == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if ((data_length > NVM3_MAX_OBJECT_SIZE)) { + return PSA_ERROR_STORAGE_FAILURE; + } + + if (create_flags != PSA_STORAGE_FLAG_WRITE_ONCE + && create_flags != PSA_STORAGE_FLAG_NONE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + && create_flags != PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE +#endif + ) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if ((create_flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) + && (!object_lives_in_s(p_data, data_length))) { + // The flag indicates that this data should not be set by the non-secure domain + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + + Ecode_t status; + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t* its_file_meta; + nvm3_ObjectKey_t nvm3_object_id = 0; +#if defined(SLI_PSA_ITS_ENCRYPTED) + sli_its_encrypted_blob_t *blob = NULL; + size_t its_file_size = data_length + SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; + size_t blob_length = 0u; +#else + size_t its_file_size = data_length; +#endif + + uint8_t *its_file_buffer = mbedtls_calloc(1, its_file_size + sizeof(sli_its_file_meta_v2_t)); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + its_file_meta = (sli_its_file_meta_v2_t *)its_file_buffer; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, true, its_file_meta, NULL, NULL, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + if (psa_status == PSA_ERROR_DOES_NOT_EXIST) { + psa_status = PSA_ERROR_INSUFFICIENT_STORAGE; + } + goto exit; + } + + its_file_meta->magic = SLI_PSA_ITS_META_MAGIC_V2; + its_file_meta->uid = uid; + its_file_meta->flags = create_flags; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Everything after the the file metadata will make up the encrypted & authenticated blob + blob = (sli_its_encrypted_blob_t*)(its_file_buffer + sizeof(sli_its_file_meta_v2_t)); + + // Encrypt and authenticate the provided data + psa_status = sli_encrypt_its_file(its_file_meta, + (uint8_t*)p_data, + data_length, + blob, + its_file_size, + &blob_length); + + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (blob_length != its_file_size) { + psa_status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + +#else + if (data_length != 0U) { + memcpy(its_file_buffer + sizeof(sli_its_file_meta_v2_t), ((uint8_t*)p_data), data_length); + } +#endif + + status = nvm3_writeData(nvm3_defaultHandle, + nvm3_object_id, + its_file_buffer, its_file_size + sizeof(sli_its_file_meta_v2_t)); + + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + set_cache(nvm3_object_id); + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size + sizeof(sli_its_file_meta_v2_t)); + mbedtls_free(its_file_buffer); + sli_its_release_mutex(); + return psa_status; +} + +/** + * \brief Retrieve the value associated with a provided uid + * + * \param[in] uid The uid value + * \param[in] data_offset The starting offset of the data requested + * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) + * \param[out] p_data The buffer where the data will be placed upon successful completion + * \param[out] p_data_length The amount of data returned in the p_data buffer + * + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval PSA_ERROR_BUFFER_TOO_SMALL The operation failed because the data associated with provided uid is larger than `data_size` + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * is invalid. For example is `NULL` or references memory the caller cannot access. + * In addition, this can also happen if an invalid offset was provided. + */ +psa_status_t psa_its_get(psa_storage_uid_t uid, + uint32_t data_offset, + uint32_t data_length, + void *p_data, + size_t *p_data_length) +{ + if ((data_length != 0U) && (p_data_length == NULL)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (data_length != 0U) { + // If the request amount of data is 0, allow invalid pointer of the output buffer. + if ((p_data == NULL) + || ((uint32_t)p_data < SRAM_BASE) + || ((uint32_t)p_data > (SRAM_BASE + SRAM_SIZE - data_length))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + size_t plaintext_length; + sli_its_encrypted_blob_t *blob = NULL; +#endif + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0u; + size_t its_file_data_size = 0u; + size_t its_file_offset = 0u; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + goto exit; + } +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE + && !object_lives_in_s(p_data, data_length)) { + // The flag indicates that this data should not be read back to the non-secure domain + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } +#endif + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Subtract IV and MAC from ITS file as the below checks concern the actual data size + its_file_data_size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#else + its_file_data_size = its_file_size; +#endif + + if (data_length != 0U) { + if ((data_offset >= its_file_data_size) && (its_file_data_size != 0U)) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if ((its_file_data_size == 0U) && (data_offset != 0U)) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } else { + // Allow the offset at the data size boundary if the requested amount of data is zero. + if (data_offset > its_file_data_size) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } + + if (data_length > (its_file_data_size - data_offset)) { + *p_data_length = its_file_data_size - data_offset; + } else { + *p_data_length = data_length; + } + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // its_file_size includes size of sli_its_encrypted_blob_t struct + blob = (sli_its_encrypted_blob_t*)mbedtls_calloc(1, its_file_size); + if (blob == NULL) { + psa_status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + memset(blob, 0, its_file_size); + + status = nvm3_readPartialData(nvm3_defaultHandle, + nvm3_object_id, + blob, + its_file_offset, + its_file_size); + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + goto exit; + } + + // Decrypt and authenticate blob + psa_status = sli_decrypt_its_file(&its_file_meta, + blob, + its_file_size, + blob->data, + its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD, + &plaintext_length); + + if (psa_status != PSA_SUCCESS) { + goto exit; + } + + if (plaintext_length != (its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD)) { + psa_status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + // Verify that the requested UID is equal to the retrieved and authenticated UID + if (uid != its_file_meta.uid) { + psa_status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (*p_data_length > 0) { + memcpy(p_data, blob->data + data_offset, *p_data_length); + } + psa_status = PSA_SUCCESS; + + exit: + if (blob != NULL) { + memset(blob, 0, its_file_size); + mbedtls_free(blob); + } + sli_its_release_mutex(); +#else + // If no encryption is used, just read out the data and write it directly to the output buffer + status = nvm3_readPartialData(nvm3_defaultHandle, nvm3_object_id, p_data, its_file_offset + data_offset, *p_data_length); + + if (status != ECODE_NVM3_OK) { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } else { + psa_status = PSA_SUCCESS; + } + + exit: + sli_its_release_mutex(); +#endif + + return psa_status; +} + +/** + * \brief Retrieve the metadata about the provided uid + * + * \param[in] uid The uid value + * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * is invalid, for example is `NULL` or references memory the caller cannot access + * \retval PSA_ERROR_INVALID_SIGANTURE The operation failed because authentication of the stored metadata failed. + */ +psa_status_t psa_its_get_info(psa_storage_uid_t uid, + struct psa_storage_info_t *p_info) +{ + if (p_info == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + sli_its_release_mutex(); + return psa_status; + } + + p_info->flags = its_file_meta.flags; + p_info->size = its_file_size; + +#if defined(SLI_PSA_ITS_ENCRYPTED) + // Remove IV and MAC size from file size + p_info->size = its_file_size - SLI_ITS_ENCRYPTED_BLOB_SIZE_OVERHEAD; +#endif + sli_its_release_mutex(); + return PSA_SUCCESS; +} + +/** + * \brief Remove the provided key and its associated data from the storage + * + * \param[in] uid The uid value + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The operation completed successfully + * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + */ +psa_status_t psa_its_remove(psa_storage_uid_t uid) +{ + psa_status_t psa_status = PSA_ERROR_CORRUPTION_DETECTED; + Ecode_t status; + sli_its_file_meta_v2_t its_file_meta = { 0 }; + size_t its_file_size = 0; + size_t its_file_offset = 0; + nvm3_ObjectKey_t nvm3_object_id; + + sli_its_acquire_mutex(); + psa_status = find_nvm3_id(uid, false, &its_file_meta, &its_file_offset, &its_file_size, &nvm3_object_id); + if (psa_status != PSA_SUCCESS) { + goto exit; + } + if (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE +#if defined(TFM_CONFIG_SL_SECURE_LIBRARY) + || (its_file_meta.flags == PSA_STORAGE_FLAG_WRITE_ONCE_SECURE_ACCESSIBLE) +#endif + ) { + psa_status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + status = nvm3_deleteObject(nvm3_defaultHandle, nvm3_object_id); + if (status == ECODE_NVM3_OK) { + // Power-loss might occur, however upon boot, the look-up table will be + // re-filled as long as the data has been successfully written to NVM3. + clear_cache(nvm3_object_id); + set_tomb(nvm3_object_id); + psa_status = PSA_SUCCESS; + } else { + psa_status = PSA_ERROR_STORAGE_FAILURE; + } + + exit: + sli_its_release_mutex(); + return psa_status; +} + +// ------------------------------------- +// Silicon Labs extensions + +static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) +{ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + /* Encode the owner in the upper 32 bits. This means that if + * owner values are nonzero (as they are on a PSA platform), + * no key file will ever have a value less than 0x100000000, so + * the whole range 0..0xffffffff is available for non-key files. */ + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); + return ((uint64_t) unsigned_owner_id << 32) | MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); +#else + /* Use the key id directly as a file name. + * psa_is_key_id_valid() in psa_crypto_slot_management.c + * is responsible for ensuring that key identifiers do not have a + * value that is reserved for non-key files. */ + return key; +#endif +} + +psa_status_t sli_psa_its_change_key_id(mbedtls_svc_key_id_t old_id, + mbedtls_svc_key_id_t new_id) +{ + psa_storage_uid_t old_uid = psa_its_identifier_of_slot(old_id); + psa_storage_uid_t new_uid = psa_its_identifier_of_slot(new_id); + size_t its_file_size = 0; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + if (old_id == new_id) { + return PSA_SUCCESS; + } + // Check whether the key to migrate exists on disk + struct psa_storage_info_t p_info; + status = psa_its_get_info(old_uid, &p_info); + if (status != PSA_SUCCESS) { + return status; + } + + // Allocate temporary buffer and cast it to the metadata format + uint8_t *its_file_buffer = mbedtls_calloc(1, p_info.size); + if (its_file_buffer == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + // Read contents of pre-existing key into the temporary buffer + status = psa_its_get(old_uid, 0, p_info.size, its_file_buffer, + &its_file_size); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_its_set(new_uid, its_file_size, its_file_buffer, + p_info.flags); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_its_remove(old_uid); + + if (status != PSA_SUCCESS) { + goto exit; + } + + exit: + // Clear and free key buffer before return. + memset(its_file_buffer, 0, its_file_size); + mbedtls_free(its_file_buffer); + return status; +} + +/** + * \brief Check if the ITS encryption is enabled + */ +psa_status_t sli_psa_its_encrypted(void) +{ +#if defined(SLI_PSA_ITS_ENCRYPTED) + return PSA_SUCCESS; +#else + return PSA_ERROR_NOT_SUPPORTED; +#endif +} + +#if defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +/** + * \brief Set the root key to be used when deriving session keys for ITS encryption. + * + * \param[in] root_key Buffer containing the root key. + * \param[in] root_key_size Size of the root key in bytes. Must be 32 (256 bits). + * + * \return A status indicating the success/failure of the operation + * + * \retval PSA_SUCCESS The key was successfully set. + * \retval PSA_ERROR_INVALID_ARGUMENT The root key was NULL or had an invalid size. + * \retval PSA_ERROR_ALREADY_EXISTS The root key has already been initialized. + */ +psa_status_t sli_psa_its_set_root_key(uint8_t *root_key, size_t root_key_size) +{ + // Check that arguments are valid + if (root_key == NULL || root_key_size != sizeof(g_root_key.data)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check that the root key has not already been set + // (This is possibly too restrictive. For TrustZone usage this can be enforced by + // not exposing the function to NS instead.) + if (g_root_key.initialized) { + return PSA_ERROR_ALREADY_EXISTS; + } + + // Store the provided root key and mark it as initialized + memcpy(g_root_key.data, root_key, sizeof(g_root_key.data)); + g_root_key.initialized = true; + + return PSA_SUCCESS; +} +#endif // defined(SLI_PSA_ITS_ENCRYPTED) && !defined(SEMAILBOX_PRESENT) +#endif // (!SL_PSA_ITS_SUPPORT_V3_DRIVER) +#endif // MBEDTLS_PSA_CRYPTO_STORAGE_C && !MBEDTLS_PSA_ITS_FILE_C diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c index eea804c..200ed31 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c @@ -1,281 +1,281 @@ -/******************************************************************************* - * @file - * @brief Driver for TRNG randomness generation through the TRNG peripheral on - VSE devices. - ******************************************************************************* - * # License - * Copyright 2024 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "psa/crypto.h" - -#include "cryptoacc_management.h" -#include "sli_cryptoacc_driver_trng.h" - -#include "sx_errors.h" -#include "cryptolib_types.h" -#include "sx_trng.h" -#include "sx_rng.h" -#include "sx_memcpy.h" -#include "ba431_config.h" - -#include "sl_assert.h" -#include "em_device.h" - -//------------------------------------------------------------------------------ -// Defines - -// Perform the TRNG conditioning test on startup. -#define DO_TRNG_COND_TEST (1) - -// Allow performing a few retries before determining that the TRNG is in a -// seriously bad state and cannot be initialized properly. -#define MAX_INITIALIZATION_ATTEMPTS (4) - -//------------------------------------------------------------------------------ -// Constants - -static const block_t trng_fifo_block = { - .addr = (uint8_t *)ADDR_BA431_FIFO, - .len = 0, - .flags = BLOCK_S_CONST_ADDR -}; - -//------------------------------------------------------------------------------ -// Forward Declarations - -static void cryptoacc_trng_get_random_wrapper(void *unused_state, - block_t output); - -//------------------------------------------------------------------------------ -// Global Data - -const struct sx_rng sli_cryptoacc_trng_wrapper = { - .param = NULL, - .get_rand_blk = cryptoacc_trng_get_random_wrapper, -}; - -//------------------------------------------------------------------------------ -// Static Function Definitions - -static psa_status_t wait_until_trng_is_ready_for_sleep(void) -{ - // We do not want to risk clocking down the CRYPTOACC while the ring - // oscillators are still spinning, since that means that they will not be - // shut down (unless EM2 or lower is entered). - uint32_t current_trng_status = BA431_STATE_RESET; - while (((current_trng_status = ba431_read_status()) & BA431_STAT_MASK_STATE) - != BA431_STATE_FIFOFULLOFF) { - switch (current_trng_status & BA431_STAT_MASK_STATE) { - case BA431_STATE_STARTUP: - case BA431_STATE_RUNNING: - case BA431_STATE_FIFOFULLON: - // These are the only valid states that we would expect the TRNG to be - // in now that we have read randomness from it. - break; - default: - return PSA_ERROR_HARDWARE_FAILURE; - break; - } - } - - // Make sure that no new alarms have been triggered while the FIFO was being - // filled. All other (more serious) continous test failures will result in the - // TRNG control finite state machine moving to the error state: meaning that - // we would have already returned in the switch statement above. - if (current_trng_status & BA431_STAT_MASK_PREALM_INT) { - // The severity of a preliminary noise alarm is lower than other alarms that - // will put the TRNG in an error state. Instead of (potentially) triggering - // a system reset, we will make sure to disable the TRNG such that it needs - // to be re-initialized before the next use: that will cause startup tests - // to run again. - ba431_disable_ndrng(); - } - - return PSA_SUCCESS; -} - -static psa_status_t wait_until_trng_has_started(void) -{ - uint32_t ba431_status = 0; - ba431_state_t ba431_state = BA431_STATE_RESET; - - // Poll the status until the startup routine has finished. - do { - ba431_status = ba431_read_status(); - ba431_state = (ba431_state_t) (ba431_status & BA431_STAT_MASK_STATE); - } while ((ba431_state == BA431_STATE_RESET) - || (ba431_state == BA431_STATE_STARTUP)); - - // Make sure that the NIST-800-90B startup test passed (the fact that we have - // left the startup state means that the corresponding AIS31 test also - // passed). - if (ba431_status & BA431_STAT_MASK_STARTUP_FAIL) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // This would have been caught by the above startup failure check. - EFM_ASSERT(ba431_state != BA431_STATE_ERROR); - - return PSA_SUCCESS; -} - -static psa_status_t initialize_trng(void) -{ - size_t attempts_remaining = MAX_INITIALIZATION_ATTEMPTS; - - while (attempts_remaining--) { - if (sx_trng_init(DO_TRNG_COND_TEST) != CRYPTOLIB_SUCCESS) { - continue; - } - - // The implementation of sx_trng_get_rand_blk() doesn't actually assert - // that the startup check passed succesfully (only that the TRNG is no - // longer in a reset- or startup state). Therefore, we will implement our - // own functions for waiting until the startup has completed and then - // getting randomness from the TRNG FIFO. - if (wait_until_trng_has_started() != PSA_SUCCESS) { - continue; - } - - // When we reach this point, the TRNG has started succesfully and is ready - // to be used. - return PSA_SUCCESS; - } - - // If we against all odds reach this point, we have not been able to - // initialize the TRNG even after multiple retries. - return PSA_ERROR_HARDWARE_FAILURE; -} - -static bool trng_needs_initialization(void) -{ - // If the TRNG (NDRNG) is not enabled, it most definitely is not initialized. - if ((ba431_read_controlreg() & BA431_CTRL_NDRNG_ENABLE) == 0u) { - return true; - } - - // If a full word of the conditioning (whitening) key is all zero, it probably - // hasn't been initialized properly. - uint32_t cond_key[4] = { 0 }; - ba431_read_conditioning_key(cond_key); - if ((cond_key[0] == 0) - || (cond_key[1] == 0) - || (cond_key[2] == 0) - || (cond_key[3] == 0)) { - return true; - } - - // No conditions were met, which means that the TRNG must have already been - // initialized. - return false; -} - -static psa_status_t cryptoacc_trng_get_random(block_t output) -{ - if (trng_needs_initialization()) { - // In addition to configuring the TRNG, this funtion will also wait until - // the hardware is fully ready for usage. - psa_status_t status = initialize_trng(); - if (status != PSA_SUCCESS) { - return status; - } - } - - size_t n_bytes_generated = 0; - while (n_bytes_generated < output.len) { - // Don't attempt to read more from the TRNG FIFO than the amount of random - // words that it currently holds. - block_t chunk_block = block_t_convert( - output.addr + n_bytes_generated, - SX_MIN(output.len - n_bytes_generated, - sizeof(uint32_t) * (ba431_read_fifolevel()))); - memcpy_blk(chunk_block, trng_fifo_block, chunk_block.len); - n_bytes_generated += chunk_block.len; - } - - // Potential bad states reached by the TRNG during the above randomness - // generation will be handled by this function. - return wait_until_trng_is_ready_for_sleep(); -} - -//------------------------------------------------------------------------------ -// Public Function Definitions - -/* - * \brief - * Wrapper function for getting random data from the TRNG. - * - * \details - * Even though it is declared with a static scope, a function pointer to this - * function will be exposed so that it is indirectly usable for other - * compilation units as well. - * - * \note - * This function does not assume any responsibility to aquire and release - * ownership of the CRYPTOACC peripheral. - * - * \warning - * This function is called from contexts where it is not possible to return an - * error code. Any errors are therefore handled by resetting the system. This - * is deemed appropriate since a failed randomness generation may have severe - * security implications. - */ -static void cryptoacc_trng_get_random_wrapper(void *unused_state, - block_t output) -{ - (void)unused_state; - - if (cryptoacc_trng_get_random(output) != PSA_SUCCESS) { - EFM_ASSERT(false); - sx_trng_apply_soft_reset(); - NVIC_SystemReset(); - } -} - -psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len) -{ - psa_status_t status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - status = cryptoacc_trng_get_random(block_t_convert(output, len)); - if (status != PSA_SUCCESS) { - // Soft reset such that the next attempt (if the function is called again) - // is more likely to succeed. - sx_trng_apply_soft_reset(); - cryptoacc_management_release(); - return status; - } - - return cryptoacc_management_release(); -} - -#endif // SLI_MBEDTLS_DEVICE_VSE +/******************************************************************************* + * @file + * @brief Driver for TRNG randomness generation through the TRNG peripheral on + VSE devices. + ******************************************************************************* + * # License + * Copyright 2024 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "cryptolib_types.h" +#include "sx_trng.h" +#include "sx_rng.h" +#include "sx_memcpy.h" +#include "ba431_config.h" + +#include "sl_assert.h" +#include "em_device.h" + +//------------------------------------------------------------------------------ +// Defines + +// Perform the TRNG conditioning test on startup. +#define DO_TRNG_COND_TEST (1) + +// Allow performing a few retries before determining that the TRNG is in a +// seriously bad state and cannot be initialized properly. +#define MAX_INITIALIZATION_ATTEMPTS (4) + +//------------------------------------------------------------------------------ +// Constants + +static const block_t trng_fifo_block = { + .addr = (uint8_t *)ADDR_BA431_FIFO, + .len = 0, + .flags = BLOCK_S_CONST_ADDR +}; + +//------------------------------------------------------------------------------ +// Forward Declarations + +static void cryptoacc_trng_get_random_wrapper(void *unused_state, + block_t output); + +//------------------------------------------------------------------------------ +// Global Data + +const struct sx_rng sli_cryptoacc_trng_wrapper = { + .param = NULL, + .get_rand_blk = cryptoacc_trng_get_random_wrapper, +}; + +//------------------------------------------------------------------------------ +// Static Function Definitions + +static psa_status_t wait_until_trng_is_ready_for_sleep(void) +{ + // We do not want to risk clocking down the CRYPTOACC while the ring + // oscillators are still spinning, since that means that they will not be + // shut down (unless EM2 or lower is entered). + uint32_t current_trng_status = BA431_STATE_RESET; + while (((current_trng_status = ba431_read_status()) & BA431_STAT_MASK_STATE) + != BA431_STATE_FIFOFULLOFF) { + switch (current_trng_status & BA431_STAT_MASK_STATE) { + case BA431_STATE_STARTUP: + case BA431_STATE_RUNNING: + case BA431_STATE_FIFOFULLON: + // These are the only valid states that we would expect the TRNG to be + // in now that we have read randomness from it. + break; + default: + return PSA_ERROR_HARDWARE_FAILURE; + break; + } + } + + // Make sure that no new alarms have been triggered while the FIFO was being + // filled. All other (more serious) continous test failures will result in the + // TRNG control finite state machine moving to the error state: meaning that + // we would have already returned in the switch statement above. + if (current_trng_status & BA431_STAT_MASK_PREALM_INT) { + // The severity of a preliminary noise alarm is lower than other alarms that + // will put the TRNG in an error state. Instead of (potentially) triggering + // a system reset, we will make sure to disable the TRNG such that it needs + // to be re-initialized before the next use: that will cause startup tests + // to run again. + ba431_disable_ndrng(); + } + + return PSA_SUCCESS; +} + +static psa_status_t wait_until_trng_has_started(void) +{ + uint32_t ba431_status = 0; + ba431_state_t ba431_state = BA431_STATE_RESET; + + // Poll the status until the startup routine has finished. + do { + ba431_status = ba431_read_status(); + ba431_state = (ba431_state_t) (ba431_status & BA431_STAT_MASK_STATE); + } while ((ba431_state == BA431_STATE_RESET) + || (ba431_state == BA431_STATE_STARTUP)); + + // Make sure that the NIST-800-90B startup test passed (the fact that we have + // left the startup state means that the corresponding AIS31 test also + // passed). + if (ba431_status & BA431_STAT_MASK_STARTUP_FAIL) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // This would have been caught by the above startup failure check. + EFM_ASSERT(ba431_state != BA431_STATE_ERROR); + + return PSA_SUCCESS; +} + +static psa_status_t initialize_trng(void) +{ + size_t attempts_remaining = MAX_INITIALIZATION_ATTEMPTS; + + while (attempts_remaining--) { + if (sx_trng_init(DO_TRNG_COND_TEST) != CRYPTOLIB_SUCCESS) { + continue; + } + + // The implementation of sx_trng_get_rand_blk() doesn't actually assert + // that the startup check passed succesfully (only that the TRNG is no + // longer in a reset- or startup state). Therefore, we will implement our + // own functions for waiting until the startup has completed and then + // getting randomness from the TRNG FIFO. + if (wait_until_trng_has_started() != PSA_SUCCESS) { + continue; + } + + // When we reach this point, the TRNG has started succesfully and is ready + // to be used. + return PSA_SUCCESS; + } + + // If we against all odds reach this point, we have not been able to + // initialize the TRNG even after multiple retries. + return PSA_ERROR_HARDWARE_FAILURE; +} + +static bool trng_needs_initialization(void) +{ + // If the TRNG (NDRNG) is not enabled, it most definitely is not initialized. + if ((ba431_read_controlreg() & BA431_CTRL_NDRNG_ENABLE) == 0u) { + return true; + } + + // If a full word of the conditioning (whitening) key is all zero, it probably + // hasn't been initialized properly. + uint32_t cond_key[4] = { 0 }; + ba431_read_conditioning_key(cond_key); + if ((cond_key[0] == 0) + || (cond_key[1] == 0) + || (cond_key[2] == 0) + || (cond_key[3] == 0)) { + return true; + } + + // No conditions were met, which means that the TRNG must have already been + // initialized. + return false; +} + +static psa_status_t cryptoacc_trng_get_random(block_t output) +{ + if (trng_needs_initialization()) { + // In addition to configuring the TRNG, this funtion will also wait until + // the hardware is fully ready for usage. + psa_status_t status = initialize_trng(); + if (status != PSA_SUCCESS) { + return status; + } + } + + size_t n_bytes_generated = 0; + while (n_bytes_generated < output.len) { + // Don't attempt to read more from the TRNG FIFO than the amount of random + // words that it currently holds. + block_t chunk_block = block_t_convert( + output.addr + n_bytes_generated, + SX_MIN(output.len - n_bytes_generated, + sizeof(uint32_t) * (ba431_read_fifolevel()))); + memcpy_blk(chunk_block, trng_fifo_block, chunk_block.len); + n_bytes_generated += chunk_block.len; + } + + // Potential bad states reached by the TRNG during the above randomness + // generation will be handled by this function. + return wait_until_trng_is_ready_for_sleep(); +} + +//------------------------------------------------------------------------------ +// Public Function Definitions + +/* + * \brief + * Wrapper function for getting random data from the TRNG. + * + * \details + * Even though it is declared with a static scope, a function pointer to this + * function will be exposed so that it is indirectly usable for other + * compilation units as well. + * + * \note + * This function does not assume any responsibility to aquire and release + * ownership of the CRYPTOACC peripheral. + * + * \warning + * This function is called from contexts where it is not possible to return an + * error code. Any errors are therefore handled by resetting the system. This + * is deemed appropriate since a failed randomness generation may have severe + * security implications. + */ +static void cryptoacc_trng_get_random_wrapper(void *unused_state, + block_t output) +{ + (void)unused_state; + + if (cryptoacc_trng_get_random(output) != PSA_SUCCESS) { + EFM_ASSERT(false); + sx_trng_apply_soft_reset(); + NVIC_SystemReset(); + } +} + +psa_status_t sli_cryptoacc_trng_get_random(unsigned char *output, size_t len) +{ + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + status = cryptoacc_trng_get_random(block_t_convert(output, len)); + if (status != PSA_SUCCESS) { + // Soft reset such that the next attempt (if the function is called again) + // is more likely to succeed. + sx_trng_apply_soft_reset(); + cryptoacc_management_release(); + return status; + } + + return cryptoacc_management_release(); +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c index f01361b..c89a7d1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c @@ -1,1825 +1,1825 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver AEAD functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" -#include "sli_psa_driver_common.h" -#include "cryptoacc_management.h" -// Replace inclusion of psa/crypto_xxx.h with the new psa driver common -// interface header file when it becomes available. -#include "psa/crypto_platform.h" -#include "psa/crypto_sizes.h" -#include "psa/crypto_struct.h" -#include "sx_aes.h" -#include "sx_errors.h" -#include "cryptolib_types.h" - -#include - -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - -static psa_status_t check_aead_parameters(const psa_key_attributes_t *attributes, - psa_algorithm_t alg, - size_t nonce_length, - size_t additional_data_length) -{ - size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), - psa_get_key_bits(attributes), - alg); - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (tag_length < 4 - || tag_length > 16 - || tag_length % 2 != 0 - || nonce_length < 7 - || nonce_length > 13) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - // AD are limited to 2^64 bits, so 2^61 bytes. - // We need not check if SIZE_MAX (max of size_t) is less than 2^61 (0x2000000000000000) -#if SIZE_MAX > 0x2000000000000000ull - if (additional_data_length >> 61 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } -#else // SIZE_MAX > 0x2000000000000000ull - (void) additional_data_length; -#endif // SIZE_MAX > 0x2000000000000000ull - if ((tag_length < 4) || (tag_length > 16)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (nonce_length == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } -#if !defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) - if (nonce_length != AES_IV_GCM_SIZE) { - // Libcryptosoc only supports 12 bytes long IVs. - return PSA_ERROR_NOT_SUPPORTED; - } -#endif // ! SLI_PSA_SUPPORT_GCM_IV_CALCULATION - break; -#endif // PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - break; - } - -#if !defined(PSA_WANT_ALG_GCM) - (void) additional_data_length; -#endif // !PSA_WANT_ALG_GCM - - switch (psa_get_key_bits(attributes)) { - case 128: // fallthrough - case 192: // fallthrough - case 256: - break; - default: - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - -#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) && defined(PSA_WANT_ALG_GCM) -/* Do GCM in software in case the IV isn't 12 bytes, since that's the only - * thing the accelerator supports. */ -static psa_status_t sli_cryptoacc_software_gcm(const uint8_t* keybuf, - size_t key_length, - const uint8_t* nonce, - size_t nonce_length, - const uint8_t* additional_data, - size_t additional_data_length, - const uint8_t* input, - uint8_t* output, - size_t plaintext_length, - size_t tag_length, - uint8_t* tag, - bool encrypt_ndecrypt) -{ - // Step 1: calculate H = Ek(0) - uint8_t Ek[16] = { 0 }; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key = block_t_convert(keybuf, key_length); - block_t data_in = block_t_convert(Ek, sizeof(Ek)); - block_t data_out = block_t_convert(Ek, sizeof(Ek)); - - psa_status_t status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_ecb_encrypt(&key, - &data_in, - &data_out); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Step 2: calculate IV = GHASH(H, {}, IV) - uint8_t iv[16] = { 0 }; - uint64_t HL[16], HH[16]; - - sli_psa_software_ghash_setup(Ek, HL, HH); - - for (size_t i = 0; i < nonce_length; i += 16) { - // Mix in IV - for (size_t j = 0; j < (nonce_length - i > 16 ? 16 : nonce_length - i); j++) { - iv[j] ^= nonce[i + j]; - } - // Update result - sli_psa_software_ghash_multiply(HL, HH, iv, iv); - } - - iv[12] ^= (nonce_length * 8) >> 24; - iv[13] ^= (nonce_length * 8) >> 16; - iv[14] ^= (nonce_length * 8) >> 8; - iv[15] ^= (nonce_length * 8) >> 0; - - sli_psa_software_ghash_multiply(HL, HH, iv, iv); - - // Step 3: Calculate first counter block for tag generation - uint8_t tagbuf[16] = { 0 }; - data_in = block_t_convert(iv, sizeof(iv)); - data_out = block_t_convert(tagbuf, sizeof(tagbuf)); - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_ecb_encrypt(&key, - &data_in, - &data_out); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // If we're decrypting, mix in the to-be-checked tag value before transforming - if (!encrypt_ndecrypt) { - for (size_t i = 0; i < tag_length; i++) { - tagbuf[i] ^= tag[i]; - } - } - - // Step 4: increment IV (ripple increment) - for (size_t i = 0; i < 16; i++) { - iv[15 - i]++; - - if (iv[15 - i] != 0) { - break; - } - } - - // Step 5: Accumulate additional data - memset(Ek, 0, sizeof(Ek)); - for (size_t i = 0; i < additional_data_length; i += 16) { - // Mix in additional data as much as we have - for (size_t j = 0; - j < (additional_data_length - i > 16 ? 16 : additional_data_length - i); - j++) { - Ek[j] ^= additional_data[i + j]; - } - - sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); - } - - // Step 6: If we're decrypting, accumulate the ciphertext before it gets transformed - if (!encrypt_ndecrypt) { - for (size_t i = 0; i < plaintext_length; i += 16) { - // Mix in ciphertext - for (size_t j = 0; - j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); - j++) { - Ek[j] ^= input[i + j]; - } - - sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); - } - } - - // Step 7: transform data using AES-CTR - if (plaintext_length) { - data_in = block_t_convert(input, plaintext_length); - data_out = block_t_convert(output, plaintext_length); - block_t nonce_internal = block_t_convert(iv, sizeof(iv)); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_ctr_encrypt(&key, - &data_in, - &data_out, - &nonce_internal); - - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Step 8: If we're encrypting, accumulate the ciphertext now - if (encrypt_ndecrypt) { - for (size_t i = 0; i < plaintext_length; i += 16) { - // Mix in ciphertext - for (size_t j = 0; - j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); - j++) { - Ek[j] ^= output[i + j]; - } - - sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); - } - } - - // Step 9: add len(A) || len(C) block to tag calculation - uint64_t bitlen = additional_data_length * 8; - Ek[0] ^= bitlen >> 56; - Ek[1] ^= bitlen >> 48; - Ek[2] ^= bitlen >> 40; - Ek[3] ^= bitlen >> 32; - Ek[4] ^= bitlen >> 24; - Ek[5] ^= bitlen >> 16; - Ek[6] ^= bitlen >> 8; - Ek[7] ^= bitlen >> 0; - - bitlen = plaintext_length * 8; - Ek[8] ^= bitlen >> 56; - Ek[9] ^= bitlen >> 48; - Ek[10] ^= bitlen >> 40; - Ek[11] ^= bitlen >> 32; - Ek[12] ^= bitlen >> 24; - Ek[13] ^= bitlen >> 16; - Ek[14] ^= bitlen >> 8; - Ek[15] ^= bitlen >> 0; - - sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); - - // Step 10: calculate tag value - for (size_t i = 0; i < tag_length; i++) { - tagbuf[i] ^= Ek[i]; - } - - // Step 11: output tag for encrypt operation, check tag for decrypt - if (encrypt_ndecrypt) { - memcpy(tag, tagbuf, tag_length); - } else { - uint8_t accumulator = 0; - for (size_t i = 0; i < tag_length; i++) { - accumulator |= tagbuf[i]; - } - if (accumulator != 0) { - return PSA_ERROR_INVALID_SIGNATURE; - } - } - - return PSA_SUCCESS; -} -#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION && PSA_WANT_ALG_GCM - -psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length) -{ -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - if (ciphertext_size <= plaintext_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - size_t tag_length = 0; - psa_status_t psa_status = sli_cryptoacc_transparent_aead_encrypt_tag( - attributes, key_buffer, key_buffer_size, alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, plaintext_length, ciphertext_length, - &ciphertext[plaintext_length], ciphertext_size - plaintext_length, &tag_length); - - if (psa_status == PSA_SUCCESS) { - *ciphertext_length += tag_length; - } - - return psa_status; - -#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)nonce; - (void)nonce_length; - (void)additional_data; - (void)additional_data_length; - (void)plaintext; - (void)plaintext_length; - (void)ciphertext; - (void)ciphertext_size; - (void)ciphertext_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length) -{ -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - if (attributes == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), - psa_get_key_bits(attributes), - alg); - - if (ciphertext_length < tag_length - || ciphertext == NULL - || (tag_length > 16)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Split the tag in its own buffer to avoid potential issues when the - // plaintext buffer extends into the tag area - uint8_t check_tag[16]; - memcpy(check_tag, &ciphertext[ciphertext_length - tag_length], tag_length); - - return sli_cryptoacc_transparent_aead_decrypt_tag( - attributes, key_buffer, key_buffer_size, alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length - tag_length, - check_tag, tag_length, - plaintext, plaintext_size, plaintext_length); -#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)nonce; - (void)nonce_length; - (void)additional_data; - (void)additional_data_length; - (void)plaintext; - (void)plaintext_size; - (void)plaintext_length; - (void)ciphertext; - (void)ciphertext_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length) -{ -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (key_buffer == NULL - || attributes == NULL - || nonce == NULL - || (additional_data == NULL && additional_data_length > 0) - || (plaintext == NULL && plaintext_length > 0) - || (plaintext_length > 0 && (ciphertext == NULL || ciphertext_size == 0)) - || ciphertext_length == NULL || tag_length == NULL - || tag_size == 0 || tag == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - size_t key_bits = psa_get_key_bits(attributes); - *tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), - psa_get_key_bits(attributes), - alg); - - // Verify that the driver supports the given parameters. - psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); - if (status != PSA_SUCCESS) { - return status; - } - - // Check input-key size. - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check sufficient output buffer size. - if ((ciphertext_size < plaintext_length) - || (tag_size < *tag_length)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((ciphertext > plaintext) && (ciphertext < (plaintext + plaintext_length))) { - memmove(ciphertext, plaintext, plaintext_length); - plaintext = ciphertext; - } - - psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - - block_t key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - block_t aad_block = block_t_convert(additional_data, additional_data_length); - block_t nonce_internal = block_t_convert(nonce, nonce_length); - block_t data_in = block_t_convert(plaintext, plaintext_length); - block_t data_out = block_t_convert(ciphertext, plaintext_length); - block_t tag_block = block_t_convert(tag, *tag_length); - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - - // Check length of plaintext. - { - unsigned char q = 16 - 1 - (unsigned char) nonce_length; - if (q < sizeof(plaintext_length) - && plaintext_length >= (1UL << (q * 8))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_ccm_encrypt(&key, - &data_in, - &data_out, - &nonce_internal, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return_status = PSA_SUCCESS; - break; -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - if (nonce_length == AES_IV_GCM_SIZE) { - uint8_t tagbuf[16]; - tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_gcm_encrypt(&key, - &data_in, - &data_out, - &nonce_internal, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - // Copy only requested part of computed tag to user output buffer. - memcpy(tag, tagbuf, *tag_length); - return_status = PSA_SUCCESS; - } -#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) - else { - return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, - ciphertext, - plaintext_length, - *tag_length, - tag, - true); - } -#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION - else { - return_status = PSA_ERROR_NOT_SUPPORTED; - } -#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION - break; -#endif // PSA_WANT_ALG_GCM - } - - if (return_status == PSA_SUCCESS) { - *ciphertext_length = plaintext_length; - } else { - *ciphertext_length = 0; - *tag_length = 0; - } - - return return_status; - -#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)nonce; - (void)nonce_length; - (void)additional_data; - (void)additional_data_length; - (void)plaintext; - (void)plaintext_length; - (void)ciphertext; - (void)ciphertext_size; - (void)ciphertext_length; - (void)tag; - (void)tag_size; - (void)tag_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - const uint8_t* tag, - size_t tag_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length) -{ -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - if (attributes == NULL - || key_buffer == NULL - || nonce == NULL - || (additional_data == NULL && additional_data_length > 0) - || (ciphertext == NULL && ciphertext_length > 0) - || (plaintext == NULL && plaintext_size > 0) - || plaintext_length == NULL - || tag == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Verify that the driver supports the given parameters. - size_t key_bits = psa_get_key_bits(attributes); - psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); - if (status != PSA_SUCCESS) { - return status; - } - - // Check input-key size. - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check sufficient output buffer size. - if (plaintext_size < ciphertext_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((plaintext > ciphertext) && (plaintext < (ciphertext + ciphertext_length))) { - memmove(plaintext, ciphertext, ciphertext_length); - ciphertext = plaintext; - } - - psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key = NULL_blk; - block_t aad_block = NULL_blk; - block_t tag_block = NULL_blk; - block_t nonce_internal = NULL_blk; - block_t data_in = NULL_blk; - block_t data_out = NULL_blk; - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - - { - // Check length of ciphertext. - unsigned char q = 16 - 1 - (unsigned char) nonce_length; - if (q < sizeof(ciphertext_length) - && ciphertext_length >= (1UL << (q * 8))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - aad_block = block_t_convert(additional_data, additional_data_length); - tag_block = block_t_convert(tag, tag_length); - nonce_internal = block_t_convert(nonce, nonce_length); - data_in = block_t_convert(ciphertext, ciphertext_length); - data_out = block_t_convert(plaintext, ciphertext_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_ccm_decrypt_verify(&key, - &data_in, - &data_out, - &nonce_internal, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { - return_status = PSA_ERROR_INVALID_SIGNATURE; - } else if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return_status = PSA_ERROR_HARDWARE_FAILURE; - } else { - *plaintext_length = ciphertext_length; - return_status = PSA_SUCCESS; - } - break; -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - uint8_t tagbuf[16]; - uint32_t diff = 0; - - if (nonce_length == AES_IV_GCM_SIZE) { - key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - aad_block = block_t_convert(additional_data, additional_data_length); - tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); - nonce_internal = block_t_convert(nonce, nonce_length); - data_in = block_t_convert(ciphertext, ciphertext_length); - data_out = block_t_convert(plaintext, ciphertext_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_aes_gcm_decrypt(&key, - &data_in, - &data_out, - &nonce_internal, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return_status = PSA_ERROR_HARDWARE_FAILURE; - } else { - // Check that the provided tag equals the calculated one - // (in constant time). Note that the tag returned by ccm_auth_crypt - // is encrypted, so we don't have to decrypt the tag. - diff = sli_psa_safer_memcmp(tag, tagbuf, tag_length); - sli_psa_zeroize(tagbuf, tag_length); - - if (diff != 0) { - return_status = PSA_ERROR_INVALID_SIGNATURE; - } else { - *plaintext_length = ciphertext_length; - return_status = PSA_SUCCESS; - } - - break; - } - } -#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) - else { - return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, - plaintext, - ciphertext_length, - tag_length, - (uint8_t*)tag, - false); - if (return_status == PSA_SUCCESS) { - *plaintext_length = ciphertext_length; - } - } -#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION - else { - return_status = PSA_ERROR_NOT_SUPPORTED; - } -#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION - break; - } -#endif // PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - if (return_status != PSA_SUCCESS) { - *plaintext_length = 0; - sli_psa_zeroize(plaintext, plaintext_size); - } - - return return_status; - -#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)nonce; - (void)nonce_length; - (void)additional_data; - (void)additional_data_length; - (void)plaintext; - (void)plaintext_size; - (void)plaintext_length; - (void)ciphertext; - (void)ciphertext_length; - (void)tag; - (void)tag_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) -static psa_status_t transparent_aead_encrypt_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - sli_aes_mode_t operation_direction) -{ - if (operation == NULL - || attributes == NULL - || key_buffer == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memset(operation, 0, sizeof(*operation)); - - size_t key_bits = psa_get_key_bits(attributes); - size_t key_size = PSA_BITS_TO_BYTES(key_bits); - - if (key_buffer_size < key_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (sizeof(operation->key) < key_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Validate key type. - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // Validate tag length. - if ( PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), key_bits, alg) > 16 ) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Validate operation. - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined (PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - operation->alg = alg; - break; - } - #endif - #if defined (PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - operation->alg = alg; - break; - } - #endif - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - memcpy(operation->key, key_buffer, key_size); - operation->key_len = key_size; - - operation->direction = operation_direction; - - return PSA_SUCCESS; -} -#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - -psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_ENC); - - #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)operation; - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - - return PSA_ERROR_NOT_SUPPORTED; - #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_DEC); - - #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - (void)operation; - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - return PSA_ERROR_NOT_SUPPORTED; - #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_size) -{ -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (operation == NULL || nonce == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Not able to set nonce twice. - if (operation->ctx.preinit.nonce_length != 0) { - return PSA_ERROR_BAD_STATE; - } - - if (nonce_size > sizeof(operation->ctx.preinit.nonce)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // Validate operation. - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - if (nonce_size != 12) { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - } -#endif -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - if (nonce_size < 7 || nonce_size > 13) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; - } -#endif - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - memcpy(operation->ctx.preinit.nonce, nonce, nonce_size); - operation->ctx.preinit.nonce_length = nonce_size; - return PSA_SUCCESS; - -#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - (void)operation; - (void)nonce; - (void)nonce_size; - return PSA_ERROR_NOT_SUPPORTED; -#endif -} - -psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - (void)ad_length; - - // Check if operation has already started - if (operation->ad_len != 0 || operation->processed_len != 0) { - return PSA_ERROR_BAD_STATE; - } - - // To pass current PSA Crypto test suite, tag length encoded in the - // algorithm needs to be checked at this point. - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - if ((PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) % 2 != 0) - || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 - || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - operation->total_length = plaintext_length; - - break; -#endif -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - (void)plaintext_length; - if (PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 - || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif - default: - return PSA_ERROR_BAD_STATE; - } - - return PSA_SUCCESS; - #else//PSA_WANT_ALG_CCM - (void)operation; - (void)ad_length; - (void)plaintext_length; - return PSA_ERROR_NOT_SUPPORTED; - #endif//PSA_WANT_ALG_CCM -} - -#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) -static psa_status_t cryptoacc_aead_start(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - - psa_algorithm_t alg = operation->alg; - - block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); - - block_t key = block_t_convert(operation->key, operation->key_len); - block_t aad_block = block_t_convert(input, input_length); - block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); - block_t data_in = NULL_blk; - block_t data_out = NULL_blk; - - // Get ownership. - return_status = cryptoacc_management_acquire(); - if (return_status != PSA_SUCCESS) { - return return_status; - } - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - uint32_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); - if (operation->direction == SLI_AES_ENC) { - // CCM finish must have input data, in the case of pt_len = 0 and aad_len != 0 we - // need to precompute the tag. (Only needed for encrypt) - if (operation->total_length == 0 && input_length != 0) { - block_t tag_block = block_t_convert(operation->ctx.tag_buf, tag_length); - sx_ret = sx_aes_ccm_encrypt(&key, - &data_in, - &data_out, - &nonce_block, - &tag_block, - &aad_block); - - goto exit; - } else { - sx_ret = sx_aes_ccm_encrypt_init(&key, - &data_in, - &data_out, - &nonce_block, - &ctx_out_block, - &aad_block, - tag_length, - operation->total_length); - } - } else { - sx_ret = sx_aes_ccm_decrypt_init(&key, - &data_in, - &data_out, - &nonce_block, - &ctx_out_block, - &aad_block, - tag_length, - operation->total_length); - } - break; - } -#endif//PSA_WANT_ALG_CCM -#if defined (PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_gcm_encrypt_init(&key, - &data_in, - &data_out, - &nonce_block, - &ctx_out_block, - &aad_block); - } else { - sx_ret = sx_aes_gcm_decrypt_init(&key, - &data_in, - &data_out, - &nonce_block, - &ctx_out_block, - &aad_block); - } - goto exit; - break; -#endif//PSA_WANT_ALG_GCM - } - - exit: - - // Release ownership. - return_status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - operation->ad_len += input_length; - return PSA_SUCCESS; -} -#endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - -psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (operation == NULL - || (input == NULL && input_length > 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - - if (operation->ad_len > 0 || operation->processed_len > 0) { - return PSA_ERROR_BAD_STATE; - } - - // No additional data. - if (input_length == 0) { - return PSA_SUCCESS; - } - - return cryptoacc_aead_start(operation, input, input_length); -#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - - (void)operation; - (void)input; - (void)input_length; - return PSA_ERROR_NOT_SUPPORTED; -#endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - if (operation == NULL - || ((input == NULL || output == NULL) && input_length > 0) - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - - // Check variable overflow - if (operation->processed_len > 0xFFFFFFFF - input_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - *output_length = 0; - - if (input_length == 0) { - return PSA_SUCCESS; - } - - psa_algorithm_t alg = operation->alg; - - psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - - block_t key = block_t_convert(operation->key, operation->key_len); - - block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); - block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); - - block_t input_block = block_t_convert(input, input_length); - block_t output_block = block_t_convert(output, input_length); - - // The extra logic is to support non-blocksize input data. - - // Store data in context if there is space in the data buffer. - if ((input_length + operation->final_data_length) < 16 && input_length < 16) { - if (operation->final_data_length > 16) { - // Invalid context. - return PSA_ERROR_INVALID_ARGUMENT; - } - - memcpy(operation->final_data + operation->final_data_length, input, input_length); - operation->final_data_length += input_length; - return PSA_SUCCESS; - } - - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { - if (operation->ad_len == 0 && operation->processed_len == 0) { - cryptoacc_aead_start(operation, NULL, 0); - } - } - - uint8_t input_offset = 0; - -#if defined(PSA_WANT_ALG_GCM) - block_t aad_block = NULL_blk; - block_t nonce_block = NULL_blk; - - if (operation->ad_len == 0 && operation->processed_len == 0) { - // Operation is not initialized. - nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); - } -#endif - - if (operation->final_data_length) { - if (operation->final_data_length > 16) { - // Invalid context. - return PSA_ERROR_INVALID_ARGUMENT; - } - - // If there is data stored in context: fill final_data buffer and process it first. - input_offset = 16 - operation->final_data_length; - memcpy(operation->final_data + operation->final_data_length, input, input_offset); - -#if defined(PSA_WANT_ALG_CCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { - if (operation->processed_len + 16 == operation->total_length) { - operation->final_data_length = 16; - return PSA_SUCCESS; - } - } -#endif - - block_t input_block_final = block_t_convert(operation->final_data, 16); - block_t output_block_final = block_t_convert(output, 16); - - return_status = cryptoacc_management_acquire(); - if (return_status != PSA_SUCCESS) { - return return_status; - } - - #if defined(PSA_WANT_ALG_GCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { - if (operation->ad_len == 0 && operation->processed_len == 0) { - // Not initialized. - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_gcm_encrypt_init(&key, - &input_block_final, - &output_block_final, - &nonce_block, - &ctx_out_block, - &aad_block); - } else { - sx_ret = sx_aes_gcm_decrypt_init(&key, - &input_block_final, - &output_block_final, - &nonce_block, - &ctx_out_block, - &aad_block); - } - } else { - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_gcm_encrypt_update(&key, - &input_block_final, - &output_block_final, - &ctx_in_block, - &ctx_out_block); - } else { - sx_ret = sx_aes_gcm_decrypt_update(&key, - &input_block_final, - &output_block_final, - &ctx_in_block, - &ctx_out_block); - } - } - } - #endif //PSA_WANT_ALG_GCM - - #if defined(PSA_WANT_ALG_CCM) - if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_ccm_encrypt_update(&key, - &input_block_final, - &output_block_final, - &ctx_in_block, - &ctx_out_block); - } else { - sx_ret = sx_aes_ccm_decrypt_update(&key, - &input_block_final, - &output_block_final, - &ctx_in_block, - &ctx_out_block); - } - } - #endif //PSA_WANT_ALG_CCM - - // Release ownership. - return_status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - operation->final_data_length = 0; - input_length -= input_offset; - operation->processed_len += 16; - output += 16; - *output_length += 16; - } - - // Store data in context if there is space in the data buffer. - if (input_length < 16 && !operation->final_data_length && input_length < 16) { - memcpy(operation->final_data, input + input_offset, input_length); - operation->final_data_length = input_length; - return PSA_SUCCESS; - } - - // Store data that is not a multiple of 16 in context. - uint8_t res_data_length = input_length % 16; - memcpy(operation->final_data, input + input_offset + (input_length - res_data_length), res_data_length); - operation->final_data_length = res_data_length; - input_length -= res_data_length; - - // Get ownership. - return_status = cryptoacc_management_acquire(); - if (return_status != PSA_SUCCESS) { - return return_status; - } - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - // CCM multipart finish will hardfault without input data, so we must always save - // some data for the final operation. - if ((operation->processed_len + input_length) == operation->total_length) { - memcpy(operation->final_data, input + (input_length - 16), 16); - operation->final_data_length = 16; - input_length -= operation->final_data_length; - if (!input_length) { - return PSA_SUCCESS; - } - } - - input_block = block_t_convert(input + input_offset, input_length); - output_block = block_t_convert(output, input_length); - - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_ccm_encrypt_update(&key, - &input_block, - &output_block, - &ctx_in_block, - &ctx_out_block); - } else { - sx_ret = sx_aes_ccm_decrypt_update(&key, - &input_block, - &output_block, - &ctx_in_block, - &ctx_out_block); - } - break; - #endif //PSA_WANT_ALG_CCM - #if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - - input_block = block_t_convert(input + input_offset, input_length); - output_block = block_t_convert(output, input_length); - - if (operation->ad_len == 0 && operation->processed_len == 0) { - // Not initialized. - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_gcm_encrypt_init(&key, - &input_block, - &output_block, - &nonce_block, - &ctx_out_block, - &aad_block); - } else { - sx_ret = sx_aes_gcm_decrypt_init(&key, - &input_block, - &output_block, - &nonce_block, - &ctx_out_block, - &aad_block); - } - } else { - if (operation->direction == SLI_AES_ENC) { - sx_ret = sx_aes_gcm_encrypt_update(&key, - &input_block, - &output_block, - &ctx_in_block, - &ctx_out_block); - } else { - sx_ret = sx_aes_gcm_decrypt_update(&key, - &input_block, - &output_block, - &ctx_in_block, - &ctx_out_block); - } - } - break; - #endif //PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - // Release ownership. - return_status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *output_length += input_length; - operation->processed_len += input_length; - return return_status; - - #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - (void)operation; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - return PSA_ERROR_NOT_SUPPORTED; - #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (ciphertext_size < operation->final_data_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); - - if (tag_size < tag_len) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - block_t key = block_t_convert(operation->key, operation->key_len); - - uint8_t tagbuf[16]; - block_t tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - - psa_algorithm_t alg = operation->alg; - - if (operation->direction != SLI_AES_ENC) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->ad_len == 0 && operation->processed_len == 0) { - // Operation is not initialized. - - block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); - block_t data_in = NULL_blk; - block_t data_out = NULL_blk; - block_t aad_block = NULL_blk; - - // Get ownership. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - tag_block = block_t_convert(tagbuf, tag_len); - sx_ret = sx_aes_ccm_encrypt(&key, - &data_in, - &data_out, - &nonce_block, - &tag_block, - &aad_block); - *ciphertext_length = 0; - break; - } - #endif //PSA_WANT_ALG_CCM - #if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - data_in = block_t_convert(operation->final_data, operation->final_data_length); - data_out = block_t_convert(ciphertext, operation->final_data_length); - sx_ret = sx_aes_gcm_encrypt(&key, - &data_in, - &data_out, - &nonce_block, - &tag_block, - &aad_block); - *ciphertext_length = operation->final_data_length; - break; - } - #endif //PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - // Release ownership. - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS ) { - *ciphertext_length = 0; - return PSA_ERROR_HARDWARE_FAILURE; - } - memcpy(tag, tagbuf, tag_len); - return PSA_SUCCESS; - } - - #if defined(PSA_WANT_ALG_GCM) - uint32_t lena_lenc[4]; - lena_lenc[0] = __REV(operation->ad_len >> 29); - lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); - lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); - lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); - - block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); - #endif - - block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); - - block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); - block_t data_out_block = block_t_convert(ciphertext, operation->final_data_length); - - // Get ownership. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - if (operation->ad_len != 0 && operation->total_length == 0) { - // Tag is calculated in update_ad. - memcpy(tag, operation->ctx.tag_buf, tag_len); - return PSA_SUCCESS; - } - - sx_ret = sx_aes_ccm_encrypt_final( - &key, - &data_in_block, - &data_out_block, - &ctx_in_block, - &tag_block); - break; - } - #endif //PSA_WANT_ALG_CCM - #if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - sx_ret = sx_aes_gcm_encrypt_final( - &key, - &data_in_block, - &data_out_block, - &ctx_in_block, - &tag_block, - &len_a_c); - break; - } - #endif //PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - // Release ownership. - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - memcpy(tag, tagbuf, tag_size); - *ciphertext_length = operation->final_data_length; - *tag_length = tag_len; - return status; - - #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - (void)operation; - (void)ciphertext; - (void)ciphertext_size; - (void)ciphertext_length; - (void)tag; - (void)tag_size; - (void)tag_length; - return PSA_ERROR_NOT_SUPPORTED; - #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM) -} - -psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length) -{ - #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) - - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (tag == NULL || tag_length == 0 ) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - if (plaintext_size < operation->final_data_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - block_t key = block_t_convert(operation->key, operation->key_len); - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - - psa_algorithm_t alg = operation->alg; - if (operation->direction != SLI_AES_DEC) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->ad_len == 0 && operation->processed_len == 0) { - // Operation is not initialized. - block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); - block_t aad_block = NULL_blk; - block_t data_in = NULL_blk; - block_t data_out = NULL_blk; - // Get ownership. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - block_t tag_block = block_t_convert(tag, tag_length); - sx_ret = sx_aes_ccm_decrypt_verify(&key, - &data_in, - &data_out, - &nonce_block, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - *plaintext_length = 0; - break; - } - #endif//PSA_WANT_ALG_CCM - #if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - block_t tag_block = block_t_convert(tag, tag_length); - - data_in = block_t_convert(operation->final_data, operation->final_data_length); - data_out = block_t_convert(plaintext, operation->final_data_length); - - sx_ret = sx_aes_gcm_decrypt_verify(&key, - &data_in, - &data_out, - &nonce_block, - &tag_block, - &aad_block); - status = cryptoacc_management_release(); - if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { - return PSA_ERROR_INVALID_SIGNATURE; - } - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *plaintext_length = operation->final_data_length; - break; - } - #endif//PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; - } - - #if defined(PSA_WANT_ALG_GCM) - uint32_t lena_lenc[4]; - lena_lenc[0] = __REV(operation->ad_len >> 29); - lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); - lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); - lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); - block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); - #endif - - block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); - block_t tag_block = block_t_convert(tag, tag_length); - - block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); - block_t data_out_block = block_t_convert(plaintext, operation->final_data_length); - - // Get ownership. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { - #if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - { - uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); - if (tag_length != tag_len) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - sx_ret = sx_aes_ccm_decrypt_verify_final( - &key, - &data_in_block, - &data_out_block, - &ctx_in_block, - &tag_block); - break; - } - #endif//PSA_WANT_ALG_CCM - #if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - { - sx_ret = sx_aes_gcm_decrypt_verify_final( - &key, - &data_in_block, - &data_out_block, - &ctx_in_block, - &tag_block, - &len_a_c); - break; - } - #endif//PSA_WANT_ALG_GCM - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // Release ownership. - status = cryptoacc_management_release(); - - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { - return PSA_ERROR_INVALID_SIGNATURE; - } - if (sx_ret != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *plaintext_length = operation->final_data_length; - - return PSA_SUCCESS; - - #else//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM - (void)operation; - (void)plaintext; - (void)plaintext_size; - (void)plaintext_length; - (void)tag; - (void)tag_length; - return PSA_ERROR_NOT_SUPPORTED; - #endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM -} - -psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation) -{ - // No state is ever left in HW, so zeroing context should do the trick - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memset(operation, 0, sizeof(*operation)); - return PSA_SUCCESS; -} - -#endif // defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver AEAD functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver common +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "sx_aes.h" +#include "sx_errors.h" +#include "cryptolib_types.h" + +#include + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + +static psa_status_t check_aead_parameters(const psa_key_attributes_t *attributes, + psa_algorithm_t alg, + size_t nonce_length, + size_t additional_data_length) +{ + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (tag_length < 4 + || tag_length > 16 + || tag_length % 2 != 0 + || nonce_length < 7 + || nonce_length > 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + // AD are limited to 2^64 bits, so 2^61 bytes. + // We need not check if SIZE_MAX (max of size_t) is less than 2^61 (0x2000000000000000) +#if SIZE_MAX > 0x2000000000000000ull + if (additional_data_length >> 61 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#else // SIZE_MAX > 0x2000000000000000ull + (void) additional_data_length; +#endif // SIZE_MAX > 0x2000000000000000ull + if ((tag_length < 4) || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (nonce_length == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#if !defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + if (nonce_length != AES_IV_GCM_SIZE) { + // Libcryptosoc only supports 12 bytes long IVs. + return PSA_ERROR_NOT_SUPPORTED; + } +#endif // ! SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; +#endif // PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + break; + } + +#if !defined(PSA_WANT_ALG_GCM) + (void) additional_data_length; +#endif // !PSA_WANT_ALG_GCM + + switch (psa_get_key_bits(attributes)) { + case 128: // fallthrough + case 192: // fallthrough + case 256: + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) && defined(PSA_WANT_ALG_GCM) +/* Do GCM in software in case the IV isn't 12 bytes, since that's the only + * thing the accelerator supports. */ +static psa_status_t sli_cryptoacc_software_gcm(const uint8_t* keybuf, + size_t key_length, + const uint8_t* nonce, + size_t nonce_length, + const uint8_t* additional_data, + size_t additional_data_length, + const uint8_t* input, + uint8_t* output, + size_t plaintext_length, + size_t tag_length, + uint8_t* tag, + bool encrypt_ndecrypt) +{ + // Step 1: calculate H = Ek(0) + uint8_t Ek[16] = { 0 }; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key = block_t_convert(keybuf, key_length); + block_t data_in = block_t_convert(Ek, sizeof(Ek)); + block_t data_out = block_t_convert(Ek, sizeof(Ek)); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ecb_encrypt(&key, + &data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Step 2: calculate IV = GHASH(H, {}, IV) + uint8_t iv[16] = { 0 }; + uint64_t HL[16], HH[16]; + + sli_psa_software_ghash_setup(Ek, HL, HH); + + for (size_t i = 0; i < nonce_length; i += 16) { + // Mix in IV + for (size_t j = 0; j < (nonce_length - i > 16 ? 16 : nonce_length - i); j++) { + iv[j] ^= nonce[i + j]; + } + // Update result + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + } + + iv[12] ^= (nonce_length * 8) >> 24; + iv[13] ^= (nonce_length * 8) >> 16; + iv[14] ^= (nonce_length * 8) >> 8; + iv[15] ^= (nonce_length * 8) >> 0; + + sli_psa_software_ghash_multiply(HL, HH, iv, iv); + + // Step 3: Calculate first counter block for tag generation + uint8_t tagbuf[16] = { 0 }; + data_in = block_t_convert(iv, sizeof(iv)); + data_out = block_t_convert(tagbuf, sizeof(tagbuf)); + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ecb_encrypt(&key, + &data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // If we're decrypting, mix in the to-be-checked tag value before transforming + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= tag[i]; + } + } + + // Step 4: increment IV (ripple increment) + for (size_t i = 0; i < 16; i++) { + iv[15 - i]++; + + if (iv[15 - i] != 0) { + break; + } + } + + // Step 5: Accumulate additional data + memset(Ek, 0, sizeof(Ek)); + for (size_t i = 0; i < additional_data_length; i += 16) { + // Mix in additional data as much as we have + for (size_t j = 0; + j < (additional_data_length - i > 16 ? 16 : additional_data_length - i); + j++) { + Ek[j] ^= additional_data[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + + // Step 6: If we're decrypting, accumulate the ciphertext before it gets transformed + if (!encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= input[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 7: transform data using AES-CTR + if (plaintext_length) { + data_in = block_t_convert(input, plaintext_length); + data_out = block_t_convert(output, plaintext_length); + block_t nonce_internal = block_t_convert(iv, sizeof(iv)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ctr_encrypt(&key, + &data_in, + &data_out, + &nonce_internal); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Step 8: If we're encrypting, accumulate the ciphertext now + if (encrypt_ndecrypt) { + for (size_t i = 0; i < plaintext_length; i += 16) { + // Mix in ciphertext + for (size_t j = 0; + j < (plaintext_length - i > 16 ? 16 : plaintext_length - i); + j++) { + Ek[j] ^= output[i + j]; + } + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + } + } + + // Step 9: add len(A) || len(C) block to tag calculation + uint64_t bitlen = additional_data_length * 8; + Ek[0] ^= bitlen >> 56; + Ek[1] ^= bitlen >> 48; + Ek[2] ^= bitlen >> 40; + Ek[3] ^= bitlen >> 32; + Ek[4] ^= bitlen >> 24; + Ek[5] ^= bitlen >> 16; + Ek[6] ^= bitlen >> 8; + Ek[7] ^= bitlen >> 0; + + bitlen = plaintext_length * 8; + Ek[8] ^= bitlen >> 56; + Ek[9] ^= bitlen >> 48; + Ek[10] ^= bitlen >> 40; + Ek[11] ^= bitlen >> 32; + Ek[12] ^= bitlen >> 24; + Ek[13] ^= bitlen >> 16; + Ek[14] ^= bitlen >> 8; + Ek[15] ^= bitlen >> 0; + + sli_psa_software_ghash_multiply(HL, HH, Ek, Ek); + + // Step 10: calculate tag value + for (size_t i = 0; i < tag_length; i++) { + tagbuf[i] ^= Ek[i]; + } + + // Step 11: output tag for encrypt operation, check tag for decrypt + if (encrypt_ndecrypt) { + memcpy(tag, tagbuf, tag_length); + } else { + uint8_t accumulator = 0; + for (size_t i = 0; i < tag_length; i++) { + accumulator |= tagbuf[i]; + } + if (accumulator != 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + } + + return PSA_SUCCESS; +} +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION && PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (ciphertext_size <= plaintext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + size_t tag_length = 0; + psa_status_t psa_status = sli_cryptoacc_transparent_aead_encrypt_tag( + attributes, key_buffer, key_buffer_size, alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, plaintext_length, ciphertext_length, + &ciphertext[plaintext_length], ciphertext_size - plaintext_length, &tag_length); + + if (psa_status == PSA_SUCCESS) { + *ciphertext_length += tag_length; + } + + return psa_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (attributes == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + if (ciphertext_length < tag_length + || ciphertext == NULL + || (tag_length > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Split the tag in its own buffer to avoid potential issues when the + // plaintext buffer extends into the tag area + uint8_t check_tag[16]; + memcpy(check_tag, &ciphertext[ciphertext_length - tag_length], tag_length); + + return sli_cryptoacc_transparent_aead_decrypt_tag( + attributes, key_buffer, key_buffer_size, alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length - tag_length, + check_tag, tag_length, + plaintext, plaintext_size, plaintext_length); +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (key_buffer == NULL + || attributes == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (plaintext == NULL && plaintext_length > 0) + || (plaintext_length > 0 && (ciphertext == NULL || ciphertext_size == 0)) + || ciphertext_length == NULL || tag_length == NULL + || tag_size == 0 || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_bits = psa_get_key_bits(attributes); + *tag_length = PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), + psa_get_key_bits(attributes), + alg); + + // Verify that the driver supports the given parameters. + psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); + if (status != PSA_SUCCESS) { + return status; + } + + // Check input-key size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if ((ciphertext_size < plaintext_length) + || (tag_size < *tag_length)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((ciphertext > plaintext) && (ciphertext < (plaintext + plaintext_length))) { + memmove(ciphertext, plaintext, plaintext_length); + plaintext = ciphertext; + } + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + block_t key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t aad_block = block_t_convert(additional_data, additional_data_length); + block_t nonce_internal = block_t_convert(nonce, nonce_length); + block_t data_in = block_t_convert(plaintext, plaintext_length); + block_t data_out = block_t_convert(ciphertext, plaintext_length); + block_t tag_block = block_t_convert(tag, *tag_length); + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + + // Check length of plaintext. + { + unsigned char q = 16 - 1 - (unsigned char) nonce_length; + if (q < sizeof(plaintext_length) + && plaintext_length >= (1UL << (q * 8))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return_status = PSA_SUCCESS; + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (nonce_length == AES_IV_GCM_SIZE) { + uint8_t tagbuf[16]; + tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_gcm_encrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + // Copy only requested part of computed tag to user output buffer. + memcpy(tag, tagbuf, *tag_length); + return_status = PSA_SUCCESS; + } +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, + ciphertext, + plaintext_length, + *tag_length, + tag, + true); + } +#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + return_status = PSA_ERROR_NOT_SUPPORTED; + } +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; +#endif // PSA_WANT_ALG_GCM + } + + if (return_status == PSA_SUCCESS) { + *ciphertext_length = plaintext_length; + } else { + *ciphertext_length = 0; + *tag_length = 0; + } + + return return_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_tag(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + const uint8_t* tag, + size_t tag_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (attributes == NULL + || key_buffer == NULL + || nonce == NULL + || (additional_data == NULL && additional_data_length > 0) + || (ciphertext == NULL && ciphertext_length > 0) + || (plaintext == NULL && plaintext_size > 0) + || plaintext_length == NULL + || tag == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Verify that the driver supports the given parameters. + size_t key_bits = psa_get_key_bits(attributes); + psa_status_t status = check_aead_parameters(attributes, alg, nonce_length, additional_data_length); + if (status != PSA_SUCCESS) { + return status; + } + + // Check input-key size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (plaintext_size < ciphertext_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((plaintext > ciphertext) && (plaintext < (ciphertext + ciphertext_length))) { + memmove(plaintext, ciphertext, ciphertext_length); + ciphertext = plaintext; + } + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key = NULL_blk; + block_t aad_block = NULL_blk; + block_t tag_block = NULL_blk; + block_t nonce_internal = NULL_blk; + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + + { + // Check length of ciphertext. + unsigned char q = 16 - 1 - (unsigned char) nonce_length; + if (q < sizeof(ciphertext_length) + && ciphertext_length >= (1UL << (q * 8))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + aad_block = block_t_convert(additional_data, additional_data_length); + tag_block = block_t_convert(tag, tag_length); + nonce_internal = block_t_convert(nonce, nonce_length); + data_in = block_t_convert(ciphertext, ciphertext_length); + data_out = block_t_convert(plaintext, ciphertext_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_ccm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return_status = PSA_ERROR_INVALID_SIGNATURE; + } else if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + *plaintext_length = ciphertext_length; + return_status = PSA_SUCCESS; + } + break; +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + uint8_t tagbuf[16]; + uint32_t diff = 0; + + if (nonce_length == AES_IV_GCM_SIZE) { + key = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + aad_block = block_t_convert(additional_data, additional_data_length); + tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + nonce_internal = block_t_convert(nonce, nonce_length); + data_in = block_t_convert(ciphertext, ciphertext_length); + data_out = block_t_convert(plaintext, ciphertext_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_aes_gcm_decrypt(&key, + &data_in, + &data_out, + &nonce_internal, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return_status = PSA_ERROR_HARDWARE_FAILURE; + } else { + // Check that the provided tag equals the calculated one + // (in constant time). Note that the tag returned by ccm_auth_crypt + // is encrypted, so we don't have to decrypt the tag. + diff = sli_psa_safer_memcmp(tag, tagbuf, tag_length); + sli_psa_zeroize(tagbuf, tag_length); + + if (diff != 0) { + return_status = PSA_ERROR_INVALID_SIGNATURE; + } else { + *plaintext_length = ciphertext_length; + return_status = PSA_SUCCESS; + } + + break; + } + } +#if defined(SLI_PSA_SUPPORT_GCM_IV_CALCULATION) + else { + return_status = sli_cryptoacc_software_gcm(key_buffer, PSA_BITS_TO_BYTES(key_bits), + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, + plaintext, + ciphertext_length, + tag_length, + (uint8_t*)tag, + false); + if (return_status == PSA_SUCCESS) { + *plaintext_length = ciphertext_length; + } + } +#else // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + else { + return_status = PSA_ERROR_NOT_SUPPORTED; + } +#endif // SLI_PSA_SUPPORT_GCM_IV_CALCULATION + break; + } +#endif // PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (return_status != PSA_SUCCESS) { + *plaintext_length = 0; + sli_psa_zeroize(plaintext, plaintext_size); + } + + return return_status; + +#else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)nonce; + (void)nonce_length; + (void)additional_data; + (void)additional_data_length; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)ciphertext; + (void)ciphertext_length; + (void)tag; + (void)tag_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) +static psa_status_t transparent_aead_encrypt_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + sli_aes_mode_t operation_direction) +{ + if (operation == NULL + || attributes == NULL + || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + + size_t key_bits = psa_get_key_bits(attributes); + size_t key_size = PSA_BITS_TO_BYTES(key_bits); + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (sizeof(operation->key) < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Validate key type. + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Validate tag length. + if ( PSA_AEAD_TAG_LENGTH(psa_get_key_type(attributes), key_bits, alg) > 16 ) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Validate operation. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined (PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + operation->alg = alg; + break; + } + #endif + #if defined (PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + operation->alg = alg; + break; + } + #endif + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + memcpy(operation->key, key_buffer, key_size); + operation->key_len = key_size; + + operation->direction = operation_direction; + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_encrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_ENC); + + #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_decrypt_setup(sli_cryptoacc_transparent_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + return transparent_aead_encrypt_decrypt_setup(operation, attributes, key_buffer, key_buffer_size, alg, SLI_AES_DEC); + + #else // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + return PSA_ERROR_NOT_SUPPORTED; + #endif // PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_set_nonce(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_size) +{ +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL || nonce == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Not able to set nonce twice. + if (operation->ctx.preinit.nonce_length != 0) { + return PSA_ERROR_BAD_STATE; + } + + if (nonce_size > sizeof(operation->ctx.preinit.nonce)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Validate operation. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + if (nonce_size != 12) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + } +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + if (nonce_size < 7 || nonce_size > 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + } +#endif + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + memcpy(operation->ctx.preinit.nonce, nonce, nonce_size); + operation->ctx.preinit.nonce_length = nonce_size; + return PSA_SUCCESS; + +#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)nonce; + (void)nonce_size; + return PSA_ERROR_NOT_SUPPORTED; +#endif +} + +psa_status_t sli_cryptoacc_transparent_aead_set_lengths(sli_cryptoacc_transparent_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + (void)ad_length; + + // Check if operation has already started + if (operation->ad_len != 0 || operation->processed_len != 0) { + return PSA_ERROR_BAD_STATE; + } + + // To pass current PSA Crypto test suite, tag length encoded in the + // algorithm needs to be checked at this point. + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(operation->alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + if ((PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) % 2 != 0) + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->total_length = plaintext_length; + + break; +#endif +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + (void)plaintext_length; + if (PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) < 4 + || PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg) > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif + default: + return PSA_ERROR_BAD_STATE; + } + + return PSA_SUCCESS; + #else//PSA_WANT_ALG_CCM + (void)operation; + (void)ad_length; + (void)plaintext_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif//PSA_WANT_ALG_CCM +} + +#if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) +static psa_status_t cryptoacc_aead_start(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + + block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t key = block_t_convert(operation->key, operation->key_len); + block_t aad_block = block_t_convert(input, input_length); + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + + // Get ownership. + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + uint32_t tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + if (operation->direction == SLI_AES_ENC) { + // CCM finish must have input data, in the case of pt_len = 0 and aad_len != 0 we + // need to precompute the tag. (Only needed for encrypt) + if (operation->total_length == 0 && input_length != 0) { + block_t tag_block = block_t_convert(operation->ctx.tag_buf, tag_length); + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + + goto exit; + } else { + sx_ret = sx_aes_ccm_encrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } + } else { + sx_ret = sx_aes_ccm_decrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block, + tag_length, + operation->total_length); + } + break; + } +#endif//PSA_WANT_ALG_CCM +#if defined (PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &data_in, + &data_out, + &nonce_block, + &ctx_out_block, + &aad_block); + } + goto exit; + break; +#endif//PSA_WANT_ALG_GCM + } + + exit: + + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + operation->ad_len += input_length; + return PSA_SUCCESS; +} +#endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + +psa_status_t sli_cryptoacc_transparent_aead_update_ad(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->ad_len > 0 || operation->processed_len > 0) { + return PSA_ERROR_BAD_STATE; + } + + // No additional data. + if (input_length == 0) { + return PSA_SUCCESS; + } + + return cryptoacc_aead_start(operation, input, input_length); +#else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + + (void)operation; + (void)input; + (void)input_length; + return PSA_ERROR_NOT_SUPPORTED; +#endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_update(sli_cryptoacc_transparent_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (operation == NULL + || ((input == NULL || output == NULL) && input_length > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Check variable overflow + if (operation->processed_len > 0xFFFFFFFF - input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + *output_length = 0; + + if (input_length == 0) { + return PSA_SUCCESS; + } + + psa_algorithm_t alg = operation->alg; + + psa_status_t return_status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + block_t key = block_t_convert(operation->key, operation->key_len); + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + block_t ctx_out_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t input_block = block_t_convert(input, input_length); + block_t output_block = block_t_convert(output, input_length); + + // The extra logic is to support non-blocksize input data. + + // Store data in context if there is space in the data buffer. + if ((input_length + operation->final_data_length) < 16 && input_length < 16) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(operation->final_data + operation->final_data_length, input, input_length); + operation->final_data_length += input_length; + return PSA_SUCCESS; + } + + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->ad_len == 0 && operation->processed_len == 0) { + cryptoacc_aead_start(operation, NULL, 0); + } + } + + uint8_t input_offset = 0; + +#if defined(PSA_WANT_ALG_GCM) + block_t aad_block = NULL_blk; + block_t nonce_block = NULL_blk; + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + } +#endif + + if (operation->final_data_length) { + if (operation->final_data_length > 16) { + // Invalid context. + return PSA_ERROR_INVALID_ARGUMENT; + } + + // If there is data stored in context: fill final_data buffer and process it first. + input_offset = 16 - operation->final_data_length; + memcpy(operation->final_data + operation->final_data_length, input, input_offset); + +#if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->processed_len + 16 == operation->total_length) { + operation->final_data_length = 16; + return PSA_SUCCESS; + } + } +#endif + + block_t input_block_final = block_t_convert(operation->final_data, 16); + block_t output_block_final = block_t_convert(output, 16); + + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + #if defined(PSA_WANT_ALG_GCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0)) { + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Not initialized. + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &input_block_final, + &output_block_final, + &nonce_block, + &ctx_out_block, + &aad_block); + } + } else { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_gcm_decrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } + } + } + #endif //PSA_WANT_ALG_GCM + + #if defined(PSA_WANT_ALG_CCM) + if (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0) == PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0)) { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_ccm_decrypt_update(&key, + &input_block_final, + &output_block_final, + &ctx_in_block, + &ctx_out_block); + } + } + #endif //PSA_WANT_ALG_CCM + + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + operation->final_data_length = 0; + input_length -= input_offset; + operation->processed_len += 16; + output += 16; + *output_length += 16; + } + + // Store data in context if there is space in the data buffer. + if (input_length < 16 && !operation->final_data_length && input_length < 16) { + memcpy(operation->final_data, input + input_offset, input_length); + operation->final_data_length = input_length; + return PSA_SUCCESS; + } + + // Store data that is not a multiple of 16 in context. + uint8_t res_data_length = input_length % 16; + memcpy(operation->final_data, input + input_offset + (input_length - res_data_length), res_data_length); + operation->final_data_length = res_data_length; + input_length -= res_data_length; + + // Get ownership. + return_status = cryptoacc_management_acquire(); + if (return_status != PSA_SUCCESS) { + return return_status; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + // CCM multipart finish will hardfault without input data, so we must always save + // some data for the final operation. + if ((operation->processed_len + input_length) == operation->total_length) { + memcpy(operation->final_data, input + (input_length - 16), 16); + operation->final_data_length = 16; + input_length -= operation->final_data_length; + if (!input_length) { + return PSA_SUCCESS; + } + } + + input_block = block_t_convert(input + input_offset, input_length); + output_block = block_t_convert(output, input_length); + + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_ccm_encrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_ccm_decrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } + break; + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + + input_block = block_t_convert(input + input_offset, input_length); + output_block = block_t_convert(output, input_length); + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Not initialized. + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_init(&key, + &input_block, + &output_block, + &nonce_block, + &ctx_out_block, + &aad_block); + } else { + sx_ret = sx_aes_gcm_decrypt_init(&key, + &input_block, + &output_block, + &nonce_block, + &ctx_out_block, + &aad_block); + } + } else { + if (operation->direction == SLI_AES_ENC) { + sx_ret = sx_aes_gcm_encrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } else { + sx_ret = sx_aes_gcm_decrypt_update(&key, + &input_block, + &output_block, + &ctx_in_block, + &ctx_out_block); + } + } + break; + #endif //PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + return_status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || return_status != PSA_SUCCESS ) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length += input_length; + operation->processed_len += input_length; + return return_status; + + #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_finish(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (ciphertext_size < operation->final_data_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + + if (tag_size < tag_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t key = block_t_convert(operation->key, operation->key_len); + + uint8_t tagbuf[16]; + block_t tag_block = block_t_convert(tagbuf, sizeof(tagbuf)); + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + + if (operation->direction != SLI_AES_ENC) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + block_t aad_block = NULL_blk; + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + tag_block = block_t_convert(tagbuf, tag_len); + sx_ret = sx_aes_ccm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + *ciphertext_length = 0; + break; + } + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + data_in = block_t_convert(operation->final_data, operation->final_data_length); + data_out = block_t_convert(ciphertext, operation->final_data_length); + sx_ret = sx_aes_gcm_encrypt(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + *ciphertext_length = operation->final_data_length; + break; + } + #endif //PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS ) { + *ciphertext_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + memcpy(tag, tagbuf, tag_len); + return PSA_SUCCESS; + } + + #if defined(PSA_WANT_ALG_GCM) + uint32_t lena_lenc[4]; + lena_lenc[0] = __REV(operation->ad_len >> 29); + lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); + lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); + lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); + + block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); + #endif + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + + block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); + block_t data_out_block = block_t_convert(ciphertext, operation->final_data_length); + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + if (operation->ad_len != 0 && operation->total_length == 0) { + // Tag is calculated in update_ad. + memcpy(tag, operation->ctx.tag_buf, tag_len); + return PSA_SUCCESS; + } + + sx_ret = sx_aes_ccm_encrypt_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block); + break; + } + #endif //PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + sx_ret = sx_aes_gcm_encrypt_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block, + &len_a_c); + break; + } + #endif //PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + // Release ownership. + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + memcpy(tag, tagbuf, tag_size); + *ciphertext_length = operation->final_data_length; + *tag_length = tag_len; + return status; + + #else //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif //PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM) +} + +psa_status_t sli_cryptoacc_transparent_aead_verify(sli_cryptoacc_transparent_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + #if defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_GCM) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (tag == NULL || tag_length == 0 ) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + if (plaintext_size < operation->final_data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + block_t key = block_t_convert(operation->key, operation->key_len); + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + + psa_algorithm_t alg = operation->alg; + if (operation->direction != SLI_AES_DEC) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->ad_len == 0 && operation->processed_len == 0) { + // Operation is not initialized. + block_t nonce_block = block_t_convert(operation->ctx.preinit.nonce, operation->ctx.preinit.nonce_length); + block_t aad_block = NULL_blk; + block_t data_in = NULL_blk; + block_t data_out = NULL_blk; + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + block_t tag_block = block_t_convert(tag, tag_length); + sx_ret = sx_aes_ccm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + *plaintext_length = 0; + break; + } + #endif//PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + block_t tag_block = block_t_convert(tag, tag_length); + + data_in = block_t_convert(operation->final_data, operation->final_data_length); + data_out = block_t_convert(plaintext, operation->final_data_length); + + sx_ret = sx_aes_gcm_decrypt_verify(&key, + &data_in, + &data_out, + &nonce_block, + &tag_block, + &aad_block); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = operation->final_data_length; + break; + } + #endif//PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + } + + #if defined(PSA_WANT_ALG_GCM) + uint32_t lena_lenc[4]; + lena_lenc[0] = __REV(operation->ad_len >> 29); + lena_lenc[1] = __REV((operation->ad_len << 3) & 0xFFFFFFFFUL); + lena_lenc[2] = __REV((operation->processed_len + operation->final_data_length) >> 29); + lena_lenc[3] = __REV(((operation->processed_len + operation->final_data_length) << 3) & 0xFFFFFFFFUL); + block_t len_a_c = block_t_convert(lena_lenc, sizeof(lena_lenc)); + #endif + + block_t ctx_in_block = block_t_convert(operation->ctx.xcm_ctx, sizeof(operation->ctx.xcm_ctx)); + block_t tag_block = block_t_convert(tag, tag_length); + + block_t data_in_block = block_t_convert(operation->final_data, operation->final_data_length); + block_t data_out_block = block_t_convert(plaintext, operation->final_data_length); + + // Get ownership. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { + #if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + { + uint32_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(operation->alg); + if (tag_length != tag_len) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + sx_ret = sx_aes_ccm_decrypt_verify_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block); + break; + } + #endif//PSA_WANT_ALG_CCM + #if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + { + sx_ret = sx_aes_gcm_decrypt_verify_final( + &key, + &data_in_block, + &data_out_block, + &ctx_in_block, + &tag_block, + &len_a_c); + break; + } + #endif//PSA_WANT_ALG_GCM + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Release ownership. + status = cryptoacc_management_release(); + + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *plaintext_length = operation->final_data_length; + + return PSA_SUCCESS; + + #else//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM + (void)operation; + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)tag; + (void)tag_length; + return PSA_ERROR_NOT_SUPPORTED; + #endif//PSA_WANT_ALG_CCM || PSA_WANT_ALG_GCM +} + +psa_status_t sli_cryptoacc_transparent_aead_abort(sli_cryptoacc_transparent_aead_operation_t *operation) +{ + // No state is ever left in HW, so zeroing context should do the trick + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + return PSA_SUCCESS; +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c index 59eb049..ddf4a88 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c @@ -1,2168 +1,2168 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Cipher functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" -#include "sli_psa_driver_common.h" -#include "cryptoacc_management.h" -// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong -// interface header file when it becomes available. -#include "psa/crypto_platform.h" -#include "psa/crypto_sizes.h" -#include "psa/crypto_struct.h" -#include "psa/crypto_extra.h" -#include "cryptolib_def.h" -#include "sx_errors.h" -#include "sx_aes.h" - -#include - -/** Encrypt a message using a symmetric cipher. - * - * This function encrypts a message with a random IV (initialization - * vector). Use the multipart operation interface with a - * #psa_cipher_operation_t object to provide other forms of IV. - * - * \param handle Handle to the key to use for the operation. - * It must remain valid until the operation - * terminates. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to encrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * The output contains the IV followed by - * the ciphertext proper. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE - * \retval #PSA_ERROR_NOT_PERMITTED - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * \retval #PSA_ERROR_HARDWARE_FAILURE - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * \retval #PSA_ERROR_STORAGE_FAILURE - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *iv, - size_t iv_length, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key; - block_t data_in; - block_t data_out; -#if defined(MBEDTLS_PSA_CRYPTO_C) -#if defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7) - uint8_t tmp_buf[16] = { 0 }; -#endif -#if defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7) - block_t iv_block; -#endif -#endif // MBEDTLS_PSA_CRYPTO_C - // Argument check - if (key_buffer == NULL - || key_buffer_size == 0 - || (input == NULL && input_length > 0) - || (iv == NULL && iv_length > 0) - || (output == NULL && output_size > 0) - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check key type and size. - switch (alg) { - case PSA_ALG_ECB_NO_PADDING: -#if defined(MBEDTLS_PSA_CRYPTO_C) -#if defined(PSA_WANT_ALG_CTR) - case PSA_ALG_CTR: -#endif -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: -#endif -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: -#endif -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: -#endif -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: -#endif -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: -#endif -#endif /* MBEDTLS_PSA_CRYPTO_C */ - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (key_buffer_size < (psa_get_key_bits(attributes) / 8) - || !(psa_get_key_bits(attributes) == 128 - || psa_get_key_bits(attributes) == 192 - || psa_get_key_bits(attributes) == 256)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // 0-length encrypt/decrypt is allowed according to the unit tests in PSA - if (input_length == 0) { - *output_length = 0; - return PSA_SUCCESS; - } - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((output > input) && (output < (input + input_length))) { - // Sanity check before copying. Some ciphers have a stricter requirement - // than this (if an IV is included), but no ciphers will have an output - // smaller than the input. - if (output_size < input_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memmove(output, input, input_length); - input = output; - } - - // Encrypt. - switch (alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: { - // Check buffer sizes. - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // We cannot do ECB on non-block sizes. - if (input_length % 16 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - key = block_t_convert(key_buffer, key_buffer_size); - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(output, input_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(MBEDTLS_PSA_CRYPTO_C) -#if defined(PSA_WANT_KEY_TYPE_AES) && defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: { - // Check buffer sizes. - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - -#if defined(PSA_WANT_ALG_CCM) - if (alg == PSA_ALG_CCM_STAR_NO_TAG) { - if (iv_length != 13) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // AES-CCM*-no-tag is basically AES-CTR with preformatted IV - tmp_buf[0] = 1; - memcpy(&tmp_buf[1], iv, 13); - tmp_buf[14] = 0; - tmp_buf[15] = 1; - iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); - } else -#endif - { - if (iv_length != AES_IV_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - iv_block = block_t_convert(iv, AES_IV_SIZE); - } - - key = block_t_convert(key_buffer, key_buffer_size); - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(output, input_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ctr_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: { - // Check buffer sizes. - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - if (iv_length != AES_IV_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Copy final input bytes before they are overwritten (in case of overlap with output buffer). - memcpy(tmp_buf, input + (input_length / 16) * 16, input_length % 16); - - key = block_t_convert(key_buffer, key_buffer_size); - - size_t input_length_full_blocks = (input_length / 16) * 16; - - // Process full blocks. - if (input_length_full_blocks > 0) { - iv_block = block_t_convert(iv, AES_IV_SIZE); - data_in = block_t_convert(input, input_length_full_blocks); - data_out = block_t_convert(output, - input_length_full_blocks); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process final bytes. - if (input_length % 16 != 0) { - iv_block = block_t_convert(&output[input_length_full_blocks - 16], - AES_IV_SIZE); - data_in = block_t_convert(tmp_buf, 16); - data_out = block_t_convert(tmp_buf, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output + input_length_full_blocks, - tmp_buf, - input_length % 16); - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: { - uint8_t final_block[16]; - - // Check buffer sizes. - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - if (iv_length != AES_IV_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Copy final input bytes before they are overwritten (in case of overlap with output buffer). - memcpy(final_block, input + (input_length / 16) * 16, input_length % 16); - - // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. - memcpy(tmp_buf, iv, AES_IV_SIZE); - - key = block_t_convert(key_buffer, key_buffer_size); - iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); - - size_t input_length_full_blocks = (input_length / 16) * 16; - - // Process full blocks. - if (input_length_full_blocks > 0) { - data_in = block_t_convert(input, input_length_full_blocks); - data_out = block_t_convert(output, input_length_full_blocks); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process leftover bytes. - if (input_length % 16 != 0) { - data_in = block_t_convert(final_block, 16); - data_out = block_t_convert(final_block, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ofb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output + input_length_full_blocks, - final_block, - input_length % 16); - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_NO_PADDING: - // We cannot do CBC without padding on non-block sizes. - if (input_length % 16 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - // fall through - case PSA_ALG_CBC_PKCS7: { - uint8_t final_block[16]; - - // Check buffer sizes. - if (alg == PSA_ALG_CBC_NO_PADDING) { - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - } else { - if (output_size < (input_length & ~0xF) + 16) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - } - - if (iv_length != AES_IV_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. - memcpy(tmp_buf, iv, AES_IV_SIZE); - - key = block_t_convert(key_buffer, key_buffer_size); - iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); - data_in = block_t_convert(input, input_length & ~0xF); - data_out = block_t_convert(output, input_length & ~0xF); - - // Store last block (if non-blocksize input-length) to temporary buffer to be used in padding. - if (alg == PSA_ALG_CBC_PKCS7) { - memcpy(final_block, - &input[input_length & ~0xF], - input_length & 0xF); - } - - if ((input_length & ~0xF) > 0) { - // CBC-encrypt all but the last block. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, - (const block_t *)&data_in, - &data_out, - (const block_t *)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process final block. - if (alg == PSA_ALG_CBC_PKCS7) { - // Add PKCS7 padding. - memset(&final_block[input_length & 0xF], - 16 - (input_length & 0xF), - 16 - (input_length & 0xF)); - - // CBC-encrypt the last block. - data_in = block_t_convert(final_block, 16); - data_out = block_t_convert(final_block, 16); - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, - (const block_t *)&data_in, - &data_out, - (const block_t *)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Copy to output. - memcpy(&output[(input_length & ~0xF)], - final_block, - 16); - - *output_length = (input_length & ~0xF) + 16; - } else { - *output_length = input_length; - } - break; - } -#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING -#endif /* MBEDTLS_PSA_CRYPTO_C */ - default: - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)iv; - (void)iv_length; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)iv; - (void)iv_length; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES -} - -/** Decrypt a message using a symmetric cipher. - * - * This function decrypts a message encrypted with a symmetric cipher. - * - * \param handle Handle to the key to use for the operation. - * It must remain valid until the operation - * terminates. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to decrypt. - * This consists of the IV followed by the - * ciphertext proper. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the plaintext is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE - * \retval #PSA_ERROR_NOT_PERMITTED - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * \retval #PSA_ERROR_HARDWARE_FAILURE - * \retval #PSA_ERROR_STORAGE_FAILURE - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key; - block_t data_in; - block_t data_out; - -#if defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7) - block_t iv_block; -#endif -#if defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7) - uint8_t tmp_buf[16]; -#endif - - // Argument check - if (key_buffer == NULL - || key_buffer_size == 0 - || (input == NULL && input_length > 0) - || (output == NULL && output_size > 0) - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check key type and size. - switch (alg) { - case PSA_ALG_ECB_NO_PADDING: -#if defined(PSA_WANT_ALG_CTR) - case PSA_ALG_CTR: -#endif -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: -#endif -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: -#endif -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: -#endif -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: -#endif -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: -#endif - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (key_buffer_size < (psa_get_key_bits(attributes) / 8) - || !(psa_get_key_bits(attributes) == 128 - || psa_get_key_bits(attributes) == 192 - || psa_get_key_bits(attributes) == 256)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // 0-length encrypt/decrypt is allowed according to the unit tests in Mbed TLS. - if (input_length == 0) { - *output_length = 0; - return PSA_SUCCESS; - } - // Only passing an IV should also be OK (all modes use an IV except ECB). - if ((input_length == AES_IV_SIZE) - && (alg != PSA_ALG_ECB_NO_PADDING)) { - *output_length = 0; - return PSA_SUCCESS; - } - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((output > input) && (output < (input + input_length))) { - // Sanity check before copying. Some ciphers have a stricter requirement - // than this (if an IV is included), but no ciphers will have an output - // smaller than the input. - if (output_size < input_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memmove(output, input, input_length); - input = output; - } - - switch (alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: { - // Check buffer sizes. - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // We cannot do ECB on non-block sizes. - if (input_length % 16 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - key = block_t_convert(key_buffer, key_buffer_size); - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(output, input_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: { - // Check buffer sizes. -#if defined(PSA_WANT_ALG_CCM) - if (alg == PSA_ALG_CCM_STAR_NO_TAG) { - if (output_size < input_length - 13) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // AES-CCM*-no-tag is basically AES-CTR with preformatted IV - tmp_buf[0] = 1; - memcpy(&tmp_buf[1], input, 13); - tmp_buf[14] = 0; - tmp_buf[15] = 1; - iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); - - input += 13; - input_length -= 13; - } else -#endif - { - if (output_size < input_length - AES_IV_SIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - iv_block = block_t_convert(input, AES_IV_SIZE); - - input += AES_IV_SIZE; - input_length -= AES_IV_SIZE; - } - - key = block_t_convert(key_buffer, key_buffer_size); - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(output, input_length); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ctr_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *output_length = input_length; - break; - } -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: { - // Check buffer sizes. - if (output_size < input_length - AES_IV_SIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - key = block_t_convert(key_buffer, key_buffer_size); - - size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; - - // Process full blocks. - if (input_length_full_blocks > 0) { - iv_block = block_t_convert(input, AES_IV_SIZE); - data_in = block_t_convert(input + AES_IV_SIZE, - input_length_full_blocks); - data_out = block_t_convert(output, input_length_full_blocks); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process final bytes. - if (input_length % 16 != 0) { - iv_block = block_t_convert(input + input_length_full_blocks, - AES_IV_SIZE); - data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, - 16); - data_out = block_t_convert(tmp_buf, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output + input_length_full_blocks, - tmp_buf, - input_length % 16); - } - - *output_length = input_length - AES_IV_SIZE; - break; - } -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: { - // Check buffer sizes. - if (output_size < input_length - AES_IV_SIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Move IV into tmp buffer in order to avoid messing up output (in case of overlap with input). - memcpy(tmp_buf, input, AES_IV_SIZE); - - key = block_t_convert(key_buffer, key_buffer_size); - iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); - - size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; - - // Process full blocks. - if (input_length_full_blocks > 0) { - data_in = block_t_convert(input + AES_IV_SIZE, - input_length_full_blocks); - data_out = block_t_convert(output, input_length_full_blocks); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process final bytes. - if (input_length % 16 != 0) { - data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, - 16); - data_out = block_t_convert(tmp_buf, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_ofb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output + input_length_full_blocks, - tmp_buf, - input_length % 16); - } - - *output_length = input_length - AES_IV_SIZE; - break; - } -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_NO_PADDING: - // fall through - case PSA_ALG_CBC_PKCS7: { - size_t input_length_full_blocks; - uint8_t iv_buf[AES_IV_SIZE]; - - // We cannot do CBC decryption on non-block sizes. - if (input_length % 16 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (alg == PSA_ALG_CBC_NO_PADDING) { - if (output_size < input_length - AES_IV_SIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; - } else { - // Check output has enough room for at least n-1 blocks. - if (input_length < AES_IV_SIZE + 16 - || output_size < (input_length - AES_IV_SIZE - 16)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - input_length_full_blocks = ((input_length - AES_IV_SIZE - 16) / 16) * 16; - } - - // Write IV to temporary buf to be used by sx_aes_cbc_decrypt_update. - memcpy(iv_buf, input, AES_IV_SIZE); - key = block_t_convert(key_buffer, key_buffer_size); - iv_block = block_t_convert(iv_buf, AES_IV_SIZE); - - if (input_length_full_blocks > 0) { - data_in = block_t_convert(input + AES_IV_SIZE, - input_length_full_blocks); - data_out = block_t_convert(output, input_length_full_blocks); - - // CBC-decrypt all but the last block. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, - (const block_t *)&data_in, - &data_out, - (const block_t *)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - // Process final block. - if (alg == PSA_ALG_CBC_PKCS7) { - // Store last block to temporary buffer to be used in removing the padding. - memcpy(tmp_buf, &input[input_length - 16], 16); - - data_in = block_t_convert(tmp_buf, 16); - data_out = block_t_convert(tmp_buf, 16); - - // CBC-decrypt the last block. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, - (const block_t *)&data_in, - &data_out, - (const block_t *)&iv_block, - &iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Check all padding bytes. - size_t pad_bytes = 0; - status = sli_psa_validate_pkcs7_padding(tmp_buf, - 16, - &pad_bytes); - if (status != PSA_SUCCESS) { - return status; - } - - if (output_size < (input_length - AES_IV_SIZE - pad_bytes)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Copy non-padding bytes. - memcpy(&output[input_length_full_blocks], tmp_buf, 16 - pad_bytes); - - *output_length = input_length - AES_IV_SIZE - pad_bytes; - } else { - *output_length = input_length - AES_IV_SIZE; - } - break; - } -#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES -} - -psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - if (operation == NULL || attributes == NULL || key_buffer == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Reset context. - memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); - - // Set up context. - memcpy(&operation->alg, &alg, sizeof(alg)); - operation->direction = SLI_AES_ENC; - - // Validate combination of key and algorithm. - switch (alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CTR) - case PSA_ALG_CTR: -#endif // PSA_WANT_ALG_CTR -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: -#endif // PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: -#endif // PSA_WANT_ALG_CBC_PKCS7 - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // Copy key into context. - switch (psa_get_key_bits(attributes)) { - case 128: - if (key_buffer_size < 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 16); - operation->key_len = 16; - break; - case 192: - if (key_buffer_size < 24) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 24); - operation->key_len = 24; - break; - case 256: - if (key_buffer_size < 32) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 32); - operation->key_len = 32; - break; - default: - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES - - (void)operation; - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES -} - -psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - if (operation == NULL || attributes == NULL || key_buffer == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Reset context. - memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); - - // Set up context. - memcpy(&operation->alg, &alg, sizeof(alg)); - operation->direction = SLI_AES_DEC; - - // Validate combination of key and algorithm. - switch (alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CTR) - case PSA_ALG_CTR: -#endif // PSA_WANT_ALG_CTR -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: -#endif // PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: -#endif // PSA_WANT_ALG_CBC_PKCS7 - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // Copy key into context. - switch (psa_get_key_bits(attributes)) { - case 128: - if (key_buffer_size < 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 16); - operation->key_len = 16; - break; - case 192: - if (key_buffer_size < 24) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 24); - operation->key_len = 24; - break; - case 256: - if (key_buffer_size < 32) { - return PSA_ERROR_INVALID_ARGUMENT; - } - memcpy(operation->key, key_buffer, 32); - operation->key_len = 32; - break; - default: - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES - - (void)operation; - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES -} - -psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - if (operation == NULL || iv == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (iv_length > sizeof(operation->iv)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->iv_len != 0) { - // IV was set previously. - return PSA_ERROR_BAD_STATE; - } - - if (operation->key_len == 0) { - // context hasn't been properly initialised. - return PSA_ERROR_BAD_STATE; - } - -#if defined(PSA_WANT_ALG_CCM) - if (operation->alg == PSA_ALG_CCM_STAR_NO_TAG) { - // Preformat the IV for CCM*-no-tag here, such that the remainder - // of the processing for this algorithm boils down to AES-CTR - if (iv_length != 13) { - return PSA_ERROR_INVALID_ARGUMENT; - } - operation->iv[0] = 1; - memcpy(&operation->iv[1], iv, iv_length); - operation->iv[14] = 0; - operation->iv[15] = 1; - operation->iv_len = 16; - } else -#endif // PSA_WANT_ALG_CCM - if (operation->alg != PSA_ALG_ECB_NO_PADDING) { - if (iv_length != 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - operation->iv_len = iv_length; - memcpy(operation->iv, iv, iv_length); - } else { - if (iv_length > 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES - - (void)operation; - (void)iv; - (void)iv_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES -} - -psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key; - block_t data_in; - block_t data_out; - - // Argument check. - if (operation == NULL - || (input == NULL && input_length > 0) - || (output == NULL && output_size > 0) - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check if IV has been set. - if ((operation->alg != PSA_ALG_ECB_NO_PADDING) - && (operation->iv_len == 0)) { - return PSA_ERROR_BAD_STATE; - } - -#if defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) - uint8_t tmp_buf[16]; - block_t tmp_iv_block = block_t_convert(tmp_buf, 16); -#endif -#if defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7) - block_t iv_block = block_t_convert(operation->iv, operation->iv_len); -#endif - - // Figure out whether the operation is on a lagging or forward-looking cipher - // Lagging: needs a full block of input data before being able to output - // Non-lagging: can output the same amount of data as getting fed - bool lagging = true; - switch (operation->alg) { - case PSA_ALG_ECB_NO_PADDING: - case PSA_ALG_CBC_NO_PADDING: - case PSA_ALG_CBC_PKCS7: - lagging = true; - break; - case PSA_ALG_CTR: - case PSA_ALG_CCM_STAR_NO_TAG: - case PSA_ALG_CFB: - case PSA_ALG_OFB: - lagging = false; - break; - default: - return PSA_ERROR_BAD_STATE; - } - - size_t bytes_to_boundary = 16 - (operation->processed_length % 16); - size_t actual_output_length = 0; - *output_length = 0; - - if ( input_length == 0 ) { - return PSA_SUCCESS; - } - - // We need to cache (not return) the whole last block for decryption with - // padding, otherwise it won't be possible to remove a potential padding block - // during finish. - bool cache_full_block = (operation->alg == PSA_ALG_CBC_PKCS7 - && operation->direction == SLI_AES_DEC); - - // Early processing if not getting to a full block for lagging ciphers. - if (lagging) { - if (cache_full_block - && bytes_to_boundary == 16 - && operation->processed_length > 0) { - // Don't overwrite the streaming block yet if it's currently full. - } else if (input_length < bytes_to_boundary) { - memcpy(&operation->streaming_block[operation->processed_length % 16], - input, - input_length); - operation->processed_length += input_length; - *output_length = actual_output_length; - return PSA_SUCCESS; - } - - // We know we'll be computing at least the completed streaming block - size_t output_blocks = 1; - if (input_length > bytes_to_boundary) { - // plus however many full blocks are left over after filling the stream buffer - output_blocks += (input_length - bytes_to_boundary) / 16; - // If we're caching and the sum of already-input and to-be-input data - // ends up at a block boundary, we won't be outputting the last block - if (cache_full_block && ((input_length - bytes_to_boundary) % 16 == 0)) { - output_blocks -= 1; - } - } - - if (output_size < (output_blocks * 16)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - } else { - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - } - - // Our drivers only support full or no overlap between input and output - // buffers. So in the case of partial overlap, copy the input buffer into - // the output buffer and process it in place as if the buffers fully - // overlapped. - if ((output > input) && (output < (input + input_length))) { - // Sanity check before copying. Some ciphers have a stricter requirement - // than this (if an IV is included), but no ciphers will have an output - // smaller than the input. - if (output_size < input_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memmove(output, input, input_length); - input = output; - } - - key = block_t_convert(operation->key, operation->key_len); - - if (bytes_to_boundary != 16) { - // Read in up to full streaming input block. - memcpy(&operation->streaming_block[operation->processed_length % 16], - input, - bytes_to_boundary); - - data_in = block_t_convert(operation->streaming_block, 16); - data_out = block_t_convert(operation->streaming_block, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (operation->direction == SLI_AES_ENC) { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: - sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - break; -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: - sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: - if (cache_full_block && (bytes_to_boundary == input_length)) { - // Don't process the streaming block if there is no more input data - sx_ret = CRYPTOLIB_SUCCESS; - } else { - sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - } - break; -#endif // PSA_WANT_ALG_CBC_PKCS7 - default: - return PSA_ERROR_BAD_STATE; - } - } else { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: - sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - break; -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: - sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: - if (cache_full_block && (bytes_to_boundary == input_length)) { - // Don't process the streaming block if there is no more input data - sx_ret = CRYPTOLIB_SUCCESS; - } else { - sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - } - break; -#endif // PSA_WANT_ALG_CBC_PKCS7 - default: - return PSA_ERROR_BAD_STATE; - } - } - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - if (lagging) { - memcpy(output, operation->streaming_block, 16); - // Don't increase output if no encryption/decryption was done - if (!(cache_full_block && (bytes_to_boundary == input_length))) { - output += 16; - actual_output_length += 16; - } - operation->processed_length += bytes_to_boundary; - input += bytes_to_boundary; - input_length -= bytes_to_boundary; - } else { - if (input_length < bytes_to_boundary) { - bytes_to_boundary = input_length; - } - - memcpy(output, operation->streaming_block + (operation->processed_length % 16), bytes_to_boundary); - output += bytes_to_boundary; - actual_output_length += bytes_to_boundary; - operation->processed_length += bytes_to_boundary; - input += bytes_to_boundary; - input_length -= bytes_to_boundary; - -#if defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) - // Only want to update IV if we actually finished an entire block. - if (operation->processed_length % 16 == 0) { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - if (operation->direction == SLI_AES_ENC) { - memcpy(operation->iv, output - 16, 16); - } else { - memcpy(operation->iv, input - 16, 16); - } - break; -#endif -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_OFB) - case PSA_ALG_CTR: - case PSA_ALG_CCM_STAR_NO_TAG: - case PSA_ALG_OFB: - memcpy(operation->iv, tmp_buf, 16); - break; -#endif - } - } -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB - } - } -#if defined(PSA_WANT_ALG_CBC_PKCS7) - else if (cache_full_block && operation->processed_length > 0) { - // We know there's processing to be done, and that we haven't processed - // the full block in the streaming buffer yet. Process it now. - data_in = block_t_convert(operation->streaming_block, 16); - data_out = block_t_convert(operation->streaming_block, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output, operation->streaming_block, 16); - output += 16; - actual_output_length += 16; - } -#endif - - // Do multi-block operation if applicable. - if (input_length >= 16) { - size_t operation_size = (input_length / 16) * 16; - - if (cache_full_block && (input_length % 16 == 0)) { - // Don't decrypt the last block until finish is called, so that we - // can properly remove the padding before returning it. - operation_size -= 16; - } - - if (operation_size > 0) { - data_in = block_t_convert(input, operation_size); - data_out = block_t_convert(output, operation_size); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - if (operation->direction == SLI_AES_ENC) { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: - sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - break; -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_NO_PADDING: - // fall through - case PSA_ALG_CBC_PKCS7: - sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 - default: - return PSA_ERROR_BAD_STATE; - } - } else { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: - sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, - (const block_t*)&data_in, - &data_out); - break; -#endif // PSA_WANT_ALG_ECB_NO_PADDING -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_OFB -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) - case PSA_ALG_CBC_NO_PADDING: - // fall through - case PSA_ALG_CBC_PKCS7: - sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &iv_block); - break; -#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 - default: - return PSA_ERROR_BAD_STATE; - } - } - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } - - input += operation_size; - input_length -= operation_size; - actual_output_length += operation_size; - output += operation_size; - operation->processed_length += operation_size; - } - - // Process final block. - if (input_length > 0) { - if (!lagging) { -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) - data_in = block_t_convert(input, 16); - data_out = block_t_convert(operation->streaming_block, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (operation->direction == SLI_AES_ENC) { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_OFB - default: - return PSA_ERROR_BAD_STATE; - } - } else { - switch (operation->alg) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM_STAR_NO_TAG: - // Explicit fallthrough -#endif // PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CTR: - sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM -#if defined(PSA_WANT_ALG_CFB) - case PSA_ALG_CFB: - sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_CFB -#if defined(PSA_WANT_ALG_OFB) - case PSA_ALG_OFB: - sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, - (const block_t*)&data_in, - &data_out, - (const block_t*)&iv_block, - &tmp_iv_block); - break; -#endif // PSA_WANT_ALG_OFB - default: - return PSA_ERROR_BAD_STATE; - } - } - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - memcpy(output, - operation->streaming_block, - input_length); - - actual_output_length += input_length; - operation->processed_length += input_length; -#else - return PSA_ERROR_BAD_STATE; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB - } else { - if ((input_length >= 16 && !cache_full_block) - || (input_length > 16 && cache_full_block)) { - *output_length = 0; - return PSA_ERROR_BAD_STATE; - } - memcpy(operation->streaming_block, - input, - input_length); - operation->processed_length += input_length; - } - } - - *output_length = actual_output_length; - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES - - (void)operation; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES -} - -psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - -#if defined(PSA_WANT_ALG_CBC_PKCS7) - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t key; - block_t iv_block; - block_t data_in; - block_t data_out; -#endif // PSA_WANT_ALG_CBC_PKCS7 - - // Argument check. - if (operation == NULL) { - *output_length = 0; - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) || defined(PSA_WANT_ALG_CBC_NO_PADDING) - // Blocksize-only modes without padding. - case PSA_ALG_ECB_NO_PADDING: - case PSA_ALG_CBC_NO_PADDING: - // Can't finish if they haven't processed block-size input. - if (operation->processed_length % 16 != 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - } else { - status = PSA_SUCCESS; - } - *output_length = 0; - break; -#endif // PSA_WANT_ALG_ECB_NO_PADDING || PSA_WANT_ALG_CBC_NO_PADDING -#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) - // Stream cipher modes. - case PSA_ALG_CTR: - case PSA_ALG_CCM_STAR_NO_TAG: - case PSA_ALG_CFB: - case PSA_ALG_OFB: - status = PSA_SUCCESS; - *output_length = 0; - break; -#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_*FB -#if defined(PSA_WANT_ALG_CBC_PKCS7) - // Padding mode. - case PSA_ALG_CBC_PKCS7: - if ((output == NULL && output_size > 0) - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - key = block_t_convert(operation->key, operation->key_len); - iv_block = block_t_convert(operation->iv, operation->iv_len); - data_in = block_t_convert(operation->streaming_block, 16); - data_out = block_t_convert(output, 16); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - if (operation->direction == SLI_AES_ENC) { - if (output_size < 16) { - status = cryptoacc_management_release(); - if (status == PSA_SUCCESS) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - } - break; - } - size_t padding_bytes = 16 - (operation->processed_length % 16); - memset(&operation->streaming_block[16 - padding_bytes], - padding_bytes, - padding_bytes); - - sx_ret = sx_aes_cbc_encrypt((const block_t *)&key, - (const block_t *)&data_in, - &data_out, - (const block_t *)&iv_block); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - status = PSA_ERROR_HARDWARE_FAILURE; - } else { - *output_length = 16; - status = PSA_SUCCESS; - } - } else { - // Expect full-block input. - if (operation->processed_length % 16 != 0 - || operation->processed_length < 16) { - status = PSA_ERROR_INVALID_ARGUMENT; - break; - } - - uint8_t out_buf[16]; - block_t out_buf_block = block_t_convert(&out_buf, 16); - - // Decrypt the last block - sx_ret = sx_aes_cbc_decrypt((const block_t *)&key, - (const block_t *)&data_in, - &out_buf_block, - (const block_t *)&iv_block); - - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - status = PSA_ERROR_HARDWARE_FAILURE; - break; - } - - size_t padding_bytes = 0; - status = sli_psa_validate_pkcs7_padding(out_buf, - 16, - &padding_bytes); - - if (status == PSA_SUCCESS) { - // The padding was valid. - if (output_size < 16 - padding_bytes) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - break; - } - memcpy(output, out_buf, 16 - padding_bytes); - *output_length = 16 - padding_bytes; - } - } - break; -#endif // PSA_WANT_ALG_CBC_PKCS7 - default: - status = PSA_ERROR_BAD_STATE; - break; - } - -#if !defined(PSA_WANT_ALG_CBC_PKCS7) - (void)output; - (void)output_size; -#endif // PSA_WANT_ALG_CBC_PKCS7 - - if (status != PSA_SUCCESS) { - *output_length = 0; - } - - // Wipe context. - memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); - - return status; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* - - (void)operation; - (void)output; - (void)output_size; - (void)output_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* -} - -psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation) -{ -#if (defined(PSA_WANT_KEY_TYPE_AES) \ - && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ - || defined(PSA_WANT_ALG_CTR) \ - || defined(PSA_WANT_ALG_CCM) \ - || defined(PSA_WANT_ALG_CFB) \ - || defined(PSA_WANT_ALG_OFB) \ - || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ - || defined(PSA_WANT_ALG_CBC_PKCS7))) - - if (operation != NULL) { - // Wipe context. - memset(operation, 0, sizeof(*operation)); - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES - - (void)operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES -} - -#endif // defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Cipher functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "psa/crypto_extra.h" +#include "cryptolib_def.h" +#include "sx_errors.h" +#include "sx_aes.h" + +#include + +/** Encrypt a message using a symmetric cipher. + * + * This function encrypts a message with a random IV (initialization + * vector). Use the multipart operation interface with a + * #psa_cipher_operation_t object to provide other forms of IV. + * + * \param handle Handle to the key to use for the operation. + * It must remain valid until the operation + * terminates. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to encrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * The output contains the IV followed by + * the ciphertext proper. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p handle is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sli_cryptoacc_transparent_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + uint8_t tmp_buf[16] = { 0 }; +#endif +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block; +#endif +#endif // MBEDTLS_PSA_CRYPTO_C + // Argument check + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (iv == NULL && iv_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check key type and size. + switch (alg) { + case PSA_ALG_ECB_NO_PADDING: +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif +#endif /* MBEDTLS_PSA_CRYPTO_C */ + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (key_buffer_size < (psa_get_key_bits(attributes) / 8) + || !(psa_get_key_bits(attributes) == 128 + || psa_get_key_bits(attributes) == 192 + || psa_get_key_bits(attributes) == 256)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // 0-length encrypt/decrypt is allowed according to the unit tests in PSA + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + // Encrypt. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // We cannot do ECB on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(PSA_WANT_KEY_TYPE_AES) && defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + +#if defined(PSA_WANT_ALG_CCM) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + tmp_buf[0] = 1; + memcpy(&tmp_buf[1], iv, 13); + tmp_buf[14] = 0; + tmp_buf[15] = 1; + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + } else +#endif + { + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + iv_block = block_t_convert(iv, AES_IV_SIZE); + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ctr_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy final input bytes before they are overwritten (in case of overlap with output buffer). + memcpy(tmp_buf, input + (input_length / 16) * 16, input_length % 16); + + key = block_t_convert(key_buffer, key_buffer_size); + + size_t input_length_full_blocks = (input_length / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + iv_block = block_t_convert(iv, AES_IV_SIZE); + data_in = block_t_convert(input, input_length_full_blocks); + data_out = block_t_convert(output, + input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + iv_block = block_t_convert(&output[input_length_full_blocks - 16], + AES_IV_SIZE); + data_in = block_t_convert(tmp_buf, 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: { + uint8_t final_block[16]; + + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy final input bytes before they are overwritten (in case of overlap with output buffer). + memcpy(final_block, input + (input_length / 16) * 16, input_length % 16); + + // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. + memcpy(tmp_buf, iv, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + size_t input_length_full_blocks = (input_length / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input, input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process leftover bytes. + if (input_length % 16 != 0) { + data_in = block_t_convert(final_block, 16); + data_out = block_t_convert(final_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + final_block, + input_length % 16); + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // We cannot do CBC without padding on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + // fall through + case PSA_ALG_CBC_PKCS7: { + uint8_t final_block[16]; + + // Check buffer sizes. + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + if (output_size < (input_length & ~0xF) + 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + if (iv_length != AES_IV_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Copy IV to tmp buf in order to avoid overwriting it with intermediate IV. + memcpy(tmp_buf, iv, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + data_in = block_t_convert(input, input_length & ~0xF); + data_out = block_t_convert(output, input_length & ~0xF); + + // Store last block (if non-blocksize input-length) to temporary buffer to be used in padding. + if (alg == PSA_ALG_CBC_PKCS7) { + memcpy(final_block, + &input[input_length & ~0xF], + input_length & 0xF); + } + + if ((input_length & ~0xF) > 0) { + // CBC-encrypt all but the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Add PKCS7 padding. + memset(&final_block[input_length & 0xF], + 16 - (input_length & 0xF), + 16 - (input_length & 0xF)); + + // CBC-encrypt the last block. + data_in = block_t_convert(final_block, 16); + data_out = block_t_convert(final_block, 16); + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_encrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Copy to output. + memcpy(&output[(input_length & ~0xF)], + final_block, + 16); + + *output_length = (input_length & ~0xF) + 16; + } else { + *output_length = input_length; + } + break; + } +#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING +#endif /* MBEDTLS_PSA_CRYPTO_C */ + default: + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES +} + +/** Decrypt a message using a symmetric cipher. + * + * This function decrypts a message encrypted with a symmetric cipher. + * + * \param handle Handle to the key to use for the operation. + * It must remain valid until the operation + * terminates. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to decrypt. + * This consists of the IV followed by the + * ciphertext proper. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the plaintext is to be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p handle is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sli_cryptoacc_transparent_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block; +#endif +#if defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + uint8_t tmp_buf[16]; +#endif + + // Argument check + if (key_buffer == NULL + || key_buffer_size == 0 + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check key type and size. + switch (alg) { + case PSA_ALG_ECB_NO_PADDING: +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (key_buffer_size < (psa_get_key_bits(attributes) / 8) + || !(psa_get_key_bits(attributes) == 128 + || psa_get_key_bits(attributes) == 192 + || psa_get_key_bits(attributes) == 256)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // 0-length encrypt/decrypt is allowed according to the unit tests in Mbed TLS. + if (input_length == 0) { + *output_length = 0; + return PSA_SUCCESS; + } + // Only passing an IV should also be OK (all modes use an IV except ECB). + if ((input_length == AES_IV_SIZE) + && (alg != PSA_ALG_ECB_NO_PADDING)) { + *output_length = 0; + return PSA_SUCCESS; + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: { + // Check buffer sizes. + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // We cannot do ECB on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: { + // Check buffer sizes. +#if defined(PSA_WANT_ALG_CCM) + if (alg == PSA_ALG_CCM_STAR_NO_TAG) { + if (output_size < input_length - 13) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // AES-CCM*-no-tag is basically AES-CTR with preformatted IV + tmp_buf[0] = 1; + memcpy(&tmp_buf[1], input, 13); + tmp_buf[14] = 0; + tmp_buf[15] = 1; + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + input += 13; + input_length -= 13; + } else +#endif + { + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + iv_block = block_t_convert(input, AES_IV_SIZE); + + input += AES_IV_SIZE; + input_length -= AES_IV_SIZE; + } + + key = block_t_convert(key_buffer, key_buffer_size); + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(output, input_length); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ctr_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *output_length = input_length; + break; + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: { + // Check buffer sizes. + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + key = block_t_convert(key_buffer, key_buffer_size); + + size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + iv_block = block_t_convert(input, AES_IV_SIZE); + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + iv_block = block_t_convert(input + input_length_full_blocks, + AES_IV_SIZE); + data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, + 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cfb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length - AES_IV_SIZE; + break; + } +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: { + // Check buffer sizes. + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Move IV into tmp buffer in order to avoid messing up output (in case of overlap with input). + memcpy(tmp_buf, input, AES_IV_SIZE); + + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(tmp_buf, AES_IV_SIZE); + + size_t input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + + // Process full blocks. + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final bytes. + if (input_length % 16 != 0) { + data_in = block_t_convert(input + AES_IV_SIZE + input_length_full_blocks, + 16); + data_out = block_t_convert(tmp_buf, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_ofb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output + input_length_full_blocks, + tmp_buf, + input_length % 16); + } + + *output_length = input_length - AES_IV_SIZE; + break; + } +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: { + size_t input_length_full_blocks; + uint8_t iv_buf[AES_IV_SIZE]; + + // We cannot do CBC decryption on non-block sizes. + if (input_length % 16 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (alg == PSA_ALG_CBC_NO_PADDING) { + if (output_size < input_length - AES_IV_SIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + input_length_full_blocks = ((input_length - AES_IV_SIZE) / 16) * 16; + } else { + // Check output has enough room for at least n-1 blocks. + if (input_length < AES_IV_SIZE + 16 + || output_size < (input_length - AES_IV_SIZE - 16)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + input_length_full_blocks = ((input_length - AES_IV_SIZE - 16) / 16) * 16; + } + + // Write IV to temporary buf to be used by sx_aes_cbc_decrypt_update. + memcpy(iv_buf, input, AES_IV_SIZE); + key = block_t_convert(key_buffer, key_buffer_size); + iv_block = block_t_convert(iv_buf, AES_IV_SIZE); + + if (input_length_full_blocks > 0) { + data_in = block_t_convert(input + AES_IV_SIZE, + input_length_full_blocks); + data_out = block_t_convert(output, input_length_full_blocks); + + // CBC-decrypt all but the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + // Process final block. + if (alg == PSA_ALG_CBC_PKCS7) { + // Store last block to temporary buffer to be used in removing the padding. + memcpy(tmp_buf, &input[input_length - 16], 16); + + data_in = block_t_convert(tmp_buf, 16); + data_out = block_t_convert(tmp_buf, 16); + + // CBC-decrypt the last block. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + sx_ret = sx_aes_cbc_decrypt_update((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block, + &iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Check all padding bytes. + size_t pad_bytes = 0; + status = sli_psa_validate_pkcs7_padding(tmp_buf, + 16, + &pad_bytes); + if (status != PSA_SUCCESS) { + return status; + } + + if (output_size < (input_length - AES_IV_SIZE - pad_bytes)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Copy non-padding bytes. + memcpy(&output[input_length_full_blocks], tmp_buf, 16 - pad_bytes); + + *output_length = input_length - AES_IV_SIZE - pad_bytes; + } else { + *output_length = input_length - AES_IV_SIZE; + } + break; + } +#endif // PSA_WANT_ALG_CBC_PKCS7 || PSA_WANT_ALG_CBC_NO_PADDING + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_* && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_encrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + // Set up context. + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SLI_AES_ENC; + + // Validate combination of key and algorithm. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif // PSA_WANT_ALG_CTR +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif // PSA_WANT_ALG_CBC_PKCS7 + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Copy key into context. + switch (psa_get_key_bits(attributes)) { + case 128: + if (key_buffer_size < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 16); + operation->key_len = 16; + break; + case 192: + if (key_buffer_size < 24) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 24); + operation->key_len = 24; + break; + case 256: + if (key_buffer_size < 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 32); + operation->key_len = 32; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_decrypt_setup(sli_cryptoacc_transparent_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || attributes == NULL || key_buffer == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + // Set up context. + memcpy(&operation->alg, &alg, sizeof(alg)); + operation->direction = SLI_AES_DEC; + + // Validate combination of key and algorithm. + switch (alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) + case PSA_ALG_CTR: +#endif // PSA_WANT_ALG_CTR +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: +#endif // PSA_WANT_ALG_CBC_PKCS7 + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Copy key into context. + switch (psa_get_key_bits(attributes)) { + case 128: + if (key_buffer_size < 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 16); + operation->key_len = 16; + break; + case 192: + if (key_buffer_size < 24) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 24); + operation->key_len = 24; + break; + case 256: + if (key_buffer_size < 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + memcpy(operation->key, key_buffer, 32); + operation->key_len = 32; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_set_iv(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation == NULL || iv == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (iv_length > sizeof(operation->iv)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->iv_len != 0) { + // IV was set previously. + return PSA_ERROR_BAD_STATE; + } + + if (operation->key_len == 0) { + // context hasn't been properly initialised. + return PSA_ERROR_BAD_STATE; + } + +#if defined(PSA_WANT_ALG_CCM) + if (operation->alg == PSA_ALG_CCM_STAR_NO_TAG) { + // Preformat the IV for CCM*-no-tag here, such that the remainder + // of the processing for this algorithm boils down to AES-CTR + if (iv_length != 13) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->iv[0] = 1; + memcpy(&operation->iv[1], iv, iv_length); + operation->iv[14] = 0; + operation->iv[15] = 1; + operation->iv_len = 16; + } else +#endif // PSA_WANT_ALG_CCM + if (operation->alg != PSA_ALG_ECB_NO_PADDING) { + if (iv_length != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->iv_len = iv_length; + memcpy(operation->iv, iv, iv_length); + } else { + if (iv_length > 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)iv; + (void)iv_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_update(sli_cryptoacc_transparent_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t data_in; + block_t data_out; + + // Argument check. + if (operation == NULL + || (input == NULL && input_length > 0) + || (output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check if IV has been set. + if ((operation->alg != PSA_ALG_ECB_NO_PADDING) + && (operation->iv_len == 0)) { + return PSA_ERROR_BAD_STATE; + } + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) + uint8_t tmp_buf[16]; + block_t tmp_iv_block = block_t_convert(tmp_buf, 16); +#endif +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7) + block_t iv_block = block_t_convert(operation->iv, operation->iv_len); +#endif + + // Figure out whether the operation is on a lagging or forward-looking cipher + // Lagging: needs a full block of input data before being able to output + // Non-lagging: can output the same amount of data as getting fed + bool lagging = true; + switch (operation->alg) { + case PSA_ALG_ECB_NO_PADDING: + case PSA_ALG_CBC_NO_PADDING: + case PSA_ALG_CBC_PKCS7: + lagging = true; + break; + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + lagging = false; + break; + default: + return PSA_ERROR_BAD_STATE; + } + + size_t bytes_to_boundary = 16 - (operation->processed_length % 16); + size_t actual_output_length = 0; + *output_length = 0; + + if ( input_length == 0 ) { + return PSA_SUCCESS; + } + + // We need to cache (not return) the whole last block for decryption with + // padding, otherwise it won't be possible to remove a potential padding block + // during finish. + bool cache_full_block = (operation->alg == PSA_ALG_CBC_PKCS7 + && operation->direction == SLI_AES_DEC); + + // Early processing if not getting to a full block for lagging ciphers. + if (lagging) { + if (cache_full_block + && bytes_to_boundary == 16 + && operation->processed_length > 0) { + // Don't overwrite the streaming block yet if it's currently full. + } else if (input_length < bytes_to_boundary) { + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + input_length); + operation->processed_length += input_length; + *output_length = actual_output_length; + return PSA_SUCCESS; + } + + // We know we'll be computing at least the completed streaming block + size_t output_blocks = 1; + if (input_length > bytes_to_boundary) { + // plus however many full blocks are left over after filling the stream buffer + output_blocks += (input_length - bytes_to_boundary) / 16; + // If we're caching and the sum of already-input and to-be-input data + // ends up at a block boundary, we won't be outputting the last block + if (cache_full_block && ((input_length - bytes_to_boundary) % 16 == 0)) { + output_blocks -= 1; + } + } + + if (output_size < (output_blocks * 16)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } else { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + // Our drivers only support full or no overlap between input and output + // buffers. So in the case of partial overlap, copy the input buffer into + // the output buffer and process it in place as if the buffers fully + // overlapped. + if ((output > input) && (output < (input + input_length))) { + // Sanity check before copying. Some ciphers have a stricter requirement + // than this (if an IV is included), but no ciphers will have an output + // smaller than the input. + if (output_size < input_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memmove(output, input, input_length); + input = output; + } + + key = block_t_convert(operation->key, operation->key_len); + + if (bytes_to_boundary != 16) { + // Read in up to full streaming input block. + memcpy(&operation->streaming_block[operation->processed_length % 16], + input, + bytes_to_boundary); + + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + if (cache_full_block && (bytes_to_boundary == input_length)) { + // Don't process the streaming block if there is no more input data + sx_ret = CRYPTOLIB_SUCCESS; + } else { + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + if (cache_full_block && (bytes_to_boundary == input_length)) { + // Don't process the streaming block if there is no more input data + sx_ret = CRYPTOLIB_SUCCESS; + } else { + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (lagging) { + memcpy(output, operation->streaming_block, 16); + // Don't increase output if no encryption/decryption was done + if (!(cache_full_block && (bytes_to_boundary == input_length))) { + output += 16; + actual_output_length += 16; + } + operation->processed_length += bytes_to_boundary; + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + } else { + if (input_length < bytes_to_boundary) { + bytes_to_boundary = input_length; + } + + memcpy(output, operation->streaming_block + (operation->processed_length % 16), bytes_to_boundary); + output += bytes_to_boundary; + actual_output_length += bytes_to_boundary; + operation->processed_length += bytes_to_boundary; + input += bytes_to_boundary; + input_length -= bytes_to_boundary; + +#if defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) + // Only want to update IV if we actually finished an entire block. + if (operation->processed_length % 16 == 0) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + if (operation->direction == SLI_AES_ENC) { + memcpy(operation->iv, output - 16, 16); + } else { + memcpy(operation->iv, input - 16, 16); + } + break; +#endif +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_OFB) + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_OFB: + memcpy(operation->iv, tmp_buf, 16); + break; +#endif + } + } +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB + } + } +#if defined(PSA_WANT_ALG_CBC_PKCS7) + else if (cache_full_block && operation->processed_length > 0) { + // We know there's processing to be done, and that we haven't processed + // the full block in the streaming buffer yet. Process it now. + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output, operation->streaming_block, 16); + output += 16; + actual_output_length += 16; + } +#endif + + // Do multi-block operation if applicable. + if (input_length >= 16) { + size_t operation_size = (input_length / 16) * 16; + + if (cache_full_block && (input_length % 16 == 0)) { + // Don't decrypt the last block until finish is called, so that we + // can properly remove the padding before returning it. + operation_size -= 16; + } + + if (operation_size > 0) { + data_in = block_t_convert(input, operation_size); + data_out = block_t_convert(output, operation_size); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_encrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: + sx_ret = sx_aes_cbc_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + sx_ret = sx_aes_ecb_decrypt((const block_t*)&key, + (const block_t*)&data_in, + &data_out); + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_OFB +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) || defined(PSA_WANT_ALG_CBC_PKCS7) + case PSA_ALG_CBC_NO_PADDING: + // fall through + case PSA_ALG_CBC_PKCS7: + sx_ret = sx_aes_cbc_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &iv_block); + break; +#endif // PSA_WANT_ALG_CBC_NO_PADDING || PSA_WANT_ALG_CBC_PKCS7 + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } + + input += operation_size; + input_length -= operation_size; + actual_output_length += operation_size; + output += operation_size; + operation->processed_length += operation_size; + } + + // Process final block. + if (input_length > 0) { + if (!lagging) { +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) + data_in = block_t_convert(input, 16); + data_out = block_t_convert(operation->streaming_block, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (operation->direction == SLI_AES_ENC) { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_encrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB + default: + return PSA_ERROR_BAD_STATE; + } + } else { + switch (operation->alg) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM_STAR_NO_TAG: + // Explicit fallthrough +#endif // PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CTR: + sx_ret = sx_aes_ctr_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM +#if defined(PSA_WANT_ALG_CFB) + case PSA_ALG_CFB: + sx_ret = sx_aes_cfb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_CFB +#if defined(PSA_WANT_ALG_OFB) + case PSA_ALG_OFB: + sx_ret = sx_aes_ofb_decrypt_update((const block_t*)&key, + (const block_t*)&data_in, + &data_out, + (const block_t*)&iv_block, + &tmp_iv_block); + break; +#endif // PSA_WANT_ALG_OFB + default: + return PSA_ERROR_BAD_STATE; + } + } + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + memcpy(output, + operation->streaming_block, + input_length); + + actual_output_length += input_length; + operation->processed_length += input_length; +#else + return PSA_ERROR_BAD_STATE; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_CFB || PSA_WANT_ALG_OFB + } else { + if ((input_length >= 16 && !cache_full_block) + || (input_length > 16 && cache_full_block)) { + *output_length = 0; + return PSA_ERROR_BAD_STATE; + } + memcpy(operation->streaming_block, + input, + input_length); + operation->processed_length += input_length; + } + } + + *output_length = actual_output_length; + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +psa_status_t sli_cryptoacc_transparent_cipher_finish(sli_cryptoacc_transparent_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + +#if defined(PSA_WANT_ALG_CBC_PKCS7) + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t key; + block_t iv_block; + block_t data_in; + block_t data_out; +#endif // PSA_WANT_ALG_CBC_PKCS7 + + // Argument check. + if (operation == NULL) { + *output_length = 0; + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) || defined(PSA_WANT_ALG_CBC_NO_PADDING) + // Blocksize-only modes without padding. + case PSA_ALG_ECB_NO_PADDING: + case PSA_ALG_CBC_NO_PADDING: + // Can't finish if they haven't processed block-size input. + if (operation->processed_length % 16 != 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + } else { + status = PSA_SUCCESS; + } + *output_length = 0; + break; +#endif // PSA_WANT_ALG_ECB_NO_PADDING || PSA_WANT_ALG_CBC_NO_PADDING +#if defined(PSA_WANT_ALG_CTR) || defined(PSA_WANT_ALG_CCM) || defined(PSA_WANT_ALG_CFB) || defined(PSA_WANT_ALG_OFB) + // Stream cipher modes. + case PSA_ALG_CTR: + case PSA_ALG_CCM_STAR_NO_TAG: + case PSA_ALG_CFB: + case PSA_ALG_OFB: + status = PSA_SUCCESS; + *output_length = 0; + break; +#endif // PSA_WANT_ALG_CTR || PSA_WANT_ALG_CCM || PSA_WANT_ALG_*FB +#if defined(PSA_WANT_ALG_CBC_PKCS7) + // Padding mode. + case PSA_ALG_CBC_PKCS7: + if ((output == NULL && output_size > 0) + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + key = block_t_convert(operation->key, operation->key_len); + iv_block = block_t_convert(operation->iv, operation->iv_len); + data_in = block_t_convert(operation->streaming_block, 16); + data_out = block_t_convert(output, 16); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + if (operation->direction == SLI_AES_ENC) { + if (output_size < 16) { + status = cryptoacc_management_release(); + if (status == PSA_SUCCESS) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + } + break; + } + size_t padding_bytes = 16 - (operation->processed_length % 16); + memset(&operation->streaming_block[16 - padding_bytes], + padding_bytes, + padding_bytes); + + sx_ret = sx_aes_cbc_encrypt((const block_t *)&key, + (const block_t *)&data_in, + &data_out, + (const block_t *)&iv_block); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + } else { + *output_length = 16; + status = PSA_SUCCESS; + } + } else { + // Expect full-block input. + if (operation->processed_length % 16 != 0 + || operation->processed_length < 16) { + status = PSA_ERROR_INVALID_ARGUMENT; + break; + } + + uint8_t out_buf[16]; + block_t out_buf_block = block_t_convert(&out_buf, 16); + + // Decrypt the last block + sx_ret = sx_aes_cbc_decrypt((const block_t *)&key, + (const block_t *)&data_in, + &out_buf_block, + (const block_t *)&iv_block); + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + break; + } + + size_t padding_bytes = 0; + status = sli_psa_validate_pkcs7_padding(out_buf, + 16, + &padding_bytes); + + if (status == PSA_SUCCESS) { + // The padding was valid. + if (output_size < 16 - padding_bytes) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + break; + } + memcpy(output, out_buf, 16 - padding_bytes); + *output_length = 16 - padding_bytes; + } + } + break; +#endif // PSA_WANT_ALG_CBC_PKCS7 + default: + status = PSA_ERROR_BAD_STATE; + break; + } + +#if !defined(PSA_WANT_ALG_CBC_PKCS7) + (void)output; + (void)output_size; +#endif // PSA_WANT_ALG_CBC_PKCS7 + + if (status != PSA_SUCCESS) { + *output_length = 0; + } + + // Wipe context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_cipher_operation_t)); + + return status; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* + + (void)operation; + (void)output; + (void)output_size; + (void)output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_* +} + +psa_status_t sli_cryptoacc_transparent_cipher_abort(sli_cryptoacc_transparent_cipher_operation_t *operation) +{ +#if (defined(PSA_WANT_KEY_TYPE_AES) \ + && (defined(PSA_WANT_ALG_ECB_NO_PADDING) \ + || defined(PSA_WANT_ALG_CTR) \ + || defined(PSA_WANT_ALG_CCM) \ + || defined(PSA_WANT_ALG_CFB) \ + || defined(PSA_WANT_ALG_OFB) \ + || defined(PSA_WANT_ALG_CBC_NO_PADDING) \ + || defined(PSA_WANT_ALG_CBC_PKCS7))) + + if (operation != NULL) { + // Wipe context. + memset(operation, 0, sizeof(*operation)); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_AES && PSA_WANT_KEY_TYPE_AES +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c index 65b46ec..8de9323 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c @@ -1,490 +1,490 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Hash functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" - -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - -#include "cryptoacc_management.h" -#include "sx_hash.h" -#include "sx_errors.h" -#include - -// Define all init vectors. -#if defined(PSA_WANT_ALG_SHA_1) -static const uint8_t init_state_sha1[32] = { - 0x67, 0x45, 0x23, 0x01, - 0xEF, 0xCD, 0xAB, 0x89, - 0x98, 0xBA, 0xDC, 0xFE, - 0x10, 0x32, 0x54, 0x76, - 0xC3, 0xD2, 0xE1, 0xF0, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) -static const uint8_t init_state_sha224[32] = { - 0xC1, 0x05, 0x9E, 0xD8, - 0x36, 0x7C, 0xD5, 0x07, - 0x30, 0x70, 0xDD, 0x17, - 0xF7, 0x0E, 0x59, 0x39, - 0xFF, 0xC0, 0x0B, 0x31, - 0x68, 0x58, 0x15, 0x11, - 0x64, 0xF9, 0x8F, 0xA7, - 0xBE, 0xFA, 0x4F, 0xA4 -}; -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) -static const uint8_t init_state_sha256[32] = { - 0x6A, 0x09, 0xE6, 0x67, - 0xBB, 0x67, 0xAE, 0x85, - 0x3C, 0x6E, 0xF3, 0x72, - 0xA5, 0x4F, 0xF5, 0x3A, - 0x51, 0x0E, 0x52, 0x7F, - 0x9B, 0x05, 0x68, 0x8C, - 0x1F, 0x83, 0xD9, 0xAB, - 0x5B, 0xE0, 0xCD, 0x19 -}; -#endif // PSA_WANT_ALG_SHA_256 - -#endif // PSA_WANT_ALG_SHA_* - -psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, - psa_algorithm_t alg) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (!PSA_ALG_IS_HASH(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Reset context. - memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); - - switch (alg) { -#if defined(PSA_WANT_ALG_SHA_1) - case PSA_ALG_SHA_1: - operation->hash_type = e_SHA1; - memcpy(operation->state, init_state_sha1, SHA1_STATESIZE); - break; -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) - case PSA_ALG_SHA_224: - operation->hash_type = e_SHA224; - memcpy(operation->state, init_state_sha224, SHA224_STATESIZE); - break; -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) - case PSA_ALG_SHA_256: - operation->hash_type = e_SHA256; - memcpy(operation->state, init_state_sha256, SHA256_STATESIZE); - break; -#endif // PSA_WANT_ALG_SHA_256 - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - operation->total = 0; - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)operation; - (void)alg; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - size_t blocks, fill, left; - block_t data_in; - block_t state; - uint32_t sx_ret; - psa_status_t status; - - if (operation == NULL - || (input == NULL && input_length > 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (operation->hash_type) { -#if defined(PSA_WANT_ALG_SHA_1) - case e_SHA1: -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) - case e_SHA224: -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) - case e_SHA256: -#endif // PSA_WANT_ALG_SHA_256 - break; - default: - // State must have not been initialized by the setup function. - return PSA_ERROR_BAD_STATE; - } - - if (input_length == 0) { - return PSA_SUCCESS; - } - - state = block_t_convert((uint8_t*)operation->state, - sx_hash_get_state_size(operation->hash_type)); - - // Same blocksize for all of SHA-256, SHA-224, and SHA-256. - left = (operation->total & (SHA256_BLOCKSIZE - 1)); - fill = SHA256_BLOCKSIZE - left; - - operation->total += input_length; - - if ((left > 0) && (input_length >= fill)) { - memcpy((void *)(operation->buffer + left), input, fill); - - data_in = block_t_convert(operation->buffer, SHA256_BLOCKSIZE); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - input += fill; - input_length -= fill; - left = 0; - } - - if (input_length >= SHA256_BLOCKSIZE) { - blocks = input_length / SHA256_BLOCKSIZE; - - data_in = block_t_convert((uint8_t*)input, SHA256_BLOCKSIZE * blocks); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - input += SHA256_BLOCKSIZE * blocks; - input_length -= SHA256_BLOCKSIZE * blocks; - } - - if (input_length > 0) { - memcpy((void *)(operation->buffer + left), input, input_length); - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)operation; - (void)input; - (void)input_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - psa_status_t status; - uint32_t sx_ret; - block_t state; - block_t data_in; - block_t data_out; - - if (operation == NULL - || (hash_length == NULL && hash_size > 0) - || (hash == NULL && hash_size > 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (operation->hash_type) { -#if defined(PSA_WANT_ALG_SHA_1) - case e_SHA1: -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) - case e_SHA224: -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) - case e_SHA256: -#endif // PSA_WANT_ALG_SHA_256 - break; - default: - // State must have not been initialized by the setup function. - return PSA_ERROR_BAD_STATE; - } - - if (hash_size < sx_hash_get_digest_size(operation->hash_type)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - state = block_t_convert((uint8_t*)operation->state, - sx_hash_get_state_size(operation->hash_type)); - data_in = block_t_convert((uint8_t*)operation->buffer, - (operation->total & (SHA256_BLOCKSIZE - 1))); - - data_out = block_t_convert((uint8_t*)operation->state, - sx_hash_get_state_size(operation->hash_type)); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = sx_hash_finish_blk(operation->hash_type, - state, - data_in, - data_out, - operation->total); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *hash_length = sx_hash_get_digest_size(operation->hash_type); - memcpy(hash, operation->state, *hash_length); - memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)operation; - (void)hash; - (void)hash_size; - (void)hash_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - if (operation != NULL) { - // Accelerator does not keep state, so just zero out the context and we're good. - memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - psa_status_t status; - uint32_t sx_ret = CRYPTOLIB_INVALID_PARAM; - block_t data_in; - block_t data_out; - - if ((input == NULL && input_length > 0) - || (hash == NULL && hash_size > 0) - || (hash_length == NULL && hash_size > 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (alg) { -#if defined(PSA_WANT_ALG_SHA_1) - case PSA_ALG_SHA_1: - if (hash_size < SHA1_DIGESTSIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - break; -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) - case PSA_ALG_SHA_224: - if (hash_size < SHA224_DIGESTSIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - break; -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) - case PSA_ALG_SHA_256: - if (hash_size < SHA256_DIGESTSIZE) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - break; -#endif // PSA_WANT_ALG_SHA_256 - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - data_in = block_t_convert(input, input_length); - data_out = block_t_convert(hash, hash_size); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - switch (alg) { -#if defined(PSA_WANT_ALG_SHA_1) - case PSA_ALG_SHA_1: - sx_ret = sx_hash_blk(e_SHA1, data_in, data_out); - *hash_length = SHA1_DIGESTSIZE; - break; -#endif // PSA_WANT_ALG_SHA_1 -#if defined(PSA_WANT_ALG_SHA_224) - case PSA_ALG_SHA_224: - sx_ret = sx_hash_blk(e_SHA224, data_in, data_out); - *hash_length = SHA224_DIGESTSIZE; - break; -#endif // PSA_WANT_ALG_SHA_224 -#if defined(PSA_WANT_ALG_SHA_256) - case PSA_ALG_SHA_256: - sx_ret = sx_hash_blk(e_SHA256, data_in, data_out); - *hash_length = SHA256_DIGESTSIZE; - break; -#endif // PSA_WANT_ALG_SHA_256 - } - - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - *hash_length = 0; - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)alg; - (void)input; - (void)input_length; - (void)hash; - (void)hash_size; - (void)hash_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, - sli_cryptoacc_transparent_hash_operation_t *target_operation) -{ -#if defined(PSA_WANT_ALG_SHA_1) \ - || defined(PSA_WANT_ALG_SHA_224) \ - || defined(PSA_WANT_ALG_SHA_256) - - if (source_operation == NULL - || target_operation == NULL) { - return PSA_ERROR_BAD_STATE; - } - - // Source operation must be active (setup has been called) - if (source_operation->hash_type == 0) { - return PSA_ERROR_BAD_STATE; - } - - // Target operation must be inactive (setup has not been called) - if (target_operation->hash_type != 0) { - return PSA_ERROR_BAD_STATE; - } - - // The operation context does not contain any pointers, and the target operation - // have already have been initialized, so we can do a direct copy. - *target_operation = *source_operation; - - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_SHA_* - - (void)source_operation; - (void)target_operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_SHA_* -} - -#endif // defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Hash functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" + +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + +#include "cryptoacc_management.h" +#include "sx_hash.h" +#include "sx_errors.h" +#include + +// Define all init vectors. +#if defined(PSA_WANT_ALG_SHA_1) +static const uint8_t init_state_sha1[32] = { + 0x67, 0x45, 0x23, 0x01, + 0xEF, 0xCD, 0xAB, 0x89, + 0x98, 0xBA, 0xDC, 0xFE, + 0x10, 0x32, 0x54, 0x76, + 0xC3, 0xD2, 0xE1, 0xF0, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) +static const uint8_t init_state_sha224[32] = { + 0xC1, 0x05, 0x9E, 0xD8, + 0x36, 0x7C, 0xD5, 0x07, + 0x30, 0x70, 0xDD, 0x17, + 0xF7, 0x0E, 0x59, 0x39, + 0xFF, 0xC0, 0x0B, 0x31, + 0x68, 0x58, 0x15, 0x11, + 0x64, 0xF9, 0x8F, 0xA7, + 0xBE, 0xFA, 0x4F, 0xA4 +}; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) +static const uint8_t init_state_sha256[32] = { + 0x6A, 0x09, 0xE6, 0x67, + 0xBB, 0x67, 0xAE, 0x85, + 0x3C, 0x6E, 0xF3, 0x72, + 0xA5, 0x4F, 0xF5, 0x3A, + 0x51, 0x0E, 0x52, 0x7F, + 0x9B, 0x05, 0x68, 0x8C, + 0x1F, 0x83, 0xD9, 0xAB, + 0x5B, 0xE0, 0xCD, 0x19 +}; +#endif // PSA_WANT_ALG_SHA_256 + +#endif // PSA_WANT_ALG_SHA_* + +psa_status_t sli_cryptoacc_transparent_hash_setup(sli_cryptoacc_transparent_hash_operation_t *operation, + psa_algorithm_t alg) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_ALG_IS_HASH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Reset context. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + operation->hash_type = e_SHA1; + memcpy(operation->state, init_state_sha1, SHA1_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + operation->hash_type = e_SHA224; + memcpy(operation->state, init_state_sha224, SHA224_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + operation->hash_type = e_SHA256; + memcpy(operation->state, init_state_sha256, SHA256_STATESIZE); + break; +#endif // PSA_WANT_ALG_SHA_256 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + operation->total = 0; + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_update(sli_cryptoacc_transparent_hash_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + size_t blocks, fill, left; + block_t data_in; + block_t state; + uint32_t sx_ret; + psa_status_t status; + + if (operation == NULL + || (input == NULL && input_length > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->hash_type) { +#if defined(PSA_WANT_ALG_SHA_1) + case e_SHA1: +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case e_SHA224: +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case e_SHA256: +#endif // PSA_WANT_ALG_SHA_256 + break; + default: + // State must have not been initialized by the setup function. + return PSA_ERROR_BAD_STATE; + } + + if (input_length == 0) { + return PSA_SUCCESS; + } + + state = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + + // Same blocksize for all of SHA-256, SHA-224, and SHA-256. + left = (operation->total & (SHA256_BLOCKSIZE - 1)); + fill = SHA256_BLOCKSIZE - left; + + operation->total += input_length; + + if ((left > 0) && (input_length >= fill)) { + memcpy((void *)(operation->buffer + left), input, fill); + + data_in = block_t_convert(operation->buffer, SHA256_BLOCKSIZE); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + input += fill; + input_length -= fill; + left = 0; + } + + if (input_length >= SHA256_BLOCKSIZE) { + blocks = input_length / SHA256_BLOCKSIZE; + + data_in = block_t_convert((uint8_t*)input, SHA256_BLOCKSIZE * blocks); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_update_blk(operation->hash_type, state, data_in); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + input += SHA256_BLOCKSIZE * blocks; + input_length -= SHA256_BLOCKSIZE * blocks; + } + + if (input_length > 0) { + memcpy((void *)(operation->buffer + left), input, input_length); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_finish(sli_cryptoacc_transparent_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + psa_status_t status; + uint32_t sx_ret; + block_t state; + block_t data_in; + block_t data_out; + + if (operation == NULL + || (hash_length == NULL && hash_size > 0) + || (hash == NULL && hash_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (operation->hash_type) { +#if defined(PSA_WANT_ALG_SHA_1) + case e_SHA1: +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case e_SHA224: +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case e_SHA256: +#endif // PSA_WANT_ALG_SHA_256 + break; + default: + // State must have not been initialized by the setup function. + return PSA_ERROR_BAD_STATE; + } + + if (hash_size < sx_hash_get_digest_size(operation->hash_type)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + state = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + data_in = block_t_convert((uint8_t*)operation->buffer, + (operation->total & (SHA256_BLOCKSIZE - 1))); + + data_out = block_t_convert((uint8_t*)operation->state, + sx_hash_get_state_size(operation->hash_type)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = sx_hash_finish_blk(operation->hash_type, + state, + data_in, + data_out, + operation->total); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *hash_length = sx_hash_get_digest_size(operation->hash_type); + memcpy(hash, operation->state, *hash_length); + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + (void)hash; + (void)hash_size; + (void)hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_abort(sli_cryptoacc_transparent_hash_operation_t *operation) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (operation != NULL) { + // Accelerator does not keep state, so just zero out the context and we're good. + memset(operation, 0, sizeof(sli_cryptoacc_transparent_hash_operation_t)); + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + psa_status_t status; + uint32_t sx_ret = CRYPTOLIB_INVALID_PARAM; + block_t data_in; + block_t data_out; + + if ((input == NULL && input_length > 0) + || (hash == NULL && hash_size > 0) + || (hash_length == NULL && hash_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + if (hash_size < SHA1_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + if (hash_size < SHA224_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + if (hash_size < SHA256_DIGESTSIZE) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + break; +#endif // PSA_WANT_ALG_SHA_256 + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + data_in = block_t_convert(input, input_length); + data_out = block_t_convert(hash, hash_size); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + switch (alg) { +#if defined(PSA_WANT_ALG_SHA_1) + case PSA_ALG_SHA_1: + sx_ret = sx_hash_blk(e_SHA1, data_in, data_out); + *hash_length = SHA1_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_1 +#if defined(PSA_WANT_ALG_SHA_224) + case PSA_ALG_SHA_224: + sx_ret = sx_hash_blk(e_SHA224, data_in, data_out); + *hash_length = SHA224_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_224 +#if defined(PSA_WANT_ALG_SHA_256) + case PSA_ALG_SHA_256: + sx_ret = sx_hash_blk(e_SHA256, data_in, data_out); + *hash_length = SHA256_DIGESTSIZE; + break; +#endif // PSA_WANT_ALG_SHA_256 + } + + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + *hash_length = 0; + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)alg; + (void)input; + (void)input_length; + (void)hash; + (void)hash_size; + (void)hash_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +psa_status_t sli_cryptoacc_transparent_hash_clone(const sli_cryptoacc_transparent_hash_operation_t *source_operation, + sli_cryptoacc_transparent_hash_operation_t *target_operation) +{ +#if defined(PSA_WANT_ALG_SHA_1) \ + || defined(PSA_WANT_ALG_SHA_224) \ + || defined(PSA_WANT_ALG_SHA_256) + + if (source_operation == NULL + || target_operation == NULL) { + return PSA_ERROR_BAD_STATE; + } + + // Source operation must be active (setup has been called) + if (source_operation->hash_type == 0) { + return PSA_ERROR_BAD_STATE; + } + + // Target operation must be inactive (setup has not been called) + if (target_operation->hash_type != 0) { + return PSA_ERROR_BAD_STATE; + } + + // The operation context does not contain any pointers, and the target operation + // have already have been initialized, so we can do a direct copy. + *target_operation = *source_operation; + + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_SHA_* + + (void)source_operation; + (void)target_operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_SHA_* +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c index ed91304..108716e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c @@ -1,196 +1,196 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Key Derivation functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "sli_psa_driver_common.h" // sli_psa_zeroize -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" -#include "cryptoacc_management.h" -// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong -// interface header file when it becomes available. -#include "psa/crypto_platform.h" -#include "psa/crypto_sizes.h" -#include "psa/crypto_struct.h" - -#include "sx_dh_alg.h" -#include "sx_ecc_curves.h" -#include "sx_errors.h" -#include "cryptolib_types.h" -#include - -// ----------------------------------------------------------------------------- -// Driver entry points - -psa_status_t sli_cryptoacc_transparent_key_agreement( - psa_algorithm_t alg, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECDH) - - // Argument check. - if (attributes == NULL - || key_buffer == NULL - || peer_key == NULL - || output == NULL - || output_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - uint32_t curve_flags = 0; - block_t domain = NULL_blk; - uint8_t tmp_output_buf[64] = { 0 }; - size_t key_bits = psa_get_key_bits(attributes); - psa_key_type_t key_type = psa_get_key_type(attributes); - - // Check that key_buffer contains private key. - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(key_type)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Only accelerate ECDH over secp{192, 224, 256}r1 and secp256k1 curves. - if (!PSA_ALG_IS_ECDH(alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - switch (key_bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { - return PSA_ERROR_NOT_SUPPORTED; - } - curve_flags = sx_ecc_curve_p192.pk_flags; - domain = block_t_convert(sx_ecc_curve_p192.params.addr, - 6 * sx_ecc_curve_p192.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { - return PSA_ERROR_NOT_SUPPORTED; - } - curve_flags = sx_ecc_curve_p224.pk_flags; - domain = block_t_convert(sx_ecc_curve_p224.params.addr, - 6 * sx_ecc_curve_p224.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { - curve_flags = sx_ecc_curve_p256.pk_flags; - domain = block_t_convert(sx_ecc_curve_p256.params.addr, - 6 * sx_ecc_curve_p256.bytesize); - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1)) { - curve_flags = sx_ecc_curve_p256k1.pk_flags; - domain = block_t_convert(sx_ecc_curve_p256k1.params.addr, - 6 * sx_ecc_curve_p256k1.bytesize); - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // Check input-keys sizes. - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits) - || peer_key_length < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check sufficient output buffer size. - if (output_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - block_t pub = block_t_convert(peer_key + 1, PSA_BITS_TO_BYTES(key_bits) * 2); - block_t shared_key = block_t_convert(tmp_output_buf, PSA_BITS_TO_BYTES(key_bits) * 2); - - // Check peer_key is a public key of correct format. - if (peer_key[0] != 0x04) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Compute shared key. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = dh_shared_key_ecdh(domain, priv, pub, shared_key, PSA_BITS_TO_BYTES(key_bits), curve_flags); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - // If the ECDH libcryptosoc operation failed, this is most likely due to - // the peer key being an invalid elliptic curve point. Other sources for - // failure should hopefully have been caught during parameter validation. - return PSA_ERROR_INVALID_ARGUMENT; - } - - memcpy(output, tmp_output_buf, PSA_BITS_TO_BYTES(key_bits)); - sli_psa_zeroize(tmp_output_buf, sizeof(tmp_output_buf)); - *output_length = PSA_BITS_TO_BYTES(key_bits); - - return PSA_SUCCESS; - -#else // SLI_PSA_DRIVER_FEATURE_ECDH - - (void) alg; - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) peer_key; - (void) peer_key_length; - (void) output; - (void) output_size; - (void) output_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECDH -} - -#endif // SLI_MBEDTLS_DEVICE_VSE +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Key Derivation functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "sli_psa_driver_common.h" // sli_psa_zeroize +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" + +#include "sx_dh_alg.h" +#include "sx_ecc_curves.h" +#include "sx_errors.h" +#include "cryptolib_types.h" +#include + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_key_agreement( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDH) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || peer_key == NULL + || output == NULL + || output_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + uint32_t curve_flags = 0; + block_t domain = NULL_blk; + uint8_t tmp_output_buf[64] = { 0 }; + size_t key_bits = psa_get_key_bits(attributes); + psa_key_type_t key_type = psa_get_key_type(attributes); + + // Check that key_buffer contains private key. + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(key_type)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Only accelerate ECDH over secp{192, 224, 256}r1 and secp256k1 curves. + if (!PSA_ALG_IS_ECDH(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + return PSA_ERROR_NOT_SUPPORTED; + } + curve_flags = sx_ecc_curve_p192.pk_flags; + domain = block_t_convert(sx_ecc_curve_p192.params.addr, + 6 * sx_ecc_curve_p192.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (key_type != PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + return PSA_ERROR_NOT_SUPPORTED; + } + curve_flags = sx_ecc_curve_p224.pk_flags; + domain = block_t_convert(sx_ecc_curve_p224.params.addr, + 6 * sx_ecc_curve_p224.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1)) { + curve_flags = sx_ecc_curve_p256.pk_flags; + domain = block_t_convert(sx_ecc_curve_p256.params.addr, + 6 * sx_ecc_curve_p256.bytesize); + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (key_type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_K1)) { + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain = block_t_convert(sx_ecc_curve_p256k1.params.addr, + 6 * sx_ecc_curve_p256k1.bytesize); + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check input-keys sizes. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits) + || peer_key_length < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (output_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t pub = block_t_convert(peer_key + 1, PSA_BITS_TO_BYTES(key_bits) * 2); + block_t shared_key = block_t_convert(tmp_output_buf, PSA_BITS_TO_BYTES(key_bits) * 2); + + // Check peer_key is a public key of correct format. + if (peer_key[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Compute shared key. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = dh_shared_key_ecdh(domain, priv, pub, shared_key, PSA_BITS_TO_BYTES(key_bits), curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + // If the ECDH libcryptosoc operation failed, this is most likely due to + // the peer key being an invalid elliptic curve point. Other sources for + // failure should hopefully have been caught during parameter validation. + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(output, tmp_output_buf, PSA_BITS_TO_BYTES(key_bits)); + sli_psa_zeroize(tmp_output_buf, sizeof(tmp_output_buf)); + *output_length = PSA_BITS_TO_BYTES(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDH + + (void) alg; + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) peer_key; + (void) peer_key_length; + (void) output; + (void) output_size; + (void) output_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDH +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c index db49f1d..aea570e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c @@ -1,484 +1,484 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Key Management functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "psa/crypto.h" - -#include "cryptoacc_management.h" - -#include "sli_psa_driver_common.h" -#include "sli_cryptoacc_driver_trng.h" - -#include "sx_errors.h" -#include "sx_ecc_curves.h" -#include "sx_ecc_keygen_alg.h" -#include "sx_primitives.h" - -#include - -// ----------------------------------------------------------------------------- -// Driver entry points - -psa_status_t sli_cryptoacc_transparent_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_length) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECC) - - // Argument check. - if (attributes == NULL - || key_buffer == NULL - || key_buffer_size == 0 - || key_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_key_type_t key_type = psa_get_key_type(attributes); - psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); - size_t key_bits = psa_get_key_bits(attributes); - - // Check key type. PSA Crypto defines generate_key to be an invalid call with a key type - // of public key. - if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // We currently only support R1 or K1 - if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // Check sufficient buffer size. - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Grab the correct order for the requested curve - block_t n = NULL_blk; - switch (key_bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - // The order n is stored as the second element in the curve-parameter tuple - // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is - // dependent on the length of the corresponding key. - n = block_t_convert(sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize), - sx_ecc_curve_p192.bytesize); - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - n = block_t_convert(sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize), - sx_ecc_curve_p224.bytesize); - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - switch (curve_type) { - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - case PSA_ECC_FAMILY_SECP_R1: - n = block_t_convert(sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize), - sx_ecc_curve_p256.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - case PSA_ECC_FAMILY_SECP_K1: - n = block_t_convert(sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize), - sx_ecc_curve_p256k1.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - - // Get random number < n -> private key. - psa_status_t status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - uint32_t sx_ret = ecc_generate_private_key(n, - priv, - sli_cryptoacc_trng_wrapper); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *key_length = PSA_BITS_TO_BYTES(key_bits); - - return PSA_SUCCESS; - -#else // SLI_PSA_DRIVER_FEATURE_ECC - - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) key_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECC -} - -psa_status_t sli_cryptoacc_transparent_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECC) - - // Argument check. - if (attributes == NULL - || key_buffer == NULL - || key_buffer_size == 0 - || data == NULL - || data_size == 0 - || data_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_key_type_t key_type = psa_get_key_type(attributes); - psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); - size_t key_bits = psa_get_key_bits(attributes); - - // If the key is stored transparently and is already a public key, - // let the core handle it. - if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (!PSA_KEY_TYPE_IS_ECC(key_type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // We currently only support R1 or K1 - if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check sufficient output buffer size. - if (data_size < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - block_t *domain_ptr = NULL; - uint32_t curve_flags = 0; - switch (key_bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_flags = sx_ecc_curve_p192.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p192.params; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_flags = sx_ecc_curve_p224.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p224.params; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - switch (curve_type) { - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - case PSA_ECC_FAMILY_SECP_R1: - curve_flags = sx_ecc_curve_p256.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p256.params; - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - case PSA_ECC_FAMILY_SECP_K1: - curve_flags = sx_ecc_curve_p256k1.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - block_t pub = block_t_convert(data + 1, PSA_BITS_TO_BYTES(key_bits) * 2); - - psa_status_t status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - uint32_t sx_ret = ecc_generate_public_key(*domain_ptr, - pub, - priv, - PSA_BITS_TO_BYTES(key_bits), - curve_flags); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - data[0] = 0x04; - *data_length = PSA_BITS_TO_BYTES(key_bits) * 2 + 1; - - return PSA_SUCCESS; - -#else // SLI_PSA_DRIVER_FEATURE_ECC - - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) data; - (void) data_size; - (void) data_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECC -} - -psa_status_t sli_cryptoacc_transparent_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_buffer_length, - size_t *bits) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECC) - - // Argument check. - if (attributes == NULL - || data == NULL - || data_length == 0 - || bits == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t status; - psa_key_type_t key_type = psa_get_key_type(attributes); - psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); - - // Transparent driver is not involved in validation of symmetric keys. - if (!PSA_KEY_TYPE_IS_ECC(key_type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - // We currently only support R1 or K1 - if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { // Private key. - void *modulus_ptr = NULL; - *bits = psa_get_key_bits(attributes); - - // Determine key bit-size - if (*bits == 0) { - *bits = data_length * 8; - } else { - if (PSA_BITS_TO_BYTES(*bits) != data_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - switch (*bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - // The order n is stored as the second element in the curve-parameter tuple - // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is - // dependent on the length of the corresponding key. - modulus_ptr = sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize); - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - modulus_ptr = sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize); - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - switch (curve_type) { - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - case PSA_ECC_FAMILY_SECP_R1: - modulus_ptr = sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - case PSA_ECC_FAMILY_SECP_K1: - modulus_ptr = sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize); - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - status = sli_psa_validate_ecc_weierstrass_privkey(data, - modulus_ptr, - data_length); - } else { // Public key. - block_t *domain_ptr = NULL; - uint32_t curve_flags = 0; - - // Check that uncompressed representation is given. - if (data[0] != 0x04) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Determine key bit size. - *bits = (data_length - 1) * 8 / 2; - - switch (*bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_flags = sx_ecc_curve_p192.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p192.params; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_flags = sx_ecc_curve_p224.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p224.params; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - switch (curve_type) { - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - case PSA_ECC_FAMILY_SECP_R1: - curve_flags = sx_ecc_curve_p256.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p256.params; - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - case PSA_ECC_FAMILY_SECP_K1: - curve_flags = sx_ecc_curve_p256k1.pk_flags; - domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; - break; - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - block_t point = block_t_convert(data + 1, PSA_BITS_TO_BYTES(*bits) * 2); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - uint32_t sx_ret = ecc_is_point_on_curve(*domain_ptr, - point, - PSA_BITS_TO_BYTES(*bits), - curve_flags); - status = cryptoacc_management_release(); - if (status != PSA_SUCCESS) { - return status; - } - if (sx_ret != CRYPTOLIB_SUCCESS) { - return PSA_ERROR_INVALID_ARGUMENT; - } else { - status = PSA_SUCCESS; - } - } - - if ( status == PSA_SUCCESS ) { - if ( key_buffer_size >= data_length ) { - memcpy(key_buffer, data, data_length); - *key_buffer_length = data_length; - } else { - status = PSA_ERROR_BUFFER_TOO_SMALL; - } - } - - return status; - -#else // SLI_PSA_DRIVER_FEATURE_ECC - - (void) attributes; - (void) data; - (void) data_length; - (void) key_buffer; - (void) key_buffer_size; - (void) key_buffer_length; - (void) bits; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECC -} - -#endif // SLI_MBEDTLS_DEVICE_VSE +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Key Management functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" + +#include "sli_psa_driver_common.h" +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "sx_ecc_curves.h" +#include "sx_ecc_keygen_alg.h" +#include "sx_primitives.h" + +#include + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || key_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + // Check key type. PSA Crypto defines generate_key to be an invalid call with a key type + // of public key. + if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check sufficient buffer size. + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Grab the correct order for the requested curve + block_t n = NULL_blk; + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + // The order n is stored as the second element in the curve-parameter tuple + // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is + // dependent on the length of the corresponding key. + n = block_t_convert(sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize), + sx_ecc_curve_p192.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + n = block_t_convert(sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize), + sx_ecc_curve_p224.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + n = block_t_convert(sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize), + sx_ecc_curve_p256.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + n = block_t_convert(sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize), + sx_ecc_curve_p256k1.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + + // Get random number < n -> private key. + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + uint32_t sx_ret = ecc_generate_private_key(n, + priv, + sli_cryptoacc_trng_wrapper); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *key_length = PSA_BITS_TO_BYTES(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) key_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +psa_status_t sli_cryptoacc_transparent_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || data == NULL + || data_size == 0 + || data_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + // If the key is stored transparently and is already a public key, + // let the core handle it. + if (PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check sufficient output buffer size. + if (data_size < PSA_BITS_TO_BYTES(key_bits) * 2 + 1) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t *domain_ptr = NULL; + uint32_t curve_flags = 0; + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p192.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p192.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p224.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p224.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + curve_flags = sx_ecc_curve_p256.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t pub = block_t_convert(data + 1, PSA_BITS_TO_BYTES(key_bits) * 2); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = ecc_generate_public_key(*domain_ptr, + pub, + priv, + PSA_BITS_TO_BYTES(key_bits), + curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + data[0] = 0x04; + *data_length = PSA_BITS_TO_BYTES(key_bits) * 2 + 1; + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) data; + (void) data_size; + (void) data_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +psa_status_t sli_cryptoacc_transparent_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECC) + + // Argument check. + if (attributes == NULL + || data == NULL + || data_length == 0 + || bits == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + + // Transparent driver is not involved in validation of symmetric keys. + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + // We currently only support R1 or K1 + if (curve_type != PSA_ECC_FAMILY_SECP_R1 && curve_type != PSA_ECC_FAMILY_SECP_K1) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { // Private key. + void *modulus_ptr = NULL; + *bits = psa_get_key_bits(attributes); + + // Determine key bit-size + if (*bits == 0) { + *bits = data_length * 8; + } else { + if (PSA_BITS_TO_BYTES(*bits) != data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + // The order n is stored as the second element in the curve-parameter tuple + // consisting of (q, n, Gx, Gy, a, b). The length of the parameters is + // dependent on the length of the corresponding key. + modulus_ptr = sx_ecc_curve_p192.params.addr + (1 * sx_ecc_curve_p192.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + modulus_ptr = sx_ecc_curve_p224.params.addr + (1 * sx_ecc_curve_p224.bytesize); + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + modulus_ptr = sx_ecc_curve_p256.params.addr + (1 * sx_ecc_curve_p256.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + modulus_ptr = sx_ecc_curve_p256k1.params.addr + (1 * sx_ecc_curve_p256k1.bytesize); + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + status = sli_psa_validate_ecc_weierstrass_privkey(data, + modulus_ptr, + data_length); + } else { // Public key. + block_t *domain_ptr = NULL; + uint32_t curve_flags = 0; + + // Check that uncompressed representation is given. + if (data[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Determine key bit size. + *bits = (data_length - 1) * 8 / 2; + + switch (*bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p192.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p192.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_flags = sx_ecc_curve_p224.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p224.params; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + switch (curve_type) { + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + case PSA_ECC_FAMILY_SECP_R1: + curve_flags = sx_ecc_curve_p256.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + case PSA_ECC_FAMILY_SECP_K1: + curve_flags = sx_ecc_curve_p256k1.pk_flags; + domain_ptr = (block_t*)&sx_ecc_curve_p256k1.params; + break; + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + block_t point = block_t_convert(data + 1, PSA_BITS_TO_BYTES(*bits) * 2); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + uint32_t sx_ret = ecc_is_point_on_curve(*domain_ptr, + point, + PSA_BITS_TO_BYTES(*bits), + curve_flags); + status = cryptoacc_management_release(); + if (status != PSA_SUCCESS) { + return status; + } + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_INVALID_ARGUMENT; + } else { + status = PSA_SUCCESS; + } + } + + if ( status == PSA_SUCCESS ) { + if ( key_buffer_size >= data_length ) { + memcpy(key_buffer, data, data_length); + *key_buffer_length = data_length; + } else { + status = PSA_ERROR_BUFFER_TOO_SMALL; + } + } + + return status; + +#else // SLI_PSA_DRIVER_FEATURE_ECC + + (void) attributes; + (void) data; + (void) data_length; + (void) key_buffer; + (void) key_buffer_size; + (void) key_buffer_length; + (void) bits; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECC +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c index 109bb9d..14a64cc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c @@ -1,740 +1,740 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Mac functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" - -#if defined(CRYPTOACC_PRESENT) - -#include "sli_cryptoacc_transparent_functions.h" -#include "sli_psa_driver_common.h" -#include "cryptoacc_management.h" -// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong -// interface header file when it becomes available. -#include "psa/crypto_platform.h" -#include "psa/crypto_sizes.h" -#include "psa/crypto_struct.h" -#include "sx_aes.h" -#include "sx_hash.h" -#include "sx_errors.h" -#include - -#if defined(PSA_WANT_ALG_HMAC) -static psa_status_t sli_cryptoacc_hmac_validate_key( - const psa_key_attributes_t *attributes, - psa_algorithm_t alg, - sx_hash_fct_t *hash_fct, - size_t *digest_length) -{ - // Check key type and output size - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_HMAC) { - // For HMAC, key type is strictly enforced - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (PSA_ALG_HMAC_GET_HASH(alg)) { - case PSA_ALG_SHA_1: - *hash_fct = e_SHA1; - *digest_length = 20; - break; - case PSA_ALG_SHA_224: - *hash_fct = e_SHA224; - *digest_length = 28; - break; - case PSA_ALG_SHA_256: - *hash_fct = e_SHA256; - *digest_length = 32; - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; -} -#endif // PSA_WANT_ALG_HMAC - -#if defined(PSA_WANT_ALG_CMAC) -static psa_status_t sli_cryptoacc_cmac_validate_key( - const psa_key_attributes_t *attributes) -{ - // Check key type and size - if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { - // CMAC could be used with DES - return PSA_ERROR_NOT_SUPPORTED; - } - - switch (psa_get_key_bits(attributes) / 8) { - case 16: - case 24: - case 32: - break; - default: - // There's no other AES algorithm in existence - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} -#endif // PSA_WANT_ALG_CMAC - -psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ -#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) - - if (key_buffer == NULL - || attributes == NULL - || mac == NULL - || mac_length == NULL - || ((input == NULL) && (input_length > 0))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t status; - uint32_t sx_ret; - size_t key_size = psa_get_key_bits(attributes) / 8; - -#if defined(PSA_WANT_ALG_HMAC) - if (PSA_ALG_IS_HMAC(alg)) { - sx_hash_fct_t sx_hash_alg; - size_t digest_length; - - status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); - if (status != PSA_SUCCESS) { - return status; - } - - if ((PSA_MAC_TRUNCATED_LENGTH(alg) > 0) - && (PSA_MAC_TRUNCATED_LENGTH(alg) < digest_length)) { - digest_length = PSA_MAC_TRUNCATED_LENGTH(alg); - } - - if (mac_size < digest_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Acquire exclusive access to the CRYPTOACC hardware - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - // Execute the HMAC operation - sx_ret = sx_hmac_blk(sx_hash_alg, - block_t_convert(key_buffer, key_size), - block_t_convert(input, input_length), - block_t_convert(mac, digest_length)); - - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (status != PSA_SUCCESS) { - return status; - } - - // Report generated hmac length - *mac_length = digest_length; - return PSA_SUCCESS; - } -#endif // PSA_WANT_ALG_HMAC - - // If not HMAC, continue with the regular MAC algos - switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { -#if defined(PSA_WANT_ALG_CMAC) - case PSA_ALG_CMAC: - { - status = sli_cryptoacc_cmac_validate_key(attributes); - if (status != PSA_SUCCESS) { - return status; - } - - if (key_buffer_size < key_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - size_t output_length = PSA_MAC_TRUNCATED_LENGTH(alg); - if (output_length == 0) { - output_length = 16; - } else if (output_length > 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (mac_size < output_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - uint8_t sx_mac_buf[BLK_CIPHER_MAC_SIZE]; - - // Setup DMA descriptors - block_t key_sxblk = block_t_convert(key_buffer, key_size); - block_t input_sxblk = block_t_convert(input, input_length); - block_t mac_sxblk = block_t_convert(sx_mac_buf, BLK_CIPHER_MAC_SIZE); - - // Acquire exclusive access to the CRYPTOACC hardware - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - // Execute the CMAC operation - sx_ret = sx_aes_cmac_generate((const block_t *)&key_sxblk, - (const block_t *)&input_sxblk, - &mac_sxblk); - - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - status = PSA_ERROR_HARDWARE_FAILURE; - } - - if (status == PSA_SUCCESS) { - memcpy(mac, sx_mac_buf, output_length); - *mac_length = output_length; - } else { - *mac_length = 0; - } - - memset(sx_mac_buf, 0, BLK_CIPHER_MAC_SIZE); - break; - } -#endif // PSA_WANT_ALG_CMAC - default: - status = PSA_ERROR_NOT_SUPPORTED; - } - -#if !defined(PSA_WANT_ALG_CMAC) - (void)key_buffer_size; -#endif // !PSA_WANT_ALG_CMAC - - return status; - -#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC - - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)input; - (void)input_length; - (void)mac; - (void)mac_size; - (void)mac_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC -} - -// Make sure that the two locations of 'alg' are in the same place, since we access them -// interchangeably. -#if defined(PSA_WANT_ALG_HMAC) -_Static_assert(offsetof(sli_cryptoacc_transparent_mac_operation_t, hmac.alg) - == offsetof(sli_cryptoacc_transparent_mac_operation_t, cipher_mac.alg), - "hmac.alg and cipher_mac.alg are not aliases"); -#endif // PSA_WANT_ALG_HMAC - -psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ -#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) - - if (operation == NULL - || attributes == NULL - || (key_buffer == NULL && key_buffer_size > 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - size_t key_size = psa_get_key_bits(attributes) / 8; - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - - if (key_size > key_buffer_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // start by resetting context - memset(operation, 0, sizeof(*operation)); - -#if defined(PSA_WANT_ALG_HMAC) - if (PSA_ALG_IS_HMAC(alg)) { - sx_hash_fct_t sx_hash_alg; - size_t digest_length; - status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); - if (status != PSA_SUCCESS) { - return status; - } - - if (PSA_MAC_TRUNCATED_LENGTH(alg) > digest_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // CRYPTOACC does not support multipart HMAC. Construct it from hashing instead. - psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(alg); - - // Reduce the key if larger than a block - if (key_size > sizeof(operation->hmac.opad)) { - status = sli_cryptoacc_transparent_hash_compute( - hash_alg, - key_buffer, - key_size, - operation->hmac.opad, - sizeof(operation->hmac.opad), - &key_size); - if (status != PSA_SUCCESS) { - return status; - } - } else if (key_size > 0) { - memcpy(operation->hmac.opad, key_buffer, key_size); - } - - // Calculate inner padding in opad buffer and start a multipart hash with it - for (size_t i = 0; i < key_size; i++) { - operation->hmac.opad[i] ^= 0x36; - } - memset(&operation->hmac.opad[key_size], 0x36, sizeof(operation->hmac.opad) - key_size); - - status = sli_cryptoacc_transparent_hash_setup( - &operation->hmac.hash_ctx, - hash_alg); - if (status != PSA_SUCCESS) { - return status; - } - - status = sli_cryptoacc_transparent_hash_update( - &operation->hmac.hash_ctx, - operation->hmac.opad, sizeof(operation->hmac.opad)); - if (status != PSA_SUCCESS) { - return status; - } - - // Calculate outer padding and store it for finalisation - for (size_t i = 0; i < sizeof(operation->hmac.opad); i++) { - operation->hmac.opad[i] ^= 0x36 ^ 0x5C; - } - - operation->hmac.alg = alg; - return PSA_SUCCESS; - } -#endif // PSA_WANT_ALG_HMAC - - // If not HMAC, check other algos - switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { -#if defined(PSA_WANT_ALG_CMAC) - case PSA_ALG_CMAC: - status = sli_cryptoacc_cmac_validate_key(attributes); - if (status != PSA_SUCCESS) { - return status; - } - - if (key_buffer_size < key_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memcpy(operation->cipher_mac.key, key_buffer, key_size); - operation->cipher_mac.key_len = key_size; - - operation->cipher_mac.alg = alg; - status = PSA_SUCCESS; - break; -#endif // PSA_WANT_ALG_CMAC - default: - status = PSA_ERROR_NOT_SUPPORTED; - break; - } - -#if !defined(PSA_WANT_ALG_CMAC) - (void)key_buffer_size; -#endif // !PSA_WANT_ALG_CMAC - - return status; - -#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC - - (void)operation; - (void)attributes; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC -} - -psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - // Since the PSA Crypto core exposes the verify functionality of the drivers without - // actually implementing the fallback to 'sign' when the driver doesn't support verify, - // we need to do this ourselves for the time being. - return sli_cryptoacc_transparent_mac_sign_setup(operation, - attributes, - key_buffer, - key_buffer_size, - alg); -} - -#if defined(PSA_WANT_ALG_CMAC) -static psa_status_t cryptoacc_cmac_update_blk(sli_cryptoacc_transparent_mac_operation_t *operation, - const uint8_t *input, size_t input_length) -{ - psa_status_t status; - uint32_t sx_ret; - - const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); - const block_t input_blk = block_t_convert(input, input_length); - block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); - - // Acquire exclusive access to the CRYPTOACC hardware - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - // CMAC state context is already initialized, do update. - sx_ret = sx_aes_cmac_generate_update(&key_blk, - &input_blk, - (const block_t*)&ctx_blk, - &ctx_blk); - - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (status != PSA_SUCCESS) { - return status; - } - return PSA_SUCCESS; -} -#endif // PSA_WANT_ALG_CMAC - -psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ -#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) - - if (operation == NULL - || input == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (input_length == 0 ) { - return PSA_SUCCESS; - } - -#if defined(PSA_WANT_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { - return sli_cryptoacc_transparent_hash_update( - &operation->hmac.hash_ctx, - input, - input_length); - } -#endif // PSA_WANT_ALG_HMAC - - switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { -#if defined(PSA_WANT_ALG_CMAC) - case PSA_ALG_CMAC: - { - psa_status_t status; - size_t current_block_len; - - // if the potential last block include data - // we need to process them first - current_block_len = operation->cipher_mac.current_block_len; - if (current_block_len) { - size_t bytes_to_boundary = 16 - current_block_len; - // if the total of bytes is smaller than a block, just copy and return - // else fill up the potential last block - if (input_length < bytes_to_boundary) { - memcpy(&operation->cipher_mac.current_block[current_block_len], input, input_length); - operation->cipher_mac.current_block_len = current_block_len + input_length; - return PSA_SUCCESS; - } else { - // fill up the potential last block - memcpy(&operation->cipher_mac.current_block[current_block_len], input, bytes_to_boundary); - operation->cipher_mac.current_block_len = 16; - input_length -= bytes_to_boundary; - input += bytes_to_boundary; - } - - // if there are more input data, the potential last block is not - // the last block, which means we can process it now, - if (input_length) { - // Execute CMAC operation on the single context block - status = cryptoacc_cmac_update_blk(operation, operation->cipher_mac.current_block, 16); - if (status != PSA_SUCCESS) { - return status; - } - operation->cipher_mac.current_block_len = 0; - } - } - - // Process complete input blocks - if (input_length > 16) { - // Calculate the number of bytes in complete blocks to process. - // If the last block is complete we need to postpone processing it - // since it may be the last block which should go to sx_aes_cmac_generate_final. - size_t bytes_to_copy = (input_length - 1) & ~0xFUL; - - // Execute CMAC operation on the single context block - status = cryptoacc_cmac_update_blk(operation, input, bytes_to_copy); - if (status != PSA_SUCCESS) { - return status; - } - - input_length -= bytes_to_copy; - input += bytes_to_copy; - } - - // Store remaining input bytes - if (input_length) { - memcpy(operation->cipher_mac.current_block, input, input_length); - operation->cipher_mac.current_block_len = input_length; - } - - return PSA_SUCCESS; - } -#endif // PSA_WANT_ALG_CMAC - default: - return PSA_ERROR_BAD_STATE; - } - -#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC - - (void)operation; - (void)input; - (void)input_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC -} - -psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ -#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) - - if (operation == NULL - || mac == NULL - || mac_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t status; - -#if defined(PSA_WANT_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { - uint8_t buffer[64 + 32]; - size_t olen; - - // Construct outer hash input from opad and hash result - memcpy(buffer, operation->hmac.opad, sizeof(operation->hmac.opad)); - memset(operation->hmac.opad, 0, sizeof(operation->hmac.opad)); - - status = sli_cryptoacc_transparent_hash_finish( - &operation->hmac.hash_ctx, - &buffer[sizeof(operation->hmac.opad)], - sizeof(buffer) - sizeof(operation->hmac.opad), - &olen); - - if (status != PSA_SUCCESS) { - return status; - } - - // Calculate HMAC - status = sli_cryptoacc_transparent_hash_compute( - PSA_ALG_HMAC_GET_HASH(operation->hmac.alg), - buffer, - sizeof(operation->hmac.opad) + olen, - buffer, - sizeof(buffer), - &olen); - if (status != PSA_SUCCESS) { - return status; - } - - // Copy out a potentially truncated HMAC - size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->hmac.alg); - if (requested_length == 0) { - requested_length = olen; - } - - if (requested_length > mac_size) { - memset(buffer, 0, sizeof(buffer)); - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(mac, buffer, requested_length); - *mac_length = requested_length; - memset(buffer, 0, sizeof(buffer)); - return PSA_SUCCESS; - } -#endif // PSA_WANT_ALG_HMAC - - // Check algorithm and store if supported - switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { -#if defined(PSA_WANT_ALG_CMAC) - case PSA_ALG_CMAC: - { - // Check output size - size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->cipher_mac.alg); - if (requested_length == 0) { - requested_length = BLK_CIPHER_MAC_SIZE; - } else if (requested_length > BLK_CIPHER_MAC_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (mac_size < requested_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - // Acquire exclusive access to the CRYPTOACC hardware - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - // Setup DMA descriptors - block_t input_blk = block_t_convert(operation->cipher_mac.current_block, - operation->cipher_mac.current_block_len); - const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); - block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); - - // Execute the first CMAC operation. - // Receive the final mac in the cmac_ctx buffer and copy the requested - // number of bytes to the user buffer after. - uint32_t sx_ret = sx_aes_cmac_generate_final(&key_blk, - (const block_t *)&input_blk, - (const block_t *)&ctx_blk, - &ctx_blk); - - status = cryptoacc_management_release(); - - if (sx_ret != CRYPTOLIB_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - if (status != PSA_SUCCESS) { - return status; - } - - // Copy the requested number of bytes (max 16 for CMAC) to the user buffer. - memcpy(mac, operation->cipher_mac.cmac_ctx, requested_length); - *mac_length = requested_length; - - return PSA_SUCCESS; - } - break; -#endif // PSA_WANT_ALG_CMAC - default: - return PSA_ERROR_NOT_SUPPORTED; - } - -#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC - - (void)operation; - (void)mac; - (void)mac_size; - (void)mac_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC -} - -psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length) -{ - // Since the PSA Crypto core exposes the verify functionality of the drivers without - // actually implementing the fallback to 'sign' when the driver doesn't support verify, - // we need to do this ourselves for the time being. - uint8_t calculated_mac[PSA_MAC_MAX_SIZE] = { 0 }; - size_t calculated_length = PSA_MAC_MAX_SIZE; - - psa_status_t status = sli_cryptoacc_transparent_mac_sign_finish( - operation, - calculated_mac, sizeof(calculated_mac), &calculated_length); - if (status != PSA_SUCCESS) { - return status; - } - - if (mac_length > sizeof(calculated_mac)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (sli_psa_safer_memcmp(mac, calculated_mac, mac_length) != 0) { - status = PSA_ERROR_INVALID_SIGNATURE; - } else { - status = PSA_SUCCESS; - } - - memset(calculated_mac, 0, sizeof(calculated_mac)); - return status; -} - -psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation) -{ -#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) - - // There's no state in hardware that we need to preserve, so zeroing out the context suffices. - if (operation == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memset(operation, 0, sizeof(*operation)); - return PSA_SUCCESS; - -#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC - - (void)operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC -} - -#endif // defined(CRYPTOACC_PRESENT) +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Mac functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" + +#if defined(CRYPTOACC_PRESENT) + +#include "sli_cryptoacc_transparent_functions.h" +#include "sli_psa_driver_common.h" +#include "cryptoacc_management.h" +// Replace inclusion of psa/crypto_xxx.h with the new psa driver commong +// interface header file when it becomes available. +#include "psa/crypto_platform.h" +#include "psa/crypto_sizes.h" +#include "psa/crypto_struct.h" +#include "sx_aes.h" +#include "sx_hash.h" +#include "sx_errors.h" +#include + +#if defined(PSA_WANT_ALG_HMAC) +static psa_status_t sli_cryptoacc_hmac_validate_key( + const psa_key_attributes_t *attributes, + psa_algorithm_t alg, + sx_hash_fct_t *hash_fct, + size_t *digest_length) +{ + // Check key type and output size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_HMAC) { + // For HMAC, key type is strictly enforced + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (PSA_ALG_HMAC_GET_HASH(alg)) { + case PSA_ALG_SHA_1: + *hash_fct = e_SHA1; + *digest_length = 20; + break; + case PSA_ALG_SHA_224: + *hash_fct = e_SHA224; + *digest_length = 28; + break; + case PSA_ALG_SHA_256: + *hash_fct = e_SHA256; + *digest_length = 32; + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_HMAC + +#if defined(PSA_WANT_ALG_CMAC) +static psa_status_t sli_cryptoacc_cmac_validate_key( + const psa_key_attributes_t *attributes) +{ + // Check key type and size + if (psa_get_key_type(attributes) != PSA_KEY_TYPE_AES) { + // CMAC could be used with DES + return PSA_ERROR_NOT_SUPPORTED; + } + + switch (psa_get_key_bits(attributes) / 8) { + case 16: + case 24: + case 32: + break; + default: + // There's no other AES algorithm in existence + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CMAC + +psa_status_t sli_cryptoacc_transparent_mac_compute(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (key_buffer == NULL + || attributes == NULL + || mac == NULL + || mac_length == NULL + || ((input == NULL) && (input_length > 0))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + uint32_t sx_ret; + size_t key_size = psa_get_key_bits(attributes) / 8; + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + sx_hash_fct_t sx_hash_alg; + size_t digest_length; + + status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); + if (status != PSA_SUCCESS) { + return status; + } + + if ((PSA_MAC_TRUNCATED_LENGTH(alg) > 0) + && (PSA_MAC_TRUNCATED_LENGTH(alg) < digest_length)) { + digest_length = PSA_MAC_TRUNCATED_LENGTH(alg); + } + + if (mac_size < digest_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Execute the HMAC operation + sx_ret = sx_hmac_blk(sx_hash_alg, + block_t_convert(key_buffer, key_size), + block_t_convert(input, input_length), + block_t_convert(mac, digest_length)); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + + // Report generated hmac length + *mac_length = digest_length; + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // If not HMAC, continue with the regular MAC algos + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + status = sli_cryptoacc_cmac_validate_key(attributes); + if (status != PSA_SUCCESS) { + return status; + } + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t output_length = PSA_MAC_TRUNCATED_LENGTH(alg); + if (output_length == 0) { + output_length = 16; + } else if (output_length > 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (mac_size < output_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + uint8_t sx_mac_buf[BLK_CIPHER_MAC_SIZE]; + + // Setup DMA descriptors + block_t key_sxblk = block_t_convert(key_buffer, key_size); + block_t input_sxblk = block_t_convert(input, input_length); + block_t mac_sxblk = block_t_convert(sx_mac_buf, BLK_CIPHER_MAC_SIZE); + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Execute the CMAC operation + sx_ret = sx_aes_cmac_generate((const block_t *)&key_sxblk, + (const block_t *)&input_sxblk, + &mac_sxblk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + status = PSA_ERROR_HARDWARE_FAILURE; + } + + if (status == PSA_SUCCESS) { + memcpy(mac, sx_mac_buf, output_length); + *mac_length = output_length; + } else { + *mac_length = 0; + } + + memset(sx_mac_buf, 0, BLK_CIPHER_MAC_SIZE); + break; + } +#endif // PSA_WANT_ALG_CMAC + default: + status = PSA_ERROR_NOT_SUPPORTED; + } + +#if !defined(PSA_WANT_ALG_CMAC) + (void)key_buffer_size; +#endif // !PSA_WANT_ALG_CMAC + + return status; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +// Make sure that the two locations of 'alg' are in the same place, since we access them +// interchangeably. +#if defined(PSA_WANT_ALG_HMAC) +_Static_assert(offsetof(sli_cryptoacc_transparent_mac_operation_t, hmac.alg) + == offsetof(sli_cryptoacc_transparent_mac_operation_t, cipher_mac.alg), + "hmac.alg and cipher_mac.alg are not aliases"); +#endif // PSA_WANT_ALG_HMAC + +psa_status_t sli_cryptoacc_transparent_mac_sign_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || attributes == NULL + || (key_buffer == NULL && key_buffer_size > 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + size_t key_size = psa_get_key_bits(attributes) / 8; + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + + if (key_size > key_buffer_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // start by resetting context + memset(operation, 0, sizeof(*operation)); + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + sx_hash_fct_t sx_hash_alg; + size_t digest_length; + status = sli_cryptoacc_hmac_validate_key(attributes, alg, &sx_hash_alg, &digest_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (PSA_MAC_TRUNCATED_LENGTH(alg) > digest_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // CRYPTOACC does not support multipart HMAC. Construct it from hashing instead. + psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH(alg); + + // Reduce the key if larger than a block + if (key_size > sizeof(operation->hmac.opad)) { + status = sli_cryptoacc_transparent_hash_compute( + hash_alg, + key_buffer, + key_size, + operation->hmac.opad, + sizeof(operation->hmac.opad), + &key_size); + if (status != PSA_SUCCESS) { + return status; + } + } else if (key_size > 0) { + memcpy(operation->hmac.opad, key_buffer, key_size); + } + + // Calculate inner padding in opad buffer and start a multipart hash with it + for (size_t i = 0; i < key_size; i++) { + operation->hmac.opad[i] ^= 0x36; + } + memset(&operation->hmac.opad[key_size], 0x36, sizeof(operation->hmac.opad) - key_size); + + status = sli_cryptoacc_transparent_hash_setup( + &operation->hmac.hash_ctx, + hash_alg); + if (status != PSA_SUCCESS) { + return status; + } + + status = sli_cryptoacc_transparent_hash_update( + &operation->hmac.hash_ctx, + operation->hmac.opad, sizeof(operation->hmac.opad)); + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate outer padding and store it for finalisation + for (size_t i = 0; i < sizeof(operation->hmac.opad); i++) { + operation->hmac.opad[i] ^= 0x36 ^ 0x5C; + } + + operation->hmac.alg = alg; + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // If not HMAC, check other algos + switch (PSA_ALG_FULL_LENGTH_MAC(alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + status = sli_cryptoacc_cmac_validate_key(attributes); + if (status != PSA_SUCCESS) { + return status; + } + + if (key_buffer_size < key_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(operation->cipher_mac.key, key_buffer, key_size); + operation->cipher_mac.key_len = key_size; + + operation->cipher_mac.alg = alg; + status = PSA_SUCCESS; + break; +#endif // PSA_WANT_ALG_CMAC + default: + status = PSA_ERROR_NOT_SUPPORTED; + break; + } + +#if !defined(PSA_WANT_ALG_CMAC) + (void)key_buffer_size; +#endif // !PSA_WANT_ALG_CMAC + + return status; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)attributes; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_verify_setup(sli_cryptoacc_transparent_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers without + // actually implementing the fallback to 'sign' when the driver doesn't support verify, + // we need to do this ourselves for the time being. + return sli_cryptoacc_transparent_mac_sign_setup(operation, + attributes, + key_buffer, + key_buffer_size, + alg); +} + +#if defined(PSA_WANT_ALG_CMAC) +static psa_status_t cryptoacc_cmac_update_blk(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, size_t input_length) +{ + psa_status_t status; + uint32_t sx_ret; + + const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); + const block_t input_blk = block_t_convert(input, input_length); + block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // CMAC state context is already initialized, do update. + sx_ret = sx_aes_cmac_generate_update(&key_blk, + &input_blk, + (const block_t*)&ctx_blk, + &ctx_blk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + return PSA_SUCCESS; +} +#endif // PSA_WANT_ALG_CMAC + +psa_status_t sli_cryptoacc_transparent_mac_update(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || input == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (input_length == 0 ) { + return PSA_SUCCESS; + } + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + return sli_cryptoacc_transparent_hash_update( + &operation->hmac.hash_ctx, + input, + input_length); + } +#endif // PSA_WANT_ALG_HMAC + + switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + psa_status_t status; + size_t current_block_len; + + // if the potential last block include data + // we need to process them first + current_block_len = operation->cipher_mac.current_block_len; + if (current_block_len) { + size_t bytes_to_boundary = 16 - current_block_len; + // if the total of bytes is smaller than a block, just copy and return + // else fill up the potential last block + if (input_length < bytes_to_boundary) { + memcpy(&operation->cipher_mac.current_block[current_block_len], input, input_length); + operation->cipher_mac.current_block_len = current_block_len + input_length; + return PSA_SUCCESS; + } else { + // fill up the potential last block + memcpy(&operation->cipher_mac.current_block[current_block_len], input, bytes_to_boundary); + operation->cipher_mac.current_block_len = 16; + input_length -= bytes_to_boundary; + input += bytes_to_boundary; + } + + // if there are more input data, the potential last block is not + // the last block, which means we can process it now, + if (input_length) { + // Execute CMAC operation on the single context block + status = cryptoacc_cmac_update_blk(operation, operation->cipher_mac.current_block, 16); + if (status != PSA_SUCCESS) { + return status; + } + operation->cipher_mac.current_block_len = 0; + } + } + + // Process complete input blocks + if (input_length > 16) { + // Calculate the number of bytes in complete blocks to process. + // If the last block is complete we need to postpone processing it + // since it may be the last block which should go to sx_aes_cmac_generate_final. + size_t bytes_to_copy = (input_length - 1) & ~0xFUL; + + // Execute CMAC operation on the single context block + status = cryptoacc_cmac_update_blk(operation, input, bytes_to_copy); + if (status != PSA_SUCCESS) { + return status; + } + + input_length -= bytes_to_copy; + input += bytes_to_copy; + } + + // Store remaining input bytes + if (input_length) { + memcpy(operation->cipher_mac.current_block, input, input_length); + operation->cipher_mac.current_block_len = input_length; + } + + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_CMAC + default: + return PSA_ERROR_BAD_STATE; + } + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)input; + (void)input_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_sign_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + if (operation == NULL + || mac == NULL + || mac_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status; + +#if defined(PSA_WANT_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->hmac.alg)) { + uint8_t buffer[64 + 32]; + size_t olen; + + // Construct outer hash input from opad and hash result + memcpy(buffer, operation->hmac.opad, sizeof(operation->hmac.opad)); + memset(operation->hmac.opad, 0, sizeof(operation->hmac.opad)); + + status = sli_cryptoacc_transparent_hash_finish( + &operation->hmac.hash_ctx, + &buffer[sizeof(operation->hmac.opad)], + sizeof(buffer) - sizeof(operation->hmac.opad), + &olen); + + if (status != PSA_SUCCESS) { + return status; + } + + // Calculate HMAC + status = sli_cryptoacc_transparent_hash_compute( + PSA_ALG_HMAC_GET_HASH(operation->hmac.alg), + buffer, + sizeof(operation->hmac.opad) + olen, + buffer, + sizeof(buffer), + &olen); + if (status != PSA_SUCCESS) { + return status; + } + + // Copy out a potentially truncated HMAC + size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->hmac.alg); + if (requested_length == 0) { + requested_length = olen; + } + + if (requested_length > mac_size) { + memset(buffer, 0, sizeof(buffer)); + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(mac, buffer, requested_length); + *mac_length = requested_length; + memset(buffer, 0, sizeof(buffer)); + return PSA_SUCCESS; + } +#endif // PSA_WANT_ALG_HMAC + + // Check algorithm and store if supported + switch (PSA_ALG_FULL_LENGTH_MAC(operation->cipher_mac.alg)) { +#if defined(PSA_WANT_ALG_CMAC) + case PSA_ALG_CMAC: + { + // Check output size + size_t requested_length = PSA_MAC_TRUNCATED_LENGTH(operation->cipher_mac.alg); + if (requested_length == 0) { + requested_length = BLK_CIPHER_MAC_SIZE; + } else if (requested_length > BLK_CIPHER_MAC_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (mac_size < requested_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + // Acquire exclusive access to the CRYPTOACC hardware + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + // Setup DMA descriptors + block_t input_blk = block_t_convert(operation->cipher_mac.current_block, + operation->cipher_mac.current_block_len); + const block_t key_blk = block_t_convert(operation->cipher_mac.key, operation->cipher_mac.key_len); + block_t ctx_blk = block_t_convert(operation->cipher_mac.cmac_ctx, sizeof(operation->cipher_mac.cmac_ctx)); + + // Execute the first CMAC operation. + // Receive the final mac in the cmac_ctx buffer and copy the requested + // number of bytes to the user buffer after. + uint32_t sx_ret = sx_aes_cmac_generate_final(&key_blk, + (const block_t *)&input_blk, + (const block_t *)&ctx_blk, + &ctx_blk); + + status = cryptoacc_management_release(); + + if (sx_ret != CRYPTOLIB_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + if (status != PSA_SUCCESS) { + return status; + } + + // Copy the requested number of bytes (max 16 for CMAC) to the user buffer. + memcpy(mac, operation->cipher_mac.cmac_ctx, requested_length); + *mac_length = requested_length; + + return PSA_SUCCESS; + } + break; +#endif // PSA_WANT_ALG_CMAC + default: + return PSA_ERROR_NOT_SUPPORTED; + } + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + (void)mac; + (void)mac_size; + (void)mac_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +psa_status_t sli_cryptoacc_transparent_mac_verify_finish(sli_cryptoacc_transparent_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + // Since the PSA Crypto core exposes the verify functionality of the drivers without + // actually implementing the fallback to 'sign' when the driver doesn't support verify, + // we need to do this ourselves for the time being. + uint8_t calculated_mac[PSA_MAC_MAX_SIZE] = { 0 }; + size_t calculated_length = PSA_MAC_MAX_SIZE; + + psa_status_t status = sli_cryptoacc_transparent_mac_sign_finish( + operation, + calculated_mac, sizeof(calculated_mac), &calculated_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (mac_length > sizeof(calculated_mac)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (sli_psa_safer_memcmp(mac, calculated_mac, mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } else { + status = PSA_SUCCESS; + } + + memset(calculated_mac, 0, sizeof(calculated_mac)); + return status; +} + +psa_status_t sli_cryptoacc_transparent_mac_abort(sli_cryptoacc_transparent_mac_operation_t *operation) +{ +#if defined(PSA_WANT_ALG_HMAC) || defined(PSA_WANT_ALG_CMAC) + + // There's no state in hardware that we need to preserve, so zeroing out the context suffices. + if (operation == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memset(operation, 0, sizeof(*operation)); + return PSA_SUCCESS; + +#else // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC + + (void)operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // PSA_WANT_ALG_HMAC) || PSA_WANT_ALG_CMAC +} + +#endif // defined(CRYPTOACC_PRESENT) diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c index f60dc4a..e0a07a4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c @@ -1,336 +1,336 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Transparent Driver Signature functions. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - -#include "psa/crypto.h" - -#include "cryptoacc_management.h" - -#include "sli_cryptoacc_driver_trng.h" - -#include "sx_errors.h" -#include "sx_ecdsa_alg.h" -#include "sx_ecc_keygen_alg.h" - -// ----------------------------------------------------------------------------- -// Driver entry points - -psa_status_t sli_cryptoacc_transparent_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) - - // Argument check. - if (attributes == NULL - || key_buffer == NULL - || key_buffer_size == 0 - || hash == NULL - || hash_length == 0 - || signature == NULL - || signature_size == 0 - || signature_length == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - // Check the requested algorithm is ECDSA with randomized k. - if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - psa_key_type_t key_type = psa_get_key_type(attributes); - psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); - size_t key_bits = psa_get_key_bits(attributes); - - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { - // Not able to sign using non-ECC keys, or using public keys. - return PSA_ERROR_INVALID_ARGUMENT; - } - - sx_ecc_curve_t *curve = NULL; - - switch (key_bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve = (sx_ecc_curve_t*)&sx_ecc_curve_p192; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve = (sx_ecc_curve_t*)&sx_ecc_curve_p224; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256; - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - if (curve_type == PSA_ECC_FAMILY_SECP_K1) { - curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - // Check sufficient output buffer size. - if (signature_size < PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - block_t data_in = block_t_convert(hash, hash_length); - block_t data_out = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); - - psa_status_t status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - - uint32_t sx_ret = ecdsa_generate_signature_digest(curve, - data_in, - priv, - data_out, - sli_cryptoacc_trng_wrapper); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - *signature_length = PSA_ECDSA_SIGNATURE_SIZE(key_bits); - - return PSA_SUCCESS; - -#else // SLI_PSA_DRIVER_FEATURE_ECDSA - - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - (void) hash; - (void) hash_length; - (void) signature; - (void) signature_size; - (void) signature_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECDSA -} - -psa_status_t sli_cryptoacc_transparent_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length) -{ -#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) - - // Argument check. - if (attributes == NULL - || key_buffer == NULL - || key_buffer_size == 0 - || hash == NULL - || hash_length == 0 - || signature == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_key_type_t key_type = psa_get_key_type(attributes); - psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); - size_t key_bits = psa_get_key_bits(attributes); - - if (!PSA_KEY_TYPE_IS_ECC(key_type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { - // We shouldn't have a RSA-type alg for a ECC key. - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (!PSA_ALG_IS_ECDSA(alg)) { - // We only support ECDSA. - return PSA_ERROR_NOT_SUPPORTED; - } - - if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (signature_length == 0) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - uint32_t curve_flags = 0; - sx_ecc_curve_t *curve_ptr = NULL; - - switch (key_bits) { - #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) - case 192: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p192; - curve_flags = sx_ecc_curve_p192.pk_flags; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P192R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) - case 224: - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p224; - curve_flags = sx_ecc_curve_p224.pk_flags; - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - #endif // SLI_PSA_DRIVER_FEATURE_P224R1 - case 256: - #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) - if (curve_type == PSA_ECC_FAMILY_SECP_R1) { - curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256; - curve_flags = sx_ecc_curve_p256.pk_flags; - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256R1 - #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) - if (curve_type == PSA_ECC_FAMILY_SECP_K1) { - curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; - curve_flags = sx_ecc_curve_p256k1.pk_flags; - } else - #endif // SLI_PSA_DRIVER_FEATURE_P256K1 - { - return PSA_ERROR_NOT_SUPPORTED; - } - break; - default: - return PSA_ERROR_NOT_SUPPORTED; - } - - if (signature_length != PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - // Export public key if necessary. - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; - block_t pub = NULL_blk; - uint8_t pub_buf[64] = { 0 }; - if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { - block_t curve = block_t_convert(curve_ptr->params.addr, 6 * PSA_BITS_TO_BYTES(key_bits)); - block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); - pub = block_t_convert(pub_buf, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); - - // Perform point multiplication in order to get public key. - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = ecc_generate_public_key(curve, pub, priv, PSA_BITS_TO_BYTES(key_bits), curve_flags); - status = cryptoacc_management_release(); - if (sx_ret != CRYPTOLIB_SUCCESS - || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - } else { - pub = block_t_convert(key_buffer + 1, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); - } - - block_t digest = block_t_convert(hash, hash_length); - block_t signature_internal = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); - - status = cryptoacc_management_acquire(); - if (status != PSA_SUCCESS) { - return status; - } - sx_ret = ecdsa_verify_signature_digest(curve_ptr, - digest, - pub, - signature_internal); - status = cryptoacc_management_release(); - if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { - return PSA_ERROR_INVALID_SIGNATURE; - } - if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; - -#else // SLI_PSA_DRIVER_FEATURE_ECDSA - - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - (void) hash; - (void) hash_length; - (void) signature; - (void) signature_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif // SLI_PSA_DRIVER_FEATURE_ECDSA -} - -#endif // SLI_MBEDTLS_DEVICE_VSE +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Transparent Driver Signature functions. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + +#include "psa/crypto.h" + +#include "cryptoacc_management.h" + +#include "sli_cryptoacc_driver_trng.h" + +#include "sx_errors.h" +#include "sx_ecdsa_alg.h" +#include "sx_ecc_keygen_alg.h" + +// ----------------------------------------------------------------------------- +// Driver entry points + +psa_status_t sli_cryptoacc_transparent_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || signature == NULL + || signature_size == 0 + || signature_length == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + // Check the requested algorithm is ECDSA with randomized k. + if (!PSA_ALG_IS_RANDOMIZED_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + // Not able to sign using non-ECC keys, or using public keys. + return PSA_ERROR_INVALID_ARGUMENT; + } + + sx_ecc_curve_t *curve = NULL; + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p192; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p224; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (curve_type == PSA_ECC_FAMILY_SECP_K1) { + curve = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + // Check sufficient output buffer size. + if (signature_size < PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + block_t data_in = block_t_convert(hash, hash_length); + block_t data_out = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + psa_status_t status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + + uint32_t sx_ret = ecdsa_generate_signature_digest(curve, + data_in, + priv, + data_out, + sli_cryptoacc_trng_wrapper); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + *signature_length = PSA_ECDSA_SIGNATURE_SIZE(key_bits); + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +psa_status_t sli_cryptoacc_transparent_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ +#if defined(SLI_PSA_DRIVER_FEATURE_ECDSA) + + // Argument check. + if (attributes == NULL + || key_buffer == NULL + || key_buffer_size == 0 + || hash == NULL + || hash_length == 0 + || signature == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_key_type_t key_type = psa_get_key_type(attributes); + psa_ecc_family_t curve_type = PSA_KEY_TYPE_ECC_GET_FAMILY(key_type); + size_t key_bits = psa_get_key_bits(attributes); + + if (!PSA_KEY_TYPE_IS_ECC(key_type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { + // We shouldn't have a RSA-type alg for a ECC key. + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_ALG_IS_ECDSA(alg)) { + // We only support ECDSA. + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_buffer_size < PSA_BITS_TO_BYTES(key_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (signature_length == 0) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + uint32_t curve_flags = 0; + sx_ecc_curve_t *curve_ptr = NULL; + + switch (key_bits) { + #if defined(SLI_PSA_DRIVER_FEATURE_P192R1) + case 192: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p192; + curve_flags = sx_ecc_curve_p192.pk_flags; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P192R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P224R1) + case 224: + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p224; + curve_flags = sx_ecc_curve_p224.pk_flags; + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + #endif // SLI_PSA_DRIVER_FEATURE_P224R1 + case 256: + #if defined(SLI_PSA_DRIVER_FEATURE_P256R1) + if (curve_type == PSA_ECC_FAMILY_SECP_R1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256; + curve_flags = sx_ecc_curve_p256.pk_flags; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256R1 + #if defined(SLI_PSA_DRIVER_FEATURE_P256K1) + if (curve_type == PSA_ECC_FAMILY_SECP_K1) { + curve_ptr = (sx_ecc_curve_t*)&sx_ecc_curve_p256k1; + curve_flags = sx_ecc_curve_p256k1.pk_flags; + } else + #endif // SLI_PSA_DRIVER_FEATURE_P256K1 + { + return PSA_ERROR_NOT_SUPPORTED; + } + break; + default: + return PSA_ERROR_NOT_SUPPORTED; + } + + if (signature_length != PSA_ECDSA_SIGNATURE_SIZE(key_bits)) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + // Export public key if necessary. + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint32_t sx_ret = CRYPTOLIB_CRYPTO_ERR; + block_t pub = NULL_blk; + uint8_t pub_buf[64] = { 0 }; + if (PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type)) { + block_t curve = block_t_convert(curve_ptr->params.addr, 6 * PSA_BITS_TO_BYTES(key_bits)); + block_t priv = block_t_convert(key_buffer, PSA_BITS_TO_BYTES(key_bits)); + pub = block_t_convert(pub_buf, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + // Perform point multiplication in order to get public key. + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = ecc_generate_public_key(curve, pub, priv, PSA_BITS_TO_BYTES(key_bits), curve_flags); + status = cryptoacc_management_release(); + if (sx_ret != CRYPTOLIB_SUCCESS + || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + } else { + pub = block_t_convert(key_buffer + 1, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + } + + block_t digest = block_t_convert(hash, hash_length); + block_t signature_internal = block_t_convert(signature, PSA_ECDSA_SIGNATURE_SIZE(key_bits)); + + status = cryptoacc_management_acquire(); + if (status != PSA_SUCCESS) { + return status; + } + sx_ret = ecdsa_verify_signature_digest(curve_ptr, + digest, + pub, + signature_internal); + status = cryptoacc_management_release(); + if (sx_ret == CRYPTOLIB_INVALID_SIGN_ERR) { + return PSA_ERROR_INVALID_SIGNATURE; + } + if (sx_ret != CRYPTOLIB_SUCCESS || status != PSA_SUCCESS) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; + +#else // SLI_PSA_DRIVER_FEATURE_ECDSA + + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif // SLI_PSA_DRIVER_FEATURE_ECDSA +} + +#endif // SLI_MBEDTLS_DEVICE_VSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c index 83c3e32..cd7f566 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c @@ -1,65 +1,65 @@ -/***************************************************************************/ /** - * @file - * @brief PSA Driver common utility functions - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_common.h" - -#include "constant_time_internal.h" -#include "constant_time_impl.h" - -//------------------------------------------------------------------------------ -// Function definitions - -psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, - size_t padded_data_length, - size_t *padding_bytes) -{ - size_t i, pad_idx; - unsigned char padding_len; - - padding_len = padded_data[padded_data_length - 1]; - *padding_bytes = padding_len; - - mbedtls_ct_condition_t bad = - mbedtls_ct_uint_gt(padding_len, padded_data_length); - bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); - - // The number of bytes checked must be independent of padding_len, so pick - // input_len, which is 16 bytes (one block) for our use cases. - pad_idx = padded_data_length - padding_len; - for (i = 0; i < padded_data_length; i++) { - mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); - mbedtls_ct_condition_t different = - mbedtls_ct_uint_ne(padded_data[i], padding_len); - bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); - } - - return (psa_status_t)mbedtls_ct_error_if_else_0(bad, - PSA_ERROR_INVALID_PADDING); -} +/***************************************************************************/ /** + * @file + * @brief PSA Driver common utility functions + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_common.h" + +#include "constant_time_internal.h" +#include "constant_time_impl.h" + +//------------------------------------------------------------------------------ +// Function definitions + +psa_status_t sli_psa_validate_pkcs7_padding(uint8_t *padded_data, + size_t padded_data_length, + size_t *padding_bytes) +{ + size_t i, pad_idx; + unsigned char padding_len; + + padding_len = padded_data[padded_data_length - 1]; + *padding_bytes = padding_len; + + mbedtls_ct_condition_t bad = + mbedtls_ct_uint_gt(padding_len, padded_data_length); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); + + // The number of bytes checked must be independent of padding_len, so pick + // input_len, which is 16 bytes (one block) for our use cases. + pad_idx = padded_data_length - padding_len; + for (i = 0; i < padded_data_length; i++) { + mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); + mbedtls_ct_condition_t different = + mbedtls_ct_uint_ne(padded_data[i], padding_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); + } + + return (psa_status_t)mbedtls_ct_error_if_else_0(bad, + PSA_ERROR_INVALID_PADDING); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c index 7f08a75..f29e802 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c @@ -1,132 +1,132 @@ -/***************************************************************************//** - * @file - * @brief PSA Driver initialization interface. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#include "psa/crypto.h" - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #include "sli_se_transparent_functions.h" - #include "sl_se_manager.h" - #include "sli_se_opaque_functions.h" -#endif // SLI_MBEDTLS_DEVICE_HSE - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - #include "sli_cryptoacc_transparent_functions.h" - #include "cryptoacc_management.h" -#endif // SLI_MBEDTLS_DEVICE_VSE - -#if defined(SLI_MBEDTLS_DEVICE_S1) - #include "sli_crypto_transparent_functions.h" -#endif // SLI_MBEDTLS_DEVICE_S1 - -// ----------------------------------------------------------------------------- -// Driver entry points - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - -psa_status_t sli_se_transparent_driver_init(void) -{ - sl_status_t sl_status = sl_se_init(); - if (sl_status != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; -} - -psa_status_t sli_se_transparent_driver_deinit(void) -{ - sl_status_t sl_status = sl_se_deinit(); - if (sl_status != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; -} - -#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - -psa_status_t sli_se_opaque_driver_init(void) -{ - sl_status_t sl_status = sl_se_init(); - if (sl_status != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; -} - -psa_status_t sli_se_opaque_driver_deinit(void) -{ - sl_status_t sl_status = sl_se_deinit(); - if (sl_status != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - return PSA_SUCCESS; -} - -#endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS - -#elif defined(SLI_MBEDTLS_DEVICE_VSE) - -psa_status_t sli_cryptoacc_transparent_driver_init(void) -{ - // Consider moving the clock init and etc. here, which is performed by the - // management functions. - - #if defined(SLI_MBEDTLS_DEVICE_VSE_V2) - return cryptoacc_initialize_countermeasures(); - #else - return PSA_SUCCESS; - #endif -} - -psa_status_t sli_cryptoacc_transparent_driver_deinit(void) -{ - return PSA_SUCCESS; -} - -#elif defined(SLI_MBEDTLS_DEVICE_S1) - -psa_status_t sli_crypto_transparent_driver_init(void) -{ - // Leave this function empty for now. Consider moving the clock init and etc. - // here, which is performed by the management functions. - return PSA_SUCCESS; -} - -psa_status_t sli_crypto_transparent_driver_deinit(void) -{ - return PSA_SUCCESS; -} - -#endif +/***************************************************************************//** + * @file + * @brief PSA Driver initialization interface. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#include "psa/crypto.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "sli_se_transparent_functions.h" + #include "sl_se_manager.h" + #include "sli_se_opaque_functions.h" +#endif // SLI_MBEDTLS_DEVICE_HSE + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + #include "sli_cryptoacc_transparent_functions.h" + #include "cryptoacc_management.h" +#endif // SLI_MBEDTLS_DEVICE_VSE + +#if defined(SLI_MBEDTLS_DEVICE_S1) + #include "sli_crypto_transparent_functions.h" +#endif // SLI_MBEDTLS_DEVICE_S1 + +// ----------------------------------------------------------------------------- +// Driver entry points + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +psa_status_t sli_se_transparent_driver_init(void) +{ + sl_status_t sl_status = sl_se_init(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +psa_status_t sli_se_transparent_driver_deinit(void) +{ + sl_status_t sl_status = sl_se_deinit(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + +psa_status_t sli_se_opaque_driver_init(void) +{ + sl_status_t sl_status = sl_se_init(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +psa_status_t sli_se_opaque_driver_deinit(void) +{ + sl_status_t sl_status = sl_se_deinit(); + if (sl_status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + return PSA_SUCCESS; +} + +#endif // SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS + +#elif defined(SLI_MBEDTLS_DEVICE_VSE) + +psa_status_t sli_cryptoacc_transparent_driver_init(void) +{ + // Consider moving the clock init and etc. here, which is performed by the + // management functions. + + #if defined(SLI_MBEDTLS_DEVICE_VSE_V2) + return cryptoacc_initialize_countermeasures(); + #else + return PSA_SUCCESS; + #endif +} + +psa_status_t sli_cryptoacc_transparent_driver_deinit(void) +{ + return PSA_SUCCESS; +} + +#elif defined(SLI_MBEDTLS_DEVICE_S1) + +psa_status_t sli_crypto_transparent_driver_init(void) +{ + // Leave this function empty for now. Consider moving the clock init and etc. + // here, which is performed by the management functions. + return PSA_SUCCESS; +} + +psa_status_t sli_crypto_transparent_driver_deinit(void) +{ + return PSA_SUCCESS; +} + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c index a745568..363cd77 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c @@ -1,166 +1,166 @@ -/***************************************************************************//** - * @file - * @brief Default PSA TRNG hook for Silicon Labs devices. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) - -#include "psa/crypto.h" -#include "psa/crypto_extra.h" -#include "psa/crypto_platform.h" - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #include "sl_se_manager.h" - #include "sl_se_manager_entropy.h" -#elif defined(SLI_MBEDTLS_DEVICE_VSE) - #include "sli_cryptoacc_driver_trng.h" -#elif defined(SLI_MBEDTLS_DEVICE_S1) && defined(SLI_PSA_DRIVER_FEATURE_TRNG) - #include "sli_crypto_driver_trng.h" -#elif defined(SLI_TRNG_DEVICE_SI91X) - #include "sl_si91x_psa_trng.h" -#endif - -// ----------------------------------------------------------------------------- -// Typedefs - -#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -typedef void mbedtls_psa_external_random_context_t; -#endif - -// ----------------------------------------------------------------------------- -// Static functions - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - -static psa_status_t se_get_random(unsigned char *output, - size_t len, - size_t *out_len) -{ - sl_status_t ret; - sl_se_command_context_t cmd_ctx; - - // Initialize the SE manager. - ret = sl_se_init(); - if (ret != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Initialize command context - ret = sl_se_init_command_context(&cmd_ctx); - if (ret != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - - // Get entropy - ret = sl_se_get_random(&cmd_ctx, output, len); - - if (ret == SL_STATUS_OK) { - *out_len = len; - return PSA_SUCCESS; - } - - *out_len = 0; - return PSA_ERROR_HARDWARE_FAILURE; -} - -#endif // SLI_MBEDTLS_DEVICE_HSE - -// ----------------------------------------------------------------------------- -// Global entry points - -psa_status_t mbedtls_psa_external_get_random( - mbedtls_psa_external_random_context_t *context, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - (void)context; - - #if defined(SLI_PSA_DRIVER_FEATURE_TRNG) - - psa_status_t entropy_status = PSA_ERROR_CORRUPTION_DETECTED; - *output_length = 0; - - #if defined(SLI_MBEDTLS_DEVICE_HSE) - - entropy_status = se_get_random(output, - output_size, - output_length); - - #elif defined(SLI_MBEDTLS_DEVICE_VSE) - - entropy_status = sli_cryptoacc_trng_get_random(output, output_size); - if (entropy_status == PSA_SUCCESS) { - *output_length = output_size; - } - - #else - - size_t entropy_max_retries = 5; - while (entropy_max_retries > 0 && entropy_status != PSA_SUCCESS) { - size_t offset = *output_length; - - // Read random bytes - #if defined(SLI_MBEDTLS_DEVICE_S1) - entropy_status = sli_crypto_trng_get_random(&output[offset], - output_size - offset, - output_length); - #elif defined(SLI_TRNG_DEVICE_SI91X) - entropy_status = sl_si91x_psa_get_random(&output[offset], - output_size - offset, - output_length); - #endif - - *output_length += offset; - - if (*output_length >= output_size) { - entropy_status = PSA_SUCCESS; - } - - // Consume a retry before going through another loop - entropy_max_retries--; - } - - #endif - - return entropy_status; - - #else // SLI_PSA_DRIVER_FEATURE_TRNG - - (void) output; - (void) output_size; - (void) output_length; - - return PSA_ERROR_HARDWARE_FAILURE; - - #endif // SLI_PSA_DRIVER_FEATURE_TRNG -} - -#endif // MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG || MBEDTLS_ENTROPY_HARDWARE_ALT +/***************************************************************************//** + * @file + * @brief Default PSA TRNG hook for Silicon Labs devices. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) || defined(MBEDTLS_ENTROPY_HARDWARE_ALT) + +#include "psa/crypto.h" +#include "psa/crypto_extra.h" +#include "psa/crypto_platform.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "sl_se_manager.h" + #include "sl_se_manager_entropy.h" +#elif defined(SLI_MBEDTLS_DEVICE_VSE) + #include "sli_cryptoacc_driver_trng.h" +#elif defined(SLI_MBEDTLS_DEVICE_S1) && defined(SLI_PSA_DRIVER_FEATURE_TRNG) + #include "sli_crypto_driver_trng.h" +#elif defined(SLI_TRNG_DEVICE_SI91X) + #include "sl_si91x_psa_trng.h" +#endif + +// ----------------------------------------------------------------------------- +// Typedefs + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +typedef void mbedtls_psa_external_random_context_t; +#endif + +// ----------------------------------------------------------------------------- +// Static functions + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +static psa_status_t se_get_random(unsigned char *output, + size_t len, + size_t *out_len) +{ + sl_status_t ret; + sl_se_command_context_t cmd_ctx; + + // Initialize the SE manager. + ret = sl_se_init(); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Initialize command context + ret = sl_se_init_command_context(&cmd_ctx); + if (ret != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + + // Get entropy + ret = sl_se_get_random(&cmd_ctx, output, len); + + if (ret == SL_STATUS_OK) { + *out_len = len; + return PSA_SUCCESS; + } + + *out_len = 0; + return PSA_ERROR_HARDWARE_FAILURE; +} + +#endif // SLI_MBEDTLS_DEVICE_HSE + +// ----------------------------------------------------------------------------- +// Global entry points + +psa_status_t mbedtls_psa_external_get_random( + mbedtls_psa_external_random_context_t *context, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + (void)context; + + #if defined(SLI_PSA_DRIVER_FEATURE_TRNG) + + psa_status_t entropy_status = PSA_ERROR_CORRUPTION_DETECTED; + *output_length = 0; + + #if defined(SLI_MBEDTLS_DEVICE_HSE) + + entropy_status = se_get_random(output, + output_size, + output_length); + + #elif defined(SLI_MBEDTLS_DEVICE_VSE) + + entropy_status = sli_cryptoacc_trng_get_random(output, output_size); + if (entropy_status == PSA_SUCCESS) { + *output_length = output_size; + } + + #else + + size_t entropy_max_retries = 5; + while (entropy_max_retries > 0 && entropy_status != PSA_SUCCESS) { + size_t offset = *output_length; + + // Read random bytes + #if defined(SLI_MBEDTLS_DEVICE_S1) + entropy_status = sli_crypto_trng_get_random(&output[offset], + output_size - offset, + output_length); + #elif defined(SLI_TRNG_DEVICE_SI91X) + entropy_status = sl_si91x_psa_get_random(&output[offset], + output_size - offset, + output_length); + #endif + + *output_length += offset; + + if (*output_length >= output_size) { + entropy_status = PSA_SUCCESS; + } + + // Consume a retry before going through another loop + entropy_max_retries--; + } + + #endif + + return entropy_status; + + #else // SLI_PSA_DRIVER_FEATURE_TRNG + + (void) output; + (void) output_size; + (void) output_length; + + return PSA_ERROR_HARDWARE_FAILURE; + + #endif // SLI_PSA_DRIVER_FEATURE_TRNG +} + +#endif // MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG || MBEDTLS_ENTROPY_HARDWARE_ALT diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c index 4713902..3ef26ee 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c @@ -1,72 +1,72 @@ -/***************************************************************************//** - * @file - * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - -#include "psa/crypto.h" - -#include "sli_se_version_dependencies.h" -#include "sli_se_driver_key_management.h" - -#include "sl_se_manager_util.h" - -// ----------------------------------------------------------------------------- -// Global functions - -#if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) - -// Check for an errata causing the SE to emit a faulty EdDSA public key for -// operations where only a private key is provided. Assumes that an already -// initalized SE command context is passed as input. -psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, - sl_se_command_context_t* cmd_ctx) -{ - if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) - == PSA_ECC_FAMILY_TWISTED_EDWARDS) { - uint32_t se_version = 0; - sl_status_t status = sl_se_get_se_version(cmd_ctx, &se_version); - if (status != SL_STATUS_OK) { - return PSA_ERROR_HARDWARE_FAILURE; - } - se_version = SLI_VERSION_REMOVE_DIE_ID(se_version); - - if (SLI_SE_VERSION_ED25519_BROKEN(se_version)) { - return PSA_ERROR_NOT_SUPPORTED; - } - } - - return PSA_SUCCESS; -} - -#endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED - -#endif // SLI_MBEDTLS_DEVICE_HSE +/***************************************************************************//** + * @file + * @brief Silicon Labs PSA Crypto Driver SE Version Dependencies. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + +#include "psa/crypto.h" + +#include "sli_se_version_dependencies.h" +#include "sli_se_driver_key_management.h" + +#include "sl_se_manager_util.h" + +// ----------------------------------------------------------------------------- +// Global functions + +#if defined(SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED) + +// Check for an errata causing the SE to emit a faulty EdDSA public key for +// operations where only a private key is provided. Assumes that an already +// initalized SE command context is passed as input. +psa_status_t sli_se_check_eddsa_errata(const psa_key_attributes_t* attributes, + sl_se_command_context_t* cmd_ctx) +{ + if (PSA_KEY_TYPE_ECC_GET_FAMILY(psa_get_key_type(attributes)) + == PSA_ECC_FAMILY_TWISTED_EDWARDS) { + uint32_t se_version = 0; + sl_status_t status = sl_se_get_se_version(cmd_ctx, &se_version); + if (status != SL_STATUS_OK) { + return PSA_ERROR_HARDWARE_FAILURE; + } + se_version = SLI_VERSION_REMOVE_DIE_ID(se_version); + + if (SLI_SE_VERSION_ED25519_BROKEN(se_version)) { + return PSA_ERROR_NOT_SUPPORTED; + } + } + + return PSA_SUCCESS; +} + +#endif // SLI_SE_VERSION_ED25519_ERRATA_CHECK_REQUIRED + +#endif // SLI_MBEDTLS_DEVICE_HSE diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h index 766f3a6..548774e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_clocks.h @@ -1,121 +1,121 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for clocks. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_CLOCKS_H -#define SL_DEVICE_INIT_CLOCKS_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init Device Initialization - * @brief Device Initialization - * @details - * The Device Initialization functions assist in bringing the device from the - * reset state to an initialized state by applying errata fixes, starting - * oscillators and configuring certain power control features. - * - * The top-level Device Init component will automatically add required and - * recommended initialization components to the platform init event handled - * by the System Init component based on the selected hardware. - * - * - Errata fixes are applied on all devices - * - EMU initialization is added on all devices - * - Clock tree initialization is added on all devices - * - NVIC initialization is added on all devices - * - DCDC initialization is added on devices with a DCDC converter - * - HFXO initialization is added on Silicon Labs modules and development - * boards with HFXO - * - LFXO initialization is added on Silicon Labs modules and development - * boards with LFXO - * - HFRCO initialization is added on EFR32xG21 devices to set the core - * frequency to 80 MHz (oscillator band is configurable in the component) - * - LFRCO initialization is added on EFR32xG22 devices when Bluetooth is - * present to enable high precision mode (precision mode is configurable - * in the component) - * - * If the individual initialization components are not sufficiently configurable, - * or if any of these default actions are not desired, the top-level device - * initialization component can be removed from the project and replaced by the - * subset of desired initialization components. - * - * @{ - * @addtogroup device_init_clocks Clock Initialization - * @brief Initialize the clock tree. - * @details - * - * Automatically configures the clock tree to use the appropriate high- and - * low-frequency clock sources depending on which other device initialization - * components are present. - * - * ### High Frequency Clocks - * If the **DPLL** or **HFRCO** device init components are present, the - * **HFRCO** oscillator is used as the clock source for high frequency clock - * trees. Otherwise, if the **HFXO** device init component is present, the - * **HFXO** oscillator is used. If no high frequency oscillator device init - * component is present, the **HFRCO** oscillator is used with its default - * settings. - * - * ### Low Frequency Clocks - * If the **LFXO** device init component is present, the **LFXO** oscillator is - * used as the clock source for low frequency clock trees. - * Otherwise, the **LFRCO** oscillator is used. - * - * @note This module has a limited configurability. Users can override the code - * based on the project ask. - * - * @{ - */ - -/** - * Configure the clock tree and enable clocks - * - * @details - * Automatically configures the clock tree to use the appropriate HF and LF - * clock sources depending on which other device initialization components are - * present. - * - * @return Status code - * @retval SL_STATUS_OK Clock tree configured successfully - */ -sl_status_t sl_device_init_clocks(void); - -/** - * @} device_init_clocks - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_CLOCKS_H +/***************************************************************************//** + * @file + * @brief Device initialization for clocks. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_CLOCKS_H +#define SL_DEVICE_INIT_CLOCKS_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init Device Initialization + * @brief Device Initialization + * @details + * The Device Initialization functions assist in bringing the device from the + * reset state to an initialized state by applying errata fixes, starting + * oscillators and configuring certain power control features. + * + * The top-level Device Init component will automatically add required and + * recommended initialization components to the platform init event handled + * by the System Init component based on the selected hardware. + * + * - Errata fixes are applied on all devices + * - EMU initialization is added on all devices + * - Clock tree initialization is added on all devices + * - NVIC initialization is added on all devices + * - DCDC initialization is added on devices with a DCDC converter + * - HFXO initialization is added on Silicon Labs modules and development + * boards with HFXO + * - LFXO initialization is added on Silicon Labs modules and development + * boards with LFXO + * - HFRCO initialization is added on EFR32xG21 devices to set the core + * frequency to 80 MHz (oscillator band is configurable in the component) + * - LFRCO initialization is added on EFR32xG22 devices when Bluetooth is + * present to enable high precision mode (precision mode is configurable + * in the component) + * + * If the individual initialization components are not sufficiently configurable, + * or if any of these default actions are not desired, the top-level device + * initialization component can be removed from the project and replaced by the + * subset of desired initialization components. + * + * @{ + * @addtogroup device_init_clocks Clock Initialization + * @brief Initialize the clock tree. + * @details + * + * Automatically configures the clock tree to use the appropriate high- and + * low-frequency clock sources depending on which other device initialization + * components are present. + * + * ### High Frequency Clocks + * If the **DPLL** or **HFRCO** device init components are present, the + * **HFRCO** oscillator is used as the clock source for high frequency clock + * trees. Otherwise, if the **HFXO** device init component is present, the + * **HFXO** oscillator is used. If no high frequency oscillator device init + * component is present, the **HFRCO** oscillator is used with its default + * settings. + * + * ### Low Frequency Clocks + * If the **LFXO** device init component is present, the **LFXO** oscillator is + * used as the clock source for low frequency clock trees. + * Otherwise, the **LFRCO** oscillator is used. + * + * @note This module has a limited configurability. Users can override the code + * based on the project ask. + * + * @{ + */ + +/** + * Configure the clock tree and enable clocks + * + * @details + * Automatically configures the clock tree to use the appropriate HF and LF + * clock sources depending on which other device initialization components are + * present. + * + * @return Status code + * @retval SL_STATUS_OK Clock tree configured successfully + */ +sl_status_t sl_device_init_clocks(void); + +/** + * @} device_init_clocks + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_CLOCKS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h index bfa0e9e..bba6990 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_dcdc.h @@ -1,88 +1,88 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DC/DC converter. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_DCDC_H -#define SL_DEVICE_INIT_DCDC_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_dcdc DCDC Initialization - * @brief Initialize the DC-DC converter. - * @details - * Configures the DC-DC converter. If the DC-DC converter is not to be - * used, the configuration option `SL_DEVICE_INIT_DCDC_ENABLE` can be disabled, - * and the converter will be powered off. On Series 1 devices, this option - * should only be used when DVDD is externally powered. - * - * To enable the bypass switch and short the DC-DC converter input to - * the DC-DC output, set the configuration option `SL_DEVICE_INIT_DCDC_BYPASS`. - * - * See **AN0948 Power Configurations and DC-DC** for further details about DC-DC - * converter configuration and operation. - * - * - Series 1: [AN0948](https://www.silabs.com/documents/public/application-notes/an0948-power-configurations-and-dcdc.pdf) - * - Series 2: [AN0948.2](https://www.silabs.com/documents/public/application-notes/an0948.2-efr32-series-2-power-configurations-and-dcdc.pdf) - * @{ - */ - -// ----------------------------------------------------------------------------- -// Defines - -/// @brief DC/DC Converter Type -#define SL_DEVICE_INIT_DCDC_TYPE_BUCK 0 ///< Buck Type -#define SL_DEVICE_INIT_DCDC_TYPE_BOOST 1 ///< Boost Type - -/** - * Initialize DCDC - * - * @details - * Configure and start the DCDC - * - * @return Status code - * @retval SL_STATUS_OK DC-DC converter initialized successfully - */ -sl_status_t sl_device_init_dcdc(void); - -/** - * @} device_init_dcdc - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_DCDC_H +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_DCDC_H +#define SL_DEVICE_INIT_DCDC_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_dcdc DCDC Initialization + * @brief Initialize the DC-DC converter. + * @details + * Configures the DC-DC converter. If the DC-DC converter is not to be + * used, the configuration option `SL_DEVICE_INIT_DCDC_ENABLE` can be disabled, + * and the converter will be powered off. On Series 1 devices, this option + * should only be used when DVDD is externally powered. + * + * To enable the bypass switch and short the DC-DC converter input to + * the DC-DC output, set the configuration option `SL_DEVICE_INIT_DCDC_BYPASS`. + * + * See **AN0948 Power Configurations and DC-DC** for further details about DC-DC + * converter configuration and operation. + * + * - Series 1: [AN0948](https://www.silabs.com/documents/public/application-notes/an0948-power-configurations-and-dcdc.pdf) + * - Series 2: [AN0948.2](https://www.silabs.com/documents/public/application-notes/an0948.2-efr32-series-2-power-configurations-and-dcdc.pdf) + * @{ + */ + +// ----------------------------------------------------------------------------- +// Defines + +/// @brief DC/DC Converter Type +#define SL_DEVICE_INIT_DCDC_TYPE_BUCK 0 ///< Buck Type +#define SL_DEVICE_INIT_DCDC_TYPE_BOOST 1 ///< Boost Type + +/** + * Initialize DCDC + * + * @details + * Configure and start the DCDC + * + * @return Status code + * @retval SL_STATUS_OK DC-DC converter initialized successfully + */ +sl_status_t sl_device_init_dcdc(void); + +/** + * @} device_init_dcdc + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_DCDC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h index 9743224..4d1ffe2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_emu.h @@ -1,89 +1,89 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for EMU. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_EMU_H -#define SL_DEVICE_INIT_EMU_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_emu EMU Initialization - * @brief Initialize the Energy Management Unit. - * @details - * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) - * according to settings in the configuration header - * `sl_device_init_emu_config.h`. - * - * On Series 2 devices, debugging in EM2 is enabled by default by ensuring - * that power to the debug power domain is sustained on EM2 entry. - * Debugging in EM2 can be disabled through the configuration header. If - * using Simplicity Studio, this header can also be configured using the - * Project Configurator by selecting the "Device Init: EMU" configuration - * component. - * - * @note Voltage scaling for Energy Modes 0 to 3 are configured by the - * @ref power_manager. - * @{ - */ - -/** - * Initialize EMU - * - * @details - * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) - * according to settings in the configuration header - * `sl_device_init_emu_config.h`. - * - * On Series 2 devices, debugging in EM2 is enabled by default by ensuring - * that power to the debug power domain is sustained on EM2 entry. - * - * @note Voltage scaling for Energy Modes 0 to 3 are configured by the - * @ref power_manager. - * - * @return Status code - * @retval SL_STATUS_OK EMU initialized successfully - */ -sl_status_t sl_device_init_emu(void); - -/** - * @} device_init_emu - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_EMU_H +/***************************************************************************//** + * @file + * @brief Device initialization for EMU. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_EMU_H +#define SL_DEVICE_INIT_EMU_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_emu EMU Initialization + * @brief Initialize the Energy Management Unit. + * @details + * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) + * according to settings in the configuration header + * `sl_device_init_emu_config.h`. + * + * On Series 2 devices, debugging in EM2 is enabled by default by ensuring + * that power to the debug power domain is sustained on EM2 entry. + * Debugging in EM2 can be disabled through the configuration header. If + * using Simplicity Studio, this header can also be configured using the + * Project Configurator by selecting the "Device Init: EMU" configuration + * component. + * + * @note Voltage scaling for Energy Modes 0 to 3 are configured by the + * @ref power_manager. + * @{ + */ + +/** + * Initialize EMU + * + * @details + * Initializes the Energy Management Unit by configuring Energy Mode 4 (EM4) + * according to settings in the configuration header + * `sl_device_init_emu_config.h`. + * + * On Series 2 devices, debugging in EM2 is enabled by default by ensuring + * that power to the debug power domain is sustained on EM2 entry. + * + * @note Voltage scaling for Energy Modes 0 to 3 are configured by the + * @ref power_manager. + * + * @return Status code + * @retval SL_STATUS_OK EMU initialized successfully + */ +sl_status_t sl_device_init_emu(void); + +/** + * @} device_init_emu + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_EMU_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h index cb97a3f..d9f2dfc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_hfxo.h @@ -1,88 +1,88 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for HFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_HFXO_H -#define SL_DEVICE_INIT_HFXO_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_hfxo HFXO Initialization - * @brief Initialize the HFXO oscillator. - * @details - * Configure the HFXO for crystal or externally-generated waveform operation. - * - * When operating in crystal mode, the value of the variable tuning capacitor - * Ctune is sourced from a prioritized list of locations: - * - * 1. Device-specific tuning value in Device Information page (factory calibrated PCB and SiP modules with integrated HFXO) - * 2. Device-specific tuning value in User Data page at offset 0x100 (manufacturing token `TOKEN_MFG_CTUNE`) - * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` - * 4. Default value in EMLIB initialization struct for HFXO - * - * If using Simplicity Studio, this configuration header is also configurable through the Project Configurator by selecting the - * "Device Init: HFXO" configuration component. - * @{ - */ - -/** - * Initialize HFXO - * - * @details - * Configure the HFXO for crystal or externally-generated waveform operation. - * - * When operating in crystal mode, the value of the variable tuning capacitor - * Ctune is sourced from a prioritized list of locations: - * - * 1. Device-specific tuning value in Device Information page (PCB and SiP modules with integrated HFXO) - * 2. Device-specific tuning value in User Data page at offset 0x100 ("manufacturing token") - * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` - * 4. Default value in EMLIB initialization struct for HFXO - * - * @return Status code - * @retval SL_STATUS_OK HFXO started successfully - */ -sl_status_t sl_device_init_hfxo(void); - -/** - * @} device_init_hfxo - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_HFXO_H +/***************************************************************************//** + * @file + * @brief Device initialization for HFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_HFXO_H +#define SL_DEVICE_INIT_HFXO_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_hfxo HFXO Initialization + * @brief Initialize the HFXO oscillator. + * @details + * Configure the HFXO for crystal or externally-generated waveform operation. + * + * When operating in crystal mode, the value of the variable tuning capacitor + * Ctune is sourced from a prioritized list of locations: + * + * 1. Device-specific tuning value in Device Information page (factory calibrated PCB and SiP modules with integrated HFXO) + * 2. Device-specific tuning value in User Data page at offset 0x100 (manufacturing token `TOKEN_MFG_CTUNE`) + * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` + * 4. Default value in EMLIB initialization struct for HFXO + * + * If using Simplicity Studio, this configuration header is also configurable through the Project Configurator by selecting the + * "Device Init: HFXO" configuration component. + * @{ + */ + +/** + * Initialize HFXO + * + * @details + * Configure the HFXO for crystal or externally-generated waveform operation. + * + * When operating in crystal mode, the value of the variable tuning capacitor + * Ctune is sourced from a prioritized list of locations: + * + * 1. Device-specific tuning value in Device Information page (PCB and SiP modules with integrated HFXO) + * 2. Device-specific tuning value in User Data page at offset 0x100 ("manufacturing token") + * 3. Application-specific tuning value in configuration header `sl_device_init_hfxo_config.h` + * 4. Default value in EMLIB initialization struct for HFXO + * + * @return Status code + * @retval SL_STATUS_OK HFXO started successfully + */ +sl_status_t sl_device_init_hfxo(void); + +/** + * @} device_init_hfxo + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_HFXO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfrco.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfrco.h index a026b34..b4bd451 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfrco.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfrco.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFRCO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_LFRCO_H -#define SL_DEVICE_INIT_LFRCO_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_lfrco LFRCO Initialization - * @brief Initialize the LFRCO oscillator. - * @details - * Initialize the low frequency RC oscillator. On Series 2 devices with - * precision mode support, the precision mode is configured in the configuration - * header `sl_device_init_lfrco_config.h`. On other devices, there is nothing - * to configure. - * - * If using Simplicity Studio, this configuration header is also configurable - * through the Project Configurator, by selecting the "Device Init: LFRCO" - * configuration component. - * @{ - */ - -/** - * Initialize LFRCO - * - * @details - * Initialize the low frequency RC oscillator. On devices that support - * high precision mode, this function configures the precision mode based - * on the configuration option SL_DEVICE_INIT_LFRCO_PRECISION. - * - * @return Status code - * @retval SL_STATUS_OK LFRCO initialized successfully - */ -sl_status_t sl_device_init_lfrco(void); - -/** - * @} device_init_lfrco - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_LFRCO_H +/***************************************************************************//** + * @file + * @brief Device initialization for LFRCO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_LFRCO_H +#define SL_DEVICE_INIT_LFRCO_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_lfrco LFRCO Initialization + * @brief Initialize the LFRCO oscillator. + * @details + * Initialize the low frequency RC oscillator. On Series 2 devices with + * precision mode support, the precision mode is configured in the configuration + * header `sl_device_init_lfrco_config.h`. On other devices, there is nothing + * to configure. + * + * If using Simplicity Studio, this configuration header is also configurable + * through the Project Configurator, by selecting the "Device Init: LFRCO" + * configuration component. + * @{ + */ + +/** + * Initialize LFRCO + * + * @details + * Initialize the low frequency RC oscillator. On devices that support + * high precision mode, this function configures the precision mode based + * on the configuration option SL_DEVICE_INIT_LFRCO_PRECISION. + * + * @return Status code + * @retval SL_STATUS_OK LFRCO initialized successfully + */ +sl_status_t sl_device_init_lfrco(void); + +/** + * @} device_init_lfrco + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_LFRCO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h index 6cbd57a..c2cff36 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_lfxo.h @@ -1,85 +1,85 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_LFXO_H -#define SL_DEVICE_INIT_LFXO_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_lfxo LFXO Initialization - * @brief Initialize the LFXO oscillator. - * @details - * Configure the low frequency crystal oscillator using settings in the - * configuration header `sl_device_init_lfxo_config.h`. - * - * The precision of the oscillator can be indicated using the configuration - * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless - * stacks to optimize wakeup time for scheduled events (such as Bluetooth - * advertising). - * - * If using Simplicity Studio, this configuration header is also configurable - * through the Project Configurator by selecting the "Device Init: LFXO" - * configuration component. - * @{ - */ - -/** - * Initialize LFXO - * - * @details - * Configure the low frequency crystal oscillator using settings in the - * configuration header `sl_device_init_lfxo_config.h`. - * - * The precision of the oscillator can be indicated using the configuration - * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless - * stacks to optimize wakeup time for scheduled events (such as Bluetooth - * advertising). - * - * @return Status code - * @retval SL_STATUS_OK LFXO initialized successfully - */ -sl_status_t sl_device_init_lfxo(void); - -/** - * @} device_init_lfxo - * @} device_init - */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_DEVICE_INIT_LFXO_H +/***************************************************************************//** + * @file + * @brief Device initialization for LFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_LFXO_H +#define SL_DEVICE_INIT_LFXO_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_lfxo LFXO Initialization + * @brief Initialize the LFXO oscillator. + * @details + * Configure the low frequency crystal oscillator using settings in the + * configuration header `sl_device_init_lfxo_config.h`. + * + * The precision of the oscillator can be indicated using the configuration + * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless + * stacks to optimize wakeup time for scheduled events (such as Bluetooth + * advertising). + * + * If using Simplicity Studio, this configuration header is also configurable + * through the Project Configurator by selecting the "Device Init: LFXO" + * configuration component. + * @{ + */ + +/** + * Initialize LFXO + * + * @details + * Configure the low frequency crystal oscillator using settings in the + * configuration header `sl_device_init_lfxo_config.h`. + * + * The precision of the oscillator can be indicated using the configuration + * option `SL_DEVICE_INIT_LFXO_PRECISION`. This is used by certain wireless + * stacks to optimize wakeup time for scheduled events (such as Bluetooth + * advertising). + * + * @return Status code + * @retval SL_STATUS_OK LFXO initialized successfully + */ +sl_status_t sl_device_init_lfxo(void); + +/** + * @} device_init_lfxo + * @} device_init + */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_DEVICE_INIT_LFXO_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h index be8a677..f200448 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/inc/sl_device_init_nvic.h @@ -1,70 +1,70 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for NVIC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_DEVICE_INIT_NVIC_H -#define SL_DEVICE_INIT_NVIC_H - -#include "sl_status.h" - -/** - * @addtogroup device_init - * @{ - * @addtogroup device_init_nvic NVIC Initialization - * @brief Initialize the NVIC Interrupt Handlers priority. - * @details - * Set all interrupt priorities, except the Fault exceptions, to - * `CORE_INTERRUPT_DEFAULT_PRIORITY` value. - * - * When the Device Init NVIC module is present and no configuration overwrites - * the em_core `CORE_ATOMIC_METHOD` define, the atomic method is automatically - * set to BASEPRI (`CORE_ATOMIC_METHOD_BASEPRI`). - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Sets default priority for all configurable interrupts in NVIC. - * - * @return Status code - ******************************************************************************/ -sl_status_t sl_device_init_nvic(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} device_init_nvic - * @} device_init - */ - -#endif // SL_DEVICE_INIT_NVIC_H +/***************************************************************************//** + * @file + * @brief Device initialization for NVIC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_DEVICE_INIT_NVIC_H +#define SL_DEVICE_INIT_NVIC_H + +#include "sl_status.h" + +/** + * @addtogroup device_init + * @{ + * @addtogroup device_init_nvic NVIC Initialization + * @brief Initialize the NVIC Interrupt Handlers priority. + * @details + * Set all interrupt priorities, except the Fault exceptions, to + * `CORE_INTERRUPT_DEFAULT_PRIORITY` value. + * + * When the Device Init NVIC module is present and no configuration overwrites + * the em_core `CORE_ATOMIC_METHOD` define, the atomic method is automatically + * set to BASEPRI (`CORE_ATOMIC_METHOD_BASEPRI`). + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Sets default priority for all configurable interrupts in NVIC. + * + * @return Status code + ******************************************************************************/ +sl_status_t sl_device_init_nvic(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} device_init_nvic + * @} device_init + */ + +#endif // SL_DEVICE_INIT_NVIC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c index 5227eb4..c5a1005 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_dcdc_s2.c @@ -1,57 +1,57 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for DC/DC converter. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_dcdc.h" -#include "sl_device_init_dcdc_config.h" - -#include "em_emu.h" - -sl_status_t sl_device_init_dcdc(void) -{ -#if !defined(SL_DEVICE_INIT_DCDC_TYPE) || (defined(SL_DEVICE_INIT_DCDC_TYPE) && (SL_DEVICE_INIT_DCDC_TYPE == SL_DEVICE_INIT_DCDC_TYPE_BUCK)) -#if SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; -#if SL_DEVICE_INIT_DCDC_BYPASS - dcdcInit.mode = emuDcdcMode_Bypass; -#endif - EMU_DCDCInit(&dcdcInit); -#if SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE - EMU_DCDCSetPFMXModePeakCurrent(SL_DEVICE_INIT_DCDC_PFMX_IPKVAL); -#endif -#else // SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCPowerOff(); -#endif // SL_DEVICE_INIT_DCDC_ENABLE -#else // SL_DEVICE_INIT_DCDC_TYPE -#if SL_DEVICE_INIT_DCDC_ENABLE - EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; - EMU_DCDCBoostInit(&dcdcBoostInit); -#endif -#endif //SL_DEVICE_INIT_DCDC_TYPE - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for DC/DC converter. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_dcdc.h" +#include "sl_device_init_dcdc_config.h" + +#include "em_emu.h" + +sl_status_t sl_device_init_dcdc(void) +{ +#if !defined(SL_DEVICE_INIT_DCDC_TYPE) || (defined(SL_DEVICE_INIT_DCDC_TYPE) && (SL_DEVICE_INIT_DCDC_TYPE == SL_DEVICE_INIT_DCDC_TYPE_BUCK)) +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT; +#if SL_DEVICE_INIT_DCDC_BYPASS + dcdcInit.mode = emuDcdcMode_Bypass; +#endif + EMU_DCDCInit(&dcdcInit); +#if SL_DEVICE_INIT_DCDC_PFMX_IPKVAL_OVERRIDE + EMU_DCDCSetPFMXModePeakCurrent(SL_DEVICE_INIT_DCDC_PFMX_IPKVAL); +#endif +#else // SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCPowerOff(); +#endif // SL_DEVICE_INIT_DCDC_ENABLE +#else // SL_DEVICE_INIT_DCDC_TYPE +#if SL_DEVICE_INIT_DCDC_ENABLE + EMU_DCDCBoostInit_TypeDef dcdcBoostInit = EMU_DCDCBOOSTINIT_DEFAULT; + EMU_DCDCBoostInit(&dcdcBoostInit); +#endif +#endif //SL_DEVICE_INIT_DCDC_TYPE + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c index cf54a76..042467e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_emu_s2.c @@ -1,49 +1,49 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for EMU. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_device_init_emu.h" -#include "sl_device_init_emu_config.h" - -#include "em_emu.h" - -sl_status_t sl_device_init_emu(void) -{ - // EM2 set debug enable - EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) - | (SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE << _EMU_CTRL_EM2DBGEN_SHIFT); - - // EM4 Init - EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; - - em4_init.pinRetentionMode = SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE; - EMU_EM4Init(&em4_init); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for EMU. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_device_init_emu.h" +#include "sl_device_init_emu_config.h" + +#include "em_emu.h" + +sl_status_t sl_device_init_emu(void) +{ + // EM2 set debug enable + EMU->CTRL = (EMU->CTRL & ~_EMU_CTRL_EM2DBGEN_MASK) + | (SL_DEVICE_INIT_EMU_EM2_DEBUG_ENABLE << _EMU_CTRL_EM2DBGEN_SHIFT); + + // EM4 Init + EMU_EM4Init_TypeDef em4_init = EMU_EM4INIT_DEFAULT; + + em4_init.pinRetentionMode = SL_DEVICE_INIT_EMU_EM4_PIN_RETENTION_MODE; + EMU_EM4Init(&em4_init); + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c index a65242b..673e17b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_hfxo_s2.c @@ -1,87 +1,87 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for HFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_hfxo.h" -#include "sl_device_init_hfxo_config.h" - -#include "em_cmu.h" - -// Fetch CTUNE value from USERDATA page as a manufacturing token -#define MFG_CTUNE_ADDR 0x0FE00100UL -#define MFG_CTUNE_VAL (*((uint16_t *) (MFG_CTUNE_ADDR))) - -sl_status_t sl_device_init_hfxo(void) -{ - CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; - hfxoInit.mode = SL_DEVICE_INIT_HFXO_MODE; - - if (SL_DEVICE_INIT_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { - hfxoInit = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; - } - - int ctune = -1; - -#if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) - // Use HFXO tuning value from DEVINFO if available (PCB modules) - if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { - ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; - } -#endif - - // Use HFXO tuning value from MFG token in UD page if not already set - if ((ctune == -1) && (MFG_CTUNE_VAL != 0xFFFF)) { - ctune = MFG_CTUNE_VAL; - } - - // Use HFXO tuning value from configuration header as fallback - if (ctune == -1) { - ctune = SL_DEVICE_INIT_HFXO_CTUNE; - } - - // Configure CTUNE XI and XO. - if (ctune != -1) { - hfxoInit.ctuneXiAna = (uint8_t)ctune; - - // Ensure CTUNE XO plus a delta is within the correct range. The delta accounts for internal chip - // load imbalance on some series 2 chips. - ctune += CMU_HFXOCTuneDeltaGet(); - if (ctune < 0) { - ctune = 0; - } else if (ctune > ((int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT))) { - ctune = (int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); - } - hfxoInit.ctuneXoAna = (uint8_t)ctune; - } - - SystemHFXOClockSet(SL_DEVICE_INIT_HFXO_FREQ); - CMU_HFXOInit(&hfxoInit); - CMU_HFXOPrecisionSet(SL_DEVICE_INIT_HFXO_PRECISION); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for HFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_hfxo.h" +#include "sl_device_init_hfxo_config.h" + +#include "em_cmu.h" + +// Fetch CTUNE value from USERDATA page as a manufacturing token +#define MFG_CTUNE_ADDR 0x0FE00100UL +#define MFG_CTUNE_VAL (*((uint16_t *) (MFG_CTUNE_ADDR))) + +sl_status_t sl_device_init_hfxo(void) +{ + CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; + hfxoInit.mode = SL_DEVICE_INIT_HFXO_MODE; + + if (SL_DEVICE_INIT_HFXO_MODE == cmuHfxoOscMode_ExternalSine) { + hfxoInit = (CMU_HFXOInit_TypeDef)CMU_HFXOINIT_EXTERNAL_SINE; + } + + int ctune = -1; + +#if defined(_DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) + // Use HFXO tuning value from DEVINFO if available (PCB modules) + if ((DEVINFO->MODULEINFO & _DEVINFO_MODULEINFO_HFXOCALVAL_MASK) == 0) { + ctune = DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK; + } +#endif + + // Use HFXO tuning value from MFG token in UD page if not already set + if ((ctune == -1) && (MFG_CTUNE_VAL != 0xFFFF)) { + ctune = MFG_CTUNE_VAL; + } + + // Use HFXO tuning value from configuration header as fallback + if (ctune == -1) { + ctune = SL_DEVICE_INIT_HFXO_CTUNE; + } + + // Configure CTUNE XI and XO. + if (ctune != -1) { + hfxoInit.ctuneXiAna = (uint8_t)ctune; + + // Ensure CTUNE XO plus a delta is within the correct range. The delta accounts for internal chip + // load imbalance on some series 2 chips. + ctune += CMU_HFXOCTuneDeltaGet(); + if (ctune < 0) { + ctune = 0; + } else if (ctune > ((int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT))) { + ctune = (int)(_HFXO_XTALCTRL_CTUNEXOANA_MASK >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT); + } + hfxoInit.ctuneXoAna = (uint8_t)ctune; + } + + SystemHFXOClockSet(SL_DEVICE_INIT_HFXO_FREQ); + CMU_HFXOInit(&hfxoInit); + CMU_HFXOPrecisionSet(SL_DEVICE_INIT_HFXO_PRECISION); + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfrco.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfrco.c index 77301b6..18d5ca7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfrco.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfrco.c @@ -1,66 +1,66 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFRCO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_lfrco.h" -#include "em_cmu.h" - -#if defined(_SILICON_LABS_32B_SERIES_1) -#include "sl_device_init_lfrco_config.h" -#elif defined(_SILICON_LABS_32B_SERIES_2) && defined(PLFRCO_PRESENT) -#include "sl_device_init_lfrco_config.h" -#endif - -sl_status_t sl_device_init_lfrco(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) && defined(PLFRCO_PRESENT) - CMU_LFRCOSetPrecision(SL_DEVICE_INIT_LFRCO_PRECISION); -#endif - -#if defined(_SILICON_LABS_32B_SERIES_1) -#if SL_DEVICE_INIT_LFRCO_ENVREF == 0 - CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENVREF); -#else - CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENVREF; -#endif - -#if SL_DEVICE_INIT_LFRCO_ENCHOP == 0 - CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENCHOP); -#else - CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENCHOP; -#endif - -#if SL_DEVICE_INIT_LFRCO_ENDEM == 0 - CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENDEM); -#else - CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENDEM; -#endif -#endif // defined(_SILICON_LABS_32B_SERIES_1) - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for LFRCO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_lfrco.h" +#include "em_cmu.h" + +#if defined(_SILICON_LABS_32B_SERIES_1) +#include "sl_device_init_lfrco_config.h" +#elif defined(_SILICON_LABS_32B_SERIES_2) && defined(PLFRCO_PRESENT) +#include "sl_device_init_lfrco_config.h" +#endif + +sl_status_t sl_device_init_lfrco(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) && defined(PLFRCO_PRESENT) + CMU_LFRCOSetPrecision(SL_DEVICE_INIT_LFRCO_PRECISION); +#endif + +#if defined(_SILICON_LABS_32B_SERIES_1) +#if SL_DEVICE_INIT_LFRCO_ENVREF == 0 + CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENVREF); +#else + CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENVREF; +#endif + +#if SL_DEVICE_INIT_LFRCO_ENCHOP == 0 + CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENCHOP); +#else + CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENCHOP; +#endif + +#if SL_DEVICE_INIT_LFRCO_ENDEM == 0 + CMU->LFRCOCTRL &= ~(CMU_LFRCOCTRL_ENDEM); +#else + CMU->LFRCOCTRL |= CMU_LFRCOCTRL_ENDEM; +#endif +#endif // defined(_SILICON_LABS_32B_SERIES_1) + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c index b3a7669..a7821c0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_lfxo_s2.c @@ -1,47 +1,47 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for LFXO. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_device_init_lfxo.h" -#include "sl_device_init_lfxo_config.h" - -#include "em_cmu.h" - -sl_status_t sl_device_init_lfxo(void) -{ - CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; - - lfxoInit.mode = SL_DEVICE_INIT_LFXO_MODE; - lfxoInit.capTune = SL_DEVICE_INIT_LFXO_CTUNE; - lfxoInit.timeout = SL_DEVICE_INIT_LFXO_TIMEOUT; - - CMU_LFXOInit(&lfxoInit); - CMU_LFXOPrecisionSet(SL_DEVICE_INIT_LFXO_PRECISION); - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for LFXO. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_device_init_lfxo.h" +#include "sl_device_init_lfxo_config.h" + +#include "em_cmu.h" + +sl_status_t sl_device_init_lfxo(void) +{ + CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; + + lfxoInit.mode = SL_DEVICE_INIT_LFXO_MODE; + lfxoInit.capTune = SL_DEVICE_INIT_LFXO_CTUNE; + lfxoInit.timeout = SL_DEVICE_INIT_LFXO_TIMEOUT; + + CMU_LFXOInit(&lfxoInit); + CMU_LFXOPrecisionSet(SL_DEVICE_INIT_LFXO_PRECISION); + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c index 2386a2f..ba08abe 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/device_init/src/sl_device_init_nvic.c @@ -1,46 +1,46 @@ -/***************************************************************************//** - * @file - * @brief Device initialization for NVIC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_status.h" -#include "em_device.h" -#include "em_core.h" - -/***************************************************************************//** - * Sets default priority for all configurable interrupts in NVIC. - * - * @note Fault exceptions are let at priority 0. - ******************************************************************************/ -sl_status_t sl_device_init_nvic(void) -{ - for (IRQn_Type i = SVCall_IRQn; i < EXT_IRQ_COUNT; i++) { - NVIC_SetPriority(i, CORE_INTERRUPT_DEFAULT_PRIORITY); - } - - return SL_STATUS_OK; -} +/***************************************************************************//** + * @file + * @brief Device initialization for NVIC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_status.h" +#include "em_device.h" +#include "em_core.h" + +/***************************************************************************//** + * Sets default priority for all configurable interrupts in NVIC. + * + * @note Fault exceptions are let at priority 0. + ******************************************************************************/ +sl_status_t sl_device_init_nvic(void) +{ + for (IRQn_Type i = SVCall_IRQn; i < EXT_IRQ_COUNT; i++) { + NVIC_SetPriority(i, CORE_INTERRUPT_DEFAULT_PRIORITY); + } + + return SL_STATUS_OK; +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h index 013fb81..22e0d76 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/inc/sl_mpu.h @@ -1,87 +1,87 @@ -/***************************************************************************//** - * @file - * @brief MPU API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup mpu RAM execution disable - * @brief RAM execution disable utilities can be used to disable execution from - * RAM and other selected memory regions. - * @details - * RAM execution disable utilities are useful to protect against code injection attacks. - * These utilities make use of MPU to disable execution from RAM and other selected - * memory regions. - * - * @{ - ******************************************************************************/ - -#ifndef SL_MPU_H -#define SL_MPU_H - -#include "sl_status.h" - -#if (defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) || defined(DOXYGEN) - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Configures internal SRAM as non-executable and enable MPU. - * - * @note This function configures the MPU in order to make the entire RAM as - * non-executable (with the exception of the functions marked as ramfunc). - ******************************************************************************/ -void sl_mpu_disable_execute_from_ram(void); - -/***************************************************************************//** - * Configures an address range as non-executable and enable MPU. - * - * @note Configures a MPU region in order to make an address range as - * non-executable. The memory region must have a size of at least 32 bytes. - * - * @param address_begin Beginning of memory segment. - * - * @param address_end End of memory segment. - * - * @param size Size of memory segment. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_mpu_disable_execute(uint32_t address_begin, - uint32_t address_end, - uint32_t size); - -#ifdef __cplusplus -} -#endif - -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ -#endif /* SL_MPU_H */ - -/** @} (end addtogroup mpu) */ +/***************************************************************************//** + * @file + * @brief MPU API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup mpu RAM execution disable + * @brief RAM execution disable utilities can be used to disable execution from + * RAM and other selected memory regions. + * @details + * RAM execution disable utilities are useful to protect against code injection attacks. + * These utilities make use of MPU to disable execution from RAM and other selected + * memory regions. + * + * @{ + ******************************************************************************/ + +#ifndef SL_MPU_H +#define SL_MPU_H + +#include "sl_status.h" + +#if (defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)) || defined(DOXYGEN) + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Configures internal SRAM as non-executable and enable MPU. + * + * @note This function configures the MPU in order to make the entire RAM as + * non-executable (with the exception of the functions marked as ramfunc). + ******************************************************************************/ +void sl_mpu_disable_execute_from_ram(void); + +/***************************************************************************//** + * Configures an address range as non-executable and enable MPU. + * + * @note Configures a MPU region in order to make an address range as + * non-executable. The memory region must have a size of at least 32 bytes. + * + * @param address_begin Beginning of memory segment. + * + * @param address_end End of memory segment. + * + * @param size Size of memory segment. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +#endif /* SL_MPU_H */ + +/** @} (end addtogroup mpu) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c index f0198f2..0d56019 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/mpu/src/sl_mpu.c @@ -1,403 +1,403 @@ -/***************************************************************************//** - * @file - * @brief MPU API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "em_device.h" - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "sl_common.h" -#include "em_core.h" -#include "sl_mpu.h" -#include -#include - -#define MPU_RBAR_VALUE ARM_MPU_RBAR(0u, ARM_MPU_SH_NON, 0, 1, 1) - -// ARM memory map SRAM location and size. -#define MPU_ARM_SRAM_MEM_BASE 0x20000000 -#define MPU_ARM_SRAM_MEM_SIZE 0x20000000 - -// Number of sub-regions per MPU region. -#define MPU_SUBREGION_NBR 8u - -// Minimum size of a MPU region to use sub-regions disable feature. -#define MPU_SUBREGION_USE_MIN_SIZE 256u - -// Pre-defined MPU regions. -#define MPU_RAM_BACKGROUND_XN_REGION_NBR 0u -#define MPU_RAM_FUNCTION_REGION_NBR 1u - -#if defined(__ICCARM__) -// iccarm -#pragma section = ".textrw" -#define RAMFUNC_SECTION_BEGIN ((uint32_t)(uint32_t *)__section_begin(".textrw")) -#define RAMFUNC_SECTION_END ((uint32_t)(uint32_t *)__section_end(".textrw")) -#define RAMFUNC_SECTION_SIZE __section_size(".textrw") - -#elif defined(__GNUC__) -// armgcc -extern uint32_t __ram_func_section_start; -extern uint32_t __ram_func_section_end; -#define RAMFUNC_SECTION_BEGIN (uint32_t) &__ram_func_section_start -#define RAMFUNC_SECTION_END (uint32_t) &__ram_func_section_end -#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) - -#elif defined(__CC_ARM) -// armcc -// The section name in the armcc scatter file must be "ram_code". -extern uint32_t ram_code$$Base; -extern uint32_t ram_code$$Limit; -#define RAMFUNC_SECTION_BEGIN (uint32_t) &ram_code$$Base -#define RAMFUNC_SECTION_END (uint32_t) &ram_code$$Limit -#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) - -#endif - -#ifndef ARM_MPU_ARMV8_H -static uint32_t mpu_round_up_next_pwr2(uint32_t nbr); -static uint8_t mpu_region_size_encode(uint32_t region_size); -static void mpu_compute_region_data(uint32_t section_begin, - uint32_t section_end, - uint32_t section_size, - uint32_t *mpu_region_begin, - uint32_t *mpu_region_end, - uint32_t *mpu_region_size); - -#endif - -static uint32_t region_nbr = 0; - -/**************************************************************************//** - *****************************************************************************/ -void sl_mpu_disable_execute_from_ram(void) -{ - uint32_t mpu_region_begin = 0u; - uint32_t mpu_region_end = 0u; - - ARM_MPU_Disable(); - -#ifdef ARM_MPU_ARMV8_H - uint32_t rbar; - - // Region end address LSB are always considered 1F. - mpu_region_begin = MPU_ARM_SRAM_MEM_BASE; - mpu_region_end = (RAMFUNC_SECTION_SIZE > 0) ? (RAMFUNC_SECTION_BEGIN & MPU_RBAR_BASE_Msk) - 32u - : (MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE); - - ARM_MPU_SetMemAttr(0, ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), 0)); - - if (mpu_region_begin <= mpu_region_end) { - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); - region_nbr++; - } - - if (RAMFUNC_SECTION_SIZE > 0u) { - // Region end address LSB are always considered 1F. - mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; - mpu_region_end = MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE - 32u; - - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); - region_nbr++; - } -#else - uint8_t region_size_encoded; - uint32_t mpu_region_size; - - (void) mpu_region_begin; - (void) mpu_region_end; - - // Set background RAM region as execute never - region_size_encoded = mpu_region_size_encode(MPU_ARM_SRAM_MEM_SIZE); - ARM_MPU_SetRegionEx(region_nbr, - MPU_ARM_SRAM_MEM_BASE, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_XN_Msk - | MPU_RASR_ENABLE_Msk); - region_nbr++; - - // Set RAM functions region as executable - if (RAMFUNC_SECTION_SIZE > 0u) { - uint32_t sr_size; - uint8_t srd_msk; - - mpu_compute_region_data(RAMFUNC_SECTION_BEGIN, - RAMFUNC_SECTION_END, - RAMFUNC_SECTION_SIZE, - &mpu_region_begin, - &mpu_region_end, - &mpu_region_size); - - // Compute sub-region Disable (SRD) mask - sr_size = mpu_region_size / MPU_SUBREGION_NBR; - // Check if sr_size is zero to satisfy MISRA - sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; - srd_msk = (uint8_t)((1u << ((mpu_region_end - RAMFUNC_SECTION_END) / sr_size)) - 1u); - srd_msk = (uint8_t)(srd_msk << (((RAMFUNC_SECTION_END - mpu_region_begin - 1u) / sr_size) + 1u)); - srd_msk |= (1u << ((RAMFUNC_SECTION_BEGIN - mpu_region_begin) / sr_size)) - 1u; - - region_size_encoded = mpu_region_size_encode(mpu_region_size); - ARM_MPU_SetRegionEx(region_nbr, - mpu_region_begin, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_ENABLE_Msk - | (srd_msk << MPU_RASR_SRD_Pos)); - region_nbr++; - } -#endif - - // Enable MPU with default background region - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - __DSB(); - __ISB(); -} - -/**************************************************************************//** - * Enables simplified MPU driver. Configures memory address as non-executable. - *****************************************************************************/ -sl_status_t sl_mpu_disable_execute(uint32_t address_begin, - uint32_t address_end, - uint32_t size) -{ - uint32_t mpu_region_begin = 0u; - uint32_t mpu_region_end = 0u; - sl_status_t status = SL_STATUS_OK; - - ARM_MPU_Disable(); - -#ifdef ARM_MPU_ARMV8_H - uint32_t rbar; - uint8_t is_overlapping = 0u; - uint32_t prev_base_address = 0u; - uint32_t prev_limit_address = 0u; - - // Size of memory region must be 32 bytes or more. - if (size >= 32u) { - // Round inside the memory region, if address is not align on 32 bytes. - mpu_region_begin = ((address_begin % 32u) == 0u) ? address_begin - : (address_begin + (32u - (address_begin % 32u))); - - // Round inside the memory region, if address is not align on 32 bytes. - mpu_region_end = ((address_end % 32u) == 0u) ? address_end - : (address_end - (address_end % 32u)); - - // The scanning to check the overlapping region - for (uint8_t index_region = 0; index_region < region_nbr; index_region++) { - // Set to the previous region number - MPU->RNR = index_region; - - // Read the base address that was configured by the region number register before - prev_base_address = (MPU->RBAR & MPU_RBAR_BASE_Msk); - // Read the limit address that was configured by the region number register before - prev_limit_address = (MPU->RLAR & MPU_RLAR_LIMIT_Msk); - - // Check the overlapping region - if ((mpu_region_begin == prev_base_address) && (mpu_region_end == prev_limit_address)) { - // The new region is the same as the previous region - is_overlapping = 1; - status = SL_STATUS_OK; - } else if (!((mpu_region_begin > prev_limit_address) || (mpu_region_end < prev_base_address))) { - // The new region is invalid - is_overlapping = 1; - status = SL_STATUS_INVALID_RANGE; - } - - if (is_overlapping == 1) { - break; - } - - MPU->RNR &= ~MPU_RNR_REGION_Msk; - } - - if (!is_overlapping) { - // Device memory type non Gathering, non Re-ordering, Early Write Acknowledgment - ARM_MPU_SetMemAttr(1, ARM_MPU_ATTR_DEVICE_nGnRE); - - // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. - rbar = ARM_MPU_RBAR(0u, 0u, 0u, 1u, 1u) | (mpu_region_begin & MPU_RBAR_BASE_Msk); - ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 1u)); - region_nbr++; - } - } -#else - uint8_t region_size_encoded; - uint32_t mpu_region_size; - uint32_t sr_size; - uint8_t srd_msk; - - (void) mpu_region_begin; - (void) mpu_region_end; - - mpu_compute_region_data(address_begin, - address_end, - size, - &mpu_region_begin, - &mpu_region_end, - &mpu_region_size); - - // Compute sub-region Disable (SRD) mask - sr_size = mpu_region_size / MPU_SUBREGION_NBR; - // Check if sr_size is zero to satisfy MISRA - sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; - srd_msk = (uint8_t)((1u << (((mpu_region_end - address_end) + (sr_size - 1)) / sr_size)) - 1u); - srd_msk = (uint8_t)(srd_msk << ((address_end - mpu_region_begin - 1u) / sr_size)); - srd_msk |= (1u << (((address_begin - mpu_region_begin) + (sr_size - 1)) / sr_size)) - 1u; - - if (srd_msk == 0xFF) { - return SL_STATUS_INVALID_RANGE; - } - - // Set region as execute never. - region_size_encoded = mpu_region_size_encode(mpu_region_size); - ARM_MPU_SetRegionEx(region_nbr, - mpu_region_begin, - ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) - | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) - | MPU_RASR_B_Msk - | MPU_RASR_XN_Msk - | MPU_RASR_ENABLE_Msk - | (srd_msk << MPU_RASR_SRD_Pos)); - region_nbr++; -#endif - - // Enable MPU with default background region - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - __DSB(); - __ISB(); - - return status; -} - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Rounds up given number to next power of 2. - * - * @param nbr Number to round-up to next power of 2. - *****************************************************************************/ -static uint32_t mpu_round_up_next_pwr2(uint32_t nbr) -{ - nbr--; - nbr |= nbr >> 1; - nbr |= nbr >> 2; - nbr |= nbr >> 4; - nbr |= nbr >> 8; - nbr |= nbr >> 16; - nbr++; - - return nbr; -} -#endif - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Encode region size in RASR register REGION size field format. - * - * @param region_size Size of region. - *****************************************************************************/ -static uint8_t mpu_region_size_encode(uint32_t region_size) -{ - return (uint8_t)(30u - __CLZ(region_size)); -} -#endif - -#ifndef ARM_MPU_ARMV8_H -/**************************************************************************//** - * Compute region size. - * - * @param section_begin Section begin address. - * - * @param section_end Section end address. - * - * @param section_size Size of section. - * - * @param mpu_region_begin Pointer to a region begin variable. - * - * @param mpu_region_end Pointer to a region end variable. - * - * @param mpu_region_size Pointer to a region size variable. - *****************************************************************************/ -static void mpu_compute_region_data(uint32_t section_begin, - uint32_t section_end, - uint32_t section_size, - uint32_t *mpu_region_begin, - uint32_t *mpu_region_end, - uint32_t *mpu_region_size) -{ - uint32_t region_begin; - uint32_t region_end; - uint32_t region_size; - - // Compute MPU region size and begin address - region_size = mpu_round_up_next_pwr2(section_size); - region_size = (region_size < MPU_SUBREGION_USE_MIN_SIZE) ? MPU_SUBREGION_USE_MIN_SIZE : region_size; - - region_begin = section_begin & ~(region_size - 1u); - region_end = region_begin + region_size; - - while (region_end < section_end) { - region_size *= 2u; - region_begin = section_begin & ~(region_size - 1u); - region_end = region_begin + region_size; - } - - *mpu_region_begin = region_begin; - *mpu_region_end = region_end; - *mpu_region_size = region_size; -} -#endif - -#if __CORTEX_M != (0u) -/**************************************************************************//** - * MemManage default exception handler. Reset target. - *****************************************************************************/ -__WEAK void mpu_fault_handler(void) -{ - // Force fail assert to trigger reset - __NVIC_SystemReset(); -} - -/**************************************************************************//** - * MemManage exception handler. - *****************************************************************************/ -void MemManage_Handler(void) -{ - mpu_fault_handler(); -} -#endif - -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +/***************************************************************************//** + * @file + * @brief MPU API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "em_device.h" + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "sl_common.h" +#include "em_core.h" +#include "sl_mpu.h" +#include +#include + +#define MPU_RBAR_VALUE ARM_MPU_RBAR(0u, ARM_MPU_SH_NON, 0, 1, 1) + +// ARM memory map SRAM location and size. +#define MPU_ARM_SRAM_MEM_BASE 0x20000000 +#define MPU_ARM_SRAM_MEM_SIZE 0x20000000 + +// Number of sub-regions per MPU region. +#define MPU_SUBREGION_NBR 8u + +// Minimum size of a MPU region to use sub-regions disable feature. +#define MPU_SUBREGION_USE_MIN_SIZE 256u + +// Pre-defined MPU regions. +#define MPU_RAM_BACKGROUND_XN_REGION_NBR 0u +#define MPU_RAM_FUNCTION_REGION_NBR 1u + +#if defined(__ICCARM__) +// iccarm +#pragma section = ".textrw" +#define RAMFUNC_SECTION_BEGIN ((uint32_t)(uint32_t *)__section_begin(".textrw")) +#define RAMFUNC_SECTION_END ((uint32_t)(uint32_t *)__section_end(".textrw")) +#define RAMFUNC_SECTION_SIZE __section_size(".textrw") + +#elif defined(__GNUC__) +// armgcc +extern uint32_t __ram_func_section_start; +extern uint32_t __ram_func_section_end; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &__ram_func_section_start +#define RAMFUNC_SECTION_END (uint32_t) &__ram_func_section_end +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#elif defined(__CC_ARM) +// armcc +// The section name in the armcc scatter file must be "ram_code". +extern uint32_t ram_code$$Base; +extern uint32_t ram_code$$Limit; +#define RAMFUNC_SECTION_BEGIN (uint32_t) &ram_code$$Base +#define RAMFUNC_SECTION_END (uint32_t) &ram_code$$Limit +#define RAMFUNC_SECTION_SIZE (RAMFUNC_SECTION_END - RAMFUNC_SECTION_BEGIN) + +#endif + +#ifndef ARM_MPU_ARMV8_H +static uint32_t mpu_round_up_next_pwr2(uint32_t nbr); +static uint8_t mpu_region_size_encode(uint32_t region_size); +static void mpu_compute_region_data(uint32_t section_begin, + uint32_t section_end, + uint32_t section_size, + uint32_t *mpu_region_begin, + uint32_t *mpu_region_end, + uint32_t *mpu_region_size); + +#endif + +static uint32_t region_nbr = 0; + +/**************************************************************************//** + *****************************************************************************/ +void sl_mpu_disable_execute_from_ram(void) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + + ARM_MPU_Disable(); + +#ifdef ARM_MPU_ARMV8_H + uint32_t rbar; + + // Region end address LSB are always considered 1F. + mpu_region_begin = MPU_ARM_SRAM_MEM_BASE; + mpu_region_end = (RAMFUNC_SECTION_SIZE > 0) ? (RAMFUNC_SECTION_BEGIN & MPU_RBAR_BASE_Msk) - 32u + : (MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE); + + ARM_MPU_SetMemAttr(0, ARM_MPU_ATTR(ARM_MPU_ATTR_MEMORY_(1, 0, 1, 0), 0)); + + if (mpu_region_begin <= mpu_region_end) { + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); + region_nbr++; + } + + if (RAMFUNC_SECTION_SIZE > 0u) { + // Region end address LSB are always considered 1F. + mpu_region_begin = (RAMFUNC_SECTION_END + 31u) & MPU_RLAR_LIMIT_Msk; + mpu_region_end = MPU_ARM_SRAM_MEM_BASE + MPU_ARM_SRAM_MEM_SIZE - 32u; + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = MPU_RBAR_VALUE | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 0u)); + region_nbr++; + } +#else + uint8_t region_size_encoded; + uint32_t mpu_region_size; + + (void) mpu_region_begin; + (void) mpu_region_end; + + // Set background RAM region as execute never + region_size_encoded = mpu_region_size_encode(MPU_ARM_SRAM_MEM_SIZE); + ARM_MPU_SetRegionEx(region_nbr, + MPU_ARM_SRAM_MEM_BASE, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_XN_Msk + | MPU_RASR_ENABLE_Msk); + region_nbr++; + + // Set RAM functions region as executable + if (RAMFUNC_SECTION_SIZE > 0u) { + uint32_t sr_size; + uint8_t srd_msk; + + mpu_compute_region_data(RAMFUNC_SECTION_BEGIN, + RAMFUNC_SECTION_END, + RAMFUNC_SECTION_SIZE, + &mpu_region_begin, + &mpu_region_end, + &mpu_region_size); + + // Compute sub-region Disable (SRD) mask + sr_size = mpu_region_size / MPU_SUBREGION_NBR; + // Check if sr_size is zero to satisfy MISRA + sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; + srd_msk = (uint8_t)((1u << ((mpu_region_end - RAMFUNC_SECTION_END) / sr_size)) - 1u); + srd_msk = (uint8_t)(srd_msk << (((RAMFUNC_SECTION_END - mpu_region_begin - 1u) / sr_size) + 1u)); + srd_msk |= (1u << ((RAMFUNC_SECTION_BEGIN - mpu_region_begin) / sr_size)) - 1u; + + region_size_encoded = mpu_region_size_encode(mpu_region_size); + ARM_MPU_SetRegionEx(region_nbr, + mpu_region_begin, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_ENABLE_Msk + | (srd_msk << MPU_RASR_SRD_Pos)); + region_nbr++; + } +#endif + + // Enable MPU with default background region + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); +} + +/**************************************************************************//** + * Enables simplified MPU driver. Configures memory address as non-executable. + *****************************************************************************/ +sl_status_t sl_mpu_disable_execute(uint32_t address_begin, + uint32_t address_end, + uint32_t size) +{ + uint32_t mpu_region_begin = 0u; + uint32_t mpu_region_end = 0u; + sl_status_t status = SL_STATUS_OK; + + ARM_MPU_Disable(); + +#ifdef ARM_MPU_ARMV8_H + uint32_t rbar; + uint8_t is_overlapping = 0u; + uint32_t prev_base_address = 0u; + uint32_t prev_limit_address = 0u; + + // Size of memory region must be 32 bytes or more. + if (size >= 32u) { + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_begin = ((address_begin % 32u) == 0u) ? address_begin + : (address_begin + (32u - (address_begin % 32u))); + + // Round inside the memory region, if address is not align on 32 bytes. + mpu_region_end = ((address_end % 32u) == 0u) ? address_end + : (address_end - (address_end % 32u)); + + // The scanning to check the overlapping region + for (uint8_t index_region = 0; index_region < region_nbr; index_region++) { + // Set to the previous region number + MPU->RNR = index_region; + + // Read the base address that was configured by the region number register before + prev_base_address = (MPU->RBAR & MPU_RBAR_BASE_Msk); + // Read the limit address that was configured by the region number register before + prev_limit_address = (MPU->RLAR & MPU_RLAR_LIMIT_Msk); + + // Check the overlapping region + if ((mpu_region_begin == prev_base_address) && (mpu_region_end == prev_limit_address)) { + // The new region is the same as the previous region + is_overlapping = 1; + status = SL_STATUS_OK; + } else if (!((mpu_region_begin > prev_limit_address) || (mpu_region_end < prev_base_address))) { + // The new region is invalid + is_overlapping = 1; + status = SL_STATUS_INVALID_RANGE; + } + + if (is_overlapping == 1) { + break; + } + + MPU->RNR &= ~MPU_RNR_REGION_Msk; + } + + if (!is_overlapping) { + // Device memory type non Gathering, non Re-ordering, Early Write Acknowledgment + ARM_MPU_SetMemAttr(1, ARM_MPU_ATTR_DEVICE_nGnRE); + + // A bug exists in some versions of ARM_MPU_RBAR(). Set base addr manually. + rbar = ARM_MPU_RBAR(0u, 0u, 0u, 1u, 1u) | (mpu_region_begin & MPU_RBAR_BASE_Msk); + ARM_MPU_SetRegion(region_nbr, rbar, ARM_MPU_RLAR(mpu_region_end, 1u)); + region_nbr++; + } + } +#else + uint8_t region_size_encoded; + uint32_t mpu_region_size; + uint32_t sr_size; + uint8_t srd_msk; + + (void) mpu_region_begin; + (void) mpu_region_end; + + mpu_compute_region_data(address_begin, + address_end, + size, + &mpu_region_begin, + &mpu_region_end, + &mpu_region_size); + + // Compute sub-region Disable (SRD) mask + sr_size = mpu_region_size / MPU_SUBREGION_NBR; + // Check if sr_size is zero to satisfy MISRA + sr_size = (sr_size != 0) ? sr_size : MPU_SUBREGION_USE_MIN_SIZE / MPU_SUBREGION_NBR; + srd_msk = (uint8_t)((1u << (((mpu_region_end - address_end) + (sr_size - 1)) / sr_size)) - 1u); + srd_msk = (uint8_t)(srd_msk << ((address_end - mpu_region_begin - 1u) / sr_size)); + srd_msk |= (1u << (((address_begin - mpu_region_begin) + (sr_size - 1)) / sr_size)) - 1u; + + if (srd_msk == 0xFF) { + return SL_STATUS_INVALID_RANGE; + } + + // Set region as execute never. + region_size_encoded = mpu_region_size_encode(mpu_region_size); + ARM_MPU_SetRegionEx(region_nbr, + mpu_region_begin, + ((region_size_encoded << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) + | (ARM_MPU_AP_FULL << MPU_RASR_AP_Pos) + | MPU_RASR_B_Msk + | MPU_RASR_XN_Msk + | MPU_RASR_ENABLE_Msk + | (srd_msk << MPU_RASR_SRD_Pos)); + region_nbr++; +#endif + + // Enable MPU with default background region + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + __DSB(); + __ISB(); + + return status; +} + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Rounds up given number to next power of 2. + * + * @param nbr Number to round-up to next power of 2. + *****************************************************************************/ +static uint32_t mpu_round_up_next_pwr2(uint32_t nbr) +{ + nbr--; + nbr |= nbr >> 1; + nbr |= nbr >> 2; + nbr |= nbr >> 4; + nbr |= nbr >> 8; + nbr |= nbr >> 16; + nbr++; + + return nbr; +} +#endif + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Encode region size in RASR register REGION size field format. + * + * @param region_size Size of region. + *****************************************************************************/ +static uint8_t mpu_region_size_encode(uint32_t region_size) +{ + return (uint8_t)(30u - __CLZ(region_size)); +} +#endif + +#ifndef ARM_MPU_ARMV8_H +/**************************************************************************//** + * Compute region size. + * + * @param section_begin Section begin address. + * + * @param section_end Section end address. + * + * @param section_size Size of section. + * + * @param mpu_region_begin Pointer to a region begin variable. + * + * @param mpu_region_end Pointer to a region end variable. + * + * @param mpu_region_size Pointer to a region size variable. + *****************************************************************************/ +static void mpu_compute_region_data(uint32_t section_begin, + uint32_t section_end, + uint32_t section_size, + uint32_t *mpu_region_begin, + uint32_t *mpu_region_end, + uint32_t *mpu_region_size) +{ + uint32_t region_begin; + uint32_t region_end; + uint32_t region_size; + + // Compute MPU region size and begin address + region_size = mpu_round_up_next_pwr2(section_size); + region_size = (region_size < MPU_SUBREGION_USE_MIN_SIZE) ? MPU_SUBREGION_USE_MIN_SIZE : region_size; + + region_begin = section_begin & ~(region_size - 1u); + region_end = region_begin + region_size; + + while (region_end < section_end) { + region_size *= 2u; + region_begin = section_begin & ~(region_size - 1u); + region_end = region_begin + region_size; + } + + *mpu_region_begin = region_begin; + *mpu_region_end = region_end; + *mpu_region_size = region_size; +} +#endif + +#if __CORTEX_M != (0u) +/**************************************************************************//** + * MemManage default exception handler. Reset target. + *****************************************************************************/ +__WEAK void mpu_fault_handler(void) +{ + // Force fail assert to trigger reset + __NVIC_SystemReset(); +} + +/**************************************************************************//** + * MemManage exception handler. + *****************************************************************************/ +void MemManage_Handler(void) +{ + mpu_fault_handler(); +} +#endif + +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager.h index 321bcdc..f39a38b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager.h @@ -1,535 +1,535 @@ -/***************************************************************************//** - * @file - * @brief Power Manager API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_POWER_MANAGER_H -#define SL_POWER_MANAGER_H - -#ifndef SL_POWER_MANAGER_DEBUG -#include "sl_power_manager_config.h" -#endif -#include "sl_slist.h" -#include "sl_status.h" -#include "sl_sleeptimer.h" -#include "sl_enum.h" - -#include "em_core_generic.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup power_manager Power Manager - * - * @details Power manager is a platform level software module that manages - * the system's energy modes. Its main purpose is to transition the system to a - * low energy mode when the processor has nothing to execute. The energy mode the - * system will transition to is determined each time the system goes to sleep - * using requirements. These requirements are set by the different software modules - * (drivers, stacks, application code, etc...). Power manager also ensures a - * strict control of some power hungry resources such as the high frequency - * external oscillator (normally called HFXO). Power manager also - * offers a notification mechanism through which any piece of software module can be - * notified of energy mode transitions through callbacks. - * - * @note Sleep Driver is deprecated. Use Power Manager for all sleep-related - * operations. See AN1358: - * Migrating from Sleep Driver to Power Manager for information on how - * to migrate from Sleep Driver to Power Manager. - * @note Emlib EMU functions EMU_EnterEM1()/EMU_EnterEM2()/EMU_EnterEM3() must not - * be used when the Power Manager is present. The Power Manager module must be - * the one deciding at which EM level the device sleeps to ensure the application - * properly works. Using both at the same time could lead to undefined behavior - * in the application. - * - * @details - * ## Initialization - * - * Power manager must be initialized prior to any call to power manager API. - * If sl_system is used, only sl_system_init() must be called, otherwise - * sl_power_manager_init() must be called manually. Note that power manager - * must be initialized after the clock(s), when initialized manually, as the - * power manager check which oscillators are used during the initialization phase. - * - * ## Add and remove requirements - * - * The drivers should add and remove energy mode requirements, at runtime, on the - * lowest energy mode for them depending on their state. When calling - * sl_power_manager_sleep(), the lowest possible Energy mode will be automatically - * selected. - * - * It is possible to add and remove requirements from ISR. If a specific energy mode - * is required in the ISR, but not required to generate the interrupt, a requirement - * on the energy mode can be added from the ISR. It is guaranteed that the associated - * clock will be active once sl_power_manager_add_requirement() returns. The EM - * requirement can be also be removed from an ISR. - * - * ## Subscribe to events - * - * It possible to get notified when the system transition from a power level to - * another power level. This can allow to do some operations depending on which level - * the system goes, such as saving/restoring context. - * - * ## Sleep - * - * When the software has no more operation and only need to wait for an event, the - * software must call sl_power_manager_sleep(). This is automatically done when the - * kernel is present, but it needs to be called from the super loop in a baremetal - * project. - * - * ## Query callback functions - * - * ### Is OK to sleep - * - * Between the time `sl_power_manager_sleep` is called and the MCU is really put - * in a lower Energy mode, it is possible that an ISR occur and require the system - * to resume at that time instead of sleeping. So a callback is called in a critical - * section to validate that the MCU can go to sleep. - * - * In case of an application that runs on an RTOS, the RTOS will take care of determining - * if it is ok to sleep. In case of a baremetal application, the function `sl_power_manager_is_ok_to_sleep()` - * will be generated automatically by Simplicity Studio's wizard. - * The function will look at multiple software modules from the SDK to take a decision. - * The application can contribute to the decision by defining the function `app_is_ok_to_sleep()`. - * If any of the software modules (including the application via `app_is_ok_to_sleep()`) return false, - * the process of entering in sleep will be aborted. - * - * ### Sleep on ISR exit - * - * When the system enters sleep, the only way to wake it up is via an interrupt or - * exception. By default, power manager will assume that when an interrupt - * occurs and the corresponding ISR has been executed, the system must not go back - * to sleep. However, in the case where all the processing related to this interrupt - * is performed in the ISR, it is possible to go back to sleep by using this hook. - * - * In case of an application that runs on an RTOS, the RTOS will take care of determining - * if the system can go back to sleep on ISR exit. Power manager will ensure the system resumes - * its operations as soon as a task is resumed, posted or that its delay expires. - * In case of a baremetal application, the function `sl_power_manager_sleep_on_isr_exit()` will be generated - * automatically by Simplicity Studio's wizard. The function will look at multiple software modules from the SDK - * to take a decision. The application can contribute to the decision by defining the - * function `app_sleep_on_isr_exit()`. - * The generated function will take a decision based on the value returned by the different software modules - * (including the application via `app_sleep_on_isr_exit()`): - * - * `SL_POWER_MANAGER_IGNORE`: if the software module did not cause the system wakeup and/or doesn't want to contribute to the decision. - * `SL_POWER_MANAGER_SLEEP`: if the software module did cause the system wakeup, but the system should go back to sleep. - * `SL_POWER_MANAGER_WAKEUP`: if the software module did cause the system wakeup, and the system should not go back to sleep. - * - * If any software module returned `SL_POWER_MANAGER_SLEEP` and none returned `SL_POWER_MANAGER_WAKEUP`, - * the system will go back to sleep. Any other combination will cause the system not to go back to sleep. - * - * ### Debugging feature - * - * By setting the configuration define SL_POWER_MANAGER_DEBUG to 1, it is possible - * to record the requirements currently set and their owner. It is possible to print - * at any time a table that lists all the added requirements and their owner. This - * table can be printed by caling the function - * sl_power_manager_debug_print_em_requirements(). - * Make sure to add the following define - * ``` - * #define CURRENT_MODULE_NAME "" - * ``` - * to any application code source file that adds and removes requirements. - * - * ## Usage Example - * - * ``` - * #define EM_EVENT_MASK_ALL (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) - * - * sl_power_manager_em_transition_event_handle_t event_handle; - * sl_power_manager_em_transition_event_info_t event_info = { - * .event_mask = EM_EVENT_MASK_ALL, - * .on_event = my_events_callback, - * } - * - * void main(void) - * { - * // Initialize power manager; not needed if sl_system_init() is used. - * sl_power_manager_init(); - * - * // Limit sleep level to EM1 - * sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); - * - * // Subscribe to all event types; get notified for every power transition. - * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); - * while (1) { - * // Actions - * [...] - * if (completed) { - * // Remove energy mode requirement, can go to EM2 or EM3 now, depending on the configuration - * sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); - * } - * - * // Sleep to lowest possible energy mode; This call is not needed when using the kernel. - * sl_power_manager_sleep(); - * // Will resume after an interrupt or exception - * } - * } - * - * void my_events_callback(sl_power_manager_em_t from, - * sl_power_manager_em_t to) - * { - * printf("Event:%s-%s\r\n", string_lookup_table[from], string_lookup_table[to]); - * } - * ``` - * - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Defines - -// Current module name for debugging features -#ifndef CURRENT_MODULE_NAME -#define CURRENT_MODULE_NAME "Anonymous" ///< current module name -#endif - -// Power transition events -#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 (1 << 0) ///< sl power manager event transition entering em0 -#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 (1 << 1) ///< sl power manager event transition leaving em0 -#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 (1 << 2) ///< sl power manager event transition entering em1 -#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 (1 << 3) ///< sl power manager event transition leaving em1 -#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 (1 << 4) ///< sl power manager event transition entering em2 -#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 (1 << 5) ///< sl power manager event transition leaving em2 -#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 (1 << 6) ///< sl power manager event transition entering em3 -#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3 (1 << 7) ///< sl power manager event transition leaving em3 - -// ----------------------------------------------------------------------------- -// Data Types - -/// @brief Energy modes -typedef enum { - SL_POWER_MANAGER_EM0 = 0, ///< Run Mode (Energy Mode 0) - SL_POWER_MANAGER_EM1, ///< Sleep Mode (Energy Mode 1) - SL_POWER_MANAGER_EM2, ///< Deep Sleep Mode (Energy Mode 2) - SL_POWER_MANAGER_EM3, ///< Stop Mode (Energy Mode 3) - SL_POWER_MANAGER_EM4, ///< Shutoff Mode (Energy Mode 4) -} sl_power_manager_em_t; - -/// @brief Mask of all the event(s) to listen to. -typedef uint32_t sl_power_manager_em_transition_event_t; - -/***************************************************************************//** - * Typedef for the user supplied callback function which is called when - * an energy mode transition occurs. - * - * @param from Energy mode we are leaving. - * @param to Energy mode we are entering. - ******************************************************************************/ -typedef void (*sl_power_manager_em_transition_on_event_t)(sl_power_manager_em_t from, - sl_power_manager_em_t to); - -/// @brief Struct representing energy mode transition event information -typedef struct { - const sl_power_manager_em_transition_event_t event_mask; ///< Mask of the transitions on which the callback should be called. - const sl_power_manager_em_transition_on_event_t on_event; ///< Function that must be called when the event occurs. -} sl_power_manager_em_transition_event_info_t; - -/// @brief Struct representing energy mode transition event handle -typedef struct { - sl_slist_node_t node; ///< List node. - sl_power_manager_em_transition_event_info_t *info; ///< Handle event info. -} sl_power_manager_em_transition_event_handle_t; - -/// On ISR Exit Hook answer -SL_ENUM(sl_power_manager_on_isr_exit_t) { - SL_POWER_MANAGER_IGNORE = (1UL << 0UL), ///< The module did not trigger an ISR and it doesn't want to contribute to the decision - SL_POWER_MANAGER_SLEEP = (1UL << 1UL), ///< The module was the one that caused the system wakeup and the system SHOULD go back to sleep - SL_POWER_MANAGER_WAKEUP = (1UL << 2UL), ///< The module was the one that caused the system wakeup and the system MUST NOT go back to sleep -}; - -// ----------------------------------------------------------------------------- -// Internal Prototypes only to be used by Power Manager module -void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, - bool add); - -// To make sure that we are able to optimize out the string argument when the -// debug feature is disable, we use a pre-processor macro resulting in a no-op. -// We also make sure to always have a definition for the function regardless if -// the debug feature is enable or not for binary compatibility. -#if (SL_POWER_MANAGER_DEBUG == 1) -void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, - bool add, - const char *name); -#else -#define sli_power_manager_debug_log_em_requirement(em, add, name) /* no-op */ -#endif - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * Initialize Power Manager module. - * @return Status code - ******************************************************************************/ -sl_status_t sl_power_manager_init(void); - -/***************************************************************************//** - * Sleep at the lowest allowed energy mode. - * - * @note Must not be called from ISR - * @par - * @note This function will expect and call a callback with the following - * signature: `bool sl_power_manager_is_ok_to_sleep(void)`. - * - * @note This function can be used to cancel a sleep action and handle the - * possible race condition where an ISR that would cause a wakeup is - * triggered right after the decision to call sl_power_manager_sleep() - * has been made. - * - * @note This function must not be called with interrupts disabled. - * - * Usage example: - * - * ```c - * void main(void) - * { - * sl_power_manager_init(); - * while (1) { - * tick(); - * sl_power_manager_sleep(); - * } - * } - * ``` - ******************************************************************************/ -void sl_power_manager_sleep(void); - -/***************************************************************************//** - * Adds requirement on given energy mode. - * - * @param em Energy mode to add the requirement to: - * - ::SL_POWER_MANAGER_EM1 - * - ::SL_POWER_MANAGER_EM2 - ******************************************************************************/ -__STATIC_INLINE void sl_power_manager_add_em_requirement(sl_power_manager_em_t em) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - sli_power_manager_update_em_requirement(em, true); - - sli_power_manager_debug_log_em_requirement(em, true, (const char *)CURRENT_MODULE_NAME); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * Removes requirement on given energy mode. - * - * @param em Energy mode to remove the requirement to: - * - ::SL_POWER_MANAGER_EM1 - * - ::SL_POWER_MANAGER_EM2 - ******************************************************************************/ -__STATIC_INLINE void sl_power_manager_remove_em_requirement(sl_power_manager_em_t em) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - sli_power_manager_update_em_requirement(em, false); - - sli_power_manager_debug_log_em_requirement(em, false, (const char *)CURRENT_MODULE_NAME); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * Registers a callback to be called on given Energy Mode transition(s). - * - * @param event_handle Event handle (no initialization needed). - * - * @param event_info Event info structure that contains the event mask and the - * callback that must be called. - * - * @note Adding and removing requirement(s) from a callback on a transition event - * is not supported. - * - * @note The parameters passed must be persistent, meaning that they need to survive - * until the callback fires. - * - * Usage example: - * - * ```c - * #define EM_EVENT_MASK_ALL ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ - * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) - * - * sl_power_manager_em_transition_event_handle_t event_handle; - * sl_power_manager_em_transition_event_info_t event_info = { - * .event_mask = EM_EVENT_MASK_ALL, - * .on_event = my_callback, - * }; - * - * void my_callback(sl_power_manager_em_t from, - * sl_power_manager_em_t to) - * { - * [...] - * } - * - * void main(void) - * { - * sl_power_manager_init(); - * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); - * } - * ``` - ******************************************************************************/ -void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, - const sl_power_manager_em_transition_event_info_t *event_info); - -/***************************************************************************//** - * Unregisters an event callback handle on Energy mode transition. - * - * @param event_handle Event handle which must be unregistered (must have been - * registered previously). - * - * @note An EFM_ASSERT is thrown if the handle is not found. - ******************************************************************************/ -void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle); - -/***************************************************************************//** - * Get configurable overhead value for early restore time in Sleeptimer ticks - * when a schedule wake-up is set. - * - * @return Current overhead value for early restore time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void); - -/***************************************************************************//** - * Set configurable overhead value for early restore time in Sleeptimer ticks - * used for schedule wake-up. - * Must be called after initialization else the value will be overwritten. - * - * @param overhead_tick Overhead value to set for early restore time. - * - * @note The overhead value can also be negative to remove time from the restore - * process. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick); - -/***************************************************************************//** - * Get configurable minimum off-time value for schedule wake-up in Sleeptimer - * ticks. - * - * @return Current minimum off-time value for schedule wake-up. - * - * @note Turning on external high frequency clock, such as HFXO, requires more - * energy since we must supply higher current for the wake-up. - * Therefore, when an 'external high frequency clock enable' is scheduled - * in 'x' time, there is a threshold 'x' value where turning off the clock - * is not worthwhile since the energy consumed by taking into account the - * wake-up will be greater than if we just keep the clock on until the next - * scheduled clock enabled. This threshold value is what we refer as the - * minimum off-time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void); - -/***************************************************************************//** - * Set configurable minimum off-time value for schedule wake-up in Sleeptimer - * ticks. - * - * @param minimum_offtime_tick minimum off-time value to set for schedule - * wake-up. - * - * @note Turning on external high frequency clock, such as HFXO, requires more - * energy since we must supply higher current for the wake-up. - * Therefore, when an 'external high frequency clock enable' is scheduled - * in 'x' time, there is a threshold 'x' value where turning off the clock - * is not worthwhile since the energy consumed by taking into account the - * wake-up will be greater than if we just keep the clock on until the next - * scheduled clock enabled. This threshold value is what we refer as the - * minimum off-time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick); - -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3 - * - * @param enable True False variable act as a switch for this api - * - * @note Will also update the wake up time from EM2 to EM0. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); - -/**************************************************************************//** - * Determines if the HFXO interrupt was part of the last wake-up and/or if - * the HFXO early wakeup expired during the last ISR - * and if it was the only timer to expire in that period. - * - * @return true if power manager sleep can return to sleep, - * false otherwise. - * - * @note This function will always return false in case a requirement - * is added on SL_POWER_MANAGER_EM1, since we will - * never sleep at a lower level than EM1. - *****************************************************************************/ -bool sl_power_manager_is_latest_wakeup_internal(void); - -/** @} (end addtogroup power_manager) */ - -#ifdef __cplusplus -} -#endif - -#endif // SL_POWER_MANAGER_H +/***************************************************************************//** + * @file + * @brief Power Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_POWER_MANAGER_H +#define SL_POWER_MANAGER_H + +#ifndef SL_POWER_MANAGER_DEBUG +#include "sl_power_manager_config.h" +#endif +#include "sl_slist.h" +#include "sl_status.h" +#include "sl_sleeptimer.h" +#include "sl_enum.h" + +#include "em_core_generic.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup power_manager Power Manager + * + * @details Power manager is a platform level software module that manages + * the system's energy modes. Its main purpose is to transition the system to a + * low energy mode when the processor has nothing to execute. The energy mode the + * system will transition to is determined each time the system goes to sleep + * using requirements. These requirements are set by the different software modules + * (drivers, stacks, application code, etc...). Power manager also ensures a + * strict control of some power hungry resources such as the high frequency + * external oscillator (normally called HFXO). Power manager also + * offers a notification mechanism through which any piece of software module can be + * notified of energy mode transitions through callbacks. + * + * @note Sleep Driver is deprecated. Use Power Manager for all sleep-related + * operations. See AN1358: + * Migrating from Sleep Driver to Power Manager for information on how + * to migrate from Sleep Driver to Power Manager. + * @note Emlib EMU functions EMU_EnterEM1()/EMU_EnterEM2()/EMU_EnterEM3() must not + * be used when the Power Manager is present. The Power Manager module must be + * the one deciding at which EM level the device sleeps to ensure the application + * properly works. Using both at the same time could lead to undefined behavior + * in the application. + * + * @details + * ## Initialization + * + * Power manager must be initialized prior to any call to power manager API. + * If sl_system is used, only sl_system_init() must be called, otherwise + * sl_power_manager_init() must be called manually. Note that power manager + * must be initialized after the clock(s), when initialized manually, as the + * power manager check which oscillators are used during the initialization phase. + * + * ## Add and remove requirements + * + * The drivers should add and remove energy mode requirements, at runtime, on the + * lowest energy mode for them depending on their state. When calling + * sl_power_manager_sleep(), the lowest possible Energy mode will be automatically + * selected. + * + * It is possible to add and remove requirements from ISR. If a specific energy mode + * is required in the ISR, but not required to generate the interrupt, a requirement + * on the energy mode can be added from the ISR. It is guaranteed that the associated + * clock will be active once sl_power_manager_add_requirement() returns. The EM + * requirement can be also be removed from an ISR. + * + * ## Subscribe to events + * + * It possible to get notified when the system transition from a power level to + * another power level. This can allow to do some operations depending on which level + * the system goes, such as saving/restoring context. + * + * ## Sleep + * + * When the software has no more operation and only need to wait for an event, the + * software must call sl_power_manager_sleep(). This is automatically done when the + * kernel is present, but it needs to be called from the super loop in a baremetal + * project. + * + * ## Query callback functions + * + * ### Is OK to sleep + * + * Between the time `sl_power_manager_sleep` is called and the MCU is really put + * in a lower Energy mode, it is possible that an ISR occur and require the system + * to resume at that time instead of sleeping. So a callback is called in a critical + * section to validate that the MCU can go to sleep. + * + * In case of an application that runs on an RTOS, the RTOS will take care of determining + * if it is ok to sleep. In case of a baremetal application, the function `sl_power_manager_is_ok_to_sleep()` + * will be generated automatically by Simplicity Studio's wizard. + * The function will look at multiple software modules from the SDK to take a decision. + * The application can contribute to the decision by defining the function `app_is_ok_to_sleep()`. + * If any of the software modules (including the application via `app_is_ok_to_sleep()`) return false, + * the process of entering in sleep will be aborted. + * + * ### Sleep on ISR exit + * + * When the system enters sleep, the only way to wake it up is via an interrupt or + * exception. By default, power manager will assume that when an interrupt + * occurs and the corresponding ISR has been executed, the system must not go back + * to sleep. However, in the case where all the processing related to this interrupt + * is performed in the ISR, it is possible to go back to sleep by using this hook. + * + * In case of an application that runs on an RTOS, the RTOS will take care of determining + * if the system can go back to sleep on ISR exit. Power manager will ensure the system resumes + * its operations as soon as a task is resumed, posted or that its delay expires. + * In case of a baremetal application, the function `sl_power_manager_sleep_on_isr_exit()` will be generated + * automatically by Simplicity Studio's wizard. The function will look at multiple software modules from the SDK + * to take a decision. The application can contribute to the decision by defining the + * function `app_sleep_on_isr_exit()`. + * The generated function will take a decision based on the value returned by the different software modules + * (including the application via `app_sleep_on_isr_exit()`): + * + * `SL_POWER_MANAGER_IGNORE`: if the software module did not cause the system wakeup and/or doesn't want to contribute to the decision. + * `SL_POWER_MANAGER_SLEEP`: if the software module did cause the system wakeup, but the system should go back to sleep. + * `SL_POWER_MANAGER_WAKEUP`: if the software module did cause the system wakeup, and the system should not go back to sleep. + * + * If any software module returned `SL_POWER_MANAGER_SLEEP` and none returned `SL_POWER_MANAGER_WAKEUP`, + * the system will go back to sleep. Any other combination will cause the system not to go back to sleep. + * + * ### Debugging feature + * + * By setting the configuration define SL_POWER_MANAGER_DEBUG to 1, it is possible + * to record the requirements currently set and their owner. It is possible to print + * at any time a table that lists all the added requirements and their owner. This + * table can be printed by caling the function + * sl_power_manager_debug_print_em_requirements(). + * Make sure to add the following define + * ``` + * #define CURRENT_MODULE_NAME "" + * ``` + * to any application code source file that adds and removes requirements. + * + * ## Usage Example + * + * ``` + * #define EM_EVENT_MASK_ALL (SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) + * + * sl_power_manager_em_transition_event_handle_t event_handle; + * sl_power_manager_em_transition_event_info_t event_info = { + * .event_mask = EM_EVENT_MASK_ALL, + * .on_event = my_events_callback, + * } + * + * void main(void) + * { + * // Initialize power manager; not needed if sl_system_init() is used. + * sl_power_manager_init(); + * + * // Limit sleep level to EM1 + * sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); + * + * // Subscribe to all event types; get notified for every power transition. + * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); + * while (1) { + * // Actions + * [...] + * if (completed) { + * // Remove energy mode requirement, can go to EM2 or EM3 now, depending on the configuration + * sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); + * } + * + * // Sleep to lowest possible energy mode; This call is not needed when using the kernel. + * sl_power_manager_sleep(); + * // Will resume after an interrupt or exception + * } + * } + * + * void my_events_callback(sl_power_manager_em_t from, + * sl_power_manager_em_t to) + * { + * printf("Event:%s-%s\r\n", string_lookup_table[from], string_lookup_table[to]); + * } + * ``` + * + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Defines + +// Current module name for debugging features +#ifndef CURRENT_MODULE_NAME +#define CURRENT_MODULE_NAME "Anonymous" ///< current module name +#endif + +// Power transition events +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 (1 << 0) ///< sl power manager event transition entering em0 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 (1 << 1) ///< sl power manager event transition leaving em0 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 (1 << 2) ///< sl power manager event transition entering em1 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 (1 << 3) ///< sl power manager event transition leaving em1 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 (1 << 4) ///< sl power manager event transition entering em2 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 (1 << 5) ///< sl power manager event transition leaving em2 +#define SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 (1 << 6) ///< sl power manager event transition entering em3 +#define SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3 (1 << 7) ///< sl power manager event transition leaving em3 + +// ----------------------------------------------------------------------------- +// Data Types + +/// @brief Energy modes +typedef enum { + SL_POWER_MANAGER_EM0 = 0, ///< Run Mode (Energy Mode 0) + SL_POWER_MANAGER_EM1, ///< Sleep Mode (Energy Mode 1) + SL_POWER_MANAGER_EM2, ///< Deep Sleep Mode (Energy Mode 2) + SL_POWER_MANAGER_EM3, ///< Stop Mode (Energy Mode 3) + SL_POWER_MANAGER_EM4, ///< Shutoff Mode (Energy Mode 4) +} sl_power_manager_em_t; + +/// @brief Mask of all the event(s) to listen to. +typedef uint32_t sl_power_manager_em_transition_event_t; + +/***************************************************************************//** + * Typedef for the user supplied callback function which is called when + * an energy mode transition occurs. + * + * @param from Energy mode we are leaving. + * @param to Energy mode we are entering. + ******************************************************************************/ +typedef void (*sl_power_manager_em_transition_on_event_t)(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +/// @brief Struct representing energy mode transition event information +typedef struct { + const sl_power_manager_em_transition_event_t event_mask; ///< Mask of the transitions on which the callback should be called. + const sl_power_manager_em_transition_on_event_t on_event; ///< Function that must be called when the event occurs. +} sl_power_manager_em_transition_event_info_t; + +/// @brief Struct representing energy mode transition event handle +typedef struct { + sl_slist_node_t node; ///< List node. + sl_power_manager_em_transition_event_info_t *info; ///< Handle event info. +} sl_power_manager_em_transition_event_handle_t; + +/// On ISR Exit Hook answer +SL_ENUM(sl_power_manager_on_isr_exit_t) { + SL_POWER_MANAGER_IGNORE = (1UL << 0UL), ///< The module did not trigger an ISR and it doesn't want to contribute to the decision + SL_POWER_MANAGER_SLEEP = (1UL << 1UL), ///< The module was the one that caused the system wakeup and the system SHOULD go back to sleep + SL_POWER_MANAGER_WAKEUP = (1UL << 2UL), ///< The module was the one that caused the system wakeup and the system MUST NOT go back to sleep +}; + +// ----------------------------------------------------------------------------- +// Internal Prototypes only to be used by Power Manager module +void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, + bool add); + +// To make sure that we are able to optimize out the string argument when the +// debug feature is disable, we use a pre-processor macro resulting in a no-op. +// We also make sure to always have a definition for the function regardless if +// the debug feature is enable or not for binary compatibility. +#if (SL_POWER_MANAGER_DEBUG == 1) +void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, + bool add, + const char *name); +#else +#define sli_power_manager_debug_log_em_requirement(em, add, name) /* no-op */ +#endif + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Initialize Power Manager module. + * @return Status code + ******************************************************************************/ +sl_status_t sl_power_manager_init(void); + +/***************************************************************************//** + * Sleep at the lowest allowed energy mode. + * + * @note Must not be called from ISR + * @par + * @note This function will expect and call a callback with the following + * signature: `bool sl_power_manager_is_ok_to_sleep(void)`. + * + * @note This function can be used to cancel a sleep action and handle the + * possible race condition where an ISR that would cause a wakeup is + * triggered right after the decision to call sl_power_manager_sleep() + * has been made. + * + * @note This function must not be called with interrupts disabled. + * + * Usage example: + * + * ```c + * void main(void) + * { + * sl_power_manager_init(); + * while (1) { + * tick(); + * sl_power_manager_sleep(); + * } + * } + * ``` + ******************************************************************************/ +void sl_power_manager_sleep(void); + +/***************************************************************************//** + * Adds requirement on given energy mode. + * + * @param em Energy mode to add the requirement to: + * - ::SL_POWER_MANAGER_EM1 + * - ::SL_POWER_MANAGER_EM2 + ******************************************************************************/ +__STATIC_INLINE void sl_power_manager_add_em_requirement(sl_power_manager_em_t em) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_power_manager_update_em_requirement(em, true); + + sli_power_manager_debug_log_em_requirement(em, true, (const char *)CURRENT_MODULE_NAME); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Removes requirement on given energy mode. + * + * @param em Energy mode to remove the requirement to: + * - ::SL_POWER_MANAGER_EM1 + * - ::SL_POWER_MANAGER_EM2 + ******************************************************************************/ +__STATIC_INLINE void sl_power_manager_remove_em_requirement(sl_power_manager_em_t em) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sli_power_manager_update_em_requirement(em, false); + + sli_power_manager_debug_log_em_requirement(em, false, (const char *)CURRENT_MODULE_NAME); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Registers a callback to be called on given Energy Mode transition(s). + * + * @param event_handle Event handle (no initialization needed). + * + * @param event_info Event info structure that contains the event mask and the + * callback that must be called. + * + * @note Adding and removing requirement(s) from a callback on a transition event + * is not supported. + * + * @note The parameters passed must be persistent, meaning that they need to survive + * until the callback fires. + * + * Usage example: + * + * ```c + * #define EM_EVENT_MASK_ALL ( SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3 \ + * | SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3) + * + * sl_power_manager_em_transition_event_handle_t event_handle; + * sl_power_manager_em_transition_event_info_t event_info = { + * .event_mask = EM_EVENT_MASK_ALL, + * .on_event = my_callback, + * }; + * + * void my_callback(sl_power_manager_em_t from, + * sl_power_manager_em_t to) + * { + * [...] + * } + * + * void main(void) + * { + * sl_power_manager_init(); + * sl_power_manager_subscribe_em_transition_event(&event_handle, &event_info); + * } + * ``` + ******************************************************************************/ +void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, + const sl_power_manager_em_transition_event_info_t *event_info); + +/***************************************************************************//** + * Unregisters an event callback handle on Energy mode transition. + * + * @param event_handle Event handle which must be unregistered (must have been + * registered previously). + * + * @note An EFM_ASSERT is thrown if the handle is not found. + ******************************************************************************/ +void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle); + +/***************************************************************************//** + * Get configurable overhead value for early restore time in Sleeptimer ticks + * when a schedule wake-up is set. + * + * @return Current overhead value for early restore time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void); + +/***************************************************************************//** + * Set configurable overhead value for early restore time in Sleeptimer ticks + * used for schedule wake-up. + * Must be called after initialization else the value will be overwritten. + * + * @param overhead_tick Overhead value to set for early restore time. + * + * @note The overhead value can also be negative to remove time from the restore + * process. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick); + +/***************************************************************************//** + * Get configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @return Current minimum off-time value for schedule wake-up. + * + * @note Turning on external high frequency clock, such as HFXO, requires more + * energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency clock enable' is scheduled + * in 'x' time, there is a threshold 'x' value where turning off the clock + * is not worthwhile since the energy consumed by taking into account the + * wake-up will be greater than if we just keep the clock on until the next + * scheduled clock enabled. This threshold value is what we refer as the + * minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void); + +/***************************************************************************//** + * Set configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @param minimum_offtime_tick minimum off-time value to set for schedule + * wake-up. + * + * @note Turning on external high frequency clock, such as HFXO, requires more + * energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency clock enable' is scheduled + * in 'x' time, there is a threshold 'x' value where turning off the clock + * is not worthwhile since the energy consumed by taking into account the + * wake-up will be greater than if we just keep the clock on until the next + * scheduled clock enabled. This threshold value is what we refer as the + * minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick); + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @param enable True False variable act as a switch for this api + * + * @note Will also update the wake up time from EM2 to EM0. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); + +/**************************************************************************//** + * Determines if the HFXO interrupt was part of the last wake-up and/or if + * the HFXO early wakeup expired during the last ISR + * and if it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + * + * @note This function will always return false in case a requirement + * is added on SL_POWER_MANAGER_EM1, since we will + * never sleep at a lower level than EM1. + *****************************************************************************/ +bool sl_power_manager_is_latest_wakeup_internal(void); + +/** @} (end addtogroup power_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif // SL_POWER_MANAGER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager_debug.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager_debug.h index 6376ab7..4299cb4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager_debug.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sl_power_manager_debug.h @@ -1,60 +1,60 @@ -/***************************************************************************//** - * @file - * @brief Power Manager API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_POWER_MANAGER_DEBUG_H -#define SL_POWER_MANAGER_DEBUG_H - -#include "sl_power_manager.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup power_manager - * @{ - ******************************************************************************/ - -// ----------------------------------------------------------------------------- -// Prototypes - -/***************************************************************************//** - * Print a table that describes the current requirements on each energy - * mode and their owner. - ******************************************************************************/ -void sl_power_manager_debug_print_em_requirements(void); - -/** @} (end addtogroup power_manager) */ - -#ifdef __cplusplus -} -#endif - -#endif +/***************************************************************************//** + * @file + * @brief Power Manager API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_POWER_MANAGER_DEBUG_H +#define SL_POWER_MANAGER_DEBUG_H + +#include "sl_power_manager.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup power_manager + * @{ + ******************************************************************************/ + +// ----------------------------------------------------------------------------- +// Prototypes + +/***************************************************************************//** + * Print a table that describes the current requirements on each energy + * mode and their owner. + ******************************************************************************/ +void sl_power_manager_debug_print_em_requirements(void); + +/** @} (end addtogroup power_manager) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sli_power_manager.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sli_power_manager.h index ebd71d5..e5fd7eb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sli_power_manager.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/inc/sli_power_manager.h @@ -1,97 +1,97 @@ -/***************************************************************************//** - * @file - * @brief Power Manager Private API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_POWER_MANAGER_H -#define SLI_POWER_MANAGER_H - -#include "sl_power_manager.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add); - -/***************************************************************************//** - * Adds requirement on the preservation of the High Frequency Clocks settings. - * - * @note FOR INTERNAL USE ONLY. - * - * @note Must be used together with adding an EM2 requirement. - ******************************************************************************/ -void sli_power_manager_add_hf_clock_settings_preservation_requirement(void); - -/***************************************************************************//** - * Removes requirement on the preservation of the High Frequency Clocks settings. - * - * @note FOR INTERNAL USE ONLY. - * - * @note Must be used together with removing an EM2 requirement. - ******************************************************************************/ -void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void); - -/***************************************************************************//** - * Informs the power manager module that the high accuracy/high frequency clock - * is used. - * - * @note FOR INTERNAL USE ONLY. - * - * @note Must be called by RAIL initialization in case radio clock settings - * are not set before the Power Manager initialization. - ******************************************************************************/ -__WEAK void sli_power_manager_set_high_accuracy_hf_clock_as_used(void); - -/***************************************************************************//** - * Gets the wake-up restore process time. - * If we are not in the context of a deepsleep and therefore don't need to - * do a restore, the return value is 0. - * - * - * @return Wake-up restore process time. - ******************************************************************************/ -uint32_t sli_power_manager_get_restore_delay(void); - -/***************************************************************************//** - * Initiates the wake-up restore process. - ******************************************************************************/ -void sli_power_manager_initiate_restore(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SLI_POWER_MANAGER_H */ +/***************************************************************************//** + * @file + * @brief Power Manager Private API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_POWER_MANAGER_H +#define SLI_POWER_MANAGER_H + +#include "sl_power_manager.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add); + +/***************************************************************************//** + * Adds requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with adding an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_add_hf_clock_settings_preservation_requirement(void); + +/***************************************************************************//** + * Removes requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with removing an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void); + +/***************************************************************************//** + * Informs the power manager module that the high accuracy/high frequency clock + * is used. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be called by RAIL initialization in case radio clock settings + * are not set before the Power Manager initialization. + ******************************************************************************/ +__WEAK void sli_power_manager_set_high_accuracy_hf_clock_as_used(void); + +/***************************************************************************//** + * Gets the wake-up restore process time. + * If we are not in the context of a deepsleep and therefore don't need to + * do a restore, the return value is 0. + * + * + * @return Wake-up restore process time. + ******************************************************************************/ +uint32_t sli_power_manager_get_restore_delay(void); + +/***************************************************************************//** + * Initiates the wake-up restore process. + ******************************************************************************/ +void sli_power_manager_initiate_restore(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_POWER_MANAGER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager.c index 21c843b..d84577b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager.c @@ -1,1180 +1,1180 @@ -/***************************************************************************//** - * @file - * @brief Power Manager API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_power_manager.h" -#include "sl_power_manager_config.h" -#include "sli_power_manager_private.h" -#include "sli_power_manager.h" -#include "sli_sleeptimer.h" -#include "sl_assert.h" -#include "sl_atomic.h" - -#include "em_device.h" -#if !defined(_SILICON_LABS_32B_SERIES_3) -#include "em_emu.h" -#endif - -#include -#include -#include - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -// Default overhead value for the wake-up time used for the schedule wake-up -// functionality. -#define SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK 0 - -// Determine if the device supports EM1P -#if !defined(SLI_DEVICE_SUPPORTS_EM1P) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && _SILICON_LABS_32B_SERIES_2_CONFIG >= 2 -#define SLI_DEVICE_SUPPORTS_EM1P -#endif - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -// Initialization flag. -static bool is_initialized = false; - -// Current active energy mode. -static sl_power_manager_em_t current_em = SL_POWER_MANAGER_EM0; - -// Events subscribers lists -static sl_slist_node_t *power_manager_em_transition_event_list = NULL; - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -// Store the sleeptimer module clock frequency for conversion calculation -static uint32_t sleeptimer_frequency; - -// Table of energy modes counters. Each counter indicates the presence (not zero) -// or absence (zero) of requirements on a given energy mode. The table doesn't -// contain requirement on EM0. -static uint8_t requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE] = { - 0, // EM1 requirement counter - 0, // EM2 requirement counter -}; - -// Counter variable to save the number of High Accuracy HF clock requirements requested. -uint8_t requirement_high_accuracy_hf_clock_counter = 0; - -#ifdef SLI_DEVICE_SUPPORTS_EM1P -// Variable to indicate if the High Accuracy HF clock requirements count is back to zero. -bool requirement_high_accuracy_hf_clock_back_to_zero = false; -#endif - -// Saved energy mode we are coming from when waiting for HFXO ready. -static sl_power_manager_em_t waiting_clock_restore_from_em = SL_POWER_MANAGER_EM0; - -// Flag indicating if we are sleeping, waiting for the HF clock restore -static bool is_sleeping_waiting_for_clock_restore = false; - -// Flag indicating if the system states (clocks) are saved and should be restored -static bool is_states_saved = false; - -// Timer that it is used for enabling the clock for the scheduled wakeup -static sl_sleeptimer_timer_handle_t clock_wakeup_timer_handle = { 0 }; - -// Store if requirement on EM1 has been added before sleeping; -// i.e. only possible if sleeping for less than minimum off time -static bool requirement_on_em1_added = false; - -// Threshold delay in sleeptimer ticks indicating the minimum time required -// to make the shut down of external high frequency oscillator worthwhile before -// the next synchronous high frequency oscillator requirement. Shorter than this -// delay, the power gain of shutting down is invalidated. -uint32_t high_frequency_min_offtime_tick = 0; - -// Store the configuration overhead value in sleeptimer tick to add/remove to the wake-up time. -int32_t wakeup_time_config_overhead_tick = 0; - -static bool is_hf_x_oscillator_not_preserved; - -// Store if we are currently waiting for HF clock restoration to finish -static bool is_actively_waiting_for_clock_restore = false; - -// Indicates if the clock restore was completed from the HFXO ISR -static bool is_restored_from_hfxo_isr = false; -static bool is_restored_from_hfxo_isr_internal = false; -#endif - -/* - ********************************************************************************************************* - * HOOK REFERENCES - ********************************************************************************************************* - */ - -bool sl_power_manager_sleep_on_isr_exit(void); - -// Callback to application after wakeup but before restoring interrupts. -// For internal Silicon Labs use only -__WEAK void sli_power_manager_on_wakeup(void); - -// Hook that can be used by the log outputer to suspend transmission of logs -// in case it would require energy mode changes while in the sleep loop. -__WEAK void sli_power_manager_suspend_log_transmission(void); - -// Hook that can be used by the log outputer to resume transmission of logs. -__WEAK void sli_power_manager_resume_log_transmission(void); - -// Callback to notify possible transition from EM1P to EM2. -// For internal Silicon Labs use only -#ifdef SLI_DEVICE_SUPPORTS_EM1P -__WEAK void sli_power_manager_em1p_to_em2_notification(void); -#endif - -/***************************************************************************//** - * Mandatory callback that allows to cancel sleeping action. - ******************************************************************************/ -bool sl_power_manager_is_ok_to_sleep(void); - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -static sl_power_manager_em_t get_lowest_em(void); - -static void evaluate_wakeup(sl_power_manager_em_t to); - -static void update_em1_requirement(bool add); - -static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, - void *data); - -static void clock_restore_and_wait(void); - -static void clock_restore(void); -#endif - -static void power_manager_notify_em_transition(sl_power_manager_em_t from, - sl_power_manager_em_t to); - -// Use PriMask to enter critical section by disabling interrupts. -static CORE_irqState_t enter_critical_with_primask(); - -// Exit critical section by re-enabling interrupts in PriMask. -static void exit_critical_with_primask(CORE_irqState_t primask_state); - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * Initialize Power Manager module. - ******************************************************************************/ -sl_status_t sl_power_manager_init(void) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - if (!is_initialized) { - sl_status_t status = SL_STATUS_OK; - - // Initialize Sleeptimer module in case not already done. - status = sl_sleeptimer_init(); - if (status != SL_STATUS_OK) { - CORE_EXIT_CRITICAL(); - return status; - } -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - // Additional Sleeptimer HW configuration if the "power_manager_deepsleep" component is used - sli_sleeptimer_hal_power_manager_integration_init(); -#endif - - #if (SL_POWER_MANAGER_DEBUG == 1) - sli_power_manager_debug_init(); - #endif - sl_slist_init(&power_manager_em_transition_event_list); - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - // If lowest energy mode is not restricted to EM1, determine and set lowest energy mode - sli_sleeptimer_set_pm_em_requirement(); - // Set the default wake-up overhead value - wakeup_time_config_overhead_tick = SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK; - - // Get the sleeptimer frequency - sleeptimer_frequency = sl_sleeptimer_get_timer_frequency(); -#endif - } - - // Do all necessary hardware initialization. - sli_power_manager_init_hardware(); - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - // Set the HF minimum offtime in sleeptimer ticks - high_frequency_min_offtime_tick = sli_power_manager_get_default_high_frequency_minimum_offtime(); -#endif - - is_initialized = true; - CORE_EXIT_CRITICAL(); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Sleep at the lowest allowed energy mode. - ******************************************************************************/ -void sl_power_manager_sleep(void) -{ - CORE_irqState_t primask_state; - - primask_state = enter_critical_with_primask(); - - sli_power_manager_suspend_log_transmission(); - - if (sl_power_manager_is_ok_to_sleep() != true) { - sli_power_manager_resume_log_transmission(); - exit_critical_with_primask(primask_state); - return; - } - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - sl_power_manager_em_t lowest_em; - - // Go to another energy mode (same, higher to lower or lower to higher) - do { - // Remove any previous EM1 requirement added internally by the power manager itself - if (requirement_on_em1_added) { - update_em1_requirement(false); - requirement_on_em1_added = false; - } - - lowest_em = get_lowest_em(); - evaluate_wakeup(lowest_em); - lowest_em = get_lowest_em(); // Reevaluate as a requirement can be added from evaluate_wakeup() - - if ((lowest_em >= SL_POWER_MANAGER_EM2) - && (is_states_saved == false)) { - sli_power_manager_save_states(); - } - - // Notify listeners if transition to another energy mode - if (lowest_em != current_em) { -#ifdef SLI_DEVICE_SUPPORTS_EM1P - requirement_high_accuracy_hf_clock_back_to_zero = false; -#endif - if (is_sleeping_waiting_for_clock_restore == false) { - // But only notify if we are not in the process of waiting for the HF oscillators restore. - power_manager_notify_em_transition(current_em, lowest_em); - } - current_em = lowest_em; // Keep new active energy mode - } - -#ifdef SLI_DEVICE_SUPPORTS_EM1P - // Notification for possible transition from EM1P to EM2 - // For internal Silicon Labs use only - if (requirement_high_accuracy_hf_clock_back_to_zero - && current_em == SL_POWER_MANAGER_EM2) { - requirement_high_accuracy_hf_clock_back_to_zero = false; - sli_power_manager_em1p_to_em2_notification(); - } -#endif - - // Pre-sleep operations if any are necessary - if ((lowest_em >= SL_POWER_MANAGER_EM2) - && (is_states_saved == false)) { - // Only do pre-sleep operations if there is no requirement on High Accuracy Clock. - // Else we must not touch the clock tree. - if (requirement_high_accuracy_hf_clock_counter == 0) { - sli_power_manager_handle_pre_deepsleep_operations(); - is_hf_x_oscillator_not_preserved = true; - } - is_states_saved = true; - } - - // Apply lowest reachable energy mode - sli_power_manager_apply_em(current_em); - - // In case we are waiting for the restore from an early wake-up, - // we put back the current EM to the one before the early wake-up to do the next notification correctly. - if (is_sleeping_waiting_for_clock_restore == true) { - current_em = waiting_clock_restore_from_em; - } - - // Notify consumer of wakeup while interrupts are still off - // For internal Silicon Labs use only - sli_power_manager_on_wakeup(); - - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); - - // In case the HF restore was completed from the HFXO ISR, - // and notification not done elsewhere, do it here - if (is_restored_from_hfxo_isr_internal == true) { - is_restored_from_hfxo_isr_internal = false; - if (current_em == waiting_clock_restore_from_em) { - current_em = SL_POWER_MANAGER_EM1; - power_manager_notify_em_transition(waiting_clock_restore_from_em, SL_POWER_MANAGER_EM1); - } - } - - // Stop the internal power manager sleeptimer. - sl_sleeptimer_stop_timer(&clock_wakeup_timer_handle); - } while (sl_power_manager_sleep_on_isr_exit() == true); - -#ifdef SLI_DEVICE_SUPPORTS_EM1P - requirement_high_accuracy_hf_clock_back_to_zero = false; -#endif - - if (is_states_saved == true) { - is_sleeping_waiting_for_clock_restore = false; - // Restore clocks - if (is_hf_x_oscillator_not_preserved) { - sli_power_manager_restore_high_freq_accuracy_clk(); - is_hf_x_oscillator_not_preserved = false; - } - // If possible, go back to sleep in EM1 while waiting for HF accuracy restore - while (!sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { - sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); - } - sli_power_manager_restore_states(); - is_states_saved = false; - } - - evaluate_wakeup(SL_POWER_MANAGER_EM0); -#else - current_em = SL_POWER_MANAGER_EM1; - - // Notify listeners of transition to EM1 - power_manager_notify_em_transition(SL_POWER_MANAGER_EM0, SL_POWER_MANAGER_EM1); - do { - // Apply EM1 energy mode - sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); - - exit_critical_with_primask(primask_state); - primask_state = enter_critical_with_primask(); - } while (sl_power_manager_sleep_on_isr_exit() == true); -#endif - - // Indicate back to EM0 - power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM0); - current_em = SL_POWER_MANAGER_EM0; - - sli_power_manager_resume_log_transmission(); - - exit_critical_with_primask(primask_state); -} - -/***************************************************************************//** - * Updates requirement on the given energy mode. - * - * @param em Energy mode. Possible values are: - * SL_POWER_MANAGER_EM1 - * SL_POWER_MANAGER_EM2 - * - * @param add Flag indicating if requirement is added (true) or removed - * (false). - * - * @note Need to be call inside a critical section. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, - bool add) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - // EM0 is not allowed - EFM_ASSERT((em > SL_POWER_MANAGER_EM0) && (em < SL_POWER_MANAGER_EM3)); - - // Cannot increment above 255 (wraparound not allowed) - EFM_ASSERT(!((requirement_em_table[em - 1] == UINT8_MAX) && (add == true))); - // Cannot decrement below 0 (wraparound not allowed) - EFM_ASSERT(!((requirement_em_table[em - 1] == 0) && (add == false))); - - // Increment (add) or decrement (remove) energy mode counter. - requirement_em_table[em - 1] += (add) ? 1 : -1; - - if (add == true - && current_em >= SL_POWER_MANAGER_EM2) { // if currently sleeping at a level that can require a clock restore; i.e. called from ISR - sl_power_manager_em_t lowest_em; - // If requirement added when sleeping, restore the clock before continuing the processing. - // Retrieve lowest reachable energy mode - lowest_em = get_lowest_em(); - - if (lowest_em <= SL_POWER_MANAGER_EM1) { - // If new lowest requirement is greater than the current - // Restore clock; Everything is restored (HF and LF Clocks), the sleep loop will - // shutdown the clocks when returning sleeping - clock_restore_and_wait(); - } else if (current_em == SL_POWER_MANAGER_EM3 - && lowest_em == SL_POWER_MANAGER_EM2) { - // Restore LF clocks if we are transitioning from EM3 to EM2 - sli_power_manager_low_frequency_restore(); - } - - if (current_em != lowest_em) { - power_manager_notify_em_transition(current_em, lowest_em); - current_em = lowest_em; // Keep new active energy mode - } - } -#else - (void)em; - (void)add; -#endif -} - -/***************************************************************************//** - * Updates requirement on preservation of High Frequency Clocks settings. - * - * @param add Flag indicating if requirement is added (true) or removed - * (false). - ******************************************************************************/ -void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add) -{ -#if (defined(SLI_DEVICE_SUPPORTS_EM1P) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - // Cannot increment above 255 (wraparound not allowed) - EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true))); - // Cannot decrement below 0 (wraparound not allowed) - EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == 0) && (add == false))); - - // Cannot add requirement if the "normal" clock settings are not currently applied - EFM_ASSERT(!((current_em > SL_POWER_MANAGER_EM2) && (add == true))); - - // Increment (add) or decrement (remove) energy mode counter. - requirement_high_accuracy_hf_clock_counter += (add) ? 1 : -1; - - // Save if the requirement is back to zero. - requirement_high_accuracy_hf_clock_back_to_zero = (requirement_high_accuracy_hf_clock_counter == 0) ? true : false; - - CORE_EXIT_CRITICAL(); -#else - (void)add; -#endif -} - -/***************************************************************************//** - * Adds requirement on the preservation of the High Frequency Clocks settings. - * - * @note FOR INTERNAL USE ONLY. - * - * @note Must be used together with adding an EM2 requirement. - ******************************************************************************/ -void sli_power_manager_add_hf_clock_settings_preservation_requirement(void) -{ -#if defined(SLI_DEVICE_SUPPORTS_EM1P) - sli_power_manager_update_hf_clock_settings_preservation_requirement(true); -#else - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); -#endif -} - -/***************************************************************************//** - * Removes requirement on the preservation of the High Frequency Clocks settings. - * - * @note FOR INTERNAL USE ONLY. - * - * @note Must be used together with removing an EM2 requirement. - ******************************************************************************/ -void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void) -{ -#if defined(SLI_DEVICE_SUPPORTS_EM1P) - sli_power_manager_update_hf_clock_settings_preservation_requirement(false); -#else - sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); -#endif -} - -/***************************************************************************//** - * Gets the wake-up restore process time. - * If we are not in the context of a deepsleep and therefore don't need to - * do a restore, the return value is 0. - * - * @return Wake-up restore process time. - ******************************************************************************/ -uint32_t sli_power_manager_get_restore_delay(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - uint32_t wakeup_delay = 0; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - - // If we are not currently in deepsleep, not need for any clock restore - if (current_em <= SL_POWER_MANAGER_EM1) { - CORE_EXIT_CRITICAL(); - return wakeup_delay; - } - - // Get the clock restore delay - wakeup_delay = sl_power_manager_schedule_wakeup_get_restore_overhead_tick(); - wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); - - CORE_EXIT_CRITICAL(); - - return wakeup_delay; -#else - return 0; -#endif -} - -/***************************************************************************//** - * Initiates the wake-up restore process. - ******************************************************************************/ -void sli_power_manager_initiate_restore(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - - // Start restore process - clock_restore(); - - CORE_EXIT_CRITICAL(); -#endif -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/******************************************************************************* - * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. - ******************************************************************************/ -bool sli_power_manager_get_clock_restore_status(void) -{ - return is_sleeping_waiting_for_clock_restore; -} -#endif - -/***************************************************************************//** - * Registers a callback to be called on given Energy Mode transition(s). - * - * @note Adding/Removing requirement(s) from the callback is not supported. - ******************************************************************************/ -void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, - const sl_power_manager_em_transition_event_info_t *event_info) -{ - CORE_DECLARE_IRQ_STATE; - - event_handle->info = (sl_power_manager_em_transition_event_info_t *)event_info; - CORE_ENTER_CRITICAL(); - sl_slist_push(&power_manager_em_transition_event_list, &event_handle->node); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * Unregisters an event callback handle on Energy mode transition. - ******************************************************************************/ -void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - sl_slist_remove(&power_manager_em_transition_event_list, &event_handle->node); - CORE_EXIT_CRITICAL(); -} - -/***************************************************************************//** - * Get configurable overhead value for early restore time in Sleeptimer ticks - * when a schedule wake-up is set. - * - * @return Current overhead value for early wake-up time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - int32_t overhead_tick; - - sl_atomic_load(overhead_tick, wakeup_time_config_overhead_tick); - return overhead_tick; -#else - return 0; -#endif -} - -/***************************************************************************//** - * Set configurable overhead value for early restore time in Sleeptimer ticks - * used for schedule wake-up. - * Must be called after initialization else the value will be overwritten. - * - * @param overhead_tick Overhead value to set for early restore time. - * - * @note The overhead value can also be negative to remove time from the restore - * process. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - sl_atomic_store(wakeup_time_config_overhead_tick, overhead_tick); -#else - (void)overhead_tick; -#endif -} - -/***************************************************************************//** - * Get configurable minimum off-time value for schedule wake-up in Sleeptimer - * ticks. - * - * @return Current minimum off-time value for schedule wake-up. - * - * @note Turning on external high frequency oscillator, such as HFXO, requires - * more energy since we must supply higher current for the wake-up. - * Therefore, when an 'external high frequency oscillator enable' is - * scheduled in 'x' time, there is a threshold 'x' value where turning - * off the oscillator is not worthwhile since the energy consumed by - * taking into account the wake-up will be greater than if we just keep - * the oscillator on until the next scheduled oscillator enabled. This - * threshold value is what we refer as the minimum off-time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - uint32_t offtime_tick; - - sl_atomic_load(offtime_tick, high_frequency_min_offtime_tick); - return offtime_tick; -#else - return 0; -#endif -} - -/***************************************************************************//** - * Set configurable minimum off-time value for schedule wake-up in Sleeptimer - * ticks. - * - * @param minimum_offtime_tick minimum off-time value to set for schedule - * wake-up. - * - * @note Turning on external high frequency oscillator, such as HFXO, requires - * more energy since we must supply higher current for the wake-up. - * Therefore, when an 'external high frequency oscillator enable' is - * scheduled in 'x' time, there is a threshold 'x' value where turning - * off the oscillator is not worthwhile since the energy consumed by - * taking into account the wake-up will be greater than if we just keep - * the oscillator on until the next scheduled oscillator enabled. This - * threshold value is what we refer as the minimum off-time. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - sl_atomic_store(high_frequency_min_offtime_tick, minimum_offtime_tick); -#else - (void)minimum_offtime_tick; -#endif -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/******************************************************************************* - * Converts microseconds time in sleeptimer ticks. - ******************************************************************************/ -uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us) -{ - return (((time_us * sleeptimer_frequency) + (1000000 - 1)) / 1000000); -} -#endif - -/***************************************************************************//** - * Last-chance check before sleep. - * - * @return True, if the system should actually sleep. - * False, if not. - * - * @note This is the fallback implementation of the callback, it can be - * overridden by the application or other components. - ******************************************************************************/ -__WEAK bool sl_power_manager_is_ok_to_sleep(void) -{ - return true; -} - -/***************************************************************************//** - * Check if the MCU can sleep after an interrupt. - * - * @return True, if the system can sleep after the interrupt. - * False, otherwise. - * - * @note This is the fallback implementation of the callback, it can be - * overridden by the application or other components. - ******************************************************************************/ -__WEAK bool sl_power_manager_sleep_on_isr_exit(void) -{ - return false; -} - -/**************************************************************************//** - * Determines if the HFXO interrupt was part of the last wake-up and/or if - * the HFXO early wakeup expired during the last ISR - * and if it was the only timer to expire in that period. - * - * @return true if power manager sleep can return to sleep, - * false otherwise. - * - * @note This function will always return false in case - * a requirement is added on SL_POWER_MANAGER_EM1, - * since we will never sleep at a lower level than EM1. - *****************************************************************************/ -bool sl_power_manager_is_latest_wakeup_internal(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - CORE_DECLARE_IRQ_STATE; - bool sleep; - - CORE_ENTER_CRITICAL(); - sleep = is_restored_from_hfxo_isr; - is_restored_from_hfxo_isr = false; - CORE_EXIT_CRITICAL(); - - sleep |= sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(); - return sleep; -#else - return false; -#endif -} - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Get lowest energy mode to apply given the requirements on the different - * energy modes. - * - * @return Lowest energy mode: EM1, EM2 or EM3. - * - * @note If no requirement for any energy mode (EM1 and EM2), lowest energy mode - * is EM3. - ******************************************************************************/ -static sl_power_manager_em_t get_lowest_em(void) -{ - uint32_t em_ix; - sl_power_manager_em_t em; - - // Retrieve lowest Energy mode allowed given the requirements - for (em_ix = 1; (em_ix < 3) && (requirement_em_table[em_ix - 1] == 0); em_ix++) { - ; - } - - em = (sl_power_manager_em_t)em_ix; - - return em; -} -#endif - -/***************************************************************************//** - * Notify subscribers about energy mode transition. - * - * @param from Energy mode from which CPU comes from. - * - * @param to Energy mode to which CPU is going to. - ******************************************************************************/ -static void power_manager_notify_em_transition(sl_power_manager_em_t from, - sl_power_manager_em_t to) -{ - sl_power_manager_em_transition_event_handle_t *handle; - sl_power_manager_em_transition_event_t transition = 0; - - switch (to) { - case SL_POWER_MANAGER_EM0: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0; - break; - - case SL_POWER_MANAGER_EM1: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1; - break; - - case SL_POWER_MANAGER_EM2: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2; - break; - - case SL_POWER_MANAGER_EM3: - transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3; - break; - - default: - EFM_ASSERT(0); - } - - switch (from) { - case SL_POWER_MANAGER_EM0: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0; - break; - - case SL_POWER_MANAGER_EM1: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1; - break; - - case SL_POWER_MANAGER_EM2: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2; - break; - - case SL_POWER_MANAGER_EM3: - transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3; - break; - - default: - EFM_ASSERT(0); - } - - SL_SLIST_FOR_EACH_ENTRY(power_manager_em_transition_event_list, handle, sl_power_manager_em_transition_event_handle_t, node) { - if ((handle->info->event_mask & transition) > 0) { - handle->info->on_event(from, to); - } - } -} - -/***************************************************************************//** - * Enter critical section by disabling interrupts using PriMask. - * - * @return primask Initial primask state. - * - * @note @ref sl_power_manager_sleep() function should use PriMask to disable - * interrupts. - ******************************************************************************/ -static CORE_irqState_t enter_critical_with_primask(void) -{ - CORE_irqState_t irqState = __get_PRIMASK(); - __disable_irq(); - - return irqState; -} - -/***************************************************************************//** - * Exit critical section by re-enabling interrupts using PriMask. - * - * @param primask_state Initial primask state. - ******************************************************************************/ -static void exit_critical_with_primask(CORE_irqState_t primask_state) -{ - if (primask_state == 0U) { - __enable_irq(); - } -} -/***************************************************************************//** - * Evaluates scheduled wakeup and restart timer based on the wakeup time. - * If the remaining time is shorter than the wakeup time then add a requirement - * on EM1 for avoiding the wakeup delay time. - * - * @note Must be called in a critical section. - ******************************************************************************/ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -static void evaluate_wakeup(sl_power_manager_em_t to) -{ - sl_status_t status; - uint32_t tick_remaining; - - switch (to) { - case SL_POWER_MANAGER_EM0: - // Coming back from Sleep. - if (requirement_on_em1_added) { - update_em1_requirement(false); - requirement_on_em1_added = false; - } - break; - - case SL_POWER_MANAGER_EM1: - // External high frequency clock, such as HFXO, already enabled; No wakeup delay - break; - - case SL_POWER_MANAGER_EM2: - case SL_POWER_MANAGER_EM3: - // Get the time remaining until the next sleeptimer requiring early wake-up - status = sl_sleeptimer_get_remaining_time_of_first_timer(0, &tick_remaining); - if (status == SL_STATUS_OK) { - if (tick_remaining <= high_frequency_min_offtime_tick) { - // Add EM1 requirement if time remaining is to short to be energy efficient - // if going back to deepsleep. - update_em1_requirement(true); - requirement_on_em1_added = true; - } else { - int32_t wakeup_delay = 0; - int32_t cfg_overhead_tick = 0; - - // Calculate overall wake-up delay. - sl_atomic_load(cfg_overhead_tick, wakeup_time_config_overhead_tick); - wakeup_delay += cfg_overhead_tick; - wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); - EFM_ASSERT(wakeup_delay >= 0); - if (tick_remaining <= (uint32_t)wakeup_delay) { - // Add EM1 requirement if time remaining is smaller than wake-up delay. - update_em1_requirement(true); - requirement_on_em1_added = true; - } else { - uint16_t hf_accuracy_clk_flag = 0; - if (sli_power_manager_is_high_freq_accuracy_clk_used()) { - hf_accuracy_clk_flag = SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG; - } - // Start internal sleeptimer to do the early wake-up. - sl_sleeptimer_restart_timer(&clock_wakeup_timer_handle, - (tick_remaining - (uint32_t)wakeup_delay), - on_clock_wakeup_timeout, - NULL, - 0, - (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | hf_accuracy_clk_flag)); - } - } - } - break; - - default: - EFM_ASSERT(false); - } -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Updates internal EM1 requirement. - * We add an internal EM1 requirement when we would usually go into EM2/EM3 - * but there is not enough time before the next schedule event requiring a - * clock restore. So we just go to sleep in EM1. - * We remove this internal EM1 requirement next time we wake-up. - * - * @param add true, to add EM1 requirement, - * false, to remove EM1 requirement. - * - * @note For internal use only. - * - * @note Need to be call inside a critical section. - ******************************************************************************/ -static void update_em1_requirement(bool add) -{ - // Cannot increment above 255 (wraparound not allowed) - EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true))); - // Cannot decrement below 0 (wraparound not allowed) - EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false))); - -#if (SL_POWER_MANAGER_DEBUG == 1) - sli_power_manager_debug_log_em_requirement(SL_POWER_MANAGER_EM1, add, "PM_INTERNAL_EM1_REQUIREMENT"); -#endif - - // Increment (add) or decrement (remove) energy mode counter. - requirement_em_table[SL_POWER_MANAGER_EM1 - 1] += (add) ? 1 : -1; - - // In rare occasions a clock restore must be started here: - // - An asynchronous event wake-up the system from deepsleep very near the early wake-up event, - // When we re-enter the sleep loop, we delete the internal early wake-up timer, but during - // the evaluation before sleep, it is calculated that not enough time is remains to go to - // deepsleep. In that case, since we deleted the early wake-up timer we must start the - // restore process here. - // - A synchronous event is added during an ISR, when we evaluate if the timeout is bigger - // than the clock restore time, it's barely bigger, so no clock restore process is started - // at that time. But when we do the evaluate before sleep, the remaining time is now smaller - // than the clock restore delay. So me must start the restore process here. - if (add == true - && current_em >= SL_POWER_MANAGER_EM2 - && is_sleeping_waiting_for_clock_restore == false) { - clock_restore(); - } -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Do clock restore process and wait for it to be completed. - ******************************************************************************/ -static void clock_restore_and_wait(void) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - if (is_states_saved == true) { - if (is_actively_waiting_for_clock_restore == false) { - is_actively_waiting_for_clock_restore = true; - - // Since we will actively wait for clock restore, we cancel any current non-active wait. - is_sleeping_waiting_for_clock_restore = false; - } - - if (is_hf_x_oscillator_not_preserved) { - sli_power_manager_restore_high_freq_accuracy_clk(); - is_hf_x_oscillator_not_preserved = false; - } - - CORE_EXIT_CRITICAL(); - // We remove the critical section in case HFXO fails to startup and the HFXO Interrupt needs to run to handle the error. - sli_power_manager_is_high_freq_accuracy_clk_ready(true); - CORE_ENTER_CRITICAL(); - if (is_actively_waiting_for_clock_restore) { - sli_power_manager_restore_states(); - is_actively_waiting_for_clock_restore = false; - } - - is_states_saved = false; - } - CORE_EXIT_CRITICAL(); -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Start clock restore process. - * - * @note Need to be call inside a critical section. - ******************************************************************************/ -static void clock_restore(void) -{ - // Check if we need to start the clock restore process - if (is_states_saved == true) { - if (is_hf_x_oscillator_not_preserved) { - sli_power_manager_restore_high_freq_accuracy_clk(); - is_hf_x_oscillator_not_preserved = false; - } - if (sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { - // Do the clock restore if the HF oscillator is already ready - sli_power_manager_restore_states(); - is_states_saved = false; - - // We do the notification only when the restore is completed. - power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM1); - current_em = SL_POWER_MANAGER_EM1; // Keep new active energy mode - } else { - // If the HF oscillator is not yet ready, we will go back to sleep while waiting - is_sleeping_waiting_for_clock_restore = true; - - // Save current EM to do the right notification later - waiting_clock_restore_from_em = current_em; - } - } -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Callback for clock enable timer. - * - * @param handle Pointer to sleeptimer handle - * - * @param data Pointer to callback data - * - * @note We restore the HF clocks and go to EM1 here to be ready in time for the - * Application sleeptimer callback. But no EM1 requirement is added - * here. Since the time until the Application sleeptimer times out is <= - * than the wake-up delay, it protects us from going back to sleep lower - * than EM1. After that, it's up to the Application sleeptimer callback to - * put a EM1 requirement if still needed. - ******************************************************************************/ -static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - (void)handle; - (void)data; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - - if (is_actively_waiting_for_clock_restore) { - // In case we are already actively waiting for HFXO ready in another ISR, just exit - CORE_EXIT_CRITICAL(); - return; - } - - // If needed start the clock restore process - clock_restore(); - - CORE_EXIT_CRITICAL(); -} -#endif - -/***************************************************************************//** - * HFXO ready notification callback for internal use with power manager - * - * @note Will only be used on series 2 devices when HFXO Manager is present. - ******************************************************************************/ -void sli_hfxo_manager_notify_ready_for_power_manager(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - // Complete HF restore and change current Energy mode - // The notification will be done once back in the sleep loop - if (current_em != SL_POWER_MANAGER_EM0 - && (is_sleeping_waiting_for_clock_restore == true)) { - sli_power_manager_restore_states(); - is_sleeping_waiting_for_clock_restore = false; - is_states_saved = false; - is_restored_from_hfxo_isr = true; - is_restored_from_hfxo_isr_internal = true; - } -#endif -} - -/***************************************************************************//** - * HFXO PRS ready notification callback for internal use with power manager - * - * @note Will only be used on series 2 devices when HFXO Manager and SYSRTC - * is present. - ******************************************************************************/ -void sli_hfxo_notify_ready_for_power_manager_from_prs(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - // Set clock restore to true to indicate that HFXO has been restored from a - // PRS interrupt unless already in EM0 indicating HFXO didn't need to be restored. - if (current_em != SL_POWER_MANAGER_EM0) { - is_sleeping_waiting_for_clock_restore = true; - } -#endif -} - -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3 - * - * @note Will also update the wake up time from EM2 to EM0. - * - * @note This function will do nothing when a project contains the - * power_manager_no_deepsleep component, which configures the - * lowest energy mode as EM1. - ******************************************************************************/ -void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) -{ -#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_CRITICAL(); - - sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(enable); - - CORE_EXIT_CRITICAL(); -#else - (void)enable; -#endif -} +/***************************************************************************//** + * @file + * @brief Power Manager API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sli_power_manager_private.h" +#include "sli_power_manager.h" +#include "sli_sleeptimer.h" +#include "sl_assert.h" +#include "sl_atomic.h" + +#include "em_device.h" +#if !defined(_SILICON_LABS_32B_SERIES_3) +#include "em_emu.h" +#endif + +#include +#include +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Default overhead value for the wake-up time used for the schedule wake-up +// functionality. +#define SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK 0 + +// Determine if the device supports EM1P +#if !defined(SLI_DEVICE_SUPPORTS_EM1P) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) && _SILICON_LABS_32B_SERIES_2_CONFIG >= 2 +#define SLI_DEVICE_SUPPORTS_EM1P +#endif + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +// Initialization flag. +static bool is_initialized = false; + +// Current active energy mode. +static sl_power_manager_em_t current_em = SL_POWER_MANAGER_EM0; + +// Events subscribers lists +static sl_slist_node_t *power_manager_em_transition_event_list = NULL; + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +// Store the sleeptimer module clock frequency for conversion calculation +static uint32_t sleeptimer_frequency; + +// Table of energy modes counters. Each counter indicates the presence (not zero) +// or absence (zero) of requirements on a given energy mode. The table doesn't +// contain requirement on EM0. +static uint8_t requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE] = { + 0, // EM1 requirement counter + 0, // EM2 requirement counter +}; + +// Counter variable to save the number of High Accuracy HF clock requirements requested. +uint8_t requirement_high_accuracy_hf_clock_counter = 0; + +#ifdef SLI_DEVICE_SUPPORTS_EM1P +// Variable to indicate if the High Accuracy HF clock requirements count is back to zero. +bool requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + +// Saved energy mode we are coming from when waiting for HFXO ready. +static sl_power_manager_em_t waiting_clock_restore_from_em = SL_POWER_MANAGER_EM0; + +// Flag indicating if we are sleeping, waiting for the HF clock restore +static bool is_sleeping_waiting_for_clock_restore = false; + +// Flag indicating if the system states (clocks) are saved and should be restored +static bool is_states_saved = false; + +// Timer that it is used for enabling the clock for the scheduled wakeup +static sl_sleeptimer_timer_handle_t clock_wakeup_timer_handle = { 0 }; + +// Store if requirement on EM1 has been added before sleeping; +// i.e. only possible if sleeping for less than minimum off time +static bool requirement_on_em1_added = false; + +// Threshold delay in sleeptimer ticks indicating the minimum time required +// to make the shut down of external high frequency oscillator worthwhile before +// the next synchronous high frequency oscillator requirement. Shorter than this +// delay, the power gain of shutting down is invalidated. +uint32_t high_frequency_min_offtime_tick = 0; + +// Store the configuration overhead value in sleeptimer tick to add/remove to the wake-up time. +int32_t wakeup_time_config_overhead_tick = 0; + +static bool is_hf_x_oscillator_not_preserved; + +// Store if we are currently waiting for HF clock restoration to finish +static bool is_actively_waiting_for_clock_restore = false; + +// Indicates if the clock restore was completed from the HFXO ISR +static bool is_restored_from_hfxo_isr = false; +static bool is_restored_from_hfxo_isr_internal = false; +#endif + +/* + ********************************************************************************************************* + * HOOK REFERENCES + ********************************************************************************************************* + */ + +bool sl_power_manager_sleep_on_isr_exit(void); + +// Callback to application after wakeup but before restoring interrupts. +// For internal Silicon Labs use only +__WEAK void sli_power_manager_on_wakeup(void); + +// Hook that can be used by the log outputer to suspend transmission of logs +// in case it would require energy mode changes while in the sleep loop. +__WEAK void sli_power_manager_suspend_log_transmission(void); + +// Hook that can be used by the log outputer to resume transmission of logs. +__WEAK void sli_power_manager_resume_log_transmission(void); + +// Callback to notify possible transition from EM1P to EM2. +// For internal Silicon Labs use only +#ifdef SLI_DEVICE_SUPPORTS_EM1P +__WEAK void sli_power_manager_em1p_to_em2_notification(void); +#endif + +/***************************************************************************//** + * Mandatory callback that allows to cancel sleeping action. + ******************************************************************************/ +bool sl_power_manager_is_ok_to_sleep(void); + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +static sl_power_manager_em_t get_lowest_em(void); + +static void evaluate_wakeup(sl_power_manager_em_t to); + +static void update_em1_requirement(bool add); + +static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, + void *data); + +static void clock_restore_and_wait(void); + +static void clock_restore(void); +#endif + +static void power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to); + +// Use PriMask to enter critical section by disabling interrupts. +static CORE_irqState_t enter_critical_with_primask(); + +// Exit critical section by re-enabling interrupts in PriMask. +static void exit_critical_with_primask(CORE_irqState_t primask_state); + +/******************************************************************************* + ************************** GLOBAL FUNCTIONS ******************************* + ******************************************************************************/ + +/***************************************************************************//** + * Initialize Power Manager module. + ******************************************************************************/ +sl_status_t sl_power_manager_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + if (!is_initialized) { + sl_status_t status = SL_STATUS_OK; + + // Initialize Sleeptimer module in case not already done. + status = sl_sleeptimer_init(); + if (status != SL_STATUS_OK) { + CORE_EXIT_CRITICAL(); + return status; + } +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Additional Sleeptimer HW configuration if the "power_manager_deepsleep" component is used + sli_sleeptimer_hal_power_manager_integration_init(); +#endif + + #if (SL_POWER_MANAGER_DEBUG == 1) + sli_power_manager_debug_init(); + #endif + sl_slist_init(&power_manager_em_transition_event_list); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // If lowest energy mode is not restricted to EM1, determine and set lowest energy mode + sli_sleeptimer_set_pm_em_requirement(); + // Set the default wake-up overhead value + wakeup_time_config_overhead_tick = SCHEDULE_WAKEUP_DEFAULT_RESTORE_TIME_OVERHEAD_TICK; + + // Get the sleeptimer frequency + sleeptimer_frequency = sl_sleeptimer_get_timer_frequency(); +#endif + } + + // Do all necessary hardware initialization. + sli_power_manager_init_hardware(); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Set the HF minimum offtime in sleeptimer ticks + high_frequency_min_offtime_tick = sli_power_manager_get_default_high_frequency_minimum_offtime(); +#endif + + is_initialized = true; + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Sleep at the lowest allowed energy mode. + ******************************************************************************/ +void sl_power_manager_sleep(void) +{ + CORE_irqState_t primask_state; + + primask_state = enter_critical_with_primask(); + + sli_power_manager_suspend_log_transmission(); + + if (sl_power_manager_is_ok_to_sleep() != true) { + sli_power_manager_resume_log_transmission(); + exit_critical_with_primask(primask_state); + return; + } + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + sl_power_manager_em_t lowest_em; + + // Go to another energy mode (same, higher to lower or lower to higher) + do { + // Remove any previous EM1 requirement added internally by the power manager itself + if (requirement_on_em1_added) { + update_em1_requirement(false); + requirement_on_em1_added = false; + } + + lowest_em = get_lowest_em(); + evaluate_wakeup(lowest_em); + lowest_em = get_lowest_em(); // Reevaluate as a requirement can be added from evaluate_wakeup() + + if ((lowest_em >= SL_POWER_MANAGER_EM2) + && (is_states_saved == false)) { + sli_power_manager_save_states(); + } + + // Notify listeners if transition to another energy mode + if (lowest_em != current_em) { +#ifdef SLI_DEVICE_SUPPORTS_EM1P + requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + if (is_sleeping_waiting_for_clock_restore == false) { + // But only notify if we are not in the process of waiting for the HF oscillators restore. + power_manager_notify_em_transition(current_em, lowest_em); + } + current_em = lowest_em; // Keep new active energy mode + } + +#ifdef SLI_DEVICE_SUPPORTS_EM1P + // Notification for possible transition from EM1P to EM2 + // For internal Silicon Labs use only + if (requirement_high_accuracy_hf_clock_back_to_zero + && current_em == SL_POWER_MANAGER_EM2) { + requirement_high_accuracy_hf_clock_back_to_zero = false; + sli_power_manager_em1p_to_em2_notification(); + } +#endif + + // Pre-sleep operations if any are necessary + if ((lowest_em >= SL_POWER_MANAGER_EM2) + && (is_states_saved == false)) { + // Only do pre-sleep operations if there is no requirement on High Accuracy Clock. + // Else we must not touch the clock tree. + if (requirement_high_accuracy_hf_clock_counter == 0) { + sli_power_manager_handle_pre_deepsleep_operations(); + is_hf_x_oscillator_not_preserved = true; + } + is_states_saved = true; + } + + // Apply lowest reachable energy mode + sli_power_manager_apply_em(current_em); + + // In case we are waiting for the restore from an early wake-up, + // we put back the current EM to the one before the early wake-up to do the next notification correctly. + if (is_sleeping_waiting_for_clock_restore == true) { + current_em = waiting_clock_restore_from_em; + } + + // Notify consumer of wakeup while interrupts are still off + // For internal Silicon Labs use only + sli_power_manager_on_wakeup(); + + exit_critical_with_primask(primask_state); + primask_state = enter_critical_with_primask(); + + // In case the HF restore was completed from the HFXO ISR, + // and notification not done elsewhere, do it here + if (is_restored_from_hfxo_isr_internal == true) { + is_restored_from_hfxo_isr_internal = false; + if (current_em == waiting_clock_restore_from_em) { + current_em = SL_POWER_MANAGER_EM1; + power_manager_notify_em_transition(waiting_clock_restore_from_em, SL_POWER_MANAGER_EM1); + } + } + + // Stop the internal power manager sleeptimer. + sl_sleeptimer_stop_timer(&clock_wakeup_timer_handle); + } while (sl_power_manager_sleep_on_isr_exit() == true); + +#ifdef SLI_DEVICE_SUPPORTS_EM1P + requirement_high_accuracy_hf_clock_back_to_zero = false; +#endif + + if (is_states_saved == true) { + is_sleeping_waiting_for_clock_restore = false; + // Restore clocks + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + // If possible, go back to sleep in EM1 while waiting for HF accuracy restore + while (!sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { + sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); + exit_critical_with_primask(primask_state); + primask_state = enter_critical_with_primask(); + } + sli_power_manager_restore_states(); + is_states_saved = false; + } + + evaluate_wakeup(SL_POWER_MANAGER_EM0); +#else + current_em = SL_POWER_MANAGER_EM1; + + // Notify listeners of transition to EM1 + power_manager_notify_em_transition(SL_POWER_MANAGER_EM0, SL_POWER_MANAGER_EM1); + do { + // Apply EM1 energy mode + sli_power_manager_apply_em(SL_POWER_MANAGER_EM1); + + exit_critical_with_primask(primask_state); + primask_state = enter_critical_with_primask(); + } while (sl_power_manager_sleep_on_isr_exit() == true); +#endif + + // Indicate back to EM0 + power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM0); + current_em = SL_POWER_MANAGER_EM0; + + sli_power_manager_resume_log_transmission(); + + exit_critical_with_primask(primask_state); +} + +/***************************************************************************//** + * Updates requirement on the given energy mode. + * + * @param em Energy mode. Possible values are: + * SL_POWER_MANAGER_EM1 + * SL_POWER_MANAGER_EM2 + * + * @param add Flag indicating if requirement is added (true) or removed + * (false). + * + * @note Need to be call inside a critical section. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sli_power_manager_update_em_requirement(sl_power_manager_em_t em, + bool add) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // EM0 is not allowed + EFM_ASSERT((em > SL_POWER_MANAGER_EM0) && (em < SL_POWER_MANAGER_EM3)); + + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[em - 1] == UINT8_MAX) && (add == true))); + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[em - 1] == 0) && (add == false))); + + // Increment (add) or decrement (remove) energy mode counter. + requirement_em_table[em - 1] += (add) ? 1 : -1; + + if (add == true + && current_em >= SL_POWER_MANAGER_EM2) { // if currently sleeping at a level that can require a clock restore; i.e. called from ISR + sl_power_manager_em_t lowest_em; + // If requirement added when sleeping, restore the clock before continuing the processing. + // Retrieve lowest reachable energy mode + lowest_em = get_lowest_em(); + + if (lowest_em <= SL_POWER_MANAGER_EM1) { + // If new lowest requirement is greater than the current + // Restore clock; Everything is restored (HF and LF Clocks), the sleep loop will + // shutdown the clocks when returning sleeping + clock_restore_and_wait(); + } else if (current_em == SL_POWER_MANAGER_EM3 + && lowest_em == SL_POWER_MANAGER_EM2) { + // Restore LF clocks if we are transitioning from EM3 to EM2 + sli_power_manager_low_frequency_restore(); + } + + if (current_em != lowest_em) { + power_manager_notify_em_transition(current_em, lowest_em); + current_em = lowest_em; // Keep new active energy mode + } + } +#else + (void)em; + (void)add; +#endif +} + +/***************************************************************************//** + * Updates requirement on preservation of High Frequency Clocks settings. + * + * @param add Flag indicating if requirement is added (true) or removed + * (false). + ******************************************************************************/ +void sli_power_manager_update_hf_clock_settings_preservation_requirement(bool add) +{ +#if (defined(SLI_DEVICE_SUPPORTS_EM1P) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == UINT8_MAX) && (add == true))); + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_high_accuracy_hf_clock_counter == 0) && (add == false))); + + // Cannot add requirement if the "normal" clock settings are not currently applied + EFM_ASSERT(!((current_em > SL_POWER_MANAGER_EM2) && (add == true))); + + // Increment (add) or decrement (remove) energy mode counter. + requirement_high_accuracy_hf_clock_counter += (add) ? 1 : -1; + + // Save if the requirement is back to zero. + requirement_high_accuracy_hf_clock_back_to_zero = (requirement_high_accuracy_hf_clock_counter == 0) ? true : false; + + CORE_EXIT_CRITICAL(); +#else + (void)add; +#endif +} + +/***************************************************************************//** + * Adds requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with adding an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_add_hf_clock_settings_preservation_requirement(void) +{ +#if defined(SLI_DEVICE_SUPPORTS_EM1P) + sli_power_manager_update_hf_clock_settings_preservation_requirement(true); +#else + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +#endif +} + +/***************************************************************************//** + * Removes requirement on the preservation of the High Frequency Clocks settings. + * + * @note FOR INTERNAL USE ONLY. + * + * @note Must be used together with removing an EM2 requirement. + ******************************************************************************/ +void sli_power_manager_remove_hf_clock_settings_preservation_requirement(void) +{ +#if defined(SLI_DEVICE_SUPPORTS_EM1P) + sli_power_manager_update_hf_clock_settings_preservation_requirement(false); +#else + sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1); +#endif +} + +/***************************************************************************//** + * Gets the wake-up restore process time. + * If we are not in the context of a deepsleep and therefore don't need to + * do a restore, the return value is 0. + * + * @return Wake-up restore process time. + ******************************************************************************/ +uint32_t sli_power_manager_get_restore_delay(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t wakeup_delay = 0; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + // If we are not currently in deepsleep, not need for any clock restore + if (current_em <= SL_POWER_MANAGER_EM1) { + CORE_EXIT_CRITICAL(); + return wakeup_delay; + } + + // Get the clock restore delay + wakeup_delay = sl_power_manager_schedule_wakeup_get_restore_overhead_tick(); + wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); + + CORE_EXIT_CRITICAL(); + + return wakeup_delay; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Initiates the wake-up restore process. + ******************************************************************************/ +void sli_power_manager_initiate_restore(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + // Start restore process + clock_restore(); + + CORE_EXIT_CRITICAL(); +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. + ******************************************************************************/ +bool sli_power_manager_get_clock_restore_status(void) +{ + return is_sleeping_waiting_for_clock_restore; +} +#endif + +/***************************************************************************//** + * Registers a callback to be called on given Energy Mode transition(s). + * + * @note Adding/Removing requirement(s) from the callback is not supported. + ******************************************************************************/ +void sl_power_manager_subscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle, + const sl_power_manager_em_transition_event_info_t *event_info) +{ + CORE_DECLARE_IRQ_STATE; + + event_handle->info = (sl_power_manager_em_transition_event_info_t *)event_info; + CORE_ENTER_CRITICAL(); + sl_slist_push(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Unregisters an event callback handle on Energy mode transition. + ******************************************************************************/ +void sl_power_manager_unsubscribe_em_transition_event(sl_power_manager_em_transition_event_handle_t *event_handle) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + sl_slist_remove(&power_manager_em_transition_event_list, &event_handle->node); + CORE_EXIT_CRITICAL(); +} + +/***************************************************************************//** + * Get configurable overhead value for early restore time in Sleeptimer ticks + * when a schedule wake-up is set. + * + * @return Current overhead value for early wake-up time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +int32_t sl_power_manager_schedule_wakeup_get_restore_overhead_tick(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + int32_t overhead_tick; + + sl_atomic_load(overhead_tick, wakeup_time_config_overhead_tick); + return overhead_tick; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Set configurable overhead value for early restore time in Sleeptimer ticks + * used for schedule wake-up. + * Must be called after initialization else the value will be overwritten. + * + * @param overhead_tick Overhead value to set for early restore time. + * + * @note The overhead value can also be negative to remove time from the restore + * process. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_restore_overhead_tick(int32_t overhead_tick) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + sl_atomic_store(wakeup_time_config_overhead_tick, overhead_tick); +#else + (void)overhead_tick; +#endif +} + +/***************************************************************************//** + * Get configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @return Current minimum off-time value for schedule wake-up. + * + * @note Turning on external high frequency oscillator, such as HFXO, requires + * more energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency oscillator enable' is + * scheduled in 'x' time, there is a threshold 'x' value where turning + * off the oscillator is not worthwhile since the energy consumed by + * taking into account the wake-up will be greater than if we just keep + * the oscillator on until the next scheduled oscillator enabled. This + * threshold value is what we refer as the minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +uint32_t sl_power_manager_schedule_wakeup_get_minimum_offtime_tick(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t offtime_tick; + + sl_atomic_load(offtime_tick, high_frequency_min_offtime_tick); + return offtime_tick; +#else + return 0; +#endif +} + +/***************************************************************************//** + * Set configurable minimum off-time value for schedule wake-up in Sleeptimer + * ticks. + * + * @param minimum_offtime_tick minimum off-time value to set for schedule + * wake-up. + * + * @note Turning on external high frequency oscillator, such as HFXO, requires + * more energy since we must supply higher current for the wake-up. + * Therefore, when an 'external high frequency oscillator enable' is + * scheduled in 'x' time, there is a threshold 'x' value where turning + * off the oscillator is not worthwhile since the energy consumed by + * taking into account the wake-up will be greater than if we just keep + * the oscillator on until the next scheduled oscillator enabled. This + * threshold value is what we refer as the minimum off-time. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_schedule_wakeup_set_minimum_offtime_tick(uint32_t minimum_offtime_tick) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + sl_atomic_store(high_frequency_min_offtime_tick, minimum_offtime_tick); +#else + (void)minimum_offtime_tick; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Converts microseconds time in sleeptimer ticks. + ******************************************************************************/ +uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us) +{ + return (((time_us * sleeptimer_frequency) + (1000000 - 1)) / 1000000); +} +#endif + +/***************************************************************************//** + * Last-chance check before sleep. + * + * @return True, if the system should actually sleep. + * False, if not. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_is_ok_to_sleep(void) +{ + return true; +} + +/***************************************************************************//** + * Check if the MCU can sleep after an interrupt. + * + * @return True, if the system can sleep after the interrupt. + * False, otherwise. + * + * @note This is the fallback implementation of the callback, it can be + * overridden by the application or other components. + ******************************************************************************/ +__WEAK bool sl_power_manager_sleep_on_isr_exit(void) +{ + return false; +} + +/**************************************************************************//** + * Determines if the HFXO interrupt was part of the last wake-up and/or if + * the HFXO early wakeup expired during the last ISR + * and if it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + * + * @note This function will always return false in case + * a requirement is added on SL_POWER_MANAGER_EM1, + * since we will never sleep at a lower level than EM1. + *****************************************************************************/ +bool sl_power_manager_is_latest_wakeup_internal(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + CORE_DECLARE_IRQ_STATE; + bool sleep; + + CORE_ENTER_CRITICAL(); + sleep = is_restored_from_hfxo_isr; + is_restored_from_hfxo_isr = false; + CORE_EXIT_CRITICAL(); + + sleep |= sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(); + return sleep; +#else + return false; +#endif +} + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Get lowest energy mode to apply given the requirements on the different + * energy modes. + * + * @return Lowest energy mode: EM1, EM2 or EM3. + * + * @note If no requirement for any energy mode (EM1 and EM2), lowest energy mode + * is EM3. + ******************************************************************************/ +static sl_power_manager_em_t get_lowest_em(void) +{ + uint32_t em_ix; + sl_power_manager_em_t em; + + // Retrieve lowest Energy mode allowed given the requirements + for (em_ix = 1; (em_ix < 3) && (requirement_em_table[em_ix - 1] == 0); em_ix++) { + ; + } + + em = (sl_power_manager_em_t)em_ix; + + return em; +} +#endif + +/***************************************************************************//** + * Notify subscribers about energy mode transition. + * + * @param from Energy mode from which CPU comes from. + * + * @param to Energy mode to which CPU is going to. + ******************************************************************************/ +static void power_manager_notify_em_transition(sl_power_manager_em_t from, + sl_power_manager_em_t to) +{ + sl_power_manager_em_transition_event_handle_t *handle; + sl_power_manager_em_transition_event_t transition = 0; + + switch (to) { + case SL_POWER_MANAGER_EM0: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM2; + break; + + case SL_POWER_MANAGER_EM3: + transition = SL_POWER_MANAGER_EVENT_TRANSITION_ENTERING_EM3; + break; + + default: + EFM_ASSERT(0); + } + + switch (from) { + case SL_POWER_MANAGER_EM0: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM0; + break; + + case SL_POWER_MANAGER_EM1: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM1; + break; + + case SL_POWER_MANAGER_EM2: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM2; + break; + + case SL_POWER_MANAGER_EM3: + transition |= SL_POWER_MANAGER_EVENT_TRANSITION_LEAVING_EM3; + break; + + default: + EFM_ASSERT(0); + } + + SL_SLIST_FOR_EACH_ENTRY(power_manager_em_transition_event_list, handle, sl_power_manager_em_transition_event_handle_t, node) { + if ((handle->info->event_mask & transition) > 0) { + handle->info->on_event(from, to); + } + } +} + +/***************************************************************************//** + * Enter critical section by disabling interrupts using PriMask. + * + * @return primask Initial primask state. + * + * @note @ref sl_power_manager_sleep() function should use PriMask to disable + * interrupts. + ******************************************************************************/ +static CORE_irqState_t enter_critical_with_primask(void) +{ + CORE_irqState_t irqState = __get_PRIMASK(); + __disable_irq(); + + return irqState; +} + +/***************************************************************************//** + * Exit critical section by re-enabling interrupts using PriMask. + * + * @param primask_state Initial primask state. + ******************************************************************************/ +static void exit_critical_with_primask(CORE_irqState_t primask_state) +{ + if (primask_state == 0U) { + __enable_irq(); + } +} +/***************************************************************************//** + * Evaluates scheduled wakeup and restart timer based on the wakeup time. + * If the remaining time is shorter than the wakeup time then add a requirement + * on EM1 for avoiding the wakeup delay time. + * + * @note Must be called in a critical section. + ******************************************************************************/ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +static void evaluate_wakeup(sl_power_manager_em_t to) +{ + sl_status_t status; + uint32_t tick_remaining; + + switch (to) { + case SL_POWER_MANAGER_EM0: + // Coming back from Sleep. + if (requirement_on_em1_added) { + update_em1_requirement(false); + requirement_on_em1_added = false; + } + break; + + case SL_POWER_MANAGER_EM1: + // External high frequency clock, such as HFXO, already enabled; No wakeup delay + break; + + case SL_POWER_MANAGER_EM2: + case SL_POWER_MANAGER_EM3: + // Get the time remaining until the next sleeptimer requiring early wake-up + status = sl_sleeptimer_get_remaining_time_of_first_timer(0, &tick_remaining); + if (status == SL_STATUS_OK) { + if (tick_remaining <= high_frequency_min_offtime_tick) { + // Add EM1 requirement if time remaining is to short to be energy efficient + // if going back to deepsleep. + update_em1_requirement(true); + requirement_on_em1_added = true; + } else { + int32_t wakeup_delay = 0; + int32_t cfg_overhead_tick = 0; + + // Calculate overall wake-up delay. + sl_atomic_load(cfg_overhead_tick, wakeup_time_config_overhead_tick); + wakeup_delay += cfg_overhead_tick; + wakeup_delay += sli_power_manager_get_wakeup_process_time_overhead(); + EFM_ASSERT(wakeup_delay >= 0); + if (tick_remaining <= (uint32_t)wakeup_delay) { + // Add EM1 requirement if time remaining is smaller than wake-up delay. + update_em1_requirement(true); + requirement_on_em1_added = true; + } else { + uint16_t hf_accuracy_clk_flag = 0; + if (sli_power_manager_is_high_freq_accuracy_clk_used()) { + hf_accuracy_clk_flag = SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG; + } + // Start internal sleeptimer to do the early wake-up. + sl_sleeptimer_restart_timer(&clock_wakeup_timer_handle, + (tick_remaining - (uint32_t)wakeup_delay), + on_clock_wakeup_timeout, + NULL, + 0, + (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | hf_accuracy_clk_flag)); + } + } + } + break; + + default: + EFM_ASSERT(false); + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Updates internal EM1 requirement. + * We add an internal EM1 requirement when we would usually go into EM2/EM3 + * but there is not enough time before the next schedule event requiring a + * clock restore. So we just go to sleep in EM1. + * We remove this internal EM1 requirement next time we wake-up. + * + * @param add true, to add EM1 requirement, + * false, to remove EM1 requirement. + * + * @note For internal use only. + * + * @note Need to be call inside a critical section. + ******************************************************************************/ +static void update_em1_requirement(bool add) +{ + // Cannot increment above 255 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == UINT8_MAX) && (add == true))); + // Cannot decrement below 0 (wraparound not allowed) + EFM_ASSERT(!((requirement_em_table[SL_POWER_MANAGER_EM1 - 1] == 0) && (add == false))); + +#if (SL_POWER_MANAGER_DEBUG == 1) + sli_power_manager_debug_log_em_requirement(SL_POWER_MANAGER_EM1, add, "PM_INTERNAL_EM1_REQUIREMENT"); +#endif + + // Increment (add) or decrement (remove) energy mode counter. + requirement_em_table[SL_POWER_MANAGER_EM1 - 1] += (add) ? 1 : -1; + + // In rare occasions a clock restore must be started here: + // - An asynchronous event wake-up the system from deepsleep very near the early wake-up event, + // When we re-enter the sleep loop, we delete the internal early wake-up timer, but during + // the evaluation before sleep, it is calculated that not enough time is remains to go to + // deepsleep. In that case, since we deleted the early wake-up timer we must start the + // restore process here. + // - A synchronous event is added during an ISR, when we evaluate if the timeout is bigger + // than the clock restore time, it's barely bigger, so no clock restore process is started + // at that time. But when we do the evaluate before sleep, the remaining time is now smaller + // than the clock restore delay. So me must start the restore process here. + if (add == true + && current_em >= SL_POWER_MANAGER_EM2 + && is_sleeping_waiting_for_clock_restore == false) { + clock_restore(); + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Do clock restore process and wait for it to be completed. + ******************************************************************************/ +static void clock_restore_and_wait(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + if (is_states_saved == true) { + if (is_actively_waiting_for_clock_restore == false) { + is_actively_waiting_for_clock_restore = true; + + // Since we will actively wait for clock restore, we cancel any current non-active wait. + is_sleeping_waiting_for_clock_restore = false; + } + + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + + CORE_EXIT_CRITICAL(); + // We remove the critical section in case HFXO fails to startup and the HFXO Interrupt needs to run to handle the error. + sli_power_manager_is_high_freq_accuracy_clk_ready(true); + CORE_ENTER_CRITICAL(); + if (is_actively_waiting_for_clock_restore) { + sli_power_manager_restore_states(); + is_actively_waiting_for_clock_restore = false; + } + + is_states_saved = false; + } + CORE_EXIT_CRITICAL(); +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Start clock restore process. + * + * @note Need to be call inside a critical section. + ******************************************************************************/ +static void clock_restore(void) +{ + // Check if we need to start the clock restore process + if (is_states_saved == true) { + if (is_hf_x_oscillator_not_preserved) { + sli_power_manager_restore_high_freq_accuracy_clk(); + is_hf_x_oscillator_not_preserved = false; + } + if (sli_power_manager_is_high_freq_accuracy_clk_ready(false)) { + // Do the clock restore if the HF oscillator is already ready + sli_power_manager_restore_states(); + is_states_saved = false; + + // We do the notification only when the restore is completed. + power_manager_notify_em_transition(current_em, SL_POWER_MANAGER_EM1); + current_em = SL_POWER_MANAGER_EM1; // Keep new active energy mode + } else { + // If the HF oscillator is not yet ready, we will go back to sleep while waiting + is_sleeping_waiting_for_clock_restore = true; + + // Save current EM to do the right notification later + waiting_clock_restore_from_em = current_em; + } + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Callback for clock enable timer. + * + * @param handle Pointer to sleeptimer handle + * + * @param data Pointer to callback data + * + * @note We restore the HF clocks and go to EM1 here to be ready in time for the + * Application sleeptimer callback. But no EM1 requirement is added + * here. Since the time until the Application sleeptimer times out is <= + * than the wake-up delay, it protects us from going back to sleep lower + * than EM1. After that, it's up to the Application sleeptimer callback to + * put a EM1 requirement if still needed. + ******************************************************************************/ +static void on_clock_wakeup_timeout(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + (void)handle; + (void)data; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + if (is_actively_waiting_for_clock_restore) { + // In case we are already actively waiting for HFXO ready in another ISR, just exit + CORE_EXIT_CRITICAL(); + return; + } + + // If needed start the clock restore process + clock_restore(); + + CORE_EXIT_CRITICAL(); +} +#endif + +/***************************************************************************//** + * HFXO ready notification callback for internal use with power manager + * + * @note Will only be used on series 2 devices when HFXO Manager is present. + ******************************************************************************/ +void sli_hfxo_manager_notify_ready_for_power_manager(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Complete HF restore and change current Energy mode + // The notification will be done once back in the sleep loop + if (current_em != SL_POWER_MANAGER_EM0 + && (is_sleeping_waiting_for_clock_restore == true)) { + sli_power_manager_restore_states(); + is_sleeping_waiting_for_clock_restore = false; + is_states_saved = false; + is_restored_from_hfxo_isr = true; + is_restored_from_hfxo_isr_internal = true; + } +#endif +} + +/***************************************************************************//** + * HFXO PRS ready notification callback for internal use with power manager + * + * @note Will only be used on series 2 devices when HFXO Manager and SYSRTC + * is present. + ******************************************************************************/ +void sli_hfxo_notify_ready_for_power_manager_from_prs(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + // Set clock restore to true to indicate that HFXO has been restored from a + // PRS interrupt unless already in EM0 indicating HFXO didn't need to be restored. + if (current_em != SL_POWER_MANAGER_EM0) { + is_sleeping_waiting_for_clock_restore = true; + } +#endif +} + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + * + * @note This function will do nothing when a project contains the + * power_manager_no_deepsleep component, which configures the + * lowest energy mode as EM1. + ******************************************************************************/ +void sl_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) +{ +#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_CRITICAL(); + + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(enable); + + CORE_EXIT_CRITICAL(); +#else + (void)enable; +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_debug.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_debug.c index 10405f9..a803d8d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_debug.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_debug.c @@ -1,169 +1,169 @@ -/***************************************************************************//** - * @file - * @brief Power Manager Debug API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_power_manager.h" -#include "sl_power_manager_config.h" -#include "sl_power_manager_debug.h" -#include "sli_power_manager_private.h" - -#if (SL_POWER_MANAGER_DEBUG == 1) -#include -#include -#include -#include - -static sl_slist_node_t *power_manager_debug_requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE]; -static sli_power_debug_requirement_entry_t power_debug_entry_table[SL_POWER_MANAGER_DEBUG_POOL_SIZE]; -static sl_slist_node_t *power_debug_free_entry_list = NULL; -static bool power_debug_ran_out_of_entry = false; - -#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) -static void power_manager_log_add_requirement(sl_slist_node_t **p_list, - bool add, - const char *name); -#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - -/***************************************************************************//** - * Print a fancy table that describes the current requirements on each energy - * mode and their owner. - ******************************************************************************/ -void sl_power_manager_debug_print_em_requirements(void) -{ - uint8_t i; - sli_power_debug_requirement_entry_t *entry; - - if (power_debug_ran_out_of_entry) { - printf("WARNING: The system ran out of Debug Entry; This report is likely to be incomplete. Increase SL_POWER_MANAGER_DEBUG_POOL_SIZE\n\n"); - } - printf("------------------------------------------\n"); - printf("| EM requirements\n"); - printf("------------------------------------------\n"); - for (i = 0; i < SLI_POWER_MANAGER_EM_TABLE_SIZE; i++) { - if (power_manager_debug_requirement_em_table[i] != NULL) { - printf("| EM%d requirement module owners:\n", i + 1); - } - SL_SLIST_FOR_EACH_ENTRY(power_manager_debug_requirement_em_table[i], entry, sli_power_debug_requirement_entry_t, node) { - printf("| %s\n", entry->module_name); - } - if (power_manager_debug_requirement_em_table[i] != NULL) { - printf("------------------------------------------\n"); - } - } -} - -/***************************************************************************//** - * Initialize debugging feature. - ******************************************************************************/ -void sli_power_manager_debug_init(void) -{ - uint32_t i; - - for (i = 0; i < SL_POWER_MANAGER_DEBUG_POOL_SIZE; i++) { - sli_power_debug_requirement_entry_t *entry = &power_debug_entry_table[i]; - sl_slist_push(&power_debug_free_entry_list, &entry->node); - } -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Log requirement to a list - * - * @param p_list List where to push or remove the requirement. - * - * @param add Add (true) or remove (false) the requirement. - * - * @param name Module name that acquired or remove the requirement. - ******************************************************************************/ -static void power_manager_log_add_requirement(sl_slist_node_t **p_list, - bool add, - const char *name) -{ - sl_slist_node_t *node; - sli_power_debug_requirement_entry_t *entry; - - if (add == true) { - // Get entry from free list - node = sl_slist_pop(&power_debug_free_entry_list); - if (node == NULL) { - power_debug_ran_out_of_entry = true; - return; - } - - // Push entry to the EMx requirement debug list - entry = SL_SLIST_ENTRY(node, sli_power_debug_requirement_entry_t, node); - entry->module_name = name; - sl_slist_push(p_list, &entry->node); - } else { - sli_power_debug_requirement_entry_t *entry_remove = NULL; - - // Search in the EMx requirement debug list - SL_SLIST_FOR_EACH_ENTRY(*p_list, entry, sli_power_debug_requirement_entry_t, node) { - // Current module name and entry module name - if (strcmp(entry->module_name, name) == 0) { - entry_remove = entry; - break; - } - } - - if (entry_remove == NULL) { - return; - } - - sl_slist_remove(p_list, &entry_remove->node); - sl_slist_push(&power_debug_free_entry_list, &entry_remove->node); - } -} -#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -#endif // SL_POWER_MANAGER_DEBUG - -#undef sli_power_manager_debug_log_em_requirement -/***************************************************************************//** - * Log energy mode (EM) requirement - * - * @param em Energy mode added or removed. - * - * @param add Add (true) or remove (false) the requirement. - * - * @param name Module name that adds or removes the requirement. - ******************************************************************************/ -void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, - bool add, - const char *name) -{ -#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) && (SL_POWER_MANAGER_DEBUG == 1)) - if (em != SL_POWER_MANAGER_EM0) { - power_manager_log_add_requirement(&power_manager_debug_requirement_em_table[em - 1], add, name); - } -#else - (void)em; - (void)add; - (void)name; -#endif -} +/***************************************************************************//** + * @file + * @brief Power Manager Debug API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_power_manager_config.h" +#include "sl_power_manager_debug.h" +#include "sli_power_manager_private.h" + +#if (SL_POWER_MANAGER_DEBUG == 1) +#include +#include +#include +#include + +static sl_slist_node_t *power_manager_debug_requirement_em_table[SLI_POWER_MANAGER_EM_TABLE_SIZE]; +static sli_power_debug_requirement_entry_t power_debug_entry_table[SL_POWER_MANAGER_DEBUG_POOL_SIZE]; +static sl_slist_node_t *power_debug_free_entry_list = NULL; +static bool power_debug_ran_out_of_entry = false; + +#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) +static void power_manager_log_add_requirement(sl_slist_node_t **p_list, + bool add, + const char *name); +#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + +/***************************************************************************//** + * Print a fancy table that describes the current requirements on each energy + * mode and their owner. + ******************************************************************************/ +void sl_power_manager_debug_print_em_requirements(void) +{ + uint8_t i; + sli_power_debug_requirement_entry_t *entry; + + if (power_debug_ran_out_of_entry) { + printf("WARNING: The system ran out of Debug Entry; This report is likely to be incomplete. Increase SL_POWER_MANAGER_DEBUG_POOL_SIZE\n\n"); + } + printf("------------------------------------------\n"); + printf("| EM requirements\n"); + printf("------------------------------------------\n"); + for (i = 0; i < SLI_POWER_MANAGER_EM_TABLE_SIZE; i++) { + if (power_manager_debug_requirement_em_table[i] != NULL) { + printf("| EM%d requirement module owners:\n", i + 1); + } + SL_SLIST_FOR_EACH_ENTRY(power_manager_debug_requirement_em_table[i], entry, sli_power_debug_requirement_entry_t, node) { + printf("| %s\n", entry->module_name); + } + if (power_manager_debug_requirement_em_table[i] != NULL) { + printf("------------------------------------------\n"); + } + } +} + +/***************************************************************************//** + * Initialize debugging feature. + ******************************************************************************/ +void sli_power_manager_debug_init(void) +{ + uint32_t i; + + for (i = 0; i < SL_POWER_MANAGER_DEBUG_POOL_SIZE; i++) { + sli_power_debug_requirement_entry_t *entry = &power_debug_entry_table[i]; + sl_slist_push(&power_debug_free_entry_list, &entry->node); + } +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Log requirement to a list + * + * @param p_list List where to push or remove the requirement. + * + * @param add Add (true) or remove (false) the requirement. + * + * @param name Module name that acquired or remove the requirement. + ******************************************************************************/ +static void power_manager_log_add_requirement(sl_slist_node_t **p_list, + bool add, + const char *name) +{ + sl_slist_node_t *node; + sli_power_debug_requirement_entry_t *entry; + + if (add == true) { + // Get entry from free list + node = sl_slist_pop(&power_debug_free_entry_list); + if (node == NULL) { + power_debug_ran_out_of_entry = true; + return; + } + + // Push entry to the EMx requirement debug list + entry = SL_SLIST_ENTRY(node, sli_power_debug_requirement_entry_t, node); + entry->module_name = name; + sl_slist_push(p_list, &entry->node); + } else { + sli_power_debug_requirement_entry_t *entry_remove = NULL; + + // Search in the EMx requirement debug list + SL_SLIST_FOR_EACH_ENTRY(*p_list, entry, sli_power_debug_requirement_entry_t, node) { + // Current module name and entry module name + if (strcmp(entry->module_name, name) == 0) { + entry_remove = entry; + break; + } + } + + if (entry_remove == NULL) { + return; + } + + sl_slist_remove(p_list, &entry_remove->node); + sl_slist_push(&power_debug_free_entry_list, &entry_remove->node); + } +} +#endif // !(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +#endif // SL_POWER_MANAGER_DEBUG + +#undef sli_power_manager_debug_log_em_requirement +/***************************************************************************//** + * Log energy mode (EM) requirement + * + * @param em Energy mode added or removed. + * + * @param add Add (true) or remove (false) the requirement. + * + * @param name Module name that adds or removes the requirement. + ******************************************************************************/ +void sli_power_manager_debug_log_em_requirement(sl_power_manager_em_t em, + bool add, + const char *name) +{ +#if (!defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) && (SL_POWER_MANAGER_DEBUG == 1)) + if (em != SL_POWER_MANAGER_EM0) { + power_manager_log_add_requirement(&power_manager_debug_requirement_em_table[em - 1], add, name); + } +#else + (void)em; + (void)add; + (void)name; +#endif +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_hal_s2.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_hal_s2.c index 4207710..49d25c0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_hal_s2.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sl_power_manager_hal_s2.c @@ -1,664 +1,664 @@ -/***************************************************************************//** - * @file - * @brief Power Manager HAL API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" -#if defined(_SILICON_LABS_32B_SERIES_2) -#include "em_emu.h" -#include "em_cmu.h" -#include "sl_assert.h" -#include "sl_power_manager_config.h" -#include "sl_power_manager.h" -#include "sli_power_manager_private.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer.h" -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) -#include "sli_hfxo_manager.h" -#endif - -#include - -/******************************************************************************* - ********************************* DEFINES ********************************* - ******************************************************************************/ - -// Time required by the hardware to come out of EM2 in microseconds. -// This value includes HW startup, emlib and sleepdrv execution time. -// Voltage scaling, HFXO startup and HFXO steady times are excluded from -// this because they are handled separately. RTCCSYNC time is also -// excluded and it is handled by RTCCSYNC code itself. -#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) -#else // (_SILICON_LABS_32B_SERIES_2_CONFIG == 2), -#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) -#endif - -// DPLL Locking delay related defines -#define DPLL_COARSECOUNT_VALUE (5u) - -// Time it takes to upscale voltage after EM2 in microseconds. -// This value represents the time for scaling from VSCALE0 to VSCALE2. -#define EM2_WAKEUP_VSCALE_OVERHEAD_US (64u) - -// Default time value in microseconds required to wake-up the hfxo oscillator. -#define HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US (400u) - -// high frequency oscillator wake-up time margin for possible variation -// A shift by 3 will be like a division by 8, so a percentage of 12.5%. -#define HFXO_START_UP_TIME_OVERHEAD_LOG2 3 - -// Default time value in microseconds for the HFXO minimum off time. -#define HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US (400u) - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) -// Table size of HFXO wake-up time measurement -#define HFXO_WAKE_UP_TIME_TABLE_SIZE 10 -#endif - -// Defines for hidden HFXO0 DBGSTATUS register and STARTUPDONE flag -#define HFXO0_DBGSTATUS (*(volatile uint32_t *)(HFXO0_BASE + 0x05C)) -#define HFXO_DBGSTATUS_STARTUPDONE (0x1UL << 1) /**< Startup Done Status */ -#define _HFXO_DBGSTATUS_STARTUPDONE_SHIFT 1 /**< Shift value for HFXO_STARTUPDONE */ -#define _HFXO_DBGSTATUS_STARTUPDONE_MASK 0x2UL /**< Bit mask for HFXO_STARTUPDONE */ - -/******************************************************************************* - ******************************* MACROS ************************************* - ******************************************************************************/ - -/******************************************************************************* -* DPLL lock time can be approximately calculated by the equation: -* COARSECOUNT * (M + 1) * Tref -* Where -* - COARSECOUNT is calibration value in a hidden register. Its default value -* is 5 and should not change with calibration. -* - M is one the DPLL configuration parameter. -* - Tref is the reference clock period. -*******************************************************************************/ -#define DPLL_LOCKING_DELAY_US_FUNCTION(M, freq_ref) \ - ((uint64_t)(DPLL_COARSECOUNT_VALUE * ((M) +1)) * 1000000 + ((freq_ref) - 1)) / (freq_ref) - -/******************************************************************************* - *************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -// Variables to save the relevant clock registers. -uint32_t cmu_em01_grpA_clock_register; -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) -uint32_t cmu_em01_grpB_clock_register; -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) -uint32_t cmu_em01_grpC_clock_register; -#endif -#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) -uint32_t cmu_dpll_ref_clock_register; -#endif - -uint32_t cmu_sys_clock_register; - -// Time in ticks required for the general wake-up process. -static uint32_t process_wakeup_overhead_tick = 0; - -#if defined(EMU_VSCALE_PRESENT) -static bool is_fast_wakeup_enabled = true; -#endif - -static bool is_hf_x_oscillator_used = false; -static bool is_dpll_used = false; -static bool is_entering_deepsleep = false; - -static bool is_hf_x_oscillator_already_started = false; - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) -static uint32_t hf_x_oscillator_wakeup_time_tc_inital = 0; - -static uint32_t hfxo_wakeup_time_table[HFXO_WAKE_UP_TIME_TABLE_SIZE]; -static uint8_t hfxo_wakeup_time_table_index = 0; -static uint32_t hfxo_wakeup_time_sum_average = 0; - -// Time in ticks required for HFXO start-up after wake-up from sleep. -static uint32_t hfxo_wakeup_time_tick = 0; -#endif -#endif - -/******************************************************************************* - ************************** LOCAL FUNCTIONS ******************************** - ******************************************************************************/ - -/***************************************************************************//** - * Do some hardware initialization if necessary. - ******************************************************************************/ -void sli_power_manager_init_hardware(void) -{ - // Initializes EMU (voltage scaling in EM2/3) -#if defined(EMU_VSCALE_EM01_PRESENT) - EMU_EM01Init_TypeDef em01_init = EMU_EM01INIT_DEFAULT; - - EMU_EM01Init(&em01_init); -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -#if defined(EMU_VSCALE_PRESENT) -#if defined(SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP) -#if (SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP == 0) - sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); -#else - sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(true); -#endif -#else - sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); -#endif -#endif - - // Get the current HF oscillator for the SYSCLK - cmu_sys_clock_register = CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK; -#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) - cmu_dpll_ref_clock_register = CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK; -#endif - -#if defined(CMU_CLKEN0_DPLL0) - CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; - - CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; -#endif - - is_dpll_used = ((DPLL0->STATUS & _DPLL_STATUS_ENS_MASK) != 0); - - is_hf_x_oscillator_used = ((cmu_sys_clock_register == CMU_SYSCLKCTRL_CLKSEL_HFXO) - || ((CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) == CMU_EM01GRPACLKCTRL_CLKSEL_HFXO)); - -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) - is_hf_x_oscillator_used |= (CMU->RADIOCLKCTRL & _CMU_RADIOCLKCTRL_EN_MASK) != 0; -#endif - -#if defined(CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO) - is_hf_x_oscillator_used |= ((CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO); -#endif - -#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO) - is_hf_x_oscillator_used |= ((CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO); -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - // Set HFXO wakeup time to conservative default value - hfxo_wakeup_time_tick = sli_power_manager_convert_delay_us_to_tick(HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US); - for (uint8_t i = 0; i < HFXO_WAKE_UP_TIME_TABLE_SIZE; i++) { - hfxo_wakeup_time_table[i] = hfxo_wakeup_time_tick; - hfxo_wakeup_time_sum_average += hfxo_wakeup_time_tick; - } -#endif - - if (is_dpll_used && !is_hf_x_oscillator_used) { - is_hf_x_oscillator_used |= (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) == _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; - } - - // Calculate DPLL locking delay from its configuration - if (is_dpll_used) { - uint32_t freq = 0; - - switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { - case _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: - freq = SystemHFXOClockGet(); - break; - - case _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: - freq = SystemLFXOClockGet(); - break; - - case _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: - freq = SystemCLKIN0Get(); - break; - - default: - EFM_ASSERT(false); - break; - } - if (freq > 0) { // Avoid division by 0 - // Add DPLL Locking delay - process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(DPLL_LOCKING_DELAY_US_FUNCTION((DPLL0->CFG1 & _DPLL_CFG1_M_MASK) >> _DPLL_CFG1_M_SHIFT, freq)); - } - } - - process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US); -#endif -} - -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3. - ******************************************************************************/ -void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) -{ -#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - - if (enable == is_fast_wakeup_enabled) { - return; - } - - EMU_EM23Init_TypeDef em23_init = EMU_EM23INIT_DEFAULT; - - // Enable/disable EMU voltage scaling in EM2/3 - if (enable) { - em23_init.vScaleEM23Voltage = emuVScaleEM23_FastWakeup; - } else { - em23_init.vScaleEM23Voltage = emuVScaleEM23_LowPower; - } - - EMU_EM23Init(&em23_init); - - // Calculate and add voltage scaling wake-up delays in ticks - if (enable) { - // Remove voltage scaling delay if it was added before - process_wakeup_overhead_tick -= sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); - } else { - // Add voltage scaling delay if it was not added before - process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); - } - - is_fast_wakeup_enabled = enable; -#else - (void)enable; -#endif -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Save the CMU HF clock select state, oscillator enable, and voltage scaling. - ******************************************************************************/ -void sli_power_manager_save_states(void) -{ - // Save HF clock sources - cmu_em01_grpA_clock_register = CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK; -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) - cmu_em01_grpB_clock_register = CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK; -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) - cmu_em01_grpC_clock_register = CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK; -#endif - - EMU_Save(); -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Handle pre-sleep operations if any are necessary, like manually disabling - * oscillators, change clock settings, etc. - ******************************************************************************/ -void EMU_EM23PresleepHook(void) -{ - // Change the HF Clocks to be on FSRCO before sleep - if (is_entering_deepsleep) { - is_entering_deepsleep = false; - - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | _CMU_SYSCLKCTRL_CLKSEL_FSRCO; - // Switch the HF Clocks oscillator's to FSRCO before deepsleep - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; -#endif - // Disable DPLL before deepsleep -#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) -#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) - if (is_dpll_used) { - DPLL0->EN_CLR = DPLL_EN_EN; - while ((DPLL0->EN & _DPLL_EN_DISABLING_MASK) != 0) { - } - } -#endif -#endif - - SystemCoreClockUpdate(); - } - // Clear HFXO IEN RDY before entering sleep to prevent HFXO HW requests from waking up the system - HFXO0->IEN_CLR = HFXO_IEN_RDY; -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Handle post-sleep operations. The idea is to start HFXO ASAP when we know we - * will need it. - * - * @note In case HFXO is already started when we wake-up (ENS flag is up), - * the hidden flag STARTUPDONE is check to see if the HFXO was just - * enabled or not. If HFXO is enabled automatically following the wake-up, - * the STARTUPDONE flag will not yet be up, and it's an indication that - * we can still process to the HFXO restore time measurement. - ******************************************************************************/ -void EMU_EM23PostsleepHook(void) -{ - // Re enable HFXO IEN RDY since it was disabled in EMU_EM23PresleepHook - HFXO0->IEN_SET = HFXO_IEN_RDY; - - // Poke sleeptimer to determine if power manager's timer expired before the - // ISR handler executes. - // Also, check if HFXO is used. - if (is_hf_x_oscillator_used - && sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_COMP) - && sli_sleeptimer_is_power_manager_timer_next_to_expire()) { - // Check if HFXO is already running and has finished its startup. - // If yes, don't do the HFXO restore time measurement. - if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 - && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) - || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { -#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - // Force-enable HFXO in case the HFXO on-demand request would be removed - // before we finish the restore process. - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -#endif - return; - } - - // Start measure HFXO restore time. - is_hf_x_oscillator_already_started = true; - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); - - // Switch SYSCLK to HFXO to measure restore time - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; - SystemCoreClockUpdate(); -#else - sli_hfxo_manager_begin_startup_measurement(); - - // Force enable HFXO to measure restore time - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -#endif - } -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Handle pre-deepsleep operations if any are necessary, like manually disabling - * oscillators, change clock settings, etc. - ******************************************************************************/ -void sli_power_manager_handle_pre_deepsleep_operations(void) -{ - is_entering_deepsleep = true; -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Handle post-sleep operations if any are necessary, like manually enabling - * oscillators, change clock settings, etc. - ******************************************************************************/ -void sli_power_manager_restore_high_freq_accuracy_clk(void) -{ - if (!is_hf_x_oscillator_used) { - return; - } - - // For the cases where it's not started from an early wake up - // And if HFXO is not already running. - if (!is_hf_x_oscillator_already_started) { - // Check if HFXO is already running and has finished its startup. - // If yes, don't do the HFXO restore time measurement. - if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 - && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) - || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { -#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - // Force-enable HFXO in case the HFXO on-demand request would be removed - // before we finish the restore process. - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -#endif - return; - } - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); - - // Switch SYSCLK to HFXO to measure restore time - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; - SystemCoreClockUpdate(); -#else - // Start measure HFXO restore time - sli_hfxo_manager_begin_startup_measurement(); - - // Force enable HFXO to measure restore time - HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; -#endif - } - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - uint32_t current_time = sl_sleeptimer_get_tick_count() - hf_x_oscillator_wakeup_time_tc_inital; - // Calculate average for HFXO restore time - hfxo_wakeup_time_sum_average -= (int32_t)hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] - (int32_t)current_time; - hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] = current_time; - hfxo_wakeup_time_tick = ((hfxo_wakeup_time_sum_average + (HFXO_WAKE_UP_TIME_TABLE_SIZE - 1) ) / HFXO_WAKE_UP_TIME_TABLE_SIZE); - - // Update index of wakeup time table - hfxo_wakeup_time_table_index++; - hfxo_wakeup_time_table_index %= HFXO_WAKE_UP_TIME_TABLE_SIZE; -#endif - - is_hf_x_oscillator_already_started = false; -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Checks if HF accuracy clocks is fully restored and, if needed, waits for it. - * - * @param wait True, to wait for HF accuracy clocks to be ready - * False, otherwise. - * - * @return True, if HFXO ready. - * False, otherwise. - ******************************************************************************/ -bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait) -{ - if (!is_hf_x_oscillator_used) { - return true; - } - -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - (void)wait; - return true; -#else - return sli_hfxo_manager_is_hfxo_ready(wait); -#endif -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Restore CMU HF clock select state, oscillator enable, and voltage scaling. - ******************************************************************************/ -void sli_power_manager_restore_states(void) -{ - // Restore specific EMU saved contexts - EMU_Restore(); - - // Restore DPLL after deepsleep -#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) -#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) - if (is_dpll_used) { - DPLL0->EN_SET = DPLL_EN_EN; - while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { - } - } -#endif -#endif - - // Restore SYSCLK to what it was before the deepsleep - CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmu_sys_clock_register; - - // Restore the HF Clocks to what they were before deepsleep - CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | cmu_em01_grpA_clock_register; -#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) - CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | cmu_em01_grpB_clock_register; -#endif -#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) - CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | cmu_em01_grpC_clock_register; -#endif - - // Remove FORCEEN on HFXO - if (is_hf_x_oscillator_used) { - HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; - } - - SystemCoreClockUpdate(); - -#if 0 // TODO PLATFORM_MTL-8499 - // Wait for DPLL to lock - if (is_dpll_used) { - while (!(DPLL0->STATUS && _DPLL_STATUS_RDY_MASK)) { - } - } -#endif -} -#endif - -/***************************************************************************//** - * Applies energy mode. - * - * @param em Energy mode to apply: - * SL_POWER_MANAGER_EM0 - * SL_POWER_MANAGER_EM1 - * SL_POWER_MANAGER_EM2 - * - * @note EMU_EnterEM2() and EMU_EnterEM3() has the parameter 'restore' set to - * true in the Power Manager. When set to true, the parameter 'restore' - * allows the EMU driver to save and restore oscillators, clocks and - * voltage scaling. When the processor returns from EM2 or EM3, its - * execution resumes in a clean and stable state. - ******************************************************************************/ -void sli_power_manager_apply_em(sl_power_manager_em_t em) -{ - // Perform required actions according to energy mode - switch (em) { - case SL_POWER_MANAGER_EM1: -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - // when measuring interrupt disabled time, we don't - // want to count the time spent in sleep - sl_cycle_counter_pause(); -#endif - EMU_EnterEM1(); -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) - sl_cycle_counter_resume(); -#endif - break; - - case SL_POWER_MANAGER_EM2: - EMU_EnterEM2(false); - break; - - case SL_POWER_MANAGER_EM3: - EMU_EnterEM3(false); - break; - - case SL_POWER_MANAGER_EM0: - default: - EFM_ASSERT(false); - break; - } -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/******************************************************************************* - * Returns the default minimum offtime for HFXO. - ******************************************************************************/ -uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void) -{ - return sli_power_manager_convert_delay_us_to_tick(HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US); -} -#endif - -/******************************************************************************* - * Gets the delay associated the wake-up process from EM23. - * - * @return Delay for the complete wake-up process with full restore. - ******************************************************************************/ -uint32_t sli_power_manager_get_wakeup_process_time_overhead(void) -{ -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) - uint32_t delay = 0; - - // Add HFXO start-up delay if applicable - if (is_hf_x_oscillator_used) { -#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) - delay = hfxo_wakeup_time_tick; -#else - delay = sli_hfxo_manager_get_startup_time(); -#endif - delay += delay >> HFXO_START_UP_TIME_OVERHEAD_LOG2; - } - - // Add all additional overhead wake-up delays (DPLL, VSCALE, general wake-up process) - delay += process_wakeup_overhead_tick; - - return delay; -#else - return 0; -#endif -} - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/***************************************************************************//** - * Informs the power manager module that the high accuracy/high frequency clock - * is used. - ******************************************************************************/ -void sli_power_manager_set_high_accuracy_hf_clock_as_used(void) -{ - is_hf_x_oscillator_used = true; -} -#endif - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/******************************************************************************* - * Restores the Low Frequency clocks according to what LF oscillators are used. - * - * @note On series 2, the on-demand will enable automatically the oscillators - * used when coming from sleep. - ******************************************************************************/ -void sli_power_manager_low_frequency_restore(void) -{ -} - -/***************************************************************************//** - * Informs the power manager if the high accuracy/high frequency clock - * is used, prior to scheduling an early clock restore. - * - * @return true if HFXO is used, else false. - ******************************************************************************/ -bool sli_power_manager_is_high_freq_accuracy_clk_used(void) -{ - return is_hf_x_oscillator_used; -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief Power Manager HAL API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) +#include "em_emu.h" +#include "em_cmu.h" +#include "sl_assert.h" +#include "sl_power_manager_config.h" +#include "sl_power_manager.h" +#include "sli_power_manager_private.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer.h" +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +#include "sli_hfxo_manager.h" +#endif + +#include + +/******************************************************************************* + ********************************* DEFINES ********************************* + ******************************************************************************/ + +// Time required by the hardware to come out of EM2 in microseconds. +// This value includes HW startup, emlib and sleepdrv execution time. +// Voltage scaling, HFXO startup and HFXO steady times are excluded from +// this because they are handled separately. RTCCSYNC time is also +// excluded and it is handled by RTCCSYNC code itself. +#if (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) +#else // (_SILICON_LABS_32B_SERIES_2_CONFIG == 2), +#define EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US (31u) +#endif + +// DPLL Locking delay related defines +#define DPLL_COARSECOUNT_VALUE (5u) + +// Time it takes to upscale voltage after EM2 in microseconds. +// This value represents the time for scaling from VSCALE0 to VSCALE2. +#define EM2_WAKEUP_VSCALE_OVERHEAD_US (64u) + +// Default time value in microseconds required to wake-up the hfxo oscillator. +#define HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US (400u) + +// high frequency oscillator wake-up time margin for possible variation +// A shift by 3 will be like a division by 8, so a percentage of 12.5%. +#define HFXO_START_UP_TIME_OVERHEAD_LOG2 3 + +// Default time value in microseconds for the HFXO minimum off time. +#define HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US (400u) + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +// Table size of HFXO wake-up time measurement +#define HFXO_WAKE_UP_TIME_TABLE_SIZE 10 +#endif + +// Defines for hidden HFXO0 DBGSTATUS register and STARTUPDONE flag +#define HFXO0_DBGSTATUS (*(volatile uint32_t *)(HFXO0_BASE + 0x05C)) +#define HFXO_DBGSTATUS_STARTUPDONE (0x1UL << 1) /**< Startup Done Status */ +#define _HFXO_DBGSTATUS_STARTUPDONE_SHIFT 1 /**< Shift value for HFXO_STARTUPDONE */ +#define _HFXO_DBGSTATUS_STARTUPDONE_MASK 0x2UL /**< Bit mask for HFXO_STARTUPDONE */ + +/******************************************************************************* + ******************************* MACROS ************************************* + ******************************************************************************/ + +/******************************************************************************* +* DPLL lock time can be approximately calculated by the equation: +* COARSECOUNT * (M + 1) * Tref +* Where +* - COARSECOUNT is calibration value in a hidden register. Its default value +* is 5 and should not change with calibration. +* - M is one the DPLL configuration parameter. +* - Tref is the reference clock period. +*******************************************************************************/ +#define DPLL_LOCKING_DELAY_US_FUNCTION(M, freq_ref) \ + ((uint64_t)(DPLL_COARSECOUNT_VALUE * ((M) +1)) * 1000000 + ((freq_ref) - 1)) / (freq_ref) + +/******************************************************************************* + *************************** LOCAL VARIABLES ******************************** + ******************************************************************************/ + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +// Variables to save the relevant clock registers. +uint32_t cmu_em01_grpA_clock_register; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) +uint32_t cmu_em01_grpB_clock_register; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) +uint32_t cmu_em01_grpC_clock_register; +#endif +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) +uint32_t cmu_dpll_ref_clock_register; +#endif + +uint32_t cmu_sys_clock_register; + +// Time in ticks required for the general wake-up process. +static uint32_t process_wakeup_overhead_tick = 0; + +#if defined(EMU_VSCALE_PRESENT) +static bool is_fast_wakeup_enabled = true; +#endif + +static bool is_hf_x_oscillator_used = false; +static bool is_dpll_used = false; +static bool is_entering_deepsleep = false; + +static bool is_hf_x_oscillator_already_started = false; + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) +static uint32_t hf_x_oscillator_wakeup_time_tc_inital = 0; + +static uint32_t hfxo_wakeup_time_table[HFXO_WAKE_UP_TIME_TABLE_SIZE]; +static uint8_t hfxo_wakeup_time_table_index = 0; +static uint32_t hfxo_wakeup_time_sum_average = 0; + +// Time in ticks required for HFXO start-up after wake-up from sleep. +static uint32_t hfxo_wakeup_time_tick = 0; +#endif +#endif + +/******************************************************************************* + ************************** LOCAL FUNCTIONS ******************************** + ******************************************************************************/ + +/***************************************************************************//** + * Do some hardware initialization if necessary. + ******************************************************************************/ +void sli_power_manager_init_hardware(void) +{ + // Initializes EMU (voltage scaling in EM2/3) +#if defined(EMU_VSCALE_EM01_PRESENT) + EMU_EM01Init_TypeDef em01_init = EMU_EM01INIT_DEFAULT; + + EMU_EM01Init(&em01_init); +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +#if defined(EMU_VSCALE_PRESENT) +#if defined(SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP) +#if (SL_POWER_MANAGER_CONFIG_VOLTAGE_SCALING_FAST_WAKEUP == 0) + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); +#else + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(true); +#endif +#else + sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(false); +#endif +#endif + + // Get the current HF oscillator for the SYSCLK + cmu_sys_clock_register = CMU->SYSCLKCTRL & _CMU_SYSCLKCTRL_CLKSEL_MASK; +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + cmu_dpll_ref_clock_register = CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK; +#endif + +#if defined(CMU_CLKEN0_DPLL0) + CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0; + + CMU->CLKEN0_SET = CMU_CLKEN0_DPLL0; +#endif + + is_dpll_used = ((DPLL0->STATUS & _DPLL_STATUS_ENS_MASK) != 0); + + is_hf_x_oscillator_used = ((cmu_sys_clock_register == CMU_SYSCLKCTRL_CLKSEL_HFXO) + || ((CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK) == CMU_EM01GRPACLKCTRL_CLKSEL_HFXO)); + +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1) + is_hf_x_oscillator_used |= (CMU->RADIOCLKCTRL & _CMU_RADIOCLKCTRL_EN_MASK) != 0; +#endif + +#if defined(CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO) + is_hf_x_oscillator_used |= ((CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO); +#endif + +#if defined(CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO) + is_hf_x_oscillator_used |= ((CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) == CMU_EM01GRPCCLKCTRL_CLKSEL_HFXO); +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Set HFXO wakeup time to conservative default value + hfxo_wakeup_time_tick = sli_power_manager_convert_delay_us_to_tick(HFXO_WAKE_UP_TIME_DEFAULT_VALUE_US); + for (uint8_t i = 0; i < HFXO_WAKE_UP_TIME_TABLE_SIZE; i++) { + hfxo_wakeup_time_table[i] = hfxo_wakeup_time_tick; + hfxo_wakeup_time_sum_average += hfxo_wakeup_time_tick; + } +#endif + + if (is_dpll_used && !is_hf_x_oscillator_used) { + is_hf_x_oscillator_used |= (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) == _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO; + } + + // Calculate DPLL locking delay from its configuration + if (is_dpll_used) { + uint32_t freq = 0; + + switch (CMU->DPLLREFCLKCTRL & _CMU_DPLLREFCLKCTRL_CLKSEL_MASK) { + case _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO: + freq = SystemHFXOClockGet(); + break; + + case _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO: + freq = SystemLFXOClockGet(); + break; + + case _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0: + freq = SystemCLKIN0Get(); + break; + + default: + EFM_ASSERT(false); + break; + } + if (freq > 0) { // Avoid division by 0 + // Add DPLL Locking delay + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(DPLL_LOCKING_DELAY_US_FUNCTION((DPLL0->CFG1 & _DPLL_CFG1_M_MASK) >> _DPLL_CFG1_M_SHIFT, freq)); + } + } + + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_PROCESS_TIME_OVERHEAD_US); +#endif +} + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3. + ******************************************************************************/ +void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable) +{ +#if (defined(EMU_VSCALE_PRESENT) && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + + if (enable == is_fast_wakeup_enabled) { + return; + } + + EMU_EM23Init_TypeDef em23_init = EMU_EM23INIT_DEFAULT; + + // Enable/disable EMU voltage scaling in EM2/3 + if (enable) { + em23_init.vScaleEM23Voltage = emuVScaleEM23_FastWakeup; + } else { + em23_init.vScaleEM23Voltage = emuVScaleEM23_LowPower; + } + + EMU_EM23Init(&em23_init); + + // Calculate and add voltage scaling wake-up delays in ticks + if (enable) { + // Remove voltage scaling delay if it was added before + process_wakeup_overhead_tick -= sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); + } else { + // Add voltage scaling delay if it was not added before + process_wakeup_overhead_tick += sli_power_manager_convert_delay_us_to_tick(EM2_WAKEUP_VSCALE_OVERHEAD_US); + } + + is_fast_wakeup_enabled = enable; +#else + (void)enable; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Save the CMU HF clock select state, oscillator enable, and voltage scaling. + ******************************************************************************/ +void sli_power_manager_save_states(void) +{ + // Save HF clock sources + cmu_em01_grpA_clock_register = CMU->EM01GRPACLKCTRL & _CMU_EM01GRPACLKCTRL_CLKSEL_MASK; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + cmu_em01_grpB_clock_register = CMU->EM01GRPBCLKCTRL & _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + cmu_em01_grpC_clock_register = CMU->EM01GRPCCLKCTRL & _CMU_EM01GRPCCLKCTRL_CLKSEL_MASK; +#endif + + EMU_Save(); +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle pre-sleep operations if any are necessary, like manually disabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +void EMU_EM23PresleepHook(void) +{ + // Change the HF Clocks to be on FSRCO before sleep + if (is_entering_deepsleep) { + is_entering_deepsleep = false; + + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | _CMU_SYSCLKCTRL_CLKSEL_FSRCO; + // Switch the HF Clocks oscillator's to FSRCO before deepsleep + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | _CMU_EM01GRPCCLKCTRL_CLKSEL_FSRCO; +#endif + // Disable DPLL before deepsleep +#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + if (is_dpll_used) { + DPLL0->EN_CLR = DPLL_EN_EN; + while ((DPLL0->EN & _DPLL_EN_DISABLING_MASK) != 0) { + } + } +#endif +#endif + + SystemCoreClockUpdate(); + } + // Clear HFXO IEN RDY before entering sleep to prevent HFXO HW requests from waking up the system + HFXO0->IEN_CLR = HFXO_IEN_RDY; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle post-sleep operations. The idea is to start HFXO ASAP when we know we + * will need it. + * + * @note In case HFXO is already started when we wake-up (ENS flag is up), + * the hidden flag STARTUPDONE is check to see if the HFXO was just + * enabled or not. If HFXO is enabled automatically following the wake-up, + * the STARTUPDONE flag will not yet be up, and it's an indication that + * we can still process to the HFXO restore time measurement. + ******************************************************************************/ +void EMU_EM23PostsleepHook(void) +{ + // Re enable HFXO IEN RDY since it was disabled in EMU_EM23PresleepHook + HFXO0->IEN_SET = HFXO_IEN_RDY; + + // Poke sleeptimer to determine if power manager's timer expired before the + // ISR handler executes. + // Also, check if HFXO is used. + if (is_hf_x_oscillator_used + && sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_COMP) + && sli_sleeptimer_is_power_manager_timer_next_to_expire()) { + // Check if HFXO is already running and has finished its startup. + // If yes, don't do the HFXO restore time measurement. + if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 + && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) + || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { +#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Force-enable HFXO in case the HFXO on-demand request would be removed + // before we finish the restore process. + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + return; + } + + // Start measure HFXO restore time. + is_hf_x_oscillator_already_started = true; + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); + + // Switch SYSCLK to HFXO to measure restore time + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; + SystemCoreClockUpdate(); +#else + sli_hfxo_manager_begin_startup_measurement(); + + // Force enable HFXO to measure restore time + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + } +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle pre-deepsleep operations if any are necessary, like manually disabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +void sli_power_manager_handle_pre_deepsleep_operations(void) +{ + is_entering_deepsleep = true; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Handle post-sleep operations if any are necessary, like manually enabling + * oscillators, change clock settings, etc. + ******************************************************************************/ +void sli_power_manager_restore_high_freq_accuracy_clk(void) +{ + if (!is_hf_x_oscillator_used) { + return; + } + + // For the cases where it's not started from an early wake up + // And if HFXO is not already running. + if (!is_hf_x_oscillator_already_started) { + // Check if HFXO is already running and has finished its startup. + // If yes, don't do the HFXO restore time measurement. + if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 + && (HFXO0_DBGSTATUS & _HFXO_DBGSTATUS_STARTUPDONE_MASK) != 0) + || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { +#if !defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + // Force-enable HFXO in case the HFXO on-demand request would be removed + // before we finish the restore process. + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + return; + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + hf_x_oscillator_wakeup_time_tc_inital = sl_sleeptimer_get_tick_count(); + + // Switch SYSCLK to HFXO to measure restore time + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmuSelect_HFXO; + SystemCoreClockUpdate(); +#else + // Start measure HFXO restore time + sli_hfxo_manager_begin_startup_measurement(); + + // Force enable HFXO to measure restore time + HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; +#endif + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + uint32_t current_time = sl_sleeptimer_get_tick_count() - hf_x_oscillator_wakeup_time_tc_inital; + // Calculate average for HFXO restore time + hfxo_wakeup_time_sum_average -= (int32_t)hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] - (int32_t)current_time; + hfxo_wakeup_time_table[hfxo_wakeup_time_table_index] = current_time; + hfxo_wakeup_time_tick = ((hfxo_wakeup_time_sum_average + (HFXO_WAKE_UP_TIME_TABLE_SIZE - 1) ) / HFXO_WAKE_UP_TIME_TABLE_SIZE); + + // Update index of wakeup time table + hfxo_wakeup_time_table_index++; + hfxo_wakeup_time_table_index %= HFXO_WAKE_UP_TIME_TABLE_SIZE; +#endif + + is_hf_x_oscillator_already_started = false; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Checks if HF accuracy clocks is fully restored and, if needed, waits for it. + * + * @param wait True, to wait for HF accuracy clocks to be ready + * False, otherwise. + * + * @return True, if HFXO ready. + * False, otherwise. + ******************************************************************************/ +bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait) +{ + if (!is_hf_x_oscillator_used) { + return true; + } + +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + (void)wait; + return true; +#else + return sli_hfxo_manager_is_hfxo_ready(wait); +#endif +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Restore CMU HF clock select state, oscillator enable, and voltage scaling. + ******************************************************************************/ +void sli_power_manager_restore_states(void) +{ + // Restore specific EMU saved contexts + EMU_Restore(); + + // Restore DPLL after deepsleep +#if (_DPLL_IPVERSION_IPVERSION_DEFAULT >= 1) +#if defined(_CMU_DPLLREFCLKCTRL_CLKSEL_MASK) + if (is_dpll_used) { + DPLL0->EN_SET = DPLL_EN_EN; + while ((DPLL0->STATUS & _DPLL_STATUS_RDY_MASK) == 0U) { + } + } +#endif +#endif + + // Restore SYSCLK to what it was before the deepsleep + CMU->SYSCLKCTRL = (CMU->SYSCLKCTRL & ~_CMU_SYSCLKCTRL_CLKSEL_MASK) | cmu_sys_clock_register; + + // Restore the HF Clocks to what they were before deepsleep + CMU->EM01GRPACLKCTRL = (CMU->EM01GRPACLKCTRL & ~_CMU_EM01GRPACLKCTRL_CLKSEL_MASK) | cmu_em01_grpA_clock_register; +#if defined(_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPBCLKCTRL = (CMU->EM01GRPBCLKCTRL & ~_CMU_EM01GRPBCLKCTRL_CLKSEL_MASK) | cmu_em01_grpB_clock_register; +#endif +#if defined(_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) + CMU->EM01GRPCCLKCTRL = (CMU->EM01GRPCCLKCTRL & ~_CMU_EM01GRPCCLKCTRL_CLKSEL_MASK) | cmu_em01_grpC_clock_register; +#endif + + // Remove FORCEEN on HFXO + if (is_hf_x_oscillator_used) { + HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; + } + + SystemCoreClockUpdate(); + +#if 0 // TODO PLATFORM_MTL-8499 + // Wait for DPLL to lock + if (is_dpll_used) { + while (!(DPLL0->STATUS && _DPLL_STATUS_RDY_MASK)) { + } + } +#endif +} +#endif + +/***************************************************************************//** + * Applies energy mode. + * + * @param em Energy mode to apply: + * SL_POWER_MANAGER_EM0 + * SL_POWER_MANAGER_EM1 + * SL_POWER_MANAGER_EM2 + * + * @note EMU_EnterEM2() and EMU_EnterEM3() has the parameter 'restore' set to + * true in the Power Manager. When set to true, the parameter 'restore' + * allows the EMU driver to save and restore oscillators, clocks and + * voltage scaling. When the processor returns from EM2 or EM3, its + * execution resumes in a clean and stable state. + ******************************************************************************/ +void sli_power_manager_apply_em(sl_power_manager_em_t em) +{ + // Perform required actions according to energy mode + switch (em) { + case SL_POWER_MANAGER_EM1: +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + // when measuring interrupt disabled time, we don't + // want to count the time spent in sleep + sl_cycle_counter_pause(); +#endif + EMU_EnterEM1(); +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) + sl_cycle_counter_resume(); +#endif + break; + + case SL_POWER_MANAGER_EM2: + EMU_EnterEM2(false); + break; + + case SL_POWER_MANAGER_EM3: + EMU_EnterEM3(false); + break; + + case SL_POWER_MANAGER_EM0: + default: + EFM_ASSERT(false); + break; + } +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Returns the default minimum offtime for HFXO. + ******************************************************************************/ +uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void) +{ + return sli_power_manager_convert_delay_us_to_tick(HFXO_MINIMUM_OFFTIME_DEFAULT_VALUE_US); +} +#endif + +/******************************************************************************* + * Gets the delay associated the wake-up process from EM23. + * + * @return Delay for the complete wake-up process with full restore. + ******************************************************************************/ +uint32_t sli_power_manager_get_wakeup_process_time_overhead(void) +{ +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) + uint32_t delay = 0; + + // Add HFXO start-up delay if applicable + if (is_hf_x_oscillator_used) { +#if defined(SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT) + delay = hfxo_wakeup_time_tick; +#else + delay = sli_hfxo_manager_get_startup_time(); +#endif + delay += delay >> HFXO_START_UP_TIME_OVERHEAD_LOG2; + } + + // Add all additional overhead wake-up delays (DPLL, VSCALE, general wake-up process) + delay += process_wakeup_overhead_tick; + + return delay; +#else + return 0; +#endif +} + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/***************************************************************************//** + * Informs the power manager module that the high accuracy/high frequency clock + * is used. + ******************************************************************************/ +void sli_power_manager_set_high_accuracy_hf_clock_as_used(void) +{ + is_hf_x_oscillator_used = true; +} +#endif + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Restores the Low Frequency clocks according to what LF oscillators are used. + * + * @note On series 2, the on-demand will enable automatically the oscillators + * used when coming from sleep. + ******************************************************************************/ +void sli_power_manager_low_frequency_restore(void) +{ +} + +/***************************************************************************//** + * Informs the power manager if the high accuracy/high frequency clock + * is used, prior to scheduling an early clock restore. + * + * @return true if HFXO is used, else false. + ******************************************************************************/ +bool sli_power_manager_is_high_freq_accuracy_clk_used(void) +{ + return is_hf_x_oscillator_used; +} +#endif +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sli_power_manager_private.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sli_power_manager_private.h index 1fa7f0a..5923442 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sli_power_manager_private.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/power_manager/src/sli_power_manager_private.h @@ -1,142 +1,142 @@ -/***************************************************************************//** - * @file - * @brief Power Manager Internal API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_power_manager.h" -#include "sl_slist.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif - -#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) -#include "emlib_core_debug_config.h" -#endif - -#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) -#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 -#endif - -#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) -#include "sl_cycle_counter.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - ******************************* DEFINES *********************************** - ******************************************************************************/ - -#define SLI_POWER_MANAGER_EM_TABLE_SIZE 2 - -/******************************************************************************* - ***************************** DATA TYPES ********************************* - ******************************************************************************/ - -// Debug entry -typedef struct { - sl_slist_node_t node; - const char *module_name; -} sli_power_debug_requirement_entry_t; - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -void sli_power_manager_init_hardware(void); - -void sli_power_manager_apply_em(sl_power_manager_em_t em); - -void sli_power_manager_debug_init(void); - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -void sli_power_manager_save_states(void); - -void sli_power_manager_handle_pre_deepsleep_operations(void); - -void sli_power_manager_restore_high_freq_accuracy_clk(void); - -bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait); - -void sli_power_manager_restore_states(void); - -/******************************************************************************* - * Converts microseconds time in sleeptimer ticks. - ******************************************************************************/ -uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us); - -/******************************************************************************* - * Returns the default minimum offtime for xtal high frequency oscillator. - ******************************************************************************/ -uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void); - -/******************************************************************************* - * Restores the Low Frequency clocks according to which LF oscillators are used. - ******************************************************************************/ -void sli_power_manager_low_frequency_restore(void); - -/***************************************************************************//** - * Informs the power manager if the high accuracy/high frequency clock - * is used, prior to scheduling an early clock restore. - * - * @return true if HFXO is used, else false. - ******************************************************************************/ -bool sli_power_manager_is_high_freq_accuracy_clk_used(void); -#endif - -/***************************************************************************//** - * Enable or disable fast wake-up in EM2 and EM3 - * - * @note Will also update the wake up time from EM2 to EM0. - ******************************************************************************/ -void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); - -/******************************************************************************* - * Gets the delay associated the wake-up process from EM23. - * - * @return Delay for the complete wake-up process with full restore. - ******************************************************************************/ -uint32_t sli_power_manager_get_wakeup_process_time_overhead(void); - -#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) -/******************************************************************************* - * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. - * - * @return true if Power Manager is sleeping waiting for clock restore, else false. - * - * @note FOR INTERNAL USE ONLY. - ******************************************************************************/ -bool sli_power_manager_get_clock_restore_status(void); -#endif - -#ifdef __cplusplus -} -#endif +/***************************************************************************//** + * @file + * @brief Power Manager Internal API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_power_manager.h" +#include "sl_slist.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif + +#if defined(SL_CATALOG_EMLIB_CORE_DEBUG_CONFIG_PRESENT) +#include "emlib_core_debug_config.h" +#endif + +#if !defined(SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING) +#define SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING 0 +#endif + +#if (SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING == 1) +#include "sl_cycle_counter.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + ******************************* DEFINES *********************************** + ******************************************************************************/ + +#define SLI_POWER_MANAGER_EM_TABLE_SIZE 2 + +/******************************************************************************* + ***************************** DATA TYPES ********************************* + ******************************************************************************/ + +// Debug entry +typedef struct { + sl_slist_node_t node; + const char *module_name; +} sli_power_debug_requirement_entry_t; + +/******************************************************************************* + ***************************** PROTOTYPES ********************************** + ******************************************************************************/ + +void sli_power_manager_init_hardware(void); + +void sli_power_manager_apply_em(sl_power_manager_em_t em); + +void sli_power_manager_debug_init(void); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +void sli_power_manager_save_states(void); + +void sli_power_manager_handle_pre_deepsleep_operations(void); + +void sli_power_manager_restore_high_freq_accuracy_clk(void); + +bool sli_power_manager_is_high_freq_accuracy_clk_ready(bool wait); + +void sli_power_manager_restore_states(void); + +/******************************************************************************* + * Converts microseconds time in sleeptimer ticks. + ******************************************************************************/ +uint32_t sli_power_manager_convert_delay_us_to_tick(uint32_t time_us); + +/******************************************************************************* + * Returns the default minimum offtime for xtal high frequency oscillator. + ******************************************************************************/ +uint32_t sli_power_manager_get_default_high_frequency_minimum_offtime(void); + +/******************************************************************************* + * Restores the Low Frequency clocks according to which LF oscillators are used. + ******************************************************************************/ +void sli_power_manager_low_frequency_restore(void); + +/***************************************************************************//** + * Informs the power manager if the high accuracy/high frequency clock + * is used, prior to scheduling an early clock restore. + * + * @return true if HFXO is used, else false. + ******************************************************************************/ +bool sli_power_manager_is_high_freq_accuracy_clk_used(void); +#endif + +/***************************************************************************//** + * Enable or disable fast wake-up in EM2 and EM3 + * + * @note Will also update the wake up time from EM2 to EM0. + ******************************************************************************/ +void sli_power_manager_em23_voltage_scaling_enable_fast_wakeup(bool enable); + +/******************************************************************************* + * Gets the delay associated the wake-up process from EM23. + * + * @return Delay for the complete wake-up process with full restore. + ******************************************************************************/ +uint32_t sli_power_manager_get_wakeup_process_time_overhead(void); + +#if !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT) +/******************************************************************************* + * Gets the status of power manager variable is_sleeping_waiting_for_clock_restore. + * + * @return true if Power Manager is sleeping waiting for clock restore, else false. + * + * @note FOR INTERNAL USE ONLY. + ******************************************************************************/ +bool sli_power_manager_get_clock_restore_status(void); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h index d45f2ae..78c2307 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sl_sleeptimer.h @@ -1,1131 +1,1131 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER API definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -/***************************************************************************//** - * @addtogroup sleeptimer Sleep Timer - * @{ - ******************************************************************************/ - -#ifndef SL_SLEEPTIMER_H -#define SL_SLEEPTIMER_H - -#include -#include -#include -#include "sl_status.h" -#include "sl_common.h" - -/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN -#define SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG (0x01) -#define SL_SLEEPTIMER_ANY_FLAG (0xFF) - -#define SLEEPTIMER_ENUM(name) typedef uint8_t name; enum name##_enum - -/// @endcond - -/// Timestamp, wall clock time in seconds. -typedef uint32_t sl_sleeptimer_timestamp_t; - -// Timestamp, 64 bits wall clock in seconds. -typedef uint64_t sl_sleeptimer_timestamp_64_t; ///< sl sleeptimer timestamp 64 t - -/// Time zone offset from UTC(second). -typedef int32_t sl_sleeptimer_time_zone_offset_t; - -// Forward declaration -typedef struct sl_sleeptimer_timer_handle sl_sleeptimer_timer_handle_t; - -/***************************************************************************//** - * Typedef for the user supplied callback function which is called when - * a timer expires. - * - * @param handle The timer handle. - * - * @param data An extra parameter for the user application. - ******************************************************************************/ -typedef void (*sl_sleeptimer_timer_callback_t)(sl_sleeptimer_timer_handle_t *handle, void *data); - -/// @brief Timer structure for sleeptimer -struct sl_sleeptimer_timer_handle { - void *callback_data; ///< User data to pass to callback function. - uint8_t priority; ///< Priority of timer. - uint16_t option_flags; ///< Option flags. - sl_sleeptimer_timer_handle_t *next; ///< Pointer to next element in list. - sl_sleeptimer_timer_callback_t callback; ///< Function to call when timer expires. - uint32_t timeout_periodic; ///< Periodic timeout. - uint32_t delta; ///< Delay relative to previous element in list. - uint32_t timeout_expected_tc; ///< Expected tick count of the next timeout (only used for periodic timer). - uint16_t conversion_error; ///< The error when converting ms to ticks (thousandths of ticks) - uint16_t accumulated_error; ///< Accumulated conversion error (thousandths of ticks) -}; - -/// @brief Month enum. -SLEEPTIMER_ENUM(sl_sleeptimer_month_t) { - MONTH_JANUARY = 0, - MONTH_FEBRUARY = 1, - MONTH_MARCH = 2, - MONTH_APRIL = 3, - MONTH_MAY = 4, - MONTH_JUNE = 5, - MONTH_JULY = 6, - MONTH_AUGUST = 7, - MONTH_SEPTEMBER = 8, - MONTH_OCTOBER = 9, - MONTH_NOVEMBER = 10, - MONTH_DECEMBER = 11, -}; - -/// @brief Week Day enum. -SLEEPTIMER_ENUM(sl_sleeptimer_weekDay_t) { - DAY_SUNDAY = 0, - DAY_MONDAY = 1, - DAY_TUESDAY = 2, - DAY_WEDNESDAY = 3, - DAY_THURSDAY = 4, - DAY_FRIDAY = 5, - DAY_SATURDAY = 6, -}; - -/// @brief Time and Date structure. -typedef struct time_date { - uint8_t sec; ///< Second (0-59) - uint8_t min; ///< Minute of month (0-59) - uint8_t hour; ///< Hour (0-23) - uint8_t month_day; ///< Day of month (1-31) - sl_sleeptimer_month_t month; ///< Month (0-11) - uint16_t year; ///< Year, based on a 1900 Epoch. - sl_sleeptimer_weekDay_t day_of_week; ///< Day of week (0-6) - uint16_t day_of_year; ///< Day of year (1-366) - sl_sleeptimer_time_zone_offset_t time_zone; ///< Offset, in seconds, from UTC -} sl_sleeptimer_date_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * Initializes the Sleeptimer. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_init(void); - -/***************************************************************************//** - * Starts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Starts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer periodic timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer periodic timeout, in timer ticks. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Stops a timer. - * - * @param handle Pointer to handle to timer. - * - * @return - ******************************************************************************/ -sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); - -/***************************************************************************//** - * Gets the status of a timer. - * - * @param handle Pointer to handle to timer. - * @param running Pointer to the status of the timer. - * - * @note A non periodic timer is considered not running during its callback. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, - bool *running); - -/***************************************************************************//** - * Gets remaining time until timer expires. - * - * @param handle Pointer to handle to timer. - * @param time Time left in timer ticks. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, - uint32_t *time); - -/**************************************************************************//** - * Gets the time remaining until the first timer with the matching set of flags - * expires. - * - * @param option_flags Set of flags to match: - * - SL_SLEEPTIMER_ANY_TIMER_FLAG - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * - * @param time_remaining Time left in timer ticks. - * - * @return 0 if successful. Error code otherwise. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, - uint32_t *time_remaining); - -/***************************************************************************//** - * Gets current 32 bits global tick count. - * - * @return Current tick count. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_tick_count(void); - -/***************************************************************************//** - * Gets current 64 bits global tick count. - * - * @return Current tick count. - ******************************************************************************/ -uint64_t sl_sleeptimer_get_tick_count64(void); - -/***************************************************************************//** - * Get timer frequency. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_timer_frequency(void); - -/***************************************************************************//** - * Converts a Unix timestamp into a date. - * - * @param time 32 bit Unix timestamp to convert. - * @param time_zone Offset from UTC in second. - * @param date Pointer to converted date. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Converts a 64 bit Unix timestamp into a date. - * - * @param time 64 bit Unix timestamp to convert. - * @param time_zone Offset from UTC in second. - * @param date Pointer to converted date. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Converts a date into a Unix timestamp. - * - * @param date Pointer to date to convert. - * @param time Pointer to converted 32 bit Unix timestamp. - * - * @return 0 if successful. Error code otherwise. - * - * @note Dates are based on the Unix time representation. - * Range of dates supported : - * - January 1, 1970, 00:00:00 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Converts a date into a 64 bit timestamp. - * - * @param date Pointer to date to convert. - * @param time Pointer to converted 64 bit Unix timestamp. - * - * @return 0 if successful. Error code otherwise. - * - * @note Dates are based on the 64 bit Unix time representation. - * Range of dates supported : - * - January 1, 1900, 00:00:00 to December 31, 11899 23:59:59. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_64_t *time); - -/***************************************************************************//** - * Convert date to string. - * - * @param str Output string. - * @param size Size of the input array. - * @param format The format specification character. - * @param date Pointer to date structure. - * - * @return 0 if error. Number of character in the output string. - * - * @note Refer strftime() from UNIX. - * http://man7.org/linux/man-pages/man3/strftime.3.html - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - ******************************************************************************/ -uint32_t sl_sleeptimer_convert_date_to_str(char *str, - size_t size, - const uint8_t *format, - sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Sets time zone offset. - * - * @param offset Time zone offset, in seconds. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - ******************************************************************************/ -void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset); - -/***************************************************************************//** - * Gets time zone offset. - * - * @return Time zone offset, in seconds. - ******************************************************************************/ -sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void); - -/***************************************************************************//** - * Retrieves current 32 bit time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return Current timestamps in Unix format. - ******************************************************************************/ -sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); - -/***************************************************************************//** - * Retrieves current 64 bit time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return Current timestamps in Unix format. - ******************************************************************************/ -sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void); - -/***************************************************************************//** - * Sets current time. - * - * @param time timestamp structure to set. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); - -/***************************************************************************//** - * Sets current time. - * - * @param time timestamp structure to set. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time); - -/***************************************************************************//** - * Gets current date. - * - * @param date Pointer to a sl_sleeptimer_date_t structure. - * - * @note Time is in Standard Time. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Sets current time, in date format. - * - * @param date Pointer to current date. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters, - * where the maximum supported date is 10:14:07 PM 01/18/2038. - * - * @param date Pointer to the structure to be populated. - * @param year Current year. May be provided based on a 0 Epoch or a 1900 Epoch. - * @param month Months since January. Expected value: 0-11. - * @param month_day Day of the month. Expected value: 1-31. - * @param hour Hours since midnight. Expected value: 0-23. - * @param min Minutes after the hour. Expected value: 0-59. - * @param sec Seconds after the minute. Expected value: 0-59. - * @param tzOffset Offset, in seconds, from UTC. - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tzOffset); - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters, - * where the maximum supported date is 11:59:59 PM 12/31/11899. - * - * @param date Pointer to the structure to be populated. - * @param year Current year based on 0 Epoch. - * @param month Months since January. Expected value: 0-11. - * @param month_day Day of the month. Expected value: 1-31. - * @param hour Hours since midnight. Expected value: 0-23. - * @param min Minutes after the hour. Expected value: 0-59. - * @param sec Seconds after the minute. Expected value: 0-59. - * @param tzOffset Offset, in seconds, from UTC. - * - * @note Resulting date structure's year will be based on 1900 epoch - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tzOffset); - -/***************************************************************************//** - * Converts Unix timestamp into NTP timestamp. - * - * @param time Unix timestamp. - * @param ntp_time Pointer to NTP Timestamp. - * - * @note Unix timestamp range supported : 0x0 to 0x7C55 817F - * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, - uint32_t *ntp_time); - -/***************************************************************************//** - * Converts NTP timestamp into Unix timestamp. - * - * @param ntp_time NTP Timestamp. - * @param time Pointer to Unix timestamp. - * - * @note NTP timestamp range supported : 0x83AA 7E80 to 0xFFFF FFFF - * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Converts Unix timestamp into Zigbee timestamp. - * - * @param time Unix timestamp. - * - * @param zigbee_time Pointer to NTP Timestamp. - * - * @note Unix timestamp range supported : 0x386D 4380 to 0x7FFF FFFF - * ie. January 1, 2000, 00:00:0 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, - uint32_t *zigbee_time); - -/***************************************************************************//** - * Converts Zigbee timestamp into Unix timestamp. - * - * @param zigbee_time NTP Timestamp. - * @param time Pointer to Unix timestamp. - * - * @note ZIGBEE timestamp range supported : 0x0 to 0x4792 BC7F - * ie. January 1, 2000, 00:00:00 to January 19, 2038, 03:14:00 - * - * @note Function definition is accessible only when - * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, - sl_sleeptimer_timestamp_t *time); - -/***************************************************************************//** - * Calculates offset for time zone after UTC-0. - * - * @param hours Number of hours from UTC-0. - * @param minutes Number of minutes from UTC-0. - * - * @return The time zone offset in seconds. - ******************************************************************************/ -__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_ahead_utc(uint8_t hours, - uint8_t minutes) -{ - return ((hours * 3600u) + (minutes * 60u)); -} - -/***************************************************************************//** - * Calculates offset for time zone before UTC-0. - * - * @param hours Number of hours to UTC-0. - * @param minutes Number of minutes to UTC-0. - * - * @return The time zone offset in seconds. - ******************************************************************************/ -__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_behind_utc(uint8_t hours, - uint8_t minutes) -{ - return -(sl_sleeptimer_time_zone_offset_t)((hours * 3600u) + (minutes * 60u)); -} - -/***************************************************************************//** - * Active delay. - * - * @param time_ms Delay duration in milliseconds. - ******************************************************************************/ -void sl_sleeptimer_delay_millisecond(uint16_t time_ms); - -/***************************************************************************//** - * Converts milliseconds in ticks. - * - * @param time_ms Number of milliseconds. - * - * @return Corresponding ticks number. - * - * @note The result is "rounded" to the superior tick number. - * This function is light and cannot fail so it should be privilegied to - * perform a millisecond to tick conversion. - ******************************************************************************/ -uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms); - -/***************************************************************************//** - * Converts 32-bits milliseconds in ticks. - * - * @param time_ms Number of milliseconds. - * @param tick Pointer to the converted tick number. - * - * @return 0 if successful. Error code otherwise. - * - * @note The result is "rounded" to the superior tick number. - * If possible the sl_sleeptimer_ms_to_tick() function should be used. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'time_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'time_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, - uint32_t *tick); - -/***************************************************************************//** - * Gets the maximum value that can be passed to the functions that have a - * 32-bits time or timeout argument expressed in milliseconds. - * - * @return Maximum time or timeout value in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_max_ms32_conversion(void); - -/***************************************************************************//** - * Converts ticks in milliseconds. - * - * @param tick Number of tick. - * - * @return Corresponding milliseconds number. - * - * @note The result is rounded to the inferior millisecond. - ******************************************************************************/ -uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick); - -/***************************************************************************//** - * Converts 64-bit ticks in milliseconds. - * - * @param tick Number of tick. - * @param ms Pointer to the converted milliseconds number. - * - * @return 0 if successful. Error code otherwise. - * - * @note The result is rounded to the inferior millisecond. - ******************************************************************************/ -sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, - uint64_t *ms); - -/***************************************************************************//** - * Allow sleep after ISR exit. - * - * @return true if sleep is allowed after ISR exit. False otherwise. - ******************************************************************************/ -bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); - -/**************************************************************************//** - * Starts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - *****************************************************************************/ -__STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - return sl_sleeptimer_start_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - *****************************************************************************/ -__STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - return sl_sleeptimer_restart_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); -} - -/***************************************************************************//** - * Starts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer periodic timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * Restarts a 32 bits periodic timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_ms Timer periodic timeout, in milliseconds. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * @param option_flags Bit array of option flags for the timer. - * Valid bit-wise OR of one or more of the following: - * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG - * or 0 for not flags. - * - * @return 0 if successful. Error code otherwise. - * - * @note This function converts the delay expressed in milliseconds to timer - * ticks (represented on 32 bits). This means that the value that can - * be passed to the argument 'timeout_ms' is limited. The maximum - * timeout value that can be passed to this function can be retrieved - * by calling sl_sleeptimer_get_max_ms32_conversion(). - * If the value passed to 'timeout_ms' is too large, - * SL_STATUS_INVALID_PARAMETER will be returned. - ******************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -/***************************************************************************//** - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - ******************************************************************************/ -uint16_t sl_sleeptimer_get_clock_accuracy(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup sleeptimer) */ - -/* *INDENT-OFF* */ -/* THE REST OF THE FILE IS DOCUMENTATION ONLY! */ -/// @addtogroup sleeptimer Sleep Timer -/// @{ -/// -/// @details -/// Sleep Timer can be used for creating timers which are tightly integrated with power management. -/// The Power Manager requires precision timing to have all clocks ready on time, so that wakeup -/// happens a little bit earlier to prepare the system to be ready at the right time. -/// Sleep Timer uses one Hardware Timer and creates multiple software timer instances. It is important -/// to note that when sleeptimer is used with WTIMER/TIMER, the MCU cannot go to EM2 energy mode -/// because WTIMER/TIMER uses a high frequency clock source which is not retained in low energy mode. -/// -/// The sleeptimer.c and sleeptimer.h source files for the SLEEPTIMER device driver library are in the -/// service/sleeptimer folder. -/// -/// @n @section sleeptimer_intro Introduction -/// -/// The Sleeptimer driver provides software timers, delays, timekeeping and date functionalities using a low-frequency real-time clock peripheral. -/// -/// All Silicon Labs microcontrollers equipped with the RTC or RTCC peripheral are currently supported. Only one instance of this driver can be initialized by the application. -/// -/// @n @section sleeptimer_functionalities_overview Functionalities overview -/// -/// @n @subsection software_timers Software Timers -/// -/// This functionality allows the user to create periodic and one shot timers. A user callback can be associated with a timer and is called when the timer expires. -/// -/// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. -/// -/// @n @subsection timekeeping Timekeeping -/// -/// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver -/// -/// The `SL_SLEEPTIMER_WALLCLOCK_CONFIG` configuration enables a UNIX timestamp (seconds count since January 1, 1970, 00:00:00). -/// -/// This timestamp can be retrieved/modified using the following API: -/// -/// @li sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); -/// @li sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); -/// -/// Convenience conversion functions are provided to convert UNIX timestamp to/from NTP and Zigbee cluster format : -/// -/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, uint32_t *ntp_time); -/// @li sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, sl_sleeptimer_timestamp_t *time); -/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, uint32_t *zigbee_time); -/// @li sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, sl_sleeptimer_timestamp_t *time); -/// -/// @n @subsection date Date -/// -/// The previously described internal timestamp can also be retrieved/modified in a date format sl_sleeptimer_date_t. -/// -/// @n API : @n -/// -/// @li sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); -/// @li sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); -/// -/// @n @subsection frequency_setup Frequency Setup and Tick Count -/// -/// This driver works with a configurable time unit called tick. -/// -/// The frequency of the ticks is based on the clock source and the internal frequency divider. -/// -/// WTIMER/TIMER peripherals uses high frequency oscillator. To have a reasonable tick frequency, divider is set to maximum value (1024). -/// -/// One of the following clock sources must be enabled before initializing the sleeptimer: -/// -/// @li LFXO: external crystal oscillator. Typically running at 32.768 kHz. -/// @li LFRCO: internal oscillator running at 32.768 kHz -/// @li ULFRCO: Ultra low-frequency oscillator running at 1.000 kHz -/// @li HFXO: High Frequency Crystal Oscillator at 39 Mhz. HFXO is only needed when Sleeptimer runs on TIMER or WTIMER. -/// -/// The frequency divider is selected with the `SL_SLEEPTIMER_FREQ_DIVIDER` configuration. Its value must be a power of two within the range of 1 to 32. The number of ticks per second (sleeptimer frequency) is dictated by the following formula: -/// -/// Tick (seconds) = 1 / (clock_frequency / frequency_divider) -/// -/// The highest resolution for a tick is 30.5 us. It is achieved with a 32.768 kHz clock and a divider of 1. -/// -/// @n @section sleeptimer_getting_started Getting Started -/// -/// @n @subsection clock_selection Clock Selection -/// -/// The sleeptimer relies on the hardware timer to operate. The hardware timer peripheral must be properly clocked from the application. Selecting the appropriate timer is crucial for design considerations. Each timer can potentially be used as a sleeptimer and is also available to the user. However, note that if a timer is used by the sleeptimer, it can't be used by the application and vice versa. -/// -/// For WTIMER/TIMER peripherals, the user must select the appropriate oscillator if it is not the default wanted clock source. -/// -/// When WTIMER/TIMER is selected, sleeptimer uses channel 0 and it is not possible to use other channels of the same instance for other purposes. -/// -/// @n @subsection Clock Selection in a Project without Micrium OS -/// -/// When RTC, RTCC, or BURTC is selected, the clock source for the peripheral must be configured and enabled in the application before initializing the sleeptimer module or any communication stacks. Most of the time, it consists in enabling the desired oscillators and setting up the clock source for the peripheral, like in the following example: -/// -/// @code{.c} -/// CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); -/// CMU_ClockEnable(cmuClock_RTCC, true); -/// @endcode -/// -/// @n @subsection clock_branch_select Clock Branch Select -/// -/// | Clock | Enum | Description | Frequency | -/// |--------|-------------------------|-----------------------------------|-----------| -/// | LFXO | cmuSelect_LFXO | Low-frequency crystal oscillator |32.768 Khz | -/// | LFRCO | cmuSelect_LFRCO | Low-frequency RC oscillator |32.768 Khz | -/// | ULFRCO | cmuSelect_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | -/// -/// @n @subsection timer_clock_enable Timer Clock Enable -/// -/// | Module | Enum | Description | -/// |--------------------|-----------------------|----------------------------------------------------| -/// | RTCC | cmuClock_RTCC | Real-time counter and calendar clock (LF E branch) | -/// | RTC | cmuClock_RTC | Real time counter clock (LF A branch) | -/// | BURTC | cmuClock_BURTC | BURTC clock (EM4 Group A branch) | -/// -/// When the Radio internal RTC (PRORTC) is selected, it is not necessary to configure the clock source for the peripheral. However, it is important to enable the desired oscillator before initializing the sleeptimer module or any communication stacks. The best oscillator available (LFXO being the first choice) will be used by the sleeptimer at initalization. The following example shows how the desired oscilator should be enabled: -/// -/// @code{.c} -/// CMU_OscillatorEnable(cmuSelect_LFXO, true, true); -/// @endcode -/// -/// @n @subsection clock_micrium_os Clock Selection in a Project with Micrium OS -/// -/// When Micrium OS is used, a BSP (all instances) is provided that sets up some parts of the clock tree. The sleeptimer clock source will be enabled by this bsp. However, the desired oscillator remains configurable from the file bsp_cfg.h. -/// -/// The configuration `BSP_LF_CLK_SEL` determines which oscillator will be used by the sleeptimer's hardware timer peripheral. It can take the following values: -/// -/// | Config | Description | Frequency | -/// |--------------------------|-----------------------------------|-----------| -/// | BSP_LF_CLK_LFXO | Low-frequency crystal oscillator |32.768 Khz | -/// | BSP_LF_CLK_LFRCO | Low-frequency RC oscillator |32.768 Khz | -/// | BSP_LF_CLK_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | -/// -/// @n @section sleeptimer_conf Configuration Options -/// -/// `SL_SLEEPTIMER_PERIPHERAL` can be set to one of the following values: -/// -/// | Config | Description | -/// | --------------------------------- |------------------------------------------------------------------------------------------------------| -/// | `SL_SLEEPTIMER_PERIPHERAL_DEFAULT`| Selects either RTC or RTCC, depending of what is available on the platform. | -/// | `SL_SLEEPTIMER_PERIPHERAL_RTCC` | Selects RTCC | -/// | `SL_SLEEPTIMER_PERIPHERAL_RTC` | Selects RTC | -/// | `SL_SLEEPTIMER_PERIPHERAL_PRORTC` | Selects Internal radio RTC. Available only on EFR32XG13, EFR32XG14, EFR32XG21 and EFR32XG22 families.| -/// | `SL_SLEEPTIMER_PERIPHERAL_BURTC` | Selects BURTC. Not available on Series 0 devices. | -/// -/// `SL_SLEEPTIMER_WALLCLOCK_CONFIG` must be set to 1 to enable timestamp and date functionnalities. -/// -/// `SL_SLEEPTIMER_FREQ_DIVIDER` must be a power of 2 within the range 1 to 32. When `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`, `SL_SLEEPTIMER_FREQ_DIVIDER` must be set to 1. -/// -/// `SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER` is only meaningful when `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`. Set to 1 if no communication stack is used in your project. Otherwise, must be set to 0. -/// -/// @n @section sleeptimer_api The API -/// -/// This section contains brief descriptions of the API functions. For -/// more information about input and output parameters and return values, -/// click on the hyperlinked function names. Most functions return an error -/// code, `SL_STATUS_OK` is returned on success, -/// see sl_status.h for other error codes. -/// -/// The application code must include the @em sl_sleeptimer.h header file. -/// -/// All API functions can be called from within interrupt handlers. -/// -/// @ref sl_sleeptimer_init() @n -/// These functions initialize the sleeptimer driver. Typically, -/// sl_sleeptimer_init() is called once in the startup code. -/// -/// @ref sl_sleeptimer_start_timer() @n -/// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_restart_timer() @n -/// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_start_periodic_timer() @n -/// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_restart_periodic_timer() @n -/// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function -/// is called. A pointer to this function is passed to -/// sl_sleeptimer_start_timer(). See @ref callback for -/// details of the callback prototype. -/// -/// @ref sl_sleeptimer_stop_timer() @n -/// Stop a timer. -/// -/// @ref sl_sleeptimer_get_timer_time_remaining() @n -/// Get the time remaining before the timer expires. -/// -/// @ref sl_sleeptimer_delay_millisecond() @n -/// Delay for the given number of milliseconds. This is an "active wait" delay function. -/// -/// @ref sl_sleeptimer_is_timer_running() @n -/// Check if a timer is running. -/// -/// @ref sl_sleeptimer_get_time(), @ref sl_sleeptimer_set_time() @n -/// Get or set wallclock time. -/// -/// @ref sl_sleeptimer_ms_to_tick(), @ref sl_sleeptimer_ms32_to_tick(), -/// @ref sl_sleeptimer_tick_to_ms(), @ref sl_sleeptimer_tick64_to_ms() @n -/// Convert between milliseconds and RTC/RTCC -/// counter ticks. -/// -/// @n @anchor callback The timer expiry callback function: @n -/// The callback function, prototyped as @ref sl_sleeptimer_timer_callback_t(), is called from -/// within the RTC peripheral interrupt handler on timer expiration. -/// sl_sleeptimer_timer_callback_t(sl_sleeptimer_timer_handle_t *handle, void *data) -/// -/// @n @section sleeptimer_example Example -/// @code{.c} -///#include "sl_sleeptimer.h" -/// -///void my_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data) -///{ -/// //Code executed when the timer expire. -///} -/// -///int start_timer(void) -///{ -/// sl_status_t status; -/// sl_sleeptimer_timer_handle_t my_timer; -/// uint32_t timer_timeout = 300; -/// -/// // We assume the sleeptimer is initialized properly -/// -/// status = sl_sleeptimer_start_timer(&my_timer, -/// timer_timeout, -/// my_timer_callback, -/// (void *)NULL, -/// 0, -/// 0); -/// if(status != SL_STATUS_OK) { -/// return -1; -/// } -/// return 1; -///} -/// @endcode -/// -/// @} (end addtogroup sleeptimer) - -#endif // SL_SLEEPTIMER_H +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sleeptimer Sleep Timer + * @{ + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_H +#define SL_SLEEPTIMER_H + +#include +#include +#include +#include "sl_status.h" +#include "sl_common.h" + +/// @cond DO_NOT_INCLUDE_WITH_DOXYGEN +#define SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG (0x01) +#define SL_SLEEPTIMER_ANY_FLAG (0xFF) + +#define SLEEPTIMER_ENUM(name) typedef uint8_t name; enum name##_enum + +/// @endcond + +/// Timestamp, wall clock time in seconds. +typedef uint32_t sl_sleeptimer_timestamp_t; + +// Timestamp, 64 bits wall clock in seconds. +typedef uint64_t sl_sleeptimer_timestamp_64_t; ///< sl sleeptimer timestamp 64 t + +/// Time zone offset from UTC(second). +typedef int32_t sl_sleeptimer_time_zone_offset_t; + +// Forward declaration +typedef struct sl_sleeptimer_timer_handle sl_sleeptimer_timer_handle_t; + +/***************************************************************************//** + * Typedef for the user supplied callback function which is called when + * a timer expires. + * + * @param handle The timer handle. + * + * @param data An extra parameter for the user application. + ******************************************************************************/ +typedef void (*sl_sleeptimer_timer_callback_t)(sl_sleeptimer_timer_handle_t *handle, void *data); + +/// @brief Timer structure for sleeptimer +struct sl_sleeptimer_timer_handle { + void *callback_data; ///< User data to pass to callback function. + uint8_t priority; ///< Priority of timer. + uint16_t option_flags; ///< Option flags. + sl_sleeptimer_timer_handle_t *next; ///< Pointer to next element in list. + sl_sleeptimer_timer_callback_t callback; ///< Function to call when timer expires. + uint32_t timeout_periodic; ///< Periodic timeout. + uint32_t delta; ///< Delay relative to previous element in list. + uint32_t timeout_expected_tc; ///< Expected tick count of the next timeout (only used for periodic timer). + uint16_t conversion_error; ///< The error when converting ms to ticks (thousandths of ticks) + uint16_t accumulated_error; ///< Accumulated conversion error (thousandths of ticks) +}; + +/// @brief Month enum. +SLEEPTIMER_ENUM(sl_sleeptimer_month_t) { + MONTH_JANUARY = 0, + MONTH_FEBRUARY = 1, + MONTH_MARCH = 2, + MONTH_APRIL = 3, + MONTH_MAY = 4, + MONTH_JUNE = 5, + MONTH_JULY = 6, + MONTH_AUGUST = 7, + MONTH_SEPTEMBER = 8, + MONTH_OCTOBER = 9, + MONTH_NOVEMBER = 10, + MONTH_DECEMBER = 11, +}; + +/// @brief Week Day enum. +SLEEPTIMER_ENUM(sl_sleeptimer_weekDay_t) { + DAY_SUNDAY = 0, + DAY_MONDAY = 1, + DAY_TUESDAY = 2, + DAY_WEDNESDAY = 3, + DAY_THURSDAY = 4, + DAY_FRIDAY = 5, + DAY_SATURDAY = 6, +}; + +/// @brief Time and Date structure. +typedef struct time_date { + uint8_t sec; ///< Second (0-59) + uint8_t min; ///< Minute of month (0-59) + uint8_t hour; ///< Hour (0-23) + uint8_t month_day; ///< Day of month (1-31) + sl_sleeptimer_month_t month; ///< Month (0-11) + uint16_t year; ///< Year, based on a 1900 Epoch. + sl_sleeptimer_weekDay_t day_of_week; ///< Day of week (0-6) + uint16_t day_of_year; ///< Day of year (1-366) + sl_sleeptimer_time_zone_offset_t time_zone; ///< Offset, in seconds, from UTC +} sl_sleeptimer_date_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * Initializes the Sleeptimer. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_init(void); + +/***************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer periodic timeout, in timer ticks. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Stops a timer. + * + * @param handle Pointer to handle to timer. + * + * @return + ******************************************************************************/ +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle); + +/***************************************************************************//** + * Gets the status of a timer. + * + * @param handle Pointer to handle to timer. + * @param running Pointer to the status of the timer. + * + * @note A non periodic timer is considered not running during its callback. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, + bool *running); + +/***************************************************************************//** + * Gets remaining time until timer expires. + * + * @param handle Pointer to handle to timer. + * @param time Time left in timer ticks. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, + uint32_t *time); + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + * + * @param option_flags Set of flags to match: + * - SL_SLEEPTIMER_ANY_TIMER_FLAG + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * + * @param time_remaining Time left in timer ticks. + * + * @return 0 if successful. Error code otherwise. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining); + +/***************************************************************************//** + * Gets current 32 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_tick_count(void); + +/***************************************************************************//** + * Gets current 64 bits global tick count. + * + * @return Current tick count. + ******************************************************************************/ +uint64_t sl_sleeptimer_get_tick_count64(void); + +/***************************************************************************//** + * Get timer frequency. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_timer_frequency(void); + +/***************************************************************************//** + * Converts a Unix timestamp into a date. + * + * @param time 32 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a 64 bit Unix timestamp into a date. + * + * @param time 64 bit Unix timestamp to convert. + * @param time_zone Offset from UTC in second. + * @param date Pointer to converted date. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Converts a date into a Unix timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 32 bit Unix timestamp. + * + * @return 0 if successful. Error code otherwise. + * + * @note Dates are based on the Unix time representation. + * Range of dates supported : + * - January 1, 1970, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts a date into a 64 bit timestamp. + * + * @param date Pointer to date to convert. + * @param time Pointer to converted 64 bit Unix timestamp. + * + * @return 0 if successful. Error code otherwise. + * + * @note Dates are based on the 64 bit Unix time representation. + * Range of dates supported : + * - January 1, 1900, 00:00:00 to December 31, 11899 23:59:59. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time); + +/***************************************************************************//** + * Convert date to string. + * + * @param str Output string. + * @param size Size of the input array. + * @param format The format specification character. + * @param date Pointer to date structure. + * + * @return 0 if error. Number of character in the output string. + * + * @note Refer strftime() from UNIX. + * http://man7.org/linux/man-pages/man3/strftime.3.html + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset); + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void); + +/***************************************************************************//** + * Retrieves current 32 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); + +/***************************************************************************//** + * Retrieves current 64 bit time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return Current timestamps in Unix format. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); + +/***************************************************************************//** + * Sets current time. + * + * @param time timestamp structure to set. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time); + +/***************************************************************************//** + * Gets current date. + * + * @param date Pointer to a sl_sleeptimer_date_t structure. + * + * @note Time is in Standard Time. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Sets current time, in date format. + * + * @param date Pointer to current date. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 10:14:07 PM 01/18/2038. + * + * @param date Pointer to the structure to be populated. + * @param year Current year. May be provided based on a 0 Epoch or a 1900 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters, + * where the maximum supported date is 11:59:59 PM 12/31/11899. + * + * @param date Pointer to the structure to be populated. + * @param year Current year based on 0 Epoch. + * @param month Months since January. Expected value: 0-11. + * @param month_day Day of the month. Expected value: 1-31. + * @param hour Hours since midnight. Expected value: 0-23. + * @param min Minutes after the hour. Expected value: 0-59. + * @param sec Seconds after the minute. Expected value: 0-59. + * @param tzOffset Offset, in seconds, from UTC. + * + * @note Resulting date structure's year will be based on 1900 epoch + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tzOffset); + +/***************************************************************************//** + * Converts Unix timestamp into NTP timestamp. + * + * @param time Unix timestamp. + * @param ntp_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x0 to 0x7C55 817F + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time); + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + * + * @param ntp_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note NTP timestamp range supported : 0x83AA 7E80 to 0xFFFF FFFF + * ie. January 1, 1970, 00:00:00 to February 07, 2036, 06:28:15 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + * + * @param time Unix timestamp. + * + * @param zigbee_time Pointer to NTP Timestamp. + * + * @note Unix timestamp range supported : 0x386D 4380 to 0x7FFF FFFF + * ie. January 1, 2000, 00:00:0 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time); + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + * + * @param zigbee_time NTP Timestamp. + * @param time Pointer to Unix timestamp. + * + * @note ZIGBEE timestamp range supported : 0x0 to 0x4792 BC7F + * ie. January 1, 2000, 00:00:00 to January 19, 2038, 03:14:00 + * + * @note Function definition is accessible only when + * SL_SLEEPTIMER_WALLCLOCK_CONFIG is set to 1. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time); + +/***************************************************************************//** + * Calculates offset for time zone after UTC-0. + * + * @param hours Number of hours from UTC-0. + * @param minutes Number of minutes from UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_ahead_utc(uint8_t hours, + uint8_t minutes) +{ + return ((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Calculates offset for time zone before UTC-0. + * + * @param hours Number of hours to UTC-0. + * @param minutes Number of minutes to UTC-0. + * + * @return The time zone offset in seconds. + ******************************************************************************/ +__STATIC_INLINE sl_sleeptimer_time_zone_offset_t sl_sleeptimer_set_tz_behind_utc(uint8_t hours, + uint8_t minutes) +{ + return -(sl_sleeptimer_time_zone_offset_t)((hours * 3600u) + (minutes * 60u)); +} + +/***************************************************************************//** + * Active delay. + * + * @param time_ms Delay duration in milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms); + +/***************************************************************************//** + * Converts milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * + * @return Corresponding ticks number. + * + * @note The result is "rounded" to the superior tick number. + * This function is light and cannot fail so it should be privilegied to + * perform a millisecond to tick conversion. + ******************************************************************************/ +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms); + +/***************************************************************************//** + * Converts 32-bits milliseconds in ticks. + * + * @param time_ms Number of milliseconds. + * @param tick Pointer to the converted tick number. + * + * @return 0 if successful. Error code otherwise. + * + * @note The result is "rounded" to the superior tick number. + * If possible the sl_sleeptimer_ms_to_tick() function should be used. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'time_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'time_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick); + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + * + * @return Maximum time or timeout value in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void); + +/***************************************************************************//** + * Converts ticks in milliseconds. + * + * @param tick Number of tick. + * + * @return Corresponding milliseconds number. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick); + +/***************************************************************************//** + * Converts 64-bit ticks in milliseconds. + * + * @param tick Number of tick. + * @param ms Pointer to the converted milliseconds number. + * + * @return 0 if successful. Error code otherwise. + * + * @note The result is rounded to the inferior millisecond. + ******************************************************************************/ +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms); + +/***************************************************************************//** + * Allow sleep after ISR exit. + * + * @return true if sleep is allowed after ISR exit. False otherwise. + ******************************************************************************/ +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void); + +/**************************************************************************//** + * Starts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sl_sleeptimer_start_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_start_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + *****************************************************************************/ +__STATIC_INLINE sl_status_t sl_sleeptimer_restart_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + return sl_sleeptimer_restart_timer(handle, timeout_tick, callback, callback_data, priority, option_flags); +} + +/***************************************************************************//** + * Starts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * Restarts a 32 bits periodic timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_ms Timer periodic timeout, in milliseconds. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * @param option_flags Bit array of option flags for the timer. + * Valid bit-wise OR of one or more of the following: + * - SL_SLEEPTIMER_NO_HIGH_PRECISION_HF_CLOCKS_REQUIRED_FLAG + * or 0 for not flags. + * + * @return 0 if successful. Error code otherwise. + * + * @note This function converts the delay expressed in milliseconds to timer + * ticks (represented on 32 bits). This means that the value that can + * be passed to the argument 'timeout_ms' is limited. The maximum + * timeout value that can be passed to this function can be retrieved + * by calling sl_sleeptimer_get_max_ms32_conversion(). + * If the value passed to 'timeout_ms' is too large, + * SL_STATUS_INVALID_PARAMETER will be returned. + ******************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +/***************************************************************************//** + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup sleeptimer) */ + +/* *INDENT-OFF* */ +/* THE REST OF THE FILE IS DOCUMENTATION ONLY! */ +/// @addtogroup sleeptimer Sleep Timer +/// @{ +/// +/// @details +/// Sleep Timer can be used for creating timers which are tightly integrated with power management. +/// The Power Manager requires precision timing to have all clocks ready on time, so that wakeup +/// happens a little bit earlier to prepare the system to be ready at the right time. +/// Sleep Timer uses one Hardware Timer and creates multiple software timer instances. It is important +/// to note that when sleeptimer is used with WTIMER/TIMER, the MCU cannot go to EM2 energy mode +/// because WTIMER/TIMER uses a high frequency clock source which is not retained in low energy mode. +/// +/// The sleeptimer.c and sleeptimer.h source files for the SLEEPTIMER device driver library are in the +/// service/sleeptimer folder. +/// +/// @n @section sleeptimer_intro Introduction +/// +/// The Sleeptimer driver provides software timers, delays, timekeeping and date functionalities using a low-frequency real-time clock peripheral. +/// +/// All Silicon Labs microcontrollers equipped with the RTC or RTCC peripheral are currently supported. Only one instance of this driver can be initialized by the application. +/// +/// @n @section sleeptimer_functionalities_overview Functionalities overview +/// +/// @n @subsection software_timers Software Timers +/// +/// This functionality allows the user to create periodic and one shot timers. A user callback can be associated with a timer and is called when the timer expires. +/// +/// Timer structures must be allocated by the user. The function is called from within an interrupt handler with interrupts enabled. +/// +/// @n @subsection timekeeping Timekeeping +/// +/// A 64-bits tick counter is accessible through the @li uint64_t sl_sleeptimer_get_tick_count64(void) API. It keeps the tick count since the initialization of the driver +/// +/// The `SL_SLEEPTIMER_WALLCLOCK_CONFIG` configuration enables a UNIX timestamp (seconds count since January 1, 1970, 00:00:00). +/// +/// This timestamp can be retrieved/modified using the following API: +/// +/// @li sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void); +/// @li sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time); +/// +/// Convenience conversion functions are provided to convert UNIX timestamp to/from NTP and Zigbee cluster format : +/// +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, uint32_t *ntp_time); +/// @li sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, sl_sleeptimer_timestamp_t *time); +/// @li sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, uint32_t *zigbee_time); +/// @li sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, sl_sleeptimer_timestamp_t *time); +/// +/// @n @subsection date Date +/// +/// The previously described internal timestamp can also be retrieved/modified in a date format sl_sleeptimer_date_t. +/// +/// @n API : @n +/// +/// @li sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date); +/// @li sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date); +/// +/// @n @subsection frequency_setup Frequency Setup and Tick Count +/// +/// This driver works with a configurable time unit called tick. +/// +/// The frequency of the ticks is based on the clock source and the internal frequency divider. +/// +/// WTIMER/TIMER peripherals uses high frequency oscillator. To have a reasonable tick frequency, divider is set to maximum value (1024). +/// +/// One of the following clock sources must be enabled before initializing the sleeptimer: +/// +/// @li LFXO: external crystal oscillator. Typically running at 32.768 kHz. +/// @li LFRCO: internal oscillator running at 32.768 kHz +/// @li ULFRCO: Ultra low-frequency oscillator running at 1.000 kHz +/// @li HFXO: High Frequency Crystal Oscillator at 39 Mhz. HFXO is only needed when Sleeptimer runs on TIMER or WTIMER. +/// +/// The frequency divider is selected with the `SL_SLEEPTIMER_FREQ_DIVIDER` configuration. Its value must be a power of two within the range of 1 to 32. The number of ticks per second (sleeptimer frequency) is dictated by the following formula: +/// +/// Tick (seconds) = 1 / (clock_frequency / frequency_divider) +/// +/// The highest resolution for a tick is 30.5 us. It is achieved with a 32.768 kHz clock and a divider of 1. +/// +/// @n @section sleeptimer_getting_started Getting Started +/// +/// @n @subsection clock_selection Clock Selection +/// +/// The sleeptimer relies on the hardware timer to operate. The hardware timer peripheral must be properly clocked from the application. Selecting the appropriate timer is crucial for design considerations. Each timer can potentially be used as a sleeptimer and is also available to the user. However, note that if a timer is used by the sleeptimer, it can't be used by the application and vice versa. +/// +/// For WTIMER/TIMER peripherals, the user must select the appropriate oscillator if it is not the default wanted clock source. +/// +/// When WTIMER/TIMER is selected, sleeptimer uses channel 0 and it is not possible to use other channels of the same instance for other purposes. +/// +/// @n @subsection Clock Selection in a Project without Micrium OS +/// +/// When RTC, RTCC, or BURTC is selected, the clock source for the peripheral must be configured and enabled in the application before initializing the sleeptimer module or any communication stacks. Most of the time, it consists in enabling the desired oscillators and setting up the clock source for the peripheral, like in the following example: +/// +/// @code{.c} +/// CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFRCO); +/// CMU_ClockEnable(cmuClock_RTCC, true); +/// @endcode +/// +/// @n @subsection clock_branch_select Clock Branch Select +/// +/// | Clock | Enum | Description | Frequency | +/// |--------|-------------------------|-----------------------------------|-----------| +/// | LFXO | cmuSelect_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | LFRCO | cmuSelect_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | ULFRCO | cmuSelect_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @subsection timer_clock_enable Timer Clock Enable +/// +/// | Module | Enum | Description | +/// |--------------------|-----------------------|----------------------------------------------------| +/// | RTCC | cmuClock_RTCC | Real-time counter and calendar clock (LF E branch) | +/// | RTC | cmuClock_RTC | Real time counter clock (LF A branch) | +/// | BURTC | cmuClock_BURTC | BURTC clock (EM4 Group A branch) | +/// +/// When the Radio internal RTC (PRORTC) is selected, it is not necessary to configure the clock source for the peripheral. However, it is important to enable the desired oscillator before initializing the sleeptimer module or any communication stacks. The best oscillator available (LFXO being the first choice) will be used by the sleeptimer at initalization. The following example shows how the desired oscilator should be enabled: +/// +/// @code{.c} +/// CMU_OscillatorEnable(cmuSelect_LFXO, true, true); +/// @endcode +/// +/// @n @subsection clock_micrium_os Clock Selection in a Project with Micrium OS +/// +/// When Micrium OS is used, a BSP (all instances) is provided that sets up some parts of the clock tree. The sleeptimer clock source will be enabled by this bsp. However, the desired oscillator remains configurable from the file bsp_cfg.h. +/// +/// The configuration `BSP_LF_CLK_SEL` determines which oscillator will be used by the sleeptimer's hardware timer peripheral. It can take the following values: +/// +/// | Config | Description | Frequency | +/// |--------------------------|-----------------------------------|-----------| +/// | BSP_LF_CLK_LFXO | Low-frequency crystal oscillator |32.768 Khz | +/// | BSP_LF_CLK_LFRCO | Low-frequency RC oscillator |32.768 Khz | +/// | BSP_LF_CLK_ULFRCO | Ultra low-frequency RC oscillator |1 Khz | +/// +/// @n @section sleeptimer_conf Configuration Options +/// +/// `SL_SLEEPTIMER_PERIPHERAL` can be set to one of the following values: +/// +/// | Config | Description | +/// | --------------------------------- |------------------------------------------------------------------------------------------------------| +/// | `SL_SLEEPTIMER_PERIPHERAL_DEFAULT`| Selects either RTC or RTCC, depending of what is available on the platform. | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTCC` | Selects RTCC | +/// | `SL_SLEEPTIMER_PERIPHERAL_RTC` | Selects RTC | +/// | `SL_SLEEPTIMER_PERIPHERAL_PRORTC` | Selects Internal radio RTC. Available only on EFR32XG13, EFR32XG14, EFR32XG21 and EFR32XG22 families.| +/// | `SL_SLEEPTIMER_PERIPHERAL_BURTC` | Selects BURTC. Not available on Series 0 devices. | +/// +/// `SL_SLEEPTIMER_WALLCLOCK_CONFIG` must be set to 1 to enable timestamp and date functionnalities. +/// +/// `SL_SLEEPTIMER_FREQ_DIVIDER` must be a power of 2 within the range 1 to 32. When `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`, `SL_SLEEPTIMER_FREQ_DIVIDER` must be set to 1. +/// +/// `SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER` is only meaningful when `SL_SLEEPTIMER_PERIPHERAL` is set to `SL_SLEEPTIMER_PERIPHERAL_PRORTC`. Set to 1 if no communication stack is used in your project. Otherwise, must be set to 0. +/// +/// @n @section sleeptimer_api The API +/// +/// This section contains brief descriptions of the API functions. For +/// more information about input and output parameters and return values, +/// click on the hyperlinked function names. Most functions return an error +/// code, `SL_STATUS_OK` is returned on success, +/// see sl_status.h for other error codes. +/// +/// The application code must include the @em sl_sleeptimer.h header file. +/// +/// All API functions can be called from within interrupt handlers. +/// +/// @ref sl_sleeptimer_init() @n +/// These functions initialize the sleeptimer driver. Typically, +/// sl_sleeptimer_init() is called once in the startup code. +/// +/// @ref sl_sleeptimer_start_timer() @n +/// Start a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_timer() @n +/// Restart a one shot 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_start_periodic_timer() @n +/// Start a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_restart_periodic_timer() @n +/// Restart a periodic 32 bits timer. When a timer expires, a user-supplied callback function +/// is called. A pointer to this function is passed to +/// sl_sleeptimer_start_timer(). See @ref callback for +/// details of the callback prototype. +/// +/// @ref sl_sleeptimer_stop_timer() @n +/// Stop a timer. +/// +/// @ref sl_sleeptimer_get_timer_time_remaining() @n +/// Get the time remaining before the timer expires. +/// +/// @ref sl_sleeptimer_delay_millisecond() @n +/// Delay for the given number of milliseconds. This is an "active wait" delay function. +/// +/// @ref sl_sleeptimer_is_timer_running() @n +/// Check if a timer is running. +/// +/// @ref sl_sleeptimer_get_time(), @ref sl_sleeptimer_set_time() @n +/// Get or set wallclock time. +/// +/// @ref sl_sleeptimer_ms_to_tick(), @ref sl_sleeptimer_ms32_to_tick(), +/// @ref sl_sleeptimer_tick_to_ms(), @ref sl_sleeptimer_tick64_to_ms() @n +/// Convert between milliseconds and RTC/RTCC +/// counter ticks. +/// +/// @n @anchor callback The timer expiry callback function: @n +/// The callback function, prototyped as @ref sl_sleeptimer_timer_callback_t(), is called from +/// within the RTC peripheral interrupt handler on timer expiration. +/// sl_sleeptimer_timer_callback_t(sl_sleeptimer_timer_handle_t *handle, void *data) +/// +/// @n @section sleeptimer_example Example +/// @code{.c} +///#include "sl_sleeptimer.h" +/// +///void my_timer_callback(sl_sleeptimer_timer_handle_t *handle, void *data) +///{ +/// //Code executed when the timer expire. +///} +/// +///int start_timer(void) +///{ +/// sl_status_t status; +/// sl_sleeptimer_timer_handle_t my_timer; +/// uint32_t timer_timeout = 300; +/// +/// // We assume the sleeptimer is initialized properly +/// +/// status = sl_sleeptimer_start_timer(&my_timer, +/// timer_timeout, +/// my_timer_callback, +/// (void *)NULL, +/// 0, +/// 0); +/// if(status != SL_STATUS_OK) { +/// return -1; +/// } +/// return 1; +///} +/// @endcode +/// +/// @} (end addtogroup sleeptimer) + +#endif // SL_SLEEPTIMER_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h index aaa353a..254323d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/inc/sli_sleeptimer.h @@ -1,136 +1,136 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER SDK internal APIs. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SLI_SLEEPTIMER_H -#define SLI_SLEEPTIMER_H - -#include -#include -#include -#include "em_device.h" -#include "sl_sleeptimer_config.h" - -#define SLEEPTIMER_EVENT_OF (0x01) -#define SLEEPTIMER_EVENT_COMP (0x02) - -#define SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG 0x02 -#define SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG 0x04 - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_DEFAULT -#if defined(RTCC_PRESENT) && RTCC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTCC -#elif defined(RTC_PRESENT) && RTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTC -#elif defined(SYSRTC_PRESENT) && SYSRTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_SYSRTC -#elif defined(BURTC_PRESENT) && BURTC_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_BURTC -#elif defined(WTIMER_PRESENT) && WTIMER_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_WTIMER -#elif defined(TIMER_PRESENT) && TIMER_COUNT >= 1 -#undef SL_SLEEPTIMER_PERIPHERAL -#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_TIMER -#endif -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to Power Manager. - ******************************************************************************/ -__WEAK void sli_sleeptimer_hal_power_manager_integration_init(void); - -/******************************************************************************* - * Hardware Abstraction Layer to perform initialization related to HFXO Manager. - ******************************************************************************/ -__WEAK void sli_sleeptimer_hal_hfxo_manager_integration_init(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get interrupt status. - * - * @param local_flag Internal interrupt flag. - * - * @return Boolean indicating if specified interrupt is set. - ******************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag); - -/**************************************************************************//** - * Determines if next timer to expire has the option flag - * "SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". - * - * @return true if power manager will expire at next compare match, - * false otherwise. - *****************************************************************************/ -bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void); - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void); -#endif - -/***************************************************************************//** - * @brief - * Update sleep_on_isr_exit flag. - * - * @param flag Boolean value update_sleep_on_isr_exit will be set to. - ******************************************************************************/ -void sli_sleeptimer_update_sleep_on_isr_exit(bool flag); - -/******************************************************************************* - * Gets the associated peripheral capture channel current value. - * - * @return Capture value - * 0 if capture channel is not valid - ******************************************************************************/ -uint32_t sli_sleeptimer_get_capture(void); - -/******************************************************************************* - * Resets the PRS signal triggered by the associated peripheral. - ******************************************************************************/ -void sli_sleeptimer_reset_prs_signal(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SLI_SLEEPTIMER_H */ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER SDK internal APIs. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SLI_SLEEPTIMER_H +#define SLI_SLEEPTIMER_H + +#include +#include +#include +#include "em_device.h" +#include "sl_sleeptimer_config.h" + +#define SLEEPTIMER_EVENT_OF (0x01) +#define SLEEPTIMER_EVENT_COMP (0x02) + +#define SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG 0x02 +#define SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG 0x04 + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_DEFAULT +#if defined(RTCC_PRESENT) && RTCC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTCC +#elif defined(RTC_PRESENT) && RTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_RTC +#elif defined(SYSRTC_PRESENT) && SYSRTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_SYSRTC +#elif defined(BURTC_PRESENT) && BURTC_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_BURTC +#elif defined(WTIMER_PRESENT) && WTIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_WTIMER +#elif defined(TIMER_PRESENT) && TIMER_COUNT >= 1 +#undef SL_SLEEPTIMER_PERIPHERAL +#define SL_SLEEPTIMER_PERIPHERAL SL_SLEEPTIMER_PERIPHERAL_TIMER +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to Power Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_power_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to perform initialization related to HFXO Manager. + ******************************************************************************/ +__WEAK void sli_sleeptimer_hal_hfxo_manager_integration_init(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get interrupt status. + * + * @param local_flag Internal interrupt flag. + * + * @return Boolean indicating if specified interrupt is set. + ******************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag); + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @return true if power manager will expire at next compare match, + * false otherwise. + *****************************************************************************/ +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void); + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void); +#endif + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Boolean value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag); + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + * + * @return Capture value + * 0 if capture channel is not valid + ******************************************************************************/ +uint32_t sli_sleeptimer_get_capture(void); + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +void sli_sleeptimer_reset_prs_signal(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SLI_SLEEPTIMER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c index 1f7cbd2..8cf245e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer.c @@ -1,1942 +1,1942 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER API implementation. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include -#include - -#include "em_device.h" -#include "em_core_generic.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "sl_atomic.h" -#include "sl_sleeptimer_config.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include "sl_component_catalog.h" -#endif -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#include "sli_power_manager.h" -#endif - -#define TIME_UNIX_EPOCH (1970u) -#define TIME_NTP_EPOCH (1900u) -#define TIME_ZIGBEE_EPOCH (2000u) -#define TIME_64_EPOCH TIME_NTP_EPOCH -#define TIME_NTP_UNIX_EPOCH_DIFF (TIME_UNIX_EPOCH - TIME_NTP_EPOCH) -#define TIME_ZIGBEE_UNIX_EPOCH_DIFF (TIME_ZIGBEE_EPOCH - TIME_UNIX_EPOCH) -#define TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH (TIME_NTP_UNIX_EPOCH_DIFF * 365u + 17u) ///< 70 years and 17 leap days -#define TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH (TIME_ZIGBEE_UNIX_EPOCH_DIFF * 365u + 7u) ///< 30 years and 7 leap days -#define TIME_SEC_PER_DAY (60u * 60u * 24u) -#define TIME_NTP_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) -#define TIME_ZIGBEE_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) -#define TIME_DAY_PER_YEAR (365u) -#define TIME_SEC_PER_YEAR (TIME_SEC_PER_DAY * TIME_DAY_PER_YEAR) -#define TIME_UNIX_TIMESTAMP_MAX (0x7FFFFFFF) -#define TIME_64_BIT_UNIX_TIMESTAMP_MAX (0x497968BD7F) /// Max 64 bit timestamp supported is 11:59:59 PM 12/31/11899 -#define TIME_UNIX_YEAR_MAX (2038u - TIME_NTP_EPOCH) ///< Max UNIX year based from a 1900 epoch -#define TIME_64_BIT_YEAR_MAX (11899u - TIME_NTP_EPOCH) ///< Max 64 bit format year based from a 1900 epoch -#define TIME_64_TO_32_EPOCH_OFFSET_SEC TIME_NTP_EPOCH_OFFSET_SEC -#define TIME_UNIX_TO_NTP_MAX (0xFFFFFFFF - TIME_NTP_EPOCH_OFFSET_SEC) - -// Minimum count difference used when evaluating if a timer expired or not after an interrupt -// by comparing the current count value and the expected expiration count value. -// The difference should be null or of few ticks since the counter never stop. -#define MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION 2 - -/// @brief Time Format. -SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { - TIME_FORMAT_UNIX = 0, ///< Number of seconds since January 1, 1970, 00:00. Type is signed, so represented on 31 bit. - TIME_FORMAT_NTP = 1, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 32 bit. - TIME_FORMAT_ZIGBEE_CLUSTER = 2, ///< Number of seconds since January 1, 2000, 00:00. Type is unsigned, so represented on 32 bit. - TIME_FORMAT_UNIX_64_BIT = 3, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 64 bit. -}; - -// tick_count, it can wrap around. -typedef uint32_t sl_sleeptimer_tick_count_t; - -// Overflow counter used to provide 64-bits tick count. -static volatile uint16_t overflow_counter; - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -// Current time count. -static sl_sleeptimer_timestamp_64_t second_count; -// Tick rest when the frequency is not a divider of the timer width. -static uint32_t overflow_tick_rest = 0; -// Current time zone offset. -static sl_sleeptimer_time_zone_offset_t tz_offset = 0; -// Precalculated tick rest in case of overflow. -static uint32_t calculated_tick_rest = 0; -// Precalculated timer overflow duration in seconds. -static uint32_t calculated_sec_count = 0; -#endif - -// Timer frequency in Hz. -static uint32_t timer_frequency; - -// Head of timer list. -static sl_sleeptimer_timer_handle_t *timer_head; - -// Count at last update of delta of first timer. -static volatile sl_sleeptimer_tick_count_t last_delta_update_count; - -// Initialization flag. -static bool is_sleeptimer_initialized = false; - -// Flag that indicates if power manager's timer will expire at next compare match. -static bool next_timer_to_expire_is_power_manager = false; - -// Precalculated value to avoid millisecond to tick conversion overflow. -static uint32_t max_millisecond_conversion; - -// Sleep on ISR exit flag. -static bool sleep_on_isr_exit = false; - -static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout); - -static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); - -static void set_comparator_for_next_timer(void); - -static void update_delta_list(void); - -__STATIC_INLINE uint32_t div_to_log2(uint32_t div); - -__STATIC_INLINE bool is_power_of_2(uint32_t nbr); - -static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout_initial, - sl_sleeptimer_tick_count_t timeout_periodic, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags); - -static void update_next_timer_to_expire_is_power_manager(void); - -static void delay_callback(sl_sleeptimer_timer_handle_t *handle, - void *data); - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -static bool is_leap_year(uint16_t year); -static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year); - -static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day); -static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day); -static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool isLeapYear); - -static bool is_valid_time(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone); - -static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone); - -static bool is_valid_date(sl_sleeptimer_date_t *date); - -static bool is_valid_date_64(sl_sleeptimer_date_t *date); - -static const uint8_t days_in_month[2u][12] = { - /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ - { 31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u }, - { 31u, 29u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u } -}; -#endif - -/**************************************************************************//** - * Initializes sleep timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_init(void) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - if (!is_sleeptimer_initialized) { - timer_head = NULL; - last_delta_update_count = 0u; - overflow_counter = 0u; - sleeptimer_hal_init_timer(); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_OF); - timer_frequency = sleeptimer_hal_get_timer_frequency(); - if (timer_frequency == 0) { - CORE_EXIT_ATOMIC(); - return SL_STATUS_INVALID_CONFIGURATION; - } - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG - second_count = 0; - calculated_tick_rest = ((uint64_t)UINT32_MAX + 1) % (uint64_t)timer_frequency; - calculated_sec_count = (((uint64_t)UINT32_MAX + 1) / (uint64_t)timer_frequency); -#endif - max_millisecond_conversion = (uint32_t)(((uint64_t)UINT32_MAX * (uint64_t)1000u) / timer_frequency); - is_sleeptimer_initialized = true; - } - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Starts a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_NOT_READY; - } - - return create_timer(handle, - timeout, - 0, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer is not running. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout, - 0, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Starts a 32 bits periodic timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_INVALID_STATE; - } - - return create_timer(handle, - timeout, - timeout, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Starts a 32 bits periodic timer using milliseconds as the timebase. - *****************************************************************************/ -sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - bool is_running = false; - sl_status_t status; - uint32_t timeout_tick; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - sl_sleeptimer_is_timer_running(handle, &is_running); - if (is_running == true) { - return SL_STATUS_INVALID_STATE; - } - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - // Calculate ms to ticks conversion error - handle->conversion_error = 1000 - - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) - % 1000); - if (handle->conversion_error == 1000) { - handle->conversion_error = 0; - } - // Initialize accumulated error to 0. The calculated conversion error will - // be added to this variable each time a timer in the series of periodic timers - // expires. - handle->accumulated_error = 0; - - return create_timer(handle, - timeout_tick, - timeout_tick, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits periodic timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - handle->conversion_error = 0; - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout, - timeout, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Restarts a 32 bits periodic timer using milliseconds as the timebase. - *****************************************************************************/ -sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, - uint32_t timeout_ms, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - sl_status_t status; - uint32_t timeout_tick; - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); - if (status != SL_STATUS_OK) { - return status; - } - - // Calculate ms to ticks conversion error - handle->conversion_error = 1000 - - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) - % 1000); - if (handle->conversion_error == 1000) { - handle->conversion_error = 0; - } - - // Initialize accumulated error to 0. The calculated conversion error will - // be added to this variable each time a timer in the series of periodic timers - // expires. - handle->accumulated_error = 0; - - //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. - sl_sleeptimer_stop_timer(handle); - - //Creates the timer in any case. - return create_timer(handle, - timeout_tick, - timeout_tick, - callback, - callback_data, - priority, - option_flags); -} - -/**************************************************************************//** - * Stops a 32 bits timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) -{ - CORE_DECLARE_IRQ_STATE; - sl_status_t error; - bool set_comparator = false; - - // Disable PRS compare and capture channel, if configured for early wakeup -#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ - && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - if (handle->option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { - sleeptimer_hal_disable_prs_compare_and_capture_channel(); - } -#endif - - if (handle == NULL) { - return SL_STATUS_NULL_POINTER; - } - - CORE_ENTER_CRITICAL(); - update_delta_list(); - - // If first timer in list, update timer comparator. - if (timer_head == handle) { - set_comparator = true; - } - - error = delta_list_remove_timer(handle); - if (error != SL_STATUS_OK) { - CORE_EXIT_CRITICAL(); - - return error; - } - - if (set_comparator && timer_head) { - set_comparator_for_next_timer(); - } else if (!timer_head) { - sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); - } - - CORE_EXIT_CRITICAL(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets the status of a timer. - *****************************************************************************/ -sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, - bool *running) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - - if (handle == NULL || running == NULL) { - return SL_STATUS_NULL_POINTER; - } else { - *running = false; - CORE_ENTER_ATOMIC(); - current = timer_head; - while (current != NULL && !*running) { - if (current == handle) { - *running = true; - } else { - current = current->next; - } - } - CORE_EXIT_ATOMIC(); - } - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets a 32 bits timer's time remaining. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, - uint32_t *time) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - - if (handle == NULL || time == NULL) { - return SL_STATUS_NULL_POINTER; - } - - CORE_ENTER_ATOMIC(); - - update_delta_list(); - *time = handle->delta; - - // Retrieve timer in list and add the deltas. - current = timer_head; - while (current != handle && current != NULL) { - *time += current->delta; - current = current->next; - } - - if (current != handle) { - CORE_EXIT_ATOMIC(); - - return SL_STATUS_NOT_READY; - } - - // Substract time since last compare match. - if (*time > sleeptimer_hal_get_counter() - last_delta_update_count) { - *time -= sleeptimer_hal_get_counter() - last_delta_update_count; - } else { - *time = 0; - } - - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/**************************************************************************//** - * Gets the time remaining until the first timer with the matching set of flags - * expires. - *****************************************************************************/ -sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, - uint32_t *time_remaining) -{ - CORE_DECLARE_IRQ_STATE; - sl_sleeptimer_timer_handle_t *current; - uint32_t time = 0; - - CORE_ENTER_ATOMIC(); - // parse list and retrieve first timer with option flags requirement. - current = timer_head; - while (current != NULL) { - // save time remaining for timer. - time += current->delta; - // Check if the current timer has the flags requested - if (current->option_flags == option_flags - || option_flags == SL_SLEEPTIMER_ANY_FLAG) { - // Substract time since last compare match. - if (time > (sleeptimer_hal_get_counter() - last_delta_update_count)) { - time -= (sleeptimer_hal_get_counter() - last_delta_update_count); - } else { - time = 0; - } - *time_remaining = time; - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; - } - current = current->next; - } - CORE_EXIT_ATOMIC(); - - return SL_STATUS_EMPTY; -} - -/**************************************************************************//** - * Determines if next timer to expire has the option flag - * "SL_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". - * - * @note This function is for internal use only. - * - * @note A check to validate that the Power Manager Sleeptimer is expired on - * top of being the next timer was added. This is because - * this function is called when coming back from EM2 sleep to validate - * that the system woke up because of this precise timer expiration. - * Some race conditions, seen with FreeRTOS, could create invalid RTC - * interrupt leading to believe that the power manager timer was expired - * when it was not. - *****************************************************************************/ -bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) -{ - bool next_timer_is_power_manager; - - sl_atomic_load(next_timer_is_power_manager, next_timer_to_expire_is_power_manager); - - // Make sure that the Power Manager Sleeptimer is actually expired in addition - // to being the next timer. - if ((next_timer_is_power_manager) - && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { - next_timer_is_power_manager = false; - } - - return next_timer_is_power_manager; -} - -/***************************************************************************//** -* Gets current 32 bits tick count. -*******************************************************************************/ -uint32_t sl_sleeptimer_get_tick_count(void) -{ - uint32_t cnt; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - cnt = sleeptimer_hal_get_counter(); - CORE_EXIT_ATOMIC(); - - return cnt; -} - -/***************************************************************************//** -* Gets current 64 bits tick count. -*******************************************************************************/ -uint64_t sl_sleeptimer_get_tick_count64(void) -{ - uint32_t tick_cnt; - uint32_t of_cnt; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - tick_cnt = sleeptimer_hal_get_counter(); - of_cnt = overflow_counter; - - if (sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_OF)) { - tick_cnt = sleeptimer_hal_get_counter(); - of_cnt++; - } - CORE_EXIT_ATOMIC(); - - return (((uint64_t) of_cnt) << 32) | tick_cnt; -} - -/***************************************************************************//** - * Get timer frequency. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_timer_frequency(void) -{ - return timer_frequency; -} - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -/***************************************************************************//** - * Retrieves current 32 bit time. - ******************************************************************************/ -sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void) -{ - uint64_t temp_time = sl_sleeptimer_get_time_64(); - // Add offset for 64 to 32 bit time - if (temp_time >= TIME_64_TO_32_EPOCH_OFFSET_SEC) { - temp_time -= TIME_64_TO_32_EPOCH_OFFSET_SEC; - } - // Return lower 32 bits of 64 bit time - uint32_t time = (temp_time & 0xFFFFFFFF); - - return time; -} - -/***************************************************************************//** - * Retrieves current 64 bit time. - ******************************************************************************/ -sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void) -{ - uint32_t cnt = 0u; - uint32_t freq = 0u; - sl_sleeptimer_timestamp_64_t time; - CORE_DECLARE_IRQ_STATE; - - cnt = sleeptimer_hal_get_counter(); - freq = sl_sleeptimer_get_timer_frequency(); - - CORE_ENTER_ATOMIC(); - time = second_count + cnt / freq; - - if (cnt % freq + overflow_tick_rest >= freq) { - time++; - } - CORE_EXIT_ATOMIC(); - - return time; -} - -/***************************************************************************//** - * Sets current time from 32 bit variable. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time) -{ - // convert 32 bit time to 64 bit time - uint64_t temp_time = time + TIME_64_TO_32_EPOCH_OFFSET_SEC; - sl_status_t err_code = sl_sleeptimer_set_time_64(temp_time); - return err_code; -} - -/***************************************************************************//** - * Sets current time from 64 bit variable. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time) -{ - uint32_t freq = 0u; - uint32_t counter_sec = 0u; - uint32_t cnt = 0; - CORE_DECLARE_IRQ_STATE; - - // convert 64 bit time to 32 bit time - if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } - - freq = sl_sleeptimer_get_timer_frequency(); - cnt = sleeptimer_hal_get_counter(); - - CORE_ENTER_ATOMIC(); - // store 64 bit time as 64 bits's - second_count = time; - - // Convert 64 bit time to 32 bit time in order to check for overflow - // i.e. if 32 bit time is >=counter_sec - uint64_t temp_time = second_count - TIME_64_TO_32_EPOCH_OFFSET_SEC; - uint32_t second_time_32 = (temp_time & 0xFFFFFFFF); - - overflow_tick_rest = 0; - counter_sec = cnt / freq; - - if (second_time_32 >= counter_sec) { - second_count -= counter_sec; - } else { - CORE_EXIT_ATOMIC(); - - return SL_STATUS_INVALID_PARAMETER; - } - - CORE_EXIT_ATOMIC(); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Gets current date. - ******************************************************************************/ -sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date) -{ - sl_sleeptimer_timestamp_64_t time = 0u; - sl_sleeptimer_time_zone_offset_t tz; - sl_status_t err_code = SL_STATUS_OK; - - // Fetch 64 bit timestamp - time = sl_sleeptimer_get_time_64(); - tz = sl_sleeptimer_get_tz(); - err_code = sl_sleeptimer_convert_time_to_date_64(time, tz, date); - - return err_code; -} - -/***************************************************************************//** - * Sets current time, in date format. - ******************************************************************************/ -sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date) -{ - sl_sleeptimer_timestamp_64_t time = 0u; - sl_status_t err_code = SL_STATUS_OK; - CORE_DECLARE_IRQ_STATE; - - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - err_code = sl_sleeptimer_convert_date_to_time_64(date, &time); - if (err_code != SL_STATUS_OK) { - return err_code; - } - - CORE_ENTER_ATOMIC(); - // sets the 64 bit second_time value - err_code = sl_sleeptimer_set_time_64(time); - if (err_code == SL_STATUS_OK) { - sl_sleeptimer_set_tz(date->time_zone); - } - CORE_EXIT_ATOMIC(); - - return err_code; -} - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tz_offset) -{ - if (date == NULL) { - return SL_STATUS_NULL_POINTER; - } - - // If year is smaller than 1900, assume NTP Epoch is used. - date->year = ((year < TIME_NTP_EPOCH) ? year : (year - TIME_NTP_EPOCH)); - date->month = month; - date->month_day = month_day; - date->hour = hour; - date->min = min; - date->sec = sec; - date->time_zone = tz_offset; - - // Validate that input parameters are correct before filing the missing fields - if (!is_valid_date(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); - date->day_of_week = compute_day_of_week(((date->year - TIME_NTP_UNIX_EPOCH_DIFF) * TIME_DAY_PER_YEAR) - + number_of_leap_days(TIME_UNIX_EPOCH, (date->year + TIME_NTP_EPOCH)) - + date->day_of_year - 1); - - return SL_STATUS_OK; -} - -/***************************************************************************//** - * Builds a date time structure based on the provided parameters. - ******************************************************************************/ -sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, - uint16_t year, - sl_sleeptimer_month_t month, - uint8_t month_day, - uint8_t hour, - uint8_t min, - uint8_t sec, - sl_sleeptimer_time_zone_offset_t tz_offset) -{ - if (date == NULL) { - return SL_STATUS_NULL_POINTER; - } - - // Ensure that year is greater than 1900 and based on 0 epoch - if (year < TIME_NTP_EPOCH) { - return SL_STATUS_INVALID_PARAMETER; - } - - // Convert year based on 0 epoch to a valid date->year based on 1900 epoch - date->year = (year - TIME_NTP_EPOCH); - date->month = month; - date->month_day = month_day; - date->hour = hour; - date->min = min; - date->sec = sec; - date->time_zone = tz_offset; - - // Validate that input parameters are correct before filing the missing fields - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); - date->day_of_week = compute_day_of_week_64((date->year * TIME_DAY_PER_YEAR) - + number_of_leap_days(TIME_NTP_EPOCH, (date->year + TIME_NTP_EPOCH)) - + date->day_of_year - 1); - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a 32 bit time stamp into a date structure. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date) -{ - // convert 32 bit timestamp to 64 bit - sl_sleeptimer_timestamp_64_t temp_time = (uint64_t)time + TIME_64_TO_32_EPOCH_OFFSET_SEC; - sl_status_t err_code = sl_sleeptimer_convert_time_to_date_64(temp_time, time_zone, date); - return err_code; -} - -/******************************************************************************* - * Convert a 64 bit time stamp into a date structure. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_zone_offset_t time_zone, - sl_sleeptimer_date_t *date) -{ - uint16_t full_year = 0; - uint16_t leap_day = 0; - uint8_t leap_year_flag = 0; - uint8_t current_month = 0; - - if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, time_zone)) { - return SL_STATUS_INVALID_PARAMETER; - } - - time += time_zone; // add UTC offset to convert to Standard Time - date->sec = time % 60; - time /= 60; - date->min = time % 60; - time /= 60; - date->hour = time % 24; - time /= 24; // time is now the number of days since 1900 - - date->day_of_week = (sl_sleeptimer_weekDay_t)compute_day_of_week_64(time); - - full_year = time / TIME_DAY_PER_YEAR; // Approximates the number of full years - uint32_t base_year = 1900u; - uint32_t current_year = full_year + base_year; - - if (full_year > 4) { // 1904 is the first leap year since 1900 - leap_day = number_of_leap_days(base_year, current_year); // Approximates the number of leap days. - full_year = (time - leap_day) / TIME_DAY_PER_YEAR; // Computes the number of year integrating the leap days. - current_year = full_year + base_year; - leap_day = number_of_leap_days(base_year, current_year); // Computes the actual number of leap days of the previous years. - } - date->year = full_year; // Year in date struct must be based on a 1900 epoch. - if (is_leap_year(date->year)) { - leap_year_flag = 1; - } - - time = (time - leap_day) - (TIME_DAY_PER_YEAR * full_year); // Subtracts days of previous year. - date->day_of_year = time + 1; - - while (time >= days_in_month[leap_year_flag][current_month]) { - time -= days_in_month[leap_year_flag][current_month]; // Subtracts the number of days of the passed month. - current_month++; - } - date->month = (sl_sleeptimer_month_t)current_month; - date->month_day = time + 1; - date->time_zone = time_zone; - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a date structure into a 32 bit time stamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_t *time) -{ - // Create a 64 bit time stamp - sl_sleeptimer_timestamp_64_t temp_time = 0; - sl_status_t err_code = sl_sleeptimer_convert_date_to_time_64(date, &temp_time); - - if (err_code != SL_STATUS_OK) { - return err_code; - } - // Convert 64 bit time to 32 bit time - - sl_sleeptimer_timestamp_64_t time_32 = temp_time; - time_32 -= TIME_64_TO_32_EPOCH_OFFSET_SEC; - *time = (time_32 & 0xFFFFFFFF); - - return err_code; -} - -/******************************************************************************* - * Convert a date structure into a 64 bit time stamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, - sl_sleeptimer_timestamp_64_t *time) -{ - uint16_t month_days = 0; - uint8_t month; - uint16_t full_year = 0; - uint8_t leap_year_flag = 0; - uint16_t leap_days = 0; - - if (!is_valid_date_64(date)) { - return SL_STATUS_INVALID_PARAMETER; - } - - full_year = (date->year); // base year for 64 bits its 1900 not 1970 - month = date->month; // offset to get months value from 1 to 12. - - uint32_t base_year = 1900u; - uint32_t current_year = full_year + base_year; - - *time = (full_year * (uint64_t)TIME_SEC_PER_YEAR); - - if (full_year > 4) { // 1904 is the first leap year since 1900 - leap_days = number_of_leap_days(base_year, current_year); - month_days = leap_days; - } - - if (is_leap_year(date->year)) { - leap_year_flag = 1; - } - - for (int i = 0; i < month; i++) { - month_days += days_in_month[leap_year_flag][i]; // Add the number of days of the month of the year. - } - - month_days += (date->month_day - 1); // Add full days of the current month. - *time += month_days * TIME_SEC_PER_DAY; - *time += (3600 * date->hour) + (60 * date->min) + date->sec; - *time -= date->time_zone; - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Convert a date structure to string. - ******************************************************************************/ -uint32_t sl_sleeptimer_convert_date_to_str(char *str, - size_t size, - const uint8_t *format, - sl_sleeptimer_date_t *date) -{ - uint32_t return_size = 0u; - if (is_valid_date(date)) { - struct tm date_struct; - - date_struct.tm_hour = date->hour; - date_struct.tm_mday = date->month_day; - date_struct.tm_min = date->min; - date_struct.tm_mon = date->month; - date_struct.tm_sec = date->sec; - date_struct.tm_wday = date->day_of_week; - date_struct.tm_yday = date->day_of_year; - date_struct.tm_year = date->year; - - return_size = strftime(str, - size, - (const char *)format, - &date_struct); - } - - return return_size; -} - -/***************************************************************************//** - * Sets time zone offset. - * - * @param offset Time zone offset, in seconds. - ******************************************************************************/ -void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset) -{ - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - tz_offset = offset; - CORE_EXIT_ATOMIC(); -} - -/***************************************************************************//** - * Gets time zone offset. - * - * @return Time zone offset, in seconds. - ******************************************************************************/ -sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void) -{ - sl_sleeptimer_time_zone_offset_t offset; - CORE_DECLARE_IRQ_STATE; - - CORE_ENTER_ATOMIC(); - offset = tz_offset; - CORE_EXIT_ATOMIC(); - - return offset; -} - -/***************************************************************************//** - * Converts Unix 32 timestamp into NTP timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, - uint32_t *ntp_time) -{ - if (time > TIME_UNIX_TO_NTP_MAX) { - // Maximum Unix timestamp that can be converted to NTP is 2085978495 - return SL_STATUS_INVALID_PARAMETER; - } - - uint32_t temp_ntp_time; - temp_ntp_time = time + TIME_NTP_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_ntp_time, TIME_FORMAT_NTP, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *ntp_time = temp_ntp_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts NTP timestamp into Unix timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, - sl_sleeptimer_timestamp_t *time) -{ - uint32_t temp_time; - temp_time = ntp_time - TIME_NTP_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *time = temp_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts Unix timestamp into Zigbee timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, - uint32_t *zigbee_time) -{ - uint32_t temp_zigbee_time; - temp_zigbee_time = time - TIME_ZIGBEE_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_zigbee_time, TIME_FORMAT_ZIGBEE_CLUSTER, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *zigbee_time = temp_zigbee_time; - return SL_STATUS_OK; - } -} - -/***************************************************************************//** - * Converts Zigbee timestamp into Unix timestamp. - ******************************************************************************/ -sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, - sl_sleeptimer_timestamp_t *time) -{ - uint32_t temp_time; - temp_time = zigbee_time + TIME_ZIGBEE_EPOCH_OFFSET_SEC; - if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { - return SL_STATUS_INVALID_PARAMETER; - } else { - *time = temp_time; - return SL_STATUS_OK; - } -} - -#endif // SL_SLEEPTIMER_WALLCLOCK_CONFIG - -/******************************************************************************* - * Active delay of 'time_ms' milliseconds. - ******************************************************************************/ -void sl_sleeptimer_delay_millisecond(uint16_t time_ms) -{ - volatile bool wait = true; - sl_status_t error_code; - sl_sleeptimer_timer_handle_t delay_timer; - uint32_t delay = sl_sleeptimer_ms_to_tick(time_ms); - - error_code = sl_sleeptimer_start_timer(&delay_timer, - delay, - delay_callback, - (void *)&wait, - 0, - 0); - if (error_code == SL_STATUS_OK) { - while (wait) { // Active delay loop. - } - } -} - -/******************************************************************************* - * Converts milliseconds in ticks. - ******************************************************************************/ -uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms) -{ - return (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000); -} - -/******************************************************************************* - * Converts 32-bits milliseconds in ticks. - ******************************************************************************/ -sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, - uint32_t *tick) -{ - if (time_ms <= max_millisecond_conversion) { - *tick = (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000u); - return SL_STATUS_OK; - } else { - return SL_STATUS_INVALID_PARAMETER; - } -} - -/***************************************************************************//** - * Gets the maximum value that can be passed to the functions that have a - * 32-bits time or timeout argument expressed in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_get_max_ms32_conversion(void) -{ - return max_millisecond_conversion; -} - -/******************************************************************************* - * Converts ticks in milliseconds. - ******************************************************************************/ -uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick) -{ - uint32_t time_ms; - time_ms = 0; - - if (timer_frequency != 0u) { - if (is_power_of_2(timer_frequency)) { - time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); - } else { - time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); - } - } - - return time_ms; -} - -/******************************************************************************* - * Converts 64-bits ticks in milliseconds. - ******************************************************************************/ -sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, - uint64_t *ms) - -{ - if ((tick <= UINT64_MAX / 1000) - && (timer_frequency != 0u)) { - if (is_power_of_2(timer_frequency)) { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); - return SL_STATUS_OK; - } else { - *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); - return SL_STATUS_OK; - } - } else { - return SL_STATUS_INVALID_PARAMETER; - } -} - -/******************************************************************************* - * Process timer interrupt. - * - * @param local_flag Flag indicating the type of timer interrupt. - ******************************************************************************/ -void process_timer_irq(uint8_t local_flag) -{ - CORE_DECLARE_IRQ_STATE; - if (local_flag & SLEEPTIMER_EVENT_OF) { -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG - uint32_t timer_freq = sl_sleeptimer_get_timer_frequency(); - - overflow_tick_rest += calculated_tick_rest; - if (overflow_tick_rest >= timer_freq) { - second_count++; - overflow_tick_rest -= timer_freq; - } - second_count = second_count + calculated_sec_count; -#endif - overflow_counter++; - - update_delta_list(); - - if (timer_head) { - set_comparator_for_next_timer(); - } - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - sl_sleeptimer_timer_handle_t *current = NULL; - - uint32_t nb_timer_expire = 0u; - uint16_t option_flags = 0; - - CORE_ENTER_ATOMIC(); - // Make sure the timers list is up to date with the time elapsed since the last update - update_delta_list(); - - // Process all timers that have expired. - while ((timer_head) && (timer_head->delta == 0)) { - sl_sleeptimer_timer_handle_t *temp = timer_head; - current = timer_head; - int32_t periodic_correction = 0u; - int64_t timeout_temp = 0; - bool skip_remove = false; - - // Process timers with higher priority first - while ((temp != NULL) && (temp->delta == 0)) { - if (current->priority > temp->priority) { - current = temp; - } - temp = temp->next; - } - CORE_EXIT_ATOMIC(); - - // Check if current periodic timer was delayed more than its actual timeout value - // and keep it at the head of the timers list if it's the case so that the - // callback function can be called the number of required time. - if (current->timeout_periodic != 0u) { - timeout_temp = current->timeout_periodic; - - periodic_correction = sleeptimer_hal_get_counter() - current->timeout_expected_tc; - if (periodic_correction > timeout_temp) { - skip_remove = true; - current->timeout_expected_tc += current->timeout_periodic; - } - } - - // Remove current timer from timer list except if the current timer is a periodic timer - // that was intentionally kept at the head of the timers list. - if (skip_remove != true) { - CORE_ENTER_ATOMIC(); - delta_list_remove_timer(current); - CORE_EXIT_ATOMIC(); - } - - // Re-insert periodic timer that was previsouly removed from the list - // and compensate for any deviation from the periodic timer frequency. - if (current->timeout_periodic != 0u && skip_remove != true) { - timeout_temp -= periodic_correction; - EFM_ASSERT(timeout_temp >= 0); - // Compensate for drift caused by ms to ticks conversion - if (current->conversion_error > 0) { - // Increment accumulated error by the ms to ticks conversion error - current->accumulated_error += current->conversion_error; - // If the accumulated error exceeds a tick, subtract that tick from the next - // periodic timer's timeout value. - if (current->accumulated_error >= 1000) { - current->accumulated_error -= 1000; - timeout_temp -= 1; - current->timeout_expected_tc -= 1; - } - } - CORE_ENTER_ATOMIC(); - delta_list_insert_timer(current, (sl_sleeptimer_tick_count_t)timeout_temp); - current->timeout_expected_tc += current->timeout_periodic; - CORE_EXIT_ATOMIC(); - } - - // Save current option flag and the number of timers that expired. - option_flags = current->option_flags; - nb_timer_expire++; - - // Call current timer callback function if any. - if (current->callback != NULL) { - current->callback(current, current->callback_data); - } - - CORE_ENTER_ATOMIC(); - - // Re-update the list to account for delays during timer's callback. - update_delta_list(); - } - - // If the only timer expired is the internal Power Manager one, - // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. - sleep_on_isr_exit = false; - if (nb_timer_expire == 1u) { - if (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { - sleep_on_isr_exit = true; - } - } - - if (timer_head) { - set_comparator_for_next_timer(); - } else { - sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_ATOMIC(); - } -} - -/******************************************************************************* - * Timer expiration callback for the delay function. - * - * @param handle Pointer to handle to timer. - * @param data Pointer to delay flag. - ******************************************************************************/ -static void delay_callback(sl_sleeptimer_timer_handle_t *handle, - void *data) -{ - volatile bool *wait_flag = (bool *)data; - - (void)handle; // Unused parameter. - - *wait_flag = false; -} - -/******************************************************************************* - * Inserts a timer in the delta list. - * - * @param handle Pointer to handle to timer. - * @param timeout Timer timeout, in ticks. - ******************************************************************************/ -static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout) -{ - sl_sleeptimer_tick_count_t local_handle_delta = timeout; - -#ifdef SL_CATALOG_POWER_MANAGER_PRESENT - // If Power Manager is present, it's possible that a clock restore is needed right away - // if we are in the context of a deepsleep and the timeout value is smaller than the restore time. - // If it's the case, the restore will be started and the timeout value will be updated to match - // the restore delay. - if (handle->option_flags == 0) { - uint32_t wakeup_delay = sli_power_manager_get_restore_delay(); - - if (local_handle_delta < wakeup_delay) { - local_handle_delta = wakeup_delay; - sli_power_manager_initiate_restore(); - } - } -#endif - - handle->delta = local_handle_delta; - - if (timer_head != NULL) { - sl_sleeptimer_timer_handle_t *prev = NULL; - sl_sleeptimer_timer_handle_t *current = timer_head; - // Find timer position taking into accounts the deltas and priority. - while (current != NULL - && (local_handle_delta >= current->delta || current->delta == 0u - || (((local_handle_delta - current->delta) == 0) && (handle->priority > current->priority)))) { - local_handle_delta -= current->delta; - handle->delta = local_handle_delta; - prev = current; - current = current->next; - } - - // Insert timer in middle of delta list. - if (prev != NULL) { - prev->next = handle; - } else { - timer_head = handle; - } - handle->next = current; - - if (current != NULL) { - current->delta -= local_handle_delta; - } - } else { - timer_head = handle; - handle->next = NULL; - } -} - -/******************************************************************************* - * Removes a timer from delta list. - * - * @param handle Pointer to handle to timer. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) -{ - sl_sleeptimer_timer_handle_t *prev = NULL; - sl_sleeptimer_timer_handle_t *current = timer_head; - - // Retrieve timer in delta list. - while (current != NULL && current != handle) { - prev = current; - current = current->next; - } - - if (current != handle) { - return SL_STATUS_INVALID_STATE; - } - - if (prev != NULL) { - prev->next = handle->next; - } else { - timer_head = handle->next; - } - - // Update delta of next timer - if (handle->next != NULL) { - handle->next->delta += handle->delta; - } - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Sets comparator for next timer. - ******************************************************************************/ -static void set_comparator_for_next_timer(void) -{ - if (timer_head->delta > 0) { - sl_sleeptimer_tick_count_t compare_value; - - compare_value = last_delta_update_count + timer_head->delta; - - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_compare(compare_value); - } else { - // In case timer has already expire, don't attempt to set comparator. Just - // trigger compare match interrupt. - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); - } - - update_next_timer_to_expire_is_power_manager(); -} - -/******************************************************************************* - * Updates timer list's deltas. - ******************************************************************************/ -static void update_delta_list(void) -{ - sl_sleeptimer_tick_count_t current_cnt = sleeptimer_hal_get_counter(); - sl_sleeptimer_timer_handle_t *timer_handle = timer_head; - sl_sleeptimer_tick_count_t time_diff = current_cnt - last_delta_update_count; - - // Go through the delta timer list and update every necessary deltas - // according to the time elapsed since the last update. - while (timer_handle != NULL && time_diff > 0) { - if (timer_handle->delta >= time_diff) { - timer_handle->delta -= time_diff; - time_diff = 0; - } else { - time_diff -= timer_handle->delta; - timer_handle->delta = 0; - } - timer_handle = timer_handle->next; - } - - last_delta_update_count = current_cnt; -} - -/******************************************************************************* - * Creates and start a 32 bits timer. - * - * @param handle Pointer to handle to timer. - * @param timeout_initial Initial timeout, in timer ticks. - * @param timeout_periodic Periodic timeout, in timer ticks. This timeout - * applies once timeoutInitial expires. Can be set to 0 for a one - * shot timer. - * @param callback Callback function that will be called when - * initial/periodic timeout expires. - * @param callback_data Pointer to user data that will be passed to callback. - * @param priority Priority of callback. Useful in case multiple timer expire - * at the same time. 0 = highest priority. - * - * @return 0 if successful. Error code otherwise. - ******************************************************************************/ -static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, - sl_sleeptimer_tick_count_t timeout_initial, - sl_sleeptimer_tick_count_t timeout_periodic, - sl_sleeptimer_timer_callback_t callback, - void *callback_data, - uint8_t priority, - uint16_t option_flags) -{ - CORE_DECLARE_IRQ_STATE; - - handle->priority = priority; - handle->callback_data = callback_data; - handle->next = NULL; - handle->timeout_periodic = timeout_periodic; - handle->callback = callback; - handle->option_flags = option_flags; - if (timeout_periodic == 0) { - handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_initial; - } else { - handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_periodic; - } - - if (timeout_initial == 0) { - handle->delta = 0; - if (handle->callback != NULL) { - handle->callback(handle, handle->callback_data); - } - if (timeout_periodic != 0) { - timeout_initial = timeout_periodic; - } else { - return SL_STATUS_OK; - } - } - -#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ - && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ - && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) - if (option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { - HFXO0->CTRL |= HFXO_CTRL_EM23ONDEMAND; - sleeptimer_hal_set_compare_prs_hfxo_startup(timeout_initial); - return SL_STATUS_OK; - } -#endif - - CORE_ENTER_CRITICAL(); - update_delta_list(); - delta_list_insert_timer(handle, timeout_initial); - - // If first timer, update timer comparator. - if (timer_head == handle) { - set_comparator_for_next_timer(); - } - - CORE_EXIT_CRITICAL(); - - return SL_STATUS_OK; -} - -/******************************************************************************* - * Updates internal flag that indicates if next timer to expire is the power - * manager's one. - ******************************************************************************/ -static void update_next_timer_to_expire_is_power_manager(void) -{ - sl_sleeptimer_timer_handle_t *current = timer_head; - uint32_t delta_diff_with_first = 0; - - next_timer_to_expire_is_power_manager = false; - - while (delta_diff_with_first <= 1) { - if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { - next_timer_to_expire_is_power_manager = true; - break; - } - - current = current->next; - if (current == NULL) { - break; - } - - delta_diff_with_first += current->delta; - } -} - -/**************************************************************************//** - * Determines if the power manager's early wakeup expired during the last ISR - * and it was the only timer to expire in that period. - * - * @return true if power manager sleep can return to sleep, - * false otherwise. - *****************************************************************************/ -bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void) -{ - CORE_DECLARE_IRQ_STATE; - bool sleep; - - CORE_ENTER_ATOMIC(); - sleep = sleep_on_isr_exit; - CORE_EXIT_ATOMIC(); - - return sleep; -} - -/******************************************************************************* - * Convert dividend to logarithmic value. It only works for even - * numbers equal to 2^n. - * - * @param div An unscaled dividend. - * - * @return Logarithm of 2. - ******************************************************************************/ -__STATIC_INLINE uint32_t div_to_log2(uint32_t div) -{ - return 31UL - __CLZ(div); // Count leading zeroes and "reverse" result. -} - -/******************************************************************************* - * Determines if a number is a power of two. - * - * @param nbr Input value. - * - * @return True if the number is a power of two. - ******************************************************************************/ -__STATIC_INLINE bool is_power_of_2(uint32_t nbr) -{ - if ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u))) { - return true; - } else { - return false; - } -} - -#if SL_SLEEPTIMER_WALLCLOCK_CONFIG -/******************************************************************************* - * Compute the day of the week. - * - * @param day Days since January 1st of 1970. - * - * @return the day of the week. - ******************************************************************************/ -static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day) -{ - return (sl_sleeptimer_weekDay_t)((day + 4) % 7); // January 1st was a Thursday(4) in 1970 -} - -/******************************************************************************* - * Compute the day of the week. - * - * @param day Days since January 1st of 1900. - * - * @return the day of the week. - ******************************************************************************/ -static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day) -{ - return (sl_sleeptimer_weekDay_t)((day + 1) % 7); // January 1st was a Monday(1) in 1900 -} - -/******************************************************************************* - * Compute the day of the year. This function assumes that the inputs are properly - * sanitized. - * - * @param month Number of months since January. - * @param day Day of the month - * @param is_leap_year Specifies if the year computed against is a leap year. - * - * @return the number of days since the beginning of the year - ******************************************************************************/ -static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool is_leap_year) -{ - uint8_t i; - uint16_t dayOfYear = 0; - - for (i = 0; i < month; ++i) { - dayOfYear += days_in_month[is_leap_year][i]; - } - dayOfYear += day; - - return dayOfYear; -} - -/******************************************************************************* - * Checks if the year is a leap year. - * - * @param year Year to check. - * - * @return true if the year is a leap year. False otherwise. - ******************************************************************************/ -static bool is_leap_year(uint16_t year) -{ - // 1900 is not a leap year but 0 % anything is 0. - if (year == 0) { - return false; - } - - bool leap_year; - - leap_year = (((year % 4u) == 0u) - && (((year % 100u) != 0u) || ((year % 400u) == 0u))) ? true : false; - - return (leap_year); -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param base_year Year to start from to compute leap days. - * @param current_year Year end at for computing leap days. - * - * @return leap_days Days number of leap days between base_year and current_year. - ******************************************************************************/ -static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year) -{ - // Regular leap years - uint16_t lo_reg = (base_year - 0) / 4; - uint16_t hi_reg = (current_year - 1) / 4; - uint16_t leap_days = hi_reg - lo_reg; - - // Account for non leap years - uint16_t lo_century = (base_year - 0) / 100; - uint16_t hi_century = (current_year - 1) / 100; - leap_days -= hi_century - lo_century; - - // Account for quad century leap years - uint16_t lo_quad = (base_year - 0) / 400; - uint16_t hi_quad = (current_year - 1) / 400; - leap_days += hi_quad - lo_quad; - - return (leap_days); -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param time Time stamp to check. - * @param format Format of the time. - * @param time_zone Time zone offset in second. - * - * @return true if the time is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_time(sl_sleeptimer_timestamp_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone) -{ - bool valid_time = false; - - // Check for overflow. - if ((time_zone < 0 && time > (uint32_t)abs(time_zone)) \ - || (time_zone >= 0 && (time <= UINT32_MAX - time_zone))) { - valid_time = true; - } - if (format == TIME_FORMAT_UNIX) { - if (time > TIME_UNIX_TIMESTAMP_MAX) { // Check if Unix time stamp is an unsigned 31 bits. - valid_time = false; - } - } else { - if ((format == TIME_FORMAT_NTP) && (time >= TIME_NTP_EPOCH_OFFSET_SEC)) { - valid_time &= true; - } else if ((format == TIME_FORMAT_ZIGBEE_CLUSTER) && (time <= TIME_UNIX_TIMESTAMP_MAX - TIME_ZIGBEE_EPOCH_OFFSET_SEC)) { - valid_time &= true; - } else { - valid_time = false; - } - } - return valid_time; -} - -/******************************************************************************* - * Checks if the time stamp, format and time zone are - * within the supported range. - * - * @param time Time stamp to check. - * @param format Format of the time. - * @param time_zone Time zone offset in second. - * - * @return true if the time is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, - sl_sleeptimer_time_format_t format, - sl_sleeptimer_time_zone_offset_t time_zone) -{ - bool valid_time = false; - - // Check for overflow. - if ((time_zone < 0 && time > (uint64_t)abs(time_zone)) - || (time_zone >= 0 && (time <= UINT64_MAX - time_zone))) { - valid_time = true; - } - if (format == TIME_FORMAT_UNIX_64_BIT) { - if (time > TIME_64_BIT_UNIX_TIMESTAMP_MAX) { // Check if time stamp is an unsigned 64 bits. - valid_time = false; - } - } - return valid_time; -} - -/******************************************************************************* - * Checks if the date is valid. - * - * @param date Date to check. - * - * @return true if the date is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_date(sl_sleeptimer_date_t *date) -{ - if ((date == NULL) - || (date->year > TIME_UNIX_YEAR_MAX) - || (date->month > MONTH_DECEMBER) - || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) - || (date->hour > 23) - || (date->min > 59) - || (date->sec > 59)) { - return false; - } - - // Unix is valid until the 19th of January 2038 at 03:14:07 - if (date->year == TIME_UNIX_YEAR_MAX) { - if ((uint8_t)date->month > (uint8_t)MONTH_JANUARY) { - return false; - } else if (date->month_day > 19) { - return false; - } else if (date->hour > 3) { - return false; - } else if (date->min > 14) { - return false; - } else if (date->sec > 7) { - return false; - } - } - - return true; -} - -/******************************************************************************* - * Checks if the date is valid. - * - * @param date Date to check. - * - * @return true if the date is valid. False otherwise. - ******************************************************************************/ -static bool is_valid_date_64(sl_sleeptimer_date_t *date) -{ - if ((date == NULL) - || (date->year > TIME_64_BIT_YEAR_MAX) - || (date->month > MONTH_DECEMBER) - || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) - || (date->hour > 23) - || (date->min > 59) - || (date->sec > 59)) { - return false; - } - return true; -} -#endif - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sl_sleeptimer_get_clock_accuracy(void) -{ - return sleeptimer_hal_get_clock_accuracy(); -} - -/***************************************************************************//** - * @brief - * Update sleep_on_isr_exit flag. - * - * @param flag Value update_sleep_on_isr_exit will be set to. - ******************************************************************************/ -void sli_sleeptimer_update_sleep_on_isr_exit(bool flag) -{ - sleep_on_isr_exit = flag; -} - -/******************************************************************************* - * Gets the associated peripheral capture channel current value. - ******************************************************************************/ -uint32_t sli_sleeptimer_get_capture(void) -{ - return sleeptimer_hal_get_capture(); -} - -/******************************************************************************* - * Resets the PRS signal triggered by the associated peripheral. - ******************************************************************************/ -void sli_sleeptimer_reset_prs_signal(void) -{ - sleeptimer_hal_reset_prs_signal(); -} +/***************************************************************************//** + * @file + * @brief SLEEPTIMER API implementation. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include +#include + +#include "em_device.h" +#include "em_core_generic.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "sl_atomic.h" +#include "sl_sleeptimer_config.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include "sl_component_catalog.h" +#endif +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#include "sli_power_manager.h" +#endif + +#define TIME_UNIX_EPOCH (1970u) +#define TIME_NTP_EPOCH (1900u) +#define TIME_ZIGBEE_EPOCH (2000u) +#define TIME_64_EPOCH TIME_NTP_EPOCH +#define TIME_NTP_UNIX_EPOCH_DIFF (TIME_UNIX_EPOCH - TIME_NTP_EPOCH) +#define TIME_ZIGBEE_UNIX_EPOCH_DIFF (TIME_ZIGBEE_EPOCH - TIME_UNIX_EPOCH) +#define TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH (TIME_NTP_UNIX_EPOCH_DIFF * 365u + 17u) ///< 70 years and 17 leap days +#define TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH (TIME_ZIGBEE_UNIX_EPOCH_DIFF * 365u + 7u) ///< 30 years and 7 leap days +#define TIME_SEC_PER_DAY (60u * 60u * 24u) +#define TIME_NTP_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_NTP_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_ZIGBEE_EPOCH_OFFSET_SEC (TIME_DAY_COUNT_ZIGBEE_TO_UNIX_EPOCH * TIME_SEC_PER_DAY) +#define TIME_DAY_PER_YEAR (365u) +#define TIME_SEC_PER_YEAR (TIME_SEC_PER_DAY * TIME_DAY_PER_YEAR) +#define TIME_UNIX_TIMESTAMP_MAX (0x7FFFFFFF) +#define TIME_64_BIT_UNIX_TIMESTAMP_MAX (0x497968BD7F) /// Max 64 bit timestamp supported is 11:59:59 PM 12/31/11899 +#define TIME_UNIX_YEAR_MAX (2038u - TIME_NTP_EPOCH) ///< Max UNIX year based from a 1900 epoch +#define TIME_64_BIT_YEAR_MAX (11899u - TIME_NTP_EPOCH) ///< Max 64 bit format year based from a 1900 epoch +#define TIME_64_TO_32_EPOCH_OFFSET_SEC TIME_NTP_EPOCH_OFFSET_SEC +#define TIME_UNIX_TO_NTP_MAX (0xFFFFFFFF - TIME_NTP_EPOCH_OFFSET_SEC) + +// Minimum count difference used when evaluating if a timer expired or not after an interrupt +// by comparing the current count value and the expected expiration count value. +// The difference should be null or of few ticks since the counter never stop. +#define MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION 2 + +/// @brief Time Format. +SLEEPTIMER_ENUM(sl_sleeptimer_time_format_t) { + TIME_FORMAT_UNIX = 0, ///< Number of seconds since January 1, 1970, 00:00. Type is signed, so represented on 31 bit. + TIME_FORMAT_NTP = 1, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_ZIGBEE_CLUSTER = 2, ///< Number of seconds since January 1, 2000, 00:00. Type is unsigned, so represented on 32 bit. + TIME_FORMAT_UNIX_64_BIT = 3, ///< Number of seconds since January 1, 1900, 00:00. Type is unsigned, so represented on 64 bit. +}; + +// tick_count, it can wrap around. +typedef uint32_t sl_sleeptimer_tick_count_t; + +// Overflow counter used to provide 64-bits tick count. +static volatile uint16_t overflow_counter; + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +// Current time count. +static sl_sleeptimer_timestamp_64_t second_count; +// Tick rest when the frequency is not a divider of the timer width. +static uint32_t overflow_tick_rest = 0; +// Current time zone offset. +static sl_sleeptimer_time_zone_offset_t tz_offset = 0; +// Precalculated tick rest in case of overflow. +static uint32_t calculated_tick_rest = 0; +// Precalculated timer overflow duration in seconds. +static uint32_t calculated_sec_count = 0; +#endif + +// Timer frequency in Hz. +static uint32_t timer_frequency; + +// Head of timer list. +static sl_sleeptimer_timer_handle_t *timer_head; + +// Count at last update of delta of first timer. +static volatile sl_sleeptimer_tick_count_t last_delta_update_count; + +// Initialization flag. +static bool is_sleeptimer_initialized = false; + +// Flag that indicates if power manager's timer will expire at next compare match. +static bool next_timer_to_expire_is_power_manager = false; + +// Precalculated value to avoid millisecond to tick conversion overflow. +static uint32_t max_millisecond_conversion; + +// Sleep on ISR exit flag. +static bool sleep_on_isr_exit = false; + +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout); + +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle); + +static void set_comparator_for_next_timer(void); + +static void update_delta_list(void); + +__STATIC_INLINE uint32_t div_to_log2(uint32_t div); + +__STATIC_INLINE bool is_power_of_2(uint32_t nbr); + +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags); + +static void update_next_timer_to_expire_is_power_manager(void); + +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data); + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +static bool is_leap_year(uint16_t year); +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year); + +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day); +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day); +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool isLeapYear); + +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone); + +static bool is_valid_date(sl_sleeptimer_date_t *date); + +static bool is_valid_date_64(sl_sleeptimer_date_t *date); + +static const uint8_t days_in_month[2u][12] = { + /* Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec */ + { 31u, 28u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u }, + { 31u, 29u, 31u, 30u, 31u, 30u, 31u, 31u, 30u, 31u, 30u, 31u } +}; +#endif + +/**************************************************************************//** + * Initializes sleep timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_init(void) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + if (!is_sleeptimer_initialized) { + timer_head = NULL; + last_delta_update_count = 0u; + overflow_counter = 0u; + sleeptimer_hal_init_timer(); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_OF); + timer_frequency = sleeptimer_hal_get_timer_frequency(); + if (timer_frequency == 0) { + CORE_EXIT_ATOMIC(); + return SL_STATUS_INVALID_CONFIGURATION; + } + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + second_count = 0; + calculated_tick_rest = ((uint64_t)UINT32_MAX + 1) % (uint64_t)timer_frequency; + calculated_sec_count = (((uint64_t)UINT32_MAX + 1) / (uint64_t)timer_frequency); +#endif + max_millisecond_conversion = (uint32_t)(((uint64_t)UINT32_MAX * (uint64_t)1000u) / timer_frequency); + is_sleeptimer_initialized = true; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Starts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_NOT_READY; + } + + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer is not running. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + 0, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Starts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_start_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + bool is_running = false; + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + sl_sleeptimer_is_timer_running(handle, &is_running); + if (is_running == true) { + return SL_STATUS_INVALID_STATE; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + handle->conversion_error = 0; + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout, + timeout, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Restarts a 32 bits periodic timer using milliseconds as the timebase. + *****************************************************************************/ +sl_status_t sl_sleeptimer_restart_periodic_timer_ms(sl_sleeptimer_timer_handle_t *handle, + uint32_t timeout_ms, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + sl_status_t status; + uint32_t timeout_tick; + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + status = sl_sleeptimer_ms32_to_tick(timeout_ms, &timeout_tick); + if (status != SL_STATUS_OK) { + return status; + } + + // Calculate ms to ticks conversion error + handle->conversion_error = 1000 + - ((uint64_t)(timeout_ms * sl_sleeptimer_get_timer_frequency()) + % 1000); + if (handle->conversion_error == 1000) { + handle->conversion_error = 0; + } + + // Initialize accumulated error to 0. The calculated conversion error will + // be added to this variable each time a timer in the series of periodic timers + // expires. + handle->accumulated_error = 0; + + //Trying to stop the Timer. Failing to do so implies the timer has already been stopped. + sl_sleeptimer_stop_timer(handle); + + //Creates the timer in any case. + return create_timer(handle, + timeout_tick, + timeout_tick, + callback, + callback_data, + priority, + option_flags); +} + +/**************************************************************************//** + * Stops a 32 bits timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_stop_timer(sl_sleeptimer_timer_handle_t *handle) +{ + CORE_DECLARE_IRQ_STATE; + sl_status_t error; + bool set_comparator = false; + + // Disable PRS compare and capture channel, if configured for early wakeup +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (handle->option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + sleeptimer_hal_disable_prs_compare_and_capture_channel(); + } +#endif + + if (handle == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_CRITICAL(); + update_delta_list(); + + // If first timer in list, update timer comparator. + if (timer_head == handle) { + set_comparator = true; + } + + error = delta_list_remove_timer(handle); + if (error != SL_STATUS_OK) { + CORE_EXIT_CRITICAL(); + + return error; + } + + if (set_comparator && timer_head) { + set_comparator_for_next_timer(); + } else if (!timer_head) { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the status of a timer. + *****************************************************************************/ +sl_status_t sl_sleeptimer_is_timer_running(sl_sleeptimer_timer_handle_t *handle, + bool *running) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || running == NULL) { + return SL_STATUS_NULL_POINTER; + } else { + *running = false; + CORE_ENTER_ATOMIC(); + current = timer_head; + while (current != NULL && !*running) { + if (current == handle) { + *running = true; + } else { + current = current->next; + } + } + CORE_EXIT_ATOMIC(); + } + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets a 32 bits timer's time remaining. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_timer_time_remaining(sl_sleeptimer_timer_handle_t *handle, + uint32_t *time) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + + if (handle == NULL || time == NULL) { + return SL_STATUS_NULL_POINTER; + } + + CORE_ENTER_ATOMIC(); + + update_delta_list(); + *time = handle->delta; + + // Retrieve timer in list and add the deltas. + current = timer_head; + while (current != handle && current != NULL) { + *time += current->delta; + current = current->next; + } + + if (current != handle) { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_NOT_READY; + } + + // Substract time since last compare match. + if (*time > sleeptimer_hal_get_counter() - last_delta_update_count) { + *time -= sleeptimer_hal_get_counter() - last_delta_update_count; + } else { + *time = 0; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/**************************************************************************//** + * Gets the time remaining until the first timer with the matching set of flags + * expires. + *****************************************************************************/ +sl_status_t sl_sleeptimer_get_remaining_time_of_first_timer(uint16_t option_flags, + uint32_t *time_remaining) +{ + CORE_DECLARE_IRQ_STATE; + sl_sleeptimer_timer_handle_t *current; + uint32_t time = 0; + + CORE_ENTER_ATOMIC(); + // parse list and retrieve first timer with option flags requirement. + current = timer_head; + while (current != NULL) { + // save time remaining for timer. + time += current->delta; + // Check if the current timer has the flags requested + if (current->option_flags == option_flags + || option_flags == SL_SLEEPTIMER_ANY_FLAG) { + // Substract time since last compare match. + if (time > (sleeptimer_hal_get_counter() - last_delta_update_count)) { + time -= (sleeptimer_hal_get_counter() - last_delta_update_count); + } else { + time = 0; + } + *time_remaining = time; + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; + } + current = current->next; + } + CORE_EXIT_ATOMIC(); + + return SL_STATUS_EMPTY; +} + +/**************************************************************************//** + * Determines if next timer to expire has the option flag + * "SL_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG". + * + * @note This function is for internal use only. + * + * @note A check to validate that the Power Manager Sleeptimer is expired on + * top of being the next timer was added. This is because + * this function is called when coming back from EM2 sleep to validate + * that the system woke up because of this precise timer expiration. + * Some race conditions, seen with FreeRTOS, could create invalid RTC + * interrupt leading to believe that the power manager timer was expired + * when it was not. + *****************************************************************************/ +bool sli_sleeptimer_is_power_manager_timer_next_to_expire(void) +{ + bool next_timer_is_power_manager; + + sl_atomic_load(next_timer_is_power_manager, next_timer_to_expire_is_power_manager); + + // Make sure that the Power Manager Sleeptimer is actually expired in addition + // to being the next timer. + if ((next_timer_is_power_manager) + && ((sl_sleeptimer_get_tick_count() - timer_head->timeout_expected_tc) > MIN_DIFF_BETWEEN_COUNT_AND_EXPIRATION)) { + next_timer_is_power_manager = false; + } + + return next_timer_is_power_manager; +} + +/***************************************************************************//** +* Gets current 32 bits tick count. +*******************************************************************************/ +uint32_t sl_sleeptimer_get_tick_count(void) +{ + uint32_t cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + cnt = sleeptimer_hal_get_counter(); + CORE_EXIT_ATOMIC(); + + return cnt; +} + +/***************************************************************************//** +* Gets current 64 bits tick count. +*******************************************************************************/ +uint64_t sl_sleeptimer_get_tick_count64(void) +{ + uint32_t tick_cnt; + uint32_t of_cnt; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt = overflow_counter; + + if (sli_sleeptimer_hal_is_int_status_set(SLEEPTIMER_EVENT_OF)) { + tick_cnt = sleeptimer_hal_get_counter(); + of_cnt++; + } + CORE_EXIT_ATOMIC(); + + return (((uint64_t) of_cnt) << 32) | tick_cnt; +} + +/***************************************************************************//** + * Get timer frequency. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_timer_frequency(void) +{ + return timer_frequency; +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/***************************************************************************//** + * Retrieves current 32 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_t sl_sleeptimer_get_time(void) +{ + uint64_t temp_time = sl_sleeptimer_get_time_64(); + // Add offset for 64 to 32 bit time + if (temp_time >= TIME_64_TO_32_EPOCH_OFFSET_SEC) { + temp_time -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + } + // Return lower 32 bits of 64 bit time + uint32_t time = (temp_time & 0xFFFFFFFF); + + return time; +} + +/***************************************************************************//** + * Retrieves current 64 bit time. + ******************************************************************************/ +sl_sleeptimer_timestamp_64_t sl_sleeptimer_get_time_64(void) +{ + uint32_t cnt = 0u; + uint32_t freq = 0u; + sl_sleeptimer_timestamp_64_t time; + CORE_DECLARE_IRQ_STATE; + + cnt = sleeptimer_hal_get_counter(); + freq = sl_sleeptimer_get_timer_frequency(); + + CORE_ENTER_ATOMIC(); + time = second_count + cnt / freq; + + if (cnt % freq + overflow_tick_rest >= freq) { + time++; + } + CORE_EXIT_ATOMIC(); + + return time; +} + +/***************************************************************************//** + * Sets current time from 32 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time(sl_sleeptimer_timestamp_t time) +{ + // convert 32 bit time to 64 bit time + uint64_t temp_time = time + TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_set_time_64(temp_time); + return err_code; +} + +/***************************************************************************//** + * Sets current time from 64 bit variable. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_time_64(sl_sleeptimer_timestamp_64_t time) +{ + uint32_t freq = 0u; + uint32_t counter_sec = 0u; + uint32_t cnt = 0; + CORE_DECLARE_IRQ_STATE; + + // convert 64 bit time to 32 bit time + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } + + freq = sl_sleeptimer_get_timer_frequency(); + cnt = sleeptimer_hal_get_counter(); + + CORE_ENTER_ATOMIC(); + // store 64 bit time as 64 bits's + second_count = time; + + // Convert 64 bit time to 32 bit time in order to check for overflow + // i.e. if 32 bit time is >=counter_sec + uint64_t temp_time = second_count - TIME_64_TO_32_EPOCH_OFFSET_SEC; + uint32_t second_time_32 = (temp_time & 0xFFFFFFFF); + + overflow_tick_rest = 0; + counter_sec = cnt / freq; + + if (second_time_32 >= counter_sec) { + second_count -= counter_sec; + } else { + CORE_EXIT_ATOMIC(); + + return SL_STATUS_INVALID_PARAMETER; + } + + CORE_EXIT_ATOMIC(); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Gets current date. + ******************************************************************************/ +sl_status_t sl_sleeptimer_get_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_sleeptimer_time_zone_offset_t tz; + sl_status_t err_code = SL_STATUS_OK; + + // Fetch 64 bit timestamp + time = sl_sleeptimer_get_time_64(); + tz = sl_sleeptimer_get_tz(); + err_code = sl_sleeptimer_convert_time_to_date_64(time, tz, date); + + return err_code; +} + +/***************************************************************************//** + * Sets current time, in date format. + ******************************************************************************/ +sl_status_t sl_sleeptimer_set_datetime(sl_sleeptimer_date_t *date) +{ + sl_sleeptimer_timestamp_64_t time = 0u; + sl_status_t err_code = SL_STATUS_OK; + CORE_DECLARE_IRQ_STATE; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + err_code = sl_sleeptimer_convert_date_to_time_64(date, &time); + if (err_code != SL_STATUS_OK) { + return err_code; + } + + CORE_ENTER_ATOMIC(); + // sets the 64 bit second_time value + err_code = sl_sleeptimer_set_time_64(time); + if (err_code == SL_STATUS_OK) { + sl_sleeptimer_set_tz(date->time_zone); + } + CORE_EXIT_ATOMIC(); + + return err_code; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // If year is smaller than 1900, assume NTP Epoch is used. + date->year = ((year < TIME_NTP_EPOCH) ? year : (year - TIME_NTP_EPOCH)); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week(((date->year - TIME_NTP_UNIX_EPOCH_DIFF) * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_UNIX_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/***************************************************************************//** + * Builds a date time structure based on the provided parameters. + ******************************************************************************/ +sl_status_t sl_sleeptimer_build_datetime_64(sl_sleeptimer_date_t *date, + uint16_t year, + sl_sleeptimer_month_t month, + uint8_t month_day, + uint8_t hour, + uint8_t min, + uint8_t sec, + sl_sleeptimer_time_zone_offset_t tz_offset) +{ + if (date == NULL) { + return SL_STATUS_NULL_POINTER; + } + + // Ensure that year is greater than 1900 and based on 0 epoch + if (year < TIME_NTP_EPOCH) { + return SL_STATUS_INVALID_PARAMETER; + } + + // Convert year based on 0 epoch to a valid date->year based on 1900 epoch + date->year = (year - TIME_NTP_EPOCH); + date->month = month; + date->month_day = month_day; + date->hour = hour; + date->min = min; + date->sec = sec; + date->time_zone = tz_offset; + + // Validate that input parameters are correct before filing the missing fields + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + date->day_of_year = compute_day_of_year(date->month, date->month_day, is_leap_year(date->year)); + date->day_of_week = compute_day_of_week_64((date->year * TIME_DAY_PER_YEAR) + + number_of_leap_days(TIME_NTP_EPOCH, (date->year + TIME_NTP_EPOCH)) + + date->day_of_year - 1); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a 32 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + // convert 32 bit timestamp to 64 bit + sl_sleeptimer_timestamp_64_t temp_time = (uint64_t)time + TIME_64_TO_32_EPOCH_OFFSET_SEC; + sl_status_t err_code = sl_sleeptimer_convert_time_to_date_64(temp_time, time_zone, date); + return err_code; +} + +/******************************************************************************* + * Convert a 64 bit time stamp into a date structure. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_time_to_date_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_zone_offset_t time_zone, + sl_sleeptimer_date_t *date) +{ + uint16_t full_year = 0; + uint16_t leap_day = 0; + uint8_t leap_year_flag = 0; + uint8_t current_month = 0; + + if (!is_valid_time_64(time, TIME_FORMAT_UNIX_64_BIT, time_zone)) { + return SL_STATUS_INVALID_PARAMETER; + } + + time += time_zone; // add UTC offset to convert to Standard Time + date->sec = time % 60; + time /= 60; + date->min = time % 60; + time /= 60; + date->hour = time % 24; + time /= 24; // time is now the number of days since 1900 + + date->day_of_week = (sl_sleeptimer_weekDay_t)compute_day_of_week_64(time); + + full_year = time / TIME_DAY_PER_YEAR; // Approximates the number of full years + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_day = number_of_leap_days(base_year, current_year); // Approximates the number of leap days. + full_year = (time - leap_day) / TIME_DAY_PER_YEAR; // Computes the number of year integrating the leap days. + current_year = full_year + base_year; + leap_day = number_of_leap_days(base_year, current_year); // Computes the actual number of leap days of the previous years. + } + date->year = full_year; // Year in date struct must be based on a 1900 epoch. + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + time = (time - leap_day) - (TIME_DAY_PER_YEAR * full_year); // Subtracts days of previous year. + date->day_of_year = time + 1; + + while (time >= days_in_month[leap_year_flag][current_month]) { + time -= days_in_month[leap_year_flag][current_month]; // Subtracts the number of days of the passed month. + current_month++; + } + date->month = (sl_sleeptimer_month_t)current_month; + date->month_day = time + 1; + date->time_zone = time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure into a 32 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_t *time) +{ + // Create a 64 bit time stamp + sl_sleeptimer_timestamp_64_t temp_time = 0; + sl_status_t err_code = sl_sleeptimer_convert_date_to_time_64(date, &temp_time); + + if (err_code != SL_STATUS_OK) { + return err_code; + } + // Convert 64 bit time to 32 bit time + + sl_sleeptimer_timestamp_64_t time_32 = temp_time; + time_32 -= TIME_64_TO_32_EPOCH_OFFSET_SEC; + *time = (time_32 & 0xFFFFFFFF); + + return err_code; +} + +/******************************************************************************* + * Convert a date structure into a 64 bit time stamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_date_to_time_64(sl_sleeptimer_date_t *date, + sl_sleeptimer_timestamp_64_t *time) +{ + uint16_t month_days = 0; + uint8_t month; + uint16_t full_year = 0; + uint8_t leap_year_flag = 0; + uint16_t leap_days = 0; + + if (!is_valid_date_64(date)) { + return SL_STATUS_INVALID_PARAMETER; + } + + full_year = (date->year); // base year for 64 bits its 1900 not 1970 + month = date->month; // offset to get months value from 1 to 12. + + uint32_t base_year = 1900u; + uint32_t current_year = full_year + base_year; + + *time = (full_year * (uint64_t)TIME_SEC_PER_YEAR); + + if (full_year > 4) { // 1904 is the first leap year since 1900 + leap_days = number_of_leap_days(base_year, current_year); + month_days = leap_days; + } + + if (is_leap_year(date->year)) { + leap_year_flag = 1; + } + + for (int i = 0; i < month; i++) { + month_days += days_in_month[leap_year_flag][i]; // Add the number of days of the month of the year. + } + + month_days += (date->month_day - 1); // Add full days of the current month. + *time += month_days * TIME_SEC_PER_DAY; + *time += (3600 * date->hour) + (60 * date->min) + date->sec; + *time -= date->time_zone; + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Convert a date structure to string. + ******************************************************************************/ +uint32_t sl_sleeptimer_convert_date_to_str(char *str, + size_t size, + const uint8_t *format, + sl_sleeptimer_date_t *date) +{ + uint32_t return_size = 0u; + if (is_valid_date(date)) { + struct tm date_struct; + + date_struct.tm_hour = date->hour; + date_struct.tm_mday = date->month_day; + date_struct.tm_min = date->min; + date_struct.tm_mon = date->month; + date_struct.tm_sec = date->sec; + date_struct.tm_wday = date->day_of_week; + date_struct.tm_yday = date->day_of_year; + date_struct.tm_year = date->year; + + return_size = strftime(str, + size, + (const char *)format, + &date_struct); + } + + return return_size; +} + +/***************************************************************************//** + * Sets time zone offset. + * + * @param offset Time zone offset, in seconds. + ******************************************************************************/ +void sl_sleeptimer_set_tz(sl_sleeptimer_time_zone_offset_t offset) +{ + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + tz_offset = offset; + CORE_EXIT_ATOMIC(); +} + +/***************************************************************************//** + * Gets time zone offset. + * + * @return Time zone offset, in seconds. + ******************************************************************************/ +sl_sleeptimer_time_zone_offset_t sl_sleeptimer_get_tz(void) +{ + sl_sleeptimer_time_zone_offset_t offset; + CORE_DECLARE_IRQ_STATE; + + CORE_ENTER_ATOMIC(); + offset = tz_offset; + CORE_EXIT_ATOMIC(); + + return offset; +} + +/***************************************************************************//** + * Converts Unix 32 timestamp into NTP timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_ntp(sl_sleeptimer_timestamp_t time, + uint32_t *ntp_time) +{ + if (time > TIME_UNIX_TO_NTP_MAX) { + // Maximum Unix timestamp that can be converted to NTP is 2085978495 + return SL_STATUS_INVALID_PARAMETER; + } + + uint32_t temp_ntp_time; + temp_ntp_time = time + TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_ntp_time, TIME_FORMAT_NTP, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *ntp_time = temp_ntp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts NTP timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_ntp_time_to_unix(uint32_t ntp_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = ntp_time - TIME_NTP_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Unix timestamp into Zigbee timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_unix_time_to_zigbee(sl_sleeptimer_timestamp_t time, + uint32_t *zigbee_time) +{ + uint32_t temp_zigbee_time; + temp_zigbee_time = time - TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_zigbee_time, TIME_FORMAT_ZIGBEE_CLUSTER, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *zigbee_time = temp_zigbee_time; + return SL_STATUS_OK; + } +} + +/***************************************************************************//** + * Converts Zigbee timestamp into Unix timestamp. + ******************************************************************************/ +sl_status_t sl_sleeptimer_convert_zigbee_time_to_unix(uint32_t zigbee_time, + sl_sleeptimer_timestamp_t *time) +{ + uint32_t temp_time; + temp_time = zigbee_time + TIME_ZIGBEE_EPOCH_OFFSET_SEC; + if (!is_valid_time(temp_time, TIME_FORMAT_UNIX, 0u)) { + return SL_STATUS_INVALID_PARAMETER; + } else { + *time = temp_time; + return SL_STATUS_OK; + } +} + +#endif // SL_SLEEPTIMER_WALLCLOCK_CONFIG + +/******************************************************************************* + * Active delay of 'time_ms' milliseconds. + ******************************************************************************/ +void sl_sleeptimer_delay_millisecond(uint16_t time_ms) +{ + volatile bool wait = true; + sl_status_t error_code; + sl_sleeptimer_timer_handle_t delay_timer; + uint32_t delay = sl_sleeptimer_ms_to_tick(time_ms); + + error_code = sl_sleeptimer_start_timer(&delay_timer, + delay, + delay_callback, + (void *)&wait, + 0, + 0); + if (error_code == SL_STATUS_OK) { + while (wait) { // Active delay loop. + } + } +} + +/******************************************************************************* + * Converts milliseconds in ticks. + ******************************************************************************/ +uint32_t sl_sleeptimer_ms_to_tick(uint16_t time_ms) +{ + return (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000); +} + +/******************************************************************************* + * Converts 32-bits milliseconds in ticks. + ******************************************************************************/ +sl_status_t sl_sleeptimer_ms32_to_tick(uint32_t time_ms, + uint32_t *tick) +{ + if (time_ms <= max_millisecond_conversion) { + *tick = (uint32_t)((((uint64_t)time_ms * timer_frequency) + 999) / 1000u); + return SL_STATUS_OK; + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/***************************************************************************//** + * Gets the maximum value that can be passed to the functions that have a + * 32-bits time or timeout argument expressed in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_get_max_ms32_conversion(void) +{ + return max_millisecond_conversion; +} + +/******************************************************************************* + * Converts ticks in milliseconds. + ******************************************************************************/ +uint32_t sl_sleeptimer_tick_to_ms(uint32_t tick) +{ + uint32_t time_ms; + time_ms = 0; + + if (timer_frequency != 0u) { + if (is_power_of_2(timer_frequency)) { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + } else { + time_ms = (uint32_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + } + } + + return time_ms; +} + +/******************************************************************************* + * Converts 64-bits ticks in milliseconds. + ******************************************************************************/ +sl_status_t sl_sleeptimer_tick64_to_ms(uint64_t tick, + uint64_t *ms) + +{ + if ((tick <= UINT64_MAX / 1000) + && (timer_frequency != 0u)) { + if (is_power_of_2(timer_frequency)) { + *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) >> div_to_log2(timer_frequency)); + return SL_STATUS_OK; + } else { + *ms = (uint64_t)(((uint64_t)tick * (uint64_t)1000u) / timer_frequency); + return SL_STATUS_OK; + } + } else { + return SL_STATUS_INVALID_PARAMETER; + } +} + +/******************************************************************************* + * Process timer interrupt. + * + * @param local_flag Flag indicating the type of timer interrupt. + ******************************************************************************/ +void process_timer_irq(uint8_t local_flag) +{ + CORE_DECLARE_IRQ_STATE; + if (local_flag & SLEEPTIMER_EVENT_OF) { +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG + uint32_t timer_freq = sl_sleeptimer_get_timer_frequency(); + + overflow_tick_rest += calculated_tick_rest; + if (overflow_tick_rest >= timer_freq) { + second_count++; + overflow_tick_rest -= timer_freq; + } + second_count = second_count + calculated_sec_count; +#endif + overflow_counter++; + + update_delta_list(); + + if (timer_head) { + set_comparator_for_next_timer(); + } + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + sl_sleeptimer_timer_handle_t *current = NULL; + + uint32_t nb_timer_expire = 0u; + uint16_t option_flags = 0; + + CORE_ENTER_ATOMIC(); + // Make sure the timers list is up to date with the time elapsed since the last update + update_delta_list(); + + // Process all timers that have expired. + while ((timer_head) && (timer_head->delta == 0)) { + sl_sleeptimer_timer_handle_t *temp = timer_head; + current = timer_head; + int32_t periodic_correction = 0u; + int64_t timeout_temp = 0; + bool skip_remove = false; + + // Process timers with higher priority first + while ((temp != NULL) && (temp->delta == 0)) { + if (current->priority > temp->priority) { + current = temp; + } + temp = temp->next; + } + CORE_EXIT_ATOMIC(); + + // Check if current periodic timer was delayed more than its actual timeout value + // and keep it at the head of the timers list if it's the case so that the + // callback function can be called the number of required time. + if (current->timeout_periodic != 0u) { + timeout_temp = current->timeout_periodic; + + periodic_correction = sleeptimer_hal_get_counter() - current->timeout_expected_tc; + if (periodic_correction > timeout_temp) { + skip_remove = true; + current->timeout_expected_tc += current->timeout_periodic; + } + } + + // Remove current timer from timer list except if the current timer is a periodic timer + // that was intentionally kept at the head of the timers list. + if (skip_remove != true) { + CORE_ENTER_ATOMIC(); + delta_list_remove_timer(current); + CORE_EXIT_ATOMIC(); + } + + // Re-insert periodic timer that was previsouly removed from the list + // and compensate for any deviation from the periodic timer frequency. + if (current->timeout_periodic != 0u && skip_remove != true) { + timeout_temp -= periodic_correction; + EFM_ASSERT(timeout_temp >= 0); + // Compensate for drift caused by ms to ticks conversion + if (current->conversion_error > 0) { + // Increment accumulated error by the ms to ticks conversion error + current->accumulated_error += current->conversion_error; + // If the accumulated error exceeds a tick, subtract that tick from the next + // periodic timer's timeout value. + if (current->accumulated_error >= 1000) { + current->accumulated_error -= 1000; + timeout_temp -= 1; + current->timeout_expected_tc -= 1; + } + } + CORE_ENTER_ATOMIC(); + delta_list_insert_timer(current, (sl_sleeptimer_tick_count_t)timeout_temp); + current->timeout_expected_tc += current->timeout_periodic; + CORE_EXIT_ATOMIC(); + } + + // Save current option flag and the number of timers that expired. + option_flags = current->option_flags; + nb_timer_expire++; + + // Call current timer callback function if any. + if (current->callback != NULL) { + current->callback(current, current->callback_data); + } + + CORE_ENTER_ATOMIC(); + + // Re-update the list to account for delays during timer's callback. + update_delta_list(); + } + + // If the only timer expired is the internal Power Manager one, + // from the Sleeptimer perspective, the system can go back to sleep after the ISR handling. + sleep_on_isr_exit = false; + if (nb_timer_expire == 1u) { + if (option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { + sleep_on_isr_exit = true; + } + } + + if (timer_head) { + set_comparator_for_next_timer(); + } else { + sleeptimer_hal_disable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_ATOMIC(); + } +} + +/******************************************************************************* + * Timer expiration callback for the delay function. + * + * @param handle Pointer to handle to timer. + * @param data Pointer to delay flag. + ******************************************************************************/ +static void delay_callback(sl_sleeptimer_timer_handle_t *handle, + void *data) +{ + volatile bool *wait_flag = (bool *)data; + + (void)handle; // Unused parameter. + + *wait_flag = false; +} + +/******************************************************************************* + * Inserts a timer in the delta list. + * + * @param handle Pointer to handle to timer. + * @param timeout Timer timeout, in ticks. + ******************************************************************************/ +static void delta_list_insert_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout) +{ + sl_sleeptimer_tick_count_t local_handle_delta = timeout; + +#ifdef SL_CATALOG_POWER_MANAGER_PRESENT + // If Power Manager is present, it's possible that a clock restore is needed right away + // if we are in the context of a deepsleep and the timeout value is smaller than the restore time. + // If it's the case, the restore will be started and the timeout value will be updated to match + // the restore delay. + if (handle->option_flags == 0) { + uint32_t wakeup_delay = sli_power_manager_get_restore_delay(); + + if (local_handle_delta < wakeup_delay) { + local_handle_delta = wakeup_delay; + sli_power_manager_initiate_restore(); + } + } +#endif + + handle->delta = local_handle_delta; + + if (timer_head != NULL) { + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + // Find timer position taking into accounts the deltas and priority. + while (current != NULL + && (local_handle_delta >= current->delta || current->delta == 0u + || (((local_handle_delta - current->delta) == 0) && (handle->priority > current->priority)))) { + local_handle_delta -= current->delta; + handle->delta = local_handle_delta; + prev = current; + current = current->next; + } + + // Insert timer in middle of delta list. + if (prev != NULL) { + prev->next = handle; + } else { + timer_head = handle; + } + handle->next = current; + + if (current != NULL) { + current->delta -= local_handle_delta; + } + } else { + timer_head = handle; + handle->next = NULL; + } +} + +/******************************************************************************* + * Removes a timer from delta list. + * + * @param handle Pointer to handle to timer. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t delta_list_remove_timer(sl_sleeptimer_timer_handle_t *handle) +{ + sl_sleeptimer_timer_handle_t *prev = NULL; + sl_sleeptimer_timer_handle_t *current = timer_head; + + // Retrieve timer in delta list. + while (current != NULL && current != handle) { + prev = current; + current = current->next; + } + + if (current != handle) { + return SL_STATUS_INVALID_STATE; + } + + if (prev != NULL) { + prev->next = handle->next; + } else { + timer_head = handle->next; + } + + // Update delta of next timer + if (handle->next != NULL) { + handle->next->delta += handle->delta; + } + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Sets comparator for next timer. + ******************************************************************************/ +static void set_comparator_for_next_timer(void) +{ + if (timer_head->delta > 0) { + sl_sleeptimer_tick_count_t compare_value; + + compare_value = last_delta_update_count + timer_head->delta; + + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_compare(compare_value); + } else { + // In case timer has already expire, don't attempt to set comparator. Just + // trigger compare match interrupt. + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + sleeptimer_hal_set_int(SLEEPTIMER_EVENT_COMP); + } + + update_next_timer_to_expire_is_power_manager(); +} + +/******************************************************************************* + * Updates timer list's deltas. + ******************************************************************************/ +static void update_delta_list(void) +{ + sl_sleeptimer_tick_count_t current_cnt = sleeptimer_hal_get_counter(); + sl_sleeptimer_timer_handle_t *timer_handle = timer_head; + sl_sleeptimer_tick_count_t time_diff = current_cnt - last_delta_update_count; + + // Go through the delta timer list and update every necessary deltas + // according to the time elapsed since the last update. + while (timer_handle != NULL && time_diff > 0) { + if (timer_handle->delta >= time_diff) { + timer_handle->delta -= time_diff; + time_diff = 0; + } else { + time_diff -= timer_handle->delta; + timer_handle->delta = 0; + } + timer_handle = timer_handle->next; + } + + last_delta_update_count = current_cnt; +} + +/******************************************************************************* + * Creates and start a 32 bits timer. + * + * @param handle Pointer to handle to timer. + * @param timeout_initial Initial timeout, in timer ticks. + * @param timeout_periodic Periodic timeout, in timer ticks. This timeout + * applies once timeoutInitial expires. Can be set to 0 for a one + * shot timer. + * @param callback Callback function that will be called when + * initial/periodic timeout expires. + * @param callback_data Pointer to user data that will be passed to callback. + * @param priority Priority of callback. Useful in case multiple timer expire + * at the same time. 0 = highest priority. + * + * @return 0 if successful. Error code otherwise. + ******************************************************************************/ +static sl_status_t create_timer(sl_sleeptimer_timer_handle_t *handle, + sl_sleeptimer_tick_count_t timeout_initial, + sl_sleeptimer_tick_count_t timeout_periodic, + sl_sleeptimer_timer_callback_t callback, + void *callback_data, + uint8_t priority, + uint16_t option_flags) +{ + CORE_DECLARE_IRQ_STATE; + + handle->priority = priority; + handle->callback_data = callback_data; + handle->next = NULL; + handle->timeout_periodic = timeout_periodic; + handle->callback = callback; + handle->option_flags = option_flags; + if (timeout_periodic == 0) { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_initial; + } else { + handle->timeout_expected_tc = sleeptimer_hal_get_counter() + timeout_periodic; + } + + if (timeout_initial == 0) { + handle->delta = 0; + if (handle->callback != NULL) { + handle->callback(handle, handle->callback_data); + } + if (timeout_periodic != 0) { + timeout_initial = timeout_periodic; + } else { + return SL_STATUS_OK; + } + } + +#if ((SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_SYSRTC) \ + && defined(SL_CATALOG_POWER_MANAGER_PRESENT) \ + && !defined(SL_CATALOG_POWER_MANAGER_NO_DEEPSLEEP_PRESENT)) + if (option_flags == (SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG | SLI_SLEEPTIMER_POWER_MANAGER_HF_ACCURACY_CLK_FLAG)) { + HFXO0->CTRL |= HFXO_CTRL_EM23ONDEMAND; + sleeptimer_hal_set_compare_prs_hfxo_startup(timeout_initial); + return SL_STATUS_OK; + } +#endif + + CORE_ENTER_CRITICAL(); + update_delta_list(); + delta_list_insert_timer(handle, timeout_initial); + + // If first timer, update timer comparator. + if (timer_head == handle) { + set_comparator_for_next_timer(); + } + + CORE_EXIT_CRITICAL(); + + return SL_STATUS_OK; +} + +/******************************************************************************* + * Updates internal flag that indicates if next timer to expire is the power + * manager's one. + ******************************************************************************/ +static void update_next_timer_to_expire_is_power_manager(void) +{ + sl_sleeptimer_timer_handle_t *current = timer_head; + uint32_t delta_diff_with_first = 0; + + next_timer_to_expire_is_power_manager = false; + + while (delta_diff_with_first <= 1) { + if (current->option_flags & SLI_SLEEPTIMER_POWER_MANAGER_EARLY_WAKEUP_TIMER_FLAG) { + next_timer_to_expire_is_power_manager = true; + break; + } + + current = current->next; + if (current == NULL) { + break; + } + + delta_diff_with_first += current->delta; + } +} + +/**************************************************************************//** + * Determines if the power manager's early wakeup expired during the last ISR + * and it was the only timer to expire in that period. + * + * @return true if power manager sleep can return to sleep, + * false otherwise. + *****************************************************************************/ +bool sl_sleeptimer_is_power_manager_early_restore_timer_latest_to_expire(void) +{ + CORE_DECLARE_IRQ_STATE; + bool sleep; + + CORE_ENTER_ATOMIC(); + sleep = sleep_on_isr_exit; + CORE_EXIT_ATOMIC(); + + return sleep; +} + +/******************************************************************************* + * Convert dividend to logarithmic value. It only works for even + * numbers equal to 2^n. + * + * @param div An unscaled dividend. + * + * @return Logarithm of 2. + ******************************************************************************/ +__STATIC_INLINE uint32_t div_to_log2(uint32_t div) +{ + return 31UL - __CLZ(div); // Count leading zeroes and "reverse" result. +} + +/******************************************************************************* + * Determines if a number is a power of two. + * + * @param nbr Input value. + * + * @return True if the number is a power of two. + ******************************************************************************/ +__STATIC_INLINE bool is_power_of_2(uint32_t nbr) +{ + if ((((nbr) != 0u) && (((nbr) & ((nbr) - 1u)) == 0u))) { + return true; + } else { + return false; + } +} + +#if SL_SLEEPTIMER_WALLCLOCK_CONFIG +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1970. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week(uint32_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 4) % 7); // January 1st was a Thursday(4) in 1970 +} + +/******************************************************************************* + * Compute the day of the week. + * + * @param day Days since January 1st of 1900. + * + * @return the day of the week. + ******************************************************************************/ +static sl_sleeptimer_weekDay_t compute_day_of_week_64(uint64_t day) +{ + return (sl_sleeptimer_weekDay_t)((day + 1) % 7); // January 1st was a Monday(1) in 1900 +} + +/******************************************************************************* + * Compute the day of the year. This function assumes that the inputs are properly + * sanitized. + * + * @param month Number of months since January. + * @param day Day of the month + * @param is_leap_year Specifies if the year computed against is a leap year. + * + * @return the number of days since the beginning of the year + ******************************************************************************/ +static uint16_t compute_day_of_year(sl_sleeptimer_month_t month, uint8_t day, bool is_leap_year) +{ + uint8_t i; + uint16_t dayOfYear = 0; + + for (i = 0; i < month; ++i) { + dayOfYear += days_in_month[is_leap_year][i]; + } + dayOfYear += day; + + return dayOfYear; +} + +/******************************************************************************* + * Checks if the year is a leap year. + * + * @param year Year to check. + * + * @return true if the year is a leap year. False otherwise. + ******************************************************************************/ +static bool is_leap_year(uint16_t year) +{ + // 1900 is not a leap year but 0 % anything is 0. + if (year == 0) { + return false; + } + + bool leap_year; + + leap_year = (((year % 4u) == 0u) + && (((year % 100u) != 0u) || ((year % 400u) == 0u))) ? true : false; + + return (leap_year); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param base_year Year to start from to compute leap days. + * @param current_year Year end at for computing leap days. + * + * @return leap_days Days number of leap days between base_year and current_year. + ******************************************************************************/ +static uint16_t number_of_leap_days(uint32_t base_year, uint32_t current_year) +{ + // Regular leap years + uint16_t lo_reg = (base_year - 0) / 4; + uint16_t hi_reg = (current_year - 1) / 4; + uint16_t leap_days = hi_reg - lo_reg; + + // Account for non leap years + uint16_t lo_century = (base_year - 0) / 100; + uint16_t hi_century = (current_year - 1) / 100; + leap_days -= hi_century - lo_century; + + // Account for quad century leap years + uint16_t lo_quad = (base_year - 0) / 400; + uint16_t hi_quad = (current_year - 1) / 400; + leap_days += hi_quad - lo_quad; + + return (leap_days); +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time(sl_sleeptimer_timestamp_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint32_t)abs(time_zone)) \ + || (time_zone >= 0 && (time <= UINT32_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX) { + if (time > TIME_UNIX_TIMESTAMP_MAX) { // Check if Unix time stamp is an unsigned 31 bits. + valid_time = false; + } + } else { + if ((format == TIME_FORMAT_NTP) && (time >= TIME_NTP_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else if ((format == TIME_FORMAT_ZIGBEE_CLUSTER) && (time <= TIME_UNIX_TIMESTAMP_MAX - TIME_ZIGBEE_EPOCH_OFFSET_SEC)) { + valid_time &= true; + } else { + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the time stamp, format and time zone are + * within the supported range. + * + * @param time Time stamp to check. + * @param format Format of the time. + * @param time_zone Time zone offset in second. + * + * @return true if the time is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_time_64(sl_sleeptimer_timestamp_64_t time, + sl_sleeptimer_time_format_t format, + sl_sleeptimer_time_zone_offset_t time_zone) +{ + bool valid_time = false; + + // Check for overflow. + if ((time_zone < 0 && time > (uint64_t)abs(time_zone)) + || (time_zone >= 0 && (time <= UINT64_MAX - time_zone))) { + valid_time = true; + } + if (format == TIME_FORMAT_UNIX_64_BIT) { + if (time > TIME_64_BIT_UNIX_TIMESTAMP_MAX) { // Check if time stamp is an unsigned 64 bits. + valid_time = false; + } + } + return valid_time; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_UNIX_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + + // Unix is valid until the 19th of January 2038 at 03:14:07 + if (date->year == TIME_UNIX_YEAR_MAX) { + if ((uint8_t)date->month > (uint8_t)MONTH_JANUARY) { + return false; + } else if (date->month_day > 19) { + return false; + } else if (date->hour > 3) { + return false; + } else if (date->min > 14) { + return false; + } else if (date->sec > 7) { + return false; + } + } + + return true; +} + +/******************************************************************************* + * Checks if the date is valid. + * + * @param date Date to check. + * + * @return true if the date is valid. False otherwise. + ******************************************************************************/ +static bool is_valid_date_64(sl_sleeptimer_date_t *date) +{ + if ((date == NULL) + || (date->year > TIME_64_BIT_YEAR_MAX) + || (date->month > MONTH_DECEMBER) + || (date->month_day == 0 || date->month_day > days_in_month[is_leap_year(date->year)][date->month]) + || (date->hour > 23) + || (date->min > 59) + || (date->sec > 59)) { + return false; + } + return true; +} +#endif + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sl_sleeptimer_get_clock_accuracy(void) +{ + return sleeptimer_hal_get_clock_accuracy(); +} + +/***************************************************************************//** + * @brief + * Update sleep_on_isr_exit flag. + * + * @param flag Value update_sleep_on_isr_exit will be set to. + ******************************************************************************/ +void sli_sleeptimer_update_sleep_on_isr_exit(bool flag) +{ + sleep_on_isr_exit = flag; +} + +/******************************************************************************* + * Gets the associated peripheral capture channel current value. + ******************************************************************************/ +uint32_t sli_sleeptimer_get_capture(void) +{ + return sleeptimer_hal_get_capture(); +} + +/******************************************************************************* + * Resets the PRS signal triggered by the associated peripheral. + ******************************************************************************/ +void sli_sleeptimer_reset_prs_signal(void) +{ + sleeptimer_hal_reset_prs_signal(); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c index a2435f4..6ea3a09 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c @@ -1,325 +1,325 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER Hardware abstraction implementation for BURTC. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_device.h" -#if defined(_SILICON_LABS_32B_SERIES_2) - -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_burtc.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_BURTC - -#if defined(_SILICON_LABS_32B_SERIES_0) -#error BURTC implementation of the sleeptimer not available on Series 0 chips -#endif - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) -#define SLEEPTIMER_COMPARE_MIN_DIFF (5 + 1) -#else -#define SLEEPTIMER_COMPARE_MIN_DIFF (4 + 1) -#endif - -#define SLEEPTIMER_TMR_WIDTH (_BURTC_CNT_MASK) - -static uint32_t get_time_diff(uint32_t a, uint32_t b); - -/****************************************************************************** - * Convert HAL interrupt flag BURTC-interrupt-enable bitmask - *****************************************************************************/ -static uint32_t irqien_hal2burtc(uint8_t hal_flag) -{ - uint32_t burtc_if = 0u; - - if (hal_flag & SLEEPTIMER_EVENT_OF) { - burtc_if |= BURTC_IEN_OF; - } - - if (hal_flag & SLEEPTIMER_EVENT_COMP) { - burtc_if |= BURTC_IEN_COMP; - } - - return burtc_if; -} - -/****************************************************************************** - * Convert BURTC interrupt flags to HAL events - *****************************************************************************/ -static uint8_t irqflags_burtc2hal(uint32_t burtc_flag) -{ - uint8_t hal_if = 0u; - - if (burtc_flag & BURTC_IF_OF) { - hal_if |= SLEEPTIMER_EVENT_OF; - } - - if (burtc_flag & BURTC_IF_COMP) { - hal_if |= SLEEPTIMER_EVENT_COMP; - } - - return hal_if; -} - -/****************************************************************************** - * Initializes BURTC sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer() -{ - BURTC_Init_TypeDef burtc_init = BURTC_INIT_DEFAULT; - - CMU_ClockEnable(cmuClock_BURTC, true); - - burtc_init.start = false; - burtc_init.clkDiv = SL_SLEEPTIMER_FREQ_DIVIDER; -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - burtc_init.debugRun = true; -#endif - - BURTC_Init(&burtc_init); - BURTC_IntDisable(_BURTC_IEN_MASK); - BURTC_IntClear(_BURTC_IF_MASK); - BURTC_CounterReset(); - - BURTC_Start(); - BURTC_SyncWait(); - - // Setup BURTC interrupt - NVIC_ClearPendingIRQ(BURTC_IRQn); - NVIC_EnableIRQ(BURTC_IRQn); -} - -/****************************************************************************** - * Gets BURTC counter. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return BURTC_CounterGet(); -} - -/****************************************************************************** - * Gets BURTC compare value - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return BURTC_CompareGet(0U); -} - -/****************************************************************************** - * Sets BURTC compare value - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the BURTC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare_current; - uint32_t compare_new = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare_current = sleeptimer_hal_get_compare(); - - if (((BURTC_IntGet() & _BURTC_IF_COMP_MASK) != 0) - || get_time_diff(compare_current, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare_current == counter) { - // Add margin if necessary - if (get_time_diff(compare_new, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_new = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - - // wrap around if necessary - compare_new %= SLEEPTIMER_TMR_WIDTH; - - BURTC_CompareSet(0U, compare_new - 1); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_CRITICAL(); -} - -/****************************************************************************** - * Enables BURTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - BURTC_IntEnable(irqien_hal2burtc(local_flag)); -} - -/****************************************************************************** - * Disables BURTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - BURTC_IntDisable(irqien_hal2burtc(local_flag)); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - BURTC_IntSet(irqien_hal2burtc(local_flag)); -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = BURTC_IntGet(); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = (irq_flag & BURTC_IF_COMP); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = (irq_flag & BURTC_IF_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * Gets BURTC timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - return (CMU_ClockFreqGet(cmuClock_BURTC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); -} - -/******************************************************************************* - * BURTC interrupt handler. - ******************************************************************************/ -void BURTC_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = BURTC_IntGet(); - local_flag = irqflags_burtc2hal(irq_flag); - - BURTC_IntClear(irq_flag & (BURTC_IF_OF | BURTC_IF_COMP)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -static uint32_t get_time_diff(uint32_t a, uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ - return CMU_LF_ClockPrecisionGet(cmuClock_BURTC); -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for BURTC peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for BURTC peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ - switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { - case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: - case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -} -#endif -#endif - -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER Hardware abstraction implementation for BURTC. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_device.h" +#if defined(_SILICON_LABS_32B_SERIES_2) + +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_burtc.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_BURTC + +#if defined(_SILICON_LABS_32B_SERIES_0) +#error BURTC implementation of the sleeptimer not available on Series 0 chips +#endif + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8) +#define SLEEPTIMER_COMPARE_MIN_DIFF (5 + 1) +#else +#define SLEEPTIMER_COMPARE_MIN_DIFF (4 + 1) +#endif + +#define SLEEPTIMER_TMR_WIDTH (_BURTC_CNT_MASK) + +static uint32_t get_time_diff(uint32_t a, uint32_t b); + +/****************************************************************************** + * Convert HAL interrupt flag BURTC-interrupt-enable bitmask + *****************************************************************************/ +static uint32_t irqien_hal2burtc(uint8_t hal_flag) +{ + uint32_t burtc_if = 0u; + + if (hal_flag & SLEEPTIMER_EVENT_OF) { + burtc_if |= BURTC_IEN_OF; + } + + if (hal_flag & SLEEPTIMER_EVENT_COMP) { + burtc_if |= BURTC_IEN_COMP; + } + + return burtc_if; +} + +/****************************************************************************** + * Convert BURTC interrupt flags to HAL events + *****************************************************************************/ +static uint8_t irqflags_burtc2hal(uint32_t burtc_flag) +{ + uint8_t hal_if = 0u; + + if (burtc_flag & BURTC_IF_OF) { + hal_if |= SLEEPTIMER_EVENT_OF; + } + + if (burtc_flag & BURTC_IF_COMP) { + hal_if |= SLEEPTIMER_EVENT_COMP; + } + + return hal_if; +} + +/****************************************************************************** + * Initializes BURTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer() +{ + BURTC_Init_TypeDef burtc_init = BURTC_INIT_DEFAULT; + + CMU_ClockEnable(cmuClock_BURTC, true); + + burtc_init.start = false; + burtc_init.clkDiv = SL_SLEEPTIMER_FREQ_DIVIDER; +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + burtc_init.debugRun = true; +#endif + + BURTC_Init(&burtc_init); + BURTC_IntDisable(_BURTC_IEN_MASK); + BURTC_IntClear(_BURTC_IF_MASK); + BURTC_CounterReset(); + + BURTC_Start(); + BURTC_SyncWait(); + + // Setup BURTC interrupt + NVIC_ClearPendingIRQ(BURTC_IRQn); + NVIC_EnableIRQ(BURTC_IRQn); +} + +/****************************************************************************** + * Gets BURTC counter. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return BURTC_CounterGet(); +} + +/****************************************************************************** + * Gets BURTC compare value + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return BURTC_CompareGet(0U); +} + +/****************************************************************************** + * Sets BURTC compare value + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the BURTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare_current; + uint32_t compare_new = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare_current = sleeptimer_hal_get_compare(); + + if (((BURTC_IntGet() & _BURTC_IF_COMP_MASK) != 0) + || get_time_diff(compare_current, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare_current == counter) { + // Add margin if necessary + if (get_time_diff(compare_new, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_new = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + + // wrap around if necessary + compare_new %= SLEEPTIMER_TMR_WIDTH; + + BURTC_CompareSet(0U, compare_new - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + BURTC_IntEnable(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Disables BURTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + BURTC_IntDisable(irqien_hal2burtc(local_flag)); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + BURTC_IntSet(irqien_hal2burtc(local_flag)); +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = BURTC_IntGet(); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = (irq_flag & BURTC_IF_COMP); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = (irq_flag & BURTC_IF_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * Gets BURTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + return (CMU_ClockFreqGet(cmuClock_BURTC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); +} + +/******************************************************************************* + * BURTC interrupt handler. + ******************************************************************************/ +void BURTC_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = BURTC_IntGet(); + local_flag = irqflags_burtc2hal(irq_flag); + + BURTC_IntClear(irq_flag & (BURTC_IF_OF | BURTC_IF_COMP)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +static uint32_t get_time_diff(uint32_t a, uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + return CMU_LF_ClockPrecisionGet(cmuClock_BURTC); +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for BURTC peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + switch (CMU->EM4GRPACLKCTRL & _CMU_EM4GRPACLKCTRL_CLKSEL_MASK) { + case CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO: + case CMU_EM4GRPACLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +} +#endif +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c index 6741f19..18b5604 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c @@ -1,534 +1,534 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction implementation for PRORTC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_core.h" -#include "em_cmu.h" -#include "em_bus.h" - -#if defined(SL_COMPONENT_CATALOG_PRESENT) -#include -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ - && (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) -#include "sli_power_manager.h" -#endif - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_PRORTC - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) -#define PRORTC_CNT_MASK 0xFFFFFFFFUL - -#define SLEEPTIMER_TMR_WIDTH (PRORTC_CNT_MASK) - -#define TIMER_COMP_REQ 0U - -#define _PRORTC_IF_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ -#define PRORTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ - -#if (TIMER_COMP_REQ == 0) -#define PRORTC_IF_COMP_BIT RTCC_IF_CC0 -#elif (TIMER_COMP_REQ == 1) -#define PRORTC_IF_COMP_BIT RTCC_IF_CC1 -#endif - -#ifndef SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER -#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 -#endif - -#if SL_SLEEPTIMER_FREQ_DIVIDER != 1 -#warning A value other than 1 for SL_SLEEPTIMER_FREQ_DIVIDER is not supported on Radio Internal RTC (PRORTC) -#endif - -static uint32_t get_time_diff(uint32_t a, uint32_t b); - -static bool cc_disabled = true; - -/****************************************************************************** - * Initializes PRORTC sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t cmu_status = CMU->STATUS; - uint32_t lfr_clk_sel = CMU_LFRCLKSEL_LFR_DEFAULT; - - if ((cmu_status & _CMU_STATUS_LFXORDY_MASK) == CMU_STATUS_LFXORDY) { - lfr_clk_sel = CMU_LFRCLKSEL_LFR_LFXO; -#ifdef PLFRCO_PRESENT - } else if ((cmu_status & _CMU_STATUS_PLFRCORDY_MASK) == CMU_STATUS_PLFRCORDY) { - lfr_clk_sel = CMU_LFRCLKSEL_LFR_PLFRCO; -#endif - } else { - lfr_clk_sel = CMU_LFRCLKSEL_LFR_LFRCO; - } - - // Set the Low Frequency R Clock Select Register - CMU->LFRCLKSEL = (CMU->LFRCLKSEL & ~_CMU_LFRCLKSEL_LFR_MASK) - | (lfr_clk_sel << _CMU_LFRCLKSEL_LFR_SHIFT); - - // Enable the PRORTC module - CMU->LFRCLKEN0 |= 1 << _CMU_LFRCLKEN0_PRORTC_SHIFT; - - PRORTC->IFC = _PRORTC_IF_MASK; - -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - PRORTC->CTRL = _PRORTC_CTRL_EN_MASK | _PRORTC_CTRL_DEBUGRUN_MASK; -#else - PRORTC->CTRL = _PRORTC_CTRL_EN_MASK; -#endif -#else - bool use_clk_lfxo = true; - - // Must enable radio clock branch to clock the radio bus as PRORTC is on this bus. - CMU->RADIOCLKCTRL = CMU_RADIOCLKCTRL_EN; - -#if defined(CMU_CLKEN1_PRORTC) - CMU->CLKEN1_SET = CMU_CLKEN1_PRORTC; -#endif - -#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1 - uint32_t enabled_clocks = CMU->CLKEN0; - use_clk_lfxo = ((enabled_clocks & _CMU_CLKEN0_LFXO_MASK) == _CMU_CLKEN0_LFXO_MASK); -#endif //_SILICON_LABS_32B_SERIES_2_CONFIG == 2 - - // On demand clocking for series 2 chips, make sure that the clock is - // not force disabled i.e. FORCEEN = 0, DISONDEMAND = 1 - // Cannot rely on ENS bit of STATUS register since that is only set - // when a module uses the LF clock otherwise the ENS bit will be set to 0. - use_clk_lfxo = use_clk_lfxo - && ((LFXO->CTRL - & (_LFXO_CTRL_FORCEEN_MASK | _LFXO_CTRL_DISONDEMAND_MASK)) - != _LFXO_CTRL_DISONDEMAND_MASK); - - if (use_clk_lfxo) { - CMU->PRORTCCLKCTRL = CMU_PRORTCCLKCTRL_CLKSEL_LFXO; - } else { - CMU->PRORTCCLKCTRL = CMU_PRORTCCLKCTRL_CLKSEL_LFRCO; - } - -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - PRORTC->CFG |= _RTCC_CFG_DEBUGRUN_MASK; -#endif - - PRORTC->EN_SET = RTCC_EN_EN; - - PRORTC->CC[TIMER_COMP_REQ].CTRL = (_RTCC_CC_CTRL_MODE_OFF << _RTCC_CC_CTRL_MODE_SHIFT) - | (_RTCC_CC_CTRL_CMOA_PULSE << _RTCC_CC_CTRL_CMOA_SHIFT) - | (_RTCC_CC_CTRL_ICEDGE_NONE << _RTCC_CC_CTRL_ICEDGE_SHIFT) - | (_RTCC_CC_CTRL_COMPBASE_CNT << _RTCC_CC_CTRL_COMPBASE_SHIFT); - - // Write the start bit until it syncs to the low frequency domain - do { - PRORTC->CMD = RTCC_CMD_START; - while ((PRORTC->SYNCBUSY & _RTCC_SYNCBUSY_MASK) != 0U) ; - } while ((PRORTC->STATUS & _RTCC_STATUS_RUNNING_MASK) != RTCC_STATUS_RUNNING); - - // Disable ALL PRORTC interrupts - PRORTC->IEN &= ~_RTCC_IEN_MASK; - - // Clear any pending interrupts -#if defined (RTCC_HAS_SET_CLEAR) - PRORTC->IF_CLR = _RTCC_IF_MASK; -#else - PRORTC->IFC = _RTCC_IF_MASK; -#endif -#endif - - NVIC_ClearPendingIRQ(PRORTC_IRQn); - NVIC_EnableIRQ(PRORTC_IRQn); -} - -/****************************************************************************** - * Gets PRORTC counter value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return PRORTC->CNT; -} - -/****************************************************************************** - * Gets PRORTC compare value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - return PRORTC->COMP[TIMER_COMP_REQ].COMP; -#else - return PRORTC->CC[TIMER_COMP_REQ].OCVALUE; -#endif -} - -/****************************************************************************** - * Sets PRORTC compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the PRORTC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare; - uint32_t compare_value = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare = sleeptimer_hal_get_compare(); - - if (((PRORTC->IF & PRORTC_IF_COMP_BIT) != 0) - || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare == counter) { - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - compare_value %= SLEEPTIMER_TMR_WIDTH; - -#if defined(_SILICON_LABS_32B_SERIES_1) - PRORTC->COMP[TIMER_COMP_REQ].COMP = compare_value - 1; -#else - PRORTC->CC[TIMER_COMP_REQ].OCVALUE = compare_value - 1; -#endif - - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_CRITICAL(); - -#if defined(_SILICON_LABS_32B_SERIES_2) - if (cc_disabled) { - PRORTC->CC[TIMER_COMP_REQ].CTRL |= RTCC_CC_CTRL_MODE_OUTPUTCOMPARE; - cc_disabled = false; - } -#endif -} - -/****************************************************************************** - * Enables PRORTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - uint32_t prortc_ien = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - prortc_ien |= PRORTC_IF_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { -#if defined(_SILICON_LABS_32B_SERIES_1) - if (cc_disabled == true) { -#if defined (RTCC_HAS_SET_CLEAR) - PRORTC->IF_CLR = PRORTC_IF_COMP_BIT; -#else - PRORTC->IFC = PRORTC_IF_COMP_BIT; -#endif - - cc_disabled = false; - } -#endif - - prortc_ien |= PRORTC_IF_COMP_BIT; - } - - BUS_RegMaskedSet(&PRORTC->IEN, prortc_ien); -} - -/****************************************************************************** - * Disables PRORTC interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - uint32_t prortc_int_dis = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - prortc_int_dis |= PRORTC_IF_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - prortc_int_dis |= PRORTC_IF_COMP_BIT; - cc_disabled = true; - -#if defined(_SILICON_LABS_32B_SERIES_2) - PRORTC->CC[TIMER_COMP_REQ].CTRL &= ~_RTCC_CC_CTRL_MODE_MASK; -#endif - } - - BUS_RegMaskedClear(&PRORTC->IEN, prortc_int_dis); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - if (local_flag & SLEEPTIMER_EVENT_COMP) { -#if defined (RTCC_HAS_SET_CLEAR) - PRORTC->IF_SET = PRORTC_IF_COMP_BIT; -#else - PRORTC->IFS = PRORTC_IF_COMP_BIT; -#endif - } -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = PRORTC->IF;; - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = ((irq_flag & PRORTC_IF_COMP_BIT) == PRORTC_IF_COMP_BIT); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = ((irq_flag & PRORTC_IF_OF) == PRORTC_IF_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * PRORTC interrupt handler. - ******************************************************************************/ -#if (SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER == 1) -void PRORTC_IRQHandler(void) -#else -void PRORTC_IRQHandlerOverride(void) -#endif -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = PRORTC->IF; - - if (irq_flag & PRORTC_IF_OF) { - local_flag |= SLEEPTIMER_EVENT_OF; - } - if (irq_flag & PRORTC_IF_COMP_BIT) { - local_flag |= SLEEPTIMER_EVENT_COMP; - } - - /* Clear interrupt source. */ -#if defined (RTCC_HAS_SET_CLEAR) - PRORTC->IF_CLR = irq_flag; -#else - PRORTC->IFC = irq_flag; -#endif - - process_timer_irq(local_flag); - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Gets PRORTC timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - uint32_t lfr_clk_sel; -#endif - uint32_t freq; - -#if defined(_SILICON_LABS_32B_SERIES_1) - lfr_clk_sel = (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) << _CMU_LFRCLKSEL_LFR_SHIFT; - - switch (lfr_clk_sel) { - case _CMU_LFRCLKSEL_LFR_LFXO: - freq = SystemLFXOClockGet(); - break; - -#if defined(PLFRCO_PRESENT) - case _CMU_LFRCLKSEL_LFR_PLFRCO: - freq = SystemLFRCOClockGet(); - break; -#endif - - case _CMU_LFRCLKSEL_LFR_LFRCO: - default: - freq = SystemLFRCOClockGet(); - break; - } - - freq >>= (CMU->LFRPRESC0 & _CMU_LFRPRESC0_PRORTC_MASK) - >> _CMU_LFRPRESC0_PRORTC_SHIFT; -#elif defined(_SILICON_LABS_32B_SERIES_2) - if (CMU->PRORTCCLKCTRL == CMU_PRORTCCLKCTRL_CLKSEL_LFXO) { - freq = SystemLFXOClockGet(); - } else { - freq = SystemLFRCOClockGet(); - } -#endif - - return freq; -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -static uint32_t get_time_diff(uint32_t a, uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - * @note - * The CMU_LF_ClockPrecisionGet function usally used to retrieve - * the clock accuracy can't be used for PRORTC as it isn't public, - * so this function works in the same way. - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ - uint16_t precision = 0xFFFF; - -#if defined(_SILICON_LABS_32B_SERIES_2) - if (CMU->PRORTCCLKCTRL == CMU_PRORTCCLKCTRL_CLKSEL_LFXO) { - precision = CMU_LFXOPrecisionGet(); - -#if defined(LFRCO_CFG_HIGHPRECEN) && defined(PLFRCO_PRESENT) - } else { - CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; - - if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { - precision = 500; - } else { - precision = 0xFFFF; - } -#endif - } - -#else - uint32_t lfr_clk_sel = (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) << _CMU_LFRCLKSEL_LFR_SHIFT; - - switch (lfr_clk_sel) { - case _CMU_LFRCLKSEL_LFR_LFXO: - precision = CMU_LFXOPrecisionGet(); - break; - -#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) - case _CMU_LFRCLKSEL_LFR_PLFRCO: - precision = 500; - break; -#endif - - default: - precision = 0xFFFF; - break; - } - -#endif - - return precision; -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for PRORTC peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for PRORTC peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_1) - switch (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) { - case CMU_LFRCLKSEL_LFR_LFRCO: - case CMU_LFRCLKSEL_LFR_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -#else - switch (CMU->PRORTCCLKCTRL & _CMU_PRORTCCLKCTRL_CLKSEL_MASK) { - case CMU_PRORTCCLKCTRL_CLKSEL_LFRCO: - case CMU_PRORTCCLKCTRL_CLKSEL_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -#endif -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for PRORTC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_core.h" +#include "em_cmu.h" +#include "em_bus.h" + +#if defined(SL_COMPONENT_CATALOG_PRESENT) +#include +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \ + && (_SILICON_LABS_32B_SERIES_2_CONFIG == 1) +#include "sli_power_manager.h" +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_PRORTC + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) +#define PRORTC_CNT_MASK 0xFFFFFFFFUL + +#define SLEEPTIMER_TMR_WIDTH (PRORTC_CNT_MASK) + +#define TIMER_COMP_REQ 0U + +#define _PRORTC_IF_COMP_SHIFT 1 /**< Shift value for RTC_COMP */ +#define PRORTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ + +#if (TIMER_COMP_REQ == 0) +#define PRORTC_IF_COMP_BIT RTCC_IF_CC0 +#elif (TIMER_COMP_REQ == 1) +#define PRORTC_IF_COMP_BIT RTCC_IF_CC1 +#endif + +#ifndef SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER +#define SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER 0 +#endif + +#if SL_SLEEPTIMER_FREQ_DIVIDER != 1 +#warning A value other than 1 for SL_SLEEPTIMER_FREQ_DIVIDER is not supported on Radio Internal RTC (PRORTC) +#endif + +static uint32_t get_time_diff(uint32_t a, uint32_t b); + +static bool cc_disabled = true; + +/****************************************************************************** + * Initializes PRORTC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t cmu_status = CMU->STATUS; + uint32_t lfr_clk_sel = CMU_LFRCLKSEL_LFR_DEFAULT; + + if ((cmu_status & _CMU_STATUS_LFXORDY_MASK) == CMU_STATUS_LFXORDY) { + lfr_clk_sel = CMU_LFRCLKSEL_LFR_LFXO; +#ifdef PLFRCO_PRESENT + } else if ((cmu_status & _CMU_STATUS_PLFRCORDY_MASK) == CMU_STATUS_PLFRCORDY) { + lfr_clk_sel = CMU_LFRCLKSEL_LFR_PLFRCO; +#endif + } else { + lfr_clk_sel = CMU_LFRCLKSEL_LFR_LFRCO; + } + + // Set the Low Frequency R Clock Select Register + CMU->LFRCLKSEL = (CMU->LFRCLKSEL & ~_CMU_LFRCLKSEL_LFR_MASK) + | (lfr_clk_sel << _CMU_LFRCLKSEL_LFR_SHIFT); + + // Enable the PRORTC module + CMU->LFRCLKEN0 |= 1 << _CMU_LFRCLKEN0_PRORTC_SHIFT; + + PRORTC->IFC = _PRORTC_IF_MASK; + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + PRORTC->CTRL = _PRORTC_CTRL_EN_MASK | _PRORTC_CTRL_DEBUGRUN_MASK; +#else + PRORTC->CTRL = _PRORTC_CTRL_EN_MASK; +#endif +#else + bool use_clk_lfxo = true; + + // Must enable radio clock branch to clock the radio bus as PRORTC is on this bus. + CMU->RADIOCLKCTRL = CMU_RADIOCLKCTRL_EN; + +#if defined(CMU_CLKEN1_PRORTC) + CMU->CLKEN1_SET = CMU_CLKEN1_PRORTC; +#endif + +#if _SILICON_LABS_32B_SERIES_2_CONFIG > 1 + uint32_t enabled_clocks = CMU->CLKEN0; + use_clk_lfxo = ((enabled_clocks & _CMU_CLKEN0_LFXO_MASK) == _CMU_CLKEN0_LFXO_MASK); +#endif //_SILICON_LABS_32B_SERIES_2_CONFIG == 2 + + // On demand clocking for series 2 chips, make sure that the clock is + // not force disabled i.e. FORCEEN = 0, DISONDEMAND = 1 + // Cannot rely on ENS bit of STATUS register since that is only set + // when a module uses the LF clock otherwise the ENS bit will be set to 0. + use_clk_lfxo = use_clk_lfxo + && ((LFXO->CTRL + & (_LFXO_CTRL_FORCEEN_MASK | _LFXO_CTRL_DISONDEMAND_MASK)) + != _LFXO_CTRL_DISONDEMAND_MASK); + + if (use_clk_lfxo) { + CMU->PRORTCCLKCTRL = CMU_PRORTCCLKCTRL_CLKSEL_LFXO; + } else { + CMU->PRORTCCLKCTRL = CMU_PRORTCCLKCTRL_CLKSEL_LFRCO; + } + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + PRORTC->CFG |= _RTCC_CFG_DEBUGRUN_MASK; +#endif + + PRORTC->EN_SET = RTCC_EN_EN; + + PRORTC->CC[TIMER_COMP_REQ].CTRL = (_RTCC_CC_CTRL_MODE_OFF << _RTCC_CC_CTRL_MODE_SHIFT) + | (_RTCC_CC_CTRL_CMOA_PULSE << _RTCC_CC_CTRL_CMOA_SHIFT) + | (_RTCC_CC_CTRL_ICEDGE_NONE << _RTCC_CC_CTRL_ICEDGE_SHIFT) + | (_RTCC_CC_CTRL_COMPBASE_CNT << _RTCC_CC_CTRL_COMPBASE_SHIFT); + + // Write the start bit until it syncs to the low frequency domain + do { + PRORTC->CMD = RTCC_CMD_START; + while ((PRORTC->SYNCBUSY & _RTCC_SYNCBUSY_MASK) != 0U) ; + } while ((PRORTC->STATUS & _RTCC_STATUS_RUNNING_MASK) != RTCC_STATUS_RUNNING); + + // Disable ALL PRORTC interrupts + PRORTC->IEN &= ~_RTCC_IEN_MASK; + + // Clear any pending interrupts +#if defined (RTCC_HAS_SET_CLEAR) + PRORTC->IF_CLR = _RTCC_IF_MASK; +#else + PRORTC->IFC = _RTCC_IF_MASK; +#endif +#endif + + NVIC_ClearPendingIRQ(PRORTC_IRQn); + NVIC_EnableIRQ(PRORTC_IRQn); +} + +/****************************************************************************** + * Gets PRORTC counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return PRORTC->CNT; +} + +/****************************************************************************** + * Gets PRORTC compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + return PRORTC->COMP[TIMER_COMP_REQ].COMP; +#else + return PRORTC->CC[TIMER_COMP_REQ].OCVALUE; +#endif +} + +/****************************************************************************** + * Sets PRORTC compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the PRORTC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((PRORTC->IF & PRORTC_IF_COMP_BIT) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + +#if defined(_SILICON_LABS_32B_SERIES_1) + PRORTC->COMP[TIMER_COMP_REQ].COMP = compare_value - 1; +#else + PRORTC->CC[TIMER_COMP_REQ].OCVALUE = compare_value - 1; +#endif + + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); + +#if defined(_SILICON_LABS_32B_SERIES_2) + if (cc_disabled) { + PRORTC->CC[TIMER_COMP_REQ].CTRL |= RTCC_CC_CTRL_MODE_OUTPUTCOMPARE; + cc_disabled = false; + } +#endif +} + +/****************************************************************************** + * Enables PRORTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t prortc_ien = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + prortc_ien |= PRORTC_IF_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { +#if defined(_SILICON_LABS_32B_SERIES_1) + if (cc_disabled == true) { +#if defined (RTCC_HAS_SET_CLEAR) + PRORTC->IF_CLR = PRORTC_IF_COMP_BIT; +#else + PRORTC->IFC = PRORTC_IF_COMP_BIT; +#endif + + cc_disabled = false; + } +#endif + + prortc_ien |= PRORTC_IF_COMP_BIT; + } + + BUS_RegMaskedSet(&PRORTC->IEN, prortc_ien); +} + +/****************************************************************************** + * Disables PRORTC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t prortc_int_dis = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + prortc_int_dis |= PRORTC_IF_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + prortc_int_dis |= PRORTC_IF_COMP_BIT; + cc_disabled = true; + +#if defined(_SILICON_LABS_32B_SERIES_2) + PRORTC->CC[TIMER_COMP_REQ].CTRL &= ~_RTCC_CC_CTRL_MODE_MASK; +#endif + } + + BUS_RegMaskedClear(&PRORTC->IEN, prortc_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { +#if defined (RTCC_HAS_SET_CLEAR) + PRORTC->IF_SET = PRORTC_IF_COMP_BIT; +#else + PRORTC->IFS = PRORTC_IF_COMP_BIT; +#endif + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = PRORTC->IF;; + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & PRORTC_IF_COMP_BIT) == PRORTC_IF_COMP_BIT); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & PRORTC_IF_OF) == PRORTC_IF_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * PRORTC interrupt handler. + ******************************************************************************/ +#if (SL_SLEEPTIMER_PRORTC_HAL_OWNS_IRQ_HANDLER == 1) +void PRORTC_IRQHandler(void) +#else +void PRORTC_IRQHandlerOverride(void) +#endif +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = PRORTC->IF; + + if (irq_flag & PRORTC_IF_OF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + if (irq_flag & PRORTC_IF_COMP_BIT) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + + /* Clear interrupt source. */ +#if defined (RTCC_HAS_SET_CLEAR) + PRORTC->IF_CLR = irq_flag; +#else + PRORTC->IFC = irq_flag; +#endif + + process_timer_irq(local_flag); + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets PRORTC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + uint32_t lfr_clk_sel; +#endif + uint32_t freq; + +#if defined(_SILICON_LABS_32B_SERIES_1) + lfr_clk_sel = (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) << _CMU_LFRCLKSEL_LFR_SHIFT; + + switch (lfr_clk_sel) { + case _CMU_LFRCLKSEL_LFR_LFXO: + freq = SystemLFXOClockGet(); + break; + +#if defined(PLFRCO_PRESENT) + case _CMU_LFRCLKSEL_LFR_PLFRCO: + freq = SystemLFRCOClockGet(); + break; +#endif + + case _CMU_LFRCLKSEL_LFR_LFRCO: + default: + freq = SystemLFRCOClockGet(); + break; + } + + freq >>= (CMU->LFRPRESC0 & _CMU_LFRPRESC0_PRORTC_MASK) + >> _CMU_LFRPRESC0_PRORTC_SHIFT; +#elif defined(_SILICON_LABS_32B_SERIES_2) + if (CMU->PRORTCCLKCTRL == CMU_PRORTCCLKCTRL_CLKSEL_LFXO) { + freq = SystemLFXOClockGet(); + } else { + freq = SystemLFRCOClockGet(); + } +#endif + + return freq; +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +static uint32_t get_time_diff(uint32_t a, uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + * @note + * The CMU_LF_ClockPrecisionGet function usally used to retrieve + * the clock accuracy can't be used for PRORTC as it isn't public, + * so this function works in the same way. + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ + uint16_t precision = 0xFFFF; + +#if defined(_SILICON_LABS_32B_SERIES_2) + if (CMU->PRORTCCLKCTRL == CMU_PRORTCCLKCTRL_CLKSEL_LFXO) { + precision = CMU_LFXOPrecisionGet(); + +#if defined(LFRCO_CFG_HIGHPRECEN) && defined(PLFRCO_PRESENT) + } else { + CMU->CLKEN0_SET = CMU_CLKEN0_LFRCO; + + if (LFRCO->CFG & _LFRCO_CFG_HIGHPRECEN_MASK) { + precision = 500; + } else { + precision = 0xFFFF; + } +#endif + } + +#else + uint32_t lfr_clk_sel = (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) << _CMU_LFRCLKSEL_LFR_SHIFT; + + switch (lfr_clk_sel) { + case _CMU_LFRCLKSEL_LFR_LFXO: + precision = CMU_LFXOPrecisionGet(); + break; + +#if defined(_SILICON_LABS_32B_SERIES_1) && defined(PLFRCO_PRESENT) + case _CMU_LFRCLKSEL_LFR_PLFRCO: + precision = 500; + break; +#endif + + default: + precision = 0xFFFF; + break; + } + +#endif + + return precision; +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for PRORTC peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for PRORTC peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_1) + switch (CMU->LFRCLKSEL & _CMU_LFRCLKSEL_LFR_MASK) { + case CMU_LFRCLKSEL_LFR_LFRCO: + case CMU_LFRCLKSEL_LFR_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +#else + switch (CMU->PRORTCCLKCTRL & _CMU_PRORTCCLKCTRL_CLKSEL_MASK) { + case CMU_PRORTCCLKCTRL_CLKSEL_LFRCO: + case CMU_PRORTCCLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +#endif +} +#endif +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c index 2e76bd8..9e0811d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c @@ -1,341 +1,341 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction implementation for RTCC. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_rtcc.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_RTCC - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) - -#define SLEEPTIMER_TMR_WIDTH (_RTCC_CNT_MASK) - -static bool cc_disabled = true; - -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b); - -/****************************************************************************** - * Initializes RTCC sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer(void) -{ - RTCC_Init_TypeDef rtcc_init = RTCC_INIT_DEFAULT; - RTCC_CCChConf_TypeDef channel = RTCC_CH_INIT_COMPARE_DEFAULT; - - CMU_ClockEnable(cmuClock_RTCC, true); - - rtcc_init.enable = false; - rtcc_init.presc = (RTCC_CntPresc_TypeDef)(CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1)); -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - rtcc_init.debugRun = true; -#endif - - RTCC_Init(&rtcc_init); - - // Compare channel starts disabled and is enabled only when compare match interrupt is enabled. - channel.chMode = rtccCapComChModeOff; - RTCC_ChannelInit(1u, &channel); - - RTCC_IntDisable(_RTCC_IEN_MASK); - RTCC_IntClear(_RTCC_IF_MASK); - RTCC_CounterSet(0u); - - RTCC_Enable(true); - - NVIC_ClearPendingIRQ(RTCC_IRQn); - NVIC_EnableIRQ(RTCC_IRQn); -} - -/****************************************************************************** - * Gets RTCC counter value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return RTCC_CounterGet(); -} - -/****************************************************************************** - * Gets RTCC compare value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return RTCC_ChannelCCVGet(1u); -} - -/****************************************************************************** - * Sets RTCC compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the RTCC compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare; - uint32_t compare_value = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare = sleeptimer_hal_get_compare(); - if (((RTCC_IntGet() & RTCC_IEN_CC1) != 0) - || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare == counter) { - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - compare_value %= SLEEPTIMER_TMR_WIDTH; - - RTCC_ChannelCCVSet(1u, compare_value - 1u); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - } - CORE_EXIT_CRITICAL(); - - if (cc_disabled) { - RTCC->CC[1].CTRL |= RTCC_CC_CTRL_MODE_OUTPUTCOMPARE; - cc_disabled = false; - } -} - -/****************************************************************************** - * Enables RTCC interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - uint32_t rtcc_ien = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - rtcc_ien |= RTCC_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - rtcc_ien |= RTCC_IEN_CC1; - } - - RTCC_IntEnable(rtcc_ien); -} - -/****************************************************************************** - * Disables RTCC interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - uint32_t rtcc_int_dis = 0u; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - rtcc_int_dis |= RTCC_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - rtcc_int_dis |= RTCC_IEN_CC1; - - cc_disabled = true; - RTCC->CC[1].CTRL &= ~_RTCC_CC_CTRL_MODE_MASK; - } - - RTCC_IntDisable(rtcc_int_dis); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - if (local_flag & SLEEPTIMER_EVENT_COMP) { - RTCC_IntSet(RTCC_IF_CC1); - } -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = RTCC_IntGet(); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = ((irq_flag & RTCC_IF_CC1) == RTCC_IF_CC1); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = ((irq_flag & RTCC_IF_OF) == RTCC_IF_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * RTCC interrupt handler. - ******************************************************************************/ -void RTCC_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = RTCC_IntGet(); - - if (irq_flag & RTCC_IF_OF) { - local_flag |= SLEEPTIMER_EVENT_OF; - } - if (irq_flag & RTCC_IF_CC1) { - local_flag |= SLEEPTIMER_EVENT_COMP; - } - RTCC_IntClear(irq_flag & (RTCC_IF_OF | RTCC_IF_CC1 | RTCC_IF_CC0)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Gets RTCC timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - return (CMU_ClockFreqGet(cmuClock_RTCC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ -#if defined(_SILICON_LABS_32B_SERIES_2) - return CMU_LF_ClockPrecisionGet(cmuClock_RTCC); - -#else - return CMU_LF_ClockPrecisionGet(cmuClock_LFE); -#endif -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for RTCC peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for RTCC peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note If power_manager_no_deepsleep component is included in a project, the - * lowest possible energy mode is EM1, else lowest energy mode is - * determined by clock source. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ -#if defined(_CMU_RTCCCLKCTRL_CLKSEL_MASK) - switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { - case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: - case CMU_RTCCCLKCTRL_CLKSEL_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -#elif defined(_CMU_LFECLKEN0_RTCC_MASK) - switch ((CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT) { - case CMU_LFECLKSEL_LFE_LFRCO: - case CMU_LFECLKSEL_LFE_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -#elif defined(_CMU_LFACLKEN0_RTCC_MASK) - switch ((CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT) { - case CMU_LFACLKSEL_LFA_LFRCO: - case CMU_LFACLKSEL_LFA_LFXO: - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); - break; - default: - break; - } -#endif -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for RTCC. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_rtcc.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_RTCC + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (2 + 1) + +#define SLEEPTIMER_TMR_WIDTH (_RTCC_CNT_MASK) + +static bool cc_disabled = true; + +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes RTCC sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + RTCC_Init_TypeDef rtcc_init = RTCC_INIT_DEFAULT; + RTCC_CCChConf_TypeDef channel = RTCC_CH_INIT_COMPARE_DEFAULT; + + CMU_ClockEnable(cmuClock_RTCC, true); + + rtcc_init.enable = false; + rtcc_init.presc = (RTCC_CntPresc_TypeDef)(CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1)); +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + rtcc_init.debugRun = true; +#endif + + RTCC_Init(&rtcc_init); + + // Compare channel starts disabled and is enabled only when compare match interrupt is enabled. + channel.chMode = rtccCapComChModeOff; + RTCC_ChannelInit(1u, &channel); + + RTCC_IntDisable(_RTCC_IEN_MASK); + RTCC_IntClear(_RTCC_IF_MASK); + RTCC_CounterSet(0u); + + RTCC_Enable(true); + + NVIC_ClearPendingIRQ(RTCC_IRQn); + NVIC_EnableIRQ(RTCC_IRQn); +} + +/****************************************************************************** + * Gets RTCC counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return RTCC_CounterGet(); +} + +/****************************************************************************** + * Gets RTCC compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return RTCC_ChannelCCVGet(1u); +} + +/****************************************************************************** + * Sets RTCC compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the RTCC compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + if (((RTCC_IntGet() & RTCC_IEN_CC1) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + RTCC_ChannelCCVSet(1u, compare_value - 1u); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + } + CORE_EXIT_CRITICAL(); + + if (cc_disabled) { + RTCC->CC[1].CTRL |= RTCC_CC_CTRL_MODE_OUTPUTCOMPARE; + cc_disabled = false; + } +} + +/****************************************************************************** + * Enables RTCC interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t rtcc_ien = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + rtcc_ien |= RTCC_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + rtcc_ien |= RTCC_IEN_CC1; + } + + RTCC_IntEnable(rtcc_ien); +} + +/****************************************************************************** + * Disables RTCC interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t rtcc_int_dis = 0u; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + rtcc_int_dis |= RTCC_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + rtcc_int_dis |= RTCC_IEN_CC1; + + cc_disabled = true; + RTCC->CC[1].CTRL &= ~_RTCC_CC_CTRL_MODE_MASK; + } + + RTCC_IntDisable(rtcc_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + RTCC_IntSet(RTCC_IF_CC1); + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = RTCC_IntGet(); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & RTCC_IF_CC1) == RTCC_IF_CC1); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & RTCC_IF_OF) == RTCC_IF_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * RTCC interrupt handler. + ******************************************************************************/ +void RTCC_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = RTCC_IntGet(); + + if (irq_flag & RTCC_IF_OF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + if (irq_flag & RTCC_IF_CC1) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + RTCC_IntClear(irq_flag & (RTCC_IF_OF | RTCC_IF_CC1 | RTCC_IF_CC0)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets RTCC timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + return (CMU_ClockFreqGet(cmuClock_RTCC) >> (CMU_PrescToLog2(SL_SLEEPTIMER_FREQ_DIVIDER - 1))); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ +#if defined(_SILICON_LABS_32B_SERIES_2) + return CMU_LF_ClockPrecisionGet(cmuClock_RTCC); + +#else + return CMU_LF_ClockPrecisionGet(cmuClock_LFE); +#endif +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for RTCC peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for RTCC peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note If power_manager_no_deepsleep component is included in a project, the + * lowest possible energy mode is EM1, else lowest energy mode is + * determined by clock source. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ +#if defined(_CMU_RTCCCLKCTRL_CLKSEL_MASK) + switch (CMU->RTCCCLKCTRL & _CMU_RTCCCLKCTRL_CLKSEL_MASK) { + case CMU_RTCCCLKCTRL_CLKSEL_LFRCO: + case CMU_RTCCCLKCTRL_CLKSEL_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +#elif defined(_CMU_LFECLKEN0_RTCC_MASK) + switch ((CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT) { + case CMU_LFECLKSEL_LFE_LFRCO: + case CMU_LFECLKSEL_LFE_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +#elif defined(_CMU_LFACLKEN0_RTCC_MASK) + switch ((CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT) { + case CMU_LFACLKSEL_LFA_LFRCO: + case CMU_LFACLKSEL_LFA_LFXO: + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM2); + break; + default: + break; + } +#endif +} +#endif +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c index 54702bb..75feff4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c @@ -1,363 +1,363 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction implementation for WTIMER/TIMER. - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#include "em_timer.h" -#include "sl_sleeptimer.h" -#include "sli_sleeptimer_hal.h" -#include "em_core.h" -#include "em_cmu.h" - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif - -#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ - || (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) - -// Minimum difference between current count value and what the comparator of the timer can be set to. -// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that -// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. -#define SLEEPTIMER_COMPARE_MIN_DIFF (1 + 1) - -// Macros used to constructs WTIMER/TIMER instance -#define _CONCAT_TWO_TOKENS(token_1, token_2) token_1 ## token_2 -#define _CONCAT_THREE_TOKENS(token_1, token_2, token_3) token_1 ## token_2 ## token_3 -#define CONCAT_TWO_TOKENS(token_1, token_2) _CONCAT_TWO_TOKENS(token_1, token_2) -#define CONCAT_THREE_TOKENS(token_1, token_2, token_3) _CONCAT_THREE_TOKENS(token_1, token_2, token_3) - -#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) -#if defined(WTIMER_PRESENT) \ - && (SL_SLEEPTIMER_TIMER_INSTANCE < WTIMER_COUNT) \ - && (_WTIMER_CNT_MASK == 0xFFFFFFFFUL) - #define SLEEPTIMER_TIMER_INSTANCE CONCAT_TWO_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_CHANNEL 0 - #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) - #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) - #define SLEEPTIMER_TIMER_IEN_COMPARE WTIMER_IEN_CC0 - #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_TOP_MAX _WTIMER_TOP_MASK - #define SLEEPTIMER_TMR_WIDTH _WTIMER_CNT_MASK -#else - #define TIMER_UNSUPORTED -#endif - -#elif (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ - && (_SILICON_LABS_32B_SERIES > 1) -#if defined(TIMER_PRESENT) \ - && (SL_SLEEPTIMER_TIMER_INSTANCE < TIMER_COUNT) \ - && (TIMER_CNTWIDTH(SL_SLEEPTIMER_TIMER_INSTANCE) == 0x20) - #define SLEEPTIMER_TIMER_INSTANCE TIMER(SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_CHANNEL 0 - #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) - #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) - #define SLEEPTIMER_TIMER_IEN_COMPARE TIMER_IEN_CC0 - #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) - #define SLEEPTIMER_TIMER_TOP_MAX _TIMER_TOP_MASK - #define SLEEPTIMER_TMR_WIDTH _TIMER_CNT_MASK -#else - #define TIMER_UNSUPORTED -#endif - -#else - #define TIMER_UNSUPORTED -#endif - -#if defined(TIMER_UNSUPORTED) -#error "The WTIMER/TIMER peripheral instance or channel is not supported. It must be a valid 32-bits size instance." -#endif -static bool comp_int_disabled = true; - -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b); - -/****************************************************************************** - * Initializes TIMER sleep timer. - *****************************************************************************/ -void sleeptimer_hal_init_timer(void) -{ - TIMER_Init_TypeDef init_config = TIMER_INIT_DEFAULT; - TIMER_InitCC_TypeDef init_config_cc = TIMER_INITCC_DEFAULT; - - CMU_ClockEnable(SLEEPTIMER_TIMER_CLK, true); - - init_config_cc.mode = timerCCModeCompare; - TIMER_InitCC(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); - TIMER_TopSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); - -#if (SL_SLEEPTIMER_DEBUGRUN == 1) - init_config.debugRun = true; -#endif - - // - init_config.prescale = timerPrescale1024; - - TIMER_Init(SLEEPTIMER_TIMER_INSTANCE, &init_config); -#if defined(TIMER_STATUS_SYNCBUSY) - TIMER_SyncWait(SLEEPTIMER_TIMER_INSTANCE); -#endif - - TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); - - TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); - - NVIC_ClearPendingIRQ(SLEEPTIMER_TIMER_IRQ); - NVIC_EnableIRQ(SLEEPTIMER_TIMER_IRQ); -} - -/****************************************************************************** - * Gets TIMER counter value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void) -{ - return TIMER_CounterGet(SLEEPTIMER_TIMER_INSTANCE); -} - -/****************************************************************************** - * Gets TIMER compare value. - *****************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void) -{ - return TIMER_CaptureGet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL); -} - -/****************************************************************************** - * Sets TIMER compare value. - * - * @note Compare match value is set to the requested value - 1. This is done - * to compensate for the fact that the TIMER compare match interrupt always - * triggers at the end of the requested ticks and that the IRQ handler is - * executed when current tick count == compare_value + 1. - *****************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value) -{ - CORE_DECLARE_IRQ_STATE; - uint32_t counter; - uint32_t compare; - uint32_t compare_value = value; - - CORE_ENTER_CRITICAL(); - counter = sleeptimer_hal_get_counter(); - compare = sleeptimer_hal_get_compare(); - - if (((TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE) & SLEEPTIMER_TIMER_IEN_COMPARE) != 0) - || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF - || compare == counter) { - // Add margin if necessary - if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { - compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; - } - compare_value %= SLEEPTIMER_TMR_WIDTH; - - TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, compare_value - 1); - sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); - comp_int_disabled = false; - } - CORE_EXIT_CRITICAL(); -} - -/****************************************************************************** - * Enables TIMER interrupts. - *****************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag) -{ - uint32_t timer_ien = 0UL; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - timer_ien |= TIMER_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - if (comp_int_disabled == true) { - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); - comp_int_disabled = false; - } - timer_ien |= SLEEPTIMER_TIMER_IEN_COMPARE; - } - - TIMER_IntEnable(SLEEPTIMER_TIMER_INSTANCE, timer_ien); -} - -/****************************************************************************** - * Disables TIMER interrupts. - *****************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag) -{ - uint32_t timer_int_dis = 0UL; - - if (local_flag & SLEEPTIMER_EVENT_OF) { - timer_int_dis |= TIMER_IEN_OF; - } - - if (local_flag & SLEEPTIMER_EVENT_COMP) { - timer_int_dis |= SLEEPTIMER_TIMER_IEN_COMPARE; - - comp_int_disabled = true; - } - - TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, timer_int_dis); -} - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag) -{ - if (local_flag & SLEEPTIMER_EVENT_COMP) { - TIMER_IntSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); - } -} - -/****************************************************************************** - * Gets status of specified interrupt. - * - * Note: This function must be called with interrupts disabled. - *****************************************************************************/ -bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) -{ - bool int_is_set = false; - uint32_t irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); - - switch (local_flag) { - case SLEEPTIMER_EVENT_COMP: - int_is_set = ((irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) == SLEEPTIMER_TIMER_IEN_COMPARE); - break; - - case SLEEPTIMER_EVENT_OF: - int_is_set = ((irq_flag & TIMER_IEN_OF) == TIMER_IEN_OF); - break; - - default: - break; - } - - return int_is_set; -} - -/******************************************************************************* - * TIMER interrupt handler. - ******************************************************************************/ -void SLEEPTIMER_TIMER_IRQHandler(void) -{ - CORE_DECLARE_IRQ_STATE; - uint8_t local_flag = 0; - uint32_t irq_flag; - - CORE_ENTER_ATOMIC(); - irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); - - if (irq_flag & TIMER_IEN_OF) { - local_flag |= SLEEPTIMER_EVENT_OF; - } - - if (irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) { - local_flag |= SLEEPTIMER_EVENT_COMP; - } - TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, irq_flag & (TIMER_IEN_OF | SLEEPTIMER_TIMER_IEN_COMPARE)); - - process_timer_irq(local_flag); - - CORE_EXIT_ATOMIC(); -} - -/******************************************************************************* - * Gets TIMER timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void) -{ - // Returns source frequency divided by max prescaler value 1024. - return (CMU_ClockFreqGet(SLEEPTIMER_TIMER_CLK) >> 10UL); -} - -/******************************************************************************* - * Computes difference between two times taking into account timer wrap-around. - * - * @param a Time. - * @param b Time to substract from a. - * - * @return Time difference. - ******************************************************************************/ -__STATIC_INLINE uint32_t get_time_diff(uint32_t a, - uint32_t b) -{ - return (a - b); -} - -/******************************************************************************* - * @brief - * Gets the precision (in PPM) of the sleeptimer's clock. - * - * @return - * Clock accuracy, in PPM. - * - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void) -{ -#if defined(WTIMER_PRESENT) - return CMU_HF_ClockPrecisionGet(cmuClock_HF); -#else - return CMU_HF_ClockPrecisionGet(SLEEPTIMER_TIMER_CLK); -#endif -} - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - * - * @return Capture value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void) -{ - // Invalid for TIMER peripheral - EFM_ASSERT(0); - return 0; -} - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void) -{ - // Invalid for TIMER peripheral - EFM_ASSERT(0); -} - -/***************************************************************************//** - * Set lowest energy mode based on a project's configurations and clock source - * - * @note Lowest possible energy mode for WTIMER and TIMER peripheral is EM1. - ******************************************************************************/ -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -void sli_sleeptimer_set_pm_em_requirement(void) -{ - sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); -} -#endif -#endif +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction implementation for WTIMER/TIMER. + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#include "em_timer.h" +#include "sl_sleeptimer.h" +#include "sli_sleeptimer_hal.h" +#include "em_core.h" +#include "em_cmu.h" + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif + +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ + || (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) + +// Minimum difference between current count value and what the comparator of the timer can be set to. +// 1 tick is added to the minimum diff for the algorithm of compensation for the IRQ handler that +// triggers when CNT == compare_value + 1. For more details refer to sleeptimer_hal_set_compare() function's header. +#define SLEEPTIMER_COMPARE_MIN_DIFF (1 + 1) + +// Macros used to constructs WTIMER/TIMER instance +#define _CONCAT_TWO_TOKENS(token_1, token_2) token_1 ## token_2 +#define _CONCAT_THREE_TOKENS(token_1, token_2, token_3) token_1 ## token_2 ## token_3 +#define CONCAT_TWO_TOKENS(token_1, token_2) _CONCAT_TWO_TOKENS(token_1, token_2) +#define CONCAT_THREE_TOKENS(token_1, token_2, token_3) _CONCAT_THREE_TOKENS(token_1, token_2, token_3) + +#if (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_WTIMER) +#if defined(WTIMER_PRESENT) \ + && (SL_SLEEPTIMER_TIMER_INSTANCE < WTIMER_COUNT) \ + && (_WTIMER_CNT_MASK == 0xFFFFFFFFUL) + #define SLEEPTIMER_TIMER_INSTANCE CONCAT_TWO_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_CHANNEL 0 + #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) + #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) + #define SLEEPTIMER_TIMER_IEN_COMPARE WTIMER_IEN_CC0 + #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_WTIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_TOP_MAX _WTIMER_TOP_MASK + #define SLEEPTIMER_TMR_WIDTH _WTIMER_CNT_MASK +#else + #define TIMER_UNSUPORTED +#endif + +#elif (SL_SLEEPTIMER_PERIPHERAL == SL_SLEEPTIMER_PERIPHERAL_TIMER) \ + && (_SILICON_LABS_32B_SERIES > 1) +#if defined(TIMER_PRESENT) \ + && (SL_SLEEPTIMER_TIMER_INSTANCE < TIMER_COUNT) \ + && (TIMER_CNTWIDTH(SL_SLEEPTIMER_TIMER_INSTANCE) == 0x20) + #define SLEEPTIMER_TIMER_INSTANCE TIMER(SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_CHANNEL 0 + #define SLEEPTIMER_TIMER_IRQ CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQn) + #define SLEEPTIMER_TIMER_IRQHandler CONCAT_THREE_TOKENS(TIMER, SL_SLEEPTIMER_TIMER_INSTANCE, _IRQHandler) + #define SLEEPTIMER_TIMER_IEN_COMPARE TIMER_IEN_CC0 + #define SLEEPTIMER_TIMER_CLK CONCAT_TWO_TOKENS(cmuClock_TIMER, SL_SLEEPTIMER_TIMER_INSTANCE) + #define SLEEPTIMER_TIMER_TOP_MAX _TIMER_TOP_MASK + #define SLEEPTIMER_TMR_WIDTH _TIMER_CNT_MASK +#else + #define TIMER_UNSUPORTED +#endif + +#else + #define TIMER_UNSUPORTED +#endif + +#if defined(TIMER_UNSUPORTED) +#error "The WTIMER/TIMER peripheral instance or channel is not supported. It must be a valid 32-bits size instance." +#endif +static bool comp_int_disabled = true; + +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b); + +/****************************************************************************** + * Initializes TIMER sleep timer. + *****************************************************************************/ +void sleeptimer_hal_init_timer(void) +{ + TIMER_Init_TypeDef init_config = TIMER_INIT_DEFAULT; + TIMER_InitCC_TypeDef init_config_cc = TIMER_INITCC_DEFAULT; + + CMU_ClockEnable(SLEEPTIMER_TIMER_CLK, true); + + init_config_cc.mode = timerCCModeCompare; + TIMER_InitCC(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, &init_config_cc); + TIMER_TopSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_TOP_MAX); + +#if (SL_SLEEPTIMER_DEBUGRUN == 1) + init_config.debugRun = true; +#endif + + // + init_config.prescale = timerPrescale1024; + + TIMER_Init(SLEEPTIMER_TIMER_INSTANCE, &init_config); +#if defined(TIMER_STATUS_SYNCBUSY) + TIMER_SyncWait(SLEEPTIMER_TIMER_INSTANCE); +#endif + + TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, _TIMER_IEN_MASK); + + TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, 0UL); + + NVIC_ClearPendingIRQ(SLEEPTIMER_TIMER_IRQ); + NVIC_EnableIRQ(SLEEPTIMER_TIMER_IRQ); +} + +/****************************************************************************** + * Gets TIMER counter value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void) +{ + return TIMER_CounterGet(SLEEPTIMER_TIMER_INSTANCE); +} + +/****************************************************************************** + * Gets TIMER compare value. + *****************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void) +{ + return TIMER_CaptureGet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL); +} + +/****************************************************************************** + * Sets TIMER compare value. + * + * @note Compare match value is set to the requested value - 1. This is done + * to compensate for the fact that the TIMER compare match interrupt always + * triggers at the end of the requested ticks and that the IRQ handler is + * executed when current tick count == compare_value + 1. + *****************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value) +{ + CORE_DECLARE_IRQ_STATE; + uint32_t counter; + uint32_t compare; + uint32_t compare_value = value; + + CORE_ENTER_CRITICAL(); + counter = sleeptimer_hal_get_counter(); + compare = sleeptimer_hal_get_compare(); + + if (((TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE) & SLEEPTIMER_TIMER_IEN_COMPARE) != 0) + || get_time_diff(compare, counter) > SLEEPTIMER_COMPARE_MIN_DIFF + || compare == counter) { + // Add margin if necessary + if (get_time_diff(compare_value, counter) < SLEEPTIMER_COMPARE_MIN_DIFF) { + compare_value = counter + SLEEPTIMER_COMPARE_MIN_DIFF; + } + compare_value %= SLEEPTIMER_TMR_WIDTH; + + TIMER_CompareSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_CHANNEL, compare_value - 1); + sleeptimer_hal_enable_int(SLEEPTIMER_EVENT_COMP); + comp_int_disabled = false; + } + CORE_EXIT_CRITICAL(); +} + +/****************************************************************************** + * Enables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag) +{ + uint32_t timer_ien = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_ien |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + if (comp_int_disabled == true) { + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + comp_int_disabled = false; + } + timer_ien |= SLEEPTIMER_TIMER_IEN_COMPARE; + } + + TIMER_IntEnable(SLEEPTIMER_TIMER_INSTANCE, timer_ien); +} + +/****************************************************************************** + * Disables TIMER interrupts. + *****************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag) +{ + uint32_t timer_int_dis = 0UL; + + if (local_flag & SLEEPTIMER_EVENT_OF) { + timer_int_dis |= TIMER_IEN_OF; + } + + if (local_flag & SLEEPTIMER_EVENT_COMP) { + timer_int_dis |= SLEEPTIMER_TIMER_IEN_COMPARE; + + comp_int_disabled = true; + } + + TIMER_IntDisable(SLEEPTIMER_TIMER_INSTANCE, timer_int_dis); +} + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag) +{ + if (local_flag & SLEEPTIMER_EVENT_COMP) { + TIMER_IntSet(SLEEPTIMER_TIMER_INSTANCE, SLEEPTIMER_TIMER_IEN_COMPARE); + } +} + +/****************************************************************************** + * Gets status of specified interrupt. + * + * Note: This function must be called with interrupts disabled. + *****************************************************************************/ +bool sli_sleeptimer_hal_is_int_status_set(uint8_t local_flag) +{ + bool int_is_set = false; + uint32_t irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); + + switch (local_flag) { + case SLEEPTIMER_EVENT_COMP: + int_is_set = ((irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) == SLEEPTIMER_TIMER_IEN_COMPARE); + break; + + case SLEEPTIMER_EVENT_OF: + int_is_set = ((irq_flag & TIMER_IEN_OF) == TIMER_IEN_OF); + break; + + default: + break; + } + + return int_is_set; +} + +/******************************************************************************* + * TIMER interrupt handler. + ******************************************************************************/ +void SLEEPTIMER_TIMER_IRQHandler(void) +{ + CORE_DECLARE_IRQ_STATE; + uint8_t local_flag = 0; + uint32_t irq_flag; + + CORE_ENTER_ATOMIC(); + irq_flag = TIMER_IntGet(SLEEPTIMER_TIMER_INSTANCE); + + if (irq_flag & TIMER_IEN_OF) { + local_flag |= SLEEPTIMER_EVENT_OF; + } + + if (irq_flag & SLEEPTIMER_TIMER_IEN_COMPARE) { + local_flag |= SLEEPTIMER_EVENT_COMP; + } + TIMER_IntClear(SLEEPTIMER_TIMER_INSTANCE, irq_flag & (TIMER_IEN_OF | SLEEPTIMER_TIMER_IEN_COMPARE)); + + process_timer_irq(local_flag); + + CORE_EXIT_ATOMIC(); +} + +/******************************************************************************* + * Gets TIMER timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void) +{ + // Returns source frequency divided by max prescaler value 1024. + return (CMU_ClockFreqGet(SLEEPTIMER_TIMER_CLK) >> 10UL); +} + +/******************************************************************************* + * Computes difference between two times taking into account timer wrap-around. + * + * @param a Time. + * @param b Time to substract from a. + * + * @return Time difference. + ******************************************************************************/ +__STATIC_INLINE uint32_t get_time_diff(uint32_t a, + uint32_t b) +{ + return (a - b); +} + +/******************************************************************************* + * @brief + * Gets the precision (in PPM) of the sleeptimer's clock. + * + * @return + * Clock accuracy, in PPM. + * + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void) +{ +#if defined(WTIMER_PRESENT) + return CMU_HF_ClockPrecisionGet(cmuClock_HF); +#else + return CMU_HF_ClockPrecisionGet(SLEEPTIMER_TIMER_CLK); +#endif +} + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @return Capture value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); + return 0; +} + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void) +{ + // Invalid for TIMER peripheral + EFM_ASSERT(0); +} + +/***************************************************************************//** + * Set lowest energy mode based on a project's configurations and clock source + * + * @note Lowest possible energy mode for WTIMER and TIMER peripheral is EM1. + ******************************************************************************/ +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +void sli_sleeptimer_set_pm_em_requirement(void) +{ + sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1); +} +#endif +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h index a6f06b0..10c3d87 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/sleeptimer/src/sli_sleeptimer_hal.h @@ -1,146 +1,146 @@ -/***************************************************************************//** - * @file - * @brief SLEEPTIMER hardware abstraction layer definition. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_SLEEPTIMER_HAL_H -#define SL_SLEEPTIMER_HAL_H - -#include -#include -#include -#include "em_device.h" -#include "sli_sleeptimer.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/******************************************************************************* - * Hardware Abstraction Layer of the sleep timer init. - ******************************************************************************/ -void sleeptimer_hal_init_timer(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get the current timer count. - * - * @return Value in ticks of the timer counter. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_counter(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get a timer comparator value. - * - * @return Value in ticks of the timer comparator. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_compare(void); - -/******************************************************************************* - * Hardware Abstraction Layer to set a timer comparator value. - * - * @param value Number of ticks to set. - ******************************************************************************/ -void sleeptimer_hal_set_compare(uint32_t value); - -/******************************************************************************* - * Hardware Abstraction Layer to set a comparator value to trigger a - * peripheral request signal to initialize. - * - * @param value Number of ticks to set. - ******************************************************************************/ -void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value); - -/******************************************************************************* - * Hardware Abstraction Layer to get the timer frequency. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_timer_frequency(void); - -/******************************************************************************* - * Hardware Abstraction Layer to enable timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_enable_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to disable timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_disable_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to set timer interrupts. - * - * @param local_flag Internal interrupt flag. - ******************************************************************************/ -void sleeptimer_hal_set_int(uint8_t local_flag); - -/******************************************************************************* - * Hardware Abstraction Layer to get the sleeptimer's clock accuracy. - * - * @return Clock accuracy in PPM. - ******************************************************************************/ -uint16_t sleeptimer_hal_get_clock_accuracy(void); - -/******************************************************************************* - * Hardware Abstraction Layer to get the capture channel value. - * - * @note Not supported by all peripherals Sleeptimer can use. - * - * @return Capture value. - ******************************************************************************/ -uint32_t sleeptimer_hal_get_capture(void); - -/******************************************************************************* - * Hardware Abstraction Layer to reset PRS signal triggered by the associated - * peripheral. - * - * @note Not supported by all peripherals Sleeptimer can use. - ******************************************************************************/ -void sleeptimer_hal_reset_prs_signal(void); - -/******************************************************************************* - * Hardware Abstraction Layer to disable PRS compare and capture channel. - * - * @note Not supported by all peripherals Sleeptimer can use. - ******************************************************************************/ -void sleeptimer_hal_disable_prs_compare_and_capture_channel(void); - -/******************************************************************************* - * Process the timer interrupt. - * - * @param flags Internal interrupt flag. - ******************************************************************************/ -void process_timer_irq(uint8_t local_flag); - -#ifdef __cplusplus -} -#endif - -#endif /* SL_SLEEPTIMER_HAL_H */ +/***************************************************************************//** + * @file + * @brief SLEEPTIMER hardware abstraction layer definition. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_SLEEPTIMER_HAL_H +#define SL_SLEEPTIMER_HAL_H + +#include +#include +#include +#include "em_device.h" +#include "sli_sleeptimer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Hardware Abstraction Layer of the sleep timer init. + ******************************************************************************/ +void sleeptimer_hal_init_timer(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the current timer count. + * + * @return Value in ticks of the timer counter. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_counter(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get a timer comparator value. + * + * @return Value in ticks of the timer comparator. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_compare(void); + +/******************************************************************************* + * Hardware Abstraction Layer to set a timer comparator value. + * + * @param value Number of ticks to set. + ******************************************************************************/ +void sleeptimer_hal_set_compare(uint32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to set a comparator value to trigger a + * peripheral request signal to initialize. + * + * @param value Number of ticks to set. + ******************************************************************************/ +void sleeptimer_hal_set_compare_prs_hfxo_startup(int32_t value); + +/******************************************************************************* + * Hardware Abstraction Layer to get the timer frequency. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_timer_frequency(void); + +/******************************************************************************* + * Hardware Abstraction Layer to enable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_enable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to disable timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_disable_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to set timer interrupts. + * + * @param local_flag Internal interrupt flag. + ******************************************************************************/ +void sleeptimer_hal_set_int(uint8_t local_flag); + +/******************************************************************************* + * Hardware Abstraction Layer to get the sleeptimer's clock accuracy. + * + * @return Clock accuracy in PPM. + ******************************************************************************/ +uint16_t sleeptimer_hal_get_clock_accuracy(void); + +/******************************************************************************* + * Hardware Abstraction Layer to get the capture channel value. + * + * @note Not supported by all peripherals Sleeptimer can use. + * + * @return Capture value. + ******************************************************************************/ +uint32_t sleeptimer_hal_get_capture(void); + +/******************************************************************************* + * Hardware Abstraction Layer to reset PRS signal triggered by the associated + * peripheral. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +void sleeptimer_hal_reset_prs_signal(void); + +/******************************************************************************* + * Hardware Abstraction Layer to disable PRS compare and capture channel. + * + * @note Not supported by all peripherals Sleeptimer can use. + ******************************************************************************/ +void sleeptimer_hal_disable_prs_compare_and_capture_channel(void); + +/******************************************************************************* + * Process the timer interrupt. + * + * @param flags Internal interrupt flag. + ******************************************************************************/ +void process_timer_irq(uint8_t local_flag); + +#ifdef __cplusplus +} +#endif + +#endif /* SL_SLEEPTIMER_HAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h index 9bdd8ea..597a00c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_init.h @@ -1,153 +1,153 @@ -/***************************************************************************//** - * @file - * @brief System Initialization. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SYSTEM_INIT_H -#define SL_SYSTEM_INIT_H - -/***************************************************************************//** - * @addtogroup system System Initialization and Action Processing - * @brief System Initialization and Action Processing - * @details - * ### System Init - * System Init provides a function for initializing the system and the products: - * - * - sl_system_init(). - * - * This function calls a set of functions that are automatically generated - * and located in `autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - platform_init -> sl_platform_init() - * - driver_init -> sl_driver_init() - * - service_init -> sl_service_init() - * - stack_init -> sl_stack_init() - * - internal_app_init -> sl_internal_app_init() - * - * These events are fired in the order listed above when `sl_system_init()` - * is called. - * - * ### System Kernel - * - * System Kernel component provides a function for starting the kernel: - * - * - sl_system_kernel_start(). - * - * This function calls a functions that is automatically generated - * and located in `$autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - kernel_start -> sl_kernel_start() - * - * The event is fired when `sl_system_kernel_start()` is called. - * - * ### System Process Action - * - * System Process Action component provides a function for running - * the products from a super loop: - * - * - sl_system_process_action(). - * - * This function calls a set of functions that are automatically generated - * and located in `$autogen/sl_event_handler.c`. Handlers can be registered - * for the following events using the Event Handler API provided by the - * Event Handler component: - * - * - platform_process_action -> sl_platform_process_action() - * - service_process_action -> sl_service_process_action() - * - stack_process_action -> sl_stack_process_action() - * - internal_app_process_action -> sl_internal_process_action() - * - * These events are fired in the order listed above when `sl_system_process_action()` - * is called. - * - * Usage example: - * - * @code{.c} - * #if defined(SL_COMPONENT_CATALOG_PRESENT) - * #include "sl_component_catalog.h" - * #endif - * #include "sl_system_init.h" - * #include "sl_power_manager.h" - * #include "app.h" - * #if defined(SL_CATALOG_KERNEL_PRESENT) - * #include "sl_system_kernel.h" - * #else - * #include "sl_system_process_action.h" - * #endif - * - * int main(void) - * { - * // Initialize Silicon Labs device, system, service(s) and protocol stack(s). - * // Note that if the kernel is present, processing task(s) will be created by - * // this call. - * sl_system_init(); - * - * // Initialize the application. - * app_init(); - * - * #if defined(SL_CATALOG_KERNEL_PRESENT) - * // Start the kernel. Task(s) created in app_init() will start running. - * sl_system_kernel_start(); - * #else - * do { - * // Do not remove this call: Silicon Labs components process action routine - * // must be called from the super loop. - * sl_system_process_action(); - * - * // Application process. - * app_process_action(); - * - * // Let the CPU go to sleep if the system allow it. - * sl_power_manager_sleep(); - * } while (1); - * #endif // SL_CATALOG_KERNEL_PRESENT - * } - * @endcode - * @{ - * - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Initialize Silicon Labs products - */ -void sl_system_init(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup system) */ - -#endif // SL_SYSTEM_INIT_H +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_INIT_H +#define SL_SYSTEM_INIT_H + +/***************************************************************************//** + * @addtogroup system System Initialization and Action Processing + * @brief System Initialization and Action Processing + * @details + * ### System Init + * System Init provides a function for initializing the system and the products: + * + * - sl_system_init(). + * + * This function calls a set of functions that are automatically generated + * and located in `autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_init -> sl_platform_init() + * - driver_init -> sl_driver_init() + * - service_init -> sl_service_init() + * - stack_init -> sl_stack_init() + * - internal_app_init -> sl_internal_app_init() + * + * These events are fired in the order listed above when `sl_system_init()` + * is called. + * + * ### System Kernel + * + * System Kernel component provides a function for starting the kernel: + * + * - sl_system_kernel_start(). + * + * This function calls a functions that is automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - kernel_start -> sl_kernel_start() + * + * The event is fired when `sl_system_kernel_start()` is called. + * + * ### System Process Action + * + * System Process Action component provides a function for running + * the products from a super loop: + * + * - sl_system_process_action(). + * + * This function calls a set of functions that are automatically generated + * and located in `$autogen/sl_event_handler.c`. Handlers can be registered + * for the following events using the Event Handler API provided by the + * Event Handler component: + * + * - platform_process_action -> sl_platform_process_action() + * - service_process_action -> sl_service_process_action() + * - stack_process_action -> sl_stack_process_action() + * - internal_app_process_action -> sl_internal_process_action() + * + * These events are fired in the order listed above when `sl_system_process_action()` + * is called. + * + * Usage example: + * + * @code{.c} + * #if defined(SL_COMPONENT_CATALOG_PRESENT) + * #include "sl_component_catalog.h" + * #endif + * #include "sl_system_init.h" + * #include "sl_power_manager.h" + * #include "app.h" + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * #include "sl_system_kernel.h" + * #else + * #include "sl_system_process_action.h" + * #endif + * + * int main(void) + * { + * // Initialize Silicon Labs device, system, service(s) and protocol stack(s). + * // Note that if the kernel is present, processing task(s) will be created by + * // this call. + * sl_system_init(); + * + * // Initialize the application. + * app_init(); + * + * #if defined(SL_CATALOG_KERNEL_PRESENT) + * // Start the kernel. Task(s) created in app_init() will start running. + * sl_system_kernel_start(); + * #else + * do { + * // Do not remove this call: Silicon Labs components process action routine + * // must be called from the super loop. + * sl_system_process_action(); + * + * // Application process. + * app_process_action(); + * + * // Let the CPU go to sleep if the system allow it. + * sl_power_manager_sleep(); + * } while (1); + * #endif // SL_CATALOG_KERNEL_PRESENT + * } + * @endcode + * @{ + * + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Initialize Silicon Labs products + */ +void sl_system_init(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_INIT_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h index a6dceba..c37dffa 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/inc/sl_system_process_action.h @@ -1,53 +1,53 @@ -/***************************************************************************//** - * @file - * @brief System process action. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#ifndef SL_SYSTEM_PROCESS_ACTION_H -#define SL_SYSTEM_PROCESS_ACTION_H - -/***************************************************************************//** - * @addtogroup system - * @{ - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * System processing action - */ -void sl_system_process_action(void); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup system) */ - -#endif // SL_SYSTEM_PROCESS_ACTION_H +/***************************************************************************//** + * @file + * @brief System process action. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#ifndef SL_SYSTEM_PROCESS_ACTION_H +#define SL_SYSTEM_PROCESS_ACTION_H + +/***************************************************************************//** + * @addtogroup system + * @{ + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * System processing action + */ +void sl_system_process_action(void); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup system) */ + +#endif // SL_SYSTEM_PROCESS_ACTION_H diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c index 9e4988f..595baf7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_init.c @@ -1,39 +1,39 @@ -/***************************************************************************//** - * @file - * @brief System Initialization. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_event_handler.h" - -void sl_system_init(void) -{ - sl_platform_init(); - sl_driver_init(); - sl_service_init(); - sl_stack_init(); - sl_internal_app_init(); -} +/***************************************************************************//** + * @file + * @brief System Initialization. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_init(void) +{ + sl_platform_init(); + sl_driver_init(); + sl_service_init(); + sl_stack_init(); + sl_internal_app_init(); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c index 83be324..a4be21c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/system/src/sl_system_process_action.c @@ -1,38 +1,38 @@ -/***************************************************************************//** - * @file - * @brief System process action. - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_event_handler.h" - -void sl_system_process_action(void) -{ - sl_platform_process_action(); - sl_service_process_action(); - sl_stack_process_action(); - sl_internal_app_process_action(); -} +/***************************************************************************//** + * @file + * @brief System process action. + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_event_handler.h" + +void sl_system_process_action(void) +{ + sl_platform_process_action(); + sl_service_process_action(); + sl_stack_process_action(); + sl_internal_app_process_action(); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h index e26a356..67dfa4c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/inc/sl_udelay.h @@ -1,78 +1,78 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef UDELAY_H -#define UDELAY_H - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************************************************************//** - * @addtogroup udelay Microsecond Delay - * @brief Microsecond delay function - * @{ - ******************************************************************************/ - -/** - * @brief - * Delay a number of microseconds - * - * @details - * This function will use a busy loop to delay code execution by a certain - * number of microseconds before returning to the caller. This function will - * not return to the caller earlier than the time given as the input parameter. - * This function will not use any hardware timing peripherals, it is using - * the core clock frequency to calculate the delay. - * - * Note that there will always be some overhead associated with calling this - * function in addition to the internal delay loop. This overhead is relatively - * small when the delay is large (>= 100us). - * - * The accuracy of this delay loop will be affected by interrupts and context - * switching. If accuracy is needed, a hardware timer should be used - * to handle delays. - * - * @param[in] us - * This is the number of microseconds to delay execution. This function will - * return after this amount of time has elapsed. Minimum value is 0 us and - * maximum value is 100 000 us (100 ms). It is however recommended to use - * the sleeptimer api for delays of more than 1 ms as it is using a hardware - * counter and will result in better accuracy. - */ -void sl_udelay_wait(unsigned us); - -#ifdef __cplusplus -} -#endif - -/** @} (end addtogroup udelay) */ - -#endif +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef UDELAY_H +#define UDELAY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************************************************************//** + * @addtogroup udelay Microsecond Delay + * @brief Microsecond delay function + * @{ + ******************************************************************************/ + +/** + * @brief + * Delay a number of microseconds + * + * @details + * This function will use a busy loop to delay code execution by a certain + * number of microseconds before returning to the caller. This function will + * not return to the caller earlier than the time given as the input parameter. + * This function will not use any hardware timing peripherals, it is using + * the core clock frequency to calculate the delay. + * + * Note that there will always be some overhead associated with calling this + * function in addition to the internal delay loop. This overhead is relatively + * small when the delay is large (>= 100us). + * + * The accuracy of this delay loop will be affected by interrupts and context + * switching. If accuracy is needed, a hardware timer should be used + * to handle delays. + * + * @param[in] us + * This is the number of microseconds to delay execution. This function will + * return after this amount of time has elapsed. Minimum value is 0 us and + * maximum value is 100 000 us (100 ms). It is however recommended to use + * the sleeptimer api for delays of more than 1 ms as it is using a hardware + * counter and will result in better accuracy. + */ +void sl_udelay_wait(unsigned us); + +#ifdef __cplusplus +} +#endif + +/** @} (end addtogroup udelay) */ + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c index aa2931e..51860ea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay.c @@ -1,69 +1,69 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_udelay.h" -#include "em_device.h" -#include "sl_assert.h" -#include - -/* The Cortex-M33 has a faster execution of the hw loop - * with the same arm instructions. */ -#if defined(__CORTEX_M) && (__CORTEX_M == 33U) - #define HW_LOOP_CYCLE 3 -#else - #define HW_LOOP_CYCLE 4 -#endif - -void sli_delay_loop(unsigned n); - -void sl_udelay_wait(unsigned us) -{ - uint32_t freq_khz; - uint32_t ns_period; - uint32_t cycles; - uint32_t loops; - - freq_khz = SystemCoreClockGet() / 1000U; - if (freq_khz == 0) { - EFM_ASSERT(false); - return; - } - - ns_period = 1000000U / freq_khz; - if (ns_period == 0) { - EFM_ASSERT(false); - return; - } - - cycles = us * 1000U / ns_period; - loops = cycles / HW_LOOP_CYCLE; - if (loops > 0U) { - sli_delay_loop(loops); - } -} +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_udelay.h" +#include "em_device.h" +#include "sl_assert.h" +#include + +/* The Cortex-M33 has a faster execution of the hw loop + * with the same arm instructions. */ +#if defined(__CORTEX_M) && (__CORTEX_M == 33U) + #define HW_LOOP_CYCLE 3 +#else + #define HW_LOOP_CYCLE 4 +#endif + +void sli_delay_loop(unsigned n); + +void sl_udelay_wait(unsigned us) +{ + uint32_t freq_khz; + uint32_t ns_period; + uint32_t cycles; + uint32_t loops; + + freq_khz = SystemCoreClockGet() / 1000U; + if (freq_khz == 0) { + EFM_ASSERT(false); + return; + } + + ns_period = 1000000U / freq_khz; + if (ns_period == 0) { + EFM_ASSERT(false); + return; + } + + cycles = us * 1000U / ns_period; + loops = cycles / HW_LOOP_CYCLE; + if (loops > 0U) { + sli_delay_loop(loops); + } +} diff --git a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S index bb16feb..2fcc720 100644 --- a/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S +++ b/locator_ncp/gecko_sdk_4.4.1/platform/service/udelay/src/sl_udelay_armv6m_gcc.S @@ -1,60 +1,60 @@ -/***************************************************************************//** - * @file - * @brief Microsecond delay. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - - .text - .align 4 - .syntax unified - .thumb_func - .global sli_delay_loop - -/* - * @brief - * Hardware delay loop - * - * @detail - * This is the hardware specific delay loop. It is designed specifically to - * execute in 4 or 3 cycles for each iteration depending on the architecture. - * Using this information the caller can use the core clock frequency to - * calculate the number of loops required in order to delay a specific time - * period. - * - * @param[in] n (r0) - * n is the number of loops to execute. Each loop will execute in 4 cycles. - * Note that we assume that r0 > 0, so this invariant should be checked by - * the caller. - */ -sli_delay_loop: - subs r0, r0, #1 - beq done - b.n sli_delay_loop -done: - bx lr - - .end +/***************************************************************************//** + * @file + * @brief Microsecond delay. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + + .text + .align 4 + .syntax unified + .thumb_func + .global sli_delay_loop + +/* + * @brief + * Hardware delay loop + * + * @detail + * This is the hardware specific delay loop. It is designed specifically to + * execute in 4 or 3 cycles for each iteration depending on the architecture. + * Using this information the caller can use the core clock frequency to + * calculate the number of loops required in order to delay a specific time + * period. + * + * @param[in] n (r0) + * n is the number of loops to execute. Each loop will execute in 4 cycles. + * Note that we assume that r0 > 0, so this invariant should be checked by + * the caller. + */ +sli_delay_loop: + subs r0, r0, #1 + beq done + b.n sli_delay_loop +done: + bx lr + + .end diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/api/sl_bt.xapi b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/api/sl_bt.xapi index abcf61c..febcff1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/api/sl_bt.xapi +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/api/sl_bt.xapi @@ -1,3712 +1,3712 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h index b245842..25f2a28 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/bgstack/ll/inc/sl_btctrl_linklayer.h @@ -1,307 +1,307 @@ -/***************************************************************************//** - * @brief Bluetooth Link Layer configuration API - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef _SL_BTCTRL_LINKLAYER_H_ -#define _SL_BTCTRL_LINKLAYER_H_ -#include "sl_status.h" -#include - -void sl_bt_controller_init(void); - -void sl_bt_controller_deinit(void); - -void sl_btctrl_init(void); - -/** - * Allocate memory buffers for controller - * - * @param memsize size of memory to allocate - * @returns number of memory buffers allocated - */ -uint32_t sl_btctrl_init_mem(uint32_t memsize); - -/** - * Configures how many maximum sized ACL data packets - * can the controller store. - */ -void sl_btctrl_configure_le_buffer_size(uint8_t count); - -/** - * Release all memory allocated by controller - */ -void sli_btctrl_deinit_mem(void); - -void sli_btctrl_set_interrupt_priorities(); - -sl_status_t sl_btctrl_init_ll(void); - -void sli_btctrl_set_address(uint8_t *address); - -//Initialize memory objects used by LinkLayer -//In future these should be configured individually -sl_status_t sl_btctrl_init_basic(uint8_t connections, uint8_t adv_sets, uint8_t whitelist); - -void sli_btctrl_events_init(void); - -enum sl_btctrl_channelmap_flags{ - SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY = 0x01, - SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY= 0x02, -}; - -/** - * Initialize and enable adaptive frequency hopping - */ -sl_status_t sl_btctrl_init_afh(uint32_t flags); - -/** - * Enable high power use under appropriate conditions - */ -void sl_btctrl_init_highpower(void); - -/** - * @brief Initilize periodic advertiser - */ -void sl_btctrl_init_periodic_adv(); - -/** - * @brief Initilize periodic advertiser - */ -void sl_btctrl_init_periodic_scan(); - -/** - * Configuration for Periodic Advertising with Responses. - */ -struct sl_btctrl_pawr_advertiser_config { - /** - * Number of advertising sets supporting PAwR. - * If set to zero, previously allocated PAwR sets are only freed. */ - uint8_t max_pawr_sets; - /** - * Hint to the controller what will be the maximum advertised data length. - * The value does not prevent using longer advertising data. Value zero means - * that maximum data length can expected to be up to the length of Periodic - * Advertising Delay. */ - uint8_t max_advertised_data_length_hint; - /** - * The number of subevent advertising packets requested from the host - * at once. */ - uint8_t subevent_data_request_count; - /** - * How many subevents before airing a subevent its data is requested from - * the host. */ - uint8_t subevent_data_request_advance; -}; - -/** - * Configuration of synchronizer for Periodic Advertising with Responses. - */ -struct sl_btctrl_pawr_synchronizer_config { - /** - * Number of advertising sets supporting PArR. - * If set to zero, previously allocated PArR sets are only freed. */ - uint8_t max_pawr_sets; -}; - -/** - * @brief Enable and initialize support for the PAwR advertiser. - * @param[in] pawr_adv_config PAwR advertiser configuration. - * @return SL_STATUS_OK, or an appropriate error code. */ -sl_status_t sl_btctrl_pawr_advertiser_configure(struct sl_btctrl_pawr_advertiser_config *pawr_adv_config); - -/** - * @brief Enable and initialize support for PAwR sync/receiver. - * @param[in] pawr_sync_config PAwR synchronizer configuration. - * @return SL_STATUS_OK, or an appropriate error code. */ -sl_status_t sl_btctrl_pawr_synchronizer_configure(struct sl_btctrl_pawr_synchronizer_config *pawr_sync_config); - -/** - * @brief Allocate memory for synchronized scanners - * - * @param num_scan Number of Periodic Scanners Allowed - * @return SL_STATUS_OK if allocation was succesfull, failure reason otherwise - */ -sl_status_t sl_btctrl_alloc_periodic_scan(uint8_t num_scan); - -/** - * @brief Allocate memory for periodic advertisers - * - * @param num_adv Number of advertisers to allocate - */ -sl_status_t sl_btctrl_alloc_periodic_adv(uint8_t num_adv); - -/** - * Call to import the conn scheduler state variables in the binary - */ -void sli_btctrl_enable_conn_scheduler_state(void); - -/** - * @brief Set maximum number of advertisement reports allowed to be queued - * - * @param num_adv Maximum number of advertisement reports allowed to be queued - */ -void sl_btctrl_configure_max_queued_adv_reports(uint8_t num_reports); - -/** - * Call to enable the even connection scheduling algorithm. - * This function should be called before link layer initialization. - */ -void sl_btctrl_enable_even_connsch(); - -/** - * Call to enable the PAwR aware connection scheduling algorithm. - * This function should be called before link layer initialization. - */ -void sl_btctrl_enable_pawr_connsch(); - -/** - * Call to enable the legacy connection scheduling algorithm. - * This function should be called before link layer initialization. - */ -void sl_btctrl_enable_legacy_connsch(); - -/** - * Call to enable connection statistics collection. - */ -void sl_btctrl_init_conn_statistics(void); - -/** - * Call to initialize multiprotocol - * in bluetooth controller - */ -void sl_btctrl_init_multiprotocol(); - -/** - * Link with symbol to enable radio watchdog - */ -void sl_btctrl_enable_radio_watchdog(); - -/** - * Initialize CTE receiver - */ -sl_status_t sl_btctrl_init_cte_receiver(); - -/** - * Initialize CTE transmitter - */ -sl_status_t sl_btctrl_init_cte_transmitter(); - -/** - * Initialize both CTE receiver and transmitter - * - * Note: This is for backward compatibility. It is recommend to - * use sl_btctrl_init_cte_receiver and sl_btctrl_init_cte_transmitter - * functions instead. - */ -sl_status_t sl_btctrl_init_cte(); - -/** - * Initialize Channel Sounding - */ -struct sl_btctrl_cs_config { - /** number of channel sounding configurations per connection */ - uint8_t configs_per_connection; - /** number of simultaneous channel sounding procedures */ - uint8_t procedures; -}; - -sl_status_t sl_btctrl_init_cs(const struct sl_btctrl_cs_config *config); - -/** - * Check if event bitmap indicates pending events - * @return bool pending events - */ -bool sli_pending_btctrl_events(void); - -/** - * Disable the support for Coded and Simulscan PHYs. - */ -void sl_btctrl_disable_coded_phy(void); - -/** - * Disable the support for 2M PHY. - */ -void sl_btctrl_disable_2m_phy(void); - -/** - * Initialize adv component - */ -void sl_btctrl_init_adv(void); - -void sl_btctrl_init_conn(void); - -void sl_btctrl_init_phy(void); - -void sl_btctrl_init_adv_ext(void); - -void sl_btctrl_init_privacy(void); - -sl_status_t sl_btctrl_allocate_resolving_list_memory(uint8_t resolvingListSize); - -/** - * @brief Initialize extended scanner state - * - */ -void sl_btctrl_init_scan_ext(void); - -void sl_btctrl_init_scan(void); - -/** - * @brief return true if controller is initialized - * - */ -bool sl_btctrl_is_initialized(); - -/** - * @brief Sets PAST initiator feature bit, - * and links in PAST sender and ll_adv_sync symbols to the project. - */ -void sl_btctrl_init_past_local_sync_transfer(void); - -/** - * @brief Sets PAST initiator feature bit, - * and links in PAST sender, ll_scan_sync and ll_scan_sync_registry symbols to the project. - */ -void sl_btctrl_init_past_remote_sync_transfer(void); - -/** - * @brief Sets PAST receiver feature bit, - * and links in PAST receiver, ll_scan_sync and ll_scan_sync_registry symbols to the project. - */ -void sl_btctrl_init_past_receiver(void); - -/** - * @brief Configure how often to send the Number Of Completed Packets HCI event. - * @param[in] packets When the controller has transmitted this number of ACL data packets it will send - * the Number Of Completed Packets HCI event to the host. - * @param[in] events When this number of connection events have passed and the controller did not yet report - * all the transmitted packets, then it will send the Number Of Completed Packets HCI event to the host. - */ -void sl_btctrl_configure_completed_packets_reporting(uint8_t packets, uint8_t events); - -#endif +/***************************************************************************//** + * @brief Bluetooth Link Layer configuration API + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef _SL_BTCTRL_LINKLAYER_H_ +#define _SL_BTCTRL_LINKLAYER_H_ +#include "sl_status.h" +#include + +void sl_bt_controller_init(void); + +void sl_bt_controller_deinit(void); + +void sl_btctrl_init(void); + +/** + * Allocate memory buffers for controller + * + * @param memsize size of memory to allocate + * @returns number of memory buffers allocated + */ +uint32_t sl_btctrl_init_mem(uint32_t memsize); + +/** + * Configures how many maximum sized ACL data packets + * can the controller store. + */ +void sl_btctrl_configure_le_buffer_size(uint8_t count); + +/** + * Release all memory allocated by controller + */ +void sli_btctrl_deinit_mem(void); + +void sli_btctrl_set_interrupt_priorities(); + +sl_status_t sl_btctrl_init_ll(void); + +void sli_btctrl_set_address(uint8_t *address); + +//Initialize memory objects used by LinkLayer +//In future these should be configured individually +sl_status_t sl_btctrl_init_basic(uint8_t connections, uint8_t adv_sets, uint8_t whitelist); + +void sli_btctrl_events_init(void); + +enum sl_btctrl_channelmap_flags{ + SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY = 0x01, + SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY= 0x02, +}; + +/** + * Initialize and enable adaptive frequency hopping + */ +sl_status_t sl_btctrl_init_afh(uint32_t flags); + +/** + * Enable high power use under appropriate conditions + */ +void sl_btctrl_init_highpower(void); + +/** + * @brief Initilize periodic advertiser + */ +void sl_btctrl_init_periodic_adv(); + +/** + * @brief Initilize periodic advertiser + */ +void sl_btctrl_init_periodic_scan(); + +/** + * Configuration for Periodic Advertising with Responses. + */ +struct sl_btctrl_pawr_advertiser_config { + /** + * Number of advertising sets supporting PAwR. + * If set to zero, previously allocated PAwR sets are only freed. */ + uint8_t max_pawr_sets; + /** + * Hint to the controller what will be the maximum advertised data length. + * The value does not prevent using longer advertising data. Value zero means + * that maximum data length can expected to be up to the length of Periodic + * Advertising Delay. */ + uint8_t max_advertised_data_length_hint; + /** + * The number of subevent advertising packets requested from the host + * at once. */ + uint8_t subevent_data_request_count; + /** + * How many subevents before airing a subevent its data is requested from + * the host. */ + uint8_t subevent_data_request_advance; +}; + +/** + * Configuration of synchronizer for Periodic Advertising with Responses. + */ +struct sl_btctrl_pawr_synchronizer_config { + /** + * Number of advertising sets supporting PArR. + * If set to zero, previously allocated PArR sets are only freed. */ + uint8_t max_pawr_sets; +}; + +/** + * @brief Enable and initialize support for the PAwR advertiser. + * @param[in] pawr_adv_config PAwR advertiser configuration. + * @return SL_STATUS_OK, or an appropriate error code. */ +sl_status_t sl_btctrl_pawr_advertiser_configure(struct sl_btctrl_pawr_advertiser_config *pawr_adv_config); + +/** + * @brief Enable and initialize support for PAwR sync/receiver. + * @param[in] pawr_sync_config PAwR synchronizer configuration. + * @return SL_STATUS_OK, or an appropriate error code. */ +sl_status_t sl_btctrl_pawr_synchronizer_configure(struct sl_btctrl_pawr_synchronizer_config *pawr_sync_config); + +/** + * @brief Allocate memory for synchronized scanners + * + * @param num_scan Number of Periodic Scanners Allowed + * @return SL_STATUS_OK if allocation was succesfull, failure reason otherwise + */ +sl_status_t sl_btctrl_alloc_periodic_scan(uint8_t num_scan); + +/** + * @brief Allocate memory for periodic advertisers + * + * @param num_adv Number of advertisers to allocate + */ +sl_status_t sl_btctrl_alloc_periodic_adv(uint8_t num_adv); + +/** + * Call to import the conn scheduler state variables in the binary + */ +void sli_btctrl_enable_conn_scheduler_state(void); + +/** + * @brief Set maximum number of advertisement reports allowed to be queued + * + * @param num_adv Maximum number of advertisement reports allowed to be queued + */ +void sl_btctrl_configure_max_queued_adv_reports(uint8_t num_reports); + +/** + * Call to enable the even connection scheduling algorithm. + * This function should be called before link layer initialization. + */ +void sl_btctrl_enable_even_connsch(); + +/** + * Call to enable the PAwR aware connection scheduling algorithm. + * This function should be called before link layer initialization. + */ +void sl_btctrl_enable_pawr_connsch(); + +/** + * Call to enable the legacy connection scheduling algorithm. + * This function should be called before link layer initialization. + */ +void sl_btctrl_enable_legacy_connsch(); + +/** + * Call to enable connection statistics collection. + */ +void sl_btctrl_init_conn_statistics(void); + +/** + * Call to initialize multiprotocol + * in bluetooth controller + */ +void sl_btctrl_init_multiprotocol(); + +/** + * Link with symbol to enable radio watchdog + */ +void sl_btctrl_enable_radio_watchdog(); + +/** + * Initialize CTE receiver + */ +sl_status_t sl_btctrl_init_cte_receiver(); + +/** + * Initialize CTE transmitter + */ +sl_status_t sl_btctrl_init_cte_transmitter(); + +/** + * Initialize both CTE receiver and transmitter + * + * Note: This is for backward compatibility. It is recommend to + * use sl_btctrl_init_cte_receiver and sl_btctrl_init_cte_transmitter + * functions instead. + */ +sl_status_t sl_btctrl_init_cte(); + +/** + * Initialize Channel Sounding + */ +struct sl_btctrl_cs_config { + /** number of channel sounding configurations per connection */ + uint8_t configs_per_connection; + /** number of simultaneous channel sounding procedures */ + uint8_t procedures; +}; + +sl_status_t sl_btctrl_init_cs(const struct sl_btctrl_cs_config *config); + +/** + * Check if event bitmap indicates pending events + * @return bool pending events + */ +bool sli_pending_btctrl_events(void); + +/** + * Disable the support for Coded and Simulscan PHYs. + */ +void sl_btctrl_disable_coded_phy(void); + +/** + * Disable the support for 2M PHY. + */ +void sl_btctrl_disable_2m_phy(void); + +/** + * Initialize adv component + */ +void sl_btctrl_init_adv(void); + +void sl_btctrl_init_conn(void); + +void sl_btctrl_init_phy(void); + +void sl_btctrl_init_adv_ext(void); + +void sl_btctrl_init_privacy(void); + +sl_status_t sl_btctrl_allocate_resolving_list_memory(uint8_t resolvingListSize); + +/** + * @brief Initialize extended scanner state + * + */ +void sl_btctrl_init_scan_ext(void); + +void sl_btctrl_init_scan(void); + +/** + * @brief return true if controller is initialized + * + */ +bool sl_btctrl_is_initialized(); + +/** + * @brief Sets PAST initiator feature bit, + * and links in PAST sender and ll_adv_sync symbols to the project. + */ +void sl_btctrl_init_past_local_sync_transfer(void); + +/** + * @brief Sets PAST initiator feature bit, + * and links in PAST sender, ll_scan_sync and ll_scan_sync_registry symbols to the project. + */ +void sl_btctrl_init_past_remote_sync_transfer(void); + +/** + * @brief Sets PAST receiver feature bit, + * and links in PAST receiver, ll_scan_sync and ll_scan_sync_registry symbols to the project. + */ +void sl_btctrl_init_past_receiver(void); + +/** + * @brief Configure how often to send the Number Of Completed Packets HCI event. + * @param[in] packets When the controller has transmitted this number of ACL data packets it will send + * the Number Of Completed Packets HCI event to the host. + * @param[in] events When this number of connection events have passed and the controller did not yet report + * all the transmitted packets, then it will send the Number Of Completed Packets HCI event to the host. + */ +void sl_btctrl_configure_completed_packets_reporting(uint8_t packets, uint8_t events); + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h index df5e418..e6643ea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bgapi.h @@ -1,310 +1,310 @@ -/***************************************************************************//** - * @brief Silicon Labs BGAPI types and macros - ******************************************************************************* - * # License - * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BGAPI_H -#define SL_BGAPI_H - -#include -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Macros to declare deprecated functions */ -#if defined(__IAR_SYSTEMS_ICC__) - #define SL_BGAPI_DEPRECATED _Pragma("deprecated") -#elif defined(__GNUC__) - #define SL_BGAPI_DEPRECATED __attribute__((deprecated)) -#else - #define SL_BGAPI_DEPRECATED -#endif - -/* Compatibility */ -#ifndef PACKSTRUCT -/*Default packed configuration*/ -#ifdef __GNUC__ -#ifdef _WIN32 -#define PACKSTRUCT(decl) decl __attribute__((__packed__, gcc_struct)) -#else -#define PACKSTRUCT(decl) decl __attribute__((__packed__)) -#endif -#define ALIGNED __attribute__((aligned(0x4))) -#elif __IAR_SYSTEMS_ICC__ - -#define PACKSTRUCT(decl) __packed decl - -#define ALIGNED -#elif _MSC_VER /*msvc*/ - -#define PACKSTRUCT(decl) __pragma(pack(push, 1) ) decl __pragma(pack(pop) ) -#define ALIGNED -#else -#define PACKSTRUCT(a) a PACKED -#endif -#endif - -/** - * The maximum BGAPI command payload size. - */ -#ifndef SL_BGAPI_MAX_PAYLOAD_SIZE -#define SL_BGAPI_MAX_PAYLOAD_SIZE 256 -#endif - -/***************************************************************************//** - * @addtogroup sl_bgapi_types BGAPI Types - * @brief Common types in BGAPI protocol - * @{ - */ - -#ifndef SL_BT_TYPE_UINT8ARRARY -#define SL_BT_TYPE_UINT8ARRARY -/** @brief Variable-length uint8_t array. Maximum length: 255 */ -typedef struct { - uint8_t len; /**< Number of bytes stored in @p data */ - uint8_t data[]; /**< Data bytes*/ -} uint8array; -#endif - -#ifndef SL_BT_TYPE_BYTE_ARRARY -#define SL_BT_TYPE_BYTE_ARRARY -/** @brief Variable-length int8_t array. Maximum length: 65535 */ -typedef struct { - uint16_t len; /**< Number of bytes stored in @p data */ - int8_t data[]; /**< Data bytes*/ -} byte_array; -#endif - -#ifndef SL_BT_TYPE_BDADDR -#define SL_BT_TYPE_BDADDR -/** @brief Bluetooth address */ -typedef struct { - uint8_t addr[6]; /**< @brief Bluetooth address in reverse byte order */ -} bd_addr; -#endif - -#ifndef SL_BT_TYPE_UUID128 -#define SL_BT_TYPE_UUID128 -/** @brief 128-bit UUID */ -typedef struct { - uint8_t data[16]; /**< 128-bit UUID */ -} uuid_128; -#endif - -#ifndef SL_BT_TYPE_AES_KEY128 -#define SL_BT_TYPE_AES_KEY128 -/** @brief 128-bit AES key */ -typedef struct { - uint8_t data[16]; /**< 128-bit AES key */ -} aes_key_128; -#endif - -#ifndef SL_BT_TYPE_UUID16 -#define SL_BT_TYPE_UUID16 -/** @brief 16-bit UUID */ -typedef struct { - uint8_t data[2]; /**< 16-bit UUID */ -} sl_bt_uuid_16_t; -#endif - -#ifndef SL_BT_TYPE_UUID64 -#define SL_BT_TYPE_UUID64 -/** @brief 64-bit UUID */ -typedef struct { - uint8_t data[8]; /**< 64-bit UUID */ -} sl_bt_uuid_64_t; -#endif - -/** @} */ // end addtogroup sl_bgapi_types -/******************************************************************************/ - -/** @brief Internal function prototype for BGAPI command handlers */ -typedef void (*sl_bgapi_handler)(const void*); - -typedef enum sl_bgapi_msg_types { - sl_bgapi_msg_type_cmd = 0x00, - sl_bgapi_msg_type_rsp = 0x00, - sl_bgapi_msg_type_evt = 0x80 -} sl_bgapi_msg_types_t; - -enum sl_bgapi_dev_types { - sl_bgapi_dev_type_app = 0x00, - sl_bgapi_dev_type_bt = 0x20, - sl_bgapi_dev_type_btmesh = 0x28, - sl_bgapi_dev_type_bgapi_debug = 0x30, -}; - -/***************************************************************************//** - * @addtogroup sl_bgapi_types BGAPI Types - * @brief Common types in BGAPI protocol - * @{ - */ - -/** - * @brief The length of a BGAPI message header which is 4 bytes - */ -#define SL_BGAPI_MSG_HEADER_LEN (4) - -/** - * @brief Get the device type of a BGAPI message - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_DEVICE_TYPE(HDR) ((HDR) & 0x38) - -/** - * @brief Get the identifier of a BGAPI message including device type, class ID, - * message type and message ID. - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_ID(HDR) ((HDR) & 0xffff00f8) - -/** - * @brief Get the data payload length in a BGAPI message. - * - * @param HDR The header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_LEN(HDR) ((((HDR) & 0x7) << 8) | (((HDR) & 0xff00) >> 8)) - -/** - * @brief The bit indicating whether data of a BGAPI message is encrypted - */ -#define SL_BGAPI_BIT_ENCRYPTED (1 << 6) // Bit - -/** - * @brief Check whether data of a BGAPI message is encrypted. - * - * @param HDR The BGAPI header of the message as a uint32_t integer - */ -#define SL_BGAPI_MSG_ENCRYPTED(HDR) ((HDR)&SL_BGAPI_BIT_ENCRYPTED) - -/** @} */ // end addtogroup sl_bgapi_types -/******************************************************************************/ - -/** - * Internal function for setting the command handler function. Used by API library. - * - * @param cmd_handler_delegate Pointer to command handler delegate function - */ -void sli_bgapi_set_cmd_handler_delegate(void (*cmd_handler_delegate)(uint32_t, - sl_bgapi_handler, - const void*)); - -/** - * @addtogroup sl_bgapi_functions BGAPI Functions - * @{ - * - * @brief Functions provided by the BGAPI protocol - */ - -/** - * @brief Lock the BGAPI for exclusive access. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format in an application that - * uses an RTOS. Normal application code that issues BGAPI commands by calling - * API functions defined by protocol stacks must never call this function - * directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - * - * @return SL_STATUS_OK if the lock has been obtained, otherwise an error code - */ -sl_status_t sl_bgapi_lock(void); - -/** - * @brief Release the lock obtained by @ref sl_bgapi_lock - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format in an application that - * uses an RTOS. Normal application code that issues BGAPI commands by calling - * API functions defined by protocol stacks must never call this function - * directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - */ -void sl_bgapi_unlock(void); - -/** - * @brief Handle a BGAPI command in binary format. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format. Normal application code - * that issues BGAPI commands by calling API functions defined by protocol - * stacks must never call this function directly. - * - * If the application uses an RTOS, the caller must protect the BGAPI handling - * by obtaining the BGAPI lock with @ref sl_bgapi_lock, handle the command with - * @ref sl_bgapi_handle_command, read the response from the buffer returned by - * @ref sl_bgapi_get_command_response, and then release the lock with @ref - * sl_bgapi_unlock. Here's an example of the full sequence that's required: - * - * @code - * // Lock BGAPI for exclusive access - * sl_status_t status = sl_bgapi_lock(); - * if (status != SL_STATUS_OK) { - * // Locking will only fail if there are fatal unrecoverable errors with the - * // RTOS primitives, so caller may choose to just assert in case of errors. - * } - * - * // Process the command - * sl_bgapi_handle_command(hdr, data); - * - * // Read the response - * void *rsp = sl_bgapi_get_command_response(); - * uint32_t rsp_header = *((uint32_t *)rsp); - * size_t rsp_len = SL_BGAPI_MSG_LEN(rsp_header) + SL_BGAPI_MSG_HEADER_LEN; - * // Send the `rsp_len` bytes of response starting from `rsp` - * - * // Finally unlock the BGAPI to allow other commands to proceed - * sl_bgapi_unlock(); - * @endcode - * - * Empty stub implementations are provided for @ref sl_bgapi_lock and @ref - * sl_bgapi_unlock, so the same sequence can be used for all NCP/CPC - * implementations even if an RTOS is not present. - * - * @param[in] hdr The BGAPI command header - * @param[in] data The payload data associated with the command - */ -void sl_bgapi_handle_command(uint32_t hdr, const void* data); - -/** - * @brief Get the response of a handled BGAPI command. - * - * NOTE: This function is provided for NCP/CPC components that need to handle - * BGAPI commands and responses in their binary format. Normal application code - * that issues BGAPI commands by calling API functions defined by protocol - * stacks must never call this function directly. - * - * See the documentation of @ref sl_bgapi_handle_command for the full sequence - * that must be followed when processing commands in their binary format. - * - * @return Pointer to the BGAPI response structure that was filled when the - * command was executed in @ref sl_bgapi_handle_command. - */ -void* sl_bgapi_get_command_response(void); - -/** @} */ // end addtogroup sl_bgapi_functions - -#ifdef __cplusplus -} -#endif - -#endif +/***************************************************************************//** + * @brief Silicon Labs BGAPI types and macros + ******************************************************************************* + * # License + * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BGAPI_H +#define SL_BGAPI_H + +#include +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Macros to declare deprecated functions */ +#if defined(__IAR_SYSTEMS_ICC__) + #define SL_BGAPI_DEPRECATED _Pragma("deprecated") +#elif defined(__GNUC__) + #define SL_BGAPI_DEPRECATED __attribute__((deprecated)) +#else + #define SL_BGAPI_DEPRECATED +#endif + +/* Compatibility */ +#ifndef PACKSTRUCT +/*Default packed configuration*/ +#ifdef __GNUC__ +#ifdef _WIN32 +#define PACKSTRUCT(decl) decl __attribute__((__packed__, gcc_struct)) +#else +#define PACKSTRUCT(decl) decl __attribute__((__packed__)) +#endif +#define ALIGNED __attribute__((aligned(0x4))) +#elif __IAR_SYSTEMS_ICC__ + +#define PACKSTRUCT(decl) __packed decl + +#define ALIGNED +#elif _MSC_VER /*msvc*/ + +#define PACKSTRUCT(decl) __pragma(pack(push, 1) ) decl __pragma(pack(pop) ) +#define ALIGNED +#else +#define PACKSTRUCT(a) a PACKED +#endif +#endif + +/** + * The maximum BGAPI command payload size. + */ +#ifndef SL_BGAPI_MAX_PAYLOAD_SIZE +#define SL_BGAPI_MAX_PAYLOAD_SIZE 256 +#endif + +/***************************************************************************//** + * @addtogroup sl_bgapi_types BGAPI Types + * @brief Common types in BGAPI protocol + * @{ + */ + +#ifndef SL_BT_TYPE_UINT8ARRARY +#define SL_BT_TYPE_UINT8ARRARY +/** @brief Variable-length uint8_t array. Maximum length: 255 */ +typedef struct { + uint8_t len; /**< Number of bytes stored in @p data */ + uint8_t data[]; /**< Data bytes*/ +} uint8array; +#endif + +#ifndef SL_BT_TYPE_BYTE_ARRARY +#define SL_BT_TYPE_BYTE_ARRARY +/** @brief Variable-length int8_t array. Maximum length: 65535 */ +typedef struct { + uint16_t len; /**< Number of bytes stored in @p data */ + int8_t data[]; /**< Data bytes*/ +} byte_array; +#endif + +#ifndef SL_BT_TYPE_BDADDR +#define SL_BT_TYPE_BDADDR +/** @brief Bluetooth address */ +typedef struct { + uint8_t addr[6]; /**< @brief Bluetooth address in reverse byte order */ +} bd_addr; +#endif + +#ifndef SL_BT_TYPE_UUID128 +#define SL_BT_TYPE_UUID128 +/** @brief 128-bit UUID */ +typedef struct { + uint8_t data[16]; /**< 128-bit UUID */ +} uuid_128; +#endif + +#ifndef SL_BT_TYPE_AES_KEY128 +#define SL_BT_TYPE_AES_KEY128 +/** @brief 128-bit AES key */ +typedef struct { + uint8_t data[16]; /**< 128-bit AES key */ +} aes_key_128; +#endif + +#ifndef SL_BT_TYPE_UUID16 +#define SL_BT_TYPE_UUID16 +/** @brief 16-bit UUID */ +typedef struct { + uint8_t data[2]; /**< 16-bit UUID */ +} sl_bt_uuid_16_t; +#endif + +#ifndef SL_BT_TYPE_UUID64 +#define SL_BT_TYPE_UUID64 +/** @brief 64-bit UUID */ +typedef struct { + uint8_t data[8]; /**< 64-bit UUID */ +} sl_bt_uuid_64_t; +#endif + +/** @} */ // end addtogroup sl_bgapi_types +/******************************************************************************/ + +/** @brief Internal function prototype for BGAPI command handlers */ +typedef void (*sl_bgapi_handler)(const void*); + +typedef enum sl_bgapi_msg_types { + sl_bgapi_msg_type_cmd = 0x00, + sl_bgapi_msg_type_rsp = 0x00, + sl_bgapi_msg_type_evt = 0x80 +} sl_bgapi_msg_types_t; + +enum sl_bgapi_dev_types { + sl_bgapi_dev_type_app = 0x00, + sl_bgapi_dev_type_bt = 0x20, + sl_bgapi_dev_type_btmesh = 0x28, + sl_bgapi_dev_type_bgapi_debug = 0x30, +}; + +/***************************************************************************//** + * @addtogroup sl_bgapi_types BGAPI Types + * @brief Common types in BGAPI protocol + * @{ + */ + +/** + * @brief The length of a BGAPI message header which is 4 bytes + */ +#define SL_BGAPI_MSG_HEADER_LEN (4) + +/** + * @brief Get the device type of a BGAPI message + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_DEVICE_TYPE(HDR) ((HDR) & 0x38) + +/** + * @brief Get the identifier of a BGAPI message including device type, class ID, + * message type and message ID. + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_ID(HDR) ((HDR) & 0xffff00f8) + +/** + * @brief Get the data payload length in a BGAPI message. + * + * @param HDR The header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_LEN(HDR) ((((HDR) & 0x7) << 8) | (((HDR) & 0xff00) >> 8)) + +/** + * @brief The bit indicating whether data of a BGAPI message is encrypted + */ +#define SL_BGAPI_BIT_ENCRYPTED (1 << 6) // Bit + +/** + * @brief Check whether data of a BGAPI message is encrypted. + * + * @param HDR The BGAPI header of the message as a uint32_t integer + */ +#define SL_BGAPI_MSG_ENCRYPTED(HDR) ((HDR)&SL_BGAPI_BIT_ENCRYPTED) + +/** @} */ // end addtogroup sl_bgapi_types +/******************************************************************************/ + +/** + * Internal function for setting the command handler function. Used by API library. + * + * @param cmd_handler_delegate Pointer to command handler delegate function + */ +void sli_bgapi_set_cmd_handler_delegate(void (*cmd_handler_delegate)(uint32_t, + sl_bgapi_handler, + const void*)); + +/** + * @addtogroup sl_bgapi_functions BGAPI Functions + * @{ + * + * @brief Functions provided by the BGAPI protocol + */ + +/** + * @brief Lock the BGAPI for exclusive access. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format in an application that + * uses an RTOS. Normal application code that issues BGAPI commands by calling + * API functions defined by protocol stacks must never call this function + * directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + * + * @return SL_STATUS_OK if the lock has been obtained, otherwise an error code + */ +sl_status_t sl_bgapi_lock(void); + +/** + * @brief Release the lock obtained by @ref sl_bgapi_lock + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format in an application that + * uses an RTOS. Normal application code that issues BGAPI commands by calling + * API functions defined by protocol stacks must never call this function + * directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + */ +void sl_bgapi_unlock(void); + +/** + * @brief Handle a BGAPI command in binary format. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format. Normal application code + * that issues BGAPI commands by calling API functions defined by protocol + * stacks must never call this function directly. + * + * If the application uses an RTOS, the caller must protect the BGAPI handling + * by obtaining the BGAPI lock with @ref sl_bgapi_lock, handle the command with + * @ref sl_bgapi_handle_command, read the response from the buffer returned by + * @ref sl_bgapi_get_command_response, and then release the lock with @ref + * sl_bgapi_unlock. Here's an example of the full sequence that's required: + * + * @code + * // Lock BGAPI for exclusive access + * sl_status_t status = sl_bgapi_lock(); + * if (status != SL_STATUS_OK) { + * // Locking will only fail if there are fatal unrecoverable errors with the + * // RTOS primitives, so caller may choose to just assert in case of errors. + * } + * + * // Process the command + * sl_bgapi_handle_command(hdr, data); + * + * // Read the response + * void *rsp = sl_bgapi_get_command_response(); + * uint32_t rsp_header = *((uint32_t *)rsp); + * size_t rsp_len = SL_BGAPI_MSG_LEN(rsp_header) + SL_BGAPI_MSG_HEADER_LEN; + * // Send the `rsp_len` bytes of response starting from `rsp` + * + * // Finally unlock the BGAPI to allow other commands to proceed + * sl_bgapi_unlock(); + * @endcode + * + * Empty stub implementations are provided for @ref sl_bgapi_lock and @ref + * sl_bgapi_unlock, so the same sequence can be used for all NCP/CPC + * implementations even if an RTOS is not present. + * + * @param[in] hdr The BGAPI command header + * @param[in] data The payload data associated with the command + */ +void sl_bgapi_handle_command(uint32_t hdr, const void* data); + +/** + * @brief Get the response of a handled BGAPI command. + * + * NOTE: This function is provided for NCP/CPC components that need to handle + * BGAPI commands and responses in their binary format. Normal application code + * that issues BGAPI commands by calling API functions defined by protocol + * stacks must never call this function directly. + * + * See the documentation of @ref sl_bgapi_handle_command for the full sequence + * that must be followed when processing commands in their binary format. + * + * @return Pointer to the BGAPI response structure that was filled when the + * command was executed in @ref sl_bgapi_handle_command. + */ +void* sl_bgapi_get_command_response(void); + +/** @} */ // end addtogroup sl_bgapi_functions + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h index 793d765..f970827 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api.h @@ -1,15633 +1,15633 @@ -/***************************************************************************//** - * @brief SL_BT_API command declarations - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - - -#ifndef SL_BT_API_H -#define SL_BT_API_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include "sl_status.h" -#include "sl_bgapi.h" -#include "sl_bt_api_compatibility.h" - - -/* SL_BT_ synonyms for BGAPI header macros */ -#define SL_BT_MSG_ID(HDR) SL_BGAPI_MSG_ID(HDR) -#define SL_BT_MSG_HEADER_LEN SL_BGAPI_MSG_HEADER_LEN -#define SL_BT_MSG_LEN(HDR) SL_BGAPI_MSG_LEN(HDR) -#define SL_BT_BIT_ENCRYPTED SL_BGAPI_BIT_ENCRYPTED -#define SL_BT_MSG_ENCRYPTED(HDR) SL_BGAPI_MSG_ENCRYPTED(HDR) - -/** - * @addtogroup sl_bt_common_types BT Common Types - * @{ - * - * @brief BT common types - */ - -/** - * @brief Value used to indicate an invalid connection handle - */ -#define SL_BT_INVALID_CONNECTION_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid bonding handle - */ -#define SL_BT_INVALID_BONDING_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid advertising set handle - */ -#define SL_BT_INVALID_ADVERTISING_SET_HANDLE ((uint8_t) 0xFF) - -/** - * @brief Value used to indicate an invalid sync handle - */ -#define SL_BT_INVALID_SYNC_HANDLE ((uint16_t) 0xFFFF) - -/** - * @brief Value used to indicate an invalid connection analyzer handle - */ -#define SL_BT_INVALID_CONNECTION_ANALYZER_HANDLE ((uint8_t) 0xFF) - -/** @} */ // end addtogroup sl_bt_common_types - - -/** - * @brief ABR subevent length - */ -typedef struct { - uint8_t data[3]; /**< ABR subevent length */ -} sl_bt_cs_subevent_length_t; - -/** - * @brief DRBG key - */ -typedef struct { - uint8_t data[16]; /**< DRBG key */ -} sl_bt_drbg_key_t; - -/** - * @brief 79 1-bit fields containing the values of the ABR channel index - */ -typedef struct { - uint8_t data[10]; /**< 79 1-bit fields containing the values of the ABR channel index */ -} sl_bt_cs_channel_map_t; - -/** - * @brief 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection - */ -typedef struct { - uint8_t data[5]; /**< 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection */ -} sl_bt_connection_channel_map_t; - - - -/** - * @addtogroup sl_bt_dfu Device Firmware Update - * @{ - * - * @brief Device Firmware Update - * - * These commands and events are related to controlling firmware updates over - * the configured host interface and are available only when the device is - * booted in DFU mode. DFU process: - * 1. Boot device to DFU mode with the Bootloader interface - * 2. Wait for @ref sl_bt_evt_dfu_boot event - * 3. Send command @ref sl_bt_dfu_flash_set_address command to start the - * firmware update - * 4. Upload the firmware with @ref sl_bt_dfu_flash_upload commands until all - * data is uploaded - * 5. Send @ref sl_bt_dfu_flash_upload_finish command when all data is - * uploaded - * 6. Finalize DFU firmware update with @ref sl_bt_system_reset command - * - * DFU mode is using the UART baudrate set in bootloader. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_dfu_flash_set_address_id 0x01000020 -#define sl_bt_cmd_dfu_flash_upload_id 0x02000020 -#define sl_bt_cmd_dfu_flash_upload_finish_id 0x03000020 -#define sl_bt_rsp_dfu_flash_set_address_id 0x01000020 -#define sl_bt_rsp_dfu_flash_upload_id 0x02000020 -#define sl_bt_rsp_dfu_flash_upload_finish_id 0x03000020 - -/** - * @addtogroup sl_bt_evt_dfu_boot sl_bt_evt_dfu_boot - * @{ - * @brief This event indicates that the device booted in DFU mode and is now - * ready to receive commands related to device firmware upgrade (DFU). - */ - -/** @brief Identifier of the boot event */ -#define sl_bt_evt_dfu_boot_id 0x000000a0 - -/***************************************************************************//** - * @brief Data structure of the boot event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_dfu_boot_s -{ - uint32_t version; /**< The version of the bootloader */ -}); - -typedef struct sl_bt_evt_dfu_boot_s sl_bt_evt_dfu_boot_t; - -/** @} */ // end addtogroup sl_bt_evt_dfu_boot - -/** - * @addtogroup sl_bt_evt_dfu_boot_failure sl_bt_evt_dfu_boot_failure - * @{ - * @brief This event indicates that an error, which prevents the device from - * booting, has occurred in bootloader. - */ - -/** @brief Identifier of the boot_failure event */ -#define sl_bt_evt_dfu_boot_failure_id 0x010000a0 - -/***************************************************************************//** - * @brief Data structure of the boot_failure event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_dfu_boot_failure_s -{ - uint16_t reason; /**< The reason for boot failure. */ -}); - -typedef struct sl_bt_evt_dfu_boot_failure_s sl_bt_evt_dfu_boot_failure_t; - -/** @} */ // end addtogroup sl_bt_evt_dfu_boot_failure - -/***************************************************************************//** - * - * After re-booting the local device in DFU mode, this command defines the - * starting address on the flash where the new firmware will be written. - * - * @param[in] address The offset in the flash where the new firmware is uploaded - * to. Always use the value 0x00000000. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_set_address(uint32_t address); - -/***************************************************************************//** - * - * Upload the whole firmware image file into the Bluetooth device. The passed - * data length must be a multiple of 4 bytes. Because the BGAPI command payload - * size is limited, multiple commands need to be issued one after the other - * until the whole firmware image file is uploaded to the device. After each - * command, the next address of the flash sector in memory to write to is - * automatically updated by the bootloader. - * - * @param[in] data_len Length of data in @p data - * @param[in] data An array of data which will be written onto the flash. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data); - -/***************************************************************************//** - * - * Inform the device that the DFU file is fully uploaded. To return the device - * back to normal mode, issue the command @ref sl_bt_system_reset. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_dfu_flash_upload_finish(); - -/** @} */ // end addtogroup sl_bt_dfu - -/** - * @addtogroup sl_bt_system System - * @{ - * - * @brief System - * - * Commands and events in this class can be used to access and query the local - * device. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_system_hello_id 0x00010020 -#define sl_bt_cmd_system_start_bluetooth_id 0x1c010020 -#define sl_bt_cmd_system_stop_bluetooth_id 0x1d010020 -#define sl_bt_cmd_system_forcefully_stop_bluetooth_id 0x1e010020 -#define sl_bt_cmd_system_get_version_id 0x1b010020 -#define sl_bt_cmd_system_reset_id 0x01010020 -#define sl_bt_cmd_system_halt_id 0x0c010020 -#define sl_bt_cmd_system_linklayer_configure_id 0x0e010020 -#define sl_bt_cmd_system_set_tx_power_id 0x17010020 -#define sl_bt_cmd_system_get_tx_power_setting_id 0x18010020 -#define sl_bt_cmd_system_set_identity_address_id 0x13010020 -#define sl_bt_cmd_system_get_identity_address_id 0x15010020 -#define sl_bt_cmd_system_get_random_data_id 0x0b010020 -#define sl_bt_cmd_system_data_buffer_write_id 0x12010020 -#define sl_bt_cmd_system_data_buffer_clear_id 0x14010020 -#define sl_bt_cmd_system_get_counters_id 0x0f010020 -#define sl_bt_cmd_system_set_lazy_soft_timer_id 0x1a010020 -#define sl_bt_rsp_system_hello_id 0x00010020 -#define sl_bt_rsp_system_start_bluetooth_id 0x1c010020 -#define sl_bt_rsp_system_stop_bluetooth_id 0x1d010020 -#define sl_bt_rsp_system_forcefully_stop_bluetooth_id 0x1e010020 -#define sl_bt_rsp_system_get_version_id 0x1b010020 -#define sl_bt_rsp_system_reset_id 0x01010020 -#define sl_bt_rsp_system_halt_id 0x0c010020 -#define sl_bt_rsp_system_linklayer_configure_id 0x0e010020 -#define sl_bt_rsp_system_set_tx_power_id 0x17010020 -#define sl_bt_rsp_system_get_tx_power_setting_id 0x18010020 -#define sl_bt_rsp_system_set_identity_address_id 0x13010020 -#define sl_bt_rsp_system_get_identity_address_id 0x15010020 -#define sl_bt_rsp_system_get_random_data_id 0x0b010020 -#define sl_bt_rsp_system_data_buffer_write_id 0x12010020 -#define sl_bt_rsp_system_data_buffer_clear_id 0x14010020 -#define sl_bt_rsp_system_get_counters_id 0x0f010020 -#define sl_bt_rsp_system_set_lazy_soft_timer_id 0x1a010020 - -/** - * @brief Specifies the mode that the system will boot into. - */ -typedef enum -{ - sl_bt_system_boot_mode_normal = 0x0, /**< (0x0) Boot to normal mode */ - sl_bt_system_boot_mode_uart_dfu = 0x1, /**< (0x1) Boot to UART DFU mode */ - sl_bt_system_boot_mode_ota_dfu = 0x2 /**< (0x2) Boot to OTA DFU mode */ -} sl_bt_system_boot_mode_t; - -/** - * @brief These Keys are used to configure Link Layer Operation - */ -typedef enum -{ - sl_bt_system_linklayer_config_key_halt = 0x1, /**< - (0x1) - Same - as - system_halt - command, - value-0 - Stop - Radio - 1- - Start - Radio */ - sl_bt_system_linklayer_config_key_priority_range = 0x2, /**< - (0x2) - Sets - the - RAIL - priority_mapping - offset - field - of - the - link - layer - priority - configuration - structure - to - the - first - byte - of - the - value - field. */ - sl_bt_system_linklayer_config_key_scan_channels = 0x3, /**< - (0x3) - Sets - channels - to - scan - on. - The - first - byte - of - the - value - is - the - channel - map. - 0x1 - = - Channel - 37, - 0x2 - = - Channel - 38, - 0x4 - = - Channel - 39 */ - sl_bt_system_linklayer_config_key_set_flags = 0x4, /**< - (0x4) - Sets - the - link - layer - configuration - flags. - The - value - is - a - little - endian - 32-bit - integer. - Flag - Values: - - 0x00000001 - \- - Disable - Feature - Exchange - in - peripheral - role - of - the - connection - - 0x00000002 - \- - Disable - Feature - Exchange - in - central - role - of - the - connection */ - sl_bt_system_linklayer_config_key_clr_flags = 0x5, /**< - (0x5) - The - value - is - flags - to - clear. - Flags - are - the - same - as - in - SET_FLAGS - command. */ - sl_bt_system_linklayer_config_key_set_afh_interval = 0x7, /**< - (0x7) - Set - the - afh_scan_interval. - Value - is - in - units - of - 10 - ms. - Setting - the - interval - to - 0 - will - result - in - using - the - default - value - of - 1 - second. */ - sl_bt_system_linklayer_config_key_set_priority_table = 0x9, /**< - (0x9) - The - value - contains - a - priority - table - to - be - copied - over - the - existing - table. - If - the - value - is - smaller - than - the - full - table, - only - those - values - are - updated. - See - sl_bt_bluetooth_ll_priorities - struct - for - the - definition - of - a - priority - table. */ - sl_bt_system_linklayer_config_key_set_rx_packet_filtering = 0xa, /**< - (0xa) - Configure - and - enable - or - disable - RX - packet - filtering - feature. - Value: - >= - 5 - bytes. - - Byte - 1 - \- - The - filter - count - - Byte - 2 - \- - The - filter - offset - - Byte - 3 - \- - The - length - of - the - filter - list - - Byte - 4 - \- - The - bitmask - flags - - Rest - of - the - data - \- - The - filter - list */ - sl_bt_system_linklayer_config_key_set_simultaneous_scanning = 0xb, /**< - (0xb) - Enable - or - disable - simultaneous - scanning - on - the - 1M - and - Coded - PHYs. - Value: - 1 - byte. - - 0 - \- - Disable - simultaneous - scanning. - - 1 - \- - Enable - simultaneous - scanning. */ - sl_bt_system_linklayer_config_key_set_channelmap_flags = 0xc, /**< - (0xc) - Configure - channelmap - adaptivity - flags. - Value: - 4 - bytes. */ - sl_bt_system_linklayer_config_key_power_control_golden_range = 0x10, /**< - (0x10) - Set - Power - Control - golden - range - parameters. - The - value - is - a - 8-bytes - long - array - that - consists - of - 4 - pairs - of - golden - range - configurations. - In - each - pair, - the - first - byte - is - the - lower - RSSI - boundary - and - the - second - byte - is - the - upper - RSSI - boundary. - RSSI - values - are - in - dBm. - This - configuration - is - not - allowed - if - there - are - active - Bluetooth - connections. - - Byte - 1 - \- - Minimal - RSSI - on - 1M - PHY - - Byte - 2 - \- - Maximal - RSSI - on - 1M - PHY - - Byte - 3 - \- - Minimal - RSSI - on - 2M - PHY - - Byte - 4 - \- - Maximal - RSSI - on - 2M - PHY - - Byte - 5 - \- - Minimal - RSSI - on - Coded - PHY - S=8 - - Byte - 6 - \- - Maximal - RSSI - on - Coded - PHY - S=8 - - Byte - 7 - \- - Minimal - RSSI - on - Coded - PHY - S=2 - - Byte - 8 - \- - Maximal - RSSI - on - Coded - PHY - S=2 */ - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit = 0x11, /**< - (0x11) - Value: - uint16_t - Adjust - upper - limit - for - backoff - counter. - If - 0 - restores - default - value - of - 256 - Value - must - be - between - 16 - \- - 256 */ - sl_bt_system_linklayer_config_key_afh_rssi_threshold = 0x12, /**< - (0x12) - Value: - int8_t - Configures - RSSI - limit - for - AFH - channel - blocking */ - sl_bt_system_linklayer_config_key_afh_channel_cooldown = 0x13, /**< - (0x13) - Value: - int16_t - Configures - how - long - channel - is - blocked - after - activity - is - detected - Default: - 8000 */ - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps = 0x14 /**< - (0x14) - Value: - uint8_t - 0 - \- - default, - only - reports - scan - responses - that - is - received - after - sending - scan_req - nonzero - \- - Will - report - all - scan - responses - that - are - received - on - primary - advertising - channels */ -} sl_bt_system_linklayer_config_key_t; - -/** - * @addtogroup sl_bt_evt_system_boot sl_bt_evt_system_boot - * @{ - * @brief Indicates that the device has started and the radio is ready - * - * This event carries the firmware build number and other software and hardware - * identification codes. - */ - -/** @brief Identifier of the boot event */ -#define sl_bt_evt_system_boot_id 0x000100a0 - -/***************************************************************************//** - * @brief Data structure of the boot event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_boot_s -{ - uint16_t major; /**< Major release version */ - uint16_t minor; /**< Minor release version */ - uint16_t patch; /**< Patch release number */ - uint16_t build; /**< Build number */ - uint32_t bootloader; /**< Unused. Ignore this field. */ - uint16_t hw; /**< Hardware type: the major chip revision number in the - most significant byte and the minor revision in the - least significant byte */ - uint32_t hash; /**< Version hash */ -}); - -typedef struct sl_bt_evt_system_boot_s sl_bt_evt_system_boot_t; - -/** @} */ // end addtogroup sl_bt_evt_system_boot - -/** - * @addtogroup sl_bt_evt_system_stopped sl_bt_evt_system_stopped - * @{ - * @brief When the Bluetooth on-demand start component is included in the - * application build, this event is triggered when stopping the Bluetooth stack - * using commands @ref sl_bt_system_stop_bluetooth or @ref - * sl_bt_system_forcefully_stop_bluetooth has completed. - */ - -/** @brief Identifier of the stopped event */ -#define sl_bt_evt_system_stopped_id 0x010100a0 - -/** @} */ // end addtogroup sl_bt_evt_system_stopped - -/** - * @addtogroup sl_bt_evt_system_error sl_bt_evt_system_error - * @{ - * @brief Indicates that an error has occurred - * - * See error codes table for more information. - */ - -/** @brief Identifier of the error event */ -#define sl_bt_evt_system_error_id 0x060100a0 - -/***************************************************************************//** - * @brief Data structure of the error event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_error_s -{ - uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ - uint8array data; /**< Data related to the error; this field can be empty. */ -}); - -typedef struct sl_bt_evt_system_error_s sl_bt_evt_system_error_t; - -/** @} */ // end addtogroup sl_bt_evt_system_error - -/** - * @addtogroup sl_bt_evt_system_hardware_error sl_bt_evt_system_hardware_error - * @{ - * @brief Indicates that a hardware-related error has occurred. - */ - -/** @brief Identifier of the hardware_error event */ -#define sl_bt_evt_system_hardware_error_id 0x050100a0 - -/***************************************************************************//** - * @brief Data structure of the hardware_error event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_hardware_error_s -{ - uint16_t status; /**< SL_STATUS_OK if successful. Error code otherwise. */ -}); - -typedef struct sl_bt_evt_system_hardware_error_s sl_bt_evt_system_hardware_error_t; - -/** @} */ // end addtogroup sl_bt_evt_system_hardware_error - -/** - * @addtogroup sl_bt_evt_system_resource_exhausted sl_bt_evt_system_resource_exhausted - * @{ - * @brief Indicates that a system resource has been exhausted during the - * operation of the Bluetooth stack - * - * If resource errors occur already when the Bluetooth stack is starting, the - * error is reported directly as a return value from sl_bt_stack_init (when the - * Bluetooth on-demand start component is not included in the application - * build), or from @ref sl_bt_system_start_bluetooth (when the on-demand start - * component is included). The fields of this event indicate how many failures - * have occurred for a specific resource. If further resource failures occur - * while this event is already queued in the BGAPI event queue but not yet - * delivered to the application, the new failures are included in the already - * queued event. When the application receives this event, the fields represent - * the number of failures that have occurred since the previous @ref - * sl_bt_evt_system_resource_exhausted event. - */ - -/** @brief Identifier of the resource_exhausted event */ -#define sl_bt_evt_system_resource_exhausted_id 0x080100a0 - -/***************************************************************************//** - * @brief Data structure of the resource_exhausted event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_resource_exhausted_s -{ - uint8_t num_buffers_discarded; /**< The system has temporarily run - out of the pre-allocated data - buffers that are allocated based - on SL_BT_CONFIG_BUFFER_SIZE - configuration and some expendable - data or event had to be discarded - to satisfy a non-expendble buffer - allocation. A typical case is - discarding scan reports when a - large inflow of scan reports - exceeds the speed at which the - application drains the BGAPI - event queue. */ - uint8_t num_buffer_allocation_failures; /**< The system has run out of the - pre-allocated data buffers that - are allocated based on - SL_BT_CONFIG_BUFFER_SIZE - configuration and a buffer - allocation has failed. */ - uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed to - make an allocation from the heap. - Note that only allocations made - by the Bluetooth stack are - detected and reported by this - field. Allocation failures in - other components that use - sl_malloc() or malloc() are not - included in this count. */ -}); - -typedef struct sl_bt_evt_system_resource_exhausted_s sl_bt_evt_system_resource_exhausted_t; - -/** @} */ // end addtogroup sl_bt_evt_system_resource_exhausted - -/** - * @addtogroup sl_bt_evt_system_external_signal sl_bt_evt_system_external_signal - * @{ - * @brief Indicates that the external signals have been received - * - * External signals are generated from the native application. - */ - -/** @brief Identifier of the external_signal event */ -#define sl_bt_evt_system_external_signal_id 0x030100a0 - -/***************************************************************************//** - * @brief Data structure of the external_signal event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_external_signal_s -{ - uint32_t extsignals; /**< Bitmask of external signals received since last - event. */ -}); - -typedef struct sl_bt_evt_system_external_signal_s sl_bt_evt_system_external_signal_t; - -/** @} */ // end addtogroup sl_bt_evt_system_external_signal - -/** - * @addtogroup sl_bt_evt_system_awake sl_bt_evt_system_awake - * @{ - * @brief Indicates that the device is awake and no longer in sleep mode - * - * NOTE: Stack does not generate this event by itself because sleep and - * wakeup are managed by applications. If this event is needed, call function - * @ref sl_bt_send_system_awake, which signals the stack to send the event. - */ - -/** @brief Identifier of the awake event */ -#define sl_bt_evt_system_awake_id 0x040100a0 - -/** @} */ // end addtogroup sl_bt_evt_system_awake - -/** - * @addtogroup sl_bt_evt_system_soft_timer sl_bt_evt_system_soft_timer - * @{ - * @brief Indicates that a soft timer has lapsed. - */ - -/** @brief Identifier of the soft_timer event */ -#define sl_bt_evt_system_soft_timer_id 0x070100a0 - -/***************************************************************************//** - * @brief Data structure of the soft_timer event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_system_soft_timer_s -{ - uint8_t handle; /**< Timer Handle */ -}); - -typedef struct sl_bt_evt_system_soft_timer_s sl_bt_evt_system_soft_timer_t; - -/** @} */ // end addtogroup sl_bt_evt_system_soft_timer - -/***************************************************************************//** - * - * Verify whether the communication between the host and the device is - * functional. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_hello(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the on-demand start command is not available and the - * command returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to request starting the - * Bluetooth stack when the application needs it. If the command returns a - * success result, the stack starts to asynchronously allocate the resources and - * configure the Bluetooth stack based on the configuration passed at - * initialization time. - * - * The Bluetooth stack cannot be restarted while it's still stopping after - * issuing the command @ref sl_bt_system_stop_bluetooth. If @ref - * sl_bt_system_start_bluetooth is called when stopping is still on-going the - * command returns the error SL_STATUS_INVALID_STATE. The application must wait - * for the @ref sl_bt_evt_system_stopped event before attempting to restart the - * stack. - * - * Successful start of the stack is indicated by the @ref sl_bt_evt_system_boot - * event. The configured classes and Bluetooth stack features are available - * after the application has received the @ref sl_bt_evt_system_boot event. If - * starting the Bluetooth stack fails, the error is indicated to the application - * with the @ref sl_bt_evt_system_error event. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_boot - Triggered when the Bluetooth stack has - * succesfully started and is ready to accept commands from the application - * - @ref sl_bt_evt_system_error - Triggered if the command to start the - * Bluetooth stack was accepted but the asynchronous starting of the stack - * has failed - * - ******************************************************************************/ -sl_status_t sl_bt_system_start_bluetooth(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the stop command is not available and the command - * returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to stop the Bluetooth stack - * when the application no longer needs it. This command gracefully restores - * Bluetooth to an idle state by disconnecting any active connections and - * stopping any on-going advertising and scanning. Any resources that were - * allocated when the stack was started are freed when the stack has finished - * stopping. After this command, the BGAPI classes other than @ref sl_bt_system - * become unavailable. - * - * Stopping the Bluetooth stack with this command is asynchronous and the - * completion is indicated by the @ref sl_bt_evt_system_stopped event. The - * application can use the command @ref sl_bt_system_start_bluetooth to restart - * the stack any time after it has received the @ref sl_bt_evt_system_stopped - * event. If the application needs to stop the Bluetooth stack immediately, use - * the command @ref sl_bt_system_forcefully_stop_bluetooth. That command can - * also be used to immediately complete the asynchronous stopping if the command - * @ref sl_bt_system_stop_bluetooth has not completed in expected time period. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_stopped - Triggered when stopping the Bluetooth - * stack has completed - * - ******************************************************************************/ -sl_status_t sl_bt_system_stop_bluetooth(); - -/***************************************************************************//** - * - * If the Bluetooth on-demand start component is not included in the application - * build, the Bluetooth stack is automatically started when the device boots up. - * In this configuration, the stop command is not available and the command - * returns the error SL_STATUS_NOT_AVAILABLE. - * - * When the Bluetooth on-demand start component is included in the application - * build, this command is used by the application to forcefully stop the - * Bluetooth stack when the application no longer needs it. This command - * immediately stops all active Bluetooth operations such as advertising, - * scanning, and connections. Active connections are forcefully closed without - * performing the ACL Termination procedure. This can result in the observation - * of connection loss or supervision timeout on the remote device. Only use this - * command for special cases, for example, when stopping Bluetooth with @ref - * sl_bt_system_stop_bluetooth did not complete in expected time period. - * - * Stopping the Bluetooth stack with this command is immediate and it directly - * triggers the @ref sl_bt_evt_system_stopped event. Any resources that were - * allocated when the stack was started are freed. After this command, the BGAPI - * classes other than @ref sl_bt_system become unavailable. The application can - * use the command @ref sl_bt_system_start_bluetooth to continue using Bluetooth - * later. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_stopped - Triggered immediately to indicate the - * Bluetooth stack has stopped - * - ******************************************************************************/ -sl_status_t sl_bt_system_forcefully_stop_bluetooth(); - -/***************************************************************************//** - * - * Get the firmware version information. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * @param[out] major Major release version - * @param[out] minor Minor release version - * @param[out] patch Patch release number - * @param[out] build Build number - * @param[out] bootloader Unused. Ignore this field. - * @param[out] hash Version hash - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_version(uint16_t *major, - uint16_t *minor, - uint16_t *patch, - uint16_t *build, - uint32_t *bootloader, - uint32_t *hash); - -/***************************************************************************//** - * - * Reset the system. This command does not have a response. - * - * On EFR series 1 devices, this command boots into the given mode and triggers - * one of the boot events (normal reset or boot to DFU mode) depending on the - * given boot mode. - * - * On EFR series 2 devices, the @p dfu parameter is ignored and this command - * always boots the user application. To boot into a DFU mode on series 2, use - * the Bootloader API @c bootloader_rebootAndInstall. - * - * NOTE: This command is available even if the Bluetooth stack has not - * been started. See @ref sl_bt_system_start_bluetooth for description of how - * the Bluetooth stack is started. - * - * @param[in] dfu @parblock - * Enum @ref sl_bt_system_boot_mode_t. Boot mode. Values: - * - sl_bt_system_boot_mode_normal (0x0): Boot to normal mode - * - sl_bt_system_boot_mode_uart_dfu (0x1): Boot to UART DFU mode - * - sl_bt_system_boot_mode_ota_dfu (0x2): Boot to OTA DFU mode - * - * This parameter is ignored on EFR series 2 devices. - * @endparblock - * - * @b Events - * - @ref sl_bt_evt_system_boot - Sent after the device has booted in normal - * mode. - * - @ref sl_bt_evt_dfu_boot - Sent after the device has booted in UART DFU - * mode. - * - ******************************************************************************/ -void sl_bt_system_reset(uint8_t dfu); - -/***************************************************************************//** - * - * Force radio to idle state and allow device to sleep. Advertising, scanning, - * connections, and software timers are halted by this command. Halted - * operations resume after calling this command with parameter 0. Connections - * stay alive if the system is resumed before connection supervision timeout. - * - * Use this command only for a short time period (maximum few seconds). Although - * it halts Bluetooth activity, all tasks and operations still exist inside the - * stack with their own concepts of time. Halting the system for a long time - * period may have negative consequences on stack's internal states. - * - * NOTE: The software timer is also halted. Hardware interrupts are the - * only way to wake up from energy mode 2 when the system is halted. - * - * @param[in] halt Values: - * - 1: halt - * - 0: resume - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_halt(uint8_t halt); - -/***************************************************************************//** - * - * Send configuration data to the link layer. This command fine tunes low-level - * Bluetooth operations. - * - * @param[in] key @parblock - * Enum @ref sl_bt_system_linklayer_config_key_t. Key to configure. Values: - * - sl_bt_system_linklayer_config_key_halt (0x1): Same as - * system_halt command, value-0 Stop Radio 1- Start Radio - * - sl_bt_system_linklayer_config_key_priority_range (0x2): Sets the - * RAIL priority_mapping offset field of the link layer priority - * configuration structure to the first byte of the value field. - * - sl_bt_system_linklayer_config_key_scan_channels (0x3): Sets - * channels to scan on. The first byte of the value is the channel map. - * 0x1 = Channel 37, 0x2 = Channel 38, 0x4 = Channel 39 - * - sl_bt_system_linklayer_config_key_set_flags (0x4): Sets the link - * layer configuration flags. The value is a little endian 32-bit integer. - * Flag Values: - * - 0x00000001 - Disable Feature Exchange in peripheral role of the - * connection - * - 0x00000002 - Disable Feature Exchange in central role of the - * connection - * - * - sl_bt_system_linklayer_config_key_clr_flags (0x5): The value is - * flags to clear. Flags are the same as in SET_FLAGS command. - * - sl_bt_system_linklayer_config_key_set_afh_interval (0x7): Set - * the afh_scan_interval. Value is in units of 10 ms. Setting the interval - * to 0 will result in using the default value of 1 second. - * - sl_bt_system_linklayer_config_key_set_priority_table (0x9): The - * value contains a priority table to be copied over the existing table. - * If the value is smaller than the full table, only those values are - * updated. See sl_bt_bluetooth_ll_priorities struct for the definition of - * a priority table. - * - sl_bt_system_linklayer_config_key_set_rx_packet_filtering (0xa): - * Configure and enable or disable RX packet filtering feature. Value: >= - * 5 bytes. - * - Byte 1 - The filter count - * - Byte 2 - The filter offset - * - Byte 3 - The length of the filter list - * - Byte 4 - The bitmask flags - * - Rest of the data - The filter list - * - * - sl_bt_system_linklayer_config_key_set_simultaneous_scanning - * (0xb): Enable or disable simultaneous scanning on the 1M and Coded - * PHYs. Value: 1 byte. - * - 0 - Disable simultaneous scanning. - * - 1 - Enable simultaneous scanning. - * - * - sl_bt_system_linklayer_config_key_set_channelmap_flags (0xc): - * Configure channelmap adaptivity flags. Value: 4 bytes. - * - sl_bt_system_linklayer_config_key_power_control_golden_range - * (0x10): Set Power Control golden range parameters. The value is a - * 8-bytes long array that consists of 4 pairs of golden range - * configurations. In each pair, the first byte is the lower RSSI boundary - * and the second byte is the upper RSSI boundary. RSSI values are in dBm. - * This configuration is not allowed if there are active Bluetooth - * connections. - * - Byte 1 - Minimal RSSI on 1M PHY - * - Byte 2 - Maximal RSSI on 1M PHY - * - Byte 3 - Minimal RSSI on 2M PHY - * - Byte 4 - Maximal RSSI on 2M PHY - * - Byte 5 - Minimal RSSI on Coded PHY S=8 - * - Byte 6 - Maximal RSSI on Coded PHY S=8 - * - Byte 7 - Minimal RSSI on Coded PHY S=2 - * - Byte 8 - Maximal RSSI on Coded PHY S=2 - * - * - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit - * (0x11): Value: uint16_t Adjust upper limit for backoff counter. If - * 0 restores default value of 256 Value must be between 16 - 256 - * - sl_bt_system_linklayer_config_key_afh_rssi_threshold (0x12): - * Value: int8_t Configures RSSI limit for AFH channel blocking - * - sl_bt_system_linklayer_config_key_afh_channel_cooldown (0x13): - * Value: int16_t Configures how long channel is blocked after activity is - * detected Default: 8000 - * - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps - * (0x14): Value: uint8_t 0 - default, only reports scan responses - * that is received after sending scan_req nonzero - Will report all scan - * responses that are received on primary advertising channels - * @endparblock - * @param[in] data_len Length of data in @p data - * @param[in] data Configuration data. Length and contents of the data field - * depend on the key value used. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_linklayer_configure(uint8_t key, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set the global minimum and maximum radiated TX power levels for Bluetooth. - * This returns selected power levels that are radiated from the antenna at TX. - * The transmitter power at antenna pin will apply the RF TX path gain to match - * this setting. RF TX path gain can be set in the Bluetooth configuration. If - * the GATT server contains a TX power service, the TX Power Level attribute - * will be updated with the selected maximum power level. - * - * A selected power level may be different than the requested value because of - * Bluetooth feature restrictions or the device's radio characteristics. For - * Bluetooth connections, the maximum radiated TX power is limited to 10 dBm if - * Adaptive Frequency Hopping (AFH) is not enabled. - * - * The minimum TX power setting is used by LE power control. It has no effect in - * Bluetooth stack if the LE power control feature is not enabled. However, the - * application may still use this setting for other purposes, e.g., setting the - * minimum TX power for DTM transmitter test. - * - * The minimum and maximum radiated TX power levels can also be configured in - * the Bluetooth configuration and passed into the Bluetooth stack - * initialization. By default, the minimum radiated TX power level is configured - * to -3 dBm and the maximum radiated TX power level to 8 dBm. - * - * NOTE: Do not use this command while advertising or scanning. - * Furthermore, the stack does not allow setting TX powers during connections. - * - * @param[in] min_power Minimum radiated TX power. Unit: 0.1 dBm. For example, - * the value 10 means 1 dBm. - * @param[in] max_power Maximum radiated TX power. Unit: 0.1 dBm. For example, - * the value 10 means 1 dBm. - * @param[out] set_min The selected minimum radiated TX power. Unit: 0.1 dBm - * @param[out] set_max The selected maximum radiated TX power. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_tx_power(int16_t min_power, - int16_t max_power, - int16_t *set_min, - int16_t *set_max); - -/***************************************************************************//** - * - * Get TX power settings including the minimum and maximum radiated TX power - * levels the device supports, the minimum and maximum radiated TX power levels - * currently set in the stack, and the TX RF path gain configuration. - * - * @param[out] support_min The minimum radiated TX power the device supports. - * Unit: 0.1 dBm - * @param[out] support_max The maximum radiated TX power the device supports. - * Unit: 0.1 dBm - * @param[out] set_min The minimum radiated TX power currently set in stack. - * Unit: 0.1 dBm - * @param[out] set_max The maximum radiated TX power currently set in stack. - * Unit: 0.1 dBm - * @param[out] rf_path_gain TX RF path gain. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, - int16_t *support_max, - int16_t *set_min, - int16_t *set_max, - int16_t *rf_path_gain); - -/***************************************************************************//** - * - * Store the device's Bluetooth identity address in persistent storage using NVM - * keys. The address can be a public device address or a static device address. - * The stack returns an error if the static device address does not conform to - * the Bluetooth specification. - * - * The new address will be effective in the next system reboot. The stack will - * use the address in the NVM keys when present. Otherwise, it uses the default - * Bluetooth public device address which is programmed at production. - * - * The stack treats 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid - * addresses. Therefore, passing one of them into this command will cause the - * stack to delete the NVM keys and use the default address in the next system - * reboot. - * - * Note: Because the NVM keys are located in flash and flash wearing can - * occur, avoid calling this command regularly. - * - * @param[in] address Bluetooth identity address in little endian format - * @param[in] type Enum @ref sl_bt_gap_address_type_t. Identity address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type); - -/***************************************************************************//** - * - * Read the Bluetooth identity address used by the device, which can be a public - * or random static device address. - * - * @param[out] address Bluetooth identity address in little endian format - * @param[out] type Enum @ref sl_bt_gap_address_type_t. Identity address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type); - -/***************************************************************************//** - * - * Get random data. - * - * @param[in] length Length of random data. - * @param[in] max_data_size Size of output buffer passed in @p data - * @param[out] data_len On return, set to the length of output data written to - * @p data - * @param[out] data Random data - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_random_data(uint8_t length, - size_t max_data_size, - size_t *data_len, - uint8_t *data); - -/***************************************************************************//** - * - * Write data into the system data buffer. Data will be appended to the end of - * existing data. - * - * @param[in] data_len Length of data in @p data - * @param[in] data Data to write - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_data_buffer_write(size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Remove all data from the system data buffer. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_data_buffer_clear(); - -/***************************************************************************//** - * - * Get packet and error counters. Passing a non-zero value also resets counters. - * - * @param[in] reset Reset counters if the parameter value is not zero. - * @param[out] tx_packets The number of successfully transmitted packets - * @param[out] rx_packets The number of successfully received packets - * @param[out] crc_errors The number of received packets with CRC errors - * @param[out] failures The number of radio failures, such as aborted TX/RX - * packets, scheduling failures, and so on. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_system_get_counters(uint8_t reset, - uint16_t *tx_packets, - uint16_t *rx_packets, - uint16_t *crc_errors, - uint16_t *failures); - -/***************************************************************************//** - * - * Deprecated . Use the sleeptimer component (in platform services - * category) for timers. Because the sleeptimer does not support a timer with - * slack yet, the Bluetooth stack will continue to support this command until - * another component provides the functionality. - * - * Start a software timer with slack. The slack parameter allows the stack to - * optimize wakeups and save power. The timer event is triggered between time - * and time + @p slack. - * - * Multiple concurrent timers can be running simultaneously. 256 unique timer - * handles (IDs) are available. The maximum number of concurrent timers is - * configurable at device initialization. Up to 16 concurrent timers can be - * configured. The default configuration is 4. As the RAM for storing timer data - * is pre-allocated at initialization, an application should not configure the - * amount more than it needs for minimizing RAM usage. - * - * @param[in] time @parblock - * An interval between how often to send events in hardware clock ticks (1 - * second is equal to 32768 ticks). - * - * The smallest interval value supported is 328, which is around 10 - * milliseconds. Any parameters between 0 and 328 will be rounded up to 328. - * The maximum value is 2147483647, which corresponds to about 18.2 hours. - * - * If @p time is 0, removes the scheduled timer with the same handle. - * @endparblock - * @param[in] slack Slack time in hardware clock ticks - * @param[in] handle Timer handle to use, which is returned in timeout event - * @param[in] single_shot Timer mode. Values: - * - 0: false (timer is repeating) - * - 1: true (timer runs only once) - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_system_soft_timer - Sent after this timer has lapsed. - * - ******************************************************************************/ -sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, - uint32_t slack, - uint8_t handle, - uint8_t single_shot); - -/** @} */ // end addtogroup sl_bt_system - -/** - * @addtogroup sl_bt_resource Resource Report - * @{ - * - * @brief Resource Report - * - * Commands and events in this class can be used to query and receive the memory - * buffer usage status. The memory buffer is used by the Bluetooth stack for - * storing application data (e.g., API commands and events), user data over - * Bluetooth connections, advertising, scanning, etc. Total buffer size is - * defined by the application using the SL_BT_CONFIG_BUFFER_SIZE configuration. - * The Bluetooth stack does not partition the buffer, instead, the buffer is a - * shared resource for all features. Therefore, the available memory for one - * feature could be affected by another feature in simultaneous use cases. This - * API class provides a utility for application to get some insight of the - * buffer usage. As allocations in the memory buffer have overhead, the actual - * amount of memory that can be used for user data is less than a reported free - * memory amount. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_resource_get_status_id 0x005f0020 -#define sl_bt_cmd_resource_set_report_threshold_id 0x015f0020 -#define sl_bt_cmd_resource_enable_connection_tx_report_id 0x025f0020 -#define sl_bt_cmd_resource_get_connection_tx_status_id 0x035f0020 -#define sl_bt_cmd_resource_disable_connection_tx_report_id 0x045f0020 -#define sl_bt_rsp_resource_get_status_id 0x005f0020 -#define sl_bt_rsp_resource_set_report_threshold_id 0x015f0020 -#define sl_bt_rsp_resource_enable_connection_tx_report_id 0x025f0020 -#define sl_bt_rsp_resource_get_connection_tx_status_id 0x035f0020 -#define sl_bt_rsp_resource_disable_connection_tx_report_id 0x045f0020 - -/** - * @addtogroup sl_bt_resource_connection_tx_flags Connection TX status flags - * @{ - * - * Defines the connection TX status flags reported by @ref - * sl_bt_resource_get_connection_tx_status. - */ - -/** - * - * The number of TX packets queued on a connection has overflowed the @p - * packet_count that was effective at the time the connection opened. The packet - * count is configured with command @ref - * sl_bt_resource_enable_connection_tx_report and is valid for subsequent - * connections. - * - * When this bit is set, the @p packet_count returned by @ref - * sl_bt_resource_get_connection_tx_status is correct, but @p data_len excludes - * the data bytes in the packets that overflowed the configured packet count. - * - * */ -#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_PACKET_OVERFLOW 0x1 - -/** - * - * Internal inconsistency has been detected in the connection TX bookkeeping. - * When this bit is set, the application should consider both @p packet_count - * and @p data_len returned by @ref sl_bt_resource_get_connection_tx_status to - * be unreliable. - * - * */ -#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_CORRUPT 0x2 - -/** @} */ // end Connection TX status flags - -/** - * @addtogroup sl_bt_evt_resource_status sl_bt_evt_resource_status - * @{ - * @brief Indicates that the memory buffer usage has crossed a threshold - */ - -/** @brief Identifier of the status event */ -#define sl_bt_evt_resource_status_id 0x005f00a0 - -/***************************************************************************//** - * @brief Data structure of the status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_resource_status_s -{ - uint32_t free_bytes; /**< The number of free bytes in the memory buffer */ -}); - -typedef struct sl_bt_evt_resource_status_s sl_bt_evt_resource_status_t; - -/** @} */ // end addtogroup sl_bt_evt_resource_status - -/***************************************************************************//** - * - * Get the present memory buffer usage status. - * - * @param[out] total_bytes The number of total bytes in the memory buffer - * @param[out] free_bytes The number of free bytes in the memory buffer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, - uint32_t *free_bytes); - -/***************************************************************************//** - * - * Set low and high thresholds of memory buffer usage reports. Value 0 in - * parameter @p low for the low threshold disables the reporting, and a non-zero - * value in @p low enables the reporting. - * - * When the reporting is enabled, event @ref sl_bt_evt_resource_status will be - * generated to report the status when the free buffer amount decreases and - * crosses the low threshold, and later another event will be generated if the - * free buffer amount increases and crosses the high threshold. If only the high - * threshold is crossed but the low threshold isn't, no event will be generated. - * - * By default, low and high threshold values are 0, i.e., no report event is - * generated. - * - * @param[in] low The low threshold of free bytes in the memory buffer, or 0 to - * disable the reporting - * @param[in] high A non-zero value as the high threshold that must be greater - * than parameter @p low, or 0 for not reporting the status for high threshold - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high); - -/***************************************************************************//** - * - * Enable tracking and reporting data packet TX status of future new - * connections. Existing connections are not affected by this command. - * - * @param[in] packet_count The maximum number of data packets to track on a - * connection - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_server_notification_tx_completed - Sent when GATT - * notifications from the GATT server were transmitted. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count); - -/***************************************************************************//** - * - * Get the data packet TX status of a connection. - * - * @param[in] connection Connection handle - * @param[out] flags Flags that indicate the status of connection TX packet - * reporting. This value is a bitmask of @ref - * sl_bt_resource_connection_tx_flags. - * @param[out] packet_count Number of data packets in the TX queue waiting to be - * transmitted - * @param[out] data_len Total number of bytes of data packets in the TX queue - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, - uint16_t *flags, - uint16_t *packet_count, - uint32_t *data_len); - -/***************************************************************************//** - * - * Disable tracking and reporting data packet TX status of future new - * connections. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resource_disable_connection_tx_report(); - -/** @} */ // end addtogroup sl_bt_resource - -/** - * @addtogroup sl_bt_gap GAP - * @{ - * - * @brief GAP - * - * The commands and events in this class are related to the Generic Access - * Profile (GAP) in Bluetooth. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gap_set_privacy_mode_id 0x01020020 -#define sl_bt_cmd_gap_set_data_channel_classification_id 0x02020020 -#define sl_bt_cmd_gap_enable_whitelisting_id 0x03020020 -#define sl_bt_cmd_gap_set_identity_address_id 0x04020020 -#define sl_bt_rsp_gap_set_privacy_mode_id 0x01020020 -#define sl_bt_rsp_gap_set_data_channel_classification_id 0x02020020 -#define sl_bt_rsp_gap_enable_whitelisting_id 0x03020020 -#define sl_bt_rsp_gap_set_identity_address_id 0x04020020 - -/** - * @brief These values define Bluetooth device address types. Commands and - * events that have Bluetooth device address parameters will specify which - * values are valid for that particular command or event. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, most Bluetooth - * commands and events use a coarse address type that only differentiates - * between a public address and any random address. When the application - * includes the bluetooth_feature_use_accurate_api_address_types component, - * Bluetooth commands and events that include an address type will - * systematically use values of this @ref sl_bt_gap_address_type_t enumeration - * to indicate the accurate address type. - * - * The values @ref sl_bt_gap_public_address_resolved_from_rpa and @ref - * sl_bt_gap_static_address_resolved_from_rpa are reported by the Bluetooth - * stack only when the application includes the bluetooth_feature_resolving_list - * component and the address was resolved in the Bluetooth controller. If the - * application uses these two types in input parameters, they are treated as - * synonyms of @ref sl_bt_gap_public_address and @ref sl_bt_gap_static_address, - * respectively. - */ -typedef enum -{ - sl_bt_gap_public_address = 0x0, /**< (0x0) Public device - address */ - sl_bt_gap_static_address = 0x1, /**< (0x1) Static device - address */ - sl_bt_gap_random_resolvable_address = 0x2, /**< (0x2) Resolvable - private random address */ - sl_bt_gap_random_nonresolvable_address = 0x3, /**< (0x3) Non-resolvable - private random address */ - sl_bt_gap_public_address_resolved_from_rpa = 0x4, /**< (0x4) Public identity - address resolved from - a resolvable private - address (RPA) */ - sl_bt_gap_static_address_resolved_from_rpa = 0x5, /**< (0x5) Static identity - address resolved from - a resolvable private - address (RPA) */ - sl_bt_gap_anonymous_address = 0xff /**< (0xff) No address - provided (anonymous - advertising) */ -} sl_bt_gap_address_type_t; - -/** - * @brief Types of PHYs - */ -typedef enum -{ - sl_bt_gap_phy_1m = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_phy_2m = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_phy_coded = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ - sl_bt_gap_phy_any = 0xff /**< (0xff) Any PHYs the device supports */ -} sl_bt_gap_phy_t; - -/** - * @brief PHY types with coding schemes - */ -typedef enum -{ - sl_bt_gap_phy_coding_1m_uncoded = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_phy_coding_2m_uncoded = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_phy_coding_125k_coded = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ - sl_bt_gap_phy_coding_500k_coded = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ -} sl_bt_gap_phy_coding_t; - -/** - * @brief Types of channel selection algorithms in Link Layer - */ -typedef enum -{ - sl_bt_gap_channel_selection_algorithm_1 = 0x0, /**< (0x0) Channel selection - algorithm #1 */ - sl_bt_gap_channel_selection_algorithm_2 = 0x1 /**< (0x1) Channel selection - algorithm #2 */ -} sl_bt_gap_channel_selection_algorithm_t; - -/***************************************************************************//** - * - * Enable or disable the privacy feature on all GAP roles. New privacy mode will - * take effect for advertising next time advertising is enabled, for scanning - * next time scanning is enabled, and for initiating on the next open connection - * command. - * - * When privacy is enabled and the device is advertising or scanning, the stack - * will maintain a periodic timer with the specified time interval as a timeout - * value. At each timeout, the stack generates a new resolvable private address - * and uses it in scanning requests. For advertisers, the stack generates a new - * resolvable or non-resolvable private address and uses it in advertising data - * packets for each advertising set if its address is not application-managed, - * i.e., the address was not set by the application (with the @ref - * sl_bt_advertiser_set_random_address command). The application is fully - * responsible for application-managed advertiser addresses. For an - * application-managed resolvable private address, the application should - * schedule periodic address updates for enhancing the privacy. It is - * recommended to use different schedules for different advertising sets. - * - * Disabling the privacy during active advertising or scanning is not allowed. - * - * By default, privacy feature is disabled. - * - * @param[in] privacy Values: - * - 0: Disable privacy - * - 1: Enable privacy - * @param[in] interval The minimum time interval between a private address - * change. This parameter is ignored if this command is issued to disable - * privacy mode. Values: - * - 0: Use default interval, 15 minutes - * - others: The time interval in minutes - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval); - -/***************************************************************************//** - * - * Specify a channel classification for data channels. This classification - * persists until overwritten with a subsequent command or until the system is - * reset. The value length of @p channel_map must be 5 bytes. - * - * @param[in] channel_map_len Length of data in @p channel_map - * @param[in] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Bits 37-39 are reserved for future use and must be set to 0. - * - * A channel is bad when its bit is 0. A channel is unknown when its bit is 1. - * At least two channels shall be marked as unknown. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, - const uint8_t* channel_map); - -/***************************************************************************//** - * - * Deprecated and replaced by functionality-specific settings provided by - * the bluetooth_feature_accept_list component. For advertising, use the command - * @ref sl_bt_advertiser_configure and @p flags bits @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to configure the - * advertising filter policy. For scanning, use the command @ref - * sl_bt_scanner_set_parameters_and_filter to control the scanning filter - * policy. - * - * Enable or disable accept list filtering. The setting will be effective the - * next time that scanning is enabled. Use command @ref - * sl_bt_sm_add_to_whitelist to add devices to the accept list. - * - * When the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) is used, bonded devices are - * added into the accept list automatically by the stack. Note that the - * Bluetooth stack uses the built-in bonding database by default. - * - * When the application specifically uses the external bonding database - * (bluetooth_feature_external_bonding_database), the application is fully - * responsible for managing the accept list using @ref sl_bt_sm_add_to_whitelist - * and @ref sl_bt_sm_delete_bondings commands. - * - * @param[in] enable 1 enable, 0 disable accept list filtering. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable); - -/***************************************************************************//** - * - * Set the device's Bluetooth identity address to be used in advertising, - * scanning, connection initiation, and identity address exchange in bonding. - * The address is stored in RAM only and does not change the identity address in - * persistent storage. The address can be a public device address or static - * device address. It will be effective immediately in the next advertising, - * scanning, connection initiation, and bonding. Error - * SL_STATUS_INVALID_PARAMETER is returned if the address does not conform to - * the Bluetooth specification. - * - * Note that advertising sets that have own addresses set by @ref - * sl_bt_advertiser_set_random_address are not affected by this command, i.e., - * they will continue to use their own user defined addresses. - * - * @param[in] address The address in little endian format - * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. The address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type); - -/** @} */ // end addtogroup sl_bt_gap - -/** - * @addtogroup sl_bt_advertiser Advertiser - * @{ - * - * @brief Advertiser - * - * This is the base class of legacy, extended, and periodic advertisings for - * common functionalities including advertising set management, TX power - * setting, advertising address, and so on. - * - * On an advertising set, either the legacy or extended advertising can be - * enabled at a time but they cannot be enabled simultaneously on the same - * advertising set. For example, the following sequence shows how to start the - * legacy advertising on an advertising set. Starting the extended advertising - * is similar. The only difference is to use the extended_advertiser API class. - * 1. Create an advertise set with the @ref sl_bt_advertiser_create_set - * command. - * 2. Configure and set advertising parameters for the advertising set as - * needed. - * 3. Set the advertising data with the @ref sl_bt_legacy_advertiser_set_data - * or @ref sl_bt_legacy_advertiser_generate_data command. - * 4. Start the legacy advertising with the @ref sl_bt_legacy_advertiser_start - * command. - * - * Periodic advertising can be enabled independently on the advertising set - * regardless of the state of the legacy or extended advertising. However, to - * ensure that scanners can find the periodic advertising information and - * establish a synchronization, the extended advertising must be enabled - * simultaneously with the periodic advertising. - * - * When the bluetooth_feature_legacy_advertiser, - * bluetooth_feature_extended_advertiser or - * bluetooth_feature_periodic_advertiser component is included by the - * application, commands that have been superseded by the new classes are no - * longer available for use in the advertiser class. Calling them will receive - * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: @ref - * sl_bt_advertiser_set_phy, @ref sl_bt_advertiser_set_configuration, @ref - * sl_bt_advertiser_clear_configuration, @ref sl_bt_advertiser_set_data, @ref - * sl_bt_advertiser_set_long_data, @ref sl_bt_advertiser_start, @ref - * sl_bt_advertiser_start_periodic_advertising, and @ref - * sl_bt_advertiser_stop_periodic_advertising. See the command descriptions for - * the replacements. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_advertiser_create_set_id 0x01040020 -#define sl_bt_cmd_advertiser_configure_id 0x12040020 -#define sl_bt_cmd_advertiser_set_timing_id 0x03040020 -#define sl_bt_cmd_advertiser_set_channel_map_id 0x04040020 -#define sl_bt_cmd_advertiser_set_tx_power_id 0x0b040020 -#define sl_bt_cmd_advertiser_set_report_scan_request_id 0x05040020 -#define sl_bt_cmd_advertiser_set_random_address_id 0x10040020 -#define sl_bt_cmd_advertiser_clear_random_address_id 0x11040020 -#define sl_bt_cmd_advertiser_stop_id 0x0a040020 -#define sl_bt_cmd_advertiser_delete_set_id 0x02040020 -#define sl_bt_cmd_advertiser_set_phy_id 0x06040020 -#define sl_bt_cmd_advertiser_set_configuration_id 0x07040020 -#define sl_bt_cmd_advertiser_clear_configuration_id 0x08040020 -#define sl_bt_cmd_advertiser_set_data_id 0x0f040020 -#define sl_bt_cmd_advertiser_set_long_data_id 0x0e040020 -#define sl_bt_cmd_advertiser_start_id 0x09040020 -#define sl_bt_cmd_advertiser_start_periodic_advertising_id 0x0c040020 -#define sl_bt_cmd_advertiser_stop_periodic_advertising_id 0x0d040020 -#define sl_bt_rsp_advertiser_create_set_id 0x01040020 -#define sl_bt_rsp_advertiser_configure_id 0x12040020 -#define sl_bt_rsp_advertiser_set_timing_id 0x03040020 -#define sl_bt_rsp_advertiser_set_channel_map_id 0x04040020 -#define sl_bt_rsp_advertiser_set_tx_power_id 0x0b040020 -#define sl_bt_rsp_advertiser_set_report_scan_request_id 0x05040020 -#define sl_bt_rsp_advertiser_set_random_address_id 0x10040020 -#define sl_bt_rsp_advertiser_clear_random_address_id 0x11040020 -#define sl_bt_rsp_advertiser_stop_id 0x0a040020 -#define sl_bt_rsp_advertiser_delete_set_id 0x02040020 -#define sl_bt_rsp_advertiser_set_phy_id 0x06040020 -#define sl_bt_rsp_advertiser_set_configuration_id 0x07040020 -#define sl_bt_rsp_advertiser_clear_configuration_id 0x08040020 -#define sl_bt_rsp_advertiser_set_data_id 0x0f040020 -#define sl_bt_rsp_advertiser_set_long_data_id 0x0e040020 -#define sl_bt_rsp_advertiser_start_id 0x09040020 -#define sl_bt_rsp_advertiser_start_periodic_advertising_id 0x0c040020 -#define sl_bt_rsp_advertiser_stop_periodic_advertising_id 0x0d040020 - -/** - * @brief These values define the available connection modes, which indicate - * whether the device accepts connection requests or scan requests. - */ -typedef enum -{ - sl_bt_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable - non-scannable */ - sl_bt_advertiser_connectable_scannable = 0x2, /**< (0x2) Undirected - connectable scannable. - This mode can only be - used in legacy - advertising PDUs. */ - sl_bt_advertiser_scannable_non_connectable = 0x3, /**< (0x3) Undirected - scannable - (Non-connectable but - responds to scan - requests) */ - sl_bt_advertiser_connectable_non_scannable = 0x4 /**< (0x4) Undirected - connectable - non-scannable. This - mode can only be used - in extended advertising - PDUs. */ -} sl_bt_advertiser_connection_mode_t; - -/** - * @brief These values define the available discovery modes, which dictate how - * the device is visible to other devices in the legacy and extended - * advertising. - */ -typedef enum -{ - sl_bt_advertiser_non_discoverable = 0x0, /**< (0x0) Not discoverable */ - sl_bt_advertiser_limited_discoverable = 0x1, /**< (0x1) Discoverable by both - limited and general - discovery procedures */ - sl_bt_advertiser_general_discoverable = 0x2, /**< (0x2) Discoverable by the - general discovery procedure */ - sl_bt_advertiser_broadcast = 0x3, /**< (0x3) Device is not - discoverable in either - limited or generic discovery - procedure but may be - discovered using the - Observation procedure. */ - sl_bt_advertiser_user_data = 0x4 /**< (0x4) Send advertising - and/or scan response data - defined by the user. The - discovery mode is defined by - the user. */ -} sl_bt_advertiser_discovery_mode_t; - -/** - * @brief Address type to use for the legacy and extended advertising - */ -typedef enum -{ - sl_bt_advertiser_identity_address = 0x0, /**< (0x0) Use public or static - device address, or an identity - address if privacy mode is - enabled. */ - sl_bt_advertiser_non_resolvable = 0x1 /**< (0x1) Use non-resolvable address - type; the advertising must be - non-connectable. */ -} sl_bt_advertiser_adv_address_type_t; - -/** - * @brief These values define the packet types in legacy and extended - * advertising. - */ -typedef enum -{ - sl_bt_advertiser_advertising_data_packet = 0x0, /**< (0x0) Advertising data - packet */ - sl_bt_advertiser_scan_response_packet = 0x1 /**< (0x1) Scan response - packet */ -} sl_bt_advertiser_packet_type_t; - -/** - * @addtogroup sl_bt_advertiser_flags Generic Advertising Configuration Flags - * @{ - * - * This enum defines configuration flags common for legacy and extended - * advertisings. - */ - -/** Use a non-resolvable private address managed by the stack. The advertising - * must be non-connectable when using this configuration. The stack generates a - * non-resolvable private address for the advertising set and the stack will - * update the address periodically in privacy mode. By default this flag is not - * set, i.e., the advertising address uses the device identity address. This - * configuration has no effect if the advertising address has been set with the - * @ref sl_bt_advertiser_set_random_address command. */ -#define SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS 0x4 - -/** Use the device identity address when privacy mode is enabled. By default, - * this flag is not set, i.e., the advertising address uses a resolvable private - * address managed by the stack in privacy mode. This configuration has no - * effect if the @ref SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS flag is set or - * the advertising address has been set with the @ref - * sl_bt_advertiser_set_random_address command. */ -#define SL_BT_ADVERTISER_USE_DEVICE_IDENTITY_IN_PRIVACY 0x10 - -/** - * - * Use the Filter Accept List to filter scan requests received while performing - * scannable advertising with this advertising set. By default, this flag is not - * set and scan requests from all devices are processed. If the application sets - * this flag, scan requests are processed only from those devices that the - * application has added to the Filter Accept List. - * - * This configuration is supported only when the application has included the - * Bluetooth component bluetooth_feature_accept_list. - * - * */ -#define SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS 0x20 - -/** - * - * Use the Filter Accept List to filter connection requests received while - * performing connectable advertising with this advertising set. By default, - * this flag is not set and connection requests from all devices are processed. - * If the application sets this flag, connection requests are processed only - * from those devices that the application has added to the Filter Accept List. - * - * This configuration is supported only when the application has included the - * Bluetooth component bluetooth_feature_accept_list. - * - * */ -#define SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS 0x40 - -/** @} */ // end Generic Advertising Configuration Flags - -/** - * @addtogroup sl_bt_evt_advertiser_timeout sl_bt_evt_advertiser_timeout - * @{ - * @brief Indicates the legacy or extended advertising on an advertising set has - * stopped because the advertiser has completed the configured number of - * advertising events or the advertising has reached the configured duration - * - * The maximum number of advertising events or advertising duration can be - * configured by the @p maxevents or @p duration parameter in the command @ref - * sl_bt_advertiser_set_timing. - */ - -/** @brief Identifier of the timeout event */ -#define sl_bt_evt_advertiser_timeout_id 0x010400a0 - -/***************************************************************************//** - * @brief Data structure of the timeout event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_advertiser_timeout_s -{ - uint8_t handle; /**< The advertising set handle */ -}); - -typedef struct sl_bt_evt_advertiser_timeout_s sl_bt_evt_advertiser_timeout_t; - -/** @} */ // end addtogroup sl_bt_evt_advertiser_timeout - -/** - * @addtogroup sl_bt_evt_advertiser_scan_request sl_bt_evt_advertiser_scan_request - * @{ - * @brief Reports a scan request received during the legacy or extended - * advertising advertising if the scan request notification is enabled - * - * Do not confuse this event with the @ref sl_bt_evt_scanner_scan_report event. - */ - -/** @brief Identifier of the scan_request event */ -#define sl_bt_evt_advertiser_scan_request_id 0x020400a0 - -/***************************************************************************//** - * @brief Data structure of the scan_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_advertiser_scan_request_s -{ - uint8_t handle; /**< Advertising set handle where the scan request was - received */ - bd_addr address; /**< Bluetooth address of the scanner */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Scanner address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): Public - device address - - sl_bt_gap_static_address (0x1): Static - device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote scanning device has - previously bonded with the local device. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): No - bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_advertiser_scan_request_s sl_bt_evt_advertiser_scan_request_t; - -/** @} */ // end addtogroup sl_bt_evt_advertiser_scan_request - -/***************************************************************************//** - * - * Create an advertising set that can be used for legacy, extended, or periodic - * advertising. The handle of the created advertising set is returned in - * response if the operation succeeds. - * - * The maximum number of advertising sets for user advertisers is limited by the - * SL_BT_CONFIG_USER_ADVERTISERS configuration. - * - * @param[out] handle Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_create_set(uint8_t *handle); - -/***************************************************************************//** - * - * Configure the legacy and extended advertising on an advertising set. The - * configuration will take effect next time the legacy or extended advertising - * is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] flags @parblock - * Configuration flags. Value: 0 or bitmask of @ref sl_bt_advertiser_flags - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags); - -/***************************************************************************//** - * - * Set the timing parameters for legacy or extended advertising on an - * advertising set. This setting will take effect next time the legacy or - * extended advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum advertising interval. Value in units of 0.625 ms - * - Range: 0x20 to 0xFFFFFF - * - Time range: 20 ms to 10485.759375 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum advertising interval. Value in units of 0.625 ms - * - Range: 0x20 to 0xFFFFFF - * - Time range: 20 ms to 10485.759375 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] duration @parblock - * Advertising duration for this advertising set. Value 0 indicates no - * advertising duration limit and advertising continues until it is disabled. - * A non-zero value sets the duration in units of 10 ms. The duration begins - * at the start of the first advertising event of this advertising set. - * - Range: 0x0001 to 0xFFFF - * - Time range: 10 ms to 655.35 s - * - * Default value: 0 - * @endparblock - * @param[in] maxevents @parblock - * If non-zero, indicates the maximum number of advertising events to send - * before the advertiser is stopped. Value 0 indicates no maximum number - * limit. - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, - uint32_t interval_min, - uint32_t interval_max, - uint16_t duration, - uint8_t maxevents); - -/***************************************************************************//** - * - * Set the primary advertising channel map on an advertising set. This setting - * will take effect next time when the legacy or extended advertising is - * enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] channel_map @parblock - * Advertising channel map which determines, which of the three channels will - * be used for advertising. This value is given as a bitmask. Values: - * - 1: Advertise on CH37 - * - 2: Advertise on CH38 - * - 3: Advertise on CH37 and CH38 - * - 4: Advertise on CH39 - * - 5: Advertise on CH37 and CH39 - * - 6: Advertise on CH38 and CH39 - * - 7: Advertise on all channels - * - * Recommended value: 7 - * - * Default value: 7 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, - uint8_t channel_map); - -/***************************************************************************//** - * - * Limit the maximum advertising TX power on an advertising set. If the value - * goes over the global value that was set using the @ref - * sl_bt_system_set_tx_power command, the global value will be the maximum - * limit. The maximum TX power of legacy advertising is further constrained to - * be less than +10 dBm. Extended advertising TX power can be +10 dBm and over - * if Adaptive Frequency Hopping is enabled. This setting has no effect on - * periodic advertising. - * - * This setting will take effect next time the legacy or extended advertising is - * enabled. - * - * By default, maximum advertising TX power is limited by the global value. - * - * @param[in] advertising_set Advertising set handle - * @param[in] power TX power in 0.1 dBm steps. For example, the value of 10 is 1 - * dBm and 55 is 5.5 dBm. - * @param[out] set_power The selected maximum advertising TX power - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, - int16_t power, - int16_t *set_power); - -/***************************************************************************//** - * - * Enable or disable the scan request notification on an advertising set. This - * setting will take effect next time the legacy or extended advertising is - * enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] report_scan_req @parblock - * If non-zero, enables scan request notification and scan requests will be - * reported as events. - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_scan_request - Triggered when a scan request is - * received during advertising if the scan request notification is enabled - * by this command. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, - uint8_t report_scan_req); - -/***************************************************************************//** - * - * Set the advertiser on an advertising set to use a random address. This - * overrides the default advertiser address, which is either the public device - * address programmed at production or the address written into persistent - * storage using @ref sl_bt_system_set_identity_address command. This setting is - * stored in RAM only and does not change the identity address in persistent - * storage. In privacy mode, the stack does not change an advertiser address set - * by this command. To ensure that the stack can manage the address update - * periodically in privacy mode, the address setting should be removed with the - * @ref sl_bt_advertiser_clear_random_address command. - * - * When setting a resolvable random address, the address parameter is ignored. - * The stack generates one and set it as the advertiser address. The generated - * address is returned in the response. To enhance the privacy, the application - * should schedule periodic address updates by calling this command - * periodically. Use different schedules for different advertising sets. - * - * To use the default advertiser address, remove this setting using @ref - * sl_bt_advertiser_clear_random_address command. - * - * Wrong state error is returned if advertising has been enabled on the - * advertising set. Invalid parameter error is returned if the advertising set - * handle is invalid or the address does not conform to the Bluetooth - * specification. - * - * @param[in] advertising_set Advertising set handle - * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. Address type. - * Values: - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address. This type can only be used for non-connectable - * advertising. - * @param[in] address The random address to set. Ignore this field when setting - * a resolvable random address. - * @param[out] address_out The resolvable random address set for the advertiser. - * Ignore this field when setting other types of random addresses. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, - uint8_t addr_type, - bd_addr address, - bd_addr *address_out); - -/***************************************************************************//** - * - * Clear the random address previously set for the advertiser address on an - * advertising set. To set a random address, use @ref - * sl_bt_advertiser_set_random_address command. The default advertiser address - * will be used after this operation. - * - * The error SL_STATUS_INVALID_STATE is returned if advertising has been enabled - * on the advertising set. An invalid parameter error is returned if the - * advertising set handle is invalid. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set); - -/***************************************************************************//** - * - * Stop the legacy or extended advertising on an advertising set. Counterpart - * with @ref sl_bt_legacy_advertiser_start or @ref - * sl_bt_extended_advertiser_start. - * - * This command does not affect the enable state of the periodic advertising on - * the advertising set, i.e., periodic advertising is not stopped. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set); - -/***************************************************************************//** - * - * Delete an advertising set. Any enabled legacy, extended, or periodic - * advertising is stopped before the deletion. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_extended_advertiser_set_phy. - * - * Set the primary and secondary advertising PHYs used for extended and periodic - * advertising on an advertising set. This setting will take effect next time - * extended or periodic advertising is enabled. When advertising on the LE Coded - * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is - * returned if a PHY value is invalid or the device does not support a given - * PHY. - * - * @param[in] advertising_set Advertising set handle - * @param[in] primary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the primary advertising channel. If legacy advertising PDUs - * are used, 1M PHY must be used. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * @param[in] secondary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the secondary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_advertiser_configure command. - * - * Enable advertising configuration flags on an advertising set. The - * configuration change will take effect next time the legacy or extended - * advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] configurations @parblock - * Advertising configuration flags to enable. This value can be a bitmask of - * multiple flags. Flags: - * - 1 (Bit 0): Use legacy advertising PDUs. - * - 2 (Bit 1): Omit advertiser's address from all PDUs (anonymous - * advertising). This flag is effective only in extended advertising. - * - 4 (Bit 2): Use a non-resolvable private address. When this - * configuration is enabled, the advertising must use non-connectable - * mode. The stack generates a non-resolvable private address for the - * advertising set and the stack will update the address periodically when - * the privacy mode is enabled. This configuration is ignored if the - * advertiser address has been set with the @ref - * sl_bt_advertiser_set_random_address command. - * - 8 (Bit 3): Include TX power in advertising packets. This flag is - * effective only in extended advertising. - * - 16 (Bit 4): Use the device identity address when the privacy - * mode is enabled in the stack. This configuration is ignored if the - * configuration of using non-resolvable private address is enabled or the - * advertising address has been set with the @ref - * sl_bt_advertiser_set_random_address command. - * - * Default value: 1 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, - uint32_t configurations); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_advertiser_configure command. - * - * Disable advertising configuration flags on an advertising set. The - * configuration change will take effect next time the legacy or extended - * advertising is enabled. - * - * @param[in] advertising_set Advertising set handle - * @param[in] configurations Advertising configuration flags to disable. This - * value can be a bitmask of multiple flags. See @ref - * sl_bt_advertiser_set_configuration for possible flags. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, - uint32_t configurations); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_legacy_advertiser_set_data for - * legacy advertising PDUs, @ref sl_bt_extended_advertiser_set_data for extended - * advertising PDUs, and @ref sl_bt_periodic_advertiser_set_data for periodic - * advertising PDUs. - * - * Set user-defined data in advertising packets, scan response packets, or - * periodic advertising packets. Maximum 31 bytes of data can be set for legacy - * advertising. Maximum 191 bytes of data can be set for connectable extended - * advertising. Maximum 253 bytes of data can be set for periodic and - * non-connectable extended advertising. For setting longer advertising data, - * use command @ref sl_bt_advertiser_set_long_data. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_advertiser_start. Periodic advertising mode can be enabled using - * command @ref sl_bt_advertiser_start_periodic_advertising. - * - * The invalid parameter error will be returned in the following situations: - * - Data length is more than 31 bytes but the advertiser can only advertise - * using legacy advertising PDUs. - * - Data is too long to fit into a single advertisement. - * - Set data of the advertising data packet when the scannable advertising is - * enabled using extended advertising PDUs. - * - Set data of the scan response data packet when the connectable - * advertising is enabled using extended advertising PDUs. - * - * Note that the user-defined data may be overwritten by the system when the - * advertising is later enabled in a discovery mode other than user_data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] packet_type This value selects whether data is intended for - * advertising packets, scan response packets, or periodic advertising - * packets. - * - 0: Advertising packets - * - 1: Scan response packets - * - 8: Periodic advertising packets - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, - uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_extended_advertiser_set_long_data for extended advertising PDUs and - * @ref sl_bt_periodic_advertiser_set_long_data for periodic advertising PDUs. - * - * Set advertising data for a specified packet type and advertising set. Data - * currently in the system data buffer will be extracted as the advertising - * data. The buffer will be emptied after this command regardless of the - * completion status. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. - * - * Maximum 31 bytes of data can be set for legacy advertising. Maximum 191 bytes - * of data can be set for connectable extended advertising. Maximum 1650 bytes - * of data can be set for periodic and non-connectable extended advertising, but - * advertising parameters may limit the amount of data that can be sent in a - * single advertisement. - * - * See @ref sl_bt_advertiser_set_data for more details on advertising data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] packet_type This value selects whether data is intended for - * advertising packets, scan response packets, or periodic advertising - * packets. Values: - * - 0: Advertising packets - * - 1: Scan response packets - * - 8: Periodic advertising packets - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, - uint8_t packet_type); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_legacy_advertiser_start and @ref - * sl_bt_extended_advertiser_start commands. - * - * Start the legacy or extended advertising on an advertising set with specified - * discovery and connection modes. - * - * The number of concurrent connectable advertisings is limited by the number of - * connections reserved by the user application (the - * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other - * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This - * command fails with the connection limit exceeded error if it may cause the - * number of connections exceeding the configured value in future. For example, - * only one connectable advertising can be enabled if the device has - * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. - * This limitation does not apply to non-connectable advertising. - * - * The default advertising configuration in the stack is set to using legacy - * advertising PDUs on 1M PHY. The stack will automatically select extended - * advertising PDUs if either of the following has occurred with the default - * configuration: - * 1. The connection mode is set to @ref - * sl_bt_advertiser_connectable_non_scannable. - * 2. The primary advertising PHY is set to Coded PHY by @ref - * sl_bt_extended_advertiser_set_phy. - * 3. The user advertising data length is more than 31 bytes. - * 4. Periodic advertising is enabled. - * - * This command fails with the invalid parameter error if one of the following - * cases occurs: - * 1. Non-resolvable random address is used but the connection mode is - * advertiser_connectable_scannable or - * advertiser_connectable_non_scannable. - * 2. advertiser_connectable_non_scannable is the connection mode but using - * legacy advertising PDUs has been explicitly enabled with command @ref - * sl_bt_advertiser_set_configuration. - * 3. Coded PHY is the primary advertising PHY but using legacy advertising - * PDUs has been explicitly enabled with command @ref - * sl_bt_advertiser_set_configuration. - * 4. advertiser_connectable_scannable is the connection mode but using - * extended advertising PDUs has been explicitly enabled or the primary - * advertising PHY is set to Coded PHY. - * - * If advertising is enabled in user_data mode, use @ref - * sl_bt_advertiser_set_data to set advertising and scan response data before - * issuing this command. When advertising is enabled in modes other than - * user_data, advertising and scan response data is generated by the stack using - * the following procedure: - * 1. Add a flags field to advertising data. - * 2. Add a TX power level field to advertising data if the TX power service - * exists in the local GATT database. - * 3. Add a peripheral connection interval range field to advertising data if - * the GAP peripheral preferred connection parameters characteristic exists - * in the local GATT database. - * 4. Add a list of 16-bit service UUIDs to advertising data if there are one - * or more 16-bit service UUIDs to advertise. The list is complete if all - * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is - * incomplete. - * 5. Add a list of 128-bit service UUIDs to advertising data if there are one - * or more 128-bit service UUIDs to advertise and there is still free space - * for this field. The list is complete if all advertised 128-bit UUIDs are - * in advertising data. Otherwise, the list is incomplete. Note that an - * advertising data packet can contain at most one 128-bit service UUID. - * 6. Try to add the full local name to advertising data if the device is not - * in privacy mode. If the full local name does not fit into the remaining - * free space, the advertised name is a shortened version by cutting off - * the end if the free space has at least 6 bytes. Otherwise, the local - * name is added to scan response data. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. Discovery - * mode. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - sl_bt_advertiser_broadcast (0x3): Device is not discoverable in - * either limited or generic discovery procedure but may be discovered - * using the Observation procedure. - * - sl_bt_advertiser_user_data (0x4): Send advertising and/or scan - * response data defined by the user. The discovery mode is defined by the - * user. - * @param[in] connect Enum @ref sl_bt_advertiser_connection_mode_t. Connection - * mode. Values: - * - sl_bt_advertiser_non_connectable (0x0): Non-connectable - * non-scannable - * - sl_bt_advertiser_connectable_scannable (0x2): Undirected - * connectable scannable. This mode can only be used in legacy advertising - * PDUs. - * - sl_bt_advertiser_scannable_non_connectable (0x3): Undirected - * scannable (Non-connectable but responds to scan requests) - * - sl_bt_advertiser_connectable_non_scannable (0x4): Undirected - * connectable non-scannable. This mode can only be used in extended - * advertising PDUs. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and advertising has stopped on an advertising set. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, - uint8_t discover, - uint8_t connect); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_periodic_advertiser_start - * command. - * - * Start periodic advertising on an advertising set. The stack enables the - * advertising set automatically if the set was not enabled and the set can - * advertise using extended advertising PDUs beside the syncInfo, which is - * needed for the periodic advertising. - * - * The invalid parameter error is returned if the application has configured - * legacy advertising PDUs or anonymous advertising, or the advertising set is - * enabled using legacy advertising PDUs. - * - * To stop periodic advertising, use @ref - * sl_bt_advertiser_stop_periodic_advertising command with the handle received - * in response from this command. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Periodic advertising configurations. Bitmask of the - * following: - * - Bit 0: Include TX power in advertising PDU - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_periodic_advertiser_stop - * command. - * - * Stop periodic advertising on an advertising set. Counterpart with @ref - * sl_bt_advertiser_start_periodic_advertising. - * - * This command does not affect the enable state of the advertising set, i.e., - * legacy or extended advertising is not stopped. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_advertiser - -/** - * @addtogroup sl_bt_legacy_advertiser Legacy Advertiser - * @{ - * - * @brief Legacy Advertiser - * - * The commands and events in this class are related to legacy advertising - * functionalities. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_legacy_advertiser_set_data_id 0x00560020 -#define sl_bt_cmd_legacy_advertiser_generate_data_id 0x01560020 -#define sl_bt_cmd_legacy_advertiser_start_id 0x02560020 -#define sl_bt_cmd_legacy_advertiser_start_directed_id 0x03560020 -#define sl_bt_rsp_legacy_advertiser_set_data_id 0x00560020 -#define sl_bt_rsp_legacy_advertiser_generate_data_id 0x01560020 -#define sl_bt_rsp_legacy_advertiser_start_id 0x02560020 -#define sl_bt_rsp_legacy_advertiser_start_directed_id 0x03560020 - -/** - * @brief These values define the available connection modes of undirected - * legacy advertising. - */ -typedef enum -{ - sl_bt_legacy_advertiser_non_connectable = 0x0, /**< (0x0) Undirected - non-connectable and - non-scannable legacy - advertising */ - sl_bt_legacy_advertiser_connectable = 0x2, /**< (0x2) Undirected - connectable and scannable - legacy advertising */ - sl_bt_legacy_advertiser_scannable = 0x3 /**< (0x3) Undirected scannable - and non-connectable legacy - advertising */ -} sl_bt_legacy_advertiser_connection_mode_t; - -/** - * @brief These values define the available connection modes of directed legacy - * advertising. - */ -typedef enum -{ - sl_bt_legacy_advertiser_high_duty_directed_connectable = 0x1, /**< (0x1) High - duty cycle - directed - connectable - legacy - advertising */ - sl_bt_legacy_advertiser_low_duty_directed_connectable = 0x5 /**< (0x5) Low - duty cycle - directed - connectable - legacy - advertising */ -} sl_bt_legacy_advertiser_directed_connection_mode_t; - -/***************************************************************************//** - * - * Set user-defined advertising data packet or scan response packet on an - * advertising set. This overwrites the existing advertising data packet and - * scan response packet on this advertising set regardless of whether the data - * was set for the legacy or extended advertising. Maximum 31 bytes of data can - * be set with this command. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_legacy_advertiser_start. - * - * @param[in] advertising_set Advertising set handle - * @param[in] type Enum @ref sl_bt_advertiser_packet_type_t. The advertising - * packet type - * @param[in] data_len Length of data in @p data - * @param[in] data Data to set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Ask the stack to generate the advertising data packet and scan response - * packet on an advertising set. Alternatively, the user-defined advertising - * data can be set using the @ref sl_bt_legacy_advertiser_set_data command. - * - * This overwrites the existing advertising data packet and scan response packet - * on this advertising set regardless of whether the data was set for the legacy - * or extended advertising. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. To enable advertising mode, use command @ref - * sl_bt_legacy_advertiser_start. - * - * The stack generates the advertising data and scan response packet using the - * following logic. - * 1. Add a flags field to advertising data. - * 2. Add a TX power level field to advertising data if the TX power service - * exists in the local GATT database. - * 3. Add a peripheral connection interval range field to advertising data if - * the GAP peripheral preferred connection parameters characteristic exists - * in the local GATT database. - * 4. Add a list of 16-bit service UUIDs to advertising data if there are one - * or more 16-bit service UUIDs to advertise. The list is complete if all - * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is - * incomplete. - * 5. Add a list of 128-bit service UUIDs to advertising data if there are one - * or more 128-bit service UUIDs to advertise and there is still free space - * for this field. The list is complete if all advertised 128-bit UUIDs are - * in advertising data. Otherwise, the list is incomplete. Note that an - * advertising data packet can contain at most one 128-bit service UUID. - * 6. Try to add the full local name to advertising data if the device is not - * in privacy mode. If the full local name does not fit into the remaining - * free space, the advertised name is a shortened version by cutting off - * the end if the free space has at least 6 bytes. Otherwise, the local - * name is added to scan response data. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The - * discovery mode for the Flags data field in the packet. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover); - -/***************************************************************************//** - * - * Start undirected legacy advertising on an advertising set with the specified - * connection mode. Use @ref sl_bt_advertiser_stop to stop the advertising. - * - * Use the @ref sl_bt_legacy_advertiser_set_data or @ref - * sl_bt_legacy_advertiser_generate_data command to set the advertising data - * before calling this command. The advertising data is added into the - * advertising data packet and scan response packet if the connection mode is - * connectable and/or scannable. The data is only added into the advertising - * data packet when the connection mode is non-connectable and non-scannable. - * - * The number of concurrent connectable advertisings is limited by the number of - * connections reserved by the user application (the - * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other - * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This - * command fails with the connection limit exceeded error if it may cause the - * number of connections exceeding the configured value in future. For example, - * only one connectable advertising can be enabled if the device has - * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. - * This limitation does not apply to non-connectable advertising. - * - * This command fails with the invalid parameter error if non-resolvable random - * address is used but the connection mode is @ref - * sl_bt_legacy_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_legacy_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_legacy_advertiser_non_connectable (0x0): Undirected - * non-connectable and non-scannable legacy advertising - * - sl_bt_legacy_advertiser_connectable (0x2): Undirected - * connectable and scannable legacy advertising - * - sl_bt_legacy_advertiser_scannable (0x3): Undirected scannable - * and non-connectable legacy advertising - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, - uint8_t connect); - -/***************************************************************************//** - * - * Start directed legacy advertising on an advertising set with the specified - * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to - * stop the advertising. - * - * Directed legacy advertising does not allow any advertising data. When the - * connection mode is @ref - * sl_bt_legacy_advertiser_high_duty_directed_connectable, the stack defaults - * the advertising duration to 0.64 s if the application has not set the - * parameter. The duration is reduced to 1.28 s if the application has set a - * larger duration value. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if non-resolvable random - * address is set as the advertising address. - * - * Event @ref sl_bt_evt_connection_opened will be received when the target - * device opens a connection to the advertiser on this advertising set. As a - * result, the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising - * stops and no Bluetooth connection is opened to it. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref - * sl_bt_legacy_advertiser_directed_connection_mode_t. Connection mode. - * Values: - * - sl_bt_legacy_advertiser_high_duty_directed_connectable (0x1): - * High duty cycle directed connectable legacy advertising - * - sl_bt_legacy_advertiser_low_duty_directed_connectable (0x5): Low - * duty cycle directed connectable legacy advertising - * @param[in] peer_addr Address of the peer target device the advertising is - * directed to - * @param[in] peer_addr_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Peer target device address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - bd_addr peer_addr, - uint8_t peer_addr_type); - -/** @} */ // end addtogroup sl_bt_legacy_advertiser - -/** - * @addtogroup sl_bt_extended_advertiser Extended Advertiser - * @{ - * - * @brief Extended Advertiser - * - * The commands and events in this class are related to extended advertising - * functionalities in GAP peripheral and broadcaster roles. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_extended_advertiser_set_phy_id 0x00570020 -#define sl_bt_cmd_extended_advertiser_set_data_id 0x01570020 -#define sl_bt_cmd_extended_advertiser_set_long_data_id 0x02570020 -#define sl_bt_cmd_extended_advertiser_generate_data_id 0x03570020 -#define sl_bt_cmd_extended_advertiser_start_id 0x04570020 -#define sl_bt_cmd_extended_advertiser_start_directed_id 0x05570020 -#define sl_bt_rsp_extended_advertiser_set_phy_id 0x00570020 -#define sl_bt_rsp_extended_advertiser_set_data_id 0x01570020 -#define sl_bt_rsp_extended_advertiser_set_long_data_id 0x02570020 -#define sl_bt_rsp_extended_advertiser_generate_data_id 0x03570020 -#define sl_bt_rsp_extended_advertiser_start_id 0x04570020 -#define sl_bt_rsp_extended_advertiser_start_directed_id 0x05570020 - -/** - * @brief These values define the available connection modes in extended - * advertising. - */ -typedef enum -{ - sl_bt_extended_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable - and non-scannable - extended advertising */ - sl_bt_extended_advertiser_scannable = 0x3, /**< (0x3) Scannable extended - advertising */ - sl_bt_extended_advertiser_connectable = 0x4 /**< (0x4) Connectable - extended advertising */ -} sl_bt_extended_advertiser_connection_mode_t; - -/** - * @addtogroup sl_bt_extended_advertiser_flags Extended Advertising Configuration Flags - * @{ - * - * This enum defines configuration flags for the extended advertising. - */ - -/** Omit advertiser's address from all PDUs (anonymous advertising). The - * advertising cannot be connectable or scannable if this flag is set. */ -#define SL_BT_EXTENDED_ADVERTISER_ANONYMOUS_ADVERTISING 0x1 - -/** Include the TX power in advertising packets. */ -#define SL_BT_EXTENDED_ADVERTISER_INCLUDE_TX_POWER 0x2 - -/** @} */ // end Extended Advertising Configuration Flags - -/***************************************************************************//** - * - * Set the primary and secondary advertising PHYs used for extended and periodic - * advertising on an advertising set. This setting will take effect next time - * extended or periodic advertising is enabled. When advertising on the LE Coded - * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is - * returned if a PHY value is invalid or the device does not support a given - * PHY. - * - * @param[in] advertising_set Advertising set handle - * @param[in] primary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the primary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * @param[in] secondary_phy @parblock - * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are - * transmitted on the secondary advertising channel. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) - * - * Default value: @ref sl_bt_gap_phy_1m - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, - uint8_t primary_phy, - uint8_t secondary_phy); - -/***************************************************************************//** - * - * Set user-defined data for extended advertising. This overwrites the existing - * advertising data packet and scan response packet on this advertising set - * regardless of whether the data was set for the legacy or extended - * advertising. Maximum 191 bytes of data can be set for connectable extended - * advertising. Maximum 253 bytes of data can be set for non-connectable - * extended advertising. For setting longer advertising data, use command @ref - * sl_bt_extended_advertiser_set_long_data. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. Advertising mode can be enabled using command @ref - * sl_bt_extended_advertiser_start. - * - * The invalid parameter error is returned if the data is too long to fit into a - * single advertisement. - * - * @param[in] advertising_set Advertising set handle - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set long user-defined data for extended advertising. This overwrites the - * existing advertising data packet and scan response packet on this advertising - * set regardless of whether the data was set for the legacy or extended - * advertising. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. When this command is called, - * the data in the system data buffer is extracted as the advertising data. The - * buffer will be emptied after this command regardless of the completion - * status. - * - * Maximum 191 bytes of data can be set for connectable extended advertising. - * Maximum 1650 bytes of data can be set for non-connectable extended - * advertising. Advertising parameters may limit the amount of data that can be - * sent in a single advertisement. See @ref sl_bt_extended_advertiser_set_data - * for more details. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set); - -/***************************************************************************//** - * - * Ask the stack to generate the extended advertising data on an advertising - * set. Alternatively, user-defined advertising data can be set using the @ref - * sl_bt_extended_advertiser_set_data command. - * - * This overwrites the existing advertising data packet and scan response packet - * on this advertising set regardless of whether the data was set for the legacy - * or extended advertising. - * - * If advertising mode is currently enabled, the new advertising data will be - * used immediately. To enable advertising mode, use command @ref - * sl_bt_extended_advertiser_start. - * - * See @ref sl_bt_legacy_advertiser_generate_data for the advertising data - * generation logic. - * - * @param[in] advertising_set Advertising set handle - * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The - * discovery mode for the Flags data field in the packet. Values: - * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable - * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by - * both limited and general discovery procedures - * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the - * general discovery procedure - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, - uint8_t discover); - -/***************************************************************************//** - * - * Start undirected extended advertising on an advertising set with the - * specified connection mode. Use @ref sl_bt_advertiser_stop to stop the - * advertising. - * - * Use the @ref sl_bt_extended_advertiser_set_data or @ref - * sl_bt_extended_advertiser_generate_data command to set the advertising data - * before calling this command. Advertising data is added into the scan response - * packet if the connection mode is scannable. Otherwise, data is in the - * advertising data packet. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if the advertising uses a - * non-resolvable random address but the connection mode is @ref - * sl_bt_extended_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when a remote device - * opens a connection to the advertiser on this advertising set. As a result, - * the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is done - * and the advertising has stopped. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable - * and non-scannable extended advertising - * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended - * advertising - * - sl_bt_extended_advertiser_connectable (0x4): Connectable - * extended advertising - * @param[in] flags Additional extended advertising options. Value: 0 or bitmask - * of @ref sl_bt_extended_advertiser_flags - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and advertising has stopped on an advertising set. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, - uint8_t connect, - uint32_t flags); - -/***************************************************************************//** - * - * Start directed extended advertising on an advertising set with the specified - * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to - * stop the advertising. - * - * The number of concurrent connectable advertisings is limited by the - * connection number configuration. See @ref sl_bt_legacy_advertiser_start for - * more details. - * - * This command fails with the invalid parameter error if the advertising uses a - * non-resolvable random address but the connection mode is @ref - * sl_bt_extended_advertiser_connectable. - * - * Event @ref sl_bt_evt_connection_opened will be received when the target - * device opens a connection to the advertiser on this advertising set. As a - * result, the advertising stops. - * - * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising - * stops and no Bluetooth connection is opened to it. - * - * @param[in] advertising_set Advertising set handle - * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. - * Connection mode. Values: - * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable - * and non-scannable extended advertising - * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended - * advertising - * - sl_bt_extended_advertiser_connectable (0x4): Connectable - * extended advertising - * @param[in] flags Additional extended advertising options. Value: 0 or bitmask - * of @ref sl_bt_extended_advertiser_flags - * @param[in] peer_addr Address of the peer target device the advertising is - * directed to - * @param[in] peer_addr_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Peer target device address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p - * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of - * advertising events set by @ref sl_bt_advertiser_set_timing command is - * done and the advertising has stopped. - * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a - * connection to the advertiser and the advertising has stopped. - * - ******************************************************************************/ -sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, - uint8_t connect, - uint32_t flags, - bd_addr peer_addr, - uint8_t peer_addr_type); - -/** @} */ // end addtogroup sl_bt_extended_advertiser - -/** - * @addtogroup sl_bt_periodic_advertiser Periodic Advertiser - * @{ - * - * @brief Periodic Advertiser - * - * Provides support for advertising with periodic advertising trains that do not - * have subevents or response slots. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_periodic_advertiser_set_data_id 0x00580020 -#define sl_bt_cmd_periodic_advertiser_set_long_data_id 0x01580020 -#define sl_bt_cmd_periodic_advertiser_start_id 0x02580020 -#define sl_bt_cmd_periodic_advertiser_stop_id 0x03580020 -#define sl_bt_rsp_periodic_advertiser_set_data_id 0x00580020 -#define sl_bt_rsp_periodic_advertiser_set_long_data_id 0x01580020 -#define sl_bt_rsp_periodic_advertiser_start_id 0x02580020 -#define sl_bt_rsp_periodic_advertiser_stop_id 0x03580020 - -/** - * @addtogroup sl_bt_periodic_advertiser_flags Periodic Advertising Configuration Flags - * @{ - * - * Defines configuration flags for periodic advertising. - */ - -/** Include the TX power in advertising packets. */ -#define SL_BT_PERIODIC_ADVERTISER_INCLUDE_TX_POWER 0x1 - -/** Automatically start the extended advertising on the advertising set. The - * advertising will be started in non-connectable and non-scannable mode. */ -#define SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING 0x2 - -/** @} */ // end Periodic Advertising Configuration Flags - -/** - * @cond RESTRICTED - * - * @addtogroup sl_bt_evt_periodic_advertiser_status sl_bt_evt_periodic_advertiser_status - * @{ - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * @brief This event indicates a status update in the periodic advertising. - */ - -/** @brief Identifier of the status event */ -#define sl_bt_evt_periodic_advertiser_status_id 0x005800a0 - -/***************************************************************************//** - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * @brief Data structure of the status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_advertiser_status_s -{ - uint8_t advertising_set; /**< The advertising set handle */ - uint32_t status; /**< Reserved for future */ -}); - -typedef struct sl_bt_evt_periodic_advertiser_status_s sl_bt_evt_periodic_advertiser_status_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_advertiser_status -/** @endcond */ // end restricted event - -/***************************************************************************//** - * - * Set the data for periodic advertising on an advertising set. Maximum 254 - * bytes of data can be set with this command. For setting longer advertising - * data, use command @ref sl_bt_periodic_advertiser_set_long_data. - * - * If the periodic advertising is currently enabled, the new advertising data - * will be used immediately. Periodic advertising can be enabled using the - * command @ref sl_bt_periodic_advertiser_start. - * - * The invalid parameter error will be returned if the data is too long to fit - * into the advertisement. - * - * @param[in] advertising_set Advertising set handle - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Set data for periodic advertising on an advertising set. Data currently in - * the system data buffer will be extracted as the advertising data. The buffer - * will be emptied after this command regardless of the completion status. - * - * Prior to calling this command, add data to the buffer with one or multiple - * calls to @ref sl_bt_system_data_buffer_write. - * - * Maximum 1650 bytes of data can be set for periodic advertising. Advertising - * parameters may limit the amount of data that can be sent. - * - * See @ref sl_bt_periodic_advertiser_set_data for more details. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set); - -/***************************************************************************//** - * - * Start periodic advertising on an advertising set. - * - * According to the Bluetooth Core specification, periodic advertising PDUs - * cannot be transmitted until at least one extended advertising event has been - * completed. If the application needs exact control over the extended - * advertising data and parameters, use the @ref sl_bt_advertiser class to - * configure the parameters of the advertising set and the @ref - * sl_bt_extended_advertiser class to set or generate the desired extended - * advertising data payload. If the application does not configure the - * parameters or set the data, the default parameters and empty advertising data - * are used for the extended advertising. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p - * flags, the stack will automatically start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. The application may stop the automatically started extended - * advertising using the @ref sl_bt_advertiser_stop command. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in - * @p flags, the stack will momentarily start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. Unless the application starts extended advertising before - * the first extended advertising event has completed, the stack will - * automatically stop the momentary extended advertising after the first - * extended advertising event. - * - * Periodic advertising PDUs are transmitted on the secondary PHY configured for - * the advertising set with the @ref sl_bt_extended_advertiser_set_phy command. - * - * Use @ref sl_bt_periodic_advertiser_stop command to stop the periodic - * advertising. - * - * @param[in] advertising_set Advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask - * of @ref sl_bt_periodic_advertiser_flags - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags); - -/***************************************************************************//** - * - * Stop the periodic advertising on an advertising set. Counterpart to @ref - * sl_bt_periodic_advertiser_start. - * - * This command does not affect the enable state of the legacy or extended - * advertising on the advertising set, i.e., the legacy or extended advertising - * is not stopped.. - * - * @param[in] advertising_set Advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_periodic_advertiser - -/** - * @addtogroup sl_bt_scanner Scanner - * @{ - * - * @brief Scanner - * - * This is the scanning feature that is brought in when the application includes - * a software component for the scanning functionality. The functionality - * differences are listed below for various component inclusion scenario: - * - The bluetooth_feature_scanner component is included but neither - * bluetooth_feature_legacy_scanner nor bluetooth_feature_extended_scanner - * is included: - * - The scanner can scan advertising devices that use legacy or extended - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_scan_report event is used to report the - * received advertisements. - * - * - The bluetooth_feature_legacy_scanner component is included but the - * bluetooth_feature_extended_scanner is not: - * - The scanner can only scan advertising devices that use legacy - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used - * to report the received advertisements. - * - * - The bluetooth_feature_extended_scanner component is included: - * - The scanner can scan advertising devices that use legacy or extended - * advertising PDUs. - * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used - * to report the received advertisements that use legacy advertising - * PDUs, and the @ref sl_bt_evt_scanner_extended_advertisement_report - * event is used to report the received advertisements that use extended - * advertising PDUs. - * - * - Either the bluetooth_feature_legacy_scanner or - * bluetooth_feature_extended_scanner component is included: - * - The @ref sl_bt_scanner_set_timing and @ref sl_bt_scanner_set_mode - * commands are not available to use. They are superseded by the @ref - * sl_bt_scanner_set_parameters command. - * - Calling a superseded command receives SL_STATUS_NOT_SUPPORTED error - * code. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_scanner_set_parameters_id 0x06050020 -#define sl_bt_cmd_scanner_set_parameters_and_filter_id 0x07050020 -#define sl_bt_cmd_scanner_stop_id 0x05050020 -#define sl_bt_cmd_scanner_set_timing_id 0x01050020 -#define sl_bt_cmd_scanner_set_mode_id 0x02050020 -#define sl_bt_cmd_scanner_start_id 0x03050020 -#define sl_bt_rsp_scanner_set_parameters_id 0x06050020 -#define sl_bt_rsp_scanner_set_parameters_and_filter_id 0x07050020 -#define sl_bt_rsp_scanner_stop_id 0x05050020 -#define sl_bt_rsp_scanner_set_timing_id 0x01050020 -#define sl_bt_rsp_scanner_set_mode_id 0x02050020 -#define sl_bt_rsp_scanner_start_id 0x03050020 - -/** - * @brief These values indicate which Bluetooth discovery mode to use when - * scanning for advertising devices. - */ -typedef enum -{ - sl_bt_scanner_discover_limited = 0x0, /**< (0x0) Discover only limited - discoverable devices. */ - sl_bt_scanner_discover_generic = 0x1, /**< (0x1) Discover limited and - general discoverable devices. */ - sl_bt_scanner_discover_observation = 0x2 /**< (0x2) Discover - non-discoverable, limited and - general discoverable devices. */ -} sl_bt_scanner_discover_mode_t; - -/** - * @brief The scanning modes. - */ -typedef enum -{ - sl_bt_scanner_scan_mode_passive = 0x0, /**< (0x0) Passive scanning mode where - the device only listens to - advertising packets and does not - transmit packets */ - sl_bt_scanner_scan_mode_active = 0x1 /**< (0x1) Active scanning mode where - the device sends out a scan - request packet upon receiving a - scannable advertising packet from - a remote device and listens to the - scan response packet from the - remote device */ -} sl_bt_scanner_scan_mode_t; - -/** - * @brief The enum defines the scanning PHYs. - */ -typedef enum -{ - sl_bt_scanner_scan_phy_1m = 0x1, /**< (0x1) Initiate the scanning on - the 1M PHY */ - sl_bt_scanner_scan_phy_coded = 0x4, /**< (0x4) Initiate the scanning on - the Coded PHY */ - sl_bt_scanner_scan_phy_1m_and_coded = 0x5 /**< (0x5) Simultaneous scanning by - initiating the scanning on the - 1M and Coded PHY alternatively */ -} sl_bt_scanner_scan_phy_t; - -/** - * @brief Defines the data completeness status types of an advertisement - * reported by the scanner. - */ -typedef enum -{ - sl_bt_scanner_data_status_complete = 0x0, /**< (0x0) All data of the - advertisement has been - reported. */ - sl_bt_scanner_data_status_incomplete_more = 0x1, /**< (0x1) Data of the - advertisement is - incomplete in this - event, and more data - will come in new - events. */ - sl_bt_scanner_data_status_incomplete_nomore = 0x2 /**< (0x2) Data of the - advertisement is - incomplete in this - event, but no more - data will come, i.e., - the data of the - advertisement is - truncated. */ -} sl_bt_scanner_data_status_t; - -/** - * @brief The scanning filter policy setting determines which advertisements and - * scan responses are delivered to the application when scanning. See the - * Bluetooth Core specification Volume 6, Part B, Section 4.3.3 "Scanning filter - * policy" for a detailed description of this setting. - * - * Note that some filter policies require the application to include additional - * Bluetooth feature components. Filter policies that use the Filter Accept List - * require that the application has included the bluetooth_feature_accept_list - * component. Filter policies that require the Bluetooth controller to resolve a - * Resolvable Private Address require that the application has included the - * bluetooth_feature_resolving_list component. - */ -typedef enum -{ - sl_bt_scanner_filter_policy_basic_unfiltered = 0x0, /**< (0x0) Advertising - and scan response - PDUs are processed - from all devices. - For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - a Resolvable - Private Address - that is resolved - to the local - device by the - Bluetooth - controller. */ - sl_bt_scanner_filter_policy_basic_filtered = 0x1, /**< (0x1) Advertising - and scan response - PDUs are processed - only from devices - that the - application has - added to the - Filter Accept - List. For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - a Resolvable - Private Address - that is resolved - to the local - device by the - Bluetooth - controller. */ - sl_bt_scanner_filter_policy_extended_unfiltered = 0x2, /**< (0x2) Advertising - and scan response - PDUs are processed - from all devices. - For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - any Resolvable - Private Address. */ - sl_bt_scanner_filter_policy_extended_filtered = 0x3 /**< (0x3) Advertising - and scan response - PDUs are processed - only from devices - that the - application has - added to the - Filter Accept - List. For directed - advertising, the - target address - must additionally - match the identity - address of the - local device or be - any Resolvable - Private Address. */ -} sl_bt_scanner_filter_policy_t; - -/** - * @addtogroup sl_bt_scanner_event_flag Event Type Flags of Advertisement Reports - * @{ - * - * Defines the event type flags of the advertisement packets the scanner - * reports. An advertisement packet could have multiple applicable flags. - */ - -/** A connectable advertising data packet */ -#define SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE 0x1 - -/** A scannable advertising data packet */ -#define SL_BT_SCANNER_EVENT_FLAG_SCANNABLE 0x2 - -/** Directed advertising */ -#define SL_BT_SCANNER_EVENT_FLAG_DIRECTED 0x4 - -/** A scan response packet that can be received in active scan mode only */ -#define SL_BT_SCANNER_EVENT_FLAG_SCAN_RESPONSE 0x8 - -/** @} */ // end Event Type Flags of Advertisement Reports - -/** - * @addtogroup sl_bt_evt_scanner_legacy_advertisement_report sl_bt_evt_scanner_legacy_advertisement_report - * @{ - * @brief Reports an advertising data or scan response packet from an - * advertising device that uses legacy advertising PDUs. - * - * This event is used to report advertisements only if the application includes - * the bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component - * - * Otherwise, the @ref sl_bt_evt_scanner_scan_report event is used for - * maintaining the backwards compatibility. - */ - -/** @brief Identifier of the legacy_advertisement_report event */ -#define sl_bt_evt_scanner_legacy_advertisement_report_id 0x000500a0 - -/***************************************************************************//** - * @brief Data structure of the legacy_advertisement_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_legacy_advertisement_report_s -{ - uint8_t event_flags; /**< The event type flag(s) in the - advertisement packet. Value: One or more - flags defined in @ref - sl_bt_scanner_event_flag */ - bd_addr address; /**< Advertiser address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the - local device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last - packet was received */ - bd_addr target_address; /**< The target address if the advertisement - is from directed advertising, otherwise - ignored */ - uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - The target address type if the - advertisement is from directed - advertising, otherwise ignored. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - the following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - enum @ref sl_bt_gap_address_type_t - values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8array data; /**< Advertising or scan response data. Ignore - if this is directed advertising. */ -}); - -typedef struct sl_bt_evt_scanner_legacy_advertisement_report_s sl_bt_evt_scanner_legacy_advertisement_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_legacy_advertisement_report - -/** - * @addtogroup sl_bt_evt_scanner_extended_advertisement_report sl_bt_evt_scanner_extended_advertisement_report - * @{ - * @brief Reports an advertising or scan response packet from an advertising - * device that uses extended advertising PDUs - * - * Multiple events may be reported for single advertisement train. - * - * This event is used to report advertisements only if the application includes - * the bluetooth_feature_extended_scanner component. Otherwise, the @ref - * sl_bt_evt_scanner_scan_report event is used for maintaining the backwards - * compatibility. - */ - -/** @brief Identifier of the extended_advertisement_report event */ -#define sl_bt_evt_scanner_extended_advertisement_report_id 0x020500a0 - -/***************************************************************************//** - * @brief Data structure of the extended_advertisement_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_extended_advertisement_report_s -{ - uint8_t event_flags; /**< The event type flag(s) in the - advertisement packet. Value: One or more - flags defined in @ref - sl_bt_scanner_event_flag */ - bd_addr address; /**< Advertiser address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the - local device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last - packet was received */ - bd_addr target_address; /**< The target address if this is directed - advertising, otherwise ignored */ - uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - The target address type if the - advertisement is from directed - advertising, otherwise ignored. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - the following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p target_address_type uses - enum @ref sl_bt_gap_address_type_t - values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_sid; /**< Advertising set identifier */ - uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on - which advertising packets are transmitted - on the primary advertising channel - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on - which advertising packets are transmitted - on the secondary advertising channel - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - int8_t tx_power; /**< TX power value in the received packet - header. Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - uint16_t periodic_interval; /**< The periodic advertising interval. Value - 0 indicates no periodic advertising. - Otherwise, - - Range: 0x06 to 0xFFFF - - Unit: 1.25 ms - - Time range: 7.5 ms to 81.92 s */ - uint8_t data_completeness; /**< Enum @ref sl_bt_scanner_data_status_t. - The data completeness status. Values: - - sl_bt_scanner_data_status_complete - (0x0): All data of the - advertisement has been reported. - - sl_bt_scanner_data_status_incomplete_more - (0x1): Data of the advertisement - is incomplete in this event, and more - data will come in new events. - - sl_bt_scanner_data_status_incomplete_nomore - (0x2): Data of the advertisement - is incomplete in this event, but no - more data will come, i.e., the data - of the advertisement is truncated. */ - uint8_t counter; /**< The monotonically increasing counter as - the sequence number of the event. This - counter is specific to @ref - sl_bt_evt_scanner_extended_advertisement_report_id. - It can be used to detect if one more @ref - sl_bt_evt_scanner_extended_advertisement_report - events were dropped due to temporarily - out of resources or other reasons. Ignore - this field if event loss is not a - concern. */ - uint8array data; /**< Advertising or scan response data */ -}); - -typedef struct sl_bt_evt_scanner_extended_advertisement_report_s sl_bt_evt_scanner_extended_advertisement_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_extended_advertisement_report - -/** - * @addtogroup sl_bt_evt_scanner_scan_report sl_bt_evt_scanner_scan_report - * @{ - * @brief Deprecated and replaced by new @ref - * sl_bt_evt_scanner_legacy_advertisement_report and @ref - * sl_bt_evt_scanner_extended_advertisement_report events - * - * To use these new events, the application needs to include the - * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component. - * - * Reports an advertising or scan response packet from an advertising device - * that uses legacy or extended advertising PDUs. - */ - -/** @brief Identifier of the scan_report event */ -#define sl_bt_evt_scanner_scan_report_id 0x010500a0 - -/***************************************************************************//** - * @brief Data structure of the scan_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_scanner_scan_report_s -{ - uint8_t packet_type; /**< Bits 0..2 : advertising packet type - - 000 : Connectable scannable - undirected advertising - - 001 : Connectable undirected - advertising - - 010 : Scannable undirected - advertising - - 011 : Non-connectable - non-scannable undirected advertising - - 100 : Scan Response. Note that - this is received only if the device is - in active scan mode. - - Bits 3..4 : Reserved for future - - Bits 5..6 : data completeness - - 00: Complete - - 01: Incomplete, more data to - come in new events - - 10: Incomplete, data truncated, - no more to come - - Bit 7 : legacy or extended - advertising - - 0: Legacy advertising PDUs used - - 1: Extended advertising PDUs - used */ - bd_addr address; /**< Bluetooth address of the remote device */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t bonding; /**< Bonding handle if the remote advertising - device has previously bonded with the local - device. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ - uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which - advertising packets are transmitted on the - primary advertising channel. Ignore this - field if the report is for a legacy - advertising PDU. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_coded (0x4): Coded - PHY, 125k (S=8) or 500k (S=2) */ - uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which - advertising packets are transmitted on the - secondary advertising channel. Ignore this - field if the report is for a legacy - advertising PDU. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded - PHY, 125k (S=8) or 500k (S=2) */ - uint8_t adv_sid; /**< Advertising set identifier */ - int8_t tx_power; /**< TX power value in the received packet - header. Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the - last received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t channel; /**< The channel number on which the last packet - was received */ - uint16_t periodic_interval; /**< The periodic advertising interval. Value 0 - indicates no periodic advertising. - Otherwise, - - Range: 0x06 to 0xFFFF - - Unit: 1.25 ms - - Time range: 7.5 ms to 81.92 s */ - uint8array data; /**< Advertising or scan response data */ -}); - -typedef struct sl_bt_evt_scanner_scan_report_s sl_bt_evt_scanner_scan_report_t; - -/** @} */ // end addtogroup sl_bt_evt_scanner_scan_report - -/***************************************************************************//** - * - * Set scan parameters for subsequent scanning operations. If the device is - * currently scanning, new parameters will take effect when scanning is - * restarted. - * - * This command sets the scanning filter policy to the default value @ref - * sl_bt_scanner_filter_policy_basic_unfiltered. Use the command @ref - * sl_bt_scanner_set_parameters_and_filter to set a specific scanning filter - * policy. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * Passive or active scan. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * @param[in] interval @parblock - * The time interval when the device starts its last scan until it begins the - * subsequent scan. In other words, how often to scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] window @parblock - * The scan window, i.e., the duration of the scan, which must be less than or - * equal to the @p interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * Note that the packet reception is aborted if it's started just before the - * scan window ends. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, - uint16_t interval, - uint16_t window); - -/***************************************************************************//** - * - * Set scan parameters and the scanning filter policy for subsequent scanning - * operations. If the device is currently scanning, new parameters will take - * effect when scanning is restarted. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * Passive or active scan. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * @param[in] interval @parblock - * The time interval when the device starts its last scan until it begins the - * subsequent scan. In other words, how often to scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] window @parblock - * The scan window, i.e., the duration of the scan, which must be less than or - * equal to the @p interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * Note that the packet reception is aborted if it's started just before the - * scan window ends. - * @endparblock - * @param[in] flags No flags are currently defined. Set this parameter to 0. - * @param[in] filter_policy @parblock - * Enum @ref sl_bt_scanner_filter_policy_t. - * - * The scanning filter policy to use when scanning is started. The filter - * policy determines which advertisements and scan responses are delivered to - * the application. Values: - * - sl_bt_scanner_filter_policy_basic_unfiltered (0x0): Advertising - * and scan response PDUs are processed from all devices. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be a Resolvable Private Address that is - * resolved to the local device by the Bluetooth controller. - * - sl_bt_scanner_filter_policy_basic_filtered (0x1): Advertising - * and scan response PDUs are processed only from devices that the - * application has added to the Filter Accept List. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be a Resolvable Private Address that is - * resolved to the local device by the Bluetooth controller. - * - sl_bt_scanner_filter_policy_extended_unfiltered (0x2): - * Advertising and scan response PDUs are processed from all devices. For - * directed advertising, the target address must additionally match the - * identity address of the local device or be any Resolvable Private - * Address. - * - sl_bt_scanner_filter_policy_extended_filtered (0x3): Advertising - * and scan response PDUs are processed only from devices that the - * application has added to the Filter Accept List. For directed - * advertising, the target address must additionally match the identity - * address of the local device or be any Resolvable Private Address. - * - * Default value: @ref sl_bt_scanner_filter_policy_basic_unfiltered - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, - uint16_t interval, - uint16_t window, - uint32_t flags, - uint8_t filter_policy); - -/***************************************************************************//** - * - * Stop scanning for advertising devices. For more information about the - * discovery, see the @ref sl_bt_scanner_start command. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_stop(); - -/***************************************************************************//** - * - * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters - * command. - * - * Set the scanning timing parameters on the specified PHY(s). If the device is - * currently scanning, new parameters will take effect when scanning is - * restarted. - * - * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the - * setting is set for. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs - * @param[in] scan_interval @parblock - * Scan interval is defined as the time interval when the device starts its - * last scan until it begins the subsequent scan. In other words, how often to - * scan - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms - * - * A variable delay occurs when switching channels at the end of each scanning - * interval, which is included in the scanning interval time. During the - * switch time, advertising packets are not received by the device. The switch - * time variation is use case-dependent. For example, if scanning while - * keeping active connections, the channel switch time might be longer than - * when scanning without any active connections. Increasing the scanning - * interval reduces the amount of time in which the device can't receive - * advertising packets because it switches channels less often. - * - * After every scan interval, the scanner changes the frequency at which it - * operates. It cycles through all three advertising channels in a round robin - * fashion. According to the specification, all three channels must be used by - * a scanner. - * @endparblock - * @param[in] scan_window @parblock - * Scan window defines the duration of the scan which must be less than or - * equal to the @p scan_interval - * - Time = Value x 0.625 ms - * - Range: 0x0004 to 0xFFFF - * - Time Range: 2.5 ms to 40.96 s - * - * Default value: 10 ms Note that the packet reception is aborted if it's - * started just before the scan window ends. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, - uint16_t scan_interval, - uint16_t scan_window); - -/***************************************************************************//** - * - * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters - * command. - * - * Set the scan mode on the specified PHY(s). If the device is currently - * scanning, new parameters will take effect when scanning is restarted. - * - * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the - * setting is set for. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs - * @param[in] scan_mode @parblock - * Enum @ref sl_bt_scanner_scan_mode_t. - * - * The scan mode. Values: - * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode - * where the device only listens to advertising packets and does not - * transmit packets - * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where - * the device sends out a scan request packet upon receiving a scannable - * advertising packet from a remote device and listens to the scan - * response packet from the remote device - * - * Default value: @ref sl_bt_scanner_scan_mode_passive. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode); - -/***************************************************************************//** - * - * Start the GAP discovery procedure to scan for advertising devices that use - * legacy or extended advertising PDUs. To cancel an ongoing discovery - * procedure, use the @ref sl_bt_scanner_stop command. - * - * The invalid parameter error will be returned if the value of scanning PHYs is - * invalid or the device does not support a PHY. - * - * Received advertising packets are not filtered in any way, so multiple events - * will be received for every advertising device in range. - * - * @param[in] scanning_phy @parblock - * Enum @ref sl_bt_scanner_scan_phy_t. - * - * The scanning PHY(s). - * - * In simultaneous scanning, the stack alternates the scanning on two PHYs by - * switching the PHY at every scan interval. When a timing parameter is set - * differently on 1M and Coded PHY, the stack chooses the most relaxed value - * for both PHYs during simultaneous scanning, i.e., the largest scan interval - * or the smallest scan window. If one PHY is set to passive scanning and the - * other to active scanning, passive scanning is chosen for simultaneous - * scanning. Values: - * - sl_bt_scanner_scan_phy_1m (0x1): Initiate the scanning on the 1M - * PHY - * - sl_bt_scanner_scan_phy_coded (0x4): Initiate the scanning on the - * Coded PHY - * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): Simultaneous scanning - * by initiating the scanning on the 1M and Coded PHY alternatively - * @endparblock - * @param[in] discover_mode Enum @ref sl_bt_scanner_discover_mode_t. Bluetooth - * discovery Mode. Values: - * - sl_bt_scanner_discover_limited (0x0): Discover only limited - * discoverable devices. - * - sl_bt_scanner_discover_generic (0x1): Discover limited and - * general discoverable devices. - * - sl_bt_scanner_discover_observation (0x2): Discover - * non-discoverable, limited and general discoverable devices. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_scanner_scan_report - This event is triggered for - * reporting a received advertisement if the application includes the - * bluetooth_feature_scanner component but does not include any other - * scanner component. - * - @ref sl_bt_evt_scanner_legacy_advertisement_report - This event is - * triggered for reporting a received advertisement that uses legacy - * advertising PDUs if the application includes the - * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner - * component. - * - @ref sl_bt_evt_scanner_extended_advertisement_report - This event is - * triggered for reporting a received advertisement that uses extended - * advertising PDUs if the application includes the - * bluetooth_feature_extended_scanner component. - * - ******************************************************************************/ -sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode); - -/** @} */ // end addtogroup sl_bt_scanner - -/** - * @addtogroup sl_bt_sync Synchronization - * @{ - * - * @brief Synchronization - * - * Provides the base functionality of periodic advertising synchronization. Use - * bluetooth_feature_sync_scanner and/or bluetooth_feature_past_receiver - * components to include the synchronization mechanisms that the application - * requires. Use bluetooth_feature_periodic_sync to include support for trains - * that do not have subevents or response slots, and/or - * bluetooth_feature_pawr_sync to include support for Periodic Advertising with - * Responses (PAwR) trains. - * - * Some functionality in this class is considered deprecated and has been - * superseded by new classes. When one or more of - * bluetooth_feature_sync_scanner, bluetooth_feature_periodic_sync, or - * bluetooth_feature_pawr_sync components is included by the application, - * commands that have been superseded by the new classes are no longer available - * for use in the @ref sl_bt_sync class. Calling them will receive - * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: - * - @ref sl_bt_sync_set_parameters - * - @ref sl_bt_sync_open - * - * See the command descriptions for the replacements. - * - * Events that are deprecated and superseded by the new classes are no longer - * triggered by the @ref sl_bt_sync class if any of the new classes are included - * in the application. See event descriptions for the replacements. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_set_parameters_id 0x02420020 -#define sl_bt_cmd_sync_open_id 0x00420020 -#define sl_bt_cmd_sync_set_reporting_mode_id 0x03420020 -#define sl_bt_cmd_sync_update_sync_parameters_id 0x04420020 -#define sl_bt_cmd_sync_close_id 0x01420020 -#define sl_bt_rsp_sync_set_parameters_id 0x02420020 -#define sl_bt_rsp_sync_open_id 0x00420020 -#define sl_bt_rsp_sync_set_reporting_mode_id 0x03420020 -#define sl_bt_rsp_sync_update_sync_parameters_id 0x04420020 -#define sl_bt_rsp_sync_close_id 0x01420020 - -/** - * @brief Specifies the mode for periodic advertising reports. - */ -typedef enum -{ - sl_bt_sync_report_none = 0x0, /**< (0x0) Data received in periodic advertising - trains is not reported to the application. */ - sl_bt_sync_report_all = 0x1 /**< (0x1) Data received in periodic advertising - trains is reported to the application. */ -} sl_bt_sync_reporting_mode_t; - -/** - * @brief These values indicate the advertiser clock accuracy in a periodic - * advertising synchronization. - */ -typedef enum -{ - sl_bt_sync_clock_accuracy_500 = 0x1f4, /**< (0x1f4) Clock accuracy 500 ppm */ - sl_bt_sync_clock_accuracy_250 = 0xfa, /**< (0xfa) Clock accuracy 250 ppm */ - sl_bt_sync_clock_accuracy_150 = 0x96, /**< (0x96) Clock accuracy 150 ppm */ - sl_bt_sync_clock_accuracy_100 = 0x64, /**< (0x64) Clock accuracy 100 ppm */ - sl_bt_sync_clock_accuracy_75 = 0x4b, /**< (0x4b) Clock accuracy 75 ppm */ - sl_bt_sync_clock_accuracy_50 = 0x32, /**< (0x32) Clock accuracy 50 ppm */ - sl_bt_sync_clock_accuracy_30 = 0x1e, /**< (0x1e) Clock accuracy 30 ppm */ - sl_bt_sync_clock_accuracy_20 = 0x14 /**< (0x14) Clock accuracy 20 ppm */ -} sl_bt_sync_advertiser_clock_accuracy_t; - -/** - * @addtogroup sl_bt_evt_sync_opened sl_bt_evt_sync_opened - * @{ - * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_opened - * for periodic advertising trains that do not have subevents or response slots, - * and with @ref sl_bt_evt_pawr_sync_opened for Periodic Advertising with - * Responses (PAwR) trains. - * - * Indicates that a periodic advertising synchronization has been opened. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_sync_opened_id 0x004200a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_opened_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_sync_opened_s sl_bt_evt_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_opened - -/** - * @addtogroup sl_bt_evt_sync_transfer_received sl_bt_evt_sync_transfer_received - * @{ - * @brief Deprecated and replaced by @ref - * sl_bt_evt_periodic_sync_transfer_received for periodic advertising trains - * that do not have subevents or response slots responses, and with @ref - * sl_bt_evt_pawr_sync_transfer_received for Periodic Advertising with Responses - * (PAwR) trains. - * - * Indicates that synchronization information for a periodic advertising train - * has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_sync_transfer_received_id 0x034200a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was established. - Other values indicate that the sync failed to - get established. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_sync_transfer_received_s sl_bt_evt_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_sync_data sl_bt_evt_sync_data - * @{ - * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_report. - * - * Reports a received periodic advertisement packet. - */ - -/** @brief Identifier of the data event */ -#define sl_bt_evt_sync_data_id 0x024200a0 - -/***************************************************************************//** - * @brief Data structure of the data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_data_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the latest - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no more - to come */ - uint8array data; /**< Periodic advertising data */ -}); - -typedef struct sl_bt_evt_sync_data_s sl_bt_evt_sync_data_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_data - -/** - * @addtogroup sl_bt_evt_sync_closed sl_bt_evt_sync_closed - * @{ - * @brief Indicates that periodic advertising synchronization was lost or a - * synchronization establishment procedure was canceled - * - * The synchronization establishment procedure can be canceled explicitly by the - * application by issuing command @ref sl_bt_sync_close, or internally due to - * synchronization failing. Synchronization can fail for example due to - * incompatible sync CTE type. - */ - -/** @brief Identifier of the closed event */ -#define sl_bt_evt_sync_closed_id 0x014200a0 - -/***************************************************************************//** - * @brief Data structure of the closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sync_closed_s -{ - uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ -}); - -typedef struct sl_bt_evt_sync_closed_s sl_bt_evt_sync_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_sync_closed - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_sync_scanner_set_sync_parameters. - * - * Configure periodic advertiser synchronization parameters. The specified - * parameters take effect immediately for all advertisers that have not already - * established synchronization. - * - * The application should determine skip and timeout values based on the - * periodic advertising interval provided by the advertiser. Ensure that you use - * a long enough timeout to allow multiple receives. If @p skip and @p timeout - * are used, select appropriate values so that they allow a few receiving - * attempts. Periodic advertising intervals are reported in event @ref - * sl_bt_evt_scanner_scan_report. - * - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] flags No flags defined currently - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, - uint16_t timeout, - uint32_t flags); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_sync_scanner_open. - * - * Start establishing synchronization with the specified periodic advertiser in - * parallel with other advertisers given in previous invocations of this - * command. The stack will internally enable scanning when needed so that - * synchronizations can occur. The scanning responses from the internal scanning - * are not passed to the application unless the application has also enabled - * scanning. - * - * Advertisers that have not already synced before the invocation of this - * command will be synced using the @p skip and @p timeout values configured in - * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. - * - * @param[in] address Address of the advertiser - * @param[in] address_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Advertiser address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * @param[in] adv_sid Advertising set identifier - * @param[out] sync A handle that will be assigned to the periodic advertising - * synchronization after the synchronization is established. This handle is - * valid only if the result code of this response is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_opened - Triggered after the synchronization is - * established. - * - @ref sl_bt_evt_sync_data - Indicates that a periodic advertisement packet - * is received. - * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising - * synchronization was lost or explicitly closed, or a synchronization - * establishment procedure was canceled. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync); - -/***************************************************************************//** - * - * Set data reporting mode of the periodic advertising synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] reporting_mode Enum @ref sl_bt_sync_reporting_mode_t. Specifies - * the mode for reporting data received in the periodic advertising train. - * Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Update synchronization parameters for a periodic sync that was already - * established. - * - * When a sync is established by scanning (see @ref sl_bt_sync_scanner) or by - * receiving Periodic Advertising Synchronization Transfer (see @ref - * sl_bt_past_receiver), the sync gets the @p skip and @p timeout parameters - * that were configured in the corresponding class. The application can use this - * command @ref sl_bt_sync_update_sync_parameters to update the values of a sync - * that has been established. The application can for example update the values - * to better match the actual interval of the periodic advertising train, or to - * increase the @p skip value to minimize wakeups when power saving is - * prioritized over receiving every periodic advertisement. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, - uint16_t skip, - uint16_t timeout); - -/***************************************************************************//** - * - * Close a periodic advertising synchronization or cancel an ongoing attempt of - * establishing a synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_closed - Triggered after a periodic advertising - * synchronization has been closed or canceled. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_close(uint16_t sync); - -/** @} */ // end addtogroup sl_bt_sync - -/** - * @addtogroup sl_bt_sync_scanner Periodic Advertising Sync Scanner - * @{ - * - * @brief Periodic Advertising Sync Scanner - * - * Synchronize to periodic advertising trains by scanning for extended - * advertisements that provide the synchronization information. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_scanner_set_sync_parameters_id 0x00500020 -#define sl_bt_cmd_sync_scanner_open_id 0x01500020 -#define sl_bt_rsp_sync_scanner_set_sync_parameters_id 0x00500020 -#define sl_bt_rsp_sync_scanner_open_id 0x01500020 - -/***************************************************************************//** - * - * Configure synchronization parameters for synchronizing to periodic - * advertising trains. The specified parameters take effect immediately for all - * periodic advertising trains that have not already established - * synchronization. - * - * The application should determine skip and timeout values based on the - * periodic advertising interval provided by the advertiser. Ensure that you use - * a long enough timeout to allow multiple receives. If @p skip and @p timeout - * are used, select appropriate values so that they allow a few receiving - * attempts. Periodic advertising intervals are reported in @ref - * sl_bt_evt_scanner_scan_report or @ref - * sl_bt_evt_scanner_extended_advertisement_report event. - * - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Start establishing synchronization with the specified periodic advertiser in - * parallel with other advertisers given in previous invocations of this - * command. - * - * If the application has not already started scanning with the @ref - * sl_bt_scanner_start command, the stack will internally enable scanning so - * that synchronizations can occur. The internal scanning uses the PHY that was - * most recently used with @ref sl_bt_scanner_start and the parameters that have - * been configured with @ref sl_bt_scanner_set_timing. The internal scanning is - * automatically stopped when all requested synchronizations have occurred. - * - * The scanning responses from the internal scanning are not passed to the - * application unless the application starts scanning with the @ref - * sl_bt_scanner_start command. If the application starts scanning while - * synchronizations are being established, the scanning PHY and settings set by - * the application take effect immediately and scanning for synchronizations - * continues with the new settings. When the application has started scanning - * with the @ref sl_bt_scanner_start command, scanning continues until the - * application stops scanning with the @ref sl_bt_scanner_stop command. - * - * Advertisers that have not already synced before the invocation of this - * command will be synced using the @p skip and @p timeout values configured in - * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. - * - * @param[in] address Address of the advertiser - * @param[in] address_type @parblock - * Enum @ref sl_bt_gap_address_type_t. - * - * Advertiser address type. - * - * If the application does not include the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses the following values: - * - 0: Public address - * - 1: Random address - * - * If the application includes the - * bluetooth_feature_use_accurate_api_address_types component, @p address_type - * uses enum @ref sl_bt_gap_address_type_t values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @endparblock - * @param[in] adv_sid Advertising set identifier - * @param[out] sync A handle that will be assigned to the periodic advertising - * synchronization after the synchronization is established. This handle is - * valid only if the result code of this response is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_periodic_sync_opened - Triggered after synchronization is - * established to a periodic advertising train that does not have subevents - * or response slots. - * - @ref sl_bt_evt_pawr_sync_opened - Triggered after synchronization is - * established to a Periodic Advertising with Responses (PAwR) train. - * - @ref sl_bt_evt_periodic_sync_report - Triggered when data for periodic - * advertising train that does not have subevents or response slots is - * received and accepted by the reporting mode currently set to the train. - * - @ref sl_bt_evt_pawr_sync_subevent_report - Triggered when subevent data - * for Periodic Advertising with Responses (PAwR) train is received and - * accepted by the reporting mode currently set to the train. - * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising - * synchronization was lost or explicitly closed, or a synchronization - * establishment procedure was canceled. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_scanner_open(bd_addr address, - uint8_t address_type, - uint8_t adv_sid, - uint16_t *sync); - -/** @} */ // end addtogroup sl_bt_sync_scanner - -/** - * @addtogroup sl_bt_past_receiver PAST Receiver - * @{ - * - * @brief PAST Receiver - * - * Synchronize to periodic advertising trains by receiving Periodic Advertising - * Synchronization Transfer over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id 0x00510020 -#define sl_bt_cmd_past_receiver_set_sync_receive_parameters_id 0x01510020 -#define sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_id 0x00510020 -#define sl_bt_rsp_past_receiver_set_sync_receive_parameters_id 0x01510020 - -/** - * @brief Specifies the mode for receiving synchronization transfers - */ -typedef enum -{ - sl_bt_past_receiver_mode_ignore = 0x0, /**< (0x0) No attempt is made to - synchronize to a periodic - advertising train for which - the synchronization - information was received. No - event will be triggered - towards the application. */ - sl_bt_past_receiver_mode_synchronize = 0x1 /**< (0x1) Attempt to synchronize - to a periodic advertising - train for which the - synchronization information - was received. When the - information is received, an - event will be triggered to - indicate success or failure - and to provide the - application with the periodic - advertising synchronization - handle. */ -} sl_bt_past_receiver_mode_t; - -/***************************************************************************//** - * - * Set the default parameters for receiving Periodic Advertising Synchronization - * Transfers (PAST) over connections. The default parameters will be in effect - * for all subsequent connections, unless overridden by command @ref - * sl_bt_past_receiver_set_sync_receive_parameters after the connection is - * opened. - * - * This command sets parameters that do not limit the synchronization based on - * the CTE type. If the application includes bluetooth_feature_aoa_receiver or - * bluetooth_feature_aod_receiver component and wants to specify a particular - * CTE limitation, the application should use the command @ref - * sl_bt_cte_receiver_set_default_sync_receive_parameters to set the default - * parameters. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Set the parameters for receiving Periodic Advertising Synchronization - * Transfers (PAST) over the specified connection. The parameters do not affect - * periodic advertising trains that the device has already synchronized to. - * - * This command sets parameters that do not limit the synchronization based on - * the CTE type. If the application includes bluetooth_feature_aoa_receiver or - * bluetooth_feature_aod_receiver component and wants to specify a particular - * CTE limitation, the application should use the command @ref - * sl_bt_cte_receiver_set_sync_receive_parameters to set the parameters. - * - * @param[in] connection Connection handle of the connection used to receive the - * sync transfer - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t reporting_mode); - -/** @} */ // end addtogroup sl_bt_past_receiver - -/** - * @addtogroup sl_bt_advertiser_past Advertiser PAST - * @{ - * - * @brief Advertiser PAST - * - * Transfer the synchronization information of a local active periodic - * advertising set to a remote device using Periodic Advertising Synchronization - * Transfer (PAST) over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_advertiser_past_transfer_id 0x00520020 -#define sl_bt_rsp_advertiser_past_transfer_id 0x00520020 - -/***************************************************************************//** - * - * Transfer the synchronization information of an advertising set that is - * actively performing periodic advertising. - * - * @param[in] connection Connection handle of the connection used to transmit - * the sync transfer - * @param[in] service_data A value provided by the application for use by the - * peer device. - * @param[in] advertising_set Handle of the periodic advertising set to transfer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, - uint16_t service_data, - uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_advertiser_past - -/** - * @addtogroup sl_bt_sync_past Sync PAST - * @{ - * - * @brief Sync PAST - * - * Transfer the synchronization information of a synchronized periodic - * advertising train to a remote device using Periodic Advertising - * Synchronization Transfer (PAST) over a connection. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sync_past_transfer_id 0x005b0020 -#define sl_bt_rsp_sync_past_transfer_id 0x005b0020 - -/***************************************************************************//** - * - * Transfer the synchronization information of a periodic advertising train for - * which a sync has been established. - * - * @param[in] connection Connection handle of the connection used to transmit - * the sync transfer - * @param[in] service_data A value provided by the application for use by the - * peer device. - * @param[in] sync Handle of the periodic advertising synchronization to - * transfer - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sync_past_transfer(uint8_t connection, - uint16_t service_data, - uint16_t sync); - -/** @} */ // end addtogroup sl_bt_sync_past - -/** - * @addtogroup sl_bt_periodic_sync Periodic Advertising without responses Synchronization - * @{ - * - * @brief Periodic Advertising without responses Synchronization - * - * Provides events and control for synchronized periodic advertising trains that - * do not have subevents or response slots. Synchronization is achieved by - * scanning (see @ref sl_bt_sync_scanner) or by receiving Periodic Advertising - * Synchronization Transfer (see @ref sl_bt_past_receiver). - */ - -/* Command and Response IDs */ - -/** - * @addtogroup sl_bt_evt_periodic_sync_opened sl_bt_evt_periodic_sync_opened - * @{ - * @brief Indicates that synchronization to a periodic advertising train that - * does not have subevents or response slots has been opened by scanning - * - * See command @ref sl_bt_sync_scanner_open. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_periodic_sync_opened_id 0x005300a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_opened_s -{ - uint16_t sync; /**< Periodic Advertising synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The Periodic Advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_periodic_sync_opened_s sl_bt_evt_periodic_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_opened - -/** - * @addtogroup sl_bt_evt_periodic_sync_transfer_received sl_bt_evt_periodic_sync_transfer_received - * @{ - * @brief Indicates that synchronization information for a periodic advertising - * train that does not have subevents or response slots has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_periodic_sync_transfer_received_id 0x015300a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was established. - Other values indicate that the sync failed to - get established. */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. - Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): Coded PHY, - 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value in - units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. The - advertiser clock accuracy. */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_periodic_sync_transfer_received_s sl_bt_evt_periodic_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_periodic_sync_report sl_bt_evt_periodic_sync_report - * @{ - * @brief Reports a periodic advertising packet for periodic advertising train - * that does not have subevents or response slots - */ - -/** @brief Identifier of the report event */ -#define sl_bt_evt_periodic_sync_report_id 0x025300a0 - -/***************************************************************************//** - * @brief Data structure of the report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_periodic_sync_report_s -{ - uint16_t sync; /**< Periodic advertising synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) in the latest - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no more - to come */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_periodic_sync_report event as a - monotonically increasing counter that wraps from - 255 to 0. There is a single counter for this - event type that starts from value 0 when the - Bluetooth stack is started and is never reset - while the stack is running. This counter can be - used to detect if one or more @ref - sl_bt_evt_periodic_sync_report events have been - created by the stack but dropped due to problems - such as temporarily running out of resources - before the event reached the application. */ - uint8array data; /**< Periodic advertising data */ -}); - -typedef struct sl_bt_evt_periodic_sync_report_s sl_bt_evt_periodic_sync_report_t; - -/** @} */ // end addtogroup sl_bt_evt_periodic_sync_report - -/** @} */ // end addtogroup sl_bt_periodic_sync - -/** - * @addtogroup sl_bt_pawr_sync Periodic Advertising with responses Synchronization - * @{ - * - * @brief Periodic Advertising with responses Synchronization - * - * Provides events and control for synchronized Periodic Advertising with - * Responses (PAwR) trains. Synchronization is achieved by scanning (see @ref - * sl_bt_sync_scanner) or by receiving Periodic Advertising Synchronization - * Transfer (see @ref sl_bt_past_receiver). - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_pawr_sync_set_sync_subevents_id 0x02540020 -#define sl_bt_cmd_pawr_sync_set_response_data_id 0x03540020 -#define sl_bt_rsp_pawr_sync_set_sync_subevents_id 0x02540020 -#define sl_bt_rsp_pawr_sync_set_response_data_id 0x03540020 - -/** - * @addtogroup sl_bt_evt_pawr_sync_opened sl_bt_evt_pawr_sync_opened - * @{ - * @brief Indicates that synchronization to a Periodic Advertising with - * Responses (PAwR) train has been opened by scanning - * - * See command @ref sl_bt_sync_scanner_open. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_pawr_sync_opened_id 0x005400a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_opened_s -{ - uint16_t sync; /**< PAwR synchronization handle */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser - PHY. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value - in units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. - The advertiser clock accuracy. */ - uint8_t num_subevents; /**< The number of subevents. - - Range: 0x01 to 0x80 */ - uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 - ms. - - Range: 0x06 to 0xFF - - Time range: 7.5 ms to 318.75 ms */ - uint8_t response_slot_delay; /**< Time between the advertising packet in a - subevent and the first response slot. - Value in units of 1.25 ms. - - Range: 0x01 to 0xFE - - Time range: 1.25 ms to 317.5 ms */ - uint8_t response_slot_spacing; /**< Time between response slots. Value in - units of 0.125 ms. - - Range: 0x02 to 0xFF - - Time range: 0.25 ms to 31.875 ms */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_pawr_sync_opened_s sl_bt_evt_pawr_sync_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_opened - -/** - * @addtogroup sl_bt_evt_pawr_sync_transfer_received sl_bt_evt_pawr_sync_transfer_received - * @{ - * @brief Indicates that synchronization information for Periodic Advertising - * with Responses (PAwR) train has been received - * - * See @ref sl_bt_past_receiver. - */ - -/** @brief Identifier of the transfer_received event */ -#define sl_bt_evt_pawr_sync_transfer_received_id 0x015400a0 - -/***************************************************************************//** - * @brief Data structure of the transfer_received event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_transfer_received_s -{ - uint16_t status; /**< SL_STATUS_OK if synchronization was - established. Other values indicate that - the sync failed to get established. */ - uint16_t sync; /**< PAwR synchronization handle */ - uint16_t service_data; /**< A value provided by the peer device. */ - uint8_t connection; /**< Connection handle of the connection that - transferred the sync info */ - uint8_t adv_sid; /**< Advertising set identifier */ - bd_addr address; /**< Address of the advertiser */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the - following values: - - 0: Public address - - 1: Random address - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address - (0x0): Public device address - - sl_bt_gap_static_address - (0x1): Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private - random address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser - PHY. Values: - - sl_bt_gap_phy_1m (0x1): 1M PHY - - sl_bt_gap_phy_2m (0x2): 2M PHY - - sl_bt_gap_phy_coded (0x4): - Coded PHY, 125k (S=8) or 500k (S=2) */ - uint16_t adv_interval; /**< The periodic advertising interval. Value - in units of 1.25 ms - - Range: 0x06 to 0xFFFF - - Time range: 7.5 ms to 81.92 s */ - uint16_t clock_accuracy; /**< Enum @ref - sl_bt_sync_advertiser_clock_accuracy_t. - The advertiser clock accuracy. */ - uint8_t num_subevents; /**< The number of subevents. - - Range: 0x01 to 0x80 */ - uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 - ms. - - Range: 0x06 to 0xFF - - Time range: 7.5 ms to 318.75 ms */ - uint8_t response_slot_delay; /**< Time between the advertising packet in a - subevent and the first response slot. - Value in units of 1.25 ms. - - Range: 0x01 to 0xFE - - Time range: 1.25 ms to 317.5 ms */ - uint8_t response_slot_spacing; /**< Time between response slots. Value in - units of 0.125 ms. - - Range: 0x02 to 0xFF - - Time range: 0.25 ms to 31.875 ms */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE - (0xff): No bonding - - Other: Bonding handle */ -}); - -typedef struct sl_bt_evt_pawr_sync_transfer_received_s sl_bt_evt_pawr_sync_transfer_received_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_transfer_received - -/** - * @addtogroup sl_bt_evt_pawr_sync_subevent_report sl_bt_evt_pawr_sync_subevent_report - * @{ - * @brief Reports that the device's radio has received a periodic advertisement - * in a subevent of an active PAwR train - * - * This event reports also empty advertisements, i.e., advertisements that - * contained no payload data. In this case the @p data parameter has zero - * length. - */ - -/** @brief Identifier of the subevent_report event */ -#define sl_bt_evt_pawr_sync_subevent_report_id 0x025400a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_sync_subevent_report_s -{ - uint16_t sync; /**< PAwR synchronization handle */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) of the - received packet. Units: dBm - - Range: -127 to +20 */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint16_t event_counter; /**< The value of the periodic advertising event - counter (paEventCounter) of the event in which - the advertisement was received. If the - application responds to this advertisement, use - this field as the value of @p request_event - parameter for the @ref - sl_bt_pawr_sync_set_response_data command. */ - uint8_t subevent; /**< The subevent in which the advertisement was - received. If the application responds to this - advertisement, use this field as the value of - @p request_subevent parameter for the @ref - sl_bt_pawr_sync_set_response_data command. */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come in - new events - - 2: Incomplete, data truncated, no - more to come - - 255: Failed to receive subevent data - in this subevent */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_pawr_sync_subevent_report event as a - monotonically increasing counter that wraps - from 255 to 0. There is a single counter for - this event type that starts from value 0 when - the Bluetooth stack is started and is never - reset while the stack is running. This counter - can be used to detect if one or more @ref - sl_bt_evt_pawr_sync_subevent_report events have - been created by the stack but dropped due to - problems such as temporarily running out of - resources before the event reached the - application. */ - uint8array data; /**< The advertisement data that was received */ -}); - -typedef struct sl_bt_evt_pawr_sync_subevent_report_s sl_bt_evt_pawr_sync_subevent_report_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_sync_subevent_report - -/***************************************************************************//** - * - * Specify the subevents that this device will synchronize to on the specified - * PAwR train. - * - * @param[in] sync PAwR synchronization handle - * @param[in] subevents_len Length of data in @p subevents - * @param[in] subevents Array of subevent indexes to synchronize to - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, - size_t subevents_len, - const uint8_t* subevents); - -/***************************************************************************//** - * - * Set the data to be sent in the specified response slot of a subevent of an - * active PAwR train. - * - * Use this command when the application receives the @ref - * sl_bt_evt_pawr_sync_subevent_report event and the application needs to send a - * response. The application needs to set the response data within the timing - * requirements implied by the parameters of the PAwR train that the device is - * synchronized to. If the response data is set too late, this command will fail - * with result SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT. - * - * @param[in] sync PAwR synchronization handle - * @param[in] request_event The periodic advertising event counter - * (paEventCounter) of the request. Set this parameter to the value of the @p - * event_counter field of the @ref sl_bt_evt_pawr_sync_subevent_report_id - * event that the application is responding to. - * @param[in] request_subevent The subevent of the request. Set this parameter - * to the value of the @p subevent field of the @ref - * sl_bt_evt_pawr_sync_subevent_report_id event that the application is - * responding to. - * @param[in] response_subevent The subevent in which the response is to be sent - * @param[in] response_slot The response slot in which the response is to be - * sent - * @param[in] response_data_len Length of data in @p response_data - * @param[in] response_data Data to be sent in the specified response slot. - * Maximum of 248 bytes of data can be set with this command. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, - uint16_t request_event, - uint8_t request_subevent, - uint8_t response_subevent, - uint8_t response_slot, - size_t response_data_len, - const uint8_t* response_data); - -/** @} */ // end addtogroup sl_bt_pawr_sync - -/** - * @addtogroup sl_bt_pawr_advertiser PAwR Advertiser - * @{ - * - * @brief PAwR Advertiser - * - * Provides support for advertising with Periodic Advertising with Responses - * (PAwR) trains. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_pawr_advertiser_start_id 0x00550020 -#define sl_bt_cmd_pawr_advertiser_set_subevent_data_id 0x01550020 -#define sl_bt_cmd_pawr_advertiser_create_connection_id 0x02550020 -#define sl_bt_cmd_pawr_advertiser_stop_id 0x03550020 -#define sl_bt_rsp_pawr_advertiser_start_id 0x00550020 -#define sl_bt_rsp_pawr_advertiser_set_subevent_data_id 0x01550020 -#define sl_bt_rsp_pawr_advertiser_create_connection_id 0x02550020 -#define sl_bt_rsp_pawr_advertiser_stop_id 0x03550020 - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request sl_bt_evt_pawr_advertiser_subevent_data_request - * @{ - * @brief This event is triggered to indicate that the Bluetooth stack is ready - * to accept data for the specified subevents of the PAwR train. - * - * To ensure effective use of the available memory, applications are encouraged - * to observe these events and set data using @ref - * sl_bt_pawr_advertiser_set_subevent_data for the subevents that are being - * requested and for which the application has data to send - * - * If the application has no data to send, it does not need to call @ref - * sl_bt_pawr_advertiser_set_subevent_data for that subevent. The application - * can attempt to set data for that subevent later when the application has new - * data to send. - */ - -/** @brief Identifier of the subevent_data_request event */ -#define sl_bt_evt_pawr_advertiser_subevent_data_request_id 0x005500a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_data_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_data_request_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle */ - uint8_t subevent_start; /**< The first subevent that data is requested - for */ - uint8_t subevent_data_count; /**< The number of subevents that data is - requested for */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_subevent_data_request_s sl_bt_evt_pawr_advertiser_subevent_data_request_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed sl_bt_evt_pawr_advertiser_subevent_tx_failed - * @{ - * @brief This event is triggered if subevent data was successfully set using - * @ref sl_bt_pawr_advertiser_set_subevent_data command but the attempt to - * transmit the subevent data has failed - * - * This error is not fatal. The event is provided to the application so that it - * knows not to expect response reports for this subevent and can set subevent - * data again for retransmission without needing to timeout waiting for response - * reports that will not be received because the transmission failed. - */ - -/** @brief Identifier of the subevent_tx_failed event */ -#define sl_bt_evt_pawr_advertiser_subevent_tx_failed_id 0x025500a0 - -/***************************************************************************//** - * @brief Data structure of the subevent_tx_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle for the PAwR - train that failed to transmit subevent data */ - uint8_t subevent; /**< The subevent that failed to transmit subevent - data */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s sl_bt_evt_pawr_advertiser_subevent_tx_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed - -/** - * @addtogroup sl_bt_evt_pawr_advertiser_response_report sl_bt_evt_pawr_advertiser_response_report - * @{ - * @brief Reports the status and data of a used response slot of an active PAwR - * train - * - * The report is given for every response slot that was marked as used in the - * @ref sl_bt_pawr_advertiser_set_subevent_data command. - */ - -/** @brief Identifier of the response_report event */ -#define sl_bt_evt_pawr_advertiser_response_report_id 0x015500a0 - -/***************************************************************************//** - * @brief Data structure of the response_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_response_report_s -{ - uint8_t advertising_set; /**< The PAwR advertising set handle */ - uint8_t subevent; /**< The subevent that this report corresponds to */ - int8_t tx_power; /**< TX power value in the received packet header. - Units: dBm - - Valid value range: -127 to 126 - - Value 127: information unavailable */ - int8_t rssi; /**< Signal strength indicator (RSSI) of the - received packet. Units: dBm - - Valid value range: -127 to +20 - - Value 127: information unavailable */ - uint8_t cte_type; /**< The CTE type - - 0x00: AoA CTE - - 0x01: AoD CTE with 1us slots - - 0x02: AoD CTE with 2us slots - - 0xFF: No CTE */ - uint8_t response_slot; /**< The response slot that this report - corresponds to */ - uint8_t data_status; /**< Data completeness: - - 0: Complete - - 1: Incomplete, more data to come - in new events - - 2: Incomplete, data truncated, no - more to come - - 255: Failed to receive subevent - response in this response slot */ - uint8_t counter; /**< The sequence number of this @ref - sl_bt_evt_pawr_advertiser_response_report - event as a monotonically increasing counter - that wraps from 255 to 0. There is a single - counter for this event type that starts from - value 0 when the Bluetooth stack is started - and is never reset while the stack is - running. This counter can be used to detect - if one or more @ref - sl_bt_evt_pawr_advertiser_response_report - events have been created by the stack but - dropped due to problems such as temporarily - running out of resources before the event - reached the application. */ - uint8array data; /**< The response data that was received, if any */ -}); - -typedef struct sl_bt_evt_pawr_advertiser_response_report_s sl_bt_evt_pawr_advertiser_response_report_t; - -/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_response_report - -/***************************************************************************//** - * - * Start PAwR advertising on the specified advertising set. - * - * According to the Bluetooth Core specification, PAwR advertising PDUs cannot - * be transmitted until at least one extended advertising event has been - * completed. If the application needs exact control over the extended - * advertising data and parameters, use the @ref sl_bt_advertiser class to - * configure the parameters of the advertising set and the @ref - * sl_bt_extended_advertiser class to set or generate the desired extended - * advertising data payload. If the application does not configure the - * parameters or set the data, the default parameters and empty advertising data - * are used for the extended advertising. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p - * flags, the stack will automatically start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. The application may stop the automatically started extended - * advertising using the @ref sl_bt_advertiser_stop command. - * - * If the application has not already started extended advertising and the flag - * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in - * @p flags, the stack will momentarily start extended advertising with the - * parameters and extended advertising data currently configured to the - * advertising set. Unless the application starts extended advertising before - * the first extended advertising event has completed, the stack will - * automatically stop the momentary extended advertising after the first - * extended advertising event. - * - * PAwR advertising PDUs are transmitted on the secondary PHY configured for the - * advertising set with the @ref sl_bt_extended_advertiser_set_phy command. - * - * To stop PAwR advertising, use @ref sl_bt_pawr_advertiser_stop command. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] interval_min @parblock - * Minimum periodic advertising interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - * Default value: 100 ms - * @endparblock - * @param[in] interval_max @parblock - * Maximum periodic advertising interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFFFF - * - Time range: 7.5 ms to 81.92 s - * - Note: interval_max should be bigger than interval_min - * - * Default value: 200 ms - * @endparblock - * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask - * of @ref sl_bt_periodic_advertiser_flags - * @param[in] num_subevents The number of subevents. - * - Range: 0x01 to 0x80 - * @param[in] subevent_interval Subevent interval. Value in units of 1.25 ms. - * - Range: 0x06 to 0xFF - * - Time range: 7.5 ms to 318.75 ms - * @param[in] response_slot_delay Time between the advertising packet in a - * subevent and the first response slot. Value in units of 1.25 ms. - * - Range: 0x01 to 0xFE - * - Time range: 1.25 ms to 317.5 ms - * @param[in] response_slot_spacing Time between response slots. Value in units - * of 0.125 ms. - * - Range: 0x02 to 0xFF - * - Time range: 0.25 ms to 31.875 ms - * @param[in] response_slots Number of subevent response slots. - * - Range: 0x01 to 0xFF - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, - uint16_t interval_min, - uint16_t interval_max, - uint32_t flags, - uint8_t num_subevents, - uint8_t subevent_interval, - uint8_t response_slot_delay, - uint8_t response_slot_spacing, - uint8_t response_slots); - -/***************************************************************************//** - * - * Set data to be sent in the specified subevent of an active PAwR train. Data - * is transmitted only once and is discarded after it has been transmitted. - * - * Data given to this command is passed to the Bluetooth controller, which will - * queue data and transmit it at the correct time. The application may always - * opportunistically try to queue more data with this command, but the - * controller may reject data and return an error if the queuing capacity is - * exceeded. In this case, the Bluetooth stack will trigger the @ref - * sl_bt_evt_pawr_advertiser_subevent_data_request event later when the - * controller is ready to accept more data. - * - * To ensure effective use of the available memory, applications are encouraged - * to observe the @ref sl_bt_evt_pawr_advertiser_subevent_data_request events - * and set data for the subevents that are being requested and for which the - * application has data to send. Applications should also note that PAwR is an - * unreliable transport and cannot guarantee delivery. If reliability is - * required, the application must implement an acknowledgment mechanism using - * response slots of the PAwR train and set subevent data again for a - * re-transmission if it was not successfully delivered. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] subevent The subevent in which the data is to be sent - * @param[in] response_slot_start The first response slot to be used in this - * subevent - * @param[in] response_slot_count The number of response slots to be used - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be sent in the specified subevent - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_pawr_advertiser_subevent_data_request - This event is - * triggered when the Bluetooth stack is ready to accept more subevent data. - * - @ref sl_bt_evt_pawr_advertiser_subevent_tx_failed - This event is - * triggered if transmitting the subevent data has failed. - * - @ref sl_bt_evt_pawr_advertiser_response_report - If the subevent data was - * successfully transmitted, this event is triggered for each response slot - * that was marked as used in this subevent. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, - uint8_t subevent, - uint8_t response_slot_start, - uint8_t response_slot_count, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Initiate a connection request to a device that is synchronized to the - * specified active PAwR train. The connection is established on the secondary - * PHY configured for the advertising set with the @ref - * sl_bt_extended_advertiser_set_phy command. The connection uses the parameters - * configured with command @ref sl_bt_connection_set_default_parameters. - * - * @param[in] advertising_set The PAwR advertising set handle - * @param[in] subevent The subevent in which the connection request is to be - * sent - * @param[in] address Address of the device to connect to - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device to connect to. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @param[out] connection Handle that will be assigned to the connection after - * the connection is established. This handle is valid only if the result code - * of this command is SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - This event is triggered if the - * connection failed to be created. - * - @ref sl_bt_evt_connection_opened - This event is triggered after the - * connection is opened and indicates whether the devices are already bonded - * and the role of the device in this connection. - * - @ref sl_bt_evt_connection_parameters - This event indicates the - * connection parameters and security mode of the connection. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, - uint8_t subevent, - bd_addr address, - uint8_t address_type, - uint8_t *connection); - -/***************************************************************************//** - * - * Stop PAwR advertising on an advertising set. Counterpart to @ref - * sl_bt_pawr_advertiser_start. - * - * This command does not affect the enable state of the advertising set, i.e., - * legacy or extended advertising is not stopped. - * - * @param[in] advertising_set The PAwR advertising set handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set); - -/** @} */ // end addtogroup sl_bt_pawr_advertiser - -/** - * @addtogroup sl_bt_connection Connection - * @{ - * - * @brief Connection - * - * The commands and events in this class are related to managing connection - * establishment, parameter setting, and disconnection procedures. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_connection_set_default_parameters_id 0x00060020 -#define sl_bt_cmd_connection_set_default_preferred_phy_id 0x01060020 -#define sl_bt_cmd_connection_set_default_data_length_id 0x10060020 -#define sl_bt_cmd_connection_open_id 0x04060020 -#define sl_bt_cmd_connection_set_parameters_id 0x06060020 -#define sl_bt_cmd_connection_set_preferred_phy_id 0x08060020 -#define sl_bt_cmd_connection_disable_slave_latency_id 0x03060020 -#define sl_bt_cmd_connection_get_median_rssi_id 0x15060020 -#define sl_bt_cmd_connection_read_channel_map_id 0x07060020 -#define sl_bt_cmd_connection_set_power_reporting_id 0x09060020 -#define sl_bt_cmd_connection_set_remote_power_reporting_id 0x0a060020 -#define sl_bt_cmd_connection_get_tx_power_id 0x0b060020 -#define sl_bt_cmd_connection_get_remote_tx_power_id 0x0c060020 -#define sl_bt_cmd_connection_set_tx_power_id 0x12060020 -#define sl_bt_cmd_connection_read_remote_used_features_id 0x0d060020 -#define sl_bt_cmd_connection_get_security_status_id 0x0e060020 -#define sl_bt_cmd_connection_set_data_length_id 0x11060020 -#define sl_bt_cmd_connection_read_statistics_id 0x13060020 -#define sl_bt_cmd_connection_get_scheduling_details_id 0x14060020 -#define sl_bt_cmd_connection_close_id 0x05060020 -#define sl_bt_cmd_connection_forcefully_close_id 0x0f060020 -#define sl_bt_cmd_connection_get_rssi_id 0x02060020 -#define sl_bt_rsp_connection_set_default_parameters_id 0x00060020 -#define sl_bt_rsp_connection_set_default_preferred_phy_id 0x01060020 -#define sl_bt_rsp_connection_set_default_data_length_id 0x10060020 -#define sl_bt_rsp_connection_open_id 0x04060020 -#define sl_bt_rsp_connection_set_parameters_id 0x06060020 -#define sl_bt_rsp_connection_set_preferred_phy_id 0x08060020 -#define sl_bt_rsp_connection_disable_slave_latency_id 0x03060020 -#define sl_bt_rsp_connection_get_median_rssi_id 0x15060020 -#define sl_bt_rsp_connection_read_channel_map_id 0x07060020 -#define sl_bt_rsp_connection_set_power_reporting_id 0x09060020 -#define sl_bt_rsp_connection_set_remote_power_reporting_id 0x0a060020 -#define sl_bt_rsp_connection_get_tx_power_id 0x0b060020 -#define sl_bt_rsp_connection_get_remote_tx_power_id 0x0c060020 -#define sl_bt_rsp_connection_set_tx_power_id 0x12060020 -#define sl_bt_rsp_connection_read_remote_used_features_id 0x0d060020 -#define sl_bt_rsp_connection_get_security_status_id 0x0e060020 -#define sl_bt_rsp_connection_set_data_length_id 0x11060020 -#define sl_bt_rsp_connection_read_statistics_id 0x13060020 -#define sl_bt_rsp_connection_get_scheduling_details_id 0x14060020 -#define sl_bt_rsp_connection_close_id 0x05060020 -#define sl_bt_rsp_connection_forcefully_close_id 0x0f060020 -#define sl_bt_rsp_connection_get_rssi_id 0x02060020 - -/** - * @brief Types of device roles in a Bluetooth connection - */ -typedef enum -{ - sl_bt_connection_role_peripheral = 0x0, /**< (0x0) The Peripheral role */ - sl_bt_connection_role_central = 0x1 /**< (0x1) The Central role */ -} sl_bt_connection_role_t; - -/** - * @brief Indicate the Bluetooth Security Mode. - */ -typedef enum -{ - sl_bt_connection_mode1_level1 = 0x0, /**< (0x0) No security */ - sl_bt_connection_mode1_level2 = 0x1, /**< (0x1) Unauthenticated pairing with - encryption */ - sl_bt_connection_mode1_level3 = 0x2, /**< (0x2) Authenticated pairing with - encryption */ - sl_bt_connection_mode1_level4 = 0x3 /**< (0x3) Authenticated Secure - Connections pairing with encryption - using a 128-bit strength encryption - key */ -} sl_bt_connection_security_t; - -/** - * @brief These values define transmit power reporting modes in LE power - * control. - */ -typedef enum -{ - sl_bt_connection_power_reporting_disable = 0x0, /**< (0x0) Disable transmit - power reporting */ - sl_bt_connection_power_reporting_enable = 0x1 /**< (0x1) Enable transmit - power reporting */ -} sl_bt_connection_power_reporting_mode_t; - -/** - * @brief This enum defines the flag values for a reported transmit power level. - */ -typedef enum -{ - sl_bt_connection_tx_power_flag_none = 0x0, /**< (0x0) No flag is defined for - the reported TX power level */ - sl_bt_connection_tx_power_at_minimum = 0x1, /**< (0x1) Transmit power level is - at minimum level. */ - sl_bt_connection_tx_power_at_maximum = 0x2 /**< (0x2) Transmit power level is - at maximum level. */ -} sl_bt_connection_tx_power_flag_t; - -/** - * @addtogroup sl_bt_connection_rssi_const RSSI Value Constants - * @{ - * - * Constants for RSSI value - */ - -/** RSSI value is unavailable */ -#define SL_BT_CONNECTION_RSSI_UNAVAILABLE 0x7f - -/** @} */ // end RSSI Value Constants - -/** - * @addtogroup sl_bt_connection_tx_power_const Transmit Power Reporting Constants - * @{ - * - * Constants in transmit power reporting - */ - -/** Remote device is not managing power levels. */ -#define SL_BT_CONNECTION_TX_POWER_UNMANAGED 0x7e - -/** Transmit power level is not available. */ -#define SL_BT_CONNECTION_TX_POWER_UNAVAILABLE 0x7f - -/** Change is not available or is out of range. */ -#define SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE 0x7f - -/** @} */ // end Transmit Power Reporting Constants - -/** - * @addtogroup sl_bt_evt_connection_opened sl_bt_evt_connection_opened - * @{ - * @brief Indicates that a new connection was opened - * - * The specific semantics depend on the role of the device: - * - On the central device (parameter @p master set to @ref - * sl_bt_connection_role_central) the event is triggered when the Link Layer - * has sent a connect request to the remote device. - * - On the peripheral device (parameter @p master set to @ref - * sl_bt_connection_role_peripheral) the event is triggered when the Link - * Layer has responded to the connect request of the remote device. - * - * This event does not indicate the connection has been established (i.e., that - * a data packet was received within 6 connection intervals). If the connection - * is not established, an @ref sl_bt_evt_connection_closed event will - * immediately follow. - * - * An open connection can be closed with @ref sl_bt_connection_close command by - * giving the connection handle obtained from this event. - */ - -/** @brief Identifier of the opened event */ -#define sl_bt_evt_connection_opened_id 0x000600a0 - -/***************************************************************************//** - * @brief Data structure of the opened event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_opened_s -{ - bd_addr address; /**< Remote device address */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. Remote device - address type. Values: - - sl_bt_gap_public_address (0x0): Public - device address - - sl_bt_gap_static_address (0x1): Static - device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address resolved - from a resolvable private address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address resolved - from a resolvable private address (RPA) */ - uint8_t master; /**< Enum @ref sl_bt_connection_role_t. The role this - device operates in the connection. Values: - - sl_bt_connection_role_peripheral (0x0): - The Peripheral role - - sl_bt_connection_role_central (0x1): - The Central role */ - uint8_t connection; /**< Handle for new connection */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): No - bonding - - Other: Bonding handle */ - uint8_t advertiser; /**< The local advertising set that this connection was - opened to. Values: - - SL_BT_INVALID_ADVERTISING_SET_HANDLE - (0xff): Invalid value or not applicable. - Ignore this field - - Other: The advertising set handle */ - uint16_t sync; /**< The sync handle if the local device is in the - peripheral-role and the connection was opened via - a Periodic Advertising with Responses (PAwR) train - that the local device has synchronized to. Values: - - SL_BT_INVALID_SYNC_HANDLE (0xffff): The - connection was not opened over a PAwR train - that the local device is synchronized to - - Other: The sync handle for the PAwR - train that was used to open the connection */ -}); - -typedef struct sl_bt_evt_connection_opened_s sl_bt_evt_connection_opened_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_opened - -/** - * @addtogroup sl_bt_evt_connection_parameters sl_bt_evt_connection_parameters - * @{ - * @brief Triggered whenever the connection parameters are changed and at any - * time a connection is established - */ - -/** @brief Identifier of the parameters event */ -#define sl_bt_evt_connection_parameters_id 0x020600a0 - -/***************************************************************************//** - * @brief Data structure of the parameters event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_parameters_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t interval; /**< Connection interval. Time = Value x 1.25 ms */ - uint16_t latency; /**< Peripheral latency (how many connection intervals - the peripheral can skip) */ - uint16_t timeout; /**< Supervision timeout. Time = Value x 10 ms */ - uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection - security mode. Values: - - sl_bt_connection_mode1_level1 (0x0): - No security - - sl_bt_connection_mode1_level2 (0x1): - Unauthenticated pairing with encryption - - sl_bt_connection_mode1_level3 (0x2): - Authenticated pairing with encryption - - sl_bt_connection_mode1_level4 (0x3): - Authenticated Secure Connections pairing with - encryption using a 128-bit strength - encryption key */ - uint16_t txsize; /**< Deprecated and no longer used for - reporting the connection data length update. Use - the event @ref sl_bt_evt_connection_data_length - instead. */ -}); - -typedef struct sl_bt_evt_connection_parameters_s sl_bt_evt_connection_parameters_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_parameters - -/** - * @addtogroup sl_bt_evt_connection_set_parameters_failed sl_bt_evt_connection_set_parameters_failed - * @{ - * @brief Triggered when the peer device rejected an L2CAP connection parameter - * update request as a result of calling command @ref - * sl_bt_connection_set_parameters to change connection parameters on the @ref - * sl_bt_connection_role_peripheral role - */ - -/** @brief Identifier of the set_parameters_failed event */ -#define sl_bt_evt_connection_set_parameters_failed_id 0x100600a0 - -/***************************************************************************//** - * @brief Data structure of the set_parameters_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_set_parameters_failed_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_connection_set_parameters_failed_s sl_bt_evt_connection_set_parameters_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_set_parameters_failed - -/** - * @addtogroup sl_bt_evt_connection_phy_status sl_bt_evt_connection_phy_status - * @{ - * @brief Indicates that PHY update procedure is completed. - */ - -/** @brief Identifier of the phy_status event */ -#define sl_bt_evt_connection_phy_status_id 0x040600a0 - -/***************************************************************************//** - * @brief Data structure of the phy_status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_phy_status_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t phy; /**< Current active PHY. See values from @ref - sl_bt_connection_set_preferred_phy command. */ -}); - -typedef struct sl_bt_evt_connection_phy_status_s sl_bt_evt_connection_phy_status_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_phy_status - -/** - * @addtogroup sl_bt_evt_connection_get_remote_tx_power_completed sl_bt_evt_connection_get_remote_tx_power_completed - * @{ - * @brief Indicates that reading remote transmit power initiated by @ref - * sl_bt_connection_get_remote_tx_power command has completed - */ - -/** @brief Identifier of the get_remote_tx_power_completed event */ -#define sl_bt_evt_connection_get_remote_tx_power_completed_id 0x050600a0 - -/***************************************************************************//** - * @brief Data structure of the get_remote_tx_power_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_get_remote_tx_power_completed_s -{ - uint16_t status; /**< SL_STATUS_OK or another error code indicating the - reading remote transmit power operation failed. */ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY for which - the transmit power is reported. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): - 1M PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): - 2M PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED - (0x7E): Remote device is not managing power - levels on this PHY. - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. - Transmit power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out - of range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_get_remote_tx_power_completed_s sl_bt_evt_connection_get_remote_tx_power_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_get_remote_tx_power_completed - -/** - * @addtogroup sl_bt_evt_connection_tx_power sl_bt_evt_connection_tx_power - * @{ - * @brief Reports a transmit power change on the local device of a connection if - * transmit power reporting has been enabled - * - * Enable or disable transmit power reporting using @ref - * sl_bt_connection_set_power_reporting command. Local transmit power reporting - * is enabled by default for new connections. - * - * When enabled, local transmit power change events may get triggered in the - * following situations: - * - When the connection has just opened and the initial transmit power is set - * - When the application explicitly changes the system TX power using the - * @ref sl_bt_system_set_tx_power command - * - When the bluetooth_feature_power_control component is included and - * enabled in the application and the local transmit power is adjusted by - * the power control feature - * - When the bluetooth_feature_afh component for Adaptive Frequency Hopping - * is included and enabled in the application and the local transmit power - * is adjusted due to changes in the availability of good channels. - */ - -/** @brief Identifier of the tx_power event */ -#define sl_bt_evt_connection_tx_power_id 0x060600a0 - -/***************************************************************************//** - * @brief Data structure of the tx_power event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_tx_power_s -{ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the - transmit power is reported for. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M - PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M - PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit - power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out of - range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_tx_power_s sl_bt_evt_connection_tx_power_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_tx_power - -/** - * @addtogroup sl_bt_evt_connection_remote_tx_power sl_bt_evt_connection_remote_tx_power - * @{ - * @brief Reports a transmit power change of the connection on the remote device - * that supports the LE Power Control for the connection - * - * This event is enabled if reporting the remote transmit power change has been - * enabled with the @ref sl_bt_connection_set_remote_power_reporting command. - */ - -/** @brief Identifier of the remote_tx_power event */ -#define sl_bt_evt_connection_remote_tx_power_id 0x070600a0 - -/***************************************************************************//** - * @brief Data structure of the remote_tx_power event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_remote_tx_power_s -{ - uint8_t connection; /**< Handle of the connection */ - uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the - transmit power is reported for. Values: - - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M - PHY - - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M - PHY - - sl_bt_gap_phy_coding_125k_coded (0x4): - 125k Coded PHY (S=8) - - sl_bt_gap_phy_coding_500k_coded (0x8): - 500k Coded PHY (S=2) */ - int8_t power_level; /**< Transmit power level. Values: - - Range -127 to 20: The transmit power - level in dBm - - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED - (0x7E): Remote device is not managing power - levels on this PHY. - - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE - (0x7F): Transmit power level is not - available. */ - uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit - power level flags. Ignore this field if @p - power_level is set to 0x7E or 0x7F. Values: - - sl_bt_connection_tx_power_flag_none - (0x0): No flag is defined for the reported - TX power level - - sl_bt_connection_tx_power_at_minimum - (0x1): Transmit power level is at minimum - level. - - sl_bt_connection_tx_power_at_maximum - (0x2): Transmit power level is at maximum - level. */ - int8_t delta; /**< Change in transmit power level. Values: - - @ref - SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE - (0x7F): Change is not available or is out of - range. - - Other values: positive indicates - increased power, negative indicates decreased - power, and zero indicates unchanged. Units: dB */ -}); - -typedef struct sl_bt_evt_connection_remote_tx_power_s sl_bt_evt_connection_remote_tx_power_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_remote_tx_power - -/** - * @addtogroup sl_bt_evt_connection_remote_used_features sl_bt_evt_connection_remote_used_features - * @{ - * @brief List of link layer features supported by the remote device. - */ - -/** @brief Identifier of the remote_used_features event */ -#define sl_bt_evt_connection_remote_used_features_id 0x080600a0 - -/***************************************************************************//** - * @brief Data structure of the remote_used_features event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_remote_used_features_s -{ - uint8_t connection; /**< Connection handle */ - uint8array features; /**< This parameter is 8 bytes in little endian format - and contains bit fields describing the supported - link layer features of the remote device. Bit - value 1 means that the feature is supported. - - The bits are explained in Bluetooth specification - Vol 6, Part B, 4.6. */ -}); - -typedef struct sl_bt_evt_connection_remote_used_features_s sl_bt_evt_connection_remote_used_features_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_remote_used_features - -/** - * @addtogroup sl_bt_evt_connection_data_length sl_bt_evt_connection_data_length - * @{ - * @brief Reports a change to the maximum payload length or maximum TX time in - * either direction of a connection. - */ - -/** @brief Identifier of the data_length event */ -#define sl_bt_evt_connection_data_length_id 0x090600a0 - -/***************************************************************************//** - * @brief Data structure of the data_length event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_data_length_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t tx_data_len; /**< The maximum payload octets of a packet that the - local Controller will send */ - uint16_t tx_time_us; /**< The maximum time in microseconds that the local - Controller will take to send a data packet */ - uint16_t rx_data_len; /**< The maximum payload octets of a packet that the - local Controller expects to receive */ - uint16_t rx_time_us; /**< The maximum time in microseconds that the local - Controller expects to take to receive a data packet */ -}); - -typedef struct sl_bt_evt_connection_data_length_s sl_bt_evt_connection_data_length_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_data_length - -/** - * @addtogroup sl_bt_evt_connection_statistics sl_bt_evt_connection_statistics - * @{ - * @brief Provides the connection statistic values when the application includes - * the component bluetooth_feature_connection_statistics - * - * When the component is included by the application, this event is - * automatically triggered to provide the final statistics for the connection - * just before the @ref sl_bt_evt_connection_closed event indicates that a - * connection has been closed. This event is also triggered when the application - * has requested reading the statistics using the command @ref - * sl_bt_connection_read_statistics. - */ - -/** @brief Identifier of the statistics event */ -#define sl_bt_evt_connection_statistics_id 0x0a0600a0 - -/***************************************************************************//** - * @brief Data structure of the statistics event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_statistics_s -{ - uint8_t connection; /**< Handle of the connection */ - int8_t rssi_min; /**< The minimum Received Signal - Strength Indicator (RSSI) - value measured for packets - that have been successfully - received on this connection. - Units: dBm - - Valid value range: -127 to - +20 - - Value 127: information - unavailable */ - int8_t rssi_max; /**< The maximum Received Signal - Strength Indicator (RSSI) - value measured for packets - that have been successfully - received on this connection. - Units: dBm - - Valid value range: -127 to - +20 - - Value 127: information - unavailable */ - uint32_t num_total_connection_events; /**< The total number of connection - events that would have - occurred on this connection if - no packets were lost. This - count therefore includes also - connection events that were - missed due to errors (see @p - num_missed_connection_events). - In the Peripheral device this - count does not include - connection events where the - Peripheral deliberately did - not listen due to Peripheral - latency. */ - uint32_t num_missed_connection_events; /**< The number of connection - events that have been missed - on this connection. This - includes connection events - where the first packet of a - connection event was either - not received at all or was - corrupted so that it was not - recognized as belonging to - this connection. */ - uint32_t num_successful_connection_events; /**< The number of connection - events that have occured on - this connection without - errors. */ - uint32_t num_crc_errors; /**< The number of packets that - have been received on this - connection with a Cyclic - Redundancy Check (CRC) error. */ -}); - -typedef struct sl_bt_evt_connection_statistics_s sl_bt_evt_connection_statistics_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_statistics - -/** - * @addtogroup sl_bt_evt_connection_closed sl_bt_evt_connection_closed - * @{ - * @brief Indicates that a connection was either closed or that no connection - * was established from a high duty cycle directed advertising. - * - * If the application includes the component - * bluetooth_feature_connection_statistics and the connection was successfully - * opened, the event @ref sl_bt_evt_connection_statistics is automatically - * triggered just before the connection closed event to provide the application - * with the final statistic values of the connection. - */ - -/** @brief Identifier of the closed event */ -#define sl_bt_evt_connection_closed_id 0x010600a0 - -/***************************************************************************//** - * @brief Data structure of the closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_closed_s -{ - uint16_t reason; /**< Reason of connection close. - - Error code SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT - indicates that the high duty cycle directed - advertising timed out and no connection was - established. Ignore the value of @p connection in - this case. */ - uint8_t connection; /**< Handle of the closed connection */ -}); - -typedef struct sl_bt_evt_connection_closed_s sl_bt_evt_connection_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_closed - -/** - * @addtogroup sl_bt_evt_connection_rssi sl_bt_evt_connection_rssi - * @{ - * @brief Triggered when a @ref sl_bt_connection_get_rssi command has completed - * - * This event is only used by deprecated @ref sl_bt_connection_get_rssi that - * returns the RSSI value asynchronously. - * - * Use the @ref sl_bt_connection_get_median_rssi command to get the RSSI - * synchronously. - */ - -/** @brief Identifier of the rssi event */ -#define sl_bt_evt_connection_rssi_id 0x030600a0 - -/***************************************************************************//** - * @brief Data structure of the rssi event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_rssi_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t status; /**< Command complete status which is always SL_STATUS_OK */ - int8_t rssi; /**< The median of the last seven measured RSSI values on - the connection. Units: dBm. Range: -127 to +20. */ -}); - -typedef struct sl_bt_evt_connection_rssi_s sl_bt_evt_connection_rssi_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_rssi - -/***************************************************************************//** - * - * Set default Bluetooth connection parameters. The values are valid for all - * subsequent connections initiated by this device. - * - * @p min_ce_length and @p max_ce_length specify the preference of the - * connection event length so that the Link Layer can prioritize tasks - * accordingly in simultaneous connections, or scanning and so on. A connection - * event starts at an anchor point of a connection interval and lasts until the - * lesser of @p max_ce_length and the actual connection interval. Packets that - * do not fit into the connection event will be sent in the next connection - * interval. - * - * To change parameters of an already established connection, use the command - * @ref sl_bt_connection_set_parameters. - * - * @param[in] min_interval @parblock - * Minimum value for the connection event interval. This must be set less than - * or equal to @p max_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * - * Default value: 20 ms - * @endparblock - * @param[in] max_interval @parblock - * Maximum value for the connection event interval. This must be set greater - * than or equal to @p min_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * - * Default value: 50 ms - * @endparblock - * @param[in] latency @parblock - * Peripheral latency, which defines how many connection intervals the - * peripheral can skip if it has no data to send - * - Range: 0x0000 to 0x01f3 - * - * Default value: 0 - * @endparblock - * @param[in] timeout @parblock - * Supervision timeout, which defines the time that the connection is - * maintained although the devices can't communicate at the currently - * configured connection intervals. - * - Range: 0x000a to 0x0c80 - * - Time = Value x 10 ms - * - Time Range: 100 ms to 32 s - * - The value in milliseconds must be larger than (1 + @p latency) * @p - * max_interval * 2, where @p max_interval is given in milliseconds - * - * Set the supervision timeout at a value which allows communication attempts - * over at least a few connection intervals. - * - * Default value: 1000 ms - * @endparblock - * @param[in] min_ce_length @parblock - * Minimum length of the connection event. It must be less than or equal to @p - * max_ce_length. - * - * This value defines the minimum time that should be given to the connection - * event in a situation where other tasks need to run immediately after the - * connection event. When the value is very small, the connection event still - * has at least one TX/RX operation. If this value is increased, more time is - * reserved for the connection event so it can transmit and receive more - * packets in a connection interval. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0x0000 - * @endparblock - * @param[in] max_ce_length @parblock - * Maximum length of the connection event. It must be greater than or equal to - * @p min_ce_length. - * - * This value is used for limiting the connection event length so that a - * connection that has large amounts of data to transmit or receive doesn't - * block other tasks. Limiting the connection event is a hard stop. If there - * is no enough time to send or receive a packet, the connection event will be - * closed. - * - * If the value is set to 0, the connection event still has at least one TX/RX - * operation. This is useful to limit power consumption or leave more time to - * other tasks. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0xffff - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length); - -/***************************************************************************//** - * - * Set default preferred and accepted PHYs. PHY settings will be used for all - * subsequent connections. Non-preferred PHY can also be set if the remote - * device does not accept any of the preferred PHYs. - * - * The parameter @p accepted_phy is used to specify PHYs that the stack can - * accept in a remotely-initiated PHY update request. A PHY update will not - * happen if none of the accepted PHYs are present in the request. - * - * NOTE: 2M and Coded PHYs are not supported by all devices. - * - * @param[in] preferred_phy @parblock - * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (no preference) - * @endparblock - * @param[in] accepted_phy @parblock - * Accepted PHYs in remotely-initiated PHY update request. This parameter is a - * bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (all PHYs accepted) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, - uint8_t accepted_phy); - -/***************************************************************************//** - * - * Set the default preferred maximum TX payload length to be used for new - * connections. - * - * When a connection is open, the maximum TX payload length is 27. Either device - * could initiate a data length update procedure and event @ref - * sl_bt_evt_connection_data_length is generated when the data length has been - * changed on the connection. - * - * @param[in] tx_data_len @parblock - * Preferred maximum payload octets of a packet that the local Controller will - * send - * - * Range: Range: 27 (0x1B) to 251 (0xFB) - * - * Default: 251 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len); - -/***************************************************************************//** - * - * Connect to an advertising device with the specified initiating PHY on which - * connectable advertisements on primary advertising channels are received. The - * Bluetooth stack will enter a state where it continuously scans for the - * connectable advertising packets from the remote device, which matches the - * Bluetooth address given as a parameter. Scan parameters set in @ref - * sl_bt_scanner_set_timing are used in this operation. Upon receiving the - * advertising packet, the module will send a connection request packet to the - * target device to initiate a Bluetooth connection. To cancel an ongoing - * connection process, use @ref sl_bt_connection_close command with the handle - * received in response from this command. - * - * A connection is opened in no-security mode. If the GATT client needs to read - * or write the attributes on GATT server requiring encryption or - * authentication, it must first encrypt the connection using an appropriate - * authentication method. - * - * If a connection can't be established, for example, the remote device has gone - * out of range, has entered into deep sleep, or is not advertising, the stack - * will try to connect forever. In this case, the application will not get an - * event related to the connection request. To recover from this situation, the - * application can implement a timeout and call @ref sl_bt_connection_close to - * cancel the connection request. - * - * This command fails with the connection limit exceeded error if the number of - * connections attempted exceeds the configured MAX_CONNECTIONS value. - * - * This command fails with the invalid parameter error if the initiating PHY - * value is invalid or the device does not support PHY. - * - * Subsequent calls of this command have to wait for the ongoing command to - * complete. A received event @ref sl_bt_evt_connection_opened indicates that - * the connection opened successfully and a received event @ref - * sl_bt_evt_connection_closed indicates that connection failures have occurred. - * - * @param[in] address Address of the device to connect to - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device to connect to. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private - * random address - * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable - * private random address - * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public - * identity address resolved from a resolvable private address (RPA) - * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static - * identity address resolved from a resolvable private address (RPA) - * @param[in] initiating_phy Enum @ref sl_bt_gap_phy_t. The initiating PHY. - * Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] connection Handle that will be assigned to the connection after - * the connection is established. This handle is valid only if the result code - * of this response is 0 (zero). - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_opened - This event is triggered after the - * connection is opened and indicates whether the devices are already bonded - * and the role of the device in this connection. - * - @ref sl_bt_evt_connection_parameters - This event indicates the - * connection parameters and security mode of the connection. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_open(bd_addr address, - uint8_t address_type, - uint8_t initiating_phy, - uint8_t *connection); - -/***************************************************************************//** - * - * Request a change in the connection parameters of a Bluetooth connection. - * - On the central device the HCI LE Connection Update command is used to - * update the parameters. - * - On the peripheral device an L2CAP connection parameter update request is - * sent to the peer device to update the parameters. - * - * @p min_ce_length and @p max_ce_length specify the preference of the - * connection event length so that the Link Layer can prioritize tasks - * accordingly in simultaneous connections, or scanning and so on. A connection - * event starts at an anchor point of a connection interval and lasts until the - * lesser of @p max_ce_length and the actual connection interval. Packets that - * do not fit into the connection event will be sent in the next connection - * interval. - * - * @param[in] connection Connection Handle - * @param[in] min_interval Minimum value for the connection event interval. This - * must be set less than or equal to @p max_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * @param[in] max_interval Maximum value for the connection event interval. This - * must be set greater than or equal to @p min_interval. - * - Time = Value x 1.25 ms - * - Range: 0x0006 to 0x0c80 - * - Time Range: 7.5 ms to 4 s - * @param[in] latency Peripheral latency, which defines how many connection - * intervals the peripheral can skip if it has no data to send - * - Range: 0x0000 to 0x01f3 - * @param[in] timeout @parblock - * Supervision timeout, which defines the time that the connection is - * maintained although the devices can't communicate at the currently - * configured connection intervals. - * - Range: 0x000a to 0x0c80 - * - Time = Value x 10 ms - * - Time Range: 100 ms to 32 s - * - The value in milliseconds must be larger than (1 + @p latency) * @p - * max_interval * 2, where @p max_interval is given in milliseconds - * - * Set the supervision timeout at a value which allows communication attempts - * over at least a few connection intervals. - * @endparblock - * @param[in] min_ce_length @parblock - * Minimum length of the connection event. It must be less than or equal to @p - * max_ce_length. - * - * This value defines the minimum time that should be given to the connection - * event in a situation where other tasks need to run immediately after the - * connection event. When the value is very small, the connection event still - * has at least one TX/RX operation. If this value is increased, more time is - * reserved for the connection event so it can transmit and receive more - * packets in a connection interval. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0x0000 - * @endparblock - * @param[in] max_ce_length @parblock - * Maximum length of the connection event. It must be greater than or equal to - * @p min_ce_length. - * - * This value is used for limiting the connection event length so that a - * connection that has large amounts of data to transmit or receive doesn't - * block other tasks. Limiting the connection event is a hard stop. If there - * is no enough time to send or receive a packet, the connection event will be - * closed. - * - * If the value is set to 0, the connection event still has at least one TX/RX - * operation. This is useful to limit power consumption or leave more time to - * other tasks. - * - * Use the default value if the application doesn't care about the connection - * event length or doesn't want to do fine tuning. - * - Time = Value x 0.625 ms - * - Range: 0x0000 to 0xffff - * - * Default value: 0xffff - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_parameters - Triggered after new connection - * parameters are applied on the connection. - * - @ref sl_bt_evt_connection_set_parameters_failed - Triggered when the peer - * device rejected an L2CAP connection parameter update request. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_parameters(uint8_t connection, - uint16_t min_interval, - uint16_t max_interval, - uint16_t latency, - uint16_t timeout, - uint16_t min_ce_length, - uint16_t max_ce_length); - -/***************************************************************************//** - * - * Set preferred and accepted PHYs for a given connection. Event @ref - * sl_bt_evt_connection_phy_status is received when PHY update procedure is - * completed. Non-preferred PHY can also be set if remote device does not accept - * any of the preferred PHYs. - * - * The parameter @p accepted_phy is used for specifying the PHYs that the stack - * can accept in a remote initiated PHY update request. A PHY update will not - * occur if none of the accepted PHYs presents in the request. - * - * NOTE: 2M and Coded PHYs are not supported by all devices. - * - * @param[in] connection Connection handle - * @param[in] preferred_phy @parblock - * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: 125k Coded PHY (S=8) - * - 0x08: 500k Coded PHY (S=2) - * - * Default: 0xff (no preference) - * @endparblock - * @param[in] accepted_phy @parblock - * Accepted PHYs in remotely-initiated PHY update requests. This parameter is - * a bitfield and multiple PHYs can be set. - * - 0x01: 1M PHY - * - 0x02: 2M PHY - * - 0x04: Coded PHY - * - 0xff: Any PHYs - * - * Default: 0xff (all PHYs accepted) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_phy_status - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, - uint8_t preferred_phy, - uint8_t accepted_phy); - -/***************************************************************************//** - * - * Temporarily enable or disable peripheral latency. Used only when Bluetooth - * device is acting as a peripheral. When peripheral latency is disabled, the - * peripheral latency connection parameter is not set to 0 but the device will - * wake up on every connection interval to receive and send packets. - * - * @param[in] connection Connection Handle - * @param[in] disable 0 enable, 1 disable peripheral latency. Default: 0 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, - uint8_t disable); - -/***************************************************************************//** - * - * Get the RSSI value measured on a connection. - * - * @param[in] connection Connection handle - * @param[out] rssi The median of the last seven measured RSSI values. Units: - * dBm. Range: -127 to +20. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi); - -/***************************************************************************//** - * - * Read channel map for a specified connection. - * - * @param[in] connection Connection Handle - * @param[in] max_channel_map_size Size of output buffer passed in @p - * channel_map - * @param[out] channel_map_len On return, set to the length of output data - * written to @p channel_map - * @param[out] channel_map @parblock - * This parameter is 5 bytes and contains 37 1-bit fields. - * - * The nth field (in the range 0 to 36) contains the value for the link layer - * channel index n. - * - * - 0: Channel n is unused. - * - 1: Channel n is used. - * - * The most significant bits are reserved for future use. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, - size_t max_channel_map_size, - size_t *channel_map_len, - uint8_t *channel_map); - -/***************************************************************************//** - * - * Enable or disable the transmit power reporting for the local device on a - * connection. When transmit power reporting is enabled, event @ref - * sl_bt_evt_connection_tx_power is generated when transmit power on the local - * device changes. - * - * The command is a built-in feature in the stack and is supported regardless of - * whether the LE Power Control feature is used. By default, power reporting for - * local device is enabled. - * - * @param[in] connection Handle of the connection - * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit - * power reporting mode. Values: - * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit - * power reporting - * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit - * power reporting - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_tx_power - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, - uint8_t mode); - -/***************************************************************************//** - * - * Enable or disable reporting the transmit power change on the remote device. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. - * - * When the remote transmit power reporting is enabled, event @ref - * sl_bt_evt_connection_remote_tx_power is generated when transmit power on the - * remote device changes. - * - * By default, power reporting for the remote device is disabled. - * - * @param[in] connection Handle of the connection - * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit - * power reporting mode. Values: - * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit - * power reporting - * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit - * power reporting - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_remote_tx_power - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, - uint8_t mode); - -/***************************************************************************//** - * - * Get the transmit power of the local device on the given connection and PHY. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. - * - * @param[in] connection Handle of the connection - * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: - * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY - * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY - * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) - * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) - * @param[out] current_level The current transmit power level of the PHY on the - * connection. Values: - * - Range -127 to 20: The transmit power level in dBm - * - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE (0x7F): Transmit - * power level is not available. - * @param[out] max_level The maximum transmit power level of the PHY on the - * connection. Values: Range -127 to +20 in dBm. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, - uint8_t phy, - int8_t *current_level, - int8_t *max_level); - -/***************************************************************************//** - * - * Get the transmit power of the remote device on the given connection and PHY. - * The application must include the LE Power Control feature - * (bluetooth_feature_power_control) in order to use this command. Transmit - * power levels are returned in event @ref - * sl_bt_evt_connection_get_remote_tx_power_completed after the operation - * completed. - * - * @param[in] connection Handle of the connection - * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: - * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY - * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY - * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) - * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) - * - * @return SL_STATUS_OK if the command is accepted. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_get_remote_tx_power_completed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, - uint8_t phy); - -/***************************************************************************//** - * - * Set the transmit power of a connection. The application must include - * component bluetooth_feature_user_power_control in order to use this command - * for controlling the transmit power of the connection at application level. - * This command is unavailable if the standard Bluetooth feature LE power - * control (component bluetooth_feature_power_control) is used by the - * application. - * - * The actual selected power level is returned from this command. The value may - * be different than the requested one because of Bluetooth feature restrictions - * or radio characteristics. - * - * @param[in] connection The connection handle - * @param[in] tx_power The requested TX power. Unit: 0.1 dBm - * @param[out] tx_power_out The selected TX power. Unit: 0.1 dBm - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, - int16_t tx_power, - int16_t *tx_power_out); - -/***************************************************************************//** - * - * Read link layer features supported by the remote device. - * - * @param[in] connection Connection Handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_remote_used_features - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection); - -/***************************************************************************//** - * - * Get the security status of the connection. - * - * @param[in] connection Connection handle - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size The size of encryption key - * @param[out] bonding_handle Bonding handle. Values: - * - SL_BT_INVALID_BONDING_HANDLE (0xff): No bonding - * - Other: Bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_security_status(uint8_t connection, - uint8_t *security_mode, - uint8_t *key_size, - uint8_t *bonding_handle); - -/***************************************************************************//** - * - * Request to update the maximum TX payload length and maximum packet TX time of - * a Bluetooth connection. - * - * Event @ref sl_bt_evt_connection_data_length is generated when the data length - * has been changed on the connection. - * - * @param[in] connection Connection handle - * @param[in] tx_data_len @parblock - * Preferred maximum payload octets of a packet that the local Controller will - * send - * - * Range: 27 (0x1B) to 251 (0xFB) - * @endparblock - * @param[in] tx_time_us @parblock - * Preferred maximum TX time in microseconds that the local Controller will - * take to send a packet - * - * Range: 328 (0x0148) to 17040 (0x4290) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_data_length - * - ******************************************************************************/ -sl_status_t sl_bt_connection_set_data_length(uint8_t connection, - uint16_t tx_data_len, - uint16_t tx_time_us); - -/***************************************************************************//** - * - * Read the statistic values collected on the specified connection. The - * application must include component bluetooth_feature_connection_statistics in - * order to use this command. If the component is not included in the - * application this command returns the error SL_STATUS_NOT_AVAILABLE. If this - * command is called before the connection has opened, the command returns the - * error SL_STATUS_NOT_READY. - * - * @param[in] connection The connection handle - * @param[in] reset Reset statistics if parameter value is not zero - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_statistics - Triggered to deliver the statistic - * values of the connection at the time the command was issued. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset); - -/***************************************************************************//** - * - * Get parameters and next connection event scheduling details of a connection. - * Returned values from this command provide the necessary information for - * following the packet transmissions of the connection on an external device. - * Note that the stack cannot ensure a determined timing latency from the time - * when issuing this command to the time when another device starts to follow - * the connection, and the stack cannot guarantee that a scheduled connection - * event will always happen. - * - * @param[in] connection Connection handle - * @param[out] access_address Access address of the connection - * @param[out] role Enum @ref sl_bt_connection_role_t. The role the local device - * operates in the connection. Values: - * - sl_bt_connection_role_peripheral (0x0): The Peripheral role - * - sl_bt_connection_role_central (0x1): The Central role - * @param[out] crc_init The CRC initialization value - * @param[out] interval The connection interval. Time = Value x 1.25 ms - * @param[out] supervision_timeout The connection supervision time. Time = Value - * x 10 ms - * @param[out] central_clock_accuracy The central device's clock accuracy index - * value - * @param[out] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central - * device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the - * Peripheral device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[out] channel_selection_algorithm Enum @ref - * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. - * Values: - * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection - * algorithm #1 - * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection - * algorithm #2 - * @param[out] hop The hop increment when the channel selection algorithm #1 is - * used on the connection. Ignore if @p channel_selection_algorithm indicates - * that the connection uses channel selection algorithm #2. - * @param[out] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Ignore bits 37-39 that are reserved for future use. - * - * A channel is unused when its bit is 0. A channel is used when its bit is 1. - * @endparblock - * @param[out] channel The data channel number that transmissions will use in - * the next connection event - * @param[out] event_counter The event counter of the next connection event - * @param[out] start_time_us Time in microseconds from the PROTIMER tick when - * the next connection event is scheduled to happen - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, - uint32_t *access_address, - uint8_t *role, - uint32_t *crc_init, - uint16_t *interval, - uint16_t *supervision_timeout, - uint8_t *central_clock_accuracy, - uint8_t *central_phy, - uint8_t *peripheral_phy, - uint8_t *channel_selection_algorithm, - uint8_t *hop, - sl_bt_connection_channel_map_t *channel_map, - uint8_t *channel, - uint16_t *event_counter, - uint32_t *start_time_us); - -/***************************************************************************//** - * - * Close a Bluetooth connection gracefully by performing the ACL Termination - * procedure or cancel an ongoing connection establishment process. The - * parameter is a connection handle which is reported in @ref - * sl_bt_evt_connection_opened event or @ref sl_bt_connection_open command - * response. - * - * Disconnecting a connection is an asynchronous operation. The disconnection is - * completed when a @ref sl_bt_evt_connection_closed event for the given - * connection handle is received. To open a new connection to the same remote - * device, wait for the @ref sl_bt_evt_connection_closed event and then initiate - * the connection. - * - * @param[in] connection Handle of the connection to be closed - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_close(uint8_t connection); - -/***************************************************************************//** - * - * Forcefully close a Bluetooth connection without performing the ACL - * Termination procedure. The parameter is a connection handle which is reported - * in @ref sl_bt_evt_connection_opened event or @ref sl_bt_connection_open - * command response. - * - * Closing a connection using this command could result in the observation of - * connection loss or supervision timeout on the remote device. Only use this - * command for special cases, for example, when disconnecting a connection with - * @ref sl_bt_connection_close did not complete in expected time period. - * - * @param[in] connection Handle of the connection to be closed - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_closed - * - ******************************************************************************/ -sl_status_t sl_bt_connection_forcefully_close(uint8_t connection); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref sl_bt_connection_get_median_rssi which - * synchronously returns the value. - * - * Get the latest RSSI value of a Bluetooth connection. The RSSI value will be - * reported in a @ref sl_bt_evt_connection_rssi event if the command returns - * SL_STATUS_OK. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_rssi - Triggered when this command has - * completed. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection); - -/** @} */ // end addtogroup sl_bt_connection - -/** - * @addtogroup sl_bt_gatt GATT Client - * @{ - * - * @brief GATT Client - * - * The commands and events in this class are used to browse and manage - * attributes in a remote GATT server. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gatt_set_max_mtu_id 0x00090020 -#define sl_bt_cmd_gatt_discover_primary_services_id 0x01090020 -#define sl_bt_cmd_gatt_discover_primary_services_by_uuid_id 0x02090020 -#define sl_bt_cmd_gatt_find_included_services_id 0x10090020 -#define sl_bt_cmd_gatt_discover_characteristics_id 0x03090020 -#define sl_bt_cmd_gatt_discover_characteristics_by_uuid_id 0x04090020 -#define sl_bt_cmd_gatt_discover_descriptors_id 0x06090020 -#define sl_bt_cmd_gatt_discover_characteristic_descriptors_id 0x14090020 -#define sl_bt_cmd_gatt_set_characteristic_notification_id 0x05090020 -#define sl_bt_cmd_gatt_send_characteristic_confirmation_id 0x0d090020 -#define sl_bt_cmd_gatt_read_characteristic_value_id 0x07090020 -#define sl_bt_cmd_gatt_read_characteristic_value_from_offset_id 0x12090020 -#define sl_bt_cmd_gatt_read_multiple_characteristic_values_id 0x11090020 -#define sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id 0x08090020 -#define sl_bt_cmd_gatt_write_characteristic_value_id 0x09090020 -#define sl_bt_cmd_gatt_write_characteristic_value_without_response_id 0x0a090020 -#define sl_bt_cmd_gatt_prepare_characteristic_value_write_id 0x0b090020 -#define sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 -#define sl_bt_cmd_gatt_execute_characteristic_value_write_id 0x0c090020 -#define sl_bt_cmd_gatt_read_descriptor_value_id 0x0e090020 -#define sl_bt_cmd_gatt_write_descriptor_value_id 0x0f090020 -#define sl_bt_rsp_gatt_set_max_mtu_id 0x00090020 -#define sl_bt_rsp_gatt_discover_primary_services_id 0x01090020 -#define sl_bt_rsp_gatt_discover_primary_services_by_uuid_id 0x02090020 -#define sl_bt_rsp_gatt_find_included_services_id 0x10090020 -#define sl_bt_rsp_gatt_discover_characteristics_id 0x03090020 -#define sl_bt_rsp_gatt_discover_characteristics_by_uuid_id 0x04090020 -#define sl_bt_rsp_gatt_discover_descriptors_id 0x06090020 -#define sl_bt_rsp_gatt_discover_characteristic_descriptors_id 0x14090020 -#define sl_bt_rsp_gatt_set_characteristic_notification_id 0x05090020 -#define sl_bt_rsp_gatt_send_characteristic_confirmation_id 0x0d090020 -#define sl_bt_rsp_gatt_read_characteristic_value_id 0x07090020 -#define sl_bt_rsp_gatt_read_characteristic_value_from_offset_id 0x12090020 -#define sl_bt_rsp_gatt_read_multiple_characteristic_values_id 0x11090020 -#define sl_bt_rsp_gatt_read_characteristic_value_by_uuid_id 0x08090020 -#define sl_bt_rsp_gatt_write_characteristic_value_id 0x09090020 -#define sl_bt_rsp_gatt_write_characteristic_value_without_response_id 0x0a090020 -#define sl_bt_rsp_gatt_prepare_characteristic_value_write_id 0x0b090020 -#define sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 -#define sl_bt_rsp_gatt_execute_characteristic_value_write_id 0x0c090020 -#define sl_bt_rsp_gatt_read_descriptor_value_id 0x0e090020 -#define sl_bt_rsp_gatt_write_descriptor_value_id 0x0f090020 - -/** - * @brief These values indicate which attribute request or response has caused - * the event. - */ -typedef enum -{ - sl_bt_gatt_read_by_type_request = 0x8, /**< (0x8) Read by type request */ - sl_bt_gatt_read_by_type_response = 0x9, /**< (0x9) Read by type response */ - sl_bt_gatt_read_request = 0xa, /**< (0xa) Read request */ - sl_bt_gatt_read_response = 0xb, /**< (0xb) Read response */ - sl_bt_gatt_read_blob_request = 0xc, /**< (0xc) Read blob request */ - sl_bt_gatt_read_blob_response = 0xd, /**< (0xd) Read blob response */ - sl_bt_gatt_read_multiple_request = 0xe, /**< (0xe) Read multiple request */ - sl_bt_gatt_read_multiple_response = 0xf, /**< (0xf) Read multiple response */ - sl_bt_gatt_write_request = 0x12, /**< (0x12) Write request */ - sl_bt_gatt_write_response = 0x13, /**< (0x13) Write response */ - sl_bt_gatt_write_command = 0x52, /**< (0x52) Write command */ - sl_bt_gatt_prepare_write_request = 0x16, /**< (0x16) Prepare write request */ - sl_bt_gatt_prepare_write_response = 0x17, /**< (0x17) Prepare write - response */ - sl_bt_gatt_execute_write_request = 0x18, /**< (0x18) Execute write request */ - sl_bt_gatt_execute_write_response = 0x19, /**< (0x19) Execute write - response */ - sl_bt_gatt_handle_value_notification = 0x1b, /**< (0x1b) Notification */ - sl_bt_gatt_handle_value_indication = 0x1d /**< (0x1d) Indication */ -} sl_bt_gatt_att_opcode_t; - -/** - * @brief These values define whether the client is to receive notifications or - * indications from a remote GATT server. - */ -typedef enum -{ - sl_bt_gatt_disable = 0x0, /**< (0x0) Disable notifications and - indications */ - sl_bt_gatt_notification = 0x1, /**< (0x1) Notification */ - sl_bt_gatt_indication = 0x2 /**< (0x2) Indication */ -} sl_bt_gatt_client_config_flag_t; - -/** - * @brief These values define whether the GATT server is to cancel all queued - * writes or commit all queued writes to a remote database. - */ -typedef enum -{ - sl_bt_gatt_cancel = 0x0, /**< (0x0) Cancel all queued writes */ - sl_bt_gatt_commit = 0x1 /**< (0x1) Commit all queued writes */ -} sl_bt_gatt_execute_write_flag_t; - -/** - * @addtogroup sl_bt_evt_gatt_mtu_exchanged sl_bt_evt_gatt_mtu_exchanged - * @{ - * @brief Indicates that an ATT_MTU exchange procedure is completed - * - * The @p mtu parameter describes new MTU size. MTU size 23 is used before this - * event is received. - */ - -/** @brief Identifier of the mtu_exchanged event */ -#define sl_bt_evt_gatt_mtu_exchanged_id 0x000900a0 - -/***************************************************************************//** - * @brief Data structure of the mtu_exchanged event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_mtu_exchanged_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t mtu; /**< Exchanged ATT_MTU */ -}); - -typedef struct sl_bt_evt_gatt_mtu_exchanged_s sl_bt_evt_gatt_mtu_exchanged_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_mtu_exchanged - -/** - * @addtogroup sl_bt_evt_gatt_service sl_bt_evt_gatt_service - * @{ - * @brief Indicates that a GATT service in the remote GATT database was - * discovered - * - * This event is generated after issuing either the @ref - * sl_bt_gatt_discover_primary_services or @ref - * sl_bt_gatt_discover_primary_services_by_uuid command. - */ - -/** @brief Identifier of the service event */ -#define sl_bt_evt_gatt_service_id 0x010900a0 - -/***************************************************************************//** - * @brief Data structure of the service event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_service_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t service; /**< GATT service handle */ - uint8array uuid; /**< Service UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_service_s sl_bt_evt_gatt_service_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_service - -/** - * @addtogroup sl_bt_evt_gatt_characteristic sl_bt_evt_gatt_characteristic - * @{ - * @brief Indicates that a GATT characteristic in the remote GATT database was - * discovered - * - * This event is generated after issuing either the @ref - * sl_bt_gatt_discover_characteristics or @ref - * sl_bt_gatt_discover_characteristics_by_uuid command. - */ - -/** @brief Identifier of the characteristic event */ -#define sl_bt_evt_gatt_characteristic_id 0x020900a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle */ - uint8_t properties; /**< Characteristic properties */ - uint8array uuid; /**< Characteristic UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_characteristic_s sl_bt_evt_gatt_characteristic_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic - -/** - * @addtogroup sl_bt_evt_gatt_descriptor sl_bt_evt_gatt_descriptor - * @{ - * @brief Indicates that a GATT characteristic descriptor in the remote GATT - * database was discovered - * - * It is generated after issuing the @ref sl_bt_gatt_discover_descriptors or - * @ref sl_bt_gatt_discover_characteristic_descriptors command. - */ - -/** @brief Identifier of the descriptor event */ -#define sl_bt_evt_gatt_descriptor_id 0x030900a0 - -/***************************************************************************//** - * @brief Data structure of the descriptor event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t descriptor; /**< GATT characteristic descriptor handle */ - uint8array uuid; /**< Descriptor UUID in little endian format */ -}); - -typedef struct sl_bt_evt_gatt_descriptor_s sl_bt_evt_gatt_descriptor_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor - -/** - * @addtogroup sl_bt_evt_gatt_characteristic_value sl_bt_evt_gatt_characteristic_value - * @{ - * @brief Indicates that the value of one or several characteristics in the - * remote GATT server was received - * - * It is triggered by several commands: @ref - * sl_bt_gatt_read_characteristic_value, @ref - * sl_bt_gatt_read_characteristic_value_from_offset, @ref - * sl_bt_gatt_read_characteristic_value_by_uuid, @ref - * sl_bt_gatt_read_multiple_characteristic_values; and when the remote GATT - * server sends indications or notifications after enabling notifications with - * @ref sl_bt_gatt_set_characteristic_notification. The parameter @p att_opcode - * indicates which type of GATT transaction triggered this event. In particular, - * if the @p att_opcode type is @ref sl_bt_gatt_handle_value_indication (0x1d), - * the application needs to confirm the indication with @ref - * sl_bt_gatt_send_characteristic_confirmation. - */ - -/** @brief Identifier of the characteristic_value event */ -#define sl_bt_evt_gatt_characteristic_value_id 0x040900a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode, which indicates the GATT transaction - used. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Characteristic value */ -}); - -typedef struct sl_bt_evt_gatt_characteristic_value_s sl_bt_evt_gatt_characteristic_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic_value - -/** - * @addtogroup sl_bt_evt_gatt_descriptor_value sl_bt_evt_gatt_descriptor_value - * @{ - * @brief Indicates that the value of a descriptor in the remote GATT server was - * received - * - * This event is generated by the @ref sl_bt_gatt_read_descriptor_value command. - */ - -/** @brief Identifier of the descriptor_value event */ -#define sl_bt_evt_gatt_descriptor_value_id 0x050900a0 - -/***************************************************************************//** - * @brief Data structure of the descriptor_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t descriptor; /**< GATT characteristic descriptor handle */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Descriptor value */ -}); - -typedef struct sl_bt_evt_gatt_descriptor_value_s sl_bt_evt_gatt_descriptor_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor_value - -/** - * @addtogroup sl_bt_evt_gatt_procedure_completed sl_bt_evt_gatt_procedure_completed - * @{ - * @brief Indicates that the current GATT procedure was completed successfully - * or that it failed with an error - * - * All GATT commands excluding @ref - * sl_bt_gatt_write_characteristic_value_without_response and @ref - * sl_bt_gatt_send_characteristic_confirmation will trigger this event. As a - * result, the application must wait for this event before issuing another GATT - * command (excluding the two aforementioned exceptions). - * - * Note: After a failed GATT procedure with SL_STATUS_TIMEOUT error, - * further GATT transactions over this connection are not allowed by the stack. - */ - -/** @brief Identifier of the procedure_completed event */ -#define sl_bt_evt_gatt_procedure_completed_id 0x060900a0 - -/***************************************************************************//** - * @brief Data structure of the procedure_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_procedure_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t result; /**< SL_STATUS_OK if successful. Error code otherwise. */ -}); - -typedef struct sl_bt_evt_gatt_procedure_completed_s sl_bt_evt_gatt_procedure_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_procedure_completed - -/***************************************************************************//** - * - * Set the maximum size of ATT Message Transfer Units (MTU). Functionality is - * the same as @ref sl_bt_gatt_server_set_max_mtu and this setting applies to - * both GATT client and server. If the given value is too large according to the - * maximum BGAPI payload size, the system will select the maximum possible value - * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT - * client in the stack will automatically send an MTU exchange request after a - * Bluetooth connection has been established. - * - * @param[in] max_mtu @parblock - * Maximum size of Message Transfer Units (MTU) allowed - * - Range: 23 to 250 - * - * Default: 247 - * @endparblock - * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this - * command succeeds - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out); - -/***************************************************************************//** - * - * Discover all primary services of a remote GATT database. This command - * generates a unique gatt_service event for every discovered primary service. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection); - -/***************************************************************************//** - * - * Discover primary services with the specified UUID in a remote GATT database. - * This command generates unique gatt_service event for every discovered primary - * service. Received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that this GATT procedure was successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Service UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Find the services that are included by a service in a remote GATT database. - * This command generates a unique gatt_service event for each included service. - * The received @ref sl_bt_evt_gatt_procedure_completed event indicates that - * this GATT procedure was successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, - uint32_t service); - -/***************************************************************************//** - * - * Discover all characteristics of a GATT service from a remote GATT database. - * This command generates a unique gatt_characteristic event for every - * discovered characteristic. Received @ref sl_bt_evt_gatt_procedure_completed - * event indicates that this GATT procedure was successfully completed or failed - * with an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from - * remote GATT database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, - uint32_t service); - -/***************************************************************************//** - * - * Discover all characteristics of a GATT service in a remote GATT database - * having the specified UUID. This command generates a unique - * gatt_characteristic event for every discovered characteristic having the - * specified UUID. Received @ref sl_bt_evt_gatt_procedure_completed event - * indicates that this GATT procedure was successfully completed or failed with - * an error. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Characteristic UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from - * remote GATT database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Discover all descriptors in a remote GATT database starting from handle. It - * generates a unique gatt_descriptor event for every discovered descriptor. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, - uint16_t characteristic); - -/***************************************************************************//** - * - * Discover all descriptors of a GATT characteristic in a remote GATT database. - * It generates a unique gatt_descriptor event for every discovered descriptor. - * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this - * GATT procedure has successfully completed or failed with an error. - * - * @param[in] connection Connection handle - * @param[in] start GATT characteristic handle. This value is normally received - * from the gatt_characteristic event. - * @param[in] end GATT characteristic handle. This value is normally received - * from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT - * database. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, - uint16_t start, - uint16_t end); - -/***************************************************************************//** - * - * Enable or disable the notifications and indications sent from a remote GATT - * server. This procedure discovers a characteristic client configuration - * descriptor and writes the related configuration flags to a remote GATT - * database. A received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that this GATT procedure was successfully completed or that it failed with an - * error. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] flags Enum @ref sl_bt_gatt_client_config_flag_t. Characteristic - * client configuration flags. Values: - * - sl_bt_gatt_disable (0x0): Disable notifications and indications - * - sl_bt_gatt_notification (0x1): Notification - * - sl_bt_gatt_indication (0x2): Indication - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - @ref sl_bt_evt_gatt_characteristic_value - If an indication or - * notification has been enabled for a characteristic, this event is - * triggered whenever an indication or notification is sent by the remote - * GATT server. The triggering conditions of the GATT server are defined by - * an upper level, for example by a profile. As a result, it is possible - * that no values are ever received, or that it may take time, depending on - * how the server is configured. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, - uint16_t characteristic, - uint8_t flags); - -/***************************************************************************//** - * - * Send a confirmation to a remote GATT server after receiving a characteristic - * indication. The @ref sl_bt_evt_gatt_characteristic_value event carries the @p - * att_opcode containing @ref sl_bt_gatt_handle_value_indication (0x1d), which - * reveals that an indication has been received and must be confirmed with this - * command. The confirmation needs to be sent within 30 seconds, otherwise - * further GATT transactions are not allowed by the remote side. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection); - -/***************************************************************************//** - * - * Read the value of a characteristic from a remote GATT database. A single @ref - * sl_bt_evt_gatt_characteristic_value is generated if the characteristic value - * fits in one ATT PDU. Otherwise, more than one @ref - * sl_bt_evt_gatt_characteristic_value event is generated because the firmware - * will automatically use the Read Long Characteristic Values procedure. A - * received @ref sl_bt_evt_gatt_procedure_completed event indicates that all - * data was read successfully or that an error response was received. - * - * Note that the GATT client does not verify if the requested attribute is a - * characteristic value. Therefore, before calling this command, ensure that the - * attribute handle is for a characteristic value, for example, by performing - * characteristic discovery. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, - uint16_t characteristic); - -/***************************************************************************//** - * - * Read a partial characteristic value with a specified offset and maximum - * length from a remote GATT database. It is equivalent to @ref - * sl_bt_gatt_read_characteristic_value if both the offset and maximum length - * parameters are 0. A single @ref sl_bt_evt_gatt_characteristic_value event is - * generated if the value to read fits in one ATT PDU. Otherwise, more than one - * @ref sl_bt_evt_gatt_characteristic_value events are generated because the - * firmware will automatically use the Read Long Characteristic Values - * procedure. A received @ref sl_bt_evt_gatt_procedure_completed event indicates - * that all data was read successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] maxlen Maximum bytes to read. If this parameter is 0, all - * characteristic values starting at a given offset will be read. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - uint16_t maxlen); - -/***************************************************************************//** - * - * Read values of multiple characteristics from a remote GATT database at once. - * The GATT server returns values in one ATT PDU as the response. If the total - * set of values is greater than (ATT_MTU - 1) bytes in length, only the first - * (ATT_MTU - 1) bytes are included. A single @ref - * sl_bt_evt_gatt_characteristic_value event is generated, in which the - * characteristic is set to 0 and data in the value parameter is a concatenation - * of characteristic values in the order they were requested. The received @ref - * sl_bt_evt_gatt_procedure_completed event indicates either that this GATT - * procedure was successfully completed or failed with an error. - * - * Use this command only for characteristics values that have a known fixed - * size, except the last one that could have variable length. - * - * When the remote GATT server is from Silicon Labs Bluetooth stack, the server - * returns ATT Invalid PDU (0x04) if this command only reads one characteristic - * value. The server returns ATT Application Error 0x80 if this command reads - * the value of a user-type characteristic. - * - * @param[in] connection Connection handle - * @param[in] characteristic_list_len Length of data in @p characteristic_list - * @param[in] characteristic_list List of uint16 characteristic handles each in - * little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - A concatenation of - * characteristic values in the order they were requested - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was either - * successfully completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, - size_t characteristic_list_len, - const uint8_t* characteristic_list); - -/***************************************************************************//** - * - * Read characteristic values of a service from a remote GATT database by giving - * the UUID of the characteristic and the handle of the service containing this - * characteristic. If multiple characteristic values are received in one ATT - * PDU, one @ref sl_bt_evt_gatt_characteristic_value event is generated for each - * value. If the first characteristic value does not fit in one ATT PDU, the - * firmware automatically uses the Read Long Characteristic Values procedure and - * generate more @ref sl_bt_evt_gatt_characteristic_value events until the value - * has been completely read. A received @ref sl_bt_evt_gatt_procedure_completed - * event indicates that all data was read successfully or that an error response - * was received. - * - * @param[in] connection Connection handle - * @param[in] service GATT service handle. This value is normally received from - * the gatt_service event. - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid Characteristic UUID in little endian format - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a - * characteristic sent by the GATT Server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, - uint32_t service, - size_t uuid_len, - const uint8_t* uuid); - -/***************************************************************************//** - * - * Write the value of a characteristic in a remote GATT database. If the value - * length is greater than (ATT_MTU - 3) and does not fit in one ATT PDU, "write - * long" GATT procedure is used automatically. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that all data was written - * successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Write the value of a characteristic in a remote GATT server. It does not - * generate an event. All failures on the server are ignored silently. For - * example, if an error is generated in the remote GATT server and the given - * value is not written into the database, no error message will be reported to - * the local GATT client. Note that this command can't be used to write long - * values. At most ATT_MTU - 3 number of bytes can be sent once. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Add a characteristic value to the write queue of a remote GATT server. It can - * be used when long attributes need to be written or a set of values needs to - * be written atomically. At most ATT_MTU - 5 number of bytes can be sent at one - * time. Writes are executed or canceled with the @ref - * sl_bt_gatt_execute_characteristic_value_write command. Whether the writes - * succeed or not is indicated in the response of the @ref - * sl_bt_gatt_execute_characteristic_value_write command. - * - * In all use cases where the amount of data to transfer fits into the BGAPI - * payload, use the command @ref sl_bt_gatt_write_characteristic_value to write - * long values because it transparently performs the prepare_write and - * execute_write commands. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] value_len Length of data in @p value - * @param[in] value Value to write into the specified characteristic of the - * remote GATT database - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Add a characteristic value to the write queue of a remote GATT server and - * verify whether the value was correctly received by the server. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that this GATT procedure - * was successfully completed or failed with an error. Specifically, error code - * 0x0194 (data_corrupted) will be returned if the value received from the GATT - * server's response fails to pass the reliable write verification. At most, - * ATT_MTU - 5 number of bytes can be sent at one time. Writes are executed or - * canceled with the @ref sl_bt_gatt_execute_characteristic_value_write command. - * Whether the writes succeed or not is indicated in the response of the @ref - * sl_bt_gatt_execute_characteristic_value_write command. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] offset Offset of the characteristic value - * @param[in] value_len Length of data in @p value - * @param[in] value Value to write into the specified characteristic of the - * remote GATT database - * @param[out] sent_len The length of data sent to the remote GATT server - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, - uint16_t characteristic, - uint16_t offset, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Commit or cancel previously queued writes to a long characteristic of a - * remote GATT server. Writes are sent to the queue with @ref - * sl_bt_gatt_prepare_characteristic_value_write command. Content, offset, and - * length of queued values are validated by this procedure. A received @ref - * sl_bt_evt_gatt_procedure_completed event indicates that all data was written - * successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] flags Enum @ref sl_bt_gatt_execute_write_flag_t. Execute write - * flag. Values: - * - sl_bt_gatt_cancel (0x0): Cancel all queued writes - * - sl_bt_gatt_commit (0x1): Commit all queued writes - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, - uint8_t flags); - -/***************************************************************************//** - * - * Read the descriptor value of a characteristic in a remote GATT database. A - * single @ref sl_bt_evt_gatt_descriptor_value event is generated if the - * descriptor value fits in one ATT PDU. Otherwise, more than one @ref - * sl_bt_evt_gatt_descriptor_value events are generated because the firmware - * automatically uses the Read Long Characteristic Values procedure. A received - * @ref sl_bt_evt_gatt_procedure_completed event indicates that all data was - * read successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] descriptor GATT characteristic descriptor handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_descriptor_value - Descriptor value received from the - * remote GATT server. - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, - uint16_t descriptor); - -/***************************************************************************//** - * - * Write the value of a characteristic descriptor in a remote GATT database. If - * the value length is greater than ATT_MTU - 3 and does not fit in one ATT PDU, - * "write long" GATT procedure is used automatically. Received @ref - * sl_bt_evt_gatt_procedure_completed event indicates either that all data was - * written successfully or that an error response was received. - * - * @param[in] connection Connection handle - * @param[in] descriptor GATT characteristic descriptor handle - * @param[in] value_len Length of data in @p value - * @param[in] value Descriptor value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully - * completed or failed with an error. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, - uint16_t descriptor, - size_t value_len, - const uint8_t* value); - -/** @} */ // end addtogroup sl_bt_gatt - -/** - * @addtogroup sl_bt_gattdb GATT Database - * @{ - * - * @brief GATT Database - * - * These commands and events are used for managing the local GATT database. - * - * Many commands in this class return the handles of created attributes. These - * handles may change during commit if attributes are not created in the order - * they present in the database. For example, when creating a new service using - * the @ref sl_bt_gattdb_add_service command, the service declaration handle - * returned from this command becomes invalid later when an attribute is added - * or removed in front of this service. If the user requires that the attribute - * handles returned from these commands must remain valid after the database - * update has been committed, attributes must be created in the order they - * present in the database. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gattdb_new_session_id 0x00460020 -#define sl_bt_cmd_gattdb_add_service_id 0x01460020 -#define sl_bt_cmd_gattdb_remove_service_id 0x02460020 -#define sl_bt_cmd_gattdb_add_included_service_id 0x03460020 -#define sl_bt_cmd_gattdb_remove_included_service_id 0x04460020 -#define sl_bt_cmd_gattdb_add_uuid16_characteristic_id 0x05460020 -#define sl_bt_cmd_gattdb_add_uuid128_characteristic_id 0x06460020 -#define sl_bt_cmd_gattdb_remove_characteristic_id 0x07460020 -#define sl_bt_cmd_gattdb_add_uuid16_descriptor_id 0x08460020 -#define sl_bt_cmd_gattdb_add_uuid128_descriptor_id 0x09460020 -#define sl_bt_cmd_gattdb_remove_descriptor_id 0x0a460020 -#define sl_bt_cmd_gattdb_start_service_id 0x0b460020 -#define sl_bt_cmd_gattdb_stop_service_id 0x0c460020 -#define sl_bt_cmd_gattdb_start_characteristic_id 0x0d460020 -#define sl_bt_cmd_gattdb_stop_characteristic_id 0x0e460020 -#define sl_bt_cmd_gattdb_commit_id 0x0f460020 -#define sl_bt_cmd_gattdb_abort_id 0x10460020 -#define sl_bt_rsp_gattdb_new_session_id 0x00460020 -#define sl_bt_rsp_gattdb_add_service_id 0x01460020 -#define sl_bt_rsp_gattdb_remove_service_id 0x02460020 -#define sl_bt_rsp_gattdb_add_included_service_id 0x03460020 -#define sl_bt_rsp_gattdb_remove_included_service_id 0x04460020 -#define sl_bt_rsp_gattdb_add_uuid16_characteristic_id 0x05460020 -#define sl_bt_rsp_gattdb_add_uuid128_characteristic_id 0x06460020 -#define sl_bt_rsp_gattdb_remove_characteristic_id 0x07460020 -#define sl_bt_rsp_gattdb_add_uuid16_descriptor_id 0x08460020 -#define sl_bt_rsp_gattdb_add_uuid128_descriptor_id 0x09460020 -#define sl_bt_rsp_gattdb_remove_descriptor_id 0x0a460020 -#define sl_bt_rsp_gattdb_start_service_id 0x0b460020 -#define sl_bt_rsp_gattdb_stop_service_id 0x0c460020 -#define sl_bt_rsp_gattdb_start_characteristic_id 0x0d460020 -#define sl_bt_rsp_gattdb_stop_characteristic_id 0x0e460020 -#define sl_bt_rsp_gattdb_commit_id 0x0f460020 -#define sl_bt_rsp_gattdb_abort_id 0x10460020 - -/** - * @brief This enum defines GATT service types. - */ -typedef enum -{ - sl_bt_gattdb_primary_service = 0x0, /**< (0x0) Primary service */ - sl_bt_gattdb_secondary_service = 0x1 /**< (0x1) Secondary service */ -} sl_bt_gattdb_service_type_t; - -/** - * @brief This enum defines characteristic and descriptor value types. - */ -typedef enum -{ - sl_bt_gattdb_fixed_length_value = 0x1, /**< (0x1) A fixed-length value - managed by the local GATT - server for responding the read - and write requests of remote - GATT clients */ - sl_bt_gattdb_variable_length_value = 0x2, /**< (0x2) A variable-length value - managed by the local GATT - server for responding the read - and write requests of remote - GATT clients */ - sl_bt_gattdb_user_managed_value = 0x3 /**< (0x3) A value managed by the - user application for responding - the read and write requests of - remote GATT clients. */ -} sl_bt_gattdb_value_type_t; - -/** - * @addtogroup sl_bt_gattdb_service_property_flags GATT Service Property Flags - * @{ - * - * This enum defines GATT service property flags. - */ - -/** The service should be advertised. */ -#define SL_BT_GATTDB_ADVERTISED_SERVICE 0x1 - -/** @} */ // end GATT Service Property Flags - -/** - * @addtogroup sl_bt_gattdb_security_requirements GATT Attribute Security Requirement Flags - * @{ - * - * This enum defines the security requirement flags for GATT characteristic - * value properties. - */ - -/** The read property requires pairing and encrypted connection. */ -#define SL_BT_GATTDB_ENCRYPTED_READ 0x1 - -/** The read property requires bonding and encrypted connection. */ -#define SL_BT_GATTDB_BONDED_READ 0x2 - -/** The read property requires authenticated pairing and encrypted connection. - * */ -#define SL_BT_GATTDB_AUTHENTICATED_READ 0x4 - -/** The write property requires pairing and encrypted connection. */ -#define SL_BT_GATTDB_ENCRYPTED_WRITE 0x8 - -/** The write property requires bonding and encrypted connection. */ -#define SL_BT_GATTDB_BONDED_WRITE 0x10 - -/** The write property requires authenticated pairing and encrypted connection. - * */ -#define SL_BT_GATTDB_AUTHENTICATED_WRITE 0x20 - -/** The notification and indication properties require pairing and encrypted - * connection. */ -#define SL_BT_GATTDB_ENCRYPTED_NOTIFY 0x40 - -/** The notification and indication properties require bonding and encrypted - * connection. */ -#define SL_BT_GATTDB_BONDED_NOTIFY 0x80 - -/** The notification and indication properties require authenticated pairing and - * encrypted connection. */ -#define SL_BT_GATTDB_AUTHENTICATED_NOTIFY 0x100 - -/** @} */ // end GATT Attribute Security Requirement Flags - -/** - * @addtogroup sl_bt_gattdb_flags GATT Database Flags - * @{ - * - * This enum defines the options of GATT attribute management. - */ - -/** Do not automatically create a Client Characteristic Configuration descriptor - * when adding a characteristic that has the notify or indicate property. */ -#define SL_BT_GATTDB_NO_AUTO_CCCD 0x1 - -/** @} */ // end GATT Database Flags - -/** - * @addtogroup sl_bt_gattdb_characteristic_properties GATT Characteristic Property Flags - * @{ - * - * This enum defines the property flags for GATT characteristic values. Lower - * byte is Characteristic Properties and higher byte is Characteristic Extended - * Properties. - */ - -/** A GATT client can read the characteristic value. */ -#define SL_BT_GATTDB_CHARACTERISTIC_READ 0x2 - -/** A GATT client can write the characteristic value without a response. */ -#define SL_BT_GATTDB_CHARACTERISTIC_WRITE_NO_RESPONSE 0x4 - -/** A GATT client can write the characteristic value. */ -#define SL_BT_GATTDB_CHARACTERISTIC_WRITE 0x8 - -/** The characteristic value can be notified without acknowledgment. */ -#define SL_BT_GATTDB_CHARACTERISTIC_NOTIFY 0x10 - -/** The characteristic value can be notified with acknowledgment. */ -#define SL_BT_GATTDB_CHARACTERISTIC_INDICATE 0x20 - -/** The additional characteristic properties are defined. */ -#define SL_BT_GATTDB_CHARACTERISTIC_EXTENDED_PROPS 0x80 - -/** The characteristic value supports reliable write. */ -#define SL_BT_GATTDB_CHARACTERISTIC_RELIABLE_WRITE 0x101 - -/** @} */ // end GATT Characteristic Property Flags - -/** - * @addtogroup sl_bt_gattdb_descriptor_properties GATT Descriptor Property Flags - * @{ - * - * This enum defines the property flags for GATT characteristic descriptors. - */ - -/** A GATT client can read the descriptor value. */ -#define SL_BT_GATTDB_DESCRIPTOR_READ 0x1 - -/** A GATT client can write the descriptor value. */ -#define SL_BT_GATTDB_DESCRIPTOR_WRITE 0x2 - -/** The descriptor is local only and should be invisible to GATT clients. */ -#define SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY 0x200 - -/** @} */ // end GATT Descriptor Property Flags - -/***************************************************************************//** - * - * Start a new GATT database update session. If the operation is successful, the - * Bluetooth stack returns a session ID, with which the GATT database can be - * updated by calling other database management APIs of this class. Changes in - * the database are not immediately saved. Unsaved changes are invisible to a - * connected remote GATT client. - * - * After all changes were performed successfully, commit the changes using the - * @ref sl_bt_gattdb_commit command. The Bluetooth stack will save the changes - * and handle GATT caching as needed. Unsaved database changes can also be - * canceled by calling the @ref sl_bt_gattdb_abort command. In either case, - * after a commit or abort command is called, the current session is closed and - * the session ID becomes invalid. - * - * Only one session is allowed at a time. Error SL_STATUS_ALREADY_EXISTS is - * returned if another session has been started already. - * - * @param[out] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_new_session(uint16_t *session); - -/***************************************************************************//** - * - * Add a service into the local GATT database. When successful, the service is - * appended to the service list and is in stopped state. Use @ref - * sl_bt_gattdb_start_service command to set it visible to remote GATT clients. - * - * You are not allowed to add the Generic Attribute Profile service. If the - * application needs GATT caching, enable the feature in the configuration of - * this component and the GATT server will handle GATT caching according to the - * procedures specified by the Bluetooth core specification. - * - * @param[in] session The database update session ID - * @param[in] type Enum @ref sl_bt_gattdb_service_type_t. The service type. - * Values: - * - sl_bt_gattdb_primary_service (0x0): Primary service - * - sl_bt_gattdb_secondary_service (0x1): Secondary service - * @param[in] property Service properties. Value: 0 or bit flag @ref - * SL_BT_GATTDB_ADVERTISED_SERVICE - * @param[in] uuid_len Length of data in @p uuid - * @param[in] uuid The service UUID in little endian format - * @param[out] service The service declaration attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_service(uint16_t session, - uint8_t type, - uint8_t property, - size_t uuid_len, - const uint8_t* uuid, - uint16_t *service); - -/***************************************************************************//** - * - * Remove a service and its characteristics from the local GATT database. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Add an included-service attribute to a service. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the included-service attribute is added to - * @param[in] included_service The service declaration attribute handle of the - * service to be included - * @param[out] attribute The included-service attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, - uint16_t service, - uint16_t included_service, - uint16_t *attribute); - -/***************************************************************************//** - * - * Remove an included-service attribute from a service. - * - * @param[in] session The database update session ID - * @param[in] attribute The included-service attribute handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, - uint16_t attribute); - -/***************************************************************************//** - * - * Add a 16-bits UUID characteristic to a service. On success, the - * characteristic is appended to the characteristic list of the service and it - * inherits the started or stopped state of the service. In addition, it can be - * started and stopped separately with the @ref - * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic - * commands. - * - * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the - * stack will automatically add a Client Characteristic Configuration descriptor - * to this characteristic when it has the notify or indicate property. If @ref - * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the - * descriptor separately as needed. - * - * A Characteristic Extended Properties descriptor is automatically added if the - * reliable write property is set. - * - * Use the @ref sl_bt_gattdb_add_uuid128_characteristic command to add a - * 128-bits UUID characteristic. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the characteristic is added to - * @param[in] property Characteristic value properties. Value: bitmask of @ref - * sl_bt_gattdb_characteristic_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the characteristic - * value. - * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. - * @param[in] uuid The 16-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the characteristic value. Ignored if - * @p value_type is @ref sl_bt_gattdb_user_managed_value. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial characteristic value. Length of this value must - * be less than or equal to @p maxlen. Ignored if @p value_type is @ref - * sl_bt_gattdb_user_managed_value. - * @param[out] characteristic The characteristic value attribute handle. This - * handle is ensured valid in current session. It may change after the session - * if attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic); - -/***************************************************************************//** - * - * Add a 128-bits UUID characteristic to a service. When successful, the - * characteristic is appended to the characteristic list of the service and - * inherits the started or stopped state of the service. Additionally, it can be - * started and stopped separately with the @ref - * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic - * commands. - * - * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the - * stack will automatically add a Client Characteristic Configuration descriptor - * to this characteristic when it has the notify or indicate property. If @ref - * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the - * descriptor separately as needed. - * - * A Characteristic Extended Properties descriptor is automatically added if the - * reliable write property is set. - * - * Use the @ref sl_bt_gattdb_add_uuid16_characteristic command to add a 16-bits - * UUID characteristic. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * which the characteristic is added to - * @param[in] property Characteristic value properties. Value: bitmask of @ref - * sl_bt_gattdb_characteristic_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the characteristic - * value. - * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. - * @param[in] uuid The 128-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the characteristic value. Ignored if - * @p value_type is @ref sl_bt_gattdb_user_managed_value. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial characteristic value. Length of this value must - * be less than or equal to @p maxlen. Ignored if @p value_type is @ref - * sl_bt_gattdb_user_managed_value. - * @param[out] characteristic The characteristic value attribute handle. This - * handle is ensured valid in current session. It may change after the session - * if attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, - uint16_t service, - uint16_t property, - uint16_t security, - uint8_t flag, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *characteristic); - -/***************************************************************************//** - * - * Remove a characteristic and its descriptors from a service. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Add a 16-bits UUID descriptor to a characteristic. When successful, the - * descriptor is appended to the descriptor list of the characteristic and - * inherits the started or stopped state of the characteristic. - * - * This command does not support adding Characteristic Extended Properties - * descriptors. This descriptor is automatically added if the characteristic - * value has the reliable-write property or when a Characteristic User - * Description descriptor is added and the user description has the write - * property. - * - * Use the @ref sl_bt_gattdb_add_uuid128_descriptor command to add a 128-bits - * UUID descriptor. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic the descriptor is added to - * @param[in] property The descriptor properties. Value: bitmask of @ref - * sl_bt_gattdb_descriptor_properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the descriptor. - * @param[in] uuid The 16-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Ignored if this is a Client Characteristic Configuration descriptor. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p - * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client - * Characteristic Configuration descriptor. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial descriptor value. Length of this value must be - * less than or equal to @p maxlen. Ingored if value type is @ref - * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic - * Configuration descriptor. - * @param[out] descriptor The descriptor attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - sl_bt_uuid_16_t uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor); - -/***************************************************************************//** - * - * Add a 128-bits UUID descriptor to a characteristic. When successful, the - * descriptor is appended to the descriptor list of the characteristic and - * inherits the started or stopped state of the characteristic. - * - * This command does not support adding Characteristic Extended Properties - * descriptors. This descriptor is automatically added if the characteristic - * value has the reliable-write property or when a Characteristic User - * Description descriptor is added and the user description has the write - * property. - * - * Use the @ref sl_bt_gattdb_add_uuid16_descriptor command to add a 16-bits UUID - * descriptor. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic the descriptor is added to - * @param[in] property Bitmask of characteristic descriptor properties - * @param[in] security Security requirement. Value: 0 or bitmask of @ref - * sl_bt_gattdb_security_requirements. A security requirement flag for a - * property is ignored if the property is not set for the descriptor. - * @param[in] uuid The 128-bits UUID in little endian format - * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. - * Ignored if this is a Client Characteristic Configuration descriptor. - * Values: - * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value - * managed by the local GATT server for responding the read and write - * requests of remote GATT clients - * - sl_bt_gattdb_variable_length_value (0x2): A variable-length - * value managed by the local GATT server for responding the read and - * write requests of remote GATT clients - * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the - * user application for responding the read and write requests of remote - * GATT clients. - * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p - * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client - * Characteristic Configuration descriptor. - * @param[in] value_len Length of data in @p value - * @param[in] value The initial descriptor value. Length of this value must be - * less than or equal to @p maxlen. Ignored if value type is @ref - * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic - * Configuration descriptor. - * @param[out] descriptor The descriptor attribute handle. This handle is - * ensured valid in current session. It may change after the session if - * attributes have been inserted or deleted in front of it. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, - uint16_t characteristic, - uint16_t property, - uint16_t security, - uuid_128 uuid, - uint8_t value_type, - uint16_t maxlen, - size_t value_len, - const uint8_t* value, - uint16_t *descriptor); - -/***************************************************************************//** - * - * Remove a descriptor from a characteristic. - * - * @param[in] session The database update session ID - * @param[in] descriptor The descriptor handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, - uint16_t descriptor); - -/***************************************************************************//** - * - * Start a service, so that the service and its attributes including - * characteristics and descriptors become visible to remote GATT clients after - * this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Stop a service, so that the service and its attributes including - * characteristics and descriptors become invisible to remote GATT clients after - * this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] service The service declaration attribute handle of the service - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service); - -/***************************************************************************//** - * - * Start a characteristic, so that the characteristic and its attributes become - * visible to remote GATT clients after this change has been committed. - * SL_STATUS_INVALID_STATE error is returned if the parent service is not - * started. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Stop a characteristic, so that the characteristic and its attributes become - * invisible to remote GATT clients after this change has been committed. - * - * @param[in] session The database update session ID - * @param[in] characteristic The characteristic value attribute handle of the - * characteristic - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, - uint16_t characteristic); - -/***************************************************************************//** - * - * Save all changes performed in the current session and close the session. The - * stack will assign final handles to new and affected attributes and handle - * GATT caching as needed. The stack removes the client characteristic - * configurations of non-connected GATT clients except the service-changed - * configuration. For connected GATT clients during this database change, the - * stack removes the configurations to the removed characteristics. The session - * ID, temporary attribute handles returned during this session, and other - * existing attribute handles that are after newly added or removed attributes - * are invalidated. - * - * Some attribute handles returned in this session may become invalid if - * attributes are not created in the order they present in the database. In this - * case, attribute handle cache of the database in the user application must be - * refreshed to avoid accidentally using an invalidated handle in subsequent - * operations. - * - * @param[in] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_commit(uint16_t session); - -/***************************************************************************//** - * - * Cancel all changes performed in the current session and close the session. - * The database remains in the same state it was in just before the session was - * started. The session ID and all temporary attribute handles returned during - * this session are invalidated. - * - * @param[in] session The database update session ID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gattdb_abort(uint16_t session); - -/** @} */ // end addtogroup sl_bt_gattdb - -/** - * @addtogroup sl_bt_gatt_server GATT Server - * @{ - * - * @brief GATT Server - * - * These commands and events are used for accessing to the local GATT server and - * database. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_gatt_server_set_max_mtu_id 0x0a0a0020 -#define sl_bt_cmd_gatt_server_get_mtu_id 0x0b0a0020 -#define sl_bt_cmd_gatt_server_find_attribute_id 0x060a0020 -#define sl_bt_cmd_gatt_server_read_attribute_value_id 0x000a0020 -#define sl_bt_cmd_gatt_server_read_attribute_type_id 0x010a0020 -#define sl_bt_cmd_gatt_server_write_attribute_value_id 0x020a0020 -#define sl_bt_cmd_gatt_server_send_user_read_response_id 0x030a0020 -#define sl_bt_cmd_gatt_server_send_user_write_response_id 0x040a0020 -#define sl_bt_cmd_gatt_server_send_notification_id 0x0f0a0020 -#define sl_bt_cmd_gatt_server_send_indication_id 0x100a0020 -#define sl_bt_cmd_gatt_server_notify_all_id 0x110a0020 -#define sl_bt_cmd_gatt_server_read_client_configuration_id 0x120a0020 -#define sl_bt_cmd_gatt_server_send_user_prepare_write_response_id 0x140a0020 -#define sl_bt_cmd_gatt_server_set_capabilities_id 0x080a0020 -#define sl_bt_cmd_gatt_server_enable_capabilities_id 0x0c0a0020 -#define sl_bt_cmd_gatt_server_disable_capabilities_id 0x0d0a0020 -#define sl_bt_cmd_gatt_server_get_enabled_capabilities_id 0x0e0a0020 -#define sl_bt_cmd_gatt_server_read_client_supported_features_id 0x150a0020 -#define sl_bt_rsp_gatt_server_set_max_mtu_id 0x0a0a0020 -#define sl_bt_rsp_gatt_server_get_mtu_id 0x0b0a0020 -#define sl_bt_rsp_gatt_server_find_attribute_id 0x060a0020 -#define sl_bt_rsp_gatt_server_read_attribute_value_id 0x000a0020 -#define sl_bt_rsp_gatt_server_read_attribute_type_id 0x010a0020 -#define sl_bt_rsp_gatt_server_write_attribute_value_id 0x020a0020 -#define sl_bt_rsp_gatt_server_send_user_read_response_id 0x030a0020 -#define sl_bt_rsp_gatt_server_send_user_write_response_id 0x040a0020 -#define sl_bt_rsp_gatt_server_send_notification_id 0x0f0a0020 -#define sl_bt_rsp_gatt_server_send_indication_id 0x100a0020 -#define sl_bt_rsp_gatt_server_notify_all_id 0x110a0020 -#define sl_bt_rsp_gatt_server_read_client_configuration_id 0x120a0020 -#define sl_bt_rsp_gatt_server_send_user_prepare_write_response_id 0x140a0020 -#define sl_bt_rsp_gatt_server_set_capabilities_id 0x080a0020 -#define sl_bt_rsp_gatt_server_enable_capabilities_id 0x0c0a0020 -#define sl_bt_rsp_gatt_server_disable_capabilities_id 0x0d0a0020 -#define sl_bt_rsp_gatt_server_get_enabled_capabilities_id 0x0e0a0020 -#define sl_bt_rsp_gatt_server_read_client_supported_features_id 0x150a0020 - -/** - * @brief These values define whether the server is to sent notifications or - * indications to a remote GATT server. - */ -typedef enum -{ - sl_bt_gatt_server_disable = 0x0, /**< (0x0) Disable - notifications and - indications. */ - sl_bt_gatt_server_notification = 0x1, /**< (0x1) The - characteristic value - shall be notified. */ - sl_bt_gatt_server_indication = 0x2, /**< (0x2) The - characteristic value - shall be indicated. */ - sl_bt_gatt_server_notification_and_indication = 0x3 /**< (0x3) The - characteristic value - notification and - indication are - enabled, application - decides which one to - send. */ -} sl_bt_gatt_server_client_configuration_t; - -/** - * @brief These values describe whether the characteristic client configuration - * was changed or whether a characteristic confirmation was received. - */ -typedef enum -{ - sl_bt_gatt_server_client_config = 0x1, /**< (0x1) Characteristic client - configuration has been changed. */ - sl_bt_gatt_server_confirmation = 0x2 /**< (0x2) Characteristic confirmation - has been received. */ -} sl_bt_gatt_server_characteristic_status_flag_t; - -/** - * @addtogroup sl_bt_evt_gatt_server_attribute_value sl_bt_evt_gatt_server_attribute_value - * @{ - * @brief Indicates that the value of an attribute in the local GATT database - * was changed by a remote GATT client - * - * The parameter @p att_opcode describes which GATT procedure was used to change - * the value. - */ - -/** @brief Identifier of the attribute_value event */ -#define sl_bt_evt_gatt_server_attribute_value_id 0x000a00a0 - -/***************************************************************************//** - * @brief Data structure of the attribute_value event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_attribute_value_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t attribute; /**< Attribute Handle */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which the - value was received. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Value */ -}); - -typedef struct sl_bt_evt_gatt_server_attribute_value_s sl_bt_evt_gatt_server_attribute_value_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_attribute_value - -/** - * @addtogroup sl_bt_evt_gatt_server_user_read_request sl_bt_evt_gatt_server_user_read_request - * @{ - * @brief Indicates that a remote GATT client is attempting to read a value of - * an attribute from the local GATT database, where the attribute was defined in - * the GATT database XML file to have the type="user" - * - * The parameter @p att_opcode informs which GATT procedure was used to read the - * value. The application needs to respond to this request by using the @ref - * sl_bt_gatt_server_send_user_read_response command within 30 seconds, - * otherwise further GATT transactions are not allowed by the remote side. - */ - -/** @brief Identifier of the user_read_request event */ -#define sl_bt_evt_gatt_server_user_read_request_id 0x010a00a0 - -/***************************************************************************//** - * @brief Data structure of the user_read_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_user_read_request_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which the - value was received. */ - uint16_t offset; /**< Value offset */ -}); - -typedef struct sl_bt_evt_gatt_server_user_read_request_s sl_bt_evt_gatt_server_user_read_request_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_read_request - -/** - * @addtogroup sl_bt_evt_gatt_server_user_write_request sl_bt_evt_gatt_server_user_write_request - * @{ - * @brief Indicates that a remote GATT client is attempting to write a value of - * an attribute into the local GATT database, where the attribute was defined in - * the GATT database XML file to have the type="user" - * - * The parameter @p att_opcode informs which attribute procedure was used to - * write the value. If the @p att_opcode is @ref sl_bt_gatt_write_request (see - * @ref sl_bt_gatt_att_opcode_t), the application needs to respond to this - * request by using the @ref sl_bt_gatt_server_send_user_write_response command - * within 30 seconds, otherwise further GATT transactions are not allowed by the - * remote side. If the @p att_opcode is @ref sl_bt_gatt_prepare_write_request, - * the application needs to respond to this request by using the @ref - * sl_bt_gatt_server_send_user_prepare_write_response command within 30 seconds, - * otherwise further GATT transactions are not allowed by the remote side. If - * the value of @p att_opcode is @ref sl_bt_gatt_execute_write_request, it - * indicates that there was one or more prepare writes earlier and now the GATT - * server is processing the execute write, the value of @p characteristic is set - * to 0 and should be ignored. The event @ref - * sl_bt_evt_gatt_server_execute_write_completed will be emitted after - * responding to @ref sl_bt_gatt_execute_write_request by using @ref - * sl_bt_gatt_server_send_user_write_response. - */ - -/** @brief Identifier of the user_write_request event */ -#define sl_bt_evt_gatt_server_user_write_request_id 0x020a00a0 - -/***************************************************************************//** - * @brief Data structure of the user_write_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_user_write_request_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the gatt_characteristic - event. */ - uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute - opcode that informs the procedure from which - the value was received. */ - uint16_t offset; /**< Value offset */ - uint8array value; /**< Value */ -}); - -typedef struct sl_bt_evt_gatt_server_user_write_request_s sl_bt_evt_gatt_server_user_write_request_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_write_request - -/** - * @addtogroup sl_bt_evt_gatt_server_characteristic_status sl_bt_evt_gatt_server_characteristic_status - * @{ - * @brief Indicates either that a local Client Characteristic Configuration - * descriptor was changed by the remote GATT client, or that a confirmation from - * the remote GATT client was received upon a successful reception of the - * indication - * - * A confirmation by the remote GATT client should be received within 30 seconds - * after an indication was sent with the @ref sl_bt_gatt_server_send_indication - * command, otherwise further GATT transactions over this connection are not - * allowed by the stack. - */ - -/** @brief Identifier of the characteristic_status event */ -#define sl_bt_evt_gatt_server_characteristic_status_id 0x030a00a0 - -/***************************************************************************//** - * @brief Data structure of the characteristic_status event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_characteristic_status_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t characteristic; /**< GATT characteristic handle. This value is - normally received from the - gatt_characteristic event. */ - uint8_t status_flags; /**< Enum @ref - sl_bt_gatt_server_characteristic_status_flag_t. - Describes whether Client Characteristic - Configuration was changed or if a - confirmation was received. Values: - - sl_bt_gatt_server_client_config - (0x1): Characteristic client - configuration has been changed. - - sl_bt_gatt_server_confirmation - (0x2): Characteristic confirmation - has been received. */ - uint16_t client_config_flags; /**< Enum @ref - sl_bt_gatt_server_client_configuration_t. - This field carries the new value of the - Client Characteristic Configuration. If the - status_flags is 0x2 (confirmation - received), the value of this field can be - ignored. */ - uint16_t client_config; /**< The handle of client-config descriptor. */ -}); - -typedef struct sl_bt_evt_gatt_server_characteristic_status_s sl_bt_evt_gatt_server_characteristic_status_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_characteristic_status - -/** - * @addtogroup sl_bt_evt_gatt_server_execute_write_completed sl_bt_evt_gatt_server_execute_write_completed - * @{ - * @brief Indicates that the execute write command from a remote GATT client has - * completed with the given result - */ - -/** @brief Identifier of the execute_write_completed event */ -#define sl_bt_evt_gatt_server_execute_write_completed_id 0x040a00a0 - -/***************************************************************************//** - * @brief Data structure of the execute_write_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_execute_write_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t result; /**< Execute write result */ -}); - -typedef struct sl_bt_evt_gatt_server_execute_write_completed_s sl_bt_evt_gatt_server_execute_write_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_execute_write_completed - -/** - * @addtogroup sl_bt_evt_gatt_server_indication_timeout sl_bt_evt_gatt_server_indication_timeout - * @{ - * @brief Indicates confirmation from the remote GATT client has not been - * received within 30 seconds after an indication was sent - * - * Furthermore, the stack does not allow GATT transactions over this connection. - */ - -/** @brief Identifier of the indication_timeout event */ -#define sl_bt_evt_gatt_server_indication_timeout_id 0x050a00a0 - -/***************************************************************************//** - * @brief Data structure of the indication_timeout event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_indication_timeout_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_gatt_server_indication_timeout_s sl_bt_evt_gatt_server_indication_timeout_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_indication_timeout - -/** - * @addtogroup sl_bt_evt_gatt_server_notification_tx_completed sl_bt_evt_gatt_server_notification_tx_completed - * @{ - * @brief Indicates that one or more GATT notifications have been transmitted. - * - * By default, this event is not enabled on Bluetooth connections due to - * additional resource usages - * - * Following enablers are required to enable the Bluetooth stack's functionality - * for supporting this event, - * - Include feature bluetooth_feature_resource_report in the application - * project. - * - Use command @ref sl_bt_resource_enable_connection_tx_report to enable - * data packet TX status reports before this Bluetooth connection is - * established. - */ - -/** @brief Identifier of the notification_tx_completed event */ -#define sl_bt_evt_gatt_server_notification_tx_completed_id 0x060a00a0 - -/***************************************************************************//** - * @brief Data structure of the notification_tx_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_gatt_server_notification_tx_completed_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t count; /**< Number of notifications that have been transmitted */ -}); - -typedef struct sl_bt_evt_gatt_server_notification_tx_completed_s sl_bt_evt_gatt_server_notification_tx_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_gatt_server_notification_tx_completed - -/***************************************************************************//** - * - * Set the maximum size of ATT Message Transfer Units (MTU). The functionality - * is the same as @ref sl_bt_gatt_set_max_mtu and this setting applies to both - * GATT client and server. If the given value is too large according to the - * maximum BGAPI payload size, the system will select the maximum possible value - * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT - * client in the stack will automatically send an MTU exchange request after a - * Bluetooth connection was established. - * - * @param[in] max_mtu @parblock - * Maximum size of Message Transfer Units (MTU) allowed - * - Range: 23 to 250 - * - * Default: 247 - * @endparblock - * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this - * command succeeded - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, - uint16_t *max_mtu_out); - -/***************************************************************************//** - * - * Get the size of ATT Message Transfer Units (MTU) for a connection. - * - * @param[in] connection Connection handle - * @param[out] mtu The maximum ATT_MTU used by the connection - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu); - -/***************************************************************************//** - * - * Find attributes of a certain type from a local GATT database. The type is - * usually given as a 16-bit or 128-bit UUID in little endian format. - * - * @param[in] start Search start handle - * @param[in] type_len Length of data in @p type - * @param[in] type The attribute type UUID - * @param[out] attribute Attribute handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, - size_t type_len, - const uint8_t* type, - uint16_t *attribute); - -/***************************************************************************//** - * - * Read the value of an attribute from a local GATT database. Only (maximum - * BGAPI payload size - 3) amount of data can be read at once. The application - * can continue reading with increased offset value if it receives (maximum - * BGAPI payload size - 3) number of bytes. - * - * @param[in] attribute Attribute handle - * @param[in] offset Value offset - * @param[in] max_value_size Size of output buffer passed in @p value - * @param[out] value_len On return, set to the length of output data written to - * @p value - * @param[out] value The attribute value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, - uint16_t offset, - size_t max_value_size, - size_t *value_len, - uint8_t *value); - -/***************************************************************************//** - * - * Read the type of an attribute from a local GATT database. The type is a UUID, - * usually 16 or 128 bits long in little endian format. - * - * @param[in] attribute Attribute handle - * @param[in] max_type_size Size of output buffer passed in @p type - * @param[out] type_len On return, set to the length of output data written to - * @p type - * @param[out] type The attribute type UUID - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, - size_t max_type_size, - size_t *type_len, - uint8_t *type); - -/***************************************************************************//** - * - * Write the value of an attribute in the local GATT database. Writing the value - * of a characteristic of the local GATT database will not trigger notifications - * or indications to the remote GATT client if the characteristic has a property - * to indicate or notify and the client has enabled notification or indication. - * Notifications and indications are sent to the remote GATT client using @ref - * sl_bt_gatt_server_send_notification or @ref sl_bt_gatt_server_send_indication - * commands. - * - * @param[in] attribute Attribute handle - * @param[in] offset Value offset - * @param[in] value_len Length of data in @p value - * @param[in] value Value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, - uint16_t offset, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_read_request event. The - * response needs to be sent within 30 seconds, otherwise no more GATT - * transactions are allowed by the remote side. If attr_errorcode is set to 0, - * the characteristic value is sent to the remote GATT client in the standard - * way. Other attr_errorcode values will cause the local GATT server to send an - * attribute protocol error response instead of the actual data. Maximum number - * of bytes this command can send depends on the value of parameter att_opcode - * in @ref sl_bt_evt_gatt_server_user_read_request event: - * - ATT_MTU - 1 if the opcode is @ref sl_bt_gatt_read_request or @ref - * sl_bt_gatt_read_blob_request - * - ATT_MTU - 4 if the opcode is @ref sl_bt_gatt_read_by_type_request - * - * If the data length in @p value exceeds the limit, the first maximum number of - * bytes will be sent and rest data is ignored. The actual number of bytes that - * was sent is retruned in the response of this command. - * - * The client will continue reading by sending a new read blob request with an - * increased offset value if it receives the maximum amount of attribute data - * the read respond packet can contain. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle received in the @ref - * sl_bt_evt_gatt_server_user_read_request event. - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * @param[in] value_len Length of data in @p value - * @param[in] value Characteristic value to send to the GATT client. Ignored if - * att_errorcode is not 0. - * @param[out] sent_len The length of data sent to the remote GATT client - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - size_t value_len, - const uint8_t* value, - uint16_t *sent_len); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when - * parameter @p att_opcode in the event is @ref sl_bt_gatt_write_request or @ref - * sl_bt_gatt_execute_write_request (see @ref sl_bt_gatt_att_opcode_t). The - * response needs to be sent within 30 seconds, otherwise no more GATT - * transactions are allowed by the remote side. When responding to @ref - * sl_bt_gatt_execute_write_request, the value of parameter @p characteristic is - * ignored. If attr_errorcode is set to 0, the ATT protocol's write response is - * sent to indicate to the remote GATT client that the write operation was - * processed successfully. Other values will cause the local GATT server to send - * an ATT protocol error response. - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle received in the @ref - * sl_bt_evt_gatt_server_user_write_request event - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode); - -/***************************************************************************//** - * - * Send a notification to a remote GATT client. At most, ATT_MTU - 3 number of - * bytes can be sent in a notification. An error SL_STATUS_COMMAND_TOO_LONG is - * returned if the value length exceeds ATT_MTU - 3. - * - * A notification is sent only if the client has enabled it by setting the - * corresponding flag to the Client Characteristic Configuration descriptor. The - * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not - * have the notification property. The error SL_STATUS_INVALID_STATE is returned - * if the client has not enabled the notification. - * - * @param[in] connection A handle of the connection over which the notification - * is sent. - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be notified - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send an indication to a remote GATT client. At most, ATT_MTU - 3 number of - * bytes can be sent in an indication. An error SL_STATUS_COMMAND_TOO_LONG is - * returned if the value length exceeds ATT_MTU - 3. - * - * An indication is sent only if the client has enabled it by setting the - * corresponding flag to the Client Characteristic Configuration descriptor. The - * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not - * have the indication property. The error SL_STATUS_INVALID_STATE is returned - * if the client has not enabled the indication. - * - * A new indication to a GATT client can't be sent until an outstanding - * indication procedure with the same client has completed. The procedure is - * completed when a confirmation from the client is received. The confirmation - * is indicated by @ref sl_bt_evt_gatt_server_characteristic_status. - * - * The error SL_STATUS_IN_PROGRESS is returned if an indication procedure with - * the same client is outstanding. Always wait for confirmation for previous - * indication before sending a new indication. - * - * @param[in] connection A handle of the connection over which the indication is - * sent. - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be indicated - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_gatt_server_characteristic_status - This event is - * triggered after the confirmation from the client is received. - * - @ref sl_bt_evt_gatt_server_indication_timeout - This event indicates - * confirmation from the remote GATT client has not been received within 30 - * seconds after an indication was sent. Further GATT transactions over this - * connection are not allowed by the stack. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, - uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Send notifications or indications to all connected remote GATT clients. At - * most, ATT_MTU - 3 number of bytes can be sent in a notification or - * indication. If the value length exceeds the limit on a connection, the first - * ATT_MTU - 3 bytes will be sent and rest of data is ignored. - * - * A notification or indication is sent only if the client has enabled it by - * setting the corresponding flag to the Client Characteristic Configuration - * descriptor. If the Client Characteristic Configuration descriptor supports - * both notifications and indications, the stack will always send a notification - * even when the client has enabled both. - * - * A new indication to a GATT client can't be sent until an outstanding - * indication procedure with the same client has completed, and the operation - * will continue for the next client. The procedure is completed when a - * confirmation from the client is received. The confirmation is indicated by - * @ref sl_bt_evt_gatt_server_characteristic_status. - * - * @param[in] characteristic Characteristic handle - * @param[in] value_len Length of data in @p value - * @param[in] value Value to be notified or indicated - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Read client characteristic configuration of a remote GATT client. - * - * @param[in] connection A handle of the connection to a remote client. - * @param[in] characteristic Characteristic handle - * @param[out] client_config_flags Enum @ref - * sl_bt_gatt_server_client_configuration_t. Client characteristic - * configuration of a remote client. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, - uint16_t characteristic, - uint16_t *client_config_flags); - -/***************************************************************************//** - * - * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when - * parameter @p att_opcode in the event is @ref sl_bt_gatt_prepare_write_request - * (see @ref sl_bt_gatt_att_opcode_t). The response needs to be sent within 30 - * seconds, otherwise no more GATT transactions are allowed by the remote side. - * If @p att_errorcode is set to 0, the ATT protocol's prepare write response is - * sent to indicate to the remote GATT client that the write operation was - * processed successfully. Other values will cause the local GATT server to send - * an ATT protocol error response. The application should set values of - * parameters @p offset and @p value to identical values from the @ref - * sl_bt_evt_gatt_server_user_write_request event. The values will be verified - * on the client side in case the request is a reliable write (by Bluetooth Core - * Specification Volume 3, Part G, 4.9.5). - * - * @param[in] connection Connection handle - * @param[in] characteristic GATT characteristic handle. This value is normally - * received from the gatt_characteristic event. - * @param[in] att_errorcode Attribute protocol error code - * - 0: No error - * - Non-zero: See Bluetooth specification, Host volume, Attribute - * Protocol, Error Codes table. - * @param[in] offset Value offset - * @param[in] value_len Length of data in @p value - * @param[in] value Value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, - uint16_t characteristic, - uint8_t att_errorcode, - uint16_t offset, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Reset capabilities that should be enabled by the GATT database. A service is - * visible to remote GATT clients if at least one of its capabilities is - * enabled. The same applies to a characteristic and its attributes. Capability - * identifiers and their corresponding bit flag values are in the auto-generated - * database header file. See UG118: Blue Gecko Bluetooth Profile Toolkit - * Developer's Guide for how to declare capabilities in the GATT database. - * - * Changing the capabilities of a database effectively causes a database change - * (attributes being added or removed) from a remote GATT client point of view. - * If the database has a Generic Attribute service and Service Changed - * characteristic, the stack will monitor the local database change status and - * manage service changed indications for a GATT client that has enabled the - * indication configuration of the Service Changed characteristic. - * - * @param[in] caps Bit flags of capabilities to reset. Value 0 sets the default - * database capabilities. - * @param[in] reserved Use the value 0 on this reserved field. Do not use - * none-zero values because they are reserved for future use. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, - uint32_t reserved); - -/***************************************************************************//** - * - * Enable additional capabilities in the local GATT database. Already enabled - * capabilities keep unchanged after this command. See @ref - * sl_bt_gatt_server_set_capabilities for more information. - * - * @param[in] caps Capabilities to enable - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps); - -/***************************************************************************//** - * - * Disable the given capabilities in the local GATT database. See @ref - * sl_bt_gatt_server_set_capabilities for more information. - * - * @param[in] caps Capabilities to disable - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps); - -/***************************************************************************//** - * - * Get capabilities currently enabled in the local GATT database. - * - * @param[out] caps Enabled capabilities - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps); - -/***************************************************************************//** - * - * Read client supported features of a remote GATT client. - * - * @param[in] connection A handle of the connection to a remote client. - * @param[out] client_features Bit field describing client supported features of - * a remote client. See Bluetooth specification Vol 3, Part G, 7.2 for the - * values. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, - uint8_t *client_features); - -/** @} */ // end addtogroup sl_bt_gatt_server - -/** - * @addtogroup sl_bt_nvm NVM - * @{ - * - * @brief NVM - * - * Provide an interface to manage user data objects (key/value pairs) in the - * flash memory. User data stored within the flash memory is persistent across - * reset and power cycling of the device. Because Bluetooth bondings are also - * stored in the flash area, in addition to the flash storage size, the space - * available for user data also depends on the number of bondings the device has - * at the time. - * - * On EFR32[B|M]G1x devices, either PS Store or NVM3 data storage driver can be - * used. PS Store is supported by the Bluetooth stack only. Using NVM3 is - * recommended if the device needs to support Dynamic Multiple Protocol (DMP). - * On EFR32[B|M]G2x devices, only NVM3 is supported. When NVM3 is used, - * applications can also use the NVM3 APIs directly. - * - * In PS Store, the flash storage size is fixed at 2048 bytes. The maximum data - * object size associated to a key is 56 bytes. A Bluetooth bonding uses at - * maximum 138 bytes for secure connections and 174 bytes for legacy pairing. - * - * In NVM3, the flash store size is configurable and the minimum is 3 flash - * pages. The maximum data object size is configurable up to 4096 bytes. A - * Bluetooth bonding uses maximum 110 bytes for secure connections and 138 bytes - * for legacy pairing. For more details, see AN1135 "Using Third Generation - * NonVolatile Memory (NVM3) Data Storage". - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_nvm_save_id 0x020d0020 -#define sl_bt_cmd_nvm_load_id 0x030d0020 -#define sl_bt_cmd_nvm_erase_id 0x040d0020 -#define sl_bt_cmd_nvm_erase_all_id 0x010d0020 -#define sl_bt_rsp_nvm_save_id 0x020d0020 -#define sl_bt_rsp_nvm_load_id 0x030d0020 -#define sl_bt_rsp_nvm_erase_id 0x040d0020 -#define sl_bt_rsp_nvm_erase_all_id 0x010d0020 - -/** - * @addtogroup sl_bt_nvm_keys Defined Keys - * @{ - * - * Define keys - */ - -/** Crystal tuning value override */ -#define SL_BT_NVM_KEY_CTUNE 0x32 - -/** @} */ // end Defined Keys - -/***************************************************************************//** - * - * Store a value into the specified NVM key. Allowed NVM keys are in range from - * 0x4000 to 0x407F. At most, 56 bytes user data can be stored in one NVM key. - * The error code 0x018a (command_too_long) is returned if the value data is - * more than 56 bytes. - * - * @param[in] key NVM key - * @param[in] value_len Length of data in @p value - * @param[in] value Value to store into the specified NVM key - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_save(uint16_t key, - size_t value_len, - const uint8_t* value); - -/***************************************************************************//** - * - * Retrieve the value of the specified NVM key. - * - * @param[in] key NVM key of the value to be retrieved - * @param[in] max_value_size Size of output buffer passed in @p value - * @param[out] value_len On return, set to the length of output data written to - * @p value - * @param[out] value The returned value of the specified NVM key - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_load(uint16_t key, - size_t max_value_size, - size_t *value_len, - uint8_t *value); - -/***************************************************************************//** - * - * Delete a single NVM key and its value from the persistent store. - * - * @param[in] key NVM key to delete - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_erase(uint16_t key); - -/***************************************************************************//** - * - * Delete all NVM keys and their corresponding values. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_nvm_erase_all(); - -/** @} */ // end addtogroup sl_bt_nvm - -/** - * @addtogroup sl_bt_test Testing Commands - * @{ - * - * @brief Testing Commands - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_test_dtm_tx_v4_id 0x030e0020 -#define sl_bt_cmd_test_dtm_tx_cw_id 0x040e0020 -#define sl_bt_cmd_test_dtm_rx_id 0x010e0020 -#define sl_bt_cmd_test_dtm_end_id 0x020e0020 -#define sl_bt_rsp_test_dtm_tx_v4_id 0x030e0020 -#define sl_bt_rsp_test_dtm_tx_cw_id 0x040e0020 -#define sl_bt_rsp_test_dtm_rx_id 0x010e0020 -#define sl_bt_rsp_test_dtm_end_id 0x020e0020 - -/** - * @brief Test packet types supported by the stack - */ -typedef enum -{ - sl_bt_test_pkt_prbs9 = 0x0, /**< (0x0) PRBS9 packet payload */ - sl_bt_test_pkt_11110000 = 0x1, /**< (0x1) 11110000 packet payload */ - sl_bt_test_pkt_10101010 = 0x2, /**< (0x2) 10101010 packet payload */ - sl_bt_test_pkt_11111111 = 0x4, /**< (0x4) 11111111 packet payload */ - sl_bt_test_pkt_00000000 = 0x5, /**< (0x5) 00000000 packet payload */ - sl_bt_test_pkt_00001111 = 0x6, /**< (0x6) 00001111 packet payload */ - sl_bt_test_pkt_01010101 = 0x7, /**< (0x7) 01010101 packet payload */ - sl_bt_test_pkt_pn9 = 0xfd, /**< (0xfd) PN9 continuously modulated output */ - sl_bt_test_pkt_carrier = 0xfe /**< (0xfe) Unmodulated carrier */ -} sl_bt_test_packet_type_t; - -/** - * @brief Test PHY types - */ -typedef enum -{ - sl_bt_test_phy_1m = 0x1, /**< (0x1) 1M PHY */ - sl_bt_test_phy_2m = 0x2, /**< (0x2) 2M PHY */ - sl_bt_test_phy_125k = 0x3, /**< (0x3) 125k Coded PHY */ - sl_bt_test_phy_500k = 0x4 /**< (0x4) 500k Coded PHY */ -} sl_bt_test_phy_t; - -/** - * @addtogroup sl_bt_evt_test_dtm_completed sl_bt_evt_test_dtm_completed - * @{ - * @brief Indicates that the radio has processed a test start or end command - * - * The @p result parameter indicates the success of the command. - * - * After the receiver or transmitter test is stopped, the @p number_of_packets - * parameter in this event indicates the number of received or transmitted - * packets. - */ - -/** @brief Identifier of the dtm_completed event */ -#define sl_bt_evt_test_dtm_completed_id 0x000e00a0 - -/***************************************************************************//** - * @brief Data structure of the dtm_completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_test_dtm_completed_s -{ - uint16_t result; /**< Command result */ - uint16_t number_of_packets; /**< Number of packets - - Only valid for @ref sl_bt_test_dtm_end - command. */ -}); - -typedef struct sl_bt_evt_test_dtm_completed_s sl_bt_evt_test_dtm_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_test_dtm_completed - -/***************************************************************************//** - * - * Start a transmitter test against a separate Bluetooth tester device. When the - * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event - * is triggered. This event indicates whether the test started successfully. - * - * In the transmitter test, the device sends packets continuously with a fixed - * interval. The type and length of each packet is set by @p packet_type and @p - * length parameters. The parameter @p phy specifies which PHY is used to - * transmit the packets. All devices support at least 1M PHY. A special packet - * type, test_pkt_carrier , can be used to transmit continuous - * unmodulated carrier. The length field is ignored in this mode. As this - * command has the limitation within the value of @p power_level, use of @ref - * sl_bt_test_dtm_tx_cw for custom waves is recommended. - * - * Stop the test using the @ref sl_bt_test_dtm_end command. - * - * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to - * transmit. Values: - * - sl_bt_test_pkt_prbs9 (0x0): PRBS9 packet payload - * - sl_bt_test_pkt_11110000 (0x1): 11110000 packet payload - * - sl_bt_test_pkt_10101010 (0x2): 10101010 packet payload - * - sl_bt_test_pkt_11111111 (0x4): 11111111 packet payload - * - sl_bt_test_pkt_00000000 (0x5): 00000000 packet payload - * - sl_bt_test_pkt_00001111 (0x6): 00001111 packet payload - * - sl_bt_test_pkt_01010101 (0x7): 01010101 packet payload - * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output - * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier - * @param[in] length @parblock - * Packet length in bytes - * - * Range: 0-255 - * @endparblock - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * @param[in] power_level @parblock - * TX power level in unit dBm. Values: - * - -127 to +20: Use specified or the nearest TX power level. The - * minimum -127 dBm is specified in the Bluetooth specification. However, - * a device may not support this low TX power. In addition, only some - * devices support 20 dBm TX power. Effective TX power will be limited by - * the global system TX power that can be set with the @ref - * sl_bt_system_set_tx_power command. - * - 0x7E: Use minimum TX power level the device supports. - * - 0x7F: Use the smallest of the maximum TX power level the device - * supports and the global maximum TX power setting in stack. - * - * For continuous unmodulated carrier mode, the values are set in 0.1 dBm - * unit. If the value exceeds the range of power level value allowed by the - * device, the command will adjust the power level to the closest minimum or - * maximum value. - * @endparblock - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, - uint8_t length, - uint8_t channel, - uint8_t phy, - int8_t power_level); - -/***************************************************************************//** - * - * Start a transmitter test for a custom wave. When the command is processed by - * the radio, a @ref sl_bt_evt_test_dtm_completed event is triggered. This event - * indicates whether the test started successfully. - * - * In the custom wave transmitter test, the device continuously transmits the - * career. The parameter @p packet_type specifies the packet type. The parameter - * @p phy specifies which PHY is used to transmit the packets. All devices - * support at least 1M PHY. - * - * Stop the test using the @ref sl_bt_test_dtm_end command. - * - * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to - * transmit. Values: - * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output - * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * @param[in] power_level @parblock - * TX power level. Unit: 0.1 dBm. - * - * If the value exceeds the range of power level value, allowed by the device, - * the command will adjust the power level to the closest minimum or maximum - * value. - * @endparblock - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, - uint8_t channel, - uint8_t phy, - int16_t power_level); - -/***************************************************************************//** - * - * Start a receiver test against a separate Bluetooth tester device. When the - * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event - * is triggered. This event indicates whether the test started successfully. - * - * Parameter @p phy specifies which PHY is used to receive the packets. All - * devices support at least 1M PHY. - * - * The test may be stopped using @ref sl_bt_test_dtm_end command. This will - * trigger another @ref sl_bt_evt_test_dtm_completed event, which carries the - * number of packets received during the test. - * - * @param[in] channel @parblock - * Bluetooth channel - * - * Range: 0-39 - * - * Channel is (F - 2402) / 2, - * - * where F is frequency in MHz - * @endparblock - * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: - * - sl_bt_test_phy_1m (0x1): 1M PHY - * - sl_bt_test_phy_2m (0x2): 2M PHY - * - sl_bt_test_phy_125k (0x3): 125k Coded PHY - * - sl_bt_test_phy_500k (0x4): 500k Coded PHY - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - This event is received when the - * command is processed. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy); - -/***************************************************************************//** - * - * End a transmitter or a receiver test. When the command is processed by the - * radio and the test has ended, a @ref sl_bt_evt_test_dtm_completed event is - * triggered. - * - * - * @return Command result - * - * @b Events - * - @ref sl_bt_evt_test_dtm_completed - Received when the command is - * processed by the radio and the test has ended. - * - ******************************************************************************/ -sl_status_t sl_bt_test_dtm_end(); - -/** @} */ // end addtogroup sl_bt_test - -/** - * @addtogroup sl_bt_sm Security Manager - * @{ - * - * @brief Security Manager - * - * The commands in this class manage Bluetooth security, including commands for - * starting and stopping encryption and commands for management of all bonding - * operations. - * - * Use the following procedure to bond with a remote device: - * - Use the command @ref sl_bt_sm_configure to configure security - * requirements and I/O capabilities of this device. - * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into - * bondable mode. - * - Use the command @ref sl_bt_connection_open to open a connection to the - * remote device. - * - After the connection is open, use command @ref sl_bt_sm_increase_security - * to encrypt the connection. This will also start the bonding process. - * - * Use the following procedure to respond to the bonding initiated by a remote - * device: - * - Use the command @ref sl_bt_sm_configure to configure security - * requirements and I/O capabilities of this device. - * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into - * bondable mode. - * - Use the command @ref sl_bt_advertiser_start to start connectable - * advertising. - * - Open a connection to this device from the remote device. - * - After the connection is open, start the bonding process on the remote - * device. - * - * If MITM is required, the application needs to display or ask the user to - * enter a passkey during the process. See events @ref - * sl_bt_evt_sm_passkey_display and @ref sl_bt_evt_sm_passkey_request for more - * information. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_sm_configure_id 0x010f0020 -#define sl_bt_cmd_sm_set_minimum_key_size_id 0x140f0020 -#define sl_bt_cmd_sm_set_debug_mode_id 0x0f0f0020 -#define sl_bt_cmd_sm_add_to_whitelist_id 0x130f0020 -#define sl_bt_cmd_sm_store_bonding_configuration_id 0x020f0020 -#define sl_bt_cmd_sm_set_bondable_mode_id 0x000f0020 -#define sl_bt_cmd_sm_set_passkey_id 0x100f0020 -#define sl_bt_cmd_sm_increase_security_id 0x040f0020 -#define sl_bt_cmd_sm_enter_passkey_id 0x080f0020 -#define sl_bt_cmd_sm_passkey_confirm_id 0x090f0020 -#define sl_bt_cmd_sm_bonding_confirm_id 0x0e0f0020 -#define sl_bt_cmd_sm_delete_bonding_id 0x060f0020 -#define sl_bt_cmd_sm_delete_bondings_id 0x070f0020 -#define sl_bt_cmd_sm_get_bonding_handles_id 0x150f0020 -#define sl_bt_cmd_sm_get_bonding_details_id 0x160f0020 -#define sl_bt_cmd_sm_find_bonding_by_address_id 0x170f0020 -#define sl_bt_cmd_sm_resolve_rpa_id 0x1d0f0020 -#define sl_bt_cmd_sm_set_bonding_key_id 0x180f0020 -#define sl_bt_cmd_sm_set_legacy_oob_id 0x190f0020 -#define sl_bt_cmd_sm_set_oob_id 0x1a0f0020 -#define sl_bt_cmd_sm_set_remote_oob_id 0x1b0f0020 -#define sl_bt_cmd_sm_set_bonding_data_id 0x1c0f0020 -#define sl_bt_rsp_sm_configure_id 0x010f0020 -#define sl_bt_rsp_sm_set_minimum_key_size_id 0x140f0020 -#define sl_bt_rsp_sm_set_debug_mode_id 0x0f0f0020 -#define sl_bt_rsp_sm_add_to_whitelist_id 0x130f0020 -#define sl_bt_rsp_sm_store_bonding_configuration_id 0x020f0020 -#define sl_bt_rsp_sm_set_bondable_mode_id 0x000f0020 -#define sl_bt_rsp_sm_set_passkey_id 0x100f0020 -#define sl_bt_rsp_sm_increase_security_id 0x040f0020 -#define sl_bt_rsp_sm_enter_passkey_id 0x080f0020 -#define sl_bt_rsp_sm_passkey_confirm_id 0x090f0020 -#define sl_bt_rsp_sm_bonding_confirm_id 0x0e0f0020 -#define sl_bt_rsp_sm_delete_bonding_id 0x060f0020 -#define sl_bt_rsp_sm_delete_bondings_id 0x070f0020 -#define sl_bt_rsp_sm_get_bonding_handles_id 0x150f0020 -#define sl_bt_rsp_sm_get_bonding_details_id 0x160f0020 -#define sl_bt_rsp_sm_find_bonding_by_address_id 0x170f0020 -#define sl_bt_rsp_sm_resolve_rpa_id 0x1d0f0020 -#define sl_bt_rsp_sm_set_bonding_key_id 0x180f0020 -#define sl_bt_rsp_sm_set_legacy_oob_id 0x190f0020 -#define sl_bt_rsp_sm_set_oob_id 0x1a0f0020 -#define sl_bt_rsp_sm_set_remote_oob_id 0x1b0f0020 -#define sl_bt_rsp_sm_set_bonding_data_id 0x1c0f0020 - -/** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * @brief These values define the bonding keys of the bonded device stored in - * the persistent store. - */ -typedef enum -{ - sl_bt_sm_bonding_key_remote_ltk = 0x1, /**< (0x1) LTK used as central device, - always used when paired using - secure connections and local LTK - does not exist */ - sl_bt_sm_bonding_key_local_ltk = 0x2, /**< (0x2) LTK used as peripheral - device when using legacy pairing, - only used with secure connections - pairing if key exists */ - sl_bt_sm_bonding_key_irk = 0x3 /**< (0x3) Identity resolving key for - resolvable private addresses */ -} sl_bt_sm_bonding_key_t; -/** @endcond */ // end restricted enum type - -/** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * @brief These values define the bonding data types, which are stored in the - * persistent store. - */ -typedef enum -{ - sl_bt_sm_bonding_data_remote_address = 0x0, /**< (0x0) Identity address - of the remote device */ - sl_bt_sm_bonding_data_remote_ltk = 0x1, /**< (0x1) LTK used as - central device */ - sl_bt_sm_bonding_data_local_ltk = 0x2, /**< (0x2) LTK used as - peripheral device */ - sl_bt_sm_bonding_data_remote_master_inf = 0x3, /**< (0x3) Idenfication info - used as central device */ - sl_bt_sm_bonding_data_local_master_inf = 0x4, /**< (0x4) Idenfication info - used as central device */ - sl_bt_sm_bonding_data_irk = 0x5, /**< (0x5) IRK of the remote - device */ - sl_bt_sm_bonding_data_meta = 0x6, /**< (0x6) Metadata about - the bonding */ - sl_bt_sm_bonding_data_gatt_client_config = 0x7, /**< (0x7) GATT database - client configuration */ - sl_bt_sm_bonding_data_gatt_client_features = 0x8, /**< (0x8) GATT client - supported features */ - sl_bt_sm_bonding_data_gatt_db_hash = 0x9 /**< (0x9) GATT database - hash */ -} sl_bt_sm_bonding_data_t; -/** @endcond */ // end restricted enum type - -/** - * @brief These values define the security management related I/O capabilities - * supported by the device. - */ -typedef enum -{ - sl_bt_sm_io_capability_displayonly = 0x0, /**< (0x0) Display Only */ - sl_bt_sm_io_capability_displayyesno = 0x1, /**< (0x1) Display with - Yes/No-buttons */ - sl_bt_sm_io_capability_keyboardonly = 0x2, /**< (0x2) Keyboard Only */ - sl_bt_sm_io_capability_noinputnooutput = 0x3, /**< (0x3) No Input and No - Output */ - sl_bt_sm_io_capability_keyboarddisplay = 0x4 /**< (0x4) Display with Keyboard */ -} sl_bt_sm_io_capability_t; - -/** - * @addtogroup sl_bt_sm_configuration Security Manager configuration flags - * @{ - * - * These values are used to configure security requirements. - */ - -/** Bonding requires authentication (Man-in-the-Middle protection). */ -#define SL_BT_SM_CONFIGURATION_MITM_REQUIRED 0x1 - -/** Encryption requires bonding. Note that this setting will also enable - * bonding. */ -#define SL_BT_SM_CONFIGURATION_BONDING_REQUIRED 0x2 - -/** Require secure connections pairing. */ -#define SL_BT_SM_CONFIGURATION_SC_ONLY 0x4 - -/** Bonding requests need to be confirmed. Received bonding requests are - * notified by @ref sl_bt_evt_sm_confirm_bonding. */ -#define SL_BT_SM_CONFIGURATION_BONDING_REQUEST_REQUIRED 0x8 - -/** Allow connections only from bonded devices. This option is ignored when the - * application includes the bluetooth_feature_external_bonding_database feature. - * */ -#define SL_BT_SM_CONFIGURATION_CONNECTIONS_FROM_BONDED_DEVICES_ONLY 0x10 - -/** Prefer authenticated pairing when both options are possible based on the - * settings. Otherwise just works pairing is preferred. */ -#define SL_BT_SM_CONFIGURATION_PREFER_MITM 0x20 - -/** Require secure connections OOB data from both devices. */ -#define SL_BT_SM_CONFIGURATION_OOB_FROM_BOTH_DEVICES_REQUIRED 0x40 - -/** Reject pairing if remote device uses debug keys. */ -#define SL_BT_SM_CONFIGURATION_REJECT_DEBUG_KEYS 0x80 - -/** @} */ // end Security Manager configuration flags - -/** - * @addtogroup sl_bt_evt_sm_passkey_display sl_bt_evt_sm_passkey_display - * @{ - * @brief Indicates a request to display the passkey to the user. - */ - -/** @brief Identifier of the passkey_display event */ -#define sl_bt_evt_sm_passkey_display_id 0x000f00a0 - -/***************************************************************************//** - * @brief Data structure of the passkey_display event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_passkey_display_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t passkey; /**< Passkey. Range: 0 to 999999. - - NOTE! When displaying the passkey to the user, - prefix the number with zeros to obtain a 6 digit - number - - Example: Passkey value is 42 - - Number to display to the user is 000042 */ -}); - -typedef struct sl_bt_evt_sm_passkey_display_s sl_bt_evt_sm_passkey_display_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_passkey_display - -/** - * @addtogroup sl_bt_evt_sm_passkey_request sl_bt_evt_sm_passkey_request - * @{ - * @brief Indicates a request for the passkey prompt displayed on the remote - * device - * - * Use the command @ref sl_bt_sm_enter_passkey to input the passkey value. - */ - -/** @brief Identifier of the passkey_request event */ -#define sl_bt_evt_sm_passkey_request_id 0x010f00a0 - -/***************************************************************************//** - * @brief Data structure of the passkey_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_passkey_request_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_sm_passkey_request_s sl_bt_evt_sm_passkey_request_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_passkey_request - -/** - * @addtogroup sl_bt_evt_sm_confirm_passkey sl_bt_evt_sm_confirm_passkey - * @{ - * @brief Indicates a request for passkey display and confirmation by the user - * - * Use the command @ref sl_bt_sm_passkey_confirm to accept or reject the - * displayed passkey. - */ - -/** @brief Identifier of the confirm_passkey event */ -#define sl_bt_evt_sm_confirm_passkey_id 0x020f00a0 - -/***************************************************************************//** - * @brief Data structure of the confirm_passkey event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_confirm_passkey_s -{ - uint8_t connection; /**< Connection handle */ - uint32_t passkey; /**< Passkey. Range: 0 to 999999. - - NOTE! When displaying the passkey to the user, - prefix the number with zeros to obtain a 6 digit - number - - Example: Passkey value is 42 - - Number to display to the user is 000042 */ -}); - -typedef struct sl_bt_evt_sm_confirm_passkey_s sl_bt_evt_sm_confirm_passkey_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_confirm_passkey - -/** - * @addtogroup sl_bt_evt_sm_bonded sl_bt_evt_sm_bonded - * @{ - * @brief Triggered when the pairing or bonding procedure is successfully - * completed. - */ - -/** @brief Identifier of the bonded event */ -#define sl_bt_evt_sm_bonded_id 0x030f00a0 - -/***************************************************************************//** - * @brief Data structure of the bonded event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_bonded_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t bonding; /**< Bonding handle. Values: - - SL_BT_INVALID_BONDING_HANDLE (0xff): - Pairing completed without bonding - the - pairing key will be discarded after - disconnection. - - Other: Procedure completed, pairing key - stored with given bonding handle */ - uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection - security mode. Values: - - sl_bt_connection_mode1_level2 (0x1): - Unauthenticated pairing with encryption - - sl_bt_connection_mode1_level3 (0x2): - Authenticated pairing with encryption - - sl_bt_connection_mode1_level4 (0x3): - Authenticated Secure Connections pairing with - encryption using a 128-bit strength encryption - key */ -}); - -typedef struct sl_bt_evt_sm_bonded_s sl_bt_evt_sm_bonded_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_bonded - -/** - * @addtogroup sl_bt_evt_sm_bonding_failed sl_bt_evt_sm_bonding_failed - * @{ - * @brief This event is triggered if the pairing or bonding procedure fails. - */ - -/** @brief Identifier of the bonding_failed event */ -#define sl_bt_evt_sm_bonding_failed_id 0x040f00a0 - -/***************************************************************************//** - * @brief Data structure of the bonding_failed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_bonding_failed_s -{ - uint8_t connection; /**< Connection handle */ - uint16_t reason; /**< Describes error that occurred */ -}); - -typedef struct sl_bt_evt_sm_bonding_failed_s sl_bt_evt_sm_bonding_failed_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_bonding_failed - -/** - * @addtogroup sl_bt_evt_sm_confirm_bonding sl_bt_evt_sm_confirm_bonding - * @{ - * @brief Indicates a user request to display that the new bonding request is - * received and for the user to confirm the request - * - * Use the command @ref sl_bt_sm_bonding_confirm to accept or reject the bonding - * request. - */ - -/** @brief Identifier of the confirm_bonding event */ -#define sl_bt_evt_sm_confirm_bonding_id 0x090f00a0 - -/***************************************************************************//** - * @brief Data structure of the confirm_bonding event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_sm_confirm_bonding_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t bonding_handle; /**< Bonding handle for the request. Range: 0 to 31, - or SL_BT_INVALID_BONDING_HANDLE (0xff). - - NOTE! When the bonding handle is anything - other than SL_BT_INVALID_BONDING_HANDLE - (0xff), a bonding already exists for this - connection. Overwriting the existing bonding - is a potential security risk. */ -}); - -typedef struct sl_bt_evt_sm_confirm_bonding_s sl_bt_evt_sm_confirm_bonding_t; - -/** @} */ // end addtogroup sl_bt_evt_sm_confirm_bonding - -/***************************************************************************//** - * - * Configure security requirements and I/O capabilities of the system. - * - * @param[in] flags @parblock - * Security requirement flags. This value can be a bitmask of multiple flags - * from @ref sl_bt_sm_configuration - * - * Bit 0: - * - 0: Allow bonding without authentication - * - 1: Bonding requires authentication (Man-in-the-Middle - * protection) - * - * Bit 1: - * - 0: Allow encryption without bonding - * - 1: Encryption requires bonding. Note that this setting will also - * enable bonding. - * - * Bit 2: - * - 0: Allow bonding with legacy pairing - * - 1: Secure connections only - * - * Bit 3: - * - 0: Bonding request does not need to be confirmed - * - 1: Bonding requests need to be confirmed. Received bonding - * requests are notified by @ref sl_bt_evt_sm_confirm_bonding - * - * Bit 4: This option is ignored when the application includes the - * bluetooth_feature_external_bonding_database feature. - * - 0: Allow all connections - * - 1: Allow connections only from bonded devices - * - * Bit 5: - * - 0: Prefer just works pairing when both options are possible - * based on the settings. - * - 1: Prefer authenticated pairing when both options are possible - * based on the settings. - * - * Bit 6: - * - 0: Allow secure connections OOB pairing with OOB data from only - * one device. - * - 1: Require secure connections OOB data from both devices. - * - * Bit 7: - * - 0: Allow debug keys from remote device. - * - 1: Reject pairing if remote device uses debug keys. - * - * Default value: 0x00 - * @endparblock - * @param[in] io_capabilities Enum @ref sl_bt_sm_io_capability_t. I/O - * Capabilities. The default I/O Capability used by the stack is No Input and - * No Output. Values: - * - sl_bt_sm_io_capability_displayonly (0x0): Display Only - * - sl_bt_sm_io_capability_displayyesno (0x1): Display with - * Yes/No-buttons - * - sl_bt_sm_io_capability_keyboardonly (0x2): Keyboard Only - * - sl_bt_sm_io_capability_noinputnooutput (0x3): No Input and No - * Output - * - sl_bt_sm_io_capability_keyboarddisplay (0x4): Display with - * Keyboard - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities); - -/***************************************************************************//** - * - * Set the minimum allowed key size used for bonding. The default value is 16 - * bytes. - * - * @param[in] minimum_key_size Minimum allowed key size for bonding. Range: 7 to - * 16 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size); - -/***************************************************************************//** - * - * Set Security Manager in debug mode. In this mode, the secure connections - * bonding uses known debug keys, so that the encrypted packet can be opened by - * Bluetooth protocol analyzer. To disable the debug mode, restart the device. - * - * Bondings made in debug mode are unsecure. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_debug_mode(); - -/***************************************************************************//** - * - * Deprecated and replaced by @ref - * sl_bt_accept_list_add_device_by_bonding and @ref - * sl_bt_accept_list_add_device_by_address provided by the - * bluetooth_feature_accept_list component. - * - * Add device to accept list, which can be enabled with @ref - * sl_bt_gap_enable_whitelisting. - * - * When using external bonding database, the accept list size must be set before - * adding devices to the list using @ref sl_bt_sm_store_bonding_configuration. - * - * @param[in] address Address of the device added to accept list - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of - * the device added to accept list. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type); - -/***************************************************************************//** - * - * Set the maximum allowed bonding count and bonding policy. The maximum number - * of bondings that can be supported depends on how much user data is stored in - * the NVM and the NVM size. When bond policy value 1 or 2 is selected, the - * stack will automatically write the new bond, as per the policy, only if the - * maximum allowed bonding count has been reached. If the stack can't write a - * new bond for any other reason (e.g., NVM is full), an error will be thrown - * through the bonding_failed event indicating why the bonding was not written. - * The application has to manually release space from the NVM (e.g., by deleting - * one of the existing bonds or application data) so that a new bond can be - * saved. The default value is 13. - * - * When using external bonding database with accept list filtering, this command - * must be called before adding devices to the accept list to define the list - * size. Calling this function empties the existing accept list. - * - * @param[in] max_bonding_count @parblock - * Maximum allowed bonding count. Range: 1 to 32 - * - * Sets the accept list size with external bonding database. - * @endparblock - * @param[in] policy_flags @parblock - * Bonding policy. Values: - * - 0: If database is full, new bonding attempts will fail - * - 1: New bonding will overwrite the oldest existing bonding - * - 2: New bonding will overwrite the bonding that was used the - * longest time ago - * - * Default: 0 - * - * With external bonding database the parameter is ignored. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, - uint8_t policy_flags); - -/***************************************************************************//** - * - * Set whether the device should accept new bondings. By default, the device - * does not accept new bondings. - * - * @param[in] bondable @parblock - * Bondable mode. Values: - * - 0: New bondings not accepted - * - 1: Bondings allowed - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable); - -/***************************************************************************//** - * - * Enter a fixed passkey, which will be used in the @ref - * sl_bt_evt_sm_passkey_display event. - * - * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to disable and - * start using random passkeys. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_passkey(int32_t passkey); - -/***************************************************************************//** - * - * Enhance the security of a connection to current security requirements. On an - * unencrypted connection, it will encrypt the connection and will also perform - * bonding if requested by both devices. On an encrypted connection, it will - * cause the connection to be re-encrypted. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_parameters - Triggered after increasing - * security has been completed successfully and indicates the latest - * security mode of the connection. - * - @ref sl_bt_evt_sm_bonded - Triggered if pairing or bonding was performed - * in this operation and the result is successful. - * - @ref sl_bt_evt_sm_bonding_failed - Triggered if pairing or bonding was - * performed in this operation and the result has failed. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_increase_security(uint8_t connection); - -/***************************************************************************//** - * - * Enter a passkey after receiving a passkey request event. - * - * @param[in] connection Connection handle - * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to cancel pairing. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey); - -/***************************************************************************//** - * - * Accept or reject the reported passkey confirm value. - * - * @param[in] connection Connection handle - * @param[in] confirm Acceptance. Values: - * - 0: Reject - * - 1: Accept confirm value - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm); - -/***************************************************************************//** - * - * Accept or reject the bonding request. - * - * @param[in] connection Connection handle - * @param[in] confirm Acceptance. Values: - * - 0: Reject - * - 1: Accept bonding request - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm); - -/***************************************************************************//** - * - * Delete the specified bonding or accept list filtering. The connection will be - * closed if the remote device is connected currently. - * - * This commands deletes the information from the persistent bonding database - * when the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) is used. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] bonding Bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding); - -/***************************************************************************//** - * - * Delete all bondings, accept list filtering and device local identity - * resolving key (IRK). All connections to affected devices are closed as well. - * - * This command empties the persistent bonding database when the built-in - * bonding database (bluetooth_feature_builtin_bonding_database) is used. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_delete_bondings(); - -/***************************************************************************//** - * - * Get number of entries and bitmask of their handles saved in the bonding - * database. The entry in the bonding database can be either bonding or accept - * list filtering device. - * - * To get the bonding type and peer device address of a bonding, use the @ref - * sl_bt_sm_get_bonding_details command. The bonding handle can be calculated - * from the handle bitmask returned by this command, or alternatively, repeat - * calling the @ref sl_bt_sm_get_bonding_details command to get the detailed - * information of all bondings. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] reserved Use the value 0 on this reserved field. Do not use - * none-zero values because they are reserved for future use. - * @param[out] num_bondings Total number of bondings and accept list filtering - * devices stored in bonding database. - * @param[in] max_bondings_size Size of output buffer passed in @p bondings - * @param[out] bondings_len On return, set to the length of output data written - * to @p bondings - * @param[out] bondings 4 byte bit field of used bonding handles in little - * endian format. Bit 0 of first byte is bonding handle 0, bit 0 of second - * byte is bonding handle 8 etc. If the bit is 1 that bonding handle exists in - * the bonding database. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, - uint32_t *num_bondings, - size_t max_bondings_size, - size_t *bondings_len, - uint8_t *bondings); - -/***************************************************************************//** - * - * Get the detailed information for a bonding entry. Data includes remote device - * address and address type as well as security mode for bonding and a used - * encryption key length. - * - * To get the detailed information of all bondings, repeat calling this command - * starting from 0 as the bonding handle value until the maximum number of - * configured bondings are reached. Use 32 as the maximum number if the - * configured number is unknown. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] bonding Bonding handle - * @param[out] address Bluetooth address of the remote device - * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Address type. - * Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Accept list filtering entry has security mode as no - * security. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size Key length in bytes, 0 for accept list filtering entry - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, - bd_addr *address, - uint8_t *address_type, - uint8_t *security_mode, - uint8_t *key_size); - -/***************************************************************************//** - * - * Find the bonding or accept list filtering entry by using a Bluetooth device - * address. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] address The Bluetooth device address - * @param[out] bonding The bonding handle - * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection - * security mode. Accept list filtering entry has security mode as no - * security. Values: - * - sl_bt_connection_mode1_level1 (0x0): No security - * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing - * with encryption - * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with - * encryption - * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure - * Connections pairing with encryption using a 128-bit strength encryption - * key - * @param[out] key_size Key length in bytes, 0 for accept list filtering entry - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, - uint32_t *bonding, - uint8_t *security_mode, - uint8_t *key_size); - -/***************************************************************************//** - * - * Find the identity address of bonded device by using resolvable private - * address (RPA). - * - * The error SL_STATUS_NOT_FOUND is returned if the RPA cannot be resolved. - * - * This command is unavailable if the external bonding database - * (bluetooth_feature_external_bonding_database) is used. - * - * @param[in] rpa Resolvable private address to be resolved - * @param[out] address The identity adderss of the bonded device - * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Identity address - * type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[out] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, - bd_addr *address, - uint8_t *address_type, - uint32_t *bonding); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Set key for bonding or accept list filtering entry overwriting any possible - * existing key. If there is error which leaves bonding entry in inconsistent - * state the bonding will be deleted. Only IRK can be added to accept list - * filtering entry. - * - * @param[in] bonding Bonding handle - * @param[in] key_type Enum @ref sl_bt_sm_bonding_key_t. Key type. Values: - * - sl_bt_sm_bonding_key_remote_ltk (0x1): LTK used as central - * device, always used when paired using secure connections and local LTK - * does not exist - * - sl_bt_sm_bonding_key_local_ltk (0x2): LTK used as peripheral - * device when using legacy pairing, only used with secure connections - * pairing if key exists - * - sl_bt_sm_bonding_key_irk (0x3): Identity resolving key for - * resolvable private addresses - * @param[in] key Bonding key in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, - uint8_t key_type, - aes_key_128 key); - -/***************************************************************************//** - * - * Set Out-Of-Band (OOB) encryption data for a legacy pairing of a device. OOB - * data may be, for example, a PIN code exchanged over an alternate path, such - * as NFC. The device will not allow any other bonding if OOB data is set. OOB - * data can't be set simultaneously with secure connections OOB data. - * - * @param[in] enable Enable OOB with legacy pairing. Values: - * - 0: disable - * - 1: enable - * @param[in] oob_data 16-byte legacy pairing OOB data in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data); - -/***************************************************************************//** - * - * Enable the use of Out-Of-Band (OOB) encryption data for a device for secure - * connections pairing. Enabling will generate new OOB data and confirm values, - * which can be sent to the remote device. After enabling the secure connections - * OOB data, the remote devices OOB data can be set with @ref - * sl_bt_sm_set_remote_oob. Calling this function will erase any set remote - * device OOB data and confirm values. The device will not allow any other - * bonding if OOB data is set. The secure connections OOB data cannot be enabled - * simultaneously with legacy pairing OOB data. - * - * @param[in] enable Enable OOB with secure connections pairing. Values: - * - 0: disable - * - 1: enable - * @param[out] random 16-byte randomly-generated secure connections OOB data in - * little endian format. - * @param[out] confirm 16-byte confirm value for the OOB random value in little - * endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_oob(uint8_t enable, - aes_key_128 *random, - aes_key_128 *confirm); - -/***************************************************************************//** - * - * Set Out-Of-Band (OOB) data and confirm values received from the remote device - * for secure connections pairing. OOB data must be enabled with @ref - * sl_bt_sm_set_oob before setting the remote device OOB data. - * - * @param[in] enable Enable remote device OOB data with secure connections - * pairing. Values: - * - 0: disable - * - 1: enable - * @param[in] random 16-byte remote device secure connections OOB data in little - * endian format. - * @param[in] confirm 16-byte remote device confirm value for the OOB random - * value in little endian format. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, - aes_key_128 random, - aes_key_128 confirm); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Set bonding data for connection from external bonding database. - * - * @param[in] connection Connection handle - * @param[in] type Enum @ref sl_bt_sm_bonding_data_t. Bonding data type. Values: - * - sl_bt_sm_bonding_data_remote_address (0x0): Identity address of - * the remote device - * - sl_bt_sm_bonding_data_remote_ltk (0x1): LTK used as central - * device - * - sl_bt_sm_bonding_data_local_ltk (0x2): LTK used as peripheral - * device - * - sl_bt_sm_bonding_data_remote_master_inf (0x3): Idenfication info - * used as central device - * - sl_bt_sm_bonding_data_local_master_inf (0x4): Idenfication info - * used as central device - * - sl_bt_sm_bonding_data_irk (0x5): IRK of the remote device - * - sl_bt_sm_bonding_data_meta (0x6): Metadata about the bonding - * - sl_bt_sm_bonding_data_gatt_client_config (0x7): GATT database - * client configuration - * - sl_bt_sm_bonding_data_gatt_client_features (0x8): GATT client - * supported features - * - sl_bt_sm_bonding_data_gatt_db_hash (0x9): GATT database hash - * @param[in] data_len Length of data in @p data - * @param[in] data Bonding data. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/** @} */ // end addtogroup sl_bt_sm - -/** - * @addtogroup sl_bt_external_bondingdb External Bonding Database - * @{ - * - * @brief External Bonding Database - * - * Receive and respond to requests related to managing an external bonding - * database. When the application uses the - * bluetooth_feature_external_bonding_database feature, the Bluetooth stack and - * the application use the commands and events in this class to store and - * retrieve data from the persistent bonding storage. - * - * When this feature is used, the built-in bonding database - * (bluetooth_feature_builtin_bonding_database) and the address resolving in the - * Bluetooth stack are excluded. The user application and external bonding - * database are responsible for the following functionalities: - * - The external bonding database must be able to reliably and permanently - * store the bonding data and type tuples that are provided by the stack in - * the @ref sl_bt_evt_external_bondingdb_data_request event. Data types @ref - * sl_bt_external_bondingdb_data_remote_address and @ref - * sl_bt_external_bondingdb_data_remote_address_type can be used by the - * application to identify the device, but they are not used by the stack - * and hence the stack will not ask for their values. Other data types in - * @ref sl_bt_external_bondingdb_data_t are needed by the Bluetooth Security - * Manager or GATT Server. The Long Term Keys (LTK) and Identity Resolving - * Keys (IRK) must be stored securely. When the database is on a separate - * host device, they must be securely transmitted between the host and - * target over the NCP transport. The application also needs to manage the - * bondings in the storage, e.g., delete a bonding when requested by the - * business logic. - * - Manage a local RAM-based bookkeeping to keep track of open connections. - * At a minimum, the remote Bluetooth address address and address type must - * be stored in the bookkeeping when a @ref sl_bt_evt_connection_opened - * event is received. If the remote Bluetooth device address is a resolvable - * private random (RPA) address, the application may perform address - * resolving using the IRK keys of the remote devices stored in the bonding - * database. Address resolving is required for identifying a connected - * device using an RPA address. When the scanner or periodic advertising - * synchronization feature is used, RPA addresses in advertisement report or - * sync events may need to be resolved if required by the business - * requirements. - * - When the Bluetooth stack requires bonding data, it will send an @ref - * sl_bt_evt_external_bondingdb_data_request event. The application must - * respond to the request by sending the data value using the @ref - * sl_bt_external_bondingdb_set_data command. The GATT server will pend the - * requests from the remote GATT client and encryption or bonding is not - * possible until all requested bonding data has been sent to the stack. The - * stack will send @ref sl_bt_evt_external_bondingdb_data_ready when it has - * received all the necessary bonding data from the application. - * - * In this configuration, the value of @p bonding parameter in @ref - * sl_bt_evt_advertiser_scan_request, @ref sl_bt_evt_connection_opened, @ref - * sl_bt_evt_sm_bonded, @ref sl_bt_evt_scanner_scan_report, @ref - * sl_bt_evt_scanner_legacy_advertisement_report, @ref - * sl_bt_evt_scanner_extended_advertisement_report, @ref sl_bt_evt_sync_opened, - * and @ref sl_bt_evt_sync_transfer_received is always - * SL_BT_INVALID_BONDING_HANDLE (0xff). Resolving the bonding handle is the - * responsibility of the external bonding database. Additionally, the following - * BGAPI commands are not available and will return the SL_STATUS_NOT_AVAILABLE - * error: - * - @ref sl_bt_sm_delete_bonding - * - @ref sl_bt_sm_get_bonding_handles - * - @ref sl_bt_sm_get_bonding_details - * - @ref sl_bt_sm_find_bonding_by_address - * - @ref sl_bt_sm_resolve_rpa - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_external_bondingdb_set_data_id 0x005c0020 -#define sl_bt_rsp_external_bondingdb_set_data_id 0x005c0020 - -/** - * @brief These values define the bonding data types, which are stored in the - * persistent store. - */ -typedef enum -{ - sl_bt_external_bondingdb_data_remote_address = 0x0, /**< (0x0) Identity - address of the - remote device, - which a - resolvable - random address - can be resolved - to */ - sl_bt_external_bondingdb_data_remote_address_type = 0x1, /**< (0x1) Type of - the remote - device identity - address. Value - 0 is public - device address - and 1 is static - device address */ - sl_bt_external_bondingdb_data_remote_ltk = 0x2, /**< (0x2) Long Term - Key (LTK) used - as central - device. The - value of this - type must be - stored - securely. */ - sl_bt_external_bondingdb_data_local_ltk = 0x3, /**< (0x3) Long Term - Key (LTK) used - as peripheral - device. The - value of this - type must be - stored - securely. */ - sl_bt_external_bondingdb_data_remote_central_inf = 0x4, /**< (0x4) - Identification - info used as a - central device */ - sl_bt_external_bondingdb_data_local_central_inf = 0x5, /**< (0x5) - Identification - info used as a - central device */ - sl_bt_external_bondingdb_data_irk = 0x6, /**< (0x6) Identity - Resolving Key - (IRK) of the - remote device - that is used - for resolving - its RPA - addresses when - the device is - in privacy - mode. The value - of this type - must be stored - securely. */ - sl_bt_external_bondingdb_data_meta = 0x7, /**< (0x7) Metadata - about the - bonding */ - sl_bt_external_bondingdb_data_gatt_client_config = 0x8, /**< (0x8) The - remote GATT - client - characteristic - configurations */ - sl_bt_external_bondingdb_data_gatt_client_features = 0x9, /**< (0x9) The - remote GATT - client - supported - features */ - sl_bt_external_bondingdb_data_gatt_db_hash = 0xa /**< (0xa) Latest - local GATT - database hash - value that the - remote client - has seen for - GATT robust - caching feature */ -} sl_bt_external_bondingdb_data_t; - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data_request sl_bt_evt_external_bondingdb_data_request - * @{ - * @brief Indicates that the Bluetooth stack requests the bonding data of a - * connection from the external bonding database - * - * The application must respond by setting bonding data using the @ref - * sl_bt_external_bondingdb_set_data command. - * - * The Bluetooth stack will send this event one or more times after a connection - * is open following the @ref sl_bt_evt_connection_opened event to get ready for - * security related operations. - */ - -/** @brief Identifier of the data_request event */ -#define sl_bt_evt_external_bondingdb_data_request_id 0x005c00a0 - -/***************************************************************************//** - * @brief Data structure of the data_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_request_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The - requested bonding data type. Values: - - sl_bt_external_bondingdb_data_remote_address - (0x0): Identity address of the remote device, - which a resolvable random address can be resolved - to - - sl_bt_external_bondingdb_data_remote_address_type - (0x1): Type of the remote device identity - address. Value 0 is public device address and 1 - is static device address - - sl_bt_external_bondingdb_data_remote_ltk - (0x2): Long Term Key (LTK) used as central - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_local_ltk - (0x3): Long Term Key (LTK) used as peripheral - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_remote_central_inf - (0x4): Identification info used as a central - device - - sl_bt_external_bondingdb_data_local_central_inf - (0x5): Identification info used as a central - device - - sl_bt_external_bondingdb_data_irk (0x6): - Identity Resolving Key (IRK) of the remote device - that is used for resolving its RPA addresses when - the device is in privacy mode. The value of this - type must be stored securely. - - sl_bt_external_bondingdb_data_meta (0x7): - Metadata about the bonding - - sl_bt_external_bondingdb_data_gatt_client_config - (0x8): The remote GATT client characteristic - configurations - - sl_bt_external_bondingdb_data_gatt_client_features - (0x9): The remote GATT client supported - features - - sl_bt_external_bondingdb_data_gatt_db_hash - (0xa): Latest local GATT database hash value - that the remote client has seen for GATT robust - caching feature */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_request_s sl_bt_evt_external_bondingdb_data_request_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_request - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data sl_bt_evt_external_bondingdb_data - * @{ - * @brief Indicates that updated bonding data of a connection is available - * - * The application must store it in the external bonding database permanently. - */ - -/** @brief Identifier of the data event */ -#define sl_bt_evt_external_bondingdb_data_id 0x015c00a0 - -/***************************************************************************//** - * @brief Data structure of the data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The - bonding data type. Values: - - sl_bt_external_bondingdb_data_remote_address - (0x0): Identity address of the remote - device, which a resolvable random address can - be resolved to - - sl_bt_external_bondingdb_data_remote_address_type - (0x1): Type of the remote device identity - address. Value 0 is public device address and - 1 is static device address - - sl_bt_external_bondingdb_data_remote_ltk - (0x2): Long Term Key (LTK) used as central - device. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_local_ltk - (0x3): Long Term Key (LTK) used as - peripheral device. The value of this type must - be stored securely. - - sl_bt_external_bondingdb_data_remote_central_inf - (0x4): Identification info used as a - central device - - sl_bt_external_bondingdb_data_local_central_inf - (0x5): Identification info used as a - central device - - sl_bt_external_bondingdb_data_irk - (0x6): Identity Resolving Key (IRK) of the - remote device that is used for resolving its - RPA addresses when the device is in privacy - mode. The value of this type must be stored - securely. - - sl_bt_external_bondingdb_data_meta - (0x7): Metadata about the bonding - - sl_bt_external_bondingdb_data_gatt_client_config - (0x8): The remote GATT client - characteristic configurations - - sl_bt_external_bondingdb_data_gatt_client_features - (0x9): The remote GATT client supported - features - - sl_bt_external_bondingdb_data_gatt_db_hash - (0xa): Latest local GATT database hash - value that the remote client has seen for GATT - robust caching feature */ - uint8array data; /**< Bonding data */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_s sl_bt_evt_external_bondingdb_data_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data - -/** - * @addtogroup sl_bt_evt_external_bondingdb_data_ready sl_bt_evt_external_bondingdb_data_ready - * @{ - * @brief Indicates that stack has received all the necessary bonding data from - * the application and is now fully functional - */ - -/** @brief Identifier of the data_ready event */ -#define sl_bt_evt_external_bondingdb_data_ready_id 0x025c00a0 - -/***************************************************************************//** - * @brief Data structure of the data_ready event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_ready_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_external_bondingdb_data_ready_s sl_bt_evt_external_bondingdb_data_ready_t; - -/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_ready - -/***************************************************************************//** - * - * Set bonding data of a connection from the external bonding database. When the - * Bluetooth stack needs bonding data, it will send the request to user - * application with a @ref sl_bt_evt_external_bondingdb_data_request event that - * contains the requested data type. The application must respond to the request - * by sending data using this command. - * - * Send 0 length data to the stack with this command if the requested data is - * not available in the external bonding database. - * - * @param[in] connection Connection handle - * @param[in] type Enum @ref sl_bt_external_bondingdb_data_t. Bonding data type. - * Values: - * - sl_bt_external_bondingdb_data_remote_address (0x0): Identity - * address of the remote device, which a resolvable random address can be - * resolved to - * - sl_bt_external_bondingdb_data_remote_address_type (0x1): Type of - * the remote device identity address. Value 0 is public device address - * and 1 is static device address - * - sl_bt_external_bondingdb_data_remote_ltk (0x2): Long Term Key - * (LTK) used as central device. The value of this type must be stored - * securely. - * - sl_bt_external_bondingdb_data_local_ltk (0x3): Long Term Key - * (LTK) used as peripheral device. The value of this type must be stored - * securely. - * - sl_bt_external_bondingdb_data_remote_central_inf (0x4): - * Identification info used as a central device - * - sl_bt_external_bondingdb_data_local_central_inf (0x5): - * Identification info used as a central device - * - sl_bt_external_bondingdb_data_irk (0x6): Identity Resolving Key - * (IRK) of the remote device that is used for resolving its RPA addresses - * when the device is in privacy mode. The value of this type must be - * stored securely. - * - sl_bt_external_bondingdb_data_meta (0x7): Metadata about the - * bonding - * - sl_bt_external_bondingdb_data_gatt_client_config (0x8): The - * remote GATT client characteristic configurations - * - sl_bt_external_bondingdb_data_gatt_client_features (0x9): The - * remote GATT client supported features - * - sl_bt_external_bondingdb_data_gatt_db_hash (0xa): Latest local - * GATT database hash value that the remote client has seen for GATT - * robust caching feature - * @param[in] data_len Length of data in @p data - * @param[in] data Bonding data - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, - uint8_t type, - size_t data_len, - const uint8_t* data); - -/** @} */ // end addtogroup sl_bt_external_bondingdb - -/** - * @addtogroup sl_bt_resolving_list Address Resolving List - * @{ - * - * @brief Address Resolving List - * - * Provides support for adding and removing devices from the Resolving List in - * controller-based privacy. - * - * Adding a peer device to the Resolving List allows the Bluetooth controller to - * resolve the address when the peer device is using privacy and is transmitting - * with a Resolvable Private Address (RPA). When the controller has resolved an - * address in a received Bluetooth packet such as an advertisement, the - * corresponding event will report the peer device's identity address even if a - * Resolvable Private Address was used over the air. - * - * When the application has added a peer device to the Resolving List, the - * application may use the peer device's identity address in commands such as - * @ref sl_bt_connection_open or @ref sl_bt_sync_scanner_open even if the peer - * device is using privacy and is using a Resolvable Private Address over the - * air. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_resolving_list_add_device_by_bonding_id 0x005d0020 -#define sl_bt_cmd_resolving_list_add_device_by_address_id 0x015d0020 -#define sl_bt_cmd_resolving_list_remove_device_by_bonding_id 0x025d0020 -#define sl_bt_cmd_resolving_list_remove_device_by_address_id 0x035d0020 -#define sl_bt_cmd_resolving_list_remove_all_devices_id 0x045d0020 -#define sl_bt_rsp_resolving_list_add_device_by_bonding_id 0x005d0020 -#define sl_bt_rsp_resolving_list_add_device_by_address_id 0x015d0020 -#define sl_bt_rsp_resolving_list_remove_device_by_bonding_id 0x025d0020 -#define sl_bt_rsp_resolving_list_remove_device_by_address_id 0x035d0020 -#define sl_bt_rsp_resolving_list_remove_all_devices_id 0x045d0020 - -/** - * @brief Specifies the Privacy Mode used for a peer device in the Resolving - * List - */ -typedef enum -{ - sl_bt_resolving_list_privacy_mode_network = 0x0, /**< (0x0) Use Network - Privacy Mode for the - peer device */ - sl_bt_resolving_list_privacy_mode_device = 0x1 /**< (0x1) Use Device Privacy - Mode for the peer device */ -} sl_bt_resolving_list_privacy_mode_t; - -/***************************************************************************//** - * - * Add a device to the Resolving List based on its bonding handle. - * - * This command is not available if the application uses the external bonding - * database provided by the component - * bluetooth_feature_external_bonding_database. In that configuration the - * application can use the command @ref - * sl_bt_resolving_list_add_device_by_address and provide the peer's identity - * address and its Identity Resolving Key (IRK). - * - * @param[in] bonding The bonding handle - * @param[in] privacy_mode @parblock - * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for - * the peer device. Values: - * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network - * Privacy Mode for the peer device - * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device - * Privacy Mode for the peer device - * - * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network - * Privacy Mode for the peer device) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, - uint8_t privacy_mode); - -/***************************************************************************//** - * - * Add a device to the Resolving List based on its identity address and its - * Identity Resolving Key (IRK). - * - * This command is typically only needed when the application uses the external - * bonding database provided by the component - * bluetooth_feature_external_bonding_database. When the application uses the - * built-in bonding database, the command @ref - * sl_bt_resolving_list_add_device_by_bonding is more convenient. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * @param[in] key Identity Resolving Key (IRK) of the peer device in little - * endian format. - * @param[in] privacy_mode @parblock - * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for - * the peer device. Values: - * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network - * Privacy Mode for the peer device - * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device - * Privacy Mode for the peer device - * - * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network - * Privacy Mode for the peer device) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, - uint8_t address_type, - aes_key_128 key, - uint8_t privacy_mode); - -/***************************************************************************//** - * - * Remove a device from the Resolving List based on its bonding handle. - * - * This command is not available if the application uses the external bonding - * database provided by the component - * bluetooth_feature_external_bonding_database. In that configuration the - * application can use the command @ref - * sl_bt_resolving_list_remove_device_by_address and provide the peer's identity - * address. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Remove a device from the Resolving List based on its identity address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove all devices from the Resolving List. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_resolving_list_remove_all_devices(); - -/** @} */ // end addtogroup sl_bt_resolving_list - -/** - * @addtogroup sl_bt_accept_list Filter Accept List - * @{ - * - * @brief Filter Accept List - * - * Provides support for adding and removing devices from the Filter Accept List - * in the Bluetooth controller. - * - * The Filter Accept List allows filtering transmissions from other Bluetooth - * devices so that the local device only receives/accepts transmissions from the - * devices that it's interested in or wants to communicate with. Operations that - * support filtering provide a means to control how the Filter Accept List is - * used: - * - For advertising, use the command @ref sl_bt_advertiser_configure and @p - * flags bits @ref SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref - * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to control the - * advertising filter policy - * - For scanning, use the command @ref - * sl_bt_scanner_set_parameters_and_filter to control the scanning filter - * policy - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_accept_list_add_device_by_bonding_id 0x005e0020 -#define sl_bt_cmd_accept_list_add_device_by_address_id 0x015e0020 -#define sl_bt_cmd_accept_list_remove_device_by_bonding_id 0x025e0020 -#define sl_bt_cmd_accept_list_remove_device_by_address_id 0x035e0020 -#define sl_bt_cmd_accept_list_remove_all_devices_id 0x045e0020 -#define sl_bt_rsp_accept_list_add_device_by_bonding_id 0x005e0020 -#define sl_bt_rsp_accept_list_add_device_by_address_id 0x015e0020 -#define sl_bt_rsp_accept_list_remove_device_by_bonding_id 0x025e0020 -#define sl_bt_rsp_accept_list_remove_device_by_address_id 0x035e0020 -#define sl_bt_rsp_accept_list_remove_all_devices_id 0x045e0020 - -/***************************************************************************//** - * - * Add a device to the Filter Accept List based on its bonding handle. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Add a device to the Filter Accept List based on its identity address. - * - * Use the special address type @ref sl_bt_gap_anonymous_address to add an entry - * that matches all advertisements sent with no address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter - * Accept List entry with this type matches all advertisements sent with - * no address. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove a device from the Filter Accept List based on its bonding handle. - * - * @param[in] bonding The bonding handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding); - -/***************************************************************************//** - * - * Remove a device from the Filter Accept List based on its identity address. - * - * Use the special address type @ref sl_bt_gap_anonymous_address to remove an - * entry that matches all advertisements sent with no address. - * - * @param[in] address Bluetooth address of the peer device - * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device - * address type. Values: - * - sl_bt_gap_public_address (0x0): Public device address - * - sl_bt_gap_static_address (0x1): Static device address - * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter - * Accept List entry with this type matches all advertisements sent with - * no address. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, - uint8_t address_type); - -/***************************************************************************//** - * - * Remove all devices from the Filter Accept List. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_accept_list_remove_all_devices(); - -/** @} */ // end addtogroup sl_bt_accept_list - -/** - * @addtogroup sl_bt_ota OTA - * @{ - * - * @brief OTA - * - * Commands in this class are used for configuring OTA DFU using the Apploader. - * - * Note that this class is used on EFR series 1 and is not available for series - * 2 devices. The Apploader runs as a Bootloader communication plugin on series - * 2 and the Apploader plugin API supports setting device name and advertising - * data. Other configurations can be implemented in the Apploader plugin - * application space. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_ota_set_device_name_id 0x01100020 -#define sl_bt_cmd_ota_set_advertising_data_id 0x02100020 -#define sl_bt_cmd_ota_set_configuration_id 0x03100020 -#define sl_bt_cmd_ota_set_rf_path_id 0x04100020 -#define sl_bt_rsp_ota_set_device_name_id 0x01100020 -#define sl_bt_rsp_ota_set_advertising_data_id 0x02100020 -#define sl_bt_rsp_ota_set_configuration_id 0x03100020 -#define sl_bt_rsp_ota_set_rf_path_id 0x04100020 - -/***************************************************************************//** - * - * Set the device name to be used during the OTA update. The name is stored in - * the persistent store. Maximum name length is 17 bytes. - * - * Default is "OTA" if a name is not set. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] name_len Length of data in @p name - * @param[in] name OTA device name - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name); - -/***************************************************************************//** - * - * Set advertising packets in OTA. Maximum 31 bytes of data can be set. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] packet_type This value selects whether data is intended for - * advertising packets or scan response packets. - * - 2: OTA advertising packets - * - 4: OTA scan response packets - * @param[in] adv_data_len Length of data in @p adv_data - * @param[in] adv_data Data to be set - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, - size_t adv_data_len, - const uint8_t* adv_data); - -/***************************************************************************//** - * - * Set OTA configuration. The setting is stored in the persistent store. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] flags @parblock - * OTA configuration flags. This value is given as a bitmask. Flags: - * - * Bit 0: Advertising address - * - * - 0: Use public device address - * - 1: Use a random address - * - * Bit 1: Application update version check. Check the version number and - * product ID of the application upgrade before applying. If the version - * number of the current application can't be determined, this implementation - * will assume that it is OK to apply the new image. Note that this is not a - * security feature. - * - * - 0: Disable version check - * - 1: Enable version check - * - * Bit 2 to 31: Reserved - * - * Default value: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_configuration(uint32_t flags); - -/***************************************************************************//** - * - * Set RF path antenna for OTA. This command should be used only if the device - * has multiple antenna ports. The setting is stored in the persistent store. - * - * Note that this command is available for EFR series 1 devices only. - * - * @param[in] enable If enabled antenna selection is used in OTA, otherwise - * default antenna is used. - * @param[in] antenna Set antenna used in OTA. Value should be come from - * RAIL_AntennaSel_t enum. See antenna path selection in RAIL - * rail_chip_specific.h. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna); - -/** @} */ // end addtogroup sl_bt_ota - -/** - * @addtogroup sl_bt_coex Coexistence - * @{ - * - * @brief Coexistence - * - * Coexistence BGAPI class. Coexistence interface is enabled and initialized - * with sl_bt_init_coex_hal function. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_coex_set_options_id 0x00200020 -#define sl_bt_cmd_coex_set_parameters_id 0x02200020 -#define sl_bt_cmd_coex_set_directional_priority_pulse_id 0x03200020 -#define sl_bt_cmd_coex_get_parameters_id 0x04200020 -#define sl_bt_cmd_coex_get_counters_id 0x01200020 -#define sl_bt_rsp_coex_set_options_id 0x00200020 -#define sl_bt_rsp_coex_set_parameters_id 0x02200020 -#define sl_bt_rsp_coex_set_directional_priority_pulse_id 0x03200020 -#define sl_bt_rsp_coex_get_parameters_id 0x04200020 -#define sl_bt_rsp_coex_get_counters_id 0x01200020 - -/** - * @brief Coexistence configuration options - */ -typedef enum -{ - sl_bt_coex_option_enable = 0x100, /**< (0x100) Enable coexistence - feature */ - sl_bt_coex_option_tx_abort = 0x400, /**< (0x400) Abort transmission if - grant is denied */ - sl_bt_coex_option_high_priority = 0x800 /**< (0x800) Enable priority signal */ -} sl_bt_coex_option_t; - -/***************************************************************************//** - * - * Configure coexistence options at runtime. - * - * @param[in] mask Bitmask of following coexistence options to change - * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence - * feature - * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if - * grant is denied - * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority - * signal - * @param[in] options Bitmask of following coexistence option values to set - * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence - * feature - * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if - * grant is denied - * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority - * signal - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options); - -/***************************************************************************//** - * - * Configure coexistence parameters. - * - * @param[in] priority Coexistence priority threshold. Coexistence priority is - * toggled if priority is below this value. - * @param[in] request Coexistence request threshold. Coexistence request is - * toggled if priority is below this value. - * @param[in] pwm_period PWM functionality period length in 1 ms units - * @param[in] pwm_dutycycle PWM functionality duty cycle in percentage - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_parameters(uint8_t priority, - uint8_t request, - uint8_t pwm_period, - uint8_t pwm_dutycycle); - -/***************************************************************************//** - * - * Set Directional Priority Pulse Width. - * - * @param[in] pulse Directional priority pulse width in us - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse); - -/***************************************************************************//** - * - * Get the coexistence parameters. - * - * @param[out] priority Coexistence priority threshold. Coexistence priority is - * toggled if priority is below this value. - * @param[out] request Coexistence request threshold. Coexistence request is - * toggled if priority is below this value. - * @param[out] pwm_period PWM functionality period length in 1 ms units - * @param[out] pwm_dutycycle PWM functionality duty cycle in percentage - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, - uint8_t *request, - uint8_t *pwm_period, - uint8_t *pwm_dutycycle); - -/***************************************************************************//** - * - * Read coexistence statistic counters from the device. Response contains the - * list of uint32 type counter values. Counters in the list are in following - * order: low priority requested, high priority requested, low priority denied, - * high priority denied, low-priority TX aborted, and high-priority TX aborted. - * Passing a non-zero value also resets counters. - * - * @param[in] reset Reset counters if parameter value is not zero. - * @param[in] max_counters_size Size of output buffer passed in @p counters - * @param[out] counters_len On return, set to the length of output data written - * to @p counters - * @param[out] counters Coexistence statistic counters - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_coex_get_counters(uint8_t reset, - size_t max_counters_size, - size_t *counters_len, - uint8_t *counters); - -/** @} */ // end addtogroup sl_bt_coex - -/** - * @addtogroup sl_bt_cs Accurate Bluetooth Ranging - * @{ - * - * @brief Accurate Bluetooth Ranging - * - * This class provides commands and events for Accurate Bluetooth Ranging (ABR) - * between Bluetooth devices. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cs_security_enable_id 0x00590020 -#define sl_bt_cmd_cs_set_default_settings_id 0x01590020 -#define sl_bt_cmd_cs_create_config_id 0x02590020 -#define sl_bt_cmd_cs_remove_config_id 0x03590020 -#define sl_bt_cmd_cs_set_channel_classification_id 0x04590020 -#define sl_bt_cmd_cs_set_procedure_parameters_id 0x05590020 -#define sl_bt_cmd_cs_procedure_enable_id 0x06590020 -#define sl_bt_cmd_cs_set_antenna_configuration_id 0x07590020 -#define sl_bt_cmd_cs_read_local_supported_capabilities_id 0x08590020 -#define sl_bt_rsp_cs_security_enable_id 0x00590020 -#define sl_bt_rsp_cs_set_default_settings_id 0x01590020 -#define sl_bt_rsp_cs_create_config_id 0x02590020 -#define sl_bt_rsp_cs_remove_config_id 0x03590020 -#define sl_bt_rsp_cs_set_channel_classification_id 0x04590020 -#define sl_bt_rsp_cs_set_procedure_parameters_id 0x05590020 -#define sl_bt_rsp_cs_procedure_enable_id 0x06590020 -#define sl_bt_rsp_cs_set_antenna_configuration_id 0x07590020 -#define sl_bt_rsp_cs_read_local_supported_capabilities_id 0x08590020 - -/** - * @brief Specifies the role for the device during ABR procedure. - */ -typedef enum -{ - sl_bt_cs_role_initiator = 0x0, /**< (0x0) The device will initiate the - procedure */ - sl_bt_cs_role_reflector = 0x1 /**< (0x1) The device will reciprocate - transmission */ -} sl_bt_cs_role_t; - -/** - * @brief Defines the status of a given role for an ABR capable device. - */ -typedef enum -{ - sl_bt_cs_role_status_disable = 0x0, /**< (0x0) The given role is disabled */ - sl_bt_cs_role_status_enable = 0x1 /**< (0x1) The given role is enabled */ -} sl_bt_cs_role_status_t; - -/** - * @brief Defines the status of a companion signal. - */ -typedef enum -{ - sl_bt_cs_companion_signal_status_disable = 0x0, /**< (0x0) The companion - signal is disabled */ - sl_bt_cs_companion_signal_status_enable = 0x1 /**< (0x1) The companion - signal is enabled */ -} sl_bt_cs_companion_signal_status_t; - -/** - * @brief Defines the ABR procedure state for the device. - */ -typedef enum -{ - sl_bt_cs_procedure_state_disabled = 0x0, /**< (0x0) ABR procedures are - disabled */ - sl_bt_cs_procedure_state_enabled = 0x1 /**< (0x1) ABR procedures are enabled */ -} sl_bt_cs_procedure_state_t; - -/** - * @brief Defines the different modes for ABR steps. - */ -typedef enum -{ - sl_bt_cs_mode_rtt = 0x1, /**< (0x1) Round Trip Time (RTT) measurement */ - sl_bt_cs_mode_pbr = 0x2, /**< (0x2) Phase-Based Ranging (PBR) - measurement */ - sl_bt_cs_submode_disabled = 0xff /**< (0xff) Submode disabled for the - procedure. */ -} sl_bt_cs_mode_t; - -/** - * @brief Defines the Round Trip Time (RTT) payload types used during the ABR - * sequence. - */ -typedef enum -{ - sl_bt_cs_rtt_type_coarse = 0x0, /**< (0x0) RTT Coarse */ - sl_bt_cs_rtt_type_fractional_96_bit_sounding = 0x2 /**< (0x2) RTT Fractional - with 96-bit Sounding - Sequence */ -} sl_bt_cs_rtt_type_t; - -/** - * @brief Specifies the ABR channel selection algorithms. - */ -typedef enum -{ - sl_bt_cs_channel_selection_algorithm_3b = 0x0, /**< (0x0) - Use - Channel - Selection - Algorithm - #3b - for - non-mode - 0 ABR - steps */ - sl_bt_cs_channel_selection_algorithm_3c = 0x1, /**< (0x1) - Use - Channel - Selection - Algorithm - #3c - for - non-mode - 0 ABR - steps */ - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved = 0x2 /**< (0x2) - Use - Interleaved - shape - for - user - specified - channel - sequence */ -} sl_bt_cs_channel_selection_algorithm_t; - -/** - * @brief Specifies the ch3c shapes. - */ -typedef enum -{ - sl_bt_cs_ch3c_shape_hat = 0x0, /**< (0x0) Use Hat shape for user - specified channel sequence */ - sl_bt_cs_chc3_shape_interleaved = 0x1 /**< (0x1) Use Interleaved shape for - user specified channel sequence */ -} sl_bt_cs_ch3c_shape_t; - -/** - * @brief Describes the current status of the procedure or subevents. - */ -typedef enum -{ - sl_bt_cs_done_status_complete = 0x0, /**< (0x0) All results - complete for the - ABR procedure or - subevent */ - sl_bt_cs_done_status_partial_results_continue = 0x1, /**< (0x1) Partial - results with more - to follow */ - sl_bt_cs_done_status_current_aborted = 0xfe, /**< (0xfe) Current ABR - procedure or - subevent aborted */ - sl_bt_cs_done_status_all_aborted = 0xff /**< (0xff) Current and - all subsequent - subevents in the - procedure aborted */ -} sl_bt_cs_done_status_t; - -/** - * @brief Describes the abort reasons for ABR procedures and subevents and is - * represented by 4 bits in a byte - */ -typedef enum -{ - sl_bt_cs_abort_reason_no_abort = 0x0, /**< (0x0) Not aborted */ - sl_bt_cs_abort_reason_host_request = 0x1, /**< (0x1) Local or remote - host request */ - sl_bt_cs_abort_reason_insufficient_channels = 0x2, /**< (0x2) Filtered channel - has less than 15 - channels */ - sl_bt_cs_abort_reason_no_map_update = 0x3, /**< (0x3) Channel map - update instant has - passed */ - sl_bt_cs_abort_reason_unspecified = 0xf /**< (0xf) Unspecified - reasons for abortion */ -} sl_bt_cs_abort_reason_t; - -/** - * @brief Specifies the role for the device during ABR procedure. - */ -typedef enum -{ - sl_bt_cs_config_state_removed = 0x0, /**< (0x0) The ABR device configuration - is removed */ - sl_bt_cs_config_state_created = 0x1 /**< (0x1) The ABR device configuration - is created */ -} sl_bt_cs_config_state_t; - -/** - * @addtogroup sl_bt_evt_cs_security_enable_complete sl_bt_evt_cs_security_enable_complete - * @{ - * @brief Indicates that a locally initiated ABR security start procedure has - * completed or the local controller has responded to a channel security request - * from the remote controller - */ - -/** @brief Identifier of the security_enable_complete event */ -#define sl_bt_evt_cs_security_enable_complete_id 0x005900a0 - -/***************************************************************************//** - * @brief Data structure of the security_enable_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_security_enable_complete_s -{ - uint8_t connection; /**< Connection handle */ -}); - -typedef struct sl_bt_evt_cs_security_enable_complete_s sl_bt_evt_cs_security_enable_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_security_enable_complete - -/** - * @addtogroup sl_bt_evt_cs_config_complete sl_bt_evt_cs_config_complete - * @{ - * @brief Indicates that a locally initiated ABR configuration procedure has - * completed or the local controller has responded to an ABR configuration - * request from the remote controller - */ - -/** @brief Identifier of the config_complete event */ -#define sl_bt_evt_cs_config_complete_id 0x015900a0 - -/***************************************************************************//** - * @brief Data structure of the config_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_config_complete_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t config_id; /**< ABR configuration - identifier. - - Range: 0 to 3 */ - uint16_t status; /**< SL_STATUS_OK if - successful. Error code - otherwise. */ - uint8_t config_state; /**< Enum @ref - sl_bt_cs_config_state_t. - ABR configuration state - Values: - - sl_bt_cs_config_state_removed - (0x0): The ABR - device configuration - is removed - - sl_bt_cs_config_state_created - (0x1): The ABR - device configuration - is created */ - uint8_t main_mode_type; /**< Enum @ref - sl_bt_cs_mode_t. Main - mode type. Values: - - sl_bt_cs_mode_rtt - (0x1): Round Trip - Time (RTT) - measurement - - sl_bt_cs_mode_pbr - (0x2): - Phase-Based Ranging - (PBR) measurement - - sl_bt_cs_submode_disabled - (0xff): Submode - disabled for the - procedure. */ - uint8_t sub_mode_type; /**< Enum @ref - sl_bt_cs_mode_t. Sub mode - type. Values: - - sl_bt_cs_mode_rtt - (0x1): Round Trip - Time (RTT) - measurement - - sl_bt_cs_mode_pbr - (0x2): - Phase-Based Ranging - (PBR) measurement - - sl_bt_cs_submode_disabled - (0xff): Submode - disabled for the - procedure. */ - uint8_t min_main_mode_steps; /**< Minimum number of ABR - main mode steps to be - executed prior to a sub - mode step. - - Range: 1 to 160 */ - uint8_t max_main_mode_steps; /**< Maximum number of ABR - main mode steps to be - executed prior to a sub - mode step. - - Range: 1 to 160 */ - uint8_t main_mode_repetition; /**< Number of main mode steps - taken from the end of the - last ABR subevent to be - repeated at the beginning - of the current ABR - subevent directly after - the last Mode 0 step of - that event. - - Range: 0 to 3 */ - uint8_t mode_calibration_steps; /**< Number of calibration - mode steps to be included - at the beginning of the - test ABR subevent. - - Range: 1 to 3 */ - uint8_t role; /**< Enum @ref - sl_bt_cs_role_t. Device - role during the ABR - procedure Values: - - sl_bt_cs_role_initiator - (0x0): The device - will initiate the - procedure - - sl_bt_cs_role_reflector - (0x1): The device - will reciprocate - transmission */ - uint8_t rtt_type; /**< Enum @ref - sl_bt_cs_rtt_type_t. RTT - payload type used in the - ABR procedure Values: - - sl_bt_cs_rtt_type_coarse - (0x0): RTT Coarse - - sl_bt_cs_rtt_type_fractional_96_bit_sounding - (0x2): RTT - Fractional with - 96-bit Sounding - Sequence */ - uint8_t cs_sync_phy; /**< Enum @ref - sl_bt_gap_phy_t. Used PHY - for ABR SYNC exchanges - during a procedure - Values: - - sl_bt_gap_phy_1m - (0x1): 1M PHY */ - sl_bt_cs_channel_map_t channel_map; /**< A fixed length byte array - of 10 bytes consisting of - 79 1-bit fields. - - The nth field (in the - range 0 to 78) contains - the value for the ABR - channel index n. - - - Bit value 0: Channel - n is disabled - - Bit value 1: Channel - n is enabled - - The rest of most - significant bits are - reserved for future use - and must be set to 0. - Channels n = 0, 1, 23, - 24, 25, 77 and 78 shall - be ignored and not used - for ABR. At least 15 - channels shall be marked - as used. */ - uint8_t channel_map_repetition; /**< Number of times the - channel_map field will be - cycled through for - non-Mode 0 steps within a - ABR procedure. - - Range: 0x01 to 0xFF */ - uint8_t channel_selection_type; /**< Enum @ref - sl_bt_cs_channel_selection_algorithm_t. - ABR algorithm to be used - during the procedure for - non-mode 0 steps Value: - - sl_bt_cs_channel_selection_algorithm_3b - (0x0): Use - Channel Selection - Algorithm #3b for - non-mode 0 ABR steps - - sl_bt_cs_channel_selection_algorithm_3c - (0x1): Use - Channel Selection - Algorithm #3c for - non-mode 0 ABR steps - - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved - (0x2): Use - Interleaved shape for - user specified - channel sequence */ - uint8_t ch3c_shape; /**< Enum @ref - sl_bt_cs_ch3c_shape_t. - Shape for user-specified - channel sequence Values: - - sl_bt_cs_ch3c_shape_hat - (0x0): Use Hat - shape for user - specified channel - sequence - - sl_bt_cs_chc3_shape_interleaved - (0x1): Use - Interleaved shape for - user specified - channel sequence */ - uint8_t ch3c_jump; /**< Number of channels - skipped in each rising - and falling sequence - - Range: 0x03 to 0x08 */ - uint8_t companion_signal_enable; /**< Enum @ref - sl_bt_cs_companion_signal_status_t. - Enabled or disabled - companion signal status - Values: - - sl_bt_cs_companion_signal_status_disable - (0x0): The - companion signal is - disabled - - sl_bt_cs_companion_signal_status_enable - (0x1): The - companion signal is - enabled */ - uint8_t ip1_time_us; /**< Interlude time in - microseconds between the - RTT packets. Values: - 0x0A, 0x14, 0x1E, 0x28, - 0x32, 0x3C, 0x50, or - 0x91. All other values - are reserved for future - use. */ - uint8_t ip2_time_us; /**< Interlude time in - microseconds between the - CS tones. Values: 0x0A, - 0x14, 0x1E, 0x28, 0x32, - 0x3C, 0x50, or 0x91. All - other values are reserved - for future use. */ - uint8_t fcs_time_us; /**< Time in microseconds for - frequency changes. - Values: 0x0F, 0x14, 0x1E, - 0x28, 0x32, 0x3C, 0x50, - 0x64, 0x78, or 0x96. All - other values are reserved - for future use. */ - uint8_t pm_time_us; /**< Time in microseconds for - the phase measurement - period of the CS tones. - Values: 0x0A, 0x14, or - 0x28. All other values - are reserved for future - use. */ -}); - -typedef struct sl_bt_evt_cs_config_complete_s sl_bt_evt_cs_config_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_config_complete - -/** - * @addtogroup sl_bt_evt_cs_procedure_enable_complete sl_bt_evt_cs_procedure_enable_complete - * @{ - * @brief Indicates the controller has scheduled a new ABR procedure - * measurement, as a result of @ref sl_bt_cs_procedure_enable command or - * disabled an ongoing, as a result of @ref sl_bt_cs_procedure_enable command. - */ - -/** @brief Identifier of the procedure_enable_complete event */ -#define sl_bt_evt_cs_procedure_enable_complete_id 0x025900a0 - -/***************************************************************************//** - * @brief Data structure of the procedure_enable_complete event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_procedure_enable_complete_s -{ - uint8_t connection; /**< Connection handle */ - uint8_t config_id; /**< ABR configuration identifier. - - Range: 0 to 3 */ - uint16_t status; /**< SL_STATUS_OK if successful. Error code - otherwise. */ - uint8_t state; /**< Enum @ref sl_bt_cs_procedure_state_t. - ABR procedure enabled or disabled - Values: - - sl_bt_cs_procedure_state_disabled - (0x0): ABR procedures are - disabled - - sl_bt_cs_procedure_state_enabled - (0x1): ABR procedures are - enabled */ - uint8_t antenna_config; /**< Antenna configuration index - - Range: 0 to 7 */ - int8_t tx_power; /**< Transmit power level used in the - transmission. Units: dBm. - - Range: -127 to +20 - - Value: 0x07F. Transmit power level - is unavailable */ - uint32_t subevent_len; /**< Duration for each subevent in - microseconds - - Range: 1250 μs to 4 s */ - uint8_t subevents_per_interval; /**< Number of subevents anchored off the - same ACL connection event - - Range: 1 to 16 */ - uint16_t subevent_interval; /**< Duration in microseconds between - consecutive ABR subevents anchored off - the same ACL connection event. Units: - 0.625 ms. */ - uint16_t event_interval; /**< Number of ACL connection events between - consecutive ABR event anchor points */ - uint16_t procedure_interval; /**< Number of ACL connection events between - consecutive ABR procedure anchor points */ - uint16_t procedure_count; /**< Number of procedures to continue until - disabled. Maximum number of procedures - to be scheduled. - - Range: 0x01 to 0xFFFF. */ -}); - -typedef struct sl_bt_evt_cs_procedure_enable_complete_s sl_bt_evt_cs_procedure_enable_complete_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_procedure_enable_complete - -/** - * @addtogroup sl_bt_evt_cs_result sl_bt_evt_cs_result - * @{ - * @brief Reports results of every ABR subevent within the ABR procedure - */ - -/** @brief Identifier of the result event */ -#define sl_bt_evt_cs_result_id 0x035900a0 - -/***************************************************************************//** - * @brief Data structure of the result event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cs_result_s -{ - uint8_t connection; /**< Connection handle. Returns a - SL_BT_INVALID_CONNECTION_HANDLE (0xFF) - when triggered as a result of @ref - sl_bt_cs_test_start command */ - uint8_t config_id; /**< ABR configuration identifier - - Range: 0 to 3 */ - uint16_t start_acl_conn_event; /**< Starting an ACL connection event count - for the results reported in the event. - This is reported only in the first - subevent in the procedure. For - subsequent subevents, this value is - set to 0. */ - uint16_t procedure_counter; /**< Indicates the associated ABR procedure - count for the results reported in this - event */ - int16_t frequency_compensation; /**< Frequency compensation value. Units: - 0.01 ppm (15-bit signed integer). - - Range: -10000 to 10000 - - Value: 0xC000. Frequency - compensation value is not - available or the role is not - initiator. This is reported only - in the first subevent in the - procedure. For subsequent - subevents, this value is set to 0. */ - uint8_t procedure_done_status; /**< Enum @ref sl_bt_cs_done_status_t. - Current status of the ABR procedure - Values: - - sl_bt_cs_done_status_complete - (0x0): All results complete - for the ABR procedure or subevent - - sl_bt_cs_done_status_partial_results_continue - (0x1): Partial results with - more to follow - - sl_bt_cs_done_status_current_aborted - (0xfe): Current ABR procedure - or subevent aborted - - sl_bt_cs_done_status_all_aborted - (0xff): Current and all - subsequent subevents in the - procedure aborted */ - uint8_t subevent_done_status; /**< Enum @ref sl_bt_cs_done_status_t. - Current status of the ABR subevent - Values: - - sl_bt_cs_done_status_complete - (0x0): All results complete - for the ABR procedure or subevent - - sl_bt_cs_done_status_partial_results_continue - (0x1): Partial results with - more to follow - - sl_bt_cs_done_status_current_aborted - (0xfe): Current ABR procedure - or subevent aborted - - sl_bt_cs_done_status_all_aborted - (0xff): Current and all - subsequent subevents in the - procedure aborted */ - uint8_t abort_reason; /**< Enum @ref sl_bt_cs_abort_reason_t. - Indicates the abort reason when the - procedure_done_status or - subevent_done_status is set to 0xF, - otherwise the default value is set to - zero. The first 4 bits are related to - the procedure abort reasons and the - last 4 bits are related to the - subevent done. Values: - - sl_bt_cs_abort_reason_no_abort - (0x0): Not aborted - - sl_bt_cs_abort_reason_host_request - (0x1): Local or remote host - request - - sl_bt_cs_abort_reason_insufficient_channels - (0x2): Filtered channel has - less than 15 channels - - sl_bt_cs_abort_reason_no_map_update - (0x3): Channel map update - instant has passed - - sl_bt_cs_abort_reason_unspecified - (0xf): Unspecified reasons for - abortion */ - int8_t reference_power_level; /**< Reference power level used by the - transmission. Units: dBm. - - Range: -127 to 20 - - Value: 0x07F. The reference power - level is not applicable */ - uint8_t num_antenna_paths; /**< Number of antenna paths supported by - the local controller for the ABR tone - exchanges. - - Range: 1 to 4. The number of - antenna paths used during the - phase measurement stage of the ABR - step - - Value: 0. Phase measurement does - not occur during the ABR step, - therefore ignored */ - uint8_t num_steps; /**< Number of steps in the ABR subevent - for which results are reported. - - Range: 1 to 160 */ - uint8array data; /**< The result data is structured as - follows: - - step_status: 1 octet for each - num_steps. 0x00 for step scheduled - and reported. 0xFE for step - aborted. - - step_mode: 1 octet for each - num_steps. Mode type. Range 0 to - 3. - - step_channel: 1 octet for each - num_steps. Channel index. Range 1 - to 78. - - step_data_length: 1 octet for each - num_steps. Length of mode and role - specific information being - reported. Range 0x00 to 0xFF. - - step_data: step_data_length octet - for each corresponding steps in - num_steps. */ -}); - -typedef struct sl_bt_evt_cs_result_s sl_bt_evt_cs_result_t; - -/** @} */ // end addtogroup sl_bt_evt_cs_result - -/***************************************************************************//** - * - * Start or restart ABR security start procedure for the specified connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_security_enable_complete - Triggered when ABR security - * start procedure has completed. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_security_enable(uint8_t connection); - -/***************************************************************************//** - * - * Set the default ABR settings for the specified connection. By default, all - * roles are disabled and the antenna is set to 1. - * - * @param[in] connection Connection handle - * @param[in] initiator_status Enum @ref sl_bt_cs_role_status_t. Enable or - * disable status of the Initiator role. Values: - * - sl_bt_cs_role_status_disable (0x0): The given role is disabled - * - sl_bt_cs_role_status_enable (0x1): The given role is enabled - * @param[in] reflector_status Enum @ref sl_bt_cs_role_status_t. Enable or - * disable status of the Reflector role. Values: - * - sl_bt_cs_role_status_disable (0x0): The given role is disabled - * - sl_bt_cs_role_status_enable (0x1): The given role is enabled - * @param[in] antenna_identifier Antenna identifier to be used for ABR sync - * packets. - * - Range: 1 to 4 - * @param[in] max_tx_power Maximum transmit power level to be used in all ABR - * transmissions. Units: dBm. - * - Range: -127 to +20 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, - uint8_t initiator_status, - uint8_t reflector_status, - uint8_t antenna_identifier, - int8_t max_tx_power); - -/***************************************************************************//** - * - * Create a new ABR configuration in the local and remote controller. The role - * used in this command must be enabled prior to issuing this command using @ref - * sl_bt_cs_set_default_settings command. - * - * @param[in] connection The connection handle - * @param[in] config_id ABR configuration identifier. - * - Range: 0 to 3 - * @param[in] create_context Defines in which device the created configuration - * will be written - * - Value: 0x00. Write ABR configuration in the local controller only - * - Value: 0x01. Write ABR configuration in both the local and remote - * controller using a configuration procedure - * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] min_main_mode_steps Minimum number of ABR main mode steps to be - * executed prior to a sub mode step. - * - Range: 1 to 160 - * @param[in] max_main_mode_steps Maximum number of ABR main mode steps to be - * executed prior to a sub mode step. - * - Range: 1 to 160 - * @param[in] main_mode_repetition Number of main mode steps taken from the end - * of the last ABR subevent to be repeated at the beginning of the current ABR - * subevent directly after the value r last Mode 0 step of that event. - * - Range: 0 to 3 - * @param[in] mode_calibration_steps Number of Mode 0 steps to be included at - * the beginning of the test ABR subevent - * - Range: 1 to 3 - * @param[in] role Enum @ref sl_bt_cs_role_t. Device's role during the ABR - * procedure Values: - * - sl_bt_cs_role_initiator (0x0): The device will initiate the - * procedure - * - sl_bt_cs_role_reflector (0x1): The device will reciprocate - * transmission - * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in - * the ABR procedure Values: - * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse - * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT - * Fractional with 96-bit Sounding Sequence - * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC - * exchanges during a procedure Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * @param[in] channel_map @parblock - * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. - * - * The nth such field (in the range 0 to 78) contains the value for the ABR - * channel index n. - * - * - Bit value 0: Channel n is disabled - * - Bit value 1: Channel n is enabled - * - * The rest of most significant bits are reserved for future use and must be - * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not - * used for ABR. At least 15 channels shall be marked as used. - * @endparblock - * @param[in] channel_map_repetition Number of times the channel_map field will - * be cycled through for non-Mode 0 steps within an ABR procedure. - * - Range: 0x01 to 0xFF - * @param[in] channel_selection_type Enum @ref - * sl_bt_cs_channel_selection_algorithm_t. Channel selection algorithm Values: - * - sl_bt_cs_channel_selection_algorithm_3b (0x0): Use Channel - * Selection Algorithm #3b for non-mode 0 ABR steps - * - sl_bt_cs_channel_selection_algorithm_3c (0x1): Use Channel - * Selection Algorithm #3c for non-mode 0 ABR steps - * - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved - * (0x2): Use Interleaved shape for user specified channel sequence - * @param[in] ch3c_shape Enum @ref sl_bt_cs_ch3c_shape_t. Ch3c shape Values: - * - sl_bt_cs_ch3c_shape_hat (0x0): Use Hat shape for user specified - * channel sequence - * - sl_bt_cs_chc3_shape_interleaved (0x1): Use Interleaved shape for - * user specified channel sequence - * @param[in] ch3c_jump Number of channels skipped in each rising and falling - * sequence. - * - Range: 2 to 8 - * @param[in] companion_signal_state Enum @ref - * sl_bt_cs_companion_signal_status_t. Companion device's signal status - * Values: - * - sl_bt_cs_companion_signal_status_disable (0x0): The companion - * signal is disabled - * - sl_bt_cs_companion_signal_status_enable (0x1): The companion - * signal is enabled - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration - * procedure completed - * - ******************************************************************************/ -sl_status_t sl_bt_cs_create_config(uint8_t connection, - uint8_t config_id, - uint8_t create_context, - uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t min_main_mode_steps, - uint8_t max_main_mode_steps, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - const sl_bt_cs_channel_map_t *channel_map, - uint8_t channel_map_repetition, - uint8_t channel_selection_type, - uint8_t ch3c_shape, - uint8_t ch3c_jump, - uint8_t companion_signal_state); - -/***************************************************************************//** - * - * Remove an ABR configuration from the local controller. - * - * @param[in] connection Connection handle - * @param[in] config_id ABR configuration identifier - * - Range: 0 to 3 - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration - * procedure is completed - * - ******************************************************************************/ -sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id); - -/***************************************************************************//** - * - * Update the channel classification for ABR. This classification persists until - * overwritten with a subsequent command or until the system is reset. - * - * @param[in] channel_map @parblock - * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. - * - * The nth field (in the range 0 to 78) contains the value for the link layer - * channel index n. - * - * - Bit value 0: Channel n is disabled. - * - Bit value 1: Channel n is enabled. - * - * The rest of most significant bits are reserved for future use and must be - * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not - * used for ABR. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map); - -/***************************************************************************//** - * - * Set the parameters for scheduling ABR procedures with the remote device. - * - * @param[in] connection The connection handle - * @param[in] config_id ABR configuration identifier. - * - Range: 0 to 3. - * @param[in] max_procedure_len Maximum duration for each measurement procedure. - * Value in units of 0.625 ms. - * - Range: 0x0001 to 0xFFFF. - * - Time: N x 0.625ms. N being the input. - * - Time range: 0.625 ms to 40.959375 s. - * @param[in] min_procedure_interval Minimum duration in number of connection - * events between consecutive measurement procedure. - * - Range: 0x01 to 0xFFFF. - * @param[in] max_procedure_interval Maximum duration in number of connection - * events between consecutive measurement procedure. - * - Range: 0x01 to 0xFFFF. - * @param[in] max_procedure_count Maximum number of ABR procedures to be - * scheduled - * - Range: 0x01 to 0xFFFF: Maximum number of procedures to be scheduled. - * - Value: 0x00. Procedures to continue until disabled. - * @param[in] min_subevent_len Minimum suggested duration for each ABR subevent. - * Units: microseconds. - * - Range: 0x01 to 0xFFFFFF - * - Time range: 1250 us to 4s - * @param[in] max_subevent_len Maximum suggested duration for each ABR subevent. - * Units: microseconds. - * - Range: 0x01 to 0xFFFFFF - * - Time range: 1250 us to 4s - * @param[in] tone_antenna_config_selection Antenna configuration index - * - Range: 0 to 7 - * @param[in] phy Enum @ref sl_bt_gap_phy_t. PHY on which the ABR transmission - * will take place Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports - * @param[in] tx_pwr_delta Transmit power delta. Units: dB. - * - Value: 0x80. Host does not have a recommendation for transmit power - * delta - * @param[in] preferred_peer_antenna Preferred peer-ordered antenna elements to - * be used by the remote device for the antenna configuration denoted by the - * tone antenna config selection. - * - Bit 0: Use first ordered antenna element - * - Bit 1: Use second ordered antenna element - * - Bit 2: Use third ordered antenna element - * - Bit 3: Use fourth ordered antenna element - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, - uint8_t config_id, - uint16_t max_procedure_len, - uint16_t min_procedure_interval, - uint16_t max_procedure_interval, - uint16_t max_procedure_count, - uint32_t min_subevent_len, - uint32_t max_subevent_len, - uint8_t tone_antenna_config_selection, - uint8_t phy, - int8_t tx_pwr_delta, - uint8_t preferred_peer_antenna); - -/***************************************************************************//** - * - * Enable or disable scheduling ABR procedures with the remote device. - * - * @param[in] connection The connection handle - * @param[in] enable Enum @ref sl_bt_cs_procedure_state_t. Enabled or disabled - * ABR procedure state. Values: - * - sl_bt_cs_procedure_state_disabled (0x0): ABR procedures are - * disabled - * - sl_bt_cs_procedure_state_enabled (0x1): ABR procedures are - * enabled - * @param[in] config_id ABR configuration identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_procedure_enable_complete - Triggered when local - * controller has scheduled or disabled an ABR procedure measurement - * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to - * report for every ABR event within the ABR procedure - * - ******************************************************************************/ -sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, - uint8_t enable, - uint8_t config_id); - -/***************************************************************************//** - * - * Set the antenna configuration for the ABR feature. - * - * @param[in] antenna_element_offset_len Length of data in @p - * antenna_element_offset - * @param[in] antenna_element_offset Offset of each antenna, each element is a - * signed 16-bit integer stored in two consecutive bytes in little-endian - * order. Units: 1 cm. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, - const uint8_t* antenna_element_offset); - -/***************************************************************************//** - * - * Read the ABR capabilities of the local controller. - * - * @param[out] num_config The number of ABR configurations supported per - * connection. - * - Range: 0x01-0x04 - * @param[out] max_consecutive_procedures The maximum number of consecutive ABR - * procedures supported. - * - 0x00: Fixed number of consecutive procedures and for an - * indefinite number of procedures until termination - * - 0x0001-0xFFFF: Maximum number of consecutive procedures - * supported - * @param[out] num_antennas The number of antenna elements available for ABR - * tone exchanges. - * - Range: 0x01-0x04 - * @param[out] max_antenna_paths The maximum number of antenna paths supported. - * - Range: 0x01-0x04 - * @param[out] roles This value is a bitmask of flags to indicate which ABR - * roles are supported by the controller. Flags: - * - 0x01, bit 0: Initiator role - * - 0x02, bit 1: Reflector role - * @param[out] optional_modes This value is a bitmask of flags to indicate which - * Optional ABR modes are supported. Flags: - * - 0x02, bit 0: Mode 3 is supported - * @param[out] rtt_capability This value is a bitmask of flags to indicate which - * Round Trip Time (RTT) ABR capabilities accuracy requirement in @p - * rtt_aa_only_n, @p rtt_sounding_n, and @p rtt_random_payload. Flags: - * - 0x01, bit 0: 10 ns time-of-flight (ToF) precision requirement - * for @p rtt_aa_only if set; otherwise 150 ns ToF - * - 0x02, bit 1: 10 ns ToF precision requirement for @p rtt_sounding - * if set; otherwise 150 ns ToF - * - 0x04, bit 2: 10 ns ToF precision requirement for @p - * rtt_random_payload if set; otherwise 150 ns ToF - * @param[out] rtt_aa_only RTT Access Address(AA) is supported by the controller - * - 0x00: RTT AA Only is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] rtt_sounding RTT Sounding is supported by the controller - * - 0x00: RTT Sounding is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] rtt_random_payload RTT Random Payload is supported by the - * controller - * - 0x00: RTT Random Payload is not supported - * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision - * requirements - * @param[out] optional_cs_sync_phys This value is a bitmask of flags to - * indicate which ABR SYNC packages supported in an specific PHY. Flags: - * - 0x02, bit 1: LE 2M PHY ABR SYNC packages are supported - * @param[out] optional_subfeatures This value is a bitmask of flags to indicate - * which Optional ABR subfeatures supported is supported. Flags: - * - 0x01, bit 0: ABR Companion Signal is supported - * - 0x02, bit 1: ABR with zero Frequency Actuation Error relative to - * Mode 0 transmissions in reflector role is supported - * - 0x04, bit 2: ABR Channel Selection Algorithm #3c is supported - * - 0x08, bit 3: ABR phase-based ranging from a sounding sequence is - * supported - * @param[out] optional_t_ip1_times This value is a bitmask of flags to indicate - * which Time for Interlude Period 1 (IP1) supported is supported. Flags: - * - 0x0001, bit 0: Time durantion of 10 microseconds is supported - * - 0x0002, bit 1: Time durantion of 20 microseconds is supported - * - 0x0004, bit 2: Time durantion of 30 microseconds is supported - * - 0x0008, bit 3: Time durantion of 40 microseconds is supported - * - 0x0010, bit 4: Time durantion of 50 microseconds is supported - * - 0x0020, bit 5: Time durantion of 60 microseconds is supported - * - 0x0040, bit 6: Time durantion of 80 microseconds is supported - * @param[out] optional_t_ip2_times This value is a bitmask of flags to indicate - * which Time for Interlude Period 2 (IP2) supported is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * - 0x0004, bit 2: Time duration of 30 microseconds is supported - * - 0x0008, bit 3: Time duration of 40 microseconds is supported - * - 0x0010, bit 4: Time duration of 50 microseconds is supported - * - 0x0020, bit 5: Time duration of 60 microseconds is supported - * - 0x0040, bit 6: Time duration of 80 microseconds is supported - * @param[out] optional_t_fcs_times This value is a bitmask of flags to indicate - * which Time for Frequency Change Spaceing (FCS) is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * - 0x0004, bit 2: Time duration of 30 microseconds is supported - * - 0x0008, bit 3: Time duration of 40 microseconds is supported - * - 0x0010, bit 4: Time duration of 50 microseconds is supported - * - 0x0020, bit 5: Time duration of 60 microseconds is supported - * - 0x0040, bit 6: Time duration of 80 microseconds is supported - * - 0x0100, bit 7: Time duration of 100 microseconds is supported - * - 0x0200, bit 8: Time duration of 120 microseconds is supported - * @param[out] optional_t_pm_times This value is a bitmask of flags to indicate - * which Time for Phase Measurement (PM) supported is supported. Flags: - * - 0x0001, bit 0: Time duration of 10 microseconds is supported - * - 0x0002, bit 1: Time duration of 20 microseconds is supported - * @param[out] t_sw_times Time in microseconds for the antenna switch period of - * the ABR tones. - * - Values: 0x02, 0x02, 0x04 and 0x0A - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, - uint16_t *max_consecutive_procedures, - uint8_t *num_antennas, - uint8_t *max_antenna_paths, - uint8_t *roles, - uint8_t *optional_modes, - uint8_t *rtt_capability, - uint8_t *rtt_aa_only, - uint8_t *rtt_sounding, - uint8_t *rtt_random_payload, - uint8_t *optional_cs_sync_phys, - uint16_t *optional_subfeatures, - uint16_t *optional_t_ip1_times, - uint16_t *optional_t_ip2_times, - uint16_t *optional_t_fcs_times, - uint16_t *optional_t_pm_times, - uint8_t *t_sw_times); - -/** @} */ // end addtogroup sl_bt_cs - -/** - * @addtogroup sl_bt_cs_test Accurate Bluetooth Ranging Test - * @{ - * - * @brief Accurate Bluetooth Ranging Test - * - * This class provides optional test commands and events for ABR between - * Bluetooth devices. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cs_test_start_id 0x005a0020 -#define sl_bt_rsp_cs_test_start_id 0x005a0020 - -/** - * @brief Defines tone extension for ABR test - */ -typedef enum -{ - sl_bt_cs_test_tone_extension_both_without = 0x0, /**< (0x0) Initiator and - Reflector tones - sent without tone - extension */ - sl_bt_cs_test_tone_extension_reflector_without = 0x1, /**< (0x1) Initiator - tone sent with - extension; - Reflector tone sent - without extension */ - sl_bt_cs_test_tone_extension_initiator_without = 0x2, /**< (0x2) Initiator - tone sent without - extension; - Reflector tone sent - with extension */ - sl_bt_cs_test_tone_extension_both_with = 0x3, /**< (0x3) Initiator and - Reflector tones - sent with extension */ - sl_bt_cs_test_tone_extension_round_robin = 0x4 /**< (0x4) Loop through - values 0x00 to 0x03 */ -} sl_bt_cs_test_tone_extension_t; - -/** - * @brief This defines sounding sequence marker for ABR test - */ -typedef enum -{ - sl_bt_cs_test_sounding_sequence_marker_1 = 0x0, /**< (0x0) Use - 0b0011 as the - Sounding - Sequence marker */ - sl_bt_cs_test_sounding_sequence_marker_2 = 0x1, /**< (0x1) Use - 0b1100 as the - Sounding - Sequence marker */ - sl_bt_cs_test_sounding_sequence_marker_round_robin = 0x2 /**< (0x2) Loop - through 0b0011 - and 0b1100 */ -} sl_bt_cs_test_sounding_sequence_marker_t; - -/***************************************************************************//** - * - * Start a single ABR procedure using the given configuration. The reflector - * must be initialized before starting the initiator. To stop an ongoing test, - * use the @ref sl_bt_test_dtm_end command. - * - * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values : - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: - * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement - * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement - * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the - * procedure. - * @param[in] main_mode_repetition Number of main mode steps taken from the end - * of the last ABR subevent to be repeated at the beginning of the current ABR - * subevent directly after the last Mode 0 step of that event. - * - Range: 0 to 3 - * @param[in] mode_calibration_steps Number of calibration mode steps to be - * included at the beginning of the test ABR subevent - * - Range: 1 to 3 - * @param[in] role Enum @ref sl_bt_cs_role_t. Role during ABR procedure Values: - * - sl_bt_cs_role_initiator (0x0): The device will initiate the - * procedure - * - sl_bt_cs_role_reflector (0x1): The device will reciprocate - * transmission - * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in - * the ABR procedure Values: - * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse - * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT - * Fractional with 96-bit Sounding Sequence - * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC - * exchanges during a procedure Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports - * @param[in] antenna_selection Antenna Identifier to be used for RTT packets - * - Range: 1 to 4 - * @param[in] subevent_len ABR subevent length in units of microseconds. - * @param[in] subevent_interval Interval between the start of two consecutive - * ABR events. Units: 0.625 ms. - * - Value: 0x0000. Single ABR subevent - * @param[in] tx_power Transmit power level for the transmission. Units: dBm. - * - Range: -127 to +20 - * - Value: 0x7E. Set transmitter to minimum transmit power level - * - Value: 0x7F. Set transmitter to maximum transmit power level - * @param[in] t_ip1_time Idle time in microseconds between the RTT packets - * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 - * @param[in] t_ip2_time Interlude time in microseconds between the ABR tones - * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 - * @param[in] t_fcs_time Time in microseconds for frequency changes - * - Values: 15, 20, 30, 40, 50, 60, 80, 100, 120 or 150 - * @param[in] t_pm_time Time in microseconds for the phase measurement period of - * the ABR tones - * - Values: 10, 20 or 40 - * @param[in] t_sw_time Time in microseconds for the antenna switch period of - * the ABR tones - * - Values: 0, 1, 2, 4 or 10 - * @param[in] tone_antenna_config Antenna Configuration Index used during - * antenna switching - * - Range: 0 to 7 - * @param[in] companion_signal_state Enum @ref - * sl_bt_cs_companion_signal_status_t. Enable or disable status of the - * companion signal. Values: - * - sl_bt_cs_companion_signal_status_disable (0x0): The companion - * signal is disabled - * - sl_bt_cs_companion_signal_status_enable (0x1): The companion - * signal is enabled - * @param[in] drbg_nonce Antenna Configuration Index used during antenna - * switching - * - Range: 0 to 7 - * @param[in] override_config Configuration of the parameters in - * override_parameters - * - Bit 0: The channel sequence for the subevent is determined by the - * values of channel map repetition, channel length, and channel - * parameters. - * - Bit 2: The number of main mode ABR steps to be executed before a sub - * mode ABR step during the ABR procedure is determined by the value of - * main mode steps parameter. - * - Bit 3: The transmission of tone extensions within each Mode 2 or Mode 3 - * step is determined by the value of T_PM_Tone_Ext parameter. - * - Bit 4: The Tone antenna permutation index for each Mode 2 or Mode 3 - * step is determined by the value of Tone_Antenna_Permutation parameter. - * - Bit 5: The ABR Access Address of all packets sent by the initiator is - * determined by ABR_SYNC_AA_Initiator parameter. The ABR Access Address - * of all packets sent by the reflector is determined by - * ABR_SYNC_AA_Reflector parameter. - * B - * - Bit 6: The Marker positions for each ABR SYNC packet with a marker is - * determined by the value of SS_Marker1_Position and SS_Marker2_Position - * parameters. - * - Bit 7: The Marker value for each marker within a ABR SYNC packet is - * determined by SS_Marker_Value parameter. - * - Bit 8: The payload of the ABR SYNC packet is determined by the value of - * ABR_SYNC_Payload_Pattern parameter. - * - Bit 10: Stable Phase test - * @param[in] override_parameters_len Length of data in @p override_parameters - * @param[in] override_parameters Variable set of parameters which are present - * dependent on the bits set in the override config parameter. - * - Bit 0: channel_map_repetition, channel_length and channel - * - Bit 2: main_mode_steps - * - Bit 3: t_pm_tone_ext - * - Bit 4: tone_antenna_permutation - * - Bit 5: aa_initiator and aa_reflector - * - Bit 6: ss_marker1_position and ss_marker2_position - * - Bit 7: ss_marker_value - * - Bit 8: ABR_SYNC_Payload_Pattern and ABR_SYNC_User_Payload - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to - * report for every ABR subevent within the ABR procedure - * - ******************************************************************************/ -sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, - uint8_t sub_mode_type, - uint8_t main_mode_repetition, - uint8_t mode_calibration_steps, - uint8_t role, - uint8_t rtt_type, - uint8_t cs_sync_phy, - uint8_t antenna_selection, - const sl_bt_cs_subevent_length_t *subevent_len, - uint16_t subevent_interval, - int8_t tx_power, - uint8_t t_ip1_time, - uint8_t t_ip2_time, - uint8_t t_fcs_time, - uint8_t t_pm_time, - uint8_t t_sw_time, - uint8_t tone_antenna_config, - uint8_t companion_signal_state, - uint16_t drbg_nonce, - uint16_t override_config, - size_t override_parameters_len, - const uint8_t* override_parameters); - -/** @} */ // end addtogroup sl_bt_cs_test - -/** - * @addtogroup sl_bt_l2cap L2CAP Connection Oriented Channels - * @{ - * - * @brief L2CAP Connection Oriented Channels - * - * The commands and events in this class provide Logical Link Control and - * Adaptation Protocol (L2CAP) credit-based logical channels. - * - * An L2CAP credit-based logical channel is a logical link identified by a - * channel identifier (the @p cid parameter in the commands and events of this - * API class). These channels use a credit-based flow control mechanism. The - * credit can be configured at the channel opening and later dynamically updated - * on the channel. - * - * The Simplified Protocol/Service Multiplexer (SPSM) of a channel specifies the - * protocol or services the channel implements. It can be a value for a fixed - * service assigned by the Bluetooth SIG or a dynamically-allocated value and - * used with services defined in the GATT Server. The dynamically-assigned value - * may be used to support multiple implementations of a particular protocol. See - * the Bluetooth core specification for more details. The application specifies - * the SPSM value in a channel open request in the @p spsm parameter of the @ref - * sl_bt_l2cap_open_le_channel command. - * - * Each of the local and peer channel endpoints must specify the maximum Service - * Data Unit (SDU) size (the 'MTU' field of the L2CAP packets in the Bluetooth - * Core specification) that it can receive on the channel. The application - * specifies the maximum Service Data Unit size (the @p max_sdu parameter in - * commands and events) of the local channel endpoint. - * - * Each channel endpoint has a maximum PDU payload Size that the L2CAP layer can - * receive in a single data packet on the channel. The maximum PDU payload size - * supported by the stack for local channel endpoints is 252 bytes, which is the - * maximum data length the @ref sl_bt_evt_l2cap_channel_data event can support. - * The application specifies the max PDU payload size (the @p max_pdu parameter - * in commands and events). Additionally, the application is responsible for - * handling the segmentation from SDU to PDU and reassembly from PDU to SDU. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_l2cap_open_le_channel_id 0x01430020 -#define sl_bt_cmd_l2cap_send_le_channel_open_response_id 0x02430020 -#define sl_bt_cmd_l2cap_channel_send_data_id 0x03430020 -#define sl_bt_cmd_l2cap_channel_send_credit_id 0x04430020 -#define sl_bt_cmd_l2cap_close_channel_id 0x05430020 -#define sl_bt_rsp_l2cap_open_le_channel_id 0x01430020 -#define sl_bt_rsp_l2cap_send_le_channel_open_response_id 0x02430020 -#define sl_bt_rsp_l2cap_channel_send_data_id 0x03430020 -#define sl_bt_rsp_l2cap_channel_send_credit_id 0x04430020 -#define sl_bt_rsp_l2cap_close_channel_id 0x05430020 - -/** - * @brief Defines possible result values in the responses to credit based - * channel connection requests. - */ -typedef enum -{ - sl_bt_l2cap_connection_result_successful = 0x0, /**< (0x0) - Connection - successful */ - sl_bt_l2cap_connection_result_spsm_not_supported = 0x2, /**< (0x2) - Connection - refused - \- - SPSM - not - supported */ - sl_bt_l2cap_connection_result_no_resources_available = 0x4, /**< (0x4) - Connection - refused - \- no - resources - available */ - sl_bt_l2cap_connection_result_insufficient_authentication = 0x5, /**< (0x5) - Connection - refused - \- - insufficient - authentication */ - sl_bt_l2cap_connection_result_insufficient_authorization = 0x6, /**< (0x6) - Connection - refused - \- - insufficient - authorization */ - sl_bt_l2cap_connection_result_encryption_key_size_too_short = 0x7, /**< (0x7) - Connection - refused - \- - encryption - key - size - too - short */ - sl_bt_l2cap_connection_result_insufficient_encryption = 0x8, /**< (0x8) - Connection - refused - \- - insufficient - encryption */ - sl_bt_l2cap_connection_result_invalid_source_cid = 0x9, /**< (0x9) - Connection - refused - \- - invalid - Source - CID */ - sl_bt_l2cap_connection_result_source_cid_already_allocated = 0xa, /**< (0xa) - Connection - refused - \- - Source - CID - already - allocated */ - sl_bt_l2cap_connection_result_unacceptable_parameters = 0xb /**< (0xb) - Connection - refused - \- - unacceptable - parameters */ -} sl_bt_l2cap_connection_result_t; - -/** - * @brief Describes why a request command was rejected. - */ -typedef enum -{ - sl_bt_l2cap_command_not_understood = 0x0, /**< (0x0) Command not understood - e.g., unknown command code */ - sl_bt_l2cap_signaling_mtu_exceeded = 0x1, /**< (0x1) Command size has exceeded - the signaling MTU size */ - sl_bt_l2cap_invalid_cid_request = 0x2 /**< (0x2) An invalid CID is - included in the command */ -} sl_bt_l2cap_command_reject_reason_t; - -/** - * @brief Describes which of the request commands has been rejected. - */ -typedef enum -{ - sl_bt_l2cap_disconnection_request = 0x6, /**< (0x6) A disconnection request */ - sl_bt_l2cap_le_connection_request = 0x14, /**< (0x14) An LE credit-based - connection request */ - sl_bt_l2cap_flow_control_credit = 0x16 /**< (0x16) A Flow Control Credit - packet */ -} sl_bt_l2cap_command_code_t; - -/** - * @addtogroup sl_bt_evt_l2cap_le_channel_open_request sl_bt_evt_l2cap_le_channel_open_request - * @{ - * @brief Indicates that an LE credit-based connection request on a Bluetooth - * connection is received - * - * The application must respond with the @ref - * sl_bt_l2cap_send_le_channel_open_response command. - */ - -/** @brief Identifier of the le_channel_open_request event */ -#define sl_bt_evt_l2cap_le_channel_open_request_id 0x014300a0 - -/***************************************************************************//** - * @brief Data structure of the le_channel_open_request event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_request_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t spsm; /**< The protocol/services implemented by the peer - channel endpoint */ - uint16_t cid; /**< The channel identifier on the local device */ - uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer - channel endpoint */ - uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel - endpoint */ - uint16_t credit; /**< The initial credit value of the peer channel - endpoint, i.e., number of PDUs that the local - channel endpoint can send */ - uint16_t remote_cid; /**< The channel identifier on the peer device */ -}); - -typedef struct sl_bt_evt_l2cap_le_channel_open_request_s sl_bt_evt_l2cap_le_channel_open_request_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_request - -/** - * @addtogroup sl_bt_evt_l2cap_le_channel_open_response sl_bt_evt_l2cap_le_channel_open_response - * @{ - * @brief Indicates that an LE credit-based connection response is received - * - * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode - * implies that the logical channel is established and data can be sent or - * received on the channel. - * - * If the connection request was rejected by the peer, indicated by @p - * errorcode, the stack automatically closes the local channel and the user - * application should clean up the resources associated to the channel - * identifier. - */ - -/** @brief Identifier of the le_channel_open_response event */ -#define sl_bt_evt_l2cap_le_channel_open_response_id 0x024300a0 - -/***************************************************************************//** - * @brief Data structure of the le_channel_open_response event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_response_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the - response is received */ - uint16_t cid; /**< The channel identifier on the local device */ - uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer - channel endpoint */ - uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel - endpoint */ - uint16_t credit; /**< The initial credit value of the peer channel - endpoint, i.e., number of PDUs the local channel - endpoint can send */ - uint16_t errorcode; /**< Enum @ref sl_bt_l2cap_connection_result_t. - - An L2CAP error code as the outcome of the connection - request. - - Result @ref sl_bt_l2cap_connection_result_successful - indicates the connection request was accepted and - the logical channel is established. Other error code - value indicates the connection request was refused - by the peer device and other parameters of this - event must be ignored. */ - uint16_t remote_cid; /**< The channel identifier on the peer device */ -}); - -typedef struct sl_bt_evt_l2cap_le_channel_open_response_s sl_bt_evt_l2cap_le_channel_open_response_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_response - -/** - * @addtogroup sl_bt_evt_l2cap_channel_data sl_bt_evt_l2cap_channel_data - * @{ - * @brief Indicates that data is received on a channel - * - * Each event should contain a K-frame of payload. The length of SDU should be - * specified in the first 2 bytes of the first K-frame. The sum of the payload - * lengths in received K-frames should be equal to the specified SDU length. - * Otherwise, application should disconnect the channel using @ref - * sl_bt_l2cap_close_channel command. The same should happen also if the SDU - * length exceeds the max_sdu of local channel endpoint. - */ - -/** @brief Identifier of the channel_data event */ -#define sl_bt_evt_l2cap_channel_data_id 0x034300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_data event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_data_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t cid; /**< The channel identifier */ - uint8array data; /**< Data received */ -}); - -typedef struct sl_bt_evt_l2cap_channel_data_s sl_bt_evt_l2cap_channel_data_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_data - -/** - * @addtogroup sl_bt_evt_l2cap_channel_credit sl_bt_evt_l2cap_channel_credit - * @{ - * @brief Indicates that flow control credits are received on a channel - * informing that the peer channel endpoint is capable of receiving more data - */ - -/** @brief Identifier of the channel_credit event */ -#define sl_bt_evt_l2cap_channel_credit_id 0x044300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_credit event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_credit_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the credit - is received */ - uint16_t cid; /**< The channel identifier */ - uint16_t credit; /**< The credit value, i.e., the additional number of - PDUs the peer channel endpoint can receive */ -}); - -typedef struct sl_bt_evt_l2cap_channel_credit_s sl_bt_evt_l2cap_channel_credit_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_credit - -/** - * @addtogroup sl_bt_evt_l2cap_channel_closed sl_bt_evt_l2cap_channel_closed - * @{ - * @brief Indicates that a credit-based logical channel is closed by the local - * or peer device. - */ - -/** @brief Identifier of the channel_closed event */ -#define sl_bt_evt_l2cap_channel_closed_id 0x054300a0 - -/***************************************************************************//** - * @brief Data structure of the channel_closed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_channel_closed_s -{ - uint8_t connection; /**< The connection handle */ - uint16_t cid; /**< The channel identifier */ - uint16_t reason; /**< The disconnection reason */ -}); - -typedef struct sl_bt_evt_l2cap_channel_closed_s sl_bt_evt_l2cap_channel_closed_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_closed - -/** - * @addtogroup sl_bt_evt_l2cap_command_rejected sl_bt_evt_l2cap_command_rejected - * @{ - * @brief Indicates that the peer device rejected a command - * - * This might happen if, for example, the device does not support the feature or - * the command has an incorrect CID. - */ - -/** @brief Identifier of the command_rejected event */ -#define sl_bt_evt_l2cap_command_rejected_id 0x064300a0 - -/***************************************************************************//** - * @brief Data structure of the command_rejected event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_l2cap_command_rejected_s -{ - uint8_t connection; /**< The Bluetooth connection handle on which the event - is received */ - uint8_t code; /**< Enum @ref sl_bt_l2cap_command_code_t. Code of the - rejected command */ - uint16_t reason; /**< Enum @ref sl_bt_l2cap_command_reject_reason_t. The - rejection reason */ - uint16_t cid; /**< The channel identifier */ -}); - -typedef struct sl_bt_evt_l2cap_command_rejected_s sl_bt_evt_l2cap_command_rejected_t; - -/** @} */ // end addtogroup sl_bt_evt_l2cap_command_rejected - -/***************************************************************************//** - * - * Create and configure an L2CAP channel on a Bluetooth connection using the LE - * credit based connection request packet. Event @ref - * sl_bt_evt_l2cap_le_channel_open_response or @ref - * sl_bt_evt_l2cap_command_rejected will be received after the peer device - * responded to the request. - * - * @param[in] connection The connection handle - * @param[in] spsm The protocol/services implemented by the local channel - * endpoint - * @param[in] max_sdu @parblock - * The Maximum Service Data Unit size the local channel endpoint can accept - * - * Range: 23 to 65533. - * @endparblock - * @param[in] max_pdu @parblock - * The maximum PDU payload size the local channel endpoint can accept - * - * Range: 23 to 252. - * @endparblock - * @param[in] credit The initial credit value of the local channel endpoint, - * i.e., number of PDUs the peer channel endpoint can send - * @param[out] cid The channel identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_l2cap_command_rejected - Triggered when the peer device - * rejected the connection request. Typically a legacy peer device that does - * not support the feature could send this response. When this event is - * received under the context of opening a channel using this command, the - * stack automatically closes the local channel and the user application - * should clean up the resources associated to the channel identifier. - * - @ref sl_bt_evt_l2cap_le_channel_open_response - Triggered when an LE - * credit-based connection response has been received in response to this - * command. If the result code in @p errorcode of the event is not equal to - * @ref sl_bt_l2cap_connection_result_successful, it means that connection - * request was rejected by the peer device. In this case, the stack - * automatically closes the local channel and the user application should - * clean up the resources associated to the channel identifier. - * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an LE credit-based - * connection response has not been received within 30 seconds after this - * command has been issued. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, - uint16_t spsm, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t *cid); - -/***************************************************************************//** - * - * Send an LE credit-based connection response to an LE credit-based connection - * request received in the @ref sl_bt_evt_l2cap_le_channel_open_request event. - * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode - * implies that the logical channel is established and data can be sent or - * received on the channel. - * - * To reject the connection request, use a result code other than - * sl_bt_l2cap_connection_result_successful in @p errorcode. Other parameters in - * this command are ignored in this case. The stack automatically closes the - * local channel and the user application should clean up the resources - * associated to the channel identifier. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] max_sdu @parblock - * The Maximum Service Data Unit size the local channel endpoint can accept - * - * Range: 23 to 65533. - * @endparblock - * @param[in] max_pdu @parblock - * The maximum PDU payload size the local channel endpoint can accept - * - * Range:23 to 252. - * @endparblock - * @param[in] credit The initial credit value of the local channel endpoint, - * i.e., number of PDUs that the peer channel endpoint can send - * @param[in] errorcode Enum @ref sl_bt_l2cap_connection_result_t. An L2CAP - * error code as the outcome of the connection request - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, - uint16_t cid, - uint16_t max_sdu, - uint16_t max_pdu, - uint16_t credit, - uint16_t errorcode); - -/***************************************************************************//** - * - * Send data to the peer channel endpoint on a Bluetooth connection. If the SDU - * length is larger than max_pdu size or 250 bytes, the application should - * fragment the SDU into multiple K-frames and call this command once for each - * K-frame. - * - * The first K-frame of the SDU should start with 2 bytes of SDU length followed - * with payload. Therefore, the first K-frame contains PDU length minus 2 bytes - * of the actual payload. All subsequent K-frames of the same SDU contain PDU - * length of the payload. The sum of the payload lengths for K-frames should be - * equal to the specified SDU length. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] data_len Length of data in @p data - * @param[in] data Data to be sent. The data length must not be greater than the - * lesser of the peer channel endpoint max_pdu and 252 bytes, which is the - * maximum data length this command can send. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, - uint16_t cid, - size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Send flow control credits to the peer channel endpoint indicating that the - * local channel endpoint is capable of receiving more data. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * @param[in] credit @parblock - * The credit value, i.e., the additional number of PDUs the peer channel - * endpoint can send - * - * Range: 1 to 65535. - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, - uint16_t cid, - uint16_t credit); - -/***************************************************************************//** - * - * Send a disconnect request to close a credit-based logical channel. - * - * @param[in] connection The connection handle - * @param[in] cid The channel identifier - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an credit-based - * logical channel is closed in response to this command. - * - ******************************************************************************/ -sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid); - -/** @} */ // end addtogroup sl_bt_l2cap - -/** - * @addtogroup sl_bt_cte_transmitter CTE Transmitter - * @{ - * - * @brief CTE Transmitter - * - * Commands and events in this class manage Constant Tone Extension (CTE) - * transmission. - * - * CTE feature is only supported by specific devices. Commands from this class - * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cte_transmitter_set_dtm_parameters_id 0x04440020 -#define sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id 0x05440020 -#define sl_bt_cmd_cte_transmitter_enable_connection_cte_id 0x00440020 -#define sl_bt_cmd_cte_transmitter_disable_connection_cte_id 0x01440020 -#define sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id 0x02440020 -#define sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id 0x03440020 -#define sl_bt_cmd_cte_transmitter_enable_silabs_cte_id 0x06440020 -#define sl_bt_cmd_cte_transmitter_disable_silabs_cte_id 0x07440020 -#define sl_bt_rsp_cte_transmitter_set_dtm_parameters_id 0x04440020 -#define sl_bt_rsp_cte_transmitter_clear_dtm_parameters_id 0x05440020 -#define sl_bt_rsp_cte_transmitter_enable_connection_cte_id 0x00440020 -#define sl_bt_rsp_cte_transmitter_disable_connection_cte_id 0x01440020 -#define sl_bt_rsp_cte_transmitter_enable_connectionless_cte_id 0x02440020 -#define sl_bt_rsp_cte_transmitter_disable_connectionless_cte_id 0x03440020 -#define sl_bt_rsp_cte_transmitter_enable_silabs_cte_id 0x06440020 -#define sl_bt_rsp_cte_transmitter_disable_silabs_cte_id 0x07440020 - -/***************************************************************************//** - * - * Set the CTE-related parameters of the LE transmitter test. - * - * @param[in] cte_length @parblock - * The length of the Constant Tone Extension in 8 us units - * - 0: No CTE - * - 0x02 to 0x14: CTE length - * - * Default: 0 (no CTE) - * @endparblock - * @param[in] cte_type @parblock - * CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * - * Default: 0 - * @endparblock - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. This can be - * an empty array if CTE is unused. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Clear CTE-related parameters that were previously set for LE transmitter - * test. Default values will be restored for these parameters. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters(); - -/***************************************************************************//** - * - * Enable different types of CTE responses on a connection. CTE response will be - * sent once requested by the peer device using the CTE Request procedure. - * - * @param[in] connection Connection handle - * @param[in] cte_types CTE types. Bitmask of the following: - * - Bit 0: AoA CTE response - * - Bit 1: AoD CTE response with 1 us slots - * - Bit 2: AoD CTE response with 2 us slots - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, - uint8_t cte_types, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable CTE responses on a connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection); - -/***************************************************************************//** - * - * Start a connectionless CTE transmit. CTEs will be transmitted in periodic - * advertisement packets. As a result, a periodic advertising has to be started - * prior to this command. - * - * @param[in] handle Periodic advertising handle - * @param[in] cte_length CTE length in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] cte_count The number of CTEs to be transmitted in each periodic - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop the connectionless CTE transmit. - * - * @param[in] handle Periodic advertising handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle); - -/***************************************************************************//** - * - * Enable Silicon Labs CTE transmit. CTEs will be transmitted in extended - * advertisement packets. As a result, extended advertising has to be started - * prior this command. - * - * @param[in] handle Advertising handle - * @param[in] cte_length CTE length in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] cte_count The number of CTEs to be transmitted in each extended - * advertising interval. Currently, only cte_count = 1 is supported. - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, - uint8_t cte_length, - uint8_t cte_type, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable Silicon Labs CTE transmit. - * - * @param[in] handle Advertising handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle); - -/** @} */ // end addtogroup sl_bt_cte_transmitter - -/** - * @addtogroup sl_bt_cte_receiver CTE Receiver - * @{ - * - * @brief CTE Receiver - * - * Commands and events in this class manage Constant Tone Extension (CTE) - * receiving. - * - * CTE feature is only supported by specific devices. Commands from this class - * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_cte_receiver_set_dtm_parameters_id 0x05450020 -#define sl_bt_cmd_cte_receiver_clear_dtm_parameters_id 0x06450020 -#define sl_bt_cmd_cte_receiver_set_sync_cte_type_id 0x09450020 -#define sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 -#define sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id 0x0b450020 -#define sl_bt_cmd_cte_receiver_configure_id 0x00450020 -#define sl_bt_cmd_cte_receiver_enable_connection_cte_id 0x01450020 -#define sl_bt_cmd_cte_receiver_disable_connection_cte_id 0x02450020 -#define sl_bt_cmd_cte_receiver_enable_connectionless_cte_id 0x03450020 -#define sl_bt_cmd_cte_receiver_disable_connectionless_cte_id 0x04450020 -#define sl_bt_cmd_cte_receiver_enable_silabs_cte_id 0x07450020 -#define sl_bt_cmd_cte_receiver_disable_silabs_cte_id 0x08450020 -#define sl_bt_rsp_cte_receiver_set_dtm_parameters_id 0x05450020 -#define sl_bt_rsp_cte_receiver_clear_dtm_parameters_id 0x06450020 -#define sl_bt_rsp_cte_receiver_set_sync_cte_type_id 0x09450020 -#define sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 -#define sl_bt_rsp_cte_receiver_set_sync_receive_parameters_id 0x0b450020 -#define sl_bt_rsp_cte_receiver_configure_id 0x00450020 -#define sl_bt_rsp_cte_receiver_enable_connection_cte_id 0x01450020 -#define sl_bt_rsp_cte_receiver_disable_connection_cte_id 0x02450020 -#define sl_bt_rsp_cte_receiver_enable_connectionless_cte_id 0x03450020 -#define sl_bt_rsp_cte_receiver_disable_connectionless_cte_id 0x04450020 -#define sl_bt_rsp_cte_receiver_enable_silabs_cte_id 0x07450020 -#define sl_bt_rsp_cte_receiver_disable_silabs_cte_id 0x08450020 - -/** - * @addtogroup sl_bt_cte_receiver_sync_cte_type CTE type flags for limiting periodic advertising synchronization - * @{ - * - * Defines sync CTE type flags that are used to limit what types of periodic - * advertisers to sync to when scanning for periodic advertising synchronization - * or receiving periodic advertising synchronization transfers. - */ - -/** Do not sync to packets with an AoA Constant Tone Extension */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA 0x1 - -/** Do not sync to packets with an AoD Constant Tone Extension with 1 us slots - * */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US 0x2 - -/** Do not sync to packets with an AoD Constant Tone Extension with 2 us slots - * */ -#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US 0x4 - -/** Do not sync to packets without a Constant Tone Extension */ -#define SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY 0x10 - -/** @} */ // end CTE type flags for limiting periodic advertising synchronization - -/** - * @addtogroup sl_bt_evt_cte_receiver_dtm_iq_report sl_bt_evt_cte_receiver_dtm_iq_report - * @{ - * @brief IQ sample report from DTM CTE packets. - */ - -/** @brief Identifier of the dtm_iq_report event */ -#define sl_bt_evt_cte_receiver_dtm_iq_report_id 0x024500a0 - -/***************************************************************************//** - * @brief Data structure of the dtm_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_dtm_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the periodic advertising - train or the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_dtm_iq_report_s sl_bt_evt_cte_receiver_dtm_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_dtm_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_connection_iq_report sl_bt_evt_cte_receiver_connection_iq_report - * @{ - * @brief IQ sample report from connection CTE packets. - */ - -/** @brief Identifier of the connection_iq_report event */ -#define sl_bt_evt_cte_receiver_connection_iq_report_id 0x004500a0 - -/***************************************************************************//** - * @brief Data structure of the connection_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_connection_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint8_t connection; /**< Connection handle or periodic advertising - synchronization handle */ - uint8_t phy; /**< The PHY on which the packet is received. - - 1: 1M PHY - - 2: 2M PHY */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_connection_iq_report_s sl_bt_evt_cte_receiver_connection_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connection_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report sl_bt_evt_cte_receiver_connectionless_iq_report - * @{ - * @brief IQ sample report from connectionless CTE packets. - */ - -/** @brief Identifier of the connectionless_iq_report event */ -#define sl_bt_evt_cte_receiver_connectionless_iq_report_id 0x014500a0 - -/***************************************************************************//** - * @brief Data structure of the connectionless_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_connectionless_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - uint16_t sync; /**< Periodic advertising synchronization handle */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t event_counter; /**< The event counter of the periodic advertising - train */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_connectionless_iq_report_s sl_bt_evt_cte_receiver_connectionless_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report - -/** - * @addtogroup sl_bt_evt_cte_receiver_silabs_iq_report sl_bt_evt_cte_receiver_silabs_iq_report - * @{ - * @brief IQ samples report from Silicon Labs CTE packets. - */ - -/** @brief Identifier of the silabs_iq_report event */ -#define sl_bt_evt_cte_receiver_silabs_iq_report_id 0x034500a0 - -/***************************************************************************//** - * @brief Data structure of the silabs_iq_report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_cte_receiver_silabs_iq_report_s -{ - uint16_t status; /**< Status of CTE IQ sampling */ - bd_addr address; /**< Bluetooth address of the remote device */ - uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. - - Advertiser address type. - - If the application does not include the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses the following - values: - - 0: Public address - - 1: Random address - - 255: No address provided - (anonymous advertising) - - If the application includes the - bluetooth_feature_use_accurate_api_address_types - component, @p address_type uses enum @ref - sl_bt_gap_address_type_t values: - - sl_bt_gap_public_address (0x0): - Public device address - - sl_bt_gap_static_address (0x1): - Static device address - - sl_bt_gap_random_resolvable_address - (0x2): Resolvable private random - address - - sl_bt_gap_random_nonresolvable_address - (0x3): Non-resolvable private random - address - - sl_bt_gap_anonymous_address - (0xff): No address provided - (anonymous advertising) - - sl_bt_gap_public_address_resolved_from_rpa - (0x4): Public identity address - resolved from a resolvable private - address (RPA) - - sl_bt_gap_static_address_resolved_from_rpa - (0x5): Static identity address - resolved from a resolvable private - address (RPA) */ - uint8_t phy; /**< The PHY on which the packet is received. - - 1: 1M PHY - - 2: 2M PHY */ - uint8_t channel; /**< The channel on which the CTE packet was - received */ - int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ - uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was - measured */ - uint8_t cte_type; /**< The CTE type - - 0: AoA CTE response - - 1: AoD CTE response with 1us slots - - 2: AoD CTE response with 2us slots */ - uint8_t slot_durations; /**< Slot durations - - 1: Switching and sampling slots - are 1 us each - - 2: Switching and sampling slots - are 2 us each */ - uint16_t packet_counter; /**< The event counter of the periodic advertising - train or the connection */ - uint8array samples; /**< IQ samples of the received CTE packet. I and - Q samples follow each other alternately (I, - Q, I, Q, ...) */ -}); - -typedef struct sl_bt_evt_cte_receiver_silabs_iq_report_s sl_bt_evt_cte_receiver_silabs_iq_report_t; - -/** @} */ // end addtogroup sl_bt_evt_cte_receiver_silabs_iq_report - -/***************************************************************************//** - * - * Set CTE-related parameters of LE receiver test. - * - * @param[in] cte_length @parblock - * Expected CTE length in 8 us units - * - 0: No CTE - * - 0x02 to 0x14: Expected CTE length - * - * Default: 0 (no CTE) - * @endparblock - * @param[in] cte_type @parblock - * Expected CTE type - * - 0: Expect AoA CTE - * - 1: Expect AoD CTE with 1 us slots - * - 2: Expect AoD CTE with 2 us slots - * - * Default: 0 - * @endparblock - * @param[in] slot_durations @parblock - * Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * - * Default: 1 - * @endparblock - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. This can be - * an empty array if CTE is unused. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_dtm_iq_report - Triggered when IQ samples - * have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Clear CTE-related parameters that were previously set for LE receiver test. - * Default values will be restored for these parameters. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_clear_dtm_parameters(); - -/***************************************************************************//** - * - * Set the sync CTE type to limit what types of periodic advertisers to sync to - * when scanning for periodic advertising synchronization. The set parameter - * takes effect immediately for all advertisers that have not already - * established synchronization. - * - * @param[in] sync_cte_type @parblock - * Sync CTE type flags. This value can be a bitmask of multiple flags from - * @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type); - -/***************************************************************************//** - * - * Set the default parameters and the CTE type limitation for receiving Periodic - * Advertising Synchronization Transfers (PAST) over connections. The default - * parameters will be in effect for all subsequent connections and do not affect - * connections that have already opened. The parameters can be overridden for a - * specific connection using command @ref - * sl_bt_cte_receiver_set_sync_receive_parameters after the connection is - * opened. - * - * This command is relevant and available only when the application has included - * the bluetooth_feature_past_receiver component into the build. If the PAST - * receiver component is not included, this command returns the error - * SL_STATUS_NOT_AVAILABLE. - * - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] sync_cte_type @parblock - * Sync CTE type flags to limit what types of periodic advertising trains to - * sync to when receiving sync transfers. This value can be a bitmask of - * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 (do not limit synchronization by CTE type) - * @endparblock - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode); - -/***************************************************************************//** - * - * Set the parameters and the CTE type limitation for receiving Periodic - * Advertising Synchronization Transfers (PAST) over the specified connection. - * The parameters do not affect periodic advertising trains that the device has - * already synchronized to. - * - * This command is relevant and available only when the application has included - * the bluetooth_feature_past_receiver component into the build. If the PAST - * receiver component is not included, this command returns the error - * SL_STATUS_NOT_AVAILABLE. - * - * @param[in] connection Connection handle - * @param[in] mode @parblock - * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth - * stack reacts when synchronization information is received. Values: - * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to - * synchronize to a periodic advertising train for which the - * synchronization information was received. No event will be triggered - * towards the application. - * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to - * synchronize to a periodic advertising train for which the - * synchronization information was received. When the information is - * received, an event will be triggered to indicate success or failure and - * to provide the application with the periodic advertising - * synchronization handle. - * - * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to - * synchronize) - * @endparblock - * @param[in] skip The maximum number of periodic advertising packets that can - * be skipped after a successful receive. - * - Range: 0x0000 to 0x01F3 - * - Default value: 0 - * @param[in] timeout The maximum permitted time between successful receives. If - * this time is exceeded, synchronization is lost. Unit: 10 ms. - * - Range: 0x0A to 0x4000 - * - Unit: 10 ms - * - Time range: 100 ms to 163.84 s - * - Default value: 1000 ms - * @param[in] sync_cte_type @parblock - * Sync CTE type flags to limit what types of periodic advertising trains to - * sync to when receiving sync transfers. This value can be a bitmask of - * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync - * to packets with an AoA Constant Tone Extension - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not - * sync to packets with an AoD Constant Tone Extension with 1 us slots - * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not - * sync to packets with an AoD Constant Tone Extension with 2 us slots - * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync - * to packets without a Constant Tone Extension - * - * Default: 0 (do not limit synchronization by CTE type) - * @endparblock - * @param[in] reporting_mode @parblock - * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for - * reporting data received in the periodic advertising train after it has - * achieved synchronization. Values: - * - sl_bt_sync_report_none (0x0): Data received in periodic - * advertising trains is not reported to the application. - * - sl_bt_sync_report_all (0x1): Data received in periodic - * advertising trains is reported to the application. - * - * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising - * trains is reported to the application) - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. This event is used only when the application - * does not include bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync components. - * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application - * includes the bluetooth_feature_periodic_sync or - * bluetooth_feature_pawr_sync component, triggered after synchronization - * transfer is received for a periodic advertising train that does not have - * subevents or response slots. - * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes - * the bluetooth_feature_pawr_sync component, triggered after - * synchronization transfer is received for a Periodic Advertising with - * Responses (PAwR) train. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, - uint8_t mode, - uint16_t skip, - uint16_t timeout, - uint8_t sync_cte_type, - uint8_t reporting_mode); - -/***************************************************************************//** - * @cond RESTRICTED - * - * Restricted/experimental API. Contact Silicon Labs sales for more information. - * - * Configure the CTE sampling mode. - * - * @param[in] flags @parblock - * Values: - * - 0: Disable raw sample mode, only picked IQ samples are reported - * (1 IQ sample pair / slot) - * - 1: Enable raw sample mode, every IQ sample is reported. - * - * Default: 0 - * @endparblock - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @endcond - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_configure(uint8_t flags); - -/***************************************************************************//** - * - * Start IQ samplings on a connection. A CTE requests will be initiated - * periodically on the given connection and IQ sampling will be made on the - * received CTE responses. - * - * @param[in] connection Connection handle - * @param[in] interval Measurement interval. CTE requests may be sent less - * often. For example, if a connection event is missed for any reason, the CTE - * request will be sent in the next connection event. - * - 0: No interval. The request is initiated only once. - * - Other values N: Initiate the request every N-th connection - * events - * @param[in] cte_length Minimum CTE length requested in 8 us units. - * - Range: 0x02 to 0x14 - * - Time Range: 16 us to 160 us - * @param[in] cte_type Requested CTE type - * - 0: AoA CTE - * - 1: AoD CTE with 1 us slots - * - 2: AoD CTE with 2 us slots - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_connection_iq_report - Triggered when IQ - * samples have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, - uint16_t interval, - uint8_t cte_length, - uint8_t cte_type, - uint8_t slot_durations, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop the IQ sampling on a connection. CTEs will not be requested on the given - * connection. - * - * @param[in] connection Connection handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection); - -/***************************************************************************//** - * - * Start IQ sampling on a periodic advertising synchronization. IQ samples are - * taken on each CTE found in the periodic advertisements. - * - * @param[in] sync Periodic advertising synchronization handle - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] cte_count - 0: Sample and report all available CTEs - * - Other values: Maximum number of sampled CTEs in each periodic - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_connectionless_iq_report - Triggered when IQ - * samples have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, - uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Stop IQ sampling on a periodic advertising synchronization. - * - * @param[in] sync Periodic advertising synchronization handle - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync); - -/***************************************************************************//** - * - * Enable IQ sampling of Silicon Labs CTE found in extended advertisements. - * - * @param[in] slot_durations Slot durations - * - 1: Switching and sampling slots are 1 us each - * - 2: Switching and sampling slots are 2 us each - * @param[in] cte_count - 0: Sample and report all available CTEs - * - Other values: Maximum number of sampled CTEs in each extended - * advertising interval - * @param[in] switching_pattern_len Length of data in @p switching_pattern - * @param[in] switching_pattern Antenna switching pattern. Antennas will be - * switched in this order with the antenna switch pins during CTE. If the CTE - * is longer than the switching pattern, the pattern starts over. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_cte_receiver_silabs_iq_report - Triggered when IQ samples - * of Silicon Labs CTE have been received. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, - uint8_t cte_count, - size_t switching_pattern_len, - const uint8_t* switching_pattern); - -/***************************************************************************//** - * - * Disable IQ sampling of Silicon Labs CTE. - * - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_cte_receiver_disable_silabs_cte(); - -/** @} */ // end addtogroup sl_bt_cte_receiver - -/** - * @addtogroup sl_bt_connection_analyzer Connection Analyzer - * @{ - * - * @brief Connection Analyzer - * - * Analyze Bluetooth packets that are transmitted on the connections of external - * devices. Include component bluetooth_feature_connection_analyzer to use the - * commands and events in this class. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_connection_analyzer_start_id 0x00480020 -#define sl_bt_cmd_connection_analyzer_stop_id 0x01480020 -#define sl_bt_rsp_connection_analyzer_start_id 0x00480020 -#define sl_bt_rsp_connection_analyzer_stop_id 0x01480020 - -/** - * @addtogroup sl_bt_connection_analyzer_flags Connection Analyzer Configuration flags - * @{ - * - * Defines the configuration flags in connection analyzer. - */ - -/** Indicates a given time value, e.g., @p start_time_us in @ref - * sl_bt_connection_analyzer_start, is a value relative to the current time. */ -#define SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME 0x1 - -/** @} */ // end Connection Analyzer Configuration flags - -/** - * @addtogroup sl_bt_evt_connection_analyzer_report sl_bt_evt_connection_analyzer_report - * @{ - * @brief Triggered when packets transmitted on a connection are captured. - */ - -/** @brief Identifier of the report event */ -#define sl_bt_evt_connection_analyzer_report_id 0x004800a0 - -/***************************************************************************//** - * @brief Data structure of the report event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_analyzer_report_s -{ - uint8_t analyzer; /**< The handle of the connection analyzer */ - int8_t central_rssi; /**< RSSI measurement of the packet transmitted by - the Central device. Units: dBm. Range: -127 to - +20. */ - int8_t peripheral_rssi; /**< RSSI measurement of the packet transmitted by - the Peripheral device. Units: dBm. Range: -127 - to +20. */ -}); - -typedef struct sl_bt_evt_connection_analyzer_report_s sl_bt_evt_connection_analyzer_report_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_report - -/** - * @addtogroup sl_bt_evt_connection_analyzer_completed sl_bt_evt_connection_analyzer_completed - * @{ - * @brief Triggered when the operation of analyzing a connection is completed. - */ - -/** @brief Identifier of the completed event */ -#define sl_bt_evt_connection_analyzer_completed_id 0x014800a0 - -/***************************************************************************//** - * @brief Data structure of the completed event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_connection_analyzer_completed_s -{ - uint8_t analyzer; /**< The handle of the connection analyzer */ - uint16_t reason; /**< The reason of stopping the operation */ -}); - -typedef struct sl_bt_evt_connection_analyzer_completed_s sl_bt_evt_connection_analyzer_completed_t; - -/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_completed - -/***************************************************************************//** - * - * Start to analyze another device's connection and report the RSSI - * measurements. The parameters in this command provide necessary information to - * identify the connection and schedule operations to follow its transmissions. - * - * If the other device uses Silabs' Bluetooth stack, the information of the - * connection could be retrieved with command @ref - * sl_bt_connection_get_scheduling_details. The method of passing the - * information to this device is application layer logic. - * - * @param[in] access_address Access address of the connection - * @param[in] crc_init The CRC initialization value - * @param[in] interval The connection interval. Time = Value x 1.25 ms - * @param[in] supervision_timeout The connection supervision time. Time = Value - * x 10 ms - * @param[in] central_clock_accuracy The central device's clock accuracy index - * value - * @param[in] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central - * device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[in] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the - * Peripheral device is transmitting on. Values: - * - sl_bt_gap_phy_1m (0x1): 1M PHY - * - sl_bt_gap_phy_2m (0x2): 2M PHY - * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) - * @param[in] channel_selection_algorithm Enum @ref - * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. - * Values: - * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection - * algorithm #1 - * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection - * algorithm #2 - * @param[in] hop The hop increment when the channel selection algorithm #1 is - * used on the connection. Ignored if @p channel_selection_algorithm indicates - * that the connection uses channel selection algorithm #2. - * @param[in] channel_map @parblock - * 5 byte bit field in little endian format. Only the first 37 bits are used. - * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel - * 8, etc. Ignore bits 37-39 that are reserved for future use. - * - * A channel is unused when its bit is 0. A channel is used when its bit is 1. - * @endparblock - * @param[in] channel The data channel number that transmissions will use in the - * next connection event - * @param[in] event_counter The event counter of the next connection event - * @param[in] start_time_us The start time of the given connection event in - * microseconds. The semantics depend on whether the configuration flag - * SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME is set in parameter @p flags: - * - When the flag is set, the value is a time relative to the current time. - * A negative value means that the start time was in the past. - * - When the flag is not set, the value is an absolute time converted from - * the PROTIMER tick. - * @param[in] flags Configuration flags. This value is a bitmask of @ref - * sl_bt_connection_analyzer_flags. - * @param[out] analyzer A handle that is assigned to the connection analyzer. - * This handle is valid only if the result code of this command is - * SL_STATUS_OK. - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - * @b Events - * - @ref sl_bt_evt_connection_analyzer_report - Triggered when a packet - * transmitted from the given device is captured. - * - @ref sl_bt_evt_connection_analyzer_completed - Triggered when analyzing a - * connection is completed in the Link Layer for some reason. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, - uint32_t crc_init, - uint16_t interval, - uint16_t supervision_timeout, - uint8_t central_clock_accuracy, - uint8_t central_phy, - uint8_t peripheral_phy, - uint8_t channel_selection_algorithm, - uint8_t hop, - const sl_bt_connection_channel_map_t *channel_map, - uint8_t channel, - uint16_t event_counter, - int32_t start_time_us, - uint32_t flags, - uint8_t *analyzer); - -/***************************************************************************//** - * - * Stop analyzing another device's Bluetooth connection. The operation is - * stopped when this command returns, and the stack does not send additional - * event. - * - * @param[in] analyzer The handle of the connection analyzer to stop - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer); - -/** @} */ // end addtogroup sl_bt_connection_analyzer - -/** - * @addtogroup sl_bt_user User Messaging - * @{ - * - * @brief User Messaging - * - * This class provides commands and events, which can be used by a NCP host and - * target to implement a communication mechanism with a custom proprietary - * protocol. An application must decide whether and how the command and event - * are used. The stack does not produce or consume any messages belonging to - * this class. - */ - -/* Command and Response IDs */ -#define sl_bt_cmd_user_message_to_target_id 0x00ff0020 -#define sl_bt_cmd_user_manage_event_filter_id 0x01ff0020 -#define sl_bt_cmd_user_reset_to_dfu_id 0x02ff0020 -#define sl_bt_rsp_user_message_to_target_id 0x00ff0020 -#define sl_bt_rsp_user_manage_event_filter_id 0x01ff0020 -#define sl_bt_rsp_user_reset_to_dfu_id 0x02ff0020 - -/** - * @addtogroup sl_bt_evt_user_message_to_host sl_bt_evt_user_message_to_host - * @{ - * @brief Used by the target application on a device to initiate communication - * and send a message to the NCP host - * - * Do not send event messages in the context of the user command handling. - */ - -/** @brief Identifier of the message_to_host event */ -#define sl_bt_evt_user_message_to_host_id 0x00ff00a0 - -/***************************************************************************//** - * @brief Data structure of the message_to_host event - ******************************************************************************/ -PACKSTRUCT( struct sl_bt_evt_user_message_to_host_s -{ - uint8array message; /**< The message */ -}); - -typedef struct sl_bt_evt_user_message_to_host_s sl_bt_evt_user_message_to_host_t; - -/** @} */ // end addtogroup sl_bt_evt_user_message_to_host - -/***************************************************************************//** - * - * Used by an NCP host to send a message to the target application on device. - * The application on the target must send the response with @ref - * sl_bt_send_rsp_user_message_to_target. - * - * @param[in] data_len Length of data in @p data - * @param[in] data The message - * @param[in] max_response_size Size of output buffer passed in @p response - * @param[out] response_len On return, set to the length of output data written - * to @p response - * @param[out] response The response message - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_user_message_to_target(size_t data_len, - const uint8_t* data, - size_t max_response_size, - size_t *response_len, - uint8_t *response); - -/***************************************************************************//** - * - * Manage NCP event filter. When the event filter is in use, API events passing - * the filter will be sent to the host and those that do not pass are discarded - * by the target. For functionality details, see the NCP component in the - * Bluetooth SDK. - * - * By default, the NCP does not use the event filter. - * - * @param[in] data_len Length of data in @p data - * @param[in] data The message for managing event filter - * - * @return SL_STATUS_OK if successful. Error code otherwise. - * - ******************************************************************************/ -sl_status_t sl_bt_user_manage_event_filter(size_t data_len, - const uint8_t* data); - -/***************************************************************************//** - * - * Reset the target device to DFU mode from the NCP host. This command is used - * by specific SDK DFU component on the target device for the functionality - * related to DFU. Do not use it in other circumstances. This command does not - * have a response. - * - * - ******************************************************************************/ -void sl_bt_user_reset_to_dfu(); - -/** @} */ // end addtogroup sl_bt_user - - -/***************************************************************************//** - * @addtogroup sl_bt_common_types BT Common Types - * @{ - * @brief BT common types - */ - -/** - * @brief Data structure of BT API messages - */ -PACKSTRUCT( struct sl_bt_msg { - /** API protocol header consisting of event identifier and data length */ - uint32_t header; - - /** Union of API event types */ - union { - uint8_t handle; - sl_bt_evt_dfu_boot_t evt_dfu_boot; /**< Data field for dfu boot event*/ - sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; /**< Data field for dfu boot_failure event*/ - sl_bt_evt_system_boot_t evt_system_boot; /**< Data field for system boot event*/ - sl_bt_evt_system_error_t evt_system_error; /**< Data field for system error event*/ - sl_bt_evt_system_hardware_error_t evt_system_hardware_error; /**< Data field for system hardware_error event*/ - sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; /**< Data field for system resource_exhausted event*/ - sl_bt_evt_system_external_signal_t evt_system_external_signal; /**< Data field for system external_signal event*/ - sl_bt_evt_system_soft_timer_t evt_system_soft_timer; /**< Data field for system soft_timer event*/ - sl_bt_evt_resource_status_t evt_resource_status; /**< Data field for resource status event*/ - sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; /**< Data field for advertiser timeout event*/ - sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; /**< Data field for advertiser scan_request event*/ - sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; /**< Data field for periodic_advertiser status event*/ - sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; /**< Data field for scanner legacy_advertisement_report event*/ - sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; /**< Data field for scanner extended_advertisement_report event*/ - sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; /**< Data field for scanner scan_report event*/ - sl_bt_evt_sync_opened_t evt_sync_opened; /**< Data field for sync opened event*/ - sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; /**< Data field for sync transfer_received event*/ - sl_bt_evt_sync_data_t evt_sync_data; /**< Data field for sync data event*/ - sl_bt_evt_sync_closed_t evt_sync_closed; /**< Data field for sync closed event*/ - sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; /**< Data field for periodic_sync opened event*/ - sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; /**< Data field for periodic_sync transfer_received event*/ - sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; /**< Data field for periodic_sync report event*/ - sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; /**< Data field for pawr_sync opened event*/ - sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; /**< Data field for pawr_sync transfer_received event*/ - sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; /**< Data field for pawr_sync subevent_report event*/ - sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; /**< Data field for pawr_advertiser subevent_data_request event*/ - sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; /**< Data field for pawr_advertiser subevent_tx_failed event*/ - sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; /**< Data field for pawr_advertiser response_report event*/ - sl_bt_evt_connection_opened_t evt_connection_opened; /**< Data field for connection opened event*/ - sl_bt_evt_connection_parameters_t evt_connection_parameters; /**< Data field for connection parameters event*/ - sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; /**< Data field for connection set_parameters_failed event*/ - sl_bt_evt_connection_phy_status_t evt_connection_phy_status; /**< Data field for connection phy_status event*/ - sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; /**< Data field for connection get_remote_tx_power_completed event*/ - sl_bt_evt_connection_tx_power_t evt_connection_tx_power; /**< Data field for connection tx_power event*/ - sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; /**< Data field for connection remote_tx_power event*/ - sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; /**< Data field for connection remote_used_features event*/ - sl_bt_evt_connection_data_length_t evt_connection_data_length; /**< Data field for connection data_length event*/ - sl_bt_evt_connection_statistics_t evt_connection_statistics; /**< Data field for connection statistics event*/ - sl_bt_evt_connection_closed_t evt_connection_closed; /**< Data field for connection closed event*/ - sl_bt_evt_connection_rssi_t evt_connection_rssi; /**< Data field for connection rssi event*/ - sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; /**< Data field for gatt mtu_exchanged event*/ - sl_bt_evt_gatt_service_t evt_gatt_service; /**< Data field for gatt service event*/ - sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; /**< Data field for gatt characteristic event*/ - sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; /**< Data field for gatt descriptor event*/ - sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; /**< Data field for gatt characteristic_value event*/ - sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; /**< Data field for gatt descriptor_value event*/ - sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; /**< Data field for gatt procedure_completed event*/ - sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; /**< Data field for gatt_server attribute_value event*/ - sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; /**< Data field for gatt_server user_read_request event*/ - sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; /**< Data field for gatt_server user_write_request event*/ - sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; /**< Data field for gatt_server characteristic_status event*/ - sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; /**< Data field for gatt_server execute_write_completed event*/ - sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; /**< Data field for gatt_server indication_timeout event*/ - sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; /**< Data field for gatt_server notification_tx_completed event*/ - sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; /**< Data field for test dtm_completed event*/ - sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; /**< Data field for sm passkey_display event*/ - sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; /**< Data field for sm passkey_request event*/ - sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; /**< Data field for sm confirm_passkey event*/ - sl_bt_evt_sm_bonded_t evt_sm_bonded; /**< Data field for sm bonded event*/ - sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; /**< Data field for sm bonding_failed event*/ - sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; /**< Data field for sm confirm_bonding event*/ - sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; /**< Data field for external_bondingdb data_request event*/ - sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; /**< Data field for external_bondingdb data event*/ - sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; /**< Data field for external_bondingdb data_ready event*/ - sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; /**< Data field for cs security_enable_complete event*/ - sl_bt_evt_cs_config_complete_t evt_cs_config_complete; /**< Data field for cs config_complete event*/ - sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; /**< Data field for cs procedure_enable_complete event*/ - sl_bt_evt_cs_result_t evt_cs_result; /**< Data field for cs result event*/ - sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; /**< Data field for l2cap le_channel_open_request event*/ - sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; /**< Data field for l2cap le_channel_open_response event*/ - sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; /**< Data field for l2cap channel_data event*/ - sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; /**< Data field for l2cap channel_credit event*/ - sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; /**< Data field for l2cap channel_closed event*/ - sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; /**< Data field for l2cap command_rejected event*/ - sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; /**< Data field for cte_receiver dtm_iq_report event*/ - sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; /**< Data field for cte_receiver connection_iq_report event*/ - sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; /**< Data field for cte_receiver connectionless_iq_report event*/ - sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; /**< Data field for cte_receiver silabs_iq_report event*/ - sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; /**< Data field for connection_analyzer report event*/ - sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; /**< Data field for connection_analyzer completed event*/ - sl_bt_evt_user_message_to_host_t evt_user_message_to_host; /**< Data field for user message_to_host event*/ - uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; - } data; -}); - -/** - * @brief Type definition for the data structure of BT API messages - */ -typedef struct sl_bt_msg sl_bt_msg_t; - -/** @} */ // end addtogroup sl_bt_common_types -/******************************************************************************/ - -/***************************************************************************//** - * @addtogroup sl_bt_utility_functions Utility Functions - * @brief Utility functions for applications on SoC - * @{ - */ - -/** - * Get the next event that requires processing by user application. Application - * is not blocked if no event is waiting. - * - * @param event the pointer for storing the new event - * @return SL_STATUS_OK if a new event is returned, or SL_STATUS_NOT_FOUND if no - * event is waiting; other value indicates an error occurred - */ -sl_status_t sl_bt_pop_event(sl_bt_msg_t* event); - -/** - * Check whether events are in queue pending for processing. - * Call @ref sl_bt_pop_event to process pending events. - * - * @return true if event is pending; false otherwise - */ -bool sl_bt_event_pending(void); - -/** - * Check whether events are in queue pending for processing and return the next - * event length in bytes if events are pending. - * Call @ref sl_bt_pop_event to process pending events. - * - * @return the next event length if event is pending; 0 otherwise - */ -uint32_t sl_bt_event_pending_len(void); - - -/** - * Run the Bluetooth stack to process scheduled tasks. Events for user - * application may be generated as a result of this operation. - */ -void sl_bt_run(); - -/** - * Handle an API command in binary format. - * - * This is provided to NCP target applications for processing commands received - * from NCP transport. This function is a synonym for a generic BGAPI function - * @ref sl_bgapi_handle_command. If the NCP application uses an RTOS, use the - * sequence documented in @ref sl_bgapi_handle_command to handle the BGAPI - * command in a thread-safe manner. - * - * @param hdr the command header - * @param data the command payload in a byte array - */ -void sl_bt_handle_command(uint32_t hdr, void* data); - -/** - * Get the response to the command currently been handled. - * - * This is provided to NCP target applications for processing commands received - * from NCP transport. This function is a synonym for a generic BGAPI function - * @ref sl_bgapi_get_command_response. - */ -static inline sl_bt_msg_t* sl_bt_get_command_response() -{ - return (sl_bt_msg_t*) sl_bgapi_get_command_response(); -} - -/** - * Priority message handler function if user application requires the use of - * PendSV interrupt. - * - * If scheduler_callback function pointer in configuration struct is something - * else than NULL, then stack will not install its own PendSV IRQ handler but - * instead uses callback/handler functions. - * - * When application receives call to the scheduler_callback function it must - * schedule the call to gecko_priority_handle function to later time to run on - * high priority thread. This callback may happen inside radio IRQ so processing - * must not block and has to happen as fast as possible. - * - * Recommended implementation: High priority thread is loop that waits on binary - * semaphore and calls gecko_priority_handler. The scheduler_callback is simple - * function that only signals the semaphore. - * - */ -void sl_bt_priority_handle(void); - -/** - * @brief Signal the Bluetooth stack that an external event has happened. - * - * Signals can be used to report status changes from interrupt context or from - * other threads to application. Signals are bits that are automatically cleared - * after application has been notified. - * - * If the Platform Core Interrupt API has been configured to use the - * CORE_ATOMIC_METHOD_BASEPRI as the implementation method of atomic sections, - * this function must not be called from an interrupt handler with a priority - * higher than CORE_ATOMIC_BASE_PRIORITY_LEVEL. - * - * @param signals is a bitmask defining active signals that are reported back to - * the application by system_external_signal-event. - * @return SL_STATUS_OK if the operation is successful, - * SL_STATUS_NO_MORE_RESOURCE indicating the request could not be processed - * due to resource limitation at the moment, or SL_STATUS_INVALID_STATE when - * the on-demand start feature is used and the stack is currently stopped. - */ -sl_status_t sl_bt_external_signal(uint32_t signals); - -/** - * Signals stack to send system_awake event when application received wakeup - * signal. - */ -void sl_bt_send_system_awake(); - -/** - * Signals stack to send system_error event when in case of an error. - */ -void sl_bt_send_system_error(uint16_t reason, uint8_t data_len, const uint8_t *data); - -/** - * Tells if a SL_BT_API message is sensitive. - * - * @param[in] message_header The header of the SL_BT_API message - * @return 1 if the message is sensitive; otherwise 0 - */ -uint8_t sl_bt_is_sensitive_message(uint32_t message_header); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_rsp_user_message_to_target_id. - * - * This a utility helping a NCP host and target application to exchange user - * data. Do not use it in SoC mode. - */ -void sl_bt_send_rsp_user_message_to_target(uint16_t result, uint8_t data_len, uint8_t *data); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_evt_user_message_to_host_id. - * - * This a utility helping a NCP host and target application to exchange user - * data. Do not use it in SoC mode. - */ -void sl_bt_send_evt_user_message_to_host(uint8_t data_len, uint8_t *data); - -/** - * Sends the NCP host a message whose SL_BT_MSG_ID is - * gecko_rsp_user_manage_event_filter_id. - * - * This a utility helping a NCP host and target application to manage event - * filter. Do not use it in SoC mode. - */ -void sl_bt_send_rsp_user_manage_event_filter(uint16_t result); - - -/** @} */ // end addtogroup sl_bt_utility_functions -/******************************************************************************/ - -#ifdef __cplusplus -} -#endif - +/***************************************************************************//** + * @brief SL_BT_API command declarations + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + + +#ifndef SL_BT_API_H +#define SL_BT_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include "sl_status.h" +#include "sl_bgapi.h" +#include "sl_bt_api_compatibility.h" + + +/* SL_BT_ synonyms for BGAPI header macros */ +#define SL_BT_MSG_ID(HDR) SL_BGAPI_MSG_ID(HDR) +#define SL_BT_MSG_HEADER_LEN SL_BGAPI_MSG_HEADER_LEN +#define SL_BT_MSG_LEN(HDR) SL_BGAPI_MSG_LEN(HDR) +#define SL_BT_BIT_ENCRYPTED SL_BGAPI_BIT_ENCRYPTED +#define SL_BT_MSG_ENCRYPTED(HDR) SL_BGAPI_MSG_ENCRYPTED(HDR) + +/** + * @addtogroup sl_bt_common_types BT Common Types + * @{ + * + * @brief BT common types + */ + +/** + * @brief Value used to indicate an invalid connection handle + */ +#define SL_BT_INVALID_CONNECTION_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid bonding handle + */ +#define SL_BT_INVALID_BONDING_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid advertising set handle + */ +#define SL_BT_INVALID_ADVERTISING_SET_HANDLE ((uint8_t) 0xFF) + +/** + * @brief Value used to indicate an invalid sync handle + */ +#define SL_BT_INVALID_SYNC_HANDLE ((uint16_t) 0xFFFF) + +/** + * @brief Value used to indicate an invalid connection analyzer handle + */ +#define SL_BT_INVALID_CONNECTION_ANALYZER_HANDLE ((uint8_t) 0xFF) + +/** @} */ // end addtogroup sl_bt_common_types + + +/** + * @brief ABR subevent length + */ +typedef struct { + uint8_t data[3]; /**< ABR subevent length */ +} sl_bt_cs_subevent_length_t; + +/** + * @brief DRBG key + */ +typedef struct { + uint8_t data[16]; /**< DRBG key */ +} sl_bt_drbg_key_t; + +/** + * @brief 79 1-bit fields containing the values of the ABR channel index + */ +typedef struct { + uint8_t data[10]; /**< 79 1-bit fields containing the values of the ABR channel index */ +} sl_bt_cs_channel_map_t; + +/** + * @brief 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection + */ +typedef struct { + uint8_t data[5]; /**< 37 1-bit fields containing the values of the link layer channel index on a Bluetooth connection */ +} sl_bt_connection_channel_map_t; + + + +/** + * @addtogroup sl_bt_dfu Device Firmware Update + * @{ + * + * @brief Device Firmware Update + * + * These commands and events are related to controlling firmware updates over + * the configured host interface and are available only when the device is + * booted in DFU mode. DFU process: + * 1. Boot device to DFU mode with the Bootloader interface + * 2. Wait for @ref sl_bt_evt_dfu_boot event + * 3. Send command @ref sl_bt_dfu_flash_set_address command to start the + * firmware update + * 4. Upload the firmware with @ref sl_bt_dfu_flash_upload commands until all + * data is uploaded + * 5. Send @ref sl_bt_dfu_flash_upload_finish command when all data is + * uploaded + * 6. Finalize DFU firmware update with @ref sl_bt_system_reset command + * + * DFU mode is using the UART baudrate set in bootloader. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_dfu_flash_set_address_id 0x01000020 +#define sl_bt_cmd_dfu_flash_upload_id 0x02000020 +#define sl_bt_cmd_dfu_flash_upload_finish_id 0x03000020 +#define sl_bt_rsp_dfu_flash_set_address_id 0x01000020 +#define sl_bt_rsp_dfu_flash_upload_id 0x02000020 +#define sl_bt_rsp_dfu_flash_upload_finish_id 0x03000020 + +/** + * @addtogroup sl_bt_evt_dfu_boot sl_bt_evt_dfu_boot + * @{ + * @brief This event indicates that the device booted in DFU mode and is now + * ready to receive commands related to device firmware upgrade (DFU). + */ + +/** @brief Identifier of the boot event */ +#define sl_bt_evt_dfu_boot_id 0x000000a0 + +/***************************************************************************//** + * @brief Data structure of the boot event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_dfu_boot_s +{ + uint32_t version; /**< The version of the bootloader */ +}); + +typedef struct sl_bt_evt_dfu_boot_s sl_bt_evt_dfu_boot_t; + +/** @} */ // end addtogroup sl_bt_evt_dfu_boot + +/** + * @addtogroup sl_bt_evt_dfu_boot_failure sl_bt_evt_dfu_boot_failure + * @{ + * @brief This event indicates that an error, which prevents the device from + * booting, has occurred in bootloader. + */ + +/** @brief Identifier of the boot_failure event */ +#define sl_bt_evt_dfu_boot_failure_id 0x010000a0 + +/***************************************************************************//** + * @brief Data structure of the boot_failure event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_dfu_boot_failure_s +{ + uint16_t reason; /**< The reason for boot failure. */ +}); + +typedef struct sl_bt_evt_dfu_boot_failure_s sl_bt_evt_dfu_boot_failure_t; + +/** @} */ // end addtogroup sl_bt_evt_dfu_boot_failure + +/***************************************************************************//** + * + * After re-booting the local device in DFU mode, this command defines the + * starting address on the flash where the new firmware will be written. + * + * @param[in] address The offset in the flash where the new firmware is uploaded + * to. Always use the value 0x00000000. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_set_address(uint32_t address); + +/***************************************************************************//** + * + * Upload the whole firmware image file into the Bluetooth device. The passed + * data length must be a multiple of 4 bytes. Because the BGAPI command payload + * size is limited, multiple commands need to be issued one after the other + * until the whole firmware image file is uploaded to the device. After each + * command, the next address of the flash sector in memory to write to is + * automatically updated by the bootloader. + * + * @param[in] data_len Length of data in @p data + * @param[in] data An array of data which will be written onto the flash. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_upload(size_t data_len, const uint8_t* data); + +/***************************************************************************//** + * + * Inform the device that the DFU file is fully uploaded. To return the device + * back to normal mode, issue the command @ref sl_bt_system_reset. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_dfu_flash_upload_finish(); + +/** @} */ // end addtogroup sl_bt_dfu + +/** + * @addtogroup sl_bt_system System + * @{ + * + * @brief System + * + * Commands and events in this class can be used to access and query the local + * device. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_system_hello_id 0x00010020 +#define sl_bt_cmd_system_start_bluetooth_id 0x1c010020 +#define sl_bt_cmd_system_stop_bluetooth_id 0x1d010020 +#define sl_bt_cmd_system_forcefully_stop_bluetooth_id 0x1e010020 +#define sl_bt_cmd_system_get_version_id 0x1b010020 +#define sl_bt_cmd_system_reset_id 0x01010020 +#define sl_bt_cmd_system_halt_id 0x0c010020 +#define sl_bt_cmd_system_linklayer_configure_id 0x0e010020 +#define sl_bt_cmd_system_set_tx_power_id 0x17010020 +#define sl_bt_cmd_system_get_tx_power_setting_id 0x18010020 +#define sl_bt_cmd_system_set_identity_address_id 0x13010020 +#define sl_bt_cmd_system_get_identity_address_id 0x15010020 +#define sl_bt_cmd_system_get_random_data_id 0x0b010020 +#define sl_bt_cmd_system_data_buffer_write_id 0x12010020 +#define sl_bt_cmd_system_data_buffer_clear_id 0x14010020 +#define sl_bt_cmd_system_get_counters_id 0x0f010020 +#define sl_bt_cmd_system_set_lazy_soft_timer_id 0x1a010020 +#define sl_bt_rsp_system_hello_id 0x00010020 +#define sl_bt_rsp_system_start_bluetooth_id 0x1c010020 +#define sl_bt_rsp_system_stop_bluetooth_id 0x1d010020 +#define sl_bt_rsp_system_forcefully_stop_bluetooth_id 0x1e010020 +#define sl_bt_rsp_system_get_version_id 0x1b010020 +#define sl_bt_rsp_system_reset_id 0x01010020 +#define sl_bt_rsp_system_halt_id 0x0c010020 +#define sl_bt_rsp_system_linklayer_configure_id 0x0e010020 +#define sl_bt_rsp_system_set_tx_power_id 0x17010020 +#define sl_bt_rsp_system_get_tx_power_setting_id 0x18010020 +#define sl_bt_rsp_system_set_identity_address_id 0x13010020 +#define sl_bt_rsp_system_get_identity_address_id 0x15010020 +#define sl_bt_rsp_system_get_random_data_id 0x0b010020 +#define sl_bt_rsp_system_data_buffer_write_id 0x12010020 +#define sl_bt_rsp_system_data_buffer_clear_id 0x14010020 +#define sl_bt_rsp_system_get_counters_id 0x0f010020 +#define sl_bt_rsp_system_set_lazy_soft_timer_id 0x1a010020 + +/** + * @brief Specifies the mode that the system will boot into. + */ +typedef enum +{ + sl_bt_system_boot_mode_normal = 0x0, /**< (0x0) Boot to normal mode */ + sl_bt_system_boot_mode_uart_dfu = 0x1, /**< (0x1) Boot to UART DFU mode */ + sl_bt_system_boot_mode_ota_dfu = 0x2 /**< (0x2) Boot to OTA DFU mode */ +} sl_bt_system_boot_mode_t; + +/** + * @brief These Keys are used to configure Link Layer Operation + */ +typedef enum +{ + sl_bt_system_linklayer_config_key_halt = 0x1, /**< + (0x1) + Same + as + system_halt + command, + value-0 + Stop + Radio + 1- + Start + Radio */ + sl_bt_system_linklayer_config_key_priority_range = 0x2, /**< + (0x2) + Sets + the + RAIL + priority_mapping + offset + field + of + the + link + layer + priority + configuration + structure + to + the + first + byte + of + the + value + field. */ + sl_bt_system_linklayer_config_key_scan_channels = 0x3, /**< + (0x3) + Sets + channels + to + scan + on. + The + first + byte + of + the + value + is + the + channel + map. + 0x1 + = + Channel + 37, + 0x2 + = + Channel + 38, + 0x4 + = + Channel + 39 */ + sl_bt_system_linklayer_config_key_set_flags = 0x4, /**< + (0x4) + Sets + the + link + layer + configuration + flags. + The + value + is + a + little + endian + 32-bit + integer. + Flag + Values: + - 0x00000001 + \- + Disable + Feature + Exchange + in + peripheral + role + of + the + connection + - 0x00000002 + \- + Disable + Feature + Exchange + in + central + role + of + the + connection */ + sl_bt_system_linklayer_config_key_clr_flags = 0x5, /**< + (0x5) + The + value + is + flags + to + clear. + Flags + are + the + same + as + in + SET_FLAGS + command. */ + sl_bt_system_linklayer_config_key_set_afh_interval = 0x7, /**< + (0x7) + Set + the + afh_scan_interval. + Value + is + in + units + of + 10 + ms. + Setting + the + interval + to + 0 + will + result + in + using + the + default + value + of + 1 + second. */ + sl_bt_system_linklayer_config_key_set_priority_table = 0x9, /**< + (0x9) + The + value + contains + a + priority + table + to + be + copied + over + the + existing + table. + If + the + value + is + smaller + than + the + full + table, + only + those + values + are + updated. + See + sl_bt_bluetooth_ll_priorities + struct + for + the + definition + of + a + priority + table. */ + sl_bt_system_linklayer_config_key_set_rx_packet_filtering = 0xa, /**< + (0xa) + Configure + and + enable + or + disable + RX + packet + filtering + feature. + Value: + >= + 5 + bytes. + - Byte + 1 + \- + The + filter + count + - Byte + 2 + \- + The + filter + offset + - Byte + 3 + \- + The + length + of + the + filter + list + - Byte + 4 + \- + The + bitmask + flags + - Rest + of + the + data + \- + The + filter + list */ + sl_bt_system_linklayer_config_key_set_simultaneous_scanning = 0xb, /**< + (0xb) + Enable + or + disable + simultaneous + scanning + on + the + 1M + and + Coded + PHYs. + Value: + 1 + byte. + - 0 + \- + Disable + simultaneous + scanning. + - 1 + \- + Enable + simultaneous + scanning. */ + sl_bt_system_linklayer_config_key_set_channelmap_flags = 0xc, /**< + (0xc) + Configure + channelmap + adaptivity + flags. + Value: + 4 + bytes. */ + sl_bt_system_linklayer_config_key_power_control_golden_range = 0x10, /**< + (0x10) + Set + Power + Control + golden + range + parameters. + The + value + is + a + 8-bytes + long + array + that + consists + of + 4 + pairs + of + golden + range + configurations. + In + each + pair, + the + first + byte + is + the + lower + RSSI + boundary + and + the + second + byte + is + the + upper + RSSI + boundary. + RSSI + values + are + in + dBm. + This + configuration + is + not + allowed + if + there + are + active + Bluetooth + connections. + - Byte + 1 + \- + Minimal + RSSI + on + 1M + PHY + - Byte + 2 + \- + Maximal + RSSI + on + 1M + PHY + - Byte + 3 + \- + Minimal + RSSI + on + 2M + PHY + - Byte + 4 + \- + Maximal + RSSI + on + 2M + PHY + - Byte + 5 + \- + Minimal + RSSI + on + Coded + PHY + S=8 + - Byte + 6 + \- + Maximal + RSSI + on + Coded + PHY + S=8 + - Byte + 7 + \- + Minimal + RSSI + on + Coded + PHY + S=2 + - Byte + 8 + \- + Maximal + RSSI + on + Coded + PHY + S=2 */ + sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit = 0x11, /**< + (0x11) + Value: + uint16_t + Adjust + upper + limit + for + backoff + counter. + If + 0 + restores + default + value + of + 256 + Value + must + be + between + 16 + \- + 256 */ + sl_bt_system_linklayer_config_key_afh_rssi_threshold = 0x12, /**< + (0x12) + Value: + int8_t + Configures + RSSI + limit + for + AFH + channel + blocking */ + sl_bt_system_linklayer_config_key_afh_channel_cooldown = 0x13, /**< + (0x13) + Value: + int16_t + Configures + how + long + channel + is + blocked + after + activity + is + detected + Default: + 8000 */ + sl_bt_system_linklayer_config_key_set_report_all_scan_rsps = 0x14 /**< + (0x14) + Value: + uint8_t + 0 + \- + default, + only + reports + scan + responses + that + is + received + after + sending + scan_req + nonzero + \- + Will + report + all + scan + responses + that + are + received + on + primary + advertising + channels */ +} sl_bt_system_linklayer_config_key_t; + +/** + * @addtogroup sl_bt_evt_system_boot sl_bt_evt_system_boot + * @{ + * @brief Indicates that the device has started and the radio is ready + * + * This event carries the firmware build number and other software and hardware + * identification codes. + */ + +/** @brief Identifier of the boot event */ +#define sl_bt_evt_system_boot_id 0x000100a0 + +/***************************************************************************//** + * @brief Data structure of the boot event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_boot_s +{ + uint16_t major; /**< Major release version */ + uint16_t minor; /**< Minor release version */ + uint16_t patch; /**< Patch release number */ + uint16_t build; /**< Build number */ + uint32_t bootloader; /**< Unused. Ignore this field. */ + uint16_t hw; /**< Hardware type: the major chip revision number in the + most significant byte and the minor revision in the + least significant byte */ + uint32_t hash; /**< Version hash */ +}); + +typedef struct sl_bt_evt_system_boot_s sl_bt_evt_system_boot_t; + +/** @} */ // end addtogroup sl_bt_evt_system_boot + +/** + * @addtogroup sl_bt_evt_system_stopped sl_bt_evt_system_stopped + * @{ + * @brief When the Bluetooth on-demand start component is included in the + * application build, this event is triggered when stopping the Bluetooth stack + * using commands @ref sl_bt_system_stop_bluetooth or @ref + * sl_bt_system_forcefully_stop_bluetooth has completed. + */ + +/** @brief Identifier of the stopped event */ +#define sl_bt_evt_system_stopped_id 0x010100a0 + +/** @} */ // end addtogroup sl_bt_evt_system_stopped + +/** + * @addtogroup sl_bt_evt_system_error sl_bt_evt_system_error + * @{ + * @brief Indicates that an error has occurred + * + * See error codes table for more information. + */ + +/** @brief Identifier of the error event */ +#define sl_bt_evt_system_error_id 0x060100a0 + +/***************************************************************************//** + * @brief Data structure of the error event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_error_s +{ + uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ + uint8array data; /**< Data related to the error; this field can be empty. */ +}); + +typedef struct sl_bt_evt_system_error_s sl_bt_evt_system_error_t; + +/** @} */ // end addtogroup sl_bt_evt_system_error + +/** + * @addtogroup sl_bt_evt_system_hardware_error sl_bt_evt_system_hardware_error + * @{ + * @brief Indicates that a hardware-related error has occurred. + */ + +/** @brief Identifier of the hardware_error event */ +#define sl_bt_evt_system_hardware_error_id 0x050100a0 + +/***************************************************************************//** + * @brief Data structure of the hardware_error event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_hardware_error_s +{ + uint16_t status; /**< SL_STATUS_OK if successful. Error code otherwise. */ +}); + +typedef struct sl_bt_evt_system_hardware_error_s sl_bt_evt_system_hardware_error_t; + +/** @} */ // end addtogroup sl_bt_evt_system_hardware_error + +/** + * @addtogroup sl_bt_evt_system_resource_exhausted sl_bt_evt_system_resource_exhausted + * @{ + * @brief Indicates that a system resource has been exhausted during the + * operation of the Bluetooth stack + * + * If resource errors occur already when the Bluetooth stack is starting, the + * error is reported directly as a return value from sl_bt_stack_init (when the + * Bluetooth on-demand start component is not included in the application + * build), or from @ref sl_bt_system_start_bluetooth (when the on-demand start + * component is included). The fields of this event indicate how many failures + * have occurred for a specific resource. If further resource failures occur + * while this event is already queued in the BGAPI event queue but not yet + * delivered to the application, the new failures are included in the already + * queued event. When the application receives this event, the fields represent + * the number of failures that have occurred since the previous @ref + * sl_bt_evt_system_resource_exhausted event. + */ + +/** @brief Identifier of the resource_exhausted event */ +#define sl_bt_evt_system_resource_exhausted_id 0x080100a0 + +/***************************************************************************//** + * @brief Data structure of the resource_exhausted event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_resource_exhausted_s +{ + uint8_t num_buffers_discarded; /**< The system has temporarily run + out of the pre-allocated data + buffers that are allocated based + on SL_BT_CONFIG_BUFFER_SIZE + configuration and some expendable + data or event had to be discarded + to satisfy a non-expendble buffer + allocation. A typical case is + discarding scan reports when a + large inflow of scan reports + exceeds the speed at which the + application drains the BGAPI + event queue. */ + uint8_t num_buffer_allocation_failures; /**< The system has run out of the + pre-allocated data buffers that + are allocated based on + SL_BT_CONFIG_BUFFER_SIZE + configuration and a buffer + allocation has failed. */ + uint8_t num_heap_allocation_failures; /**< The Bluetooth stack has failed to + make an allocation from the heap. + Note that only allocations made + by the Bluetooth stack are + detected and reported by this + field. Allocation failures in + other components that use + sl_malloc() or malloc() are not + included in this count. */ +}); + +typedef struct sl_bt_evt_system_resource_exhausted_s sl_bt_evt_system_resource_exhausted_t; + +/** @} */ // end addtogroup sl_bt_evt_system_resource_exhausted + +/** + * @addtogroup sl_bt_evt_system_external_signal sl_bt_evt_system_external_signal + * @{ + * @brief Indicates that the external signals have been received + * + * External signals are generated from the native application. + */ + +/** @brief Identifier of the external_signal event */ +#define sl_bt_evt_system_external_signal_id 0x030100a0 + +/***************************************************************************//** + * @brief Data structure of the external_signal event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_external_signal_s +{ + uint32_t extsignals; /**< Bitmask of external signals received since last + event. */ +}); + +typedef struct sl_bt_evt_system_external_signal_s sl_bt_evt_system_external_signal_t; + +/** @} */ // end addtogroup sl_bt_evt_system_external_signal + +/** + * @addtogroup sl_bt_evt_system_awake sl_bt_evt_system_awake + * @{ + * @brief Indicates that the device is awake and no longer in sleep mode + * + * NOTE: Stack does not generate this event by itself because sleep and + * wakeup are managed by applications. If this event is needed, call function + * @ref sl_bt_send_system_awake, which signals the stack to send the event. + */ + +/** @brief Identifier of the awake event */ +#define sl_bt_evt_system_awake_id 0x040100a0 + +/** @} */ // end addtogroup sl_bt_evt_system_awake + +/** + * @addtogroup sl_bt_evt_system_soft_timer sl_bt_evt_system_soft_timer + * @{ + * @brief Indicates that a soft timer has lapsed. + */ + +/** @brief Identifier of the soft_timer event */ +#define sl_bt_evt_system_soft_timer_id 0x070100a0 + +/***************************************************************************//** + * @brief Data structure of the soft_timer event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_system_soft_timer_s +{ + uint8_t handle; /**< Timer Handle */ +}); + +typedef struct sl_bt_evt_system_soft_timer_s sl_bt_evt_system_soft_timer_t; + +/** @} */ // end addtogroup sl_bt_evt_system_soft_timer + +/***************************************************************************//** + * + * Verify whether the communication between the host and the device is + * functional. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_hello(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the on-demand start command is not available and the + * command returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to request starting the + * Bluetooth stack when the application needs it. If the command returns a + * success result, the stack starts to asynchronously allocate the resources and + * configure the Bluetooth stack based on the configuration passed at + * initialization time. + * + * The Bluetooth stack cannot be restarted while it's still stopping after + * issuing the command @ref sl_bt_system_stop_bluetooth. If @ref + * sl_bt_system_start_bluetooth is called when stopping is still on-going the + * command returns the error SL_STATUS_INVALID_STATE. The application must wait + * for the @ref sl_bt_evt_system_stopped event before attempting to restart the + * stack. + * + * Successful start of the stack is indicated by the @ref sl_bt_evt_system_boot + * event. The configured classes and Bluetooth stack features are available + * after the application has received the @ref sl_bt_evt_system_boot event. If + * starting the Bluetooth stack fails, the error is indicated to the application + * with the @ref sl_bt_evt_system_error event. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_boot - Triggered when the Bluetooth stack has + * succesfully started and is ready to accept commands from the application + * - @ref sl_bt_evt_system_error - Triggered if the command to start the + * Bluetooth stack was accepted but the asynchronous starting of the stack + * has failed + * + ******************************************************************************/ +sl_status_t sl_bt_system_start_bluetooth(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the stop command is not available and the command + * returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to stop the Bluetooth stack + * when the application no longer needs it. This command gracefully restores + * Bluetooth to an idle state by disconnecting any active connections and + * stopping any on-going advertising and scanning. Any resources that were + * allocated when the stack was started are freed when the stack has finished + * stopping. After this command, the BGAPI classes other than @ref sl_bt_system + * become unavailable. + * + * Stopping the Bluetooth stack with this command is asynchronous and the + * completion is indicated by the @ref sl_bt_evt_system_stopped event. The + * application can use the command @ref sl_bt_system_start_bluetooth to restart + * the stack any time after it has received the @ref sl_bt_evt_system_stopped + * event. If the application needs to stop the Bluetooth stack immediately, use + * the command @ref sl_bt_system_forcefully_stop_bluetooth. That command can + * also be used to immediately complete the asynchronous stopping if the command + * @ref sl_bt_system_stop_bluetooth has not completed in expected time period. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_stopped - Triggered when stopping the Bluetooth + * stack has completed + * + ******************************************************************************/ +sl_status_t sl_bt_system_stop_bluetooth(); + +/***************************************************************************//** + * + * If the Bluetooth on-demand start component is not included in the application + * build, the Bluetooth stack is automatically started when the device boots up. + * In this configuration, the stop command is not available and the command + * returns the error SL_STATUS_NOT_AVAILABLE. + * + * When the Bluetooth on-demand start component is included in the application + * build, this command is used by the application to forcefully stop the + * Bluetooth stack when the application no longer needs it. This command + * immediately stops all active Bluetooth operations such as advertising, + * scanning, and connections. Active connections are forcefully closed without + * performing the ACL Termination procedure. This can result in the observation + * of connection loss or supervision timeout on the remote device. Only use this + * command for special cases, for example, when stopping Bluetooth with @ref + * sl_bt_system_stop_bluetooth did not complete in expected time period. + * + * Stopping the Bluetooth stack with this command is immediate and it directly + * triggers the @ref sl_bt_evt_system_stopped event. Any resources that were + * allocated when the stack was started are freed. After this command, the BGAPI + * classes other than @ref sl_bt_system become unavailable. The application can + * use the command @ref sl_bt_system_start_bluetooth to continue using Bluetooth + * later. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_stopped - Triggered immediately to indicate the + * Bluetooth stack has stopped + * + ******************************************************************************/ +sl_status_t sl_bt_system_forcefully_stop_bluetooth(); + +/***************************************************************************//** + * + * Get the firmware version information. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * @param[out] major Major release version + * @param[out] minor Minor release version + * @param[out] patch Patch release number + * @param[out] build Build number + * @param[out] bootloader Unused. Ignore this field. + * @param[out] hash Version hash + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_version(uint16_t *major, + uint16_t *minor, + uint16_t *patch, + uint16_t *build, + uint32_t *bootloader, + uint32_t *hash); + +/***************************************************************************//** + * + * Reset the system. This command does not have a response. + * + * On EFR series 1 devices, this command boots into the given mode and triggers + * one of the boot events (normal reset or boot to DFU mode) depending on the + * given boot mode. + * + * On EFR series 2 devices, the @p dfu parameter is ignored and this command + * always boots the user application. To boot into a DFU mode on series 2, use + * the Bootloader API @c bootloader_rebootAndInstall. + * + * NOTE: This command is available even if the Bluetooth stack has not + * been started. See @ref sl_bt_system_start_bluetooth for description of how + * the Bluetooth stack is started. + * + * @param[in] dfu @parblock + * Enum @ref sl_bt_system_boot_mode_t. Boot mode. Values: + * - sl_bt_system_boot_mode_normal (0x0): Boot to normal mode + * - sl_bt_system_boot_mode_uart_dfu (0x1): Boot to UART DFU mode + * - sl_bt_system_boot_mode_ota_dfu (0x2): Boot to OTA DFU mode + * + * This parameter is ignored on EFR series 2 devices. + * @endparblock + * + * @b Events + * - @ref sl_bt_evt_system_boot - Sent after the device has booted in normal + * mode. + * - @ref sl_bt_evt_dfu_boot - Sent after the device has booted in UART DFU + * mode. + * + ******************************************************************************/ +void sl_bt_system_reset(uint8_t dfu); + +/***************************************************************************//** + * + * Force radio to idle state and allow device to sleep. Advertising, scanning, + * connections, and software timers are halted by this command. Halted + * operations resume after calling this command with parameter 0. Connections + * stay alive if the system is resumed before connection supervision timeout. + * + * Use this command only for a short time period (maximum few seconds). Although + * it halts Bluetooth activity, all tasks and operations still exist inside the + * stack with their own concepts of time. Halting the system for a long time + * period may have negative consequences on stack's internal states. + * + * NOTE: The software timer is also halted. Hardware interrupts are the + * only way to wake up from energy mode 2 when the system is halted. + * + * @param[in] halt Values: + * - 1: halt + * - 0: resume + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_halt(uint8_t halt); + +/***************************************************************************//** + * + * Send configuration data to the link layer. This command fine tunes low-level + * Bluetooth operations. + * + * @param[in] key @parblock + * Enum @ref sl_bt_system_linklayer_config_key_t. Key to configure. Values: + * - sl_bt_system_linklayer_config_key_halt (0x1): Same as + * system_halt command, value-0 Stop Radio 1- Start Radio + * - sl_bt_system_linklayer_config_key_priority_range (0x2): Sets the + * RAIL priority_mapping offset field of the link layer priority + * configuration structure to the first byte of the value field. + * - sl_bt_system_linklayer_config_key_scan_channels (0x3): Sets + * channels to scan on. The first byte of the value is the channel map. + * 0x1 = Channel 37, 0x2 = Channel 38, 0x4 = Channel 39 + * - sl_bt_system_linklayer_config_key_set_flags (0x4): Sets the link + * layer configuration flags. The value is a little endian 32-bit integer. + * Flag Values: + * - 0x00000001 - Disable Feature Exchange in peripheral role of the + * connection + * - 0x00000002 - Disable Feature Exchange in central role of the + * connection + * + * - sl_bt_system_linklayer_config_key_clr_flags (0x5): The value is + * flags to clear. Flags are the same as in SET_FLAGS command. + * - sl_bt_system_linklayer_config_key_set_afh_interval (0x7): Set + * the afh_scan_interval. Value is in units of 10 ms. Setting the interval + * to 0 will result in using the default value of 1 second. + * - sl_bt_system_linklayer_config_key_set_priority_table (0x9): The + * value contains a priority table to be copied over the existing table. + * If the value is smaller than the full table, only those values are + * updated. See sl_bt_bluetooth_ll_priorities struct for the definition of + * a priority table. + * - sl_bt_system_linklayer_config_key_set_rx_packet_filtering (0xa): + * Configure and enable or disable RX packet filtering feature. Value: >= + * 5 bytes. + * - Byte 1 - The filter count + * - Byte 2 - The filter offset + * - Byte 3 - The length of the filter list + * - Byte 4 - The bitmask flags + * - Rest of the data - The filter list + * + * - sl_bt_system_linklayer_config_key_set_simultaneous_scanning + * (0xb): Enable or disable simultaneous scanning on the 1M and Coded + * PHYs. Value: 1 byte. + * - 0 - Disable simultaneous scanning. + * - 1 - Enable simultaneous scanning. + * + * - sl_bt_system_linklayer_config_key_set_channelmap_flags (0xc): + * Configure channelmap adaptivity flags. Value: 4 bytes. + * - sl_bt_system_linklayer_config_key_power_control_golden_range + * (0x10): Set Power Control golden range parameters. The value is a + * 8-bytes long array that consists of 4 pairs of golden range + * configurations. In each pair, the first byte is the lower RSSI boundary + * and the second byte is the upper RSSI boundary. RSSI values are in dBm. + * This configuration is not allowed if there are active Bluetooth + * connections. + * - Byte 1 - Minimal RSSI on 1M PHY + * - Byte 2 - Maximal RSSI on 1M PHY + * - Byte 3 - Minimal RSSI on 2M PHY + * - Byte 4 - Maximal RSSI on 2M PHY + * - Byte 5 - Minimal RSSI on Coded PHY S=8 + * - Byte 6 - Maximal RSSI on Coded PHY S=8 + * - Byte 7 - Minimal RSSI on Coded PHY S=2 + * - Byte 8 - Maximal RSSI on Coded PHY S=2 + * + * - sl_bt_system_linklayer_config_key_active_scanner_backoff_upper_limit + * (0x11): Value: uint16_t Adjust upper limit for backoff counter. If + * 0 restores default value of 256 Value must be between 16 - 256 + * - sl_bt_system_linklayer_config_key_afh_rssi_threshold (0x12): + * Value: int8_t Configures RSSI limit for AFH channel blocking + * - sl_bt_system_linklayer_config_key_afh_channel_cooldown (0x13): + * Value: int16_t Configures how long channel is blocked after activity is + * detected Default: 8000 + * - sl_bt_system_linklayer_config_key_set_report_all_scan_rsps + * (0x14): Value: uint8_t 0 - default, only reports scan responses + * that is received after sending scan_req nonzero - Will report all scan + * responses that are received on primary advertising channels + * @endparblock + * @param[in] data_len Length of data in @p data + * @param[in] data Configuration data. Length and contents of the data field + * depend on the key value used. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_linklayer_configure(uint8_t key, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set the global minimum and maximum radiated TX power levels for Bluetooth. + * This returns selected power levels that are radiated from the antenna at TX. + * The transmitter power at antenna pin will apply the RF TX path gain to match + * this setting. RF TX path gain can be set in the Bluetooth configuration. If + * the GATT server contains a TX power service, the TX Power Level attribute + * will be updated with the selected maximum power level. + * + * A selected power level may be different than the requested value because of + * Bluetooth feature restrictions or the device's radio characteristics. For + * Bluetooth connections, the maximum radiated TX power is limited to 10 dBm if + * Adaptive Frequency Hopping (AFH) is not enabled. + * + * The minimum TX power setting is used by LE power control. It has no effect in + * Bluetooth stack if the LE power control feature is not enabled. However, the + * application may still use this setting for other purposes, e.g., setting the + * minimum TX power for DTM transmitter test. + * + * The minimum and maximum radiated TX power levels can also be configured in + * the Bluetooth configuration and passed into the Bluetooth stack + * initialization. By default, the minimum radiated TX power level is configured + * to -3 dBm and the maximum radiated TX power level to 8 dBm. + * + * NOTE: Do not use this command while advertising or scanning. + * Furthermore, the stack does not allow setting TX powers during connections. + * + * @param[in] min_power Minimum radiated TX power. Unit: 0.1 dBm. For example, + * the value 10 means 1 dBm. + * @param[in] max_power Maximum radiated TX power. Unit: 0.1 dBm. For example, + * the value 10 means 1 dBm. + * @param[out] set_min The selected minimum radiated TX power. Unit: 0.1 dBm + * @param[out] set_max The selected maximum radiated TX power. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_tx_power(int16_t min_power, + int16_t max_power, + int16_t *set_min, + int16_t *set_max); + +/***************************************************************************//** + * + * Get TX power settings including the minimum and maximum radiated TX power + * levels the device supports, the minimum and maximum radiated TX power levels + * currently set in the stack, and the TX RF path gain configuration. + * + * @param[out] support_min The minimum radiated TX power the device supports. + * Unit: 0.1 dBm + * @param[out] support_max The maximum radiated TX power the device supports. + * Unit: 0.1 dBm + * @param[out] set_min The minimum radiated TX power currently set in stack. + * Unit: 0.1 dBm + * @param[out] set_max The maximum radiated TX power currently set in stack. + * Unit: 0.1 dBm + * @param[out] rf_path_gain TX RF path gain. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_tx_power_setting(int16_t *support_min, + int16_t *support_max, + int16_t *set_min, + int16_t *set_max, + int16_t *rf_path_gain); + +/***************************************************************************//** + * + * Store the device's Bluetooth identity address in persistent storage using NVM + * keys. The address can be a public device address or a static device address. + * The stack returns an error if the static device address does not conform to + * the Bluetooth specification. + * + * The new address will be effective in the next system reboot. The stack will + * use the address in the NVM keys when present. Otherwise, it uses the default + * Bluetooth public device address which is programmed at production. + * + * The stack treats 00:00:00:00:00:00 and ff:ff:ff:ff:ff:ff as invalid + * addresses. Therefore, passing one of them into this command will cause the + * stack to delete the NVM keys and use the default address in the next system + * reboot. + * + * Note: Because the NVM keys are located in flash and flash wearing can + * occur, avoid calling this command regularly. + * + * @param[in] address Bluetooth identity address in little endian format + * @param[in] type Enum @ref sl_bt_gap_address_type_t. Identity address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_identity_address(bd_addr address, uint8_t type); + +/***************************************************************************//** + * + * Read the Bluetooth identity address used by the device, which can be a public + * or random static device address. + * + * @param[out] address Bluetooth identity address in little endian format + * @param[out] type Enum @ref sl_bt_gap_address_type_t. Identity address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_identity_address(bd_addr *address, uint8_t *type); + +/***************************************************************************//** + * + * Get random data. + * + * @param[in] length Length of random data. + * @param[in] max_data_size Size of output buffer passed in @p data + * @param[out] data_len On return, set to the length of output data written to + * @p data + * @param[out] data Random data + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_random_data(uint8_t length, + size_t max_data_size, + size_t *data_len, + uint8_t *data); + +/***************************************************************************//** + * + * Write data into the system data buffer. Data will be appended to the end of + * existing data. + * + * @param[in] data_len Length of data in @p data + * @param[in] data Data to write + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_data_buffer_write(size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Remove all data from the system data buffer. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_data_buffer_clear(); + +/***************************************************************************//** + * + * Get packet and error counters. Passing a non-zero value also resets counters. + * + * @param[in] reset Reset counters if the parameter value is not zero. + * @param[out] tx_packets The number of successfully transmitted packets + * @param[out] rx_packets The number of successfully received packets + * @param[out] crc_errors The number of received packets with CRC errors + * @param[out] failures The number of radio failures, such as aborted TX/RX + * packets, scheduling failures, and so on. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_system_get_counters(uint8_t reset, + uint16_t *tx_packets, + uint16_t *rx_packets, + uint16_t *crc_errors, + uint16_t *failures); + +/***************************************************************************//** + * + * Deprecated . Use the sleeptimer component (in platform services + * category) for timers. Because the sleeptimer does not support a timer with + * slack yet, the Bluetooth stack will continue to support this command until + * another component provides the functionality. + * + * Start a software timer with slack. The slack parameter allows the stack to + * optimize wakeups and save power. The timer event is triggered between time + * and time + @p slack. + * + * Multiple concurrent timers can be running simultaneously. 256 unique timer + * handles (IDs) are available. The maximum number of concurrent timers is + * configurable at device initialization. Up to 16 concurrent timers can be + * configured. The default configuration is 4. As the RAM for storing timer data + * is pre-allocated at initialization, an application should not configure the + * amount more than it needs for minimizing RAM usage. + * + * @param[in] time @parblock + * An interval between how often to send events in hardware clock ticks (1 + * second is equal to 32768 ticks). + * + * The smallest interval value supported is 328, which is around 10 + * milliseconds. Any parameters between 0 and 328 will be rounded up to 328. + * The maximum value is 2147483647, which corresponds to about 18.2 hours. + * + * If @p time is 0, removes the scheduled timer with the same handle. + * @endparblock + * @param[in] slack Slack time in hardware clock ticks + * @param[in] handle Timer handle to use, which is returned in timeout event + * @param[in] single_shot Timer mode. Values: + * - 0: false (timer is repeating) + * - 1: true (timer runs only once) + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_system_soft_timer - Sent after this timer has lapsed. + * + ******************************************************************************/ +sl_status_t sl_bt_system_set_lazy_soft_timer(uint32_t time, + uint32_t slack, + uint8_t handle, + uint8_t single_shot); + +/** @} */ // end addtogroup sl_bt_system + +/** + * @addtogroup sl_bt_resource Resource Report + * @{ + * + * @brief Resource Report + * + * Commands and events in this class can be used to query and receive the memory + * buffer usage status. The memory buffer is used by the Bluetooth stack for + * storing application data (e.g., API commands and events), user data over + * Bluetooth connections, advertising, scanning, etc. Total buffer size is + * defined by the application using the SL_BT_CONFIG_BUFFER_SIZE configuration. + * The Bluetooth stack does not partition the buffer, instead, the buffer is a + * shared resource for all features. Therefore, the available memory for one + * feature could be affected by another feature in simultaneous use cases. This + * API class provides a utility for application to get some insight of the + * buffer usage. As allocations in the memory buffer have overhead, the actual + * amount of memory that can be used for user data is less than a reported free + * memory amount. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_resource_get_status_id 0x005f0020 +#define sl_bt_cmd_resource_set_report_threshold_id 0x015f0020 +#define sl_bt_cmd_resource_enable_connection_tx_report_id 0x025f0020 +#define sl_bt_cmd_resource_get_connection_tx_status_id 0x035f0020 +#define sl_bt_cmd_resource_disable_connection_tx_report_id 0x045f0020 +#define sl_bt_rsp_resource_get_status_id 0x005f0020 +#define sl_bt_rsp_resource_set_report_threshold_id 0x015f0020 +#define sl_bt_rsp_resource_enable_connection_tx_report_id 0x025f0020 +#define sl_bt_rsp_resource_get_connection_tx_status_id 0x035f0020 +#define sl_bt_rsp_resource_disable_connection_tx_report_id 0x045f0020 + +/** + * @addtogroup sl_bt_resource_connection_tx_flags Connection TX status flags + * @{ + * + * Defines the connection TX status flags reported by @ref + * sl_bt_resource_get_connection_tx_status. + */ + +/** + * + * The number of TX packets queued on a connection has overflowed the @p + * packet_count that was effective at the time the connection opened. The packet + * count is configured with command @ref + * sl_bt_resource_enable_connection_tx_report and is valid for subsequent + * connections. + * + * When this bit is set, the @p packet_count returned by @ref + * sl_bt_resource_get_connection_tx_status is correct, but @p data_len excludes + * the data bytes in the packets that overflowed the configured packet count. + * + * */ +#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_PACKET_OVERFLOW 0x1 + +/** + * + * Internal inconsistency has been detected in the connection TX bookkeeping. + * When this bit is set, the application should consider both @p packet_count + * and @p data_len returned by @ref sl_bt_resource_get_connection_tx_status to + * be unreliable. + * + * */ +#define SL_BT_RESOURCE_CONNECTION_TX_FLAGS_ERROR_CORRUPT 0x2 + +/** @} */ // end Connection TX status flags + +/** + * @addtogroup sl_bt_evt_resource_status sl_bt_evt_resource_status + * @{ + * @brief Indicates that the memory buffer usage has crossed a threshold + */ + +/** @brief Identifier of the status event */ +#define sl_bt_evt_resource_status_id 0x005f00a0 + +/***************************************************************************//** + * @brief Data structure of the status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_resource_status_s +{ + uint32_t free_bytes; /**< The number of free bytes in the memory buffer */ +}); + +typedef struct sl_bt_evt_resource_status_s sl_bt_evt_resource_status_t; + +/** @} */ // end addtogroup sl_bt_evt_resource_status + +/***************************************************************************//** + * + * Get the present memory buffer usage status. + * + * @param[out] total_bytes The number of total bytes in the memory buffer + * @param[out] free_bytes The number of free bytes in the memory buffer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_get_status(uint32_t *total_bytes, + uint32_t *free_bytes); + +/***************************************************************************//** + * + * Set low and high thresholds of memory buffer usage reports. Value 0 in + * parameter @p low for the low threshold disables the reporting, and a non-zero + * value in @p low enables the reporting. + * + * When the reporting is enabled, event @ref sl_bt_evt_resource_status will be + * generated to report the status when the free buffer amount decreases and + * crosses the low threshold, and later another event will be generated if the + * free buffer amount increases and crosses the high threshold. If only the high + * threshold is crossed but the low threshold isn't, no event will be generated. + * + * By default, low and high threshold values are 0, i.e., no report event is + * generated. + * + * @param[in] low The low threshold of free bytes in the memory buffer, or 0 to + * disable the reporting + * @param[in] high A non-zero value as the high threshold that must be greater + * than parameter @p low, or 0 for not reporting the status for high threshold + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_set_report_threshold(uint32_t low, uint32_t high); + +/***************************************************************************//** + * + * Enable tracking and reporting data packet TX status of future new + * connections. Existing connections are not affected by this command. + * + * @param[in] packet_count The maximum number of data packets to track on a + * connection + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_server_notification_tx_completed - Sent when GATT + * notifications from the GATT server were transmitted. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_enable_connection_tx_report(uint16_t packet_count); + +/***************************************************************************//** + * + * Get the data packet TX status of a connection. + * + * @param[in] connection Connection handle + * @param[out] flags Flags that indicate the status of connection TX packet + * reporting. This value is a bitmask of @ref + * sl_bt_resource_connection_tx_flags. + * @param[out] packet_count Number of data packets in the TX queue waiting to be + * transmitted + * @param[out] data_len Total number of bytes of data packets in the TX queue + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_get_connection_tx_status(uint8_t connection, + uint16_t *flags, + uint16_t *packet_count, + uint32_t *data_len); + +/***************************************************************************//** + * + * Disable tracking and reporting data packet TX status of future new + * connections. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resource_disable_connection_tx_report(); + +/** @} */ // end addtogroup sl_bt_resource + +/** + * @addtogroup sl_bt_gap GAP + * @{ + * + * @brief GAP + * + * The commands and events in this class are related to the Generic Access + * Profile (GAP) in Bluetooth. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gap_set_privacy_mode_id 0x01020020 +#define sl_bt_cmd_gap_set_data_channel_classification_id 0x02020020 +#define sl_bt_cmd_gap_enable_whitelisting_id 0x03020020 +#define sl_bt_cmd_gap_set_identity_address_id 0x04020020 +#define sl_bt_rsp_gap_set_privacy_mode_id 0x01020020 +#define sl_bt_rsp_gap_set_data_channel_classification_id 0x02020020 +#define sl_bt_rsp_gap_enable_whitelisting_id 0x03020020 +#define sl_bt_rsp_gap_set_identity_address_id 0x04020020 + +/** + * @brief These values define Bluetooth device address types. Commands and + * events that have Bluetooth device address parameters will specify which + * values are valid for that particular command or event. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, most Bluetooth + * commands and events use a coarse address type that only differentiates + * between a public address and any random address. When the application + * includes the bluetooth_feature_use_accurate_api_address_types component, + * Bluetooth commands and events that include an address type will + * systematically use values of this @ref sl_bt_gap_address_type_t enumeration + * to indicate the accurate address type. + * + * The values @ref sl_bt_gap_public_address_resolved_from_rpa and @ref + * sl_bt_gap_static_address_resolved_from_rpa are reported by the Bluetooth + * stack only when the application includes the bluetooth_feature_resolving_list + * component and the address was resolved in the Bluetooth controller. If the + * application uses these two types in input parameters, they are treated as + * synonyms of @ref sl_bt_gap_public_address and @ref sl_bt_gap_static_address, + * respectively. + */ +typedef enum +{ + sl_bt_gap_public_address = 0x0, /**< (0x0) Public device + address */ + sl_bt_gap_static_address = 0x1, /**< (0x1) Static device + address */ + sl_bt_gap_random_resolvable_address = 0x2, /**< (0x2) Resolvable + private random address */ + sl_bt_gap_random_nonresolvable_address = 0x3, /**< (0x3) Non-resolvable + private random address */ + sl_bt_gap_public_address_resolved_from_rpa = 0x4, /**< (0x4) Public identity + address resolved from + a resolvable private + address (RPA) */ + sl_bt_gap_static_address_resolved_from_rpa = 0x5, /**< (0x5) Static identity + address resolved from + a resolvable private + address (RPA) */ + sl_bt_gap_anonymous_address = 0xff /**< (0xff) No address + provided (anonymous + advertising) */ +} sl_bt_gap_address_type_t; + +/** + * @brief Types of PHYs + */ +typedef enum +{ + sl_bt_gap_phy_1m = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_phy_2m = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_phy_coded = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ + sl_bt_gap_phy_any = 0xff /**< (0xff) Any PHYs the device supports */ +} sl_bt_gap_phy_t; + +/** + * @brief PHY types with coding schemes + */ +typedef enum +{ + sl_bt_gap_phy_coding_1m_uncoded = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_phy_coding_2m_uncoded = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_phy_coding_125k_coded = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ + sl_bt_gap_phy_coding_500k_coded = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ +} sl_bt_gap_phy_coding_t; + +/** + * @brief Types of channel selection algorithms in Link Layer + */ +typedef enum +{ + sl_bt_gap_channel_selection_algorithm_1 = 0x0, /**< (0x0) Channel selection + algorithm #1 */ + sl_bt_gap_channel_selection_algorithm_2 = 0x1 /**< (0x1) Channel selection + algorithm #2 */ +} sl_bt_gap_channel_selection_algorithm_t; + +/***************************************************************************//** + * + * Enable or disable the privacy feature on all GAP roles. New privacy mode will + * take effect for advertising next time advertising is enabled, for scanning + * next time scanning is enabled, and for initiating on the next open connection + * command. + * + * When privacy is enabled and the device is advertising or scanning, the stack + * will maintain a periodic timer with the specified time interval as a timeout + * value. At each timeout, the stack generates a new resolvable private address + * and uses it in scanning requests. For advertisers, the stack generates a new + * resolvable or non-resolvable private address and uses it in advertising data + * packets for each advertising set if its address is not application-managed, + * i.e., the address was not set by the application (with the @ref + * sl_bt_advertiser_set_random_address command). The application is fully + * responsible for application-managed advertiser addresses. For an + * application-managed resolvable private address, the application should + * schedule periodic address updates for enhancing the privacy. It is + * recommended to use different schedules for different advertising sets. + * + * Disabling the privacy during active advertising or scanning is not allowed. + * + * By default, privacy feature is disabled. + * + * @param[in] privacy Values: + * - 0: Disable privacy + * - 1: Enable privacy + * @param[in] interval The minimum time interval between a private address + * change. This parameter is ignored if this command is issued to disable + * privacy mode. Values: + * - 0: Use default interval, 15 minutes + * - others: The time interval in minutes + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_privacy_mode(uint8_t privacy, uint8_t interval); + +/***************************************************************************//** + * + * Specify a channel classification for data channels. This classification + * persists until overwritten with a subsequent command or until the system is + * reset. The value length of @p channel_map must be 5 bytes. + * + * @param[in] channel_map_len Length of data in @p channel_map + * @param[in] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Bits 37-39 are reserved for future use and must be set to 0. + * + * A channel is bad when its bit is 0. A channel is unknown when its bit is 1. + * At least two channels shall be marked as unknown. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_data_channel_classification(size_t channel_map_len, + const uint8_t* channel_map); + +/***************************************************************************//** + * + * Deprecated and replaced by functionality-specific settings provided by + * the bluetooth_feature_accept_list component. For advertising, use the command + * @ref sl_bt_advertiser_configure and @p flags bits @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to configure the + * advertising filter policy. For scanning, use the command @ref + * sl_bt_scanner_set_parameters_and_filter to control the scanning filter + * policy. + * + * Enable or disable accept list filtering. The setting will be effective the + * next time that scanning is enabled. Use command @ref + * sl_bt_sm_add_to_whitelist to add devices to the accept list. + * + * When the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) is used, bonded devices are + * added into the accept list automatically by the stack. Note that the + * Bluetooth stack uses the built-in bonding database by default. + * + * When the application specifically uses the external bonding database + * (bluetooth_feature_external_bonding_database), the application is fully + * responsible for managing the accept list using @ref sl_bt_sm_add_to_whitelist + * and @ref sl_bt_sm_delete_bondings commands. + * + * @param[in] enable 1 enable, 0 disable accept list filtering. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_gap_enable_whitelisting(uint8_t enable); + +/***************************************************************************//** + * + * Set the device's Bluetooth identity address to be used in advertising, + * scanning, connection initiation, and identity address exchange in bonding. + * The address is stored in RAM only and does not change the identity address in + * persistent storage. The address can be a public device address or static + * device address. It will be effective immediately in the next advertising, + * scanning, connection initiation, and bonding. Error + * SL_STATUS_INVALID_PARAMETER is returned if the address does not conform to + * the Bluetooth specification. + * + * Note that advertising sets that have own addresses set by @ref + * sl_bt_advertiser_set_random_address are not affected by this command, i.e., + * they will continue to use their own user defined addresses. + * + * @param[in] address The address in little endian format + * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. The address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gap_set_identity_address(bd_addr address, uint8_t addr_type); + +/** @} */ // end addtogroup sl_bt_gap + +/** + * @addtogroup sl_bt_advertiser Advertiser + * @{ + * + * @brief Advertiser + * + * This is the base class of legacy, extended, and periodic advertisings for + * common functionalities including advertising set management, TX power + * setting, advertising address, and so on. + * + * On an advertising set, either the legacy or extended advertising can be + * enabled at a time but they cannot be enabled simultaneously on the same + * advertising set. For example, the following sequence shows how to start the + * legacy advertising on an advertising set. Starting the extended advertising + * is similar. The only difference is to use the extended_advertiser API class. + * 1. Create an advertise set with the @ref sl_bt_advertiser_create_set + * command. + * 2. Configure and set advertising parameters for the advertising set as + * needed. + * 3. Set the advertising data with the @ref sl_bt_legacy_advertiser_set_data + * or @ref sl_bt_legacy_advertiser_generate_data command. + * 4. Start the legacy advertising with the @ref sl_bt_legacy_advertiser_start + * command. + * + * Periodic advertising can be enabled independently on the advertising set + * regardless of the state of the legacy or extended advertising. However, to + * ensure that scanners can find the periodic advertising information and + * establish a synchronization, the extended advertising must be enabled + * simultaneously with the periodic advertising. + * + * When the bluetooth_feature_legacy_advertiser, + * bluetooth_feature_extended_advertiser or + * bluetooth_feature_periodic_advertiser component is included by the + * application, commands that have been superseded by the new classes are no + * longer available for use in the advertiser class. Calling them will receive + * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: @ref + * sl_bt_advertiser_set_phy, @ref sl_bt_advertiser_set_configuration, @ref + * sl_bt_advertiser_clear_configuration, @ref sl_bt_advertiser_set_data, @ref + * sl_bt_advertiser_set_long_data, @ref sl_bt_advertiser_start, @ref + * sl_bt_advertiser_start_periodic_advertising, and @ref + * sl_bt_advertiser_stop_periodic_advertising. See the command descriptions for + * the replacements. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_advertiser_create_set_id 0x01040020 +#define sl_bt_cmd_advertiser_configure_id 0x12040020 +#define sl_bt_cmd_advertiser_set_timing_id 0x03040020 +#define sl_bt_cmd_advertiser_set_channel_map_id 0x04040020 +#define sl_bt_cmd_advertiser_set_tx_power_id 0x0b040020 +#define sl_bt_cmd_advertiser_set_report_scan_request_id 0x05040020 +#define sl_bt_cmd_advertiser_set_random_address_id 0x10040020 +#define sl_bt_cmd_advertiser_clear_random_address_id 0x11040020 +#define sl_bt_cmd_advertiser_stop_id 0x0a040020 +#define sl_bt_cmd_advertiser_delete_set_id 0x02040020 +#define sl_bt_cmd_advertiser_set_phy_id 0x06040020 +#define sl_bt_cmd_advertiser_set_configuration_id 0x07040020 +#define sl_bt_cmd_advertiser_clear_configuration_id 0x08040020 +#define sl_bt_cmd_advertiser_set_data_id 0x0f040020 +#define sl_bt_cmd_advertiser_set_long_data_id 0x0e040020 +#define sl_bt_cmd_advertiser_start_id 0x09040020 +#define sl_bt_cmd_advertiser_start_periodic_advertising_id 0x0c040020 +#define sl_bt_cmd_advertiser_stop_periodic_advertising_id 0x0d040020 +#define sl_bt_rsp_advertiser_create_set_id 0x01040020 +#define sl_bt_rsp_advertiser_configure_id 0x12040020 +#define sl_bt_rsp_advertiser_set_timing_id 0x03040020 +#define sl_bt_rsp_advertiser_set_channel_map_id 0x04040020 +#define sl_bt_rsp_advertiser_set_tx_power_id 0x0b040020 +#define sl_bt_rsp_advertiser_set_report_scan_request_id 0x05040020 +#define sl_bt_rsp_advertiser_set_random_address_id 0x10040020 +#define sl_bt_rsp_advertiser_clear_random_address_id 0x11040020 +#define sl_bt_rsp_advertiser_stop_id 0x0a040020 +#define sl_bt_rsp_advertiser_delete_set_id 0x02040020 +#define sl_bt_rsp_advertiser_set_phy_id 0x06040020 +#define sl_bt_rsp_advertiser_set_configuration_id 0x07040020 +#define sl_bt_rsp_advertiser_clear_configuration_id 0x08040020 +#define sl_bt_rsp_advertiser_set_data_id 0x0f040020 +#define sl_bt_rsp_advertiser_set_long_data_id 0x0e040020 +#define sl_bt_rsp_advertiser_start_id 0x09040020 +#define sl_bt_rsp_advertiser_start_periodic_advertising_id 0x0c040020 +#define sl_bt_rsp_advertiser_stop_periodic_advertising_id 0x0d040020 + +/** + * @brief These values define the available connection modes, which indicate + * whether the device accepts connection requests or scan requests. + */ +typedef enum +{ + sl_bt_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable + non-scannable */ + sl_bt_advertiser_connectable_scannable = 0x2, /**< (0x2) Undirected + connectable scannable. + This mode can only be + used in legacy + advertising PDUs. */ + sl_bt_advertiser_scannable_non_connectable = 0x3, /**< (0x3) Undirected + scannable + (Non-connectable but + responds to scan + requests) */ + sl_bt_advertiser_connectable_non_scannable = 0x4 /**< (0x4) Undirected + connectable + non-scannable. This + mode can only be used + in extended advertising + PDUs. */ +} sl_bt_advertiser_connection_mode_t; + +/** + * @brief These values define the available discovery modes, which dictate how + * the device is visible to other devices in the legacy and extended + * advertising. + */ +typedef enum +{ + sl_bt_advertiser_non_discoverable = 0x0, /**< (0x0) Not discoverable */ + sl_bt_advertiser_limited_discoverable = 0x1, /**< (0x1) Discoverable by both + limited and general + discovery procedures */ + sl_bt_advertiser_general_discoverable = 0x2, /**< (0x2) Discoverable by the + general discovery procedure */ + sl_bt_advertiser_broadcast = 0x3, /**< (0x3) Device is not + discoverable in either + limited or generic discovery + procedure but may be + discovered using the + Observation procedure. */ + sl_bt_advertiser_user_data = 0x4 /**< (0x4) Send advertising + and/or scan response data + defined by the user. The + discovery mode is defined by + the user. */ +} sl_bt_advertiser_discovery_mode_t; + +/** + * @brief Address type to use for the legacy and extended advertising + */ +typedef enum +{ + sl_bt_advertiser_identity_address = 0x0, /**< (0x0) Use public or static + device address, or an identity + address if privacy mode is + enabled. */ + sl_bt_advertiser_non_resolvable = 0x1 /**< (0x1) Use non-resolvable address + type; the advertising must be + non-connectable. */ +} sl_bt_advertiser_adv_address_type_t; + +/** + * @brief These values define the packet types in legacy and extended + * advertising. + */ +typedef enum +{ + sl_bt_advertiser_advertising_data_packet = 0x0, /**< (0x0) Advertising data + packet */ + sl_bt_advertiser_scan_response_packet = 0x1 /**< (0x1) Scan response + packet */ +} sl_bt_advertiser_packet_type_t; + +/** + * @addtogroup sl_bt_advertiser_flags Generic Advertising Configuration Flags + * @{ + * + * This enum defines configuration flags common for legacy and extended + * advertisings. + */ + +/** Use a non-resolvable private address managed by the stack. The advertising + * must be non-connectable when using this configuration. The stack generates a + * non-resolvable private address for the advertising set and the stack will + * update the address periodically in privacy mode. By default this flag is not + * set, i.e., the advertising address uses the device identity address. This + * configuration has no effect if the advertising address has been set with the + * @ref sl_bt_advertiser_set_random_address command. */ +#define SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS 0x4 + +/** Use the device identity address when privacy mode is enabled. By default, + * this flag is not set, i.e., the advertising address uses a resolvable private + * address managed by the stack in privacy mode. This configuration has no + * effect if the @ref SL_BT_ADVERTISER_USE_NONRESOLVABLE_ADDRESS flag is set or + * the advertising address has been set with the @ref + * sl_bt_advertiser_set_random_address command. */ +#define SL_BT_ADVERTISER_USE_DEVICE_IDENTITY_IN_PRIVACY 0x10 + +/** + * + * Use the Filter Accept List to filter scan requests received while performing + * scannable advertising with this advertising set. By default, this flag is not + * set and scan requests from all devices are processed. If the application sets + * this flag, scan requests are processed only from those devices that the + * application has added to the Filter Accept List. + * + * This configuration is supported only when the application has included the + * Bluetooth component bluetooth_feature_accept_list. + * + * */ +#define SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS 0x20 + +/** + * + * Use the Filter Accept List to filter connection requests received while + * performing connectable advertising with this advertising set. By default, + * this flag is not set and connection requests from all devices are processed. + * If the application sets this flag, connection requests are processed only + * from those devices that the application has added to the Filter Accept List. + * + * This configuration is supported only when the application has included the + * Bluetooth component bluetooth_feature_accept_list. + * + * */ +#define SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS 0x40 + +/** @} */ // end Generic Advertising Configuration Flags + +/** + * @addtogroup sl_bt_evt_advertiser_timeout sl_bt_evt_advertiser_timeout + * @{ + * @brief Indicates the legacy or extended advertising on an advertising set has + * stopped because the advertiser has completed the configured number of + * advertising events or the advertising has reached the configured duration + * + * The maximum number of advertising events or advertising duration can be + * configured by the @p maxevents or @p duration parameter in the command @ref + * sl_bt_advertiser_set_timing. + */ + +/** @brief Identifier of the timeout event */ +#define sl_bt_evt_advertiser_timeout_id 0x010400a0 + +/***************************************************************************//** + * @brief Data structure of the timeout event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_advertiser_timeout_s +{ + uint8_t handle; /**< The advertising set handle */ +}); + +typedef struct sl_bt_evt_advertiser_timeout_s sl_bt_evt_advertiser_timeout_t; + +/** @} */ // end addtogroup sl_bt_evt_advertiser_timeout + +/** + * @addtogroup sl_bt_evt_advertiser_scan_request sl_bt_evt_advertiser_scan_request + * @{ + * @brief Reports a scan request received during the legacy or extended + * advertising advertising if the scan request notification is enabled + * + * Do not confuse this event with the @ref sl_bt_evt_scanner_scan_report event. + */ + +/** @brief Identifier of the scan_request event */ +#define sl_bt_evt_advertiser_scan_request_id 0x020400a0 + +/***************************************************************************//** + * @brief Data structure of the scan_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_advertiser_scan_request_s +{ + uint8_t handle; /**< Advertising set handle where the scan request was + received */ + bd_addr address; /**< Bluetooth address of the scanner */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Scanner address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): Public + device address + - sl_bt_gap_static_address (0x1): Static + device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote scanning device has + previously bonded with the local device. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): No + bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_advertiser_scan_request_s sl_bt_evt_advertiser_scan_request_t; + +/** @} */ // end addtogroup sl_bt_evt_advertiser_scan_request + +/***************************************************************************//** + * + * Create an advertising set that can be used for legacy, extended, or periodic + * advertising. The handle of the created advertising set is returned in + * response if the operation succeeds. + * + * The maximum number of advertising sets for user advertisers is limited by the + * SL_BT_CONFIG_USER_ADVERTISERS configuration. + * + * @param[out] handle Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_create_set(uint8_t *handle); + +/***************************************************************************//** + * + * Configure the legacy and extended advertising on an advertising set. The + * configuration will take effect next time the legacy or extended advertising + * is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] flags @parblock + * Configuration flags. Value: 0 or bitmask of @ref sl_bt_advertiser_flags + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_configure(uint8_t advertising_set, uint32_t flags); + +/***************************************************************************//** + * + * Set the timing parameters for legacy or extended advertising on an + * advertising set. This setting will take effect next time the legacy or + * extended advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum advertising interval. Value in units of 0.625 ms + * - Range: 0x20 to 0xFFFFFF + * - Time range: 20 ms to 10485.759375 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum advertising interval. Value in units of 0.625 ms + * - Range: 0x20 to 0xFFFFFF + * - Time range: 20 ms to 10485.759375 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] duration @parblock + * Advertising duration for this advertising set. Value 0 indicates no + * advertising duration limit and advertising continues until it is disabled. + * A non-zero value sets the duration in units of 10 ms. The duration begins + * at the start of the first advertising event of this advertising set. + * - Range: 0x0001 to 0xFFFF + * - Time range: 10 ms to 655.35 s + * + * Default value: 0 + * @endparblock + * @param[in] maxevents @parblock + * If non-zero, indicates the maximum number of advertising events to send + * before the advertiser is stopped. Value 0 indicates no maximum number + * limit. + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_timing(uint8_t advertising_set, + uint32_t interval_min, + uint32_t interval_max, + uint16_t duration, + uint8_t maxevents); + +/***************************************************************************//** + * + * Set the primary advertising channel map on an advertising set. This setting + * will take effect next time when the legacy or extended advertising is + * enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] channel_map @parblock + * Advertising channel map which determines, which of the three channels will + * be used for advertising. This value is given as a bitmask. Values: + * - 1: Advertise on CH37 + * - 2: Advertise on CH38 + * - 3: Advertise on CH37 and CH38 + * - 4: Advertise on CH39 + * - 5: Advertise on CH37 and CH39 + * - 6: Advertise on CH38 and CH39 + * - 7: Advertise on all channels + * + * Recommended value: 7 + * + * Default value: 7 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_channel_map(uint8_t advertising_set, + uint8_t channel_map); + +/***************************************************************************//** + * + * Limit the maximum advertising TX power on an advertising set. If the value + * goes over the global value that was set using the @ref + * sl_bt_system_set_tx_power command, the global value will be the maximum + * limit. The maximum TX power of legacy advertising is further constrained to + * be less than +10 dBm. Extended advertising TX power can be +10 dBm and over + * if Adaptive Frequency Hopping is enabled. This setting has no effect on + * periodic advertising. + * + * This setting will take effect next time the legacy or extended advertising is + * enabled. + * + * By default, maximum advertising TX power is limited by the global value. + * + * @param[in] advertising_set Advertising set handle + * @param[in] power TX power in 0.1 dBm steps. For example, the value of 10 is 1 + * dBm and 55 is 5.5 dBm. + * @param[out] set_power The selected maximum advertising TX power + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_tx_power(uint8_t advertising_set, + int16_t power, + int16_t *set_power); + +/***************************************************************************//** + * + * Enable or disable the scan request notification on an advertising set. This + * setting will take effect next time the legacy or extended advertising is + * enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] report_scan_req @parblock + * If non-zero, enables scan request notification and scan requests will be + * reported as events. + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_scan_request - Triggered when a scan request is + * received during advertising if the scan request notification is enabled + * by this command. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_report_scan_request(uint8_t advertising_set, + uint8_t report_scan_req); + +/***************************************************************************//** + * + * Set the advertiser on an advertising set to use a random address. This + * overrides the default advertiser address, which is either the public device + * address programmed at production or the address written into persistent + * storage using @ref sl_bt_system_set_identity_address command. This setting is + * stored in RAM only and does not change the identity address in persistent + * storage. In privacy mode, the stack does not change an advertiser address set + * by this command. To ensure that the stack can manage the address update + * periodically in privacy mode, the address setting should be removed with the + * @ref sl_bt_advertiser_clear_random_address command. + * + * When setting a resolvable random address, the address parameter is ignored. + * The stack generates one and set it as the advertiser address. The generated + * address is returned in the response. To enhance the privacy, the application + * should schedule periodic address updates by calling this command + * periodically. Use different schedules for different advertising sets. + * + * To use the default advertiser address, remove this setting using @ref + * sl_bt_advertiser_clear_random_address command. + * + * Wrong state error is returned if advertising has been enabled on the + * advertising set. Invalid parameter error is returned if the advertising set + * handle is invalid or the address does not conform to the Bluetooth + * specification. + * + * @param[in] advertising_set Advertising set handle + * @param[in] addr_type Enum @ref sl_bt_gap_address_type_t. Address type. + * Values: + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address. This type can only be used for non-connectable + * advertising. + * @param[in] address The random address to set. Ignore this field when setting + * a resolvable random address. + * @param[out] address_out The resolvable random address set for the advertiser. + * Ignore this field when setting other types of random addresses. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_set_random_address(uint8_t advertising_set, + uint8_t addr_type, + bd_addr address, + bd_addr *address_out); + +/***************************************************************************//** + * + * Clear the random address previously set for the advertiser address on an + * advertising set. To set a random address, use @ref + * sl_bt_advertiser_set_random_address command. The default advertiser address + * will be used after this operation. + * + * The error SL_STATUS_INVALID_STATE is returned if advertising has been enabled + * on the advertising set. An invalid parameter error is returned if the + * advertising set handle is invalid. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_clear_random_address(uint8_t advertising_set); + +/***************************************************************************//** + * + * Stop the legacy or extended advertising on an advertising set. Counterpart + * with @ref sl_bt_legacy_advertiser_start or @ref + * sl_bt_extended_advertiser_start. + * + * This command does not affect the enable state of the periodic advertising on + * the advertising set, i.e., periodic advertising is not stopped. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_stop(uint8_t advertising_set); + +/***************************************************************************//** + * + * Delete an advertising set. Any enabled legacy, extended, or periodic + * advertising is stopped before the deletion. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_delete_set(uint8_t advertising_set); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_extended_advertiser_set_phy. + * + * Set the primary and secondary advertising PHYs used for extended and periodic + * advertising on an advertising set. This setting will take effect next time + * extended or periodic advertising is enabled. When advertising on the LE Coded + * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is + * returned if a PHY value is invalid or the device does not support a given + * PHY. + * + * @param[in] advertising_set Advertising set handle + * @param[in] primary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the primary advertising channel. If legacy advertising PDUs + * are used, 1M PHY must be used. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * @param[in] secondary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the secondary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_advertiser_configure command. + * + * Enable advertising configuration flags on an advertising set. The + * configuration change will take effect next time the legacy or extended + * advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] configurations @parblock + * Advertising configuration flags to enable. This value can be a bitmask of + * multiple flags. Flags: + * - 1 (Bit 0): Use legacy advertising PDUs. + * - 2 (Bit 1): Omit advertiser's address from all PDUs (anonymous + * advertising). This flag is effective only in extended advertising. + * - 4 (Bit 2): Use a non-resolvable private address. When this + * configuration is enabled, the advertising must use non-connectable + * mode. The stack generates a non-resolvable private address for the + * advertising set and the stack will update the address periodically when + * the privacy mode is enabled. This configuration is ignored if the + * advertiser address has been set with the @ref + * sl_bt_advertiser_set_random_address command. + * - 8 (Bit 3): Include TX power in advertising packets. This flag is + * effective only in extended advertising. + * - 16 (Bit 4): Use the device identity address when the privacy + * mode is enabled in the stack. This configuration is ignored if the + * configuration of using non-resolvable private address is enabled or the + * advertising address has been set with the @ref + * sl_bt_advertiser_set_random_address command. + * + * Default value: 1 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_configuration(uint8_t advertising_set, + uint32_t configurations); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_advertiser_configure command. + * + * Disable advertising configuration flags on an advertising set. The + * configuration change will take effect next time the legacy or extended + * advertising is enabled. + * + * @param[in] advertising_set Advertising set handle + * @param[in] configurations Advertising configuration flags to disable. This + * value can be a bitmask of multiple flags. See @ref + * sl_bt_advertiser_set_configuration for possible flags. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_clear_configuration(uint8_t advertising_set, + uint32_t configurations); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_legacy_advertiser_set_data for + * legacy advertising PDUs, @ref sl_bt_extended_advertiser_set_data for extended + * advertising PDUs, and @ref sl_bt_periodic_advertiser_set_data for periodic + * advertising PDUs. + * + * Set user-defined data in advertising packets, scan response packets, or + * periodic advertising packets. Maximum 31 bytes of data can be set for legacy + * advertising. Maximum 191 bytes of data can be set for connectable extended + * advertising. Maximum 253 bytes of data can be set for periodic and + * non-connectable extended advertising. For setting longer advertising data, + * use command @ref sl_bt_advertiser_set_long_data. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_advertiser_start. Periodic advertising mode can be enabled using + * command @ref sl_bt_advertiser_start_periodic_advertising. + * + * The invalid parameter error will be returned in the following situations: + * - Data length is more than 31 bytes but the advertiser can only advertise + * using legacy advertising PDUs. + * - Data is too long to fit into a single advertisement. + * - Set data of the advertising data packet when the scannable advertising is + * enabled using extended advertising PDUs. + * - Set data of the scan response data packet when the connectable + * advertising is enabled using extended advertising PDUs. + * + * Note that the user-defined data may be overwritten by the system when the + * advertising is later enabled in a discovery mode other than user_data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] packet_type This value selects whether data is intended for + * advertising packets, scan response packets, or periodic advertising + * packets. + * - 0: Advertising packets + * - 1: Scan response packets + * - 8: Periodic advertising packets + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_data(uint8_t advertising_set, + uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_extended_advertiser_set_long_data for extended advertising PDUs and + * @ref sl_bt_periodic_advertiser_set_long_data for periodic advertising PDUs. + * + * Set advertising data for a specified packet type and advertising set. Data + * currently in the system data buffer will be extracted as the advertising + * data. The buffer will be emptied after this command regardless of the + * completion status. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. + * + * Maximum 31 bytes of data can be set for legacy advertising. Maximum 191 bytes + * of data can be set for connectable extended advertising. Maximum 1650 bytes + * of data can be set for periodic and non-connectable extended advertising, but + * advertising parameters may limit the amount of data that can be sent in a + * single advertisement. + * + * See @ref sl_bt_advertiser_set_data for more details on advertising data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] packet_type This value selects whether data is intended for + * advertising packets, scan response packets, or periodic advertising + * packets. Values: + * - 0: Advertising packets + * - 1: Scan response packets + * - 8: Periodic advertising packets + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_set_long_data(uint8_t advertising_set, + uint8_t packet_type); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_legacy_advertiser_start and @ref + * sl_bt_extended_advertiser_start commands. + * + * Start the legacy or extended advertising on an advertising set with specified + * discovery and connection modes. + * + * The number of concurrent connectable advertisings is limited by the number of + * connections reserved by the user application (the + * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other + * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This + * command fails with the connection limit exceeded error if it may cause the + * number of connections exceeding the configured value in future. For example, + * only one connectable advertising can be enabled if the device has + * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. + * This limitation does not apply to non-connectable advertising. + * + * The default advertising configuration in the stack is set to using legacy + * advertising PDUs on 1M PHY. The stack will automatically select extended + * advertising PDUs if either of the following has occurred with the default + * configuration: + * 1. The connection mode is set to @ref + * sl_bt_advertiser_connectable_non_scannable. + * 2. The primary advertising PHY is set to Coded PHY by @ref + * sl_bt_extended_advertiser_set_phy. + * 3. The user advertising data length is more than 31 bytes. + * 4. Periodic advertising is enabled. + * + * This command fails with the invalid parameter error if one of the following + * cases occurs: + * 1. Non-resolvable random address is used but the connection mode is + * advertiser_connectable_scannable or + * advertiser_connectable_non_scannable. + * 2. advertiser_connectable_non_scannable is the connection mode but using + * legacy advertising PDUs has been explicitly enabled with command @ref + * sl_bt_advertiser_set_configuration. + * 3. Coded PHY is the primary advertising PHY but using legacy advertising + * PDUs has been explicitly enabled with command @ref + * sl_bt_advertiser_set_configuration. + * 4. advertiser_connectable_scannable is the connection mode but using + * extended advertising PDUs has been explicitly enabled or the primary + * advertising PHY is set to Coded PHY. + * + * If advertising is enabled in user_data mode, use @ref + * sl_bt_advertiser_set_data to set advertising and scan response data before + * issuing this command. When advertising is enabled in modes other than + * user_data, advertising and scan response data is generated by the stack using + * the following procedure: + * 1. Add a flags field to advertising data. + * 2. Add a TX power level field to advertising data if the TX power service + * exists in the local GATT database. + * 3. Add a peripheral connection interval range field to advertising data if + * the GAP peripheral preferred connection parameters characteristic exists + * in the local GATT database. + * 4. Add a list of 16-bit service UUIDs to advertising data if there are one + * or more 16-bit service UUIDs to advertise. The list is complete if all + * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is + * incomplete. + * 5. Add a list of 128-bit service UUIDs to advertising data if there are one + * or more 128-bit service UUIDs to advertise and there is still free space + * for this field. The list is complete if all advertised 128-bit UUIDs are + * in advertising data. Otherwise, the list is incomplete. Note that an + * advertising data packet can contain at most one 128-bit service UUID. + * 6. Try to add the full local name to advertising data if the device is not + * in privacy mode. If the full local name does not fit into the remaining + * free space, the advertised name is a shortened version by cutting off + * the end if the free space has at least 6 bytes. Otherwise, the local + * name is added to scan response data. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. Discovery + * mode. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * - sl_bt_advertiser_broadcast (0x3): Device is not discoverable in + * either limited or generic discovery procedure but may be discovered + * using the Observation procedure. + * - sl_bt_advertiser_user_data (0x4): Send advertising and/or scan + * response data defined by the user. The discovery mode is defined by the + * user. + * @param[in] connect Enum @ref sl_bt_advertiser_connection_mode_t. Connection + * mode. Values: + * - sl_bt_advertiser_non_connectable (0x0): Non-connectable + * non-scannable + * - sl_bt_advertiser_connectable_scannable (0x2): Undirected + * connectable scannable. This mode can only be used in legacy advertising + * PDUs. + * - sl_bt_advertiser_scannable_non_connectable (0x3): Undirected + * scannable (Non-connectable but responds to scan requests) + * - sl_bt_advertiser_connectable_non_scannable (0x4): Undirected + * connectable non-scannable. This mode can only be used in extended + * advertising PDUs. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and advertising has stopped on an advertising set. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start(uint8_t advertising_set, + uint8_t discover, + uint8_t connect); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_periodic_advertiser_start + * command. + * + * Start periodic advertising on an advertising set. The stack enables the + * advertising set automatically if the set was not enabled and the set can + * advertise using extended advertising PDUs beside the syncInfo, which is + * needed for the periodic advertising. + * + * The invalid parameter error is returned if the application has configured + * legacy advertising PDUs or anonymous advertising, or the advertising set is + * enabled using legacy advertising PDUs. + * + * To stop periodic advertising, use @ref + * sl_bt_advertiser_stop_periodic_advertising command with the handle received + * in response from this command. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Periodic advertising configurations. Bitmask of the + * following: + * - Bit 0: Include TX power in advertising PDU + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_start_periodic_advertising(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_periodic_advertiser_stop + * command. + * + * Stop periodic advertising on an advertising set. Counterpart with @ref + * sl_bt_advertiser_start_periodic_advertising. + * + * This command does not affect the enable state of the advertising set, i.e., + * legacy or extended advertising is not stopped. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_advertiser_stop_periodic_advertising(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_advertiser + +/** + * @addtogroup sl_bt_legacy_advertiser Legacy Advertiser + * @{ + * + * @brief Legacy Advertiser + * + * The commands and events in this class are related to legacy advertising + * functionalities. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_legacy_advertiser_set_data_id 0x00560020 +#define sl_bt_cmd_legacy_advertiser_generate_data_id 0x01560020 +#define sl_bt_cmd_legacy_advertiser_start_id 0x02560020 +#define sl_bt_cmd_legacy_advertiser_start_directed_id 0x03560020 +#define sl_bt_rsp_legacy_advertiser_set_data_id 0x00560020 +#define sl_bt_rsp_legacy_advertiser_generate_data_id 0x01560020 +#define sl_bt_rsp_legacy_advertiser_start_id 0x02560020 +#define sl_bt_rsp_legacy_advertiser_start_directed_id 0x03560020 + +/** + * @brief These values define the available connection modes of undirected + * legacy advertising. + */ +typedef enum +{ + sl_bt_legacy_advertiser_non_connectable = 0x0, /**< (0x0) Undirected + non-connectable and + non-scannable legacy + advertising */ + sl_bt_legacy_advertiser_connectable = 0x2, /**< (0x2) Undirected + connectable and scannable + legacy advertising */ + sl_bt_legacy_advertiser_scannable = 0x3 /**< (0x3) Undirected scannable + and non-connectable legacy + advertising */ +} sl_bt_legacy_advertiser_connection_mode_t; + +/** + * @brief These values define the available connection modes of directed legacy + * advertising. + */ +typedef enum +{ + sl_bt_legacy_advertiser_high_duty_directed_connectable = 0x1, /**< (0x1) High + duty cycle + directed + connectable + legacy + advertising */ + sl_bt_legacy_advertiser_low_duty_directed_connectable = 0x5 /**< (0x5) Low + duty cycle + directed + connectable + legacy + advertising */ +} sl_bt_legacy_advertiser_directed_connection_mode_t; + +/***************************************************************************//** + * + * Set user-defined advertising data packet or scan response packet on an + * advertising set. This overwrites the existing advertising data packet and + * scan response packet on this advertising set regardless of whether the data + * was set for the legacy or extended advertising. Maximum 31 bytes of data can + * be set with this command. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_legacy_advertiser_start. + * + * @param[in] advertising_set Advertising set handle + * @param[in] type Enum @ref sl_bt_advertiser_packet_type_t. The advertising + * packet type + * @param[in] data_len Length of data in @p data + * @param[in] data Data to set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_set_data(uint8_t advertising_set, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Ask the stack to generate the advertising data packet and scan response + * packet on an advertising set. Alternatively, the user-defined advertising + * data can be set using the @ref sl_bt_legacy_advertiser_set_data command. + * + * This overwrites the existing advertising data packet and scan response packet + * on this advertising set regardless of whether the data was set for the legacy + * or extended advertising. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. To enable advertising mode, use command @ref + * sl_bt_legacy_advertiser_start. + * + * The stack generates the advertising data and scan response packet using the + * following logic. + * 1. Add a flags field to advertising data. + * 2. Add a TX power level field to advertising data if the TX power service + * exists in the local GATT database. + * 3. Add a peripheral connection interval range field to advertising data if + * the GAP peripheral preferred connection parameters characteristic exists + * in the local GATT database. + * 4. Add a list of 16-bit service UUIDs to advertising data if there are one + * or more 16-bit service UUIDs to advertise. The list is complete if all + * advertised 16-bit UUIDs are in advertising data. Otherwise, the list is + * incomplete. + * 5. Add a list of 128-bit service UUIDs to advertising data if there are one + * or more 128-bit service UUIDs to advertise and there is still free space + * for this field. The list is complete if all advertised 128-bit UUIDs are + * in advertising data. Otherwise, the list is incomplete. Note that an + * advertising data packet can contain at most one 128-bit service UUID. + * 6. Try to add the full local name to advertising data if the device is not + * in privacy mode. If the full local name does not fit into the remaining + * free space, the advertised name is a shortened version by cutting off + * the end if the free space has at least 6 bytes. Otherwise, the local + * name is added to scan response data. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The + * discovery mode for the Flags data field in the packet. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover); + +/***************************************************************************//** + * + * Start undirected legacy advertising on an advertising set with the specified + * connection mode. Use @ref sl_bt_advertiser_stop to stop the advertising. + * + * Use the @ref sl_bt_legacy_advertiser_set_data or @ref + * sl_bt_legacy_advertiser_generate_data command to set the advertising data + * before calling this command. The advertising data is added into the + * advertising data packet and scan response packet if the connection mode is + * connectable and/or scannable. The data is only added into the advertising + * data packet when the connection mode is non-connectable and non-scannable. + * + * The number of concurrent connectable advertisings is limited by the number of + * connections reserved by the user application (the + * SL_BT_CONFIG_MAX_CONNECTIONS configuration) and the number reserved by other + * software components (the SL_BT_COMPONENT_CONNECTIONS configuration). This + * command fails with the connection limit exceeded error if it may cause the + * number of connections exceeding the configured value in future. For example, + * only one connectable advertising can be enabled if the device has + * (SL_BT_CONFIG_MAX_CONNECTIONS + SL_BT_COMPONENT_CONNECTIONS - 1) connections. + * This limitation does not apply to non-connectable advertising. + * + * This command fails with the invalid parameter error if non-resolvable random + * address is used but the connection mode is @ref + * sl_bt_legacy_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_legacy_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_legacy_advertiser_non_connectable (0x0): Undirected + * non-connectable and non-scannable legacy advertising + * - sl_bt_legacy_advertiser_connectable (0x2): Undirected + * connectable and scannable legacy advertising + * - sl_bt_legacy_advertiser_scannable (0x3): Undirected scannable + * and non-connectable legacy advertising + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_start(uint8_t advertising_set, + uint8_t connect); + +/***************************************************************************//** + * + * Start directed legacy advertising on an advertising set with the specified + * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to + * stop the advertising. + * + * Directed legacy advertising does not allow any advertising data. When the + * connection mode is @ref + * sl_bt_legacy_advertiser_high_duty_directed_connectable, the stack defaults + * the advertising duration to 0.64 s if the application has not set the + * parameter. The duration is reduced to 1.28 s if the application has set a + * larger duration value. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if non-resolvable random + * address is set as the advertising address. + * + * Event @ref sl_bt_evt_connection_opened will be received when the target + * device opens a connection to the advertiser on this advertising set. As a + * result, the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising + * stops and no Bluetooth connection is opened to it. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref + * sl_bt_legacy_advertiser_directed_connection_mode_t. Connection mode. + * Values: + * - sl_bt_legacy_advertiser_high_duty_directed_connectable (0x1): + * High duty cycle directed connectable legacy advertising + * - sl_bt_legacy_advertiser_low_duty_directed_connectable (0x5): Low + * duty cycle directed connectable legacy advertising + * @param[in] peer_addr Address of the peer target device the advertising is + * directed to + * @param[in] peer_addr_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Peer target device address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_legacy_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + bd_addr peer_addr, + uint8_t peer_addr_type); + +/** @} */ // end addtogroup sl_bt_legacy_advertiser + +/** + * @addtogroup sl_bt_extended_advertiser Extended Advertiser + * @{ + * + * @brief Extended Advertiser + * + * The commands and events in this class are related to extended advertising + * functionalities in GAP peripheral and broadcaster roles. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_extended_advertiser_set_phy_id 0x00570020 +#define sl_bt_cmd_extended_advertiser_set_data_id 0x01570020 +#define sl_bt_cmd_extended_advertiser_set_long_data_id 0x02570020 +#define sl_bt_cmd_extended_advertiser_generate_data_id 0x03570020 +#define sl_bt_cmd_extended_advertiser_start_id 0x04570020 +#define sl_bt_cmd_extended_advertiser_start_directed_id 0x05570020 +#define sl_bt_rsp_extended_advertiser_set_phy_id 0x00570020 +#define sl_bt_rsp_extended_advertiser_set_data_id 0x01570020 +#define sl_bt_rsp_extended_advertiser_set_long_data_id 0x02570020 +#define sl_bt_rsp_extended_advertiser_generate_data_id 0x03570020 +#define sl_bt_rsp_extended_advertiser_start_id 0x04570020 +#define sl_bt_rsp_extended_advertiser_start_directed_id 0x05570020 + +/** + * @brief These values define the available connection modes in extended + * advertising. + */ +typedef enum +{ + sl_bt_extended_advertiser_non_connectable = 0x0, /**< (0x0) Non-connectable + and non-scannable + extended advertising */ + sl_bt_extended_advertiser_scannable = 0x3, /**< (0x3) Scannable extended + advertising */ + sl_bt_extended_advertiser_connectable = 0x4 /**< (0x4) Connectable + extended advertising */ +} sl_bt_extended_advertiser_connection_mode_t; + +/** + * @addtogroup sl_bt_extended_advertiser_flags Extended Advertising Configuration Flags + * @{ + * + * This enum defines configuration flags for the extended advertising. + */ + +/** Omit advertiser's address from all PDUs (anonymous advertising). The + * advertising cannot be connectable or scannable if this flag is set. */ +#define SL_BT_EXTENDED_ADVERTISER_ANONYMOUS_ADVERTISING 0x1 + +/** Include the TX power in advertising packets. */ +#define SL_BT_EXTENDED_ADVERTISER_INCLUDE_TX_POWER 0x2 + +/** @} */ // end Extended Advertising Configuration Flags + +/***************************************************************************//** + * + * Set the primary and secondary advertising PHYs used for extended and periodic + * advertising on an advertising set. This setting will take effect next time + * extended or periodic advertising is enabled. When advertising on the LE Coded + * PHY, coding scheme S=8 is used. The SL_STATUS_INVALID_PARAMETER error is + * returned if a PHY value is invalid or the device does not support a given + * PHY. + * + * @param[in] advertising_set Advertising set handle + * @param[in] primary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the primary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * @param[in] secondary_phy @parblock + * Enum @ref sl_bt_gap_phy_t. The PHY on which the advertising packets are + * transmitted on the secondary advertising channel. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) + * + * Default value: @ref sl_bt_gap_phy_1m + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_phy(uint8_t advertising_set, + uint8_t primary_phy, + uint8_t secondary_phy); + +/***************************************************************************//** + * + * Set user-defined data for extended advertising. This overwrites the existing + * advertising data packet and scan response packet on this advertising set + * regardless of whether the data was set for the legacy or extended + * advertising. Maximum 191 bytes of data can be set for connectable extended + * advertising. Maximum 253 bytes of data can be set for non-connectable + * extended advertising. For setting longer advertising data, use command @ref + * sl_bt_extended_advertiser_set_long_data. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. Advertising mode can be enabled using command @ref + * sl_bt_extended_advertiser_start. + * + * The invalid parameter error is returned if the data is too long to fit into a + * single advertisement. + * + * @param[in] advertising_set Advertising set handle + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set long user-defined data for extended advertising. This overwrites the + * existing advertising data packet and scan response packet on this advertising + * set regardless of whether the data was set for the legacy or extended + * advertising. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. When this command is called, + * the data in the system data buffer is extracted as the advertising data. The + * buffer will be emptied after this command regardless of the completion + * status. + * + * Maximum 191 bytes of data can be set for connectable extended advertising. + * Maximum 1650 bytes of data can be set for non-connectable extended + * advertising. Advertising parameters may limit the amount of data that can be + * sent in a single advertisement. See @ref sl_bt_extended_advertiser_set_data + * for more details. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_set_long_data(uint8_t advertising_set); + +/***************************************************************************//** + * + * Ask the stack to generate the extended advertising data on an advertising + * set. Alternatively, user-defined advertising data can be set using the @ref + * sl_bt_extended_advertiser_set_data command. + * + * This overwrites the existing advertising data packet and scan response packet + * on this advertising set regardless of whether the data was set for the legacy + * or extended advertising. + * + * If advertising mode is currently enabled, the new advertising data will be + * used immediately. To enable advertising mode, use command @ref + * sl_bt_extended_advertiser_start. + * + * See @ref sl_bt_legacy_advertiser_generate_data for the advertising data + * generation logic. + * + * @param[in] advertising_set Advertising set handle + * @param[in] discover Enum @ref sl_bt_advertiser_discovery_mode_t. The + * discovery mode for the Flags data field in the packet. Values: + * - sl_bt_advertiser_non_discoverable (0x0): Not discoverable + * - sl_bt_advertiser_limited_discoverable (0x1): Discoverable by + * both limited and general discovery procedures + * - sl_bt_advertiser_general_discoverable (0x2): Discoverable by the + * general discovery procedure + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_generate_data(uint8_t advertising_set, + uint8_t discover); + +/***************************************************************************//** + * + * Start undirected extended advertising on an advertising set with the + * specified connection mode. Use @ref sl_bt_advertiser_stop to stop the + * advertising. + * + * Use the @ref sl_bt_extended_advertiser_set_data or @ref + * sl_bt_extended_advertiser_generate_data command to set the advertising data + * before calling this command. Advertising data is added into the scan response + * packet if the connection mode is scannable. Otherwise, data is in the + * advertising data packet. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if the advertising uses a + * non-resolvable random address but the connection mode is @ref + * sl_bt_extended_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when a remote device + * opens a connection to the advertiser on this advertising set. As a result, + * the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is done + * and the advertising has stopped. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable + * and non-scannable extended advertising + * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended + * advertising + * - sl_bt_extended_advertiser_connectable (0x4): Connectable + * extended advertising + * @param[in] flags Additional extended advertising options. Value: 0 or bitmask + * of @ref sl_bt_extended_advertiser_flags + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and advertising has stopped on an advertising set. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_start(uint8_t advertising_set, + uint8_t connect, + uint32_t flags); + +/***************************************************************************//** + * + * Start directed extended advertising on an advertising set with the specified + * peer target device and connection mode. Use @ref sl_bt_advertiser_stop to + * stop the advertising. + * + * The number of concurrent connectable advertisings is limited by the + * connection number configuration. See @ref sl_bt_legacy_advertiser_start for + * more details. + * + * This command fails with the invalid parameter error if the advertising uses a + * non-resolvable random address but the connection mode is @ref + * sl_bt_extended_advertiser_connectable. + * + * Event @ref sl_bt_evt_connection_opened will be received when the target + * device opens a connection to the advertiser on this advertising set. As a + * result, the advertising stops. + * + * Event @ref sl_bt_evt_advertiser_timeout will be received when the advertising + * stops and no Bluetooth connection is opened to it. + * + * @param[in] advertising_set Advertising set handle + * @param[in] connect Enum @ref sl_bt_extended_advertiser_connection_mode_t. + * Connection mode. Values: + * - sl_bt_extended_advertiser_non_connectable (0x0): Non-connectable + * and non-scannable extended advertising + * - sl_bt_extended_advertiser_scannable (0x3): Scannable extended + * advertising + * - sl_bt_extended_advertiser_connectable (0x4): Connectable + * extended advertising + * @param[in] flags Additional extended advertising options. Value: 0 or bitmask + * of @ref sl_bt_extended_advertiser_flags + * @param[in] peer_addr Address of the peer target device the advertising is + * directed to + * @param[in] peer_addr_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Peer target device address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p + * peer_addr_type uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_advertiser_timeout - Triggered when the number of + * advertising events set by @ref sl_bt_advertiser_set_timing command is + * done and the advertising has stopped. + * - @ref sl_bt_evt_connection_opened - Triggered when a remote device opens a + * connection to the advertiser and the advertising has stopped. + * + ******************************************************************************/ +sl_status_t sl_bt_extended_advertiser_start_directed(uint8_t advertising_set, + uint8_t connect, + uint32_t flags, + bd_addr peer_addr, + uint8_t peer_addr_type); + +/** @} */ // end addtogroup sl_bt_extended_advertiser + +/** + * @addtogroup sl_bt_periodic_advertiser Periodic Advertiser + * @{ + * + * @brief Periodic Advertiser + * + * Provides support for advertising with periodic advertising trains that do not + * have subevents or response slots. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_periodic_advertiser_set_data_id 0x00580020 +#define sl_bt_cmd_periodic_advertiser_set_long_data_id 0x01580020 +#define sl_bt_cmd_periodic_advertiser_start_id 0x02580020 +#define sl_bt_cmd_periodic_advertiser_stop_id 0x03580020 +#define sl_bt_rsp_periodic_advertiser_set_data_id 0x00580020 +#define sl_bt_rsp_periodic_advertiser_set_long_data_id 0x01580020 +#define sl_bt_rsp_periodic_advertiser_start_id 0x02580020 +#define sl_bt_rsp_periodic_advertiser_stop_id 0x03580020 + +/** + * @addtogroup sl_bt_periodic_advertiser_flags Periodic Advertising Configuration Flags + * @{ + * + * Defines configuration flags for periodic advertising. + */ + +/** Include the TX power in advertising packets. */ +#define SL_BT_PERIODIC_ADVERTISER_INCLUDE_TX_POWER 0x1 + +/** Automatically start the extended advertising on the advertising set. The + * advertising will be started in non-connectable and non-scannable mode. */ +#define SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING 0x2 + +/** @} */ // end Periodic Advertising Configuration Flags + +/** + * @cond RESTRICTED + * + * @addtogroup sl_bt_evt_periodic_advertiser_status sl_bt_evt_periodic_advertiser_status + * @{ + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * @brief This event indicates a status update in the periodic advertising. + */ + +/** @brief Identifier of the status event */ +#define sl_bt_evt_periodic_advertiser_status_id 0x005800a0 + +/***************************************************************************//** + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * @brief Data structure of the status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_advertiser_status_s +{ + uint8_t advertising_set; /**< The advertising set handle */ + uint32_t status; /**< Reserved for future */ +}); + +typedef struct sl_bt_evt_periodic_advertiser_status_s sl_bt_evt_periodic_advertiser_status_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_advertiser_status +/** @endcond */ // end restricted event + +/***************************************************************************//** + * + * Set the data for periodic advertising on an advertising set. Maximum 254 + * bytes of data can be set with this command. For setting longer advertising + * data, use command @ref sl_bt_periodic_advertiser_set_long_data. + * + * If the periodic advertising is currently enabled, the new advertising data + * will be used immediately. Periodic advertising can be enabled using the + * command @ref sl_bt_periodic_advertiser_start. + * + * The invalid parameter error will be returned if the data is too long to fit + * into the advertisement. + * + * @param[in] advertising_set Advertising set handle + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_set_data(uint8_t advertising_set, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Set data for periodic advertising on an advertising set. Data currently in + * the system data buffer will be extracted as the advertising data. The buffer + * will be emptied after this command regardless of the completion status. + * + * Prior to calling this command, add data to the buffer with one or multiple + * calls to @ref sl_bt_system_data_buffer_write. + * + * Maximum 1650 bytes of data can be set for periodic advertising. Advertising + * parameters may limit the amount of data that can be sent. + * + * See @ref sl_bt_periodic_advertiser_set_data for more details. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_set_long_data(uint8_t advertising_set); + +/***************************************************************************//** + * + * Start periodic advertising on an advertising set. + * + * According to the Bluetooth Core specification, periodic advertising PDUs + * cannot be transmitted until at least one extended advertising event has been + * completed. If the application needs exact control over the extended + * advertising data and parameters, use the @ref sl_bt_advertiser class to + * configure the parameters of the advertising set and the @ref + * sl_bt_extended_advertiser class to set or generate the desired extended + * advertising data payload. If the application does not configure the + * parameters or set the data, the default parameters and empty advertising data + * are used for the extended advertising. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p + * flags, the stack will automatically start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. The application may stop the automatically started extended + * advertising using the @ref sl_bt_advertiser_stop command. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in + * @p flags, the stack will momentarily start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. Unless the application starts extended advertising before + * the first extended advertising event has completed, the stack will + * automatically stop the momentary extended advertising after the first + * extended advertising event. + * + * Periodic advertising PDUs are transmitted on the secondary PHY configured for + * the advertising set with the @ref sl_bt_extended_advertiser_set_phy command. + * + * Use @ref sl_bt_periodic_advertiser_stop command to stop the periodic + * advertising. + * + * @param[in] advertising_set Advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask + * of @ref sl_bt_periodic_advertiser_flags + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags); + +/***************************************************************************//** + * + * Stop the periodic advertising on an advertising set. Counterpart to @ref + * sl_bt_periodic_advertiser_start. + * + * This command does not affect the enable state of the legacy or extended + * advertising on the advertising set, i.e., the legacy or extended advertising + * is not stopped.. + * + * @param[in] advertising_set Advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_periodic_advertiser_stop(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_periodic_advertiser + +/** + * @addtogroup sl_bt_scanner Scanner + * @{ + * + * @brief Scanner + * + * This is the scanning feature that is brought in when the application includes + * a software component for the scanning functionality. The functionality + * differences are listed below for various component inclusion scenario: + * - The bluetooth_feature_scanner component is included but neither + * bluetooth_feature_legacy_scanner nor bluetooth_feature_extended_scanner + * is included: + * - The scanner can scan advertising devices that use legacy or extended + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_scan_report event is used to report the + * received advertisements. + * + * - The bluetooth_feature_legacy_scanner component is included but the + * bluetooth_feature_extended_scanner is not: + * - The scanner can only scan advertising devices that use legacy + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used + * to report the received advertisements. + * + * - The bluetooth_feature_extended_scanner component is included: + * - The scanner can scan advertising devices that use legacy or extended + * advertising PDUs. + * - The @ref sl_bt_evt_scanner_legacy_advertisement_report event is used + * to report the received advertisements that use legacy advertising + * PDUs, and the @ref sl_bt_evt_scanner_extended_advertisement_report + * event is used to report the received advertisements that use extended + * advertising PDUs. + * + * - Either the bluetooth_feature_legacy_scanner or + * bluetooth_feature_extended_scanner component is included: + * - The @ref sl_bt_scanner_set_timing and @ref sl_bt_scanner_set_mode + * commands are not available to use. They are superseded by the @ref + * sl_bt_scanner_set_parameters command. + * - Calling a superseded command receives SL_STATUS_NOT_SUPPORTED error + * code. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_scanner_set_parameters_id 0x06050020 +#define sl_bt_cmd_scanner_set_parameters_and_filter_id 0x07050020 +#define sl_bt_cmd_scanner_stop_id 0x05050020 +#define sl_bt_cmd_scanner_set_timing_id 0x01050020 +#define sl_bt_cmd_scanner_set_mode_id 0x02050020 +#define sl_bt_cmd_scanner_start_id 0x03050020 +#define sl_bt_rsp_scanner_set_parameters_id 0x06050020 +#define sl_bt_rsp_scanner_set_parameters_and_filter_id 0x07050020 +#define sl_bt_rsp_scanner_stop_id 0x05050020 +#define sl_bt_rsp_scanner_set_timing_id 0x01050020 +#define sl_bt_rsp_scanner_set_mode_id 0x02050020 +#define sl_bt_rsp_scanner_start_id 0x03050020 + +/** + * @brief These values indicate which Bluetooth discovery mode to use when + * scanning for advertising devices. + */ +typedef enum +{ + sl_bt_scanner_discover_limited = 0x0, /**< (0x0) Discover only limited + discoverable devices. */ + sl_bt_scanner_discover_generic = 0x1, /**< (0x1) Discover limited and + general discoverable devices. */ + sl_bt_scanner_discover_observation = 0x2 /**< (0x2) Discover + non-discoverable, limited and + general discoverable devices. */ +} sl_bt_scanner_discover_mode_t; + +/** + * @brief The scanning modes. + */ +typedef enum +{ + sl_bt_scanner_scan_mode_passive = 0x0, /**< (0x0) Passive scanning mode where + the device only listens to + advertising packets and does not + transmit packets */ + sl_bt_scanner_scan_mode_active = 0x1 /**< (0x1) Active scanning mode where + the device sends out a scan + request packet upon receiving a + scannable advertising packet from + a remote device and listens to the + scan response packet from the + remote device */ +} sl_bt_scanner_scan_mode_t; + +/** + * @brief The enum defines the scanning PHYs. + */ +typedef enum +{ + sl_bt_scanner_scan_phy_1m = 0x1, /**< (0x1) Initiate the scanning on + the 1M PHY */ + sl_bt_scanner_scan_phy_coded = 0x4, /**< (0x4) Initiate the scanning on + the Coded PHY */ + sl_bt_scanner_scan_phy_1m_and_coded = 0x5 /**< (0x5) Simultaneous scanning by + initiating the scanning on the + 1M and Coded PHY alternatively */ +} sl_bt_scanner_scan_phy_t; + +/** + * @brief Defines the data completeness status types of an advertisement + * reported by the scanner. + */ +typedef enum +{ + sl_bt_scanner_data_status_complete = 0x0, /**< (0x0) All data of the + advertisement has been + reported. */ + sl_bt_scanner_data_status_incomplete_more = 0x1, /**< (0x1) Data of the + advertisement is + incomplete in this + event, and more data + will come in new + events. */ + sl_bt_scanner_data_status_incomplete_nomore = 0x2 /**< (0x2) Data of the + advertisement is + incomplete in this + event, but no more + data will come, i.e., + the data of the + advertisement is + truncated. */ +} sl_bt_scanner_data_status_t; + +/** + * @brief The scanning filter policy setting determines which advertisements and + * scan responses are delivered to the application when scanning. See the + * Bluetooth Core specification Volume 6, Part B, Section 4.3.3 "Scanning filter + * policy" for a detailed description of this setting. + * + * Note that some filter policies require the application to include additional + * Bluetooth feature components. Filter policies that use the Filter Accept List + * require that the application has included the bluetooth_feature_accept_list + * component. Filter policies that require the Bluetooth controller to resolve a + * Resolvable Private Address require that the application has included the + * bluetooth_feature_resolving_list component. + */ +typedef enum +{ + sl_bt_scanner_filter_policy_basic_unfiltered = 0x0, /**< (0x0) Advertising + and scan response + PDUs are processed + from all devices. + For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + a Resolvable + Private Address + that is resolved + to the local + device by the + Bluetooth + controller. */ + sl_bt_scanner_filter_policy_basic_filtered = 0x1, /**< (0x1) Advertising + and scan response + PDUs are processed + only from devices + that the + application has + added to the + Filter Accept + List. For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + a Resolvable + Private Address + that is resolved + to the local + device by the + Bluetooth + controller. */ + sl_bt_scanner_filter_policy_extended_unfiltered = 0x2, /**< (0x2) Advertising + and scan response + PDUs are processed + from all devices. + For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + any Resolvable + Private Address. */ + sl_bt_scanner_filter_policy_extended_filtered = 0x3 /**< (0x3) Advertising + and scan response + PDUs are processed + only from devices + that the + application has + added to the + Filter Accept + List. For directed + advertising, the + target address + must additionally + match the identity + address of the + local device or be + any Resolvable + Private Address. */ +} sl_bt_scanner_filter_policy_t; + +/** + * @addtogroup sl_bt_scanner_event_flag Event Type Flags of Advertisement Reports + * @{ + * + * Defines the event type flags of the advertisement packets the scanner + * reports. An advertisement packet could have multiple applicable flags. + */ + +/** A connectable advertising data packet */ +#define SL_BT_SCANNER_EVENT_FLAG_CONNECTABLE 0x1 + +/** A scannable advertising data packet */ +#define SL_BT_SCANNER_EVENT_FLAG_SCANNABLE 0x2 + +/** Directed advertising */ +#define SL_BT_SCANNER_EVENT_FLAG_DIRECTED 0x4 + +/** A scan response packet that can be received in active scan mode only */ +#define SL_BT_SCANNER_EVENT_FLAG_SCAN_RESPONSE 0x8 + +/** @} */ // end Event Type Flags of Advertisement Reports + +/** + * @addtogroup sl_bt_evt_scanner_legacy_advertisement_report sl_bt_evt_scanner_legacy_advertisement_report + * @{ + * @brief Reports an advertising data or scan response packet from an + * advertising device that uses legacy advertising PDUs. + * + * This event is used to report advertisements only if the application includes + * the bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component + * + * Otherwise, the @ref sl_bt_evt_scanner_scan_report event is used for + * maintaining the backwards compatibility. + */ + +/** @brief Identifier of the legacy_advertisement_report event */ +#define sl_bt_evt_scanner_legacy_advertisement_report_id 0x000500a0 + +/***************************************************************************//** + * @brief Data structure of the legacy_advertisement_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_legacy_advertisement_report_s +{ + uint8_t event_flags; /**< The event type flag(s) in the + advertisement packet. Value: One or more + flags defined in @ref + sl_bt_scanner_event_flag */ + bd_addr address; /**< Advertiser address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the + local device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last + packet was received */ + bd_addr target_address; /**< The target address if the advertisement + is from directed advertising, otherwise + ignored */ + uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + The target address type if the + advertisement is from directed + advertising, otherwise ignored. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + the following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + enum @ref sl_bt_gap_address_type_t + values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8array data; /**< Advertising or scan response data. Ignore + if this is directed advertising. */ +}); + +typedef struct sl_bt_evt_scanner_legacy_advertisement_report_s sl_bt_evt_scanner_legacy_advertisement_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_legacy_advertisement_report + +/** + * @addtogroup sl_bt_evt_scanner_extended_advertisement_report sl_bt_evt_scanner_extended_advertisement_report + * @{ + * @brief Reports an advertising or scan response packet from an advertising + * device that uses extended advertising PDUs + * + * Multiple events may be reported for single advertisement train. + * + * This event is used to report advertisements only if the application includes + * the bluetooth_feature_extended_scanner component. Otherwise, the @ref + * sl_bt_evt_scanner_scan_report event is used for maintaining the backwards + * compatibility. + */ + +/** @brief Identifier of the extended_advertisement_report event */ +#define sl_bt_evt_scanner_extended_advertisement_report_id 0x020500a0 + +/***************************************************************************//** + * @brief Data structure of the extended_advertisement_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_extended_advertisement_report_s +{ + uint8_t event_flags; /**< The event type flag(s) in the + advertisement packet. Value: One or more + flags defined in @ref + sl_bt_scanner_event_flag */ + bd_addr address; /**< Advertiser address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the + local device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last + packet was received */ + bd_addr target_address; /**< The target address if this is directed + advertising, otherwise ignored */ + uint8_t target_address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + The target address type if the + advertisement is from directed + advertising, otherwise ignored. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + the following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p target_address_type uses + enum @ref sl_bt_gap_address_type_t + values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_sid; /**< Advertising set identifier */ + uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on + which advertising packets are transmitted + on the primary advertising channel + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on + which advertising packets are transmitted + on the secondary advertising channel + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + int8_t tx_power; /**< TX power value in the received packet + header. Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + uint16_t periodic_interval; /**< The periodic advertising interval. Value + 0 indicates no periodic advertising. + Otherwise, + - Range: 0x06 to 0xFFFF + - Unit: 1.25 ms + - Time range: 7.5 ms to 81.92 s */ + uint8_t data_completeness; /**< Enum @ref sl_bt_scanner_data_status_t. + The data completeness status. Values: + - sl_bt_scanner_data_status_complete + (0x0): All data of the + advertisement has been reported. + - sl_bt_scanner_data_status_incomplete_more + (0x1): Data of the advertisement + is incomplete in this event, and more + data will come in new events. + - sl_bt_scanner_data_status_incomplete_nomore + (0x2): Data of the advertisement + is incomplete in this event, but no + more data will come, i.e., the data + of the advertisement is truncated. */ + uint8_t counter; /**< The monotonically increasing counter as + the sequence number of the event. This + counter is specific to @ref + sl_bt_evt_scanner_extended_advertisement_report_id. + It can be used to detect if one more @ref + sl_bt_evt_scanner_extended_advertisement_report + events were dropped due to temporarily + out of resources or other reasons. Ignore + this field if event loss is not a + concern. */ + uint8array data; /**< Advertising or scan response data */ +}); + +typedef struct sl_bt_evt_scanner_extended_advertisement_report_s sl_bt_evt_scanner_extended_advertisement_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_extended_advertisement_report + +/** + * @addtogroup sl_bt_evt_scanner_scan_report sl_bt_evt_scanner_scan_report + * @{ + * @brief Deprecated and replaced by new @ref + * sl_bt_evt_scanner_legacy_advertisement_report and @ref + * sl_bt_evt_scanner_extended_advertisement_report events + * + * To use these new events, the application needs to include the + * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component. + * + * Reports an advertising or scan response packet from an advertising device + * that uses legacy or extended advertising PDUs. + */ + +/** @brief Identifier of the scan_report event */ +#define sl_bt_evt_scanner_scan_report_id 0x010500a0 + +/***************************************************************************//** + * @brief Data structure of the scan_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_scanner_scan_report_s +{ + uint8_t packet_type; /**< Bits 0..2 : advertising packet type + - 000 : Connectable scannable + undirected advertising + - 001 : Connectable undirected + advertising + - 010 : Scannable undirected + advertising + - 011 : Non-connectable + non-scannable undirected advertising + - 100 : Scan Response. Note that + this is received only if the device is + in active scan mode. + + Bits 3..4 : Reserved for future + + Bits 5..6 : data completeness + - 00: Complete + - 01: Incomplete, more data to + come in new events + - 10: Incomplete, data truncated, + no more to come + + Bit 7 : legacy or extended + advertising + - 0: Legacy advertising PDUs used + - 1: Extended advertising PDUs + used */ + bd_addr address; /**< Bluetooth address of the remote device */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t bonding; /**< Bonding handle if the remote advertising + device has previously bonded with the local + device. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ + uint8_t primary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which + advertising packets are transmitted on the + primary advertising channel. Ignore this + field if the report is for a legacy + advertising PDU. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_coded (0x4): Coded + PHY, 125k (S=8) or 500k (S=2) */ + uint8_t secondary_phy; /**< Enum @ref sl_bt_gap_phy_t. The PHY on which + advertising packets are transmitted on the + secondary advertising channel. Ignore this + field if the report is for a legacy + advertising PDU. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded + PHY, 125k (S=8) or 500k (S=2) */ + uint8_t adv_sid; /**< Advertising set identifier */ + int8_t tx_power; /**< TX power value in the received packet + header. Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the + last received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t channel; /**< The channel number on which the last packet + was received */ + uint16_t periodic_interval; /**< The periodic advertising interval. Value 0 + indicates no periodic advertising. + Otherwise, + - Range: 0x06 to 0xFFFF + - Unit: 1.25 ms + - Time range: 7.5 ms to 81.92 s */ + uint8array data; /**< Advertising or scan response data */ +}); + +typedef struct sl_bt_evt_scanner_scan_report_s sl_bt_evt_scanner_scan_report_t; + +/** @} */ // end addtogroup sl_bt_evt_scanner_scan_report + +/***************************************************************************//** + * + * Set scan parameters for subsequent scanning operations. If the device is + * currently scanning, new parameters will take effect when scanning is + * restarted. + * + * This command sets the scanning filter policy to the default value @ref + * sl_bt_scanner_filter_policy_basic_unfiltered. Use the command @ref + * sl_bt_scanner_set_parameters_and_filter to set a specific scanning filter + * policy. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * Passive or active scan. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * @param[in] interval @parblock + * The time interval when the device starts its last scan until it begins the + * subsequent scan. In other words, how often to scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] window @parblock + * The scan window, i.e., the duration of the scan, which must be less than or + * equal to the @p interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * Note that the packet reception is aborted if it's started just before the + * scan window ends. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_set_parameters(uint8_t mode, + uint16_t interval, + uint16_t window); + +/***************************************************************************//** + * + * Set scan parameters and the scanning filter policy for subsequent scanning + * operations. If the device is currently scanning, new parameters will take + * effect when scanning is restarted. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * Passive or active scan. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * @param[in] interval @parblock + * The time interval when the device starts its last scan until it begins the + * subsequent scan. In other words, how often to scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] window @parblock + * The scan window, i.e., the duration of the scan, which must be less than or + * equal to the @p interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * Note that the packet reception is aborted if it's started just before the + * scan window ends. + * @endparblock + * @param[in] flags No flags are currently defined. Set this parameter to 0. + * @param[in] filter_policy @parblock + * Enum @ref sl_bt_scanner_filter_policy_t. + * + * The scanning filter policy to use when scanning is started. The filter + * policy determines which advertisements and scan responses are delivered to + * the application. Values: + * - sl_bt_scanner_filter_policy_basic_unfiltered (0x0): Advertising + * and scan response PDUs are processed from all devices. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be a Resolvable Private Address that is + * resolved to the local device by the Bluetooth controller. + * - sl_bt_scanner_filter_policy_basic_filtered (0x1): Advertising + * and scan response PDUs are processed only from devices that the + * application has added to the Filter Accept List. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be a Resolvable Private Address that is + * resolved to the local device by the Bluetooth controller. + * - sl_bt_scanner_filter_policy_extended_unfiltered (0x2): + * Advertising and scan response PDUs are processed from all devices. For + * directed advertising, the target address must additionally match the + * identity address of the local device or be any Resolvable Private + * Address. + * - sl_bt_scanner_filter_policy_extended_filtered (0x3): Advertising + * and scan response PDUs are processed only from devices that the + * application has added to the Filter Accept List. For directed + * advertising, the target address must additionally match the identity + * address of the local device or be any Resolvable Private Address. + * + * Default value: @ref sl_bt_scanner_filter_policy_basic_unfiltered + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_set_parameters_and_filter(uint8_t mode, + uint16_t interval, + uint16_t window, + uint32_t flags, + uint8_t filter_policy); + +/***************************************************************************//** + * + * Stop scanning for advertising devices. For more information about the + * discovery, see the @ref sl_bt_scanner_start command. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_stop(); + +/***************************************************************************//** + * + * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters + * command. + * + * Set the scanning timing parameters on the specified PHY(s). If the device is + * currently scanning, new parameters will take effect when scanning is + * restarted. + * + * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the + * setting is set for. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs + * @param[in] scan_interval @parblock + * Scan interval is defined as the time interval when the device starts its + * last scan until it begins the subsequent scan. In other words, how often to + * scan + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms + * + * A variable delay occurs when switching channels at the end of each scanning + * interval, which is included in the scanning interval time. During the + * switch time, advertising packets are not received by the device. The switch + * time variation is use case-dependent. For example, if scanning while + * keeping active connections, the channel switch time might be longer than + * when scanning without any active connections. Increasing the scanning + * interval reduces the amount of time in which the device can't receive + * advertising packets because it switches channels less often. + * + * After every scan interval, the scanner changes the frequency at which it + * operates. It cycles through all three advertising channels in a round robin + * fashion. According to the specification, all three channels must be used by + * a scanner. + * @endparblock + * @param[in] scan_window @parblock + * Scan window defines the duration of the scan which must be less than or + * equal to the @p scan_interval + * - Time = Value x 0.625 ms + * - Range: 0x0004 to 0xFFFF + * - Time Range: 2.5 ms to 40.96 s + * + * Default value: 10 ms Note that the packet reception is aborted if it's + * started just before the scan window ends. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_timing(uint8_t phys, + uint16_t scan_interval, + uint16_t scan_window); + +/***************************************************************************//** + * + * Deprecated and replaced by the @ref sl_bt_scanner_set_parameters + * command. + * + * Set the scan mode on the specified PHY(s). If the device is currently + * scanning, new parameters will take effect when scanning is restarted. + * + * @param[in] phys Enum @ref sl_bt_scanner_scan_phy_t. The scanning PHY(s) the + * setting is set for. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): 1M PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): 1M and Coded PHYs + * @param[in] scan_mode @parblock + * Enum @ref sl_bt_scanner_scan_mode_t. + * + * The scan mode. Values: + * - sl_bt_scanner_scan_mode_passive (0x0): Passive scanning mode + * where the device only listens to advertising packets and does not + * transmit packets + * - sl_bt_scanner_scan_mode_active (0x1): Active scanning mode where + * the device sends out a scan request packet upon receiving a scannable + * advertising packet from a remote device and listens to the scan + * response packet from the remote device + * + * Default value: @ref sl_bt_scanner_scan_mode_passive. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_scanner_set_mode(uint8_t phys, uint8_t scan_mode); + +/***************************************************************************//** + * + * Start the GAP discovery procedure to scan for advertising devices that use + * legacy or extended advertising PDUs. To cancel an ongoing discovery + * procedure, use the @ref sl_bt_scanner_stop command. + * + * The invalid parameter error will be returned if the value of scanning PHYs is + * invalid or the device does not support a PHY. + * + * Received advertising packets are not filtered in any way, so multiple events + * will be received for every advertising device in range. + * + * @param[in] scanning_phy @parblock + * Enum @ref sl_bt_scanner_scan_phy_t. + * + * The scanning PHY(s). + * + * In simultaneous scanning, the stack alternates the scanning on two PHYs by + * switching the PHY at every scan interval. When a timing parameter is set + * differently on 1M and Coded PHY, the stack chooses the most relaxed value + * for both PHYs during simultaneous scanning, i.e., the largest scan interval + * or the smallest scan window. If one PHY is set to passive scanning and the + * other to active scanning, passive scanning is chosen for simultaneous + * scanning. Values: + * - sl_bt_scanner_scan_phy_1m (0x1): Initiate the scanning on the 1M + * PHY + * - sl_bt_scanner_scan_phy_coded (0x4): Initiate the scanning on the + * Coded PHY + * - sl_bt_scanner_scan_phy_1m_and_coded (0x5): Simultaneous scanning + * by initiating the scanning on the 1M and Coded PHY alternatively + * @endparblock + * @param[in] discover_mode Enum @ref sl_bt_scanner_discover_mode_t. Bluetooth + * discovery Mode. Values: + * - sl_bt_scanner_discover_limited (0x0): Discover only limited + * discoverable devices. + * - sl_bt_scanner_discover_generic (0x1): Discover limited and + * general discoverable devices. + * - sl_bt_scanner_discover_observation (0x2): Discover + * non-discoverable, limited and general discoverable devices. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_scanner_scan_report - This event is triggered for + * reporting a received advertisement if the application includes the + * bluetooth_feature_scanner component but does not include any other + * scanner component. + * - @ref sl_bt_evt_scanner_legacy_advertisement_report - This event is + * triggered for reporting a received advertisement that uses legacy + * advertising PDUs if the application includes the + * bluetooth_feature_legacy_scanner or bluetooth_feature_extended_scanner + * component. + * - @ref sl_bt_evt_scanner_extended_advertisement_report - This event is + * triggered for reporting a received advertisement that uses extended + * advertising PDUs if the application includes the + * bluetooth_feature_extended_scanner component. + * + ******************************************************************************/ +sl_status_t sl_bt_scanner_start(uint8_t scanning_phy, uint8_t discover_mode); + +/** @} */ // end addtogroup sl_bt_scanner + +/** + * @addtogroup sl_bt_sync Synchronization + * @{ + * + * @brief Synchronization + * + * Provides the base functionality of periodic advertising synchronization. Use + * bluetooth_feature_sync_scanner and/or bluetooth_feature_past_receiver + * components to include the synchronization mechanisms that the application + * requires. Use bluetooth_feature_periodic_sync to include support for trains + * that do not have subevents or response slots, and/or + * bluetooth_feature_pawr_sync to include support for Periodic Advertising with + * Responses (PAwR) trains. + * + * Some functionality in this class is considered deprecated and has been + * superseded by new classes. When one or more of + * bluetooth_feature_sync_scanner, bluetooth_feature_periodic_sync, or + * bluetooth_feature_pawr_sync components is included by the application, + * commands that have been superseded by the new classes are no longer available + * for use in the @ref sl_bt_sync class. Calling them will receive + * SL_STATUS_NOT_SUPPORTED error code. These commands are as follows: + * - @ref sl_bt_sync_set_parameters + * - @ref sl_bt_sync_open + * + * See the command descriptions for the replacements. + * + * Events that are deprecated and superseded by the new classes are no longer + * triggered by the @ref sl_bt_sync class if any of the new classes are included + * in the application. See event descriptions for the replacements. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_set_parameters_id 0x02420020 +#define sl_bt_cmd_sync_open_id 0x00420020 +#define sl_bt_cmd_sync_set_reporting_mode_id 0x03420020 +#define sl_bt_cmd_sync_update_sync_parameters_id 0x04420020 +#define sl_bt_cmd_sync_close_id 0x01420020 +#define sl_bt_rsp_sync_set_parameters_id 0x02420020 +#define sl_bt_rsp_sync_open_id 0x00420020 +#define sl_bt_rsp_sync_set_reporting_mode_id 0x03420020 +#define sl_bt_rsp_sync_update_sync_parameters_id 0x04420020 +#define sl_bt_rsp_sync_close_id 0x01420020 + +/** + * @brief Specifies the mode for periodic advertising reports. + */ +typedef enum +{ + sl_bt_sync_report_none = 0x0, /**< (0x0) Data received in periodic advertising + trains is not reported to the application. */ + sl_bt_sync_report_all = 0x1 /**< (0x1) Data received in periodic advertising + trains is reported to the application. */ +} sl_bt_sync_reporting_mode_t; + +/** + * @brief These values indicate the advertiser clock accuracy in a periodic + * advertising synchronization. + */ +typedef enum +{ + sl_bt_sync_clock_accuracy_500 = 0x1f4, /**< (0x1f4) Clock accuracy 500 ppm */ + sl_bt_sync_clock_accuracy_250 = 0xfa, /**< (0xfa) Clock accuracy 250 ppm */ + sl_bt_sync_clock_accuracy_150 = 0x96, /**< (0x96) Clock accuracy 150 ppm */ + sl_bt_sync_clock_accuracy_100 = 0x64, /**< (0x64) Clock accuracy 100 ppm */ + sl_bt_sync_clock_accuracy_75 = 0x4b, /**< (0x4b) Clock accuracy 75 ppm */ + sl_bt_sync_clock_accuracy_50 = 0x32, /**< (0x32) Clock accuracy 50 ppm */ + sl_bt_sync_clock_accuracy_30 = 0x1e, /**< (0x1e) Clock accuracy 30 ppm */ + sl_bt_sync_clock_accuracy_20 = 0x14 /**< (0x14) Clock accuracy 20 ppm */ +} sl_bt_sync_advertiser_clock_accuracy_t; + +/** + * @addtogroup sl_bt_evt_sync_opened sl_bt_evt_sync_opened + * @{ + * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_opened + * for periodic advertising trains that do not have subevents or response slots, + * and with @ref sl_bt_evt_pawr_sync_opened for Periodic Advertising with + * Responses (PAwR) trains. + * + * Indicates that a periodic advertising synchronization has been opened. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_sync_opened_id 0x004200a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_opened_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_sync_opened_s sl_bt_evt_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_opened + +/** + * @addtogroup sl_bt_evt_sync_transfer_received sl_bt_evt_sync_transfer_received + * @{ + * @brief Deprecated and replaced by @ref + * sl_bt_evt_periodic_sync_transfer_received for periodic advertising trains + * that do not have subevents or response slots responses, and with @ref + * sl_bt_evt_pawr_sync_transfer_received for Periodic Advertising with Responses + * (PAwR) trains. + * + * Indicates that synchronization information for a periodic advertising train + * has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_sync_transfer_received_id 0x034200a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was established. + Other values indicate that the sync failed to + get established. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_sync_transfer_received_s sl_bt_evt_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_sync_data sl_bt_evt_sync_data + * @{ + * @brief Deprecated and replaced by @ref sl_bt_evt_periodic_sync_report. + * + * Reports a received periodic advertisement packet. + */ + +/** @brief Identifier of the data event */ +#define sl_bt_evt_sync_data_id 0x024200a0 + +/***************************************************************************//** + * @brief Data structure of the data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_data_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the latest + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no more + to come */ + uint8array data; /**< Periodic advertising data */ +}); + +typedef struct sl_bt_evt_sync_data_s sl_bt_evt_sync_data_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_data + +/** + * @addtogroup sl_bt_evt_sync_closed sl_bt_evt_sync_closed + * @{ + * @brief Indicates that periodic advertising synchronization was lost or a + * synchronization establishment procedure was canceled + * + * The synchronization establishment procedure can be canceled explicitly by the + * application by issuing command @ref sl_bt_sync_close, or internally due to + * synchronization failing. Synchronization can fail for example due to + * incompatible sync CTE type. + */ + +/** @brief Identifier of the closed event */ +#define sl_bt_evt_sync_closed_id 0x014200a0 + +/***************************************************************************//** + * @brief Data structure of the closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sync_closed_s +{ + uint16_t reason; /**< SL_STATUS_OK if successful. Error code otherwise. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ +}); + +typedef struct sl_bt_evt_sync_closed_s sl_bt_evt_sync_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_sync_closed + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_sync_scanner_set_sync_parameters. + * + * Configure periodic advertiser synchronization parameters. The specified + * parameters take effect immediately for all advertisers that have not already + * established synchronization. + * + * The application should determine skip and timeout values based on the + * periodic advertising interval provided by the advertiser. Ensure that you use + * a long enough timeout to allow multiple receives. If @p skip and @p timeout + * are used, select appropriate values so that they allow a few receiving + * attempts. Periodic advertising intervals are reported in event @ref + * sl_bt_evt_scanner_scan_report. + * + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] flags No flags defined currently + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_set_parameters(uint16_t skip, + uint16_t timeout, + uint32_t flags); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_sync_scanner_open. + * + * Start establishing synchronization with the specified periodic advertiser in + * parallel with other advertisers given in previous invocations of this + * command. The stack will internally enable scanning when needed so that + * synchronizations can occur. The scanning responses from the internal scanning + * are not passed to the application unless the application has also enabled + * scanning. + * + * Advertisers that have not already synced before the invocation of this + * command will be synced using the @p skip and @p timeout values configured in + * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. + * + * @param[in] address Address of the advertiser + * @param[in] address_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Advertiser address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * @param[in] adv_sid Advertising set identifier + * @param[out] sync A handle that will be assigned to the periodic advertising + * synchronization after the synchronization is established. This handle is + * valid only if the result code of this response is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_opened - Triggered after the synchronization is + * established. + * - @ref sl_bt_evt_sync_data - Indicates that a periodic advertisement packet + * is received. + * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising + * synchronization was lost or explicitly closed, or a synchronization + * establishment procedure was canceled. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sync_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync); + +/***************************************************************************//** + * + * Set data reporting mode of the periodic advertising synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] reporting_mode Enum @ref sl_bt_sync_reporting_mode_t. Specifies + * the mode for reporting data received in the periodic advertising train. + * Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_set_reporting_mode(uint16_t sync, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Update synchronization parameters for a periodic sync that was already + * established. + * + * When a sync is established by scanning (see @ref sl_bt_sync_scanner) or by + * receiving Periodic Advertising Synchronization Transfer (see @ref + * sl_bt_past_receiver), the sync gets the @p skip and @p timeout parameters + * that were configured in the corresponding class. The application can use this + * command @ref sl_bt_sync_update_sync_parameters to update the values of a sync + * that has been established. The application can for example update the values + * to better match the actual interval of the periodic advertising train, or to + * increase the @p skip value to minimize wakeups when power saving is + * prioritized over receiving every periodic advertisement. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_update_sync_parameters(uint16_t sync, + uint16_t skip, + uint16_t timeout); + +/***************************************************************************//** + * + * Close a periodic advertising synchronization or cancel an ongoing attempt of + * establishing a synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_closed - Triggered after a periodic advertising + * synchronization has been closed or canceled. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_close(uint16_t sync); + +/** @} */ // end addtogroup sl_bt_sync + +/** + * @addtogroup sl_bt_sync_scanner Periodic Advertising Sync Scanner + * @{ + * + * @brief Periodic Advertising Sync Scanner + * + * Synchronize to periodic advertising trains by scanning for extended + * advertisements that provide the synchronization information. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_scanner_set_sync_parameters_id 0x00500020 +#define sl_bt_cmd_sync_scanner_open_id 0x01500020 +#define sl_bt_rsp_sync_scanner_set_sync_parameters_id 0x00500020 +#define sl_bt_rsp_sync_scanner_open_id 0x01500020 + +/***************************************************************************//** + * + * Configure synchronization parameters for synchronizing to periodic + * advertising trains. The specified parameters take effect immediately for all + * periodic advertising trains that have not already established + * synchronization. + * + * The application should determine skip and timeout values based on the + * periodic advertising interval provided by the advertiser. Ensure that you use + * a long enough timeout to allow multiple receives. If @p skip and @p timeout + * are used, select appropriate values so that they allow a few receiving + * attempts. Periodic advertising intervals are reported in @ref + * sl_bt_evt_scanner_scan_report or @ref + * sl_bt_evt_scanner_extended_advertisement_report event. + * + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_scanner_set_sync_parameters(uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Start establishing synchronization with the specified periodic advertiser in + * parallel with other advertisers given in previous invocations of this + * command. + * + * If the application has not already started scanning with the @ref + * sl_bt_scanner_start command, the stack will internally enable scanning so + * that synchronizations can occur. The internal scanning uses the PHY that was + * most recently used with @ref sl_bt_scanner_start and the parameters that have + * been configured with @ref sl_bt_scanner_set_timing. The internal scanning is + * automatically stopped when all requested synchronizations have occurred. + * + * The scanning responses from the internal scanning are not passed to the + * application unless the application starts scanning with the @ref + * sl_bt_scanner_start command. If the application starts scanning while + * synchronizations are being established, the scanning PHY and settings set by + * the application take effect immediately and scanning for synchronizations + * continues with the new settings. When the application has started scanning + * with the @ref sl_bt_scanner_start command, scanning continues until the + * application stops scanning with the @ref sl_bt_scanner_stop command. + * + * Advertisers that have not already synced before the invocation of this + * command will be synced using the @p skip and @p timeout values configured in + * the most recent invocation of command @ref sl_bt_evt_scanner_scan_report. + * + * @param[in] address Address of the advertiser + * @param[in] address_type @parblock + * Enum @ref sl_bt_gap_address_type_t. + * + * Advertiser address type. + * + * If the application does not include the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses the following values: + * - 0: Public address + * - 1: Random address + * + * If the application includes the + * bluetooth_feature_use_accurate_api_address_types component, @p address_type + * uses enum @ref sl_bt_gap_address_type_t values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @endparblock + * @param[in] adv_sid Advertising set identifier + * @param[out] sync A handle that will be assigned to the periodic advertising + * synchronization after the synchronization is established. This handle is + * valid only if the result code of this response is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_periodic_sync_opened - Triggered after synchronization is + * established to a periodic advertising train that does not have subevents + * or response slots. + * - @ref sl_bt_evt_pawr_sync_opened - Triggered after synchronization is + * established to a Periodic Advertising with Responses (PAwR) train. + * - @ref sl_bt_evt_periodic_sync_report - Triggered when data for periodic + * advertising train that does not have subevents or response slots is + * received and accepted by the reporting mode currently set to the train. + * - @ref sl_bt_evt_pawr_sync_subevent_report - Triggered when subevent data + * for Periodic Advertising with Responses (PAwR) train is received and + * accepted by the reporting mode currently set to the train. + * - @ref sl_bt_evt_sync_closed - Triggered after periodic advertising + * synchronization was lost or explicitly closed, or a synchronization + * establishment procedure was canceled. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_scanner_open(bd_addr address, + uint8_t address_type, + uint8_t adv_sid, + uint16_t *sync); + +/** @} */ // end addtogroup sl_bt_sync_scanner + +/** + * @addtogroup sl_bt_past_receiver PAST Receiver + * @{ + * + * @brief PAST Receiver + * + * Synchronize to periodic advertising trains by receiving Periodic Advertising + * Synchronization Transfer over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_past_receiver_set_default_sync_receive_parameters_id 0x00510020 +#define sl_bt_cmd_past_receiver_set_sync_receive_parameters_id 0x01510020 +#define sl_bt_rsp_past_receiver_set_default_sync_receive_parameters_id 0x00510020 +#define sl_bt_rsp_past_receiver_set_sync_receive_parameters_id 0x01510020 + +/** + * @brief Specifies the mode for receiving synchronization transfers + */ +typedef enum +{ + sl_bt_past_receiver_mode_ignore = 0x0, /**< (0x0) No attempt is made to + synchronize to a periodic + advertising train for which + the synchronization + information was received. No + event will be triggered + towards the application. */ + sl_bt_past_receiver_mode_synchronize = 0x1 /**< (0x1) Attempt to synchronize + to a periodic advertising + train for which the + synchronization information + was received. When the + information is received, an + event will be triggered to + indicate success or failure + and to provide the + application with the periodic + advertising synchronization + handle. */ +} sl_bt_past_receiver_mode_t; + +/***************************************************************************//** + * + * Set the default parameters for receiving Periodic Advertising Synchronization + * Transfers (PAST) over connections. The default parameters will be in effect + * for all subsequent connections, unless overridden by command @ref + * sl_bt_past_receiver_set_sync_receive_parameters after the connection is + * opened. + * + * This command sets parameters that do not limit the synchronization based on + * the CTE type. If the application includes bluetooth_feature_aoa_receiver or + * bluetooth_feature_aod_receiver component and wants to specify a particular + * CTE limitation, the application should use the command @ref + * sl_bt_cte_receiver_set_default_sync_receive_parameters to set the default + * parameters. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_past_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Set the parameters for receiving Periodic Advertising Synchronization + * Transfers (PAST) over the specified connection. The parameters do not affect + * periodic advertising trains that the device has already synchronized to. + * + * This command sets parameters that do not limit the synchronization based on + * the CTE type. If the application includes bluetooth_feature_aoa_receiver or + * bluetooth_feature_aod_receiver component and wants to specify a particular + * CTE limitation, the application should use the command @ref + * sl_bt_cte_receiver_set_sync_receive_parameters to set the parameters. + * + * @param[in] connection Connection handle of the connection used to receive the + * sync transfer + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_past_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t reporting_mode); + +/** @} */ // end addtogroup sl_bt_past_receiver + +/** + * @addtogroup sl_bt_advertiser_past Advertiser PAST + * @{ + * + * @brief Advertiser PAST + * + * Transfer the synchronization information of a local active periodic + * advertising set to a remote device using Periodic Advertising Synchronization + * Transfer (PAST) over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_advertiser_past_transfer_id 0x00520020 +#define sl_bt_rsp_advertiser_past_transfer_id 0x00520020 + +/***************************************************************************//** + * + * Transfer the synchronization information of an advertising set that is + * actively performing periodic advertising. + * + * @param[in] connection Connection handle of the connection used to transmit + * the sync transfer + * @param[in] service_data A value provided by the application for use by the + * peer device. + * @param[in] advertising_set Handle of the periodic advertising set to transfer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_advertiser_past_transfer(uint8_t connection, + uint16_t service_data, + uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_advertiser_past + +/** + * @addtogroup sl_bt_sync_past Sync PAST + * @{ + * + * @brief Sync PAST + * + * Transfer the synchronization information of a synchronized periodic + * advertising train to a remote device using Periodic Advertising + * Synchronization Transfer (PAST) over a connection. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sync_past_transfer_id 0x005b0020 +#define sl_bt_rsp_sync_past_transfer_id 0x005b0020 + +/***************************************************************************//** + * + * Transfer the synchronization information of a periodic advertising train for + * which a sync has been established. + * + * @param[in] connection Connection handle of the connection used to transmit + * the sync transfer + * @param[in] service_data A value provided by the application for use by the + * peer device. + * @param[in] sync Handle of the periodic advertising synchronization to + * transfer + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sync_past_transfer(uint8_t connection, + uint16_t service_data, + uint16_t sync); + +/** @} */ // end addtogroup sl_bt_sync_past + +/** + * @addtogroup sl_bt_periodic_sync Periodic Advertising without responses Synchronization + * @{ + * + * @brief Periodic Advertising without responses Synchronization + * + * Provides events and control for synchronized periodic advertising trains that + * do not have subevents or response slots. Synchronization is achieved by + * scanning (see @ref sl_bt_sync_scanner) or by receiving Periodic Advertising + * Synchronization Transfer (see @ref sl_bt_past_receiver). + */ + +/* Command and Response IDs */ + +/** + * @addtogroup sl_bt_evt_periodic_sync_opened sl_bt_evt_periodic_sync_opened + * @{ + * @brief Indicates that synchronization to a periodic advertising train that + * does not have subevents or response slots has been opened by scanning + * + * See command @ref sl_bt_sync_scanner_open. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_periodic_sync_opened_id 0x005300a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_opened_s +{ + uint16_t sync; /**< Periodic Advertising synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The Periodic Advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_periodic_sync_opened_s sl_bt_evt_periodic_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_opened + +/** + * @addtogroup sl_bt_evt_periodic_sync_transfer_received sl_bt_evt_periodic_sync_transfer_received + * @{ + * @brief Indicates that synchronization information for a periodic advertising + * train that does not have subevents or response slots has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_periodic_sync_transfer_received_id 0x015300a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was established. + Other values indicate that the sync failed to + get established. */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser PHY. + Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): Coded PHY, + 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value in + units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. The + advertiser clock accuracy. */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_periodic_sync_transfer_received_s sl_bt_evt_periodic_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_periodic_sync_report sl_bt_evt_periodic_sync_report + * @{ + * @brief Reports a periodic advertising packet for periodic advertising train + * that does not have subevents or response slots + */ + +/** @brief Identifier of the report event */ +#define sl_bt_evt_periodic_sync_report_id 0x025300a0 + +/***************************************************************************//** + * @brief Data structure of the report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_periodic_sync_report_s +{ + uint16_t sync; /**< Periodic advertising synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) in the latest + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no more + to come */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_periodic_sync_report event as a + monotonically increasing counter that wraps from + 255 to 0. There is a single counter for this + event type that starts from value 0 when the + Bluetooth stack is started and is never reset + while the stack is running. This counter can be + used to detect if one or more @ref + sl_bt_evt_periodic_sync_report events have been + created by the stack but dropped due to problems + such as temporarily running out of resources + before the event reached the application. */ + uint8array data; /**< Periodic advertising data */ +}); + +typedef struct sl_bt_evt_periodic_sync_report_s sl_bt_evt_periodic_sync_report_t; + +/** @} */ // end addtogroup sl_bt_evt_periodic_sync_report + +/** @} */ // end addtogroup sl_bt_periodic_sync + +/** + * @addtogroup sl_bt_pawr_sync Periodic Advertising with responses Synchronization + * @{ + * + * @brief Periodic Advertising with responses Synchronization + * + * Provides events and control for synchronized Periodic Advertising with + * Responses (PAwR) trains. Synchronization is achieved by scanning (see @ref + * sl_bt_sync_scanner) or by receiving Periodic Advertising Synchronization + * Transfer (see @ref sl_bt_past_receiver). + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_pawr_sync_set_sync_subevents_id 0x02540020 +#define sl_bt_cmd_pawr_sync_set_response_data_id 0x03540020 +#define sl_bt_rsp_pawr_sync_set_sync_subevents_id 0x02540020 +#define sl_bt_rsp_pawr_sync_set_response_data_id 0x03540020 + +/** + * @addtogroup sl_bt_evt_pawr_sync_opened sl_bt_evt_pawr_sync_opened + * @{ + * @brief Indicates that synchronization to a Periodic Advertising with + * Responses (PAwR) train has been opened by scanning + * + * See command @ref sl_bt_sync_scanner_open. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_pawr_sync_opened_id 0x005400a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_opened_s +{ + uint16_t sync; /**< PAwR synchronization handle */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser + PHY. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value + in units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. + The advertiser clock accuracy. */ + uint8_t num_subevents; /**< The number of subevents. + - Range: 0x01 to 0x80 */ + uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 + ms. + - Range: 0x06 to 0xFF + - Time range: 7.5 ms to 318.75 ms */ + uint8_t response_slot_delay; /**< Time between the advertising packet in a + subevent and the first response slot. + Value in units of 1.25 ms. + - Range: 0x01 to 0xFE + - Time range: 1.25 ms to 317.5 ms */ + uint8_t response_slot_spacing; /**< Time between response slots. Value in + units of 0.125 ms. + - Range: 0x02 to 0xFF + - Time range: 0.25 ms to 31.875 ms */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_pawr_sync_opened_s sl_bt_evt_pawr_sync_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_opened + +/** + * @addtogroup sl_bt_evt_pawr_sync_transfer_received sl_bt_evt_pawr_sync_transfer_received + * @{ + * @brief Indicates that synchronization information for Periodic Advertising + * with Responses (PAwR) train has been received + * + * See @ref sl_bt_past_receiver. + */ + +/** @brief Identifier of the transfer_received event */ +#define sl_bt_evt_pawr_sync_transfer_received_id 0x015400a0 + +/***************************************************************************//** + * @brief Data structure of the transfer_received event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_transfer_received_s +{ + uint16_t status; /**< SL_STATUS_OK if synchronization was + established. Other values indicate that + the sync failed to get established. */ + uint16_t sync; /**< PAwR synchronization handle */ + uint16_t service_data; /**< A value provided by the peer device. */ + uint8_t connection; /**< Connection handle of the connection that + transferred the sync info */ + uint8_t adv_sid; /**< Advertising set identifier */ + bd_addr address; /**< Address of the advertiser */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the + following values: + - 0: Public address + - 1: Random address + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address + (0x0): Public device address + - sl_bt_gap_static_address + (0x1): Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private + random address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t adv_phy; /**< Enum @ref sl_bt_gap_phy_t. The advertiser + PHY. Values: + - sl_bt_gap_phy_1m (0x1): 1M PHY + - sl_bt_gap_phy_2m (0x2): 2M PHY + - sl_bt_gap_phy_coded (0x4): + Coded PHY, 125k (S=8) or 500k (S=2) */ + uint16_t adv_interval; /**< The periodic advertising interval. Value + in units of 1.25 ms + - Range: 0x06 to 0xFFFF + - Time range: 7.5 ms to 81.92 s */ + uint16_t clock_accuracy; /**< Enum @ref + sl_bt_sync_advertiser_clock_accuracy_t. + The advertiser clock accuracy. */ + uint8_t num_subevents; /**< The number of subevents. + - Range: 0x01 to 0x80 */ + uint8_t subevent_interval; /**< Subevent interval. Value in units of 1.25 + ms. + - Range: 0x06 to 0xFF + - Time range: 7.5 ms to 318.75 ms */ + uint8_t response_slot_delay; /**< Time between the advertising packet in a + subevent and the first response slot. + Value in units of 1.25 ms. + - Range: 0x01 to 0xFE + - Time range: 1.25 ms to 317.5 ms */ + uint8_t response_slot_spacing; /**< Time between response slots. Value in + units of 0.125 ms. + - Range: 0x02 to 0xFF + - Time range: 0.25 ms to 31.875 ms */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE + (0xff): No bonding + - Other: Bonding handle */ +}); + +typedef struct sl_bt_evt_pawr_sync_transfer_received_s sl_bt_evt_pawr_sync_transfer_received_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_transfer_received + +/** + * @addtogroup sl_bt_evt_pawr_sync_subevent_report sl_bt_evt_pawr_sync_subevent_report + * @{ + * @brief Reports that the device's radio has received a periodic advertisement + * in a subevent of an active PAwR train + * + * This event reports also empty advertisements, i.e., advertisements that + * contained no payload data. In this case the @p data parameter has zero + * length. + */ + +/** @brief Identifier of the subevent_report event */ +#define sl_bt_evt_pawr_sync_subevent_report_id 0x025400a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_sync_subevent_report_s +{ + uint16_t sync; /**< PAwR synchronization handle */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) of the + received packet. Units: dBm + - Range: -127 to +20 */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint16_t event_counter; /**< The value of the periodic advertising event + counter (paEventCounter) of the event in which + the advertisement was received. If the + application responds to this advertisement, use + this field as the value of @p request_event + parameter for the @ref + sl_bt_pawr_sync_set_response_data command. */ + uint8_t subevent; /**< The subevent in which the advertisement was + received. If the application responds to this + advertisement, use this field as the value of + @p request_subevent parameter for the @ref + sl_bt_pawr_sync_set_response_data command. */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come in + new events + - 2: Incomplete, data truncated, no + more to come + - 255: Failed to receive subevent data + in this subevent */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_pawr_sync_subevent_report event as a + monotonically increasing counter that wraps + from 255 to 0. There is a single counter for + this event type that starts from value 0 when + the Bluetooth stack is started and is never + reset while the stack is running. This counter + can be used to detect if one or more @ref + sl_bt_evt_pawr_sync_subevent_report events have + been created by the stack but dropped due to + problems such as temporarily running out of + resources before the event reached the + application. */ + uint8array data; /**< The advertisement data that was received */ +}); + +typedef struct sl_bt_evt_pawr_sync_subevent_report_s sl_bt_evt_pawr_sync_subevent_report_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_sync_subevent_report + +/***************************************************************************//** + * + * Specify the subevents that this device will synchronize to on the specified + * PAwR train. + * + * @param[in] sync PAwR synchronization handle + * @param[in] subevents_len Length of data in @p subevents + * @param[in] subevents Array of subevent indexes to synchronize to + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_sync_set_sync_subevents(uint16_t sync, + size_t subevents_len, + const uint8_t* subevents); + +/***************************************************************************//** + * + * Set the data to be sent in the specified response slot of a subevent of an + * active PAwR train. + * + * Use this command when the application receives the @ref + * sl_bt_evt_pawr_sync_subevent_report event and the application needs to send a + * response. The application needs to set the response data within the timing + * requirements implied by the parameters of the PAwR train that the device is + * synchronized to. If the response data is set too late, this command will fail + * with result SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT. + * + * @param[in] sync PAwR synchronization handle + * @param[in] request_event The periodic advertising event counter + * (paEventCounter) of the request. Set this parameter to the value of the @p + * event_counter field of the @ref sl_bt_evt_pawr_sync_subevent_report_id + * event that the application is responding to. + * @param[in] request_subevent The subevent of the request. Set this parameter + * to the value of the @p subevent field of the @ref + * sl_bt_evt_pawr_sync_subevent_report_id event that the application is + * responding to. + * @param[in] response_subevent The subevent in which the response is to be sent + * @param[in] response_slot The response slot in which the response is to be + * sent + * @param[in] response_data_len Length of data in @p response_data + * @param[in] response_data Data to be sent in the specified response slot. + * Maximum of 248 bytes of data can be set with this command. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_sync_set_response_data(uint16_t sync, + uint16_t request_event, + uint8_t request_subevent, + uint8_t response_subevent, + uint8_t response_slot, + size_t response_data_len, + const uint8_t* response_data); + +/** @} */ // end addtogroup sl_bt_pawr_sync + +/** + * @addtogroup sl_bt_pawr_advertiser PAwR Advertiser + * @{ + * + * @brief PAwR Advertiser + * + * Provides support for advertising with Periodic Advertising with Responses + * (PAwR) trains. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_pawr_advertiser_start_id 0x00550020 +#define sl_bt_cmd_pawr_advertiser_set_subevent_data_id 0x01550020 +#define sl_bt_cmd_pawr_advertiser_create_connection_id 0x02550020 +#define sl_bt_cmd_pawr_advertiser_stop_id 0x03550020 +#define sl_bt_rsp_pawr_advertiser_start_id 0x00550020 +#define sl_bt_rsp_pawr_advertiser_set_subevent_data_id 0x01550020 +#define sl_bt_rsp_pawr_advertiser_create_connection_id 0x02550020 +#define sl_bt_rsp_pawr_advertiser_stop_id 0x03550020 + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request sl_bt_evt_pawr_advertiser_subevent_data_request + * @{ + * @brief This event is triggered to indicate that the Bluetooth stack is ready + * to accept data for the specified subevents of the PAwR train. + * + * To ensure effective use of the available memory, applications are encouraged + * to observe these events and set data using @ref + * sl_bt_pawr_advertiser_set_subevent_data for the subevents that are being + * requested and for which the application has data to send + * + * If the application has no data to send, it does not need to call @ref + * sl_bt_pawr_advertiser_set_subevent_data for that subevent. The application + * can attempt to set data for that subevent later when the application has new + * data to send. + */ + +/** @brief Identifier of the subevent_data_request event */ +#define sl_bt_evt_pawr_advertiser_subevent_data_request_id 0x005500a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_data_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_data_request_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle */ + uint8_t subevent_start; /**< The first subevent that data is requested + for */ + uint8_t subevent_data_count; /**< The number of subevents that data is + requested for */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_subevent_data_request_s sl_bt_evt_pawr_advertiser_subevent_data_request_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_data_request + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed sl_bt_evt_pawr_advertiser_subevent_tx_failed + * @{ + * @brief This event is triggered if subevent data was successfully set using + * @ref sl_bt_pawr_advertiser_set_subevent_data command but the attempt to + * transmit the subevent data has failed + * + * This error is not fatal. The event is provided to the application so that it + * knows not to expect response reports for this subevent and can set subevent + * data again for retransmission without needing to timeout waiting for response + * reports that will not be received because the transmission failed. + */ + +/** @brief Identifier of the subevent_tx_failed event */ +#define sl_bt_evt_pawr_advertiser_subevent_tx_failed_id 0x025500a0 + +/***************************************************************************//** + * @brief Data structure of the subevent_tx_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle for the PAwR + train that failed to transmit subevent data */ + uint8_t subevent; /**< The subevent that failed to transmit subevent + data */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_subevent_tx_failed_s sl_bt_evt_pawr_advertiser_subevent_tx_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_subevent_tx_failed + +/** + * @addtogroup sl_bt_evt_pawr_advertiser_response_report sl_bt_evt_pawr_advertiser_response_report + * @{ + * @brief Reports the status and data of a used response slot of an active PAwR + * train + * + * The report is given for every response slot that was marked as used in the + * @ref sl_bt_pawr_advertiser_set_subevent_data command. + */ + +/** @brief Identifier of the response_report event */ +#define sl_bt_evt_pawr_advertiser_response_report_id 0x015500a0 + +/***************************************************************************//** + * @brief Data structure of the response_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_pawr_advertiser_response_report_s +{ + uint8_t advertising_set; /**< The PAwR advertising set handle */ + uint8_t subevent; /**< The subevent that this report corresponds to */ + int8_t tx_power; /**< TX power value in the received packet header. + Units: dBm + - Valid value range: -127 to 126 + - Value 127: information unavailable */ + int8_t rssi; /**< Signal strength indicator (RSSI) of the + received packet. Units: dBm + - Valid value range: -127 to +20 + - Value 127: information unavailable */ + uint8_t cte_type; /**< The CTE type + - 0x00: AoA CTE + - 0x01: AoD CTE with 1us slots + - 0x02: AoD CTE with 2us slots + - 0xFF: No CTE */ + uint8_t response_slot; /**< The response slot that this report + corresponds to */ + uint8_t data_status; /**< Data completeness: + - 0: Complete + - 1: Incomplete, more data to come + in new events + - 2: Incomplete, data truncated, no + more to come + - 255: Failed to receive subevent + response in this response slot */ + uint8_t counter; /**< The sequence number of this @ref + sl_bt_evt_pawr_advertiser_response_report + event as a monotonically increasing counter + that wraps from 255 to 0. There is a single + counter for this event type that starts from + value 0 when the Bluetooth stack is started + and is never reset while the stack is + running. This counter can be used to detect + if one or more @ref + sl_bt_evt_pawr_advertiser_response_report + events have been created by the stack but + dropped due to problems such as temporarily + running out of resources before the event + reached the application. */ + uint8array data; /**< The response data that was received, if any */ +}); + +typedef struct sl_bt_evt_pawr_advertiser_response_report_s sl_bt_evt_pawr_advertiser_response_report_t; + +/** @} */ // end addtogroup sl_bt_evt_pawr_advertiser_response_report + +/***************************************************************************//** + * + * Start PAwR advertising on the specified advertising set. + * + * According to the Bluetooth Core specification, PAwR advertising PDUs cannot + * be transmitted until at least one extended advertising event has been + * completed. If the application needs exact control over the extended + * advertising data and parameters, use the @ref sl_bt_advertiser class to + * configure the parameters of the advertising set and the @ref + * sl_bt_extended_advertiser class to set or generate the desired extended + * advertising data payload. If the application does not configure the + * parameters or set the data, the default parameters and empty advertising data + * are used for the extended advertising. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is set in @p + * flags, the stack will automatically start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. The application may stop the automatically started extended + * advertising using the @ref sl_bt_advertiser_stop command. + * + * If the application has not already started extended advertising and the flag + * @ref SL_BT_PERIODIC_ADVERTISER_AUTO_START_EXTENDED_ADVERTISING is not set in + * @p flags, the stack will momentarily start extended advertising with the + * parameters and extended advertising data currently configured to the + * advertising set. Unless the application starts extended advertising before + * the first extended advertising event has completed, the stack will + * automatically stop the momentary extended advertising after the first + * extended advertising event. + * + * PAwR advertising PDUs are transmitted on the secondary PHY configured for the + * advertising set with the @ref sl_bt_extended_advertiser_set_phy command. + * + * To stop PAwR advertising, use @ref sl_bt_pawr_advertiser_stop command. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] interval_min @parblock + * Minimum periodic advertising interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * + * Default value: 100 ms + * @endparblock + * @param[in] interval_max @parblock + * Maximum periodic advertising interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFFFF + * - Time range: 7.5 ms to 81.92 s + * - Note: interval_max should be bigger than interval_min + * + * Default value: 200 ms + * @endparblock + * @param[in] flags Additional periodic advertising options. Value: 0 or bitmask + * of @ref sl_bt_periodic_advertiser_flags + * @param[in] num_subevents The number of subevents. + * - Range: 0x01 to 0x80 + * @param[in] subevent_interval Subevent interval. Value in units of 1.25 ms. + * - Range: 0x06 to 0xFF + * - Time range: 7.5 ms to 318.75 ms + * @param[in] response_slot_delay Time between the advertising packet in a + * subevent and the first response slot. Value in units of 1.25 ms. + * - Range: 0x01 to 0xFE + * - Time range: 1.25 ms to 317.5 ms + * @param[in] response_slot_spacing Time between response slots. Value in units + * of 0.125 ms. + * - Range: 0x02 to 0xFF + * - Time range: 0.25 ms to 31.875 ms + * @param[in] response_slots Number of subevent response slots. + * - Range: 0x01 to 0xFF + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_start(uint8_t advertising_set, + uint16_t interval_min, + uint16_t interval_max, + uint32_t flags, + uint8_t num_subevents, + uint8_t subevent_interval, + uint8_t response_slot_delay, + uint8_t response_slot_spacing, + uint8_t response_slots); + +/***************************************************************************//** + * + * Set data to be sent in the specified subevent of an active PAwR train. Data + * is transmitted only once and is discarded after it has been transmitted. + * + * Data given to this command is passed to the Bluetooth controller, which will + * queue data and transmit it at the correct time. The application may always + * opportunistically try to queue more data with this command, but the + * controller may reject data and return an error if the queuing capacity is + * exceeded. In this case, the Bluetooth stack will trigger the @ref + * sl_bt_evt_pawr_advertiser_subevent_data_request event later when the + * controller is ready to accept more data. + * + * To ensure effective use of the available memory, applications are encouraged + * to observe the @ref sl_bt_evt_pawr_advertiser_subevent_data_request events + * and set data for the subevents that are being requested and for which the + * application has data to send. Applications should also note that PAwR is an + * unreliable transport and cannot guarantee delivery. If reliability is + * required, the application must implement an acknowledgment mechanism using + * response slots of the PAwR train and set subevent data again for a + * re-transmission if it was not successfully delivered. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] subevent The subevent in which the data is to be sent + * @param[in] response_slot_start The first response slot to be used in this + * subevent + * @param[in] response_slot_count The number of response slots to be used + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be sent in the specified subevent + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_pawr_advertiser_subevent_data_request - This event is + * triggered when the Bluetooth stack is ready to accept more subevent data. + * - @ref sl_bt_evt_pawr_advertiser_subevent_tx_failed - This event is + * triggered if transmitting the subevent data has failed. + * - @ref sl_bt_evt_pawr_advertiser_response_report - If the subevent data was + * successfully transmitted, this event is triggered for each response slot + * that was marked as used in this subevent. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_set_subevent_data(uint8_t advertising_set, + uint8_t subevent, + uint8_t response_slot_start, + uint8_t response_slot_count, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Initiate a connection request to a device that is synchronized to the + * specified active PAwR train. The connection is established on the secondary + * PHY configured for the advertising set with the @ref + * sl_bt_extended_advertiser_set_phy command. The connection uses the parameters + * configured with command @ref sl_bt_connection_set_default_parameters. + * + * @param[in] advertising_set The PAwR advertising set handle + * @param[in] subevent The subevent in which the connection request is to be + * sent + * @param[in] address Address of the device to connect to + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device to connect to. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @param[out] connection Handle that will be assigned to the connection after + * the connection is established. This handle is valid only if the result code + * of this command is SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed - This event is triggered if the + * connection failed to be created. + * - @ref sl_bt_evt_connection_opened - This event is triggered after the + * connection is opened and indicates whether the devices are already bonded + * and the role of the device in this connection. + * - @ref sl_bt_evt_connection_parameters - This event indicates the + * connection parameters and security mode of the connection. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_create_connection(uint8_t advertising_set, + uint8_t subevent, + bd_addr address, + uint8_t address_type, + uint8_t *connection); + +/***************************************************************************//** + * + * Stop PAwR advertising on an advertising set. Counterpart to @ref + * sl_bt_pawr_advertiser_start. + * + * This command does not affect the enable state of the advertising set, i.e., + * legacy or extended advertising is not stopped. + * + * @param[in] advertising_set The PAwR advertising set handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_pawr_advertiser_stop(uint8_t advertising_set); + +/** @} */ // end addtogroup sl_bt_pawr_advertiser + +/** + * @addtogroup sl_bt_connection Connection + * @{ + * + * @brief Connection + * + * The commands and events in this class are related to managing connection + * establishment, parameter setting, and disconnection procedures. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_connection_set_default_parameters_id 0x00060020 +#define sl_bt_cmd_connection_set_default_preferred_phy_id 0x01060020 +#define sl_bt_cmd_connection_set_default_data_length_id 0x10060020 +#define sl_bt_cmd_connection_open_id 0x04060020 +#define sl_bt_cmd_connection_set_parameters_id 0x06060020 +#define sl_bt_cmd_connection_set_preferred_phy_id 0x08060020 +#define sl_bt_cmd_connection_disable_slave_latency_id 0x03060020 +#define sl_bt_cmd_connection_get_median_rssi_id 0x15060020 +#define sl_bt_cmd_connection_read_channel_map_id 0x07060020 +#define sl_bt_cmd_connection_set_power_reporting_id 0x09060020 +#define sl_bt_cmd_connection_set_remote_power_reporting_id 0x0a060020 +#define sl_bt_cmd_connection_get_tx_power_id 0x0b060020 +#define sl_bt_cmd_connection_get_remote_tx_power_id 0x0c060020 +#define sl_bt_cmd_connection_set_tx_power_id 0x12060020 +#define sl_bt_cmd_connection_read_remote_used_features_id 0x0d060020 +#define sl_bt_cmd_connection_get_security_status_id 0x0e060020 +#define sl_bt_cmd_connection_set_data_length_id 0x11060020 +#define sl_bt_cmd_connection_read_statistics_id 0x13060020 +#define sl_bt_cmd_connection_get_scheduling_details_id 0x14060020 +#define sl_bt_cmd_connection_close_id 0x05060020 +#define sl_bt_cmd_connection_forcefully_close_id 0x0f060020 +#define sl_bt_cmd_connection_get_rssi_id 0x02060020 +#define sl_bt_rsp_connection_set_default_parameters_id 0x00060020 +#define sl_bt_rsp_connection_set_default_preferred_phy_id 0x01060020 +#define sl_bt_rsp_connection_set_default_data_length_id 0x10060020 +#define sl_bt_rsp_connection_open_id 0x04060020 +#define sl_bt_rsp_connection_set_parameters_id 0x06060020 +#define sl_bt_rsp_connection_set_preferred_phy_id 0x08060020 +#define sl_bt_rsp_connection_disable_slave_latency_id 0x03060020 +#define sl_bt_rsp_connection_get_median_rssi_id 0x15060020 +#define sl_bt_rsp_connection_read_channel_map_id 0x07060020 +#define sl_bt_rsp_connection_set_power_reporting_id 0x09060020 +#define sl_bt_rsp_connection_set_remote_power_reporting_id 0x0a060020 +#define sl_bt_rsp_connection_get_tx_power_id 0x0b060020 +#define sl_bt_rsp_connection_get_remote_tx_power_id 0x0c060020 +#define sl_bt_rsp_connection_set_tx_power_id 0x12060020 +#define sl_bt_rsp_connection_read_remote_used_features_id 0x0d060020 +#define sl_bt_rsp_connection_get_security_status_id 0x0e060020 +#define sl_bt_rsp_connection_set_data_length_id 0x11060020 +#define sl_bt_rsp_connection_read_statistics_id 0x13060020 +#define sl_bt_rsp_connection_get_scheduling_details_id 0x14060020 +#define sl_bt_rsp_connection_close_id 0x05060020 +#define sl_bt_rsp_connection_forcefully_close_id 0x0f060020 +#define sl_bt_rsp_connection_get_rssi_id 0x02060020 + +/** + * @brief Types of device roles in a Bluetooth connection + */ +typedef enum +{ + sl_bt_connection_role_peripheral = 0x0, /**< (0x0) The Peripheral role */ + sl_bt_connection_role_central = 0x1 /**< (0x1) The Central role */ +} sl_bt_connection_role_t; + +/** + * @brief Indicate the Bluetooth Security Mode. + */ +typedef enum +{ + sl_bt_connection_mode1_level1 = 0x0, /**< (0x0) No security */ + sl_bt_connection_mode1_level2 = 0x1, /**< (0x1) Unauthenticated pairing with + encryption */ + sl_bt_connection_mode1_level3 = 0x2, /**< (0x2) Authenticated pairing with + encryption */ + sl_bt_connection_mode1_level4 = 0x3 /**< (0x3) Authenticated Secure + Connections pairing with encryption + using a 128-bit strength encryption + key */ +} sl_bt_connection_security_t; + +/** + * @brief These values define transmit power reporting modes in LE power + * control. + */ +typedef enum +{ + sl_bt_connection_power_reporting_disable = 0x0, /**< (0x0) Disable transmit + power reporting */ + sl_bt_connection_power_reporting_enable = 0x1 /**< (0x1) Enable transmit + power reporting */ +} sl_bt_connection_power_reporting_mode_t; + +/** + * @brief This enum defines the flag values for a reported transmit power level. + */ +typedef enum +{ + sl_bt_connection_tx_power_flag_none = 0x0, /**< (0x0) No flag is defined for + the reported TX power level */ + sl_bt_connection_tx_power_at_minimum = 0x1, /**< (0x1) Transmit power level is + at minimum level. */ + sl_bt_connection_tx_power_at_maximum = 0x2 /**< (0x2) Transmit power level is + at maximum level. */ +} sl_bt_connection_tx_power_flag_t; + +/** + * @addtogroup sl_bt_connection_rssi_const RSSI Value Constants + * @{ + * + * Constants for RSSI value + */ + +/** RSSI value is unavailable */ +#define SL_BT_CONNECTION_RSSI_UNAVAILABLE 0x7f + +/** @} */ // end RSSI Value Constants + +/** + * @addtogroup sl_bt_connection_tx_power_const Transmit Power Reporting Constants + * @{ + * + * Constants in transmit power reporting + */ + +/** Remote device is not managing power levels. */ +#define SL_BT_CONNECTION_TX_POWER_UNMANAGED 0x7e + +/** Transmit power level is not available. */ +#define SL_BT_CONNECTION_TX_POWER_UNAVAILABLE 0x7f + +/** Change is not available or is out of range. */ +#define SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE 0x7f + +/** @} */ // end Transmit Power Reporting Constants + +/** + * @addtogroup sl_bt_evt_connection_opened sl_bt_evt_connection_opened + * @{ + * @brief Indicates that a new connection was opened + * + * The specific semantics depend on the role of the device: + * - On the central device (parameter @p master set to @ref + * sl_bt_connection_role_central) the event is triggered when the Link Layer + * has sent a connect request to the remote device. + * - On the peripheral device (parameter @p master set to @ref + * sl_bt_connection_role_peripheral) the event is triggered when the Link + * Layer has responded to the connect request of the remote device. + * + * This event does not indicate the connection has been established (i.e., that + * a data packet was received within 6 connection intervals). If the connection + * is not established, an @ref sl_bt_evt_connection_closed event will + * immediately follow. + * + * An open connection can be closed with @ref sl_bt_connection_close command by + * giving the connection handle obtained from this event. + */ + +/** @brief Identifier of the opened event */ +#define sl_bt_evt_connection_opened_id 0x000600a0 + +/***************************************************************************//** + * @brief Data structure of the opened event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_opened_s +{ + bd_addr address; /**< Remote device address */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. Remote device + address type. Values: + - sl_bt_gap_public_address (0x0): Public + device address + - sl_bt_gap_static_address (0x1): Static + device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address resolved + from a resolvable private address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address resolved + from a resolvable private address (RPA) */ + uint8_t master; /**< Enum @ref sl_bt_connection_role_t. The role this + device operates in the connection. Values: + - sl_bt_connection_role_peripheral (0x0): + The Peripheral role + - sl_bt_connection_role_central (0x1): + The Central role */ + uint8_t connection; /**< Handle for new connection */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): No + bonding + - Other: Bonding handle */ + uint8_t advertiser; /**< The local advertising set that this connection was + opened to. Values: + - SL_BT_INVALID_ADVERTISING_SET_HANDLE + (0xff): Invalid value or not applicable. + Ignore this field + - Other: The advertising set handle */ + uint16_t sync; /**< The sync handle if the local device is in the + peripheral-role and the connection was opened via + a Periodic Advertising with Responses (PAwR) train + that the local device has synchronized to. Values: + - SL_BT_INVALID_SYNC_HANDLE (0xffff): The + connection was not opened over a PAwR train + that the local device is synchronized to + - Other: The sync handle for the PAwR + train that was used to open the connection */ +}); + +typedef struct sl_bt_evt_connection_opened_s sl_bt_evt_connection_opened_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_opened + +/** + * @addtogroup sl_bt_evt_connection_parameters sl_bt_evt_connection_parameters + * @{ + * @brief Triggered whenever the connection parameters are changed and at any + * time a connection is established + */ + +/** @brief Identifier of the parameters event */ +#define sl_bt_evt_connection_parameters_id 0x020600a0 + +/***************************************************************************//** + * @brief Data structure of the parameters event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_parameters_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t interval; /**< Connection interval. Time = Value x 1.25 ms */ + uint16_t latency; /**< Peripheral latency (how many connection intervals + the peripheral can skip) */ + uint16_t timeout; /**< Supervision timeout. Time = Value x 10 ms */ + uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection + security mode. Values: + - sl_bt_connection_mode1_level1 (0x0): + No security + - sl_bt_connection_mode1_level2 (0x1): + Unauthenticated pairing with encryption + - sl_bt_connection_mode1_level3 (0x2): + Authenticated pairing with encryption + - sl_bt_connection_mode1_level4 (0x3): + Authenticated Secure Connections pairing with + encryption using a 128-bit strength + encryption key */ + uint16_t txsize; /**< Deprecated and no longer used for + reporting the connection data length update. Use + the event @ref sl_bt_evt_connection_data_length + instead. */ +}); + +typedef struct sl_bt_evt_connection_parameters_s sl_bt_evt_connection_parameters_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_parameters + +/** + * @addtogroup sl_bt_evt_connection_set_parameters_failed sl_bt_evt_connection_set_parameters_failed + * @{ + * @brief Triggered when the peer device rejected an L2CAP connection parameter + * update request as a result of calling command @ref + * sl_bt_connection_set_parameters to change connection parameters on the @ref + * sl_bt_connection_role_peripheral role + */ + +/** @brief Identifier of the set_parameters_failed event */ +#define sl_bt_evt_connection_set_parameters_failed_id 0x100600a0 + +/***************************************************************************//** + * @brief Data structure of the set_parameters_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_set_parameters_failed_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_connection_set_parameters_failed_s sl_bt_evt_connection_set_parameters_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_set_parameters_failed + +/** + * @addtogroup sl_bt_evt_connection_phy_status sl_bt_evt_connection_phy_status + * @{ + * @brief Indicates that PHY update procedure is completed. + */ + +/** @brief Identifier of the phy_status event */ +#define sl_bt_evt_connection_phy_status_id 0x040600a0 + +/***************************************************************************//** + * @brief Data structure of the phy_status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_phy_status_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t phy; /**< Current active PHY. See values from @ref + sl_bt_connection_set_preferred_phy command. */ +}); + +typedef struct sl_bt_evt_connection_phy_status_s sl_bt_evt_connection_phy_status_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_phy_status + +/** + * @addtogroup sl_bt_evt_connection_get_remote_tx_power_completed sl_bt_evt_connection_get_remote_tx_power_completed + * @{ + * @brief Indicates that reading remote transmit power initiated by @ref + * sl_bt_connection_get_remote_tx_power command has completed + */ + +/** @brief Identifier of the get_remote_tx_power_completed event */ +#define sl_bt_evt_connection_get_remote_tx_power_completed_id 0x050600a0 + +/***************************************************************************//** + * @brief Data structure of the get_remote_tx_power_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_get_remote_tx_power_completed_s +{ + uint16_t status; /**< SL_STATUS_OK or another error code indicating the + reading remote transmit power operation failed. */ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY for which + the transmit power is reported. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): + 1M PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): + 2M PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED + (0x7E): Remote device is not managing power + levels on this PHY. + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. + Transmit power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out + of range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_get_remote_tx_power_completed_s sl_bt_evt_connection_get_remote_tx_power_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_get_remote_tx_power_completed + +/** + * @addtogroup sl_bt_evt_connection_tx_power sl_bt_evt_connection_tx_power + * @{ + * @brief Reports a transmit power change on the local device of a connection if + * transmit power reporting has been enabled + * + * Enable or disable transmit power reporting using @ref + * sl_bt_connection_set_power_reporting command. Local transmit power reporting + * is enabled by default for new connections. + * + * When enabled, local transmit power change events may get triggered in the + * following situations: + * - When the connection has just opened and the initial transmit power is set + * - When the application explicitly changes the system TX power using the + * @ref sl_bt_system_set_tx_power command + * - When the bluetooth_feature_power_control component is included and + * enabled in the application and the local transmit power is adjusted by + * the power control feature + * - When the bluetooth_feature_afh component for Adaptive Frequency Hopping + * is included and enabled in the application and the local transmit power + * is adjusted due to changes in the availability of good channels. + */ + +/** @brief Identifier of the tx_power event */ +#define sl_bt_evt_connection_tx_power_id 0x060600a0 + +/***************************************************************************//** + * @brief Data structure of the tx_power event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_tx_power_s +{ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the + transmit power is reported for. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M + PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M + PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit + power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out of + range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_tx_power_s sl_bt_evt_connection_tx_power_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_tx_power + +/** + * @addtogroup sl_bt_evt_connection_remote_tx_power sl_bt_evt_connection_remote_tx_power + * @{ + * @brief Reports a transmit power change of the connection on the remote device + * that supports the LE Power Control for the connection + * + * This event is enabled if reporting the remote transmit power change has been + * enabled with the @ref sl_bt_connection_set_remote_power_reporting command. + */ + +/** @brief Identifier of the remote_tx_power event */ +#define sl_bt_evt_connection_remote_tx_power_id 0x070600a0 + +/***************************************************************************//** + * @brief Data structure of the remote_tx_power event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_remote_tx_power_s +{ + uint8_t connection; /**< Handle of the connection */ + uint8_t phy; /**< Enum @ref sl_bt_gap_phy_coding_t. The PHY which the + transmit power is reported for. Values: + - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M + PHY + - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M + PHY + - sl_bt_gap_phy_coding_125k_coded (0x4): + 125k Coded PHY (S=8) + - sl_bt_gap_phy_coding_500k_coded (0x8): + 500k Coded PHY (S=2) */ + int8_t power_level; /**< Transmit power level. Values: + - Range -127 to 20: The transmit power + level in dBm + - @ref SL_BT_CONNECTION_TX_POWER_UNMANAGED + (0x7E): Remote device is not managing power + levels on this PHY. + - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE + (0x7F): Transmit power level is not + available. */ + uint8_t flags; /**< Enum @ref sl_bt_connection_tx_power_flag_t. Transmit + power level flags. Ignore this field if @p + power_level is set to 0x7E or 0x7F. Values: + - sl_bt_connection_tx_power_flag_none + (0x0): No flag is defined for the reported + TX power level + - sl_bt_connection_tx_power_at_minimum + (0x1): Transmit power level is at minimum + level. + - sl_bt_connection_tx_power_at_maximum + (0x2): Transmit power level is at maximum + level. */ + int8_t delta; /**< Change in transmit power level. Values: + - @ref + SL_BT_CONNECTION_TX_POWER_CHANGE_UNAVAILABLE + (0x7F): Change is not available or is out of + range. + - Other values: positive indicates + increased power, negative indicates decreased + power, and zero indicates unchanged. Units: dB */ +}); + +typedef struct sl_bt_evt_connection_remote_tx_power_s sl_bt_evt_connection_remote_tx_power_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_remote_tx_power + +/** + * @addtogroup sl_bt_evt_connection_remote_used_features sl_bt_evt_connection_remote_used_features + * @{ + * @brief List of link layer features supported by the remote device. + */ + +/** @brief Identifier of the remote_used_features event */ +#define sl_bt_evt_connection_remote_used_features_id 0x080600a0 + +/***************************************************************************//** + * @brief Data structure of the remote_used_features event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_remote_used_features_s +{ + uint8_t connection; /**< Connection handle */ + uint8array features; /**< This parameter is 8 bytes in little endian format + and contains bit fields describing the supported + link layer features of the remote device. Bit + value 1 means that the feature is supported. + + The bits are explained in Bluetooth specification + Vol 6, Part B, 4.6. */ +}); + +typedef struct sl_bt_evt_connection_remote_used_features_s sl_bt_evt_connection_remote_used_features_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_remote_used_features + +/** + * @addtogroup sl_bt_evt_connection_data_length sl_bt_evt_connection_data_length + * @{ + * @brief Reports a change to the maximum payload length or maximum TX time in + * either direction of a connection. + */ + +/** @brief Identifier of the data_length event */ +#define sl_bt_evt_connection_data_length_id 0x090600a0 + +/***************************************************************************//** + * @brief Data structure of the data_length event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_data_length_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t tx_data_len; /**< The maximum payload octets of a packet that the + local Controller will send */ + uint16_t tx_time_us; /**< The maximum time in microseconds that the local + Controller will take to send a data packet */ + uint16_t rx_data_len; /**< The maximum payload octets of a packet that the + local Controller expects to receive */ + uint16_t rx_time_us; /**< The maximum time in microseconds that the local + Controller expects to take to receive a data packet */ +}); + +typedef struct sl_bt_evt_connection_data_length_s sl_bt_evt_connection_data_length_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_data_length + +/** + * @addtogroup sl_bt_evt_connection_statistics sl_bt_evt_connection_statistics + * @{ + * @brief Provides the connection statistic values when the application includes + * the component bluetooth_feature_connection_statistics + * + * When the component is included by the application, this event is + * automatically triggered to provide the final statistics for the connection + * just before the @ref sl_bt_evt_connection_closed event indicates that a + * connection has been closed. This event is also triggered when the application + * has requested reading the statistics using the command @ref + * sl_bt_connection_read_statistics. + */ + +/** @brief Identifier of the statistics event */ +#define sl_bt_evt_connection_statistics_id 0x0a0600a0 + +/***************************************************************************//** + * @brief Data structure of the statistics event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_statistics_s +{ + uint8_t connection; /**< Handle of the connection */ + int8_t rssi_min; /**< The minimum Received Signal + Strength Indicator (RSSI) + value measured for packets + that have been successfully + received on this connection. + Units: dBm + - Valid value range: -127 to + +20 + - Value 127: information + unavailable */ + int8_t rssi_max; /**< The maximum Received Signal + Strength Indicator (RSSI) + value measured for packets + that have been successfully + received on this connection. + Units: dBm + - Valid value range: -127 to + +20 + - Value 127: information + unavailable */ + uint32_t num_total_connection_events; /**< The total number of connection + events that would have + occurred on this connection if + no packets were lost. This + count therefore includes also + connection events that were + missed due to errors (see @p + num_missed_connection_events). + In the Peripheral device this + count does not include + connection events where the + Peripheral deliberately did + not listen due to Peripheral + latency. */ + uint32_t num_missed_connection_events; /**< The number of connection + events that have been missed + on this connection. This + includes connection events + where the first packet of a + connection event was either + not received at all or was + corrupted so that it was not + recognized as belonging to + this connection. */ + uint32_t num_successful_connection_events; /**< The number of connection + events that have occured on + this connection without + errors. */ + uint32_t num_crc_errors; /**< The number of packets that + have been received on this + connection with a Cyclic + Redundancy Check (CRC) error. */ +}); + +typedef struct sl_bt_evt_connection_statistics_s sl_bt_evt_connection_statistics_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_statistics + +/** + * @addtogroup sl_bt_evt_connection_closed sl_bt_evt_connection_closed + * @{ + * @brief Indicates that a connection was either closed or that no connection + * was established from a high duty cycle directed advertising. + * + * If the application includes the component + * bluetooth_feature_connection_statistics and the connection was successfully + * opened, the event @ref sl_bt_evt_connection_statistics is automatically + * triggered just before the connection closed event to provide the application + * with the final statistic values of the connection. + */ + +/** @brief Identifier of the closed event */ +#define sl_bt_evt_connection_closed_id 0x010600a0 + +/***************************************************************************//** + * @brief Data structure of the closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_closed_s +{ + uint16_t reason; /**< Reason of connection close. + + Error code SL_STATUS_BT_CTRL_ADVERTISING_TIMEOUT + indicates that the high duty cycle directed + advertising timed out and no connection was + established. Ignore the value of @p connection in + this case. */ + uint8_t connection; /**< Handle of the closed connection */ +}); + +typedef struct sl_bt_evt_connection_closed_s sl_bt_evt_connection_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_closed + +/** + * @addtogroup sl_bt_evt_connection_rssi sl_bt_evt_connection_rssi + * @{ + * @brief Triggered when a @ref sl_bt_connection_get_rssi command has completed + * + * This event is only used by deprecated @ref sl_bt_connection_get_rssi that + * returns the RSSI value asynchronously. + * + * Use the @ref sl_bt_connection_get_median_rssi command to get the RSSI + * synchronously. + */ + +/** @brief Identifier of the rssi event */ +#define sl_bt_evt_connection_rssi_id 0x030600a0 + +/***************************************************************************//** + * @brief Data structure of the rssi event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_rssi_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t status; /**< Command complete status which is always SL_STATUS_OK */ + int8_t rssi; /**< The median of the last seven measured RSSI values on + the connection. Units: dBm. Range: -127 to +20. */ +}); + +typedef struct sl_bt_evt_connection_rssi_s sl_bt_evt_connection_rssi_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_rssi + +/***************************************************************************//** + * + * Set default Bluetooth connection parameters. The values are valid for all + * subsequent connections initiated by this device. + * + * @p min_ce_length and @p max_ce_length specify the preference of the + * connection event length so that the Link Layer can prioritize tasks + * accordingly in simultaneous connections, or scanning and so on. A connection + * event starts at an anchor point of a connection interval and lasts until the + * lesser of @p max_ce_length and the actual connection interval. Packets that + * do not fit into the connection event will be sent in the next connection + * interval. + * + * To change parameters of an already established connection, use the command + * @ref sl_bt_connection_set_parameters. + * + * @param[in] min_interval @parblock + * Minimum value for the connection event interval. This must be set less than + * or equal to @p max_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * + * Default value: 20 ms + * @endparblock + * @param[in] max_interval @parblock + * Maximum value for the connection event interval. This must be set greater + * than or equal to @p min_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * + * Default value: 50 ms + * @endparblock + * @param[in] latency @parblock + * Peripheral latency, which defines how many connection intervals the + * peripheral can skip if it has no data to send + * - Range: 0x0000 to 0x01f3 + * + * Default value: 0 + * @endparblock + * @param[in] timeout @parblock + * Supervision timeout, which defines the time that the connection is + * maintained although the devices can't communicate at the currently + * configured connection intervals. + * - Range: 0x000a to 0x0c80 + * - Time = Value x 10 ms + * - Time Range: 100 ms to 32 s + * - The value in milliseconds must be larger than (1 + @p latency) * @p + * max_interval * 2, where @p max_interval is given in milliseconds + * + * Set the supervision timeout at a value which allows communication attempts + * over at least a few connection intervals. + * + * Default value: 1000 ms + * @endparblock + * @param[in] min_ce_length @parblock + * Minimum length of the connection event. It must be less than or equal to @p + * max_ce_length. + * + * This value defines the minimum time that should be given to the connection + * event in a situation where other tasks need to run immediately after the + * connection event. When the value is very small, the connection event still + * has at least one TX/RX operation. If this value is increased, more time is + * reserved for the connection event so it can transmit and receive more + * packets in a connection interval. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0x0000 + * @endparblock + * @param[in] max_ce_length @parblock + * Maximum length of the connection event. It must be greater than or equal to + * @p min_ce_length. + * + * This value is used for limiting the connection event length so that a + * connection that has large amounts of data to transmit or receive doesn't + * block other tasks. Limiting the connection event is a hard stop. If there + * is no enough time to send or receive a packet, the connection event will be + * closed. + * + * If the value is set to 0, the connection event still has at least one TX/RX + * operation. This is useful to limit power consumption or leave more time to + * other tasks. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0xffff + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_parameters(uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length); + +/***************************************************************************//** + * + * Set default preferred and accepted PHYs. PHY settings will be used for all + * subsequent connections. Non-preferred PHY can also be set if the remote + * device does not accept any of the preferred PHYs. + * + * The parameter @p accepted_phy is used to specify PHYs that the stack can + * accept in a remotely-initiated PHY update request. A PHY update will not + * happen if none of the accepted PHYs are present in the request. + * + * NOTE: 2M and Coded PHYs are not supported by all devices. + * + * @param[in] preferred_phy @parblock + * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (no preference) + * @endparblock + * @param[in] accepted_phy @parblock + * Accepted PHYs in remotely-initiated PHY update request. This parameter is a + * bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (all PHYs accepted) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_preferred_phy(uint8_t preferred_phy, + uint8_t accepted_phy); + +/***************************************************************************//** + * + * Set the default preferred maximum TX payload length to be used for new + * connections. + * + * When a connection is open, the maximum TX payload length is 27. Either device + * could initiate a data length update procedure and event @ref + * sl_bt_evt_connection_data_length is generated when the data length has been + * changed on the connection. + * + * @param[in] tx_data_len @parblock + * Preferred maximum payload octets of a packet that the local Controller will + * send + * + * Range: Range: 27 (0x1B) to 251 (0xFB) + * + * Default: 251 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_default_data_length(uint16_t tx_data_len); + +/***************************************************************************//** + * + * Connect to an advertising device with the specified initiating PHY on which + * connectable advertisements on primary advertising channels are received. The + * Bluetooth stack will enter a state where it continuously scans for the + * connectable advertising packets from the remote device, which matches the + * Bluetooth address given as a parameter. Scan parameters set in @ref + * sl_bt_scanner_set_timing are used in this operation. Upon receiving the + * advertising packet, the module will send a connection request packet to the + * target device to initiate a Bluetooth connection. To cancel an ongoing + * connection process, use @ref sl_bt_connection_close command with the handle + * received in response from this command. + * + * A connection is opened in no-security mode. If the GATT client needs to read + * or write the attributes on GATT server requiring encryption or + * authentication, it must first encrypt the connection using an appropriate + * authentication method. + * + * If a connection can't be established, for example, the remote device has gone + * out of range, has entered into deep sleep, or is not advertising, the stack + * will try to connect forever. In this case, the application will not get an + * event related to the connection request. To recover from this situation, the + * application can implement a timeout and call @ref sl_bt_connection_close to + * cancel the connection request. + * + * This command fails with the connection limit exceeded error if the number of + * connections attempted exceeds the configured MAX_CONNECTIONS value. + * + * This command fails with the invalid parameter error if the initiating PHY + * value is invalid or the device does not support PHY. + * + * Subsequent calls of this command have to wait for the ongoing command to + * complete. A received event @ref sl_bt_evt_connection_opened indicates that + * the connection opened successfully and a received event @ref + * sl_bt_evt_connection_closed indicates that connection failures have occurred. + * + * @param[in] address Address of the device to connect to + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device to connect to. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_random_resolvable_address (0x2): Resolvable private + * random address + * - sl_bt_gap_random_nonresolvable_address (0x3): Non-resolvable + * private random address + * - sl_bt_gap_public_address_resolved_from_rpa (0x4): Public + * identity address resolved from a resolvable private address (RPA) + * - sl_bt_gap_static_address_resolved_from_rpa (0x5): Static + * identity address resolved from a resolvable private address (RPA) + * @param[in] initiating_phy Enum @ref sl_bt_gap_phy_t. The initiating PHY. + * Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] connection Handle that will be assigned to the connection after + * the connection is established. This handle is valid only if the result code + * of this response is 0 (zero). + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_opened - This event is triggered after the + * connection is opened and indicates whether the devices are already bonded + * and the role of the device in this connection. + * - @ref sl_bt_evt_connection_parameters - This event indicates the + * connection parameters and security mode of the connection. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_open(bd_addr address, + uint8_t address_type, + uint8_t initiating_phy, + uint8_t *connection); + +/***************************************************************************//** + * + * Request a change in the connection parameters of a Bluetooth connection. + * - On the central device the HCI LE Connection Update command is used to + * update the parameters. + * - On the peripheral device an L2CAP connection parameter update request is + * sent to the peer device to update the parameters. + * + * @p min_ce_length and @p max_ce_length specify the preference of the + * connection event length so that the Link Layer can prioritize tasks + * accordingly in simultaneous connections, or scanning and so on. A connection + * event starts at an anchor point of a connection interval and lasts until the + * lesser of @p max_ce_length and the actual connection interval. Packets that + * do not fit into the connection event will be sent in the next connection + * interval. + * + * @param[in] connection Connection Handle + * @param[in] min_interval Minimum value for the connection event interval. This + * must be set less than or equal to @p max_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * @param[in] max_interval Maximum value for the connection event interval. This + * must be set greater than or equal to @p min_interval. + * - Time = Value x 1.25 ms + * - Range: 0x0006 to 0x0c80 + * - Time Range: 7.5 ms to 4 s + * @param[in] latency Peripheral latency, which defines how many connection + * intervals the peripheral can skip if it has no data to send + * - Range: 0x0000 to 0x01f3 + * @param[in] timeout @parblock + * Supervision timeout, which defines the time that the connection is + * maintained although the devices can't communicate at the currently + * configured connection intervals. + * - Range: 0x000a to 0x0c80 + * - Time = Value x 10 ms + * - Time Range: 100 ms to 32 s + * - The value in milliseconds must be larger than (1 + @p latency) * @p + * max_interval * 2, where @p max_interval is given in milliseconds + * + * Set the supervision timeout at a value which allows communication attempts + * over at least a few connection intervals. + * @endparblock + * @param[in] min_ce_length @parblock + * Minimum length of the connection event. It must be less than or equal to @p + * max_ce_length. + * + * This value defines the minimum time that should be given to the connection + * event in a situation where other tasks need to run immediately after the + * connection event. When the value is very small, the connection event still + * has at least one TX/RX operation. If this value is increased, more time is + * reserved for the connection event so it can transmit and receive more + * packets in a connection interval. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0x0000 + * @endparblock + * @param[in] max_ce_length @parblock + * Maximum length of the connection event. It must be greater than or equal to + * @p min_ce_length. + * + * This value is used for limiting the connection event length so that a + * connection that has large amounts of data to transmit or receive doesn't + * block other tasks. Limiting the connection event is a hard stop. If there + * is no enough time to send or receive a packet, the connection event will be + * closed. + * + * If the value is set to 0, the connection event still has at least one TX/RX + * operation. This is useful to limit power consumption or leave more time to + * other tasks. + * + * Use the default value if the application doesn't care about the connection + * event length or doesn't want to do fine tuning. + * - Time = Value x 0.625 ms + * - Range: 0x0000 to 0xffff + * + * Default value: 0xffff + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_parameters - Triggered after new connection + * parameters are applied on the connection. + * - @ref sl_bt_evt_connection_set_parameters_failed - Triggered when the peer + * device rejected an L2CAP connection parameter update request. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_parameters(uint8_t connection, + uint16_t min_interval, + uint16_t max_interval, + uint16_t latency, + uint16_t timeout, + uint16_t min_ce_length, + uint16_t max_ce_length); + +/***************************************************************************//** + * + * Set preferred and accepted PHYs for a given connection. Event @ref + * sl_bt_evt_connection_phy_status is received when PHY update procedure is + * completed. Non-preferred PHY can also be set if remote device does not accept + * any of the preferred PHYs. + * + * The parameter @p accepted_phy is used for specifying the PHYs that the stack + * can accept in a remote initiated PHY update request. A PHY update will not + * occur if none of the accepted PHYs presents in the request. + * + * NOTE: 2M and Coded PHYs are not supported by all devices. + * + * @param[in] connection Connection handle + * @param[in] preferred_phy @parblock + * Preferred PHYs. This parameter is a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: 125k Coded PHY (S=8) + * - 0x08: 500k Coded PHY (S=2) + * + * Default: 0xff (no preference) + * @endparblock + * @param[in] accepted_phy @parblock + * Accepted PHYs in remotely-initiated PHY update requests. This parameter is + * a bitfield and multiple PHYs can be set. + * - 0x01: 1M PHY + * - 0x02: 2M PHY + * - 0x04: Coded PHY + * - 0xff: Any PHYs + * + * Default: 0xff (all PHYs accepted) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_phy_status + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_preferred_phy(uint8_t connection, + uint8_t preferred_phy, + uint8_t accepted_phy); + +/***************************************************************************//** + * + * Temporarily enable or disable peripheral latency. Used only when Bluetooth + * device is acting as a peripheral. When peripheral latency is disabled, the + * peripheral latency connection parameter is not set to 0 but the device will + * wake up on every connection interval to receive and send packets. + * + * @param[in] connection Connection Handle + * @param[in] disable 0 enable, 1 disable peripheral latency. Default: 0 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_disable_slave_latency(uint8_t connection, + uint8_t disable); + +/***************************************************************************//** + * + * Get the RSSI value measured on a connection. + * + * @param[in] connection Connection handle + * @param[out] rssi The median of the last seven measured RSSI values. Units: + * dBm. Range: -127 to +20. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_median_rssi(uint8_t connection, int8_t *rssi); + +/***************************************************************************//** + * + * Read channel map for a specified connection. + * + * @param[in] connection Connection Handle + * @param[in] max_channel_map_size Size of output buffer passed in @p + * channel_map + * @param[out] channel_map_len On return, set to the length of output data + * written to @p channel_map + * @param[out] channel_map @parblock + * This parameter is 5 bytes and contains 37 1-bit fields. + * + * The nth field (in the range 0 to 36) contains the value for the link layer + * channel index n. + * + * - 0: Channel n is unused. + * - 1: Channel n is used. + * + * The most significant bits are reserved for future use. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_channel_map(uint8_t connection, + size_t max_channel_map_size, + size_t *channel_map_len, + uint8_t *channel_map); + +/***************************************************************************//** + * + * Enable or disable the transmit power reporting for the local device on a + * connection. When transmit power reporting is enabled, event @ref + * sl_bt_evt_connection_tx_power is generated when transmit power on the local + * device changes. + * + * The command is a built-in feature in the stack and is supported regardless of + * whether the LE Power Control feature is used. By default, power reporting for + * local device is enabled. + * + * @param[in] connection Handle of the connection + * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit + * power reporting mode. Values: + * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit + * power reporting + * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit + * power reporting + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_tx_power + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_power_reporting(uint8_t connection, + uint8_t mode); + +/***************************************************************************//** + * + * Enable or disable reporting the transmit power change on the remote device. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. + * + * When the remote transmit power reporting is enabled, event @ref + * sl_bt_evt_connection_remote_tx_power is generated when transmit power on the + * remote device changes. + * + * By default, power reporting for the remote device is disabled. + * + * @param[in] connection Handle of the connection + * @param[in] mode Enum @ref sl_bt_connection_power_reporting_mode_t. Transmit + * power reporting mode. Values: + * - sl_bt_connection_power_reporting_disable (0x0): Disable transmit + * power reporting + * - sl_bt_connection_power_reporting_enable (0x1): Enable transmit + * power reporting + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_remote_tx_power + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_remote_power_reporting(uint8_t connection, + uint8_t mode); + +/***************************************************************************//** + * + * Get the transmit power of the local device on the given connection and PHY. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. + * + * @param[in] connection Handle of the connection + * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: + * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY + * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY + * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) + * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) + * @param[out] current_level The current transmit power level of the PHY on the + * connection. Values: + * - Range -127 to 20: The transmit power level in dBm + * - @ref SL_BT_CONNECTION_TX_POWER_UNAVAILABLE (0x7F): Transmit + * power level is not available. + * @param[out] max_level The maximum transmit power level of the PHY on the + * connection. Values: Range -127 to +20 in dBm. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_tx_power(uint8_t connection, + uint8_t phy, + int8_t *current_level, + int8_t *max_level); + +/***************************************************************************//** + * + * Get the transmit power of the remote device on the given connection and PHY. + * The application must include the LE Power Control feature + * (bluetooth_feature_power_control) in order to use this command. Transmit + * power levels are returned in event @ref + * sl_bt_evt_connection_get_remote_tx_power_completed after the operation + * completed. + * + * @param[in] connection Handle of the connection + * @param[in] phy Enum @ref sl_bt_gap_phy_coding_t. The PHY. Values: + * - sl_bt_gap_phy_coding_1m_uncoded (0x1): 1M PHY + * - sl_bt_gap_phy_coding_2m_uncoded (0x2): 2M PHY + * - sl_bt_gap_phy_coding_125k_coded (0x4): 125k Coded PHY (S=8) + * - sl_bt_gap_phy_coding_500k_coded (0x8): 500k Coded PHY (S=2) + * + * @return SL_STATUS_OK if the command is accepted. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_get_remote_tx_power_completed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_remote_tx_power(uint8_t connection, + uint8_t phy); + +/***************************************************************************//** + * + * Set the transmit power of a connection. The application must include + * component bluetooth_feature_user_power_control in order to use this command + * for controlling the transmit power of the connection at application level. + * This command is unavailable if the standard Bluetooth feature LE power + * control (component bluetooth_feature_power_control) is used by the + * application. + * + * The actual selected power level is returned from this command. The value may + * be different than the requested one because of Bluetooth feature restrictions + * or radio characteristics. + * + * @param[in] connection The connection handle + * @param[in] tx_power The requested TX power. Unit: 0.1 dBm + * @param[out] tx_power_out The selected TX power. Unit: 0.1 dBm + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_tx_power(uint8_t connection, + int16_t tx_power, + int16_t *tx_power_out); + +/***************************************************************************//** + * + * Read link layer features supported by the remote device. + * + * @param[in] connection Connection Handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_remote_used_features + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_remote_used_features(uint8_t connection); + +/***************************************************************************//** + * + * Get the security status of the connection. + * + * @param[in] connection Connection handle + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size The size of encryption key + * @param[out] bonding_handle Bonding handle. Values: + * - SL_BT_INVALID_BONDING_HANDLE (0xff): No bonding + * - Other: Bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_security_status(uint8_t connection, + uint8_t *security_mode, + uint8_t *key_size, + uint8_t *bonding_handle); + +/***************************************************************************//** + * + * Request to update the maximum TX payload length and maximum packet TX time of + * a Bluetooth connection. + * + * Event @ref sl_bt_evt_connection_data_length is generated when the data length + * has been changed on the connection. + * + * @param[in] connection Connection handle + * @param[in] tx_data_len @parblock + * Preferred maximum payload octets of a packet that the local Controller will + * send + * + * Range: 27 (0x1B) to 251 (0xFB) + * @endparblock + * @param[in] tx_time_us @parblock + * Preferred maximum TX time in microseconds that the local Controller will + * take to send a packet + * + * Range: 328 (0x0148) to 17040 (0x4290) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_data_length + * + ******************************************************************************/ +sl_status_t sl_bt_connection_set_data_length(uint8_t connection, + uint16_t tx_data_len, + uint16_t tx_time_us); + +/***************************************************************************//** + * + * Read the statistic values collected on the specified connection. The + * application must include component bluetooth_feature_connection_statistics in + * order to use this command. If the component is not included in the + * application this command returns the error SL_STATUS_NOT_AVAILABLE. If this + * command is called before the connection has opened, the command returns the + * error SL_STATUS_NOT_READY. + * + * @param[in] connection The connection handle + * @param[in] reset Reset statistics if parameter value is not zero + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_statistics - Triggered to deliver the statistic + * values of the connection at the time the command was issued. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_read_statistics(uint8_t connection, uint8_t reset); + +/***************************************************************************//** + * + * Get parameters and next connection event scheduling details of a connection. + * Returned values from this command provide the necessary information for + * following the packet transmissions of the connection on an external device. + * Note that the stack cannot ensure a determined timing latency from the time + * when issuing this command to the time when another device starts to follow + * the connection, and the stack cannot guarantee that a scheduled connection + * event will always happen. + * + * @param[in] connection Connection handle + * @param[out] access_address Access address of the connection + * @param[out] role Enum @ref sl_bt_connection_role_t. The role the local device + * operates in the connection. Values: + * - sl_bt_connection_role_peripheral (0x0): The Peripheral role + * - sl_bt_connection_role_central (0x1): The Central role + * @param[out] crc_init The CRC initialization value + * @param[out] interval The connection interval. Time = Value x 1.25 ms + * @param[out] supervision_timeout The connection supervision time. Time = Value + * x 10 ms + * @param[out] central_clock_accuracy The central device's clock accuracy index + * value + * @param[out] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central + * device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the + * Peripheral device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[out] channel_selection_algorithm Enum @ref + * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. + * Values: + * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection + * algorithm #1 + * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection + * algorithm #2 + * @param[out] hop The hop increment when the channel selection algorithm #1 is + * used on the connection. Ignore if @p channel_selection_algorithm indicates + * that the connection uses channel selection algorithm #2. + * @param[out] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Ignore bits 37-39 that are reserved for future use. + * + * A channel is unused when its bit is 0. A channel is used when its bit is 1. + * @endparblock + * @param[out] channel The data channel number that transmissions will use in + * the next connection event + * @param[out] event_counter The event counter of the next connection event + * @param[out] start_time_us Time in microseconds from the PROTIMER tick when + * the next connection event is scheduled to happen + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_get_scheduling_details(uint8_t connection, + uint32_t *access_address, + uint8_t *role, + uint32_t *crc_init, + uint16_t *interval, + uint16_t *supervision_timeout, + uint8_t *central_clock_accuracy, + uint8_t *central_phy, + uint8_t *peripheral_phy, + uint8_t *channel_selection_algorithm, + uint8_t *hop, + sl_bt_connection_channel_map_t *channel_map, + uint8_t *channel, + uint16_t *event_counter, + uint32_t *start_time_us); + +/***************************************************************************//** + * + * Close a Bluetooth connection gracefully by performing the ACL Termination + * procedure or cancel an ongoing connection establishment process. The + * parameter is a connection handle which is reported in @ref + * sl_bt_evt_connection_opened event or @ref sl_bt_connection_open command + * response. + * + * Disconnecting a connection is an asynchronous operation. The disconnection is + * completed when a @ref sl_bt_evt_connection_closed event for the given + * connection handle is received. To open a new connection to the same remote + * device, wait for the @ref sl_bt_evt_connection_closed event and then initiate + * the connection. + * + * @param[in] connection Handle of the connection to be closed + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_close(uint8_t connection); + +/***************************************************************************//** + * + * Forcefully close a Bluetooth connection without performing the ACL + * Termination procedure. The parameter is a connection handle which is reported + * in @ref sl_bt_evt_connection_opened event or @ref sl_bt_connection_open + * command response. + * + * Closing a connection using this command could result in the observation of + * connection loss or supervision timeout on the remote device. Only use this + * command for special cases, for example, when disconnecting a connection with + * @ref sl_bt_connection_close did not complete in expected time period. + * + * @param[in] connection Handle of the connection to be closed + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_closed + * + ******************************************************************************/ +sl_status_t sl_bt_connection_forcefully_close(uint8_t connection); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref sl_bt_connection_get_median_rssi which + * synchronously returns the value. + * + * Get the latest RSSI value of a Bluetooth connection. The RSSI value will be + * reported in a @ref sl_bt_evt_connection_rssi event if the command returns + * SL_STATUS_OK. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_rssi - Triggered when this command has + * completed. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_connection_get_rssi(uint8_t connection); + +/** @} */ // end addtogroup sl_bt_connection + +/** + * @addtogroup sl_bt_gatt GATT Client + * @{ + * + * @brief GATT Client + * + * The commands and events in this class are used to browse and manage + * attributes in a remote GATT server. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gatt_set_max_mtu_id 0x00090020 +#define sl_bt_cmd_gatt_discover_primary_services_id 0x01090020 +#define sl_bt_cmd_gatt_discover_primary_services_by_uuid_id 0x02090020 +#define sl_bt_cmd_gatt_find_included_services_id 0x10090020 +#define sl_bt_cmd_gatt_discover_characteristics_id 0x03090020 +#define sl_bt_cmd_gatt_discover_characteristics_by_uuid_id 0x04090020 +#define sl_bt_cmd_gatt_discover_descriptors_id 0x06090020 +#define sl_bt_cmd_gatt_discover_characteristic_descriptors_id 0x14090020 +#define sl_bt_cmd_gatt_set_characteristic_notification_id 0x05090020 +#define sl_bt_cmd_gatt_send_characteristic_confirmation_id 0x0d090020 +#define sl_bt_cmd_gatt_read_characteristic_value_id 0x07090020 +#define sl_bt_cmd_gatt_read_characteristic_value_from_offset_id 0x12090020 +#define sl_bt_cmd_gatt_read_multiple_characteristic_values_id 0x11090020 +#define sl_bt_cmd_gatt_read_characteristic_value_by_uuid_id 0x08090020 +#define sl_bt_cmd_gatt_write_characteristic_value_id 0x09090020 +#define sl_bt_cmd_gatt_write_characteristic_value_without_response_id 0x0a090020 +#define sl_bt_cmd_gatt_prepare_characteristic_value_write_id 0x0b090020 +#define sl_bt_cmd_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 +#define sl_bt_cmd_gatt_execute_characteristic_value_write_id 0x0c090020 +#define sl_bt_cmd_gatt_read_descriptor_value_id 0x0e090020 +#define sl_bt_cmd_gatt_write_descriptor_value_id 0x0f090020 +#define sl_bt_rsp_gatt_set_max_mtu_id 0x00090020 +#define sl_bt_rsp_gatt_discover_primary_services_id 0x01090020 +#define sl_bt_rsp_gatt_discover_primary_services_by_uuid_id 0x02090020 +#define sl_bt_rsp_gatt_find_included_services_id 0x10090020 +#define sl_bt_rsp_gatt_discover_characteristics_id 0x03090020 +#define sl_bt_rsp_gatt_discover_characteristics_by_uuid_id 0x04090020 +#define sl_bt_rsp_gatt_discover_descriptors_id 0x06090020 +#define sl_bt_rsp_gatt_discover_characteristic_descriptors_id 0x14090020 +#define sl_bt_rsp_gatt_set_characteristic_notification_id 0x05090020 +#define sl_bt_rsp_gatt_send_characteristic_confirmation_id 0x0d090020 +#define sl_bt_rsp_gatt_read_characteristic_value_id 0x07090020 +#define sl_bt_rsp_gatt_read_characteristic_value_from_offset_id 0x12090020 +#define sl_bt_rsp_gatt_read_multiple_characteristic_values_id 0x11090020 +#define sl_bt_rsp_gatt_read_characteristic_value_by_uuid_id 0x08090020 +#define sl_bt_rsp_gatt_write_characteristic_value_id 0x09090020 +#define sl_bt_rsp_gatt_write_characteristic_value_without_response_id 0x0a090020 +#define sl_bt_rsp_gatt_prepare_characteristic_value_write_id 0x0b090020 +#define sl_bt_rsp_gatt_prepare_characteristic_value_reliable_write_id 0x13090020 +#define sl_bt_rsp_gatt_execute_characteristic_value_write_id 0x0c090020 +#define sl_bt_rsp_gatt_read_descriptor_value_id 0x0e090020 +#define sl_bt_rsp_gatt_write_descriptor_value_id 0x0f090020 + +/** + * @brief These values indicate which attribute request or response has caused + * the event. + */ +typedef enum +{ + sl_bt_gatt_read_by_type_request = 0x8, /**< (0x8) Read by type request */ + sl_bt_gatt_read_by_type_response = 0x9, /**< (0x9) Read by type response */ + sl_bt_gatt_read_request = 0xa, /**< (0xa) Read request */ + sl_bt_gatt_read_response = 0xb, /**< (0xb) Read response */ + sl_bt_gatt_read_blob_request = 0xc, /**< (0xc) Read blob request */ + sl_bt_gatt_read_blob_response = 0xd, /**< (0xd) Read blob response */ + sl_bt_gatt_read_multiple_request = 0xe, /**< (0xe) Read multiple request */ + sl_bt_gatt_read_multiple_response = 0xf, /**< (0xf) Read multiple response */ + sl_bt_gatt_write_request = 0x12, /**< (0x12) Write request */ + sl_bt_gatt_write_response = 0x13, /**< (0x13) Write response */ + sl_bt_gatt_write_command = 0x52, /**< (0x52) Write command */ + sl_bt_gatt_prepare_write_request = 0x16, /**< (0x16) Prepare write request */ + sl_bt_gatt_prepare_write_response = 0x17, /**< (0x17) Prepare write + response */ + sl_bt_gatt_execute_write_request = 0x18, /**< (0x18) Execute write request */ + sl_bt_gatt_execute_write_response = 0x19, /**< (0x19) Execute write + response */ + sl_bt_gatt_handle_value_notification = 0x1b, /**< (0x1b) Notification */ + sl_bt_gatt_handle_value_indication = 0x1d /**< (0x1d) Indication */ +} sl_bt_gatt_att_opcode_t; + +/** + * @brief These values define whether the client is to receive notifications or + * indications from a remote GATT server. + */ +typedef enum +{ + sl_bt_gatt_disable = 0x0, /**< (0x0) Disable notifications and + indications */ + sl_bt_gatt_notification = 0x1, /**< (0x1) Notification */ + sl_bt_gatt_indication = 0x2 /**< (0x2) Indication */ +} sl_bt_gatt_client_config_flag_t; + +/** + * @brief These values define whether the GATT server is to cancel all queued + * writes or commit all queued writes to a remote database. + */ +typedef enum +{ + sl_bt_gatt_cancel = 0x0, /**< (0x0) Cancel all queued writes */ + sl_bt_gatt_commit = 0x1 /**< (0x1) Commit all queued writes */ +} sl_bt_gatt_execute_write_flag_t; + +/** + * @addtogroup sl_bt_evt_gatt_mtu_exchanged sl_bt_evt_gatt_mtu_exchanged + * @{ + * @brief Indicates that an ATT_MTU exchange procedure is completed + * + * The @p mtu parameter describes new MTU size. MTU size 23 is used before this + * event is received. + */ + +/** @brief Identifier of the mtu_exchanged event */ +#define sl_bt_evt_gatt_mtu_exchanged_id 0x000900a0 + +/***************************************************************************//** + * @brief Data structure of the mtu_exchanged event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_mtu_exchanged_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t mtu; /**< Exchanged ATT_MTU */ +}); + +typedef struct sl_bt_evt_gatt_mtu_exchanged_s sl_bt_evt_gatt_mtu_exchanged_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_mtu_exchanged + +/** + * @addtogroup sl_bt_evt_gatt_service sl_bt_evt_gatt_service + * @{ + * @brief Indicates that a GATT service in the remote GATT database was + * discovered + * + * This event is generated after issuing either the @ref + * sl_bt_gatt_discover_primary_services or @ref + * sl_bt_gatt_discover_primary_services_by_uuid command. + */ + +/** @brief Identifier of the service event */ +#define sl_bt_evt_gatt_service_id 0x010900a0 + +/***************************************************************************//** + * @brief Data structure of the service event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_service_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t service; /**< GATT service handle */ + uint8array uuid; /**< Service UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_service_s sl_bt_evt_gatt_service_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_service + +/** + * @addtogroup sl_bt_evt_gatt_characteristic sl_bt_evt_gatt_characteristic + * @{ + * @brief Indicates that a GATT characteristic in the remote GATT database was + * discovered + * + * This event is generated after issuing either the @ref + * sl_bt_gatt_discover_characteristics or @ref + * sl_bt_gatt_discover_characteristics_by_uuid command. + */ + +/** @brief Identifier of the characteristic event */ +#define sl_bt_evt_gatt_characteristic_id 0x020900a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle */ + uint8_t properties; /**< Characteristic properties */ + uint8array uuid; /**< Characteristic UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_characteristic_s sl_bt_evt_gatt_characteristic_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic + +/** + * @addtogroup sl_bt_evt_gatt_descriptor sl_bt_evt_gatt_descriptor + * @{ + * @brief Indicates that a GATT characteristic descriptor in the remote GATT + * database was discovered + * + * It is generated after issuing the @ref sl_bt_gatt_discover_descriptors or + * @ref sl_bt_gatt_discover_characteristic_descriptors command. + */ + +/** @brief Identifier of the descriptor event */ +#define sl_bt_evt_gatt_descriptor_id 0x030900a0 + +/***************************************************************************//** + * @brief Data structure of the descriptor event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t descriptor; /**< GATT characteristic descriptor handle */ + uint8array uuid; /**< Descriptor UUID in little endian format */ +}); + +typedef struct sl_bt_evt_gatt_descriptor_s sl_bt_evt_gatt_descriptor_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor + +/** + * @addtogroup sl_bt_evt_gatt_characteristic_value sl_bt_evt_gatt_characteristic_value + * @{ + * @brief Indicates that the value of one or several characteristics in the + * remote GATT server was received + * + * It is triggered by several commands: @ref + * sl_bt_gatt_read_characteristic_value, @ref + * sl_bt_gatt_read_characteristic_value_from_offset, @ref + * sl_bt_gatt_read_characteristic_value_by_uuid, @ref + * sl_bt_gatt_read_multiple_characteristic_values; and when the remote GATT + * server sends indications or notifications after enabling notifications with + * @ref sl_bt_gatt_set_characteristic_notification. The parameter @p att_opcode + * indicates which type of GATT transaction triggered this event. In particular, + * if the @p att_opcode type is @ref sl_bt_gatt_handle_value_indication (0x1d), + * the application needs to confirm the indication with @ref + * sl_bt_gatt_send_characteristic_confirmation. + */ + +/** @brief Identifier of the characteristic_value event */ +#define sl_bt_evt_gatt_characteristic_value_id 0x040900a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_characteristic_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode, which indicates the GATT transaction + used. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Characteristic value */ +}); + +typedef struct sl_bt_evt_gatt_characteristic_value_s sl_bt_evt_gatt_characteristic_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_characteristic_value + +/** + * @addtogroup sl_bt_evt_gatt_descriptor_value sl_bt_evt_gatt_descriptor_value + * @{ + * @brief Indicates that the value of a descriptor in the remote GATT server was + * received + * + * This event is generated by the @ref sl_bt_gatt_read_descriptor_value command. + */ + +/** @brief Identifier of the descriptor_value event */ +#define sl_bt_evt_gatt_descriptor_value_id 0x050900a0 + +/***************************************************************************//** + * @brief Data structure of the descriptor_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_descriptor_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t descriptor; /**< GATT characteristic descriptor handle */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Descriptor value */ +}); + +typedef struct sl_bt_evt_gatt_descriptor_value_s sl_bt_evt_gatt_descriptor_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_descriptor_value + +/** + * @addtogroup sl_bt_evt_gatt_procedure_completed sl_bt_evt_gatt_procedure_completed + * @{ + * @brief Indicates that the current GATT procedure was completed successfully + * or that it failed with an error + * + * All GATT commands excluding @ref + * sl_bt_gatt_write_characteristic_value_without_response and @ref + * sl_bt_gatt_send_characteristic_confirmation will trigger this event. As a + * result, the application must wait for this event before issuing another GATT + * command (excluding the two aforementioned exceptions). + * + * Note: After a failed GATT procedure with SL_STATUS_TIMEOUT error, + * further GATT transactions over this connection are not allowed by the stack. + */ + +/** @brief Identifier of the procedure_completed event */ +#define sl_bt_evt_gatt_procedure_completed_id 0x060900a0 + +/***************************************************************************//** + * @brief Data structure of the procedure_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_procedure_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t result; /**< SL_STATUS_OK if successful. Error code otherwise. */ +}); + +typedef struct sl_bt_evt_gatt_procedure_completed_s sl_bt_evt_gatt_procedure_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_procedure_completed + +/***************************************************************************//** + * + * Set the maximum size of ATT Message Transfer Units (MTU). Functionality is + * the same as @ref sl_bt_gatt_server_set_max_mtu and this setting applies to + * both GATT client and server. If the given value is too large according to the + * maximum BGAPI payload size, the system will select the maximum possible value + * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT + * client in the stack will automatically send an MTU exchange request after a + * Bluetooth connection has been established. + * + * @param[in] max_mtu @parblock + * Maximum size of Message Transfer Units (MTU) allowed + * - Range: 23 to 250 + * + * Default: 247 + * @endparblock + * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this + * command succeeds + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_set_max_mtu(uint16_t max_mtu, uint16_t *max_mtu_out); + +/***************************************************************************//** + * + * Discover all primary services of a remote GATT database. This command + * generates a unique gatt_service event for every discovered primary service. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_primary_services(uint8_t connection); + +/***************************************************************************//** + * + * Discover primary services with the specified UUID in a remote GATT database. + * This command generates unique gatt_service event for every discovered primary + * service. Received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that this GATT procedure was successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Service UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_primary_services_by_uuid(uint8_t connection, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Find the services that are included by a service in a remote GATT database. + * This command generates a unique gatt_service event for each included service. + * The received @ref sl_bt_evt_gatt_procedure_completed event indicates that + * this GATT procedure was successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_service - Discovered service from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_find_included_services(uint8_t connection, + uint32_t service); + +/***************************************************************************//** + * + * Discover all characteristics of a GATT service from a remote GATT database. + * This command generates a unique gatt_characteristic event for every + * discovered characteristic. Received @ref sl_bt_evt_gatt_procedure_completed + * event indicates that this GATT procedure was successfully completed or failed + * with an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from + * remote GATT database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristics(uint8_t connection, + uint32_t service); + +/***************************************************************************//** + * + * Discover all characteristics of a GATT service in a remote GATT database + * having the specified UUID. This command generates a unique + * gatt_characteristic event for every discovered characteristic having the + * specified UUID. Received @ref sl_bt_evt_gatt_procedure_completed event + * indicates that this GATT procedure was successfully completed or failed with + * an error. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Characteristic UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic - Discovered characteristic from + * remote GATT database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristics_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Discover all descriptors in a remote GATT database starting from handle. It + * generates a unique gatt_descriptor event for every discovered descriptor. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_descriptors(uint8_t connection, + uint16_t characteristic); + +/***************************************************************************//** + * + * Discover all descriptors of a GATT characteristic in a remote GATT database. + * It generates a unique gatt_descriptor event for every discovered descriptor. + * Received @ref sl_bt_evt_gatt_procedure_completed event indicates that this + * GATT procedure has successfully completed or failed with an error. + * + * @param[in] connection Connection handle + * @param[in] start GATT characteristic handle. This value is normally received + * from the gatt_characteristic event. + * @param[in] end GATT characteristic handle. This value is normally received + * from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor - Discovered descriptor from remote GATT + * database. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_discover_characteristic_descriptors(uint8_t connection, + uint16_t start, + uint16_t end); + +/***************************************************************************//** + * + * Enable or disable the notifications and indications sent from a remote GATT + * server. This procedure discovers a characteristic client configuration + * descriptor and writes the related configuration flags to a remote GATT + * database. A received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that this GATT procedure was successfully completed or that it failed with an + * error. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] flags Enum @ref sl_bt_gatt_client_config_flag_t. Characteristic + * client configuration flags. Values: + * - sl_bt_gatt_disable (0x0): Disable notifications and indications + * - sl_bt_gatt_notification (0x1): Notification + * - sl_bt_gatt_indication (0x2): Indication + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * - @ref sl_bt_evt_gatt_characteristic_value - If an indication or + * notification has been enabled for a characteristic, this event is + * triggered whenever an indication or notification is sent by the remote + * GATT server. The triggering conditions of the GATT server are defined by + * an upper level, for example by a profile. As a result, it is possible + * that no values are ever received, or that it may take time, depending on + * how the server is configured. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_set_characteristic_notification(uint8_t connection, + uint16_t characteristic, + uint8_t flags); + +/***************************************************************************//** + * + * Send a confirmation to a remote GATT server after receiving a characteristic + * indication. The @ref sl_bt_evt_gatt_characteristic_value event carries the @p + * att_opcode containing @ref sl_bt_gatt_handle_value_indication (0x1d), which + * reveals that an indication has been received and must be confirmed with this + * command. The confirmation needs to be sent within 30 seconds, otherwise + * further GATT transactions are not allowed by the remote side. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_send_characteristic_confirmation(uint8_t connection); + +/***************************************************************************//** + * + * Read the value of a characteristic from a remote GATT database. A single @ref + * sl_bt_evt_gatt_characteristic_value is generated if the characteristic value + * fits in one ATT PDU. Otherwise, more than one @ref + * sl_bt_evt_gatt_characteristic_value event is generated because the firmware + * will automatically use the Read Long Characteristic Values procedure. A + * received @ref sl_bt_evt_gatt_procedure_completed event indicates that all + * data was read successfully or that an error response was received. + * + * Note that the GATT client does not verify if the requested attribute is a + * characteristic value. Therefore, before calling this command, ensure that the + * attribute handle is for a characteristic value, for example, by performing + * characteristic discovery. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value(uint8_t connection, + uint16_t characteristic); + +/***************************************************************************//** + * + * Read a partial characteristic value with a specified offset and maximum + * length from a remote GATT database. It is equivalent to @ref + * sl_bt_gatt_read_characteristic_value if both the offset and maximum length + * parameters are 0. A single @ref sl_bt_evt_gatt_characteristic_value event is + * generated if the value to read fits in one ATT PDU. Otherwise, more than one + * @ref sl_bt_evt_gatt_characteristic_value events are generated because the + * firmware will automatically use the Read Long Characteristic Values + * procedure. A received @ref sl_bt_evt_gatt_procedure_completed event indicates + * that all data was read successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] maxlen Maximum bytes to read. If this parameter is 0, all + * characteristic values starting at a given offset will be read. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value_from_offset(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + uint16_t maxlen); + +/***************************************************************************//** + * + * Read values of multiple characteristics from a remote GATT database at once. + * The GATT server returns values in one ATT PDU as the response. If the total + * set of values is greater than (ATT_MTU - 1) bytes in length, only the first + * (ATT_MTU - 1) bytes are included. A single @ref + * sl_bt_evt_gatt_characteristic_value event is generated, in which the + * characteristic is set to 0 and data in the value parameter is a concatenation + * of characteristic values in the order they were requested. The received @ref + * sl_bt_evt_gatt_procedure_completed event indicates either that this GATT + * procedure was successfully completed or failed with an error. + * + * Use this command only for characteristics values that have a known fixed + * size, except the last one that could have variable length. + * + * When the remote GATT server is from Silicon Labs Bluetooth stack, the server + * returns ATT Invalid PDU (0x04) if this command only reads one characteristic + * value. The server returns ATT Application Error 0x80 if this command reads + * the value of a user-type characteristic. + * + * @param[in] connection Connection handle + * @param[in] characteristic_list_len Length of data in @p characteristic_list + * @param[in] characteristic_list List of uint16 characteristic handles each in + * little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - A concatenation of + * characteristic values in the order they were requested + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was either + * successfully completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_multiple_characteristic_values(uint8_t connection, + size_t characteristic_list_len, + const uint8_t* characteristic_list); + +/***************************************************************************//** + * + * Read characteristic values of a service from a remote GATT database by giving + * the UUID of the characteristic and the handle of the service containing this + * characteristic. If multiple characteristic values are received in one ATT + * PDU, one @ref sl_bt_evt_gatt_characteristic_value event is generated for each + * value. If the first characteristic value does not fit in one ATT PDU, the + * firmware automatically uses the Read Long Characteristic Values procedure and + * generate more @ref sl_bt_evt_gatt_characteristic_value events until the value + * has been completely read. A received @ref sl_bt_evt_gatt_procedure_completed + * event indicates that all data was read successfully or that an error response + * was received. + * + * @param[in] connection Connection handle + * @param[in] service GATT service handle. This value is normally received from + * the gatt_service event. + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid Characteristic UUID in little endian format + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_characteristic_value - Contains the data of a + * characteristic sent by the GATT Server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_characteristic_value_by_uuid(uint8_t connection, + uint32_t service, + size_t uuid_len, + const uint8_t* uuid); + +/***************************************************************************//** + * + * Write the value of a characteristic in a remote GATT database. If the value + * length is greater than (ATT_MTU - 3) and does not fit in one ATT PDU, "write + * long" GATT procedure is used automatically. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that all data was written + * successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_characteristic_value(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Write the value of a characteristic in a remote GATT server. It does not + * generate an event. All failures on the server are ignored silently. For + * example, if an error is generated in the remote GATT server and the given + * value is not written into the database, no error message will be reported to + * the local GATT client. Note that this command can't be used to write long + * values. At most ATT_MTU - 3 number of bytes can be sent once. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_characteristic_value_without_response(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Add a characteristic value to the write queue of a remote GATT server. It can + * be used when long attributes need to be written or a set of values needs to + * be written atomically. At most ATT_MTU - 5 number of bytes can be sent at one + * time. Writes are executed or canceled with the @ref + * sl_bt_gatt_execute_characteristic_value_write command. Whether the writes + * succeed or not is indicated in the response of the @ref + * sl_bt_gatt_execute_characteristic_value_write command. + * + * In all use cases where the amount of data to transfer fits into the BGAPI + * payload, use the command @ref sl_bt_gatt_write_characteristic_value to write + * long values because it transparently performs the prepare_write and + * execute_write commands. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] value_len Length of data in @p value + * @param[in] value Value to write into the specified characteristic of the + * remote GATT database + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_prepare_characteristic_value_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Add a characteristic value to the write queue of a remote GATT server and + * verify whether the value was correctly received by the server. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that this GATT procedure + * was successfully completed or failed with an error. Specifically, error code + * 0x0194 (data_corrupted) will be returned if the value received from the GATT + * server's response fails to pass the reliable write verification. At most, + * ATT_MTU - 5 number of bytes can be sent at one time. Writes are executed or + * canceled with the @ref sl_bt_gatt_execute_characteristic_value_write command. + * Whether the writes succeed or not is indicated in the response of the @ref + * sl_bt_gatt_execute_characteristic_value_write command. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] offset Offset of the characteristic value + * @param[in] value_len Length of data in @p value + * @param[in] value Value to write into the specified characteristic of the + * remote GATT database + * @param[out] sent_len The length of data sent to the remote GATT server + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_prepare_characteristic_value_reliable_write(uint8_t connection, + uint16_t characteristic, + uint16_t offset, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Commit or cancel previously queued writes to a long characteristic of a + * remote GATT server. Writes are sent to the queue with @ref + * sl_bt_gatt_prepare_characteristic_value_write command. Content, offset, and + * length of queued values are validated by this procedure. A received @ref + * sl_bt_evt_gatt_procedure_completed event indicates that all data was written + * successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] flags Enum @ref sl_bt_gatt_execute_write_flag_t. Execute write + * flag. Values: + * - sl_bt_gatt_cancel (0x0): Cancel all queued writes + * - sl_bt_gatt_commit (0x1): Commit all queued writes + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_execute_characteristic_value_write(uint8_t connection, + uint8_t flags); + +/***************************************************************************//** + * + * Read the descriptor value of a characteristic in a remote GATT database. A + * single @ref sl_bt_evt_gatt_descriptor_value event is generated if the + * descriptor value fits in one ATT PDU. Otherwise, more than one @ref + * sl_bt_evt_gatt_descriptor_value events are generated because the firmware + * automatically uses the Read Long Characteristic Values procedure. A received + * @ref sl_bt_evt_gatt_procedure_completed event indicates that all data was + * read successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] descriptor GATT characteristic descriptor handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_descriptor_value - Descriptor value received from the + * remote GATT server. + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_read_descriptor_value(uint8_t connection, + uint16_t descriptor); + +/***************************************************************************//** + * + * Write the value of a characteristic descriptor in a remote GATT database. If + * the value length is greater than ATT_MTU - 3 and does not fit in one ATT PDU, + * "write long" GATT procedure is used automatically. Received @ref + * sl_bt_evt_gatt_procedure_completed event indicates either that all data was + * written successfully or that an error response was received. + * + * @param[in] connection Connection handle + * @param[in] descriptor GATT characteristic descriptor handle + * @param[in] value_len Length of data in @p value + * @param[in] value Descriptor value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_procedure_completed - Procedure was successfully + * completed or failed with an error. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_write_descriptor_value(uint8_t connection, + uint16_t descriptor, + size_t value_len, + const uint8_t* value); + +/** @} */ // end addtogroup sl_bt_gatt + +/** + * @addtogroup sl_bt_gattdb GATT Database + * @{ + * + * @brief GATT Database + * + * These commands and events are used for managing the local GATT database. + * + * Many commands in this class return the handles of created attributes. These + * handles may change during commit if attributes are not created in the order + * they present in the database. For example, when creating a new service using + * the @ref sl_bt_gattdb_add_service command, the service declaration handle + * returned from this command becomes invalid later when an attribute is added + * or removed in front of this service. If the user requires that the attribute + * handles returned from these commands must remain valid after the database + * update has been committed, attributes must be created in the order they + * present in the database. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gattdb_new_session_id 0x00460020 +#define sl_bt_cmd_gattdb_add_service_id 0x01460020 +#define sl_bt_cmd_gattdb_remove_service_id 0x02460020 +#define sl_bt_cmd_gattdb_add_included_service_id 0x03460020 +#define sl_bt_cmd_gattdb_remove_included_service_id 0x04460020 +#define sl_bt_cmd_gattdb_add_uuid16_characteristic_id 0x05460020 +#define sl_bt_cmd_gattdb_add_uuid128_characteristic_id 0x06460020 +#define sl_bt_cmd_gattdb_remove_characteristic_id 0x07460020 +#define sl_bt_cmd_gattdb_add_uuid16_descriptor_id 0x08460020 +#define sl_bt_cmd_gattdb_add_uuid128_descriptor_id 0x09460020 +#define sl_bt_cmd_gattdb_remove_descriptor_id 0x0a460020 +#define sl_bt_cmd_gattdb_start_service_id 0x0b460020 +#define sl_bt_cmd_gattdb_stop_service_id 0x0c460020 +#define sl_bt_cmd_gattdb_start_characteristic_id 0x0d460020 +#define sl_bt_cmd_gattdb_stop_characteristic_id 0x0e460020 +#define sl_bt_cmd_gattdb_commit_id 0x0f460020 +#define sl_bt_cmd_gattdb_abort_id 0x10460020 +#define sl_bt_rsp_gattdb_new_session_id 0x00460020 +#define sl_bt_rsp_gattdb_add_service_id 0x01460020 +#define sl_bt_rsp_gattdb_remove_service_id 0x02460020 +#define sl_bt_rsp_gattdb_add_included_service_id 0x03460020 +#define sl_bt_rsp_gattdb_remove_included_service_id 0x04460020 +#define sl_bt_rsp_gattdb_add_uuid16_characteristic_id 0x05460020 +#define sl_bt_rsp_gattdb_add_uuid128_characteristic_id 0x06460020 +#define sl_bt_rsp_gattdb_remove_characteristic_id 0x07460020 +#define sl_bt_rsp_gattdb_add_uuid16_descriptor_id 0x08460020 +#define sl_bt_rsp_gattdb_add_uuid128_descriptor_id 0x09460020 +#define sl_bt_rsp_gattdb_remove_descriptor_id 0x0a460020 +#define sl_bt_rsp_gattdb_start_service_id 0x0b460020 +#define sl_bt_rsp_gattdb_stop_service_id 0x0c460020 +#define sl_bt_rsp_gattdb_start_characteristic_id 0x0d460020 +#define sl_bt_rsp_gattdb_stop_characteristic_id 0x0e460020 +#define sl_bt_rsp_gattdb_commit_id 0x0f460020 +#define sl_bt_rsp_gattdb_abort_id 0x10460020 + +/** + * @brief This enum defines GATT service types. + */ +typedef enum +{ + sl_bt_gattdb_primary_service = 0x0, /**< (0x0) Primary service */ + sl_bt_gattdb_secondary_service = 0x1 /**< (0x1) Secondary service */ +} sl_bt_gattdb_service_type_t; + +/** + * @brief This enum defines characteristic and descriptor value types. + */ +typedef enum +{ + sl_bt_gattdb_fixed_length_value = 0x1, /**< (0x1) A fixed-length value + managed by the local GATT + server for responding the read + and write requests of remote + GATT clients */ + sl_bt_gattdb_variable_length_value = 0x2, /**< (0x2) A variable-length value + managed by the local GATT + server for responding the read + and write requests of remote + GATT clients */ + sl_bt_gattdb_user_managed_value = 0x3 /**< (0x3) A value managed by the + user application for responding + the read and write requests of + remote GATT clients. */ +} sl_bt_gattdb_value_type_t; + +/** + * @addtogroup sl_bt_gattdb_service_property_flags GATT Service Property Flags + * @{ + * + * This enum defines GATT service property flags. + */ + +/** The service should be advertised. */ +#define SL_BT_GATTDB_ADVERTISED_SERVICE 0x1 + +/** @} */ // end GATT Service Property Flags + +/** + * @addtogroup sl_bt_gattdb_security_requirements GATT Attribute Security Requirement Flags + * @{ + * + * This enum defines the security requirement flags for GATT characteristic + * value properties. + */ + +/** The read property requires pairing and encrypted connection. */ +#define SL_BT_GATTDB_ENCRYPTED_READ 0x1 + +/** The read property requires bonding and encrypted connection. */ +#define SL_BT_GATTDB_BONDED_READ 0x2 + +/** The read property requires authenticated pairing and encrypted connection. + * */ +#define SL_BT_GATTDB_AUTHENTICATED_READ 0x4 + +/** The write property requires pairing and encrypted connection. */ +#define SL_BT_GATTDB_ENCRYPTED_WRITE 0x8 + +/** The write property requires bonding and encrypted connection. */ +#define SL_BT_GATTDB_BONDED_WRITE 0x10 + +/** The write property requires authenticated pairing and encrypted connection. + * */ +#define SL_BT_GATTDB_AUTHENTICATED_WRITE 0x20 + +/** The notification and indication properties require pairing and encrypted + * connection. */ +#define SL_BT_GATTDB_ENCRYPTED_NOTIFY 0x40 + +/** The notification and indication properties require bonding and encrypted + * connection. */ +#define SL_BT_GATTDB_BONDED_NOTIFY 0x80 + +/** The notification and indication properties require authenticated pairing and + * encrypted connection. */ +#define SL_BT_GATTDB_AUTHENTICATED_NOTIFY 0x100 + +/** @} */ // end GATT Attribute Security Requirement Flags + +/** + * @addtogroup sl_bt_gattdb_flags GATT Database Flags + * @{ + * + * This enum defines the options of GATT attribute management. + */ + +/** Do not automatically create a Client Characteristic Configuration descriptor + * when adding a characteristic that has the notify or indicate property. */ +#define SL_BT_GATTDB_NO_AUTO_CCCD 0x1 + +/** @} */ // end GATT Database Flags + +/** + * @addtogroup sl_bt_gattdb_characteristic_properties GATT Characteristic Property Flags + * @{ + * + * This enum defines the property flags for GATT characteristic values. Lower + * byte is Characteristic Properties and higher byte is Characteristic Extended + * Properties. + */ + +/** A GATT client can read the characteristic value. */ +#define SL_BT_GATTDB_CHARACTERISTIC_READ 0x2 + +/** A GATT client can write the characteristic value without a response. */ +#define SL_BT_GATTDB_CHARACTERISTIC_WRITE_NO_RESPONSE 0x4 + +/** A GATT client can write the characteristic value. */ +#define SL_BT_GATTDB_CHARACTERISTIC_WRITE 0x8 + +/** The characteristic value can be notified without acknowledgment. */ +#define SL_BT_GATTDB_CHARACTERISTIC_NOTIFY 0x10 + +/** The characteristic value can be notified with acknowledgment. */ +#define SL_BT_GATTDB_CHARACTERISTIC_INDICATE 0x20 + +/** The additional characteristic properties are defined. */ +#define SL_BT_GATTDB_CHARACTERISTIC_EXTENDED_PROPS 0x80 + +/** The characteristic value supports reliable write. */ +#define SL_BT_GATTDB_CHARACTERISTIC_RELIABLE_WRITE 0x101 + +/** @} */ // end GATT Characteristic Property Flags + +/** + * @addtogroup sl_bt_gattdb_descriptor_properties GATT Descriptor Property Flags + * @{ + * + * This enum defines the property flags for GATT characteristic descriptors. + */ + +/** A GATT client can read the descriptor value. */ +#define SL_BT_GATTDB_DESCRIPTOR_READ 0x1 + +/** A GATT client can write the descriptor value. */ +#define SL_BT_GATTDB_DESCRIPTOR_WRITE 0x2 + +/** The descriptor is local only and should be invisible to GATT clients. */ +#define SL_BT_GATTDB_DESCRIPTOR_LOCAL_ONLY 0x200 + +/** @} */ // end GATT Descriptor Property Flags + +/***************************************************************************//** + * + * Start a new GATT database update session. If the operation is successful, the + * Bluetooth stack returns a session ID, with which the GATT database can be + * updated by calling other database management APIs of this class. Changes in + * the database are not immediately saved. Unsaved changes are invisible to a + * connected remote GATT client. + * + * After all changes were performed successfully, commit the changes using the + * @ref sl_bt_gattdb_commit command. The Bluetooth stack will save the changes + * and handle GATT caching as needed. Unsaved database changes can also be + * canceled by calling the @ref sl_bt_gattdb_abort command. In either case, + * after a commit or abort command is called, the current session is closed and + * the session ID becomes invalid. + * + * Only one session is allowed at a time. Error SL_STATUS_ALREADY_EXISTS is + * returned if another session has been started already. + * + * @param[out] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_new_session(uint16_t *session); + +/***************************************************************************//** + * + * Add a service into the local GATT database. When successful, the service is + * appended to the service list and is in stopped state. Use @ref + * sl_bt_gattdb_start_service command to set it visible to remote GATT clients. + * + * You are not allowed to add the Generic Attribute Profile service. If the + * application needs GATT caching, enable the feature in the configuration of + * this component and the GATT server will handle GATT caching according to the + * procedures specified by the Bluetooth core specification. + * + * @param[in] session The database update session ID + * @param[in] type Enum @ref sl_bt_gattdb_service_type_t. The service type. + * Values: + * - sl_bt_gattdb_primary_service (0x0): Primary service + * - sl_bt_gattdb_secondary_service (0x1): Secondary service + * @param[in] property Service properties. Value: 0 or bit flag @ref + * SL_BT_GATTDB_ADVERTISED_SERVICE + * @param[in] uuid_len Length of data in @p uuid + * @param[in] uuid The service UUID in little endian format + * @param[out] service The service declaration attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_service(uint16_t session, + uint8_t type, + uint8_t property, + size_t uuid_len, + const uint8_t* uuid, + uint16_t *service); + +/***************************************************************************//** + * + * Remove a service and its characteristics from the local GATT database. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Add an included-service attribute to a service. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the included-service attribute is added to + * @param[in] included_service The service declaration attribute handle of the + * service to be included + * @param[out] attribute The included-service attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_included_service(uint16_t session, + uint16_t service, + uint16_t included_service, + uint16_t *attribute); + +/***************************************************************************//** + * + * Remove an included-service attribute from a service. + * + * @param[in] session The database update session ID + * @param[in] attribute The included-service attribute handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_included_service(uint16_t session, + uint16_t attribute); + +/***************************************************************************//** + * + * Add a 16-bits UUID characteristic to a service. On success, the + * characteristic is appended to the characteristic list of the service and it + * inherits the started or stopped state of the service. In addition, it can be + * started and stopped separately with the @ref + * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic + * commands. + * + * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the + * stack will automatically add a Client Characteristic Configuration descriptor + * to this characteristic when it has the notify or indicate property. If @ref + * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the + * descriptor separately as needed. + * + * A Characteristic Extended Properties descriptor is automatically added if the + * reliable write property is set. + * + * Use the @ref sl_bt_gattdb_add_uuid128_characteristic command to add a + * 128-bits UUID characteristic. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the characteristic is added to + * @param[in] property Characteristic value properties. Value: bitmask of @ref + * sl_bt_gattdb_characteristic_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the characteristic + * value. + * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. + * @param[in] uuid The 16-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the characteristic value. Ignored if + * @p value_type is @ref sl_bt_gattdb_user_managed_value. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial characteristic value. Length of this value must + * be less than or equal to @p maxlen. Ignored if @p value_type is @ref + * sl_bt_gattdb_user_managed_value. + * @param[out] characteristic The characteristic value attribute handle. This + * handle is ensured valid in current session. It may change after the session + * if attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid16_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic); + +/***************************************************************************//** + * + * Add a 128-bits UUID characteristic to a service. When successful, the + * characteristic is appended to the characteristic list of the service and + * inherits the started or stopped state of the service. Additionally, it can be + * started and stopped separately with the @ref + * sl_bt_gattdb_start_characteristic and @ref sl_bt_gattdb_stop_characteristic + * commands. + * + * If the @p flag parameter does not set @ref SL_BT_GATTDB_NO_AUTO_CCCD, the + * stack will automatically add a Client Characteristic Configuration descriptor + * to this characteristic when it has the notify or indicate property. If @ref + * SL_BT_GATTDB_NO_AUTO_CCCD is set, the user application should add the + * descriptor separately as needed. + * + * A Characteristic Extended Properties descriptor is automatically added if the + * reliable write property is set. + * + * Use the @ref sl_bt_gattdb_add_uuid16_characteristic command to add a 16-bits + * UUID characteristic. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * which the characteristic is added to + * @param[in] property Characteristic value properties. Value: bitmask of @ref + * sl_bt_gattdb_characteristic_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the characteristic + * value. + * @param[in] flag Option flags. Value: 0 or bitmask of @ref sl_bt_gattdb_flags. + * @param[in] uuid The 128-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the characteristic value. Ignored if + * @p value_type is @ref sl_bt_gattdb_user_managed_value. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial characteristic value. Length of this value must + * be less than or equal to @p maxlen. Ignored if @p value_type is @ref + * sl_bt_gattdb_user_managed_value. + * @param[out] characteristic The characteristic value attribute handle. This + * handle is ensured valid in current session. It may change after the session + * if attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid128_characteristic(uint16_t session, + uint16_t service, + uint16_t property, + uint16_t security, + uint8_t flag, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *characteristic); + +/***************************************************************************//** + * + * Remove a characteristic and its descriptors from a service. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Add a 16-bits UUID descriptor to a characteristic. When successful, the + * descriptor is appended to the descriptor list of the characteristic and + * inherits the started or stopped state of the characteristic. + * + * This command does not support adding Characteristic Extended Properties + * descriptors. This descriptor is automatically added if the characteristic + * value has the reliable-write property or when a Characteristic User + * Description descriptor is added and the user description has the write + * property. + * + * Use the @ref sl_bt_gattdb_add_uuid128_descriptor command to add a 128-bits + * UUID descriptor. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic the descriptor is added to + * @param[in] property The descriptor properties. Value: bitmask of @ref + * sl_bt_gattdb_descriptor_properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the descriptor. + * @param[in] uuid The 16-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Ignored if this is a Client Characteristic Configuration descriptor. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p + * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client + * Characteristic Configuration descriptor. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial descriptor value. Length of this value must be + * less than or equal to @p maxlen. Ingored if value type is @ref + * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic + * Configuration descriptor. + * @param[out] descriptor The descriptor attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid16_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + sl_bt_uuid_16_t uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor); + +/***************************************************************************//** + * + * Add a 128-bits UUID descriptor to a characteristic. When successful, the + * descriptor is appended to the descriptor list of the characteristic and + * inherits the started or stopped state of the characteristic. + * + * This command does not support adding Characteristic Extended Properties + * descriptors. This descriptor is automatically added if the characteristic + * value has the reliable-write property or when a Characteristic User + * Description descriptor is added and the user description has the write + * property. + * + * Use the @ref sl_bt_gattdb_add_uuid16_descriptor command to add a 16-bits UUID + * descriptor. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic the descriptor is added to + * @param[in] property Bitmask of characteristic descriptor properties + * @param[in] security Security requirement. Value: 0 or bitmask of @ref + * sl_bt_gattdb_security_requirements. A security requirement flag for a + * property is ignored if the property is not set for the descriptor. + * @param[in] uuid The 128-bits UUID in little endian format + * @param[in] value_type Enum @ref sl_bt_gattdb_value_type_t. The value type. + * Ignored if this is a Client Characteristic Configuration descriptor. + * Values: + * - sl_bt_gattdb_fixed_length_value (0x1): A fixed-length value + * managed by the local GATT server for responding the read and write + * requests of remote GATT clients + * - sl_bt_gattdb_variable_length_value (0x2): A variable-length + * value managed by the local GATT server for responding the read and + * write requests of remote GATT clients + * - sl_bt_gattdb_user_managed_value (0x3): A value managed by the + * user application for responding the read and write requests of remote + * GATT clients. + * @param[in] maxlen The maximum length of the descriptor value. Ignored if @p + * value_type is sl_bt_gattdb_user_managed_value, or if this is a Client + * Characteristic Configuration descriptor. + * @param[in] value_len Length of data in @p value + * @param[in] value The initial descriptor value. Length of this value must be + * less than or equal to @p maxlen. Ignored if value type is @ref + * sl_bt_gattdb_user_managed_value, or if this is a Client Characteristic + * Configuration descriptor. + * @param[out] descriptor The descriptor attribute handle. This handle is + * ensured valid in current session. It may change after the session if + * attributes have been inserted or deleted in front of it. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_add_uuid128_descriptor(uint16_t session, + uint16_t characteristic, + uint16_t property, + uint16_t security, + uuid_128 uuid, + uint8_t value_type, + uint16_t maxlen, + size_t value_len, + const uint8_t* value, + uint16_t *descriptor); + +/***************************************************************************//** + * + * Remove a descriptor from a characteristic. + * + * @param[in] session The database update session ID + * @param[in] descriptor The descriptor handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_remove_descriptor(uint16_t session, + uint16_t descriptor); + +/***************************************************************************//** + * + * Start a service, so that the service and its attributes including + * characteristics and descriptors become visible to remote GATT clients after + * this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_start_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Stop a service, so that the service and its attributes including + * characteristics and descriptors become invisible to remote GATT clients after + * this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] service The service declaration attribute handle of the service + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_stop_service(uint16_t session, uint16_t service); + +/***************************************************************************//** + * + * Start a characteristic, so that the characteristic and its attributes become + * visible to remote GATT clients after this change has been committed. + * SL_STATUS_INVALID_STATE error is returned if the parent service is not + * started. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_start_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Stop a characteristic, so that the characteristic and its attributes become + * invisible to remote GATT clients after this change has been committed. + * + * @param[in] session The database update session ID + * @param[in] characteristic The characteristic value attribute handle of the + * characteristic + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_stop_characteristic(uint16_t session, + uint16_t characteristic); + +/***************************************************************************//** + * + * Save all changes performed in the current session and close the session. The + * stack will assign final handles to new and affected attributes and handle + * GATT caching as needed. The stack removes the client characteristic + * configurations of non-connected GATT clients except the service-changed + * configuration. For connected GATT clients during this database change, the + * stack removes the configurations to the removed characteristics. The session + * ID, temporary attribute handles returned during this session, and other + * existing attribute handles that are after newly added or removed attributes + * are invalidated. + * + * Some attribute handles returned in this session may become invalid if + * attributes are not created in the order they present in the database. In this + * case, attribute handle cache of the database in the user application must be + * refreshed to avoid accidentally using an invalidated handle in subsequent + * operations. + * + * @param[in] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_commit(uint16_t session); + +/***************************************************************************//** + * + * Cancel all changes performed in the current session and close the session. + * The database remains in the same state it was in just before the session was + * started. The session ID and all temporary attribute handles returned during + * this session are invalidated. + * + * @param[in] session The database update session ID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gattdb_abort(uint16_t session); + +/** @} */ // end addtogroup sl_bt_gattdb + +/** + * @addtogroup sl_bt_gatt_server GATT Server + * @{ + * + * @brief GATT Server + * + * These commands and events are used for accessing to the local GATT server and + * database. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_gatt_server_set_max_mtu_id 0x0a0a0020 +#define sl_bt_cmd_gatt_server_get_mtu_id 0x0b0a0020 +#define sl_bt_cmd_gatt_server_find_attribute_id 0x060a0020 +#define sl_bt_cmd_gatt_server_read_attribute_value_id 0x000a0020 +#define sl_bt_cmd_gatt_server_read_attribute_type_id 0x010a0020 +#define sl_bt_cmd_gatt_server_write_attribute_value_id 0x020a0020 +#define sl_bt_cmd_gatt_server_send_user_read_response_id 0x030a0020 +#define sl_bt_cmd_gatt_server_send_user_write_response_id 0x040a0020 +#define sl_bt_cmd_gatt_server_send_notification_id 0x0f0a0020 +#define sl_bt_cmd_gatt_server_send_indication_id 0x100a0020 +#define sl_bt_cmd_gatt_server_notify_all_id 0x110a0020 +#define sl_bt_cmd_gatt_server_read_client_configuration_id 0x120a0020 +#define sl_bt_cmd_gatt_server_send_user_prepare_write_response_id 0x140a0020 +#define sl_bt_cmd_gatt_server_set_capabilities_id 0x080a0020 +#define sl_bt_cmd_gatt_server_enable_capabilities_id 0x0c0a0020 +#define sl_bt_cmd_gatt_server_disable_capabilities_id 0x0d0a0020 +#define sl_bt_cmd_gatt_server_get_enabled_capabilities_id 0x0e0a0020 +#define sl_bt_cmd_gatt_server_read_client_supported_features_id 0x150a0020 +#define sl_bt_rsp_gatt_server_set_max_mtu_id 0x0a0a0020 +#define sl_bt_rsp_gatt_server_get_mtu_id 0x0b0a0020 +#define sl_bt_rsp_gatt_server_find_attribute_id 0x060a0020 +#define sl_bt_rsp_gatt_server_read_attribute_value_id 0x000a0020 +#define sl_bt_rsp_gatt_server_read_attribute_type_id 0x010a0020 +#define sl_bt_rsp_gatt_server_write_attribute_value_id 0x020a0020 +#define sl_bt_rsp_gatt_server_send_user_read_response_id 0x030a0020 +#define sl_bt_rsp_gatt_server_send_user_write_response_id 0x040a0020 +#define sl_bt_rsp_gatt_server_send_notification_id 0x0f0a0020 +#define sl_bt_rsp_gatt_server_send_indication_id 0x100a0020 +#define sl_bt_rsp_gatt_server_notify_all_id 0x110a0020 +#define sl_bt_rsp_gatt_server_read_client_configuration_id 0x120a0020 +#define sl_bt_rsp_gatt_server_send_user_prepare_write_response_id 0x140a0020 +#define sl_bt_rsp_gatt_server_set_capabilities_id 0x080a0020 +#define sl_bt_rsp_gatt_server_enable_capabilities_id 0x0c0a0020 +#define sl_bt_rsp_gatt_server_disable_capabilities_id 0x0d0a0020 +#define sl_bt_rsp_gatt_server_get_enabled_capabilities_id 0x0e0a0020 +#define sl_bt_rsp_gatt_server_read_client_supported_features_id 0x150a0020 + +/** + * @brief These values define whether the server is to sent notifications or + * indications to a remote GATT server. + */ +typedef enum +{ + sl_bt_gatt_server_disable = 0x0, /**< (0x0) Disable + notifications and + indications. */ + sl_bt_gatt_server_notification = 0x1, /**< (0x1) The + characteristic value + shall be notified. */ + sl_bt_gatt_server_indication = 0x2, /**< (0x2) The + characteristic value + shall be indicated. */ + sl_bt_gatt_server_notification_and_indication = 0x3 /**< (0x3) The + characteristic value + notification and + indication are + enabled, application + decides which one to + send. */ +} sl_bt_gatt_server_client_configuration_t; + +/** + * @brief These values describe whether the characteristic client configuration + * was changed or whether a characteristic confirmation was received. + */ +typedef enum +{ + sl_bt_gatt_server_client_config = 0x1, /**< (0x1) Characteristic client + configuration has been changed. */ + sl_bt_gatt_server_confirmation = 0x2 /**< (0x2) Characteristic confirmation + has been received. */ +} sl_bt_gatt_server_characteristic_status_flag_t; + +/** + * @addtogroup sl_bt_evt_gatt_server_attribute_value sl_bt_evt_gatt_server_attribute_value + * @{ + * @brief Indicates that the value of an attribute in the local GATT database + * was changed by a remote GATT client + * + * The parameter @p att_opcode describes which GATT procedure was used to change + * the value. + */ + +/** @brief Identifier of the attribute_value event */ +#define sl_bt_evt_gatt_server_attribute_value_id 0x000a00a0 + +/***************************************************************************//** + * @brief Data structure of the attribute_value event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_attribute_value_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t attribute; /**< Attribute Handle */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which the + value was received. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Value */ +}); + +typedef struct sl_bt_evt_gatt_server_attribute_value_s sl_bt_evt_gatt_server_attribute_value_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_attribute_value + +/** + * @addtogroup sl_bt_evt_gatt_server_user_read_request sl_bt_evt_gatt_server_user_read_request + * @{ + * @brief Indicates that a remote GATT client is attempting to read a value of + * an attribute from the local GATT database, where the attribute was defined in + * the GATT database XML file to have the type="user" + * + * The parameter @p att_opcode informs which GATT procedure was used to read the + * value. The application needs to respond to this request by using the @ref + * sl_bt_gatt_server_send_user_read_response command within 30 seconds, + * otherwise further GATT transactions are not allowed by the remote side. + */ + +/** @brief Identifier of the user_read_request event */ +#define sl_bt_evt_gatt_server_user_read_request_id 0x010a00a0 + +/***************************************************************************//** + * @brief Data structure of the user_read_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_user_read_request_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which the + value was received. */ + uint16_t offset; /**< Value offset */ +}); + +typedef struct sl_bt_evt_gatt_server_user_read_request_s sl_bt_evt_gatt_server_user_read_request_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_read_request + +/** + * @addtogroup sl_bt_evt_gatt_server_user_write_request sl_bt_evt_gatt_server_user_write_request + * @{ + * @brief Indicates that a remote GATT client is attempting to write a value of + * an attribute into the local GATT database, where the attribute was defined in + * the GATT database XML file to have the type="user" + * + * The parameter @p att_opcode informs which attribute procedure was used to + * write the value. If the @p att_opcode is @ref sl_bt_gatt_write_request (see + * @ref sl_bt_gatt_att_opcode_t), the application needs to respond to this + * request by using the @ref sl_bt_gatt_server_send_user_write_response command + * within 30 seconds, otherwise further GATT transactions are not allowed by the + * remote side. If the @p att_opcode is @ref sl_bt_gatt_prepare_write_request, + * the application needs to respond to this request by using the @ref + * sl_bt_gatt_server_send_user_prepare_write_response command within 30 seconds, + * otherwise further GATT transactions are not allowed by the remote side. If + * the value of @p att_opcode is @ref sl_bt_gatt_execute_write_request, it + * indicates that there was one or more prepare writes earlier and now the GATT + * server is processing the execute write, the value of @p characteristic is set + * to 0 and should be ignored. The event @ref + * sl_bt_evt_gatt_server_execute_write_completed will be emitted after + * responding to @ref sl_bt_gatt_execute_write_request by using @ref + * sl_bt_gatt_server_send_user_write_response. + */ + +/** @brief Identifier of the user_write_request event */ +#define sl_bt_evt_gatt_server_user_write_request_id 0x020a00a0 + +/***************************************************************************//** + * @brief Data structure of the user_write_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_user_write_request_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the gatt_characteristic + event. */ + uint8_t att_opcode; /**< Enum @ref sl_bt_gatt_att_opcode_t. Attribute + opcode that informs the procedure from which + the value was received. */ + uint16_t offset; /**< Value offset */ + uint8array value; /**< Value */ +}); + +typedef struct sl_bt_evt_gatt_server_user_write_request_s sl_bt_evt_gatt_server_user_write_request_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_user_write_request + +/** + * @addtogroup sl_bt_evt_gatt_server_characteristic_status sl_bt_evt_gatt_server_characteristic_status + * @{ + * @brief Indicates either that a local Client Characteristic Configuration + * descriptor was changed by the remote GATT client, or that a confirmation from + * the remote GATT client was received upon a successful reception of the + * indication + * + * A confirmation by the remote GATT client should be received within 30 seconds + * after an indication was sent with the @ref sl_bt_gatt_server_send_indication + * command, otherwise further GATT transactions over this connection are not + * allowed by the stack. + */ + +/** @brief Identifier of the characteristic_status event */ +#define sl_bt_evt_gatt_server_characteristic_status_id 0x030a00a0 + +/***************************************************************************//** + * @brief Data structure of the characteristic_status event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_characteristic_status_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t characteristic; /**< GATT characteristic handle. This value is + normally received from the + gatt_characteristic event. */ + uint8_t status_flags; /**< Enum @ref + sl_bt_gatt_server_characteristic_status_flag_t. + Describes whether Client Characteristic + Configuration was changed or if a + confirmation was received. Values: + - sl_bt_gatt_server_client_config + (0x1): Characteristic client + configuration has been changed. + - sl_bt_gatt_server_confirmation + (0x2): Characteristic confirmation + has been received. */ + uint16_t client_config_flags; /**< Enum @ref + sl_bt_gatt_server_client_configuration_t. + This field carries the new value of the + Client Characteristic Configuration. If the + status_flags is 0x2 (confirmation + received), the value of this field can be + ignored. */ + uint16_t client_config; /**< The handle of client-config descriptor. */ +}); + +typedef struct sl_bt_evt_gatt_server_characteristic_status_s sl_bt_evt_gatt_server_characteristic_status_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_characteristic_status + +/** + * @addtogroup sl_bt_evt_gatt_server_execute_write_completed sl_bt_evt_gatt_server_execute_write_completed + * @{ + * @brief Indicates that the execute write command from a remote GATT client has + * completed with the given result + */ + +/** @brief Identifier of the execute_write_completed event */ +#define sl_bt_evt_gatt_server_execute_write_completed_id 0x040a00a0 + +/***************************************************************************//** + * @brief Data structure of the execute_write_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_execute_write_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t result; /**< Execute write result */ +}); + +typedef struct sl_bt_evt_gatt_server_execute_write_completed_s sl_bt_evt_gatt_server_execute_write_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_execute_write_completed + +/** + * @addtogroup sl_bt_evt_gatt_server_indication_timeout sl_bt_evt_gatt_server_indication_timeout + * @{ + * @brief Indicates confirmation from the remote GATT client has not been + * received within 30 seconds after an indication was sent + * + * Furthermore, the stack does not allow GATT transactions over this connection. + */ + +/** @brief Identifier of the indication_timeout event */ +#define sl_bt_evt_gatt_server_indication_timeout_id 0x050a00a0 + +/***************************************************************************//** + * @brief Data structure of the indication_timeout event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_indication_timeout_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_gatt_server_indication_timeout_s sl_bt_evt_gatt_server_indication_timeout_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_indication_timeout + +/** + * @addtogroup sl_bt_evt_gatt_server_notification_tx_completed sl_bt_evt_gatt_server_notification_tx_completed + * @{ + * @brief Indicates that one or more GATT notifications have been transmitted. + * + * By default, this event is not enabled on Bluetooth connections due to + * additional resource usages + * + * Following enablers are required to enable the Bluetooth stack's functionality + * for supporting this event, + * - Include feature bluetooth_feature_resource_report in the application + * project. + * - Use command @ref sl_bt_resource_enable_connection_tx_report to enable + * data packet TX status reports before this Bluetooth connection is + * established. + */ + +/** @brief Identifier of the notification_tx_completed event */ +#define sl_bt_evt_gatt_server_notification_tx_completed_id 0x060a00a0 + +/***************************************************************************//** + * @brief Data structure of the notification_tx_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_gatt_server_notification_tx_completed_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t count; /**< Number of notifications that have been transmitted */ +}); + +typedef struct sl_bt_evt_gatt_server_notification_tx_completed_s sl_bt_evt_gatt_server_notification_tx_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_gatt_server_notification_tx_completed + +/***************************************************************************//** + * + * Set the maximum size of ATT Message Transfer Units (MTU). The functionality + * is the same as @ref sl_bt_gatt_set_max_mtu and this setting applies to both + * GATT client and server. If the given value is too large according to the + * maximum BGAPI payload size, the system will select the maximum possible value + * as the maximum ATT_MTU. If the maximum ATT_MTU is larger than 23, the GATT + * client in the stack will automatically send an MTU exchange request after a + * Bluetooth connection was established. + * + * @param[in] max_mtu @parblock + * Maximum size of Message Transfer Units (MTU) allowed + * - Range: 23 to 250 + * + * Default: 247 + * @endparblock + * @param[out] max_mtu_out The maximum ATT_MTU selected by the system if this + * command succeeded + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_set_max_mtu(uint16_t max_mtu, + uint16_t *max_mtu_out); + +/***************************************************************************//** + * + * Get the size of ATT Message Transfer Units (MTU) for a connection. + * + * @param[in] connection Connection handle + * @param[out] mtu The maximum ATT_MTU used by the connection + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_get_mtu(uint8_t connection, uint16_t *mtu); + +/***************************************************************************//** + * + * Find attributes of a certain type from a local GATT database. The type is + * usually given as a 16-bit or 128-bit UUID in little endian format. + * + * @param[in] start Search start handle + * @param[in] type_len Length of data in @p type + * @param[in] type The attribute type UUID + * @param[out] attribute Attribute handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_find_attribute(uint16_t start, + size_t type_len, + const uint8_t* type, + uint16_t *attribute); + +/***************************************************************************//** + * + * Read the value of an attribute from a local GATT database. Only (maximum + * BGAPI payload size - 3) amount of data can be read at once. The application + * can continue reading with increased offset value if it receives (maximum + * BGAPI payload size - 3) number of bytes. + * + * @param[in] attribute Attribute handle + * @param[in] offset Value offset + * @param[in] max_value_size Size of output buffer passed in @p value + * @param[out] value_len On return, set to the length of output data written to + * @p value + * @param[out] value The attribute value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_attribute_value(uint16_t attribute, + uint16_t offset, + size_t max_value_size, + size_t *value_len, + uint8_t *value); + +/***************************************************************************//** + * + * Read the type of an attribute from a local GATT database. The type is a UUID, + * usually 16 or 128 bits long in little endian format. + * + * @param[in] attribute Attribute handle + * @param[in] max_type_size Size of output buffer passed in @p type + * @param[out] type_len On return, set to the length of output data written to + * @p type + * @param[out] type The attribute type UUID + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_attribute_type(uint16_t attribute, + size_t max_type_size, + size_t *type_len, + uint8_t *type); + +/***************************************************************************//** + * + * Write the value of an attribute in the local GATT database. Writing the value + * of a characteristic of the local GATT database will not trigger notifications + * or indications to the remote GATT client if the characteristic has a property + * to indicate or notify and the client has enabled notification or indication. + * Notifications and indications are sent to the remote GATT client using @ref + * sl_bt_gatt_server_send_notification or @ref sl_bt_gatt_server_send_indication + * commands. + * + * @param[in] attribute Attribute handle + * @param[in] offset Value offset + * @param[in] value_len Length of data in @p value + * @param[in] value Value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_write_attribute_value(uint16_t attribute, + uint16_t offset, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_read_request event. The + * response needs to be sent within 30 seconds, otherwise no more GATT + * transactions are allowed by the remote side. If attr_errorcode is set to 0, + * the characteristic value is sent to the remote GATT client in the standard + * way. Other attr_errorcode values will cause the local GATT server to send an + * attribute protocol error response instead of the actual data. Maximum number + * of bytes this command can send depends on the value of parameter att_opcode + * in @ref sl_bt_evt_gatt_server_user_read_request event: + * - ATT_MTU - 1 if the opcode is @ref sl_bt_gatt_read_request or @ref + * sl_bt_gatt_read_blob_request + * - ATT_MTU - 4 if the opcode is @ref sl_bt_gatt_read_by_type_request + * + * If the data length in @p value exceeds the limit, the first maximum number of + * bytes will be sent and rest data is ignored. The actual number of bytes that + * was sent is retruned in the response of this command. + * + * The client will continue reading by sending a new read blob request with an + * increased offset value if it receives the maximum amount of attribute data + * the read respond packet can contain. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle received in the @ref + * sl_bt_evt_gatt_server_user_read_request event. + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * @param[in] value_len Length of data in @p value + * @param[in] value Characteristic value to send to the GATT client. Ignored if + * att_errorcode is not 0. + * @param[out] sent_len The length of data sent to the remote GATT client + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_read_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + size_t value_len, + const uint8_t* value, + uint16_t *sent_len); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when + * parameter @p att_opcode in the event is @ref sl_bt_gatt_write_request or @ref + * sl_bt_gatt_execute_write_request (see @ref sl_bt_gatt_att_opcode_t). The + * response needs to be sent within 30 seconds, otherwise no more GATT + * transactions are allowed by the remote side. When responding to @ref + * sl_bt_gatt_execute_write_request, the value of parameter @p characteristic is + * ignored. If attr_errorcode is set to 0, the ATT protocol's write response is + * sent to indicate to the remote GATT client that the write operation was + * processed successfully. Other values will cause the local GATT server to send + * an ATT protocol error response. + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle received in the @ref + * sl_bt_evt_gatt_server_user_write_request event + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode); + +/***************************************************************************//** + * + * Send a notification to a remote GATT client. At most, ATT_MTU - 3 number of + * bytes can be sent in a notification. An error SL_STATUS_COMMAND_TOO_LONG is + * returned if the value length exceeds ATT_MTU - 3. + * + * A notification is sent only if the client has enabled it by setting the + * corresponding flag to the Client Characteristic Configuration descriptor. The + * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not + * have the notification property. The error SL_STATUS_INVALID_STATE is returned + * if the client has not enabled the notification. + * + * @param[in] connection A handle of the connection over which the notification + * is sent. + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be notified + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_notification(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send an indication to a remote GATT client. At most, ATT_MTU - 3 number of + * bytes can be sent in an indication. An error SL_STATUS_COMMAND_TOO_LONG is + * returned if the value length exceeds ATT_MTU - 3. + * + * An indication is sent only if the client has enabled it by setting the + * corresponding flag to the Client Characteristic Configuration descriptor. The + * error SL_STATUS_INVALID_PARAMETER is returned if the characteristic does not + * have the indication property. The error SL_STATUS_INVALID_STATE is returned + * if the client has not enabled the indication. + * + * A new indication to a GATT client can't be sent until an outstanding + * indication procedure with the same client has completed. The procedure is + * completed when a confirmation from the client is received. The confirmation + * is indicated by @ref sl_bt_evt_gatt_server_characteristic_status. + * + * The error SL_STATUS_IN_PROGRESS is returned if an indication procedure with + * the same client is outstanding. Always wait for confirmation for previous + * indication before sending a new indication. + * + * @param[in] connection A handle of the connection over which the indication is + * sent. + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be indicated + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_gatt_server_characteristic_status - This event is + * triggered after the confirmation from the client is received. + * - @ref sl_bt_evt_gatt_server_indication_timeout - This event indicates + * confirmation from the remote GATT client has not been received within 30 + * seconds after an indication was sent. Further GATT transactions over this + * connection are not allowed by the stack. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_indication(uint8_t connection, + uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Send notifications or indications to all connected remote GATT clients. At + * most, ATT_MTU - 3 number of bytes can be sent in a notification or + * indication. If the value length exceeds the limit on a connection, the first + * ATT_MTU - 3 bytes will be sent and rest of data is ignored. + * + * A notification or indication is sent only if the client has enabled it by + * setting the corresponding flag to the Client Characteristic Configuration + * descriptor. If the Client Characteristic Configuration descriptor supports + * both notifications and indications, the stack will always send a notification + * even when the client has enabled both. + * + * A new indication to a GATT client can't be sent until an outstanding + * indication procedure with the same client has completed, and the operation + * will continue for the next client. The procedure is completed when a + * confirmation from the client is received. The confirmation is indicated by + * @ref sl_bt_evt_gatt_server_characteristic_status. + * + * @param[in] characteristic Characteristic handle + * @param[in] value_len Length of data in @p value + * @param[in] value Value to be notified or indicated + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_notify_all(uint16_t characteristic, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Read client characteristic configuration of a remote GATT client. + * + * @param[in] connection A handle of the connection to a remote client. + * @param[in] characteristic Characteristic handle + * @param[out] client_config_flags Enum @ref + * sl_bt_gatt_server_client_configuration_t. Client characteristic + * configuration of a remote client. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_client_configuration(uint8_t connection, + uint16_t characteristic, + uint16_t *client_config_flags); + +/***************************************************************************//** + * + * Send a response to a @ref sl_bt_evt_gatt_server_user_write_request event when + * parameter @p att_opcode in the event is @ref sl_bt_gatt_prepare_write_request + * (see @ref sl_bt_gatt_att_opcode_t). The response needs to be sent within 30 + * seconds, otherwise no more GATT transactions are allowed by the remote side. + * If @p att_errorcode is set to 0, the ATT protocol's prepare write response is + * sent to indicate to the remote GATT client that the write operation was + * processed successfully. Other values will cause the local GATT server to send + * an ATT protocol error response. The application should set values of + * parameters @p offset and @p value to identical values from the @ref + * sl_bt_evt_gatt_server_user_write_request event. The values will be verified + * on the client side in case the request is a reliable write (by Bluetooth Core + * Specification Volume 3, Part G, 4.9.5). + * + * @param[in] connection Connection handle + * @param[in] characteristic GATT characteristic handle. This value is normally + * received from the gatt_characteristic event. + * @param[in] att_errorcode Attribute protocol error code + * - 0: No error + * - Non-zero: See Bluetooth specification, Host volume, Attribute + * Protocol, Error Codes table. + * @param[in] offset Value offset + * @param[in] value_len Length of data in @p value + * @param[in] value Value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_send_user_prepare_write_response(uint8_t connection, + uint16_t characteristic, + uint8_t att_errorcode, + uint16_t offset, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Reset capabilities that should be enabled by the GATT database. A service is + * visible to remote GATT clients if at least one of its capabilities is + * enabled. The same applies to a characteristic and its attributes. Capability + * identifiers and their corresponding bit flag values are in the auto-generated + * database header file. See UG118: Blue Gecko Bluetooth Profile Toolkit + * Developer's Guide for how to declare capabilities in the GATT database. + * + * Changing the capabilities of a database effectively causes a database change + * (attributes being added or removed) from a remote GATT client point of view. + * If the database has a Generic Attribute service and Service Changed + * characteristic, the stack will monitor the local database change status and + * manage service changed indications for a GATT client that has enabled the + * indication configuration of the Service Changed characteristic. + * + * @param[in] caps Bit flags of capabilities to reset. Value 0 sets the default + * database capabilities. + * @param[in] reserved Use the value 0 on this reserved field. Do not use + * none-zero values because they are reserved for future use. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_set_capabilities(uint32_t caps, + uint32_t reserved); + +/***************************************************************************//** + * + * Enable additional capabilities in the local GATT database. Already enabled + * capabilities keep unchanged after this command. See @ref + * sl_bt_gatt_server_set_capabilities for more information. + * + * @param[in] caps Capabilities to enable + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_enable_capabilities(uint32_t caps); + +/***************************************************************************//** + * + * Disable the given capabilities in the local GATT database. See @ref + * sl_bt_gatt_server_set_capabilities for more information. + * + * @param[in] caps Capabilities to disable + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_disable_capabilities(uint32_t caps); + +/***************************************************************************//** + * + * Get capabilities currently enabled in the local GATT database. + * + * @param[out] caps Enabled capabilities + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_get_enabled_capabilities(uint32_t *caps); + +/***************************************************************************//** + * + * Read client supported features of a remote GATT client. + * + * @param[in] connection A handle of the connection to a remote client. + * @param[out] client_features Bit field describing client supported features of + * a remote client. See Bluetooth specification Vol 3, Part G, 7.2 for the + * values. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_gatt_server_read_client_supported_features(uint8_t connection, + uint8_t *client_features); + +/** @} */ // end addtogroup sl_bt_gatt_server + +/** + * @addtogroup sl_bt_nvm NVM + * @{ + * + * @brief NVM + * + * Provide an interface to manage user data objects (key/value pairs) in the + * flash memory. User data stored within the flash memory is persistent across + * reset and power cycling of the device. Because Bluetooth bondings are also + * stored in the flash area, in addition to the flash storage size, the space + * available for user data also depends on the number of bondings the device has + * at the time. + * + * On EFR32[B|M]G1x devices, either PS Store or NVM3 data storage driver can be + * used. PS Store is supported by the Bluetooth stack only. Using NVM3 is + * recommended if the device needs to support Dynamic Multiple Protocol (DMP). + * On EFR32[B|M]G2x devices, only NVM3 is supported. When NVM3 is used, + * applications can also use the NVM3 APIs directly. + * + * In PS Store, the flash storage size is fixed at 2048 bytes. The maximum data + * object size associated to a key is 56 bytes. A Bluetooth bonding uses at + * maximum 138 bytes for secure connections and 174 bytes for legacy pairing. + * + * In NVM3, the flash store size is configurable and the minimum is 3 flash + * pages. The maximum data object size is configurable up to 4096 bytes. A + * Bluetooth bonding uses maximum 110 bytes for secure connections and 138 bytes + * for legacy pairing. For more details, see AN1135 "Using Third Generation + * NonVolatile Memory (NVM3) Data Storage". + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_nvm_save_id 0x020d0020 +#define sl_bt_cmd_nvm_load_id 0x030d0020 +#define sl_bt_cmd_nvm_erase_id 0x040d0020 +#define sl_bt_cmd_nvm_erase_all_id 0x010d0020 +#define sl_bt_rsp_nvm_save_id 0x020d0020 +#define sl_bt_rsp_nvm_load_id 0x030d0020 +#define sl_bt_rsp_nvm_erase_id 0x040d0020 +#define sl_bt_rsp_nvm_erase_all_id 0x010d0020 + +/** + * @addtogroup sl_bt_nvm_keys Defined Keys + * @{ + * + * Define keys + */ + +/** Crystal tuning value override */ +#define SL_BT_NVM_KEY_CTUNE 0x32 + +/** @} */ // end Defined Keys + +/***************************************************************************//** + * + * Store a value into the specified NVM key. Allowed NVM keys are in range from + * 0x4000 to 0x407F. At most, 56 bytes user data can be stored in one NVM key. + * The error code 0x018a (command_too_long) is returned if the value data is + * more than 56 bytes. + * + * @param[in] key NVM key + * @param[in] value_len Length of data in @p value + * @param[in] value Value to store into the specified NVM key + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_save(uint16_t key, + size_t value_len, + const uint8_t* value); + +/***************************************************************************//** + * + * Retrieve the value of the specified NVM key. + * + * @param[in] key NVM key of the value to be retrieved + * @param[in] max_value_size Size of output buffer passed in @p value + * @param[out] value_len On return, set to the length of output data written to + * @p value + * @param[out] value The returned value of the specified NVM key + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_load(uint16_t key, + size_t max_value_size, + size_t *value_len, + uint8_t *value); + +/***************************************************************************//** + * + * Delete a single NVM key and its value from the persistent store. + * + * @param[in] key NVM key to delete + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_erase(uint16_t key); + +/***************************************************************************//** + * + * Delete all NVM keys and their corresponding values. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_nvm_erase_all(); + +/** @} */ // end addtogroup sl_bt_nvm + +/** + * @addtogroup sl_bt_test Testing Commands + * @{ + * + * @brief Testing Commands + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_test_dtm_tx_v4_id 0x030e0020 +#define sl_bt_cmd_test_dtm_tx_cw_id 0x040e0020 +#define sl_bt_cmd_test_dtm_rx_id 0x010e0020 +#define sl_bt_cmd_test_dtm_end_id 0x020e0020 +#define sl_bt_rsp_test_dtm_tx_v4_id 0x030e0020 +#define sl_bt_rsp_test_dtm_tx_cw_id 0x040e0020 +#define sl_bt_rsp_test_dtm_rx_id 0x010e0020 +#define sl_bt_rsp_test_dtm_end_id 0x020e0020 + +/** + * @brief Test packet types supported by the stack + */ +typedef enum +{ + sl_bt_test_pkt_prbs9 = 0x0, /**< (0x0) PRBS9 packet payload */ + sl_bt_test_pkt_11110000 = 0x1, /**< (0x1) 11110000 packet payload */ + sl_bt_test_pkt_10101010 = 0x2, /**< (0x2) 10101010 packet payload */ + sl_bt_test_pkt_11111111 = 0x4, /**< (0x4) 11111111 packet payload */ + sl_bt_test_pkt_00000000 = 0x5, /**< (0x5) 00000000 packet payload */ + sl_bt_test_pkt_00001111 = 0x6, /**< (0x6) 00001111 packet payload */ + sl_bt_test_pkt_01010101 = 0x7, /**< (0x7) 01010101 packet payload */ + sl_bt_test_pkt_pn9 = 0xfd, /**< (0xfd) PN9 continuously modulated output */ + sl_bt_test_pkt_carrier = 0xfe /**< (0xfe) Unmodulated carrier */ +} sl_bt_test_packet_type_t; + +/** + * @brief Test PHY types + */ +typedef enum +{ + sl_bt_test_phy_1m = 0x1, /**< (0x1) 1M PHY */ + sl_bt_test_phy_2m = 0x2, /**< (0x2) 2M PHY */ + sl_bt_test_phy_125k = 0x3, /**< (0x3) 125k Coded PHY */ + sl_bt_test_phy_500k = 0x4 /**< (0x4) 500k Coded PHY */ +} sl_bt_test_phy_t; + +/** + * @addtogroup sl_bt_evt_test_dtm_completed sl_bt_evt_test_dtm_completed + * @{ + * @brief Indicates that the radio has processed a test start or end command + * + * The @p result parameter indicates the success of the command. + * + * After the receiver or transmitter test is stopped, the @p number_of_packets + * parameter in this event indicates the number of received or transmitted + * packets. + */ + +/** @brief Identifier of the dtm_completed event */ +#define sl_bt_evt_test_dtm_completed_id 0x000e00a0 + +/***************************************************************************//** + * @brief Data structure of the dtm_completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_test_dtm_completed_s +{ + uint16_t result; /**< Command result */ + uint16_t number_of_packets; /**< Number of packets + + Only valid for @ref sl_bt_test_dtm_end + command. */ +}); + +typedef struct sl_bt_evt_test_dtm_completed_s sl_bt_evt_test_dtm_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_test_dtm_completed + +/***************************************************************************//** + * + * Start a transmitter test against a separate Bluetooth tester device. When the + * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event + * is triggered. This event indicates whether the test started successfully. + * + * In the transmitter test, the device sends packets continuously with a fixed + * interval. The type and length of each packet is set by @p packet_type and @p + * length parameters. The parameter @p phy specifies which PHY is used to + * transmit the packets. All devices support at least 1M PHY. A special packet + * type, test_pkt_carrier , can be used to transmit continuous + * unmodulated carrier. The length field is ignored in this mode. As this + * command has the limitation within the value of @p power_level, use of @ref + * sl_bt_test_dtm_tx_cw for custom waves is recommended. + * + * Stop the test using the @ref sl_bt_test_dtm_end command. + * + * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to + * transmit. Values: + * - sl_bt_test_pkt_prbs9 (0x0): PRBS9 packet payload + * - sl_bt_test_pkt_11110000 (0x1): 11110000 packet payload + * - sl_bt_test_pkt_10101010 (0x2): 10101010 packet payload + * - sl_bt_test_pkt_11111111 (0x4): 11111111 packet payload + * - sl_bt_test_pkt_00000000 (0x5): 00000000 packet payload + * - sl_bt_test_pkt_00001111 (0x6): 00001111 packet payload + * - sl_bt_test_pkt_01010101 (0x7): 01010101 packet payload + * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output + * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier + * @param[in] length @parblock + * Packet length in bytes + * + * Range: 0-255 + * @endparblock + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * @param[in] power_level @parblock + * TX power level in unit dBm. Values: + * - -127 to +20: Use specified or the nearest TX power level. The + * minimum -127 dBm is specified in the Bluetooth specification. However, + * a device may not support this low TX power. In addition, only some + * devices support 20 dBm TX power. Effective TX power will be limited by + * the global system TX power that can be set with the @ref + * sl_bt_system_set_tx_power command. + * - 0x7E: Use minimum TX power level the device supports. + * - 0x7F: Use the smallest of the maximum TX power level the device + * supports and the global maximum TX power setting in stack. + * + * For continuous unmodulated carrier mode, the values are set in 0.1 dBm + * unit. If the value exceeds the range of power level value allowed by the + * device, the command will adjust the power level to the closest minimum or + * maximum value. + * @endparblock + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_tx_v4(uint8_t packet_type, + uint8_t length, + uint8_t channel, + uint8_t phy, + int8_t power_level); + +/***************************************************************************//** + * + * Start a transmitter test for a custom wave. When the command is processed by + * the radio, a @ref sl_bt_evt_test_dtm_completed event is triggered. This event + * indicates whether the test started successfully. + * + * In the custom wave transmitter test, the device continuously transmits the + * career. The parameter @p packet_type specifies the packet type. The parameter + * @p phy specifies which PHY is used to transmit the packets. All devices + * support at least 1M PHY. + * + * Stop the test using the @ref sl_bt_test_dtm_end command. + * + * @param[in] packet_type Enum @ref sl_bt_test_packet_type_t. Packet type to + * transmit. Values: + * - sl_bt_test_pkt_pn9 (0xfd): PN9 continuously modulated output + * - sl_bt_test_pkt_carrier (0xfe): Unmodulated carrier + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * @param[in] power_level @parblock + * TX power level. Unit: 0.1 dBm. + * + * If the value exceeds the range of power level value, allowed by the device, + * the command will adjust the power level to the closest minimum or maximum + * value. + * @endparblock + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_tx_cw(uint8_t packet_type, + uint8_t channel, + uint8_t phy, + int16_t power_level); + +/***************************************************************************//** + * + * Start a receiver test against a separate Bluetooth tester device. When the + * command is processed by the radio, a @ref sl_bt_evt_test_dtm_completed event + * is triggered. This event indicates whether the test started successfully. + * + * Parameter @p phy specifies which PHY is used to receive the packets. All + * devices support at least 1M PHY. + * + * The test may be stopped using @ref sl_bt_test_dtm_end command. This will + * trigger another @ref sl_bt_evt_test_dtm_completed event, which carries the + * number of packets received during the test. + * + * @param[in] channel @parblock + * Bluetooth channel + * + * Range: 0-39 + * + * Channel is (F - 2402) / 2, + * + * where F is frequency in MHz + * @endparblock + * @param[in] phy Enum @ref sl_bt_test_phy_t. PHY to use. Values: + * - sl_bt_test_phy_1m (0x1): 1M PHY + * - sl_bt_test_phy_2m (0x2): 2M PHY + * - sl_bt_test_phy_125k (0x3): 125k Coded PHY + * - sl_bt_test_phy_500k (0x4): 500k Coded PHY + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - This event is received when the + * command is processed. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_rx(uint8_t channel, uint8_t phy); + +/***************************************************************************//** + * + * End a transmitter or a receiver test. When the command is processed by the + * radio and the test has ended, a @ref sl_bt_evt_test_dtm_completed event is + * triggered. + * + * + * @return Command result + * + * @b Events + * - @ref sl_bt_evt_test_dtm_completed - Received when the command is + * processed by the radio and the test has ended. + * + ******************************************************************************/ +sl_status_t sl_bt_test_dtm_end(); + +/** @} */ // end addtogroup sl_bt_test + +/** + * @addtogroup sl_bt_sm Security Manager + * @{ + * + * @brief Security Manager + * + * The commands in this class manage Bluetooth security, including commands for + * starting and stopping encryption and commands for management of all bonding + * operations. + * + * Use the following procedure to bond with a remote device: + * - Use the command @ref sl_bt_sm_configure to configure security + * requirements and I/O capabilities of this device. + * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into + * bondable mode. + * - Use the command @ref sl_bt_connection_open to open a connection to the + * remote device. + * - After the connection is open, use command @ref sl_bt_sm_increase_security + * to encrypt the connection. This will also start the bonding process. + * + * Use the following procedure to respond to the bonding initiated by a remote + * device: + * - Use the command @ref sl_bt_sm_configure to configure security + * requirements and I/O capabilities of this device. + * - Use the command @ref sl_bt_sm_set_bondable_mode to set this device into + * bondable mode. + * - Use the command @ref sl_bt_advertiser_start to start connectable + * advertising. + * - Open a connection to this device from the remote device. + * - After the connection is open, start the bonding process on the remote + * device. + * + * If MITM is required, the application needs to display or ask the user to + * enter a passkey during the process. See events @ref + * sl_bt_evt_sm_passkey_display and @ref sl_bt_evt_sm_passkey_request for more + * information. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_sm_configure_id 0x010f0020 +#define sl_bt_cmd_sm_set_minimum_key_size_id 0x140f0020 +#define sl_bt_cmd_sm_set_debug_mode_id 0x0f0f0020 +#define sl_bt_cmd_sm_add_to_whitelist_id 0x130f0020 +#define sl_bt_cmd_sm_store_bonding_configuration_id 0x020f0020 +#define sl_bt_cmd_sm_set_bondable_mode_id 0x000f0020 +#define sl_bt_cmd_sm_set_passkey_id 0x100f0020 +#define sl_bt_cmd_sm_increase_security_id 0x040f0020 +#define sl_bt_cmd_sm_enter_passkey_id 0x080f0020 +#define sl_bt_cmd_sm_passkey_confirm_id 0x090f0020 +#define sl_bt_cmd_sm_bonding_confirm_id 0x0e0f0020 +#define sl_bt_cmd_sm_delete_bonding_id 0x060f0020 +#define sl_bt_cmd_sm_delete_bondings_id 0x070f0020 +#define sl_bt_cmd_sm_get_bonding_handles_id 0x150f0020 +#define sl_bt_cmd_sm_get_bonding_details_id 0x160f0020 +#define sl_bt_cmd_sm_find_bonding_by_address_id 0x170f0020 +#define sl_bt_cmd_sm_resolve_rpa_id 0x1d0f0020 +#define sl_bt_cmd_sm_set_bonding_key_id 0x180f0020 +#define sl_bt_cmd_sm_set_legacy_oob_id 0x190f0020 +#define sl_bt_cmd_sm_set_oob_id 0x1a0f0020 +#define sl_bt_cmd_sm_set_remote_oob_id 0x1b0f0020 +#define sl_bt_cmd_sm_set_bonding_data_id 0x1c0f0020 +#define sl_bt_rsp_sm_configure_id 0x010f0020 +#define sl_bt_rsp_sm_set_minimum_key_size_id 0x140f0020 +#define sl_bt_rsp_sm_set_debug_mode_id 0x0f0f0020 +#define sl_bt_rsp_sm_add_to_whitelist_id 0x130f0020 +#define sl_bt_rsp_sm_store_bonding_configuration_id 0x020f0020 +#define sl_bt_rsp_sm_set_bondable_mode_id 0x000f0020 +#define sl_bt_rsp_sm_set_passkey_id 0x100f0020 +#define sl_bt_rsp_sm_increase_security_id 0x040f0020 +#define sl_bt_rsp_sm_enter_passkey_id 0x080f0020 +#define sl_bt_rsp_sm_passkey_confirm_id 0x090f0020 +#define sl_bt_rsp_sm_bonding_confirm_id 0x0e0f0020 +#define sl_bt_rsp_sm_delete_bonding_id 0x060f0020 +#define sl_bt_rsp_sm_delete_bondings_id 0x070f0020 +#define sl_bt_rsp_sm_get_bonding_handles_id 0x150f0020 +#define sl_bt_rsp_sm_get_bonding_details_id 0x160f0020 +#define sl_bt_rsp_sm_find_bonding_by_address_id 0x170f0020 +#define sl_bt_rsp_sm_resolve_rpa_id 0x1d0f0020 +#define sl_bt_rsp_sm_set_bonding_key_id 0x180f0020 +#define sl_bt_rsp_sm_set_legacy_oob_id 0x190f0020 +#define sl_bt_rsp_sm_set_oob_id 0x1a0f0020 +#define sl_bt_rsp_sm_set_remote_oob_id 0x1b0f0020 +#define sl_bt_rsp_sm_set_bonding_data_id 0x1c0f0020 + +/** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * @brief These values define the bonding keys of the bonded device stored in + * the persistent store. + */ +typedef enum +{ + sl_bt_sm_bonding_key_remote_ltk = 0x1, /**< (0x1) LTK used as central device, + always used when paired using + secure connections and local LTK + does not exist */ + sl_bt_sm_bonding_key_local_ltk = 0x2, /**< (0x2) LTK used as peripheral + device when using legacy pairing, + only used with secure connections + pairing if key exists */ + sl_bt_sm_bonding_key_irk = 0x3 /**< (0x3) Identity resolving key for + resolvable private addresses */ +} sl_bt_sm_bonding_key_t; +/** @endcond */ // end restricted enum type + +/** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * @brief These values define the bonding data types, which are stored in the + * persistent store. + */ +typedef enum +{ + sl_bt_sm_bonding_data_remote_address = 0x0, /**< (0x0) Identity address + of the remote device */ + sl_bt_sm_bonding_data_remote_ltk = 0x1, /**< (0x1) LTK used as + central device */ + sl_bt_sm_bonding_data_local_ltk = 0x2, /**< (0x2) LTK used as + peripheral device */ + sl_bt_sm_bonding_data_remote_master_inf = 0x3, /**< (0x3) Idenfication info + used as central device */ + sl_bt_sm_bonding_data_local_master_inf = 0x4, /**< (0x4) Idenfication info + used as central device */ + sl_bt_sm_bonding_data_irk = 0x5, /**< (0x5) IRK of the remote + device */ + sl_bt_sm_bonding_data_meta = 0x6, /**< (0x6) Metadata about + the bonding */ + sl_bt_sm_bonding_data_gatt_client_config = 0x7, /**< (0x7) GATT database + client configuration */ + sl_bt_sm_bonding_data_gatt_client_features = 0x8, /**< (0x8) GATT client + supported features */ + sl_bt_sm_bonding_data_gatt_db_hash = 0x9 /**< (0x9) GATT database + hash */ +} sl_bt_sm_bonding_data_t; +/** @endcond */ // end restricted enum type + +/** + * @brief These values define the security management related I/O capabilities + * supported by the device. + */ +typedef enum +{ + sl_bt_sm_io_capability_displayonly = 0x0, /**< (0x0) Display Only */ + sl_bt_sm_io_capability_displayyesno = 0x1, /**< (0x1) Display with + Yes/No-buttons */ + sl_bt_sm_io_capability_keyboardonly = 0x2, /**< (0x2) Keyboard Only */ + sl_bt_sm_io_capability_noinputnooutput = 0x3, /**< (0x3) No Input and No + Output */ + sl_bt_sm_io_capability_keyboarddisplay = 0x4 /**< (0x4) Display with Keyboard */ +} sl_bt_sm_io_capability_t; + +/** + * @addtogroup sl_bt_sm_configuration Security Manager configuration flags + * @{ + * + * These values are used to configure security requirements. + */ + +/** Bonding requires authentication (Man-in-the-Middle protection). */ +#define SL_BT_SM_CONFIGURATION_MITM_REQUIRED 0x1 + +/** Encryption requires bonding. Note that this setting will also enable + * bonding. */ +#define SL_BT_SM_CONFIGURATION_BONDING_REQUIRED 0x2 + +/** Require secure connections pairing. */ +#define SL_BT_SM_CONFIGURATION_SC_ONLY 0x4 + +/** Bonding requests need to be confirmed. Received bonding requests are + * notified by @ref sl_bt_evt_sm_confirm_bonding. */ +#define SL_BT_SM_CONFIGURATION_BONDING_REQUEST_REQUIRED 0x8 + +/** Allow connections only from bonded devices. This option is ignored when the + * application includes the bluetooth_feature_external_bonding_database feature. + * */ +#define SL_BT_SM_CONFIGURATION_CONNECTIONS_FROM_BONDED_DEVICES_ONLY 0x10 + +/** Prefer authenticated pairing when both options are possible based on the + * settings. Otherwise just works pairing is preferred. */ +#define SL_BT_SM_CONFIGURATION_PREFER_MITM 0x20 + +/** Require secure connections OOB data from both devices. */ +#define SL_BT_SM_CONFIGURATION_OOB_FROM_BOTH_DEVICES_REQUIRED 0x40 + +/** Reject pairing if remote device uses debug keys. */ +#define SL_BT_SM_CONFIGURATION_REJECT_DEBUG_KEYS 0x80 + +/** @} */ // end Security Manager configuration flags + +/** + * @addtogroup sl_bt_evt_sm_passkey_display sl_bt_evt_sm_passkey_display + * @{ + * @brief Indicates a request to display the passkey to the user. + */ + +/** @brief Identifier of the passkey_display event */ +#define sl_bt_evt_sm_passkey_display_id 0x000f00a0 + +/***************************************************************************//** + * @brief Data structure of the passkey_display event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_passkey_display_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t passkey; /**< Passkey. Range: 0 to 999999. + - NOTE! When displaying the passkey to the user, + prefix the number with zeros to obtain a 6 digit + number + - Example: Passkey value is 42 + - Number to display to the user is 000042 */ +}); + +typedef struct sl_bt_evt_sm_passkey_display_s sl_bt_evt_sm_passkey_display_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_passkey_display + +/** + * @addtogroup sl_bt_evt_sm_passkey_request sl_bt_evt_sm_passkey_request + * @{ + * @brief Indicates a request for the passkey prompt displayed on the remote + * device + * + * Use the command @ref sl_bt_sm_enter_passkey to input the passkey value. + */ + +/** @brief Identifier of the passkey_request event */ +#define sl_bt_evt_sm_passkey_request_id 0x010f00a0 + +/***************************************************************************//** + * @brief Data structure of the passkey_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_passkey_request_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_sm_passkey_request_s sl_bt_evt_sm_passkey_request_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_passkey_request + +/** + * @addtogroup sl_bt_evt_sm_confirm_passkey sl_bt_evt_sm_confirm_passkey + * @{ + * @brief Indicates a request for passkey display and confirmation by the user + * + * Use the command @ref sl_bt_sm_passkey_confirm to accept or reject the + * displayed passkey. + */ + +/** @brief Identifier of the confirm_passkey event */ +#define sl_bt_evt_sm_confirm_passkey_id 0x020f00a0 + +/***************************************************************************//** + * @brief Data structure of the confirm_passkey event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_confirm_passkey_s +{ + uint8_t connection; /**< Connection handle */ + uint32_t passkey; /**< Passkey. Range: 0 to 999999. + - NOTE! When displaying the passkey to the user, + prefix the number with zeros to obtain a 6 digit + number + - Example: Passkey value is 42 + - Number to display to the user is 000042 */ +}); + +typedef struct sl_bt_evt_sm_confirm_passkey_s sl_bt_evt_sm_confirm_passkey_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_confirm_passkey + +/** + * @addtogroup sl_bt_evt_sm_bonded sl_bt_evt_sm_bonded + * @{ + * @brief Triggered when the pairing or bonding procedure is successfully + * completed. + */ + +/** @brief Identifier of the bonded event */ +#define sl_bt_evt_sm_bonded_id 0x030f00a0 + +/***************************************************************************//** + * @brief Data structure of the bonded event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_bonded_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t bonding; /**< Bonding handle. Values: + - SL_BT_INVALID_BONDING_HANDLE (0xff): + Pairing completed without bonding - the + pairing key will be discarded after + disconnection. + - Other: Procedure completed, pairing key + stored with given bonding handle */ + uint8_t security_mode; /**< Enum @ref sl_bt_connection_security_t. Connection + security mode. Values: + - sl_bt_connection_mode1_level2 (0x1): + Unauthenticated pairing with encryption + - sl_bt_connection_mode1_level3 (0x2): + Authenticated pairing with encryption + - sl_bt_connection_mode1_level4 (0x3): + Authenticated Secure Connections pairing with + encryption using a 128-bit strength encryption + key */ +}); + +typedef struct sl_bt_evt_sm_bonded_s sl_bt_evt_sm_bonded_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_bonded + +/** + * @addtogroup sl_bt_evt_sm_bonding_failed sl_bt_evt_sm_bonding_failed + * @{ + * @brief This event is triggered if the pairing or bonding procedure fails. + */ + +/** @brief Identifier of the bonding_failed event */ +#define sl_bt_evt_sm_bonding_failed_id 0x040f00a0 + +/***************************************************************************//** + * @brief Data structure of the bonding_failed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_bonding_failed_s +{ + uint8_t connection; /**< Connection handle */ + uint16_t reason; /**< Describes error that occurred */ +}); + +typedef struct sl_bt_evt_sm_bonding_failed_s sl_bt_evt_sm_bonding_failed_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_bonding_failed + +/** + * @addtogroup sl_bt_evt_sm_confirm_bonding sl_bt_evt_sm_confirm_bonding + * @{ + * @brief Indicates a user request to display that the new bonding request is + * received and for the user to confirm the request + * + * Use the command @ref sl_bt_sm_bonding_confirm to accept or reject the bonding + * request. + */ + +/** @brief Identifier of the confirm_bonding event */ +#define sl_bt_evt_sm_confirm_bonding_id 0x090f00a0 + +/***************************************************************************//** + * @brief Data structure of the confirm_bonding event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_sm_confirm_bonding_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t bonding_handle; /**< Bonding handle for the request. Range: 0 to 31, + or SL_BT_INVALID_BONDING_HANDLE (0xff). + - NOTE! When the bonding handle is anything + other than SL_BT_INVALID_BONDING_HANDLE + (0xff), a bonding already exists for this + connection. Overwriting the existing bonding + is a potential security risk. */ +}); + +typedef struct sl_bt_evt_sm_confirm_bonding_s sl_bt_evt_sm_confirm_bonding_t; + +/** @} */ // end addtogroup sl_bt_evt_sm_confirm_bonding + +/***************************************************************************//** + * + * Configure security requirements and I/O capabilities of the system. + * + * @param[in] flags @parblock + * Security requirement flags. This value can be a bitmask of multiple flags + * from @ref sl_bt_sm_configuration + * + * Bit 0: + * - 0: Allow bonding without authentication + * - 1: Bonding requires authentication (Man-in-the-Middle + * protection) + * + * Bit 1: + * - 0: Allow encryption without bonding + * - 1: Encryption requires bonding. Note that this setting will also + * enable bonding. + * + * Bit 2: + * - 0: Allow bonding with legacy pairing + * - 1: Secure connections only + * + * Bit 3: + * - 0: Bonding request does not need to be confirmed + * - 1: Bonding requests need to be confirmed. Received bonding + * requests are notified by @ref sl_bt_evt_sm_confirm_bonding + * + * Bit 4: This option is ignored when the application includes the + * bluetooth_feature_external_bonding_database feature. + * - 0: Allow all connections + * - 1: Allow connections only from bonded devices + * + * Bit 5: + * - 0: Prefer just works pairing when both options are possible + * based on the settings. + * - 1: Prefer authenticated pairing when both options are possible + * based on the settings. + * + * Bit 6: + * - 0: Allow secure connections OOB pairing with OOB data from only + * one device. + * - 1: Require secure connections OOB data from both devices. + * + * Bit 7: + * - 0: Allow debug keys from remote device. + * - 1: Reject pairing if remote device uses debug keys. + * + * Default value: 0x00 + * @endparblock + * @param[in] io_capabilities Enum @ref sl_bt_sm_io_capability_t. I/O + * Capabilities. The default I/O Capability used by the stack is No Input and + * No Output. Values: + * - sl_bt_sm_io_capability_displayonly (0x0): Display Only + * - sl_bt_sm_io_capability_displayyesno (0x1): Display with + * Yes/No-buttons + * - sl_bt_sm_io_capability_keyboardonly (0x2): Keyboard Only + * - sl_bt_sm_io_capability_noinputnooutput (0x3): No Input and No + * Output + * - sl_bt_sm_io_capability_keyboarddisplay (0x4): Display with + * Keyboard + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_configure(uint8_t flags, uint8_t io_capabilities); + +/***************************************************************************//** + * + * Set the minimum allowed key size used for bonding. The default value is 16 + * bytes. + * + * @param[in] minimum_key_size Minimum allowed key size for bonding. Range: 7 to + * 16 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_minimum_key_size(uint8_t minimum_key_size); + +/***************************************************************************//** + * + * Set Security Manager in debug mode. In this mode, the secure connections + * bonding uses known debug keys, so that the encrypted packet can be opened by + * Bluetooth protocol analyzer. To disable the debug mode, restart the device. + * + * Bondings made in debug mode are unsecure. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_debug_mode(); + +/***************************************************************************//** + * + * Deprecated and replaced by @ref + * sl_bt_accept_list_add_device_by_bonding and @ref + * sl_bt_accept_list_add_device_by_address provided by the + * bluetooth_feature_accept_list component. + * + * Add device to accept list, which can be enabled with @ref + * sl_bt_gap_enable_whitelisting. + * + * When using external bonding database, the accept list size must be set before + * adding devices to the list using @ref sl_bt_sm_store_bonding_configuration. + * + * @param[in] address Address of the device added to accept list + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. Address type of + * the device added to accept list. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +SL_BGAPI_DEPRECATED sl_status_t sl_bt_sm_add_to_whitelist(bd_addr address, uint8_t address_type); + +/***************************************************************************//** + * + * Set the maximum allowed bonding count and bonding policy. The maximum number + * of bondings that can be supported depends on how much user data is stored in + * the NVM and the NVM size. When bond policy value 1 or 2 is selected, the + * stack will automatically write the new bond, as per the policy, only if the + * maximum allowed bonding count has been reached. If the stack can't write a + * new bond for any other reason (e.g., NVM is full), an error will be thrown + * through the bonding_failed event indicating why the bonding was not written. + * The application has to manually release space from the NVM (e.g., by deleting + * one of the existing bonds or application data) so that a new bond can be + * saved. The default value is 13. + * + * When using external bonding database with accept list filtering, this command + * must be called before adding devices to the accept list to define the list + * size. Calling this function empties the existing accept list. + * + * @param[in] max_bonding_count @parblock + * Maximum allowed bonding count. Range: 1 to 32 + * + * Sets the accept list size with external bonding database. + * @endparblock + * @param[in] policy_flags @parblock + * Bonding policy. Values: + * - 0: If database is full, new bonding attempts will fail + * - 1: New bonding will overwrite the oldest existing bonding + * - 2: New bonding will overwrite the bonding that was used the + * longest time ago + * + * Default: 0 + * + * With external bonding database the parameter is ignored. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_store_bonding_configuration(uint8_t max_bonding_count, + uint8_t policy_flags); + +/***************************************************************************//** + * + * Set whether the device should accept new bondings. By default, the device + * does not accept new bondings. + * + * @param[in] bondable @parblock + * Bondable mode. Values: + * - 0: New bondings not accepted + * - 1: Bondings allowed + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bondable_mode(uint8_t bondable); + +/***************************************************************************//** + * + * Enter a fixed passkey, which will be used in the @ref + * sl_bt_evt_sm_passkey_display event. + * + * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to disable and + * start using random passkeys. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_passkey(int32_t passkey); + +/***************************************************************************//** + * + * Enhance the security of a connection to current security requirements. On an + * unencrypted connection, it will encrypt the connection and will also perform + * bonding if requested by both devices. On an encrypted connection, it will + * cause the connection to be re-encrypted. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_parameters - Triggered after increasing + * security has been completed successfully and indicates the latest + * security mode of the connection. + * - @ref sl_bt_evt_sm_bonded - Triggered if pairing or bonding was performed + * in this operation and the result is successful. + * - @ref sl_bt_evt_sm_bonding_failed - Triggered if pairing or bonding was + * performed in this operation and the result has failed. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_increase_security(uint8_t connection); + +/***************************************************************************//** + * + * Enter a passkey after receiving a passkey request event. + * + * @param[in] connection Connection handle + * @param[in] passkey Passkey. Valid range: 0-999999. Set -1 to cancel pairing. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_enter_passkey(uint8_t connection, int32_t passkey); + +/***************************************************************************//** + * + * Accept or reject the reported passkey confirm value. + * + * @param[in] connection Connection handle + * @param[in] confirm Acceptance. Values: + * - 0: Reject + * - 1: Accept confirm value + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_passkey_confirm(uint8_t connection, uint8_t confirm); + +/***************************************************************************//** + * + * Accept or reject the bonding request. + * + * @param[in] connection Connection handle + * @param[in] confirm Acceptance. Values: + * - 0: Reject + * - 1: Accept bonding request + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_bonding_confirm(uint8_t connection, uint8_t confirm); + +/***************************************************************************//** + * + * Delete the specified bonding or accept list filtering. The connection will be + * closed if the remote device is connected currently. + * + * This commands deletes the information from the persistent bonding database + * when the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) is used. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] bonding Bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_delete_bonding(uint8_t bonding); + +/***************************************************************************//** + * + * Delete all bondings, accept list filtering and device local identity + * resolving key (IRK). All connections to affected devices are closed as well. + * + * This command empties the persistent bonding database when the built-in + * bonding database (bluetooth_feature_builtin_bonding_database) is used. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_delete_bondings(); + +/***************************************************************************//** + * + * Get number of entries and bitmask of their handles saved in the bonding + * database. The entry in the bonding database can be either bonding or accept + * list filtering device. + * + * To get the bonding type and peer device address of a bonding, use the @ref + * sl_bt_sm_get_bonding_details command. The bonding handle can be calculated + * from the handle bitmask returned by this command, or alternatively, repeat + * calling the @ref sl_bt_sm_get_bonding_details command to get the detailed + * information of all bondings. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] reserved Use the value 0 on this reserved field. Do not use + * none-zero values because they are reserved for future use. + * @param[out] num_bondings Total number of bondings and accept list filtering + * devices stored in bonding database. + * @param[in] max_bondings_size Size of output buffer passed in @p bondings + * @param[out] bondings_len On return, set to the length of output data written + * to @p bondings + * @param[out] bondings 4 byte bit field of used bonding handles in little + * endian format. Bit 0 of first byte is bonding handle 0, bit 0 of second + * byte is bonding handle 8 etc. If the bit is 1 that bonding handle exists in + * the bonding database. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_get_bonding_handles(uint32_t reserved, + uint32_t *num_bondings, + size_t max_bondings_size, + size_t *bondings_len, + uint8_t *bondings); + +/***************************************************************************//** + * + * Get the detailed information for a bonding entry. Data includes remote device + * address and address type as well as security mode for bonding and a used + * encryption key length. + * + * To get the detailed information of all bondings, repeat calling this command + * starting from 0 as the bonding handle value until the maximum number of + * configured bondings are reached. Use 32 as the maximum number if the + * configured number is unknown. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] bonding Bonding handle + * @param[out] address Bluetooth address of the remote device + * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Address type. + * Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Accept list filtering entry has security mode as no + * security. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size Key length in bytes, 0 for accept list filtering entry + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_get_bonding_details(uint32_t bonding, + bd_addr *address, + uint8_t *address_type, + uint8_t *security_mode, + uint8_t *key_size); + +/***************************************************************************//** + * + * Find the bonding or accept list filtering entry by using a Bluetooth device + * address. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] address The Bluetooth device address + * @param[out] bonding The bonding handle + * @param[out] security_mode Enum @ref sl_bt_connection_security_t. Connection + * security mode. Accept list filtering entry has security mode as no + * security. Values: + * - sl_bt_connection_mode1_level1 (0x0): No security + * - sl_bt_connection_mode1_level2 (0x1): Unauthenticated pairing + * with encryption + * - sl_bt_connection_mode1_level3 (0x2): Authenticated pairing with + * encryption + * - sl_bt_connection_mode1_level4 (0x3): Authenticated Secure + * Connections pairing with encryption using a 128-bit strength encryption + * key + * @param[out] key_size Key length in bytes, 0 for accept list filtering entry + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_find_bonding_by_address(bd_addr address, + uint32_t *bonding, + uint8_t *security_mode, + uint8_t *key_size); + +/***************************************************************************//** + * + * Find the identity address of bonded device by using resolvable private + * address (RPA). + * + * The error SL_STATUS_NOT_FOUND is returned if the RPA cannot be resolved. + * + * This command is unavailable if the external bonding database + * (bluetooth_feature_external_bonding_database) is used. + * + * @param[in] rpa Resolvable private address to be resolved + * @param[out] address The identity adderss of the bonded device + * @param[out] address_type Enum @ref sl_bt_gap_address_type_t. Identity address + * type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[out] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_resolve_rpa(bd_addr rpa, + bd_addr *address, + uint8_t *address_type, + uint32_t *bonding); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Set key for bonding or accept list filtering entry overwriting any possible + * existing key. If there is error which leaves bonding entry in inconsistent + * state the bonding will be deleted. Only IRK can be added to accept list + * filtering entry. + * + * @param[in] bonding Bonding handle + * @param[in] key_type Enum @ref sl_bt_sm_bonding_key_t. Key type. Values: + * - sl_bt_sm_bonding_key_remote_ltk (0x1): LTK used as central + * device, always used when paired using secure connections and local LTK + * does not exist + * - sl_bt_sm_bonding_key_local_ltk (0x2): LTK used as peripheral + * device when using legacy pairing, only used with secure connections + * pairing if key exists + * - sl_bt_sm_bonding_key_irk (0x3): Identity resolving key for + * resolvable private addresses + * @param[in] key Bonding key in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bonding_key(uint32_t bonding, + uint8_t key_type, + aes_key_128 key); + +/***************************************************************************//** + * + * Set Out-Of-Band (OOB) encryption data for a legacy pairing of a device. OOB + * data may be, for example, a PIN code exchanged over an alternate path, such + * as NFC. The device will not allow any other bonding if OOB data is set. OOB + * data can't be set simultaneously with secure connections OOB data. + * + * @param[in] enable Enable OOB with legacy pairing. Values: + * - 0: disable + * - 1: enable + * @param[in] oob_data 16-byte legacy pairing OOB data in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_legacy_oob(uint8_t enable, aes_key_128 oob_data); + +/***************************************************************************//** + * + * Enable the use of Out-Of-Band (OOB) encryption data for a device for secure + * connections pairing. Enabling will generate new OOB data and confirm values, + * which can be sent to the remote device. After enabling the secure connections + * OOB data, the remote devices OOB data can be set with @ref + * sl_bt_sm_set_remote_oob. Calling this function will erase any set remote + * device OOB data and confirm values. The device will not allow any other + * bonding if OOB data is set. The secure connections OOB data cannot be enabled + * simultaneously with legacy pairing OOB data. + * + * @param[in] enable Enable OOB with secure connections pairing. Values: + * - 0: disable + * - 1: enable + * @param[out] random 16-byte randomly-generated secure connections OOB data in + * little endian format. + * @param[out] confirm 16-byte confirm value for the OOB random value in little + * endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_oob(uint8_t enable, + aes_key_128 *random, + aes_key_128 *confirm); + +/***************************************************************************//** + * + * Set Out-Of-Band (OOB) data and confirm values received from the remote device + * for secure connections pairing. OOB data must be enabled with @ref + * sl_bt_sm_set_oob before setting the remote device OOB data. + * + * @param[in] enable Enable remote device OOB data with secure connections + * pairing. Values: + * - 0: disable + * - 1: enable + * @param[in] random 16-byte remote device secure connections OOB data in little + * endian format. + * @param[in] confirm 16-byte remote device confirm value for the OOB random + * value in little endian format. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_sm_set_remote_oob(uint8_t enable, + aes_key_128 random, + aes_key_128 confirm); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Set bonding data for connection from external bonding database. + * + * @param[in] connection Connection handle + * @param[in] type Enum @ref sl_bt_sm_bonding_data_t. Bonding data type. Values: + * - sl_bt_sm_bonding_data_remote_address (0x0): Identity address of + * the remote device + * - sl_bt_sm_bonding_data_remote_ltk (0x1): LTK used as central + * device + * - sl_bt_sm_bonding_data_local_ltk (0x2): LTK used as peripheral + * device + * - sl_bt_sm_bonding_data_remote_master_inf (0x3): Idenfication info + * used as central device + * - sl_bt_sm_bonding_data_local_master_inf (0x4): Idenfication info + * used as central device + * - sl_bt_sm_bonding_data_irk (0x5): IRK of the remote device + * - sl_bt_sm_bonding_data_meta (0x6): Metadata about the bonding + * - sl_bt_sm_bonding_data_gatt_client_config (0x7): GATT database + * client configuration + * - sl_bt_sm_bonding_data_gatt_client_features (0x8): GATT client + * supported features + * - sl_bt_sm_bonding_data_gatt_db_hash (0x9): GATT database hash + * @param[in] data_len Length of data in @p data + * @param[in] data Bonding data. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_sm_set_bonding_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/** @} */ // end addtogroup sl_bt_sm + +/** + * @addtogroup sl_bt_external_bondingdb External Bonding Database + * @{ + * + * @brief External Bonding Database + * + * Receive and respond to requests related to managing an external bonding + * database. When the application uses the + * bluetooth_feature_external_bonding_database feature, the Bluetooth stack and + * the application use the commands and events in this class to store and + * retrieve data from the persistent bonding storage. + * + * When this feature is used, the built-in bonding database + * (bluetooth_feature_builtin_bonding_database) and the address resolving in the + * Bluetooth stack are excluded. The user application and external bonding + * database are responsible for the following functionalities: + * - The external bonding database must be able to reliably and permanently + * store the bonding data and type tuples that are provided by the stack in + * the @ref sl_bt_evt_external_bondingdb_data_request event. Data types @ref + * sl_bt_external_bondingdb_data_remote_address and @ref + * sl_bt_external_bondingdb_data_remote_address_type can be used by the + * application to identify the device, but they are not used by the stack + * and hence the stack will not ask for their values. Other data types in + * @ref sl_bt_external_bondingdb_data_t are needed by the Bluetooth Security + * Manager or GATT Server. The Long Term Keys (LTK) and Identity Resolving + * Keys (IRK) must be stored securely. When the database is on a separate + * host device, they must be securely transmitted between the host and + * target over the NCP transport. The application also needs to manage the + * bondings in the storage, e.g., delete a bonding when requested by the + * business logic. + * - Manage a local RAM-based bookkeeping to keep track of open connections. + * At a minimum, the remote Bluetooth address address and address type must + * be stored in the bookkeeping when a @ref sl_bt_evt_connection_opened + * event is received. If the remote Bluetooth device address is a resolvable + * private random (RPA) address, the application may perform address + * resolving using the IRK keys of the remote devices stored in the bonding + * database. Address resolving is required for identifying a connected + * device using an RPA address. When the scanner or periodic advertising + * synchronization feature is used, RPA addresses in advertisement report or + * sync events may need to be resolved if required by the business + * requirements. + * - When the Bluetooth stack requires bonding data, it will send an @ref + * sl_bt_evt_external_bondingdb_data_request event. The application must + * respond to the request by sending the data value using the @ref + * sl_bt_external_bondingdb_set_data command. The GATT server will pend the + * requests from the remote GATT client and encryption or bonding is not + * possible until all requested bonding data has been sent to the stack. The + * stack will send @ref sl_bt_evt_external_bondingdb_data_ready when it has + * received all the necessary bonding data from the application. + * + * In this configuration, the value of @p bonding parameter in @ref + * sl_bt_evt_advertiser_scan_request, @ref sl_bt_evt_connection_opened, @ref + * sl_bt_evt_sm_bonded, @ref sl_bt_evt_scanner_scan_report, @ref + * sl_bt_evt_scanner_legacy_advertisement_report, @ref + * sl_bt_evt_scanner_extended_advertisement_report, @ref sl_bt_evt_sync_opened, + * and @ref sl_bt_evt_sync_transfer_received is always + * SL_BT_INVALID_BONDING_HANDLE (0xff). Resolving the bonding handle is the + * responsibility of the external bonding database. Additionally, the following + * BGAPI commands are not available and will return the SL_STATUS_NOT_AVAILABLE + * error: + * - @ref sl_bt_sm_delete_bonding + * - @ref sl_bt_sm_get_bonding_handles + * - @ref sl_bt_sm_get_bonding_details + * - @ref sl_bt_sm_find_bonding_by_address + * - @ref sl_bt_sm_resolve_rpa + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_external_bondingdb_set_data_id 0x005c0020 +#define sl_bt_rsp_external_bondingdb_set_data_id 0x005c0020 + +/** + * @brief These values define the bonding data types, which are stored in the + * persistent store. + */ +typedef enum +{ + sl_bt_external_bondingdb_data_remote_address = 0x0, /**< (0x0) Identity + address of the + remote device, + which a + resolvable + random address + can be resolved + to */ + sl_bt_external_bondingdb_data_remote_address_type = 0x1, /**< (0x1) Type of + the remote + device identity + address. Value + 0 is public + device address + and 1 is static + device address */ + sl_bt_external_bondingdb_data_remote_ltk = 0x2, /**< (0x2) Long Term + Key (LTK) used + as central + device. The + value of this + type must be + stored + securely. */ + sl_bt_external_bondingdb_data_local_ltk = 0x3, /**< (0x3) Long Term + Key (LTK) used + as peripheral + device. The + value of this + type must be + stored + securely. */ + sl_bt_external_bondingdb_data_remote_central_inf = 0x4, /**< (0x4) + Identification + info used as a + central device */ + sl_bt_external_bondingdb_data_local_central_inf = 0x5, /**< (0x5) + Identification + info used as a + central device */ + sl_bt_external_bondingdb_data_irk = 0x6, /**< (0x6) Identity + Resolving Key + (IRK) of the + remote device + that is used + for resolving + its RPA + addresses when + the device is + in privacy + mode. The value + of this type + must be stored + securely. */ + sl_bt_external_bondingdb_data_meta = 0x7, /**< (0x7) Metadata + about the + bonding */ + sl_bt_external_bondingdb_data_gatt_client_config = 0x8, /**< (0x8) The + remote GATT + client + characteristic + configurations */ + sl_bt_external_bondingdb_data_gatt_client_features = 0x9, /**< (0x9) The + remote GATT + client + supported + features */ + sl_bt_external_bondingdb_data_gatt_db_hash = 0xa /**< (0xa) Latest + local GATT + database hash + value that the + remote client + has seen for + GATT robust + caching feature */ +} sl_bt_external_bondingdb_data_t; + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data_request sl_bt_evt_external_bondingdb_data_request + * @{ + * @brief Indicates that the Bluetooth stack requests the bonding data of a + * connection from the external bonding database + * + * The application must respond by setting bonding data using the @ref + * sl_bt_external_bondingdb_set_data command. + * + * The Bluetooth stack will send this event one or more times after a connection + * is open following the @ref sl_bt_evt_connection_opened event to get ready for + * security related operations. + */ + +/** @brief Identifier of the data_request event */ +#define sl_bt_evt_external_bondingdb_data_request_id 0x005c00a0 + +/***************************************************************************//** + * @brief Data structure of the data_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_request_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The + requested bonding data type. Values: + - sl_bt_external_bondingdb_data_remote_address + (0x0): Identity address of the remote device, + which a resolvable random address can be resolved + to + - sl_bt_external_bondingdb_data_remote_address_type + (0x1): Type of the remote device identity + address. Value 0 is public device address and 1 + is static device address + - sl_bt_external_bondingdb_data_remote_ltk + (0x2): Long Term Key (LTK) used as central + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_local_ltk + (0x3): Long Term Key (LTK) used as peripheral + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_remote_central_inf + (0x4): Identification info used as a central + device + - sl_bt_external_bondingdb_data_local_central_inf + (0x5): Identification info used as a central + device + - sl_bt_external_bondingdb_data_irk (0x6): + Identity Resolving Key (IRK) of the remote device + that is used for resolving its RPA addresses when + the device is in privacy mode. The value of this + type must be stored securely. + - sl_bt_external_bondingdb_data_meta (0x7): + Metadata about the bonding + - sl_bt_external_bondingdb_data_gatt_client_config + (0x8): The remote GATT client characteristic + configurations + - sl_bt_external_bondingdb_data_gatt_client_features + (0x9): The remote GATT client supported + features + - sl_bt_external_bondingdb_data_gatt_db_hash + (0xa): Latest local GATT database hash value + that the remote client has seen for GATT robust + caching feature */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_request_s sl_bt_evt_external_bondingdb_data_request_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_request + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data sl_bt_evt_external_bondingdb_data + * @{ + * @brief Indicates that updated bonding data of a connection is available + * + * The application must store it in the external bonding database permanently. + */ + +/** @brief Identifier of the data event */ +#define sl_bt_evt_external_bondingdb_data_id 0x015c00a0 + +/***************************************************************************//** + * @brief Data structure of the data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t type; /**< Enum @ref sl_bt_external_bondingdb_data_t. The + bonding data type. Values: + - sl_bt_external_bondingdb_data_remote_address + (0x0): Identity address of the remote + device, which a resolvable random address can + be resolved to + - sl_bt_external_bondingdb_data_remote_address_type + (0x1): Type of the remote device identity + address. Value 0 is public device address and + 1 is static device address + - sl_bt_external_bondingdb_data_remote_ltk + (0x2): Long Term Key (LTK) used as central + device. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_local_ltk + (0x3): Long Term Key (LTK) used as + peripheral device. The value of this type must + be stored securely. + - sl_bt_external_bondingdb_data_remote_central_inf + (0x4): Identification info used as a + central device + - sl_bt_external_bondingdb_data_local_central_inf + (0x5): Identification info used as a + central device + - sl_bt_external_bondingdb_data_irk + (0x6): Identity Resolving Key (IRK) of the + remote device that is used for resolving its + RPA addresses when the device is in privacy + mode. The value of this type must be stored + securely. + - sl_bt_external_bondingdb_data_meta + (0x7): Metadata about the bonding + - sl_bt_external_bondingdb_data_gatt_client_config + (0x8): The remote GATT client + characteristic configurations + - sl_bt_external_bondingdb_data_gatt_client_features + (0x9): The remote GATT client supported + features + - sl_bt_external_bondingdb_data_gatt_db_hash + (0xa): Latest local GATT database hash + value that the remote client has seen for GATT + robust caching feature */ + uint8array data; /**< Bonding data */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_s sl_bt_evt_external_bondingdb_data_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data + +/** + * @addtogroup sl_bt_evt_external_bondingdb_data_ready sl_bt_evt_external_bondingdb_data_ready + * @{ + * @brief Indicates that stack has received all the necessary bonding data from + * the application and is now fully functional + */ + +/** @brief Identifier of the data_ready event */ +#define sl_bt_evt_external_bondingdb_data_ready_id 0x025c00a0 + +/***************************************************************************//** + * @brief Data structure of the data_ready event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_external_bondingdb_data_ready_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_external_bondingdb_data_ready_s sl_bt_evt_external_bondingdb_data_ready_t; + +/** @} */ // end addtogroup sl_bt_evt_external_bondingdb_data_ready + +/***************************************************************************//** + * + * Set bonding data of a connection from the external bonding database. When the + * Bluetooth stack needs bonding data, it will send the request to user + * application with a @ref sl_bt_evt_external_bondingdb_data_request event that + * contains the requested data type. The application must respond to the request + * by sending data using this command. + * + * Send 0 length data to the stack with this command if the requested data is + * not available in the external bonding database. + * + * @param[in] connection Connection handle + * @param[in] type Enum @ref sl_bt_external_bondingdb_data_t. Bonding data type. + * Values: + * - sl_bt_external_bondingdb_data_remote_address (0x0): Identity + * address of the remote device, which a resolvable random address can be + * resolved to + * - sl_bt_external_bondingdb_data_remote_address_type (0x1): Type of + * the remote device identity address. Value 0 is public device address + * and 1 is static device address + * - sl_bt_external_bondingdb_data_remote_ltk (0x2): Long Term Key + * (LTK) used as central device. The value of this type must be stored + * securely. + * - sl_bt_external_bondingdb_data_local_ltk (0x3): Long Term Key + * (LTK) used as peripheral device. The value of this type must be stored + * securely. + * - sl_bt_external_bondingdb_data_remote_central_inf (0x4): + * Identification info used as a central device + * - sl_bt_external_bondingdb_data_local_central_inf (0x5): + * Identification info used as a central device + * - sl_bt_external_bondingdb_data_irk (0x6): Identity Resolving Key + * (IRK) of the remote device that is used for resolving its RPA addresses + * when the device is in privacy mode. The value of this type must be + * stored securely. + * - sl_bt_external_bondingdb_data_meta (0x7): Metadata about the + * bonding + * - sl_bt_external_bondingdb_data_gatt_client_config (0x8): The + * remote GATT client characteristic configurations + * - sl_bt_external_bondingdb_data_gatt_client_features (0x9): The + * remote GATT client supported features + * - sl_bt_external_bondingdb_data_gatt_db_hash (0xa): Latest local + * GATT database hash value that the remote client has seen for GATT + * robust caching feature + * @param[in] data_len Length of data in @p data + * @param[in] data Bonding data + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_external_bondingdb_set_data(uint8_t connection, + uint8_t type, + size_t data_len, + const uint8_t* data); + +/** @} */ // end addtogroup sl_bt_external_bondingdb + +/** + * @addtogroup sl_bt_resolving_list Address Resolving List + * @{ + * + * @brief Address Resolving List + * + * Provides support for adding and removing devices from the Resolving List in + * controller-based privacy. + * + * Adding a peer device to the Resolving List allows the Bluetooth controller to + * resolve the address when the peer device is using privacy and is transmitting + * with a Resolvable Private Address (RPA). When the controller has resolved an + * address in a received Bluetooth packet such as an advertisement, the + * corresponding event will report the peer device's identity address even if a + * Resolvable Private Address was used over the air. + * + * When the application has added a peer device to the Resolving List, the + * application may use the peer device's identity address in commands such as + * @ref sl_bt_connection_open or @ref sl_bt_sync_scanner_open even if the peer + * device is using privacy and is using a Resolvable Private Address over the + * air. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_resolving_list_add_device_by_bonding_id 0x005d0020 +#define sl_bt_cmd_resolving_list_add_device_by_address_id 0x015d0020 +#define sl_bt_cmd_resolving_list_remove_device_by_bonding_id 0x025d0020 +#define sl_bt_cmd_resolving_list_remove_device_by_address_id 0x035d0020 +#define sl_bt_cmd_resolving_list_remove_all_devices_id 0x045d0020 +#define sl_bt_rsp_resolving_list_add_device_by_bonding_id 0x005d0020 +#define sl_bt_rsp_resolving_list_add_device_by_address_id 0x015d0020 +#define sl_bt_rsp_resolving_list_remove_device_by_bonding_id 0x025d0020 +#define sl_bt_rsp_resolving_list_remove_device_by_address_id 0x035d0020 +#define sl_bt_rsp_resolving_list_remove_all_devices_id 0x045d0020 + +/** + * @brief Specifies the Privacy Mode used for a peer device in the Resolving + * List + */ +typedef enum +{ + sl_bt_resolving_list_privacy_mode_network = 0x0, /**< (0x0) Use Network + Privacy Mode for the + peer device */ + sl_bt_resolving_list_privacy_mode_device = 0x1 /**< (0x1) Use Device Privacy + Mode for the peer device */ +} sl_bt_resolving_list_privacy_mode_t; + +/***************************************************************************//** + * + * Add a device to the Resolving List based on its bonding handle. + * + * This command is not available if the application uses the external bonding + * database provided by the component + * bluetooth_feature_external_bonding_database. In that configuration the + * application can use the command @ref + * sl_bt_resolving_list_add_device_by_address and provide the peer's identity + * address and its Identity Resolving Key (IRK). + * + * @param[in] bonding The bonding handle + * @param[in] privacy_mode @parblock + * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for + * the peer device. Values: + * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network + * Privacy Mode for the peer device + * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device + * Privacy Mode for the peer device + * + * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network + * Privacy Mode for the peer device) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_add_device_by_bonding(uint32_t bonding, + uint8_t privacy_mode); + +/***************************************************************************//** + * + * Add a device to the Resolving List based on its identity address and its + * Identity Resolving Key (IRK). + * + * This command is typically only needed when the application uses the external + * bonding database provided by the component + * bluetooth_feature_external_bonding_database. When the application uses the + * built-in bonding database, the command @ref + * sl_bt_resolving_list_add_device_by_bonding is more convenient. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * @param[in] key Identity Resolving Key (IRK) of the peer device in little + * endian format. + * @param[in] privacy_mode @parblock + * Enum @ref sl_bt_resolving_list_privacy_mode_t. The Privacy Mode to use for + * the peer device. Values: + * - sl_bt_resolving_list_privacy_mode_network (0x0): Use Network + * Privacy Mode for the peer device + * - sl_bt_resolving_list_privacy_mode_device (0x1): Use Device + * Privacy Mode for the peer device + * + * Default: @ref sl_bt_resolving_list_privacy_mode_network (Use Network + * Privacy Mode for the peer device) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_add_device_by_address(bd_addr address, + uint8_t address_type, + aes_key_128 key, + uint8_t privacy_mode); + +/***************************************************************************//** + * + * Remove a device from the Resolving List based on its bonding handle. + * + * This command is not available if the application uses the external bonding + * database provided by the component + * bluetooth_feature_external_bonding_database. In that configuration the + * application can use the command @ref + * sl_bt_resolving_list_remove_device_by_address and provide the peer's identity + * address. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Remove a device from the Resolving List based on its identity address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove all devices from the Resolving List. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_resolving_list_remove_all_devices(); + +/** @} */ // end addtogroup sl_bt_resolving_list + +/** + * @addtogroup sl_bt_accept_list Filter Accept List + * @{ + * + * @brief Filter Accept List + * + * Provides support for adding and removing devices from the Filter Accept List + * in the Bluetooth controller. + * + * The Filter Accept List allows filtering transmissions from other Bluetooth + * devices so that the local device only receives/accepts transmissions from the + * devices that it's interested in or wants to communicate with. Operations that + * support filtering provide a means to control how the Filter Accept List is + * used: + * - For advertising, use the command @ref sl_bt_advertiser_configure and @p + * flags bits @ref SL_BT_ADVERTISER_USE_FILTER_FOR_SCAN_REQUESTS and @ref + * SL_BT_ADVERTISER_USE_FILTER_FOR_CONNECTION_REQUESTS to control the + * advertising filter policy + * - For scanning, use the command @ref + * sl_bt_scanner_set_parameters_and_filter to control the scanning filter + * policy + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_accept_list_add_device_by_bonding_id 0x005e0020 +#define sl_bt_cmd_accept_list_add_device_by_address_id 0x015e0020 +#define sl_bt_cmd_accept_list_remove_device_by_bonding_id 0x025e0020 +#define sl_bt_cmd_accept_list_remove_device_by_address_id 0x035e0020 +#define sl_bt_cmd_accept_list_remove_all_devices_id 0x045e0020 +#define sl_bt_rsp_accept_list_add_device_by_bonding_id 0x005e0020 +#define sl_bt_rsp_accept_list_add_device_by_address_id 0x015e0020 +#define sl_bt_rsp_accept_list_remove_device_by_bonding_id 0x025e0020 +#define sl_bt_rsp_accept_list_remove_device_by_address_id 0x035e0020 +#define sl_bt_rsp_accept_list_remove_all_devices_id 0x045e0020 + +/***************************************************************************//** + * + * Add a device to the Filter Accept List based on its bonding handle. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_add_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Add a device to the Filter Accept List based on its identity address. + * + * Use the special address type @ref sl_bt_gap_anonymous_address to add an entry + * that matches all advertisements sent with no address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter + * Accept List entry with this type matches all advertisements sent with + * no address. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_add_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove a device from the Filter Accept List based on its bonding handle. + * + * @param[in] bonding The bonding handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_device_by_bonding(uint32_t bonding); + +/***************************************************************************//** + * + * Remove a device from the Filter Accept List based on its identity address. + * + * Use the special address type @ref sl_bt_gap_anonymous_address to remove an + * entry that matches all advertisements sent with no address. + * + * @param[in] address Bluetooth address of the peer device + * @param[in] address_type Enum @ref sl_bt_gap_address_type_t. The peer device + * address type. Values: + * - sl_bt_gap_public_address (0x0): Public device address + * - sl_bt_gap_static_address (0x1): Static device address + * - sl_bt_gap_anonymous_address (0xff): Anonymous address. A Filter + * Accept List entry with this type matches all advertisements sent with + * no address. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_device_by_address(bd_addr address, + uint8_t address_type); + +/***************************************************************************//** + * + * Remove all devices from the Filter Accept List. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_accept_list_remove_all_devices(); + +/** @} */ // end addtogroup sl_bt_accept_list + +/** + * @addtogroup sl_bt_ota OTA + * @{ + * + * @brief OTA + * + * Commands in this class are used for configuring OTA DFU using the Apploader. + * + * Note that this class is used on EFR series 1 and is not available for series + * 2 devices. The Apploader runs as a Bootloader communication plugin on series + * 2 and the Apploader plugin API supports setting device name and advertising + * data. Other configurations can be implemented in the Apploader plugin + * application space. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_ota_set_device_name_id 0x01100020 +#define sl_bt_cmd_ota_set_advertising_data_id 0x02100020 +#define sl_bt_cmd_ota_set_configuration_id 0x03100020 +#define sl_bt_cmd_ota_set_rf_path_id 0x04100020 +#define sl_bt_rsp_ota_set_device_name_id 0x01100020 +#define sl_bt_rsp_ota_set_advertising_data_id 0x02100020 +#define sl_bt_rsp_ota_set_configuration_id 0x03100020 +#define sl_bt_rsp_ota_set_rf_path_id 0x04100020 + +/***************************************************************************//** + * + * Set the device name to be used during the OTA update. The name is stored in + * the persistent store. Maximum name length is 17 bytes. + * + * Default is "OTA" if a name is not set. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] name_len Length of data in @p name + * @param[in] name OTA device name + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_device_name(size_t name_len, const uint8_t* name); + +/***************************************************************************//** + * + * Set advertising packets in OTA. Maximum 31 bytes of data can be set. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] packet_type This value selects whether data is intended for + * advertising packets or scan response packets. + * - 2: OTA advertising packets + * - 4: OTA scan response packets + * @param[in] adv_data_len Length of data in @p adv_data + * @param[in] adv_data Data to be set + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_advertising_data(uint8_t packet_type, + size_t adv_data_len, + const uint8_t* adv_data); + +/***************************************************************************//** + * + * Set OTA configuration. The setting is stored in the persistent store. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] flags @parblock + * OTA configuration flags. This value is given as a bitmask. Flags: + * + * Bit 0: Advertising address + * + * - 0: Use public device address + * - 1: Use a random address + * + * Bit 1: Application update version check. Check the version number and + * product ID of the application upgrade before applying. If the version + * number of the current application can't be determined, this implementation + * will assume that it is OK to apply the new image. Note that this is not a + * security feature. + * + * - 0: Disable version check + * - 1: Enable version check + * + * Bit 2 to 31: Reserved + * + * Default value: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_configuration(uint32_t flags); + +/***************************************************************************//** + * + * Set RF path antenna for OTA. This command should be used only if the device + * has multiple antenna ports. The setting is stored in the persistent store. + * + * Note that this command is available for EFR series 1 devices only. + * + * @param[in] enable If enabled antenna selection is used in OTA, otherwise + * default antenna is used. + * @param[in] antenna Set antenna used in OTA. Value should be come from + * RAIL_AntennaSel_t enum. See antenna path selection in RAIL + * rail_chip_specific.h. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_ota_set_rf_path(uint8_t enable, uint8_t antenna); + +/** @} */ // end addtogroup sl_bt_ota + +/** + * @addtogroup sl_bt_coex Coexistence + * @{ + * + * @brief Coexistence + * + * Coexistence BGAPI class. Coexistence interface is enabled and initialized + * with sl_bt_init_coex_hal function. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_coex_set_options_id 0x00200020 +#define sl_bt_cmd_coex_set_parameters_id 0x02200020 +#define sl_bt_cmd_coex_set_directional_priority_pulse_id 0x03200020 +#define sl_bt_cmd_coex_get_parameters_id 0x04200020 +#define sl_bt_cmd_coex_get_counters_id 0x01200020 +#define sl_bt_rsp_coex_set_options_id 0x00200020 +#define sl_bt_rsp_coex_set_parameters_id 0x02200020 +#define sl_bt_rsp_coex_set_directional_priority_pulse_id 0x03200020 +#define sl_bt_rsp_coex_get_parameters_id 0x04200020 +#define sl_bt_rsp_coex_get_counters_id 0x01200020 + +/** + * @brief Coexistence configuration options + */ +typedef enum +{ + sl_bt_coex_option_enable = 0x100, /**< (0x100) Enable coexistence + feature */ + sl_bt_coex_option_tx_abort = 0x400, /**< (0x400) Abort transmission if + grant is denied */ + sl_bt_coex_option_high_priority = 0x800 /**< (0x800) Enable priority signal */ +} sl_bt_coex_option_t; + +/***************************************************************************//** + * + * Configure coexistence options at runtime. + * + * @param[in] mask Bitmask of following coexistence options to change + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal + * @param[in] options Bitmask of following coexistence option values to set + * - @ref sl_bt_coex_option_enable : (0x100) Enable coexistence + * feature + * - @ref sl_bt_coex_option_tx_abort : (0x400) Abort transmission if + * grant is denied + * - @ref sl_bt_coex_option_high_priority : (0x800) Enable priority + * signal + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_options(uint32_t mask, uint32_t options); + +/***************************************************************************//** + * + * Configure coexistence parameters. + * + * @param[in] priority Coexistence priority threshold. Coexistence priority is + * toggled if priority is below this value. + * @param[in] request Coexistence request threshold. Coexistence request is + * toggled if priority is below this value. + * @param[in] pwm_period PWM functionality period length in 1 ms units + * @param[in] pwm_dutycycle PWM functionality duty cycle in percentage + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_parameters(uint8_t priority, + uint8_t request, + uint8_t pwm_period, + uint8_t pwm_dutycycle); + +/***************************************************************************//** + * + * Set Directional Priority Pulse Width. + * + * @param[in] pulse Directional priority pulse width in us + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_set_directional_priority_pulse(uint8_t pulse); + +/***************************************************************************//** + * + * Get the coexistence parameters. + * + * @param[out] priority Coexistence priority threshold. Coexistence priority is + * toggled if priority is below this value. + * @param[out] request Coexistence request threshold. Coexistence request is + * toggled if priority is below this value. + * @param[out] pwm_period PWM functionality period length in 1 ms units + * @param[out] pwm_dutycycle PWM functionality duty cycle in percentage + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_get_parameters(uint8_t *priority, + uint8_t *request, + uint8_t *pwm_period, + uint8_t *pwm_dutycycle); + +/***************************************************************************//** + * + * Read coexistence statistic counters from the device. Response contains the + * list of uint32 type counter values. Counters in the list are in following + * order: low priority requested, high priority requested, low priority denied, + * high priority denied, low-priority TX aborted, and high-priority TX aborted. + * Passing a non-zero value also resets counters. + * + * @param[in] reset Reset counters if parameter value is not zero. + * @param[in] max_counters_size Size of output buffer passed in @p counters + * @param[out] counters_len On return, set to the length of output data written + * to @p counters + * @param[out] counters Coexistence statistic counters + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_coex_get_counters(uint8_t reset, + size_t max_counters_size, + size_t *counters_len, + uint8_t *counters); + +/** @} */ // end addtogroup sl_bt_coex + +/** + * @addtogroup sl_bt_cs Accurate Bluetooth Ranging + * @{ + * + * @brief Accurate Bluetooth Ranging + * + * This class provides commands and events for Accurate Bluetooth Ranging (ABR) + * between Bluetooth devices. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cs_security_enable_id 0x00590020 +#define sl_bt_cmd_cs_set_default_settings_id 0x01590020 +#define sl_bt_cmd_cs_create_config_id 0x02590020 +#define sl_bt_cmd_cs_remove_config_id 0x03590020 +#define sl_bt_cmd_cs_set_channel_classification_id 0x04590020 +#define sl_bt_cmd_cs_set_procedure_parameters_id 0x05590020 +#define sl_bt_cmd_cs_procedure_enable_id 0x06590020 +#define sl_bt_cmd_cs_set_antenna_configuration_id 0x07590020 +#define sl_bt_cmd_cs_read_local_supported_capabilities_id 0x08590020 +#define sl_bt_rsp_cs_security_enable_id 0x00590020 +#define sl_bt_rsp_cs_set_default_settings_id 0x01590020 +#define sl_bt_rsp_cs_create_config_id 0x02590020 +#define sl_bt_rsp_cs_remove_config_id 0x03590020 +#define sl_bt_rsp_cs_set_channel_classification_id 0x04590020 +#define sl_bt_rsp_cs_set_procedure_parameters_id 0x05590020 +#define sl_bt_rsp_cs_procedure_enable_id 0x06590020 +#define sl_bt_rsp_cs_set_antenna_configuration_id 0x07590020 +#define sl_bt_rsp_cs_read_local_supported_capabilities_id 0x08590020 + +/** + * @brief Specifies the role for the device during ABR procedure. + */ +typedef enum +{ + sl_bt_cs_role_initiator = 0x0, /**< (0x0) The device will initiate the + procedure */ + sl_bt_cs_role_reflector = 0x1 /**< (0x1) The device will reciprocate + transmission */ +} sl_bt_cs_role_t; + +/** + * @brief Defines the status of a given role for an ABR capable device. + */ +typedef enum +{ + sl_bt_cs_role_status_disable = 0x0, /**< (0x0) The given role is disabled */ + sl_bt_cs_role_status_enable = 0x1 /**< (0x1) The given role is enabled */ +} sl_bt_cs_role_status_t; + +/** + * @brief Defines the status of a companion signal. + */ +typedef enum +{ + sl_bt_cs_companion_signal_status_disable = 0x0, /**< (0x0) The companion + signal is disabled */ + sl_bt_cs_companion_signal_status_enable = 0x1 /**< (0x1) The companion + signal is enabled */ +} sl_bt_cs_companion_signal_status_t; + +/** + * @brief Defines the ABR procedure state for the device. + */ +typedef enum +{ + sl_bt_cs_procedure_state_disabled = 0x0, /**< (0x0) ABR procedures are + disabled */ + sl_bt_cs_procedure_state_enabled = 0x1 /**< (0x1) ABR procedures are enabled */ +} sl_bt_cs_procedure_state_t; + +/** + * @brief Defines the different modes for ABR steps. + */ +typedef enum +{ + sl_bt_cs_mode_rtt = 0x1, /**< (0x1) Round Trip Time (RTT) measurement */ + sl_bt_cs_mode_pbr = 0x2, /**< (0x2) Phase-Based Ranging (PBR) + measurement */ + sl_bt_cs_submode_disabled = 0xff /**< (0xff) Submode disabled for the + procedure. */ +} sl_bt_cs_mode_t; + +/** + * @brief Defines the Round Trip Time (RTT) payload types used during the ABR + * sequence. + */ +typedef enum +{ + sl_bt_cs_rtt_type_coarse = 0x0, /**< (0x0) RTT Coarse */ + sl_bt_cs_rtt_type_fractional_96_bit_sounding = 0x2 /**< (0x2) RTT Fractional + with 96-bit Sounding + Sequence */ +} sl_bt_cs_rtt_type_t; + +/** + * @brief Specifies the ABR channel selection algorithms. + */ +typedef enum +{ + sl_bt_cs_channel_selection_algorithm_3b = 0x0, /**< (0x0) + Use + Channel + Selection + Algorithm + #3b + for + non-mode + 0 ABR + steps */ + sl_bt_cs_channel_selection_algorithm_3c = 0x1, /**< (0x1) + Use + Channel + Selection + Algorithm + #3c + for + non-mode + 0 ABR + steps */ + sl_bt_cs_channel_selection_algorithm_user_shape_interleaved = 0x2 /**< (0x2) + Use + Interleaved + shape + for + user + specified + channel + sequence */ +} sl_bt_cs_channel_selection_algorithm_t; + +/** + * @brief Specifies the ch3c shapes. + */ +typedef enum +{ + sl_bt_cs_ch3c_shape_hat = 0x0, /**< (0x0) Use Hat shape for user + specified channel sequence */ + sl_bt_cs_chc3_shape_interleaved = 0x1 /**< (0x1) Use Interleaved shape for + user specified channel sequence */ +} sl_bt_cs_ch3c_shape_t; + +/** + * @brief Describes the current status of the procedure or subevents. + */ +typedef enum +{ + sl_bt_cs_done_status_complete = 0x0, /**< (0x0) All results + complete for the + ABR procedure or + subevent */ + sl_bt_cs_done_status_partial_results_continue = 0x1, /**< (0x1) Partial + results with more + to follow */ + sl_bt_cs_done_status_current_aborted = 0xfe, /**< (0xfe) Current ABR + procedure or + subevent aborted */ + sl_bt_cs_done_status_all_aborted = 0xff /**< (0xff) Current and + all subsequent + subevents in the + procedure aborted */ +} sl_bt_cs_done_status_t; + +/** + * @brief Describes the abort reasons for ABR procedures and subevents and is + * represented by 4 bits in a byte + */ +typedef enum +{ + sl_bt_cs_abort_reason_no_abort = 0x0, /**< (0x0) Not aborted */ + sl_bt_cs_abort_reason_host_request = 0x1, /**< (0x1) Local or remote + host request */ + sl_bt_cs_abort_reason_insufficient_channels = 0x2, /**< (0x2) Filtered channel + has less than 15 + channels */ + sl_bt_cs_abort_reason_no_map_update = 0x3, /**< (0x3) Channel map + update instant has + passed */ + sl_bt_cs_abort_reason_unspecified = 0xf /**< (0xf) Unspecified + reasons for abortion */ +} sl_bt_cs_abort_reason_t; + +/** + * @brief Specifies the role for the device during ABR procedure. + */ +typedef enum +{ + sl_bt_cs_config_state_removed = 0x0, /**< (0x0) The ABR device configuration + is removed */ + sl_bt_cs_config_state_created = 0x1 /**< (0x1) The ABR device configuration + is created */ +} sl_bt_cs_config_state_t; + +/** + * @addtogroup sl_bt_evt_cs_security_enable_complete sl_bt_evt_cs_security_enable_complete + * @{ + * @brief Indicates that a locally initiated ABR security start procedure has + * completed or the local controller has responded to a channel security request + * from the remote controller + */ + +/** @brief Identifier of the security_enable_complete event */ +#define sl_bt_evt_cs_security_enable_complete_id 0x005900a0 + +/***************************************************************************//** + * @brief Data structure of the security_enable_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_security_enable_complete_s +{ + uint8_t connection; /**< Connection handle */ +}); + +typedef struct sl_bt_evt_cs_security_enable_complete_s sl_bt_evt_cs_security_enable_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_security_enable_complete + +/** + * @addtogroup sl_bt_evt_cs_config_complete sl_bt_evt_cs_config_complete + * @{ + * @brief Indicates that a locally initiated ABR configuration procedure has + * completed or the local controller has responded to an ABR configuration + * request from the remote controller + */ + +/** @brief Identifier of the config_complete event */ +#define sl_bt_evt_cs_config_complete_id 0x015900a0 + +/***************************************************************************//** + * @brief Data structure of the config_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_config_complete_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t config_id; /**< ABR configuration + identifier. + - Range: 0 to 3 */ + uint16_t status; /**< SL_STATUS_OK if + successful. Error code + otherwise. */ + uint8_t config_state; /**< Enum @ref + sl_bt_cs_config_state_t. + ABR configuration state + Values: + - sl_bt_cs_config_state_removed + (0x0): The ABR + device configuration + is removed + - sl_bt_cs_config_state_created + (0x1): The ABR + device configuration + is created */ + uint8_t main_mode_type; /**< Enum @ref + sl_bt_cs_mode_t. Main + mode type. Values: + - sl_bt_cs_mode_rtt + (0x1): Round Trip + Time (RTT) + measurement + - sl_bt_cs_mode_pbr + (0x2): + Phase-Based Ranging + (PBR) measurement + - sl_bt_cs_submode_disabled + (0xff): Submode + disabled for the + procedure. */ + uint8_t sub_mode_type; /**< Enum @ref + sl_bt_cs_mode_t. Sub mode + type. Values: + - sl_bt_cs_mode_rtt + (0x1): Round Trip + Time (RTT) + measurement + - sl_bt_cs_mode_pbr + (0x2): + Phase-Based Ranging + (PBR) measurement + - sl_bt_cs_submode_disabled + (0xff): Submode + disabled for the + procedure. */ + uint8_t min_main_mode_steps; /**< Minimum number of ABR + main mode steps to be + executed prior to a sub + mode step. + - Range: 1 to 160 */ + uint8_t max_main_mode_steps; /**< Maximum number of ABR + main mode steps to be + executed prior to a sub + mode step. + - Range: 1 to 160 */ + uint8_t main_mode_repetition; /**< Number of main mode steps + taken from the end of the + last ABR subevent to be + repeated at the beginning + of the current ABR + subevent directly after + the last Mode 0 step of + that event. + - Range: 0 to 3 */ + uint8_t mode_calibration_steps; /**< Number of calibration + mode steps to be included + at the beginning of the + test ABR subevent. + - Range: 1 to 3 */ + uint8_t role; /**< Enum @ref + sl_bt_cs_role_t. Device + role during the ABR + procedure Values: + - sl_bt_cs_role_initiator + (0x0): The device + will initiate the + procedure + - sl_bt_cs_role_reflector + (0x1): The device + will reciprocate + transmission */ + uint8_t rtt_type; /**< Enum @ref + sl_bt_cs_rtt_type_t. RTT + payload type used in the + ABR procedure Values: + - sl_bt_cs_rtt_type_coarse + (0x0): RTT Coarse + - sl_bt_cs_rtt_type_fractional_96_bit_sounding + (0x2): RTT + Fractional with + 96-bit Sounding + Sequence */ + uint8_t cs_sync_phy; /**< Enum @ref + sl_bt_gap_phy_t. Used PHY + for ABR SYNC exchanges + during a procedure + Values: + - sl_bt_gap_phy_1m + (0x1): 1M PHY */ + sl_bt_cs_channel_map_t channel_map; /**< A fixed length byte array + of 10 bytes consisting of + 79 1-bit fields. + + The nth field (in the + range 0 to 78) contains + the value for the ABR + channel index n. + + - Bit value 0: Channel + n is disabled + - Bit value 1: Channel + n is enabled + + The rest of most + significant bits are + reserved for future use + and must be set to 0. + Channels n = 0, 1, 23, + 24, 25, 77 and 78 shall + be ignored and not used + for ABR. At least 15 + channels shall be marked + as used. */ + uint8_t channel_map_repetition; /**< Number of times the + channel_map field will be + cycled through for + non-Mode 0 steps within a + ABR procedure. + - Range: 0x01 to 0xFF */ + uint8_t channel_selection_type; /**< Enum @ref + sl_bt_cs_channel_selection_algorithm_t. + ABR algorithm to be used + during the procedure for + non-mode 0 steps Value: + - sl_bt_cs_channel_selection_algorithm_3b + (0x0): Use + Channel Selection + Algorithm #3b for + non-mode 0 ABR steps + - sl_bt_cs_channel_selection_algorithm_3c + (0x1): Use + Channel Selection + Algorithm #3c for + non-mode 0 ABR steps + - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved + (0x2): Use + Interleaved shape for + user specified + channel sequence */ + uint8_t ch3c_shape; /**< Enum @ref + sl_bt_cs_ch3c_shape_t. + Shape for user-specified + channel sequence Values: + - sl_bt_cs_ch3c_shape_hat + (0x0): Use Hat + shape for user + specified channel + sequence + - sl_bt_cs_chc3_shape_interleaved + (0x1): Use + Interleaved shape for + user specified + channel sequence */ + uint8_t ch3c_jump; /**< Number of channels + skipped in each rising + and falling sequence + - Range: 0x03 to 0x08 */ + uint8_t companion_signal_enable; /**< Enum @ref + sl_bt_cs_companion_signal_status_t. + Enabled or disabled + companion signal status + Values: + - sl_bt_cs_companion_signal_status_disable + (0x0): The + companion signal is + disabled + - sl_bt_cs_companion_signal_status_enable + (0x1): The + companion signal is + enabled */ + uint8_t ip1_time_us; /**< Interlude time in + microseconds between the + RTT packets. Values: + 0x0A, 0x14, 0x1E, 0x28, + 0x32, 0x3C, 0x50, or + 0x91. All other values + are reserved for future + use. */ + uint8_t ip2_time_us; /**< Interlude time in + microseconds between the + CS tones. Values: 0x0A, + 0x14, 0x1E, 0x28, 0x32, + 0x3C, 0x50, or 0x91. All + other values are reserved + for future use. */ + uint8_t fcs_time_us; /**< Time in microseconds for + frequency changes. + Values: 0x0F, 0x14, 0x1E, + 0x28, 0x32, 0x3C, 0x50, + 0x64, 0x78, or 0x96. All + other values are reserved + for future use. */ + uint8_t pm_time_us; /**< Time in microseconds for + the phase measurement + period of the CS tones. + Values: 0x0A, 0x14, or + 0x28. All other values + are reserved for future + use. */ +}); + +typedef struct sl_bt_evt_cs_config_complete_s sl_bt_evt_cs_config_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_config_complete + +/** + * @addtogroup sl_bt_evt_cs_procedure_enable_complete sl_bt_evt_cs_procedure_enable_complete + * @{ + * @brief Indicates the controller has scheduled a new ABR procedure + * measurement, as a result of @ref sl_bt_cs_procedure_enable command or + * disabled an ongoing, as a result of @ref sl_bt_cs_procedure_enable command. + */ + +/** @brief Identifier of the procedure_enable_complete event */ +#define sl_bt_evt_cs_procedure_enable_complete_id 0x025900a0 + +/***************************************************************************//** + * @brief Data structure of the procedure_enable_complete event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_procedure_enable_complete_s +{ + uint8_t connection; /**< Connection handle */ + uint8_t config_id; /**< ABR configuration identifier. + - Range: 0 to 3 */ + uint16_t status; /**< SL_STATUS_OK if successful. Error code + otherwise. */ + uint8_t state; /**< Enum @ref sl_bt_cs_procedure_state_t. + ABR procedure enabled or disabled + Values: + - sl_bt_cs_procedure_state_disabled + (0x0): ABR procedures are + disabled + - sl_bt_cs_procedure_state_enabled + (0x1): ABR procedures are + enabled */ + uint8_t antenna_config; /**< Antenna configuration index + - Range: 0 to 7 */ + int8_t tx_power; /**< Transmit power level used in the + transmission. Units: dBm. + - Range: -127 to +20 + - Value: 0x07F. Transmit power level + is unavailable */ + uint32_t subevent_len; /**< Duration for each subevent in + microseconds + - Range: 1250 μs to 4 s */ + uint8_t subevents_per_interval; /**< Number of subevents anchored off the + same ACL connection event + - Range: 1 to 16 */ + uint16_t subevent_interval; /**< Duration in microseconds between + consecutive ABR subevents anchored off + the same ACL connection event. Units: + 0.625 ms. */ + uint16_t event_interval; /**< Number of ACL connection events between + consecutive ABR event anchor points */ + uint16_t procedure_interval; /**< Number of ACL connection events between + consecutive ABR procedure anchor points */ + uint16_t procedure_count; /**< Number of procedures to continue until + disabled. Maximum number of procedures + to be scheduled. + - Range: 0x01 to 0xFFFF. */ +}); + +typedef struct sl_bt_evt_cs_procedure_enable_complete_s sl_bt_evt_cs_procedure_enable_complete_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_procedure_enable_complete + +/** + * @addtogroup sl_bt_evt_cs_result sl_bt_evt_cs_result + * @{ + * @brief Reports results of every ABR subevent within the ABR procedure + */ + +/** @brief Identifier of the result event */ +#define sl_bt_evt_cs_result_id 0x035900a0 + +/***************************************************************************//** + * @brief Data structure of the result event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cs_result_s +{ + uint8_t connection; /**< Connection handle. Returns a + SL_BT_INVALID_CONNECTION_HANDLE (0xFF) + when triggered as a result of @ref + sl_bt_cs_test_start command */ + uint8_t config_id; /**< ABR configuration identifier + - Range: 0 to 3 */ + uint16_t start_acl_conn_event; /**< Starting an ACL connection event count + for the results reported in the event. + This is reported only in the first + subevent in the procedure. For + subsequent subevents, this value is + set to 0. */ + uint16_t procedure_counter; /**< Indicates the associated ABR procedure + count for the results reported in this + event */ + int16_t frequency_compensation; /**< Frequency compensation value. Units: + 0.01 ppm (15-bit signed integer). + - Range: -10000 to 10000 + - Value: 0xC000. Frequency + compensation value is not + available or the role is not + initiator. This is reported only + in the first subevent in the + procedure. For subsequent + subevents, this value is set to 0. */ + uint8_t procedure_done_status; /**< Enum @ref sl_bt_cs_done_status_t. + Current status of the ABR procedure + Values: + - sl_bt_cs_done_status_complete + (0x0): All results complete + for the ABR procedure or subevent + - sl_bt_cs_done_status_partial_results_continue + (0x1): Partial results with + more to follow + - sl_bt_cs_done_status_current_aborted + (0xfe): Current ABR procedure + or subevent aborted + - sl_bt_cs_done_status_all_aborted + (0xff): Current and all + subsequent subevents in the + procedure aborted */ + uint8_t subevent_done_status; /**< Enum @ref sl_bt_cs_done_status_t. + Current status of the ABR subevent + Values: + - sl_bt_cs_done_status_complete + (0x0): All results complete + for the ABR procedure or subevent + - sl_bt_cs_done_status_partial_results_continue + (0x1): Partial results with + more to follow + - sl_bt_cs_done_status_current_aborted + (0xfe): Current ABR procedure + or subevent aborted + - sl_bt_cs_done_status_all_aborted + (0xff): Current and all + subsequent subevents in the + procedure aborted */ + uint8_t abort_reason; /**< Enum @ref sl_bt_cs_abort_reason_t. + Indicates the abort reason when the + procedure_done_status or + subevent_done_status is set to 0xF, + otherwise the default value is set to + zero. The first 4 bits are related to + the procedure abort reasons and the + last 4 bits are related to the + subevent done. Values: + - sl_bt_cs_abort_reason_no_abort + (0x0): Not aborted + - sl_bt_cs_abort_reason_host_request + (0x1): Local or remote host + request + - sl_bt_cs_abort_reason_insufficient_channels + (0x2): Filtered channel has + less than 15 channels + - sl_bt_cs_abort_reason_no_map_update + (0x3): Channel map update + instant has passed + - sl_bt_cs_abort_reason_unspecified + (0xf): Unspecified reasons for + abortion */ + int8_t reference_power_level; /**< Reference power level used by the + transmission. Units: dBm. + - Range: -127 to 20 + - Value: 0x07F. The reference power + level is not applicable */ + uint8_t num_antenna_paths; /**< Number of antenna paths supported by + the local controller for the ABR tone + exchanges. + - Range: 1 to 4. The number of + antenna paths used during the + phase measurement stage of the ABR + step + - Value: 0. Phase measurement does + not occur during the ABR step, + therefore ignored */ + uint8_t num_steps; /**< Number of steps in the ABR subevent + for which results are reported. + - Range: 1 to 160 */ + uint8array data; /**< The result data is structured as + follows: + - step_status: 1 octet for each + num_steps. 0x00 for step scheduled + and reported. 0xFE for step + aborted. + - step_mode: 1 octet for each + num_steps. Mode type. Range 0 to + 3. + - step_channel: 1 octet for each + num_steps. Channel index. Range 1 + to 78. + - step_data_length: 1 octet for each + num_steps. Length of mode and role + specific information being + reported. Range 0x00 to 0xFF. + - step_data: step_data_length octet + for each corresponding steps in + num_steps. */ +}); + +typedef struct sl_bt_evt_cs_result_s sl_bt_evt_cs_result_t; + +/** @} */ // end addtogroup sl_bt_evt_cs_result + +/***************************************************************************//** + * + * Start or restart ABR security start procedure for the specified connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_security_enable_complete - Triggered when ABR security + * start procedure has completed. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_security_enable(uint8_t connection); + +/***************************************************************************//** + * + * Set the default ABR settings for the specified connection. By default, all + * roles are disabled and the antenna is set to 1. + * + * @param[in] connection Connection handle + * @param[in] initiator_status Enum @ref sl_bt_cs_role_status_t. Enable or + * disable status of the Initiator role. Values: + * - sl_bt_cs_role_status_disable (0x0): The given role is disabled + * - sl_bt_cs_role_status_enable (0x1): The given role is enabled + * @param[in] reflector_status Enum @ref sl_bt_cs_role_status_t. Enable or + * disable status of the Reflector role. Values: + * - sl_bt_cs_role_status_disable (0x0): The given role is disabled + * - sl_bt_cs_role_status_enable (0x1): The given role is enabled + * @param[in] antenna_identifier Antenna identifier to be used for ABR sync + * packets. + * - Range: 1 to 4 + * @param[in] max_tx_power Maximum transmit power level to be used in all ABR + * transmissions. Units: dBm. + * - Range: -127 to +20 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_default_settings(uint8_t connection, + uint8_t initiator_status, + uint8_t reflector_status, + uint8_t antenna_identifier, + int8_t max_tx_power); + +/***************************************************************************//** + * + * Create a new ABR configuration in the local and remote controller. The role + * used in this command must be enabled prior to issuing this command using @ref + * sl_bt_cs_set_default_settings command. + * + * @param[in] connection The connection handle + * @param[in] config_id ABR configuration identifier. + * - Range: 0 to 3 + * @param[in] create_context Defines in which device the created configuration + * will be written + * - Value: 0x00. Write ABR configuration in the local controller only + * - Value: 0x01. Write ABR configuration in both the local and remote + * controller using a configuration procedure + * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] min_main_mode_steps Minimum number of ABR main mode steps to be + * executed prior to a sub mode step. + * - Range: 1 to 160 + * @param[in] max_main_mode_steps Maximum number of ABR main mode steps to be + * executed prior to a sub mode step. + * - Range: 1 to 160 + * @param[in] main_mode_repetition Number of main mode steps taken from the end + * of the last ABR subevent to be repeated at the beginning of the current ABR + * subevent directly after the value r last Mode 0 step of that event. + * - Range: 0 to 3 + * @param[in] mode_calibration_steps Number of Mode 0 steps to be included at + * the beginning of the test ABR subevent + * - Range: 1 to 3 + * @param[in] role Enum @ref sl_bt_cs_role_t. Device's role during the ABR + * procedure Values: + * - sl_bt_cs_role_initiator (0x0): The device will initiate the + * procedure + * - sl_bt_cs_role_reflector (0x1): The device will reciprocate + * transmission + * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in + * the ABR procedure Values: + * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse + * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT + * Fractional with 96-bit Sounding Sequence + * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC + * exchanges during a procedure Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * @param[in] channel_map @parblock + * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. + * + * The nth such field (in the range 0 to 78) contains the value for the ABR + * channel index n. + * + * - Bit value 0: Channel n is disabled + * - Bit value 1: Channel n is enabled + * + * The rest of most significant bits are reserved for future use and must be + * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not + * used for ABR. At least 15 channels shall be marked as used. + * @endparblock + * @param[in] channel_map_repetition Number of times the channel_map field will + * be cycled through for non-Mode 0 steps within an ABR procedure. + * - Range: 0x01 to 0xFF + * @param[in] channel_selection_type Enum @ref + * sl_bt_cs_channel_selection_algorithm_t. Channel selection algorithm Values: + * - sl_bt_cs_channel_selection_algorithm_3b (0x0): Use Channel + * Selection Algorithm #3b for non-mode 0 ABR steps + * - sl_bt_cs_channel_selection_algorithm_3c (0x1): Use Channel + * Selection Algorithm #3c for non-mode 0 ABR steps + * - sl_bt_cs_channel_selection_algorithm_user_shape_interleaved + * (0x2): Use Interleaved shape for user specified channel sequence + * @param[in] ch3c_shape Enum @ref sl_bt_cs_ch3c_shape_t. Ch3c shape Values: + * - sl_bt_cs_ch3c_shape_hat (0x0): Use Hat shape for user specified + * channel sequence + * - sl_bt_cs_chc3_shape_interleaved (0x1): Use Interleaved shape for + * user specified channel sequence + * @param[in] ch3c_jump Number of channels skipped in each rising and falling + * sequence. + * - Range: 2 to 8 + * @param[in] companion_signal_state Enum @ref + * sl_bt_cs_companion_signal_status_t. Companion device's signal status + * Values: + * - sl_bt_cs_companion_signal_status_disable (0x0): The companion + * signal is disabled + * - sl_bt_cs_companion_signal_status_enable (0x1): The companion + * signal is enabled + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration + * procedure completed + * + ******************************************************************************/ +sl_status_t sl_bt_cs_create_config(uint8_t connection, + uint8_t config_id, + uint8_t create_context, + uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t min_main_mode_steps, + uint8_t max_main_mode_steps, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + const sl_bt_cs_channel_map_t *channel_map, + uint8_t channel_map_repetition, + uint8_t channel_selection_type, + uint8_t ch3c_shape, + uint8_t ch3c_jump, + uint8_t companion_signal_state); + +/***************************************************************************//** + * + * Remove an ABR configuration from the local controller. + * + * @param[in] connection Connection handle + * @param[in] config_id ABR configuration identifier + * - Range: 0 to 3 + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_config_complete - Triggered when an ABR configuration + * procedure is completed + * + ******************************************************************************/ +sl_status_t sl_bt_cs_remove_config(uint8_t connection, uint8_t config_id); + +/***************************************************************************//** + * + * Update the channel classification for ABR. This classification persists until + * overwritten with a subsequent command or until the system is reset. + * + * @param[in] channel_map @parblock + * A fixed length byte array of 10 bytes consisting of 79 1-bit fields. + * + * The nth field (in the range 0 to 78) contains the value for the link layer + * channel index n. + * + * - Bit value 0: Channel n is disabled. + * - Bit value 1: Channel n is enabled. + * + * The rest of most significant bits are reserved for future use and must be + * set to 0. Channels n = 0, 1, 23, 24, 25, 77 and 78 shall be ignored and not + * used for ABR. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_channel_classification(const sl_bt_cs_channel_map_t *channel_map); + +/***************************************************************************//** + * + * Set the parameters for scheduling ABR procedures with the remote device. + * + * @param[in] connection The connection handle + * @param[in] config_id ABR configuration identifier. + * - Range: 0 to 3. + * @param[in] max_procedure_len Maximum duration for each measurement procedure. + * Value in units of 0.625 ms. + * - Range: 0x0001 to 0xFFFF. + * - Time: N x 0.625ms. N being the input. + * - Time range: 0.625 ms to 40.959375 s. + * @param[in] min_procedure_interval Minimum duration in number of connection + * events between consecutive measurement procedure. + * - Range: 0x01 to 0xFFFF. + * @param[in] max_procedure_interval Maximum duration in number of connection + * events between consecutive measurement procedure. + * - Range: 0x01 to 0xFFFF. + * @param[in] max_procedure_count Maximum number of ABR procedures to be + * scheduled + * - Range: 0x01 to 0xFFFF: Maximum number of procedures to be scheduled. + * - Value: 0x00. Procedures to continue until disabled. + * @param[in] min_subevent_len Minimum suggested duration for each ABR subevent. + * Units: microseconds. + * - Range: 0x01 to 0xFFFFFF + * - Time range: 1250 us to 4s + * @param[in] max_subevent_len Maximum suggested duration for each ABR subevent. + * Units: microseconds. + * - Range: 0x01 to 0xFFFFFF + * - Time range: 1250 us to 4s + * @param[in] tone_antenna_config_selection Antenna configuration index + * - Range: 0 to 7 + * @param[in] phy Enum @ref sl_bt_gap_phy_t. PHY on which the ABR transmission + * will take place Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports + * @param[in] tx_pwr_delta Transmit power delta. Units: dB. + * - Value: 0x80. Host does not have a recommendation for transmit power + * delta + * @param[in] preferred_peer_antenna Preferred peer-ordered antenna elements to + * be used by the remote device for the antenna configuration denoted by the + * tone antenna config selection. + * - Bit 0: Use first ordered antenna element + * - Bit 1: Use second ordered antenna element + * - Bit 2: Use third ordered antenna element + * - Bit 3: Use fourth ordered antenna element + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_procedure_parameters(uint8_t connection, + uint8_t config_id, + uint16_t max_procedure_len, + uint16_t min_procedure_interval, + uint16_t max_procedure_interval, + uint16_t max_procedure_count, + uint32_t min_subevent_len, + uint32_t max_subevent_len, + uint8_t tone_antenna_config_selection, + uint8_t phy, + int8_t tx_pwr_delta, + uint8_t preferred_peer_antenna); + +/***************************************************************************//** + * + * Enable or disable scheduling ABR procedures with the remote device. + * + * @param[in] connection The connection handle + * @param[in] enable Enum @ref sl_bt_cs_procedure_state_t. Enabled or disabled + * ABR procedure state. Values: + * - sl_bt_cs_procedure_state_disabled (0x0): ABR procedures are + * disabled + * - sl_bt_cs_procedure_state_enabled (0x1): ABR procedures are + * enabled + * @param[in] config_id ABR configuration identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_procedure_enable_complete - Triggered when local + * controller has scheduled or disabled an ABR procedure measurement + * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to + * report for every ABR event within the ABR procedure + * + ******************************************************************************/ +sl_status_t sl_bt_cs_procedure_enable(uint8_t connection, + uint8_t enable, + uint8_t config_id); + +/***************************************************************************//** + * + * Set the antenna configuration for the ABR feature. + * + * @param[in] antenna_element_offset_len Length of data in @p + * antenna_element_offset + * @param[in] antenna_element_offset Offset of each antenna, each element is a + * signed 16-bit integer stored in two consecutive bytes in little-endian + * order. Units: 1 cm. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_set_antenna_configuration(size_t antenna_element_offset_len, + const uint8_t* antenna_element_offset); + +/***************************************************************************//** + * + * Read the ABR capabilities of the local controller. + * + * @param[out] num_config The number of ABR configurations supported per + * connection. + * - Range: 0x01-0x04 + * @param[out] max_consecutive_procedures The maximum number of consecutive ABR + * procedures supported. + * - 0x00: Fixed number of consecutive procedures and for an + * indefinite number of procedures until termination + * - 0x0001-0xFFFF: Maximum number of consecutive procedures + * supported + * @param[out] num_antennas The number of antenna elements available for ABR + * tone exchanges. + * - Range: 0x01-0x04 + * @param[out] max_antenna_paths The maximum number of antenna paths supported. + * - Range: 0x01-0x04 + * @param[out] roles This value is a bitmask of flags to indicate which ABR + * roles are supported by the controller. Flags: + * - 0x01, bit 0: Initiator role + * - 0x02, bit 1: Reflector role + * @param[out] optional_modes This value is a bitmask of flags to indicate which + * Optional ABR modes are supported. Flags: + * - 0x02, bit 0: Mode 3 is supported + * @param[out] rtt_capability This value is a bitmask of flags to indicate which + * Round Trip Time (RTT) ABR capabilities accuracy requirement in @p + * rtt_aa_only_n, @p rtt_sounding_n, and @p rtt_random_payload. Flags: + * - 0x01, bit 0: 10 ns time-of-flight (ToF) precision requirement + * for @p rtt_aa_only if set; otherwise 150 ns ToF + * - 0x02, bit 1: 10 ns ToF precision requirement for @p rtt_sounding + * if set; otherwise 150 ns ToF + * - 0x04, bit 2: 10 ns ToF precision requirement for @p + * rtt_random_payload if set; otherwise 150 ns ToF + * @param[out] rtt_aa_only RTT Access Address(AA) is supported by the controller + * - 0x00: RTT AA Only is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] rtt_sounding RTT Sounding is supported by the controller + * - 0x00: RTT Sounding is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] rtt_random_payload RTT Random Payload is supported by the + * controller + * - 0x00: RTT Random Payload is not supported + * - 0x01-0xFF: Number of SYNC changes needed to satisfy the precision + * requirements + * @param[out] optional_cs_sync_phys This value is a bitmask of flags to + * indicate which ABR SYNC packages supported in an specific PHY. Flags: + * - 0x02, bit 1: LE 2M PHY ABR SYNC packages are supported + * @param[out] optional_subfeatures This value is a bitmask of flags to indicate + * which Optional ABR subfeatures supported is supported. Flags: + * - 0x01, bit 0: ABR Companion Signal is supported + * - 0x02, bit 1: ABR with zero Frequency Actuation Error relative to + * Mode 0 transmissions in reflector role is supported + * - 0x04, bit 2: ABR Channel Selection Algorithm #3c is supported + * - 0x08, bit 3: ABR phase-based ranging from a sounding sequence is + * supported + * @param[out] optional_t_ip1_times This value is a bitmask of flags to indicate + * which Time for Interlude Period 1 (IP1) supported is supported. Flags: + * - 0x0001, bit 0: Time durantion of 10 microseconds is supported + * - 0x0002, bit 1: Time durantion of 20 microseconds is supported + * - 0x0004, bit 2: Time durantion of 30 microseconds is supported + * - 0x0008, bit 3: Time durantion of 40 microseconds is supported + * - 0x0010, bit 4: Time durantion of 50 microseconds is supported + * - 0x0020, bit 5: Time durantion of 60 microseconds is supported + * - 0x0040, bit 6: Time durantion of 80 microseconds is supported + * @param[out] optional_t_ip2_times This value is a bitmask of flags to indicate + * which Time for Interlude Period 2 (IP2) supported is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * - 0x0004, bit 2: Time duration of 30 microseconds is supported + * - 0x0008, bit 3: Time duration of 40 microseconds is supported + * - 0x0010, bit 4: Time duration of 50 microseconds is supported + * - 0x0020, bit 5: Time duration of 60 microseconds is supported + * - 0x0040, bit 6: Time duration of 80 microseconds is supported + * @param[out] optional_t_fcs_times This value is a bitmask of flags to indicate + * which Time for Frequency Change Spaceing (FCS) is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * - 0x0004, bit 2: Time duration of 30 microseconds is supported + * - 0x0008, bit 3: Time duration of 40 microseconds is supported + * - 0x0010, bit 4: Time duration of 50 microseconds is supported + * - 0x0020, bit 5: Time duration of 60 microseconds is supported + * - 0x0040, bit 6: Time duration of 80 microseconds is supported + * - 0x0100, bit 7: Time duration of 100 microseconds is supported + * - 0x0200, bit 8: Time duration of 120 microseconds is supported + * @param[out] optional_t_pm_times This value is a bitmask of flags to indicate + * which Time for Phase Measurement (PM) supported is supported. Flags: + * - 0x0001, bit 0: Time duration of 10 microseconds is supported + * - 0x0002, bit 1: Time duration of 20 microseconds is supported + * @param[out] t_sw_times Time in microseconds for the antenna switch period of + * the ABR tones. + * - Values: 0x02, 0x02, 0x04 and 0x0A + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cs_read_local_supported_capabilities(uint8_t *num_config, + uint16_t *max_consecutive_procedures, + uint8_t *num_antennas, + uint8_t *max_antenna_paths, + uint8_t *roles, + uint8_t *optional_modes, + uint8_t *rtt_capability, + uint8_t *rtt_aa_only, + uint8_t *rtt_sounding, + uint8_t *rtt_random_payload, + uint8_t *optional_cs_sync_phys, + uint16_t *optional_subfeatures, + uint16_t *optional_t_ip1_times, + uint16_t *optional_t_ip2_times, + uint16_t *optional_t_fcs_times, + uint16_t *optional_t_pm_times, + uint8_t *t_sw_times); + +/** @} */ // end addtogroup sl_bt_cs + +/** + * @addtogroup sl_bt_cs_test Accurate Bluetooth Ranging Test + * @{ + * + * @brief Accurate Bluetooth Ranging Test + * + * This class provides optional test commands and events for ABR between + * Bluetooth devices. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cs_test_start_id 0x005a0020 +#define sl_bt_rsp_cs_test_start_id 0x005a0020 + +/** + * @brief Defines tone extension for ABR test + */ +typedef enum +{ + sl_bt_cs_test_tone_extension_both_without = 0x0, /**< (0x0) Initiator and + Reflector tones + sent without tone + extension */ + sl_bt_cs_test_tone_extension_reflector_without = 0x1, /**< (0x1) Initiator + tone sent with + extension; + Reflector tone sent + without extension */ + sl_bt_cs_test_tone_extension_initiator_without = 0x2, /**< (0x2) Initiator + tone sent without + extension; + Reflector tone sent + with extension */ + sl_bt_cs_test_tone_extension_both_with = 0x3, /**< (0x3) Initiator and + Reflector tones + sent with extension */ + sl_bt_cs_test_tone_extension_round_robin = 0x4 /**< (0x4) Loop through + values 0x00 to 0x03 */ +} sl_bt_cs_test_tone_extension_t; + +/** + * @brief This defines sounding sequence marker for ABR test + */ +typedef enum +{ + sl_bt_cs_test_sounding_sequence_marker_1 = 0x0, /**< (0x0) Use + 0b0011 as the + Sounding + Sequence marker */ + sl_bt_cs_test_sounding_sequence_marker_2 = 0x1, /**< (0x1) Use + 0b1100 as the + Sounding + Sequence marker */ + sl_bt_cs_test_sounding_sequence_marker_round_robin = 0x2 /**< (0x2) Loop + through 0b0011 + and 0b1100 */ +} sl_bt_cs_test_sounding_sequence_marker_t; + +/***************************************************************************//** + * + * Start a single ABR procedure using the given configuration. The reflector + * must be initialized before starting the initiator. To stop an ongoing test, + * use the @ref sl_bt_test_dtm_end command. + * + * @param[in] main_mode_type Enum @ref sl_bt_cs_mode_t. Main mode type. Values : + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] sub_mode_type Enum @ref sl_bt_cs_mode_t. Sub mode type. Values: + * - sl_bt_cs_mode_rtt (0x1): Round Trip Time (RTT) measurement + * - sl_bt_cs_mode_pbr (0x2): Phase-Based Ranging (PBR) measurement + * - sl_bt_cs_submode_disabled (0xff): Submode disabled for the + * procedure. + * @param[in] main_mode_repetition Number of main mode steps taken from the end + * of the last ABR subevent to be repeated at the beginning of the current ABR + * subevent directly after the last Mode 0 step of that event. + * - Range: 0 to 3 + * @param[in] mode_calibration_steps Number of calibration mode steps to be + * included at the beginning of the test ABR subevent + * - Range: 1 to 3 + * @param[in] role Enum @ref sl_bt_cs_role_t. Role during ABR procedure Values: + * - sl_bt_cs_role_initiator (0x0): The device will initiate the + * procedure + * - sl_bt_cs_role_reflector (0x1): The device will reciprocate + * transmission + * @param[in] rtt_type Enum @ref sl_bt_cs_rtt_type_t. RTT payload type used in + * the ABR procedure Values: + * - sl_bt_cs_rtt_type_coarse (0x0): RTT Coarse + * - sl_bt_cs_rtt_type_fractional_96_bit_sounding (0x2): RTT + * Fractional with 96-bit Sounding Sequence + * @param[in] cs_sync_phy Enum @ref sl_bt_gap_phy_t. Used PHY for ABR SYNC + * exchanges during a procedure Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * - sl_bt_gap_phy_any (0xff): Any PHYs the device supports + * @param[in] antenna_selection Antenna Identifier to be used for RTT packets + * - Range: 1 to 4 + * @param[in] subevent_len ABR subevent length in units of microseconds. + * @param[in] subevent_interval Interval between the start of two consecutive + * ABR events. Units: 0.625 ms. + * - Value: 0x0000. Single ABR subevent + * @param[in] tx_power Transmit power level for the transmission. Units: dBm. + * - Range: -127 to +20 + * - Value: 0x7E. Set transmitter to minimum transmit power level + * - Value: 0x7F. Set transmitter to maximum transmit power level + * @param[in] t_ip1_time Idle time in microseconds between the RTT packets + * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 + * @param[in] t_ip2_time Interlude time in microseconds between the ABR tones + * - Values: 10, 20, 30, 40, 50, 60, 80 or 145 + * @param[in] t_fcs_time Time in microseconds for frequency changes + * - Values: 15, 20, 30, 40, 50, 60, 80, 100, 120 or 150 + * @param[in] t_pm_time Time in microseconds for the phase measurement period of + * the ABR tones + * - Values: 10, 20 or 40 + * @param[in] t_sw_time Time in microseconds for the antenna switch period of + * the ABR tones + * - Values: 0, 1, 2, 4 or 10 + * @param[in] tone_antenna_config Antenna Configuration Index used during + * antenna switching + * - Range: 0 to 7 + * @param[in] companion_signal_state Enum @ref + * sl_bt_cs_companion_signal_status_t. Enable or disable status of the + * companion signal. Values: + * - sl_bt_cs_companion_signal_status_disable (0x0): The companion + * signal is disabled + * - sl_bt_cs_companion_signal_status_enable (0x1): The companion + * signal is enabled + * @param[in] drbg_nonce Antenna Configuration Index used during antenna + * switching + * - Range: 0 to 7 + * @param[in] override_config Configuration of the parameters in + * override_parameters + * - Bit 0: The channel sequence for the subevent is determined by the + * values of channel map repetition, channel length, and channel + * parameters. + * - Bit 2: The number of main mode ABR steps to be executed before a sub + * mode ABR step during the ABR procedure is determined by the value of + * main mode steps parameter. + * - Bit 3: The transmission of tone extensions within each Mode 2 or Mode 3 + * step is determined by the value of T_PM_Tone_Ext parameter. + * - Bit 4: The Tone antenna permutation index for each Mode 2 or Mode 3 + * step is determined by the value of Tone_Antenna_Permutation parameter. + * - Bit 5: The ABR Access Address of all packets sent by the initiator is + * determined by ABR_SYNC_AA_Initiator parameter. The ABR Access Address + * of all packets sent by the reflector is determined by + * ABR_SYNC_AA_Reflector parameter. + * B + * - Bit 6: The Marker positions for each ABR SYNC packet with a marker is + * determined by the value of SS_Marker1_Position and SS_Marker2_Position + * parameters. + * - Bit 7: The Marker value for each marker within a ABR SYNC packet is + * determined by SS_Marker_Value parameter. + * - Bit 8: The payload of the ABR SYNC packet is determined by the value of + * ABR_SYNC_Payload_Pattern parameter. + * - Bit 10: Stable Phase test + * @param[in] override_parameters_len Length of data in @p override_parameters + * @param[in] override_parameters Variable set of parameters which are present + * dependent on the bits set in the override config parameter. + * - Bit 0: channel_map_repetition, channel_length and channel + * - Bit 2: main_mode_steps + * - Bit 3: t_pm_tone_ext + * - Bit 4: tone_antenna_permutation + * - Bit 5: aa_initiator and aa_reflector + * - Bit 6: ss_marker1_position and ss_marker2_position + * - Bit 7: ss_marker_value + * - Bit 8: ABR_SYNC_Payload_Pattern and ABR_SYNC_User_Payload + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cs_result - Triggered when local controller has results to + * report for every ABR subevent within the ABR procedure + * + ******************************************************************************/ +sl_status_t sl_bt_cs_test_start(uint8_t main_mode_type, + uint8_t sub_mode_type, + uint8_t main_mode_repetition, + uint8_t mode_calibration_steps, + uint8_t role, + uint8_t rtt_type, + uint8_t cs_sync_phy, + uint8_t antenna_selection, + const sl_bt_cs_subevent_length_t *subevent_len, + uint16_t subevent_interval, + int8_t tx_power, + uint8_t t_ip1_time, + uint8_t t_ip2_time, + uint8_t t_fcs_time, + uint8_t t_pm_time, + uint8_t t_sw_time, + uint8_t tone_antenna_config, + uint8_t companion_signal_state, + uint16_t drbg_nonce, + uint16_t override_config, + size_t override_parameters_len, + const uint8_t* override_parameters); + +/** @} */ // end addtogroup sl_bt_cs_test + +/** + * @addtogroup sl_bt_l2cap L2CAP Connection Oriented Channels + * @{ + * + * @brief L2CAP Connection Oriented Channels + * + * The commands and events in this class provide Logical Link Control and + * Adaptation Protocol (L2CAP) credit-based logical channels. + * + * An L2CAP credit-based logical channel is a logical link identified by a + * channel identifier (the @p cid parameter in the commands and events of this + * API class). These channels use a credit-based flow control mechanism. The + * credit can be configured at the channel opening and later dynamically updated + * on the channel. + * + * The Simplified Protocol/Service Multiplexer (SPSM) of a channel specifies the + * protocol or services the channel implements. It can be a value for a fixed + * service assigned by the Bluetooth SIG or a dynamically-allocated value and + * used with services defined in the GATT Server. The dynamically-assigned value + * may be used to support multiple implementations of a particular protocol. See + * the Bluetooth core specification for more details. The application specifies + * the SPSM value in a channel open request in the @p spsm parameter of the @ref + * sl_bt_l2cap_open_le_channel command. + * + * Each of the local and peer channel endpoints must specify the maximum Service + * Data Unit (SDU) size (the 'MTU' field of the L2CAP packets in the Bluetooth + * Core specification) that it can receive on the channel. The application + * specifies the maximum Service Data Unit size (the @p max_sdu parameter in + * commands and events) of the local channel endpoint. + * + * Each channel endpoint has a maximum PDU payload Size that the L2CAP layer can + * receive in a single data packet on the channel. The maximum PDU payload size + * supported by the stack for local channel endpoints is 252 bytes, which is the + * maximum data length the @ref sl_bt_evt_l2cap_channel_data event can support. + * The application specifies the max PDU payload size (the @p max_pdu parameter + * in commands and events). Additionally, the application is responsible for + * handling the segmentation from SDU to PDU and reassembly from PDU to SDU. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_l2cap_open_le_channel_id 0x01430020 +#define sl_bt_cmd_l2cap_send_le_channel_open_response_id 0x02430020 +#define sl_bt_cmd_l2cap_channel_send_data_id 0x03430020 +#define sl_bt_cmd_l2cap_channel_send_credit_id 0x04430020 +#define sl_bt_cmd_l2cap_close_channel_id 0x05430020 +#define sl_bt_rsp_l2cap_open_le_channel_id 0x01430020 +#define sl_bt_rsp_l2cap_send_le_channel_open_response_id 0x02430020 +#define sl_bt_rsp_l2cap_channel_send_data_id 0x03430020 +#define sl_bt_rsp_l2cap_channel_send_credit_id 0x04430020 +#define sl_bt_rsp_l2cap_close_channel_id 0x05430020 + +/** + * @brief Defines possible result values in the responses to credit based + * channel connection requests. + */ +typedef enum +{ + sl_bt_l2cap_connection_result_successful = 0x0, /**< (0x0) + Connection + successful */ + sl_bt_l2cap_connection_result_spsm_not_supported = 0x2, /**< (0x2) + Connection + refused + \- + SPSM + not + supported */ + sl_bt_l2cap_connection_result_no_resources_available = 0x4, /**< (0x4) + Connection + refused + \- no + resources + available */ + sl_bt_l2cap_connection_result_insufficient_authentication = 0x5, /**< (0x5) + Connection + refused + \- + insufficient + authentication */ + sl_bt_l2cap_connection_result_insufficient_authorization = 0x6, /**< (0x6) + Connection + refused + \- + insufficient + authorization */ + sl_bt_l2cap_connection_result_encryption_key_size_too_short = 0x7, /**< (0x7) + Connection + refused + \- + encryption + key + size + too + short */ + sl_bt_l2cap_connection_result_insufficient_encryption = 0x8, /**< (0x8) + Connection + refused + \- + insufficient + encryption */ + sl_bt_l2cap_connection_result_invalid_source_cid = 0x9, /**< (0x9) + Connection + refused + \- + invalid + Source + CID */ + sl_bt_l2cap_connection_result_source_cid_already_allocated = 0xa, /**< (0xa) + Connection + refused + \- + Source + CID + already + allocated */ + sl_bt_l2cap_connection_result_unacceptable_parameters = 0xb /**< (0xb) + Connection + refused + \- + unacceptable + parameters */ +} sl_bt_l2cap_connection_result_t; + +/** + * @brief Describes why a request command was rejected. + */ +typedef enum +{ + sl_bt_l2cap_command_not_understood = 0x0, /**< (0x0) Command not understood + e.g., unknown command code */ + sl_bt_l2cap_signaling_mtu_exceeded = 0x1, /**< (0x1) Command size has exceeded + the signaling MTU size */ + sl_bt_l2cap_invalid_cid_request = 0x2 /**< (0x2) An invalid CID is + included in the command */ +} sl_bt_l2cap_command_reject_reason_t; + +/** + * @brief Describes which of the request commands has been rejected. + */ +typedef enum +{ + sl_bt_l2cap_disconnection_request = 0x6, /**< (0x6) A disconnection request */ + sl_bt_l2cap_le_connection_request = 0x14, /**< (0x14) An LE credit-based + connection request */ + sl_bt_l2cap_flow_control_credit = 0x16 /**< (0x16) A Flow Control Credit + packet */ +} sl_bt_l2cap_command_code_t; + +/** + * @addtogroup sl_bt_evt_l2cap_le_channel_open_request sl_bt_evt_l2cap_le_channel_open_request + * @{ + * @brief Indicates that an LE credit-based connection request on a Bluetooth + * connection is received + * + * The application must respond with the @ref + * sl_bt_l2cap_send_le_channel_open_response command. + */ + +/** @brief Identifier of the le_channel_open_request event */ +#define sl_bt_evt_l2cap_le_channel_open_request_id 0x014300a0 + +/***************************************************************************//** + * @brief Data structure of the le_channel_open_request event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_request_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t spsm; /**< The protocol/services implemented by the peer + channel endpoint */ + uint16_t cid; /**< The channel identifier on the local device */ + uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer + channel endpoint */ + uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel + endpoint */ + uint16_t credit; /**< The initial credit value of the peer channel + endpoint, i.e., number of PDUs that the local + channel endpoint can send */ + uint16_t remote_cid; /**< The channel identifier on the peer device */ +}); + +typedef struct sl_bt_evt_l2cap_le_channel_open_request_s sl_bt_evt_l2cap_le_channel_open_request_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_request + +/** + * @addtogroup sl_bt_evt_l2cap_le_channel_open_response sl_bt_evt_l2cap_le_channel_open_response + * @{ + * @brief Indicates that an LE credit-based connection response is received + * + * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode + * implies that the logical channel is established and data can be sent or + * received on the channel. + * + * If the connection request was rejected by the peer, indicated by @p + * errorcode, the stack automatically closes the local channel and the user + * application should clean up the resources associated to the channel + * identifier. + */ + +/** @brief Identifier of the le_channel_open_response event */ +#define sl_bt_evt_l2cap_le_channel_open_response_id 0x024300a0 + +/***************************************************************************//** + * @brief Data structure of the le_channel_open_response event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_le_channel_open_response_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the + response is received */ + uint16_t cid; /**< The channel identifier on the local device */ + uint16_t max_sdu; /**< The Maximum Service Data Unit size of the peer + channel endpoint */ + uint16_t max_pdu; /**< The maximum PDU payload size of the peer channel + endpoint */ + uint16_t credit; /**< The initial credit value of the peer channel + endpoint, i.e., number of PDUs the local channel + endpoint can send */ + uint16_t errorcode; /**< Enum @ref sl_bt_l2cap_connection_result_t. + + An L2CAP error code as the outcome of the connection + request. + + Result @ref sl_bt_l2cap_connection_result_successful + indicates the connection request was accepted and + the logical channel is established. Other error code + value indicates the connection request was refused + by the peer device and other parameters of this + event must be ignored. */ + uint16_t remote_cid; /**< The channel identifier on the peer device */ +}); + +typedef struct sl_bt_evt_l2cap_le_channel_open_response_s sl_bt_evt_l2cap_le_channel_open_response_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_le_channel_open_response + +/** + * @addtogroup sl_bt_evt_l2cap_channel_data sl_bt_evt_l2cap_channel_data + * @{ + * @brief Indicates that data is received on a channel + * + * Each event should contain a K-frame of payload. The length of SDU should be + * specified in the first 2 bytes of the first K-frame. The sum of the payload + * lengths in received K-frames should be equal to the specified SDU length. + * Otherwise, application should disconnect the channel using @ref + * sl_bt_l2cap_close_channel command. The same should happen also if the SDU + * length exceeds the max_sdu of local channel endpoint. + */ + +/** @brief Identifier of the channel_data event */ +#define sl_bt_evt_l2cap_channel_data_id 0x034300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_data event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_data_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t cid; /**< The channel identifier */ + uint8array data; /**< Data received */ +}); + +typedef struct sl_bt_evt_l2cap_channel_data_s sl_bt_evt_l2cap_channel_data_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_data + +/** + * @addtogroup sl_bt_evt_l2cap_channel_credit sl_bt_evt_l2cap_channel_credit + * @{ + * @brief Indicates that flow control credits are received on a channel + * informing that the peer channel endpoint is capable of receiving more data + */ + +/** @brief Identifier of the channel_credit event */ +#define sl_bt_evt_l2cap_channel_credit_id 0x044300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_credit event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_credit_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the credit + is received */ + uint16_t cid; /**< The channel identifier */ + uint16_t credit; /**< The credit value, i.e., the additional number of + PDUs the peer channel endpoint can receive */ +}); + +typedef struct sl_bt_evt_l2cap_channel_credit_s sl_bt_evt_l2cap_channel_credit_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_credit + +/** + * @addtogroup sl_bt_evt_l2cap_channel_closed sl_bt_evt_l2cap_channel_closed + * @{ + * @brief Indicates that a credit-based logical channel is closed by the local + * or peer device. + */ + +/** @brief Identifier of the channel_closed event */ +#define sl_bt_evt_l2cap_channel_closed_id 0x054300a0 + +/***************************************************************************//** + * @brief Data structure of the channel_closed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_channel_closed_s +{ + uint8_t connection; /**< The connection handle */ + uint16_t cid; /**< The channel identifier */ + uint16_t reason; /**< The disconnection reason */ +}); + +typedef struct sl_bt_evt_l2cap_channel_closed_s sl_bt_evt_l2cap_channel_closed_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_channel_closed + +/** + * @addtogroup sl_bt_evt_l2cap_command_rejected sl_bt_evt_l2cap_command_rejected + * @{ + * @brief Indicates that the peer device rejected a command + * + * This might happen if, for example, the device does not support the feature or + * the command has an incorrect CID. + */ + +/** @brief Identifier of the command_rejected event */ +#define sl_bt_evt_l2cap_command_rejected_id 0x064300a0 + +/***************************************************************************//** + * @brief Data structure of the command_rejected event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_l2cap_command_rejected_s +{ + uint8_t connection; /**< The Bluetooth connection handle on which the event + is received */ + uint8_t code; /**< Enum @ref sl_bt_l2cap_command_code_t. Code of the + rejected command */ + uint16_t reason; /**< Enum @ref sl_bt_l2cap_command_reject_reason_t. The + rejection reason */ + uint16_t cid; /**< The channel identifier */ +}); + +typedef struct sl_bt_evt_l2cap_command_rejected_s sl_bt_evt_l2cap_command_rejected_t; + +/** @} */ // end addtogroup sl_bt_evt_l2cap_command_rejected + +/***************************************************************************//** + * + * Create and configure an L2CAP channel on a Bluetooth connection using the LE + * credit based connection request packet. Event @ref + * sl_bt_evt_l2cap_le_channel_open_response or @ref + * sl_bt_evt_l2cap_command_rejected will be received after the peer device + * responded to the request. + * + * @param[in] connection The connection handle + * @param[in] spsm The protocol/services implemented by the local channel + * endpoint + * @param[in] max_sdu @parblock + * The Maximum Service Data Unit size the local channel endpoint can accept + * + * Range: 23 to 65533. + * @endparblock + * @param[in] max_pdu @parblock + * The maximum PDU payload size the local channel endpoint can accept + * + * Range: 23 to 252. + * @endparblock + * @param[in] credit The initial credit value of the local channel endpoint, + * i.e., number of PDUs the peer channel endpoint can send + * @param[out] cid The channel identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_l2cap_command_rejected - Triggered when the peer device + * rejected the connection request. Typically a legacy peer device that does + * not support the feature could send this response. When this event is + * received under the context of opening a channel using this command, the + * stack automatically closes the local channel and the user application + * should clean up the resources associated to the channel identifier. + * - @ref sl_bt_evt_l2cap_le_channel_open_response - Triggered when an LE + * credit-based connection response has been received in response to this + * command. If the result code in @p errorcode of the event is not equal to + * @ref sl_bt_l2cap_connection_result_successful, it means that connection + * request was rejected by the peer device. In this case, the stack + * automatically closes the local channel and the user application should + * clean up the resources associated to the channel identifier. + * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an LE credit-based + * connection response has not been received within 30 seconds after this + * command has been issued. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_open_le_channel(uint8_t connection, + uint16_t spsm, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t *cid); + +/***************************************************************************//** + * + * Send an LE credit-based connection response to an LE credit-based connection + * request received in the @ref sl_bt_evt_l2cap_le_channel_open_request event. + * Result code @ref sl_bt_l2cap_connection_result_successful in @p errorcode + * implies that the logical channel is established and data can be sent or + * received on the channel. + * + * To reject the connection request, use a result code other than + * sl_bt_l2cap_connection_result_successful in @p errorcode. Other parameters in + * this command are ignored in this case. The stack automatically closes the + * local channel and the user application should clean up the resources + * associated to the channel identifier. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] max_sdu @parblock + * The Maximum Service Data Unit size the local channel endpoint can accept + * + * Range: 23 to 65533. + * @endparblock + * @param[in] max_pdu @parblock + * The maximum PDU payload size the local channel endpoint can accept + * + * Range:23 to 252. + * @endparblock + * @param[in] credit The initial credit value of the local channel endpoint, + * i.e., number of PDUs that the peer channel endpoint can send + * @param[in] errorcode Enum @ref sl_bt_l2cap_connection_result_t. An L2CAP + * error code as the outcome of the connection request + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_send_le_channel_open_response(uint8_t connection, + uint16_t cid, + uint16_t max_sdu, + uint16_t max_pdu, + uint16_t credit, + uint16_t errorcode); + +/***************************************************************************//** + * + * Send data to the peer channel endpoint on a Bluetooth connection. If the SDU + * length is larger than max_pdu size or 250 bytes, the application should + * fragment the SDU into multiple K-frames and call this command once for each + * K-frame. + * + * The first K-frame of the SDU should start with 2 bytes of SDU length followed + * with payload. Therefore, the first K-frame contains PDU length minus 2 bytes + * of the actual payload. All subsequent K-frames of the same SDU contain PDU + * length of the payload. The sum of the payload lengths for K-frames should be + * equal to the specified SDU length. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] data_len Length of data in @p data + * @param[in] data Data to be sent. The data length must not be greater than the + * lesser of the peer channel endpoint max_pdu and 252 bytes, which is the + * maximum data length this command can send. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_channel_send_data(uint8_t connection, + uint16_t cid, + size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Send flow control credits to the peer channel endpoint indicating that the + * local channel endpoint is capable of receiving more data. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * @param[in] credit @parblock + * The credit value, i.e., the additional number of PDUs the peer channel + * endpoint can send + * + * Range: 1 to 65535. + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_channel_send_credit(uint8_t connection, + uint16_t cid, + uint16_t credit); + +/***************************************************************************//** + * + * Send a disconnect request to close a credit-based logical channel. + * + * @param[in] connection The connection handle + * @param[in] cid The channel identifier + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_l2cap_channel_closed - Triggered when an credit-based + * logical channel is closed in response to this command. + * + ******************************************************************************/ +sl_status_t sl_bt_l2cap_close_channel(uint8_t connection, uint16_t cid); + +/** @} */ // end addtogroup sl_bt_l2cap + +/** + * @addtogroup sl_bt_cte_transmitter CTE Transmitter + * @{ + * + * @brief CTE Transmitter + * + * Commands and events in this class manage Constant Tone Extension (CTE) + * transmission. + * + * CTE feature is only supported by specific devices. Commands from this class + * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cte_transmitter_set_dtm_parameters_id 0x04440020 +#define sl_bt_cmd_cte_transmitter_clear_dtm_parameters_id 0x05440020 +#define sl_bt_cmd_cte_transmitter_enable_connection_cte_id 0x00440020 +#define sl_bt_cmd_cte_transmitter_disable_connection_cte_id 0x01440020 +#define sl_bt_cmd_cte_transmitter_enable_connectionless_cte_id 0x02440020 +#define sl_bt_cmd_cte_transmitter_disable_connectionless_cte_id 0x03440020 +#define sl_bt_cmd_cte_transmitter_enable_silabs_cte_id 0x06440020 +#define sl_bt_cmd_cte_transmitter_disable_silabs_cte_id 0x07440020 +#define sl_bt_rsp_cte_transmitter_set_dtm_parameters_id 0x04440020 +#define sl_bt_rsp_cte_transmitter_clear_dtm_parameters_id 0x05440020 +#define sl_bt_rsp_cte_transmitter_enable_connection_cte_id 0x00440020 +#define sl_bt_rsp_cte_transmitter_disable_connection_cte_id 0x01440020 +#define sl_bt_rsp_cte_transmitter_enable_connectionless_cte_id 0x02440020 +#define sl_bt_rsp_cte_transmitter_disable_connectionless_cte_id 0x03440020 +#define sl_bt_rsp_cte_transmitter_enable_silabs_cte_id 0x06440020 +#define sl_bt_rsp_cte_transmitter_disable_silabs_cte_id 0x07440020 + +/***************************************************************************//** + * + * Set the CTE-related parameters of the LE transmitter test. + * + * @param[in] cte_length @parblock + * The length of the Constant Tone Extension in 8 us units + * - 0: No CTE + * - 0x02 to 0x14: CTE length + * + * Default: 0 (no CTE) + * @endparblock + * @param[in] cte_type @parblock + * CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * + * Default: 0 + * @endparblock + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. This can be + * an empty array if CTE is unused. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Clear CTE-related parameters that were previously set for LE transmitter + * test. Default values will be restored for these parameters. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_clear_dtm_parameters(); + +/***************************************************************************//** + * + * Enable different types of CTE responses on a connection. CTE response will be + * sent once requested by the peer device using the CTE Request procedure. + * + * @param[in] connection Connection handle + * @param[in] cte_types CTE types. Bitmask of the following: + * - Bit 0: AoA CTE response + * - Bit 1: AoD CTE response with 1 us slots + * - Bit 2: AoD CTE response with 2 us slots + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_connection_cte(uint8_t connection, + uint8_t cte_types, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable CTE responses on a connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_connection_cte(uint8_t connection); + +/***************************************************************************//** + * + * Start a connectionless CTE transmit. CTEs will be transmitted in periodic + * advertisement packets. As a result, a periodic advertising has to be started + * prior to this command. + * + * @param[in] handle Periodic advertising handle + * @param[in] cte_length CTE length in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] cte_count The number of CTEs to be transmitted in each periodic + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_connectionless_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop the connectionless CTE transmit. + * + * @param[in] handle Periodic advertising handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_connectionless_cte(uint8_t handle); + +/***************************************************************************//** + * + * Enable Silicon Labs CTE transmit. CTEs will be transmitted in extended + * advertisement packets. As a result, extended advertising has to be started + * prior this command. + * + * @param[in] handle Advertising handle + * @param[in] cte_length CTE length in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] cte_count The number of CTEs to be transmitted in each extended + * advertising interval. Currently, only cte_count = 1 is supported. + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_enable_silabs_cte(uint8_t handle, + uint8_t cte_length, + uint8_t cte_type, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable Silicon Labs CTE transmit. + * + * @param[in] handle Advertising handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_transmitter_disable_silabs_cte(uint8_t handle); + +/** @} */ // end addtogroup sl_bt_cte_transmitter + +/** + * @addtogroup sl_bt_cte_receiver CTE Receiver + * @{ + * + * @brief CTE Receiver + * + * Commands and events in this class manage Constant Tone Extension (CTE) + * receiving. + * + * CTE feature is only supported by specific devices. Commands from this class + * will return SL_STATUS_NOT_SUPPORTED on devices that do not support CTE. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_cte_receiver_set_dtm_parameters_id 0x05450020 +#define sl_bt_cmd_cte_receiver_clear_dtm_parameters_id 0x06450020 +#define sl_bt_cmd_cte_receiver_set_sync_cte_type_id 0x09450020 +#define sl_bt_cmd_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 +#define sl_bt_cmd_cte_receiver_set_sync_receive_parameters_id 0x0b450020 +#define sl_bt_cmd_cte_receiver_configure_id 0x00450020 +#define sl_bt_cmd_cte_receiver_enable_connection_cte_id 0x01450020 +#define sl_bt_cmd_cte_receiver_disable_connection_cte_id 0x02450020 +#define sl_bt_cmd_cte_receiver_enable_connectionless_cte_id 0x03450020 +#define sl_bt_cmd_cte_receiver_disable_connectionless_cte_id 0x04450020 +#define sl_bt_cmd_cte_receiver_enable_silabs_cte_id 0x07450020 +#define sl_bt_cmd_cte_receiver_disable_silabs_cte_id 0x08450020 +#define sl_bt_rsp_cte_receiver_set_dtm_parameters_id 0x05450020 +#define sl_bt_rsp_cte_receiver_clear_dtm_parameters_id 0x06450020 +#define sl_bt_rsp_cte_receiver_set_sync_cte_type_id 0x09450020 +#define sl_bt_rsp_cte_receiver_set_default_sync_receive_parameters_id 0x0a450020 +#define sl_bt_rsp_cte_receiver_set_sync_receive_parameters_id 0x0b450020 +#define sl_bt_rsp_cte_receiver_configure_id 0x00450020 +#define sl_bt_rsp_cte_receiver_enable_connection_cte_id 0x01450020 +#define sl_bt_rsp_cte_receiver_disable_connection_cte_id 0x02450020 +#define sl_bt_rsp_cte_receiver_enable_connectionless_cte_id 0x03450020 +#define sl_bt_rsp_cte_receiver_disable_connectionless_cte_id 0x04450020 +#define sl_bt_rsp_cte_receiver_enable_silabs_cte_id 0x07450020 +#define sl_bt_rsp_cte_receiver_disable_silabs_cte_id 0x08450020 + +/** + * @addtogroup sl_bt_cte_receiver_sync_cte_type CTE type flags for limiting periodic advertising synchronization + * @{ + * + * Defines sync CTE type flags that are used to limit what types of periodic + * advertisers to sync to when scanning for periodic advertising synchronization + * or receiving periodic advertising synchronization transfers. + */ + +/** Do not sync to packets with an AoA Constant Tone Extension */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA 0x1 + +/** Do not sync to packets with an AoD Constant Tone Extension with 1 us slots + * */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US 0x2 + +/** Do not sync to packets with an AoD Constant Tone Extension with 2 us slots + * */ +#define SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US 0x4 + +/** Do not sync to packets without a Constant Tone Extension */ +#define SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY 0x10 + +/** @} */ // end CTE type flags for limiting periodic advertising synchronization + +/** + * @addtogroup sl_bt_evt_cte_receiver_dtm_iq_report sl_bt_evt_cte_receiver_dtm_iq_report + * @{ + * @brief IQ sample report from DTM CTE packets. + */ + +/** @brief Identifier of the dtm_iq_report event */ +#define sl_bt_evt_cte_receiver_dtm_iq_report_id 0x024500a0 + +/***************************************************************************//** + * @brief Data structure of the dtm_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_dtm_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the periodic advertising + train or the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_dtm_iq_report_s sl_bt_evt_cte_receiver_dtm_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_dtm_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_connection_iq_report sl_bt_evt_cte_receiver_connection_iq_report + * @{ + * @brief IQ sample report from connection CTE packets. + */ + +/** @brief Identifier of the connection_iq_report event */ +#define sl_bt_evt_cte_receiver_connection_iq_report_id 0x004500a0 + +/***************************************************************************//** + * @brief Data structure of the connection_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_connection_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint8_t connection; /**< Connection handle or periodic advertising + synchronization handle */ + uint8_t phy; /**< The PHY on which the packet is received. + - 1: 1M PHY + - 2: 2M PHY */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_connection_iq_report_s sl_bt_evt_cte_receiver_connection_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connection_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report sl_bt_evt_cte_receiver_connectionless_iq_report + * @{ + * @brief IQ sample report from connectionless CTE packets. + */ + +/** @brief Identifier of the connectionless_iq_report event */ +#define sl_bt_evt_cte_receiver_connectionless_iq_report_id 0x014500a0 + +/***************************************************************************//** + * @brief Data structure of the connectionless_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_connectionless_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + uint16_t sync; /**< Periodic advertising synchronization handle */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t event_counter; /**< The event counter of the periodic advertising + train */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_connectionless_iq_report_s sl_bt_evt_cte_receiver_connectionless_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_connectionless_iq_report + +/** + * @addtogroup sl_bt_evt_cte_receiver_silabs_iq_report sl_bt_evt_cte_receiver_silabs_iq_report + * @{ + * @brief IQ samples report from Silicon Labs CTE packets. + */ + +/** @brief Identifier of the silabs_iq_report event */ +#define sl_bt_evt_cte_receiver_silabs_iq_report_id 0x034500a0 + +/***************************************************************************//** + * @brief Data structure of the silabs_iq_report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_cte_receiver_silabs_iq_report_s +{ + uint16_t status; /**< Status of CTE IQ sampling */ + bd_addr address; /**< Bluetooth address of the remote device */ + uint8_t address_type; /**< Enum @ref sl_bt_gap_address_type_t. + + Advertiser address type. + + If the application does not include the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses the following + values: + - 0: Public address + - 1: Random address + - 255: No address provided + (anonymous advertising) + + If the application includes the + bluetooth_feature_use_accurate_api_address_types + component, @p address_type uses enum @ref + sl_bt_gap_address_type_t values: + - sl_bt_gap_public_address (0x0): + Public device address + - sl_bt_gap_static_address (0x1): + Static device address + - sl_bt_gap_random_resolvable_address + (0x2): Resolvable private random + address + - sl_bt_gap_random_nonresolvable_address + (0x3): Non-resolvable private random + address + - sl_bt_gap_anonymous_address + (0xff): No address provided + (anonymous advertising) + - sl_bt_gap_public_address_resolved_from_rpa + (0x4): Public identity address + resolved from a resolvable private + address (RPA) + - sl_bt_gap_static_address_resolved_from_rpa + (0x5): Static identity address + resolved from a resolvable private + address (RPA) */ + uint8_t phy; /**< The PHY on which the packet is received. + - 1: 1M PHY + - 2: 2M PHY */ + uint8_t channel; /**< The channel on which the CTE packet was + received */ + int8_t rssi; /**< RSSI in the received CTE packet. Unit: dBm */ + uint8_t rssi_antenna_id; /**< The ID of the antenna on which RSSI was + measured */ + uint8_t cte_type; /**< The CTE type + - 0: AoA CTE response + - 1: AoD CTE response with 1us slots + - 2: AoD CTE response with 2us slots */ + uint8_t slot_durations; /**< Slot durations + - 1: Switching and sampling slots + are 1 us each + - 2: Switching and sampling slots + are 2 us each */ + uint16_t packet_counter; /**< The event counter of the periodic advertising + train or the connection */ + uint8array samples; /**< IQ samples of the received CTE packet. I and + Q samples follow each other alternately (I, + Q, I, Q, ...) */ +}); + +typedef struct sl_bt_evt_cte_receiver_silabs_iq_report_s sl_bt_evt_cte_receiver_silabs_iq_report_t; + +/** @} */ // end addtogroup sl_bt_evt_cte_receiver_silabs_iq_report + +/***************************************************************************//** + * + * Set CTE-related parameters of LE receiver test. + * + * @param[in] cte_length @parblock + * Expected CTE length in 8 us units + * - 0: No CTE + * - 0x02 to 0x14: Expected CTE length + * + * Default: 0 (no CTE) + * @endparblock + * @param[in] cte_type @parblock + * Expected CTE type + * - 0: Expect AoA CTE + * - 1: Expect AoD CTE with 1 us slots + * - 2: Expect AoD CTE with 2 us slots + * + * Default: 0 + * @endparblock + * @param[in] slot_durations @parblock + * Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * + * Default: 1 + * @endparblock + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. This can be + * an empty array if CTE is unused. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_dtm_iq_report - Triggered when IQ samples + * have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_dtm_parameters(uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Clear CTE-related parameters that were previously set for LE receiver test. + * Default values will be restored for these parameters. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_clear_dtm_parameters(); + +/***************************************************************************//** + * + * Set the sync CTE type to limit what types of periodic advertisers to sync to + * when scanning for periodic advertising synchronization. The set parameter + * takes effect immediately for all advertisers that have not already + * established synchronization. + * + * @param[in] sync_cte_type @parblock + * Sync CTE type flags. This value can be a bitmask of multiple flags from + * @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_sync_cte_type(uint8_t sync_cte_type); + +/***************************************************************************//** + * + * Set the default parameters and the CTE type limitation for receiving Periodic + * Advertising Synchronization Transfers (PAST) over connections. The default + * parameters will be in effect for all subsequent connections and do not affect + * connections that have already opened. The parameters can be overridden for a + * specific connection using command @ref + * sl_bt_cte_receiver_set_sync_receive_parameters after the connection is + * opened. + * + * This command is relevant and available only when the application has included + * the bluetooth_feature_past_receiver component into the build. If the PAST + * receiver component is not included, this command returns the error + * SL_STATUS_NOT_AVAILABLE. + * + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (No attempt is made to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] sync_cte_type @parblock + * Sync CTE type flags to limit what types of periodic advertising trains to + * sync to when receiving sync transfers. This value can be a bitmask of + * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 (do not limit synchronization by CTE type) + * @endparblock + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_default_sync_receive_parameters(uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode); + +/***************************************************************************//** + * + * Set the parameters and the CTE type limitation for receiving Periodic + * Advertising Synchronization Transfers (PAST) over the specified connection. + * The parameters do not affect periodic advertising trains that the device has + * already synchronized to. + * + * This command is relevant and available only when the application has included + * the bluetooth_feature_past_receiver component into the build. If the PAST + * receiver component is not included, this command returns the error + * SL_STATUS_NOT_AVAILABLE. + * + * @param[in] connection Connection handle + * @param[in] mode @parblock + * Enum @ref sl_bt_past_receiver_mode_t. The mode to specify how the Bluetooth + * stack reacts when synchronization information is received. Values: + * - sl_bt_past_receiver_mode_ignore (0x0): No attempt is made to + * synchronize to a periodic advertising train for which the + * synchronization information was received. No event will be triggered + * towards the application. + * - sl_bt_past_receiver_mode_synchronize (0x1): Attempt to + * synchronize to a periodic advertising train for which the + * synchronization information was received. When the information is + * received, an event will be triggered to indicate success or failure and + * to provide the application with the periodic advertising + * synchronization handle. + * + * Default: @ref sl_bt_past_receiver_mode_ignore (Do not attempt to + * synchronize) + * @endparblock + * @param[in] skip The maximum number of periodic advertising packets that can + * be skipped after a successful receive. + * - Range: 0x0000 to 0x01F3 + * - Default value: 0 + * @param[in] timeout The maximum permitted time between successful receives. If + * this time is exceeded, synchronization is lost. Unit: 10 ms. + * - Range: 0x0A to 0x4000 + * - Unit: 10 ms + * - Time range: 100 ms to 163.84 s + * - Default value: 1000 ms + * @param[in] sync_cte_type @parblock + * Sync CTE type flags to limit what types of periodic advertising trains to + * sync to when receiving sync transfers. This value can be a bitmask of + * multiple flags from @ref sl_bt_cte_receiver_sync_cte_type. Flags: + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOA (0x01, bit 0): Do not sync + * to packets with an AoA Constant Tone Extension + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_1_US (0x02, bit 1): Do not + * sync to packets with an AoD Constant Tone Extension with 1 us slots + * - SL_BT_CTE_RECEIVER_DO_NOT_SYNC_TO_AOD_2_US (0x04, bit 2): Do not + * sync to packets with an AoD Constant Tone Extension with 2 us slots + * - SL_BT_CTE_RECEIVER_SYNC_TO_CTE_ONLY (0x10, bit 4): Do not sync + * to packets without a Constant Tone Extension + * + * Default: 0 (do not limit synchronization by CTE type) + * @endparblock + * @param[in] reporting_mode @parblock + * Enum @ref sl_bt_sync_reporting_mode_t. Specifies the initial mode for + * reporting data received in the periodic advertising train after it has + * achieved synchronization. Values: + * - sl_bt_sync_report_none (0x0): Data received in periodic + * advertising trains is not reported to the application. + * - sl_bt_sync_report_all (0x1): Data received in periodic + * advertising trains is reported to the application. + * + * Default: @ref sl_bt_sync_report_all (Data received in periodic advertising + * trains is reported to the application) + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_sync_transfer_received - Triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. This event is used only when the application + * does not include bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync components. + * - @ref sl_bt_evt_periodic_sync_transfer_received - If the application + * includes the bluetooth_feature_periodic_sync or + * bluetooth_feature_pawr_sync component, triggered after synchronization + * transfer is received for a periodic advertising train that does not have + * subevents or response slots. + * - @ref sl_bt_evt_pawr_sync_transfer_received - If the application includes + * the bluetooth_feature_pawr_sync component, triggered after + * synchronization transfer is received for a Periodic Advertising with + * Responses (PAwR) train. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_set_sync_receive_parameters(uint8_t connection, + uint8_t mode, + uint16_t skip, + uint16_t timeout, + uint8_t sync_cte_type, + uint8_t reporting_mode); + +/***************************************************************************//** + * @cond RESTRICTED + * + * Restricted/experimental API. Contact Silicon Labs sales for more information. + * + * Configure the CTE sampling mode. + * + * @param[in] flags @parblock + * Values: + * - 0: Disable raw sample mode, only picked IQ samples are reported + * (1 IQ sample pair / slot) + * - 1: Enable raw sample mode, every IQ sample is reported. + * + * Default: 0 + * @endparblock + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @endcond + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_configure(uint8_t flags); + +/***************************************************************************//** + * + * Start IQ samplings on a connection. A CTE requests will be initiated + * periodically on the given connection and IQ sampling will be made on the + * received CTE responses. + * + * @param[in] connection Connection handle + * @param[in] interval Measurement interval. CTE requests may be sent less + * often. For example, if a connection event is missed for any reason, the CTE + * request will be sent in the next connection event. + * - 0: No interval. The request is initiated only once. + * - Other values N: Initiate the request every N-th connection + * events + * @param[in] cte_length Minimum CTE length requested in 8 us units. + * - Range: 0x02 to 0x14 + * - Time Range: 16 us to 160 us + * @param[in] cte_type Requested CTE type + * - 0: AoA CTE + * - 1: AoD CTE with 1 us slots + * - 2: AoD CTE with 2 us slots + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_connection_iq_report - Triggered when IQ + * samples have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_connection_cte(uint8_t connection, + uint16_t interval, + uint8_t cte_length, + uint8_t cte_type, + uint8_t slot_durations, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop the IQ sampling on a connection. CTEs will not be requested on the given + * connection. + * + * @param[in] connection Connection handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_connection_cte(uint8_t connection); + +/***************************************************************************//** + * + * Start IQ sampling on a periodic advertising synchronization. IQ samples are + * taken on each CTE found in the periodic advertisements. + * + * @param[in] sync Periodic advertising synchronization handle + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] cte_count - 0: Sample and report all available CTEs + * - Other values: Maximum number of sampled CTEs in each periodic + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_connectionless_iq_report - Triggered when IQ + * samples have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_connectionless_cte(uint16_t sync, + uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Stop IQ sampling on a periodic advertising synchronization. + * + * @param[in] sync Periodic advertising synchronization handle + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_connectionless_cte(uint16_t sync); + +/***************************************************************************//** + * + * Enable IQ sampling of Silicon Labs CTE found in extended advertisements. + * + * @param[in] slot_durations Slot durations + * - 1: Switching and sampling slots are 1 us each + * - 2: Switching and sampling slots are 2 us each + * @param[in] cte_count - 0: Sample and report all available CTEs + * - Other values: Maximum number of sampled CTEs in each extended + * advertising interval + * @param[in] switching_pattern_len Length of data in @p switching_pattern + * @param[in] switching_pattern Antenna switching pattern. Antennas will be + * switched in this order with the antenna switch pins during CTE. If the CTE + * is longer than the switching pattern, the pattern starts over. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_cte_receiver_silabs_iq_report - Triggered when IQ samples + * of Silicon Labs CTE have been received. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_enable_silabs_cte(uint8_t slot_durations, + uint8_t cte_count, + size_t switching_pattern_len, + const uint8_t* switching_pattern); + +/***************************************************************************//** + * + * Disable IQ sampling of Silicon Labs CTE. + * + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_cte_receiver_disable_silabs_cte(); + +/** @} */ // end addtogroup sl_bt_cte_receiver + +/** + * @addtogroup sl_bt_connection_analyzer Connection Analyzer + * @{ + * + * @brief Connection Analyzer + * + * Analyze Bluetooth packets that are transmitted on the connections of external + * devices. Include component bluetooth_feature_connection_analyzer to use the + * commands and events in this class. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_connection_analyzer_start_id 0x00480020 +#define sl_bt_cmd_connection_analyzer_stop_id 0x01480020 +#define sl_bt_rsp_connection_analyzer_start_id 0x00480020 +#define sl_bt_rsp_connection_analyzer_stop_id 0x01480020 + +/** + * @addtogroup sl_bt_connection_analyzer_flags Connection Analyzer Configuration flags + * @{ + * + * Defines the configuration flags in connection analyzer. + */ + +/** Indicates a given time value, e.g., @p start_time_us in @ref + * sl_bt_connection_analyzer_start, is a value relative to the current time. */ +#define SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME 0x1 + +/** @} */ // end Connection Analyzer Configuration flags + +/** + * @addtogroup sl_bt_evt_connection_analyzer_report sl_bt_evt_connection_analyzer_report + * @{ + * @brief Triggered when packets transmitted on a connection are captured. + */ + +/** @brief Identifier of the report event */ +#define sl_bt_evt_connection_analyzer_report_id 0x004800a0 + +/***************************************************************************//** + * @brief Data structure of the report event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_analyzer_report_s +{ + uint8_t analyzer; /**< The handle of the connection analyzer */ + int8_t central_rssi; /**< RSSI measurement of the packet transmitted by + the Central device. Units: dBm. Range: -127 to + +20. */ + int8_t peripheral_rssi; /**< RSSI measurement of the packet transmitted by + the Peripheral device. Units: dBm. Range: -127 + to +20. */ +}); + +typedef struct sl_bt_evt_connection_analyzer_report_s sl_bt_evt_connection_analyzer_report_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_report + +/** + * @addtogroup sl_bt_evt_connection_analyzer_completed sl_bt_evt_connection_analyzer_completed + * @{ + * @brief Triggered when the operation of analyzing a connection is completed. + */ + +/** @brief Identifier of the completed event */ +#define sl_bt_evt_connection_analyzer_completed_id 0x014800a0 + +/***************************************************************************//** + * @brief Data structure of the completed event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_connection_analyzer_completed_s +{ + uint8_t analyzer; /**< The handle of the connection analyzer */ + uint16_t reason; /**< The reason of stopping the operation */ +}); + +typedef struct sl_bt_evt_connection_analyzer_completed_s sl_bt_evt_connection_analyzer_completed_t; + +/** @} */ // end addtogroup sl_bt_evt_connection_analyzer_completed + +/***************************************************************************//** + * + * Start to analyze another device's connection and report the RSSI + * measurements. The parameters in this command provide necessary information to + * identify the connection and schedule operations to follow its transmissions. + * + * If the other device uses Silabs' Bluetooth stack, the information of the + * connection could be retrieved with command @ref + * sl_bt_connection_get_scheduling_details. The method of passing the + * information to this device is application layer logic. + * + * @param[in] access_address Access address of the connection + * @param[in] crc_init The CRC initialization value + * @param[in] interval The connection interval. Time = Value x 1.25 ms + * @param[in] supervision_timeout The connection supervision time. Time = Value + * x 10 ms + * @param[in] central_clock_accuracy The central device's clock accuracy index + * value + * @param[in] central_phy Enum @ref sl_bt_gap_phy_t. The PHY that the Central + * device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[in] peripheral_phy Enum @ref sl_bt_gap_phy_t. The PHY that the + * Peripheral device is transmitting on. Values: + * - sl_bt_gap_phy_1m (0x1): 1M PHY + * - sl_bt_gap_phy_2m (0x2): 2M PHY + * - sl_bt_gap_phy_coded (0x4): Coded PHY, 125k (S=8) or 500k (S=2) + * @param[in] channel_selection_algorithm Enum @ref + * sl_bt_gap_channel_selection_algorithm_t. The channel selection algorithm. + * Values: + * - sl_bt_gap_channel_selection_algorithm_1 (0x0): Channel selection + * algorithm #1 + * - sl_bt_gap_channel_selection_algorithm_2 (0x1): Channel selection + * algorithm #2 + * @param[in] hop The hop increment when the channel selection algorithm #1 is + * used on the connection. Ignored if @p channel_selection_algorithm indicates + * that the connection uses channel selection algorithm #2. + * @param[in] channel_map @parblock + * 5 byte bit field in little endian format. Only the first 37 bits are used. + * Bit 0 of the first byte is channel 0, bit 0 of the second byte is channel + * 8, etc. Ignore bits 37-39 that are reserved for future use. + * + * A channel is unused when its bit is 0. A channel is used when its bit is 1. + * @endparblock + * @param[in] channel The data channel number that transmissions will use in the + * next connection event + * @param[in] event_counter The event counter of the next connection event + * @param[in] start_time_us The start time of the given connection event in + * microseconds. The semantics depend on whether the configuration flag + * SL_BT_CONNECTION_ANALYZER_RELATIVE_TIME is set in parameter @p flags: + * - When the flag is set, the value is a time relative to the current time. + * A negative value means that the start time was in the past. + * - When the flag is not set, the value is an absolute time converted from + * the PROTIMER tick. + * @param[in] flags Configuration flags. This value is a bitmask of @ref + * sl_bt_connection_analyzer_flags. + * @param[out] analyzer A handle that is assigned to the connection analyzer. + * This handle is valid only if the result code of this command is + * SL_STATUS_OK. + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + * @b Events + * - @ref sl_bt_evt_connection_analyzer_report - Triggered when a packet + * transmitted from the given device is captured. + * - @ref sl_bt_evt_connection_analyzer_completed - Triggered when analyzing a + * connection is completed in the Link Layer for some reason. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_analyzer_start(uint32_t access_address, + uint32_t crc_init, + uint16_t interval, + uint16_t supervision_timeout, + uint8_t central_clock_accuracy, + uint8_t central_phy, + uint8_t peripheral_phy, + uint8_t channel_selection_algorithm, + uint8_t hop, + const sl_bt_connection_channel_map_t *channel_map, + uint8_t channel, + uint16_t event_counter, + int32_t start_time_us, + uint32_t flags, + uint8_t *analyzer); + +/***************************************************************************//** + * + * Stop analyzing another device's Bluetooth connection. The operation is + * stopped when this command returns, and the stack does not send additional + * event. + * + * @param[in] analyzer The handle of the connection analyzer to stop + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_connection_analyzer_stop(uint8_t analyzer); + +/** @} */ // end addtogroup sl_bt_connection_analyzer + +/** + * @addtogroup sl_bt_user User Messaging + * @{ + * + * @brief User Messaging + * + * This class provides commands and events, which can be used by a NCP host and + * target to implement a communication mechanism with a custom proprietary + * protocol. An application must decide whether and how the command and event + * are used. The stack does not produce or consume any messages belonging to + * this class. + */ + +/* Command and Response IDs */ +#define sl_bt_cmd_user_message_to_target_id 0x00ff0020 +#define sl_bt_cmd_user_manage_event_filter_id 0x01ff0020 +#define sl_bt_cmd_user_reset_to_dfu_id 0x02ff0020 +#define sl_bt_rsp_user_message_to_target_id 0x00ff0020 +#define sl_bt_rsp_user_manage_event_filter_id 0x01ff0020 +#define sl_bt_rsp_user_reset_to_dfu_id 0x02ff0020 + +/** + * @addtogroup sl_bt_evt_user_message_to_host sl_bt_evt_user_message_to_host + * @{ + * @brief Used by the target application on a device to initiate communication + * and send a message to the NCP host + * + * Do not send event messages in the context of the user command handling. + */ + +/** @brief Identifier of the message_to_host event */ +#define sl_bt_evt_user_message_to_host_id 0x00ff00a0 + +/***************************************************************************//** + * @brief Data structure of the message_to_host event + ******************************************************************************/ +PACKSTRUCT( struct sl_bt_evt_user_message_to_host_s +{ + uint8array message; /**< The message */ +}); + +typedef struct sl_bt_evt_user_message_to_host_s sl_bt_evt_user_message_to_host_t; + +/** @} */ // end addtogroup sl_bt_evt_user_message_to_host + +/***************************************************************************//** + * + * Used by an NCP host to send a message to the target application on device. + * The application on the target must send the response with @ref + * sl_bt_send_rsp_user_message_to_target. + * + * @param[in] data_len Length of data in @p data + * @param[in] data The message + * @param[in] max_response_size Size of output buffer passed in @p response + * @param[out] response_len On return, set to the length of output data written + * to @p response + * @param[out] response The response message + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_user_message_to_target(size_t data_len, + const uint8_t* data, + size_t max_response_size, + size_t *response_len, + uint8_t *response); + +/***************************************************************************//** + * + * Manage NCP event filter. When the event filter is in use, API events passing + * the filter will be sent to the host and those that do not pass are discarded + * by the target. For functionality details, see the NCP component in the + * Bluetooth SDK. + * + * By default, the NCP does not use the event filter. + * + * @param[in] data_len Length of data in @p data + * @param[in] data The message for managing event filter + * + * @return SL_STATUS_OK if successful. Error code otherwise. + * + ******************************************************************************/ +sl_status_t sl_bt_user_manage_event_filter(size_t data_len, + const uint8_t* data); + +/***************************************************************************//** + * + * Reset the target device to DFU mode from the NCP host. This command is used + * by specific SDK DFU component on the target device for the functionality + * related to DFU. Do not use it in other circumstances. This command does not + * have a response. + * + * + ******************************************************************************/ +void sl_bt_user_reset_to_dfu(); + +/** @} */ // end addtogroup sl_bt_user + + +/***************************************************************************//** + * @addtogroup sl_bt_common_types BT Common Types + * @{ + * @brief BT common types + */ + +/** + * @brief Data structure of BT API messages + */ +PACKSTRUCT( struct sl_bt_msg { + /** API protocol header consisting of event identifier and data length */ + uint32_t header; + + /** Union of API event types */ + union { + uint8_t handle; + sl_bt_evt_dfu_boot_t evt_dfu_boot; /**< Data field for dfu boot event*/ + sl_bt_evt_dfu_boot_failure_t evt_dfu_boot_failure; /**< Data field for dfu boot_failure event*/ + sl_bt_evt_system_boot_t evt_system_boot; /**< Data field for system boot event*/ + sl_bt_evt_system_error_t evt_system_error; /**< Data field for system error event*/ + sl_bt_evt_system_hardware_error_t evt_system_hardware_error; /**< Data field for system hardware_error event*/ + sl_bt_evt_system_resource_exhausted_t evt_system_resource_exhausted; /**< Data field for system resource_exhausted event*/ + sl_bt_evt_system_external_signal_t evt_system_external_signal; /**< Data field for system external_signal event*/ + sl_bt_evt_system_soft_timer_t evt_system_soft_timer; /**< Data field for system soft_timer event*/ + sl_bt_evt_resource_status_t evt_resource_status; /**< Data field for resource status event*/ + sl_bt_evt_advertiser_timeout_t evt_advertiser_timeout; /**< Data field for advertiser timeout event*/ + sl_bt_evt_advertiser_scan_request_t evt_advertiser_scan_request; /**< Data field for advertiser scan_request event*/ + sl_bt_evt_periodic_advertiser_status_t evt_periodic_advertiser_status; /**< Data field for periodic_advertiser status event*/ + sl_bt_evt_scanner_legacy_advertisement_report_t evt_scanner_legacy_advertisement_report; /**< Data field for scanner legacy_advertisement_report event*/ + sl_bt_evt_scanner_extended_advertisement_report_t evt_scanner_extended_advertisement_report; /**< Data field for scanner extended_advertisement_report event*/ + sl_bt_evt_scanner_scan_report_t evt_scanner_scan_report; /**< Data field for scanner scan_report event*/ + sl_bt_evt_sync_opened_t evt_sync_opened; /**< Data field for sync opened event*/ + sl_bt_evt_sync_transfer_received_t evt_sync_transfer_received; /**< Data field for sync transfer_received event*/ + sl_bt_evt_sync_data_t evt_sync_data; /**< Data field for sync data event*/ + sl_bt_evt_sync_closed_t evt_sync_closed; /**< Data field for sync closed event*/ + sl_bt_evt_periodic_sync_opened_t evt_periodic_sync_opened; /**< Data field for periodic_sync opened event*/ + sl_bt_evt_periodic_sync_transfer_received_t evt_periodic_sync_transfer_received; /**< Data field for periodic_sync transfer_received event*/ + sl_bt_evt_periodic_sync_report_t evt_periodic_sync_report; /**< Data field for periodic_sync report event*/ + sl_bt_evt_pawr_sync_opened_t evt_pawr_sync_opened; /**< Data field for pawr_sync opened event*/ + sl_bt_evt_pawr_sync_transfer_received_t evt_pawr_sync_transfer_received; /**< Data field for pawr_sync transfer_received event*/ + sl_bt_evt_pawr_sync_subevent_report_t evt_pawr_sync_subevent_report; /**< Data field for pawr_sync subevent_report event*/ + sl_bt_evt_pawr_advertiser_subevent_data_request_t evt_pawr_advertiser_subevent_data_request; /**< Data field for pawr_advertiser subevent_data_request event*/ + sl_bt_evt_pawr_advertiser_subevent_tx_failed_t evt_pawr_advertiser_subevent_tx_failed; /**< Data field for pawr_advertiser subevent_tx_failed event*/ + sl_bt_evt_pawr_advertiser_response_report_t evt_pawr_advertiser_response_report; /**< Data field for pawr_advertiser response_report event*/ + sl_bt_evt_connection_opened_t evt_connection_opened; /**< Data field for connection opened event*/ + sl_bt_evt_connection_parameters_t evt_connection_parameters; /**< Data field for connection parameters event*/ + sl_bt_evt_connection_set_parameters_failed_t evt_connection_set_parameters_failed; /**< Data field for connection set_parameters_failed event*/ + sl_bt_evt_connection_phy_status_t evt_connection_phy_status; /**< Data field for connection phy_status event*/ + sl_bt_evt_connection_get_remote_tx_power_completed_t evt_connection_get_remote_tx_power_completed; /**< Data field for connection get_remote_tx_power_completed event*/ + sl_bt_evt_connection_tx_power_t evt_connection_tx_power; /**< Data field for connection tx_power event*/ + sl_bt_evt_connection_remote_tx_power_t evt_connection_remote_tx_power; /**< Data field for connection remote_tx_power event*/ + sl_bt_evt_connection_remote_used_features_t evt_connection_remote_used_features; /**< Data field for connection remote_used_features event*/ + sl_bt_evt_connection_data_length_t evt_connection_data_length; /**< Data field for connection data_length event*/ + sl_bt_evt_connection_statistics_t evt_connection_statistics; /**< Data field for connection statistics event*/ + sl_bt_evt_connection_closed_t evt_connection_closed; /**< Data field for connection closed event*/ + sl_bt_evt_connection_rssi_t evt_connection_rssi; /**< Data field for connection rssi event*/ + sl_bt_evt_gatt_mtu_exchanged_t evt_gatt_mtu_exchanged; /**< Data field for gatt mtu_exchanged event*/ + sl_bt_evt_gatt_service_t evt_gatt_service; /**< Data field for gatt service event*/ + sl_bt_evt_gatt_characteristic_t evt_gatt_characteristic; /**< Data field for gatt characteristic event*/ + sl_bt_evt_gatt_descriptor_t evt_gatt_descriptor; /**< Data field for gatt descriptor event*/ + sl_bt_evt_gatt_characteristic_value_t evt_gatt_characteristic_value; /**< Data field for gatt characteristic_value event*/ + sl_bt_evt_gatt_descriptor_value_t evt_gatt_descriptor_value; /**< Data field for gatt descriptor_value event*/ + sl_bt_evt_gatt_procedure_completed_t evt_gatt_procedure_completed; /**< Data field for gatt procedure_completed event*/ + sl_bt_evt_gatt_server_attribute_value_t evt_gatt_server_attribute_value; /**< Data field for gatt_server attribute_value event*/ + sl_bt_evt_gatt_server_user_read_request_t evt_gatt_server_user_read_request; /**< Data field for gatt_server user_read_request event*/ + sl_bt_evt_gatt_server_user_write_request_t evt_gatt_server_user_write_request; /**< Data field for gatt_server user_write_request event*/ + sl_bt_evt_gatt_server_characteristic_status_t evt_gatt_server_characteristic_status; /**< Data field for gatt_server characteristic_status event*/ + sl_bt_evt_gatt_server_execute_write_completed_t evt_gatt_server_execute_write_completed; /**< Data field for gatt_server execute_write_completed event*/ + sl_bt_evt_gatt_server_indication_timeout_t evt_gatt_server_indication_timeout; /**< Data field for gatt_server indication_timeout event*/ + sl_bt_evt_gatt_server_notification_tx_completed_t evt_gatt_server_notification_tx_completed; /**< Data field for gatt_server notification_tx_completed event*/ + sl_bt_evt_test_dtm_completed_t evt_test_dtm_completed; /**< Data field for test dtm_completed event*/ + sl_bt_evt_sm_passkey_display_t evt_sm_passkey_display; /**< Data field for sm passkey_display event*/ + sl_bt_evt_sm_passkey_request_t evt_sm_passkey_request; /**< Data field for sm passkey_request event*/ + sl_bt_evt_sm_confirm_passkey_t evt_sm_confirm_passkey; /**< Data field for sm confirm_passkey event*/ + sl_bt_evt_sm_bonded_t evt_sm_bonded; /**< Data field for sm bonded event*/ + sl_bt_evt_sm_bonding_failed_t evt_sm_bonding_failed; /**< Data field for sm bonding_failed event*/ + sl_bt_evt_sm_confirm_bonding_t evt_sm_confirm_bonding; /**< Data field for sm confirm_bonding event*/ + sl_bt_evt_external_bondingdb_data_request_t evt_external_bondingdb_data_request; /**< Data field for external_bondingdb data_request event*/ + sl_bt_evt_external_bondingdb_data_t evt_external_bondingdb_data; /**< Data field for external_bondingdb data event*/ + sl_bt_evt_external_bondingdb_data_ready_t evt_external_bondingdb_data_ready; /**< Data field for external_bondingdb data_ready event*/ + sl_bt_evt_cs_security_enable_complete_t evt_cs_security_enable_complete; /**< Data field for cs security_enable_complete event*/ + sl_bt_evt_cs_config_complete_t evt_cs_config_complete; /**< Data field for cs config_complete event*/ + sl_bt_evt_cs_procedure_enable_complete_t evt_cs_procedure_enable_complete; /**< Data field for cs procedure_enable_complete event*/ + sl_bt_evt_cs_result_t evt_cs_result; /**< Data field for cs result event*/ + sl_bt_evt_l2cap_le_channel_open_request_t evt_l2cap_le_channel_open_request; /**< Data field for l2cap le_channel_open_request event*/ + sl_bt_evt_l2cap_le_channel_open_response_t evt_l2cap_le_channel_open_response; /**< Data field for l2cap le_channel_open_response event*/ + sl_bt_evt_l2cap_channel_data_t evt_l2cap_channel_data; /**< Data field for l2cap channel_data event*/ + sl_bt_evt_l2cap_channel_credit_t evt_l2cap_channel_credit; /**< Data field for l2cap channel_credit event*/ + sl_bt_evt_l2cap_channel_closed_t evt_l2cap_channel_closed; /**< Data field for l2cap channel_closed event*/ + sl_bt_evt_l2cap_command_rejected_t evt_l2cap_command_rejected; /**< Data field for l2cap command_rejected event*/ + sl_bt_evt_cte_receiver_dtm_iq_report_t evt_cte_receiver_dtm_iq_report; /**< Data field for cte_receiver dtm_iq_report event*/ + sl_bt_evt_cte_receiver_connection_iq_report_t evt_cte_receiver_connection_iq_report; /**< Data field for cte_receiver connection_iq_report event*/ + sl_bt_evt_cte_receiver_connectionless_iq_report_t evt_cte_receiver_connectionless_iq_report; /**< Data field for cte_receiver connectionless_iq_report event*/ + sl_bt_evt_cte_receiver_silabs_iq_report_t evt_cte_receiver_silabs_iq_report; /**< Data field for cte_receiver silabs_iq_report event*/ + sl_bt_evt_connection_analyzer_report_t evt_connection_analyzer_report; /**< Data field for connection_analyzer report event*/ + sl_bt_evt_connection_analyzer_completed_t evt_connection_analyzer_completed; /**< Data field for connection_analyzer completed event*/ + sl_bt_evt_user_message_to_host_t evt_user_message_to_host; /**< Data field for user message_to_host event*/ + uint8_t payload[SL_BGAPI_MAX_PAYLOAD_SIZE]; + } data; +}); + +/** + * @brief Type definition for the data structure of BT API messages + */ +typedef struct sl_bt_msg sl_bt_msg_t; + +/** @} */ // end addtogroup sl_bt_common_types +/******************************************************************************/ + +/***************************************************************************//** + * @addtogroup sl_bt_utility_functions Utility Functions + * @brief Utility functions for applications on SoC + * @{ + */ + +/** + * Get the next event that requires processing by user application. Application + * is not blocked if no event is waiting. + * + * @param event the pointer for storing the new event + * @return SL_STATUS_OK if a new event is returned, or SL_STATUS_NOT_FOUND if no + * event is waiting; other value indicates an error occurred + */ +sl_status_t sl_bt_pop_event(sl_bt_msg_t* event); + +/** + * Check whether events are in queue pending for processing. + * Call @ref sl_bt_pop_event to process pending events. + * + * @return true if event is pending; false otherwise + */ +bool sl_bt_event_pending(void); + +/** + * Check whether events are in queue pending for processing and return the next + * event length in bytes if events are pending. + * Call @ref sl_bt_pop_event to process pending events. + * + * @return the next event length if event is pending; 0 otherwise + */ +uint32_t sl_bt_event_pending_len(void); + + +/** + * Run the Bluetooth stack to process scheduled tasks. Events for user + * application may be generated as a result of this operation. + */ +void sl_bt_run(); + +/** + * Handle an API command in binary format. + * + * This is provided to NCP target applications for processing commands received + * from NCP transport. This function is a synonym for a generic BGAPI function + * @ref sl_bgapi_handle_command. If the NCP application uses an RTOS, use the + * sequence documented in @ref sl_bgapi_handle_command to handle the BGAPI + * command in a thread-safe manner. + * + * @param hdr the command header + * @param data the command payload in a byte array + */ +void sl_bt_handle_command(uint32_t hdr, void* data); + +/** + * Get the response to the command currently been handled. + * + * This is provided to NCP target applications for processing commands received + * from NCP transport. This function is a synonym for a generic BGAPI function + * @ref sl_bgapi_get_command_response. + */ +static inline sl_bt_msg_t* sl_bt_get_command_response() +{ + return (sl_bt_msg_t*) sl_bgapi_get_command_response(); +} + +/** + * Priority message handler function if user application requires the use of + * PendSV interrupt. + * + * If scheduler_callback function pointer in configuration struct is something + * else than NULL, then stack will not install its own PendSV IRQ handler but + * instead uses callback/handler functions. + * + * When application receives call to the scheduler_callback function it must + * schedule the call to gecko_priority_handle function to later time to run on + * high priority thread. This callback may happen inside radio IRQ so processing + * must not block and has to happen as fast as possible. + * + * Recommended implementation: High priority thread is loop that waits on binary + * semaphore and calls gecko_priority_handler. The scheduler_callback is simple + * function that only signals the semaphore. + * + */ +void sl_bt_priority_handle(void); + +/** + * @brief Signal the Bluetooth stack that an external event has happened. + * + * Signals can be used to report status changes from interrupt context or from + * other threads to application. Signals are bits that are automatically cleared + * after application has been notified. + * + * If the Platform Core Interrupt API has been configured to use the + * CORE_ATOMIC_METHOD_BASEPRI as the implementation method of atomic sections, + * this function must not be called from an interrupt handler with a priority + * higher than CORE_ATOMIC_BASE_PRIORITY_LEVEL. + * + * @param signals is a bitmask defining active signals that are reported back to + * the application by system_external_signal-event. + * @return SL_STATUS_OK if the operation is successful, + * SL_STATUS_NO_MORE_RESOURCE indicating the request could not be processed + * due to resource limitation at the moment, or SL_STATUS_INVALID_STATE when + * the on-demand start feature is used and the stack is currently stopped. + */ +sl_status_t sl_bt_external_signal(uint32_t signals); + +/** + * Signals stack to send system_awake event when application received wakeup + * signal. + */ +void sl_bt_send_system_awake(); + +/** + * Signals stack to send system_error event when in case of an error. + */ +void sl_bt_send_system_error(uint16_t reason, uint8_t data_len, const uint8_t *data); + +/** + * Tells if a SL_BT_API message is sensitive. + * + * @param[in] message_header The header of the SL_BT_API message + * @return 1 if the message is sensitive; otherwise 0 + */ +uint8_t sl_bt_is_sensitive_message(uint32_t message_header); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_rsp_user_message_to_target_id. + * + * This a utility helping a NCP host and target application to exchange user + * data. Do not use it in SoC mode. + */ +void sl_bt_send_rsp_user_message_to_target(uint16_t result, uint8_t data_len, uint8_t *data); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_evt_user_message_to_host_id. + * + * This a utility helping a NCP host and target application to exchange user + * data. Do not use it in SoC mode. + */ +void sl_bt_send_evt_user_message_to_host(uint8_t data_len, uint8_t *data); + +/** + * Sends the NCP host a message whose SL_BT_MSG_ID is + * gecko_rsp_user_manage_event_filter_id. + * + * This a utility helping a NCP host and target application to manage event + * filter. Do not use it in SoC mode. + */ +void sl_bt_send_rsp_user_manage_event_filter(uint16_t result); + + +/** @} */ // end addtogroup sl_bt_utility_functions +/******************************************************************************/ + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h index 06cdcd6..52903bd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_api_compatibility.h @@ -1,51 +1,51 @@ -/***************************************************************************//** - * @brief BT API source code compatibility for deprecated items - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_API_COMPATIBILITY_H -#define SL_BT_API_COMPATIBILITY_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Deprecated and replaced by sl_bt_gap_phy_t. - */ -typedef enum -{ - sl_bt_gap_1m_phy = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_2m_phy = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_coded_phy = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ - sl_bt_gap_any_phys = 0xff /**< (0xff) Any PHYs the device supports */ -} sl_bt_gap_phy_type_t; - -/** - * Deprecated and replaced by sl_bt_gap_phy_coding_t. - */ -typedef enum -{ - sl_bt_gap_1m_phy_uncoded = 0x1, /**< (0x1) 1M PHY */ - sl_bt_gap_2m_phy_uncoded = 0x2, /**< (0x2) 2M PHY */ - sl_bt_gap_coded_phy_125k = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ - sl_bt_gap_coded_phy_500k = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ -} sl_bt_gap_phy_and_coding_type_t; - - -#ifdef __cplusplus -} -#endif - +/***************************************************************************//** + * @brief BT API source code compatibility for deprecated items + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_API_COMPATIBILITY_H +#define SL_BT_API_COMPATIBILITY_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Deprecated and replaced by sl_bt_gap_phy_t. + */ +typedef enum +{ + sl_bt_gap_1m_phy = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_2m_phy = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_coded_phy = 0x4, /**< (0x4) Coded PHY, 125k (S=8) or 500k (S=2) */ + sl_bt_gap_any_phys = 0xff /**< (0xff) Any PHYs the device supports */ +} sl_bt_gap_phy_type_t; + +/** + * Deprecated and replaced by sl_bt_gap_phy_coding_t. + */ +typedef enum +{ + sl_bt_gap_1m_phy_uncoded = 0x1, /**< (0x1) 1M PHY */ + sl_bt_gap_2m_phy_uncoded = 0x2, /**< (0x2) 2M PHY */ + sl_bt_gap_coded_phy_125k = 0x4, /**< (0x4) 125k Coded PHY (S=8) */ + sl_bt_gap_coded_phy_500k = 0x8 /**< (0x8) 500k Coded PHY (S=2) */ +} sl_bt_gap_phy_and_coding_type_t; + + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ll_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ll_config.h index 7cd2d9c..c37fe82 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ll_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_ll_config.h @@ -1,80 +1,80 @@ -/***************************************************************************//** - * @brief Bluetooth Link Layer configuration - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ - -#ifndef SL_BT_BLUETOOTH_LL_PRIORITIES_DEFINED -#define SL_BT_BLUETOOTH_LL_PRIORITIES_DEFINED - -typedef struct { - uint8_t scan_min; - uint8_t scan_max; - uint8_t adv_min; - uint8_t adv_max; - uint8_t conn_min; - uint8_t conn_max; - uint8_t init_min; - uint8_t init_max; - uint8_t rail_mapping_offset; - uint8_t rail_mapping_range; - uint8_t _reserved; - uint8_t adv_step; - uint8_t scan_step; - uint8_t pawr_tx_min; - uint8_t pawr_tx_max; - uint8_t pawr_rx_min; - uint8_t pawr_rx_max; -} sl_bt_bluetooth_ll_priorities; - -//Default priority configuration -#define SL_BT_BLUETOOTH_PRIORITIES_DEFAULT { 191, 143, 175, 127, 135, 0, 55, 15, 16, 16, 0, 4, 4, 15, 5, 20, 10 } - -#define SL_BT_BLUETOOTH_PA_AUTOMODE 0xff - -#include "sl_common.h" -SL_PACK_START(1) -typedef struct { - int8_t golden_rssi_min_1m; //Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ + +#ifndef SL_BT_BLUETOOTH_LL_PRIORITIES_DEFINED +#define SL_BT_BLUETOOTH_LL_PRIORITIES_DEFINED + +typedef struct { + uint8_t scan_min; + uint8_t scan_max; + uint8_t adv_min; + uint8_t adv_max; + uint8_t conn_min; + uint8_t conn_max; + uint8_t init_min; + uint8_t init_max; + uint8_t rail_mapping_offset; + uint8_t rail_mapping_range; + uint8_t _reserved; + uint8_t adv_step; + uint8_t scan_step; + uint8_t pawr_tx_min; + uint8_t pawr_tx_max; + uint8_t pawr_rx_min; + uint8_t pawr_rx_max; +} sl_bt_bluetooth_ll_priorities; + +//Default priority configuration +#define SL_BT_BLUETOOTH_PRIORITIES_DEFAULT { 191, 143, 175, 127, 135, 0, 55, 15, 16, 16, 0, 4, 4, 15, 5, 20, 10 } + +#define SL_BT_BLUETOOTH_PA_AUTOMODE 0xff + +#include "sl_common.h" +SL_PACK_START(1) +typedef struct { + int8_t golden_rssi_min_1m; //Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_STACK_CONFIG_H -#define SL_BT_STACK_CONFIG_H - -#include -#include "sl_bt_ll_config.h" - -typedef struct { - uint32_t max_buffer_memory; //!< Maximum number of bytes to use for data buffers - uint32_t linklayer_config; - sl_bt_bluetooth_ll_priorities * linklayer_priorities; //Priority configuration, if NULL uses default values -}sl_bt_stack_config_t; - -/** Flag indicating Bluetooth runs in RTOS */ -#define SL_BT_CONFIG_FLAG_RTOS 256 - -/** Flag indicating Bluetooth can allow EM2 with inaccurate LF clock */ -#define SL_BT_CONFIG_FLAG_INACCURATE_LFCLK_EM2 512 - -typedef void (*sl_bt_priority_schedule_callback)(void); -typedef void (*sl_bt_stack_schedule_callback)(void); - -#define SL_BT_RF_CONFIG_ANTENNA (1 << 0) -typedef struct { - int16_t tx_gain; // RF TX gain. Unit: 0.1 dBm. For example, -20 means -2.0 dBm (signal loss). - int16_t rx_gain; // RF RX gain. Unit: 0.1 dBm. - uint8_t flags; // bit 0 is enabling antenna config, other bits 1-7 are reserved. - uint8_t antenna; // A configuration for antenna selection. - // Value should be come from RAIL_AntennaSel_t enum. - // See antenna path selection in RAIL rail_chip_specific.h. - int16_t tx_min_power; // Minimum TX power level. Unit: 0.1 dBm. - int16_t tx_max_power; // Maximum TX power level. Unit: 0.1 dBm. -} sl_bt_rf_config_t; - -typedef struct { - uint32_t config_flags; - sl_bt_stack_config_t bluetooth; - - // GATT database (pointer of "sli_bt_gattdb_t*" type) - const void* gattdb; - - //Callback for priority scheduling, used for RTOS support. If NULL uses pendsv irq. - //This is called from Interrupt context - sl_bt_priority_schedule_callback scheduler_callback; - - //Callback for requesting Bluetooth stack scheduling, used for RTOS support - //This is called from Interrupt context - sl_bt_stack_schedule_callback stack_schedule_callback; - - uint8_t max_timers; // Max number of soft timers, up to 16, the application will use through SL_BT_API. Default: 4 - sl_bt_rf_config_t rf; -}sl_bt_configuration_t; - -#endif +/***************************************************************************//** + * @brief Bluetooth stack configuration + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_STACK_CONFIG_H +#define SL_BT_STACK_CONFIG_H + +#include +#include "sl_bt_ll_config.h" + +typedef struct { + uint32_t max_buffer_memory; //!< Maximum number of bytes to use for data buffers + uint32_t linklayer_config; + sl_bt_bluetooth_ll_priorities * linklayer_priorities; //Priority configuration, if NULL uses default values +}sl_bt_stack_config_t; + +/** Flag indicating Bluetooth runs in RTOS */ +#define SL_BT_CONFIG_FLAG_RTOS 256 + +/** Flag indicating Bluetooth can allow EM2 with inaccurate LF clock */ +#define SL_BT_CONFIG_FLAG_INACCURATE_LFCLK_EM2 512 + +typedef void (*sl_bt_priority_schedule_callback)(void); +typedef void (*sl_bt_stack_schedule_callback)(void); + +#define SL_BT_RF_CONFIG_ANTENNA (1 << 0) +typedef struct { + int16_t tx_gain; // RF TX gain. Unit: 0.1 dBm. For example, -20 means -2.0 dBm (signal loss). + int16_t rx_gain; // RF RX gain. Unit: 0.1 dBm. + uint8_t flags; // bit 0 is enabling antenna config, other bits 1-7 are reserved. + uint8_t antenna; // A configuration for antenna selection. + // Value should be come from RAIL_AntennaSel_t enum. + // See antenna path selection in RAIL rail_chip_specific.h. + int16_t tx_min_power; // Minimum TX power level. Unit: 0.1 dBm. + int16_t tx_max_power; // Maximum TX power level. Unit: 0.1 dBm. +} sl_bt_rf_config_t; + +typedef struct { + uint32_t config_flags; + sl_bt_stack_config_t bluetooth; + + // GATT database (pointer of "sli_bt_gattdb_t*" type) + const void* gattdb; + + //Callback for priority scheduling, used for RTOS support. If NULL uses pendsv irq. + //This is called from Interrupt context + sl_bt_priority_schedule_callback scheduler_callback; + + //Callback for requesting Bluetooth stack scheduling, used for RTOS support + //This is called from Interrupt context + sl_bt_stack_schedule_callback stack_schedule_callback; + + uint8_t max_timers; // Max number of soft timers, up to 16, the application will use through SL_BT_API. Default: 4 + sl_bt_rf_config_t rf; +}sl_bt_configuration_t; + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_stack_init.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_stack_init.h index 74bd365..cb4b453 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_stack_init.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_stack_init.h @@ -1,38 +1,38 @@ -/***************************************************************************//** - * @brief Initialization APIs for Bluetooth stack - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_STACK_INIT_H -#define SL_BT_STACK_INIT_H - -#include "sl_status.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Initialize the Bluetooth stack. - * - * @return SL_STATUS_OK if the initialization was successful; Other error code - * indicates a failure. - */ -sl_status_t sl_bt_stack_init(); - -#ifdef __cplusplus -} -#endif - -#endif +/***************************************************************************//** + * @brief Initialization APIs for Bluetooth stack + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_STACK_INIT_H +#define SL_BT_STACK_INIT_H + +#include "sl_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize the Bluetooth stack. + * + * @return SL_STATUS_OK if the initialization was successful; Other error code + * indicates a failure. + */ +sl_status_t sl_bt_stack_init(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h index 934163f..78fc2d6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_types.h @@ -1,22 +1,22 @@ -/***************************************************************************//** - * @brief Deprecated Bluetooth API data type header - ******************************************************************************* - * # License - * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -/* - * "sl_bt_types.h" is deprecated and replaced by "sl_bt_api.h". We include - * "sl_bt_api.h" here to maintain source code compatibility with files that only - * include "sl_bt_types.h". - */ -#include "sl_bt_api.h" +/***************************************************************************//** + * @brief Deprecated Bluetooth API data type header + ******************************************************************************* + * # License + * Copyright 2019-2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +/* + * "sl_bt_types.h" is deprecated and replaced by "sl_bt_api.h". We include + * "sl_bt_api.h" here to maintain source code compatibility with files that only + * include "sl_bt_types.h". + */ +#include "sl_bt_api.h" diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h index 66e9c9c..621010e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sl_bt_version.h @@ -1,84 +1,84 @@ -/***************************************************************************//** - * @brief Bluetooth stack version definition - ******************************************************************************* - * # License - * Copyright 2022 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_BT_VERSION_H -#define SL_BT_VERSION_H - -/***************************************************************************//** - * @addtogroup sl_bt_version Bluetooth SDK version - * @brief Bluetooth SDK version information - * @{ - */ - -/** - * @brief The major number of Bluetooth SDK version - * - * An increment indicates incompatible Bluetooth API changes. - */ -#define SL_BT_VERSION_MAJOR 7 - -/** - * @brief The minor number of Bluetooth SDK version - * - * An increment indicates new backwards compatible functionalities. - */ -#define SL_BT_VERSION_MINOR 0 - -/** - * @brief The patch number of Bluetooth SDK version - * - * An increment indicates backwards compatible bug fixes. - */ -#define SL_BT_VERSION_PATCH 1 - -/** - * @brief The build number which the Bluetooth SDK was created from - */ -#define SL_BT_VERSION_BUILD 206 - -/** - * @brief The hash value of the build the Bluetooth SDK was created from - */ -#define SL_BT_VERSION_HASH {0x5b,0x56,0x2c,0x1a,0x0e,0x64,0x78,0xa5,0x6f,0x6d,0xcd,0xd4,0x17,0x91,0x18,0x7e,0xaf,0x86,0x8e,0xf6} - -/** - * Deprecated and replaced by SL_BT_VERSION_MAJOR - */ -#define BG_VERSION_MAJOR SL_BT_VERSION_MAJOR - -/** - * Deprecated and replaced by SL_BT_VERSION_MINOR - */ -#define BG_VERSION_MINOR SL_BT_VERSION_MINOR - -/** - * Deprecated and replaced by SL_BT_VERSION_PATCH - */ -#define BG_VERSION_PATCH SL_BT_VERSION_PATCH - -/** - * Deprecated and replaced by SL_BT_VERSION_BUILD - */ -#define BG_VERSION_BUILD SL_BT_VERSION_BUILD - -/** - * Deprecated and replaced by SL_BT_VERSION_HASH - */ -#define BG_VERSION_HASH SL_BT_VERSION_HASH - -/** @} */ // end addtogroup sl_bt_version - -#endif +/***************************************************************************//** + * @brief Bluetooth stack version definition + ******************************************************************************* + * # License + * Copyright 2022 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_BT_VERSION_H +#define SL_BT_VERSION_H + +/***************************************************************************//** + * @addtogroup sl_bt_version Bluetooth SDK version + * @brief Bluetooth SDK version information + * @{ + */ + +/** + * @brief The major number of Bluetooth SDK version + * + * An increment indicates incompatible Bluetooth API changes. + */ +#define SL_BT_VERSION_MAJOR 7 + +/** + * @brief The minor number of Bluetooth SDK version + * + * An increment indicates new backwards compatible functionalities. + */ +#define SL_BT_VERSION_MINOR 0 + +/** + * @brief The patch number of Bluetooth SDK version + * + * An increment indicates backwards compatible bug fixes. + */ +#define SL_BT_VERSION_PATCH 1 + +/** + * @brief The build number which the Bluetooth SDK was created from + */ +#define SL_BT_VERSION_BUILD 206 + +/** + * @brief The hash value of the build the Bluetooth SDK was created from + */ +#define SL_BT_VERSION_HASH {0x5b,0x56,0x2c,0x1a,0x0e,0x64,0x78,0xa5,0x6f,0x6d,0xcd,0xd4,0x17,0x91,0x18,0x7e,0xaf,0x86,0x8e,0xf6} + +/** + * Deprecated and replaced by SL_BT_VERSION_MAJOR + */ +#define BG_VERSION_MAJOR SL_BT_VERSION_MAJOR + +/** + * Deprecated and replaced by SL_BT_VERSION_MINOR + */ +#define BG_VERSION_MINOR SL_BT_VERSION_MINOR + +/** + * Deprecated and replaced by SL_BT_VERSION_PATCH + */ +#define BG_VERSION_PATCH SL_BT_VERSION_PATCH + +/** + * Deprecated and replaced by SL_BT_VERSION_BUILD + */ +#define BG_VERSION_BUILD SL_BT_VERSION_BUILD + +/** + * Deprecated and replaced by SL_BT_VERSION_HASH + */ +#define BG_VERSION_HASH SL_BT_VERSION_HASH + +/** @} */ // end addtogroup sl_bt_version + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_accept_list_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_accept_list_config.h index 10ceb82..5643ff9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_accept_list_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_accept_list_config.h @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file - * @brief Configuration types for "accept_list" - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_ACCEPT_LIST_CONFIG_H -#define SLI_BT_ACCEPT_LIST_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "accept_list" - * - * See "sl_bt_accept_list_config.h" for detailed description of each - * configuration parameter. - */ -typedef struct { - uint8_t accept_list_size; ///< Set to value of SL_BT_CONFIG_ACCEPT_LIST_SIZE -} sli_bt_accept_list_config_t; - -#endif // SLI_BT_ACCEPT_LIST_CONFIG_H +/***************************************************************************//** + * @file + * @brief Configuration types for "accept_list" + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_ACCEPT_LIST_CONFIG_H +#define SLI_BT_ACCEPT_LIST_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "accept_list" + * + * See "sl_bt_accept_list_config.h" for detailed description of each + * configuration parameter. + */ +typedef struct { + uint8_t accept_list_size; ///< Set to value of SL_BT_CONFIG_ACCEPT_LIST_SIZE +} sli_bt_accept_list_config_t; + +#endif // SLI_BT_ACCEPT_LIST_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_advertiser_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_advertiser_config.h index 8778964..638afc7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_advertiser_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_advertiser_config.h @@ -1,30 +1,30 @@ -/***************************************************************************//** - * @file sli_bt_advertiser_config.h - * @brief Configuration types for "advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_ADVERTISER_CONFIG_H -#define SLI_BT_ADVERTISER_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "advertiser" - */ -typedef struct { - uint8_t max_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_ADVERTISERS -} sli_bt_advertiser_config_t; - -#endif // SLI_BT_ADVERTISER_CONFIG_H +/***************************************************************************//** + * @file sli_bt_advertiser_config.h + * @brief Configuration types for "advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_ADVERTISER_CONFIG_H +#define SLI_BT_ADVERTISER_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "advertiser" + */ +typedef struct { + uint8_t max_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_ADVERTISERS +} sli_bt_advertiser_config_t; + +#endif // SLI_BT_ADVERTISER_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_config_defs.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_config_defs.h index 0e57782..7209fa1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_config_defs.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_config_defs.h @@ -1,216 +1,216 @@ -/***************************************************************************//** - * @brief Internal types and defines for Bluetooth configuration - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_CONFIG_DEFS_H -#define SLI_BT_CONFIG_DEFS_H - -#include "sl_status.h" - -/** @brief Forward declaration of the internal feature structure */ -struct sli_bt_feature; - -/** @brief Forward declaration of the internal BGAPI class structure */ -struct sli_bgapi_class; - -/** - * @brief Forward declaration of internal feature config structure - * - * Note that this is only used as an opaque type that is never instantiated - * directly. The actual configuration structure is defined and populated in - * feature-specific files. - */ -struct sli_bt_feature_config; - -/** @brief Structure to specify the use of a feature and its configuration */ -struct sli_bt_feature_use { - const struct sli_bt_feature *feature; /**< Pointer to the feature definition */ - const struct sli_bt_feature_config *config; /**< Pointer to the feature-specific configuration */ -}; - -/** - * @brief Macro that expands to the name of a BGAPI class structure - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] class_name Short class name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, mode) \ - sli_bgapi_class_ ## category_name ## _ ## class_name ## _ ## mode - -/** - * @brief Macro to forward declare a BGAPI class structure - */ -#define SLI_BT_DECLARE_BGAPI_CLASS(category_name, class_name) \ - extern const struct sli_bgapi_class SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, full); \ - extern const struct sli_bgapi_class SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, optimized) - -#ifdef SL_BT_API_FULL -/** - * @brief Macro to declare the use of a BGAPI class - * - * This macro is used by stack-specific initialization code to declare the use - * of a BGAPI class in the array of used BGAPI classes. - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] class_name Short class name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_USE_BGAPI_CLASS(category_name, class_name) \ - & SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, full) -#else -#define SLI_BT_USE_BGAPI_CLASS(category_name, class_name) \ - & SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, optimized) -#endif - -/** - * @brief Macro that expands to the name of a feature definition structure - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - * @param[in] init_mode Feature initialization mode without quotes: init_always - * or on_demand - */ -#define SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode) \ - sli_feature_ ## category_name ## _ ## feature_name ## _ ## init_mode - -/** - * @brief Macro that expands to the name of a feature configuration structure - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) \ - sli_feature_ ## category_name ## _ ## feature_name ## _config - -/** - * @brief Macro to forward declare a feature definition structure - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_DECLARE_FEATURE(category_name, feature_name) \ - extern const struct sli_bt_feature SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_always); \ - extern const struct sli_bt_feature SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, on_demand) - -/** - * @brief Macro to forward declare an instance of a feature configuration structure - * - * This macro is used by stack-specific initialization code to declare relevant - * configuration structures before populating the array of optional features. - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_DECLARE_FEATURE_CONFIG(category_name, feature_name) \ - extern const struct sli_bt_feature_config SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) - -/** - * @brief Macro to define an instance of a feature configuration structure - * - * This macro is used by the internal feature-specific configuration files - * `sli_bt_*_config.c` to define an instance of the feature configuration - * structure. The intended use is to assign the value directly. For example: - * - * @code - * SLI_BT_DEFINE_FEATURE_CONFIG(bt, advertiser, sli_bt_advertiser_config_t) = { - * .max_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS - * }; - * @endcode - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - * @param[in] type The C language type of the configuration, for example - * sli_bt_advertiser_config_t - */ -#define SLI_BT_DEFINE_FEATURE_CONFIG(category_name, feature_name, type) \ - const type SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) - -/** - * @brief Internal helper to implement @ref SLI_BT_USE_FEATURE - * - * This macro provides the extra layer of indirection that's needed to expand - * `SLI_BT_INIT_MODE` before it's used as a parameter to @ref - * SLI_BT_FEATURE_DEFINITION_NAME(). Files that define feature uses should - * invoke @ref SLI_BT_USE_FEATURE() instead of this helper. - */ -#define SLI_BT_USE_FEATURE_MODE(category_name, feature_name, init_mode) \ - { &SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode), NULL } - -/** - * @brief Macro to declare the use of an optional feature that has no configuration - * - * This macro is used by stack-specific initialization code to declare the use - * of a feature in the array of optional features. - * - * Files that invoke this macro must define `SLI_BT_INIT_MODE` to either - * init_always or on_demand to decide the initialization mode of all features. - * When the init_always mode is used, the de-init functions are omitted to - * eliminate code that's not needed in the build. - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - */ -#define SLI_BT_USE_FEATURE(category_name, feature_name) \ - SLI_BT_USE_FEATURE_MODE(category_name, feature_name, SLI_BT_INIT_MODE) - -/** - * @brief Internal helper to implement @ref SLI_BT_USE_FEATURE_WITH_CONFIG - * - * This macro provides the extra layer of indirection that's needed to expand - * `SLI_BT_INIT_MODE` before it's used as a parameter to @ref - * SLI_BT_FEATURE_DEFINITION_NAME(). Files that define feature uses should - * invoke @ref SLI_BT_USE_FEATURE_WITH_CONFIG() instead of this helper. - */ -#define SLI_BT_USE_FEATURE_MODE_WITH_CONFIG(category_name, feature_name, init_mode, config_name) \ - { &SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode), &config_name } - -/** - * @brief Macro to declare the use of an optional feature with configuration - * - * This macro is used by stack-specific initialization code to declare the use - * of a feature in the array of optional features. - * - * Files that invoke this macro must define `SLI_BT_INIT_MODE` to either - * init_always or on_demand to decide the initialization mode of all features. - * When the init_always mode is used, the de-init functions are omitted to - * eliminate code that's not needed in the build. - * - * @param[in] category_name Short category name string without quotes, for - * example bt, btmesh, or btctrl - * @param[in] feature_name Short feature name string without quotes, for example - * advertiser or connection - * @param[in] config_name The name of the configuration structure. The caller - * should use @ref SLI_BT_FEATURE_CONFIG_NAME() to get the name of the - * configuration structure. - */ -#define SLI_BT_USE_FEATURE_WITH_CONFIG(category_name, feature_name, config_name) \ - SLI_BT_USE_FEATURE_MODE_WITH_CONFIG(category_name, feature_name, SLI_BT_INIT_MODE, config_name) - -#endif // SLI_BT_CONFIG_DEFS_H +/***************************************************************************//** + * @brief Internal types and defines for Bluetooth configuration + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_CONFIG_DEFS_H +#define SLI_BT_CONFIG_DEFS_H + +#include "sl_status.h" + +/** @brief Forward declaration of the internal feature structure */ +struct sli_bt_feature; + +/** @brief Forward declaration of the internal BGAPI class structure */ +struct sli_bgapi_class; + +/** + * @brief Forward declaration of internal feature config structure + * + * Note that this is only used as an opaque type that is never instantiated + * directly. The actual configuration structure is defined and populated in + * feature-specific files. + */ +struct sli_bt_feature_config; + +/** @brief Structure to specify the use of a feature and its configuration */ +struct sli_bt_feature_use { + const struct sli_bt_feature *feature; /**< Pointer to the feature definition */ + const struct sli_bt_feature_config *config; /**< Pointer to the feature-specific configuration */ +}; + +/** + * @brief Macro that expands to the name of a BGAPI class structure + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] class_name Short class name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, mode) \ + sli_bgapi_class_ ## category_name ## _ ## class_name ## _ ## mode + +/** + * @brief Macro to forward declare a BGAPI class structure + */ +#define SLI_BT_DECLARE_BGAPI_CLASS(category_name, class_name) \ + extern const struct sli_bgapi_class SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, full); \ + extern const struct sli_bgapi_class SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, optimized) + +#ifdef SL_BT_API_FULL +/** + * @brief Macro to declare the use of a BGAPI class + * + * This macro is used by stack-specific initialization code to declare the use + * of a BGAPI class in the array of used BGAPI classes. + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] class_name Short class name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_USE_BGAPI_CLASS(category_name, class_name) \ + & SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, full) +#else +#define SLI_BT_USE_BGAPI_CLASS(category_name, class_name) \ + & SLI_BT_BGAPI_CLASS_NAME(category_name, class_name, optimized) +#endif + +/** + * @brief Macro that expands to the name of a feature definition structure + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + * @param[in] init_mode Feature initialization mode without quotes: init_always + * or on_demand + */ +#define SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode) \ + sli_feature_ ## category_name ## _ ## feature_name ## _ ## init_mode + +/** + * @brief Macro that expands to the name of a feature configuration structure + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) \ + sli_feature_ ## category_name ## _ ## feature_name ## _config + +/** + * @brief Macro to forward declare a feature definition structure + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_DECLARE_FEATURE(category_name, feature_name) \ + extern const struct sli_bt_feature SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_always); \ + extern const struct sli_bt_feature SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, on_demand) + +/** + * @brief Macro to forward declare an instance of a feature configuration structure + * + * This macro is used by stack-specific initialization code to declare relevant + * configuration structures before populating the array of optional features. + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_DECLARE_FEATURE_CONFIG(category_name, feature_name) \ + extern const struct sli_bt_feature_config SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) + +/** + * @brief Macro to define an instance of a feature configuration structure + * + * This macro is used by the internal feature-specific configuration files + * `sli_bt_*_config.c` to define an instance of the feature configuration + * structure. The intended use is to assign the value directly. For example: + * + * @code + * SLI_BT_DEFINE_FEATURE_CONFIG(bt, advertiser, sli_bt_advertiser_config_t) = { + * .max_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS + * }; + * @endcode + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + * @param[in] type The C language type of the configuration, for example + * sli_bt_advertiser_config_t + */ +#define SLI_BT_DEFINE_FEATURE_CONFIG(category_name, feature_name, type) \ + const type SLI_BT_FEATURE_CONFIG_NAME(category_name, feature_name) + +/** + * @brief Internal helper to implement @ref SLI_BT_USE_FEATURE + * + * This macro provides the extra layer of indirection that's needed to expand + * `SLI_BT_INIT_MODE` before it's used as a parameter to @ref + * SLI_BT_FEATURE_DEFINITION_NAME(). Files that define feature uses should + * invoke @ref SLI_BT_USE_FEATURE() instead of this helper. + */ +#define SLI_BT_USE_FEATURE_MODE(category_name, feature_name, init_mode) \ + { &SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode), NULL } + +/** + * @brief Macro to declare the use of an optional feature that has no configuration + * + * This macro is used by stack-specific initialization code to declare the use + * of a feature in the array of optional features. + * + * Files that invoke this macro must define `SLI_BT_INIT_MODE` to either + * init_always or on_demand to decide the initialization mode of all features. + * When the init_always mode is used, the de-init functions are omitted to + * eliminate code that's not needed in the build. + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + */ +#define SLI_BT_USE_FEATURE(category_name, feature_name) \ + SLI_BT_USE_FEATURE_MODE(category_name, feature_name, SLI_BT_INIT_MODE) + +/** + * @brief Internal helper to implement @ref SLI_BT_USE_FEATURE_WITH_CONFIG + * + * This macro provides the extra layer of indirection that's needed to expand + * `SLI_BT_INIT_MODE` before it's used as a parameter to @ref + * SLI_BT_FEATURE_DEFINITION_NAME(). Files that define feature uses should + * invoke @ref SLI_BT_USE_FEATURE_WITH_CONFIG() instead of this helper. + */ +#define SLI_BT_USE_FEATURE_MODE_WITH_CONFIG(category_name, feature_name, init_mode, config_name) \ + { &SLI_BT_FEATURE_DEFINITION_NAME(category_name, feature_name, init_mode), &config_name } + +/** + * @brief Macro to declare the use of an optional feature with configuration + * + * This macro is used by stack-specific initialization code to declare the use + * of a feature in the array of optional features. + * + * Files that invoke this macro must define `SLI_BT_INIT_MODE` to either + * init_always or on_demand to decide the initialization mode of all features. + * When the init_always mode is used, the de-init functions are omitted to + * eliminate code that's not needed in the build. + * + * @param[in] category_name Short category name string without quotes, for + * example bt, btmesh, or btctrl + * @param[in] feature_name Short feature name string without quotes, for example + * advertiser or connection + * @param[in] config_name The name of the configuration structure. The caller + * should use @ref SLI_BT_FEATURE_CONFIG_NAME() to get the name of the + * configuration structure. + */ +#define SLI_BT_USE_FEATURE_WITH_CONFIG(category_name, feature_name, config_name) \ + SLI_BT_USE_FEATURE_MODE_WITH_CONFIG(category_name, feature_name, SLI_BT_INIT_MODE, config_name) + +#endif // SLI_BT_CONFIG_DEFS_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_connection_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_connection_config.h index ae7757a..b32f7a0 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_connection_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_connection_config.h @@ -1,31 +1,31 @@ -/***************************************************************************//** - * @file sli_bt_connection_config.h - * @brief Configuration types for "connection" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_CONNECTION_CONFIG_H -#define SLI_BT_CONNECTION_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "connection" - */ -typedef struct { - uint8_t max_connections; ///< Set to value of SL_BT_CONFIG_MAX_CONNECTIONS_SUM - uint16_t data_len; ///< Set to value of SL_BT_CONFIG_CONNECTION_DATA_LENGTH -} sli_bt_connection_config_t; - -#endif // SLI_BT_CONNECTION_CONFIG_H +/***************************************************************************//** + * @file sli_bt_connection_config.h + * @brief Configuration types for "connection" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_CONNECTION_CONFIG_H +#define SLI_BT_CONNECTION_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "connection" + */ +typedef struct { + uint8_t max_connections; ///< Set to value of SL_BT_CONFIG_MAX_CONNECTIONS_SUM + uint16_t data_len; ///< Set to value of SL_BT_CONFIG_CONNECTION_DATA_LENGTH +} sli_bt_connection_config_t; + +#endif // SLI_BT_CONNECTION_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_dynamic_gattdb_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_dynamic_gattdb_config.h index b6052fc..f91c976 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_dynamic_gattdb_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_dynamic_gattdb_config.h @@ -1,30 +1,30 @@ -/***************************************************************************//** - * @file sli_bt_dynamic_gattdb_config.h - * @brief Configuration types for "dynamic_gattdb" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_DYNAMIC_GATTDB_CONFIG_H -#define SLI_BT_DYNAMIC_GATTDB_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "dynamic_gattdb" - */ -typedef struct { - uint8_t max_dynamic_gattdbs; ///< Set to value of SL_BT_CONFIG_MAX_DYNAMIC_GATTDBS_SUM -} sli_bt_dynamic_gattdb_config_t; - -#endif // SLI_BT_DYNAMIC_GATTDB_CONFIG_H +/***************************************************************************//** + * @file sli_bt_dynamic_gattdb_config.h + * @brief Configuration types for "dynamic_gattdb" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_DYNAMIC_GATTDB_CONFIG_H +#define SLI_BT_DYNAMIC_GATTDB_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "dynamic_gattdb" + */ +typedef struct { + uint8_t max_dynamic_gattdbs; ///< Set to value of SL_BT_CONFIG_MAX_DYNAMIC_GATTDBS_SUM +} sli_bt_dynamic_gattdb_config_t; + +#endif // SLI_BT_DYNAMIC_GATTDB_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h index 20d298f..f1f0f02 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_gattdb_def.h @@ -1,108 +1,108 @@ -/***************************************************************************//** - * @brief Bluetooth GATT database structure definition - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_GATT_DEF_H -#define SLI_BT_GATT_DEF_H - -#include -#include - -typedef struct { - uint16_t len; //size of buffer - uint8_t data[]; -} sli_bt_gattdb_value_t; - -typedef struct { - uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop - uint16_t max_len; //Maximum length of data in buffer - uint16_t len; //current size of data in buffer - uint8_t data[]; //size is max_len -} sli_bt_gattdb_attribute_chrvalue_t; - -typedef struct { - uint8_t flags; //client characteristic flags allowed 1-notification, 2-indication) - uint8_t clientconfig_index; // index to client config. -} sli_bt_gattdb_attribute_config_t; - -typedef struct { - uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop - uint16_t char_uuid; // characteristic UUID handle -} sli_bt_gattdb_attribute_characteristic_t; - -typedef struct { - uint16_t start; //Included Service Attribute Handle - uint16_t end; //End Group Handle -} sli_bt_gattdb_attribute_service_include_t; - -typedef struct { - uint16_t handle; - uint16_t uuid; - uint16_t permissions; //gatt_attribute_permission - uint16_t caps; // Capability bit flags - uint8_t datatype; //Just use uint8_t Do not use enum type, may cause compatibility troubles - uint8_t state; - union { - const sli_bt_gattdb_value_t *constdata; //generic constant data - sli_bt_gattdb_attribute_chrvalue_t *dynamicdata; //Modifiable data - sli_bt_gattdb_attribute_config_t configdata; - sli_bt_gattdb_attribute_characteristic_t characteristic; - sli_bt_gattdb_attribute_service_include_t service_include; - }; -} sli_bt_gattdb_attribute_t; - -struct sli_bt_gattdb_s { - const sli_bt_gattdb_attribute_t *attributes; - uint16_t attribute_table_size; - uint16_t attribute_num; - const uint16_t *uuid16; - uint16_t uuid16_table_size; - uint16_t uuid16_num; - const uint8_t *uuid128; - uint16_t uuid128_table_size; - uint16_t uuid128_num; - uint8_t num_ccfg; - uint16_t caps_mask; - uint16_t enabled_caps; -}; - -typedef struct sli_bt_gattdb_s sli_bt_gattdb_t; - -extern const sli_bt_gattdb_t *static_gattdb; - -/** - * @addtogroup dynamic_gatt_config - * - * Dynamic GATT database configuration. - */ - -/** - * Flag indicating GATT caching should be enabled. When enabled, a Generic - * Attribute Profile Service will be created in database if one doesn't exist. - **/ -#define SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING (0x01) - -/** - * Flag indicating the static database should be included if one exists. - */ -#define SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB (0X02) - -typedef struct { - uint32_t flags; -} sli_bt_gattdb_config_t; - -/** @} (end addtogroup dynamic_gatt_config) */ - -#endif +/***************************************************************************//** + * @brief Bluetooth GATT database structure definition + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_GATT_DEF_H +#define SLI_BT_GATT_DEF_H + +#include +#include + +typedef struct { + uint16_t len; //size of buffer + uint8_t data[]; +} sli_bt_gattdb_value_t; + +typedef struct { + uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop + uint16_t max_len; //Maximum length of data in buffer + uint16_t len; //current size of data in buffer + uint8_t data[]; //size is max_len +} sli_bt_gattdb_attribute_chrvalue_t; + +typedef struct { + uint8_t flags; //client characteristic flags allowed 1-notification, 2-indication) + uint8_t clientconfig_index; // index to client config. +} sli_bt_gattdb_attribute_config_t; + +typedef struct { + uint8_t properties; //Characteristic properties, same as in characteristic descriptor gatt_char_prop + uint16_t char_uuid; // characteristic UUID handle +} sli_bt_gattdb_attribute_characteristic_t; + +typedef struct { + uint16_t start; //Included Service Attribute Handle + uint16_t end; //End Group Handle +} sli_bt_gattdb_attribute_service_include_t; + +typedef struct { + uint16_t handle; + uint16_t uuid; + uint16_t permissions; //gatt_attribute_permission + uint16_t caps; // Capability bit flags + uint8_t datatype; //Just use uint8_t Do not use enum type, may cause compatibility troubles + uint8_t state; + union { + const sli_bt_gattdb_value_t *constdata; //generic constant data + sli_bt_gattdb_attribute_chrvalue_t *dynamicdata; //Modifiable data + sli_bt_gattdb_attribute_config_t configdata; + sli_bt_gattdb_attribute_characteristic_t characteristic; + sli_bt_gattdb_attribute_service_include_t service_include; + }; +} sli_bt_gattdb_attribute_t; + +struct sli_bt_gattdb_s { + const sli_bt_gattdb_attribute_t *attributes; + uint16_t attribute_table_size; + uint16_t attribute_num; + const uint16_t *uuid16; + uint16_t uuid16_table_size; + uint16_t uuid16_num; + const uint8_t *uuid128; + uint16_t uuid128_table_size; + uint16_t uuid128_num; + uint8_t num_ccfg; + uint16_t caps_mask; + uint16_t enabled_caps; +}; + +typedef struct sli_bt_gattdb_s sli_bt_gattdb_t; + +extern const sli_bt_gattdb_t *static_gattdb; + +/** + * @addtogroup dynamic_gatt_config + * + * Dynamic GATT database configuration. + */ + +/** + * Flag indicating GATT caching should be enabled. When enabled, a Generic + * Attribute Profile Service will be created in database if one doesn't exist. + **/ +#define SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING (0x01) + +/** + * Flag indicating the static database should be included if one exists. + */ +#define SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB (0X02) + +typedef struct { + uint32_t flags; +} sli_bt_gattdb_config_t; + +/** @} (end addtogroup dynamic_gatt_config) */ + +#endif diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_l2cap_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_l2cap_config.h index 7ca4b9a..58194ea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_l2cap_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_l2cap_config.h @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file sli_bt_l2cap_config.h - * @brief Configuration types for "l2cap" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_L2CAP_CONFIG_H -#define SLI_BT_L2CAP_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "l2cap" - * - * See "sl_bluetooth_l2cap_config.h" for detailed description of each - * configuration parameter. - */ -typedef struct { - uint8_t max_l2cap_coc_channels; ///< Set to value of SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS -} sli_bt_l2cap_config_t; - -#endif // SLI_BT_L2CAP_CONFIG_H +/***************************************************************************//** + * @file sli_bt_l2cap_config.h + * @brief Configuration types for "l2cap" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_L2CAP_CONFIG_H +#define SLI_BT_L2CAP_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "l2cap" + * + * See "sl_bluetooth_l2cap_config.h" for detailed description of each + * configuration parameter. + */ +typedef struct { + uint8_t max_l2cap_coc_channels; ///< Set to value of SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS +} sli_bt_l2cap_config_t; + +#endif // SLI_BT_L2CAP_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_pawr_advertiser_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_pawr_advertiser_config.h index a76efb0..9fe67bf 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_pawr_advertiser_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_pawr_advertiser_config.h @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file sli_bt_pawr_advertiser_config.h - * @brief Configuration types for "pawr_advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_PAWR_ADVERTISER_CONFIG_H -#define SLI_BT_PAWR_ADVERTISER_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "pawr_advertiser" - * - * See "sl_bt_pawr_advertiser_config.h" for detailed description of each - * configuration parameter. - */ -typedef struct { - uint8_t max_pawr_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PAWR_ADVERTISERS -} sli_bt_pawr_advertiser_config_t; - -#endif // SLI_BT_PAWR_ADVERTISER_CONFIG_H +/***************************************************************************//** + * @file sli_bt_pawr_advertiser_config.h + * @brief Configuration types for "pawr_advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_PAWR_ADVERTISER_CONFIG_H +#define SLI_BT_PAWR_ADVERTISER_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "pawr_advertiser" + * + * See "sl_bt_pawr_advertiser_config.h" for detailed description of each + * configuration parameter. + */ +typedef struct { + uint8_t max_pawr_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PAWR_ADVERTISERS +} sli_bt_pawr_advertiser_config_t; + +#endif // SLI_BT_PAWR_ADVERTISER_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_adv_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_adv_config.h index 019dc50..71a02ec 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_adv_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_adv_config.h @@ -1,38 +1,38 @@ -/***************************************************************************//** - * @file sli_bt_periodic_adv_config.h - * @brief Configuration types for "periodic_adv" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_PERIODIC_ADV_CONFIG_H -#define SLI_BT_PERIODIC_ADV_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "periodic_adv" - * - * Note that this configuration is for the deprecated "periodic_adv" component - * that has been replaced by "periodic_advertiser". This deprecated component - * defines a configuration structure that is binary-compatible with the - * configuration of the new "periodic_advertiser" component. - * - * See "sl_bluetooth_periodic_adv_config.h" for detailed description of each - * configuration parameter. - */ -typedef struct { - uint8_t max_periodic_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS -} sli_bt_periodic_adv_config_t; - -#endif // SLI_BT_PERIODIC_ADV_CONFIG_H +/***************************************************************************//** + * @file sli_bt_periodic_adv_config.h + * @brief Configuration types for "periodic_adv" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_PERIODIC_ADV_CONFIG_H +#define SLI_BT_PERIODIC_ADV_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "periodic_adv" + * + * Note that this configuration is for the deprecated "periodic_adv" component + * that has been replaced by "periodic_advertiser". This deprecated component + * defines a configuration structure that is binary-compatible with the + * configuration of the new "periodic_advertiser" component. + * + * See "sl_bluetooth_periodic_adv_config.h" for detailed description of each + * configuration parameter. + */ +typedef struct { + uint8_t max_periodic_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS +} sli_bt_periodic_adv_config_t; + +#endif // SLI_BT_PERIODIC_ADV_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_advertiser_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_advertiser_config.h index e078c65..c5b8778 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_advertiser_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_periodic_advertiser_config.h @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file sli_bt_periodic_advertiser_config.h - * @brief Configuration types for "periodic_advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_PERIODIC_ADVERTISER_CONFIG_H -#define SLI_BT_PERIODIC_ADVERTISER_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "periodic_advertiser" - * - * See "sl_bt_periodic_advertiser_config.h" for detailed description of each - * configuration parameter. - */ -typedef struct { - uint8_t max_periodic_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS -} sli_bt_periodic_advertiser_config_t; - -#endif // SLI_BT_PERIODIC_ADVERTISER_CONFIG_H +/***************************************************************************//** + * @file sli_bt_periodic_advertiser_config.h + * @brief Configuration types for "periodic_advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_PERIODIC_ADVERTISER_CONFIG_H +#define SLI_BT_PERIODIC_ADVERTISER_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "periodic_advertiser" + * + * See "sl_bt_periodic_advertiser_config.h" for detailed description of each + * configuration parameter. + */ +typedef struct { + uint8_t max_periodic_advertisers; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS +} sli_bt_periodic_advertiser_config_t; + +#endif // SLI_BT_PERIODIC_ADVERTISER_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_sync_config.h b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_sync_config.h index 76bb53a..14c4239 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_sync_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/inc/sli_bt_sync_config.h @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file sli_bt_sync_config.h - * @brief Configuration types for "sync" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SLI_BT_SYNC_CONFIG_H -#define SLI_BT_SYNC_CONFIG_H - -#include "sli_bt_config_defs.h" - -/** - * @brief Configuration structure used by "sync" - * - * See "sl_bt_sync_config.h" for detailed description of each configuration - * parameter. - */ -typedef struct { - uint8_t max_periodic_syncs; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC -} sli_bt_sync_config_t; - -#endif // SLI_BT_SYNC_CONFIG_H +/***************************************************************************//** + * @file sli_bt_sync_config.h + * @brief Configuration types for "sync" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SLI_BT_SYNC_CONFIG_H +#define SLI_BT_SYNC_CONFIG_H + +#include "sli_bt_config_defs.h" + +/** + * @brief Configuration structure used by "sync" + * + * See "sl_bt_sync_config.h" for detailed description of each configuration + * parameter. + */ +typedef struct { + uint8_t max_periodic_syncs; ///< Set to value of SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC +} sli_bt_sync_config_t; + +#endif // SLI_BT_SYNC_CONFIG_H diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_stack_init.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_stack_init.c index b4cf115..b98d946 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_stack_init.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sl_bt_stack_init.c @@ -1,906 +1,906 @@ -/***************************************************************************//** - * @brief Initialization APIs for Bluetooth stack - ******************************************************************************* - * # License - * Copyright 2019 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -// Include the catalog first to make sure everything below can see it -#ifdef SL_COMPONENT_CATALOG_PRESENT -#include "sl_component_catalog.h" -#else // SL_COMPONENT_CATALOG_PRESENT -#error The SL component catalog required by Bluetooth stack is not present in the build -#endif // SL_COMPONENT_CATALOG_PRESENT - -// Define the initilization mode for the configuration definition headers. The -// initialization mode for the Bluetooth stack depends on the on-demand start -// component. When on-demand start is used, features support de-initialization. -// When on-demand start is not used, the de-init functions are omitted to -// eliminate code that's not needed in the build. -#if defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) -#define SLI_BT_INIT_MODE on_demand -#else -#define SLI_BT_INIT_MODE init_always -#endif - -#include "sl_status.h" -#include "sl_bt_api.h" -#include "sl_bt_stack_config.h" -#include "sl_bt_stack_init.h" -#include "sl_bluetooth.h" -#include "sl_bluetooth_config.h" -#include "sl_btctrl_linklayer.h" -#include "sli_bt_gattdb_def.h" -#include "sli_bt_config_defs.h" - -#ifdef SL_CATALOG_GATT_CONFIGURATION_PRESENT -extern const sli_bt_gattdb_t gattdb; -#else -const sli_bt_gattdb_t gattdb = { 0 }; -#endif // SL_CATALOG_GATT_CONFIGURATION_PRESENT - -// Forward declaration of BGAPI classes -SLI_BT_DECLARE_BGAPI_CLASS(bt, system); -SLI_BT_DECLARE_BGAPI_CLASS(bt, nvm); -SLI_BT_DECLARE_BGAPI_CLASS(bt, ota); -SLI_BT_DECLARE_BGAPI_CLASS(bt, gap); -SLI_BT_DECLARE_BGAPI_CLASS(bt, sm); -SLI_BT_DECLARE_BGAPI_CLASS(bt, external_bondingdb); -SLI_BT_DECLARE_BGAPI_CLASS(bt, accept_list); -SLI_BT_DECLARE_BGAPI_CLASS(bt, resolving_list); -SLI_BT_DECLARE_BGAPI_CLASS(bt, advertiser); -SLI_BT_DECLARE_BGAPI_CLASS(bt, legacy_advertiser); -SLI_BT_DECLARE_BGAPI_CLASS(bt, extended_advertiser); -SLI_BT_DECLARE_BGAPI_CLASS(bt, periodic_advertiser); -SLI_BT_DECLARE_BGAPI_CLASS(bt, scanner); -SLI_BT_DECLARE_BGAPI_CLASS(bt, sync); -SLI_BT_DECLARE_BGAPI_CLASS(bt, pawr_advertiser); -SLI_BT_DECLARE_BGAPI_CLASS(bt, sync_scanner); -SLI_BT_DECLARE_BGAPI_CLASS(bt, periodic_sync); -SLI_BT_DECLARE_BGAPI_CLASS(bt, pawr_sync); -SLI_BT_DECLARE_BGAPI_CLASS(bt, past_receiver); -SLI_BT_DECLARE_BGAPI_CLASS(bt, advertiser_past); -SLI_BT_DECLARE_BGAPI_CLASS(bt, sync_past); -SLI_BT_DECLARE_BGAPI_CLASS(bt, cs); -SLI_BT_DECLARE_BGAPI_CLASS(bt, cs_test); -SLI_BT_DECLARE_BGAPI_CLASS(bt, l2cap); -SLI_BT_DECLARE_BGAPI_CLASS(bt, connection); -SLI_BT_DECLARE_BGAPI_CLASS(bt, gatt); -SLI_BT_DECLARE_BGAPI_CLASS(bt, gattdb); -SLI_BT_DECLARE_BGAPI_CLASS(bt, gatt_server); -SLI_BT_DECLARE_BGAPI_CLASS(bt, cte_receiver); -SLI_BT_DECLARE_BGAPI_CLASS(bt, cte_transmitter); -SLI_BT_DECLARE_BGAPI_CLASS(bt, test); -SLI_BT_DECLARE_BGAPI_CLASS(bt, coex); -SLI_BT_DECLARE_BGAPI_CLASS(bt, resource); -SLI_BT_DECLARE_BGAPI_CLASS(bt, connection_analyzer); - -// Forward declaration of the internal Bluetooth stack init function -sl_status_t sli_bt_init_stack(const sl_bt_configuration_t *config, - const struct sli_bt_feature_use *features, - const struct sli_bgapi_class * const *bgapi_classes); - -// Some features do not correspond directly to a particular component but are -// needed depending on a specific combination of components. Decide the derived -// feature selections here to simplify the feature inclusion rules below. - -// Advertiser backwards compatibility is needed if the application uses the -// "advertiser" component but not any of the components that supersede its -// functionality. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) -#define SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY -#endif - -// Extended advertising feature is included if it's explicitly used or needed -// for backwards compatibility, but only when there's no device incompatibility. -#if (defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) \ - || defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY)) \ - && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_ADVERTISING_INCOMPATIBLE_PRESENT) -#define SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE -#endif - -// Deprecated "periodic_adv" feature is only relevant for applications that need -// advertiser backwards compatibility, as new applications would use -// "periodic_advertiser". Include "periodic_adv" if it's used together with -// advertiser backwards compatibility, but only when there's no device incompatibility. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) \ - && defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY) \ - && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_ADVERTISING_INCOMPATIBLE_PRESENT) -#define SLI_BT_ENABLE_PERIODIC_ADV_FEATURE -#endif - -// Scanner backwards compatibility is needed if the application uses the -// "scanner" component but not any of the components that supersede its -// functionality. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_SCANNER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) -#define SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY -#endif - -// The scanner event handler is included if the legacy or extended scanner -// component is used. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_SCANNER_PRESENT) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) -#define SLI_BT_ENABLE_SCANNER_BASE -#endif - -// Extended scanner feature is included if it's explicitly used or needed -// for backwards compatibility, but only when there's no device incompatibility. -#if (defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) \ - || defined(SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY)) \ - && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_SCANNING_INCOMPATIBLE_PRESENT) -#define SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE -#endif - -// Periodic synchronization backwards compatibility is needed if the application -// uses the "sync" component but not any of the components that supersede its -// functionality. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_SYNC_PRESENT) \ - && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) -#define SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY -#endif - -// If the build configuration needs a specific feature, we pick it for inclusion -// in the feature and BGAPI lists, as applicable. - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYSTEM_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, system); -#define SLI_BT_FEATURE_SYSTEM SLI_BT_USE_FEATURE(bt, system), -#define SLI_BT_BGAPI_SYSTEM SLI_BT_USE_BGAPI_CLASS(bt, system), -#else -#define SLI_BT_FEATURE_SYSTEM -#define SLI_BT_BGAPI_SYSTEM -#endif - -#if defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, on_demand_start); -#define SLI_BT_FEATURE_ON_DEMAND_START SLI_BT_USE_FEATURE(bt, on_demand_start), -#else -#define SLI_BT_FEATURE_ON_DEMAND_START -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_NVM_PRESENT) -#define SLI_BT_BGAPI_NVM SLI_BT_USE_BGAPI_CLASS(bt, nvm), -#else -#define SLI_BT_BGAPI_NVM -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_OTA_CONFIG_PRESENT) -#define SLI_BT_BGAPI_OTA_CONFIG SLI_BT_USE_BGAPI_CLASS(bt, ota), -#else -#define SLI_BT_BGAPI_OTA_CONFIG -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GAP_PRESENT) -#define SLI_BT_BGAPI_GAP SLI_BT_USE_BGAPI_CLASS(bt, gap), -#else -#define SLI_BT_BGAPI_GAP -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SM_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, sm); -#define SLI_BT_FEATURE_SM SLI_BT_USE_FEATURE(bt, sm), -#define SLI_BT_BGAPI_SM SLI_BT_USE_BGAPI_CLASS(bt, sm), -#else -#define SLI_BT_FEATURE_SM -#define SLI_BT_BGAPI_SM -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_BUILTIN_BONDING_DATABASE_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, builtin_bonding_database); -#define SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE SLI_BT_USE_FEATURE(bt, builtin_bonding_database), -#else -#define SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTERNAL_BONDING_DATABASE_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, external_bonding_database); -#define SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE SLI_BT_USE_FEATURE(bt, external_bonding_database), -#define SLI_BT_BGAPI_EXTERNAL_BONDINGDB SLI_BT_USE_BGAPI_CLASS(bt, external_bondingdb), -#else -#define SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE -#define SLI_BT_BGAPI_EXTERNAL_BONDINGDB -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, accept_list); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, accept_list); -#define SLI_BT_FEATURE_ACCEPT_LIST SLI_BT_USE_FEATURE_WITH_CONFIG(bt, accept_list, SLI_BT_FEATURE_CONFIG_NAME(bt, accept_list)), -#define SLI_BT_BGAPI_ACCEPT_LIST SLI_BT_USE_BGAPI_CLASS(bt, accept_list), -#else -#define SLI_BT_FEATURE_ACCEPT_LIST -#define SLI_BT_BGAPI_ACCEPT_LIST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, resolving_list); -#define SLI_BT_FEATURE_RESOLVING_LIST SLI_BT_USE_FEATURE(bt, resolving_list), -#define SLI_BT_BGAPI_RESOLVING_LIST SLI_BT_USE_BGAPI_CLASS(bt, resolving_list), -#else -#define SLI_BT_FEATURE_RESOLVING_LIST -#define SLI_BT_BGAPI_RESOLVING_LIST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, advertiser); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, advertiser); -#define SLI_BT_FEATURE_ADVERTISER SLI_BT_USE_FEATURE_WITH_CONFIG(bt, advertiser, SLI_BT_FEATURE_CONFIG_NAME(bt, advertiser)), -#define SLI_BT_BGAPI_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, advertiser), -#else -#define SLI_BT_FEATURE_ADVERTISER -#define SLI_BT_BGAPI_ADVERTISER -#endif - -#if defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY) -SLI_BT_DECLARE_FEATURE(bt, advertiser_compatibility); -#define SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY SLI_BT_USE_FEATURE(bt, advertiser_compatibility), -#else -#define SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT) -#define SLI_BT_BGAPI_LEGACY_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, legacy_advertiser), -#else -#define SLI_BT_BGAPI_LEGACY_ADVERTISER -#endif - -#if defined(SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE) -SLI_BT_DECLARE_FEATURE(bt, extended_advertiser); -#define SLI_BT_FEATURE_EXTENDED_ADVERTISER SLI_BT_USE_FEATURE(bt, extended_advertiser), -#else -#define SLI_BT_FEATURE_EXTENDED_ADVERTISER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) -#define SLI_BT_BGAPI_EXTENDED_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, extended_advertiser), -#else -#define SLI_BT_BGAPI_EXTENDED_ADVERTISER -#endif - -#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) -SLI_BT_DECLARE_FEATURE(bt, periodic_adv); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, periodic_adv); -#define SLI_BT_FEATURE_PERIODIC_ADV SLI_BT_USE_FEATURE_WITH_CONFIG(bt, periodic_adv, SLI_BT_FEATURE_CONFIG_NAME(bt, periodic_adv)), -#else -#define SLI_BT_FEATURE_PERIODIC_ADV -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, periodic_advertiser); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, periodic_advertiser); -#define SLI_BT_FEATURE_PERIODIC_ADVERTISER SLI_BT_USE_FEATURE_WITH_CONFIG(bt, periodic_advertiser, SLI_BT_FEATURE_CONFIG_NAME(bt, periodic_advertiser)), -#define SLI_BT_BGAPI_PERIODIC_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, periodic_advertiser), -#else -#define SLI_BT_FEATURE_PERIODIC_ADVERTISER -#define SLI_BT_BGAPI_PERIODIC_ADVERTISER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) -#define SLI_BT_BGAPI_PAWR_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, pawr_advertiser), -#else -#define SLI_BT_BGAPI_PAWR_ADVERTISER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, scanner); -#define SLI_BT_FEATURE_SCANNER SLI_BT_USE_FEATURE(bt, scanner), -#define SLI_BT_BGAPI_SCANNER SLI_BT_USE_BGAPI_CLASS(bt, scanner), -#else -#define SLI_BT_FEATURE_SCANNER -#define SLI_BT_BGAPI_SCANNER -#endif - -#if defined(SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY) -SLI_BT_DECLARE_FEATURE(bt, scanner_compatibility); -#define SLI_BT_FEATURE_SCANNER_COMPATIBILITY SLI_BT_USE_FEATURE(bt, scanner_compatibility), -#else -#define SLI_BT_FEATURE_SCANNER_COMPATIBILITY -#endif - -#if defined(SLI_BT_ENABLE_SCANNER_BASE) -SLI_BT_DECLARE_FEATURE(bt, scanner_base); -#define SLI_BT_FEATURE_SCANNER_BASE SLI_BT_USE_FEATURE(bt, scanner_base), -#else -#define SLI_BT_FEATURE_SCANNER_BASE -#endif - -#if defined(SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE) -SLI_BT_DECLARE_FEATURE(bt, extended_scanner); -#define SLI_BT_FEATURE_EXTENDED_SCANNER SLI_BT_USE_FEATURE(bt, extended_scanner), -#else -#define SLI_BT_FEATURE_EXTENDED_SCANNER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, sync); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, sync); -#define SLI_BT_FEATURE_SYNC SLI_BT_USE_FEATURE_WITH_CONFIG(bt, sync, SLI_BT_FEATURE_CONFIG_NAME(bt, sync)), -#define SLI_BT_BGAPI_SYNC SLI_BT_USE_BGAPI_CLASS(bt, sync), -#else -#define SLI_BT_FEATURE_SYNC -#define SLI_BT_BGAPI_SYNC -#endif - -// Sync scanner feature is needed when specifically included or when sync -// backwards compatibility needs to be enabled -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) \ - || defined(SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY) -SLI_BT_DECLARE_FEATURE(bt, sync_scanner); -#define SLI_BT_FEATURE_SYNC_SCANNER SLI_BT_USE_FEATURE(bt, sync_scanner), -#else -#define SLI_BT_FEATURE_SYNC_SCANNER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) -#define SLI_BT_BGAPI_SYNC_SCANNER SLI_BT_USE_BGAPI_CLASS(bt, sync_scanner), -#else -#define SLI_BT_BGAPI_SYNC_SCANNER -#endif - -#if defined(SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY) -SLI_BT_DECLARE_FEATURE(bt, sync_compatibility); -#define SLI_BT_FEATURE_SYNC_COMPATIBILITY SLI_BT_USE_FEATURE(bt, sync_compatibility), -#else -#define SLI_BT_FEATURE_SYNC_COMPATIBILITY -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_SYNC_PRESENT) -#define SLI_BT_BGAPI_PERIODIC_SYNC SLI_BT_USE_BGAPI_CLASS(bt, periodic_sync), -#else -#define SLI_BT_BGAPI_PERIODIC_SYNC -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) -#define SLI_BT_BGAPI_PAWR_SYNC SLI_BT_USE_BGAPI_CLASS(bt, pawr_sync), -#else -#define SLI_BT_BGAPI_PAWR_SYNC -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAST_RECEIVER_PRESENT) -#define SLI_BT_BGAPI_PAST_RECEIVER SLI_BT_USE_BGAPI_CLASS(bt, past_receiver), -#else -#define SLI_BT_BGAPI_PAST_RECEIVER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PAST_PRESENT) -#define SLI_BT_BGAPI_ADVERTISER_PAST SLI_BT_USE_BGAPI_CLASS(bt, advertiser_past), -#else -#define SLI_BT_BGAPI_ADVERTISER_PAST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PAST_PRESENT) -#define SLI_BT_BGAPI_SYNC_PAST SLI_BT_USE_BGAPI_CLASS(bt, sync_past), -#else -#define SLI_BT_BGAPI_SYNC_PAST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, cs); -#define SLI_BT_FEATURE_CS SLI_BT_USE_FEATURE(bt, cs), -#define SLI_BT_BGAPI_CS SLI_BT_USE_BGAPI_CLASS(bt, cs), -#else -#define SLI_BT_FEATURE_CS -#define SLI_BT_BGAPI_CS -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_TEST_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, cs_test); -#define SLI_BT_FEATURE_CS_TEST SLI_BT_USE_FEATURE(bt, cs_test), -#define SLI_BT_BGAPI_CS_TEST SLI_BT_USE_BGAPI_CLASS(bt, cs_test), -#else -#define SLI_BT_FEATURE_CS_TEST -#define SLI_BT_BGAPI_CS_TEST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, l2cap); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, l2cap); -#define SLI_BT_FEATURE_L2CAP SLI_BT_USE_FEATURE_WITH_CONFIG(bt, l2cap, SLI_BT_FEATURE_CONFIG_NAME(bt, l2cap)), -#define SLI_BT_BGAPI_L2CAP SLI_BT_USE_BGAPI_CLASS(bt, l2cap), -#else -#define SLI_BT_FEATURE_L2CAP -#define SLI_BT_BGAPI_L2CAP -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, connection); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, connection); -#define SLI_BT_FEATURE_CONNECTION SLI_BT_USE_FEATURE_WITH_CONFIG(bt, connection, SLI_BT_FEATURE_CONFIG_NAME(bt, connection)), -#define SLI_BT_BGAPI_CONNECTION SLI_BT_USE_BGAPI_CLASS(bt, connection), -#else -#define SLI_BT_FEATURE_CONNECTION -#define SLI_BT_BGAPI_CONNECTION -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_STATISTICS_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, connection_statistics); -#define SLI_BT_FEATURE_CONNECTION_STATISTICS SLI_BT_USE_FEATURE(bt, connection_statistics), -#else -#define SLI_BT_FEATURE_CONNECTION_STATISTICS -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) \ - && defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) -#error bluetooth_feature_power_control and bluetooth_feature_user_power_control cannot coexist. -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, power_control); -#define SLI_BT_FEATURE_POWER_CONTROL SLI_BT_USE_FEATURE(bt, power_control), -#else -#define SLI_BT_FEATURE_POWER_CONTROL -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, user_power_control); -#define SLI_BT_FEATURE_USER_POWER_CONTROL SLI_BT_USE_FEATURE(bt, user_power_control), -#else -#define SLI_BT_FEATURE_USER_POWER_CONTROL -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GATT_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, gatt); -#define SLI_BT_FEATURE_GATT SLI_BT_USE_FEATURE(bt, gatt), -#define SLI_BT_BGAPI_GATT SLI_BT_USE_BGAPI_CLASS(bt, gatt), -#else -#define SLI_BT_FEATURE_GATT -#define SLI_BT_BGAPI_GATT -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, dynamic_gattdb); -SLI_BT_DECLARE_FEATURE_CONFIG(bt, dynamic_gattdb); -#define SLI_BT_FEATURE_DYNAMIC_GATTDB SLI_BT_USE_FEATURE_WITH_CONFIG(bt, dynamic_gattdb, SLI_BT_FEATURE_CONFIG_NAME(bt, dynamic_gattdb)), -#define SLI_BT_BGAPI_DYNAMIC_GATTDB SLI_BT_USE_BGAPI_CLASS(bt, gattdb), -#else -#define SLI_BT_FEATURE_DYNAMIC_GATTDB -#define SLI_BT_BGAPI_DYNAMIC_GATTDB -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GATT_SERVER_PRESENT) -#define SLI_BT_BGAPI_GATT_SERVER SLI_BT_USE_BGAPI_CLASS(bt, gatt_server), -#else -#define SLI_BT_BGAPI_GATT_SERVER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_RECEIVER_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, cte_receiver); -#define SLI_BT_FEATURE_CTE_RECEIVER SLI_BT_USE_FEATURE(bt, cte_receiver), -#define SLI_BT_BGAPI_CTE_RECEIVER SLI_BT_USE_BGAPI_CLASS(bt, cte_receiver), -#else -#define SLI_BT_FEATURE_CTE_RECEIVER -#define SLI_BT_BGAPI_CTE_RECEIVER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_TRANSMITTER_PRESENT) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_TRANSMITTER_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, cte_transmitter); -#define SLI_BT_FEATURE_CTE_TRANSMITTER SLI_BT_USE_FEATURE(bt, cte_transmitter), -#define SLI_BT_BGAPI_CTE_TRANSMITTER SLI_BT_USE_BGAPI_CLASS(bt, cte_transmitter), -#else -#define SLI_BT_FEATURE_CTE_TRANSMITTER -#define SLI_BT_BGAPI_CTE_TRANSMITTER -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_TEST_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, test); -#define SLI_BT_FEATURE_TEST SLI_BT_USE_FEATURE(bt, test), -#define SLI_BT_BGAPI_TEST SLI_BT_USE_BGAPI_CLASS(bt, test), -#else -#define SLI_BT_FEATURE_TEST -#define SLI_BT_BGAPI_TEST -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_WHITELISTING_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, whitelisting); -#define SLI_BT_FEATURE_WHITELISTING SLI_BT_USE_FEATURE(bt, whitelisting), -#else -#define SLI_BT_FEATURE_WHITELISTING -#endif - -#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) -#define SLI_BT_BGAPI_COEX SLI_BT_USE_BGAPI_CLASS(bt, coex), -#else -#define SLI_BT_BGAPI_COEX -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOURCE_REPORT_PRESENT) -#define SLI_BT_BGAPI_RESOURCE SLI_BT_USE_BGAPI_CLASS(bt, resource), -#else -#define SLI_BT_BGAPI_RESOURCE -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USE_ACCURATE_API_ADDRESS_TYPES_PRESENT) -SLI_BT_DECLARE_FEATURE(bt, accurate_api_address_types); -#define SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES SLI_BT_USE_FEATURE(bt, accurate_api_address_types), -#else -#define SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) -#define SLI_BT_BGAPI_CONNECTION_ANALYZER SLI_BT_USE_BGAPI_CLASS(bt, connection_analyzer), -#else -#define SLI_BT_BGAPI_CONNECTION_ANALYZER -#endif - -/** @brief Structure that specifies the Bluetooth configuration */ -static const sl_bt_configuration_t bt_config = SL_BT_CONFIG_DEFAULT; - -/** @brief Table of used Bluetooth features */ -static const struct sli_bt_feature_use bt_used_features[] = -{ - // Invoke the feature inclusion macro for each feature. Depending on the build - // configuration, the feature inclusion rules above have defined the macro to - // either empty or the relevant feature use declaration. - SLI_BT_FEATURE_ON_DEMAND_START - SLI_BT_FEATURE_SYSTEM - SLI_BT_FEATURE_SM - SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE - SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE - SLI_BT_FEATURE_ACCEPT_LIST - SLI_BT_FEATURE_RESOLVING_LIST - SLI_BT_FEATURE_SCANNER - SLI_BT_FEATURE_SCANNER_COMPATIBILITY - SLI_BT_FEATURE_SCANNER_BASE - SLI_BT_FEATURE_EXTENDED_SCANNER - SLI_BT_FEATURE_SYNC - SLI_BT_FEATURE_SYNC_SCANNER - SLI_BT_FEATURE_SYNC_COMPATIBILITY - SLI_BT_FEATURE_ADVERTISER - SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY - SLI_BT_FEATURE_EXTENDED_ADVERTISER - SLI_BT_FEATURE_PERIODIC_ADV - SLI_BT_FEATURE_PERIODIC_ADVERTISER - SLI_BT_FEATURE_CS - SLI_BT_FEATURE_CS_TEST - SLI_BT_FEATURE_L2CAP - SLI_BT_FEATURE_CONNECTION - SLI_BT_FEATURE_CONNECTION_STATISTICS - SLI_BT_FEATURE_DYNAMIC_GATTDB - SLI_BT_FEATURE_CTE_RECEIVER - SLI_BT_FEATURE_CTE_TRANSMITTER - SLI_BT_FEATURE_TEST - SLI_BT_FEATURE_POWER_CONTROL - SLI_BT_FEATURE_USER_POWER_CONTROL - SLI_BT_FEATURE_GATT - SLI_BT_FEATURE_WHITELISTING - SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES - { NULL, NULL } -}; - -/** @brief Table of used BGAPI classes */ -static const struct sli_bgapi_class * const bt_bgapi_classes[] = -{ - // Invoke the BGAPI class inclusion macro for each feature that provides a - // BGAPI class. Depending on the build configuration, the feature inclusion - // rules above have defined the macro to either empty or the relevant BGAPI - // class declaration. - SLI_BT_BGAPI_SYSTEM - SLI_BT_BGAPI_NVM - SLI_BT_BGAPI_OTA_CONFIG - SLI_BT_BGAPI_GAP - SLI_BT_BGAPI_SM - SLI_BT_BGAPI_EXTERNAL_BONDINGDB - SLI_BT_BGAPI_ACCEPT_LIST - SLI_BT_BGAPI_RESOLVING_LIST - SLI_BT_BGAPI_ADVERTISER - SLI_BT_BGAPI_LEGACY_ADVERTISER - SLI_BT_BGAPI_EXTENDED_ADVERTISER - SLI_BT_BGAPI_PERIODIC_ADVERTISER - SLI_BT_BGAPI_PAWR_ADVERTISER - SLI_BT_BGAPI_SCANNER - SLI_BT_BGAPI_SYNC - SLI_BT_BGAPI_SYNC_SCANNER - SLI_BT_BGAPI_PERIODIC_SYNC - SLI_BT_BGAPI_PAWR_SYNC - SLI_BT_BGAPI_PAST_RECEIVER - SLI_BT_BGAPI_ADVERTISER_PAST - SLI_BT_BGAPI_SYNC_PAST - SLI_BT_BGAPI_CS - SLI_BT_BGAPI_CS_TEST - SLI_BT_BGAPI_L2CAP - SLI_BT_BGAPI_CONNECTION - SLI_BT_BGAPI_GATT - SLI_BT_BGAPI_DYNAMIC_GATTDB - SLI_BT_BGAPI_GATT_SERVER - SLI_BT_BGAPI_CTE_RECEIVER - SLI_BT_BGAPI_CTE_TRANSMITTER - SLI_BT_BGAPI_TEST - SLI_BT_BGAPI_COEX - SLI_BT_BGAPI_RESOURCE - SLI_BT_BGAPI_CONNECTION_ANALYZER - NULL -}; - -// Forward declaration of Bluetooth controller init functions -extern void ll_addrEnable(); -extern sl_status_t sl_bt_ll_deinit(); -#include "sl_bt_ll_config.h" -extern sl_status_t ll_connPowerControlEnable(const sl_bt_ll_power_control_config_t *); -extern void sl_bt_init_app_controlled_tx_power(); -extern sl_status_t sl_btctrl_init_sniff(uint8_t); -extern void sl_btctrl_deinit_sniff(void); -#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) -#include "coexistence-ble.h" -#endif - -/** - * @brief Initialize controller features according to the feature selection. - * - * This function is called by the Bluetooth host stack when Bluetooth is started. - */ -sl_status_t sli_bt_init_controller_features() -{ - sl_status_t status = SL_STATUS_OK; - -#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) - sl_bt_init_coex_hal(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT) - sl_btctrl_init_multiprotocol(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RADIO_WATCHDOG_PRESENT) - sl_btctrl_enable_radio_watchdog(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) - sl_btctrl_init_adv(); -#endif - -#if defined(SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE) - sl_btctrl_init_adv_ext(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) - sl_btctrl_init_scan(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EVEN_SCHEDULING_PRESENT) - sl_btctrl_enable_even_connsch(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PAWR_SCHEDULING_PRESENT) - sl_btctrl_enable_pawr_connsch(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) - sl_btctrl_init_conn(); -#if !defined(SL_CATALOG_BLUETOOTH_CONNECTION_PHY_UPDATE_INCOMPATIBLE_PRESENT) - sl_btctrl_init_phy(); -#endif -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_STATISTICS_PRESENT) - sl_btctrl_init_conn_statistics(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) -#include "sl_bt_power_control_config.h" - const sl_bt_ll_power_control_config_t power_control_config = { - .activate_power_control = SL_BT_ACTIVATE_POWER_CONTROL, - .golden_rssi_min_1m = SL_BT_GOLDEN_RSSI_MIN_1M, - .golden_rssi_max_1m = SL_BT_GOLDEN_RSSI_MAX_1M, - .golden_rssi_min_2m = SL_BT_GOLDEN_RSSI_MIN_2M, - .golden_rssi_max_2m = SL_BT_GOLDEN_RSSI_MAX_2M, - .golden_rssi_min_coded_s8 = SL_BT_GOLDEN_RSSI_MIN_CODED_S8, - .golden_rssi_max_coded_s8 = SL_BT_GOLDEN_RSSI_MAX_CODED_S8, - .golden_rssi_min_coded_s2 = SL_BT_GOLDEN_RSSI_MIN_CODED_S2, - .golden_rssi_max_coded_s2 = SL_BT_GOLDEN_RSSI_MAX_CODED_S2 - }; - - status = ll_connPowerControlEnable(&power_control_config); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) - sl_bt_init_app_controlled_tx_power(); -#endif - -#if defined(SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE) - sl_btctrl_init_scan_ext(); -#endif - -#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) - // A build with the host stack doesn't have the dedicated config file - // "sl_bluetooth_periodic_adv_config.h". We use the global advertiser count to - // enable all advertisers as periodic advertisers. -#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS -#include "sl_bluetooth_config.h" - sl_btctrl_init_periodic_adv(); - status = sl_btctrl_alloc_periodic_adv(SL_BT_CONFIG_MAX_ADVERTISERS); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) -#include "sl_bt_periodic_advertiser_config.h" - sl_btctrl_init_periodic_adv(); - sl_btctrl_alloc_periodic_adv(SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) -#include "sl_bt_pawr_advertiser_config.h" - struct sl_btctrl_pawr_advertiser_config pawr_config = { - .max_pawr_sets = SL_BT_CONFIG_MAX_PAWR_ADVERTISERS, - .max_advertised_data_length_hint = SL_BT_CONFIG_MAX_PAWR_ADVERTISED_DATA_LENGTH_HINT, - .subevent_data_request_count = SL_BT_CONFIG_PAWR_PACKET_REQUEST_COUNT, - .subevent_data_request_advance = SL_BT_CONFIG_PAWR_PACKET_REQUEST_ADVANCE, - }; - status = sl_btctrl_pawr_advertiser_configure(&pawr_config); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) -#include "sl_bluetooth_periodic_sync_config.h" - sl_btctrl_init_periodic_scan(); - status = sl_btctrl_alloc_periodic_scan(SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) -#include "sl_bt_pawr_sync_config.h" - struct sl_btctrl_pawr_synchronizer_config pawr_sync_config = { - .max_pawr_sets = SL_BT_CONFIG_MAX_PAWR_SYNCHRONIZERS, - }; - status = sl_btctrl_pawr_synchronizer_configure(&pawr_sync_config); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) -#include "sl_bt_resolving_list_config.h" - sl_btctrl_init_privacy(); - status = sl_btctrl_allocate_resolving_list_memory(SL_BT_CONFIG_RESOLVING_LIST_SIZE); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AFH_PRESENT) - status = sl_btctrl_init_afh(1); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_HIGH_POWER_PRESENT) - sl_btctrl_init_highpower(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PHY_SUPPORT_CONFIG_PRESENT) -#include "sl_btctrl_phy_support_config.h" -#if SL_BT_CONTROLLER_2M_PHY_SUPPORT == 0 - sl_btctrl_disable_2m_phy(); -#endif -#if SL_BT_CONTROLLER_CODED_PHY_SUPPORT == 0 - sl_btctrl_disable_coded_phy(); -#endif -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_WHITELISTING_PRESENT) - ll_addrEnable(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_RECEIVER_PRESENT) - status = sl_btctrl_init_cte_receiver(); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_TRANSMITTER_PRESENT) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_TRANSMITTER_PRESENT) - status = sl_btctrl_init_cte_transmitter(); - if (status != SL_STATUS_OK) { - return status; - } -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PAST_PRESENT) - sl_btctrl_init_past_local_sync_transfer(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PAST_PRESENT) - sl_btctrl_init_past_remote_sync_transfer(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAST_RECEIVER_PRESENT) - sl_btctrl_init_past_receiver(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_PRESENT) -#include "sl_bluetooth_cs_config.h" - struct sl_btctrl_cs_config cs_config = { 0 }; - cs_config.configs_per_connection = SL_BT_CONFIG_MAX_CS_CONFIGS_PER_CONNECTION; - cs_config.procedures = SL_BT_CONFIG_MAX_CS_PROCEDURES; - sl_btctrl_init_cs(&cs_config); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) -#include "sl_bluetooth_connection_analyzer_config.h" - status = sl_btctrl_init_sniff(SL_BT_CONFIG_MAX_CONNECTION_ANALYZERS); - if (status != SL_STATUS_OK) { - return status; - } -#endif - - return status; -} - -/** - * @brief De-initialize controller features according to the feature selection. - * - * This function is called by the Bluetooth host stack when Bluetooth is stopped. - */ -void sli_bt_deinit_controller_features() -{ -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) - sl_btctrl_deinit_sniff(); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) - sl_btctrl_allocate_resolving_list_memory(0); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) - sl_btctrl_alloc_periodic_scan(0); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) - struct sl_btctrl_pawr_advertiser_config pawr_config = { - .max_pawr_sets = 0, - .max_advertised_data_length_hint = 0, - .subevent_data_request_count = 0, - .subevent_data_request_advance = 0, - }; - (void) sl_btctrl_pawr_advertiser_configure(&pawr_config); -#endif - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) - struct sl_btctrl_pawr_synchronizer_config pawr_sync_config = { - .max_pawr_sets = 0, - }; - (void) sl_btctrl_pawr_synchronizer_configure(&pawr_sync_config); -#endif - -#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) \ - || defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) - (void) sl_btctrl_alloc_periodic_adv(0); -#endif - - (void) sl_bt_ll_deinit(); -} - -// Initialize the Bluetooth stack. -sl_status_t sl_bt_stack_init() -{ - // Initialize the Bluetooth stack with the given configuration, features, and BGAPI classes - return sli_bt_init_stack(&bt_config, bt_used_features, bt_bgapi_classes); +/***************************************************************************//** + * @brief Initialization APIs for Bluetooth stack + ******************************************************************************* + * # License + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +// Include the catalog first to make sure everything below can see it +#ifdef SL_COMPONENT_CATALOG_PRESENT +#include "sl_component_catalog.h" +#else // SL_COMPONENT_CATALOG_PRESENT +#error The SL component catalog required by Bluetooth stack is not present in the build +#endif // SL_COMPONENT_CATALOG_PRESENT + +// Define the initilization mode for the configuration definition headers. The +// initialization mode for the Bluetooth stack depends on the on-demand start +// component. When on-demand start is used, features support de-initialization. +// When on-demand start is not used, the de-init functions are omitted to +// eliminate code that's not needed in the build. +#if defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) +#define SLI_BT_INIT_MODE on_demand +#else +#define SLI_BT_INIT_MODE init_always +#endif + +#include "sl_status.h" +#include "sl_bt_api.h" +#include "sl_bt_stack_config.h" +#include "sl_bt_stack_init.h" +#include "sl_bluetooth.h" +#include "sl_bluetooth_config.h" +#include "sl_btctrl_linklayer.h" +#include "sli_bt_gattdb_def.h" +#include "sli_bt_config_defs.h" + +#ifdef SL_CATALOG_GATT_CONFIGURATION_PRESENT +extern const sli_bt_gattdb_t gattdb; +#else +const sli_bt_gattdb_t gattdb = { 0 }; +#endif // SL_CATALOG_GATT_CONFIGURATION_PRESENT + +// Forward declaration of BGAPI classes +SLI_BT_DECLARE_BGAPI_CLASS(bt, system); +SLI_BT_DECLARE_BGAPI_CLASS(bt, nvm); +SLI_BT_DECLARE_BGAPI_CLASS(bt, ota); +SLI_BT_DECLARE_BGAPI_CLASS(bt, gap); +SLI_BT_DECLARE_BGAPI_CLASS(bt, sm); +SLI_BT_DECLARE_BGAPI_CLASS(bt, external_bondingdb); +SLI_BT_DECLARE_BGAPI_CLASS(bt, accept_list); +SLI_BT_DECLARE_BGAPI_CLASS(bt, resolving_list); +SLI_BT_DECLARE_BGAPI_CLASS(bt, advertiser); +SLI_BT_DECLARE_BGAPI_CLASS(bt, legacy_advertiser); +SLI_BT_DECLARE_BGAPI_CLASS(bt, extended_advertiser); +SLI_BT_DECLARE_BGAPI_CLASS(bt, periodic_advertiser); +SLI_BT_DECLARE_BGAPI_CLASS(bt, scanner); +SLI_BT_DECLARE_BGAPI_CLASS(bt, sync); +SLI_BT_DECLARE_BGAPI_CLASS(bt, pawr_advertiser); +SLI_BT_DECLARE_BGAPI_CLASS(bt, sync_scanner); +SLI_BT_DECLARE_BGAPI_CLASS(bt, periodic_sync); +SLI_BT_DECLARE_BGAPI_CLASS(bt, pawr_sync); +SLI_BT_DECLARE_BGAPI_CLASS(bt, past_receiver); +SLI_BT_DECLARE_BGAPI_CLASS(bt, advertiser_past); +SLI_BT_DECLARE_BGAPI_CLASS(bt, sync_past); +SLI_BT_DECLARE_BGAPI_CLASS(bt, cs); +SLI_BT_DECLARE_BGAPI_CLASS(bt, cs_test); +SLI_BT_DECLARE_BGAPI_CLASS(bt, l2cap); +SLI_BT_DECLARE_BGAPI_CLASS(bt, connection); +SLI_BT_DECLARE_BGAPI_CLASS(bt, gatt); +SLI_BT_DECLARE_BGAPI_CLASS(bt, gattdb); +SLI_BT_DECLARE_BGAPI_CLASS(bt, gatt_server); +SLI_BT_DECLARE_BGAPI_CLASS(bt, cte_receiver); +SLI_BT_DECLARE_BGAPI_CLASS(bt, cte_transmitter); +SLI_BT_DECLARE_BGAPI_CLASS(bt, test); +SLI_BT_DECLARE_BGAPI_CLASS(bt, coex); +SLI_BT_DECLARE_BGAPI_CLASS(bt, resource); +SLI_BT_DECLARE_BGAPI_CLASS(bt, connection_analyzer); + +// Forward declaration of the internal Bluetooth stack init function +sl_status_t sli_bt_init_stack(const sl_bt_configuration_t *config, + const struct sli_bt_feature_use *features, + const struct sli_bgapi_class * const *bgapi_classes); + +// Some features do not correspond directly to a particular component but are +// needed depending on a specific combination of components. Decide the derived +// feature selections here to simplify the feature inclusion rules below. + +// Advertiser backwards compatibility is needed if the application uses the +// "advertiser" component but not any of the components that supersede its +// functionality. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) +#define SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY +#endif + +// Extended advertising feature is included if it's explicitly used or needed +// for backwards compatibility, but only when there's no device incompatibility. +#if (defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) \ + || defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY)) \ + && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_ADVERTISING_INCOMPATIBLE_PRESENT) +#define SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE +#endif + +// Deprecated "periodic_adv" feature is only relevant for applications that need +// advertiser backwards compatibility, as new applications would use +// "periodic_advertiser". Include "periodic_adv" if it's used together with +// advertiser backwards compatibility, but only when there's no device incompatibility. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) \ + && defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY) \ + && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_ADVERTISING_INCOMPATIBLE_PRESENT) +#define SLI_BT_ENABLE_PERIODIC_ADV_FEATURE +#endif + +// Scanner backwards compatibility is needed if the application uses the +// "scanner" component but not any of the components that supersede its +// functionality. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_SCANNER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) +#define SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY +#endif + +// The scanner event handler is included if the legacy or extended scanner +// component is used. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_SCANNER_PRESENT) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) +#define SLI_BT_ENABLE_SCANNER_BASE +#endif + +// Extended scanner feature is included if it's explicitly used or needed +// for backwards compatibility, but only when there's no device incompatibility. +#if (defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_SCANNER_PRESENT) \ + || defined(SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY)) \ + && !defined(SL_CATALOG_BLUETOOTH_EXTENDED_SCANNING_INCOMPATIBLE_PRESENT) +#define SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE +#endif + +// Periodic synchronization backwards compatibility is needed if the application +// uses the "sync" component but not any of the components that supersede its +// functionality. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_SYNC_PRESENT) \ + && !defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) +#define SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY +#endif + +// If the build configuration needs a specific feature, we pick it for inclusion +// in the feature and BGAPI lists, as applicable. + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYSTEM_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, system); +#define SLI_BT_FEATURE_SYSTEM SLI_BT_USE_FEATURE(bt, system), +#define SLI_BT_BGAPI_SYSTEM SLI_BT_USE_BGAPI_CLASS(bt, system), +#else +#define SLI_BT_FEATURE_SYSTEM +#define SLI_BT_BGAPI_SYSTEM +#endif + +#if defined(SL_CATALOG_BLUETOOTH_ON_DEMAND_START_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, on_demand_start); +#define SLI_BT_FEATURE_ON_DEMAND_START SLI_BT_USE_FEATURE(bt, on_demand_start), +#else +#define SLI_BT_FEATURE_ON_DEMAND_START +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_NVM_PRESENT) +#define SLI_BT_BGAPI_NVM SLI_BT_USE_BGAPI_CLASS(bt, nvm), +#else +#define SLI_BT_BGAPI_NVM +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_OTA_CONFIG_PRESENT) +#define SLI_BT_BGAPI_OTA_CONFIG SLI_BT_USE_BGAPI_CLASS(bt, ota), +#else +#define SLI_BT_BGAPI_OTA_CONFIG +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GAP_PRESENT) +#define SLI_BT_BGAPI_GAP SLI_BT_USE_BGAPI_CLASS(bt, gap), +#else +#define SLI_BT_BGAPI_GAP +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SM_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, sm); +#define SLI_BT_FEATURE_SM SLI_BT_USE_FEATURE(bt, sm), +#define SLI_BT_BGAPI_SM SLI_BT_USE_BGAPI_CLASS(bt, sm), +#else +#define SLI_BT_FEATURE_SM +#define SLI_BT_BGAPI_SM +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_BUILTIN_BONDING_DATABASE_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, builtin_bonding_database); +#define SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE SLI_BT_USE_FEATURE(bt, builtin_bonding_database), +#else +#define SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTERNAL_BONDING_DATABASE_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, external_bonding_database); +#define SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE SLI_BT_USE_FEATURE(bt, external_bonding_database), +#define SLI_BT_BGAPI_EXTERNAL_BONDINGDB SLI_BT_USE_BGAPI_CLASS(bt, external_bondingdb), +#else +#define SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE +#define SLI_BT_BGAPI_EXTERNAL_BONDINGDB +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, accept_list); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, accept_list); +#define SLI_BT_FEATURE_ACCEPT_LIST SLI_BT_USE_FEATURE_WITH_CONFIG(bt, accept_list, SLI_BT_FEATURE_CONFIG_NAME(bt, accept_list)), +#define SLI_BT_BGAPI_ACCEPT_LIST SLI_BT_USE_BGAPI_CLASS(bt, accept_list), +#else +#define SLI_BT_FEATURE_ACCEPT_LIST +#define SLI_BT_BGAPI_ACCEPT_LIST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, resolving_list); +#define SLI_BT_FEATURE_RESOLVING_LIST SLI_BT_USE_FEATURE(bt, resolving_list), +#define SLI_BT_BGAPI_RESOLVING_LIST SLI_BT_USE_BGAPI_CLASS(bt, resolving_list), +#else +#define SLI_BT_FEATURE_RESOLVING_LIST +#define SLI_BT_BGAPI_RESOLVING_LIST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, advertiser); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, advertiser); +#define SLI_BT_FEATURE_ADVERTISER SLI_BT_USE_FEATURE_WITH_CONFIG(bt, advertiser, SLI_BT_FEATURE_CONFIG_NAME(bt, advertiser)), +#define SLI_BT_BGAPI_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, advertiser), +#else +#define SLI_BT_FEATURE_ADVERTISER +#define SLI_BT_BGAPI_ADVERTISER +#endif + +#if defined(SLI_BT_ENABLE_ADVERTISER_BACKWARDS_COMPATIBILITY) +SLI_BT_DECLARE_FEATURE(bt, advertiser_compatibility); +#define SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY SLI_BT_USE_FEATURE(bt, advertiser_compatibility), +#else +#define SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_LEGACY_ADVERTISER_PRESENT) +#define SLI_BT_BGAPI_LEGACY_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, legacy_advertiser), +#else +#define SLI_BT_BGAPI_LEGACY_ADVERTISER +#endif + +#if defined(SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE) +SLI_BT_DECLARE_FEATURE(bt, extended_advertiser); +#define SLI_BT_FEATURE_EXTENDED_ADVERTISER SLI_BT_USE_FEATURE(bt, extended_advertiser), +#else +#define SLI_BT_FEATURE_EXTENDED_ADVERTISER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EXTENDED_ADVERTISER_PRESENT) +#define SLI_BT_BGAPI_EXTENDED_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, extended_advertiser), +#else +#define SLI_BT_BGAPI_EXTENDED_ADVERTISER +#endif + +#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) +SLI_BT_DECLARE_FEATURE(bt, periodic_adv); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, periodic_adv); +#define SLI_BT_FEATURE_PERIODIC_ADV SLI_BT_USE_FEATURE_WITH_CONFIG(bt, periodic_adv, SLI_BT_FEATURE_CONFIG_NAME(bt, periodic_adv)), +#else +#define SLI_BT_FEATURE_PERIODIC_ADV +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, periodic_advertiser); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, periodic_advertiser); +#define SLI_BT_FEATURE_PERIODIC_ADVERTISER SLI_BT_USE_FEATURE_WITH_CONFIG(bt, periodic_advertiser, SLI_BT_FEATURE_CONFIG_NAME(bt, periodic_advertiser)), +#define SLI_BT_BGAPI_PERIODIC_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, periodic_advertiser), +#else +#define SLI_BT_FEATURE_PERIODIC_ADVERTISER +#define SLI_BT_BGAPI_PERIODIC_ADVERTISER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) +#define SLI_BT_BGAPI_PAWR_ADVERTISER SLI_BT_USE_BGAPI_CLASS(bt, pawr_advertiser), +#else +#define SLI_BT_BGAPI_PAWR_ADVERTISER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, scanner); +#define SLI_BT_FEATURE_SCANNER SLI_BT_USE_FEATURE(bt, scanner), +#define SLI_BT_BGAPI_SCANNER SLI_BT_USE_BGAPI_CLASS(bt, scanner), +#else +#define SLI_BT_FEATURE_SCANNER +#define SLI_BT_BGAPI_SCANNER +#endif + +#if defined(SLI_BT_ENABLE_SCANNER_BACKWARDS_COMPATIBILITY) +SLI_BT_DECLARE_FEATURE(bt, scanner_compatibility); +#define SLI_BT_FEATURE_SCANNER_COMPATIBILITY SLI_BT_USE_FEATURE(bt, scanner_compatibility), +#else +#define SLI_BT_FEATURE_SCANNER_COMPATIBILITY +#endif + +#if defined(SLI_BT_ENABLE_SCANNER_BASE) +SLI_BT_DECLARE_FEATURE(bt, scanner_base); +#define SLI_BT_FEATURE_SCANNER_BASE SLI_BT_USE_FEATURE(bt, scanner_base), +#else +#define SLI_BT_FEATURE_SCANNER_BASE +#endif + +#if defined(SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE) +SLI_BT_DECLARE_FEATURE(bt, extended_scanner); +#define SLI_BT_FEATURE_EXTENDED_SCANNER SLI_BT_USE_FEATURE(bt, extended_scanner), +#else +#define SLI_BT_FEATURE_EXTENDED_SCANNER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, sync); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, sync); +#define SLI_BT_FEATURE_SYNC SLI_BT_USE_FEATURE_WITH_CONFIG(bt, sync, SLI_BT_FEATURE_CONFIG_NAME(bt, sync)), +#define SLI_BT_BGAPI_SYNC SLI_BT_USE_BGAPI_CLASS(bt, sync), +#else +#define SLI_BT_FEATURE_SYNC +#define SLI_BT_BGAPI_SYNC +#endif + +// Sync scanner feature is needed when specifically included or when sync +// backwards compatibility needs to be enabled +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) \ + || defined(SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY) +SLI_BT_DECLARE_FEATURE(bt, sync_scanner); +#define SLI_BT_FEATURE_SYNC_SCANNER SLI_BT_USE_FEATURE(bt, sync_scanner), +#else +#define SLI_BT_FEATURE_SYNC_SCANNER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_SCANNER_PRESENT) +#define SLI_BT_BGAPI_SYNC_SCANNER SLI_BT_USE_BGAPI_CLASS(bt, sync_scanner), +#else +#define SLI_BT_BGAPI_SYNC_SCANNER +#endif + +#if defined(SLI_BT_ENABLE_SYNC_BACKWARDS_COMPATIBILITY) +SLI_BT_DECLARE_FEATURE(bt, sync_compatibility); +#define SLI_BT_FEATURE_SYNC_COMPATIBILITY SLI_BT_USE_FEATURE(bt, sync_compatibility), +#else +#define SLI_BT_FEATURE_SYNC_COMPATIBILITY +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_SYNC_PRESENT) +#define SLI_BT_BGAPI_PERIODIC_SYNC SLI_BT_USE_BGAPI_CLASS(bt, periodic_sync), +#else +#define SLI_BT_BGAPI_PERIODIC_SYNC +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) +#define SLI_BT_BGAPI_PAWR_SYNC SLI_BT_USE_BGAPI_CLASS(bt, pawr_sync), +#else +#define SLI_BT_BGAPI_PAWR_SYNC +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAST_RECEIVER_PRESENT) +#define SLI_BT_BGAPI_PAST_RECEIVER SLI_BT_USE_BGAPI_CLASS(bt, past_receiver), +#else +#define SLI_BT_BGAPI_PAST_RECEIVER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PAST_PRESENT) +#define SLI_BT_BGAPI_ADVERTISER_PAST SLI_BT_USE_BGAPI_CLASS(bt, advertiser_past), +#else +#define SLI_BT_BGAPI_ADVERTISER_PAST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PAST_PRESENT) +#define SLI_BT_BGAPI_SYNC_PAST SLI_BT_USE_BGAPI_CLASS(bt, sync_past), +#else +#define SLI_BT_BGAPI_SYNC_PAST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, cs); +#define SLI_BT_FEATURE_CS SLI_BT_USE_FEATURE(bt, cs), +#define SLI_BT_BGAPI_CS SLI_BT_USE_BGAPI_CLASS(bt, cs), +#else +#define SLI_BT_FEATURE_CS +#define SLI_BT_BGAPI_CS +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_TEST_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, cs_test); +#define SLI_BT_FEATURE_CS_TEST SLI_BT_USE_FEATURE(bt, cs_test), +#define SLI_BT_BGAPI_CS_TEST SLI_BT_USE_BGAPI_CLASS(bt, cs_test), +#else +#define SLI_BT_FEATURE_CS_TEST +#define SLI_BT_BGAPI_CS_TEST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, l2cap); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, l2cap); +#define SLI_BT_FEATURE_L2CAP SLI_BT_USE_FEATURE_WITH_CONFIG(bt, l2cap, SLI_BT_FEATURE_CONFIG_NAME(bt, l2cap)), +#define SLI_BT_BGAPI_L2CAP SLI_BT_USE_BGAPI_CLASS(bt, l2cap), +#else +#define SLI_BT_FEATURE_L2CAP +#define SLI_BT_BGAPI_L2CAP +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, connection); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, connection); +#define SLI_BT_FEATURE_CONNECTION SLI_BT_USE_FEATURE_WITH_CONFIG(bt, connection, SLI_BT_FEATURE_CONFIG_NAME(bt, connection)), +#define SLI_BT_BGAPI_CONNECTION SLI_BT_USE_BGAPI_CLASS(bt, connection), +#else +#define SLI_BT_FEATURE_CONNECTION +#define SLI_BT_BGAPI_CONNECTION +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_STATISTICS_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, connection_statistics); +#define SLI_BT_FEATURE_CONNECTION_STATISTICS SLI_BT_USE_FEATURE(bt, connection_statistics), +#else +#define SLI_BT_FEATURE_CONNECTION_STATISTICS +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) \ + && defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) +#error bluetooth_feature_power_control and bluetooth_feature_user_power_control cannot coexist. +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, power_control); +#define SLI_BT_FEATURE_POWER_CONTROL SLI_BT_USE_FEATURE(bt, power_control), +#else +#define SLI_BT_FEATURE_POWER_CONTROL +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, user_power_control); +#define SLI_BT_FEATURE_USER_POWER_CONTROL SLI_BT_USE_FEATURE(bt, user_power_control), +#else +#define SLI_BT_FEATURE_USER_POWER_CONTROL +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GATT_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, gatt); +#define SLI_BT_FEATURE_GATT SLI_BT_USE_FEATURE(bt, gatt), +#define SLI_BT_BGAPI_GATT SLI_BT_USE_BGAPI_CLASS(bt, gatt), +#else +#define SLI_BT_FEATURE_GATT +#define SLI_BT_BGAPI_GATT +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, dynamic_gattdb); +SLI_BT_DECLARE_FEATURE_CONFIG(bt, dynamic_gattdb); +#define SLI_BT_FEATURE_DYNAMIC_GATTDB SLI_BT_USE_FEATURE_WITH_CONFIG(bt, dynamic_gattdb, SLI_BT_FEATURE_CONFIG_NAME(bt, dynamic_gattdb)), +#define SLI_BT_BGAPI_DYNAMIC_GATTDB SLI_BT_USE_BGAPI_CLASS(bt, gattdb), +#else +#define SLI_BT_FEATURE_DYNAMIC_GATTDB +#define SLI_BT_BGAPI_DYNAMIC_GATTDB +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_GATT_SERVER_PRESENT) +#define SLI_BT_BGAPI_GATT_SERVER SLI_BT_USE_BGAPI_CLASS(bt, gatt_server), +#else +#define SLI_BT_BGAPI_GATT_SERVER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_RECEIVER_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, cte_receiver); +#define SLI_BT_FEATURE_CTE_RECEIVER SLI_BT_USE_FEATURE(bt, cte_receiver), +#define SLI_BT_BGAPI_CTE_RECEIVER SLI_BT_USE_BGAPI_CLASS(bt, cte_receiver), +#else +#define SLI_BT_FEATURE_CTE_RECEIVER +#define SLI_BT_BGAPI_CTE_RECEIVER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_TRANSMITTER_PRESENT) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_TRANSMITTER_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, cte_transmitter); +#define SLI_BT_FEATURE_CTE_TRANSMITTER SLI_BT_USE_FEATURE(bt, cte_transmitter), +#define SLI_BT_BGAPI_CTE_TRANSMITTER SLI_BT_USE_BGAPI_CLASS(bt, cte_transmitter), +#else +#define SLI_BT_FEATURE_CTE_TRANSMITTER +#define SLI_BT_BGAPI_CTE_TRANSMITTER +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_TEST_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, test); +#define SLI_BT_FEATURE_TEST SLI_BT_USE_FEATURE(bt, test), +#define SLI_BT_BGAPI_TEST SLI_BT_USE_BGAPI_CLASS(bt, test), +#else +#define SLI_BT_FEATURE_TEST +#define SLI_BT_BGAPI_TEST +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_WHITELISTING_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, whitelisting); +#define SLI_BT_FEATURE_WHITELISTING SLI_BT_USE_FEATURE(bt, whitelisting), +#else +#define SLI_BT_FEATURE_WHITELISTING +#endif + +#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) +#define SLI_BT_BGAPI_COEX SLI_BT_USE_BGAPI_CLASS(bt, coex), +#else +#define SLI_BT_BGAPI_COEX +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOURCE_REPORT_PRESENT) +#define SLI_BT_BGAPI_RESOURCE SLI_BT_USE_BGAPI_CLASS(bt, resource), +#else +#define SLI_BT_BGAPI_RESOURCE +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USE_ACCURATE_API_ADDRESS_TYPES_PRESENT) +SLI_BT_DECLARE_FEATURE(bt, accurate_api_address_types); +#define SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES SLI_BT_USE_FEATURE(bt, accurate_api_address_types), +#else +#define SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) +#define SLI_BT_BGAPI_CONNECTION_ANALYZER SLI_BT_USE_BGAPI_CLASS(bt, connection_analyzer), +#else +#define SLI_BT_BGAPI_CONNECTION_ANALYZER +#endif + +/** @brief Structure that specifies the Bluetooth configuration */ +static const sl_bt_configuration_t bt_config = SL_BT_CONFIG_DEFAULT; + +/** @brief Table of used Bluetooth features */ +static const struct sli_bt_feature_use bt_used_features[] = +{ + // Invoke the feature inclusion macro for each feature. Depending on the build + // configuration, the feature inclusion rules above have defined the macro to + // either empty or the relevant feature use declaration. + SLI_BT_FEATURE_ON_DEMAND_START + SLI_BT_FEATURE_SYSTEM + SLI_BT_FEATURE_SM + SLI_BT_FEATURE_BUILTIN_BONDING_DATABASE + SLI_BT_FEATURE_EXTERNAL_BONDING_DATABASE + SLI_BT_FEATURE_ACCEPT_LIST + SLI_BT_FEATURE_RESOLVING_LIST + SLI_BT_FEATURE_SCANNER + SLI_BT_FEATURE_SCANNER_COMPATIBILITY + SLI_BT_FEATURE_SCANNER_BASE + SLI_BT_FEATURE_EXTENDED_SCANNER + SLI_BT_FEATURE_SYNC + SLI_BT_FEATURE_SYNC_SCANNER + SLI_BT_FEATURE_SYNC_COMPATIBILITY + SLI_BT_FEATURE_ADVERTISER + SLI_BT_FEATURE_ADVERTISER_COMPATIBILITY + SLI_BT_FEATURE_EXTENDED_ADVERTISER + SLI_BT_FEATURE_PERIODIC_ADV + SLI_BT_FEATURE_PERIODIC_ADVERTISER + SLI_BT_FEATURE_CS + SLI_BT_FEATURE_CS_TEST + SLI_BT_FEATURE_L2CAP + SLI_BT_FEATURE_CONNECTION + SLI_BT_FEATURE_CONNECTION_STATISTICS + SLI_BT_FEATURE_DYNAMIC_GATTDB + SLI_BT_FEATURE_CTE_RECEIVER + SLI_BT_FEATURE_CTE_TRANSMITTER + SLI_BT_FEATURE_TEST + SLI_BT_FEATURE_POWER_CONTROL + SLI_BT_FEATURE_USER_POWER_CONTROL + SLI_BT_FEATURE_GATT + SLI_BT_FEATURE_WHITELISTING + SLI_BT_FEATURE_ACCURATE_API_ADDRESS_TYPES + { NULL, NULL } +}; + +/** @brief Table of used BGAPI classes */ +static const struct sli_bgapi_class * const bt_bgapi_classes[] = +{ + // Invoke the BGAPI class inclusion macro for each feature that provides a + // BGAPI class. Depending on the build configuration, the feature inclusion + // rules above have defined the macro to either empty or the relevant BGAPI + // class declaration. + SLI_BT_BGAPI_SYSTEM + SLI_BT_BGAPI_NVM + SLI_BT_BGAPI_OTA_CONFIG + SLI_BT_BGAPI_GAP + SLI_BT_BGAPI_SM + SLI_BT_BGAPI_EXTERNAL_BONDINGDB + SLI_BT_BGAPI_ACCEPT_LIST + SLI_BT_BGAPI_RESOLVING_LIST + SLI_BT_BGAPI_ADVERTISER + SLI_BT_BGAPI_LEGACY_ADVERTISER + SLI_BT_BGAPI_EXTENDED_ADVERTISER + SLI_BT_BGAPI_PERIODIC_ADVERTISER + SLI_BT_BGAPI_PAWR_ADVERTISER + SLI_BT_BGAPI_SCANNER + SLI_BT_BGAPI_SYNC + SLI_BT_BGAPI_SYNC_SCANNER + SLI_BT_BGAPI_PERIODIC_SYNC + SLI_BT_BGAPI_PAWR_SYNC + SLI_BT_BGAPI_PAST_RECEIVER + SLI_BT_BGAPI_ADVERTISER_PAST + SLI_BT_BGAPI_SYNC_PAST + SLI_BT_BGAPI_CS + SLI_BT_BGAPI_CS_TEST + SLI_BT_BGAPI_L2CAP + SLI_BT_BGAPI_CONNECTION + SLI_BT_BGAPI_GATT + SLI_BT_BGAPI_DYNAMIC_GATTDB + SLI_BT_BGAPI_GATT_SERVER + SLI_BT_BGAPI_CTE_RECEIVER + SLI_BT_BGAPI_CTE_TRANSMITTER + SLI_BT_BGAPI_TEST + SLI_BT_BGAPI_COEX + SLI_BT_BGAPI_RESOURCE + SLI_BT_BGAPI_CONNECTION_ANALYZER + NULL +}; + +// Forward declaration of Bluetooth controller init functions +extern void ll_addrEnable(); +extern sl_status_t sl_bt_ll_deinit(); +#include "sl_bt_ll_config.h" +extern sl_status_t ll_connPowerControlEnable(const sl_bt_ll_power_control_config_t *); +extern void sl_bt_init_app_controlled_tx_power(); +extern sl_status_t sl_btctrl_init_sniff(uint8_t); +extern void sl_btctrl_deinit_sniff(void); +#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) +#include "coexistence-ble.h" +#endif + +/** + * @brief Initialize controller features according to the feature selection. + * + * This function is called by the Bluetooth host stack when Bluetooth is started. + */ +sl_status_t sli_bt_init_controller_features() +{ + sl_status_t status = SL_STATUS_OK; + +#if defined(SL_CATALOG_RAIL_UTIL_COEX_PRESENT) + sl_bt_init_coex_hal(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_MULTIPROTOCOL_PRESENT) + sl_btctrl_init_multiprotocol(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RADIO_WATCHDOG_PRESENT) + sl_btctrl_enable_radio_watchdog(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) + sl_btctrl_init_adv(); +#endif + +#if defined(SLI_BT_ENABLE_EXTENDED_ADVERTISER_FEATURE) + sl_btctrl_init_adv_ext(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SCANNER_PRESENT) + sl_btctrl_init_scan(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EVEN_SCHEDULING_PRESENT) + sl_btctrl_enable_even_connsch(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PAWR_SCHEDULING_PRESENT) + sl_btctrl_enable_pawr_connsch(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) + sl_btctrl_init_conn(); +#if !defined(SL_CATALOG_BLUETOOTH_CONNECTION_PHY_UPDATE_INCOMPATIBLE_PRESENT) + sl_btctrl_init_phy(); +#endif +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_STATISTICS_PRESENT) + sl_btctrl_init_conn_statistics(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_POWER_CONTROL_PRESENT) +#include "sl_bt_power_control_config.h" + const sl_bt_ll_power_control_config_t power_control_config = { + .activate_power_control = SL_BT_ACTIVATE_POWER_CONTROL, + .golden_rssi_min_1m = SL_BT_GOLDEN_RSSI_MIN_1M, + .golden_rssi_max_1m = SL_BT_GOLDEN_RSSI_MAX_1M, + .golden_rssi_min_2m = SL_BT_GOLDEN_RSSI_MIN_2M, + .golden_rssi_max_2m = SL_BT_GOLDEN_RSSI_MAX_2M, + .golden_rssi_min_coded_s8 = SL_BT_GOLDEN_RSSI_MIN_CODED_S8, + .golden_rssi_max_coded_s8 = SL_BT_GOLDEN_RSSI_MAX_CODED_S8, + .golden_rssi_min_coded_s2 = SL_BT_GOLDEN_RSSI_MIN_CODED_S2, + .golden_rssi_max_coded_s2 = SL_BT_GOLDEN_RSSI_MAX_CODED_S2 + }; + + status = ll_connPowerControlEnable(&power_control_config); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_USER_POWER_CONTROL_PRESENT) + sl_bt_init_app_controlled_tx_power(); +#endif + +#if defined(SLI_BT_ENABLE_EXTENDED_SCANNER_FEATURE) + sl_btctrl_init_scan_ext(); +#endif + +#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) + // A build with the host stack doesn't have the dedicated config file + // "sl_bluetooth_periodic_adv_config.h". We use the global advertiser count to + // enable all advertisers as periodic advertisers. +#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS +#include "sl_bluetooth_config.h" + sl_btctrl_init_periodic_adv(); + status = sl_btctrl_alloc_periodic_adv(SL_BT_CONFIG_MAX_ADVERTISERS); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) +#include "sl_bt_periodic_advertiser_config.h" + sl_btctrl_init_periodic_adv(); + sl_btctrl_alloc_periodic_adv(SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) +#include "sl_bt_pawr_advertiser_config.h" + struct sl_btctrl_pawr_advertiser_config pawr_config = { + .max_pawr_sets = SL_BT_CONFIG_MAX_PAWR_ADVERTISERS, + .max_advertised_data_length_hint = SL_BT_CONFIG_MAX_PAWR_ADVERTISED_DATA_LENGTH_HINT, + .subevent_data_request_count = SL_BT_CONFIG_PAWR_PACKET_REQUEST_COUNT, + .subevent_data_request_advance = SL_BT_CONFIG_PAWR_PACKET_REQUEST_ADVANCE, + }; + status = sl_btctrl_pawr_advertiser_configure(&pawr_config); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) +#include "sl_bluetooth_periodic_sync_config.h" + sl_btctrl_init_periodic_scan(); + status = sl_btctrl_alloc_periodic_scan(SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) +#include "sl_bt_pawr_sync_config.h" + struct sl_btctrl_pawr_synchronizer_config pawr_sync_config = { + .max_pawr_sets = SL_BT_CONFIG_MAX_PAWR_SYNCHRONIZERS, + }; + status = sl_btctrl_pawr_synchronizer_configure(&pawr_sync_config); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) +#include "sl_bt_resolving_list_config.h" + sl_btctrl_init_privacy(); + status = sl_btctrl_allocate_resolving_list_memory(SL_BT_CONFIG_RESOLVING_LIST_SIZE); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AFH_PRESENT) + status = sl_btctrl_init_afh(1); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_HIGH_POWER_PRESENT) + sl_btctrl_init_highpower(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PHY_SUPPORT_CONFIG_PRESENT) +#include "sl_btctrl_phy_support_config.h" +#if SL_BT_CONTROLLER_2M_PHY_SUPPORT == 0 + sl_btctrl_disable_2m_phy(); +#endif +#if SL_BT_CONTROLLER_CODED_PHY_SUPPORT == 0 + sl_btctrl_disable_coded_phy(); +#endif +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_WHITELISTING_PRESENT) + ll_addrEnable(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_RECEIVER_PRESENT) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_RECEIVER_PRESENT) + status = sl_btctrl_init_cte_receiver(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_AOA_TRANSMITTER_PRESENT) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_AOD_TRANSMITTER_PRESENT) + status = sl_btctrl_init_cte_transmitter(); + if (status != SL_STATUS_OK) { + return status; + } +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PAST_PRESENT) + sl_btctrl_init_past_local_sync_transfer(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PAST_PRESENT) + sl_btctrl_init_past_remote_sync_transfer(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAST_RECEIVER_PRESENT) + sl_btctrl_init_past_receiver(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CS_PRESENT) +#include "sl_bluetooth_cs_config.h" + struct sl_btctrl_cs_config cs_config = { 0 }; + cs_config.configs_per_connection = SL_BT_CONFIG_MAX_CS_CONFIGS_PER_CONNECTION; + cs_config.procedures = SL_BT_CONFIG_MAX_CS_PROCEDURES; + sl_btctrl_init_cs(&cs_config); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) +#include "sl_bluetooth_connection_analyzer_config.h" + status = sl_btctrl_init_sniff(SL_BT_CONFIG_MAX_CONNECTION_ANALYZERS); + if (status != SL_STATUS_OK) { + return status; + } +#endif + + return status; +} + +/** + * @brief De-initialize controller features according to the feature selection. + * + * This function is called by the Bluetooth host stack when Bluetooth is stopped. + */ +void sli_bt_deinit_controller_features() +{ +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_ANALYZER_PRESENT) + sl_btctrl_deinit_sniff(); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_RESOLVING_LIST_PRESENT) + sl_btctrl_allocate_resolving_list_memory(0); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) + sl_btctrl_alloc_periodic_scan(0); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) + struct sl_btctrl_pawr_advertiser_config pawr_config = { + .max_pawr_sets = 0, + .max_advertised_data_length_hint = 0, + .subevent_data_request_count = 0, + .subevent_data_request_advance = 0, + }; + (void) sl_btctrl_pawr_advertiser_configure(&pawr_config); +#endif + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_SYNC_PRESENT) + struct sl_btctrl_pawr_synchronizer_config pawr_sync_config = { + .max_pawr_sets = 0, + }; + (void) sl_btctrl_pawr_synchronizer_configure(&pawr_sync_config); +#endif + +#if defined(SLI_BT_ENABLE_PERIODIC_ADV_FEATURE) \ + || defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) + (void) sl_btctrl_alloc_periodic_adv(0); +#endif + + (void) sl_bt_ll_deinit(); +} + +// Initialize the Bluetooth stack. +sl_status_t sl_bt_stack_init() +{ + // Initialize the Bluetooth stack with the given configuration, features, and BGAPI classes + return sli_bt_init_stack(&bt_config, bt_used_features, bt_bgapi_classes); } \ No newline at end of file diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_accept_list_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_accept_list_config.c index b26aa67..53d688c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_accept_list_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_accept_list_config.c @@ -1,28 +1,28 @@ -/***************************************************************************//** - * @file sli_bt_accept_list_config.c - * @brief Configuration instance for "accept_list" - ******************************************************************************* - * # License - * Copyright 2023 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_accept_list_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT) -#include "sl_bt_accept_list_config.h" - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, accept_list, sli_bt_accept_list_config_t) = { - .accept_list_size = SL_BT_CONFIG_ACCEPT_LIST_SIZE -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT +/***************************************************************************//** + * @file sli_bt_accept_list_config.c + * @brief Configuration instance for "accept_list" + ******************************************************************************* + * # License + * Copyright 2023 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_accept_list_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT) +#include "sl_bt_accept_list_config.h" + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, accept_list, sli_bt_accept_list_config_t) = { + .accept_list_size = SL_BT_CONFIG_ACCEPT_LIST_SIZE +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_ACCEPT_LIST_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_advertiser_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_advertiser_config.c index d7c1231..1f435ee 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_advertiser_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_advertiser_config.c @@ -1,33 +1,33 @@ -/***************************************************************************//** - * @file sli_bt_advertiser_config.c - * @brief Configuration instance for "advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_advertiser_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) -#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS -#include "sl_bluetooth_config.h" - -// Note that advertiser configuration is not dictated directly by the advertiser -// component's configuration file. The top-level Bluetooth stack configuration -// calculates a sum of all advertiser needs, and that value is used to configure -// the advertiser feature. -SLI_BT_DEFINE_FEATURE_CONFIG(bt, advertiser, sli_bt_advertiser_config_t) = { - .max_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT +/***************************************************************************//** + * @file sli_bt_advertiser_config.c + * @brief Configuration instance for "advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_advertiser_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT) +#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS +#include "sl_bluetooth_config.h" + +// Note that advertiser configuration is not dictated directly by the advertiser +// component's configuration file. The top-level Bluetooth stack configuration +// calculates a sum of all advertiser needs, and that value is used to configure +// the advertiser feature. +SLI_BT_DEFINE_FEATURE_CONFIG(bt, advertiser, sli_bt_advertiser_config_t) = { + .max_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_ADVERTISER_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_connection_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_connection_config.c index fe996d0..de48934 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_connection_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_connection_config.c @@ -1,35 +1,35 @@ -/***************************************************************************//** - * @file sli_bt_connection_config.c - * @brief Configuration instanc for "connection" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_connection_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) -#include "sl_bluetooth.h" // For SL_BT_COMPONENT_CONNECTIONS -#include "sl_bluetooth_config.h" -#include "sl_bluetooth_connection_config.h" - -// Note that connection configuration is not dictated directly by the connection -// component's configuration file. The top-level Bluetooth stack configuration -// calculates a sum of all connection needs, and that value is used to configure -// the connection feature. -SLI_BT_DEFINE_FEATURE_CONFIG(bt, connection, sli_bt_connection_config_t) = { - .max_connections = SL_BT_CONFIG_MAX_CONNECTIONS_SUM, - .data_len = SL_BT_CONFIG_CONNECTION_DATA_LENGTH -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT +/***************************************************************************//** + * @file sli_bt_connection_config.c + * @brief Configuration instanc for "connection" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_connection_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT) +#include "sl_bluetooth.h" // For SL_BT_COMPONENT_CONNECTIONS +#include "sl_bluetooth_config.h" +#include "sl_bluetooth_connection_config.h" + +// Note that connection configuration is not dictated directly by the connection +// component's configuration file. The top-level Bluetooth stack configuration +// calculates a sum of all connection needs, and that value is used to configure +// the connection feature. +SLI_BT_DEFINE_FEATURE_CONFIG(bt, connection, sli_bt_connection_config_t) = { + .max_connections = SL_BT_CONFIG_MAX_CONNECTIONS_SUM, + .data_len = SL_BT_CONFIG_CONNECTION_DATA_LENGTH +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_CONNECTION_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c index 99f2b92..f7ebc9e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c @@ -1,41 +1,41 @@ -/***************************************************************************//** - * @file sli_bt_dynamic_gattdb_config.c - * @brief Configuration instance for "dynamic_gattdb" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc.www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc.Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement(MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_config_defs.h" -#include "sli_bt_gattdb_def.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT) -#include "sl_bt_dynamic_gattdb_config.h" - #if SL_BT_GATTDB_ENABLE_GATT_CACHING == 1 - #define GATTDB_ENABLE_GATT_CACHING SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING - #else - #define GATTDB_ENABLE_GATT_CACHING 0 - #endif - #if SL_BT_GATTDB_INCLUDE_STATIC_DATABASE == 1 - #define GATTDB_INCLUDE_STATIC SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB - #else - #define GATTDB_INCLUDE_STATIC 0 - #endif -#else // SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT - #define GATTDB_ENABLE_GATT_CACHING SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING - #define GATTDB_INCLUDE_STATIC SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB -#endif // SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, dynamic_gattdb, sli_bt_gattdb_config_t) = { - .flags = (GATTDB_ENABLE_GATT_CACHING | GATTDB_INCLUDE_STATIC) -}; +/***************************************************************************//** + * @file sli_bt_dynamic_gattdb_config.c + * @brief Configuration instance for "dynamic_gattdb" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc.www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc.Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement(MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_config_defs.h" +#include "sli_bt_gattdb_def.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT) +#include "sl_bt_dynamic_gattdb_config.h" + #if SL_BT_GATTDB_ENABLE_GATT_CACHING == 1 + #define GATTDB_ENABLE_GATT_CACHING SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING + #else + #define GATTDB_ENABLE_GATT_CACHING 0 + #endif + #if SL_BT_GATTDB_INCLUDE_STATIC_DATABASE == 1 + #define GATTDB_INCLUDE_STATIC SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB + #else + #define GATTDB_INCLUDE_STATIC 0 + #endif +#else // SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT + #define GATTDB_ENABLE_GATT_CACHING SLI_BT_GATTDB_CONFIG_FLAG_ENABLE_GATT_CACHING + #define GATTDB_INCLUDE_STATIC SLI_BT_GATTDB_CONFIG_FLAG_INCLUDE_STATIC_DB +#endif // SL_CATALOG_BLUETOOTH_FEATURE_DYNAMIC_GATTDB_PRESENT + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, dynamic_gattdb, sli_bt_gattdb_config_t) = { + .flags = (GATTDB_ENABLE_GATT_CACHING | GATTDB_INCLUDE_STATIC) +}; diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_l2cap_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_l2cap_config.c index 8824bc4..83e51b6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_l2cap_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_l2cap_config.c @@ -1,35 +1,35 @@ -/***************************************************************************//** - * @file sli_bt_l2cap_config.c - * @brief Configuration instance for "l2cap" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_l2cap_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT) -#include "sl_bluetooth_l2cap_config.h" -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EATT) -// Each Enhanced ATT bearer requires an L2CAP COC channel -#include "sl_bt_eatt_config.h" -#define SL_BT_CONFIG_MAX_L2CAP_CHANNELS (SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS + SL_BT_CONFIG_USER_EATT_BEARERS) -#else -#define SL_BT_CONFIG_MAX_L2CAP_CHANNELS SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS -#endif - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, l2cap, sli_bt_l2cap_config_t) = { - .max_l2cap_coc_channels = SL_BT_CONFIG_MAX_L2CAP_CHANNELS -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT +/***************************************************************************//** + * @file sli_bt_l2cap_config.c + * @brief Configuration instance for "l2cap" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_l2cap_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT) +#include "sl_bluetooth_l2cap_config.h" +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_EATT) +// Each Enhanced ATT bearer requires an L2CAP COC channel +#include "sl_bt_eatt_config.h" +#define SL_BT_CONFIG_MAX_L2CAP_CHANNELS (SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS + SL_BT_CONFIG_USER_EATT_BEARERS) +#else +#define SL_BT_CONFIG_MAX_L2CAP_CHANNELS SL_BT_CONFIG_USER_L2CAP_COC_CHANNELS +#endif + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, l2cap, sli_bt_l2cap_config_t) = { + .max_l2cap_coc_channels = SL_BT_CONFIG_MAX_L2CAP_CHANNELS +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_L2CAP_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c index f1e48ac..a0f3dca 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c @@ -1,28 +1,28 @@ -/***************************************************************************//** - * @file sli_bt_pawr_advertiser_config.c - * @brief Configuration instance for "pawr_advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_pawr_advertiser_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) -#include "sl_bt_pawr_advertiser_config.h" - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, pawr_advertiser, sli_bt_pawr_advertiser_config_t) = { - .max_pawr_advertisers = SL_BT_CONFIG_MAX_PAWR_ADVERTISERS -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT +/***************************************************************************//** + * @file sli_bt_pawr_advertiser_config.c + * @brief Configuration instance for "pawr_advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_pawr_advertiser_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT) +#include "sl_bt_pawr_advertiser_config.h" + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, pawr_advertiser, sli_bt_pawr_advertiser_config_t) = { + .max_pawr_advertisers = SL_BT_CONFIG_MAX_PAWR_ADVERTISERS +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_PAWR_ADVERTISER_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_adv_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_adv_config.c index 8837fac..f37f0ef 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_adv_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_adv_config.c @@ -1,44 +1,44 @@ -/***************************************************************************//** - * @file sli_bt_periodic_adv_config.c - * @brief Configuration instance for "periodic_adv" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_periodic_adv_config.h" - -// This deprecated "periodic_adv" component does not have a dedicated -// configuration file if the Bluetooth stack is present. In that case we can -// always instantiate the config using configuration from the Bluetooth stack -// and configure all advertisers to be capable of periodic advertising. -#if defined(SL_CATALOG_BLUETOOTH_PRESENT) - -#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS -#include "sl_bluetooth_config.h" -SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_adv, sli_bt_periodic_adv_config_t) = { - .max_periodic_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS -}; - -#else // SL_CATALOG_BLUETOOTH_PRESENT - -// Bluetooth stack is not present. Instantiate the configuration if the -// component is present and use its dedicated configuration. -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) -#include "sl_bluetooth_periodic_adv_config.h" -SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_adv, sli_bt_periodic_adv_config_t) = { - .max_periodic_advertisers = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS -}; -#endif // SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT - -#endif // SL_CATALOG_BLUETOOTH_PRESENT +/***************************************************************************//** + * @file sli_bt_periodic_adv_config.c + * @brief Configuration instance for "periodic_adv" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_periodic_adv_config.h" + +// This deprecated "periodic_adv" component does not have a dedicated +// configuration file if the Bluetooth stack is present. In that case we can +// always instantiate the config using configuration from the Bluetooth stack +// and configure all advertisers to be capable of periodic advertising. +#if defined(SL_CATALOG_BLUETOOTH_PRESENT) + +#include "sl_bluetooth.h" // For SL_BT_COMPONENT_ADVERTISERS +#include "sl_bluetooth_config.h" +SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_adv, sli_bt_periodic_adv_config_t) = { + .max_periodic_advertisers = SL_BT_CONFIG_MAX_ADVERTISERS +}; + +#else // SL_CATALOG_BLUETOOTH_PRESENT + +// Bluetooth stack is not present. Instantiate the configuration if the +// component is present and use its dedicated configuration. +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT) +#include "sl_bluetooth_periodic_adv_config.h" +SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_adv, sli_bt_periodic_adv_config_t) = { + .max_periodic_advertisers = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS +}; +#endif // SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADV_PRESENT + +#endif // SL_CATALOG_BLUETOOTH_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c index 4d2ca3c..dba649d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c @@ -1,28 +1,28 @@ -/***************************************************************************//** - * @file sli_bt_periodic_advertiser_config.c - * @brief Configuration instance for "periodic_advertiser" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_periodic_advertiser_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) -#include "sl_bt_periodic_advertiser_config.h" - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_advertiser, sli_bt_periodic_advertiser_config_t) = { - .max_periodic_advertisers = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT +/***************************************************************************//** + * @file sli_bt_periodic_advertiser_config.c + * @brief Configuration instance for "periodic_advertiser" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_periodic_advertiser_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT) +#include "sl_bt_periodic_advertiser_config.h" + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, periodic_advertiser, sli_bt_periodic_advertiser_config_t) = { + .max_periodic_advertisers = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISERS +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_PERIODIC_ADVERTISER_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_sync_config.c b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_sync_config.c index 5dfe6a0..290cff9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_sync_config.c +++ b/locator_ncp/gecko_sdk_4.4.1/protocol/bluetooth/src/sli_bt_sync_config.c @@ -1,28 +1,28 @@ -/***************************************************************************//** - * @file sli_bt_sync_config.c - * @brief Configuration instance for "sync" - ******************************************************************************* - * # License - * Copyright 2021 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_component_catalog.h" -#include "sli_bt_sync_config.h" - -#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) -#include "sl_bluetooth_periodic_sync_config.h" - -SLI_BT_DEFINE_FEATURE_CONFIG(bt, sync, sli_bt_sync_config_t) = { - .max_periodic_syncs = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC -}; - -#endif // SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT +/***************************************************************************//** + * @file sli_bt_sync_config.c + * @brief Configuration instance for "sync" + ******************************************************************************* + * # License + * Copyright 2021 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_component_catalog.h" +#include "sli_bt_sync_config.h" + +#if defined(SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT) +#include "sl_bluetooth_periodic_sync_config.h" + +SLI_BT_DEFINE_FEATURE_CONFIG(bt, sync, sli_bt_sync_config_t) = { + .max_periodic_syncs = SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC +}; + +#endif // SL_CATALOG_BLUETOOTH_FEATURE_SYNC_PRESENT diff --git a/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c b/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c index c5528aa..91c3405 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c @@ -1,101 +1,101 @@ -/***************************************************************************//** - * @file - * @brief This is a simple wrapper for the stdlib memory management functions - * like malloc, calloc, realloc and free in order to make them - * thread safe. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#include "sl_malloc.h" -#include "em_core.h" -#include - -/***************************************************************************//** - * @brief - * Wrap a call to stdlib malloc in a critical section. - * - * @param[in] size - * number of bytes to allocate. - * - * @return - * Either a pointer to the allocated space or a null pointer. - ******************************************************************************/ -void *sl_malloc(size_t size) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - void *ptr = malloc(size); - CORE_EXIT_CRITICAL(); - return ptr; -} - -/***************************************************************************//** - * @brief - * Wrap a call to stdlib calloc in a critical section. - * - * @param[in] nmemb - * number of element to allocate space for. - * - * @param[in] size - * size of each element. - * - * @return - * Either a pointer to the allocated space or a null pointer. - ******************************************************************************/ -void *sl_calloc(size_t nmemb, size_t size) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - void *ptr = calloc(nmemb, size); - CORE_EXIT_CRITICAL(); - return ptr; -} - -/***************************************************************************//** - * @brief - * Wrap a call to stdlib realloc in a critical section. - * - * @param[in] ptr - * ptr is a pointer to a memory that has previously been allocated. If ptr - * is a null pointer then this function behaves like sl_malloc. - * - * @param[in] size - * number of bytes to allocate. - * - * @return - * Either a pointer to the allocated space or a null pointer. - ******************************************************************************/ -void *sl_realloc(void * ptr, size_t size) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - void *p = realloc(ptr, size); - CORE_EXIT_CRITICAL(); - return p; -} - -/***************************************************************************//** - * @brief - * Wrap a call to stdlib free in a critical section. - * - * @param[in] ptr - * ptr is a pointer to a memory that has previously been allocated. - ******************************************************************************/ -void sl_free(void * ptr) -{ - CORE_DECLARE_IRQ_STATE; - CORE_ENTER_CRITICAL(); - free(ptr); - CORE_EXIT_CRITICAL(); -} +/***************************************************************************//** + * @file + * @brief This is a simple wrapper for the stdlib memory management functions + * like malloc, calloc, realloc and free in order to make them + * thread safe. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#include "sl_malloc.h" +#include "em_core.h" +#include + +/***************************************************************************//** + * @brief + * Wrap a call to stdlib malloc in a critical section. + * + * @param[in] size + * number of bytes to allocate. + * + * @return + * Either a pointer to the allocated space or a null pointer. + ******************************************************************************/ +void *sl_malloc(size_t size) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + void *ptr = malloc(size); + CORE_EXIT_CRITICAL(); + return ptr; +} + +/***************************************************************************//** + * @brief + * Wrap a call to stdlib calloc in a critical section. + * + * @param[in] nmemb + * number of element to allocate space for. + * + * @param[in] size + * size of each element. + * + * @return + * Either a pointer to the allocated space or a null pointer. + ******************************************************************************/ +void *sl_calloc(size_t nmemb, size_t size) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + void *ptr = calloc(nmemb, size); + CORE_EXIT_CRITICAL(); + return ptr; +} + +/***************************************************************************//** + * @brief + * Wrap a call to stdlib realloc in a critical section. + * + * @param[in] ptr + * ptr is a pointer to a memory that has previously been allocated. If ptr + * is a null pointer then this function behaves like sl_malloc. + * + * @param[in] size + * number of bytes to allocate. + * + * @return + * Either a pointer to the allocated space or a null pointer. + ******************************************************************************/ +void *sl_realloc(void * ptr, size_t size) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + void *p = realloc(ptr, size); + CORE_EXIT_CRITICAL(); + return p; +} + +/***************************************************************************//** + * @brief + * Wrap a call to stdlib free in a critical section. + * + * @param[in] ptr + * ptr is a pointer to a memory that has previously been allocated. + ******************************************************************************/ +void sl_free(void * ptr) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + free(ptr); + CORE_EXIT_CRITICAL(); +} diff --git a/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h b/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h index cc9f25a..e114b66 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/silicon_labs/silabs_core/memory_manager/sl_malloc.h @@ -1,38 +1,38 @@ -/***************************************************************************//** - * @file - * @brief This is a simple wrapper for the stdlib memory management functions - * like malloc, calloc, realloc and free in order to make them - * thread safe. - ******************************************************************************* - * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * The licensor of this software is Silicon Laboratories Inc. Your use of this - * software is governed by the terms of Silicon Labs Master Software License - * Agreement (MSLA) available at - * www.silabs.com/about-us/legal/master-software-license-agreement. This - * software is distributed to you in Source Code format and is governed by the - * sections of the MSLA applicable to Source Code. - * - ******************************************************************************/ - -#ifndef SL_MALLOC_H -#define SL_MALLOC_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -void *sl_malloc(size_t size); -void *sl_calloc(size_t nmemb, size_t size); -void *sl_realloc(void * ptr, size_t size); -void sl_free(void * ptr); - -#ifdef __cplusplus -} -#endif - -#endif // SL_MALLOC_H +/***************************************************************************//** + * @file + * @brief This is a simple wrapper for the stdlib memory management functions + * like malloc, calloc, realloc and free in order to make them + * thread safe. + ******************************************************************************* + * # License + * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * The licensor of this software is Silicon Laboratories Inc. Your use of this + * software is governed by the terms of Silicon Labs Master Software License + * Agreement (MSLA) available at + * www.silabs.com/about-us/legal/master-software-license-agreement. This + * software is distributed to you in Source Code format and is governed by the + * sections of the MSLA applicable to Source Code. + * + ******************************************************************************/ + +#ifndef SL_MALLOC_H +#define SL_MALLOC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +void *sl_malloc(size_t size); +void *sl_calloc(size_t nmemb, size_t size); +void *sl_realloc(void * ptr, size_t size); +void sl_free(void * ptr); + +#ifdef __cplusplus +} +#endif + +#endif // SL_MALLOC_H diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aes.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aes.h index 7c92162..615cd08 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aes.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aes.h @@ -1,639 +1,639 @@ -/** - * \file aes.h - * - * \brief This file contains AES definitions and functions. - * - * The Advanced Encryption Standard (AES) specifies a FIPS-approved - * cryptographic algorithm that can be used to protect electronic - * data. - * - * The AES algorithm is a symmetric block cipher that can - * encrypt and decrypt information. For more information, see - * FIPS Publication 197: Advanced Encryption Standard and - * ISO/IEC 18033-2:2006: Information technology -- Security - * techniques -- Encryption algorithms -- Part 2: Asymmetric - * ciphers. - * - * The AES-XTS block mode is standardized by NIST SP 800-38E - * - * and described in detail by IEEE P1619 - * . - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_AES_H -#define MBEDTLS_AES_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" -#include "mbedtls/platform_util.h" - -#include -#include - -/* padlock.c and aesni.c rely on these values! */ -#define MBEDTLS_AES_ENCRYPT 1 /**< AES encryption. */ -#define MBEDTLS_AES_DECRYPT 0 /**< AES decryption. */ - -/* Error codes in range 0x0020-0x0022 */ -/** Invalid key length. */ -#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH -0x0020 -/** Invalid data input length. */ -#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH -0x0022 - -/* Error codes in range 0x0021-0x0025 */ -/** Invalid input data. */ -#define MBEDTLS_ERR_AES_BAD_INPUT_DATA -0x0021 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_AES_ALT) -// Regular implementation -// - -/** - * \brief The AES context-type definition. - */ -typedef struct mbedtls_aes_context { - int MBEDTLS_PRIVATE(nr); /*!< The number of rounds. */ - size_t MBEDTLS_PRIVATE(rk_offset); /*!< The offset in array elements to AES - round keys in the buffer. */ -#if defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) && !defined(MBEDTLS_PADLOCK_C) - uint32_t MBEDTLS_PRIVATE(buf)[44]; /*!< Aligned data buffer to hold - 10 round keys for 128-bit case. */ -#else - uint32_t MBEDTLS_PRIVATE(buf)[68]; /*!< Unaligned data buffer. This buffer can - hold 32 extra Bytes, which can be used for - one of the following purposes: -
  • Alignment if VIA padlock is - used.
    • -
  • Simplifying key expansion in the 256-bit - case by generating an extra round key. -
*/ -#endif /* MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH && !MBEDTLS_PADLOCK_C */ -} -mbedtls_aes_context; - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -/** - * \brief The AES XTS context-type definition. - */ -typedef struct mbedtls_aes_xts_context { - mbedtls_aes_context MBEDTLS_PRIVATE(crypt); /*!< The AES context to use for AES block - encryption or decryption. */ - mbedtls_aes_context MBEDTLS_PRIVATE(tweak); /*!< The AES context used for tweak - computation. */ -} mbedtls_aes_xts_context; -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -#else /* MBEDTLS_AES_ALT */ -#include "aes_alt.h" -#endif /* MBEDTLS_AES_ALT */ - -/** - * \brief This function initializes the specified AES context. - * - * It must be the first API called before using - * the context. - * - * \param ctx The AES context to initialize. This must not be \c NULL. - */ -void mbedtls_aes_init(mbedtls_aes_context *ctx); - -/** - * \brief This function releases and clears the specified AES context. - * - * \param ctx The AES context to clear. - * If this is \c NULL, this function does nothing. - * Otherwise, the context must have been at least initialized. - */ -void mbedtls_aes_free(mbedtls_aes_context *ctx); - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -/** - * \brief This function initializes the specified AES XTS context. - * - * It must be the first API called before using - * the context. - * - * \param ctx The AES XTS context to initialize. This must not be \c NULL. - */ -void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx); - -/** - * \brief This function releases and clears the specified AES XTS context. - * - * \param ctx The AES XTS context to clear. - * If this is \c NULL, this function does nothing. - * Otherwise, the context must have been at least initialized. - */ -void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx); -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -/** - * \brief This function sets the encryption key. - * - * \param ctx The AES context to which the key should be bound. - * It must be initialized. - * \param key The encryption key. - * This must be a readable buffer of size \p keybits bits. - * \param keybits The size of data passed in bits. Valid options are: - *
  • 128 bits
    • - *
  • 192 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function sets the decryption key. - * - * \param ctx The AES context to which the key should be bound. - * It must be initialized. - * \param key The decryption key. - * This must be a readable buffer of size \p keybits bits. - * \param keybits The size of data passed. Valid options are: - *
  • 128 bits
    • - *
  • 192 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, - unsigned int keybits); - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -/** - * \brief This function prepares an XTS context for encryption and - * sets the encryption key. - * - * \param ctx The AES XTS context to which the key should be bound. - * It must be initialized. - * \param key The encryption key. This is comprised of the XTS key1 - * concatenated with the XTS key2. - * This must be a readable buffer of size \p keybits bits. - * \param keybits The size of \p key passed in bits. Valid options are: - *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • - *
  • 512 bits (each of key1 and key2 is a 256-bit key)
- * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function prepares an XTS context for decryption and - * sets the decryption key. - * - * \param ctx The AES XTS context to which the key should be bound. - * It must be initialized. - * \param key The decryption key. This is comprised of the XTS key1 - * concatenated with the XTS key2. - * This must be a readable buffer of size \p keybits bits. - * \param keybits The size of \p key passed in bits. Valid options are: - *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • - *
  • 512 bits (each of key1 and key2 is a 256-bit key)
- * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, - const unsigned char *key, - unsigned int keybits); -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -/** - * \brief This function performs an AES single-block encryption or - * decryption operation. - * - * It performs the operation defined in the \p mode parameter - * (encrypt or decrypt), on the input data buffer defined in - * the \p input parameter. - * - * mbedtls_aes_init(), and either mbedtls_aes_setkey_enc() or - * mbedtls_aes_setkey_dec() must be called before the first - * call to this API with the same context. - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or - * #MBEDTLS_AES_DECRYPT. - * \param input The buffer holding the input data. - * It must be readable and at least \c 16 Bytes long. - * \param output The buffer where the output data will be written. - * It must be writeable and at least \c 16 Bytes long. - - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16]); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief This function performs an AES-CBC encryption or decryption operation - * on full blocks. - * - * It performs the operation defined in the \p mode - * parameter (encrypt/decrypt), on the input data buffer defined in - * the \p input parameter. - * - * It can be called as many times as needed, until all the input - * data is processed. mbedtls_aes_init(), and either - * mbedtls_aes_setkey_enc() or mbedtls_aes_setkey_dec() must be called - * before the first call to this API with the same context. - * - * \note This function operates on full blocks, that is, the input size - * must be a multiple of the AES block size of \c 16 Bytes. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the same function again on the next - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If you need to retain the contents of the IV, you should - * either save it manually or use the cipher module instead. - * - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or - * #MBEDTLS_AES_DECRYPT. - * \param length The length of the input data in Bytes. This must be a - * multiple of the block size (\c 16 Bytes). - * \param iv Initialization vector (updated after use). - * It must be a readable and writeable buffer of \c 16 Bytes. - * \param input The buffer holding the input data. - * It must be readable and of size \p length Bytes. - * \param output The buffer holding the output data. - * It must be writeable and of size \p length Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH - * on failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -/** - * \brief This function performs an AES-XTS encryption or decryption - * operation for an entire XTS data unit. - * - * AES-XTS encrypts or decrypts blocks based on their location as - * defined by a data unit number. The data unit number must be - * provided by \p data_unit. - * - * NIST SP 800-38E limits the maximum size of a data unit to 2^20 - * AES blocks. If the data unit is larger than this, this function - * returns #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH. - * - * \param ctx The AES XTS context to use for AES XTS operations. - * It must be initialized and bound to a key. - * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or - * #MBEDTLS_AES_DECRYPT. - * \param length The length of a data unit in Bytes. This can be any - * length between 16 bytes and 2^24 bytes inclusive - * (between 1 and 2^20 block cipher blocks). - * \param data_unit The address of the data unit encoded as an array of 16 - * bytes in little-endian format. For disk encryption, this - * is typically the index of the block device sector that - * contains the data. - * \param input The buffer holding the input data (which is an entire - * data unit). This function reads \p length Bytes from \p - * input. - * \param output The buffer holding the output data (which is an entire - * data unit). This function writes \p length Bytes to \p - * output. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH if \p length is - * smaller than an AES block in size (16 Bytes) or if \p - * length is larger than 2^20 blocks (16 MiB). - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, - int mode, - size_t length, - const unsigned char data_unit[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -/** - * \brief This function performs an AES-CFB128 encryption or decryption - * operation. - * - * It performs the operation defined in the \p mode - * parameter (encrypt or decrypt), on the input data buffer - * defined in the \p input parameter. - * - * For CFB, you must set up the context with mbedtls_aes_setkey_enc(), - * regardless of whether you are performing an encryption or decryption - * operation, that is, regardless of the \p mode parameter. This is - * because CFB mode uses the same key schedule for encryption and - * decryption. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the same function again on the next - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If you need to retain the contents of the - * IV, you must either save it manually or use the cipher - * module instead. - * - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or - * #MBEDTLS_AES_DECRYPT. - * \param length The length of the input data in Bytes. - * \param iv_off The offset in IV (updated after use). - * It must point to a valid \c size_t. - * \param iv The initialization vector (updated after use). - * It must be a readable and writeable buffer of \c 16 Bytes. - * \param input The buffer holding the input data. - * It must be readable and of size \p length Bytes. - * \param output The buffer holding the output data. - * It must be writeable and of size \p length Bytes. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function performs an AES-CFB8 encryption or decryption - * operation. - * - * It performs the operation defined in the \p mode - * parameter (encrypt/decrypt), on the input data buffer defined - * in the \p input parameter. - * - * Due to the nature of CFB, you must use the same key schedule for - * both encryption and decryption operations. Therefore, you must - * use the context initialized with mbedtls_aes_setkey_enc() for - * both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the same function again on the next - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or - * #MBEDTLS_AES_DECRYPT - * \param length The length of the input data. - * \param iv The initialization vector (updated after use). - * It must be a readable and writeable buffer of \c 16 Bytes. - * \param input The buffer holding the input data. - * It must be readable and of size \p length Bytes. - * \param output The buffer holding the output data. - * It must be writeable and of size \p length Bytes. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); -#endif /*MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_OFB) -/** - * \brief This function performs an AES-OFB (Output Feedback Mode) - * encryption or decryption operation. - * - * For OFB, you must set up the context with - * mbedtls_aes_setkey_enc(), regardless of whether you are - * performing an encryption or decryption operation. This is - * because OFB mode uses the same key schedule for encryption and - * decryption. - * - * The OFB operation is identical for encryption or decryption, - * therefore no operation mode needs to be specified. - * - * \note Upon exit, the content of iv, the Initialisation Vector, is - * updated so that you can call the same function again on the next - * block(s) of data and get the same result as if it was encrypted - * in one call. This allows a "streaming" usage, by initialising - * iv_off to 0 before the first call, and preserving its value - * between calls. - * - * For non-streaming use, the iv should be initialised on each call - * to a unique value, and iv_off set to 0 on each call. - * - * If you need to retain the contents of the initialisation vector, - * you must either save it manually or use the cipher module - * instead. - * - * \warning For the OFB mode, the initialisation vector must be unique - * every encryption operation. Reuse of an initialisation vector - * will compromise security. - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param length The length of the input data. - * \param iv_off The offset in IV (updated after use). - * It must point to a valid \c size_t. - * \param iv The initialization vector (updated after use). - * It must be a readable and writeable buffer of \c 16 Bytes. - * \param input The buffer holding the input data. - * It must be readable and of size \p length Bytes. - * \param output The buffer holding the output data. - * It must be writeable and of size \p length Bytes. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -#endif /* MBEDTLS_CIPHER_MODE_OFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -/** - * \brief This function performs an AES-CTR encryption or decryption - * operation. - * - * Due to the nature of CTR, you must use the same key schedule - * for both encryption and decryption operations. Therefore, you - * must use the context initialized with mbedtls_aes_setkey_enc() - * for both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. - * - * \warning You must never reuse a nonce value with the same key. Doing so - * would void the encryption for the two messages encrypted with - * the same nonce and key. - * - * There are two common strategies for managing nonces with CTR: - * - * 1. You can handle everything as a single message processed over - * successive calls to this function. In that case, you want to - * set \p nonce_counter and \p nc_off to 0 for the first call, and - * then preserve the values of \p nonce_counter, \p nc_off and \p - * stream_block across calls to this function as they will be - * updated by this function. - * - * With this strategy, you must not encrypt more than 2**128 - * blocks of data with the same key. - * - * 2. You can encrypt separate messages by dividing the \p - * nonce_counter buffer in two areas: the first one used for a - * per-message nonce, handled by yourself, and the second one - * updated by this function internally. - * - * For example, you might reserve the first 12 bytes for the - * per-message nonce, and the last 4 bytes for internal use. In that - * case, before calling this function on a new message you need to - * set the first 12 bytes of \p nonce_counter to your chosen nonce - * value, the last 4 to 0, and \p nc_off to 0 (which will cause \p - * stream_block to be ignored). That way, you can encrypt at most - * 2**96 messages of up to 2**32 blocks each with the same key. - * - * The per-message nonce (or information sufficient to reconstruct - * it) needs to be communicated with the ciphertext and must be unique. - * The recommended way to ensure uniqueness is to use a message - * counter. An alternative is to generate random nonces, but this - * limits the number of messages that can be securely encrypted: - * for example, with 96-bit random nonces, you should not encrypt - * more than 2**32 messages with the same key. - * - * Note that for both strategies, sizes are measured in blocks and - * that an AES block is 16 bytes. - * - * \warning Upon return, \p stream_block contains sensitive data. Its - * content must not be written to insecure storage and should be - * securely discarded as soon as it's no longer needed. - * - * \param ctx The AES context to use for encryption or decryption. - * It must be initialized and bound to a key. - * \param length The length of the input data. - * \param nc_off The offset in the current \p stream_block, for - * resuming within the current cipher stream. The - * offset pointer should be 0 at the start of a stream. - * It must point to a valid \c size_t. - * \param nonce_counter The 128-bit nonce and counter. - * It must be a readable-writeable buffer of \c 16 Bytes. - * \param stream_block The saved stream block for resuming. This is - * overwritten by the function. - * It must be a readable-writeable buffer of \c 16 Bytes. - * \param input The buffer holding the input data. - * It must be readable and of size \p length Bytes. - * \param output The buffer holding the output data. - * It must be writeable and of size \p length Bytes. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -/** - * \brief Internal AES block encryption function. This is only - * exposed to allow overriding it using - * \c MBEDTLS_AES_ENCRYPT_ALT. - * - * \param ctx The AES context to use for encryption. - * \param input The plaintext block. - * \param output The output (ciphertext) block. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16]); - -/** - * \brief Internal AES block decryption function. This is only - * exposed to allow overriding it using see - * \c MBEDTLS_AES_DECRYPT_ALT. - * - * \param ctx The AES context to use for decryption. - * \param input The ciphertext block. - * \param output The output (plaintext) block. - * - * \return \c 0 on success. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, - const unsigned char input[16], - unsigned char output[16]); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_aes_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* aes.h */ +/** + * \file aes.h + * + * \brief This file contains AES definitions and functions. + * + * The Advanced Encryption Standard (AES) specifies a FIPS-approved + * cryptographic algorithm that can be used to protect electronic + * data. + * + * The AES algorithm is a symmetric block cipher that can + * encrypt and decrypt information. For more information, see + * FIPS Publication 197: Advanced Encryption Standard and + * ISO/IEC 18033-2:2006: Information technology -- Security + * techniques -- Encryption algorithms -- Part 2: Asymmetric + * ciphers. + * + * The AES-XTS block mode is standardized by NIST SP 800-38E + * + * and described in detail by IEEE P1619 + * . + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_AES_H +#define MBEDTLS_AES_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" +#include "mbedtls/platform_util.h" + +#include +#include + +/* padlock.c and aesni.c rely on these values! */ +#define MBEDTLS_AES_ENCRYPT 1 /**< AES encryption. */ +#define MBEDTLS_AES_DECRYPT 0 /**< AES decryption. */ + +/* Error codes in range 0x0020-0x0022 */ +/** Invalid key length. */ +#define MBEDTLS_ERR_AES_INVALID_KEY_LENGTH -0x0020 +/** Invalid data input length. */ +#define MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH -0x0022 + +/* Error codes in range 0x0021-0x0025 */ +/** Invalid input data. */ +#define MBEDTLS_ERR_AES_BAD_INPUT_DATA -0x0021 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_AES_ALT) +// Regular implementation +// + +/** + * \brief The AES context-type definition. + */ +typedef struct mbedtls_aes_context { + int MBEDTLS_PRIVATE(nr); /*!< The number of rounds. */ + size_t MBEDTLS_PRIVATE(rk_offset); /*!< The offset in array elements to AES + round keys in the buffer. */ +#if defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) && !defined(MBEDTLS_PADLOCK_C) + uint32_t MBEDTLS_PRIVATE(buf)[44]; /*!< Aligned data buffer to hold + 10 round keys for 128-bit case. */ +#else + uint32_t MBEDTLS_PRIVATE(buf)[68]; /*!< Unaligned data buffer. This buffer can + hold 32 extra Bytes, which can be used for + one of the following purposes: +
  • Alignment if VIA padlock is + used.
    • +
  • Simplifying key expansion in the 256-bit + case by generating an extra round key. +
*/ +#endif /* MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH && !MBEDTLS_PADLOCK_C */ +} +mbedtls_aes_context; + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief The AES XTS context-type definition. + */ +typedef struct mbedtls_aes_xts_context { + mbedtls_aes_context MBEDTLS_PRIVATE(crypt); /*!< The AES context to use for AES block + encryption or decryption. */ + mbedtls_aes_context MBEDTLS_PRIVATE(tweak); /*!< The AES context used for tweak + computation. */ +} mbedtls_aes_xts_context; +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#else /* MBEDTLS_AES_ALT */ +#include "aes_alt.h" +#endif /* MBEDTLS_AES_ALT */ + +/** + * \brief This function initializes the specified AES context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES context to initialize. This must not be \c NULL. + */ +void mbedtls_aes_init(mbedtls_aes_context *ctx); + +/** + * \brief This function releases and clears the specified AES context. + * + * \param ctx The AES context to clear. + * If this is \c NULL, this function does nothing. + * Otherwise, the context must have been at least initialized. + */ +void mbedtls_aes_free(mbedtls_aes_context *ctx); + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function initializes the specified AES XTS context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The AES XTS context to initialize. This must not be \c NULL. + */ +void mbedtls_aes_xts_init(mbedtls_aes_xts_context *ctx); + +/** + * \brief This function releases and clears the specified AES XTS context. + * + * \param ctx The AES XTS context to clear. + * If this is \c NULL, this function does nothing. + * Otherwise, the context must have been at least initialized. + */ +void mbedtls_aes_xts_free(mbedtls_aes_xts_context *ctx); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/** + * \brief This function sets the encryption key. + * + * \param ctx The AES context to which the key should be bound. + * It must be initialized. + * \param key The encryption key. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of data passed in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_setkey_enc(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function sets the decryption key. + * + * \param ctx The AES context to which the key should be bound. + * It must be initialized. + * \param key The decryption key. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of data passed. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_setkey_dec(mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits); + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function prepares an XTS context for encryption and + * sets the encryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * It must be initialized. + * \param key The encryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_xts_setkey_enc(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function prepares an XTS context for decryption and + * sets the decryption key. + * + * \param ctx The AES XTS context to which the key should be bound. + * It must be initialized. + * \param key The decryption key. This is comprised of the XTS key1 + * concatenated with the XTS key2. + * This must be a readable buffer of size \p keybits bits. + * \param keybits The size of \p key passed in bits. Valid options are: + *
  • 256 bits (each of key1 and key2 is a 128-bit key)
    • + *
  • 512 bits (each of key1 and key2 is a 256-bit key)
+ * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_xts_setkey_dec(mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/** + * \brief This function performs an AES single-block encryption or + * decryption operation. + * + * It performs the operation defined in the \p mode parameter + * (encrypt or decrypt), on the input data buffer defined in + * the \p input parameter. + * + * mbedtls_aes_init(), and either mbedtls_aes_setkey_enc() or + * mbedtls_aes_setkey_dec() must be called before the first + * call to this API with the same context. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param input The buffer holding the input data. + * It must be readable and at least \c 16 Bytes long. + * \param output The buffer where the output data will be written. + * It must be writeable and at least \c 16 Bytes long. + + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_ecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief This function performs an AES-CBC encryption or decryption operation + * on full blocks. + * + * It performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer defined in + * the \p input parameter. + * + * It can be called as many times as needed, until all the input + * data is processed. mbedtls_aes_init(), and either + * mbedtls_aes_setkey_enc() or mbedtls_aes_setkey_dec() must be called + * before the first call to this API with the same context. + * + * \note This function operates on full blocks, that is, the input size + * must be a multiple of the AES block size of \c 16 Bytes. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the IV, you should + * either save it manually or use the cipher module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of the input data in Bytes. This must be a + * multiple of the block size (\c 16 Bytes). + * \param iv Initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH + * on failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_cbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +/** + * \brief This function performs an AES-XTS encryption or decryption + * operation for an entire XTS data unit. + * + * AES-XTS encrypts or decrypts blocks based on their location as + * defined by a data unit number. The data unit number must be + * provided by \p data_unit. + * + * NIST SP 800-38E limits the maximum size of a data unit to 2^20 + * AES blocks. If the data unit is larger than this, this function + * returns #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH. + * + * \param ctx The AES XTS context to use for AES XTS operations. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of a data unit in Bytes. This can be any + * length between 16 bytes and 2^24 bytes inclusive + * (between 1 and 2^20 block cipher blocks). + * \param data_unit The address of the data unit encoded as an array of 16 + * bytes in little-endian format. For disk encryption, this + * is typically the index of the block device sector that + * contains the data. + * \param input The buffer holding the input data (which is an entire + * data unit). This function reads \p length Bytes from \p + * input. + * \param output The buffer holding the output data (which is an entire + * data unit). This function writes \p length Bytes to \p + * output. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH if \p length is + * smaller than an AES block in size (16 Bytes) or if \p + * length is larger than 2^20 blocks (16 MiB). + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_xts(mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief This function performs an AES-CFB128 encryption or decryption + * operation. + * + * It performs the operation defined in the \p mode + * parameter (encrypt or decrypt), on the input data buffer + * defined in the \p input parameter. + * + * For CFB, you must set up the context with mbedtls_aes_setkey_enc(), + * regardless of whether you are performing an encryption or decryption + * operation, that is, regardless of the \p mode parameter. This is + * because CFB mode uses the same key schedule for encryption and + * decryption. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the + * IV, you must either save it manually or use the cipher + * module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT. + * \param length The length of the input data in Bytes. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_cfb128(mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function performs an AES-CFB8 encryption or decryption + * operation. + * + * It performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer defined + * in the \p input parameter. + * + * Due to the nature of CFB, you must use the same key schedule for + * both encryption and decryption operations. Therefore, you must + * use the context initialized with mbedtls_aes_setkey_enc() for + * both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param mode The AES operation: #MBEDTLS_AES_ENCRYPT or + * #MBEDTLS_AES_DECRYPT + * \param length The length of the input data. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_cfb8(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/** + * \brief This function performs an AES-OFB (Output Feedback Mode) + * encryption or decryption operation. + * + * For OFB, you must set up the context with + * mbedtls_aes_setkey_enc(), regardless of whether you are + * performing an encryption or decryption operation. This is + * because OFB mode uses the same key schedule for encryption and + * decryption. + * + * The OFB operation is identical for encryption or decryption, + * therefore no operation mode needs to be specified. + * + * \note Upon exit, the content of iv, the Initialisation Vector, is + * updated so that you can call the same function again on the next + * block(s) of data and get the same result as if it was encrypted + * in one call. This allows a "streaming" usage, by initialising + * iv_off to 0 before the first call, and preserving its value + * between calls. + * + * For non-streaming use, the iv should be initialised on each call + * to a unique value, and iv_off set to 0 on each call. + * + * If you need to retain the contents of the initialisation vector, + * you must either save it manually or use the cipher module + * instead. + * + * \warning For the OFB mode, the initialisation vector must be unique + * every encryption operation. Reuse of an initialisation vector + * will compromise security. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param iv_off The offset in IV (updated after use). + * It must point to a valid \c size_t. + * \param iv The initialization vector (updated after use). + * It must be a readable and writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_ofb(mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief This function performs an AES-CTR encryption or decryption + * operation. + * + * Due to the nature of CTR, you must use the same key schedule + * for both encryption and decryption operations. Therefore, you + * must use the context initialized with mbedtls_aes_setkey_enc() + * for both #MBEDTLS_AES_ENCRYPT and #MBEDTLS_AES_DECRYPT. + * + * \warning You must never reuse a nonce value with the same key. Doing so + * would void the encryption for the two messages encrypted with + * the same nonce and key. + * + * There are two common strategies for managing nonces with CTR: + * + * 1. You can handle everything as a single message processed over + * successive calls to this function. In that case, you want to + * set \p nonce_counter and \p nc_off to 0 for the first call, and + * then preserve the values of \p nonce_counter, \p nc_off and \p + * stream_block across calls to this function as they will be + * updated by this function. + * + * With this strategy, you must not encrypt more than 2**128 + * blocks of data with the same key. + * + * 2. You can encrypt separate messages by dividing the \p + * nonce_counter buffer in two areas: the first one used for a + * per-message nonce, handled by yourself, and the second one + * updated by this function internally. + * + * For example, you might reserve the first 12 bytes for the + * per-message nonce, and the last 4 bytes for internal use. In that + * case, before calling this function on a new message you need to + * set the first 12 bytes of \p nonce_counter to your chosen nonce + * value, the last 4 to 0, and \p nc_off to 0 (which will cause \p + * stream_block to be ignored). That way, you can encrypt at most + * 2**96 messages of up to 2**32 blocks each with the same key. + * + * The per-message nonce (or information sufficient to reconstruct + * it) needs to be communicated with the ciphertext and must be unique. + * The recommended way to ensure uniqueness is to use a message + * counter. An alternative is to generate random nonces, but this + * limits the number of messages that can be securely encrypted: + * for example, with 96-bit random nonces, you should not encrypt + * more than 2**32 messages with the same key. + * + * Note that for both strategies, sizes are measured in blocks and + * that an AES block is 16 bytes. + * + * \warning Upon return, \p stream_block contains sensitive data. Its + * content must not be written to insecure storage and should be + * securely discarded as soon as it's no longer needed. + * + * \param ctx The AES context to use for encryption or decryption. + * It must be initialized and bound to a key. + * \param length The length of the input data. + * \param nc_off The offset in the current \p stream_block, for + * resuming within the current cipher stream. The + * offset pointer should be 0 at the start of a stream. + * It must point to a valid \c size_t. + * \param nonce_counter The 128-bit nonce and counter. + * It must be a readable-writeable buffer of \c 16 Bytes. + * \param stream_block The saved stream block for resuming. This is + * overwritten by the function. + * It must be a readable-writeable buffer of \c 16 Bytes. + * \param input The buffer holding the input data. + * It must be readable and of size \p length Bytes. + * \param output The buffer holding the output data. + * It must be writeable and of size \p length Bytes. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_aes_crypt_ctr(mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +/** + * \brief Internal AES block encryption function. This is only + * exposed to allow overriding it using + * \c MBEDTLS_AES_ENCRYPT_ALT. + * + * \param ctx The AES context to use for encryption. + * \param input The plaintext block. + * \param output The output (ciphertext) block. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_internal_aes_encrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); + +/** + * \brief Internal AES block decryption function. This is only + * exposed to allow overriding it using see + * \c MBEDTLS_AES_DECRYPT_ALT. + * + * \param ctx The AES context to use for decryption. + * \param input The ciphertext block. + * \param output The output (plaintext) block. + * + * \return \c 0 on success. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_internal_aes_decrypt(mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16]); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_aes_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* aes.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aria.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aria.h index 7e55df7..ff5ee4c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aria.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/aria.h @@ -1,353 +1,353 @@ -/** - * \file aria.h - * - * \brief ARIA block cipher - * - * The ARIA algorithm is a symmetric block cipher that can encrypt and - * decrypt information. It is defined by the Korean Agency for - * Technology and Standards (KATS) in KS X 1213:2004 (in - * Korean, but see http://210.104.33.10/ARIA/index-e.html in English) - * and also described by the IETF in RFC 5794. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_ARIA_H -#define MBEDTLS_ARIA_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#include "mbedtls/platform_util.h" - -#define MBEDTLS_ARIA_ENCRYPT 1 /**< ARIA encryption. */ -#define MBEDTLS_ARIA_DECRYPT 0 /**< ARIA decryption. */ - -#define MBEDTLS_ARIA_BLOCKSIZE 16 /**< ARIA block size in bytes. */ -#define MBEDTLS_ARIA_MAX_ROUNDS 16 /**< Maximum number of rounds in ARIA. */ -#define MBEDTLS_ARIA_MAX_KEYSIZE 32 /**< Maximum size of an ARIA key in bytes. */ - -/** Bad input data. */ -#define MBEDTLS_ERR_ARIA_BAD_INPUT_DATA -0x005C - -/** Invalid data input length. */ -#define MBEDTLS_ERR_ARIA_INVALID_INPUT_LENGTH -0x005E - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_ARIA_ALT) -// Regular implementation -// - -/** - * \brief The ARIA context-type definition. - */ -typedef struct mbedtls_aria_context { - unsigned char MBEDTLS_PRIVATE(nr); /*!< The number of rounds (12, 14 or 16) */ - /*! The ARIA round keys. */ - uint32_t MBEDTLS_PRIVATE(rk)[MBEDTLS_ARIA_MAX_ROUNDS + 1][MBEDTLS_ARIA_BLOCKSIZE / 4]; -} -mbedtls_aria_context; - -#else /* MBEDTLS_ARIA_ALT */ -#include "aria_alt.h" -#endif /* MBEDTLS_ARIA_ALT */ - -/** - * \brief This function initializes the specified ARIA context. - * - * It must be the first API called before using - * the context. - * - * \param ctx The ARIA context to initialize. This must not be \c NULL. - */ -void mbedtls_aria_init(mbedtls_aria_context *ctx); - -/** - * \brief This function releases and clears the specified ARIA context. - * - * \param ctx The ARIA context to clear. This may be \c NULL, in which - * case this function returns immediately. If it is not \c NULL, - * it must point to an initialized ARIA context. - */ -void mbedtls_aria_free(mbedtls_aria_context *ctx); - -/** - * \brief This function sets the encryption key. - * - * \param ctx The ARIA context to which the key should be bound. - * This must be initialized. - * \param key The encryption key. This must be a readable buffer - * of size \p keybits Bits. - * \param keybits The size of \p key in Bits. Valid options are: - *
  • 128 bits
    • - *
  • 192 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_setkey_enc(mbedtls_aria_context *ctx, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function sets the decryption key. - * - * \param ctx The ARIA context to which the key should be bound. - * This must be initialized. - * \param key The decryption key. This must be a readable buffer - * of size \p keybits Bits. - * \param keybits The size of data passed. Valid options are: - *
  • 128 bits
    • - *
  • 192 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_setkey_dec(mbedtls_aria_context *ctx, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function performs an ARIA single-block encryption or - * decryption operation. - * - * It performs encryption or decryption (depending on whether - * the key was set for encryption on decryption) on the input - * data buffer defined in the \p input parameter. - * - * mbedtls_aria_init(), and either mbedtls_aria_setkey_enc() or - * mbedtls_aria_setkey_dec() must be called before the first - * call to this API with the same context. - * - * \param ctx The ARIA context to use for encryption or decryption. - * This must be initialized and bound to a key. - * \param input The 16-Byte buffer holding the input data. - * \param output The 16-Byte buffer holding the output data. - - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_crypt_ecb(mbedtls_aria_context *ctx, - const unsigned char input[MBEDTLS_ARIA_BLOCKSIZE], - unsigned char output[MBEDTLS_ARIA_BLOCKSIZE]); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief This function performs an ARIA-CBC encryption or decryption operation - * on full blocks. - * - * It performs the operation defined in the \p mode - * parameter (encrypt/decrypt), on the input data buffer defined in - * the \p input parameter. - * - * It can be called as many times as needed, until all the input - * data is processed. mbedtls_aria_init(), and either - * mbedtls_aria_setkey_enc() or mbedtls_aria_setkey_dec() must be called - * before the first call to this API with the same context. - * - * \note This function operates on aligned blocks, that is, the input size - * must be a multiple of the ARIA block size of 16 Bytes. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the same function again on the next - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If you need to retain the contents of the IV, you should - * either save it manually or use the cipher module instead. - * - * - * \param ctx The ARIA context to use for encryption or decryption. - * This must be initialized and bound to a key. - * \param mode The mode of operation. This must be either - * #MBEDTLS_ARIA_ENCRYPT for encryption, or - * #MBEDTLS_ARIA_DECRYPT for decryption. - * \param length The length of the input data in Bytes. This must be a - * multiple of the block size (16 Bytes). - * \param iv Initialization vector (updated after use). - * This must be a readable buffer of size 16 Bytes. - * \param input The buffer holding the input data. This must - * be a readable buffer of length \p length Bytes. - * \param output The buffer holding the output data. This must - * be a writable buffer of length \p length Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_crypt_cbc(mbedtls_aria_context *ctx, - int mode, - size_t length, - unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -/** - * \brief This function performs an ARIA-CFB128 encryption or decryption - * operation. - * - * It performs the operation defined in the \p mode - * parameter (encrypt or decrypt), on the input data buffer - * defined in the \p input parameter. - * - * For CFB, you must set up the context with mbedtls_aria_setkey_enc(), - * regardless of whether you are performing an encryption or decryption - * operation, that is, regardless of the \p mode parameter. This is - * because CFB mode uses the same key schedule for encryption and - * decryption. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the same function again on the next - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If you need to retain the contents of the - * IV, you must either save it manually or use the cipher - * module instead. - * - * - * \param ctx The ARIA context to use for encryption or decryption. - * This must be initialized and bound to a key. - * \param mode The mode of operation. This must be either - * #MBEDTLS_ARIA_ENCRYPT for encryption, or - * #MBEDTLS_ARIA_DECRYPT for decryption. - * \param length The length of the input data \p input in Bytes. - * \param iv_off The offset in IV (updated after use). - * This must not be larger than 15. - * \param iv The initialization vector (updated after use). - * This must be a readable buffer of size 16 Bytes. - * \param input The buffer holding the input data. This must - * be a readable buffer of length \p length Bytes. - * \param output The buffer holding the output data. This must - * be a writable buffer of length \p length Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_crypt_cfb128(mbedtls_aria_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -/** - * \brief This function performs an ARIA-CTR encryption or decryption - * operation. - * - * Due to the nature of CTR, you must use the same key schedule - * for both encryption and decryption operations. Therefore, you - * must use the context initialized with mbedtls_aria_setkey_enc() - * for both #MBEDTLS_ARIA_ENCRYPT and #MBEDTLS_ARIA_DECRYPT. - * - * \warning You must never reuse a nonce value with the same key. Doing so - * would void the encryption for the two messages encrypted with - * the same nonce and key. - * - * There are two common strategies for managing nonces with CTR: - * - * 1. You can handle everything as a single message processed over - * successive calls to this function. In that case, you want to - * set \p nonce_counter and \p nc_off to 0 for the first call, and - * then preserve the values of \p nonce_counter, \p nc_off and \p - * stream_block across calls to this function as they will be - * updated by this function. - * - * With this strategy, you must not encrypt more than 2**128 - * blocks of data with the same key. - * - * 2. You can encrypt separate messages by dividing the \p - * nonce_counter buffer in two areas: the first one used for a - * per-message nonce, handled by yourself, and the second one - * updated by this function internally. - * - * For example, you might reserve the first 12 bytes for the - * per-message nonce, and the last 4 bytes for internal use. In that - * case, before calling this function on a new message you need to - * set the first 12 bytes of \p nonce_counter to your chosen nonce - * value, the last 4 to 0, and \p nc_off to 0 (which will cause \p - * stream_block to be ignored). That way, you can encrypt at most - * 2**96 messages of up to 2**32 blocks each with the same key. - * - * The per-message nonce (or information sufficient to reconstruct - * it) needs to be communicated with the ciphertext and must be unique. - * The recommended way to ensure uniqueness is to use a message - * counter. An alternative is to generate random nonces, but this - * limits the number of messages that can be securely encrypted: - * for example, with 96-bit random nonces, you should not encrypt - * more than 2**32 messages with the same key. - * - * Note that for both strategies, sizes are measured in blocks and - * that an ARIA block is 16 bytes. - * - * \warning Upon return, \p stream_block contains sensitive data. Its - * content must not be written to insecure storage and should be - * securely discarded as soon as it's no longer needed. - * - * \param ctx The ARIA context to use for encryption or decryption. - * This must be initialized and bound to a key. - * \param length The length of the input data \p input in Bytes. - * \param nc_off The offset in Bytes in the current \p stream_block, - * for resuming within the current cipher stream. The - * offset pointer should be \c 0 at the start of a - * stream. This must not be larger than \c 15 Bytes. - * \param nonce_counter The 128-bit nonce and counter. This must point to - * a read/write buffer of length \c 16 bytes. - * \param stream_block The saved stream block for resuming. This must - * point to a read/write buffer of length \c 16 bytes. - * This is overwritten by the function. - * \param input The buffer holding the input data. This must - * be a readable buffer of length \p length Bytes. - * \param output The buffer holding the output data. This must - * be a writable buffer of length \p length Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_aria_crypt_ctr(mbedtls_aria_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[MBEDTLS_ARIA_BLOCKSIZE], - unsigned char stream_block[MBEDTLS_ARIA_BLOCKSIZE], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine. - * - * \return \c 0 on success, or \c 1 on failure. - */ -int mbedtls_aria_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* aria.h */ +/** + * \file aria.h + * + * \brief ARIA block cipher + * + * The ARIA algorithm is a symmetric block cipher that can encrypt and + * decrypt information. It is defined by the Korean Agency for + * Technology and Standards (KATS) in KS X 1213:2004 (in + * Korean, but see http://210.104.33.10/ARIA/index-e.html in English) + * and also described by the IETF in RFC 5794. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_ARIA_H +#define MBEDTLS_ARIA_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#include "mbedtls/platform_util.h" + +#define MBEDTLS_ARIA_ENCRYPT 1 /**< ARIA encryption. */ +#define MBEDTLS_ARIA_DECRYPT 0 /**< ARIA decryption. */ + +#define MBEDTLS_ARIA_BLOCKSIZE 16 /**< ARIA block size in bytes. */ +#define MBEDTLS_ARIA_MAX_ROUNDS 16 /**< Maximum number of rounds in ARIA. */ +#define MBEDTLS_ARIA_MAX_KEYSIZE 32 /**< Maximum size of an ARIA key in bytes. */ + +/** Bad input data. */ +#define MBEDTLS_ERR_ARIA_BAD_INPUT_DATA -0x005C + +/** Invalid data input length. */ +#define MBEDTLS_ERR_ARIA_INVALID_INPUT_LENGTH -0x005E + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_ARIA_ALT) +// Regular implementation +// + +/** + * \brief The ARIA context-type definition. + */ +typedef struct mbedtls_aria_context { + unsigned char MBEDTLS_PRIVATE(nr); /*!< The number of rounds (12, 14 or 16) */ + /*! The ARIA round keys. */ + uint32_t MBEDTLS_PRIVATE(rk)[MBEDTLS_ARIA_MAX_ROUNDS + 1][MBEDTLS_ARIA_BLOCKSIZE / 4]; +} +mbedtls_aria_context; + +#else /* MBEDTLS_ARIA_ALT */ +#include "aria_alt.h" +#endif /* MBEDTLS_ARIA_ALT */ + +/** + * \brief This function initializes the specified ARIA context. + * + * It must be the first API called before using + * the context. + * + * \param ctx The ARIA context to initialize. This must not be \c NULL. + */ +void mbedtls_aria_init(mbedtls_aria_context *ctx); + +/** + * \brief This function releases and clears the specified ARIA context. + * + * \param ctx The ARIA context to clear. This may be \c NULL, in which + * case this function returns immediately. If it is not \c NULL, + * it must point to an initialized ARIA context. + */ +void mbedtls_aria_free(mbedtls_aria_context *ctx); + +/** + * \brief This function sets the encryption key. + * + * \param ctx The ARIA context to which the key should be bound. + * This must be initialized. + * \param key The encryption key. This must be a readable buffer + * of size \p keybits Bits. + * \param keybits The size of \p key in Bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_setkey_enc(mbedtls_aria_context *ctx, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function sets the decryption key. + * + * \param ctx The ARIA context to which the key should be bound. + * This must be initialized. + * \param key The decryption key. This must be a readable buffer + * of size \p keybits Bits. + * \param keybits The size of data passed. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_setkey_dec(mbedtls_aria_context *ctx, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function performs an ARIA single-block encryption or + * decryption operation. + * + * It performs encryption or decryption (depending on whether + * the key was set for encryption on decryption) on the input + * data buffer defined in the \p input parameter. + * + * mbedtls_aria_init(), and either mbedtls_aria_setkey_enc() or + * mbedtls_aria_setkey_dec() must be called before the first + * call to this API with the same context. + * + * \param ctx The ARIA context to use for encryption or decryption. + * This must be initialized and bound to a key. + * \param input The 16-Byte buffer holding the input data. + * \param output The 16-Byte buffer holding the output data. + + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_crypt_ecb(mbedtls_aria_context *ctx, + const unsigned char input[MBEDTLS_ARIA_BLOCKSIZE], + unsigned char output[MBEDTLS_ARIA_BLOCKSIZE]); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief This function performs an ARIA-CBC encryption or decryption operation + * on full blocks. + * + * It performs the operation defined in the \p mode + * parameter (encrypt/decrypt), on the input data buffer defined in + * the \p input parameter. + * + * It can be called as many times as needed, until all the input + * data is processed. mbedtls_aria_init(), and either + * mbedtls_aria_setkey_enc() or mbedtls_aria_setkey_dec() must be called + * before the first call to this API with the same context. + * + * \note This function operates on aligned blocks, that is, the input size + * must be a multiple of the ARIA block size of 16 Bytes. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the IV, you should + * either save it manually or use the cipher module instead. + * + * + * \param ctx The ARIA context to use for encryption or decryption. + * This must be initialized and bound to a key. + * \param mode The mode of operation. This must be either + * #MBEDTLS_ARIA_ENCRYPT for encryption, or + * #MBEDTLS_ARIA_DECRYPT for decryption. + * \param length The length of the input data in Bytes. This must be a + * multiple of the block size (16 Bytes). + * \param iv Initialization vector (updated after use). + * This must be a readable buffer of size 16 Bytes. + * \param input The buffer holding the input data. This must + * be a readable buffer of length \p length Bytes. + * \param output The buffer holding the output data. This must + * be a writable buffer of length \p length Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_crypt_cbc(mbedtls_aria_context *ctx, + int mode, + size_t length, + unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief This function performs an ARIA-CFB128 encryption or decryption + * operation. + * + * It performs the operation defined in the \p mode + * parameter (encrypt or decrypt), on the input data buffer + * defined in the \p input parameter. + * + * For CFB, you must set up the context with mbedtls_aria_setkey_enc(), + * regardless of whether you are performing an encryption or decryption + * operation, that is, regardless of the \p mode parameter. This is + * because CFB mode uses the same key schedule for encryption and + * decryption. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the next + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If you need to retain the contents of the + * IV, you must either save it manually or use the cipher + * module instead. + * + * + * \param ctx The ARIA context to use for encryption or decryption. + * This must be initialized and bound to a key. + * \param mode The mode of operation. This must be either + * #MBEDTLS_ARIA_ENCRYPT for encryption, or + * #MBEDTLS_ARIA_DECRYPT for decryption. + * \param length The length of the input data \p input in Bytes. + * \param iv_off The offset in IV (updated after use). + * This must not be larger than 15. + * \param iv The initialization vector (updated after use). + * This must be a readable buffer of size 16 Bytes. + * \param input The buffer holding the input data. This must + * be a readable buffer of length \p length Bytes. + * \param output The buffer holding the output data. This must + * be a writable buffer of length \p length Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_crypt_cfb128(mbedtls_aria_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[MBEDTLS_ARIA_BLOCKSIZE], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief This function performs an ARIA-CTR encryption or decryption + * operation. + * + * Due to the nature of CTR, you must use the same key schedule + * for both encryption and decryption operations. Therefore, you + * must use the context initialized with mbedtls_aria_setkey_enc() + * for both #MBEDTLS_ARIA_ENCRYPT and #MBEDTLS_ARIA_DECRYPT. + * + * \warning You must never reuse a nonce value with the same key. Doing so + * would void the encryption for the two messages encrypted with + * the same nonce and key. + * + * There are two common strategies for managing nonces with CTR: + * + * 1. You can handle everything as a single message processed over + * successive calls to this function. In that case, you want to + * set \p nonce_counter and \p nc_off to 0 for the first call, and + * then preserve the values of \p nonce_counter, \p nc_off and \p + * stream_block across calls to this function as they will be + * updated by this function. + * + * With this strategy, you must not encrypt more than 2**128 + * blocks of data with the same key. + * + * 2. You can encrypt separate messages by dividing the \p + * nonce_counter buffer in two areas: the first one used for a + * per-message nonce, handled by yourself, and the second one + * updated by this function internally. + * + * For example, you might reserve the first 12 bytes for the + * per-message nonce, and the last 4 bytes for internal use. In that + * case, before calling this function on a new message you need to + * set the first 12 bytes of \p nonce_counter to your chosen nonce + * value, the last 4 to 0, and \p nc_off to 0 (which will cause \p + * stream_block to be ignored). That way, you can encrypt at most + * 2**96 messages of up to 2**32 blocks each with the same key. + * + * The per-message nonce (or information sufficient to reconstruct + * it) needs to be communicated with the ciphertext and must be unique. + * The recommended way to ensure uniqueness is to use a message + * counter. An alternative is to generate random nonces, but this + * limits the number of messages that can be securely encrypted: + * for example, with 96-bit random nonces, you should not encrypt + * more than 2**32 messages with the same key. + * + * Note that for both strategies, sizes are measured in blocks and + * that an ARIA block is 16 bytes. + * + * \warning Upon return, \p stream_block contains sensitive data. Its + * content must not be written to insecure storage and should be + * securely discarded as soon as it's no longer needed. + * + * \param ctx The ARIA context to use for encryption or decryption. + * This must be initialized and bound to a key. + * \param length The length of the input data \p input in Bytes. + * \param nc_off The offset in Bytes in the current \p stream_block, + * for resuming within the current cipher stream. The + * offset pointer should be \c 0 at the start of a + * stream. This must not be larger than \c 15 Bytes. + * \param nonce_counter The 128-bit nonce and counter. This must point to + * a read/write buffer of length \c 16 bytes. + * \param stream_block The saved stream block for resuming. This must + * point to a read/write buffer of length \c 16 bytes. + * This is overwritten by the function. + * \param input The buffer holding the input data. This must + * be a readable buffer of length \p length Bytes. + * \param output The buffer holding the output data. This must + * be a writable buffer of length \p length Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_aria_crypt_ctr(mbedtls_aria_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[MBEDTLS_ARIA_BLOCKSIZE], + unsigned char stream_block[MBEDTLS_ARIA_BLOCKSIZE], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine. + * + * \return \c 0 on success, or \c 1 on failure. + */ +int mbedtls_aria_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* aria.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1.h index c7aae0f..d95c232 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1.h @@ -1,653 +1,653 @@ -/** - * \file asn1.h - * - * \brief Generic ASN.1 parsing - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ASN1_H -#define MBEDTLS_ASN1_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" -#include "mbedtls/platform_util.h" - -#include - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -/** - * \addtogroup asn1_module - * \{ - */ - -/** - * \name ASN1 Error codes - * These error codes are combined with other error codes for - * higher error granularity. - * e.g. X.509 and PKCS #7 error codes - * ASN1 is a standard to specify data structures. - * \{ - */ -/** Out of data when parsing an ASN1 data structure. */ -#define MBEDTLS_ERR_ASN1_OUT_OF_DATA -0x0060 -/** ASN1 tag was of an unexpected value. */ -#define MBEDTLS_ERR_ASN1_UNEXPECTED_TAG -0x0062 -/** Error when trying to determine the length or invalid length. */ -#define MBEDTLS_ERR_ASN1_INVALID_LENGTH -0x0064 -/** Actual length differs from expected length. */ -#define MBEDTLS_ERR_ASN1_LENGTH_MISMATCH -0x0066 -/** Data is invalid. */ -#define MBEDTLS_ERR_ASN1_INVALID_DATA -0x0068 -/** Memory allocation failed */ -#define MBEDTLS_ERR_ASN1_ALLOC_FAILED -0x006A -/** Buffer too small when writing ASN.1 data structure. */ -#define MBEDTLS_ERR_ASN1_BUF_TOO_SMALL -0x006C - -/** \} name ASN1 Error codes */ - -/** - * \name DER constants - * These constants comply with the DER encoded ASN.1 type tags. - * DER encoding uses hexadecimal representation. - * An example DER sequence is:\n - * - 0x02 -- tag indicating INTEGER - * - 0x01 -- length in octets - * - 0x05 -- value - * Such sequences are typically read into \c ::mbedtls_x509_buf. - * \{ - */ -#define MBEDTLS_ASN1_BOOLEAN 0x01 -#define MBEDTLS_ASN1_INTEGER 0x02 -#define MBEDTLS_ASN1_BIT_STRING 0x03 -#define MBEDTLS_ASN1_OCTET_STRING 0x04 -#define MBEDTLS_ASN1_NULL 0x05 -#define MBEDTLS_ASN1_OID 0x06 -#define MBEDTLS_ASN1_ENUMERATED 0x0A -#define MBEDTLS_ASN1_UTF8_STRING 0x0C -#define MBEDTLS_ASN1_SEQUENCE 0x10 -#define MBEDTLS_ASN1_SET 0x11 -#define MBEDTLS_ASN1_PRINTABLE_STRING 0x13 -#define MBEDTLS_ASN1_T61_STRING 0x14 -#define MBEDTLS_ASN1_IA5_STRING 0x16 -#define MBEDTLS_ASN1_UTC_TIME 0x17 -#define MBEDTLS_ASN1_GENERALIZED_TIME 0x18 -#define MBEDTLS_ASN1_UNIVERSAL_STRING 0x1C -#define MBEDTLS_ASN1_BMP_STRING 0x1E -#define MBEDTLS_ASN1_PRIMITIVE 0x00 -#define MBEDTLS_ASN1_CONSTRUCTED 0x20 -#define MBEDTLS_ASN1_CONTEXT_SPECIFIC 0x80 - -/* Slightly smaller way to check if tag is a string tag - * compared to canonical implementation. */ -#define MBEDTLS_ASN1_IS_STRING_TAG(tag) \ - ((unsigned int) (tag) < 32u && ( \ - ((1u << (tag)) & ((1u << MBEDTLS_ASN1_BMP_STRING) | \ - (1u << MBEDTLS_ASN1_UTF8_STRING) | \ - (1u << MBEDTLS_ASN1_T61_STRING) | \ - (1u << MBEDTLS_ASN1_IA5_STRING) | \ - (1u << MBEDTLS_ASN1_UNIVERSAL_STRING) | \ - (1u << MBEDTLS_ASN1_PRINTABLE_STRING))) != 0)) - -/* - * Bit masks for each of the components of an ASN.1 tag as specified in - * ITU X.690 (08/2015), section 8.1 "General rules for encoding", - * paragraph 8.1.2.2: - * - * Bit 8 7 6 5 1 - * +-------+-----+------------+ - * | Class | P/C | Tag number | - * +-------+-----+------------+ - */ -#define MBEDTLS_ASN1_TAG_CLASS_MASK 0xC0 -#define MBEDTLS_ASN1_TAG_PC_MASK 0x20 -#define MBEDTLS_ASN1_TAG_VALUE_MASK 0x1F - -/** \} name DER constants */ - -/** Returns the size of the binary string, without the trailing \\0 */ -#define MBEDTLS_OID_SIZE(x) (sizeof(x) - 1) - -/** - * Compares an mbedtls_asn1_buf structure to a reference OID. - * - * Only works for 'defined' oid_str values (MBEDTLS_OID_HMAC_SHA1), you cannot use a - * 'unsigned char *oid' here! - */ -#define MBEDTLS_OID_CMP(oid_str, oid_buf) \ - ((MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len) || \ - memcmp((oid_str), (oid_buf)->p, (oid_buf)->len) != 0) - -#define MBEDTLS_OID_CMP_RAW(oid_str, oid_buf, oid_buf_len) \ - ((MBEDTLS_OID_SIZE(oid_str) != (oid_buf_len)) || \ - memcmp((oid_str), (oid_buf), (oid_buf_len)) != 0) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Functions to parse ASN.1 data structures - * \{ - */ - -/** - * Type-length-value structure that allows for ASN1 using DER. - */ -typedef struct mbedtls_asn1_buf { - int tag; /**< ASN1 type, e.g. MBEDTLS_ASN1_UTF8_STRING. */ - size_t len; /**< ASN1 length, in octets. */ - unsigned char *p; /**< ASN1 data, e.g. in ASCII. */ -} -mbedtls_asn1_buf; - -/** - * Container for ASN1 bit strings. - */ -typedef struct mbedtls_asn1_bitstring { - size_t len; /**< ASN1 length, in octets. */ - unsigned char unused_bits; /**< Number of unused bits at the end of the string */ - unsigned char *p; /**< Raw ASN1 data for the bit string */ -} -mbedtls_asn1_bitstring; - -/** - * Container for a sequence of ASN.1 items - */ -typedef struct mbedtls_asn1_sequence { - mbedtls_asn1_buf buf; /**< Buffer containing the given ASN.1 item. */ - - /** The next entry in the sequence. - * - * The details of memory management for sequences are not documented and - * may change in future versions. Set this field to \p NULL when - * initializing a structure, and do not modify it except via Mbed TLS - * library functions. - */ - struct mbedtls_asn1_sequence *next; -} -mbedtls_asn1_sequence; - -/** - * Container for a sequence or list of 'named' ASN.1 data items - */ -typedef struct mbedtls_asn1_named_data { - mbedtls_asn1_buf oid; /**< The object identifier. */ - mbedtls_asn1_buf val; /**< The named value. */ - - /** The next entry in the sequence. - * - * The details of memory management for named data sequences are not - * documented and may change in future versions. Set this field to \p NULL - * when initializing a structure, and do not modify it except via Mbed TLS - * library functions. - */ - struct mbedtls_asn1_named_data *next; - - /** Merge next item into the current one? - * - * This field exists for the sake of Mbed TLS's X.509 certificate parsing - * code and may change in future versions of the library. - */ - unsigned char MBEDTLS_PRIVATE(next_merged); -} -mbedtls_asn1_named_data; - -#if defined(MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_X509_CREATE_C) -/** - * \brief Get the length of an ASN.1 element. - * Updates the pointer to immediately behind the length. - * - * \param p On entry, \c *p points to the first byte of the length, - * i.e. immediately after the tag. - * On successful completion, \c *p points to the first byte - * after the length, i.e. the first byte of the content. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param len On successful completion, \c *len contains the length - * read from the ASN.1 input. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_ASN1_OUT_OF_DATA if the ASN.1 element - * would end beyond \p end. - * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the length is unparsable. - */ -int mbedtls_asn1_get_len(unsigned char **p, - const unsigned char *end, - size_t *len); - -/** - * \brief Get the tag and length of the element. - * Check for the requested tag. - * Updates the pointer to immediately behind the tag and length. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * after the length, i.e. the first byte of the content. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param len On successful completion, \c *len contains the length - * read from the ASN.1 input. - * \param tag The expected tag. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the data does not start - * with the requested tag. - * \return #MBEDTLS_ERR_ASN1_OUT_OF_DATA if the ASN.1 element - * would end beyond \p end. - * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the length is unparsable. - */ -int mbedtls_asn1_get_tag(unsigned char **p, - const unsigned char *end, - size_t *len, int tag); -#endif /* MBEDTLS_ASN1_PARSE_C || MBEDTLS_X509_CREATE_C */ - -#if defined(MBEDTLS_ASN1_PARSE_C) -/** - * \brief Retrieve a boolean ASN.1 tag and its value. - * Updates the pointer to immediately behind the full tag. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the ASN.1 element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param val On success, the parsed value (\c 0 or \c 1). - * - * \return 0 if successful. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 BOOLEAN. - */ -int mbedtls_asn1_get_bool(unsigned char **p, - const unsigned char *end, - int *val); - -/** - * \brief Retrieve an integer ASN.1 tag and its value. - * Updates the pointer to immediately behind the full tag. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the ASN.1 element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param val On success, the parsed value. - * - * \return 0 if successful. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 INTEGER. - * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does - * not fit in an \c int. - */ -int mbedtls_asn1_get_int(unsigned char **p, - const unsigned char *end, - int *val); - -/** - * \brief Retrieve an enumerated ASN.1 tag and its value. - * Updates the pointer to immediately behind the full tag. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the ASN.1 element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param val On success, the parsed value. - * - * \return 0 if successful. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 ENUMERATED. - * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does - * not fit in an \c int. - */ -int mbedtls_asn1_get_enum(unsigned char **p, - const unsigned char *end, - int *val); - -/** - * \brief Retrieve a bitstring ASN.1 tag and its value. - * Updates the pointer to immediately behind the full tag. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p is equal to \p end. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param bs On success, ::mbedtls_asn1_bitstring information about - * the parsed value. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input contains - * extra data after a valid BIT STRING. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 BIT STRING. - */ -int mbedtls_asn1_get_bitstring(unsigned char **p, const unsigned char *end, - mbedtls_asn1_bitstring *bs); - -/** - * \brief Retrieve a bitstring ASN.1 tag without unused bits and its - * value. - * Updates the pointer to the beginning of the bit/octet string. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * of the content of the BIT STRING. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param len On success, \c *len is the length of the content in bytes. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if the input starts with - * a valid BIT STRING with a nonzero number of unused bits. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 BIT STRING. - */ -int mbedtls_asn1_get_bitstring_null(unsigned char **p, - const unsigned char *end, - size_t *len); - -/** - * \brief Parses and splits an ASN.1 "SEQUENCE OF ". - * Updates the pointer to immediately behind the full sequence tag. - * - * This function allocates memory for the sequence elements. You can free - * the allocated memory with mbedtls_asn1_sequence_free(). - * - * \note On error, this function may return a partial list in \p cur. - * You must set `cur->next = NULL` before calling this function! - * Otherwise it is impossible to distinguish a previously non-null - * pointer from a pointer to an object allocated by this function. - * - * \note If the sequence is empty, this function does not modify - * \c *cur. If the sequence is valid and non-empty, this - * function sets `cur->buf.tag` to \p tag. This allows - * callers to distinguish between an empty sequence and - * a one-element sequence. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p is equal to \p end. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param cur A ::mbedtls_asn1_sequence which this function fills. - * When this function returns, \c *cur is the head of a linked - * list. Each node in this list is allocated with - * mbedtls_calloc() apart from \p cur itself, and should - * therefore be freed with mbedtls_free(). - * The list describes the content of the sequence. - * The head of the list (i.e. \c *cur itself) describes the - * first element, `*cur->next` describes the second element, etc. - * For each element, `buf.tag == tag`, `buf.len` is the length - * of the content of the content of the element, and `buf.p` - * points to the first byte of the content (i.e. immediately - * past the length of the element). - * Note that list elements may be allocated even on error. - * \param tag Each element of the sequence must have this tag. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input contains - * extra data after a valid SEQUENCE OF \p tag. - * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts with - * an ASN.1 SEQUENCE in which an element has a tag that - * is different from \p tag. - * \return #MBEDTLS_ERR_ASN1_ALLOC_FAILED if a memory allocation failed. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 SEQUENCE. - */ -int mbedtls_asn1_get_sequence_of(unsigned char **p, - const unsigned char *end, - mbedtls_asn1_sequence *cur, - int tag); -/** - * \brief Free a heap-allocated linked list presentation of - * an ASN.1 sequence, including the first element. - * - * There are two common ways to manage the memory used for the representation - * of a parsed ASN.1 sequence: - * - Allocate a head node `mbedtls_asn1_sequence *head` with mbedtls_calloc(). - * Pass this node as the `cur` argument to mbedtls_asn1_get_sequence_of(). - * When you have finished processing the sequence, - * call mbedtls_asn1_sequence_free() on `head`. - * - Allocate a head node `mbedtls_asn1_sequence *head` in any manner, - * for example on the stack. Make sure that `head->next == NULL`. - * Pass `head` as the `cur` argument to mbedtls_asn1_get_sequence_of(). - * When you have finished processing the sequence, - * call mbedtls_asn1_sequence_free() on `head->cur`, - * then free `head` itself in the appropriate manner. - * - * \param seq The address of the first sequence component. This may - * be \c NULL, in which case this functions returns - * immediately. - */ -void mbedtls_asn1_sequence_free(mbedtls_asn1_sequence *seq); - -/** - * \brief Traverse an ASN.1 SEQUENCE container and - * call a callback for each entry. - * - * This function checks that the input is a SEQUENCE of elements that - * each have a "must" tag, and calls a callback function on the elements - * that have a "may" tag. - * - * For example, to validate that the input is a SEQUENCE of `tag1` and call - * `cb` on each element, use - * ``` - * mbedtls_asn1_traverse_sequence_of(&p, end, 0xff, tag1, 0, 0, cb, ctx); - * ``` - * - * To validate that the input is a SEQUENCE of ANY and call `cb` on - * each element, use - * ``` - * mbedtls_asn1_traverse_sequence_of(&p, end, 0, 0, 0, 0, cb, ctx); - * ``` - * - * To validate that the input is a SEQUENCE of CHOICE {NULL, OCTET STRING} - * and call `cb` on each element that is an OCTET STRING, use - * ``` - * mbedtls_asn1_traverse_sequence_of(&p, end, 0xfe, 0x04, 0xff, 0x04, cb, ctx); - * ``` - * - * The callback is called on the elements with a "may" tag from left to - * right. If the input is not a valid SEQUENCE of elements with a "must" tag, - * the callback is called on the elements up to the leftmost point where - * the input is invalid. - * - * \warning This function is still experimental and may change - * at any time. - * - * \param p The address of the pointer to the beginning of - * the ASN.1 SEQUENCE header. This is updated to - * point to the end of the ASN.1 SEQUENCE container - * on a successful invocation. - * \param end The end of the ASN.1 SEQUENCE container. - * \param tag_must_mask A mask to be applied to the ASN.1 tags found within - * the SEQUENCE before comparing to \p tag_must_val. - * \param tag_must_val The required value of each ASN.1 tag found in the - * SEQUENCE, after masking with \p tag_must_mask. - * Mismatching tags lead to an error. - * For example, a value of \c 0 for both \p tag_must_mask - * and \p tag_must_val means that every tag is allowed, - * while a value of \c 0xFF for \p tag_must_mask means - * that \p tag_must_val is the only allowed tag. - * \param tag_may_mask A mask to be applied to the ASN.1 tags found within - * the SEQUENCE before comparing to \p tag_may_val. - * \param tag_may_val The desired value of each ASN.1 tag found in the - * SEQUENCE, after masking with \p tag_may_mask. - * Mismatching tags will be silently ignored. - * For example, a value of \c 0 for \p tag_may_mask and - * \p tag_may_val means that any tag will be considered, - * while a value of \c 0xFF for \p tag_may_mask means - * that all tags with value different from \p tag_may_val - * will be ignored. - * \param cb The callback to trigger for each component - * in the ASN.1 SEQUENCE that matches \p tag_may_val. - * The callback function is called with the following - * parameters: - * - \p ctx. - * - The tag of the current element. - * - A pointer to the start of the current element's - * content inside the input. - * - The length of the content of the current element. - * If the callback returns a non-zero value, - * the function stops immediately, - * forwarding the callback's return value. - * \param ctx The context to be passed to the callback \p cb. - * - * \return \c 0 if successful the entire ASN.1 SEQUENCE - * was traversed without parsing or callback errors. - * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input - * contains extra data after a valid SEQUENCE - * of elements with an accepted tag. - * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts - * with an ASN.1 SEQUENCE in which an element has a tag - * that is not accepted. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 SEQUENCE. - * \return A non-zero error code forwarded from the callback - * \p cb in case the latter returns a non-zero value. - */ -int mbedtls_asn1_traverse_sequence_of( - unsigned char **p, - const unsigned char *end, - unsigned char tag_must_mask, unsigned char tag_must_val, - unsigned char tag_may_mask, unsigned char tag_may_val, - int (*cb)(void *ctx, int tag, - unsigned char *start, size_t len), - void *ctx); - -#if defined(MBEDTLS_BIGNUM_C) -/** - * \brief Retrieve an integer ASN.1 tag and its value. - * Updates the pointer to immediately behind the full tag. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the ASN.1 element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param X On success, the parsed value. - * - * \return 0 if successful. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 INTEGER. - * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does - * not fit in an \c int. - * \return An MPI error code if the parsed value is too large. - */ -int mbedtls_asn1_get_mpi(unsigned char **p, - const unsigned char *end, - mbedtls_mpi *X); -#endif /* MBEDTLS_BIGNUM_C */ - -/** - * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence. - * Updates the pointer to immediately behind the full - * AlgorithmIdentifier. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the AlgorithmIdentifier element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param alg The buffer to receive the OID. - * \param params The buffer to receive the parameters. - * This is zeroized if there are no parameters. - * - * \return 0 if successful or a specific ASN.1 or MPI error code. - */ -int mbedtls_asn1_get_alg(unsigned char **p, - const unsigned char *end, - mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params); - -/** - * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence with NULL or no - * params. - * Updates the pointer to immediately behind the full - * AlgorithmIdentifier. - * - * \param p On entry, \c *p points to the start of the ASN.1 element. - * On successful completion, \c *p points to the first byte - * beyond the AlgorithmIdentifier element. - * On error, the value of \c *p is undefined. - * \param end End of data. - * \param alg The buffer to receive the OID. - * - * \return 0 if successful or a specific ASN.1 or MPI error code. - */ -int mbedtls_asn1_get_alg_null(unsigned char **p, - const unsigned char *end, - mbedtls_asn1_buf *alg); - -/** - * \brief Find a specific named_data entry in a sequence or list based on - * the OID. - * - * \param list The list to seek through - * \param oid The OID to look for - * \param len Size of the OID - * - * \return NULL if not found, or a pointer to the existing entry. - */ -const mbedtls_asn1_named_data *mbedtls_asn1_find_named_data(const mbedtls_asn1_named_data *list, - const char *oid, size_t len); - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Free a mbedtls_asn1_named_data entry - * - * \deprecated This function is deprecated and will be removed in a - * future version of the library. - * Please use mbedtls_asn1_free_named_data_list() - * or mbedtls_asn1_free_named_data_list_shallow(). - * - * \param entry The named data entry to free. - * This function calls mbedtls_free() on - * `entry->oid.p` and `entry->val.p`. - */ -void MBEDTLS_DEPRECATED mbedtls_asn1_free_named_data(mbedtls_asn1_named_data *entry); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -/** - * \brief Free all entries in a mbedtls_asn1_named_data list. - * - * \param head Pointer to the head of the list of named data entries to free. - * This function calls mbedtls_free() on - * `entry->oid.p` and `entry->val.p` and then on `entry` - * for each list entry, and sets \c *head to \c NULL. - */ -void mbedtls_asn1_free_named_data_list(mbedtls_asn1_named_data **head); - -/** - * \brief Free all shallow entries in a mbedtls_asn1_named_data list, - * but do not free internal pointer targets. - * - * \param name Head of the list of named data entries to free. - * This function calls mbedtls_free() on each list element. - */ -void mbedtls_asn1_free_named_data_list_shallow(mbedtls_asn1_named_data *name); - -/** \} name Functions to parse ASN.1 data structures */ -/** \} addtogroup asn1_module */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_ASN1_PARSE_C */ - -#endif /* asn1.h */ +/** + * \file asn1.h + * + * \brief Generic ASN.1 parsing + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ASN1_H +#define MBEDTLS_ASN1_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +/** + * \addtogroup asn1_module + * \{ + */ + +/** + * \name ASN1 Error codes + * These error codes are combined with other error codes for + * higher error granularity. + * e.g. X.509 and PKCS #7 error codes + * ASN1 is a standard to specify data structures. + * \{ + */ +/** Out of data when parsing an ASN1 data structure. */ +#define MBEDTLS_ERR_ASN1_OUT_OF_DATA -0x0060 +/** ASN1 tag was of an unexpected value. */ +#define MBEDTLS_ERR_ASN1_UNEXPECTED_TAG -0x0062 +/** Error when trying to determine the length or invalid length. */ +#define MBEDTLS_ERR_ASN1_INVALID_LENGTH -0x0064 +/** Actual length differs from expected length. */ +#define MBEDTLS_ERR_ASN1_LENGTH_MISMATCH -0x0066 +/** Data is invalid. */ +#define MBEDTLS_ERR_ASN1_INVALID_DATA -0x0068 +/** Memory allocation failed */ +#define MBEDTLS_ERR_ASN1_ALLOC_FAILED -0x006A +/** Buffer too small when writing ASN.1 data structure. */ +#define MBEDTLS_ERR_ASN1_BUF_TOO_SMALL -0x006C + +/** \} name ASN1 Error codes */ + +/** + * \name DER constants + * These constants comply with the DER encoded ASN.1 type tags. + * DER encoding uses hexadecimal representation. + * An example DER sequence is:\n + * - 0x02 -- tag indicating INTEGER + * - 0x01 -- length in octets + * - 0x05 -- value + * Such sequences are typically read into \c ::mbedtls_x509_buf. + * \{ + */ +#define MBEDTLS_ASN1_BOOLEAN 0x01 +#define MBEDTLS_ASN1_INTEGER 0x02 +#define MBEDTLS_ASN1_BIT_STRING 0x03 +#define MBEDTLS_ASN1_OCTET_STRING 0x04 +#define MBEDTLS_ASN1_NULL 0x05 +#define MBEDTLS_ASN1_OID 0x06 +#define MBEDTLS_ASN1_ENUMERATED 0x0A +#define MBEDTLS_ASN1_UTF8_STRING 0x0C +#define MBEDTLS_ASN1_SEQUENCE 0x10 +#define MBEDTLS_ASN1_SET 0x11 +#define MBEDTLS_ASN1_PRINTABLE_STRING 0x13 +#define MBEDTLS_ASN1_T61_STRING 0x14 +#define MBEDTLS_ASN1_IA5_STRING 0x16 +#define MBEDTLS_ASN1_UTC_TIME 0x17 +#define MBEDTLS_ASN1_GENERALIZED_TIME 0x18 +#define MBEDTLS_ASN1_UNIVERSAL_STRING 0x1C +#define MBEDTLS_ASN1_BMP_STRING 0x1E +#define MBEDTLS_ASN1_PRIMITIVE 0x00 +#define MBEDTLS_ASN1_CONSTRUCTED 0x20 +#define MBEDTLS_ASN1_CONTEXT_SPECIFIC 0x80 + +/* Slightly smaller way to check if tag is a string tag + * compared to canonical implementation. */ +#define MBEDTLS_ASN1_IS_STRING_TAG(tag) \ + ((unsigned int) (tag) < 32u && ( \ + ((1u << (tag)) & ((1u << MBEDTLS_ASN1_BMP_STRING) | \ + (1u << MBEDTLS_ASN1_UTF8_STRING) | \ + (1u << MBEDTLS_ASN1_T61_STRING) | \ + (1u << MBEDTLS_ASN1_IA5_STRING) | \ + (1u << MBEDTLS_ASN1_UNIVERSAL_STRING) | \ + (1u << MBEDTLS_ASN1_PRINTABLE_STRING))) != 0)) + +/* + * Bit masks for each of the components of an ASN.1 tag as specified in + * ITU X.690 (08/2015), section 8.1 "General rules for encoding", + * paragraph 8.1.2.2: + * + * Bit 8 7 6 5 1 + * +-------+-----+------------+ + * | Class | P/C | Tag number | + * +-------+-----+------------+ + */ +#define MBEDTLS_ASN1_TAG_CLASS_MASK 0xC0 +#define MBEDTLS_ASN1_TAG_PC_MASK 0x20 +#define MBEDTLS_ASN1_TAG_VALUE_MASK 0x1F + +/** \} name DER constants */ + +/** Returns the size of the binary string, without the trailing \\0 */ +#define MBEDTLS_OID_SIZE(x) (sizeof(x) - 1) + +/** + * Compares an mbedtls_asn1_buf structure to a reference OID. + * + * Only works for 'defined' oid_str values (MBEDTLS_OID_HMAC_SHA1), you cannot use a + * 'unsigned char *oid' here! + */ +#define MBEDTLS_OID_CMP(oid_str, oid_buf) \ + ((MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len) || \ + memcmp((oid_str), (oid_buf)->p, (oid_buf)->len) != 0) + +#define MBEDTLS_OID_CMP_RAW(oid_str, oid_buf, oid_buf_len) \ + ((MBEDTLS_OID_SIZE(oid_str) != (oid_buf_len)) || \ + memcmp((oid_str), (oid_buf), (oid_buf_len)) != 0) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name Functions to parse ASN.1 data structures + * \{ + */ + +/** + * Type-length-value structure that allows for ASN1 using DER. + */ +typedef struct mbedtls_asn1_buf { + int tag; /**< ASN1 type, e.g. MBEDTLS_ASN1_UTF8_STRING. */ + size_t len; /**< ASN1 length, in octets. */ + unsigned char *p; /**< ASN1 data, e.g. in ASCII. */ +} +mbedtls_asn1_buf; + +/** + * Container for ASN1 bit strings. + */ +typedef struct mbedtls_asn1_bitstring { + size_t len; /**< ASN1 length, in octets. */ + unsigned char unused_bits; /**< Number of unused bits at the end of the string */ + unsigned char *p; /**< Raw ASN1 data for the bit string */ +} +mbedtls_asn1_bitstring; + +/** + * Container for a sequence of ASN.1 items + */ +typedef struct mbedtls_asn1_sequence { + mbedtls_asn1_buf buf; /**< Buffer containing the given ASN.1 item. */ + + /** The next entry in the sequence. + * + * The details of memory management for sequences are not documented and + * may change in future versions. Set this field to \p NULL when + * initializing a structure, and do not modify it except via Mbed TLS + * library functions. + */ + struct mbedtls_asn1_sequence *next; +} +mbedtls_asn1_sequence; + +/** + * Container for a sequence or list of 'named' ASN.1 data items + */ +typedef struct mbedtls_asn1_named_data { + mbedtls_asn1_buf oid; /**< The object identifier. */ + mbedtls_asn1_buf val; /**< The named value. */ + + /** The next entry in the sequence. + * + * The details of memory management for named data sequences are not + * documented and may change in future versions. Set this field to \p NULL + * when initializing a structure, and do not modify it except via Mbed TLS + * library functions. + */ + struct mbedtls_asn1_named_data *next; + + /** Merge next item into the current one? + * + * This field exists for the sake of Mbed TLS's X.509 certificate parsing + * code and may change in future versions of the library. + */ + unsigned char MBEDTLS_PRIVATE(next_merged); +} +mbedtls_asn1_named_data; + +#if defined(MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_X509_CREATE_C) +/** + * \brief Get the length of an ASN.1 element. + * Updates the pointer to immediately behind the length. + * + * \param p On entry, \c *p points to the first byte of the length, + * i.e. immediately after the tag. + * On successful completion, \c *p points to the first byte + * after the length, i.e. the first byte of the content. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param len On successful completion, \c *len contains the length + * read from the ASN.1 input. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_OUT_OF_DATA if the ASN.1 element + * would end beyond \p end. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the length is unparsable. + */ +int mbedtls_asn1_get_len(unsigned char **p, + const unsigned char *end, + size_t *len); + +/** + * \brief Get the tag and length of the element. + * Check for the requested tag. + * Updates the pointer to immediately behind the tag and length. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * after the length, i.e. the first byte of the content. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param len On successful completion, \c *len contains the length + * read from the ASN.1 input. + * \param tag The expected tag. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the data does not start + * with the requested tag. + * \return #MBEDTLS_ERR_ASN1_OUT_OF_DATA if the ASN.1 element + * would end beyond \p end. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the length is unparsable. + */ +int mbedtls_asn1_get_tag(unsigned char **p, + const unsigned char *end, + size_t *len, int tag); +#endif /* MBEDTLS_ASN1_PARSE_C || MBEDTLS_X509_CREATE_C */ + +#if defined(MBEDTLS_ASN1_PARSE_C) +/** + * \brief Retrieve a boolean ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the ASN.1 element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param val On success, the parsed value (\c 0 or \c 1). + * + * \return 0 if successful. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 BOOLEAN. + */ +int mbedtls_asn1_get_bool(unsigned char **p, + const unsigned char *end, + int *val); + +/** + * \brief Retrieve an integer ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the ASN.1 element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param val On success, the parsed value. + * + * \return 0 if successful. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 INTEGER. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does + * not fit in an \c int. + */ +int mbedtls_asn1_get_int(unsigned char **p, + const unsigned char *end, + int *val); + +/** + * \brief Retrieve an enumerated ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the ASN.1 element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param val On success, the parsed value. + * + * \return 0 if successful. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 ENUMERATED. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does + * not fit in an \c int. + */ +int mbedtls_asn1_get_enum(unsigned char **p, + const unsigned char *end, + int *val); + +/** + * \brief Retrieve a bitstring ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p is equal to \p end. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param bs On success, ::mbedtls_asn1_bitstring information about + * the parsed value. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input contains + * extra data after a valid BIT STRING. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 BIT STRING. + */ +int mbedtls_asn1_get_bitstring(unsigned char **p, const unsigned char *end, + mbedtls_asn1_bitstring *bs); + +/** + * \brief Retrieve a bitstring ASN.1 tag without unused bits and its + * value. + * Updates the pointer to the beginning of the bit/octet string. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * of the content of the BIT STRING. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param len On success, \c *len is the length of the content in bytes. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if the input starts with + * a valid BIT STRING with a nonzero number of unused bits. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 BIT STRING. + */ +int mbedtls_asn1_get_bitstring_null(unsigned char **p, + const unsigned char *end, + size_t *len); + +/** + * \brief Parses and splits an ASN.1 "SEQUENCE OF ". + * Updates the pointer to immediately behind the full sequence tag. + * + * This function allocates memory for the sequence elements. You can free + * the allocated memory with mbedtls_asn1_sequence_free(). + * + * \note On error, this function may return a partial list in \p cur. + * You must set `cur->next = NULL` before calling this function! + * Otherwise it is impossible to distinguish a previously non-null + * pointer from a pointer to an object allocated by this function. + * + * \note If the sequence is empty, this function does not modify + * \c *cur. If the sequence is valid and non-empty, this + * function sets `cur->buf.tag` to \p tag. This allows + * callers to distinguish between an empty sequence and + * a one-element sequence. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p is equal to \p end. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param cur A ::mbedtls_asn1_sequence which this function fills. + * When this function returns, \c *cur is the head of a linked + * list. Each node in this list is allocated with + * mbedtls_calloc() apart from \p cur itself, and should + * therefore be freed with mbedtls_free(). + * The list describes the content of the sequence. + * The head of the list (i.e. \c *cur itself) describes the + * first element, `*cur->next` describes the second element, etc. + * For each element, `buf.tag == tag`, `buf.len` is the length + * of the content of the content of the element, and `buf.p` + * points to the first byte of the content (i.e. immediately + * past the length of the element). + * Note that list elements may be allocated even on error. + * \param tag Each element of the sequence must have this tag. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input contains + * extra data after a valid SEQUENCE OF \p tag. + * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts with + * an ASN.1 SEQUENCE in which an element has a tag that + * is different from \p tag. + * \return #MBEDTLS_ERR_ASN1_ALLOC_FAILED if a memory allocation failed. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 SEQUENCE. + */ +int mbedtls_asn1_get_sequence_of(unsigned char **p, + const unsigned char *end, + mbedtls_asn1_sequence *cur, + int tag); +/** + * \brief Free a heap-allocated linked list presentation of + * an ASN.1 sequence, including the first element. + * + * There are two common ways to manage the memory used for the representation + * of a parsed ASN.1 sequence: + * - Allocate a head node `mbedtls_asn1_sequence *head` with mbedtls_calloc(). + * Pass this node as the `cur` argument to mbedtls_asn1_get_sequence_of(). + * When you have finished processing the sequence, + * call mbedtls_asn1_sequence_free() on `head`. + * - Allocate a head node `mbedtls_asn1_sequence *head` in any manner, + * for example on the stack. Make sure that `head->next == NULL`. + * Pass `head` as the `cur` argument to mbedtls_asn1_get_sequence_of(). + * When you have finished processing the sequence, + * call mbedtls_asn1_sequence_free() on `head->cur`, + * then free `head` itself in the appropriate manner. + * + * \param seq The address of the first sequence component. This may + * be \c NULL, in which case this functions returns + * immediately. + */ +void mbedtls_asn1_sequence_free(mbedtls_asn1_sequence *seq); + +/** + * \brief Traverse an ASN.1 SEQUENCE container and + * call a callback for each entry. + * + * This function checks that the input is a SEQUENCE of elements that + * each have a "must" tag, and calls a callback function on the elements + * that have a "may" tag. + * + * For example, to validate that the input is a SEQUENCE of `tag1` and call + * `cb` on each element, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0xff, tag1, 0, 0, cb, ctx); + * ``` + * + * To validate that the input is a SEQUENCE of ANY and call `cb` on + * each element, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0, 0, 0, 0, cb, ctx); + * ``` + * + * To validate that the input is a SEQUENCE of CHOICE {NULL, OCTET STRING} + * and call `cb` on each element that is an OCTET STRING, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0xfe, 0x04, 0xff, 0x04, cb, ctx); + * ``` + * + * The callback is called on the elements with a "may" tag from left to + * right. If the input is not a valid SEQUENCE of elements with a "must" tag, + * the callback is called on the elements up to the leftmost point where + * the input is invalid. + * + * \warning This function is still experimental and may change + * at any time. + * + * \param p The address of the pointer to the beginning of + * the ASN.1 SEQUENCE header. This is updated to + * point to the end of the ASN.1 SEQUENCE container + * on a successful invocation. + * \param end The end of the ASN.1 SEQUENCE container. + * \param tag_must_mask A mask to be applied to the ASN.1 tags found within + * the SEQUENCE before comparing to \p tag_must_val. + * \param tag_must_val The required value of each ASN.1 tag found in the + * SEQUENCE, after masking with \p tag_must_mask. + * Mismatching tags lead to an error. + * For example, a value of \c 0 for both \p tag_must_mask + * and \p tag_must_val means that every tag is allowed, + * while a value of \c 0xFF for \p tag_must_mask means + * that \p tag_must_val is the only allowed tag. + * \param tag_may_mask A mask to be applied to the ASN.1 tags found within + * the SEQUENCE before comparing to \p tag_may_val. + * \param tag_may_val The desired value of each ASN.1 tag found in the + * SEQUENCE, after masking with \p tag_may_mask. + * Mismatching tags will be silently ignored. + * For example, a value of \c 0 for \p tag_may_mask and + * \p tag_may_val means that any tag will be considered, + * while a value of \c 0xFF for \p tag_may_mask means + * that all tags with value different from \p tag_may_val + * will be ignored. + * \param cb The callback to trigger for each component + * in the ASN.1 SEQUENCE that matches \p tag_may_val. + * The callback function is called with the following + * parameters: + * - \p ctx. + * - The tag of the current element. + * - A pointer to the start of the current element's + * content inside the input. + * - The length of the content of the current element. + * If the callback returns a non-zero value, + * the function stops immediately, + * forwarding the callback's return value. + * \param ctx The context to be passed to the callback \p cb. + * + * \return \c 0 if successful the entire ASN.1 SEQUENCE + * was traversed without parsing or callback errors. + * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input + * contains extra data after a valid SEQUENCE + * of elements with an accepted tag. + * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts + * with an ASN.1 SEQUENCE in which an element has a tag + * that is not accepted. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 SEQUENCE. + * \return A non-zero error code forwarded from the callback + * \p cb in case the latter returns a non-zero value. + */ +int mbedtls_asn1_traverse_sequence_of( + unsigned char **p, + const unsigned char *end, + unsigned char tag_must_mask, unsigned char tag_must_val, + unsigned char tag_may_mask, unsigned char tag_may_val, + int (*cb)(void *ctx, int tag, + unsigned char *start, size_t len), + void *ctx); + +#if defined(MBEDTLS_BIGNUM_C) +/** + * \brief Retrieve an integer ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the ASN.1 element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param X On success, the parsed value. + * + * \return 0 if successful. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 INTEGER. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does + * not fit in an \c int. + * \return An MPI error code if the parsed value is too large. + */ +int mbedtls_asn1_get_mpi(unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X); +#endif /* MBEDTLS_BIGNUM_C */ + +/** + * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence. + * Updates the pointer to immediately behind the full + * AlgorithmIdentifier. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the AlgorithmIdentifier element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param alg The buffer to receive the OID. + * \param params The buffer to receive the parameters. + * This is zeroized if there are no parameters. + * + * \return 0 if successful or a specific ASN.1 or MPI error code. + */ +int mbedtls_asn1_get_alg(unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params); + +/** + * \brief Retrieve an AlgorithmIdentifier ASN.1 sequence with NULL or no + * params. + * Updates the pointer to immediately behind the full + * AlgorithmIdentifier. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the AlgorithmIdentifier element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param alg The buffer to receive the OID. + * + * \return 0 if successful or a specific ASN.1 or MPI error code. + */ +int mbedtls_asn1_get_alg_null(unsigned char **p, + const unsigned char *end, + mbedtls_asn1_buf *alg); + +/** + * \brief Find a specific named_data entry in a sequence or list based on + * the OID. + * + * \param list The list to seek through + * \param oid The OID to look for + * \param len Size of the OID + * + * \return NULL if not found, or a pointer to the existing entry. + */ +const mbedtls_asn1_named_data *mbedtls_asn1_find_named_data(const mbedtls_asn1_named_data *list, + const char *oid, size_t len); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Free a mbedtls_asn1_named_data entry + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * Please use mbedtls_asn1_free_named_data_list() + * or mbedtls_asn1_free_named_data_list_shallow(). + * + * \param entry The named data entry to free. + * This function calls mbedtls_free() on + * `entry->oid.p` and `entry->val.p`. + */ +void MBEDTLS_DEPRECATED mbedtls_asn1_free_named_data(mbedtls_asn1_named_data *entry); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Free all entries in a mbedtls_asn1_named_data list. + * + * \param head Pointer to the head of the list of named data entries to free. + * This function calls mbedtls_free() on + * `entry->oid.p` and `entry->val.p` and then on `entry` + * for each list entry, and sets \c *head to \c NULL. + */ +void mbedtls_asn1_free_named_data_list(mbedtls_asn1_named_data **head); + +/** + * \brief Free all shallow entries in a mbedtls_asn1_named_data list, + * but do not free internal pointer targets. + * + * \param name Head of the list of named data entries to free. + * This function calls mbedtls_free() on each list element. + */ +void mbedtls_asn1_free_named_data_list_shallow(mbedtls_asn1_named_data *name); + +/** \} name Functions to parse ASN.1 data structures */ +/** \} addtogroup asn1_module */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_ASN1_PARSE_C */ + +#endif /* asn1.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1write.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1write.h index 6fe57c8..488948e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1write.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/asn1write.h @@ -1,401 +1,401 @@ -/** - * \file asn1write.h - * - * \brief ASN.1 buffer writing functionality - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ASN1_WRITE_H -#define MBEDTLS_ASN1_WRITE_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/asn1.h" - -#define MBEDTLS_ASN1_CHK_ADD(g, f) \ - do \ - { \ - if ((ret = (f)) < 0) \ - return ret; \ - else \ - (g) += ret; \ - } while (0) - -#define MBEDTLS_ASN1_CHK_CLEANUP_ADD(g, f) \ - do \ - { \ - if ((ret = (f)) < 0) \ - goto cleanup; \ - else \ - (g) += ret; \ - } while (0) - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(MBEDTLS_ASN1_WRITE_C) || defined(MBEDTLS_X509_USE_C) -/** - * \brief Write a length field in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param len The length value to write. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_len(unsigned char **p, const unsigned char *start, - size_t len); -/** - * \brief Write an ASN.1 tag in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param tag The tag to write. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_tag(unsigned char **p, const unsigned char *start, - unsigned char tag); -#endif /* MBEDTLS_ASN1_WRITE_C || MBEDTLS_X509_USE_C */ - -#if defined(MBEDTLS_ASN1_WRITE_C) -/** - * \brief Write raw buffer data. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param buf The data buffer to write. - * \param size The length of the data buffer. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_raw_buffer(unsigned char **p, const unsigned char *start, - const unsigned char *buf, size_t size); - -#if defined(MBEDTLS_BIGNUM_C) -/** - * \brief Write an arbitrary-precision number (#MBEDTLS_ASN1_INTEGER) - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param X The MPI to write. - * It must be non-negative. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_mpi(unsigned char **p, const unsigned char *start, - const mbedtls_mpi *X); -#endif /* MBEDTLS_BIGNUM_C */ - -/** - * \brief Write a NULL tag (#MBEDTLS_ASN1_NULL) with zero data - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_null(unsigned char **p, const unsigned char *start); - -/** - * \brief Write an OID tag (#MBEDTLS_ASN1_OID) and data - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param oid The OID to write. - * \param oid_len The length of the OID. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_oid(unsigned char **p, const unsigned char *start, - const char *oid, size_t oid_len); - -/** - * \brief Write an AlgorithmIdentifier sequence in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param oid The OID of the algorithm to write. - * \param oid_len The length of the algorithm's OID. - * \param par_len The length of the parameters, which must be already written. - * If 0, NULL parameters are added - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_algorithm_identifier(unsigned char **p, - const unsigned char *start, - const char *oid, size_t oid_len, - size_t par_len); - -/** - * \brief Write an AlgorithmIdentifier sequence in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param oid The OID of the algorithm to write. - * \param oid_len The length of the algorithm's OID. - * \param par_len The length of the parameters, which must be already written. - * \param has_par If there are any parameters. If 0, par_len must be 0. If 1 - * and \p par_len is 0, NULL parameters are added. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_algorithm_identifier_ext(unsigned char **p, - const unsigned char *start, - const char *oid, size_t oid_len, - size_t par_len, int has_par); - -/** - * \brief Write a boolean tag (#MBEDTLS_ASN1_BOOLEAN) and value - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param boolean The boolean value to write, either \c 0 or \c 1. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_bool(unsigned char **p, const unsigned char *start, - int boolean); - -/** - * \brief Write an int tag (#MBEDTLS_ASN1_INTEGER) and value - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param val The integer value to write. - * It must be non-negative. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_int(unsigned char **p, const unsigned char *start, int val); - -/** - * \brief Write an enum tag (#MBEDTLS_ASN1_ENUMERATED) and value - * in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param val The integer value to write. - * - * \return The number of bytes written to \p p on success. - * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_asn1_write_enum(unsigned char **p, const unsigned char *start, int val); - -/** - * \brief Write a string in ASN.1 format using a specific - * string encoding tag. - - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param tag The string encoding tag to write, e.g. - * #MBEDTLS_ASN1_UTF8_STRING. - * \param text The string to write. - * \param text_len The length of \p text in bytes (which might - * be strictly larger than the number of characters). - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_tagged_string(unsigned char **p, const unsigned char *start, - int tag, const char *text, - size_t text_len); - -/** - * \brief Write a string in ASN.1 format using the PrintableString - * string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING). - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param text The string to write. - * \param text_len The length of \p text in bytes (which might - * be strictly larger than the number of characters). - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_printable_string(unsigned char **p, - const unsigned char *start, - const char *text, size_t text_len); - -/** - * \brief Write a UTF8 string in ASN.1 format using the UTF8String - * string encoding tag (#MBEDTLS_ASN1_UTF8_STRING). - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param text The string to write. - * \param text_len The length of \p text in bytes (which might - * be strictly larger than the number of characters). - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_utf8_string(unsigned char **p, const unsigned char *start, - const char *text, size_t text_len); - -/** - * \brief Write a string in ASN.1 format using the IA5String - * string encoding tag (#MBEDTLS_ASN1_IA5_STRING). - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param text The string to write. - * \param text_len The length of \p text in bytes (which might - * be strictly larger than the number of characters). - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_ia5_string(unsigned char **p, const unsigned char *start, - const char *text, size_t text_len); - -/** - * \brief Write a bitstring tag (#MBEDTLS_ASN1_BIT_STRING) and - * value in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param buf The bitstring to write. - * \param bits The total number of bits in the bitstring. - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_bitstring(unsigned char **p, const unsigned char *start, - const unsigned char *buf, size_t bits); - -/** - * \brief This function writes a named bitstring tag - * (#MBEDTLS_ASN1_BIT_STRING) and value in ASN.1 format. - * - * As stated in RFC 5280 Appendix B, trailing zeroes are - * omitted when encoding named bitstrings in DER. - * - * \note This function works backwards within the data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer which is used for bounds-checking. - * \param buf The bitstring to write. - * \param bits The total number of bits in the bitstring. - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_named_bitstring(unsigned char **p, - const unsigned char *start, - const unsigned char *buf, - size_t bits); - -/** - * \brief Write an octet string tag (#MBEDTLS_ASN1_OCTET_STRING) - * and value in ASN.1 format. - * - * \note This function works backwards in data buffer. - * - * \param p The reference to the current position pointer. - * \param start The start of the buffer, for bounds-checking. - * \param buf The buffer holding the data to write. - * \param size The length of the data buffer \p buf. - * - * \return The number of bytes written to \p p on success. - * \return A negative error code on failure. - */ -int mbedtls_asn1_write_octet_string(unsigned char **p, const unsigned char *start, - const unsigned char *buf, size_t size); - -/** - * \brief Create or find a specific named_data entry for writing in a - * sequence or list based on the OID. If not already in there, - * a new entry is added to the head of the list. - * Warning: Destructive behaviour for the val data! - * - * \param list The pointer to the location of the head of the list to seek - * through (will be updated in case of a new entry). - * \param oid The OID to look for. - * \param oid_len The size of the OID. - * \param val The associated data to store. If this is \c NULL, - * no data is copied to the new or existing buffer. - * \param val_len The minimum length of the data buffer needed. - * If this is 0, do not allocate a buffer for the associated - * data. - * If the OID was already present, enlarge, shrink or free - * the existing buffer to fit \p val_len. - * - * \return A pointer to the new / existing entry on success. - * \return \c NULL if there was a memory allocation error. - */ -mbedtls_asn1_named_data *mbedtls_asn1_store_named_data(mbedtls_asn1_named_data **list, - const char *oid, size_t oid_len, - const unsigned char *val, - size_t val_len); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_ASN1_WRITE_C */ - -#endif /* MBEDTLS_ASN1_WRITE_H */ +/** + * \file asn1write.h + * + * \brief ASN.1 buffer writing functionality + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ASN1_WRITE_H +#define MBEDTLS_ASN1_WRITE_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/asn1.h" + +#define MBEDTLS_ASN1_CHK_ADD(g, f) \ + do \ + { \ + if ((ret = (f)) < 0) \ + return ret; \ + else \ + (g) += ret; \ + } while (0) + +#define MBEDTLS_ASN1_CHK_CLEANUP_ADD(g, f) \ + do \ + { \ + if ((ret = (f)) < 0) \ + goto cleanup; \ + else \ + (g) += ret; \ + } while (0) + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ASN1_WRITE_C) || defined(MBEDTLS_X509_USE_C) +/** + * \brief Write a length field in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param len The length value to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_len(unsigned char **p, const unsigned char *start, + size_t len); +/** + * \brief Write an ASN.1 tag in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param tag The tag to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_tag(unsigned char **p, const unsigned char *start, + unsigned char tag); +#endif /* MBEDTLS_ASN1_WRITE_C || MBEDTLS_X509_USE_C */ + +#if defined(MBEDTLS_ASN1_WRITE_C) +/** + * \brief Write raw buffer data. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The data buffer to write. + * \param size The length of the data buffer. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_raw_buffer(unsigned char **p, const unsigned char *start, + const unsigned char *buf, size_t size); + +#if defined(MBEDTLS_BIGNUM_C) +/** + * \brief Write an arbitrary-precision number (#MBEDTLS_ASN1_INTEGER) + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param X The MPI to write. + * It must be non-negative. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_mpi(unsigned char **p, const unsigned char *start, + const mbedtls_mpi *X); +#endif /* MBEDTLS_BIGNUM_C */ + +/** + * \brief Write a NULL tag (#MBEDTLS_ASN1_NULL) with zero data + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_null(unsigned char **p, const unsigned char *start); + +/** + * \brief Write an OID tag (#MBEDTLS_ASN1_OID) and data + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param oid The OID to write. + * \param oid_len The length of the OID. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_oid(unsigned char **p, const unsigned char *start, + const char *oid, size_t oid_len); + +/** + * \brief Write an AlgorithmIdentifier sequence in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param oid The OID of the algorithm to write. + * \param oid_len The length of the algorithm's OID. + * \param par_len The length of the parameters, which must be already written. + * If 0, NULL parameters are added + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_algorithm_identifier(unsigned char **p, + const unsigned char *start, + const char *oid, size_t oid_len, + size_t par_len); + +/** + * \brief Write an AlgorithmIdentifier sequence in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param oid The OID of the algorithm to write. + * \param oid_len The length of the algorithm's OID. + * \param par_len The length of the parameters, which must be already written. + * \param has_par If there are any parameters. If 0, par_len must be 0. If 1 + * and \p par_len is 0, NULL parameters are added. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_algorithm_identifier_ext(unsigned char **p, + const unsigned char *start, + const char *oid, size_t oid_len, + size_t par_len, int has_par); + +/** + * \brief Write a boolean tag (#MBEDTLS_ASN1_BOOLEAN) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param boolean The boolean value to write, either \c 0 or \c 1. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_bool(unsigned char **p, const unsigned char *start, + int boolean); + +/** + * \brief Write an int tag (#MBEDTLS_ASN1_INTEGER) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param val The integer value to write. + * It must be non-negative. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_int(unsigned char **p, const unsigned char *start, int val); + +/** + * \brief Write an enum tag (#MBEDTLS_ASN1_ENUMERATED) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param val The integer value to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_enum(unsigned char **p, const unsigned char *start, int val); + +/** + * \brief Write a string in ASN.1 format using a specific + * string encoding tag. + + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param tag The string encoding tag to write, e.g. + * #MBEDTLS_ASN1_UTF8_STRING. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_tagged_string(unsigned char **p, const unsigned char *start, + int tag, const char *text, + size_t text_len); + +/** + * \brief Write a string in ASN.1 format using the PrintableString + * string encoding tag (#MBEDTLS_ASN1_PRINTABLE_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_printable_string(unsigned char **p, + const unsigned char *start, + const char *text, size_t text_len); + +/** + * \brief Write a UTF8 string in ASN.1 format using the UTF8String + * string encoding tag (#MBEDTLS_ASN1_UTF8_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_utf8_string(unsigned char **p, const unsigned char *start, + const char *text, size_t text_len); + +/** + * \brief Write a string in ASN.1 format using the IA5String + * string encoding tag (#MBEDTLS_ASN1_IA5_STRING). + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param text The string to write. + * \param text_len The length of \p text in bytes (which might + * be strictly larger than the number of characters). + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_ia5_string(unsigned char **p, const unsigned char *start, + const char *text, size_t text_len); + +/** + * \brief Write a bitstring tag (#MBEDTLS_ASN1_BIT_STRING) and + * value in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The bitstring to write. + * \param bits The total number of bits in the bitstring. + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_bitstring(unsigned char **p, const unsigned char *start, + const unsigned char *buf, size_t bits); + +/** + * \brief This function writes a named bitstring tag + * (#MBEDTLS_ASN1_BIT_STRING) and value in ASN.1 format. + * + * As stated in RFC 5280 Appendix B, trailing zeroes are + * omitted when encoding named bitstrings in DER. + * + * \note This function works backwards within the data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer which is used for bounds-checking. + * \param buf The bitstring to write. + * \param bits The total number of bits in the bitstring. + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_named_bitstring(unsigned char **p, + const unsigned char *start, + const unsigned char *buf, + size_t bits); + +/** + * \brief Write an octet string tag (#MBEDTLS_ASN1_OCTET_STRING) + * and value in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param buf The buffer holding the data to write. + * \param size The length of the data buffer \p buf. + * + * \return The number of bytes written to \p p on success. + * \return A negative error code on failure. + */ +int mbedtls_asn1_write_octet_string(unsigned char **p, const unsigned char *start, + const unsigned char *buf, size_t size); + +/** + * \brief Create or find a specific named_data entry for writing in a + * sequence or list based on the OID. If not already in there, + * a new entry is added to the head of the list. + * Warning: Destructive behaviour for the val data! + * + * \param list The pointer to the location of the head of the list to seek + * through (will be updated in case of a new entry). + * \param oid The OID to look for. + * \param oid_len The size of the OID. + * \param val The associated data to store. If this is \c NULL, + * no data is copied to the new or existing buffer. + * \param val_len The minimum length of the data buffer needed. + * If this is 0, do not allocate a buffer for the associated + * data. + * If the OID was already present, enlarge, shrink or free + * the existing buffer to fit \p val_len. + * + * \return A pointer to the new / existing entry on success. + * \return \c NULL if there was a memory allocation error. + */ +mbedtls_asn1_named_data *mbedtls_asn1_store_named_data(mbedtls_asn1_named_data **list, + const char *oid, size_t oid_len, + const unsigned char *val, + size_t val_len); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_ASN1_WRITE_C */ + +#endif /* MBEDTLS_ASN1_WRITE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/base64.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/base64.h index 635be71..f9e6dd1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/base64.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/base64.h @@ -1,94 +1,94 @@ -/** - * \file base64.h - * - * \brief RFC 1521 base64 encoding/decoding - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_BASE64_H -#define MBEDTLS_BASE64_H - -#include "mbedtls/build_info.h" - -#include - -/** Output buffer too small. */ -#define MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL -0x002A -/** Invalid character in input. */ -#define MBEDTLS_ERR_BASE64_INVALID_CHARACTER -0x002C - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Encode a buffer into base64 format - * - * \param dst destination buffer - * \param dlen size of the destination buffer - * \param olen number of bytes written - * \param src source buffer - * \param slen amount of data to be encoded - * - * \return 0 if successful, or MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL. - * *olen is always updated to reflect the amount - * of data that has (or would have) been written. - * If that length cannot be represented, then no data is - * written to the buffer and *olen is set to the maximum - * length representable as a size_t. - * - * \note Call this function with dlen = 0 to obtain the - * required buffer size in *olen - */ -int mbedtls_base64_encode(unsigned char *dst, size_t dlen, size_t *olen, - const unsigned char *src, size_t slen); - -/** - * \brief Decode a base64-formatted buffer - * - * \param dst destination buffer (can be NULL for checking size) - * \param dlen size of the destination buffer - * \param olen number of bytes written - * \param src source buffer - * \param slen amount of data to be decoded - * - * \return 0 if successful, MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL, or - * MBEDTLS_ERR_BASE64_INVALID_CHARACTER if the input data is - * not correct. *olen is always updated to reflect the amount - * of data that has (or would have) been written. - * - * \note Call this function with *dst = NULL or dlen = 0 to obtain - * the required buffer size in *olen - */ -int mbedtls_base64_decode(unsigned char *dst, size_t dlen, size_t *olen, - const unsigned char *src, size_t slen); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int mbedtls_base64_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* base64.h */ +/** + * \file base64.h + * + * \brief RFC 1521 base64 encoding/decoding + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_BASE64_H +#define MBEDTLS_BASE64_H + +#include "mbedtls/build_info.h" + +#include + +/** Output buffer too small. */ +#define MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL -0x002A +/** Invalid character in input. */ +#define MBEDTLS_ERR_BASE64_INVALID_CHARACTER -0x002C + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Encode a buffer into base64 format + * + * \param dst destination buffer + * \param dlen size of the destination buffer + * \param olen number of bytes written + * \param src source buffer + * \param slen amount of data to be encoded + * + * \return 0 if successful, or MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL. + * *olen is always updated to reflect the amount + * of data that has (or would have) been written. + * If that length cannot be represented, then no data is + * written to the buffer and *olen is set to the maximum + * length representable as a size_t. + * + * \note Call this function with dlen = 0 to obtain the + * required buffer size in *olen + */ +int mbedtls_base64_encode(unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen); + +/** + * \brief Decode a base64-formatted buffer + * + * \param dst destination buffer (can be NULL for checking size) + * \param dlen size of the destination buffer + * \param olen number of bytes written + * \param src source buffer + * \param slen amount of data to be decoded + * + * \return 0 if successful, MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL, or + * MBEDTLS_ERR_BASE64_INVALID_CHARACTER if the input data is + * not correct. *olen is always updated to reflect the amount + * of data that has (or would have) been written. + * + * \note Call this function with *dst = NULL or dlen = 0 to obtain + * the required buffer size in *olen + */ +int mbedtls_base64_decode(unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_base64_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* base64.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/bignum.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/bignum.h index ebb5900..3e4f6a3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/bignum.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/bignum.h @@ -1,1096 +1,1096 @@ -/** - * \file bignum.h - * - * \brief Multi-precision integer library - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_BIGNUM_H -#define MBEDTLS_BIGNUM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#if defined(MBEDTLS_FS_IO) -#include -#endif - -/** An error occurred while reading from or writing to a file. */ -#define MBEDTLS_ERR_MPI_FILE_IO_ERROR -0x0002 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_MPI_BAD_INPUT_DATA -0x0004 -/** There is an invalid character in the digit string. */ -#define MBEDTLS_ERR_MPI_INVALID_CHARACTER -0x0006 -/** The buffer is too small to write to. */ -#define MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL -0x0008 -/** The input arguments are negative or result in illegal output. */ -#define MBEDTLS_ERR_MPI_NEGATIVE_VALUE -0x000A -/** The input argument for division is zero, which is not allowed. */ -#define MBEDTLS_ERR_MPI_DIVISION_BY_ZERO -0x000C -/** The input arguments are not acceptable. */ -#define MBEDTLS_ERR_MPI_NOT_ACCEPTABLE -0x000E -/** Memory allocation failed. */ -#define MBEDTLS_ERR_MPI_ALLOC_FAILED -0x0010 - -#define MBEDTLS_MPI_CHK(f) \ - do \ - { \ - if ((ret = (f)) != 0) \ - goto cleanup; \ - } while (0) - -/* - * Maximum size MPIs are allowed to grow to in number of limbs. - */ -#define MBEDTLS_MPI_MAX_LIMBS 10000 - -#if !defined(MBEDTLS_MPI_WINDOW_SIZE) -/* - * Maximum window size used for modular exponentiation. Default: 2 - * Minimum value: 1. Maximum value: 6. - * - * Result is an array of ( 2 ** MBEDTLS_MPI_WINDOW_SIZE ) MPIs used - * for the sliding window calculation. (So 64 by default) - * - * Reduction in size, reduces speed. - */ -#define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ -#endif /* !MBEDTLS_MPI_WINDOW_SIZE */ - -#if !defined(MBEDTLS_MPI_MAX_SIZE) -/* - * Maximum size of MPIs allowed in bits and bytes for user-MPIs. - * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits ) - * - * Note: Calculations can temporarily result in larger MPIs. So the number - * of limbs required (MBEDTLS_MPI_MAX_LIMBS) is higher. - */ -#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ -#endif /* !MBEDTLS_MPI_MAX_SIZE */ - -#define MBEDTLS_MPI_MAX_BITS (8 * MBEDTLS_MPI_MAX_SIZE) /**< Maximum number of bits for usable MPIs. */ - -/* - * When reading from files with mbedtls_mpi_read_file() and writing to files with - * mbedtls_mpi_write_file() the buffer should have space - * for a (short) label, the MPI (in the provided radix), the newline - * characters and the '\0'. - * - * By default we assume at least a 10 char label, a minimum radix of 10 - * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars). - * Autosized at compile time for at least a 10 char label, a minimum radix - * of 10 (decimal) for a number of MBEDTLS_MPI_MAX_BITS size. - * - * This used to be statically sized to 1250 for a maximum of 4096 bit - * numbers (1234 decimal chars). - * - * Calculate using the formula: - * MBEDTLS_MPI_RW_BUFFER_SIZE = ceil(MBEDTLS_MPI_MAX_BITS / ln(10) * ln(2)) + - * LabelSize + 6 - */ -#define MBEDTLS_MPI_MAX_BITS_SCALE100 (100 * MBEDTLS_MPI_MAX_BITS) -#define MBEDTLS_LN_2_DIV_LN_10_SCALE100 332 -#define MBEDTLS_MPI_RW_BUFFER_SIZE (((MBEDTLS_MPI_MAX_BITS_SCALE100 + \ - MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / \ - MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6) - -/* - * Define the base integer type, architecture-wise. - * - * 32 or 64-bit integer types can be forced regardless of the underlying - * architecture by defining MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64 - * respectively and undefining MBEDTLS_HAVE_ASM. - * - * Double-width integers (e.g. 128-bit in 64-bit architectures) can be - * disabled by defining MBEDTLS_NO_UDBL_DIVISION. - */ -#if !defined(MBEDTLS_HAVE_INT32) - #if defined(_MSC_VER) && defined(_M_AMD64) -/* Always choose 64-bit when using MSC */ - #if !defined(MBEDTLS_HAVE_INT64) - #define MBEDTLS_HAVE_INT64 - #endif /* !MBEDTLS_HAVE_INT64 */ -typedef int64_t mbedtls_mpi_sint; -typedef uint64_t mbedtls_mpi_uint; -#define MBEDTLS_MPI_UINT_MAX UINT64_MAX - #elif defined(__GNUC__) && ( \ - defined(__amd64__) || defined(__x86_64__) || \ - defined(__ppc64__) || defined(__powerpc64__) || \ - defined(__ia64__) || defined(__alpha__) || \ - (defined(__sparc__) && defined(__arch64__)) || \ - defined(__s390x__) || defined(__mips64) || \ - defined(__aarch64__)) - #if !defined(MBEDTLS_HAVE_INT64) - #define MBEDTLS_HAVE_INT64 - #endif /* MBEDTLS_HAVE_INT64 */ -typedef int64_t mbedtls_mpi_sint; -typedef uint64_t mbedtls_mpi_uint; -#define MBEDTLS_MPI_UINT_MAX UINT64_MAX - #if !defined(MBEDTLS_NO_UDBL_DIVISION) -/* mbedtls_t_udbl defined as 128-bit unsigned int */ -typedef unsigned int mbedtls_t_udbl __attribute__((mode(TI))); - #define MBEDTLS_HAVE_UDBL - #endif /* !MBEDTLS_NO_UDBL_DIVISION */ - #elif defined(__ARMCC_VERSION) && defined(__aarch64__) -/* - * __ARMCC_VERSION is defined for both armcc and armclang and - * __aarch64__ is only defined by armclang when compiling 64-bit code - */ - #if !defined(MBEDTLS_HAVE_INT64) - #define MBEDTLS_HAVE_INT64 - #endif /* !MBEDTLS_HAVE_INT64 */ -typedef int64_t mbedtls_mpi_sint; -typedef uint64_t mbedtls_mpi_uint; -#define MBEDTLS_MPI_UINT_MAX UINT64_MAX - #if !defined(MBEDTLS_NO_UDBL_DIVISION) -/* mbedtls_t_udbl defined as 128-bit unsigned int */ -typedef __uint128_t mbedtls_t_udbl; - #define MBEDTLS_HAVE_UDBL - #endif /* !MBEDTLS_NO_UDBL_DIVISION */ - #elif defined(MBEDTLS_HAVE_INT64) -/* Force 64-bit integers with unknown compiler */ -typedef int64_t mbedtls_mpi_sint; -typedef uint64_t mbedtls_mpi_uint; -#define MBEDTLS_MPI_UINT_MAX UINT64_MAX - #endif -#endif /* !MBEDTLS_HAVE_INT32 */ - -#if !defined(MBEDTLS_HAVE_INT64) -/* Default to 32-bit compilation */ - #if !defined(MBEDTLS_HAVE_INT32) - #define MBEDTLS_HAVE_INT32 - #endif /* !MBEDTLS_HAVE_INT32 */ -typedef int32_t mbedtls_mpi_sint; -typedef uint32_t mbedtls_mpi_uint; -#define MBEDTLS_MPI_UINT_MAX UINT32_MAX - #if !defined(MBEDTLS_NO_UDBL_DIVISION) -typedef uint64_t mbedtls_t_udbl; - #define MBEDTLS_HAVE_UDBL - #endif /* !MBEDTLS_NO_UDBL_DIVISION */ -#endif /* !MBEDTLS_HAVE_INT64 */ - -/* - * Sanity check that exactly one of MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64 is defined, - * so that code elsewhere doesn't have to check. - */ -#if (!(defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64))) || \ - (defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64)) -#error "Only 32-bit or 64-bit limbs are supported in bignum" -#endif - -/** \typedef mbedtls_mpi_uint - * \brief The type of machine digits in a bignum, called _limbs_. - * - * This is always an unsigned integer type with no padding bits. The size - * is platform-dependent. - */ - -/** \typedef mbedtls_mpi_sint - * \brief The signed type corresponding to #mbedtls_mpi_uint. - * - * This is always an signed integer type with no padding bits. The size - * is platform-dependent. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief MPI structure - */ -typedef struct mbedtls_mpi { - /** Pointer to limbs. - * - * This may be \c NULL if \c n is 0. - */ - mbedtls_mpi_uint *MBEDTLS_PRIVATE(p); - - /** Sign: -1 if the mpi is negative, 1 otherwise. - * - * The number 0 must be represented with `s = +1`. Although many library - * functions treat all-limbs-zero as equivalent to a valid representation - * of 0 regardless of the sign bit, there are exceptions, so bignum - * functions and external callers must always set \c s to +1 for the - * number zero. - * - * Note that this implies that calloc() or `... = {0}` does not create - * a valid MPI representation. You must call mbedtls_mpi_init(). - */ - signed short MBEDTLS_PRIVATE(s); - - /** Total number of limbs in \c p. */ - unsigned short MBEDTLS_PRIVATE(n); - /* Make sure that MBEDTLS_MPI_MAX_LIMBS fits in n. - * Use the same limit value on all platforms so that we don't have to - * think about different behavior on the rare platforms where - * unsigned short can store values larger than the minimum required by - * the C language, which is 65535. - */ -#if MBEDTLS_MPI_MAX_LIMBS > 65535 -#error "MBEDTLS_MPI_MAX_LIMBS > 65535 is not supported" -#endif -} -mbedtls_mpi; - -/** - * \brief Initialize an MPI context. - * - * This makes the MPI ready to be set or freed, - * but does not define a value for the MPI. - * - * \param X The MPI context to initialize. This must not be \c NULL. - */ -void mbedtls_mpi_init(mbedtls_mpi *X); - -/** - * \brief This function frees the components of an MPI context. - * - * \param X The MPI context to be cleared. This may be \c NULL, - * in which case this function is a no-op. If it is - * not \c NULL, it must point to an initialized MPI. - */ -void mbedtls_mpi_free(mbedtls_mpi *X); - -/** - * \brief Enlarge an MPI to the specified number of limbs. - * - * \note This function does nothing if the MPI is - * already large enough. - * - * \param X The MPI to grow. It must be initialized. - * \param nblimbs The target number of limbs. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_grow(mbedtls_mpi *X, size_t nblimbs); - -/** - * \brief This function resizes an MPI downwards, keeping at least the - * specified number of limbs. - * - * If \c X is smaller than \c nblimbs, it is resized up - * instead. - * - * \param X The MPI to shrink. This must point to an initialized MPI. - * \param nblimbs The minimum number of limbs to keep. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed - * (this can only happen when resizing up). - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_shrink(mbedtls_mpi *X, size_t nblimbs); - -/** - * \brief Make a copy of an MPI. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param Y The source MPI. This must point to an initialized MPI. - * - * \note The limb-buffer in the destination MPI is enlarged - * if necessary to hold the value in the source MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_copy(mbedtls_mpi *X, const mbedtls_mpi *Y); - -/** - * \brief Swap the contents of two MPIs. - * - * \param X The first MPI. It must be initialized. - * \param Y The second MPI. It must be initialized. - */ -void mbedtls_mpi_swap(mbedtls_mpi *X, mbedtls_mpi *Y); - -/** - * \brief Perform a safe conditional copy of MPI which doesn't - * reveal whether the condition was true or not. - * - * \param X The MPI to conditionally assign to. This must point - * to an initialized MPI. - * \param Y The MPI to be assigned from. This must point to an - * initialized MPI. - * \param assign The condition deciding whether to perform the - * assignment or not. Must be either 0 or 1: - * * \c 1: Perform the assignment `X = Y`. - * * \c 0: Keep the original value of \p X. - * - * \note This function is equivalent to - * `if( assign ) mbedtls_mpi_copy( X, Y );` - * except that it avoids leaking any information about whether - * the assignment was done or not (the above code may leak - * information through branch prediction and/or memory access - * patterns analysis). - * - * \warning If \p assign is neither 0 nor 1, the result of this function - * is indeterminate, and the resulting value in \p X might be - * neither its original value nor the value in \p Y. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_safe_cond_assign(mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign); - -/** - * \brief Perform a safe conditional swap which doesn't - * reveal whether the condition was true or not. - * - * \param X The first MPI. This must be initialized. - * \param Y The second MPI. This must be initialized. - * \param swap The condition deciding whether to perform - * the swap or not. Must be either 0 or 1: - * * \c 1: Swap the values of \p X and \p Y. - * * \c 0: Keep the original values of \p X and \p Y. - * - * \note This function is equivalent to - * if( swap ) mbedtls_mpi_swap( X, Y ); - * except that it avoids leaking any information about whether - * the swap was done or not (the above code may leak - * information through branch prediction and/or memory access - * patterns analysis). - * - * \warning If \p swap is neither 0 nor 1, the result of this function - * is indeterminate, and both \p X and \p Y might end up with - * values different to either of the original ones. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - * - */ -int mbedtls_mpi_safe_cond_swap(mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char swap); - -/** - * \brief Store integer value in MPI. - * - * \param X The MPI to set. This must be initialized. - * \param z The value to use. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_lset(mbedtls_mpi *X, mbedtls_mpi_sint z); - -/** - * \brief Get a specific bit from an MPI. - * - * \param X The MPI to query. This must be initialized. - * \param pos Zero-based index of the bit to query. - * - * \return \c 0 or \c 1 on success, depending on whether bit \c pos - * of \c X is unset or set. - * \return A negative error code on failure. - */ -int mbedtls_mpi_get_bit(const mbedtls_mpi *X, size_t pos); - -/** - * \brief Modify a specific bit in an MPI. - * - * \note This function will grow the target MPI if necessary to set a - * bit to \c 1 in a not yet existing limb. It will not grow if - * the bit should be set to \c 0. - * - * \param X The MPI to modify. This must be initialized. - * \param pos Zero-based index of the bit to modify. - * \param val The desired value of bit \c pos: \c 0 or \c 1. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_set_bit(mbedtls_mpi *X, size_t pos, unsigned char val); - -/** - * \brief Return the number of bits of value \c 0 before the - * least significant bit of value \c 1. - * - * \note This is the same as the zero-based index of - * the least significant bit of value \c 1. - * - * \param X The MPI to query. - * - * \return The number of bits of value \c 0 before the least significant - * bit of value \c 1 in \p X. - */ -size_t mbedtls_mpi_lsb(const mbedtls_mpi *X); - -/** - * \brief Return the number of bits up to and including the most - * significant bit of value \c 1. - * - * * \note This is same as the one-based index of the most - * significant bit of value \c 1. - * - * \param X The MPI to query. This must point to an initialized MPI. - * - * \return The number of bits up to and including the most - * significant bit of value \c 1. - */ -size_t mbedtls_mpi_bitlen(const mbedtls_mpi *X); - -/** - * \brief Return the total size of an MPI value in bytes. - * - * \param X The MPI to use. This must point to an initialized MPI. - * - * \note The value returned by this function may be less than - * the number of bytes used to store \p X internally. - * This happens if and only if there are trailing bytes - * of value zero. - * - * \return The least number of bytes capable of storing - * the absolute value of \p X. - */ -size_t mbedtls_mpi_size(const mbedtls_mpi *X); - -/** - * \brief Import an MPI from an ASCII string. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param radix The numeric base of the input string. - * \param s Null-terminated string buffer. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_mpi_read_string(mbedtls_mpi *X, int radix, const char *s); - -/** - * \brief Export an MPI to an ASCII string. - * - * \param X The source MPI. This must point to an initialized MPI. - * \param radix The numeric base of the output string. - * \param buf The buffer to write the string to. This must be writable - * buffer of length \p buflen Bytes. - * \param buflen The available size in Bytes of \p buf. - * \param olen The address at which to store the length of the string - * written, including the final \c NULL byte. This must - * not be \c NULL. - * - * \note You can call this function with `buflen == 0` to obtain the - * minimum required buffer size in `*olen`. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the target buffer \p buf - * is too small to hold the value of \p X in the desired base. - * In this case, `*olen` is nonetheless updated to contain the - * size of \p buf required for a successful call. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_write_string(const mbedtls_mpi *X, int radix, - char *buf, size_t buflen, size_t *olen); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief Read an MPI from a line in an opened file. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param radix The numeric base of the string representation used - * in the source line. - * \param fin The input file handle to use. This must not be \c NULL. - * - * \note On success, this function advances the file stream - * to the end of the current line or to EOF. - * - * The function returns \c 0 on an empty line. - * - * Leading whitespaces are ignored, as is a - * '0x' prefix for radix \c 16. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the file read buffer - * is too small. - * \return Another negative error code on failure. - */ -int mbedtls_mpi_read_file(mbedtls_mpi *X, int radix, FILE *fin); - -/** - * \brief Export an MPI into an opened file. - * - * \param p A string prefix to emit prior to the MPI data. - * For example, this might be a label, or "0x" when - * printing in base \c 16. This may be \c NULL if no prefix - * is needed. - * \param X The source MPI. This must point to an initialized MPI. - * \param radix The numeric base to be used in the emitted string. - * \param fout The output file handle. This may be \c NULL, in which case - * the output is written to \c stdout. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_mpi_write_file(const char *p, const mbedtls_mpi *X, - int radix, FILE *fout); -#endif /* MBEDTLS_FS_IO */ - -/** - * \brief Import an MPI from unsigned big endian binary data. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param buf The input buffer. This must be a readable buffer of length - * \p buflen Bytes. - * \param buflen The length of the input buffer \p buf in Bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_read_binary(mbedtls_mpi *X, const unsigned char *buf, - size_t buflen); - -/** - * \brief Import X from unsigned binary data, little endian - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param buf The input buffer. This must be a readable buffer of length - * \p buflen Bytes. - * \param buflen The length of the input buffer \p buf in Bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_read_binary_le(mbedtls_mpi *X, - const unsigned char *buf, size_t buflen); - -/** - * \brief Export X into unsigned binary data, big endian. - * Always fills the whole buffer, which will start with zeros - * if the number is smaller. - * - * \param X The source MPI. This must point to an initialized MPI. - * \param buf The output buffer. This must be a writable buffer of length - * \p buflen Bytes. - * \param buflen The size of the output buffer \p buf in Bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't - * large enough to hold the value of \p X. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_write_binary(const mbedtls_mpi *X, unsigned char *buf, - size_t buflen); - -/** - * \brief Export X into unsigned binary data, little endian. - * Always fills the whole buffer, which will end with zeros - * if the number is smaller. - * - * \param X The source MPI. This must point to an initialized MPI. - * \param buf The output buffer. This must be a writable buffer of length - * \p buflen Bytes. - * \param buflen The size of the output buffer \p buf in Bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't - * large enough to hold the value of \p X. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_write_binary_le(const mbedtls_mpi *X, - unsigned char *buf, size_t buflen); - -/** - * \brief Perform a left-shift on an MPI: X <<= count - * - * \param X The MPI to shift. This must point to an initialized MPI. - * The MPI pointed by \p X may be resized to fit - * the resulting number. - * \param count The number of bits to shift by. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_shift_l(mbedtls_mpi *X, size_t count); - -/** - * \brief Perform a right-shift on an MPI: X >>= count - * - * \param X The MPI to shift. This must point to an initialized MPI. - * \param count The number of bits to shift by. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_shift_r(mbedtls_mpi *X, size_t count); - -/** - * \brief Compare the absolute values of two MPIs. - * - * \param X The left-hand MPI. This must point to an initialized MPI. - * \param Y The right-hand MPI. This must point to an initialized MPI. - * - * \return \c 1 if `|X|` is greater than `|Y|`. - * \return \c -1 if `|X|` is lesser than `|Y|`. - * \return \c 0 if `|X|` is equal to `|Y|`. - */ -int mbedtls_mpi_cmp_abs(const mbedtls_mpi *X, const mbedtls_mpi *Y); - -/** - * \brief Compare two MPIs. - * - * \param X The left-hand MPI. This must point to an initialized MPI. - * \param Y The right-hand MPI. This must point to an initialized MPI. - * - * \return \c 1 if \p X is greater than \p Y. - * \return \c -1 if \p X is lesser than \p Y. - * \return \c 0 if \p X is equal to \p Y. - */ -int mbedtls_mpi_cmp_mpi(const mbedtls_mpi *X, const mbedtls_mpi *Y); - -/** - * \brief Check if an MPI is less than the other in constant time. - * - * \param X The left-hand MPI. This must point to an initialized MPI - * with the same allocated length as Y. - * \param Y The right-hand MPI. This must point to an initialized MPI - * with the same allocated length as X. - * \param ret The result of the comparison: - * \c 1 if \p X is less than \p Y. - * \c 0 if \p X is greater than or equal to \p Y. - * - * \return 0 on success. - * \return MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the allocated length of - * the two input MPIs is not the same. - */ -int mbedtls_mpi_lt_mpi_ct(const mbedtls_mpi *X, const mbedtls_mpi *Y, - unsigned *ret); - -/** - * \brief Compare an MPI with an integer. - * - * \param X The left-hand MPI. This must point to an initialized MPI. - * \param z The integer value to compare \p X to. - * - * \return \c 1 if \p X is greater than \p z. - * \return \c -1 if \p X is lesser than \p z. - * \return \c 0 if \p X is equal to \p z. - */ -int mbedtls_mpi_cmp_int(const mbedtls_mpi *X, mbedtls_mpi_sint z); - -/** - * \brief Perform an unsigned addition of MPIs: X = |A| + |B| - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The first summand. This must point to an initialized MPI. - * \param B The second summand. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_add_abs(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform an unsigned subtraction of MPIs: X = |A| - |B| - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The minuend. This must point to an initialized MPI. - * \param B The subtrahend. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is greater than \p A. - * \return Another negative error code on different kinds of failure. - * - */ -int mbedtls_mpi_sub_abs(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a signed addition of MPIs: X = A + B - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The first summand. This must point to an initialized MPI. - * \param B The second summand. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_add_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a signed subtraction of MPIs: X = A - B - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The minuend. This must point to an initialized MPI. - * \param B The subtrahend. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_sub_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a signed addition of an MPI and an integer: X = A + b - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The first summand. This must point to an initialized MPI. - * \param b The second summand. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_add_int(mbedtls_mpi *X, const mbedtls_mpi *A, - mbedtls_mpi_sint b); - -/** - * \brief Perform a signed subtraction of an MPI and an integer: - * X = A - b - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The minuend. This must point to an initialized MPI. - * \param b The subtrahend. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_sub_int(mbedtls_mpi *X, const mbedtls_mpi *A, - mbedtls_mpi_sint b); - -/** - * \brief Perform a multiplication of two MPIs: X = A * B - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The first factor. This must point to an initialized MPI. - * \param B The second factor. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - * - */ -int mbedtls_mpi_mul_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a multiplication of an MPI with an unsigned integer: - * X = A * b - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The first factor. This must point to an initialized MPI. - * \param b The second factor. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - * - */ -int mbedtls_mpi_mul_int(mbedtls_mpi *X, const mbedtls_mpi *A, - mbedtls_mpi_uint b); - -/** - * \brief Perform a division with remainder of two MPIs: - * A = Q * B + R - * - * \param Q The destination MPI for the quotient. - * This may be \c NULL if the value of the - * quotient is not needed. This must not alias A or B. - * \param R The destination MPI for the remainder value. - * This may be \c NULL if the value of the - * remainder is not needed. This must not alias A or B. - * \param A The dividend. This must point to an initialized MPI. - * \param B The divisor. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_div_mpi(mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a division with remainder of an MPI by an integer: - * A = Q * b + R - * - * \param Q The destination MPI for the quotient. - * This may be \c NULL if the value of the - * quotient is not needed. This must not alias A. - * \param R The destination MPI for the remainder value. - * This may be \c NULL if the value of the - * remainder is not needed. This must not alias A. - * \param A The dividend. This must point to an initialized MPi. - * \param b The divisor. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_div_int(mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, - mbedtls_mpi_sint b); - -/** - * \brief Perform a modular reduction. R = A mod B - * - * \param R The destination MPI for the residue value. - * This must point to an initialized MPI. - * \param A The MPI to compute the residue of. - * This must point to an initialized MPI. - * \param B The base of the modular reduction. - * This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. - * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is negative. - * \return Another negative error code on different kinds of failure. - * - */ -int mbedtls_mpi_mod_mpi(mbedtls_mpi *R, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Perform a modular reduction with respect to an integer. - * r = A mod b - * - * \param r The address at which to store the residue. - * This must not be \c NULL. - * \param A The MPI to compute the residue of. - * This must point to an initialized MPi. - * \param b The integer base of the modular reduction. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. - * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p b is negative. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_mod_int(mbedtls_mpi_uint *r, const mbedtls_mpi *A, - mbedtls_mpi_sint b); - -/** - * \brief Perform a sliding-window exponentiation: X = A^E mod N - * - * \param X The destination MPI. This must point to an initialized MPI. - * This must not alias E or N. - * \param A The base of the exponentiation. - * This must point to an initialized MPI. - * \param E The exponent MPI. This must point to an initialized MPI. - * \param N The base for the modular reduction. This must point to an - * initialized MPI. - * \param prec_RR A helper MPI depending solely on \p N which can be used to - * speed-up multiple modular exponentiations for the same value - * of \p N. This may be \c NULL. If it is not \c NULL, it must - * point to an initialized MPI. If it hasn't been used after - * the call to mbedtls_mpi_init(), this function will compute - * the helper value and store it in \p prec_RR for reuse on - * subsequent calls to this function. Otherwise, the function - * will assume that \p prec_RR holds the helper value set by a - * previous call to mbedtls_mpi_exp_mod(), and reuse it. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \c N is negative or - * even, or if \c E is negative. - * \return Another negative error code on different kinds of failures. - * - */ -int mbedtls_mpi_exp_mod(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *E, const mbedtls_mpi *N, - mbedtls_mpi *prec_RR); - -/** - * \brief Fill an MPI with a number of random bytes. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param size The number of random bytes to generate. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on failure. - * - * \note The bytes obtained from the RNG are interpreted - * as a big-endian representation of an MPI; this can - * be relevant in applications like deterministic ECDSA. - */ -int mbedtls_mpi_fill_random(mbedtls_mpi *X, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** Generate a random number uniformly in a range. - * - * This function generates a random number between \p min inclusive and - * \p N exclusive. - * - * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) - * when the RNG is a suitably parametrized instance of HMAC_DRBG - * and \p min is \c 1. - * - * \note There are `N - min` possible outputs. The lower bound - * \p min can be reached, but the upper bound \p N cannot. - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param min The minimum value to return. - * It must be nonnegative. - * \param N The upper bound of the range, exclusive. - * In other words, this is one plus the maximum value to return. - * \p N must be strictly larger than \p min. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p min or \p N is invalid - * or if they are incompatible. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was - * unable to find a suitable value within a limited number - * of attempts. This has a negligible probability if \p N - * is significantly larger than \p min, which is the case - * for all usual cryptographic applications. - * \return Another negative error code on failure. - */ -int mbedtls_mpi_random(mbedtls_mpi *X, - mbedtls_mpi_sint min, - const mbedtls_mpi *N, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Compute the greatest common divisor: G = gcd(A, B) - * - * \param G The destination MPI. This must point to an initialized MPI. - * \param A The first operand. This must point to an initialized MPI. - * \param B The second operand. This must point to an initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_mpi_gcd(mbedtls_mpi *G, const mbedtls_mpi *A, - const mbedtls_mpi *B); - -/** - * \brief Compute the modular inverse: X = A^-1 mod N - * - * \param X The destination MPI. This must point to an initialized MPI. - * \param A The MPI to calculate the modular inverse of. This must point - * to an initialized MPI. - * \param N The base of the modular inversion. This must point to an - * initialized MPI. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p N is less than - * or equal to one. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p A has no modular - * inverse with respect to \p N. - */ -int mbedtls_mpi_inv_mod(mbedtls_mpi *X, const mbedtls_mpi *A, - const mbedtls_mpi *N); - -/** - * \brief Miller-Rabin primality test. - * - * \warning If \p X is potentially generated by an adversary, for example - * when validating cryptographic parameters that you didn't - * generate yourself and that are supposed to be prime, then - * \p rounds should be at least the half of the security - * strength of the cryptographic algorithm. On the other hand, - * if \p X is chosen uniformly or non-adversarially (as is the - * case when mbedtls_mpi_gen_prime calls this function), then - * \p rounds can be much lower. - * - * \param X The MPI to check for primality. - * This must point to an initialized MPI. - * \param rounds The number of bases to perform the Miller-Rabin primality - * test for. The probability of returning 0 on a composite is - * at most 2^-2*\p rounds. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * This may be \c NULL if \p f_rng doesn't use - * a context parameter. - * - * \return \c 0 if successful, i.e. \p X is probably prime. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_mpi_is_prime_ext(const mbedtls_mpi *X, int rounds, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); -/** - * \brief Flags for mbedtls_mpi_gen_prime() - * - * Each of these flags is a constraint on the result X returned by - * mbedtls_mpi_gen_prime(). - */ -typedef enum { - MBEDTLS_MPI_GEN_PRIME_FLAG_DH = 0x0001, /**< (X-1)/2 is prime too */ - MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR = 0x0002, /**< lower error rate from 2-80 to 2-128 */ -} mbedtls_mpi_gen_prime_flag_t; - -/** - * \brief Generate a prime number. - * - * \param X The destination MPI to store the generated prime in. - * This must point to an initialized MPi. - * \param nbits The required size of the destination MPI in bits. - * This must be between \c 3 and #MBEDTLS_MPI_MAX_BITS. - * \param flags A mask of flags of type #mbedtls_mpi_gen_prime_flag_t. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * This may be \c NULL if \p f_rng doesn't use - * a context parameter. - * - * \return \c 0 if successful, in which case \p X holds a - * probably prime number. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if `nbits` is not between - * \c 3 and #MBEDTLS_MPI_MAX_BITS. - */ -int mbedtls_mpi_gen_prime(mbedtls_mpi *X, size_t nbits, int flags, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int mbedtls_mpi_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* bignum.h */ +/** + * \file bignum.h + * + * \brief Multi-precision integer library + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_BIGNUM_H +#define MBEDTLS_BIGNUM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#if defined(MBEDTLS_FS_IO) +#include +#endif + +/** An error occurred while reading from or writing to a file. */ +#define MBEDTLS_ERR_MPI_FILE_IO_ERROR -0x0002 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_MPI_BAD_INPUT_DATA -0x0004 +/** There is an invalid character in the digit string. */ +#define MBEDTLS_ERR_MPI_INVALID_CHARACTER -0x0006 +/** The buffer is too small to write to. */ +#define MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL -0x0008 +/** The input arguments are negative or result in illegal output. */ +#define MBEDTLS_ERR_MPI_NEGATIVE_VALUE -0x000A +/** The input argument for division is zero, which is not allowed. */ +#define MBEDTLS_ERR_MPI_DIVISION_BY_ZERO -0x000C +/** The input arguments are not acceptable. */ +#define MBEDTLS_ERR_MPI_NOT_ACCEPTABLE -0x000E +/** Memory allocation failed. */ +#define MBEDTLS_ERR_MPI_ALLOC_FAILED -0x0010 + +#define MBEDTLS_MPI_CHK(f) \ + do \ + { \ + if ((ret = (f)) != 0) \ + goto cleanup; \ + } while (0) + +/* + * Maximum size MPIs are allowed to grow to in number of limbs. + */ +#define MBEDTLS_MPI_MAX_LIMBS 10000 + +#if !defined(MBEDTLS_MPI_WINDOW_SIZE) +/* + * Maximum window size used for modular exponentiation. Default: 2 + * Minimum value: 1. Maximum value: 6. + * + * Result is an array of ( 2 ** MBEDTLS_MPI_WINDOW_SIZE ) MPIs used + * for the sliding window calculation. (So 64 by default) + * + * Reduction in size, reduces speed. + */ +#define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ +#endif /* !MBEDTLS_MPI_WINDOW_SIZE */ + +#if !defined(MBEDTLS_MPI_MAX_SIZE) +/* + * Maximum size of MPIs allowed in bits and bytes for user-MPIs. + * ( Default: 512 bytes => 4096 bits, Maximum tested: 2048 bytes => 16384 bits ) + * + * Note: Calculations can temporarily result in larger MPIs. So the number + * of limbs required (MBEDTLS_MPI_MAX_LIMBS) is higher. + */ +#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ +#endif /* !MBEDTLS_MPI_MAX_SIZE */ + +#define MBEDTLS_MPI_MAX_BITS (8 * MBEDTLS_MPI_MAX_SIZE) /**< Maximum number of bits for usable MPIs. */ + +/* + * When reading from files with mbedtls_mpi_read_file() and writing to files with + * mbedtls_mpi_write_file() the buffer should have space + * for a (short) label, the MPI (in the provided radix), the newline + * characters and the '\0'. + * + * By default we assume at least a 10 char label, a minimum radix of 10 + * (decimal) and a maximum of 4096 bit numbers (1234 decimal chars). + * Autosized at compile time for at least a 10 char label, a minimum radix + * of 10 (decimal) for a number of MBEDTLS_MPI_MAX_BITS size. + * + * This used to be statically sized to 1250 for a maximum of 4096 bit + * numbers (1234 decimal chars). + * + * Calculate using the formula: + * MBEDTLS_MPI_RW_BUFFER_SIZE = ceil(MBEDTLS_MPI_MAX_BITS / ln(10) * ln(2)) + + * LabelSize + 6 + */ +#define MBEDTLS_MPI_MAX_BITS_SCALE100 (100 * MBEDTLS_MPI_MAX_BITS) +#define MBEDTLS_LN_2_DIV_LN_10_SCALE100 332 +#define MBEDTLS_MPI_RW_BUFFER_SIZE (((MBEDTLS_MPI_MAX_BITS_SCALE100 + \ + MBEDTLS_LN_2_DIV_LN_10_SCALE100 - 1) / \ + MBEDTLS_LN_2_DIV_LN_10_SCALE100) + 10 + 6) + +/* + * Define the base integer type, architecture-wise. + * + * 32 or 64-bit integer types can be forced regardless of the underlying + * architecture by defining MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64 + * respectively and undefining MBEDTLS_HAVE_ASM. + * + * Double-width integers (e.g. 128-bit in 64-bit architectures) can be + * disabled by defining MBEDTLS_NO_UDBL_DIVISION. + */ +#if !defined(MBEDTLS_HAVE_INT32) + #if defined(_MSC_VER) && defined(_M_AMD64) +/* Always choose 64-bit when using MSC */ + #if !defined(MBEDTLS_HAVE_INT64) + #define MBEDTLS_HAVE_INT64 + #endif /* !MBEDTLS_HAVE_INT64 */ +typedef int64_t mbedtls_mpi_sint; +typedef uint64_t mbedtls_mpi_uint; +#define MBEDTLS_MPI_UINT_MAX UINT64_MAX + #elif defined(__GNUC__) && ( \ + defined(__amd64__) || defined(__x86_64__) || \ + defined(__ppc64__) || defined(__powerpc64__) || \ + defined(__ia64__) || defined(__alpha__) || \ + (defined(__sparc__) && defined(__arch64__)) || \ + defined(__s390x__) || defined(__mips64) || \ + defined(__aarch64__)) + #if !defined(MBEDTLS_HAVE_INT64) + #define MBEDTLS_HAVE_INT64 + #endif /* MBEDTLS_HAVE_INT64 */ +typedef int64_t mbedtls_mpi_sint; +typedef uint64_t mbedtls_mpi_uint; +#define MBEDTLS_MPI_UINT_MAX UINT64_MAX + #if !defined(MBEDTLS_NO_UDBL_DIVISION) +/* mbedtls_t_udbl defined as 128-bit unsigned int */ +typedef unsigned int mbedtls_t_udbl __attribute__((mode(TI))); + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ + #elif defined(__ARMCC_VERSION) && defined(__aarch64__) +/* + * __ARMCC_VERSION is defined for both armcc and armclang and + * __aarch64__ is only defined by armclang when compiling 64-bit code + */ + #if !defined(MBEDTLS_HAVE_INT64) + #define MBEDTLS_HAVE_INT64 + #endif /* !MBEDTLS_HAVE_INT64 */ +typedef int64_t mbedtls_mpi_sint; +typedef uint64_t mbedtls_mpi_uint; +#define MBEDTLS_MPI_UINT_MAX UINT64_MAX + #if !defined(MBEDTLS_NO_UDBL_DIVISION) +/* mbedtls_t_udbl defined as 128-bit unsigned int */ +typedef __uint128_t mbedtls_t_udbl; + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ + #elif defined(MBEDTLS_HAVE_INT64) +/* Force 64-bit integers with unknown compiler */ +typedef int64_t mbedtls_mpi_sint; +typedef uint64_t mbedtls_mpi_uint; +#define MBEDTLS_MPI_UINT_MAX UINT64_MAX + #endif +#endif /* !MBEDTLS_HAVE_INT32 */ + +#if !defined(MBEDTLS_HAVE_INT64) +/* Default to 32-bit compilation */ + #if !defined(MBEDTLS_HAVE_INT32) + #define MBEDTLS_HAVE_INT32 + #endif /* !MBEDTLS_HAVE_INT32 */ +typedef int32_t mbedtls_mpi_sint; +typedef uint32_t mbedtls_mpi_uint; +#define MBEDTLS_MPI_UINT_MAX UINT32_MAX + #if !defined(MBEDTLS_NO_UDBL_DIVISION) +typedef uint64_t mbedtls_t_udbl; + #define MBEDTLS_HAVE_UDBL + #endif /* !MBEDTLS_NO_UDBL_DIVISION */ +#endif /* !MBEDTLS_HAVE_INT64 */ + +/* + * Sanity check that exactly one of MBEDTLS_HAVE_INT32 or MBEDTLS_HAVE_INT64 is defined, + * so that code elsewhere doesn't have to check. + */ +#if (!(defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64))) || \ + (defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64)) +#error "Only 32-bit or 64-bit limbs are supported in bignum" +#endif + +/** \typedef mbedtls_mpi_uint + * \brief The type of machine digits in a bignum, called _limbs_. + * + * This is always an unsigned integer type with no padding bits. The size + * is platform-dependent. + */ + +/** \typedef mbedtls_mpi_sint + * \brief The signed type corresponding to #mbedtls_mpi_uint. + * + * This is always an signed integer type with no padding bits. The size + * is platform-dependent. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief MPI structure + */ +typedef struct mbedtls_mpi { + /** Pointer to limbs. + * + * This may be \c NULL if \c n is 0. + */ + mbedtls_mpi_uint *MBEDTLS_PRIVATE(p); + + /** Sign: -1 if the mpi is negative, 1 otherwise. + * + * The number 0 must be represented with `s = +1`. Although many library + * functions treat all-limbs-zero as equivalent to a valid representation + * of 0 regardless of the sign bit, there are exceptions, so bignum + * functions and external callers must always set \c s to +1 for the + * number zero. + * + * Note that this implies that calloc() or `... = {0}` does not create + * a valid MPI representation. You must call mbedtls_mpi_init(). + */ + signed short MBEDTLS_PRIVATE(s); + + /** Total number of limbs in \c p. */ + unsigned short MBEDTLS_PRIVATE(n); + /* Make sure that MBEDTLS_MPI_MAX_LIMBS fits in n. + * Use the same limit value on all platforms so that we don't have to + * think about different behavior on the rare platforms where + * unsigned short can store values larger than the minimum required by + * the C language, which is 65535. + */ +#if MBEDTLS_MPI_MAX_LIMBS > 65535 +#error "MBEDTLS_MPI_MAX_LIMBS > 65535 is not supported" +#endif +} +mbedtls_mpi; + +/** + * \brief Initialize an MPI context. + * + * This makes the MPI ready to be set or freed, + * but does not define a value for the MPI. + * + * \param X The MPI context to initialize. This must not be \c NULL. + */ +void mbedtls_mpi_init(mbedtls_mpi *X); + +/** + * \brief This function frees the components of an MPI context. + * + * \param X The MPI context to be cleared. This may be \c NULL, + * in which case this function is a no-op. If it is + * not \c NULL, it must point to an initialized MPI. + */ +void mbedtls_mpi_free(mbedtls_mpi *X); + +/** + * \brief Enlarge an MPI to the specified number of limbs. + * + * \note This function does nothing if the MPI is + * already large enough. + * + * \param X The MPI to grow. It must be initialized. + * \param nblimbs The target number of limbs. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_grow(mbedtls_mpi *X, size_t nblimbs); + +/** + * \brief This function resizes an MPI downwards, keeping at least the + * specified number of limbs. + * + * If \c X is smaller than \c nblimbs, it is resized up + * instead. + * + * \param X The MPI to shrink. This must point to an initialized MPI. + * \param nblimbs The minimum number of limbs to keep. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed + * (this can only happen when resizing up). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_shrink(mbedtls_mpi *X, size_t nblimbs); + +/** + * \brief Make a copy of an MPI. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param Y The source MPI. This must point to an initialized MPI. + * + * \note The limb-buffer in the destination MPI is enlarged + * if necessary to hold the value in the source MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_copy(mbedtls_mpi *X, const mbedtls_mpi *Y); + +/** + * \brief Swap the contents of two MPIs. + * + * \param X The first MPI. It must be initialized. + * \param Y The second MPI. It must be initialized. + */ +void mbedtls_mpi_swap(mbedtls_mpi *X, mbedtls_mpi *Y); + +/** + * \brief Perform a safe conditional copy of MPI which doesn't + * reveal whether the condition was true or not. + * + * \param X The MPI to conditionally assign to. This must point + * to an initialized MPI. + * \param Y The MPI to be assigned from. This must point to an + * initialized MPI. + * \param assign The condition deciding whether to perform the + * assignment or not. Must be either 0 or 1: + * * \c 1: Perform the assignment `X = Y`. + * * \c 0: Keep the original value of \p X. + * + * \note This function is equivalent to + * `if( assign ) mbedtls_mpi_copy( X, Y );` + * except that it avoids leaking any information about whether + * the assignment was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + * + * \warning If \p assign is neither 0 nor 1, the result of this function + * is indeterminate, and the resulting value in \p X might be + * neither its original value nor the value in \p Y. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_safe_cond_assign(mbedtls_mpi *X, const mbedtls_mpi *Y, unsigned char assign); + +/** + * \brief Perform a safe conditional swap which doesn't + * reveal whether the condition was true or not. + * + * \param X The first MPI. This must be initialized. + * \param Y The second MPI. This must be initialized. + * \param swap The condition deciding whether to perform + * the swap or not. Must be either 0 or 1: + * * \c 1: Swap the values of \p X and \p Y. + * * \c 0: Keep the original values of \p X and \p Y. + * + * \note This function is equivalent to + * if( swap ) mbedtls_mpi_swap( X, Y ); + * except that it avoids leaking any information about whether + * the swap was done or not (the above code may leak + * information through branch prediction and/or memory access + * patterns analysis). + * + * \warning If \p swap is neither 0 nor 1, the result of this function + * is indeterminate, and both \p X and \p Y might end up with + * values different to either of the original ones. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + * + */ +int mbedtls_mpi_safe_cond_swap(mbedtls_mpi *X, mbedtls_mpi *Y, unsigned char swap); + +/** + * \brief Store integer value in MPI. + * + * \param X The MPI to set. This must be initialized. + * \param z The value to use. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_lset(mbedtls_mpi *X, mbedtls_mpi_sint z); + +/** + * \brief Get a specific bit from an MPI. + * + * \param X The MPI to query. This must be initialized. + * \param pos Zero-based index of the bit to query. + * + * \return \c 0 or \c 1 on success, depending on whether bit \c pos + * of \c X is unset or set. + * \return A negative error code on failure. + */ +int mbedtls_mpi_get_bit(const mbedtls_mpi *X, size_t pos); + +/** + * \brief Modify a specific bit in an MPI. + * + * \note This function will grow the target MPI if necessary to set a + * bit to \c 1 in a not yet existing limb. It will not grow if + * the bit should be set to \c 0. + * + * \param X The MPI to modify. This must be initialized. + * \param pos Zero-based index of the bit to modify. + * \param val The desired value of bit \c pos: \c 0 or \c 1. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_set_bit(mbedtls_mpi *X, size_t pos, unsigned char val); + +/** + * \brief Return the number of bits of value \c 0 before the + * least significant bit of value \c 1. + * + * \note This is the same as the zero-based index of + * the least significant bit of value \c 1. + * + * \param X The MPI to query. + * + * \return The number of bits of value \c 0 before the least significant + * bit of value \c 1 in \p X. + */ +size_t mbedtls_mpi_lsb(const mbedtls_mpi *X); + +/** + * \brief Return the number of bits up to and including the most + * significant bit of value \c 1. + * + * * \note This is same as the one-based index of the most + * significant bit of value \c 1. + * + * \param X The MPI to query. This must point to an initialized MPI. + * + * \return The number of bits up to and including the most + * significant bit of value \c 1. + */ +size_t mbedtls_mpi_bitlen(const mbedtls_mpi *X); + +/** + * \brief Return the total size of an MPI value in bytes. + * + * \param X The MPI to use. This must point to an initialized MPI. + * + * \note The value returned by this function may be less than + * the number of bytes used to store \p X internally. + * This happens if and only if there are trailing bytes + * of value zero. + * + * \return The least number of bytes capable of storing + * the absolute value of \p X. + */ +size_t mbedtls_mpi_size(const mbedtls_mpi *X); + +/** + * \brief Import an MPI from an ASCII string. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param radix The numeric base of the input string. + * \param s Null-terminated string buffer. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_mpi_read_string(mbedtls_mpi *X, int radix, const char *s); + +/** + * \brief Export an MPI to an ASCII string. + * + * \param X The source MPI. This must point to an initialized MPI. + * \param radix The numeric base of the output string. + * \param buf The buffer to write the string to. This must be writable + * buffer of length \p buflen Bytes. + * \param buflen The available size in Bytes of \p buf. + * \param olen The address at which to store the length of the string + * written, including the final \c NULL byte. This must + * not be \c NULL. + * + * \note You can call this function with `buflen == 0` to obtain the + * minimum required buffer size in `*olen`. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the target buffer \p buf + * is too small to hold the value of \p X in the desired base. + * In this case, `*olen` is nonetheless updated to contain the + * size of \p buf required for a successful call. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_write_string(const mbedtls_mpi *X, int radix, + char *buf, size_t buflen, size_t *olen); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Read an MPI from a line in an opened file. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param radix The numeric base of the string representation used + * in the source line. + * \param fin The input file handle to use. This must not be \c NULL. + * + * \note On success, this function advances the file stream + * to the end of the current line or to EOF. + * + * The function returns \c 0 on an empty line. + * + * Leading whitespaces are ignored, as is a + * '0x' prefix for radix \c 16. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if the file read buffer + * is too small. + * \return Another negative error code on failure. + */ +int mbedtls_mpi_read_file(mbedtls_mpi *X, int radix, FILE *fin); + +/** + * \brief Export an MPI into an opened file. + * + * \param p A string prefix to emit prior to the MPI data. + * For example, this might be a label, or "0x" when + * printing in base \c 16. This may be \c NULL if no prefix + * is needed. + * \param X The source MPI. This must point to an initialized MPI. + * \param radix The numeric base to be used in the emitted string. + * \param fout The output file handle. This may be \c NULL, in which case + * the output is written to \c stdout. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_mpi_write_file(const char *p, const mbedtls_mpi *X, + int radix, FILE *fout); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief Import an MPI from unsigned big endian binary data. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param buf The input buffer. This must be a readable buffer of length + * \p buflen Bytes. + * \param buflen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_read_binary(mbedtls_mpi *X, const unsigned char *buf, + size_t buflen); + +/** + * \brief Import X from unsigned binary data, little endian + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param buf The input buffer. This must be a readable buffer of length + * \p buflen Bytes. + * \param buflen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_read_binary_le(mbedtls_mpi *X, + const unsigned char *buf, size_t buflen); + +/** + * \brief Export X into unsigned binary data, big endian. + * Always fills the whole buffer, which will start with zeros + * if the number is smaller. + * + * \param X The source MPI. This must point to an initialized MPI. + * \param buf The output buffer. This must be a writable buffer of length + * \p buflen Bytes. + * \param buflen The size of the output buffer \p buf in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't + * large enough to hold the value of \p X. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_write_binary(const mbedtls_mpi *X, unsigned char *buf, + size_t buflen); + +/** + * \brief Export X into unsigned binary data, little endian. + * Always fills the whole buffer, which will end with zeros + * if the number is smaller. + * + * \param X The source MPI. This must point to an initialized MPI. + * \param buf The output buffer. This must be a writable buffer of length + * \p buflen Bytes. + * \param buflen The size of the output buffer \p buf in Bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't + * large enough to hold the value of \p X. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_write_binary_le(const mbedtls_mpi *X, + unsigned char *buf, size_t buflen); + +/** + * \brief Perform a left-shift on an MPI: X <<= count + * + * \param X The MPI to shift. This must point to an initialized MPI. + * The MPI pointed by \p X may be resized to fit + * the resulting number. + * \param count The number of bits to shift by. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_shift_l(mbedtls_mpi *X, size_t count); + +/** + * \brief Perform a right-shift on an MPI: X >>= count + * + * \param X The MPI to shift. This must point to an initialized MPI. + * \param count The number of bits to shift by. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_shift_r(mbedtls_mpi *X, size_t count); + +/** + * \brief Compare the absolute values of two MPIs. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param Y The right-hand MPI. This must point to an initialized MPI. + * + * \return \c 1 if `|X|` is greater than `|Y|`. + * \return \c -1 if `|X|` is lesser than `|Y|`. + * \return \c 0 if `|X|` is equal to `|Y|`. + */ +int mbedtls_mpi_cmp_abs(const mbedtls_mpi *X, const mbedtls_mpi *Y); + +/** + * \brief Compare two MPIs. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param Y The right-hand MPI. This must point to an initialized MPI. + * + * \return \c 1 if \p X is greater than \p Y. + * \return \c -1 if \p X is lesser than \p Y. + * \return \c 0 if \p X is equal to \p Y. + */ +int mbedtls_mpi_cmp_mpi(const mbedtls_mpi *X, const mbedtls_mpi *Y); + +/** + * \brief Check if an MPI is less than the other in constant time. + * + * \param X The left-hand MPI. This must point to an initialized MPI + * with the same allocated length as Y. + * \param Y The right-hand MPI. This must point to an initialized MPI + * with the same allocated length as X. + * \param ret The result of the comparison: + * \c 1 if \p X is less than \p Y. + * \c 0 if \p X is greater than or equal to \p Y. + * + * \return 0 on success. + * \return MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the allocated length of + * the two input MPIs is not the same. + */ +int mbedtls_mpi_lt_mpi_ct(const mbedtls_mpi *X, const mbedtls_mpi *Y, + unsigned *ret); + +/** + * \brief Compare an MPI with an integer. + * + * \param X The left-hand MPI. This must point to an initialized MPI. + * \param z The integer value to compare \p X to. + * + * \return \c 1 if \p X is greater than \p z. + * \return \c -1 if \p X is lesser than \p z. + * \return \c 0 if \p X is equal to \p z. + */ +int mbedtls_mpi_cmp_int(const mbedtls_mpi *X, mbedtls_mpi_sint z); + +/** + * \brief Perform an unsigned addition of MPIs: X = |A| + |B| + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param B The second summand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_abs(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform an unsigned subtraction of MPIs: X = |A| - |B| + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param B The subtrahend. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is greater than \p A. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_sub_abs(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a signed addition of MPIs: X = A + B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param B The second summand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a signed subtraction of MPIs: X = A - B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param B The subtrahend. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_sub_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a signed addition of an MPI and an integer: X = A + b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first summand. This must point to an initialized MPI. + * \param b The second summand. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_add_int(mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_sint b); + +/** + * \brief Perform a signed subtraction of an MPI and an integer: + * X = A - b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The minuend. This must point to an initialized MPI. + * \param b The subtrahend. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_sub_int(mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_sint b); + +/** + * \brief Perform a multiplication of two MPIs: X = A * B + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first factor. This must point to an initialized MPI. + * \param B The second factor. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mul_mpi(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a multiplication of an MPI with an unsigned integer: + * X = A * b + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The first factor. This must point to an initialized MPI. + * \param b The second factor. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mul_int(mbedtls_mpi *X, const mbedtls_mpi *A, + mbedtls_mpi_uint b); + +/** + * \brief Perform a division with remainder of two MPIs: + * A = Q * B + R + * + * \param Q The destination MPI for the quotient. + * This may be \c NULL if the value of the + * quotient is not needed. This must not alias A or B. + * \param R The destination MPI for the remainder value. + * This may be \c NULL if the value of the + * remainder is not needed. This must not alias A or B. + * \param A The dividend. This must point to an initialized MPI. + * \param B The divisor. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_div_mpi(mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a division with remainder of an MPI by an integer: + * A = Q * b + R + * + * \param Q The destination MPI for the quotient. + * This may be \c NULL if the value of the + * quotient is not needed. This must not alias A. + * \param R The destination MPI for the remainder value. + * This may be \c NULL if the value of the + * remainder is not needed. This must not alias A. + * \param A The dividend. This must point to an initialized MPi. + * \param b The divisor. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_div_int(mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, + mbedtls_mpi_sint b); + +/** + * \brief Perform a modular reduction. R = A mod B + * + * \param R The destination MPI for the residue value. + * This must point to an initialized MPI. + * \param A The MPI to compute the residue of. + * This must point to an initialized MPI. + * \param B The base of the modular reduction. + * This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p B equals zero. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p B is negative. + * \return Another negative error code on different kinds of failure. + * + */ +int mbedtls_mpi_mod_mpi(mbedtls_mpi *R, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Perform a modular reduction with respect to an integer. + * r = A mod b + * + * \param r The address at which to store the residue. + * This must not be \c NULL. + * \param A The MPI to compute the residue of. + * This must point to an initialized MPi. + * \param b The integer base of the modular reduction. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p b equals zero. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p b is negative. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_mod_int(mbedtls_mpi_uint *r, const mbedtls_mpi *A, + mbedtls_mpi_sint b); + +/** + * \brief Perform a sliding-window exponentiation: X = A^E mod N + * + * \param X The destination MPI. This must point to an initialized MPI. + * This must not alias E or N. + * \param A The base of the exponentiation. + * This must point to an initialized MPI. + * \param E The exponent MPI. This must point to an initialized MPI. + * \param N The base for the modular reduction. This must point to an + * initialized MPI. + * \param prec_RR A helper MPI depending solely on \p N which can be used to + * speed-up multiple modular exponentiations for the same value + * of \p N. This may be \c NULL. If it is not \c NULL, it must + * point to an initialized MPI. If it hasn't been used after + * the call to mbedtls_mpi_init(), this function will compute + * the helper value and store it in \p prec_RR for reuse on + * subsequent calls to this function. Otherwise, the function + * will assume that \p prec_RR holds the helper value set by a + * previous call to mbedtls_mpi_exp_mod(), and reuse it. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \c N is negative or + * even, or if \c E is negative. + * \return Another negative error code on different kinds of failures. + * + */ +int mbedtls_mpi_exp_mod(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *E, const mbedtls_mpi *N, + mbedtls_mpi *prec_RR); + +/** + * \brief Fill an MPI with a number of random bytes. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param size The number of random bytes to generate. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on failure. + * + * \note The bytes obtained from the RNG are interpreted + * as a big-endian representation of an MPI; this can + * be relevant in applications like deterministic ECDSA. + */ +int mbedtls_mpi_fill_random(mbedtls_mpi *X, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** Generate a random number uniformly in a range. + * + * This function generates a random number between \p min inclusive and + * \p N exclusive. + * + * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) + * when the RNG is a suitably parametrized instance of HMAC_DRBG + * and \p min is \c 1. + * + * \note There are `N - min` possible outputs. The lower bound + * \p min can be reached, but the upper bound \p N cannot. + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param min The minimum value to return. + * It must be nonnegative. + * \param N The upper bound of the range, exclusive. + * In other words, this is one plus the maximum value to return. + * \p N must be strictly larger than \p min. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p min or \p N is invalid + * or if they are incompatible. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was + * unable to find a suitable value within a limited number + * of attempts. This has a negligible probability if \p N + * is significantly larger than \p min, which is the case + * for all usual cryptographic applications. + * \return Another negative error code on failure. + */ +int mbedtls_mpi_random(mbedtls_mpi *X, + mbedtls_mpi_sint min, + const mbedtls_mpi *N, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Compute the greatest common divisor: G = gcd(A, B) + * + * \param G The destination MPI. This must point to an initialized MPI. + * \param A The first operand. This must point to an initialized MPI. + * \param B The second operand. This must point to an initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_mpi_gcd(mbedtls_mpi *G, const mbedtls_mpi *A, + const mbedtls_mpi *B); + +/** + * \brief Compute the modular inverse: X = A^-1 mod N + * + * \param X The destination MPI. This must point to an initialized MPI. + * \param A The MPI to calculate the modular inverse of. This must point + * to an initialized MPI. + * \param N The base of the modular inversion. This must point to an + * initialized MPI. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p N is less than + * or equal to one. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p A has no modular + * inverse with respect to \p N. + */ +int mbedtls_mpi_inv_mod(mbedtls_mpi *X, const mbedtls_mpi *A, + const mbedtls_mpi *N); + +/** + * \brief Miller-Rabin primality test. + * + * \warning If \p X is potentially generated by an adversary, for example + * when validating cryptographic parameters that you didn't + * generate yourself and that are supposed to be prime, then + * \p rounds should be at least the half of the security + * strength of the cryptographic algorithm. On the other hand, + * if \p X is chosen uniformly or non-adversarially (as is the + * case when mbedtls_mpi_gen_prime calls this function), then + * \p rounds can be much lower. + * + * \param X The MPI to check for primality. + * This must point to an initialized MPI. + * \param rounds The number of bases to perform the Miller-Rabin primality + * test for. The probability of returning 0 on a composite is + * at most 2^-2*\p rounds. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't use + * a context parameter. + * + * \return \c 0 if successful, i.e. \p X is probably prime. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if \p X is not prime. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_mpi_is_prime_ext(const mbedtls_mpi *X, int rounds, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +/** + * \brief Flags for mbedtls_mpi_gen_prime() + * + * Each of these flags is a constraint on the result X returned by + * mbedtls_mpi_gen_prime(). + */ +typedef enum { + MBEDTLS_MPI_GEN_PRIME_FLAG_DH = 0x0001, /**< (X-1)/2 is prime too */ + MBEDTLS_MPI_GEN_PRIME_FLAG_LOW_ERR = 0x0002, /**< lower error rate from 2-80 to 2-128 */ +} mbedtls_mpi_gen_prime_flag_t; + +/** + * \brief Generate a prime number. + * + * \param X The destination MPI to store the generated prime in. + * This must point to an initialized MPi. + * \param nbits The required size of the destination MPI in bits. + * This must be between \c 3 and #MBEDTLS_MPI_MAX_BITS. + * \param flags A mask of flags of type #mbedtls_mpi_gen_prime_flag_t. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't use + * a context parameter. + * + * \return \c 0 if successful, in which case \p X holds a + * probably prime number. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if a memory allocation failed. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if `nbits` is not between + * \c 3 and #MBEDTLS_MPI_MAX_BITS. + */ +int mbedtls_mpi_gen_prime(mbedtls_mpi *X, size_t nbits, int flags, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_mpi_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* bignum.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/build_info.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/build_info.h index 842f15c..9f36485 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/build_info.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/build_info.h @@ -1,158 +1,158 @@ -/** - * \file mbedtls/build_info.h - * - * \brief Build-time configuration info - * - * Include this file if you need to depend on the - * configuration options defined in mbedtls_config.h or MBEDTLS_CONFIG_FILE - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BUILD_INFO_H -#define MBEDTLS_BUILD_INFO_H - -/* - * This set of compile-time defines can be used to determine the version number - * of the Mbed TLS library used. Run-time variables for the same can be found in - * version.h - */ - -/** - * The version number x.y.z is split into three parts. - * Major, Minor, Patchlevel - */ -#define MBEDTLS_VERSION_MAJOR 3 -#define MBEDTLS_VERSION_MINOR 5 -#define MBEDTLS_VERSION_PATCH 0 - -/** - * The single version number has the following structure: - * MMNNPP00 - * Major version | Minor version | Patch version - */ -#define MBEDTLS_VERSION_NUMBER 0x03050000 -#define MBEDTLS_VERSION_STRING "3.5.0" -#define MBEDTLS_VERSION_STRING_FULL "Mbed TLS 3.5.0" - -/* Macros for build-time platform detection */ - -#if !defined(MBEDTLS_ARCH_IS_ARM64) && \ - (defined(__aarch64__) || defined(_M_ARM64) || defined(_M_ARM64EC)) -#define MBEDTLS_ARCH_IS_ARM64 -#endif - -#if !defined(MBEDTLS_ARCH_IS_ARM32) && \ - (defined(__arm__) || defined(_M_ARM) || \ - defined(_M_ARMT) || defined(__thumb__) || defined(__thumb2__)) -#define MBEDTLS_ARCH_IS_ARM32 -#endif - -#if !defined(MBEDTLS_ARCH_IS_X64) && \ - (defined(__amd64__) || defined(__x86_64__) || \ - ((defined(_M_X64) || defined(_M_AMD64)) && !defined(_M_ARM64EC))) -#define MBEDTLS_ARCH_IS_X64 -#endif - -#if !defined(MBEDTLS_ARCH_IS_X86) && \ - (defined(__i386__) || defined(_X86_) || \ - (defined(_M_IX86) && !defined(_M_I86))) -#define MBEDTLS_ARCH_IS_X86 -#endif - -#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE) -#define _CRT_SECURE_NO_DEPRECATE 1 -#endif - -/* Define `inline` on some non-C99-compliant compilers. */ -#if (defined(__ARMCC_VERSION) || defined(_MSC_VER)) && \ - !defined(inline) && !defined(__cplusplus) -#define inline __inline -#endif - -/* X.509, TLS and non-PSA crypto configuration */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/mbedtls_config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif - -#if defined(MBEDTLS_CONFIG_VERSION) && ( \ - MBEDTLS_CONFIG_VERSION < 0x03000000 || \ - MBEDTLS_CONFIG_VERSION > MBEDTLS_VERSION_NUMBER) -#error "Invalid config version, defined value of MBEDTLS_CONFIG_VERSION is unsupported" -#endif - -/* Target and application specific configurations - * - * Allow user to override any previous default. - * - */ -#if defined(MBEDTLS_USER_CONFIG_FILE) -#include MBEDTLS_USER_CONFIG_FILE -#endif - -/* PSA crypto configuration */ -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG_FILE) -#include MBEDTLS_PSA_CRYPTO_CONFIG_FILE -#else -#include "psa/crypto_config.h" -#endif -#if defined(MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE) -#include MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE -#endif -#endif /* defined(MBEDTLS_PSA_CRYPTO_CONFIG) */ - -/* Auto-enable MBEDTLS_CTR_DRBG_USE_128_BIT_KEY if - * MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH and MBEDTLS_CTR_DRBG_C defined - * to ensure a 128-bit key size in CTR_DRBG. - */ -#if defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) && defined(MBEDTLS_CTR_DRBG_C) -#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY -#endif - -/* Auto-enable MBEDTLS_MD_C if needed by a module that didn't require it - * in a previous release, to ensure backwards compatibility. - */ -#if defined(MBEDTLS_PKCS5_C) -#define MBEDTLS_MD_C -#endif - -/* PSA crypto specific configuration options - * - If config_psa.h reads a configuration option in preprocessor directive, - * this symbol should be set before its inclusion. (e.g. MBEDTLS_MD_C) - * - If config_psa.h writes a configuration option in conditional directive, - * this symbol should be consulted after its inclusion. - * (e.g. MBEDTLS_MD_LIGHT) - */ -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) /* PSA_WANT_xxx influences MBEDTLS_xxx */ || \ - defined(MBEDTLS_PSA_CRYPTO_C) /* MBEDTLS_xxx influences PSA_WANT_xxx */ -#include "mbedtls/config_psa.h" -#endif - -#include "mbedtls/config_adjust_legacy_crypto.h" - -#include "mbedtls/config_adjust_x509.h" - -#include "mbedtls/config_adjust_ssl.h" - -/* Make sure all configuration symbols are set before including check_config.h, - * even the ones that are calculated programmatically. */ -#include "mbedtls/check_config.h" - -#endif /* MBEDTLS_BUILD_INFO_H */ +/** + * \file mbedtls/build_info.h + * + * \brief Build-time configuration info + * + * Include this file if you need to depend on the + * configuration options defined in mbedtls_config.h or MBEDTLS_CONFIG_FILE + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BUILD_INFO_H +#define MBEDTLS_BUILD_INFO_H + +/* + * This set of compile-time defines can be used to determine the version number + * of the Mbed TLS library used. Run-time variables for the same can be found in + * version.h + */ + +/** + * The version number x.y.z is split into three parts. + * Major, Minor, Patchlevel + */ +#define MBEDTLS_VERSION_MAJOR 3 +#define MBEDTLS_VERSION_MINOR 5 +#define MBEDTLS_VERSION_PATCH 0 + +/** + * The single version number has the following structure: + * MMNNPP00 + * Major version | Minor version | Patch version + */ +#define MBEDTLS_VERSION_NUMBER 0x03050000 +#define MBEDTLS_VERSION_STRING "3.5.0" +#define MBEDTLS_VERSION_STRING_FULL "Mbed TLS 3.5.0" + +/* Macros for build-time platform detection */ + +#if !defined(MBEDTLS_ARCH_IS_ARM64) && \ + (defined(__aarch64__) || defined(_M_ARM64) || defined(_M_ARM64EC)) +#define MBEDTLS_ARCH_IS_ARM64 +#endif + +#if !defined(MBEDTLS_ARCH_IS_ARM32) && \ + (defined(__arm__) || defined(_M_ARM) || \ + defined(_M_ARMT) || defined(__thumb__) || defined(__thumb2__)) +#define MBEDTLS_ARCH_IS_ARM32 +#endif + +#if !defined(MBEDTLS_ARCH_IS_X64) && \ + (defined(__amd64__) || defined(__x86_64__) || \ + ((defined(_M_X64) || defined(_M_AMD64)) && !defined(_M_ARM64EC))) +#define MBEDTLS_ARCH_IS_X64 +#endif + +#if !defined(MBEDTLS_ARCH_IS_X86) && \ + (defined(__i386__) || defined(_X86_) || \ + (defined(_M_IX86) && !defined(_M_I86))) +#define MBEDTLS_ARCH_IS_X86 +#endif + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE) +#define _CRT_SECURE_NO_DEPRECATE 1 +#endif + +/* Define `inline` on some non-C99-compliant compilers. */ +#if (defined(__ARMCC_VERSION) || defined(_MSC_VER)) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +/* X.509, TLS and non-PSA crypto configuration */ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/mbedtls_config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_CONFIG_VERSION) && ( \ + MBEDTLS_CONFIG_VERSION < 0x03000000 || \ + MBEDTLS_CONFIG_VERSION > MBEDTLS_VERSION_NUMBER) +#error "Invalid config version, defined value of MBEDTLS_CONFIG_VERSION is unsupported" +#endif + +/* Target and application specific configurations + * + * Allow user to override any previous default. + * + */ +#if defined(MBEDTLS_USER_CONFIG_FILE) +#include MBEDTLS_USER_CONFIG_FILE +#endif + +/* PSA crypto configuration */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG_FILE) +#include MBEDTLS_PSA_CRYPTO_CONFIG_FILE +#else +#include "psa/crypto_config.h" +#endif +#if defined(MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE) +#include MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE +#endif +#endif /* defined(MBEDTLS_PSA_CRYPTO_CONFIG) */ + +/* Auto-enable MBEDTLS_CTR_DRBG_USE_128_BIT_KEY if + * MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH and MBEDTLS_CTR_DRBG_C defined + * to ensure a 128-bit key size in CTR_DRBG. + */ +#if defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) && defined(MBEDTLS_CTR_DRBG_C) +#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY +#endif + +/* Auto-enable MBEDTLS_MD_C if needed by a module that didn't require it + * in a previous release, to ensure backwards compatibility. + */ +#if defined(MBEDTLS_PKCS5_C) +#define MBEDTLS_MD_C +#endif + +/* PSA crypto specific configuration options + * - If config_psa.h reads a configuration option in preprocessor directive, + * this symbol should be set before its inclusion. (e.g. MBEDTLS_MD_C) + * - If config_psa.h writes a configuration option in conditional directive, + * this symbol should be consulted after its inclusion. + * (e.g. MBEDTLS_MD_LIGHT) + */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) /* PSA_WANT_xxx influences MBEDTLS_xxx */ || \ + defined(MBEDTLS_PSA_CRYPTO_C) /* MBEDTLS_xxx influences PSA_WANT_xxx */ +#include "mbedtls/config_psa.h" +#endif + +#include "mbedtls/config_adjust_legacy_crypto.h" + +#include "mbedtls/config_adjust_x509.h" + +#include "mbedtls/config_adjust_ssl.h" + +/* Make sure all configuration symbols are set before including check_config.h, + * even the ones that are calculated programmatically. */ +#include "mbedtls/check_config.h" + +#endif /* MBEDTLS_BUILD_INFO_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/camellia.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/camellia.h index 8033c13..e04f724 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/camellia.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/camellia.h @@ -1,315 +1,315 @@ -/** - * \file camellia.h - * - * \brief Camellia block cipher - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_CAMELLIA_H -#define MBEDTLS_CAMELLIA_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#include "mbedtls/platform_util.h" - -#define MBEDTLS_CAMELLIA_ENCRYPT 1 -#define MBEDTLS_CAMELLIA_DECRYPT 0 - -/** Bad input data. */ -#define MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA -0x0024 - -/** Invalid data input length. */ -#define MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH -0x0026 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_CAMELLIA_ALT) -// Regular implementation -// - -/** - * \brief CAMELLIA context structure - */ -typedef struct mbedtls_camellia_context { - int MBEDTLS_PRIVATE(nr); /*!< number of rounds */ - uint32_t MBEDTLS_PRIVATE(rk)[68]; /*!< CAMELLIA round keys */ -} -mbedtls_camellia_context; - -#else /* MBEDTLS_CAMELLIA_ALT */ -#include "camellia_alt.h" -#endif /* MBEDTLS_CAMELLIA_ALT */ - -/** - * \brief Initialize a CAMELLIA context. - * - * \param ctx The CAMELLIA context to be initialized. - * This must not be \c NULL. - */ -void mbedtls_camellia_init(mbedtls_camellia_context *ctx); - -/** - * \brief Clear a CAMELLIA context. - * - * \param ctx The CAMELLIA context to be cleared. This may be \c NULL, - * in which case this function returns immediately. If it is not - * \c NULL, it must be initialized. - */ -void mbedtls_camellia_free(mbedtls_camellia_context *ctx); - -/** - * \brief Perform a CAMELLIA key schedule operation for encryption. - * - * \param ctx The CAMELLIA context to use. This must be initialized. - * \param key The encryption key to use. This must be a readable buffer - * of size \p keybits Bits. - * \param keybits The length of \p key in Bits. This must be either \c 128, - * \c 192 or \c 256. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_setkey_enc(mbedtls_camellia_context *ctx, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief Perform a CAMELLIA key schedule operation for decryption. - * - * \param ctx The CAMELLIA context to use. This must be initialized. - * \param key The decryption key. This must be a readable buffer - * of size \p keybits Bits. - * \param keybits The length of \p key in Bits. This must be either \c 128, - * \c 192 or \c 256. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_setkey_dec(mbedtls_camellia_context *ctx, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief Perform a CAMELLIA-ECB block encryption/decryption operation. - * - * \param ctx The CAMELLIA context to use. This must be initialized - * and bound to a key. - * \param mode The mode of operation. This must be either - * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. - * \param input The input block. This must be a readable buffer - * of size \c 16 Bytes. - * \param output The output block. This must be a writable buffer - * of size \c 16 Bytes. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_crypt_ecb(mbedtls_camellia_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16]); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief Perform a CAMELLIA-CBC buffer encryption/decryption operation. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx The CAMELLIA context to use. This must be initialized - * and bound to a key. - * \param mode The mode of operation. This must be either - * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. - * \param length The length in Bytes of the input data \p input. - * This must be a multiple of \c 16 Bytes. - * \param iv The initialization vector. This must be a read/write buffer - * of length \c 16 Bytes. It is updated to allow streaming - * use as explained above. - * \param input The buffer holding the input data. This must point to a - * readable buffer of length \p length Bytes. - * \param output The buffer holding the output data. This must point to a - * writable buffer of length \p length Bytes. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_crypt_cbc(mbedtls_camellia_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -/** - * \brief Perform a CAMELLIA-CFB128 buffer encryption/decryption - * operation. - * - * \note Due to the nature of CFB mode, you should use the same - * key for both encryption and decryption. In particular, calls - * to this function should be preceded by a key-schedule via - * mbedtls_camellia_setkey_enc() regardless of whether \p mode - * is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx The CAMELLIA context to use. This must be initialized - * and bound to a key. - * \param mode The mode of operation. This must be either - * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. - * \param length The length of the input data \p input. Any value is allowed. - * \param iv_off The current offset in the IV. This must be smaller - * than \c 16 Bytes. It is updated after this call to allow - * the aforementioned streaming usage. - * \param iv The initialization vector. This must be a read/write buffer - * of length \c 16 Bytes. It is updated after this call to - * allow the aforementioned streaming usage. - * \param input The buffer holding the input data. This must be a readable - * buffer of size \p length Bytes. - * \param output The buffer to hold the output data. This must be a writable - * buffer of length \p length Bytes. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_crypt_cfb128(mbedtls_camellia_context *ctx, - int mode, - size_t length, - size_t *iv_off, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -/** - * \brief Perform a CAMELLIA-CTR buffer encryption/decryption operation. - * - * *note Due to the nature of CTR mode, you should use the same - * key for both encryption and decryption. In particular, calls - * to this function should be preceded by a key-schedule via - * mbedtls_camellia_setkey_enc() regardless of whether the mode - * is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. - * - * \warning You must never reuse a nonce value with the same key. Doing so - * would void the encryption for the two messages encrypted with - * the same nonce and key. - * - * There are two common strategies for managing nonces with CTR: - * - * 1. You can handle everything as a single message processed over - * successive calls to this function. In that case, you want to - * set \p nonce_counter and \p nc_off to 0 for the first call, and - * then preserve the values of \p nonce_counter, \p nc_off and \p - * stream_block across calls to this function as they will be - * updated by this function. - * - * With this strategy, you must not encrypt more than 2**128 - * blocks of data with the same key. - * - * 2. You can encrypt separate messages by dividing the \p - * nonce_counter buffer in two areas: the first one used for a - * per-message nonce, handled by yourself, and the second one - * updated by this function internally. - * - * For example, you might reserve the first \c 12 Bytes for the - * per-message nonce, and the last \c 4 Bytes for internal use. - * In that case, before calling this function on a new message you - * need to set the first \c 12 Bytes of \p nonce_counter to your - * chosen nonce value, the last four to \c 0, and \p nc_off to \c 0 - * (which will cause \p stream_block to be ignored). That way, you - * can encrypt at most \c 2**96 messages of up to \c 2**32 blocks - * each with the same key. - * - * The per-message nonce (or information sufficient to reconstruct - * it) needs to be communicated with the ciphertext and must be - * unique. The recommended way to ensure uniqueness is to use a - * message counter. An alternative is to generate random nonces, - * but this limits the number of messages that can be securely - * encrypted: for example, with 96-bit random nonces, you should - * not encrypt more than 2**32 messages with the same key. - * - * Note that for both strategies, sizes are measured in blocks and - * that a CAMELLIA block is \c 16 Bytes. - * - * \warning Upon return, \p stream_block contains sensitive data. Its - * content must not be written to insecure storage and should be - * securely discarded as soon as it's no longer needed. - * - * \param ctx The CAMELLIA context to use. This must be initialized - * and bound to a key. - * \param length The length of the input data \p input in Bytes. - * Any value is allowed. - * \param nc_off The offset in the current \p stream_block (for resuming - * within current cipher stream). The offset pointer to - * should be \c 0 at the start of a stream. It is updated - * at the end of this call. - * \param nonce_counter The 128-bit nonce and counter. This must be a read/write - * buffer of length \c 16 Bytes. - * \param stream_block The saved stream-block for resuming. This must be a - * read/write buffer of length \c 16 Bytes. - * \param input The input data stream. This must be a readable buffer of - * size \p length Bytes. - * \param output The output data stream. This must be a writable buffer - * of size \p length Bytes. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_camellia_crypt_ctr(mbedtls_camellia_context *ctx, - size_t length, - size_t *nc_off, - unsigned char nonce_counter[16], - unsigned char stream_block[16], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int mbedtls_camellia_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* camellia.h */ +/** + * \file camellia.h + * + * \brief Camellia block cipher + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_CAMELLIA_H +#define MBEDTLS_CAMELLIA_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#include "mbedtls/platform_util.h" + +#define MBEDTLS_CAMELLIA_ENCRYPT 1 +#define MBEDTLS_CAMELLIA_DECRYPT 0 + +/** Bad input data. */ +#define MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA -0x0024 + +/** Invalid data input length. */ +#define MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH -0x0026 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_CAMELLIA_ALT) +// Regular implementation +// + +/** + * \brief CAMELLIA context structure + */ +typedef struct mbedtls_camellia_context { + int MBEDTLS_PRIVATE(nr); /*!< number of rounds */ + uint32_t MBEDTLS_PRIVATE(rk)[68]; /*!< CAMELLIA round keys */ +} +mbedtls_camellia_context; + +#else /* MBEDTLS_CAMELLIA_ALT */ +#include "camellia_alt.h" +#endif /* MBEDTLS_CAMELLIA_ALT */ + +/** + * \brief Initialize a CAMELLIA context. + * + * \param ctx The CAMELLIA context to be initialized. + * This must not be \c NULL. + */ +void mbedtls_camellia_init(mbedtls_camellia_context *ctx); + +/** + * \brief Clear a CAMELLIA context. + * + * \param ctx The CAMELLIA context to be cleared. This may be \c NULL, + * in which case this function returns immediately. If it is not + * \c NULL, it must be initialized. + */ +void mbedtls_camellia_free(mbedtls_camellia_context *ctx); + +/** + * \brief Perform a CAMELLIA key schedule operation for encryption. + * + * \param ctx The CAMELLIA context to use. This must be initialized. + * \param key The encryption key to use. This must be a readable buffer + * of size \p keybits Bits. + * \param keybits The length of \p key in Bits. This must be either \c 128, + * \c 192 or \c 256. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_setkey_enc(mbedtls_camellia_context *ctx, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief Perform a CAMELLIA key schedule operation for decryption. + * + * \param ctx The CAMELLIA context to use. This must be initialized. + * \param key The decryption key. This must be a readable buffer + * of size \p keybits Bits. + * \param keybits The length of \p key in Bits. This must be either \c 128, + * \c 192 or \c 256. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_setkey_dec(mbedtls_camellia_context *ctx, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief Perform a CAMELLIA-ECB block encryption/decryption operation. + * + * \param ctx The CAMELLIA context to use. This must be initialized + * and bound to a key. + * \param mode The mode of operation. This must be either + * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. + * \param input The input block. This must be a readable buffer + * of size \c 16 Bytes. + * \param output The output block. This must be a writable buffer + * of size \c 16 Bytes. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_crypt_ecb(mbedtls_camellia_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief Perform a CAMELLIA-CBC buffer encryption/decryption operation. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx The CAMELLIA context to use. This must be initialized + * and bound to a key. + * \param mode The mode of operation. This must be either + * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. + * \param length The length in Bytes of the input data \p input. + * This must be a multiple of \c 16 Bytes. + * \param iv The initialization vector. This must be a read/write buffer + * of length \c 16 Bytes. It is updated to allow streaming + * use as explained above. + * \param input The buffer holding the input data. This must point to a + * readable buffer of length \p length Bytes. + * \param output The buffer holding the output data. This must point to a + * writable buffer of length \p length Bytes. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_crypt_cbc(mbedtls_camellia_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief Perform a CAMELLIA-CFB128 buffer encryption/decryption + * operation. + * + * \note Due to the nature of CFB mode, you should use the same + * key for both encryption and decryption. In particular, calls + * to this function should be preceded by a key-schedule via + * mbedtls_camellia_setkey_enc() regardless of whether \p mode + * is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx The CAMELLIA context to use. This must be initialized + * and bound to a key. + * \param mode The mode of operation. This must be either + * #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. + * \param length The length of the input data \p input. Any value is allowed. + * \param iv_off The current offset in the IV. This must be smaller + * than \c 16 Bytes. It is updated after this call to allow + * the aforementioned streaming usage. + * \param iv The initialization vector. This must be a read/write buffer + * of length \c 16 Bytes. It is updated after this call to + * allow the aforementioned streaming usage. + * \param input The buffer holding the input data. This must be a readable + * buffer of size \p length Bytes. + * \param output The buffer to hold the output data. This must be a writable + * buffer of length \p length Bytes. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_crypt_cfb128(mbedtls_camellia_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief Perform a CAMELLIA-CTR buffer encryption/decryption operation. + * + * *note Due to the nature of CTR mode, you should use the same + * key for both encryption and decryption. In particular, calls + * to this function should be preceded by a key-schedule via + * mbedtls_camellia_setkey_enc() regardless of whether the mode + * is #MBEDTLS_CAMELLIA_ENCRYPT or #MBEDTLS_CAMELLIA_DECRYPT. + * + * \warning You must never reuse a nonce value with the same key. Doing so + * would void the encryption for the two messages encrypted with + * the same nonce and key. + * + * There are two common strategies for managing nonces with CTR: + * + * 1. You can handle everything as a single message processed over + * successive calls to this function. In that case, you want to + * set \p nonce_counter and \p nc_off to 0 for the first call, and + * then preserve the values of \p nonce_counter, \p nc_off and \p + * stream_block across calls to this function as they will be + * updated by this function. + * + * With this strategy, you must not encrypt more than 2**128 + * blocks of data with the same key. + * + * 2. You can encrypt separate messages by dividing the \p + * nonce_counter buffer in two areas: the first one used for a + * per-message nonce, handled by yourself, and the second one + * updated by this function internally. + * + * For example, you might reserve the first \c 12 Bytes for the + * per-message nonce, and the last \c 4 Bytes for internal use. + * In that case, before calling this function on a new message you + * need to set the first \c 12 Bytes of \p nonce_counter to your + * chosen nonce value, the last four to \c 0, and \p nc_off to \c 0 + * (which will cause \p stream_block to be ignored). That way, you + * can encrypt at most \c 2**96 messages of up to \c 2**32 blocks + * each with the same key. + * + * The per-message nonce (or information sufficient to reconstruct + * it) needs to be communicated with the ciphertext and must be + * unique. The recommended way to ensure uniqueness is to use a + * message counter. An alternative is to generate random nonces, + * but this limits the number of messages that can be securely + * encrypted: for example, with 96-bit random nonces, you should + * not encrypt more than 2**32 messages with the same key. + * + * Note that for both strategies, sizes are measured in blocks and + * that a CAMELLIA block is \c 16 Bytes. + * + * \warning Upon return, \p stream_block contains sensitive data. Its + * content must not be written to insecure storage and should be + * securely discarded as soon as it's no longer needed. + * + * \param ctx The CAMELLIA context to use. This must be initialized + * and bound to a key. + * \param length The length of the input data \p input in Bytes. + * Any value is allowed. + * \param nc_off The offset in the current \p stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be \c 0 at the start of a stream. It is updated + * at the end of this call. + * \param nonce_counter The 128-bit nonce and counter. This must be a read/write + * buffer of length \c 16 Bytes. + * \param stream_block The saved stream-block for resuming. This must be a + * read/write buffer of length \c 16 Bytes. + * \param input The input data stream. This must be a readable buffer of + * size \p length Bytes. + * \param output The output data stream. This must be a writable buffer + * of size \p length Bytes. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_camellia_crypt_ctr(mbedtls_camellia_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_camellia_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* camellia.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ccm.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ccm.h index e00e747..682b88f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ccm.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ccm.h @@ -1,530 +1,530 @@ -/** - * \file ccm.h - * - * \brief This file provides an API for the CCM authenticated encryption - * mode for block ciphers. - * - * CCM combines Counter mode encryption with CBC-MAC authentication - * for 128-bit block ciphers. - * - * Input to CCM includes the following elements: - *
  • Payload - data that is both authenticated and encrypted.
    • - *
  • Associated data (Adata) - data that is authenticated but not - * encrypted, For example, a header.
    • - *
  • Nonce - A unique value that is assigned to the payload and the - * associated data.
- * - * Definition of CCM: - * http://csrc.nist.gov/publications/nistpubs/800-38C/SP800-38C_updated-July20_2007.pdf - * RFC 3610 "Counter with CBC-MAC (CCM)" - * - * Related: - * RFC 5116 "An Interface and Algorithms for Authenticated Encryption" - * - * Definition of CCM*: - * IEEE 802.15.4 - IEEE Standard for Local and metropolitan area networks - * Integer representation is fixed most-significant-octet-first order and - * the representation of octets is most-significant-bit-first order. This is - * consistent with RFC 3610. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CCM_H -#define MBEDTLS_CCM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/cipher.h" - -#define MBEDTLS_CCM_DECRYPT 0 -#define MBEDTLS_CCM_ENCRYPT 1 -#define MBEDTLS_CCM_STAR_DECRYPT 2 -#define MBEDTLS_CCM_STAR_ENCRYPT 3 - -/** Bad input parameters to the function. */ -#define MBEDTLS_ERR_CCM_BAD_INPUT -0x000D -/** Authenticated decryption failed. */ -#define MBEDTLS_ERR_CCM_AUTH_FAILED -0x000F - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_CCM_ALT) -// Regular implementation -// - -/** - * \brief The CCM context-type definition. The CCM context is passed - * to the APIs called. - */ -typedef struct mbedtls_ccm_context { - unsigned char MBEDTLS_PRIVATE(y)[16]; /*!< The Y working buffer */ - unsigned char MBEDTLS_PRIVATE(ctr)[16]; /*!< The counter buffer */ - size_t MBEDTLS_PRIVATE(plaintext_len); /*!< Total plaintext length */ - size_t MBEDTLS_PRIVATE(add_len); /*!< Total authentication data length */ - size_t MBEDTLS_PRIVATE(tag_len); /*!< Total tag length */ - size_t MBEDTLS_PRIVATE(processed); /*!< Track how many bytes of input data - were processed (chunked input). - Used independently for both auth data - and plaintext/ciphertext. - This variable is set to zero after - auth data input is finished. */ - unsigned int MBEDTLS_PRIVATE(q); /*!< The Q working value */ - unsigned int MBEDTLS_PRIVATE(mode); /*!< The operation to perform: - #MBEDTLS_CCM_ENCRYPT or - #MBEDTLS_CCM_DECRYPT or - #MBEDTLS_CCM_STAR_ENCRYPT or - #MBEDTLS_CCM_STAR_DECRYPT. */ - mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ - int MBEDTLS_PRIVATE(state); /*!< Working value holding context's - state. Used for chunked data input */ -} -mbedtls_ccm_context; - -#else /* MBEDTLS_CCM_ALT */ -#include "ccm_alt.h" -#endif /* MBEDTLS_CCM_ALT */ - -/** - * \brief This function initializes the specified CCM context, - * to make references valid, and prepare the context - * for mbedtls_ccm_setkey() or mbedtls_ccm_free(). - * - * \param ctx The CCM context to initialize. This must not be \c NULL. - */ -void mbedtls_ccm_init(mbedtls_ccm_context *ctx); - -/** - * \brief This function initializes the CCM context set in the - * \p ctx parameter and sets the encryption key. - * - * \param ctx The CCM context to initialize. This must be an initialized - * context. - * \param cipher The 128-bit block cipher to use. - * \param key The encryption key. This must not be \c NULL. - * \param keybits The key size in bits. This must be acceptable by the cipher. - * - * \return \c 0 on success. - * \return A CCM or cipher-specific error code on failure. - */ -int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, - mbedtls_cipher_id_t cipher, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function releases and clears the specified CCM context - * and underlying cipher sub-context. - * - * \param ctx The CCM context to clear. If this is \c NULL, the function - * has no effect. Otherwise, this must be initialized. - */ -void mbedtls_ccm_free(mbedtls_ccm_context *ctx); - -/** - * \brief This function encrypts a buffer using CCM. - * - * \note The tag is written to a separate buffer. To concatenate - * the \p tag with the \p output, as done in RFC-3610: - * Counter with CBC-MAC (CCM), use - * \p tag = \p output + \p length, and make sure that the - * output buffer is at least \p length + \p tag_len wide. - * - * \param ctx The CCM context to use for encryption. This must be - * initialized and bound to a key. - * \param length The length of the input data in Bytes. - * \param iv The initialization vector (nonce). This must be a readable - * buffer of at least \p iv_len Bytes. - * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, - * or 13. The length L of the message length field is - * 15 - \p iv_len. - * \param ad The additional data field. If \p ad_len is greater than - * zero, \p ad must be a readable buffer of at least that - * length. - * \param ad_len The length of additional data in Bytes. - * This must be less than `2^16 - 2^8`. - * \param input The buffer holding the input data. If \p length is greater - * than zero, \p input must be a readable buffer of at least - * that length. - * \param output The buffer holding the output data. If \p length is greater - * than zero, \p output must be a writable buffer of at least - * that length. - * \param tag The buffer holding the authentication field. This must be a - * writable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the authentication field to generate in Bytes: - * 4, 6, 8, 10, 12, 14 or 16. - * - * \return \c 0 on success. - * \return A CCM or cipher-specific error code on failure. - */ -int mbedtls_ccm_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, unsigned char *output, - unsigned char *tag, size_t tag_len); - -/** - * \brief This function encrypts a buffer using CCM*. - * - * \note The tag is written to a separate buffer. To concatenate - * the \p tag with the \p output, as done in RFC-3610: - * Counter with CBC-MAC (CCM), use - * \p tag = \p output + \p length, and make sure that the - * output buffer is at least \p length + \p tag_len wide. - * - * \note When using this function in a variable tag length context, - * the tag length has to be encoded into the \p iv passed to - * this function. - * - * \param ctx The CCM context to use for encryption. This must be - * initialized and bound to a key. - * \param length The length of the input data in Bytes. - * For tag length = 0, input length is ignored. - * \param iv The initialization vector (nonce). This must be a readable - * buffer of at least \p iv_len Bytes. - * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, - * or 13. The length L of the message length field is - * 15 - \p iv_len. - * \param ad The additional data field. This must be a readable buffer of - * at least \p ad_len Bytes. - * \param ad_len The length of additional data in Bytes. - * This must be less than 2^16 - 2^8. - * \param input The buffer holding the input data. If \p length is greater - * than zero, \p input must be a readable buffer of at least - * that length. - * \param output The buffer holding the output data. If \p length is greater - * than zero, \p output must be a writable buffer of at least - * that length. - * \param tag The buffer holding the authentication field. This must be a - * writable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the authentication field to generate in Bytes: - * 0, 4, 6, 8, 10, 12, 14 or 16. - * - * \warning Passing \c 0 as \p tag_len means that the message is no - * longer authenticated. - * - * \return \c 0 on success. - * \return A CCM or cipher-specific error code on failure. - */ -int mbedtls_ccm_star_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, unsigned char *output, - unsigned char *tag, size_t tag_len); - -/** - * \brief This function performs a CCM authenticated decryption of a - * buffer. - * - * \param ctx The CCM context to use for decryption. This must be - * initialized and bound to a key. - * \param length The length of the input data in Bytes. - * \param iv The initialization vector (nonce). This must be a readable - * buffer of at least \p iv_len Bytes. - * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, - * or 13. The length L of the message length field is - * 15 - \p iv_len. - * \param ad The additional data field. This must be a readable buffer - * of at least that \p ad_len Bytes.. - * \param ad_len The length of additional data in Bytes. - * This must be less than 2^16 - 2^8. - * \param input The buffer holding the input data. If \p length is greater - * than zero, \p input must be a readable buffer of at least - * that length. - * \param output The buffer holding the output data. If \p length is greater - * than zero, \p output must be a writable buffer of at least - * that length. - * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the authentication field to generate in Bytes: - * 4, 6, 8, 10, 12, 14 or 16. - * - * \return \c 0 on success. This indicates that the message is authentic. - * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. - * \return A cipher-specific error code on calculation failure. - */ -int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, unsigned char *output, - const unsigned char *tag, size_t tag_len); - -/** - * \brief This function performs a CCM* authenticated decryption of a - * buffer. - * - * \note When using this function in a variable tag length context, - * the tag length has to be decoded from \p iv and passed to - * this function as \p tag_len. (\p tag needs to be adjusted - * accordingly.) - * - * \param ctx The CCM context to use for decryption. This must be - * initialized and bound to a key. - * \param length The length of the input data in Bytes. - * For tag length = 0, input length is ignored. - * \param iv The initialization vector (nonce). This must be a readable - * buffer of at least \p iv_len Bytes. - * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, - * or 13. The length L of the message length field is - * 15 - \p iv_len. - * \param ad The additional data field. This must be a readable buffer of - * at least that \p ad_len Bytes. - * \param ad_len The length of additional data in Bytes. - * This must be less than 2^16 - 2^8. - * \param input The buffer holding the input data. If \p length is greater - * than zero, \p input must be a readable buffer of at least - * that length. - * \param output The buffer holding the output data. If \p length is greater - * than zero, \p output must be a writable buffer of at least - * that length. - * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the authentication field in Bytes. - * 0, 4, 6, 8, 10, 12, 14 or 16. - * - * \warning Passing \c 0 as \p tag_len means that the message is nos - * longer authenticated. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. - * \return A cipher-specific error code on calculation failure. - */ -int mbedtls_ccm_star_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, unsigned char *output, - const unsigned char *tag, size_t tag_len); - -/** - * \brief This function starts a CCM encryption or decryption - * operation. - * - * This function and mbedtls_ccm_set_lengths() must be called - * before calling mbedtls_ccm_update_ad() or - * mbedtls_ccm_update(). This function can be called before - * or after mbedtls_ccm_set_lengths(). - * - * \note This function is not implemented in Mbed TLS yet. - * - * \param ctx The CCM context. This must be initialized. - * \param mode The operation to perform: #MBEDTLS_CCM_ENCRYPT or - * #MBEDTLS_CCM_DECRYPT or #MBEDTLS_CCM_STAR_ENCRYPT or - * #MBEDTLS_CCM_STAR_DECRYPT. - * \param iv The initialization vector. This must be a readable buffer - * of at least \p iv_len Bytes. - * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, - * or 13. The length L of the message length field is - * 15 - \p iv_len. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: - * \p ctx is in an invalid state, - * \p mode is invalid, - * \p iv_len is invalid (lower than \c 7 or greater than - * \c 13). - */ -int mbedtls_ccm_starts(mbedtls_ccm_context *ctx, - int mode, - const unsigned char *iv, - size_t iv_len); - -/** - * \brief This function declares the lengths of the message - * and additional data for a CCM encryption or decryption - * operation. - * - * This function and mbedtls_ccm_starts() must be called - * before calling mbedtls_ccm_update_ad() or - * mbedtls_ccm_update(). This function can be called before - * or after mbedtls_ccm_starts(). - * - * \note This function is not implemented in Mbed TLS yet. - * - * \param ctx The CCM context. This must be initialized. - * \param total_ad_len The total length of additional data in bytes. - * This must be less than `2^16 - 2^8`. - * \param plaintext_len The length in bytes of the plaintext to encrypt or - * result of the decryption (thus not encompassing the - * additional data that are not encrypted). - * \param tag_len The length of the tag to generate in Bytes: - * 4, 6, 8, 10, 12, 14 or 16. - * For CCM*, zero is also valid. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: - * \p ctx is in an invalid state, - * \p total_ad_len is greater than \c 0xFF00. - */ -int mbedtls_ccm_set_lengths(mbedtls_ccm_context *ctx, - size_t total_ad_len, - size_t plaintext_len, - size_t tag_len); - -/** - * \brief This function feeds an input buffer as associated data - * (authenticated but not encrypted data) in a CCM - * encryption or decryption operation. - * - * You may call this function zero, one or more times - * to pass successive parts of the additional data. The - * lengths \p ad_len of the data parts should eventually add - * up exactly to the total length of additional data - * \c total_ad_len passed to mbedtls_ccm_set_lengths(). You - * may not call this function after calling - * mbedtls_ccm_update(). - * - * \note This function is not implemented in Mbed TLS yet. - * - * \param ctx The CCM context. This must have been started with - * mbedtls_ccm_starts(), the lengths of the message and - * additional data must have been declared with - * mbedtls_ccm_set_lengths() and this must not have yet - * received any input with mbedtls_ccm_update(). - * \param ad The buffer holding the additional data, or \c NULL - * if \p ad_len is \c 0. - * \param ad_len The length of the additional data. If \c 0, - * \p ad may be \c NULL. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: - * \p ctx is in an invalid state, - * total input length too long. - */ -int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, - const unsigned char *ad, - size_t ad_len); - -/** - * \brief This function feeds an input buffer into an ongoing CCM - * encryption or decryption operation. - * - * You may call this function zero, one or more times - * to pass successive parts of the input: the plaintext to - * encrypt, or the ciphertext (not including the tag) to - * decrypt. After the last part of the input, call - * mbedtls_ccm_finish(). The lengths \p input_len of the - * data parts should eventually add up exactly to the - * plaintext length \c plaintext_len passed to - * mbedtls_ccm_set_lengths(). - * - * This function may produce output in one of the following - * ways: - * - Immediate output: the output length is always equal - * to the input length. - * - Buffered output: except for the last part of input data, - * the output consists of a whole number of 16-byte blocks. - * If the total input length so far (not including - * associated data) is 16 \* *B* + *A* with *A* < 16 then - * the total output length is 16 \* *B*. - * For the last part of input data, the output length is - * equal to the input length plus the number of bytes (*A*) - * buffered in the previous call to the function (if any). - * The function uses the plaintext length - * \c plaintext_len passed to mbedtls_ccm_set_lengths() - * to detect the last part of input data. - * - * In particular: - * - It is always correct to call this function with - * \p output_size >= \p input_len + 15. - * - If \p input_len is a multiple of 16 for all the calls - * to this function during an operation (not necessary for - * the last one) then it is correct to use \p output_size - * =\p input_len. - * - * \note This function is not implemented in Mbed TLS yet. - * - * \param ctx The CCM context. This must have been started with - * mbedtls_ccm_starts() and the lengths of the message and - * additional data must have been declared with - * mbedtls_ccm_set_lengths(). - * \param input The buffer holding the input data. If \p input_len - * is greater than zero, this must be a readable buffer - * of at least \p input_len bytes. - * \param input_len The length of the input data in bytes. - * \param output The buffer for the output data. If \p output_size - * is greater than zero, this must be a writable buffer of - * at least \p output_size bytes. - * \param output_size The size of the output buffer in bytes. - * See the function description regarding the output size. - * \param output_len On success, \p *output_len contains the actual - * length of the output written in \p output. - * On failure, the content of \p *output_len is - * unspecified. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: - * \p ctx is in an invalid state, - * total input length too long, - * or \p output_size too small. - */ -int mbedtls_ccm_update(mbedtls_ccm_context *ctx, - const unsigned char *input, size_t input_len, - unsigned char *output, size_t output_size, - size_t *output_len); - -/** - * \brief This function finishes the CCM operation and generates - * the authentication tag. - * - * It wraps up the CCM stream, and generates the - * tag. The tag can have a maximum length of 16 Bytes. - * - * \note This function is not implemented in Mbed TLS yet. - * - * \param ctx The CCM context. This must have been started with - * mbedtls_ccm_starts() and the lengths of the message and - * additional data must have been declared with - * mbedtls_ccm_set_lengths(). - * \param tag The buffer for holding the tag. If \p tag_len is greater - * than zero, this must be a writable buffer of at least \p - * tag_len Bytes. - * \param tag_len The length of the tag. Must match the tag length passed to - * mbedtls_ccm_set_lengths() function. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: - * \p ctx is in an invalid state, - * invalid value of \p tag_len, - * the total amount of additional data passed to - * mbedtls_ccm_update_ad() was lower than the total length of - * additional data \c total_ad_len passed to - * mbedtls_ccm_set_lengths(), - * the total amount of input data passed to - * mbedtls_ccm_update() was lower than the plaintext length - * \c plaintext_len passed to mbedtls_ccm_set_lengths(). - */ -int mbedtls_ccm_finish(mbedtls_ccm_context *ctx, - unsigned char *tag, size_t tag_len); - -#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) -/** - * \brief The CCM checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_ccm_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CCM_H */ +/** + * \file ccm.h + * + * \brief This file provides an API for the CCM authenticated encryption + * mode for block ciphers. + * + * CCM combines Counter mode encryption with CBC-MAC authentication + * for 128-bit block ciphers. + * + * Input to CCM includes the following elements: + *
  • Payload - data that is both authenticated and encrypted.
    • + *
  • Associated data (Adata) - data that is authenticated but not + * encrypted, For example, a header.
    • + *
  • Nonce - A unique value that is assigned to the payload and the + * associated data.
+ * + * Definition of CCM: + * http://csrc.nist.gov/publications/nistpubs/800-38C/SP800-38C_updated-July20_2007.pdf + * RFC 3610 "Counter with CBC-MAC (CCM)" + * + * Related: + * RFC 5116 "An Interface and Algorithms for Authenticated Encryption" + * + * Definition of CCM*: + * IEEE 802.15.4 - IEEE Standard for Local and metropolitan area networks + * Integer representation is fixed most-significant-octet-first order and + * the representation of octets is most-significant-bit-first order. This is + * consistent with RFC 3610. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CCM_H +#define MBEDTLS_CCM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/cipher.h" + +#define MBEDTLS_CCM_DECRYPT 0 +#define MBEDTLS_CCM_ENCRYPT 1 +#define MBEDTLS_CCM_STAR_DECRYPT 2 +#define MBEDTLS_CCM_STAR_ENCRYPT 3 + +/** Bad input parameters to the function. */ +#define MBEDTLS_ERR_CCM_BAD_INPUT -0x000D +/** Authenticated decryption failed. */ +#define MBEDTLS_ERR_CCM_AUTH_FAILED -0x000F + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_CCM_ALT) +// Regular implementation +// + +/** + * \brief The CCM context-type definition. The CCM context is passed + * to the APIs called. + */ +typedef struct mbedtls_ccm_context { + unsigned char MBEDTLS_PRIVATE(y)[16]; /*!< The Y working buffer */ + unsigned char MBEDTLS_PRIVATE(ctr)[16]; /*!< The counter buffer */ + size_t MBEDTLS_PRIVATE(plaintext_len); /*!< Total plaintext length */ + size_t MBEDTLS_PRIVATE(add_len); /*!< Total authentication data length */ + size_t MBEDTLS_PRIVATE(tag_len); /*!< Total tag length */ + size_t MBEDTLS_PRIVATE(processed); /*!< Track how many bytes of input data + were processed (chunked input). + Used independently for both auth data + and plaintext/ciphertext. + This variable is set to zero after + auth data input is finished. */ + unsigned int MBEDTLS_PRIVATE(q); /*!< The Q working value */ + unsigned int MBEDTLS_PRIVATE(mode); /*!< The operation to perform: + #MBEDTLS_CCM_ENCRYPT or + #MBEDTLS_CCM_DECRYPT or + #MBEDTLS_CCM_STAR_ENCRYPT or + #MBEDTLS_CCM_STAR_DECRYPT. */ + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ + int MBEDTLS_PRIVATE(state); /*!< Working value holding context's + state. Used for chunked data input */ +} +mbedtls_ccm_context; + +#else /* MBEDTLS_CCM_ALT */ +#include "ccm_alt.h" +#endif /* MBEDTLS_CCM_ALT */ + +/** + * \brief This function initializes the specified CCM context, + * to make references valid, and prepare the context + * for mbedtls_ccm_setkey() or mbedtls_ccm_free(). + * + * \param ctx The CCM context to initialize. This must not be \c NULL. + */ +void mbedtls_ccm_init(mbedtls_ccm_context *ctx); + +/** + * \brief This function initializes the CCM context set in the + * \p ctx parameter and sets the encryption key. + * + * \param ctx The CCM context to initialize. This must be an initialized + * context. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. This must not be \c NULL. + * \param keybits The key size in bits. This must be acceptable by the cipher. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_setkey(mbedtls_ccm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function releases and clears the specified CCM context + * and underlying cipher sub-context. + * + * \param ctx The CCM context to clear. If this is \c NULL, the function + * has no effect. Otherwise, this must be initialized. + */ +void mbedtls_ccm_free(mbedtls_ccm_context *ctx); + +/** + * \brief This function encrypts a buffer using CCM. + * + * \note The tag is written to a separate buffer. To concatenate + * the \p tag with the \p output, as done in RFC-3610: + * Counter with CBC-MAC (CCM), use + * \p tag = \p output + \p length, and make sure that the + * output buffer is at least \p length + \p tag_len wide. + * + * \param ctx The CCM context to use for encryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param ad The additional data field. If \p ad_len is greater than + * zero, \p ad must be a readable buffer of at least that + * length. + * \param ad_len The length of additional data in Bytes. + * This must be less than `2^16 - 2^8`. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * writable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 4, 6, 8, 10, 12, 14 or 16. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len); + +/** + * \brief This function encrypts a buffer using CCM*. + * + * \note The tag is written to a separate buffer. To concatenate + * the \p tag with the \p output, as done in RFC-3610: + * Counter with CBC-MAC (CCM), use + * \p tag = \p output + \p length, and make sure that the + * output buffer is at least \p length + \p tag_len wide. + * + * \note When using this function in a variable tag length context, + * the tag length has to be encoded into the \p iv passed to + * this function. + * + * \param ctx The CCM context to use for encryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * For tag length = 0, input length is ignored. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param ad The additional data field. This must be a readable buffer of + * at least \p ad_len Bytes. + * \param ad_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * writable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 0, 4, 6, 8, 10, 12, 14 or 16. + * + * \warning Passing \c 0 as \p tag_len means that the message is no + * longer authenticated. + * + * \return \c 0 on success. + * \return A CCM or cipher-specific error code on failure. + */ +int mbedtls_ccm_star_encrypt_and_tag(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, unsigned char *output, + unsigned char *tag, size_t tag_len); + +/** + * \brief This function performs a CCM authenticated decryption of a + * buffer. + * + * \param ctx The CCM context to use for decryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param ad The additional data field. This must be a readable buffer + * of at least that \p ad_len Bytes.. + * \param ad_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field to generate in Bytes: + * 4, 6, 8, 10, 12, 14 or 16. + * + * \return \c 0 on success. This indicates that the message is authentic. + * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. + * \return A cipher-specific error code on calculation failure. + */ +int mbedtls_ccm_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len); + +/** + * \brief This function performs a CCM* authenticated decryption of a + * buffer. + * + * \note When using this function in a variable tag length context, + * the tag length has to be decoded from \p iv and passed to + * this function as \p tag_len. (\p tag needs to be adjusted + * accordingly.) + * + * \param ctx The CCM context to use for decryption. This must be + * initialized and bound to a key. + * \param length The length of the input data in Bytes. + * For tag length = 0, input length is ignored. + * \param iv The initialization vector (nonce). This must be a readable + * buffer of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * \param ad The additional data field. This must be a readable buffer of + * at least that \p ad_len Bytes. + * \param ad_len The length of additional data in Bytes. + * This must be less than 2^16 - 2^8. + * \param input The buffer holding the input data. If \p length is greater + * than zero, \p input must be a readable buffer of at least + * that length. + * \param output The buffer holding the output data. If \p length is greater + * than zero, \p output must be a writable buffer of at least + * that length. + * \param tag The buffer holding the authentication field. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the authentication field in Bytes. + * 0, 4, 6, 8, 10, 12, 14 or 16. + * + * \warning Passing \c 0 as \p tag_len means that the message is nos + * longer authenticated. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_AUTH_FAILED if the tag does not match. + * \return A cipher-specific error code on calculation failure. + */ +int mbedtls_ccm_star_auth_decrypt(mbedtls_ccm_context *ctx, size_t length, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, unsigned char *output, + const unsigned char *tag, size_t tag_len); + +/** + * \brief This function starts a CCM encryption or decryption + * operation. + * + * This function and mbedtls_ccm_set_lengths() must be called + * before calling mbedtls_ccm_update_ad() or + * mbedtls_ccm_update(). This function can be called before + * or after mbedtls_ccm_set_lengths(). + * + * \note This function is not implemented in Mbed TLS yet. + * + * \param ctx The CCM context. This must be initialized. + * \param mode The operation to perform: #MBEDTLS_CCM_ENCRYPT or + * #MBEDTLS_CCM_DECRYPT or #MBEDTLS_CCM_STAR_ENCRYPT or + * #MBEDTLS_CCM_STAR_DECRYPT. + * \param iv The initialization vector. This must be a readable buffer + * of at least \p iv_len Bytes. + * \param iv_len The length of the nonce in Bytes: 7, 8, 9, 10, 11, 12, + * or 13. The length L of the message length field is + * 15 - \p iv_len. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: + * \p ctx is in an invalid state, + * \p mode is invalid, + * \p iv_len is invalid (lower than \c 7 or greater than + * \c 13). + */ +int mbedtls_ccm_starts(mbedtls_ccm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len); + +/** + * \brief This function declares the lengths of the message + * and additional data for a CCM encryption or decryption + * operation. + * + * This function and mbedtls_ccm_starts() must be called + * before calling mbedtls_ccm_update_ad() or + * mbedtls_ccm_update(). This function can be called before + * or after mbedtls_ccm_starts(). + * + * \note This function is not implemented in Mbed TLS yet. + * + * \param ctx The CCM context. This must be initialized. + * \param total_ad_len The total length of additional data in bytes. + * This must be less than `2^16 - 2^8`. + * \param plaintext_len The length in bytes of the plaintext to encrypt or + * result of the decryption (thus not encompassing the + * additional data that are not encrypted). + * \param tag_len The length of the tag to generate in Bytes: + * 4, 6, 8, 10, 12, 14 or 16. + * For CCM*, zero is also valid. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: + * \p ctx is in an invalid state, + * \p total_ad_len is greater than \c 0xFF00. + */ +int mbedtls_ccm_set_lengths(mbedtls_ccm_context *ctx, + size_t total_ad_len, + size_t plaintext_len, + size_t tag_len); + +/** + * \brief This function feeds an input buffer as associated data + * (authenticated but not encrypted data) in a CCM + * encryption or decryption operation. + * + * You may call this function zero, one or more times + * to pass successive parts of the additional data. The + * lengths \p ad_len of the data parts should eventually add + * up exactly to the total length of additional data + * \c total_ad_len passed to mbedtls_ccm_set_lengths(). You + * may not call this function after calling + * mbedtls_ccm_update(). + * + * \note This function is not implemented in Mbed TLS yet. + * + * \param ctx The CCM context. This must have been started with + * mbedtls_ccm_starts(), the lengths of the message and + * additional data must have been declared with + * mbedtls_ccm_set_lengths() and this must not have yet + * received any input with mbedtls_ccm_update(). + * \param ad The buffer holding the additional data, or \c NULL + * if \p ad_len is \c 0. + * \param ad_len The length of the additional data. If \c 0, + * \p ad may be \c NULL. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: + * \p ctx is in an invalid state, + * total input length too long. + */ +int mbedtls_ccm_update_ad(mbedtls_ccm_context *ctx, + const unsigned char *ad, + size_t ad_len); + +/** + * \brief This function feeds an input buffer into an ongoing CCM + * encryption or decryption operation. + * + * You may call this function zero, one or more times + * to pass successive parts of the input: the plaintext to + * encrypt, or the ciphertext (not including the tag) to + * decrypt. After the last part of the input, call + * mbedtls_ccm_finish(). The lengths \p input_len of the + * data parts should eventually add up exactly to the + * plaintext length \c plaintext_len passed to + * mbedtls_ccm_set_lengths(). + * + * This function may produce output in one of the following + * ways: + * - Immediate output: the output length is always equal + * to the input length. + * - Buffered output: except for the last part of input data, + * the output consists of a whole number of 16-byte blocks. + * If the total input length so far (not including + * associated data) is 16 \* *B* + *A* with *A* < 16 then + * the total output length is 16 \* *B*. + * For the last part of input data, the output length is + * equal to the input length plus the number of bytes (*A*) + * buffered in the previous call to the function (if any). + * The function uses the plaintext length + * \c plaintext_len passed to mbedtls_ccm_set_lengths() + * to detect the last part of input data. + * + * In particular: + * - It is always correct to call this function with + * \p output_size >= \p input_len + 15. + * - If \p input_len is a multiple of 16 for all the calls + * to this function during an operation (not necessary for + * the last one) then it is correct to use \p output_size + * =\p input_len. + * + * \note This function is not implemented in Mbed TLS yet. + * + * \param ctx The CCM context. This must have been started with + * mbedtls_ccm_starts() and the lengths of the message and + * additional data must have been declared with + * mbedtls_ccm_set_lengths(). + * \param input The buffer holding the input data. If \p input_len + * is greater than zero, this must be a readable buffer + * of at least \p input_len bytes. + * \param input_len The length of the input data in bytes. + * \param output The buffer for the output data. If \p output_size + * is greater than zero, this must be a writable buffer of + * at least \p output_size bytes. + * \param output_size The size of the output buffer in bytes. + * See the function description regarding the output size. + * \param output_len On success, \p *output_len contains the actual + * length of the output written in \p output. + * On failure, the content of \p *output_len is + * unspecified. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: + * \p ctx is in an invalid state, + * total input length too long, + * or \p output_size too small. + */ +int mbedtls_ccm_update(mbedtls_ccm_context *ctx, + const unsigned char *input, size_t input_len, + unsigned char *output, size_t output_size, + size_t *output_len); + +/** + * \brief This function finishes the CCM operation and generates + * the authentication tag. + * + * It wraps up the CCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \note This function is not implemented in Mbed TLS yet. + * + * \param ctx The CCM context. This must have been started with + * mbedtls_ccm_starts() and the lengths of the message and + * additional data must have been declared with + * mbedtls_ccm_set_lengths(). + * \param tag The buffer for holding the tag. If \p tag_len is greater + * than zero, this must be a writable buffer of at least \p + * tag_len Bytes. + * \param tag_len The length of the tag. Must match the tag length passed to + * mbedtls_ccm_set_lengths() function. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CCM_BAD_INPUT on failure: + * \p ctx is in an invalid state, + * invalid value of \p tag_len, + * the total amount of additional data passed to + * mbedtls_ccm_update_ad() was lower than the total length of + * additional data \c total_ad_len passed to + * mbedtls_ccm_set_lengths(), + * the total amount of input data passed to + * mbedtls_ccm_update() was lower than the plaintext length + * \c plaintext_len passed to mbedtls_ccm_set_lengths(). + */ +int mbedtls_ccm_finish(mbedtls_ccm_context *ctx, + unsigned char *tag, size_t tag_len); + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +/** + * \brief The CCM checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ccm_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CCM_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chacha20.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chacha20.h index e24e56b..f7f5702 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chacha20.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chacha20.h @@ -1,214 +1,214 @@ -/** - * \file chacha20.h - * - * \brief This file contains ChaCha20 definitions and functions. - * - * ChaCha20 is a stream cipher that can encrypt and decrypt - * information. ChaCha was created by Daniel Bernstein as a variant of - * its Salsa cipher https://cr.yp.to/chacha/chacha-20080128.pdf - * ChaCha20 is the variant with 20 rounds, that was also standardized - * in RFC 7539. - * - * \author Daniel King - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CHACHA20_H -#define MBEDTLS_CHACHA20_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -/** Invalid input parameter(s). */ -#define MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA -0x0051 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_CHACHA20_ALT) - -typedef struct mbedtls_chacha20_context { - uint32_t MBEDTLS_PRIVATE(state)[16]; /*! The state (before round operations). */ - uint8_t MBEDTLS_PRIVATE(keystream8)[64]; /*! Leftover keystream bytes. */ - size_t MBEDTLS_PRIVATE(keystream_bytes_used); /*! Number of keystream bytes already used. */ -} -mbedtls_chacha20_context; - -#else /* MBEDTLS_CHACHA20_ALT */ -#include "chacha20_alt.h" -#endif /* MBEDTLS_CHACHA20_ALT */ - -/** - * \brief This function initializes the specified ChaCha20 context. - * - * It must be the first API called before using - * the context. - * - * It is usually followed by calls to - * \c mbedtls_chacha20_setkey() and - * \c mbedtls_chacha20_starts(), then one or more calls to - * to \c mbedtls_chacha20_update(), and finally to - * \c mbedtls_chacha20_free(). - * - * \param ctx The ChaCha20 context to initialize. - * This must not be \c NULL. - */ -void mbedtls_chacha20_init(mbedtls_chacha20_context *ctx); - -/** - * \brief This function releases and clears the specified - * ChaCha20 context. - * - * \param ctx The ChaCha20 context to clear. This may be \c NULL, - * in which case this function is a no-op. If it is not - * \c NULL, it must point to an initialized context. - * - */ -void mbedtls_chacha20_free(mbedtls_chacha20_context *ctx); - -/** - * \brief This function sets the encryption/decryption key. - * - * \note After using this function, you must also call - * \c mbedtls_chacha20_starts() to set a nonce before you - * start encrypting/decrypting data with - * \c mbedtls_chacha_update(). - * - * \param ctx The ChaCha20 context to which the key should be bound. - * It must be initialized. - * \param key The encryption/decryption key. This must be \c 32 Bytes - * in length. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or key is NULL. - */ -int mbedtls_chacha20_setkey(mbedtls_chacha20_context *ctx, - const unsigned char key[32]); - -/** - * \brief This function sets the nonce and initial counter value. - * - * \note A ChaCha20 context can be re-used with the same key by - * calling this function to change the nonce. - * - * \warning You must never use the same nonce twice with the same key. - * This would void any confidentiality guarantees for the - * messages encrypted with the same nonce and key. - * - * \param ctx The ChaCha20 context to which the nonce should be bound. - * It must be initialized and bound to a key. - * \param nonce The nonce. This must be \c 12 Bytes in size. - * \param counter The initial counter value. This is usually \c 0. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or nonce is - * NULL. - */ -int mbedtls_chacha20_starts(mbedtls_chacha20_context *ctx, - const unsigned char nonce[12], - uint32_t counter); - -/** - * \brief This function encrypts or decrypts data. - * - * Since ChaCha20 is a stream cipher, the same operation is - * used for encrypting and decrypting data. - * - * \note The \p input and \p output pointers must either be equal or - * point to non-overlapping buffers. - * - * \note \c mbedtls_chacha20_setkey() and - * \c mbedtls_chacha20_starts() must be called at least once - * to setup the context before this function can be called. - * - * \note This function can be called multiple times in a row in - * order to encrypt of decrypt data piecewise with the same - * key and nonce. - * - * \param ctx The ChaCha20 context to use for encryption or decryption. - * It must be initialized and bound to a key and nonce. - * \param size The length of the input data in Bytes. - * \param input The buffer holding the input data. - * This pointer can be \c NULL if `size == 0`. - * \param output The buffer holding the output data. - * This must be able to hold \p size Bytes. - * This pointer can be \c NULL if `size == 0`. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_chacha20_update(mbedtls_chacha20_context *ctx, - size_t size, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function encrypts or decrypts data with ChaCha20 and - * the given key and nonce. - * - * Since ChaCha20 is a stream cipher, the same operation is - * used for encrypting and decrypting data. - * - * \warning You must never use the same (key, nonce) pair more than - * once. This would void any confidentiality guarantees for - * the messages encrypted with the same nonce and key. - * - * \note The \p input and \p output pointers must either be equal or - * point to non-overlapping buffers. - * - * \param key The encryption/decryption key. - * This must be \c 32 Bytes in length. - * \param nonce The nonce. This must be \c 12 Bytes in size. - * \param counter The initial counter value. This is usually \c 0. - * \param size The length of the input data in Bytes. - * \param input The buffer holding the input data. - * This pointer can be \c NULL if `size == 0`. - * \param output The buffer holding the output data. - * This must be able to hold \p size Bytes. - * This pointer can be \c NULL if `size == 0`. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_chacha20_crypt(const unsigned char key[32], - const unsigned char nonce[12], - uint32_t counter, - size_t size, - const unsigned char *input, - unsigned char *output); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief The ChaCha20 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_chacha20_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CHACHA20_H */ +/** + * \file chacha20.h + * + * \brief This file contains ChaCha20 definitions and functions. + * + * ChaCha20 is a stream cipher that can encrypt and decrypt + * information. ChaCha was created by Daniel Bernstein as a variant of + * its Salsa cipher https://cr.yp.to/chacha/chacha-20080128.pdf + * ChaCha20 is the variant with 20 rounds, that was also standardized + * in RFC 7539. + * + * \author Daniel King + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CHACHA20_H +#define MBEDTLS_CHACHA20_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +/** Invalid input parameter(s). */ +#define MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA -0x0051 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_CHACHA20_ALT) + +typedef struct mbedtls_chacha20_context { + uint32_t MBEDTLS_PRIVATE(state)[16]; /*! The state (before round operations). */ + uint8_t MBEDTLS_PRIVATE(keystream8)[64]; /*! Leftover keystream bytes. */ + size_t MBEDTLS_PRIVATE(keystream_bytes_used); /*! Number of keystream bytes already used. */ +} +mbedtls_chacha20_context; + +#else /* MBEDTLS_CHACHA20_ALT */ +#include "chacha20_alt.h" +#endif /* MBEDTLS_CHACHA20_ALT */ + +/** + * \brief This function initializes the specified ChaCha20 context. + * + * It must be the first API called before using + * the context. + * + * It is usually followed by calls to + * \c mbedtls_chacha20_setkey() and + * \c mbedtls_chacha20_starts(), then one or more calls to + * to \c mbedtls_chacha20_update(), and finally to + * \c mbedtls_chacha20_free(). + * + * \param ctx The ChaCha20 context to initialize. + * This must not be \c NULL. + */ +void mbedtls_chacha20_init(mbedtls_chacha20_context *ctx); + +/** + * \brief This function releases and clears the specified + * ChaCha20 context. + * + * \param ctx The ChaCha20 context to clear. This may be \c NULL, + * in which case this function is a no-op. If it is not + * \c NULL, it must point to an initialized context. + * + */ +void mbedtls_chacha20_free(mbedtls_chacha20_context *ctx); + +/** + * \brief This function sets the encryption/decryption key. + * + * \note After using this function, you must also call + * \c mbedtls_chacha20_starts() to set a nonce before you + * start encrypting/decrypting data with + * \c mbedtls_chacha_update(). + * + * \param ctx The ChaCha20 context to which the key should be bound. + * It must be initialized. + * \param key The encryption/decryption key. This must be \c 32 Bytes + * in length. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or key is NULL. + */ +int mbedtls_chacha20_setkey(mbedtls_chacha20_context *ctx, + const unsigned char key[32]); + +/** + * \brief This function sets the nonce and initial counter value. + * + * \note A ChaCha20 context can be re-used with the same key by + * calling this function to change the nonce. + * + * \warning You must never use the same nonce twice with the same key. + * This would void any confidentiality guarantees for the + * messages encrypted with the same nonce and key. + * + * \param ctx The ChaCha20 context to which the nonce should be bound. + * It must be initialized and bound to a key. + * \param nonce The nonce. This must be \c 12 Bytes in size. + * \param counter The initial counter value. This is usually \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA if ctx or nonce is + * NULL. + */ +int mbedtls_chacha20_starts(mbedtls_chacha20_context *ctx, + const unsigned char nonce[12], + uint32_t counter); + +/** + * \brief This function encrypts or decrypts data. + * + * Since ChaCha20 is a stream cipher, the same operation is + * used for encrypting and decrypting data. + * + * \note The \p input and \p output pointers must either be equal or + * point to non-overlapping buffers. + * + * \note \c mbedtls_chacha20_setkey() and + * \c mbedtls_chacha20_starts() must be called at least once + * to setup the context before this function can be called. + * + * \note This function can be called multiple times in a row in + * order to encrypt of decrypt data piecewise with the same + * key and nonce. + * + * \param ctx The ChaCha20 context to use for encryption or decryption. + * It must be initialized and bound to a key and nonce. + * \param size The length of the input data in Bytes. + * \param input The buffer holding the input data. + * This pointer can be \c NULL if `size == 0`. + * \param output The buffer holding the output data. + * This must be able to hold \p size Bytes. + * This pointer can be \c NULL if `size == 0`. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_chacha20_update(mbedtls_chacha20_context *ctx, + size_t size, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function encrypts or decrypts data with ChaCha20 and + * the given key and nonce. + * + * Since ChaCha20 is a stream cipher, the same operation is + * used for encrypting and decrypting data. + * + * \warning You must never use the same (key, nonce) pair more than + * once. This would void any confidentiality guarantees for + * the messages encrypted with the same nonce and key. + * + * \note The \p input and \p output pointers must either be equal or + * point to non-overlapping buffers. + * + * \param key The encryption/decryption key. + * This must be \c 32 Bytes in length. + * \param nonce The nonce. This must be \c 12 Bytes in size. + * \param counter The initial counter value. This is usually \c 0. + * \param size The length of the input data in Bytes. + * \param input The buffer holding the input data. + * This pointer can be \c NULL if `size == 0`. + * \param output The buffer holding the output data. + * This must be able to hold \p size Bytes. + * This pointer can be \c NULL if `size == 0`. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_chacha20_crypt(const unsigned char key[32], + const unsigned char nonce[12], + uint32_t counter, + size_t size, + const unsigned char *input, + unsigned char *output); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief The ChaCha20 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_chacha20_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CHACHA20_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chachapoly.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chachapoly.h index 19baade..e442bd9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chachapoly.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/chachapoly.h @@ -1,354 +1,354 @@ -/** - * \file chachapoly.h - * - * \brief This file contains the AEAD-ChaCha20-Poly1305 definitions and - * functions. - * - * ChaCha20-Poly1305 is an algorithm for Authenticated Encryption - * with Associated Data (AEAD) that can be used to encrypt and - * authenticate data. It is based on ChaCha20 and Poly1305 by Daniel - * Bernstein and was standardized in RFC 7539. - * - * \author Daniel King - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CHACHAPOLY_H -#define MBEDTLS_CHACHAPOLY_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -/* for shared error codes */ -#include "mbedtls/poly1305.h" - -/** The requested operation is not permitted in the current state. */ -#define MBEDTLS_ERR_CHACHAPOLY_BAD_STATE -0x0054 -/** Authenticated decryption failed: data was not authentic. */ -#define MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED -0x0056 - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - MBEDTLS_CHACHAPOLY_ENCRYPT, /**< The mode value for performing encryption. */ - MBEDTLS_CHACHAPOLY_DECRYPT /**< The mode value for performing decryption. */ -} -mbedtls_chachapoly_mode_t; - -#if !defined(MBEDTLS_CHACHAPOLY_ALT) - -#include "mbedtls/chacha20.h" - -typedef struct mbedtls_chachapoly_context { - mbedtls_chacha20_context MBEDTLS_PRIVATE(chacha20_ctx); /**< The ChaCha20 context. */ - mbedtls_poly1305_context MBEDTLS_PRIVATE(poly1305_ctx); /**< The Poly1305 context. */ - uint64_t MBEDTLS_PRIVATE(aad_len); /**< The length (bytes) of the Additional Authenticated Data. */ - uint64_t MBEDTLS_PRIVATE(ciphertext_len); /**< The length (bytes) of the ciphertext. */ - int MBEDTLS_PRIVATE(state); /**< The current state of the context. */ - mbedtls_chachapoly_mode_t MBEDTLS_PRIVATE(mode); /**< Cipher mode (encrypt or decrypt). */ -} -mbedtls_chachapoly_context; - -#else /* !MBEDTLS_CHACHAPOLY_ALT */ -#include "chachapoly_alt.h" -#endif /* !MBEDTLS_CHACHAPOLY_ALT */ - -/** - * \brief This function initializes the specified ChaCha20-Poly1305 context. - * - * It must be the first API called before using - * the context. It must be followed by a call to - * \c mbedtls_chachapoly_setkey() before any operation can be - * done, and to \c mbedtls_chachapoly_free() once all - * operations with that context have been finished. - * - * In order to encrypt or decrypt full messages at once, for - * each message you should make a single call to - * \c mbedtls_chachapoly_crypt_and_tag() or - * \c mbedtls_chachapoly_auth_decrypt(). - * - * In order to encrypt messages piecewise, for each - * message you should make a call to - * \c mbedtls_chachapoly_starts(), then 0 or more calls to - * \c mbedtls_chachapoly_update_aad(), then 0 or more calls to - * \c mbedtls_chachapoly_update(), then one call to - * \c mbedtls_chachapoly_finish(). - * - * \warning Decryption with the piecewise API is discouraged! Always - * use \c mbedtls_chachapoly_auth_decrypt() when possible! - * - * If however this is not possible because the data is too - * large to fit in memory, you need to: - * - * - call \c mbedtls_chachapoly_starts() and (if needed) - * \c mbedtls_chachapoly_update_aad() as above, - * - call \c mbedtls_chachapoly_update() multiple times and - * ensure its output (the plaintext) is NOT used in any other - * way than placing it in temporary storage at this point, - * - call \c mbedtls_chachapoly_finish() to compute the - * authentication tag and compared it in constant time to the - * tag received with the ciphertext. - * - * If the tags are not equal, you must immediately discard - * all previous outputs of \c mbedtls_chachapoly_update(), - * otherwise you can now safely use the plaintext. - * - * \param ctx The ChachaPoly context to initialize. Must not be \c NULL. - */ -void mbedtls_chachapoly_init(mbedtls_chachapoly_context *ctx); - -/** - * \brief This function releases and clears the specified - * ChaCha20-Poly1305 context. - * - * \param ctx The ChachaPoly context to clear. This may be \c NULL, in which - * case this function is a no-op. - */ -void mbedtls_chachapoly_free(mbedtls_chachapoly_context *ctx); - -/** - * \brief This function sets the ChaCha20-Poly1305 - * symmetric encryption key. - * - * \param ctx The ChaCha20-Poly1305 context to which the key should be - * bound. This must be initialized. - * \param key The \c 256 Bit (\c 32 Bytes) key. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_chachapoly_setkey(mbedtls_chachapoly_context *ctx, - const unsigned char key[32]); - -/** - * \brief This function starts a ChaCha20-Poly1305 encryption or - * decryption operation. - * - * \warning You must never use the same nonce twice with the same key. - * This would void any confidentiality and authenticity - * guarantees for the messages encrypted with the same nonce - * and key. - * - * \note If the context is being used for AAD only (no data to - * encrypt or decrypt) then \p mode can be set to any value. - * - * \warning Decryption with the piecewise API is discouraged, see the - * warning on \c mbedtls_chachapoly_init(). - * - * \param ctx The ChaCha20-Poly1305 context. This must be initialized - * and bound to a key. - * \param nonce The nonce/IV to use for the message. - * This must be a readable buffer of length \c 12 Bytes. - * \param mode The operation to perform: #MBEDTLS_CHACHAPOLY_ENCRYPT or - * #MBEDTLS_CHACHAPOLY_DECRYPT (discouraged, see warning). - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_chachapoly_starts(mbedtls_chachapoly_context *ctx, - const unsigned char nonce[12], - mbedtls_chachapoly_mode_t mode); - -/** - * \brief This function feeds additional data to be authenticated - * into an ongoing ChaCha20-Poly1305 operation. - * - * The Additional Authenticated Data (AAD), also called - * Associated Data (AD) is only authenticated but not - * encrypted nor included in the encrypted output. It is - * usually transmitted separately from the ciphertext or - * computed locally by each party. - * - * \note This function is called before data is encrypted/decrypted. - * I.e. call this function to process the AAD before calling - * \c mbedtls_chachapoly_update(). - * - * You may call this function multiple times to process - * an arbitrary amount of AAD. It is permitted to call - * this function 0 times, if no AAD is used. - * - * This function cannot be called any more if data has - * been processed by \c mbedtls_chachapoly_update(), - * or if the context has been finished. - * - * \warning Decryption with the piecewise API is discouraged, see the - * warning on \c mbedtls_chachapoly_init(). - * - * \param ctx The ChaCha20-Poly1305 context. This must be initialized - * and bound to a key. - * \param aad_len The length in Bytes of the AAD. The length has no - * restrictions. - * \param aad Buffer containing the AAD. - * This pointer can be \c NULL if `aad_len == 0`. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA - * if \p ctx or \p aad are NULL. - * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE - * if the operations has not been started or has been - * finished, or if the AAD has been finished. - */ -int mbedtls_chachapoly_update_aad(mbedtls_chachapoly_context *ctx, - const unsigned char *aad, - size_t aad_len); - -/** - * \brief Thus function feeds data to be encrypted or decrypted - * into an on-going ChaCha20-Poly1305 - * operation. - * - * The direction (encryption or decryption) depends on the - * mode that was given when calling - * \c mbedtls_chachapoly_starts(). - * - * You may call this function multiple times to process - * an arbitrary amount of data. It is permitted to call - * this function 0 times, if no data is to be encrypted - * or decrypted. - * - * \warning Decryption with the piecewise API is discouraged, see the - * warning on \c mbedtls_chachapoly_init(). - * - * \param ctx The ChaCha20-Poly1305 context to use. This must be initialized. - * \param len The length (in bytes) of the data to encrypt or decrypt. - * \param input The buffer containing the data to encrypt or decrypt. - * This pointer can be \c NULL if `len == 0`. - * \param output The buffer to where the encrypted or decrypted data is - * written. This must be able to hold \p len bytes. - * This pointer can be \c NULL if `len == 0`. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE - * if the operation has not been started or has been - * finished. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_chachapoly_update(mbedtls_chachapoly_context *ctx, - size_t len, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function finished the ChaCha20-Poly1305 operation and - * generates the MAC (authentication tag). - * - * \param ctx The ChaCha20-Poly1305 context to use. This must be initialized. - * \param mac The buffer to where the 128-bit (16 bytes) MAC is written. - * - * \warning Decryption with the piecewise API is discouraged, see the - * warning on \c mbedtls_chachapoly_init(). - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE - * if the operation has not been started or has been - * finished. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_chachapoly_finish(mbedtls_chachapoly_context *ctx, - unsigned char mac[16]); - -/** - * \brief This function performs a complete ChaCha20-Poly1305 - * authenticated encryption with the previously-set key. - * - * \note Before using this function, you must set the key with - * \c mbedtls_chachapoly_setkey(). - * - * \warning You must never use the same nonce twice with the same key. - * This would void any confidentiality and authenticity - * guarantees for the messages encrypted with the same nonce - * and key. - * - * \param ctx The ChaCha20-Poly1305 context to use (holds the key). - * This must be initialized. - * \param length The length (in bytes) of the data to encrypt or decrypt. - * \param nonce The 96-bit (12 bytes) nonce/IV to use. - * \param aad The buffer containing the additional authenticated - * data (AAD). This pointer can be \c NULL if `aad_len == 0`. - * \param aad_len The length (in bytes) of the AAD data to process. - * \param input The buffer containing the data to encrypt or decrypt. - * This pointer can be \c NULL if `ilen == 0`. - * \param output The buffer to where the encrypted or decrypted data - * is written. This pointer can be \c NULL if `ilen == 0`. - * \param tag The buffer to where the computed 128-bit (16 bytes) MAC - * is written. This must not be \c NULL. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_chachapoly_encrypt_and_tag(mbedtls_chachapoly_context *ctx, - size_t length, - const unsigned char nonce[12], - const unsigned char *aad, - size_t aad_len, - const unsigned char *input, - unsigned char *output, - unsigned char tag[16]); - -/** - * \brief This function performs a complete ChaCha20-Poly1305 - * authenticated decryption with the previously-set key. - * - * \note Before using this function, you must set the key with - * \c mbedtls_chachapoly_setkey(). - * - * \param ctx The ChaCha20-Poly1305 context to use (holds the key). - * \param length The length (in Bytes) of the data to decrypt. - * \param nonce The \c 96 Bit (\c 12 bytes) nonce/IV to use. - * \param aad The buffer containing the additional authenticated data (AAD). - * This pointer can be \c NULL if `aad_len == 0`. - * \param aad_len The length (in bytes) of the AAD data to process. - * \param tag The buffer holding the authentication tag. - * This must be a readable buffer of length \c 16 Bytes. - * \param input The buffer containing the data to decrypt. - * This pointer can be \c NULL if `ilen == 0`. - * \param output The buffer to where the decrypted data is written. - * This pointer can be \c NULL if `ilen == 0`. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED - * if the data was not authentic. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_chachapoly_auth_decrypt(mbedtls_chachapoly_context *ctx, - size_t length, - const unsigned char nonce[12], - const unsigned char *aad, - size_t aad_len, - const unsigned char tag[16], - const unsigned char *input, - unsigned char *output); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief The ChaCha20-Poly1305 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_chachapoly_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CHACHAPOLY_H */ +/** + * \file chachapoly.h + * + * \brief This file contains the AEAD-ChaCha20-Poly1305 definitions and + * functions. + * + * ChaCha20-Poly1305 is an algorithm for Authenticated Encryption + * with Associated Data (AEAD) that can be used to encrypt and + * authenticate data. It is based on ChaCha20 and Poly1305 by Daniel + * Bernstein and was standardized in RFC 7539. + * + * \author Daniel King + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CHACHAPOLY_H +#define MBEDTLS_CHACHAPOLY_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +/* for shared error codes */ +#include "mbedtls/poly1305.h" + +/** The requested operation is not permitted in the current state. */ +#define MBEDTLS_ERR_CHACHAPOLY_BAD_STATE -0x0054 +/** Authenticated decryption failed: data was not authentic. */ +#define MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED -0x0056 + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + MBEDTLS_CHACHAPOLY_ENCRYPT, /**< The mode value for performing encryption. */ + MBEDTLS_CHACHAPOLY_DECRYPT /**< The mode value for performing decryption. */ +} +mbedtls_chachapoly_mode_t; + +#if !defined(MBEDTLS_CHACHAPOLY_ALT) + +#include "mbedtls/chacha20.h" + +typedef struct mbedtls_chachapoly_context { + mbedtls_chacha20_context MBEDTLS_PRIVATE(chacha20_ctx); /**< The ChaCha20 context. */ + mbedtls_poly1305_context MBEDTLS_PRIVATE(poly1305_ctx); /**< The Poly1305 context. */ + uint64_t MBEDTLS_PRIVATE(aad_len); /**< The length (bytes) of the Additional Authenticated Data. */ + uint64_t MBEDTLS_PRIVATE(ciphertext_len); /**< The length (bytes) of the ciphertext. */ + int MBEDTLS_PRIVATE(state); /**< The current state of the context. */ + mbedtls_chachapoly_mode_t MBEDTLS_PRIVATE(mode); /**< Cipher mode (encrypt or decrypt). */ +} +mbedtls_chachapoly_context; + +#else /* !MBEDTLS_CHACHAPOLY_ALT */ +#include "chachapoly_alt.h" +#endif /* !MBEDTLS_CHACHAPOLY_ALT */ + +/** + * \brief This function initializes the specified ChaCha20-Poly1305 context. + * + * It must be the first API called before using + * the context. It must be followed by a call to + * \c mbedtls_chachapoly_setkey() before any operation can be + * done, and to \c mbedtls_chachapoly_free() once all + * operations with that context have been finished. + * + * In order to encrypt or decrypt full messages at once, for + * each message you should make a single call to + * \c mbedtls_chachapoly_crypt_and_tag() or + * \c mbedtls_chachapoly_auth_decrypt(). + * + * In order to encrypt messages piecewise, for each + * message you should make a call to + * \c mbedtls_chachapoly_starts(), then 0 or more calls to + * \c mbedtls_chachapoly_update_aad(), then 0 or more calls to + * \c mbedtls_chachapoly_update(), then one call to + * \c mbedtls_chachapoly_finish(). + * + * \warning Decryption with the piecewise API is discouraged! Always + * use \c mbedtls_chachapoly_auth_decrypt() when possible! + * + * If however this is not possible because the data is too + * large to fit in memory, you need to: + * + * - call \c mbedtls_chachapoly_starts() and (if needed) + * \c mbedtls_chachapoly_update_aad() as above, + * - call \c mbedtls_chachapoly_update() multiple times and + * ensure its output (the plaintext) is NOT used in any other + * way than placing it in temporary storage at this point, + * - call \c mbedtls_chachapoly_finish() to compute the + * authentication tag and compared it in constant time to the + * tag received with the ciphertext. + * + * If the tags are not equal, you must immediately discard + * all previous outputs of \c mbedtls_chachapoly_update(), + * otherwise you can now safely use the plaintext. + * + * \param ctx The ChachaPoly context to initialize. Must not be \c NULL. + */ +void mbedtls_chachapoly_init(mbedtls_chachapoly_context *ctx); + +/** + * \brief This function releases and clears the specified + * ChaCha20-Poly1305 context. + * + * \param ctx The ChachaPoly context to clear. This may be \c NULL, in which + * case this function is a no-op. + */ +void mbedtls_chachapoly_free(mbedtls_chachapoly_context *ctx); + +/** + * \brief This function sets the ChaCha20-Poly1305 + * symmetric encryption key. + * + * \param ctx The ChaCha20-Poly1305 context to which the key should be + * bound. This must be initialized. + * \param key The \c 256 Bit (\c 32 Bytes) key. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_chachapoly_setkey(mbedtls_chachapoly_context *ctx, + const unsigned char key[32]); + +/** + * \brief This function starts a ChaCha20-Poly1305 encryption or + * decryption operation. + * + * \warning You must never use the same nonce twice with the same key. + * This would void any confidentiality and authenticity + * guarantees for the messages encrypted with the same nonce + * and key. + * + * \note If the context is being used for AAD only (no data to + * encrypt or decrypt) then \p mode can be set to any value. + * + * \warning Decryption with the piecewise API is discouraged, see the + * warning on \c mbedtls_chachapoly_init(). + * + * \param ctx The ChaCha20-Poly1305 context. This must be initialized + * and bound to a key. + * \param nonce The nonce/IV to use for the message. + * This must be a readable buffer of length \c 12 Bytes. + * \param mode The operation to perform: #MBEDTLS_CHACHAPOLY_ENCRYPT or + * #MBEDTLS_CHACHAPOLY_DECRYPT (discouraged, see warning). + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_chachapoly_starts(mbedtls_chachapoly_context *ctx, + const unsigned char nonce[12], + mbedtls_chachapoly_mode_t mode); + +/** + * \brief This function feeds additional data to be authenticated + * into an ongoing ChaCha20-Poly1305 operation. + * + * The Additional Authenticated Data (AAD), also called + * Associated Data (AD) is only authenticated but not + * encrypted nor included in the encrypted output. It is + * usually transmitted separately from the ciphertext or + * computed locally by each party. + * + * \note This function is called before data is encrypted/decrypted. + * I.e. call this function to process the AAD before calling + * \c mbedtls_chachapoly_update(). + * + * You may call this function multiple times to process + * an arbitrary amount of AAD. It is permitted to call + * this function 0 times, if no AAD is used. + * + * This function cannot be called any more if data has + * been processed by \c mbedtls_chachapoly_update(), + * or if the context has been finished. + * + * \warning Decryption with the piecewise API is discouraged, see the + * warning on \c mbedtls_chachapoly_init(). + * + * \param ctx The ChaCha20-Poly1305 context. This must be initialized + * and bound to a key. + * \param aad_len The length in Bytes of the AAD. The length has no + * restrictions. + * \param aad Buffer containing the AAD. + * This pointer can be \c NULL if `aad_len == 0`. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA + * if \p ctx or \p aad are NULL. + * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE + * if the operations has not been started or has been + * finished, or if the AAD has been finished. + */ +int mbedtls_chachapoly_update_aad(mbedtls_chachapoly_context *ctx, + const unsigned char *aad, + size_t aad_len); + +/** + * \brief Thus function feeds data to be encrypted or decrypted + * into an on-going ChaCha20-Poly1305 + * operation. + * + * The direction (encryption or decryption) depends on the + * mode that was given when calling + * \c mbedtls_chachapoly_starts(). + * + * You may call this function multiple times to process + * an arbitrary amount of data. It is permitted to call + * this function 0 times, if no data is to be encrypted + * or decrypted. + * + * \warning Decryption with the piecewise API is discouraged, see the + * warning on \c mbedtls_chachapoly_init(). + * + * \param ctx The ChaCha20-Poly1305 context to use. This must be initialized. + * \param len The length (in bytes) of the data to encrypt or decrypt. + * \param input The buffer containing the data to encrypt or decrypt. + * This pointer can be \c NULL if `len == 0`. + * \param output The buffer to where the encrypted or decrypted data is + * written. This must be able to hold \p len bytes. + * This pointer can be \c NULL if `len == 0`. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE + * if the operation has not been started or has been + * finished. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_chachapoly_update(mbedtls_chachapoly_context *ctx, + size_t len, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function finished the ChaCha20-Poly1305 operation and + * generates the MAC (authentication tag). + * + * \param ctx The ChaCha20-Poly1305 context to use. This must be initialized. + * \param mac The buffer to where the 128-bit (16 bytes) MAC is written. + * + * \warning Decryption with the piecewise API is discouraged, see the + * warning on \c mbedtls_chachapoly_init(). + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CHACHAPOLY_BAD_STATE + * if the operation has not been started or has been + * finished. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_chachapoly_finish(mbedtls_chachapoly_context *ctx, + unsigned char mac[16]); + +/** + * \brief This function performs a complete ChaCha20-Poly1305 + * authenticated encryption with the previously-set key. + * + * \note Before using this function, you must set the key with + * \c mbedtls_chachapoly_setkey(). + * + * \warning You must never use the same nonce twice with the same key. + * This would void any confidentiality and authenticity + * guarantees for the messages encrypted with the same nonce + * and key. + * + * \param ctx The ChaCha20-Poly1305 context to use (holds the key). + * This must be initialized. + * \param length The length (in bytes) of the data to encrypt or decrypt. + * \param nonce The 96-bit (12 bytes) nonce/IV to use. + * \param aad The buffer containing the additional authenticated + * data (AAD). This pointer can be \c NULL if `aad_len == 0`. + * \param aad_len The length (in bytes) of the AAD data to process. + * \param input The buffer containing the data to encrypt or decrypt. + * This pointer can be \c NULL if `ilen == 0`. + * \param output The buffer to where the encrypted or decrypted data + * is written. This pointer can be \c NULL if `ilen == 0`. + * \param tag The buffer to where the computed 128-bit (16 bytes) MAC + * is written. This must not be \c NULL. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_chachapoly_encrypt_and_tag(mbedtls_chachapoly_context *ctx, + size_t length, + const unsigned char nonce[12], + const unsigned char *aad, + size_t aad_len, + const unsigned char *input, + unsigned char *output, + unsigned char tag[16]); + +/** + * \brief This function performs a complete ChaCha20-Poly1305 + * authenticated decryption with the previously-set key. + * + * \note Before using this function, you must set the key with + * \c mbedtls_chachapoly_setkey(). + * + * \param ctx The ChaCha20-Poly1305 context to use (holds the key). + * \param length The length (in Bytes) of the data to decrypt. + * \param nonce The \c 96 Bit (\c 12 bytes) nonce/IV to use. + * \param aad The buffer containing the additional authenticated data (AAD). + * This pointer can be \c NULL if `aad_len == 0`. + * \param aad_len The length (in bytes) of the AAD data to process. + * \param tag The buffer holding the authentication tag. + * This must be a readable buffer of length \c 16 Bytes. + * \param input The buffer containing the data to decrypt. + * This pointer can be \c NULL if `ilen == 0`. + * \param output The buffer to where the decrypted data is written. + * This pointer can be \c NULL if `ilen == 0`. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED + * if the data was not authentic. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_chachapoly_auth_decrypt(mbedtls_chachapoly_context *ctx, + size_t length, + const unsigned char nonce[12], + const unsigned char *aad, + size_t aad_len, + const unsigned char tag[16], + const unsigned char *input, + unsigned char *output); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief The ChaCha20-Poly1305 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_chachapoly_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CHACHAPOLY_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/check_config.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/check_config.h index e18e9a5..57ccea1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/check_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/check_config.h @@ -1,1218 +1,1218 @@ -/** - * \file check_config.h - * - * \brief Consistency checks for configuration options - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CHECK_CONFIG_H -#define MBEDTLS_CHECK_CONFIG_H - -/* *INDENT-OFF* */ -/* - * We assume CHAR_BIT is 8 in many places. In practice, this is true on our - * target platforms, so not an issue, but let's just be extra sure. - */ -#include -#if CHAR_BIT != 8 -#error "Mbed TLS requires a platform with 8-bit chars" -#endif - -#include - -#if defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER <= 1900) -#if !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_C is required on Windows" -#endif - -/* Fix the config here. Not convenient to put an #ifdef _WIN32 in mbedtls_config.h as - * it would confuse config.py. */ -#if !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && \ - !defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) -#define MBEDTLS_PLATFORM_SNPRINTF_ALT -#endif - -#if !defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) && \ - !defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) -#define MBEDTLS_PLATFORM_VSNPRINTF_ALT -#endif -#endif /* _MINGW32__ || (_MSC_VER && (_MSC_VER <= 1900)) */ - -#if defined(TARGET_LIKE_MBED) && defined(MBEDTLS_NET_C) -#error "The NET module is not available for mbed OS - please use the network functions provided by Mbed OS" -#endif - -#if defined(MBEDTLS_DEPRECATED_WARNING) && \ - !defined(__GNUC__) && !defined(__clang__) -#error "MBEDTLS_DEPRECATED_WARNING only works with GCC and Clang" -#endif - -#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_HAVE_TIME) -#error "MBEDTLS_HAVE_TIME_DATE without MBEDTLS_HAVE_TIME does not make sense" -#endif - -/* Check that each MBEDTLS_ECP_DP_xxx symbol has its PSA_WANT_ECC_xxx counterpart - * when PSA crypto is enabled. */ -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) || defined(MBEDTLS_PSA_CRYPTO_C) - -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#error "MBEDTLS_ECP_DP_BP256R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#error "MBEDTLS_ECP_DP_BP384R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#error "MBEDTLS_ECP_DP_BP512R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && !defined(PSA_WANT_ECC_MONTGOMERY_255) -#error "MBEDTLS_ECP_DP_CURVE25519_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) && !defined(PSA_WANT_ECC_MONTGOMERY_448) -#error "MBEDTLS_ECP_DP_CURVE448_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_192) -#error "MBEDTLS_ECP_DP_SECP192R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_224) -#error "MBEDTLS_ECP_DP_SECP224R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_256) -#error "MBEDTLS_ECP_DP_SECP256R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_384) -#error "MBEDTLS_ECP_DP_SECP384R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_521) -#error "MBEDTLS_ECP_DP_SECP521R1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_192) -#error "MBEDTLS_ECP_DP_SECP192K1_ENABLED defined, but not its PSA counterpart" -#endif - -/* SECP224K1 is buggy in PSA API so we skip this check */ -#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_224) -#error "MBEDTLS_ECP_DP_SECP224K1_ENABLED defined, but not its PSA counterpart" -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_256) -#error "MBEDTLS_ECP_DP_SECP256K1_ENABLED defined, but not its PSA counterpart" -#endif - -#endif /* MBEDTLS_PSA_CRYPTO_CONFIG || MBEDTLS_PSA_CRYPTO_C */ - -/* Limitations on ECC key types acceleration: if we have any of `PUBLIC_KEY`, - * `KEY_PAIR_BASIC`, `KEY_PAIR_IMPORT`, `KEY_PAIR_EXPORT` then we must have - * all 4 of them. - */ -#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ - defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ - !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#error "Unsupported partial support for ECC key type acceleration, see docs/driver-only-builds.md" -#endif /* not all of public, basic, import, export */ -#endif /* one of public, basic, import, export */ - -/* Limitations on ECC curves acceleration: partial curve acceleration is only - * supported with crypto excluding PK, X.509 or TLS. - * Note: no need to check X.509 as it depends on PK. */ -#if defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_256) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_384) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_512) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_192) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384) || \ - defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521) -#if defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) -#if defined(MBEDTLS_PK_C) || \ - defined(MBEDTLS_SSL_TLS_C) -#error "Unsupported partial support for ECC curves acceleration, see docs/driver-only-builds.md" -#endif /* modules beyond what's supported */ -#endif /* not all curves accelerated */ -#endif /* some curve accelerated */ - -#if defined(MBEDTLS_CTR_DRBG_C) && !defined(MBEDTLS_AES_C) -#error "MBEDTLS_CTR_DRBG_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_DHM_C) && !defined(MBEDTLS_BIGNUM_C) -#error "MBEDTLS_DHM_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_CMAC_C) && \ - ( !defined(MBEDTLS_CIPHER_C ) || ( !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_DES_C) ) ) -#error "MBEDTLS_CMAC_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_NIST_KW_C) && \ - ( !defined(MBEDTLS_AES_C) || !defined(MBEDTLS_CIPHER_C) ) -#error "MBEDTLS_NIST_KW_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECDH_C) && !defined(MBEDTLS_ECP_C) -#error "MBEDTLS_ECDH_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECDSA_C) && \ - ( !defined(MBEDTLS_ECP_C) || \ - !( defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) ) || \ - !defined(MBEDTLS_ASN1_PARSE_C) || \ - !defined(MBEDTLS_ASN1_WRITE_C) ) -#error "MBEDTLS_ECDSA_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECJPAKE_C) && \ - ( !defined(MBEDTLS_ECP_C) || \ - !( defined(MBEDTLS_MD_C) || defined(MBEDTLS_PSA_CRYPTO_C) ) ) -#error "MBEDTLS_ECJPAKE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_RESTARTABLE) && \ - ( defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) || \ - defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || \ - defined(MBEDTLS_ECDSA_SIGN_ALT) || \ - defined(MBEDTLS_ECDSA_VERIFY_ALT) || \ - defined(MBEDTLS_ECDSA_GENKEY_ALT) || \ - defined(MBEDTLS_ECP_INTERNAL_ALT) || \ - defined(MBEDTLS_ECP_ALT) ) -#error "MBEDTLS_ECP_RESTARTABLE defined, but it cannot coexist with an alternative ECP implementation" -#endif - -#if defined(MBEDTLS_ECP_RESTARTABLE) && \ - !defined(MBEDTLS_ECP_C) -#error "MBEDTLS_ECP_RESTARTABLE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) && !defined(MBEDTLS_HMAC_DRBG_C) -#error "MBEDTLS_ECDSA_DETERMINISTIC defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_C) && ( !defined(MBEDTLS_BIGNUM_C) || ( \ - !defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && \ - !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) ) -#error "MBEDTLS_ECP_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C) -#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PKCS12_C) && !defined(MBEDTLS_CIPHER_C) -#error "MBEDTLS_PKCS12_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PKCS5_C) && \ - !defined(MBEDTLS_CIPHER_C) -#error "MBEDTLS_PKCS5_C defined, but not all prerequisites" -#endif - -/* Helpers for hash dependencies, will be undefined at the end of the file */ -/* Do SHA-256, 384, 512 to cover Entropy and TLS. */ -#if defined(MBEDTLS_SHA256_C) || \ - (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_256)) -#define MBEDTLS_MD_HAVE_SHA256 -#endif -#if defined(MBEDTLS_SHA384_C) || \ - (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_384)) -#define MBEDTLS_MD_HAVE_SHA384 -#endif -#if defined(MBEDTLS_SHA512_C) || \ - (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_512)) -#define MBEDTLS_MD_HAVE_SHA512 -#endif - -#if defined(MBEDTLS_ENTROPY_C) && \ - !(defined(MBEDTLS_MD_HAVE_SHA512) || defined(MBEDTLS_MD_HAVE_SHA256)) -#error "MBEDTLS_ENTROPY_C defined, but not all prerequisites" -#endif -#if defined(MBEDTLS_ENTROPY_C) && \ - defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 64) -#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" -#endif -#if defined(MBEDTLS_ENTROPY_C) && \ - (defined(MBEDTLS_ENTROPY_FORCE_SHA256) || !defined(MBEDTLS_MD_HAVE_SHA512)) \ - && defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 32) -#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" -#endif -#if defined(MBEDTLS_ENTROPY_C) && \ - defined(MBEDTLS_ENTROPY_FORCE_SHA256) && !defined(MBEDTLS_MD_HAVE_SHA256) -#error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites" -#endif - -#if defined(__has_feature) -#if __has_feature(memory_sanitizer) -#define MBEDTLS_HAS_MEMSAN -#endif -#endif -#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) && !defined(MBEDTLS_HAS_MEMSAN) -#error "MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN requires building with MemorySanitizer" -#endif -#undef MBEDTLS_HAS_MEMSAN - -#if defined(MBEDTLS_CCM_C) && ( \ - !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) && !defined(MBEDTLS_ARIA_C) ) -#error "MBEDTLS_CCM_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_CCM_C) && !defined(MBEDTLS_CIPHER_C) -#error "MBEDTLS_CCM_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_GCM_C) && ( \ - !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) && !defined(MBEDTLS_ARIA_C) ) -#error "MBEDTLS_GCM_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_GCM_C) && !defined(MBEDTLS_CIPHER_C) -#error "MBEDTLS_GCM_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) && !defined(MBEDTLS_CHACHA20_C) -#error "MBEDTLS_CHACHAPOLY_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) && !defined(MBEDTLS_POLY1305_C) -#error "MBEDTLS_CHACHAPOLY_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_RANDOMIZE_JAC_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_ADD_MIXED_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_DOUBLE_JAC_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_NORMALIZE_JAC_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_RANDOMIZE_MXZ_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_NORMALIZE_MXZ_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ECP_NO_FALLBACK) && !defined(MBEDTLS_ECP_INTERNAL_ALT) -#error "MBEDTLS_ECP_NO_FALLBACK defined, but no alternative implementation enabled" -#endif - -#if defined(MBEDTLS_HKDF_C) && !defined(MBEDTLS_MD_C) -#error "MBEDTLS_HKDF_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_HMAC_DRBG_C) && !defined(MBEDTLS_MD_C) -#error "MBEDTLS_HMAC_DRBG_C defined, but not all prerequisites" -#endif - -/* Helper for JPAKE dependencies, will be undefined at the end of the file */ -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if defined(PSA_WANT_ALG_JPAKE) && defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define MBEDTLS_PK_HAVE_JPAKE -#endif -#else /* MBEDTLS_USE_PSA_CRYPTO */ -#if defined(MBEDTLS_ECJPAKE_C) -#define MBEDTLS_PK_HAVE_JPAKE -#endif -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/* Helper for curve SECP256R1 */ -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if defined(PSA_WANT_ECC_SECP_R1_256) -#define MBEDTLS_PK_HAVE_CURVE_SECP256R1 -#endif -#else /* MBEDTLS_USE_PSA_CRYPTO */ -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) -#define MBEDTLS_PK_HAVE_CURVE_SECP256R1 -#endif -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) && \ - ( !defined(MBEDTLS_CAN_ECDH) || \ - !defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) ) -#error "MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) && \ - ( !defined(MBEDTLS_CAN_ECDH) || !defined(MBEDTLS_RSA_C) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) ) -#error "MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) && !defined(MBEDTLS_DHM_C) -#error "MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) && \ - !defined(MBEDTLS_CAN_ECDH) -#error "MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) && \ - ( !defined(MBEDTLS_DHM_C) || !defined(MBEDTLS_RSA_C) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) -#error "MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) && \ - ( !defined(MBEDTLS_CAN_ECDH) || !defined(MBEDTLS_RSA_C) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) -#error "MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) && \ - ( !defined(MBEDTLS_CAN_ECDH) || \ - !defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || \ - !defined(MBEDTLS_X509_CRT_PARSE_C) ) -#error "MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) && \ - ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ - !defined(MBEDTLS_PKCS1_V15) ) -#error "MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) && \ - ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ - !defined(MBEDTLS_PKCS1_V15) ) -#error "MBEDTLS_KEY_EXCHANGE_RSA_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ - ( !defined(MBEDTLS_PK_HAVE_JPAKE) || \ - !defined(MBEDTLS_PK_HAVE_CURVE_SECP256R1) ) -#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites" -#endif - -/* Use of EC J-PAKE in TLS requires SHA-256. */ -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ - !defined(MBEDTLS_MD_HAVE_SHA256) -#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) && \ - !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) && \ - ( !defined(MBEDTLS_SHA256_C) && \ - !defined(MBEDTLS_SHA512_C) && \ - !defined(MBEDTLS_SHA1_C) ) -#error "!MBEDTLS_SSL_KEEP_PEER_CERTIFICATE requires MBEDTLS_SHA512_C, MBEDTLS_SHA256_C or MBEDTLS_SHA1_C" -#endif - -#if defined(MBEDTLS_MD_C) && !( \ - defined(MBEDTLS_MD5_C) || \ - defined(MBEDTLS_RIPEMD160_C) || \ - defined(MBEDTLS_SHA1_C) || \ - defined(MBEDTLS_SHA224_C) || \ - defined(MBEDTLS_SHA256_C) || \ - defined(MBEDTLS_SHA384_C) || \ - defined(MBEDTLS_SHA512_C) || \ - (defined(MBEDTLS_PSA_CRYPTO_C) && \ - (defined(PSA_WANT_ALG_MD5) || \ - defined(PSA_WANT_ALG_RIPEMD160) || \ - defined(PSA_WANT_ALG_SHA_1) || \ - defined(PSA_WANT_ALG_SHA_224) || \ - defined(PSA_WANT_ALG_SHA_256) || \ - defined(PSA_WANT_ALG_SHA_384) || \ - defined(PSA_WANT_ALG_SHA_512)))) -#error "MBEDTLS_MD_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_LMS_C) && \ - ! ( defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_256) ) -#error "MBEDTLS_LMS_C requires MBEDTLS_PSA_CRYPTO_C and PSA_WANT_ALG_SHA_256" -#endif - -#if defined(MBEDTLS_LMS_PRIVATE) && \ - ( !defined(MBEDTLS_LMS_C) ) -#error "MBEDTLS_LMS_PRIVATE requires MBEDTLS_LMS_C" -#endif - -#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) && \ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) -#error "MBEDTLS_MEMORY_BUFFER_ALLOC_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_MEMORY_BACKTRACE) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) -#error "MBEDTLS_MEMORY_BACKTRACE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_MEMORY_DEBUG) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) -#error "MBEDTLS_MEMORY_DEBUG defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PEM_PARSE_C) && !defined(MBEDTLS_BASE64_C) -#error "MBEDTLS_PEM_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PEM_WRITE_C) && !defined(MBEDTLS_BASE64_C) -#error "MBEDTLS_PEM_WRITE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PK_C) && \ - !defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_PK_HAVE_ECC_KEYS) -#error "MBEDTLS_PK_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_PK_C) -#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PK_WRITE_C) && !defined(MBEDTLS_PK_C) -#error "MBEDTLS_PK_WRITE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_EXIT_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_EXIT) ||\ - defined(MBEDTLS_PLATFORM_EXIT_ALT) ) -#error "MBEDTLS_PLATFORM_EXIT_MACRO and MBEDTLS_PLATFORM_STD_EXIT/MBEDTLS_PLATFORM_EXIT_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_SETBUF_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_SETBUF_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_SETBUF) ||\ - defined(MBEDTLS_PLATFORM_SETBUF_ALT) ) -#error "MBEDTLS_PLATFORM_SETBUF_MACRO and MBEDTLS_PLATFORM_STD_SETBUF/MBEDTLS_PLATFORM_SETBUF_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_TIME_ALT) &&\ - ( !defined(MBEDTLS_PLATFORM_C) ||\ - !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_TIME_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ - ( !defined(MBEDTLS_PLATFORM_C) ||\ - !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_TIME_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO) &&\ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_MS_TIME_ALT) && \ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_MS_TIME_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ - ( !defined(MBEDTLS_PLATFORM_C) ||\ - !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ - defined(MBEDTLS_PLATFORM_TIME_ALT) ) -#error "MBEDTLS_PLATFORM_TIME_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ - defined(MBEDTLS_PLATFORM_TIME_ALT) ) -#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_FPRINTF_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_FPRINTF_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_FPRINTF) ||\ - defined(MBEDTLS_PLATFORM_FPRINTF_ALT) ) -#error "MBEDTLS_PLATFORM_FPRINTF_MACRO and MBEDTLS_PLATFORM_STD_FPRINTF/MBEDTLS_PLATFORM_FPRINTF_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) -#error "MBEDTLS_PLATFORM_FREE_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ - defined(MBEDTLS_PLATFORM_STD_FREE) -#error "MBEDTLS_PLATFORM_FREE_MACRO and MBEDTLS_PLATFORM_STD_FREE cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO) -#error "MBEDTLS_PLATFORM_CALLOC_MACRO must be defined if MBEDTLS_PLATFORM_FREE_MACRO is" -#endif - -#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) -#error "MBEDTLS_PLATFORM_CALLOC_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ - defined(MBEDTLS_PLATFORM_STD_CALLOC) -#error "MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_STD_CALLOC cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && !defined(MBEDTLS_PLATFORM_FREE_MACRO) -#error "MBEDTLS_PLATFORM_FREE_MACRO must be defined if MBEDTLS_PLATFORM_CALLOC_MACRO is" -#endif - -#if defined(MBEDTLS_PLATFORM_MEMORY) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_MEMORY defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_PRINTF_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_PRINTF_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_PRINTF) ||\ - defined(MBEDTLS_PLATFORM_PRINTF_ALT) ) -#error "MBEDTLS_PLATFORM_PRINTF_MACRO and MBEDTLS_PLATFORM_STD_PRINTF/MBEDTLS_PLATFORM_PRINTF_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_SNPRINTF_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_SNPRINTF) ||\ - defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) ) -#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_SNPRINTF/MBEDTLS_PLATFORM_SNPRINTF_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_VSNPRINTF_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) -#error "MBEDTLS_PLATFORM_VSNPRINTF_MACRO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) ||\ - defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) ) -#error "MBEDTLS_PLATFORM_VSNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_VSNPRINTF/MBEDTLS_PLATFORM_VSNPRINTF_ALT cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) &&\ - !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) -#error "MBEDTLS_PLATFORM_STD_MEM_HDR defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY) -#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_FREE) && !defined(MBEDTLS_PLATFORM_MEMORY) -#error "MBEDTLS_PLATFORM_STD_FREE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_EXIT) &&\ - !defined(MBEDTLS_PLATFORM_EXIT_ALT) -#error "MBEDTLS_PLATFORM_STD_EXIT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_TIME) &&\ - ( !defined(MBEDTLS_PLATFORM_TIME_ALT) ||\ - !defined(MBEDTLS_HAVE_TIME) ) -#error "MBEDTLS_PLATFORM_STD_TIME defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_FPRINTF) &&\ - !defined(MBEDTLS_PLATFORM_FPRINTF_ALT) -#error "MBEDTLS_PLATFORM_STD_FPRINTF defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_PRINTF) &&\ - !defined(MBEDTLS_PLATFORM_PRINTF_ALT) -#error "MBEDTLS_PLATFORM_STD_PRINTF defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_SNPRINTF) &&\ - !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) -#error "MBEDTLS_PLATFORM_STD_SNPRINTF defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_ENTROPY_NV_SEED) &&\ - ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_ENTROPY_C) ) -#error "MBEDTLS_ENTROPY_NV_SEED defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) &&\ - !defined(MBEDTLS_ENTROPY_NV_SEED) -#error "MBEDTLS_PLATFORM_NV_SEED_ALT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) &&\ - !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) -#error "MBEDTLS_PLATFORM_STD_NV_SEED_READ defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) &&\ - !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) -#error "MBEDTLS_PLATFORM_STD_NV_SEED_WRITE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) ||\ - defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) -#error "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_READ cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) &&\ - ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) ||\ - defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) -#error "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_WRITE cannot be defined simultaneously" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_C) && \ - !( ( ( defined(MBEDTLS_CTR_DRBG_C) || defined(MBEDTLS_HMAC_DRBG_C) ) && \ - defined(MBEDTLS_ENTROPY_C) ) || \ - defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) ) -#error "MBEDTLS_PSA_CRYPTO_C defined, but not all prerequisites (missing RNG)" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_C) && !defined(MBEDTLS_CIPHER_C ) -#error "MBEDTLS_PSA_CRYPTO_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_SPM) && !defined(MBEDTLS_PSA_CRYPTO_C) -#error "MBEDTLS_PSA_CRYPTO_SPM defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) && \ - ! ( defined(MBEDTLS_PSA_CRYPTO_C) && \ - defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) ) -#error "MBEDTLS_PSA_CRYPTO_SE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -#if defined(MBEDTLS_DEPRECATED_REMOVED) -#error "MBEDTLS_PSA_CRYPTO_SE_C is deprecated and will be removed in a future version of Mbed TLS" -#elif defined(MBEDTLS_DEPRECATED_WARNING) -#warning "MBEDTLS_PSA_CRYPTO_SE_C is deprecated and will be removed in a future version of Mbed TLS" -#endif -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && \ - ! defined(MBEDTLS_PSA_CRYPTO_C) -#error "MBEDTLS_PSA_CRYPTO_STORAGE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ - !( defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && \ - defined(MBEDTLS_ENTROPY_NV_SEED) ) -#error "MBEDTLS_PSA_INJECT_ENTROPY defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ - !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) -#error "MBEDTLS_PSA_INJECT_ENTROPY is not compatible with actual entropy sources" -#endif - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ - defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -#error "MBEDTLS_PSA_INJECT_ENTROPY is not compatible with MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG" -#endif - -#if defined(MBEDTLS_PSA_ITS_FILE_C) && \ - !defined(MBEDTLS_FS_IO) -#error "MBEDTLS_PSA_ITS_FILE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ - !defined(MBEDTLS_OID_C) ) -#error "MBEDTLS_RSA_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_PKCS1_V21) && \ - !defined(MBEDTLS_PKCS1_V15) ) -#error "MBEDTLS_RSA_C defined, but none of the PKCS1 versions enabled" -#endif - -#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) && \ - ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_PKCS1_V21) ) -#error "MBEDTLS_X509_RSASSA_PSS_SUPPORT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) && \ - defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) -#error "Must only define one of MBEDTLS_SHA512_USE_A64_CRYPTO_*" -#endif - -#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) -#if !defined(MBEDTLS_SHA512_C) -#error "MBEDTLS_SHA512_USE_A64_CRYPTO_* defined without MBEDTLS_SHA512_C" -#endif -#if defined(MBEDTLS_SHA512_ALT) || defined(MBEDTLS_SHA512_PROCESS_ALT) -#error "MBEDTLS_SHA512_*ALT can't be used with MBEDTLS_SHA512_USE_A64_CRYPTO_*" -#endif - -#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ - -#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) && !defined(__aarch64__) -#error "MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY defined on non-Aarch64 system" -#endif - -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) && \ - defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) -#error "Must only define one of MBEDTLS_SHA256_USE_A64_CRYPTO_*" -#endif - -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ - defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) -#if !defined(MBEDTLS_SHA256_C) -#error "MBEDTLS_SHA256_USE_A64_CRYPTO_* defined without MBEDTLS_SHA256_C" -#endif -#if defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA256_PROCESS_ALT) -#error "MBEDTLS_SHA256_*ALT can't be used with MBEDTLS_SHA256_USE_A64_CRYPTO_*" -#endif - -#endif - -#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) && \ - !defined(__aarch64__) && !defined(_M_ARM64) -#error "MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY defined on non-Aarch64 system" -#endif - -/* TLS 1.3 requires separate HKDF parts from PSA, - * and at least one ciphersuite, so at least SHA-256 or SHA-384 - * from PSA to use with HKDF. - * - * Note: for dependencies common with TLS 1.2 (running handshake hash), - * see MBEDTLS_SSL_TLS_C. */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ - !(defined(MBEDTLS_PSA_CRYPTO_C) && \ - defined(PSA_WANT_ALG_HKDF_EXTRACT) && \ - defined(PSA_WANT_ALG_HKDF_EXPAND) && \ - (defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_384))) -#error "MBEDTLS_SSL_PROTO_TLS1_3 defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -#if !( (defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH)) && \ - defined(MBEDTLS_X509_CRT_PARSE_C) && \ - ( defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || defined(MBEDTLS_PKCS1_V21) ) ) -#error "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED defined, but not all prerequisites" -#endif -#endif - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) -#if !( defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) ) -#error "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED defined, but not all prerequisites" -#endif -#endif - -/* - * The current implementation of TLS 1.3 requires MBEDTLS_SSL_KEEP_PEER_CERTIFICATE. - */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) -#error "MBEDTLS_SSL_PROTO_TLS1_3 defined without MBEDTLS_SSL_KEEP_PEER_CERTIFICATE" -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ - !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) ) -#error "One or more versions of the TLS protocol are enabled " \ - "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx" -#endif - -#if defined(MBEDTLS_SSL_EARLY_DATA) && \ - ( !defined(MBEDTLS_SSL_SESSION_TICKETS) || \ - ( !defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED) && \ - !defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) ) ) -#error "MBEDTLS_SSL_EARLY_DATA defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_EARLY_DATA) && defined(MBEDTLS_SSL_SRV_C) && \ - defined(MBEDTLS_SSL_MAX_EARLY_DATA_SIZE) && \ - ((MBEDTLS_SSL_MAX_EARLY_DATA_SIZE < 0) || \ - (MBEDTLS_SSL_MAX_EARLY_DATA_SIZE > UINT32_MAX)) -#error "MBEDTLS_SSL_MAX_EARLY_DATA_SIZE must be in the range(0..UINT32_MAX)" -#endif - -#if defined(MBEDTLS_SSL_PROTO_DTLS) && \ - !defined(MBEDTLS_SSL_PROTO_TLS1_2) -#error "MBEDTLS_SSL_PROTO_DTLS defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_CLI_C) && !defined(MBEDTLS_SSL_TLS_C) -#error "MBEDTLS_SSL_CLI_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) && !defined(MBEDTLS_X509_CRT_PARSE_C) -#error "MBEDTLS_SSL_ASYNC_PRIVATE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TLS_C) && !defined(MBEDTLS_CIPHER_C) -#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" -#endif - -/* TLS 1.2 and 1.3 require SHA-256 or SHA-384 (running handshake hash) */ -#if defined(MBEDTLS_SSL_TLS_C) -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if !(defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_384)) -#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" -#endif -#else /* MBEDTLS_USE_PSA_CRYPTO */ -#if !defined(MBEDTLS_MD_C) || \ - !(defined(MBEDTLS_MD_HAVE_SHA256) || defined(MBEDTLS_MD_HAVE_SHA384)) -#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" -#endif -#endif /* MBEDTLS_USE_PSA_CRYPTO */ -#endif /* MBEDTLS_SSL_TLS_C */ - -#if defined(MBEDTLS_SSL_SRV_C) && !defined(MBEDTLS_SSL_TLS_C) -#error "MBEDTLS_SSL_SRV_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TLS_C) && \ - !( defined(MBEDTLS_SSL_PROTO_TLS1_2) || defined(MBEDTLS_SSL_PROTO_TLS1_3) ) -#error "MBEDTLS_SSL_TLS_C defined, but no protocols are active" -#endif - -#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && !defined(MBEDTLS_SSL_PROTO_DTLS) -#error "MBEDTLS_SSL_DTLS_HELLO_VERIFY defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && \ - !defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) -#error "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) && \ - ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) -#error "MBEDTLS_SSL_DTLS_ANTI_REPLAY defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ - ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) -#error "MBEDTLS_SSL_DTLS_CONNECTION_ID defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ - defined(MBEDTLS_SSL_CID_IN_LEN_MAX) && \ - MBEDTLS_SSL_CID_IN_LEN_MAX > 255 -#error "MBEDTLS_SSL_CID_IN_LEN_MAX too large (max 255)" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ - defined(MBEDTLS_SSL_CID_OUT_LEN_MAX) && \ - MBEDTLS_SSL_CID_OUT_LEN_MAX > 255 -#error "MBEDTLS_SSL_CID_OUT_LEN_MAX too large (max 255)" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) && \ - !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -#error "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) && MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT != 0 -#if defined(MBEDTLS_DEPRECATED_REMOVED) -#error "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT is deprecated and will be removed in a future version of Mbed TLS" -#elif defined(MBEDTLS_DEPRECATED_WARNING) -#warning "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT is deprecated and will be removed in a future version of Mbed TLS" -#endif -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT && MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT != 0 */ - -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) && \ - !defined(MBEDTLS_SSL_PROTO_TLS1_2) -#error "MBEDTLS_SSL_ENCRYPT_THEN_MAC defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) && \ - !defined(MBEDTLS_SSL_PROTO_TLS1_2) -#error "MBEDTLS_SSL_EXTENDED_MASTER_SECRET defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_RENEGOTIATION) && \ - !defined(MBEDTLS_SSL_PROTO_TLS1_2) -#error "MBEDTLS_SSL_RENEGOTIATION defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TICKET_C) && ( !defined(MBEDTLS_CIPHER_C) && \ - !defined(MBEDTLS_USE_PSA_CRYPTO) ) -#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TICKET_C) && \ - !( defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) ) -#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH) && \ - MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH >= 256 -#error "MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH must be less than 256" -#endif - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \ - !defined(MBEDTLS_X509_CRT_PARSE_C) -#error "MBEDTLS_SSL_SERVER_NAME_INDICATION defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_THREADING_PTHREAD) -#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) -#error "MBEDTLS_THREADING_PTHREAD defined, but not all prerequisites" -#endif -#define MBEDTLS_THREADING_IMPL -#endif - -#if defined(MBEDTLS_THREADING_ALT) -#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) -#error "MBEDTLS_THREADING_ALT defined, but not all prerequisites" -#endif -#define MBEDTLS_THREADING_IMPL -#endif - -#if defined(MBEDTLS_THREADING_C) && !defined(MBEDTLS_THREADING_IMPL) -#error "MBEDTLS_THREADING_C defined, single threading implementation required" -#endif -#undef MBEDTLS_THREADING_IMPL - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_PSA_CRYPTO_C) -#error "MBEDTLS_USE_PSA_CRYPTO defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_VERSION_FEATURES) && !defined(MBEDTLS_VERSION_C) -#error "MBEDTLS_VERSION_FEATURES defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_USE_C) && \ - (!defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_PARSE_C) || \ - !defined(MBEDTLS_PK_PARSE_C) || \ - ( !defined(MBEDTLS_MD_C) && !defined(MBEDTLS_USE_PSA_CRYPTO) ) ) -#error "MBEDTLS_X509_USE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CREATE_C) && \ - (!defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_WRITE_C) || \ - !defined(MBEDTLS_PK_PARSE_C) || \ - ( !defined(MBEDTLS_MD_C) && !defined(MBEDTLS_USE_PSA_CRYPTO) ) ) -#error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) -#error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CRL_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) -#error "MBEDTLS_X509_CRL_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CSR_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) -#error "MBEDTLS_X509_CSR_PARSE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CRT_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) -#error "MBEDTLS_X509_CRT_WRITE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_CSR_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) -#error "MBEDTLS_X509_CSR_WRITE_C defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) && \ - ( !defined(MBEDTLS_X509_CRT_PARSE_C) ) -#error "MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64) -#error "MBEDTLS_HAVE_INT32 and MBEDTLS_HAVE_INT64 cannot be defined simultaneously" -#endif /* MBEDTLS_HAVE_INT32 && MBEDTLS_HAVE_INT64 */ - -#if ( defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64) ) && \ - defined(MBEDTLS_HAVE_ASM) -#error "MBEDTLS_HAVE_INT32/MBEDTLS_HAVE_INT64 and MBEDTLS_HAVE_ASM cannot be defined simultaneously" -#endif /* (MBEDTLS_HAVE_INT32 || MBEDTLS_HAVE_INT64) && MBEDTLS_HAVE_ASM */ - -#if defined(MBEDTLS_SSL_DTLS_SRTP) && ( !defined(MBEDTLS_SSL_PROTO_DTLS) ) -#error "MBEDTLS_SSL_DTLS_SRTP defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) && ( !defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) ) -#error "MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_RECORD_SIZE_LIMIT) && ( !defined(MBEDTLS_SSL_PROTO_TLS1_3) ) -#error "MBEDTLS_SSL_RECORD_SIZE_LIMIT defined, but not all prerequisites" -#endif - -#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) && !( defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) ) -#error "MBEDTLS_SSL_CONTEXT_SERIALIZATION defined, but not all prerequisites" -#endif - -/* Reject attempts to enable options that have been removed and that could - * cause a build to succeed but with features removed. */ - -#if defined(MBEDTLS_HAVEGE_C) //no-check-names -#error "MBEDTLS_HAVEGE_C was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/2599" -#endif - -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) //no-check-names -#error "MBEDTLS_SSL_HW_RECORD_ACCEL was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" -#endif - -#if defined(MBEDTLS_SSL_PROTO_SSL3) //no-check-names -#error "MBEDTLS_SSL_PROTO_SSL3 (SSL v3.0 support) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" -#endif - -#if defined(MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO) //no-check-names -#error "MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO (SSL v2 ClientHello support) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" -#endif - -#if defined(MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT) //no-check-names -#error "MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT (compatibility with the buggy implementation of truncated HMAC in Mbed TLS up to 2.7) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" -#endif - -#if defined(MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES) //no-check-names -#error "MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES was removed in Mbed TLS 3.0. See the ChangeLog entry if you really need SHA-1-signed certificates." -#endif - -#if defined(MBEDTLS_ZLIB_SUPPORT) //no-check-names -#error "MBEDTLS_ZLIB_SUPPORT was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" -#endif - -#if defined(MBEDTLS_CHECK_PARAMS) //no-check-names -#error "MBEDTLS_CHECK_PARAMS was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4313" -#endif - -#if defined(MBEDTLS_SSL_CID_PADDING_GRANULARITY) //no-check-names -#error "MBEDTLS_SSL_CID_PADDING_GRANULARITY was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4335" -#endif - -#if defined(MBEDTLS_SSL_TLS1_3_PADDING_GRANULARITY) //no-check-names -#error "MBEDTLS_SSL_TLS1_3_PADDING_GRANULARITY was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4335" -#endif - -#if defined(MBEDTLS_SSL_TRUNCATED_HMAC) //no-check-names -#error "MBEDTLS_SSL_TRUNCATED_HMAC was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4341" -#endif - -#if defined(MBEDTLS_PKCS7_C) && ( ( !defined(MBEDTLS_ASN1_PARSE_C) ) || \ - ( !defined(MBEDTLS_OID_C) ) || ( !defined(MBEDTLS_PK_PARSE_C) ) || \ - ( !defined(MBEDTLS_X509_CRT_PARSE_C) ) || \ - ( !defined(MBEDTLS_X509_CRL_PARSE_C) ) || \ - ( !defined(MBEDTLS_MD_C) ) ) -#error "MBEDTLS_PKCS7_C is defined, but not all prerequisites" -#endif - -/* Undefine helper symbols */ -#undef MBEDTLS_PK_HAVE_JPAKE -#undef MBEDTLS_MD_HAVE_SHA256 -#undef MBEDTLS_MD_HAVE_SHA384 -#undef MBEDTLS_MD_HAVE_SHA512 -#undef MBEDTLS_PK_HAVE_CURVE_SECP256R1 - -/* - * Avoid warning from -pedantic. This is a convenient place for this - * workaround since this is included by every single file before the - * #if defined(MBEDTLS_xxx_C) that results in empty translation units. - */ -typedef int mbedtls_iso_c_forbids_empty_translation_units; - -/* *INDENT-ON* */ -#endif /* MBEDTLS_CHECK_CONFIG_H */ +/** + * \file check_config.h + * + * \brief Consistency checks for configuration options + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CHECK_CONFIG_H +#define MBEDTLS_CHECK_CONFIG_H + +/* *INDENT-OFF* */ +/* + * We assume CHAR_BIT is 8 in many places. In practice, this is true on our + * target platforms, so not an issue, but let's just be extra sure. + */ +#include +#if CHAR_BIT != 8 +#error "Mbed TLS requires a platform with 8-bit chars" +#endif + +#include + +#if defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER <= 1900) +#if !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_C is required on Windows" +#endif + +/* Fix the config here. Not convenient to put an #ifdef _WIN32 in mbedtls_config.h as + * it would confuse config.py. */ +#if !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && \ + !defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) +#define MBEDTLS_PLATFORM_SNPRINTF_ALT +#endif + +#if !defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) && \ + !defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) +#define MBEDTLS_PLATFORM_VSNPRINTF_ALT +#endif +#endif /* _MINGW32__ || (_MSC_VER && (_MSC_VER <= 1900)) */ + +#if defined(TARGET_LIKE_MBED) && defined(MBEDTLS_NET_C) +#error "The NET module is not available for mbed OS - please use the network functions provided by Mbed OS" +#endif + +#if defined(MBEDTLS_DEPRECATED_WARNING) && \ + !defined(__GNUC__) && !defined(__clang__) +#error "MBEDTLS_DEPRECATED_WARNING only works with GCC and Clang" +#endif + +#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_HAVE_TIME) +#error "MBEDTLS_HAVE_TIME_DATE without MBEDTLS_HAVE_TIME does not make sense" +#endif + +/* Check that each MBEDTLS_ECP_DP_xxx symbol has its PSA_WANT_ECC_xxx counterpart + * when PSA crypto is enabled. */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) || defined(MBEDTLS_PSA_CRYPTO_C) + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) +#error "MBEDTLS_ECP_DP_BP256R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) +#error "MBEDTLS_ECP_DP_BP384R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) && !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) +#error "MBEDTLS_ECP_DP_BP512R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && !defined(PSA_WANT_ECC_MONTGOMERY_255) +#error "MBEDTLS_ECP_DP_CURVE25519_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) && !defined(PSA_WANT_ECC_MONTGOMERY_448) +#error "MBEDTLS_ECP_DP_CURVE448_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_192) +#error "MBEDTLS_ECP_DP_SECP192R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_224) +#error "MBEDTLS_ECP_DP_SECP224R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_256) +#error "MBEDTLS_ECP_DP_SECP256R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_384) +#error "MBEDTLS_ECP_DP_SECP384R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) && !defined(PSA_WANT_ECC_SECP_R1_521) +#error "MBEDTLS_ECP_DP_SECP521R1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_192) +#error "MBEDTLS_ECP_DP_SECP192K1_ENABLED defined, but not its PSA counterpart" +#endif + +/* SECP224K1 is buggy in PSA API so we skip this check */ +#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_224) +#error "MBEDTLS_ECP_DP_SECP224K1_ENABLED defined, but not its PSA counterpart" +#endif + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) && !defined(PSA_WANT_ECC_SECP_K1_256) +#error "MBEDTLS_ECP_DP_SECP256K1_ENABLED defined, but not its PSA counterpart" +#endif + +#endif /* MBEDTLS_PSA_CRYPTO_CONFIG || MBEDTLS_PSA_CRYPTO_C */ + +/* Limitations on ECC key types acceleration: if we have any of `PUBLIC_KEY`, + * `KEY_PAIR_BASIC`, `KEY_PAIR_IMPORT`, `KEY_PAIR_EXPORT` then we must have + * all 4 of them. + */ +#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ + !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) +#error "Unsupported partial support for ECC key type acceleration, see docs/driver-only-builds.md" +#endif /* not all of public, basic, import, export */ +#endif /* one of public, basic, import, export */ + +/* Limitations on ECC curves acceleration: partial curve acceleration is only + * supported with crypto excluding PK, X.509 or TLS. + * Note: no need to check X.509 as it depends on PK. */ +#if defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_256) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_384) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_512) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_192) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384) || \ + defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521) +#if defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) +#if defined(MBEDTLS_PK_C) || \ + defined(MBEDTLS_SSL_TLS_C) +#error "Unsupported partial support for ECC curves acceleration, see docs/driver-only-builds.md" +#endif /* modules beyond what's supported */ +#endif /* not all curves accelerated */ +#endif /* some curve accelerated */ + +#if defined(MBEDTLS_CTR_DRBG_C) && !defined(MBEDTLS_AES_C) +#error "MBEDTLS_CTR_DRBG_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_DHM_C) && !defined(MBEDTLS_BIGNUM_C) +#error "MBEDTLS_DHM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CMAC_C) && \ + ( !defined(MBEDTLS_CIPHER_C ) || ( !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_DES_C) ) ) +#error "MBEDTLS_CMAC_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_NIST_KW_C) && \ + ( !defined(MBEDTLS_AES_C) || !defined(MBEDTLS_CIPHER_C) ) +#error "MBEDTLS_NIST_KW_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECDH_C) && !defined(MBEDTLS_ECP_C) +#error "MBEDTLS_ECDH_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECDSA_C) && \ + ( !defined(MBEDTLS_ECP_C) || \ + !( defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) ) || \ + !defined(MBEDTLS_ASN1_PARSE_C) || \ + !defined(MBEDTLS_ASN1_WRITE_C) ) +#error "MBEDTLS_ECDSA_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECJPAKE_C) && \ + ( !defined(MBEDTLS_ECP_C) || \ + !( defined(MBEDTLS_MD_C) || defined(MBEDTLS_PSA_CRYPTO_C) ) ) +#error "MBEDTLS_ECJPAKE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) && \ + ( defined(MBEDTLS_ECDH_COMPUTE_SHARED_ALT) || \ + defined(MBEDTLS_ECDH_GEN_PUBLIC_ALT) || \ + defined(MBEDTLS_ECDSA_SIGN_ALT) || \ + defined(MBEDTLS_ECDSA_VERIFY_ALT) || \ + defined(MBEDTLS_ECDSA_GENKEY_ALT) || \ + defined(MBEDTLS_ECP_INTERNAL_ALT) || \ + defined(MBEDTLS_ECP_ALT) ) +#error "MBEDTLS_ECP_RESTARTABLE defined, but it cannot coexist with an alternative ECP implementation" +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) && \ + !defined(MBEDTLS_ECP_C) +#error "MBEDTLS_ECP_RESTARTABLE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) && !defined(MBEDTLS_HMAC_DRBG_C) +#error "MBEDTLS_ECDSA_DETERMINISTIC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_C) && ( !defined(MBEDTLS_BIGNUM_C) || ( \ + !defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && \ + !defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) ) ) +#error "MBEDTLS_ECP_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_ASN1_PARSE_C) +#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PKCS12_C) && !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_PKCS12_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PKCS5_C) && \ + !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_PKCS5_C defined, but not all prerequisites" +#endif + +/* Helpers for hash dependencies, will be undefined at the end of the file */ +/* Do SHA-256, 384, 512 to cover Entropy and TLS. */ +#if defined(MBEDTLS_SHA256_C) || \ + (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_256)) +#define MBEDTLS_MD_HAVE_SHA256 +#endif +#if defined(MBEDTLS_SHA384_C) || \ + (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_384)) +#define MBEDTLS_MD_HAVE_SHA384 +#endif +#if defined(MBEDTLS_SHA512_C) || \ + (defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_512)) +#define MBEDTLS_MD_HAVE_SHA512 +#endif + +#if defined(MBEDTLS_ENTROPY_C) && \ + !(defined(MBEDTLS_MD_HAVE_SHA512) || defined(MBEDTLS_MD_HAVE_SHA256)) +#error "MBEDTLS_ENTROPY_C defined, but not all prerequisites" +#endif +#if defined(MBEDTLS_ENTROPY_C) && \ + defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 64) +#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" +#endif +#if defined(MBEDTLS_ENTROPY_C) && \ + (defined(MBEDTLS_ENTROPY_FORCE_SHA256) || !defined(MBEDTLS_MD_HAVE_SHA512)) \ + && defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) && (MBEDTLS_CTR_DRBG_ENTROPY_LEN > 32) +#error "MBEDTLS_CTR_DRBG_ENTROPY_LEN value too high" +#endif +#if defined(MBEDTLS_ENTROPY_C) && \ + defined(MBEDTLS_ENTROPY_FORCE_SHA256) && !defined(MBEDTLS_MD_HAVE_SHA256) +#error "MBEDTLS_ENTROPY_FORCE_SHA256 defined, but not all prerequisites" +#endif + +#if defined(__has_feature) +#if __has_feature(memory_sanitizer) +#define MBEDTLS_HAS_MEMSAN +#endif +#endif +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) && !defined(MBEDTLS_HAS_MEMSAN) +#error "MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN requires building with MemorySanitizer" +#endif +#undef MBEDTLS_HAS_MEMSAN + +#if defined(MBEDTLS_CCM_C) && ( \ + !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) && !defined(MBEDTLS_ARIA_C) ) +#error "MBEDTLS_CCM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CCM_C) && !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_CCM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_GCM_C) && ( \ + !defined(MBEDTLS_AES_C) && !defined(MBEDTLS_CAMELLIA_C) && !defined(MBEDTLS_ARIA_C) ) +#error "MBEDTLS_GCM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_GCM_C) && !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_GCM_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) && !defined(MBEDTLS_CHACHA20_C) +#error "MBEDTLS_CHACHAPOLY_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) && !defined(MBEDTLS_POLY1305_C) +#error "MBEDTLS_CHACHAPOLY_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_RANDOMIZE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_ADD_MIXED_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_DOUBLE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_JAC_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_RANDOMIZE_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NORMALIZE_MXZ_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ECP_NO_FALLBACK) && !defined(MBEDTLS_ECP_INTERNAL_ALT) +#error "MBEDTLS_ECP_NO_FALLBACK defined, but no alternative implementation enabled" +#endif + +#if defined(MBEDTLS_HKDF_C) && !defined(MBEDTLS_MD_C) +#error "MBEDTLS_HKDF_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HMAC_DRBG_C) && !defined(MBEDTLS_MD_C) +#error "MBEDTLS_HMAC_DRBG_C defined, but not all prerequisites" +#endif + +/* Helper for JPAKE dependencies, will be undefined at the end of the file */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(PSA_WANT_ALG_JPAKE) && defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define MBEDTLS_PK_HAVE_JPAKE +#endif +#else /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(MBEDTLS_ECJPAKE_C) +#define MBEDTLS_PK_HAVE_JPAKE +#endif +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/* Helper for curve SECP256R1 */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(PSA_WANT_ECC_SECP_R1_256) +#define MBEDTLS_PK_HAVE_CURVE_SECP256R1 +#endif +#else /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#define MBEDTLS_PK_HAVE_CURVE_SECP256R1 +#endif +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) && \ + ( !defined(MBEDTLS_CAN_ECDH) || \ + !defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) && \ + ( !defined(MBEDTLS_CAN_ECDH) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) && !defined(MBEDTLS_DHM_C) +#error "MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) && \ + !defined(MBEDTLS_CAN_ECDH) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_DHM_C) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_CAN_ECDH) || !defined(MBEDTLS_RSA_C) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) || !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) && \ + ( !defined(MBEDTLS_CAN_ECDH) || \ + !defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || \ + !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_X509_CRT_PARSE_C) || \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_KEY_EXCHANGE_RSA_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ + ( !defined(MBEDTLS_PK_HAVE_JPAKE) || \ + !defined(MBEDTLS_PK_HAVE_CURVE_SECP256R1) ) +#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites" +#endif + +/* Use of EC J-PAKE in TLS requires SHA-256. */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ + !defined(MBEDTLS_MD_HAVE_SHA256) +#error "MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) && \ + !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) && \ + ( !defined(MBEDTLS_SHA256_C) && \ + !defined(MBEDTLS_SHA512_C) && \ + !defined(MBEDTLS_SHA1_C) ) +#error "!MBEDTLS_SSL_KEEP_PEER_CERTIFICATE requires MBEDTLS_SHA512_C, MBEDTLS_SHA256_C or MBEDTLS_SHA1_C" +#endif + +#if defined(MBEDTLS_MD_C) && !( \ + defined(MBEDTLS_MD5_C) || \ + defined(MBEDTLS_RIPEMD160_C) || \ + defined(MBEDTLS_SHA1_C) || \ + defined(MBEDTLS_SHA224_C) || \ + defined(MBEDTLS_SHA256_C) || \ + defined(MBEDTLS_SHA384_C) || \ + defined(MBEDTLS_SHA512_C) || \ + (defined(MBEDTLS_PSA_CRYPTO_C) && \ + (defined(PSA_WANT_ALG_MD5) || \ + defined(PSA_WANT_ALG_RIPEMD160) || \ + defined(PSA_WANT_ALG_SHA_1) || \ + defined(PSA_WANT_ALG_SHA_224) || \ + defined(PSA_WANT_ALG_SHA_256) || \ + defined(PSA_WANT_ALG_SHA_384) || \ + defined(PSA_WANT_ALG_SHA_512)))) +#error "MBEDTLS_MD_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_LMS_C) && \ + ! ( defined(MBEDTLS_PSA_CRYPTO_C) && defined(PSA_WANT_ALG_SHA_256) ) +#error "MBEDTLS_LMS_C requires MBEDTLS_PSA_CRYPTO_C and PSA_WANT_ALG_SHA_256" +#endif + +#if defined(MBEDTLS_LMS_PRIVATE) && \ + ( !defined(MBEDTLS_LMS_C) ) +#error "MBEDTLS_LMS_PRIVATE requires MBEDTLS_LMS_C" +#endif + +#if defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) && \ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_MEMORY_BUFFER_ALLOC_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_MEMORY_BACKTRACE) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) +#error "MBEDTLS_MEMORY_BACKTRACE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_MEMORY_DEBUG) && !defined(MBEDTLS_MEMORY_BUFFER_ALLOC_C) +#error "MBEDTLS_MEMORY_DEBUG defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) && !defined(MBEDTLS_BASE64_C) +#error "MBEDTLS_PEM_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PEM_WRITE_C) && !defined(MBEDTLS_BASE64_C) +#error "MBEDTLS_PEM_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_C) && \ + !defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_PK_HAVE_ECC_KEYS) +#error "MBEDTLS_PK_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_PARSE_C) && !defined(MBEDTLS_PK_C) +#error "MBEDTLS_PK_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PK_WRITE_C) && !defined(MBEDTLS_PK_C) +#error "MBEDTLS_PK_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_EXIT_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_EXIT) ||\ + defined(MBEDTLS_PLATFORM_EXIT_ALT) ) +#error "MBEDTLS_PLATFORM_EXIT_MACRO and MBEDTLS_PLATFORM_STD_EXIT/MBEDTLS_PLATFORM_EXIT_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SETBUF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SETBUF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_SETBUF) ||\ + defined(MBEDTLS_PLATFORM_SETBUF_ALT) ) +#error "MBEDTLS_PLATFORM_SETBUF_MACRO and MBEDTLS_PLATFORM_STD_SETBUF/MBEDTLS_PLATFORM_SETBUF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_ALT) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_MS_TIME_ALT) && \ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_MS_TIME_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ + defined(MBEDTLS_PLATFORM_TIME_ALT) ) +#error "MBEDTLS_PLATFORM_TIME_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_TIME) ||\ + defined(MBEDTLS_PLATFORM_TIME_ALT) ) +#error "MBEDTLS_PLATFORM_TIME_TYPE_MACRO and MBEDTLS_PLATFORM_STD_TIME/MBEDTLS_PLATFORM_TIME_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_FPRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_FPRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_FPRINTF) ||\ + defined(MBEDTLS_PLATFORM_FPRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_FPRINTF_MACRO and MBEDTLS_PLATFORM_STD_FPRINTF/MBEDTLS_PLATFORM_FPRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_PLATFORM_FREE_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) &&\ + defined(MBEDTLS_PLATFORM_STD_FREE) +#error "MBEDTLS_PLATFORM_FREE_MACRO and MBEDTLS_PLATFORM_STD_FREE cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && !defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO must be defined if MBEDTLS_PLATFORM_FREE_MACRO is" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_PLATFORM_MEMORY) ) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) &&\ + defined(MBEDTLS_PLATFORM_STD_CALLOC) +#error "MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_STD_CALLOC cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && !defined(MBEDTLS_PLATFORM_FREE_MACRO) +#error "MBEDTLS_PLATFORM_FREE_MACRO must be defined if MBEDTLS_PLATFORM_CALLOC_MACRO is" +#endif + +#if defined(MBEDTLS_PLATFORM_MEMORY) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_MEMORY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_PRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_PRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_PRINTF) ||\ + defined(MBEDTLS_PLATFORM_PRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_PRINTF_MACRO and MBEDTLS_PLATFORM_STD_PRINTF/MBEDTLS_PLATFORM_PRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SNPRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_SNPRINTF) ||\ + defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_SNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_SNPRINTF/MBEDTLS_PLATFORM_SNPRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_VSNPRINTF_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) && !defined(MBEDTLS_PLATFORM_C) +#error "MBEDTLS_PLATFORM_VSNPRINTF_MACRO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) ||\ + defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) ) +#error "MBEDTLS_PLATFORM_VSNPRINTF_MACRO and MBEDTLS_PLATFORM_STD_VSNPRINTF/MBEDTLS_PLATFORM_VSNPRINTF_ALT cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) &&\ + !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) +#error "MBEDTLS_PLATFORM_STD_MEM_HDR defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_CALLOC) && !defined(MBEDTLS_PLATFORM_MEMORY) +#error "MBEDTLS_PLATFORM_STD_CALLOC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_FREE) && !defined(MBEDTLS_PLATFORM_MEMORY) +#error "MBEDTLS_PLATFORM_STD_FREE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_EXIT) &&\ + !defined(MBEDTLS_PLATFORM_EXIT_ALT) +#error "MBEDTLS_PLATFORM_STD_EXIT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_TIME) &&\ + ( !defined(MBEDTLS_PLATFORM_TIME_ALT) ||\ + !defined(MBEDTLS_HAVE_TIME) ) +#error "MBEDTLS_PLATFORM_STD_TIME defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_FPRINTF) &&\ + !defined(MBEDTLS_PLATFORM_FPRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_FPRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_PRINTF) &&\ + !defined(MBEDTLS_PLATFORM_PRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_PRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_SNPRINTF) &&\ + !defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) +#error "MBEDTLS_PLATFORM_STD_SNPRINTF defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_ENTROPY_NV_SEED) &&\ + ( !defined(MBEDTLS_PLATFORM_C) || !defined(MBEDTLS_ENTROPY_C) ) +#error "MBEDTLS_ENTROPY_NV_SEED defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) &&\ + !defined(MBEDTLS_ENTROPY_NV_SEED) +#error "MBEDTLS_PLATFORM_NV_SEED_ALT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) &&\ + !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +#error "MBEDTLS_PLATFORM_STD_NV_SEED_READ defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) &&\ + !defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +#error "MBEDTLS_PLATFORM_STD_NV_SEED_WRITE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) ||\ + defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) +#error "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_READ cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) &&\ + ( defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) ||\ + defined(MBEDTLS_PLATFORM_NV_SEED_ALT) ) +#error "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and MBEDTLS_PLATFORM_STD_NV_SEED_WRITE cannot be defined simultaneously" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_C) && \ + !( ( ( defined(MBEDTLS_CTR_DRBG_C) || defined(MBEDTLS_HMAC_DRBG_C) ) && \ + defined(MBEDTLS_ENTROPY_C) ) || \ + defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) ) +#error "MBEDTLS_PSA_CRYPTO_C defined, but not all prerequisites (missing RNG)" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_C) && !defined(MBEDTLS_CIPHER_C ) +#error "MBEDTLS_PSA_CRYPTO_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_SPM) && !defined(MBEDTLS_PSA_CRYPTO_C) +#error "MBEDTLS_PSA_CRYPTO_SPM defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) && \ + ! ( defined(MBEDTLS_PSA_CRYPTO_C) && \ + defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) ) +#error "MBEDTLS_PSA_CRYPTO_SE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "MBEDTLS_PSA_CRYPTO_SE_C is deprecated and will be removed in a future version of Mbed TLS" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "MBEDTLS_PSA_CRYPTO_SE_C is deprecated and will be removed in a future version of Mbed TLS" +#endif +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && \ + ! defined(MBEDTLS_PSA_CRYPTO_C) +#error "MBEDTLS_PSA_CRYPTO_STORAGE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ + !( defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) && \ + defined(MBEDTLS_ENTROPY_NV_SEED) ) +#error "MBEDTLS_PSA_INJECT_ENTROPY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ + !defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) +#error "MBEDTLS_PSA_INJECT_ENTROPY is not compatible with actual entropy sources" +#endif + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ + defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +#error "MBEDTLS_PSA_INJECT_ENTROPY is not compatible with MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG" +#endif + +#if defined(MBEDTLS_PSA_ITS_FILE_C) && \ + !defined(MBEDTLS_FS_IO) +#error "MBEDTLS_PSA_ITS_FILE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ + !defined(MBEDTLS_OID_C) ) +#error "MBEDTLS_RSA_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_PKCS1_V21) && \ + !defined(MBEDTLS_PKCS1_V15) ) +#error "MBEDTLS_RSA_C defined, but none of the PKCS1 versions enabled" +#endif + +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) && \ + ( !defined(MBEDTLS_RSA_C) || !defined(MBEDTLS_PKCS1_V21) ) +#error "MBEDTLS_X509_RSASSA_PSS_SUPPORT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) && \ + defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) +#error "Must only define one of MBEDTLS_SHA512_USE_A64_CRYPTO_*" +#endif + +#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT) || \ + defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) +#if !defined(MBEDTLS_SHA512_C) +#error "MBEDTLS_SHA512_USE_A64_CRYPTO_* defined without MBEDTLS_SHA512_C" +#endif +#if defined(MBEDTLS_SHA512_ALT) || defined(MBEDTLS_SHA512_PROCESS_ALT) +#error "MBEDTLS_SHA512_*ALT can't be used with MBEDTLS_SHA512_USE_A64_CRYPTO_*" +#endif + +#endif /* MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT || MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY */ + +#if defined(MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY) && !defined(__aarch64__) +#error "MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY defined on non-Aarch64 system" +#endif + +#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) && \ + defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#error "Must only define one of MBEDTLS_SHA256_USE_A64_CRYPTO_*" +#endif + +#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT) || \ + defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) +#if !defined(MBEDTLS_SHA256_C) +#error "MBEDTLS_SHA256_USE_A64_CRYPTO_* defined without MBEDTLS_SHA256_C" +#endif +#if defined(MBEDTLS_SHA256_ALT) || defined(MBEDTLS_SHA256_PROCESS_ALT) +#error "MBEDTLS_SHA256_*ALT can't be used with MBEDTLS_SHA256_USE_A64_CRYPTO_*" +#endif + +#endif + +#if defined(MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY) && \ + !defined(__aarch64__) && !defined(_M_ARM64) +#error "MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY defined on non-Aarch64 system" +#endif + +/* TLS 1.3 requires separate HKDF parts from PSA, + * and at least one ciphersuite, so at least SHA-256 or SHA-384 + * from PSA to use with HKDF. + * + * Note: for dependencies common with TLS 1.2 (running handshake hash), + * see MBEDTLS_SSL_TLS_C. */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ + !(defined(MBEDTLS_PSA_CRYPTO_C) && \ + defined(PSA_WANT_ALG_HKDF_EXTRACT) && \ + defined(PSA_WANT_ALG_HKDF_EXPAND) && \ + (defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_384))) +#error "MBEDTLS_SSL_PROTO_TLS1_3 defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +#if !( (defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH)) && \ + defined(MBEDTLS_X509_CRT_PARSE_C) && \ + ( defined(MBEDTLS_PK_CAN_ECDSA_SIGN) || defined(MBEDTLS_PKCS1_V21) ) ) +#error "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED defined, but not all prerequisites" +#endif +#endif + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) +#if !( defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) ) +#error "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED defined, but not all prerequisites" +#endif +#endif + +/* + * The current implementation of TLS 1.3 requires MBEDTLS_SSL_KEEP_PEER_CERTIFICATE. + */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) +#error "MBEDTLS_SSL_PROTO_TLS1_3 defined without MBEDTLS_SSL_KEEP_PEER_CERTIFICATE" +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ + !(defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) ) +#error "One or more versions of the TLS protocol are enabled " \ + "but no key exchange methods defined with MBEDTLS_KEY_EXCHANGE_xxxx" +#endif + +#if defined(MBEDTLS_SSL_EARLY_DATA) && \ + ( !defined(MBEDTLS_SSL_SESSION_TICKETS) || \ + ( !defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED) && \ + !defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) ) ) +#error "MBEDTLS_SSL_EARLY_DATA defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_EARLY_DATA) && defined(MBEDTLS_SSL_SRV_C) && \ + defined(MBEDTLS_SSL_MAX_EARLY_DATA_SIZE) && \ + ((MBEDTLS_SSL_MAX_EARLY_DATA_SIZE < 0) || \ + (MBEDTLS_SSL_MAX_EARLY_DATA_SIZE > UINT32_MAX)) +#error "MBEDTLS_SSL_MAX_EARLY_DATA_SIZE must be in the range(0..UINT32_MAX)" +#endif + +#if defined(MBEDTLS_SSL_PROTO_DTLS) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_PROTO_DTLS defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_CLI_C) && !defined(MBEDTLS_SSL_TLS_C) +#error "MBEDTLS_SSL_CLI_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) && !defined(MBEDTLS_X509_CRT_PARSE_C) +#error "MBEDTLS_SSL_ASYNC_PRIVATE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && !defined(MBEDTLS_CIPHER_C) +#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" +#endif + +/* TLS 1.2 and 1.3 require SHA-256 or SHA-384 (running handshake hash) */ +#if defined(MBEDTLS_SSL_TLS_C) +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if !(defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_384)) +#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" +#endif +#else /* MBEDTLS_USE_PSA_CRYPTO */ +#if !defined(MBEDTLS_MD_C) || \ + !(defined(MBEDTLS_MD_HAVE_SHA256) || defined(MBEDTLS_MD_HAVE_SHA384)) +#error "MBEDTLS_SSL_TLS_C defined, but not all prerequisites" +#endif +#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_SSL_TLS_C */ + +#if defined(MBEDTLS_SSL_SRV_C) && !defined(MBEDTLS_SSL_TLS_C) +#error "MBEDTLS_SSL_SRV_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS_C) && \ + !( defined(MBEDTLS_SSL_PROTO_TLS1_2) || defined(MBEDTLS_SSL_PROTO_TLS1_3) ) +#error "MBEDTLS_SSL_TLS_C defined, but no protocols are active" +#endif + +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && !defined(MBEDTLS_SSL_PROTO_DTLS) +#error "MBEDTLS_SSL_DTLS_HELLO_VERIFY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && \ + !defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) +#error "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) && \ + ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_ANTI_REPLAY defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ + ( !defined(MBEDTLS_SSL_TLS_C) || !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_CONNECTION_ID defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ + defined(MBEDTLS_SSL_CID_IN_LEN_MAX) && \ + MBEDTLS_SSL_CID_IN_LEN_MAX > 255 +#error "MBEDTLS_SSL_CID_IN_LEN_MAX too large (max 255)" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) && \ + defined(MBEDTLS_SSL_CID_OUT_LEN_MAX) && \ + MBEDTLS_SSL_CID_OUT_LEN_MAX > 255 +#error "MBEDTLS_SSL_CID_OUT_LEN_MAX too large (max 255)" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) && \ + !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +#error "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) && MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT != 0 +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT is deprecated and will be removed in a future version of Mbed TLS" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT is deprecated and will be removed in a future version of Mbed TLS" +#endif +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT && MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT != 0 */ + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_ENCRYPT_THEN_MAC defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_EXTENDED_MASTER_SECRET defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_RENEGOTIATION) && \ + !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#error "MBEDTLS_SSL_RENEGOTIATION defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TICKET_C) && ( !defined(MBEDTLS_CIPHER_C) && \ + !defined(MBEDTLS_USE_PSA_CRYPTO) ) +#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TICKET_C) && \ + !( defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) ) +#error "MBEDTLS_SSL_TICKET_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH) && \ + MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH >= 256 +#error "MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH must be less than 256" +#endif + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \ + !defined(MBEDTLS_X509_CRT_PARSE_C) +#error "MBEDTLS_SSL_SERVER_NAME_INDICATION defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_THREADING_PTHREAD) +#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_PTHREAD defined, but not all prerequisites" +#endif +#define MBEDTLS_THREADING_IMPL +#endif + +#if defined(MBEDTLS_THREADING_ALT) +#if !defined(MBEDTLS_THREADING_C) || defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_ALT defined, but not all prerequisites" +#endif +#define MBEDTLS_THREADING_IMPL +#endif + +#if defined(MBEDTLS_THREADING_C) && !defined(MBEDTLS_THREADING_IMPL) +#error "MBEDTLS_THREADING_C defined, single threading implementation required" +#endif +#undef MBEDTLS_THREADING_IMPL + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_PSA_CRYPTO_C) +#error "MBEDTLS_USE_PSA_CRYPTO defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_VERSION_FEATURES) && !defined(MBEDTLS_VERSION_C) +#error "MBEDTLS_VERSION_FEATURES defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_USE_C) && \ + (!defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_PARSE_C) || \ + !defined(MBEDTLS_PK_PARSE_C) || \ + ( !defined(MBEDTLS_MD_C) && !defined(MBEDTLS_USE_PSA_CRYPTO) ) ) +#error "MBEDTLS_X509_USE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CREATE_C) && \ + (!defined(MBEDTLS_OID_C) || !defined(MBEDTLS_ASN1_WRITE_C) || \ + !defined(MBEDTLS_PK_PARSE_C) || \ + ( !defined(MBEDTLS_MD_C) && !defined(MBEDTLS_USE_PSA_CRYPTO) ) ) +#error "MBEDTLS_X509_CREATE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CRT_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRL_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CRL_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CSR_PARSE_C) && ( !defined(MBEDTLS_X509_USE_C) ) +#error "MBEDTLS_X509_CSR_PARSE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CRT_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) +#error "MBEDTLS_X509_CRT_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_CSR_WRITE_C) && ( !defined(MBEDTLS_X509_CREATE_C) ) +#error "MBEDTLS_X509_CSR_WRITE_C defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) && \ + ( !defined(MBEDTLS_X509_CRT_PARSE_C) ) +#error "MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_HAVE_INT32) && defined(MBEDTLS_HAVE_INT64) +#error "MBEDTLS_HAVE_INT32 and MBEDTLS_HAVE_INT64 cannot be defined simultaneously" +#endif /* MBEDTLS_HAVE_INT32 && MBEDTLS_HAVE_INT64 */ + +#if ( defined(MBEDTLS_HAVE_INT32) || defined(MBEDTLS_HAVE_INT64) ) && \ + defined(MBEDTLS_HAVE_ASM) +#error "MBEDTLS_HAVE_INT32/MBEDTLS_HAVE_INT64 and MBEDTLS_HAVE_ASM cannot be defined simultaneously" +#endif /* (MBEDTLS_HAVE_INT32 || MBEDTLS_HAVE_INT64) && MBEDTLS_HAVE_ASM */ + +#if defined(MBEDTLS_SSL_DTLS_SRTP) && ( !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_SRTP defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) && ( !defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) ) +#error "MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_RECORD_SIZE_LIMIT) && ( !defined(MBEDTLS_SSL_PROTO_TLS1_3) ) +#error "MBEDTLS_SSL_RECORD_SIZE_LIMIT defined, but not all prerequisites" +#endif + +#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) && !( defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) ) +#error "MBEDTLS_SSL_CONTEXT_SERIALIZATION defined, but not all prerequisites" +#endif + +/* Reject attempts to enable options that have been removed and that could + * cause a build to succeed but with features removed. */ + +#if defined(MBEDTLS_HAVEGE_C) //no-check-names +#error "MBEDTLS_HAVEGE_C was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/2599" +#endif + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) //no-check-names +#error "MBEDTLS_SSL_HW_RECORD_ACCEL was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" +#endif + +#if defined(MBEDTLS_SSL_PROTO_SSL3) //no-check-names +#error "MBEDTLS_SSL_PROTO_SSL3 (SSL v3.0 support) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" +#endif + +#if defined(MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO) //no-check-names +#error "MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO (SSL v2 ClientHello support) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" +#endif + +#if defined(MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT) //no-check-names +#error "MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT (compatibility with the buggy implementation of truncated HMAC in Mbed TLS up to 2.7) was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" +#endif + +#if defined(MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES) //no-check-names +#error "MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_CERTIFICATES was removed in Mbed TLS 3.0. See the ChangeLog entry if you really need SHA-1-signed certificates." +#endif + +#if defined(MBEDTLS_ZLIB_SUPPORT) //no-check-names +#error "MBEDTLS_ZLIB_SUPPORT was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4031" +#endif + +#if defined(MBEDTLS_CHECK_PARAMS) //no-check-names +#error "MBEDTLS_CHECK_PARAMS was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4313" +#endif + +#if defined(MBEDTLS_SSL_CID_PADDING_GRANULARITY) //no-check-names +#error "MBEDTLS_SSL_CID_PADDING_GRANULARITY was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4335" +#endif + +#if defined(MBEDTLS_SSL_TLS1_3_PADDING_GRANULARITY) //no-check-names +#error "MBEDTLS_SSL_TLS1_3_PADDING_GRANULARITY was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4335" +#endif + +#if defined(MBEDTLS_SSL_TRUNCATED_HMAC) //no-check-names +#error "MBEDTLS_SSL_TRUNCATED_HMAC was removed in Mbed TLS 3.0. See https://github.com/Mbed-TLS/mbedtls/issues/4341" +#endif + +#if defined(MBEDTLS_PKCS7_C) && ( ( !defined(MBEDTLS_ASN1_PARSE_C) ) || \ + ( !defined(MBEDTLS_OID_C) ) || ( !defined(MBEDTLS_PK_PARSE_C) ) || \ + ( !defined(MBEDTLS_X509_CRT_PARSE_C) ) || \ + ( !defined(MBEDTLS_X509_CRL_PARSE_C) ) || \ + ( !defined(MBEDTLS_MD_C) ) ) +#error "MBEDTLS_PKCS7_C is defined, but not all prerequisites" +#endif + +/* Undefine helper symbols */ +#undef MBEDTLS_PK_HAVE_JPAKE +#undef MBEDTLS_MD_HAVE_SHA256 +#undef MBEDTLS_MD_HAVE_SHA384 +#undef MBEDTLS_MD_HAVE_SHA512 +#undef MBEDTLS_PK_HAVE_CURVE_SECP256R1 + +/* + * Avoid warning from -pedantic. This is a convenient place for this + * workaround since this is included by every single file before the + * #if defined(MBEDTLS_xxx_C) that results in empty translation units. + */ +typedef int mbedtls_iso_c_forbids_empty_translation_units; + +/* *INDENT-ON* */ +#endif /* MBEDTLS_CHECK_CONFIG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cipher.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cipher.h index 6b39303..1d45634 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cipher.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cipher.h @@ -1,1189 +1,1189 @@ -/** - * \file cipher.h - * - * \brief This file contains an abstraction interface for use with the cipher - * primitives provided by the library. It provides a common interface to all of - * the available cipher operations. - * - * \author Adriaan de Jong - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CIPHER_H -#define MBEDTLS_CIPHER_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include "mbedtls/platform_util.h" - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) -#define MBEDTLS_CIPHER_MODE_AEAD -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -#define MBEDTLS_CIPHER_MODE_WITH_PADDING -#endif - -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) || \ - defined(MBEDTLS_CHACHA20_C) -#define MBEDTLS_CIPHER_MODE_STREAM -#endif - -/** The selected feature is not available. */ -#define MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE -0x6080 -/** Bad input parameters. */ -#define MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA -0x6100 -/** Failed to allocate memory. */ -#define MBEDTLS_ERR_CIPHER_ALLOC_FAILED -0x6180 -/** Input data contains invalid padding and is rejected. */ -#define MBEDTLS_ERR_CIPHER_INVALID_PADDING -0x6200 -/** Decryption of block requires a full block. */ -#define MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED -0x6280 -/** Authentication failed (for AEAD modes). */ -#define MBEDTLS_ERR_CIPHER_AUTH_FAILED -0x6300 -/** The context is invalid. For example, because it was freed. */ -#define MBEDTLS_ERR_CIPHER_INVALID_CONTEXT -0x6380 - -#define MBEDTLS_CIPHER_VARIABLE_IV_LEN 0x01 /**< Cipher accepts IVs of variable length. */ -#define MBEDTLS_CIPHER_VARIABLE_KEY_LEN 0x02 /**< Cipher accepts keys of variable length. */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Supported cipher types. - * - * \warning DES/3DES are considered weak ciphers and their use - * constitutes a security risk. We recommend considering stronger - * ciphers instead. - */ -typedef enum { - MBEDTLS_CIPHER_ID_NONE = 0, /**< Placeholder to mark the end of cipher ID lists. */ - MBEDTLS_CIPHER_ID_NULL, /**< The identity cipher, treated as a stream cipher. */ - MBEDTLS_CIPHER_ID_AES, /**< The AES cipher. */ - MBEDTLS_CIPHER_ID_DES, /**< The DES cipher. \warning DES is considered weak. */ - MBEDTLS_CIPHER_ID_3DES, /**< The Triple DES cipher. \warning 3DES is considered weak. */ - MBEDTLS_CIPHER_ID_CAMELLIA, /**< The Camellia cipher. */ - MBEDTLS_CIPHER_ID_ARIA, /**< The Aria cipher. */ - MBEDTLS_CIPHER_ID_CHACHA20, /**< The ChaCha20 cipher. */ -} mbedtls_cipher_id_t; - -/** - * \brief Supported {cipher type, cipher mode} pairs. - * - * \warning DES/3DES are considered weak ciphers and their use - * constitutes a security risk. We recommend considering stronger - * ciphers instead. - */ -typedef enum { - MBEDTLS_CIPHER_NONE = 0, /**< Placeholder to mark the end of cipher-pair lists. */ - MBEDTLS_CIPHER_NULL, /**< The identity stream cipher. */ - MBEDTLS_CIPHER_AES_128_ECB, /**< AES cipher with 128-bit ECB mode. */ - MBEDTLS_CIPHER_AES_192_ECB, /**< AES cipher with 192-bit ECB mode. */ - MBEDTLS_CIPHER_AES_256_ECB, /**< AES cipher with 256-bit ECB mode. */ - MBEDTLS_CIPHER_AES_128_CBC, /**< AES cipher with 128-bit CBC mode. */ - MBEDTLS_CIPHER_AES_192_CBC, /**< AES cipher with 192-bit CBC mode. */ - MBEDTLS_CIPHER_AES_256_CBC, /**< AES cipher with 256-bit CBC mode. */ - MBEDTLS_CIPHER_AES_128_CFB128, /**< AES cipher with 128-bit CFB128 mode. */ - MBEDTLS_CIPHER_AES_192_CFB128, /**< AES cipher with 192-bit CFB128 mode. */ - MBEDTLS_CIPHER_AES_256_CFB128, /**< AES cipher with 256-bit CFB128 mode. */ - MBEDTLS_CIPHER_AES_128_CTR, /**< AES cipher with 128-bit CTR mode. */ - MBEDTLS_CIPHER_AES_192_CTR, /**< AES cipher with 192-bit CTR mode. */ - MBEDTLS_CIPHER_AES_256_CTR, /**< AES cipher with 256-bit CTR mode. */ - MBEDTLS_CIPHER_AES_128_GCM, /**< AES cipher with 128-bit GCM mode. */ - MBEDTLS_CIPHER_AES_192_GCM, /**< AES cipher with 192-bit GCM mode. */ - MBEDTLS_CIPHER_AES_256_GCM, /**< AES cipher with 256-bit GCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_ECB, /**< Camellia cipher with 128-bit ECB mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_ECB, /**< Camellia cipher with 192-bit ECB mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_ECB, /**< Camellia cipher with 256-bit ECB mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_CBC, /**< Camellia cipher with 128-bit CBC mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_CBC, /**< Camellia cipher with 192-bit CBC mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_CBC, /**< Camellia cipher with 256-bit CBC mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_CFB128, /**< Camellia cipher with 128-bit CFB128 mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_CFB128, /**< Camellia cipher with 192-bit CFB128 mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_CFB128, /**< Camellia cipher with 256-bit CFB128 mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_CTR, /**< Camellia cipher with 128-bit CTR mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_CTR, /**< Camellia cipher with 192-bit CTR mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_CTR, /**< Camellia cipher with 256-bit CTR mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_GCM, /**< Camellia cipher with 128-bit GCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_GCM, /**< Camellia cipher with 192-bit GCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_GCM, /**< Camellia cipher with 256-bit GCM mode. */ - MBEDTLS_CIPHER_DES_ECB, /**< DES cipher with ECB mode. \warning DES is considered weak. */ - MBEDTLS_CIPHER_DES_CBC, /**< DES cipher with CBC mode. \warning DES is considered weak. */ - MBEDTLS_CIPHER_DES_EDE_ECB, /**< DES cipher with EDE ECB mode. \warning 3DES is considered weak. */ - MBEDTLS_CIPHER_DES_EDE_CBC, /**< DES cipher with EDE CBC mode. \warning 3DES is considered weak. */ - MBEDTLS_CIPHER_DES_EDE3_ECB, /**< DES cipher with EDE3 ECB mode. \warning 3DES is considered weak. */ - MBEDTLS_CIPHER_DES_EDE3_CBC, /**< DES cipher with EDE3 CBC mode. \warning 3DES is considered weak. */ - MBEDTLS_CIPHER_AES_128_CCM, /**< AES cipher with 128-bit CCM mode. */ - MBEDTLS_CIPHER_AES_192_CCM, /**< AES cipher with 192-bit CCM mode. */ - MBEDTLS_CIPHER_AES_256_CCM, /**< AES cipher with 256-bit CCM mode. */ - MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, /**< AES cipher with 128-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, /**< AES cipher with 192-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, /**< AES cipher with 256-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_CCM, /**< Camellia cipher with 128-bit CCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_CCM, /**< Camellia cipher with 192-bit CCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_CCM, /**< Camellia cipher with 256-bit CCM mode. */ - MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, /**< Camellia cipher with 128-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, /**< Camellia cipher with 192-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, /**< Camellia cipher with 256-bit CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_ARIA_128_ECB, /**< Aria cipher with 128-bit key and ECB mode. */ - MBEDTLS_CIPHER_ARIA_192_ECB, /**< Aria cipher with 192-bit key and ECB mode. */ - MBEDTLS_CIPHER_ARIA_256_ECB, /**< Aria cipher with 256-bit key and ECB mode. */ - MBEDTLS_CIPHER_ARIA_128_CBC, /**< Aria cipher with 128-bit key and CBC mode. */ - MBEDTLS_CIPHER_ARIA_192_CBC, /**< Aria cipher with 192-bit key and CBC mode. */ - MBEDTLS_CIPHER_ARIA_256_CBC, /**< Aria cipher with 256-bit key and CBC mode. */ - MBEDTLS_CIPHER_ARIA_128_CFB128, /**< Aria cipher with 128-bit key and CFB-128 mode. */ - MBEDTLS_CIPHER_ARIA_192_CFB128, /**< Aria cipher with 192-bit key and CFB-128 mode. */ - MBEDTLS_CIPHER_ARIA_256_CFB128, /**< Aria cipher with 256-bit key and CFB-128 mode. */ - MBEDTLS_CIPHER_ARIA_128_CTR, /**< Aria cipher with 128-bit key and CTR mode. */ - MBEDTLS_CIPHER_ARIA_192_CTR, /**< Aria cipher with 192-bit key and CTR mode. */ - MBEDTLS_CIPHER_ARIA_256_CTR, /**< Aria cipher with 256-bit key and CTR mode. */ - MBEDTLS_CIPHER_ARIA_128_GCM, /**< Aria cipher with 128-bit key and GCM mode. */ - MBEDTLS_CIPHER_ARIA_192_GCM, /**< Aria cipher with 192-bit key and GCM mode. */ - MBEDTLS_CIPHER_ARIA_256_GCM, /**< Aria cipher with 256-bit key and GCM mode. */ - MBEDTLS_CIPHER_ARIA_128_CCM, /**< Aria cipher with 128-bit key and CCM mode. */ - MBEDTLS_CIPHER_ARIA_192_CCM, /**< Aria cipher with 192-bit key and CCM mode. */ - MBEDTLS_CIPHER_ARIA_256_CCM, /**< Aria cipher with 256-bit key and CCM mode. */ - MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, /**< Aria cipher with 128-bit key and CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, /**< Aria cipher with 192-bit key and CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, /**< Aria cipher with 256-bit key and CCM_STAR_NO_TAG mode. */ - MBEDTLS_CIPHER_AES_128_OFB, /**< AES 128-bit cipher in OFB mode. */ - MBEDTLS_CIPHER_AES_192_OFB, /**< AES 192-bit cipher in OFB mode. */ - MBEDTLS_CIPHER_AES_256_OFB, /**< AES 256-bit cipher in OFB mode. */ - MBEDTLS_CIPHER_AES_128_XTS, /**< AES 128-bit cipher in XTS block mode. */ - MBEDTLS_CIPHER_AES_256_XTS, /**< AES 256-bit cipher in XTS block mode. */ - MBEDTLS_CIPHER_CHACHA20, /**< ChaCha20 stream cipher. */ - MBEDTLS_CIPHER_CHACHA20_POLY1305, /**< ChaCha20-Poly1305 AEAD cipher. */ - MBEDTLS_CIPHER_AES_128_KW, /**< AES cipher with 128-bit NIST KW mode. */ - MBEDTLS_CIPHER_AES_192_KW, /**< AES cipher with 192-bit NIST KW mode. */ - MBEDTLS_CIPHER_AES_256_KW, /**< AES cipher with 256-bit NIST KW mode. */ - MBEDTLS_CIPHER_AES_128_KWP, /**< AES cipher with 128-bit NIST KWP mode. */ - MBEDTLS_CIPHER_AES_192_KWP, /**< AES cipher with 192-bit NIST KWP mode. */ - MBEDTLS_CIPHER_AES_256_KWP, /**< AES cipher with 256-bit NIST KWP mode. */ -} mbedtls_cipher_type_t; - -/** Supported cipher modes. */ -typedef enum { - MBEDTLS_MODE_NONE = 0, /**< None. */ - MBEDTLS_MODE_ECB, /**< The ECB cipher mode. */ - MBEDTLS_MODE_CBC, /**< The CBC cipher mode. */ - MBEDTLS_MODE_CFB, /**< The CFB cipher mode. */ - MBEDTLS_MODE_OFB, /**< The OFB cipher mode. */ - MBEDTLS_MODE_CTR, /**< The CTR cipher mode. */ - MBEDTLS_MODE_GCM, /**< The GCM cipher mode. */ - MBEDTLS_MODE_STREAM, /**< The stream cipher mode. */ - MBEDTLS_MODE_CCM, /**< The CCM cipher mode. */ - MBEDTLS_MODE_CCM_STAR_NO_TAG, /**< The CCM*-no-tag cipher mode. */ - MBEDTLS_MODE_XTS, /**< The XTS cipher mode. */ - MBEDTLS_MODE_CHACHAPOLY, /**< The ChaCha-Poly cipher mode. */ - MBEDTLS_MODE_KW, /**< The SP800-38F KW mode */ - MBEDTLS_MODE_KWP, /**< The SP800-38F KWP mode */ -} mbedtls_cipher_mode_t; - -/** Supported cipher padding types. */ -typedef enum { - MBEDTLS_PADDING_PKCS7 = 0, /**< PKCS7 padding (default). */ - MBEDTLS_PADDING_ONE_AND_ZEROS, /**< ISO/IEC 7816-4 padding. */ - MBEDTLS_PADDING_ZEROS_AND_LEN, /**< ANSI X.923 padding. */ - MBEDTLS_PADDING_ZEROS, /**< Zero padding (not reversible). */ - MBEDTLS_PADDING_NONE, /**< Never pad (full blocks only). */ -} mbedtls_cipher_padding_t; - -/** Type of operation. */ -typedef enum { - MBEDTLS_OPERATION_NONE = -1, - MBEDTLS_DECRYPT = 0, - MBEDTLS_ENCRYPT, -} mbedtls_operation_t; - -enum { - /** Undefined key length. */ - MBEDTLS_KEY_LENGTH_NONE = 0, - /** Key length, in bits (including parity), for DES keys. \warning DES is considered weak. */ - MBEDTLS_KEY_LENGTH_DES = 64, - /** Key length in bits, including parity, for DES in two-key EDE. \warning 3DES is considered weak. */ - MBEDTLS_KEY_LENGTH_DES_EDE = 128, - /** Key length in bits, including parity, for DES in three-key EDE. \warning 3DES is considered weak. */ - MBEDTLS_KEY_LENGTH_DES_EDE3 = 192, -}; - -/** Maximum length of any IV, in Bytes. */ -/* This should ideally be derived automatically from list of ciphers. - * This should be kept in sync with MBEDTLS_SSL_MAX_IV_LENGTH defined - * in library/ssl_misc.h. */ -#define MBEDTLS_MAX_IV_LENGTH 16 - -/** Maximum block size of any cipher, in Bytes. */ -/* This should ideally be derived automatically from list of ciphers. - * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined - * in library/ssl_misc.h. */ -#define MBEDTLS_MAX_BLOCK_LENGTH 16 - -/** Maximum key length, in Bytes. */ -/* This should ideally be derived automatically from list of ciphers. - * For now, only check whether XTS is enabled which uses 64 Byte keys, - * and use 32 Bytes as an upper bound for the maximum key length otherwise. - * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined - * in library/ssl_misc.h, which however deliberately ignores the case of XTS - * since the latter isn't used in SSL/TLS. */ -#if defined(MBEDTLS_CIPHER_MODE_XTS) -#define MBEDTLS_MAX_KEY_LENGTH 64 -#else -#define MBEDTLS_MAX_KEY_LENGTH 32 -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -/** - * Base cipher information (opaque struct). - */ -typedef struct mbedtls_cipher_base_t mbedtls_cipher_base_t; - -/** - * CMAC context (opaque struct). - */ -typedef struct mbedtls_cmac_context_t mbedtls_cmac_context_t; - -/** - * Cipher information. Allows calling cipher functions - * in a generic way. - * - * \note The library does not support custom cipher info structures, - * only built-in structures returned by the functions - * mbedtls_cipher_info_from_string(), - * mbedtls_cipher_info_from_type(), - * mbedtls_cipher_info_from_values(), - * mbedtls_cipher_info_from_psa(). - * - * \note Some fields store a value that has been right-shifted to save - * code-size, so should not be used directly. The accessor - * functions adjust for this and return the "natural" value. - */ -typedef struct mbedtls_cipher_info_t { - /** Name of the cipher. */ - const char *MBEDTLS_PRIVATE(name); - - /** The block size, in bytes. */ - unsigned int MBEDTLS_PRIVATE(block_size) : 5; - - /** IV or nonce size, in bytes (right shifted by #MBEDTLS_IV_SIZE_SHIFT). - * For ciphers that accept variable IV sizes, - * this is the recommended size. - */ - unsigned int MBEDTLS_PRIVATE(iv_size) : 3; - - /** The cipher key length, in bits (right shifted by #MBEDTLS_KEY_BITLEN_SHIFT). - * This is the default length for variable sized ciphers. - * Includes parity bits for ciphers like DES. - */ - unsigned int MBEDTLS_PRIVATE(key_bitlen) : 4; - - /** The cipher mode (as per mbedtls_cipher_mode_t). - * For example, MBEDTLS_MODE_CBC. - */ - unsigned int MBEDTLS_PRIVATE(mode) : 4; - - /** Full cipher identifier (as per mbedtls_cipher_type_t). - * For example, MBEDTLS_CIPHER_AES_256_CBC. - * - * This could be 7 bits, but 8 bits retains byte alignment for the - * next field, which reduces code size to access that field. - */ - unsigned int MBEDTLS_PRIVATE(type) : 8; - - /** Bitflag comprised of MBEDTLS_CIPHER_VARIABLE_IV_LEN and - * MBEDTLS_CIPHER_VARIABLE_KEY_LEN indicating whether the - * cipher supports variable IV or variable key sizes, respectively. - */ - unsigned int MBEDTLS_PRIVATE(flags) : 2; - - /** Index to LUT for base cipher information and functions. */ - unsigned int MBEDTLS_PRIVATE(base_idx) : 5; - -} mbedtls_cipher_info_t; - -/* For internal use only. - * These are used to more compactly represent the fields above. */ -#define MBEDTLS_KEY_BITLEN_SHIFT 6 -#define MBEDTLS_IV_SIZE_SHIFT 2 -/** - * Generic cipher context. - */ -typedef struct mbedtls_cipher_context_t { - /** Information about the associated cipher. */ - const mbedtls_cipher_info_t *MBEDTLS_PRIVATE(cipher_info); - - /** Key length to use. */ - int MBEDTLS_PRIVATE(key_bitlen); - - /** Operation that the key of the context has been - * initialized for. - */ - mbedtls_operation_t MBEDTLS_PRIVATE(operation); - - /** Padding functions to use, if relevant for - * the specific cipher mode. - */ - void(*MBEDTLS_PRIVATE(add_padding))(unsigned char *output, size_t olen, size_t data_len); - int(*MBEDTLS_PRIVATE(get_padding))(unsigned char *input, size_t ilen, size_t *data_len); - - /** Buffer for input that has not been processed yet. */ - unsigned char MBEDTLS_PRIVATE(unprocessed_data)[MBEDTLS_MAX_BLOCK_LENGTH]; - - /** Number of Bytes that have not been processed yet. */ - size_t MBEDTLS_PRIVATE(unprocessed_len); - - /** Current IV or NONCE_COUNTER for CTR-mode, data unit (or sector) number - * for XTS-mode. */ - unsigned char MBEDTLS_PRIVATE(iv)[MBEDTLS_MAX_IV_LENGTH]; - - /** IV size in Bytes, for ciphers with variable-length IVs. */ - size_t MBEDTLS_PRIVATE(iv_size); - - /** The cipher-specific context. */ - void *MBEDTLS_PRIVATE(cipher_ctx); - - /** CMAC-specific context. */ - mbedtls_cmac_context_t *MBEDTLS_PRIVATE(cmac_ctx); - - /** Indicates whether the cipher operations should be performed - * by Mbed TLS' own crypto library or an external implementation - * of the PSA Crypto API. - * This is unset if the cipher context was established through - * mbedtls_cipher_setup(), and set if it was established through - * mbedtls_cipher_setup_psa(). - */ - unsigned char MBEDTLS_PRIVATE(psa_enabled); - -} mbedtls_cipher_context_t; - -/** - * \brief This function retrieves the list of ciphers supported - * by the generic cipher module. - * - * For any cipher identifier in the returned list, you can - * obtain the corresponding generic cipher information structure - * via mbedtls_cipher_info_from_type(), which can then be used - * to prepare a cipher context via mbedtls_cipher_setup(). - * - * - * \return A statically-allocated array of cipher identifiers - * of type cipher_type_t. The last entry is zero. - */ -const int *mbedtls_cipher_list(void); - -/** - * \brief This function retrieves the cipher-information - * structure associated with the given cipher name. - * - * \param cipher_name Name of the cipher to search for. This must not be - * \c NULL. - * - * \return The cipher information structure associated with the - * given \p cipher_name. - * \return \c NULL if the associated cipher information is not found. - */ -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string(const char *cipher_name); - -/** - * \brief This function retrieves the cipher-information - * structure associated with the given cipher type. - * - * \param cipher_type Type of the cipher to search for. - * - * \return The cipher information structure associated with the - * given \p cipher_type. - * \return \c NULL if the associated cipher information is not found. - */ -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type(const mbedtls_cipher_type_t cipher_type); - -/** - * \brief This function retrieves the cipher-information - * structure associated with the given cipher ID, - * key size and mode. - * - * \param cipher_id The ID of the cipher to search for. For example, - * #MBEDTLS_CIPHER_ID_AES. - * \param key_bitlen The length of the key in bits. - * \param mode The cipher mode. For example, #MBEDTLS_MODE_CBC. - * - * \return The cipher information structure associated with the - * given \p cipher_id. - * \return \c NULL if the associated cipher information is not found. - */ -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values(const mbedtls_cipher_id_t cipher_id, - int key_bitlen, - const mbedtls_cipher_mode_t mode); - -/** - * \brief Retrieve the identifier for a cipher info structure. - * - * \param[in] info The cipher info structure to query. - * This may be \c NULL. - * - * \return The full cipher identifier (\c MBEDTLS_CIPHER_xxx). - * \return #MBEDTLS_CIPHER_NONE if \p info is \c NULL. - */ -static inline mbedtls_cipher_type_t mbedtls_cipher_info_get_type( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return MBEDTLS_CIPHER_NONE; - } else { - return (mbedtls_cipher_type_t) info->MBEDTLS_PRIVATE(type); - } -} - -/** - * \brief Retrieve the operation mode for a cipher info structure. - * - * \param[in] info The cipher info structure to query. - * This may be \c NULL. - * - * \return The cipher mode (\c MBEDTLS_MODE_xxx). - * \return #MBEDTLS_MODE_NONE if \p info is \c NULL. - */ -static inline mbedtls_cipher_mode_t mbedtls_cipher_info_get_mode( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return MBEDTLS_MODE_NONE; - } else { - return (mbedtls_cipher_mode_t) info->MBEDTLS_PRIVATE(mode); - } -} - -/** - * \brief Retrieve the key size for a cipher info structure. - * - * \param[in] info The cipher info structure to query. - * This may be \c NULL. - * - * \return The key length in bits. - * For variable-sized ciphers, this is the default length. - * For DES, this includes the parity bits. - * \return \c 0 if \p info is \c NULL. - */ -static inline size_t mbedtls_cipher_info_get_key_bitlen( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return 0; - } else { - return info->MBEDTLS_PRIVATE(key_bitlen) << MBEDTLS_KEY_BITLEN_SHIFT; - } -} - -/** - * \brief Retrieve the human-readable name for a - * cipher info structure. - * - * \param[in] info The cipher info structure to query. - * This may be \c NULL. - * - * \return The cipher name, which is a human readable string, - * with static storage duration. - * \return \c NULL if \p info is \c NULL. - */ -static inline const char *mbedtls_cipher_info_get_name( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return NULL; - } else { - return info->MBEDTLS_PRIVATE(name); - } -} - -/** - * \brief This function returns the size of the IV or nonce - * for the cipher info structure, in bytes. - * - * \param info The cipher info structure. This may be \c NULL. - * - * \return The recommended IV size. - * \return \c 0 for ciphers not using an IV or a nonce. - * \return \c 0 if \p info is \c NULL. - */ -static inline size_t mbedtls_cipher_info_get_iv_size( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return 0; - } - - return ((size_t) info->MBEDTLS_PRIVATE(iv_size)) << MBEDTLS_IV_SIZE_SHIFT; -} - -/** - * \brief This function returns the block size of the given - * cipher info structure in bytes. - * - * \param info The cipher info structure. This may be \c NULL. - * - * \return The block size of the cipher. - * \return \c 1 if the cipher is a stream cipher. - * \return \c 0 if \p info is \c NULL. - */ -static inline size_t mbedtls_cipher_info_get_block_size( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return 0; - } - - return (size_t) (info->MBEDTLS_PRIVATE(block_size)); -} - -/** - * \brief This function returns a non-zero value if the key length for - * the given cipher is variable. - * - * \param info The cipher info structure. This may be \c NULL. - * - * \return Non-zero if the key length is variable, \c 0 otherwise. - * \return \c 0 if the given pointer is \c NULL. - */ -static inline int mbedtls_cipher_info_has_variable_key_bitlen( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return 0; - } - - return info->MBEDTLS_PRIVATE(flags) & MBEDTLS_CIPHER_VARIABLE_KEY_LEN; -} - -/** - * \brief This function returns a non-zero value if the IV size for - * the given cipher is variable. - * - * \param info The cipher info structure. This may be \c NULL. - * - * \return Non-zero if the IV size is variable, \c 0 otherwise. - * \return \c 0 if the given pointer is \c NULL. - */ -static inline int mbedtls_cipher_info_has_variable_iv_size( - const mbedtls_cipher_info_t *info) -{ - if (info == NULL) { - return 0; - } - - return info->MBEDTLS_PRIVATE(flags) & MBEDTLS_CIPHER_VARIABLE_IV_LEN; -} - -/** - * \brief This function initializes a \p ctx as NONE. - * - * \param ctx The context to be initialized. This must not be \c NULL. - */ -void mbedtls_cipher_init(mbedtls_cipher_context_t *ctx); - -/** - * \brief This function frees and clears the cipher-specific - * context of \p ctx. Freeing \p ctx itself remains the - * responsibility of the caller. - * - * \param ctx The context to be freed. If this is \c NULL, the - * function has no effect, otherwise this must point to an - * initialized context. - */ -void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx); - - -/** - * \brief This function prepares a cipher context for - * use with the given cipher primitive. - * - * \note After calling this function, you should call - * mbedtls_cipher_setkey() and, if the mode uses padding, - * mbedtls_cipher_set_padding_mode(), then for each - * message to encrypt or decrypt with this key, either: - * - mbedtls_cipher_crypt() for one-shot processing with - * non-AEAD modes; - * - mbedtls_cipher_auth_encrypt_ext() or - * mbedtls_cipher_auth_decrypt_ext() for one-shot - * processing with AEAD modes or NIST_KW; - * - for multi-part processing, see the documentation of - * mbedtls_cipher_reset(). - * - * \param ctx The context to prepare. This must be initialized by - * a call to mbedtls_cipher_init() first. - * \param cipher_info The cipher to use. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the - * cipher-specific context fails. - */ -int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, - const mbedtls_cipher_info_t *cipher_info); - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief This function initializes a cipher context for - * PSA-based use with the given cipher primitive. - * - * \deprecated This function is deprecated and will be removed in a - * future version of the library. - * Please use psa_aead_xxx() / psa_cipher_xxx() directly - * instead. - * - * \note See #MBEDTLS_USE_PSA_CRYPTO for information on PSA. - * - * \param ctx The context to initialize. May not be \c NULL. - * \param cipher_info The cipher to use. - * \param taglen For AEAD ciphers, the length in bytes of the - * authentication tag to use. Subsequent uses of - * mbedtls_cipher_auth_encrypt_ext() or - * mbedtls_cipher_auth_decrypt_ext() must provide - * the same tag length. - * For non-AEAD ciphers, the value must be \c 0. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the - * cipher-specific context fails. - */ -int MBEDTLS_DEPRECATED mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, - const mbedtls_cipher_info_t *cipher_info, - size_t taglen); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/** - * \brief This function returns the block size of the given cipher - * in bytes. - * - * \param ctx The context of the cipher. - * - * \return The block size of the underlying cipher. - * \return \c 1 if the cipher is a stream cipher. - * \return \c 0 if \p ctx has not been initialized. - */ -static inline unsigned int mbedtls_cipher_get_block_size( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return 0; - } - - return (unsigned int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(block_size); -} - -/** - * \brief This function returns the mode of operation for - * the cipher. For example, MBEDTLS_MODE_CBC. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The mode of operation. - * \return #MBEDTLS_MODE_NONE if \p ctx has not been initialized. - */ -static inline mbedtls_cipher_mode_t mbedtls_cipher_get_cipher_mode( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, MBEDTLS_MODE_NONE); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return MBEDTLS_MODE_NONE; - } - - return (mbedtls_cipher_mode_t) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(mode); -} - -/** - * \brief This function returns the size of the IV or nonce - * of the cipher, in Bytes. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The recommended IV size if no IV has been set. - * \return \c 0 for ciphers not using an IV or a nonce. - * \return The actual size if an IV has been set. - */ -static inline int mbedtls_cipher_get_iv_size( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return 0; - } - - if (ctx->MBEDTLS_PRIVATE(iv_size) != 0) { - return (int) ctx->MBEDTLS_PRIVATE(iv_size); - } - - return (int) (((int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(iv_size)) << - MBEDTLS_IV_SIZE_SHIFT); -} - -/** - * \brief This function returns the type of the given cipher. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The type of the cipher. - * \return #MBEDTLS_CIPHER_NONE if \p ctx has not been initialized. - */ -static inline mbedtls_cipher_type_t mbedtls_cipher_get_type( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET( - ctx != NULL, MBEDTLS_CIPHER_NONE); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return MBEDTLS_CIPHER_NONE; - } - - return (mbedtls_cipher_type_t) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(type); -} - -/** - * \brief This function returns the name of the given cipher - * as a string. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The name of the cipher. - * \return NULL if \p ctx has not been not initialized. - */ -static inline const char *mbedtls_cipher_get_name( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return 0; - } - - return ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(name); -} - -/** - * \brief This function returns the key length of the cipher. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The key length of the cipher in bits. - * \return #MBEDTLS_KEY_LENGTH_NONE if \p ctx has not been - * initialized. - */ -static inline int mbedtls_cipher_get_key_bitlen( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET( - ctx != NULL, MBEDTLS_KEY_LENGTH_NONE); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return MBEDTLS_KEY_LENGTH_NONE; - } - - return (int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(key_bitlen) << - MBEDTLS_KEY_BITLEN_SHIFT; -} - -/** - * \brief This function returns the operation of the given cipher. - * - * \param ctx The context of the cipher. This must be initialized. - * - * \return The type of operation: #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. - * \return #MBEDTLS_OPERATION_NONE if \p ctx has not been initialized. - */ -static inline mbedtls_operation_t mbedtls_cipher_get_operation( - const mbedtls_cipher_context_t *ctx) -{ - MBEDTLS_INTERNAL_VALIDATE_RET( - ctx != NULL, MBEDTLS_OPERATION_NONE); - if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { - return MBEDTLS_OPERATION_NONE; - } - - return ctx->MBEDTLS_PRIVATE(operation); -} - -/** - * \brief This function sets the key to use with the given context. - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a cipher information structure. - * \param key The key to use. This must be a readable buffer of at - * least \p key_bitlen Bits. - * \param key_bitlen The key length to use, in Bits. - * \param operation The operation that the key will be used for: - * #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, - const unsigned char *key, - int key_bitlen, - const mbedtls_operation_t operation); - -#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) -/** - * \brief This function sets the padding mode, for cipher modes - * that use padding. - * - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a cipher information structure. - * \param mode The padding mode. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE - * if the selected padding mode is not supported. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if the cipher mode - * does not support padding. - */ -int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, - mbedtls_cipher_padding_t mode); -#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ - -/** - * \brief This function sets the initialization vector (IV) - * or nonce. - * - * \note Some ciphers do not use IVs nor nonce. For these - * ciphers, this function has no effect. - * - * \note For #MBEDTLS_CIPHER_CHACHA20, the nonce length must - * be 12, and the initial counter value is 0. - * - * \note For #MBEDTLS_CIPHER_CHACHA20_POLY1305, the nonce length - * must be 12. - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a cipher information structure. - * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. This - * must be a readable buffer of at least \p iv_len Bytes. - * \param iv_len The IV length for ciphers with variable-size IV. - * This parameter is discarded by ciphers with fixed-size IV. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - */ -int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, - size_t iv_len); - -/** - * \brief This function resets the cipher state. - * - * \note With non-AEAD ciphers, the order of calls for each message - * is as follows: - * 1. mbedtls_cipher_set_iv() if the mode uses an IV/nonce. - * 2. mbedtls_cipher_reset() - * 3. mbedtls_cipher_update() one or more times - * 4. mbedtls_cipher_finish() - * . - * This sequence can be repeated to encrypt or decrypt multiple - * messages with the same key. - * - * \note With AEAD ciphers, the order of calls for each message - * is as follows: - * 1. mbedtls_cipher_set_iv() if the mode uses an IV/nonce. - * 2. mbedtls_cipher_reset() - * 3. mbedtls_cipher_update_ad() - * 4. mbedtls_cipher_update() one or more times - * 5. mbedtls_cipher_finish() - * 6. mbedtls_cipher_check_tag() (for decryption) or - * mbedtls_cipher_write_tag() (for encryption). - * . - * This sequence can be repeated to encrypt or decrypt multiple - * messages with the same key. - * - * \param ctx The generic cipher context. This must be bound to a key. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - */ -int mbedtls_cipher_reset(mbedtls_cipher_context_t *ctx); - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) -/** - * \brief This function adds additional data for AEAD ciphers. - * Currently supported with GCM and ChaCha20+Poly1305. - * - * \param ctx The generic cipher context. This must be initialized. - * \param ad The additional data to use. This must be a readable - * buffer of at least \p ad_len Bytes. - * \param ad_len The length of \p ad in Bytes. - * - * \return \c 0 on success. - * \return A specific error code on failure. - */ -int mbedtls_cipher_update_ad(mbedtls_cipher_context_t *ctx, - const unsigned char *ad, size_t ad_len); -#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ - -/** - * \brief The generic cipher update function. It encrypts or - * decrypts using the given cipher context. Writes as - * many block-sized blocks of data as possible to output. - * Any data that cannot be written immediately is either - * added to the next block, or flushed when - * mbedtls_cipher_finish() is called. - * Exception: For MBEDTLS_MODE_ECB, expects a single block - * in size. For example, 16 Bytes for AES. - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a key. - * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes. - * \param ilen The length of the input data. - * \param output The buffer for the output data. This must be able to - * hold at least `ilen + block_size`. This must not be the - * same buffer as \p input. - * \param olen The length of the output data, to be updated with the - * actual number of Bytes written. This must not be - * \c NULL. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE on an - * unsupported mode for a cipher. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, - const unsigned char *input, - size_t ilen, unsigned char *output, - size_t *olen); - -/** - * \brief The generic cipher finalization function. If data still - * needs to be flushed from an incomplete block, the data - * contained in it is padded to the size of - * the last block, and written to the \p output buffer. - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a key. - * \param output The buffer to write data to. This needs to be a writable - * buffer of at least block_size Bytes. - * \param olen The length of the data written to the \p output buffer. - * This may not be \c NULL. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption - * expecting a full block but not receiving one. - * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding - * while decrypting. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, - unsigned char *output, size_t *olen); - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) -/** - * \brief This function writes a tag for AEAD ciphers. - * Currently supported with GCM and ChaCha20+Poly1305. - * This must be called after mbedtls_cipher_finish(). - * - * \param ctx The generic cipher context. This must be initialized, - * bound to a key, and have just completed a cipher - * operation through mbedtls_cipher_finish() the tag for - * which should be written. - * \param tag The buffer to write the tag to. This must be a writable - * buffer of at least \p tag_len Bytes. - * \param tag_len The length of the tag to write. - * - * \return \c 0 on success. - * \return A specific error code on failure. - */ -int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, - unsigned char *tag, size_t tag_len); - -/** - * \brief This function checks the tag for AEAD ciphers. - * Currently supported with GCM and ChaCha20+Poly1305. - * This must be called after mbedtls_cipher_finish(). - * - * \param ctx The generic cipher context. This must be initialized. - * \param tag The buffer holding the tag. This must be a readable - * buffer of at least \p tag_len Bytes. - * \param tag_len The length of the tag to check. - * - * \return \c 0 on success. - * \return A specific error code on failure. - */ -int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, - const unsigned char *tag, size_t tag_len); -#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ - -/** - * \brief The generic all-in-one encryption/decryption function, - * for all ciphers except AEAD constructs. - * - * \param ctx The generic cipher context. This must be initialized. - * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. - * This must be a readable buffer of at least \p iv_len - * Bytes. - * \param iv_len The IV length for ciphers with variable-size IV. - * This parameter is discarded by ciphers with fixed-size - * IV. - * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * \param output The buffer for the output data. This must be able to - * hold at least `ilen + block_size`. This must not be the - * same buffer as \p input. - * \param olen The length of the output data, to be updated with the - * actual number of Bytes written. This must not be - * \c NULL. - * - * \note Some ciphers do not use IVs nor nonce. For these - * ciphers, use \p iv = NULL and \p iv_len = 0. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption - * expecting a full block but not receiving one. - * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding - * while decrypting. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen); - -#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) -/** - * \brief The authenticated encryption (AEAD/NIST_KW) function. - * - * \note For AEAD modes, the tag will be appended to the - * ciphertext, as recommended by RFC 5116. - * (NIST_KW doesn't have a separate tag.) - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a key, with an AEAD algorithm or NIST_KW. - * \param iv The nonce to use. This must be a readable buffer of - * at least \p iv_len Bytes and may be \c NULL if \p - * iv_len is \c 0. - * \param iv_len The length of the nonce. For AEAD ciphers, this must - * satisfy the constraints imposed by the cipher used. - * For NIST_KW, this must be \c 0. - * \param ad The additional data to authenticate. This must be a - * readable buffer of at least \p ad_len Bytes, and may - * be \c NULL is \p ad_len is \c 0. - * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. - * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes, and may be - * \c NULL if \p ilen is \c 0. - * \param ilen The length of the input data. - * \param output The buffer for the output data. This must be a - * writable buffer of at least \p output_len Bytes, and - * must not be \c NULL. - * \param output_len The length of the \p output buffer in Bytes. For AEAD - * ciphers, this must be at least \p ilen + \p tag_len. - * For NIST_KW, this must be at least \p ilen + 8 - * (rounded up to a multiple of 8 if KWP is used); - * \p ilen + 15 is always a safe value. - * \param olen This will be filled with the actual number of Bytes - * written to the \p output buffer. This must point to a - * writable object of type \c size_t. - * \param tag_len The desired length of the authentication tag. For AEAD - * ciphers, this must match the constraints imposed by - * the cipher used, and in particular must not be \c 0. - * For NIST_KW, this must be \c 0. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_auth_encrypt_ext(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t output_len, - size_t *olen, size_t tag_len); - -/** - * \brief The authenticated encryption (AEAD/NIST_KW) function. - * - * \note If the data is not authentic, then the output buffer - * is zeroed out to prevent the unauthentic plaintext being - * used, making this interface safer. - * - * \note For AEAD modes, the tag must be appended to the - * ciphertext, as recommended by RFC 5116. - * (NIST_KW doesn't have a separate tag.) - * - * \param ctx The generic cipher context. This must be initialized and - * bound to a key, with an AEAD algorithm or NIST_KW. - * \param iv The nonce to use. This must be a readable buffer of - * at least \p iv_len Bytes and may be \c NULL if \p - * iv_len is \c 0. - * \param iv_len The length of the nonce. For AEAD ciphers, this must - * satisfy the constraints imposed by the cipher used. - * For NIST_KW, this must be \c 0. - * \param ad The additional data to authenticate. This must be a - * readable buffer of at least \p ad_len Bytes, and may - * be \c NULL is \p ad_len is \c 0. - * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. - * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes, and may be - * \c NULL if \p ilen is \c 0. - * \param ilen The length of the input data. For AEAD ciphers this - * must be at least \p tag_len. For NIST_KW this must be - * at least \c 8. - * \param output The buffer for the output data. This must be a - * writable buffer of at least \p output_len Bytes, and - * may be \c NULL if \p output_len is \c 0. - * \param output_len The length of the \p output buffer in Bytes. For AEAD - * ciphers, this must be at least \p ilen - \p tag_len. - * For NIST_KW, this must be at least \p ilen - 8. - * \param olen This will be filled with the actual number of Bytes - * written to the \p output buffer. This must point to a - * writable object of type \c size_t. - * \param tag_len The actual length of the authentication tag. For AEAD - * ciphers, this must match the constraints imposed by - * the cipher used, and in particular must not be \c 0. - * For NIST_KW, this must be \c 0. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on - * parameter-verification failure. - * \return #MBEDTLS_ERR_CIPHER_AUTH_FAILED if data is not authentic. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t output_len, - size_t *olen, size_t tag_len); -#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CIPHER_H */ +/** + * \file cipher.h + * + * \brief This file contains an abstraction interface for use with the cipher + * primitives provided by the library. It provides a common interface to all of + * the available cipher operations. + * + * \author Adriaan de Jong + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CIPHER_H +#define MBEDTLS_CIPHER_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +#define MBEDTLS_CIPHER_MODE_AEAD +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define MBEDTLS_CIPHER_MODE_WITH_PADDING +#endif + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) || \ + defined(MBEDTLS_CHACHA20_C) +#define MBEDTLS_CIPHER_MODE_STREAM +#endif + +/** The selected feature is not available. */ +#define MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE -0x6080 +/** Bad input parameters. */ +#define MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA -0x6100 +/** Failed to allocate memory. */ +#define MBEDTLS_ERR_CIPHER_ALLOC_FAILED -0x6180 +/** Input data contains invalid padding and is rejected. */ +#define MBEDTLS_ERR_CIPHER_INVALID_PADDING -0x6200 +/** Decryption of block requires a full block. */ +#define MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED -0x6280 +/** Authentication failed (for AEAD modes). */ +#define MBEDTLS_ERR_CIPHER_AUTH_FAILED -0x6300 +/** The context is invalid. For example, because it was freed. */ +#define MBEDTLS_ERR_CIPHER_INVALID_CONTEXT -0x6380 + +#define MBEDTLS_CIPHER_VARIABLE_IV_LEN 0x01 /**< Cipher accepts IVs of variable length. */ +#define MBEDTLS_CIPHER_VARIABLE_KEY_LEN 0x02 /**< Cipher accepts keys of variable length. */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Supported cipher types. + * + * \warning DES/3DES are considered weak ciphers and their use + * constitutes a security risk. We recommend considering stronger + * ciphers instead. + */ +typedef enum { + MBEDTLS_CIPHER_ID_NONE = 0, /**< Placeholder to mark the end of cipher ID lists. */ + MBEDTLS_CIPHER_ID_NULL, /**< The identity cipher, treated as a stream cipher. */ + MBEDTLS_CIPHER_ID_AES, /**< The AES cipher. */ + MBEDTLS_CIPHER_ID_DES, /**< The DES cipher. \warning DES is considered weak. */ + MBEDTLS_CIPHER_ID_3DES, /**< The Triple DES cipher. \warning 3DES is considered weak. */ + MBEDTLS_CIPHER_ID_CAMELLIA, /**< The Camellia cipher. */ + MBEDTLS_CIPHER_ID_ARIA, /**< The Aria cipher. */ + MBEDTLS_CIPHER_ID_CHACHA20, /**< The ChaCha20 cipher. */ +} mbedtls_cipher_id_t; + +/** + * \brief Supported {cipher type, cipher mode} pairs. + * + * \warning DES/3DES are considered weak ciphers and their use + * constitutes a security risk. We recommend considering stronger + * ciphers instead. + */ +typedef enum { + MBEDTLS_CIPHER_NONE = 0, /**< Placeholder to mark the end of cipher-pair lists. */ + MBEDTLS_CIPHER_NULL, /**< The identity stream cipher. */ + MBEDTLS_CIPHER_AES_128_ECB, /**< AES cipher with 128-bit ECB mode. */ + MBEDTLS_CIPHER_AES_192_ECB, /**< AES cipher with 192-bit ECB mode. */ + MBEDTLS_CIPHER_AES_256_ECB, /**< AES cipher with 256-bit ECB mode. */ + MBEDTLS_CIPHER_AES_128_CBC, /**< AES cipher with 128-bit CBC mode. */ + MBEDTLS_CIPHER_AES_192_CBC, /**< AES cipher with 192-bit CBC mode. */ + MBEDTLS_CIPHER_AES_256_CBC, /**< AES cipher with 256-bit CBC mode. */ + MBEDTLS_CIPHER_AES_128_CFB128, /**< AES cipher with 128-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_192_CFB128, /**< AES cipher with 192-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_256_CFB128, /**< AES cipher with 256-bit CFB128 mode. */ + MBEDTLS_CIPHER_AES_128_CTR, /**< AES cipher with 128-bit CTR mode. */ + MBEDTLS_CIPHER_AES_192_CTR, /**< AES cipher with 192-bit CTR mode. */ + MBEDTLS_CIPHER_AES_256_CTR, /**< AES cipher with 256-bit CTR mode. */ + MBEDTLS_CIPHER_AES_128_GCM, /**< AES cipher with 128-bit GCM mode. */ + MBEDTLS_CIPHER_AES_192_GCM, /**< AES cipher with 192-bit GCM mode. */ + MBEDTLS_CIPHER_AES_256_GCM, /**< AES cipher with 256-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_ECB, /**< Camellia cipher with 128-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_ECB, /**< Camellia cipher with 192-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_ECB, /**< Camellia cipher with 256-bit ECB mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CBC, /**< Camellia cipher with 128-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CBC, /**< Camellia cipher with 192-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CBC, /**< Camellia cipher with 256-bit CBC mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CFB128, /**< Camellia cipher with 128-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CFB128, /**< Camellia cipher with 192-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CFB128, /**< Camellia cipher with 256-bit CFB128 mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CTR, /**< Camellia cipher with 128-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CTR, /**< Camellia cipher with 192-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CTR, /**< Camellia cipher with 256-bit CTR mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_GCM, /**< Camellia cipher with 128-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_GCM, /**< Camellia cipher with 192-bit GCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_GCM, /**< Camellia cipher with 256-bit GCM mode. */ + MBEDTLS_CIPHER_DES_ECB, /**< DES cipher with ECB mode. \warning DES is considered weak. */ + MBEDTLS_CIPHER_DES_CBC, /**< DES cipher with CBC mode. \warning DES is considered weak. */ + MBEDTLS_CIPHER_DES_EDE_ECB, /**< DES cipher with EDE ECB mode. \warning 3DES is considered weak. */ + MBEDTLS_CIPHER_DES_EDE_CBC, /**< DES cipher with EDE CBC mode. \warning 3DES is considered weak. */ + MBEDTLS_CIPHER_DES_EDE3_ECB, /**< DES cipher with EDE3 ECB mode. \warning 3DES is considered weak. */ + MBEDTLS_CIPHER_DES_EDE3_CBC, /**< DES cipher with EDE3 CBC mode. \warning 3DES is considered weak. */ + MBEDTLS_CIPHER_AES_128_CCM, /**< AES cipher with 128-bit CCM mode. */ + MBEDTLS_CIPHER_AES_192_CCM, /**< AES cipher with 192-bit CCM mode. */ + MBEDTLS_CIPHER_AES_256_CCM, /**< AES cipher with 256-bit CCM mode. */ + MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, /**< AES cipher with 128-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, /**< AES cipher with 192-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, /**< AES cipher with 256-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CCM, /**< Camellia cipher with 128-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CCM, /**< Camellia cipher with 192-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CCM, /**< Camellia cipher with 256-bit CCM mode. */ + MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, /**< Camellia cipher with 128-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, /**< Camellia cipher with 192-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, /**< Camellia cipher with 256-bit CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_ARIA_128_ECB, /**< Aria cipher with 128-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_192_ECB, /**< Aria cipher with 192-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_256_ECB, /**< Aria cipher with 256-bit key and ECB mode. */ + MBEDTLS_CIPHER_ARIA_128_CBC, /**< Aria cipher with 128-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_192_CBC, /**< Aria cipher with 192-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_256_CBC, /**< Aria cipher with 256-bit key and CBC mode. */ + MBEDTLS_CIPHER_ARIA_128_CFB128, /**< Aria cipher with 128-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_192_CFB128, /**< Aria cipher with 192-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_256_CFB128, /**< Aria cipher with 256-bit key and CFB-128 mode. */ + MBEDTLS_CIPHER_ARIA_128_CTR, /**< Aria cipher with 128-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_192_CTR, /**< Aria cipher with 192-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_256_CTR, /**< Aria cipher with 256-bit key and CTR mode. */ + MBEDTLS_CIPHER_ARIA_128_GCM, /**< Aria cipher with 128-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_192_GCM, /**< Aria cipher with 192-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_256_GCM, /**< Aria cipher with 256-bit key and GCM mode. */ + MBEDTLS_CIPHER_ARIA_128_CCM, /**< Aria cipher with 128-bit key and CCM mode. */ + MBEDTLS_CIPHER_ARIA_192_CCM, /**< Aria cipher with 192-bit key and CCM mode. */ + MBEDTLS_CIPHER_ARIA_256_CCM, /**< Aria cipher with 256-bit key and CCM mode. */ + MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, /**< Aria cipher with 128-bit key and CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, /**< Aria cipher with 192-bit key and CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, /**< Aria cipher with 256-bit key and CCM_STAR_NO_TAG mode. */ + MBEDTLS_CIPHER_AES_128_OFB, /**< AES 128-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_192_OFB, /**< AES 192-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_256_OFB, /**< AES 256-bit cipher in OFB mode. */ + MBEDTLS_CIPHER_AES_128_XTS, /**< AES 128-bit cipher in XTS block mode. */ + MBEDTLS_CIPHER_AES_256_XTS, /**< AES 256-bit cipher in XTS block mode. */ + MBEDTLS_CIPHER_CHACHA20, /**< ChaCha20 stream cipher. */ + MBEDTLS_CIPHER_CHACHA20_POLY1305, /**< ChaCha20-Poly1305 AEAD cipher. */ + MBEDTLS_CIPHER_AES_128_KW, /**< AES cipher with 128-bit NIST KW mode. */ + MBEDTLS_CIPHER_AES_192_KW, /**< AES cipher with 192-bit NIST KW mode. */ + MBEDTLS_CIPHER_AES_256_KW, /**< AES cipher with 256-bit NIST KW mode. */ + MBEDTLS_CIPHER_AES_128_KWP, /**< AES cipher with 128-bit NIST KWP mode. */ + MBEDTLS_CIPHER_AES_192_KWP, /**< AES cipher with 192-bit NIST KWP mode. */ + MBEDTLS_CIPHER_AES_256_KWP, /**< AES cipher with 256-bit NIST KWP mode. */ +} mbedtls_cipher_type_t; + +/** Supported cipher modes. */ +typedef enum { + MBEDTLS_MODE_NONE = 0, /**< None. */ + MBEDTLS_MODE_ECB, /**< The ECB cipher mode. */ + MBEDTLS_MODE_CBC, /**< The CBC cipher mode. */ + MBEDTLS_MODE_CFB, /**< The CFB cipher mode. */ + MBEDTLS_MODE_OFB, /**< The OFB cipher mode. */ + MBEDTLS_MODE_CTR, /**< The CTR cipher mode. */ + MBEDTLS_MODE_GCM, /**< The GCM cipher mode. */ + MBEDTLS_MODE_STREAM, /**< The stream cipher mode. */ + MBEDTLS_MODE_CCM, /**< The CCM cipher mode. */ + MBEDTLS_MODE_CCM_STAR_NO_TAG, /**< The CCM*-no-tag cipher mode. */ + MBEDTLS_MODE_XTS, /**< The XTS cipher mode. */ + MBEDTLS_MODE_CHACHAPOLY, /**< The ChaCha-Poly cipher mode. */ + MBEDTLS_MODE_KW, /**< The SP800-38F KW mode */ + MBEDTLS_MODE_KWP, /**< The SP800-38F KWP mode */ +} mbedtls_cipher_mode_t; + +/** Supported cipher padding types. */ +typedef enum { + MBEDTLS_PADDING_PKCS7 = 0, /**< PKCS7 padding (default). */ + MBEDTLS_PADDING_ONE_AND_ZEROS, /**< ISO/IEC 7816-4 padding. */ + MBEDTLS_PADDING_ZEROS_AND_LEN, /**< ANSI X.923 padding. */ + MBEDTLS_PADDING_ZEROS, /**< Zero padding (not reversible). */ + MBEDTLS_PADDING_NONE, /**< Never pad (full blocks only). */ +} mbedtls_cipher_padding_t; + +/** Type of operation. */ +typedef enum { + MBEDTLS_OPERATION_NONE = -1, + MBEDTLS_DECRYPT = 0, + MBEDTLS_ENCRYPT, +} mbedtls_operation_t; + +enum { + /** Undefined key length. */ + MBEDTLS_KEY_LENGTH_NONE = 0, + /** Key length, in bits (including parity), for DES keys. \warning DES is considered weak. */ + MBEDTLS_KEY_LENGTH_DES = 64, + /** Key length in bits, including parity, for DES in two-key EDE. \warning 3DES is considered weak. */ + MBEDTLS_KEY_LENGTH_DES_EDE = 128, + /** Key length in bits, including parity, for DES in three-key EDE. \warning 3DES is considered weak. */ + MBEDTLS_KEY_LENGTH_DES_EDE3 = 192, +}; + +/** Maximum length of any IV, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * This should be kept in sync with MBEDTLS_SSL_MAX_IV_LENGTH defined + * in library/ssl_misc.h. */ +#define MBEDTLS_MAX_IV_LENGTH 16 + +/** Maximum block size of any cipher, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined + * in library/ssl_misc.h. */ +#define MBEDTLS_MAX_BLOCK_LENGTH 16 + +/** Maximum key length, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * For now, only check whether XTS is enabled which uses 64 Byte keys, + * and use 32 Bytes as an upper bound for the maximum key length otherwise. + * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined + * in library/ssl_misc.h, which however deliberately ignores the case of XTS + * since the latter isn't used in SSL/TLS. */ +#if defined(MBEDTLS_CIPHER_MODE_XTS) +#define MBEDTLS_MAX_KEY_LENGTH 64 +#else +#define MBEDTLS_MAX_KEY_LENGTH 32 +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/** + * Base cipher information (opaque struct). + */ +typedef struct mbedtls_cipher_base_t mbedtls_cipher_base_t; + +/** + * CMAC context (opaque struct). + */ +typedef struct mbedtls_cmac_context_t mbedtls_cmac_context_t; + +/** + * Cipher information. Allows calling cipher functions + * in a generic way. + * + * \note The library does not support custom cipher info structures, + * only built-in structures returned by the functions + * mbedtls_cipher_info_from_string(), + * mbedtls_cipher_info_from_type(), + * mbedtls_cipher_info_from_values(), + * mbedtls_cipher_info_from_psa(). + * + * \note Some fields store a value that has been right-shifted to save + * code-size, so should not be used directly. The accessor + * functions adjust for this and return the "natural" value. + */ +typedef struct mbedtls_cipher_info_t { + /** Name of the cipher. */ + const char *MBEDTLS_PRIVATE(name); + + /** The block size, in bytes. */ + unsigned int MBEDTLS_PRIVATE(block_size) : 5; + + /** IV or nonce size, in bytes (right shifted by #MBEDTLS_IV_SIZE_SHIFT). + * For ciphers that accept variable IV sizes, + * this is the recommended size. + */ + unsigned int MBEDTLS_PRIVATE(iv_size) : 3; + + /** The cipher key length, in bits (right shifted by #MBEDTLS_KEY_BITLEN_SHIFT). + * This is the default length for variable sized ciphers. + * Includes parity bits for ciphers like DES. + */ + unsigned int MBEDTLS_PRIVATE(key_bitlen) : 4; + + /** The cipher mode (as per mbedtls_cipher_mode_t). + * For example, MBEDTLS_MODE_CBC. + */ + unsigned int MBEDTLS_PRIVATE(mode) : 4; + + /** Full cipher identifier (as per mbedtls_cipher_type_t). + * For example, MBEDTLS_CIPHER_AES_256_CBC. + * + * This could be 7 bits, but 8 bits retains byte alignment for the + * next field, which reduces code size to access that field. + */ + unsigned int MBEDTLS_PRIVATE(type) : 8; + + /** Bitflag comprised of MBEDTLS_CIPHER_VARIABLE_IV_LEN and + * MBEDTLS_CIPHER_VARIABLE_KEY_LEN indicating whether the + * cipher supports variable IV or variable key sizes, respectively. + */ + unsigned int MBEDTLS_PRIVATE(flags) : 2; + + /** Index to LUT for base cipher information and functions. */ + unsigned int MBEDTLS_PRIVATE(base_idx) : 5; + +} mbedtls_cipher_info_t; + +/* For internal use only. + * These are used to more compactly represent the fields above. */ +#define MBEDTLS_KEY_BITLEN_SHIFT 6 +#define MBEDTLS_IV_SIZE_SHIFT 2 +/** + * Generic cipher context. + */ +typedef struct mbedtls_cipher_context_t { + /** Information about the associated cipher. */ + const mbedtls_cipher_info_t *MBEDTLS_PRIVATE(cipher_info); + + /** Key length to use. */ + int MBEDTLS_PRIVATE(key_bitlen); + + /** Operation that the key of the context has been + * initialized for. + */ + mbedtls_operation_t MBEDTLS_PRIVATE(operation); + + /** Padding functions to use, if relevant for + * the specific cipher mode. + */ + void(*MBEDTLS_PRIVATE(add_padding))(unsigned char *output, size_t olen, size_t data_len); + int(*MBEDTLS_PRIVATE(get_padding))(unsigned char *input, size_t ilen, size_t *data_len); + + /** Buffer for input that has not been processed yet. */ + unsigned char MBEDTLS_PRIVATE(unprocessed_data)[MBEDTLS_MAX_BLOCK_LENGTH]; + + /** Number of Bytes that have not been processed yet. */ + size_t MBEDTLS_PRIVATE(unprocessed_len); + + /** Current IV or NONCE_COUNTER for CTR-mode, data unit (or sector) number + * for XTS-mode. */ + unsigned char MBEDTLS_PRIVATE(iv)[MBEDTLS_MAX_IV_LENGTH]; + + /** IV size in Bytes, for ciphers with variable-length IVs. */ + size_t MBEDTLS_PRIVATE(iv_size); + + /** The cipher-specific context. */ + void *MBEDTLS_PRIVATE(cipher_ctx); + + /** CMAC-specific context. */ + mbedtls_cmac_context_t *MBEDTLS_PRIVATE(cmac_ctx); + + /** Indicates whether the cipher operations should be performed + * by Mbed TLS' own crypto library or an external implementation + * of the PSA Crypto API. + * This is unset if the cipher context was established through + * mbedtls_cipher_setup(), and set if it was established through + * mbedtls_cipher_setup_psa(). + */ + unsigned char MBEDTLS_PRIVATE(psa_enabled); + +} mbedtls_cipher_context_t; + +/** + * \brief This function retrieves the list of ciphers supported + * by the generic cipher module. + * + * For any cipher identifier in the returned list, you can + * obtain the corresponding generic cipher information structure + * via mbedtls_cipher_info_from_type(), which can then be used + * to prepare a cipher context via mbedtls_cipher_setup(). + * + * + * \return A statically-allocated array of cipher identifiers + * of type cipher_type_t. The last entry is zero. + */ +const int *mbedtls_cipher_list(void); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher name. + * + * \param cipher_name Name of the cipher to search for. This must not be + * \c NULL. + * + * \return The cipher information structure associated with the + * given \p cipher_name. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string(const char *cipher_name); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher type. + * + * \param cipher_type Type of the cipher to search for. + * + * \return The cipher information structure associated with the + * given \p cipher_type. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type(const mbedtls_cipher_type_t cipher_type); + +/** + * \brief This function retrieves the cipher-information + * structure associated with the given cipher ID, + * key size and mode. + * + * \param cipher_id The ID of the cipher to search for. For example, + * #MBEDTLS_CIPHER_ID_AES. + * \param key_bitlen The length of the key in bits. + * \param mode The cipher mode. For example, #MBEDTLS_MODE_CBC. + * + * \return The cipher information structure associated with the + * given \p cipher_id. + * \return \c NULL if the associated cipher information is not found. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values(const mbedtls_cipher_id_t cipher_id, + int key_bitlen, + const mbedtls_cipher_mode_t mode); + +/** + * \brief Retrieve the identifier for a cipher info structure. + * + * \param[in] info The cipher info structure to query. + * This may be \c NULL. + * + * \return The full cipher identifier (\c MBEDTLS_CIPHER_xxx). + * \return #MBEDTLS_CIPHER_NONE if \p info is \c NULL. + */ +static inline mbedtls_cipher_type_t mbedtls_cipher_info_get_type( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return MBEDTLS_CIPHER_NONE; + } else { + return (mbedtls_cipher_type_t) info->MBEDTLS_PRIVATE(type); + } +} + +/** + * \brief Retrieve the operation mode for a cipher info structure. + * + * \param[in] info The cipher info structure to query. + * This may be \c NULL. + * + * \return The cipher mode (\c MBEDTLS_MODE_xxx). + * \return #MBEDTLS_MODE_NONE if \p info is \c NULL. + */ +static inline mbedtls_cipher_mode_t mbedtls_cipher_info_get_mode( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return MBEDTLS_MODE_NONE; + } else { + return (mbedtls_cipher_mode_t) info->MBEDTLS_PRIVATE(mode); + } +} + +/** + * \brief Retrieve the key size for a cipher info structure. + * + * \param[in] info The cipher info structure to query. + * This may be \c NULL. + * + * \return The key length in bits. + * For variable-sized ciphers, this is the default length. + * For DES, this includes the parity bits. + * \return \c 0 if \p info is \c NULL. + */ +static inline size_t mbedtls_cipher_info_get_key_bitlen( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return 0; + } else { + return info->MBEDTLS_PRIVATE(key_bitlen) << MBEDTLS_KEY_BITLEN_SHIFT; + } +} + +/** + * \brief Retrieve the human-readable name for a + * cipher info structure. + * + * \param[in] info The cipher info structure to query. + * This may be \c NULL. + * + * \return The cipher name, which is a human readable string, + * with static storage duration. + * \return \c NULL if \p info is \c NULL. + */ +static inline const char *mbedtls_cipher_info_get_name( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return NULL; + } else { + return info->MBEDTLS_PRIVATE(name); + } +} + +/** + * \brief This function returns the size of the IV or nonce + * for the cipher info structure, in bytes. + * + * \param info The cipher info structure. This may be \c NULL. + * + * \return The recommended IV size. + * \return \c 0 for ciphers not using an IV or a nonce. + * \return \c 0 if \p info is \c NULL. + */ +static inline size_t mbedtls_cipher_info_get_iv_size( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return 0; + } + + return ((size_t) info->MBEDTLS_PRIVATE(iv_size)) << MBEDTLS_IV_SIZE_SHIFT; +} + +/** + * \brief This function returns the block size of the given + * cipher info structure in bytes. + * + * \param info The cipher info structure. This may be \c NULL. + * + * \return The block size of the cipher. + * \return \c 1 if the cipher is a stream cipher. + * \return \c 0 if \p info is \c NULL. + */ +static inline size_t mbedtls_cipher_info_get_block_size( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return 0; + } + + return (size_t) (info->MBEDTLS_PRIVATE(block_size)); +} + +/** + * \brief This function returns a non-zero value if the key length for + * the given cipher is variable. + * + * \param info The cipher info structure. This may be \c NULL. + * + * \return Non-zero if the key length is variable, \c 0 otherwise. + * \return \c 0 if the given pointer is \c NULL. + */ +static inline int mbedtls_cipher_info_has_variable_key_bitlen( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return 0; + } + + return info->MBEDTLS_PRIVATE(flags) & MBEDTLS_CIPHER_VARIABLE_KEY_LEN; +} + +/** + * \brief This function returns a non-zero value if the IV size for + * the given cipher is variable. + * + * \param info The cipher info structure. This may be \c NULL. + * + * \return Non-zero if the IV size is variable, \c 0 otherwise. + * \return \c 0 if the given pointer is \c NULL. + */ +static inline int mbedtls_cipher_info_has_variable_iv_size( + const mbedtls_cipher_info_t *info) +{ + if (info == NULL) { + return 0; + } + + return info->MBEDTLS_PRIVATE(flags) & MBEDTLS_CIPHER_VARIABLE_IV_LEN; +} + +/** + * \brief This function initializes a \p ctx as NONE. + * + * \param ctx The context to be initialized. This must not be \c NULL. + */ +void mbedtls_cipher_init(mbedtls_cipher_context_t *ctx); + +/** + * \brief This function frees and clears the cipher-specific + * context of \p ctx. Freeing \p ctx itself remains the + * responsibility of the caller. + * + * \param ctx The context to be freed. If this is \c NULL, the + * function has no effect, otherwise this must point to an + * initialized context. + */ +void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx); + + +/** + * \brief This function prepares a cipher context for + * use with the given cipher primitive. + * + * \note After calling this function, you should call + * mbedtls_cipher_setkey() and, if the mode uses padding, + * mbedtls_cipher_set_padding_mode(), then for each + * message to encrypt or decrypt with this key, either: + * - mbedtls_cipher_crypt() for one-shot processing with + * non-AEAD modes; + * - mbedtls_cipher_auth_encrypt_ext() or + * mbedtls_cipher_auth_decrypt_ext() for one-shot + * processing with AEAD modes or NIST_KW; + * - for multi-part processing, see the documentation of + * mbedtls_cipher_reset(). + * + * \param ctx The context to prepare. This must be initialized by + * a call to mbedtls_cipher_init() first. + * \param cipher_info The cipher to use. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the + * cipher-specific context fails. + */ +int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, + const mbedtls_cipher_info_t *cipher_info); + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief This function initializes a cipher context for + * PSA-based use with the given cipher primitive. + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * Please use psa_aead_xxx() / psa_cipher_xxx() directly + * instead. + * + * \note See #MBEDTLS_USE_PSA_CRYPTO for information on PSA. + * + * \param ctx The context to initialize. May not be \c NULL. + * \param cipher_info The cipher to use. + * \param taglen For AEAD ciphers, the length in bytes of the + * authentication tag to use. Subsequent uses of + * mbedtls_cipher_auth_encrypt_ext() or + * mbedtls_cipher_auth_decrypt_ext() must provide + * the same tag length. + * For non-AEAD ciphers, the value must be \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_ALLOC_FAILED if allocation of the + * cipher-specific context fails. + */ +int MBEDTLS_DEPRECATED mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, + const mbedtls_cipher_info_t *cipher_info, + size_t taglen); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/** + * \brief This function returns the block size of the given cipher + * in bytes. + * + * \param ctx The context of the cipher. + * + * \return The block size of the underlying cipher. + * \return \c 1 if the cipher is a stream cipher. + * \return \c 0 if \p ctx has not been initialized. + */ +static inline unsigned int mbedtls_cipher_get_block_size( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return 0; + } + + return (unsigned int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(block_size); +} + +/** + * \brief This function returns the mode of operation for + * the cipher. For example, MBEDTLS_MODE_CBC. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The mode of operation. + * \return #MBEDTLS_MODE_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_cipher_mode_t mbedtls_cipher_get_cipher_mode( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, MBEDTLS_MODE_NONE); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return MBEDTLS_MODE_NONE; + } + + return (mbedtls_cipher_mode_t) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(mode); +} + +/** + * \brief This function returns the size of the IV or nonce + * of the cipher, in Bytes. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The recommended IV size if no IV has been set. + * \return \c 0 for ciphers not using an IV or a nonce. + * \return The actual size if an IV has been set. + */ +static inline int mbedtls_cipher_get_iv_size( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return 0; + } + + if (ctx->MBEDTLS_PRIVATE(iv_size) != 0) { + return (int) ctx->MBEDTLS_PRIVATE(iv_size); + } + + return (int) (((int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(iv_size)) << + MBEDTLS_IV_SIZE_SHIFT); +} + +/** + * \brief This function returns the type of the given cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The type of the cipher. + * \return #MBEDTLS_CIPHER_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_cipher_type_t mbedtls_cipher_get_type( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_CIPHER_NONE); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return MBEDTLS_CIPHER_NONE; + } + + return (mbedtls_cipher_type_t) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(type); +} + +/** + * \brief This function returns the name of the given cipher + * as a string. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The name of the cipher. + * \return NULL if \p ctx has not been not initialized. + */ +static inline const char *mbedtls_cipher_get_name( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET(ctx != NULL, 0); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return 0; + } + + return ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(name); +} + +/** + * \brief This function returns the key length of the cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The key length of the cipher in bits. + * \return #MBEDTLS_KEY_LENGTH_NONE if \p ctx has not been + * initialized. + */ +static inline int mbedtls_cipher_get_key_bitlen( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_KEY_LENGTH_NONE); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return MBEDTLS_KEY_LENGTH_NONE; + } + + return (int) ctx->MBEDTLS_PRIVATE(cipher_info)->MBEDTLS_PRIVATE(key_bitlen) << + MBEDTLS_KEY_BITLEN_SHIFT; +} + +/** + * \brief This function returns the operation of the given cipher. + * + * \param ctx The context of the cipher. This must be initialized. + * + * \return The type of operation: #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. + * \return #MBEDTLS_OPERATION_NONE if \p ctx has not been initialized. + */ +static inline mbedtls_operation_t mbedtls_cipher_get_operation( + const mbedtls_cipher_context_t *ctx) +{ + MBEDTLS_INTERNAL_VALIDATE_RET( + ctx != NULL, MBEDTLS_OPERATION_NONE); + if (ctx->MBEDTLS_PRIVATE(cipher_info) == NULL) { + return MBEDTLS_OPERATION_NONE; + } + + return ctx->MBEDTLS_PRIVATE(operation); +} + +/** + * \brief This function sets the key to use with the given context. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param key The key to use. This must be a readable buffer of at + * least \p key_bitlen Bits. + * \param key_bitlen The key length to use, in Bits. + * \param operation The operation that the key will be used for: + * #MBEDTLS_ENCRYPT or #MBEDTLS_DECRYPT. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, + const unsigned char *key, + int key_bitlen, + const mbedtls_operation_t operation); + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +/** + * \brief This function sets the padding mode, for cipher modes + * that use padding. + * + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param mode The padding mode. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE + * if the selected padding mode is not supported. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA if the cipher mode + * does not support padding. + */ +int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, + mbedtls_cipher_padding_t mode); +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +/** + * \brief This function sets the initialization vector (IV) + * or nonce. + * + * \note Some ciphers do not use IVs nor nonce. For these + * ciphers, this function has no effect. + * + * \note For #MBEDTLS_CIPHER_CHACHA20, the nonce length must + * be 12, and the initial counter value is 0. + * + * \note For #MBEDTLS_CIPHER_CHACHA20_POLY1305, the nonce length + * must be 12. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a cipher information structure. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. This + * must be a readable buffer of at least \p iv_len Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size IV. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + */ +int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, + size_t iv_len); + +/** + * \brief This function resets the cipher state. + * + * \note With non-AEAD ciphers, the order of calls for each message + * is as follows: + * 1. mbedtls_cipher_set_iv() if the mode uses an IV/nonce. + * 2. mbedtls_cipher_reset() + * 3. mbedtls_cipher_update() one or more times + * 4. mbedtls_cipher_finish() + * . + * This sequence can be repeated to encrypt or decrypt multiple + * messages with the same key. + * + * \note With AEAD ciphers, the order of calls for each message + * is as follows: + * 1. mbedtls_cipher_set_iv() if the mode uses an IV/nonce. + * 2. mbedtls_cipher_reset() + * 3. mbedtls_cipher_update_ad() + * 4. mbedtls_cipher_update() one or more times + * 5. mbedtls_cipher_finish() + * 6. mbedtls_cipher_check_tag() (for decryption) or + * mbedtls_cipher_write_tag() (for encryption). + * . + * This sequence can be repeated to encrypt or decrypt multiple + * messages with the same key. + * + * \param ctx The generic cipher context. This must be bound to a key. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + */ +int mbedtls_cipher_reset(mbedtls_cipher_context_t *ctx); + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +/** + * \brief This function adds additional data for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * + * \param ctx The generic cipher context. This must be initialized. + * \param ad The additional data to use. This must be a readable + * buffer of at least \p ad_len Bytes. + * \param ad_len The length of \p ad in Bytes. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_update_ad(mbedtls_cipher_context_t *ctx, + const unsigned char *ad, size_t ad_len); +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/** + * \brief The generic cipher update function. It encrypts or + * decrypts using the given cipher context. Writes as + * many block-sized blocks of data as possible to output. + * Any data that cannot be written immediately is either + * added to the next block, or flushed when + * mbedtls_cipher_finish() is called. + * Exception: For MBEDTLS_MODE_ECB, expects a single block + * in size. For example, 16 Bytes for AES. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data. + * \param output The buffer for the output data. This must be able to + * hold at least `ilen + block_size`. This must not be the + * same buffer as \p input. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE on an + * unsupported mode for a cipher. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, + const unsigned char *input, + size_t ilen, unsigned char *output, + size_t *olen); + +/** + * \brief The generic cipher finalization function. If data still + * needs to be flushed from an incomplete block, the data + * contained in it is padded to the size of + * the last block, and written to the \p output buffer. + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key. + * \param output The buffer to write data to. This needs to be a writable + * buffer of at least block_size Bytes. + * \param olen The length of the data written to the \p output buffer. + * This may not be \c NULL. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption + * expecting a full block but not receiving one. + * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding + * while decrypting. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, + unsigned char *output, size_t *olen); + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +/** + * \brief This function writes a tag for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * This must be called after mbedtls_cipher_finish(). + * + * \param ctx The generic cipher context. This must be initialized, + * bound to a key, and have just completed a cipher + * operation through mbedtls_cipher_finish() the tag for + * which should be written. + * \param tag The buffer to write the tag to. This must be a writable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to write. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, + unsigned char *tag, size_t tag_len); + +/** + * \brief This function checks the tag for AEAD ciphers. + * Currently supported with GCM and ChaCha20+Poly1305. + * This must be called after mbedtls_cipher_finish(). + * + * \param ctx The generic cipher context. This must be initialized. + * \param tag The buffer holding the tag. This must be a readable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to check. + * + * \return \c 0 on success. + * \return A specific error code on failure. + */ +int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, + const unsigned char *tag, size_t tag_len); +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/** + * \brief The generic all-in-one encryption/decryption function, + * for all ciphers except AEAD constructs. + * + * \param ctx The generic cipher context. This must be initialized. + * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. + * This must be a readable buffer of at least \p iv_len + * Bytes. + * \param iv_len The IV length for ciphers with variable-size IV. + * This parameter is discarded by ciphers with fixed-size + * IV. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The buffer for the output data. This must be able to + * hold at least `ilen + block_size`. This must not be the + * same buffer as \p input. + * \param olen The length of the output data, to be updated with the + * actual number of Bytes written. This must not be + * \c NULL. + * + * \note Some ciphers do not use IVs nor nonce. For these + * ciphers, use \p iv = NULL and \p iv_len = 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED on decryption + * expecting a full block but not receiving one. + * \return #MBEDTLS_ERR_CIPHER_INVALID_PADDING on invalid padding + * while decrypting. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen); + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) +/** + * \brief The authenticated encryption (AEAD/NIST_KW) function. + * + * \note For AEAD modes, the tag will be appended to the + * ciphertext, as recommended by RFC 5116. + * (NIST_KW doesn't have a separate tag.) + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key, with an AEAD algorithm or NIST_KW. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and may be \c NULL if \p + * iv_len is \c 0. + * \param iv_len The length of the nonce. For AEAD ciphers, this must + * satisfy the constraints imposed by the cipher used. + * For NIST_KW, this must be \c 0. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. + * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. + * \param ilen The length of the input data. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p output_len Bytes, and + * must not be \c NULL. + * \param output_len The length of the \p output buffer in Bytes. For AEAD + * ciphers, this must be at least \p ilen + \p tag_len. + * For NIST_KW, this must be at least \p ilen + 8 + * (rounded up to a multiple of 8 if KWP is used); + * \p ilen + 15 is always a safe value. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. + * \param tag_len The desired length of the authentication tag. For AEAD + * ciphers, this must match the constraints imposed by + * the cipher used, and in particular must not be \c 0. + * For NIST_KW, this must be \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_encrypt_ext(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len); + +/** + * \brief The authenticated encryption (AEAD/NIST_KW) function. + * + * \note If the data is not authentic, then the output buffer + * is zeroed out to prevent the unauthentic plaintext being + * used, making this interface safer. + * + * \note For AEAD modes, the tag must be appended to the + * ciphertext, as recommended by RFC 5116. + * (NIST_KW doesn't have a separate tag.) + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key, with an AEAD algorithm or NIST_KW. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and may be \c NULL if \p + * iv_len is \c 0. + * \param iv_len The length of the nonce. For AEAD ciphers, this must + * satisfy the constraints imposed by the cipher used. + * For NIST_KW, this must be \c 0. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. + * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. + * \param ilen The length of the input data. For AEAD ciphers this + * must be at least \p tag_len. For NIST_KW this must be + * at least \c 8. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p output_len Bytes, and + * may be \c NULL if \p output_len is \c 0. + * \param output_len The length of the \p output buffer in Bytes. For AEAD + * ciphers, this must be at least \p ilen - \p tag_len. + * For NIST_KW, this must be at least \p ilen - 8. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. + * \param tag_len The actual length of the authentication tag. For AEAD + * ciphers, this must match the constraints imposed by + * the cipher used, and in particular must not be \c 0. + * For NIST_KW, this must be \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_AUTH_FAILED if data is not authentic. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len); +#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CIPHER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cmac.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cmac.h index b2aca5d..9b5d230 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cmac.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/cmac.h @@ -1,258 +1,258 @@ -/** - * \file cmac.h - * - * \brief This file contains CMAC definitions and functions. - * - * The Cipher-based Message Authentication Code (CMAC) Mode for - * Authentication is defined in RFC-4493: The AES-CMAC Algorithm. - * It is supported with AES and DES. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CMAC_H -#define MBEDTLS_CMAC_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/cipher.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define MBEDTLS_AES_BLOCK_SIZE 16 -#define MBEDTLS_DES3_BLOCK_SIZE 8 - -/* We don't support Camellia or ARIA in this module */ -#if defined(MBEDTLS_AES_C) -#define MBEDTLS_CMAC_MAX_BLOCK_SIZE 16 /**< The longest block used by CMAC is that of AES. */ -#else -#define MBEDTLS_CMAC_MAX_BLOCK_SIZE 8 /**< The longest block used by CMAC is that of 3DES. */ -#endif - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** The longest block supported by the cipher module. - * - * \deprecated - * For the maximum block size of a cipher supported by the CMAC module, - * use #MBEDTLS_CMAC_MAX_BLOCK_SIZE. - * For the maximum block size of a cipher supported by the cipher module, - * use #MBEDTLS_MAX_BLOCK_LENGTH. - */ -/* Before Mbed TLS 3.5, this was the maximum block size supported by the CMAC - * module, so it didn't take Camellia or ARIA into account. Since the name - * of the macro doesn't even convey "CMAC", this was misleading. Now the size - * is sufficient for any cipher, but the name is defined in cmac.h for - * backward compatibility. */ -#define MBEDTLS_CIPHER_BLKSIZE_MAX MBEDTLS_MAX_BLOCK_LENGTH -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -#if !defined(MBEDTLS_CMAC_ALT) - -/** - * The CMAC context structure. - */ -struct mbedtls_cmac_context_t { - /** The internal state of the CMAC algorithm. */ - unsigned char MBEDTLS_PRIVATE(state)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; - - /** Unprocessed data - either data that was not block aligned and is still - * pending processing, or the final block. */ - unsigned char MBEDTLS_PRIVATE(unprocessed_block)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; - - /** The length of data pending processing. */ - size_t MBEDTLS_PRIVATE(unprocessed_len); -}; - -#else /* !MBEDTLS_CMAC_ALT */ -#include "cmac_alt.h" -#endif /* !MBEDTLS_CMAC_ALT */ - -/** - * \brief This function starts a new CMAC computation - * by setting the CMAC key, and preparing to authenticate - * the input data. - * It must be called with an initialized cipher context. - * - * Once this function has completed, data can be supplied - * to the CMAC computation by calling - * mbedtls_cipher_cmac_update(). - * - * To start a CMAC computation using the same key as a previous - * CMAC computation, use mbedtls_cipher_cmac_finish(). - * - * \note When the CMAC implementation is supplied by an alternate - * implementation (through #MBEDTLS_CMAC_ALT), some ciphers - * may not be supported by that implementation, and thus - * return an error. Alternate implementations must support - * AES-128 and AES-256, and may support AES-192 and 3DES. - * - * \param ctx The cipher context used for the CMAC operation, initialized - * as one of the following types: MBEDTLS_CIPHER_AES_128_ECB, - * MBEDTLS_CIPHER_AES_192_ECB, MBEDTLS_CIPHER_AES_256_ECB, - * or MBEDTLS_CIPHER_DES_EDE3_ECB. - * \param key The CMAC key. - * \param keybits The length of the CMAC key in bits. - * Must be supported by the cipher. - * - * \return \c 0 on success. - * \return A cipher-specific error code on failure. - */ -int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, - const unsigned char *key, size_t keybits); - -/** - * \brief This function feeds an input buffer into an ongoing CMAC - * computation. - * - * The CMAC computation must have previously been started - * by calling mbedtls_cipher_cmac_starts() or - * mbedtls_cipher_cmac_reset(). - * - * Call this function as many times as needed to input the - * data to be authenticated. - * Once all of the required data has been input, - * call mbedtls_cipher_cmac_finish() to obtain the result - * of the CMAC operation. - * - * \param ctx The cipher context used for the CMAC operation. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA - * if parameter verification fails. - */ -int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, - const unsigned char *input, size_t ilen); - -/** - * \brief This function finishes an ongoing CMAC operation, and - * writes the result to the output buffer. - * - * It should be followed either by - * mbedtls_cipher_cmac_reset(), which starts another CMAC - * operation with the same key, or mbedtls_cipher_free(), - * which clears the cipher context. - * - * \param ctx The cipher context used for the CMAC operation. - * \param output The output buffer for the CMAC checksum result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA - * if parameter verification fails. - */ -int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, - unsigned char *output); - -/** - * \brief This function starts a new CMAC operation with the same - * key as the previous one. - * - * It should be called after finishing the previous CMAC - * operation with mbedtls_cipher_cmac_finish(). - * After calling this function, - * call mbedtls_cipher_cmac_update() to supply the new - * CMAC operation with data. - * - * \param ctx The cipher context used for the CMAC operation. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA - * if parameter verification fails. - */ -int mbedtls_cipher_cmac_reset(mbedtls_cipher_context_t *ctx); - -/** - * \brief This function calculates the full generic CMAC - * on the input buffer with the provided key. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The CMAC result is calculated as - * output = generic CMAC(cmac key, input buffer). - * - * \note When the CMAC implementation is supplied by an alternate - * implementation (through #MBEDTLS_CMAC_ALT), some ciphers - * may not be supported by that implementation, and thus - * return an error. Alternate implementations must support - * AES-128 and AES-256, and may support AES-192 and 3DES. - * - * \param cipher_info The cipher information. - * \param key The CMAC key. - * \param keylen The length of the CMAC key in bits. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * \param output The buffer for the generic CMAC result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA - * if parameter verification fails. - */ -int mbedtls_cipher_cmac(const mbedtls_cipher_info_t *cipher_info, - const unsigned char *key, size_t keylen, - const unsigned char *input, size_t ilen, - unsigned char *output); - -#if defined(MBEDTLS_AES_C) -/** - * \brief This function implements the AES-CMAC-PRF-128 pseudorandom - * function, as defined in - * RFC-4615: The Advanced Encryption Standard-Cipher-based - * Message Authentication Code-Pseudo-Random Function-128 - * (AES-CMAC-PRF-128) Algorithm for the Internet Key - * Exchange Protocol (IKE). - * - * \param key The key to use. - * \param key_len The key length in Bytes. - * \param input The buffer holding the input data. - * \param in_len The length of the input data in Bytes. - * \param output The buffer holding the generated 16 Bytes of - * pseudorandom output. - * - * \return \c 0 on success. - */ -int mbedtls_aes_cmac_prf_128(const unsigned char *key, size_t key_len, - const unsigned char *input, size_t in_len, - unsigned char output[16]); -#endif /* MBEDTLS_AES_C */ - -#if defined(MBEDTLS_SELF_TEST) && (defined(MBEDTLS_AES_C) || defined(MBEDTLS_DES_C)) -/** - * \brief The CMAC checkup routine. - * - * \note In case the CMAC routines are provided by an alternative - * implementation (i.e. #MBEDTLS_CMAC_ALT is defined), the - * checkup routine will succeed even if the implementation does - * not support the less widely used AES-192 or 3DES primitives. - * The self-test requires at least AES-128 and AES-256 to be - * supported by the underlying implementation. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_cmac_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST && ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CMAC_H */ +/** + * \file cmac.h + * + * \brief This file contains CMAC definitions and functions. + * + * The Cipher-based Message Authentication Code (CMAC) Mode for + * Authentication is defined in RFC-4493: The AES-CMAC Algorithm. + * It is supported with AES and DES. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CMAC_H +#define MBEDTLS_CMAC_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/cipher.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MBEDTLS_AES_BLOCK_SIZE 16 +#define MBEDTLS_DES3_BLOCK_SIZE 8 + +/* We don't support Camellia or ARIA in this module */ +#if defined(MBEDTLS_AES_C) +#define MBEDTLS_CMAC_MAX_BLOCK_SIZE 16 /**< The longest block used by CMAC is that of AES. */ +#else +#define MBEDTLS_CMAC_MAX_BLOCK_SIZE 8 /**< The longest block used by CMAC is that of 3DES. */ +#endif + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** The longest block supported by the cipher module. + * + * \deprecated + * For the maximum block size of a cipher supported by the CMAC module, + * use #MBEDTLS_CMAC_MAX_BLOCK_SIZE. + * For the maximum block size of a cipher supported by the cipher module, + * use #MBEDTLS_MAX_BLOCK_LENGTH. + */ +/* Before Mbed TLS 3.5, this was the maximum block size supported by the CMAC + * module, so it didn't take Camellia or ARIA into account. Since the name + * of the macro doesn't even convey "CMAC", this was misleading. Now the size + * is sufficient for any cipher, but the name is defined in cmac.h for + * backward compatibility. */ +#define MBEDTLS_CIPHER_BLKSIZE_MAX MBEDTLS_MAX_BLOCK_LENGTH +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +#if !defined(MBEDTLS_CMAC_ALT) + +/** + * The CMAC context structure. + */ +struct mbedtls_cmac_context_t { + /** The internal state of the CMAC algorithm. */ + unsigned char MBEDTLS_PRIVATE(state)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; + + /** Unprocessed data - either data that was not block aligned and is still + * pending processing, or the final block. */ + unsigned char MBEDTLS_PRIVATE(unprocessed_block)[MBEDTLS_CMAC_MAX_BLOCK_SIZE]; + + /** The length of data pending processing. */ + size_t MBEDTLS_PRIVATE(unprocessed_len); +}; + +#else /* !MBEDTLS_CMAC_ALT */ +#include "cmac_alt.h" +#endif /* !MBEDTLS_CMAC_ALT */ + +/** + * \brief This function starts a new CMAC computation + * by setting the CMAC key, and preparing to authenticate + * the input data. + * It must be called with an initialized cipher context. + * + * Once this function has completed, data can be supplied + * to the CMAC computation by calling + * mbedtls_cipher_cmac_update(). + * + * To start a CMAC computation using the same key as a previous + * CMAC computation, use mbedtls_cipher_cmac_finish(). + * + * \note When the CMAC implementation is supplied by an alternate + * implementation (through #MBEDTLS_CMAC_ALT), some ciphers + * may not be supported by that implementation, and thus + * return an error. Alternate implementations must support + * AES-128 and AES-256, and may support AES-192 and 3DES. + * + * \param ctx The cipher context used for the CMAC operation, initialized + * as one of the following types: MBEDTLS_CIPHER_AES_128_ECB, + * MBEDTLS_CIPHER_AES_192_ECB, MBEDTLS_CIPHER_AES_256_ECB, + * or MBEDTLS_CIPHER_DES_EDE3_ECB. + * \param key The CMAC key. + * \param keybits The length of the CMAC key in bits. + * Must be supported by the cipher. + * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_cmac_starts(mbedtls_cipher_context_t *ctx, + const unsigned char *key, size_t keybits); + +/** + * \brief This function feeds an input buffer into an ongoing CMAC + * computation. + * + * The CMAC computation must have previously been started + * by calling mbedtls_cipher_cmac_starts() or + * mbedtls_cipher_cmac_reset(). + * + * Call this function as many times as needed to input the + * data to be authenticated. + * Once all of the required data has been input, + * call mbedtls_cipher_cmac_finish() to obtain the result + * of the CMAC operation. + * + * \param ctx The cipher context used for the CMAC operation. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA + * if parameter verification fails. + */ +int mbedtls_cipher_cmac_update(mbedtls_cipher_context_t *ctx, + const unsigned char *input, size_t ilen); + +/** + * \brief This function finishes an ongoing CMAC operation, and + * writes the result to the output buffer. + * + * It should be followed either by + * mbedtls_cipher_cmac_reset(), which starts another CMAC + * operation with the same key, or mbedtls_cipher_free(), + * which clears the cipher context. + * + * \param ctx The cipher context used for the CMAC operation. + * \param output The output buffer for the CMAC checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA + * if parameter verification fails. + */ +int mbedtls_cipher_cmac_finish(mbedtls_cipher_context_t *ctx, + unsigned char *output); + +/** + * \brief This function starts a new CMAC operation with the same + * key as the previous one. + * + * It should be called after finishing the previous CMAC + * operation with mbedtls_cipher_cmac_finish(). + * After calling this function, + * call mbedtls_cipher_cmac_update() to supply the new + * CMAC operation with data. + * + * \param ctx The cipher context used for the CMAC operation. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA + * if parameter verification fails. + */ +int mbedtls_cipher_cmac_reset(mbedtls_cipher_context_t *ctx); + +/** + * \brief This function calculates the full generic CMAC + * on the input buffer with the provided key. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The CMAC result is calculated as + * output = generic CMAC(cmac key, input buffer). + * + * \note When the CMAC implementation is supplied by an alternate + * implementation (through #MBEDTLS_CMAC_ALT), some ciphers + * may not be supported by that implementation, and thus + * return an error. Alternate implementations must support + * AES-128 and AES-256, and may support AES-192 and 3DES. + * + * \param cipher_info The cipher information. + * \param key The CMAC key. + * \param keylen The length of the CMAC key in bits. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * \param output The buffer for the generic CMAC result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA + * if parameter verification fails. + */ +int mbedtls_cipher_cmac(const mbedtls_cipher_info_t *cipher_info, + const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output); + +#if defined(MBEDTLS_AES_C) +/** + * \brief This function implements the AES-CMAC-PRF-128 pseudorandom + * function, as defined in + * RFC-4615: The Advanced Encryption Standard-Cipher-based + * Message Authentication Code-Pseudo-Random Function-128 + * (AES-CMAC-PRF-128) Algorithm for the Internet Key + * Exchange Protocol (IKE). + * + * \param key The key to use. + * \param key_len The key length in Bytes. + * \param input The buffer holding the input data. + * \param in_len The length of the input data in Bytes. + * \param output The buffer holding the generated 16 Bytes of + * pseudorandom output. + * + * \return \c 0 on success. + */ +int mbedtls_aes_cmac_prf_128(const unsigned char *key, size_t key_len, + const unsigned char *input, size_t in_len, + unsigned char output[16]); +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_SELF_TEST) && (defined(MBEDTLS_AES_C) || defined(MBEDTLS_DES_C)) +/** + * \brief The CMAC checkup routine. + * + * \note In case the CMAC routines are provided by an alternative + * implementation (i.e. #MBEDTLS_CMAC_ALT is defined), the + * checkup routine will succeed even if the implementation does + * not support the less widely used AES-192 or 3DES primitives. + * The self-test requires at least AES-128 and AES-256 to be + * supported by the underlying implementation. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_cmac_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST && ( MBEDTLS_AES_C || MBEDTLS_DES_C ) */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CMAC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/compat-2.x.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/compat-2.x.h index cdf81dc..ccd9dfd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/compat-2.x.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/compat-2.x.h @@ -1,58 +1,58 @@ -/** - * \file compat-2.x.h - * - * \brief Compatibility definitions - * - * \deprecated Use the new names directly instead - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(MBEDTLS_DEPRECATED_WARNING) -#warning "Including compat-2.x.h is deprecated" -#endif - -#ifndef MBEDTLS_COMPAT2X_H -#define MBEDTLS_COMPAT2X_H - -/* - * Macros for renamed functions - */ -#define mbedtls_ctr_drbg_update_ret mbedtls_ctr_drbg_update -#define mbedtls_hmac_drbg_update_ret mbedtls_hmac_drbg_update -#define mbedtls_md5_starts_ret mbedtls_md5_starts -#define mbedtls_md5_update_ret mbedtls_md5_update -#define mbedtls_md5_finish_ret mbedtls_md5_finish -#define mbedtls_md5_ret mbedtls_md5 -#define mbedtls_ripemd160_starts_ret mbedtls_ripemd160_starts -#define mbedtls_ripemd160_update_ret mbedtls_ripemd160_update -#define mbedtls_ripemd160_finish_ret mbedtls_ripemd160_finish -#define mbedtls_ripemd160_ret mbedtls_ripemd160 -#define mbedtls_sha1_starts_ret mbedtls_sha1_starts -#define mbedtls_sha1_update_ret mbedtls_sha1_update -#define mbedtls_sha1_finish_ret mbedtls_sha1_finish -#define mbedtls_sha1_ret mbedtls_sha1 -#define mbedtls_sha256_starts_ret mbedtls_sha256_starts -#define mbedtls_sha256_update_ret mbedtls_sha256_update -#define mbedtls_sha256_finish_ret mbedtls_sha256_finish -#define mbedtls_sha256_ret mbedtls_sha256 -#define mbedtls_sha512_starts_ret mbedtls_sha512_starts -#define mbedtls_sha512_update_ret mbedtls_sha512_update -#define mbedtls_sha512_finish_ret mbedtls_sha512_finish -#define mbedtls_sha512_ret mbedtls_sha512 - -#endif /* MBEDTLS_COMPAT2X_H */ +/** + * \file compat-2.x.h + * + * \brief Compatibility definitions + * + * \deprecated Use the new names directly instead + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(MBEDTLS_DEPRECATED_WARNING) +#warning "Including compat-2.x.h is deprecated" +#endif + +#ifndef MBEDTLS_COMPAT2X_H +#define MBEDTLS_COMPAT2X_H + +/* + * Macros for renamed functions + */ +#define mbedtls_ctr_drbg_update_ret mbedtls_ctr_drbg_update +#define mbedtls_hmac_drbg_update_ret mbedtls_hmac_drbg_update +#define mbedtls_md5_starts_ret mbedtls_md5_starts +#define mbedtls_md5_update_ret mbedtls_md5_update +#define mbedtls_md5_finish_ret mbedtls_md5_finish +#define mbedtls_md5_ret mbedtls_md5 +#define mbedtls_ripemd160_starts_ret mbedtls_ripemd160_starts +#define mbedtls_ripemd160_update_ret mbedtls_ripemd160_update +#define mbedtls_ripemd160_finish_ret mbedtls_ripemd160_finish +#define mbedtls_ripemd160_ret mbedtls_ripemd160 +#define mbedtls_sha1_starts_ret mbedtls_sha1_starts +#define mbedtls_sha1_update_ret mbedtls_sha1_update +#define mbedtls_sha1_finish_ret mbedtls_sha1_finish +#define mbedtls_sha1_ret mbedtls_sha1 +#define mbedtls_sha256_starts_ret mbedtls_sha256_starts +#define mbedtls_sha256_update_ret mbedtls_sha256_update +#define mbedtls_sha256_finish_ret mbedtls_sha256_finish +#define mbedtls_sha256_ret mbedtls_sha256 +#define mbedtls_sha512_starts_ret mbedtls_sha512_starts +#define mbedtls_sha512_update_ret mbedtls_sha512_update +#define mbedtls_sha512_finish_ret mbedtls_sha512_finish +#define mbedtls_sha512_ret mbedtls_sha512 + +#endif /* MBEDTLS_COMPAT2X_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_crypto.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_crypto.h index 6ec59f1..dd00613 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_crypto.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_crypto.h @@ -1,195 +1,195 @@ -/** - * \file mbedtls/config_adjust_legacy_crypto.h - * \brief Adjust legacy configuration configuration - * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx - * configurations need to be explicitly enabled by the user: enabling - * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a - * compilation error. However, we do automatically enable certain options - * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option - * used to identify parts of a module that are used by other module, and we - * don't want to make the symbol MBEDTLS_xxx_B part of the public API. - * Another case is if A didn't depend on B in earlier versions, and we - * want to use B in A but we need to preserve backward compatibility with - * configurations that explicitly activate MBEDTLS_xxx_A but not - * MBEDTLS_xxx_B. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H -#define MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H - -/* Auto-enable MBEDTLS_MD_LIGHT based on MBEDTLS_MD_C. - * This allows checking for MD_LIGHT rather than MD_LIGHT || MD_C. - */ -#if defined(MBEDTLS_MD_C) -#define MBEDTLS_MD_LIGHT -#endif - -/* Auto-enable MBEDTLS_MD_LIGHT if needed by a module that didn't require it - * in a previous release, to ensure backwards compatibility. - */ -#if defined(MBEDTLS_ECJPAKE_C) || \ - defined(MBEDTLS_PEM_PARSE_C) || \ - defined(MBEDTLS_ENTROPY_C) || \ - defined(MBEDTLS_PK_C) || \ - defined(MBEDTLS_PKCS12_C) || \ - defined(MBEDTLS_RSA_C) || \ - defined(MBEDTLS_SSL_TLS_C) || \ - defined(MBEDTLS_X509_USE_C) || \ - defined(MBEDTLS_X509_CREATE_C) -#define MBEDTLS_MD_LIGHT -#endif - -/* MBEDTLS_ECP_LIGHT is auto-enabled by the following symbols: - * - MBEDTLS_ECP_C because now it consists of MBEDTLS_ECP_LIGHT plus functions - * for curve arithmetic. As a consequence if MBEDTLS_ECP_C is required for - * some reason, then MBEDTLS_ECP_LIGHT should be enabled as well. - * - MBEDTLS_PK_PARSE_EC_EXTENDED and MBEDTLS_PK_PARSE_EC_COMPRESSED because - * these features are not supported in PSA so the only way to have them is - * to enable the built-in solution. - * Both of them are temporary dependencies: - * - PK_PARSE_EC_EXTENDED will be removed after #7779 and #7789 - * - support for compressed points should also be added to PSA, but in this - * case there is no associated issue to track it yet. - * - PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE because Weierstrass key derivation - * still depends on ECP_LIGHT. - * - PK_C + USE_PSA + PSA_WANT_ALG_ECDSA is a temporary dependency which will - * be fixed by #7453. - */ -#if defined(MBEDTLS_ECP_C) || \ - defined(MBEDTLS_PK_PARSE_EC_EXTENDED) || \ - defined(MBEDTLS_PK_PARSE_EC_COMPRESSED) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define MBEDTLS_ECP_LIGHT -#endif - -/* MBEDTLS_PK_PARSE_EC_COMPRESSED is introduced in MbedTLS version 3.5, while - * in previous version compressed points were automatically supported as long - * as PK_PARSE_C and ECP_C were enabled. As a consequence, for backward - * compatibility, we auto-enable PK_PARSE_EC_COMPRESSED when these conditions - * are met. */ -#if defined(MBEDTLS_PK_PARSE_C) && defined(MBEDTLS_ECP_C) -#define MBEDTLS_PK_PARSE_EC_COMPRESSED -#endif - -/* Helper symbol to state that there is support for ECDH, either through - * library implementation (ECDH_C) or through PSA. */ -#if (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_ALG_ECDH)) || \ - (!defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_ECDH_C)) -#define MBEDTLS_CAN_ECDH -#endif - -/* PK module can achieve ECDSA functionalities by means of either software - * implementations (ECDSA_C) or through a PSA driver. The following defines - * are meant to list these capabilities in a general way which abstracts how - * they are implemented under the hood. */ -#if !defined(MBEDTLS_USE_PSA_CRYPTO) -#if defined(MBEDTLS_ECDSA_C) -#define MBEDTLS_PK_CAN_ECDSA_SIGN -#define MBEDTLS_PK_CAN_ECDSA_VERIFY -#endif /* MBEDTLS_ECDSA_C */ -#else /* MBEDTLS_USE_PSA_CRYPTO */ -#if defined(PSA_WANT_ALG_ECDSA) -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define MBEDTLS_PK_CAN_ECDSA_SIGN -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC */ -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -#define MBEDTLS_PK_CAN_ECDSA_VERIFY -#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ -#endif /* PSA_WANT_ALG_ECDSA */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_PK_CAN_ECDSA_VERIFY) || defined(MBEDTLS_PK_CAN_ECDSA_SIGN) -#define MBEDTLS_PK_CAN_ECDSA_SOME -#endif - -/* If MBEDTLS_PSA_CRYPTO_C is defined, make sure MBEDTLS_PSA_CRYPTO_CLIENT - * is defined as well to include all PSA code. - */ -#if defined(MBEDTLS_PSA_CRYPTO_C) -#define MBEDTLS_PSA_CRYPTO_CLIENT -#endif /* MBEDTLS_PSA_CRYPTO_C */ - -/* The PK wrappers need pk_write functions to format RSA key objects - * when they are dispatching to the PSA API. This happens under USE_PSA_CRYPTO, - * and also even without USE_PSA_CRYPTO for mbedtls_pk_sign_ext(). */ -#if defined(MBEDTLS_PSA_CRYPTO_C) && defined(MBEDTLS_RSA_C) -#define MBEDTLS_PK_C -#define MBEDTLS_PK_WRITE_C -#define MBEDTLS_PK_PARSE_C -#endif - -/* Helpers to state that each key is supported either on the builtin or PSA side. */ -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_521) -#define MBEDTLS_ECP_HAVE_SECP521R1 -#endif -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#define MBEDTLS_ECP_HAVE_BP512R1 -#endif -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) || defined(PSA_WANT_ECC_MONTGOMERY_448) -#define MBEDTLS_ECP_HAVE_CURVE448 -#endif -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#define MBEDTLS_ECP_HAVE_BP384R1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_384) -#define MBEDTLS_ECP_HAVE_SECP384R1 -#endif -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#define MBEDTLS_ECP_HAVE_BP256R1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_256) -#define MBEDTLS_ECP_HAVE_SECP256K1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_256) -#define MBEDTLS_ECP_HAVE_SECP256R1 -#endif -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || defined(PSA_WANT_ECC_MONTGOMERY_255) -#define MBEDTLS_ECP_HAVE_CURVE25519 -#endif -#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_224) -#define MBEDTLS_ECP_HAVE_SECP224K1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_224) -#define MBEDTLS_ECP_HAVE_SECP224R1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_192) -#define MBEDTLS_ECP_HAVE_SECP192K1 -#endif -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_192) -#define MBEDTLS_ECP_HAVE_SECP192R1 -#endif - -/* Helper symbol to state that the PK module has support for EC keys. This - * can either be provided through the legacy ECP solution or through the - * PSA friendly MBEDTLS_PK_USE_PSA_EC_DATA (see pk.h for its description). */ -#if defined(MBEDTLS_ECP_C) || \ - (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) -#define MBEDTLS_PK_HAVE_ECC_KEYS -#endif /* MBEDTLS_PK_USE_PSA_EC_DATA || MBEDTLS_ECP_C */ - -/* Historically pkparse did not check the CBC padding when decrypting - * a key. This was a bug, which is now fixed. As a consequence, pkparse - * now needs PKCS7 padding support, but existing configurations might not - * enable it, so we enable it here. */ -#if defined(MBEDTLS_PK_PARSE_C) && defined(MBEDTLS_PKCS5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) -#define MBEDTLS_CIPHER_PADDING_PKCS7 -#endif - -#endif /* MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H */ +/** + * \file mbedtls/config_adjust_legacy_crypto.h + * \brief Adjust legacy configuration configuration + * + * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * configurations need to be explicitly enabled by the user: enabling + * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a + * compilation error. However, we do automatically enable certain options + * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option + * used to identify parts of a module that are used by other module, and we + * don't want to make the symbol MBEDTLS_xxx_B part of the public API. + * Another case is if A didn't depend on B in earlier versions, and we + * want to use B in A but we need to preserve backward compatibility with + * configurations that explicitly activate MBEDTLS_xxx_A but not + * MBEDTLS_xxx_B. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H +#define MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H + +/* Auto-enable MBEDTLS_MD_LIGHT based on MBEDTLS_MD_C. + * This allows checking for MD_LIGHT rather than MD_LIGHT || MD_C. + */ +#if defined(MBEDTLS_MD_C) +#define MBEDTLS_MD_LIGHT +#endif + +/* Auto-enable MBEDTLS_MD_LIGHT if needed by a module that didn't require it + * in a previous release, to ensure backwards compatibility. + */ +#if defined(MBEDTLS_ECJPAKE_C) || \ + defined(MBEDTLS_PEM_PARSE_C) || \ + defined(MBEDTLS_ENTROPY_C) || \ + defined(MBEDTLS_PK_C) || \ + defined(MBEDTLS_PKCS12_C) || \ + defined(MBEDTLS_RSA_C) || \ + defined(MBEDTLS_SSL_TLS_C) || \ + defined(MBEDTLS_X509_USE_C) || \ + defined(MBEDTLS_X509_CREATE_C) +#define MBEDTLS_MD_LIGHT +#endif + +/* MBEDTLS_ECP_LIGHT is auto-enabled by the following symbols: + * - MBEDTLS_ECP_C because now it consists of MBEDTLS_ECP_LIGHT plus functions + * for curve arithmetic. As a consequence if MBEDTLS_ECP_C is required for + * some reason, then MBEDTLS_ECP_LIGHT should be enabled as well. + * - MBEDTLS_PK_PARSE_EC_EXTENDED and MBEDTLS_PK_PARSE_EC_COMPRESSED because + * these features are not supported in PSA so the only way to have them is + * to enable the built-in solution. + * Both of them are temporary dependencies: + * - PK_PARSE_EC_EXTENDED will be removed after #7779 and #7789 + * - support for compressed points should also be added to PSA, but in this + * case there is no associated issue to track it yet. + * - PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE because Weierstrass key derivation + * still depends on ECP_LIGHT. + * - PK_C + USE_PSA + PSA_WANT_ALG_ECDSA is a temporary dependency which will + * be fixed by #7453. + */ +#if defined(MBEDTLS_ECP_C) || \ + defined(MBEDTLS_PK_PARSE_EC_EXTENDED) || \ + defined(MBEDTLS_PK_PARSE_EC_COMPRESSED) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#define MBEDTLS_ECP_LIGHT +#endif + +/* MBEDTLS_PK_PARSE_EC_COMPRESSED is introduced in MbedTLS version 3.5, while + * in previous version compressed points were automatically supported as long + * as PK_PARSE_C and ECP_C were enabled. As a consequence, for backward + * compatibility, we auto-enable PK_PARSE_EC_COMPRESSED when these conditions + * are met. */ +#if defined(MBEDTLS_PK_PARSE_C) && defined(MBEDTLS_ECP_C) +#define MBEDTLS_PK_PARSE_EC_COMPRESSED +#endif + +/* Helper symbol to state that there is support for ECDH, either through + * library implementation (ECDH_C) or through PSA. */ +#if (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_ALG_ECDH)) || \ + (!defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_ECDH_C)) +#define MBEDTLS_CAN_ECDH +#endif + +/* PK module can achieve ECDSA functionalities by means of either software + * implementations (ECDSA_C) or through a PSA driver. The following defines + * are meant to list these capabilities in a general way which abstracts how + * they are implemented under the hood. */ +#if !defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_ECDSA_C) +#define MBEDTLS_PK_CAN_ECDSA_SIGN +#define MBEDTLS_PK_CAN_ECDSA_VERIFY +#endif /* MBEDTLS_ECDSA_C */ +#else /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(PSA_WANT_ALG_ECDSA) +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define MBEDTLS_PK_CAN_ECDSA_SIGN +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC */ +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#define MBEDTLS_PK_CAN_ECDSA_VERIFY +#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ +#endif /* PSA_WANT_ALG_ECDSA */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_PK_CAN_ECDSA_VERIFY) || defined(MBEDTLS_PK_CAN_ECDSA_SIGN) +#define MBEDTLS_PK_CAN_ECDSA_SOME +#endif + +/* If MBEDTLS_PSA_CRYPTO_C is defined, make sure MBEDTLS_PSA_CRYPTO_CLIENT + * is defined as well to include all PSA code. + */ +#if defined(MBEDTLS_PSA_CRYPTO_C) +#define MBEDTLS_PSA_CRYPTO_CLIENT +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +/* The PK wrappers need pk_write functions to format RSA key objects + * when they are dispatching to the PSA API. This happens under USE_PSA_CRYPTO, + * and also even without USE_PSA_CRYPTO for mbedtls_pk_sign_ext(). */ +#if defined(MBEDTLS_PSA_CRYPTO_C) && defined(MBEDTLS_RSA_C) +#define MBEDTLS_PK_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_PK_PARSE_C +#endif + +/* Helpers to state that each key is supported either on the builtin or PSA side. */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_521) +#define MBEDTLS_ECP_HAVE_SECP521R1 +#endif +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) +#define MBEDTLS_ECP_HAVE_BP512R1 +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) || defined(PSA_WANT_ECC_MONTGOMERY_448) +#define MBEDTLS_ECP_HAVE_CURVE448 +#endif +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) +#define MBEDTLS_ECP_HAVE_BP384R1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_384) +#define MBEDTLS_ECP_HAVE_SECP384R1 +#endif +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) +#define MBEDTLS_ECP_HAVE_BP256R1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_256) +#define MBEDTLS_ECP_HAVE_SECP256K1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_256) +#define MBEDTLS_ECP_HAVE_SECP256R1 +#endif +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || defined(PSA_WANT_ECC_MONTGOMERY_255) +#define MBEDTLS_ECP_HAVE_CURVE25519 +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_224) +#define MBEDTLS_ECP_HAVE_SECP224K1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_224) +#define MBEDTLS_ECP_HAVE_SECP224R1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || defined(PSA_WANT_ECC_SECP_K1_192) +#define MBEDTLS_ECP_HAVE_SECP192K1 +#endif +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || defined(PSA_WANT_ECC_SECP_R1_192) +#define MBEDTLS_ECP_HAVE_SECP192R1 +#endif + +/* Helper symbol to state that the PK module has support for EC keys. This + * can either be provided through the legacy ECP solution or through the + * PSA friendly MBEDTLS_PK_USE_PSA_EC_DATA (see pk.h for its description). */ +#if defined(MBEDTLS_ECP_C) || \ + (defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) +#define MBEDTLS_PK_HAVE_ECC_KEYS +#endif /* MBEDTLS_PK_USE_PSA_EC_DATA || MBEDTLS_ECP_C */ + +/* Historically pkparse did not check the CBC padding when decrypting + * a key. This was a bug, which is now fixed. As a consequence, pkparse + * now needs PKCS7 padding support, but existing configurations might not + * enable it, so we enable it here. */ +#if defined(MBEDTLS_PK_PARSE_C) && defined(MBEDTLS_PKCS5_C) && defined(MBEDTLS_CIPHER_MODE_CBC) +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#endif + +#endif /* MBEDTLS_CONFIG_ADJUST_LEGACY_CRYPTO_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_from_psa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_from_psa.h index 2acb4ae..562e5c2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_from_psa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_legacy_from_psa.h @@ -1,761 +1,761 @@ -/** - * \file mbedtls/config_adjust_legacy_from_psa.h - * \brief Adjust PSA configuration: activate legacy implementations - * - * When MBEDTLS_PSA_CRYPTO_CONFIG is enabled, activate legacy implementations - * of cryptographic mechanisms as needed to fulfill the needs of the PSA - * configuration. Generally speaking, we activate a legacy mechanism if - * it's needed for a requested PSA mechanism and there is no PSA driver - * for it. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H -#define MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H - -/* Define appropriate ACCEL macros for the p256-m driver. - * In the future, those should be generated from the drivers JSON description. - */ -#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) -#define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256 -#define MBEDTLS_PSA_ACCEL_ALG_ECDSA -#define MBEDTLS_PSA_ACCEL_ALG_ECDH -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE -#endif - -/* - * ECC: support for a feature is controlled by a triplet or a pair: - * (curve, key_type public/basic, alg) or (curve, key_type_). - * - * A triplet/pair is accelerated if all of is components are accelerated; - * otherwise each component needs to be built in. - * - * We proceed in two passes: - * 1. Check if acceleration is complete for curves, key types, algs. - * 2. Then enable built-ins for each thing that's either not accelerated of - * doesn't have complete acceleration of the other triplet/pair components. - * - * Note: this needs psa/crypto_adjust_keypair_types.h to have been included - * already, so that we know the full set of key types that are requested. - */ - -/* ECC: curves: enable built-ins as needed. - * - * We need the curve built-in: - * - if it's not accelerated, or - * - if there's a key type with missing acceleration, or - * - if there's a alg with missing acceleration. - */ -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_256) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_256 1 -#define MBEDTLS_ECP_DP_BP256R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_256 */ - -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_384) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_384 1 -#define MBEDTLS_ECP_DP_BP384R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_384 */ - -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_512) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_512 1 -#define MBEDTLS_ECP_DP_BP512R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_512 */ - -#if defined(PSA_WANT_ECC_MONTGOMERY_255) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 1 -#define MBEDTLS_ECP_DP_CURVE25519_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_MONTGOMERY_255 */ - -#if defined(PSA_WANT_ECC_MONTGOMERY_448) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_448 1 -#define MBEDTLS_ECP_DP_CURVE448_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_MONTGOMERY_448 */ - -#if defined(PSA_WANT_ECC_SECP_R1_192) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_192 1 -#define MBEDTLS_ECP_DP_SECP192R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_R1_192 */ - -#if defined(PSA_WANT_ECC_SECP_R1_224) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_224 1 -#define MBEDTLS_ECP_DP_SECP224R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_R1_224 */ - -#if defined(PSA_WANT_ECC_SECP_R1_256) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_R1_256 */ - -#if defined(PSA_WANT_ECC_SECP_R1_384) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_384 1 -#define MBEDTLS_ECP_DP_SECP384R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_R1_384 */ - -#if defined(PSA_WANT_ECC_SECP_R1_521) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_521 1 -#define MBEDTLS_ECP_DP_SECP521R1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_R1_521 */ - -#if defined(PSA_WANT_ECC_SECP_K1_192) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_192) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_192 1 -#define MBEDTLS_ECP_DP_SECP192K1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_K1_192 */ - -#if defined(PSA_WANT_ECC_SECP_K1_224) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_224 1 -#define MBEDTLS_ECP_DP_SECP224K1_ENABLED -/* https://github.com/Mbed-TLS/mbedtls/issues/3541 */ -#error "SECP224K1 is buggy via the PSA API in Mbed TLS." -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_K1_224 */ - -#if defined(PSA_WANT_ECC_SECP_K1_256) -#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_256 1 -#define MBEDTLS_ECP_DP_SECP256K1_ENABLED -#endif /* missing accel */ -#endif /* PSA_WANT_ECC_SECP_K1_256 */ - -/* ECC: algs: enable built-ins as needed. - * - * We need the alg built-in: - * - if it's not accelerated, or - * - if there's a relevant curve (see below) with missing acceleration, or - * - if there's a key type among (public, basic) with missing acceleration. - * - * Relevant curves are: - * - all curves for ECDH - * - Weierstrass curves for (deterministic) ECDSA - * - secp256r1 for EC J-PAKE - */ -#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_DETERMINISTIC_ECDSA) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_WEIERSTRASS_CURVES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) -#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 -#define MBEDTLS_ECDSA_DETERMINISTIC -#define MBEDTLS_HMAC_DRBG_C -#define MBEDTLS_MD_C -#define MBEDTLS_ECDSA_C -#define MBEDTLS_ECP_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_ASN1_PARSE_C -#define MBEDTLS_ASN1_WRITE_C -#endif /* missing accel */ -#endif /* PSA_WANT_ALG_DETERMINISTIC_ECDSA */ - -#if defined(PSA_WANT_ALG_ECDH) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) -#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 -#define MBEDTLS_ECDH_C -#define MBEDTLS_ECP_C -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_ALG_ECDH */ - -#if defined(PSA_WANT_ALG_ECDSA) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_WEIERSTRASS_CURVES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) -#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 -#define MBEDTLS_ECDSA_C -#define MBEDTLS_ECP_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_ASN1_PARSE_C -#define MBEDTLS_ASN1_WRITE_C -#endif /* missing accel */ -#endif /* PSA_WANT_ALG_ECDSA */ - -#if defined(PSA_WANT_ALG_JPAKE) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_JPAKE) || \ - !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) -#define MBEDTLS_PSA_BUILTIN_PAKE 1 -#define MBEDTLS_PSA_BUILTIN_ALG_JPAKE 1 -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_ECP_C -#define MBEDTLS_ECJPAKE_C -#endif /* missing accel */ -#endif /* PSA_WANT_ALG_JPAKE */ - -/* ECC: key types: enable built-ins as needed. - * - * We need the key type built-in: - * - if it's not accelerated, or - * - if there's a curve with missing acceleration, or - * - only for public/basic: if there's an alg with missing acceleration. - */ -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 -#define MBEDTLS_ECP_LIGHT -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#define MBEDTLS_ECP_LIGHT -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC */ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define MBEDTLS_ECP_LIGHT -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT */ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#define MBEDTLS_ECP_C -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT */ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -#define MBEDTLS_ECP_C -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE */ - -/* Note: the condition is always true as DERIVE can't be accelerated yet */ -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || \ - defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 -#define MBEDTLS_ECP_LIGHT -#define MBEDTLS_BIGNUM_C -#endif /* missing accel */ -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ - -/* End of ECC section */ - -#if defined(PSA_WANT_ALG_FFDH) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_FFDH) -#define MBEDTLS_PSA_BUILTIN_ALG_FFDH 1 -#define MBEDTLS_BIGNUM_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_FFDH */ -#endif /* PSA_WANT_ALG_FFDH */ - -#if defined(PSA_WANT_ALG_HKDF) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF) -/* - * The PSA implementation has its own implementation of HKDF, separate from - * hkdf.c. No need to enable MBEDTLS_HKDF_C here. - */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 -#define MBEDTLS_MD_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF */ -#endif /* PSA_WANT_ALG_HKDF */ - -#if defined(PSA_WANT_ALG_HKDF_EXTRACT) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT) -/* - * The PSA implementation has its own implementation of HKDF, separate from - * hkdf.c. No need to enable MBEDTLS_HKDF_C here. - */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT */ -#endif /* PSA_WANT_ALG_HKDF_EXTRACT */ - -#if defined(PSA_WANT_ALG_HKDF_EXPAND) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND) -/* - * The PSA implementation has its own implementation of HKDF, separate from - * hkdf.c. No need to enable MBEDTLS_HKDF_C here. - */ -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND */ -#endif /* PSA_WANT_ALG_HKDF_EXPAND */ - -#if defined(PSA_WANT_ALG_HMAC) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_MD_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ -#endif /* PSA_WANT_ALG_HMAC */ - -#if defined(PSA_WANT_ALG_MD5) && !defined(MBEDTLS_PSA_ACCEL_ALG_MD5) -#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 -#define MBEDTLS_MD5_C -#endif - -#if defined(PSA_WANT_ALG_RIPEMD160) && !defined(MBEDTLS_PSA_ACCEL_ALG_RIPEMD160) -#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 -#define MBEDTLS_RIPEMD160_C -#endif - -#if defined(PSA_WANT_ALG_RSA_OAEP) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 -#define MBEDTLS_RSA_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_OID_C -#define MBEDTLS_PKCS1_V21 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP */ -#endif /* PSA_WANT_ALG_RSA_OAEP */ - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 -#define MBEDTLS_RSA_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_OID_C -#define MBEDTLS_PKCS1_V15 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT */ -#endif /* PSA_WANT_ALG_RSA_PKCS1V15_CRYPT */ - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 -#define MBEDTLS_RSA_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_OID_C -#define MBEDTLS_PKCS1_V15 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN */ -#endif /* PSA_WANT_ALG_RSA_PKCS1V15_SIGN */ - -#if defined(PSA_WANT_ALG_RSA_PSS) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PSS) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 -#define MBEDTLS_RSA_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_OID_C -#define MBEDTLS_PKCS1_V21 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PSS */ -#endif /* PSA_WANT_ALG_RSA_PSS */ - -#if defined(PSA_WANT_ALG_SHA_1) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 -#define MBEDTLS_SHA1_C -#endif - -#if defined(PSA_WANT_ALG_SHA_224) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 -#define MBEDTLS_SHA224_C -#endif - -#if defined(PSA_WANT_ALG_SHA_256) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 -#define MBEDTLS_SHA256_C -#endif - -#if defined(PSA_WANT_ALG_SHA_384) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 -#define MBEDTLS_SHA384_C -#endif - -#if defined(PSA_WANT_ALG_SHA_512) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 -#define MBEDTLS_SHA512_C -#endif - -#if defined(PSA_WANT_ALG_SHA3_224) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_224) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_224 1 -#define MBEDTLS_SHA3_C -#endif - -#if defined(PSA_WANT_ALG_SHA3_256) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_256) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_256 1 -#define MBEDTLS_SHA3_C -#endif - -#if defined(PSA_WANT_ALG_SHA3_384) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_384) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_384 1 -#define MBEDTLS_SHA3_C -#endif - -#if defined(PSA_WANT_ALG_SHA3_512) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_512) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_512 1 -#define MBEDTLS_SHA3_C -#endif - -#if defined(PSA_WANT_ALG_PBKDF2_HMAC) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_HMAC) -#define MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC 1 -#define PSA_HAVE_SOFT_PBKDF2_HMAC 1 -#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ -#endif /* !MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ -#endif /* PSA_WANT_ALG_PBKDF2_HMAC */ - -#if defined(PSA_WANT_ALG_TLS12_PRF) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF) -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_MD_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF */ -#endif /* PSA_WANT_ALG_TLS12_PRF */ - -#if defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS) -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define MBEDTLS_MD_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS */ -#endif /* PSA_WANT_ALG_TLS12_PSK_TO_MS */ - -#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_ECJPAKE_TO_PMS) -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_ECJPAKE_TO_PMS */ -#endif /* PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT */ -#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT */ -#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -#define MBEDTLS_GENPRIME -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE */ -#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC */ -#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC */ - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_IMPORT */ -#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT */ - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_EXPORT */ -#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT */ - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_GENERATE */ -#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE */ - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_BASIC */ -#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC */ - -#if defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_PUBLIC_KEY) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY 1 -#define MBEDTLS_BIGNUM_C -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_PUBLIC_KEY */ -#endif /* PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 -#define MBEDTLS_RSA_C -#define MBEDTLS_BIGNUM_C -#define MBEDTLS_OID_C -#define MBEDTLS_PK_PARSE_C -#define MBEDTLS_PK_WRITE_C -#define MBEDTLS_PK_C -#define MBEDTLS_ASN1_PARSE_C -#define MBEDTLS_ASN1_WRITE_C -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY */ -#endif /* PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY */ - -/* If any of the block modes are requested that don't have an - * associated HW assist, define PSA_HAVE_SOFT_BLOCK_MODE for checking - * in the block cipher key types. */ -#if (defined(PSA_WANT_ALG_CTR) && !defined(MBEDTLS_PSA_ACCEL_ALG_CTR)) || \ - (defined(PSA_WANT_ALG_CFB) && !defined(MBEDTLS_PSA_ACCEL_ALG_CFB)) || \ - (defined(PSA_WANT_ALG_OFB) && !defined(MBEDTLS_PSA_ACCEL_ALG_OFB)) || \ - (defined(PSA_WANT_ALG_ECB_NO_PADDING) && \ - !defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING)) || \ - (defined(PSA_WANT_ALG_CBC_NO_PADDING) && \ - !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING)) || \ - (defined(PSA_WANT_ALG_CBC_PKCS7) && \ - !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7)) || \ - (defined(PSA_WANT_ALG_CMAC) && !defined(MBEDTLS_PSA_ACCEL_ALG_CMAC)) -#define PSA_HAVE_SOFT_BLOCK_MODE 1 -#endif - -#if (defined(PSA_WANT_ALG_GCM) && !defined(MBEDTLS_PSA_ACCEL_ALG_GCM)) || \ - (defined(PSA_WANT_ALG_CCM) && !defined(MBEDTLS_PSA_ACCEL_ALG_CCM)) -#define PSA_HAVE_SOFT_BLOCK_AEAD 1 -#endif - -#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_AES_CMAC_PRF_128) -#define MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 1 -#define PSA_HAVE_SOFT_PBKDF2_CMAC 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_PBKDF2_AES_CMAC_PRF_128 */ -#endif /* PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128 */ - -#if defined(PSA_WANT_KEY_TYPE_AES) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_AES) -#define PSA_HAVE_SOFT_KEY_TYPE_AES 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_AES */ -#if defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ - defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ - defined(PSA_HAVE_SOFT_BLOCK_AEAD) || \ - defined(PSA_HAVE_SOFT_PBKDF2_CMAC) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES 1 -#define MBEDTLS_AES_C -#endif /* PSA_HAVE_SOFT_KEY_TYPE_AES || PSA_HAVE_SOFT_BLOCK_MODE */ -#endif /* PSA_WANT_KEY_TYPE_AES */ - -#if defined(PSA_WANT_KEY_TYPE_ARIA) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ARIA) -#define PSA_HAVE_SOFT_KEY_TYPE_ARIA 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ARIA */ -#if defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ - defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ - defined(PSA_HAVE_SOFT_BLOCK_AEAD) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA 1 -#define MBEDTLS_ARIA_C -#endif /* PSA_HAVE_SOFT_KEY_TYPE_ARIA || PSA_HAVE_SOFT_BLOCK_MODE */ -#endif /* PSA_WANT_KEY_TYPE_ARIA */ - -#if defined(PSA_WANT_KEY_TYPE_CAMELLIA) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CAMELLIA) -#define PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_CAMELLIA */ -#if defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) || \ - defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ - defined(PSA_HAVE_SOFT_BLOCK_AEAD) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA 1 -#define MBEDTLS_CAMELLIA_C -#endif /* PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA || PSA_HAVE_SOFT_BLOCK_MODE */ -#endif /* PSA_WANT_KEY_TYPE_CAMELLIA */ - -#if defined(PSA_WANT_KEY_TYPE_DES) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DES) -#define PSA_HAVE_SOFT_KEY_TYPE_DES 1 -#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DES */ -#if defined(PSA_HAVE_SOFT_KEY_TYPE_DES) || \ - defined(PSA_HAVE_SOFT_BLOCK_MODE) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES 1 -#define MBEDTLS_DES_C -#endif /*PSA_HAVE_SOFT_KEY_TYPE_DES || PSA_HAVE_SOFT_BLOCK_MODE */ -#endif /* PSA_WANT_KEY_TYPE_DES */ - -#if defined(PSA_WANT_KEY_TYPE_CHACHA20) -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20 1 -#define MBEDTLS_CHACHA20_C -#endif /*!MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20 */ -#endif /* PSA_WANT_KEY_TYPE_CHACHA20 */ - -/* If any of the software block ciphers are selected, define - * PSA_HAVE_SOFT_BLOCK_CIPHER, which can be used in any of these - * situations. */ -#if defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_DES) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) -#define PSA_HAVE_SOFT_BLOCK_CIPHER 1 -#endif - -#if defined(PSA_WANT_ALG_STREAM_CIPHER) -#define MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER 1 -#endif /* PSA_WANT_ALG_STREAM_CIPHER */ - -#if defined(PSA_WANT_ALG_CBC_MAC) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) -#error "CBC-MAC is not yet supported via the PSA API in Mbed TLS." -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_MAC 1 -#endif /* !MBEDTLS_PSA_ACCEL_ALG_CBC_MAC */ -#endif /* PSA_WANT_ALG_CBC_MAC */ - -#if defined(PSA_WANT_ALG_CMAC) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) || \ - defined(PSA_HAVE_SOFT_PBKDF2_CMAC) -#define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1 -#define MBEDTLS_CMAC_C -#endif /* !MBEDTLS_PSA_ACCEL_ALG_CMAC */ -#endif /* PSA_WANT_ALG_CMAC */ - -#if defined(PSA_HAVE_SOFT_PBKDF2_HMAC) || \ - defined(PSA_HAVE_SOFT_PBKDF2_CMAC) -#define PSA_HAVE_SOFT_PBKDF2 1 -#endif /* PSA_HAVE_SOFT_PBKDF2_HMAC || PSA_HAVE_SOFT_PBKDF2_CMAC */ - -#if defined(PSA_WANT_ALG_CTR) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CTR) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_PSA_BUILTIN_ALG_CTR 1 -#define MBEDTLS_CIPHER_MODE_CTR -#endif -#endif /* PSA_WANT_ALG_CTR */ - -#if defined(PSA_WANT_ALG_CFB) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CFB) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_PSA_BUILTIN_ALG_CFB 1 -#define MBEDTLS_CIPHER_MODE_CFB -#endif -#endif /* PSA_WANT_ALG_CFB */ - -#if defined(PSA_WANT_ALG_OFB) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_OFB) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_PSA_BUILTIN_ALG_OFB 1 -#define MBEDTLS_CIPHER_MODE_OFB -#endif -#endif /* PSA_WANT_ALG_OFB */ - -#if defined(PSA_WANT_ALG_ECB_NO_PADDING) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING 1 -#endif -#endif /* PSA_WANT_ALG_ECB_NO_PADDING */ - -#if defined(PSA_WANT_ALG_CBC_NO_PADDING) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_CIPHER_MODE_CBC -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING 1 -#endif -#endif /* PSA_WANT_ALG_CBC_NO_PADDING */ - -#if defined(PSA_WANT_ALG_CBC_PKCS7) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7) || \ - defined(PSA_HAVE_SOFT_BLOCK_CIPHER) -#define MBEDTLS_CIPHER_MODE_CBC -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 1 -#define MBEDTLS_CIPHER_PADDING_PKCS7 -#endif -#endif /* PSA_WANT_ALG_CBC_PKCS7 */ - -#if defined(PSA_WANT_ALG_CCM) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CCM) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) -#define MBEDTLS_PSA_BUILTIN_ALG_CCM 1 -#define MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG 1 -#define MBEDTLS_CCM_C -#endif -#endif /* PSA_WANT_ALG_CCM */ - -#if defined(PSA_WANT_ALG_GCM) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_GCM) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ - defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) -#define MBEDTLS_PSA_BUILTIN_ALG_GCM 1 -#define MBEDTLS_GCM_C -#endif -#endif /* PSA_WANT_ALG_GCM */ - -#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) -#if !defined(MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305) -#if defined(PSA_WANT_KEY_TYPE_CHACHA20) -#define MBEDTLS_CHACHAPOLY_C -#define MBEDTLS_CHACHA20_C -#define MBEDTLS_POLY1305_C -#define MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 1 -#endif /* PSA_WANT_KEY_TYPE_CHACHA20 */ -#endif /* !MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305 */ -#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ - -#endif /* MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H */ +/** + * \file mbedtls/config_adjust_legacy_from_psa.h + * \brief Adjust PSA configuration: activate legacy implementations + * + * When MBEDTLS_PSA_CRYPTO_CONFIG is enabled, activate legacy implementations + * of cryptographic mechanisms as needed to fulfill the needs of the PSA + * configuration. Generally speaking, we activate a legacy mechanism if + * it's needed for a requested PSA mechanism and there is no PSA driver + * for it. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H +#define MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H + +/* Define appropriate ACCEL macros for the p256-m driver. + * In the future, those should be generated from the drivers JSON description. + */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) +#define MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256 +#define MBEDTLS_PSA_ACCEL_ALG_ECDSA +#define MBEDTLS_PSA_ACCEL_ALG_ECDH +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE +#endif + +/* + * ECC: support for a feature is controlled by a triplet or a pair: + * (curve, key_type public/basic, alg) or (curve, key_type_). + * + * A triplet/pair is accelerated if all of is components are accelerated; + * otherwise each component needs to be built in. + * + * We proceed in two passes: + * 1. Check if acceleration is complete for curves, key types, algs. + * 2. Then enable built-ins for each thing that's either not accelerated of + * doesn't have complete acceleration of the other triplet/pair components. + * + * Note: this needs psa/crypto_adjust_keypair_types.h to have been included + * already, so that we know the full set of key types that are requested. + */ + +/* ECC: curves: enable built-ins as needed. + * + * We need the curve built-in: + * - if it's not accelerated, or + * - if there's a key type with missing acceleration, or + * - if there's a alg with missing acceleration. + */ +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_256) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_256 1 +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_256 */ + +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_384) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_384 1 +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_384 */ + +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_BRAINPOOL_P_R1_512) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_512 1 +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_512 */ + +#if defined(PSA_WANT_ECC_MONTGOMERY_255) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_255) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 1 +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_MONTGOMERY_255 */ + +#if defined(PSA_WANT_ECC_MONTGOMERY_448) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_MONTGOMERY_448) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_448 1 +#define MBEDTLS_ECP_DP_CURVE448_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_MONTGOMERY_448 */ + +#if defined(PSA_WANT_ECC_SECP_R1_192) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_192) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_192 1 +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_R1_192 */ + +#if defined(PSA_WANT_ECC_SECP_R1_224) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_224) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_224 1 +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_R1_224 */ + +#if defined(PSA_WANT_ECC_SECP_R1_256) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_R1_256 */ + +#if defined(PSA_WANT_ECC_SECP_R1_384) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_384) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_384 1 +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_R1_384 */ + +#if defined(PSA_WANT_ECC_SECP_R1_521) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_521) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_521 1 +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_R1_521 */ + +#if defined(PSA_WANT_ECC_SECP_K1_192) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_192) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_192 1 +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_K1_192 */ + +#if defined(PSA_WANT_ECC_SECP_K1_224) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_224) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_224 1 +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +/* https://github.com/Mbed-TLS/mbedtls/issues/3541 */ +#error "SECP224K1 is buggy via the PSA API in Mbed TLS." +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_K1_224 */ + +#if defined(PSA_WANT_ECC_SECP_K1_256) +#if !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_K1_256) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_256 1 +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#endif /* missing accel */ +#endif /* PSA_WANT_ECC_SECP_K1_256 */ + +/* ECC: algs: enable built-ins as needed. + * + * We need the alg built-in: + * - if it's not accelerated, or + * - if there's a relevant curve (see below) with missing acceleration, or + * - if there's a key type among (public, basic) with missing acceleration. + * + * Relevant curves are: + * - all curves for ECDH + * - Weierstrass curves for (deterministic) ECDSA + * - secp256r1 for EC J-PAKE + */ +#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_DETERMINISTIC_ECDSA) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_WEIERSTRASS_CURVES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) +#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 +#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_HMAC_DRBG_C +#define MBEDTLS_MD_C +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#endif /* missing accel */ +#endif /* PSA_WANT_ALG_DETERMINISTIC_ECDSA */ + +#if defined(PSA_WANT_ALG_ECDH) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 +#define MBEDTLS_ECDH_C +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_ALG_ECDH */ + +#if defined(PSA_WANT_ALG_ECDSA) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_WEIERSTRASS_CURVES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#endif /* missing accel */ +#endif /* PSA_WANT_ALG_ECDSA */ + +#if defined(PSA_WANT_ALG_JPAKE) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_JPAKE) || \ + !defined(MBEDTLS_PSA_ACCEL_ECC_SECP_R1_256) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_KEY_TYPES_BASIC) +#define MBEDTLS_PSA_BUILTIN_PAKE 1 +#define MBEDTLS_PSA_BUILTIN_ALG_JPAKE 1 +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECJPAKE_C +#endif /* missing accel */ +#endif /* PSA_WANT_ALG_JPAKE */ + +/* ECC: key types: enable built-ins as needed. + * + * We need the key type built-in: + * - if it's not accelerated, or + * - if there's a curve with missing acceleration, or + * - only for public/basic: if there's an alg with missing acceleration. + */ +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define MBEDTLS_ECP_LIGHT +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_ALGS) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define MBEDTLS_ECP_LIGHT +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define MBEDTLS_ECP_LIGHT +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE */ + +/* Note: the condition is always true as DERIVE can't be accelerated yet */ +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || \ + defined(MBEDTLS_PSA_ECC_ACCEL_INCOMPLETE_CURVES) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 +#define MBEDTLS_ECP_LIGHT +#define MBEDTLS_BIGNUM_C +#endif /* missing accel */ +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ + +/* End of ECC section */ + +#if defined(PSA_WANT_ALG_FFDH) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_FFDH) +#define MBEDTLS_PSA_BUILTIN_ALG_FFDH 1 +#define MBEDTLS_BIGNUM_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_FFDH */ +#endif /* PSA_WANT_ALG_FFDH */ + +#if defined(PSA_WANT_ALG_HKDF) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF) +/* + * The PSA implementation has its own implementation of HKDF, separate from + * hkdf.c. No need to enable MBEDTLS_HKDF_C here. + */ +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF */ +#endif /* PSA_WANT_ALG_HKDF */ + +#if defined(PSA_WANT_ALG_HKDF_EXTRACT) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT) +/* + * The PSA implementation has its own implementation of HKDF, separate from + * hkdf.c. No need to enable MBEDTLS_HKDF_C here. + */ +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXTRACT */ +#endif /* PSA_WANT_ALG_HKDF_EXTRACT */ + +#if defined(PSA_WANT_ALG_HKDF_EXPAND) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND) +/* + * The PSA implementation has its own implementation of HKDF, separate from + * hkdf.c. No need to enable MBEDTLS_HKDF_C here. + */ +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF_EXPAND */ +#endif /* PSA_WANT_ALG_HKDF_EXPAND */ + +#if defined(PSA_WANT_ALG_HMAC) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ +#endif /* PSA_WANT_ALG_HMAC */ + +#if defined(PSA_WANT_ALG_MD5) && !defined(MBEDTLS_PSA_ACCEL_ALG_MD5) +#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 +#define MBEDTLS_MD5_C +#endif + +#if defined(PSA_WANT_ALG_RIPEMD160) && !defined(MBEDTLS_PSA_ACCEL_ALG_RIPEMD160) +#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 +#define MBEDTLS_RIPEMD160_C +#endif + +#if defined(PSA_WANT_ALG_RSA_OAEP) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V21 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP */ +#endif /* PSA_WANT_ALG_RSA_OAEP */ + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V15 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT */ +#endif /* PSA_WANT_ALG_RSA_PKCS1V15_CRYPT */ + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V15 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN */ +#endif /* PSA_WANT_ALG_RSA_PKCS1V15_SIGN */ + +#if defined(PSA_WANT_ALG_RSA_PSS) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PSS) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V21 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PSS */ +#endif /* PSA_WANT_ALG_RSA_PSS */ + +#if defined(PSA_WANT_ALG_SHA_1) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 +#define MBEDTLS_SHA1_C +#endif + +#if defined(PSA_WANT_ALG_SHA_224) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 +#define MBEDTLS_SHA224_C +#endif + +#if defined(PSA_WANT_ALG_SHA_256) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 +#define MBEDTLS_SHA256_C +#endif + +#if defined(PSA_WANT_ALG_SHA_384) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 +#define MBEDTLS_SHA384_C +#endif + +#if defined(PSA_WANT_ALG_SHA_512) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 +#define MBEDTLS_SHA512_C +#endif + +#if defined(PSA_WANT_ALG_SHA3_224) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_224) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_224 1 +#define MBEDTLS_SHA3_C +#endif + +#if defined(PSA_WANT_ALG_SHA3_256) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_256) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_256 1 +#define MBEDTLS_SHA3_C +#endif + +#if defined(PSA_WANT_ALG_SHA3_384) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_384) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_384 1 +#define MBEDTLS_SHA3_C +#endif + +#if defined(PSA_WANT_ALG_SHA3_512) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_512) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_512 1 +#define MBEDTLS_SHA3_C +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_HMAC) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_HMAC) +#define MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC 1 +#define PSA_HAVE_SOFT_PBKDF2_HMAC 1 +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ +#endif /* !MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ +#endif /* PSA_WANT_ALG_PBKDF2_HMAC */ + +#if defined(PSA_WANT_ALG_TLS12_PRF) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF */ +#endif /* PSA_WANT_ALG_TLS12_PRF */ + +#if defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS */ +#endif /* PSA_WANT_ALG_TLS12_PSK_TO_MS */ + +#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_ECJPAKE_TO_PMS) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_ECJPAKE_TO_PMS */ +#endif /* PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +#define MBEDTLS_GENPRIME +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC */ + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_IMPORT) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_IMPORT */ +#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT */ + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_EXPORT) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_EXPORT */ +#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT */ + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_GENERATE) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_GENERATE */ +#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE */ + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_BASIC) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_KEY_PAIR_BASIC */ +#endif /* PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC */ + +#if defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_PUBLIC_KEY) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY 1 +#define MBEDTLS_BIGNUM_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DH_PUBLIC_KEY */ +#endif /* PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_PK_C +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY */ +#endif /* PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY */ + +/* If any of the block modes are requested that don't have an + * associated HW assist, define PSA_HAVE_SOFT_BLOCK_MODE for checking + * in the block cipher key types. */ +#if (defined(PSA_WANT_ALG_CTR) && !defined(MBEDTLS_PSA_ACCEL_ALG_CTR)) || \ + (defined(PSA_WANT_ALG_CFB) && !defined(MBEDTLS_PSA_ACCEL_ALG_CFB)) || \ + (defined(PSA_WANT_ALG_OFB) && !defined(MBEDTLS_PSA_ACCEL_ALG_OFB)) || \ + (defined(PSA_WANT_ALG_ECB_NO_PADDING) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING)) || \ + (defined(PSA_WANT_ALG_CBC_NO_PADDING) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING)) || \ + (defined(PSA_WANT_ALG_CBC_PKCS7) && \ + !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7)) || \ + (defined(PSA_WANT_ALG_CMAC) && !defined(MBEDTLS_PSA_ACCEL_ALG_CMAC)) +#define PSA_HAVE_SOFT_BLOCK_MODE 1 +#endif + +#if (defined(PSA_WANT_ALG_GCM) && !defined(MBEDTLS_PSA_ACCEL_ALG_GCM)) || \ + (defined(PSA_WANT_ALG_CCM) && !defined(MBEDTLS_PSA_ACCEL_ALG_CCM)) +#define PSA_HAVE_SOFT_BLOCK_AEAD 1 +#endif + +#if defined(PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_PBKDF2_AES_CMAC_PRF_128) +#define MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 1 +#define PSA_HAVE_SOFT_PBKDF2_CMAC 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_PBKDF2_AES_CMAC_PRF_128 */ +#endif /* PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128 */ + +#if defined(PSA_WANT_KEY_TYPE_AES) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_AES) +#define PSA_HAVE_SOFT_KEY_TYPE_AES 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_AES */ +#if defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ + defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ + defined(PSA_HAVE_SOFT_BLOCK_AEAD) || \ + defined(PSA_HAVE_SOFT_PBKDF2_CMAC) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES 1 +#define MBEDTLS_AES_C +#endif /* PSA_HAVE_SOFT_KEY_TYPE_AES || PSA_HAVE_SOFT_BLOCK_MODE */ +#endif /* PSA_WANT_KEY_TYPE_AES */ + +#if defined(PSA_WANT_KEY_TYPE_ARIA) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ARIA) +#define PSA_HAVE_SOFT_KEY_TYPE_ARIA 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ARIA */ +#if defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ + defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ + defined(PSA_HAVE_SOFT_BLOCK_AEAD) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA 1 +#define MBEDTLS_ARIA_C +#endif /* PSA_HAVE_SOFT_KEY_TYPE_ARIA || PSA_HAVE_SOFT_BLOCK_MODE */ +#endif /* PSA_WANT_KEY_TYPE_ARIA */ + +#if defined(PSA_WANT_KEY_TYPE_CAMELLIA) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CAMELLIA) +#define PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_CAMELLIA */ +#if defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) || \ + defined(PSA_HAVE_SOFT_BLOCK_MODE) || \ + defined(PSA_HAVE_SOFT_BLOCK_AEAD) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA 1 +#define MBEDTLS_CAMELLIA_C +#endif /* PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA || PSA_HAVE_SOFT_BLOCK_MODE */ +#endif /* PSA_WANT_KEY_TYPE_CAMELLIA */ + +#if defined(PSA_WANT_KEY_TYPE_DES) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_DES) +#define PSA_HAVE_SOFT_KEY_TYPE_DES 1 +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_DES */ +#if defined(PSA_HAVE_SOFT_KEY_TYPE_DES) || \ + defined(PSA_HAVE_SOFT_BLOCK_MODE) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES 1 +#define MBEDTLS_DES_C +#endif /*PSA_HAVE_SOFT_KEY_TYPE_DES || PSA_HAVE_SOFT_BLOCK_MODE */ +#endif /* PSA_WANT_KEY_TYPE_DES */ + +#if defined(PSA_WANT_KEY_TYPE_CHACHA20) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20 1 +#define MBEDTLS_CHACHA20_C +#endif /*!MBEDTLS_PSA_ACCEL_KEY_TYPE_CHACHA20 */ +#endif /* PSA_WANT_KEY_TYPE_CHACHA20 */ + +/* If any of the software block ciphers are selected, define + * PSA_HAVE_SOFT_BLOCK_CIPHER, which can be used in any of these + * situations. */ +#if defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_DES) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) +#define PSA_HAVE_SOFT_BLOCK_CIPHER 1 +#endif + +#if defined(PSA_WANT_ALG_STREAM_CIPHER) +#define MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER 1 +#endif /* PSA_WANT_ALG_STREAM_CIPHER */ + +#if defined(PSA_WANT_ALG_CBC_MAC) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_MAC) +#error "CBC-MAC is not yet supported via the PSA API in Mbed TLS." +#define MBEDTLS_PSA_BUILTIN_ALG_CBC_MAC 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_CBC_MAC */ +#endif /* PSA_WANT_ALG_CBC_MAC */ + +#if defined(PSA_WANT_ALG_CMAC) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CMAC) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) || \ + defined(PSA_HAVE_SOFT_PBKDF2_CMAC) +#define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1 +#define MBEDTLS_CMAC_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_CMAC */ +#endif /* PSA_WANT_ALG_CMAC */ + +#if defined(PSA_HAVE_SOFT_PBKDF2_HMAC) || \ + defined(PSA_HAVE_SOFT_PBKDF2_CMAC) +#define PSA_HAVE_SOFT_PBKDF2 1 +#endif /* PSA_HAVE_SOFT_PBKDF2_HMAC || PSA_HAVE_SOFT_PBKDF2_CMAC */ + +#if defined(PSA_WANT_ALG_CTR) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CTR) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_PSA_BUILTIN_ALG_CTR 1 +#define MBEDTLS_CIPHER_MODE_CTR +#endif +#endif /* PSA_WANT_ALG_CTR */ + +#if defined(PSA_WANT_ALG_CFB) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CFB) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_PSA_BUILTIN_ALG_CFB 1 +#define MBEDTLS_CIPHER_MODE_CFB +#endif +#endif /* PSA_WANT_ALG_CFB */ + +#if defined(PSA_WANT_ALG_OFB) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_OFB) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_PSA_BUILTIN_ALG_OFB 1 +#define MBEDTLS_CIPHER_MODE_OFB +#endif +#endif /* PSA_WANT_ALG_OFB */ + +#if defined(PSA_WANT_ALG_ECB_NO_PADDING) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECB_NO_PADDING) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING 1 +#endif +#endif /* PSA_WANT_ALG_ECB_NO_PADDING */ + +#if defined(PSA_WANT_ALG_CBC_NO_PADDING) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_NO_PADDING) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING 1 +#endif +#endif /* PSA_WANT_ALG_CBC_NO_PADDING */ + +#if defined(PSA_WANT_ALG_CBC_PKCS7) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CBC_PKCS7) || \ + defined(PSA_HAVE_SOFT_BLOCK_CIPHER) +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 1 +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#endif +#endif /* PSA_WANT_ALG_CBC_PKCS7 */ + +#if defined(PSA_WANT_ALG_CCM) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CCM) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) +#define MBEDTLS_PSA_BUILTIN_ALG_CCM 1 +#define MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG 1 +#define MBEDTLS_CCM_C +#endif +#endif /* PSA_WANT_ALG_CCM */ + +#if defined(PSA_WANT_ALG_GCM) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_GCM) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_AES) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_ARIA) || \ + defined(PSA_HAVE_SOFT_KEY_TYPE_CAMELLIA) +#define MBEDTLS_PSA_BUILTIN_ALG_GCM 1 +#define MBEDTLS_GCM_C +#endif +#endif /* PSA_WANT_ALG_GCM */ + +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305) +#if defined(PSA_WANT_KEY_TYPE_CHACHA20) +#define MBEDTLS_CHACHAPOLY_C +#define MBEDTLS_CHACHA20_C +#define MBEDTLS_POLY1305_C +#define MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 1 +#endif /* PSA_WANT_KEY_TYPE_CHACHA20 */ +#endif /* !MBEDTLS_PSA_ACCEL_ALG_CHACHA20_POLY1305 */ +#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ + +#endif /* MBEDTLS_CONFIG_ADJUST_LEGACY_FROM_PSA_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_from_legacy.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_from_legacy.h index 088711d..76482a3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_from_legacy.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_from_legacy.h @@ -1,346 +1,346 @@ -/** - * \file mbedtls/config_adjust_psa_from_legacy.h - * \brief Adjust PSA configuration: construct PSA configuration from legacy - * - * When MBEDTLS_PSA_CRYPTO_CONFIG is disabled, we automatically enable - * cryptographic mechanisms through the PSA interface when the corresponding - * legacy mechanism is enabled. In many cases, this just enables the PSA - * wrapper code around the legacy implementation, but we also do this for - * some mechanisms where PSA has its own independent implementation so - * that high-level modules that can use either cryptographic API have the - * same feature set in both cases. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H -#define MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H - -/* - * Ensure PSA_WANT_* defines are setup properly if MBEDTLS_PSA_CRYPTO_CONFIG - * is not defined - */ - -#if defined(MBEDTLS_CCM_C) -#define MBEDTLS_PSA_BUILTIN_ALG_CCM 1 -#define MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG 1 -#define PSA_WANT_ALG_CCM 1 -#define PSA_WANT_ALG_CCM_STAR_NO_TAG 1 -#endif /* MBEDTLS_CCM_C */ - -#if defined(MBEDTLS_CMAC_C) -#define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1 -#define PSA_WANT_ALG_CMAC 1 -#endif /* MBEDTLS_CMAC_C */ - -#if defined(MBEDTLS_ECDH_C) -#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 -#define PSA_WANT_ALG_ECDH 1 -#endif /* MBEDTLS_ECDH_C */ - -#if defined(MBEDTLS_ECDSA_C) -#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 -#define PSA_WANT_ALG_ECDSA 1 -#define PSA_WANT_ALG_ECDSA_ANY 1 - -// Only add in DETERMINISTIC support if ECDSA is also enabled -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) -#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 -#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 -#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ - -#endif /* MBEDTLS_ECDSA_C */ - -#if defined(MBEDTLS_ECP_C) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -/* Normally we wouldn't enable this because it's not implemented in ecp.c, - * but since it used to be available any time ECP_C was enabled, let's enable - * it anyway for the sake of backwards compatibility */ -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -/* See comment for PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE above. */ -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 -#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 -#endif /* MBEDTLS_ECP_C */ - -#if defined(MBEDTLS_DHM_C) -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 -#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 -#define PSA_WANT_ALG_FFDH 1 -#define PSA_WANT_DH_FAMILY_RFC7919 1 -#define MBEDTLS_PSA_BUILTIN_ALG_FFDH 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY 1 -#endif /* MBEDTLS_DHM_C */ - -#if defined(MBEDTLS_GCM_C) -#define MBEDTLS_PSA_BUILTIN_ALG_GCM 1 -#define PSA_WANT_ALG_GCM 1 -#endif /* MBEDTLS_GCM_C */ - -/* Enable PSA HKDF algorithm if mbedtls HKDF is supported. - * PSA HKDF EXTRACT and PSA HKDF EXPAND have minimal cost when - * PSA HKDF is enabled, so enable both algorithms together - * with PSA HKDF. */ -#if defined(MBEDTLS_HKDF_C) -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define PSA_WANT_ALG_HMAC 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 -#define PSA_WANT_ALG_HKDF 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT 1 -#define PSA_WANT_ALG_HKDF_EXTRACT 1 -#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND 1 -#define PSA_WANT_ALG_HKDF_EXPAND 1 -#endif /* MBEDTLS_HKDF_C */ - -#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 -#define PSA_WANT_ALG_HMAC 1 -#define PSA_WANT_KEY_TYPE_HMAC 1 - -#if defined(MBEDTLS_MD_C) -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 -#define PSA_WANT_ALG_TLS12_PRF 1 -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 -#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 -#endif /* MBEDTLS_MD_C */ - -#if defined(MBEDTLS_MD5_C) -#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 -#define PSA_WANT_ALG_MD5 1 -#endif - -#if defined(MBEDTLS_ECJPAKE_C) -#define MBEDTLS_PSA_BUILTIN_PAKE 1 -#define MBEDTLS_PSA_BUILTIN_ALG_JPAKE 1 -#define PSA_WANT_ALG_JPAKE 1 -#endif - -#if defined(MBEDTLS_RIPEMD160_C) -#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 -#define PSA_WANT_ALG_RIPEMD160 1 -#endif - -#if defined(MBEDTLS_RSA_C) -#if defined(MBEDTLS_PKCS1_V15) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 -#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW 1 -#endif /* MBEDTLS_PKCS1_V15 */ -#if defined(MBEDTLS_PKCS1_V21) -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 -#define PSA_WANT_ALG_RSA_OAEP 1 -#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 -#define PSA_WANT_ALG_RSA_PSS 1 -#endif /* MBEDTLS_PKCS1_V21 */ -#if defined(MBEDTLS_GENPRIME) -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -#endif /* MBEDTLS_GENPRIME */ -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 -#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 -#endif /* MBEDTLS_RSA_C */ - -#if defined(MBEDTLS_SHA1_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 -#define PSA_WANT_ALG_SHA_1 1 -#endif - -#if defined(MBEDTLS_SHA224_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 -#define PSA_WANT_ALG_SHA_224 1 -#endif - -#if defined(MBEDTLS_SHA256_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 -#define PSA_WANT_ALG_SHA_256 1 -#endif - -#if defined(MBEDTLS_SHA384_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 -#define PSA_WANT_ALG_SHA_384 1 -#endif - -#if defined(MBEDTLS_SHA512_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 -#define PSA_WANT_ALG_SHA_512 1 -#endif - -#if defined(MBEDTLS_SHA3_C) -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_224 1 -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_256 1 -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_384 1 -#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_512 1 -#define PSA_WANT_ALG_SHA3_224 1 -#define PSA_WANT_ALG_SHA3_256 1 -#define PSA_WANT_ALG_SHA3_384 1 -#define PSA_WANT_ALG_SHA3_512 1 -#endif - -#if defined(MBEDTLS_AES_C) -#define PSA_WANT_KEY_TYPE_AES 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES 1 -#endif - -#if defined(MBEDTLS_ARIA_C) -#define PSA_WANT_KEY_TYPE_ARIA 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA 1 -#endif - -#if defined(MBEDTLS_CAMELLIA_C) -#define PSA_WANT_KEY_TYPE_CAMELLIA 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA 1 -#endif - -#if defined(MBEDTLS_DES_C) -#define PSA_WANT_KEY_TYPE_DES 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES 1 -#endif - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) -#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS 1 -#define PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS 1 -#endif - -#if defined(MBEDTLS_CHACHA20_C) -#define PSA_WANT_KEY_TYPE_CHACHA20 1 -#define PSA_WANT_ALG_STREAM_CIPHER 1 -#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20 1 -#define MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER 1 -#if defined(MBEDTLS_CHACHAPOLY_C) -#define PSA_WANT_ALG_CHACHA20_POLY1305 1 -#define MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 1 -#endif -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING 1 -#define PSA_WANT_ALG_CBC_NO_PADDING 1 -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) -#define MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 1 -#define PSA_WANT_ALG_CBC_PKCS7 1 -#endif -#endif - -#if defined(MBEDTLS_AES_C) || defined(MBEDTLS_DES_C) || \ - defined(MBEDTLS_ARIA_C) || defined(MBEDTLS_CAMELLIA_C) -#define MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING 1 -#define PSA_WANT_ALG_ECB_NO_PADDING 1 -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -#define MBEDTLS_PSA_BUILTIN_ALG_CFB 1 -#define PSA_WANT_ALG_CFB 1 -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -#define MBEDTLS_PSA_BUILTIN_ALG_CTR 1 -#define PSA_WANT_ALG_CTR 1 -#endif - -#if defined(MBEDTLS_CIPHER_MODE_OFB) -#define MBEDTLS_PSA_BUILTIN_ALG_OFB 1 -#define PSA_WANT_ALG_OFB 1 -#endif - -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_256 1 -#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 -#endif - -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_384 1 -#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 -#endif - -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_512 1 -#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 1 -#define PSA_WANT_ECC_MONTGOMERY_255 1 -#endif - -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_448 1 -#define PSA_WANT_ECC_MONTGOMERY_448 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_192 1 -#define PSA_WANT_ECC_SECP_R1_192 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_224 1 -#define PSA_WANT_ECC_SECP_R1_224 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 -#define PSA_WANT_ECC_SECP_R1_256 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_384 1 -#define PSA_WANT_ECC_SECP_R1_384 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_521 1 -#define PSA_WANT_ECC_SECP_R1_521 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_192 1 -#define PSA_WANT_ECC_SECP_K1_192 1 -#endif - -/* SECP224K1 is buggy via the PSA API (https://github.com/Mbed-TLS/mbedtls/issues/3541) */ -#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_224 1 -#define PSA_WANT_ECC_SECP_K1_224 1 -#endif - -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) -#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_256 1 -#define PSA_WANT_ECC_SECP_K1_256 1 -#endif - -#endif /* MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H */ +/** + * \file mbedtls/config_adjust_psa_from_legacy.h + * \brief Adjust PSA configuration: construct PSA configuration from legacy + * + * When MBEDTLS_PSA_CRYPTO_CONFIG is disabled, we automatically enable + * cryptographic mechanisms through the PSA interface when the corresponding + * legacy mechanism is enabled. In many cases, this just enables the PSA + * wrapper code around the legacy implementation, but we also do this for + * some mechanisms where PSA has its own independent implementation so + * that high-level modules that can use either cryptographic API have the + * same feature set in both cases. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H +#define MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H + +/* + * Ensure PSA_WANT_* defines are setup properly if MBEDTLS_PSA_CRYPTO_CONFIG + * is not defined + */ + +#if defined(MBEDTLS_CCM_C) +#define MBEDTLS_PSA_BUILTIN_ALG_CCM 1 +#define MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG 1 +#define PSA_WANT_ALG_CCM 1 +#define PSA_WANT_ALG_CCM_STAR_NO_TAG 1 +#endif /* MBEDTLS_CCM_C */ + +#if defined(MBEDTLS_CMAC_C) +#define MBEDTLS_PSA_BUILTIN_ALG_CMAC 1 +#define PSA_WANT_ALG_CMAC 1 +#endif /* MBEDTLS_CMAC_C */ + +#if defined(MBEDTLS_ECDH_C) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 +#define PSA_WANT_ALG_ECDH 1 +#endif /* MBEDTLS_ECDH_C */ + +#if defined(MBEDTLS_ECDSA_C) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 +#define PSA_WANT_ALG_ECDSA 1 +#define PSA_WANT_ALG_ECDSA_ANY 1 + +// Only add in DETERMINISTIC support if ECDSA is also enabled +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#endif /* MBEDTLS_ECDSA_C */ + +#if defined(MBEDTLS_ECP_C) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +/* Normally we wouldn't enable this because it's not implemented in ecp.c, + * but since it used to be available any time ECP_C was enabled, let's enable + * it anyway for the sake of backwards compatibility */ +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +/* See comment for PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE above. */ +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_DHM_C) +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 +#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 +#define PSA_WANT_ALG_FFDH 1 +#define PSA_WANT_DH_FAMILY_RFC7919 1 +#define MBEDTLS_PSA_BUILTIN_ALG_FFDH 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY 1 +#endif /* MBEDTLS_DHM_C */ + +#if defined(MBEDTLS_GCM_C) +#define MBEDTLS_PSA_BUILTIN_ALG_GCM 1 +#define PSA_WANT_ALG_GCM 1 +#endif /* MBEDTLS_GCM_C */ + +/* Enable PSA HKDF algorithm if mbedtls HKDF is supported. + * PSA HKDF EXTRACT and PSA HKDF EXPAND have minimal cost when + * PSA HKDF is enabled, so enable both algorithms together + * with PSA HKDF. */ +#if defined(MBEDTLS_HKDF_C) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define PSA_WANT_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 +#define PSA_WANT_ALG_HKDF 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT 1 +#define PSA_WANT_ALG_HKDF_EXTRACT 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND 1 +#define PSA_WANT_ALG_HKDF_EXPAND 1 +#endif /* MBEDTLS_HKDF_C */ + +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_KEY_TYPE_HMAC 1 + +#if defined(MBEDTLS_MD_C) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 +#define PSA_WANT_ALG_TLS12_PRF 1 +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 +#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 +#endif /* MBEDTLS_MD_C */ + +#if defined(MBEDTLS_MD5_C) +#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 +#define PSA_WANT_ALG_MD5 1 +#endif + +#if defined(MBEDTLS_ECJPAKE_C) +#define MBEDTLS_PSA_BUILTIN_PAKE 1 +#define MBEDTLS_PSA_BUILTIN_ALG_JPAKE 1 +#define PSA_WANT_ALG_JPAKE 1 +#endif + +#if defined(MBEDTLS_RIPEMD160_C) +#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 +#define PSA_WANT_ALG_RIPEMD160 1 +#endif + +#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PKCS1_V15) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW 1 +#endif /* MBEDTLS_PKCS1_V15 */ +#if defined(MBEDTLS_PKCS1_V21) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 +#define PSA_WANT_ALG_RSA_OAEP 1 +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 +#define PSA_WANT_ALG_RSA_PSS 1 +#endif /* MBEDTLS_PKCS1_V21 */ +#if defined(MBEDTLS_GENPRIME) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +#endif /* MBEDTLS_GENPRIME */ +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_SHA1_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 +#define PSA_WANT_ALG_SHA_1 1 +#endif + +#if defined(MBEDTLS_SHA224_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 +#define PSA_WANT_ALG_SHA_224 1 +#endif + +#if defined(MBEDTLS_SHA256_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 +#define PSA_WANT_ALG_SHA_256 1 +#endif + +#if defined(MBEDTLS_SHA384_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 +#define PSA_WANT_ALG_SHA_384 1 +#endif + +#if defined(MBEDTLS_SHA512_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 +#define PSA_WANT_ALG_SHA_512 1 +#endif + +#if defined(MBEDTLS_SHA3_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_224 1 +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_256 1 +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_384 1 +#define MBEDTLS_PSA_BUILTIN_ALG_SHA3_512 1 +#define PSA_WANT_ALG_SHA3_224 1 +#define PSA_WANT_ALG_SHA3_256 1 +#define PSA_WANT_ALG_SHA3_384 1 +#define PSA_WANT_ALG_SHA3_512 1 +#endif + +#if defined(MBEDTLS_AES_C) +#define PSA_WANT_KEY_TYPE_AES 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES 1 +#endif + +#if defined(MBEDTLS_ARIA_C) +#define PSA_WANT_KEY_TYPE_ARIA 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA 1 +#endif + +#if defined(MBEDTLS_CAMELLIA_C) +#define PSA_WANT_KEY_TYPE_CAMELLIA 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA 1 +#endif + +#if defined(MBEDTLS_DES_C) +#define PSA_WANT_KEY_TYPE_DES 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES 1 +#endif + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS 1 +#define PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS 1 +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#define PSA_WANT_KEY_TYPE_CHACHA20 1 +#define PSA_WANT_ALG_STREAM_CIPHER 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20 1 +#define MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER 1 +#if defined(MBEDTLS_CHACHAPOLY_C) +#define PSA_WANT_ALG_CHACHA20_POLY1305 1 +#define MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 1 +#endif +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING 1 +#define PSA_WANT_ALG_CBC_NO_PADDING 1 +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) +#define MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 1 +#define PSA_WANT_ALG_CBC_PKCS7 1 +#endif +#endif + +#if defined(MBEDTLS_AES_C) || defined(MBEDTLS_DES_C) || \ + defined(MBEDTLS_ARIA_C) || defined(MBEDTLS_CAMELLIA_C) +#define MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING 1 +#define PSA_WANT_ALG_ECB_NO_PADDING 1 +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +#define MBEDTLS_PSA_BUILTIN_ALG_CFB 1 +#define PSA_WANT_ALG_CFB 1 +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +#define MBEDTLS_PSA_BUILTIN_ALG_CTR 1 +#define PSA_WANT_ALG_CTR 1 +#endif + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +#define MBEDTLS_PSA_BUILTIN_ALG_OFB 1 +#define PSA_WANT_ALG_OFB 1 +#endif + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_256 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 +#endif + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_384 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 +#endif + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_BRAINPOOL_P_R1_512 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_255 1 +#define PSA_WANT_ECC_MONTGOMERY_255 1 +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_MONTGOMERY_448 1 +#define PSA_WANT_ECC_MONTGOMERY_448 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_192 1 +#define PSA_WANT_ECC_SECP_R1_192 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_224 1 +#define PSA_WANT_ECC_SECP_R1_224 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_256 1 +#define PSA_WANT_ECC_SECP_R1_256 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_384 1 +#define PSA_WANT_ECC_SECP_R1_384 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_R1_521 1 +#define PSA_WANT_ECC_SECP_R1_521 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_192 1 +#define PSA_WANT_ECC_SECP_K1_192 1 +#endif + +/* SECP224K1 is buggy via the PSA API (https://github.com/Mbed-TLS/mbedtls/issues/3541) */ +#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_224 1 +#define PSA_WANT_ECC_SECP_K1_224 1 +#endif + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define MBEDTLS_PSA_BUILTIN_ECC_SECP_K1_256 1 +#define PSA_WANT_ECC_SECP_K1_256 1 +#endif + +#endif /* MBEDTLS_CONFIG_ADJUST_PSA_FROM_LEGACY_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_superset_legacy.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_superset_legacy.h index 3d9029b..e202398 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_superset_legacy.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_psa_superset_legacy.h @@ -1,154 +1,154 @@ -/** - * \file mbedtls/config_adjust_psa_superset_legacy.h - * \brief Adjust PSA configuration: automatic enablement from legacy - * - * To simplify some edge cases, we automatically enable certain cryptographic - * mechanisms in the PSA API if they are enabled in the legacy API. The general - * idea is that if legacy module M uses mechanism A internally, and A has - * both a legacy and a PSA implementation, we enable A through PSA whenever - * it's enabled through legacy. This facilitates the transition to PSA - * implementations of A for users of M. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H -#define MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H - -/****************************************************************/ -/* Hashes that are built in are also enabled in PSA. - * This simplifies dependency declarations especially - * for modules that obey MBEDTLS_USE_PSA_CRYPTO. */ -/****************************************************************/ - -#if defined(MBEDTLS_MD5_C) -#define PSA_WANT_ALG_MD5 1 -#endif - -#if defined(MBEDTLS_RIPEMD160_C) -#define PSA_WANT_ALG_RIPEMD160 1 -#endif - -#if defined(MBEDTLS_SHA1_C) -#define PSA_WANT_ALG_SHA_1 1 -#endif - -#if defined(MBEDTLS_SHA224_C) -#define PSA_WANT_ALG_SHA_224 1 -#endif - -#if defined(MBEDTLS_SHA256_C) -#define PSA_WANT_ALG_SHA_256 1 -#endif - -#if defined(MBEDTLS_SHA384_C) -#define PSA_WANT_ALG_SHA_384 1 -#endif - -#if defined(MBEDTLS_SHA512_C) -#define PSA_WANT_ALG_SHA_512 1 -#endif - -#if defined(MBEDTLS_SHA3_C) -#define PSA_WANT_ALG_SHA3_224 1 -#define PSA_WANT_ALG_SHA3_256 1 -#define PSA_WANT_ALG_SHA3_384 1 -#define PSA_WANT_ALG_SHA3_512 1 -#endif - -/* Ensure that the PSA's supported curves (PSA_WANT_ECC_xxx) are always a - * superset of the builtin ones (MBEDTLS_ECP_DP_xxx). */ -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) -#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_256 */ -#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) -#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_384 */ -#endif /*MBEDTLS_ECP_DP_BP384R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) -#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 -#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_512 */ -#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) -#if !defined(PSA_WANT_ECC_MONTGOMERY_255) -#define PSA_WANT_ECC_MONTGOMERY_255 1 -#endif /* PSA_WANT_ECC_MONTGOMERY_255 */ -#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) -#if !defined(PSA_WANT_ECC_MONTGOMERY_448) -#define PSA_WANT_ECC_MONTGOMERY_448 1 -#endif /* PSA_WANT_ECC_MONTGOMERY_448 */ -#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_R1_192) -#define PSA_WANT_ECC_SECP_R1_192 1 -#endif /* PSA_WANT_ECC_SECP_R1_192 */ -#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_R1_224) -#define PSA_WANT_ECC_SECP_R1_224 1 -#endif /* PSA_WANT_ECC_SECP_R1_224 */ -#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_R1_256) -#define PSA_WANT_ECC_SECP_R1_256 1 -#endif /* PSA_WANT_ECC_SECP_R1_256 */ -#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_R1_384) -#define PSA_WANT_ECC_SECP_R1_384 1 -#endif /* PSA_WANT_ECC_SECP_R1_384 */ -#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_R1_521) -#define PSA_WANT_ECC_SECP_R1_521 1 -#endif /* PSA_WANT_ECC_SECP_R1_521 */ -#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_K1_192) -#define PSA_WANT_ECC_SECP_K1_192 1 -#endif /* PSA_WANT_ECC_SECP_K1_192 */ -#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ - -/* SECP224K1 is buggy via the PSA API (https://github.com/Mbed-TLS/mbedtls/issues/3541) */ -#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_K1_224) -#define PSA_WANT_ECC_SECP_K1_224 1 -#endif /* PSA_WANT_ECC_SECP_K1_224 */ -#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) -#if !defined(PSA_WANT_ECC_SECP_K1_256) -#define PSA_WANT_ECC_SECP_K1_256 1 -#endif /* PSA_WANT_ECC_SECP_K1_256 */ -#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ - -#endif /* MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H */ +/** + * \file mbedtls/config_adjust_psa_superset_legacy.h + * \brief Adjust PSA configuration: automatic enablement from legacy + * + * To simplify some edge cases, we automatically enable certain cryptographic + * mechanisms in the PSA API if they are enabled in the legacy API. The general + * idea is that if legacy module M uses mechanism A internally, and A has + * both a legacy and a PSA implementation, we enable A through PSA whenever + * it's enabled through legacy. This facilitates the transition to PSA + * implementations of A for users of M. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H +#define MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H + +/****************************************************************/ +/* Hashes that are built in are also enabled in PSA. + * This simplifies dependency declarations especially + * for modules that obey MBEDTLS_USE_PSA_CRYPTO. */ +/****************************************************************/ + +#if defined(MBEDTLS_MD5_C) +#define PSA_WANT_ALG_MD5 1 +#endif + +#if defined(MBEDTLS_RIPEMD160_C) +#define PSA_WANT_ALG_RIPEMD160 1 +#endif + +#if defined(MBEDTLS_SHA1_C) +#define PSA_WANT_ALG_SHA_1 1 +#endif + +#if defined(MBEDTLS_SHA224_C) +#define PSA_WANT_ALG_SHA_224 1 +#endif + +#if defined(MBEDTLS_SHA256_C) +#define PSA_WANT_ALG_SHA_256 1 +#endif + +#if defined(MBEDTLS_SHA384_C) +#define PSA_WANT_ALG_SHA_384 1 +#endif + +#if defined(MBEDTLS_SHA512_C) +#define PSA_WANT_ALG_SHA_512 1 +#endif + +#if defined(MBEDTLS_SHA3_C) +#define PSA_WANT_ALG_SHA3_224 1 +#define PSA_WANT_ALG_SHA3_256 1 +#define PSA_WANT_ALG_SHA3_384 1 +#define PSA_WANT_ALG_SHA3_512 1 +#endif + +/* Ensure that the PSA's supported curves (PSA_WANT_ECC_xxx) are always a + * superset of the builtin ones (MBEDTLS_ECP_DP_xxx). */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) +#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_256 */ +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) +#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_384 */ +#endif /*MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +#if !defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) +#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 +#endif /* PSA_WANT_ECC_BRAINPOOL_P_R1_512 */ +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#if !defined(PSA_WANT_ECC_MONTGOMERY_255) +#define PSA_WANT_ECC_MONTGOMERY_255 1 +#endif /* PSA_WANT_ECC_MONTGOMERY_255 */ +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#if !defined(PSA_WANT_ECC_MONTGOMERY_448) +#define PSA_WANT_ECC_MONTGOMERY_448 1 +#endif /* PSA_WANT_ECC_MONTGOMERY_448 */ +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_R1_192) +#define PSA_WANT_ECC_SECP_R1_192 1 +#endif /* PSA_WANT_ECC_SECP_R1_192 */ +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_R1_224) +#define PSA_WANT_ECC_SECP_R1_224 1 +#endif /* PSA_WANT_ECC_SECP_R1_224 */ +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_R1_256) +#define PSA_WANT_ECC_SECP_R1_256 1 +#endif /* PSA_WANT_ECC_SECP_R1_256 */ +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_R1_384) +#define PSA_WANT_ECC_SECP_R1_384 1 +#endif /* PSA_WANT_ECC_SECP_R1_384 */ +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_R1_521) +#define PSA_WANT_ECC_SECP_R1_521 1 +#endif /* PSA_WANT_ECC_SECP_R1_521 */ +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_K1_192) +#define PSA_WANT_ECC_SECP_K1_192 1 +#endif /* PSA_WANT_ECC_SECP_K1_192 */ +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +/* SECP224K1 is buggy via the PSA API (https://github.com/Mbed-TLS/mbedtls/issues/3541) */ +#if 0 && defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_K1_224) +#define PSA_WANT_ECC_SECP_K1_224 1 +#endif /* PSA_WANT_ECC_SECP_K1_224 */ +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#if !defined(PSA_WANT_ECC_SECP_K1_256) +#define PSA_WANT_ECC_SECP_K1_256 1 +#endif /* PSA_WANT_ECC_SECP_K1_256 */ +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#endif /* MBEDTLS_CONFIG_ADJUST_PSA_SUPERSET_LEGACY_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_ssl.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_ssl.h index 2275f3a..9842ef5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_ssl.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_ssl.h @@ -1,88 +1,88 @@ -/** - * \file mbedtls/config_adjust_ssl.h - * \brief Adjust TLS configuration - * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx - * configurations need to be explicitly enabled by the user: enabling - * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a - * compilation error. However, we do automatically enable certain options - * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option - * used to identify parts of a module that are used by other module, and we - * don't want to make the symbol MBEDTLS_xxx_B part of the public API. - * Another case is if A didn't depend on B in earlier versions, and we - * want to use B in A but we need to preserve backward compatibility with - * configurations that explicitly activate MBEDTLS_xxx_A but not - * MBEDTLS_xxx_B. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_SSL_H -#define MBEDTLS_CONFIG_ADJUST_SSL_H - -/* The following blocks make it easier to disable all of TLS, - * or of TLS 1.2 or 1.3 or DTLS, without having to manually disable all - * key exchanges, options and extensions related to them. */ - -#if !defined(MBEDTLS_SSL_TLS_C) -#undef MBEDTLS_SSL_CLI_C -#undef MBEDTLS_SSL_SRV_C -#undef MBEDTLS_SSL_PROTO_TLS1_3 -#undef MBEDTLS_SSL_PROTO_TLS1_2 -#undef MBEDTLS_SSL_PROTO_DTLS -#endif - -#if !defined(MBEDTLS_SSL_PROTO_DTLS) -#undef MBEDTLS_SSL_DTLS_ANTI_REPLAY -#undef MBEDTLS_SSL_DTLS_CONNECTION_ID -#undef MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT -#undef MBEDTLS_SSL_DTLS_HELLO_VERIFY -#undef MBEDTLS_SSL_DTLS_SRTP -#undef MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE -#endif - -#if !defined(MBEDTLS_SSL_PROTO_TLS1_2) -#undef MBEDTLS_SSL_ENCRYPT_THEN_MAC -#undef MBEDTLS_SSL_EXTENDED_MASTER_SECRET -#undef MBEDTLS_SSL_RENEGOTIATION -#undef MBEDTLS_KEY_EXCHANGE_RSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_PSK_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED -#undef MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED -#endif - -#if !defined(MBEDTLS_SSL_PROTO_TLS1_3) -#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED -#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED -#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED -#undef MBEDTLS_SSL_EARLY_DATA -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ - (defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)) -#define MBEDTLS_SSL_TLS1_2_SOME_ECC -#endif - -#endif /* MBEDTLS_CONFIG_ADJUST_SSL_H */ +/** + * \file mbedtls/config_adjust_ssl.h + * \brief Adjust TLS configuration + * + * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * configurations need to be explicitly enabled by the user: enabling + * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a + * compilation error. However, we do automatically enable certain options + * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option + * used to identify parts of a module that are used by other module, and we + * don't want to make the symbol MBEDTLS_xxx_B part of the public API. + * Another case is if A didn't depend on B in earlier versions, and we + * want to use B in A but we need to preserve backward compatibility with + * configurations that explicitly activate MBEDTLS_xxx_A but not + * MBEDTLS_xxx_B. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_SSL_H +#define MBEDTLS_CONFIG_ADJUST_SSL_H + +/* The following blocks make it easier to disable all of TLS, + * or of TLS 1.2 or 1.3 or DTLS, without having to manually disable all + * key exchanges, options and extensions related to them. */ + +#if !defined(MBEDTLS_SSL_TLS_C) +#undef MBEDTLS_SSL_CLI_C +#undef MBEDTLS_SSL_SRV_C +#undef MBEDTLS_SSL_PROTO_TLS1_3 +#undef MBEDTLS_SSL_PROTO_TLS1_2 +#undef MBEDTLS_SSL_PROTO_DTLS +#endif + +#if !defined(MBEDTLS_SSL_PROTO_DTLS) +#undef MBEDTLS_SSL_DTLS_ANTI_REPLAY +#undef MBEDTLS_SSL_DTLS_CONNECTION_ID +#undef MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT +#undef MBEDTLS_SSL_DTLS_HELLO_VERIFY +#undef MBEDTLS_SSL_DTLS_SRTP +#undef MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#endif + +#if !defined(MBEDTLS_SSL_PROTO_TLS1_2) +#undef MBEDTLS_SSL_ENCRYPT_THEN_MAC +#undef MBEDTLS_SSL_EXTENDED_MASTER_SECRET +#undef MBEDTLS_SSL_RENEGOTIATION +#undef MBEDTLS_KEY_EXCHANGE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#undef MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED +#endif + +#if !defined(MBEDTLS_SSL_PROTO_TLS1_3) +#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED +#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED +#undef MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED +#undef MBEDTLS_SSL_EARLY_DATA +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ + (defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)) +#define MBEDTLS_SSL_TLS1_2_SOME_ECC +#endif + +#endif /* MBEDTLS_CONFIG_ADJUST_SSL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_x509.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_x509.h index 99a0ace..bb49b0d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_x509.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_adjust_x509.h @@ -1,37 +1,37 @@ -/** - * \file mbedtls/config_adjust_x509.h - * \brief Adjust X.509 configuration - * - * Automatically enable certain dependencies. Generally, MBEDLTS_xxx - * configurations need to be explicitly enabled by the user: enabling - * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a - * compilation error. However, we do automatically enable certain options - * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option - * used to identify parts of a module that are used by other module, and we - * don't want to make the symbol MBEDTLS_xxx_B part of the public API. - * Another case is if A didn't depend on B in earlier versions, and we - * want to use B in A but we need to preserve backward compatibility with - * configurations that explicitly activate MBEDTLS_xxx_A but not - * MBEDTLS_xxx_B. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_ADJUST_X509_H -#define MBEDTLS_CONFIG_ADJUST_X509_H - -#endif /* MBEDTLS_CONFIG_ADJUST_X509_H */ +/** + * \file mbedtls/config_adjust_x509.h + * \brief Adjust X.509 configuration + * + * Automatically enable certain dependencies. Generally, MBEDLTS_xxx + * configurations need to be explicitly enabled by the user: enabling + * MBEDTLS_xxx_A but not MBEDTLS_xxx_B when A requires B results in a + * compilation error. However, we do automatically enable certain options + * in some circumstances. One case is if MBEDTLS_xxx_B is an internal option + * used to identify parts of a module that are used by other module, and we + * don't want to make the symbol MBEDTLS_xxx_B part of the public API. + * Another case is if A didn't depend on B in earlier versions, and we + * want to use B in A but we need to preserve backward compatibility with + * configurations that explicitly activate MBEDTLS_xxx_A but not + * MBEDTLS_xxx_B. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_ADJUST_X509_H +#define MBEDTLS_CONFIG_ADJUST_X509_H + +#endif /* MBEDTLS_CONFIG_ADJUST_X509_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_psa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_psa.h index 2d23971..6300c98 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_psa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/config_psa.h @@ -1,67 +1,67 @@ -/** - * \file mbedtls/config_psa.h - * \brief PSA crypto configuration options (set of defines) - * - * This set of compile-time options takes settings defined in - * include/mbedtls/mbedtls_config.h and include/psa/crypto_config.h and uses - * those definitions to define symbols used in the library code. - * - * Users and integrators should not edit this file, please edit - * include/mbedtls/mbedtls_config.h for MBEDTLS_XXX settings or - * include/psa/crypto_config.h for PSA_WANT_XXX settings. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONFIG_PSA_H -#define MBEDTLS_CONFIG_PSA_H - -#include "psa/crypto_legacy.h" - -#include "psa/crypto_adjust_config_synonyms.h" - -#include "mbedtls/config_adjust_psa_superset_legacy.h" - -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) - -/* Require built-in implementations based on PSA requirements */ - -/* We need this to have a complete list of requirements - * before we deduce what built-ins are required. */ -#include "psa/crypto_adjust_config_key_pair_types.h" - -#include "mbedtls/config_adjust_legacy_from_psa.h" - -#else /* MBEDTLS_PSA_CRYPTO_CONFIG */ - -/* Infer PSA requirements from Mbed TLS capabilities */ - -#include "mbedtls/config_adjust_psa_from_legacy.h" - -/* Hopefully the file above will have enabled keypair symbols in a consistent - * way, but including this here fixes them if that wasn't the case. */ -#include "psa/crypto_adjust_config_key_pair_types.h" - -#endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ - -#if defined(PSA_WANT_ALG_JPAKE) -#define PSA_WANT_ALG_SOME_PAKE 1 -#endif - -#include "psa/crypto_adjust_auto_enabled.h" - -#endif /* MBEDTLS_CONFIG_PSA_H */ +/** + * \file mbedtls/config_psa.h + * \brief PSA crypto configuration options (set of defines) + * + * This set of compile-time options takes settings defined in + * include/mbedtls/mbedtls_config.h and include/psa/crypto_config.h and uses + * those definitions to define symbols used in the library code. + * + * Users and integrators should not edit this file, please edit + * include/mbedtls/mbedtls_config.h for MBEDTLS_XXX settings or + * include/psa/crypto_config.h for PSA_WANT_XXX settings. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_PSA_H +#define MBEDTLS_CONFIG_PSA_H + +#include "psa/crypto_legacy.h" + +#include "psa/crypto_adjust_config_synonyms.h" + +#include "mbedtls/config_adjust_psa_superset_legacy.h" + +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) + +/* Require built-in implementations based on PSA requirements */ + +/* We need this to have a complete list of requirements + * before we deduce what built-ins are required. */ +#include "psa/crypto_adjust_config_key_pair_types.h" + +#include "mbedtls/config_adjust_legacy_from_psa.h" + +#else /* MBEDTLS_PSA_CRYPTO_CONFIG */ + +/* Infer PSA requirements from Mbed TLS capabilities */ + +#include "mbedtls/config_adjust_psa_from_legacy.h" + +/* Hopefully the file above will have enabled keypair symbols in a consistent + * way, but including this here fixes them if that wasn't the case. */ +#include "psa/crypto_adjust_config_key_pair_types.h" + +#endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ + +#if defined(PSA_WANT_ALG_JPAKE) +#define PSA_WANT_ALG_SOME_PAKE 1 +#endif + +#include "psa/crypto_adjust_auto_enabled.h" + +#endif /* MBEDTLS_CONFIG_PSA_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/constant_time.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/constant_time.h index ebecf35..5e26d66 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/constant_time.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/constant_time.h @@ -1,48 +1,48 @@ -/** - * Constant-time functions - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONSTANT_TIME_H -#define MBEDTLS_CONSTANT_TIME_H - -#include - -/** Constant-time buffer comparison without branches. - * - * This is equivalent to the standard memcmp function, but is likely to be - * compiled to code using bitwise operations rather than a branch, such that - * the time taken is constant w.r.t. the data pointed to by \p a and \p b, - * and w.r.t. whether \p a and \p b are equal or not. It is not constant-time - * w.r.t. \p n . - * - * This function can be used to write constant-time code by replacing branches - * with bit operations using masks. - * - * \param a Pointer to the first buffer, containing at least \p n bytes. May not be NULL. - * \param b Pointer to the second buffer, containing at least \p n bytes. May not be NULL. - * \param n The number of bytes to compare. - * - * \return Zero if the contents of the two buffers are the same, - * otherwise non-zero. - */ -int mbedtls_ct_memcmp(const void *a, - const void *b, - size_t n); - -#endif /* MBEDTLS_CONSTANT_TIME_H */ +/** + * Constant-time functions + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONSTANT_TIME_H +#define MBEDTLS_CONSTANT_TIME_H + +#include + +/** Constant-time buffer comparison without branches. + * + * This is equivalent to the standard memcmp function, but is likely to be + * compiled to code using bitwise operations rather than a branch, such that + * the time taken is constant w.r.t. the data pointed to by \p a and \p b, + * and w.r.t. whether \p a and \p b are equal or not. It is not constant-time + * w.r.t. \p n . + * + * This function can be used to write constant-time code by replacing branches + * with bit operations using masks. + * + * \param a Pointer to the first buffer, containing at least \p n bytes. May not be NULL. + * \param b Pointer to the second buffer, containing at least \p n bytes. May not be NULL. + * \param n The number of bytes to compare. + * + * \return Zero if the contents of the two buffers are the same, + * otherwise non-zero. + */ +int mbedtls_ct_memcmp(const void *a, + const void *b, + size_t n); + +#endif /* MBEDTLS_CONSTANT_TIME_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ctr_drbg.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ctr_drbg.h index 0348281..2eab6b9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ctr_drbg.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ctr_drbg.h @@ -1,576 +1,576 @@ -/** - * \file ctr_drbg.h - * - * \brief This file contains definitions and functions for the - * CTR_DRBG pseudorandom generator. - * - * CTR_DRBG is a standardized way of building a PRNG from a block-cipher - * in counter mode operation, as defined in NIST SP 800-90A: - * Recommendation for Random Number Generation Using Deterministic Random - * Bit Generators. - * - * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128 - * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time) - * as the underlying block cipher, with a derivation function. - * - * The security strength as defined in NIST SP 800-90A is - * 128 bits when AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) - * and 256 bits otherwise, provided that #MBEDTLS_CTR_DRBG_ENTROPY_LEN is - * kept at its default value (and not overridden in mbedtls_config.h) and that the - * DRBG instance is set up with default parameters. - * See the documentation of mbedtls_ctr_drbg_seed() for more - * information. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CTR_DRBG_H -#define MBEDTLS_CTR_DRBG_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/aes.h" -#include "entropy.h" - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - -/** The entropy source failed. */ -#define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED -0x0034 -/** The requested random buffer length is too big. */ -#define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG -0x0036 -/** The input (entropy + additional data) is too large. */ -#define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG -0x0038 -/** Read or write error in file. */ -#define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR -0x003A - -#define MBEDTLS_CTR_DRBG_BLOCKSIZE 16 /**< The block size used by the cipher. */ - -#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) -#define MBEDTLS_CTR_DRBG_KEYSIZE 16 -/**< The key size in bytes used by the cipher. - * - * Compile-time choice: 16 bytes (128 bits) - * because #MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled. - */ -#else -#define MBEDTLS_CTR_DRBG_KEYSIZE 32 -/**< The key size in bytes used by the cipher. - * - * Compile-time choice: 32 bytes (256 bits) - * because \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled. - */ -#endif - -#define MBEDTLS_CTR_DRBG_KEYBITS (MBEDTLS_CTR_DRBG_KEYSIZE * 8) /**< The key size for the DRBG operation, in bits. */ -#define MBEDTLS_CTR_DRBG_SEEDLEN (MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE) /**< The seed length, calculated as (counter + AES key). */ - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them using the compiler command - * line. - * \{ - */ - -/** \def MBEDTLS_CTR_DRBG_ENTROPY_LEN - * - * \brief The amount of entropy used per seed by default, in bytes. - */ -#if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) -#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) -/** This is 48 bytes because the entropy module uses SHA-512. - */ -#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 - -#else /* MBEDTLS_ENTROPY_SHA512_ACCUMULATOR */ - -/** This is 32 bytes because the entropy module uses SHA-256. - */ -#if !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) -/** \warning To achieve a 256-bit security strength, you must pass a nonce - * to mbedtls_ctr_drbg_seed(). - */ -#endif /* !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) */ -#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 32 -#endif /* MBEDTLS_ENTROPY_SHA512_ACCUMULATOR */ -#endif /* !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) */ - -#if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL) -#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 -/**< The interval before reseed is performed by default. */ -#endif - -#if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT) -#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 -/**< The maximum number of additional input Bytes. */ -#endif - -#if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST) -#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 -/**< The maximum number of requested Bytes per call. */ -#endif - -#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) -#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 -/**< The maximum size of seed or reseed buffer in bytes. */ -#endif - -/** \} name SECTION: Module settings */ - -#define MBEDTLS_CTR_DRBG_PR_OFF 0 -/**< Prediction resistance is disabled. */ -#define MBEDTLS_CTR_DRBG_PR_ON 1 -/**< Prediction resistance is enabled. */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if MBEDTLS_CTR_DRBG_ENTROPY_LEN >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 -/** The default length of the nonce read from the entropy source. - * - * This is \c 0 because a single read from the entropy source is sufficient - * to include a nonce. - * See the documentation of mbedtls_ctr_drbg_seed() for more information. - */ -#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN 0 -#else -/** The default length of the nonce read from the entropy source. - * - * This is half of the default entropy length because a single read from - * the entropy source does not provide enough material to form a nonce. - * See the documentation of mbedtls_ctr_drbg_seed() for more information. - */ -#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN (MBEDTLS_CTR_DRBG_ENTROPY_LEN + 1) / 2 -#endif - -/** - * \brief The CTR_DRBG context structure. - */ -typedef struct mbedtls_ctr_drbg_context { - unsigned char MBEDTLS_PRIVATE(counter)[16]; /*!< The counter (V). */ - int MBEDTLS_PRIVATE(reseed_counter); /*!< The reseed counter. - * This is the number of requests that have - * been made since the last (re)seeding, - * minus one. - * Before the initial seeding, this field - * contains the amount of entropy in bytes - * to use as a nonce for the initial seeding, - * or -1 if no nonce length has been explicitly - * set (see mbedtls_ctr_drbg_set_nonce_len()). - */ - int MBEDTLS_PRIVATE(prediction_resistance); /*!< This determines whether prediction - resistance is enabled, that is - whether to systematically reseed before - each random generation. */ - size_t MBEDTLS_PRIVATE(entropy_len); /*!< The amount of entropy grabbed on each - seed or reseed operation, in bytes. */ - int MBEDTLS_PRIVATE(reseed_interval); /*!< The reseed interval. - * This is the maximum number of requests - * that can be made between reseedings. */ - - mbedtls_aes_context MBEDTLS_PRIVATE(aes_ctx); /*!< The AES context. */ - - /* - * Callbacks (Entropy) - */ - int(*MBEDTLS_PRIVATE(f_entropy))(void *, unsigned char *, size_t); - /*!< The entropy callback function. */ - - void *MBEDTLS_PRIVATE(p_entropy); /*!< The context for the entropy function. */ - -#if defined(MBEDTLS_THREADING_C) - /* Invariant: the mutex is initialized if and only if f_entropy != NULL. - * This means that the mutex is initialized during the initial seeding - * in mbedtls_ctr_drbg_seed() and freed in mbedtls_ctr_drbg_free(). - * - * Note that this invariant may change without notice. Do not rely on it - * and do not access the mutex directly in application code. - */ - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); -#endif -} -mbedtls_ctr_drbg_context; - -/** - * \brief This function initializes the CTR_DRBG context, - * and prepares it for mbedtls_ctr_drbg_seed() - * or mbedtls_ctr_drbg_free(). - * - * \note The reseed interval is - * #MBEDTLS_CTR_DRBG_RESEED_INTERVAL by default. - * You can override it by calling - * mbedtls_ctr_drbg_set_reseed_interval(). - * - * \param ctx The CTR_DRBG context to initialize. - */ -void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context *ctx); - -/** - * \brief This function seeds and sets up the CTR_DRBG - * entropy source for future reseeds. - * - * A typical choice for the \p f_entropy and \p p_entropy parameters is - * to use the entropy module: - * - \p f_entropy is mbedtls_entropy_func(); - * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized - * with mbedtls_entropy_init() (which registers the platform's default - * entropy sources). - * - * The entropy length is #MBEDTLS_CTR_DRBG_ENTROPY_LEN by default. - * You can override it by calling mbedtls_ctr_drbg_set_entropy_len(). - * - * The entropy nonce length is: - * - \c 0 if the entropy length is at least 3/2 times the entropy length, - * which guarantees that the security strength is the maximum permitted - * by the key size and entropy length according to NIST SP 800-90A §10.2.1; - * - Half the entropy length otherwise. - * You can override it by calling mbedtls_ctr_drbg_set_nonce_len(). - * With the default entropy length, the entropy nonce length is - * #MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN. - * - * You can provide a nonce and personalization string in addition to the - * entropy source, to make this instantiation as unique as possible. - * See SP 800-90A §8.6.7 for more details about nonces. - * - * The _seed_material_ value passed to the derivation function in - * the CTR_DRBG Instantiate Process described in NIST SP 800-90A §10.2.1.3.2 - * is the concatenation of the following strings: - * - A string obtained by calling \p f_entropy function for the entropy - * length. - */ -#if MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN == 0 -/** - * - If mbedtls_ctr_drbg_set_nonce_len() has been called, a string - * obtained by calling \p f_entropy function for the specified length. - */ -#else -/** - * - A string obtained by calling \p f_entropy function for the entropy nonce - * length. If the entropy nonce length is \c 0, this function does not - * make a second call to \p f_entropy. - */ -#endif -#if defined(MBEDTLS_THREADING_C) -/** - * \note When Mbed TLS is built with threading support, - * after this function returns successfully, - * it is safe to call mbedtls_ctr_drbg_random() - * from multiple threads. Other operations, including - * reseeding, are not thread-safe. - */ -#endif /* MBEDTLS_THREADING_C */ -/** - * - The \p custom string. - * - * \note To achieve the nominal security strength permitted - * by CTR_DRBG, the entropy length must be: - * - at least 16 bytes for a 128-bit strength - * (maximum achievable strength when using AES-128); - * - at least 32 bytes for a 256-bit strength - * (maximum achievable strength when using AES-256). - * - * In addition, if you do not pass a nonce in \p custom, - * the sum of the entropy length - * and the entropy nonce length must be: - * - at least 24 bytes for a 128-bit strength - * (maximum achievable strength when using AES-128); - * - at least 48 bytes for a 256-bit strength - * (maximum achievable strength when using AES-256). - * - * \param ctx The CTR_DRBG context to seed. - * It must have been initialized with - * mbedtls_ctr_drbg_init(). - * After a successful call to mbedtls_ctr_drbg_seed(), - * you may not call mbedtls_ctr_drbg_seed() again on - * the same context unless you call - * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() - * again first. - * After a failed call to mbedtls_ctr_drbg_seed(), - * you must call mbedtls_ctr_drbg_free(). - * \param f_entropy The entropy callback, taking as arguments the - * \p p_entropy context, the buffer to fill, and the - * length of the buffer. - * \p f_entropy is always called with a buffer size - * less than or equal to the entropy length. - * \param p_entropy The entropy context to pass to \p f_entropy. - * \param custom The personalization string. - * This can be \c NULL, in which case the personalization - * string is empty regardless of the value of \p len. - * \param len The length of the personalization string. - * This must be at most - * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - * - #MBEDTLS_CTR_DRBG_ENTROPY_LEN. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. - */ -int mbedtls_ctr_drbg_seed(mbedtls_ctr_drbg_context *ctx, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len); - -/** - * \brief This function resets CTR_DRBG context to the state immediately - * after initial call of mbedtls_ctr_drbg_init(). - * - * \param ctx The CTR_DRBG context to clear. - */ -void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context *ctx); - -/** - * \brief This function turns prediction resistance on or off. - * The default value is off. - * - * \note If enabled, entropy is gathered at the beginning of - * every call to mbedtls_ctr_drbg_random_with_add() - * or mbedtls_ctr_drbg_random(). - * Only use this if your entropy source has sufficient - * throughput. - * - * \param ctx The CTR_DRBG context. - * \param resistance #MBEDTLS_CTR_DRBG_PR_ON or #MBEDTLS_CTR_DRBG_PR_OFF. - */ -void mbedtls_ctr_drbg_set_prediction_resistance(mbedtls_ctr_drbg_context *ctx, - int resistance); - -/** - * \brief This function sets the amount of entropy grabbed on each - * seed or reseed. - * - * The default value is #MBEDTLS_CTR_DRBG_ENTROPY_LEN. - * - * \note The security strength of CTR_DRBG is bounded by the - * entropy length. Thus: - * - When using AES-256 - * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled, - * which is the default), - * \p len must be at least 32 (in bytes) - * to achieve a 256-bit strength. - * - When using AES-128 - * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled) - * \p len must be at least 16 (in bytes) - * to achieve a 128-bit strength. - * - * \param ctx The CTR_DRBG context. - * \param len The amount of entropy to grab, in bytes. - * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - * and at most the maximum length accepted by the - * entropy function that is set in the context. - */ -void mbedtls_ctr_drbg_set_entropy_len(mbedtls_ctr_drbg_context *ctx, - size_t len); - -/** - * \brief This function sets the amount of entropy grabbed - * as a nonce for the initial seeding. - * - * Call this function before calling mbedtls_ctr_drbg_seed() to read - * a nonce from the entropy source during the initial seeding. - * - * \param ctx The CTR_DRBG context. - * \param len The amount of entropy to grab for the nonce, in bytes. - * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - * and at most the maximum length accepted by the - * entropy function that is set in the context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if \p len is - * more than #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED - * if the initial seeding has already taken place. - */ -int mbedtls_ctr_drbg_set_nonce_len(mbedtls_ctr_drbg_context *ctx, - size_t len); - -/** - * \brief This function sets the reseed interval. - * - * The reseed interval is the number of calls to mbedtls_ctr_drbg_random() - * or mbedtls_ctr_drbg_random_with_add() after which the entropy function - * is called again. - * - * The default value is #MBEDTLS_CTR_DRBG_RESEED_INTERVAL. - * - * \param ctx The CTR_DRBG context. - * \param interval The reseed interval. - */ -void mbedtls_ctr_drbg_set_reseed_interval(mbedtls_ctr_drbg_context *ctx, - int interval); - -/** - * \brief This function reseeds the CTR_DRBG context, that is - * extracts data from the entropy source. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param ctx The CTR_DRBG context. - * \param additional Additional data to add to the state. Can be \c NULL. - * \param len The length of the additional data. - * This must be less than - * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len - * where \c entropy_len is the entropy length - * configured for the context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. - */ -int mbedtls_ctr_drbg_reseed(mbedtls_ctr_drbg_context *ctx, - const unsigned char *additional, size_t len); - -/** - * \brief This function updates the state of the CTR_DRBG context. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param ctx The CTR_DRBG context. - * \param additional The data to update the state with. This must not be - * \c NULL unless \p add_len is \c 0. - * \param add_len Length of \p additional in bytes. This must be at - * most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if - * \p add_len is more than - * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. - * \return An error from the underlying AES cipher on failure. - */ -int mbedtls_ctr_drbg_update(mbedtls_ctr_drbg_context *ctx, - const unsigned char *additional, - size_t add_len); - -/** - * \brief This function updates a CTR_DRBG instance with additional - * data and uses it to generate random data. - * - * This function automatically reseeds if the reseed counter is exceeded - * or prediction resistance is enabled. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param p_rng The CTR_DRBG context. This must be a pointer to a - * #mbedtls_ctr_drbg_context structure. - * \param output The buffer to fill. - * \param output_len The length of the buffer in bytes. - * \param additional Additional data to update. Can be \c NULL, in which - * case the additional data is empty regardless of - * the value of \p add_len. - * \param add_len The length of the additional data - * if \p additional is not \c NULL. - * This must be less than #MBEDTLS_CTR_DRBG_MAX_INPUT - * and less than - * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len - * where \c entropy_len is the entropy length - * configured for the context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or - * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. - */ -int mbedtls_ctr_drbg_random_with_add(void *p_rng, - unsigned char *output, size_t output_len, - const unsigned char *additional, size_t add_len); - -/** - * \brief This function uses CTR_DRBG to generate random data. - * - * This function automatically reseeds if the reseed counter is exceeded - * or prediction resistance is enabled. - */ -#if defined(MBEDTLS_THREADING_C) -/** - * \note When Mbed TLS is built with threading support, - * it is safe to call mbedtls_ctr_drbg_random() - * from multiple threads. Other operations, including - * reseeding, are not thread-safe. - */ -#endif /* MBEDTLS_THREADING_C */ -/** - * \param p_rng The CTR_DRBG context. This must be a pointer to a - * #mbedtls_ctr_drbg_context structure. - * \param output The buffer to fill. - * \param output_len The length of the buffer in bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or - * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. - */ -int mbedtls_ctr_drbg_random(void *p_rng, - unsigned char *output, size_t output_len); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief This function writes a seed file. - * - * \param ctx The CTR_DRBG context. - * \param path The name of the file. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on reseed - * failure. - */ -int mbedtls_ctr_drbg_write_seed_file(mbedtls_ctr_drbg_context *ctx, const char *path); - -/** - * \brief This function reads and updates a seed file. The seed - * is added to this instance. - * - * \param ctx The CTR_DRBG context. - * \param path The name of the file. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. - * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on - * reseed failure. - * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if the existing - * seed file is too large. - */ -int mbedtls_ctr_drbg_update_seed_file(mbedtls_ctr_drbg_context *ctx, const char *path); -#endif /* MBEDTLS_FS_IO */ - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The CTR_DRBG checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_ctr_drbg_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* ctr_drbg.h */ +/** + * \file ctr_drbg.h + * + * \brief This file contains definitions and functions for the + * CTR_DRBG pseudorandom generator. + * + * CTR_DRBG is a standardized way of building a PRNG from a block-cipher + * in counter mode operation, as defined in NIST SP 800-90A: + * Recommendation for Random Number Generation Using Deterministic Random + * Bit Generators. + * + * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128 + * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time) + * as the underlying block cipher, with a derivation function. + * + * The security strength as defined in NIST SP 800-90A is + * 128 bits when AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) + * and 256 bits otherwise, provided that #MBEDTLS_CTR_DRBG_ENTROPY_LEN is + * kept at its default value (and not overridden in mbedtls_config.h) and that the + * DRBG instance is set up with default parameters. + * See the documentation of mbedtls_ctr_drbg_seed() for more + * information. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CTR_DRBG_H +#define MBEDTLS_CTR_DRBG_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/aes.h" +#include "entropy.h" + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +/** The entropy source failed. */ +#define MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED -0x0034 +/** The requested random buffer length is too big. */ +#define MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG -0x0036 +/** The input (entropy + additional data) is too large. */ +#define MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG -0x0038 +/** Read or write error in file. */ +#define MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR -0x003A + +#define MBEDTLS_CTR_DRBG_BLOCKSIZE 16 /**< The block size used by the cipher. */ + +#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +#define MBEDTLS_CTR_DRBG_KEYSIZE 16 +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 16 bytes (128 bits) + * because #MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled. + */ +#else +#define MBEDTLS_CTR_DRBG_KEYSIZE 32 +/**< The key size in bytes used by the cipher. + * + * Compile-time choice: 32 bytes (256 bits) + * because \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled. + */ +#endif + +#define MBEDTLS_CTR_DRBG_KEYBITS (MBEDTLS_CTR_DRBG_KEYSIZE * 8) /**< The key size for the DRBG operation, in bits. */ +#define MBEDTLS_CTR_DRBG_SEEDLEN (MBEDTLS_CTR_DRBG_KEYSIZE + MBEDTLS_CTR_DRBG_BLOCKSIZE) /**< The seed length, calculated as (counter + AES key). */ + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them using the compiler command + * line. + * \{ + */ + +/** \def MBEDTLS_CTR_DRBG_ENTROPY_LEN + * + * \brief The amount of entropy used per seed by default, in bytes. + */ +#if !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) +#if defined(MBEDTLS_ENTROPY_SHA512_ACCUMULATOR) +/** This is 48 bytes because the entropy module uses SHA-512. + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 + +#else /* MBEDTLS_ENTROPY_SHA512_ACCUMULATOR */ + +/** This is 32 bytes because the entropy module uses SHA-256. + */ +#if !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +/** \warning To achieve a 256-bit security strength, you must pass a nonce + * to mbedtls_ctr_drbg_seed(). + */ +#endif /* !defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) */ +#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 32 +#endif /* MBEDTLS_ENTROPY_SHA512_ACCUMULATOR */ +#endif /* !defined(MBEDTLS_CTR_DRBG_ENTROPY_LEN) */ + +#if !defined(MBEDTLS_CTR_DRBG_RESEED_INTERVAL) +#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 +/**< The interval before reseed is performed by default. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_INPUT) +#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 +/**< The maximum number of additional input Bytes. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_REQUEST) +#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 +/**< The maximum number of requested Bytes per call. */ +#endif + +#if !defined(MBEDTLS_CTR_DRBG_MAX_SEED_INPUT) +#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 +/**< The maximum size of seed or reseed buffer in bytes. */ +#endif + +/** \} name SECTION: Module settings */ + +#define MBEDTLS_CTR_DRBG_PR_OFF 0 +/**< Prediction resistance is disabled. */ +#define MBEDTLS_CTR_DRBG_PR_ON 1 +/**< Prediction resistance is enabled. */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if MBEDTLS_CTR_DRBG_ENTROPY_LEN >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 +/** The default length of the nonce read from the entropy source. + * + * This is \c 0 because a single read from the entropy source is sufficient + * to include a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN 0 +#else +/** The default length of the nonce read from the entropy source. + * + * This is half of the default entropy length because a single read from + * the entropy source does not provide enough material to form a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN (MBEDTLS_CTR_DRBG_ENTROPY_LEN + 1) / 2 +#endif + +/** + * \brief The CTR_DRBG context structure. + */ +typedef struct mbedtls_ctr_drbg_context { + unsigned char MBEDTLS_PRIVATE(counter)[16]; /*!< The counter (V). */ + int MBEDTLS_PRIVATE(reseed_counter); /*!< The reseed counter. + * This is the number of requests that have + * been made since the last (re)seeding, + * minus one. + * Before the initial seeding, this field + * contains the amount of entropy in bytes + * to use as a nonce for the initial seeding, + * or -1 if no nonce length has been explicitly + * set (see mbedtls_ctr_drbg_set_nonce_len()). + */ + int MBEDTLS_PRIVATE(prediction_resistance); /*!< This determines whether prediction + resistance is enabled, that is + whether to systematically reseed before + each random generation. */ + size_t MBEDTLS_PRIVATE(entropy_len); /*!< The amount of entropy grabbed on each + seed or reseed operation, in bytes. */ + int MBEDTLS_PRIVATE(reseed_interval); /*!< The reseed interval. + * This is the maximum number of requests + * that can be made between reseedings. */ + + mbedtls_aes_context MBEDTLS_PRIVATE(aes_ctx); /*!< The AES context. */ + + /* + * Callbacks (Entropy) + */ + int(*MBEDTLS_PRIVATE(f_entropy))(void *, unsigned char *, size_t); + /*!< The entropy callback function. */ + + void *MBEDTLS_PRIVATE(p_entropy); /*!< The context for the entropy function. */ + +#if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized if and only if f_entropy != NULL. + * This means that the mutex is initialized during the initial seeding + * in mbedtls_ctr_drbg_seed() and freed in mbedtls_ctr_drbg_free(). + * + * Note that this invariant may change without notice. Do not rely on it + * and do not access the mutex directly in application code. + */ + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); +#endif +} +mbedtls_ctr_drbg_context; + +/** + * \brief This function initializes the CTR_DRBG context, + * and prepares it for mbedtls_ctr_drbg_seed() + * or mbedtls_ctr_drbg_free(). + * + * \note The reseed interval is + * #MBEDTLS_CTR_DRBG_RESEED_INTERVAL by default. + * You can override it by calling + * mbedtls_ctr_drbg_set_reseed_interval(). + * + * \param ctx The CTR_DRBG context to initialize. + */ +void mbedtls_ctr_drbg_init(mbedtls_ctr_drbg_context *ctx); + +/** + * \brief This function seeds and sets up the CTR_DRBG + * entropy source for future reseeds. + * + * A typical choice for the \p f_entropy and \p p_entropy parameters is + * to use the entropy module: + * - \p f_entropy is mbedtls_entropy_func(); + * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized + * with mbedtls_entropy_init() (which registers the platform's default + * entropy sources). + * + * The entropy length is #MBEDTLS_CTR_DRBG_ENTROPY_LEN by default. + * You can override it by calling mbedtls_ctr_drbg_set_entropy_len(). + * + * The entropy nonce length is: + * - \c 0 if the entropy length is at least 3/2 times the entropy length, + * which guarantees that the security strength is the maximum permitted + * by the key size and entropy length according to NIST SP 800-90A §10.2.1; + * - Half the entropy length otherwise. + * You can override it by calling mbedtls_ctr_drbg_set_nonce_len(). + * With the default entropy length, the entropy nonce length is + * #MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN. + * + * You can provide a nonce and personalization string in addition to the + * entropy source, to make this instantiation as unique as possible. + * See SP 800-90A §8.6.7 for more details about nonces. + * + * The _seed_material_ value passed to the derivation function in + * the CTR_DRBG Instantiate Process described in NIST SP 800-90A §10.2.1.3.2 + * is the concatenation of the following strings: + * - A string obtained by calling \p f_entropy function for the entropy + * length. + */ +#if MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN == 0 +/** + * - If mbedtls_ctr_drbg_set_nonce_len() has been called, a string + * obtained by calling \p f_entropy function for the specified length. + */ +#else +/** + * - A string obtained by calling \p f_entropy function for the entropy nonce + * length. If the entropy nonce length is \c 0, this function does not + * make a second call to \p f_entropy. + */ +#endif +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * - The \p custom string. + * + * \note To achieve the nominal security strength permitted + * by CTR_DRBG, the entropy length must be: + * - at least 16 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 32 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * + * In addition, if you do not pass a nonce in \p custom, + * the sum of the entropy length + * and the entropy nonce length must be: + * - at least 24 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 48 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * + * \param ctx The CTR_DRBG context to seed. + * It must have been initialized with + * mbedtls_ctr_drbg_init(). + * After a successful call to mbedtls_ctr_drbg_seed(), + * you may not call mbedtls_ctr_drbg_seed() again on + * the same context unless you call + * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() + * again first. + * After a failed call to mbedtls_ctr_drbg_seed(), + * you must call mbedtls_ctr_drbg_free(). + * \param f_entropy The entropy callback, taking as arguments the + * \p p_entropy context, the buffer to fill, and the + * length of the buffer. + * \p f_entropy is always called with a buffer size + * less than or equal to the entropy length. + * \param p_entropy The entropy context to pass to \p f_entropy. + * \param custom The personalization string. + * This can be \c NULL, in which case the personalization + * string is empty regardless of the value of \p len. + * \param len The length of the personalization string. + * This must be at most + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * - #MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_seed(mbedtls_ctr_drbg_context *ctx, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len); + +/** + * \brief This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). + * + * \param ctx The CTR_DRBG context to clear. + */ +void mbedtls_ctr_drbg_free(mbedtls_ctr_drbg_context *ctx); + +/** + * \brief This function turns prediction resistance on or off. + * The default value is off. + * + * \note If enabled, entropy is gathered at the beginning of + * every call to mbedtls_ctr_drbg_random_with_add() + * or mbedtls_ctr_drbg_random(). + * Only use this if your entropy source has sufficient + * throughput. + * + * \param ctx The CTR_DRBG context. + * \param resistance #MBEDTLS_CTR_DRBG_PR_ON or #MBEDTLS_CTR_DRBG_PR_OFF. + */ +void mbedtls_ctr_drbg_set_prediction_resistance(mbedtls_ctr_drbg_context *ctx, + int resistance); + +/** + * \brief This function sets the amount of entropy grabbed on each + * seed or reseed. + * + * The default value is #MBEDTLS_CTR_DRBG_ENTROPY_LEN. + * + * \note The security strength of CTR_DRBG is bounded by the + * entropy length. Thus: + * - When using AES-256 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is disabled, + * which is the default), + * \p len must be at least 32 (in bytes) + * to achieve a 256-bit strength. + * - When using AES-128 + * (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled) + * \p len must be at least 16 (in bytes) + * to achieve a 128-bit strength. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab, in bytes. + * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. + */ +void mbedtls_ctr_drbg_set_entropy_len(mbedtls_ctr_drbg_context *ctx, + size_t len); + +/** + * \brief This function sets the amount of entropy grabbed + * as a nonce for the initial seeding. + * + * Call this function before calling mbedtls_ctr_drbg_seed() to read + * a nonce from the entropy source during the initial seeding. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab for the nonce, in bytes. + * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if \p len is + * more than #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED + * if the initial seeding has already taken place. + */ +int mbedtls_ctr_drbg_set_nonce_len(mbedtls_ctr_drbg_context *ctx, + size_t len); + +/** + * \brief This function sets the reseed interval. + * + * The reseed interval is the number of calls to mbedtls_ctr_drbg_random() + * or mbedtls_ctr_drbg_random_with_add() after which the entropy function + * is called again. + * + * The default value is #MBEDTLS_CTR_DRBG_RESEED_INTERVAL. + * + * \param ctx The CTR_DRBG context. + * \param interval The reseed interval. + */ +void mbedtls_ctr_drbg_set_reseed_interval(mbedtls_ctr_drbg_context *ctx, + int interval); + +/** + * \brief This function reseeds the CTR_DRBG context, that is + * extracts data from the entropy source. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The CTR_DRBG context. + * \param additional Additional data to add to the state. Can be \c NULL. + * \param len The length of the additional data. + * This must be less than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on failure. + */ +int mbedtls_ctr_drbg_reseed(mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, size_t len); + +/** + * \brief This function updates the state of the CTR_DRBG context. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The CTR_DRBG context. + * \param additional The data to update the state with. This must not be + * \c NULL unless \p add_len is \c 0. + * \param add_len Length of \p additional in bytes. This must be at + * most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if + * \p add_len is more than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return An error from the underlying AES cipher on failure. + */ +int mbedtls_ctr_drbg_update(mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t add_len); + +/** + * \brief This function updates a CTR_DRBG instance with additional + * data and uses it to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * \param additional Additional data to update. Can be \c NULL, in which + * case the additional data is empty regardless of + * the value of \p add_len. + * \param add_len The length of the additional data + * if \p additional is not \c NULL. + * This must be less than #MBEDTLS_CTR_DRBG_MAX_INPUT + * and less than + * #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * configured for the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random_with_add(void *p_rng, + unsigned char *output, size_t output_len, + const unsigned char *additional, size_t add_len); + +/** + * \brief This function uses CTR_DRBG to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param p_rng The CTR_DRBG context. This must be a pointer to a + * #mbedtls_ctr_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED or + * #MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG on failure. + */ +int mbedtls_ctr_drbg_random(void *p_rng, + unsigned char *output, size_t output_len); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function writes a seed file. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on reseed + * failure. + */ +int mbedtls_ctr_drbg_write_seed_file(mbedtls_ctr_drbg_context *ctx, const char *path); + +/** + * \brief This function reads and updates a seed file. The seed + * is added to this instance. + * + * \param ctx The CTR_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED on + * reseed failure. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if the existing + * seed file is too large. + */ +int mbedtls_ctr_drbg_update_seed_file(mbedtls_ctr_drbg_context *ctx, const char *path); +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The CTR_DRBG checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ctr_drbg_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* ctr_drbg.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/debug.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/debug.h index d6dd152..d6e46e8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/debug.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/debug.h @@ -1,320 +1,320 @@ -/** - * \file debug.h - * - * \brief Functions for controlling and providing debug output from the library. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_DEBUG_H -#define MBEDTLS_DEBUG_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/ssl.h" - -#if defined(MBEDTLS_ECP_C) -#include "mbedtls/ecp.h" -#endif - -#if defined(MBEDTLS_DEBUG_C) - -#define MBEDTLS_DEBUG_STRIP_PARENS(...) __VA_ARGS__ - -#define MBEDTLS_SSL_DEBUG_MSG(level, args) \ - mbedtls_debug_print_msg(ssl, level, __FILE__, __LINE__, \ - MBEDTLS_DEBUG_STRIP_PARENS args) - -#define MBEDTLS_SSL_DEBUG_RET(level, text, ret) \ - mbedtls_debug_print_ret(ssl, level, __FILE__, __LINE__, text, ret) - -#define MBEDTLS_SSL_DEBUG_BUF(level, text, buf, len) \ - mbedtls_debug_print_buf(ssl, level, __FILE__, __LINE__, text, buf, len) - -#if defined(MBEDTLS_BIGNUM_C) -#define MBEDTLS_SSL_DEBUG_MPI(level, text, X) \ - mbedtls_debug_print_mpi(ssl, level, __FILE__, __LINE__, text, X) -#endif - -#if defined(MBEDTLS_ECP_C) -#define MBEDTLS_SSL_DEBUG_ECP(level, text, X) \ - mbedtls_debug_print_ecp(ssl, level, __FILE__, __LINE__, text, X) -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -#if !defined(MBEDTLS_X509_REMOVE_INFO) -#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) \ - mbedtls_debug_print_crt(ssl, level, __FILE__, __LINE__, text, crt) -#else -#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) do { } while (0) -#endif /* MBEDTLS_X509_REMOVE_INFO */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_ECDH_C) -#define MBEDTLS_SSL_DEBUG_ECDH(level, ecdh, attr) \ - mbedtls_debug_printf_ecdh(ssl, level, __FILE__, __LINE__, ecdh, attr) -#endif - -#else /* MBEDTLS_DEBUG_C */ - -#define MBEDTLS_SSL_DEBUG_MSG(level, args) do { } while (0) -#define MBEDTLS_SSL_DEBUG_RET(level, text, ret) do { } while (0) -#define MBEDTLS_SSL_DEBUG_BUF(level, text, buf, len) do { } while (0) -#define MBEDTLS_SSL_DEBUG_MPI(level, text, X) do { } while (0) -#define MBEDTLS_SSL_DEBUG_ECP(level, text, X) do { } while (0) -#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) do { } while (0) -#define MBEDTLS_SSL_DEBUG_ECDH(level, ecdh, attr) do { } while (0) - -#endif /* MBEDTLS_DEBUG_C */ - -/** - * \def MBEDTLS_PRINTF_ATTRIBUTE - * - * Mark a function as having printf attributes, and thus enable checking - * via -wFormat and other flags. This does nothing on builds with compilers - * that do not support the format attribute - * - * Module: library/debug.c - * Caller: - * - * This module provides debugging functions. - */ -#if defined(__has_attribute) -#if __has_attribute(format) -#if defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 1 -#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) \ - __attribute__((__format__(gnu_printf, string_index, first_to_check))) -#else /* defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 1 */ -#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) \ - __attribute__((format(printf, string_index, first_to_check))) -#endif -#else /* __has_attribute(format) */ -#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) -#endif /* __has_attribute(format) */ -#else /* defined(__has_attribute) */ -#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) -#endif - -/** - * \def MBEDTLS_PRINTF_SIZET - * - * MBEDTLS_PRINTF_xxx: Due to issues with older window compilers - * and MinGW we need to define the printf specifier for size_t - * and long long per platform. - * - * Module: library/debug.c - * Caller: - * - * This module provides debugging functions. - */ -#if (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) - #include - #define MBEDTLS_PRINTF_SIZET PRIuPTR - #define MBEDTLS_PRINTF_LONGLONG "I64d" -#else \ - /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ - #define MBEDTLS_PRINTF_SIZET "zu" - #define MBEDTLS_PRINTF_LONGLONG "lld" -#endif \ - /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ - -#if !defined(MBEDTLS_PRINTF_MS_TIME) -#define MBEDTLS_PRINTF_MS_TIME PRId64 -#endif /* MBEDTLS_PRINTF_MS_TIME */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set the threshold error level to handle globally all debug output. - * Debug messages that have a level over the threshold value are - * discarded. - * (Default value: 0 = No debug ) - * - * \param threshold threshold level of messages to filter on. Messages at a - * higher level will be discarded. - * - Debug levels - * - 0 No debug - * - 1 Error - * - 2 State change - * - 3 Informational - * - 4 Verbose - */ -void mbedtls_debug_set_threshold(int threshold); - -/** - * \brief Print a message to the debug output. This function is always used - * through the MBEDTLS_SSL_DEBUG_MSG() macro, which supplies the ssl - * context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the message has occurred in - * \param line line number the message has occurred at - * \param format format specifier, in printf format - * \param ... variables used by the format specifier - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_msg(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const char *format, ...) MBEDTLS_PRINTF_ATTRIBUTE(5, 6); - -/** - * \brief Print the return value of a function to the debug output. This - * function is always used through the MBEDTLS_SSL_DEBUG_RET() macro, - * which supplies the ssl context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param text the name of the function that returned the error - * \param ret the return code value - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_ret(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const char *text, int ret); - -/** - * \brief Output a buffer of size len bytes to the debug output. This function - * is always used through the MBEDTLS_SSL_DEBUG_BUF() macro, - * which supplies the ssl context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param text a name or label for the buffer being dumped. Normally the - * variable or buffer name - * \param buf the buffer to be outputted - * \param len length of the buffer - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_buf(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, const char *text, - const unsigned char *buf, size_t len); - -#if defined(MBEDTLS_BIGNUM_C) -/** - * \brief Print a MPI variable to the debug output. This function is always - * used through the MBEDTLS_SSL_DEBUG_MPI() macro, which supplies the - * ssl context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param text a name or label for the MPI being output. Normally the - * variable name - * \param X the MPI variable - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_mpi(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const char *text, const mbedtls_mpi *X); -#endif - -#if defined(MBEDTLS_ECP_C) -/** - * \brief Print an ECP point to the debug output. This function is always - * used through the MBEDTLS_SSL_DEBUG_ECP() macro, which supplies the - * ssl context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param text a name or label for the ECP point being output. Normally the - * variable name - * \param X the ECP point - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_ecp(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const char *text, const mbedtls_ecp_point *X); -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_INFO) -/** - * \brief Print a X.509 certificate structure to the debug output. This - * function is always used through the MBEDTLS_SSL_DEBUG_CRT() macro, - * which supplies the ssl context, file and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param text a name or label for the certificate being output - * \param crt X.509 certificate structure - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_print_crt(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const char *text, const mbedtls_x509_crt *crt); -#endif - -/* Note: the MBEDTLS_ECDH_C guard here is mandatory because this debug function - only works for the built-in implementation. */ -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) && \ - defined(MBEDTLS_ECDH_C) -typedef enum { - MBEDTLS_DEBUG_ECDH_Q, - MBEDTLS_DEBUG_ECDH_QP, - MBEDTLS_DEBUG_ECDH_Z, -} mbedtls_debug_ecdh_attr; - -/** - * \brief Print a field of the ECDH structure in the SSL context to the debug - * output. This function is always used through the - * MBEDTLS_SSL_DEBUG_ECDH() macro, which supplies the ssl context, file - * and line number parameters. - * - * \param ssl SSL context - * \param level error level of the debug message - * \param file file the error has occurred in - * \param line line number the error has occurred in - * \param ecdh the ECDH context - * \param attr the identifier of the attribute being output - * - * \attention This function is intended for INTERNAL usage within the - * library only. - */ -void mbedtls_debug_printf_ecdh(const mbedtls_ssl_context *ssl, int level, - const char *file, int line, - const mbedtls_ecdh_context *ecdh, - mbedtls_debug_ecdh_attr attr); -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED && - MBEDTLS_ECDH_C */ - -#ifdef __cplusplus -} -#endif - -#endif /* debug.h */ +/** + * \file debug.h + * + * \brief Functions for controlling and providing debug output from the library. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_DEBUG_H +#define MBEDTLS_DEBUG_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/ssl.h" + +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif + +#if defined(MBEDTLS_DEBUG_C) + +#define MBEDTLS_DEBUG_STRIP_PARENS(...) __VA_ARGS__ + +#define MBEDTLS_SSL_DEBUG_MSG(level, args) \ + mbedtls_debug_print_msg(ssl, level, __FILE__, __LINE__, \ + MBEDTLS_DEBUG_STRIP_PARENS args) + +#define MBEDTLS_SSL_DEBUG_RET(level, text, ret) \ + mbedtls_debug_print_ret(ssl, level, __FILE__, __LINE__, text, ret) + +#define MBEDTLS_SSL_DEBUG_BUF(level, text, buf, len) \ + mbedtls_debug_print_buf(ssl, level, __FILE__, __LINE__, text, buf, len) + +#if defined(MBEDTLS_BIGNUM_C) +#define MBEDTLS_SSL_DEBUG_MPI(level, text, X) \ + mbedtls_debug_print_mpi(ssl, level, __FILE__, __LINE__, text, X) +#endif + +#if defined(MBEDTLS_ECP_C) +#define MBEDTLS_SSL_DEBUG_ECP(level, text, X) \ + mbedtls_debug_print_ecp(ssl, level, __FILE__, __LINE__, text, X) +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +#if !defined(MBEDTLS_X509_REMOVE_INFO) +#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) \ + mbedtls_debug_print_crt(ssl, level, __FILE__, __LINE__, text, crt) +#else +#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) do { } while (0) +#endif /* MBEDTLS_X509_REMOVE_INFO */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_ECDH_C) +#define MBEDTLS_SSL_DEBUG_ECDH(level, ecdh, attr) \ + mbedtls_debug_printf_ecdh(ssl, level, __FILE__, __LINE__, ecdh, attr) +#endif + +#else /* MBEDTLS_DEBUG_C */ + +#define MBEDTLS_SSL_DEBUG_MSG(level, args) do { } while (0) +#define MBEDTLS_SSL_DEBUG_RET(level, text, ret) do { } while (0) +#define MBEDTLS_SSL_DEBUG_BUF(level, text, buf, len) do { } while (0) +#define MBEDTLS_SSL_DEBUG_MPI(level, text, X) do { } while (0) +#define MBEDTLS_SSL_DEBUG_ECP(level, text, X) do { } while (0) +#define MBEDTLS_SSL_DEBUG_CRT(level, text, crt) do { } while (0) +#define MBEDTLS_SSL_DEBUG_ECDH(level, ecdh, attr) do { } while (0) + +#endif /* MBEDTLS_DEBUG_C */ + +/** + * \def MBEDTLS_PRINTF_ATTRIBUTE + * + * Mark a function as having printf attributes, and thus enable checking + * via -wFormat and other flags. This does nothing on builds with compilers + * that do not support the format attribute + * + * Module: library/debug.c + * Caller: + * + * This module provides debugging functions. + */ +#if defined(__has_attribute) +#if __has_attribute(format) +#if defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 1 +#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) \ + __attribute__((__format__(gnu_printf, string_index, first_to_check))) +#else /* defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 1 */ +#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) \ + __attribute__((format(printf, string_index, first_to_check))) +#endif +#else /* __has_attribute(format) */ +#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) +#endif /* __has_attribute(format) */ +#else /* defined(__has_attribute) */ +#define MBEDTLS_PRINTF_ATTRIBUTE(string_index, first_to_check) +#endif + +/** + * \def MBEDTLS_PRINTF_SIZET + * + * MBEDTLS_PRINTF_xxx: Due to issues with older window compilers + * and MinGW we need to define the printf specifier for size_t + * and long long per platform. + * + * Module: library/debug.c + * Caller: + * + * This module provides debugging functions. + */ +#if (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) + #include + #define MBEDTLS_PRINTF_SIZET PRIuPTR + #define MBEDTLS_PRINTF_LONGLONG "I64d" +#else \ + /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ + #define MBEDTLS_PRINTF_SIZET "zu" + #define MBEDTLS_PRINTF_LONGLONG "lld" +#endif \ + /* (defined(__MINGW32__) && __USE_MINGW_ANSI_STDIO == 0) || (defined(_MSC_VER) && _MSC_VER < 1800) */ + +#if !defined(MBEDTLS_PRINTF_MS_TIME) +#define MBEDTLS_PRINTF_MS_TIME PRId64 +#endif /* MBEDTLS_PRINTF_MS_TIME */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set the threshold error level to handle globally all debug output. + * Debug messages that have a level over the threshold value are + * discarded. + * (Default value: 0 = No debug ) + * + * \param threshold threshold level of messages to filter on. Messages at a + * higher level will be discarded. + * - Debug levels + * - 0 No debug + * - 1 Error + * - 2 State change + * - 3 Informational + * - 4 Verbose + */ +void mbedtls_debug_set_threshold(int threshold); + +/** + * \brief Print a message to the debug output. This function is always used + * through the MBEDTLS_SSL_DEBUG_MSG() macro, which supplies the ssl + * context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the message has occurred in + * \param line line number the message has occurred at + * \param format format specifier, in printf format + * \param ... variables used by the format specifier + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_msg(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const char *format, ...) MBEDTLS_PRINTF_ATTRIBUTE(5, 6); + +/** + * \brief Print the return value of a function to the debug output. This + * function is always used through the MBEDTLS_SSL_DEBUG_RET() macro, + * which supplies the ssl context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param text the name of the function that returned the error + * \param ret the return code value + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_ret(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const char *text, int ret); + +/** + * \brief Output a buffer of size len bytes to the debug output. This function + * is always used through the MBEDTLS_SSL_DEBUG_BUF() macro, + * which supplies the ssl context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param text a name or label for the buffer being dumped. Normally the + * variable or buffer name + * \param buf the buffer to be outputted + * \param len length of the buffer + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_buf(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, const char *text, + const unsigned char *buf, size_t len); + +#if defined(MBEDTLS_BIGNUM_C) +/** + * \brief Print a MPI variable to the debug output. This function is always + * used through the MBEDTLS_SSL_DEBUG_MPI() macro, which supplies the + * ssl context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param text a name or label for the MPI being output. Normally the + * variable name + * \param X the MPI variable + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_mpi(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const char *text, const mbedtls_mpi *X); +#endif + +#if defined(MBEDTLS_ECP_C) +/** + * \brief Print an ECP point to the debug output. This function is always + * used through the MBEDTLS_SSL_DEBUG_ECP() macro, which supplies the + * ssl context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param text a name or label for the ECP point being output. Normally the + * variable name + * \param X the ECP point + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_ecp(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const char *text, const mbedtls_ecp_point *X); +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_INFO) +/** + * \brief Print a X.509 certificate structure to the debug output. This + * function is always used through the MBEDTLS_SSL_DEBUG_CRT() macro, + * which supplies the ssl context, file and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param text a name or label for the certificate being output + * \param crt X.509 certificate structure + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_print_crt(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const char *text, const mbedtls_x509_crt *crt); +#endif + +/* Note: the MBEDTLS_ECDH_C guard here is mandatory because this debug function + only works for the built-in implementation. */ +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) && \ + defined(MBEDTLS_ECDH_C) +typedef enum { + MBEDTLS_DEBUG_ECDH_Q, + MBEDTLS_DEBUG_ECDH_QP, + MBEDTLS_DEBUG_ECDH_Z, +} mbedtls_debug_ecdh_attr; + +/** + * \brief Print a field of the ECDH structure in the SSL context to the debug + * output. This function is always used through the + * MBEDTLS_SSL_DEBUG_ECDH() macro, which supplies the ssl context, file + * and line number parameters. + * + * \param ssl SSL context + * \param level error level of the debug message + * \param file file the error has occurred in + * \param line line number the error has occurred in + * \param ecdh the ECDH context + * \param attr the identifier of the attribute being output + * + * \attention This function is intended for INTERNAL usage within the + * library only. + */ +void mbedtls_debug_printf_ecdh(const mbedtls_ssl_context *ssl, int level, + const char *file, int line, + const mbedtls_ecdh_context *ecdh, + mbedtls_debug_ecdh_attr attr); +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED && + MBEDTLS_ECDH_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* debug.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/des.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/des.h index f445102..e0b8e10 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/des.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/des.h @@ -1,397 +1,397 @@ -/** - * \file des.h - * - * \brief DES block cipher - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ -#ifndef MBEDTLS_DES_H -#define MBEDTLS_DES_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" -#include "mbedtls/platform_util.h" - -#include -#include - -#define MBEDTLS_DES_ENCRYPT 1 -#define MBEDTLS_DES_DECRYPT 0 - -/** The data input has an invalid length. */ -#define MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH -0x0032 - -#define MBEDTLS_DES_KEY_SIZE 8 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_DES_ALT) -// Regular implementation -// - -/** - * \brief DES context structure - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -typedef struct mbedtls_des_context { - uint32_t MBEDTLS_PRIVATE(sk)[32]; /*!< DES subkeys */ -} -mbedtls_des_context; - -/** - * \brief Triple-DES context structure - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -typedef struct mbedtls_des3_context { - uint32_t MBEDTLS_PRIVATE(sk)[96]; /*!< 3DES subkeys */ -} -mbedtls_des3_context; - -#else /* MBEDTLS_DES_ALT */ -#include "des_alt.h" -#endif /* MBEDTLS_DES_ALT */ - -/** - * \brief Initialize DES context - * - * \param ctx DES context to be initialized - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des_init(mbedtls_des_context *ctx); - -/** - * \brief Clear DES context - * - * \param ctx DES context to be cleared - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des_free(mbedtls_des_context *ctx); - -/** - * \brief Initialize Triple-DES context - * - * \param ctx DES3 context to be initialized - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des3_init(mbedtls_des3_context *ctx); - -/** - * \brief Clear Triple-DES context - * - * \param ctx DES3 context to be cleared - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des3_free(mbedtls_des3_context *ctx); - -/** - * \brief Set key parity on the given key to odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -/** - * \brief Check that key parity on the given key is odd. - * - * DES keys are 56 bits long, but each byte is padded with - * a parity bit to allow verification. - * - * \param key 8-byte secret key - * - * \return 0 is parity was ok, 1 if parity was not correct. - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_key_check_key_parity(const unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -/** - * \brief Check that key is not a weak or semi-weak DES key - * - * \param key 8-byte secret key - * - * \return 0 if no weak key was found, 1 if a weak key was identified. - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_key_check_weak(const unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -/** - * \brief DES key schedule (56-bit, encryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_setkey_enc(mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -/** - * \brief DES key schedule (56-bit, decryption) - * - * \param ctx DES context to be initialized - * \param key 8-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_setkey_dec(mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -/** - * \brief Triple-DES key schedule (112-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_set2key_enc(mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2]); - -/** - * \brief Triple-DES key schedule (112-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 16-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_set2key_dec(mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2]); - -/** - * \brief Triple-DES key schedule (168-bit, encryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_set3key_enc(mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3]); - -/** - * \brief Triple-DES key schedule (168-bit, decryption) - * - * \param ctx 3DES context to be initialized - * \param key 24-byte secret key - * - * \return 0 - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_set3key_dec(mbedtls_des3_context *ctx, - const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3]); - -/** - * \brief DES-ECB block encryption/decryption - * - * \param ctx DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_crypt_ecb(mbedtls_des_context *ctx, - const unsigned char input[8], - unsigned char output[8]); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des_crypt_cbc(mbedtls_des_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief 3DES-ECB block encryption/decryption - * - * \param ctx 3DES context - * \param input 64-bit input block - * \param output 64-bit output block - * - * \return 0 if successful - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_crypt_ecb(mbedtls_des3_context *ctx, - const unsigned char input[8], - unsigned char output[8]); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -/** - * \brief 3DES-CBC buffer encryption/decryption - * - * \note Upon exit, the content of the IV is updated so that you can - * call the function same function again on the following - * block(s) of data and get the same result as if it was - * encrypted in one call. This allows a "streaming" usage. - * If on the other hand you need to retain the contents of the - * IV, you should either save it manually or use the cipher - * module instead. - * - * \param ctx 3DES context - * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_des3_crypt_cbc(mbedtls_des3_context *ctx, - int mode, - size_t length, - unsigned char iv[8], - const unsigned char *input, - unsigned char *output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -/** - * \brief Internal function for key expansion. - * (Only exposed to allow overriding it, - * see MBEDTLS_DES_SETKEY_ALT) - * - * \param SK Round keys - * \param key Base key - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers - * instead. - */ -void mbedtls_des_setkey(uint32_t SK[32], - const unsigned char key[MBEDTLS_DES_KEY_SIZE]); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_des_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* des.h */ +/** + * \file des.h + * + * \brief DES block cipher + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#ifndef MBEDTLS_DES_H +#define MBEDTLS_DES_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" +#include "mbedtls/platform_util.h" + +#include +#include + +#define MBEDTLS_DES_ENCRYPT 1 +#define MBEDTLS_DES_DECRYPT 0 + +/** The data input has an invalid length. */ +#define MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH -0x0032 + +#define MBEDTLS_DES_KEY_SIZE 8 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_DES_ALT) +// Regular implementation +// + +/** + * \brief DES context structure + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +typedef struct mbedtls_des_context { + uint32_t MBEDTLS_PRIVATE(sk)[32]; /*!< DES subkeys */ +} +mbedtls_des_context; + +/** + * \brief Triple-DES context structure + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +typedef struct mbedtls_des3_context { + uint32_t MBEDTLS_PRIVATE(sk)[96]; /*!< 3DES subkeys */ +} +mbedtls_des3_context; + +#else /* MBEDTLS_DES_ALT */ +#include "des_alt.h" +#endif /* MBEDTLS_DES_ALT */ + +/** + * \brief Initialize DES context + * + * \param ctx DES context to be initialized + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_init(mbedtls_des_context *ctx); + +/** + * \brief Clear DES context + * + * \param ctx DES context to be cleared + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_free(mbedtls_des_context *ctx); + +/** + * \brief Initialize Triple-DES context + * + * \param ctx DES3 context to be initialized + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des3_init(mbedtls_des3_context *ctx); + +/** + * \brief Clear Triple-DES context + * + * \param ctx DES3 context to be cleared + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des3_free(mbedtls_des3_context *ctx); + +/** + * \brief Set key parity on the given key to odd. + * + * DES keys are 56 bits long, but each byte is padded with + * a parity bit to allow verification. + * + * \param key 8-byte secret key + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_key_set_parity(unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +/** + * \brief Check that key parity on the given key is odd. + * + * DES keys are 56 bits long, but each byte is padded with + * a parity bit to allow verification. + * + * \param key 8-byte secret key + * + * \return 0 is parity was ok, 1 if parity was not correct. + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_key_check_key_parity(const unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +/** + * \brief Check that key is not a weak or semi-weak DES key + * + * \param key 8-byte secret key + * + * \return 0 if no weak key was found, 1 if a weak key was identified. + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_key_check_weak(const unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +/** + * \brief DES key schedule (56-bit, encryption) + * + * \param ctx DES context to be initialized + * \param key 8-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_setkey_enc(mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +/** + * \brief DES key schedule (56-bit, decryption) + * + * \param ctx DES context to be initialized + * \param key 8-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_setkey_dec(mbedtls_des_context *ctx, const unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +/** + * \brief Triple-DES key schedule (112-bit, encryption) + * + * \param ctx 3DES context to be initialized + * \param key 16-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_set2key_enc(mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2]); + +/** + * \brief Triple-DES key schedule (112-bit, decryption) + * + * \param ctx 3DES context to be initialized + * \param key 16-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_set2key_dec(mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 2]); + +/** + * \brief Triple-DES key schedule (168-bit, encryption) + * + * \param ctx 3DES context to be initialized + * \param key 24-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_set3key_enc(mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3]); + +/** + * \brief Triple-DES key schedule (168-bit, decryption) + * + * \param ctx 3DES context to be initialized + * \param key 24-byte secret key + * + * \return 0 + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_set3key_dec(mbedtls_des3_context *ctx, + const unsigned char key[MBEDTLS_DES_KEY_SIZE * 3]); + +/** + * \brief DES-ECB block encryption/decryption + * + * \param ctx DES context + * \param input 64-bit input block + * \param output 64-bit output block + * + * \return 0 if successful + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_crypt_ecb(mbedtls_des_context *ctx, + const unsigned char input[8], + unsigned char output[8]); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief DES-CBC buffer encryption/decryption + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx DES context + * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des_crypt_cbc(mbedtls_des_context *ctx, + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +/** + * \brief 3DES-ECB block encryption/decryption + * + * \param ctx 3DES context + * \param input 64-bit input block + * \param output 64-bit output block + * + * \return 0 if successful + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_crypt_ecb(mbedtls_des3_context *ctx, + const unsigned char input[8], + unsigned char output[8]); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief 3DES-CBC buffer encryption/decryption + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx 3DES context + * \param mode MBEDTLS_DES_ENCRYPT or MBEDTLS_DES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_des3_crypt_cbc(mbedtls_des3_context *ctx, + int mode, + size_t length, + unsigned char iv[8], + const unsigned char *input, + unsigned char *output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +/** + * \brief Internal function for key expansion. + * (Only exposed to allow overriding it, + * see MBEDTLS_DES_SETKEY_ALT) + * + * \param SK Round keys + * \param key Base key + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers + * instead. + */ +void mbedtls_des_setkey(uint32_t SK[32], + const unsigned char key[MBEDTLS_DES_KEY_SIZE]); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_des_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* des.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/dhm.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/dhm.h index 0232a71..7599946 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/dhm.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/dhm.h @@ -1,984 +1,984 @@ -/** - * \file dhm.h - * - * \brief This file contains Diffie-Hellman-Merkle (DHM) key exchange - * definitions and functions. - * - * Diffie-Hellman-Merkle (DHM) key exchange is defined in - * RFC-2631: Diffie-Hellman Key Agreement Method and - * Public-Key Cryptography Standards (PKCS) #3: Diffie - * Hellman Key Agreement Standard. - * - * RFC-3526: More Modular Exponential (MODP) Diffie-Hellman groups for - * Internet Key Exchange (IKE) defines a number of standardized - * Diffie-Hellman groups for IKE. - * - * RFC-5114: Additional Diffie-Hellman Groups for Use with IETF - * Standards defines a number of standardized Diffie-Hellman - * groups that can be used. - * - * \warning The security of the DHM key exchange relies on the proper choice - * of prime modulus - optimally, it should be a safe prime. The usage - * of non-safe primes both decreases the difficulty of the underlying - * discrete logarithm problem and can lead to small subgroup attacks - * leaking private exponent bits when invalid public keys are used - * and not detected. This is especially relevant if the same DHM - * parameters are reused for multiple key exchanges as in static DHM, - * while the criticality of small-subgroup attacks is lower for - * ephemeral DHM. - * - * \warning For performance reasons, the code does neither perform primality - * nor safe primality tests, nor the expensive checks for invalid - * subgroups. Moreover, even if these were performed, non-standardized - * primes cannot be trusted because of the possibility of backdoors - * that can't be effectively checked for. - * - * \warning Diffie-Hellman-Merkle is therefore a security risk when not using - * standardized primes generated using a trustworthy ("nothing up - * my sleeve") method, such as the RFC 3526 / 7919 primes. In the TLS - * protocol, DH parameters need to be negotiated, so using the default - * primes systematically is not always an option. If possible, use - * Elliptic Curve Diffie-Hellman (ECDH), which has better performance, - * and for which the TLS protocol mandates the use of standard - * parameters. - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_DHM_H -#define MBEDTLS_DHM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" -#include "mbedtls/bignum.h" - -/* - * DHM Error codes - */ -/** Bad input parameters. */ -#define MBEDTLS_ERR_DHM_BAD_INPUT_DATA -0x3080 -/** Reading of the DHM parameters failed. */ -#define MBEDTLS_ERR_DHM_READ_PARAMS_FAILED -0x3100 -/** Making of the DHM parameters failed. */ -#define MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED -0x3180 -/** Reading of the public values failed. */ -#define MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED -0x3200 -/** Making of the public value failed. */ -#define MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED -0x3280 -/** Calculation of the DHM secret failed. */ -#define MBEDTLS_ERR_DHM_CALC_SECRET_FAILED -0x3300 -/** The ASN.1 data is not formatted correctly. */ -#define MBEDTLS_ERR_DHM_INVALID_FORMAT -0x3380 -/** Allocation of memory failed. */ -#define MBEDTLS_ERR_DHM_ALLOC_FAILED -0x3400 -/** Read or write of file failed. */ -#define MBEDTLS_ERR_DHM_FILE_IO_ERROR -0x3480 -/** Setting the modulus and generator failed. */ -#define MBEDTLS_ERR_DHM_SET_GROUP_FAILED -0x3580 - -/** Which parameter to access in mbedtls_dhm_get_value(). */ -typedef enum { - MBEDTLS_DHM_PARAM_P, /*!< The prime modulus. */ - MBEDTLS_DHM_PARAM_G, /*!< The generator. */ - MBEDTLS_DHM_PARAM_X, /*!< Our secret value. */ - MBEDTLS_DHM_PARAM_GX, /*!< Our public key = \c G^X mod \c P. */ - MBEDTLS_DHM_PARAM_GY, /*!< The public key of the peer = \c G^Y mod \c P. */ - MBEDTLS_DHM_PARAM_K, /*!< The shared secret = \c G^(XY) mod \c P. */ -} mbedtls_dhm_parameter; - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_DHM_ALT) - -/** - * \brief The DHM context structure. - */ -typedef struct mbedtls_dhm_context { - mbedtls_mpi MBEDTLS_PRIVATE(P); /*!< The prime modulus. */ - mbedtls_mpi MBEDTLS_PRIVATE(G); /*!< The generator. */ - mbedtls_mpi MBEDTLS_PRIVATE(X); /*!< Our secret value. */ - mbedtls_mpi MBEDTLS_PRIVATE(GX); /*!< Our public key = \c G^X mod \c P. */ - mbedtls_mpi MBEDTLS_PRIVATE(GY); /*!< The public key of the peer = \c G^Y mod \c P. */ - mbedtls_mpi MBEDTLS_PRIVATE(K); /*!< The shared secret = \c G^(XY) mod \c P. */ - mbedtls_mpi MBEDTLS_PRIVATE(RP); /*!< The cached value = \c R^2 mod \c P. */ - mbedtls_mpi MBEDTLS_PRIVATE(Vi); /*!< The blinding value. */ - mbedtls_mpi MBEDTLS_PRIVATE(Vf); /*!< The unblinding value. */ - mbedtls_mpi MBEDTLS_PRIVATE(pX); /*!< The previous \c X. */ -} -mbedtls_dhm_context; - -#else /* MBEDTLS_DHM_ALT */ -#include "dhm_alt.h" -#endif /* MBEDTLS_DHM_ALT */ - -/** - * \brief This function initializes the DHM context. - * - * \param ctx The DHM context to initialize. - */ -void mbedtls_dhm_init(mbedtls_dhm_context *ctx); - -/** - * \brief This function parses the DHM parameters in a - * TLS ServerKeyExchange handshake message - * (DHM modulus, generator, and public key). - * - * \note In a TLS handshake, this is the how the client - * sets up its DHM context from the server's public - * DHM key material. - * - * \param ctx The DHM context to use. This must be initialized. - * \param p On input, *p must be the start of the input buffer. - * On output, *p is updated to point to the end of the data - * that has been read. On success, this is the first byte - * past the end of the ServerKeyExchange parameters. - * On error, this is the point at which an error has been - * detected, which is usually not useful except to debug - * failures. - * \param end The end of the input buffer. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_read_params(mbedtls_dhm_context *ctx, - unsigned char **p, - const unsigned char *end); - -/** - * \brief This function generates a DHM key pair and exports its - * public part together with the DHM parameters in the format - * used in a TLS ServerKeyExchange handshake message. - * - * \note This function assumes that the DHM parameters \c ctx->P - * and \c ctx->G have already been properly set. For that, use - * mbedtls_dhm_set_group() below in conjunction with - * mbedtls_mpi_read_binary() and mbedtls_mpi_read_string(). - * - * \note In a TLS handshake, this is the how the server generates - * and exports its DHM key material. - * - * \param ctx The DHM context to use. This must be initialized - * and have the DHM parameters set. It may or may not - * already have imported the peer's public key. - * \param x_size The private key size in Bytes. - * \param olen The address at which to store the number of Bytes - * written on success. This must not be \c NULL. - * \param output The destination buffer. This must be a writable buffer of - * sufficient size to hold the reduced binary presentation of - * the modulus, the generator and the public key, each wrapped - * with a 2-byte length field. It is the responsibility of the - * caller to ensure that enough space is available. Refer to - * mbedtls_mpi_size() to computing the byte-size of an MPI. - * \param f_rng The RNG function. Must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context parameter. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_make_params(mbedtls_dhm_context *ctx, int x_size, - unsigned char *output, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function sets the prime modulus and generator. - * - * \note This function can be used to set \c ctx->P, \c ctx->G - * in preparation for mbedtls_dhm_make_params(). - * - * \param ctx The DHM context to configure. This must be initialized. - * \param P The MPI holding the DHM prime modulus. This must be - * an initialized MPI. - * \param G The MPI holding the DHM generator. This must be an - * initialized MPI. - * - * \return \c 0 if successful. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_set_group(mbedtls_dhm_context *ctx, - const mbedtls_mpi *P, - const mbedtls_mpi *G); - -/** - * \brief This function imports the raw public value of the peer. - * - * \note In a TLS handshake, this is the how the server imports - * the Client's public DHM key. - * - * \param ctx The DHM context to use. This must be initialized and have - * its DHM parameters set, e.g. via mbedtls_dhm_set_group(). - * It may or may not already have generated its own private key. - * \param input The input buffer containing the \c G^Y value of the peer. - * This must be a readable buffer of size \p ilen Bytes. - * \param ilen The size of the input buffer \p input in Bytes. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_read_public(mbedtls_dhm_context *ctx, - const unsigned char *input, size_t ilen); - -/** - * \brief This function creates a DHM key pair and exports - * the raw public key in big-endian format. - * - * \note The destination buffer is always fully written - * so as to contain a big-endian representation of G^X mod P. - * If it is larger than \c ctx->len, it is padded accordingly - * with zero-bytes at the beginning. - * - * \param ctx The DHM context to use. This must be initialized and - * have the DHM parameters set. It may or may not already - * have imported the peer's public key. - * \param x_size The private key size in Bytes. - * \param output The destination buffer. This must be a writable buffer of - * size \p olen Bytes. - * \param olen The length of the destination buffer. This must be at least - * equal to `ctx->len` (the size of \c P). - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_make_public(mbedtls_dhm_context *ctx, int x_size, - unsigned char *output, size_t olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function derives and exports the shared secret - * \c (G^Y)^X mod \c P. - * - * \note If \p f_rng is not \c NULL, it is used to blind the input as - * a countermeasure against timing attacks. Blinding is used - * only if our private key \c X is re-used, and not used - * otherwise. We recommend always passing a non-NULL - * \p f_rng argument. - * - * \param ctx The DHM context to use. This must be initialized - * and have its own private key generated and the peer's - * public key imported. - * \param output The buffer to write the generated shared key to. This - * must be a writable buffer of size \p output_size Bytes. - * \param output_size The size of the destination buffer. This must be at - * least the size of \c ctx->len (the size of \c P). - * \param olen On exit, holds the actual number of Bytes written. - * \param f_rng The RNG function. Must not be \c NULL. Used for - * blinding. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context parameter. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. - */ -int mbedtls_dhm_calc_secret(mbedtls_dhm_context *ctx, - unsigned char *output, size_t output_size, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function returns the size of the prime modulus in bits. - * - * \param ctx The DHM context to query. - * - * \return The size of the prime modulus in bits, - * i.e. the number n such that 2^(n-1) <= P < 2^n. - */ -size_t mbedtls_dhm_get_bitlen(const mbedtls_dhm_context *ctx); - -/** - * \brief This function returns the size of the prime modulus in bytes. - * - * \param ctx The DHM context to query. - * - * \return The size of the prime modulus in bytes, - * i.e. the number n such that 2^(8*(n-1)) <= P < 2^(8*n). - */ -size_t mbedtls_dhm_get_len(const mbedtls_dhm_context *ctx); - -/** - * \brief This function copies a parameter of a DHM key. - * - * \param ctx The DHM context to query. - * \param param The parameter to copy. - * \param dest The MPI object to copy the value into. It must be - * initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_DHM_BAD_INPUT_DATA if \p param is invalid. - * \return An \c MBEDTLS_ERR_MPI_XXX error code if the copy fails. - */ -int mbedtls_dhm_get_value(const mbedtls_dhm_context *ctx, - mbedtls_dhm_parameter param, - mbedtls_mpi *dest); - -/** - * \brief This function frees and clears the components - * of a DHM context. - * - * \param ctx The DHM context to free and clear. This may be \c NULL, - * in which case this function is a no-op. If it is not \c NULL, - * it must point to an initialized DHM context. - */ -void mbedtls_dhm_free(mbedtls_dhm_context *ctx); - -#if defined(MBEDTLS_ASN1_PARSE_C) -/** - * \brief This function parses DHM parameters in PEM or DER format. - * - * \param dhm The DHM context to import the DHM parameters into. - * This must be initialized. - * \param dhmin The input buffer. This must be a readable buffer of - * length \p dhminlen Bytes. - * \param dhminlen The size of the input buffer \p dhmin, including the - * terminating \c NULL Byte for PEM data. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX error - * code on failure. - */ -int mbedtls_dhm_parse_dhm(mbedtls_dhm_context *dhm, const unsigned char *dhmin, - size_t dhminlen); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief This function loads and parses DHM parameters from a file. - * - * \param dhm The DHM context to load the parameters to. - * This must be initialized. - * \param path The filename to read the DHM parameters from. - * This must not be \c NULL. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX - * error code on failure. - */ -int mbedtls_dhm_parse_dhmfile(mbedtls_dhm_context *dhm, const char *path); -#endif /* MBEDTLS_FS_IO */ -#endif /* MBEDTLS_ASN1_PARSE_C */ - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The DMH checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_dhm_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ -#ifdef __cplusplus -} -#endif - -/** - * RFC 3526, RFC 5114 and RFC 7919 standardize a number of - * Diffie-Hellman groups, some of which are included here - * for use within the SSL/TLS module and the user's convenience - * when configuring the Diffie-Hellman parameters by hand - * through \c mbedtls_ssl_conf_dh_param. - * - * The following lists the source of the above groups in the standards: - * - RFC 5114 section 2.2: 2048-bit MODP Group with 224-bit Prime Order Subgroup - * - RFC 3526 section 3: 2048-bit MODP Group - * - RFC 3526 section 4: 3072-bit MODP Group - * - RFC 3526 section 5: 4096-bit MODP Group - * - RFC 7919 section A.1: ffdhe2048 - * - RFC 7919 section A.2: ffdhe3072 - * - RFC 7919 section A.3: ffdhe4096 - * - RFC 7919 section A.4: ffdhe6144 - * - RFC 7919 section A.5: ffdhe8192 - * - * The constants with suffix "_p" denote the chosen prime moduli, while - * the constants with suffix "_g" denote the chosen generator - * of the associated prime field. - * - * The constants further suffixed with "_bin" are provided in binary format, - * while all other constants represent null-terminated strings holding the - * hexadecimal presentation of the respective numbers. - * - * The primes from RFC 3526 and RFC 7919 have been generating by the following - * trust-worthy procedure: - * - Fix N in { 2048, 3072, 4096, 6144, 8192 } and consider the N-bit number - * the first and last 64 bits are all 1, and the remaining N - 128 bits of - * which are 0x7ff...ff. - * - Add the smallest multiple of the first N - 129 bits of the binary expansion - * of pi (for RFC 5236) or e (for RFC 7919) to this intermediate bit-string - * such that the resulting integer is a safe-prime. - * - The result is the respective RFC 3526 / 7919 prime, and the corresponding - * generator is always chosen to be 2 (which is a square for these prime, - * hence the corresponding subgroup has order (p-1)/2 and avoids leaking a - * bit in the private exponent). - * - */ - -/* - * Trustworthy DHM parameters in binary form - */ - -#define MBEDTLS_DHM_RFC3526_MODP_2048_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ - 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ - 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ - 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ - 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ - 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ - 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ - 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ - 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ - 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ - 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ - 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ - 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ - 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ - 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ - 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ - 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ - 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ - 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ - 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ - 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ - 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ - 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ - 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ - 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ - 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ - 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ - 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ - 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ - 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAC, 0xAA, 0x68, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC3526_MODP_2048_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC3526_MODP_3072_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ - 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ - 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ - 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ - 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ - 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ - 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ - 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ - 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ - 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ - 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ - 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ - 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ - 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ - 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ - 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ - 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ - 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ - 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ - 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ - 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ - 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ - 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ - 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ - 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ - 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ - 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ - 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ - 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ - 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D, \ - 0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33, \ - 0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64, \ - 0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A, \ - 0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D, \ - 0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7, \ - 0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7, \ - 0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D, \ - 0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B, \ - 0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64, \ - 0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64, \ - 0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C, \ - 0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C, \ - 0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2, \ - 0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31, \ - 0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E, \ - 0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x3A, 0xD2, 0xCA, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC3526_MODP_3072_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC3526_MODP_4096_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ - 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ - 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ - 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ - 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ - 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ - 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ - 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ - 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ - 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ - 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ - 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ - 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ - 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ - 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ - 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ - 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ - 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ - 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ - 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ - 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ - 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ - 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ - 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ - 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ - 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ - 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ - 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ - 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ - 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D, \ - 0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33, \ - 0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64, \ - 0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A, \ - 0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D, \ - 0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7, \ - 0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7, \ - 0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D, \ - 0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B, \ - 0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64, \ - 0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64, \ - 0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C, \ - 0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C, \ - 0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2, \ - 0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31, \ - 0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E, \ - 0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x21, 0x08, 0x01, \ - 0x1A, 0x72, 0x3C, 0x12, 0xA7, 0x87, 0xE6, 0xD7, \ - 0x88, 0x71, 0x9A, 0x10, 0xBD, 0xBA, 0x5B, 0x26, \ - 0x99, 0xC3, 0x27, 0x18, 0x6A, 0xF4, 0xE2, 0x3C, \ - 0x1A, 0x94, 0x68, 0x34, 0xB6, 0x15, 0x0B, 0xDA, \ - 0x25, 0x83, 0xE9, 0xCA, 0x2A, 0xD4, 0x4C, 0xE8, \ - 0xDB, 0xBB, 0xC2, 0xDB, 0x04, 0xDE, 0x8E, 0xF9, \ - 0x2E, 0x8E, 0xFC, 0x14, 0x1F, 0xBE, 0xCA, 0xA6, \ - 0x28, 0x7C, 0x59, 0x47, 0x4E, 0x6B, 0xC0, 0x5D, \ - 0x99, 0xB2, 0x96, 0x4F, 0xA0, 0x90, 0xC3, 0xA2, \ - 0x23, 0x3B, 0xA1, 0x86, 0x51, 0x5B, 0xE7, 0xED, \ - 0x1F, 0x61, 0x29, 0x70, 0xCE, 0xE2, 0xD7, 0xAF, \ - 0xB8, 0x1B, 0xDD, 0x76, 0x21, 0x70, 0x48, 0x1C, \ - 0xD0, 0x06, 0x91, 0x27, 0xD5, 0xB0, 0x5A, 0xA9, \ - 0x93, 0xB4, 0xEA, 0x98, 0x8D, 0x8F, 0xDD, 0xC1, \ - 0x86, 0xFF, 0xB7, 0xDC, 0x90, 0xA6, 0xC0, 0x8F, \ - 0x4D, 0xF4, 0x35, 0xC9, 0x34, 0x06, 0x31, 0x99, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC3526_MODP_4096_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC7919_FFDHE2048_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ - 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ - 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ - 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ - 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ - 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ - 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ - 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ - 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ - 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ - 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ - 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ - 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ - 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ - 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ - 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ - 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ - 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ - 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ - 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ - 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ - 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ - 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ - 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ - 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ - 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ - 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ - 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ - 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ - 0x88, 0x6B, 0x42, 0x38, 0x61, 0x28, 0x5C, 0x97, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, } - -#define MBEDTLS_DHM_RFC7919_FFDHE2048_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC7919_FFDHE3072_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ - 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ - 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ - 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ - 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ - 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ - 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ - 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ - 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ - 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ - 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ - 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ - 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ - 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ - 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ - 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ - 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ - 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ - 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ - 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ - 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ - 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ - 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ - 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ - 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ - 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ - 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ - 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ - 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ - 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ - 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ - 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ - 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ - 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ - 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ - 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ - 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ - 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ - 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ - 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ - 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ - 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ - 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ - 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ - 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ - 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0xC6, 0x2E, 0x37, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC7919_FFDHE3072_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC7919_FFDHE4096_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ - 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ - 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ - 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ - 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ - 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ - 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ - 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ - 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ - 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ - 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ - 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ - 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ - 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ - 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ - 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ - 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ - 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ - 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ - 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ - 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ - 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ - 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ - 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ - 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ - 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ - 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ - 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ - 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ - 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ - 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ - 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ - 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ - 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ - 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ - 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ - 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ - 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ - 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ - 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ - 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ - 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ - 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ - 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ - 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ - 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ - 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ - 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ - 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ - 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ - 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ - 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ - 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ - 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ - 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ - 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ - 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ - 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ - 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ - 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ - 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ - 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x65, 0x5F, 0x6A, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC7919_FFDHE4096_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC7919_FFDHE6144_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ - 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ - 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ - 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ - 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ - 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ - 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ - 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ - 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ - 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ - 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ - 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ - 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ - 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ - 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ - 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ - 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ - 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ - 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ - 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ - 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ - 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ - 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ - 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ - 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ - 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ - 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ - 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ - 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ - 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ - 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ - 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ - 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ - 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ - 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ - 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ - 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ - 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ - 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ - 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ - 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ - 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ - 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ - 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ - 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ - 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ - 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ - 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ - 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ - 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ - 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ - 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ - 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ - 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ - 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ - 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ - 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ - 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ - 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ - 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ - 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ - 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \ - 0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \ - 0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \ - 0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \ - 0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \ - 0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \ - 0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \ - 0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \ - 0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \ - 0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \ - 0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \ - 0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \ - 0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \ - 0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \ - 0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \ - 0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \ - 0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \ - 0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \ - 0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \ - 0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \ - 0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \ - 0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \ - 0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \ - 0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \ - 0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \ - 0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \ - 0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \ - 0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \ - 0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \ - 0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \ - 0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \ - 0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \ - 0xA4, 0x0E, 0x32, 0x9C, 0xD0, 0xE4, 0x0E, 0x65, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC7919_FFDHE6144_G_BIN { 0x02 } - -#define MBEDTLS_DHM_RFC7919_FFDHE8192_P_BIN { \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ - 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ - 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ - 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ - 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ - 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ - 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ - 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ - 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ - 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ - 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ - 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ - 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ - 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ - 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ - 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ - 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ - 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ - 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ - 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ - 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ - 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ - 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ - 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ - 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ - 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ - 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ - 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ - 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ - 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ - 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ - 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ - 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ - 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ - 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ - 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ - 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ - 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ - 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ - 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ - 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ - 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ - 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ - 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ - 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ - 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ - 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ - 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ - 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ - 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ - 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ - 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ - 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ - 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ - 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ - 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ - 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ - 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ - 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ - 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ - 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ - 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \ - 0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \ - 0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \ - 0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \ - 0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \ - 0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \ - 0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \ - 0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \ - 0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \ - 0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \ - 0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \ - 0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \ - 0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \ - 0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \ - 0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \ - 0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \ - 0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \ - 0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \ - 0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \ - 0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \ - 0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \ - 0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \ - 0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \ - 0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \ - 0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \ - 0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \ - 0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \ - 0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \ - 0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \ - 0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \ - 0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \ - 0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \ - 0xA4, 0x0E, 0x32, 0x9C, 0xCF, 0xF4, 0x6A, 0xAA, \ - 0x36, 0xAD, 0x00, 0x4C, 0xF6, 0x00, 0xC8, 0x38, \ - 0x1E, 0x42, 0x5A, 0x31, 0xD9, 0x51, 0xAE, 0x64, \ - 0xFD, 0xB2, 0x3F, 0xCE, 0xC9, 0x50, 0x9D, 0x43, \ - 0x68, 0x7F, 0xEB, 0x69, 0xED, 0xD1, 0xCC, 0x5E, \ - 0x0B, 0x8C, 0xC3, 0xBD, 0xF6, 0x4B, 0x10, 0xEF, \ - 0x86, 0xB6, 0x31, 0x42, 0xA3, 0xAB, 0x88, 0x29, \ - 0x55, 0x5B, 0x2F, 0x74, 0x7C, 0x93, 0x26, 0x65, \ - 0xCB, 0x2C, 0x0F, 0x1C, 0xC0, 0x1B, 0xD7, 0x02, \ - 0x29, 0x38, 0x88, 0x39, 0xD2, 0xAF, 0x05, 0xE4, \ - 0x54, 0x50, 0x4A, 0xC7, 0x8B, 0x75, 0x82, 0x82, \ - 0x28, 0x46, 0xC0, 0xBA, 0x35, 0xC3, 0x5F, 0x5C, \ - 0x59, 0x16, 0x0C, 0xC0, 0x46, 0xFD, 0x82, 0x51, \ - 0x54, 0x1F, 0xC6, 0x8C, 0x9C, 0x86, 0xB0, 0x22, \ - 0xBB, 0x70, 0x99, 0x87, 0x6A, 0x46, 0x0E, 0x74, \ - 0x51, 0xA8, 0xA9, 0x31, 0x09, 0x70, 0x3F, 0xEE, \ - 0x1C, 0x21, 0x7E, 0x6C, 0x38, 0x26, 0xE5, 0x2C, \ - 0x51, 0xAA, 0x69, 0x1E, 0x0E, 0x42, 0x3C, 0xFC, \ - 0x99, 0xE9, 0xE3, 0x16, 0x50, 0xC1, 0x21, 0x7B, \ - 0x62, 0x48, 0x16, 0xCD, 0xAD, 0x9A, 0x95, 0xF9, \ - 0xD5, 0xB8, 0x01, 0x94, 0x88, 0xD9, 0xC0, 0xA0, \ - 0xA1, 0xFE, 0x30, 0x75, 0xA5, 0x77, 0xE2, 0x31, \ - 0x83, 0xF8, 0x1D, 0x4A, 0x3F, 0x2F, 0xA4, 0x57, \ - 0x1E, 0xFC, 0x8C, 0xE0, 0xBA, 0x8A, 0x4F, 0xE8, \ - 0xB6, 0x85, 0x5D, 0xFE, 0x72, 0xB0, 0xA6, 0x6E, \ - 0xDE, 0xD2, 0xFB, 0xAB, 0xFB, 0xE5, 0x8A, 0x30, \ - 0xFA, 0xFA, 0xBE, 0x1C, 0x5D, 0x71, 0xA8, 0x7E, \ - 0x2F, 0x74, 0x1E, 0xF8, 0xC1, 0xFE, 0x86, 0xFE, \ - 0xA6, 0xBB, 0xFD, 0xE5, 0x30, 0x67, 0x7F, 0x0D, \ - 0x97, 0xD1, 0x1D, 0x49, 0xF7, 0xA8, 0x44, 0x3D, \ - 0x08, 0x22, 0xE5, 0x06, 0xA9, 0xF4, 0x61, 0x4E, \ - 0x01, 0x1E, 0x2A, 0x94, 0x83, 0x8F, 0xF8, 0x8C, \ - 0xD6, 0x8C, 0x8B, 0xB7, 0xC5, 0xC6, 0x42, 0x4C, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - -#define MBEDTLS_DHM_RFC7919_FFDHE8192_G_BIN { 0x02 } - -#endif /* dhm.h */ +/** + * \file dhm.h + * + * \brief This file contains Diffie-Hellman-Merkle (DHM) key exchange + * definitions and functions. + * + * Diffie-Hellman-Merkle (DHM) key exchange is defined in + * RFC-2631: Diffie-Hellman Key Agreement Method and + * Public-Key Cryptography Standards (PKCS) #3: Diffie + * Hellman Key Agreement Standard. + * + * RFC-3526: More Modular Exponential (MODP) Diffie-Hellman groups for + * Internet Key Exchange (IKE) defines a number of standardized + * Diffie-Hellman groups for IKE. + * + * RFC-5114: Additional Diffie-Hellman Groups for Use with IETF + * Standards defines a number of standardized Diffie-Hellman + * groups that can be used. + * + * \warning The security of the DHM key exchange relies on the proper choice + * of prime modulus - optimally, it should be a safe prime. The usage + * of non-safe primes both decreases the difficulty of the underlying + * discrete logarithm problem and can lead to small subgroup attacks + * leaking private exponent bits when invalid public keys are used + * and not detected. This is especially relevant if the same DHM + * parameters are reused for multiple key exchanges as in static DHM, + * while the criticality of small-subgroup attacks is lower for + * ephemeral DHM. + * + * \warning For performance reasons, the code does neither perform primality + * nor safe primality tests, nor the expensive checks for invalid + * subgroups. Moreover, even if these were performed, non-standardized + * primes cannot be trusted because of the possibility of backdoors + * that can't be effectively checked for. + * + * \warning Diffie-Hellman-Merkle is therefore a security risk when not using + * standardized primes generated using a trustworthy ("nothing up + * my sleeve") method, such as the RFC 3526 / 7919 primes. In the TLS + * protocol, DH parameters need to be negotiated, so using the default + * primes systematically is not always an option. If possible, use + * Elliptic Curve Diffie-Hellman (ECDH), which has better performance, + * and for which the TLS protocol mandates the use of standard + * parameters. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_DHM_H +#define MBEDTLS_DHM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" +#include "mbedtls/bignum.h" + +/* + * DHM Error codes + */ +/** Bad input parameters. */ +#define MBEDTLS_ERR_DHM_BAD_INPUT_DATA -0x3080 +/** Reading of the DHM parameters failed. */ +#define MBEDTLS_ERR_DHM_READ_PARAMS_FAILED -0x3100 +/** Making of the DHM parameters failed. */ +#define MBEDTLS_ERR_DHM_MAKE_PARAMS_FAILED -0x3180 +/** Reading of the public values failed. */ +#define MBEDTLS_ERR_DHM_READ_PUBLIC_FAILED -0x3200 +/** Making of the public value failed. */ +#define MBEDTLS_ERR_DHM_MAKE_PUBLIC_FAILED -0x3280 +/** Calculation of the DHM secret failed. */ +#define MBEDTLS_ERR_DHM_CALC_SECRET_FAILED -0x3300 +/** The ASN.1 data is not formatted correctly. */ +#define MBEDTLS_ERR_DHM_INVALID_FORMAT -0x3380 +/** Allocation of memory failed. */ +#define MBEDTLS_ERR_DHM_ALLOC_FAILED -0x3400 +/** Read or write of file failed. */ +#define MBEDTLS_ERR_DHM_FILE_IO_ERROR -0x3480 +/** Setting the modulus and generator failed. */ +#define MBEDTLS_ERR_DHM_SET_GROUP_FAILED -0x3580 + +/** Which parameter to access in mbedtls_dhm_get_value(). */ +typedef enum { + MBEDTLS_DHM_PARAM_P, /*!< The prime modulus. */ + MBEDTLS_DHM_PARAM_G, /*!< The generator. */ + MBEDTLS_DHM_PARAM_X, /*!< Our secret value. */ + MBEDTLS_DHM_PARAM_GX, /*!< Our public key = \c G^X mod \c P. */ + MBEDTLS_DHM_PARAM_GY, /*!< The public key of the peer = \c G^Y mod \c P. */ + MBEDTLS_DHM_PARAM_K, /*!< The shared secret = \c G^(XY) mod \c P. */ +} mbedtls_dhm_parameter; + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_DHM_ALT) + +/** + * \brief The DHM context structure. + */ +typedef struct mbedtls_dhm_context { + mbedtls_mpi MBEDTLS_PRIVATE(P); /*!< The prime modulus. */ + mbedtls_mpi MBEDTLS_PRIVATE(G); /*!< The generator. */ + mbedtls_mpi MBEDTLS_PRIVATE(X); /*!< Our secret value. */ + mbedtls_mpi MBEDTLS_PRIVATE(GX); /*!< Our public key = \c G^X mod \c P. */ + mbedtls_mpi MBEDTLS_PRIVATE(GY); /*!< The public key of the peer = \c G^Y mod \c P. */ + mbedtls_mpi MBEDTLS_PRIVATE(K); /*!< The shared secret = \c G^(XY) mod \c P. */ + mbedtls_mpi MBEDTLS_PRIVATE(RP); /*!< The cached value = \c R^2 mod \c P. */ + mbedtls_mpi MBEDTLS_PRIVATE(Vi); /*!< The blinding value. */ + mbedtls_mpi MBEDTLS_PRIVATE(Vf); /*!< The unblinding value. */ + mbedtls_mpi MBEDTLS_PRIVATE(pX); /*!< The previous \c X. */ +} +mbedtls_dhm_context; + +#else /* MBEDTLS_DHM_ALT */ +#include "dhm_alt.h" +#endif /* MBEDTLS_DHM_ALT */ + +/** + * \brief This function initializes the DHM context. + * + * \param ctx The DHM context to initialize. + */ +void mbedtls_dhm_init(mbedtls_dhm_context *ctx); + +/** + * \brief This function parses the DHM parameters in a + * TLS ServerKeyExchange handshake message + * (DHM modulus, generator, and public key). + * + * \note In a TLS handshake, this is the how the client + * sets up its DHM context from the server's public + * DHM key material. + * + * \param ctx The DHM context to use. This must be initialized. + * \param p On input, *p must be the start of the input buffer. + * On output, *p is updated to point to the end of the data + * that has been read. On success, this is the first byte + * past the end of the ServerKeyExchange parameters. + * On error, this is the point at which an error has been + * detected, which is usually not useful except to debug + * failures. + * \param end The end of the input buffer. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_read_params(mbedtls_dhm_context *ctx, + unsigned char **p, + const unsigned char *end); + +/** + * \brief This function generates a DHM key pair and exports its + * public part together with the DHM parameters in the format + * used in a TLS ServerKeyExchange handshake message. + * + * \note This function assumes that the DHM parameters \c ctx->P + * and \c ctx->G have already been properly set. For that, use + * mbedtls_dhm_set_group() below in conjunction with + * mbedtls_mpi_read_binary() and mbedtls_mpi_read_string(). + * + * \note In a TLS handshake, this is the how the server generates + * and exports its DHM key material. + * + * \param ctx The DHM context to use. This must be initialized + * and have the DHM parameters set. It may or may not + * already have imported the peer's public key. + * \param x_size The private key size in Bytes. + * \param olen The address at which to store the number of Bytes + * written on success. This must not be \c NULL. + * \param output The destination buffer. This must be a writable buffer of + * sufficient size to hold the reduced binary presentation of + * the modulus, the generator and the public key, each wrapped + * with a 2-byte length field. It is the responsibility of the + * caller to ensure that enough space is available. Refer to + * mbedtls_mpi_size() to computing the byte-size of an MPI. + * \param f_rng The RNG function. Must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_make_params(mbedtls_dhm_context *ctx, int x_size, + unsigned char *output, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function sets the prime modulus and generator. + * + * \note This function can be used to set \c ctx->P, \c ctx->G + * in preparation for mbedtls_dhm_make_params(). + * + * \param ctx The DHM context to configure. This must be initialized. + * \param P The MPI holding the DHM prime modulus. This must be + * an initialized MPI. + * \param G The MPI holding the DHM generator. This must be an + * initialized MPI. + * + * \return \c 0 if successful. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_set_group(mbedtls_dhm_context *ctx, + const mbedtls_mpi *P, + const mbedtls_mpi *G); + +/** + * \brief This function imports the raw public value of the peer. + * + * \note In a TLS handshake, this is the how the server imports + * the Client's public DHM key. + * + * \param ctx The DHM context to use. This must be initialized and have + * its DHM parameters set, e.g. via mbedtls_dhm_set_group(). + * It may or may not already have generated its own private key. + * \param input The input buffer containing the \c G^Y value of the peer. + * This must be a readable buffer of size \p ilen Bytes. + * \param ilen The size of the input buffer \p input in Bytes. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_read_public(mbedtls_dhm_context *ctx, + const unsigned char *input, size_t ilen); + +/** + * \brief This function creates a DHM key pair and exports + * the raw public key in big-endian format. + * + * \note The destination buffer is always fully written + * so as to contain a big-endian representation of G^X mod P. + * If it is larger than \c ctx->len, it is padded accordingly + * with zero-bytes at the beginning. + * + * \param ctx The DHM context to use. This must be initialized and + * have the DHM parameters set. It may or may not already + * have imported the peer's public key. + * \param x_size The private key size in Bytes. + * \param output The destination buffer. This must be a writable buffer of + * size \p olen Bytes. + * \param olen The length of the destination buffer. This must be at least + * equal to `ctx->len` (the size of \c P). + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_make_public(mbedtls_dhm_context *ctx, int x_size, + unsigned char *output, size_t olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function derives and exports the shared secret + * \c (G^Y)^X mod \c P. + * + * \note If \p f_rng is not \c NULL, it is used to blind the input as + * a countermeasure against timing attacks. Blinding is used + * only if our private key \c X is re-used, and not used + * otherwise. We recommend always passing a non-NULL + * \p f_rng argument. + * + * \param ctx The DHM context to use. This must be initialized + * and have its own private key generated and the peer's + * public key imported. + * \param output The buffer to write the generated shared key to. This + * must be a writable buffer of size \p output_size Bytes. + * \param output_size The size of the destination buffer. This must be at + * least the size of \c ctx->len (the size of \c P). + * \param olen On exit, holds the actual number of Bytes written. + * \param f_rng The RNG function. Must not be \c NULL. Used for + * blinding. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX error code on failure. + */ +int mbedtls_dhm_calc_secret(mbedtls_dhm_context *ctx, + unsigned char *output, size_t output_size, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function returns the size of the prime modulus in bits. + * + * \param ctx The DHM context to query. + * + * \return The size of the prime modulus in bits, + * i.e. the number n such that 2^(n-1) <= P < 2^n. + */ +size_t mbedtls_dhm_get_bitlen(const mbedtls_dhm_context *ctx); + +/** + * \brief This function returns the size of the prime modulus in bytes. + * + * \param ctx The DHM context to query. + * + * \return The size of the prime modulus in bytes, + * i.e. the number n such that 2^(8*(n-1)) <= P < 2^(8*n). + */ +size_t mbedtls_dhm_get_len(const mbedtls_dhm_context *ctx); + +/** + * \brief This function copies a parameter of a DHM key. + * + * \param ctx The DHM context to query. + * \param param The parameter to copy. + * \param dest The MPI object to copy the value into. It must be + * initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_DHM_BAD_INPUT_DATA if \p param is invalid. + * \return An \c MBEDTLS_ERR_MPI_XXX error code if the copy fails. + */ +int mbedtls_dhm_get_value(const mbedtls_dhm_context *ctx, + mbedtls_dhm_parameter param, + mbedtls_mpi *dest); + +/** + * \brief This function frees and clears the components + * of a DHM context. + * + * \param ctx The DHM context to free and clear. This may be \c NULL, + * in which case this function is a no-op. If it is not \c NULL, + * it must point to an initialized DHM context. + */ +void mbedtls_dhm_free(mbedtls_dhm_context *ctx); + +#if defined(MBEDTLS_ASN1_PARSE_C) +/** + * \brief This function parses DHM parameters in PEM or DER format. + * + * \param dhm The DHM context to import the DHM parameters into. + * This must be initialized. + * \param dhmin The input buffer. This must be a readable buffer of + * length \p dhminlen Bytes. + * \param dhminlen The size of the input buffer \p dhmin, including the + * terminating \c NULL Byte for PEM data. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX error + * code on failure. + */ +int mbedtls_dhm_parse_dhm(mbedtls_dhm_context *dhm, const unsigned char *dhmin, + size_t dhminlen); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function loads and parses DHM parameters from a file. + * + * \param dhm The DHM context to load the parameters to. + * This must be initialized. + * \param path The filename to read the DHM parameters from. + * This must not be \c NULL. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_DHM_XXX or \c MBEDTLS_ERR_PEM_XXX + * error code on failure. + */ +int mbedtls_dhm_parse_dhmfile(mbedtls_dhm_context *dhm, const char *path); +#endif /* MBEDTLS_FS_IO */ +#endif /* MBEDTLS_ASN1_PARSE_C */ + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The DMH checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_dhm_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ +#ifdef __cplusplus +} +#endif + +/** + * RFC 3526, RFC 5114 and RFC 7919 standardize a number of + * Diffie-Hellman groups, some of which are included here + * for use within the SSL/TLS module and the user's convenience + * when configuring the Diffie-Hellman parameters by hand + * through \c mbedtls_ssl_conf_dh_param. + * + * The following lists the source of the above groups in the standards: + * - RFC 5114 section 2.2: 2048-bit MODP Group with 224-bit Prime Order Subgroup + * - RFC 3526 section 3: 2048-bit MODP Group + * - RFC 3526 section 4: 3072-bit MODP Group + * - RFC 3526 section 5: 4096-bit MODP Group + * - RFC 7919 section A.1: ffdhe2048 + * - RFC 7919 section A.2: ffdhe3072 + * - RFC 7919 section A.3: ffdhe4096 + * - RFC 7919 section A.4: ffdhe6144 + * - RFC 7919 section A.5: ffdhe8192 + * + * The constants with suffix "_p" denote the chosen prime moduli, while + * the constants with suffix "_g" denote the chosen generator + * of the associated prime field. + * + * The constants further suffixed with "_bin" are provided in binary format, + * while all other constants represent null-terminated strings holding the + * hexadecimal presentation of the respective numbers. + * + * The primes from RFC 3526 and RFC 7919 have been generating by the following + * trust-worthy procedure: + * - Fix N in { 2048, 3072, 4096, 6144, 8192 } and consider the N-bit number + * the first and last 64 bits are all 1, and the remaining N - 128 bits of + * which are 0x7ff...ff. + * - Add the smallest multiple of the first N - 129 bits of the binary expansion + * of pi (for RFC 5236) or e (for RFC 7919) to this intermediate bit-string + * such that the resulting integer is a safe-prime. + * - The result is the respective RFC 3526 / 7919 prime, and the corresponding + * generator is always chosen to be 2 (which is a square for these prime, + * hence the corresponding subgroup has order (p-1)/2 and avoids leaking a + * bit in the private exponent). + * + */ + +/* + * Trustworthy DHM parameters in binary form + */ + +#define MBEDTLS_DHM_RFC3526_MODP_2048_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ + 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ + 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ + 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ + 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ + 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ + 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ + 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ + 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ + 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ + 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ + 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ + 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ + 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ + 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ + 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ + 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ + 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ + 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ + 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ + 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ + 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ + 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ + 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ + 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ + 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ + 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ + 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ + 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ + 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAC, 0xAA, 0x68, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC3526_MODP_2048_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC3526_MODP_3072_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ + 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ + 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ + 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ + 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ + 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ + 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ + 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ + 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ + 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ + 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ + 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ + 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ + 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ + 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ + 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ + 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ + 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ + 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ + 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ + 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ + 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ + 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ + 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ + 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ + 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ + 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ + 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ + 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ + 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D, \ + 0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33, \ + 0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64, \ + 0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A, \ + 0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D, \ + 0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7, \ + 0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7, \ + 0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D, \ + 0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B, \ + 0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64, \ + 0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64, \ + 0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C, \ + 0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C, \ + 0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2, \ + 0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31, \ + 0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E, \ + 0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x3A, 0xD2, 0xCA, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC3526_MODP_3072_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC3526_MODP_4096_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xC9, 0x0F, 0xDA, 0xA2, 0x21, 0x68, 0xC2, 0x34, \ + 0xC4, 0xC6, 0x62, 0x8B, 0x80, 0xDC, 0x1C, 0xD1, \ + 0x29, 0x02, 0x4E, 0x08, 0x8A, 0x67, 0xCC, 0x74, \ + 0x02, 0x0B, 0xBE, 0xA6, 0x3B, 0x13, 0x9B, 0x22, \ + 0x51, 0x4A, 0x08, 0x79, 0x8E, 0x34, 0x04, 0xDD, \ + 0xEF, 0x95, 0x19, 0xB3, 0xCD, 0x3A, 0x43, 0x1B, \ + 0x30, 0x2B, 0x0A, 0x6D, 0xF2, 0x5F, 0x14, 0x37, \ + 0x4F, 0xE1, 0x35, 0x6D, 0x6D, 0x51, 0xC2, 0x45, \ + 0xE4, 0x85, 0xB5, 0x76, 0x62, 0x5E, 0x7E, 0xC6, \ + 0xF4, 0x4C, 0x42, 0xE9, 0xA6, 0x37, 0xED, 0x6B, \ + 0x0B, 0xFF, 0x5C, 0xB6, 0xF4, 0x06, 0xB7, 0xED, \ + 0xEE, 0x38, 0x6B, 0xFB, 0x5A, 0x89, 0x9F, 0xA5, \ + 0xAE, 0x9F, 0x24, 0x11, 0x7C, 0x4B, 0x1F, 0xE6, \ + 0x49, 0x28, 0x66, 0x51, 0xEC, 0xE4, 0x5B, 0x3D, \ + 0xC2, 0x00, 0x7C, 0xB8, 0xA1, 0x63, 0xBF, 0x05, \ + 0x98, 0xDA, 0x48, 0x36, 0x1C, 0x55, 0xD3, 0x9A, \ + 0x69, 0x16, 0x3F, 0xA8, 0xFD, 0x24, 0xCF, 0x5F, \ + 0x83, 0x65, 0x5D, 0x23, 0xDC, 0xA3, 0xAD, 0x96, \ + 0x1C, 0x62, 0xF3, 0x56, 0x20, 0x85, 0x52, 0xBB, \ + 0x9E, 0xD5, 0x29, 0x07, 0x70, 0x96, 0x96, 0x6D, \ + 0x67, 0x0C, 0x35, 0x4E, 0x4A, 0xBC, 0x98, 0x04, \ + 0xF1, 0x74, 0x6C, 0x08, 0xCA, 0x18, 0x21, 0x7C, \ + 0x32, 0x90, 0x5E, 0x46, 0x2E, 0x36, 0xCE, 0x3B, \ + 0xE3, 0x9E, 0x77, 0x2C, 0x18, 0x0E, 0x86, 0x03, \ + 0x9B, 0x27, 0x83, 0xA2, 0xEC, 0x07, 0xA2, 0x8F, \ + 0xB5, 0xC5, 0x5D, 0xF0, 0x6F, 0x4C, 0x52, 0xC9, \ + 0xDE, 0x2B, 0xCB, 0xF6, 0x95, 0x58, 0x17, 0x18, \ + 0x39, 0x95, 0x49, 0x7C, 0xEA, 0x95, 0x6A, 0xE5, \ + 0x15, 0xD2, 0x26, 0x18, 0x98, 0xFA, 0x05, 0x10, \ + 0x15, 0x72, 0x8E, 0x5A, 0x8A, 0xAA, 0xC4, 0x2D, \ + 0xAD, 0x33, 0x17, 0x0D, 0x04, 0x50, 0x7A, 0x33, \ + 0xA8, 0x55, 0x21, 0xAB, 0xDF, 0x1C, 0xBA, 0x64, \ + 0xEC, 0xFB, 0x85, 0x04, 0x58, 0xDB, 0xEF, 0x0A, \ + 0x8A, 0xEA, 0x71, 0x57, 0x5D, 0x06, 0x0C, 0x7D, \ + 0xB3, 0x97, 0x0F, 0x85, 0xA6, 0xE1, 0xE4, 0xC7, \ + 0xAB, 0xF5, 0xAE, 0x8C, 0xDB, 0x09, 0x33, 0xD7, \ + 0x1E, 0x8C, 0x94, 0xE0, 0x4A, 0x25, 0x61, 0x9D, \ + 0xCE, 0xE3, 0xD2, 0x26, 0x1A, 0xD2, 0xEE, 0x6B, \ + 0xF1, 0x2F, 0xFA, 0x06, 0xD9, 0x8A, 0x08, 0x64, \ + 0xD8, 0x76, 0x02, 0x73, 0x3E, 0xC8, 0x6A, 0x64, \ + 0x52, 0x1F, 0x2B, 0x18, 0x17, 0x7B, 0x20, 0x0C, \ + 0xBB, 0xE1, 0x17, 0x57, 0x7A, 0x61, 0x5D, 0x6C, \ + 0x77, 0x09, 0x88, 0xC0, 0xBA, 0xD9, 0x46, 0xE2, \ + 0x08, 0xE2, 0x4F, 0xA0, 0x74, 0xE5, 0xAB, 0x31, \ + 0x43, 0xDB, 0x5B, 0xFC, 0xE0, 0xFD, 0x10, 0x8E, \ + 0x4B, 0x82, 0xD1, 0x20, 0xA9, 0x21, 0x08, 0x01, \ + 0x1A, 0x72, 0x3C, 0x12, 0xA7, 0x87, 0xE6, 0xD7, \ + 0x88, 0x71, 0x9A, 0x10, 0xBD, 0xBA, 0x5B, 0x26, \ + 0x99, 0xC3, 0x27, 0x18, 0x6A, 0xF4, 0xE2, 0x3C, \ + 0x1A, 0x94, 0x68, 0x34, 0xB6, 0x15, 0x0B, 0xDA, \ + 0x25, 0x83, 0xE9, 0xCA, 0x2A, 0xD4, 0x4C, 0xE8, \ + 0xDB, 0xBB, 0xC2, 0xDB, 0x04, 0xDE, 0x8E, 0xF9, \ + 0x2E, 0x8E, 0xFC, 0x14, 0x1F, 0xBE, 0xCA, 0xA6, \ + 0x28, 0x7C, 0x59, 0x47, 0x4E, 0x6B, 0xC0, 0x5D, \ + 0x99, 0xB2, 0x96, 0x4F, 0xA0, 0x90, 0xC3, 0xA2, \ + 0x23, 0x3B, 0xA1, 0x86, 0x51, 0x5B, 0xE7, 0xED, \ + 0x1F, 0x61, 0x29, 0x70, 0xCE, 0xE2, 0xD7, 0xAF, \ + 0xB8, 0x1B, 0xDD, 0x76, 0x21, 0x70, 0x48, 0x1C, \ + 0xD0, 0x06, 0x91, 0x27, 0xD5, 0xB0, 0x5A, 0xA9, \ + 0x93, 0xB4, 0xEA, 0x98, 0x8D, 0x8F, 0xDD, 0xC1, \ + 0x86, 0xFF, 0xB7, 0xDC, 0x90, 0xA6, 0xC0, 0x8F, \ + 0x4D, 0xF4, 0x35, 0xC9, 0x34, 0x06, 0x31, 0x99, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC3526_MODP_4096_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC7919_FFDHE2048_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ + 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ + 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ + 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ + 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ + 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ + 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ + 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ + 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ + 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ + 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ + 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ + 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ + 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ + 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ + 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ + 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ + 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ + 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ + 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ + 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ + 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ + 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ + 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ + 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ + 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ + 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ + 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ + 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ + 0x88, 0x6B, 0x42, 0x38, 0x61, 0x28, 0x5C, 0x97, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, } + +#define MBEDTLS_DHM_RFC7919_FFDHE2048_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC7919_FFDHE3072_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ + 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ + 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ + 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ + 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ + 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ + 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ + 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ + 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ + 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ + 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ + 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ + 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ + 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ + 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ + 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ + 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ + 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ + 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ + 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ + 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ + 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ + 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ + 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ + 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ + 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ + 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ + 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ + 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ + 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ + 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ + 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ + 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ + 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ + 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ + 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ + 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ + 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ + 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ + 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ + 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ + 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ + 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ + 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ + 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ + 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0xC6, 0x2E, 0x37, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC7919_FFDHE3072_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC7919_FFDHE4096_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ + 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ + 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ + 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ + 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ + 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ + 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ + 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ + 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ + 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ + 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ + 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ + 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ + 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ + 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ + 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ + 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ + 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ + 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ + 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ + 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ + 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ + 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ + 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ + 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ + 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ + 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ + 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ + 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ + 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ + 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ + 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ + 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ + 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ + 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ + 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ + 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ + 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ + 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ + 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ + 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ + 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ + 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ + 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ + 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ + 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ + 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ + 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ + 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ + 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ + 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ + 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ + 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ + 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ + 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ + 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ + 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ + 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ + 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ + 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ + 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ + 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x65, 0x5F, 0x6A, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC7919_FFDHE4096_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC7919_FFDHE6144_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ + 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ + 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ + 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ + 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ + 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ + 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ + 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ + 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ + 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ + 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ + 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ + 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ + 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ + 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ + 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ + 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ + 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ + 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ + 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ + 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ + 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ + 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ + 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ + 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ + 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ + 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ + 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ + 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ + 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ + 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ + 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ + 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ + 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ + 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ + 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ + 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ + 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ + 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ + 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ + 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ + 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ + 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ + 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ + 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ + 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ + 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ + 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ + 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ + 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ + 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ + 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ + 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ + 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ + 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ + 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ + 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ + 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ + 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ + 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ + 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ + 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \ + 0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \ + 0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \ + 0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \ + 0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \ + 0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \ + 0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \ + 0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \ + 0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \ + 0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \ + 0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \ + 0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \ + 0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \ + 0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \ + 0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \ + 0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \ + 0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \ + 0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \ + 0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \ + 0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \ + 0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \ + 0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \ + 0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \ + 0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \ + 0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \ + 0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \ + 0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \ + 0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \ + 0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \ + 0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \ + 0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \ + 0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \ + 0xA4, 0x0E, 0x32, 0x9C, 0xD0, 0xE4, 0x0E, 0x65, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC7919_FFDHE6144_G_BIN { 0x02 } + +#define MBEDTLS_DHM_RFC7919_FFDHE8192_P_BIN { \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \ + 0xAD, 0xF8, 0x54, 0x58, 0xA2, 0xBB, 0x4A, 0x9A, \ + 0xAF, 0xDC, 0x56, 0x20, 0x27, 0x3D, 0x3C, 0xF1, \ + 0xD8, 0xB9, 0xC5, 0x83, 0xCE, 0x2D, 0x36, 0x95, \ + 0xA9, 0xE1, 0x36, 0x41, 0x14, 0x64, 0x33, 0xFB, \ + 0xCC, 0x93, 0x9D, 0xCE, 0x24, 0x9B, 0x3E, 0xF9, \ + 0x7D, 0x2F, 0xE3, 0x63, 0x63, 0x0C, 0x75, 0xD8, \ + 0xF6, 0x81, 0xB2, 0x02, 0xAE, 0xC4, 0x61, 0x7A, \ + 0xD3, 0xDF, 0x1E, 0xD5, 0xD5, 0xFD, 0x65, 0x61, \ + 0x24, 0x33, 0xF5, 0x1F, 0x5F, 0x06, 0x6E, 0xD0, \ + 0x85, 0x63, 0x65, 0x55, 0x3D, 0xED, 0x1A, 0xF3, \ + 0xB5, 0x57, 0x13, 0x5E, 0x7F, 0x57, 0xC9, 0x35, \ + 0x98, 0x4F, 0x0C, 0x70, 0xE0, 0xE6, 0x8B, 0x77, \ + 0xE2, 0xA6, 0x89, 0xDA, 0xF3, 0xEF, 0xE8, 0x72, \ + 0x1D, 0xF1, 0x58, 0xA1, 0x36, 0xAD, 0xE7, 0x35, \ + 0x30, 0xAC, 0xCA, 0x4F, 0x48, 0x3A, 0x79, 0x7A, \ + 0xBC, 0x0A, 0xB1, 0x82, 0xB3, 0x24, 0xFB, 0x61, \ + 0xD1, 0x08, 0xA9, 0x4B, 0xB2, 0xC8, 0xE3, 0xFB, \ + 0xB9, 0x6A, 0xDA, 0xB7, 0x60, 0xD7, 0xF4, 0x68, \ + 0x1D, 0x4F, 0x42, 0xA3, 0xDE, 0x39, 0x4D, 0xF4, \ + 0xAE, 0x56, 0xED, 0xE7, 0x63, 0x72, 0xBB, 0x19, \ + 0x0B, 0x07, 0xA7, 0xC8, 0xEE, 0x0A, 0x6D, 0x70, \ + 0x9E, 0x02, 0xFC, 0xE1, 0xCD, 0xF7, 0xE2, 0xEC, \ + 0xC0, 0x34, 0x04, 0xCD, 0x28, 0x34, 0x2F, 0x61, \ + 0x91, 0x72, 0xFE, 0x9C, 0xE9, 0x85, 0x83, 0xFF, \ + 0x8E, 0x4F, 0x12, 0x32, 0xEE, 0xF2, 0x81, 0x83, \ + 0xC3, 0xFE, 0x3B, 0x1B, 0x4C, 0x6F, 0xAD, 0x73, \ + 0x3B, 0xB5, 0xFC, 0xBC, 0x2E, 0xC2, 0x20, 0x05, \ + 0xC5, 0x8E, 0xF1, 0x83, 0x7D, 0x16, 0x83, 0xB2, \ + 0xC6, 0xF3, 0x4A, 0x26, 0xC1, 0xB2, 0xEF, 0xFA, \ + 0x88, 0x6B, 0x42, 0x38, 0x61, 0x1F, 0xCF, 0xDC, \ + 0xDE, 0x35, 0x5B, 0x3B, 0x65, 0x19, 0x03, 0x5B, \ + 0xBC, 0x34, 0xF4, 0xDE, 0xF9, 0x9C, 0x02, 0x38, \ + 0x61, 0xB4, 0x6F, 0xC9, 0xD6, 0xE6, 0xC9, 0x07, \ + 0x7A, 0xD9, 0x1D, 0x26, 0x91, 0xF7, 0xF7, 0xEE, \ + 0x59, 0x8C, 0xB0, 0xFA, 0xC1, 0x86, 0xD9, 0x1C, \ + 0xAE, 0xFE, 0x13, 0x09, 0x85, 0x13, 0x92, 0x70, \ + 0xB4, 0x13, 0x0C, 0x93, 0xBC, 0x43, 0x79, 0x44, \ + 0xF4, 0xFD, 0x44, 0x52, 0xE2, 0xD7, 0x4D, 0xD3, \ + 0x64, 0xF2, 0xE2, 0x1E, 0x71, 0xF5, 0x4B, 0xFF, \ + 0x5C, 0xAE, 0x82, 0xAB, 0x9C, 0x9D, 0xF6, 0x9E, \ + 0xE8, 0x6D, 0x2B, 0xC5, 0x22, 0x36, 0x3A, 0x0D, \ + 0xAB, 0xC5, 0x21, 0x97, 0x9B, 0x0D, 0xEA, 0xDA, \ + 0x1D, 0xBF, 0x9A, 0x42, 0xD5, 0xC4, 0x48, 0x4E, \ + 0x0A, 0xBC, 0xD0, 0x6B, 0xFA, 0x53, 0xDD, 0xEF, \ + 0x3C, 0x1B, 0x20, 0xEE, 0x3F, 0xD5, 0x9D, 0x7C, \ + 0x25, 0xE4, 0x1D, 0x2B, 0x66, 0x9E, 0x1E, 0xF1, \ + 0x6E, 0x6F, 0x52, 0xC3, 0x16, 0x4D, 0xF4, 0xFB, \ + 0x79, 0x30, 0xE9, 0xE4, 0xE5, 0x88, 0x57, 0xB6, \ + 0xAC, 0x7D, 0x5F, 0x42, 0xD6, 0x9F, 0x6D, 0x18, \ + 0x77, 0x63, 0xCF, 0x1D, 0x55, 0x03, 0x40, 0x04, \ + 0x87, 0xF5, 0x5B, 0xA5, 0x7E, 0x31, 0xCC, 0x7A, \ + 0x71, 0x35, 0xC8, 0x86, 0xEF, 0xB4, 0x31, 0x8A, \ + 0xED, 0x6A, 0x1E, 0x01, 0x2D, 0x9E, 0x68, 0x32, \ + 0xA9, 0x07, 0x60, 0x0A, 0x91, 0x81, 0x30, 0xC4, \ + 0x6D, 0xC7, 0x78, 0xF9, 0x71, 0xAD, 0x00, 0x38, \ + 0x09, 0x29, 0x99, 0xA3, 0x33, 0xCB, 0x8B, 0x7A, \ + 0x1A, 0x1D, 0xB9, 0x3D, 0x71, 0x40, 0x00, 0x3C, \ + 0x2A, 0x4E, 0xCE, 0xA9, 0xF9, 0x8D, 0x0A, 0xCC, \ + 0x0A, 0x82, 0x91, 0xCD, 0xCE, 0xC9, 0x7D, 0xCF, \ + 0x8E, 0xC9, 0xB5, 0x5A, 0x7F, 0x88, 0xA4, 0x6B, \ + 0x4D, 0xB5, 0xA8, 0x51, 0xF4, 0x41, 0x82, 0xE1, \ + 0xC6, 0x8A, 0x00, 0x7E, 0x5E, 0x0D, 0xD9, 0x02, \ + 0x0B, 0xFD, 0x64, 0xB6, 0x45, 0x03, 0x6C, 0x7A, \ + 0x4E, 0x67, 0x7D, 0x2C, 0x38, 0x53, 0x2A, 0x3A, \ + 0x23, 0xBA, 0x44, 0x42, 0xCA, 0xF5, 0x3E, 0xA6, \ + 0x3B, 0xB4, 0x54, 0x32, 0x9B, 0x76, 0x24, 0xC8, \ + 0x91, 0x7B, 0xDD, 0x64, 0xB1, 0xC0, 0xFD, 0x4C, \ + 0xB3, 0x8E, 0x8C, 0x33, 0x4C, 0x70, 0x1C, 0x3A, \ + 0xCD, 0xAD, 0x06, 0x57, 0xFC, 0xCF, 0xEC, 0x71, \ + 0x9B, 0x1F, 0x5C, 0x3E, 0x4E, 0x46, 0x04, 0x1F, \ + 0x38, 0x81, 0x47, 0xFB, 0x4C, 0xFD, 0xB4, 0x77, \ + 0xA5, 0x24, 0x71, 0xF7, 0xA9, 0xA9, 0x69, 0x10, \ + 0xB8, 0x55, 0x32, 0x2E, 0xDB, 0x63, 0x40, 0xD8, \ + 0xA0, 0x0E, 0xF0, 0x92, 0x35, 0x05, 0x11, 0xE3, \ + 0x0A, 0xBE, 0xC1, 0xFF, 0xF9, 0xE3, 0xA2, 0x6E, \ + 0x7F, 0xB2, 0x9F, 0x8C, 0x18, 0x30, 0x23, 0xC3, \ + 0x58, 0x7E, 0x38, 0xDA, 0x00, 0x77, 0xD9, 0xB4, \ + 0x76, 0x3E, 0x4E, 0x4B, 0x94, 0xB2, 0xBB, 0xC1, \ + 0x94, 0xC6, 0x65, 0x1E, 0x77, 0xCA, 0xF9, 0x92, \ + 0xEE, 0xAA, 0xC0, 0x23, 0x2A, 0x28, 0x1B, 0xF6, \ + 0xB3, 0xA7, 0x39, 0xC1, 0x22, 0x61, 0x16, 0x82, \ + 0x0A, 0xE8, 0xDB, 0x58, 0x47, 0xA6, 0x7C, 0xBE, \ + 0xF9, 0xC9, 0x09, 0x1B, 0x46, 0x2D, 0x53, 0x8C, \ + 0xD7, 0x2B, 0x03, 0x74, 0x6A, 0xE7, 0x7F, 0x5E, \ + 0x62, 0x29, 0x2C, 0x31, 0x15, 0x62, 0xA8, 0x46, \ + 0x50, 0x5D, 0xC8, 0x2D, 0xB8, 0x54, 0x33, 0x8A, \ + 0xE4, 0x9F, 0x52, 0x35, 0xC9, 0x5B, 0x91, 0x17, \ + 0x8C, 0xCF, 0x2D, 0xD5, 0xCA, 0xCE, 0xF4, 0x03, \ + 0xEC, 0x9D, 0x18, 0x10, 0xC6, 0x27, 0x2B, 0x04, \ + 0x5B, 0x3B, 0x71, 0xF9, 0xDC, 0x6B, 0x80, 0xD6, \ + 0x3F, 0xDD, 0x4A, 0x8E, 0x9A, 0xDB, 0x1E, 0x69, \ + 0x62, 0xA6, 0x95, 0x26, 0xD4, 0x31, 0x61, 0xC1, \ + 0xA4, 0x1D, 0x57, 0x0D, 0x79, 0x38, 0xDA, 0xD4, \ + 0xA4, 0x0E, 0x32, 0x9C, 0xCF, 0xF4, 0x6A, 0xAA, \ + 0x36, 0xAD, 0x00, 0x4C, 0xF6, 0x00, 0xC8, 0x38, \ + 0x1E, 0x42, 0x5A, 0x31, 0xD9, 0x51, 0xAE, 0x64, \ + 0xFD, 0xB2, 0x3F, 0xCE, 0xC9, 0x50, 0x9D, 0x43, \ + 0x68, 0x7F, 0xEB, 0x69, 0xED, 0xD1, 0xCC, 0x5E, \ + 0x0B, 0x8C, 0xC3, 0xBD, 0xF6, 0x4B, 0x10, 0xEF, \ + 0x86, 0xB6, 0x31, 0x42, 0xA3, 0xAB, 0x88, 0x29, \ + 0x55, 0x5B, 0x2F, 0x74, 0x7C, 0x93, 0x26, 0x65, \ + 0xCB, 0x2C, 0x0F, 0x1C, 0xC0, 0x1B, 0xD7, 0x02, \ + 0x29, 0x38, 0x88, 0x39, 0xD2, 0xAF, 0x05, 0xE4, \ + 0x54, 0x50, 0x4A, 0xC7, 0x8B, 0x75, 0x82, 0x82, \ + 0x28, 0x46, 0xC0, 0xBA, 0x35, 0xC3, 0x5F, 0x5C, \ + 0x59, 0x16, 0x0C, 0xC0, 0x46, 0xFD, 0x82, 0x51, \ + 0x54, 0x1F, 0xC6, 0x8C, 0x9C, 0x86, 0xB0, 0x22, \ + 0xBB, 0x70, 0x99, 0x87, 0x6A, 0x46, 0x0E, 0x74, \ + 0x51, 0xA8, 0xA9, 0x31, 0x09, 0x70, 0x3F, 0xEE, \ + 0x1C, 0x21, 0x7E, 0x6C, 0x38, 0x26, 0xE5, 0x2C, \ + 0x51, 0xAA, 0x69, 0x1E, 0x0E, 0x42, 0x3C, 0xFC, \ + 0x99, 0xE9, 0xE3, 0x16, 0x50, 0xC1, 0x21, 0x7B, \ + 0x62, 0x48, 0x16, 0xCD, 0xAD, 0x9A, 0x95, 0xF9, \ + 0xD5, 0xB8, 0x01, 0x94, 0x88, 0xD9, 0xC0, 0xA0, \ + 0xA1, 0xFE, 0x30, 0x75, 0xA5, 0x77, 0xE2, 0x31, \ + 0x83, 0xF8, 0x1D, 0x4A, 0x3F, 0x2F, 0xA4, 0x57, \ + 0x1E, 0xFC, 0x8C, 0xE0, 0xBA, 0x8A, 0x4F, 0xE8, \ + 0xB6, 0x85, 0x5D, 0xFE, 0x72, 0xB0, 0xA6, 0x6E, \ + 0xDE, 0xD2, 0xFB, 0xAB, 0xFB, 0xE5, 0x8A, 0x30, \ + 0xFA, 0xFA, 0xBE, 0x1C, 0x5D, 0x71, 0xA8, 0x7E, \ + 0x2F, 0x74, 0x1E, 0xF8, 0xC1, 0xFE, 0x86, 0xFE, \ + 0xA6, 0xBB, 0xFD, 0xE5, 0x30, 0x67, 0x7F, 0x0D, \ + 0x97, 0xD1, 0x1D, 0x49, 0xF7, 0xA8, 0x44, 0x3D, \ + 0x08, 0x22, 0xE5, 0x06, 0xA9, 0xF4, 0x61, 0x4E, \ + 0x01, 0x1E, 0x2A, 0x94, 0x83, 0x8F, 0xF8, 0x8C, \ + 0xD6, 0x8C, 0x8B, 0xB7, 0xC5, 0xC6, 0x42, 0x4C, \ + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + +#define MBEDTLS_DHM_RFC7919_FFDHE8192_G_BIN { 0x02 } + +#endif /* dhm.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdh.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdh.h index 67c94f0..34a50ca 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdh.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdh.h @@ -1,453 +1,453 @@ -/** - * \file ecdh.h - * - * \brief This file contains ECDH definitions and functions. - * - * The Elliptic Curve Diffie-Hellman (ECDH) protocol is an anonymous - * key agreement protocol allowing two parties to establish a shared - * secret over an insecure channel. Each party must have an - * elliptic-curve public–private key pair. - * - * For more information, see NIST SP 800-56A Rev. 2: Recommendation for - * Pair-Wise Key Establishment Schemes Using Discrete Logarithm - * Cryptography. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_ECDH_H -#define MBEDTLS_ECDH_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/ecp.h" - -/* - * Mbed TLS supports two formats for ECDH contexts (#mbedtls_ecdh_context - * defined in `ecdh.h`). For most applications, the choice of format makes - * no difference, since all library functions can work with either format, - * except that the new format is incompatible with MBEDTLS_ECP_RESTARTABLE. - - * The new format used when this option is disabled is smaller - * (56 bytes on a 32-bit platform). In future versions of the library, it - * will support alternative implementations of ECDH operations. - * The new format is incompatible with applications that access - * context fields directly and with restartable ECP operations. - */ - -#if defined(MBEDTLS_ECP_RESTARTABLE) -#define MBEDTLS_ECDH_LEGACY_CONTEXT -#else -#undef MBEDTLS_ECDH_LEGACY_CONTEXT -#endif - -#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) -#undef MBEDTLS_ECDH_LEGACY_CONTEXT -#include "everest/everest.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Defines the source of the imported EC key. - */ -typedef enum { - MBEDTLS_ECDH_OURS, /**< Our key. */ - MBEDTLS_ECDH_THEIRS, /**< The key of the peer. */ -} mbedtls_ecdh_side; - -#if !defined(MBEDTLS_ECDH_LEGACY_CONTEXT) -/** - * Defines the ECDH implementation used. - * - * Later versions of the library may add new variants, therefore users should - * not make any assumptions about them. - */ -typedef enum { - MBEDTLS_ECDH_VARIANT_NONE = 0, /*!< Implementation not defined. */ - MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0,/*!< The default Mbed TLS implementation */ -#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) - MBEDTLS_ECDH_VARIANT_EVEREST /*!< Everest implementation */ -#endif -} mbedtls_ecdh_variant; - -/** - * The context used by the default ECDH implementation. - * - * Later versions might change the structure of this context, therefore users - * should not make any assumptions about the structure of - * mbedtls_ecdh_context_mbed. - */ -typedef struct mbedtls_ecdh_context_mbed { - mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< The elliptic curve used. */ - mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< The private key. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< The public key. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Qp); /*!< The value of the public key of the peer. */ - mbedtls_mpi MBEDTLS_PRIVATE(z); /*!< The shared secret. */ -#if defined(MBEDTLS_ECP_RESTARTABLE) - mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(rs); /*!< The restart context for EC computations. */ -#endif -} mbedtls_ecdh_context_mbed; -#endif - -/** - * - * \warning Performing multiple operations concurrently on the same - * ECDSA context is not supported; objects of this type - * should not be shared between multiple threads. - * \brief The ECDH context structure. - */ -typedef struct mbedtls_ecdh_context { -#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) - mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< The elliptic curve used. */ - mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< The private key. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< The public key. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Qp); /*!< The value of the public key of the peer. */ - mbedtls_mpi MBEDTLS_PRIVATE(z); /*!< The shared secret. */ - int MBEDTLS_PRIVATE(point_format); /*!< The format of point export in TLS messages. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Vi); /*!< The blinding value. */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Vf); /*!< The unblinding value. */ - mbedtls_mpi MBEDTLS_PRIVATE(_d); /*!< The previous \p d. */ -#if defined(MBEDTLS_ECP_RESTARTABLE) - int MBEDTLS_PRIVATE(restart_enabled); /*!< The flag for restartable mode. */ - mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(rs); /*!< The restart context for EC computations. */ -#endif /* MBEDTLS_ECP_RESTARTABLE */ -#else - uint8_t MBEDTLS_PRIVATE(point_format); /*!< The format of point export in TLS messages - as defined in RFC 4492. */ - mbedtls_ecp_group_id MBEDTLS_PRIVATE(grp_id);/*!< The elliptic curve used. */ - mbedtls_ecdh_variant MBEDTLS_PRIVATE(var); /*!< The ECDH implementation/structure used. */ - union { - mbedtls_ecdh_context_mbed MBEDTLS_PRIVATE(mbed_ecdh); -#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) - mbedtls_ecdh_context_everest MBEDTLS_PRIVATE(everest_ecdh); -#endif - } MBEDTLS_PRIVATE(ctx); /*!< Implementation-specific context. The - context in use is specified by the \c var - field. */ -#if defined(MBEDTLS_ECP_RESTARTABLE) - uint8_t MBEDTLS_PRIVATE(restart_enabled); /*!< The flag for restartable mode. Functions of - an alternative implementation not supporting - restartable mode must return - MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED error - if this flag is set. */ -#endif /* MBEDTLS_ECP_RESTARTABLE */ -#endif /* MBEDTLS_ECDH_LEGACY_CONTEXT */ -} -mbedtls_ecdh_context; - -/** - * \brief Check whether a given group can be used for ECDH. - * - * \param gid The ECP group ID to check. - * - * \return \c 1 if the group can be used, \c 0 otherwise - */ -int mbedtls_ecdh_can_do(mbedtls_ecp_group_id gid); - -/** - * \brief This function generates an ECDH keypair on an elliptic - * curve. - * - * This function performs the first of two core computations - * implemented during the ECDH key exchange. The second core - * computation is performed by mbedtls_ecdh_compute_shared(). - * - * \see ecp.h - * - * \param grp The ECP group to use. This must be initialized and have - * domain parameters loaded, for example through - * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). - * \param d The destination MPI (private key). - * This must be initialized. - * \param Q The destination point (public key). - * This must be initialized. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL in case \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return Another \c MBEDTLS_ERR_ECP_XXX or - * \c MBEDTLS_MPI_XXX error code on failure. - */ -int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function computes the shared secret. - * - * This function performs the second of two core computations - * implemented during the ECDH key exchange. The first core - * computation is performed by mbedtls_ecdh_gen_public(). - * - * \see ecp.h - * - * \note If \p f_rng is not NULL, it is used to implement - * countermeasures against side-channel attacks. - * For more information, see mbedtls_ecp_mul(). - * - * \param grp The ECP group to use. This must be initialized and have - * domain parameters loaded, for example through - * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). - * \param z The destination MPI (shared secret). - * This must be initialized. - * \param Q The public key from another party. - * This must be initialized. - * \param d Our secret exponent (private key). - * This must be initialized. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng is \c NULL or doesn't need a - * context argument. - * - * \return \c 0 on success. - * \return Another \c MBEDTLS_ERR_ECP_XXX or - * \c MBEDTLS_MPI_XXX error code on failure. - */ -int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, mbedtls_mpi *z, - const mbedtls_ecp_point *Q, const mbedtls_mpi *d, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function initializes an ECDH context. - * - * \param ctx The ECDH context to initialize. This must not be \c NULL. - */ -void mbedtls_ecdh_init(mbedtls_ecdh_context *ctx); - -/** - * \brief This function sets up the ECDH context with the information - * given. - * - * This function should be called after mbedtls_ecdh_init() but - * before mbedtls_ecdh_make_params(). There is no need to call - * this function before mbedtls_ecdh_read_params(). - * - * This is the first function used by a TLS server for ECDHE - * ciphersuites. - * - * \param ctx The ECDH context to set up. This must be initialized. - * \param grp_id The group id of the group to set up the context for. - * - * \return \c 0 on success. - */ -int mbedtls_ecdh_setup(mbedtls_ecdh_context *ctx, - mbedtls_ecp_group_id grp_id); - -/** - * \brief This function frees a context. - * - * \param ctx The context to free. This may be \c NULL, in which - * case this function does nothing. If it is not \c NULL, - * it must point to an initialized ECDH context. - */ -void mbedtls_ecdh_free(mbedtls_ecdh_context *ctx); - -/** - * \brief This function generates an EC key pair and exports its - * in the format used in a TLS ServerKeyExchange handshake - * message. - * - * This is the second function used by a TLS server for ECDHE - * ciphersuites. (It is called after mbedtls_ecdh_setup().) - * - * \see ecp.h - * - * \param ctx The ECDH context to use. This must be initialized - * and bound to a group, for example via mbedtls_ecdh_setup(). - * \param olen The address at which to store the number of Bytes written. - * \param buf The destination buffer. This must be a writable buffer of - * length \p blen Bytes. - * \param blen The length of the destination buffer \p buf in Bytes. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL in case \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. - */ -int mbedtls_ecdh_make_params(mbedtls_ecdh_context *ctx, size_t *olen, - unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function parses the ECDHE parameters in a - * TLS ServerKeyExchange handshake message. - * - * \note In a TLS handshake, this is the how the client - * sets up its ECDHE context from the server's public - * ECDHE key material. - * - * \see ecp.h - * - * \param ctx The ECDHE context to use. This must be initialized. - * \param buf On input, \c *buf must be the start of the input buffer. - * On output, \c *buf is updated to point to the end of the - * data that has been read. On success, this is the first byte - * past the end of the ServerKeyExchange parameters. - * On error, this is the point at which an error has been - * detected, which is usually not useful except to debug - * failures. - * \param end The end of the input buffer. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. - * - */ -int mbedtls_ecdh_read_params(mbedtls_ecdh_context *ctx, - const unsigned char **buf, - const unsigned char *end); - -/** - * \brief This function sets up an ECDH context from an EC key. - * - * It is used by clients and servers in place of the - * ServerKeyEchange for static ECDH, and imports ECDH - * parameters from the EC key information of a certificate. - * - * \see ecp.h - * - * \param ctx The ECDH context to set up. This must be initialized. - * \param key The EC key to use. This must be initialized. - * \param side Defines the source of the key. Possible values are: - * - #MBEDTLS_ECDH_OURS: The key is ours. - * - #MBEDTLS_ECDH_THEIRS: The key is that of the peer. - * - * \return \c 0 on success. - * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. - * - */ -int mbedtls_ecdh_get_params(mbedtls_ecdh_context *ctx, - const mbedtls_ecp_keypair *key, - mbedtls_ecdh_side side); - -/** - * \brief This function generates a public key and exports it - * as a TLS ClientKeyExchange payload. - * - * This is the second function used by a TLS client for ECDH(E) - * ciphersuites. - * - * \see ecp.h - * - * \param ctx The ECDH context to use. This must be initialized - * and bound to a group, the latter usually by - * mbedtls_ecdh_read_params(). - * \param olen The address at which to store the number of Bytes written. - * This must not be \c NULL. - * \param buf The destination buffer. This must be a writable buffer - * of length \p blen Bytes. - * \param blen The size of the destination buffer \p buf in Bytes. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL in case \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. - */ -int mbedtls_ecdh_make_public(mbedtls_ecdh_context *ctx, size_t *olen, - unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function parses and processes the ECDHE payload of a - * TLS ClientKeyExchange message. - * - * This is the third function used by a TLS server for ECDH(E) - * ciphersuites. (It is called after mbedtls_ecdh_setup() and - * mbedtls_ecdh_make_params().) - * - * \see ecp.h - * - * \param ctx The ECDH context to use. This must be initialized - * and bound to a group, for example via mbedtls_ecdh_setup(). - * \param buf The pointer to the ClientKeyExchange payload. This must - * be a readable buffer of length \p blen Bytes. - * \param blen The length of the input buffer \p buf in Bytes. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. - */ -int mbedtls_ecdh_read_public(mbedtls_ecdh_context *ctx, - const unsigned char *buf, size_t blen); - -/** - * \brief This function derives and exports the shared secret. - * - * This is the last function used by both TLS client - * and servers. - * - * \note If \p f_rng is not NULL, it is used to implement - * countermeasures against side-channel attacks. - * For more information, see mbedtls_ecp_mul(). - * - * \see ecp.h - - * \param ctx The ECDH context to use. This must be initialized - * and have its own private key generated and the peer's - * public key imported. - * \param olen The address at which to store the total number of - * Bytes written on success. This must not be \c NULL. - * \param buf The buffer to write the generated shared key to. This - * must be a writable buffer of size \p blen Bytes. - * \param blen The length of the destination buffer \p buf in Bytes. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context. This may be \c NULL if \p f_rng - * doesn't need a context argument. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. - */ -int mbedtls_ecdh_calc_secret(mbedtls_ecdh_context *ctx, size_t *olen, - unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#if defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief This function enables restartable EC computations for this - * context. (Default: disabled.) - * - * \see \c mbedtls_ecp_set_max_ops() - * - * \note It is not possible to safely disable restartable - * computations once enabled, except by free-ing the context, - * which cancels possible in-progress operations. - * - * \param ctx The ECDH context to use. This must be initialized. - */ -void mbedtls_ecdh_enable_restart(mbedtls_ecdh_context *ctx); -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -#ifdef __cplusplus -} -#endif - -#endif /* ecdh.h */ +/** + * \file ecdh.h + * + * \brief This file contains ECDH definitions and functions. + * + * The Elliptic Curve Diffie-Hellman (ECDH) protocol is an anonymous + * key agreement protocol allowing two parties to establish a shared + * secret over an insecure channel. Each party must have an + * elliptic-curve public–private key pair. + * + * For more information, see NIST SP 800-56A Rev. 2: Recommendation for + * Pair-Wise Key Establishment Schemes Using Discrete Logarithm + * Cryptography. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_ECDH_H +#define MBEDTLS_ECDH_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/ecp.h" + +/* + * Mbed TLS supports two formats for ECDH contexts (#mbedtls_ecdh_context + * defined in `ecdh.h`). For most applications, the choice of format makes + * no difference, since all library functions can work with either format, + * except that the new format is incompatible with MBEDTLS_ECP_RESTARTABLE. + + * The new format used when this option is disabled is smaller + * (56 bytes on a 32-bit platform). In future versions of the library, it + * will support alternative implementations of ECDH operations. + * The new format is incompatible with applications that access + * context fields directly and with restartable ECP operations. + */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) +#define MBEDTLS_ECDH_LEGACY_CONTEXT +#else +#undef MBEDTLS_ECDH_LEGACY_CONTEXT +#endif + +#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) +#undef MBEDTLS_ECDH_LEGACY_CONTEXT +#include "everest/everest.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Defines the source of the imported EC key. + */ +typedef enum { + MBEDTLS_ECDH_OURS, /**< Our key. */ + MBEDTLS_ECDH_THEIRS, /**< The key of the peer. */ +} mbedtls_ecdh_side; + +#if !defined(MBEDTLS_ECDH_LEGACY_CONTEXT) +/** + * Defines the ECDH implementation used. + * + * Later versions of the library may add new variants, therefore users should + * not make any assumptions about them. + */ +typedef enum { + MBEDTLS_ECDH_VARIANT_NONE = 0, /*!< Implementation not defined. */ + MBEDTLS_ECDH_VARIANT_MBEDTLS_2_0,/*!< The default Mbed TLS implementation */ +#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) + MBEDTLS_ECDH_VARIANT_EVEREST /*!< Everest implementation */ +#endif +} mbedtls_ecdh_variant; + +/** + * The context used by the default ECDH implementation. + * + * Later versions might change the structure of this context, therefore users + * should not make any assumptions about the structure of + * mbedtls_ecdh_context_mbed. + */ +typedef struct mbedtls_ecdh_context_mbed { + mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< The elliptic curve used. */ + mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< The private key. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< The public key. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Qp); /*!< The value of the public key of the peer. */ + mbedtls_mpi MBEDTLS_PRIVATE(z); /*!< The shared secret. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(rs); /*!< The restart context for EC computations. */ +#endif +} mbedtls_ecdh_context_mbed; +#endif + +/** + * + * \warning Performing multiple operations concurrently on the same + * ECDSA context is not supported; objects of this type + * should not be shared between multiple threads. + * \brief The ECDH context structure. + */ +typedef struct mbedtls_ecdh_context { +#if defined(MBEDTLS_ECDH_LEGACY_CONTEXT) + mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< The elliptic curve used. */ + mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< The private key. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< The public key. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Qp); /*!< The value of the public key of the peer. */ + mbedtls_mpi MBEDTLS_PRIVATE(z); /*!< The shared secret. */ + int MBEDTLS_PRIVATE(point_format); /*!< The format of point export in TLS messages. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Vi); /*!< The blinding value. */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Vf); /*!< The unblinding value. */ + mbedtls_mpi MBEDTLS_PRIVATE(_d); /*!< The previous \p d. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + int MBEDTLS_PRIVATE(restart_enabled); /*!< The flag for restartable mode. */ + mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(rs); /*!< The restart context for EC computations. */ +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#else + uint8_t MBEDTLS_PRIVATE(point_format); /*!< The format of point export in TLS messages + as defined in RFC 4492. */ + mbedtls_ecp_group_id MBEDTLS_PRIVATE(grp_id);/*!< The elliptic curve used. */ + mbedtls_ecdh_variant MBEDTLS_PRIVATE(var); /*!< The ECDH implementation/structure used. */ + union { + mbedtls_ecdh_context_mbed MBEDTLS_PRIVATE(mbed_ecdh); +#if defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) + mbedtls_ecdh_context_everest MBEDTLS_PRIVATE(everest_ecdh); +#endif + } MBEDTLS_PRIVATE(ctx); /*!< Implementation-specific context. The + context in use is specified by the \c var + field. */ +#if defined(MBEDTLS_ECP_RESTARTABLE) + uint8_t MBEDTLS_PRIVATE(restart_enabled); /*!< The flag for restartable mode. Functions of + an alternative implementation not supporting + restartable mode must return + MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED error + if this flag is set. */ +#endif /* MBEDTLS_ECP_RESTARTABLE */ +#endif /* MBEDTLS_ECDH_LEGACY_CONTEXT */ +} +mbedtls_ecdh_context; + +/** + * \brief Check whether a given group can be used for ECDH. + * + * \param gid The ECP group ID to check. + * + * \return \c 1 if the group can be used, \c 0 otherwise + */ +int mbedtls_ecdh_can_do(mbedtls_ecp_group_id gid); + +/** + * \brief This function generates an ECDH keypair on an elliptic + * curve. + * + * This function performs the first of two core computations + * implemented during the ECDH key exchange. The second core + * computation is performed by mbedtls_ecdh_compute_shared(). + * + * \see ecp.h + * + * \param grp The ECP group to use. This must be initialized and have + * domain parameters loaded, for example through + * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). + * \param d The destination MPI (private key). + * This must be initialized. + * \param Q The destination point (public key). + * This must be initialized. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX or + * \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdh_gen_public(mbedtls_ecp_group *grp, mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function computes the shared secret. + * + * This function performs the second of two core computations + * implemented during the ECDH key exchange. The first core + * computation is performed by mbedtls_ecdh_gen_public(). + * + * \see ecp.h + * + * \note If \p f_rng is not NULL, it is used to implement + * countermeasures against side-channel attacks. + * For more information, see mbedtls_ecp_mul(). + * + * \param grp The ECP group to use. This must be initialized and have + * domain parameters loaded, for example through + * mbedtls_ecp_load() or mbedtls_ecp_tls_read_group(). + * \param z The destination MPI (shared secret). + * This must be initialized. + * \param Q The public key from another party. + * This must be initialized. + * \param d Our secret exponent (private key). + * This must be initialized. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't need a + * context argument. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX or + * \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdh_compute_shared(mbedtls_ecp_group *grp, mbedtls_mpi *z, + const mbedtls_ecp_point *Q, const mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function initializes an ECDH context. + * + * \param ctx The ECDH context to initialize. This must not be \c NULL. + */ +void mbedtls_ecdh_init(mbedtls_ecdh_context *ctx); + +/** + * \brief This function sets up the ECDH context with the information + * given. + * + * This function should be called after mbedtls_ecdh_init() but + * before mbedtls_ecdh_make_params(). There is no need to call + * this function before mbedtls_ecdh_read_params(). + * + * This is the first function used by a TLS server for ECDHE + * ciphersuites. + * + * \param ctx The ECDH context to set up. This must be initialized. + * \param grp_id The group id of the group to set up the context for. + * + * \return \c 0 on success. + */ +int mbedtls_ecdh_setup(mbedtls_ecdh_context *ctx, + mbedtls_ecp_group_id grp_id); + +/** + * \brief This function frees a context. + * + * \param ctx The context to free. This may be \c NULL, in which + * case this function does nothing. If it is not \c NULL, + * it must point to an initialized ECDH context. + */ +void mbedtls_ecdh_free(mbedtls_ecdh_context *ctx); + +/** + * \brief This function generates an EC key pair and exports its + * in the format used in a TLS ServerKeyExchange handshake + * message. + * + * This is the second function used by a TLS server for ECDHE + * ciphersuites. (It is called after mbedtls_ecdh_setup().) + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, for example via mbedtls_ecdh_setup(). + * \param olen The address at which to store the number of Bytes written. + * \param buf The destination buffer. This must be a writable buffer of + * length \p blen Bytes. + * \param blen The length of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_make_params(mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function parses the ECDHE parameters in a + * TLS ServerKeyExchange handshake message. + * + * \note In a TLS handshake, this is the how the client + * sets up its ECDHE context from the server's public + * ECDHE key material. + * + * \see ecp.h + * + * \param ctx The ECDHE context to use. This must be initialized. + * \param buf On input, \c *buf must be the start of the input buffer. + * On output, \c *buf is updated to point to the end of the + * data that has been read. On success, this is the first byte + * past the end of the ServerKeyExchange parameters. + * On error, this is the point at which an error has been + * detected, which is usually not useful except to debug + * failures. + * \param end The end of the input buffer. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. + * + */ +int mbedtls_ecdh_read_params(mbedtls_ecdh_context *ctx, + const unsigned char **buf, + const unsigned char *end); + +/** + * \brief This function sets up an ECDH context from an EC key. + * + * It is used by clients and servers in place of the + * ServerKeyEchange for static ECDH, and imports ECDH + * parameters from the EC key information of a certificate. + * + * \see ecp.h + * + * \param ctx The ECDH context to set up. This must be initialized. + * \param key The EC key to use. This must be initialized. + * \param side Defines the source of the key. Possible values are: + * - #MBEDTLS_ECDH_OURS: The key is ours. + * - #MBEDTLS_ECDH_THEIRS: The key is that of the peer. + * + * \return \c 0 on success. + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + * + */ +int mbedtls_ecdh_get_params(mbedtls_ecdh_context *ctx, + const mbedtls_ecp_keypair *key, + mbedtls_ecdh_side side); + +/** + * \brief This function generates a public key and exports it + * as a TLS ClientKeyExchange payload. + * + * This is the second function used by a TLS client for ECDH(E) + * ciphersuites. + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, the latter usually by + * mbedtls_ecdh_read_params(). + * \param olen The address at which to store the number of Bytes written. + * This must not be \c NULL. + * \param buf The destination buffer. This must be a writable buffer + * of length \p blen Bytes. + * \param blen The size of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL in case \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_make_public(mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function parses and processes the ECDHE payload of a + * TLS ClientKeyExchange message. + * + * This is the third function used by a TLS server for ECDH(E) + * ciphersuites. (It is called after mbedtls_ecdh_setup() and + * mbedtls_ecdh_make_params().) + * + * \see ecp.h + * + * \param ctx The ECDH context to use. This must be initialized + * and bound to a group, for example via mbedtls_ecdh_setup(). + * \param buf The pointer to the ClientKeyExchange payload. This must + * be a readable buffer of length \p blen Bytes. + * \param blen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_read_public(mbedtls_ecdh_context *ctx, + const unsigned char *buf, size_t blen); + +/** + * \brief This function derives and exports the shared secret. + * + * This is the last function used by both TLS client + * and servers. + * + * \note If \p f_rng is not NULL, it is used to implement + * countermeasures against side-channel attacks. + * For more information, see mbedtls_ecp_mul(). + * + * \see ecp.h + + * \param ctx The ECDH context to use. This must be initialized + * and have its own private key generated and the peer's + * public key imported. + * \param olen The address at which to store the total number of + * Bytes written on success. This must not be \c NULL. + * \param buf The buffer to write the generated shared key to. This + * must be a writable buffer of size \p blen Bytes. + * \param blen The length of the destination buffer \p buf in Bytes. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context. This may be \c NULL if \p f_rng + * doesn't need a context argument. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX error code on failure. + */ +int mbedtls_ecdh_calc_secret(mbedtls_ecdh_context *ctx, size_t *olen, + unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief This function enables restartable EC computations for this + * context. (Default: disabled.) + * + * \see \c mbedtls_ecp_set_max_ops() + * + * \note It is not possible to safely disable restartable + * computations once enabled, except by free-ing the context, + * which cancels possible in-progress operations. + * + * \param ctx The ECDH context to use. This must be initialized. + */ +void mbedtls_ecdh_enable_restart(mbedtls_ecdh_context *ctx); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecdh.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdsa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdsa.h index 3b2b418..c0c996a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdsa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecdsa.h @@ -1,683 +1,683 @@ -/** - * \file ecdsa.h - * - * \brief This file contains ECDSA definitions and functions. - * - * The Elliptic Curve Digital Signature Algorithm (ECDSA) is defined in - * Standards for Efficient Cryptography Group (SECG): - * SEC1 Elliptic Curve Cryptography. - * The use of ECDSA for TLS is defined in RFC-4492: Elliptic Curve - * Cryptography (ECC) Cipher Suites for Transport Layer Security (TLS). - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_ECDSA_H -#define MBEDTLS_ECDSA_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/ecp.h" -#include "mbedtls/md.h" - -/** - * \brief Maximum ECDSA signature size for a given curve bit size - * - * \param bits Curve size in bits - * \return Maximum signature size in bytes - * - * \note This macro returns a compile-time constant if its argument - * is one. It may evaluate its argument multiple times. - */ -/* - * Ecdsa-Sig-Value ::= SEQUENCE { - * r INTEGER, - * s INTEGER - * } - * - * For each of r and s, the value (V) may include an extra initial "0" bit. - */ -#define MBEDTLS_ECDSA_MAX_SIG_LEN(bits) \ - (/*T,L of SEQUENCE*/ ((bits) >= 61 * 8 ? 3 : 2) + \ - /*T,L of r,s*/ 2 * (((bits) >= 127 * 8 ? 3 : 2) + \ - /*V of r,s*/ ((bits) + 8) / 8)) - -/** The maximal size of an ECDSA signature in Bytes. */ -#define MBEDTLS_ECDSA_MAX_LEN MBEDTLS_ECDSA_MAX_SIG_LEN(MBEDTLS_ECP_MAX_BITS) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief The ECDSA context structure. - * - * \warning Performing multiple operations concurrently on the same - * ECDSA context is not supported; objects of this type - * should not be shared between multiple threads. - * - * \note pk_wrap module assumes that "ecdsa_context" is identical - * to "ecp_keypair" (see for example structure - * "mbedtls_eckey_info" where ECDSA sign/verify functions - * are used also for EC key) - */ -typedef mbedtls_ecp_keypair mbedtls_ecdsa_context; - -#if defined(MBEDTLS_ECP_RESTARTABLE) - -/** - * \brief Internal restart context for ecdsa_verify() - * - * \note Opaque struct, defined in ecdsa.c - */ -typedef struct mbedtls_ecdsa_restart_ver mbedtls_ecdsa_restart_ver_ctx; - -/** - * \brief Internal restart context for ecdsa_sign() - * - * \note Opaque struct, defined in ecdsa.c - */ -typedef struct mbedtls_ecdsa_restart_sig mbedtls_ecdsa_restart_sig_ctx; - -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) -/** - * \brief Internal restart context for ecdsa_sign_det() - * - * \note Opaque struct, defined in ecdsa.c - */ -typedef struct mbedtls_ecdsa_restart_det mbedtls_ecdsa_restart_det_ctx; -#endif - -/** - * \brief General context for resuming ECDSA operations - */ -typedef struct { - mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(ecp); /*!< base context for ECP restart and - shared administrative info */ - mbedtls_ecdsa_restart_ver_ctx *MBEDTLS_PRIVATE(ver); /*!< ecdsa_verify() sub-context */ - mbedtls_ecdsa_restart_sig_ctx *MBEDTLS_PRIVATE(sig); /*!< ecdsa_sign() sub-context */ -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) - mbedtls_ecdsa_restart_det_ctx *MBEDTLS_PRIVATE(det); /*!< ecdsa_sign_det() sub-context */ -#endif -} mbedtls_ecdsa_restart_ctx; - -#else /* MBEDTLS_ECP_RESTARTABLE */ - -/* Now we can declare functions that take a pointer to that */ -typedef void mbedtls_ecdsa_restart_ctx; - -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -/** - * \brief This function checks whether a given group can be used - * for ECDSA. - * - * \param gid The ECP group ID to check. - * - * \return \c 1 if the group can be used, \c 0 otherwise - */ -int mbedtls_ecdsa_can_do(mbedtls_ecp_group_id gid); - -/** - * \brief This function computes the ECDSA signature of a - * previously-hashed message. - * - * \note The deterministic version implemented in - * mbedtls_ecdsa_sign_det_ext() is usually preferred. - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated - * as defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.3, step 5. - * - * \see ecp.h - * - * \param grp The context for the elliptic curve to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param r The MPI context in which to store the first part - * the signature. This must be initialized. - * \param s The MPI context in which to store the second part - * the signature. This must be initialized. - * \param d The private signing key. This must be initialized. - * \param buf The content to be signed. This is usually the hash of - * the original data to be signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context parameter. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX - * or \c MBEDTLS_MPI_XXX error code on failure. - */ -int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, - const mbedtls_mpi *d, const unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) -/** - * \brief This function computes the ECDSA signature of a - * previously-hashed message, deterministic version. - * - * For more information, see RFC-6979: Deterministic - * Usage of the Digital Signature Algorithm (DSA) and Elliptic - * Curve Digital Signature Algorithm (ECDSA). - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated as - * defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.3, step 5. - * - * \see ecp.h - * - * \param grp The context for the elliptic curve to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param r The MPI context in which to store the first part - * the signature. This must be initialized. - * \param s The MPI context in which to store the second part - * the signature. This must be initialized. - * \param d The private signing key. This must be initialized - * and setup, for example through mbedtls_ecp_gen_privkey(). - * \param buf The hashed content to be signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param md_alg The hash algorithm used to hash the original data. - * \param f_rng_blind The RNG function used for blinding. This must not be - * \c NULL. - * \param p_rng_blind The RNG context to be passed to \p f_rng_blind. This - * may be \c NULL if \p f_rng_blind doesn't need a context - * parameter. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX - * error code on failure. - */ -int mbedtls_ecdsa_sign_det_ext(mbedtls_ecp_group *grp, mbedtls_mpi *r, - mbedtls_mpi *s, const mbedtls_mpi *d, - const unsigned char *buf, size_t blen, - mbedtls_md_type_t md_alg, - int (*f_rng_blind)(void *, unsigned char *, size_t), - void *p_rng_blind); -#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ - -#if !defined(MBEDTLS_ECDSA_SIGN_ALT) -/** - * \brief This function computes the ECDSA signature of a - * previously-hashed message, in a restartable way. - * - * \note The deterministic version implemented in - * mbedtls_ecdsa_sign_det_restartable() is usually - * preferred. - * - * \note This function is like \c mbedtls_ecdsa_sign() but - * it can return early and restart according to the - * limit set with \c mbedtls_ecp_set_max_ops() to - * reduce blocking. - * - * \note If the bitlength of the message hash is larger - * than the bitlength of the group order, then the - * hash is truncated as defined in Standards for - * Efficient Cryptography Group (SECG): SEC1 Elliptic - * Curve Cryptography, section 4.1.3, step 5. - * - * \see ecp.h - * - * \param grp The context for the elliptic curve to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param r The MPI context in which to store the first part - * the signature. This must be initialized. - * \param s The MPI context in which to store the second part - * the signature. This must be initialized. - * \param d The private signing key. This must be initialized - * and setup, for example through - * mbedtls_ecp_gen_privkey(). - * \param buf The hashed content to be signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context parameter. - * \param f_rng_blind The RNG function used for blinding. This must not be - * \c NULL. - * \param p_rng_blind The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context parameter. - * \param rs_ctx The restart context to use. This may be \c NULL - * to disable restarting. If it is not \c NULL, it - * must point to an initialized restart context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c - * mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX, \c - * MBEDTLS_ERR_MPI_XXX or \c MBEDTLS_ERR_ASN1_XXX - * error code on failure. - */ -int mbedtls_ecdsa_sign_restartable( - mbedtls_ecp_group *grp, - mbedtls_mpi *r, mbedtls_mpi *s, - const mbedtls_mpi *d, - const unsigned char *buf, size_t blen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - int (*f_rng_blind)(void *, unsigned char *, size_t), - void *p_rng_blind, - mbedtls_ecdsa_restart_ctx *rs_ctx); - -#endif /* !MBEDTLS_ECDSA_SIGN_ALT */ - -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) - -/** - * \brief This function computes the ECDSA signature of a - * previously-hashed message, in a restartable way. - * - * \note This function is like \c - * mbedtls_ecdsa_sign_det_ext() but it can return - * early and restart according to the limit set with - * \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \note If the bitlength of the message hash is larger - * than the bitlength of the group order, then the - * hash is truncated as defined in Standards for - * Efficient Cryptography Group (SECG): SEC1 Elliptic - * Curve Cryptography, section 4.1.3, step 5. - * - * \see ecp.h - * - * \param grp The context for the elliptic curve to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param r The MPI context in which to store the first part - * the signature. This must be initialized. - * \param s The MPI context in which to store the second part - * the signature. This must be initialized. - * \param d The private signing key. This must be initialized - * and setup, for example through - * mbedtls_ecp_gen_privkey(). - * \param buf The hashed content to be signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param md_alg The hash algorithm used to hash the original data. - * \param f_rng_blind The RNG function used for blinding. This must not be - * \c NULL. - * \param p_rng_blind The RNG context to be passed to \p f_rng_blind. This may be - * \c NULL if \p f_rng_blind doesn't need a context parameter. - * \param rs_ctx The restart context to use. This may be \c NULL - * to disable restarting. If it is not \c NULL, it - * must point to an initialized restart context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c - * mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX, \c - * MBEDTLS_ERR_MPI_XXX or \c MBEDTLS_ERR_ASN1_XXX - * error code on failure. - */ -int mbedtls_ecdsa_sign_det_restartable( - mbedtls_ecp_group *grp, - mbedtls_mpi *r, mbedtls_mpi *s, - const mbedtls_mpi *d, const unsigned char *buf, size_t blen, - mbedtls_md_type_t md_alg, - int (*f_rng_blind)(void *, unsigned char *, size_t), - void *p_rng_blind, - mbedtls_ecdsa_restart_ctx *rs_ctx); - -#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ - -/** - * \brief This function verifies the ECDSA signature of a - * previously-hashed message. - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated as - * defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.4, step 3. - * - * \see ecp.h - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param buf The hashed content that was signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param Q The public key to use for verification. This must be - * initialized and setup. - * \param r The first integer of the signature. - * This must be initialized. - * \param s The second integer of the signature. - * This must be initialized. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX - * error code on failure. - */ -int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, - const unsigned char *buf, size_t blen, - const mbedtls_ecp_point *Q, const mbedtls_mpi *r, - const mbedtls_mpi *s); - -#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) -/** - * \brief This function verifies the ECDSA signature of a - * previously-hashed message, in a restartable manner - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated as - * defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.4, step 3. - * - * \see ecp.h - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param buf The hashed content that was signed. This must be a readable - * buffer of length \p blen Bytes. It may be \c NULL if - * \p blen is zero. - * \param blen The length of \p buf in Bytes. - * \param Q The public key to use for verification. This must be - * initialized and setup. - * \param r The first integer of the signature. - * This must be initialized. - * \param s The second integer of the signature. - * This must be initialized. - * \param rs_ctx The restart context to use. This may be \c NULL to disable - * restarting. If it is not \c NULL, it must point to an - * initialized restart context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX - * error code on failure. - */ -int mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp, - const unsigned char *buf, size_t blen, - const mbedtls_ecp_point *Q, - const mbedtls_mpi *r, - const mbedtls_mpi *s, - mbedtls_ecdsa_restart_ctx *rs_ctx); - -#endif /* !MBEDTLS_ECDSA_VERIFY_ALT */ - -/** - * \brief This function computes the ECDSA signature and writes it - * to a buffer, serialized as defined in RFC-4492: - * Elliptic Curve Cryptography (ECC) Cipher Suites for - * Transport Layer Security (TLS). - * - * \warning It is not thread-safe to use the same context in - * multiple threads. - * - * \note The deterministic version is used if - * #MBEDTLS_ECDSA_DETERMINISTIC is defined. For more - * information, see RFC-6979: Deterministic Usage - * of the Digital Signature Algorithm (DSA) and Elliptic - * Curve Digital Signature Algorithm (ECDSA). - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated as - * defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.3, step 5. - * - * \see ecp.h - * - * \param ctx The ECDSA context to use. This must be initialized - * and have a group and private key bound to it, for example - * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). - * \param md_alg The message digest that was used to hash the message. - * \param hash The message hash to be signed. This must be a readable - * buffer of length \p hlen Bytes. - * \param hlen The length of the hash \p hash in Bytes. - * \param sig The buffer to which to write the signature. This must be a - * writable buffer of length at least twice as large as the - * size of the curve used, plus 9. For example, 73 Bytes if - * a 256-bit curve is used. A buffer length of - * #MBEDTLS_ECDSA_MAX_LEN is always safe. - * \param sig_size The size of the \p sig buffer in bytes. - * \param slen The address at which to store the actual length of - * the signature written. Must not be \c NULL. - * \param f_rng The RNG function. This must not be \c NULL if - * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, - * it is used only for blinding and may be set to \c NULL, but - * doing so is DEPRECATED. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng is \c NULL or doesn't use a context. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or - * \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_ecdsa_write_signature(mbedtls_ecdsa_context *ctx, - mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hlen, - unsigned char *sig, size_t sig_size, size_t *slen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function computes the ECDSA signature and writes it - * to a buffer, in a restartable way. - * - * \see \c mbedtls_ecdsa_write_signature() - * - * \note This function is like \c mbedtls_ecdsa_write_signature() - * but it can return early and restart according to the limit - * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \param ctx The ECDSA context to use. This must be initialized - * and have a group and private key bound to it, for example - * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). - * \param md_alg The message digest that was used to hash the message. - * \param hash The message hash to be signed. This must be a readable - * buffer of length \p hlen Bytes. - * \param hlen The length of the hash \p hash in Bytes. - * \param sig The buffer to which to write the signature. This must be a - * writable buffer of length at least twice as large as the - * size of the curve used, plus 9. For example, 73 Bytes if - * a 256-bit curve is used. A buffer length of - * #MBEDTLS_ECDSA_MAX_LEN is always safe. - * \param sig_size The size of the \p sig buffer in bytes. - * \param slen The address at which to store the actual length of - * the signature written. Must not be \c NULL. - * \param f_rng The RNG function. This must not be \c NULL if - * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, - * it is unused and may be set to \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng is \c NULL or doesn't use a context. - * \param rs_ctx The restart context to use. This may be \c NULL to disable - * restarting. If it is not \c NULL, it must point to an - * initialized restart context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or - * \c MBEDTLS_ERR_ASN1_XXX error code on failure. - */ -int mbedtls_ecdsa_write_signature_restartable(mbedtls_ecdsa_context *ctx, - mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hlen, - unsigned char *sig, size_t sig_size, size_t *slen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_ecdsa_restart_ctx *rs_ctx); - -/** - * \brief This function reads and verifies an ECDSA signature. - * - * \note If the bitlength of the message hash is larger than the - * bitlength of the group order, then the hash is truncated as - * defined in Standards for Efficient Cryptography Group - * (SECG): SEC1 Elliptic Curve Cryptography, section - * 4.1.4, step 3. - * - * \see ecp.h - * - * \param ctx The ECDSA context to use. This must be initialized - * and have a group and public key bound to it. - * \param hash The message hash that was signed. This must be a readable - * buffer of length \p hlen Bytes. - * \param hlen The size of the hash \p hash. - * \param sig The signature to read and verify. This must be a readable - * buffer of length \p slen Bytes. - * \param slen The size of \p sig in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. - * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid - * signature in \p sig, but its length is less than \p siglen. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX - * error code on failure for any other reason. - */ -int mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx, - const unsigned char *hash, size_t hlen, - const unsigned char *sig, size_t slen); - -/** - * \brief This function reads and verifies an ECDSA signature, - * in a restartable way. - * - * \see \c mbedtls_ecdsa_read_signature() - * - * \note This function is like \c mbedtls_ecdsa_read_signature() - * but it can return early and restart according to the limit - * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \param ctx The ECDSA context to use. This must be initialized - * and have a group and public key bound to it. - * \param hash The message hash that was signed. This must be a readable - * buffer of length \p hlen Bytes. - * \param hlen The size of the hash \p hash. - * \param sig The signature to read and verify. This must be a readable - * buffer of length \p slen Bytes. - * \param slen The size of \p sig in Bytes. - * \param rs_ctx The restart context to use. This may be \c NULL to disable - * restarting. If it is not \c NULL, it must point to an - * initialized restart context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. - * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid - * signature in \p sig, but its length is less than \p siglen. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX - * error code on failure for any other reason. - */ -int mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx, - const unsigned char *hash, size_t hlen, - const unsigned char *sig, size_t slen, - mbedtls_ecdsa_restart_ctx *rs_ctx); - -/** - * \brief This function generates an ECDSA keypair on the given curve. - * - * \see ecp.h - * - * \param ctx The ECDSA context to store the keypair in. - * This must be initialized. - * \param gid The elliptic curve to use. One of the various - * \c MBEDTLS_ECP_DP_XXX macros depending on configuration. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. - */ -int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** - * \brief This function sets up an ECDSA context from an EC key pair. - * - * \see ecp.h - * - * \param ctx The ECDSA context to setup. This must be initialized. - * \param key The EC key to use. This must be initialized and hold - * a private-public key pair or a public key. In the former - * case, the ECDSA context may be used for signature creation - * and verification after this call. In the latter case, it - * may be used for signature verification. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. - */ -int mbedtls_ecdsa_from_keypair(mbedtls_ecdsa_context *ctx, - const mbedtls_ecp_keypair *key); - -/** - * \brief This function initializes an ECDSA context. - * - * \param ctx The ECDSA context to initialize. - * This must not be \c NULL. - */ -void mbedtls_ecdsa_init(mbedtls_ecdsa_context *ctx); - -/** - * \brief This function frees an ECDSA context. - * - * \param ctx The ECDSA context to free. This may be \c NULL, - * in which case this function does nothing. If it - * is not \c NULL, it must be initialized. - */ -void mbedtls_ecdsa_free(mbedtls_ecdsa_context *ctx); - -#if defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Initialize a restart context. - * - * \param ctx The restart context to initialize. - * This must not be \c NULL. - */ -void mbedtls_ecdsa_restart_init(mbedtls_ecdsa_restart_ctx *ctx); - -/** - * \brief Free the components of a restart context. - * - * \param ctx The restart context to free. This may be \c NULL, - * in which case this function does nothing. If it - * is not \c NULL, it must be initialized. - */ -void mbedtls_ecdsa_restart_free(mbedtls_ecdsa_restart_ctx *ctx); -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -#ifdef __cplusplus -} -#endif - -#endif /* ecdsa.h */ +/** + * \file ecdsa.h + * + * \brief This file contains ECDSA definitions and functions. + * + * The Elliptic Curve Digital Signature Algorithm (ECDSA) is defined in + * Standards for Efficient Cryptography Group (SECG): + * SEC1 Elliptic Curve Cryptography. + * The use of ECDSA for TLS is defined in RFC-4492: Elliptic Curve + * Cryptography (ECC) Cipher Suites for Transport Layer Security (TLS). + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_ECDSA_H +#define MBEDTLS_ECDSA_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/ecp.h" +#include "mbedtls/md.h" + +/** + * \brief Maximum ECDSA signature size for a given curve bit size + * + * \param bits Curve size in bits + * \return Maximum signature size in bytes + * + * \note This macro returns a compile-time constant if its argument + * is one. It may evaluate its argument multiple times. + */ +/* + * Ecdsa-Sig-Value ::= SEQUENCE { + * r INTEGER, + * s INTEGER + * } + * + * For each of r and s, the value (V) may include an extra initial "0" bit. + */ +#define MBEDTLS_ECDSA_MAX_SIG_LEN(bits) \ + (/*T,L of SEQUENCE*/ ((bits) >= 61 * 8 ? 3 : 2) + \ + /*T,L of r,s*/ 2 * (((bits) >= 127 * 8 ? 3 : 2) + \ + /*V of r,s*/ ((bits) + 8) / 8)) + +/** The maximal size of an ECDSA signature in Bytes. */ +#define MBEDTLS_ECDSA_MAX_LEN MBEDTLS_ECDSA_MAX_SIG_LEN(MBEDTLS_ECP_MAX_BITS) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief The ECDSA context structure. + * + * \warning Performing multiple operations concurrently on the same + * ECDSA context is not supported; objects of this type + * should not be shared between multiple threads. + * + * \note pk_wrap module assumes that "ecdsa_context" is identical + * to "ecp_keypair" (see for example structure + * "mbedtls_eckey_info" where ECDSA sign/verify functions + * are used also for EC key) + */ +typedef mbedtls_ecp_keypair mbedtls_ecdsa_context; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Internal restart context for ecdsa_verify() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_ver mbedtls_ecdsa_restart_ver_ctx; + +/** + * \brief Internal restart context for ecdsa_sign() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_sig mbedtls_ecdsa_restart_sig_ctx; + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/** + * \brief Internal restart context for ecdsa_sign_det() + * + * \note Opaque struct, defined in ecdsa.c + */ +typedef struct mbedtls_ecdsa_restart_det mbedtls_ecdsa_restart_det_ctx; +#endif + +/** + * \brief General context for resuming ECDSA operations + */ +typedef struct { + mbedtls_ecp_restart_ctx MBEDTLS_PRIVATE(ecp); /*!< base context for ECP restart and + shared administrative info */ + mbedtls_ecdsa_restart_ver_ctx *MBEDTLS_PRIVATE(ver); /*!< ecdsa_verify() sub-context */ + mbedtls_ecdsa_restart_sig_ctx *MBEDTLS_PRIVATE(sig); /*!< ecdsa_sign() sub-context */ +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + mbedtls_ecdsa_restart_det_ctx *MBEDTLS_PRIVATE(det); /*!< ecdsa_sign_det() sub-context */ +#endif +} mbedtls_ecdsa_restart_ctx; + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_ecdsa_restart_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief This function checks whether a given group can be used + * for ECDSA. + * + * \param gid The ECP group ID to check. + * + * \return \c 1 if the group can be used, \c 0 otherwise + */ +int mbedtls_ecdsa_can_do(mbedtls_ecp_group_id gid); + +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message. + * + * \note The deterministic version implemented in + * mbedtls_ecdsa_sign_det_ext() is usually preferred. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated + * as defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized. + * \param buf The content to be signed. This is usually the hash of + * the original data to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX + * or \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdsa_sign(mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message, deterministic version. + * + * For more information, see RFC-6979: Deterministic + * Usage of the Digital Signature Algorithm (DSA) and Elliptic + * Curve Digital Signature Algorithm (ECDSA). + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized + * and setup, for example through mbedtls_ecp_gen_privkey(). + * \param buf The hashed content to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param md_alg The hash algorithm used to hash the original data. + * \param f_rng_blind The RNG function used for blinding. This must not be + * \c NULL. + * \param p_rng_blind The RNG context to be passed to \p f_rng_blind. This + * may be \c NULL if \p f_rng_blind doesn't need a context + * parameter. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure. + */ +int mbedtls_ecdsa_sign_det_ext(mbedtls_ecp_group *grp, mbedtls_mpi *r, + mbedtls_mpi *s, const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg, + int (*f_rng_blind)(void *, unsigned char *, size_t), + void *p_rng_blind); +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#if !defined(MBEDTLS_ECDSA_SIGN_ALT) +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message, in a restartable way. + * + * \note The deterministic version implemented in + * mbedtls_ecdsa_sign_det_restartable() is usually + * preferred. + * + * \note This function is like \c mbedtls_ecdsa_sign() but + * it can return early and restart according to the + * limit set with \c mbedtls_ecp_set_max_ops() to + * reduce blocking. + * + * \note If the bitlength of the message hash is larger + * than the bitlength of the group order, then the + * hash is truncated as defined in Standards for + * Efficient Cryptography Group (SECG): SEC1 Elliptic + * Curve Cryptography, section 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized + * and setup, for example through + * mbedtls_ecp_gen_privkey(). + * \param buf The hashed content to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * \param f_rng_blind The RNG function used for blinding. This must not be + * \c NULL. + * \param p_rng_blind The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context parameter. + * \param rs_ctx The restart context to use. This may be \c NULL + * to disable restarting. If it is not \c NULL, it + * must point to an initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c + * mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX, \c + * MBEDTLS_ERR_MPI_XXX or \c MBEDTLS_ERR_ASN1_XXX + * error code on failure. + */ +int mbedtls_ecdsa_sign_restartable( + mbedtls_ecp_group *grp, + mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, + const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int (*f_rng_blind)(void *, unsigned char *, size_t), + void *p_rng_blind, + mbedtls_ecdsa_restart_ctx *rs_ctx); + +#endif /* !MBEDTLS_ECDSA_SIGN_ALT */ + +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) + +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message, in a restartable way. + * + * \note This function is like \c + * mbedtls_ecdsa_sign_det_ext() but it can return + * early and restart according to the limit set with + * \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \note If the bitlength of the message hash is larger + * than the bitlength of the group order, then the + * hash is truncated as defined in Standards for + * Efficient Cryptography Group (SECG): SEC1 Elliptic + * Curve Cryptography, section 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The context for the elliptic curve to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param r The MPI context in which to store the first part + * the signature. This must be initialized. + * \param s The MPI context in which to store the second part + * the signature. This must be initialized. + * \param d The private signing key. This must be initialized + * and setup, for example through + * mbedtls_ecp_gen_privkey(). + * \param buf The hashed content to be signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param md_alg The hash algorithm used to hash the original data. + * \param f_rng_blind The RNG function used for blinding. This must not be + * \c NULL. + * \param p_rng_blind The RNG context to be passed to \p f_rng_blind. This may be + * \c NULL if \p f_rng_blind doesn't need a context parameter. + * \param rs_ctx The restart context to use. This may be \c NULL + * to disable restarting. If it is not \c NULL, it + * must point to an initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c + * mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX, \c + * MBEDTLS_ERR_MPI_XXX or \c MBEDTLS_ERR_ASN1_XXX + * error code on failure. + */ +int mbedtls_ecdsa_sign_det_restartable( + mbedtls_ecp_group *grp, + mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + mbedtls_md_type_t md_alg, + int (*f_rng_blind)(void *, unsigned char *, size_t), + void *p_rng_blind, + mbedtls_ecdsa_restart_ctx *rs_ctx); + +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +/** + * \brief This function verifies the ECDSA signature of a + * previously-hashed message. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.4, step 3. + * + * \see ecp.h + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param buf The hashed content that was signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param Q The public key to use for verification. This must be + * initialized and setup. + * \param r The first integer of the signature. + * This must be initialized. + * \param s The second integer of the signature. + * This must be initialized. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure. + */ +int mbedtls_ecdsa_verify(mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, const mbedtls_mpi *r, + const mbedtls_mpi *s); + +#if !defined(MBEDTLS_ECDSA_VERIFY_ALT) +/** + * \brief This function verifies the ECDSA signature of a + * previously-hashed message, in a restartable manner + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.4, step 3. + * + * \see ecp.h + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param buf The hashed content that was signed. This must be a readable + * buffer of length \p blen Bytes. It may be \c NULL if + * \p blen is zero. + * \param blen The length of \p buf in Bytes. + * \param Q The public key to use for verification. This must be + * initialized and setup. + * \param r The first integer of the signature. + * This must be initialized. + * \param s The second integer of the signature. + * This must be initialized. + * \param rs_ctx The restart context to use. This may be \c NULL to disable + * restarting. If it is not \c NULL, it must point to an + * initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX + * error code on failure. + */ +int mbedtls_ecdsa_verify_restartable(mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *r, + const mbedtls_mpi *s, + mbedtls_ecdsa_restart_ctx *rs_ctx); + +#endif /* !MBEDTLS_ECDSA_VERIFY_ALT */ + +/** + * \brief This function computes the ECDSA signature and writes it + * to a buffer, serialized as defined in RFC-4492: + * Elliptic Curve Cryptography (ECC) Cipher Suites for + * Transport Layer Security (TLS). + * + * \warning It is not thread-safe to use the same context in + * multiple threads. + * + * \note The deterministic version is used if + * #MBEDTLS_ECDSA_DETERMINISTIC is defined. For more + * information, see RFC-6979: Deterministic Usage + * of the Digital Signature Algorithm (DSA) and Elliptic + * Curve Digital Signature Algorithm (ECDSA). + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and private key bound to it, for example + * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). + * \param md_alg The message digest that was used to hash the message. + * \param hash The message hash to be signed. This must be a readable + * buffer of length \p hlen Bytes. + * \param hlen The length of the hash \p hash in Bytes. + * \param sig The buffer to which to write the signature. This must be a + * writable buffer of length at least twice as large as the + * size of the curve used, plus 9. For example, 73 Bytes if + * a 256-bit curve is used. A buffer length of + * #MBEDTLS_ECDSA_MAX_LEN is always safe. + * \param sig_size The size of the \p sig buffer in bytes. + * \param slen The address at which to store the actual length of + * the signature written. Must not be \c NULL. + * \param f_rng The RNG function. This must not be \c NULL if + * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, + * it is used only for blinding and may be set to \c NULL, but + * doing so is DEPRECATED. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't use a context. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or + * \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_ecdsa_write_signature(mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t sig_size, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function computes the ECDSA signature and writes it + * to a buffer, in a restartable way. + * + * \see \c mbedtls_ecdsa_write_signature() + * + * \note This function is like \c mbedtls_ecdsa_write_signature() + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and private key bound to it, for example + * via mbedtls_ecdsa_genkey() or mbedtls_ecdsa_from_keypair(). + * \param md_alg The message digest that was used to hash the message. + * \param hash The message hash to be signed. This must be a readable + * buffer of length \p hlen Bytes. + * \param hlen The length of the hash \p hash in Bytes. + * \param sig The buffer to which to write the signature. This must be a + * writable buffer of length at least twice as large as the + * size of the curve used, plus 9. For example, 73 Bytes if + * a 256-bit curve is used. A buffer length of + * #MBEDTLS_ECDSA_MAX_LEN is always safe. + * \param sig_size The size of the \p sig buffer in bytes. + * \param slen The address at which to store the actual length of + * the signature written. Must not be \c NULL. + * \param f_rng The RNG function. This must not be \c NULL if + * #MBEDTLS_ECDSA_DETERMINISTIC is unset. Otherwise, + * it is unused and may be set to \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng is \c NULL or doesn't use a context. + * \param rs_ctx The restart context to use. This may be \c NULL to disable + * restarting. If it is not \c NULL, it must point to an + * initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX, \c MBEDTLS_ERR_MPI_XXX or + * \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_ecdsa_write_signature_restartable(mbedtls_ecdsa_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hlen, + unsigned char *sig, size_t sig_size, size_t *slen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecdsa_restart_ctx *rs_ctx); + +/** + * \brief This function reads and verifies an ECDSA signature. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated as + * defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.4, step 3. + * + * \see ecp.h + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and public key bound to it. + * \param hash The message hash that was signed. This must be a readable + * buffer of length \p hlen Bytes. + * \param hlen The size of the hash \p hash. + * \param sig The signature to read and verify. This must be a readable + * buffer of length \p slen Bytes. + * \param slen The size of \p sig in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. + * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig, but its length is less than \p siglen. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX + * error code on failure for any other reason. + */ +int mbedtls_ecdsa_read_signature(mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen); + +/** + * \brief This function reads and verifies an ECDSA signature, + * in a restartable way. + * + * \see \c mbedtls_ecdsa_read_signature() + * + * \note This function is like \c mbedtls_ecdsa_read_signature() + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param ctx The ECDSA context to use. This must be initialized + * and have a group and public key bound to it. + * \param hash The message hash that was signed. This must be a readable + * buffer of length \p hlen Bytes. + * \param hlen The size of the hash \p hash. + * \param sig The signature to read and verify. This must be a readable + * buffer of length \p slen Bytes. + * \param slen The size of \p sig in Bytes. + * \param rs_ctx The restart context to use. This may be \c NULL to disable + * restarting. If it is not \c NULL, it must point to an + * initialized restart context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if signature is invalid. + * \return #MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig, but its length is less than \p siglen. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_ERR_MPI_XXX + * error code on failure for any other reason. + */ +int mbedtls_ecdsa_read_signature_restartable(mbedtls_ecdsa_context *ctx, + const unsigned char *hash, size_t hlen, + const unsigned char *sig, size_t slen, + mbedtls_ecdsa_restart_ctx *rs_ctx); + +/** + * \brief This function generates an ECDSA keypair on the given curve. + * + * \see ecp.h + * + * \param ctx The ECDSA context to store the keypair in. + * This must be initialized. + * \param gid The elliptic curve to use. One of the various + * \c MBEDTLS_ECP_DP_XXX macros depending on configuration. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. + */ +int mbedtls_ecdsa_genkey(mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** + * \brief This function sets up an ECDSA context from an EC key pair. + * + * \see ecp.h + * + * \param ctx The ECDSA context to setup. This must be initialized. + * \param key The EC key to use. This must be initialized and hold + * a private-public key pair or a public key. In the former + * case, the ECDSA context may be used for signature creation + * and verification after this call. In the latter case, it + * may be used for signature verification. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX code on failure. + */ +int mbedtls_ecdsa_from_keypair(mbedtls_ecdsa_context *ctx, + const mbedtls_ecp_keypair *key); + +/** + * \brief This function initializes an ECDSA context. + * + * \param ctx The ECDSA context to initialize. + * This must not be \c NULL. + */ +void mbedtls_ecdsa_init(mbedtls_ecdsa_context *ctx); + +/** + * \brief This function frees an ECDSA context. + * + * \param ctx The ECDSA context to free. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must be initialized. + */ +void mbedtls_ecdsa_free(mbedtls_ecdsa_context *ctx); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context. + * + * \param ctx The restart context to initialize. + * This must not be \c NULL. + */ +void mbedtls_ecdsa_restart_init(mbedtls_ecdsa_restart_ctx *ctx); + +/** + * \brief Free the components of a restart context. + * + * \param ctx The restart context to free. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must be initialized. + */ +void mbedtls_ecdsa_restart_free(mbedtls_ecdsa_restart_ctx *ctx); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecdsa.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecjpake.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecjpake.h index 0008d73..ee2d05d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecjpake.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecjpake.h @@ -1,310 +1,310 @@ -/** - * \file ecjpake.h - * - * \brief Elliptic curve J-PAKE - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ECJPAKE_H -#define MBEDTLS_ECJPAKE_H -#include "mbedtls/private_access.h" - -/* - * J-PAKE is a password-authenticated key exchange that allows deriving a - * strong shared secret from a (potentially low entropy) pre-shared - * passphrase, with forward secrecy and mutual authentication. - * https://en.wikipedia.org/wiki/Password_Authenticated_Key_Exchange_by_Juggling - * - * This file implements the Elliptic Curve variant of J-PAKE, - * as defined in Chapter 7.4 of the Thread v1.0 Specification, - * available to members of the Thread Group http://threadgroup.org/ - * - * As the J-PAKE algorithm is inherently symmetric, so is our API. - * Each party needs to send its first round message, in any order, to the - * other party, then each sends its second round message, in any order. - * The payloads are serialized in a way suitable for use in TLS, but could - * also be use outside TLS. - */ -#include "mbedtls/build_info.h" - -#include "mbedtls/ecp.h" -#include "mbedtls/md.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Roles in the EC J-PAKE exchange - */ -typedef enum { - MBEDTLS_ECJPAKE_CLIENT = 0, /**< Client */ - MBEDTLS_ECJPAKE_SERVER, /**< Server */ - MBEDTLS_ECJPAKE_NONE, /**< Undefined */ -} mbedtls_ecjpake_role; - -#if !defined(MBEDTLS_ECJPAKE_ALT) -/** - * EC J-PAKE context structure. - * - * J-PAKE is a symmetric protocol, except for the identifiers used in - * Zero-Knowledge Proofs, and the serialization of the second message - * (KeyExchange) as defined by the Thread spec. - * - * In order to benefit from this symmetry, we choose a different naming - * convention from the Thread v1.0 spec. Correspondence is indicated in the - * description as a pair C: client name, S: server name - */ -typedef struct mbedtls_ecjpake_context { - mbedtls_md_type_t MBEDTLS_PRIVATE(md_type); /**< Hash to use */ - mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /**< Elliptic curve */ - mbedtls_ecjpake_role MBEDTLS_PRIVATE(role); /**< Are we client or server? */ - int MBEDTLS_PRIVATE(point_format); /**< Format for point export */ - - mbedtls_ecp_point MBEDTLS_PRIVATE(Xm1); /**< My public key 1 C: X1, S: X3 */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Xm2); /**< My public key 2 C: X2, S: X4 */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Xp1); /**< Peer public key 1 C: X3, S: X1 */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Xp2); /**< Peer public key 2 C: X4, S: X2 */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Xp); /**< Peer public key C: Xs, S: Xc */ - - mbedtls_mpi MBEDTLS_PRIVATE(xm1); /**< My private key 1 C: x1, S: x3 */ - mbedtls_mpi MBEDTLS_PRIVATE(xm2); /**< My private key 2 C: x2, S: x4 */ - - mbedtls_mpi MBEDTLS_PRIVATE(s); /**< Pre-shared secret (passphrase) */ -} mbedtls_ecjpake_context; - -#else /* MBEDTLS_ECJPAKE_ALT */ -#include "ecjpake_alt.h" -#endif /* MBEDTLS_ECJPAKE_ALT */ - -/** - * \brief Initialize an ECJPAKE context. - * - * \param ctx The ECJPAKE context to initialize. - * This must not be \c NULL. - */ -void mbedtls_ecjpake_init(mbedtls_ecjpake_context *ctx); - -/** - * \brief Set up an ECJPAKE context for use. - * - * \note Currently the only values for hash/curve allowed by the - * standard are #MBEDTLS_MD_SHA256/#MBEDTLS_ECP_DP_SECP256R1. - * - * \param ctx The ECJPAKE context to set up. This must be initialized. - * \param role The role of the caller. This must be either - * #MBEDTLS_ECJPAKE_CLIENT or #MBEDTLS_ECJPAKE_SERVER. - * \param hash The identifier of the hash function to use, - * for example #MBEDTLS_MD_SHA256. - * \param curve The identifier of the elliptic curve to use, - * for example #MBEDTLS_ECP_DP_SECP256R1. - * \param secret The pre-shared secret (passphrase). This must be - * a readable not empty buffer of length \p len Bytes. It need - * only be valid for the duration of this call. - * \param len The length of the pre-shared secret \p secret. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_setup(mbedtls_ecjpake_context *ctx, - mbedtls_ecjpake_role role, - mbedtls_md_type_t hash, - mbedtls_ecp_group_id curve, - const unsigned char *secret, - size_t len); - -/** - * \brief Set the point format for future reads and writes. - * - * \param ctx The ECJPAKE context to configure. - * \param point_format The point format to use: - * #MBEDTLS_ECP_PF_UNCOMPRESSED (default) - * or #MBEDTLS_ECP_PF_COMPRESSED. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p point_format - * is invalid. - */ -int mbedtls_ecjpake_set_point_format(mbedtls_ecjpake_context *ctx, - int point_format); - -/** - * \brief Check if an ECJPAKE context is ready for use. - * - * \param ctx The ECJPAKE context to check. This must be - * initialized. - * - * \return \c 0 if the context is ready for use. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA otherwise. - */ -int mbedtls_ecjpake_check(const mbedtls_ecjpake_context *ctx); - -/** - * \brief Generate and write the first round message - * (TLS: contents of the Client/ServerHello extension, - * excluding extension type and length bytes). - * - * \param ctx The ECJPAKE context to use. This must be - * initialized and set up. - * \param buf The buffer to write the contents to. This must be a - * writable buffer of length \p len Bytes. - * \param len The length of \p buf in Bytes. - * \param olen The address at which to store the total number - * of Bytes written to \p buf. This must not be \c NULL. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This - * may be \c NULL if \p f_rng doesn't use a context. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_write_round_one(mbedtls_ecjpake_context *ctx, - unsigned char *buf, size_t len, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Read and process the first round message - * (TLS: contents of the Client/ServerHello extension, - * excluding extension type and length bytes). - * - * \param ctx The ECJPAKE context to use. This must be initialized - * and set up. - * \param buf The buffer holding the first round message. This must - * be a readable buffer of length \p len Bytes. - * \param len The length in Bytes of \p buf. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_read_round_one(mbedtls_ecjpake_context *ctx, - const unsigned char *buf, - size_t len); - -/** - * \brief Generate and write the second round message - * (TLS: contents of the Client/ServerKeyExchange). - * - * \param ctx The ECJPAKE context to use. This must be initialized, - * set up, and already have performed round one. - * \param buf The buffer to write the round two contents to. - * This must be a writable buffer of length \p len Bytes. - * \param len The size of \p buf in Bytes. - * \param olen The address at which to store the total number of Bytes - * written to \p buf. This must not be \c NULL. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This - * may be \c NULL if \p f_rng doesn't use a context. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_write_round_two(mbedtls_ecjpake_context *ctx, - unsigned char *buf, size_t len, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Read and process the second round message - * (TLS: contents of the Client/ServerKeyExchange). - * - * \param ctx The ECJPAKE context to use. This must be initialized - * and set up and already have performed round one. - * \param buf The buffer holding the second round message. This must - * be a readable buffer of length \p len Bytes. - * \param len The length in Bytes of \p buf. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_read_round_two(mbedtls_ecjpake_context *ctx, - const unsigned char *buf, - size_t len); - -/** - * \brief Derive the shared secret - * (TLS: Pre-Master Secret). - * - * \param ctx The ECJPAKE context to use. This must be initialized, - * set up and have performed both round one and two. - * \param buf The buffer to write the derived secret to. This must - * be a writable buffer of length \p len Bytes. - * \param len The length of \p buf in Bytes. - * \param olen The address at which to store the total number of Bytes - * written to \p buf. This must not be \c NULL. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This - * may be \c NULL if \p f_rng doesn't use a context. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_derive_secret(mbedtls_ecjpake_context *ctx, - unsigned char *buf, size_t len, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Write the shared key material to be passed to a Key - * Derivation Function as described in RFC8236. - * - * \param ctx The ECJPAKE context to use. This must be initialized, - * set up and have performed both round one and two. - * \param buf The buffer to write the derived secret to. This must - * be a writable buffer of length \p len Bytes. - * \param len The length of \p buf in Bytes. - * \param olen The address at which to store the total number of bytes - * written to \p buf. This must not be \c NULL. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This - * may be \c NULL if \p f_rng doesn't use a context. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_ecjpake_write_shared_key(mbedtls_ecjpake_context *ctx, - unsigned char *buf, size_t len, size_t *olen, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This clears an ECJPAKE context and frees any - * embedded data structure. - * - * \param ctx The ECJPAKE context to free. This may be \c NULL, - * in which case this function does nothing. If it is not - * \c NULL, it must point to an initialized ECJPAKE context. - */ -void mbedtls_ecjpake_free(mbedtls_ecjpake_context *ctx); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if a test failed - */ -int mbedtls_ecjpake_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - - -#endif /* ecjpake.h */ +/** + * \file ecjpake.h + * + * \brief Elliptic curve J-PAKE + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ECJPAKE_H +#define MBEDTLS_ECJPAKE_H +#include "mbedtls/private_access.h" + +/* + * J-PAKE is a password-authenticated key exchange that allows deriving a + * strong shared secret from a (potentially low entropy) pre-shared + * passphrase, with forward secrecy and mutual authentication. + * https://en.wikipedia.org/wiki/Password_Authenticated_Key_Exchange_by_Juggling + * + * This file implements the Elliptic Curve variant of J-PAKE, + * as defined in Chapter 7.4 of the Thread v1.0 Specification, + * available to members of the Thread Group http://threadgroup.org/ + * + * As the J-PAKE algorithm is inherently symmetric, so is our API. + * Each party needs to send its first round message, in any order, to the + * other party, then each sends its second round message, in any order. + * The payloads are serialized in a way suitable for use in TLS, but could + * also be use outside TLS. + */ +#include "mbedtls/build_info.h" + +#include "mbedtls/ecp.h" +#include "mbedtls/md.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Roles in the EC J-PAKE exchange + */ +typedef enum { + MBEDTLS_ECJPAKE_CLIENT = 0, /**< Client */ + MBEDTLS_ECJPAKE_SERVER, /**< Server */ + MBEDTLS_ECJPAKE_NONE, /**< Undefined */ +} mbedtls_ecjpake_role; + +#if !defined(MBEDTLS_ECJPAKE_ALT) +/** + * EC J-PAKE context structure. + * + * J-PAKE is a symmetric protocol, except for the identifiers used in + * Zero-Knowledge Proofs, and the serialization of the second message + * (KeyExchange) as defined by the Thread spec. + * + * In order to benefit from this symmetry, we choose a different naming + * convention from the Thread v1.0 spec. Correspondence is indicated in the + * description as a pair C: client name, S: server name + */ +typedef struct mbedtls_ecjpake_context { + mbedtls_md_type_t MBEDTLS_PRIVATE(md_type); /**< Hash to use */ + mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /**< Elliptic curve */ + mbedtls_ecjpake_role MBEDTLS_PRIVATE(role); /**< Are we client or server? */ + int MBEDTLS_PRIVATE(point_format); /**< Format for point export */ + + mbedtls_ecp_point MBEDTLS_PRIVATE(Xm1); /**< My public key 1 C: X1, S: X3 */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Xm2); /**< My public key 2 C: X2, S: X4 */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Xp1); /**< Peer public key 1 C: X3, S: X1 */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Xp2); /**< Peer public key 2 C: X4, S: X2 */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Xp); /**< Peer public key C: Xs, S: Xc */ + + mbedtls_mpi MBEDTLS_PRIVATE(xm1); /**< My private key 1 C: x1, S: x3 */ + mbedtls_mpi MBEDTLS_PRIVATE(xm2); /**< My private key 2 C: x2, S: x4 */ + + mbedtls_mpi MBEDTLS_PRIVATE(s); /**< Pre-shared secret (passphrase) */ +} mbedtls_ecjpake_context; + +#else /* MBEDTLS_ECJPAKE_ALT */ +#include "ecjpake_alt.h" +#endif /* MBEDTLS_ECJPAKE_ALT */ + +/** + * \brief Initialize an ECJPAKE context. + * + * \param ctx The ECJPAKE context to initialize. + * This must not be \c NULL. + */ +void mbedtls_ecjpake_init(mbedtls_ecjpake_context *ctx); + +/** + * \brief Set up an ECJPAKE context for use. + * + * \note Currently the only values for hash/curve allowed by the + * standard are #MBEDTLS_MD_SHA256/#MBEDTLS_ECP_DP_SECP256R1. + * + * \param ctx The ECJPAKE context to set up. This must be initialized. + * \param role The role of the caller. This must be either + * #MBEDTLS_ECJPAKE_CLIENT or #MBEDTLS_ECJPAKE_SERVER. + * \param hash The identifier of the hash function to use, + * for example #MBEDTLS_MD_SHA256. + * \param curve The identifier of the elliptic curve to use, + * for example #MBEDTLS_ECP_DP_SECP256R1. + * \param secret The pre-shared secret (passphrase). This must be + * a readable not empty buffer of length \p len Bytes. It need + * only be valid for the duration of this call. + * \param len The length of the pre-shared secret \p secret. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_setup(mbedtls_ecjpake_context *ctx, + mbedtls_ecjpake_role role, + mbedtls_md_type_t hash, + mbedtls_ecp_group_id curve, + const unsigned char *secret, + size_t len); + +/** + * \brief Set the point format for future reads and writes. + * + * \param ctx The ECJPAKE context to configure. + * \param point_format The point format to use: + * #MBEDTLS_ECP_PF_UNCOMPRESSED (default) + * or #MBEDTLS_ECP_PF_COMPRESSED. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p point_format + * is invalid. + */ +int mbedtls_ecjpake_set_point_format(mbedtls_ecjpake_context *ctx, + int point_format); + +/** + * \brief Check if an ECJPAKE context is ready for use. + * + * \param ctx The ECJPAKE context to check. This must be + * initialized. + * + * \return \c 0 if the context is ready for use. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA otherwise. + */ +int mbedtls_ecjpake_check(const mbedtls_ecjpake_context *ctx); + +/** + * \brief Generate and write the first round message + * (TLS: contents of the Client/ServerHello extension, + * excluding extension type and length bytes). + * + * \param ctx The ECJPAKE context to use. This must be + * initialized and set up. + * \param buf The buffer to write the contents to. This must be a + * writable buffer of length \p len Bytes. + * \param len The length of \p buf in Bytes. + * \param olen The address at which to store the total number + * of Bytes written to \p buf. This must not be \c NULL. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This + * may be \c NULL if \p f_rng doesn't use a context. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_write_round_one(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Read and process the first round message + * (TLS: contents of the Client/ServerHello extension, + * excluding extension type and length bytes). + * + * \param ctx The ECJPAKE context to use. This must be initialized + * and set up. + * \param buf The buffer holding the first round message. This must + * be a readable buffer of length \p len Bytes. + * \param len The length in Bytes of \p buf. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_read_round_one(mbedtls_ecjpake_context *ctx, + const unsigned char *buf, + size_t len); + +/** + * \brief Generate and write the second round message + * (TLS: contents of the Client/ServerKeyExchange). + * + * \param ctx The ECJPAKE context to use. This must be initialized, + * set up, and already have performed round one. + * \param buf The buffer to write the round two contents to. + * This must be a writable buffer of length \p len Bytes. + * \param len The size of \p buf in Bytes. + * \param olen The address at which to store the total number of Bytes + * written to \p buf. This must not be \c NULL. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This + * may be \c NULL if \p f_rng doesn't use a context. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_write_round_two(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Read and process the second round message + * (TLS: contents of the Client/ServerKeyExchange). + * + * \param ctx The ECJPAKE context to use. This must be initialized + * and set up and already have performed round one. + * \param buf The buffer holding the second round message. This must + * be a readable buffer of length \p len Bytes. + * \param len The length in Bytes of \p buf. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_read_round_two(mbedtls_ecjpake_context *ctx, + const unsigned char *buf, + size_t len); + +/** + * \brief Derive the shared secret + * (TLS: Pre-Master Secret). + * + * \param ctx The ECJPAKE context to use. This must be initialized, + * set up and have performed both round one and two. + * \param buf The buffer to write the derived secret to. This must + * be a writable buffer of length \p len Bytes. + * \param len The length of \p buf in Bytes. + * \param olen The address at which to store the total number of Bytes + * written to \p buf. This must not be \c NULL. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This + * may be \c NULL if \p f_rng doesn't use a context. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_derive_secret(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Write the shared key material to be passed to a Key + * Derivation Function as described in RFC8236. + * + * \param ctx The ECJPAKE context to use. This must be initialized, + * set up and have performed both round one and two. + * \param buf The buffer to write the derived secret to. This must + * be a writable buffer of length \p len Bytes. + * \param len The length of \p buf in Bytes. + * \param olen The address at which to store the total number of bytes + * written to \p buf. This must not be \c NULL. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This + * may be \c NULL if \p f_rng doesn't use a context. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_ecjpake_write_shared_key(mbedtls_ecjpake_context *ctx, + unsigned char *buf, size_t len, size_t *olen, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This clears an ECJPAKE context and frees any + * embedded data structure. + * + * \param ctx The ECJPAKE context to free. This may be \c NULL, + * in which case this function does nothing. If it is not + * \c NULL, it must point to an initialized ECJPAKE context. + */ +void mbedtls_ecjpake_free(mbedtls_ecjpake_context *ctx); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_ecjpake_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + + +#endif /* ecjpake.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecp.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecp.h index bf95b90..f5a4cea 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecp.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ecp.h @@ -1,1374 +1,1374 @@ -/** - * \file ecp.h - * - * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). - * - * The use of ECP in cryptography and TLS is defined in - * Standards for Efficient Cryptography Group (SECG): SEC1 - * Elliptic Curve Cryptography and - * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites - * for Transport Layer Security (TLS). - * - * RFC-2409: The Internet Key Exchange (IKE) defines ECP - * group types. - * - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_ECP_H -#define MBEDTLS_ECP_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/bignum.h" - -/* - * ECP error codes - */ -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_ECP_BAD_INPUT_DATA -0x4F80 -/** The buffer is too small to write to. */ -#define MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL -0x4F00 -/** The requested feature is not available, for example, the requested curve is not supported. */ -#define MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE -0x4E80 -/** The signature is not valid. */ -#define MBEDTLS_ERR_ECP_VERIFY_FAILED -0x4E00 -/** Memory allocation failed. */ -#define MBEDTLS_ERR_ECP_ALLOC_FAILED -0x4D80 -/** Generation of random value, such as ephemeral key, failed. */ -#define MBEDTLS_ERR_ECP_RANDOM_FAILED -0x4D00 -/** Invalid private or public key. */ -#define MBEDTLS_ERR_ECP_INVALID_KEY -0x4C80 -/** The buffer contains a valid signature followed by more data. */ -#define MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH -0x4C00 -/** Operation in progress, call again with the same parameters to continue. */ -#define MBEDTLS_ERR_ECP_IN_PROGRESS -0x4B00 - -/* Flags indicating whether to include code that is specific to certain - * types of curves. These flags are for internal library use only. */ -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ - defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) -#define MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED -#endif -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || \ - defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) -#define MBEDTLS_ECP_MONTGOMERY_ENABLED -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Domain-parameter identifiers: curve, subgroup, and generator. - * - * \note Only curves over prime fields are supported. - * - * \warning This library does not support validation of arbitrary domain - * parameters. Therefore, only standardized domain parameters from trusted - * sources should be used. See mbedtls_ecp_group_load(). - */ -/* Note: when adding a new curve: - * - Add it at the end of this enum, otherwise you'll break the ABI by - * changing the numerical value for existing curves. - * - Increment MBEDTLS_ECP_DP_MAX below if needed. - * - Update the calculation of MBEDTLS_ECP_MAX_BITS below. - * - Add the corresponding MBEDTLS_ECP_DP_xxx_ENABLED macro definition to - * mbedtls_config.h. - * - List the curve as a dependency of MBEDTLS_ECP_C and - * MBEDTLS_ECDSA_C if supported in check_config.h. - * - Add the curve to the appropriate curve type macro - * MBEDTLS_ECP_yyy_ENABLED above. - * - Add the necessary definitions to ecp_curves.c. - * - Add the curve to the ecp_supported_curves array in ecp.c. - * - Add the curve to applicable profiles in x509_crt.c. - * - Add the curve to applicable presets in ssl_tls.c. - */ -typedef enum { - MBEDTLS_ECP_DP_NONE = 0, /*!< Curve not defined. */ - MBEDTLS_ECP_DP_SECP192R1, /*!< Domain parameters for the 192-bit curve defined by FIPS 186-4 and SEC1. */ - MBEDTLS_ECP_DP_SECP224R1, /*!< Domain parameters for the 224-bit curve defined by FIPS 186-4 and SEC1. */ - MBEDTLS_ECP_DP_SECP256R1, /*!< Domain parameters for the 256-bit curve defined by FIPS 186-4 and SEC1. */ - MBEDTLS_ECP_DP_SECP384R1, /*!< Domain parameters for the 384-bit curve defined by FIPS 186-4 and SEC1. */ - MBEDTLS_ECP_DP_SECP521R1, /*!< Domain parameters for the 521-bit curve defined by FIPS 186-4 and SEC1. */ - MBEDTLS_ECP_DP_BP256R1, /*!< Domain parameters for 256-bit Brainpool curve. */ - MBEDTLS_ECP_DP_BP384R1, /*!< Domain parameters for 384-bit Brainpool curve. */ - MBEDTLS_ECP_DP_BP512R1, /*!< Domain parameters for 512-bit Brainpool curve. */ - MBEDTLS_ECP_DP_CURVE25519, /*!< Domain parameters for Curve25519. */ - MBEDTLS_ECP_DP_SECP192K1, /*!< Domain parameters for 192-bit "Koblitz" curve. */ - MBEDTLS_ECP_DP_SECP224K1, /*!< Domain parameters for 224-bit "Koblitz" curve. */ - MBEDTLS_ECP_DP_SECP256K1, /*!< Domain parameters for 256-bit "Koblitz" curve. */ - MBEDTLS_ECP_DP_CURVE448, /*!< Domain parameters for Curve448. */ -} mbedtls_ecp_group_id; - -/** - * The number of supported curves, plus one for #MBEDTLS_ECP_DP_NONE. - */ -#define MBEDTLS_ECP_DP_MAX 14 - -/* - * Curve types - */ -typedef enum { - MBEDTLS_ECP_TYPE_NONE = 0, - MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS, /* y^2 = x^3 + a x + b */ - MBEDTLS_ECP_TYPE_MONTGOMERY, /* y^2 = x^3 + a x^2 + x */ -} mbedtls_ecp_curve_type; - -/** - * Curve information, for use by other modules. - * - * The fields of this structure are part of the public API and can be - * accessed directly by applications. Future versions of the library may - * add extra fields or reorder existing fields. - */ -typedef struct mbedtls_ecp_curve_info { - mbedtls_ecp_group_id grp_id; /*!< An internal identifier. */ - uint16_t tls_id; /*!< The TLS NamedCurve identifier. */ - uint16_t bit_size; /*!< The curve size in bits. */ - const char *name; /*!< A human-friendly name. */ -} mbedtls_ecp_curve_info; - -/** - * \brief The ECP point structure, in Jacobian coordinates. - * - * \note All functions expect and return points satisfying - * the following condition: Z == 0 or - * Z == 1. Other values of \p Z are - * used only by internal functions. - * The point is zero, or "at infinity", if Z == 0. - * Otherwise, \p X and \p Y are its standard (affine) - * coordinates. - */ -typedef struct mbedtls_ecp_point { - mbedtls_mpi MBEDTLS_PRIVATE(X); /*!< The X coordinate of the ECP point. */ - mbedtls_mpi MBEDTLS_PRIVATE(Y); /*!< The Y coordinate of the ECP point. */ - mbedtls_mpi MBEDTLS_PRIVATE(Z); /*!< The Z coordinate of the ECP point. */ -} -mbedtls_ecp_point; - -#if !defined(MBEDTLS_ECP_ALT) -/* - * default Mbed TLS elliptic curve arithmetic implementation - * - * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an - * alternative implementation for the whole module and it will replace this - * one.) - */ - -/** - * \brief The ECP group structure. - * - * We consider two types of curve equations: - *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P - * (SEC1 + RFC-4492)
    • - *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, - * Curve448)
- * In both cases, the generator (\p G) for a prime-order subgroup is fixed. - * - * For Short Weierstrass, this subgroup is the whole curve, and its - * cardinality is denoted by \p N. Our code requires that \p N is an - * odd prime as mbedtls_ecp_mul() requires an odd number, and - * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. - * - * The default implementation only initializes \p A without setting it to the - * authentic value for curves with A = -3(SECP256R1, etc), in which - * case you need to load \p A by yourself when using domain parameters directly, - * for example: - * \code - * mbedtls_mpi_init(&A); - * mbedtls_ecp_group_init(&grp); - * CHECK_RETURN(mbedtls_ecp_group_load(&grp, grp_id)); - * if (mbedtls_ecp_group_a_is_minus_3(&grp)) { - * CHECK_RETURN(mbedtls_mpi_sub_int(&A, &grp.P, 3)); - * } else { - * CHECK_RETURN(mbedtls_mpi_copy(&A, &grp.A)); - * } - * - * do_something_with_a(&A); - * - * cleanup: - * mbedtls_mpi_free(&A); - * mbedtls_ecp_group_free(&grp); - * \endcode - * - * For Montgomery curves, we do not store \p A, but (A + 2) / 4, - * which is the quantity used in the formulas. Additionally, \p nbits is - * not the size of \p N but the required size for private keys. - * - * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. - * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the - * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer - * which is congruent mod \p P to the given MPI, and is close enough to \p pbits - * in size, so that it may be efficiently brought in the 0..P-1 range by a few - * additions or subtractions. Therefore, it is only an approximative modular - * reduction. It must return 0 on success and non-zero on failure. - * - * \note Alternative implementations of the ECP module must obey the - * following constraints. - * * Group IDs must be distinct: if two group structures have - * the same ID, then they must be identical. - * * The fields \c id, \c P, \c A, \c B, \c G, \c N, - * \c pbits and \c nbits must have the same type and semantics - * as in the built-in implementation. - * They must be available for reading, but direct modification - * of these fields does not need to be supported. - * They do not need to be at the same offset in the structure. - */ -typedef struct mbedtls_ecp_group { - mbedtls_ecp_group_id id; /*!< An internal group identifier. */ - mbedtls_mpi P; /*!< The prime modulus of the base field. */ - mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. Note that - \p A is not set to the authentic value in some cases. - Refer to detailed description of ::mbedtls_ecp_group if - using domain parameters in the structure. - For Montgomery curves: (A + 2) / 4. */ - mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. - For Montgomery curves: unused. */ - mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ - mbedtls_mpi N; /*!< The order of \p G. */ - size_t pbits; /*!< The number of bits in \p P.*/ - size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. - For Montgomery curves: the number of bits in the - private keys. */ - /* End of public fields */ - - unsigned int MBEDTLS_PRIVATE(h); /*!< \internal 1 if the constants are static. */ - int(*MBEDTLS_PRIVATE(modp))(mbedtls_mpi *); /*!< The function for fast pseudo-reduction - mod \p P (see above).*/ - int(*MBEDTLS_PRIVATE(t_pre))(mbedtls_ecp_point *, void *); /*!< Unused. */ - int(*MBEDTLS_PRIVATE(t_post))(mbedtls_ecp_point *, void *); /*!< Unused. */ - void *MBEDTLS_PRIVATE(t_data); /*!< Unused. */ - mbedtls_ecp_point *MBEDTLS_PRIVATE(T); /*!< Pre-computed points for ecp_mul_comb(). */ - size_t MBEDTLS_PRIVATE(T_size); /*!< The number of dynamic allocated pre-computed points. */ -} -mbedtls_ecp_group; - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h, or define them using the compiler command line. - * \{ - */ - -#if !defined(MBEDTLS_ECP_WINDOW_SIZE) -/* - * Maximum "window" size used for point multiplication. - * Default: a point where higher memory usage yields diminishing performance - * returns. - * Minimum value: 2. Maximum value: 7. - * - * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) - * points used for point multiplication. This value is directly tied to EC - * peak memory usage, so decreasing it by one should roughly cut memory usage - * by two (if large curves are in use). - * - * Reduction in size may reduce speed, but larger curves are impacted first. - * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): - * w-size: 6 5 4 3 2 - * 521 145 141 135 120 97 - * 384 214 209 198 177 146 - * 256 320 320 303 262 226 - * 224 475 475 453 398 342 - * 192 640 640 633 587 476 - */ -#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< The maximum window size used. */ -#endif /* MBEDTLS_ECP_WINDOW_SIZE */ - -#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) -/* - * Trade code size for speed on fixed-point multiplication. - * - * This speeds up repeated multiplication of the generator (that is, the - * multiplication in ECDSA signatures, and half of the multiplications in - * ECDSA verification and ECDHE) by a factor roughly 3 to 4. - * - * For each n-bit Short Weierstrass curve that is enabled, this adds 4n bytes - * of code size if n < 384 and 8n otherwise. - * - * Change this value to 0 to reduce code size. - */ -#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ -#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ - -/** \} name SECTION: Module settings */ - -#else /* MBEDTLS_ECP_ALT */ -#include "ecp_alt.h" -#endif /* MBEDTLS_ECP_ALT */ - -/** - * The maximum size of the groups, that is, of \c N and \c P. - */ -#if !defined(MBEDTLS_ECP_LIGHT) -/* Dummy definition to help code that has optional ECP support and - * defines an MBEDTLS_ECP_MAX_BYTES-sized array unconditionally. */ -#define MBEDTLS_ECP_MAX_BITS 1 -/* Note: the curves must be listed in DECREASING size! */ -#elif defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 521 -#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 512 -#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 448 -#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 384 -#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 384 -#elif defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 256 -#elif defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 256 -#elif defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 256 -#elif defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 255 -#elif defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 225 // n is slightly above 2^224 -#elif defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 224 -#elif defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 192 -#elif defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) -#define MBEDTLS_ECP_MAX_BITS 192 -#else /* !MBEDTLS_ECP_LIGHT */ -#error "Missing definition of MBEDTLS_ECP_MAX_BITS" -#endif /* !MBEDTLS_ECP_LIGHT */ - -#define MBEDTLS_ECP_MAX_BYTES ((MBEDTLS_ECP_MAX_BITS + 7) / 8) -#define MBEDTLS_ECP_MAX_PT_LEN (2 * MBEDTLS_ECP_MAX_BYTES + 1) - -#if defined(MBEDTLS_ECP_RESTARTABLE) - -/** - * \brief Internal restart context for multiplication - * - * \note Opaque struct - */ -typedef struct mbedtls_ecp_restart_mul mbedtls_ecp_restart_mul_ctx; - -/** - * \brief Internal restart context for ecp_muladd() - * - * \note Opaque struct - */ -typedef struct mbedtls_ecp_restart_muladd mbedtls_ecp_restart_muladd_ctx; - -/** - * \brief General context for resuming ECC operations - */ -typedef struct { - unsigned MBEDTLS_PRIVATE(ops_done); /*!< current ops count */ - unsigned MBEDTLS_PRIVATE(depth); /*!< call depth (0 = top-level) */ - mbedtls_ecp_restart_mul_ctx *MBEDTLS_PRIVATE(rsm); /*!< ecp_mul_comb() sub-context */ - mbedtls_ecp_restart_muladd_ctx *MBEDTLS_PRIVATE(ma); /*!< ecp_muladd() sub-context */ -} mbedtls_ecp_restart_ctx; - -/* - * Operation counts for restartable functions - */ -#define MBEDTLS_ECP_OPS_CHK 3 /*!< basic ops count for ecp_check_pubkey() */ -#define MBEDTLS_ECP_OPS_DBL 8 /*!< basic ops count for ecp_double_jac() */ -#define MBEDTLS_ECP_OPS_ADD 11 /*!< basic ops count for see ecp_add_mixed() */ -#define MBEDTLS_ECP_OPS_INV 120 /*!< empirical equivalent for mpi_mod_inv() */ - -/** - * \brief Internal; for restartable functions in other modules. - * Check and update basic ops budget. - * - * \param grp Group structure - * \param rs_ctx Restart context - * \param ops Number of basic ops to do - * - * \return \c 0 if doing \p ops basic ops is still allowed, - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS otherwise. - */ -int mbedtls_ecp_check_budget(const mbedtls_ecp_group *grp, - mbedtls_ecp_restart_ctx *rs_ctx, - unsigned ops); - -/* Utility macro for checking and updating ops budget */ -#define MBEDTLS_ECP_BUDGET(ops) \ - MBEDTLS_MPI_CHK(mbedtls_ecp_check_budget(grp, rs_ctx, \ - (unsigned) (ops))); - -#else /* MBEDTLS_ECP_RESTARTABLE */ - -#define MBEDTLS_ECP_BUDGET(ops) /* no-op; for compatibility */ - -/* We want to declare restartable versions of existing functions anyway */ -typedef void mbedtls_ecp_restart_ctx; - -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -/** - * \brief The ECP key-pair structure. - * - * A generic key-pair that may be used for ECDSA and fixed ECDH, for example. - * - * \note Members are deliberately in the same order as in the - * ::mbedtls_ecdsa_context structure. - */ -typedef struct mbedtls_ecp_keypair { - mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< Elliptic curve and base point */ - mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< our secret value */ - mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< our public value */ -} -mbedtls_ecp_keypair; - -/** - * The uncompressed point format for Short Weierstrass curves - * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX). - */ -#define MBEDTLS_ECP_PF_UNCOMPRESSED 0 -/** - * The compressed point format for Short Weierstrass curves - * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX). - * - * \warning While this format is supported for all concerned curves for - * writing, when it comes to parsing, it is not supported for all - * curves. Specifically, parsing compressed points on - * MBEDTLS_ECP_DP_SECP224R1 and MBEDTLS_ECP_DP_SECP224K1 is not - * supported. - */ -#define MBEDTLS_ECP_PF_COMPRESSED 1 - -/* - * Some other constants from RFC 4492 - */ -#define MBEDTLS_ECP_TLS_NAMED_CURVE 3 /**< The named_curve of ECCurveType. */ - -#if defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Set the maximum number of basic operations done in a row. - * - * If more operations are needed to complete a computation, - * #MBEDTLS_ERR_ECP_IN_PROGRESS will be returned by the - * function performing the computation. It is then the - * caller's responsibility to either call again with the same - * parameters until it returns 0 or an error code; or to free - * the restart context if the operation is to be aborted. - * - * It is strictly required that all input parameters and the - * restart context be the same on successive calls for the - * same operation, but output parameters need not be the - * same; they must not be used until the function finally - * returns 0. - * - * This only applies to functions whose documentation - * mentions they may return #MBEDTLS_ERR_ECP_IN_PROGRESS (or - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS for functions in the - * SSL module). For functions that accept a "restart context" - * argument, passing NULL disables restart and makes the - * function equivalent to the function with the same name - * with \c _restartable removed. For functions in the ECDH - * module, restart is disabled unless the function accepts - * an "ECDH context" argument and - * mbedtls_ecdh_enable_restart() was previously called on - * that context. For function in the SSL module, restart is - * only enabled for specific sides and key exchanges - * (currently only for clients and ECDHE-ECDSA). - * - * \warning Using the PSA interruptible interfaces with keys in local - * storage and no accelerator driver will also call this - * function to set the values specified via those interfaces, - * overwriting values previously set. Care should be taken if - * mixing these two interfaces. - * - * \param max_ops Maximum number of basic operations done in a row. - * Default: 0 (unlimited). - * Lower (non-zero) values mean ECC functions will block for - * a lesser maximum amount of time. - * - * \note A "basic operation" is defined as a rough equivalent of a - * multiplication in GF(p) for the NIST P-256 curve. - * As an indication, with default settings, a scalar - * multiplication (full run of \c mbedtls_ecp_mul()) is: - * - about 3300 basic operations for P-256 - * - about 9400 basic operations for P-384 - * - * \note Very low values are not always respected: sometimes - * functions need to block for a minimum number of - * operations, and will do so even if max_ops is set to a - * lower value. That minimum depends on the curve size, and - * can be made lower by decreasing the value of - * \c MBEDTLS_ECP_WINDOW_SIZE. As an indication, here is the - * lowest effective value for various curves and values of - * that parameter (w for short): - * w=6 w=5 w=4 w=3 w=2 - * P-256 208 208 160 136 124 - * P-384 682 416 320 272 248 - * P-521 1364 832 640 544 496 - * - * \note This setting is currently ignored by Curve25519. - */ -void mbedtls_ecp_set_max_ops(unsigned max_ops); - -/** - * \brief Check if restart is enabled (max_ops != 0) - * - * \return \c 0 if \c max_ops == 0 (restart disabled) - * \return \c 1 otherwise (restart enabled) - */ -int mbedtls_ecp_restart_is_enabled(void); -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -/* - * Get the type of a curve - */ -mbedtls_ecp_curve_type mbedtls_ecp_get_type(const mbedtls_ecp_group *grp); - -/** - * \brief This function retrieves the information defined in - * mbedtls_ecp_curve_info() for all supported curves. - * - * \note This function returns information about all curves - * supported by the library. Some curves may not be - * supported for all algorithms. Call mbedtls_ecdh_can_do() - * or mbedtls_ecdsa_can_do() to check if a curve is - * supported for ECDH or ECDSA. - * - * \return A statically allocated array. The last entry is 0. - */ -const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list(void); - -/** - * \brief This function retrieves the list of internal group - * identifiers of all supported curves in the order of - * preference. - * - * \note This function returns information about all curves - * supported by the library. Some curves may not be - * supported for all algorithms. Call mbedtls_ecdh_can_do() - * or mbedtls_ecdsa_can_do() to check if a curve is - * supported for ECDH or ECDSA. - * - * \return A statically allocated array, - * terminated with MBEDTLS_ECP_DP_NONE. - */ -const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list(void); - -/** - * \brief This function retrieves curve information from an internal - * group identifier. - * - * \param grp_id An \c MBEDTLS_ECP_DP_XXX value. - * - * \return The associated curve information on success. - * \return NULL on failure. - */ -const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id(mbedtls_ecp_group_id grp_id); - -/** - * \brief This function retrieves curve information from a TLS - * NamedCurve value. - * - * \param tls_id An \c MBEDTLS_ECP_DP_XXX value. - * - * \return The associated curve information on success. - * \return NULL on failure. - */ -const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id(uint16_t tls_id); - -/** - * \brief This function retrieves curve information from a - * human-readable name. - * - * \param name The human-readable name. - * - * \return The associated curve information on success. - * \return NULL on failure. - */ -const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name(const char *name); - -/** - * \brief This function initializes a point as zero. - * - * \param pt The point to initialize. - */ -void mbedtls_ecp_point_init(mbedtls_ecp_point *pt); - -/** - * \brief This function initializes an ECP group context - * without loading any domain parameters. - * - * \note After this function is called, domain parameters - * for various ECP groups can be loaded through the - * mbedtls_ecp_group_load() or mbedtls_ecp_tls_read_group() - * functions. - */ -void mbedtls_ecp_group_init(mbedtls_ecp_group *grp); - -/** - * \brief This function initializes a key pair as an invalid one. - * - * \param key The key pair to initialize. - */ -void mbedtls_ecp_keypair_init(mbedtls_ecp_keypair *key); - -/** - * \brief This function frees the components of a point. - * - * \param pt The point to free. - */ -void mbedtls_ecp_point_free(mbedtls_ecp_point *pt); - -/** - * \brief This function frees the components of an ECP group. - * - * \param grp The group to free. This may be \c NULL, in which - * case this function returns immediately. If it is not - * \c NULL, it must point to an initialized ECP group. - */ -void mbedtls_ecp_group_free(mbedtls_ecp_group *grp); - -/** - * \brief This function frees the components of a key pair. - * - * \param key The key pair to free. This may be \c NULL, in which - * case this function returns immediately. If it is not - * \c NULL, it must point to an initialized ECP key pair. - */ -void mbedtls_ecp_keypair_free(mbedtls_ecp_keypair *key); - -#if defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Initialize a restart context. - * - * \param ctx The restart context to initialize. This must - * not be \c NULL. - */ -void mbedtls_ecp_restart_init(mbedtls_ecp_restart_ctx *ctx); - -/** - * \brief Free the components of a restart context. - * - * \param ctx The restart context to free. This may be \c NULL, in which - * case this function returns immediately. If it is not - * \c NULL, it must point to an initialized restart context. - */ -void mbedtls_ecp_restart_free(mbedtls_ecp_restart_ctx *ctx); -#endif /* MBEDTLS_ECP_RESTARTABLE */ - -/** - * \brief This function copies the contents of point \p Q into - * point \p P. - * - * \param P The destination point. This must be initialized. - * \param Q The source point. This must be initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return Another negative error code for other kinds of failure. - */ -int mbedtls_ecp_copy(mbedtls_ecp_point *P, const mbedtls_ecp_point *Q); - -/** - * \brief This function copies the contents of group \p src into - * group \p dst. - * - * \param dst The destination group. This must be initialized. - * \param src The source group. This must be initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_group_copy(mbedtls_ecp_group *dst, - const mbedtls_ecp_group *src); - -/** - * \brief This function sets a point to the point at infinity. - * - * \param pt The point to set. This must be initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_set_zero(mbedtls_ecp_point *pt); - -/** - * \brief This function checks if a point is the point at infinity. - * - * \param pt The point to test. This must be initialized. - * - * \return \c 1 if the point is zero. - * \return \c 0 if the point is non-zero. - * \return A negative error code on failure. - */ -int mbedtls_ecp_is_zero(mbedtls_ecp_point *pt); - -/** - * \brief This function compares two points. - * - * \note This assumes that the points are normalized. Otherwise, - * they may compare as "not equal" even if they are. - * - * \param P The first point to compare. This must be initialized. - * \param Q The second point to compare. This must be initialized. - * - * \return \c 0 if the points are equal. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the points are not equal. - */ -int mbedtls_ecp_point_cmp(const mbedtls_ecp_point *P, - const mbedtls_ecp_point *Q); - -/** - * \brief This function imports a non-zero point from two ASCII - * strings. - * - * \param P The destination point. This must be initialized. - * \param radix The numeric base of the input. - * \param x The first affine coordinate, as a null-terminated string. - * \param y The second affine coordinate, as a null-terminated string. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_MPI_XXX error code on failure. - */ -int mbedtls_ecp_point_read_string(mbedtls_ecp_point *P, int radix, - const char *x, const char *y); - -/** - * \brief This function exports a point into unsigned binary data. - * - * \param grp The group to which the point should belong. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param P The point to export. This must be initialized. - * \param format The point format. This must be either - * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. - * (For groups without these formats, this parameter is - * ignored. But it still has to be either of the above - * values.) - * \param olen The address at which to store the length of - * the output in Bytes. This must not be \c NULL. - * \param buf The output buffer. This must be a writable buffer - * of length \p buflen Bytes. - * \param buflen The length of the output buffer \p buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output buffer - * is too small to hold the point. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the point format - * or the export for the given group is not implemented. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_point_write_binary(const mbedtls_ecp_group *grp, - const mbedtls_ecp_point *P, - int format, size_t *olen, - unsigned char *buf, size_t buflen); - -/** - * \brief This function imports a point from unsigned binary data. - * - * \note This function does not check that the point actually - * belongs to the given group, see mbedtls_ecp_check_pubkey() - * for that. - * - * \note For compressed points, see #MBEDTLS_ECP_PF_COMPRESSED for - * limitations. - * - * \param grp The group to which the point should belong. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param P The destination context to import the point to. - * This must be initialized. - * \param buf The input buffer. This must be a readable buffer - * of length \p ilen Bytes. - * \param ilen The length of the input buffer \p buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the import for the - * given group is not implemented. - */ -int mbedtls_ecp_point_read_binary(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *P, - const unsigned char *buf, size_t ilen); - -/** - * \brief This function imports a point from a TLS ECPoint record. - * - * \note On function return, \p *buf is updated to point immediately - * after the ECPoint record. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param pt The destination point. - * \param buf The address of the pointer to the start of the input buffer. - * \param len The length of the buffer. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_MPI_XXX error code on initialization - * failure. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. - */ -int mbedtls_ecp_tls_read_point(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *pt, - const unsigned char **buf, size_t len); - -/** - * \brief This function exports a point as a TLS ECPoint record - * defined in RFC 4492, Section 5.4. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param pt The point to be exported. This must be initialized. - * \param format The point format to use. This must be either - * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. - * \param olen The address at which to store the length in Bytes - * of the data written. - * \param buf The target buffer. This must be a writable buffer of - * length \p blen Bytes. - * \param blen The length of the target buffer \p buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. - * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the target buffer - * is too small to hold the exported point. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_tls_write_point(const mbedtls_ecp_group *grp, - const mbedtls_ecp_point *pt, - int format, size_t *olen, - unsigned char *buf, size_t blen); - -/** - * \brief This function sets up an ECP group context - * from a standardized set of domain parameters. - * - * \note The index should be a value of the NamedCurve enum, - * as defined in RFC-4492: Elliptic Curve Cryptography - * (ECC) Cipher Suites for Transport Layer Security (TLS), - * usually in the form of an \c MBEDTLS_ECP_DP_XXX macro. - * - * \param grp The group context to setup. This must be initialized. - * \param id The identifier of the domain parameter set to load. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p id doesn't - * correspond to a known group. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_group_load(mbedtls_ecp_group *grp, mbedtls_ecp_group_id id); - -/** - * \brief This function sets up an ECP group context from a TLS - * ECParameters record as defined in RFC 4492, Section 5.4. - * - * \note The read pointer \p buf is updated to point right after - * the ECParameters record on exit. - * - * \param grp The group context to setup. This must be initialized. - * \param buf The address of the pointer to the start of the input buffer. - * \param len The length of the input buffer \c *buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not - * recognized. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_tls_read_group(mbedtls_ecp_group *grp, - const unsigned char **buf, size_t len); - -/** - * \brief This function extracts an elliptic curve group ID from a - * TLS ECParameters record as defined in RFC 4492, Section 5.4. - * - * \note The read pointer \p buf is updated to point right after - * the ECParameters record on exit. - * - * \param grp The address at which to store the group id. - * This must not be \c NULL. - * \param buf The address of the pointer to the start of the input buffer. - * \param len The length of the input buffer \c *buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not - * recognized. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_tls_read_group_id(mbedtls_ecp_group_id *grp, - const unsigned char **buf, - size_t len); -/** - * \brief This function exports an elliptic curve as a TLS - * ECParameters record as defined in RFC 4492, Section 5.4. - * - * \param grp The ECP group to be exported. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param olen The address at which to store the number of Bytes written. - * This must not be \c NULL. - * \param buf The buffer to write to. This must be a writable buffer - * of length \p blen Bytes. - * \param blen The length of the output buffer \p buf in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output - * buffer is too small to hold the exported group. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_tls_write_group(const mbedtls_ecp_group *grp, - size_t *olen, - unsigned char *buf, size_t blen); - -/** - * \brief This function performs a scalar multiplication of a point - * by an integer: \p R = \p m * \p P. - * - * It is not thread-safe to use same group in multiple threads. - * - * \note To prevent timing attacks, this function - * executes the exact same sequence of base-field - * operations for any valid \p m. It avoids any if-branch or - * array index depending on the value of \p m. It also uses - * \p f_rng to randomize some intermediate results. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param R The point in which to store the result of the calculation. - * This must be initialized. - * \param m The integer by which to multiply. This must be initialized. - * \param P The point to multiply. This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c - * NULL if \p f_rng doesn't need a context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private - * key, or \p P is not a valid public key. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_mul(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, - const mbedtls_mpi *m, const mbedtls_ecp_point *P, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** - * \brief This function performs multiplication of a point by - * an integer: \p R = \p m * \p P in a restartable way. - * - * \see mbedtls_ecp_mul() - * - * \note This function does the same as \c mbedtls_ecp_mul(), but - * it can return early and restart according to the limit set - * with \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param R The point in which to store the result of the calculation. - * This must be initialized. - * \param m The integer by which to multiply. This must be initialized. - * \param P The point to multiply. This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c - * NULL if \p f_rng doesn't need a context. - * \param rs_ctx The restart context (NULL disables restart). - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private - * key, or \p P is not a valid public key. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_mul_restartable(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, - const mbedtls_mpi *m, const mbedtls_ecp_point *P, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, - mbedtls_ecp_restart_ctx *rs_ctx); - -#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) -/** - * \brief This function checks if domain parameter A of the curve is - * \c -3. - * - * \note This function is only defined for short Weierstrass curves. - * It may not be included in builds without any short - * Weierstrass curve. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * - * \return \c 1 if A = -3. - * \return \c 0 Otherwise. - */ -static inline int mbedtls_ecp_group_a_is_minus_3(const mbedtls_ecp_group *grp) -{ - return grp->A.MBEDTLS_PRIVATE(p) == NULL; -} - -/** - * \brief This function performs multiplication and addition of two - * points by integers: \p R = \p m * \p P + \p n * \p Q - * - * It is not thread-safe to use same group in multiple threads. - * - * \note In contrast to mbedtls_ecp_mul(), this function does not - * guarantee a constant execution flow and timing. - * - * \note This function is only defined for short Weierstrass curves. - * It may not be included in builds without any short - * Weierstrass curve. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param R The point in which to store the result of the calculation. - * This must be initialized. - * \param m The integer by which to multiply \p P. - * This must be initialized. - * \param P The point to multiply by \p m. This must be initialized. - * \param n The integer by which to multiply \p Q. - * This must be initialized. - * \param Q The point to be multiplied by \p n. - * This must be initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not - * valid private keys, or \p P or \p Q are not valid public - * keys. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p grp does not - * designate a short Weierstrass curve. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_muladd(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, - const mbedtls_mpi *m, const mbedtls_ecp_point *P, - const mbedtls_mpi *n, const mbedtls_ecp_point *Q); - -/** - * \brief This function performs multiplication and addition of two - * points by integers: \p R = \p m * \p P + \p n * \p Q in a - * restartable way. - * - * \see \c mbedtls_ecp_muladd() - * - * \note This function works the same as \c mbedtls_ecp_muladd(), - * but it can return early and restart according to the limit - * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \note This function is only defined for short Weierstrass curves. - * It may not be included in builds without any short - * Weierstrass curve. - * - * \param grp The ECP group to use. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param R The point in which to store the result of the calculation. - * This must be initialized. - * \param m The integer by which to multiply \p P. - * This must be initialized. - * \param P The point to multiply by \p m. This must be initialized. - * \param n The integer by which to multiply \p Q. - * This must be initialized. - * \param Q The point to be multiplied by \p n. - * This must be initialized. - * \param rs_ctx The restart context (NULL disables restart). - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not - * valid private keys, or \p P or \p Q are not valid public - * keys. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p grp does not - * designate a short Weierstrass curve. - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_muladd_restartable( - mbedtls_ecp_group *grp, mbedtls_ecp_point *R, - const mbedtls_mpi *m, const mbedtls_ecp_point *P, - const mbedtls_mpi *n, const mbedtls_ecp_point *Q, - mbedtls_ecp_restart_ctx *rs_ctx); -#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ - -/** - * \brief This function checks that a point is a valid public key - * on this curve. - * - * It only checks that the point is non-zero, has - * valid coordinates and lies on the curve. It does not verify - * that it is indeed a multiple of \c G. This additional - * check is computationally more expensive, is not required - * by standards, and should not be necessary if the group - * used has a small cofactor. In particular, it is useless for - * the NIST groups which all have a cofactor of 1. - * - * \note This function uses bare components rather than an - * ::mbedtls_ecp_keypair structure, to ease use with other - * structures, such as ::mbedtls_ecdh_context or - * ::mbedtls_ecdsa_context. - * - * \param grp The ECP group the point should belong to. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param pt The point to check. This must be initialized. - * - * \return \c 0 if the point is a valid public key. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not - * a valid public key for the given curve. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_check_pubkey(const mbedtls_ecp_group *grp, - const mbedtls_ecp_point *pt); - -/** - * \brief This function checks that an \c mbedtls_mpi is a - * valid private key for this curve. - * - * \note This function uses bare components rather than an - * ::mbedtls_ecp_keypair structure to ease use with other - * structures, such as ::mbedtls_ecdh_context or - * ::mbedtls_ecdsa_context. - * - * \param grp The ECP group the private key should belong to. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param d The integer to check. This must be initialized. - * - * \return \c 0 if the point is a valid private key. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not a valid - * private key for the given curve. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_check_privkey(const mbedtls_ecp_group *grp, - const mbedtls_mpi *d); - -/** - * \brief This function generates a private key. - * - * \param grp The ECP group to generate a private key for. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param d The destination MPI (secret part). This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code - * on failure. - */ -int mbedtls_ecp_gen_privkey(const mbedtls_ecp_group *grp, - mbedtls_mpi *d, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function generates a keypair with a configurable base - * point. - * - * \note This function uses bare components rather than an - * ::mbedtls_ecp_keypair structure to ease use with other - * structures, such as ::mbedtls_ecdh_context or - * ::mbedtls_ecdsa_context. - * - * \param grp The ECP group to generate a key pair for. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param G The base point to use. This must be initialized - * and belong to \p grp. It replaces the default base - * point \c grp->G used by mbedtls_ecp_gen_keypair(). - * \param d The destination MPI (secret part). - * This must be initialized. - * \param Q The destination point (public part). - * This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may - * be \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code - * on failure. - */ -int mbedtls_ecp_gen_keypair_base(mbedtls_ecp_group *grp, - const mbedtls_ecp_point *G, - mbedtls_mpi *d, mbedtls_ecp_point *Q, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function generates an ECP keypair. - * - * \note This function uses bare components rather than an - * ::mbedtls_ecp_keypair structure to ease use with other - * structures, such as ::mbedtls_ecdh_context or - * ::mbedtls_ecdsa_context. - * - * \param grp The ECP group to generate a key pair for. - * This must be initialized and have group parameters - * set, for example through mbedtls_ecp_group_load(). - * \param d The destination MPI (secret part). - * This must be initialized. - * \param Q The destination point (public part). - * This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may - * be \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code - * on failure. - */ -int mbedtls_ecp_gen_keypair(mbedtls_ecp_group *grp, mbedtls_mpi *d, - mbedtls_ecp_point *Q, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function generates an ECP key. - * - * \param grp_id The ECP group identifier. - * \param key The destination key. This must be initialized. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may - * be \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code - * on failure. - */ -int mbedtls_ecp_gen_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief This function reads an elliptic curve private key. - * - * \param grp_id The ECP group identifier. - * \param key The destination key. - * \param buf The buffer containing the binary representation of the - * key. (Big endian integer for Weierstrass curves, byte - * string for Montgomery curves.) - * \param buflen The length of the buffer in bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_INVALID_KEY error if the key is - * invalid. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the operation for - * the group is not implemented. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_ecp_read_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, - const unsigned char *buf, size_t buflen); - -/** - * \brief This function exports an elliptic curve private key. - * - * \param key The private key. - * \param buf The output buffer for containing the binary representation - * of the key. (Big endian integer for Weierstrass curves, byte - * string for Montgomery curves.) - * \param buflen The total length of the buffer in bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the \p key - representation is larger than the available space in \p buf. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the operation for - * the group is not implemented. - * \return Another negative error code on different kinds of failure. - */ -int mbedtls_ecp_write_key(mbedtls_ecp_keypair *key, - unsigned char *buf, size_t buflen); - -/** - * \brief This function checks that the keypair objects - * \p pub and \p prv have the same group and the - * same public point, and that the private key in - * \p prv is consistent with the public key. - * - * \param pub The keypair structure holding the public key. This - * must be initialized. If it contains a private key, that - * part is ignored. - * \param prv The keypair structure holding the full keypair. - * This must be initialized. - * \param f_rng The RNG function. This must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c - * NULL if \p f_rng doesn't need a context. - * - * \return \c 0 on success, meaning that the keys are valid and match. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the keys are invalid or do not match. - * \return An \c MBEDTLS_ERR_ECP_XXX or an \c MBEDTLS_ERR_MPI_XXX - * error code on calculation failure. - */ -int mbedtls_ecp_check_pub_priv( - const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** - * \brief This function exports generic key-pair parameters. - * - * \param key The key pair to export from. - * \param grp Slot for exported ECP group. - * It must point to an initialized ECP group. - * \param d Slot for the exported secret value. - * It must point to an initialized mpi. - * \param Q Slot for the exported public value. - * It must point to an initialized ECP point. - * - * \return \c 0 on success, - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if key id doesn't - * correspond to a known group. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ecp_export(const mbedtls_ecp_keypair *key, mbedtls_ecp_group *grp, - mbedtls_mpi *d, mbedtls_ecp_point *Q); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The ECP checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_ecp_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* ecp.h */ +/** + * \file ecp.h + * + * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). + * + * The use of ECP in cryptography and TLS is defined in + * Standards for Efficient Cryptography Group (SECG): SEC1 + * Elliptic Curve Cryptography and + * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites + * for Transport Layer Security (TLS). + * + * RFC-2409: The Internet Key Exchange (IKE) defines ECP + * group types. + * + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_ECP_H +#define MBEDTLS_ECP_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/bignum.h" + +/* + * ECP error codes + */ +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_ECP_BAD_INPUT_DATA -0x4F80 +/** The buffer is too small to write to. */ +#define MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL -0x4F00 +/** The requested feature is not available, for example, the requested curve is not supported. */ +#define MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE -0x4E80 +/** The signature is not valid. */ +#define MBEDTLS_ERR_ECP_VERIFY_FAILED -0x4E00 +/** Memory allocation failed. */ +#define MBEDTLS_ERR_ECP_ALLOC_FAILED -0x4D80 +/** Generation of random value, such as ephemeral key, failed. */ +#define MBEDTLS_ERR_ECP_RANDOM_FAILED -0x4D00 +/** Invalid private or public key. */ +#define MBEDTLS_ERR_ECP_INVALID_KEY -0x4C80 +/** The buffer contains a valid signature followed by more data. */ +#define MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH -0x4C00 +/** Operation in progress, call again with the same parameters to continue. */ +#define MBEDTLS_ERR_ECP_IN_PROGRESS -0x4B00 + +/* Flags indicating whether to include code that is specific to certain + * types of curves. These flags are for internal library use only. */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED +#endif +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || \ + defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define MBEDTLS_ECP_MONTGOMERY_ENABLED +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Domain-parameter identifiers: curve, subgroup, and generator. + * + * \note Only curves over prime fields are supported. + * + * \warning This library does not support validation of arbitrary domain + * parameters. Therefore, only standardized domain parameters from trusted + * sources should be used. See mbedtls_ecp_group_load(). + */ +/* Note: when adding a new curve: + * - Add it at the end of this enum, otherwise you'll break the ABI by + * changing the numerical value for existing curves. + * - Increment MBEDTLS_ECP_DP_MAX below if needed. + * - Update the calculation of MBEDTLS_ECP_MAX_BITS below. + * - Add the corresponding MBEDTLS_ECP_DP_xxx_ENABLED macro definition to + * mbedtls_config.h. + * - List the curve as a dependency of MBEDTLS_ECP_C and + * MBEDTLS_ECDSA_C if supported in check_config.h. + * - Add the curve to the appropriate curve type macro + * MBEDTLS_ECP_yyy_ENABLED above. + * - Add the necessary definitions to ecp_curves.c. + * - Add the curve to the ecp_supported_curves array in ecp.c. + * - Add the curve to applicable profiles in x509_crt.c. + * - Add the curve to applicable presets in ssl_tls.c. + */ +typedef enum { + MBEDTLS_ECP_DP_NONE = 0, /*!< Curve not defined. */ + MBEDTLS_ECP_DP_SECP192R1, /*!< Domain parameters for the 192-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP224R1, /*!< Domain parameters for the 224-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP256R1, /*!< Domain parameters for the 256-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP384R1, /*!< Domain parameters for the 384-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_SECP521R1, /*!< Domain parameters for the 521-bit curve defined by FIPS 186-4 and SEC1. */ + MBEDTLS_ECP_DP_BP256R1, /*!< Domain parameters for 256-bit Brainpool curve. */ + MBEDTLS_ECP_DP_BP384R1, /*!< Domain parameters for 384-bit Brainpool curve. */ + MBEDTLS_ECP_DP_BP512R1, /*!< Domain parameters for 512-bit Brainpool curve. */ + MBEDTLS_ECP_DP_CURVE25519, /*!< Domain parameters for Curve25519. */ + MBEDTLS_ECP_DP_SECP192K1, /*!< Domain parameters for 192-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_SECP224K1, /*!< Domain parameters for 224-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_SECP256K1, /*!< Domain parameters for 256-bit "Koblitz" curve. */ + MBEDTLS_ECP_DP_CURVE448, /*!< Domain parameters for Curve448. */ +} mbedtls_ecp_group_id; + +/** + * The number of supported curves, plus one for #MBEDTLS_ECP_DP_NONE. + */ +#define MBEDTLS_ECP_DP_MAX 14 + +/* + * Curve types + */ +typedef enum { + MBEDTLS_ECP_TYPE_NONE = 0, + MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS, /* y^2 = x^3 + a x + b */ + MBEDTLS_ECP_TYPE_MONTGOMERY, /* y^2 = x^3 + a x^2 + x */ +} mbedtls_ecp_curve_type; + +/** + * Curve information, for use by other modules. + * + * The fields of this structure are part of the public API and can be + * accessed directly by applications. Future versions of the library may + * add extra fields or reorder existing fields. + */ +typedef struct mbedtls_ecp_curve_info { + mbedtls_ecp_group_id grp_id; /*!< An internal identifier. */ + uint16_t tls_id; /*!< The TLS NamedCurve identifier. */ + uint16_t bit_size; /*!< The curve size in bits. */ + const char *name; /*!< A human-friendly name. */ +} mbedtls_ecp_curve_info; + +/** + * \brief The ECP point structure, in Jacobian coordinates. + * + * \note All functions expect and return points satisfying + * the following condition: Z == 0 or + * Z == 1. Other values of \p Z are + * used only by internal functions. + * The point is zero, or "at infinity", if Z == 0. + * Otherwise, \p X and \p Y are its standard (affine) + * coordinates. + */ +typedef struct mbedtls_ecp_point { + mbedtls_mpi MBEDTLS_PRIVATE(X); /*!< The X coordinate of the ECP point. */ + mbedtls_mpi MBEDTLS_PRIVATE(Y); /*!< The Y coordinate of the ECP point. */ + mbedtls_mpi MBEDTLS_PRIVATE(Z); /*!< The Z coordinate of the ECP point. */ +} +mbedtls_ecp_point; + +#if !defined(MBEDTLS_ECP_ALT) +/* + * default Mbed TLS elliptic curve arithmetic implementation + * + * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an + * alternative implementation for the whole module and it will replace this + * one.) + */ + +/** + * \brief The ECP group structure. + * + * We consider two types of curve equations: + *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P + * (SEC1 + RFC-4492)
    • + *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, + * Curve448)
+ * In both cases, the generator (\p G) for a prime-order subgroup is fixed. + * + * For Short Weierstrass, this subgroup is the whole curve, and its + * cardinality is denoted by \p N. Our code requires that \p N is an + * odd prime as mbedtls_ecp_mul() requires an odd number, and + * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. + * + * The default implementation only initializes \p A without setting it to the + * authentic value for curves with A = -3(SECP256R1, etc), in which + * case you need to load \p A by yourself when using domain parameters directly, + * for example: + * \code + * mbedtls_mpi_init(&A); + * mbedtls_ecp_group_init(&grp); + * CHECK_RETURN(mbedtls_ecp_group_load(&grp, grp_id)); + * if (mbedtls_ecp_group_a_is_minus_3(&grp)) { + * CHECK_RETURN(mbedtls_mpi_sub_int(&A, &grp.P, 3)); + * } else { + * CHECK_RETURN(mbedtls_mpi_copy(&A, &grp.A)); + * } + * + * do_something_with_a(&A); + * + * cleanup: + * mbedtls_mpi_free(&A); + * mbedtls_ecp_group_free(&grp); + * \endcode + * + * For Montgomery curves, we do not store \p A, but (A + 2) / 4, + * which is the quantity used in the formulas. Additionally, \p nbits is + * not the size of \p N but the required size for private keys. + * + * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. + * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the + * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer + * which is congruent mod \p P to the given MPI, and is close enough to \p pbits + * in size, so that it may be efficiently brought in the 0..P-1 range by a few + * additions or subtractions. Therefore, it is only an approximative modular + * reduction. It must return 0 on success and non-zero on failure. + * + * \note Alternative implementations of the ECP module must obey the + * following constraints. + * * Group IDs must be distinct: if two group structures have + * the same ID, then they must be identical. + * * The fields \c id, \c P, \c A, \c B, \c G, \c N, + * \c pbits and \c nbits must have the same type and semantics + * as in the built-in implementation. + * They must be available for reading, but direct modification + * of these fields does not need to be supported. + * They do not need to be at the same offset in the structure. + */ +typedef struct mbedtls_ecp_group { + mbedtls_ecp_group_id id; /*!< An internal group identifier. */ + mbedtls_mpi P; /*!< The prime modulus of the base field. */ + mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. Note that + \p A is not set to the authentic value in some cases. + Refer to detailed description of ::mbedtls_ecp_group if + using domain parameters in the structure. + For Montgomery curves: (A + 2) / 4. */ + mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. + For Montgomery curves: unused. */ + mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ + mbedtls_mpi N; /*!< The order of \p G. */ + size_t pbits; /*!< The number of bits in \p P.*/ + size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. + For Montgomery curves: the number of bits in the + private keys. */ + /* End of public fields */ + + unsigned int MBEDTLS_PRIVATE(h); /*!< \internal 1 if the constants are static. */ + int(*MBEDTLS_PRIVATE(modp))(mbedtls_mpi *); /*!< The function for fast pseudo-reduction + mod \p P (see above).*/ + int(*MBEDTLS_PRIVATE(t_pre))(mbedtls_ecp_point *, void *); /*!< Unused. */ + int(*MBEDTLS_PRIVATE(t_post))(mbedtls_ecp_point *, void *); /*!< Unused. */ + void *MBEDTLS_PRIVATE(t_data); /*!< Unused. */ + mbedtls_ecp_point *MBEDTLS_PRIVATE(T); /*!< Pre-computed points for ecp_mul_comb(). */ + size_t MBEDTLS_PRIVATE(T_size); /*!< The number of dynamic allocated pre-computed points. */ +} +mbedtls_ecp_group; + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h, or define them using the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ECP_WINDOW_SIZE) +/* + * Maximum "window" size used for point multiplication. + * Default: a point where higher memory usage yields diminishing performance + * returns. + * Minimum value: 2. Maximum value: 7. + * + * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + * points used for point multiplication. This value is directly tied to EC + * peak memory usage, so decreasing it by one should roughly cut memory usage + * by two (if large curves are in use). + * + * Reduction in size may reduce speed, but larger curves are impacted first. + * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): + * w-size: 6 5 4 3 2 + * 521 145 141 135 120 97 + * 384 214 209 198 177 146 + * 256 320 320 303 262 226 + * 224 475 475 453 398 342 + * 192 640 640 633 587 476 + */ +#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< The maximum window size used. */ +#endif /* MBEDTLS_ECP_WINDOW_SIZE */ + +#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) +/* + * Trade code size for speed on fixed-point multiplication. + * + * This speeds up repeated multiplication of the generator (that is, the + * multiplication in ECDSA signatures, and half of the multiplications in + * ECDSA verification and ECDHE) by a factor roughly 3 to 4. + * + * For each n-bit Short Weierstrass curve that is enabled, this adds 4n bytes + * of code size if n < 384 and 8n otherwise. + * + * Change this value to 0 to reduce code size. + */ +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ +#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ + +/** \} name SECTION: Module settings */ + +#else /* MBEDTLS_ECP_ALT */ +#include "ecp_alt.h" +#endif /* MBEDTLS_ECP_ALT */ + +/** + * The maximum size of the groups, that is, of \c N and \c P. + */ +#if !defined(MBEDTLS_ECP_LIGHT) +/* Dummy definition to help code that has optional ECP support and + * defines an MBEDTLS_ECP_MAX_BYTES-sized array unconditionally. */ +#define MBEDTLS_ECP_MAX_BITS 1 +/* Note: the curves must be listed in DECREASING size! */ +#elif defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 521 +#elif defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 512 +#elif defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 448 +#elif defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 384 +#elif defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 384 +#elif defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 256 +#elif defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 256 +#elif defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 256 +#elif defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 255 +#elif defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 225 // n is slightly above 2^224 +#elif defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 224 +#elif defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 192 +#elif defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +#define MBEDTLS_ECP_MAX_BITS 192 +#else /* !MBEDTLS_ECP_LIGHT */ +#error "Missing definition of MBEDTLS_ECP_MAX_BITS" +#endif /* !MBEDTLS_ECP_LIGHT */ + +#define MBEDTLS_ECP_MAX_BYTES ((MBEDTLS_ECP_MAX_BITS + 7) / 8) +#define MBEDTLS_ECP_MAX_PT_LEN (2 * MBEDTLS_ECP_MAX_BYTES + 1) + +#if defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Internal restart context for multiplication + * + * \note Opaque struct + */ +typedef struct mbedtls_ecp_restart_mul mbedtls_ecp_restart_mul_ctx; + +/** + * \brief Internal restart context for ecp_muladd() + * + * \note Opaque struct + */ +typedef struct mbedtls_ecp_restart_muladd mbedtls_ecp_restart_muladd_ctx; + +/** + * \brief General context for resuming ECC operations + */ +typedef struct { + unsigned MBEDTLS_PRIVATE(ops_done); /*!< current ops count */ + unsigned MBEDTLS_PRIVATE(depth); /*!< call depth (0 = top-level) */ + mbedtls_ecp_restart_mul_ctx *MBEDTLS_PRIVATE(rsm); /*!< ecp_mul_comb() sub-context */ + mbedtls_ecp_restart_muladd_ctx *MBEDTLS_PRIVATE(ma); /*!< ecp_muladd() sub-context */ +} mbedtls_ecp_restart_ctx; + +/* + * Operation counts for restartable functions + */ +#define MBEDTLS_ECP_OPS_CHK 3 /*!< basic ops count for ecp_check_pubkey() */ +#define MBEDTLS_ECP_OPS_DBL 8 /*!< basic ops count for ecp_double_jac() */ +#define MBEDTLS_ECP_OPS_ADD 11 /*!< basic ops count for see ecp_add_mixed() */ +#define MBEDTLS_ECP_OPS_INV 120 /*!< empirical equivalent for mpi_mod_inv() */ + +/** + * \brief Internal; for restartable functions in other modules. + * Check and update basic ops budget. + * + * \param grp Group structure + * \param rs_ctx Restart context + * \param ops Number of basic ops to do + * + * \return \c 0 if doing \p ops basic ops is still allowed, + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS otherwise. + */ +int mbedtls_ecp_check_budget(const mbedtls_ecp_group *grp, + mbedtls_ecp_restart_ctx *rs_ctx, + unsigned ops); + +/* Utility macro for checking and updating ops budget */ +#define MBEDTLS_ECP_BUDGET(ops) \ + MBEDTLS_MPI_CHK(mbedtls_ecp_check_budget(grp, rs_ctx, \ + (unsigned) (ops))); + +#else /* MBEDTLS_ECP_RESTARTABLE */ + +#define MBEDTLS_ECP_BUDGET(ops) /* no-op; for compatibility */ + +/* We want to declare restartable versions of existing functions anyway */ +typedef void mbedtls_ecp_restart_ctx; + +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief The ECP key-pair structure. + * + * A generic key-pair that may be used for ECDSA and fixed ECDH, for example. + * + * \note Members are deliberately in the same order as in the + * ::mbedtls_ecdsa_context structure. + */ +typedef struct mbedtls_ecp_keypair { + mbedtls_ecp_group MBEDTLS_PRIVATE(grp); /*!< Elliptic curve and base point */ + mbedtls_mpi MBEDTLS_PRIVATE(d); /*!< our secret value */ + mbedtls_ecp_point MBEDTLS_PRIVATE(Q); /*!< our public value */ +} +mbedtls_ecp_keypair; + +/** + * The uncompressed point format for Short Weierstrass curves + * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX). + */ +#define MBEDTLS_ECP_PF_UNCOMPRESSED 0 +/** + * The compressed point format for Short Weierstrass curves + * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX). + * + * \warning While this format is supported for all concerned curves for + * writing, when it comes to parsing, it is not supported for all + * curves. Specifically, parsing compressed points on + * MBEDTLS_ECP_DP_SECP224R1 and MBEDTLS_ECP_DP_SECP224K1 is not + * supported. + */ +#define MBEDTLS_ECP_PF_COMPRESSED 1 + +/* + * Some other constants from RFC 4492 + */ +#define MBEDTLS_ECP_TLS_NAMED_CURVE 3 /**< The named_curve of ECCurveType. */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Set the maximum number of basic operations done in a row. + * + * If more operations are needed to complete a computation, + * #MBEDTLS_ERR_ECP_IN_PROGRESS will be returned by the + * function performing the computation. It is then the + * caller's responsibility to either call again with the same + * parameters until it returns 0 or an error code; or to free + * the restart context if the operation is to be aborted. + * + * It is strictly required that all input parameters and the + * restart context be the same on successive calls for the + * same operation, but output parameters need not be the + * same; they must not be used until the function finally + * returns 0. + * + * This only applies to functions whose documentation + * mentions they may return #MBEDTLS_ERR_ECP_IN_PROGRESS (or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS for functions in the + * SSL module). For functions that accept a "restart context" + * argument, passing NULL disables restart and makes the + * function equivalent to the function with the same name + * with \c _restartable removed. For functions in the ECDH + * module, restart is disabled unless the function accepts + * an "ECDH context" argument and + * mbedtls_ecdh_enable_restart() was previously called on + * that context. For function in the SSL module, restart is + * only enabled for specific sides and key exchanges + * (currently only for clients and ECDHE-ECDSA). + * + * \warning Using the PSA interruptible interfaces with keys in local + * storage and no accelerator driver will also call this + * function to set the values specified via those interfaces, + * overwriting values previously set. Care should be taken if + * mixing these two interfaces. + * + * \param max_ops Maximum number of basic operations done in a row. + * Default: 0 (unlimited). + * Lower (non-zero) values mean ECC functions will block for + * a lesser maximum amount of time. + * + * \note A "basic operation" is defined as a rough equivalent of a + * multiplication in GF(p) for the NIST P-256 curve. + * As an indication, with default settings, a scalar + * multiplication (full run of \c mbedtls_ecp_mul()) is: + * - about 3300 basic operations for P-256 + * - about 9400 basic operations for P-384 + * + * \note Very low values are not always respected: sometimes + * functions need to block for a minimum number of + * operations, and will do so even if max_ops is set to a + * lower value. That minimum depends on the curve size, and + * can be made lower by decreasing the value of + * \c MBEDTLS_ECP_WINDOW_SIZE. As an indication, here is the + * lowest effective value for various curves and values of + * that parameter (w for short): + * w=6 w=5 w=4 w=3 w=2 + * P-256 208 208 160 136 124 + * P-384 682 416 320 272 248 + * P-521 1364 832 640 544 496 + * + * \note This setting is currently ignored by Curve25519. + */ +void mbedtls_ecp_set_max_ops(unsigned max_ops); + +/** + * \brief Check if restart is enabled (max_ops != 0) + * + * \return \c 0 if \c max_ops == 0 (restart disabled) + * \return \c 1 otherwise (restart enabled) + */ +int mbedtls_ecp_restart_is_enabled(void); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/* + * Get the type of a curve + */ +mbedtls_ecp_curve_type mbedtls_ecp_get_type(const mbedtls_ecp_group *grp); + +/** + * \brief This function retrieves the information defined in + * mbedtls_ecp_curve_info() for all supported curves. + * + * \note This function returns information about all curves + * supported by the library. Some curves may not be + * supported for all algorithms. Call mbedtls_ecdh_can_do() + * or mbedtls_ecdsa_can_do() to check if a curve is + * supported for ECDH or ECDSA. + * + * \return A statically allocated array. The last entry is 0. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list(void); + +/** + * \brief This function retrieves the list of internal group + * identifiers of all supported curves in the order of + * preference. + * + * \note This function returns information about all curves + * supported by the library. Some curves may not be + * supported for all algorithms. Call mbedtls_ecdh_can_do() + * or mbedtls_ecdsa_can_do() to check if a curve is + * supported for ECDH or ECDSA. + * + * \return A statically allocated array, + * terminated with MBEDTLS_ECP_DP_NONE. + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list(void); + +/** + * \brief This function retrieves curve information from an internal + * group identifier. + * + * \param grp_id An \c MBEDTLS_ECP_DP_XXX value. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id(mbedtls_ecp_group_id grp_id); + +/** + * \brief This function retrieves curve information from a TLS + * NamedCurve value. + * + * \param tls_id An \c MBEDTLS_ECP_DP_XXX value. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id(uint16_t tls_id); + +/** + * \brief This function retrieves curve information from a + * human-readable name. + * + * \param name The human-readable name. + * + * \return The associated curve information on success. + * \return NULL on failure. + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name(const char *name); + +/** + * \brief This function initializes a point as zero. + * + * \param pt The point to initialize. + */ +void mbedtls_ecp_point_init(mbedtls_ecp_point *pt); + +/** + * \brief This function initializes an ECP group context + * without loading any domain parameters. + * + * \note After this function is called, domain parameters + * for various ECP groups can be loaded through the + * mbedtls_ecp_group_load() or mbedtls_ecp_tls_read_group() + * functions. + */ +void mbedtls_ecp_group_init(mbedtls_ecp_group *grp); + +/** + * \brief This function initializes a key pair as an invalid one. + * + * \param key The key pair to initialize. + */ +void mbedtls_ecp_keypair_init(mbedtls_ecp_keypair *key); + +/** + * \brief This function frees the components of a point. + * + * \param pt The point to free. + */ +void mbedtls_ecp_point_free(mbedtls_ecp_point *pt); + +/** + * \brief This function frees the components of an ECP group. + * + * \param grp The group to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized ECP group. + */ +void mbedtls_ecp_group_free(mbedtls_ecp_group *grp); + +/** + * \brief This function frees the components of a key pair. + * + * \param key The key pair to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized ECP key pair. + */ +void mbedtls_ecp_keypair_free(mbedtls_ecp_keypair *key); + +#if defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context. + * + * \param ctx The restart context to initialize. This must + * not be \c NULL. + */ +void mbedtls_ecp_restart_init(mbedtls_ecp_restart_ctx *ctx); + +/** + * \brief Free the components of a restart context. + * + * \param ctx The restart context to free. This may be \c NULL, in which + * case this function returns immediately. If it is not + * \c NULL, it must point to an initialized restart context. + */ +void mbedtls_ecp_restart_free(mbedtls_ecp_restart_ctx *ctx); +#endif /* MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief This function copies the contents of point \p Q into + * point \p P. + * + * \param P The destination point. This must be initialized. + * \param Q The source point. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code for other kinds of failure. + */ +int mbedtls_ecp_copy(mbedtls_ecp_point *P, const mbedtls_ecp_point *Q); + +/** + * \brief This function copies the contents of group \p src into + * group \p dst. + * + * \param dst The destination group. This must be initialized. + * \param src The source group. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_group_copy(mbedtls_ecp_group *dst, + const mbedtls_ecp_group *src); + +/** + * \brief This function sets a point to the point at infinity. + * + * \param pt The point to set. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_set_zero(mbedtls_ecp_point *pt); + +/** + * \brief This function checks if a point is the point at infinity. + * + * \param pt The point to test. This must be initialized. + * + * \return \c 1 if the point is zero. + * \return \c 0 if the point is non-zero. + * \return A negative error code on failure. + */ +int mbedtls_ecp_is_zero(mbedtls_ecp_point *pt); + +/** + * \brief This function compares two points. + * + * \note This assumes that the points are normalized. Otherwise, + * they may compare as "not equal" even if they are. + * + * \param P The first point to compare. This must be initialized. + * \param Q The second point to compare. This must be initialized. + * + * \return \c 0 if the points are equal. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the points are not equal. + */ +int mbedtls_ecp_point_cmp(const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q); + +/** + * \brief This function imports a non-zero point from two ASCII + * strings. + * + * \param P The destination point. This must be initialized. + * \param radix The numeric base of the input. + * \param x The first affine coordinate, as a null-terminated string. + * \param y The second affine coordinate, as a null-terminated string. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_MPI_XXX error code on failure. + */ +int mbedtls_ecp_point_read_string(mbedtls_ecp_point *P, int radix, + const char *x, const char *y); + +/** + * \brief This function exports a point into unsigned binary data. + * + * \param grp The group to which the point should belong. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param P The point to export. This must be initialized. + * \param format The point format. This must be either + * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. + * (For groups without these formats, this parameter is + * ignored. But it still has to be either of the above + * values.) + * \param olen The address at which to store the length of + * the output in Bytes. This must not be \c NULL. + * \param buf The output buffer. This must be a writable buffer + * of length \p buflen Bytes. + * \param buflen The length of the output buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output buffer + * is too small to hold the point. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the point format + * or the export for the given group is not implemented. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_point_write_binary(const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen); + +/** + * \brief This function imports a point from unsigned binary data. + * + * \note This function does not check that the point actually + * belongs to the given group, see mbedtls_ecp_check_pubkey() + * for that. + * + * \note For compressed points, see #MBEDTLS_ECP_PF_COMPRESSED for + * limitations. + * + * \param grp The group to which the point should belong. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param P The destination context to import the point to. + * This must be initialized. + * \param buf The input buffer. This must be a readable buffer + * of length \p ilen Bytes. + * \param ilen The length of the input buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the import for the + * given group is not implemented. + */ +int mbedtls_ecp_point_read_binary(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P, + const unsigned char *buf, size_t ilen); + +/** + * \brief This function imports a point from a TLS ECPoint record. + * + * \note On function return, \p *buf is updated to point immediately + * after the ECPoint record. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The destination point. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the buffer. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_MPI_XXX error code on initialization + * failure. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + */ +int mbedtls_ecp_tls_read_point(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t len); + +/** + * \brief This function exports a point as a TLS ECPoint record + * defined in RFC 4492, Section 5.4. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The point to be exported. This must be initialized. + * \param format The point format to use. This must be either + * #MBEDTLS_ECP_PF_COMPRESSED or #MBEDTLS_ECP_PF_UNCOMPRESSED. + * \param olen The address at which to store the length in Bytes + * of the data written. + * \param buf The target buffer. This must be a writable buffer of + * length \p blen Bytes. + * \param blen The length of the target buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the input is invalid. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the target buffer + * is too small to hold the exported point. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_write_point(const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen); + +/** + * \brief This function sets up an ECP group context + * from a standardized set of domain parameters. + * + * \note The index should be a value of the NamedCurve enum, + * as defined in RFC-4492: Elliptic Curve Cryptography + * (ECC) Cipher Suites for Transport Layer Security (TLS), + * usually in the form of an \c MBEDTLS_ECP_DP_XXX macro. + * + * \param grp The group context to setup. This must be initialized. + * \param id The identifier of the domain parameter set to load. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p id doesn't + * correspond to a known group. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_group_load(mbedtls_ecp_group *grp, mbedtls_ecp_group_id id); + +/** + * \brief This function sets up an ECP group context from a TLS + * ECParameters record as defined in RFC 4492, Section 5.4. + * + * \note The read pointer \p buf is updated to point right after + * the ECParameters record on exit. + * + * \param grp The group context to setup. This must be initialized. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the input buffer \c *buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not + * recognized. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_read_group(mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len); + +/** + * \brief This function extracts an elliptic curve group ID from a + * TLS ECParameters record as defined in RFC 4492, Section 5.4. + * + * \note The read pointer \p buf is updated to point right after + * the ECParameters record on exit. + * + * \param grp The address at which to store the group id. + * This must not be \c NULL. + * \param buf The address of the pointer to the start of the input buffer. + * \param len The length of the input buffer \c *buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if input is invalid. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the group is not + * recognized. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_read_group_id(mbedtls_ecp_group_id *grp, + const unsigned char **buf, + size_t len); +/** + * \brief This function exports an elliptic curve as a TLS + * ECParameters record as defined in RFC 4492, Section 5.4. + * + * \param grp The ECP group to be exported. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param olen The address at which to store the number of Bytes written. + * This must not be \c NULL. + * \param buf The buffer to write to. This must be a writable buffer + * of length \p blen Bytes. + * \param blen The length of the output buffer \p buf in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the output + * buffer is too small to hold the exported group. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_tls_write_group(const mbedtls_ecp_group *grp, + size_t *olen, + unsigned char *buf, size_t blen); + +/** + * \brief This function performs a scalar multiplication of a point + * by an integer: \p R = \p m * \p P. + * + * It is not thread-safe to use same group in multiple threads. + * + * \note To prevent timing attacks, this function + * executes the exact same sequence of base-field + * operations for any valid \p m. It avoids any if-branch or + * array index depending on the value of \p m. It also uses + * \p f_rng to randomize some intermediate results. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply. This must be initialized. + * \param P The point to multiply. This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c + * NULL if \p f_rng doesn't need a context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private + * key, or \p P is not a valid public key. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_mul(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** + * \brief This function performs multiplication of a point by + * an integer: \p R = \p m * \p P in a restartable way. + * + * \see mbedtls_ecp_mul() + * + * \note This function does the same as \c mbedtls_ecp_mul(), but + * it can return early and restart according to the limit set + * with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply. This must be initialized. + * \param P The point to multiply. This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c + * NULL if \p f_rng doesn't need a context. + * \param rs_ctx The restart context (NULL disables restart). + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m is not a valid private + * key, or \p P is not a valid public key. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_mul_restartable(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx); + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) +/** + * \brief This function checks if domain parameter A of the curve is + * \c -3. + * + * \note This function is only defined for short Weierstrass curves. + * It may not be included in builds without any short + * Weierstrass curve. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * + * \return \c 1 if A = -3. + * \return \c 0 Otherwise. + */ +static inline int mbedtls_ecp_group_a_is_minus_3(const mbedtls_ecp_group *grp) +{ + return grp->A.MBEDTLS_PRIVATE(p) == NULL; +} + +/** + * \brief This function performs multiplication and addition of two + * points by integers: \p R = \p m * \p P + \p n * \p Q + * + * It is not thread-safe to use same group in multiple threads. + * + * \note In contrast to mbedtls_ecp_mul(), this function does not + * guarantee a constant execution flow and timing. + * + * \note This function is only defined for short Weierstrass curves. + * It may not be included in builds without any short + * Weierstrass curve. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply \p P. + * This must be initialized. + * \param P The point to multiply by \p m. This must be initialized. + * \param n The integer by which to multiply \p Q. + * This must be initialized. + * \param Q The point to be multiplied by \p n. + * This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not + * valid private keys, or \p P or \p Q are not valid public + * keys. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p grp does not + * designate a short Weierstrass curve. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_muladd(mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q); + +/** + * \brief This function performs multiplication and addition of two + * points by integers: \p R = \p m * \p P + \p n * \p Q in a + * restartable way. + * + * \see \c mbedtls_ecp_muladd() + * + * \note This function works the same as \c mbedtls_ecp_muladd(), + * but it can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \note This function is only defined for short Weierstrass curves. + * It may not be included in builds without any short + * Weierstrass curve. + * + * \param grp The ECP group to use. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param R The point in which to store the result of the calculation. + * This must be initialized. + * \param m The integer by which to multiply \p P. + * This must be initialized. + * \param P The point to multiply by \p m. This must be initialized. + * \param n The integer by which to multiply \p Q. + * This must be initialized. + * \param Q The point to be multiplied by \p n. + * This must be initialized. + * \param rs_ctx The restart context (NULL disables restart). + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if \p m or \p n are not + * valid private keys, or \p P or \p Q are not valid public + * keys. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if \p grp does not + * designate a short Weierstrass curve. + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx); +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +/** + * \brief This function checks that a point is a valid public key + * on this curve. + * + * It only checks that the point is non-zero, has + * valid coordinates and lies on the curve. It does not verify + * that it is indeed a multiple of \c G. This additional + * check is computationally more expensive, is not required + * by standards, and should not be necessary if the group + * used has a small cofactor. In particular, it is useless for + * the NIST groups which all have a cofactor of 1. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure, to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group the point should belong to. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param pt The point to check. This must be initialized. + * + * \return \c 0 if the point is a valid public key. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not + * a valid public key for the given curve. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_check_pubkey(const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt); + +/** + * \brief This function checks that an \c mbedtls_mpi is a + * valid private key for this curve. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group the private key should belong to. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The integer to check. This must be initialized. + * + * \return \c 0 if the point is a valid private key. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY if the point is not a valid + * private key for the given curve. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_check_privkey(const mbedtls_ecp_group *grp, + const mbedtls_mpi *d); + +/** + * \brief This function generates a private key. + * + * \param grp The ECP group to generate a private key for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The destination MPI (secret part). This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_privkey(const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function generates a keypair with a configurable base + * point. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group to generate a key pair for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param G The base point to use. This must be initialized + * and belong to \p grp. It replaces the default base + * point \c grp->G used by mbedtls_ecp_gen_keypair(). + * \param d The destination MPI (secret part). + * This must be initialized. + * \param Q The destination point (public part). + * This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_keypair_base(mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function generates an ECP keypair. + * + * \note This function uses bare components rather than an + * ::mbedtls_ecp_keypair structure to ease use with other + * structures, such as ::mbedtls_ecdh_context or + * ::mbedtls_ecdsa_context. + * + * \param grp The ECP group to generate a key pair for. + * This must be initialized and have group parameters + * set, for example through mbedtls_ecp_group_load(). + * \param d The destination MPI (secret part). + * This must be initialized. + * \param Q The destination point (public part). + * This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_keypair(mbedtls_ecp_group *grp, mbedtls_mpi *d, + mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function generates an ECP key. + * + * \param grp_id The ECP group identifier. + * \param key The destination key. This must be initialized. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX or \c MBEDTLS_MPI_XXX error code + * on failure. + */ +int mbedtls_ecp_gen_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief This function reads an elliptic curve private key. + * + * \param grp_id The ECP group identifier. + * \param key The destination key. + * \param buf The buffer containing the binary representation of the + * key. (Big endian integer for Weierstrass curves, byte + * string for Montgomery curves.) + * \param buflen The length of the buffer in bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_INVALID_KEY error if the key is + * invalid. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the operation for + * the group is not implemented. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_ecp_read_key(mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + const unsigned char *buf, size_t buflen); + +/** + * \brief This function exports an elliptic curve private key. + * + * \param key The private key. + * \param buf The output buffer for containing the binary representation + * of the key. (Big endian integer for Weierstrass curves, byte + * string for Montgomery curves.) + * \param buflen The total length of the buffer in bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL if the \p key + representation is larger than the available space in \p buf. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if the operation for + * the group is not implemented. + * \return Another negative error code on different kinds of failure. + */ +int mbedtls_ecp_write_key(mbedtls_ecp_keypair *key, + unsigned char *buf, size_t buflen); + +/** + * \brief This function checks that the keypair objects + * \p pub and \p prv have the same group and the + * same public point, and that the private key in + * \p prv is consistent with the public key. + * + * \param pub The keypair structure holding the public key. This + * must be initialized. If it contains a private key, that + * part is ignored. + * \param prv The keypair structure holding the full keypair. + * This must be initialized. + * \param f_rng The RNG function. This must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c + * NULL if \p f_rng doesn't need a context. + * + * \return \c 0 on success, meaning that the keys are valid and match. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the keys are invalid or do not match. + * \return An \c MBEDTLS_ERR_ECP_XXX or an \c MBEDTLS_ERR_MPI_XXX + * error code on calculation failure. + */ +int mbedtls_ecp_check_pub_priv( + const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** + * \brief This function exports generic key-pair parameters. + * + * \param key The key pair to export from. + * \param grp Slot for exported ECP group. + * It must point to an initialized ECP group. + * \param d Slot for the exported secret value. + * It must point to an initialized mpi. + * \param Q Slot for the exported public value. + * It must point to an initialized ECP point. + * + * \return \c 0 on success, + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + * \return #MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE if key id doesn't + * correspond to a known group. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ecp_export(const mbedtls_ecp_keypair *key, mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The ECP checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_ecp_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecp.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/entropy.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/entropy.h index c2bba41..eca50b7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/entropy.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/entropy.h @@ -1,285 +1,285 @@ -/** - * \file entropy.h - * - * \brief Entropy accumulator implementation - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ENTROPY_H -#define MBEDTLS_ENTROPY_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include - -#include "md.h" - -#if defined(MBEDTLS_MD_CAN_SHA512) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) -#define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR -#define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA512 -#define MBEDTLS_ENTROPY_BLOCK_SIZE 64 /**< Block size of entropy accumulator (SHA-512) */ -#else -#if defined(MBEDTLS_MD_CAN_SHA256) -#define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR -#define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA256 -#define MBEDTLS_ENTROPY_BLOCK_SIZE 32 /**< Block size of entropy accumulator (SHA-256) */ -#endif -#endif - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - - -/** Critical entropy source failure. */ -#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED -0x003C -/** No more sources can be added. */ -#define MBEDTLS_ERR_ENTROPY_MAX_SOURCES -0x003E -/** No sources have been added to poll. */ -#define MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED -0x0040 -/** No strong sources have been added to poll. */ -#define MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE -0x003D -/** Read/write error in file. */ -#define MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR -0x003F - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -#if !defined(MBEDTLS_ENTROPY_MAX_SOURCES) -#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ -#endif - -#if !defined(MBEDTLS_ENTROPY_MAX_GATHER) -#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ -#endif - -/** \} name SECTION: Module settings */ - -#define MBEDTLS_ENTROPY_MAX_SEED_SIZE 1024 /**< Maximum size of seed we read from seed file */ -#define MBEDTLS_ENTROPY_SOURCE_MANUAL MBEDTLS_ENTROPY_MAX_SOURCES - -#define MBEDTLS_ENTROPY_SOURCE_STRONG 1 /**< Entropy source is strong */ -#define MBEDTLS_ENTROPY_SOURCE_WEAK 0 /**< Entropy source is weak */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Entropy poll callback pointer - * - * \param data Callback-specific data pointer - * \param output Data to fill - * \param len Maximum size to provide - * \param olen The actual amount of bytes put into the buffer (Can be 0) - * - * \return 0 if no critical failures occurred, - * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED otherwise - */ -typedef int (*mbedtls_entropy_f_source_ptr)(void *data, unsigned char *output, size_t len, - size_t *olen); - -/** - * \brief Entropy source state - */ -typedef struct mbedtls_entropy_source_state { - mbedtls_entropy_f_source_ptr MBEDTLS_PRIVATE(f_source); /**< The entropy source callback */ - void *MBEDTLS_PRIVATE(p_source); /**< The callback data pointer */ - size_t MBEDTLS_PRIVATE(size); /**< Amount received in bytes */ - size_t MBEDTLS_PRIVATE(threshold); /**< Minimum bytes required before release */ - int MBEDTLS_PRIVATE(strong); /**< Is the source strong? */ -} -mbedtls_entropy_source_state; - -/** - * \brief Entropy context structure - */ -typedef struct mbedtls_entropy_context { - mbedtls_md_context_t MBEDTLS_PRIVATE(accumulator); - int MBEDTLS_PRIVATE(accumulator_started); /* 0 after init. - * 1 after the first update. - * -1 after free. */ - int MBEDTLS_PRIVATE(source_count); /* Number of entries used in source. */ - mbedtls_entropy_source_state MBEDTLS_PRIVATE(source)[MBEDTLS_ENTROPY_MAX_SOURCES]; -#if defined(MBEDTLS_THREADING_C) - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< mutex */ -#endif -#if defined(MBEDTLS_ENTROPY_NV_SEED) - int MBEDTLS_PRIVATE(initial_entropy_run); -#endif -} -mbedtls_entropy_context; - -#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY) -/** - * \brief Platform-specific entropy poll callback - */ -int mbedtls_platform_entropy_poll(void *data, - unsigned char *output, size_t len, size_t *olen); -#endif - -/** - * \brief Initialize the context - * - * \param ctx Entropy context to initialize - */ -void mbedtls_entropy_init(mbedtls_entropy_context *ctx); - -/** - * \brief Free the data in the context - * - * \param ctx Entropy context to free - */ -void mbedtls_entropy_free(mbedtls_entropy_context *ctx); - -/** - * \brief Adds an entropy source to poll - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param ctx Entropy context - * \param f_source Entropy function - * \param p_source Function data - * \param threshold Minimum required from source before entropy is released - * ( with mbedtls_entropy_func() ) (in bytes) - * \param strong MBEDTLS_ENTROPY_SOURCE_STRONG or - * MBEDTLS_ENTROPY_SOURCE_WEAK. - * At least one strong source needs to be added. - * Weaker sources (such as the cycle counter) can be used as - * a complement. - * - * \return 0 if successful or MBEDTLS_ERR_ENTROPY_MAX_SOURCES - */ -int mbedtls_entropy_add_source(mbedtls_entropy_context *ctx, - mbedtls_entropy_f_source_ptr f_source, void *p_source, - size_t threshold, int strong); - -/** - * \brief Trigger an extra gather poll for the accumulator - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param ctx Entropy context - * - * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED - */ -int mbedtls_entropy_gather(mbedtls_entropy_context *ctx); - -/** - * \brief Retrieve entropy from the accumulator - * (Maximum length: MBEDTLS_ENTROPY_BLOCK_SIZE) - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param data Entropy context - * \param output Buffer to fill - * \param len Number of bytes desired, must be at most MBEDTLS_ENTROPY_BLOCK_SIZE - * - * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED - */ -int mbedtls_entropy_func(void *data, unsigned char *output, size_t len); - -/** - * \brief Add data to the accumulator manually - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param ctx Entropy context - * \param data Data to add - * \param len Length of data - * - * \return 0 if successful - */ -int mbedtls_entropy_update_manual(mbedtls_entropy_context *ctx, - const unsigned char *data, size_t len); - -#if defined(MBEDTLS_ENTROPY_NV_SEED) -/** - * \brief Trigger an update of the seed file in NV by using the - * current entropy pool. - * - * \param ctx Entropy context - * - * \return 0 if successful - */ -int mbedtls_entropy_update_nv_seed(mbedtls_entropy_context *ctx); -#endif /* MBEDTLS_ENTROPY_NV_SEED */ - -#if defined(MBEDTLS_FS_IO) -/** - * \brief Write a seed file - * - * \param ctx Entropy context - * \param path Name of the file - * - * \return 0 if successful, - * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, or - * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED - */ -int mbedtls_entropy_write_seed_file(mbedtls_entropy_context *ctx, const char *path); - -/** - * \brief Read and update a seed file. Seed is added to this - * instance. No more than MBEDTLS_ENTROPY_MAX_SEED_SIZE bytes are - * read from the seed file. The rest is ignored. - * - * \param ctx Entropy context - * \param path Name of the file - * - * \return 0 if successful, - * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, - * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED - */ -int mbedtls_entropy_update_seed_file(mbedtls_entropy_context *ctx, const char *path); -#endif /* MBEDTLS_FS_IO */ - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine - * - * This module self-test also calls the entropy self-test, - * mbedtls_entropy_source_self_test(); - * - * \return 0 if successful, or 1 if a test failed - */ -int mbedtls_entropy_self_test(int verbose); - -#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) -/** - * \brief Checkup routine - * - * Verifies the integrity of the hardware entropy source - * provided by the function 'mbedtls_hardware_poll()'. - * - * Note this is the only hardware entropy source that is known - * at link time, and other entropy sources configured - * dynamically at runtime by the function - * mbedtls_entropy_add_source() will not be tested. - * - * \return 0 if successful, or 1 if a test failed - */ -int mbedtls_entropy_source_self_test(int verbose); -#endif /* MBEDTLS_ENTROPY_HARDWARE_ALT */ -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* entropy.h */ +/** + * \file entropy.h + * + * \brief Entropy accumulator implementation + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ENTROPY_H +#define MBEDTLS_ENTROPY_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include + +#include "md.h" + +#if defined(MBEDTLS_MD_CAN_SHA512) && !defined(MBEDTLS_ENTROPY_FORCE_SHA256) +#define MBEDTLS_ENTROPY_SHA512_ACCUMULATOR +#define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA512 +#define MBEDTLS_ENTROPY_BLOCK_SIZE 64 /**< Block size of entropy accumulator (SHA-512) */ +#else +#if defined(MBEDTLS_MD_CAN_SHA256) +#define MBEDTLS_ENTROPY_SHA256_ACCUMULATOR +#define MBEDTLS_ENTROPY_MD MBEDTLS_MD_SHA256 +#define MBEDTLS_ENTROPY_BLOCK_SIZE 32 /**< Block size of entropy accumulator (SHA-256) */ +#endif +#endif + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + + +/** Critical entropy source failure. */ +#define MBEDTLS_ERR_ENTROPY_SOURCE_FAILED -0x003C +/** No more sources can be added. */ +#define MBEDTLS_ERR_ENTROPY_MAX_SOURCES -0x003E +/** No sources have been added to poll. */ +#define MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED -0x0040 +/** No strong sources have been added to poll. */ +#define MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE -0x003D +/** Read/write error in file. */ +#define MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR -0x003F + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ENTROPY_MAX_SOURCES) +#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +#endif + +#if !defined(MBEDTLS_ENTROPY_MAX_GATHER) +#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +#endif + +/** \} name SECTION: Module settings */ + +#define MBEDTLS_ENTROPY_MAX_SEED_SIZE 1024 /**< Maximum size of seed we read from seed file */ +#define MBEDTLS_ENTROPY_SOURCE_MANUAL MBEDTLS_ENTROPY_MAX_SOURCES + +#define MBEDTLS_ENTROPY_SOURCE_STRONG 1 /**< Entropy source is strong */ +#define MBEDTLS_ENTROPY_SOURCE_WEAK 0 /**< Entropy source is weak */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Entropy poll callback pointer + * + * \param data Callback-specific data pointer + * \param output Data to fill + * \param len Maximum size to provide + * \param olen The actual amount of bytes put into the buffer (Can be 0) + * + * \return 0 if no critical failures occurred, + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED otherwise + */ +typedef int (*mbedtls_entropy_f_source_ptr)(void *data, unsigned char *output, size_t len, + size_t *olen); + +/** + * \brief Entropy source state + */ +typedef struct mbedtls_entropy_source_state { + mbedtls_entropy_f_source_ptr MBEDTLS_PRIVATE(f_source); /**< The entropy source callback */ + void *MBEDTLS_PRIVATE(p_source); /**< The callback data pointer */ + size_t MBEDTLS_PRIVATE(size); /**< Amount received in bytes */ + size_t MBEDTLS_PRIVATE(threshold); /**< Minimum bytes required before release */ + int MBEDTLS_PRIVATE(strong); /**< Is the source strong? */ +} +mbedtls_entropy_source_state; + +/** + * \brief Entropy context structure + */ +typedef struct mbedtls_entropy_context { + mbedtls_md_context_t MBEDTLS_PRIVATE(accumulator); + int MBEDTLS_PRIVATE(accumulator_started); /* 0 after init. + * 1 after the first update. + * -1 after free. */ + int MBEDTLS_PRIVATE(source_count); /* Number of entries used in source. */ + mbedtls_entropy_source_state MBEDTLS_PRIVATE(source)[MBEDTLS_ENTROPY_MAX_SOURCES]; +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< mutex */ +#endif +#if defined(MBEDTLS_ENTROPY_NV_SEED) + int MBEDTLS_PRIVATE(initial_entropy_run); +#endif +} +mbedtls_entropy_context; + +#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY) +/** + * \brief Platform-specific entropy poll callback + */ +int mbedtls_platform_entropy_poll(void *data, + unsigned char *output, size_t len, size_t *olen); +#endif + +/** + * \brief Initialize the context + * + * \param ctx Entropy context to initialize + */ +void mbedtls_entropy_init(mbedtls_entropy_context *ctx); + +/** + * \brief Free the data in the context + * + * \param ctx Entropy context to free + */ +void mbedtls_entropy_free(mbedtls_entropy_context *ctx); + +/** + * \brief Adds an entropy source to poll + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * \param f_source Entropy function + * \param p_source Function data + * \param threshold Minimum required from source before entropy is released + * ( with mbedtls_entropy_func() ) (in bytes) + * \param strong MBEDTLS_ENTROPY_SOURCE_STRONG or + * MBEDTLS_ENTROPY_SOURCE_WEAK. + * At least one strong source needs to be added. + * Weaker sources (such as the cycle counter) can be used as + * a complement. + * + * \return 0 if successful or MBEDTLS_ERR_ENTROPY_MAX_SOURCES + */ +int mbedtls_entropy_add_source(mbedtls_entropy_context *ctx, + mbedtls_entropy_f_source_ptr f_source, void *p_source, + size_t threshold, int strong); + +/** + * \brief Trigger an extra gather poll for the accumulator + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * + * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_gather(mbedtls_entropy_context *ctx); + +/** + * \brief Retrieve entropy from the accumulator + * (Maximum length: MBEDTLS_ENTROPY_BLOCK_SIZE) + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param data Entropy context + * \param output Buffer to fill + * \param len Number of bytes desired, must be at most MBEDTLS_ENTROPY_BLOCK_SIZE + * + * \return 0 if successful, or MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_func(void *data, unsigned char *output, size_t len); + +/** + * \brief Add data to the accumulator manually + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param ctx Entropy context + * \param data Data to add + * \param len Length of data + * + * \return 0 if successful + */ +int mbedtls_entropy_update_manual(mbedtls_entropy_context *ctx, + const unsigned char *data, size_t len); + +#if defined(MBEDTLS_ENTROPY_NV_SEED) +/** + * \brief Trigger an update of the seed file in NV by using the + * current entropy pool. + * + * \param ctx Entropy context + * + * \return 0 if successful + */ +int mbedtls_entropy_update_nv_seed(mbedtls_entropy_context *ctx); +#endif /* MBEDTLS_ENTROPY_NV_SEED */ + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Write a seed file + * + * \param ctx Entropy context + * \param path Name of the file + * + * \return 0 if successful, + * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, or + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_write_seed_file(mbedtls_entropy_context *ctx, const char *path); + +/** + * \brief Read and update a seed file. Seed is added to this + * instance. No more than MBEDTLS_ENTROPY_MAX_SEED_SIZE bytes are + * read from the seed file. The rest is ignored. + * + * \param ctx Entropy context + * \param path Name of the file + * + * \return 0 if successful, + * MBEDTLS_ERR_ENTROPY_FILE_IO_ERROR on file error, + * MBEDTLS_ERR_ENTROPY_SOURCE_FAILED + */ +int mbedtls_entropy_update_seed_file(mbedtls_entropy_context *ctx, const char *path); +#endif /* MBEDTLS_FS_IO */ + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine + * + * This module self-test also calls the entropy self-test, + * mbedtls_entropy_source_self_test(); + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_entropy_self_test(int verbose); + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +/** + * \brief Checkup routine + * + * Verifies the integrity of the hardware entropy source + * provided by the function 'mbedtls_hardware_poll()'. + * + * Note this is the only hardware entropy source that is known + * at link time, and other entropy sources configured + * dynamically at runtime by the function + * mbedtls_entropy_add_source() will not be tested. + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_entropy_source_self_test(int verbose); +#endif /* MBEDTLS_ENTROPY_HARDWARE_ALT */ +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* entropy.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/error.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/error.h index 1372ba0..8e0c334 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/error.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/error.h @@ -1,213 +1,213 @@ -/** - * \file mbedtls/error.h - * - * \brief Error to string translation - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ERROR_H -#define MBEDTLS_ERROR_H - -#include "mbedtls/build_info.h" - -#include - -/** - * Error code layout. - * - * Currently we try to keep all error codes within the negative space of 16 - * bits signed integers to support all platforms (-0x0001 - -0x7FFF). In - * addition we'd like to give two layers of information on the error if - * possible. - * - * For that purpose the error codes are segmented in the following manner: - * - * 16 bit error code bit-segmentation - * - * 1 bit - Unused (sign bit) - * 3 bits - High level module ID - * 5 bits - Module-dependent error code - * 7 bits - Low level module errors - * - * For historical reasons, low-level error codes are divided in even and odd, - * even codes were assigned first, and -1 is reserved for other errors. - * - * Low-level module errors (0x0002-0x007E, 0x0001-0x007F) - * - * Module Nr Codes assigned - * ERROR 2 0x006E 0x0001 - * MPI 7 0x0002-0x0010 - * GCM 3 0x0012-0x0016 0x0013-0x0013 - * THREADING 3 0x001A-0x001E - * AES 5 0x0020-0x0022 0x0021-0x0025 - * CAMELLIA 3 0x0024-0x0026 0x0027-0x0027 - * BASE64 2 0x002A-0x002C - * OID 1 0x002E-0x002E 0x000B-0x000B - * PADLOCK 1 0x0030-0x0030 - * DES 2 0x0032-0x0032 0x0033-0x0033 - * CTR_DBRG 4 0x0034-0x003A - * ENTROPY 3 0x003C-0x0040 0x003D-0x003F - * NET 13 0x0042-0x0052 0x0043-0x0049 - * ARIA 4 0x0058-0x005E - * ASN1 7 0x0060-0x006C - * CMAC 1 0x007A-0x007A - * PBKDF2 1 0x007C-0x007C - * HMAC_DRBG 4 0x0003-0x0009 - * CCM 3 0x000D-0x0011 - * MD5 1 0x002F-0x002F - * RIPEMD160 1 0x0031-0x0031 - * SHA1 1 0x0035-0x0035 0x0073-0x0073 - * SHA256 1 0x0037-0x0037 0x0074-0x0074 - * SHA512 1 0x0039-0x0039 0x0075-0x0075 - * SHA-3 1 0x0076-0x0076 - * CHACHA20 3 0x0051-0x0055 - * POLY1305 3 0x0057-0x005B - * CHACHAPOLY 2 0x0054-0x0056 - * PLATFORM 2 0x0070-0x0072 - * LMS 5 0x0011-0x0019 - * - * High-level module nr (3 bits - 0x0...-0x7...) - * Name ID Nr of Errors - * PEM 1 9 - * PKCS#12 1 4 (Started from top) - * X509 2 20 - * PKCS5 2 4 (Started from top) - * DHM 3 11 - * PK 3 15 (Started from top) - * RSA 4 11 - * ECP 4 10 (Started from top) - * MD 5 5 - * HKDF 5 1 (Started from top) - * PKCS7 5 12 (Started from 0x5300) - * SSL 5 2 (Started from 0x5F00) - * CIPHER 6 8 (Started from 0x6080) - * SSL 6 22 (Started from top, plus 0x6000) - * SSL 7 20 (Started from 0x7000, gaps at - * 0x7380, 0x7900-0x7980, 0x7A80-0x7E80) - * - * Module dependent error code (5 bits 0x.00.-0x.F8.) - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Generic error */ -#define MBEDTLS_ERR_ERROR_GENERIC_ERROR -0x0001 -/** This is a bug in the library */ -#define MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED -0x006E - -/** Hardware accelerator failed */ -#define MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED -0x0070 -/** The requested feature is not supported by the platform */ -#define MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED -0x0072 - -/** - * \brief Combines a high-level and low-level error code together. - * - * Wrapper macro for mbedtls_error_add(). See that function for - * more details. - */ -#define MBEDTLS_ERROR_ADD(high, low) \ - mbedtls_error_add(high, low, __FILE__, __LINE__) - -#if defined(MBEDTLS_TEST_HOOKS) -/** - * \brief Testing hook called before adding/combining two error codes together. - * Only used when invasive testing is enabled via MBEDTLS_TEST_HOOKS. - */ -extern void (*mbedtls_test_hook_error_add)(int, int, const char *, int); -#endif - -/** - * \brief Combines a high-level and low-level error code together. - * - * This function can be called directly however it is usually - * called via the #MBEDTLS_ERROR_ADD macro. - * - * While a value of zero is not a negative error code, it is still an - * error code (that denotes success) and can be combined with both a - * negative error code or another value of zero. - * - * \note When invasive testing is enabled via #MBEDTLS_TEST_HOOKS, also try to - * call \link mbedtls_test_hook_error_add \endlink. - * - * \param high high-level error code. See error.h for more details. - * \param low low-level error code. See error.h for more details. - * \param file file where this error code addition occurred. - * \param line line where this error code addition occurred. - */ -static inline int mbedtls_error_add(int high, int low, - const char *file, int line) -{ -#if defined(MBEDTLS_TEST_HOOKS) - if (*mbedtls_test_hook_error_add != NULL) { - (*mbedtls_test_hook_error_add)(high, low, file, line); - } -#endif - (void) file; - (void) line; - - return high + low; -} - -/** - * \brief Translate an Mbed TLS error code into a string representation. - * The result is truncated if necessary and always includes a - * terminating null byte. - * - * \param errnum error code - * \param buffer buffer to place representation in - * \param buflen length of the buffer - */ -void mbedtls_strerror(int errnum, char *buffer, size_t buflen); - -/** - * \brief Translate the high-level part of an Mbed TLS error code into a string - * representation. - * - * This function returns a const pointer to an un-modifiable string. The caller - * must not try to modify the string. It is intended to be used mostly for - * logging purposes. - * - * \param error_code error code - * - * \return The string representation of the error code, or \c NULL if the error - * code is unknown. - */ -const char *mbedtls_high_level_strerr(int error_code); - -/** - * \brief Translate the low-level part of an Mbed TLS error code into a string - * representation. - * - * This function returns a const pointer to an un-modifiable string. The caller - * must not try to modify the string. It is intended to be used mostly for - * logging purposes. - * - * \param error_code error code - * - * \return The string representation of the error code, or \c NULL if the error - * code is unknown. - */ -const char *mbedtls_low_level_strerr(int error_code); - -#ifdef __cplusplus -} -#endif - -#endif /* error.h */ +/** + * \file mbedtls/error.h + * + * \brief Error to string translation + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ERROR_H +#define MBEDTLS_ERROR_H + +#include "mbedtls/build_info.h" + +#include + +/** + * Error code layout. + * + * Currently we try to keep all error codes within the negative space of 16 + * bits signed integers to support all platforms (-0x0001 - -0x7FFF). In + * addition we'd like to give two layers of information on the error if + * possible. + * + * For that purpose the error codes are segmented in the following manner: + * + * 16 bit error code bit-segmentation + * + * 1 bit - Unused (sign bit) + * 3 bits - High level module ID + * 5 bits - Module-dependent error code + * 7 bits - Low level module errors + * + * For historical reasons, low-level error codes are divided in even and odd, + * even codes were assigned first, and -1 is reserved for other errors. + * + * Low-level module errors (0x0002-0x007E, 0x0001-0x007F) + * + * Module Nr Codes assigned + * ERROR 2 0x006E 0x0001 + * MPI 7 0x0002-0x0010 + * GCM 3 0x0012-0x0016 0x0013-0x0013 + * THREADING 3 0x001A-0x001E + * AES 5 0x0020-0x0022 0x0021-0x0025 + * CAMELLIA 3 0x0024-0x0026 0x0027-0x0027 + * BASE64 2 0x002A-0x002C + * OID 1 0x002E-0x002E 0x000B-0x000B + * PADLOCK 1 0x0030-0x0030 + * DES 2 0x0032-0x0032 0x0033-0x0033 + * CTR_DBRG 4 0x0034-0x003A + * ENTROPY 3 0x003C-0x0040 0x003D-0x003F + * NET 13 0x0042-0x0052 0x0043-0x0049 + * ARIA 4 0x0058-0x005E + * ASN1 7 0x0060-0x006C + * CMAC 1 0x007A-0x007A + * PBKDF2 1 0x007C-0x007C + * HMAC_DRBG 4 0x0003-0x0009 + * CCM 3 0x000D-0x0011 + * MD5 1 0x002F-0x002F + * RIPEMD160 1 0x0031-0x0031 + * SHA1 1 0x0035-0x0035 0x0073-0x0073 + * SHA256 1 0x0037-0x0037 0x0074-0x0074 + * SHA512 1 0x0039-0x0039 0x0075-0x0075 + * SHA-3 1 0x0076-0x0076 + * CHACHA20 3 0x0051-0x0055 + * POLY1305 3 0x0057-0x005B + * CHACHAPOLY 2 0x0054-0x0056 + * PLATFORM 2 0x0070-0x0072 + * LMS 5 0x0011-0x0019 + * + * High-level module nr (3 bits - 0x0...-0x7...) + * Name ID Nr of Errors + * PEM 1 9 + * PKCS#12 1 4 (Started from top) + * X509 2 20 + * PKCS5 2 4 (Started from top) + * DHM 3 11 + * PK 3 15 (Started from top) + * RSA 4 11 + * ECP 4 10 (Started from top) + * MD 5 5 + * HKDF 5 1 (Started from top) + * PKCS7 5 12 (Started from 0x5300) + * SSL 5 2 (Started from 0x5F00) + * CIPHER 6 8 (Started from 0x6080) + * SSL 6 22 (Started from top, plus 0x6000) + * SSL 7 20 (Started from 0x7000, gaps at + * 0x7380, 0x7900-0x7980, 0x7A80-0x7E80) + * + * Module dependent error code (5 bits 0x.00.-0x.F8.) + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Generic error */ +#define MBEDTLS_ERR_ERROR_GENERIC_ERROR -0x0001 +/** This is a bug in the library */ +#define MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED -0x006E + +/** Hardware accelerator failed */ +#define MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED -0x0070 +/** The requested feature is not supported by the platform */ +#define MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED -0x0072 + +/** + * \brief Combines a high-level and low-level error code together. + * + * Wrapper macro for mbedtls_error_add(). See that function for + * more details. + */ +#define MBEDTLS_ERROR_ADD(high, low) \ + mbedtls_error_add(high, low, __FILE__, __LINE__) + +#if defined(MBEDTLS_TEST_HOOKS) +/** + * \brief Testing hook called before adding/combining two error codes together. + * Only used when invasive testing is enabled via MBEDTLS_TEST_HOOKS. + */ +extern void (*mbedtls_test_hook_error_add)(int, int, const char *, int); +#endif + +/** + * \brief Combines a high-level and low-level error code together. + * + * This function can be called directly however it is usually + * called via the #MBEDTLS_ERROR_ADD macro. + * + * While a value of zero is not a negative error code, it is still an + * error code (that denotes success) and can be combined with both a + * negative error code or another value of zero. + * + * \note When invasive testing is enabled via #MBEDTLS_TEST_HOOKS, also try to + * call \link mbedtls_test_hook_error_add \endlink. + * + * \param high high-level error code. See error.h for more details. + * \param low low-level error code. See error.h for more details. + * \param file file where this error code addition occurred. + * \param line line where this error code addition occurred. + */ +static inline int mbedtls_error_add(int high, int low, + const char *file, int line) +{ +#if defined(MBEDTLS_TEST_HOOKS) + if (*mbedtls_test_hook_error_add != NULL) { + (*mbedtls_test_hook_error_add)(high, low, file, line); + } +#endif + (void) file; + (void) line; + + return high + low; +} + +/** + * \brief Translate an Mbed TLS error code into a string representation. + * The result is truncated if necessary and always includes a + * terminating null byte. + * + * \param errnum error code + * \param buffer buffer to place representation in + * \param buflen length of the buffer + */ +void mbedtls_strerror(int errnum, char *buffer, size_t buflen); + +/** + * \brief Translate the high-level part of an Mbed TLS error code into a string + * representation. + * + * This function returns a const pointer to an un-modifiable string. The caller + * must not try to modify the string. It is intended to be used mostly for + * logging purposes. + * + * \param error_code error code + * + * \return The string representation of the error code, or \c NULL if the error + * code is unknown. + */ +const char *mbedtls_high_level_strerr(int error_code); + +/** + * \brief Translate the low-level part of an Mbed TLS error code into a string + * representation. + * + * This function returns a const pointer to an un-modifiable string. The caller + * must not try to modify the string. It is intended to be used mostly for + * logging purposes. + * + * \param error_code error code + * + * \return The string representation of the error code, or \c NULL if the error + * code is unknown. + */ +const char *mbedtls_low_level_strerr(int error_code); + +#ifdef __cplusplus +} +#endif + +#endif /* error.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/gcm.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/gcm.h index c3343e6..0af8e68 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/gcm.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/gcm.h @@ -1,382 +1,382 @@ -/** - * \file gcm.h - * - * \brief This file contains GCM definitions and functions. - * - * The Galois/Counter Mode (GCM) for 128-bit block ciphers is defined - * in D. McGrew, J. Viega, The Galois/Counter Mode of Operation - * (GCM), Natl. Inst. Stand. Technol. - * - * For more information on GCM, see NIST SP 800-38D: Recommendation for - * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_GCM_H -#define MBEDTLS_GCM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/cipher.h" - -#include - -#define MBEDTLS_GCM_ENCRYPT 1 -#define MBEDTLS_GCM_DECRYPT 0 - -/** Authenticated decryption failed. */ -#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 -/** An output buffer is too small. */ -#define MBEDTLS_ERR_GCM_BUFFER_TOO_SMALL -0x0016 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_GCM_ALT) - -/** - * \brief The GCM context structure. - */ -typedef struct mbedtls_gcm_context { - mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ - uint64_t MBEDTLS_PRIVATE(HL)[16]; /*!< Precalculated HTable low. */ - uint64_t MBEDTLS_PRIVATE(HH)[16]; /*!< Precalculated HTable high. */ - uint64_t MBEDTLS_PRIVATE(len); /*!< The total length of the encrypted data. */ - uint64_t MBEDTLS_PRIVATE(add_len); /*!< The total length of the additional data. */ - unsigned char MBEDTLS_PRIVATE(base_ectr)[16]; /*!< The first ECTR for tag. */ - unsigned char MBEDTLS_PRIVATE(y)[16]; /*!< The Y working value. */ - unsigned char MBEDTLS_PRIVATE(buf)[16]; /*!< The buf working value. */ - int MBEDTLS_PRIVATE(mode); /*!< The operation to perform: - #MBEDTLS_GCM_ENCRYPT or - #MBEDTLS_GCM_DECRYPT. */ -} -mbedtls_gcm_context; - -#else /* !MBEDTLS_GCM_ALT */ -#include "gcm_alt.h" -#endif /* !MBEDTLS_GCM_ALT */ - -/** - * \brief This function initializes the specified GCM context, - * to make references valid, and prepares the context - * for mbedtls_gcm_setkey() or mbedtls_gcm_free(). - * - * The function does not bind the GCM context to a particular - * cipher, nor set the key. For this purpose, use - * mbedtls_gcm_setkey(). - * - * \param ctx The GCM context to initialize. This must not be \c NULL. - */ -void mbedtls_gcm_init(mbedtls_gcm_context *ctx); - -/** - * \brief This function associates a GCM context with a - * cipher algorithm and a key. - * - * \param ctx The GCM context. This must be initialized. - * \param cipher The 128-bit block cipher to use. - * \param key The encryption key. This must be a readable buffer of at - * least \p keybits bits. - * \param keybits The key size in bits. Valid options are: - *
  • 128 bits
    • - *
  • 192 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return A cipher-specific error code on failure. - */ -int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, - mbedtls_cipher_id_t cipher, - const unsigned char *key, - unsigned int keybits); - -/** - * \brief This function performs GCM encryption or decryption of a buffer. - * - * \note For encryption, the output buffer can be the same as the - * input buffer. For decryption, the output buffer cannot be - * the same as input buffer. If the buffers overlap, the output - * buffer must trail at least 8 Bytes behind the input buffer. - * - * \warning When this function performs a decryption, it outputs the - * authentication tag and does not verify that the data is - * authentic. You should use this function to perform encryption - * only. For decryption, use mbedtls_gcm_auth_decrypt() instead. - * - * \param ctx The GCM context to use for encryption or decryption. This - * must be initialized. - * \param mode The operation to perform: - * - #MBEDTLS_GCM_ENCRYPT to perform authenticated encryption. - * The ciphertext is written to \p output and the - * authentication tag is written to \p tag. - * - #MBEDTLS_GCM_DECRYPT to perform decryption. - * The plaintext is written to \p output and the - * authentication tag is written to \p tag. - * Note that this mode is not recommended, because it does - * not verify the authenticity of the data. For this reason, - * you should use mbedtls_gcm_auth_decrypt() instead of - * calling this function in decryption mode. - * \param length The length of the input data, which is equal to the length - * of the output data. - * \param iv The initialization vector. This must be a readable buffer of - * at least \p iv_len Bytes. - * \param iv_len The length of the IV. - * \param add The buffer holding the additional data. This must be of at - * least that size in Bytes. - * \param add_len The length of the additional data. - * \param input The buffer holding the input data. If \p length is greater - * than zero, this must be a readable buffer of at least that - * size in Bytes. - * \param output The buffer for holding the output data. If \p length is greater - * than zero, this must be a writable buffer of at least that - * size in Bytes. - * \param tag_len The length of the tag to generate. - * \param tag The buffer for holding the tag. This must be a writable - * buffer of at least \p tag_len Bytes. - * - * \return \c 0 if the encryption or decryption was performed - * successfully. Note that in #MBEDTLS_GCM_DECRYPT mode, - * this does not indicate that the data is authentic. - * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are - * not valid or a cipher-specific error code if the encryption - * or decryption failed. - */ -int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, - int mode, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *input, - unsigned char *output, - size_t tag_len, - unsigned char *tag); - -/** - * \brief This function performs a GCM authenticated decryption of a - * buffer. - * - * \note For decryption, the output buffer cannot be the same as - * input buffer. If the buffers overlap, the output buffer - * must trail at least 8 Bytes behind the input buffer. - * - * \param ctx The GCM context. This must be initialized. - * \param length The length of the ciphertext to decrypt, which is also - * the length of the decrypted plaintext. - * \param iv The initialization vector. This must be a readable buffer - * of at least \p iv_len Bytes. - * \param iv_len The length of the IV. - * \param add The buffer holding the additional data. This must be of at - * least that size in Bytes. - * \param add_len The length of the additional data. - * \param tag The buffer holding the tag to verify. This must be a - * readable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the tag to verify. - * \param input The buffer holding the ciphertext. If \p length is greater - * than zero, this must be a readable buffer of at least that - * size. - * \param output The buffer for holding the decrypted plaintext. If \p length - * is greater than zero, this must be a writable buffer of at - * least that size. - * - * \return \c 0 if successful and authenticated. - * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. - * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are - * not valid or a cipher-specific error code if the decryption - * failed. - */ -int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, - size_t length, - const unsigned char *iv, - size_t iv_len, - const unsigned char *add, - size_t add_len, - const unsigned char *tag, - size_t tag_len, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function starts a GCM encryption or decryption - * operation. - * - * \param ctx The GCM context. This must be initialized. - * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or - * #MBEDTLS_GCM_DECRYPT. - * \param iv The initialization vector. This must be a readable buffer of - * at least \p iv_len Bytes. - * \param iv_len The length of the IV. - * - * \return \c 0 on success. - */ -int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, - int mode, - const unsigned char *iv, - size_t iv_len); - -/** - * \brief This function feeds an input buffer as associated data - * (authenticated but not encrypted data) in a GCM - * encryption or decryption operation. - * - * Call this function after mbedtls_gcm_starts() to pass - * the associated data. If the associated data is empty, - * you do not need to call this function. You may not - * call this function after calling mbedtls_cipher_update(). - * - * \param ctx The GCM context. This must have been started with - * mbedtls_gcm_starts() and must not have yet received - * any input with mbedtls_gcm_update(). - * \param add The buffer holding the additional data, or \c NULL - * if \p add_len is \c 0. - * \param add_len The length of the additional data. If \c 0, - * \p add may be \c NULL. - * - * \return \c 0 on success. - */ -int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, - const unsigned char *add, - size_t add_len); - -/** - * \brief This function feeds an input buffer into an ongoing GCM - * encryption or decryption operation. - * - * You may call this function zero, one or more times - * to pass successive parts of the input: the plaintext to - * encrypt, or the ciphertext (not including the tag) to - * decrypt. After the last part of the input, call - * mbedtls_gcm_finish(). - * - * This function may produce output in one of the following - * ways: - * - Immediate output: the output length is always equal - * to the input length. - * - Buffered output: the output consists of a whole number - * of 16-byte blocks. If the total input length so far - * (not including associated data) is 16 \* *B* + *A* - * with *A* < 16 then the total output length is 16 \* *B*. - * - * In particular: - * - It is always correct to call this function with - * \p output_size >= \p input_length + 15. - * - If \p input_length is a multiple of 16 for all the calls - * to this function during an operation, then it is - * correct to use \p output_size = \p input_length. - * - * \note For decryption, the output buffer cannot be the same as - * input buffer. If the buffers overlap, the output buffer - * must trail at least 8 Bytes behind the input buffer. - * - * \param ctx The GCM context. This must be initialized. - * \param input The buffer holding the input data. If \p input_length - * is greater than zero, this must be a readable buffer - * of at least \p input_length bytes. - * \param input_length The length of the input data in bytes. - * \param output The buffer for the output data. If \p output_size - * is greater than zero, this must be a writable buffer of - * of at least \p output_size bytes. - * \param output_size The size of the output buffer in bytes. - * See the function description regarding the output size. - * \param output_length On success, \p *output_length contains the actual - * length of the output written in \p output. - * On failure, the content of \p *output_length is - * unspecified. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure: - * total input length too long, - * unsupported input/output buffer overlap detected, - * or \p output_size too small. - */ -int mbedtls_gcm_update(mbedtls_gcm_context *ctx, - const unsigned char *input, size_t input_length, - unsigned char *output, size_t output_size, - size_t *output_length); - -/** - * \brief This function finishes the GCM operation and generates - * the authentication tag. - * - * It wraps up the GCM stream, and generates the - * tag. The tag can have a maximum length of 16 Bytes. - * - * \param ctx The GCM context. This must be initialized. - * \param tag The buffer for holding the tag. This must be a writable - * buffer of at least \p tag_len Bytes. - * \param tag_len The length of the tag to generate. This must be at least - * four. - * \param output The buffer for the final output. - * If \p output_size is nonzero, this must be a writable - * buffer of at least \p output_size bytes. - * \param output_size The size of the \p output buffer in bytes. - * This must be large enough for the output that - * mbedtls_gcm_update() has not produced. In particular: - * - If mbedtls_gcm_update() produces immediate output, - * or if the total input size is a multiple of \c 16, - * then mbedtls_gcm_finish() never produces any output, - * so \p output_size can be \c 0. - * - \p output_size never needs to be more than \c 15. - * \param output_length On success, \p *output_length contains the actual - * length of the output written in \p output. - * On failure, the content of \p *output_length is - * unspecified. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure: - * invalid value of \p tag_len, - * or \p output_size too small. - */ -int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, - unsigned char *output, size_t output_size, - size_t *output_length, - unsigned char *tag, size_t tag_len); - -/** - * \brief This function clears a GCM context and the underlying - * cipher sub-context. - * - * \param ctx The GCM context to clear. If this is \c NULL, the call has - * no effect. Otherwise, this must be initialized. - */ -void mbedtls_gcm_free(mbedtls_gcm_context *ctx); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The GCM checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_gcm_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - - -#endif /* gcm.h */ +/** + * \file gcm.h + * + * \brief This file contains GCM definitions and functions. + * + * The Galois/Counter Mode (GCM) for 128-bit block ciphers is defined + * in D. McGrew, J. Viega, The Galois/Counter Mode of Operation + * (GCM), Natl. Inst. Stand. Technol. + * + * For more information on GCM, see NIST SP 800-38D: Recommendation for + * Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_GCM_H +#define MBEDTLS_GCM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/cipher.h" + +#include + +#define MBEDTLS_GCM_ENCRYPT 1 +#define MBEDTLS_GCM_DECRYPT 0 + +/** Authenticated decryption failed. */ +#define MBEDTLS_ERR_GCM_AUTH_FAILED -0x0012 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_GCM_BAD_INPUT -0x0014 +/** An output buffer is too small. */ +#define MBEDTLS_ERR_GCM_BUFFER_TOO_SMALL -0x0016 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_GCM_ALT) + +/** + * \brief The GCM context structure. + */ +typedef struct mbedtls_gcm_context { + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ + uint64_t MBEDTLS_PRIVATE(HL)[16]; /*!< Precalculated HTable low. */ + uint64_t MBEDTLS_PRIVATE(HH)[16]; /*!< Precalculated HTable high. */ + uint64_t MBEDTLS_PRIVATE(len); /*!< The total length of the encrypted data. */ + uint64_t MBEDTLS_PRIVATE(add_len); /*!< The total length of the additional data. */ + unsigned char MBEDTLS_PRIVATE(base_ectr)[16]; /*!< The first ECTR for tag. */ + unsigned char MBEDTLS_PRIVATE(y)[16]; /*!< The Y working value. */ + unsigned char MBEDTLS_PRIVATE(buf)[16]; /*!< The buf working value. */ + int MBEDTLS_PRIVATE(mode); /*!< The operation to perform: + #MBEDTLS_GCM_ENCRYPT or + #MBEDTLS_GCM_DECRYPT. */ +} +mbedtls_gcm_context; + +#else /* !MBEDTLS_GCM_ALT */ +#include "gcm_alt.h" +#endif /* !MBEDTLS_GCM_ALT */ + +/** + * \brief This function initializes the specified GCM context, + * to make references valid, and prepares the context + * for mbedtls_gcm_setkey() or mbedtls_gcm_free(). + * + * The function does not bind the GCM context to a particular + * cipher, nor set the key. For this purpose, use + * mbedtls_gcm_setkey(). + * + * \param ctx The GCM context to initialize. This must not be \c NULL. + */ +void mbedtls_gcm_init(mbedtls_gcm_context *ctx); + +/** + * \brief This function associates a GCM context with a + * cipher algorithm and a key. + * + * \param ctx The GCM context. This must be initialized. + * \param cipher The 128-bit block cipher to use. + * \param key The encryption key. This must be a readable buffer of at + * least \p keybits bits. + * \param keybits The key size in bits. Valid options are: + *
  • 128 bits
    • + *
  • 192 bits
    • + *
  • 256 bits
+ * + * \return \c 0 on success. + * \return A cipher-specific error code on failure. + */ +int mbedtls_gcm_setkey(mbedtls_gcm_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits); + +/** + * \brief This function performs GCM encryption or decryption of a buffer. + * + * \note For encryption, the output buffer can be the same as the + * input buffer. For decryption, the output buffer cannot be + * the same as input buffer. If the buffers overlap, the output + * buffer must trail at least 8 Bytes behind the input buffer. + * + * \warning When this function performs a decryption, it outputs the + * authentication tag and does not verify that the data is + * authentic. You should use this function to perform encryption + * only. For decryption, use mbedtls_gcm_auth_decrypt() instead. + * + * \param ctx The GCM context to use for encryption or decryption. This + * must be initialized. + * \param mode The operation to perform: + * - #MBEDTLS_GCM_ENCRYPT to perform authenticated encryption. + * The ciphertext is written to \p output and the + * authentication tag is written to \p tag. + * - #MBEDTLS_GCM_DECRYPT to perform decryption. + * The plaintext is written to \p output and the + * authentication tag is written to \p tag. + * Note that this mode is not recommended, because it does + * not verify the authenticity of the data. For this reason, + * you should use mbedtls_gcm_auth_decrypt() instead of + * calling this function in decryption mode. + * \param length The length of the input data, which is equal to the length + * of the output data. + * \param iv The initialization vector. This must be a readable buffer of + * at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. This must be of at + * least that size in Bytes. + * \param add_len The length of the additional data. + * \param input The buffer holding the input data. If \p length is greater + * than zero, this must be a readable buffer of at least that + * size in Bytes. + * \param output The buffer for holding the output data. If \p length is greater + * than zero, this must be a writable buffer of at least that + * size in Bytes. + * \param tag_len The length of the tag to generate. + * \param tag The buffer for holding the tag. This must be a writable + * buffer of at least \p tag_len Bytes. + * + * \return \c 0 if the encryption or decryption was performed + * successfully. Note that in #MBEDTLS_GCM_DECRYPT mode, + * this does not indicate that the data is authentic. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are + * not valid or a cipher-specific error code if the encryption + * or decryption failed. + */ +int mbedtls_gcm_crypt_and_tag(mbedtls_gcm_context *ctx, + int mode, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *input, + unsigned char *output, + size_t tag_len, + unsigned char *tag); + +/** + * \brief This function performs a GCM authenticated decryption of a + * buffer. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. This must be initialized. + * \param length The length of the ciphertext to decrypt, which is also + * the length of the decrypted plaintext. + * \param iv The initialization vector. This must be a readable buffer + * of at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * \param add The buffer holding the additional data. This must be of at + * least that size in Bytes. + * \param add_len The length of the additional data. + * \param tag The buffer holding the tag to verify. This must be a + * readable buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to verify. + * \param input The buffer holding the ciphertext. If \p length is greater + * than zero, this must be a readable buffer of at least that + * size. + * \param output The buffer for holding the decrypted plaintext. If \p length + * is greater than zero, this must be a writable buffer of at + * least that size. + * + * \return \c 0 if successful and authenticated. + * \return #MBEDTLS_ERR_GCM_AUTH_FAILED if the tag does not match. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT if the lengths or pointers are + * not valid or a cipher-specific error code if the decryption + * failed. + */ +int mbedtls_gcm_auth_decrypt(mbedtls_gcm_context *ctx, + size_t length, + const unsigned char *iv, + size_t iv_len, + const unsigned char *add, + size_t add_len, + const unsigned char *tag, + size_t tag_len, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function starts a GCM encryption or decryption + * operation. + * + * \param ctx The GCM context. This must be initialized. + * \param mode The operation to perform: #MBEDTLS_GCM_ENCRYPT or + * #MBEDTLS_GCM_DECRYPT. + * \param iv The initialization vector. This must be a readable buffer of + * at least \p iv_len Bytes. + * \param iv_len The length of the IV. + * + * \return \c 0 on success. + */ +int mbedtls_gcm_starts(mbedtls_gcm_context *ctx, + int mode, + const unsigned char *iv, + size_t iv_len); + +/** + * \brief This function feeds an input buffer as associated data + * (authenticated but not encrypted data) in a GCM + * encryption or decryption operation. + * + * Call this function after mbedtls_gcm_starts() to pass + * the associated data. If the associated data is empty, + * you do not need to call this function. You may not + * call this function after calling mbedtls_cipher_update(). + * + * \param ctx The GCM context. This must have been started with + * mbedtls_gcm_starts() and must not have yet received + * any input with mbedtls_gcm_update(). + * \param add The buffer holding the additional data, or \c NULL + * if \p add_len is \c 0. + * \param add_len The length of the additional data. If \c 0, + * \p add may be \c NULL. + * + * \return \c 0 on success. + */ +int mbedtls_gcm_update_ad(mbedtls_gcm_context *ctx, + const unsigned char *add, + size_t add_len); + +/** + * \brief This function feeds an input buffer into an ongoing GCM + * encryption or decryption operation. + * + * You may call this function zero, one or more times + * to pass successive parts of the input: the plaintext to + * encrypt, or the ciphertext (not including the tag) to + * decrypt. After the last part of the input, call + * mbedtls_gcm_finish(). + * + * This function may produce output in one of the following + * ways: + * - Immediate output: the output length is always equal + * to the input length. + * - Buffered output: the output consists of a whole number + * of 16-byte blocks. If the total input length so far + * (not including associated data) is 16 \* *B* + *A* + * with *A* < 16 then the total output length is 16 \* *B*. + * + * In particular: + * - It is always correct to call this function with + * \p output_size >= \p input_length + 15. + * - If \p input_length is a multiple of 16 for all the calls + * to this function during an operation, then it is + * correct to use \p output_size = \p input_length. + * + * \note For decryption, the output buffer cannot be the same as + * input buffer. If the buffers overlap, the output buffer + * must trail at least 8 Bytes behind the input buffer. + * + * \param ctx The GCM context. This must be initialized. + * \param input The buffer holding the input data. If \p input_length + * is greater than zero, this must be a readable buffer + * of at least \p input_length bytes. + * \param input_length The length of the input data in bytes. + * \param output The buffer for the output data. If \p output_size + * is greater than zero, this must be a writable buffer of + * of at least \p output_size bytes. + * \param output_size The size of the output buffer in bytes. + * See the function description regarding the output size. + * \param output_length On success, \p *output_length contains the actual + * length of the output written in \p output. + * On failure, the content of \p *output_length is + * unspecified. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure: + * total input length too long, + * unsupported input/output buffer overlap detected, + * or \p output_size too small. + */ +int mbedtls_gcm_update(mbedtls_gcm_context *ctx, + const unsigned char *input, size_t input_length, + unsigned char *output, size_t output_size, + size_t *output_length); + +/** + * \brief This function finishes the GCM operation and generates + * the authentication tag. + * + * It wraps up the GCM stream, and generates the + * tag. The tag can have a maximum length of 16 Bytes. + * + * \param ctx The GCM context. This must be initialized. + * \param tag The buffer for holding the tag. This must be a writable + * buffer of at least \p tag_len Bytes. + * \param tag_len The length of the tag to generate. This must be at least + * four. + * \param output The buffer for the final output. + * If \p output_size is nonzero, this must be a writable + * buffer of at least \p output_size bytes. + * \param output_size The size of the \p output buffer in bytes. + * This must be large enough for the output that + * mbedtls_gcm_update() has not produced. In particular: + * - If mbedtls_gcm_update() produces immediate output, + * or if the total input size is a multiple of \c 16, + * then mbedtls_gcm_finish() never produces any output, + * so \p output_size can be \c 0. + * - \p output_size never needs to be more than \c 15. + * \param output_length On success, \p *output_length contains the actual + * length of the output written in \p output. + * On failure, the content of \p *output_length is + * unspecified. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_GCM_BAD_INPUT on failure: + * invalid value of \p tag_len, + * or \p output_size too small. + */ +int mbedtls_gcm_finish(mbedtls_gcm_context *ctx, + unsigned char *output, size_t output_size, + size_t *output_length, + unsigned char *tag, size_t tag_len); + +/** + * \brief This function clears a GCM context and the underlying + * cipher sub-context. + * + * \param ctx The GCM context to clear. If this is \c NULL, the call has + * no effect. Otherwise, this must be initialized. + */ +void mbedtls_gcm_free(mbedtls_gcm_context *ctx); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The GCM checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_gcm_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + + +#endif /* gcm.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hkdf.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hkdf.h index 699c6d9..bb86715 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hkdf.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hkdf.h @@ -1,136 +1,136 @@ -/** - * \file hkdf.h - * - * \brief This file contains the HKDF interface. - * - * The HMAC-based Extract-and-Expand Key Derivation Function (HKDF) is - * specified by RFC 5869. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_HKDF_H -#define MBEDTLS_HKDF_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/md.h" - -/** - * \name HKDF Error codes - * \{ - */ -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_HKDF_BAD_INPUT_DATA -0x5F80 -/** \} name */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief This is the HMAC-based Extract-and-Expand Key Derivation Function - * (HKDF). - * - * \param md A hash function; md.size denotes the length of the hash - * function output in bytes. - * \param salt An optional salt value (a non-secret random value); - * if the salt is not provided, a string of all zeros of - * md.size length is used as the salt. - * \param salt_len The length in bytes of the optional \p salt. - * \param ikm The input keying material. - * \param ikm_len The length in bytes of \p ikm. - * \param info An optional context and application specific information - * string. This can be a zero-length string. - * \param info_len The length of \p info in bytes. - * \param okm The output keying material of \p okm_len bytes. - * \param okm_len The length of the output keying material in bytes. This - * must be less than or equal to 255 * md.size bytes. - * - * \return 0 on success. - * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. - * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying - * MD layer. - */ -int mbedtls_hkdf(const mbedtls_md_info_t *md, const unsigned char *salt, - size_t salt_len, const unsigned char *ikm, size_t ikm_len, - const unsigned char *info, size_t info_len, - unsigned char *okm, size_t okm_len); - -/** - * \brief Take the input keying material \p ikm and extract from it a - * fixed-length pseudorandom key \p prk. - * - * \warning This function should only be used if the security of it has been - * studied and established in that particular context (eg. TLS 1.3 - * key schedule). For standard HKDF security guarantees use - * \c mbedtls_hkdf instead. - * - * \param md A hash function; md.size denotes the length of the - * hash function output in bytes. - * \param salt An optional salt value (a non-secret random value); - * if the salt is not provided, a string of all zeros - * of md.size length is used as the salt. - * \param salt_len The length in bytes of the optional \p salt. - * \param ikm The input keying material. - * \param ikm_len The length in bytes of \p ikm. - * \param[out] prk A pseudorandom key of at least md.size bytes. - * - * \return 0 on success. - * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. - * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying - * MD layer. - */ -int mbedtls_hkdf_extract(const mbedtls_md_info_t *md, - const unsigned char *salt, size_t salt_len, - const unsigned char *ikm, size_t ikm_len, - unsigned char *prk); - -/** - * \brief Expand the supplied \p prk into several additional pseudorandom - * keys, which is the output of the HKDF. - * - * \warning This function should only be used if the security of it has been - * studied and established in that particular context (eg. TLS 1.3 - * key schedule). For standard HKDF security guarantees use - * \c mbedtls_hkdf instead. - * - * \param md A hash function; md.size denotes the length of the hash - * function output in bytes. - * \param prk A pseudorandom key of at least md.size bytes. \p prk is - * usually the output from the HKDF extract step. - * \param prk_len The length in bytes of \p prk. - * \param info An optional context and application specific information - * string. This can be a zero-length string. - * \param info_len The length of \p info in bytes. - * \param okm The output keying material of \p okm_len bytes. - * \param okm_len The length of the output keying material in bytes. This - * must be less than or equal to 255 * md.size bytes. - * - * \return 0 on success. - * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. - * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying - * MD layer. - */ -int mbedtls_hkdf_expand(const mbedtls_md_info_t *md, const unsigned char *prk, - size_t prk_len, const unsigned char *info, - size_t info_len, unsigned char *okm, size_t okm_len); - -#ifdef __cplusplus -} -#endif - -#endif /* hkdf.h */ +/** + * \file hkdf.h + * + * \brief This file contains the HKDF interface. + * + * The HMAC-based Extract-and-Expand Key Derivation Function (HKDF) is + * specified by RFC 5869. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_HKDF_H +#define MBEDTLS_HKDF_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/md.h" + +/** + * \name HKDF Error codes + * \{ + */ +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_HKDF_BAD_INPUT_DATA -0x5F80 +/** \} name */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief This is the HMAC-based Extract-and-Expand Key Derivation Function + * (HKDF). + * + * \param md A hash function; md.size denotes the length of the hash + * function output in bytes. + * \param salt An optional salt value (a non-secret random value); + * if the salt is not provided, a string of all zeros of + * md.size length is used as the salt. + * \param salt_len The length in bytes of the optional \p salt. + * \param ikm The input keying material. + * \param ikm_len The length in bytes of \p ikm. + * \param info An optional context and application specific information + * string. This can be a zero-length string. + * \param info_len The length of \p info in bytes. + * \param okm The output keying material of \p okm_len bytes. + * \param okm_len The length of the output keying material in bytes. This + * must be less than or equal to 255 * md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf(const mbedtls_md_info_t *md, const unsigned char *salt, + size_t salt_len, const unsigned char *ikm, size_t ikm_len, + const unsigned char *info, size_t info_len, + unsigned char *okm, size_t okm_len); + +/** + * \brief Take the input keying material \p ikm and extract from it a + * fixed-length pseudorandom key \p prk. + * + * \warning This function should only be used if the security of it has been + * studied and established in that particular context (eg. TLS 1.3 + * key schedule). For standard HKDF security guarantees use + * \c mbedtls_hkdf instead. + * + * \param md A hash function; md.size denotes the length of the + * hash function output in bytes. + * \param salt An optional salt value (a non-secret random value); + * if the salt is not provided, a string of all zeros + * of md.size length is used as the salt. + * \param salt_len The length in bytes of the optional \p salt. + * \param ikm The input keying material. + * \param ikm_len The length in bytes of \p ikm. + * \param[out] prk A pseudorandom key of at least md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf_extract(const mbedtls_md_info_t *md, + const unsigned char *salt, size_t salt_len, + const unsigned char *ikm, size_t ikm_len, + unsigned char *prk); + +/** + * \brief Expand the supplied \p prk into several additional pseudorandom + * keys, which is the output of the HKDF. + * + * \warning This function should only be used if the security of it has been + * studied and established in that particular context (eg. TLS 1.3 + * key schedule). For standard HKDF security guarantees use + * \c mbedtls_hkdf instead. + * + * \param md A hash function; md.size denotes the length of the hash + * function output in bytes. + * \param prk A pseudorandom key of at least md.size bytes. \p prk is + * usually the output from the HKDF extract step. + * \param prk_len The length in bytes of \p prk. + * \param info An optional context and application specific information + * string. This can be a zero-length string. + * \param info_len The length of \p info in bytes. + * \param okm The output keying material of \p okm_len bytes. + * \param okm_len The length of the output keying material in bytes. This + * must be less than or equal to 255 * md.size bytes. + * + * \return 0 on success. + * \return #MBEDTLS_ERR_HKDF_BAD_INPUT_DATA when the parameters are invalid. + * \return An MBEDTLS_ERR_MD_* error for errors returned from the underlying + * MD layer. + */ +int mbedtls_hkdf_expand(const mbedtls_md_info_t *md, const unsigned char *prk, + size_t prk_len, const unsigned char *info, + size_t info_len, unsigned char *okm, size_t okm_len); + +#ifdef __cplusplus +} +#endif + +#endif /* hkdf.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hmac_drbg.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hmac_drbg.h index 2e5aa6d..f4b19f4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hmac_drbg.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/hmac_drbg.h @@ -1,446 +1,446 @@ -/** - * \file hmac_drbg.h - * - * \brief The HMAC_DRBG pseudorandom generator. - * - * This module implements the HMAC_DRBG pseudorandom generator described - * in NIST SP 800-90A: Recommendation for Random Number Generation Using - * Deterministic Random Bit Generators. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_HMAC_DRBG_H -#define MBEDTLS_HMAC_DRBG_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/md.h" - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - -/* - * Error codes - */ -/** Too many random requested in single call. */ -#define MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG -0x0003 -/** Input too large (Entropy + additional). */ -#define MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG -0x0005 -/** Read/write error in file. */ -#define MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR -0x0007 -/** The entropy source failed. */ -#define MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED -0x0009 - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -#if !defined(MBEDTLS_HMAC_DRBG_RESEED_INTERVAL) -#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ -#endif - -#if !defined(MBEDTLS_HMAC_DRBG_MAX_INPUT) -#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ -#endif - -#if !defined(MBEDTLS_HMAC_DRBG_MAX_REQUEST) -#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ -#endif - -#if !defined(MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT) -#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ -#endif - -/** \} name SECTION: Module settings */ - -#define MBEDTLS_HMAC_DRBG_PR_OFF 0 /**< No prediction resistance */ -#define MBEDTLS_HMAC_DRBG_PR_ON 1 /**< Prediction resistance enabled */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * HMAC_DRBG context. - */ -typedef struct mbedtls_hmac_drbg_context { - /* Working state: the key K is not stored explicitly, - * but is implied by the HMAC context */ - mbedtls_md_context_t MBEDTLS_PRIVATE(md_ctx); /*!< HMAC context (inc. K) */ - unsigned char MBEDTLS_PRIVATE(V)[MBEDTLS_MD_MAX_SIZE]; /*!< V in the spec */ - int MBEDTLS_PRIVATE(reseed_counter); /*!< reseed counter */ - - /* Administrative state */ - size_t MBEDTLS_PRIVATE(entropy_len); /*!< entropy bytes grabbed on each (re)seed */ - int MBEDTLS_PRIVATE(prediction_resistance); /*!< enable prediction resistance (Automatic - reseed before every random generation) */ - int MBEDTLS_PRIVATE(reseed_interval); /*!< reseed interval */ - - /* Callbacks */ - int(*MBEDTLS_PRIVATE(f_entropy))(void *, unsigned char *, size_t); /*!< entropy function */ - void *MBEDTLS_PRIVATE(p_entropy); /*!< context for the entropy function */ - -#if defined(MBEDTLS_THREADING_C) - /* Invariant: the mutex is initialized if and only if - * md_ctx->md_info != NULL. This means that the mutex is initialized - * during the initial seeding in mbedtls_hmac_drbg_seed() or - * mbedtls_hmac_drbg_seed_buf() and freed in mbedtls_ctr_drbg_free(). - * - * Note that this invariant may change without notice. Do not rely on it - * and do not access the mutex directly in application code. - */ - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); -#endif -} mbedtls_hmac_drbg_context; - -/** - * \brief HMAC_DRBG context initialization. - * - * This function makes the context ready for mbedtls_hmac_drbg_seed(), - * mbedtls_hmac_drbg_seed_buf() or mbedtls_hmac_drbg_free(). - * - * \note The reseed interval is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL - * by default. Override this value by calling - * mbedtls_hmac_drbg_set_reseed_interval(). - * - * \param ctx HMAC_DRBG context to be initialized. - */ -void mbedtls_hmac_drbg_init(mbedtls_hmac_drbg_context *ctx); - -/** - * \brief HMAC_DRBG initial seeding. - * - * Set the initial seed and set up the entropy source for future reseeds. - * - * A typical choice for the \p f_entropy and \p p_entropy parameters is - * to use the entropy module: - * - \p f_entropy is mbedtls_entropy_func(); - * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized - * with mbedtls_entropy_init() (which registers the platform's default - * entropy sources). - * - * You can provide a personalization string in addition to the - * entropy source, to make this instantiation as unique as possible. - * - * \note By default, the security strength as defined by NIST is: - * - 128 bits if \p md_info is SHA-1; - * - 192 bits if \p md_info is SHA-224; - * - 256 bits if \p md_info is SHA-256, SHA-384 or SHA-512. - * Note that SHA-256 is just as efficient as SHA-224. - * The security strength can be reduced if a smaller - * entropy length is set with - * mbedtls_hmac_drbg_set_entropy_len(). - * - * \note The default entropy length is the security strength - * (converted from bits to bytes). You can override - * it by calling mbedtls_hmac_drbg_set_entropy_len(). - * - * \note During the initial seeding, this function calls - * the entropy source to obtain a nonce - * whose length is half the entropy length. - */ -#if defined(MBEDTLS_THREADING_C) -/** - * \note When Mbed TLS is built with threading support, - * after this function returns successfully, - * it is safe to call mbedtls_hmac_drbg_random() - * from multiple threads. Other operations, including - * reseeding, are not thread-safe. - */ -#endif /* MBEDTLS_THREADING_C */ -/** - * \param ctx HMAC_DRBG context to be seeded. - * \param md_info MD algorithm to use for HMAC_DRBG. - * \param f_entropy The entropy callback, taking as arguments the - * \p p_entropy context, the buffer to fill, and the - * length of the buffer. - * \p f_entropy is always called with a length that is - * less than or equal to the entropy length. - * \param p_entropy The entropy context to pass to \p f_entropy. - * \param custom The personalization string. - * This can be \c NULL, in which case the personalization - * string is empty regardless of the value of \p len. - * \param len The length of the personalization string. - * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT - * and also at most - * #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \c entropy_len * 3 / 2 - * where \c entropy_len is the entropy length - * described above. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is - * invalid. - * \return #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough - * memory to allocate context data. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED - * if the call to \p f_entropy failed. - */ -int mbedtls_hmac_drbg_seed(mbedtls_hmac_drbg_context *ctx, - const mbedtls_md_info_t *md_info, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len); - -/** - * \brief Initialisation of simplified HMAC_DRBG (never reseeds). - * - * This function is meant for use in algorithms that need a pseudorandom - * input such as deterministic ECDSA. - */ -#if defined(MBEDTLS_THREADING_C) -/** - * \note When Mbed TLS is built with threading support, - * after this function returns successfully, - * it is safe to call mbedtls_hmac_drbg_random() - * from multiple threads. Other operations, including - * reseeding, are not thread-safe. - */ -#endif /* MBEDTLS_THREADING_C */ -/** - * \param ctx HMAC_DRBG context to be initialised. - * \param md_info MD algorithm to use for HMAC_DRBG. - * \param data Concatenation of the initial entropy string and - * the additional data. - * \param data_len Length of \p data in bytes. - * - * \return \c 0 if successful. or - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is - * invalid. - * \return #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough - * memory to allocate context data. - */ -int mbedtls_hmac_drbg_seed_buf(mbedtls_hmac_drbg_context *ctx, - const mbedtls_md_info_t *md_info, - const unsigned char *data, size_t data_len); - -/** - * \brief This function turns prediction resistance on or off. - * The default value is off. - * - * \note If enabled, entropy is gathered at the beginning of - * every call to mbedtls_hmac_drbg_random_with_add() - * or mbedtls_hmac_drbg_random(). - * Only use this if your entropy source has sufficient - * throughput. - * - * \param ctx The HMAC_DRBG context. - * \param resistance #MBEDTLS_HMAC_DRBG_PR_ON or #MBEDTLS_HMAC_DRBG_PR_OFF. - */ -void mbedtls_hmac_drbg_set_prediction_resistance(mbedtls_hmac_drbg_context *ctx, - int resistance); - -/** - * \brief This function sets the amount of entropy grabbed on each - * seed or reseed. - * - * See the documentation of mbedtls_hmac_drbg_seed() for the default value. - * - * \param ctx The HMAC_DRBG context. - * \param len The amount of entropy to grab, in bytes. - */ -void mbedtls_hmac_drbg_set_entropy_len(mbedtls_hmac_drbg_context *ctx, - size_t len); - -/** - * \brief Set the reseed interval. - * - * The reseed interval is the number of calls to mbedtls_hmac_drbg_random() - * or mbedtls_hmac_drbg_random_with_add() after which the entropy function - * is called again. - * - * The default value is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL. - * - * \param ctx The HMAC_DRBG context. - * \param interval The reseed interval. - */ -void mbedtls_hmac_drbg_set_reseed_interval(mbedtls_hmac_drbg_context *ctx, - int interval); - -/** - * \brief This function updates the state of the HMAC_DRBG context. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param ctx The HMAC_DRBG context. - * \param additional The data to update the state with. - * If this is \c NULL, there is no additional data. - * \param add_len Length of \p additional in bytes. - * Unused if \p additional is \c NULL. - * - * \return \c 0 on success, or an error from the underlying - * hash calculation. - */ -int mbedtls_hmac_drbg_update(mbedtls_hmac_drbg_context *ctx, - const unsigned char *additional, size_t add_len); - -/** - * \brief This function reseeds the HMAC_DRBG context, that is - * extracts data from the entropy source. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param ctx The HMAC_DRBG context. - * \param additional Additional data to add to the state. - * If this is \c NULL, there is no additional data - * and \p len should be \c 0. - * \param len The length of the additional data. - * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT - * and also at most - * #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \c entropy_len - * where \c entropy_len is the entropy length - * (see mbedtls_hmac_drbg_set_entropy_len()). - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED - * if a call to the entropy function failed. - */ -int mbedtls_hmac_drbg_reseed(mbedtls_hmac_drbg_context *ctx, - const unsigned char *additional, size_t len); - -/** - * \brief This function updates an HMAC_DRBG instance with additional - * data and uses it to generate random data. - * - * This function automatically reseeds if the reseed counter is exceeded - * or prediction resistance is enabled. - * - * \note This function is not thread-safe. It is not safe - * to call this function if another thread might be - * concurrently obtaining random numbers from the same - * context or updating or reseeding the same context. - * - * \param p_rng The HMAC_DRBG context. This must be a pointer to a - * #mbedtls_hmac_drbg_context structure. - * \param output The buffer to fill. - * \param output_len The length of the buffer in bytes. - * This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST. - * \param additional Additional data to update with. - * If this is \c NULL, there is no additional data - * and \p add_len should be \c 0. - * \param add_len The length of the additional data. - * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED - * if a call to the entropy source failed. - * \return #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if - * \p output_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST. - * \return #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if - * \p add_len > #MBEDTLS_HMAC_DRBG_MAX_INPUT. - */ -int mbedtls_hmac_drbg_random_with_add(void *p_rng, - unsigned char *output, size_t output_len, - const unsigned char *additional, - size_t add_len); - -/** - * \brief This function uses HMAC_DRBG to generate random data. - * - * This function automatically reseeds if the reseed counter is exceeded - * or prediction resistance is enabled. - */ -#if defined(MBEDTLS_THREADING_C) -/** - * \note When Mbed TLS is built with threading support, - * it is safe to call mbedtls_ctr_drbg_random() - * from multiple threads. Other operations, including - * reseeding, are not thread-safe. - */ -#endif /* MBEDTLS_THREADING_C */ -/** - * \param p_rng The HMAC_DRBG context. This must be a pointer to a - * #mbedtls_hmac_drbg_context structure. - * \param output The buffer to fill. - * \param out_len The length of the buffer in bytes. - * This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED - * if a call to the entropy source failed. - * \return #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if - * \p out_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST. - */ -int mbedtls_hmac_drbg_random(void *p_rng, unsigned char *output, size_t out_len); - -/** - * \brief This function resets HMAC_DRBG context to the state immediately - * after initial call of mbedtls_hmac_drbg_init(). - * - * \param ctx The HMAC_DRBG context to free. - */ -void mbedtls_hmac_drbg_free(mbedtls_hmac_drbg_context *ctx); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief This function writes a seed file. - * - * \param ctx The HMAC_DRBG context. - * \param path The name of the file. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on reseed - * failure. - */ -int mbedtls_hmac_drbg_write_seed_file(mbedtls_hmac_drbg_context *ctx, const char *path); - -/** - * \brief This function reads and updates a seed file. The seed - * is added to this instance. - * - * \param ctx The HMAC_DRBG context. - * \param path The name of the file. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error. - * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on - * reseed failure. - * \return #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if the existing - * seed file is too large. - */ -int mbedtls_hmac_drbg_update_seed_file(mbedtls_hmac_drbg_context *ctx, const char *path); -#endif /* MBEDTLS_FS_IO */ - - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief The HMAC_DRBG Checkup routine. - * - * \return \c 0 if successful. - * \return \c 1 if the test failed. - */ -int mbedtls_hmac_drbg_self_test(int verbose); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* hmac_drbg.h */ +/** + * \file hmac_drbg.h + * + * \brief The HMAC_DRBG pseudorandom generator. + * + * This module implements the HMAC_DRBG pseudorandom generator described + * in NIST SP 800-90A: Recommendation for Random Number Generation Using + * Deterministic Random Bit Generators. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_HMAC_DRBG_H +#define MBEDTLS_HMAC_DRBG_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/md.h" + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +/* + * Error codes + */ +/** Too many random requested in single call. */ +#define MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG -0x0003 +/** Input too large (Entropy + additional). */ +#define MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG -0x0005 +/** Read/write error in file. */ +#define MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR -0x0007 +/** The entropy source failed. */ +#define MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED -0x0009 + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_HMAC_DRBG_RESEED_INTERVAL) +#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +#endif + +#if !defined(MBEDTLS_HMAC_DRBG_MAX_INPUT) +#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +#endif + +#if !defined(MBEDTLS_HMAC_DRBG_MAX_REQUEST) +#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +#endif + +#if !defined(MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT) +#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ +#endif + +/** \} name SECTION: Module settings */ + +#define MBEDTLS_HMAC_DRBG_PR_OFF 0 /**< No prediction resistance */ +#define MBEDTLS_HMAC_DRBG_PR_ON 1 /**< Prediction resistance enabled */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * HMAC_DRBG context. + */ +typedef struct mbedtls_hmac_drbg_context { + /* Working state: the key K is not stored explicitly, + * but is implied by the HMAC context */ + mbedtls_md_context_t MBEDTLS_PRIVATE(md_ctx); /*!< HMAC context (inc. K) */ + unsigned char MBEDTLS_PRIVATE(V)[MBEDTLS_MD_MAX_SIZE]; /*!< V in the spec */ + int MBEDTLS_PRIVATE(reseed_counter); /*!< reseed counter */ + + /* Administrative state */ + size_t MBEDTLS_PRIVATE(entropy_len); /*!< entropy bytes grabbed on each (re)seed */ + int MBEDTLS_PRIVATE(prediction_resistance); /*!< enable prediction resistance (Automatic + reseed before every random generation) */ + int MBEDTLS_PRIVATE(reseed_interval); /*!< reseed interval */ + + /* Callbacks */ + int(*MBEDTLS_PRIVATE(f_entropy))(void *, unsigned char *, size_t); /*!< entropy function */ + void *MBEDTLS_PRIVATE(p_entropy); /*!< context for the entropy function */ + +#if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized if and only if + * md_ctx->md_info != NULL. This means that the mutex is initialized + * during the initial seeding in mbedtls_hmac_drbg_seed() or + * mbedtls_hmac_drbg_seed_buf() and freed in mbedtls_ctr_drbg_free(). + * + * Note that this invariant may change without notice. Do not rely on it + * and do not access the mutex directly in application code. + */ + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); +#endif +} mbedtls_hmac_drbg_context; + +/** + * \brief HMAC_DRBG context initialization. + * + * This function makes the context ready for mbedtls_hmac_drbg_seed(), + * mbedtls_hmac_drbg_seed_buf() or mbedtls_hmac_drbg_free(). + * + * \note The reseed interval is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL + * by default. Override this value by calling + * mbedtls_hmac_drbg_set_reseed_interval(). + * + * \param ctx HMAC_DRBG context to be initialized. + */ +void mbedtls_hmac_drbg_init(mbedtls_hmac_drbg_context *ctx); + +/** + * \brief HMAC_DRBG initial seeding. + * + * Set the initial seed and set up the entropy source for future reseeds. + * + * A typical choice for the \p f_entropy and \p p_entropy parameters is + * to use the entropy module: + * - \p f_entropy is mbedtls_entropy_func(); + * - \p p_entropy is an instance of ::mbedtls_entropy_context initialized + * with mbedtls_entropy_init() (which registers the platform's default + * entropy sources). + * + * You can provide a personalization string in addition to the + * entropy source, to make this instantiation as unique as possible. + * + * \note By default, the security strength as defined by NIST is: + * - 128 bits if \p md_info is SHA-1; + * - 192 bits if \p md_info is SHA-224; + * - 256 bits if \p md_info is SHA-256, SHA-384 or SHA-512. + * Note that SHA-256 is just as efficient as SHA-224. + * The security strength can be reduced if a smaller + * entropy length is set with + * mbedtls_hmac_drbg_set_entropy_len(). + * + * \note The default entropy length is the security strength + * (converted from bits to bytes). You can override + * it by calling mbedtls_hmac_drbg_set_entropy_len(). + * + * \note During the initial seeding, this function calls + * the entropy source to obtain a nonce + * whose length is half the entropy length. + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_hmac_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param ctx HMAC_DRBG context to be seeded. + * \param md_info MD algorithm to use for HMAC_DRBG. + * \param f_entropy The entropy callback, taking as arguments the + * \p p_entropy context, the buffer to fill, and the + * length of the buffer. + * \p f_entropy is always called with a length that is + * less than or equal to the entropy length. + * \param p_entropy The entropy context to pass to \p f_entropy. + * \param custom The personalization string. + * This can be \c NULL, in which case the personalization + * string is empty regardless of the value of \p len. + * \param len The length of the personalization string. + * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT + * and also at most + * #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \c entropy_len * 3 / 2 + * where \c entropy_len is the entropy length + * described above. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is + * invalid. + * \return #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough + * memory to allocate context data. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED + * if the call to \p f_entropy failed. + */ +int mbedtls_hmac_drbg_seed(mbedtls_hmac_drbg_context *ctx, + const mbedtls_md_info_t *md_info, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len); + +/** + * \brief Initialisation of simplified HMAC_DRBG (never reseeds). + * + * This function is meant for use in algorithms that need a pseudorandom + * input such as deterministic ECDSA. + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * after this function returns successfully, + * it is safe to call mbedtls_hmac_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param ctx HMAC_DRBG context to be initialised. + * \param md_info MD algorithm to use for HMAC_DRBG. + * \param data Concatenation of the initial entropy string and + * the additional data. + * \param data_len Length of \p data in bytes. + * + * \return \c 0 if successful. or + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info is + * invalid. + * \return #MBEDTLS_ERR_MD_ALLOC_FAILED if there was not enough + * memory to allocate context data. + */ +int mbedtls_hmac_drbg_seed_buf(mbedtls_hmac_drbg_context *ctx, + const mbedtls_md_info_t *md_info, + const unsigned char *data, size_t data_len); + +/** + * \brief This function turns prediction resistance on or off. + * The default value is off. + * + * \note If enabled, entropy is gathered at the beginning of + * every call to mbedtls_hmac_drbg_random_with_add() + * or mbedtls_hmac_drbg_random(). + * Only use this if your entropy source has sufficient + * throughput. + * + * \param ctx The HMAC_DRBG context. + * \param resistance #MBEDTLS_HMAC_DRBG_PR_ON or #MBEDTLS_HMAC_DRBG_PR_OFF. + */ +void mbedtls_hmac_drbg_set_prediction_resistance(mbedtls_hmac_drbg_context *ctx, + int resistance); + +/** + * \brief This function sets the amount of entropy grabbed on each + * seed or reseed. + * + * See the documentation of mbedtls_hmac_drbg_seed() for the default value. + * + * \param ctx The HMAC_DRBG context. + * \param len The amount of entropy to grab, in bytes. + */ +void mbedtls_hmac_drbg_set_entropy_len(mbedtls_hmac_drbg_context *ctx, + size_t len); + +/** + * \brief Set the reseed interval. + * + * The reseed interval is the number of calls to mbedtls_hmac_drbg_random() + * or mbedtls_hmac_drbg_random_with_add() after which the entropy function + * is called again. + * + * The default value is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL. + * + * \param ctx The HMAC_DRBG context. + * \param interval The reseed interval. + */ +void mbedtls_hmac_drbg_set_reseed_interval(mbedtls_hmac_drbg_context *ctx, + int interval); + +/** + * \brief This function updates the state of the HMAC_DRBG context. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The HMAC_DRBG context. + * \param additional The data to update the state with. + * If this is \c NULL, there is no additional data. + * \param add_len Length of \p additional in bytes. + * Unused if \p additional is \c NULL. + * + * \return \c 0 on success, or an error from the underlying + * hash calculation. + */ +int mbedtls_hmac_drbg_update(mbedtls_hmac_drbg_context *ctx, + const unsigned char *additional, size_t add_len); + +/** + * \brief This function reseeds the HMAC_DRBG context, that is + * extracts data from the entropy source. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param ctx The HMAC_DRBG context. + * \param additional Additional data to add to the state. + * If this is \c NULL, there is no additional data + * and \p len should be \c 0. + * \param len The length of the additional data. + * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT + * and also at most + * #MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT - \c entropy_len + * where \c entropy_len is the entropy length + * (see mbedtls_hmac_drbg_set_entropy_len()). + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED + * if a call to the entropy function failed. + */ +int mbedtls_hmac_drbg_reseed(mbedtls_hmac_drbg_context *ctx, + const unsigned char *additional, size_t len); + +/** + * \brief This function updates an HMAC_DRBG instance with additional + * data and uses it to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + * + * \note This function is not thread-safe. It is not safe + * to call this function if another thread might be + * concurrently obtaining random numbers from the same + * context or updating or reseeding the same context. + * + * \param p_rng The HMAC_DRBG context. This must be a pointer to a + * #mbedtls_hmac_drbg_context structure. + * \param output The buffer to fill. + * \param output_len The length of the buffer in bytes. + * This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST. + * \param additional Additional data to update with. + * If this is \c NULL, there is no additional data + * and \p add_len should be \c 0. + * \param add_len The length of the additional data. + * This must be at most #MBEDTLS_HMAC_DRBG_MAX_INPUT. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED + * if a call to the entropy source failed. + * \return #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if + * \p output_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST. + * \return #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if + * \p add_len > #MBEDTLS_HMAC_DRBG_MAX_INPUT. + */ +int mbedtls_hmac_drbg_random_with_add(void *p_rng, + unsigned char *output, size_t output_len, + const unsigned char *additional, + size_t add_len); + +/** + * \brief This function uses HMAC_DRBG to generate random data. + * + * This function automatically reseeds if the reseed counter is exceeded + * or prediction resistance is enabled. + */ +#if defined(MBEDTLS_THREADING_C) +/** + * \note When Mbed TLS is built with threading support, + * it is safe to call mbedtls_ctr_drbg_random() + * from multiple threads. Other operations, including + * reseeding, are not thread-safe. + */ +#endif /* MBEDTLS_THREADING_C */ +/** + * \param p_rng The HMAC_DRBG context. This must be a pointer to a + * #mbedtls_hmac_drbg_context structure. + * \param output The buffer to fill. + * \param out_len The length of the buffer in bytes. + * This must be at most #MBEDTLS_HMAC_DRBG_MAX_REQUEST. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED + * if a call to the entropy source failed. + * \return #MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG if + * \p out_len > #MBEDTLS_HMAC_DRBG_MAX_REQUEST. + */ +int mbedtls_hmac_drbg_random(void *p_rng, unsigned char *output, size_t out_len); + +/** + * \brief This function resets HMAC_DRBG context to the state immediately + * after initial call of mbedtls_hmac_drbg_init(). + * + * \param ctx The HMAC_DRBG context to free. + */ +void mbedtls_hmac_drbg_free(mbedtls_hmac_drbg_context *ctx); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function writes a seed file. + * + * \param ctx The HMAC_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on reseed + * failure. + */ +int mbedtls_hmac_drbg_write_seed_file(mbedtls_hmac_drbg_context *ctx, const char *path); + +/** + * \brief This function reads and updates a seed file. The seed + * is added to this instance. + * + * \param ctx The HMAC_DRBG context. + * \param path The name of the file. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR on file error. + * \return #MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED on + * reseed failure. + * \return #MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG if the existing + * seed file is too large. + */ +int mbedtls_hmac_drbg_update_seed_file(mbedtls_hmac_drbg_context *ctx, const char *path); +#endif /* MBEDTLS_FS_IO */ + + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief The HMAC_DRBG Checkup routine. + * + * \return \c 0 if successful. + * \return \c 1 if the test failed. + */ +int mbedtls_hmac_drbg_self_test(int verbose); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* hmac_drbg.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/lms.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/lms.h index 5c8df42..edbbd2f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/lms.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/lms.h @@ -1,452 +1,452 @@ -/** - * \file lms.h - * - * \brief This file provides an API for the LMS post-quantum-safe stateful-hash - public-key signature scheme as defined in RFC8554 and NIST.SP.200-208. - * This implementation currently only supports a single parameter set - * MBEDTLS_LMS_SHA256_M32_H10 in order to reduce complexity. This is one - * of the signature schemes recommended by the IETF draft SUIT standard - * for IOT firmware upgrades (RFC9019). - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_LMS_H -#define MBEDTLS_LMS_H - -#include -#include - -#include "mbedtls/private_access.h" -#include "mbedtls/build_info.h" - -#define MBEDTLS_ERR_LMS_BAD_INPUT_DATA -0x0011 /**< Bad data has been input to an LMS function */ -#define MBEDTLS_ERR_LMS_OUT_OF_PRIVATE_KEYS -0x0013 /**< Specified LMS key has utilised all of its private keys */ -#define MBEDTLS_ERR_LMS_VERIFY_FAILED -0x0015 /**< LMS signature verification failed */ -#define MBEDTLS_ERR_LMS_ALLOC_FAILED -0x0017 /**< LMS failed to allocate space for a private key */ -#define MBEDTLS_ERR_LMS_BUFFER_TOO_SMALL -0x0019 /**< Input/output buffer is too small to contain requited data */ - -/* Currently only defined for SHA256, 32 is the max hash output size */ -#define MBEDTLS_LMOTS_N_HASH_LEN_MAX (32u) -#define MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT_MAX (34u) -#define MBEDTLS_LMOTS_N_HASH_LEN(type) ((type) == MBEDTLS_LMOTS_SHA256_N32_W8 ? 32u : 0) -#define MBEDTLS_LMOTS_I_KEY_ID_LEN (16u) -#define MBEDTLS_LMOTS_Q_LEAF_ID_LEN (4u) -#define MBEDTLS_LMOTS_TYPE_LEN (4u) -#define MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT(type) ((type) == MBEDTLS_LMOTS_SHA256_N32_W8 ? 34u : 0) -#define MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type) (MBEDTLS_LMOTS_N_HASH_LEN(type)) - -#define MBEDTLS_LMOTS_SIG_LEN(type) (MBEDTLS_LMOTS_TYPE_LEN + \ - MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type) + \ - (MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT(type) * \ - MBEDTLS_LMOTS_N_HASH_LEN(type))) - - -#define MBEDTLS_LMS_TYPE_LEN (4) -#define MBEDTLS_LMS_H_TREE_HEIGHT(type) ((type) == MBEDTLS_LMS_SHA256_M32_H10 ? 10u : 0) - -/* The length of a hash output, Currently only implemented for SHA256. - * Max is 32 bytes. - */ -#define MBEDTLS_LMS_M_NODE_BYTES(type) ((type) == MBEDTLS_LMS_SHA256_M32_H10 ? 32 : 0) -#define MBEDTLS_LMS_M_NODE_BYTES_MAX 32 - -#define MBEDTLS_LMS_SIG_LEN(type, otstype) (MBEDTLS_LMOTS_Q_LEAF_ID_LEN + \ - MBEDTLS_LMOTS_SIG_LEN(otstype) + \ - MBEDTLS_LMS_TYPE_LEN + \ - (MBEDTLS_LMS_H_TREE_HEIGHT(type) * \ - MBEDTLS_LMS_M_NODE_BYTES(type))) - -#define MBEDTLS_LMS_PUBLIC_KEY_LEN(type) (MBEDTLS_LMS_TYPE_LEN + \ - MBEDTLS_LMOTS_TYPE_LEN + \ - MBEDTLS_LMOTS_I_KEY_ID_LEN + \ - MBEDTLS_LMS_M_NODE_BYTES(type)) - - -#ifdef __cplusplus -extern "C" { -#endif - -/** The Identifier of the LMS parameter set, as per - * https://www.iana.org/assignments/leighton-micali-signatures/leighton-micali-signatures.xhtml - * We are only implementing a subset of the types, particularly H10, for the sake of simplicity. - */ -typedef enum { - MBEDTLS_LMS_SHA256_M32_H10 = 0x6, -} mbedtls_lms_algorithm_type_t; - -/** The Identifier of the LMOTS parameter set, as per - * https://www.iana.org/assignments/leighton-micali-signatures/leighton-micali-signatures.xhtml. - * We are only implementing a subset of the types, particularly N32_W8, for the sake of simplicity. - */ -typedef enum { - MBEDTLS_LMOTS_SHA256_N32_W8 = 4 -} mbedtls_lmots_algorithm_type_t; - -/** LMOTS parameters structure. - * - * This contains the metadata associated with an LMOTS key, detailing the - * algorithm type, the key ID, and the leaf identifier should be key be part of - * a LMS key. - */ -typedef struct { - unsigned char MBEDTLS_PRIVATE(I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN]); /*!< The key - identifier. */ - unsigned char MBEDTLS_PRIVATE(q_leaf_identifier[MBEDTLS_LMOTS_Q_LEAF_ID_LEN]); /*!< Which - leaf of the LMS key this is. - 0 if the key is not part of an LMS key. */ - mbedtls_lmots_algorithm_type_t MBEDTLS_PRIVATE(type); /*!< The LM-OTS key type identifier as - per IANA. Only SHA256_N32_W8 is - currently supported. */ -} mbedtls_lmots_parameters_t; - -/** LMOTS public context structure. - * - * A LMOTS public key is a hash output, and the applicable parameter set. - * - * The context must be initialized before it is used. A public key must either - * be imported or generated from a private context. - * - * \dot - * digraph lmots_public_t { - * UNINITIALIZED -> INIT [label="init"]; - * HAVE_PUBLIC_KEY -> INIT [label="free"]; - * INIT -> HAVE_PUBLIC_KEY [label="import_public_key"]; - * INIT -> HAVE_PUBLIC_KEY [label="calculate_public_key from private key"]; - * HAVE_PUBLIC_KEY -> HAVE_PUBLIC_KEY [label="export_public_key"]; - * } - * \enddot - */ -typedef struct { - mbedtls_lmots_parameters_t MBEDTLS_PRIVATE(params); - unsigned char MBEDTLS_PRIVATE(public_key)[MBEDTLS_LMOTS_N_HASH_LEN_MAX]; - unsigned char MBEDTLS_PRIVATE(have_public_key); /*!< Whether the context contains a public key. - Boolean values only. */ -} mbedtls_lmots_public_t; - -#if defined(MBEDTLS_LMS_PRIVATE) -/** LMOTS private context structure. - * - * A LMOTS private key is one hash output for each of digit of the digest + - * checksum, and the applicable parameter set. - * - * The context must be initialized before it is used. A public key must either - * be imported or generated from a private context. - * - * \dot - * digraph lmots_public_t { - * UNINITIALIZED -> INIT [label="init"]; - * HAVE_PRIVATE_KEY -> INIT [label="free"]; - * INIT -> HAVE_PRIVATE_KEY [label="generate_private_key"]; - * HAVE_PRIVATE_KEY -> INIT [label="sign"]; - * } - * \enddot - */ -typedef struct { - mbedtls_lmots_parameters_t MBEDTLS_PRIVATE(params); - unsigned char MBEDTLS_PRIVATE(private_key)[MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT_MAX][ - MBEDTLS_LMOTS_N_HASH_LEN_MAX]; - unsigned char MBEDTLS_PRIVATE(have_private_key); /*!< Whether the context contains a private key. - Boolean values only. */ -} mbedtls_lmots_private_t; -#endif /* defined(MBEDTLS_LMS_PRIVATE) */ - - -/** LMS parameters structure. - * - * This contains the metadata associated with an LMS key, detailing the - * algorithm type, the type of the underlying OTS algorithm, and the key ID. - */ -typedef struct { - unsigned char MBEDTLS_PRIVATE(I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN]); /*!< The key - identifier. */ - mbedtls_lmots_algorithm_type_t MBEDTLS_PRIVATE(otstype); /*!< The LM-OTS key type identifier as - per IANA. Only SHA256_N32_W8 is - currently supported. */ - mbedtls_lms_algorithm_type_t MBEDTLS_PRIVATE(type); /*!< The LMS key type identifier as per - IANA. Only SHA256_M32_H10 is currently - supported. */ -} mbedtls_lms_parameters_t; - -/** LMS public context structure. - * - * A LMS public key is the hash output that is the root of the Merkle tree, and - * the applicable parameter set - * - * The context must be initialized before it is used. A public key must either - * be imported or generated from a private context. - * - * \dot - * digraph lms_public_t { - * UNINITIALIZED -> INIT [label="init"]; - * HAVE_PUBLIC_KEY -> INIT [label="free"]; - * INIT -> HAVE_PUBLIC_KEY [label="import_public_key"]; - * INIT -> HAVE_PUBLIC_KEY [label="calculate_public_key from private key"]; - * HAVE_PUBLIC_KEY -> HAVE_PUBLIC_KEY [label="export_public_key"]; - * } - * \enddot - */ -typedef struct { - mbedtls_lms_parameters_t MBEDTLS_PRIVATE(params); - unsigned char MBEDTLS_PRIVATE(T_1_pub_key)[MBEDTLS_LMS_M_NODE_BYTES_MAX]; /*!< The public key, in - the form of the Merkle tree root node. */ - unsigned char MBEDTLS_PRIVATE(have_public_key); /*!< Whether the context contains a public key. - Boolean values only. */ -} mbedtls_lms_public_t; - - -#if defined(MBEDTLS_LMS_PRIVATE) -/** LMS private context structure. - * - * A LMS private key is a set of LMOTS private keys, an index to the next usable - * key, and the applicable parameter set. - * - * The context must be initialized before it is used. A public key must either - * be imported or generated from a private context. - * - * \dot - * digraph lms_public_t { - * UNINITIALIZED -> INIT [label="init"]; - * HAVE_PRIVATE_KEY -> INIT [label="free"]; - * INIT -> HAVE_PRIVATE_KEY [label="generate_private_key"]; - * } - * \enddot - */ -typedef struct { - mbedtls_lms_parameters_t MBEDTLS_PRIVATE(params); - uint32_t MBEDTLS_PRIVATE(q_next_usable_key); /*!< The index of the next OTS key that has not - been used. */ - mbedtls_lmots_private_t *MBEDTLS_PRIVATE(ots_private_keys); /*!< The private key material. One OTS key - for each leaf node in the Merkle tree. NULL - when have_private_key is 0 and non-NULL otherwise. - is 2^MBEDTLS_LMS_H_TREE_HEIGHT(type) in length. */ - mbedtls_lmots_public_t *MBEDTLS_PRIVATE(ots_public_keys); /*!< The OTS key public keys, used to - build the Merkle tree. NULL - when have_private_key is 0 and - non-NULL otherwise. - Is 2^MBEDTLS_LMS_H_TREE_HEIGHT(type) - in length. */ - unsigned char MBEDTLS_PRIVATE(have_private_key); /*!< Whether the context contains a private key. - Boolean values only. */ -} mbedtls_lms_private_t; -#endif /* defined(MBEDTLS_LMS_PRIVATE) */ - -/** - * \brief This function initializes an LMS public context - * - * \param ctx The uninitialized LMS context that will then be - * initialized. - */ -void mbedtls_lms_public_init(mbedtls_lms_public_t *ctx); - -/** - * \brief This function uninitializes an LMS public context - * - * \param ctx The initialized LMS context that will then be - * uninitialized. - */ -void mbedtls_lms_public_free(mbedtls_lms_public_t *ctx); - -/** - * \brief This function imports an LMS public key into a - * public LMS context. - * - * \note Before this function is called, the context must - * have been initialized. - * - * \note See IETF RFC8554 for details of the encoding of - * this public key. - * - * \param ctx The initialized LMS context store the key in. - * \param key The buffer from which the key will be read. - * #MBEDTLS_LMS_PUBLIC_KEY_LEN bytes will be read from - * this. - * \param key_size The size of the key being imported. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_import_public_key(mbedtls_lms_public_t *ctx, - const unsigned char *key, size_t key_size); - -/** - * \brief This function exports an LMS public key from a - * LMS public context that already contains a public - * key. - * - * \note Before this function is called, the context must - * have been initialized and the context must contain - * a public key. - * - * \note See IETF RFC8554 for details of the encoding of - * this public key. - * - * \param ctx The initialized LMS public context that contains - * the public key. - * \param key The buffer into which the key will be output. Must - * be at least #MBEDTLS_LMS_PUBLIC_KEY_LEN in size. - * \param key_size The size of the key buffer. - * \param key_len If not NULL, will be written with the size of the - * key. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_export_public_key(const mbedtls_lms_public_t *ctx, - unsigned char *key, size_t key_size, - size_t *key_len); - -/** - * \brief This function verifies a LMS signature, using a - * LMS context that contains a public key. - * - * \note Before this function is called, the context must - * have been initialized and must contain a public key - * (either by import or generation). - * - * \param ctx The initialized LMS public context from which the - * public key will be read. - * \param msg The buffer from which the message will be read. - * \param msg_size The size of the message that will be read. - * \param sig The buf from which the signature will be read. - * #MBEDTLS_LMS_SIG_LEN bytes will be read from - * this. - * \param sig_size The size of the signature to be verified. - * - * \return \c 0 on successful verification. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_verify(const mbedtls_lms_public_t *ctx, - const unsigned char *msg, size_t msg_size, - const unsigned char *sig, size_t sig_size); - -#if defined(MBEDTLS_LMS_PRIVATE) -/** - * \brief This function initializes an LMS private context - * - * \param ctx The uninitialized LMS private context that will - * then be initialized. */ -void mbedtls_lms_private_init(mbedtls_lms_private_t *ctx); - -/** - * \brief This function uninitializes an LMS private context - * - * \param ctx The initialized LMS private context that will then - * be uninitialized. - */ -void mbedtls_lms_private_free(mbedtls_lms_private_t *ctx); - -/** - * \brief This function generates an LMS private key, and - * stores in into an LMS private context. - * - * \warning This function is **not intended for use in - * production**, due to as-yet unsolved problems with - * handling stateful keys. The API for this function - * may change considerably in future versions. - * - * \note The seed must have at least 256 bits of entropy. - * - * \param ctx The initialized LMOTS context to generate the key - * into. - * \param type The LMS parameter set identifier. - * \param otstype The LMOTS parameter set identifier. - * \param f_rng The RNG function to be used to generate the key ID. - * \param p_rng The RNG context to be passed to f_rng - * \param seed The seed used to deterministically generate the - * key. - * \param seed_size The length of the seed. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_generate_private_key(mbedtls_lms_private_t *ctx, - mbedtls_lms_algorithm_type_t type, - mbedtls_lmots_algorithm_type_t otstype, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, const unsigned char *seed, - size_t seed_size); - -/** - * \brief This function calculates an LMS public key from a - * LMS context that already contains a private key. - * - * \note Before this function is called, the context must - * have been initialized and the context must contain - * a private key. - * - * \param ctx The initialized LMS public context to calculate the key - * from and store it into. - * - * \param priv_ctx The LMS private context to read the private key - * from. This must have been initialized and contain a - * private key. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_calculate_public_key(mbedtls_lms_public_t *ctx, - const mbedtls_lms_private_t *priv_ctx); - -/** - * \brief This function creates a LMS signature, using a - * LMS context that contains unused private keys. - * - * \warning This function is **not intended for use in - * production**, due to as-yet unsolved problems with - * handling stateful keys. The API for this function - * may change considerably in future versions. - * - * \note Before this function is called, the context must - * have been initialized and must contain a private - * key. - * - * \note Each of the LMOTS private keys inside a LMS private - * key can only be used once. If they are reused, then - * attackers may be able to forge signatures with that - * key. This is all handled transparently, but it is - * important to not perform copy operations on LMS - * contexts that contain private key material. - * - * \param ctx The initialized LMS private context from which the - * private key will be read. - * \param f_rng The RNG function to be used for signature - * generation. - * \param p_rng The RNG context to be passed to f_rng - * \param msg The buffer from which the message will be read. - * \param msg_size The size of the message that will be read. - * \param sig The buf into which the signature will be stored. - * Must be at least #MBEDTLS_LMS_SIG_LEN in size. - * \param sig_size The size of the buffer the signature will be - * written into. - * \param sig_len If not NULL, will be written with the size of the - * signature. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lms_sign(mbedtls_lms_private_t *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, const unsigned char *msg, - unsigned int msg_size, unsigned char *sig, size_t sig_size, - size_t *sig_len); -#endif /* defined(MBEDTLS_LMS_PRIVATE) */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_LMS_H */ +/** + * \file lms.h + * + * \brief This file provides an API for the LMS post-quantum-safe stateful-hash + public-key signature scheme as defined in RFC8554 and NIST.SP.200-208. + * This implementation currently only supports a single parameter set + * MBEDTLS_LMS_SHA256_M32_H10 in order to reduce complexity. This is one + * of the signature schemes recommended by the IETF draft SUIT standard + * for IOT firmware upgrades (RFC9019). + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_LMS_H +#define MBEDTLS_LMS_H + +#include +#include + +#include "mbedtls/private_access.h" +#include "mbedtls/build_info.h" + +#define MBEDTLS_ERR_LMS_BAD_INPUT_DATA -0x0011 /**< Bad data has been input to an LMS function */ +#define MBEDTLS_ERR_LMS_OUT_OF_PRIVATE_KEYS -0x0013 /**< Specified LMS key has utilised all of its private keys */ +#define MBEDTLS_ERR_LMS_VERIFY_FAILED -0x0015 /**< LMS signature verification failed */ +#define MBEDTLS_ERR_LMS_ALLOC_FAILED -0x0017 /**< LMS failed to allocate space for a private key */ +#define MBEDTLS_ERR_LMS_BUFFER_TOO_SMALL -0x0019 /**< Input/output buffer is too small to contain requited data */ + +/* Currently only defined for SHA256, 32 is the max hash output size */ +#define MBEDTLS_LMOTS_N_HASH_LEN_MAX (32u) +#define MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT_MAX (34u) +#define MBEDTLS_LMOTS_N_HASH_LEN(type) ((type) == MBEDTLS_LMOTS_SHA256_N32_W8 ? 32u : 0) +#define MBEDTLS_LMOTS_I_KEY_ID_LEN (16u) +#define MBEDTLS_LMOTS_Q_LEAF_ID_LEN (4u) +#define MBEDTLS_LMOTS_TYPE_LEN (4u) +#define MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT(type) ((type) == MBEDTLS_LMOTS_SHA256_N32_W8 ? 34u : 0) +#define MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type) (MBEDTLS_LMOTS_N_HASH_LEN(type)) + +#define MBEDTLS_LMOTS_SIG_LEN(type) (MBEDTLS_LMOTS_TYPE_LEN + \ + MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type) + \ + (MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT(type) * \ + MBEDTLS_LMOTS_N_HASH_LEN(type))) + + +#define MBEDTLS_LMS_TYPE_LEN (4) +#define MBEDTLS_LMS_H_TREE_HEIGHT(type) ((type) == MBEDTLS_LMS_SHA256_M32_H10 ? 10u : 0) + +/* The length of a hash output, Currently only implemented for SHA256. + * Max is 32 bytes. + */ +#define MBEDTLS_LMS_M_NODE_BYTES(type) ((type) == MBEDTLS_LMS_SHA256_M32_H10 ? 32 : 0) +#define MBEDTLS_LMS_M_NODE_BYTES_MAX 32 + +#define MBEDTLS_LMS_SIG_LEN(type, otstype) (MBEDTLS_LMOTS_Q_LEAF_ID_LEN + \ + MBEDTLS_LMOTS_SIG_LEN(otstype) + \ + MBEDTLS_LMS_TYPE_LEN + \ + (MBEDTLS_LMS_H_TREE_HEIGHT(type) * \ + MBEDTLS_LMS_M_NODE_BYTES(type))) + +#define MBEDTLS_LMS_PUBLIC_KEY_LEN(type) (MBEDTLS_LMS_TYPE_LEN + \ + MBEDTLS_LMOTS_TYPE_LEN + \ + MBEDTLS_LMOTS_I_KEY_ID_LEN + \ + MBEDTLS_LMS_M_NODE_BYTES(type)) + + +#ifdef __cplusplus +extern "C" { +#endif + +/** The Identifier of the LMS parameter set, as per + * https://www.iana.org/assignments/leighton-micali-signatures/leighton-micali-signatures.xhtml + * We are only implementing a subset of the types, particularly H10, for the sake of simplicity. + */ +typedef enum { + MBEDTLS_LMS_SHA256_M32_H10 = 0x6, +} mbedtls_lms_algorithm_type_t; + +/** The Identifier of the LMOTS parameter set, as per + * https://www.iana.org/assignments/leighton-micali-signatures/leighton-micali-signatures.xhtml. + * We are only implementing a subset of the types, particularly N32_W8, for the sake of simplicity. + */ +typedef enum { + MBEDTLS_LMOTS_SHA256_N32_W8 = 4 +} mbedtls_lmots_algorithm_type_t; + +/** LMOTS parameters structure. + * + * This contains the metadata associated with an LMOTS key, detailing the + * algorithm type, the key ID, and the leaf identifier should be key be part of + * a LMS key. + */ +typedef struct { + unsigned char MBEDTLS_PRIVATE(I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN]); /*!< The key + identifier. */ + unsigned char MBEDTLS_PRIVATE(q_leaf_identifier[MBEDTLS_LMOTS_Q_LEAF_ID_LEN]); /*!< Which + leaf of the LMS key this is. + 0 if the key is not part of an LMS key. */ + mbedtls_lmots_algorithm_type_t MBEDTLS_PRIVATE(type); /*!< The LM-OTS key type identifier as + per IANA. Only SHA256_N32_W8 is + currently supported. */ +} mbedtls_lmots_parameters_t; + +/** LMOTS public context structure. + * + * A LMOTS public key is a hash output, and the applicable parameter set. + * + * The context must be initialized before it is used. A public key must either + * be imported or generated from a private context. + * + * \dot + * digraph lmots_public_t { + * UNINITIALIZED -> INIT [label="init"]; + * HAVE_PUBLIC_KEY -> INIT [label="free"]; + * INIT -> HAVE_PUBLIC_KEY [label="import_public_key"]; + * INIT -> HAVE_PUBLIC_KEY [label="calculate_public_key from private key"]; + * HAVE_PUBLIC_KEY -> HAVE_PUBLIC_KEY [label="export_public_key"]; + * } + * \enddot + */ +typedef struct { + mbedtls_lmots_parameters_t MBEDTLS_PRIVATE(params); + unsigned char MBEDTLS_PRIVATE(public_key)[MBEDTLS_LMOTS_N_HASH_LEN_MAX]; + unsigned char MBEDTLS_PRIVATE(have_public_key); /*!< Whether the context contains a public key. + Boolean values only. */ +} mbedtls_lmots_public_t; + +#if defined(MBEDTLS_LMS_PRIVATE) +/** LMOTS private context structure. + * + * A LMOTS private key is one hash output for each of digit of the digest + + * checksum, and the applicable parameter set. + * + * The context must be initialized before it is used. A public key must either + * be imported or generated from a private context. + * + * \dot + * digraph lmots_public_t { + * UNINITIALIZED -> INIT [label="init"]; + * HAVE_PRIVATE_KEY -> INIT [label="free"]; + * INIT -> HAVE_PRIVATE_KEY [label="generate_private_key"]; + * HAVE_PRIVATE_KEY -> INIT [label="sign"]; + * } + * \enddot + */ +typedef struct { + mbedtls_lmots_parameters_t MBEDTLS_PRIVATE(params); + unsigned char MBEDTLS_PRIVATE(private_key)[MBEDTLS_LMOTS_P_SIG_DIGIT_COUNT_MAX][ + MBEDTLS_LMOTS_N_HASH_LEN_MAX]; + unsigned char MBEDTLS_PRIVATE(have_private_key); /*!< Whether the context contains a private key. + Boolean values only. */ +} mbedtls_lmots_private_t; +#endif /* defined(MBEDTLS_LMS_PRIVATE) */ + + +/** LMS parameters structure. + * + * This contains the metadata associated with an LMS key, detailing the + * algorithm type, the type of the underlying OTS algorithm, and the key ID. + */ +typedef struct { + unsigned char MBEDTLS_PRIVATE(I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN]); /*!< The key + identifier. */ + mbedtls_lmots_algorithm_type_t MBEDTLS_PRIVATE(otstype); /*!< The LM-OTS key type identifier as + per IANA. Only SHA256_N32_W8 is + currently supported. */ + mbedtls_lms_algorithm_type_t MBEDTLS_PRIVATE(type); /*!< The LMS key type identifier as per + IANA. Only SHA256_M32_H10 is currently + supported. */ +} mbedtls_lms_parameters_t; + +/** LMS public context structure. + * + * A LMS public key is the hash output that is the root of the Merkle tree, and + * the applicable parameter set + * + * The context must be initialized before it is used. A public key must either + * be imported or generated from a private context. + * + * \dot + * digraph lms_public_t { + * UNINITIALIZED -> INIT [label="init"]; + * HAVE_PUBLIC_KEY -> INIT [label="free"]; + * INIT -> HAVE_PUBLIC_KEY [label="import_public_key"]; + * INIT -> HAVE_PUBLIC_KEY [label="calculate_public_key from private key"]; + * HAVE_PUBLIC_KEY -> HAVE_PUBLIC_KEY [label="export_public_key"]; + * } + * \enddot + */ +typedef struct { + mbedtls_lms_parameters_t MBEDTLS_PRIVATE(params); + unsigned char MBEDTLS_PRIVATE(T_1_pub_key)[MBEDTLS_LMS_M_NODE_BYTES_MAX]; /*!< The public key, in + the form of the Merkle tree root node. */ + unsigned char MBEDTLS_PRIVATE(have_public_key); /*!< Whether the context contains a public key. + Boolean values only. */ +} mbedtls_lms_public_t; + + +#if defined(MBEDTLS_LMS_PRIVATE) +/** LMS private context structure. + * + * A LMS private key is a set of LMOTS private keys, an index to the next usable + * key, and the applicable parameter set. + * + * The context must be initialized before it is used. A public key must either + * be imported or generated from a private context. + * + * \dot + * digraph lms_public_t { + * UNINITIALIZED -> INIT [label="init"]; + * HAVE_PRIVATE_KEY -> INIT [label="free"]; + * INIT -> HAVE_PRIVATE_KEY [label="generate_private_key"]; + * } + * \enddot + */ +typedef struct { + mbedtls_lms_parameters_t MBEDTLS_PRIVATE(params); + uint32_t MBEDTLS_PRIVATE(q_next_usable_key); /*!< The index of the next OTS key that has not + been used. */ + mbedtls_lmots_private_t *MBEDTLS_PRIVATE(ots_private_keys); /*!< The private key material. One OTS key + for each leaf node in the Merkle tree. NULL + when have_private_key is 0 and non-NULL otherwise. + is 2^MBEDTLS_LMS_H_TREE_HEIGHT(type) in length. */ + mbedtls_lmots_public_t *MBEDTLS_PRIVATE(ots_public_keys); /*!< The OTS key public keys, used to + build the Merkle tree. NULL + when have_private_key is 0 and + non-NULL otherwise. + Is 2^MBEDTLS_LMS_H_TREE_HEIGHT(type) + in length. */ + unsigned char MBEDTLS_PRIVATE(have_private_key); /*!< Whether the context contains a private key. + Boolean values only. */ +} mbedtls_lms_private_t; +#endif /* defined(MBEDTLS_LMS_PRIVATE) */ + +/** + * \brief This function initializes an LMS public context + * + * \param ctx The uninitialized LMS context that will then be + * initialized. + */ +void mbedtls_lms_public_init(mbedtls_lms_public_t *ctx); + +/** + * \brief This function uninitializes an LMS public context + * + * \param ctx The initialized LMS context that will then be + * uninitialized. + */ +void mbedtls_lms_public_free(mbedtls_lms_public_t *ctx); + +/** + * \brief This function imports an LMS public key into a + * public LMS context. + * + * \note Before this function is called, the context must + * have been initialized. + * + * \note See IETF RFC8554 for details of the encoding of + * this public key. + * + * \param ctx The initialized LMS context store the key in. + * \param key The buffer from which the key will be read. + * #MBEDTLS_LMS_PUBLIC_KEY_LEN bytes will be read from + * this. + * \param key_size The size of the key being imported. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_import_public_key(mbedtls_lms_public_t *ctx, + const unsigned char *key, size_t key_size); + +/** + * \brief This function exports an LMS public key from a + * LMS public context that already contains a public + * key. + * + * \note Before this function is called, the context must + * have been initialized and the context must contain + * a public key. + * + * \note See IETF RFC8554 for details of the encoding of + * this public key. + * + * \param ctx The initialized LMS public context that contains + * the public key. + * \param key The buffer into which the key will be output. Must + * be at least #MBEDTLS_LMS_PUBLIC_KEY_LEN in size. + * \param key_size The size of the key buffer. + * \param key_len If not NULL, will be written with the size of the + * key. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_export_public_key(const mbedtls_lms_public_t *ctx, + unsigned char *key, size_t key_size, + size_t *key_len); + +/** + * \brief This function verifies a LMS signature, using a + * LMS context that contains a public key. + * + * \note Before this function is called, the context must + * have been initialized and must contain a public key + * (either by import or generation). + * + * \param ctx The initialized LMS public context from which the + * public key will be read. + * \param msg The buffer from which the message will be read. + * \param msg_size The size of the message that will be read. + * \param sig The buf from which the signature will be read. + * #MBEDTLS_LMS_SIG_LEN bytes will be read from + * this. + * \param sig_size The size of the signature to be verified. + * + * \return \c 0 on successful verification. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_verify(const mbedtls_lms_public_t *ctx, + const unsigned char *msg, size_t msg_size, + const unsigned char *sig, size_t sig_size); + +#if defined(MBEDTLS_LMS_PRIVATE) +/** + * \brief This function initializes an LMS private context + * + * \param ctx The uninitialized LMS private context that will + * then be initialized. */ +void mbedtls_lms_private_init(mbedtls_lms_private_t *ctx); + +/** + * \brief This function uninitializes an LMS private context + * + * \param ctx The initialized LMS private context that will then + * be uninitialized. + */ +void mbedtls_lms_private_free(mbedtls_lms_private_t *ctx); + +/** + * \brief This function generates an LMS private key, and + * stores in into an LMS private context. + * + * \warning This function is **not intended for use in + * production**, due to as-yet unsolved problems with + * handling stateful keys. The API for this function + * may change considerably in future versions. + * + * \note The seed must have at least 256 bits of entropy. + * + * \param ctx The initialized LMOTS context to generate the key + * into. + * \param type The LMS parameter set identifier. + * \param otstype The LMOTS parameter set identifier. + * \param f_rng The RNG function to be used to generate the key ID. + * \param p_rng The RNG context to be passed to f_rng + * \param seed The seed used to deterministically generate the + * key. + * \param seed_size The length of the seed. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_generate_private_key(mbedtls_lms_private_t *ctx, + mbedtls_lms_algorithm_type_t type, + mbedtls_lmots_algorithm_type_t otstype, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, const unsigned char *seed, + size_t seed_size); + +/** + * \brief This function calculates an LMS public key from a + * LMS context that already contains a private key. + * + * \note Before this function is called, the context must + * have been initialized and the context must contain + * a private key. + * + * \param ctx The initialized LMS public context to calculate the key + * from and store it into. + * + * \param priv_ctx The LMS private context to read the private key + * from. This must have been initialized and contain a + * private key. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_calculate_public_key(mbedtls_lms_public_t *ctx, + const mbedtls_lms_private_t *priv_ctx); + +/** + * \brief This function creates a LMS signature, using a + * LMS context that contains unused private keys. + * + * \warning This function is **not intended for use in + * production**, due to as-yet unsolved problems with + * handling stateful keys. The API for this function + * may change considerably in future versions. + * + * \note Before this function is called, the context must + * have been initialized and must contain a private + * key. + * + * \note Each of the LMOTS private keys inside a LMS private + * key can only be used once. If they are reused, then + * attackers may be able to forge signatures with that + * key. This is all handled transparently, but it is + * important to not perform copy operations on LMS + * contexts that contain private key material. + * + * \param ctx The initialized LMS private context from which the + * private key will be read. + * \param f_rng The RNG function to be used for signature + * generation. + * \param p_rng The RNG context to be passed to f_rng + * \param msg The buffer from which the message will be read. + * \param msg_size The size of the message that will be read. + * \param sig The buf into which the signature will be stored. + * Must be at least #MBEDTLS_LMS_SIG_LEN in size. + * \param sig_size The size of the buffer the signature will be + * written into. + * \param sig_len If not NULL, will be written with the size of the + * signature. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lms_sign(mbedtls_lms_private_t *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, const unsigned char *msg, + unsigned int msg_size, unsigned char *sig, size_t sig_size, + size_t *sig_len); +#endif /* defined(MBEDTLS_LMS_PRIVATE) */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_LMS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/mbedtls_config.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/mbedtls_config.h index af07613..5324166 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/mbedtls_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/mbedtls_config.h @@ -1,4125 +1,4125 @@ -/** - * \file mbedtls_config.h - * - * \brief Configuration options (set of defines) - * - * This set of compile-time options may be used to enable - * or disable features selectively, and reduce the global - * memory footprint. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * This is an optional version symbol that enables compatibility handling of - * config files. - * - * It is equal to the #MBEDTLS_VERSION_NUMBER of the Mbed TLS version that - * introduced the config format we want to be compatible with. - */ -//#define MBEDTLS_CONFIG_VERSION 0x03000000 - -/** - * \name SECTION: System support - * - * This section sets system specific settings. - * \{ - */ - -/** - * \def MBEDTLS_HAVE_ASM - * - * The compiler has support for asm(). - * - * Requires support for asm() in compiler. - * - * Used in: - * library/aesni.h - * library/aria.c - * library/bn_mul.h - * library/constant_time.c - * library/padlock.h - * - * Required by: - * MBEDTLS_AESCE_C - * MBEDTLS_AESNI_C (on some platforms) - * MBEDTLS_PADLOCK_C - * - * Comment to disable the use of assembly code. - */ -#define MBEDTLS_HAVE_ASM - -/** - * \def MBEDTLS_NO_UDBL_DIVISION - * - * The platform lacks support for double-width integer division (64-bit - * division on a 32-bit platform, 128-bit division on a 64-bit platform). - * - * Used in: - * include/mbedtls/bignum.h - * library/bignum.c - * - * The bignum code uses double-width division to speed up some operations. - * Double-width division is often implemented in software that needs to - * be linked with the program. The presence of a double-width integer - * type is usually detected automatically through preprocessor macros, - * but the automatic detection cannot know whether the code needs to - * and can be linked with an implementation of division for that type. - * By default division is assumed to be usable if the type is present. - * Uncomment this option to prevent the use of double-width division. - * - * Note that division for the native integer type is always required. - * Furthermore, a 64-bit type is always required even on a 32-bit - * platform, but it need not support multiplication or division. In some - * cases it is also desirable to disable some double-width operations. For - * example, if double-width division is implemented in software, disabling - * it can reduce code size in some embedded targets. - */ -//#define MBEDTLS_NO_UDBL_DIVISION - -/** - * \def MBEDTLS_NO_64BIT_MULTIPLICATION - * - * The platform lacks support for 32x32 -> 64-bit multiplication. - * - * Used in: - * library/poly1305.c - * - * Some parts of the library may use multiplication of two unsigned 32-bit - * operands with a 64-bit result in order to speed up computations. On some - * platforms, this is not available in hardware and has to be implemented in - * software, usually in a library provided by the toolchain. - * - * Sometimes it is not desirable to have to link to that library. This option - * removes the dependency of that library on platforms that lack a hardware - * 64-bit multiplier by embedding a software implementation in Mbed TLS. - * - * Note that depending on the compiler, this may decrease performance compared - * to using the library function provided by the toolchain. - */ -//#define MBEDTLS_NO_64BIT_MULTIPLICATION - -/** - * \def MBEDTLS_HAVE_SSE2 - * - * CPU supports SSE2 instruction set. - * - * Uncomment if the CPU supports SSE2 (IA-32 specific). - */ -//#define MBEDTLS_HAVE_SSE2 - -/** - * \def MBEDTLS_HAVE_TIME - * - * System has time.h and time(). - * The time does not need to be correct, only time differences are used, - * by contrast with MBEDTLS_HAVE_TIME_DATE - * - * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, - * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and - * MBEDTLS_PLATFORM_STD_TIME. - * - * Comment if your system does not support time functions. - * - * \note If MBEDTLS_TIMING_C is set - to enable the semi-portable timing - * interface - timing.c will include time.h on suitable platforms - * regardless of the setting of MBEDTLS_HAVE_TIME, unless - * MBEDTLS_TIMING_ALT is used. See timing.c for more information. - */ -#define MBEDTLS_HAVE_TIME - -/** - * \def MBEDTLS_HAVE_TIME_DATE - * - * System has time.h, time(), and an implementation for - * mbedtls_platform_gmtime_r() (see below). - * The time needs to be correct (not necessarily very accurate, but at least - * the date should be correct). This is used to verify the validity period of - * X.509 certificates. - * - * Comment if your system does not have a correct clock. - * - * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that - * behaves similarly to the gmtime_r() function from the C standard. Refer to - * the documentation for mbedtls_platform_gmtime_r() for more information. - * - * \note It is possible to configure an implementation for - * mbedtls_platform_gmtime_r() at compile-time by using the macro - * MBEDTLS_PLATFORM_GMTIME_R_ALT. - */ -#define MBEDTLS_HAVE_TIME_DATE - -/** - * \def MBEDTLS_PLATFORM_MEMORY - * - * Enable the memory allocation layer. - * - * By default Mbed TLS uses the system-provided calloc() and free(). - * This allows different allocators (self-implemented or provided) to be - * provided to the platform abstraction layer. - * - * Enabling #MBEDTLS_PLATFORM_MEMORY without the - * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide - * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and - * free() function pointer at runtime. - * - * Enabling #MBEDTLS_PLATFORM_MEMORY and specifying - * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the - * alternate function at compile time. - * - * An overview of how the value of mbedtls_calloc is determined: - * - * - if !MBEDTLS_PLATFORM_MEMORY - * - mbedtls_calloc = calloc - * - if MBEDTLS_PLATFORM_MEMORY - * - if (MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): - * - mbedtls_calloc = MBEDTLS_PLATFORM_CALLOC_MACRO - * - if !(MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): - * - Dynamic setup via mbedtls_platform_set_calloc_free is now possible with a default value MBEDTLS_PLATFORM_STD_CALLOC. - * - How is MBEDTLS_PLATFORM_STD_CALLOC handled? - * - if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: - * - MBEDTLS_PLATFORM_STD_CALLOC is not set to anything; - * - MBEDTLS_PLATFORM_STD_MEM_HDR can be included if present; - * - if !MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: - * - if MBEDTLS_PLATFORM_STD_CALLOC is present: - * - User-defined MBEDTLS_PLATFORM_STD_CALLOC is respected; - * - if !MBEDTLS_PLATFORM_STD_CALLOC: - * - MBEDTLS_PLATFORM_STD_CALLOC = calloc - * - * - At this point the presence of MBEDTLS_PLATFORM_STD_CALLOC is checked. - * - if !MBEDTLS_PLATFORM_STD_CALLOC - * - MBEDTLS_PLATFORM_STD_CALLOC = uninitialized_calloc - * - * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. - * - * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. - * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. - * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they are used, - * dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * - * Requires: MBEDTLS_PLATFORM_C - * - * Enable this layer to allow use of alternative memory allocators. - */ -//#define MBEDTLS_PLATFORM_MEMORY - -/** - * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS - * - * Do not assign standard functions in the platform layer (e.g. calloc() to - * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) - * - * This makes sure there are no linking errors on platforms that do not support - * these functions. You will HAVE to provide alternatives, either at runtime - * via the platform_set_xxx() functions or at compile time by setting - * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a - * MBEDTLS_PLATFORM_XXX_MACRO. - * - * Requires: MBEDTLS_PLATFORM_C - * - * Uncomment to prevent default assignment of standard functions in the - * platform layer. - */ -//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS - -/** - * \def MBEDTLS_PLATFORM_EXIT_ALT - * - * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let Mbed TLS support the - * function in the platform abstraction layer. - * - * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, Mbed TLS will - * provide a function "mbedtls_platform_set_printf()" that allows you to set an - * alternative printf function pointer. - * - * All these define require MBEDTLS_PLATFORM_C to be defined! - * - * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; - * it will be enabled automatically by check_config.h - * - * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as - * MBEDTLS_PLATFORM_XXX_MACRO! - * - * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME - * - * Uncomment a macro to enable alternate implementation of specific base - * platform function - */ -//#define MBEDTLS_PLATFORM_SETBUF_ALT -//#define MBEDTLS_PLATFORM_EXIT_ALT -//#define MBEDTLS_PLATFORM_TIME_ALT -//#define MBEDTLS_PLATFORM_FPRINTF_ALT -//#define MBEDTLS_PLATFORM_PRINTF_ALT -//#define MBEDTLS_PLATFORM_SNPRINTF_ALT -//#define MBEDTLS_PLATFORM_VSNPRINTF_ALT -//#define MBEDTLS_PLATFORM_NV_SEED_ALT -//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT -//#define MBEDTLS_PLATFORM_MS_TIME_ALT - -/** - * Uncomment the macro to let Mbed TLS use your alternate implementation of - * mbedtls_platform_gmtime_r(). This replaces the default implementation in - * platform_util.c. - * - * gmtime() is not a thread-safe function as defined in the C standard. The - * library will try to use safer implementations of this function, such as - * gmtime_r() when available. However, if Mbed TLS cannot identify the target - * system, the implementation of mbedtls_platform_gmtime_r() will default to - * using the standard gmtime(). In this case, calls from the library to - * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex - * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the - * library are also guarded with this mutex to avoid race conditions. However, - * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will - * unconditionally use the implementation for mbedtls_platform_gmtime_r() - * supplied at compile time. - */ -//#define MBEDTLS_PLATFORM_GMTIME_R_ALT - -/** - * Uncomment the macro to let Mbed TLS use your alternate implementation of - * mbedtls_platform_zeroize(), to wipe sensitive data in memory. This replaces - * the default implementation in platform_util.c. - * - * By default, the library uses a system function such as memset_s() - * (optional feature of C11), explicit_bzero() (BSD and compatible), or - * SecureZeroMemory (Windows). If no such function is detected, the library - * falls back to a plain C implementation. Compilers are technically - * permitted to optimize this implementation out, meaning that the memory is - * not actually wiped. The library tries to prevent that, but the C language - * makes it impossible to guarantee that the memory will always be wiped. - * - * If your platform provides a guaranteed method to wipe memory which - * `platform_util.c` does not detect, define this macro to the name of - * a function that takes two arguments, a `void *` pointer and a length, - * and wipes that many bytes starting at the specified address. For example, - * if your platform has explicit_bzero() but `platform_util.c` does not - * detect its presence, define `MBEDTLS_PLATFORM_ZEROIZE_ALT` to be - * `explicit_bzero` to use that function as mbedtls_platform_zeroize(). - */ -//#define MBEDTLS_PLATFORM_ZEROIZE_ALT - -/** - * \def MBEDTLS_DEPRECATED_WARNING - * - * Mark deprecated functions and features so that they generate a warning if - * used. Functionality deprecated in one version will usually be removed in the - * next version. You can enable this to help you prepare the transition to a - * new major version by making sure your code is not using this functionality. - * - * This only works with GCC and Clang. With other compilers, you may want to - * use MBEDTLS_DEPRECATED_REMOVED - * - * Uncomment to get warnings on using deprecated functions and features. - */ -//#define MBEDTLS_DEPRECATED_WARNING - -/** - * \def MBEDTLS_DEPRECATED_REMOVED - * - * Remove deprecated functions and features so that they generate an error if - * used. Functionality deprecated in one version will usually be removed in the - * next version. You can enable this to help you prepare the transition to a - * new major version by making sure your code is not using this functionality. - * - * Uncomment to get errors on using deprecated functions and features. - */ -//#define MBEDTLS_DEPRECATED_REMOVED - -/** \} name SECTION: System support */ - -/** - * \name SECTION: Mbed TLS feature support - * - * This section sets support for features that are or are not needed - * within the modules that are enabled. - * \{ - */ - -/** - * \def MBEDTLS_TIMING_ALT - * - * Uncomment to provide your own alternate implementation for - * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() - * - * Only works if you have MBEDTLS_TIMING_C enabled. - * - * You will need to provide a header "timing_alt.h" and an implementation at - * compile time. - */ -//#define MBEDTLS_TIMING_ALT - -/** - * \def MBEDTLS_AES_ALT - * - * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let Mbed TLS use your - * alternate core implementation of a symmetric crypto, an arithmetic or hash - * module (e.g. platform specific assembly optimized implementations). Keep - * in mind that the function prototypes should remain the same. - * - * This replaces the whole module. If you only want to replace one of the - * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. - * - * Example: In case you uncomment MBEDTLS_AES_ALT, Mbed TLS will no longer - * provide the "struct mbedtls_aes_context" definition and omit the base - * function declarations and implementations. "aes_alt.h" will be included from - * "aes.h" to include the new function definitions. - * - * Uncomment a macro to enable alternate implementation of the corresponding - * module. - * - * \warning MD5, DES and SHA-1 are considered weak and their - * use constitutes a security risk. If possible, we recommend - * avoiding dependencies on them, and considering stronger message - * digests and ciphers instead. - * - */ -//#define MBEDTLS_AES_ALT -//#define MBEDTLS_ARIA_ALT -//#define MBEDTLS_CAMELLIA_ALT -//#define MBEDTLS_CCM_ALT -//#define MBEDTLS_CHACHA20_ALT -//#define MBEDTLS_CHACHAPOLY_ALT -//#define MBEDTLS_CMAC_ALT -//#define MBEDTLS_DES_ALT -//#define MBEDTLS_DHM_ALT -//#define MBEDTLS_ECJPAKE_ALT -//#define MBEDTLS_GCM_ALT -//#define MBEDTLS_NIST_KW_ALT -//#define MBEDTLS_MD5_ALT -//#define MBEDTLS_POLY1305_ALT -//#define MBEDTLS_RIPEMD160_ALT -//#define MBEDTLS_RSA_ALT -//#define MBEDTLS_SHA1_ALT -//#define MBEDTLS_SHA256_ALT -//#define MBEDTLS_SHA512_ALT - -/* - * When replacing the elliptic curve module, please consider, that it is - * implemented with two .c files: - * - ecp.c - * - ecp_curves.c - * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT - * macros as described above. The only difference is that you have to make sure - * that you provide functionality for both .c files. - */ -//#define MBEDTLS_ECP_ALT - -/** - * \def MBEDTLS_SHA256_PROCESS_ALT - * - * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use you - * alternate core implementation of symmetric crypto or hash function. Keep in - * mind that function prototypes should remain the same. - * - * This replaces only one function. The header file from Mbed TLS is still - * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. - * - * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, Mbed TLS will - * no longer provide the mbedtls_sha1_process() function, but it will still provide - * the other function (using your mbedtls_sha1_process() function) and the definition - * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible - * with this definition. - * - * \note If you use the AES_xxx_ALT macros, then it is recommended to also set - * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES - * tables. - * - * Uncomment a macro to enable alternate implementation of the corresponding - * function. - * - * \warning MD5, DES and SHA-1 are considered weak and their use - * constitutes a security risk. If possible, we recommend avoiding - * dependencies on them, and considering stronger message digests - * and ciphers instead. - * - * \warning If both MBEDTLS_ECDSA_SIGN_ALT and MBEDTLS_ECDSA_DETERMINISTIC are - * enabled, then the deterministic ECDH signature functions pass the - * the static HMAC-DRBG as RNG to mbedtls_ecdsa_sign(). Therefore - * alternative implementations should use the RNG only for generating - * the ephemeral key and nothing else. If this is not possible, then - * MBEDTLS_ECDSA_DETERMINISTIC should be disabled and an alternative - * implementation should be provided for mbedtls_ecdsa_sign_det_ext(). - * - */ -//#define MBEDTLS_MD5_PROCESS_ALT -//#define MBEDTLS_RIPEMD160_PROCESS_ALT -//#define MBEDTLS_SHA1_PROCESS_ALT -//#define MBEDTLS_SHA256_PROCESS_ALT -//#define MBEDTLS_SHA512_PROCESS_ALT -//#define MBEDTLS_DES_SETKEY_ALT -//#define MBEDTLS_DES_CRYPT_ECB_ALT -//#define MBEDTLS_DES3_CRYPT_ECB_ALT -//#define MBEDTLS_AES_SETKEY_ENC_ALT -//#define MBEDTLS_AES_SETKEY_DEC_ALT -//#define MBEDTLS_AES_ENCRYPT_ALT -//#define MBEDTLS_AES_DECRYPT_ALT -//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT -//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT -//#define MBEDTLS_ECDSA_VERIFY_ALT -//#define MBEDTLS_ECDSA_SIGN_ALT -//#define MBEDTLS_ECDSA_GENKEY_ALT - -/** - * \def MBEDTLS_ECP_INTERNAL_ALT - * - * Expose a part of the internal interface of the Elliptic Curve Point module. - * - * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use your - * alternative core implementation of elliptic curve arithmetic. Keep in mind - * that function prototypes should remain the same. - * - * This partially replaces one function. The header file from Mbed TLS is still - * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation - * is still present and it is used for group structures not supported by the - * alternative. - * - * The original implementation can in addition be removed by setting the - * MBEDTLS_ECP_NO_FALLBACK option, in which case any function for which the - * corresponding MBEDTLS_ECP__FUNCTION_NAME__ALT macro is defined will not be - * able to fallback to curves not supported by the alternative implementation. - * - * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT - * and implementing the following functions: - * unsigned char mbedtls_internal_ecp_grp_capable( - * const mbedtls_ecp_group *grp ) - * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) - * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) - * The mbedtls_internal_ecp_grp_capable function should return 1 if the - * replacement functions implement arithmetic for the given group and 0 - * otherwise. - * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are - * called before and after each point operation and provide an opportunity to - * implement optimized set up and tear down instructions. - * - * Example: In case you set MBEDTLS_ECP_INTERNAL_ALT and - * MBEDTLS_ECP_DOUBLE_JAC_ALT, Mbed TLS will still provide the ecp_double_jac() - * function, but will use your mbedtls_internal_ecp_double_jac() if the group - * for the operation is supported by your implementation (i.e. your - * mbedtls_internal_ecp_grp_capable() function returns 1 for this group). If the - * group is not supported by your implementation, then the original Mbed TLS - * implementation of ecp_double_jac() is used instead, unless this fallback - * behaviour is disabled by setting MBEDTLS_ECP_NO_FALLBACK (in which case - * ecp_double_jac() will return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE). - * - * The function prototypes and the definition of mbedtls_ecp_group and - * mbedtls_ecp_point will not change based on MBEDTLS_ECP_INTERNAL_ALT, so your - * implementation of mbedtls_internal_ecp__function_name__ must be compatible - * with their definitions. - * - * Uncomment a macro to enable alternate implementation of the corresponding - * function. - */ -/* Required for all the functions in this section */ -//#define MBEDTLS_ECP_INTERNAL_ALT -/* Turn off software fallback for curves not supported in hardware */ -//#define MBEDTLS_ECP_NO_FALLBACK -/* Support for Weierstrass curves with Jacobi representation */ -//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT -//#define MBEDTLS_ECP_ADD_MIXED_ALT -//#define MBEDTLS_ECP_DOUBLE_JAC_ALT -//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT -//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT -/* Support for curves with Montgomery arithmetic */ -//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT -//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT -//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT - -/** - * \def MBEDTLS_ENTROPY_HARDWARE_ALT - * - * Uncomment this macro to let Mbed TLS use your own implementation of a - * hardware entropy collector. - * - * Your function must be called \c mbedtls_hardware_poll(), have the same - * prototype as declared in library/entropy_poll.h, and accept NULL as first - * argument. - * - * Uncomment to use your own hardware entropy collector. - */ -//#define MBEDTLS_ENTROPY_HARDWARE_ALT - -/** - * \def MBEDTLS_AES_ROM_TABLES - * - * Use precomputed AES tables stored in ROM. - * - * Uncomment this macro to use precomputed AES tables stored in ROM. - * Comment this macro to generate AES tables in RAM at runtime. - * - * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb - * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the - * initialization time before the first AES operation can be performed. - * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c - * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded - * performance if ROM access is slower than RAM access. - * - * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. - */ -//#define MBEDTLS_AES_ROM_TABLES - -/** - * \def MBEDTLS_AES_FEWER_TABLES - * - * Use less ROM/RAM for AES tables. - * - * Uncommenting this macro omits 75% of the AES tables from - * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) - * by computing their values on the fly during operations - * (the tables are entry-wise rotations of one another). - * - * Tradeoff: Uncommenting this reduces the RAM / ROM footprint - * by ~6kb but at the cost of more arithmetic operations during - * runtime. Specifically, one has to compare 4 accesses within - * different tables to 4 accesses with additional arithmetic - * operations within the same table. The performance gain/loss - * depends on the system and memory details. - * - * This option is independent of \c MBEDTLS_AES_ROM_TABLES. - */ -//#define MBEDTLS_AES_FEWER_TABLES - -/** - * \def MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH - * - * Use only 128-bit keys in AES operations to save ROM. - * - * Uncomment this macro to remove support for AES operations that use 192- - * or 256-bit keys. - * - * Uncommenting this macro reduces the size of AES code by ~300 bytes - * on v8-M/Thumb2. - * - * Module: library/aes.c - * - * Requires: MBEDTLS_AES_C - */ -//#define MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH - -/* - * Disable plain C implementation for AES. - * - * When the plain C implementation is enabled, and an implementation using a - * special CPU feature (such as MBEDTLS_AESCE_C) is also enabled, runtime - * detection will be used to select between them. - * - * If only one implementation is present, runtime detection will not be used. - * This configuration will crash at runtime if running on a CPU without the - * necessary features. It will not build unless at least one of MBEDTLS_AESCE_C - * and/or MBEDTLS_AESNI_C is enabled & present in the build. - */ -//#define MBEDTLS_AES_USE_HARDWARE_ONLY - -/** - * \def MBEDTLS_CAMELLIA_SMALL_MEMORY - * - * Use less ROM for the Camellia implementation (saves about 768 bytes). - * - * Uncomment this macro to use less memory for Camellia. - */ -//#define MBEDTLS_CAMELLIA_SMALL_MEMORY - -/** - * \def MBEDTLS_CHECK_RETURN_WARNING - * - * If this macro is defined, emit a compile-time warning if application code - * calls a function without checking its return value, but the return value - * should generally be checked in portable applications. - * - * This is only supported on platforms where #MBEDTLS_CHECK_RETURN is - * implemented. Otherwise this option has no effect. - * - * Uncomment to get warnings on using fallible functions without checking - * their return value. - * - * \note This feature is a work in progress. - * Warnings will be added to more functions in the future. - * - * \note A few functions are considered critical, and ignoring the return - * value of these functions will trigger a warning even if this - * macro is not defined. To completely disable return value check - * warnings, define #MBEDTLS_CHECK_RETURN with an empty expansion. - */ -//#define MBEDTLS_CHECK_RETURN_WARNING - -/** - * \def MBEDTLS_CIPHER_MODE_CBC - * - * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers. - */ -#define MBEDTLS_CIPHER_MODE_CBC - -/** - * \def MBEDTLS_CIPHER_MODE_CFB - * - * Enable Cipher Feedback mode (CFB) for symmetric ciphers. - */ -#define MBEDTLS_CIPHER_MODE_CFB - -/** - * \def MBEDTLS_CIPHER_MODE_CTR - * - * Enable Counter Block Cipher mode (CTR) for symmetric ciphers. - */ -#define MBEDTLS_CIPHER_MODE_CTR - -/** - * \def MBEDTLS_CIPHER_MODE_OFB - * - * Enable Output Feedback mode (OFB) for symmetric ciphers. - */ -#define MBEDTLS_CIPHER_MODE_OFB - -/** - * \def MBEDTLS_CIPHER_MODE_XTS - * - * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES. - */ -#define MBEDTLS_CIPHER_MODE_XTS - -/** - * \def MBEDTLS_CIPHER_NULL_CIPHER - * - * Enable NULL cipher. - * Warning: Only do so when you know what you are doing. This allows for - * encryption or channels without any security! - * - * To enable the following ciphersuites: - * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA - * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA - * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA - * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA - * MBEDTLS_TLS_RSA_WITH_NULL_SHA256 - * MBEDTLS_TLS_RSA_WITH_NULL_SHA - * MBEDTLS_TLS_RSA_WITH_NULL_MD5 - * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA - * MBEDTLS_TLS_PSK_WITH_NULL_SHA384 - * MBEDTLS_TLS_PSK_WITH_NULL_SHA256 - * MBEDTLS_TLS_PSK_WITH_NULL_SHA - * - * Uncomment this macro to enable the NULL cipher and ciphersuites - */ -//#define MBEDTLS_CIPHER_NULL_CIPHER - -/** - * \def MBEDTLS_CIPHER_PADDING_PKCS7 - * - * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for - * specific padding modes in the cipher layer with cipher modes that support - * padding (e.g. CBC) - * - * If you disable all padding modes, only full blocks can be used with CBC. - * - * Enable padding modes in the cipher layer. - */ -#define MBEDTLS_CIPHER_PADDING_PKCS7 -#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS -#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN -#define MBEDTLS_CIPHER_PADDING_ZEROS - -/** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY - * - * Uncomment this macro to use a 128-bit key in the CTR_DRBG module. - * Without this, CTR_DRBG uses a 256-bit key - * unless \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. - */ -//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY - -/** - * Enable the verified implementations of ECDH primitives from Project Everest - * (currently only Curve25519). This feature changes the layout of ECDH - * contexts and therefore is a compatibility break for applications that access - * fields of a mbedtls_ecdh_context structure directly. See also - * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h. - */ -//#define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED - -/** - * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED - * - * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve - * module. By default all supported curves are enabled. - * - * Comment macros to disable the curve and functions for it - */ -/* Short Weierstrass curves (supporting ECP, ECDH, ECDSA) */ -#define MBEDTLS_ECP_DP_SECP192R1_ENABLED -#define MBEDTLS_ECP_DP_SECP224R1_ENABLED -#define MBEDTLS_ECP_DP_SECP256R1_ENABLED -#define MBEDTLS_ECP_DP_SECP384R1_ENABLED -#define MBEDTLS_ECP_DP_SECP521R1_ENABLED -#define MBEDTLS_ECP_DP_SECP192K1_ENABLED -#define MBEDTLS_ECP_DP_SECP224K1_ENABLED -#define MBEDTLS_ECP_DP_SECP256K1_ENABLED -#define MBEDTLS_ECP_DP_BP256R1_ENABLED -#define MBEDTLS_ECP_DP_BP384R1_ENABLED -#define MBEDTLS_ECP_DP_BP512R1_ENABLED -/* Montgomery curves (supporting ECP) */ -#define MBEDTLS_ECP_DP_CURVE25519_ENABLED -#define MBEDTLS_ECP_DP_CURVE448_ENABLED - -/** - * \def MBEDTLS_ECP_NIST_OPTIM - * - * Enable specific 'modulo p' routines for each NIST prime. - * Depending on the prime and architecture, makes operations 4 to 8 times - * faster on the corresponding curve. - * - * Comment this macro to disable NIST curves optimisation. - */ -#define MBEDTLS_ECP_NIST_OPTIM - -/** - * \def MBEDTLS_ECP_RESTARTABLE - * - * Enable "non-blocking" ECC operations that can return early and be resumed. - * - * This allows various functions to pause by returning - * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module, - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in - * order to further progress and eventually complete their operation. This is - * controlled through mbedtls_ecp_set_max_ops() which limits the maximum - * number of ECC operations a function may perform before pausing; see - * mbedtls_ecp_set_max_ops() for more information. - * - * This is useful in non-threaded environments if you want to avoid blocking - * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. - * - * This option: - * - Adds xxx_restartable() variants of existing operations in the - * following modules, with corresponding restart context types: - * - ECP (for Short Weierstrass curves only): scalar multiplication (mul), - * linear combination (muladd); - * - ECDSA: signature generation & verification; - * - PK: signature generation & verification; - * - X509: certificate chain verification. - * - Adds mbedtls_ecdh_enable_restart() in the ECDH module. - * - Changes the behaviour of TLS 1.2 clients (not servers) when using the - * ECDHE-ECDSA key exchange (not other key exchanges) to make all ECC - * computations restartable: - * - ECDH operations from the key exchange, only for Short Weierstrass - * curves, only when MBEDTLS_USE_PSA_CRYPTO is not enabled. - * - verification of the server's key exchange signature; - * - verification of the server's certificate chain; - * - generation of the client's signature if client authentication is used, - * with an ECC key/certificate. - * - * \note In the cases above, the usual SSL/TLS functions, such as - * mbedtls_ssl_handshake(), can now return - * MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS. - * - * \note When this option and MBEDTLS_USE_PSA_CRYPTO are both enabled, - * restartable operations in PK, X.509 and TLS (see above) are not - * using PSA. On the other hand, ECDH computations in TLS are using - * PSA, and are not restartable. These are temporary limitations that - * should be lifted in the future. - * - * \note This option only works with the default software implementation of - * elliptic curve functionality. It is incompatible with - * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT, MBEDTLS_ECDSA_XXX_ALT. - * - * Requires: MBEDTLS_ECP_C - * - * Uncomment this macro to enable restartable ECC computations. - */ -//#define MBEDTLS_ECP_RESTARTABLE - -/** - * Uncomment to enable using new bignum code in the ECC modules. - * - * \warning This is currently experimental, incomplete and therefore should not - * be used in production. - */ -//#define MBEDTLS_ECP_WITH_MPI_UINT - -/** - * \def MBEDTLS_ECDSA_DETERMINISTIC - * - * Enable deterministic ECDSA (RFC 6979). - * Standard ECDSA is "fragile" in the sense that lack of entropy when signing - * may result in a compromise of the long-term signing key. This is avoided by - * the deterministic variant. - * - * Requires: MBEDTLS_HMAC_DRBG_C, MBEDTLS_ECDSA_C - * - * Comment this macro to disable deterministic ECDSA. - */ -#define MBEDTLS_ECDSA_DETERMINISTIC - -/** - * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED - * - * Enable the PSK based ciphersuite modes in SSL / TLS. - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED - * - * Enable the DHE-PSK based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_DHM_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 - * - * \warning Using DHE constitutes a security risk as it - * is not possible to validate custom DH parameters. - * If possible, it is recommended users should consider - * preferring other methods of key exchange. - * See dhm.h for more details. - * - */ -#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - * - * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED - * - * Enable the RSA-PSK based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED - * - * Enable the RSA-only based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA - */ -#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED - * - * Enable the DHE-RSA based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA - * - * \warning Using DHE constitutes a security risk as it - * is not possible to validate custom DH parameters. - * If possible, it is recommended users should consider - * preferring other methods of key exchange. - * See dhm.h for more details. - * - */ -#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED - * - * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) - * MBEDTLS_RSA_C - * MBEDTLS_PKCS1_V15 - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED - * - * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) - * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED - * - * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) - * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 - */ -#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED - * - * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. - * - * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) - * MBEDTLS_RSA_C - * MBEDTLS_X509_CRT_PARSE_C - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 - */ -#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED - -/** - * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED - * - * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. - * - * \warning This is currently experimental. EC J-PAKE support is based on the - * Thread v1.0.0 specification; incompatible changes to the specification - * might still happen. For this reason, this is disabled by default. - * - * Requires: MBEDTLS_ECJPAKE_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_JPAKE) - * SHA-256 (via MBEDTLS_SHA256_C or a PSA driver) - * MBEDTLS_ECP_DP_SECP256R1_ENABLED - * - * \warning If SHA-256 is provided only by a PSA driver, you must call - * psa_crypto_init() before the first hanshake (even if - * MBEDTLS_USE_PSA_CRYPTO is disabled). - * - * This enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 - */ -//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED - -/** - * \def MBEDTLS_PK_PARSE_EC_EXTENDED - * - * Enhance support for reading EC keys using variants of SEC1 not allowed by - * RFC 5915 and RFC 5480. - * - * Currently this means parsing the SpecifiedECDomain choice of EC - * parameters (only known groups are supported, not arbitrary domains, to - * avoid validation issues). - * - * Disable if you only need to support RFC 5915 + 5480 key formats. - */ -#define MBEDTLS_PK_PARSE_EC_EXTENDED - -/** - * \def MBEDTLS_PK_PARSE_EC_COMPRESSED - * - * Enable the support for parsing public keys of type Short Weierstrass - * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX) which are using the - * compressed point format. This parsing is done through ECP module's functions. - * - * \note As explained in the description of MBEDTLS_ECP_PF_COMPRESSED (in ecp.h) - * the only unsupported curves are MBEDTLS_ECP_DP_SECP224R1 and - * MBEDTLS_ECP_DP_SECP224K1. - */ -#define MBEDTLS_PK_PARSE_EC_COMPRESSED - -/** - * \def MBEDTLS_ERROR_STRERROR_DUMMY - * - * Enable a dummy error function to make use of mbedtls_strerror() in - * third party libraries easier when MBEDTLS_ERROR_C is disabled - * (no effect when MBEDTLS_ERROR_C is enabled). - * - * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're - * not using mbedtls_strerror() or error_strerror() in your application. - * - * Disable if you run into name conflicts and want to really remove the - * mbedtls_strerror() - */ -#define MBEDTLS_ERROR_STRERROR_DUMMY - -/** - * \def MBEDTLS_GENPRIME - * - * Enable the prime-number generation code. - * - * Requires: MBEDTLS_BIGNUM_C - */ -#define MBEDTLS_GENPRIME - -/** - * \def MBEDTLS_FS_IO - * - * Enable functions that use the filesystem. - */ -#define MBEDTLS_FS_IO - -/** - * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES - * - * Do not add default entropy sources in mbedtls_entropy_init(). - * - * This is useful to have more control over the added entropy sources in an - * application. - * - * Uncomment this macro to prevent loading of default entropy functions. - */ -//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES - -/** - * \def MBEDTLS_NO_PLATFORM_ENTROPY - * - * Do not use built-in platform entropy functions. - * This is useful if your platform does not support - * standards like the /dev/urandom or Windows CryptoAPI. - * - * Uncomment this macro to disable the built-in platform entropy functions. - */ -//#define MBEDTLS_NO_PLATFORM_ENTROPY - -/** - * \def MBEDTLS_ENTROPY_FORCE_SHA256 - * - * Force the entropy accumulator to use a SHA-256 accumulator instead of the - * default SHA-512 based one (if both are available). - * - * Requires: MBEDTLS_SHA256_C - * - * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option - * if you have performance concerns. - * - * This option is only useful if both MBEDTLS_SHA256_C and - * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. - */ -//#define MBEDTLS_ENTROPY_FORCE_SHA256 - -/** - * \def MBEDTLS_ENTROPY_NV_SEED - * - * Enable the non-volatile (NV) seed file-based entropy source. - * (Also enables the NV seed read/write functions in the platform layer) - * - * This is crucial (if not required) on systems that do not have a - * cryptographic entropy source (in hardware or kernel) available. - * - * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C - * - * \note The read/write functions that are used by the entropy source are - * determined in the platform layer, and can be modified at runtime and/or - * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. - * - * \note If you use the default implementation functions that read a seedfile - * with regular fopen(), please make sure you make a seedfile with the - * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at - * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from - * and written to or you will get an entropy source error! The default - * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE - * bytes from the file. - * - * \note The entropy collector will write to the seed file before entropy is - * given to an external source, to update it. - */ -//#define MBEDTLS_ENTROPY_NV_SEED - -/* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER - * - * Enable key identifiers that encode a key owner identifier. - * - * The owner of a key is identified by a value of type ::mbedtls_key_owner_id_t - * which is currently hard-coded to be int32_t. - * - * Note that this option is meant for internal use only and may be removed - * without notice. - */ -//#define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER - -/** - * \def MBEDTLS_MEMORY_DEBUG - * - * Enable debugging of buffer allocator memory issues. Automatically prints - * (to stderr) all (fatal) messages on memory allocation issues. Enables - * function for 'debug output' of allocated memory. - * - * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C - * - * Uncomment this macro to let the buffer allocator print out error messages. - */ -//#define MBEDTLS_MEMORY_DEBUG - -/** - * \def MBEDTLS_MEMORY_BACKTRACE - * - * Include backtrace information with each allocated block. - * - * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C - * GLIBC-compatible backtrace() and backtrace_symbols() support - * - * Uncomment this macro to include backtrace information - */ -//#define MBEDTLS_MEMORY_BACKTRACE - -/** - * \def MBEDTLS_PK_RSA_ALT_SUPPORT - * - * Support external private RSA keys (eg from a HSM) in the PK layer. - * - * Comment this macro to disable support for external private RSA keys. - */ -#define MBEDTLS_PK_RSA_ALT_SUPPORT - -/** - * \def MBEDTLS_PKCS1_V15 - * - * Enable support for PKCS#1 v1.5 encoding. - * - * Requires: MBEDTLS_RSA_C - * - * This enables support for PKCS#1 v1.5 operations. - */ -#define MBEDTLS_PKCS1_V15 - -/** - * \def MBEDTLS_PKCS1_V21 - * - * Enable support for PKCS#1 v2.1 encoding. - * - * Requires: MBEDTLS_RSA_C - * - * \warning If using a hash that is only provided by PSA drivers, you must - * call psa_crypto_init() before doing any PKCS#1 v2.1 operation. - * - * This enables support for RSAES-OAEP and RSASSA-PSS operations. - */ -#define MBEDTLS_PKCS1_V21 - -/** \def MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS - * - * Enable support for platform built-in keys. If you enable this feature, - * you must implement the function mbedtls_psa_platform_get_builtin_key(). - * See the documentation of that function for more information. - * - * Built-in keys are typically derived from a hardware unique key or - * stored in a secure element. - * - * Requires: MBEDTLS_PSA_CRYPTO_C. - * - * \warning This interface is experimental and may change or be removed - * without notice. - */ -//#define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS - -/** \def MBEDTLS_PSA_CRYPTO_CLIENT - * - * Enable support for PSA crypto client. - * - * \note This option allows to include the code necessary for a PSA - * crypto client when the PSA crypto implementation is not included in - * the library (MBEDTLS_PSA_CRYPTO_C disabled). The code included is the - * code to set and get PSA key attributes. - * The development of PSA drivers partially relying on the library to - * fulfill the hardware gaps is another possible usage of this option. - * - * \warning This interface is experimental and may change or be removed - * without notice. - */ -//#define MBEDTLS_PSA_CRYPTO_CLIENT - -/** \def MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG - * - * Make the PSA Crypto module use an external random generator provided - * by a driver, instead of Mbed TLS's entropy and DRBG modules. - * - * \note This random generator must deliver random numbers with cryptographic - * quality and high performance. It must supply unpredictable numbers - * with a uniform distribution. The implementation of this function - * is responsible for ensuring that the random generator is seeded - * with sufficient entropy. If you have a hardware TRNG which is slow - * or delivers non-uniform output, declare it as an entropy source - * with mbedtls_entropy_add_source() instead of enabling this option. - * - * If you enable this option, you must configure the type - * ::mbedtls_psa_external_random_context_t in psa/crypto_platform.h - * and define a function called mbedtls_psa_external_get_random() - * with the following prototype: - * ``` - * psa_status_t mbedtls_psa_external_get_random( - * mbedtls_psa_external_random_context_t *context, - * uint8_t *output, size_t output_size, size_t *output_length); - * ); - * ``` - * The \c context value is initialized to 0 before the first call. - * The function must fill the \c output buffer with \c output_size bytes - * of random data and set \c *output_length to \c output_size. - * - * Requires: MBEDTLS_PSA_CRYPTO_C - * - * \warning If you enable this option, code that uses the PSA cryptography - * interface will not use any of the entropy sources set up for - * the entropy module, nor the NV seed that MBEDTLS_ENTROPY_NV_SEED - * enables. - * - * \note This option is experimental and may be removed without notice. - */ -//#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG - -/** - * \def MBEDTLS_PSA_CRYPTO_SPM - * - * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is built for SPM (Secure - * Partition Manager) integration which separates the code into two parts: a - * NSPE (Non-Secure Process Environment) and an SPE (Secure Process - * Environment). - * - * If you enable this option, your build environment must include a header - * file `"crypto_spe.h"` (either in the `psa` subdirectory of the Mbed TLS - * header files, or in another directory on the compiler's include search - * path). Alternatively, your platform may customize the header - * `psa/crypto_platform.h`, in which case it can skip or replace the - * inclusion of `"crypto_spe.h"`. - * - * Module: library/psa_crypto.c - * Requires: MBEDTLS_PSA_CRYPTO_C - * - */ -//#define MBEDTLS_PSA_CRYPTO_SPM - -/** - * Uncomment to enable p256-m. This is an alternative implementation of - * key generation, ECDH and (randomized) ECDSA on the curve SECP256R1. - * Compared to the default implementation: - * - * - p256-m has a much smaller code size and RAM footprint. - * - p256-m is only available via the PSA API. This includes the pk module - * when #MBEDTLS_USE_PSA_CRYPTO is enabled. - * - p256-m does not support deterministic ECDSA, EC-JPAKE, custom protocols - * over the core arithmetic, or deterministic derivation of keys. - * - * We recommend enabling this option if your application uses the PSA API - * and the only elliptic curve support it needs is ECDH and ECDSA over - * SECP256R1. - * - * If you enable this option, you do not need to enable any ECC-related - * MBEDTLS_xxx option. You do need to separately request support for the - * cryptographic mechanisms through the PSA API: - * - #MBEDTLS_PSA_CRYPTO_C and #MBEDTLS_PSA_CRYPTO_CONFIG for PSA-based - * configuration; - * - #MBEDTLS_USE_PSA_CRYPTO if you want to use p256-m from PK, X.509 or TLS; - * - #PSA_WANT_ECC_SECP_R1_256; - * - #PSA_WANT_ALG_ECDH and/or #PSA_WANT_ALG_ECDSA as needed; - * - #PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY, #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC, - * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT, - * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT and/or - * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE as needed. - * - * \note To benefit from the smaller code size of p256-m, make sure that you - * do not enable any ECC-related option not supported by p256-m: this - * would cause the built-in ECC implementation to be built as well, in - * order to provide the required option. - * Make sure #PSA_WANT_ALG_DETERMINISTIC_ECDSA, #PSA_WANT_ALG_JPAKE and - * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE, and curves other than - * SECP256R1 are disabled as they are not supported by this driver. - * Also, avoid defining #MBEDTLS_PK_PARSE_EC_COMPRESSED or - * #MBEDTLS_PK_PARSE_EC_EXTENDED as those currently require a subset of - * the built-in ECC implementation, see docs/driver-only-builds.md. - */ -//#define MBEDTLS_PSA_P256M_DRIVER_ENABLED - -/** - * \def MBEDTLS_PSA_INJECT_ENTROPY - * - * Enable support for entropy injection at first boot. This feature is - * required on systems that do not have a built-in entropy source (TRNG). - * This feature is currently not supported on systems that have a built-in - * entropy source. - * - * Requires: MBEDTLS_PSA_CRYPTO_STORAGE_C, MBEDTLS_ENTROPY_NV_SEED - * - */ -//#define MBEDTLS_PSA_INJECT_ENTROPY - -/** - * \def MBEDTLS_RSA_NO_CRT - * - * Do not use the Chinese Remainder Theorem - * for the RSA private operation. - * - * Uncomment this macro to disable the use of CRT in RSA. - * - */ -//#define MBEDTLS_RSA_NO_CRT - -/** - * \def MBEDTLS_SELF_TEST - * - * Enable the checkup functions (*_self_test). - */ -#define MBEDTLS_SELF_TEST - -/** - * \def MBEDTLS_SHA256_SMALLER - * - * Enable an implementation of SHA-256 that has lower ROM footprint but also - * lower performance. - * - * The default implementation is meant to be a reasonable compromise between - * performance and size. This version optimizes more aggressively for size at - * the expense of performance. Eg on Cortex-M4 it reduces the size of - * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about - * 30%. - * - * Uncomment to enable the smaller implementation of SHA256. - */ -//#define MBEDTLS_SHA256_SMALLER - -/** - * \def MBEDTLS_SHA512_SMALLER - * - * Enable an implementation of SHA-512 that has lower ROM footprint but also - * lower performance. - * - * Uncomment to enable the smaller implementation of SHA512. - */ -//#define MBEDTLS_SHA512_SMALLER - -/** - * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES - * - * Enable sending of alert messages in case of encountered errors as per RFC. - * If you choose not to send the alert messages, Mbed TLS can still communicate - * with other servers, only debugging of failures is harder. - * - * The advantage of not sending alert messages, is that no information is given - * about reasons for failures thus preventing adversaries of gaining intel. - * - * Enable sending of all alert messages - */ -#define MBEDTLS_SSL_ALL_ALERT_MESSAGES - -/** - * \def MBEDTLS_SSL_DTLS_CONNECTION_ID - * - * Enable support for the DTLS Connection ID (CID) extension, - * which allows to identify DTLS connections across changes - * in the underlying transport. The CID functionality is described - * in RFC 9146. - * - * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`, - * mbedtls_ssl_get_own_cid()`, `mbedtls_ssl_get_peer_cid()` and - * `mbedtls_ssl_conf_cid()`. See the corresponding documentation for - * more information. - * - * The maximum lengths of outgoing and incoming CIDs can be configured - * through the options - * - MBEDTLS_SSL_CID_OUT_LEN_MAX - * - MBEDTLS_SSL_CID_IN_LEN_MAX. - * - * Requires: MBEDTLS_SSL_PROTO_DTLS - * - * Uncomment to enable the Connection ID extension. - */ -#define MBEDTLS_SSL_DTLS_CONNECTION_ID - - -/** - * \def MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT - * - * Defines whether RFC 9146 (default) or the legacy version - * (version draft-ietf-tls-dtls-connection-id-05, - * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05) - * is used. - * - * Set the value to 0 for the standard version, and - * 1 for the legacy draft version. - * - * \deprecated Support for the legacy version of the DTLS - * Connection ID feature is deprecated. Please - * switch to the standardized version defined - * in RFC 9146 enabled by utilizing - * MBEDTLS_SSL_DTLS_CONNECTION_ID without use - * of MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT. - * - * Requires: MBEDTLS_SSL_DTLS_CONNECTION_ID - */ -#define MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT 0 - -/** - * \def MBEDTLS_SSL_ASYNC_PRIVATE - * - * Enable asynchronous external private key operations in SSL. This allows - * you to configure an SSL connection to call an external cryptographic - * module to perform private key operations instead of performing the - * operation inside the library. - * - * Requires: MBEDTLS_X509_CRT_PARSE_C - */ -//#define MBEDTLS_SSL_ASYNC_PRIVATE - -/** - * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION - * - * Enable serialization of the TLS context structures, through use of the - * functions mbedtls_ssl_context_save() and mbedtls_ssl_context_load(). - * - * This pair of functions allows one side of a connection to serialize the - * context associated with the connection, then free or re-use that context - * while the serialized state is persisted elsewhere, and finally deserialize - * that state to a live context for resuming read/write operations on the - * connection. From a protocol perspective, the state of the connection is - * unaffected, in particular this is entirely transparent to the peer. - * - * Note: this is distinct from TLS session resumption, which is part of the - * protocol and fully visible by the peer. TLS session resumption enables - * establishing new connections associated to a saved session with shorter, - * lighter handshakes, while context serialization is a local optimization in - * handling a single, potentially long-lived connection. - * - * Enabling these APIs makes some SSL structures larger, as 64 extra bytes are - * saved after the handshake to allow for more efficient serialization, so if - * you don't need this feature you'll save RAM by disabling it. - * - * Requires: MBEDTLS_GCM_C or MBEDTLS_CCM_C or MBEDTLS_CHACHAPOLY_C - * - * Comment to disable the context serialization APIs. - */ -#define MBEDTLS_SSL_CONTEXT_SERIALIZATION - -/** - * \def MBEDTLS_SSL_DEBUG_ALL - * - * Enable the debug messages in SSL module for all issues. - * Debug messages have been disabled in some places to prevent timing - * attacks due to (unbalanced) debugging function calls. - * - * If you need all error reporting you should enable this during debugging, - * but remove this for production servers that should log as well. - * - * Uncomment this macro to report all debug messages on errors introducing - * a timing side-channel. - * - */ -//#define MBEDTLS_SSL_DEBUG_ALL - -/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC - * - * Enable support for Encrypt-then-MAC, RFC 7366. - * - * This allows peers that both support it to use a more robust protection for - * ciphersuites using CBC, providing deep resistance against timing attacks - * on the padding or underlying cipher. - * - * This only affects CBC ciphersuites, and is useless if none is defined. - * - * Requires: MBEDTLS_SSL_PROTO_TLS1_2 - * - * Comment this macro to disable support for Encrypt-then-MAC - */ -#define MBEDTLS_SSL_ENCRYPT_THEN_MAC - -/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET - * - * Enable support for RFC 7627: Session Hash and Extended Master Secret - * Extension. - * - * This was introduced as "the proper fix" to the Triple Handshake family of - * attacks, but it is recommended to always use it (even if you disable - * renegotiation), since it actually fixes a more fundamental issue in the - * original SSL/TLS design, and has implications beyond Triple Handshake. - * - * Requires: MBEDTLS_SSL_PROTO_TLS1_2 - * - * Comment this macro to disable support for Extended Master Secret. - */ -#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET - -/** - * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE - * - * This option controls the availability of the API mbedtls_ssl_get_peer_cert() - * giving access to the peer's certificate after completion of the handshake. - * - * Unless you need mbedtls_ssl_peer_cert() in your application, it is - * recommended to disable this option for reduced RAM usage. - * - * \note If this option is disabled, mbedtls_ssl_get_peer_cert() is still - * defined, but always returns \c NULL. - * - * \note This option has no influence on the protection against the - * triple handshake attack. Even if it is disabled, Mbed TLS will - * still ensure that certificates do not change during renegotiation, - * for example by keeping a hash of the peer's certificate. - * - * \note This option is required if MBEDTLS_SSL_PROTO_TLS1_3 is set. - * - * Comment this macro to disable storing the peer's certificate - * after the handshake. - */ -#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE - -/** - * \def MBEDTLS_SSL_RENEGOTIATION - * - * Enable support for TLS renegotiation. - * - * The two main uses of renegotiation are (1) refresh keys on long-lived - * connections and (2) client authentication after the initial handshake. - * If you don't need renegotiation, it's probably better to disable it, since - * it has been associated with security issues in the past and is easy to - * misuse/misunderstand. - * - * Requires: MBEDTLS_SSL_PROTO_TLS1_2 - * - * Comment this to disable support for renegotiation. - * - * \note Even if this option is disabled, both client and server are aware - * of the Renegotiation Indication Extension (RFC 5746) used to - * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). - * (See \c mbedtls_ssl_conf_legacy_renegotiation for the - * configuration of this extension). - * - */ -#define MBEDTLS_SSL_RENEGOTIATION - -/** - * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH - * - * Enable support for RFC 6066 max_fragment_length extension in SSL. - * - * Comment this macro to disable support for the max_fragment_length extension - */ -#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH - -/** - * \def MBEDTLS_SSL_RECORD_SIZE_LIMIT - * - * Enable support for RFC 8449 record_size_limit extension in SSL (TLS 1.3 only). - * - * \warning This extension is currently in development and must NOT be used except - * for testing purposes. - * - * Requires: MBEDTLS_SSL_PROTO_TLS1_3 - * - * Uncomment this macro to enable support for the record_size_limit extension - */ -//#define MBEDTLS_SSL_RECORD_SIZE_LIMIT - -/** - * \def MBEDTLS_SSL_PROTO_TLS1_2 - * - * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). - * - * Requires: Without MBEDTLS_USE_PSA_CRYPTO: MBEDTLS_MD_C and - * (MBEDTLS_SHA256_C or MBEDTLS_SHA384_C or - * SHA-256 or SHA-512 provided by a PSA driver) - * With MBEDTLS_USE_PSA_CRYPTO: - * PSA_WANT_ALG_SHA_256 or PSA_WANT_ALG_SHA_384 - * - * \warning If building with MBEDTLS_USE_PSA_CRYPTO, or if the hash(es) used - * are only provided by PSA drivers, you must call psa_crypto_init() before - * doing any TLS operations. - * - * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 - */ -#define MBEDTLS_SSL_PROTO_TLS1_2 - -/** - * \def MBEDTLS_SSL_PROTO_TLS1_3 - * - * Enable support for TLS 1.3. - * - * \note See docs/architecture/tls13-support.md for a description of the TLS - * 1.3 support that this option enables. - * - * Requires: MBEDTLS_SSL_KEEP_PEER_CERTIFICATE - * Requires: MBEDTLS_PSA_CRYPTO_C - * - * \note TLS 1.3 uses PSA crypto for cryptographic operations that are - * directly performed by TLS 1.3 code. As a consequence, you must - * call psa_crypto_init() before the first TLS 1.3 handshake. - * - * \note Cryptographic operations performed indirectly via another module - * (X.509, PK) or by code shared with TLS 1.2 (record protection, - * running handshake hash) only use PSA crypto if - * #MBEDTLS_USE_PSA_CRYPTO is enabled. - * - * Uncomment this macro to enable the support for TLS 1.3. - */ -//#define MBEDTLS_SSL_PROTO_TLS1_3 - -/** - * \def MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE - * - * Enable TLS 1.3 middlebox compatibility mode. - * - * As specified in Section D.4 of RFC 8446, TLS 1.3 offers a compatibility - * mode to make a TLS 1.3 connection more likely to pass through middle boxes - * expecting TLS 1.2 traffic. - * - * Turning on the compatibility mode comes at the cost of a few added bytes - * on the wire, but it doesn't affect compatibility with TLS 1.3 implementations - * that don't use it. Therefore, unless transmission bandwidth is critical and - * you know that middlebox compatibility issues won't occur, it is therefore - * recommended to set this option. - * - * Comment to disable compatibility mode for TLS 1.3. If - * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any - * effect on the build. - * - */ -//#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE - -/** - * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED - * - * Enable TLS 1.3 PSK key exchange mode. - * - * Comment to disable support for the PSK key exchange mode in TLS 1.3. If - * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any - * effect on the build. - * - */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED - -/** - * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED - * - * Enable TLS 1.3 ephemeral key exchange mode. - * - * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH - * MBEDTLS_X509_CRT_PARSE_C - * and at least one of: - * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) - * MBEDTLS_PKCS1_V21 - * - * Comment to disable support for the ephemeral key exchange mode in TLS 1.3. - * If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any - * effect on the build. - * - */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED - -/** - * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED - * - * Enable TLS 1.3 PSK ephemeral key exchange mode. - * - * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH - * - * Comment to disable support for the PSK ephemeral key exchange mode in - * TLS 1.3. If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not - * have any effect on the build. - * - */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED - -/** - * \def MBEDTLS_SSL_EARLY_DATA - * - * Enable support for RFC 8446 TLS 1.3 early data. - * - * Requires: MBEDTLS_SSL_SESSION_TICKETS and either - * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED or - * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED - * - * Comment this to disable support for early data. If MBEDTLS_SSL_PROTO_TLS1_3 - * is not enabled, this option does not have any effect on the build. - * - * This feature is experimental, not completed and thus not ready for - * production. - * - * \note The maximum amount of early data can be set with - * MBEDTLS_SSL_MAX_EARLY_DATA_SIZE. - * - */ -//#define MBEDTLS_SSL_EARLY_DATA - -/** - * \def MBEDTLS_SSL_PROTO_DTLS - * - * Enable support for DTLS (all available versions). - * - * Enable this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. - * - * Requires: MBEDTLS_SSL_PROTO_TLS1_2 - * - * Comment this macro to disable support for DTLS - */ -#define MBEDTLS_SSL_PROTO_DTLS - -/** - * \def MBEDTLS_SSL_ALPN - * - * Enable support for RFC 7301 Application Layer Protocol Negotiation. - * - * Comment this macro to disable support for ALPN. - */ -#define MBEDTLS_SSL_ALPN - -/** - * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY - * - * Enable support for the anti-replay mechanism in DTLS. - * - * Requires: MBEDTLS_SSL_TLS_C - * MBEDTLS_SSL_PROTO_DTLS - * - * \warning Disabling this is often a security risk! - * See mbedtls_ssl_conf_dtls_anti_replay() for details. - * - * Comment this to disable anti-replay in DTLS. - */ -#define MBEDTLS_SSL_DTLS_ANTI_REPLAY - -/** - * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY - * - * Enable support for HelloVerifyRequest on DTLS servers. - * - * This feature is highly recommended to prevent DTLS servers being used as - * amplifiers in DoS attacks against other hosts. It should always be enabled - * unless you know for sure amplification cannot be a problem in the - * environment in which your server operates. - * - * \warning Disabling this can be a security risk! (see above) - * - * Requires: MBEDTLS_SSL_PROTO_DTLS - * - * Comment this to disable support for HelloVerifyRequest. - */ -#define MBEDTLS_SSL_DTLS_HELLO_VERIFY - -/** - * \def MBEDTLS_SSL_DTLS_SRTP - * - * Enable support for negotiation of DTLS-SRTP (RFC 5764) - * through the use_srtp extension. - * - * \note This feature provides the minimum functionality required - * to negotiate the use of DTLS-SRTP and to allow the derivation of - * the associated SRTP packet protection key material. - * In particular, the SRTP packet protection itself, as well as the - * demultiplexing of RTP and DTLS packets at the datagram layer - * (see Section 5 of RFC 5764), are not handled by this feature. - * Instead, after successful completion of a handshake negotiating - * the use of DTLS-SRTP, the extended key exporter API - * mbedtls_ssl_conf_export_keys_cb() should be used to implement - * the key exporter described in Section 4.2 of RFC 5764 and RFC 5705 - * (this is implemented in the SSL example programs). - * The resulting key should then be passed to an SRTP stack. - * - * Setting this option enables the runtime API - * mbedtls_ssl_conf_dtls_srtp_protection_profiles() - * through which the supported DTLS-SRTP protection - * profiles can be configured. You must call this API at - * runtime if you wish to negotiate the use of DTLS-SRTP. - * - * Requires: MBEDTLS_SSL_PROTO_DTLS - * - * Uncomment this to enable support for use_srtp extension. - */ -//#define MBEDTLS_SSL_DTLS_SRTP - -/** - * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE - * - * Enable server-side support for clients that reconnect from the same port. - * - * Some clients unexpectedly close the connection and try to reconnect using the - * same source port. This needs special support from the server to handle the - * new connection securely, as described in section 4.2.8 of RFC 6347. This - * flag enables that support. - * - * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY - * - * Comment this to disable support for clients reusing the source port. - */ -#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE - -/** - * \def MBEDTLS_SSL_SESSION_TICKETS - * - * Enable support for RFC 5077 session tickets in SSL. - * Client-side, provides full support for session tickets (maintenance of a - * session store remains the responsibility of the application, though). - * Server-side, you also need to provide callbacks for writing and parsing - * tickets, including authenticated encryption and key management. Example - * callbacks are provided by MBEDTLS_SSL_TICKET_C. - * - * Comment this macro to disable support for SSL session tickets - */ -#define MBEDTLS_SSL_SESSION_TICKETS - -/** - * \def MBEDTLS_SSL_SERVER_NAME_INDICATION - * - * Enable support for RFC 6066 server name indication (SNI) in SSL. - * - * Requires: MBEDTLS_X509_CRT_PARSE_C - * - * Comment this macro to disable support for server name indication in SSL - */ -#define MBEDTLS_SSL_SERVER_NAME_INDICATION - -/** - * \def MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH - * - * When this option is enabled, the SSL buffer will be resized automatically - * based on the negotiated maximum fragment length in each direction. - * - * Requires: MBEDTLS_SSL_MAX_FRAGMENT_LENGTH - */ -//#define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH - -/** - * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN - * - * Enable testing of the constant-flow nature of some sensitive functions with - * clang's MemorySanitizer. This causes some existing tests to also test - * this non-functional property of the code under test. - * - * This setting requires compiling with clang -fsanitize=memory. The test - * suites can then be run normally. - * - * \warning This macro is only used for extended testing; it is not considered - * part of the library's API, so it may change or disappear at any time. - * - * Uncomment to enable testing of the constant-flow nature of selected code. - */ -//#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN - -/** - * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND - * - * Enable testing of the constant-flow nature of some sensitive functions with - * valgrind's memcheck tool. This causes some existing tests to also test - * this non-functional property of the code under test. - * - * This setting requires valgrind headers for building, and is only useful for - * testing if the tests suites are run with valgrind's memcheck. This can be - * done for an individual test suite with 'valgrind ./test_suite_xxx', or when - * using CMake, this can be done for all test suites with 'make memcheck'. - * - * \warning This macro is only used for extended testing; it is not considered - * part of the library's API, so it may change or disappear at any time. - * - * Uncomment to enable testing of the constant-flow nature of selected code. - */ -//#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND - -/** - * \def MBEDTLS_TEST_HOOKS - * - * Enable features for invasive testing such as introspection functions and - * hooks for fault injection. This enables additional unit tests. - * - * Merely enabling this feature should not change the behavior of the product. - * It only adds new code, and new branching points where the default behavior - * is the same as when this feature is disabled. - * However, this feature increases the attack surface: there is an added - * risk of vulnerabilities, and more gadgets that can make exploits easier. - * Therefore this feature must never be enabled in production. - * - * See `docs/architecture/testing/mbed-crypto-invasive-testing.md` for more - * information. - * - * Uncomment to enable invasive tests. - */ -//#define MBEDTLS_TEST_HOOKS - -/** - * \def MBEDTLS_THREADING_ALT - * - * Provide your own alternate threading implementation. - * - * Requires: MBEDTLS_THREADING_C - * - * Uncomment this to allow your own alternate threading implementation. - */ -//#define MBEDTLS_THREADING_ALT - -/** - * \def MBEDTLS_THREADING_PTHREAD - * - * Enable the pthread wrapper layer for the threading layer. - * - * Requires: MBEDTLS_THREADING_C - * - * Uncomment this to enable pthread mutexes. - */ -//#define MBEDTLS_THREADING_PTHREAD - -/** - * \def MBEDTLS_USE_PSA_CRYPTO - * - * Make the X.509 and TLS libraries use PSA for cryptographic operations as - * much as possible, and enable new APIs for using keys handled by PSA Crypto. - * - * \note Development of this option is currently in progress, and parts of Mbed - * TLS's X.509 and TLS modules are not ported to PSA yet. However, these parts - * will still continue to work as usual, so enabling this option should not - * break backwards compatibility. - * - * \warning If you enable this option, you need to call `psa_crypto_init()` - * before calling any function from the SSL/TLS, X.509 or PK modules, except - * for the various mbedtls_xxx_init() functions which can be called at any time. - * - * \note An important and desirable effect of this option is that it allows - * PK, X.509 and TLS to take advantage of PSA drivers. For example, enabling - * this option is what allows use of drivers for ECDSA, ECDH and EC J-PAKE in - * those modules. However, note that even with this option disabled, some code - * in PK, X.509, TLS or the crypto library might still use PSA drivers, if it - * can determine it's safe to do so; currently that's the case for hashes. - * - * \note See docs/use-psa-crypto.md for a complete description this option. - * - * Requires: MBEDTLS_PSA_CRYPTO_C. - * - * Uncomment this to enable internal use of PSA Crypto and new associated APIs. - */ -//#define MBEDTLS_USE_PSA_CRYPTO - -/** - * \def MBEDTLS_PSA_CRYPTO_CONFIG - * - * This setting allows support for cryptographic mechanisms through the PSA - * API to be configured separately from support through the mbedtls API. - * - * When this option is disabled, the PSA API exposes the cryptographic - * mechanisms that can be implemented on top of the `mbedtls_xxx` API - * configured with `MBEDTLS_XXX` symbols. - * - * When this option is enabled, the PSA API exposes the cryptographic - * mechanisms requested by the `PSA_WANT_XXX` symbols defined in - * include/psa/crypto_config.h. The corresponding `MBEDTLS_XXX` settings are - * automatically enabled if required (i.e. if no PSA driver provides the - * mechanism). You may still freely enable additional `MBEDTLS_XXX` symbols - * in mbedtls_config.h. - * - * If the symbol #MBEDTLS_PSA_CRYPTO_CONFIG_FILE is defined, it specifies - * an alternative header to include instead of include/psa/crypto_config.h. - * - * \warning This option is experimental, in that the set of `PSA_WANT_XXX` - * symbols is not completely finalized yet, and the configuration - * tooling is not ideally adapted to having two separate configuration - * files. - * Future minor releases of Mbed TLS may make minor changes to those - * symbols, but we will endeavor to provide a transition path. - * Nonetheless, this option is considered mature enough to use in - * production, as long as you accept that you may need to make - * minor changes to psa/crypto_config.h when upgrading Mbed TLS. - */ -//#define MBEDTLS_PSA_CRYPTO_CONFIG - -/** - * \def MBEDTLS_VERSION_FEATURES - * - * Allow run-time checking of compile-time enabled features. Thus allowing users - * to check at run-time if the library is for instance compiled with threading - * support via mbedtls_version_check_feature(). - * - * Requires: MBEDTLS_VERSION_C - * - * Comment this to disable run-time checking and save ROM space - */ -#define MBEDTLS_VERSION_FEATURES - -/** - * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK - * - * If set, this enables the X.509 API `mbedtls_x509_crt_verify_with_ca_cb()` - * and the SSL API `mbedtls_ssl_conf_ca_cb()` which allow users to configure - * the set of trusted certificates through a callback instead of a linked - * list. - * - * This is useful for example in environments where a large number of trusted - * certificates is present and storing them in a linked list isn't efficient - * enough, or when the set of trusted certificates changes frequently. - * - * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and - * `mbedtls_ssl_conf_ca_cb()` for more information. - * - * Requires: MBEDTLS_X509_CRT_PARSE_C - * - * Uncomment to enable trusted certificate callbacks. - */ -//#define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK - -/** - * \def MBEDTLS_X509_REMOVE_INFO - * - * Disable mbedtls_x509_*_info() and related APIs. - * - * Uncomment to omit mbedtls_x509_*_info(), as well as mbedtls_debug_print_crt() - * and other functions/constants only used by these functions, thus reducing - * the code footprint by several KB. - */ -//#define MBEDTLS_X509_REMOVE_INFO - -/** - * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT - * - * Enable parsing and verification of X.509 certificates, CRLs and CSRS - * signed with RSASSA-PSS (aka PKCS#1 v2.1). - * - * Comment this macro to disallow using RSASSA-PSS in certificates. - */ -#define MBEDTLS_X509_RSASSA_PSS_SUPPORT -/** \} name SECTION: Mbed TLS feature support */ - -/** - * \name SECTION: Mbed TLS modules - * - * This section enables or disables entire modules in Mbed TLS - * \{ - */ - -/** - * \def MBEDTLS_AESNI_C - * - * Enable AES-NI support on x86-64 or x86-32. - * - * \note AESNI is only supported with certain compilers and target options: - * - Visual Studio 2013: supported. - * - GCC, x86-64, target not explicitly supporting AESNI: - * requires MBEDTLS_HAVE_ASM. - * - GCC, x86-32, target not explicitly supporting AESNI: - * not supported. - * - GCC, x86-64 or x86-32, target supporting AESNI: supported. - * For this assembly-less implementation, you must currently compile - * `library/aesni.c` and `library/aes.c` with machine options to enable - * SSE2 and AESNI instructions: `gcc -msse2 -maes -mpclmul` or - * `clang -maes -mpclmul`. - * - Non-x86 targets: this option is silently ignored. - * - Other compilers: this option is silently ignored. - * - * \note - * Above, "GCC" includes compatible compilers such as Clang. - * The limitations on target support are likely to be relaxed in the future. - * - * Module: library/aesni.c - * Caller: library/aes.c - * - * Requires: MBEDTLS_HAVE_ASM (on some platforms, see note) - * - * This modules adds support for the AES-NI instructions on x86. - */ -#define MBEDTLS_AESNI_C - -/** - * \def MBEDTLS_AESCE_C - * - * Enable AES cryptographic extension support on 64-bit Arm. - * - * Module: library/aesce.c - * Caller: library/aes.c - * - * Requires: MBEDTLS_AES_C - * - * \warning Runtime detection only works on Linux. For non-Linux operating - * system, Armv8-A Cryptographic Extensions must be supported by - * the CPU when this option is enabled. - * - * \note Minimum compiler versions for this feature are Clang 4.0, - * armclang 6.6, GCC 6.0 or MSVC 2019 version 16.11.2. - * - * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for - * armclang <= 6.9 - * - * This module adds support for the AES Armv8-A Cryptographic Extensions on Aarch64 systems. - */ -#define MBEDTLS_AESCE_C - -/** - * \def MBEDTLS_AES_C - * - * Enable the AES block cipher. - * - * Module: library/aes.c - * Caller: library/cipher.c - * library/pem.c - * library/ctr_drbg.c - * - * This module enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA - * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 - * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 - * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA - * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 - * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 - * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA - * - * PEM_PARSE uses AES for decrypting encrypted keys. - */ -#define MBEDTLS_AES_C - -/** - * \def MBEDTLS_ASN1_PARSE_C - * - * Enable the generic ASN1 parser. - * - * Module: library/asn1.c - * Caller: library/x509.c - * library/dhm.c - * library/pkcs12.c - * library/pkcs5.c - * library/pkparse.c - */ -#define MBEDTLS_ASN1_PARSE_C - -/** - * \def MBEDTLS_ASN1_WRITE_C - * - * Enable the generic ASN1 writer. - * - * Module: library/asn1write.c - * Caller: library/ecdsa.c - * library/pkwrite.c - * library/x509_create.c - * library/x509write_crt.c - * library/x509write_csr.c - */ -#define MBEDTLS_ASN1_WRITE_C - -/** - * \def MBEDTLS_BASE64_C - * - * Enable the Base64 module. - * - * Module: library/base64.c - * Caller: library/pem.c - * - * This module is required for PEM support (required by X.509). - */ -#define MBEDTLS_BASE64_C - -/** - * \def MBEDTLS_BIGNUM_C - * - * Enable the multi-precision integer library. - * - * Module: library/bignum.c - * library/bignum_core.c - * library/bignum_mod.c - * library/bignum_mod_raw.c - * Caller: library/dhm.c - * library/ecp.c - * library/ecdsa.c - * library/rsa.c - * library/rsa_alt_helpers.c - * library/ssl_tls.c - * - * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support. - */ -#define MBEDTLS_BIGNUM_C - -/** - * \def MBEDTLS_CAMELLIA_C - * - * Enable the Camellia block cipher. - * - * Module: library/camellia.c - * Caller: library/cipher.c - * - * This module enables the following ciphersuites (if other requisites are - * enabled as well): - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 - * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 - */ -#define MBEDTLS_CAMELLIA_C - -/** - * \def MBEDTLS_ARIA_C - * - * Enable the ARIA block cipher. - * - * Module: library/aria.c - * Caller: library/cipher.c - * - * This module enables the following ciphersuites (if other requisites are - * enabled as well): - * - * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 - * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 - * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 - * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 - * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 - */ -#define MBEDTLS_ARIA_C - -/** - * \def MBEDTLS_CCM_C - * - * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher. - * - * Module: library/ccm.c - * - * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C or - * MBEDTLS_ARIA_C - * - * This module enables the AES-CCM ciphersuites, if other requisites are - * enabled as well. - */ -#define MBEDTLS_CCM_C - -/** - * \def MBEDTLS_CHACHA20_C - * - * Enable the ChaCha20 stream cipher. - * - * Module: library/chacha20.c - */ -#define MBEDTLS_CHACHA20_C - -/** - * \def MBEDTLS_CHACHAPOLY_C - * - * Enable the ChaCha20-Poly1305 AEAD algorithm. - * - * Module: library/chachapoly.c - * - * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C - */ -#define MBEDTLS_CHACHAPOLY_C - -/** - * \def MBEDTLS_CIPHER_C - * - * Enable the generic cipher layer. - * - * Module: library/cipher.c - * Caller: library/ccm.c - * library/cmac.c - * library/gcm.c - * library/nist_kw.c - * library/pkcs12.c - * library/pkcs5.c - * library/psa_crypto_aead.c - * library/psa_crypto_mac.c - * library/ssl_ciphersuites.c - * library/ssl_msg.c - * library/ssl_ticket.c (unless MBEDTLS_USE_PSA_CRYPTO is enabled) - * - * Uncomment to enable generic cipher wrappers. - */ -#define MBEDTLS_CIPHER_C - -/** - * \def MBEDTLS_CMAC_C - * - * Enable the CMAC (Cipher-based Message Authentication Code) mode for block - * ciphers. - * - * \note When #MBEDTLS_CMAC_ALT is active, meaning that the underlying - * implementation of the CMAC algorithm is provided by an alternate - * implementation, that alternate implementation may opt to not support - * AES-192 or 3DES as underlying block ciphers for the CMAC operation. - * - * Module: library/cmac.c - * - * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_DES_C - * - */ -#define MBEDTLS_CMAC_C - -/** - * \def MBEDTLS_CTR_DRBG_C - * - * Enable the CTR_DRBG AES-based random generator. - * The CTR_DRBG generator uses AES-256 by default. - * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above. - * - * \note AES-128 will be used if \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. - * - * \note To achieve a 256-bit security strength with CTR_DRBG, - * you must use AES-256 *and* use sufficient entropy. - * See ctr_drbg.h for more details. - * - * Module: library/ctr_drbg.c - * Caller: - * - * Requires: MBEDTLS_AES_C - * - * This module provides the CTR_DRBG AES random number generator. - */ -#define MBEDTLS_CTR_DRBG_C - -/** - * \def MBEDTLS_DEBUG_C - * - * Enable the debug functions. - * - * Module: library/debug.c - * Caller: library/ssl_msg.c - * library/ssl_tls.c - * library/ssl_tls12_*.c - * library/ssl_tls13_*.c - * - * This module provides debugging functions. - */ -#define MBEDTLS_DEBUG_C - -/** - * \def MBEDTLS_DES_C - * - * Enable the DES block cipher. - * - * Module: library/des.c - * Caller: library/pem.c - * library/cipher.c - * - * PEM_PARSE uses DES/3DES for decrypting encrypted keys. - * - * \warning DES/3DES are considered weak ciphers and their use constitutes a - * security risk. We recommend considering stronger ciphers instead. - */ -#define MBEDTLS_DES_C - -/** - * \def MBEDTLS_DHM_C - * - * Enable the Diffie-Hellman-Merkle module. - * - * Module: library/dhm.c - * Caller: library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * This module is used by the following key exchanges: - * DHE-RSA, DHE-PSK - * - * \warning Using DHE constitutes a security risk as it - * is not possible to validate custom DH parameters. - * If possible, it is recommended users should consider - * preferring other methods of key exchange. - * See dhm.h for more details. - * - */ -#define MBEDTLS_DHM_C - -/** - * \def MBEDTLS_ECDH_C - * - * Enable the elliptic curve Diffie-Hellman library. - * - * Module: library/ecdh.c - * Caller: library/psa_crypto.c - * library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * This module is used by the following key exchanges: - * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK - * - * Requires: MBEDTLS_ECP_C - */ -#define MBEDTLS_ECDH_C - -/** - * \def MBEDTLS_ECDSA_C - * - * Enable the elliptic curve DSA library. - * - * Module: library/ecdsa.c - * Caller: - * - * This module is used by the following key exchanges: - * ECDHE-ECDSA - * - * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C, - * and at least one MBEDTLS_ECP_DP_XXX_ENABLED for a - * short Weierstrass curve. - */ -#define MBEDTLS_ECDSA_C - -/** - * \def MBEDTLS_ECJPAKE_C - * - * Enable the elliptic curve J-PAKE library. - * - * \note EC J-PAKE support is based on the Thread v1.0.0 specification. - * It has not been reviewed for compliance with newer standards such as - * Thread v1.1 or RFC 8236. - * - * Module: library/ecjpake.c - * Caller: - * - * This module is used by the following key exchanges: - * ECJPAKE - * - * Requires: MBEDTLS_ECP_C and either MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C - * - * \warning If using a hash that is only provided by PSA drivers, you must - * call psa_crypto_init() before doing any EC J-PAKE operations. - */ -#define MBEDTLS_ECJPAKE_C - -/** - * \def MBEDTLS_ECP_C - * - * Enable the elliptic curve over GF(p) library. - * - * Module: library/ecp.c - * Caller: library/ecdh.c - * library/ecdsa.c - * library/ecjpake.c - * - * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED - */ -#define MBEDTLS_ECP_C - -/** - * \def MBEDTLS_ENTROPY_C - * - * Enable the platform-specific entropy code. - * - * Module: library/entropy.c - * Caller: - * - * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C - * - * This module provides a generic entropy pool - */ -#define MBEDTLS_ENTROPY_C - -/** - * \def MBEDTLS_ERROR_C - * - * Enable error code to error string conversion. - * - * Module: library/error.c - * Caller: - * - * This module enables mbedtls_strerror(). - */ -#define MBEDTLS_ERROR_C - -/** - * \def MBEDTLS_GCM_C - * - * Enable the Galois/Counter Mode (GCM). - * - * Module: library/gcm.c - * - * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C or - * MBEDTLS_ARIA_C - * - * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other - * requisites are enabled as well. - */ -#define MBEDTLS_GCM_C - -/** - * \def MBEDTLS_HKDF_C - * - * Enable the HKDF algorithm (RFC 5869). - * - * Module: library/hkdf.c - * Caller: - * - * Requires: MBEDTLS_MD_C - * - * This module adds support for the Hashed Message Authentication Code - * (HMAC)-based key derivation function (HKDF). - */ -#define MBEDTLS_HKDF_C - -/** - * \def MBEDTLS_HMAC_DRBG_C - * - * Enable the HMAC_DRBG random generator. - * - * Module: library/hmac_drbg.c - * Caller: - * - * Requires: MBEDTLS_MD_C - * - * Uncomment to enable the HMAC_DRBG random number generator. - */ -#define MBEDTLS_HMAC_DRBG_C - -/** - * \def MBEDTLS_LMS_C - * - * Enable the LMS stateful-hash asymmetric signature algorithm. - * - * Module: library/lms.c - * Caller: - * - * Requires: MBEDTLS_PSA_CRYPTO_C - * - * Uncomment to enable the LMS verification algorithm and public key operations. - */ -#define MBEDTLS_LMS_C - -/** - * \def MBEDTLS_LMS_PRIVATE - * - * Enable LMS private-key operations and signing code. Functions enabled by this - * option are experimental, and should not be used in production. - * - * Requires: MBEDTLS_LMS_C - * - * Uncomment to enable the LMS signature algorithm and private key operations. - */ -//#define MBEDTLS_LMS_PRIVATE - -/** - * \def MBEDTLS_NIST_KW_C - * - * Enable the Key Wrapping mode for 128-bit block ciphers, - * as defined in NIST SP 800-38F. Only KW and KWP modes - * are supported. At the moment, only AES is approved by NIST. - * - * Module: library/nist_kw.c - * - * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C - */ -#define MBEDTLS_NIST_KW_C - -/** - * \def MBEDTLS_MD_C - * - * Enable the generic layer for message digest (hashing) and HMAC. - * - * Requires: one of: MBEDTLS_MD5_C, MBEDTLS_RIPEMD160_C, MBEDTLS_SHA1_C, - * MBEDTLS_SHA224_C, MBEDTLS_SHA256_C, MBEDTLS_SHA384_C, - * MBEDTLS_SHA512_C, or MBEDTLS_PSA_CRYPTO_C with at least - * one hash. - * Module: library/md.c - * Caller: library/constant_time.c - * library/ecdsa.c - * library/ecjpake.c - * library/hkdf.c - * library/hmac_drbg.c - * library/pk.c - * library/pkcs5.c - * library/pkcs12.c - * library/psa_crypto_ecp.c - * library/psa_crypto_rsa.c - * library/rsa.c - * library/ssl_cookie.c - * library/ssl_msg.c - * library/ssl_tls.c - * library/x509.c - * library/x509_crt.c - * library/x509write_crt.c - * library/x509write_csr.c - * - * Uncomment to enable generic message digest wrappers. - */ -#define MBEDTLS_MD_C - -/** - * \def MBEDTLS_MD5_C - * - * Enable the MD5 hash algorithm. - * - * Module: library/md5.c - * Caller: library/md.c - * library/pem.c - * library/ssl_tls.c - * - * This module is required for TLS 1.2 depending on the handshake parameters. - * Further, it is used for checking MD5-signed certificates, and for PBKDF1 - * when decrypting PEM-encoded encrypted keys. - * - * \warning MD5 is considered a weak message digest and its use constitutes a - * security risk. If possible, we recommend avoiding dependencies on - * it, and considering stronger message digests instead. - * - */ -#define MBEDTLS_MD5_C - -/** - * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C - * - * Enable the buffer allocator implementation that makes use of a (stack) - * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() - * calls) - * - * Module: library/memory_buffer_alloc.c - * - * Requires: MBEDTLS_PLATFORM_C - * MBEDTLS_PLATFORM_MEMORY (to use it within Mbed TLS) - * - * Enable this module to enable the buffer memory allocator. - */ -//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C - -/** - * \def MBEDTLS_NET_C - * - * Enable the TCP and UDP over IPv6/IPv4 networking routines. - * - * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) - * and Windows. For other platforms, you'll want to disable it, and write your - * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). - * - * \note See also our Knowledge Base article about porting to a new - * environment: - * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS - * - * Module: library/net_sockets.c - * - * This module provides networking routines. - */ -#define MBEDTLS_NET_C - -/** - * \def MBEDTLS_OID_C - * - * Enable the OID database. - * - * Module: library/oid.c - * Caller: library/asn1write.c - * library/pkcs5.c - * library/pkparse.c - * library/pkwrite.c - * library/rsa.c - * library/x509.c - * library/x509_create.c - * library/x509_crl.c - * library/x509_crt.c - * library/x509_csr.c - * library/x509write_crt.c - * library/x509write_csr.c - * - * This modules translates between OIDs and internal values. - */ -#define MBEDTLS_OID_C - -/** - * \def MBEDTLS_PADLOCK_C - * - * Enable VIA Padlock support on x86. - * - * Module: library/padlock.c - * Caller: library/aes.c - * - * Requires: MBEDTLS_HAVE_ASM - * - * This modules adds support for the VIA PadLock on x86. - */ -#define MBEDTLS_PADLOCK_C - -/** - * \def MBEDTLS_PEM_PARSE_C - * - * Enable PEM decoding / parsing. - * - * Module: library/pem.c - * Caller: library/dhm.c - * library/pkparse.c - * library/x509_crl.c - * library/x509_crt.c - * library/x509_csr.c - * - * Requires: MBEDTLS_BASE64_C - * optionally MBEDTLS_MD5_C, or PSA Crypto with MD5 (see below) - * - * \warning When parsing password-protected files, if MD5 is provided only by - * a PSA driver, you must call psa_crypto_init() before the first file. - * - * This modules adds support for decoding / parsing PEM files. - */ -#define MBEDTLS_PEM_PARSE_C - -/** - * \def MBEDTLS_PEM_WRITE_C - * - * Enable PEM encoding / writing. - * - * Module: library/pem.c - * Caller: library/pkwrite.c - * library/x509write_crt.c - * library/x509write_csr.c - * - * Requires: MBEDTLS_BASE64_C - * - * This modules adds support for encoding / writing PEM files. - */ -#define MBEDTLS_PEM_WRITE_C - -/** - * \def MBEDTLS_PK_C - * - * Enable the generic public (asymmetric) key layer. - * - * Module: library/pk.c - * Caller: library/psa_crypto_rsa.c - * library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * library/x509.c - * - * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C or MBEDTLS_ECP_C - * - * Uncomment to enable generic public key wrappers. - */ -#define MBEDTLS_PK_C - -/** - * \def MBEDTLS_PK_PARSE_C - * - * Enable the generic public (asymmetric) key parser. - * - * Module: library/pkparse.c - * Caller: library/x509_crt.c - * library/x509_csr.c - * - * Requires: MBEDTLS_PK_C - * - * Uncomment to enable generic public key parse functions. - */ -#define MBEDTLS_PK_PARSE_C - -/** - * \def MBEDTLS_PK_WRITE_C - * - * Enable the generic public (asymmetric) key writer. - * - * Module: library/pkwrite.c - * Caller: library/x509write.c - * - * Requires: MBEDTLS_PK_C - * - * Uncomment to enable generic public key write functions. - */ -#define MBEDTLS_PK_WRITE_C - -/** - * \def MBEDTLS_PKCS5_C - * - * Enable PKCS#5 functions. - * - * Module: library/pkcs5.c - * - * Requires: MBEDTLS_CIPHER_C - * Auto-enables: MBEDTLS_MD_C - * - * \warning If using a hash that is only provided by PSA drivers, you must - * call psa_crypto_init() before doing any PKCS5 operations. - * - * This module adds support for the PKCS#5 functions. - */ -#define MBEDTLS_PKCS5_C - -/** - * \def MBEDTLS_PKCS7_C - * - * Enable PKCS #7 core for using PKCS #7-formatted signatures. - * RFC Link - https://tools.ietf.org/html/rfc2315 - * - * Module: library/pkcs7.c - * - * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, - * MBEDTLS_X509_CRT_PARSE_C MBEDTLS_X509_CRL_PARSE_C, - * MBEDTLS_BIGNUM_C, MBEDTLS_MD_C - * - * This module is required for the PKCS #7 parsing modules. - */ -#define MBEDTLS_PKCS7_C - -/** - * \def MBEDTLS_PKCS12_C - * - * Enable PKCS#12 PBE functions. - * Adds algorithms for parsing PKCS#8 encrypted private keys - * - * Module: library/pkcs12.c - * Caller: library/pkparse.c - * - * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C and either - * MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C. - * - * \warning If using a hash that is only provided by PSA drivers, you must - * call psa_crypto_init() before doing any PKCS12 operations. - * - * This module enables PKCS#12 functions. - */ -#define MBEDTLS_PKCS12_C - -/** - * \def MBEDTLS_PLATFORM_C - * - * Enable the platform abstraction layer that allows you to re-assign - * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). - * - * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT - * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned - * above to be specified at runtime or compile time respectively. - * - * \note This abstraction layer must be enabled on Windows (including MSYS2) - * as other modules rely on it for a fixed snprintf implementation. - * - * Module: library/platform.c - * Caller: Most other .c files - * - * This module enables abstraction of common (libc) functions. - */ -#define MBEDTLS_PLATFORM_C - -/** - * \def MBEDTLS_POLY1305_C - * - * Enable the Poly1305 MAC algorithm. - * - * Module: library/poly1305.c - * Caller: library/chachapoly.c - */ -#define MBEDTLS_POLY1305_C - -/** - * \def MBEDTLS_PSA_CRYPTO_C - * - * Enable the Platform Security Architecture cryptography API. - * - * Module: library/psa_crypto.c - * - * Requires: MBEDTLS_CIPHER_C, - * either MBEDTLS_CTR_DRBG_C and MBEDTLS_ENTROPY_C, - * or MBEDTLS_HMAC_DRBG_C and MBEDTLS_ENTROPY_C, - * or MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. - * - */ -#define MBEDTLS_PSA_CRYPTO_C - -/** - * \def MBEDTLS_PSA_CRYPTO_SE_C - * - * Enable dynamic secure element support in the Platform Security Architecture - * cryptography API. - * - * \deprecated This feature is deprecated. Please switch to the PSA driver - * interface. - * - * Module: library/psa_crypto_se.c - * - * Requires: MBEDTLS_PSA_CRYPTO_C, MBEDTLS_PSA_CRYPTO_STORAGE_C - * - */ -//#define MBEDTLS_PSA_CRYPTO_SE_C - -/** - * \def MBEDTLS_PSA_CRYPTO_STORAGE_C - * - * Enable the Platform Security Architecture persistent key storage. - * - * Module: library/psa_crypto_storage.c - * - * Requires: MBEDTLS_PSA_CRYPTO_C, - * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of - * the PSA ITS interface - */ -#define MBEDTLS_PSA_CRYPTO_STORAGE_C - -/** - * \def MBEDTLS_PSA_ITS_FILE_C - * - * Enable the emulation of the Platform Security Architecture - * Internal Trusted Storage (PSA ITS) over files. - * - * Module: library/psa_its_file.c - * - * Requires: MBEDTLS_FS_IO - */ -#define MBEDTLS_PSA_ITS_FILE_C - -/** - * \def MBEDTLS_RIPEMD160_C - * - * Enable the RIPEMD-160 hash algorithm. - * - * Module: library/ripemd160.c - * Caller: library/md.c - * - */ -#define MBEDTLS_RIPEMD160_C - -/** - * \def MBEDTLS_RSA_C - * - * Enable the RSA public-key cryptosystem. - * - * Module: library/rsa.c - * library/rsa_alt_helpers.c - * Caller: library/pk.c - * library/psa_crypto.c - * library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * This module is used by the following key exchanges: - * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK - * - * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C - */ -#define MBEDTLS_RSA_C - -/** - * \def MBEDTLS_SHA1_C - * - * Enable the SHA1 cryptographic hash algorithm. - * - * Module: library/sha1.c - * Caller: library/md.c - * library/psa_crypto_hash.c - * - * This module is required for TLS 1.2 depending on the handshake parameters, - * and for SHA1-signed certificates. - * - * \warning SHA-1 is considered a weak message digest and its use constitutes - * a security risk. If possible, we recommend avoiding dependencies - * on it, and considering stronger message digests instead. - * - */ -#define MBEDTLS_SHA1_C - -/** - * \def MBEDTLS_SHA224_C - * - * Enable the SHA-224 cryptographic hash algorithm. - * - * Module: library/sha256.c - * Caller: library/md.c - * library/ssl_cookie.c - * - * This module adds support for SHA-224. - */ -#define MBEDTLS_SHA224_C - -/** - * \def MBEDTLS_SHA256_C - * - * Enable the SHA-256 cryptographic hash algorithm. - * - * Module: library/sha256.c - * Caller: library/entropy.c - * library/md.c - * library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * This module adds support for SHA-256. - * This module is required for the SSL/TLS 1.2 PRF function. - */ -#define MBEDTLS_SHA256_C - -/** - * \def MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT - * - * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms - * with the ARMv8 cryptographic extensions if they are available at runtime. - * If not, the library will fall back to the C implementation. - * - * \note If MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT is defined when building - * for a non-Aarch64 build it will be silently ignored. - * - * \note Minimum compiler versions for this feature are Clang 4.0, - * armclang 6.6 or GCC 6.0. - * - * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for - * armclang <= 6.9 - * - * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the - * same time as MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY. - * - * Requires: MBEDTLS_SHA256_C. - * - * Module: library/sha256.c - * - * Uncomment to have the library check for the A64 SHA-256 crypto extensions - * and use them if available. - */ -//#define MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT - -/** - * \def MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY - * - * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms - * with the ARMv8 cryptographic extensions, which must be available at runtime - * or else an illegal instruction fault will occur. - * - * \note This allows builds with a smaller code size than with - * MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT - * - * \note Minimum compiler versions for this feature are Clang 4.0, - * armclang 6.6 or GCC 6.0. - * - * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for - * armclang <= 6.9 - * - * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY cannot be defined at the same - * time as MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT. - * - * Requires: MBEDTLS_SHA256_C. - * - * Module: library/sha256.c - * - * Uncomment to have the library use the A64 SHA-256 crypto extensions - * unconditionally. - */ -//#define MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY - -/** - * \def MBEDTLS_SHA384_C - * - * Enable the SHA-384 cryptographic hash algorithm. - * - * Module: library/sha512.c - * Caller: library/md.c - * library/psa_crypto_hash.c - * library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * Comment to disable SHA-384 - */ -#define MBEDTLS_SHA384_C - -/** - * \def MBEDTLS_SHA512_C - * - * Enable SHA-512 cryptographic hash algorithms. - * - * Module: library/sha512.c - * Caller: library/entropy.c - * library/md.c - * library/ssl_tls.c - * library/ssl_cookie.c - * - * This module adds support for SHA-512. - */ -#define MBEDTLS_SHA512_C - -/** - * \def MBEDTLS_SHA3_C - * - * Enable the SHA3 cryptographic hash algorithm. - * - * Module: library/sha3.c - * - * This module adds support for SHA3. - */ -#define MBEDTLS_SHA3_C - -/** - * \def MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT - * - * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms - * with the ARMv8 cryptographic extensions if they are available at runtime. - * If not, the library will fall back to the C implementation. - * - * \note If MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT is defined when building - * for a non-Aarch64 build it will be silently ignored. - * - * \note Minimum compiler versions for this feature are Clang 7.0, - * armclang 6.9 or GCC 8.0. - * - * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for - * armclang 6.9 - * - * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the - * same time as MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY. - * - * Requires: MBEDTLS_SHA512_C. - * - * Module: library/sha512.c - * - * Uncomment to have the library check for the A64 SHA-512 crypto extensions - * and use them if available. - */ -//#define MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT - -/** - * \def MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY - * - * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms - * with the ARMv8 cryptographic extensions, which must be available at runtime - * or else an illegal instruction fault will occur. - * - * \note This allows builds with a smaller code size than with - * MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT - * - * \note Minimum compiler versions for this feature are Clang 7.0, - * armclang 6.9 or GCC 8.0. - * - * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for - * armclang 6.9 - * - * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY cannot be defined at the same - * time as MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT. - * - * Requires: MBEDTLS_SHA512_C. - * - * Module: library/sha512.c - * - * Uncomment to have the library use the A64 SHA-512 crypto extensions - * unconditionally. - */ -//#define MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY - -/** - * \def MBEDTLS_SSL_CACHE_C - * - * Enable simple SSL cache implementation. - * - * Module: library/ssl_cache.c - * Caller: - * - * Requires: MBEDTLS_SSL_CACHE_C - */ -#define MBEDTLS_SSL_CACHE_C - -/** - * \def MBEDTLS_SSL_COOKIE_C - * - * Enable basic implementation of DTLS cookies for hello verification. - * - * Module: library/ssl_cookie.c - * Caller: - */ -#define MBEDTLS_SSL_COOKIE_C - -/** - * \def MBEDTLS_SSL_TICKET_C - * - * Enable an implementation of TLS server-side callbacks for session tickets. - * - * Module: library/ssl_ticket.c - * Caller: - * - * Requires: (MBEDTLS_CIPHER_C || MBEDTLS_USE_PSA_CRYPTO) && - * (MBEDTLS_GCM_C || MBEDTLS_CCM_C || MBEDTLS_CHACHAPOLY_C) - */ -#define MBEDTLS_SSL_TICKET_C - -/** - * \def MBEDTLS_SSL_CLI_C - * - * Enable the SSL/TLS client code. - * - * Module: library/ssl*_client.c - * Caller: - * - * Requires: MBEDTLS_SSL_TLS_C - * - * This module is required for SSL/TLS client support. - */ -#define MBEDTLS_SSL_CLI_C - -/** - * \def MBEDTLS_SSL_SRV_C - * - * Enable the SSL/TLS server code. - * - * Module: library/ssl*_server.c - * Caller: - * - * Requires: MBEDTLS_SSL_TLS_C - * - * This module is required for SSL/TLS server support. - */ -#define MBEDTLS_SSL_SRV_C - -/** - * \def MBEDTLS_SSL_TLS_C - * - * Enable the generic SSL/TLS code. - * - * Module: library/ssl_tls.c - * Caller: library/ssl*_client.c - * library/ssl*_server.c - * - * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C - * and at least one of the MBEDTLS_SSL_PROTO_XXX defines - * - * This module is required for SSL/TLS. - */ -#define MBEDTLS_SSL_TLS_C - -/** - * \def MBEDTLS_THREADING_C - * - * Enable the threading abstraction layer. - * By default Mbed TLS assumes it is used in a non-threaded environment or that - * contexts are not shared between threads. If you do intend to use contexts - * between threads, you will need to enable this layer to prevent race - * conditions. See also our Knowledge Base article about threading: - * https://mbed-tls.readthedocs.io/en/latest/kb/development/thread-safety-and-multi-threading - * - * Module: library/threading.c - * - * This allows different threading implementations (self-implemented or - * provided). - * - * You will have to enable either MBEDTLS_THREADING_ALT or - * MBEDTLS_THREADING_PTHREAD. - * - * Enable this layer to allow use of mutexes within Mbed TLS - */ -//#define MBEDTLS_THREADING_C - -/** - * \def MBEDTLS_TIMING_C - * - * Enable the semi-portable timing interface. - * - * \note The provided implementation only works on POSIX/Unix (including Linux, - * BSD and OS X) and Windows. On other platforms, you can either disable that - * module and provide your own implementations of the callbacks needed by - * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide - * your own implementation of the whole module by setting - * \c MBEDTLS_TIMING_ALT in the current file. - * - * \note The timing module will include time.h on suitable platforms - * regardless of the setting of MBEDTLS_HAVE_TIME, unless - * MBEDTLS_TIMING_ALT is used. See timing.c for more information. - * - * \note See also our Knowledge Base article about porting to a new - * environment: - * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS - * - * Module: library/timing.c - */ -#define MBEDTLS_TIMING_C - -/** - * \def MBEDTLS_VERSION_C - * - * Enable run-time version information. - * - * Module: library/version.c - * - * This module provides run-time version information. - */ -#define MBEDTLS_VERSION_C - -/** - * \def MBEDTLS_X509_USE_C - * - * Enable X.509 core for using certificates. - * - * Module: library/x509.c - * Caller: library/x509_crl.c - * library/x509_crt.c - * library/x509_csr.c - * - * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, - * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) - * - * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call - * psa_crypto_init() before doing any X.509 operation. - * - * This module is required for the X.509 parsing modules. - */ -#define MBEDTLS_X509_USE_C - -/** - * \def MBEDTLS_X509_CRT_PARSE_C - * - * Enable X.509 certificate parsing. - * - * Module: library/x509_crt.c - * Caller: library/ssl_tls.c - * library/ssl*_client.c - * library/ssl*_server.c - * - * Requires: MBEDTLS_X509_USE_C - * - * This module is required for X.509 certificate parsing. - */ -#define MBEDTLS_X509_CRT_PARSE_C - -/** - * \def MBEDTLS_X509_CRL_PARSE_C - * - * Enable X.509 CRL parsing. - * - * Module: library/x509_crl.c - * Caller: library/x509_crt.c - * - * Requires: MBEDTLS_X509_USE_C - * - * This module is required for X.509 CRL parsing. - */ -#define MBEDTLS_X509_CRL_PARSE_C - -/** - * \def MBEDTLS_X509_CSR_PARSE_C - * - * Enable X.509 Certificate Signing Request (CSR) parsing. - * - * Module: library/x509_csr.c - * Caller: library/x509_crt_write.c - * - * Requires: MBEDTLS_X509_USE_C - * - * This module is used for reading X.509 certificate request. - */ -#define MBEDTLS_X509_CSR_PARSE_C - -/** - * \def MBEDTLS_X509_CREATE_C - * - * Enable X.509 core for creating certificates. - * - * Module: library/x509_create.c - * - * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, - * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) - * - * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call - * psa_crypto_init() before doing any X.509 create operation. - * - * This module is the basis for creating X.509 certificates and CSRs. - */ -#define MBEDTLS_X509_CREATE_C - -/** - * \def MBEDTLS_X509_CRT_WRITE_C - * - * Enable creating X.509 certificates. - * - * Module: library/x509_crt_write.c - * - * Requires: MBEDTLS_X509_CREATE_C - * - * This module is required for X.509 certificate creation. - */ -#define MBEDTLS_X509_CRT_WRITE_C - -/** - * \def MBEDTLS_X509_CSR_WRITE_C - * - * Enable creating X.509 Certificate Signing Requests (CSR). - * - * Module: library/x509_csr_write.c - * - * Requires: MBEDTLS_X509_CREATE_C - * - * This module is required for X.509 certificate request writing. - */ -#define MBEDTLS_X509_CSR_WRITE_C - -/** \} name SECTION: Mbed TLS modules */ - -/** - * \name SECTION: General configuration options - * - * This section contains Mbed TLS build settings that are not associated - * with a particular module. - * - * \{ - */ - -/** - * \def MBEDTLS_CONFIG_FILE - * - * If defined, this is a header which will be included instead of - * `"mbedtls/mbedtls_config.h"`. - * This header file specifies the compile-time configuration of Mbed TLS. - * Unlike other configuration options, this one must be defined on the - * compiler command line: a definition in `mbedtls_config.h` would have - * no effect. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_CONFIG_FILE "mbedtls/mbedtls_config.h" - -/** - * \def MBEDTLS_USER_CONFIG_FILE - * - * If defined, this is a header which will be included after - * `"mbedtls/mbedtls_config.h"` or #MBEDTLS_CONFIG_FILE. - * This allows you to modify the default configuration, including the ability - * to undefine options that are enabled by default. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_USER_CONFIG_FILE "/dev/null" - -/** - * \def MBEDTLS_PSA_CRYPTO_CONFIG_FILE - * - * If defined, this is a header which will be included instead of - * `"psa/crypto_config.h"`. - * This header file specifies which cryptographic mechanisms are available - * through the PSA API when #MBEDTLS_PSA_CRYPTO_CONFIG is enabled, and - * is not used when #MBEDTLS_PSA_CRYPTO_CONFIG is disabled. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_PSA_CRYPTO_CONFIG_FILE "psa/crypto_config.h" - -/** - * \def MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE - * - * If defined, this is a header which will be included after - * `"psa/crypto_config.h"` or #MBEDTLS_PSA_CRYPTO_CONFIG_FILE. - * This allows you to modify the default configuration, including the ability - * to undefine options that are enabled by default. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE "/dev/null" - -/** - * \def MBEDTLS_PSA_CRYPTO_PLATFORM_FILE - * - * If defined, this is a header which will be included instead of - * `"psa/crypto_platform.h"`. This file should declare the same identifiers - * as the one in Mbed TLS, but with definitions adapted to the platform on - * which the library code will run. - * - * \note The required content of this header can vary from one version of - * Mbed TLS to the next. Integrators who provide an alternative file - * should review the changes in the original file whenever they - * upgrade Mbed TLS. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_PSA_CRYPTO_PLATFORM_FILE "psa/crypto_platform_alt.h" - -/** - * \def MBEDTLS_PSA_CRYPTO_STRUCT_FILE - * - * If defined, this is a header which will be included instead of - * `"psa/crypto_struct.h"`. This file should declare the same identifiers - * as the one in Mbed TLS, but with definitions adapted to the environment - * in which the library code will run. The typical use for this feature - * is to provide alternative type definitions on the client side in - * client-server integrations of PSA crypto, where operation structures - * contain handles instead of cryptographic data. - * - * \note The required content of this header can vary from one version of - * Mbed TLS to the next. Integrators who provide an alternative file - * should review the changes in the original file whenever they - * upgrade Mbed TLS. - * - * This macro is expanded after an \#include directive. This is a popular but - * non-standard feature of the C language, so this feature is only available - * with compilers that perform macro expansion on an \#include line. - * - * The value of this symbol is typically a path in double quotes, either - * absolute or relative to a directory on the include search path. - */ -//#define MBEDTLS_PSA_CRYPTO_STRUCT_FILE "psa/crypto_struct_alt.h" - -/** \} name SECTION: General configuration options */ - -/** - * \name SECTION: Module configuration options - * - * This section allows for the setting of module specific sizes and - * configuration options. The default values are already present in the - * relevant header files and should suffice for the regular use cases. - * - * Our advice is to enable options and change their values here - * only if you have a good reason and know the consequences. - * \{ - */ -/* The Doxygen documentation here is used when a user comments out a - * setting and runs doxygen themselves. On the other hand, when we typeset - * the full documentation including disabled settings, the documentation - * in specific modules' header files is used if present. When editing this - * file, make sure that each option is documented in exactly one place, - * plus optionally a same-line Doxygen comment here if there is a Doxygen - * comment in the specific module. */ - -/* MPI / BIGNUM options */ -//#define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ -//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ - -/* CTR_DRBG options */ -//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ -//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ -//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ -//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ -//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ - -/* HMAC_DRBG options */ -//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ -//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ -//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ -//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ - -/* ECP options */ -//#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */ -//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ - -/* Entropy options */ -//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ -//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ -//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ - -/* Memory buffer allocator options */ -//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ - -/* Platform options */ -//#define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ - -/** \def MBEDTLS_PLATFORM_STD_CALLOC - * - * Default allocator to use, can be undefined. - * It must initialize the allocated buffer memory to zeroes. - * The size of the buffer is the product of the two parameters. - * The calloc function returns either a null pointer or a pointer to the allocated space. - * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid input to the deallocation function. - * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details. - * The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. - */ -//#define MBEDTLS_PLATFORM_STD_CALLOC calloc - -/** \def MBEDTLS_PLATFORM_STD_FREE - * - * Default free to use, can be undefined. - * NULL is a valid parameter, and the function must do nothing. - * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. - * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. - * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC apply). - */ -//#define MBEDTLS_PLATFORM_STD_FREE free -//#define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ -//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ -/* Note: your snprintf must correctly zero-terminate the buffer! */ -//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ -//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ - -/* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ -/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ -//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ -//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ -//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ -//#define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ -//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ -//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ -//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ -//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ -/* Note: your snprintf must correctly zero-terminate the buffer! */ -//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ -//#define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf /**< Default vsnprintf macro to use, can be undefined */ -//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ -//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ -//#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ -//#define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ - -/** \def MBEDTLS_CHECK_RETURN - * - * This macro is used at the beginning of the declaration of a function - * to indicate that its return value should be checked. It should - * instruct the compiler to emit a warning or an error if the function - * is called without checking its return value. - * - * There is a default implementation for popular compilers in platform_util.h. - * You can override the default implementation by defining your own here. - * - * If the implementation here is empty, this will effectively disable the - * checking of functions' return values. - */ -//#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) - -/** \def MBEDTLS_IGNORE_RETURN - * - * This macro requires one argument, which should be a C function call. - * If that function call would cause a #MBEDTLS_CHECK_RETURN warning, this - * warning is suppressed. - */ -//#define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) - -/* PSA options */ -/** - * Use HMAC_DRBG with the specified hash algorithm for HMAC_DRBG for the - * PSA crypto subsystem. - * - * If this option is unset: - * - If CTR_DRBG is available, the PSA subsystem uses it rather than HMAC_DRBG. - * - Otherwise, the PSA subsystem uses HMAC_DRBG with either - * #MBEDTLS_MD_SHA512 or #MBEDTLS_MD_SHA256 based on availability and - * on unspecified heuristics. - */ -//#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 - -/** \def MBEDTLS_PSA_KEY_SLOT_COUNT - * Restrict the PSA library to supporting a maximum amount of simultaneously - * loaded keys. A loaded key is a key stored by the PSA Crypto core as a - * volatile key, or a persistent key which is loaded temporarily by the - * library as part of a crypto operation in flight. - * - * If this option is unset, the library will fall back to a default value of - * 32 keys. - */ -//#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 - -/* RSA OPTIONS */ -//#define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits (Minimum possible value is 128 bits) */ - -/* SSL Cache options */ -//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ -//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ - -/* SSL options */ - -/** \def MBEDTLS_SSL_IN_CONTENT_LEN - * - * Maximum length (in bytes) of incoming plaintext fragments. - * - * This determines the size of the incoming TLS I/O buffer in such a way - * that it is capable of holding the specified amount of plaintext data, - * regardless of the protection mechanism used. - * - * \note When using a value less than the default of 16KB on the client, it is - * recommended to use the Maximum Fragment Length (MFL) extension to - * inform the server about this limitation. On the server, there - * is no supported, standardized way of informing the client about - * restriction on the maximum size of incoming messages, and unless - * the limitation has been communicated by other means, it is recommended - * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN - * while keeping the default value of 16KB for the incoming buffer. - * - * Uncomment to set the maximum plaintext size of the incoming I/O buffer. - */ -//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 - -/** \def MBEDTLS_SSL_CID_IN_LEN_MAX - * - * The maximum length of CIDs used for incoming DTLS messages. - * - */ -//#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 - -/** \def MBEDTLS_SSL_CID_OUT_LEN_MAX - * - * The maximum length of CIDs used for outgoing DTLS messages. - * - */ -//#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 - -/** \def MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY - * - * This option controls the use of record plaintext padding - * in TLS 1.3 and when using the Connection ID extension in DTLS 1.2. - * - * The padding will always be chosen so that the length of the - * padded plaintext is a multiple of the value of this option. - * - * Note: A value of \c 1 means that no padding will be used - * for outgoing records. - * - * Note: On systems lacking division instructions, - * a power of two should be preferred. - */ -//#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 - -/** \def MBEDTLS_SSL_OUT_CONTENT_LEN - * - * Maximum length (in bytes) of outgoing plaintext fragments. - * - * This determines the size of the outgoing TLS I/O buffer in such a way - * that it is capable of holding the specified amount of plaintext data, - * regardless of the protection mechanism used. - * - * It is possible to save RAM by setting a smaller outward buffer, while keeping - * the default inward 16384 byte buffer to conform to the TLS specification. - * - * The minimum required outward buffer size is determined by the handshake - * protocol's usage. Handshaking will fail if the outward buffer is too small. - * The specific size requirement depends on the configured ciphers and any - * certificate data which is sent during the handshake. - * - * Uncomment to set the maximum plaintext size of the outgoing I/O buffer. - */ -//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 - -/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING - * - * Maximum number of heap-allocated bytes for the purpose of - * DTLS handshake message reassembly and future message buffering. - * - * This should be at least 9/8 * MBEDTLS_SSL_IN_CONTENT_LEN - * to account for a reassembled handshake message of maximum size, - * together with its reassembly bitmap. - * - * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) - * should be sufficient for all practical situations as it allows - * to reassembly a large handshake message (such as a certificate) - * while buffering multiple smaller handshake messages. - * - */ -//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 - -//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) */ -//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ - -/** - * Complete list of ciphersuites to use, in order of preference. - * - * \warning No dependency checking is done on that field! This option can only - * be used to restrict the set of available ciphersuites. It is your - * responsibility to make sure the needed modules are active. - * - * Use this to save a few hundred bytes of ROM (default ordering of all - * available ciphersuites) and a few to a few hundred bytes of RAM. - * - * The value below is only an example, not the default. - */ -//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 - -/** - * \def MBEDTLS_SSL_MAX_EARLY_DATA_SIZE - * - * The default maximum amount of 0-RTT data. See the documentation of - * \c mbedtls_ssl_tls13_conf_max_early_data_size() for more information. - * - * It must be positive and smaller than UINT32_MAX. - * - * If MBEDTLS_SSL_EARLY_DATA is not defined, this default value does not - * have any impact on the build. - * - * This feature is experimental, not completed and thus not ready for - * production. - * - */ -//#define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 - -/** - * \def MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE - * - * Maximum time difference in milliseconds tolerated between the age of a - * ticket from the server and client point of view. - * From the client point of view, the age of a ticket is the time difference - * between the time when the client proposes to the server to use the ticket - * (time of writing of the Pre-Shared Key Extension including the ticket) and - * the time the client received the ticket from the server. - * From the server point of view, the age of a ticket is the time difference - * between the time when the server receives a proposition from the client - * to use the ticket and the time when the ticket was created by the server. - * The server age is expected to be always greater than the client one and - * MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE defines the - * maximum difference tolerated for the server to accept the ticket. - * This is not used in TLS 1.2. - * - */ -//#define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 - -/** - * \def MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH - * - * Size in bytes of a ticket nonce. This is not used in TLS 1.2. - * - * This must be less than 256. - */ -//#define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 - -/** - * \def MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS - * - * Default number of NewSessionTicket messages to be sent by a TLS 1.3 server - * after handshake completion. This is not used in TLS 1.2 and relevant only if - * the MBEDTLS_SSL_SESSION_TICKETS option is enabled. - * - */ -//#define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 - -/* X509 options */ -//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ -//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ - -/** \} name SECTION: Module configuration options */ +/** + * \file mbedtls_config.h + * + * \brief Configuration options (set of defines) + * + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * This is an optional version symbol that enables compatibility handling of + * config files. + * + * It is equal to the #MBEDTLS_VERSION_NUMBER of the Mbed TLS version that + * introduced the config format we want to be compatible with. + */ +//#define MBEDTLS_CONFIG_VERSION 0x03000000 + +/** + * \name SECTION: System support + * + * This section sets system specific settings. + * \{ + */ + +/** + * \def MBEDTLS_HAVE_ASM + * + * The compiler has support for asm(). + * + * Requires support for asm() in compiler. + * + * Used in: + * library/aesni.h + * library/aria.c + * library/bn_mul.h + * library/constant_time.c + * library/padlock.h + * + * Required by: + * MBEDTLS_AESCE_C + * MBEDTLS_AESNI_C (on some platforms) + * MBEDTLS_PADLOCK_C + * + * Comment to disable the use of assembly code. + */ +#define MBEDTLS_HAVE_ASM + +/** + * \def MBEDTLS_NO_UDBL_DIVISION + * + * The platform lacks support for double-width integer division (64-bit + * division on a 32-bit platform, 128-bit division on a 64-bit platform). + * + * Used in: + * include/mbedtls/bignum.h + * library/bignum.c + * + * The bignum code uses double-width division to speed up some operations. + * Double-width division is often implemented in software that needs to + * be linked with the program. The presence of a double-width integer + * type is usually detected automatically through preprocessor macros, + * but the automatic detection cannot know whether the code needs to + * and can be linked with an implementation of division for that type. + * By default division is assumed to be usable if the type is present. + * Uncomment this option to prevent the use of double-width division. + * + * Note that division for the native integer type is always required. + * Furthermore, a 64-bit type is always required even on a 32-bit + * platform, but it need not support multiplication or division. In some + * cases it is also desirable to disable some double-width operations. For + * example, if double-width division is implemented in software, disabling + * it can reduce code size in some embedded targets. + */ +//#define MBEDTLS_NO_UDBL_DIVISION + +/** + * \def MBEDTLS_NO_64BIT_MULTIPLICATION + * + * The platform lacks support for 32x32 -> 64-bit multiplication. + * + * Used in: + * library/poly1305.c + * + * Some parts of the library may use multiplication of two unsigned 32-bit + * operands with a 64-bit result in order to speed up computations. On some + * platforms, this is not available in hardware and has to be implemented in + * software, usually in a library provided by the toolchain. + * + * Sometimes it is not desirable to have to link to that library. This option + * removes the dependency of that library on platforms that lack a hardware + * 64-bit multiplier by embedding a software implementation in Mbed TLS. + * + * Note that depending on the compiler, this may decrease performance compared + * to using the library function provided by the toolchain. + */ +//#define MBEDTLS_NO_64BIT_MULTIPLICATION + +/** + * \def MBEDTLS_HAVE_SSE2 + * + * CPU supports SSE2 instruction set. + * + * Uncomment if the CPU supports SSE2 (IA-32 specific). + */ +//#define MBEDTLS_HAVE_SSE2 + +/** + * \def MBEDTLS_HAVE_TIME + * + * System has time.h and time(). + * The time does not need to be correct, only time differences are used, + * by contrast with MBEDTLS_HAVE_TIME_DATE + * + * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, + * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and + * MBEDTLS_PLATFORM_STD_TIME. + * + * Comment if your system does not support time functions. + * + * \note If MBEDTLS_TIMING_C is set - to enable the semi-portable timing + * interface - timing.c will include time.h on suitable platforms + * regardless of the setting of MBEDTLS_HAVE_TIME, unless + * MBEDTLS_TIMING_ALT is used. See timing.c for more information. + */ +#define MBEDTLS_HAVE_TIME + +/** + * \def MBEDTLS_HAVE_TIME_DATE + * + * System has time.h, time(), and an implementation for + * mbedtls_platform_gmtime_r() (see below). + * The time needs to be correct (not necessarily very accurate, but at least + * the date should be correct). This is used to verify the validity period of + * X.509 certificates. + * + * Comment if your system does not have a correct clock. + * + * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that + * behaves similarly to the gmtime_r() function from the C standard. Refer to + * the documentation for mbedtls_platform_gmtime_r() for more information. + * + * \note It is possible to configure an implementation for + * mbedtls_platform_gmtime_r() at compile-time by using the macro + * MBEDTLS_PLATFORM_GMTIME_R_ALT. + */ +#define MBEDTLS_HAVE_TIME_DATE + +/** + * \def MBEDTLS_PLATFORM_MEMORY + * + * Enable the memory allocation layer. + * + * By default Mbed TLS uses the system-provided calloc() and free(). + * This allows different allocators (self-implemented or provided) to be + * provided to the platform abstraction layer. + * + * Enabling #MBEDTLS_PLATFORM_MEMORY without the + * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide + * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and + * free() function pointer at runtime. + * + * Enabling #MBEDTLS_PLATFORM_MEMORY and specifying + * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the + * alternate function at compile time. + * + * An overview of how the value of mbedtls_calloc is determined: + * + * - if !MBEDTLS_PLATFORM_MEMORY + * - mbedtls_calloc = calloc + * - if MBEDTLS_PLATFORM_MEMORY + * - if (MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - mbedtls_calloc = MBEDTLS_PLATFORM_CALLOC_MACRO + * - if !(MBEDTLS_PLATFORM_CALLOC_MACRO && MBEDTLS_PLATFORM_FREE_MACRO): + * - Dynamic setup via mbedtls_platform_set_calloc_free is now possible with a default value MBEDTLS_PLATFORM_STD_CALLOC. + * - How is MBEDTLS_PLATFORM_STD_CALLOC handled? + * - if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - MBEDTLS_PLATFORM_STD_CALLOC is not set to anything; + * - MBEDTLS_PLATFORM_STD_MEM_HDR can be included if present; + * - if !MBEDTLS_PLATFORM_NO_STD_FUNCTIONS: + * - if MBEDTLS_PLATFORM_STD_CALLOC is present: + * - User-defined MBEDTLS_PLATFORM_STD_CALLOC is respected; + * - if !MBEDTLS_PLATFORM_STD_CALLOC: + * - MBEDTLS_PLATFORM_STD_CALLOC = calloc + * + * - At this point the presence of MBEDTLS_PLATFORM_STD_CALLOC is checked. + * - if !MBEDTLS_PLATFORM_STD_CALLOC + * - MBEDTLS_PLATFORM_STD_CALLOC = uninitialized_calloc + * + * - mbedtls_calloc = MBEDTLS_PLATFORM_STD_CALLOC. + * + * Defining MBEDTLS_PLATFORM_CALLOC_MACRO and #MBEDTLS_PLATFORM_STD_CALLOC at the same time is not possible. + * MBEDTLS_PLATFORM_CALLOC_MACRO and MBEDTLS_PLATFORM_FREE_MACRO must both be defined or undefined at the same time. + * #MBEDTLS_PLATFORM_STD_CALLOC and #MBEDTLS_PLATFORM_STD_FREE do not have to be defined at the same time, as, if they are used, + * dynamic setup of these functions is possible. See the tree above to see how are they handled in all cases. + * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. + * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Enable this layer to allow use of alternative memory allocators. + */ +//#define MBEDTLS_PLATFORM_MEMORY + +/** + * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + * + * Do not assign standard functions in the platform layer (e.g. calloc() to + * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) + * + * This makes sure there are no linking errors on platforms that do not support + * these functions. You will HAVE to provide alternatives, either at runtime + * via the platform_set_xxx() functions or at compile time by setting + * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a + * MBEDTLS_PLATFORM_XXX_MACRO. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Uncomment to prevent default assignment of standard functions in the + * platform layer. + */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +/** + * \def MBEDTLS_PLATFORM_EXIT_ALT + * + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let Mbed TLS support the + * function in the platform abstraction layer. + * + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, Mbed TLS will + * provide a function "mbedtls_platform_set_printf()" that allows you to set an + * alternative printf function pointer. + * + * All these define require MBEDTLS_PLATFORM_C to be defined! + * + * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; + * it will be enabled automatically by check_config.h + * + * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as + * MBEDTLS_PLATFORM_XXX_MACRO! + * + * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME + * + * Uncomment a macro to enable alternate implementation of specific base + * platform function + */ +//#define MBEDTLS_PLATFORM_SETBUF_ALT +//#define MBEDTLS_PLATFORM_EXIT_ALT +//#define MBEDTLS_PLATFORM_TIME_ALT +//#define MBEDTLS_PLATFORM_FPRINTF_ALT +//#define MBEDTLS_PLATFORM_PRINTF_ALT +//#define MBEDTLS_PLATFORM_SNPRINTF_ALT +//#define MBEDTLS_PLATFORM_VSNPRINTF_ALT +//#define MBEDTLS_PLATFORM_NV_SEED_ALT +//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT +//#define MBEDTLS_PLATFORM_MS_TIME_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +//#define MBEDTLS_PLATFORM_GMTIME_R_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(), to wipe sensitive data in memory. This replaces + * the default implementation in platform_util.c. + * + * By default, the library uses a system function such as memset_s() + * (optional feature of C11), explicit_bzero() (BSD and compatible), or + * SecureZeroMemory (Windows). If no such function is detected, the library + * falls back to a plain C implementation. Compilers are technically + * permitted to optimize this implementation out, meaning that the memory is + * not actually wiped. The library tries to prevent that, but the C language + * makes it impossible to guarantee that the memory will always be wiped. + * + * If your platform provides a guaranteed method to wipe memory which + * `platform_util.c` does not detect, define this macro to the name of + * a function that takes two arguments, a `void *` pointer and a length, + * and wipes that many bytes starting at the specified address. For example, + * if your platform has explicit_bzero() but `platform_util.c` does not + * detect its presence, define `MBEDTLS_PLATFORM_ZEROIZE_ALT` to be + * `explicit_bzero` to use that function as mbedtls_platform_zeroize(). + */ +//#define MBEDTLS_PLATFORM_ZEROIZE_ALT + +/** + * \def MBEDTLS_DEPRECATED_WARNING + * + * Mark deprecated functions and features so that they generate a warning if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * This only works with GCC and Clang. With other compilers, you may want to + * use MBEDTLS_DEPRECATED_REMOVED + * + * Uncomment to get warnings on using deprecated functions and features. + */ +//#define MBEDTLS_DEPRECATED_WARNING + +/** + * \def MBEDTLS_DEPRECATED_REMOVED + * + * Remove deprecated functions and features so that they generate an error if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * Uncomment to get errors on using deprecated functions and features. + */ +//#define MBEDTLS_DEPRECATED_REMOVED + +/** \} name SECTION: System support */ + +/** + * \name SECTION: Mbed TLS feature support + * + * This section sets support for features that are or are not needed + * within the modules that are enabled. + * \{ + */ + +/** + * \def MBEDTLS_TIMING_ALT + * + * Uncomment to provide your own alternate implementation for + * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() + * + * Only works if you have MBEDTLS_TIMING_C enabled. + * + * You will need to provide a header "timing_alt.h" and an implementation at + * compile time. + */ +//#define MBEDTLS_TIMING_ALT + +/** + * \def MBEDTLS_AES_ALT + * + * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let Mbed TLS use your + * alternate core implementation of a symmetric crypto, an arithmetic or hash + * module (e.g. platform specific assembly optimized implementations). Keep + * in mind that the function prototypes should remain the same. + * + * This replaces the whole module. If you only want to replace one of the + * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_AES_ALT, Mbed TLS will no longer + * provide the "struct mbedtls_aes_context" definition and omit the base + * function declarations and implementations. "aes_alt.h" will be included from + * "aes.h" to include the new function definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * module. + * + * \warning MD5, DES and SHA-1 are considered weak and their + * use constitutes a security risk. If possible, we recommend + * avoiding dependencies on them, and considering stronger message + * digests and ciphers instead. + * + */ +//#define MBEDTLS_AES_ALT +//#define MBEDTLS_ARIA_ALT +//#define MBEDTLS_CAMELLIA_ALT +//#define MBEDTLS_CCM_ALT +//#define MBEDTLS_CHACHA20_ALT +//#define MBEDTLS_CHACHAPOLY_ALT +//#define MBEDTLS_CMAC_ALT +//#define MBEDTLS_DES_ALT +//#define MBEDTLS_DHM_ALT +//#define MBEDTLS_ECJPAKE_ALT +//#define MBEDTLS_GCM_ALT +//#define MBEDTLS_NIST_KW_ALT +//#define MBEDTLS_MD5_ALT +//#define MBEDTLS_POLY1305_ALT +//#define MBEDTLS_RIPEMD160_ALT +//#define MBEDTLS_RSA_ALT +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT + +/* + * When replacing the elliptic curve module, please consider, that it is + * implemented with two .c files: + * - ecp.c + * - ecp_curves.c + * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT + * macros as described above. The only difference is that you have to make sure + * that you provide functionality for both .c files. + */ +//#define MBEDTLS_ECP_ALT + +/** + * \def MBEDTLS_SHA256_PROCESS_ALT + * + * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use you + * alternate core implementation of symmetric crypto or hash function. Keep in + * mind that function prototypes should remain the same. + * + * This replaces only one function. The header file from Mbed TLS is still + * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, Mbed TLS will + * no longer provide the mbedtls_sha1_process() function, but it will still provide + * the other function (using your mbedtls_sha1_process() function) and the definition + * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible + * with this definition. + * + * \note If you use the AES_xxx_ALT macros, then it is recommended to also set + * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES + * tables. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + * + * \warning MD5, DES and SHA-1 are considered weak and their use + * constitutes a security risk. If possible, we recommend avoiding + * dependencies on them, and considering stronger message digests + * and ciphers instead. + * + * \warning If both MBEDTLS_ECDSA_SIGN_ALT and MBEDTLS_ECDSA_DETERMINISTIC are + * enabled, then the deterministic ECDH signature functions pass the + * the static HMAC-DRBG as RNG to mbedtls_ecdsa_sign(). Therefore + * alternative implementations should use the RNG only for generating + * the ephemeral key and nothing else. If this is not possible, then + * MBEDTLS_ECDSA_DETERMINISTIC should be disabled and an alternative + * implementation should be provided for mbedtls_ecdsa_sign_det_ext(). + * + */ +//#define MBEDTLS_MD5_PROCESS_ALT +//#define MBEDTLS_RIPEMD160_PROCESS_ALT +//#define MBEDTLS_SHA1_PROCESS_ALT +//#define MBEDTLS_SHA256_PROCESS_ALT +//#define MBEDTLS_SHA512_PROCESS_ALT +//#define MBEDTLS_DES_SETKEY_ALT +//#define MBEDTLS_DES_CRYPT_ECB_ALT +//#define MBEDTLS_DES3_CRYPT_ECB_ALT +//#define MBEDTLS_AES_SETKEY_ENC_ALT +//#define MBEDTLS_AES_SETKEY_DEC_ALT +//#define MBEDTLS_AES_ENCRYPT_ALT +//#define MBEDTLS_AES_DECRYPT_ALT +//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT +//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT +//#define MBEDTLS_ECDSA_VERIFY_ALT +//#define MBEDTLS_ECDSA_SIGN_ALT +//#define MBEDTLS_ECDSA_GENKEY_ALT + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * + * Expose a part of the internal interface of the Elliptic Curve Point module. + * + * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let Mbed TLS use your + * alternative core implementation of elliptic curve arithmetic. Keep in mind + * that function prototypes should remain the same. + * + * This partially replaces one function. The header file from Mbed TLS is still + * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation + * is still present and it is used for group structures not supported by the + * alternative. + * + * The original implementation can in addition be removed by setting the + * MBEDTLS_ECP_NO_FALLBACK option, in which case any function for which the + * corresponding MBEDTLS_ECP__FUNCTION_NAME__ALT macro is defined will not be + * able to fallback to curves not supported by the alternative implementation. + * + * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT + * and implementing the following functions: + * unsigned char mbedtls_internal_ecp_grp_capable( + * const mbedtls_ecp_group *grp ) + * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) + * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) + * The mbedtls_internal_ecp_grp_capable function should return 1 if the + * replacement functions implement arithmetic for the given group and 0 + * otherwise. + * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are + * called before and after each point operation and provide an opportunity to + * implement optimized set up and tear down instructions. + * + * Example: In case you set MBEDTLS_ECP_INTERNAL_ALT and + * MBEDTLS_ECP_DOUBLE_JAC_ALT, Mbed TLS will still provide the ecp_double_jac() + * function, but will use your mbedtls_internal_ecp_double_jac() if the group + * for the operation is supported by your implementation (i.e. your + * mbedtls_internal_ecp_grp_capable() function returns 1 for this group). If the + * group is not supported by your implementation, then the original Mbed TLS + * implementation of ecp_double_jac() is used instead, unless this fallback + * behaviour is disabled by setting MBEDTLS_ECP_NO_FALLBACK (in which case + * ecp_double_jac() will return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE). + * + * The function prototypes and the definition of mbedtls_ecp_group and + * mbedtls_ecp_point will not change based on MBEDTLS_ECP_INTERNAL_ALT, so your + * implementation of mbedtls_internal_ecp__function_name__ must be compatible + * with their definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + */ +/* Required for all the functions in this section */ +//#define MBEDTLS_ECP_INTERNAL_ALT +/* Turn off software fallback for curves not supported in hardware */ +//#define MBEDTLS_ECP_NO_FALLBACK +/* Support for Weierstrass curves with Jacobi representation */ +//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +//#define MBEDTLS_ECP_ADD_MIXED_ALT +//#define MBEDTLS_ECP_DOUBLE_JAC_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +/* Support for curves with Montgomery arithmetic */ +//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT +//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT +//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT + +/** + * \def MBEDTLS_ENTROPY_HARDWARE_ALT + * + * Uncomment this macro to let Mbed TLS use your own implementation of a + * hardware entropy collector. + * + * Your function must be called \c mbedtls_hardware_poll(), have the same + * prototype as declared in library/entropy_poll.h, and accept NULL as first + * argument. + * + * Uncomment to use your own hardware entropy collector. + */ +//#define MBEDTLS_ENTROPY_HARDWARE_ALT + +/** + * \def MBEDTLS_AES_ROM_TABLES + * + * Use precomputed AES tables stored in ROM. + * + * Uncomment this macro to use precomputed AES tables stored in ROM. + * Comment this macro to generate AES tables in RAM at runtime. + * + * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb + * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the + * initialization time before the first AES operation can be performed. + * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c + * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded + * performance if ROM access is slower than RAM access. + * + * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. + */ +//#define MBEDTLS_AES_ROM_TABLES + +/** + * \def MBEDTLS_AES_FEWER_TABLES + * + * Use less ROM/RAM for AES tables. + * + * Uncommenting this macro omits 75% of the AES tables from + * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) + * by computing their values on the fly during operations + * (the tables are entry-wise rotations of one another). + * + * Tradeoff: Uncommenting this reduces the RAM / ROM footprint + * by ~6kb but at the cost of more arithmetic operations during + * runtime. Specifically, one has to compare 4 accesses within + * different tables to 4 accesses with additional arithmetic + * operations within the same table. The performance gain/loss + * depends on the system and memory details. + * + * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + */ +//#define MBEDTLS_AES_FEWER_TABLES + +/** + * \def MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH + * + * Use only 128-bit keys in AES operations to save ROM. + * + * Uncomment this macro to remove support for AES operations that use 192- + * or 256-bit keys. + * + * Uncommenting this macro reduces the size of AES code by ~300 bytes + * on v8-M/Thumb2. + * + * Module: library/aes.c + * + * Requires: MBEDTLS_AES_C + */ +//#define MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH + +/* + * Disable plain C implementation for AES. + * + * When the plain C implementation is enabled, and an implementation using a + * special CPU feature (such as MBEDTLS_AESCE_C) is also enabled, runtime + * detection will be used to select between them. + * + * If only one implementation is present, runtime detection will not be used. + * This configuration will crash at runtime if running on a CPU without the + * necessary features. It will not build unless at least one of MBEDTLS_AESCE_C + * and/or MBEDTLS_AESNI_C is enabled & present in the build. + */ +//#define MBEDTLS_AES_USE_HARDWARE_ONLY + +/** + * \def MBEDTLS_CAMELLIA_SMALL_MEMORY + * + * Use less ROM for the Camellia implementation (saves about 768 bytes). + * + * Uncomment this macro to use less memory for Camellia. + */ +//#define MBEDTLS_CAMELLIA_SMALL_MEMORY + +/** + * \def MBEDTLS_CHECK_RETURN_WARNING + * + * If this macro is defined, emit a compile-time warning if application code + * calls a function without checking its return value, but the return value + * should generally be checked in portable applications. + * + * This is only supported on platforms where #MBEDTLS_CHECK_RETURN is + * implemented. Otherwise this option has no effect. + * + * Uncomment to get warnings on using fallible functions without checking + * their return value. + * + * \note This feature is a work in progress. + * Warnings will be added to more functions in the future. + * + * \note A few functions are considered critical, and ignoring the return + * value of these functions will trigger a warning even if this + * macro is not defined. To completely disable return value check + * warnings, define #MBEDTLS_CHECK_RETURN with an empty expansion. + */ +//#define MBEDTLS_CHECK_RETURN_WARNING + +/** + * \def MBEDTLS_CIPHER_MODE_CBC + * + * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CBC + +/** + * \def MBEDTLS_CIPHER_MODE_CFB + * + * Enable Cipher Feedback mode (CFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CFB + +/** + * \def MBEDTLS_CIPHER_MODE_CTR + * + * Enable Counter Block Cipher mode (CTR) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CTR + +/** + * \def MBEDTLS_CIPHER_MODE_OFB + * + * Enable Output Feedback mode (OFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_OFB + +/** + * \def MBEDTLS_CIPHER_MODE_XTS + * + * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES. + */ +#define MBEDTLS_CIPHER_MODE_XTS + +/** + * \def MBEDTLS_CIPHER_NULL_CIPHER + * + * Enable NULL cipher. + * Warning: Only do so when you know what you are doing. This allows for + * encryption or channels without any security! + * + * To enable the following ciphersuites: + * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA + * + * Uncomment this macro to enable the NULL cipher and ciphersuites + */ +//#define MBEDTLS_CIPHER_NULL_CIPHER + +/** + * \def MBEDTLS_CIPHER_PADDING_PKCS7 + * + * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for + * specific padding modes in the cipher layer with cipher modes that support + * padding (e.g. CBC) + * + * If you disable all padding modes, only full blocks can be used with CBC. + * + * Enable padding modes in the cipher layer. + */ +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS + +/** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + * + * Uncomment this macro to use a 128-bit key in the CTR_DRBG module. + * Without this, CTR_DRBG uses a 256-bit key + * unless \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. + */ +//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + +/** + * Enable the verified implementations of ECDH primitives from Project Everest + * (currently only Curve25519). This feature changes the layout of ECDH + * contexts and therefore is a compatibility break for applications that access + * fields of a mbedtls_ecdh_context structure directly. See also + * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h. + */ +//#define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED + +/** + * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED + * + * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve + * module. By default all supported curves are enabled. + * + * Comment macros to disable the curve and functions for it + */ +/* Short Weierstrass curves (supporting ECP, ECDH, ECDSA) */ +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +/* Montgomery curves (supporting ECP) */ +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_CURVE448_ENABLED + +/** + * \def MBEDTLS_ECP_NIST_OPTIM + * + * Enable specific 'modulo p' routines for each NIST prime. + * Depending on the prime and architecture, makes operations 4 to 8 times + * faster on the corresponding curve. + * + * Comment this macro to disable NIST curves optimisation. + */ +#define MBEDTLS_ECP_NIST_OPTIM + +/** + * \def MBEDTLS_ECP_RESTARTABLE + * + * Enable "non-blocking" ECC operations that can return early and be resumed. + * + * This allows various functions to pause by returning + * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module, + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in + * order to further progress and eventually complete their operation. This is + * controlled through mbedtls_ecp_set_max_ops() which limits the maximum + * number of ECC operations a function may perform before pausing; see + * mbedtls_ecp_set_max_ops() for more information. + * + * This is useful in non-threaded environments if you want to avoid blocking + * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. + * + * This option: + * - Adds xxx_restartable() variants of existing operations in the + * following modules, with corresponding restart context types: + * - ECP (for Short Weierstrass curves only): scalar multiplication (mul), + * linear combination (muladd); + * - ECDSA: signature generation & verification; + * - PK: signature generation & verification; + * - X509: certificate chain verification. + * - Adds mbedtls_ecdh_enable_restart() in the ECDH module. + * - Changes the behaviour of TLS 1.2 clients (not servers) when using the + * ECDHE-ECDSA key exchange (not other key exchanges) to make all ECC + * computations restartable: + * - ECDH operations from the key exchange, only for Short Weierstrass + * curves, only when MBEDTLS_USE_PSA_CRYPTO is not enabled. + * - verification of the server's key exchange signature; + * - verification of the server's certificate chain; + * - generation of the client's signature if client authentication is used, + * with an ECC key/certificate. + * + * \note In the cases above, the usual SSL/TLS functions, such as + * mbedtls_ssl_handshake(), can now return + * MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS. + * + * \note When this option and MBEDTLS_USE_PSA_CRYPTO are both enabled, + * restartable operations in PK, X.509 and TLS (see above) are not + * using PSA. On the other hand, ECDH computations in TLS are using + * PSA, and are not restartable. These are temporary limitations that + * should be lifted in the future. + * + * \note This option only works with the default software implementation of + * elliptic curve functionality. It is incompatible with + * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT, MBEDTLS_ECDSA_XXX_ALT. + * + * Requires: MBEDTLS_ECP_C + * + * Uncomment this macro to enable restartable ECC computations. + */ +//#define MBEDTLS_ECP_RESTARTABLE + +/** + * Uncomment to enable using new bignum code in the ECC modules. + * + * \warning This is currently experimental, incomplete and therefore should not + * be used in production. + */ +//#define MBEDTLS_ECP_WITH_MPI_UINT + +/** + * \def MBEDTLS_ECDSA_DETERMINISTIC + * + * Enable deterministic ECDSA (RFC 6979). + * Standard ECDSA is "fragile" in the sense that lack of entropy when signing + * may result in a compromise of the long-term signing key. This is avoided by + * the deterministic variant. + * + * Requires: MBEDTLS_HMAC_DRBG_C, MBEDTLS_ECDSA_C + * + * Comment this macro to disable deterministic ECDSA. + */ +#define MBEDTLS_ECDSA_DETERMINISTIC + +/** + * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + * + * Enable the PSK based ciphersuite modes in SSL / TLS. + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + * + * Enable the DHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + * + * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + * + * Enable the RSA-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + * + * Enable the RSA-only based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + * + * Enable the DHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + * + * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_RSA_C + * MBEDTLS_PKCS1_V15 + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + * + * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + * + * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + * + * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDH) + * MBEDTLS_RSA_C + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + * + * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Requires: MBEDTLS_ECJPAKE_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_JPAKE) + * SHA-256 (via MBEDTLS_SHA256_C or a PSA driver) + * MBEDTLS_ECP_DP_SECP256R1_ENABLED + * + * \warning If SHA-256 is provided only by a PSA driver, you must call + * psa_crypto_init() before the first hanshake (even if + * MBEDTLS_USE_PSA_CRYPTO is disabled). + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + */ +//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + +/** + * \def MBEDTLS_PK_PARSE_EC_EXTENDED + * + * Enhance support for reading EC keys using variants of SEC1 not allowed by + * RFC 5915 and RFC 5480. + * + * Currently this means parsing the SpecifiedECDomain choice of EC + * parameters (only known groups are supported, not arbitrary domains, to + * avoid validation issues). + * + * Disable if you only need to support RFC 5915 + 5480 key formats. + */ +#define MBEDTLS_PK_PARSE_EC_EXTENDED + +/** + * \def MBEDTLS_PK_PARSE_EC_COMPRESSED + * + * Enable the support for parsing public keys of type Short Weierstrass + * (MBEDTLS_ECP_DP_SECP_XXX and MBEDTLS_ECP_DP_BP_XXX) which are using the + * compressed point format. This parsing is done through ECP module's functions. + * + * \note As explained in the description of MBEDTLS_ECP_PF_COMPRESSED (in ecp.h) + * the only unsupported curves are MBEDTLS_ECP_DP_SECP224R1 and + * MBEDTLS_ECP_DP_SECP224K1. + */ +#define MBEDTLS_PK_PARSE_EC_COMPRESSED + +/** + * \def MBEDTLS_ERROR_STRERROR_DUMMY + * + * Enable a dummy error function to make use of mbedtls_strerror() in + * third party libraries easier when MBEDTLS_ERROR_C is disabled + * (no effect when MBEDTLS_ERROR_C is enabled). + * + * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're + * not using mbedtls_strerror() or error_strerror() in your application. + * + * Disable if you run into name conflicts and want to really remove the + * mbedtls_strerror() + */ +#define MBEDTLS_ERROR_STRERROR_DUMMY + +/** + * \def MBEDTLS_GENPRIME + * + * Enable the prime-number generation code. + * + * Requires: MBEDTLS_BIGNUM_C + */ +#define MBEDTLS_GENPRIME + +/** + * \def MBEDTLS_FS_IO + * + * Enable functions that use the filesystem. + */ +#define MBEDTLS_FS_IO + +/** + * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + * Do not add default entropy sources in mbedtls_entropy_init(). + * + * This is useful to have more control over the added entropy sources in an + * application. + * + * Uncomment this macro to prevent loading of default entropy functions. + */ +//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + +/** + * \def MBEDTLS_NO_PLATFORM_ENTROPY + * + * Do not use built-in platform entropy functions. + * This is useful if your platform does not support + * standards like the /dev/urandom or Windows CryptoAPI. + * + * Uncomment this macro to disable the built-in platform entropy functions. + */ +//#define MBEDTLS_NO_PLATFORM_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_FORCE_SHA256 + * + * Force the entropy accumulator to use a SHA-256 accumulator instead of the + * default SHA-512 based one (if both are available). + * + * Requires: MBEDTLS_SHA256_C + * + * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option + * if you have performance concerns. + * + * This option is only useful if both MBEDTLS_SHA256_C and + * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. + */ +//#define MBEDTLS_ENTROPY_FORCE_SHA256 + +/** + * \def MBEDTLS_ENTROPY_NV_SEED + * + * Enable the non-volatile (NV) seed file-based entropy source. + * (Also enables the NV seed read/write functions in the platform layer) + * + * This is crucial (if not required) on systems that do not have a + * cryptographic entropy source (in hardware or kernel) available. + * + * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C + * + * \note The read/write functions that are used by the entropy source are + * determined in the platform layer, and can be modified at runtime and/or + * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. + * + * \note If you use the default implementation functions that read a seedfile + * with regular fopen(), please make sure you make a seedfile with the + * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at + * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from + * and written to or you will get an entropy source error! The default + * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE + * bytes from the file. + * + * \note The entropy collector will write to the seed file before entropy is + * given to an external source, to update it. + */ +//#define MBEDTLS_ENTROPY_NV_SEED + +/* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + * + * Enable key identifiers that encode a key owner identifier. + * + * The owner of a key is identified by a value of type ::mbedtls_key_owner_id_t + * which is currently hard-coded to be int32_t. + * + * Note that this option is meant for internal use only and may be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + +/** + * \def MBEDTLS_MEMORY_DEBUG + * + * Enable debugging of buffer allocator memory issues. Automatically prints + * (to stderr) all (fatal) messages on memory allocation issues. Enables + * function for 'debug output' of allocated memory. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Uncomment this macro to let the buffer allocator print out error messages. + */ +//#define MBEDTLS_MEMORY_DEBUG + +/** + * \def MBEDTLS_MEMORY_BACKTRACE + * + * Include backtrace information with each allocated block. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * GLIBC-compatible backtrace() and backtrace_symbols() support + * + * Uncomment this macro to include backtrace information + */ +//#define MBEDTLS_MEMORY_BACKTRACE + +/** + * \def MBEDTLS_PK_RSA_ALT_SUPPORT + * + * Support external private RSA keys (eg from a HSM) in the PK layer. + * + * Comment this macro to disable support for external private RSA keys. + */ +#define MBEDTLS_PK_RSA_ALT_SUPPORT + +/** + * \def MBEDTLS_PKCS1_V15 + * + * Enable support for PKCS#1 v1.5 encoding. + * + * Requires: MBEDTLS_RSA_C + * + * This enables support for PKCS#1 v1.5 operations. + */ +#define MBEDTLS_PKCS1_V15 + +/** + * \def MBEDTLS_PKCS1_V21 + * + * Enable support for PKCS#1 v2.1 encoding. + * + * Requires: MBEDTLS_RSA_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS#1 v2.1 operation. + * + * This enables support for RSAES-OAEP and RSASSA-PSS operations. + */ +#define MBEDTLS_PKCS1_V21 + +/** \def MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + * + * Enable support for platform built-in keys. If you enable this feature, + * you must implement the function mbedtls_psa_platform_get_builtin_key(). + * See the documentation of that function for more information. + * + * Built-in keys are typically derived from a hardware unique key or + * stored in a secure element. + * + * Requires: MBEDTLS_PSA_CRYPTO_C. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + +/** \def MBEDTLS_PSA_CRYPTO_CLIENT + * + * Enable support for PSA crypto client. + * + * \note This option allows to include the code necessary for a PSA + * crypto client when the PSA crypto implementation is not included in + * the library (MBEDTLS_PSA_CRYPTO_C disabled). The code included is the + * code to set and get PSA key attributes. + * The development of PSA drivers partially relying on the library to + * fulfill the hardware gaps is another possible usage of this option. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_CLIENT + +/** \def MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * + * Make the PSA Crypto module use an external random generator provided + * by a driver, instead of Mbed TLS's entropy and DRBG modules. + * + * \note This random generator must deliver random numbers with cryptographic + * quality and high performance. It must supply unpredictable numbers + * with a uniform distribution. The implementation of this function + * is responsible for ensuring that the random generator is seeded + * with sufficient entropy. If you have a hardware TRNG which is slow + * or delivers non-uniform output, declare it as an entropy source + * with mbedtls_entropy_add_source() instead of enabling this option. + * + * If you enable this option, you must configure the type + * ::mbedtls_psa_external_random_context_t in psa/crypto_platform.h + * and define a function called mbedtls_psa_external_get_random() + * with the following prototype: + * ``` + * psa_status_t mbedtls_psa_external_get_random( + * mbedtls_psa_external_random_context_t *context, + * uint8_t *output, size_t output_size, size_t *output_length); + * ); + * ``` + * The \c context value is initialized to 0 before the first call. + * The function must fill the \c output buffer with \c output_size bytes + * of random data and set \c *output_length to \c output_size. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \warning If you enable this option, code that uses the PSA cryptography + * interface will not use any of the entropy sources set up for + * the entropy module, nor the NV seed that MBEDTLS_ENTROPY_NV_SEED + * enables. + * + * \note This option is experimental and may be removed without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +/** + * \def MBEDTLS_PSA_CRYPTO_SPM + * + * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is built for SPM (Secure + * Partition Manager) integration which separates the code into two parts: a + * NSPE (Non-Secure Process Environment) and an SPE (Secure Process + * Environment). + * + * If you enable this option, your build environment must include a header + * file `"crypto_spe.h"` (either in the `psa` subdirectory of the Mbed TLS + * header files, or in another directory on the compiler's include search + * path). Alternatively, your platform may customize the header + * `psa/crypto_platform.h`, in which case it can skip or replace the + * inclusion of `"crypto_spe.h"`. + * + * Module: library/psa_crypto.c + * Requires: MBEDTLS_PSA_CRYPTO_C + * + */ +//#define MBEDTLS_PSA_CRYPTO_SPM + +/** + * Uncomment to enable p256-m. This is an alternative implementation of + * key generation, ECDH and (randomized) ECDSA on the curve SECP256R1. + * Compared to the default implementation: + * + * - p256-m has a much smaller code size and RAM footprint. + * - p256-m is only available via the PSA API. This includes the pk module + * when #MBEDTLS_USE_PSA_CRYPTO is enabled. + * - p256-m does not support deterministic ECDSA, EC-JPAKE, custom protocols + * over the core arithmetic, or deterministic derivation of keys. + * + * We recommend enabling this option if your application uses the PSA API + * and the only elliptic curve support it needs is ECDH and ECDSA over + * SECP256R1. + * + * If you enable this option, you do not need to enable any ECC-related + * MBEDTLS_xxx option. You do need to separately request support for the + * cryptographic mechanisms through the PSA API: + * - #MBEDTLS_PSA_CRYPTO_C and #MBEDTLS_PSA_CRYPTO_CONFIG for PSA-based + * configuration; + * - #MBEDTLS_USE_PSA_CRYPTO if you want to use p256-m from PK, X.509 or TLS; + * - #PSA_WANT_ECC_SECP_R1_256; + * - #PSA_WANT_ALG_ECDH and/or #PSA_WANT_ALG_ECDSA as needed; + * - #PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY, #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT, + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT and/or + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE as needed. + * + * \note To benefit from the smaller code size of p256-m, make sure that you + * do not enable any ECC-related option not supported by p256-m: this + * would cause the built-in ECC implementation to be built as well, in + * order to provide the required option. + * Make sure #PSA_WANT_ALG_DETERMINISTIC_ECDSA, #PSA_WANT_ALG_JPAKE and + * #PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE, and curves other than + * SECP256R1 are disabled as they are not supported by this driver. + * Also, avoid defining #MBEDTLS_PK_PARSE_EC_COMPRESSED or + * #MBEDTLS_PK_PARSE_EC_EXTENDED as those currently require a subset of + * the built-in ECC implementation, see docs/driver-only-builds.md. + */ +//#define MBEDTLS_PSA_P256M_DRIVER_ENABLED + +/** + * \def MBEDTLS_PSA_INJECT_ENTROPY + * + * Enable support for entropy injection at first boot. This feature is + * required on systems that do not have a built-in entropy source (TRNG). + * This feature is currently not supported on systems that have a built-in + * entropy source. + * + * Requires: MBEDTLS_PSA_CRYPTO_STORAGE_C, MBEDTLS_ENTROPY_NV_SEED + * + */ +//#define MBEDTLS_PSA_INJECT_ENTROPY + +/** + * \def MBEDTLS_RSA_NO_CRT + * + * Do not use the Chinese Remainder Theorem + * for the RSA private operation. + * + * Uncomment this macro to disable the use of CRT in RSA. + * + */ +//#define MBEDTLS_RSA_NO_CRT + +/** + * \def MBEDTLS_SELF_TEST + * + * Enable the checkup functions (*_self_test). + */ +#define MBEDTLS_SELF_TEST + +/** + * \def MBEDTLS_SHA256_SMALLER + * + * Enable an implementation of SHA-256 that has lower ROM footprint but also + * lower performance. + * + * The default implementation is meant to be a reasonable compromise between + * performance and size. This version optimizes more aggressively for size at + * the expense of performance. Eg on Cortex-M4 it reduces the size of + * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about + * 30%. + * + * Uncomment to enable the smaller implementation of SHA256. + */ +//#define MBEDTLS_SHA256_SMALLER + +/** + * \def MBEDTLS_SHA512_SMALLER + * + * Enable an implementation of SHA-512 that has lower ROM footprint but also + * lower performance. + * + * Uncomment to enable the smaller implementation of SHA512. + */ +//#define MBEDTLS_SHA512_SMALLER + +/** + * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES + * + * Enable sending of alert messages in case of encountered errors as per RFC. + * If you choose not to send the alert messages, Mbed TLS can still communicate + * with other servers, only debugging of failures is harder. + * + * The advantage of not sending alert messages, is that no information is given + * about reasons for failures thus preventing adversaries of gaining intel. + * + * Enable sending of all alert messages + */ +#define MBEDTLS_SSL_ALL_ALERT_MESSAGES + +/** + * \def MBEDTLS_SSL_DTLS_CONNECTION_ID + * + * Enable support for the DTLS Connection ID (CID) extension, + * which allows to identify DTLS connections across changes + * in the underlying transport. The CID functionality is described + * in RFC 9146. + * + * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`, + * mbedtls_ssl_get_own_cid()`, `mbedtls_ssl_get_peer_cid()` and + * `mbedtls_ssl_conf_cid()`. See the corresponding documentation for + * more information. + * + * The maximum lengths of outgoing and incoming CIDs can be configured + * through the options + * - MBEDTLS_SSL_CID_OUT_LEN_MAX + * - MBEDTLS_SSL_CID_IN_LEN_MAX. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment to enable the Connection ID extension. + */ +#define MBEDTLS_SSL_DTLS_CONNECTION_ID + + +/** + * \def MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT + * + * Defines whether RFC 9146 (default) or the legacy version + * (version draft-ietf-tls-dtls-connection-id-05, + * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05) + * is used. + * + * Set the value to 0 for the standard version, and + * 1 for the legacy draft version. + * + * \deprecated Support for the legacy version of the DTLS + * Connection ID feature is deprecated. Please + * switch to the standardized version defined + * in RFC 9146 enabled by utilizing + * MBEDTLS_SSL_DTLS_CONNECTION_ID without use + * of MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT. + * + * Requires: MBEDTLS_SSL_DTLS_CONNECTION_ID + */ +#define MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT 0 + +/** + * \def MBEDTLS_SSL_ASYNC_PRIVATE + * + * Enable asynchronous external private key operations in SSL. This allows + * you to configure an SSL connection to call an external cryptographic + * module to perform private key operations instead of performing the + * operation inside the library. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + */ +//#define MBEDTLS_SSL_ASYNC_PRIVATE + +/** + * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION + * + * Enable serialization of the TLS context structures, through use of the + * functions mbedtls_ssl_context_save() and mbedtls_ssl_context_load(). + * + * This pair of functions allows one side of a connection to serialize the + * context associated with the connection, then free or re-use that context + * while the serialized state is persisted elsewhere, and finally deserialize + * that state to a live context for resuming read/write operations on the + * connection. From a protocol perspective, the state of the connection is + * unaffected, in particular this is entirely transparent to the peer. + * + * Note: this is distinct from TLS session resumption, which is part of the + * protocol and fully visible by the peer. TLS session resumption enables + * establishing new connections associated to a saved session with shorter, + * lighter handshakes, while context serialization is a local optimization in + * handling a single, potentially long-lived connection. + * + * Enabling these APIs makes some SSL structures larger, as 64 extra bytes are + * saved after the handshake to allow for more efficient serialization, so if + * you don't need this feature you'll save RAM by disabling it. + * + * Requires: MBEDTLS_GCM_C or MBEDTLS_CCM_C or MBEDTLS_CHACHAPOLY_C + * + * Comment to disable the context serialization APIs. + */ +#define MBEDTLS_SSL_CONTEXT_SERIALIZATION + +/** + * \def MBEDTLS_SSL_DEBUG_ALL + * + * Enable the debug messages in SSL module for all issues. + * Debug messages have been disabled in some places to prevent timing + * attacks due to (unbalanced) debugging function calls. + * + * If you need all error reporting you should enable this during debugging, + * but remove this for production servers that should log as well. + * + * Uncomment this macro to report all debug messages on errors introducing + * a timing side-channel. + * + */ +//#define MBEDTLS_SSL_DEBUG_ALL + +/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC + * + * Enable support for Encrypt-then-MAC, RFC 7366. + * + * This allows peers that both support it to use a more robust protection for + * ciphersuites using CBC, providing deep resistance against timing attacks + * on the padding or underlying cipher. + * + * This only affects CBC ciphersuites, and is useless if none is defined. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Encrypt-then-MAC + */ +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC + +/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET + * + * Enable support for RFC 7627: Session Hash and Extended Master Secret + * Extension. + * + * This was introduced as "the proper fix" to the Triple Handshake family of + * attacks, but it is recommended to always use it (even if you disable + * renegotiation), since it actually fixes a more fundamental issue in the + * original SSL/TLS design, and has implications beyond Triple Handshake. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Extended Master Secret. + */ +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET + +/** + * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + * + * This option controls the availability of the API mbedtls_ssl_get_peer_cert() + * giving access to the peer's certificate after completion of the handshake. + * + * Unless you need mbedtls_ssl_peer_cert() in your application, it is + * recommended to disable this option for reduced RAM usage. + * + * \note If this option is disabled, mbedtls_ssl_get_peer_cert() is still + * defined, but always returns \c NULL. + * + * \note This option has no influence on the protection against the + * triple handshake attack. Even if it is disabled, Mbed TLS will + * still ensure that certificates do not change during renegotiation, + * for example by keeping a hash of the peer's certificate. + * + * \note This option is required if MBEDTLS_SSL_PROTO_TLS1_3 is set. + * + * Comment this macro to disable storing the peer's certificate + * after the handshake. + */ +#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + +/** + * \def MBEDTLS_SSL_RENEGOTIATION + * + * Enable support for TLS renegotiation. + * + * The two main uses of renegotiation are (1) refresh keys on long-lived + * connections and (2) client authentication after the initial handshake. + * If you don't need renegotiation, it's probably better to disable it, since + * it has been associated with security issues in the past and is easy to + * misuse/misunderstand. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this to disable support for renegotiation. + * + * \note Even if this option is disabled, both client and server are aware + * of the Renegotiation Indication Extension (RFC 5746) used to + * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). + * (See \c mbedtls_ssl_conf_legacy_renegotiation for the + * configuration of this extension). + * + */ +#define MBEDTLS_SSL_RENEGOTIATION + +/** + * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + * + * Enable support for RFC 6066 max_fragment_length extension in SSL. + * + * Comment this macro to disable support for the max_fragment_length extension + */ +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/** + * \def MBEDTLS_SSL_RECORD_SIZE_LIMIT + * + * Enable support for RFC 8449 record_size_limit extension in SSL (TLS 1.3 only). + * + * \warning This extension is currently in development and must NOT be used except + * for testing purposes. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_3 + * + * Uncomment this macro to enable support for the record_size_limit extension + */ +//#define MBEDTLS_SSL_RECORD_SIZE_LIMIT + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_2 + * + * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). + * + * Requires: Without MBEDTLS_USE_PSA_CRYPTO: MBEDTLS_MD_C and + * (MBEDTLS_SHA256_C or MBEDTLS_SHA384_C or + * SHA-256 or SHA-512 provided by a PSA driver) + * With MBEDTLS_USE_PSA_CRYPTO: + * PSA_WANT_ALG_SHA_256 or PSA_WANT_ALG_SHA_384 + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, or if the hash(es) used + * are only provided by PSA drivers, you must call psa_crypto_init() before + * doing any TLS operations. + * + * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 + */ +#define MBEDTLS_SSL_PROTO_TLS1_2 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_3 + * + * Enable support for TLS 1.3. + * + * \note See docs/architecture/tls13-support.md for a description of the TLS + * 1.3 support that this option enables. + * + * Requires: MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \note TLS 1.3 uses PSA crypto for cryptographic operations that are + * directly performed by TLS 1.3 code. As a consequence, you must + * call psa_crypto_init() before the first TLS 1.3 handshake. + * + * \note Cryptographic operations performed indirectly via another module + * (X.509, PK) or by code shared with TLS 1.2 (record protection, + * running handshake hash) only use PSA crypto if + * #MBEDTLS_USE_PSA_CRYPTO is enabled. + * + * Uncomment this macro to enable the support for TLS 1.3. + */ +//#define MBEDTLS_SSL_PROTO_TLS1_3 + +/** + * \def MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + * + * Enable TLS 1.3 middlebox compatibility mode. + * + * As specified in Section D.4 of RFC 8446, TLS 1.3 offers a compatibility + * mode to make a TLS 1.3 connection more likely to pass through middle boxes + * expecting TLS 1.2 traffic. + * + * Turning on the compatibility mode comes at the cost of a few added bytes + * on the wire, but it doesn't affect compatibility with TLS 1.3 implementations + * that don't use it. Therefore, unless transmission bandwidth is critical and + * you know that middlebox compatibility issues won't occur, it is therefore + * recommended to set this option. + * + * Comment to disable compatibility mode for TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +//#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + * + * Enable TLS 1.3 PSK key exchange mode. + * + * Comment to disable support for the PSK key exchange mode in TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * MBEDTLS_X509_CRT_PARSE_C + * and at least one of: + * MBEDTLS_ECDSA_C or (MBEDTLS_USE_PSA_CRYPTO and PSA_WANT_ALG_ECDSA) + * MBEDTLS_PKCS1_V21 + * + * Comment to disable support for the ephemeral key exchange mode in TLS 1.3. + * If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Enable TLS 1.3 PSK ephemeral key exchange mode. + * + * Requires: PSA_WANT_ALG_ECDH or PSA_WANT_ALG_FFDH + * + * Comment to disable support for the PSK ephemeral key exchange mode in + * TLS 1.3. If MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not + * have any effect on the build. + * + */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + +/** + * \def MBEDTLS_SSL_EARLY_DATA + * + * Enable support for RFC 8446 TLS 1.3 early data. + * + * Requires: MBEDTLS_SSL_SESSION_TICKETS and either + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED or + * MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED + * + * Comment this to disable support for early data. If MBEDTLS_SSL_PROTO_TLS1_3 + * is not enabled, this option does not have any effect on the build. + * + * This feature is experimental, not completed and thus not ready for + * production. + * + * \note The maximum amount of early data can be set with + * MBEDTLS_SSL_MAX_EARLY_DATA_SIZE. + * + */ +//#define MBEDTLS_SSL_EARLY_DATA + +/** + * \def MBEDTLS_SSL_PROTO_DTLS + * + * Enable support for DTLS (all available versions). + * + * Enable this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for DTLS + */ +#define MBEDTLS_SSL_PROTO_DTLS + +/** + * \def MBEDTLS_SSL_ALPN + * + * Enable support for RFC 7301 Application Layer Protocol Negotiation. + * + * Comment this macro to disable support for ALPN. + */ +#define MBEDTLS_SSL_ALPN + +/** + * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY + * + * Enable support for the anti-replay mechanism in DTLS. + * + * Requires: MBEDTLS_SSL_TLS_C + * MBEDTLS_SSL_PROTO_DTLS + * + * \warning Disabling this is often a security risk! + * See mbedtls_ssl_conf_dtls_anti_replay() for details. + * + * Comment this to disable anti-replay in DTLS. + */ +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY + +/** + * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Enable support for HelloVerifyRequest on DTLS servers. + * + * This feature is highly recommended to prevent DTLS servers being used as + * amplifiers in DoS attacks against other hosts. It should always be enabled + * unless you know for sure amplification cannot be a problem in the + * environment in which your server operates. + * + * \warning Disabling this can be a security risk! (see above) + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Comment this to disable support for HelloVerifyRequest. + */ +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY + +/** + * \def MBEDTLS_SSL_DTLS_SRTP + * + * Enable support for negotiation of DTLS-SRTP (RFC 5764) + * through the use_srtp extension. + * + * \note This feature provides the minimum functionality required + * to negotiate the use of DTLS-SRTP and to allow the derivation of + * the associated SRTP packet protection key material. + * In particular, the SRTP packet protection itself, as well as the + * demultiplexing of RTP and DTLS packets at the datagram layer + * (see Section 5 of RFC 5764), are not handled by this feature. + * Instead, after successful completion of a handshake negotiating + * the use of DTLS-SRTP, the extended key exporter API + * mbedtls_ssl_conf_export_keys_cb() should be used to implement + * the key exporter described in Section 4.2 of RFC 5764 and RFC 5705 + * (this is implemented in the SSL example programs). + * The resulting key should then be passed to an SRTP stack. + * + * Setting this option enables the runtime API + * mbedtls_ssl_conf_dtls_srtp_protection_profiles() + * through which the supported DTLS-SRTP protection + * profiles can be configured. You must call this API at + * runtime if you wish to negotiate the use of DTLS-SRTP. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment this to enable support for use_srtp extension. + */ +//#define MBEDTLS_SSL_DTLS_SRTP + +/** + * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + * + * Enable server-side support for clients that reconnect from the same port. + * + * Some clients unexpectedly close the connection and try to reconnect using the + * same source port. This needs special support from the server to handle the + * new connection securely, as described in section 4.2.8 of RFC 6347. This + * flag enables that support. + * + * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Comment this to disable support for clients reusing the source port. + */ +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + +/** + * \def MBEDTLS_SSL_SESSION_TICKETS + * + * Enable support for RFC 5077 session tickets in SSL. + * Client-side, provides full support for session tickets (maintenance of a + * session store remains the responsibility of the application, though). + * Server-side, you also need to provide callbacks for writing and parsing + * tickets, including authenticated encryption and key management. Example + * callbacks are provided by MBEDTLS_SSL_TICKET_C. + * + * Comment this macro to disable support for SSL session tickets + */ +#define MBEDTLS_SSL_SESSION_TICKETS + +/** + * \def MBEDTLS_SSL_SERVER_NAME_INDICATION + * + * Enable support for RFC 6066 server name indication (SNI) in SSL. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Comment this macro to disable support for server name indication in SSL + */ +#define MBEDTLS_SSL_SERVER_NAME_INDICATION + +/** + * \def MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + * + * When this option is enabled, the SSL buffer will be resized automatically + * based on the negotiated maximum fragment length in each direction. + * + * Requires: MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + */ +//#define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + * + * Enable testing of the constant-flow nature of some sensitive functions with + * clang's MemorySanitizer. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires compiling with clang -fsanitize=memory. The test + * suites can then be run normally. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + * + * Enable testing of the constant-flow nature of some sensitive functions with + * valgrind's memcheck tool. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires valgrind headers for building, and is only useful for + * testing if the tests suites are run with valgrind's memcheck. This can be + * done for an individual test suite with 'valgrind ./test_suite_xxx', or when + * using CMake, this can be done for all test suites with 'make memcheck'. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + +/** + * \def MBEDTLS_TEST_HOOKS + * + * Enable features for invasive testing such as introspection functions and + * hooks for fault injection. This enables additional unit tests. + * + * Merely enabling this feature should not change the behavior of the product. + * It only adds new code, and new branching points where the default behavior + * is the same as when this feature is disabled. + * However, this feature increases the attack surface: there is an added + * risk of vulnerabilities, and more gadgets that can make exploits easier. + * Therefore this feature must never be enabled in production. + * + * See `docs/architecture/testing/mbed-crypto-invasive-testing.md` for more + * information. + * + * Uncomment to enable invasive tests. + */ +//#define MBEDTLS_TEST_HOOKS + +/** + * \def MBEDTLS_THREADING_ALT + * + * Provide your own alternate threading implementation. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to allow your own alternate threading implementation. + */ +//#define MBEDTLS_THREADING_ALT + +/** + * \def MBEDTLS_THREADING_PTHREAD + * + * Enable the pthread wrapper layer for the threading layer. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to enable pthread mutexes. + */ +//#define MBEDTLS_THREADING_PTHREAD + +/** + * \def MBEDTLS_USE_PSA_CRYPTO + * + * Make the X.509 and TLS libraries use PSA for cryptographic operations as + * much as possible, and enable new APIs for using keys handled by PSA Crypto. + * + * \note Development of this option is currently in progress, and parts of Mbed + * TLS's X.509 and TLS modules are not ported to PSA yet. However, these parts + * will still continue to work as usual, so enabling this option should not + * break backwards compatibility. + * + * \warning If you enable this option, you need to call `psa_crypto_init()` + * before calling any function from the SSL/TLS, X.509 or PK modules, except + * for the various mbedtls_xxx_init() functions which can be called at any time. + * + * \note An important and desirable effect of this option is that it allows + * PK, X.509 and TLS to take advantage of PSA drivers. For example, enabling + * this option is what allows use of drivers for ECDSA, ECDH and EC J-PAKE in + * those modules. However, note that even with this option disabled, some code + * in PK, X.509, TLS or the crypto library might still use PSA drivers, if it + * can determine it's safe to do so; currently that's the case for hashes. + * + * \note See docs/use-psa-crypto.md for a complete description this option. + * + * Requires: MBEDTLS_PSA_CRYPTO_C. + * + * Uncomment this to enable internal use of PSA Crypto and new associated APIs. + */ +//#define MBEDTLS_USE_PSA_CRYPTO + +/** + * \def MBEDTLS_PSA_CRYPTO_CONFIG + * + * This setting allows support for cryptographic mechanisms through the PSA + * API to be configured separately from support through the mbedtls API. + * + * When this option is disabled, the PSA API exposes the cryptographic + * mechanisms that can be implemented on top of the `mbedtls_xxx` API + * configured with `MBEDTLS_XXX` symbols. + * + * When this option is enabled, the PSA API exposes the cryptographic + * mechanisms requested by the `PSA_WANT_XXX` symbols defined in + * include/psa/crypto_config.h. The corresponding `MBEDTLS_XXX` settings are + * automatically enabled if required (i.e. if no PSA driver provides the + * mechanism). You may still freely enable additional `MBEDTLS_XXX` symbols + * in mbedtls_config.h. + * + * If the symbol #MBEDTLS_PSA_CRYPTO_CONFIG_FILE is defined, it specifies + * an alternative header to include instead of include/psa/crypto_config.h. + * + * \warning This option is experimental, in that the set of `PSA_WANT_XXX` + * symbols is not completely finalized yet, and the configuration + * tooling is not ideally adapted to having two separate configuration + * files. + * Future minor releases of Mbed TLS may make minor changes to those + * symbols, but we will endeavor to provide a transition path. + * Nonetheless, this option is considered mature enough to use in + * production, as long as you accept that you may need to make + * minor changes to psa/crypto_config.h when upgrading Mbed TLS. + */ +//#define MBEDTLS_PSA_CRYPTO_CONFIG + +/** + * \def MBEDTLS_VERSION_FEATURES + * + * Allow run-time checking of compile-time enabled features. Thus allowing users + * to check at run-time if the library is for instance compiled with threading + * support via mbedtls_version_check_feature(). + * + * Requires: MBEDTLS_VERSION_C + * + * Comment this to disable run-time checking and save ROM space + */ +#define MBEDTLS_VERSION_FEATURES + +/** + * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + * + * If set, this enables the X.509 API `mbedtls_x509_crt_verify_with_ca_cb()` + * and the SSL API `mbedtls_ssl_conf_ca_cb()` which allow users to configure + * the set of trusted certificates through a callback instead of a linked + * list. + * + * This is useful for example in environments where a large number of trusted + * certificates is present and storing them in a linked list isn't efficient + * enough, or when the set of trusted certificates changes frequently. + * + * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and + * `mbedtls_ssl_conf_ca_cb()` for more information. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Uncomment to enable trusted certificate callbacks. + */ +//#define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + +/** + * \def MBEDTLS_X509_REMOVE_INFO + * + * Disable mbedtls_x509_*_info() and related APIs. + * + * Uncomment to omit mbedtls_x509_*_info(), as well as mbedtls_debug_print_crt() + * and other functions/constants only used by these functions, thus reducing + * the code footprint by several KB. + */ +//#define MBEDTLS_X509_REMOVE_INFO + +/** + * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT + * + * Enable parsing and verification of X.509 certificates, CRLs and CSRS + * signed with RSASSA-PSS (aka PKCS#1 v2.1). + * + * Comment this macro to disallow using RSASSA-PSS in certificates. + */ +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT +/** \} name SECTION: Mbed TLS feature support */ + +/** + * \name SECTION: Mbed TLS modules + * + * This section enables or disables entire modules in Mbed TLS + * \{ + */ + +/** + * \def MBEDTLS_AESNI_C + * + * Enable AES-NI support on x86-64 or x86-32. + * + * \note AESNI is only supported with certain compilers and target options: + * - Visual Studio 2013: supported. + * - GCC, x86-64, target not explicitly supporting AESNI: + * requires MBEDTLS_HAVE_ASM. + * - GCC, x86-32, target not explicitly supporting AESNI: + * not supported. + * - GCC, x86-64 or x86-32, target supporting AESNI: supported. + * For this assembly-less implementation, you must currently compile + * `library/aesni.c` and `library/aes.c` with machine options to enable + * SSE2 and AESNI instructions: `gcc -msse2 -maes -mpclmul` or + * `clang -maes -mpclmul`. + * - Non-x86 targets: this option is silently ignored. + * - Other compilers: this option is silently ignored. + * + * \note + * Above, "GCC" includes compatible compilers such as Clang. + * The limitations on target support are likely to be relaxed in the future. + * + * Module: library/aesni.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM (on some platforms, see note) + * + * This modules adds support for the AES-NI instructions on x86. + */ +#define MBEDTLS_AESNI_C + +/** + * \def MBEDTLS_AESCE_C + * + * Enable AES cryptographic extension support on 64-bit Arm. + * + * Module: library/aesce.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_AES_C + * + * \warning Runtime detection only works on Linux. For non-Linux operating + * system, Armv8-A Cryptographic Extensions must be supported by + * the CPU when this option is enabled. + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6, GCC 6.0 or MSVC 2019 version 16.11.2. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * This module adds support for the AES Armv8-A Cryptographic Extensions on Aarch64 systems. + */ +#define MBEDTLS_AESCE_C + +/** + * \def MBEDTLS_AES_C + * + * Enable the AES block cipher. + * + * Module: library/aes.c + * Caller: library/cipher.c + * library/pem.c + * library/ctr_drbg.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * + * PEM_PARSE uses AES for decrypting encrypted keys. + */ +#define MBEDTLS_AES_C + +/** + * \def MBEDTLS_ASN1_PARSE_C + * + * Enable the generic ASN1 parser. + * + * Module: library/asn1.c + * Caller: library/x509.c + * library/dhm.c + * library/pkcs12.c + * library/pkcs5.c + * library/pkparse.c + */ +#define MBEDTLS_ASN1_PARSE_C + +/** + * \def MBEDTLS_ASN1_WRITE_C + * + * Enable the generic ASN1 writer. + * + * Module: library/asn1write.c + * Caller: library/ecdsa.c + * library/pkwrite.c + * library/x509_create.c + * library/x509write_crt.c + * library/x509write_csr.c + */ +#define MBEDTLS_ASN1_WRITE_C + +/** + * \def MBEDTLS_BASE64_C + * + * Enable the Base64 module. + * + * Module: library/base64.c + * Caller: library/pem.c + * + * This module is required for PEM support (required by X.509). + */ +#define MBEDTLS_BASE64_C + +/** + * \def MBEDTLS_BIGNUM_C + * + * Enable the multi-precision integer library. + * + * Module: library/bignum.c + * library/bignum_core.c + * library/bignum_mod.c + * library/bignum_mod_raw.c + * Caller: library/dhm.c + * library/ecp.c + * library/ecdsa.c + * library/rsa.c + * library/rsa_alt_helpers.c + * library/ssl_tls.c + * + * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support. + */ +#define MBEDTLS_BIGNUM_C + +/** + * \def MBEDTLS_CAMELLIA_C + * + * Enable the Camellia block cipher. + * + * Module: library/camellia.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_CAMELLIA_C + +/** + * \def MBEDTLS_ARIA_C + * + * Enable the ARIA block cipher. + * + * Module: library/aria.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * + * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 + */ +#define MBEDTLS_ARIA_C + +/** + * \def MBEDTLS_CCM_C + * + * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher. + * + * Module: library/ccm.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C or + * MBEDTLS_ARIA_C + * + * This module enables the AES-CCM ciphersuites, if other requisites are + * enabled as well. + */ +#define MBEDTLS_CCM_C + +/** + * \def MBEDTLS_CHACHA20_C + * + * Enable the ChaCha20 stream cipher. + * + * Module: library/chacha20.c + */ +#define MBEDTLS_CHACHA20_C + +/** + * \def MBEDTLS_CHACHAPOLY_C + * + * Enable the ChaCha20-Poly1305 AEAD algorithm. + * + * Module: library/chachapoly.c + * + * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C + */ +#define MBEDTLS_CHACHAPOLY_C + +/** + * \def MBEDTLS_CIPHER_C + * + * Enable the generic cipher layer. + * + * Module: library/cipher.c + * Caller: library/ccm.c + * library/cmac.c + * library/gcm.c + * library/nist_kw.c + * library/pkcs12.c + * library/pkcs5.c + * library/psa_crypto_aead.c + * library/psa_crypto_mac.c + * library/ssl_ciphersuites.c + * library/ssl_msg.c + * library/ssl_ticket.c (unless MBEDTLS_USE_PSA_CRYPTO is enabled) + * + * Uncomment to enable generic cipher wrappers. + */ +#define MBEDTLS_CIPHER_C + +/** + * \def MBEDTLS_CMAC_C + * + * Enable the CMAC (Cipher-based Message Authentication Code) mode for block + * ciphers. + * + * \note When #MBEDTLS_CMAC_ALT is active, meaning that the underlying + * implementation of the CMAC algorithm is provided by an alternate + * implementation, that alternate implementation may opt to not support + * AES-192 or 3DES as underlying block ciphers for the CMAC operation. + * + * Module: library/cmac.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_DES_C + * + */ +#define MBEDTLS_CMAC_C + +/** + * \def MBEDTLS_CTR_DRBG_C + * + * Enable the CTR_DRBG AES-based random generator. + * The CTR_DRBG generator uses AES-256 by default. + * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above. + * + * \note AES-128 will be used if \c MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH is set. + * + * \note To achieve a 256-bit security strength with CTR_DRBG, + * you must use AES-256 *and* use sufficient entropy. + * See ctr_drbg.h for more details. + * + * Module: library/ctr_drbg.c + * Caller: + * + * Requires: MBEDTLS_AES_C + * + * This module provides the CTR_DRBG AES random number generator. + */ +#define MBEDTLS_CTR_DRBG_C + +/** + * \def MBEDTLS_DEBUG_C + * + * Enable the debug functions. + * + * Module: library/debug.c + * Caller: library/ssl_msg.c + * library/ssl_tls.c + * library/ssl_tls12_*.c + * library/ssl_tls13_*.c + * + * This module provides debugging functions. + */ +#define MBEDTLS_DEBUG_C + +/** + * \def MBEDTLS_DES_C + * + * Enable the DES block cipher. + * + * Module: library/des.c + * Caller: library/pem.c + * library/cipher.c + * + * PEM_PARSE uses DES/3DES for decrypting encrypted keys. + * + * \warning DES/3DES are considered weak ciphers and their use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +#define MBEDTLS_DES_C + +/** + * \def MBEDTLS_DHM_C + * + * Enable the Diffie-Hellman-Merkle module. + * + * Module: library/dhm.c + * Caller: library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * This module is used by the following key exchanges: + * DHE-RSA, DHE-PSK + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_DHM_C + +/** + * \def MBEDTLS_ECDH_C + * + * Enable the elliptic curve Diffie-Hellman library. + * + * Module: library/ecdh.c + * Caller: library/psa_crypto.c + * library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK + * + * Requires: MBEDTLS_ECP_C + */ +#define MBEDTLS_ECDH_C + +/** + * \def MBEDTLS_ECDSA_C + * + * Enable the elliptic curve DSA library. + * + * Module: library/ecdsa.c + * Caller: + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C, + * and at least one MBEDTLS_ECP_DP_XXX_ENABLED for a + * short Weierstrass curve. + */ +#define MBEDTLS_ECDSA_C + +/** + * \def MBEDTLS_ECJPAKE_C + * + * Enable the elliptic curve J-PAKE library. + * + * \note EC J-PAKE support is based on the Thread v1.0.0 specification. + * It has not been reviewed for compliance with newer standards such as + * Thread v1.1 or RFC 8236. + * + * Module: library/ecjpake.c + * Caller: + * + * This module is used by the following key exchanges: + * ECJPAKE + * + * Requires: MBEDTLS_ECP_C and either MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any EC J-PAKE operations. + */ +#define MBEDTLS_ECJPAKE_C + +/** + * \def MBEDTLS_ECP_C + * + * Enable the elliptic curve over GF(p) library. + * + * Module: library/ecp.c + * Caller: library/ecdh.c + * library/ecdsa.c + * library/ecjpake.c + * + * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED + */ +#define MBEDTLS_ECP_C + +/** + * \def MBEDTLS_ENTROPY_C + * + * Enable the platform-specific entropy code. + * + * Module: library/entropy.c + * Caller: + * + * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C + * + * This module provides a generic entropy pool + */ +#define MBEDTLS_ENTROPY_C + +/** + * \def MBEDTLS_ERROR_C + * + * Enable error code to error string conversion. + * + * Module: library/error.c + * Caller: + * + * This module enables mbedtls_strerror(). + */ +#define MBEDTLS_ERROR_C + +/** + * \def MBEDTLS_GCM_C + * + * Enable the Galois/Counter Mode (GCM). + * + * Module: library/gcm.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C or + * MBEDTLS_ARIA_C + * + * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other + * requisites are enabled as well. + */ +#define MBEDTLS_GCM_C + +/** + * \def MBEDTLS_HKDF_C + * + * Enable the HKDF algorithm (RFC 5869). + * + * Module: library/hkdf.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the Hashed Message Authentication Code + * (HMAC)-based key derivation function (HKDF). + */ +#define MBEDTLS_HKDF_C + +/** + * \def MBEDTLS_HMAC_DRBG_C + * + * Enable the HMAC_DRBG random generator. + * + * Module: library/hmac_drbg.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * Uncomment to enable the HMAC_DRBG random number generator. + */ +#define MBEDTLS_HMAC_DRBG_C + +/** + * \def MBEDTLS_LMS_C + * + * Enable the LMS stateful-hash asymmetric signature algorithm. + * + * Module: library/lms.c + * Caller: + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * Uncomment to enable the LMS verification algorithm and public key operations. + */ +#define MBEDTLS_LMS_C + +/** + * \def MBEDTLS_LMS_PRIVATE + * + * Enable LMS private-key operations and signing code. Functions enabled by this + * option are experimental, and should not be used in production. + * + * Requires: MBEDTLS_LMS_C + * + * Uncomment to enable the LMS signature algorithm and private key operations. + */ +//#define MBEDTLS_LMS_PRIVATE + +/** + * \def MBEDTLS_NIST_KW_C + * + * Enable the Key Wrapping mode for 128-bit block ciphers, + * as defined in NIST SP 800-38F. Only KW and KWP modes + * are supported. At the moment, only AES is approved by NIST. + * + * Module: library/nist_kw.c + * + * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C + */ +#define MBEDTLS_NIST_KW_C + +/** + * \def MBEDTLS_MD_C + * + * Enable the generic layer for message digest (hashing) and HMAC. + * + * Requires: one of: MBEDTLS_MD5_C, MBEDTLS_RIPEMD160_C, MBEDTLS_SHA1_C, + * MBEDTLS_SHA224_C, MBEDTLS_SHA256_C, MBEDTLS_SHA384_C, + * MBEDTLS_SHA512_C, or MBEDTLS_PSA_CRYPTO_C with at least + * one hash. + * Module: library/md.c + * Caller: library/constant_time.c + * library/ecdsa.c + * library/ecjpake.c + * library/hkdf.c + * library/hmac_drbg.c + * library/pk.c + * library/pkcs5.c + * library/pkcs12.c + * library/psa_crypto_ecp.c + * library/psa_crypto_rsa.c + * library/rsa.c + * library/ssl_cookie.c + * library/ssl_msg.c + * library/ssl_tls.c + * library/x509.c + * library/x509_crt.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * Uncomment to enable generic message digest wrappers. + */ +#define MBEDTLS_MD_C + +/** + * \def MBEDTLS_MD5_C + * + * Enable the MD5 hash algorithm. + * + * Module: library/md5.c + * Caller: library/md.c + * library/pem.c + * library/ssl_tls.c + * + * This module is required for TLS 1.2 depending on the handshake parameters. + * Further, it is used for checking MD5-signed certificates, and for PBKDF1 + * when decrypting PEM-encoded encrypted keys. + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_MD5_C + +/** + * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Enable the buffer allocator implementation that makes use of a (stack) + * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() + * calls) + * + * Module: library/memory_buffer_alloc.c + * + * Requires: MBEDTLS_PLATFORM_C + * MBEDTLS_PLATFORM_MEMORY (to use it within Mbed TLS) + * + * Enable this module to enable the buffer memory allocator. + */ +//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +/** + * \def MBEDTLS_NET_C + * + * Enable the TCP and UDP over IPv6/IPv4 networking routines. + * + * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) + * and Windows. For other platforms, you'll want to disable it, and write your + * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/net_sockets.c + * + * This module provides networking routines. + */ +#define MBEDTLS_NET_C + +/** + * \def MBEDTLS_OID_C + * + * Enable the OID database. + * + * Module: library/oid.c + * Caller: library/asn1write.c + * library/pkcs5.c + * library/pkparse.c + * library/pkwrite.c + * library/rsa.c + * library/x509.c + * library/x509_create.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * This modules translates between OIDs and internal values. + */ +#define MBEDTLS_OID_C + +/** + * \def MBEDTLS_PADLOCK_C + * + * Enable VIA Padlock support on x86. + * + * Module: library/padlock.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the VIA PadLock on x86. + */ +#define MBEDTLS_PADLOCK_C + +/** + * \def MBEDTLS_PEM_PARSE_C + * + * Enable PEM decoding / parsing. + * + * Module: library/pem.c + * Caller: library/dhm.c + * library/pkparse.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_BASE64_C + * optionally MBEDTLS_MD5_C, or PSA Crypto with MD5 (see below) + * + * \warning When parsing password-protected files, if MD5 is provided only by + * a PSA driver, you must call psa_crypto_init() before the first file. + * + * This modules adds support for decoding / parsing PEM files. + */ +#define MBEDTLS_PEM_PARSE_C + +/** + * \def MBEDTLS_PEM_WRITE_C + * + * Enable PEM encoding / writing. + * + * Module: library/pem.c + * Caller: library/pkwrite.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for encoding / writing PEM files. + */ +#define MBEDTLS_PEM_WRITE_C + +/** + * \def MBEDTLS_PK_C + * + * Enable the generic public (asymmetric) key layer. + * + * Module: library/pk.c + * Caller: library/psa_crypto_rsa.c + * library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * library/x509.c + * + * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C or MBEDTLS_ECP_C + * + * Uncomment to enable generic public key wrappers. + */ +#define MBEDTLS_PK_C + +/** + * \def MBEDTLS_PK_PARSE_C + * + * Enable the generic public (asymmetric) key parser. + * + * Module: library/pkparse.c + * Caller: library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key parse functions. + */ +#define MBEDTLS_PK_PARSE_C + +/** + * \def MBEDTLS_PK_WRITE_C + * + * Enable the generic public (asymmetric) key writer. + * + * Module: library/pkwrite.c + * Caller: library/x509write.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key write functions. + */ +#define MBEDTLS_PK_WRITE_C + +/** + * \def MBEDTLS_PKCS5_C + * + * Enable PKCS#5 functions. + * + * Module: library/pkcs5.c + * + * Requires: MBEDTLS_CIPHER_C + * Auto-enables: MBEDTLS_MD_C + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS5 operations. + * + * This module adds support for the PKCS#5 functions. + */ +#define MBEDTLS_PKCS5_C + +/** + * \def MBEDTLS_PKCS7_C + * + * Enable PKCS #7 core for using PKCS #7-formatted signatures. + * RFC Link - https://tools.ietf.org/html/rfc2315 + * + * Module: library/pkcs7.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * MBEDTLS_X509_CRT_PARSE_C MBEDTLS_X509_CRL_PARSE_C, + * MBEDTLS_BIGNUM_C, MBEDTLS_MD_C + * + * This module is required for the PKCS #7 parsing modules. + */ +#define MBEDTLS_PKCS7_C + +/** + * \def MBEDTLS_PKCS12_C + * + * Enable PKCS#12 PBE functions. + * Adds algorithms for parsing PKCS#8 encrypted private keys + * + * Module: library/pkcs12.c + * Caller: library/pkparse.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C and either + * MBEDTLS_MD_C or MBEDTLS_PSA_CRYPTO_C. + * + * \warning If using a hash that is only provided by PSA drivers, you must + * call psa_crypto_init() before doing any PKCS12 operations. + * + * This module enables PKCS#12 functions. + */ +#define MBEDTLS_PKCS12_C + +/** + * \def MBEDTLS_PLATFORM_C + * + * Enable the platform abstraction layer that allows you to re-assign + * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). + * + * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT + * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned + * above to be specified at runtime or compile time respectively. + * + * \note This abstraction layer must be enabled on Windows (including MSYS2) + * as other modules rely on it for a fixed snprintf implementation. + * + * Module: library/platform.c + * Caller: Most other .c files + * + * This module enables abstraction of common (libc) functions. + */ +#define MBEDTLS_PLATFORM_C + +/** + * \def MBEDTLS_POLY1305_C + * + * Enable the Poly1305 MAC algorithm. + * + * Module: library/poly1305.c + * Caller: library/chachapoly.c + */ +#define MBEDTLS_POLY1305_C + +/** + * \def MBEDTLS_PSA_CRYPTO_C + * + * Enable the Platform Security Architecture cryptography API. + * + * Module: library/psa_crypto.c + * + * Requires: MBEDTLS_CIPHER_C, + * either MBEDTLS_CTR_DRBG_C and MBEDTLS_ENTROPY_C, + * or MBEDTLS_HMAC_DRBG_C and MBEDTLS_ENTROPY_C, + * or MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. + * + */ +#define MBEDTLS_PSA_CRYPTO_C + +/** + * \def MBEDTLS_PSA_CRYPTO_SE_C + * + * Enable dynamic secure element support in the Platform Security Architecture + * cryptography API. + * + * \deprecated This feature is deprecated. Please switch to the PSA driver + * interface. + * + * Module: library/psa_crypto_se.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, MBEDTLS_PSA_CRYPTO_STORAGE_C + * + */ +//#define MBEDTLS_PSA_CRYPTO_SE_C + +/** + * \def MBEDTLS_PSA_CRYPTO_STORAGE_C + * + * Enable the Platform Security Architecture persistent key storage. + * + * Module: library/psa_crypto_storage.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, + * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of + * the PSA ITS interface + */ +#define MBEDTLS_PSA_CRYPTO_STORAGE_C + +/** + * \def MBEDTLS_PSA_ITS_FILE_C + * + * Enable the emulation of the Platform Security Architecture + * Internal Trusted Storage (PSA ITS) over files. + * + * Module: library/psa_its_file.c + * + * Requires: MBEDTLS_FS_IO + */ +#define MBEDTLS_PSA_ITS_FILE_C + +/** + * \def MBEDTLS_RIPEMD160_C + * + * Enable the RIPEMD-160 hash algorithm. + * + * Module: library/ripemd160.c + * Caller: library/md.c + * + */ +#define MBEDTLS_RIPEMD160_C + +/** + * \def MBEDTLS_RSA_C + * + * Enable the RSA public-key cryptosystem. + * + * Module: library/rsa.c + * library/rsa_alt_helpers.c + * Caller: library/pk.c + * library/psa_crypto.c + * library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * This module is used by the following key exchanges: + * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C + */ +#define MBEDTLS_RSA_C + +/** + * \def MBEDTLS_SHA1_C + * + * Enable the SHA1 cryptographic hash algorithm. + * + * Module: library/sha1.c + * Caller: library/md.c + * library/psa_crypto_hash.c + * + * This module is required for TLS 1.2 depending on the handshake parameters, + * and for SHA1-signed certificates. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_SHA1_C + +/** + * \def MBEDTLS_SHA224_C + * + * Enable the SHA-224 cryptographic hash algorithm. + * + * Module: library/sha256.c + * Caller: library/md.c + * library/ssl_cookie.c + * + * This module adds support for SHA-224. + */ +#define MBEDTLS_SHA224_C + +/** + * \def MBEDTLS_SHA256_C + * + * Enable the SHA-256 cryptographic hash algorithm. + * + * Module: library/sha256.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * This module adds support for SHA-256. + * This module is required for the SSL/TLS 1.2 PRF function. + */ +#define MBEDTLS_SHA256_C + +/** + * \def MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT + * + * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions if they are available at runtime. + * If not, the library will fall back to the C implementation. + * + * \note If MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT is defined when building + * for a non-Aarch64 build it will be silently ignored. + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the + * same time as MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY. + * + * Requires: MBEDTLS_SHA256_C. + * + * Module: library/sha256.c + * + * Uncomment to have the library check for the A64 SHA-256 crypto extensions + * and use them if available. + */ +//#define MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT + +/** + * \def MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY + * + * Enable acceleration of the SHA-256 and SHA-224 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions, which must be available at runtime + * or else an illegal instruction fault will occur. + * + * \note This allows builds with a smaller code size than with + * MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT + * + * \note Minimum compiler versions for this feature are Clang 4.0, + * armclang 6.6 or GCC 6.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8-a+crypto for + * armclang <= 6.9 + * + * \warning MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY cannot be defined at the same + * time as MBEDTLS_SHA256_USE_A64_CRYPTO_IF_PRESENT. + * + * Requires: MBEDTLS_SHA256_C. + * + * Module: library/sha256.c + * + * Uncomment to have the library use the A64 SHA-256 crypto extensions + * unconditionally. + */ +//#define MBEDTLS_SHA256_USE_A64_CRYPTO_ONLY + +/** + * \def MBEDTLS_SHA384_C + * + * Enable the SHA-384 cryptographic hash algorithm. + * + * Module: library/sha512.c + * Caller: library/md.c + * library/psa_crypto_hash.c + * library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * Comment to disable SHA-384 + */ +#define MBEDTLS_SHA384_C + +/** + * \def MBEDTLS_SHA512_C + * + * Enable SHA-512 cryptographic hash algorithms. + * + * Module: library/sha512.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_tls.c + * library/ssl_cookie.c + * + * This module adds support for SHA-512. + */ +#define MBEDTLS_SHA512_C + +/** + * \def MBEDTLS_SHA3_C + * + * Enable the SHA3 cryptographic hash algorithm. + * + * Module: library/sha3.c + * + * This module adds support for SHA3. + */ +#define MBEDTLS_SHA3_C + +/** + * \def MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + * + * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions if they are available at runtime. + * If not, the library will fall back to the C implementation. + * + * \note If MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT is defined when building + * for a non-Aarch64 build it will be silently ignored. + * + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 + * + * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT cannot be defined at the + * same time as MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY. + * + * Requires: MBEDTLS_SHA512_C. + * + * Module: library/sha512.c + * + * Uncomment to have the library check for the A64 SHA-512 crypto extensions + * and use them if available. + */ +//#define MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + +/** + * \def MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY + * + * Enable acceleration of the SHA-512 and SHA-384 cryptographic hash algorithms + * with the ARMv8 cryptographic extensions, which must be available at runtime + * or else an illegal instruction fault will occur. + * + * \note This allows builds with a smaller code size than with + * MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT + * + * \note Minimum compiler versions for this feature are Clang 7.0, + * armclang 6.9 or GCC 8.0. + * + * \note \c CFLAGS must be set to a minimum of \c -march=armv8.2-a+sha3 for + * armclang 6.9 + * + * \warning MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY cannot be defined at the same + * time as MBEDTLS_SHA512_USE_A64_CRYPTO_IF_PRESENT. + * + * Requires: MBEDTLS_SHA512_C. + * + * Module: library/sha512.c + * + * Uncomment to have the library use the A64 SHA-512 crypto extensions + * unconditionally. + */ +//#define MBEDTLS_SHA512_USE_A64_CRYPTO_ONLY + +/** + * \def MBEDTLS_SSL_CACHE_C + * + * Enable simple SSL cache implementation. + * + * Module: library/ssl_cache.c + * Caller: + * + * Requires: MBEDTLS_SSL_CACHE_C + */ +#define MBEDTLS_SSL_CACHE_C + +/** + * \def MBEDTLS_SSL_COOKIE_C + * + * Enable basic implementation of DTLS cookies for hello verification. + * + * Module: library/ssl_cookie.c + * Caller: + */ +#define MBEDTLS_SSL_COOKIE_C + +/** + * \def MBEDTLS_SSL_TICKET_C + * + * Enable an implementation of TLS server-side callbacks for session tickets. + * + * Module: library/ssl_ticket.c + * Caller: + * + * Requires: (MBEDTLS_CIPHER_C || MBEDTLS_USE_PSA_CRYPTO) && + * (MBEDTLS_GCM_C || MBEDTLS_CCM_C || MBEDTLS_CHACHAPOLY_C) + */ +#define MBEDTLS_SSL_TICKET_C + +/** + * \def MBEDTLS_SSL_CLI_C + * + * Enable the SSL/TLS client code. + * + * Module: library/ssl*_client.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS client support. + */ +#define MBEDTLS_SSL_CLI_C + +/** + * \def MBEDTLS_SSL_SRV_C + * + * Enable the SSL/TLS server code. + * + * Module: library/ssl*_server.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS server support. + */ +#define MBEDTLS_SSL_SRV_C + +/** + * \def MBEDTLS_SSL_TLS_C + * + * Enable the generic SSL/TLS code. + * + * Module: library/ssl_tls.c + * Caller: library/ssl*_client.c + * library/ssl*_server.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * and at least one of the MBEDTLS_SSL_PROTO_XXX defines + * + * This module is required for SSL/TLS. + */ +#define MBEDTLS_SSL_TLS_C + +/** + * \def MBEDTLS_THREADING_C + * + * Enable the threading abstraction layer. + * By default Mbed TLS assumes it is used in a non-threaded environment or that + * contexts are not shared between threads. If you do intend to use contexts + * between threads, you will need to enable this layer to prevent race + * conditions. See also our Knowledge Base article about threading: + * https://mbed-tls.readthedocs.io/en/latest/kb/development/thread-safety-and-multi-threading + * + * Module: library/threading.c + * + * This allows different threading implementations (self-implemented or + * provided). + * + * You will have to enable either MBEDTLS_THREADING_ALT or + * MBEDTLS_THREADING_PTHREAD. + * + * Enable this layer to allow use of mutexes within Mbed TLS + */ +//#define MBEDTLS_THREADING_C + +/** + * \def MBEDTLS_TIMING_C + * + * Enable the semi-portable timing interface. + * + * \note The provided implementation only works on POSIX/Unix (including Linux, + * BSD and OS X) and Windows. On other platforms, you can either disable that + * module and provide your own implementations of the callbacks needed by + * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide + * your own implementation of the whole module by setting + * \c MBEDTLS_TIMING_ALT in the current file. + * + * \note The timing module will include time.h on suitable platforms + * regardless of the setting of MBEDTLS_HAVE_TIME, unless + * MBEDTLS_TIMING_ALT is used. See timing.c for more information. + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/timing.c + */ +#define MBEDTLS_TIMING_C + +/** + * \def MBEDTLS_VERSION_C + * + * Enable run-time version information. + * + * Module: library/version.c + * + * This module provides run-time version information. + */ +#define MBEDTLS_VERSION_C + +/** + * \def MBEDTLS_X509_USE_C + * + * Enable X.509 core for using certificates. + * + * Module: library/x509.c + * Caller: library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call + * psa_crypto_init() before doing any X.509 operation. + * + * This module is required for the X.509 parsing modules. + */ +#define MBEDTLS_X509_USE_C + +/** + * \def MBEDTLS_X509_CRT_PARSE_C + * + * Enable X.509 certificate parsing. + * + * Module: library/x509_crt.c + * Caller: library/ssl_tls.c + * library/ssl*_client.c + * library/ssl*_server.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 certificate parsing. + */ +#define MBEDTLS_X509_CRT_PARSE_C + +/** + * \def MBEDTLS_X509_CRL_PARSE_C + * + * Enable X.509 CRL parsing. + * + * Module: library/x509_crl.c + * Caller: library/x509_crt.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 CRL parsing. + */ +#define MBEDTLS_X509_CRL_PARSE_C + +/** + * \def MBEDTLS_X509_CSR_PARSE_C + * + * Enable X.509 Certificate Signing Request (CSR) parsing. + * + * Module: library/x509_csr.c + * Caller: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is used for reading X.509 certificate request. + */ +#define MBEDTLS_X509_CSR_PARSE_C + +/** + * \def MBEDTLS_X509_CREATE_C + * + * Enable X.509 core for creating certificates. + * + * Module: library/x509_create.c + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_PARSE_C, + * (MBEDTLS_MD_C or MBEDTLS_USE_PSA_CRYPTO) + * + * \warning If building with MBEDTLS_USE_PSA_CRYPTO, you must call + * psa_crypto_init() before doing any X.509 create operation. + * + * This module is the basis for creating X.509 certificates and CSRs. + */ +#define MBEDTLS_X509_CREATE_C + +/** + * \def MBEDTLS_X509_CRT_WRITE_C + * + * Enable creating X.509 certificates. + * + * Module: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate creation. + */ +#define MBEDTLS_X509_CRT_WRITE_C + +/** + * \def MBEDTLS_X509_CSR_WRITE_C + * + * Enable creating X.509 Certificate Signing Requests (CSR). + * + * Module: library/x509_csr_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate request writing. + */ +#define MBEDTLS_X509_CSR_WRITE_C + +/** \} name SECTION: Mbed TLS modules */ + +/** + * \name SECTION: General configuration options + * + * This section contains Mbed TLS build settings that are not associated + * with a particular module. + * + * \{ + */ + +/** + * \def MBEDTLS_CONFIG_FILE + * + * If defined, this is a header which will be included instead of + * `"mbedtls/mbedtls_config.h"`. + * This header file specifies the compile-time configuration of Mbed TLS. + * Unlike other configuration options, this one must be defined on the + * compiler command line: a definition in `mbedtls_config.h` would have + * no effect. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_CONFIG_FILE "mbedtls/mbedtls_config.h" + +/** + * \def MBEDTLS_USER_CONFIG_FILE + * + * If defined, this is a header which will be included after + * `"mbedtls/mbedtls_config.h"` or #MBEDTLS_CONFIG_FILE. + * This allows you to modify the default configuration, including the ability + * to undefine options that are enabled by default. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_USER_CONFIG_FILE "/dev/null" + +/** + * \def MBEDTLS_PSA_CRYPTO_CONFIG_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_config.h"`. + * This header file specifies which cryptographic mechanisms are available + * through the PSA API when #MBEDTLS_PSA_CRYPTO_CONFIG is enabled, and + * is not used when #MBEDTLS_PSA_CRYPTO_CONFIG is disabled. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_PSA_CRYPTO_CONFIG_FILE "psa/crypto_config.h" + +/** + * \def MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE + * + * If defined, this is a header which will be included after + * `"psa/crypto_config.h"` or #MBEDTLS_PSA_CRYPTO_CONFIG_FILE. + * This allows you to modify the default configuration, including the ability + * to undefine options that are enabled by default. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_PSA_CRYPTO_USER_CONFIG_FILE "/dev/null" + +/** + * \def MBEDTLS_PSA_CRYPTO_PLATFORM_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_platform.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the platform on + * which the library code will run. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_PSA_CRYPTO_PLATFORM_FILE "psa/crypto_platform_alt.h" + +/** + * \def MBEDTLS_PSA_CRYPTO_STRUCT_FILE + * + * If defined, this is a header which will be included instead of + * `"psa/crypto_struct.h"`. This file should declare the same identifiers + * as the one in Mbed TLS, but with definitions adapted to the environment + * in which the library code will run. The typical use for this feature + * is to provide alternative type definitions on the client side in + * client-server integrations of PSA crypto, where operation structures + * contain handles instead of cryptographic data. + * + * \note The required content of this header can vary from one version of + * Mbed TLS to the next. Integrators who provide an alternative file + * should review the changes in the original file whenever they + * upgrade Mbed TLS. + * + * This macro is expanded after an \#include directive. This is a popular but + * non-standard feature of the C language, so this feature is only available + * with compilers that perform macro expansion on an \#include line. + * + * The value of this symbol is typically a path in double quotes, either + * absolute or relative to a directory on the include search path. + */ +//#define MBEDTLS_PSA_CRYPTO_STRUCT_FILE "psa/crypto_struct_alt.h" + +/** \} name SECTION: General configuration options */ + +/** + * \name SECTION: Module configuration options + * + * This section allows for the setting of module specific sizes and + * configuration options. The default values are already present in the + * relevant header files and should suffice for the regular use cases. + * + * Our advice is to enable options and change their values here + * only if you have a good reason and know the consequences. + * \{ + */ +/* The Doxygen documentation here is used when a user comments out a + * setting and runs doxygen themselves. On the other hand, when we typeset + * the full documentation including disabled settings, the documentation + * in specific modules' header files is used if present. When editing this + * file, make sure that each option is documented in exactly one place, + * plus optionally a same-line Doxygen comment here if there is a Doxygen + * comment in the specific module. */ + +/* MPI / BIGNUM options */ +//#define MBEDTLS_MPI_WINDOW_SIZE 2 /**< Maximum window size used. */ +//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ + +/* CTR_DRBG options */ +//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ +//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* HMAC_DRBG options */ +//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* ECP options */ +//#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */ +//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ + +/* Entropy options */ +//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ + +/* Memory buffer allocator options */ +//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ + +/* Platform options */ +//#define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ + +/** \def MBEDTLS_PLATFORM_STD_CALLOC + * + * Default allocator to use, can be undefined. + * It must initialize the allocated buffer memory to zeroes. + * The size of the buffer is the product of the two parameters. + * The calloc function returns either a null pointer or a pointer to the allocated space. + * If the product is 0, the function may either return NULL or a valid pointer to an array of size 0 which is a valid input to the deallocation function. + * An uninitialized #MBEDTLS_PLATFORM_STD_CALLOC always fails, returning a null pointer. + * See the description of #MBEDTLS_PLATFORM_MEMORY for more details. + * The corresponding deallocation function is #MBEDTLS_PLATFORM_STD_FREE. + */ +//#define MBEDTLS_PLATFORM_STD_CALLOC calloc + +/** \def MBEDTLS_PLATFORM_STD_FREE + * + * Default free to use, can be undefined. + * NULL is a valid parameter, and the function must do nothing. + * A non-null parameter will always be a pointer previously returned by #MBEDTLS_PLATFORM_STD_CALLOC and not yet freed. + * An uninitialized #MBEDTLS_PLATFORM_STD_FREE does not do anything. + * See the description of #MBEDTLS_PLATFORM_MEMORY for more details (same principles as for MBEDTLS_PLATFORM_STD_CALLOC apply). + */ +//#define MBEDTLS_PLATFORM_STD_FREE free +//#define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< Default setbuf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ + +/* To use the following function macros, MBEDTLS_PLATFORM_C must be enabled. */ +/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ +//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_CALLOC for requirements. */ +//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined. See MBEDTLS_PLATFORM_STD_FREE for requirements. */ +//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_SETBUF_MACRO setbuf /**< Default setbuf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf /**< Default vsnprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t //#define MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO int64_t /**< Default milliseconds time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled. It must be signed, and at least 64 bits. If it is changed from the default, MBEDTLS_PRINTF_MS_TIME must be updated to match.*/ +//#define MBEDTLS_PRINTF_MS_TIME PRId64 /**< Default fmt for printf. That's avoid compiler warning if mbedtls_ms_time_t is redefined */ + +/** \def MBEDTLS_CHECK_RETURN + * + * This macro is used at the beginning of the declaration of a function + * to indicate that its return value should be checked. It should + * instruct the compiler to emit a warning or an error if the function + * is called without checking its return value. + * + * There is a default implementation for popular compilers in platform_util.h. + * You can override the default implementation by defining your own here. + * + * If the implementation here is empty, this will effectively disable the + * checking of functions' return values. + */ +//#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) + +/** \def MBEDTLS_IGNORE_RETURN + * + * This macro requires one argument, which should be a C function call. + * If that function call would cause a #MBEDTLS_CHECK_RETURN warning, this + * warning is suppressed. + */ +//#define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) + +/* PSA options */ +/** + * Use HMAC_DRBG with the specified hash algorithm for HMAC_DRBG for the + * PSA crypto subsystem. + * + * If this option is unset: + * - If CTR_DRBG is available, the PSA subsystem uses it rather than HMAC_DRBG. + * - Otherwise, the PSA subsystem uses HMAC_DRBG with either + * #MBEDTLS_MD_SHA512 or #MBEDTLS_MD_SHA256 based on availability and + * on unspecified heuristics. + */ +//#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 + +/** \def MBEDTLS_PSA_KEY_SLOT_COUNT + * Restrict the PSA library to supporting a maximum amount of simultaneously + * loaded keys. A loaded key is a key stored by the PSA Crypto core as a + * volatile key, or a persistent key which is loaded temporarily by the + * library as part of a crypto operation in flight. + * + * If this option is unset, the library will fall back to a default value of + * 32 keys. + */ +//#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 + +/* RSA OPTIONS */ +//#define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 /**< Minimum RSA key size that can be generated in bits (Minimum possible value is 128 bits) */ + +/* SSL Cache options */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ + +/* SSL options */ + +/** \def MBEDTLS_SSL_IN_CONTENT_LEN + * + * Maximum length (in bytes) of incoming plaintext fragments. + * + * This determines the size of the incoming TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of the incoming I/O buffer. + */ +//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_CID_IN_LEN_MAX + * + * The maximum length of CIDs used for incoming DTLS messages. + * + */ +//#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_OUT_LEN_MAX + * + * The maximum length of CIDs used for outgoing DTLS messages. + * + */ +//#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY + * + * This option controls the use of record plaintext padding + * in TLS 1.3 and when using the Connection ID extension in DTLS 1.2. + * + * The padding will always be chosen so that the length of the + * padded plaintext is a multiple of the value of this option. + * + * Note: A value of \c 1 means that no padding will be used + * for outgoing records. + * + * Note: On systems lacking division instructions, + * a power of two should be preferred. + */ +//#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 + +/** \def MBEDTLS_SSL_OUT_CONTENT_LEN + * + * Maximum length (in bytes) of outgoing plaintext fragments. + * + * This determines the size of the outgoing TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * It is possible to save RAM by setting a smaller outward buffer, while keeping + * the default inward 16384 byte buffer to conform to the TLS specification. + * + * The minimum required outward buffer size is determined by the handshake + * protocol's usage. Handshaking will fail if the outward buffer is too small. + * The specific size requirement depends on the configured ciphers and any + * certificate data which is sent during the handshake. + * + * Uncomment to set the maximum plaintext size of the outgoing I/O buffer. + */ +//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING + * + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + * + * This should be at least 9/8 * MBEDTLS_SSL_IN_CONTENT_LEN + * to account for a reassembled handshake message of maximum size, + * together with its reassembly bitmap. + * + * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) + * should be sufficient for all practical situations as it allows + * to reassembly a large handshake message (such as a certificate) + * while buffering multiple smaller handshake messages. + * + */ +//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 + +//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 or 384 bits) */ +//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ + +/** + * Complete list of ciphersuites to use, in order of preference. + * + * \warning No dependency checking is done on that field! This option can only + * be used to restrict the set of available ciphersuites. It is your + * responsibility to make sure the needed modules are active. + * + * Use this to save a few hundred bytes of ROM (default ordering of all + * available ciphersuites) and a few to a few hundred bytes of RAM. + * + * The value below is only an example, not the default. + */ +//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +/** + * \def MBEDTLS_SSL_MAX_EARLY_DATA_SIZE + * + * The default maximum amount of 0-RTT data. See the documentation of + * \c mbedtls_ssl_tls13_conf_max_early_data_size() for more information. + * + * It must be positive and smaller than UINT32_MAX. + * + * If MBEDTLS_SSL_EARLY_DATA is not defined, this default value does not + * have any impact on the build. + * + * This feature is experimental, not completed and thus not ready for + * production. + * + */ +//#define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 + +/** + * \def MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE + * + * Maximum time difference in milliseconds tolerated between the age of a + * ticket from the server and client point of view. + * From the client point of view, the age of a ticket is the time difference + * between the time when the client proposes to the server to use the ticket + * (time of writing of the Pre-Shared Key Extension including the ticket) and + * the time the client received the ticket from the server. + * From the server point of view, the age of a ticket is the time difference + * between the time when the server receives a proposition from the client + * to use the ticket and the time when the ticket was created by the server. + * The server age is expected to be always greater than the client one and + * MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE defines the + * maximum difference tolerated for the server to accept the ticket. + * This is not used in TLS 1.2. + * + */ +//#define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 + +/** + * \def MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH + * + * Size in bytes of a ticket nonce. This is not used in TLS 1.2. + * + * This must be less than 256. + */ +//#define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 + +/** + * \def MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS + * + * Default number of NewSessionTicket messages to be sent by a TLS 1.3 server + * after handshake completion. This is not used in TLS 1.2 and relevant only if + * the MBEDTLS_SSL_SESSION_TICKETS option is enabled. + * + */ +//#define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 + +/* X509 options */ +//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ +//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ + +/** \} name SECTION: Module configuration options */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md.h index a6858b2..326bbab 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md.h @@ -1,648 +1,648 @@ -/** - * \file md.h - * - * \brief This file contains the generic functions for message-digest - * (hashing) and HMAC. - * - * \author Adriaan de Jong - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_MD_H -#define MBEDTLS_MD_H -#include "mbedtls/private_access.h" - -#include - -#include "mbedtls/build_info.h" -#include "mbedtls/platform_util.h" - -#if defined(MBEDTLS_MD_LIGHT) - -/* - * - MBEDTLS_MD_CAN_xxx is defined if the md module can perform xxx. - * - MBEDTLS_MD_xxx_VIA_PSA is defined if the md module may perform xxx via PSA - * (see below). - * - MBEDTLS_MD_SOME_PSA is defined if at least one algorithm may be performed - * via PSA (see below). - * - MBEDTLS_MD_SOME_LEGACY is defined if at least one algorithm may be performed - * via a direct legacy call (see below). - * - * The md module performs an algorithm via PSA if there is a PSA hash - * accelerator and the PSA driver subsytem is initialized at the time the - * operation is started, and makes a direct legacy call otherwise. - */ - -/* PSA accelerated implementations */ -#if defined(MBEDTLS_PSA_CRYPTO_C) -#if defined(MBEDTLS_PSA_ACCEL_ALG_MD5) -#define MBEDTLS_MD_CAN_MD5 -#define MBEDTLS_MD_MD5_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(PSA_WANT_ALG_SHA_1) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) -#define MBEDTLS_MD_CAN_SHA1 -#define MBEDTLS_MD_SHA1_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(PSA_WANT_ALG_SHA_224) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) -#define MBEDTLS_MD_CAN_SHA224 -#define MBEDTLS_MD_SHA224_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(PSA_WANT_ALG_SHA_256) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) -#define MBEDTLS_MD_CAN_SHA256 -#define MBEDTLS_MD_SHA256_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(PSA_WANT_ALG_SHA_384) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) -#define MBEDTLS_MD_CAN_SHA384 -#define MBEDTLS_MD_SHA384_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(PSA_WANT_ALG_SHA_512) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) -#define MBEDTLS_MD_CAN_SHA512 -#define MBEDTLS_MD_SHA512_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(MBEDTLS_PSA_ACCEL_ALG_RIPEMD160) -#define MBEDTLS_MD_CAN_RIPEMD160 -#define MBEDTLS_MD_RIPEMD160_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_224) -#define MBEDTLS_MD_CAN_SHA3_224 -#define MBEDTLS_MD_SHA3_224_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_256) -#define MBEDTLS_MD_CAN_SHA3_256 -#define MBEDTLS_MD_SHA3_256_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_384) -#define MBEDTLS_MD_CAN_SHA3_384 -#define MBEDTLS_MD_SHA3_384_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_512) -#define MBEDTLS_MD_CAN_SHA3_512 -#define MBEDTLS_MD_SHA3_512_VIA_PSA -#define MBEDTLS_MD_SOME_PSA -#endif -#endif /* MBEDTLS_PSA_CRYPTO_C */ - -/* Built-in implementations */ -#if defined(MBEDTLS_MD5_C) -#define MBEDTLS_MD_CAN_MD5 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA1_C) -#define MBEDTLS_MD_CAN_SHA1 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA224_C) -#define MBEDTLS_MD_CAN_SHA224 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA256_C) -#define MBEDTLS_MD_CAN_SHA256 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA384_C) -#define MBEDTLS_MD_CAN_SHA384 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA512_C) -#define MBEDTLS_MD_CAN_SHA512 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_SHA3_C) -#define MBEDTLS_MD_CAN_SHA3_224 -#define MBEDTLS_MD_CAN_SHA3_256 -#define MBEDTLS_MD_CAN_SHA3_384 -#define MBEDTLS_MD_CAN_SHA3_512 -#define MBEDTLS_MD_SOME_LEGACY -#endif -#if defined(MBEDTLS_RIPEMD160_C) -#define MBEDTLS_MD_CAN_RIPEMD160 -#define MBEDTLS_MD_SOME_LEGACY -#endif - -#endif /* MBEDTLS_MD_LIGHT */ - -/** The selected feature is not available. */ -#define MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE -0x5080 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_MD_BAD_INPUT_DATA -0x5100 -/** Failed to allocate memory. */ -#define MBEDTLS_ERR_MD_ALLOC_FAILED -0x5180 -/** Opening or reading of file failed. */ -#define MBEDTLS_ERR_MD_FILE_IO_ERROR -0x5200 - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Supported message digests. - * - * \warning MD5 and SHA-1 are considered weak message digests and - * their use constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -/* Note: these are aligned with the definitions of PSA_ALG_ macros for hashes, - * in order to enable an efficient implementation of conversion functions. - * This is tested by md_to_from_psa() in test_suite_md. */ -typedef enum { - MBEDTLS_MD_NONE=0, /**< None. */ - MBEDTLS_MD_MD5=0x03, /**< The MD5 message digest. */ - MBEDTLS_MD_RIPEMD160=0x04, /**< The RIPEMD-160 message digest. */ - MBEDTLS_MD_SHA1=0x05, /**< The SHA-1 message digest. */ - MBEDTLS_MD_SHA224=0x08, /**< The SHA-224 message digest. */ - MBEDTLS_MD_SHA256=0x09, /**< The SHA-256 message digest. */ - MBEDTLS_MD_SHA384=0x0a, /**< The SHA-384 message digest. */ - MBEDTLS_MD_SHA512=0x0b, /**< The SHA-512 message digest. */ - MBEDTLS_MD_SHA3_224=0x10, /**< The SHA3-224 message digest. */ - MBEDTLS_MD_SHA3_256=0x11, /**< The SHA3-256 message digest. */ - MBEDTLS_MD_SHA3_384=0x12, /**< The SHA3-384 message digest. */ - MBEDTLS_MD_SHA3_512=0x13, /**< The SHA3-512 message digest. */ -} mbedtls_md_type_t; - -/* Note: this should always be >= PSA_HASH_MAX_SIZE - * in all builds with both CRYPTO_C and MD_LIGHT. - * - * This is to make things easier for modules such as TLS that may define a - * buffer size using MD_MAX_SIZE in a part of the code that's common to PSA - * and legacy, then assume the buffer's size is PSA_HASH_MAX_SIZE in another - * part of the code based on PSA. - */ -#if defined(MBEDTLS_MD_CAN_SHA512) || defined(MBEDTLS_MD_CAN_SHA3_512) -#define MBEDTLS_MD_MAX_SIZE 64 /* longest known is SHA512 */ -#elif defined(MBEDTLS_MD_CAN_SHA384) || defined(MBEDTLS_MD_CAN_SHA3_384) -#define MBEDTLS_MD_MAX_SIZE 48 /* longest known is SHA384 */ -#elif defined(MBEDTLS_MD_CAN_SHA256) || defined(MBEDTLS_MD_CAN_SHA3_256) -#define MBEDTLS_MD_MAX_SIZE 32 /* longest known is SHA256 */ -#elif defined(MBEDTLS_MD_CAN_SHA224) || defined(MBEDTLS_MD_CAN_SHA3_224) -#define MBEDTLS_MD_MAX_SIZE 28 /* longest known is SHA224 */ -#else -#define MBEDTLS_MD_MAX_SIZE 20 /* longest known is SHA1 or RIPE MD-160 - or smaller (MD5 and earlier) */ -#endif - -#if defined(MBEDTLS_MD_CAN_SHA3_224) -#define MBEDTLS_MD_MAX_BLOCK_SIZE 144 /* the longest known is SHA3-224 */ -#elif defined(MBEDTLS_MD_CAN_SHA3_256) -#define MBEDTLS_MD_MAX_BLOCK_SIZE 136 -#elif defined(MBEDTLS_MD_CAN_SHA512) || defined(MBEDTLS_MD_CAN_SHA384) -#define MBEDTLS_MD_MAX_BLOCK_SIZE 128 -#elif defined(MBEDTLS_MD_CAN_SHA3_384) -#define MBEDTLS_MD_MAX_BLOCK_SIZE 104 -#elif defined(MBEDTLS_MD_CAN_SHA3_512) -#define MBEDTLS_MD_MAX_BLOCK_SIZE 72 -#else -#define MBEDTLS_MD_MAX_BLOCK_SIZE 64 -#endif - -/** - * Opaque struct. - * - * Constructed using either #mbedtls_md_info_from_string or - * #mbedtls_md_info_from_type. - * - * Fields can be accessed with #mbedtls_md_get_size, - * #mbedtls_md_get_type and #mbedtls_md_get_name. - */ -/* Defined internally in library/md_wrap.h. */ -typedef struct mbedtls_md_info_t mbedtls_md_info_t; - -/** - * Used internally to indicate whether a context uses legacy or PSA. - * - * Internal use only. - */ -typedef enum { - MBEDTLS_MD_ENGINE_LEGACY = 0, - MBEDTLS_MD_ENGINE_PSA, -} mbedtls_md_engine_t; - -/** - * The generic message-digest context. - */ -typedef struct mbedtls_md_context_t { - /** Information about the associated message digest. */ - const mbedtls_md_info_t *MBEDTLS_PRIVATE(md_info); - - /** Are hash operations dispatched to PSA or legacy? */ - mbedtls_md_engine_t MBEDTLS_PRIVATE(engine); - - /** The digest-specific context (legacy) or the PSA operation. */ - void *MBEDTLS_PRIVATE(md_ctx); - - /** The HMAC part of the context. */ - void *MBEDTLS_PRIVATE(hmac_ctx); -} mbedtls_md_context_t; - -/** - * \brief This function returns the message-digest information - * associated with the given digest type. - * - * \param md_type The type of digest to search for. - * - * \return The message-digest information associated with \p md_type. - * \return NULL if the associated message-digest information is not found. - */ -const mbedtls_md_info_t *mbedtls_md_info_from_type(mbedtls_md_type_t md_type); - -/** - * \brief This function initializes a message-digest context without - * binding it to a particular message-digest algorithm. - * - * This function should always be called first. It prepares the - * context for mbedtls_md_setup() for binding it to a - * message-digest algorithm. - */ -void mbedtls_md_init(mbedtls_md_context_t *ctx); - -/** - * \brief This function clears the internal structure of \p ctx and - * frees any embedded internal structure, but does not free - * \p ctx itself. - * - * If you have called mbedtls_md_setup() on \p ctx, you must - * call mbedtls_md_free() when you are no longer using the - * context. - * Calling this function if you have previously - * called mbedtls_md_init() and nothing else is optional. - * You must not call this function if you have not called - * mbedtls_md_init(). - */ -void mbedtls_md_free(mbedtls_md_context_t *ctx); - - -/** - * \brief This function selects the message digest algorithm to use, - * and allocates internal structures. - * - * It should be called after mbedtls_md_init() or - * mbedtls_md_free(). Makes it necessary to call - * mbedtls_md_free() later. - * - * \param ctx The context to set up. - * \param md_info The information structure of the message-digest algorithm - * to use. - * \param hmac Defines if HMAC is used. 0: HMAC is not used (saves some memory), - * or non-zero: HMAC is used with this context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - * \return #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_setup(mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac); - -/** - * \brief This function clones the state of a message-digest - * context. - * - * \note You must call mbedtls_md_setup() on \c dst before calling - * this function. - * - * \note The two contexts must have the same type, - * for example, both are SHA-256. - * - * \warning This function clones the message-digest state, not the - * HMAC state. - * - * \param dst The destination context. - * \param src The context to be cloned. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification failure. - * \return #MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE if both contexts are - * not using the same engine. This can be avoided by moving - * the call to psa_crypto_init() before the first call to - * mbedtls_md_setup(). - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_clone(mbedtls_md_context_t *dst, - const mbedtls_md_context_t *src); - -/** - * \brief This function extracts the message-digest size from the - * message-digest information structure. - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * - * \return The size of the message-digest output in Bytes. - */ -unsigned char mbedtls_md_get_size(const mbedtls_md_info_t *md_info); - -/** - * \brief This function gives the message-digest size associated to - * message-digest type. - * - * \param md_type The message-digest type. - * - * \return The size of the message-digest output in Bytes, - * or 0 if the message-digest type is not known. - */ -static inline unsigned char mbedtls_md_get_size_from_type(mbedtls_md_type_t md_type) -{ - return mbedtls_md_get_size(mbedtls_md_info_from_type(md_type)); -} - -/** - * \brief This function extracts the message-digest type from the - * message-digest information structure. - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * - * \return The type of the message digest. - */ -mbedtls_md_type_t mbedtls_md_get_type(const mbedtls_md_info_t *md_info); - -/** - * \brief This function starts a message-digest computation. - * - * You must call this function after setting up the context - * with mbedtls_md_setup(), and before passing data with - * mbedtls_md_update(). - * - * \param ctx The generic message-digest context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_starts(mbedtls_md_context_t *ctx); - -/** - * \brief This function feeds an input buffer into an ongoing - * message-digest computation. - * - * You must call mbedtls_md_starts() before calling this - * function. You may call this function multiple times. - * Afterwards, call mbedtls_md_finish(). - * - * \param ctx The generic message-digest context. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_update(mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen); - -/** - * \brief This function finishes the digest operation, - * and writes the result to the output buffer. - * - * Call this function after a call to mbedtls_md_starts(), - * followed by any number of calls to mbedtls_md_update(). - * Afterwards, you may either clear the context with - * mbedtls_md_free(), or call mbedtls_md_starts() to reuse - * the context for another digest operation with the same - * algorithm. - * - * \param ctx The generic message-digest context. - * \param output The buffer for the generic message-digest checksum result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_finish(mbedtls_md_context_t *ctx, unsigned char *output); - -/** - * \brief This function calculates the message-digest of a buffer, - * with respect to a configurable message-digest algorithm - * in a single call. - * - * The result is calculated as - * Output = message_digest(input buffer). - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * \param input The buffer holding the data. - * \param ilen The length of the input data. - * \param output The generic message-digest checksum result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md(const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen, - unsigned char *output); - -/** - * \brief This function returns the list of digests supported by the - * generic digest module. - * - * \note The list starts with the strongest available hashes. - * - * \return A statically allocated array of digests. Each element - * in the returned list is an integer belonging to the - * message-digest enumeration #mbedtls_md_type_t. - * The last entry is 0. - */ -const mbedtls_md_type_t *mbedtls_md_list(void); - -/** - * \brief This function returns the message-digest information - * associated with the given digest name. - * - * \param md_name The name of the digest to search for. - * - * \return The message-digest information associated with \p md_name. - * \return NULL if the associated message-digest information is not found. - */ -const mbedtls_md_info_t *mbedtls_md_info_from_string(const char *md_name); - -/** - * \brief This function returns the name of the message digest for - * the message-digest information structure given. - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * - * \return The name of the message digest. - */ -const char *mbedtls_md_get_name(const mbedtls_md_info_t *md_info); - -/** - * \brief This function returns the message-digest information - * from the given context. - * - * \param ctx The context from which to extract the information. - * This must be initialized (or \c NULL). - * - * \return The message-digest information associated with \p ctx. - * \return \c NULL if \p ctx is \c NULL. - */ -const mbedtls_md_info_t *mbedtls_md_info_from_ctx( - const mbedtls_md_context_t *ctx); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief This function calculates the message-digest checksum - * result of the contents of the provided file. - * - * The result is calculated as - * Output = message_digest(file contents). - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * \param path The input file name. - * \param output The generic message-digest checksum result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_FILE_IO_ERROR on an I/O error accessing - * the file pointed by \p path. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info was NULL. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_file(const mbedtls_md_info_t *md_info, const char *path, - unsigned char *output); -#endif /* MBEDTLS_FS_IO */ - -/** - * \brief This function sets the HMAC key and prepares to - * authenticate a new message. - * - * Call this function after mbedtls_md_setup(), to use - * the MD context for an HMAC calculation, then call - * mbedtls_md_hmac_update() to provide the input data, and - * mbedtls_md_hmac_finish() to get the HMAC value. - * - * \param ctx The message digest context containing an embedded HMAC - * context. - * \param key The HMAC secret key. - * \param keylen The length of the HMAC key in Bytes. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_hmac_starts(mbedtls_md_context_t *ctx, const unsigned char *key, - size_t keylen); - -/** - * \brief This function feeds an input buffer into an ongoing HMAC - * computation. - * - * Call mbedtls_md_hmac_starts() or mbedtls_md_hmac_reset() - * before calling this function. - * You may call this function multiple times to pass the - * input piecewise. - * Afterwards, call mbedtls_md_hmac_finish(). - * - * \param ctx The message digest context containing an embedded HMAC - * context. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_hmac_update(mbedtls_md_context_t *ctx, const unsigned char *input, - size_t ilen); - -/** - * \brief This function finishes the HMAC operation, and writes - * the result to the output buffer. - * - * Call this function after mbedtls_md_hmac_starts() and - * mbedtls_md_hmac_update() to get the HMAC value. Afterwards - * you may either call mbedtls_md_free() to clear the context, - * or call mbedtls_md_hmac_reset() to reuse the context with - * the same HMAC key. - * - * \param ctx The message digest context containing an embedded HMAC - * context. - * \param output The generic HMAC checksum result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_hmac_finish(mbedtls_md_context_t *ctx, unsigned char *output); - -/** - * \brief This function prepares to authenticate a new message with - * the same key as the previous HMAC operation. - * - * You may call this function after mbedtls_md_hmac_finish(). - * Afterwards call mbedtls_md_hmac_update() to pass the new - * input. - * - * \param ctx The message digest context containing an embedded HMAC - * context. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_hmac_reset(mbedtls_md_context_t *ctx); - -/** - * \brief This function calculates the full generic HMAC - * on the input buffer with the provided key. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The HMAC result is calculated as - * output = generic HMAC(hmac key, input buffer). - * - * \param md_info The information structure of the message-digest algorithm - * to use. - * \param key The HMAC secret key. - * \param keylen The length of the HMAC secret key in Bytes. - * \param input The buffer holding the input data. - * \param ilen The length of the input data. - * \param output The generic HMAC result. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification - * failure. - */ -MBEDTLS_CHECK_RETURN_TYPICAL -int mbedtls_md_hmac(const mbedtls_md_info_t *md_info, const unsigned char *key, size_t keylen, - const unsigned char *input, size_t ilen, - unsigned char *output); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_MD_H */ +/** + * \file md.h + * + * \brief This file contains the generic functions for message-digest + * (hashing) and HMAC. + * + * \author Adriaan de Jong + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_MD_H +#define MBEDTLS_MD_H +#include "mbedtls/private_access.h" + +#include + +#include "mbedtls/build_info.h" +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_MD_LIGHT) + +/* + * - MBEDTLS_MD_CAN_xxx is defined if the md module can perform xxx. + * - MBEDTLS_MD_xxx_VIA_PSA is defined if the md module may perform xxx via PSA + * (see below). + * - MBEDTLS_MD_SOME_PSA is defined if at least one algorithm may be performed + * via PSA (see below). + * - MBEDTLS_MD_SOME_LEGACY is defined if at least one algorithm may be performed + * via a direct legacy call (see below). + * + * The md module performs an algorithm via PSA if there is a PSA hash + * accelerator and the PSA driver subsytem is initialized at the time the + * operation is started, and makes a direct legacy call otherwise. + */ + +/* PSA accelerated implementations */ +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(MBEDTLS_PSA_ACCEL_ALG_MD5) +#define MBEDTLS_MD_CAN_MD5 +#define MBEDTLS_MD_MD5_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_1) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) +#define MBEDTLS_MD_CAN_SHA1 +#define MBEDTLS_MD_SHA1_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_224) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) +#define MBEDTLS_MD_CAN_SHA224 +#define MBEDTLS_MD_SHA224_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_256) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) +#define MBEDTLS_MD_CAN_SHA256 +#define MBEDTLS_MD_SHA256_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_384) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) +#define MBEDTLS_MD_CAN_SHA384 +#define MBEDTLS_MD_SHA384_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(PSA_WANT_ALG_SHA_512) && defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) +#define MBEDTLS_MD_CAN_SHA512 +#define MBEDTLS_MD_SHA512_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(MBEDTLS_PSA_ACCEL_ALG_RIPEMD160) +#define MBEDTLS_MD_CAN_RIPEMD160 +#define MBEDTLS_MD_RIPEMD160_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_224) +#define MBEDTLS_MD_CAN_SHA3_224 +#define MBEDTLS_MD_SHA3_224_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_256) +#define MBEDTLS_MD_CAN_SHA3_256 +#define MBEDTLS_MD_SHA3_256_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_384) +#define MBEDTLS_MD_CAN_SHA3_384 +#define MBEDTLS_MD_SHA3_384_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#if defined(MBEDTLS_PSA_ACCEL_ALG_SHA3_512) +#define MBEDTLS_MD_CAN_SHA3_512 +#define MBEDTLS_MD_SHA3_512_VIA_PSA +#define MBEDTLS_MD_SOME_PSA +#endif +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +/* Built-in implementations */ +#if defined(MBEDTLS_MD5_C) +#define MBEDTLS_MD_CAN_MD5 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA1_C) +#define MBEDTLS_MD_CAN_SHA1 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA224_C) +#define MBEDTLS_MD_CAN_SHA224 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA256_C) +#define MBEDTLS_MD_CAN_SHA256 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA384_C) +#define MBEDTLS_MD_CAN_SHA384 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA512_C) +#define MBEDTLS_MD_CAN_SHA512 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_SHA3_C) +#define MBEDTLS_MD_CAN_SHA3_224 +#define MBEDTLS_MD_CAN_SHA3_256 +#define MBEDTLS_MD_CAN_SHA3_384 +#define MBEDTLS_MD_CAN_SHA3_512 +#define MBEDTLS_MD_SOME_LEGACY +#endif +#if defined(MBEDTLS_RIPEMD160_C) +#define MBEDTLS_MD_CAN_RIPEMD160 +#define MBEDTLS_MD_SOME_LEGACY +#endif + +#endif /* MBEDTLS_MD_LIGHT */ + +/** The selected feature is not available. */ +#define MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE -0x5080 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_MD_BAD_INPUT_DATA -0x5100 +/** Failed to allocate memory. */ +#define MBEDTLS_ERR_MD_ALLOC_FAILED -0x5180 +/** Opening or reading of file failed. */ +#define MBEDTLS_ERR_MD_FILE_IO_ERROR -0x5200 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Supported message digests. + * + * \warning MD5 and SHA-1 are considered weak message digests and + * their use constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +/* Note: these are aligned with the definitions of PSA_ALG_ macros for hashes, + * in order to enable an efficient implementation of conversion functions. + * This is tested by md_to_from_psa() in test_suite_md. */ +typedef enum { + MBEDTLS_MD_NONE=0, /**< None. */ + MBEDTLS_MD_MD5=0x03, /**< The MD5 message digest. */ + MBEDTLS_MD_RIPEMD160=0x04, /**< The RIPEMD-160 message digest. */ + MBEDTLS_MD_SHA1=0x05, /**< The SHA-1 message digest. */ + MBEDTLS_MD_SHA224=0x08, /**< The SHA-224 message digest. */ + MBEDTLS_MD_SHA256=0x09, /**< The SHA-256 message digest. */ + MBEDTLS_MD_SHA384=0x0a, /**< The SHA-384 message digest. */ + MBEDTLS_MD_SHA512=0x0b, /**< The SHA-512 message digest. */ + MBEDTLS_MD_SHA3_224=0x10, /**< The SHA3-224 message digest. */ + MBEDTLS_MD_SHA3_256=0x11, /**< The SHA3-256 message digest. */ + MBEDTLS_MD_SHA3_384=0x12, /**< The SHA3-384 message digest. */ + MBEDTLS_MD_SHA3_512=0x13, /**< The SHA3-512 message digest. */ +} mbedtls_md_type_t; + +/* Note: this should always be >= PSA_HASH_MAX_SIZE + * in all builds with both CRYPTO_C and MD_LIGHT. + * + * This is to make things easier for modules such as TLS that may define a + * buffer size using MD_MAX_SIZE in a part of the code that's common to PSA + * and legacy, then assume the buffer's size is PSA_HASH_MAX_SIZE in another + * part of the code based on PSA. + */ +#if defined(MBEDTLS_MD_CAN_SHA512) || defined(MBEDTLS_MD_CAN_SHA3_512) +#define MBEDTLS_MD_MAX_SIZE 64 /* longest known is SHA512 */ +#elif defined(MBEDTLS_MD_CAN_SHA384) || defined(MBEDTLS_MD_CAN_SHA3_384) +#define MBEDTLS_MD_MAX_SIZE 48 /* longest known is SHA384 */ +#elif defined(MBEDTLS_MD_CAN_SHA256) || defined(MBEDTLS_MD_CAN_SHA3_256) +#define MBEDTLS_MD_MAX_SIZE 32 /* longest known is SHA256 */ +#elif defined(MBEDTLS_MD_CAN_SHA224) || defined(MBEDTLS_MD_CAN_SHA3_224) +#define MBEDTLS_MD_MAX_SIZE 28 /* longest known is SHA224 */ +#else +#define MBEDTLS_MD_MAX_SIZE 20 /* longest known is SHA1 or RIPE MD-160 + or smaller (MD5 and earlier) */ +#endif + +#if defined(MBEDTLS_MD_CAN_SHA3_224) +#define MBEDTLS_MD_MAX_BLOCK_SIZE 144 /* the longest known is SHA3-224 */ +#elif defined(MBEDTLS_MD_CAN_SHA3_256) +#define MBEDTLS_MD_MAX_BLOCK_SIZE 136 +#elif defined(MBEDTLS_MD_CAN_SHA512) || defined(MBEDTLS_MD_CAN_SHA384) +#define MBEDTLS_MD_MAX_BLOCK_SIZE 128 +#elif defined(MBEDTLS_MD_CAN_SHA3_384) +#define MBEDTLS_MD_MAX_BLOCK_SIZE 104 +#elif defined(MBEDTLS_MD_CAN_SHA3_512) +#define MBEDTLS_MD_MAX_BLOCK_SIZE 72 +#else +#define MBEDTLS_MD_MAX_BLOCK_SIZE 64 +#endif + +/** + * Opaque struct. + * + * Constructed using either #mbedtls_md_info_from_string or + * #mbedtls_md_info_from_type. + * + * Fields can be accessed with #mbedtls_md_get_size, + * #mbedtls_md_get_type and #mbedtls_md_get_name. + */ +/* Defined internally in library/md_wrap.h. */ +typedef struct mbedtls_md_info_t mbedtls_md_info_t; + +/** + * Used internally to indicate whether a context uses legacy or PSA. + * + * Internal use only. + */ +typedef enum { + MBEDTLS_MD_ENGINE_LEGACY = 0, + MBEDTLS_MD_ENGINE_PSA, +} mbedtls_md_engine_t; + +/** + * The generic message-digest context. + */ +typedef struct mbedtls_md_context_t { + /** Information about the associated message digest. */ + const mbedtls_md_info_t *MBEDTLS_PRIVATE(md_info); + + /** Are hash operations dispatched to PSA or legacy? */ + mbedtls_md_engine_t MBEDTLS_PRIVATE(engine); + + /** The digest-specific context (legacy) or the PSA operation. */ + void *MBEDTLS_PRIVATE(md_ctx); + + /** The HMAC part of the context. */ + void *MBEDTLS_PRIVATE(hmac_ctx); +} mbedtls_md_context_t; + +/** + * \brief This function returns the message-digest information + * associated with the given digest type. + * + * \param md_type The type of digest to search for. + * + * \return The message-digest information associated with \p md_type. + * \return NULL if the associated message-digest information is not found. + */ +const mbedtls_md_info_t *mbedtls_md_info_from_type(mbedtls_md_type_t md_type); + +/** + * \brief This function initializes a message-digest context without + * binding it to a particular message-digest algorithm. + * + * This function should always be called first. It prepares the + * context for mbedtls_md_setup() for binding it to a + * message-digest algorithm. + */ +void mbedtls_md_init(mbedtls_md_context_t *ctx); + +/** + * \brief This function clears the internal structure of \p ctx and + * frees any embedded internal structure, but does not free + * \p ctx itself. + * + * If you have called mbedtls_md_setup() on \p ctx, you must + * call mbedtls_md_free() when you are no longer using the + * context. + * Calling this function if you have previously + * called mbedtls_md_init() and nothing else is optional. + * You must not call this function if you have not called + * mbedtls_md_init(). + */ +void mbedtls_md_free(mbedtls_md_context_t *ctx); + + +/** + * \brief This function selects the message digest algorithm to use, + * and allocates internal structures. + * + * It should be called after mbedtls_md_init() or + * mbedtls_md_free(). Makes it necessary to call + * mbedtls_md_free() later. + * + * \param ctx The context to set up. + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param hmac Defines if HMAC is used. 0: HMAC is not used (saves some memory), + * or non-zero: HMAC is used with this context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + * \return #MBEDTLS_ERR_MD_ALLOC_FAILED on memory-allocation failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_setup(mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_info, int hmac); + +/** + * \brief This function clones the state of a message-digest + * context. + * + * \note You must call mbedtls_md_setup() on \c dst before calling + * this function. + * + * \note The two contexts must have the same type, + * for example, both are SHA-256. + * + * \warning This function clones the message-digest state, not the + * HMAC state. + * + * \param dst The destination context. + * \param src The context to be cloned. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification failure. + * \return #MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE if both contexts are + * not using the same engine. This can be avoided by moving + * the call to psa_crypto_init() before the first call to + * mbedtls_md_setup(). + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_clone(mbedtls_md_context_t *dst, + const mbedtls_md_context_t *src); + +/** + * \brief This function extracts the message-digest size from the + * message-digest information structure. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The size of the message-digest output in Bytes. + */ +unsigned char mbedtls_md_get_size(const mbedtls_md_info_t *md_info); + +/** + * \brief This function gives the message-digest size associated to + * message-digest type. + * + * \param md_type The message-digest type. + * + * \return The size of the message-digest output in Bytes, + * or 0 if the message-digest type is not known. + */ +static inline unsigned char mbedtls_md_get_size_from_type(mbedtls_md_type_t md_type) +{ + return mbedtls_md_get_size(mbedtls_md_info_from_type(md_type)); +} + +/** + * \brief This function extracts the message-digest type from the + * message-digest information structure. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The type of the message digest. + */ +mbedtls_md_type_t mbedtls_md_get_type(const mbedtls_md_info_t *md_info); + +/** + * \brief This function starts a message-digest computation. + * + * You must call this function after setting up the context + * with mbedtls_md_setup(), and before passing data with + * mbedtls_md_update(). + * + * \param ctx The generic message-digest context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_starts(mbedtls_md_context_t *ctx); + +/** + * \brief This function feeds an input buffer into an ongoing + * message-digest computation. + * + * You must call mbedtls_md_starts() before calling this + * function. You may call this function multiple times. + * Afterwards, call mbedtls_md_finish(). + * + * \param ctx The generic message-digest context. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_update(mbedtls_md_context_t *ctx, const unsigned char *input, size_t ilen); + +/** + * \brief This function finishes the digest operation, + * and writes the result to the output buffer. + * + * Call this function after a call to mbedtls_md_starts(), + * followed by any number of calls to mbedtls_md_update(). + * Afterwards, you may either clear the context with + * mbedtls_md_free(), or call mbedtls_md_starts() to reuse + * the context for another digest operation with the same + * algorithm. + * + * \param ctx The generic message-digest context. + * \param output The buffer for the generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_finish(mbedtls_md_context_t *ctx, unsigned char *output); + +/** + * \brief This function calculates the message-digest of a buffer, + * with respect to a configurable message-digest algorithm + * in a single call. + * + * The result is calculated as + * Output = message_digest(input buffer). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param input The buffer holding the data. + * \param ilen The length of the input data. + * \param output The generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md(const mbedtls_md_info_t *md_info, const unsigned char *input, size_t ilen, + unsigned char *output); + +/** + * \brief This function returns the list of digests supported by the + * generic digest module. + * + * \note The list starts with the strongest available hashes. + * + * \return A statically allocated array of digests. Each element + * in the returned list is an integer belonging to the + * message-digest enumeration #mbedtls_md_type_t. + * The last entry is 0. + */ +const mbedtls_md_type_t *mbedtls_md_list(void); + +/** + * \brief This function returns the message-digest information + * associated with the given digest name. + * + * \param md_name The name of the digest to search for. + * + * \return The message-digest information associated with \p md_name. + * \return NULL if the associated message-digest information is not found. + */ +const mbedtls_md_info_t *mbedtls_md_info_from_string(const char *md_name); + +/** + * \brief This function returns the name of the message digest for + * the message-digest information structure given. + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * + * \return The name of the message digest. + */ +const char *mbedtls_md_get_name(const mbedtls_md_info_t *md_info); + +/** + * \brief This function returns the message-digest information + * from the given context. + * + * \param ctx The context from which to extract the information. + * This must be initialized (or \c NULL). + * + * \return The message-digest information associated with \p ctx. + * \return \c NULL if \p ctx is \c NULL. + */ +const mbedtls_md_info_t *mbedtls_md_info_from_ctx( + const mbedtls_md_context_t *ctx); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief This function calculates the message-digest checksum + * result of the contents of the provided file. + * + * The result is calculated as + * Output = message_digest(file contents). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param path The input file name. + * \param output The generic message-digest checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_FILE_IO_ERROR on an I/O error accessing + * the file pointed by \p path. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA if \p md_info was NULL. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_file(const mbedtls_md_info_t *md_info, const char *path, + unsigned char *output); +#endif /* MBEDTLS_FS_IO */ + +/** + * \brief This function sets the HMAC key and prepares to + * authenticate a new message. + * + * Call this function after mbedtls_md_setup(), to use + * the MD context for an HMAC calculation, then call + * mbedtls_md_hmac_update() to provide the input data, and + * mbedtls_md_hmac_finish() to get the HMAC value. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param key The HMAC secret key. + * \param keylen The length of the HMAC key in Bytes. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_hmac_starts(mbedtls_md_context_t *ctx, const unsigned char *key, + size_t keylen); + +/** + * \brief This function feeds an input buffer into an ongoing HMAC + * computation. + * + * Call mbedtls_md_hmac_starts() or mbedtls_md_hmac_reset() + * before calling this function. + * You may call this function multiple times to pass the + * input piecewise. + * Afterwards, call mbedtls_md_hmac_finish(). + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_hmac_update(mbedtls_md_context_t *ctx, const unsigned char *input, + size_t ilen); + +/** + * \brief This function finishes the HMAC operation, and writes + * the result to the output buffer. + * + * Call this function after mbedtls_md_hmac_starts() and + * mbedtls_md_hmac_update() to get the HMAC value. Afterwards + * you may either call mbedtls_md_free() to clear the context, + * or call mbedtls_md_hmac_reset() to reuse the context with + * the same HMAC key. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * \param output The generic HMAC checksum result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_hmac_finish(mbedtls_md_context_t *ctx, unsigned char *output); + +/** + * \brief This function prepares to authenticate a new message with + * the same key as the previous HMAC operation. + * + * You may call this function after mbedtls_md_hmac_finish(). + * Afterwards call mbedtls_md_hmac_update() to pass the new + * input. + * + * \param ctx The message digest context containing an embedded HMAC + * context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_hmac_reset(mbedtls_md_context_t *ctx); + +/** + * \brief This function calculates the full generic HMAC + * on the input buffer with the provided key. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The HMAC result is calculated as + * output = generic HMAC(hmac key, input buffer). + * + * \param md_info The information structure of the message-digest algorithm + * to use. + * \param key The HMAC secret key. + * \param keylen The length of the HMAC secret key in Bytes. + * \param input The buffer holding the input data. + * \param ilen The length of the input data. + * \param output The generic HMAC result. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MD_BAD_INPUT_DATA on parameter-verification + * failure. + */ +MBEDTLS_CHECK_RETURN_TYPICAL +int mbedtls_md_hmac(const mbedtls_md_info_t *md_info, const unsigned char *key, size_t keylen, + const unsigned char *input, size_t ilen, + unsigned char *output); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_MD_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md5.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md5.h index 8081886..d8d2024 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md5.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/md5.h @@ -1,202 +1,202 @@ -/** - * \file md5.h - * - * \brief MD5 message digest algorithm (hash function) - * - * \warning MD5 is considered a weak message digest and its use constitutes a - * security risk. We recommend considering stronger message - * digests instead. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_MD5_H -#define MBEDTLS_MD5_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_MD5_ALT) -// Regular implementation -// - -/** - * \brief MD5 context structure - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -typedef struct mbedtls_md5_context { - uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< number of bytes processed */ - uint32_t MBEDTLS_PRIVATE(state)[4]; /*!< intermediate digest state */ - unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< data block being processed */ -} -mbedtls_md5_context; - -#else /* MBEDTLS_MD5_ALT */ -#include "md5_alt.h" -#endif /* MBEDTLS_MD5_ALT */ - -/** - * \brief Initialize MD5 context - * - * \param ctx MD5 context to be initialized - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_md5_init(mbedtls_md5_context *ctx); - -/** - * \brief Clear MD5 context - * - * \param ctx MD5 context to be cleared - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_md5_free(mbedtls_md5_context *ctx); - -/** - * \brief Clone (the state of) an MD5 context - * - * \param dst The destination context - * \param src The context to be cloned - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -void mbedtls_md5_clone(mbedtls_md5_context *dst, - const mbedtls_md5_context *src); - -/** - * \brief MD5 context setup - * - * \param ctx context to be initialized - * - * \return 0 if successful - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_md5_starts(mbedtls_md5_context *ctx); - -/** - * \brief MD5 process buffer - * - * \param ctx MD5 context - * \param input buffer holding the data - * \param ilen length of the input data - * - * \return 0 if successful - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_md5_update(mbedtls_md5_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief MD5 final digest - * - * \param ctx MD5 context - * \param output MD5 checksum result - * - * \return 0 if successful - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_md5_finish(mbedtls_md5_context *ctx, - unsigned char output[16]); - -/** - * \brief MD5 process data block (internal use only) - * - * \param ctx MD5 context - * \param data buffer holding one block of data - * - * \return 0 if successful - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, - const unsigned char data[64]); - -/** - * \brief Output = MD5( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output MD5 checksum result - * - * \return 0 if successful - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_md5(const unsigned char *input, - size_t ilen, - unsigned char output[16]); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - * - * \warning MD5 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -int mbedtls_md5_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_md5.h */ +/** + * \file md5.h + * + * \brief MD5 message digest algorithm (hash function) + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. We recommend considering stronger message + * digests instead. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_MD5_H +#define MBEDTLS_MD5_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_MD5_ALT) +// Regular implementation +// + +/** + * \brief MD5 context structure + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +typedef struct mbedtls_md5_context { + uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< number of bytes processed */ + uint32_t MBEDTLS_PRIVATE(state)[4]; /*!< intermediate digest state */ + unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< data block being processed */ +} +mbedtls_md5_context; + +#else /* MBEDTLS_MD5_ALT */ +#include "md5_alt.h" +#endif /* MBEDTLS_MD5_ALT */ + +/** + * \brief Initialize MD5 context + * + * \param ctx MD5 context to be initialized + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_init(mbedtls_md5_context *ctx); + +/** + * \brief Clear MD5 context + * + * \param ctx MD5 context to be cleared + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_free(mbedtls_md5_context *ctx); + +/** + * \brief Clone (the state of) an MD5 context + * + * \param dst The destination context + * \param src The context to be cloned + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +void mbedtls_md5_clone(mbedtls_md5_context *dst, + const mbedtls_md5_context *src); + +/** + * \brief MD5 context setup + * + * \param ctx context to be initialized + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_starts(mbedtls_md5_context *ctx); + +/** + * \brief MD5 process buffer + * + * \param ctx MD5 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_update(mbedtls_md5_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief MD5 final digest + * + * \param ctx MD5 context + * \param output MD5 checksum result + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_finish(mbedtls_md5_context *ctx, + unsigned char output[16]); + +/** + * \brief MD5 process data block (internal use only) + * + * \param ctx MD5 context + * \param data buffer holding one block of data + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_internal_md5_process(mbedtls_md5_context *ctx, + const unsigned char data[64]); + +/** + * \brief Output = MD5( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output MD5 checksum result + * + * \return 0 if successful + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5(const unsigned char *input, + size_t ilen, + unsigned char output[16]); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + * + * \warning MD5 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +int mbedtls_md5_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_md5.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/memory_buffer_alloc.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/memory_buffer_alloc.h index 9694d24..6016002 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/memory_buffer_alloc.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/memory_buffer_alloc.h @@ -1,154 +1,154 @@ -/** - * \file memory_buffer_alloc.h - * - * \brief Buffer-based memory allocator - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H -#define MBEDTLS_MEMORY_BUFFER_ALLOC_H - -#include "mbedtls/build_info.h" - -#include - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -#if !defined(MBEDTLS_MEMORY_ALIGN_MULTIPLE) -#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ -#endif - -/** \} name SECTION: Module settings */ - -#define MBEDTLS_MEMORY_VERIFY_NONE 0 -#define MBEDTLS_MEMORY_VERIFY_ALLOC (1 << 0) -#define MBEDTLS_MEMORY_VERIFY_FREE (1 << 1) -#define MBEDTLS_MEMORY_VERIFY_ALWAYS (MBEDTLS_MEMORY_VERIFY_ALLOC | \ - MBEDTLS_MEMORY_VERIFY_FREE) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Initialize use of stack-based memory allocator. - * The stack-based allocator does memory management inside the - * presented buffer and does not call calloc() and free(). - * It sets the global mbedtls_calloc() and mbedtls_free() pointers - * to its own functions. - * (Provided mbedtls_calloc() and mbedtls_free() are thread-safe if - * MBEDTLS_THREADING_C is defined) - * - * \note This code is not optimized and provides a straight-forward - * implementation of a stack-based memory allocator. - * - * \param buf buffer to use as heap - * \param len size of the buffer - */ -void mbedtls_memory_buffer_alloc_init(unsigned char *buf, size_t len); - -/** - * \brief Free the mutex for thread-safety and clear remaining memory - */ -void mbedtls_memory_buffer_alloc_free(void); - -/** - * \brief Determine when the allocator should automatically verify the state - * of the entire chain of headers / meta-data. - * (Default: MBEDTLS_MEMORY_VERIFY_NONE) - * - * \param verify One of MBEDTLS_MEMORY_VERIFY_NONE, MBEDTLS_MEMORY_VERIFY_ALLOC, - * MBEDTLS_MEMORY_VERIFY_FREE or MBEDTLS_MEMORY_VERIFY_ALWAYS - */ -void mbedtls_memory_buffer_set_verify(int verify); - -#if defined(MBEDTLS_MEMORY_DEBUG) -/** - * \brief Print out the status of the allocated memory (primarily for use - * after a program should have de-allocated all memory) - * Prints out a list of 'still allocated' blocks and their stack - * trace if MBEDTLS_MEMORY_BACKTRACE is defined. - */ -void mbedtls_memory_buffer_alloc_status(void); - -/** - * \brief Get the number of alloc/free so far. - * - * \param alloc_count Number of allocations. - * \param free_count Number of frees. - */ -void mbedtls_memory_buffer_alloc_count_get(size_t *alloc_count, size_t *free_count); - -/** - * \brief Get the peak heap usage so far - * - * \param max_used Peak number of bytes in use or committed. This - * includes bytes in allocated blocks too small to split - * into smaller blocks but larger than the requested size. - * \param max_blocks Peak number of blocks in use, including free and used - */ -void mbedtls_memory_buffer_alloc_max_get(size_t *max_used, size_t *max_blocks); - -/** - * \brief Reset peak statistics - */ -void mbedtls_memory_buffer_alloc_max_reset(void); - -/** - * \brief Get the current heap usage - * - * \param cur_used Current number of bytes in use or committed. This - * includes bytes in allocated blocks too small to split - * into smaller blocks but larger than the requested size. - * \param cur_blocks Current number of blocks in use, including free and used - */ -void mbedtls_memory_buffer_alloc_cur_get(size_t *cur_used, size_t *cur_blocks); -#endif /* MBEDTLS_MEMORY_DEBUG */ - -/** - * \brief Verifies that all headers in the memory buffer are correct - * and contain sane values. Helps debug buffer-overflow errors. - * - * Prints out first failure if MBEDTLS_MEMORY_DEBUG is defined. - * Prints out full header information if MBEDTLS_MEMORY_DEBUG - * is defined. (Includes stack trace information for each block if - * MBEDTLS_MEMORY_BACKTRACE is defined as well). - * - * \return 0 if verified, 1 otherwise - */ -int mbedtls_memory_buffer_alloc_verify(void); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if a test failed - */ -int mbedtls_memory_buffer_alloc_self_test(int verbose); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* memory_buffer_alloc.h */ +/** + * \file memory_buffer_alloc.h + * + * \brief Buffer-based memory allocator + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_MEMORY_BUFFER_ALLOC_H +#define MBEDTLS_MEMORY_BUFFER_ALLOC_H + +#include "mbedtls/build_info.h" + +#include + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_MEMORY_ALIGN_MULTIPLE) +#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ +#endif + +/** \} name SECTION: Module settings */ + +#define MBEDTLS_MEMORY_VERIFY_NONE 0 +#define MBEDTLS_MEMORY_VERIFY_ALLOC (1 << 0) +#define MBEDTLS_MEMORY_VERIFY_FREE (1 << 1) +#define MBEDTLS_MEMORY_VERIFY_ALWAYS (MBEDTLS_MEMORY_VERIFY_ALLOC | \ + MBEDTLS_MEMORY_VERIFY_FREE) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize use of stack-based memory allocator. + * The stack-based allocator does memory management inside the + * presented buffer and does not call calloc() and free(). + * It sets the global mbedtls_calloc() and mbedtls_free() pointers + * to its own functions. + * (Provided mbedtls_calloc() and mbedtls_free() are thread-safe if + * MBEDTLS_THREADING_C is defined) + * + * \note This code is not optimized and provides a straight-forward + * implementation of a stack-based memory allocator. + * + * \param buf buffer to use as heap + * \param len size of the buffer + */ +void mbedtls_memory_buffer_alloc_init(unsigned char *buf, size_t len); + +/** + * \brief Free the mutex for thread-safety and clear remaining memory + */ +void mbedtls_memory_buffer_alloc_free(void); + +/** + * \brief Determine when the allocator should automatically verify the state + * of the entire chain of headers / meta-data. + * (Default: MBEDTLS_MEMORY_VERIFY_NONE) + * + * \param verify One of MBEDTLS_MEMORY_VERIFY_NONE, MBEDTLS_MEMORY_VERIFY_ALLOC, + * MBEDTLS_MEMORY_VERIFY_FREE or MBEDTLS_MEMORY_VERIFY_ALWAYS + */ +void mbedtls_memory_buffer_set_verify(int verify); + +#if defined(MBEDTLS_MEMORY_DEBUG) +/** + * \brief Print out the status of the allocated memory (primarily for use + * after a program should have de-allocated all memory) + * Prints out a list of 'still allocated' blocks and their stack + * trace if MBEDTLS_MEMORY_BACKTRACE is defined. + */ +void mbedtls_memory_buffer_alloc_status(void); + +/** + * \brief Get the number of alloc/free so far. + * + * \param alloc_count Number of allocations. + * \param free_count Number of frees. + */ +void mbedtls_memory_buffer_alloc_count_get(size_t *alloc_count, size_t *free_count); + +/** + * \brief Get the peak heap usage so far + * + * \param max_used Peak number of bytes in use or committed. This + * includes bytes in allocated blocks too small to split + * into smaller blocks but larger than the requested size. + * \param max_blocks Peak number of blocks in use, including free and used + */ +void mbedtls_memory_buffer_alloc_max_get(size_t *max_used, size_t *max_blocks); + +/** + * \brief Reset peak statistics + */ +void mbedtls_memory_buffer_alloc_max_reset(void); + +/** + * \brief Get the current heap usage + * + * \param cur_used Current number of bytes in use or committed. This + * includes bytes in allocated blocks too small to split + * into smaller blocks but larger than the requested size. + * \param cur_blocks Current number of blocks in use, including free and used + */ +void mbedtls_memory_buffer_alloc_cur_get(size_t *cur_used, size_t *cur_blocks); +#endif /* MBEDTLS_MEMORY_DEBUG */ + +/** + * \brief Verifies that all headers in the memory buffer are correct + * and contain sane values. Helps debug buffer-overflow errors. + * + * Prints out first failure if MBEDTLS_MEMORY_DEBUG is defined. + * Prints out full header information if MBEDTLS_MEMORY_DEBUG + * is defined. (Includes stack trace information for each block if + * MBEDTLS_MEMORY_BACKTRACE is defined as well). + * + * \return 0 if verified, 1 otherwise + */ +int mbedtls_memory_buffer_alloc_verify(void); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if a test failed + */ +int mbedtls_memory_buffer_alloc_self_test(int verbose); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* memory_buffer_alloc.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/net_sockets.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/net_sockets.h index 1096d66..36313f3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/net_sockets.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/net_sockets.h @@ -1,311 +1,311 @@ -/** - * \file net_sockets.h - * - * \brief Network sockets abstraction layer to integrate Mbed TLS into a - * BSD-style sockets API. - * - * The network sockets module provides an example integration of the - * Mbed TLS library into a BSD sockets implementation. The module is - * intended to be an example of how Mbed TLS can be integrated into a - * networking stack, as well as to be Mbed TLS's network integration - * for its supported platforms. - * - * The module is intended only to be used with the Mbed TLS library and - * is not intended to be used by third party application software - * directly. - * - * The supported platforms are as follows: - * * Microsoft Windows and Windows CE - * * POSIX/Unix platforms including Linux, OS X - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_NET_SOCKETS_H -#define MBEDTLS_NET_SOCKETS_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/ssl.h" - -#include -#include - -/** Failed to open a socket. */ -#define MBEDTLS_ERR_NET_SOCKET_FAILED -0x0042 -/** The connection to the given server / port failed. */ -#define MBEDTLS_ERR_NET_CONNECT_FAILED -0x0044 -/** Binding of the socket failed. */ -#define MBEDTLS_ERR_NET_BIND_FAILED -0x0046 -/** Could not listen on the socket. */ -#define MBEDTLS_ERR_NET_LISTEN_FAILED -0x0048 -/** Could not accept the incoming connection. */ -#define MBEDTLS_ERR_NET_ACCEPT_FAILED -0x004A -/** Reading information from the socket failed. */ -#define MBEDTLS_ERR_NET_RECV_FAILED -0x004C -/** Sending information through the socket failed. */ -#define MBEDTLS_ERR_NET_SEND_FAILED -0x004E -/** Connection was reset by peer. */ -#define MBEDTLS_ERR_NET_CONN_RESET -0x0050 -/** Failed to get an IP address for the given hostname. */ -#define MBEDTLS_ERR_NET_UNKNOWN_HOST -0x0052 -/** Buffer is too small to hold the data. */ -#define MBEDTLS_ERR_NET_BUFFER_TOO_SMALL -0x0043 -/** The context is invalid, eg because it was free()ed. */ -#define MBEDTLS_ERR_NET_INVALID_CONTEXT -0x0045 -/** Polling the net context failed. */ -#define MBEDTLS_ERR_NET_POLL_FAILED -0x0047 -/** Input invalid. */ -#define MBEDTLS_ERR_NET_BAD_INPUT_DATA -0x0049 - -#define MBEDTLS_NET_LISTEN_BACKLOG 10 /**< The backlog that listen() should use. */ - -#define MBEDTLS_NET_PROTO_TCP 0 /**< The TCP transport protocol */ -#define MBEDTLS_NET_PROTO_UDP 1 /**< The UDP transport protocol */ - -#define MBEDTLS_NET_POLL_READ 1 /**< Used in \c mbedtls_net_poll to check for pending data */ -#define MBEDTLS_NET_POLL_WRITE 2 /**< Used in \c mbedtls_net_poll to check if write possible */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Wrapper type for sockets. - * - * Currently backed by just a file descriptor, but might be more in the future - * (eg two file descriptors for combined IPv4 + IPv6 support, or additional - * structures for hand-made UDP demultiplexing). - */ -typedef struct mbedtls_net_context { - /** The underlying file descriptor. - * - * This field is only guaranteed to be present on POSIX/Unix-like platforms. - * On other platforms, it may have a different type, have a different - * meaning, or be absent altogether. - */ - int fd; -} -mbedtls_net_context; - -/** - * \brief Initialize a context - * Just makes the context ready to be used or freed safely. - * - * \param ctx Context to initialize - */ -void mbedtls_net_init(mbedtls_net_context *ctx); - -/** - * \brief Initiate a connection with host:port in the given protocol - * - * \param ctx Socket to use - * \param host Host to connect to - * \param port Port to connect to - * \param proto Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP - * - * \return 0 if successful, or one of: - * MBEDTLS_ERR_NET_SOCKET_FAILED, - * MBEDTLS_ERR_NET_UNKNOWN_HOST, - * MBEDTLS_ERR_NET_CONNECT_FAILED - * - * \note Sets the socket in connected mode even with UDP. - */ -int mbedtls_net_connect(mbedtls_net_context *ctx, const char *host, const char *port, int proto); - -/** - * \brief Create a receiving socket on bind_ip:port in the chosen - * protocol. If bind_ip == NULL, all interfaces are bound. - * - * \param ctx Socket to use - * \param bind_ip IP to bind to, can be NULL - * \param port Port number to use - * \param proto Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP - * - * \return 0 if successful, or one of: - * MBEDTLS_ERR_NET_SOCKET_FAILED, - * MBEDTLS_ERR_NET_UNKNOWN_HOST, - * MBEDTLS_ERR_NET_BIND_FAILED, - * MBEDTLS_ERR_NET_LISTEN_FAILED - * - * \note Regardless of the protocol, opens the sockets and binds it. - * In addition, make the socket listening if protocol is TCP. - */ -int mbedtls_net_bind(mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto); - -/** - * \brief Accept a connection from a remote client - * - * \param bind_ctx Relevant socket - * \param client_ctx Will contain the connected client socket - * \param client_ip Will contain the client IP address, can be NULL - * \param buf_size Size of the client_ip buffer - * \param ip_len Will receive the size of the client IP written, - * can be NULL if client_ip is null - * - * \return 0 if successful, or - * MBEDTLS_ERR_NET_SOCKET_FAILED, - * MBEDTLS_ERR_NET_BIND_FAILED, - * MBEDTLS_ERR_NET_ACCEPT_FAILED, or - * MBEDTLS_ERR_NET_BUFFER_TOO_SMALL if buf_size is too small, - * MBEDTLS_ERR_SSL_WANT_READ if bind_fd was set to - * non-blocking and accept() would block. - */ -int mbedtls_net_accept(mbedtls_net_context *bind_ctx, - mbedtls_net_context *client_ctx, - void *client_ip, size_t buf_size, size_t *ip_len); - -/** - * \brief Check and wait for the context to be ready for read/write - * - * \note The current implementation of this function uses - * select() and returns an error if the file descriptor - * is \c FD_SETSIZE or greater. - * - * \param ctx Socket to check - * \param rw Bitflag composed of MBEDTLS_NET_POLL_READ and - * MBEDTLS_NET_POLL_WRITE specifying the events - * to wait for: - * - If MBEDTLS_NET_POLL_READ is set, the function - * will return as soon as the net context is available - * for reading. - * - If MBEDTLS_NET_POLL_WRITE is set, the function - * will return as soon as the net context is available - * for writing. - * \param timeout Maximal amount of time to wait before returning, - * in milliseconds. If \c timeout is zero, the - * function returns immediately. If \c timeout is - * -1u, the function blocks potentially indefinitely. - * - * \return Bitmask composed of MBEDTLS_NET_POLL_READ/WRITE - * on success or timeout, or a negative return code otherwise. - */ -int mbedtls_net_poll(mbedtls_net_context *ctx, uint32_t rw, uint32_t timeout); - -/** - * \brief Set the socket blocking - * - * \param ctx Socket to set - * - * \return 0 if successful, or a non-zero error code - */ -int mbedtls_net_set_block(mbedtls_net_context *ctx); - -/** - * \brief Set the socket non-blocking - * - * \param ctx Socket to set - * - * \return 0 if successful, or a non-zero error code - */ -int mbedtls_net_set_nonblock(mbedtls_net_context *ctx); - -/** - * \brief Portable usleep helper - * - * \param usec Amount of microseconds to sleep - * - * \note Real amount of time slept will not be less than - * select()'s timeout granularity (typically, 10ms). - */ -void mbedtls_net_usleep(unsigned long usec); - -/** - * \brief Read at most 'len' characters. If no error occurs, - * the actual amount read is returned. - * - * \param ctx Socket - * \param buf The buffer to write to - * \param len Maximum length of the buffer - * - * \return the number of bytes received, - * or a non-zero error code; with a non-blocking socket, - * MBEDTLS_ERR_SSL_WANT_READ indicates read() would block. - */ -int mbedtls_net_recv(void *ctx, unsigned char *buf, size_t len); - -/** - * \brief Write at most 'len' characters. If no error occurs, - * the actual amount read is returned. - * - * \param ctx Socket - * \param buf The buffer to read from - * \param len The length of the buffer - * - * \return the number of bytes sent, - * or a non-zero error code; with a non-blocking socket, - * MBEDTLS_ERR_SSL_WANT_WRITE indicates write() would block. - */ -int mbedtls_net_send(void *ctx, const unsigned char *buf, size_t len); - -/** - * \brief Read at most 'len' characters, blocking for at most - * 'timeout' seconds. If no error occurs, the actual amount - * read is returned. - * - * \note The current implementation of this function uses - * select() and returns an error if the file descriptor - * is \c FD_SETSIZE or greater. - * - * \param ctx Socket - * \param buf The buffer to write to - * \param len Maximum length of the buffer - * \param timeout Maximum number of milliseconds to wait for data - * 0 means no timeout (wait forever) - * - * \return The number of bytes received if successful. - * MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out. - * MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal. - * Another negative error code (MBEDTLS_ERR_NET_xxx) - * for other failures. - * - * \note This function will block (until data becomes available or - * timeout is reached) even if the socket is set to - * non-blocking. Handling timeouts with non-blocking reads - * requires a different strategy. - */ -int mbedtls_net_recv_timeout(void *ctx, unsigned char *buf, size_t len, - uint32_t timeout); - -/** - * \brief Closes down the connection and free associated data - * - * \param ctx The context to close - * - * \note This function frees and clears data associated with the - * context but does not free the memory pointed to by \p ctx. - * This memory is the responsibility of the caller. - */ -void mbedtls_net_close(mbedtls_net_context *ctx); - -/** - * \brief Gracefully shutdown the connection and free associated data - * - * \param ctx The context to free - * - * \note This function frees and clears data associated with the - * context but does not free the memory pointed to by \p ctx. - * This memory is the responsibility of the caller. - */ -void mbedtls_net_free(mbedtls_net_context *ctx); - -#ifdef __cplusplus -} -#endif - -#endif /* net_sockets.h */ +/** + * \file net_sockets.h + * + * \brief Network sockets abstraction layer to integrate Mbed TLS into a + * BSD-style sockets API. + * + * The network sockets module provides an example integration of the + * Mbed TLS library into a BSD sockets implementation. The module is + * intended to be an example of how Mbed TLS can be integrated into a + * networking stack, as well as to be Mbed TLS's network integration + * for its supported platforms. + * + * The module is intended only to be used with the Mbed TLS library and + * is not intended to be used by third party application software + * directly. + * + * The supported platforms are as follows: + * * Microsoft Windows and Windows CE + * * POSIX/Unix platforms including Linux, OS X + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_NET_SOCKETS_H +#define MBEDTLS_NET_SOCKETS_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/ssl.h" + +#include +#include + +/** Failed to open a socket. */ +#define MBEDTLS_ERR_NET_SOCKET_FAILED -0x0042 +/** The connection to the given server / port failed. */ +#define MBEDTLS_ERR_NET_CONNECT_FAILED -0x0044 +/** Binding of the socket failed. */ +#define MBEDTLS_ERR_NET_BIND_FAILED -0x0046 +/** Could not listen on the socket. */ +#define MBEDTLS_ERR_NET_LISTEN_FAILED -0x0048 +/** Could not accept the incoming connection. */ +#define MBEDTLS_ERR_NET_ACCEPT_FAILED -0x004A +/** Reading information from the socket failed. */ +#define MBEDTLS_ERR_NET_RECV_FAILED -0x004C +/** Sending information through the socket failed. */ +#define MBEDTLS_ERR_NET_SEND_FAILED -0x004E +/** Connection was reset by peer. */ +#define MBEDTLS_ERR_NET_CONN_RESET -0x0050 +/** Failed to get an IP address for the given hostname. */ +#define MBEDTLS_ERR_NET_UNKNOWN_HOST -0x0052 +/** Buffer is too small to hold the data. */ +#define MBEDTLS_ERR_NET_BUFFER_TOO_SMALL -0x0043 +/** The context is invalid, eg because it was free()ed. */ +#define MBEDTLS_ERR_NET_INVALID_CONTEXT -0x0045 +/** Polling the net context failed. */ +#define MBEDTLS_ERR_NET_POLL_FAILED -0x0047 +/** Input invalid. */ +#define MBEDTLS_ERR_NET_BAD_INPUT_DATA -0x0049 + +#define MBEDTLS_NET_LISTEN_BACKLOG 10 /**< The backlog that listen() should use. */ + +#define MBEDTLS_NET_PROTO_TCP 0 /**< The TCP transport protocol */ +#define MBEDTLS_NET_PROTO_UDP 1 /**< The UDP transport protocol */ + +#define MBEDTLS_NET_POLL_READ 1 /**< Used in \c mbedtls_net_poll to check for pending data */ +#define MBEDTLS_NET_POLL_WRITE 2 /**< Used in \c mbedtls_net_poll to check if write possible */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Wrapper type for sockets. + * + * Currently backed by just a file descriptor, but might be more in the future + * (eg two file descriptors for combined IPv4 + IPv6 support, or additional + * structures for hand-made UDP demultiplexing). + */ +typedef struct mbedtls_net_context { + /** The underlying file descriptor. + * + * This field is only guaranteed to be present on POSIX/Unix-like platforms. + * On other platforms, it may have a different type, have a different + * meaning, or be absent altogether. + */ + int fd; +} +mbedtls_net_context; + +/** + * \brief Initialize a context + * Just makes the context ready to be used or freed safely. + * + * \param ctx Context to initialize + */ +void mbedtls_net_init(mbedtls_net_context *ctx); + +/** + * \brief Initiate a connection with host:port in the given protocol + * + * \param ctx Socket to use + * \param host Host to connect to + * \param port Port to connect to + * \param proto Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP + * + * \return 0 if successful, or one of: + * MBEDTLS_ERR_NET_SOCKET_FAILED, + * MBEDTLS_ERR_NET_UNKNOWN_HOST, + * MBEDTLS_ERR_NET_CONNECT_FAILED + * + * \note Sets the socket in connected mode even with UDP. + */ +int mbedtls_net_connect(mbedtls_net_context *ctx, const char *host, const char *port, int proto); + +/** + * \brief Create a receiving socket on bind_ip:port in the chosen + * protocol. If bind_ip == NULL, all interfaces are bound. + * + * \param ctx Socket to use + * \param bind_ip IP to bind to, can be NULL + * \param port Port number to use + * \param proto Protocol: MBEDTLS_NET_PROTO_TCP or MBEDTLS_NET_PROTO_UDP + * + * \return 0 if successful, or one of: + * MBEDTLS_ERR_NET_SOCKET_FAILED, + * MBEDTLS_ERR_NET_UNKNOWN_HOST, + * MBEDTLS_ERR_NET_BIND_FAILED, + * MBEDTLS_ERR_NET_LISTEN_FAILED + * + * \note Regardless of the protocol, opens the sockets and binds it. + * In addition, make the socket listening if protocol is TCP. + */ +int mbedtls_net_bind(mbedtls_net_context *ctx, const char *bind_ip, const char *port, int proto); + +/** + * \brief Accept a connection from a remote client + * + * \param bind_ctx Relevant socket + * \param client_ctx Will contain the connected client socket + * \param client_ip Will contain the client IP address, can be NULL + * \param buf_size Size of the client_ip buffer + * \param ip_len Will receive the size of the client IP written, + * can be NULL if client_ip is null + * + * \return 0 if successful, or + * MBEDTLS_ERR_NET_SOCKET_FAILED, + * MBEDTLS_ERR_NET_BIND_FAILED, + * MBEDTLS_ERR_NET_ACCEPT_FAILED, or + * MBEDTLS_ERR_NET_BUFFER_TOO_SMALL if buf_size is too small, + * MBEDTLS_ERR_SSL_WANT_READ if bind_fd was set to + * non-blocking and accept() would block. + */ +int mbedtls_net_accept(mbedtls_net_context *bind_ctx, + mbedtls_net_context *client_ctx, + void *client_ip, size_t buf_size, size_t *ip_len); + +/** + * \brief Check and wait for the context to be ready for read/write + * + * \note The current implementation of this function uses + * select() and returns an error if the file descriptor + * is \c FD_SETSIZE or greater. + * + * \param ctx Socket to check + * \param rw Bitflag composed of MBEDTLS_NET_POLL_READ and + * MBEDTLS_NET_POLL_WRITE specifying the events + * to wait for: + * - If MBEDTLS_NET_POLL_READ is set, the function + * will return as soon as the net context is available + * for reading. + * - If MBEDTLS_NET_POLL_WRITE is set, the function + * will return as soon as the net context is available + * for writing. + * \param timeout Maximal amount of time to wait before returning, + * in milliseconds. If \c timeout is zero, the + * function returns immediately. If \c timeout is + * -1u, the function blocks potentially indefinitely. + * + * \return Bitmask composed of MBEDTLS_NET_POLL_READ/WRITE + * on success or timeout, or a negative return code otherwise. + */ +int mbedtls_net_poll(mbedtls_net_context *ctx, uint32_t rw, uint32_t timeout); + +/** + * \brief Set the socket blocking + * + * \param ctx Socket to set + * + * \return 0 if successful, or a non-zero error code + */ +int mbedtls_net_set_block(mbedtls_net_context *ctx); + +/** + * \brief Set the socket non-blocking + * + * \param ctx Socket to set + * + * \return 0 if successful, or a non-zero error code + */ +int mbedtls_net_set_nonblock(mbedtls_net_context *ctx); + +/** + * \brief Portable usleep helper + * + * \param usec Amount of microseconds to sleep + * + * \note Real amount of time slept will not be less than + * select()'s timeout granularity (typically, 10ms). + */ +void mbedtls_net_usleep(unsigned long usec); + +/** + * \brief Read at most 'len' characters. If no error occurs, + * the actual amount read is returned. + * + * \param ctx Socket + * \param buf The buffer to write to + * \param len Maximum length of the buffer + * + * \return the number of bytes received, + * or a non-zero error code; with a non-blocking socket, + * MBEDTLS_ERR_SSL_WANT_READ indicates read() would block. + */ +int mbedtls_net_recv(void *ctx, unsigned char *buf, size_t len); + +/** + * \brief Write at most 'len' characters. If no error occurs, + * the actual amount read is returned. + * + * \param ctx Socket + * \param buf The buffer to read from + * \param len The length of the buffer + * + * \return the number of bytes sent, + * or a non-zero error code; with a non-blocking socket, + * MBEDTLS_ERR_SSL_WANT_WRITE indicates write() would block. + */ +int mbedtls_net_send(void *ctx, const unsigned char *buf, size_t len); + +/** + * \brief Read at most 'len' characters, blocking for at most + * 'timeout' seconds. If no error occurs, the actual amount + * read is returned. + * + * \note The current implementation of this function uses + * select() and returns an error if the file descriptor + * is \c FD_SETSIZE or greater. + * + * \param ctx Socket + * \param buf The buffer to write to + * \param len Maximum length of the buffer + * \param timeout Maximum number of milliseconds to wait for data + * 0 means no timeout (wait forever) + * + * \return The number of bytes received if successful. + * MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out. + * MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal. + * Another negative error code (MBEDTLS_ERR_NET_xxx) + * for other failures. + * + * \note This function will block (until data becomes available or + * timeout is reached) even if the socket is set to + * non-blocking. Handling timeouts with non-blocking reads + * requires a different strategy. + */ +int mbedtls_net_recv_timeout(void *ctx, unsigned char *buf, size_t len, + uint32_t timeout); + +/** + * \brief Closes down the connection and free associated data + * + * \param ctx The context to close + * + * \note This function frees and clears data associated with the + * context but does not free the memory pointed to by \p ctx. + * This memory is the responsibility of the caller. + */ +void mbedtls_net_close(mbedtls_net_context *ctx); + +/** + * \brief Gracefully shutdown the connection and free associated data + * + * \param ctx The context to free + * + * \note This function frees and clears data associated with the + * context but does not free the memory pointed to by \p ctx. + * This memory is the responsibility of the caller. + */ +void mbedtls_net_free(mbedtls_net_context *ctx); + +#ifdef __cplusplus +} +#endif + +#endif /* net_sockets.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/nist_kw.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/nist_kw.h index 0c95c90..f144d4d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/nist_kw.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/nist_kw.h @@ -1,178 +1,178 @@ -/** - * \file nist_kw.h - * - * \brief This file provides an API for key wrapping (KW) and key wrapping with - * padding (KWP) as defined in NIST SP 800-38F. - * https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-38F.pdf - * - * Key wrapping specifies a deterministic authenticated-encryption mode - * of operation, according to NIST SP 800-38F: Recommendation for - * Block Cipher Modes of Operation: Methods for Key Wrapping. Its - * purpose is to protect cryptographic keys. - * - * Its equivalent is RFC 3394 for KW, and RFC 5649 for KWP. - * https://tools.ietf.org/html/rfc3394 - * https://tools.ietf.org/html/rfc5649 - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_NIST_KW_H -#define MBEDTLS_NIST_KW_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/cipher.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - MBEDTLS_KW_MODE_KW = 0, - MBEDTLS_KW_MODE_KWP = 1 -} mbedtls_nist_kw_mode_t; - -#if !defined(MBEDTLS_NIST_KW_ALT) -// Regular implementation -// - -/** - * \brief The key wrapping context-type definition. The key wrapping context is passed - * to the APIs called. - * - * \note The definition of this type may change in future library versions. - * Don't make any assumptions on this context! - */ -typedef struct { - mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ -} mbedtls_nist_kw_context; - -#else /* MBEDTLS_NIST_key wrapping_ALT */ -#include "nist_kw_alt.h" -#endif /* MBEDTLS_NIST_KW_ALT */ - -/** - * \brief This function initializes the specified key wrapping context - * to make references valid and prepare the context - * for mbedtls_nist_kw_setkey() or mbedtls_nist_kw_free(). - * - * \param ctx The key wrapping context to initialize. - * - */ -void mbedtls_nist_kw_init(mbedtls_nist_kw_context *ctx); - -/** - * \brief This function initializes the key wrapping context set in the - * \p ctx parameter and sets the encryption key. - * - * \param ctx The key wrapping context. - * \param cipher The 128-bit block cipher to use. Only AES is supported. - * \param key The Key Encryption Key (KEK). - * \param keybits The KEK size in bits. This must be acceptable by the cipher. - * \param is_wrap Specify whether the operation within the context is wrapping or unwrapping - * - * \return \c 0 on success. - * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for any invalid input. - * \return \c MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE for 128-bit block ciphers - * which are not supported. - * \return cipher-specific error code on failure of the underlying cipher. - */ -int mbedtls_nist_kw_setkey(mbedtls_nist_kw_context *ctx, - mbedtls_cipher_id_t cipher, - const unsigned char *key, - unsigned int keybits, - const int is_wrap); - -/** - * \brief This function releases and clears the specified key wrapping context - * and underlying cipher sub-context. - * - * \param ctx The key wrapping context to clear. - */ -void mbedtls_nist_kw_free(mbedtls_nist_kw_context *ctx); - -/** - * \brief This function encrypts a buffer using key wrapping. - * - * \param ctx The key wrapping context to use for encryption. - * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) - * \param input The buffer holding the input data. - * \param in_len The length of the input data in Bytes. - * The input uses units of 8 Bytes called semiblocks. - *
  • For KW mode: a multiple of 8 bytes between 16 and 2^57-8 inclusive.
    • - *
  • For KWP mode: any length between 1 and 2^32-1 inclusive.
- * \param[out] output The buffer holding the output data. - *
  • For KW mode: Must be at least 8 bytes larger than \p in_len.
    • - *
  • For KWP mode: Must be at least 8 bytes larger rounded up to a multiple of - * 8 bytes for KWP (15 bytes at most).
- * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. - * \param[in] out_size The capacity of the output buffer. - * - * \return \c 0 on success. - * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. - * \return cipher-specific error code on failure of the underlying cipher. - */ -int mbedtls_nist_kw_wrap(mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, - const unsigned char *input, size_t in_len, - unsigned char *output, size_t *out_len, size_t out_size); - -/** - * \brief This function decrypts a buffer using key wrapping. - * - * \param ctx The key wrapping context to use for decryption. - * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) - * \param input The buffer holding the input data. - * \param in_len The length of the input data in Bytes. - * The input uses units of 8 Bytes called semiblocks. - * The input must be a multiple of semiblocks. - *
  • For KW mode: a multiple of 8 bytes between 24 and 2^57 inclusive.
    • - *
  • For KWP mode: a multiple of 8 bytes between 16 and 2^32 inclusive.
- * \param[out] output The buffer holding the output data. - * The output buffer's minimal length is 8 bytes shorter than \p in_len. - * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. - * For KWP mode, the length could be up to 15 bytes shorter than \p in_len, - * depending on how much padding was added to the data. - * \param[in] out_size The capacity of the output buffer. - * - * \return \c 0 on success. - * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. - * \return \c MBEDTLS_ERR_CIPHER_AUTH_FAILED for verification failure of the ciphertext. - * \return cipher-specific error code on failure of the underlying cipher. - */ -int mbedtls_nist_kw_unwrap(mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, - const unsigned char *input, size_t in_len, - unsigned char *output, size_t *out_len, size_t out_size); - - -#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) -/** - * \brief The key wrapping checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_nist_kw_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_NIST_KW_H */ +/** + * \file nist_kw.h + * + * \brief This file provides an API for key wrapping (KW) and key wrapping with + * padding (KWP) as defined in NIST SP 800-38F. + * https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-38F.pdf + * + * Key wrapping specifies a deterministic authenticated-encryption mode + * of operation, according to NIST SP 800-38F: Recommendation for + * Block Cipher Modes of Operation: Methods for Key Wrapping. Its + * purpose is to protect cryptographic keys. + * + * Its equivalent is RFC 3394 for KW, and RFC 5649 for KWP. + * https://tools.ietf.org/html/rfc3394 + * https://tools.ietf.org/html/rfc5649 + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_NIST_KW_H +#define MBEDTLS_NIST_KW_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/cipher.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + MBEDTLS_KW_MODE_KW = 0, + MBEDTLS_KW_MODE_KWP = 1 +} mbedtls_nist_kw_mode_t; + +#if !defined(MBEDTLS_NIST_KW_ALT) +// Regular implementation +// + +/** + * \brief The key wrapping context-type definition. The key wrapping context is passed + * to the APIs called. + * + * \note The definition of this type may change in future library versions. + * Don't make any assumptions on this context! + */ +typedef struct { + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher_ctx); /*!< The cipher context used. */ +} mbedtls_nist_kw_context; + +#else /* MBEDTLS_NIST_key wrapping_ALT */ +#include "nist_kw_alt.h" +#endif /* MBEDTLS_NIST_KW_ALT */ + +/** + * \brief This function initializes the specified key wrapping context + * to make references valid and prepare the context + * for mbedtls_nist_kw_setkey() or mbedtls_nist_kw_free(). + * + * \param ctx The key wrapping context to initialize. + * + */ +void mbedtls_nist_kw_init(mbedtls_nist_kw_context *ctx); + +/** + * \brief This function initializes the key wrapping context set in the + * \p ctx parameter and sets the encryption key. + * + * \param ctx The key wrapping context. + * \param cipher The 128-bit block cipher to use. Only AES is supported. + * \param key The Key Encryption Key (KEK). + * \param keybits The KEK size in bits. This must be acceptable by the cipher. + * \param is_wrap Specify whether the operation within the context is wrapping or unwrapping + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for any invalid input. + * \return \c MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE for 128-bit block ciphers + * which are not supported. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_setkey(mbedtls_nist_kw_context *ctx, + mbedtls_cipher_id_t cipher, + const unsigned char *key, + unsigned int keybits, + const int is_wrap); + +/** + * \brief This function releases and clears the specified key wrapping context + * and underlying cipher sub-context. + * + * \param ctx The key wrapping context to clear. + */ +void mbedtls_nist_kw_free(mbedtls_nist_kw_context *ctx); + +/** + * \brief This function encrypts a buffer using key wrapping. + * + * \param ctx The key wrapping context to use for encryption. + * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) + * \param input The buffer holding the input data. + * \param in_len The length of the input data in Bytes. + * The input uses units of 8 Bytes called semiblocks. + *
  • For KW mode: a multiple of 8 bytes between 16 and 2^57-8 inclusive.
    • + *
  • For KWP mode: any length between 1 and 2^32-1 inclusive.
+ * \param[out] output The buffer holding the output data. + *
  • For KW mode: Must be at least 8 bytes larger than \p in_len.
    • + *
  • For KWP mode: Must be at least 8 bytes larger rounded up to a multiple of + * 8 bytes for KWP (15 bytes at most).
+ * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. + * \param[in] out_size The capacity of the output buffer. + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_wrap(mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, + const unsigned char *input, size_t in_len, + unsigned char *output, size_t *out_len, size_t out_size); + +/** + * \brief This function decrypts a buffer using key wrapping. + * + * \param ctx The key wrapping context to use for decryption. + * \param mode The key wrapping mode to use (MBEDTLS_KW_MODE_KW or MBEDTLS_KW_MODE_KWP) + * \param input The buffer holding the input data. + * \param in_len The length of the input data in Bytes. + * The input uses units of 8 Bytes called semiblocks. + * The input must be a multiple of semiblocks. + *
  • For KW mode: a multiple of 8 bytes between 24 and 2^57 inclusive.
    • + *
  • For KWP mode: a multiple of 8 bytes between 16 and 2^32 inclusive.
+ * \param[out] output The buffer holding the output data. + * The output buffer's minimal length is 8 bytes shorter than \p in_len. + * \param[out] out_len The number of bytes written to the output buffer. \c 0 on failure. + * For KWP mode, the length could be up to 15 bytes shorter than \p in_len, + * depending on how much padding was added to the data. + * \param[in] out_size The capacity of the output buffer. + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA for invalid input length. + * \return \c MBEDTLS_ERR_CIPHER_AUTH_FAILED for verification failure of the ciphertext. + * \return cipher-specific error code on failure of the underlying cipher. + */ +int mbedtls_nist_kw_unwrap(mbedtls_nist_kw_context *ctx, mbedtls_nist_kw_mode_t mode, + const unsigned char *input, size_t in_len, + unsigned char *output, size_t *out_len, size_t out_size); + + +#if defined(MBEDTLS_SELF_TEST) && defined(MBEDTLS_AES_C) +/** + * \brief The key wrapping checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_nist_kw_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST && MBEDTLS_AES_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_NIST_KW_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/oid.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/oid.h index 9545072..c7cdbad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/oid.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/oid.h @@ -1,734 +1,734 @@ -/** - * \file oid.h - * - * \brief Object Identifier (OID) database - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_OID_H -#define MBEDTLS_OID_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/asn1.h" -#include "mbedtls/pk.h" - -#include - -#if defined(MBEDTLS_CIPHER_C) -#include "mbedtls/cipher.h" -#endif - -#include "mbedtls/md.h" - -/** OID is not found. */ -#define MBEDTLS_ERR_OID_NOT_FOUND -0x002E -/** output buffer is too small */ -#define MBEDTLS_ERR_OID_BUF_TOO_SMALL -0x000B - -/* This is for the benefit of X.509, but defined here in order to avoid - * having a "backwards" include of x.509.h here */ -/* - * X.509 extension types (internal, arbitrary values for bitsets) - */ -#define MBEDTLS_OID_X509_EXT_AUTHORITY_KEY_IDENTIFIER (1 << 0) -#define MBEDTLS_OID_X509_EXT_SUBJECT_KEY_IDENTIFIER (1 << 1) -#define MBEDTLS_OID_X509_EXT_KEY_USAGE (1 << 2) -#define MBEDTLS_OID_X509_EXT_CERTIFICATE_POLICIES (1 << 3) -#define MBEDTLS_OID_X509_EXT_POLICY_MAPPINGS (1 << 4) -#define MBEDTLS_OID_X509_EXT_SUBJECT_ALT_NAME (1 << 5) -#define MBEDTLS_OID_X509_EXT_ISSUER_ALT_NAME (1 << 6) -#define MBEDTLS_OID_X509_EXT_SUBJECT_DIRECTORY_ATTRS (1 << 7) -#define MBEDTLS_OID_X509_EXT_BASIC_CONSTRAINTS (1 << 8) -#define MBEDTLS_OID_X509_EXT_NAME_CONSTRAINTS (1 << 9) -#define MBEDTLS_OID_X509_EXT_POLICY_CONSTRAINTS (1 << 10) -#define MBEDTLS_OID_X509_EXT_EXTENDED_KEY_USAGE (1 << 11) -#define MBEDTLS_OID_X509_EXT_CRL_DISTRIBUTION_POINTS (1 << 12) -#define MBEDTLS_OID_X509_EXT_INIHIBIT_ANYPOLICY (1 << 13) -#define MBEDTLS_OID_X509_EXT_FRESHEST_CRL (1 << 14) -#define MBEDTLS_OID_X509_EXT_NS_CERT_TYPE (1 << 16) - -/* - * Maximum number of OID components allowed - */ -#define MBEDTLS_OID_MAX_COMPONENTS 128 - -/* - * Top level OID tuples - */ -#define MBEDTLS_OID_ISO_MEMBER_BODIES "\x2a" /* {iso(1) member-body(2)} */ -#define MBEDTLS_OID_ISO_IDENTIFIED_ORG "\x2b" /* {iso(1) identified-organization(3)} */ -#define MBEDTLS_OID_ISO_CCITT_DS "\x55" /* {joint-iso-ccitt(2) ds(5)} */ -#define MBEDTLS_OID_ISO_ITU_COUNTRY "\x60" /* {joint-iso-itu-t(2) country(16)} */ - -/* - * ISO Member bodies OID parts - */ -#define MBEDTLS_OID_COUNTRY_US "\x86\x48" /* {us(840)} */ -#define MBEDTLS_OID_ORG_RSA_DATA_SECURITY "\x86\xf7\x0d" /* {rsadsi(113549)} */ -#define MBEDTLS_OID_RSA_COMPANY MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ - MBEDTLS_OID_ORG_RSA_DATA_SECURITY /* {iso(1) member-body(2) us(840) rsadsi(113549)} */ -#define MBEDTLS_OID_ORG_ANSI_X9_62 "\xce\x3d" /* ansi-X9-62(10045) */ -#define MBEDTLS_OID_ANSI_X9_62 MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ - MBEDTLS_OID_ORG_ANSI_X9_62 - -/* - * ISO Identified organization OID parts - */ -#define MBEDTLS_OID_ORG_DOD "\x06" /* {dod(6)} */ -#define MBEDTLS_OID_ORG_OIW "\x0e" -#define MBEDTLS_OID_OIW_SECSIG MBEDTLS_OID_ORG_OIW "\x03" -#define MBEDTLS_OID_OIW_SECSIG_ALG MBEDTLS_OID_OIW_SECSIG "\x02" -#define MBEDTLS_OID_OIW_SECSIG_SHA1 MBEDTLS_OID_OIW_SECSIG_ALG "\x1a" -#define MBEDTLS_OID_ORG_THAWTE "\x65" /* thawte(101) */ -#define MBEDTLS_OID_THAWTE MBEDTLS_OID_ISO_IDENTIFIED_ORG \ - MBEDTLS_OID_ORG_THAWTE -#define MBEDTLS_OID_ORG_CERTICOM "\x81\x04" /* certicom(132) */ -#define MBEDTLS_OID_CERTICOM MBEDTLS_OID_ISO_IDENTIFIED_ORG \ - MBEDTLS_OID_ORG_CERTICOM -#define MBEDTLS_OID_ORG_TELETRUST "\x24" /* teletrust(36) */ -#define MBEDTLS_OID_TELETRUST MBEDTLS_OID_ISO_IDENTIFIED_ORG \ - MBEDTLS_OID_ORG_TELETRUST - -/* - * ISO ITU OID parts - */ -#define MBEDTLS_OID_ORGANIZATION "\x01" /* {organization(1)} */ -#define MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ISO_ITU_COUNTRY MBEDTLS_OID_COUNTRY_US \ - MBEDTLS_OID_ORGANIZATION /* {joint-iso-itu-t(2) country(16) us(840) organization(1)} */ - -#define MBEDTLS_OID_ORG_GOV "\x65" /* {gov(101)} */ -#define MBEDTLS_OID_GOV MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_GOV /* {joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101)} */ - -#define MBEDTLS_OID_ORG_NETSCAPE "\x86\xF8\x42" /* {netscape(113730)} */ -#define MBEDTLS_OID_NETSCAPE MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_NETSCAPE /* Netscape OID {joint-iso-itu-t(2) country(16) us(840) organization(1) netscape(113730)} */ - -/* ISO arc for standard certificate and CRL extensions */ -#define MBEDTLS_OID_ID_CE MBEDTLS_OID_ISO_CCITT_DS "\x1D" /**< id-ce OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 29} */ - -#define MBEDTLS_OID_NIST_ALG MBEDTLS_OID_GOV "\x03\x04" /** { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) */ - -/** - * Private Internet Extensions - * { iso(1) identified-organization(3) dod(6) internet(1) - * security(5) mechanisms(5) pkix(7) } - */ -#define MBEDTLS_OID_INTERNET MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_DOD \ - "\x01" -#define MBEDTLS_OID_PKIX MBEDTLS_OID_INTERNET "\x05\x05\x07" - -/* - * Arc for standard naming attributes - */ -#define MBEDTLS_OID_AT MBEDTLS_OID_ISO_CCITT_DS "\x04" /**< id-at OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 4} */ -#define MBEDTLS_OID_AT_CN MBEDTLS_OID_AT "\x03" /**< id-at-commonName AttributeType:= {id-at 3} */ -#define MBEDTLS_OID_AT_SUR_NAME MBEDTLS_OID_AT "\x04" /**< id-at-surName AttributeType:= {id-at 4} */ -#define MBEDTLS_OID_AT_SERIAL_NUMBER MBEDTLS_OID_AT "\x05" /**< id-at-serialNumber AttributeType:= {id-at 5} */ -#define MBEDTLS_OID_AT_COUNTRY MBEDTLS_OID_AT "\x06" /**< id-at-countryName AttributeType:= {id-at 6} */ -#define MBEDTLS_OID_AT_LOCALITY MBEDTLS_OID_AT "\x07" /**< id-at-locality AttributeType:= {id-at 7} */ -#define MBEDTLS_OID_AT_STATE MBEDTLS_OID_AT "\x08" /**< id-at-state AttributeType:= {id-at 8} */ -#define MBEDTLS_OID_AT_ORGANIZATION MBEDTLS_OID_AT "\x0A" /**< id-at-organizationName AttributeType:= {id-at 10} */ -#define MBEDTLS_OID_AT_ORG_UNIT MBEDTLS_OID_AT "\x0B" /**< id-at-organizationalUnitName AttributeType:= {id-at 11} */ -#define MBEDTLS_OID_AT_TITLE MBEDTLS_OID_AT "\x0C" /**< id-at-title AttributeType:= {id-at 12} */ -#define MBEDTLS_OID_AT_POSTAL_ADDRESS MBEDTLS_OID_AT "\x10" /**< id-at-postalAddress AttributeType:= {id-at 16} */ -#define MBEDTLS_OID_AT_POSTAL_CODE MBEDTLS_OID_AT "\x11" /**< id-at-postalCode AttributeType:= {id-at 17} */ -#define MBEDTLS_OID_AT_GIVEN_NAME MBEDTLS_OID_AT "\x2A" /**< id-at-givenName AttributeType:= {id-at 42} */ -#define MBEDTLS_OID_AT_INITIALS MBEDTLS_OID_AT "\x2B" /**< id-at-initials AttributeType:= {id-at 43} */ -#define MBEDTLS_OID_AT_GENERATION_QUALIFIER MBEDTLS_OID_AT "\x2C" /**< id-at-generationQualifier AttributeType:= {id-at 44} */ -#define MBEDTLS_OID_AT_UNIQUE_IDENTIFIER MBEDTLS_OID_AT "\x2D" /**< id-at-uniqueIdentifier AttributeType:= {id-at 45} */ -#define MBEDTLS_OID_AT_DN_QUALIFIER MBEDTLS_OID_AT "\x2E" /**< id-at-dnQualifier AttributeType:= {id-at 46} */ -#define MBEDTLS_OID_AT_PSEUDONYM MBEDTLS_OID_AT "\x41" /**< id-at-pseudonym AttributeType:= {id-at 65} */ - -#define MBEDTLS_OID_UID "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x01" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) uid(1)} */ -#define MBEDTLS_OID_DOMAIN_COMPONENT "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x19" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) domainComponent(25)} */ - -/* - * OIDs for standard certificate extensions - */ -#define MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 35 } */ -#define MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 14 } */ -#define MBEDTLS_OID_KEY_USAGE MBEDTLS_OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::= { id-ce 15 } */ -#define MBEDTLS_OID_CERTIFICATE_POLICIES MBEDTLS_OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::= { id-ce 32 } */ -#define MBEDTLS_OID_POLICY_MAPPINGS MBEDTLS_OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::= { id-ce 33 } */ -#define MBEDTLS_OID_SUBJECT_ALT_NAME MBEDTLS_OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::= { id-ce 17 } */ -#define MBEDTLS_OID_ISSUER_ALT_NAME MBEDTLS_OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::= { id-ce 18 } */ -#define MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::= { id-ce 9 } */ -#define MBEDTLS_OID_BASIC_CONSTRAINTS MBEDTLS_OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::= { id-ce 19 } */ -#define MBEDTLS_OID_NAME_CONSTRAINTS MBEDTLS_OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::= { id-ce 30 } */ -#define MBEDTLS_OID_POLICY_CONSTRAINTS MBEDTLS_OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::= { id-ce 36 } */ -#define MBEDTLS_OID_EXTENDED_KEY_USAGE MBEDTLS_OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */ -#define MBEDTLS_OID_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::= { id-ce 31 } */ -#define MBEDTLS_OID_INIHIBIT_ANYPOLICY MBEDTLS_OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::= { id-ce 54 } */ -#define MBEDTLS_OID_FRESHEST_CRL MBEDTLS_OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::= { id-ce 46 } */ - -/* - * Certificate policies - */ -#define MBEDTLS_OID_ANY_POLICY MBEDTLS_OID_CERTIFICATE_POLICIES "\x00" /**< anyPolicy OBJECT IDENTIFIER ::= { id-ce-certificatePolicies 0 } */ - -/* - * Netscape certificate extensions - */ -#define MBEDTLS_OID_NS_CERT MBEDTLS_OID_NETSCAPE "\x01" -#define MBEDTLS_OID_NS_CERT_TYPE MBEDTLS_OID_NS_CERT "\x01" -#define MBEDTLS_OID_NS_BASE_URL MBEDTLS_OID_NS_CERT "\x02" -#define MBEDTLS_OID_NS_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x03" -#define MBEDTLS_OID_NS_CA_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x04" -#define MBEDTLS_OID_NS_RENEWAL_URL MBEDTLS_OID_NS_CERT "\x07" -#define MBEDTLS_OID_NS_CA_POLICY_URL MBEDTLS_OID_NS_CERT "\x08" -#define MBEDTLS_OID_NS_SSL_SERVER_NAME MBEDTLS_OID_NS_CERT "\x0C" -#define MBEDTLS_OID_NS_COMMENT MBEDTLS_OID_NS_CERT "\x0D" -#define MBEDTLS_OID_NS_DATA_TYPE MBEDTLS_OID_NETSCAPE "\x02" -#define MBEDTLS_OID_NS_CERT_SEQUENCE MBEDTLS_OID_NS_DATA_TYPE "\x05" - -/* - * OIDs for CRL extensions - */ -#define MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD MBEDTLS_OID_ID_CE "\x10" -#define MBEDTLS_OID_CRL_NUMBER MBEDTLS_OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */ - -/* - * X.509 v3 Extended key usage OIDs - */ -#define MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE MBEDTLS_OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */ - -#define MBEDTLS_OID_KP MBEDTLS_OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */ -#define MBEDTLS_OID_SERVER_AUTH MBEDTLS_OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */ -#define MBEDTLS_OID_CLIENT_AUTH MBEDTLS_OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */ -#define MBEDTLS_OID_CODE_SIGNING MBEDTLS_OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */ -#define MBEDTLS_OID_EMAIL_PROTECTION MBEDTLS_OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */ -#define MBEDTLS_OID_TIME_STAMPING MBEDTLS_OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */ -#define MBEDTLS_OID_OCSP_SIGNING MBEDTLS_OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */ - -/** - * Wi-SUN Alliance Field Area Network - * { iso(1) identified-organization(3) dod(6) internet(1) - * private(4) enterprise(1) WiSUN(45605) FieldAreaNetwork(1) } - */ -#define MBEDTLS_OID_WISUN_FAN MBEDTLS_OID_INTERNET "\x04\x01\x82\xe4\x25\x01" - -#define MBEDTLS_OID_ON MBEDTLS_OID_PKIX "\x08" /**< id-on OBJECT IDENTIFIER ::= { id-pkix 8 } */ -#define MBEDTLS_OID_ON_HW_MODULE_NAME MBEDTLS_OID_ON "\x04" /**< id-on-hardwareModuleName OBJECT IDENTIFIER ::= { id-on 4 } */ - -/* - * PKCS definition OIDs - */ - -#define MBEDTLS_OID_PKCS MBEDTLS_OID_RSA_COMPANY "\x01" /**< pkcs OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) 1 } */ -#define MBEDTLS_OID_PKCS1 MBEDTLS_OID_PKCS "\x01" /**< pkcs-1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 1 } */ -#define MBEDTLS_OID_PKCS5 MBEDTLS_OID_PKCS "\x05" /**< pkcs-5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 5 } */ -#define MBEDTLS_OID_PKCS7 MBEDTLS_OID_PKCS "\x07" /**< pkcs-7 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 7 } */ -#define MBEDTLS_OID_PKCS9 MBEDTLS_OID_PKCS "\x09" /**< pkcs-9 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 9 } */ -#define MBEDTLS_OID_PKCS12 MBEDTLS_OID_PKCS "\x0c" /**< pkcs-12 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 12 } */ - -/* - * PKCS#1 OIDs - */ -#define MBEDTLS_OID_PKCS1_RSA MBEDTLS_OID_PKCS1 "\x01" /**< rsaEncryption OBJECT IDENTIFIER ::= { pkcs-1 1 } */ -#define MBEDTLS_OID_PKCS1_MD5 MBEDTLS_OID_PKCS1 "\x04" /**< md5WithRSAEncryption ::= { pkcs-1 4 } */ -#define MBEDTLS_OID_PKCS1_SHA1 MBEDTLS_OID_PKCS1 "\x05" /**< sha1WithRSAEncryption ::= { pkcs-1 5 } */ -#define MBEDTLS_OID_PKCS1_SHA224 MBEDTLS_OID_PKCS1 "\x0e" /**< sha224WithRSAEncryption ::= { pkcs-1 14 } */ -#define MBEDTLS_OID_PKCS1_SHA256 MBEDTLS_OID_PKCS1 "\x0b" /**< sha256WithRSAEncryption ::= { pkcs-1 11 } */ -#define MBEDTLS_OID_PKCS1_SHA384 MBEDTLS_OID_PKCS1 "\x0c" /**< sha384WithRSAEncryption ::= { pkcs-1 12 } */ -#define MBEDTLS_OID_PKCS1_SHA512 MBEDTLS_OID_PKCS1 "\x0d" /**< sha512WithRSAEncryption ::= { pkcs-1 13 } */ - -#define MBEDTLS_OID_RSA_SHA_OBS "\x2B\x0E\x03\x02\x1D" - -#define MBEDTLS_OID_PKCS9_EMAIL MBEDTLS_OID_PKCS9 "\x01" /**< emailAddress AttributeType ::= { pkcs-9 1 } */ - -/* RFC 4055 */ -#define MBEDTLS_OID_RSASSA_PSS MBEDTLS_OID_PKCS1 "\x0a" /**< id-RSASSA-PSS ::= { pkcs-1 10 } */ -#define MBEDTLS_OID_MGF1 MBEDTLS_OID_PKCS1 "\x08" /**< id-mgf1 ::= { pkcs-1 8 } */ - -/* - * Digest algorithms - */ -#define MBEDTLS_OID_DIGEST_ALG_MD5 MBEDTLS_OID_RSA_COMPANY "\x02\x05" /**< id-mbedtls_md5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5 } */ -#define MBEDTLS_OID_DIGEST_ALG_SHA1 MBEDTLS_OID_ISO_IDENTIFIED_ORG \ - MBEDTLS_OID_OIW_SECSIG_SHA1 /**< id-mbedtls_sha1 OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 26 } */ -#define MBEDTLS_OID_DIGEST_ALG_SHA224 MBEDTLS_OID_NIST_ALG "\x02\x04" /**< id-sha224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 4 } */ -#define MBEDTLS_OID_DIGEST_ALG_SHA256 MBEDTLS_OID_NIST_ALG "\x02\x01" /**< id-mbedtls_sha256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 1 } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA384 MBEDTLS_OID_NIST_ALG "\x02\x02" /**< id-sha384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 2 } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA512 MBEDTLS_OID_NIST_ALG "\x02\x03" /**< id-mbedtls_sha512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 3 } */ - -#define MBEDTLS_OID_DIGEST_ALG_RIPEMD160 MBEDTLS_OID_TELETRUST "\x03\x02\x01" /**< id-ripemd160 OBJECT IDENTIFIER :: { iso(1) identified-organization(3) teletrust(36) algorithm(3) hashAlgorithm(2) ripemd160(1) } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA3_224 MBEDTLS_OID_NIST_ALG "\x02\x07" /**< id-sha3-224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-224(7) } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA3_256 MBEDTLS_OID_NIST_ALG "\x02\x08" /**< id-sha3-256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-256(8) } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA3_384 MBEDTLS_OID_NIST_ALG "\x02\x09" /**< id-sha3-384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-384(9) } */ - -#define MBEDTLS_OID_DIGEST_ALG_SHA3_512 MBEDTLS_OID_NIST_ALG "\x02\x0a" /**< id-sha3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-512(10) } */ - - -#define MBEDTLS_OID_HMAC_SHA1 MBEDTLS_OID_RSA_COMPANY "\x02\x07" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 7 } */ - -#define MBEDTLS_OID_HMAC_SHA224 MBEDTLS_OID_RSA_COMPANY "\x02\x08" /**< id-hmacWithSHA224 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 8 } */ - -#define MBEDTLS_OID_HMAC_SHA256 MBEDTLS_OID_RSA_COMPANY "\x02\x09" /**< id-hmacWithSHA256 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 9 } */ - -#define MBEDTLS_OID_HMAC_SHA384 MBEDTLS_OID_RSA_COMPANY "\x02\x0A" /**< id-hmacWithSHA384 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 10 } */ - -#define MBEDTLS_OID_HMAC_SHA512 MBEDTLS_OID_RSA_COMPANY "\x02\x0B" /**< id-hmacWithSHA512 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 11 } */ - -#define MBEDTLS_OID_HMAC_SHA3_224 MBEDTLS_OID_NIST_ALG "\x02\x0d" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-224(13) } */ - -#define MBEDTLS_OID_HMAC_SHA3_256 MBEDTLS_OID_NIST_ALG "\x02\x0e" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-256(14) } */ - -#define MBEDTLS_OID_HMAC_SHA3_384 MBEDTLS_OID_NIST_ALG "\x02\x0f" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-384(15) } */ - -#define MBEDTLS_OID_HMAC_SHA3_512 MBEDTLS_OID_NIST_ALG "\x02\x10" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-512(16) } */ - -#define MBEDTLS_OID_HMAC_RIPEMD160 MBEDTLS_OID_INTERNET "\x05\x05\x08\x01\x04" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= {iso(1) iso-identified-organization(3) dod(6) internet(1) security(5) mechanisms(5) ipsec(8) isakmpOakley(1) hmacRIPEMD160(4)} */ - -/* - * Encryption algorithms - */ -#define MBEDTLS_OID_DES_CBC MBEDTLS_OID_ISO_IDENTIFIED_ORG \ - MBEDTLS_OID_OIW_SECSIG_ALG "\x07" /**< desCBC OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 7 } */ -#define MBEDTLS_OID_DES_EDE3_CBC MBEDTLS_OID_RSA_COMPANY "\x03\x07" /**< des-ede3-cbc OBJECT IDENTIFIER ::= { iso(1) member-body(2) -- us(840) rsadsi(113549) encryptionAlgorithm(3) 7 } */ -#define MBEDTLS_OID_AES MBEDTLS_OID_NIST_ALG "\x01" /** aes OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) 1 } */ - -/* - * Key Wrapping algorithms - */ -/* - * RFC 5649 - */ -#define MBEDTLS_OID_AES128_KW MBEDTLS_OID_AES "\x05" /** id-aes128-wrap OBJECT IDENTIFIER ::= { aes 5 } */ -#define MBEDTLS_OID_AES128_KWP MBEDTLS_OID_AES "\x08" /** id-aes128-wrap-pad OBJECT IDENTIFIER ::= { aes 8 } */ -#define MBEDTLS_OID_AES192_KW MBEDTLS_OID_AES "\x19" /** id-aes192-wrap OBJECT IDENTIFIER ::= { aes 25 } */ -#define MBEDTLS_OID_AES192_KWP MBEDTLS_OID_AES "\x1c" /** id-aes192-wrap-pad OBJECT IDENTIFIER ::= { aes 28 } */ -#define MBEDTLS_OID_AES256_KW MBEDTLS_OID_AES "\x2d" /** id-aes256-wrap OBJECT IDENTIFIER ::= { aes 45 } */ -#define MBEDTLS_OID_AES256_KWP MBEDTLS_OID_AES "\x30" /** id-aes256-wrap-pad OBJECT IDENTIFIER ::= { aes 48 } */ -/* - * PKCS#5 OIDs - */ -#define MBEDTLS_OID_PKCS5_PBKDF2 MBEDTLS_OID_PKCS5 "\x0c" /**< id-PBKDF2 OBJECT IDENTIFIER ::= {pkcs-5 12} */ -#define MBEDTLS_OID_PKCS5_PBES2 MBEDTLS_OID_PKCS5 "\x0d" /**< id-PBES2 OBJECT IDENTIFIER ::= {pkcs-5 13} */ -#define MBEDTLS_OID_PKCS5_PBMAC1 MBEDTLS_OID_PKCS5 "\x0e" /**< id-PBMAC1 OBJECT IDENTIFIER ::= {pkcs-5 14} */ - -/* - * PKCS#5 PBES1 algorithms - */ -#define MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC MBEDTLS_OID_PKCS5 "\x03" /**< pbeWithMD5AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 3} */ -#define MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC MBEDTLS_OID_PKCS5 "\x06" /**< pbeWithMD5AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 6} */ -#define MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC MBEDTLS_OID_PKCS5 "\x0a" /**< pbeWithSHA1AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 10} */ -#define MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC MBEDTLS_OID_PKCS5 "\x0b" /**< pbeWithSHA1AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 11} */ - -/* - * PKCS#7 OIDs - */ -#define MBEDTLS_OID_PKCS7_DATA MBEDTLS_OID_PKCS7 "\x01" /**< Content type is Data OBJECT IDENTIFIER ::= {pkcs-7 1} */ -#define MBEDTLS_OID_PKCS7_SIGNED_DATA MBEDTLS_OID_PKCS7 "\x02" /**< Content type is Signed Data OBJECT IDENTIFIER ::= {pkcs-7 2} */ -#define MBEDTLS_OID_PKCS7_ENVELOPED_DATA MBEDTLS_OID_PKCS7 "\x03" /**< Content type is Enveloped Data OBJECT IDENTIFIER ::= {pkcs-7 3} */ -#define MBEDTLS_OID_PKCS7_SIGNED_AND_ENVELOPED_DATA MBEDTLS_OID_PKCS7 "\x04" /**< Content type is Signed and Enveloped Data OBJECT IDENTIFIER ::= {pkcs-7 4} */ -#define MBEDTLS_OID_PKCS7_DIGESTED_DATA MBEDTLS_OID_PKCS7 "\x05" /**< Content type is Digested Data OBJECT IDENTIFIER ::= {pkcs-7 5} */ -#define MBEDTLS_OID_PKCS7_ENCRYPTED_DATA MBEDTLS_OID_PKCS7 "\x06" /**< Content type is Encrypted Data OBJECT IDENTIFIER ::= {pkcs-7 6} */ - -/* - * PKCS#8 OIDs - */ -#define MBEDTLS_OID_PKCS9_CSR_EXT_REQ MBEDTLS_OID_PKCS9 "\x0e" /**< extensionRequest OBJECT IDENTIFIER ::= {pkcs-9 14} */ - -/* - * PKCS#12 PBE OIDs - */ -#define MBEDTLS_OID_PKCS12_PBE MBEDTLS_OID_PKCS12 "\x01" /**< pkcs-12PbeIds OBJECT IDENTIFIER ::= {pkcs-12 1} */ - -#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x03" /**< pbeWithSHAAnd3-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 3} */ -#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x04" /**< pbeWithSHAAnd2-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 4} */ -#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC MBEDTLS_OID_PKCS12_PBE "\x05" /**< pbeWithSHAAnd128BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 5} */ -#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC MBEDTLS_OID_PKCS12_PBE "\x06" /**< pbeWithSHAAnd40BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 6} */ - -/* - * EC key algorithms from RFC 5480 - */ - -/* id-ecPublicKey OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) keyType(2) 1 } */ -#define MBEDTLS_OID_EC_ALG_UNRESTRICTED MBEDTLS_OID_ANSI_X9_62 "\x02\01" - -/* id-ecDH OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) - * schemes(1) ecdh(12) } */ -#define MBEDTLS_OID_EC_ALG_ECDH MBEDTLS_OID_CERTICOM "\x01\x0c" - -/* - * ECParameters namedCurve identifiers, from RFC 5480, RFC 5639, and SEC2 - */ - -/* secp192r1 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 1 } */ -#define MBEDTLS_OID_EC_GRP_SECP192R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x01" - -/* secp224r1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 33 } */ -#define MBEDTLS_OID_EC_GRP_SECP224R1 MBEDTLS_OID_CERTICOM "\x00\x21" - -/* secp256r1 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 7 } */ -#define MBEDTLS_OID_EC_GRP_SECP256R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x07" - -/* secp384r1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 34 } */ -#define MBEDTLS_OID_EC_GRP_SECP384R1 MBEDTLS_OID_CERTICOM "\x00\x22" - -/* secp521r1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 35 } */ -#define MBEDTLS_OID_EC_GRP_SECP521R1 MBEDTLS_OID_CERTICOM "\x00\x23" - -/* secp192k1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 31 } */ -#define MBEDTLS_OID_EC_GRP_SECP192K1 MBEDTLS_OID_CERTICOM "\x00\x1f" - -/* secp224k1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 32 } */ -#define MBEDTLS_OID_EC_GRP_SECP224K1 MBEDTLS_OID_CERTICOM "\x00\x20" - -/* secp256k1 OBJECT IDENTIFIER ::= { - * iso(1) identified-organization(3) certicom(132) curve(0) 10 } */ -#define MBEDTLS_OID_EC_GRP_SECP256K1 MBEDTLS_OID_CERTICOM "\x00\x0a" - -/* RFC 5639 4.1 - * ecStdCurvesAndGeneration OBJECT IDENTIFIER::= {iso(1) - * identified-organization(3) teletrust(36) algorithm(3) signature- - * algorithm(3) ecSign(2) 8} - * ellipticCurve OBJECT IDENTIFIER ::= {ecStdCurvesAndGeneration 1} - * versionOne OBJECT IDENTIFIER ::= {ellipticCurve 1} */ -#define MBEDTLS_OID_EC_BRAINPOOL_V1 MBEDTLS_OID_TELETRUST "\x03\x03\x02\x08\x01\x01" - -/* brainpoolP256r1 OBJECT IDENTIFIER ::= {versionOne 7} */ -#define MBEDTLS_OID_EC_GRP_BP256R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x07" - -/* brainpoolP384r1 OBJECT IDENTIFIER ::= {versionOne 11} */ -#define MBEDTLS_OID_EC_GRP_BP384R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0B" - -/* brainpoolP512r1 OBJECT IDENTIFIER ::= {versionOne 13} */ -#define MBEDTLS_OID_EC_GRP_BP512R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0D" - -/* - * SEC1 C.1 - * - * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 } - * id-fieldType OBJECT IDENTIFIER ::= { ansi-X9-62 fieldType(1)} - */ -#define MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE MBEDTLS_OID_ANSI_X9_62 "\x01" -#define MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE "\x01" - -/* - * ECDSA signature identifiers, from RFC 5480 - */ -#define MBEDTLS_OID_ANSI_X9_62_SIG MBEDTLS_OID_ANSI_X9_62 "\x04" /* signatures(4) */ -#define MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 MBEDTLS_OID_ANSI_X9_62_SIG "\x03" /* ecdsa-with-SHA2(3) */ - -/* ecdsa-with-SHA1 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) 1 } */ -#define MBEDTLS_OID_ECDSA_SHA1 MBEDTLS_OID_ANSI_X9_62_SIG "\x01" - -/* ecdsa-with-SHA224 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) - * ecdsa-with-SHA2(3) 1 } */ -#define MBEDTLS_OID_ECDSA_SHA224 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x01" - -/* ecdsa-with-SHA256 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) - * ecdsa-with-SHA2(3) 2 } */ -#define MBEDTLS_OID_ECDSA_SHA256 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x02" - -/* ecdsa-with-SHA384 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) - * ecdsa-with-SHA2(3) 3 } */ -#define MBEDTLS_OID_ECDSA_SHA384 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x03" - -/* ecdsa-with-SHA512 OBJECT IDENTIFIER ::= { - * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) - * ecdsa-with-SHA2(3) 4 } */ -#define MBEDTLS_OID_ECDSA_SHA512 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x04" - -/* - * EC key algorithms from RFC 8410 - */ - -#define MBEDTLS_OID_X25519 MBEDTLS_OID_THAWTE "\x6e" /**< id-X25519 OBJECT IDENTIFIER ::= { 1 3 101 110 } */ -#define MBEDTLS_OID_X448 MBEDTLS_OID_THAWTE "\x6f" /**< id-X448 OBJECT IDENTIFIER ::= { 1 3 101 111 } */ -#define MBEDTLS_OID_ED25519 MBEDTLS_OID_THAWTE "\x70" /**< id-Ed25519 OBJECT IDENTIFIER ::= { 1 3 101 112 } */ -#define MBEDTLS_OID_ED448 MBEDTLS_OID_THAWTE "\x71" /**< id-Ed448 OBJECT IDENTIFIER ::= { 1 3 101 113 } */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Base OID descriptor structure - */ -typedef struct mbedtls_oid_descriptor_t { - const char *MBEDTLS_PRIVATE(asn1); /*!< OID ASN.1 representation */ - size_t MBEDTLS_PRIVATE(asn1_len); /*!< length of asn1 */ -#if !defined(MBEDTLS_X509_REMOVE_INFO) - const char *MBEDTLS_PRIVATE(name); /*!< official name (e.g. from RFC) */ - const char *MBEDTLS_PRIVATE(description); /*!< human friendly description */ -#endif -} mbedtls_oid_descriptor_t; - -/** - * \brief Translate an ASN.1 OID into its numeric representation - * (e.g. "\x2A\x86\x48\x86\xF7\x0D" into "1.2.840.113549") - * - * \param buf buffer to put representation in - * \param size size of the buffer - * \param oid OID to translate - * - * \return Length of the string written (excluding final NULL) or - * MBEDTLS_ERR_OID_BUF_TOO_SMALL in case of error - */ -int mbedtls_oid_get_numeric_string(char *buf, size_t size, const mbedtls_asn1_buf *oid); - -/** - * \brief Translate a string containing a dotted-decimal - * representation of an ASN.1 OID into its encoded form - * (e.g. "1.2.840.113549" into "\x2A\x86\x48\x86\xF7\x0D"). - * On success, this function allocates oid->buf from the - * heap. It must be freed by the caller using mbedtls_free(). - * - * \param oid #mbedtls_asn1_buf to populate with the DER-encoded OID - * \param oid_str string representation of the OID to parse - * \param size length of the OID string, not including any null terminator - * - * \return 0 if successful - * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if \p oid_str does not - * represent a valid OID - * \return #MBEDTLS_ERR_ASN1_ALLOC_FAILED if the function fails to - * allocate oid->buf - */ -int mbedtls_oid_from_numeric_string(mbedtls_asn1_buf *oid, const char *oid_str, size_t size); - -/** - * \brief Translate an X.509 extension OID into local values - * - * \param oid OID to use - * \param ext_type place to store the extension type - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_x509_ext_type(const mbedtls_asn1_buf *oid, int *ext_type); - -/** - * \brief Translate an X.509 attribute type OID into the short name - * (e.g. the OID for an X520 Common Name into "CN") - * - * \param oid OID to use - * \param short_name place to store the string pointer - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_attr_short_name(const mbedtls_asn1_buf *oid, const char **short_name); - -/** - * \brief Translate PublicKeyAlgorithm OID into pk_type - * - * \param oid OID to use - * \param pk_alg place to store public key algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_pk_alg(const mbedtls_asn1_buf *oid, mbedtls_pk_type_t *pk_alg); - -/** - * \brief Translate pk_type into PublicKeyAlgorithm OID - * - * \param pk_alg Public key type to look for - * \param oid place to store ASN.1 OID string pointer - * \param olen length of the OID - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_oid_by_pk_alg(mbedtls_pk_type_t pk_alg, - const char **oid, size_t *olen); - -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) -/** - * \brief Translate NamedCurve OID into an EC group identifier - * - * \param oid OID to use - * \param grp_id place to store group id - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_ec_grp(const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id); - -/** - * \brief Translate EC group identifier into NamedCurve OID - * - * \param grp_id EC group identifier - * \param oid place to store ASN.1 OID string pointer - * \param olen length of the OID - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_oid_by_ec_grp(mbedtls_ecp_group_id grp_id, - const char **oid, size_t *olen); - -/** - * \brief Translate AlgorithmIdentifier OID into an EC group identifier, - * for curves that are directly encoded at this level - * - * \param oid OID to use - * \param grp_id place to store group id - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_ec_grp_algid(const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id); - -/** - * \brief Translate EC group identifier into AlgorithmIdentifier OID, - * for curves that are directly encoded at this level - * - * \param grp_id EC group identifier - * \param oid place to store ASN.1 OID string pointer - * \param olen length of the OID - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_oid_by_ec_grp_algid(mbedtls_ecp_group_id grp_id, - const char **oid, size_t *olen); -#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ - -/** - * \brief Translate SignatureAlgorithm OID into md_type and pk_type - * - * \param oid OID to use - * \param md_alg place to store message digest algorithm - * \param pk_alg place to store public key algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_sig_alg(const mbedtls_asn1_buf *oid, - mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg); - -/** - * \brief Translate SignatureAlgorithm OID into description - * - * \param oid OID to use - * \param desc place to store string pointer - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_sig_alg_desc(const mbedtls_asn1_buf *oid, const char **desc); - -/** - * \brief Translate md_type and pk_type into SignatureAlgorithm OID - * - * \param md_alg message digest algorithm - * \param pk_alg public key algorithm - * \param oid place to store ASN.1 OID string pointer - * \param olen length of the OID - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_oid_by_sig_alg(mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, - const char **oid, size_t *olen); - -/** - * \brief Translate hmac algorithm OID into md_type - * - * \param oid OID to use - * \param md_hmac place to store message hmac algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_md_hmac(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_hmac); - -/** - * \brief Translate hash algorithm OID into md_type - * - * \param oid OID to use - * \param md_alg place to store message digest algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_md_alg(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg); - -#if !defined(MBEDTLS_X509_REMOVE_INFO) -/** - * \brief Translate Extended Key Usage OID into description - * - * \param oid OID to use - * \param desc place to store string pointer - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_extended_key_usage(const mbedtls_asn1_buf *oid, const char **desc); -#endif - -/** - * \brief Translate certificate policies OID into description - * - * \param oid OID to use - * \param desc place to store string pointer - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_certificate_policies(const mbedtls_asn1_buf *oid, const char **desc); - -/** - * \brief Translate md_type into hash algorithm OID - * - * \param md_alg message digest algorithm - * \param oid place to store ASN.1 OID string pointer - * \param olen length of the OID - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_oid_by_md(mbedtls_md_type_t md_alg, const char **oid, size_t *olen); - -#if defined(MBEDTLS_CIPHER_C) -/** - * \brief Translate encryption algorithm OID into cipher_type - * - * \param oid OID to use - * \param cipher_alg place to store cipher algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_cipher_alg(const mbedtls_asn1_buf *oid, mbedtls_cipher_type_t *cipher_alg); -#endif /* MBEDTLS_CIPHER_C */ - -#if defined(MBEDTLS_PKCS12_C) -/** - * \brief Translate PKCS#12 PBE algorithm OID into md_type and - * cipher_type - * - * \param oid OID to use - * \param md_alg place to store message digest algorithm - * \param cipher_alg place to store cipher algorithm - * - * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND - */ -int mbedtls_oid_get_pkcs12_pbe_alg(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg, - mbedtls_cipher_type_t *cipher_alg); -#endif /* MBEDTLS_PKCS12_C */ - -#ifdef __cplusplus -} -#endif - -#endif /* oid.h */ +/** + * \file oid.h + * + * \brief Object Identifier (OID) database + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_OID_H +#define MBEDTLS_OID_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/asn1.h" +#include "mbedtls/pk.h" + +#include + +#if defined(MBEDTLS_CIPHER_C) +#include "mbedtls/cipher.h" +#endif + +#include "mbedtls/md.h" + +/** OID is not found. */ +#define MBEDTLS_ERR_OID_NOT_FOUND -0x002E +/** output buffer is too small */ +#define MBEDTLS_ERR_OID_BUF_TOO_SMALL -0x000B + +/* This is for the benefit of X.509, but defined here in order to avoid + * having a "backwards" include of x.509.h here */ +/* + * X.509 extension types (internal, arbitrary values for bitsets) + */ +#define MBEDTLS_OID_X509_EXT_AUTHORITY_KEY_IDENTIFIER (1 << 0) +#define MBEDTLS_OID_X509_EXT_SUBJECT_KEY_IDENTIFIER (1 << 1) +#define MBEDTLS_OID_X509_EXT_KEY_USAGE (1 << 2) +#define MBEDTLS_OID_X509_EXT_CERTIFICATE_POLICIES (1 << 3) +#define MBEDTLS_OID_X509_EXT_POLICY_MAPPINGS (1 << 4) +#define MBEDTLS_OID_X509_EXT_SUBJECT_ALT_NAME (1 << 5) +#define MBEDTLS_OID_X509_EXT_ISSUER_ALT_NAME (1 << 6) +#define MBEDTLS_OID_X509_EXT_SUBJECT_DIRECTORY_ATTRS (1 << 7) +#define MBEDTLS_OID_X509_EXT_BASIC_CONSTRAINTS (1 << 8) +#define MBEDTLS_OID_X509_EXT_NAME_CONSTRAINTS (1 << 9) +#define MBEDTLS_OID_X509_EXT_POLICY_CONSTRAINTS (1 << 10) +#define MBEDTLS_OID_X509_EXT_EXTENDED_KEY_USAGE (1 << 11) +#define MBEDTLS_OID_X509_EXT_CRL_DISTRIBUTION_POINTS (1 << 12) +#define MBEDTLS_OID_X509_EXT_INIHIBIT_ANYPOLICY (1 << 13) +#define MBEDTLS_OID_X509_EXT_FRESHEST_CRL (1 << 14) +#define MBEDTLS_OID_X509_EXT_NS_CERT_TYPE (1 << 16) + +/* + * Maximum number of OID components allowed + */ +#define MBEDTLS_OID_MAX_COMPONENTS 128 + +/* + * Top level OID tuples + */ +#define MBEDTLS_OID_ISO_MEMBER_BODIES "\x2a" /* {iso(1) member-body(2)} */ +#define MBEDTLS_OID_ISO_IDENTIFIED_ORG "\x2b" /* {iso(1) identified-organization(3)} */ +#define MBEDTLS_OID_ISO_CCITT_DS "\x55" /* {joint-iso-ccitt(2) ds(5)} */ +#define MBEDTLS_OID_ISO_ITU_COUNTRY "\x60" /* {joint-iso-itu-t(2) country(16)} */ + +/* + * ISO Member bodies OID parts + */ +#define MBEDTLS_OID_COUNTRY_US "\x86\x48" /* {us(840)} */ +#define MBEDTLS_OID_ORG_RSA_DATA_SECURITY "\x86\xf7\x0d" /* {rsadsi(113549)} */ +#define MBEDTLS_OID_RSA_COMPANY MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ + MBEDTLS_OID_ORG_RSA_DATA_SECURITY /* {iso(1) member-body(2) us(840) rsadsi(113549)} */ +#define MBEDTLS_OID_ORG_ANSI_X9_62 "\xce\x3d" /* ansi-X9-62(10045) */ +#define MBEDTLS_OID_ANSI_X9_62 MBEDTLS_OID_ISO_MEMBER_BODIES MBEDTLS_OID_COUNTRY_US \ + MBEDTLS_OID_ORG_ANSI_X9_62 + +/* + * ISO Identified organization OID parts + */ +#define MBEDTLS_OID_ORG_DOD "\x06" /* {dod(6)} */ +#define MBEDTLS_OID_ORG_OIW "\x0e" +#define MBEDTLS_OID_OIW_SECSIG MBEDTLS_OID_ORG_OIW "\x03" +#define MBEDTLS_OID_OIW_SECSIG_ALG MBEDTLS_OID_OIW_SECSIG "\x02" +#define MBEDTLS_OID_OIW_SECSIG_SHA1 MBEDTLS_OID_OIW_SECSIG_ALG "\x1a" +#define MBEDTLS_OID_ORG_THAWTE "\x65" /* thawte(101) */ +#define MBEDTLS_OID_THAWTE MBEDTLS_OID_ISO_IDENTIFIED_ORG \ + MBEDTLS_OID_ORG_THAWTE +#define MBEDTLS_OID_ORG_CERTICOM "\x81\x04" /* certicom(132) */ +#define MBEDTLS_OID_CERTICOM MBEDTLS_OID_ISO_IDENTIFIED_ORG \ + MBEDTLS_OID_ORG_CERTICOM +#define MBEDTLS_OID_ORG_TELETRUST "\x24" /* teletrust(36) */ +#define MBEDTLS_OID_TELETRUST MBEDTLS_OID_ISO_IDENTIFIED_ORG \ + MBEDTLS_OID_ORG_TELETRUST + +/* + * ISO ITU OID parts + */ +#define MBEDTLS_OID_ORGANIZATION "\x01" /* {organization(1)} */ +#define MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ISO_ITU_COUNTRY MBEDTLS_OID_COUNTRY_US \ + MBEDTLS_OID_ORGANIZATION /* {joint-iso-itu-t(2) country(16) us(840) organization(1)} */ + +#define MBEDTLS_OID_ORG_GOV "\x65" /* {gov(101)} */ +#define MBEDTLS_OID_GOV MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_GOV /* {joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101)} */ + +#define MBEDTLS_OID_ORG_NETSCAPE "\x86\xF8\x42" /* {netscape(113730)} */ +#define MBEDTLS_OID_NETSCAPE MBEDTLS_OID_ISO_ITU_US_ORG MBEDTLS_OID_ORG_NETSCAPE /* Netscape OID {joint-iso-itu-t(2) country(16) us(840) organization(1) netscape(113730)} */ + +/* ISO arc for standard certificate and CRL extensions */ +#define MBEDTLS_OID_ID_CE MBEDTLS_OID_ISO_CCITT_DS "\x1D" /**< id-ce OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 29} */ + +#define MBEDTLS_OID_NIST_ALG MBEDTLS_OID_GOV "\x03\x04" /** { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) */ + +/** + * Private Internet Extensions + * { iso(1) identified-organization(3) dod(6) internet(1) + * security(5) mechanisms(5) pkix(7) } + */ +#define MBEDTLS_OID_INTERNET MBEDTLS_OID_ISO_IDENTIFIED_ORG MBEDTLS_OID_ORG_DOD \ + "\x01" +#define MBEDTLS_OID_PKIX MBEDTLS_OID_INTERNET "\x05\x05\x07" + +/* + * Arc for standard naming attributes + */ +#define MBEDTLS_OID_AT MBEDTLS_OID_ISO_CCITT_DS "\x04" /**< id-at OBJECT IDENTIFIER ::= {joint-iso-ccitt(2) ds(5) 4} */ +#define MBEDTLS_OID_AT_CN MBEDTLS_OID_AT "\x03" /**< id-at-commonName AttributeType:= {id-at 3} */ +#define MBEDTLS_OID_AT_SUR_NAME MBEDTLS_OID_AT "\x04" /**< id-at-surName AttributeType:= {id-at 4} */ +#define MBEDTLS_OID_AT_SERIAL_NUMBER MBEDTLS_OID_AT "\x05" /**< id-at-serialNumber AttributeType:= {id-at 5} */ +#define MBEDTLS_OID_AT_COUNTRY MBEDTLS_OID_AT "\x06" /**< id-at-countryName AttributeType:= {id-at 6} */ +#define MBEDTLS_OID_AT_LOCALITY MBEDTLS_OID_AT "\x07" /**< id-at-locality AttributeType:= {id-at 7} */ +#define MBEDTLS_OID_AT_STATE MBEDTLS_OID_AT "\x08" /**< id-at-state AttributeType:= {id-at 8} */ +#define MBEDTLS_OID_AT_ORGANIZATION MBEDTLS_OID_AT "\x0A" /**< id-at-organizationName AttributeType:= {id-at 10} */ +#define MBEDTLS_OID_AT_ORG_UNIT MBEDTLS_OID_AT "\x0B" /**< id-at-organizationalUnitName AttributeType:= {id-at 11} */ +#define MBEDTLS_OID_AT_TITLE MBEDTLS_OID_AT "\x0C" /**< id-at-title AttributeType:= {id-at 12} */ +#define MBEDTLS_OID_AT_POSTAL_ADDRESS MBEDTLS_OID_AT "\x10" /**< id-at-postalAddress AttributeType:= {id-at 16} */ +#define MBEDTLS_OID_AT_POSTAL_CODE MBEDTLS_OID_AT "\x11" /**< id-at-postalCode AttributeType:= {id-at 17} */ +#define MBEDTLS_OID_AT_GIVEN_NAME MBEDTLS_OID_AT "\x2A" /**< id-at-givenName AttributeType:= {id-at 42} */ +#define MBEDTLS_OID_AT_INITIALS MBEDTLS_OID_AT "\x2B" /**< id-at-initials AttributeType:= {id-at 43} */ +#define MBEDTLS_OID_AT_GENERATION_QUALIFIER MBEDTLS_OID_AT "\x2C" /**< id-at-generationQualifier AttributeType:= {id-at 44} */ +#define MBEDTLS_OID_AT_UNIQUE_IDENTIFIER MBEDTLS_OID_AT "\x2D" /**< id-at-uniqueIdentifier AttributeType:= {id-at 45} */ +#define MBEDTLS_OID_AT_DN_QUALIFIER MBEDTLS_OID_AT "\x2E" /**< id-at-dnQualifier AttributeType:= {id-at 46} */ +#define MBEDTLS_OID_AT_PSEUDONYM MBEDTLS_OID_AT "\x41" /**< id-at-pseudonym AttributeType:= {id-at 65} */ + +#define MBEDTLS_OID_UID "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x01" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) uid(1)} */ +#define MBEDTLS_OID_DOMAIN_COMPONENT "\x09\x92\x26\x89\x93\xF2\x2C\x64\x01\x19" /** id-domainComponent AttributeType:= {itu-t(0) data(9) pss(2342) ucl(19200300) pilot(100) pilotAttributeType(1) domainComponent(25)} */ + +/* + * OIDs for standard certificate extensions + */ +#define MBEDTLS_OID_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x23" /**< id-ce-authorityKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 35 } */ +#define MBEDTLS_OID_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_ID_CE "\x0E" /**< id-ce-subjectKeyIdentifier OBJECT IDENTIFIER ::= { id-ce 14 } */ +#define MBEDTLS_OID_KEY_USAGE MBEDTLS_OID_ID_CE "\x0F" /**< id-ce-keyUsage OBJECT IDENTIFIER ::= { id-ce 15 } */ +#define MBEDTLS_OID_CERTIFICATE_POLICIES MBEDTLS_OID_ID_CE "\x20" /**< id-ce-certificatePolicies OBJECT IDENTIFIER ::= { id-ce 32 } */ +#define MBEDTLS_OID_POLICY_MAPPINGS MBEDTLS_OID_ID_CE "\x21" /**< id-ce-policyMappings OBJECT IDENTIFIER ::= { id-ce 33 } */ +#define MBEDTLS_OID_SUBJECT_ALT_NAME MBEDTLS_OID_ID_CE "\x11" /**< id-ce-subjectAltName OBJECT IDENTIFIER ::= { id-ce 17 } */ +#define MBEDTLS_OID_ISSUER_ALT_NAME MBEDTLS_OID_ID_CE "\x12" /**< id-ce-issuerAltName OBJECT IDENTIFIER ::= { id-ce 18 } */ +#define MBEDTLS_OID_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_ID_CE "\x09" /**< id-ce-subjectDirectoryAttributes OBJECT IDENTIFIER ::= { id-ce 9 } */ +#define MBEDTLS_OID_BASIC_CONSTRAINTS MBEDTLS_OID_ID_CE "\x13" /**< id-ce-basicConstraints OBJECT IDENTIFIER ::= { id-ce 19 } */ +#define MBEDTLS_OID_NAME_CONSTRAINTS MBEDTLS_OID_ID_CE "\x1E" /**< id-ce-nameConstraints OBJECT IDENTIFIER ::= { id-ce 30 } */ +#define MBEDTLS_OID_POLICY_CONSTRAINTS MBEDTLS_OID_ID_CE "\x24" /**< id-ce-policyConstraints OBJECT IDENTIFIER ::= { id-ce 36 } */ +#define MBEDTLS_OID_EXTENDED_KEY_USAGE MBEDTLS_OID_ID_CE "\x25" /**< id-ce-extKeyUsage OBJECT IDENTIFIER ::= { id-ce 37 } */ +#define MBEDTLS_OID_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_ID_CE "\x1F" /**< id-ce-cRLDistributionPoints OBJECT IDENTIFIER ::= { id-ce 31 } */ +#define MBEDTLS_OID_INIHIBIT_ANYPOLICY MBEDTLS_OID_ID_CE "\x36" /**< id-ce-inhibitAnyPolicy OBJECT IDENTIFIER ::= { id-ce 54 } */ +#define MBEDTLS_OID_FRESHEST_CRL MBEDTLS_OID_ID_CE "\x2E" /**< id-ce-freshestCRL OBJECT IDENTIFIER ::= { id-ce 46 } */ + +/* + * Certificate policies + */ +#define MBEDTLS_OID_ANY_POLICY MBEDTLS_OID_CERTIFICATE_POLICIES "\x00" /**< anyPolicy OBJECT IDENTIFIER ::= { id-ce-certificatePolicies 0 } */ + +/* + * Netscape certificate extensions + */ +#define MBEDTLS_OID_NS_CERT MBEDTLS_OID_NETSCAPE "\x01" +#define MBEDTLS_OID_NS_CERT_TYPE MBEDTLS_OID_NS_CERT "\x01" +#define MBEDTLS_OID_NS_BASE_URL MBEDTLS_OID_NS_CERT "\x02" +#define MBEDTLS_OID_NS_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x03" +#define MBEDTLS_OID_NS_CA_REVOCATION_URL MBEDTLS_OID_NS_CERT "\x04" +#define MBEDTLS_OID_NS_RENEWAL_URL MBEDTLS_OID_NS_CERT "\x07" +#define MBEDTLS_OID_NS_CA_POLICY_URL MBEDTLS_OID_NS_CERT "\x08" +#define MBEDTLS_OID_NS_SSL_SERVER_NAME MBEDTLS_OID_NS_CERT "\x0C" +#define MBEDTLS_OID_NS_COMMENT MBEDTLS_OID_NS_CERT "\x0D" +#define MBEDTLS_OID_NS_DATA_TYPE MBEDTLS_OID_NETSCAPE "\x02" +#define MBEDTLS_OID_NS_CERT_SEQUENCE MBEDTLS_OID_NS_DATA_TYPE "\x05" + +/* + * OIDs for CRL extensions + */ +#define MBEDTLS_OID_PRIVATE_KEY_USAGE_PERIOD MBEDTLS_OID_ID_CE "\x10" +#define MBEDTLS_OID_CRL_NUMBER MBEDTLS_OID_ID_CE "\x14" /**< id-ce-cRLNumber OBJECT IDENTIFIER ::= { id-ce 20 } */ + +/* + * X.509 v3 Extended key usage OIDs + */ +#define MBEDTLS_OID_ANY_EXTENDED_KEY_USAGE MBEDTLS_OID_EXTENDED_KEY_USAGE "\x00" /**< anyExtendedKeyUsage OBJECT IDENTIFIER ::= { id-ce-extKeyUsage 0 } */ + +#define MBEDTLS_OID_KP MBEDTLS_OID_PKIX "\x03" /**< id-kp OBJECT IDENTIFIER ::= { id-pkix 3 } */ +#define MBEDTLS_OID_SERVER_AUTH MBEDTLS_OID_KP "\x01" /**< id-kp-serverAuth OBJECT IDENTIFIER ::= { id-kp 1 } */ +#define MBEDTLS_OID_CLIENT_AUTH MBEDTLS_OID_KP "\x02" /**< id-kp-clientAuth OBJECT IDENTIFIER ::= { id-kp 2 } */ +#define MBEDTLS_OID_CODE_SIGNING MBEDTLS_OID_KP "\x03" /**< id-kp-codeSigning OBJECT IDENTIFIER ::= { id-kp 3 } */ +#define MBEDTLS_OID_EMAIL_PROTECTION MBEDTLS_OID_KP "\x04" /**< id-kp-emailProtection OBJECT IDENTIFIER ::= { id-kp 4 } */ +#define MBEDTLS_OID_TIME_STAMPING MBEDTLS_OID_KP "\x08" /**< id-kp-timeStamping OBJECT IDENTIFIER ::= { id-kp 8 } */ +#define MBEDTLS_OID_OCSP_SIGNING MBEDTLS_OID_KP "\x09" /**< id-kp-OCSPSigning OBJECT IDENTIFIER ::= { id-kp 9 } */ + +/** + * Wi-SUN Alliance Field Area Network + * { iso(1) identified-organization(3) dod(6) internet(1) + * private(4) enterprise(1) WiSUN(45605) FieldAreaNetwork(1) } + */ +#define MBEDTLS_OID_WISUN_FAN MBEDTLS_OID_INTERNET "\x04\x01\x82\xe4\x25\x01" + +#define MBEDTLS_OID_ON MBEDTLS_OID_PKIX "\x08" /**< id-on OBJECT IDENTIFIER ::= { id-pkix 8 } */ +#define MBEDTLS_OID_ON_HW_MODULE_NAME MBEDTLS_OID_ON "\x04" /**< id-on-hardwareModuleName OBJECT IDENTIFIER ::= { id-on 4 } */ + +/* + * PKCS definition OIDs + */ + +#define MBEDTLS_OID_PKCS MBEDTLS_OID_RSA_COMPANY "\x01" /**< pkcs OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) 1 } */ +#define MBEDTLS_OID_PKCS1 MBEDTLS_OID_PKCS "\x01" /**< pkcs-1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 1 } */ +#define MBEDTLS_OID_PKCS5 MBEDTLS_OID_PKCS "\x05" /**< pkcs-5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 5 } */ +#define MBEDTLS_OID_PKCS7 MBEDTLS_OID_PKCS "\x07" /**< pkcs-7 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 7 } */ +#define MBEDTLS_OID_PKCS9 MBEDTLS_OID_PKCS "\x09" /**< pkcs-9 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 9 } */ +#define MBEDTLS_OID_PKCS12 MBEDTLS_OID_PKCS "\x0c" /**< pkcs-12 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) pkcs(1) 12 } */ + +/* + * PKCS#1 OIDs + */ +#define MBEDTLS_OID_PKCS1_RSA MBEDTLS_OID_PKCS1 "\x01" /**< rsaEncryption OBJECT IDENTIFIER ::= { pkcs-1 1 } */ +#define MBEDTLS_OID_PKCS1_MD5 MBEDTLS_OID_PKCS1 "\x04" /**< md5WithRSAEncryption ::= { pkcs-1 4 } */ +#define MBEDTLS_OID_PKCS1_SHA1 MBEDTLS_OID_PKCS1 "\x05" /**< sha1WithRSAEncryption ::= { pkcs-1 5 } */ +#define MBEDTLS_OID_PKCS1_SHA224 MBEDTLS_OID_PKCS1 "\x0e" /**< sha224WithRSAEncryption ::= { pkcs-1 14 } */ +#define MBEDTLS_OID_PKCS1_SHA256 MBEDTLS_OID_PKCS1 "\x0b" /**< sha256WithRSAEncryption ::= { pkcs-1 11 } */ +#define MBEDTLS_OID_PKCS1_SHA384 MBEDTLS_OID_PKCS1 "\x0c" /**< sha384WithRSAEncryption ::= { pkcs-1 12 } */ +#define MBEDTLS_OID_PKCS1_SHA512 MBEDTLS_OID_PKCS1 "\x0d" /**< sha512WithRSAEncryption ::= { pkcs-1 13 } */ + +#define MBEDTLS_OID_RSA_SHA_OBS "\x2B\x0E\x03\x02\x1D" + +#define MBEDTLS_OID_PKCS9_EMAIL MBEDTLS_OID_PKCS9 "\x01" /**< emailAddress AttributeType ::= { pkcs-9 1 } */ + +/* RFC 4055 */ +#define MBEDTLS_OID_RSASSA_PSS MBEDTLS_OID_PKCS1 "\x0a" /**< id-RSASSA-PSS ::= { pkcs-1 10 } */ +#define MBEDTLS_OID_MGF1 MBEDTLS_OID_PKCS1 "\x08" /**< id-mgf1 ::= { pkcs-1 8 } */ + +/* + * Digest algorithms + */ +#define MBEDTLS_OID_DIGEST_ALG_MD5 MBEDTLS_OID_RSA_COMPANY "\x02\x05" /**< id-mbedtls_md5 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 5 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA1 MBEDTLS_OID_ISO_IDENTIFIED_ORG \ + MBEDTLS_OID_OIW_SECSIG_SHA1 /**< id-mbedtls_sha1 OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 26 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA224 MBEDTLS_OID_NIST_ALG "\x02\x04" /**< id-sha224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 4 } */ +#define MBEDTLS_OID_DIGEST_ALG_SHA256 MBEDTLS_OID_NIST_ALG "\x02\x01" /**< id-mbedtls_sha256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 1 } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA384 MBEDTLS_OID_NIST_ALG "\x02\x02" /**< id-sha384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 2 } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA512 MBEDTLS_OID_NIST_ALG "\x02\x03" /**< id-mbedtls_sha512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistalgorithm(4) hashalgs(2) 3 } */ + +#define MBEDTLS_OID_DIGEST_ALG_RIPEMD160 MBEDTLS_OID_TELETRUST "\x03\x02\x01" /**< id-ripemd160 OBJECT IDENTIFIER :: { iso(1) identified-organization(3) teletrust(36) algorithm(3) hashAlgorithm(2) ripemd160(1) } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA3_224 MBEDTLS_OID_NIST_ALG "\x02\x07" /**< id-sha3-224 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-224(7) } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA3_256 MBEDTLS_OID_NIST_ALG "\x02\x08" /**< id-sha3-256 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-256(8) } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA3_384 MBEDTLS_OID_NIST_ALG "\x02\x09" /**< id-sha3-384 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-384(9) } */ + +#define MBEDTLS_OID_DIGEST_ALG_SHA3_512 MBEDTLS_OID_NIST_ALG "\x02\x0a" /**< id-sha3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) sha3-512(10) } */ + + +#define MBEDTLS_OID_HMAC_SHA1 MBEDTLS_OID_RSA_COMPANY "\x02\x07" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 7 } */ + +#define MBEDTLS_OID_HMAC_SHA224 MBEDTLS_OID_RSA_COMPANY "\x02\x08" /**< id-hmacWithSHA224 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 8 } */ + +#define MBEDTLS_OID_HMAC_SHA256 MBEDTLS_OID_RSA_COMPANY "\x02\x09" /**< id-hmacWithSHA256 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 9 } */ + +#define MBEDTLS_OID_HMAC_SHA384 MBEDTLS_OID_RSA_COMPANY "\x02\x0A" /**< id-hmacWithSHA384 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 10 } */ + +#define MBEDTLS_OID_HMAC_SHA512 MBEDTLS_OID_RSA_COMPANY "\x02\x0B" /**< id-hmacWithSHA512 OBJECT IDENTIFIER ::= { iso(1) member-body(2) us(840) rsadsi(113549) digestAlgorithm(2) 11 } */ + +#define MBEDTLS_OID_HMAC_SHA3_224 MBEDTLS_OID_NIST_ALG "\x02\x0d" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-224(13) } */ + +#define MBEDTLS_OID_HMAC_SHA3_256 MBEDTLS_OID_NIST_ALG "\x02\x0e" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-256(14) } */ + +#define MBEDTLS_OID_HMAC_SHA3_384 MBEDTLS_OID_NIST_ALG "\x02\x0f" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-384(15) } */ + +#define MBEDTLS_OID_HMAC_SHA3_512 MBEDTLS_OID_NIST_ALG "\x02\x10" /**< id-hmacWithSHA3-512 OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithms(4) hashalgs(2) hmacWithSHA3-512(16) } */ + +#define MBEDTLS_OID_HMAC_RIPEMD160 MBEDTLS_OID_INTERNET "\x05\x05\x08\x01\x04" /**< id-hmacWithSHA1 OBJECT IDENTIFIER ::= {iso(1) iso-identified-organization(3) dod(6) internet(1) security(5) mechanisms(5) ipsec(8) isakmpOakley(1) hmacRIPEMD160(4)} */ + +/* + * Encryption algorithms + */ +#define MBEDTLS_OID_DES_CBC MBEDTLS_OID_ISO_IDENTIFIED_ORG \ + MBEDTLS_OID_OIW_SECSIG_ALG "\x07" /**< desCBC OBJECT IDENTIFIER ::= { iso(1) identified-organization(3) oiw(14) secsig(3) algorithms(2) 7 } */ +#define MBEDTLS_OID_DES_EDE3_CBC MBEDTLS_OID_RSA_COMPANY "\x03\x07" /**< des-ede3-cbc OBJECT IDENTIFIER ::= { iso(1) member-body(2) -- us(840) rsadsi(113549) encryptionAlgorithm(3) 7 } */ +#define MBEDTLS_OID_AES MBEDTLS_OID_NIST_ALG "\x01" /** aes OBJECT IDENTIFIER ::= { joint-iso-itu-t(2) country(16) us(840) organization(1) gov(101) csor(3) nistAlgorithm(4) 1 } */ + +/* + * Key Wrapping algorithms + */ +/* + * RFC 5649 + */ +#define MBEDTLS_OID_AES128_KW MBEDTLS_OID_AES "\x05" /** id-aes128-wrap OBJECT IDENTIFIER ::= { aes 5 } */ +#define MBEDTLS_OID_AES128_KWP MBEDTLS_OID_AES "\x08" /** id-aes128-wrap-pad OBJECT IDENTIFIER ::= { aes 8 } */ +#define MBEDTLS_OID_AES192_KW MBEDTLS_OID_AES "\x19" /** id-aes192-wrap OBJECT IDENTIFIER ::= { aes 25 } */ +#define MBEDTLS_OID_AES192_KWP MBEDTLS_OID_AES "\x1c" /** id-aes192-wrap-pad OBJECT IDENTIFIER ::= { aes 28 } */ +#define MBEDTLS_OID_AES256_KW MBEDTLS_OID_AES "\x2d" /** id-aes256-wrap OBJECT IDENTIFIER ::= { aes 45 } */ +#define MBEDTLS_OID_AES256_KWP MBEDTLS_OID_AES "\x30" /** id-aes256-wrap-pad OBJECT IDENTIFIER ::= { aes 48 } */ +/* + * PKCS#5 OIDs + */ +#define MBEDTLS_OID_PKCS5_PBKDF2 MBEDTLS_OID_PKCS5 "\x0c" /**< id-PBKDF2 OBJECT IDENTIFIER ::= {pkcs-5 12} */ +#define MBEDTLS_OID_PKCS5_PBES2 MBEDTLS_OID_PKCS5 "\x0d" /**< id-PBES2 OBJECT IDENTIFIER ::= {pkcs-5 13} */ +#define MBEDTLS_OID_PKCS5_PBMAC1 MBEDTLS_OID_PKCS5 "\x0e" /**< id-PBMAC1 OBJECT IDENTIFIER ::= {pkcs-5 14} */ + +/* + * PKCS#5 PBES1 algorithms + */ +#define MBEDTLS_OID_PKCS5_PBE_MD5_DES_CBC MBEDTLS_OID_PKCS5 "\x03" /**< pbeWithMD5AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 3} */ +#define MBEDTLS_OID_PKCS5_PBE_MD5_RC2_CBC MBEDTLS_OID_PKCS5 "\x06" /**< pbeWithMD5AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 6} */ +#define MBEDTLS_OID_PKCS5_PBE_SHA1_DES_CBC MBEDTLS_OID_PKCS5 "\x0a" /**< pbeWithSHA1AndDES-CBC OBJECT IDENTIFIER ::= {pkcs-5 10} */ +#define MBEDTLS_OID_PKCS5_PBE_SHA1_RC2_CBC MBEDTLS_OID_PKCS5 "\x0b" /**< pbeWithSHA1AndRC2-CBC OBJECT IDENTIFIER ::= {pkcs-5 11} */ + +/* + * PKCS#7 OIDs + */ +#define MBEDTLS_OID_PKCS7_DATA MBEDTLS_OID_PKCS7 "\x01" /**< Content type is Data OBJECT IDENTIFIER ::= {pkcs-7 1} */ +#define MBEDTLS_OID_PKCS7_SIGNED_DATA MBEDTLS_OID_PKCS7 "\x02" /**< Content type is Signed Data OBJECT IDENTIFIER ::= {pkcs-7 2} */ +#define MBEDTLS_OID_PKCS7_ENVELOPED_DATA MBEDTLS_OID_PKCS7 "\x03" /**< Content type is Enveloped Data OBJECT IDENTIFIER ::= {pkcs-7 3} */ +#define MBEDTLS_OID_PKCS7_SIGNED_AND_ENVELOPED_DATA MBEDTLS_OID_PKCS7 "\x04" /**< Content type is Signed and Enveloped Data OBJECT IDENTIFIER ::= {pkcs-7 4} */ +#define MBEDTLS_OID_PKCS7_DIGESTED_DATA MBEDTLS_OID_PKCS7 "\x05" /**< Content type is Digested Data OBJECT IDENTIFIER ::= {pkcs-7 5} */ +#define MBEDTLS_OID_PKCS7_ENCRYPTED_DATA MBEDTLS_OID_PKCS7 "\x06" /**< Content type is Encrypted Data OBJECT IDENTIFIER ::= {pkcs-7 6} */ + +/* + * PKCS#8 OIDs + */ +#define MBEDTLS_OID_PKCS9_CSR_EXT_REQ MBEDTLS_OID_PKCS9 "\x0e" /**< extensionRequest OBJECT IDENTIFIER ::= {pkcs-9 14} */ + +/* + * PKCS#12 PBE OIDs + */ +#define MBEDTLS_OID_PKCS12_PBE MBEDTLS_OID_PKCS12 "\x01" /**< pkcs-12PbeIds OBJECT IDENTIFIER ::= {pkcs-12 1} */ + +#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES3_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x03" /**< pbeWithSHAAnd3-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 3} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_DES2_EDE_CBC MBEDTLS_OID_PKCS12_PBE "\x04" /**< pbeWithSHAAnd2-KeyTripleDES-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 4} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_128_CBC MBEDTLS_OID_PKCS12_PBE "\x05" /**< pbeWithSHAAnd128BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 5} */ +#define MBEDTLS_OID_PKCS12_PBE_SHA1_RC2_40_CBC MBEDTLS_OID_PKCS12_PBE "\x06" /**< pbeWithSHAAnd40BitRC2-CBC OBJECT IDENTIFIER ::= {pkcs-12PbeIds 6} */ + +/* + * EC key algorithms from RFC 5480 + */ + +/* id-ecPublicKey OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) keyType(2) 1 } */ +#define MBEDTLS_OID_EC_ALG_UNRESTRICTED MBEDTLS_OID_ANSI_X9_62 "\x02\01" + +/* id-ecDH OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) + * schemes(1) ecdh(12) } */ +#define MBEDTLS_OID_EC_ALG_ECDH MBEDTLS_OID_CERTICOM "\x01\x0c" + +/* + * ECParameters namedCurve identifiers, from RFC 5480, RFC 5639, and SEC2 + */ + +/* secp192r1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 1 } */ +#define MBEDTLS_OID_EC_GRP_SECP192R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x01" + +/* secp224r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 33 } */ +#define MBEDTLS_OID_EC_GRP_SECP224R1 MBEDTLS_OID_CERTICOM "\x00\x21" + +/* secp256r1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) curves(3) prime(1) 7 } */ +#define MBEDTLS_OID_EC_GRP_SECP256R1 MBEDTLS_OID_ANSI_X9_62 "\x03\x01\x07" + +/* secp384r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 34 } */ +#define MBEDTLS_OID_EC_GRP_SECP384R1 MBEDTLS_OID_CERTICOM "\x00\x22" + +/* secp521r1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 35 } */ +#define MBEDTLS_OID_EC_GRP_SECP521R1 MBEDTLS_OID_CERTICOM "\x00\x23" + +/* secp192k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 31 } */ +#define MBEDTLS_OID_EC_GRP_SECP192K1 MBEDTLS_OID_CERTICOM "\x00\x1f" + +/* secp224k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 32 } */ +#define MBEDTLS_OID_EC_GRP_SECP224K1 MBEDTLS_OID_CERTICOM "\x00\x20" + +/* secp256k1 OBJECT IDENTIFIER ::= { + * iso(1) identified-organization(3) certicom(132) curve(0) 10 } */ +#define MBEDTLS_OID_EC_GRP_SECP256K1 MBEDTLS_OID_CERTICOM "\x00\x0a" + +/* RFC 5639 4.1 + * ecStdCurvesAndGeneration OBJECT IDENTIFIER::= {iso(1) + * identified-organization(3) teletrust(36) algorithm(3) signature- + * algorithm(3) ecSign(2) 8} + * ellipticCurve OBJECT IDENTIFIER ::= {ecStdCurvesAndGeneration 1} + * versionOne OBJECT IDENTIFIER ::= {ellipticCurve 1} */ +#define MBEDTLS_OID_EC_BRAINPOOL_V1 MBEDTLS_OID_TELETRUST "\x03\x03\x02\x08\x01\x01" + +/* brainpoolP256r1 OBJECT IDENTIFIER ::= {versionOne 7} */ +#define MBEDTLS_OID_EC_GRP_BP256R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x07" + +/* brainpoolP384r1 OBJECT IDENTIFIER ::= {versionOne 11} */ +#define MBEDTLS_OID_EC_GRP_BP384R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0B" + +/* brainpoolP512r1 OBJECT IDENTIFIER ::= {versionOne 13} */ +#define MBEDTLS_OID_EC_GRP_BP512R1 MBEDTLS_OID_EC_BRAINPOOL_V1 "\x0D" + +/* + * SEC1 C.1 + * + * prime-field OBJECT IDENTIFIER ::= { id-fieldType 1 } + * id-fieldType OBJECT IDENTIFIER ::= { ansi-X9-62 fieldType(1)} + */ +#define MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE MBEDTLS_OID_ANSI_X9_62 "\x01" +#define MBEDTLS_OID_ANSI_X9_62_PRIME_FIELD MBEDTLS_OID_ANSI_X9_62_FIELD_TYPE "\x01" + +/* + * ECDSA signature identifiers, from RFC 5480 + */ +#define MBEDTLS_OID_ANSI_X9_62_SIG MBEDTLS_OID_ANSI_X9_62 "\x04" /* signatures(4) */ +#define MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 MBEDTLS_OID_ANSI_X9_62_SIG "\x03" /* ecdsa-with-SHA2(3) */ + +/* ecdsa-with-SHA1 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) 1 } */ +#define MBEDTLS_OID_ECDSA_SHA1 MBEDTLS_OID_ANSI_X9_62_SIG "\x01" + +/* ecdsa-with-SHA224 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 1 } */ +#define MBEDTLS_OID_ECDSA_SHA224 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x01" + +/* ecdsa-with-SHA256 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 2 } */ +#define MBEDTLS_OID_ECDSA_SHA256 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x02" + +/* ecdsa-with-SHA384 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 3 } */ +#define MBEDTLS_OID_ECDSA_SHA384 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x03" + +/* ecdsa-with-SHA512 OBJECT IDENTIFIER ::= { + * iso(1) member-body(2) us(840) ansi-X9-62(10045) signatures(4) + * ecdsa-with-SHA2(3) 4 } */ +#define MBEDTLS_OID_ECDSA_SHA512 MBEDTLS_OID_ANSI_X9_62_SIG_SHA2 "\x04" + +/* + * EC key algorithms from RFC 8410 + */ + +#define MBEDTLS_OID_X25519 MBEDTLS_OID_THAWTE "\x6e" /**< id-X25519 OBJECT IDENTIFIER ::= { 1 3 101 110 } */ +#define MBEDTLS_OID_X448 MBEDTLS_OID_THAWTE "\x6f" /**< id-X448 OBJECT IDENTIFIER ::= { 1 3 101 111 } */ +#define MBEDTLS_OID_ED25519 MBEDTLS_OID_THAWTE "\x70" /**< id-Ed25519 OBJECT IDENTIFIER ::= { 1 3 101 112 } */ +#define MBEDTLS_OID_ED448 MBEDTLS_OID_THAWTE "\x71" /**< id-Ed448 OBJECT IDENTIFIER ::= { 1 3 101 113 } */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Base OID descriptor structure + */ +typedef struct mbedtls_oid_descriptor_t { + const char *MBEDTLS_PRIVATE(asn1); /*!< OID ASN.1 representation */ + size_t MBEDTLS_PRIVATE(asn1_len); /*!< length of asn1 */ +#if !defined(MBEDTLS_X509_REMOVE_INFO) + const char *MBEDTLS_PRIVATE(name); /*!< official name (e.g. from RFC) */ + const char *MBEDTLS_PRIVATE(description); /*!< human friendly description */ +#endif +} mbedtls_oid_descriptor_t; + +/** + * \brief Translate an ASN.1 OID into its numeric representation + * (e.g. "\x2A\x86\x48\x86\xF7\x0D" into "1.2.840.113549") + * + * \param buf buffer to put representation in + * \param size size of the buffer + * \param oid OID to translate + * + * \return Length of the string written (excluding final NULL) or + * MBEDTLS_ERR_OID_BUF_TOO_SMALL in case of error + */ +int mbedtls_oid_get_numeric_string(char *buf, size_t size, const mbedtls_asn1_buf *oid); + +/** + * \brief Translate a string containing a dotted-decimal + * representation of an ASN.1 OID into its encoded form + * (e.g. "1.2.840.113549" into "\x2A\x86\x48\x86\xF7\x0D"). + * On success, this function allocates oid->buf from the + * heap. It must be freed by the caller using mbedtls_free(). + * + * \param oid #mbedtls_asn1_buf to populate with the DER-encoded OID + * \param oid_str string representation of the OID to parse + * \param size length of the OID string, not including any null terminator + * + * \return 0 if successful + * \return #MBEDTLS_ERR_ASN1_INVALID_DATA if \p oid_str does not + * represent a valid OID + * \return #MBEDTLS_ERR_ASN1_ALLOC_FAILED if the function fails to + * allocate oid->buf + */ +int mbedtls_oid_from_numeric_string(mbedtls_asn1_buf *oid, const char *oid_str, size_t size); + +/** + * \brief Translate an X.509 extension OID into local values + * + * \param oid OID to use + * \param ext_type place to store the extension type + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_x509_ext_type(const mbedtls_asn1_buf *oid, int *ext_type); + +/** + * \brief Translate an X.509 attribute type OID into the short name + * (e.g. the OID for an X520 Common Name into "CN") + * + * \param oid OID to use + * \param short_name place to store the string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_attr_short_name(const mbedtls_asn1_buf *oid, const char **short_name); + +/** + * \brief Translate PublicKeyAlgorithm OID into pk_type + * + * \param oid OID to use + * \param pk_alg place to store public key algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_pk_alg(const mbedtls_asn1_buf *oid, mbedtls_pk_type_t *pk_alg); + +/** + * \brief Translate pk_type into PublicKeyAlgorithm OID + * + * \param pk_alg Public key type to look for + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_pk_alg(mbedtls_pk_type_t pk_alg, + const char **oid, size_t *olen); + +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) +/** + * \brief Translate NamedCurve OID into an EC group identifier + * + * \param oid OID to use + * \param grp_id place to store group id + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_ec_grp(const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id); + +/** + * \brief Translate EC group identifier into NamedCurve OID + * + * \param grp_id EC group identifier + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_ec_grp(mbedtls_ecp_group_id grp_id, + const char **oid, size_t *olen); + +/** + * \brief Translate AlgorithmIdentifier OID into an EC group identifier, + * for curves that are directly encoded at this level + * + * \param oid OID to use + * \param grp_id place to store group id + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_ec_grp_algid(const mbedtls_asn1_buf *oid, mbedtls_ecp_group_id *grp_id); + +/** + * \brief Translate EC group identifier into AlgorithmIdentifier OID, + * for curves that are directly encoded at this level + * + * \param grp_id EC group identifier + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_ec_grp_algid(mbedtls_ecp_group_id grp_id, + const char **oid, size_t *olen); +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ + +/** + * \brief Translate SignatureAlgorithm OID into md_type and pk_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * \param pk_alg place to store public key algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_sig_alg(const mbedtls_asn1_buf *oid, + mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg); + +/** + * \brief Translate SignatureAlgorithm OID into description + * + * \param oid OID to use + * \param desc place to store string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_sig_alg_desc(const mbedtls_asn1_buf *oid, const char **desc); + +/** + * \brief Translate md_type and pk_type into SignatureAlgorithm OID + * + * \param md_alg message digest algorithm + * \param pk_alg public key algorithm + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_sig_alg(mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, + const char **oid, size_t *olen); + +/** + * \brief Translate hmac algorithm OID into md_type + * + * \param oid OID to use + * \param md_hmac place to store message hmac algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_md_hmac(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_hmac); + +/** + * \brief Translate hash algorithm OID into md_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_md_alg(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg); + +#if !defined(MBEDTLS_X509_REMOVE_INFO) +/** + * \brief Translate Extended Key Usage OID into description + * + * \param oid OID to use + * \param desc place to store string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_extended_key_usage(const mbedtls_asn1_buf *oid, const char **desc); +#endif + +/** + * \brief Translate certificate policies OID into description + * + * \param oid OID to use + * \param desc place to store string pointer + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_certificate_policies(const mbedtls_asn1_buf *oid, const char **desc); + +/** + * \brief Translate md_type into hash algorithm OID + * + * \param md_alg message digest algorithm + * \param oid place to store ASN.1 OID string pointer + * \param olen length of the OID + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_oid_by_md(mbedtls_md_type_t md_alg, const char **oid, size_t *olen); + +#if defined(MBEDTLS_CIPHER_C) +/** + * \brief Translate encryption algorithm OID into cipher_type + * + * \param oid OID to use + * \param cipher_alg place to store cipher algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_cipher_alg(const mbedtls_asn1_buf *oid, mbedtls_cipher_type_t *cipher_alg); +#endif /* MBEDTLS_CIPHER_C */ + +#if defined(MBEDTLS_PKCS12_C) +/** + * \brief Translate PKCS#12 PBE algorithm OID into md_type and + * cipher_type + * + * \param oid OID to use + * \param md_alg place to store message digest algorithm + * \param cipher_alg place to store cipher algorithm + * + * \return 0 if successful, or MBEDTLS_ERR_OID_NOT_FOUND + */ +int mbedtls_oid_get_pkcs12_pbe_alg(const mbedtls_asn1_buf *oid, mbedtls_md_type_t *md_alg, + mbedtls_cipher_type_t *cipher_alg); +#endif /* MBEDTLS_PKCS12_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* oid.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pem.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pem.h index a33fc65..bcb4edb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pem.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pem.h @@ -1,172 +1,172 @@ -/** - * \file pem.h - * - * \brief Privacy Enhanced Mail (PEM) decoding - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PEM_H -#define MBEDTLS_PEM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include - -/** - * \name PEM Error codes - * These error codes are returned in case of errors reading the - * PEM data. - * \{ - */ -/** No PEM header or footer found. */ -#define MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT -0x1080 -/** PEM string is not as expected. */ -#define MBEDTLS_ERR_PEM_INVALID_DATA -0x1100 -/** Failed to allocate memory. */ -#define MBEDTLS_ERR_PEM_ALLOC_FAILED -0x1180 -/** RSA IV is not in hex-format. */ -#define MBEDTLS_ERR_PEM_INVALID_ENC_IV -0x1200 -/** Unsupported key encryption algorithm. */ -#define MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG -0x1280 -/** Private key password can't be empty. */ -#define MBEDTLS_ERR_PEM_PASSWORD_REQUIRED -0x1300 -/** Given private key password does not allow for correct decryption. */ -#define MBEDTLS_ERR_PEM_PASSWORD_MISMATCH -0x1380 -/** Unavailable feature, e.g. hashing/encryption combination. */ -#define MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE -0x1400 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_PEM_BAD_INPUT_DATA -0x1480 -/** \} name PEM Error codes */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(MBEDTLS_PEM_PARSE_C) -/** - * \brief PEM context structure - */ -typedef struct mbedtls_pem_context { - unsigned char *MBEDTLS_PRIVATE(buf); /*!< buffer for decoded data */ - size_t MBEDTLS_PRIVATE(buflen); /*!< length of the buffer */ - unsigned char *MBEDTLS_PRIVATE(info); /*!< buffer for extra header information */ -} -mbedtls_pem_context; - -/** - * \brief PEM context setup - * - * \param ctx context to be initialized - */ -void mbedtls_pem_init(mbedtls_pem_context *ctx); - -/** - * \brief Read a buffer for PEM information and store the resulting - * data into the specified context buffers. - * - * \param ctx context to use - * \param header header string to seek and expect - * \param footer footer string to seek and expect - * \param data source data to look in (must be nul-terminated) - * \param pwd password for decryption (can be NULL) - * \param pwdlen length of password - * \param use_len destination for total length used (set after header is - * correctly read, so unless you get - * MBEDTLS_ERR_PEM_BAD_INPUT_DATA or - * MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT, use_len is - * the length to skip) - * - * \note Attempts to check password correctness by verifying if - * the decrypted text starts with an ASN.1 sequence of - * appropriate length - * - * \note \c mbedtls_pem_free must be called on PEM context before - * the PEM context can be reused in another call to - * \c mbedtls_pem_read_buffer - * - * \return 0 on success, or a specific PEM error code - */ -int mbedtls_pem_read_buffer(mbedtls_pem_context *ctx, const char *header, const char *footer, - const unsigned char *data, - const unsigned char *pwd, - size_t pwdlen, size_t *use_len); - -/** - * \brief Get the pointer to the decoded binary data in a PEM context. - * - * \param ctx PEM context to access. - * \param buflen On success, this will contain the length of the binary data. - * This must be a valid (non-null) pointer. - * - * \return A pointer to the decoded binary data. - * - * \note The returned pointer remains valid only until \p ctx is - modified or freed. - */ -static inline const unsigned char *mbedtls_pem_get_buffer(mbedtls_pem_context *ctx, size_t *buflen) -{ - *buflen = ctx->MBEDTLS_PRIVATE(buflen); - return ctx->MBEDTLS_PRIVATE(buf); -} - - -/** - * \brief PEM context memory freeing - * - * \param ctx context to be freed - */ -void mbedtls_pem_free(mbedtls_pem_context *ctx); -#endif /* MBEDTLS_PEM_PARSE_C */ - -#if defined(MBEDTLS_PEM_WRITE_C) -/** - * \brief Write a buffer of PEM information from a DER encoded - * buffer. - * - * \param header The header string to write. - * \param footer The footer string to write. - * \param der_data The DER data to encode. - * \param der_len The length of the DER data \p der_data in Bytes. - * \param buf The buffer to write to. - * \param buf_len The length of the output buffer \p buf in Bytes. - * \param olen The address at which to store the total length written - * or required (if \p buf_len is not enough). - * - * \note You may pass \c NULL for \p buf and \c 0 for \p buf_len - * to request the length of the resulting PEM buffer in - * `*olen`. - * - * \note This function may be called with overlapping \p der_data - * and \p buf buffers. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL if \p buf isn't large - * enough to hold the PEM buffer. In this case, `*olen` holds - * the required minimum size of \p buf. - * \return Another PEM or BASE64 error code on other kinds of failure. - */ -int mbedtls_pem_write_buffer(const char *header, const char *footer, - const unsigned char *der_data, size_t der_len, - unsigned char *buf, size_t buf_len, size_t *olen); -#endif /* MBEDTLS_PEM_WRITE_C */ - -#ifdef __cplusplus -} -#endif - -#endif /* pem.h */ +/** + * \file pem.h + * + * \brief Privacy Enhanced Mail (PEM) decoding + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PEM_H +#define MBEDTLS_PEM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include + +/** + * \name PEM Error codes + * These error codes are returned in case of errors reading the + * PEM data. + * \{ + */ +/** No PEM header or footer found. */ +#define MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT -0x1080 +/** PEM string is not as expected. */ +#define MBEDTLS_ERR_PEM_INVALID_DATA -0x1100 +/** Failed to allocate memory. */ +#define MBEDTLS_ERR_PEM_ALLOC_FAILED -0x1180 +/** RSA IV is not in hex-format. */ +#define MBEDTLS_ERR_PEM_INVALID_ENC_IV -0x1200 +/** Unsupported key encryption algorithm. */ +#define MBEDTLS_ERR_PEM_UNKNOWN_ENC_ALG -0x1280 +/** Private key password can't be empty. */ +#define MBEDTLS_ERR_PEM_PASSWORD_REQUIRED -0x1300 +/** Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PEM_PASSWORD_MISMATCH -0x1380 +/** Unavailable feature, e.g. hashing/encryption combination. */ +#define MBEDTLS_ERR_PEM_FEATURE_UNAVAILABLE -0x1400 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_PEM_BAD_INPUT_DATA -0x1480 +/** \} name PEM Error codes */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_PEM_PARSE_C) +/** + * \brief PEM context structure + */ +typedef struct mbedtls_pem_context { + unsigned char *MBEDTLS_PRIVATE(buf); /*!< buffer for decoded data */ + size_t MBEDTLS_PRIVATE(buflen); /*!< length of the buffer */ + unsigned char *MBEDTLS_PRIVATE(info); /*!< buffer for extra header information */ +} +mbedtls_pem_context; + +/** + * \brief PEM context setup + * + * \param ctx context to be initialized + */ +void mbedtls_pem_init(mbedtls_pem_context *ctx); + +/** + * \brief Read a buffer for PEM information and store the resulting + * data into the specified context buffers. + * + * \param ctx context to use + * \param header header string to seek and expect + * \param footer footer string to seek and expect + * \param data source data to look in (must be nul-terminated) + * \param pwd password for decryption (can be NULL) + * \param pwdlen length of password + * \param use_len destination for total length used (set after header is + * correctly read, so unless you get + * MBEDTLS_ERR_PEM_BAD_INPUT_DATA or + * MBEDTLS_ERR_PEM_NO_HEADER_FOOTER_PRESENT, use_len is + * the length to skip) + * + * \note Attempts to check password correctness by verifying if + * the decrypted text starts with an ASN.1 sequence of + * appropriate length + * + * \note \c mbedtls_pem_free must be called on PEM context before + * the PEM context can be reused in another call to + * \c mbedtls_pem_read_buffer + * + * \return 0 on success, or a specific PEM error code + */ +int mbedtls_pem_read_buffer(mbedtls_pem_context *ctx, const char *header, const char *footer, + const unsigned char *data, + const unsigned char *pwd, + size_t pwdlen, size_t *use_len); + +/** + * \brief Get the pointer to the decoded binary data in a PEM context. + * + * \param ctx PEM context to access. + * \param buflen On success, this will contain the length of the binary data. + * This must be a valid (non-null) pointer. + * + * \return A pointer to the decoded binary data. + * + * \note The returned pointer remains valid only until \p ctx is + modified or freed. + */ +static inline const unsigned char *mbedtls_pem_get_buffer(mbedtls_pem_context *ctx, size_t *buflen) +{ + *buflen = ctx->MBEDTLS_PRIVATE(buflen); + return ctx->MBEDTLS_PRIVATE(buf); +} + + +/** + * \brief PEM context memory freeing + * + * \param ctx context to be freed + */ +void mbedtls_pem_free(mbedtls_pem_context *ctx); +#endif /* MBEDTLS_PEM_PARSE_C */ + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a buffer of PEM information from a DER encoded + * buffer. + * + * \param header The header string to write. + * \param footer The footer string to write. + * \param der_data The DER data to encode. + * \param der_len The length of the DER data \p der_data in Bytes. + * \param buf The buffer to write to. + * \param buf_len The length of the output buffer \p buf in Bytes. + * \param olen The address at which to store the total length written + * or required (if \p buf_len is not enough). + * + * \note You may pass \c NULL for \p buf and \c 0 for \p buf_len + * to request the length of the resulting PEM buffer in + * `*olen`. + * + * \note This function may be called with overlapping \p der_data + * and \p buf buffers. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_BASE64_BUFFER_TOO_SMALL if \p buf isn't large + * enough to hold the PEM buffer. In this case, `*olen` holds + * the required minimum size of \p buf. + * \return Another PEM or BASE64 error code on other kinds of failure. + */ +int mbedtls_pem_write_buffer(const char *header, const char *footer, + const unsigned char *der_data, size_t der_len, + unsigned char *buf, size_t buf_len, size_t *olen); +#endif /* MBEDTLS_PEM_WRITE_C */ + +#ifdef __cplusplus +} +#endif + +#endif /* pem.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pk.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pk.h index 68ebd73..ace3de5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pk.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pk.h @@ -1,1107 +1,1107 @@ -/** - * \file pk.h - * - * \brief Public Key abstraction layer - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PK_H -#define MBEDTLS_PK_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/md.h" - -#if defined(MBEDTLS_RSA_C) -#include "mbedtls/rsa.h" -#endif - -#if defined(MBEDTLS_ECP_C) -#include "mbedtls/ecp.h" -#endif - -#if defined(MBEDTLS_ECDSA_C) -#include "mbedtls/ecdsa.h" -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_PSA_CRYPTO_C) -#include "psa/crypto.h" -#endif - -/** Memory allocation failed. */ -#define MBEDTLS_ERR_PK_ALLOC_FAILED -0x3F80 -/** Type mismatch, eg attempt to encrypt with an ECDSA key */ -#define MBEDTLS_ERR_PK_TYPE_MISMATCH -0x3F00 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_PK_BAD_INPUT_DATA -0x3E80 -/** Read/write of file failed. */ -#define MBEDTLS_ERR_PK_FILE_IO_ERROR -0x3E00 -/** Unsupported key version */ -#define MBEDTLS_ERR_PK_KEY_INVALID_VERSION -0x3D80 -/** Invalid key tag or value. */ -#define MBEDTLS_ERR_PK_KEY_INVALID_FORMAT -0x3D00 -/** Key algorithm is unsupported (only RSA and EC are supported). */ -#define MBEDTLS_ERR_PK_UNKNOWN_PK_ALG -0x3C80 -/** Private key password can't be empty. */ -#define MBEDTLS_ERR_PK_PASSWORD_REQUIRED -0x3C00 -/** Given private key password does not allow for correct decryption. */ -#define MBEDTLS_ERR_PK_PASSWORD_MISMATCH -0x3B80 -/** The pubkey tag or value is invalid (only RSA and EC are supported). */ -#define MBEDTLS_ERR_PK_INVALID_PUBKEY -0x3B00 -/** The algorithm tag or value is invalid. */ -#define MBEDTLS_ERR_PK_INVALID_ALG -0x3A80 -/** Elliptic curve is unsupported (only NIST curves are supported). */ -#define MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE -0x3A00 -/** Unavailable feature, e.g. RSA disabled for RSA key. */ -#define MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE -0x3980 -/** The buffer contains a valid signature followed by more data. */ -#define MBEDTLS_ERR_PK_SIG_LEN_MISMATCH -0x3900 -/** The output buffer is too small. */ -#define MBEDTLS_ERR_PK_BUFFER_TOO_SMALL -0x3880 - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Public key types - */ -typedef enum { - MBEDTLS_PK_NONE=0, - MBEDTLS_PK_RSA, - MBEDTLS_PK_ECKEY, - MBEDTLS_PK_ECKEY_DH, - MBEDTLS_PK_ECDSA, - MBEDTLS_PK_RSA_ALT, - MBEDTLS_PK_RSASSA_PSS, - MBEDTLS_PK_OPAQUE, -} mbedtls_pk_type_t; - -/** - * \brief Options for RSASSA-PSS signature verification. - * See \c mbedtls_rsa_rsassa_pss_verify_ext() - */ -typedef struct mbedtls_pk_rsassa_pss_options { - /** The digest to use for MGF1 in PSS. - * - * \note When #MBEDTLS_USE_PSA_CRYPTO is enabled and #MBEDTLS_RSA_C is - * disabled, this must be equal to the \c md_alg argument passed - * to mbedtls_pk_verify_ext(). In a future version of the library, - * this constraint may apply whenever #MBEDTLS_USE_PSA_CRYPTO is - * enabled regardless of the status of #MBEDTLS_RSA_C. - */ - mbedtls_md_type_t mgf1_hash_id; - - /** The expected length of the salt, in bytes. This may be - * #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length. - * - * \note When #MBEDTLS_USE_PSA_CRYPTO is enabled, only - * #MBEDTLS_RSA_SALT_LEN_ANY is valid. Any other value may be - * ignored (allowing any salt length). - */ - int expected_salt_len; - -} mbedtls_pk_rsassa_pss_options; - -/** - * \brief Maximum size of a signature made by mbedtls_pk_sign(). - */ -/* We need to set MBEDTLS_PK_SIGNATURE_MAX_SIZE to the maximum signature - * size among the supported signature types. Do it by starting at 0, - * then incrementally increasing to be large enough for each supported - * signature mechanism. - * - * The resulting value can be 0, for example if MBEDTLS_ECDH_C is enabled - * (which allows the pk module to be included) but neither MBEDTLS_ECDSA_C - * nor MBEDTLS_RSA_C nor any opaque signature mechanism (PSA or RSA_ALT). - */ -#define MBEDTLS_PK_SIGNATURE_MAX_SIZE 0 - -#if (defined(MBEDTLS_RSA_C) || defined(MBEDTLS_PK_RSA_ALT_SUPPORT)) && \ - MBEDTLS_MPI_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE -/* For RSA, the signature can be as large as the bignum module allows. - * For RSA_ALT, the signature size is not necessarily tied to what the - * bignum module can do, but in the absence of any specific setting, - * we use that (rsa_alt_sign_wrap in library/pk_wrap.h will check). */ -#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE -#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_MPI_MAX_SIZE -#endif - -#if defined(MBEDTLS_ECDSA_C) && \ - MBEDTLS_ECDSA_MAX_LEN > MBEDTLS_PK_SIGNATURE_MAX_SIZE -/* For ECDSA, the ecdsa module exports a constant for the maximum - * signature size. */ -#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE -#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_ECDSA_MAX_LEN -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#if PSA_SIGNATURE_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE -/* PSA_SIGNATURE_MAX_SIZE is the maximum size of a signature made - * through the PSA API in the PSA representation. */ -#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE -#define MBEDTLS_PK_SIGNATURE_MAX_SIZE PSA_SIGNATURE_MAX_SIZE -#endif - -#if PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11 > MBEDTLS_PK_SIGNATURE_MAX_SIZE -/* The Mbed TLS representation is different for ECDSA signatures: - * PSA uses the raw concatenation of r and s, - * whereas Mbed TLS uses the ASN.1 representation (SEQUENCE of two INTEGERs). - * Add the overhead of ASN.1: up to (1+2) + 2 * (1+2+1) for the - * types, lengths (represented by up to 2 bytes), and potential leading - * zeros of the INTEGERs and the SEQUENCE. */ -#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE -#define MBEDTLS_PK_SIGNATURE_MAX_SIZE (PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11) -#endif -#endif /* defined(MBEDTLS_USE_PSA_CRYPTO) */ - -/* Internal helper to define which fields in the pk_context structure below - * should be used for EC keys: legacy ecp_keypair or the raw (PSA friendly) - * format. It should be noted that this only affects how data is stored, not - * which functions are used for various operations. The overall picture looks - * like this: - * - if USE_PSA is not defined and ECP_C is defined then use ecp_keypair data - * structure and legacy functions - * - if USE_PSA is defined and - * - if ECP_C then use ecp_keypair structure, convert data to a PSA friendly - * format and use PSA functions - * - if !ECP_C then use new raw data and PSA functions directly. - * - * The main reason for the "intermediate" (USE_PSA + ECP_C) above is that as long - * as ECP_C is defined mbedtls_pk_ec() gives the user a read/write access to the - * ecp_keypair structure inside the pk_context so they can modify it using - * ECP functions which are not under PK module's control. - */ -#if defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) && \ - !defined(MBEDTLS_ECP_C) -#define MBEDTLS_PK_USE_PSA_EC_DATA -#endif - -/* Helper symbol to state that the PK module has support for EC keys. This - * can either be provided through the legacy ECP solution or through the - * PSA friendly MBEDTLS_PK_USE_PSA_EC_DATA. */ -#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) || defined(MBEDTLS_ECP_C) -#define MBEDTLS_PK_HAVE_ECC_KEYS -#endif /* MBEDTLS_PK_USE_PSA_EC_DATA || MBEDTLS_ECP_C */ - -/** - * \brief Types for interfacing with the debug module - */ -typedef enum { - MBEDTLS_PK_DEBUG_NONE = 0, - MBEDTLS_PK_DEBUG_MPI, - MBEDTLS_PK_DEBUG_ECP, - MBEDTLS_PK_DEBUG_PSA_EC, -} mbedtls_pk_debug_type; - -/** - * \brief Item to send to the debug module - */ -typedef struct mbedtls_pk_debug_item { - mbedtls_pk_debug_type MBEDTLS_PRIVATE(type); - const char *MBEDTLS_PRIVATE(name); - void *MBEDTLS_PRIVATE(value); -} mbedtls_pk_debug_item; - -/** Maximum number of item send for debugging, plus 1 */ -#define MBEDTLS_PK_DEBUG_MAX_ITEMS 3 - -/** - * \brief Public key information and operations - * - * \note The library does not support custom pk info structures, - * only built-in structures returned by - * mbedtls_cipher_info_from_type(). - */ -typedef struct mbedtls_pk_info_t mbedtls_pk_info_t; - -#define MBEDTLS_PK_MAX_EC_PUBKEY_RAW_LEN \ - PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) -/** - * \brief Public key container - */ -typedef struct mbedtls_pk_context { - const mbedtls_pk_info_t *MBEDTLS_PRIVATE(pk_info); /**< Public key information */ - void *MBEDTLS_PRIVATE(pk_ctx); /**< Underlying public key context */ - /* The following field is used to store the ID of a private key in the - * following cases: - * - opaque key when MBEDTLS_PSA_CRYPTO_C is defined - * - normal key when MBEDTLS_PK_USE_PSA_EC_DATA is defined. In this case: - * - the pk_ctx above is not not used to store the private key anymore. - * Actually that field not populated at all in this case because also - * the public key will be stored in raw format as explained below - * - this ID is used for all private key operations (ex: sign, check - * key pair, key write, etc) using PSA functions - * - * Note: this private key storing solution only affects EC keys, not the - * other ones. The latters still use the pk_ctx to store their own - * context. - * - * Note: this priv_id is guarded by MBEDTLS_PSA_CRYPTO_C and not by - * MBEDTLS_PK_USE_PSA_EC_DATA (as the public counterpart below) because, - * when working with opaque keys, it can be used also in - * mbedtls_pk_sign_ext for RSA keys. */ -#if defined(MBEDTLS_PSA_CRYPTO_C) - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(priv_id); /**< Key ID for opaque keys */ -#else - uint32_t MBEDTLS_PRIVATE(priv_id); /**< Key ID for opaque keys */ -#endif /* MBEDTLS_PSA_CRYPTO_C */ - /* The following fields are meant for storing the public key in raw format - * which is handy for: - * - easily importing it into the PSA context - * - reducing the ECP module dependencies in the PK one. - * - * When MBEDTLS_PK_USE_PSA_EC_DATA is enabled: - * - the pk_ctx above is not used anymore for storing the public key - * inside the ecp_keypair structure - * - the following fields are used for all public key operations: signature - * verify, key pair check and key write. - * Of course, when MBEDTLS_PK_USE_PSA_EC_DATA is not enabled, the legacy - * ecp_keypair structure is used for storing the public key and performing - * all the operations. - * - * Note: This new public key storing solution only works for EC keys, not - * other ones. The latters still use pk_ctx to store their own - * context. - */ - uint8_t MBEDTLS_PRIVATE(pub_raw)[66 * 2 + 1]; /**< Raw public key */ - size_t MBEDTLS_PRIVATE(pub_raw_len); /**< Valid bytes in "pub_raw" */ -#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) - psa_ecc_family_t MBEDTLS_PRIVATE(ec_family); /**< EC family of pk */ -#else - uint8_t MBEDTLS_PRIVATE(ec_family); /**< EC family of pk */ -#endif /* MBEDTLS_PK_USE_PSA_EC_DATA */ - size_t MBEDTLS_PRIVATE(ec_bits); /**< Curve's bits of pk */ -} mbedtls_pk_context; - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Context for resuming operations - */ -typedef struct { - const mbedtls_pk_info_t *MBEDTLS_PRIVATE(pk_info); /**< Public key information */ - void *MBEDTLS_PRIVATE(rs_ctx); /**< Underlying restart context */ -} mbedtls_pk_restart_ctx; -#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ -/* Now we can declare functions that take a pointer to that */ -typedef void mbedtls_pk_restart_ctx; -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - -#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) -/** - * \brief Types for RSA-alt abstraction - */ -typedef int (*mbedtls_pk_rsa_alt_decrypt_func)(void *ctx, size_t *olen, - const unsigned char *input, unsigned char *output, - size_t output_max_len); -typedef int (*mbedtls_pk_rsa_alt_sign_func)(void *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, unsigned int hashlen, - const unsigned char *hash, unsigned char *sig); -typedef size_t (*mbedtls_pk_rsa_alt_key_len_func)(void *ctx); -#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ - -/** - * \brief Return information associated with the given PK type - * - * \param pk_type PK type to search for. - * - * \return The PK info associated with the type or NULL if not found. - */ -const mbedtls_pk_info_t *mbedtls_pk_info_from_type(mbedtls_pk_type_t pk_type); - -/** - * \brief Initialize a #mbedtls_pk_context (as NONE). - * - * \param ctx The context to initialize. - * This must not be \c NULL. - */ -void mbedtls_pk_init(mbedtls_pk_context *ctx); - -/** - * \brief Free the components of a #mbedtls_pk_context. - * - * \param ctx The context to clear. It must have been initialized. - * If this is \c NULL, this function does nothing. - * - * \note For contexts that have been set up with - * mbedtls_pk_setup_opaque(), this does not free the underlying - * PSA key and you still need to call psa_destroy_key() - * independently if you want to destroy that key. - */ -void mbedtls_pk_free(mbedtls_pk_context *ctx); - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Initialize a restart context - * - * \param ctx The context to initialize. - * This must not be \c NULL. - */ -void mbedtls_pk_restart_init(mbedtls_pk_restart_ctx *ctx); - -/** - * \brief Free the components of a restart context - * - * \param ctx The context to clear. It must have been initialized. - * If this is \c NULL, this function does nothing. - */ -void mbedtls_pk_restart_free(mbedtls_pk_restart_ctx *ctx); -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - -/** - * \brief Initialize a PK context with the information given - * and allocates the type-specific PK subcontext. - * - * \param ctx Context to initialize. It must not have been set - * up yet (type #MBEDTLS_PK_NONE). - * \param info Information to use - * - * \return 0 on success, - * MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input, - * MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. - * - * \note For contexts holding an RSA-alt key, use - * \c mbedtls_pk_setup_rsa_alt() instead. - */ -int mbedtls_pk_setup(mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info); - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * \brief Initialize a PK context to wrap a PSA key. - * - * \note This function replaces mbedtls_pk_setup() for contexts - * that wrap a (possibly opaque) PSA key instead of - * storing and manipulating the key material directly. - * - * \param ctx The context to initialize. It must be empty (type NONE). - * \param key The PSA key to wrap, which must hold an ECC or RSA key - * pair (see notes below). - * - * \note The wrapped key must remain valid as long as the - * wrapping PK context is in use, that is at least between - * the point this function is called and the point - * mbedtls_pk_free() is called on this context. The wrapped - * key might then be independently used or destroyed. - * - * \note This function is currently only available for ECC or RSA - * key pairs (that is, keys containing private key material). - * Support for other key types may be added later. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input - * (context already used, invalid key identifier). - * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the key is not an - * ECC key pair. - * \return #MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. - */ -int mbedtls_pk_setup_opaque(mbedtls_pk_context *ctx, - const mbedtls_svc_key_id_t key); -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) -/** - * \brief Initialize an RSA-alt context - * - * \param ctx Context to initialize. It must not have been set - * up yet (type #MBEDTLS_PK_NONE). - * \param key RSA key pointer - * \param decrypt_func Decryption function - * \param sign_func Signing function - * \param key_len_func Function returning key length in bytes - * - * \return 0 on success, or MBEDTLS_ERR_PK_BAD_INPUT_DATA if the - * context wasn't already initialized as RSA_ALT. - * - * \note This function replaces \c mbedtls_pk_setup() for RSA-alt. - */ -int mbedtls_pk_setup_rsa_alt(mbedtls_pk_context *ctx, void *key, - mbedtls_pk_rsa_alt_decrypt_func decrypt_func, - mbedtls_pk_rsa_alt_sign_func sign_func, - mbedtls_pk_rsa_alt_key_len_func key_len_func); -#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ - -/** - * \brief Get the size in bits of the underlying key - * - * \param ctx The context to query. It must have been initialized. - * - * \return Key size in bits, or 0 on error - */ -size_t mbedtls_pk_get_bitlen(const mbedtls_pk_context *ctx); - -/** - * \brief Get the length in bytes of the underlying key - * - * \param ctx The context to query. It must have been initialized. - * - * \return Key length in bytes, or 0 on error - */ -static inline size_t mbedtls_pk_get_len(const mbedtls_pk_context *ctx) -{ - return (mbedtls_pk_get_bitlen(ctx) + 7) / 8; -} - -/** - * \brief Tell if a context can do the operation given by type - * - * \param ctx The context to query. It must have been initialized. - * \param type The desired type. - * - * \return 1 if the context can do operations on the given type. - * \return 0 if the context cannot do the operations on the given - * type. This is always the case for a context that has - * been initialized but not set up, or that has been - * cleared with mbedtls_pk_free(). - */ -int mbedtls_pk_can_do(const mbedtls_pk_context *ctx, mbedtls_pk_type_t type); - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * \brief Tell if context can do the operation given by PSA algorithm - * - * \param ctx The context to query. It must have been initialized. - * \param alg PSA algorithm to check against, the following are allowed: - * PSA_ALG_RSA_PKCS1V15_SIGN(hash), - * PSA_ALG_RSA_PSS(hash), - * PSA_ALG_RSA_PKCS1V15_CRYPT, - * PSA_ALG_ECDSA(hash), - * PSA_ALG_ECDH, where hash is a specific hash. - * \param usage PSA usage flag to check against, must be composed of: - * PSA_KEY_USAGE_SIGN_HASH - * PSA_KEY_USAGE_DECRYPT - * PSA_KEY_USAGE_DERIVE. - * Context key must match all passed usage flags. - * - * \warning Since the set of allowed algorithms and usage flags may be - * expanded in the future, the return value \c 0 should not - * be taken in account for non-allowed algorithms and usage - * flags. - * - * \return 1 if the context can do operations on the given type. - * \return 0 if the context cannot do the operations on the given - * type, for non-allowed algorithms and usage flags, or - * for a context that has been initialized but not set up - * or that has been cleared with mbedtls_pk_free(). - */ -int mbedtls_pk_can_do_ext(const mbedtls_pk_context *ctx, psa_algorithm_t alg, - psa_key_usage_t usage); -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/** - * \brief Verify signature (including padding if relevant). - * - * \param ctx The PK context to use. It must have been set up. - * \param md_alg Hash algorithm used. - * This can be #MBEDTLS_MD_NONE if the signature algorithm - * does not rely on a hash algorithm (non-deterministic - * ECDSA, RSA PKCS#1 v1.5). - * For PKCS#1 v1.5, if \p md_alg is #MBEDTLS_MD_NONE, then - * \p hash is the DigestInfo structure used by RFC 8017 - * §9.2 steps 3–6. If \p md_alg is a valid hash - * algorithm then \p hash is the digest itself, and this - * function calculates the DigestInfo encoding internally. - * \param hash Hash of the message to sign - * \param hash_len Hash length - * \param sig Signature to verify - * \param sig_len Signature length - * - * \return 0 on success (signature is valid), - * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid - * signature in \p sig but its length is less than \p sig_len, - * or a specific error code. - * - * \note For RSA keys, the default padding type is PKCS#1 v1.5. - * Use \c mbedtls_pk_verify_ext( MBEDTLS_PK_RSASSA_PSS, ... ) - * to verify RSASSA_PSS signatures. - */ -int mbedtls_pk_verify(mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - const unsigned char *sig, size_t sig_len); - -/** - * \brief Restartable version of \c mbedtls_pk_verify() - * - * \note Performs the same job as \c mbedtls_pk_verify(), but can - * return early and restart according to the limit set with - * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC - * operations. For RSA, same as \c mbedtls_pk_verify(). - * - * \param ctx The PK context to use. It must have been set up. - * \param md_alg Hash algorithm used (see notes) - * \param hash Hash of the message to sign - * \param hash_len Hash length or 0 (see notes) - * \param sig Signature to verify - * \param sig_len Signature length - * \param rs_ctx Restart context (NULL to disable restart) - * - * \return See \c mbedtls_pk_verify(), or - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - */ -int mbedtls_pk_verify_restartable(mbedtls_pk_context *ctx, - mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - const unsigned char *sig, size_t sig_len, - mbedtls_pk_restart_ctx *rs_ctx); - -/** - * \brief Verify signature, with options. - * (Includes verification of the padding depending on type.) - * - * \param type Signature type (inc. possible padding type) to verify - * \param options Pointer to type-specific options, or NULL - * \param ctx The PK context to use. It must have been set up. - * \param md_alg Hash algorithm used (see notes) - * \param hash Hash of the message to sign - * \param hash_len Hash length or 0 (see notes) - * \param sig Signature to verify - * \param sig_len Signature length - * - * \return 0 on success (signature is valid), - * #MBEDTLS_ERR_PK_TYPE_MISMATCH if the PK context can't be - * used for this type of signatures, - * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid - * signature in \p sig but its length is less than \p sig_len, - * or a specific error code. - * - * \note If hash_len is 0, then the length associated with md_alg - * is used instead, or an error returned if it is invalid. - * - * \note md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0 - * - * \note If type is MBEDTLS_PK_RSASSA_PSS, then options must point - * to a mbedtls_pk_rsassa_pss_options structure, - * otherwise it must be NULL. Note that if - * #MBEDTLS_USE_PSA_CRYPTO is defined, the salt length is not - * verified as PSA_ALG_RSA_PSS_ANY_SALT is used. - */ -int mbedtls_pk_verify_ext(mbedtls_pk_type_t type, const void *options, - mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - const unsigned char *sig, size_t sig_len); - -/** - * \brief Make signature, including padding if relevant. - * - * \param ctx The PK context to use. It must have been set up - * with a private key. - * \param md_alg Hash algorithm used (see notes) - * \param hash Hash of the message to sign - * \param hash_len Hash length - * \param sig Place to write the signature. - * It must have enough room for the signature. - * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. - * You may use a smaller buffer if it is large enough - * given the key type. - * \param sig_size The size of the \p sig buffer in bytes. - * \param sig_len On successful return, - * the number of bytes written to \p sig. - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * - * \return 0 on success, or a specific error code. - * - * \note For RSA keys, the default padding type is PKCS#1 v1.5. - * There is no interface in the PK module to make RSASSA-PSS - * signatures yet. - * - * \note For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0. - * For ECDSA, md_alg may never be MBEDTLS_MD_NONE. - */ -int mbedtls_pk_sign(mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, size_t *sig_len, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -#if defined(MBEDTLS_PSA_CRYPTO_C) -/** - * \brief Make signature given a signature type. - * - * \param pk_type Signature type. - * \param ctx The PK context to use. It must have been set up - * with a private key. - * \param md_alg Hash algorithm used (see notes) - * \param hash Hash of the message to sign - * \param hash_len Hash length - * \param sig Place to write the signature. - * It must have enough room for the signature. - * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. - * You may use a smaller buffer if it is large enough - * given the key type. - * \param sig_size The size of the \p sig buffer in bytes. - * \param sig_len On successful return, - * the number of bytes written to \p sig. - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * - * \return 0 on success, or a specific error code. - * - * \note When \p pk_type is #MBEDTLS_PK_RSASSA_PSS, - * see #PSA_ALG_RSA_PSS for a description of PSS options used. - * - * \note For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0. - * For ECDSA, md_alg may never be MBEDTLS_MD_NONE. - * - */ -int mbedtls_pk_sign_ext(mbedtls_pk_type_t pk_type, - mbedtls_pk_context *ctx, - mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, size_t *sig_len, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); -#endif /* MBEDTLS_PSA_CRYPTO_C */ - -/** - * \brief Restartable version of \c mbedtls_pk_sign() - * - * \note Performs the same job as \c mbedtls_pk_sign(), but can - * return early and restart according to the limit set with - * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC - * operations. For RSA, same as \c mbedtls_pk_sign(). - * - * \param ctx The PK context to use. It must have been set up - * with a private key. - * \param md_alg Hash algorithm used (see notes for mbedtls_pk_sign()) - * \param hash Hash of the message to sign - * \param hash_len Hash length - * \param sig Place to write the signature. - * It must have enough room for the signature. - * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. - * You may use a smaller buffer if it is large enough - * given the key type. - * \param sig_size The size of the \p sig buffer in bytes. - * \param sig_len On successful return, - * the number of bytes written to \p sig. - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * \param rs_ctx Restart context (NULL to disable restart) - * - * \return See \c mbedtls_pk_sign(). - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - */ -int mbedtls_pk_sign_restartable(mbedtls_pk_context *ctx, - mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, size_t *sig_len, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, - mbedtls_pk_restart_ctx *rs_ctx); - -/** - * \brief Decrypt message (including padding if relevant). - * - * \param ctx The PK context to use. It must have been set up - * with a private key. - * \param input Input to decrypt - * \param ilen Input size - * \param output Decrypted output - * \param olen Decrypted message length - * \param osize Size of the output buffer - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * - * \note For RSA keys, the default padding type is PKCS#1 v1.5. - * - * \return 0 on success, or a specific error code. - */ -int mbedtls_pk_decrypt(mbedtls_pk_context *ctx, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, size_t osize, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** - * \brief Encrypt message (including padding if relevant). - * - * \param ctx The PK context to use. It must have been set up. - * \param input Message to encrypt - * \param ilen Message size - * \param output Encrypted output - * \param olen Encrypted output length - * \param osize Size of the output buffer - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * - * \note \p f_rng is used for padding generation. - * - * \note For RSA keys, the default padding type is PKCS#1 v1.5. - * - * \return 0 on success, or a specific error code. - */ -int mbedtls_pk_encrypt(mbedtls_pk_context *ctx, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, size_t osize, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** - * \brief Check if a public-private pair of keys matches. - * - * \param pub Context holding a public key. - * \param prv Context holding a private (and public) key. - * \param f_rng RNG function, must not be \c NULL. - * \param p_rng RNG parameter - * - * \return \c 0 on success (keys were checked and match each other). - * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the keys could not - * be checked - in that case they may or may not match. - * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA if a context is invalid. - * \return Another non-zero value if the keys do not match. - */ -int mbedtls_pk_check_pair(const mbedtls_pk_context *pub, - const mbedtls_pk_context *prv, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Export debug information - * - * \param ctx The PK context to use. It must have been initialized. - * \param items Place to write debug items - * - * \return 0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA - */ -int mbedtls_pk_debug(const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items); - -/** - * \brief Access the type name - * - * \param ctx The PK context to use. It must have been initialized. - * - * \return Type name on success, or "invalid PK" - */ -const char *mbedtls_pk_get_name(const mbedtls_pk_context *ctx); - -/** - * \brief Get the key type - * - * \param ctx The PK context to use. It must have been initialized. - * - * \return Type on success. - * \return #MBEDTLS_PK_NONE for a context that has not been set up. - */ -mbedtls_pk_type_t mbedtls_pk_get_type(const mbedtls_pk_context *ctx); - -#if defined(MBEDTLS_RSA_C) -/** - * Quick access to an RSA context inside a PK context. - * - * \warning This function can only be used when the type of the context, as - * returned by mbedtls_pk_get_type(), is #MBEDTLS_PK_RSA. - * Ensuring that is the caller's responsibility. - * Alternatively, you can check whether this function returns NULL. - * - * \return The internal RSA context held by the PK context, or NULL. - */ -static inline mbedtls_rsa_context *mbedtls_pk_rsa(const mbedtls_pk_context pk) -{ - switch (mbedtls_pk_get_type(&pk)) { - case MBEDTLS_PK_RSA: - return (mbedtls_rsa_context *) (pk).MBEDTLS_PRIVATE(pk_ctx); - default: - return NULL; - } -} -#endif /* MBEDTLS_RSA_C */ - -#if defined(MBEDTLS_ECP_C) -/** - * Quick access to an EC context inside a PK context. - * - * \warning This function can only be used when the type of the context, as - * returned by mbedtls_pk_get_type(), is #MBEDTLS_PK_ECKEY, - * #MBEDTLS_PK_ECKEY_DH, or #MBEDTLS_PK_ECDSA. - * Ensuring that is the caller's responsibility. - * Alternatively, you can check whether this function returns NULL. - * - * \return The internal EC context held by the PK context, or NULL. - */ -static inline mbedtls_ecp_keypair *mbedtls_pk_ec(const mbedtls_pk_context pk) -{ - switch (mbedtls_pk_get_type(&pk)) { - case MBEDTLS_PK_ECKEY: - case MBEDTLS_PK_ECKEY_DH: - case MBEDTLS_PK_ECDSA: - return (mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); - default: - return NULL; - } -} -#endif /* MBEDTLS_ECP_C */ - -#if defined(MBEDTLS_PK_PARSE_C) -/** \ingroup pk_module */ -/** - * \brief Parse a private key in PEM or DER format - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param ctx The PK context to fill. It must have been initialized - * but not set up. - * \param key Input buffer to parse. - * The buffer must contain the input exactly, with no - * extra trailing material. For PEM, the buffer must - * contain a null-terminated string. - * \param keylen Size of \b key in bytes. - * For PEM data, this includes the terminating null byte, - * so \p keylen must be equal to `strlen(key) + 1`. - * \param pwd Optional password for decryption. - * Pass \c NULL if expecting a non-encrypted key. - * Pass a string of \p pwdlen bytes if expecting an encrypted - * key; a non-encrypted key will also be accepted. - * The empty password is not supported. - * \param pwdlen Size of the password in bytes. - * Ignored if \p pwd is \c NULL. - * \param f_rng RNG function, must not be \c NULL. Used for blinding. - * \param p_rng RNG parameter - * - * \note On entry, ctx must be empty, either freshly initialised - * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a - * specific key type, check the result with mbedtls_pk_can_do(). - * - * \note The key is also checked for correctness. - * - * \return 0 if successful, or a specific PK or PEM error code - */ -int mbedtls_pk_parse_key(mbedtls_pk_context *ctx, - const unsigned char *key, size_t keylen, - const unsigned char *pwd, size_t pwdlen, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** \ingroup pk_module */ -/** - * \brief Parse a public key in PEM or DER format - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param ctx The PK context to fill. It must have been initialized - * but not set up. - * \param key Input buffer to parse. - * The buffer must contain the input exactly, with no - * extra trailing material. For PEM, the buffer must - * contain a null-terminated string. - * \param keylen Size of \b key in bytes. - * For PEM data, this includes the terminating null byte, - * so \p keylen must be equal to `strlen(key) + 1`. - * - * \note On entry, ctx must be empty, either freshly initialised - * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a - * specific key type, check the result with mbedtls_pk_can_do(). - * - * \note For compressed points, see #MBEDTLS_ECP_PF_COMPRESSED for - * limitations. - * - * \note The key is also checked for correctness. - * - * \return 0 if successful, or a specific PK or PEM error code - */ -int mbedtls_pk_parse_public_key(mbedtls_pk_context *ctx, - const unsigned char *key, size_t keylen); - -#if defined(MBEDTLS_FS_IO) -/** \ingroup pk_module */ -/** - * \brief Load and parse a private key - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param ctx The PK context to fill. It must have been initialized - * but not set up. - * \param path filename to read the private key from - * \param password Optional password to decrypt the file. - * Pass \c NULL if expecting a non-encrypted key. - * Pass a null-terminated string if expecting an encrypted - * key; a non-encrypted key will also be accepted. - * The empty password is not supported. - * \param f_rng RNG function, must not be \c NULL. Used for blinding. - * \param p_rng RNG parameter - * - * \note On entry, ctx must be empty, either freshly initialised - * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a - * specific key type, check the result with mbedtls_pk_can_do(). - * - * \note The key is also checked for correctness. - * - * \return 0 if successful, or a specific PK or PEM error code - */ -int mbedtls_pk_parse_keyfile(mbedtls_pk_context *ctx, - const char *path, const char *password, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -/** \ingroup pk_module */ -/** - * \brief Load and parse a public key - * - * \param ctx The PK context to fill. It must have been initialized - * but not set up. - * \param path filename to read the public key from - * - * \note On entry, ctx must be empty, either freshly initialised - * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If - * you need a specific key type, check the result with - * mbedtls_pk_can_do(). - * - * \note The key is also checked for correctness. - * - * \return 0 if successful, or a specific PK or PEM error code - */ -int mbedtls_pk_parse_public_keyfile(mbedtls_pk_context *ctx, const char *path); -#endif /* MBEDTLS_FS_IO */ -#endif /* MBEDTLS_PK_PARSE_C */ - -#if defined(MBEDTLS_PK_WRITE_C) -/** - * \brief Write a private key to a PKCS#1 or SEC1 DER structure - * Note: data is written at the end of the buffer! Use the - * return value to determine where you should start - * using the buffer - * - * \param ctx PK context which must contain a valid private key. - * \param buf buffer to write to - * \param size size of the buffer - * - * \return length of data written if successful, or a specific - * error code - */ -int mbedtls_pk_write_key_der(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); - -/** - * \brief Write a public key to a SubjectPublicKeyInfo DER structure - * Note: data is written at the end of the buffer! Use the - * return value to determine where you should start - * using the buffer - * - * \param ctx PK context which must contain a valid public or private key. - * \param buf buffer to write to - * \param size size of the buffer - * - * \return length of data written if successful, or a specific - * error code - */ -int mbedtls_pk_write_pubkey_der(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); - -#if defined(MBEDTLS_PEM_WRITE_C) -/** - * \brief Write a public key to a PEM string - * - * \param ctx PK context which must contain a valid public or private key. - * \param buf Buffer to write to. The output includes a - * terminating null byte. - * \param size Size of the buffer in bytes. - * - * \return 0 if successful, or a specific error code - */ -int mbedtls_pk_write_pubkey_pem(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); - -/** - * \brief Write a private key to a PKCS#1 or SEC1 PEM string - * - * \param ctx PK context which must contain a valid private key. - * \param buf Buffer to write to. The output includes a - * terminating null byte. - * \param size Size of the buffer in bytes. - * - * \return 0 if successful, or a specific error code - */ -int mbedtls_pk_write_key_pem(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); -#endif /* MBEDTLS_PEM_WRITE_C */ -#endif /* MBEDTLS_PK_WRITE_C */ - -/* - * WARNING: Low-level functions. You probably do not want to use these unless - * you are certain you do ;) - */ - -#if defined(MBEDTLS_PK_PARSE_C) -/** - * \brief Parse a SubjectPublicKeyInfo DER structure - * - * \param p the position in the ASN.1 data - * \param end end of the buffer - * \param pk The PK context to fill. It must have been initialized - * but not set up. - * - * \return 0 if successful, or a specific PK error code - */ -int mbedtls_pk_parse_subpubkey(unsigned char **p, const unsigned char *end, - mbedtls_pk_context *pk); -#endif /* MBEDTLS_PK_PARSE_C */ - -#if defined(MBEDTLS_PK_WRITE_C) -/** - * \brief Write a subjectPublicKey to ASN.1 data - * Note: function works backwards in data buffer - * - * \param p reference to current position pointer - * \param start start of the buffer (for bounds-checking) - * \param key PK context which must contain a valid public or private key. - * - * \return the length written or a negative error code - */ -int mbedtls_pk_write_pubkey(unsigned char **p, unsigned char *start, - const mbedtls_pk_context *key); -#endif /* MBEDTLS_PK_WRITE_C */ - -/* - * Internal module functions. You probably do not want to use these unless you - * know you do. - */ -#if defined(MBEDTLS_FS_IO) -int mbedtls_pk_load_file(const char *path, unsigned char **buf, size_t *n); -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * \brief Turn an EC or RSA key into an opaque one. - * - * \warning This is a temporary utility function for tests. It might - * change or be removed at any time without notice. - * - * \param pk Input: the EC or RSA key to import to a PSA key. - * Output: a PK context wrapping that PSA key. - * \param key Output: a PSA key identifier. - * It's the caller's responsibility to call - * psa_destroy_key() on that key identifier after calling - * mbedtls_pk_free() on the PK context. - * \param alg The algorithm to allow for use with that key. - * \param usage The usage to allow for use with that key. - * \param alg2 The secondary algorithm to allow for use with that key. - * - * \return \c 0 if successful. - * \return An Mbed TLS error code otherwise. - */ -int mbedtls_pk_wrap_as_opaque(mbedtls_pk_context *pk, - mbedtls_svc_key_id_t *key, - psa_algorithm_t alg, - psa_key_usage_t usage, - psa_algorithm_t alg2); -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_PK_H */ +/** + * \file pk.h + * + * \brief Public Key abstraction layer + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PK_H +#define MBEDTLS_PK_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/md.h" + +#if defined(MBEDTLS_RSA_C) +#include "mbedtls/rsa.h" +#endif + +#if defined(MBEDTLS_ECP_C) +#include "mbedtls/ecp.h" +#endif + +#if defined(MBEDTLS_ECDSA_C) +#include "mbedtls/ecdsa.h" +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_PSA_CRYPTO_C) +#include "psa/crypto.h" +#endif + +/** Memory allocation failed. */ +#define MBEDTLS_ERR_PK_ALLOC_FAILED -0x3F80 +/** Type mismatch, eg attempt to encrypt with an ECDSA key */ +#define MBEDTLS_ERR_PK_TYPE_MISMATCH -0x3F00 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_PK_BAD_INPUT_DATA -0x3E80 +/** Read/write of file failed. */ +#define MBEDTLS_ERR_PK_FILE_IO_ERROR -0x3E00 +/** Unsupported key version */ +#define MBEDTLS_ERR_PK_KEY_INVALID_VERSION -0x3D80 +/** Invalid key tag or value. */ +#define MBEDTLS_ERR_PK_KEY_INVALID_FORMAT -0x3D00 +/** Key algorithm is unsupported (only RSA and EC are supported). */ +#define MBEDTLS_ERR_PK_UNKNOWN_PK_ALG -0x3C80 +/** Private key password can't be empty. */ +#define MBEDTLS_ERR_PK_PASSWORD_REQUIRED -0x3C00 +/** Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PK_PASSWORD_MISMATCH -0x3B80 +/** The pubkey tag or value is invalid (only RSA and EC are supported). */ +#define MBEDTLS_ERR_PK_INVALID_PUBKEY -0x3B00 +/** The algorithm tag or value is invalid. */ +#define MBEDTLS_ERR_PK_INVALID_ALG -0x3A80 +/** Elliptic curve is unsupported (only NIST curves are supported). */ +#define MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE -0x3A00 +/** Unavailable feature, e.g. RSA disabled for RSA key. */ +#define MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE -0x3980 +/** The buffer contains a valid signature followed by more data. */ +#define MBEDTLS_ERR_PK_SIG_LEN_MISMATCH -0x3900 +/** The output buffer is too small. */ +#define MBEDTLS_ERR_PK_BUFFER_TOO_SMALL -0x3880 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Public key types + */ +typedef enum { + MBEDTLS_PK_NONE=0, + MBEDTLS_PK_RSA, + MBEDTLS_PK_ECKEY, + MBEDTLS_PK_ECKEY_DH, + MBEDTLS_PK_ECDSA, + MBEDTLS_PK_RSA_ALT, + MBEDTLS_PK_RSASSA_PSS, + MBEDTLS_PK_OPAQUE, +} mbedtls_pk_type_t; + +/** + * \brief Options for RSASSA-PSS signature verification. + * See \c mbedtls_rsa_rsassa_pss_verify_ext() + */ +typedef struct mbedtls_pk_rsassa_pss_options { + /** The digest to use for MGF1 in PSS. + * + * \note When #MBEDTLS_USE_PSA_CRYPTO is enabled and #MBEDTLS_RSA_C is + * disabled, this must be equal to the \c md_alg argument passed + * to mbedtls_pk_verify_ext(). In a future version of the library, + * this constraint may apply whenever #MBEDTLS_USE_PSA_CRYPTO is + * enabled regardless of the status of #MBEDTLS_RSA_C. + */ + mbedtls_md_type_t mgf1_hash_id; + + /** The expected length of the salt, in bytes. This may be + * #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length. + * + * \note When #MBEDTLS_USE_PSA_CRYPTO is enabled, only + * #MBEDTLS_RSA_SALT_LEN_ANY is valid. Any other value may be + * ignored (allowing any salt length). + */ + int expected_salt_len; + +} mbedtls_pk_rsassa_pss_options; + +/** + * \brief Maximum size of a signature made by mbedtls_pk_sign(). + */ +/* We need to set MBEDTLS_PK_SIGNATURE_MAX_SIZE to the maximum signature + * size among the supported signature types. Do it by starting at 0, + * then incrementally increasing to be large enough for each supported + * signature mechanism. + * + * The resulting value can be 0, for example if MBEDTLS_ECDH_C is enabled + * (which allows the pk module to be included) but neither MBEDTLS_ECDSA_C + * nor MBEDTLS_RSA_C nor any opaque signature mechanism (PSA or RSA_ALT). + */ +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE 0 + +#if (defined(MBEDTLS_RSA_C) || defined(MBEDTLS_PK_RSA_ALT_SUPPORT)) && \ + MBEDTLS_MPI_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* For RSA, the signature can be as large as the bignum module allows. + * For RSA_ALT, the signature size is not necessarily tied to what the + * bignum module can do, but in the absence of any specific setting, + * we use that (rsa_alt_sign_wrap in library/pk_wrap.h will check). */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_MPI_MAX_SIZE +#endif + +#if defined(MBEDTLS_ECDSA_C) && \ + MBEDTLS_ECDSA_MAX_LEN > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* For ECDSA, the ecdsa module exports a constant for the maximum + * signature size. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_ECDSA_MAX_LEN +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if PSA_SIGNATURE_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* PSA_SIGNATURE_MAX_SIZE is the maximum size of a signature made + * through the PSA API in the PSA representation. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE PSA_SIGNATURE_MAX_SIZE +#endif + +#if PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11 > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* The Mbed TLS representation is different for ECDSA signatures: + * PSA uses the raw concatenation of r and s, + * whereas Mbed TLS uses the ASN.1 representation (SEQUENCE of two INTEGERs). + * Add the overhead of ASN.1: up to (1+2) + 2 * (1+2+1) for the + * types, lengths (represented by up to 2 bytes), and potential leading + * zeros of the INTEGERs and the SEQUENCE. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE (PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11) +#endif +#endif /* defined(MBEDTLS_USE_PSA_CRYPTO) */ + +/* Internal helper to define which fields in the pk_context structure below + * should be used for EC keys: legacy ecp_keypair or the raw (PSA friendly) + * format. It should be noted that this only affects how data is stored, not + * which functions are used for various operations. The overall picture looks + * like this: + * - if USE_PSA is not defined and ECP_C is defined then use ecp_keypair data + * structure and legacy functions + * - if USE_PSA is defined and + * - if ECP_C then use ecp_keypair structure, convert data to a PSA friendly + * format and use PSA functions + * - if !ECP_C then use new raw data and PSA functions directly. + * + * The main reason for the "intermediate" (USE_PSA + ECP_C) above is that as long + * as ECP_C is defined mbedtls_pk_ec() gives the user a read/write access to the + * ecp_keypair structure inside the pk_context so they can modify it using + * ECP functions which are not under PK module's control. + */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) && defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) && \ + !defined(MBEDTLS_ECP_C) +#define MBEDTLS_PK_USE_PSA_EC_DATA +#endif + +/* Helper symbol to state that the PK module has support for EC keys. This + * can either be provided through the legacy ECP solution or through the + * PSA friendly MBEDTLS_PK_USE_PSA_EC_DATA. */ +#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) || defined(MBEDTLS_ECP_C) +#define MBEDTLS_PK_HAVE_ECC_KEYS +#endif /* MBEDTLS_PK_USE_PSA_EC_DATA || MBEDTLS_ECP_C */ + +/** + * \brief Types for interfacing with the debug module + */ +typedef enum { + MBEDTLS_PK_DEBUG_NONE = 0, + MBEDTLS_PK_DEBUG_MPI, + MBEDTLS_PK_DEBUG_ECP, + MBEDTLS_PK_DEBUG_PSA_EC, +} mbedtls_pk_debug_type; + +/** + * \brief Item to send to the debug module + */ +typedef struct mbedtls_pk_debug_item { + mbedtls_pk_debug_type MBEDTLS_PRIVATE(type); + const char *MBEDTLS_PRIVATE(name); + void *MBEDTLS_PRIVATE(value); +} mbedtls_pk_debug_item; + +/** Maximum number of item send for debugging, plus 1 */ +#define MBEDTLS_PK_DEBUG_MAX_ITEMS 3 + +/** + * \brief Public key information and operations + * + * \note The library does not support custom pk info structures, + * only built-in structures returned by + * mbedtls_cipher_info_from_type(). + */ +typedef struct mbedtls_pk_info_t mbedtls_pk_info_t; + +#define MBEDTLS_PK_MAX_EC_PUBKEY_RAW_LEN \ + PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) +/** + * \brief Public key container + */ +typedef struct mbedtls_pk_context { + const mbedtls_pk_info_t *MBEDTLS_PRIVATE(pk_info); /**< Public key information */ + void *MBEDTLS_PRIVATE(pk_ctx); /**< Underlying public key context */ + /* The following field is used to store the ID of a private key in the + * following cases: + * - opaque key when MBEDTLS_PSA_CRYPTO_C is defined + * - normal key when MBEDTLS_PK_USE_PSA_EC_DATA is defined. In this case: + * - the pk_ctx above is not not used to store the private key anymore. + * Actually that field not populated at all in this case because also + * the public key will be stored in raw format as explained below + * - this ID is used for all private key operations (ex: sign, check + * key pair, key write, etc) using PSA functions + * + * Note: this private key storing solution only affects EC keys, not the + * other ones. The latters still use the pk_ctx to store their own + * context. + * + * Note: this priv_id is guarded by MBEDTLS_PSA_CRYPTO_C and not by + * MBEDTLS_PK_USE_PSA_EC_DATA (as the public counterpart below) because, + * when working with opaque keys, it can be used also in + * mbedtls_pk_sign_ext for RSA keys. */ +#if defined(MBEDTLS_PSA_CRYPTO_C) + mbedtls_svc_key_id_t MBEDTLS_PRIVATE(priv_id); /**< Key ID for opaque keys */ +#else + uint32_t MBEDTLS_PRIVATE(priv_id); /**< Key ID for opaque keys */ +#endif /* MBEDTLS_PSA_CRYPTO_C */ + /* The following fields are meant for storing the public key in raw format + * which is handy for: + * - easily importing it into the PSA context + * - reducing the ECP module dependencies in the PK one. + * + * When MBEDTLS_PK_USE_PSA_EC_DATA is enabled: + * - the pk_ctx above is not used anymore for storing the public key + * inside the ecp_keypair structure + * - the following fields are used for all public key operations: signature + * verify, key pair check and key write. + * Of course, when MBEDTLS_PK_USE_PSA_EC_DATA is not enabled, the legacy + * ecp_keypair structure is used for storing the public key and performing + * all the operations. + * + * Note: This new public key storing solution only works for EC keys, not + * other ones. The latters still use pk_ctx to store their own + * context. + */ + uint8_t MBEDTLS_PRIVATE(pub_raw)[66 * 2 + 1]; /**< Raw public key */ + size_t MBEDTLS_PRIVATE(pub_raw_len); /**< Valid bytes in "pub_raw" */ +#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) + psa_ecc_family_t MBEDTLS_PRIVATE(ec_family); /**< EC family of pk */ +#else + uint8_t MBEDTLS_PRIVATE(ec_family); /**< EC family of pk */ +#endif /* MBEDTLS_PK_USE_PSA_EC_DATA */ + size_t MBEDTLS_PRIVATE(ec_bits); /**< Curve's bits of pk */ +} mbedtls_pk_context; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Context for resuming operations + */ +typedef struct { + const mbedtls_pk_info_t *MBEDTLS_PRIVATE(pk_info); /**< Public key information */ + void *MBEDTLS_PRIVATE(rs_ctx); /**< Underlying restart context */ +} mbedtls_pk_restart_ctx; +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_pk_restart_ctx; +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/** + * \brief Types for RSA-alt abstraction + */ +typedef int (*mbedtls_pk_rsa_alt_decrypt_func)(void *ctx, size_t *olen, + const unsigned char *input, unsigned char *output, + size_t output_max_len); +typedef int (*mbedtls_pk_rsa_alt_sign_func)(void *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, unsigned int hashlen, + const unsigned char *hash, unsigned char *sig); +typedef size_t (*mbedtls_pk_rsa_alt_key_len_func)(void *ctx); +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +/** + * \brief Return information associated with the given PK type + * + * \param pk_type PK type to search for. + * + * \return The PK info associated with the type or NULL if not found. + */ +const mbedtls_pk_info_t *mbedtls_pk_info_from_type(mbedtls_pk_type_t pk_type); + +/** + * \brief Initialize a #mbedtls_pk_context (as NONE). + * + * \param ctx The context to initialize. + * This must not be \c NULL. + */ +void mbedtls_pk_init(mbedtls_pk_context *ctx); + +/** + * \brief Free the components of a #mbedtls_pk_context. + * + * \param ctx The context to clear. It must have been initialized. + * If this is \c NULL, this function does nothing. + * + * \note For contexts that have been set up with + * mbedtls_pk_setup_opaque(), this does not free the underlying + * PSA key and you still need to call psa_destroy_key() + * independently if you want to destroy that key. + */ +void mbedtls_pk_free(mbedtls_pk_context *ctx); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context + * + * \param ctx The context to initialize. + * This must not be \c NULL. + */ +void mbedtls_pk_restart_init(mbedtls_pk_restart_ctx *ctx); + +/** + * \brief Free the components of a restart context + * + * \param ctx The context to clear. It must have been initialized. + * If this is \c NULL, this function does nothing. + */ +void mbedtls_pk_restart_free(mbedtls_pk_restart_ctx *ctx); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/** + * \brief Initialize a PK context with the information given + * and allocates the type-specific PK subcontext. + * + * \param ctx Context to initialize. It must not have been set + * up yet (type #MBEDTLS_PK_NONE). + * \param info Information to use + * + * \return 0 on success, + * MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input, + * MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. + * + * \note For contexts holding an RSA-alt key, use + * \c mbedtls_pk_setup_rsa_alt() instead. + */ +int mbedtls_pk_setup(mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info); + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * \brief Initialize a PK context to wrap a PSA key. + * + * \note This function replaces mbedtls_pk_setup() for contexts + * that wrap a (possibly opaque) PSA key instead of + * storing and manipulating the key material directly. + * + * \param ctx The context to initialize. It must be empty (type NONE). + * \param key The PSA key to wrap, which must hold an ECC or RSA key + * pair (see notes below). + * + * \note The wrapped key must remain valid as long as the + * wrapping PK context is in use, that is at least between + * the point this function is called and the point + * mbedtls_pk_free() is called on this context. The wrapped + * key might then be independently used or destroyed. + * + * \note This function is currently only available for ECC or RSA + * key pairs (that is, keys containing private key material). + * Support for other key types may be added later. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input + * (context already used, invalid key identifier). + * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the key is not an + * ECC key pair. + * \return #MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. + */ +int mbedtls_pk_setup_opaque(mbedtls_pk_context *ctx, + const mbedtls_svc_key_id_t key); +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/** + * \brief Initialize an RSA-alt context + * + * \param ctx Context to initialize. It must not have been set + * up yet (type #MBEDTLS_PK_NONE). + * \param key RSA key pointer + * \param decrypt_func Decryption function + * \param sign_func Signing function + * \param key_len_func Function returning key length in bytes + * + * \return 0 on success, or MBEDTLS_ERR_PK_BAD_INPUT_DATA if the + * context wasn't already initialized as RSA_ALT. + * + * \note This function replaces \c mbedtls_pk_setup() for RSA-alt. + */ +int mbedtls_pk_setup_rsa_alt(mbedtls_pk_context *ctx, void *key, + mbedtls_pk_rsa_alt_decrypt_func decrypt_func, + mbedtls_pk_rsa_alt_sign_func sign_func, + mbedtls_pk_rsa_alt_key_len_func key_len_func); +#endif /* MBEDTLS_PK_RSA_ALT_SUPPORT */ + +/** + * \brief Get the size in bits of the underlying key + * + * \param ctx The context to query. It must have been initialized. + * + * \return Key size in bits, or 0 on error + */ +size_t mbedtls_pk_get_bitlen(const mbedtls_pk_context *ctx); + +/** + * \brief Get the length in bytes of the underlying key + * + * \param ctx The context to query. It must have been initialized. + * + * \return Key length in bytes, or 0 on error + */ +static inline size_t mbedtls_pk_get_len(const mbedtls_pk_context *ctx) +{ + return (mbedtls_pk_get_bitlen(ctx) + 7) / 8; +} + +/** + * \brief Tell if a context can do the operation given by type + * + * \param ctx The context to query. It must have been initialized. + * \param type The desired type. + * + * \return 1 if the context can do operations on the given type. + * \return 0 if the context cannot do the operations on the given + * type. This is always the case for a context that has + * been initialized but not set up, or that has been + * cleared with mbedtls_pk_free(). + */ +int mbedtls_pk_can_do(const mbedtls_pk_context *ctx, mbedtls_pk_type_t type); + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * \brief Tell if context can do the operation given by PSA algorithm + * + * \param ctx The context to query. It must have been initialized. + * \param alg PSA algorithm to check against, the following are allowed: + * PSA_ALG_RSA_PKCS1V15_SIGN(hash), + * PSA_ALG_RSA_PSS(hash), + * PSA_ALG_RSA_PKCS1V15_CRYPT, + * PSA_ALG_ECDSA(hash), + * PSA_ALG_ECDH, where hash is a specific hash. + * \param usage PSA usage flag to check against, must be composed of: + * PSA_KEY_USAGE_SIGN_HASH + * PSA_KEY_USAGE_DECRYPT + * PSA_KEY_USAGE_DERIVE. + * Context key must match all passed usage flags. + * + * \warning Since the set of allowed algorithms and usage flags may be + * expanded in the future, the return value \c 0 should not + * be taken in account for non-allowed algorithms and usage + * flags. + * + * \return 1 if the context can do operations on the given type. + * \return 0 if the context cannot do the operations on the given + * type, for non-allowed algorithms and usage flags, or + * for a context that has been initialized but not set up + * or that has been cleared with mbedtls_pk_free(). + */ +int mbedtls_pk_can_do_ext(const mbedtls_pk_context *ctx, psa_algorithm_t alg, + psa_key_usage_t usage); +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/** + * \brief Verify signature (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used. + * This can be #MBEDTLS_MD_NONE if the signature algorithm + * does not rely on a hash algorithm (non-deterministic + * ECDSA, RSA PKCS#1 v1.5). + * For PKCS#1 v1.5, if \p md_alg is #MBEDTLS_MD_NONE, then + * \p hash is the DigestInfo structure used by RFC 8017 + * §9.2 steps 3–6. If \p md_alg is a valid hash + * algorithm then \p hash is the digest itself, and this + * function calculates the DigestInfo encoding internally. + * \param hash Hash of the message to sign + * \param hash_len Hash length + * \param sig Signature to verify + * \param sig_len Signature length + * + * \return 0 on success (signature is valid), + * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig but its length is less than \p sig_len, + * or a specific error code. + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * Use \c mbedtls_pk_verify_ext( MBEDTLS_PK_RSASSA_PSS, ... ) + * to verify RSASSA_PSS signatures. + */ +int mbedtls_pk_verify(mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len); + +/** + * \brief Restartable version of \c mbedtls_pk_verify() + * + * \note Performs the same job as \c mbedtls_pk_verify(), but can + * return early and restart according to the limit set with + * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC + * operations. For RSA, same as \c mbedtls_pk_verify(). + * + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Signature to verify + * \param sig_len Signature length + * \param rs_ctx Restart context (NULL to disable restart) + * + * \return See \c mbedtls_pk_verify(), or + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_pk_verify_restartable(mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + mbedtls_pk_restart_ctx *rs_ctx); + +/** + * \brief Verify signature, with options. + * (Includes verification of the padding depending on type.) + * + * \param type Signature type (inc. possible padding type) to verify + * \param options Pointer to type-specific options, or NULL + * \param ctx The PK context to use. It must have been set up. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length or 0 (see notes) + * \param sig Signature to verify + * \param sig_len Signature length + * + * \return 0 on success (signature is valid), + * #MBEDTLS_ERR_PK_TYPE_MISMATCH if the PK context can't be + * used for this type of signatures, + * #MBEDTLS_ERR_PK_SIG_LEN_MISMATCH if there is a valid + * signature in \p sig but its length is less than \p sig_len, + * or a specific error code. + * + * \note If hash_len is 0, then the length associated with md_alg + * is used instead, or an error returned if it is invalid. + * + * \note md_alg may be MBEDTLS_MD_NONE, only if hash_len != 0 + * + * \note If type is MBEDTLS_PK_RSASSA_PSS, then options must point + * to a mbedtls_pk_rsassa_pss_options structure, + * otherwise it must be NULL. Note that if + * #MBEDTLS_USE_PSA_CRYPTO is defined, the salt length is not + * verified as PSA_ALG_RSA_PSS_ANY_SALT is used. + */ +int mbedtls_pk_verify_ext(mbedtls_pk_type_t type, const void *options, + mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len); + +/** + * \brief Make signature, including padding if relevant. + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length + * \param sig Place to write the signature. + * It must have enough room for the signature. + * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. + * You may use a smaller buffer if it is large enough + * given the key type. + * \param sig_size The size of the \p sig buffer in bytes. + * \param sig_len On successful return, + * the number of bytes written to \p sig. + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * + * \return 0 on success, or a specific error code. + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * There is no interface in the PK module to make RSASSA-PSS + * signatures yet. + * + * \note For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0. + * For ECDSA, md_alg may never be MBEDTLS_MD_NONE. + */ +int mbedtls_pk_sign(mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +#if defined(MBEDTLS_PSA_CRYPTO_C) +/** + * \brief Make signature given a signature type. + * + * \param pk_type Signature type. + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param md_alg Hash algorithm used (see notes) + * \param hash Hash of the message to sign + * \param hash_len Hash length + * \param sig Place to write the signature. + * It must have enough room for the signature. + * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. + * You may use a smaller buffer if it is large enough + * given the key type. + * \param sig_size The size of the \p sig buffer in bytes. + * \param sig_len On successful return, + * the number of bytes written to \p sig. + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * + * \return 0 on success, or a specific error code. + * + * \note When \p pk_type is #MBEDTLS_PK_RSASSA_PSS, + * see #PSA_ALG_RSA_PSS for a description of PSS options used. + * + * \note For RSA, md_alg may be MBEDTLS_MD_NONE if hash_len != 0. + * For ECDSA, md_alg may never be MBEDTLS_MD_NONE. + * + */ +int mbedtls_pk_sign_ext(mbedtls_pk_type_t pk_type, + mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +/** + * \brief Restartable version of \c mbedtls_pk_sign() + * + * \note Performs the same job as \c mbedtls_pk_sign(), but can + * return early and restart according to the limit set with + * \c mbedtls_ecp_set_max_ops() to reduce blocking for ECC + * operations. For RSA, same as \c mbedtls_pk_sign(). + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param md_alg Hash algorithm used (see notes for mbedtls_pk_sign()) + * \param hash Hash of the message to sign + * \param hash_len Hash length + * \param sig Place to write the signature. + * It must have enough room for the signature. + * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. + * You may use a smaller buffer if it is large enough + * given the key type. + * \param sig_size The size of the \p sig buffer in bytes. + * \param sig_len On successful return, + * the number of bytes written to \p sig. + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * \param rs_ctx Restart context (NULL to disable restart) + * + * \return See \c mbedtls_pk_sign(). + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_pk_sign_restartable(mbedtls_pk_context *ctx, + mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_pk_restart_ctx *rs_ctx); + +/** + * \brief Decrypt message (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up + * with a private key. + * \param input Input to decrypt + * \param ilen Input size + * \param output Decrypted output + * \param olen Decrypted message length + * \param osize Size of the output buffer + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * + * \return 0 on success, or a specific error code. + */ +int mbedtls_pk_decrypt(mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** + * \brief Encrypt message (including padding if relevant). + * + * \param ctx The PK context to use. It must have been set up. + * \param input Message to encrypt + * \param ilen Message size + * \param output Encrypted output + * \param olen Encrypted output length + * \param osize Size of the output buffer + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * + * \note \p f_rng is used for padding generation. + * + * \note For RSA keys, the default padding type is PKCS#1 v1.5. + * + * \return 0 on success, or a specific error code. + */ +int mbedtls_pk_encrypt(mbedtls_pk_context *ctx, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** + * \brief Check if a public-private pair of keys matches. + * + * \param pub Context holding a public key. + * \param prv Context holding a private (and public) key. + * \param f_rng RNG function, must not be \c NULL. + * \param p_rng RNG parameter + * + * \return \c 0 on success (keys were checked and match each other). + * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the keys could not + * be checked - in that case they may or may not match. + * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA if a context is invalid. + * \return Another non-zero value if the keys do not match. + */ +int mbedtls_pk_check_pair(const mbedtls_pk_context *pub, + const mbedtls_pk_context *prv, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Export debug information + * + * \param ctx The PK context to use. It must have been initialized. + * \param items Place to write debug items + * + * \return 0 on success or MBEDTLS_ERR_PK_BAD_INPUT_DATA + */ +int mbedtls_pk_debug(const mbedtls_pk_context *ctx, mbedtls_pk_debug_item *items); + +/** + * \brief Access the type name + * + * \param ctx The PK context to use. It must have been initialized. + * + * \return Type name on success, or "invalid PK" + */ +const char *mbedtls_pk_get_name(const mbedtls_pk_context *ctx); + +/** + * \brief Get the key type + * + * \param ctx The PK context to use. It must have been initialized. + * + * \return Type on success. + * \return #MBEDTLS_PK_NONE for a context that has not been set up. + */ +mbedtls_pk_type_t mbedtls_pk_get_type(const mbedtls_pk_context *ctx); + +#if defined(MBEDTLS_RSA_C) +/** + * Quick access to an RSA context inside a PK context. + * + * \warning This function can only be used when the type of the context, as + * returned by mbedtls_pk_get_type(), is #MBEDTLS_PK_RSA. + * Ensuring that is the caller's responsibility. + * Alternatively, you can check whether this function returns NULL. + * + * \return The internal RSA context held by the PK context, or NULL. + */ +static inline mbedtls_rsa_context *mbedtls_pk_rsa(const mbedtls_pk_context pk) +{ + switch (mbedtls_pk_get_type(&pk)) { + case MBEDTLS_PK_RSA: + return (mbedtls_rsa_context *) (pk).MBEDTLS_PRIVATE(pk_ctx); + default: + return NULL; + } +} +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_ECP_C) +/** + * Quick access to an EC context inside a PK context. + * + * \warning This function can only be used when the type of the context, as + * returned by mbedtls_pk_get_type(), is #MBEDTLS_PK_ECKEY, + * #MBEDTLS_PK_ECKEY_DH, or #MBEDTLS_PK_ECDSA. + * Ensuring that is the caller's responsibility. + * Alternatively, you can check whether this function returns NULL. + * + * \return The internal EC context held by the PK context, or NULL. + */ +static inline mbedtls_ecp_keypair *mbedtls_pk_ec(const mbedtls_pk_context pk) +{ + switch (mbedtls_pk_get_type(&pk)) { + case MBEDTLS_PK_ECKEY: + case MBEDTLS_PK_ECKEY_DH: + case MBEDTLS_PK_ECDSA: + return (mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); + default: + return NULL; + } +} +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_PK_PARSE_C) +/** \ingroup pk_module */ +/** + * \brief Parse a private key in PEM or DER format + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param key Input buffer to parse. + * The buffer must contain the input exactly, with no + * extra trailing material. For PEM, the buffer must + * contain a null-terminated string. + * \param keylen Size of \b key in bytes. + * For PEM data, this includes the terminating null byte, + * so \p keylen must be equal to `strlen(key) + 1`. + * \param pwd Optional password for decryption. + * Pass \c NULL if expecting a non-encrypted key. + * Pass a string of \p pwdlen bytes if expecting an encrypted + * key; a non-encrypted key will also be accepted. + * The empty password is not supported. + * \param pwdlen Size of the password in bytes. + * Ignored if \p pwd is \c NULL. + * \param f_rng RNG function, must not be \c NULL. Used for blinding. + * \param p_rng RNG parameter + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_key(mbedtls_pk_context *ctx, + const unsigned char *key, size_t keylen, + const unsigned char *pwd, size_t pwdlen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** \ingroup pk_module */ +/** + * \brief Parse a public key in PEM or DER format + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param key Input buffer to parse. + * The buffer must contain the input exactly, with no + * extra trailing material. For PEM, the buffer must + * contain a null-terminated string. + * \param keylen Size of \b key in bytes. + * For PEM data, this includes the terminating null byte, + * so \p keylen must be equal to `strlen(key) + 1`. + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note For compressed points, see #MBEDTLS_ECP_PF_COMPRESSED for + * limitations. + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_public_key(mbedtls_pk_context *ctx, + const unsigned char *key, size_t keylen); + +#if defined(MBEDTLS_FS_IO) +/** \ingroup pk_module */ +/** + * \brief Load and parse a private key + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param path filename to read the private key from + * \param password Optional password to decrypt the file. + * Pass \c NULL if expecting a non-encrypted key. + * Pass a null-terminated string if expecting an encrypted + * key; a non-encrypted key will also be accepted. + * The empty password is not supported. + * \param f_rng RNG function, must not be \c NULL. Used for blinding. + * \param p_rng RNG parameter + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If you need a + * specific key type, check the result with mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_keyfile(mbedtls_pk_context *ctx, + const char *path, const char *password, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +/** \ingroup pk_module */ +/** + * \brief Load and parse a public key + * + * \param ctx The PK context to fill. It must have been initialized + * but not set up. + * \param path filename to read the public key from + * + * \note On entry, ctx must be empty, either freshly initialised + * with mbedtls_pk_init() or reset with mbedtls_pk_free(). If + * you need a specific key type, check the result with + * mbedtls_pk_can_do(). + * + * \note The key is also checked for correctness. + * + * \return 0 if successful, or a specific PK or PEM error code + */ +int mbedtls_pk_parse_public_keyfile(mbedtls_pk_context *ctx, const char *path); +#endif /* MBEDTLS_FS_IO */ +#endif /* MBEDTLS_PK_PARSE_C */ + +#if defined(MBEDTLS_PK_WRITE_C) +/** + * \brief Write a private key to a PKCS#1 or SEC1 DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx PK context which must contain a valid private key. + * \param buf buffer to write to + * \param size size of the buffer + * + * \return length of data written if successful, or a specific + * error code + */ +int mbedtls_pk_write_key_der(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); + +/** + * \brief Write a public key to a SubjectPublicKeyInfo DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx PK context which must contain a valid public or private key. + * \param buf buffer to write to + * \param size size of the buffer + * + * \return length of data written if successful, or a specific + * error code + */ +int mbedtls_pk_write_pubkey_der(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a public key to a PEM string + * + * \param ctx PK context which must contain a valid public or private key. + * \param buf Buffer to write to. The output includes a + * terminating null byte. + * \param size Size of the buffer in bytes. + * + * \return 0 if successful, or a specific error code + */ +int mbedtls_pk_write_pubkey_pem(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); + +/** + * \brief Write a private key to a PKCS#1 or SEC1 PEM string + * + * \param ctx PK context which must contain a valid private key. + * \param buf Buffer to write to. The output includes a + * terminating null byte. + * \param size Size of the buffer in bytes. + * + * \return 0 if successful, or a specific error code + */ +int mbedtls_pk_write_key_pem(const mbedtls_pk_context *ctx, unsigned char *buf, size_t size); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_PK_WRITE_C */ + +/* + * WARNING: Low-level functions. You probably do not want to use these unless + * you are certain you do ;) + */ + +#if defined(MBEDTLS_PK_PARSE_C) +/** + * \brief Parse a SubjectPublicKeyInfo DER structure + * + * \param p the position in the ASN.1 data + * \param end end of the buffer + * \param pk The PK context to fill. It must have been initialized + * but not set up. + * + * \return 0 if successful, or a specific PK error code + */ +int mbedtls_pk_parse_subpubkey(unsigned char **p, const unsigned char *end, + mbedtls_pk_context *pk); +#endif /* MBEDTLS_PK_PARSE_C */ + +#if defined(MBEDTLS_PK_WRITE_C) +/** + * \brief Write a subjectPublicKey to ASN.1 data + * Note: function works backwards in data buffer + * + * \param p reference to current position pointer + * \param start start of the buffer (for bounds-checking) + * \param key PK context which must contain a valid public or private key. + * + * \return the length written or a negative error code + */ +int mbedtls_pk_write_pubkey(unsigned char **p, unsigned char *start, + const mbedtls_pk_context *key); +#endif /* MBEDTLS_PK_WRITE_C */ + +/* + * Internal module functions. You probably do not want to use these unless you + * know you do. + */ +#if defined(MBEDTLS_FS_IO) +int mbedtls_pk_load_file(const char *path, unsigned char **buf, size_t *n); +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * \brief Turn an EC or RSA key into an opaque one. + * + * \warning This is a temporary utility function for tests. It might + * change or be removed at any time without notice. + * + * \param pk Input: the EC or RSA key to import to a PSA key. + * Output: a PK context wrapping that PSA key. + * \param key Output: a PSA key identifier. + * It's the caller's responsibility to call + * psa_destroy_key() on that key identifier after calling + * mbedtls_pk_free() on the PK context. + * \param alg The algorithm to allow for use with that key. + * \param usage The usage to allow for use with that key. + * \param alg2 The secondary algorithm to allow for use with that key. + * + * \return \c 0 if successful. + * \return An Mbed TLS error code otherwise. + */ +int mbedtls_pk_wrap_as_opaque(mbedtls_pk_context *pk, + mbedtls_svc_key_id_t *key, + psa_algorithm_t alg, + psa_key_usage_t usage, + psa_algorithm_t alg2); +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_PK_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs12.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs12.h index ba1a2ed..bfc7ba9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs12.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs12.h @@ -1,198 +1,198 @@ -/** - * \file pkcs12.h - * - * \brief PKCS#12 Personal Information Exchange Syntax - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PKCS12_H -#define MBEDTLS_PKCS12_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/md.h" -#include "mbedtls/cipher.h" -#include "mbedtls/asn1.h" - -#include - -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA -0x1F80 -/** Feature not available, e.g. unsupported encryption scheme. */ -#define MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE -0x1F00 -/** PBE ASN.1 data not as expected. */ -#define MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT -0x1E80 -/** Given private key password does not allow for correct decryption. */ -#define MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH -0x1E00 - -#define MBEDTLS_PKCS12_DERIVE_KEY 1 /**< encryption/decryption key */ -#define MBEDTLS_PKCS12_DERIVE_IV 2 /**< initialization vector */ -#define MBEDTLS_PKCS12_DERIVE_MAC_KEY 3 /**< integrity / MAC key */ - -#define MBEDTLS_PKCS12_PBE_DECRYPT 0 -#define MBEDTLS_PKCS12_PBE_ENCRYPT 1 - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(MBEDTLS_ASN1_PARSE_C) - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief PKCS12 Password Based function (encryption / decryption) - * for cipher-based and mbedtls_md-based PBE's - * - * \note When encrypting, #MBEDTLS_CIPHER_PADDING_PKCS7 must - * be enabled at compile time. - * - * \deprecated This function is deprecated and will be removed in a - * future version of the library. - * Please use mbedtls_pkcs12_pbe_ext() instead. - * - * \warning When decrypting: - * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is enabled at compile - * time, this function validates the CBC padding and returns - * #MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH if the padding is - * invalid. Note that this can help active adversaries - * attempting to brute-forcing the password. Note also that - * there is no guarantee that an invalid password will be - * detected (the chances of a valid padding with a random - * password are about 1/255). - * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is disabled at compile - * time, this function does not validate the CBC padding. - * - * \param pbe_params an ASN1 buffer containing the pkcs-12 PbeParams structure - * \param mode either #MBEDTLS_PKCS12_PBE_ENCRYPT or - * #MBEDTLS_PKCS12_PBE_DECRYPT - * \param cipher_type the cipher used - * \param md_type the mbedtls_md used - * \param pwd Latin1-encoded password used. This may only be \c NULL when - * \p pwdlen is 0. No null terminator should be used. - * \param pwdlen length of the password (may be 0) - * \param data the input data - * \param len data length - * \param output Output buffer. - * On success, it contains the encrypted or decrypted data, - * possibly followed by the CBC padding. - * On failure, the content is indeterminate. - * For decryption, there must be enough room for \p len - * bytes. - * For encryption, there must be enough room for - * \p len + 1 bytes, rounded up to the block size of - * the block cipher identified by \p pbe_params. - * - * \return 0 if successful, or a MBEDTLS_ERR_XXX code - */ -int MBEDTLS_DEPRECATED mbedtls_pkcs12_pbe(mbedtls_asn1_buf *pbe_params, int mode, - mbedtls_cipher_type_t cipher_type, - mbedtls_md_type_t md_type, - const unsigned char *pwd, size_t pwdlen, - const unsigned char *data, size_t len, - unsigned char *output); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) - -/** - * \brief PKCS12 Password Based function (encryption / decryption) - * for cipher-based and mbedtls_md-based PBE's - * - * - * \warning When decrypting: - * - This function validates the CBC padding and returns - * #MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH if the padding is - * invalid. Note that this can help active adversaries - * attempting to brute-forcing the password. Note also that - * there is no guarantee that an invalid password will be - * detected (the chances of a valid padding with a random - * password are about 1/255). - * - * \param pbe_params an ASN1 buffer containing the pkcs-12 PbeParams structure - * \param mode either #MBEDTLS_PKCS12_PBE_ENCRYPT or - * #MBEDTLS_PKCS12_PBE_DECRYPT - * \param cipher_type the cipher used - * \param md_type the mbedtls_md used - * \param pwd Latin1-encoded password used. This may only be \c NULL when - * \p pwdlen is 0. No null terminator should be used. - * \param pwdlen length of the password (may be 0) - * \param data the input data - * \param len data length - * \param output Output buffer. - * On success, it contains the encrypted or decrypted data, - * possibly followed by the CBC padding. - * On failure, the content is indeterminate. - * For decryption, there must be enough room for \p len - * bytes. - * For encryption, there must be enough room for - * \p len + 1 bytes, rounded up to the block size of - * the block cipher identified by \p pbe_params. - * \param output_size size of output buffer. - * This must be big enough to accommodate for output plus - * padding data. - * \param output_len On success, length of actual data written to the output buffer. - * - * \return 0 if successful, or a MBEDTLS_ERR_XXX code - */ -int mbedtls_pkcs12_pbe_ext(mbedtls_asn1_buf *pbe_params, int mode, - mbedtls_cipher_type_t cipher_type, mbedtls_md_type_t md_type, - const unsigned char *pwd, size_t pwdlen, - const unsigned char *data, size_t len, - unsigned char *output, size_t output_size, - size_t *output_len); - -#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ - -#endif /* MBEDTLS_ASN1_PARSE_C */ - -/** - * \brief The PKCS#12 derivation function uses a password and a salt - * to produce pseudo-random bits for a particular "purpose". - * - * Depending on the given id, this function can produce an - * encryption/decryption key, an initialization vector or an - * integrity key. - * - * \param data buffer to store the derived data in - * \param datalen length of buffer to fill - * \param pwd The password to use. For compliance with PKCS#12 §B.1, this - * should be a BMPString, i.e. a Unicode string where each - * character is encoded as 2 bytes in big-endian order, with - * no byte order mark and with a null terminator (i.e. the - * last two bytes should be 0x00 0x00). - * \param pwdlen length of the password (may be 0). - * \param salt Salt buffer to use. This may only be \c NULL when - * \p saltlen is 0. - * \param saltlen length of the salt (may be zero) - * \param mbedtls_md mbedtls_md type to use during the derivation - * \param id id that describes the purpose (can be - * #MBEDTLS_PKCS12_DERIVE_KEY, #MBEDTLS_PKCS12_DERIVE_IV or - * #MBEDTLS_PKCS12_DERIVE_MAC_KEY) - * \param iterations number of iterations - * - * \return 0 if successful, or a MD, BIGNUM type error. - */ -int mbedtls_pkcs12_derivation(unsigned char *data, size_t datalen, - const unsigned char *pwd, size_t pwdlen, - const unsigned char *salt, size_t saltlen, - mbedtls_md_type_t mbedtls_md, int id, int iterations); - -#ifdef __cplusplus -} -#endif - -#endif /* pkcs12.h */ +/** + * \file pkcs12.h + * + * \brief PKCS#12 Personal Information Exchange Syntax + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PKCS12_H +#define MBEDTLS_PKCS12_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/md.h" +#include "mbedtls/cipher.h" +#include "mbedtls/asn1.h" + +#include + +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_PKCS12_BAD_INPUT_DATA -0x1F80 +/** Feature not available, e.g. unsupported encryption scheme. */ +#define MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE -0x1F00 +/** PBE ASN.1 data not as expected. */ +#define MBEDTLS_ERR_PKCS12_PBE_INVALID_FORMAT -0x1E80 +/** Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH -0x1E00 + +#define MBEDTLS_PKCS12_DERIVE_KEY 1 /**< encryption/decryption key */ +#define MBEDTLS_PKCS12_DERIVE_IV 2 /**< initialization vector */ +#define MBEDTLS_PKCS12_DERIVE_MAC_KEY 3 /**< integrity / MAC key */ + +#define MBEDTLS_PKCS12_PBE_DECRYPT 0 +#define MBEDTLS_PKCS12_PBE_ENCRYPT 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ASN1_PARSE_C) + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief PKCS12 Password Based function (encryption / decryption) + * for cipher-based and mbedtls_md-based PBE's + * + * \note When encrypting, #MBEDTLS_CIPHER_PADDING_PKCS7 must + * be enabled at compile time. + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * Please use mbedtls_pkcs12_pbe_ext() instead. + * + * \warning When decrypting: + * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is enabled at compile + * time, this function validates the CBC padding and returns + * #MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH if the padding is + * invalid. Note that this can help active adversaries + * attempting to brute-forcing the password. Note also that + * there is no guarantee that an invalid password will be + * detected (the chances of a valid padding with a random + * password are about 1/255). + * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is disabled at compile + * time, this function does not validate the CBC padding. + * + * \param pbe_params an ASN1 buffer containing the pkcs-12 PbeParams structure + * \param mode either #MBEDTLS_PKCS12_PBE_ENCRYPT or + * #MBEDTLS_PKCS12_PBE_DECRYPT + * \param cipher_type the cipher used + * \param md_type the mbedtls_md used + * \param pwd Latin1-encoded password used. This may only be \c NULL when + * \p pwdlen is 0. No null terminator should be used. + * \param pwdlen length of the password (may be 0) + * \param data the input data + * \param len data length + * \param output Output buffer. + * On success, it contains the encrypted or decrypted data, + * possibly followed by the CBC padding. + * On failure, the content is indeterminate. + * For decryption, there must be enough room for \p len + * bytes. + * For encryption, there must be enough room for + * \p len + 1 bytes, rounded up to the block size of + * the block cipher identified by \p pbe_params. + * + * \return 0 if successful, or a MBEDTLS_ERR_XXX code + */ +int MBEDTLS_DEPRECATED mbedtls_pkcs12_pbe(mbedtls_asn1_buf *pbe_params, int mode, + mbedtls_cipher_type_t cipher_type, + mbedtls_md_type_t md_type, + const unsigned char *pwd, size_t pwdlen, + const unsigned char *data, size_t len, + unsigned char *output); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + +/** + * \brief PKCS12 Password Based function (encryption / decryption) + * for cipher-based and mbedtls_md-based PBE's + * + * + * \warning When decrypting: + * - This function validates the CBC padding and returns + * #MBEDTLS_ERR_PKCS12_PASSWORD_MISMATCH if the padding is + * invalid. Note that this can help active adversaries + * attempting to brute-forcing the password. Note also that + * there is no guarantee that an invalid password will be + * detected (the chances of a valid padding with a random + * password are about 1/255). + * + * \param pbe_params an ASN1 buffer containing the pkcs-12 PbeParams structure + * \param mode either #MBEDTLS_PKCS12_PBE_ENCRYPT or + * #MBEDTLS_PKCS12_PBE_DECRYPT + * \param cipher_type the cipher used + * \param md_type the mbedtls_md used + * \param pwd Latin1-encoded password used. This may only be \c NULL when + * \p pwdlen is 0. No null terminator should be used. + * \param pwdlen length of the password (may be 0) + * \param data the input data + * \param len data length + * \param output Output buffer. + * On success, it contains the encrypted or decrypted data, + * possibly followed by the CBC padding. + * On failure, the content is indeterminate. + * For decryption, there must be enough room for \p len + * bytes. + * For encryption, there must be enough room for + * \p len + 1 bytes, rounded up to the block size of + * the block cipher identified by \p pbe_params. + * \param output_size size of output buffer. + * This must be big enough to accommodate for output plus + * padding data. + * \param output_len On success, length of actual data written to the output buffer. + * + * \return 0 if successful, or a MBEDTLS_ERR_XXX code + */ +int mbedtls_pkcs12_pbe_ext(mbedtls_asn1_buf *pbe_params, int mode, + mbedtls_cipher_type_t cipher_type, mbedtls_md_type_t md_type, + const unsigned char *pwd, size_t pwdlen, + const unsigned char *data, size_t len, + unsigned char *output, size_t output_size, + size_t *output_len); + +#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ + +#endif /* MBEDTLS_ASN1_PARSE_C */ + +/** + * \brief The PKCS#12 derivation function uses a password and a salt + * to produce pseudo-random bits for a particular "purpose". + * + * Depending on the given id, this function can produce an + * encryption/decryption key, an initialization vector or an + * integrity key. + * + * \param data buffer to store the derived data in + * \param datalen length of buffer to fill + * \param pwd The password to use. For compliance with PKCS#12 §B.1, this + * should be a BMPString, i.e. a Unicode string where each + * character is encoded as 2 bytes in big-endian order, with + * no byte order mark and with a null terminator (i.e. the + * last two bytes should be 0x00 0x00). + * \param pwdlen length of the password (may be 0). + * \param salt Salt buffer to use. This may only be \c NULL when + * \p saltlen is 0. + * \param saltlen length of the salt (may be zero) + * \param mbedtls_md mbedtls_md type to use during the derivation + * \param id id that describes the purpose (can be + * #MBEDTLS_PKCS12_DERIVE_KEY, #MBEDTLS_PKCS12_DERIVE_IV or + * #MBEDTLS_PKCS12_DERIVE_MAC_KEY) + * \param iterations number of iterations + * + * \return 0 if successful, or a MD, BIGNUM type error. + */ +int mbedtls_pkcs12_derivation(unsigned char *data, size_t datalen, + const unsigned char *pwd, size_t pwdlen, + const unsigned char *salt, size_t saltlen, + mbedtls_md_type_t mbedtls_md, int id, int iterations); + +#ifdef __cplusplus +} +#endif + +#endif /* pkcs12.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs5.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs5.h index 8b086aa..c425d86 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs5.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs5.h @@ -1,209 +1,209 @@ -/** - * \file pkcs5.h - * - * \brief PKCS#5 functions - * - * \author Mathias Olsson - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PKCS5_H -#define MBEDTLS_PKCS5_H - -#include "mbedtls/build_info.h" -#include "mbedtls/platform_util.h" - -#include "mbedtls/asn1.h" -#include "mbedtls/md.h" - -#include -#include - -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA -0x2f80 -/** Unexpected ASN.1 data. */ -#define MBEDTLS_ERR_PKCS5_INVALID_FORMAT -0x2f00 -/** Requested encryption or digest alg not available. */ -#define MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE -0x2e80 -/** Given private key password does not allow for correct decryption. */ -#define MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH -0x2e00 - -#define MBEDTLS_PKCS5_DECRYPT 0 -#define MBEDTLS_PKCS5_ENCRYPT 1 - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(MBEDTLS_ASN1_PARSE_C) - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief PKCS#5 PBES2 function - * - * \note When encrypting, #MBEDTLS_CIPHER_PADDING_PKCS7 must - * be enabled at compile time. - * - * \deprecated This function is deprecated and will be removed in a - * future version of the library. - * Please use mbedtls_pkcs5_pbes2_ext() instead. - * - * \warning When decrypting: - * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is enabled at compile - * time, this function validates the CBC padding and returns - * #MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH if the padding is - * invalid. Note that this can help active adversaries - * attempting to brute-forcing the password. Note also that - * there is no guarantee that an invalid password will be - * detected (the chances of a valid padding with a random - * password are about 1/255). - * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is disabled at compile - * time, this function does not validate the CBC padding. - * - * \param pbe_params the ASN.1 algorithm parameters - * \param mode either #MBEDTLS_PKCS5_DECRYPT or #MBEDTLS_PKCS5_ENCRYPT - * \param pwd password to use when generating key - * \param pwdlen length of password - * \param data data to process - * \param datalen length of data - * \param output Output buffer. - * On success, it contains the encrypted or decrypted data, - * possibly followed by the CBC padding. - * On failure, the content is indeterminate. - * For decryption, there must be enough room for \p datalen - * bytes. - * For encryption, there must be enough room for - * \p datalen + 1 bytes, rounded up to the block size of - * the block cipher identified by \p pbe_params. - * - * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. - */ -int MBEDTLS_DEPRECATED mbedtls_pkcs5_pbes2(const mbedtls_asn1_buf *pbe_params, int mode, - const unsigned char *pwd, size_t pwdlen, - const unsigned char *data, size_t datalen, - unsigned char *output); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) - -/** - * \brief PKCS#5 PBES2 function - * - * \warning When decrypting: - * - This function validates the CBC padding and returns - * #MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH if the padding is - * invalid. Note that this can help active adversaries - * attempting to brute-forcing the password. Note also that - * there is no guarantee that an invalid password will be - * detected (the chances of a valid padding with a random - * password are about 1/255). - * - * \param pbe_params the ASN.1 algorithm parameters - * \param mode either #MBEDTLS_PKCS5_DECRYPT or #MBEDTLS_PKCS5_ENCRYPT - * \param pwd password to use when generating key - * \param pwdlen length of password - * \param data data to process - * \param datalen length of data - * \param output Output buffer. - * On success, it contains the decrypted data. - * On failure, the content is indetermidate. - * For decryption, there must be enough room for \p datalen - * bytes. - * For encryption, there must be enough room for - * \p datalen + 1 bytes, rounded up to the block size of - * the block cipher identified by \p pbe_params. - * \param output_size size of output buffer. - * This must be big enough to accommodate for output plus - * padding data. - * \param output_len On success, length of actual data written to the output buffer. - * - * \returns 0 on success, or a MBEDTLS_ERR_XXX code if parsing or decryption fails. - */ -int mbedtls_pkcs5_pbes2_ext(const mbedtls_asn1_buf *pbe_params, int mode, - const unsigned char *pwd, size_t pwdlen, - const unsigned char *data, size_t datalen, - unsigned char *output, size_t output_size, - size_t *output_len); - -#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ - -#endif /* MBEDTLS_ASN1_PARSE_C */ - -/** - * \brief PKCS#5 PBKDF2 using HMAC without using the HMAC context - * - * \param md_type Hash algorithm used - * \param password Password to use when generating key - * \param plen Length of password - * \param salt Salt to use when generating key - * \param slen Length of salt - * \param iteration_count Iteration count - * \param key_length Length of generated key in bytes - * \param output Generated key. Must be at least as big as key_length - * - * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. - */ -int mbedtls_pkcs5_pbkdf2_hmac_ext(mbedtls_md_type_t md_type, - const unsigned char *password, - size_t plen, const unsigned char *salt, size_t slen, - unsigned int iteration_count, - uint32_t key_length, unsigned char *output); - -#if defined(MBEDTLS_MD_C) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief PKCS#5 PBKDF2 using HMAC - * - * \deprecated Superseded by mbedtls_pkcs5_pbkdf2_hmac_ext(). - * - * \param ctx Generic HMAC context - * \param password Password to use when generating key - * \param plen Length of password - * \param salt Salt to use when generating key - * \param slen Length of salt - * \param iteration_count Iteration count - * \param key_length Length of generated key in bytes - * \param output Generated key. Must be at least as big as key_length - * - * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. - */ -int MBEDTLS_DEPRECATED mbedtls_pkcs5_pbkdf2_hmac(mbedtls_md_context_t *ctx, - const unsigned char *password, - size_t plen, - const unsigned char *salt, - size_t slen, - unsigned int iteration_count, - uint32_t key_length, - unsigned char *output); -#endif /* !MBEDTLS_DEPRECATED_REMOVED */ -#endif /* MBEDTLS_MD_C */ -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int mbedtls_pkcs5_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* pkcs5.h */ +/** + * \file pkcs5.h + * + * \brief PKCS#5 functions + * + * \author Mathias Olsson + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PKCS5_H +#define MBEDTLS_PKCS5_H + +#include "mbedtls/build_info.h" +#include "mbedtls/platform_util.h" + +#include "mbedtls/asn1.h" +#include "mbedtls/md.h" + +#include +#include + +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_PKCS5_BAD_INPUT_DATA -0x2f80 +/** Unexpected ASN.1 data. */ +#define MBEDTLS_ERR_PKCS5_INVALID_FORMAT -0x2f00 +/** Requested encryption or digest alg not available. */ +#define MBEDTLS_ERR_PKCS5_FEATURE_UNAVAILABLE -0x2e80 +/** Given private key password does not allow for correct decryption. */ +#define MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH -0x2e00 + +#define MBEDTLS_PKCS5_DECRYPT 0 +#define MBEDTLS_PKCS5_ENCRYPT 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ASN1_PARSE_C) + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief PKCS#5 PBES2 function + * + * \note When encrypting, #MBEDTLS_CIPHER_PADDING_PKCS7 must + * be enabled at compile time. + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * Please use mbedtls_pkcs5_pbes2_ext() instead. + * + * \warning When decrypting: + * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is enabled at compile + * time, this function validates the CBC padding and returns + * #MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH if the padding is + * invalid. Note that this can help active adversaries + * attempting to brute-forcing the password. Note also that + * there is no guarantee that an invalid password will be + * detected (the chances of a valid padding with a random + * password are about 1/255). + * - if #MBEDTLS_CIPHER_PADDING_PKCS7 is disabled at compile + * time, this function does not validate the CBC padding. + * + * \param pbe_params the ASN.1 algorithm parameters + * \param mode either #MBEDTLS_PKCS5_DECRYPT or #MBEDTLS_PKCS5_ENCRYPT + * \param pwd password to use when generating key + * \param pwdlen length of password + * \param data data to process + * \param datalen length of data + * \param output Output buffer. + * On success, it contains the encrypted or decrypted data, + * possibly followed by the CBC padding. + * On failure, the content is indeterminate. + * For decryption, there must be enough room for \p datalen + * bytes. + * For encryption, there must be enough room for + * \p datalen + 1 bytes, rounded up to the block size of + * the block cipher identified by \p pbe_params. + * + * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. + */ +int MBEDTLS_DEPRECATED mbedtls_pkcs5_pbes2(const mbedtls_asn1_buf *pbe_params, int mode, + const unsigned char *pwd, size_t pwdlen, + const unsigned char *data, size_t datalen, + unsigned char *output); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + +/** + * \brief PKCS#5 PBES2 function + * + * \warning When decrypting: + * - This function validates the CBC padding and returns + * #MBEDTLS_ERR_PKCS5_PASSWORD_MISMATCH if the padding is + * invalid. Note that this can help active adversaries + * attempting to brute-forcing the password. Note also that + * there is no guarantee that an invalid password will be + * detected (the chances of a valid padding with a random + * password are about 1/255). + * + * \param pbe_params the ASN.1 algorithm parameters + * \param mode either #MBEDTLS_PKCS5_DECRYPT or #MBEDTLS_PKCS5_ENCRYPT + * \param pwd password to use when generating key + * \param pwdlen length of password + * \param data data to process + * \param datalen length of data + * \param output Output buffer. + * On success, it contains the decrypted data. + * On failure, the content is indetermidate. + * For decryption, there must be enough room for \p datalen + * bytes. + * For encryption, there must be enough room for + * \p datalen + 1 bytes, rounded up to the block size of + * the block cipher identified by \p pbe_params. + * \param output_size size of output buffer. + * This must be big enough to accommodate for output plus + * padding data. + * \param output_len On success, length of actual data written to the output buffer. + * + * \returns 0 on success, or a MBEDTLS_ERR_XXX code if parsing or decryption fails. + */ +int mbedtls_pkcs5_pbes2_ext(const mbedtls_asn1_buf *pbe_params, int mode, + const unsigned char *pwd, size_t pwdlen, + const unsigned char *data, size_t datalen, + unsigned char *output, size_t output_size, + size_t *output_len); + +#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ + +#endif /* MBEDTLS_ASN1_PARSE_C */ + +/** + * \brief PKCS#5 PBKDF2 using HMAC without using the HMAC context + * + * \param md_type Hash algorithm used + * \param password Password to use when generating key + * \param plen Length of password + * \param salt Salt to use when generating key + * \param slen Length of salt + * \param iteration_count Iteration count + * \param key_length Length of generated key in bytes + * \param output Generated key. Must be at least as big as key_length + * + * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. + */ +int mbedtls_pkcs5_pbkdf2_hmac_ext(mbedtls_md_type_t md_type, + const unsigned char *password, + size_t plen, const unsigned char *salt, size_t slen, + unsigned int iteration_count, + uint32_t key_length, unsigned char *output); + +#if defined(MBEDTLS_MD_C) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief PKCS#5 PBKDF2 using HMAC + * + * \deprecated Superseded by mbedtls_pkcs5_pbkdf2_hmac_ext(). + * + * \param ctx Generic HMAC context + * \param password Password to use when generating key + * \param plen Length of password + * \param salt Salt to use when generating key + * \param slen Length of salt + * \param iteration_count Iteration count + * \param key_length Length of generated key in bytes + * \param output Generated key. Must be at least as big as key_length + * + * \returns 0 on success, or a MBEDTLS_ERR_XXX code if verification fails. + */ +int MBEDTLS_DEPRECATED mbedtls_pkcs5_pbkdf2_hmac(mbedtls_md_context_t *ctx, + const unsigned char *password, + size_t plen, + const unsigned char *salt, + size_t slen, + unsigned int iteration_count, + uint32_t key_length, + unsigned char *output); +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_MD_C */ +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_pkcs5_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* pkcs5.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs7.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs7.h index 1231e34..2fad9a2 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs7.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/pkcs7.h @@ -1,253 +1,253 @@ -/** - * \file pkcs7.h - * - * \brief PKCS #7 generic defines and structures - * https://tools.ietf.org/html/rfc2315 - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * Note: For the time being, this implementation of the PKCS #7 cryptographic - * message syntax is a partial implementation of RFC 2315. - * Differences include: - * - The RFC specifies 6 different content types. The only type currently - * supported in Mbed TLS is the signed-data content type. - * - The only supported PKCS #7 Signed Data syntax version is version 1 - * - The RFC specifies support for BER. This implementation is limited to - * DER only. - * - The RFC specifies that multiple digest algorithms can be specified - * in the Signed Data type. Only one digest algorithm is supported in Mbed TLS. - * - The RFC specifies the Signed Data type can contain multiple X.509 or PKCS #6 extended - * certificates. In Mbed TLS, this list can only contain 0 or 1 certificates - * and they must be in X.509 format. - * - The RFC specifies the Signed Data type can contain - * certificate-revocation lists (CRLs). This implementation has no support - * for CRLs so it is assumed to be an empty list. - * - The RFC allows for SignerInfo structure to optionally contain - * unauthenticatedAttributes and authenticatedAttributes. In Mbed TLS it is - * assumed these fields are empty. - * - The RFC allows for the signed Data type to contain contentInfo. This - * implementation assumes the type is DATA and the content is empty. - */ - -#ifndef MBEDTLS_PKCS7_H -#define MBEDTLS_PKCS7_H - -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/asn1.h" -#include "mbedtls/x509.h" -#include "mbedtls/x509_crt.h" - -/** - * \name PKCS #7 Module Error codes - * \{ - */ -#define MBEDTLS_ERR_PKCS7_INVALID_FORMAT -0x5300 /**< The format is invalid, e.g. different type expected. */ -#define MBEDTLS_ERR_PKCS7_FEATURE_UNAVAILABLE -0x5380 /**< Unavailable feature, e.g. anything other than signed data. */ -#define MBEDTLS_ERR_PKCS7_INVALID_VERSION -0x5400 /**< The PKCS #7 version element is invalid or cannot be parsed. */ -#define MBEDTLS_ERR_PKCS7_INVALID_CONTENT_INFO -0x5480 /**< The PKCS #7 content info is invalid or cannot be parsed. */ -#define MBEDTLS_ERR_PKCS7_INVALID_ALG -0x5500 /**< The algorithm tag or value is invalid or cannot be parsed. */ -#define MBEDTLS_ERR_PKCS7_INVALID_CERT -0x5580 /**< The certificate tag or value is invalid or cannot be parsed. */ -#define MBEDTLS_ERR_PKCS7_INVALID_SIGNATURE -0x5600 /**< Error parsing the signature */ -#define MBEDTLS_ERR_PKCS7_INVALID_SIGNER_INFO -0x5680 /**< Error parsing the signer's info */ -#define MBEDTLS_ERR_PKCS7_BAD_INPUT_DATA -0x5700 /**< Input invalid. */ -#define MBEDTLS_ERR_PKCS7_ALLOC_FAILED -0x5780 /**< Allocation of memory failed. */ -#define MBEDTLS_ERR_PKCS7_VERIFY_FAIL -0x5800 /**< Verification Failed */ -#define MBEDTLS_ERR_PKCS7_CERT_DATE_INVALID -0x5880 /**< The PKCS #7 date issued/expired dates are invalid */ -/* \} name */ - -/** - * \name PKCS #7 Supported Version - * \{ - */ -#define MBEDTLS_PKCS7_SUPPORTED_VERSION 0x01 -/* \} name */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Type-length-value structure that allows for ASN.1 using DER. - */ -typedef mbedtls_asn1_buf mbedtls_pkcs7_buf; - -/** - * Container for ASN.1 named information objects. - * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.). - */ -typedef mbedtls_asn1_named_data mbedtls_pkcs7_name; - -/** - * Container for a sequence of ASN.1 items - */ -typedef mbedtls_asn1_sequence mbedtls_pkcs7_sequence; - -/** - * PKCS #7 types - */ -typedef enum { - MBEDTLS_PKCS7_NONE=0, - MBEDTLS_PKCS7_DATA, - MBEDTLS_PKCS7_SIGNED_DATA, - MBEDTLS_PKCS7_ENVELOPED_DATA, - MBEDTLS_PKCS7_SIGNED_AND_ENVELOPED_DATA, - MBEDTLS_PKCS7_DIGESTED_DATA, - MBEDTLS_PKCS7_ENCRYPTED_DATA, -} -mbedtls_pkcs7_type; - -/** - * Structure holding PKCS #7 signer info - */ -typedef struct mbedtls_pkcs7_signer_info { - int MBEDTLS_PRIVATE(version); - mbedtls_x509_buf MBEDTLS_PRIVATE(serial); - mbedtls_x509_name MBEDTLS_PRIVATE(issuer); - mbedtls_x509_buf MBEDTLS_PRIVATE(issuer_raw); - mbedtls_x509_buf MBEDTLS_PRIVATE(alg_identifier); - mbedtls_x509_buf MBEDTLS_PRIVATE(sig_alg_identifier); - mbedtls_x509_buf MBEDTLS_PRIVATE(sig); - struct mbedtls_pkcs7_signer_info *MBEDTLS_PRIVATE(next); -} -mbedtls_pkcs7_signer_info; - -/** - * Structure holding the signed data section - */ -typedef struct mbedtls_pkcs7_signed_data { - int MBEDTLS_PRIVATE(version); - mbedtls_pkcs7_buf MBEDTLS_PRIVATE(digest_alg_identifiers); - int MBEDTLS_PRIVATE(no_of_certs); - mbedtls_x509_crt MBEDTLS_PRIVATE(certs); - int MBEDTLS_PRIVATE(no_of_crls); - mbedtls_x509_crl MBEDTLS_PRIVATE(crl); - int MBEDTLS_PRIVATE(no_of_signers); - mbedtls_pkcs7_signer_info MBEDTLS_PRIVATE(signers); -} -mbedtls_pkcs7_signed_data; - -/** - * Structure holding PKCS #7 structure, only signed data for now - */ -typedef struct mbedtls_pkcs7 { - mbedtls_pkcs7_buf MBEDTLS_PRIVATE(raw); - mbedtls_pkcs7_signed_data MBEDTLS_PRIVATE(signed_data); -} -mbedtls_pkcs7; - -/** - * \brief Initialize mbedtls_pkcs7 structure. - * - * \param pkcs7 mbedtls_pkcs7 structure. - */ -void mbedtls_pkcs7_init(mbedtls_pkcs7 *pkcs7); - -/** - * \brief Parse a single DER formatted PKCS #7 detached signature. - * - * \param pkcs7 The mbedtls_pkcs7 structure to be filled by the parser. - * \param buf The buffer holding only the DER encoded PKCS #7 content. - * \param buflen The size in bytes of \p buf. The size must be exactly the - * length of the DER encoded PKCS #7 content. - * - * \note This function makes an internal copy of the PKCS #7 buffer - * \p buf. In particular, \p buf may be destroyed or reused - * after this call returns. - * \note Signatures with internal data are not supported. - * - * \return The \c mbedtls_pkcs7_type of \p buf, if successful. - * \return A negative error code on failure. - */ -int mbedtls_pkcs7_parse_der(mbedtls_pkcs7 *pkcs7, const unsigned char *buf, - const size_t buflen); - -/** - * \brief Verification of PKCS #7 signature against a caller-supplied - * certificate. - * - * For each signer in the PKCS structure, this function computes - * a signature over the supplied data, using the supplied - * certificate and the same digest algorithm as specified by the - * signer. It then compares this signature against the - * signer's signature; verification succeeds if any comparison - * matches. - * - * This function does not use the certificates held within the - * PKCS #7 structure itself, and does not check that the - * certificate is signed by a trusted certification authority. - * - * \param pkcs7 mbedtls_pkcs7 structure containing signature. - * \param cert Certificate containing key to verify signature. - * \param data Plain data on which signature has to be verified. - * \param datalen Length of the data. - * - * \note This function internally calculates the hash on the supplied - * plain data for signature verification. - * - * \return 0 if the signature verifies, or a negative error code on failure. - */ -int mbedtls_pkcs7_signed_data_verify(mbedtls_pkcs7 *pkcs7, - const mbedtls_x509_crt *cert, - const unsigned char *data, - size_t datalen); - -/** - * \brief Verification of PKCS #7 signature against a caller-supplied - * certificate. - * - * For each signer in the PKCS structure, this function - * validates a signature over the supplied hash, using the - * supplied certificate and the same digest algorithm as - * specified by the signer. Verification succeeds if any - * signature is good. - * - * This function does not use the certificates held within the - * PKCS #7 structure itself, and does not check that the - * certificate is signed by a trusted certification authority. - * - * \param pkcs7 PKCS #7 structure containing signature. - * \param cert Certificate containing key to verify signature. - * \param hash Hash of the plain data on which signature has to be verified. - * \param hashlen Length of the hash. - * - * \note This function is different from mbedtls_pkcs7_signed_data_verify() - * in that it is directly passed the hash of the data. - * - * \return 0 if the signature verifies, or a negative error code on failure. - */ -int mbedtls_pkcs7_signed_hash_verify(mbedtls_pkcs7 *pkcs7, - const mbedtls_x509_crt *cert, - const unsigned char *hash, size_t hashlen); - -/** - * \brief Unallocate all PKCS #7 data and zeroize the memory. - * It doesn't free \p pkcs7 itself. This should be done by the caller. - * - * \param pkcs7 mbedtls_pkcs7 structure to free. - */ -void mbedtls_pkcs7_free(mbedtls_pkcs7 *pkcs7); - -#ifdef __cplusplus -} -#endif - -#endif /* pkcs7.h */ +/** + * \file pkcs7.h + * + * \brief PKCS #7 generic defines and structures + * https://tools.ietf.org/html/rfc2315 + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * Note: For the time being, this implementation of the PKCS #7 cryptographic + * message syntax is a partial implementation of RFC 2315. + * Differences include: + * - The RFC specifies 6 different content types. The only type currently + * supported in Mbed TLS is the signed-data content type. + * - The only supported PKCS #7 Signed Data syntax version is version 1 + * - The RFC specifies support for BER. This implementation is limited to + * DER only. + * - The RFC specifies that multiple digest algorithms can be specified + * in the Signed Data type. Only one digest algorithm is supported in Mbed TLS. + * - The RFC specifies the Signed Data type can contain multiple X.509 or PKCS #6 extended + * certificates. In Mbed TLS, this list can only contain 0 or 1 certificates + * and they must be in X.509 format. + * - The RFC specifies the Signed Data type can contain + * certificate-revocation lists (CRLs). This implementation has no support + * for CRLs so it is assumed to be an empty list. + * - The RFC allows for SignerInfo structure to optionally contain + * unauthenticatedAttributes and authenticatedAttributes. In Mbed TLS it is + * assumed these fields are empty. + * - The RFC allows for the signed Data type to contain contentInfo. This + * implementation assumes the type is DATA and the content is empty. + */ + +#ifndef MBEDTLS_PKCS7_H +#define MBEDTLS_PKCS7_H + +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/asn1.h" +#include "mbedtls/x509.h" +#include "mbedtls/x509_crt.h" + +/** + * \name PKCS #7 Module Error codes + * \{ + */ +#define MBEDTLS_ERR_PKCS7_INVALID_FORMAT -0x5300 /**< The format is invalid, e.g. different type expected. */ +#define MBEDTLS_ERR_PKCS7_FEATURE_UNAVAILABLE -0x5380 /**< Unavailable feature, e.g. anything other than signed data. */ +#define MBEDTLS_ERR_PKCS7_INVALID_VERSION -0x5400 /**< The PKCS #7 version element is invalid or cannot be parsed. */ +#define MBEDTLS_ERR_PKCS7_INVALID_CONTENT_INFO -0x5480 /**< The PKCS #7 content info is invalid or cannot be parsed. */ +#define MBEDTLS_ERR_PKCS7_INVALID_ALG -0x5500 /**< The algorithm tag or value is invalid or cannot be parsed. */ +#define MBEDTLS_ERR_PKCS7_INVALID_CERT -0x5580 /**< The certificate tag or value is invalid or cannot be parsed. */ +#define MBEDTLS_ERR_PKCS7_INVALID_SIGNATURE -0x5600 /**< Error parsing the signature */ +#define MBEDTLS_ERR_PKCS7_INVALID_SIGNER_INFO -0x5680 /**< Error parsing the signer's info */ +#define MBEDTLS_ERR_PKCS7_BAD_INPUT_DATA -0x5700 /**< Input invalid. */ +#define MBEDTLS_ERR_PKCS7_ALLOC_FAILED -0x5780 /**< Allocation of memory failed. */ +#define MBEDTLS_ERR_PKCS7_VERIFY_FAIL -0x5800 /**< Verification Failed */ +#define MBEDTLS_ERR_PKCS7_CERT_DATE_INVALID -0x5880 /**< The PKCS #7 date issued/expired dates are invalid */ +/* \} name */ + +/** + * \name PKCS #7 Supported Version + * \{ + */ +#define MBEDTLS_PKCS7_SUPPORTED_VERSION 0x01 +/* \} name */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Type-length-value structure that allows for ASN.1 using DER. + */ +typedef mbedtls_asn1_buf mbedtls_pkcs7_buf; + +/** + * Container for ASN.1 named information objects. + * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.). + */ +typedef mbedtls_asn1_named_data mbedtls_pkcs7_name; + +/** + * Container for a sequence of ASN.1 items + */ +typedef mbedtls_asn1_sequence mbedtls_pkcs7_sequence; + +/** + * PKCS #7 types + */ +typedef enum { + MBEDTLS_PKCS7_NONE=0, + MBEDTLS_PKCS7_DATA, + MBEDTLS_PKCS7_SIGNED_DATA, + MBEDTLS_PKCS7_ENVELOPED_DATA, + MBEDTLS_PKCS7_SIGNED_AND_ENVELOPED_DATA, + MBEDTLS_PKCS7_DIGESTED_DATA, + MBEDTLS_PKCS7_ENCRYPTED_DATA, +} +mbedtls_pkcs7_type; + +/** + * Structure holding PKCS #7 signer info + */ +typedef struct mbedtls_pkcs7_signer_info { + int MBEDTLS_PRIVATE(version); + mbedtls_x509_buf MBEDTLS_PRIVATE(serial); + mbedtls_x509_name MBEDTLS_PRIVATE(issuer); + mbedtls_x509_buf MBEDTLS_PRIVATE(issuer_raw); + mbedtls_x509_buf MBEDTLS_PRIVATE(alg_identifier); + mbedtls_x509_buf MBEDTLS_PRIVATE(sig_alg_identifier); + mbedtls_x509_buf MBEDTLS_PRIVATE(sig); + struct mbedtls_pkcs7_signer_info *MBEDTLS_PRIVATE(next); +} +mbedtls_pkcs7_signer_info; + +/** + * Structure holding the signed data section + */ +typedef struct mbedtls_pkcs7_signed_data { + int MBEDTLS_PRIVATE(version); + mbedtls_pkcs7_buf MBEDTLS_PRIVATE(digest_alg_identifiers); + int MBEDTLS_PRIVATE(no_of_certs); + mbedtls_x509_crt MBEDTLS_PRIVATE(certs); + int MBEDTLS_PRIVATE(no_of_crls); + mbedtls_x509_crl MBEDTLS_PRIVATE(crl); + int MBEDTLS_PRIVATE(no_of_signers); + mbedtls_pkcs7_signer_info MBEDTLS_PRIVATE(signers); +} +mbedtls_pkcs7_signed_data; + +/** + * Structure holding PKCS #7 structure, only signed data for now + */ +typedef struct mbedtls_pkcs7 { + mbedtls_pkcs7_buf MBEDTLS_PRIVATE(raw); + mbedtls_pkcs7_signed_data MBEDTLS_PRIVATE(signed_data); +} +mbedtls_pkcs7; + +/** + * \brief Initialize mbedtls_pkcs7 structure. + * + * \param pkcs7 mbedtls_pkcs7 structure. + */ +void mbedtls_pkcs7_init(mbedtls_pkcs7 *pkcs7); + +/** + * \brief Parse a single DER formatted PKCS #7 detached signature. + * + * \param pkcs7 The mbedtls_pkcs7 structure to be filled by the parser. + * \param buf The buffer holding only the DER encoded PKCS #7 content. + * \param buflen The size in bytes of \p buf. The size must be exactly the + * length of the DER encoded PKCS #7 content. + * + * \note This function makes an internal copy of the PKCS #7 buffer + * \p buf. In particular, \p buf may be destroyed or reused + * after this call returns. + * \note Signatures with internal data are not supported. + * + * \return The \c mbedtls_pkcs7_type of \p buf, if successful. + * \return A negative error code on failure. + */ +int mbedtls_pkcs7_parse_der(mbedtls_pkcs7 *pkcs7, const unsigned char *buf, + const size_t buflen); + +/** + * \brief Verification of PKCS #7 signature against a caller-supplied + * certificate. + * + * For each signer in the PKCS structure, this function computes + * a signature over the supplied data, using the supplied + * certificate and the same digest algorithm as specified by the + * signer. It then compares this signature against the + * signer's signature; verification succeeds if any comparison + * matches. + * + * This function does not use the certificates held within the + * PKCS #7 structure itself, and does not check that the + * certificate is signed by a trusted certification authority. + * + * \param pkcs7 mbedtls_pkcs7 structure containing signature. + * \param cert Certificate containing key to verify signature. + * \param data Plain data on which signature has to be verified. + * \param datalen Length of the data. + * + * \note This function internally calculates the hash on the supplied + * plain data for signature verification. + * + * \return 0 if the signature verifies, or a negative error code on failure. + */ +int mbedtls_pkcs7_signed_data_verify(mbedtls_pkcs7 *pkcs7, + const mbedtls_x509_crt *cert, + const unsigned char *data, + size_t datalen); + +/** + * \brief Verification of PKCS #7 signature against a caller-supplied + * certificate. + * + * For each signer in the PKCS structure, this function + * validates a signature over the supplied hash, using the + * supplied certificate and the same digest algorithm as + * specified by the signer. Verification succeeds if any + * signature is good. + * + * This function does not use the certificates held within the + * PKCS #7 structure itself, and does not check that the + * certificate is signed by a trusted certification authority. + * + * \param pkcs7 PKCS #7 structure containing signature. + * \param cert Certificate containing key to verify signature. + * \param hash Hash of the plain data on which signature has to be verified. + * \param hashlen Length of the hash. + * + * \note This function is different from mbedtls_pkcs7_signed_data_verify() + * in that it is directly passed the hash of the data. + * + * \return 0 if the signature verifies, or a negative error code on failure. + */ +int mbedtls_pkcs7_signed_hash_verify(mbedtls_pkcs7 *pkcs7, + const mbedtls_x509_crt *cert, + const unsigned char *hash, size_t hashlen); + +/** + * \brief Unallocate all PKCS #7 data and zeroize the memory. + * It doesn't free \p pkcs7 itself. This should be done by the caller. + * + * \param pkcs7 mbedtls_pkcs7 structure to free. + */ +void mbedtls_pkcs7_free(mbedtls_pkcs7 *pkcs7); + +#ifdef __cplusplus +} +#endif + +#endif /* pkcs7.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform.h index 3fc1fd0..251fe28 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform.h @@ -1,497 +1,497 @@ -/** - * \file platform.h - * - * \brief This file contains the definitions and functions of the - * Mbed TLS platform abstraction layer. - * - * The platform abstraction layer removes the need for the library - * to directly link to standard C library functions or operating - * system services, making the library easier to port and embed. - * Application developers and users of the library can provide their own - * implementations of these functions, or implementations specific to - * their platform, which can be statically linked to the library or - * dynamically configured at runtime. - * - * When all compilation options related to platform abstraction are - * disabled, this header just defines `mbedtls_xxx` function names - * as aliases to the standard `xxx` function. - * - * Most modules in the library and example programs are expected to - * include this header. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PLATFORM_H -#define MBEDTLS_PLATFORM_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#if defined(MBEDTLS_HAVE_TIME) -#include "mbedtls/platform_time.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -/* The older Microsoft Windows common runtime provides non-conforming - * implementations of some standard library functions, including snprintf - * and vsnprintf. This affects MSVC and MinGW builds. - */ -#if defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER <= 1900) -#define MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF -#define MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF -#endif - -#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) -#include -#include -#if defined(MBEDTLS_HAVE_TIME) -#include -#endif -#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF) -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) -#define MBEDTLS_PLATFORM_STD_SNPRINTF mbedtls_platform_win32_snprintf /**< The default \c snprintf function to use. */ -#else -#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< The default \c snprintf function to use. */ -#endif -#endif -#if !defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) -#define MBEDTLS_PLATFORM_STD_VSNPRINTF mbedtls_platform_win32_vsnprintf /**< The default \c vsnprintf function to use. */ -#else -#define MBEDTLS_PLATFORM_STD_VSNPRINTF vsnprintf /**< The default \c vsnprintf function to use. */ -#endif -#endif -#if !defined(MBEDTLS_PLATFORM_STD_PRINTF) -#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< The default \c printf function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF) -#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< The default \c fprintf function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_CALLOC) -#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< The default \c calloc function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_FREE) -#define MBEDTLS_PLATFORM_STD_FREE free /**< The default \c free function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_SETBUF) -#define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< The default \c setbuf function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_EXIT) -#define MBEDTLS_PLATFORM_STD_EXIT exit /**< The default \c exit function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_TIME) -#define MBEDTLS_PLATFORM_STD_TIME time /**< The default \c time function to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) -#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS EXIT_SUCCESS /**< The default exit value to use. */ -#endif -#if !defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) -#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE EXIT_FAILURE /**< The default exit value to use. */ -#endif -#if defined(MBEDTLS_FS_IO) -#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) -#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read -#endif -#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) -#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write -#endif -#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_FILE) -#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" -#endif -#endif /* MBEDTLS_FS_IO */ -#else /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ -#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) -#include MBEDTLS_PLATFORM_STD_MEM_HDR -#endif -#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ - -/* Enable certain documented defines only when generating doxygen to avoid - * an "unrecognized define" error. */ -#if defined(__DOXYGEN__) && !defined(MBEDTLS_PLATFORM_STD_CALLOC) -#define MBEDTLS_PLATFORM_STD_CALLOC -#endif - -#if defined(__DOXYGEN__) && !defined(MBEDTLS_PLATFORM_STD_FREE) -#define MBEDTLS_PLATFORM_STD_FREE -#endif - -/** \} name SECTION: Module settings */ - -/* - * The function pointers for calloc and free. - * Please see MBEDTLS_PLATFORM_STD_CALLOC and MBEDTLS_PLATFORM_STD_FREE - * in mbedtls_config.h for more information about behaviour and requirements. - */ -#if defined(MBEDTLS_PLATFORM_MEMORY) -#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && \ - defined(MBEDTLS_PLATFORM_CALLOC_MACRO) -#undef mbedtls_free -#undef mbedtls_calloc -#define mbedtls_free MBEDTLS_PLATFORM_FREE_MACRO -#define mbedtls_calloc MBEDTLS_PLATFORM_CALLOC_MACRO -#else -/* For size_t */ -#include -extern void *mbedtls_calloc(size_t n, size_t size); -extern void mbedtls_free(void *ptr); - -/** - * \brief This function dynamically sets the memory-management - * functions used by the library, during runtime. - * - * \param calloc_func The \c calloc function implementation. - * \param free_func The \c free function implementation. - * - * \return \c 0. - */ -int mbedtls_platform_set_calloc_free(void *(*calloc_func)(size_t, size_t), - void (*free_func)(void *)); -#endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */ -#else /* !MBEDTLS_PLATFORM_MEMORY */ -#undef mbedtls_free -#undef mbedtls_calloc -#define mbedtls_free free -#define mbedtls_calloc calloc -#endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */ - -/* - * The function pointers for fprintf - */ -#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) -/* We need FILE * */ -#include -extern int (*mbedtls_fprintf)(FILE *stream, const char *format, ...); - -/** - * \brief This function dynamically configures the fprintf - * function that is called when the - * mbedtls_fprintf() function is invoked by the library. - * - * \param fprintf_func The \c fprintf function implementation. - * - * \return \c 0. - */ -int mbedtls_platform_set_fprintf(int (*fprintf_func)(FILE *stream, const char *, - ...)); -#else -#undef mbedtls_fprintf -#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) -#define mbedtls_fprintf MBEDTLS_PLATFORM_FPRINTF_MACRO -#else -#define mbedtls_fprintf fprintf -#endif /* MBEDTLS_PLATFORM_FPRINTF_MACRO */ -#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ - -/* - * The function pointers for printf - */ -#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) -extern int (*mbedtls_printf)(const char *format, ...); - -/** - * \brief This function dynamically configures the snprintf - * function that is called when the mbedtls_snprintf() - * function is invoked by the library. - * - * \param printf_func The \c printf function implementation. - * - * \return \c 0 on success. - */ -int mbedtls_platform_set_printf(int (*printf_func)(const char *, ...)); -#else /* !MBEDTLS_PLATFORM_PRINTF_ALT */ -#undef mbedtls_printf -#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) -#define mbedtls_printf MBEDTLS_PLATFORM_PRINTF_MACRO -#else -#define mbedtls_printf printf -#endif /* MBEDTLS_PLATFORM_PRINTF_MACRO */ -#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ - -/* - * The function pointers for snprintf - * - * The snprintf implementation should conform to C99: - * - it *must* always correctly zero-terminate the buffer - * (except when n == 0, then it must leave the buffer untouched) - * - however it is acceptable to return -1 instead of the required length when - * the destination buffer is too short. - */ -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) -/* For Windows (inc. MSYS2), we provide our own fixed implementation */ -int mbedtls_platform_win32_snprintf(char *s, size_t n, const char *fmt, ...); -#endif - -#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) -extern int (*mbedtls_snprintf)(char *s, size_t n, const char *format, ...); - -/** - * \brief This function allows configuring a custom - * \c snprintf function pointer. - * - * \param snprintf_func The \c snprintf function implementation. - * - * \return \c 0 on success. - */ -int mbedtls_platform_set_snprintf(int (*snprintf_func)(char *s, size_t n, - const char *format, ...)); -#else /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ -#undef mbedtls_snprintf -#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) -#define mbedtls_snprintf MBEDTLS_PLATFORM_SNPRINTF_MACRO -#else -#define mbedtls_snprintf MBEDTLS_PLATFORM_STD_SNPRINTF -#endif /* MBEDTLS_PLATFORM_SNPRINTF_MACRO */ -#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ - -/* - * The function pointers for vsnprintf - * - * The vsnprintf implementation should conform to C99: - * - it *must* always correctly zero-terminate the buffer - * (except when n == 0, then it must leave the buffer untouched) - * - however it is acceptable to return -1 instead of the required length when - * the destination buffer is too short. - */ -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) -#include -/* For Older Windows (inc. MSYS2), we provide our own fixed implementation */ -int mbedtls_platform_win32_vsnprintf(char *s, size_t n, const char *fmt, va_list arg); -#endif - -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) -#include -extern int (*mbedtls_vsnprintf)(char *s, size_t n, const char *format, va_list arg); - -/** - * \brief Set your own snprintf function pointer - * - * \param vsnprintf_func The \c vsnprintf function implementation - * - * \return \c 0 - */ -int mbedtls_platform_set_vsnprintf(int (*vsnprintf_func)(char *s, size_t n, - const char *format, va_list arg)); -#else /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ -#undef mbedtls_vsnprintf -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) -#define mbedtls_vsnprintf MBEDTLS_PLATFORM_VSNPRINTF_MACRO -#else -#define mbedtls_vsnprintf vsnprintf -#endif /* MBEDTLS_PLATFORM_VSNPRINTF_MACRO */ -#endif /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ - -/* - * The function pointers for setbuf - */ -#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) -#include -/** - * \brief Function pointer to call for `setbuf()` functionality - * (changing the internal buffering on stdio calls). - * - * \note The library calls this function to disable - * buffering when reading or writing sensitive data, - * to avoid having extra copies of sensitive data - * remaining in stdio buffers after the file is - * closed. If this is not a concern, for example if - * your platform's stdio doesn't have any buffering, - * you can set mbedtls_setbuf to a function that - * does nothing. - * - * The library always calls this function with - * `buf` equal to `NULL`. - */ -extern void (*mbedtls_setbuf)(FILE *stream, char *buf); - -/** - * \brief Dynamically configure the function that is called - * when the mbedtls_setbuf() function is called by the - * library. - * - * \param setbuf_func The \c setbuf function implementation - * - * \return \c 0 - */ -int mbedtls_platform_set_setbuf(void (*setbuf_func)( - FILE *stream, char *buf)); -#else -#undef mbedtls_setbuf -#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) -/** - * \brief Macro defining the function for the library to - * call for `setbuf` functionality (changing the - * internal buffering on stdio calls). - * - * \note See extra comments on the mbedtls_setbuf() function - * pointer above. - * - * \return \c 0 on success, negative on error. - */ -#define mbedtls_setbuf MBEDTLS_PLATFORM_SETBUF_MACRO -#else -#define mbedtls_setbuf setbuf -#endif /* MBEDTLS_PLATFORM_SETBUF_MACRO */ -#endif /* MBEDTLS_PLATFORM_SETBUF_ALT */ - -/* - * The function pointers for exit - */ -#if defined(MBEDTLS_PLATFORM_EXIT_ALT) -extern void (*mbedtls_exit)(int status); - -/** - * \brief This function dynamically configures the exit - * function that is called when the mbedtls_exit() - * function is invoked by the library. - * - * \param exit_func The \c exit function implementation. - * - * \return \c 0 on success. - */ -int mbedtls_platform_set_exit(void (*exit_func)(int status)); -#else -#undef mbedtls_exit -#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) -#define mbedtls_exit MBEDTLS_PLATFORM_EXIT_MACRO -#else -#define mbedtls_exit exit -#endif /* MBEDTLS_PLATFORM_EXIT_MACRO */ -#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ - -/* - * The default exit values - */ -#if defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) -#define MBEDTLS_EXIT_SUCCESS MBEDTLS_PLATFORM_STD_EXIT_SUCCESS -#else -#define MBEDTLS_EXIT_SUCCESS 0 -#endif -#if defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) -#define MBEDTLS_EXIT_FAILURE MBEDTLS_PLATFORM_STD_EXIT_FAILURE -#else -#define MBEDTLS_EXIT_FAILURE 1 -#endif - -/* - * The function pointers for reading from and writing a seed file to - * Non-Volatile storage (NV) in a platform-independent way - * - * Only enabled when the NV seed entropy source is enabled - */ -#if defined(MBEDTLS_ENTROPY_NV_SEED) -#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO) -/* Internal standard platform definitions */ -int mbedtls_platform_std_nv_seed_read(unsigned char *buf, size_t buf_len); -int mbedtls_platform_std_nv_seed_write(unsigned char *buf, size_t buf_len); -#endif - -#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) -extern int (*mbedtls_nv_seed_read)(unsigned char *buf, size_t buf_len); -extern int (*mbedtls_nv_seed_write)(unsigned char *buf, size_t buf_len); - -/** - * \brief This function allows configuring custom seed file writing and - * reading functions. - * - * \param nv_seed_read_func The seed reading function implementation. - * \param nv_seed_write_func The seed writing function implementation. - * - * \return \c 0 on success. - */ -int mbedtls_platform_set_nv_seed( - int (*nv_seed_read_func)(unsigned char *buf, size_t buf_len), - int (*nv_seed_write_func)(unsigned char *buf, size_t buf_len) - ); -#else -#undef mbedtls_nv_seed_read -#undef mbedtls_nv_seed_write -#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) && \ - defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) -#define mbedtls_nv_seed_read MBEDTLS_PLATFORM_NV_SEED_READ_MACRO -#define mbedtls_nv_seed_write MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO -#else -#define mbedtls_nv_seed_read mbedtls_platform_std_nv_seed_read -#define mbedtls_nv_seed_write mbedtls_platform_std_nv_seed_write -#endif -#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ -#endif /* MBEDTLS_ENTROPY_NV_SEED */ - -#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) - -/** - * \brief The platform context structure. - * - * \note This structure may be used to assist platform-specific - * setup or teardown operations. - */ -typedef struct mbedtls_platform_context { - char MBEDTLS_PRIVATE(dummy); /**< A placeholder member, as empty structs are not portable. */ -} -mbedtls_platform_context; - -#else -#include "platform_alt.h" -#endif /* !MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ - -/** - * \brief This function performs any platform-specific initialization - * operations. - * - * \note This function should be called before any other library functions. - * - * Its implementation is platform-specific, and unless - * platform-specific code is provided, it does nothing. - * - * \note The usage and necessity of this function is dependent on the platform. - * - * \param ctx The platform context. - * - * \return \c 0 on success. - */ -int mbedtls_platform_setup(mbedtls_platform_context *ctx); -/** - * \brief This function performs any platform teardown operations. - * - * \note This function should be called after every other Mbed TLS module - * has been correctly freed using the appropriate free function. - * - * Its implementation is platform-specific, and unless - * platform-specific code is provided, it does nothing. - * - * \note The usage and necessity of this function is dependent on the platform. - * - * \param ctx The platform context. - * - */ -void mbedtls_platform_teardown(mbedtls_platform_context *ctx); - -#ifdef __cplusplus -} -#endif - -#endif /* platform.h */ +/** + * \file platform.h + * + * \brief This file contains the definitions and functions of the + * Mbed TLS platform abstraction layer. + * + * The platform abstraction layer removes the need for the library + * to directly link to standard C library functions or operating + * system services, making the library easier to port and embed. + * Application developers and users of the library can provide their own + * implementations of these functions, or implementations specific to + * their platform, which can be statically linked to the library or + * dynamically configured at runtime. + * + * When all compilation options related to platform abstraction are + * disabled, this header just defines `mbedtls_xxx` function names + * as aliases to the standard `xxx` function. + * + * Most modules in the library and example programs are expected to + * include this header. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PLATFORM_H +#define MBEDTLS_PLATFORM_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#if defined(MBEDTLS_HAVE_TIME) +#include "mbedtls/platform_time.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +/* The older Microsoft Windows common runtime provides non-conforming + * implementations of some standard library functions, including snprintf + * and vsnprintf. This affects MSVC and MinGW builds. + */ +#if defined(__MINGW32__) || (defined(_MSC_VER) && _MSC_VER <= 1900) +#define MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF +#define MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF +#endif + +#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) +#include +#include +#if defined(MBEDTLS_HAVE_TIME) +#include +#endif +#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF) +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) +#define MBEDTLS_PLATFORM_STD_SNPRINTF mbedtls_platform_win32_snprintf /**< The default \c snprintf function to use. */ +#else +#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< The default \c snprintf function to use. */ +#endif +#endif +#if !defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) +#define MBEDTLS_PLATFORM_STD_VSNPRINTF mbedtls_platform_win32_vsnprintf /**< The default \c vsnprintf function to use. */ +#else +#define MBEDTLS_PLATFORM_STD_VSNPRINTF vsnprintf /**< The default \c vsnprintf function to use. */ +#endif +#endif +#if !defined(MBEDTLS_PLATFORM_STD_PRINTF) +#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< The default \c printf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF) +#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< The default \c fprintf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_CALLOC) +#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< The default \c calloc function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_FREE) +#define MBEDTLS_PLATFORM_STD_FREE free /**< The default \c free function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_SETBUF) +#define MBEDTLS_PLATFORM_STD_SETBUF setbuf /**< The default \c setbuf function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT) +#define MBEDTLS_PLATFORM_STD_EXIT exit /**< The default \c exit function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_TIME) +#define MBEDTLS_PLATFORM_STD_TIME time /**< The default \c time function to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) +#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS EXIT_SUCCESS /**< The default exit value to use. */ +#endif +#if !defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) +#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE EXIT_FAILURE /**< The default exit value to use. */ +#endif +#if defined(MBEDTLS_FS_IO) +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) +#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read +#endif +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) +#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write +#endif +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_FILE) +#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" +#endif +#endif /* MBEDTLS_FS_IO */ +#else /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ +#if defined(MBEDTLS_PLATFORM_STD_MEM_HDR) +#include MBEDTLS_PLATFORM_STD_MEM_HDR +#endif +#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ + +/* Enable certain documented defines only when generating doxygen to avoid + * an "unrecognized define" error. */ +#if defined(__DOXYGEN__) && !defined(MBEDTLS_PLATFORM_STD_CALLOC) +#define MBEDTLS_PLATFORM_STD_CALLOC +#endif + +#if defined(__DOXYGEN__) && !defined(MBEDTLS_PLATFORM_STD_FREE) +#define MBEDTLS_PLATFORM_STD_FREE +#endif + +/** \} name SECTION: Module settings */ + +/* + * The function pointers for calloc and free. + * Please see MBEDTLS_PLATFORM_STD_CALLOC and MBEDTLS_PLATFORM_STD_FREE + * in mbedtls_config.h for more information about behaviour and requirements. + */ +#if defined(MBEDTLS_PLATFORM_MEMORY) +#if defined(MBEDTLS_PLATFORM_FREE_MACRO) && \ + defined(MBEDTLS_PLATFORM_CALLOC_MACRO) +#undef mbedtls_free +#undef mbedtls_calloc +#define mbedtls_free MBEDTLS_PLATFORM_FREE_MACRO +#define mbedtls_calloc MBEDTLS_PLATFORM_CALLOC_MACRO +#else +/* For size_t */ +#include +extern void *mbedtls_calloc(size_t n, size_t size); +extern void mbedtls_free(void *ptr); + +/** + * \brief This function dynamically sets the memory-management + * functions used by the library, during runtime. + * + * \param calloc_func The \c calloc function implementation. + * \param free_func The \c free function implementation. + * + * \return \c 0. + */ +int mbedtls_platform_set_calloc_free(void *(*calloc_func)(size_t, size_t), + void (*free_func)(void *)); +#endif /* MBEDTLS_PLATFORM_FREE_MACRO && MBEDTLS_PLATFORM_CALLOC_MACRO */ +#else /* !MBEDTLS_PLATFORM_MEMORY */ +#undef mbedtls_free +#undef mbedtls_calloc +#define mbedtls_free free +#define mbedtls_calloc calloc +#endif /* MBEDTLS_PLATFORM_MEMORY && !MBEDTLS_PLATFORM_{FREE,CALLOC}_MACRO */ + +/* + * The function pointers for fprintf + */ +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) +/* We need FILE * */ +#include +extern int (*mbedtls_fprintf)(FILE *stream, const char *format, ...); + +/** + * \brief This function dynamically configures the fprintf + * function that is called when the + * mbedtls_fprintf() function is invoked by the library. + * + * \param fprintf_func The \c fprintf function implementation. + * + * \return \c 0. + */ +int mbedtls_platform_set_fprintf(int (*fprintf_func)(FILE *stream, const char *, + ...)); +#else +#undef mbedtls_fprintf +#if defined(MBEDTLS_PLATFORM_FPRINTF_MACRO) +#define mbedtls_fprintf MBEDTLS_PLATFORM_FPRINTF_MACRO +#else +#define mbedtls_fprintf fprintf +#endif /* MBEDTLS_PLATFORM_FPRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ + +/* + * The function pointers for printf + */ +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) +extern int (*mbedtls_printf)(const char *format, ...); + +/** + * \brief This function dynamically configures the snprintf + * function that is called when the mbedtls_snprintf() + * function is invoked by the library. + * + * \param printf_func The \c printf function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_printf(int (*printf_func)(const char *, ...)); +#else /* !MBEDTLS_PLATFORM_PRINTF_ALT */ +#undef mbedtls_printf +#if defined(MBEDTLS_PLATFORM_PRINTF_MACRO) +#define mbedtls_printf MBEDTLS_PLATFORM_PRINTF_MACRO +#else +#define mbedtls_printf printf +#endif /* MBEDTLS_PLATFORM_PRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ + +/* + * The function pointers for snprintf + * + * The snprintf implementation should conform to C99: + * - it *must* always correctly zero-terminate the buffer + * (except when n == 0, then it must leave the buffer untouched) + * - however it is acceptable to return -1 instead of the required length when + * the destination buffer is too short. + */ +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) +/* For Windows (inc. MSYS2), we provide our own fixed implementation */ +int mbedtls_platform_win32_snprintf(char *s, size_t n, const char *fmt, ...); +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) +extern int (*mbedtls_snprintf)(char *s, size_t n, const char *format, ...); + +/** + * \brief This function allows configuring a custom + * \c snprintf function pointer. + * + * \param snprintf_func The \c snprintf function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_snprintf(int (*snprintf_func)(char *s, size_t n, + const char *format, ...)); +#else /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ +#undef mbedtls_snprintf +#if defined(MBEDTLS_PLATFORM_SNPRINTF_MACRO) +#define mbedtls_snprintf MBEDTLS_PLATFORM_SNPRINTF_MACRO +#else +#define mbedtls_snprintf MBEDTLS_PLATFORM_STD_SNPRINTF +#endif /* MBEDTLS_PLATFORM_SNPRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ + +/* + * The function pointers for vsnprintf + * + * The vsnprintf implementation should conform to C99: + * - it *must* always correctly zero-terminate the buffer + * (except when n == 0, then it must leave the buffer untouched) + * - however it is acceptable to return -1 instead of the required length when + * the destination buffer is too short. + */ +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) +#include +/* For Older Windows (inc. MSYS2), we provide our own fixed implementation */ +int mbedtls_platform_win32_vsnprintf(char *s, size_t n, const char *fmt, va_list arg); +#endif + +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) +#include +extern int (*mbedtls_vsnprintf)(char *s, size_t n, const char *format, va_list arg); + +/** + * \brief Set your own snprintf function pointer + * + * \param vsnprintf_func The \c vsnprintf function implementation + * + * \return \c 0 + */ +int mbedtls_platform_set_vsnprintf(int (*vsnprintf_func)(char *s, size_t n, + const char *format, va_list arg)); +#else /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ +#undef mbedtls_vsnprintf +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_MACRO) +#define mbedtls_vsnprintf MBEDTLS_PLATFORM_VSNPRINTF_MACRO +#else +#define mbedtls_vsnprintf vsnprintf +#endif /* MBEDTLS_PLATFORM_VSNPRINTF_MACRO */ +#endif /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ + +/* + * The function pointers for setbuf + */ +#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) +#include +/** + * \brief Function pointer to call for `setbuf()` functionality + * (changing the internal buffering on stdio calls). + * + * \note The library calls this function to disable + * buffering when reading or writing sensitive data, + * to avoid having extra copies of sensitive data + * remaining in stdio buffers after the file is + * closed. If this is not a concern, for example if + * your platform's stdio doesn't have any buffering, + * you can set mbedtls_setbuf to a function that + * does nothing. + * + * The library always calls this function with + * `buf` equal to `NULL`. + */ +extern void (*mbedtls_setbuf)(FILE *stream, char *buf); + +/** + * \brief Dynamically configure the function that is called + * when the mbedtls_setbuf() function is called by the + * library. + * + * \param setbuf_func The \c setbuf function implementation + * + * \return \c 0 + */ +int mbedtls_platform_set_setbuf(void (*setbuf_func)( + FILE *stream, char *buf)); +#else +#undef mbedtls_setbuf +#if defined(MBEDTLS_PLATFORM_SETBUF_MACRO) +/** + * \brief Macro defining the function for the library to + * call for `setbuf` functionality (changing the + * internal buffering on stdio calls). + * + * \note See extra comments on the mbedtls_setbuf() function + * pointer above. + * + * \return \c 0 on success, negative on error. + */ +#define mbedtls_setbuf MBEDTLS_PLATFORM_SETBUF_MACRO +#else +#define mbedtls_setbuf setbuf +#endif /* MBEDTLS_PLATFORM_SETBUF_MACRO */ +#endif /* MBEDTLS_PLATFORM_SETBUF_ALT */ + +/* + * The function pointers for exit + */ +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) +extern void (*mbedtls_exit)(int status); + +/** + * \brief This function dynamically configures the exit + * function that is called when the mbedtls_exit() + * function is invoked by the library. + * + * \param exit_func The \c exit function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_exit(void (*exit_func)(int status)); +#else +#undef mbedtls_exit +#if defined(MBEDTLS_PLATFORM_EXIT_MACRO) +#define mbedtls_exit MBEDTLS_PLATFORM_EXIT_MACRO +#else +#define mbedtls_exit exit +#endif /* MBEDTLS_PLATFORM_EXIT_MACRO */ +#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ + +/* + * The default exit values + */ +#if defined(MBEDTLS_PLATFORM_STD_EXIT_SUCCESS) +#define MBEDTLS_EXIT_SUCCESS MBEDTLS_PLATFORM_STD_EXIT_SUCCESS +#else +#define MBEDTLS_EXIT_SUCCESS 0 +#endif +#if defined(MBEDTLS_PLATFORM_STD_EXIT_FAILURE) +#define MBEDTLS_EXIT_FAILURE MBEDTLS_PLATFORM_STD_EXIT_FAILURE +#else +#define MBEDTLS_EXIT_FAILURE 1 +#endif + +/* + * The function pointers for reading from and writing a seed file to + * Non-Volatile storage (NV) in a platform-independent way + * + * Only enabled when the NV seed entropy source is enabled + */ +#if defined(MBEDTLS_ENTROPY_NV_SEED) +#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO) +/* Internal standard platform definitions */ +int mbedtls_platform_std_nv_seed_read(unsigned char *buf, size_t buf_len); +int mbedtls_platform_std_nv_seed_write(unsigned char *buf, size_t buf_len); +#endif + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +extern int (*mbedtls_nv_seed_read)(unsigned char *buf, size_t buf_len); +extern int (*mbedtls_nv_seed_write)(unsigned char *buf, size_t buf_len); + +/** + * \brief This function allows configuring custom seed file writing and + * reading functions. + * + * \param nv_seed_read_func The seed reading function implementation. + * \param nv_seed_write_func The seed writing function implementation. + * + * \return \c 0 on success. + */ +int mbedtls_platform_set_nv_seed( + int (*nv_seed_read_func)(unsigned char *buf, size_t buf_len), + int (*nv_seed_write_func)(unsigned char *buf, size_t buf_len) + ); +#else +#undef mbedtls_nv_seed_read +#undef mbedtls_nv_seed_write +#if defined(MBEDTLS_PLATFORM_NV_SEED_READ_MACRO) && \ + defined(MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO) +#define mbedtls_nv_seed_read MBEDTLS_PLATFORM_NV_SEED_READ_MACRO +#define mbedtls_nv_seed_write MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO +#else +#define mbedtls_nv_seed_read mbedtls_platform_std_nv_seed_read +#define mbedtls_nv_seed_write mbedtls_platform_std_nv_seed_write +#endif +#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ +#endif /* MBEDTLS_ENTROPY_NV_SEED */ + +#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) + +/** + * \brief The platform context structure. + * + * \note This structure may be used to assist platform-specific + * setup or teardown operations. + */ +typedef struct mbedtls_platform_context { + char MBEDTLS_PRIVATE(dummy); /**< A placeholder member, as empty structs are not portable. */ +} +mbedtls_platform_context; + +#else +#include "platform_alt.h" +#endif /* !MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ + +/** + * \brief This function performs any platform-specific initialization + * operations. + * + * \note This function should be called before any other library functions. + * + * Its implementation is platform-specific, and unless + * platform-specific code is provided, it does nothing. + * + * \note The usage and necessity of this function is dependent on the platform. + * + * \param ctx The platform context. + * + * \return \c 0 on success. + */ +int mbedtls_platform_setup(mbedtls_platform_context *ctx); +/** + * \brief This function performs any platform teardown operations. + * + * \note This function should be called after every other Mbed TLS module + * has been correctly freed using the appropriate free function. + * + * Its implementation is platform-specific, and unless + * platform-specific code is provided, it does nothing. + * + * \note The usage and necessity of this function is dependent on the platform. + * + * \param ctx The platform context. + * + */ +void mbedtls_platform_teardown(mbedtls_platform_context *ctx); + +#ifdef __cplusplus +} +#endif + +#endif /* platform.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_time.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_time.h index 21b3697..a8b9bfe 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_time.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_time.h @@ -1,91 +1,91 @@ -/** - * \file platform_time.h - * - * \brief Mbed TLS Platform time abstraction - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PLATFORM_TIME_H -#define MBEDTLS_PLATFORM_TIME_H - -#include "mbedtls/build_info.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The time_t datatype - */ -#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) -typedef MBEDTLS_PLATFORM_TIME_TYPE_MACRO mbedtls_time_t; -#else -/* For time_t */ -#include -typedef time_t mbedtls_time_t; -#endif /* MBEDTLS_PLATFORM_TIME_TYPE_MACRO */ - -#if defined(MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO) -typedef MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO mbedtls_ms_time_t; -#else -#include -#include -typedef int64_t mbedtls_ms_time_t; -#endif /* MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO */ - -/** - * \brief Get time in milliseconds. - * - * \return Monotonically-increasing current time in milliseconds. - * - * \note Define MBEDTLS_PLATFORM_MS_TIME_ALT to be able to provide an - * alternative implementation - * - * \warning This function returns a monotonically-increasing time value from a - * start time that will differ from platform to platform, and possibly - * from run to run of the process. - * - */ -mbedtls_ms_time_t mbedtls_ms_time(void); - -/* - * The function pointers for time - */ -#if defined(MBEDTLS_PLATFORM_TIME_ALT) -extern mbedtls_time_t (*mbedtls_time)(mbedtls_time_t *time); - -/** - * \brief Set your own time function pointer - * - * \param time_func the time function implementation - * - * \return 0 - */ -int mbedtls_platform_set_time(mbedtls_time_t (*time_func)(mbedtls_time_t *time)); -#else -#if defined(MBEDTLS_PLATFORM_TIME_MACRO) -#define mbedtls_time MBEDTLS_PLATFORM_TIME_MACRO -#else -#define mbedtls_time time -#endif /* MBEDTLS_PLATFORM_TIME_MACRO */ -#endif /* MBEDTLS_PLATFORM_TIME_ALT */ - -#ifdef __cplusplus -} -#endif - -#endif /* platform_time.h */ +/** + * \file platform_time.h + * + * \brief Mbed TLS Platform time abstraction + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PLATFORM_TIME_H +#define MBEDTLS_PLATFORM_TIME_H + +#include "mbedtls/build_info.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The time_t datatype + */ +#if defined(MBEDTLS_PLATFORM_TIME_TYPE_MACRO) +typedef MBEDTLS_PLATFORM_TIME_TYPE_MACRO mbedtls_time_t; +#else +/* For time_t */ +#include +typedef time_t mbedtls_time_t; +#endif /* MBEDTLS_PLATFORM_TIME_TYPE_MACRO */ + +#if defined(MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO) +typedef MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO mbedtls_ms_time_t; +#else +#include +#include +typedef int64_t mbedtls_ms_time_t; +#endif /* MBEDTLS_PLATFORM_MS_TIME_TYPE_MACRO */ + +/** + * \brief Get time in milliseconds. + * + * \return Monotonically-increasing current time in milliseconds. + * + * \note Define MBEDTLS_PLATFORM_MS_TIME_ALT to be able to provide an + * alternative implementation + * + * \warning This function returns a monotonically-increasing time value from a + * start time that will differ from platform to platform, and possibly + * from run to run of the process. + * + */ +mbedtls_ms_time_t mbedtls_ms_time(void); + +/* + * The function pointers for time + */ +#if defined(MBEDTLS_PLATFORM_TIME_ALT) +extern mbedtls_time_t (*mbedtls_time)(mbedtls_time_t *time); + +/** + * \brief Set your own time function pointer + * + * \param time_func the time function implementation + * + * \return 0 + */ +int mbedtls_platform_set_time(mbedtls_time_t (*time_func)(mbedtls_time_t *time)); +#else +#if defined(MBEDTLS_PLATFORM_TIME_MACRO) +#define mbedtls_time MBEDTLS_PLATFORM_TIME_MACRO +#else +#define mbedtls_time time +#endif /* MBEDTLS_PLATFORM_TIME_MACRO */ +#endif /* MBEDTLS_PLATFORM_TIME_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* platform_time.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_util.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_util.h index 3f23fef..58e518c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_util.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/platform_util.h @@ -1,213 +1,213 @@ -/** - * \file platform_util.h - * - * \brief Common and shared functions used by multiple modules in the Mbed TLS - * library. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PLATFORM_UTIL_H -#define MBEDTLS_PLATFORM_UTIL_H - -#include "mbedtls/build_info.h" - -#include -#if defined(MBEDTLS_HAVE_TIME_DATE) -#include "mbedtls/platform_time.h" -#include -#endif /* MBEDTLS_HAVE_TIME_DATE */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Internal macros meant to be called only from within the library. */ -#define MBEDTLS_INTERNAL_VALIDATE_RET(cond, ret) do { } while (0) -#define MBEDTLS_INTERNAL_VALIDATE(cond) do { } while (0) - -/* Internal helper macros for deprecating API constants. */ -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -#if defined(MBEDTLS_DEPRECATED_WARNING) -#define MBEDTLS_DEPRECATED __attribute__((deprecated)) -MBEDTLS_DEPRECATED typedef char const *mbedtls_deprecated_string_constant_t; -#define MBEDTLS_DEPRECATED_STRING_CONSTANT(VAL) \ - ((mbedtls_deprecated_string_constant_t) (VAL)) -MBEDTLS_DEPRECATED typedef int mbedtls_deprecated_numeric_constant_t; -#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(VAL) \ - ((mbedtls_deprecated_numeric_constant_t) (VAL)) -#else /* MBEDTLS_DEPRECATED_WARNING */ -#define MBEDTLS_DEPRECATED -#define MBEDTLS_DEPRECATED_STRING_CONSTANT(VAL) VAL -#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(VAL) VAL -#endif /* MBEDTLS_DEPRECATED_WARNING */ -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -/* Implementation of the check-return facility. - * See the user documentation in mbedtls_config.h. - * - * Do not use this macro directly to annotate function: instead, - * use one of MBEDTLS_CHECK_RETURN_CRITICAL or MBEDTLS_CHECK_RETURN_TYPICAL - * depending on how important it is to check the return value. - */ -#if !defined(MBEDTLS_CHECK_RETURN) -#if defined(__GNUC__) -#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) -#elif defined(_MSC_VER) && _MSC_VER >= 1700 -#include -#define MBEDTLS_CHECK_RETURN _Check_return_ -#else -#define MBEDTLS_CHECK_RETURN -#endif -#endif - -/** Critical-failure function - * - * This macro appearing at the beginning of the declaration of a function - * indicates that its return value should be checked in all applications. - * Omitting the check is very likely to indicate a bug in the application - * and will result in a compile-time warning if #MBEDTLS_CHECK_RETURN - * is implemented for the compiler in use. - * - * \note The use of this macro is a work in progress. - * This macro may be added to more functions in the future. - * Such an extension is not considered an API break, provided that - * there are near-unavoidable circumstances under which the function - * can fail. For example, signature/MAC/AEAD verification functions, - * and functions that require a random generator, are considered - * return-check-critical. - */ -#define MBEDTLS_CHECK_RETURN_CRITICAL MBEDTLS_CHECK_RETURN - -/** Ordinary-failure function - * - * This macro appearing at the beginning of the declaration of a function - * indicates that its return value should be generally be checked in portable - * applications. Omitting the check will result in a compile-time warning if - * #MBEDTLS_CHECK_RETURN is implemented for the compiler in use and - * #MBEDTLS_CHECK_RETURN_WARNING is enabled in the compile-time configuration. - * - * You can use #MBEDTLS_IGNORE_RETURN to explicitly ignore the return value - * of a function that is annotated with #MBEDTLS_CHECK_RETURN. - * - * \note The use of this macro is a work in progress. - * This macro will be added to more functions in the future. - * Eventually this should appear before most functions returning - * an error code (as \c int in the \c mbedtls_xxx API or - * as ::psa_status_t in the \c psa_xxx API). - */ -#if defined(MBEDTLS_CHECK_RETURN_WARNING) -#define MBEDTLS_CHECK_RETURN_TYPICAL MBEDTLS_CHECK_RETURN -#else -#define MBEDTLS_CHECK_RETURN_TYPICAL -#endif - -/** Benign-failure function - * - * This macro appearing at the beginning of the declaration of a function - * indicates that it is rarely useful to check its return value. - * - * This macro has an empty expansion. It exists for documentation purposes: - * a #MBEDTLS_CHECK_RETURN_OPTIONAL annotation indicates that the function - * has been analyzed for return-check usefulness, whereas the lack of - * an annotation indicates that the function has not been analyzed and its - * return-check usefulness is unknown. - */ -#define MBEDTLS_CHECK_RETURN_OPTIONAL - -/** \def MBEDTLS_IGNORE_RETURN - * - * Call this macro with one argument, a function call, to suppress a warning - * from #MBEDTLS_CHECK_RETURN due to that function call. - */ -#if !defined(MBEDTLS_IGNORE_RETURN) -/* GCC doesn't silence the warning with just (void)(result). - * (void)!(result) is known to work up at least up to GCC 10, as well - * as with Clang and MSVC. - * - * https://gcc.gnu.org/onlinedocs/gcc-3.4.6/gcc/Non_002dbugs.html - * https://stackoverflow.com/questions/40576003/ignoring-warning-wunused-result - * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66425#c34 - */ -#define MBEDTLS_IGNORE_RETURN(result) ((void) !(result)) -#endif - -/* If the following macro is defined, the library is being built by the test - * framework, and the framework is going to provide a replacement - * mbedtls_platform_zeroize() using a preprocessor macro, so the function - * declaration should be omitted. */ -#if !defined(MBEDTLS_TEST_DEFINES_ZEROIZE) //no-check-names -/** - * \brief Securely zeroize a buffer - * - * The function is meant to wipe the data contained in a buffer so - * that it can no longer be recovered even if the program memory - * is later compromised. Call this function on sensitive data - * stored on the stack before returning from a function, and on - * sensitive data stored on the heap before freeing the heap - * object. - * - * It is extremely difficult to guarantee that calls to - * mbedtls_platform_zeroize() are not removed by aggressive - * compiler optimizations in a portable way. For this reason, Mbed - * TLS provides the configuration option - * MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure - * mbedtls_platform_zeroize() to use a suitable implementation for - * their platform and needs - * - * \param buf Buffer to be zeroized - * \param len Length of the buffer in bytes - * - */ -void mbedtls_platform_zeroize(void *buf, size_t len); -#endif - -#if defined(MBEDTLS_HAVE_TIME_DATE) -/** - * \brief Platform-specific implementation of gmtime_r() - * - * The function is a thread-safe abstraction that behaves - * similarly to the gmtime_r() function from Unix/POSIX. - * - * Mbed TLS will try to identify the underlying platform and - * make use of an appropriate underlying implementation (e.g. - * gmtime_r() for POSIX and gmtime_s() for Windows). If this is - * not possible, then gmtime() will be used. In this case, calls - * from the library to gmtime() will be guarded by the mutex - * mbedtls_threading_gmtime_mutex if MBEDTLS_THREADING_C is - * enabled. It is recommended that calls from outside the library - * are also guarded by this mutex. - * - * If MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, then Mbed TLS will - * unconditionally use the alternative implementation for - * mbedtls_platform_gmtime_r() supplied by the user at compile time. - * - * \param tt Pointer to an object containing time (in seconds) since the - * epoch to be converted - * \param tm_buf Pointer to an object where the results will be stored - * - * \return Pointer to an object of type struct tm on success, otherwise - * NULL - */ -struct tm *mbedtls_platform_gmtime_r(const mbedtls_time_t *tt, - struct tm *tm_buf); -#endif /* MBEDTLS_HAVE_TIME_DATE */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_PLATFORM_UTIL_H */ +/** + * \file platform_util.h + * + * \brief Common and shared functions used by multiple modules in the Mbed TLS + * library. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PLATFORM_UTIL_H +#define MBEDTLS_PLATFORM_UTIL_H + +#include "mbedtls/build_info.h" + +#include +#if defined(MBEDTLS_HAVE_TIME_DATE) +#include "mbedtls/platform_time.h" +#include +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Internal macros meant to be called only from within the library. */ +#define MBEDTLS_INTERNAL_VALIDATE_RET(cond, ret) do { } while (0) +#define MBEDTLS_INTERNAL_VALIDATE(cond) do { } while (0) + +/* Internal helper macros for deprecating API constants. */ +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +MBEDTLS_DEPRECATED typedef char const *mbedtls_deprecated_string_constant_t; +#define MBEDTLS_DEPRECATED_STRING_CONSTANT(VAL) \ + ((mbedtls_deprecated_string_constant_t) (VAL)) +MBEDTLS_DEPRECATED typedef int mbedtls_deprecated_numeric_constant_t; +#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(VAL) \ + ((mbedtls_deprecated_numeric_constant_t) (VAL)) +#else /* MBEDTLS_DEPRECATED_WARNING */ +#define MBEDTLS_DEPRECATED +#define MBEDTLS_DEPRECATED_STRING_CONSTANT(VAL) VAL +#define MBEDTLS_DEPRECATED_NUMERIC_CONSTANT(VAL) VAL +#endif /* MBEDTLS_DEPRECATED_WARNING */ +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/* Implementation of the check-return facility. + * See the user documentation in mbedtls_config.h. + * + * Do not use this macro directly to annotate function: instead, + * use one of MBEDTLS_CHECK_RETURN_CRITICAL or MBEDTLS_CHECK_RETURN_TYPICAL + * depending on how important it is to check the return value. + */ +#if !defined(MBEDTLS_CHECK_RETURN) +#if defined(__GNUC__) +#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) +#elif defined(_MSC_VER) && _MSC_VER >= 1700 +#include +#define MBEDTLS_CHECK_RETURN _Check_return_ +#else +#define MBEDTLS_CHECK_RETURN +#endif +#endif + +/** Critical-failure function + * + * This macro appearing at the beginning of the declaration of a function + * indicates that its return value should be checked in all applications. + * Omitting the check is very likely to indicate a bug in the application + * and will result in a compile-time warning if #MBEDTLS_CHECK_RETURN + * is implemented for the compiler in use. + * + * \note The use of this macro is a work in progress. + * This macro may be added to more functions in the future. + * Such an extension is not considered an API break, provided that + * there are near-unavoidable circumstances under which the function + * can fail. For example, signature/MAC/AEAD verification functions, + * and functions that require a random generator, are considered + * return-check-critical. + */ +#define MBEDTLS_CHECK_RETURN_CRITICAL MBEDTLS_CHECK_RETURN + +/** Ordinary-failure function + * + * This macro appearing at the beginning of the declaration of a function + * indicates that its return value should be generally be checked in portable + * applications. Omitting the check will result in a compile-time warning if + * #MBEDTLS_CHECK_RETURN is implemented for the compiler in use and + * #MBEDTLS_CHECK_RETURN_WARNING is enabled in the compile-time configuration. + * + * You can use #MBEDTLS_IGNORE_RETURN to explicitly ignore the return value + * of a function that is annotated with #MBEDTLS_CHECK_RETURN. + * + * \note The use of this macro is a work in progress. + * This macro will be added to more functions in the future. + * Eventually this should appear before most functions returning + * an error code (as \c int in the \c mbedtls_xxx API or + * as ::psa_status_t in the \c psa_xxx API). + */ +#if defined(MBEDTLS_CHECK_RETURN_WARNING) +#define MBEDTLS_CHECK_RETURN_TYPICAL MBEDTLS_CHECK_RETURN +#else +#define MBEDTLS_CHECK_RETURN_TYPICAL +#endif + +/** Benign-failure function + * + * This macro appearing at the beginning of the declaration of a function + * indicates that it is rarely useful to check its return value. + * + * This macro has an empty expansion. It exists for documentation purposes: + * a #MBEDTLS_CHECK_RETURN_OPTIONAL annotation indicates that the function + * has been analyzed for return-check usefulness, whereas the lack of + * an annotation indicates that the function has not been analyzed and its + * return-check usefulness is unknown. + */ +#define MBEDTLS_CHECK_RETURN_OPTIONAL + +/** \def MBEDTLS_IGNORE_RETURN + * + * Call this macro with one argument, a function call, to suppress a warning + * from #MBEDTLS_CHECK_RETURN due to that function call. + */ +#if !defined(MBEDTLS_IGNORE_RETURN) +/* GCC doesn't silence the warning with just (void)(result). + * (void)!(result) is known to work up at least up to GCC 10, as well + * as with Clang and MSVC. + * + * https://gcc.gnu.org/onlinedocs/gcc-3.4.6/gcc/Non_002dbugs.html + * https://stackoverflow.com/questions/40576003/ignoring-warning-wunused-result + * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66425#c34 + */ +#define MBEDTLS_IGNORE_RETURN(result) ((void) !(result)) +#endif + +/* If the following macro is defined, the library is being built by the test + * framework, and the framework is going to provide a replacement + * mbedtls_platform_zeroize() using a preprocessor macro, so the function + * declaration should be omitted. */ +#if !defined(MBEDTLS_TEST_DEFINES_ZEROIZE) //no-check-names +/** + * \brief Securely zeroize a buffer + * + * The function is meant to wipe the data contained in a buffer so + * that it can no longer be recovered even if the program memory + * is later compromised. Call this function on sensitive data + * stored on the stack before returning from a function, and on + * sensitive data stored on the heap before freeing the heap + * object. + * + * It is extremely difficult to guarantee that calls to + * mbedtls_platform_zeroize() are not removed by aggressive + * compiler optimizations in a portable way. For this reason, Mbed + * TLS provides the configuration option + * MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure + * mbedtls_platform_zeroize() to use a suitable implementation for + * their platform and needs + * + * \param buf Buffer to be zeroized + * \param len Length of the buffer in bytes + * + */ +void mbedtls_platform_zeroize(void *buf, size_t len); +#endif + +#if defined(MBEDTLS_HAVE_TIME_DATE) +/** + * \brief Platform-specific implementation of gmtime_r() + * + * The function is a thread-safe abstraction that behaves + * similarly to the gmtime_r() function from Unix/POSIX. + * + * Mbed TLS will try to identify the underlying platform and + * make use of an appropriate underlying implementation (e.g. + * gmtime_r() for POSIX and gmtime_s() for Windows). If this is + * not possible, then gmtime() will be used. In this case, calls + * from the library to gmtime() will be guarded by the mutex + * mbedtls_threading_gmtime_mutex if MBEDTLS_THREADING_C is + * enabled. It is recommended that calls from outside the library + * are also guarded by this mutex. + * + * If MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, then Mbed TLS will + * unconditionally use the alternative implementation for + * mbedtls_platform_gmtime_r() supplied by the user at compile time. + * + * \param tt Pointer to an object containing time (in seconds) since the + * epoch to be converted + * \param tm_buf Pointer to an object where the results will be stored + * + * \return Pointer to an object of type struct tm on success, otherwise + * NULL + */ +struct tm *mbedtls_platform_gmtime_r(const mbedtls_time_t *tt, + struct tm *tm_buf); +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_PLATFORM_UTIL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/poly1305.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/poly1305.h index 3025ef1..adf2949 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/poly1305.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/poly1305.h @@ -1,180 +1,180 @@ -/** - * \file poly1305.h - * - * \brief This file contains Poly1305 definitions and functions. - * - * Poly1305 is a one-time message authenticator that can be used to - * authenticate messages. Poly1305-AES was created by Daniel - * Bernstein https://cr.yp.to/mac/poly1305-20050329.pdf The generic - * Poly1305 algorithm (not tied to AES) was also standardized in RFC - * 7539. - * - * \author Daniel King - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_POLY1305_H -#define MBEDTLS_POLY1305_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -/** Invalid input parameter(s). */ -#define MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA -0x0057 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_POLY1305_ALT) - -typedef struct mbedtls_poly1305_context { - uint32_t MBEDTLS_PRIVATE(r)[4]; /** The value for 'r' (low 128 bits of the key). */ - uint32_t MBEDTLS_PRIVATE(s)[4]; /** The value for 's' (high 128 bits of the key). */ - uint32_t MBEDTLS_PRIVATE(acc)[5]; /** The accumulator number. */ - uint8_t MBEDTLS_PRIVATE(queue)[16]; /** The current partial block of data. */ - size_t MBEDTLS_PRIVATE(queue_len); /** The number of bytes stored in 'queue'. */ -} -mbedtls_poly1305_context; - -#else /* MBEDTLS_POLY1305_ALT */ -#include "poly1305_alt.h" -#endif /* MBEDTLS_POLY1305_ALT */ - -/** - * \brief This function initializes the specified Poly1305 context. - * - * It must be the first API called before using - * the context. - * - * It is usually followed by a call to - * \c mbedtls_poly1305_starts(), then one or more calls to - * \c mbedtls_poly1305_update(), then one call to - * \c mbedtls_poly1305_finish(), then finally - * \c mbedtls_poly1305_free(). - * - * \param ctx The Poly1305 context to initialize. This must - * not be \c NULL. - */ -void mbedtls_poly1305_init(mbedtls_poly1305_context *ctx); - -/** - * \brief This function releases and clears the specified - * Poly1305 context. - * - * \param ctx The Poly1305 context to clear. This may be \c NULL, in which - * case this function is a no-op. If it is not \c NULL, it must - * point to an initialized Poly1305 context. - */ -void mbedtls_poly1305_free(mbedtls_poly1305_context *ctx); - -/** - * \brief This function sets the one-time authentication key. - * - * \warning The key must be unique and unpredictable for each - * invocation of Poly1305. - * - * \param ctx The Poly1305 context to which the key should be bound. - * This must be initialized. - * \param key The buffer containing the \c 32 Byte (\c 256 Bit) key. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_poly1305_starts(mbedtls_poly1305_context *ctx, - const unsigned char key[32]); - -/** - * \brief This functions feeds an input buffer into an ongoing - * Poly1305 computation. - * - * It is called between \c mbedtls_cipher_poly1305_starts() and - * \c mbedtls_cipher_poly1305_finish(). - * It can be called repeatedly to process a stream of data. - * - * \param ctx The Poly1305 context to use for the Poly1305 operation. - * This must be initialized and bound to a key. - * \param ilen The length of the input data in Bytes. - * Any value is accepted. - * \param input The buffer holding the input data. - * This pointer can be \c NULL if `ilen == 0`. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_poly1305_update(mbedtls_poly1305_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief This function generates the Poly1305 Message - * Authentication Code (MAC). - * - * \param ctx The Poly1305 context to use for the Poly1305 operation. - * This must be initialized and bound to a key. - * \param mac The buffer to where the MAC is written. This must - * be a writable buffer of length \c 16 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_poly1305_finish(mbedtls_poly1305_context *ctx, - unsigned char mac[16]); - -/** - * \brief This function calculates the Poly1305 MAC of the input - * buffer with the provided key. - * - * \warning The key must be unique and unpredictable for each - * invocation of Poly1305. - * - * \param key The buffer containing the \c 32 Byte (\c 256 Bit) key. - * \param ilen The length of the input data in Bytes. - * Any value is accepted. - * \param input The buffer holding the input data. - * This pointer can be \c NULL if `ilen == 0`. - * \param mac The buffer to where the MAC is written. This must be - * a writable buffer of length \c 16 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_poly1305_mac(const unsigned char key[32], - const unsigned char *input, - size_t ilen, - unsigned char mac[16]); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief The Poly1305 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_poly1305_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_POLY1305_H */ +/** + * \file poly1305.h + * + * \brief This file contains Poly1305 definitions and functions. + * + * Poly1305 is a one-time message authenticator that can be used to + * authenticate messages. Poly1305-AES was created by Daniel + * Bernstein https://cr.yp.to/mac/poly1305-20050329.pdf The generic + * Poly1305 algorithm (not tied to AES) was also standardized in RFC + * 7539. + * + * \author Daniel King + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_POLY1305_H +#define MBEDTLS_POLY1305_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +/** Invalid input parameter(s). */ +#define MBEDTLS_ERR_POLY1305_BAD_INPUT_DATA -0x0057 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_POLY1305_ALT) + +typedef struct mbedtls_poly1305_context { + uint32_t MBEDTLS_PRIVATE(r)[4]; /** The value for 'r' (low 128 bits of the key). */ + uint32_t MBEDTLS_PRIVATE(s)[4]; /** The value for 's' (high 128 bits of the key). */ + uint32_t MBEDTLS_PRIVATE(acc)[5]; /** The accumulator number. */ + uint8_t MBEDTLS_PRIVATE(queue)[16]; /** The current partial block of data. */ + size_t MBEDTLS_PRIVATE(queue_len); /** The number of bytes stored in 'queue'. */ +} +mbedtls_poly1305_context; + +#else /* MBEDTLS_POLY1305_ALT */ +#include "poly1305_alt.h" +#endif /* MBEDTLS_POLY1305_ALT */ + +/** + * \brief This function initializes the specified Poly1305 context. + * + * It must be the first API called before using + * the context. + * + * It is usually followed by a call to + * \c mbedtls_poly1305_starts(), then one or more calls to + * \c mbedtls_poly1305_update(), then one call to + * \c mbedtls_poly1305_finish(), then finally + * \c mbedtls_poly1305_free(). + * + * \param ctx The Poly1305 context to initialize. This must + * not be \c NULL. + */ +void mbedtls_poly1305_init(mbedtls_poly1305_context *ctx); + +/** + * \brief This function releases and clears the specified + * Poly1305 context. + * + * \param ctx The Poly1305 context to clear. This may be \c NULL, in which + * case this function is a no-op. If it is not \c NULL, it must + * point to an initialized Poly1305 context. + */ +void mbedtls_poly1305_free(mbedtls_poly1305_context *ctx); + +/** + * \brief This function sets the one-time authentication key. + * + * \warning The key must be unique and unpredictable for each + * invocation of Poly1305. + * + * \param ctx The Poly1305 context to which the key should be bound. + * This must be initialized. + * \param key The buffer containing the \c 32 Byte (\c 256 Bit) key. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_poly1305_starts(mbedtls_poly1305_context *ctx, + const unsigned char key[32]); + +/** + * \brief This functions feeds an input buffer into an ongoing + * Poly1305 computation. + * + * It is called between \c mbedtls_cipher_poly1305_starts() and + * \c mbedtls_cipher_poly1305_finish(). + * It can be called repeatedly to process a stream of data. + * + * \param ctx The Poly1305 context to use for the Poly1305 operation. + * This must be initialized and bound to a key. + * \param ilen The length of the input data in Bytes. + * Any value is accepted. + * \param input The buffer holding the input data. + * This pointer can be \c NULL if `ilen == 0`. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_poly1305_update(mbedtls_poly1305_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief This function generates the Poly1305 Message + * Authentication Code (MAC). + * + * \param ctx The Poly1305 context to use for the Poly1305 operation. + * This must be initialized and bound to a key. + * \param mac The buffer to where the MAC is written. This must + * be a writable buffer of length \c 16 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_poly1305_finish(mbedtls_poly1305_context *ctx, + unsigned char mac[16]); + +/** + * \brief This function calculates the Poly1305 MAC of the input + * buffer with the provided key. + * + * \warning The key must be unique and unpredictable for each + * invocation of Poly1305. + * + * \param key The buffer containing the \c 32 Byte (\c 256 Bit) key. + * \param ilen The length of the input data in Bytes. + * Any value is accepted. + * \param input The buffer holding the input data. + * This pointer can be \c NULL if `ilen == 0`. + * \param mac The buffer to where the MAC is written. This must be + * a writable buffer of length \c 16 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_poly1305_mac(const unsigned char key[32], + const unsigned char *input, + size_t ilen, + unsigned char mac[16]); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief The Poly1305 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_poly1305_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_POLY1305_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/private_access.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/private_access.h index 61fa877..bb8c1a9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/private_access.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/private_access.h @@ -1,32 +1,32 @@ -/** - * \file private_access.h - * - * \brief Macro wrapper for struct's members. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PRIVATE_ACCESS_H -#define MBEDTLS_PRIVATE_ACCESS_H - -#ifndef MBEDTLS_ALLOW_PRIVATE_ACCESS -#define MBEDTLS_PRIVATE(member) private_##member -#else -#define MBEDTLS_PRIVATE(member) member -#endif - -#endif /* MBEDTLS_PRIVATE_ACCESS_H */ +/** + * \file private_access.h + * + * \brief Macro wrapper for struct's members. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PRIVATE_ACCESS_H +#define MBEDTLS_PRIVATE_ACCESS_H + +#ifndef MBEDTLS_ALLOW_PRIVATE_ACCESS +#define MBEDTLS_PRIVATE(member) private_##member +#else +#define MBEDTLS_PRIVATE(member) member +#endif + +#endif /* MBEDTLS_PRIVATE_ACCESS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/psa_util.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/psa_util.h index 8ce1592..598eb65 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/psa_util.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/psa_util.h @@ -1,116 +1,116 @@ -/** - * \file psa_util.h - * - * \brief Utility functions for the use of the PSA Crypto library. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PSA_UTIL_H -#define MBEDTLS_PSA_UTIL_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -/* Expose whatever RNG the PSA subsystem uses to applications using the - * mbedtls_xxx API. The declarations and definitions here need to be - * consistent with the implementation in library/psa_crypto_random_impl.h. - * See that file for implementation documentation. */ - - -/* The type of a `f_rng` random generator function that many library functions - * take. - * - * This type name is not part of the Mbed TLS stable API. It may be renamed - * or moved without warning. - */ -typedef int mbedtls_f_rng_t(void *p_rng, unsigned char *output, size_t output_size); - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - -/** The random generator function for the PSA subsystem. - * - * This function is suitable as the `f_rng` random generator function - * parameter of many `mbedtls_xxx` functions. Use #MBEDTLS_PSA_RANDOM_STATE - * to obtain the \p p_rng parameter. - * - * The implementation of this function depends on the configuration of the - * library. - * - * \note Depending on the configuration, this may be a function or - * a pointer to a function. - * - * \note This function may only be used if the PSA crypto subsystem is active. - * This means that you must call psa_crypto_init() before any call to - * this function, and you must not call this function after calling - * mbedtls_psa_crypto_free(). - * - * \param p_rng The random generator context. This must be - * #MBEDTLS_PSA_RANDOM_STATE. No other state is - * supported. - * \param output The buffer to fill. It must have room for - * \c output_size bytes. - * \param output_size The number of bytes to write to \p output. - * This function may fail if \p output_size is too - * large. It is guaranteed to accept any output size - * requested by Mbed TLS library functions. The - * maximum request size depends on the library - * configuration. - * - * \return \c 0 on success. - * \return An `MBEDTLS_ERR_ENTROPY_xxx`, - * `MBEDTLS_ERR_PLATFORM_xxx, - * `MBEDTLS_ERR_CTR_DRBG_xxx` or - * `MBEDTLS_ERR_HMAC_DRBG_xxx` on error. - */ -int mbedtls_psa_get_random(void *p_rng, - unsigned char *output, - size_t output_size); - -/** The random generator state for the PSA subsystem. - * - * This macro expands to an expression which is suitable as the `p_rng` - * random generator state parameter of many `mbedtls_xxx` functions. - * It must be used in combination with the random generator function - * mbedtls_psa_get_random(). - * - * The implementation of this macro depends on the configuration of the - * library. Do not make any assumption on its nature. - */ -#define MBEDTLS_PSA_RANDOM_STATE NULL - -#else /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ - -#if defined(MBEDTLS_CTR_DRBG_C) -#include "mbedtls/ctr_drbg.h" -typedef mbedtls_ctr_drbg_context mbedtls_psa_drbg_context_t; -static mbedtls_f_rng_t *const mbedtls_psa_get_random = mbedtls_ctr_drbg_random; -#elif defined(MBEDTLS_HMAC_DRBG_C) -#include "mbedtls/hmac_drbg.h" -typedef mbedtls_hmac_drbg_context mbedtls_psa_drbg_context_t; -static mbedtls_f_rng_t *const mbedtls_psa_get_random = mbedtls_hmac_drbg_random; -#endif -extern mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state; - -#define MBEDTLS_PSA_RANDOM_STATE mbedtls_psa_random_state - -#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ -#endif /* MBEDTLS_PSA_UTIL_H */ +/** + * \file psa_util.h + * + * \brief Utility functions for the use of the PSA Crypto library. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PSA_UTIL_H +#define MBEDTLS_PSA_UTIL_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +/* Expose whatever RNG the PSA subsystem uses to applications using the + * mbedtls_xxx API. The declarations and definitions here need to be + * consistent with the implementation in library/psa_crypto_random_impl.h. + * See that file for implementation documentation. */ + + +/* The type of a `f_rng` random generator function that many library functions + * take. + * + * This type name is not part of the Mbed TLS stable API. It may be renamed + * or moved without warning. + */ +typedef int mbedtls_f_rng_t(void *p_rng, unsigned char *output, size_t output_size); + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + +/** The random generator function for the PSA subsystem. + * + * This function is suitable as the `f_rng` random generator function + * parameter of many `mbedtls_xxx` functions. Use #MBEDTLS_PSA_RANDOM_STATE + * to obtain the \p p_rng parameter. + * + * The implementation of this function depends on the configuration of the + * library. + * + * \note Depending on the configuration, this may be a function or + * a pointer to a function. + * + * \note This function may only be used if the PSA crypto subsystem is active. + * This means that you must call psa_crypto_init() before any call to + * this function, and you must not call this function after calling + * mbedtls_psa_crypto_free(). + * + * \param p_rng The random generator context. This must be + * #MBEDTLS_PSA_RANDOM_STATE. No other state is + * supported. + * \param output The buffer to fill. It must have room for + * \c output_size bytes. + * \param output_size The number of bytes to write to \p output. + * This function may fail if \p output_size is too + * large. It is guaranteed to accept any output size + * requested by Mbed TLS library functions. The + * maximum request size depends on the library + * configuration. + * + * \return \c 0 on success. + * \return An `MBEDTLS_ERR_ENTROPY_xxx`, + * `MBEDTLS_ERR_PLATFORM_xxx, + * `MBEDTLS_ERR_CTR_DRBG_xxx` or + * `MBEDTLS_ERR_HMAC_DRBG_xxx` on error. + */ +int mbedtls_psa_get_random(void *p_rng, + unsigned char *output, + size_t output_size); + +/** The random generator state for the PSA subsystem. + * + * This macro expands to an expression which is suitable as the `p_rng` + * random generator state parameter of many `mbedtls_xxx` functions. + * It must be used in combination with the random generator function + * mbedtls_psa_get_random(). + * + * The implementation of this macro depends on the configuration of the + * library. Do not make any assumption on its nature. + */ +#define MBEDTLS_PSA_RANDOM_STATE NULL + +#else /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ + +#if defined(MBEDTLS_CTR_DRBG_C) +#include "mbedtls/ctr_drbg.h" +typedef mbedtls_ctr_drbg_context mbedtls_psa_drbg_context_t; +static mbedtls_f_rng_t *const mbedtls_psa_get_random = mbedtls_ctr_drbg_random; +#elif defined(MBEDTLS_HMAC_DRBG_C) +#include "mbedtls/hmac_drbg.h" +typedef mbedtls_hmac_drbg_context mbedtls_psa_drbg_context_t; +static mbedtls_f_rng_t *const mbedtls_psa_get_random = mbedtls_hmac_drbg_random; +#endif +extern mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state; + +#define MBEDTLS_PSA_RANDOM_STATE mbedtls_psa_random_state + +#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ +#endif /* MBEDTLS_PSA_UTIL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ripemd160.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ripemd160.h index acec3c5..42e39d3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ripemd160.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ripemd160.h @@ -1,148 +1,148 @@ -/** - * \file ripemd160.h - * - * \brief RIPE MD-160 message digest - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_RIPEMD160_H -#define MBEDTLS_RIPEMD160_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_RIPEMD160_ALT) -// Regular implementation -// - -/** - * \brief RIPEMD-160 context structure - */ -typedef struct mbedtls_ripemd160_context { - uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< number of bytes processed */ - uint32_t MBEDTLS_PRIVATE(state)[5]; /*!< intermediate digest state */ - unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< data block being processed */ -} -mbedtls_ripemd160_context; - -#else /* MBEDTLS_RIPEMD160_ALT */ -#include "ripemd160_alt.h" -#endif /* MBEDTLS_RIPEMD160_ALT */ - -/** - * \brief Initialize RIPEMD-160 context - * - * \param ctx RIPEMD-160 context to be initialized - */ -void mbedtls_ripemd160_init(mbedtls_ripemd160_context *ctx); - -/** - * \brief Clear RIPEMD-160 context - * - * \param ctx RIPEMD-160 context to be cleared - */ -void mbedtls_ripemd160_free(mbedtls_ripemd160_context *ctx); - -/** - * \brief Clone (the state of) a RIPEMD-160 context - * - * \param dst The destination context - * \param src The context to be cloned - */ -void mbedtls_ripemd160_clone(mbedtls_ripemd160_context *dst, - const mbedtls_ripemd160_context *src); - -/** - * \brief RIPEMD-160 context setup - * - * \param ctx context to be initialized - * - * \return 0 if successful - */ -int mbedtls_ripemd160_starts(mbedtls_ripemd160_context *ctx); - -/** - * \brief RIPEMD-160 process buffer - * - * \param ctx RIPEMD-160 context - * \param input buffer holding the data - * \param ilen length of the input data - * - * \return 0 if successful - */ -int mbedtls_ripemd160_update(mbedtls_ripemd160_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief RIPEMD-160 final digest - * - * \param ctx RIPEMD-160 context - * \param output RIPEMD-160 checksum result - * - * \return 0 if successful - */ -int mbedtls_ripemd160_finish(mbedtls_ripemd160_context *ctx, - unsigned char output[20]); - -/** - * \brief RIPEMD-160 process data block (internal use only) - * - * \param ctx RIPEMD-160 context - * \param data buffer holding one block of data - * - * \return 0 if successful - */ -int mbedtls_internal_ripemd160_process(mbedtls_ripemd160_context *ctx, - const unsigned char data[64]); - -/** - * \brief Output = RIPEMD-160( input buffer ) - * - * \param input buffer holding the data - * \param ilen length of the input data - * \param output RIPEMD-160 checksum result - * - * \return 0 if successful - */ -int mbedtls_ripemd160(const unsigned char *input, - size_t ilen, - unsigned char output[20]); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief Checkup routine - * - * \return 0 if successful, or 1 if the test failed - */ -int mbedtls_ripemd160_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_ripemd160.h */ +/** + * \file ripemd160.h + * + * \brief RIPE MD-160 message digest + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_RIPEMD160_H +#define MBEDTLS_RIPEMD160_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_RIPEMD160_ALT) +// Regular implementation +// + +/** + * \brief RIPEMD-160 context structure + */ +typedef struct mbedtls_ripemd160_context { + uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< number of bytes processed */ + uint32_t MBEDTLS_PRIVATE(state)[5]; /*!< intermediate digest state */ + unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< data block being processed */ +} +mbedtls_ripemd160_context; + +#else /* MBEDTLS_RIPEMD160_ALT */ +#include "ripemd160_alt.h" +#endif /* MBEDTLS_RIPEMD160_ALT */ + +/** + * \brief Initialize RIPEMD-160 context + * + * \param ctx RIPEMD-160 context to be initialized + */ +void mbedtls_ripemd160_init(mbedtls_ripemd160_context *ctx); + +/** + * \brief Clear RIPEMD-160 context + * + * \param ctx RIPEMD-160 context to be cleared + */ +void mbedtls_ripemd160_free(mbedtls_ripemd160_context *ctx); + +/** + * \brief Clone (the state of) a RIPEMD-160 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_ripemd160_clone(mbedtls_ripemd160_context *dst, + const mbedtls_ripemd160_context *src); + +/** + * \brief RIPEMD-160 context setup + * + * \param ctx context to be initialized + * + * \return 0 if successful + */ +int mbedtls_ripemd160_starts(mbedtls_ripemd160_context *ctx); + +/** + * \brief RIPEMD-160 process buffer + * + * \param ctx RIPEMD-160 context + * \param input buffer holding the data + * \param ilen length of the input data + * + * \return 0 if successful + */ +int mbedtls_ripemd160_update(mbedtls_ripemd160_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief RIPEMD-160 final digest + * + * \param ctx RIPEMD-160 context + * \param output RIPEMD-160 checksum result + * + * \return 0 if successful + */ +int mbedtls_ripemd160_finish(mbedtls_ripemd160_context *ctx, + unsigned char output[20]); + +/** + * \brief RIPEMD-160 process data block (internal use only) + * + * \param ctx RIPEMD-160 context + * \param data buffer holding one block of data + * + * \return 0 if successful + */ +int mbedtls_internal_ripemd160_process(mbedtls_ripemd160_context *ctx, + const unsigned char data[64]); + +/** + * \brief Output = RIPEMD-160( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output RIPEMD-160 checksum result + * + * \return 0 if successful + */ +int mbedtls_ripemd160(const unsigned char *input, + size_t ilen, + unsigned char output[20]); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int mbedtls_ripemd160_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_ripemd160.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/rsa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/rsa.h index 69f3981..e4cb306 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/rsa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/rsa.h @@ -1,1155 +1,1155 @@ -/** - * \file rsa.h - * - * \brief This file provides an API for the RSA public-key cryptosystem. - * - * The RSA public-key cryptosystem is defined in Public-Key - * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption - * and Public-Key Cryptography Standards (PKCS) #1 v2.1: - * RSA Cryptography Specifications. - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_RSA_H -#define MBEDTLS_RSA_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/bignum.h" -#include "mbedtls/md.h" - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - -/* - * RSA Error codes - */ -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_RSA_BAD_INPUT_DATA -0x4080 -/** Input data contains invalid padding and is rejected. */ -#define MBEDTLS_ERR_RSA_INVALID_PADDING -0x4100 -/** Something failed during generation of a key. */ -#define MBEDTLS_ERR_RSA_KEY_GEN_FAILED -0x4180 -/** Key failed to pass the validity check of the library. */ -#define MBEDTLS_ERR_RSA_KEY_CHECK_FAILED -0x4200 -/** The public key operation failed. */ -#define MBEDTLS_ERR_RSA_PUBLIC_FAILED -0x4280 -/** The private key operation failed. */ -#define MBEDTLS_ERR_RSA_PRIVATE_FAILED -0x4300 -/** The PKCS#1 verification failed. */ -#define MBEDTLS_ERR_RSA_VERIFY_FAILED -0x4380 -/** The output buffer for decryption is not large enough. */ -#define MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 -/** The random generator failed to generate non-zeros. */ -#define MBEDTLS_ERR_RSA_RNG_FAILED -0x4480 - -/* - * RSA constants - */ - -#define MBEDTLS_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */ -#define MBEDTLS_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */ - -#define MBEDTLS_RSA_SIGN 1 /**< Identifier for RSA signature operations. */ -#define MBEDTLS_RSA_CRYPT 2 /**< Identifier for RSA encryption and decryption operations. */ - -#define MBEDTLS_RSA_SALT_LEN_ANY -1 - -/* - * The above constants may be used even if the RSA module is compile out, - * eg for alternative (PKCS#11) RSA implementations in the PK layers. - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_RSA_ALT) -// Regular implementation -// - -#if !defined(MBEDTLS_RSA_GEN_KEY_MIN_BITS) -#define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 -#elif MBEDTLS_RSA_GEN_KEY_MIN_BITS < 128 -#error "MBEDTLS_RSA_GEN_KEY_MIN_BITS must be at least 128 bits" -#endif - -/** - * \brief The RSA context structure. - */ -typedef struct mbedtls_rsa_context { - int MBEDTLS_PRIVATE(ver); /*!< Reserved for internal purposes. - * Do not set this field in application - * code. Its meaning might change without - * notice. */ - size_t MBEDTLS_PRIVATE(len); /*!< The size of \p N in Bytes. */ - - mbedtls_mpi MBEDTLS_PRIVATE(N); /*!< The public modulus. */ - mbedtls_mpi MBEDTLS_PRIVATE(E); /*!< The public exponent. */ - - mbedtls_mpi MBEDTLS_PRIVATE(D); /*!< The private exponent. */ - mbedtls_mpi MBEDTLS_PRIVATE(P); /*!< The first prime factor. */ - mbedtls_mpi MBEDTLS_PRIVATE(Q); /*!< The second prime factor. */ - - mbedtls_mpi MBEDTLS_PRIVATE(DP); /*!< D % (P - 1). */ - mbedtls_mpi MBEDTLS_PRIVATE(DQ); /*!< D % (Q - 1). */ - mbedtls_mpi MBEDTLS_PRIVATE(QP); /*!< 1 / (Q % P). */ - - mbedtls_mpi MBEDTLS_PRIVATE(RN); /*!< cached R^2 mod N. */ - - mbedtls_mpi MBEDTLS_PRIVATE(RP); /*!< cached R^2 mod P. */ - mbedtls_mpi MBEDTLS_PRIVATE(RQ); /*!< cached R^2 mod Q. */ - - mbedtls_mpi MBEDTLS_PRIVATE(Vi); /*!< The cached blinding value. */ - mbedtls_mpi MBEDTLS_PRIVATE(Vf); /*!< The cached un-blinding value. */ - - int MBEDTLS_PRIVATE(padding); /*!< Selects padding mode: - #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and - #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */ - int MBEDTLS_PRIVATE(hash_id); /*!< Hash identifier of mbedtls_md_type_t type, - as specified in md.h for use in the MGF - mask generating function used in the - EME-OAEP and EMSA-PSS encodings. */ -#if defined(MBEDTLS_THREADING_C) - /* Invariant: the mutex is initialized iff ver != 0. */ - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< Thread-safety mutex. */ -#endif -} -mbedtls_rsa_context; - -#else /* MBEDTLS_RSA_ALT */ -#include "rsa_alt.h" -#endif /* MBEDTLS_RSA_ALT */ - -/** - * \brief This function initializes an RSA context. - * - * \note This function initializes the padding and the hash - * identifier to respectively #MBEDTLS_RSA_PKCS_V15 and - * #MBEDTLS_MD_NONE. See mbedtls_rsa_set_padding() for more - * information about those parameters. - * - * \param ctx The RSA context to initialize. This must not be \c NULL. - */ -void mbedtls_rsa_init(mbedtls_rsa_context *ctx); - -/** - * \brief This function sets padding for an already initialized RSA - * context. - * - * \note Set padding to #MBEDTLS_RSA_PKCS_V21 for the RSAES-OAEP - * encryption scheme and the RSASSA-PSS signature scheme. - * - * \note The \p hash_id parameter is ignored when using - * #MBEDTLS_RSA_PKCS_V15 padding. - * - * \note The choice of padding mode is strictly enforced for private - * key operations, since there might be security concerns in - * mixing padding modes. For public key operations it is - * a default value, which can be overridden by calling specific - * \c mbedtls_rsa_rsaes_xxx or \c mbedtls_rsa_rsassa_xxx - * functions. - * - * \note The hash selected in \p hash_id is always used for OEAP - * encryption. For PSS signatures, it is always used for - * making signatures, but can be overridden for verifying them. - * If set to #MBEDTLS_MD_NONE, it is always overridden. - * - * \param ctx The initialized RSA context to be configured. - * \param padding The padding mode to use. This must be either - * #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21. - * \param hash_id The hash identifier for PSS or OAEP, if \p padding is - * #MBEDTLS_RSA_PKCS_V21. #MBEDTLS_MD_NONE is accepted by this - * function but may be not suitable for some operations. - * Ignored if \p padding is #MBEDTLS_RSA_PKCS_V15. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_RSA_INVALID_PADDING failure: - * \p padding or \p hash_id is invalid. - */ -int mbedtls_rsa_set_padding(mbedtls_rsa_context *ctx, int padding, - mbedtls_md_type_t hash_id); - -/** - * \brief This function retrieves padding mode of initialized - * RSA context. - * - * \param ctx The initialized RSA context. - * - * \return RSA padding mode. - * - */ -int mbedtls_rsa_get_padding_mode(const mbedtls_rsa_context *ctx); - -/** - * \brief This function retrieves hash identifier of mbedtls_md_type_t - * type. - * - * \param ctx The initialized RSA context. - * - * \return Hash identifier of mbedtls_md_type_t type. - * - */ -int mbedtls_rsa_get_md_alg(const mbedtls_rsa_context *ctx); - -/** - * \brief This function imports a set of core parameters into an - * RSA context. - * - * \note This function can be called multiple times for successive - * imports, if the parameters are not simultaneously present. - * - * Any sequence of calls to this function should be followed - * by a call to mbedtls_rsa_complete(), which checks and - * completes the provided information to a ready-for-use - * public or private RSA key. - * - * \note See mbedtls_rsa_complete() for more information on which - * parameters are necessary to set up a private or public - * RSA key. - * - * \note The imported parameters are copied and need not be preserved - * for the lifetime of the RSA context being set up. - * - * \param ctx The initialized RSA context to store the parameters in. - * \param N The RSA modulus. This may be \c NULL. - * \param P The first prime factor of \p N. This may be \c NULL. - * \param Q The second prime factor of \p N. This may be \c NULL. - * \param D The private exponent. This may be \c NULL. - * \param E The public exponent. This may be \c NULL. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_rsa_import(mbedtls_rsa_context *ctx, - const mbedtls_mpi *N, - const mbedtls_mpi *P, const mbedtls_mpi *Q, - const mbedtls_mpi *D, const mbedtls_mpi *E); - -/** - * \brief This function imports core RSA parameters, in raw big-endian - * binary format, into an RSA context. - * - * \note This function can be called multiple times for successive - * imports, if the parameters are not simultaneously present. - * - * Any sequence of calls to this function should be followed - * by a call to mbedtls_rsa_complete(), which checks and - * completes the provided information to a ready-for-use - * public or private RSA key. - * - * \note See mbedtls_rsa_complete() for more information on which - * parameters are necessary to set up a private or public - * RSA key. - * - * \note The imported parameters are copied and need not be preserved - * for the lifetime of the RSA context being set up. - * - * \param ctx The initialized RSA context to store the parameters in. - * \param N The RSA modulus. This may be \c NULL. - * \param N_len The Byte length of \p N; it is ignored if \p N == NULL. - * \param P The first prime factor of \p N. This may be \c NULL. - * \param P_len The Byte length of \p P; it is ignored if \p P == NULL. - * \param Q The second prime factor of \p N. This may be \c NULL. - * \param Q_len The Byte length of \p Q; it is ignored if \p Q == NULL. - * \param D The private exponent. This may be \c NULL. - * \param D_len The Byte length of \p D; it is ignored if \p D == NULL. - * \param E The public exponent. This may be \c NULL. - * \param E_len The Byte length of \p E; it is ignored if \p E == NULL. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_rsa_import_raw(mbedtls_rsa_context *ctx, - unsigned char const *N, size_t N_len, - unsigned char const *P, size_t P_len, - unsigned char const *Q, size_t Q_len, - unsigned char const *D, size_t D_len, - unsigned char const *E, size_t E_len); - -/** - * \brief This function completes an RSA context from - * a set of imported core parameters. - * - * To setup an RSA public key, precisely \c N and \c E - * must have been imported. - * - * To setup an RSA private key, sufficient information must - * be present for the other parameters to be derivable. - * - * The default implementation supports the following: - *
  • Derive \c P, \c Q from \c N, \c D, \c E.
    • - *
  • Derive \c N, \c D from \c P, \c Q, \c E.
- * Alternative implementations need not support these. - * - * If this function runs successfully, it guarantees that - * the RSA context can be used for RSA operations without - * the risk of failure or crash. - * - * \warning This function need not perform consistency checks - * for the imported parameters. In particular, parameters that - * are not needed by the implementation might be silently - * discarded and left unchecked. To check the consistency - * of the key material, see mbedtls_rsa_check_privkey(). - * - * \param ctx The initialized RSA context holding imported parameters. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_RSA_BAD_INPUT_DATA if the attempted derivations - * failed. - * - */ -int mbedtls_rsa_complete(mbedtls_rsa_context *ctx); - -/** - * \brief This function exports the core parameters of an RSA key. - * - * If this function runs successfully, the non-NULL buffers - * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully - * written, with additional unused space filled leading by - * zero Bytes. - * - * Possible reasons for returning - * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    - *
  • An alternative RSA implementation is in use, which - * stores the key externally, and either cannot or should - * not export it into RAM.
    • - *
  • A SW or HW implementation might not support a certain - * deduction. For example, \p P, \p Q from \p N, \p D, - * and \p E if the former are not part of the - * implementation.
- * - * If the function fails due to an unsupported operation, - * the RSA context stays intact and remains usable. - * - * \param ctx The initialized RSA context. - * \param N The MPI to hold the RSA modulus. - * This may be \c NULL if this field need not be exported. - * \param P The MPI to hold the first prime factor of \p N. - * This may be \c NULL if this field need not be exported. - * \param Q The MPI to hold the second prime factor of \p N. - * This may be \c NULL if this field need not be exported. - * \param D The MPI to hold the private exponent. - * This may be \c NULL if this field need not be exported. - * \param E The MPI to hold the public exponent. - * This may be \c NULL if this field need not be exported. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the - * requested parameters cannot be done due to missing - * functionality or because of security policies. - * \return A non-zero return code on any other failure. - * - */ -int mbedtls_rsa_export(const mbedtls_rsa_context *ctx, - mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, - mbedtls_mpi *D, mbedtls_mpi *E); - -/** - * \brief This function exports core parameters of an RSA key - * in raw big-endian binary format. - * - * If this function runs successfully, the non-NULL buffers - * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully - * written, with additional unused space filled leading by - * zero Bytes. - * - * Possible reasons for returning - * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    - *
  • An alternative RSA implementation is in use, which - * stores the key externally, and either cannot or should - * not export it into RAM.
    • - *
  • A SW or HW implementation might not support a certain - * deduction. For example, \p P, \p Q from \p N, \p D, - * and \p E if the former are not part of the - * implementation.
- * If the function fails due to an unsupported operation, - * the RSA context stays intact and remains usable. - * - * \note The length parameters are ignored if the corresponding - * buffer pointers are NULL. - * - * \param ctx The initialized RSA context. - * \param N The Byte array to store the RSA modulus, - * or \c NULL if this field need not be exported. - * \param N_len The size of the buffer for the modulus. - * \param P The Byte array to hold the first prime factor of \p N, - * or \c NULL if this field need not be exported. - * \param P_len The size of the buffer for the first prime factor. - * \param Q The Byte array to hold the second prime factor of \p N, - * or \c NULL if this field need not be exported. - * \param Q_len The size of the buffer for the second prime factor. - * \param D The Byte array to hold the private exponent, - * or \c NULL if this field need not be exported. - * \param D_len The size of the buffer for the private exponent. - * \param E The Byte array to hold the public exponent, - * or \c NULL if this field need not be exported. - * \param E_len The size of the buffer for the public exponent. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the - * requested parameters cannot be done due to missing - * functionality or because of security policies. - * \return A non-zero return code on any other failure. - */ -int mbedtls_rsa_export_raw(const mbedtls_rsa_context *ctx, - unsigned char *N, size_t N_len, - unsigned char *P, size_t P_len, - unsigned char *Q, size_t Q_len, - unsigned char *D, size_t D_len, - unsigned char *E, size_t E_len); - -/** - * \brief This function exports CRT parameters of a private RSA key. - * - * \note Alternative RSA implementations not using CRT-parameters - * internally can implement this function based on - * mbedtls_rsa_deduce_opt(). - * - * \param ctx The initialized RSA context. - * \param DP The MPI to hold \c D modulo `P-1`, - * or \c NULL if it need not be exported. - * \param DQ The MPI to hold \c D modulo `Q-1`, - * or \c NULL if it need not be exported. - * \param QP The MPI to hold modular inverse of \c Q modulo \c P, - * or \c NULL if it need not be exported. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - * - */ -int mbedtls_rsa_export_crt(const mbedtls_rsa_context *ctx, - mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP); - -/** - * \brief This function retrieves the length of RSA modulus in Bytes. - * - * \param ctx The initialized RSA context. - * - * \return The length of the RSA modulus in Bytes. - * - */ -size_t mbedtls_rsa_get_len(const mbedtls_rsa_context *ctx); - -/** - * \brief This function generates an RSA keypair. - * - * \note mbedtls_rsa_init() must be called before this function, - * to set up the RSA context. - * - * \param ctx The initialized RSA context used to hold the key. - * \param f_rng The RNG function to be used for key generation. - * This is mandatory and must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. - * This may be \c NULL if \p f_rng doesn't need a context. - * \param nbits The size of the public key in bits. - * \param exponent The public exponent to use. For example, \c 65537. - * This must be odd and greater than \c 1. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_gen_key(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - unsigned int nbits, int exponent); - -/** - * \brief This function checks if a context contains at least an RSA - * public key. - * - * If the function runs successfully, it is guaranteed that - * enough information is present to perform an RSA public key - * operation using mbedtls_rsa_public(). - * - * \param ctx The initialized RSA context to check. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - * - */ -int mbedtls_rsa_check_pubkey(const mbedtls_rsa_context *ctx); - -/** - * \brief This function checks if a context contains an RSA private key - * and perform basic consistency checks. - * - * \note The consistency checks performed by this function not only - * ensure that mbedtls_rsa_private() can be called successfully - * on the given context, but that the various parameters are - * mutually consistent with high probability, in the sense that - * mbedtls_rsa_public() and mbedtls_rsa_private() are inverses. - * - * \warning This function should catch accidental misconfigurations - * like swapping of parameters, but it cannot establish full - * trust in neither the quality nor the consistency of the key - * material that was used to setup the given RSA context: - *
  • Consistency: Imported parameters that are irrelevant - * for the implementation might be silently dropped. If dropped, - * the current function does not have access to them, - * and therefore cannot check them. See mbedtls_rsa_complete(). - * If you want to check the consistency of the entire - * content of a PKCS1-encoded RSA private key, for example, you - * should use mbedtls_rsa_validate_params() before setting - * up the RSA context. - * Additionally, if the implementation performs empirical checks, - * these checks substantiate but do not guarantee consistency.
    • - *
  • Quality: This function is not expected to perform - * extended quality assessments like checking that the prime - * factors are safe. Additionally, it is the responsibility of the - * user to ensure the trustworthiness of the source of his RSA - * parameters, which goes beyond what is effectively checkable - * by the library.
- * - * \param ctx The initialized RSA context to check. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_check_privkey(const mbedtls_rsa_context *ctx); - -/** - * \brief This function checks a public-private RSA key pair. - * - * It checks each of the contexts, and makes sure they match. - * - * \param pub The initialized RSA context holding the public key. - * \param prv The initialized RSA context holding the private key. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_check_pub_priv(const mbedtls_rsa_context *pub, - const mbedtls_rsa_context *prv); - -/** - * \brief This function performs an RSA public key operation. - * - * \param ctx The initialized RSA context to use. - * \param input The input buffer. This must be a readable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * \param output The output buffer. This must be a writable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \note This function does not handle message padding. - * - * \note Make sure to set \p input[0] = 0 or ensure that - * input is smaller than \c N. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_public(mbedtls_rsa_context *ctx, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function performs an RSA private key operation. - * - * \note Blinding is used if and only if a PRNG is provided. - * - * \note If blinding is used, both the base of exponentiation - * and the exponent are blinded, providing protection - * against some side-channel attacks. - * - * \warning It is deprecated and a security risk to not provide - * a PRNG here and thereby prevent the use of blinding. - * Future versions of the library may enforce the presence - * of a PRNG. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function, used for blinding. It is mandatory. - * \param p_rng The RNG context to pass to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context. - * \param input The input buffer. This must be a readable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * \param output The output buffer. This must be a writable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - * - */ -int mbedtls_rsa_private(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function adds the message padding, then performs an RSA - * operation. - * - * It is the generic wrapper for performing a PKCS#1 encryption - * operation. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG to use. It is used for padding generation - * and it is mandatory. - * \param p_rng The RNG context to be passed to \p f_rng. May be - * \c NULL if \p f_rng doesn't need a context argument. - * \param ilen The length of the plaintext in Bytes. - * \param input The input data to encrypt. This must be a readable - * buffer of size \p ilen Bytes. It may be \c NULL if - * `ilen == 0`. - * \param output The output buffer. This must be a writable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_pkcs1_encrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - size_t ilen, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function performs a PKCS#1 v1.5 encryption operation - * (RSAES-PKCS1-v1_5-ENCRYPT). - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function to use. It is mandatory and used for - * padding generation. - * \param p_rng The RNG context to be passed to \p f_rng. This may - * be \c NULL if \p f_rng doesn't need a context argument. - * \param ilen The length of the plaintext in Bytes. - * \param input The input data to encrypt. This must be a readable - * buffer of size \p ilen Bytes. It may be \c NULL if - * `ilen == 0`. - * \param output The output buffer. This must be a writable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsaes_pkcs1_v15_encrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - size_t ilen, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function performs a PKCS#1 v2.1 OAEP encryption - * operation (RSAES-OAEP-ENCRYPT). - * - * \note The output buffer must be as large as the size - * of ctx->N. For example, 128 Bytes if RSA-1024 is used. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function to use. This is needed for padding - * generation and is mandatory. - * \param p_rng The RNG context to be passed to \p f_rng. This may - * be \c NULL if \p f_rng doesn't need a context argument. - * \param label The buffer holding the custom label to use. - * This must be a readable buffer of length \p label_len - * Bytes. It may be \c NULL if \p label_len is \c 0. - * \param label_len The length of the label in Bytes. - * \param ilen The length of the plaintext buffer \p input in Bytes. - * \param input The input data to encrypt. This must be a readable - * buffer of size \p ilen Bytes. It may be \c NULL if - * `ilen == 0`. - * \param output The output buffer. This must be a writable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsaes_oaep_encrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - const unsigned char *label, size_t label_len, - size_t ilen, - const unsigned char *input, - unsigned char *output); - -/** - * \brief This function performs an RSA operation, then removes the - * message padding. - * - * It is the generic wrapper for performing a PKCS#1 decryption - * operation. - * - * \note The output buffer length \c output_max_len should be - * as large as the size \p ctx->len of \p ctx->N (for example, - * 128 Bytes if RSA-1024 is used) to be able to hold an - * arbitrary decrypted message. If it is not large enough to - * hold the decryption of the particular ciphertext provided, - * the function returns \c MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. This is used for blinding and is - * mandatory; see mbedtls_rsa_private() for more. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context. - * \param olen The address at which to store the length of - * the plaintext. This must not be \c NULL. - * \param input The ciphertext buffer. This must be a readable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * \param output The buffer used to hold the plaintext. This must - * be a writable buffer of length \p output_max_len Bytes. - * \param output_max_len The length in Bytes of the output buffer \p output. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_pkcs1_decrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - size_t *olen, - const unsigned char *input, - unsigned char *output, - size_t output_max_len); - -/** - * \brief This function performs a PKCS#1 v1.5 decryption - * operation (RSAES-PKCS1-v1_5-DECRYPT). - * - * \note The output buffer length \c output_max_len should be - * as large as the size \p ctx->len of \p ctx->N, for example, - * 128 Bytes if RSA-1024 is used, to be able to hold an - * arbitrary decrypted message. If it is not large enough to - * hold the decryption of the particular ciphertext provided, - * the function returns #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. This is used for blinding and is - * mandatory; see mbedtls_rsa_private() for more. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context. - * \param olen The address at which to store the length of - * the plaintext. This must not be \c NULL. - * \param input The ciphertext buffer. This must be a readable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * \param output The buffer used to hold the plaintext. This must - * be a writable buffer of length \p output_max_len Bytes. - * \param output_max_len The length in Bytes of the output buffer \p output. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - * - */ -int mbedtls_rsa_rsaes_pkcs1_v15_decrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - size_t *olen, - const unsigned char *input, - unsigned char *output, - size_t output_max_len); - -/** - * \brief This function performs a PKCS#1 v2.1 OAEP decryption - * operation (RSAES-OAEP-DECRYPT). - * - * \note The output buffer length \c output_max_len should be - * as large as the size \p ctx->len of \p ctx->N, for - * example, 128 Bytes if RSA-1024 is used, to be able to - * hold an arbitrary decrypted message. If it is not - * large enough to hold the decryption of the particular - * ciphertext provided, the function returns - * #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. This is used for blinding and is - * mandatory. - * \param p_rng The RNG context to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context. - * \param label The buffer holding the custom label to use. - * This must be a readable buffer of length \p label_len - * Bytes. It may be \c NULL if \p label_len is \c 0. - * \param label_len The length of the label in Bytes. - * \param olen The address at which to store the length of - * the plaintext. This must not be \c NULL. - * \param input The ciphertext buffer. This must be a readable buffer - * of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * \param output The buffer used to hold the plaintext. This must - * be a writable buffer of length \p output_max_len Bytes. - * \param output_max_len The length in Bytes of the output buffer \p output. - * - * \return \c 0 on success. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - const unsigned char *label, size_t label_len, - size_t *olen, - const unsigned char *input, - unsigned char *output, - size_t output_max_len); - -/** - * \brief This function performs a private RSA operation to sign - * a message digest using PKCS#1. - * - * It is the generic wrapper for performing a PKCS#1 - * signature. - * - * \note The \p sig buffer must be as large as the size - * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. - * - * \note For PKCS#1 v2.1 encoding, see comments on - * mbedtls_rsa_rsassa_pss_sign() for details on - * \p md_alg and \p hash_id. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function to use. This is mandatory and - * must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context argument. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer to hold the signature. This must be a writable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. A buffer length of - * #MBEDTLS_MPI_MAX_SIZE is always safe. - * - * \return \c 0 if the signing operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_pkcs1_sign(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v1.5 signature - * operation (RSASSA-PKCS1-v1_5-SIGN). - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. This is used for blinding and is - * mandatory; see mbedtls_rsa_private() for more. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context argument. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer to hold the signature. This must be a writable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. A buffer length of - * #MBEDTLS_MPI_MAX_SIZE is always safe. - * - * \return \c 0 if the signing operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pkcs1_v15_sign(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v2.1 PSS signature - * operation (RSASSA-PSS-SIGN). - * - * \note The \c hash_id set in \p ctx by calling - * mbedtls_rsa_set_padding() selects the hash used for the - * encoding operation and for the mask generation function - * (MGF1). For more details on the encoding operation and the - * mask generation function, consult RFC-3447: Public-Key - * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography - * Specifications. - * - * \note This function enforces that the provided salt length complies - * with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1 v2.2) §9.1.1 - * step 3. The constraint is that the hash length plus the salt - * length plus 2 bytes must be at most the key length. If this - * constraint is not met, this function returns - * #MBEDTLS_ERR_RSA_BAD_INPUT_DATA. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. It is mandatory and must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context argument. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param saltlen The length of the salt that should be used. - * If passed #MBEDTLS_RSA_SALT_LEN_ANY, the function will use - * the largest possible salt length up to the hash length, - * which is the largest permitted by some standards including - * FIPS 186-4 §5.5. - * \param sig The buffer to hold the signature. This must be a writable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. A buffer length of - * #MBEDTLS_MPI_MAX_SIZE is always safe. - * - * \return \c 0 if the signing operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pss_sign_ext(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - int saltlen, - unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v2.1 PSS signature - * operation (RSASSA-PSS-SIGN). - * - * \note The \c hash_id set in \p ctx by calling - * mbedtls_rsa_set_padding() selects the hash used for the - * encoding operation and for the mask generation function - * (MGF1). For more details on the encoding operation and the - * mask generation function, consult RFC-3447: Public-Key - * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography - * Specifications. - * - * \note This function always uses the maximum possible salt size, - * up to the length of the payload hash. This choice of salt - * size complies with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1 - * v2.2) §9.1.1 step 3. Furthermore this function enforces a - * minimum salt size which is the hash size minus 2 bytes. If - * this minimum size is too large given the key size (the salt - * size, plus the hash size, plus 2 bytes must be no more than - * the key size in bytes), this function returns - * #MBEDTLS_ERR_RSA_BAD_INPUT_DATA. - * - * \param ctx The initialized RSA context to use. - * \param f_rng The RNG function. It is mandatory and must not be \c NULL. - * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL - * if \p f_rng doesn't need a context argument. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer to hold the signature. This must be a writable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. A buffer length of - * #MBEDTLS_MPI_MAX_SIZE is always safe. - * - * \return \c 0 if the signing operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - unsigned char *sig); - -/** - * \brief This function performs a public RSA operation and checks - * the message digest. - * - * This is the generic wrapper for performing a PKCS#1 - * verification. - * - * \note For PKCS#1 v2.1 encoding, see comments on - * mbedtls_rsa_rsassa_pss_verify() about \c md_alg and - * \c hash_id. - * - * \param ctx The initialized RSA public key context to use. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer holding the signature. This must be a readable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 if the verify operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_pkcs1_verify(mbedtls_rsa_context *ctx, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - const unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v1.5 verification - * operation (RSASSA-PKCS1-v1_5-VERIFY). - * - * \param ctx The initialized RSA public key context to use. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer holding the signature. This must be a readable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 if the verify operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pkcs1_v15_verify(mbedtls_rsa_context *ctx, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - const unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v2.1 PSS verification - * operation (RSASSA-PSS-VERIFY). - * - * \note The \c hash_id set in \p ctx by calling - * mbedtls_rsa_set_padding() selects the hash used for the - * encoding operation and for the mask generation function - * (MGF1). For more details on the encoding operation and the - * mask generation function, consult RFC-3447: Public-Key - * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography - * Specifications. If the \c hash_id set in \p ctx by - * mbedtls_rsa_set_padding() is #MBEDTLS_MD_NONE, the \p md_alg - * parameter is used. - * - * \param ctx The initialized RSA public key context to use. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param sig The buffer holding the signature. This must be a readable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 if the verify operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pss_verify(mbedtls_rsa_context *ctx, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - const unsigned char *sig); - -/** - * \brief This function performs a PKCS#1 v2.1 PSS verification - * operation (RSASSA-PSS-VERIFY). - * - * \note The \p sig buffer must be as large as the size - * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. - * - * \note The \c hash_id set in \p ctx by mbedtls_rsa_set_padding() is - * ignored. - * - * \param ctx The initialized RSA public key context to use. - * \param md_alg The message-digest algorithm used to hash the original data. - * Use #MBEDTLS_MD_NONE for signing raw data. - * \param hashlen The length of the message digest or raw data in Bytes. - * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the - * output length of the corresponding hash algorithm. - * \param hash The buffer holding the message digest or raw data. - * This must be a readable buffer of at least \p hashlen Bytes. - * \param mgf1_hash_id The message digest algorithm used for the - * verification operation and the mask generation - * function (MGF1). For more details on the encoding - * operation and the mask generation function, consult - * RFC-3447: Public-Key Cryptography Standards - * (PKCS) #1 v2.1: RSA Cryptography - * Specifications. - * \param expected_salt_len The length of the salt used in padding. Use - * #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length. - * \param sig The buffer holding the signature. This must be a readable - * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. - * - * \return \c 0 if the verify operation was successful. - * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. - */ -int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - mbedtls_md_type_t mgf1_hash_id, - int expected_salt_len, - const unsigned char *sig); - -/** - * \brief This function copies the components of an RSA context. - * - * \param dst The destination context. This must be initialized. - * \param src The source context. This must be initialized. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory allocation failure. - */ -int mbedtls_rsa_copy(mbedtls_rsa_context *dst, const mbedtls_rsa_context *src); - -/** - * \brief This function frees the components of an RSA key. - * - * \param ctx The RSA context to free. May be \c NULL, in which case - * this function is a no-op. If it is not \c NULL, it must - * point to an initialized RSA context. - */ -void mbedtls_rsa_free(mbedtls_rsa_context *ctx); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The RSA checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_rsa_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* rsa.h */ +/** + * \file rsa.h + * + * \brief This file provides an API for the RSA public-key cryptosystem. + * + * The RSA public-key cryptosystem is defined in Public-Key + * Cryptography Standards (PKCS) #1 v1.5: RSA Encryption + * and Public-Key Cryptography Standards (PKCS) #1 v2.1: + * RSA Cryptography Specifications. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_RSA_H +#define MBEDTLS_RSA_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/bignum.h" +#include "mbedtls/md.h" + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +/* + * RSA Error codes + */ +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_RSA_BAD_INPUT_DATA -0x4080 +/** Input data contains invalid padding and is rejected. */ +#define MBEDTLS_ERR_RSA_INVALID_PADDING -0x4100 +/** Something failed during generation of a key. */ +#define MBEDTLS_ERR_RSA_KEY_GEN_FAILED -0x4180 +/** Key failed to pass the validity check of the library. */ +#define MBEDTLS_ERR_RSA_KEY_CHECK_FAILED -0x4200 +/** The public key operation failed. */ +#define MBEDTLS_ERR_RSA_PUBLIC_FAILED -0x4280 +/** The private key operation failed. */ +#define MBEDTLS_ERR_RSA_PRIVATE_FAILED -0x4300 +/** The PKCS#1 verification failed. */ +#define MBEDTLS_ERR_RSA_VERIFY_FAILED -0x4380 +/** The output buffer for decryption is not large enough. */ +#define MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 +/** The random generator failed to generate non-zeros. */ +#define MBEDTLS_ERR_RSA_RNG_FAILED -0x4480 + +/* + * RSA constants + */ + +#define MBEDTLS_RSA_PKCS_V15 0 /**< Use PKCS#1 v1.5 encoding. */ +#define MBEDTLS_RSA_PKCS_V21 1 /**< Use PKCS#1 v2.1 encoding. */ + +#define MBEDTLS_RSA_SIGN 1 /**< Identifier for RSA signature operations. */ +#define MBEDTLS_RSA_CRYPT 2 /**< Identifier for RSA encryption and decryption operations. */ + +#define MBEDTLS_RSA_SALT_LEN_ANY -1 + +/* + * The above constants may be used even if the RSA module is compile out, + * eg for alternative (PKCS#11) RSA implementations in the PK layers. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_RSA_ALT) +// Regular implementation +// + +#if !defined(MBEDTLS_RSA_GEN_KEY_MIN_BITS) +#define MBEDTLS_RSA_GEN_KEY_MIN_BITS 1024 +#elif MBEDTLS_RSA_GEN_KEY_MIN_BITS < 128 +#error "MBEDTLS_RSA_GEN_KEY_MIN_BITS must be at least 128 bits" +#endif + +/** + * \brief The RSA context structure. + */ +typedef struct mbedtls_rsa_context { + int MBEDTLS_PRIVATE(ver); /*!< Reserved for internal purposes. + * Do not set this field in application + * code. Its meaning might change without + * notice. */ + size_t MBEDTLS_PRIVATE(len); /*!< The size of \p N in Bytes. */ + + mbedtls_mpi MBEDTLS_PRIVATE(N); /*!< The public modulus. */ + mbedtls_mpi MBEDTLS_PRIVATE(E); /*!< The public exponent. */ + + mbedtls_mpi MBEDTLS_PRIVATE(D); /*!< The private exponent. */ + mbedtls_mpi MBEDTLS_PRIVATE(P); /*!< The first prime factor. */ + mbedtls_mpi MBEDTLS_PRIVATE(Q); /*!< The second prime factor. */ + + mbedtls_mpi MBEDTLS_PRIVATE(DP); /*!< D % (P - 1). */ + mbedtls_mpi MBEDTLS_PRIVATE(DQ); /*!< D % (Q - 1). */ + mbedtls_mpi MBEDTLS_PRIVATE(QP); /*!< 1 / (Q % P). */ + + mbedtls_mpi MBEDTLS_PRIVATE(RN); /*!< cached R^2 mod N. */ + + mbedtls_mpi MBEDTLS_PRIVATE(RP); /*!< cached R^2 mod P. */ + mbedtls_mpi MBEDTLS_PRIVATE(RQ); /*!< cached R^2 mod Q. */ + + mbedtls_mpi MBEDTLS_PRIVATE(Vi); /*!< The cached blinding value. */ + mbedtls_mpi MBEDTLS_PRIVATE(Vf); /*!< The cached un-blinding value. */ + + int MBEDTLS_PRIVATE(padding); /*!< Selects padding mode: + #MBEDTLS_RSA_PKCS_V15 for 1.5 padding and + #MBEDTLS_RSA_PKCS_V21 for OAEP or PSS. */ + int MBEDTLS_PRIVATE(hash_id); /*!< Hash identifier of mbedtls_md_type_t type, + as specified in md.h for use in the MGF + mask generating function used in the + EME-OAEP and EMSA-PSS encodings. */ +#if defined(MBEDTLS_THREADING_C) + /* Invariant: the mutex is initialized iff ver != 0. */ + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< Thread-safety mutex. */ +#endif +} +mbedtls_rsa_context; + +#else /* MBEDTLS_RSA_ALT */ +#include "rsa_alt.h" +#endif /* MBEDTLS_RSA_ALT */ + +/** + * \brief This function initializes an RSA context. + * + * \note This function initializes the padding and the hash + * identifier to respectively #MBEDTLS_RSA_PKCS_V15 and + * #MBEDTLS_MD_NONE. See mbedtls_rsa_set_padding() for more + * information about those parameters. + * + * \param ctx The RSA context to initialize. This must not be \c NULL. + */ +void mbedtls_rsa_init(mbedtls_rsa_context *ctx); + +/** + * \brief This function sets padding for an already initialized RSA + * context. + * + * \note Set padding to #MBEDTLS_RSA_PKCS_V21 for the RSAES-OAEP + * encryption scheme and the RSASSA-PSS signature scheme. + * + * \note The \p hash_id parameter is ignored when using + * #MBEDTLS_RSA_PKCS_V15 padding. + * + * \note The choice of padding mode is strictly enforced for private + * key operations, since there might be security concerns in + * mixing padding modes. For public key operations it is + * a default value, which can be overridden by calling specific + * \c mbedtls_rsa_rsaes_xxx or \c mbedtls_rsa_rsassa_xxx + * functions. + * + * \note The hash selected in \p hash_id is always used for OEAP + * encryption. For PSS signatures, it is always used for + * making signatures, but can be overridden for verifying them. + * If set to #MBEDTLS_MD_NONE, it is always overridden. + * + * \param ctx The initialized RSA context to be configured. + * \param padding The padding mode to use. This must be either + * #MBEDTLS_RSA_PKCS_V15 or #MBEDTLS_RSA_PKCS_V21. + * \param hash_id The hash identifier for PSS or OAEP, if \p padding is + * #MBEDTLS_RSA_PKCS_V21. #MBEDTLS_MD_NONE is accepted by this + * function but may be not suitable for some operations. + * Ignored if \p padding is #MBEDTLS_RSA_PKCS_V15. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_RSA_INVALID_PADDING failure: + * \p padding or \p hash_id is invalid. + */ +int mbedtls_rsa_set_padding(mbedtls_rsa_context *ctx, int padding, + mbedtls_md_type_t hash_id); + +/** + * \brief This function retrieves padding mode of initialized + * RSA context. + * + * \param ctx The initialized RSA context. + * + * \return RSA padding mode. + * + */ +int mbedtls_rsa_get_padding_mode(const mbedtls_rsa_context *ctx); + +/** + * \brief This function retrieves hash identifier of mbedtls_md_type_t + * type. + * + * \param ctx The initialized RSA context. + * + * \return Hash identifier of mbedtls_md_type_t type. + * + */ +int mbedtls_rsa_get_md_alg(const mbedtls_rsa_context *ctx); + +/** + * \brief This function imports a set of core parameters into an + * RSA context. + * + * \note This function can be called multiple times for successive + * imports, if the parameters are not simultaneously present. + * + * Any sequence of calls to this function should be followed + * by a call to mbedtls_rsa_complete(), which checks and + * completes the provided information to a ready-for-use + * public or private RSA key. + * + * \note See mbedtls_rsa_complete() for more information on which + * parameters are necessary to set up a private or public + * RSA key. + * + * \note The imported parameters are copied and need not be preserved + * for the lifetime of the RSA context being set up. + * + * \param ctx The initialized RSA context to store the parameters in. + * \param N The RSA modulus. This may be \c NULL. + * \param P The first prime factor of \p N. This may be \c NULL. + * \param Q The second prime factor of \p N. This may be \c NULL. + * \param D The private exponent. This may be \c NULL. + * \param E The public exponent. This may be \c NULL. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_rsa_import(mbedtls_rsa_context *ctx, + const mbedtls_mpi *N, + const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, const mbedtls_mpi *E); + +/** + * \brief This function imports core RSA parameters, in raw big-endian + * binary format, into an RSA context. + * + * \note This function can be called multiple times for successive + * imports, if the parameters are not simultaneously present. + * + * Any sequence of calls to this function should be followed + * by a call to mbedtls_rsa_complete(), which checks and + * completes the provided information to a ready-for-use + * public or private RSA key. + * + * \note See mbedtls_rsa_complete() for more information on which + * parameters are necessary to set up a private or public + * RSA key. + * + * \note The imported parameters are copied and need not be preserved + * for the lifetime of the RSA context being set up. + * + * \param ctx The initialized RSA context to store the parameters in. + * \param N The RSA modulus. This may be \c NULL. + * \param N_len The Byte length of \p N; it is ignored if \p N == NULL. + * \param P The first prime factor of \p N. This may be \c NULL. + * \param P_len The Byte length of \p P; it is ignored if \p P == NULL. + * \param Q The second prime factor of \p N. This may be \c NULL. + * \param Q_len The Byte length of \p Q; it is ignored if \p Q == NULL. + * \param D The private exponent. This may be \c NULL. + * \param D_len The Byte length of \p D; it is ignored if \p D == NULL. + * \param E The public exponent. This may be \c NULL. + * \param E_len The Byte length of \p E; it is ignored if \p E == NULL. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_rsa_import_raw(mbedtls_rsa_context *ctx, + unsigned char const *N, size_t N_len, + unsigned char const *P, size_t P_len, + unsigned char const *Q, size_t Q_len, + unsigned char const *D, size_t D_len, + unsigned char const *E, size_t E_len); + +/** + * \brief This function completes an RSA context from + * a set of imported core parameters. + * + * To setup an RSA public key, precisely \c N and \c E + * must have been imported. + * + * To setup an RSA private key, sufficient information must + * be present for the other parameters to be derivable. + * + * The default implementation supports the following: + *
  • Derive \c P, \c Q from \c N, \c D, \c E.
    • + *
  • Derive \c N, \c D from \c P, \c Q, \c E.
+ * Alternative implementations need not support these. + * + * If this function runs successfully, it guarantees that + * the RSA context can be used for RSA operations without + * the risk of failure or crash. + * + * \warning This function need not perform consistency checks + * for the imported parameters. In particular, parameters that + * are not needed by the implementation might be silently + * discarded and left unchecked. To check the consistency + * of the key material, see mbedtls_rsa_check_privkey(). + * + * \param ctx The initialized RSA context holding imported parameters. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_RSA_BAD_INPUT_DATA if the attempted derivations + * failed. + * + */ +int mbedtls_rsa_complete(mbedtls_rsa_context *ctx); + +/** + * \brief This function exports the core parameters of an RSA key. + * + * If this function runs successfully, the non-NULL buffers + * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully + * written, with additional unused space filled leading by + * zero Bytes. + * + * Possible reasons for returning + * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    + *
  • An alternative RSA implementation is in use, which + * stores the key externally, and either cannot or should + * not export it into RAM.
    • + *
  • A SW or HW implementation might not support a certain + * deduction. For example, \p P, \p Q from \p N, \p D, + * and \p E if the former are not part of the + * implementation.
+ * + * If the function fails due to an unsupported operation, + * the RSA context stays intact and remains usable. + * + * \param ctx The initialized RSA context. + * \param N The MPI to hold the RSA modulus. + * This may be \c NULL if this field need not be exported. + * \param P The MPI to hold the first prime factor of \p N. + * This may be \c NULL if this field need not be exported. + * \param Q The MPI to hold the second prime factor of \p N. + * This may be \c NULL if this field need not be exported. + * \param D The MPI to hold the private exponent. + * This may be \c NULL if this field need not be exported. + * \param E The MPI to hold the public exponent. + * This may be \c NULL if this field need not be exported. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the + * requested parameters cannot be done due to missing + * functionality or because of security policies. + * \return A non-zero return code on any other failure. + * + */ +int mbedtls_rsa_export(const mbedtls_rsa_context *ctx, + mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, + mbedtls_mpi *D, mbedtls_mpi *E); + +/** + * \brief This function exports core parameters of an RSA key + * in raw big-endian binary format. + * + * If this function runs successfully, the non-NULL buffers + * pointed to by \p N, \p P, \p Q, \p D, and \p E are fully + * written, with additional unused space filled leading by + * zero Bytes. + * + * Possible reasons for returning + * #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED:
    + *
  • An alternative RSA implementation is in use, which + * stores the key externally, and either cannot or should + * not export it into RAM.
    • + *
  • A SW or HW implementation might not support a certain + * deduction. For example, \p P, \p Q from \p N, \p D, + * and \p E if the former are not part of the + * implementation.
+ * If the function fails due to an unsupported operation, + * the RSA context stays intact and remains usable. + * + * \note The length parameters are ignored if the corresponding + * buffer pointers are NULL. + * + * \param ctx The initialized RSA context. + * \param N The Byte array to store the RSA modulus, + * or \c NULL if this field need not be exported. + * \param N_len The size of the buffer for the modulus. + * \param P The Byte array to hold the first prime factor of \p N, + * or \c NULL if this field need not be exported. + * \param P_len The size of the buffer for the first prime factor. + * \param Q The Byte array to hold the second prime factor of \p N, + * or \c NULL if this field need not be exported. + * \param Q_len The size of the buffer for the second prime factor. + * \param D The Byte array to hold the private exponent, + * or \c NULL if this field need not be exported. + * \param D_len The size of the buffer for the private exponent. + * \param E The Byte array to hold the public exponent, + * or \c NULL if this field need not be exported. + * \param E_len The size of the buffer for the public exponent. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED if exporting the + * requested parameters cannot be done due to missing + * functionality or because of security policies. + * \return A non-zero return code on any other failure. + */ +int mbedtls_rsa_export_raw(const mbedtls_rsa_context *ctx, + unsigned char *N, size_t N_len, + unsigned char *P, size_t P_len, + unsigned char *Q, size_t Q_len, + unsigned char *D, size_t D_len, + unsigned char *E, size_t E_len); + +/** + * \brief This function exports CRT parameters of a private RSA key. + * + * \note Alternative RSA implementations not using CRT-parameters + * internally can implement this function based on + * mbedtls_rsa_deduce_opt(). + * + * \param ctx The initialized RSA context. + * \param DP The MPI to hold \c D modulo `P-1`, + * or \c NULL if it need not be exported. + * \param DQ The MPI to hold \c D modulo `Q-1`, + * or \c NULL if it need not be exported. + * \param QP The MPI to hold modular inverse of \c Q modulo \c P, + * or \c NULL if it need not be exported. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + * + */ +int mbedtls_rsa_export_crt(const mbedtls_rsa_context *ctx, + mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP); + +/** + * \brief This function retrieves the length of RSA modulus in Bytes. + * + * \param ctx The initialized RSA context. + * + * \return The length of the RSA modulus in Bytes. + * + */ +size_t mbedtls_rsa_get_len(const mbedtls_rsa_context *ctx); + +/** + * \brief This function generates an RSA keypair. + * + * \note mbedtls_rsa_init() must be called before this function, + * to set up the RSA context. + * + * \param ctx The initialized RSA context used to hold the key. + * \param f_rng The RNG function to be used for key generation. + * This is mandatory and must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. + * This may be \c NULL if \p f_rng doesn't need a context. + * \param nbits The size of the public key in bits. + * \param exponent The public exponent to use. For example, \c 65537. + * This must be odd and greater than \c 1. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_gen_key(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + unsigned int nbits, int exponent); + +/** + * \brief This function checks if a context contains at least an RSA + * public key. + * + * If the function runs successfully, it is guaranteed that + * enough information is present to perform an RSA public key + * operation using mbedtls_rsa_public(). + * + * \param ctx The initialized RSA context to check. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_check_pubkey(const mbedtls_rsa_context *ctx); + +/** + * \brief This function checks if a context contains an RSA private key + * and perform basic consistency checks. + * + * \note The consistency checks performed by this function not only + * ensure that mbedtls_rsa_private() can be called successfully + * on the given context, but that the various parameters are + * mutually consistent with high probability, in the sense that + * mbedtls_rsa_public() and mbedtls_rsa_private() are inverses. + * + * \warning This function should catch accidental misconfigurations + * like swapping of parameters, but it cannot establish full + * trust in neither the quality nor the consistency of the key + * material that was used to setup the given RSA context: + *
  • Consistency: Imported parameters that are irrelevant + * for the implementation might be silently dropped. If dropped, + * the current function does not have access to them, + * and therefore cannot check them. See mbedtls_rsa_complete(). + * If you want to check the consistency of the entire + * content of a PKCS1-encoded RSA private key, for example, you + * should use mbedtls_rsa_validate_params() before setting + * up the RSA context. + * Additionally, if the implementation performs empirical checks, + * these checks substantiate but do not guarantee consistency.
    • + *
  • Quality: This function is not expected to perform + * extended quality assessments like checking that the prime + * factors are safe. Additionally, it is the responsibility of the + * user to ensure the trustworthiness of the source of his RSA + * parameters, which goes beyond what is effectively checkable + * by the library.
+ * + * \param ctx The initialized RSA context to check. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_check_privkey(const mbedtls_rsa_context *ctx); + +/** + * \brief This function checks a public-private RSA key pair. + * + * It checks each of the contexts, and makes sure they match. + * + * \param pub The initialized RSA context holding the public key. + * \param prv The initialized RSA context holding the private key. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_check_pub_priv(const mbedtls_rsa_context *pub, + const mbedtls_rsa_context *prv); + +/** + * \brief This function performs an RSA public key operation. + * + * \param ctx The initialized RSA context to use. + * \param input The input buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \note This function does not handle message padding. + * + * \note Make sure to set \p input[0] = 0 or ensure that + * input is smaller than \c N. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_public(mbedtls_rsa_context *ctx, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function performs an RSA private key operation. + * + * \note Blinding is used if and only if a PRNG is provided. + * + * \note If blinding is used, both the base of exponentiation + * and the exponent are blinded, providing protection + * against some side-channel attacks. + * + * \warning It is deprecated and a security risk to not provide + * a PRNG here and thereby prevent the use of blinding. + * Future versions of the library may enforce the presence + * of a PRNG. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function, used for blinding. It is mandatory. + * \param p_rng The RNG context to pass to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context. + * \param input The input buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_private(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function adds the message padding, then performs an RSA + * operation. + * + * It is the generic wrapper for performing a PKCS#1 encryption + * operation. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG to use. It is used for padding generation + * and it is mandatory. + * \param p_rng The RNG context to be passed to \p f_rng. May be + * \c NULL if \p f_rng doesn't need a context argument. + * \param ilen The length of the plaintext in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. It may be \c NULL if + * `ilen == 0`. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_encrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + size_t ilen, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function performs a PKCS#1 v1.5 encryption operation + * (RSAES-PKCS1-v1_5-ENCRYPT). + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function to use. It is mandatory and used for + * padding generation. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * \param ilen The length of the plaintext in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. It may be \c NULL if + * `ilen == 0`. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_pkcs1_v15_encrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + size_t ilen, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function performs a PKCS#1 v2.1 OAEP encryption + * operation (RSAES-OAEP-ENCRYPT). + * + * \note The output buffer must be as large as the size + * of ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function to use. This is needed for padding + * generation and is mandatory. + * \param p_rng The RNG context to be passed to \p f_rng. This may + * be \c NULL if \p f_rng doesn't need a context argument. + * \param label The buffer holding the custom label to use. + * This must be a readable buffer of length \p label_len + * Bytes. It may be \c NULL if \p label_len is \c 0. + * \param label_len The length of the label in Bytes. + * \param ilen The length of the plaintext buffer \p input in Bytes. + * \param input The input data to encrypt. This must be a readable + * buffer of size \p ilen Bytes. It may be \c NULL if + * `ilen == 0`. + * \param output The output buffer. This must be a writable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_oaep_encrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *label, size_t label_len, + size_t ilen, + const unsigned char *input, + unsigned char *output); + +/** + * \brief This function performs an RSA operation, then removes the + * message padding. + * + * It is the generic wrapper for performing a PKCS#1 decryption + * operation. + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N (for example, + * 128 Bytes if RSA-1024 is used) to be able to hold an + * arbitrary decrypted message. If it is not large enough to + * hold the decryption of the particular ciphertext provided, + * the function returns \c MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. This is used for blinding and is + * mandatory; see mbedtls_rsa_private() for more. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context. + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_decrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len); + +/** + * \brief This function performs a PKCS#1 v1.5 decryption + * operation (RSAES-PKCS1-v1_5-DECRYPT). + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N, for example, + * 128 Bytes if RSA-1024 is used, to be able to hold an + * arbitrary decrypted message. If it is not large enough to + * hold the decryption of the particular ciphertext provided, + * the function returns #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. This is used for blinding and is + * mandatory; see mbedtls_rsa_private() for more. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context. + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + * + */ +int mbedtls_rsa_rsaes_pkcs1_v15_decrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len); + +/** + * \brief This function performs a PKCS#1 v2.1 OAEP decryption + * operation (RSAES-OAEP-DECRYPT). + * + * \note The output buffer length \c output_max_len should be + * as large as the size \p ctx->len of \p ctx->N, for + * example, 128 Bytes if RSA-1024 is used, to be able to + * hold an arbitrary decrypted message. If it is not + * large enough to hold the decryption of the particular + * ciphertext provided, the function returns + * #MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. This is used for blinding and is + * mandatory. + * \param p_rng The RNG context to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context. + * \param label The buffer holding the custom label to use. + * This must be a readable buffer of length \p label_len + * Bytes. It may be \c NULL if \p label_len is \c 0. + * \param label_len The length of the label in Bytes. + * \param olen The address at which to store the length of + * the plaintext. This must not be \c NULL. + * \param input The ciphertext buffer. This must be a readable buffer + * of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * \param output The buffer used to hold the plaintext. This must + * be a writable buffer of length \p output_max_len Bytes. + * \param output_max_len The length in Bytes of the output buffer \p output. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsaes_oaep_decrypt(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *label, size_t label_len, + size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len); + +/** + * \brief This function performs a private RSA operation to sign + * a message digest using PKCS#1. + * + * It is the generic wrapper for performing a PKCS#1 + * signature. + * + * \note The \p sig buffer must be as large as the size + * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \note For PKCS#1 v2.1 encoding, see comments on + * mbedtls_rsa_rsassa_pss_sign() for details on + * \p md_alg and \p hash_id. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function to use. This is mandatory and + * must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_sign(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v1.5 signature + * operation (RSASSA-PKCS1-v1_5-SIGN). + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. This is used for blinding and is + * mandatory; see mbedtls_rsa_private() for more. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pkcs1_v15_sign(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS signature + * operation (RSASSA-PSS-SIGN). + * + * \note The \c hash_id set in \p ctx by calling + * mbedtls_rsa_set_padding() selects the hash used for the + * encoding operation and for the mask generation function + * (MGF1). For more details on the encoding operation and the + * mask generation function, consult RFC-3447: Public-Key + * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography + * Specifications. + * + * \note This function enforces that the provided salt length complies + * with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1 v2.2) §9.1.1 + * step 3. The constraint is that the hash length plus the salt + * length plus 2 bytes must be at most the key length. If this + * constraint is not met, this function returns + * #MBEDTLS_ERR_RSA_BAD_INPUT_DATA. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. It is mandatory and must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param saltlen The length of the salt that should be used. + * If passed #MBEDTLS_RSA_SALT_LEN_ANY, the function will use + * the largest possible salt length up to the hash length, + * which is the largest permitted by some standards including + * FIPS 186-4 §5.5. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_sign_ext(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + int saltlen, + unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS signature + * operation (RSASSA-PSS-SIGN). + * + * \note The \c hash_id set in \p ctx by calling + * mbedtls_rsa_set_padding() selects the hash used for the + * encoding operation and for the mask generation function + * (MGF1). For more details on the encoding operation and the + * mask generation function, consult RFC-3447: Public-Key + * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography + * Specifications. + * + * \note This function always uses the maximum possible salt size, + * up to the length of the payload hash. This choice of salt + * size complies with FIPS 186-4 §5.5 (e) and RFC 8017 (PKCS#1 + * v2.2) §9.1.1 step 3. Furthermore this function enforces a + * minimum salt size which is the hash size minus 2 bytes. If + * this minimum size is too large given the key size (the salt + * size, plus the hash size, plus 2 bytes must be no more than + * the key size in bytes), this function returns + * #MBEDTLS_ERR_RSA_BAD_INPUT_DATA. + * + * \param ctx The initialized RSA context to use. + * \param f_rng The RNG function. It is mandatory and must not be \c NULL. + * \param p_rng The RNG context to be passed to \p f_rng. This may be \c NULL + * if \p f_rng doesn't need a context argument. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer to hold the signature. This must be a writable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. + * + * \return \c 0 if the signing operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_sign(mbedtls_rsa_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig); + +/** + * \brief This function performs a public RSA operation and checks + * the message digest. + * + * This is the generic wrapper for performing a PKCS#1 + * verification. + * + * \note For PKCS#1 v2.1 encoding, see comments on + * mbedtls_rsa_rsassa_pss_verify() about \c md_alg and + * \c hash_id. + * + * \param ctx The initialized RSA public key context to use. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_pkcs1_verify(mbedtls_rsa_context *ctx, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v1.5 verification + * operation (RSASSA-PKCS1-v1_5-VERIFY). + * + * \param ctx The initialized RSA public key context to use. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pkcs1_v15_verify(mbedtls_rsa_context *ctx, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS verification + * operation (RSASSA-PSS-VERIFY). + * + * \note The \c hash_id set in \p ctx by calling + * mbedtls_rsa_set_padding() selects the hash used for the + * encoding operation and for the mask generation function + * (MGF1). For more details on the encoding operation and the + * mask generation function, consult RFC-3447: Public-Key + * Cryptography Standards (PKCS) #1 v2.1: RSA Cryptography + * Specifications. If the \c hash_id set in \p ctx by + * mbedtls_rsa_set_padding() is #MBEDTLS_MD_NONE, the \p md_alg + * parameter is used. + * + * \param ctx The initialized RSA public key context to use. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_verify(mbedtls_rsa_context *ctx, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + const unsigned char *sig); + +/** + * \brief This function performs a PKCS#1 v2.1 PSS verification + * operation (RSASSA-PSS-VERIFY). + * + * \note The \p sig buffer must be as large as the size + * of \p ctx->N. For example, 128 Bytes if RSA-1024 is used. + * + * \note The \c hash_id set in \p ctx by mbedtls_rsa_set_padding() is + * ignored. + * + * \param ctx The initialized RSA public key context to use. + * \param md_alg The message-digest algorithm used to hash the original data. + * Use #MBEDTLS_MD_NONE for signing raw data. + * \param hashlen The length of the message digest or raw data in Bytes. + * If \p md_alg is not #MBEDTLS_MD_NONE, this must match the + * output length of the corresponding hash algorithm. + * \param hash The buffer holding the message digest or raw data. + * This must be a readable buffer of at least \p hashlen Bytes. + * \param mgf1_hash_id The message digest algorithm used for the + * verification operation and the mask generation + * function (MGF1). For more details on the encoding + * operation and the mask generation function, consult + * RFC-3447: Public-Key Cryptography Standards + * (PKCS) #1 v2.1: RSA Cryptography + * Specifications. + * \param expected_salt_len The length of the salt used in padding. Use + * #MBEDTLS_RSA_SALT_LEN_ANY to accept any salt length. + * \param sig The buffer holding the signature. This must be a readable + * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes + * for an 2048-bit RSA modulus. + * + * \return \c 0 if the verify operation was successful. + * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. + */ +int mbedtls_rsa_rsassa_pss_verify_ext(mbedtls_rsa_context *ctx, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + mbedtls_md_type_t mgf1_hash_id, + int expected_salt_len, + const unsigned char *sig); + +/** + * \brief This function copies the components of an RSA context. + * + * \param dst The destination context. This must be initialized. + * \param src The source context. This must be initialized. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory allocation failure. + */ +int mbedtls_rsa_copy(mbedtls_rsa_context *dst, const mbedtls_rsa_context *src); + +/** + * \brief This function frees the components of an RSA key. + * + * \param ctx The RSA context to free. May be \c NULL, in which case + * this function is a no-op. If it is not \c NULL, it must + * point to an initialized RSA context. + */ +void mbedtls_rsa_free(mbedtls_rsa_context *ctx); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The RSA checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_rsa_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* rsa.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha1.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha1.h index 18bde93..ca1106d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha1.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha1.h @@ -1,231 +1,231 @@ -/** - * \file sha1.h - * - * \brief This file contains SHA-1 definitions and functions. - * - * The Secure Hash Algorithm 1 (SHA-1) cryptographic hash function is defined in - * FIPS 180-4: Secure Hash Standard (SHS). - * - * \warning SHA-1 is considered a weak message digest and its use constitutes - * a security risk. We recommend considering stronger message - * digests instead. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SHA1_H -#define MBEDTLS_SHA1_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -/** SHA-1 input data was malformed. */ -#define MBEDTLS_ERR_SHA1_BAD_INPUT_DATA -0x0073 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_SHA1_ALT) -// Regular implementation -// - -/** - * \brief The SHA-1 context structure. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - */ -typedef struct mbedtls_sha1_context { - uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ - uint32_t MBEDTLS_PRIVATE(state)[5]; /*!< The intermediate digest state. */ - unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< The data block being processed. */ -} -mbedtls_sha1_context; - -#else /* MBEDTLS_SHA1_ALT */ -#include "sha1_alt.h" -#endif /* MBEDTLS_SHA1_ALT */ - -/** - * \brief This function initializes a SHA-1 context. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context to initialize. - * This must not be \c NULL. - * - */ -void mbedtls_sha1_init(mbedtls_sha1_context *ctx); - -/** - * \brief This function clears a SHA-1 context. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context to clear. This may be \c NULL, - * in which case this function does nothing. If it is - * not \c NULL, it must point to an initialized - * SHA-1 context. - * - */ -void mbedtls_sha1_free(mbedtls_sha1_context *ctx); - -/** - * \brief This function clones the state of a SHA-1 context. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param dst The SHA-1 context to clone to. This must be initialized. - * \param src The SHA-1 context to clone from. This must be initialized. - * - */ -void mbedtls_sha1_clone(mbedtls_sha1_context *dst, - const mbedtls_sha1_context *src); - -/** - * \brief This function starts a SHA-1 checksum calculation. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context to initialize. This must be initialized. - * - * \return \c 0 on success. - * \return A negative error code on failure. - * - */ -int mbedtls_sha1_starts(mbedtls_sha1_context *ctx); - -/** - * \brief This function feeds an input buffer into an ongoing SHA-1 - * checksum calculation. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context. This must be initialized - * and have a hash operation started. - * \param input The buffer holding the input data. - * This must be a readable buffer of length \p ilen Bytes. - * \param ilen The length of the input data \p input in Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha1_update(mbedtls_sha1_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief This function finishes the SHA-1 operation, and writes - * the result to the output buffer. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context to use. This must be initialized and - * have a hash operation started. - * \param output The SHA-1 checksum result. This must be a writable - * buffer of length \c 20 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha1_finish(mbedtls_sha1_context *ctx, - unsigned char output[20]); - -/** - * \brief SHA-1 process data block (internal use only). - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param ctx The SHA-1 context to use. This must be initialized. - * \param data The data block being processed. This must be a - * readable buffer of length \c 64 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - * - */ -int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, - const unsigned char data[64]); - -/** - * \brief This function calculates the SHA-1 checksum of a buffer. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The SHA-1 result is calculated as - * output = SHA-1(input buffer). - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \param input The buffer holding the input data. - * This must be a readable buffer of length \p ilen Bytes. - * \param ilen The length of the input data \p input in Bytes. - * \param output The SHA-1 checksum result. - * This must be a writable buffer of length \c 20 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - * - */ -int mbedtls_sha1(const unsigned char *input, - size_t ilen, - unsigned char output[20]); - -#if defined(MBEDTLS_SELF_TEST) - -/** - * \brief The SHA-1 checkup routine. - * - * \warning SHA-1 is considered a weak message digest and its use - * constitutes a security risk. We recommend considering - * stronger message digests instead. - * - * \return \c 0 on success. - * \return \c 1 on failure. - * - */ -int mbedtls_sha1_self_test(int verbose); - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_sha1.h */ +/** + * \file sha1.h + * + * \brief This file contains SHA-1 definitions and functions. + * + * The Secure Hash Algorithm 1 (SHA-1) cryptographic hash function is defined in + * FIPS 180-4: Secure Hash Standard (SHS). + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. We recommend considering stronger message + * digests instead. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SHA1_H +#define MBEDTLS_SHA1_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +/** SHA-1 input data was malformed. */ +#define MBEDTLS_ERR_SHA1_BAD_INPUT_DATA -0x0073 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_SHA1_ALT) +// Regular implementation +// + +/** + * \brief The SHA-1 context structure. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + */ +typedef struct mbedtls_sha1_context { + uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ + uint32_t MBEDTLS_PRIVATE(state)[5]; /*!< The intermediate digest state. */ + unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< The data block being processed. */ +} +mbedtls_sha1_context; + +#else /* MBEDTLS_SHA1_ALT */ +#include "sha1_alt.h" +#endif /* MBEDTLS_SHA1_ALT */ + +/** + * \brief This function initializes a SHA-1 context. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context to initialize. + * This must not be \c NULL. + * + */ +void mbedtls_sha1_init(mbedtls_sha1_context *ctx); + +/** + * \brief This function clears a SHA-1 context. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context to clear. This may be \c NULL, + * in which case this function does nothing. If it is + * not \c NULL, it must point to an initialized + * SHA-1 context. + * + */ +void mbedtls_sha1_free(mbedtls_sha1_context *ctx); + +/** + * \brief This function clones the state of a SHA-1 context. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param dst The SHA-1 context to clone to. This must be initialized. + * \param src The SHA-1 context to clone from. This must be initialized. + * + */ +void mbedtls_sha1_clone(mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src); + +/** + * \brief This function starts a SHA-1 checksum calculation. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context to initialize. This must be initialized. + * + * \return \c 0 on success. + * \return A negative error code on failure. + * + */ +int mbedtls_sha1_starts(mbedtls_sha1_context *ctx); + +/** + * \brief This function feeds an input buffer into an ongoing SHA-1 + * checksum calculation. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the input data. + * This must be a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data \p input in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha1_update(mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief This function finishes the SHA-1 operation, and writes + * the result to the output buffer. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context to use. This must be initialized and + * have a hash operation started. + * \param output The SHA-1 checksum result. This must be a writable + * buffer of length \c 20 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha1_finish(mbedtls_sha1_context *ctx, + unsigned char output[20]); + +/** + * \brief SHA-1 process data block (internal use only). + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param ctx The SHA-1 context to use. This must be initialized. + * \param data The data block being processed. This must be a + * readable buffer of length \c 64 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + * + */ +int mbedtls_internal_sha1_process(mbedtls_sha1_context *ctx, + const unsigned char data[64]); + +/** + * \brief This function calculates the SHA-1 checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-1 result is calculated as + * output = SHA-1(input buffer). + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \param input The buffer holding the input data. + * This must be a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data \p input in Bytes. + * \param output The SHA-1 checksum result. + * This must be a writable buffer of length \c 20 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + * + */ +int mbedtls_sha1(const unsigned char *input, + size_t ilen, + unsigned char output[20]); + +#if defined(MBEDTLS_SELF_TEST) + +/** + * \brief The SHA-1 checkup routine. + * + * \warning SHA-1 is considered a weak message digest and its use + * constitutes a security risk. We recommend considering + * stronger message digests instead. + * + * \return \c 0 on success. + * \return \c 1 on failure. + * + */ +int mbedtls_sha1_self_test(int verbose); + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha1.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha256.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha256.h index 87e259f..d9c4ff7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha256.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha256.h @@ -1,210 +1,210 @@ -/** - * \file sha256.h - * - * \brief This file contains SHA-224 and SHA-256 definitions and functions. - * - * The Secure Hash Algorithms 224 and 256 (SHA-224 and SHA-256) cryptographic - * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SHA256_H -#define MBEDTLS_SHA256_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -/** SHA-256 input data was malformed. */ -#define MBEDTLS_ERR_SHA256_BAD_INPUT_DATA -0x0074 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_SHA256_ALT) -// Regular implementation -// - -/** - * \brief The SHA-256 context structure. - * - * The structure is used both for SHA-256 and for SHA-224 - * checksum calculations. The choice between these two is - * made in the call to mbedtls_sha256_starts(). - */ -typedef struct mbedtls_sha256_context { - unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< The data block being processed. */ - uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ - uint32_t MBEDTLS_PRIVATE(state)[8]; /*!< The intermediate digest state. */ - int MBEDTLS_PRIVATE(is224); /*!< Determines which function to use: - 0: Use SHA-256, or 1: Use SHA-224. */ -} -mbedtls_sha256_context; - -#else /* MBEDTLS_SHA256_ALT */ -#include "sha256_alt.h" -#endif /* MBEDTLS_SHA256_ALT */ - -/** - * \brief This function initializes a SHA-256 context. - * - * \param ctx The SHA-256 context to initialize. This must not be \c NULL. - */ -void mbedtls_sha256_init(mbedtls_sha256_context *ctx); - -/** - * \brief This function clears a SHA-256 context. - * - * \param ctx The SHA-256 context to clear. This may be \c NULL, in which - * case this function returns immediately. If it is not \c NULL, - * it must point to an initialized SHA-256 context. - */ -void mbedtls_sha256_free(mbedtls_sha256_context *ctx); - -/** - * \brief This function clones the state of a SHA-256 context. - * - * \param dst The destination context. This must be initialized. - * \param src The context to clone. This must be initialized. - */ -void mbedtls_sha256_clone(mbedtls_sha256_context *dst, - const mbedtls_sha256_context *src); - -/** - * \brief This function starts a SHA-224 or SHA-256 checksum - * calculation. - * - * \param ctx The context to use. This must be initialized. - * \param is224 This determines which function to use. This must be - * either \c 0 for SHA-256, or \c 1 for SHA-224. - * - * \note is224 must be defined accordingly to the enabled - * MBEDTLS_SHA224_C/MBEDTLS_SHA256_C symbols otherwise the - * function will return #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224); - -/** - * \brief This function feeds an input buffer into an ongoing - * SHA-256 checksum calculation. - * - * \param ctx The SHA-256 context. This must be initialized - * and have a hash operation started. - * \param input The buffer holding the data. This must be a readable - * buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha256_update(mbedtls_sha256_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief This function finishes the SHA-256 operation, and writes - * the result to the output buffer. - * - * \param ctx The SHA-256 context. This must be initialized - * and have a hash operation started. - * \param output The SHA-224 or SHA-256 checksum result. - * This must be a writable buffer of length \c 32 bytes - * for SHA-256, \c 28 bytes for SHA-224. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, - unsigned char *output); - -/** - * \brief This function processes a single data block within - * the ongoing SHA-256 computation. This function is for - * internal use only. - * - * \param ctx The SHA-256 context. This must be initialized. - * \param data The buffer holding one block of data. This must - * be a readable buffer of length \c 64 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, - const unsigned char data[64]); - -/** - * \brief This function calculates the SHA-224 or SHA-256 - * checksum of a buffer. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The SHA-256 result is calculated as - * output = SHA-256(input buffer). - * - * \param input The buffer holding the data. This must be a readable - * buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * \param output The SHA-224 or SHA-256 checksum result. - * This must be a writable buffer of length \c 32 bytes - * for SHA-256, \c 28 bytes for SHA-224. - * \param is224 Determines which function to use. This must be - * either \c 0 for SHA-256, or \c 1 for SHA-224. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha256(const unsigned char *input, - size_t ilen, - unsigned char *output, - int is224); - -#if defined(MBEDTLS_SELF_TEST) - -#if defined(MBEDTLS_SHA224_C) -/** - * \brief The SHA-224 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_sha224_self_test(int verbose); -#endif /* MBEDTLS_SHA224_C */ - -#if defined(MBEDTLS_SHA256_C) -/** - * \brief The SHA-256 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_sha256_self_test(int verbose); -#endif /* MBEDTLS_SHA256_C */ - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_sha256.h */ +/** + * \file sha256.h + * + * \brief This file contains SHA-224 and SHA-256 definitions and functions. + * + * The Secure Hash Algorithms 224 and 256 (SHA-224 and SHA-256) cryptographic + * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SHA256_H +#define MBEDTLS_SHA256_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +/** SHA-256 input data was malformed. */ +#define MBEDTLS_ERR_SHA256_BAD_INPUT_DATA -0x0074 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_SHA256_ALT) +// Regular implementation +// + +/** + * \brief The SHA-256 context structure. + * + * The structure is used both for SHA-256 and for SHA-224 + * checksum calculations. The choice between these two is + * made in the call to mbedtls_sha256_starts(). + */ +typedef struct mbedtls_sha256_context { + unsigned char MBEDTLS_PRIVATE(buffer)[64]; /*!< The data block being processed. */ + uint32_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ + uint32_t MBEDTLS_PRIVATE(state)[8]; /*!< The intermediate digest state. */ + int MBEDTLS_PRIVATE(is224); /*!< Determines which function to use: + 0: Use SHA-256, or 1: Use SHA-224. */ +} +mbedtls_sha256_context; + +#else /* MBEDTLS_SHA256_ALT */ +#include "sha256_alt.h" +#endif /* MBEDTLS_SHA256_ALT */ + +/** + * \brief This function initializes a SHA-256 context. + * + * \param ctx The SHA-256 context to initialize. This must not be \c NULL. + */ +void mbedtls_sha256_init(mbedtls_sha256_context *ctx); + +/** + * \brief This function clears a SHA-256 context. + * + * \param ctx The SHA-256 context to clear. This may be \c NULL, in which + * case this function returns immediately. If it is not \c NULL, + * it must point to an initialized SHA-256 context. + */ +void mbedtls_sha256_free(mbedtls_sha256_context *ctx); + +/** + * \brief This function clones the state of a SHA-256 context. + * + * \param dst The destination context. This must be initialized. + * \param src The context to clone. This must be initialized. + */ +void mbedtls_sha256_clone(mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src); + +/** + * \brief This function starts a SHA-224 or SHA-256 checksum + * calculation. + * + * \param ctx The context to use. This must be initialized. + * \param is224 This determines which function to use. This must be + * either \c 0 for SHA-256, or \c 1 for SHA-224. + * + * \note is224 must be defined accordingly to the enabled + * MBEDTLS_SHA224_C/MBEDTLS_SHA256_C symbols otherwise the + * function will return #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_starts(mbedtls_sha256_context *ctx, int is224); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-256 checksum calculation. + * + * \param ctx The SHA-256 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_update(mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief This function finishes the SHA-256 operation, and writes + * the result to the output buffer. + * + * \param ctx The SHA-256 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-224 or SHA-256 checksum result. + * This must be a writable buffer of length \c 32 bytes + * for SHA-256, \c 28 bytes for SHA-224. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256_finish(mbedtls_sha256_context *ctx, + unsigned char *output); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-256 computation. This function is for + * internal use only. + * + * \param ctx The SHA-256 context. This must be initialized. + * \param data The buffer holding one block of data. This must + * be a readable buffer of length \c 64 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx, + const unsigned char data[64]); + +/** + * \brief This function calculates the SHA-224 or SHA-256 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-256 result is calculated as + * output = SHA-256(input buffer). + * + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-224 or SHA-256 checksum result. + * This must be a writable buffer of length \c 32 bytes + * for SHA-256, \c 28 bytes for SHA-224. + * \param is224 Determines which function to use. This must be + * either \c 0 for SHA-256, or \c 1 for SHA-224. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha256(const unsigned char *input, + size_t ilen, + unsigned char *output, + int is224); + +#if defined(MBEDTLS_SELF_TEST) + +#if defined(MBEDTLS_SHA224_C) +/** + * \brief The SHA-224 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha224_self_test(int verbose); +#endif /* MBEDTLS_SHA224_C */ + +#if defined(MBEDTLS_SHA256_C) +/** + * \brief The SHA-256 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha256_self_test(int verbose); +#endif /* MBEDTLS_SHA256_C */ + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha256.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha3.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha3.h index 77748be..1329318 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha3.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha3.h @@ -1,184 +1,184 @@ -/** - * \file sha3.h - * - * \brief This file contains SHA-3 definitions and functions. - * - * The Secure Hash Algorithms cryptographic - * hash functions are defined in FIPS 202: SHA-3 Standard: - * Permutation-Based Hash and Extendable-Output Functions . - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_SHA3_H -#define MBEDTLS_SHA3_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** SHA-3 input data was malformed. */ -#define MBEDTLS_ERR_SHA3_BAD_INPUT_DATA -0x0076 - -/** - * SHA-3 family id. - * - * It identifies the family (SHA3-256, SHA3-512, etc.) - */ - -typedef enum { - MBEDTLS_SHA3_NONE = 0, /*!< Operation not defined. */ - MBEDTLS_SHA3_224, /*!< SHA3-224 */ - MBEDTLS_SHA3_256, /*!< SHA3-256 */ - MBEDTLS_SHA3_384, /*!< SHA3-384 */ - MBEDTLS_SHA3_512, /*!< SHA3-512 */ -} mbedtls_sha3_id; - -/** - * \brief The SHA-3 context structure. - * - * The structure is used SHA-3 checksum calculations. - */ -typedef struct { - uint64_t MBEDTLS_PRIVATE(state[25]); - uint32_t MBEDTLS_PRIVATE(index); - uint16_t MBEDTLS_PRIVATE(olen); - uint16_t MBEDTLS_PRIVATE(max_block_size); -} -mbedtls_sha3_context; - -/** - * \brief This function initializes a SHA-3 context. - * - * \param ctx The SHA-3 context to initialize. This must not be \c NULL. - */ -void mbedtls_sha3_init(mbedtls_sha3_context *ctx); - -/** - * \brief This function clears a SHA-3 context. - * - * \param ctx The SHA-3 context to clear. This may be \c NULL, in which - * case this function returns immediately. If it is not \c NULL, - * it must point to an initialized SHA-3 context. - */ -void mbedtls_sha3_free(mbedtls_sha3_context *ctx); - -/** - * \brief This function clones the state of a SHA-3 context. - * - * \param dst The destination context. This must be initialized. - * \param src The context to clone. This must be initialized. - */ -void mbedtls_sha3_clone(mbedtls_sha3_context *dst, - const mbedtls_sha3_context *src); - -/** - * \brief This function starts a SHA-3 checksum - * calculation. - * - * \param ctx The context to use. This must be initialized. - * \param id The id of the SHA-3 family. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha3_starts(mbedtls_sha3_context *ctx, mbedtls_sha3_id id); - -/** - * \brief This function feeds an input buffer into an ongoing - * SHA-3 checksum calculation. - * - * \param ctx The SHA-3 context. This must be initialized - * and have a hash operation started. - * \param input The buffer holding the data. This must be a readable - * buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha3_update(mbedtls_sha3_context *ctx, - const uint8_t *input, - size_t ilen); - -/** - * \brief This function finishes the SHA-3 operation, and writes - * the result to the output buffer. - * - * \param ctx The SHA-3 context. This must be initialized - * and have a hash operation started. - * \param output The SHA-3 checksum result. - * This must be a writable buffer of length \c olen bytes. - * \param olen Defines the length of output buffer (in bytes). For SHA-3 224, SHA-3 256, - * SHA-3 384 and SHA-3 512 \c olen must equal to 28, 32, 48 and 64, - * respectively. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha3_finish(mbedtls_sha3_context *ctx, - uint8_t *output, size_t olen); - -/** - * \brief This function calculates the SHA-3 - * checksum of a buffer. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The SHA-3 result is calculated as - * output = SHA-3(id, input buffer, d). - * - * \param id The id of the SHA-3 family. - * \param input The buffer holding the data. This must be a readable - * buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * \param output The SHA-3 checksum result. - * This must be a writable buffer of length \c olen bytes. - * \param olen Defines the length of output buffer (in bytes). For SHA-3 224, SHA-3 256, - * SHA-3 384 and SHA-3 512 \c olen must equal to 28, 32, 48 and 64, - * respectively. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha3(mbedtls_sha3_id id, const uint8_t *input, - size_t ilen, - uint8_t *output, - size_t olen); - -#if defined(MBEDTLS_SELF_TEST) -/** - * \brief Checkup routine for the algorithms implemented - * by this module: SHA3-224, SHA3-256, SHA3-384, SHA3-512. - * - * \return 0 if successful, or 1 if the test failed. - */ -int mbedtls_sha3_self_test(int verbose); -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_sha3.h */ +/** + * \file sha3.h + * + * \brief This file contains SHA-3 definitions and functions. + * + * The Secure Hash Algorithms cryptographic + * hash functions are defined in FIPS 202: SHA-3 Standard: + * Permutation-Based Hash and Extendable-Output Functions . + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SHA3_H +#define MBEDTLS_SHA3_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** SHA-3 input data was malformed. */ +#define MBEDTLS_ERR_SHA3_BAD_INPUT_DATA -0x0076 + +/** + * SHA-3 family id. + * + * It identifies the family (SHA3-256, SHA3-512, etc.) + */ + +typedef enum { + MBEDTLS_SHA3_NONE = 0, /*!< Operation not defined. */ + MBEDTLS_SHA3_224, /*!< SHA3-224 */ + MBEDTLS_SHA3_256, /*!< SHA3-256 */ + MBEDTLS_SHA3_384, /*!< SHA3-384 */ + MBEDTLS_SHA3_512, /*!< SHA3-512 */ +} mbedtls_sha3_id; + +/** + * \brief The SHA-3 context structure. + * + * The structure is used SHA-3 checksum calculations. + */ +typedef struct { + uint64_t MBEDTLS_PRIVATE(state[25]); + uint32_t MBEDTLS_PRIVATE(index); + uint16_t MBEDTLS_PRIVATE(olen); + uint16_t MBEDTLS_PRIVATE(max_block_size); +} +mbedtls_sha3_context; + +/** + * \brief This function initializes a SHA-3 context. + * + * \param ctx The SHA-3 context to initialize. This must not be \c NULL. + */ +void mbedtls_sha3_init(mbedtls_sha3_context *ctx); + +/** + * \brief This function clears a SHA-3 context. + * + * \param ctx The SHA-3 context to clear. This may be \c NULL, in which + * case this function returns immediately. If it is not \c NULL, + * it must point to an initialized SHA-3 context. + */ +void mbedtls_sha3_free(mbedtls_sha3_context *ctx); + +/** + * \brief This function clones the state of a SHA-3 context. + * + * \param dst The destination context. This must be initialized. + * \param src The context to clone. This must be initialized. + */ +void mbedtls_sha3_clone(mbedtls_sha3_context *dst, + const mbedtls_sha3_context *src); + +/** + * \brief This function starts a SHA-3 checksum + * calculation. + * + * \param ctx The context to use. This must be initialized. + * \param id The id of the SHA-3 family. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha3_starts(mbedtls_sha3_context *ctx, mbedtls_sha3_id id); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-3 checksum calculation. + * + * \param ctx The SHA-3 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha3_update(mbedtls_sha3_context *ctx, + const uint8_t *input, + size_t ilen); + +/** + * \brief This function finishes the SHA-3 operation, and writes + * the result to the output buffer. + * + * \param ctx The SHA-3 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-3 checksum result. + * This must be a writable buffer of length \c olen bytes. + * \param olen Defines the length of output buffer (in bytes). For SHA-3 224, SHA-3 256, + * SHA-3 384 and SHA-3 512 \c olen must equal to 28, 32, 48 and 64, + * respectively. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha3_finish(mbedtls_sha3_context *ctx, + uint8_t *output, size_t olen); + +/** + * \brief This function calculates the SHA-3 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-3 result is calculated as + * output = SHA-3(id, input buffer, d). + * + * \param id The id of the SHA-3 family. + * \param input The buffer holding the data. This must be a readable + * buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-3 checksum result. + * This must be a writable buffer of length \c olen bytes. + * \param olen Defines the length of output buffer (in bytes). For SHA-3 224, SHA-3 256, + * SHA-3 384 and SHA-3 512 \c olen must equal to 28, 32, 48 and 64, + * respectively. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha3(mbedtls_sha3_id id, const uint8_t *input, + size_t ilen, + uint8_t *output, + size_t olen); + +#if defined(MBEDTLS_SELF_TEST) +/** + * \brief Checkup routine for the algorithms implemented + * by this module: SHA3-224, SHA3-256, SHA3-384, SHA3-512. + * + * \return 0 if successful, or 1 if the test failed. + */ +int mbedtls_sha3_self_test(int verbose); +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha3.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha512.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha512.h index ea54678..898f3ad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha512.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/sha512.h @@ -1,220 +1,220 @@ -/** - * \file sha512.h - * \brief This file contains SHA-384 and SHA-512 definitions and functions. - * - * The Secure Hash Algorithms 384 and 512 (SHA-384 and SHA-512) cryptographic - * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SHA512_H -#define MBEDTLS_SHA512_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include -#include - -/** SHA-512 input data was malformed. */ -#define MBEDTLS_ERR_SHA512_BAD_INPUT_DATA -0x0075 - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_SHA512_ALT) -// Regular implementation -// - -/** - * \brief The SHA-512 context structure. - * - * The structure is used both for SHA-384 and for SHA-512 - * checksum calculations. The choice between these two is - * made in the call to mbedtls_sha512_starts(). - */ -typedef struct mbedtls_sha512_context { - uint64_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ - uint64_t MBEDTLS_PRIVATE(state)[8]; /*!< The intermediate digest state. */ - unsigned char MBEDTLS_PRIVATE(buffer)[128]; /*!< The data block being processed. */ -#if defined(MBEDTLS_SHA384_C) - int MBEDTLS_PRIVATE(is384); /*!< Determines which function to use: - 0: Use SHA-512, or 1: Use SHA-384. */ -#endif -} -mbedtls_sha512_context; - -#else /* MBEDTLS_SHA512_ALT */ -#include "sha512_alt.h" -#endif /* MBEDTLS_SHA512_ALT */ - -/** - * \brief This function initializes a SHA-512 context. - * - * \param ctx The SHA-512 context to initialize. This must - * not be \c NULL. - */ -void mbedtls_sha512_init(mbedtls_sha512_context *ctx); - -/** - * \brief This function clears a SHA-512 context. - * - * \param ctx The SHA-512 context to clear. This may be \c NULL, - * in which case this function does nothing. If it - * is not \c NULL, it must point to an initialized - * SHA-512 context. - */ -void mbedtls_sha512_free(mbedtls_sha512_context *ctx); - -/** - * \brief This function clones the state of a SHA-512 context. - * - * \param dst The destination context. This must be initialized. - * \param src The context to clone. This must be initialized. - */ -void mbedtls_sha512_clone(mbedtls_sha512_context *dst, - const mbedtls_sha512_context *src); - -/** - * \brief This function starts a SHA-384 or SHA-512 checksum - * calculation. - * - * \param ctx The SHA-512 context to use. This must be initialized. - * \param is384 Determines which function to use. This must be - * either \c 0 for SHA-512, or \c 1 for SHA-384. - * - * \note is384 must be defined accordingly to the enabled - * MBEDTLS_SHA384_C/MBEDTLS_SHA512_C symbols otherwise the - * function will return #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384); - -/** - * \brief This function feeds an input buffer into an ongoing - * SHA-512 checksum calculation. - * - * \param ctx The SHA-512 context. This must be initialized - * and have a hash operation started. - * \param input The buffer holding the input data. This must - * be a readable buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha512_update(mbedtls_sha512_context *ctx, - const unsigned char *input, - size_t ilen); - -/** - * \brief This function finishes the SHA-512 operation, and writes - * the result to the output buffer. - * - * \param ctx The SHA-512 context. This must be initialized - * and have a hash operation started. - * \param output The SHA-384 or SHA-512 checksum result. - * This must be a writable buffer of length \c 64 bytes - * for SHA-512, \c 48 bytes for SHA-384. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha512_finish(mbedtls_sha512_context *ctx, - unsigned char *output); - -/** - * \brief This function processes a single data block within - * the ongoing SHA-512 computation. - * This function is for internal use only. - * - * \param ctx The SHA-512 context. This must be initialized. - * \param data The buffer holding one block of data. This - * must be a readable buffer of length \c 128 Bytes. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_internal_sha512_process(mbedtls_sha512_context *ctx, - const unsigned char data[128]); - -/** - * \brief This function calculates the SHA-512 or SHA-384 - * checksum of a buffer. - * - * The function allocates the context, performs the - * calculation, and frees the context. - * - * The SHA-512 result is calculated as - * output = SHA-512(input buffer). - * - * \param input The buffer holding the input data. This must be - * a readable buffer of length \p ilen Bytes. - * \param ilen The length of the input data in Bytes. - * \param output The SHA-384 or SHA-512 checksum result. - * This must be a writable buffer of length \c 64 bytes - * for SHA-512, \c 48 bytes for SHA-384. - * \param is384 Determines which function to use. This must be either - * \c 0 for SHA-512, or \c 1 for SHA-384. - * - * \note is384 must be defined accordingly with the supported - * symbols in the config file. If: - * - is384 is 0, but \c MBEDTLS_SHA384_C is not defined, or - * - is384 is 1, but \c MBEDTLS_SHA512_C is not defined - * then the function will return - * #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_sha512(const unsigned char *input, - size_t ilen, - unsigned char *output, - int is384); - -#if defined(MBEDTLS_SELF_TEST) - -#if defined(MBEDTLS_SHA384_C) -/** - * \brief The SHA-384 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_sha384_self_test(int verbose); -#endif /* MBEDTLS_SHA384_C */ - -#if defined(MBEDTLS_SHA512_C) -/** - * \brief The SHA-512 checkup routine. - * - * \return \c 0 on success. - * \return \c 1 on failure. - */ -int mbedtls_sha512_self_test(int verbose); -#endif /* MBEDTLS_SHA512_C */ - -#endif /* MBEDTLS_SELF_TEST */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_sha512.h */ +/** + * \file sha512.h + * \brief This file contains SHA-384 and SHA-512 definitions and functions. + * + * The Secure Hash Algorithms 384 and 512 (SHA-384 and SHA-512) cryptographic + * hash functions are defined in FIPS 180-4: Secure Hash Standard (SHS). + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SHA512_H +#define MBEDTLS_SHA512_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include +#include + +/** SHA-512 input data was malformed. */ +#define MBEDTLS_ERR_SHA512_BAD_INPUT_DATA -0x0075 + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_SHA512_ALT) +// Regular implementation +// + +/** + * \brief The SHA-512 context structure. + * + * The structure is used both for SHA-384 and for SHA-512 + * checksum calculations. The choice between these two is + * made in the call to mbedtls_sha512_starts(). + */ +typedef struct mbedtls_sha512_context { + uint64_t MBEDTLS_PRIVATE(total)[2]; /*!< The number of Bytes processed. */ + uint64_t MBEDTLS_PRIVATE(state)[8]; /*!< The intermediate digest state. */ + unsigned char MBEDTLS_PRIVATE(buffer)[128]; /*!< The data block being processed. */ +#if defined(MBEDTLS_SHA384_C) + int MBEDTLS_PRIVATE(is384); /*!< Determines which function to use: + 0: Use SHA-512, or 1: Use SHA-384. */ +#endif +} +mbedtls_sha512_context; + +#else /* MBEDTLS_SHA512_ALT */ +#include "sha512_alt.h" +#endif /* MBEDTLS_SHA512_ALT */ + +/** + * \brief This function initializes a SHA-512 context. + * + * \param ctx The SHA-512 context to initialize. This must + * not be \c NULL. + */ +void mbedtls_sha512_init(mbedtls_sha512_context *ctx); + +/** + * \brief This function clears a SHA-512 context. + * + * \param ctx The SHA-512 context to clear. This may be \c NULL, + * in which case this function does nothing. If it + * is not \c NULL, it must point to an initialized + * SHA-512 context. + */ +void mbedtls_sha512_free(mbedtls_sha512_context *ctx); + +/** + * \brief This function clones the state of a SHA-512 context. + * + * \param dst The destination context. This must be initialized. + * \param src The context to clone. This must be initialized. + */ +void mbedtls_sha512_clone(mbedtls_sha512_context *dst, + const mbedtls_sha512_context *src); + +/** + * \brief This function starts a SHA-384 or SHA-512 checksum + * calculation. + * + * \param ctx The SHA-512 context to use. This must be initialized. + * \param is384 Determines which function to use. This must be + * either \c 0 for SHA-512, or \c 1 for SHA-384. + * + * \note is384 must be defined accordingly to the enabled + * MBEDTLS_SHA384_C/MBEDTLS_SHA512_C symbols otherwise the + * function will return #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_starts(mbedtls_sha512_context *ctx, int is384); + +/** + * \brief This function feeds an input buffer into an ongoing + * SHA-512 checksum calculation. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param input The buffer holding the input data. This must + * be a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_update(mbedtls_sha512_context *ctx, + const unsigned char *input, + size_t ilen); + +/** + * \brief This function finishes the SHA-512 operation, and writes + * the result to the output buffer. + * + * \param ctx The SHA-512 context. This must be initialized + * and have a hash operation started. + * \param output The SHA-384 or SHA-512 checksum result. + * This must be a writable buffer of length \c 64 bytes + * for SHA-512, \c 48 bytes for SHA-384. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512_finish(mbedtls_sha512_context *ctx, + unsigned char *output); + +/** + * \brief This function processes a single data block within + * the ongoing SHA-512 computation. + * This function is for internal use only. + * + * \param ctx The SHA-512 context. This must be initialized. + * \param data The buffer holding one block of data. This + * must be a readable buffer of length \c 128 Bytes. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_internal_sha512_process(mbedtls_sha512_context *ctx, + const unsigned char data[128]); + +/** + * \brief This function calculates the SHA-512 or SHA-384 + * checksum of a buffer. + * + * The function allocates the context, performs the + * calculation, and frees the context. + * + * The SHA-512 result is calculated as + * output = SHA-512(input buffer). + * + * \param input The buffer holding the input data. This must be + * a readable buffer of length \p ilen Bytes. + * \param ilen The length of the input data in Bytes. + * \param output The SHA-384 or SHA-512 checksum result. + * This must be a writable buffer of length \c 64 bytes + * for SHA-512, \c 48 bytes for SHA-384. + * \param is384 Determines which function to use. This must be either + * \c 0 for SHA-512, or \c 1 for SHA-384. + * + * \note is384 must be defined accordingly with the supported + * symbols in the config file. If: + * - is384 is 0, but \c MBEDTLS_SHA384_C is not defined, or + * - is384 is 1, but \c MBEDTLS_SHA512_C is not defined + * then the function will return + * #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_sha512(const unsigned char *input, + size_t ilen, + unsigned char *output, + int is384); + +#if defined(MBEDTLS_SELF_TEST) + +#if defined(MBEDTLS_SHA384_C) +/** + * \brief The SHA-384 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha384_self_test(int verbose); +#endif /* MBEDTLS_SHA384_C */ + +#if defined(MBEDTLS_SHA512_C) +/** + * \brief The SHA-512 checkup routine. + * + * \return \c 0 on success. + * \return \c 1 on failure. + */ +int mbedtls_sha512_self_test(int verbose); +#endif /* MBEDTLS_SHA512_C */ + +#endif /* MBEDTLS_SELF_TEST */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_sha512.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl.h index 3bb8b6c..be7f08e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl.h @@ -1,5380 +1,5380 @@ -/** - * \file ssl.h - * - * \brief SSL/TLS functions. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_H -#define MBEDTLS_SSL_H -#include "mbedtls/platform_util.h" -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/bignum.h" -#include "mbedtls/ecp.h" - -#include "mbedtls/ssl_ciphersuites.h" - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -#include "mbedtls/x509_crt.h" -#include "mbedtls/x509_crl.h" -#endif - -#if defined(MBEDTLS_DHM_C) -#include "mbedtls/dhm.h" -#endif - -#include "mbedtls/md.h" - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) -#include "mbedtls/ecdh.h" -#endif - -#if defined(MBEDTLS_HAVE_TIME) -#include "mbedtls/platform_time.h" -#endif - -#include "psa/crypto.h" - -/* - * SSL Error codes - */ -/** A cryptographic operation is in progress. Try again later. */ -#define MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS -0x7000 -/** The requested feature is not available. */ -#define MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE -0x7080 -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_SSL_BAD_INPUT_DATA -0x7100 -/** Verification of the message MAC failed. */ -#define MBEDTLS_ERR_SSL_INVALID_MAC -0x7180 -/** An invalid SSL record was received. */ -#define MBEDTLS_ERR_SSL_INVALID_RECORD -0x7200 -/** The connection indicated an EOF. */ -#define MBEDTLS_ERR_SSL_CONN_EOF -0x7280 -/** A message could not be parsed due to a syntactic error. */ -#define MBEDTLS_ERR_SSL_DECODE_ERROR -0x7300 -/* Error space gap */ -/** No RNG was provided to the SSL module. */ -#define MBEDTLS_ERR_SSL_NO_RNG -0x7400 -/** No client certification received from the client, but required by the authentication mode. */ -#define MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE -0x7480 -/** Client received an extended server hello containing an unsupported extension */ -#define MBEDTLS_ERR_SSL_UNSUPPORTED_EXTENSION -0x7500 -/** No ALPN protocols supported that the client advertises */ -#define MBEDTLS_ERR_SSL_NO_APPLICATION_PROTOCOL -0x7580 -/** The own private key or pre-shared key is not set, but needed. */ -#define MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED -0x7600 -/** No CA Chain is set, but required to operate. */ -#define MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED -0x7680 -/** An unexpected message was received from our peer. */ -#define MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE -0x7700 -/** A fatal alert message was received from our peer. */ -#define MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE -0x7780 -/** No server could be identified matching the client's SNI. */ -#define MBEDTLS_ERR_SSL_UNRECOGNIZED_NAME -0x7800 -/** The peer notified us that the connection is going to be closed. */ -#define MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY -0x7880 -/* Error space gap */ -/* Error space gap */ -/** Processing of the Certificate handshake message failed. */ -#define MBEDTLS_ERR_SSL_BAD_CERTIFICATE -0x7A00 -/* Error space gap */ -/** - * Received NewSessionTicket Post Handshake Message. - * This error code is experimental and may be changed or removed without notice. - */ -#define MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET -0x7B00 -/** Not possible to read early data */ -#define MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA -0x7B80 -/** Not possible to write early data */ -#define MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA -0x7C00 -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/** Cache entry not found */ -#define MBEDTLS_ERR_SSL_CACHE_ENTRY_NOT_FOUND -0x7E80 -/** Memory allocation failed */ -#define MBEDTLS_ERR_SSL_ALLOC_FAILED -0x7F00 -/** Hardware acceleration function returned with error */ -#define MBEDTLS_ERR_SSL_HW_ACCEL_FAILED -0x7F80 -/** Hardware acceleration function skipped / left alone data */ -#define MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH -0x6F80 -/** Handshake protocol not within min/max boundaries */ -#define MBEDTLS_ERR_SSL_BAD_PROTOCOL_VERSION -0x6E80 -/** The handshake negotiation failed. */ -#define MBEDTLS_ERR_SSL_HANDSHAKE_FAILURE -0x6E00 -/** Session ticket has expired. */ -#define MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED -0x6D80 -/** Public key type mismatch (eg, asked for RSA key exchange and presented EC key) */ -#define MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH -0x6D00 -/** Unknown identity received (eg, PSK identity) */ -#define MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY -0x6C80 -/** Internal error (eg, unexpected failure in lower-level module) */ -#define MBEDTLS_ERR_SSL_INTERNAL_ERROR -0x6C00 -/** A counter would wrap (eg, too many messages exchanged). */ -#define MBEDTLS_ERR_SSL_COUNTER_WRAPPING -0x6B80 -/** Unexpected message at ServerHello in renegotiation. */ -#define MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO -0x6B00 -/** DTLS client must retry for hello verification */ -#define MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED -0x6A80 -/** A buffer is too small to receive or write a message */ -#define MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL -0x6A00 -/* Error space gap */ -/** No data of requested type currently available on underlying transport. */ -#define MBEDTLS_ERR_SSL_WANT_READ -0x6900 -/** Connection requires a write call. */ -#define MBEDTLS_ERR_SSL_WANT_WRITE -0x6880 -/** The operation timed out. */ -#define MBEDTLS_ERR_SSL_TIMEOUT -0x6800 -/** The client initiated a reconnect from the same port. */ -#define MBEDTLS_ERR_SSL_CLIENT_RECONNECT -0x6780 -/** Record header looks valid but is not expected. */ -#define MBEDTLS_ERR_SSL_UNEXPECTED_RECORD -0x6700 -/** The alert message received indicates a non-fatal error. */ -#define MBEDTLS_ERR_SSL_NON_FATAL -0x6680 -/** A field in a message was incorrect or inconsistent with other fields. */ -#define MBEDTLS_ERR_SSL_ILLEGAL_PARAMETER -0x6600 -/** Internal-only message signaling that further message-processing should be done */ -#define MBEDTLS_ERR_SSL_CONTINUE_PROCESSING -0x6580 -/** The asynchronous operation is not completed yet. */ -#define MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS -0x6500 -/** Internal-only message signaling that a message arrived early. */ -#define MBEDTLS_ERR_SSL_EARLY_MESSAGE -0x6480 -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/* Error space gap */ -/** An encrypted DTLS-frame with an unexpected CID was received. */ -#define MBEDTLS_ERR_SSL_UNEXPECTED_CID -0x6000 -/** An operation failed due to an unexpected version or configuration. */ -#define MBEDTLS_ERR_SSL_VERSION_MISMATCH -0x5F00 -/** Invalid value in SSL config */ -#define MBEDTLS_ERR_SSL_BAD_CONFIG -0x5E80 - -/* - * Constants from RFC 8446 for TLS 1.3 PSK modes - * - * Those are used in the Pre-Shared Key Exchange Modes extension. - * See Section 4.2.9 in RFC 8446. - */ -#define MBEDTLS_SSL_TLS1_3_PSK_MODE_PURE 0 /* Pure PSK-based exchange */ -#define MBEDTLS_SSL_TLS1_3_PSK_MODE_ECDHE 1 /* PSK+ECDHE-based exchange */ - -/* - * TLS 1.3 NamedGroup values - * - * From RF 8446 - * enum { - * // Elliptic Curve Groups (ECDHE) - * secp256r1(0x0017), secp384r1(0x0018), secp521r1(0x0019), - * x25519(0x001D), x448(0x001E), - * // Finite Field Groups (DHE) - * ffdhe2048(0x0100), ffdhe3072(0x0101), ffdhe4096(0x0102), - * ffdhe6144(0x0103), ffdhe8192(0x0104), - * // Reserved Code Points - * ffdhe_private_use(0x01FC..0x01FF), - * ecdhe_private_use(0xFE00..0xFEFF), - * (0xFFFF) - * } NamedGroup; - * - */ - -/* Elliptic Curve Groups (ECDHE) */ -#define MBEDTLS_SSL_IANA_TLS_GROUP_NONE 0 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP192K1 0x0012 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP192R1 0x0013 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP224K1 0x0014 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP224R1 0x0015 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP256K1 0x0016 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 0x0017 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 0x0018 -#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1 0x0019 -#define MBEDTLS_SSL_IANA_TLS_GROUP_BP256R1 0x001A -#define MBEDTLS_SSL_IANA_TLS_GROUP_BP384R1 0x001B -#define MBEDTLS_SSL_IANA_TLS_GROUP_BP512R1 0x001C -#define MBEDTLS_SSL_IANA_TLS_GROUP_X25519 0x001D -#define MBEDTLS_SSL_IANA_TLS_GROUP_X448 0x001E -/* Finite Field Groups (DHE) */ -#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE2048 0x0100 -#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE3072 0x0101 -#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE4096 0x0102 -#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE6144 0x0103 -#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE8192 0x0104 - -/* - * TLS 1.3 Key Exchange Modes - * - * Mbed TLS internal identifiers for use with the SSL configuration API - * mbedtls_ssl_conf_tls13_key_exchange_modes(). - */ - -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK (1u << 0) /*!< Pure-PSK TLS 1.3 key exchange, - * encompassing both externally agreed PSKs - * as well as resumption PSKs. */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL (1u << 1) /*!< Pure-Ephemeral TLS 1.3 key exchanges, - * including for example ECDHE and DHE - * key exchanges. */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL (1u << 2) /*!< PSK-Ephemeral TLS 1.3 key exchanges, - * using both a PSK and an ephemeral - * key exchange. */ - -/* Convenience macros for sets of key exchanges. */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_ALL \ - (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK | \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL | \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL) /*!< All TLS 1.3 key exchanges */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL \ - (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK | \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL) /*!< All PSK-based TLS 1.3 key exchanges */ -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL \ - (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL | \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL) /*!< All ephemeral TLS 1.3 key exchanges */ - -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_NONE (0) - -/* - * Various constants - */ - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/* These are the high and low bytes of ProtocolVersion as defined by: - * - RFC 5246: ProtocolVersion version = { 3, 3 }; // TLS v1.2 - * - RFC 8446: see section 4.2.1 - */ -#define MBEDTLS_SSL_MAJOR_VERSION_3 3 -#define MBEDTLS_SSL_MINOR_VERSION_3 3 /*!< TLS v1.2 */ -#define MBEDTLS_SSL_MINOR_VERSION_4 4 /*!< TLS v1.3 */ -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -#define MBEDTLS_SSL_TRANSPORT_STREAM 0 /*!< TLS */ -#define MBEDTLS_SSL_TRANSPORT_DATAGRAM 1 /*!< DTLS */ - -#define MBEDTLS_SSL_MAX_HOST_NAME_LEN 255 /*!< Maximum host name defined in RFC 1035 */ -#define MBEDTLS_SSL_MAX_ALPN_NAME_LEN 255 /*!< Maximum size in bytes of a protocol name in alpn ext., RFC 7301 */ - -#define MBEDTLS_SSL_MAX_ALPN_LIST_LEN 65535 /*!< Maximum size in bytes of list in alpn ext., RFC 7301 */ - -/* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c - * NONE must be zero so that memset()ing structure to zero works */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_NONE 0 /*!< don't use this extension */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_512 1 /*!< MaxFragmentLength 2^9 */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_1024 2 /*!< MaxFragmentLength 2^10 */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_2048 3 /*!< MaxFragmentLength 2^11 */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_4096 4 /*!< MaxFragmentLength 2^12 */ -#define MBEDTLS_SSL_MAX_FRAG_LEN_INVALID 5 /*!< first invalid value */ - -#define MBEDTLS_SSL_IS_CLIENT 0 -#define MBEDTLS_SSL_IS_SERVER 1 - -#define MBEDTLS_SSL_EXTENDED_MS_DISABLED 0 -#define MBEDTLS_SSL_EXTENDED_MS_ENABLED 1 - -#define MBEDTLS_SSL_CID_DISABLED 0 -#define MBEDTLS_SSL_CID_ENABLED 1 - -#define MBEDTLS_SSL_ETM_DISABLED 0 -#define MBEDTLS_SSL_ETM_ENABLED 1 - -#define MBEDTLS_SSL_COMPRESS_NULL 0 - -#define MBEDTLS_SSL_VERIFY_NONE 0 -#define MBEDTLS_SSL_VERIFY_OPTIONAL 1 -#define MBEDTLS_SSL_VERIFY_REQUIRED 2 -#define MBEDTLS_SSL_VERIFY_UNSET 3 /* Used only for sni_authmode */ - -#define MBEDTLS_SSL_LEGACY_RENEGOTIATION 0 -#define MBEDTLS_SSL_SECURE_RENEGOTIATION 1 - -#define MBEDTLS_SSL_RENEGOTIATION_DISABLED 0 -#define MBEDTLS_SSL_RENEGOTIATION_ENABLED 1 - -#define MBEDTLS_SSL_ANTI_REPLAY_DISABLED 0 -#define MBEDTLS_SSL_ANTI_REPLAY_ENABLED 1 - -#define MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED -1 -#define MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT 16 - -#define MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION 0 -#define MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION 1 -#define MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE 2 - -#define MBEDTLS_SSL_TRUNC_HMAC_DISABLED 0 -#define MBEDTLS_SSL_TRUNC_HMAC_ENABLED 1 -#define MBEDTLS_SSL_TRUNCATED_HMAC_LEN 10 /* 80 bits, rfc 6066 section 7 */ - -#define MBEDTLS_SSL_SESSION_TICKETS_DISABLED 0 -#define MBEDTLS_SSL_SESSION_TICKETS_ENABLED 1 - -#define MBEDTLS_SSL_PRESET_DEFAULT 0 -#define MBEDTLS_SSL_PRESET_SUITEB 2 - -#define MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED 1 -#define MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED 0 - -#define MBEDTLS_SSL_EARLY_DATA_DISABLED 0 -#define MBEDTLS_SSL_EARLY_DATA_ENABLED 1 - -#define MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED 0 -#define MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED 1 - -#define MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_CLIENT 1 -#define MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER 0 - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -#if defined(PSA_WANT_ALG_SHA_384) -#define MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN 48 -#elif defined(PSA_WANT_ALG_SHA_256) -#define MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN 32 -#endif -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ -/* - * Default range for DTLS retransmission timer value, in milliseconds. - * RFC 6347 4.2.4.1 says from 1 second to 60 seconds. - */ -#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN 1000 -#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX 60000 - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -/* - * Maximum fragment length in bytes, - * determines the size of each of the two internal I/O buffers. - * - * Note: the RFC defines the default size of SSL / TLS messages. If you - * change the value here, other clients / servers may not be able to - * communicate with you anymore. Only change this value if you control - * both sides of the connection and have it reduced at both sides, or - * if you're using the Max Fragment Length extension and you know all your - * peers are using it too! - */ -#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) -#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 -#endif - -#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) -#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 -#endif - -/* - * Maximum number of heap-allocated bytes for the purpose of - * DTLS handshake message reassembly and future message buffering. - */ -#if !defined(MBEDTLS_SSL_DTLS_MAX_BUFFERING) -#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 -#endif - -/* - * Maximum length of CIDs for incoming and outgoing messages. - */ -#if !defined(MBEDTLS_SSL_CID_IN_LEN_MAX) -#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 -#endif - -#if !defined(MBEDTLS_SSL_CID_OUT_LEN_MAX) -#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 -#endif - -#if !defined(MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY) -#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 -#endif - -#if !defined(MBEDTLS_SSL_MAX_EARLY_DATA_SIZE) -#define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 -#endif - -#if !defined(MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE) -#define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 -#endif - -#if !defined(MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH) -#define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 -#endif - -#if !defined(MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS) -#define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 -#endif - -/** \} name SECTION: Module settings */ - -/* - * Default to standard CID mode - */ -#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) -#define MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT 0 -#endif - -/* - * Length of the verify data for secure renegotiation - */ -#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 12 - -/* - * Signaling ciphersuite values (SCSV) - */ -#define MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO 0xFF /**< renegotiation info ext */ - -/* - * Supported Signature and Hash algorithms (For TLS 1.2) - * RFC 5246 section 7.4.1.4.1 - */ -#define MBEDTLS_SSL_HASH_NONE 0 -#define MBEDTLS_SSL_HASH_MD5 1 -#define MBEDTLS_SSL_HASH_SHA1 2 -#define MBEDTLS_SSL_HASH_SHA224 3 -#define MBEDTLS_SSL_HASH_SHA256 4 -#define MBEDTLS_SSL_HASH_SHA384 5 -#define MBEDTLS_SSL_HASH_SHA512 6 - -#define MBEDTLS_SSL_SIG_ANON 0 -#define MBEDTLS_SSL_SIG_RSA 1 -#define MBEDTLS_SSL_SIG_ECDSA 3 - -/* - * TLS 1.3 signature algorithms - * RFC 8446, Section 4.2.2 - */ - -/* RSASSA-PKCS1-v1_5 algorithms */ -#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA256 0x0401 -#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA384 0x0501 -#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA512 0x0601 - -/* ECDSA algorithms */ -#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP256R1_SHA256 0x0403 -#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP384R1_SHA384 0x0503 -#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP521R1_SHA512 0x0603 - -/* RSASSA-PSS algorithms with public key OID rsaEncryption */ -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256 0x0804 -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384 0x0805 -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512 0x0806 - -/* EdDSA algorithms */ -#define MBEDTLS_TLS1_3_SIG_ED25519 0x0807 -#define MBEDTLS_TLS1_3_SIG_ED448 0x0808 - -/* RSASSA-PSS algorithms with public key OID RSASSA-PSS */ -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA256 0x0809 -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA384 0x080A -#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA512 0x080B - -/* LEGACY ALGORITHMS */ -#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA1 0x0201 -#define MBEDTLS_TLS1_3_SIG_ECDSA_SHA1 0x0203 - -#define MBEDTLS_TLS1_3_SIG_NONE 0x0 - -/* - * Client Certificate Types - * RFC 5246 section 7.4.4 plus RFC 4492 section 5.5 - */ -#define MBEDTLS_SSL_CERT_TYPE_RSA_SIGN 1 -#define MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN 64 - -/* - * Message, alert and handshake types - */ -#define MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC 20 -#define MBEDTLS_SSL_MSG_ALERT 21 -#define MBEDTLS_SSL_MSG_HANDSHAKE 22 -#define MBEDTLS_SSL_MSG_APPLICATION_DATA 23 -#define MBEDTLS_SSL_MSG_CID 25 - -#define MBEDTLS_SSL_ALERT_LEVEL_WARNING 1 -#define MBEDTLS_SSL_ALERT_LEVEL_FATAL 2 - -#define MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY 0 /* 0x00 */ -#define MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE 10 /* 0x0A */ -#define MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC 20 /* 0x14 */ -#define MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED 21 /* 0x15 */ -#define MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW 22 /* 0x16 */ -#define MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE 30 /* 0x1E */ -#define MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE 40 /* 0x28 */ -#define MBEDTLS_SSL_ALERT_MSG_NO_CERT 41 /* 0x29 */ -#define MBEDTLS_SSL_ALERT_MSG_BAD_CERT 42 /* 0x2A */ -#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT 43 /* 0x2B */ -#define MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED 44 /* 0x2C */ -#define MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED 45 /* 0x2D */ -#define MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN 46 /* 0x2E */ -#define MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER 47 /* 0x2F */ -#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA 48 /* 0x30 */ -#define MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED 49 /* 0x31 */ -#define MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR 50 /* 0x32 */ -#define MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR 51 /* 0x33 */ -#define MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION 60 /* 0x3C */ -#define MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION 70 /* 0x46 */ -#define MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY 71 /* 0x47 */ -#define MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR 80 /* 0x50 */ -#define MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK 86 /* 0x56 */ -#define MBEDTLS_SSL_ALERT_MSG_USER_CANCELED 90 /* 0x5A */ -#define MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION 100 /* 0x64 */ -#define MBEDTLS_SSL_ALERT_MSG_MISSING_EXTENSION 109 /* 0x6d -- new in TLS 1.3 */ -#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT 110 /* 0x6E */ -#define MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME 112 /* 0x70 */ -#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY 115 /* 0x73 */ -#define MBEDTLS_SSL_ALERT_MSG_CERT_REQUIRED 116 /* 0x74 */ -#define MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL 120 /* 0x78 */ - -#define MBEDTLS_SSL_HS_HELLO_REQUEST 0 -#define MBEDTLS_SSL_HS_CLIENT_HELLO 1 -#define MBEDTLS_SSL_HS_SERVER_HELLO 2 -#define MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST 3 -#define MBEDTLS_SSL_HS_NEW_SESSION_TICKET 4 -#define MBEDTLS_SSL_HS_END_OF_EARLY_DATA 5 -#define MBEDTLS_SSL_HS_ENCRYPTED_EXTENSIONS 8 -#define MBEDTLS_SSL_HS_CERTIFICATE 11 -#define MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE 12 -#define MBEDTLS_SSL_HS_CERTIFICATE_REQUEST 13 -#define MBEDTLS_SSL_HS_SERVER_HELLO_DONE 14 -#define MBEDTLS_SSL_HS_CERTIFICATE_VERIFY 15 -#define MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE 16 -#define MBEDTLS_SSL_HS_FINISHED 20 -#define MBEDTLS_SSL_HS_MESSAGE_HASH 254 - -/* - * TLS extensions - */ -#define MBEDTLS_TLS_EXT_SERVERNAME 0 -#define MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME 0 - -#define MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH 1 - -#define MBEDTLS_TLS_EXT_TRUNCATED_HMAC 4 -#define MBEDTLS_TLS_EXT_STATUS_REQUEST 5 /* RFC 6066 TLS 1.2 and 1.3 */ - -#define MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES 10 -#define MBEDTLS_TLS_EXT_SUPPORTED_GROUPS 10 /* RFC 8422,7919 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS 11 - -#define MBEDTLS_TLS_EXT_SIG_ALG 13 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_USE_SRTP 14 -#define MBEDTLS_TLS_EXT_HEARTBEAT 15 /* RFC 6520 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_ALPN 16 - -#define MBEDTLS_TLS_EXT_SCT 18 /* RFC 6962 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_CLI_CERT_TYPE 19 /* RFC 7250 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_SERV_CERT_TYPE 20 /* RFC 7250 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_PADDING 21 /* RFC 7685 TLS 1.2 and 1.3 */ -#define MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC 22 /* 0x16 */ -#define MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET 0x0017 /* 23 */ - -#define MBEDTLS_TLS_EXT_RECORD_SIZE_LIMIT 28 /* RFC 8449 (implemented for TLS 1.3 only) */ - -#define MBEDTLS_TLS_EXT_SESSION_TICKET 35 - -#define MBEDTLS_TLS_EXT_PRE_SHARED_KEY 41 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_EARLY_DATA 42 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_SUPPORTED_VERSIONS 43 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_COOKIE 44 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_PSK_KEY_EXCHANGE_MODES 45 /* RFC 8446 TLS 1.3 */ - -#define MBEDTLS_TLS_EXT_CERT_AUTH 47 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_OID_FILTERS 48 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_POST_HANDSHAKE_AUTH 49 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_SIG_ALG_CERT 50 /* RFC 8446 TLS 1.3 */ -#define MBEDTLS_TLS_EXT_KEY_SHARE 51 /* RFC 8446 TLS 1.3 */ - -#if MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT == 0 -#define MBEDTLS_TLS_EXT_CID 54 /* RFC 9146 DTLS 1.2 CID */ -#else -#define MBEDTLS_TLS_EXT_CID 254 /* Pre-RFC 9146 DTLS 1.2 CID */ -#endif - -#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP 256 /* experimental */ - -#define MBEDTLS_TLS_EXT_RENEGOTIATION_INFO 0xFF01 - -/* - * Size defines - */ -#if !defined(MBEDTLS_PSK_MAX_LEN) -/* - * If the library supports TLS 1.3 tickets and the cipher suite - * TLS1-3-AES-256-GCM-SHA384, set the PSK maximum length to 48 instead of 32. - * That way, the TLS 1.3 client and server are able to resume sessions where - * the cipher suite is TLS1-3-AES-256-GCM-SHA384 (pre-shared keys are 48 - * bytes long in that case). - */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ - defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_AES_C) && defined(MBEDTLS_GCM_C) && \ - defined(MBEDTLS_MD_CAN_SHA384) -#define MBEDTLS_PSK_MAX_LEN 48 /* 384 bits */ -#else -#define MBEDTLS_PSK_MAX_LEN 32 /* 256 bits */ -#endif -#endif /* !MBEDTLS_PSK_MAX_LEN */ - -/* Dummy type used only for its size */ -union mbedtls_ssl_premaster_secret { - unsigned char dummy; /* Make the union non-empty even with SSL disabled */ -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) - unsigned char _pms_rsa[48]; /* RFC 5246 8.1.1 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) - unsigned char _pms_dhm[MBEDTLS_MPI_MAX_SIZE]; /* RFC 5246 8.1.2 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) - unsigned char _pms_ecdh[MBEDTLS_ECP_MAX_BYTES]; /* RFC 4492 5.10 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) - unsigned char _pms_psk[4 + 2 * MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 2 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) - unsigned char _pms_dhe_psk[4 + MBEDTLS_MPI_MAX_SIZE - + MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 3 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) - unsigned char _pms_rsa_psk[52 + MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 4 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) - unsigned char _pms_ecdhe_psk[4 + MBEDTLS_ECP_MAX_BYTES - + MBEDTLS_PSK_MAX_LEN]; /* RFC 5489 2 */ -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) - unsigned char _pms_ecjpake[32]; /* Thread spec: SHA-256 output */ -#endif -}; - -#define MBEDTLS_PREMASTER_SIZE sizeof(union mbedtls_ssl_premaster_secret) - -#define MBEDTLS_TLS1_3_MD_MAX_SIZE PSA_HASH_MAX_SIZE - - -/* Length in number of bytes of the TLS sequence number */ -#define MBEDTLS_SSL_SEQUENCE_NUMBER_LEN 8 - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * SSL state machine - */ -typedef enum { - MBEDTLS_SSL_HELLO_REQUEST, - MBEDTLS_SSL_CLIENT_HELLO, - MBEDTLS_SSL_SERVER_HELLO, - MBEDTLS_SSL_SERVER_CERTIFICATE, - MBEDTLS_SSL_SERVER_KEY_EXCHANGE, - MBEDTLS_SSL_CERTIFICATE_REQUEST, - MBEDTLS_SSL_SERVER_HELLO_DONE, - MBEDTLS_SSL_CLIENT_CERTIFICATE, - MBEDTLS_SSL_CLIENT_KEY_EXCHANGE, - MBEDTLS_SSL_CERTIFICATE_VERIFY, - MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC, - MBEDTLS_SSL_CLIENT_FINISHED, - MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC, - MBEDTLS_SSL_SERVER_FINISHED, - MBEDTLS_SSL_FLUSH_BUFFERS, - MBEDTLS_SSL_HANDSHAKE_WRAPUP, - - MBEDTLS_SSL_NEW_SESSION_TICKET, - MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT, - MBEDTLS_SSL_HELLO_RETRY_REQUEST, - MBEDTLS_SSL_ENCRYPTED_EXTENSIONS, - MBEDTLS_SSL_END_OF_EARLY_DATA, - MBEDTLS_SSL_CLIENT_CERTIFICATE_VERIFY, - MBEDTLS_SSL_CLIENT_CCS_AFTER_SERVER_FINISHED, - MBEDTLS_SSL_CLIENT_CCS_BEFORE_2ND_CLIENT_HELLO, - MBEDTLS_SSL_SERVER_CCS_AFTER_SERVER_HELLO, - MBEDTLS_SSL_CLIENT_CCS_AFTER_CLIENT_HELLO, - MBEDTLS_SSL_SERVER_CCS_AFTER_HELLO_RETRY_REQUEST, - MBEDTLS_SSL_HANDSHAKE_OVER, - MBEDTLS_SSL_TLS1_3_NEW_SESSION_TICKET, - MBEDTLS_SSL_TLS1_3_NEW_SESSION_TICKET_FLUSH, -} -mbedtls_ssl_states; - -/** - * \brief Callback type: send data on the network. - * - * \note That callback may be either blocking or non-blocking. - * - * \param ctx Context for the send callback (typically a file descriptor) - * \param buf Buffer holding the data to send - * \param len Length of the data to send - * - * \return The callback must return the number of bytes sent if any, - * or a non-zero error code. - * If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_WRITE - * must be returned when the operation would block. - * - * \note The callback is allowed to send fewer bytes than requested. - * It must always return the number of bytes actually sent. - */ -typedef int mbedtls_ssl_send_t(void *ctx, - const unsigned char *buf, - size_t len); - -/** - * \brief Callback type: receive data from the network. - * - * \note That callback may be either blocking or non-blocking. - * - * \param ctx Context for the receive callback (typically a file - * descriptor) - * \param buf Buffer to write the received data to - * \param len Length of the receive buffer - * - * \returns If data has been received, the positive number of bytes received. - * \returns \c 0 if the connection has been closed. - * \returns If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_READ - * must be returned when the operation would block. - * \returns Another negative error code on other kinds of failures. - * - * \note The callback may receive fewer bytes than the length of the - * buffer. It must always return the number of bytes actually - * received and written to the buffer. - */ -typedef int mbedtls_ssl_recv_t(void *ctx, - unsigned char *buf, - size_t len); - -/** - * \brief Callback type: receive data from the network, with timeout - * - * \note That callback must block until data is received, or the - * timeout delay expires, or the operation is interrupted by a - * signal. - * - * \param ctx Context for the receive callback (typically a file descriptor) - * \param buf Buffer to write the received data to - * \param len Length of the receive buffer - * \param timeout Maximum number of milliseconds to wait for data - * 0 means no timeout (potentially waiting forever) - * - * \return The callback must return the number of bytes received, - * or a non-zero error code: - * \c MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out, - * \c MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal. - * - * \note The callback may receive fewer bytes than the length of the - * buffer. It must always return the number of bytes actually - * received and written to the buffer. - */ -typedef int mbedtls_ssl_recv_timeout_t(void *ctx, - unsigned char *buf, - size_t len, - uint32_t timeout); -/** - * \brief Callback type: set a pair of timers/delays to watch - * - * \param ctx Context pointer - * \param int_ms Intermediate delay in milliseconds - * \param fin_ms Final delay in milliseconds - * 0 cancels the current timer. - * - * \note This callback must at least store the necessary information - * for the associated \c mbedtls_ssl_get_timer_t callback to - * return correct information. - * - * \note If using an event-driven style of programming, an event must - * be generated when the final delay is passed. The event must - * cause a call to \c mbedtls_ssl_handshake() with the proper - * SSL context to be scheduled. Care must be taken to ensure - * that at most one such call happens at a time. - * - * \note Only one timer at a time must be running. Calling this - * function while a timer is running must cancel it. Cancelled - * timers must not generate any event. - */ -typedef void mbedtls_ssl_set_timer_t(void *ctx, - uint32_t int_ms, - uint32_t fin_ms); - -/** - * \brief Callback type: get status of timers/delays - * - * \param ctx Context pointer - * - * \return This callback must return: - * -1 if cancelled (fin_ms == 0), - * 0 if none of the delays have passed, - * 1 if only the intermediate delay has passed, - * 2 if the final delay has passed. - */ -typedef int mbedtls_ssl_get_timer_t(void *ctx); - -/* Defined below */ -typedef struct mbedtls_ssl_session mbedtls_ssl_session; -typedef struct mbedtls_ssl_context mbedtls_ssl_context; -typedef struct mbedtls_ssl_config mbedtls_ssl_config; - -/* Defined in library/ssl_misc.h */ -typedef struct mbedtls_ssl_transform mbedtls_ssl_transform; -typedef struct mbedtls_ssl_handshake_params mbedtls_ssl_handshake_params; -typedef struct mbedtls_ssl_sig_hash_set_t mbedtls_ssl_sig_hash_set_t; -#if defined(MBEDTLS_X509_CRT_PARSE_C) -typedef struct mbedtls_ssl_key_cert mbedtls_ssl_key_cert; -#endif -#if defined(MBEDTLS_SSL_PROTO_DTLS) -typedef struct mbedtls_ssl_flight_item mbedtls_ssl_flight_item; -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_RESUMPTION \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK /* 1U << 0 */ -#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_EPHEMERAL_RESUMPTION \ - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL /* 1U << 2 */ -#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_EARLY_DATA (1U << 3) - -#define MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK \ - (MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_RESUMPTION | \ - MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_EPHEMERAL_RESUMPTION | \ - MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_EARLY_DATA) -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ - -/** - * \brief Callback type: server-side session cache getter - * - * The session cache is logically a key value store, with - * keys being session IDs and values being instances of - * mbedtls_ssl_session. - * - * This callback retrieves an entry in this key-value store. - * - * \param data The address of the session cache structure to query. - * \param session_id The buffer holding the session ID to query. - * \param session_id_len The length of \p session_id in Bytes. - * \param session The address of the session structure to populate. - * It is initialized with mbdtls_ssl_session_init(), - * and the callback must always leave it in a state - * where it can safely be freed via - * mbedtls_ssl_session_free() independent of the - * return code of this function. - * - * \return \c 0 on success - * \return A non-zero return value on failure. - * - */ -typedef int mbedtls_ssl_cache_get_t(void *data, - unsigned char const *session_id, - size_t session_id_len, - mbedtls_ssl_session *session); -/** - * \brief Callback type: server-side session cache setter - * - * The session cache is logically a key value store, with - * keys being session IDs and values being instances of - * mbedtls_ssl_session. - * - * This callback sets an entry in this key-value store. - * - * \param data The address of the session cache structure to modify. - * \param session_id The buffer holding the session ID to query. - * \param session_id_len The length of \p session_id in Bytes. - * \param session The address of the session to be stored in the - * session cache. - * - * \return \c 0 on success - * \return A non-zero return value on failure. - */ -typedef int mbedtls_ssl_cache_set_t(void *data, - unsigned char const *session_id, - size_t session_id_len, - const mbedtls_ssl_session *session); - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Callback type: start external signature operation. - * - * This callback is called during an SSL handshake to start - * a signature decryption operation using an - * external processor. The parameter \p cert contains - * the public key; it is up to the callback function to - * determine how to access the associated private key. - * - * This function typically sends or enqueues a request, and - * does not wait for the operation to complete. This allows - * the handshake step to be non-blocking. - * - * The parameters \p ssl and \p cert are guaranteed to remain - * valid throughout the handshake. On the other hand, this - * function must save the contents of \p hash if the value - * is needed for later processing, because the \p hash buffer - * is no longer valid after this function returns. - * - * This function may call mbedtls_ssl_set_async_operation_data() - * to store an operation context for later retrieval - * by the resume or cancel callback. - * - * \note For RSA signatures, this function must produce output - * that is consistent with PKCS#1 v1.5 in the same way as - * mbedtls_rsa_pkcs1_sign(). Before the private key operation, - * apply the padding steps described in RFC 8017, section 9.2 - * "EMSA-PKCS1-v1_5" as follows. - * - If \p md_alg is #MBEDTLS_MD_NONE, apply the PKCS#1 v1.5 - * encoding, treating \p hash as the DigestInfo to be - * padded. In other words, apply EMSA-PKCS1-v1_5 starting - * from step 3, with `T = hash` and `tLen = hash_len`. - * - If `md_alg != MBEDTLS_MD_NONE`, apply the PKCS#1 v1.5 - * encoding, treating \p hash as the hash to be encoded and - * padded. In other words, apply EMSA-PKCS1-v1_5 starting - * from step 2, with `digestAlgorithm` obtained by calling - * mbedtls_oid_get_oid_by_md() on \p md_alg. - * - * \note For ECDSA signatures, the output format is the DER encoding - * `Ecdsa-Sig-Value` defined in - * [RFC 4492 section 5.4](https://tools.ietf.org/html/rfc4492#section-5.4). - * - * \param ssl The SSL connection instance. It should not be - * modified other than via - * mbedtls_ssl_set_async_operation_data(). - * \param cert Certificate containing the public key. - * In simple cases, this is one of the pointers passed to - * mbedtls_ssl_conf_own_cert() when configuring the SSL - * connection. However, if other callbacks are used, this - * property may not hold. For example, if an SNI callback - * is registered with mbedtls_ssl_conf_sni(), then - * this callback determines what certificate is used. - * \param md_alg Hash algorithm. - * \param hash Buffer containing the hash. This buffer is - * no longer valid when the function returns. - * \param hash_len Size of the \c hash buffer in bytes. - * - * \return 0 if the operation was started successfully and the SSL - * stack should call the resume callback immediately. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation - * was started successfully and the SSL stack should return - * immediately without calling the resume callback yet. - * \return #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external - * processor does not support this key. The SSL stack will - * use the private key object instead. - * \return Any other error indicates a fatal failure and is - * propagated up the call chain. The callback should - * use \c MBEDTLS_ERR_PK_xxx error codes, and must not - * use \c MBEDTLS_ERR_SSL_xxx error codes except as - * directed in the documentation of this callback. - */ -typedef int mbedtls_ssl_async_sign_t(mbedtls_ssl_context *ssl, - mbedtls_x509_crt *cert, - mbedtls_md_type_t md_alg, - const unsigned char *hash, - size_t hash_len); - -/** - * \brief Callback type: start external decryption operation. - * - * This callback is called during an SSL handshake to start - * an RSA decryption operation using an - * external processor. The parameter \p cert contains - * the public key; it is up to the callback function to - * determine how to access the associated private key. - * - * This function typically sends or enqueues a request, and - * does not wait for the operation to complete. This allows - * the handshake step to be non-blocking. - * - * The parameters \p ssl and \p cert are guaranteed to remain - * valid throughout the handshake. On the other hand, this - * function must save the contents of \p input if the value - * is needed for later processing, because the \p input buffer - * is no longer valid after this function returns. - * - * This function may call mbedtls_ssl_set_async_operation_data() - * to store an operation context for later retrieval - * by the resume or cancel callback. - * - * \warning RSA decryption as used in TLS is subject to a potential - * timing side channel attack first discovered by Bleichenbacher - * in 1998. This attack can be remotely exploitable - * in practice. To avoid this attack, you must ensure that - * if the callback performs an RSA decryption, the time it - * takes to execute and return the result does not depend - * on whether the RSA decryption succeeded or reported - * invalid padding. - * - * \param ssl The SSL connection instance. It should not be - * modified other than via - * mbedtls_ssl_set_async_operation_data(). - * \param cert Certificate containing the public key. - * In simple cases, this is one of the pointers passed to - * mbedtls_ssl_conf_own_cert() when configuring the SSL - * connection. However, if other callbacks are used, this - * property may not hold. For example, if an SNI callback - * is registered with mbedtls_ssl_conf_sni(), then - * this callback determines what certificate is used. - * \param input Buffer containing the input ciphertext. This buffer - * is no longer valid when the function returns. - * \param input_len Size of the \p input buffer in bytes. - * - * \return 0 if the operation was started successfully and the SSL - * stack should call the resume callback immediately. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation - * was started successfully and the SSL stack should return - * immediately without calling the resume callback yet. - * \return #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external - * processor does not support this key. The SSL stack will - * use the private key object instead. - * \return Any other error indicates a fatal failure and is - * propagated up the call chain. The callback should - * use \c MBEDTLS_ERR_PK_xxx error codes, and must not - * use \c MBEDTLS_ERR_SSL_xxx error codes except as - * directed in the documentation of this callback. - */ -typedef int mbedtls_ssl_async_decrypt_t(mbedtls_ssl_context *ssl, - mbedtls_x509_crt *cert, - const unsigned char *input, - size_t input_len); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -/** - * \brief Callback type: resume external operation. - * - * This callback is called during an SSL handshake to resume - * an external operation started by the - * ::mbedtls_ssl_async_sign_t or - * ::mbedtls_ssl_async_decrypt_t callback. - * - * This function typically checks the status of a pending - * request or causes the request queue to make progress, and - * does not wait for the operation to complete. This allows - * the handshake step to be non-blocking. - * - * This function may call mbedtls_ssl_get_async_operation_data() - * to retrieve an operation context set by the start callback. - * It may call mbedtls_ssl_set_async_operation_data() to modify - * this context. - * - * Note that when this function returns a status other than - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, it must free any - * resources associated with the operation. - * - * \param ssl The SSL connection instance. It should not be - * modified other than via - * mbedtls_ssl_set_async_operation_data(). - * \param output Buffer containing the output (signature or decrypted - * data) on success. - * \param output_len On success, number of bytes written to \p output. - * \param output_size Size of the \p output buffer in bytes. - * - * \return 0 if output of the operation is available in the - * \p output buffer. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation - * is still in progress. Subsequent requests for progress - * on the SSL connection will call the resume callback - * again. - * \return Any other error means that the operation is aborted. - * The SSL handshake is aborted. The callback should - * use \c MBEDTLS_ERR_PK_xxx error codes, and must not - * use \c MBEDTLS_ERR_SSL_xxx error codes except as - * directed in the documentation of this callback. - */ -typedef int mbedtls_ssl_async_resume_t(mbedtls_ssl_context *ssl, - unsigned char *output, - size_t *output_len, - size_t output_size); - -/** - * \brief Callback type: cancel external operation. - * - * This callback is called if an SSL connection is closed - * while an asynchronous operation is in progress. Note that - * this callback is not called if the - * ::mbedtls_ssl_async_resume_t callback has run and has - * returned a value other than - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, since in that case - * the asynchronous operation has already completed. - * - * This function may call mbedtls_ssl_get_async_operation_data() - * to retrieve an operation context set by the start callback. - * - * \param ssl The SSL connection instance. It should not be - * modified. - */ -typedef void mbedtls_ssl_async_cancel_t(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ - -#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) && \ - !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) -#define MBEDTLS_SSL_PEER_CERT_DIGEST_MAX_LEN 48 -#if defined(MBEDTLS_MD_CAN_SHA256) -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA256 -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 32 -#elif defined(MBEDTLS_MD_CAN_SHA384) -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA384 -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 48 -#elif defined(MBEDTLS_MD_CAN_SHA1) -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA1 -#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 20 -#else -/* This is already checked in check_config.h, but be sure. */ -#error "Bad configuration - need SHA-1, SHA-256 or SHA-512 enabled to compute digest of peer CRT." -#endif -#endif /* MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED && - !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ - -typedef struct { - unsigned char client_application_traffic_secret_N[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char server_application_traffic_secret_N[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char exporter_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char resumption_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; -} mbedtls_ssl_tls13_application_secrets; - -#if defined(MBEDTLS_SSL_DTLS_SRTP) - -#define MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH 255 -#define MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH 4 -/* - * For code readability use a typedef for DTLS-SRTP profiles - * - * Use_srtp extension protection profiles values as defined in - * http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml - * - * Reminder: if this list is expanded mbedtls_ssl_check_srtp_profile_value - * must be updated too. - */ -#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80 ((uint16_t) 0x0001) -#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32 ((uint16_t) 0x0002) -#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80 ((uint16_t) 0x0005) -#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32 ((uint16_t) 0x0006) -/* This one is not iana defined, but for code readability. */ -#define MBEDTLS_TLS_SRTP_UNSET ((uint16_t) 0x0000) - -typedef uint16_t mbedtls_ssl_srtp_profile; - -typedef struct mbedtls_dtls_srtp_info_t { - /*! The SRTP profile that was negotiated. */ - mbedtls_ssl_srtp_profile MBEDTLS_PRIVATE(chosen_dtls_srtp_profile); - /*! The length of mki_value. */ - uint16_t MBEDTLS_PRIVATE(mki_len); - /*! The mki_value used, with max size of 256 bytes. */ - unsigned char MBEDTLS_PRIVATE(mki_value)[MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH]; -} -mbedtls_dtls_srtp_info; - -#endif /* MBEDTLS_SSL_DTLS_SRTP */ - -/** Human-friendly representation of the (D)TLS protocol version. */ -typedef enum { - MBEDTLS_SSL_VERSION_UNKNOWN, /*!< Context not in use or version not yet negotiated. */ - MBEDTLS_SSL_VERSION_TLS1_2 = 0x0303, /*!< (D)TLS 1.2 */ - MBEDTLS_SSL_VERSION_TLS1_3 = 0x0304, /*!< (D)TLS 1.3 */ -} mbedtls_ssl_protocol_version; - -/* - * This structure is used for storing current session data. - * - * Note: when changing this definition, we need to check and update: - * - in tests/suites/test_suite_ssl.function: - * ssl_populate_session() and ssl_serialize_session_save_load() - * - in library/ssl_tls.c: - * mbedtls_ssl_session_init() and mbedtls_ssl_session_free() - * mbedtls_ssl_session_save() and ssl_session_load() - * ssl_session_copy() - */ -struct mbedtls_ssl_session { -#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) - unsigned char MBEDTLS_PRIVATE(mfl_code); /*!< MaxFragmentLength negotiated by peer */ -#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ - - unsigned char MBEDTLS_PRIVATE(exported); - - /** TLS version negotiated in the session. Used if and when renegotiating - * or resuming a session instead of the configured minor TLS version. - */ - mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(tls_version); - -#if defined(MBEDTLS_HAVE_TIME) - mbedtls_time_t MBEDTLS_PRIVATE(start); /*!< starting time */ -#endif - int MBEDTLS_PRIVATE(ciphersuite); /*!< chosen ciphersuite */ - size_t MBEDTLS_PRIVATE(id_len); /*!< session id length */ - unsigned char MBEDTLS_PRIVATE(id)[32]; /*!< session identifier */ - unsigned char MBEDTLS_PRIVATE(master)[48]; /*!< the master secret */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -#if defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) - mbedtls_x509_crt *MBEDTLS_PRIVATE(peer_cert); /*!< peer X.509 cert chain */ -#else /* MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ - /*! The digest of the peer's end-CRT. This must be kept to detect CRT - * changes during renegotiation, mitigating the triple handshake attack. */ - unsigned char *MBEDTLS_PRIVATE(peer_cert_digest); - size_t MBEDTLS_PRIVATE(peer_cert_digest_len); - mbedtls_md_type_t MBEDTLS_PRIVATE(peer_cert_digest_type); -#endif /* !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - uint32_t MBEDTLS_PRIVATE(verify_result); /*!< verification result */ - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C) - unsigned char *MBEDTLS_PRIVATE(ticket); /*!< RFC 5077 session ticket */ - size_t MBEDTLS_PRIVATE(ticket_len); /*!< session ticket length */ - uint32_t MBEDTLS_PRIVATE(ticket_lifetime); /*!< ticket lifetime hint */ -#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) - uint8_t MBEDTLS_PRIVATE(endpoint); /*!< 0: client, 1: server */ - uint8_t MBEDTLS_PRIVATE(ticket_flags); /*!< Ticket flags */ - uint32_t MBEDTLS_PRIVATE(ticket_age_add); /*!< Randomly generated value used to obscure the age of the ticket */ - uint8_t MBEDTLS_PRIVATE(resumption_key_len); /*!< resumption_key length */ - unsigned char MBEDTLS_PRIVATE(resumption_key)[MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN]; - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && defined(MBEDTLS_SSL_CLI_C) - char *MBEDTLS_PRIVATE(hostname); /*!< host name binded with tickets */ -#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION && MBEDTLS_SSL_CLI_C */ - -#if defined(MBEDTLS_HAVE_TIME) && defined(MBEDTLS_SSL_CLI_C) - mbedtls_time_t MBEDTLS_PRIVATE(ticket_received); /*!< time ticket was received */ -#endif /* MBEDTLS_HAVE_TIME && MBEDTLS_SSL_CLI_C */ - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ - -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - int MBEDTLS_PRIVATE(encrypt_then_mac); /*!< flag for EtM activation */ -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - mbedtls_ssl_tls13_application_secrets MBEDTLS_PRIVATE(app_secrets); -#endif -}; - -/* - * Identifiers for PRFs used in various versions of TLS. - */ -typedef enum { - MBEDTLS_SSL_TLS_PRF_NONE, - MBEDTLS_SSL_TLS_PRF_SHA384, - MBEDTLS_SSL_TLS_PRF_SHA256, - MBEDTLS_SSL_HKDF_EXPAND_SHA384, - MBEDTLS_SSL_HKDF_EXPAND_SHA256 -} -mbedtls_tls_prf_types; - -typedef enum { - MBEDTLS_SSL_KEY_EXPORT_TLS12_MASTER_SECRET = 0, -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_EARLY_SECRET, - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_EARLY_EXPORTER_SECRET, - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_HANDSHAKE_TRAFFIC_SECRET, - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_SERVER_HANDSHAKE_TRAFFIC_SECRET, - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_APPLICATION_TRAFFIC_SECRET, - MBEDTLS_SSL_KEY_EXPORT_TLS1_3_SERVER_APPLICATION_TRAFFIC_SECRET, -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ -} mbedtls_ssl_key_export_type; - -/** - * \brief Callback type: Export key alongside random values for - * session identification, and PRF for - * implementation of TLS key exporters. - * - * \param p_expkey Context for the callback. - * \param type The type of the key that is being exported. - * \param secret The address of the buffer holding the secret - * that's being exporterd. - * \param secret_len The length of \p secret in bytes. - * \param client_random The client random bytes. - * \param server_random The server random bytes. - * \param tls_prf_type The identifier for the PRF used in the handshake - * to which the key belongs. - */ -typedef void mbedtls_ssl_export_keys_t(void *p_expkey, - mbedtls_ssl_key_export_type type, - const unsigned char *secret, - size_t secret_len, - const unsigned char client_random[32], - const unsigned char server_random[32], - mbedtls_tls_prf_types tls_prf_type); - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Callback type: generic handshake callback - * - * \note Callbacks may use user_data funcs to set/get app user data. - * See \c mbedtls_ssl_get_user_data_p() - * \c mbedtls_ssl_get_user_data_n() - * \c mbedtls_ssl_conf_get_user_data_p() - * \c mbedtls_ssl_conf_get_user_data_n() - * - * \param ssl \c mbedtls_ssl_context on which the callback is run - * - * \return The return value of the callback is 0 if successful, - * or a specific MBEDTLS_ERR_XXX code, which will cause - * the handshake to be aborted. - */ -typedef int (*mbedtls_ssl_hs_cb_t)(mbedtls_ssl_context *ssl); -#endif - -/* A type for storing user data in a library structure. - * - * The representation of type may change in future versions of the library. - * Only the behaviors guaranteed by documented accessor functions are - * guaranteed to remain stable. - */ -typedef union { - uintptr_t n; /* typically a handle to an associated object */ - void *p; /* typically a pointer to extra data */ -} mbedtls_ssl_user_data_t; - -/** - * SSL/TLS configuration to be shared between mbedtls_ssl_context structures. - */ -struct mbedtls_ssl_config { - /* Group items mostly by size. This helps to reduce memory wasted to - * padding. It also helps to keep smaller fields early in the structure, - * so that elements tend to be in the 128-element direct access window - * on Arm Thumb, which reduces the code size. */ - - mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(max_tls_version); /*!< max. TLS version used */ - mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(min_tls_version); /*!< min. TLS version used */ - - /* - * Flags (could be bit-fields to save RAM, but separate bytes make - * the code smaller on architectures with an instruction for direct - * byte access). - */ - - uint8_t MBEDTLS_PRIVATE(endpoint); /*!< 0: client, 1: server */ - uint8_t MBEDTLS_PRIVATE(transport); /*!< 0: stream (TLS), 1: datagram (DTLS) */ - uint8_t MBEDTLS_PRIVATE(authmode); /*!< MBEDTLS_SSL_VERIFY_XXX */ - /* needed even with renego disabled for LEGACY_BREAK_HANDSHAKE */ - uint8_t MBEDTLS_PRIVATE(allow_legacy_renegotiation); /*!< MBEDTLS_LEGACY_XXX */ -#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) - uint8_t MBEDTLS_PRIVATE(mfl_code); /*!< desired fragment length indicator - (MBEDTLS_SSL_MAX_FRAG_LEN_XXX) */ -#endif -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - uint8_t MBEDTLS_PRIVATE(encrypt_then_mac); /*!< negotiate encrypt-then-mac? */ -#endif -#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) - uint8_t MBEDTLS_PRIVATE(extended_ms); /*!< negotiate extended master secret? */ -#endif -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - uint8_t MBEDTLS_PRIVATE(anti_replay); /*!< detect and prevent replay? */ -#endif -#if defined(MBEDTLS_SSL_RENEGOTIATION) - uint8_t MBEDTLS_PRIVATE(disable_renegotiation); /*!< disable renegotiation? */ -#endif -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_CLI_C) - uint8_t MBEDTLS_PRIVATE(session_tickets); /*!< use session tickets? */ -#endif - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_SRV_C) && \ - defined(MBEDTLS_SSL_PROTO_TLS1_3) - uint16_t MBEDTLS_PRIVATE(new_session_tickets_count); /*!< number of NewSessionTicket */ -#endif - -#if defined(MBEDTLS_SSL_SRV_C) - uint8_t MBEDTLS_PRIVATE(cert_req_ca_list); /*!< enable sending CA list in - Certificate Request messages? */ - uint8_t MBEDTLS_PRIVATE(respect_cli_pref); /*!< pick the ciphersuite according to - the client's preferences rather - than ours? */ -#endif -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - uint8_t MBEDTLS_PRIVATE(ignore_unexpected_cid); /*!< Should DTLS record with - * unexpected CID - * lead to failure? */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ -#if defined(MBEDTLS_SSL_DTLS_SRTP) - uint8_t MBEDTLS_PRIVATE(dtls_srtp_mki_support); /* support having mki_value - in the use_srtp extension? */ -#endif - - /* - * Pointers - */ - - /** Allowed ciphersuites for (D)TLS 1.2 (0-terminated) */ - const int *MBEDTLS_PRIVATE(ciphersuite_list); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - /** Allowed TLS 1.3 key exchange modes. */ - int MBEDTLS_PRIVATE(tls13_kex_modes); -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - - /** Callback for printing debug output */ - void(*MBEDTLS_PRIVATE(f_dbg))(void *, int, const char *, int, const char *); - void *MBEDTLS_PRIVATE(p_dbg); /*!< context for the debug function */ - - /** Callback for getting (pseudo-)random numbers */ - int(*MBEDTLS_PRIVATE(f_rng))(void *, unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_rng); /*!< context for the RNG function */ - - /** Callback to retrieve a session from the cache */ - mbedtls_ssl_cache_get_t *MBEDTLS_PRIVATE(f_get_cache); - /** Callback to store a session into the cache */ - mbedtls_ssl_cache_set_t *MBEDTLS_PRIVATE(f_set_cache); - void *MBEDTLS_PRIVATE(p_cache); /*!< context for cache callbacks */ - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) - /** Callback for setting cert according to SNI extension */ - int(*MBEDTLS_PRIVATE(f_sni))(void *, mbedtls_ssl_context *, const unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_sni); /*!< context for SNI callback */ -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) - /** Callback to customize X.509 certificate chain verification */ - int(*MBEDTLS_PRIVATE(f_vrfy))(void *, mbedtls_x509_crt *, int, uint32_t *); - void *MBEDTLS_PRIVATE(p_vrfy); /*!< context for X.509 verify calllback */ -#endif - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) -#if defined(MBEDTLS_SSL_SRV_C) - /** Callback to retrieve PSK key from identity */ - int(*MBEDTLS_PRIVATE(f_psk))(void *, mbedtls_ssl_context *, const unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_psk); /*!< context for PSK callback */ -#endif -#endif - -#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) - /** Callback to create & write a cookie for ClientHello verification */ - int(*MBEDTLS_PRIVATE(f_cookie_write))(void *, unsigned char **, unsigned char *, - const unsigned char *, size_t); - /** Callback to verify validity of a ClientHello cookie */ - int(*MBEDTLS_PRIVATE(f_cookie_check))(void *, const unsigned char *, size_t, - const unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_cookie); /*!< context for the cookie callbacks */ -#endif - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C) - /** Callback to create & write a session ticket */ - int(*MBEDTLS_PRIVATE(f_ticket_write))(void *, const mbedtls_ssl_session *, - unsigned char *, const unsigned char *, size_t *, - uint32_t *); - /** Callback to parse a session ticket into a session structure */ - int(*MBEDTLS_PRIVATE(f_ticket_parse))(void *, mbedtls_ssl_session *, unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_ticket); /*!< context for the ticket callbacks */ -#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - size_t MBEDTLS_PRIVATE(cid_len); /*!< The length of CIDs for incoming DTLS records. */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) - const mbedtls_x509_crt_profile *MBEDTLS_PRIVATE(cert_profile); /*!< verification profile */ - mbedtls_ssl_key_cert *MBEDTLS_PRIVATE(key_cert); /*!< own certificate/key pair(s) */ - mbedtls_x509_crt *MBEDTLS_PRIVATE(ca_chain); /*!< trusted CAs */ - mbedtls_x509_crl *MBEDTLS_PRIVATE(ca_crl); /*!< trusted CAs CRLs */ -#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) - mbedtls_x509_crt_ca_cb_t MBEDTLS_PRIVATE(f_ca_cb); - void *MBEDTLS_PRIVATE(p_ca_cb); -#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) -#if defined(MBEDTLS_X509_CRT_PARSE_C) - mbedtls_ssl_async_sign_t *MBEDTLS_PRIVATE(f_async_sign_start); /*!< start asynchronous signature operation */ - mbedtls_ssl_async_decrypt_t *MBEDTLS_PRIVATE(f_async_decrypt_start); /*!< start asynchronous decryption operation */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - mbedtls_ssl_async_resume_t *MBEDTLS_PRIVATE(f_async_resume); /*!< resume asynchronous operation */ - mbedtls_ssl_async_cancel_t *MBEDTLS_PRIVATE(f_async_cancel); /*!< cancel asynchronous operation */ - void *MBEDTLS_PRIVATE(p_async_config_data); /*!< Configuration data set by mbedtls_ssl_conf_async_private_cb(). */ -#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) - const int *MBEDTLS_PRIVATE(sig_hashes); /*!< allowed signature hashes */ -#endif - const uint16_t *MBEDTLS_PRIVATE(sig_algs); /*!< allowed signature algorithms */ -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - -#if defined(MBEDTLS_ECP_C) && !defined(MBEDTLS_DEPRECATED_REMOVED) - const mbedtls_ecp_group_id *MBEDTLS_PRIVATE(curve_list); /*!< allowed curves */ -#endif - - const uint16_t *MBEDTLS_PRIVATE(group_list); /*!< allowed IANA NamedGroups */ - -#if defined(MBEDTLS_DHM_C) - mbedtls_mpi MBEDTLS_PRIVATE(dhm_P); /*!< prime modulus for DHM */ - mbedtls_mpi MBEDTLS_PRIVATE(dhm_G); /*!< generator for DHM */ -#endif - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) - -#if defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(psk_opaque); /*!< PSA key slot holding opaque PSK. This field - * should only be set via - * mbedtls_ssl_conf_psk_opaque(). - * If either no PSK or a raw PSK have been - * configured, this has value \c 0. - */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - unsigned char *MBEDTLS_PRIVATE(psk); /*!< The raw pre-shared key. This field should - * only be set via mbedtls_ssl_conf_psk(). - * If either no PSK or an opaque PSK - * have been configured, this has value NULL. */ - size_t MBEDTLS_PRIVATE(psk_len); /*!< The length of the raw pre-shared key. - * This field should only be set via - * mbedtls_ssl_conf_psk(). - * Its value is non-zero if and only if - * \c psk is not \c NULL. */ - - unsigned char *MBEDTLS_PRIVATE(psk_identity); /*!< The PSK identity for PSK negotiation. - * This field should only be set via - * mbedtls_ssl_conf_psk(). - * This is set if and only if either - * \c psk or \c psk_opaque are set. */ - size_t MBEDTLS_PRIVATE(psk_identity_len);/*!< The length of PSK identity. - * This field should only be set via - * mbedtls_ssl_conf_psk(). - * Its value is non-zero if and only if - * \c psk is not \c NULL or \c psk_opaque - * is not \c 0. */ -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ - -#if defined(MBEDTLS_SSL_EARLY_DATA) - int MBEDTLS_PRIVATE(early_data_enabled); /*!< Early data enablement: - * - MBEDTLS_SSL_EARLY_DATA_DISABLED, - * - MBEDTLS_SSL_EARLY_DATA_ENABLED */ - -#if defined(MBEDTLS_SSL_SRV_C) - /* The maximum amount of 0-RTT data. RFC 8446 section 4.6.1 */ - uint32_t MBEDTLS_PRIVATE(max_early_data_size); -#endif /* MBEDTLS_SSL_SRV_C */ - -#endif /* MBEDTLS_SSL_EARLY_DATA */ - -#if defined(MBEDTLS_SSL_ALPN) - const char **MBEDTLS_PRIVATE(alpn_list); /*!< ordered list of protocols */ -#endif - -#if defined(MBEDTLS_SSL_DTLS_SRTP) - /*! ordered list of supported srtp profile */ - const mbedtls_ssl_srtp_profile *MBEDTLS_PRIVATE(dtls_srtp_profile_list); - /*! number of supported profiles */ - size_t MBEDTLS_PRIVATE(dtls_srtp_profile_list_len); -#endif /* MBEDTLS_SSL_DTLS_SRTP */ - - /* - * Numerical settings (int) - */ - - uint32_t MBEDTLS_PRIVATE(read_timeout); /*!< timeout for mbedtls_ssl_read (ms) */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - uint32_t MBEDTLS_PRIVATE(hs_timeout_min); /*!< initial value of the handshake - retransmission timeout (ms) */ - uint32_t MBEDTLS_PRIVATE(hs_timeout_max); /*!< maximum value of the handshake - retransmission timeout (ms) */ -#endif - -#if defined(MBEDTLS_SSL_RENEGOTIATION) - int MBEDTLS_PRIVATE(renego_max_records); /*!< grace period for renegotiation */ - unsigned char MBEDTLS_PRIVATE(renego_period)[8]; /*!< value of the record counters - that triggers renegotiation */ -#endif - - unsigned int MBEDTLS_PRIVATE(badmac_limit); /*!< limit of records with a bad MAC */ - -#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C) - unsigned int MBEDTLS_PRIVATE(dhm_min_bitlen); /*!< min. bit length of the DHM prime */ -#endif - - /** User data pointer or handle. - * - * The library sets this to \p 0 when creating a context and does not - * access it afterwards. - */ - mbedtls_ssl_user_data_t MBEDTLS_PRIVATE(user_data); - -#if defined(MBEDTLS_SSL_SRV_C) - mbedtls_ssl_hs_cb_t MBEDTLS_PRIVATE(f_cert_cb); /*!< certificate selection callback */ -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) - const mbedtls_x509_crt *MBEDTLS_PRIVATE(dn_hints);/*!< acceptable client cert issuers */ -#endif -}; - -struct mbedtls_ssl_context { - const mbedtls_ssl_config *MBEDTLS_PRIVATE(conf); /*!< configuration information */ - - /* - * Miscellaneous - */ - int MBEDTLS_PRIVATE(state); /*!< SSL handshake: current state */ -#if defined(MBEDTLS_SSL_RENEGOTIATION) - int MBEDTLS_PRIVATE(renego_status); /*!< Initial, in progress, pending? */ - int MBEDTLS_PRIVATE(renego_records_seen); /*!< Records since renego request, or with DTLS, - number of retransmissions of request if - renego_max_records is < 0 */ -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - - /** - * Maximum TLS version to be negotiated, then negotiated TLS version. - * - * It is initialized as the configured maximum TLS version to be - * negotiated by mbedtls_ssl_setup(). - * - * When renegotiating or resuming a session, it is overwritten in the - * ClientHello writing preparation stage with the previously negotiated - * TLS version. - * - * On client side, it is updated to the TLS version selected by the server - * for the handshake when the ServerHello is received. - * - * On server side, it is updated to the TLS version the server selects for - * the handshake when the ClientHello is received. - */ - mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(tls_version); - - unsigned MBEDTLS_PRIVATE(badmac_seen); /*!< records with a bad MAC received */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) - /** Callback to customize X.509 certificate chain verification */ - int(*MBEDTLS_PRIVATE(f_vrfy))(void *, mbedtls_x509_crt *, int, uint32_t *); - void *MBEDTLS_PRIVATE(p_vrfy); /*!< context for X.509 verify callback */ -#endif - - mbedtls_ssl_send_t *MBEDTLS_PRIVATE(f_send); /*!< Callback for network send */ - mbedtls_ssl_recv_t *MBEDTLS_PRIVATE(f_recv); /*!< Callback for network receive */ - mbedtls_ssl_recv_timeout_t *MBEDTLS_PRIVATE(f_recv_timeout); - /*!< Callback for network receive with timeout */ - - void *MBEDTLS_PRIVATE(p_bio); /*!< context for I/O operations */ - - /* - * Session layer - */ - mbedtls_ssl_session *MBEDTLS_PRIVATE(session_in); /*!< current session data (in) */ - mbedtls_ssl_session *MBEDTLS_PRIVATE(session_out); /*!< current session data (out) */ - mbedtls_ssl_session *MBEDTLS_PRIVATE(session); /*!< negotiated session data */ - mbedtls_ssl_session *MBEDTLS_PRIVATE(session_negotiate); /*!< session data in negotiation */ - - mbedtls_ssl_handshake_params *MBEDTLS_PRIVATE(handshake); /*!< params required only during - the handshake process */ - - /* - * Record layer transformations - */ - mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_in); /*!< current transform params (in) - * This is always a reference, - * never an owning pointer. */ - mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_out); /*!< current transform params (out) - * This is always a reference, - * never an owning pointer. */ - mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform); /*!< negotiated transform params - * This pointer owns the transform - * it references. */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_negotiate); /*!< transform params in negotiation - * This pointer owns the transform - * it references. */ -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - /*! The application data transform in TLS 1.3. - * This pointer owns the transform it references. */ - mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_application); -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - - /* - * Timers - */ - void *MBEDTLS_PRIVATE(p_timer); /*!< context for the timer callbacks */ - - mbedtls_ssl_set_timer_t *MBEDTLS_PRIVATE(f_set_timer); /*!< set timer callback */ - mbedtls_ssl_get_timer_t *MBEDTLS_PRIVATE(f_get_timer); /*!< get timer callback */ - - /* - * Record layer (incoming data) - */ - unsigned char *MBEDTLS_PRIVATE(in_buf); /*!< input buffer */ - unsigned char *MBEDTLS_PRIVATE(in_ctr); /*!< 64-bit incoming message counter - TLS: maintained by us - DTLS: read from peer */ - unsigned char *MBEDTLS_PRIVATE(in_hdr); /*!< start of record header */ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - unsigned char *MBEDTLS_PRIVATE(in_cid); /*!< The start of the CID; - * (the end is marked by in_len). */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - unsigned char *MBEDTLS_PRIVATE(in_len); /*!< two-bytes message length field */ - unsigned char *MBEDTLS_PRIVATE(in_iv); /*!< ivlen-byte IV */ - unsigned char *MBEDTLS_PRIVATE(in_msg); /*!< message contents (in_iv+ivlen) */ - unsigned char *MBEDTLS_PRIVATE(in_offt); /*!< read offset in application data */ - - int MBEDTLS_PRIVATE(in_msgtype); /*!< record header: message type */ - size_t MBEDTLS_PRIVATE(in_msglen); /*!< record header: message length */ - size_t MBEDTLS_PRIVATE(in_left); /*!< amount of data read so far */ -#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) - size_t MBEDTLS_PRIVATE(in_buf_len); /*!< length of input buffer */ -#endif -#if defined(MBEDTLS_SSL_PROTO_DTLS) - uint16_t MBEDTLS_PRIVATE(in_epoch); /*!< DTLS epoch for incoming records */ - size_t MBEDTLS_PRIVATE(next_record_offset); /*!< offset of the next record in datagram - (equal to in_left if none) */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - uint64_t MBEDTLS_PRIVATE(in_window_top); /*!< last validated record seq_num */ - uint64_t MBEDTLS_PRIVATE(in_window); /*!< bitmask for replay detection */ -#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ - - size_t MBEDTLS_PRIVATE(in_hslen); /*!< current handshake message length, - including the handshake header */ - int MBEDTLS_PRIVATE(nb_zero); /*!< # of 0-length encrypted messages */ - - int MBEDTLS_PRIVATE(keep_current_message); /*!< drop or reuse current message - on next call to record layer? */ - - /* The following three variables indicate if and, if yes, - * what kind of alert is pending to be sent. - */ - unsigned char MBEDTLS_PRIVATE(send_alert); /*!< Determines if a fatal alert - should be sent. Values: - - \c 0 , no alert is to be sent. - - \c 1 , alert is to be sent. */ - unsigned char MBEDTLS_PRIVATE(alert_type); /*!< Type of alert if send_alert - != 0 */ - int MBEDTLS_PRIVATE(alert_reason); /*!< The error code to be returned - to the user once the fatal alert - has been sent. */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - uint8_t MBEDTLS_PRIVATE(disable_datagram_packing); /*!< Disable packing multiple records - * within a single datagram. */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* - * Record layer (outgoing data) - */ - unsigned char *MBEDTLS_PRIVATE(out_buf); /*!< output buffer */ - unsigned char *MBEDTLS_PRIVATE(out_ctr); /*!< 64-bit outgoing message counter */ - unsigned char *MBEDTLS_PRIVATE(out_hdr); /*!< start of record header */ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - unsigned char *MBEDTLS_PRIVATE(out_cid); /*!< The start of the CID; - * (the end is marked by in_len). */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - unsigned char *MBEDTLS_PRIVATE(out_len); /*!< two-bytes message length field */ - unsigned char *MBEDTLS_PRIVATE(out_iv); /*!< ivlen-byte IV */ - unsigned char *MBEDTLS_PRIVATE(out_msg); /*!< message contents (out_iv+ivlen) */ - - int MBEDTLS_PRIVATE(out_msgtype); /*!< record header: message type */ - size_t MBEDTLS_PRIVATE(out_msglen); /*!< record header: message length */ - size_t MBEDTLS_PRIVATE(out_left); /*!< amount of data not yet written */ -#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) - size_t MBEDTLS_PRIVATE(out_buf_len); /*!< length of output buffer */ -#endif - - unsigned char MBEDTLS_PRIVATE(cur_out_ctr)[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /*!< Outgoing record sequence number. */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - uint16_t MBEDTLS_PRIVATE(mtu); /*!< path mtu, used to fragment outgoing messages */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* - * User settings - */ -#if defined(MBEDTLS_X509_CRT_PARSE_C) - char *MBEDTLS_PRIVATE(hostname); /*!< expected peer CN for verification - (and SNI if available) */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_ALPN) - const char *MBEDTLS_PRIVATE(alpn_chosen); /*!< negotiated protocol */ -#endif /* MBEDTLS_SSL_ALPN */ - -#if defined(MBEDTLS_SSL_DTLS_SRTP) - /* - * use_srtp extension - */ - mbedtls_dtls_srtp_info MBEDTLS_PRIVATE(dtls_srtp_info); -#endif /* MBEDTLS_SSL_DTLS_SRTP */ - - /* - * Information for DTLS hello verify - */ -#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) - unsigned char *MBEDTLS_PRIVATE(cli_id); /*!< transport-level ID of the client */ - size_t MBEDTLS_PRIVATE(cli_id_len); /*!< length of cli_id */ -#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */ - - /* - * Secure renegotiation - */ - /* needed to know when to send extension on server */ - int MBEDTLS_PRIVATE(secure_renegotiation); /*!< does peer support legacy or - secure renegotiation */ -#if defined(MBEDTLS_SSL_RENEGOTIATION) - size_t MBEDTLS_PRIVATE(verify_data_len); /*!< length of verify data stored */ - char MBEDTLS_PRIVATE(own_verify_data)[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!< previous handshake verify data */ - char MBEDTLS_PRIVATE(peer_verify_data)[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!< previous handshake verify data */ -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* CID configuration to use in subsequent handshakes. */ - - /*! The next incoming CID, chosen by the user and applying to - * all subsequent handshakes. This may be different from the - * CID currently used in case the user has re-configured the CID - * after an initial handshake. */ - unsigned char MBEDTLS_PRIVATE(own_cid)[MBEDTLS_SSL_CID_IN_LEN_MAX]; - uint8_t MBEDTLS_PRIVATE(own_cid_len); /*!< The length of \c own_cid. */ - uint8_t MBEDTLS_PRIVATE(negotiate_cid); /*!< This indicates whether the CID extension should - * be negotiated in the next handshake or not. - * Possible values are #MBEDTLS_SSL_CID_ENABLED - * and #MBEDTLS_SSL_CID_DISABLED. */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -#if defined(MBEDTLS_SSL_EARLY_DATA) && defined(MBEDTLS_SSL_CLI_C) - int MBEDTLS_PRIVATE(early_data_status); -#endif /* MBEDTLS_SSL_EARLY_DATA && MBEDTLS_SSL_CLI_C */ - - /** Callback to export key block and master secret */ - mbedtls_ssl_export_keys_t *MBEDTLS_PRIVATE(f_export_keys); - void *MBEDTLS_PRIVATE(p_export_keys); /*!< context for key export callback */ - - /** User data pointer or handle. - * - * The library sets this to \p 0 when creating a context and does not - * access it afterwards. - * - * \warning Serializing and restoring an SSL context with - * mbedtls_ssl_context_save() and mbedtls_ssl_context_load() - * does not currently restore the user data. - */ - mbedtls_ssl_user_data_t MBEDTLS_PRIVATE(user_data); -}; - -/** - * \brief Return the name of the ciphersuite associated with the - * given ID - * - * \param ciphersuite_id SSL ciphersuite ID - * - * \return a string containing the ciphersuite name - */ -const char *mbedtls_ssl_get_ciphersuite_name(const int ciphersuite_id); - -/** - * \brief Return the ID of the ciphersuite associated with the - * given name - * - * \param ciphersuite_name SSL ciphersuite name - * - * \return the ID with the ciphersuite or 0 if not found - */ -int mbedtls_ssl_get_ciphersuite_id(const char *ciphersuite_name); - -/** - * \brief Initialize an SSL context - * Just makes the context ready for mbedtls_ssl_setup() or - * mbedtls_ssl_free() - * - * \param ssl SSL context - */ -void mbedtls_ssl_init(mbedtls_ssl_context *ssl); - -/** - * \brief Set up an SSL context for use - * - * \note No copy of the configuration context is made, it can be - * shared by many mbedtls_ssl_context structures. - * - * \warning The conf structure will be accessed during the session. - * It must not be modified or freed as long as the session - * is active. - * - * \warning This function must be called exactly once per context. - * Calling mbedtls_ssl_setup again is not supported, even - * if no session is active. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param ssl SSL context - * \param conf SSL configuration to use - * - * \return 0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED if - * memory allocation failed - */ -int mbedtls_ssl_setup(mbedtls_ssl_context *ssl, - const mbedtls_ssl_config *conf); - -/** - * \brief Reset an already initialized SSL context for re-use - * while retaining application-set variables, function - * pointers and data. - * - * \param ssl SSL context - * \return 0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED or - MBEDTLS_ERR_SSL_HW_ACCEL_FAILED - */ -int mbedtls_ssl_session_reset(mbedtls_ssl_context *ssl); - -/** - * \brief Set the current endpoint type - * - * \param conf SSL configuration - * \param endpoint must be MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER - */ -void mbedtls_ssl_conf_endpoint(mbedtls_ssl_config *conf, int endpoint); - -/** - * \brief Get the current endpoint type - * - * \param conf SSL configuration - * - * \return Endpoint type, either MBEDTLS_SSL_IS_CLIENT - * or MBEDTLS_SSL_IS_SERVER - */ -static inline int mbedtls_ssl_conf_get_endpoint(const mbedtls_ssl_config *conf) -{ - return conf->MBEDTLS_PRIVATE(endpoint); -} - -/** - * \brief Set the transport type (TLS or DTLS). - * Default: TLS - * - * \note For DTLS, you must either provide a recv callback that - * doesn't block, or one that handles timeouts, see - * \c mbedtls_ssl_set_bio(). You also need to provide timer - * callbacks with \c mbedtls_ssl_set_timer_cb(). - * - * \param conf SSL configuration - * \param transport transport type: - * MBEDTLS_SSL_TRANSPORT_STREAM for TLS, - * MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS. - */ -void mbedtls_ssl_conf_transport(mbedtls_ssl_config *conf, int transport); - -/** - * \brief Set the certificate verification mode - * Default: NONE on server, REQUIRED on client - * - * \param conf SSL configuration - * \param authmode can be: - * - * MBEDTLS_SSL_VERIFY_NONE: peer certificate is not checked - * (default on server) - * (insecure on client) - * - * MBEDTLS_SSL_VERIFY_OPTIONAL: peer certificate is checked, however the - * handshake continues even if verification failed; - * mbedtls_ssl_get_verify_result() can be called after the - * handshake is complete. - * - * MBEDTLS_SSL_VERIFY_REQUIRED: peer *must* present a valid certificate, - * handshake is aborted if verification failed. - * (default on client) - * - * \note On client, MBEDTLS_SSL_VERIFY_REQUIRED is the recommended mode. - * With MBEDTLS_SSL_VERIFY_OPTIONAL, the user needs to call mbedtls_ssl_get_verify_result() at - * the right time(s), which may not be obvious, while REQUIRED always perform - * the verification as soon as possible. For example, REQUIRED was protecting - * against the "triple handshake" attack even before it was found. - */ -void mbedtls_ssl_conf_authmode(mbedtls_ssl_config *conf, int authmode); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_EARLY_DATA) -/** - * \brief Set the early data mode - * Default: disabled on server and client - * - * \param conf The SSL configuration to use. - * \param early_data_enabled can be: - * - * MBEDTLS_SSL_EARLY_DATA_DISABLED: early data functionality is disabled - * This is the default on client and server. - * - * MBEDTLS_SSL_EARLY_DATA_ENABLED: early data functionality is enabled and - * may be negotiated in the handshake. Application using - * early data functionality needs to be aware of the - * lack of replay protection of the early data application - * payloads. - * - * \warning This interface is experimental and may change without notice. - * - */ -void mbedtls_ssl_tls13_conf_early_data(mbedtls_ssl_config *conf, - int early_data_enabled); - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Set the maximum amount of 0-RTT data in bytes - * Default: #MBEDTLS_SSL_MAX_EARLY_DATA_SIZE - * - * This function sets the value of the max_early_data_size - * field of the early data indication extension included in - * the NewSessionTicket messages that the server may send. - * - * The value defines the maximum amount of 0-RTT data - * in bytes that a client will be allowed to send when using - * one of the tickets defined by the NewSessionTicket messages. - * - * \note When resuming a session using a ticket, if the server receives more - * early data than allowed for the ticket, it terminates the connection. - * The maximum amount of 0-RTT data should thus be large enough - * to allow a minimum of early data to be exchanged. - * - * \param[in] conf The SSL configuration to use. - * \param[in] max_early_data_size The maximum amount of 0-RTT data. - * - * \warning This interface is experimental and may change without notice. - * - */ -void mbedtls_ssl_tls13_conf_max_early_data_size( - mbedtls_ssl_config *conf, uint32_t max_early_data_size); -#endif /* MBEDTLS_SSL_SRV_C */ - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_EARLY_DATA */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Set the verification callback (Optional). - * - * If set, the provided verify callback is called for each - * certificate in the peer's CRT chain, including the trusted - * root. For more information, please see the documentation of - * \c mbedtls_x509_crt_verify(). - * - * \note For per context callbacks and contexts, please use - * mbedtls_ssl_set_verify() instead. - * - * \param conf The SSL configuration to use. - * \param f_vrfy The verification callback to use during CRT verification. - * \param p_vrfy The opaque context to be passed to the callback. - */ -void mbedtls_ssl_conf_verify(mbedtls_ssl_config *conf, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -/** - * \brief Set the random number generator callback - * - * \param conf SSL configuration - * \param f_rng RNG function (mandatory) - * \param p_rng RNG parameter - */ -void mbedtls_ssl_conf_rng(mbedtls_ssl_config *conf, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Set the debug callback - * - * The callback has the following argument: - * void * opaque context for the callback - * int debug level - * const char * file name - * int line number - * const char * message - * - * \param conf SSL configuration - * \param f_dbg debug function - * \param p_dbg debug parameter - */ -void mbedtls_ssl_conf_dbg(mbedtls_ssl_config *conf, - void (*f_dbg)(void *, int, const char *, int, const char *), - void *p_dbg); - -/** - * \brief Return the SSL configuration structure associated - * with the given SSL context. - * - * \note The pointer returned by this function is guaranteed to - * remain valid until the context is freed. - * - * \param ssl The SSL context to query. - * \return Pointer to the SSL configuration associated with \p ssl. - */ -static inline const mbedtls_ssl_config *mbedtls_ssl_context_get_config( - const mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(conf); -} - -/** - * \brief Set the underlying BIO callbacks for write, read and - * read-with-timeout. - * - * \param ssl SSL context - * \param p_bio parameter (context) shared by BIO callbacks - * \param f_send write callback - * \param f_recv read callback - * \param f_recv_timeout blocking read callback with timeout. - * - * \note One of f_recv or f_recv_timeout can be NULL, in which case - * the other is used. If both are non-NULL, f_recv_timeout is - * used and f_recv is ignored (as if it were NULL). - * - * \note The two most common use cases are: - * - non-blocking I/O, f_recv != NULL, f_recv_timeout == NULL - * - blocking I/O, f_recv == NULL, f_recv_timeout != NULL - * - * \note For DTLS, you need to provide either a non-NULL - * f_recv_timeout callback, or a f_recv that doesn't block. - * - * \note See the documentations of \c mbedtls_ssl_send_t, - * \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for - * the conventions those callbacks must follow. - * - * \note On some platforms, net_sockets.c provides - * \c mbedtls_net_send(), \c mbedtls_net_recv() and - * \c mbedtls_net_recv_timeout() that are suitable to be used - * here. - */ -void mbedtls_ssl_set_bio(mbedtls_ssl_context *ssl, - void *p_bio, - mbedtls_ssl_send_t *f_send, - mbedtls_ssl_recv_t *f_recv, - mbedtls_ssl_recv_timeout_t *f_recv_timeout); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - - -/** - * \brief Configure the use of the Connection ID (CID) - * extension in the next handshake. - * - * Reference: RFC 9146 (or draft-ietf-tls-dtls-connection-id-05 - * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05 - * for legacy version) - * - * The DTLS CID extension allows the reliable association of - * DTLS records to DTLS connections across changes in the - * underlying transport (changed IP and Port metadata) by - * adding explicit connection identifiers (CIDs) to the - * headers of encrypted DTLS records. The desired CIDs are - * configured by the application layer and are exchanged in - * new `ClientHello` / `ServerHello` extensions during the - * handshake, where each side indicates the CID it wants the - * peer to use when writing encrypted messages. The CIDs are - * put to use once records get encrypted: the stack discards - * any incoming records that don't include the configured CID - * in their header, and adds the peer's requested CID to the - * headers of outgoing messages. - * - * This API enables or disables the use of the CID extension - * in the next handshake and sets the value of the CID to - * be used for incoming messages. - * - * \param ssl The SSL context to configure. This must be initialized. - * \param enable This value determines whether the CID extension should - * be used or not. Possible values are: - * - MBEDTLS_SSL_CID_ENABLED to enable the use of the CID. - * - MBEDTLS_SSL_CID_DISABLED (default) to disable the use - * of the CID. - * \param own_cid The address of the readable buffer holding the CID we want - * the peer to use when sending encrypted messages to us. - * This may be \c NULL if \p own_cid_len is \c 0. - * This parameter is unused if \p enable is set to - * MBEDTLS_SSL_CID_DISABLED. - * \param own_cid_len The length of \p own_cid. - * This parameter is unused if \p enable is set to - * MBEDTLS_SSL_CID_DISABLED. - * - * \note The value of \p own_cid_len must match the value of the - * \c len parameter passed to mbedtls_ssl_conf_cid() - * when configuring the ::mbedtls_ssl_config that \p ssl - * is bound to. - * - * \note This CID configuration applies to subsequent handshakes - * performed on the SSL context \p ssl, but does not trigger - * one. You still have to call `mbedtls_ssl_handshake()` - * (for the initial handshake) or `mbedtls_ssl_renegotiate()` - * (for a renegotiation handshake) explicitly after a - * successful call to this function to run the handshake. - * - * \note This call cannot guarantee that the use of the CID - * will be successfully negotiated in the next handshake, - * because the peer might not support it. Specifically: - * - On the Client, enabling the use of the CID through - * this call implies that the `ClientHello` in the next - * handshake will include the CID extension, thereby - * offering the use of the CID to the server. Only if - * the `ServerHello` contains the CID extension, too, - * the CID extension will actually be put to use. - * - On the Server, enabling the use of the CID through - * this call implies that the server will look for - * the CID extension in a `ClientHello` from the client, - * and, if present, reply with a CID extension in its - * `ServerHello`. - * - * \note To check whether the use of the CID was negotiated - * after the subsequent handshake has completed, please - * use the API mbedtls_ssl_get_peer_cid(). - * - * \warning If the use of the CID extension is enabled in this call - * and the subsequent handshake negotiates its use, Mbed TLS - * will silently drop every packet whose CID does not match - * the CID configured in \p own_cid. It is the responsibility - * of the user to adapt the underlying transport to take care - * of CID-based demultiplexing before handing datagrams to - * Mbed TLS. - * - * \return \c 0 on success. In this case, the CID configuration - * applies to the next handshake. - * \return A negative error code on failure. - */ -int mbedtls_ssl_set_cid(mbedtls_ssl_context *ssl, - int enable, - unsigned char const *own_cid, - size_t own_cid_len); - -/** - * \brief Get information about our request for usage of the CID - * extension in the current connection. - * - * \param ssl The SSL context to query. - * \param enabled The address at which to store whether the CID extension - * is requested to be used or not. If the CID is - * requested, `*enabled` is set to - * MBEDTLS_SSL_CID_ENABLED; otherwise, it is set to - * MBEDTLS_SSL_CID_DISABLED. - * \param own_cid The address of the buffer in which to store our own - * CID (if the CID extension is requested). This may be - * \c NULL in case the value of our CID isn't needed. If - * it is not \c NULL, \p own_cid_len must not be \c NULL. - * \param own_cid_len The address at which to store the size of our own CID - * (if the CID extension is requested). This is also the - * number of Bytes in \p own_cid that have been written. - * This may be \c NULL in case the length of our own CID - * isn't needed. If it is \c NULL, \p own_cid must be - * \c NULL, too. - * - *\note If we are requesting an empty CID this function sets - * `*enabled` to #MBEDTLS_SSL_CID_DISABLED (the rationale - * for this is that the resulting outcome is the - * same as if the CID extensions wasn't requested). - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_ssl_get_own_cid(mbedtls_ssl_context *ssl, - int *enabled, - unsigned char own_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX], - size_t *own_cid_len); - -/** - * \brief Get information about the use of the CID extension - * in the current connection. - * - * \param ssl The SSL context to query. - * \param enabled The address at which to store whether the CID extension - * is currently in use or not. If the CID is in use, - * `*enabled` is set to MBEDTLS_SSL_CID_ENABLED; - * otherwise, it is set to MBEDTLS_SSL_CID_DISABLED. - * \param peer_cid The address of the buffer in which to store the CID - * chosen by the peer (if the CID extension is used). - * This may be \c NULL in case the value of peer CID - * isn't needed. If it is not \c NULL, \p peer_cid_len - * must not be \c NULL. - * \param peer_cid_len The address at which to store the size of the CID - * chosen by the peer (if the CID extension is used). - * This is also the number of Bytes in \p peer_cid that - * have been written. - * This may be \c NULL in case the length of the peer CID - * isn't needed. If it is \c NULL, \p peer_cid must be - * \c NULL, too. - * - * \note This applies to the state of the CID negotiated in - * the last complete handshake. If a handshake is in - * progress, this function will attempt to complete - * the handshake first. - * - * \note If CID extensions have been exchanged but both client - * and server chose to use an empty CID, this function - * sets `*enabled` to #MBEDTLS_SSL_CID_DISABLED - * (the rationale for this is that the resulting - * communication is the same as if the CID extensions - * hadn't been used). - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_ssl_get_peer_cid(mbedtls_ssl_context *ssl, - int *enabled, - unsigned char peer_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX], - size_t *peer_cid_len); - -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -/** - * \brief Set the Maximum Transport Unit (MTU). - * Special value: 0 means unset (no limit). - * This represents the maximum size of a datagram payload - * handled by the transport layer (usually UDP) as determined - * by the network link and stack. In practice, this controls - * the maximum size datagram the DTLS layer will pass to the - * \c f_send() callback set using \c mbedtls_ssl_set_bio(). - * - * \note The limit on datagram size is converted to a limit on - * record payload by subtracting the current overhead of - * encapsulation and encryption/authentication if any. - * - * \note This can be called at any point during the connection, for - * example when a Path Maximum Transfer Unit (PMTU) - * estimate becomes available from other sources, - * such as lower (or higher) protocol layers. - * - * \note This setting only controls the size of the packets we send, - * and does not restrict the size of the datagrams we're - * willing to receive. Client-side, you can request the - * server to use smaller records with \c - * mbedtls_ssl_conf_max_frag_len(). - * - * \note If both a MTU and a maximum fragment length have been - * configured (or negotiated with the peer), the resulting - * lower limit on record payload (see first note) is used. - * - * \note This can only be used to decrease the maximum size - * of datagrams (hence records, see first note) sent. It - * cannot be used to increase the maximum size of records over - * the limit set by #MBEDTLS_SSL_OUT_CONTENT_LEN. - * - * \note Values lower than the current record layer expansion will - * result in an error when trying to send data. - * - * \param ssl SSL context - * \param mtu Value of the path MTU in bytes - */ -void mbedtls_ssl_set_mtu(mbedtls_ssl_context *ssl, uint16_t mtu); -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Set a connection-specific verification callback (optional). - * - * If set, the provided verify callback is called for each - * certificate in the peer's CRT chain, including the trusted - * root. For more information, please see the documentation of - * \c mbedtls_x509_crt_verify(). - * - * \note This call is analogous to mbedtls_ssl_conf_verify() but - * binds the verification callback and context to an SSL context - * as opposed to an SSL configuration. - * If mbedtls_ssl_conf_verify() and mbedtls_ssl_set_verify() - * are both used, mbedtls_ssl_set_verify() takes precedence. - * - * \param ssl The SSL context to use. - * \param f_vrfy The verification callback to use during CRT verification. - * \param p_vrfy The opaque context to be passed to the callback. - */ -void mbedtls_ssl_set_verify(mbedtls_ssl_context *ssl, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -/** - * \brief Set the timeout period for mbedtls_ssl_read() - * (Default: no timeout.) - * - * \param conf SSL configuration context - * \param timeout Timeout value in milliseconds. - * Use 0 for no timeout (default). - * - * \note With blocking I/O, this will only work if a non-NULL - * \c f_recv_timeout was set with \c mbedtls_ssl_set_bio(). - * With non-blocking I/O, this will only work if timer - * callbacks were set with \c mbedtls_ssl_set_timer_cb(). - * - * \note With non-blocking I/O, you may also skip this function - * altogether and handle timeouts at the application layer. - */ -void mbedtls_ssl_conf_read_timeout(mbedtls_ssl_config *conf, uint32_t timeout); - -/** - * \brief Check whether a buffer contains a valid and authentic record - * that has not been seen before. (DTLS only). - * - * This function does not change the user-visible state - * of the SSL context. Its sole purpose is to provide - * an indication of the legitimacy of an incoming record. - * - * This can be useful e.g. in distributed server environments - * using the DTLS Connection ID feature, in which connections - * might need to be passed between service instances on a change - * of peer address, but where such disruptive operations should - * only happen after the validity of incoming records has been - * confirmed. - * - * \param ssl The SSL context to use. - * \param buf The address of the buffer holding the record to be checked. - * This must be a read/write buffer of length \p buflen Bytes. - * \param buflen The length of \p buf in Bytes. - * - * \note This routine only checks whether the provided buffer begins - * with a valid and authentic record that has not been seen - * before, but does not check potential data following the - * initial record. In particular, it is possible to pass DTLS - * datagrams containing multiple records, in which case only - * the first record is checked. - * - * \note This function modifies the input buffer \p buf. If you need - * to preserve the original record, you have to maintain a copy. - * - * \return \c 0 if the record is valid and authentic and has not been - * seen before. - * \return MBEDTLS_ERR_SSL_INVALID_MAC if the check completed - * successfully but the record was found to be not authentic. - * \return MBEDTLS_ERR_SSL_INVALID_RECORD if the check completed - * successfully but the record was found to be invalid for - * a reason different from authenticity checking. - * \return MBEDTLS_ERR_SSL_UNEXPECTED_RECORD if the check completed - * successfully but the record was found to be unexpected - * in the state of the SSL context, including replayed records. - * \return Another negative error code on different kinds of failure. - * In this case, the SSL context becomes unusable and needs - * to be freed or reset before reuse. - */ -int mbedtls_ssl_check_record(mbedtls_ssl_context const *ssl, - unsigned char *buf, - size_t buflen); - -/** - * \brief Set the timer callbacks (Mandatory for DTLS.) - * - * \param ssl SSL context - * \param p_timer parameter (context) shared by timer callbacks - * \param f_set_timer set timer callback - * \param f_get_timer get timer callback. Must return: - * - * \note See the documentation of \c mbedtls_ssl_set_timer_t and - * \c mbedtls_ssl_get_timer_t for the conventions this pair of - * callbacks must follow. - * - * \note On some platforms, timing.c provides - * \c mbedtls_timing_set_delay() and - * \c mbedtls_timing_get_delay() that are suitable for using - * here, except if using an event-driven style. - * - * \note See also the "DTLS tutorial" article in our knowledge base. - * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/dtls-tutorial - */ -void mbedtls_ssl_set_timer_cb(mbedtls_ssl_context *ssl, - void *p_timer, - mbedtls_ssl_set_timer_t *f_set_timer, - mbedtls_ssl_get_timer_t *f_get_timer); - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Set the certificate selection callback (server-side only). - * - * If set, the callback is always called for each handshake, - * after `ClientHello` processing has finished. - * - * \param conf The SSL configuration to register the callback with. - * \param f_cert_cb The callback for selecting server certificate after - * `ClientHello` processing has finished. - */ -static inline void mbedtls_ssl_conf_cert_cb(mbedtls_ssl_config *conf, - mbedtls_ssl_hs_cb_t f_cert_cb) -{ - conf->MBEDTLS_PRIVATE(f_cert_cb) = f_cert_cb; -} -#endif /* MBEDTLS_SSL_SRV_C */ - -/** - * \brief Callback type: generate and write session ticket - * - * \note This describes what a callback implementation should do. - * This callback should generate an encrypted and - * authenticated ticket for the session and write it to the - * output buffer. Here, ticket means the opaque ticket part - * of the NewSessionTicket structure of RFC 5077. - * - * \param p_ticket Context for the callback - * \param session SSL session to be written in the ticket - * \param start Start of the output buffer - * \param end End of the output buffer - * \param tlen On exit, holds the length written - * \param lifetime On exit, holds the lifetime of the ticket in seconds - * - * \return 0 if successful, or - * a specific MBEDTLS_ERR_XXX code. - */ -typedef int mbedtls_ssl_ticket_write_t(void *p_ticket, - const mbedtls_ssl_session *session, - unsigned char *start, - const unsigned char *end, - size_t *tlen, - uint32_t *lifetime); - -/** - * \brief Callback type: parse and load session ticket - * - * \note This describes what a callback implementation should do. - * This callback should parse a session ticket as generated - * by the corresponding mbedtls_ssl_ticket_write_t function, - * and, if the ticket is authentic and valid, load the - * session. - * - * \note The implementation is allowed to modify the first len - * bytes of the input buffer, eg to use it as a temporary - * area for the decrypted ticket contents. - * - * \param p_ticket Context for the callback - * \param session SSL session to be loaded - * \param buf Start of the buffer containing the ticket - * \param len Length of the ticket. - * - * \return 0 if successful, or - * MBEDTLS_ERR_SSL_INVALID_MAC if not authentic, or - * MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED if expired, or - * any other non-zero code for other failures. - */ -typedef int mbedtls_ssl_ticket_parse_t(void *p_ticket, - mbedtls_ssl_session *session, - unsigned char *buf, - size_t len); - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Configure SSL session ticket callbacks (server only). - * (Default: none.) - * - * \note On server, session tickets are enabled by providing - * non-NULL callbacks. - * - * \note On client, use \c mbedtls_ssl_conf_session_tickets(). - * - * \param conf SSL configuration context - * \param f_ticket_write Callback for writing a ticket - * \param f_ticket_parse Callback for parsing a ticket - * \param p_ticket Context shared by the two callbacks - */ -void mbedtls_ssl_conf_session_tickets_cb(mbedtls_ssl_config *conf, - mbedtls_ssl_ticket_write_t *f_ticket_write, - mbedtls_ssl_ticket_parse_t *f_ticket_parse, - void *p_ticket); -#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */ - -/** - * \brief Configure a key export callback. - * (Default: none.) - * - * This API can be used for two purposes: - * - Debugging: Use this API to e.g. generate an NSSKeylog - * file and use it to inspect encrypted traffic in tools - * such as Wireshark. - * - Application-specific export: Use this API to implement - * key exporters, e.g. for EAP-TLS or DTLS-SRTP. - * - * - * \param ssl The SSL context to which the export - * callback should be attached. - * \param f_export_keys The callback for the key export. - * \param p_export_keys The opaque context pointer to be passed to the - * callback \p f_export_keys. - */ -void mbedtls_ssl_set_export_keys_cb(mbedtls_ssl_context *ssl, - mbedtls_ssl_export_keys_t *f_export_keys, - void *p_export_keys); - -/** \brief Set the user data in an SSL configuration to a pointer. - * - * You can retrieve this value later with mbedtls_ssl_conf_get_user_data_p(). - * - * \note The library stores \c p without accessing it. It is the responsibility - * of the caller to ensure that the pointer remains valid. - * - * \param conf The SSL configuration context to modify. - * \param p The new value of the user data. - */ -static inline void mbedtls_ssl_conf_set_user_data_p( - mbedtls_ssl_config *conf, - void *p) -{ - conf->MBEDTLS_PRIVATE(user_data).p = p; -} - -/** \brief Set the user data in an SSL configuration to an integer. - * - * You can retrieve this value later with mbedtls_ssl_conf_get_user_data_n(). - * - * \param conf The SSL configuration context to modify. - * \param n The new value of the user data. - */ -static inline void mbedtls_ssl_conf_set_user_data_n( - mbedtls_ssl_config *conf, - uintptr_t n) -{ - conf->MBEDTLS_PRIVATE(user_data).n = n; -} - -/** \brief Retrieve the user data in an SSL configuration as a pointer. - * - * This is the value last set with mbedtls_ssl_conf_set_user_data_p(), or - * \c NULL if mbedtls_ssl_conf_set_user_data_p() has not previously been - * called. The value is undefined if mbedtls_ssl_conf_set_user_data_n() has - * been called without a subsequent call to mbedtls_ssl_conf_set_user_data_p(). - * - * \param conf The SSL configuration context to modify. - * \return The current value of the user data. - */ -static inline void *mbedtls_ssl_conf_get_user_data_p( - mbedtls_ssl_config *conf) -{ - return conf->MBEDTLS_PRIVATE(user_data).p; -} - -/** \brief Retrieve the user data in an SSL configuration as an integer. - * - * This is the value last set with mbedtls_ssl_conf_set_user_data_n(), or - * \c 0 if mbedtls_ssl_conf_set_user_data_n() has not previously been - * called. The value is undefined if mbedtls_ssl_conf_set_user_data_p() has - * been called without a subsequent call to mbedtls_ssl_conf_set_user_data_n(). - * - * \param conf The SSL configuration context to modify. - * \return The current value of the user data. - */ -static inline uintptr_t mbedtls_ssl_conf_get_user_data_n( - mbedtls_ssl_config *conf) -{ - return conf->MBEDTLS_PRIVATE(user_data).n; -} - -/** \brief Set the user data in an SSL context to a pointer. - * - * You can retrieve this value later with mbedtls_ssl_get_user_data_p(). - * - * \note The library stores \c p without accessing it. It is the responsibility - * of the caller to ensure that the pointer remains valid. - * - * \param ssl The SSL context to modify. - * \param p The new value of the user data. - */ -static inline void mbedtls_ssl_set_user_data_p( - mbedtls_ssl_context *ssl, - void *p) -{ - ssl->MBEDTLS_PRIVATE(user_data).p = p; -} - -/** \brief Set the user data in an SSL context to an integer. - * - * You can retrieve this value later with mbedtls_ssl_get_user_data_n(). - * - * \param ssl The SSL context to modify. - * \param n The new value of the user data. - */ -static inline void mbedtls_ssl_set_user_data_n( - mbedtls_ssl_context *ssl, - uintptr_t n) -{ - ssl->MBEDTLS_PRIVATE(user_data).n = n; -} - -/** \brief Retrieve the user data in an SSL context as a pointer. - * - * This is the value last set with mbedtls_ssl_set_user_data_p(), or - * \c NULL if mbedtls_ssl_set_user_data_p() has not previously been - * called. The value is undefined if mbedtls_ssl_set_user_data_n() has - * been called without a subsequent call to mbedtls_ssl_set_user_data_p(). - * - * \param ssl The SSL context to modify. - * \return The current value of the user data. - */ -static inline void *mbedtls_ssl_get_user_data_p( - mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(user_data).p; -} - -/** \brief Retrieve the user data in an SSL context as an integer. - * - * This is the value last set with mbedtls_ssl_set_user_data_n(), or - * \c 0 if mbedtls_ssl_set_user_data_n() has not previously been - * called. The value is undefined if mbedtls_ssl_set_user_data_p() has - * been called without a subsequent call to mbedtls_ssl_set_user_data_n(). - * - * \param ssl The SSL context to modify. - * \return The current value of the user data. - */ -static inline uintptr_t mbedtls_ssl_get_user_data_n( - mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(user_data).n; -} - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) -/** - * \brief Configure asynchronous private key operation callbacks. - * - * \param conf SSL configuration context - * \param f_async_sign Callback to start a signature operation. See - * the description of ::mbedtls_ssl_async_sign_t - * for more information. This may be \c NULL if the - * external processor does not support any signature - * operation; in this case the private key object - * associated with the certificate will be used. - * \param f_async_decrypt Callback to start a decryption operation. See - * the description of ::mbedtls_ssl_async_decrypt_t - * for more information. This may be \c NULL if the - * external processor does not support any decryption - * operation; in this case the private key object - * associated with the certificate will be used. - * \param f_async_resume Callback to resume an asynchronous operation. See - * the description of ::mbedtls_ssl_async_resume_t - * for more information. This may not be \c NULL unless - * \p f_async_sign and \p f_async_decrypt are both - * \c NULL. - * \param f_async_cancel Callback to cancel an asynchronous operation. See - * the description of ::mbedtls_ssl_async_cancel_t - * for more information. This may be \c NULL if - * no cleanup is needed. - * \param config_data A pointer to configuration data which can be - * retrieved with - * mbedtls_ssl_conf_get_async_config_data(). The - * library stores this value without dereferencing it. - */ -void mbedtls_ssl_conf_async_private_cb(mbedtls_ssl_config *conf, - mbedtls_ssl_async_sign_t *f_async_sign, - mbedtls_ssl_async_decrypt_t *f_async_decrypt, - mbedtls_ssl_async_resume_t *f_async_resume, - mbedtls_ssl_async_cancel_t *f_async_cancel, - void *config_data); - -/** - * \brief Retrieve the configuration data set by - * mbedtls_ssl_conf_async_private_cb(). - * - * \param conf SSL configuration context - * \return The configuration data set by - * mbedtls_ssl_conf_async_private_cb(). - */ -void *mbedtls_ssl_conf_get_async_config_data(const mbedtls_ssl_config *conf); - -/** - * \brief Retrieve the asynchronous operation user context. - * - * \note This function may only be called while a handshake - * is in progress. - * - * \param ssl The SSL context to access. - * - * \return The asynchronous operation user context that was last - * set during the current handshake. If - * mbedtls_ssl_set_async_operation_data() has not yet been - * called during the current handshake, this function returns - * \c NULL. - */ -void *mbedtls_ssl_get_async_operation_data(const mbedtls_ssl_context *ssl); - -/** - * \brief Retrieve the asynchronous operation user context. - * - * \note This function may only be called while a handshake - * is in progress. - * - * \param ssl The SSL context to access. - * \param ctx The new value of the asynchronous operation user context. - * Call mbedtls_ssl_get_async_operation_data() later during the - * same handshake to retrieve this value. - */ -void mbedtls_ssl_set_async_operation_data(mbedtls_ssl_context *ssl, - void *ctx); -#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ - -/** - * \brief Callback type: generate a cookie - * - * \param ctx Context for the callback - * \param p Buffer to write to, - * must be updated to point right after the cookie - * \param end Pointer to one past the end of the output buffer - * \param info Client ID info that was passed to - * \c mbedtls_ssl_set_client_transport_id() - * \param ilen Length of info in bytes - * - * \return The callback must return 0 on success, - * or a negative error code. - */ -typedef int mbedtls_ssl_cookie_write_t(void *ctx, - unsigned char **p, unsigned char *end, - const unsigned char *info, size_t ilen); - -/** - * \brief Callback type: verify a cookie - * - * \param ctx Context for the callback - * \param cookie Cookie to verify - * \param clen Length of cookie - * \param info Client ID info that was passed to - * \c mbedtls_ssl_set_client_transport_id() - * \param ilen Length of info in bytes - * - * \return The callback must return 0 if cookie is valid, - * or a negative error code. - */ -typedef int mbedtls_ssl_cookie_check_t(void *ctx, - const unsigned char *cookie, size_t clen, - const unsigned char *info, size_t ilen); - -#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Register callbacks for DTLS cookies - * (Server only. DTLS only.) - * - * Default: dummy callbacks that fail, in order to force you to - * register working callbacks (and initialize their context). - * - * To disable HelloVerifyRequest, register NULL callbacks. - * - * \warning Disabling hello verification allows your server to be used - * for amplification in DoS attacks against other hosts. - * Only disable if you known this can't happen in your - * particular environment. - * - * \note See comments on \c mbedtls_ssl_handshake() about handling - * the MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED that is expected - * on the first handshake attempt when this is enabled. - * - * \note This is also necessary to handle client reconnection from - * the same port as described in RFC 6347 section 4.2.8 (only - * the variant with cookies is supported currently). See - * comments on \c mbedtls_ssl_read() for details. - * - * \param conf SSL configuration - * \param f_cookie_write Cookie write callback - * \param f_cookie_check Cookie check callback - * \param p_cookie Context for both callbacks - */ -void mbedtls_ssl_conf_dtls_cookies(mbedtls_ssl_config *conf, - mbedtls_ssl_cookie_write_t *f_cookie_write, - mbedtls_ssl_cookie_check_t *f_cookie_check, - void *p_cookie); - -/** - * \brief Set client's transport-level identification info. - * (Server only. DTLS only.) - * - * This is usually the IP address (and port), but could be - * anything identify the client depending on the underlying - * network stack. Used for HelloVerifyRequest with DTLS. - * This is *not* used to route the actual packets. - * - * \param ssl SSL context - * \param info Transport-level info identifying the client (eg IP + port) - * \param ilen Length of info in bytes - * - * \note An internal copy is made, so the info buffer can be reused. - * - * \return 0 on success, - * MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used on client, - * MBEDTLS_ERR_SSL_ALLOC_FAILED if out of memory. - */ -int mbedtls_ssl_set_client_transport_id(mbedtls_ssl_context *ssl, - const unsigned char *info, - size_t ilen); - -#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) -/** - * \brief Enable or disable anti-replay protection for DTLS. - * (DTLS only, no effect on TLS.) - * Default: enabled. - * - * \param conf SSL configuration - * \param mode MBEDTLS_SSL_ANTI_REPLAY_ENABLED or MBEDTLS_SSL_ANTI_REPLAY_DISABLED. - * - * \warning Disabling this is a security risk unless the application - * protocol handles duplicated packets in a safe way. You - * should not disable this without careful consideration. - * However, if your application already detects duplicated - * packets and needs information about them to adjust its - * transmission strategy, then you'll want to disable this. - */ -void mbedtls_ssl_conf_dtls_anti_replay(mbedtls_ssl_config *conf, char mode); -#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ - -/** - * \brief Set a limit on the number of records with a bad MAC - * before terminating the connection. - * (DTLS only, no effect on TLS.) - * Default: 0 (disabled). - * - * \param conf SSL configuration - * \param limit Limit, or 0 to disable. - * - * \note If the limit is N, then the connection is terminated when - * the Nth non-authentic record is seen. - * - * \note Records with an invalid header are not counted, only the - * ones going through the authentication-decryption phase. - * - * \note This is a security trade-off related to the fact that it's - * often relatively easy for an active attacker to inject UDP - * datagrams. On one hand, setting a low limit here makes it - * easier for such an attacker to forcibly terminated a - * connection. On the other hand, a high limit or no limit - * might make us waste resources checking authentication on - * many bogus packets. - */ -void mbedtls_ssl_conf_dtls_badmac_limit(mbedtls_ssl_config *conf, unsigned limit); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - -/** - * \brief Allow or disallow packing of multiple handshake records - * within a single datagram. - * - * \param ssl The SSL context to configure. - * \param allow_packing This determines whether datagram packing may - * be used or not. A value of \c 0 means that every - * record will be sent in a separate datagram; a - * value of \c 1 means that, if space permits, - * multiple handshake messages (including CCS) belonging to - * a single flight may be packed within a single datagram. - * - * \note This is enabled by default and should only be disabled - * for test purposes, or if datagram packing causes - * interoperability issues with peers that don't support it. - * - * \note Allowing datagram packing reduces the network load since - * there's less overhead if multiple messages share the same - * datagram. Also, it increases the handshake efficiency - * since messages belonging to a single datagram will not - * be reordered in transit, and so future message buffering - * or flight retransmission (if no buffering is used) as - * means to deal with reordering are needed less frequently. - * - * \note Application records are not affected by this option and - * are currently always sent in separate datagrams. - * - */ -void mbedtls_ssl_set_datagram_packing(mbedtls_ssl_context *ssl, - unsigned allow_packing); - -/** - * \brief Set retransmit timeout values for the DTLS handshake. - * (DTLS only, no effect on TLS.) - * - * \param conf SSL configuration - * \param min Initial timeout value in milliseconds. - * Default: 1000 (1 second). - * \param max Maximum timeout value in milliseconds. - * Default: 60000 (60 seconds). - * - * \note Default values are from RFC 6347 section 4.2.4.1. - * - * \note The 'min' value should typically be slightly above the - * expected round-trip time to your peer, plus whatever time - * it takes for the peer to process the message. For example, - * if your RTT is about 600ms and you peer needs up to 1s to - * do the cryptographic operations in the handshake, then you - * should set 'min' slightly above 1600. Lower values of 'min' - * might cause spurious resends which waste network resources, - * while larger value of 'min' will increase overall latency - * on unreliable network links. - * - * \note The more unreliable your network connection is, the larger - * your max / min ratio needs to be in order to achieve - * reliable handshakes. - * - * \note Messages are retransmitted up to log2(ceil(max/min)) times. - * For example, if min = 1s and max = 5s, the retransmit plan - * goes: send ... 1s -> resend ... 2s -> resend ... 4s -> - * resend ... 5s -> give up and return a timeout error. - */ -void mbedtls_ssl_conf_handshake_timeout(mbedtls_ssl_config *conf, uint32_t min, uint32_t max); -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Set the session cache callbacks (server-side only) - * If not set, no session resuming is done (except if session - * tickets are enabled too). - * - * The session cache has the responsibility to check for stale - * entries based on timeout. See RFC 5246 for recommendations. - * - * Warning: session.peer_cert is cleared by the SSL/TLS layer on - * connection shutdown, so do not cache the pointer! Either set - * it to NULL or make a full copy of the certificate. - * - * The get callback is called once during the initial handshake - * to enable session resuming. The get function has the - * following parameters: (void *parameter, mbedtls_ssl_session *session) - * If a valid entry is found, it should fill the master of - * the session object with the cached values and return 0, - * return 1 otherwise. Optionally peer_cert can be set as well - * if it is properly present in cache entry. - * - * The set callback is called once during the initial handshake - * to enable session resuming after the entire handshake has - * been finished. The set function has the following parameters: - * (void *parameter, const mbedtls_ssl_session *session). The function - * should create a cache entry for future retrieval based on - * the data in the session structure and should keep in mind - * that the mbedtls_ssl_session object presented (and all its referenced - * data) is cleared by the SSL/TLS layer when the connection is - * terminated. It is recommended to add metadata to determine if - * an entry is still valid in the future. Return 0 if - * successfully cached, return 1 otherwise. - * - * \param conf SSL configuration - * \param p_cache parameter (context) for both callbacks - * \param f_get_cache session get callback - * \param f_set_cache session set callback - */ -void mbedtls_ssl_conf_session_cache(mbedtls_ssl_config *conf, - void *p_cache, - mbedtls_ssl_cache_get_t *f_get_cache, - mbedtls_ssl_cache_set_t *f_set_cache); -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_CLI_C) -/** - * \brief Load a session for session resumption. - * - * Sessions loaded through this call will be considered - * for session resumption in the next handshake. - * - * \note Even if this call succeeds, it is not guaranteed that - * the next handshake will indeed be shortened through the - * use of session resumption: The server is always free - * to reject any attempt for resumption and fall back to - * a full handshake. - * - * \note This function can handle a variety of mechanisms for session - * resumption: For TLS 1.2, both session ID-based resumption and - * ticket-based resumption will be considered. For TLS 1.3, - * once implemented, sessions equate to tickets, and loading - * one or more sessions via this call will lead to their - * corresponding tickets being advertised as resumption PSKs - * by the client. - * - * \note Calling this function multiple times will only be useful - * once TLS 1.3 is supported. For TLS 1.2 connections, this - * function should be called at most once. - * - * \param ssl The SSL context representing the connection which should - * be attempted to be setup using session resumption. This - * must be initialized via mbedtls_ssl_init() and bound to - * an SSL configuration via mbedtls_ssl_setup(), but - * the handshake must not yet have been started. - * \param session The session to be considered for session resumption. - * This must be a session previously exported via - * mbedtls_ssl_get_session(), and potentially serialized and - * deserialized through mbedtls_ssl_session_save() and - * mbedtls_ssl_session_load() in the meantime. - * - * \return \c 0 if successful. - * \return \c MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if the session - * could not be loaded because of an implementation limitation. - * This error is non-fatal, and has no observable effect on - * the SSL context or the session that was attempted to be loaded. - * \return Another negative error code on other kinds of failure. - * - * \sa mbedtls_ssl_get_session() - * \sa mbedtls_ssl_session_load() - */ -int mbedtls_ssl_set_session(mbedtls_ssl_context *ssl, const mbedtls_ssl_session *session); -#endif /* MBEDTLS_SSL_CLI_C */ - -/** - * \brief Load serialized session data into a session structure. - * On client, this can be used for loading saved sessions - * before resuming them with mbedtls_ssl_set_session(). - * On server, this can be used for alternative implementations - * of session cache or session tickets. - * - * \warning If a peer certificate chain is associated with the session, - * the serialized state will only contain the peer's - * end-entity certificate and the result of the chain - * verification (unless verification was disabled), but not - * the rest of the chain. - * - * \see mbedtls_ssl_session_save() - * \see mbedtls_ssl_set_session() - * - * \param session The session structure to be populated. It must have been - * initialised with mbedtls_ssl_session_init() but not - * populated yet. - * \param buf The buffer holding the serialized session data. It must be a - * readable buffer of at least \p len bytes. - * \param len The size of the serialized data in bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed. - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if input data is invalid. - * \return #MBEDTLS_ERR_SSL_VERSION_MISMATCH if the serialized data - * was generated in a different version or configuration of - * Mbed TLS. - * \return Another negative value for other kinds of errors (for - * example, unsupported features in the embedded certificate). - */ -int mbedtls_ssl_session_load(mbedtls_ssl_session *session, - const unsigned char *buf, - size_t len); - -/** - * \brief Save session structure as serialized data in a buffer. - * On client, this can be used for saving session data, - * potentially in non-volatile storage, for resuming later. - * On server, this can be used for alternative implementations - * of session cache or session tickets. - * - * \see mbedtls_ssl_session_load() - * - * \param session The session structure to be saved. - * \param buf The buffer to write the serialized data to. It must be a - * writeable buffer of at least \p buf_len bytes, or may be \c - * NULL if \p buf_len is \c 0. - * \param buf_len The number of bytes available for writing in \p buf. - * \param olen The size in bytes of the data that has been or would have - * been written. It must point to a valid \c size_t. - * - * \note \p olen is updated to the correct value regardless of - * whether \p buf_len was large enough. This makes it possible - * to determine the necessary size by calling this function - * with \p buf set to \c NULL and \p buf_len to \c 0. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL if \p buf is too small. - */ -int mbedtls_ssl_session_save(const mbedtls_ssl_session *session, - unsigned char *buf, - size_t buf_len, - size_t *olen); - -/** - * \brief Set the list of allowed ciphersuites and the preference - * order. First in the list has the highest preference. - * - * For TLS 1.2, the notion of ciphersuite determines both - * the key exchange mechanism and the suite of symmetric - * algorithms to be used during and after the handshake. - * - * For TLS 1.3 (in development), the notion of ciphersuite - * only determines the suite of symmetric algorithms to be - * used during and after the handshake, while key exchange - * mechanisms are configured separately. - * - * In Mbed TLS, ciphersuites for both TLS 1.2 and TLS 1.3 - * are configured via this function. For users of TLS 1.3, - * there will be separate API for the configuration of key - * exchange mechanisms. - * - * The list of ciphersuites passed to this function may - * contain a mixture of TLS 1.2 and TLS 1.3 ciphersuite - * identifiers. This is useful if negotiation of TLS 1.3 - * should be attempted, but a fallback to TLS 1.2 would - * be tolerated. - * - * \note By default, the server chooses its preferred - * ciphersuite among those that the client supports. If - * mbedtls_ssl_conf_preference_order() is called to prefer - * the client's preferences, the server instead chooses - * the client's preferred ciphersuite among those that - * the server supports. - * - * \warning The ciphersuites array \p ciphersuites is not copied. - * It must remain valid for the lifetime of the SSL - * configuration \p conf. - * - * \param conf The SSL configuration to modify. - * \param ciphersuites A 0-terminated list of IANA identifiers of supported - * ciphersuites, accessible through \c MBEDTLS_TLS_XXX - * and \c MBEDTLS_TLS1_3_XXX macros defined in - * ssl_ciphersuites.h. - */ -void mbedtls_ssl_conf_ciphersuites(mbedtls_ssl_config *conf, - const int *ciphersuites); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) -/** - * \brief Set the supported key exchange modes for TLS 1.3 connections. - * - * In contrast to TLS 1.2, the ciphersuite concept in TLS 1.3 does not - * include the choice of key exchange mechanism. It is therefore not - * covered by the API mbedtls_ssl_conf_ciphersuites(). See the - * documentation of mbedtls_ssl_conf_ciphersuites() for more - * information on the ciphersuite concept in TLS 1.2 and TLS 1.3. - * - * The present function is specific to TLS 1.3 and allows users to - * configure the set of supported key exchange mechanisms in TLS 1.3. - * - * \param conf The SSL configuration the change should apply to. - * \param kex_modes A bitwise combination of one or more of the following: - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK - * This flag enables pure-PSK key exchanges. - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL - * This flag enables combined PSK-ephemeral key exchanges. - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL - * This flag enables pure-ephemeral key exchanges. - * For convenience, the following pre-defined macros are - * available for combinations of the above: - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_ALL - * Includes all of pure-PSK, PSK-ephemeral and pure-ephemeral. - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL - * Includes both pure-PSK and combined PSK-ephemeral - * key exchanges, but excludes pure-ephemeral key exchanges. - * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL - * Includes both pure-ephemeral and combined PSK-ephemeral - * key exchanges. - * - * \note If a PSK-based key exchange mode shall be supported, applications - * must also use the APIs mbedtls_ssl_conf_psk() or - * mbedtls_ssl_conf_psk_cb() or mbedtls_ssl_conf_psk_opaque() - * to configure the PSKs to be used. - * - * \note If a pure-ephemeral key exchange mode shall be supported, - * server-side applications must also provide a certificate via - * mbedtls_ssl_conf_own_cert(). - * - */ - -void mbedtls_ssl_conf_tls13_key_exchange_modes(mbedtls_ssl_config *conf, - const int kex_modes); -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -#define MBEDTLS_SSL_UNEXPECTED_CID_IGNORE 0 -#define MBEDTLS_SSL_UNEXPECTED_CID_FAIL 1 -/** - * \brief Specify the length of Connection IDs for incoming - * encrypted DTLS records, as well as the behaviour - * on unexpected CIDs. - * - * By default, the CID length is set to \c 0, - * and unexpected CIDs are silently ignored. - * - * \param conf The SSL configuration to modify. - * \param len The length in Bytes of the CID fields in encrypted - * DTLS records using the CID mechanism. This must - * not be larger than #MBEDTLS_SSL_CID_OUT_LEN_MAX. - * \param ignore_other_cids This determines the stack's behaviour when - * receiving a record with an unexpected CID. - * Possible values are: - * - #MBEDTLS_SSL_UNEXPECTED_CID_IGNORE - * In this case, the record is silently ignored. - * - #MBEDTLS_SSL_UNEXPECTED_CID_FAIL - * In this case, the stack fails with the specific - * error code #MBEDTLS_ERR_SSL_UNEXPECTED_CID. - * - * \note The CID specification allows implementations to either - * use a common length for all incoming connection IDs or - * allow variable-length incoming IDs. Mbed TLS currently - * requires a common length for all connections sharing the - * same SSL configuration; this allows simpler parsing of - * record headers. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if \p len - * is too large. - */ -int mbedtls_ssl_conf_cid(mbedtls_ssl_config *conf, size_t len, - int ignore_other_cids); -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Set the X.509 security profile used for verification - * - * \note The restrictions are enforced for all certificates in the - * chain. However, signatures in the handshake are not covered - * by this setting but by \b mbedtls_ssl_conf_sig_hashes(). - * - * \param conf SSL configuration - * \param profile Profile to use - */ -void mbedtls_ssl_conf_cert_profile(mbedtls_ssl_config *conf, - const mbedtls_x509_crt_profile *profile); - -/** - * \brief Set the data required to verify peer certificate - * - * \note See \c mbedtls_x509_crt_verify() for notes regarding the - * parameters ca_chain (maps to trust_ca for that function) - * and ca_crl. - * - * \param conf SSL configuration - * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs) - * \param ca_crl trusted CA CRLs - */ -void mbedtls_ssl_conf_ca_chain(mbedtls_ssl_config *conf, - mbedtls_x509_crt *ca_chain, - mbedtls_x509_crl *ca_crl); - -#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) -/** - * \brief Set DN hints sent to client in CertificateRequest message - * - * \note If not set, subject distinguished names (DNs) are taken - * from \c mbedtls_ssl_conf_ca_chain() - * or \c mbedtls_ssl_set_hs_ca_chain()) - * - * \param conf SSL configuration - * \param crt crt chain whose subject DNs are issuer DNs of client certs - * from which the client should select client peer certificate. - */ -static inline -void mbedtls_ssl_conf_dn_hints(mbedtls_ssl_config *conf, - const mbedtls_x509_crt *crt) -{ - conf->MBEDTLS_PRIVATE(dn_hints) = crt; -} -#endif /* MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED */ - -#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) -/** - * \brief Set the trusted certificate callback. - * - * This API allows to register the set of trusted certificates - * through a callback, instead of a linked list as configured - * by mbedtls_ssl_conf_ca_chain(). - * - * This is useful for example in contexts where a large number - * of CAs are used, and the inefficiency of maintaining them - * in a linked list cannot be tolerated. It is also useful when - * the set of trusted CAs needs to be modified frequently. - * - * See the documentation of `mbedtls_x509_crt_ca_cb_t` for - * more information. - * - * \param conf The SSL configuration to register the callback with. - * \param f_ca_cb The trusted certificate callback to use when verifying - * certificate chains. - * \param p_ca_cb The context to be passed to \p f_ca_cb (for example, - * a reference to a trusted CA database). - * - * \note This API is incompatible with mbedtls_ssl_conf_ca_chain(): - * Any call to this function overwrites the values set through - * earlier calls to mbedtls_ssl_conf_ca_chain() or - * mbedtls_ssl_conf_ca_cb(). - * - * \note This API is incompatible with CA indication in - * CertificateRequest messages: A server-side SSL context which - * is bound to an SSL configuration that uses a CA callback - * configured via mbedtls_ssl_conf_ca_cb(), and which requires - * client authentication, will send an empty CA list in the - * corresponding CertificateRequest message. - * - * \note This API is incompatible with mbedtls_ssl_set_hs_ca_chain(): - * If an SSL context is bound to an SSL configuration which uses - * CA callbacks configured via mbedtls_ssl_conf_ca_cb(), then - * calls to mbedtls_ssl_set_hs_ca_chain() have no effect. - * - * \note The use of this API disables the use of restartable ECC - * during X.509 CRT signature verification (but doesn't affect - * other uses). - * - * \warning This API is incompatible with the use of CRLs. Any call to - * mbedtls_ssl_conf_ca_cb() unsets CRLs configured through - * earlier calls to mbedtls_ssl_conf_ca_chain(). - * - * \warning In multi-threaded environments, the callback \p f_ca_cb - * must be thread-safe, and it is the user's responsibility - * to guarantee this (for example through a mutex - * contained in the callback context pointed to by \p p_ca_cb). - */ -void mbedtls_ssl_conf_ca_cb(mbedtls_ssl_config *conf, - mbedtls_x509_crt_ca_cb_t f_ca_cb, - void *p_ca_cb); -#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ - -/** - * \brief Set own certificate chain and private key - * - * \note own_cert should contain in order from the bottom up your - * certificate chain. The top certificate (self-signed) - * can be omitted. - * - * \note On server, this function can be called multiple times to - * provision more than one cert/key pair (eg one ECDSA, one - * RSA with SHA-256, one RSA with SHA-1). An adequate - * certificate will be selected according to the client's - * advertised capabilities. In case multiple certificates are - * adequate, preference is given to the one set by the first - * call to this function, then second, etc. - * - * \note On client, only the first call has any effect. That is, - * only one client certificate can be provisioned. The - * server's preferences in its CertificateRequest message will - * be ignored and our only cert will be sent regardless of - * whether it matches those preferences - the server can then - * decide what it wants to do with it. - * - * \note The provided \p pk_key needs to match the public key in the - * first certificate in \p own_cert, or all handshakes using - * that certificate will fail. It is your responsibility - * to ensure that; this function will not perform any check. - * You may use mbedtls_pk_check_pair() in order to perform - * this check yourself, but be aware that this function can - * be computationally expensive on some key types. - * - * \param conf SSL configuration - * \param own_cert own public certificate chain - * \param pk_key own private key - * - * \return 0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED - */ -int mbedtls_ssl_conf_own_cert(mbedtls_ssl_config *conf, - mbedtls_x509_crt *own_cert, - mbedtls_pk_context *pk_key); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) -/** - * \brief Configure pre-shared keys (PSKs) and their - * identities to be used in PSK-based ciphersuites. - * - * Only one PSK can be registered, through either - * mbedtls_ssl_conf_psk() or mbedtls_ssl_conf_psk_opaque(). - * If you attempt to register more than one PSK, this function - * fails, though this may change in future versions, which - * may add support for multiple PSKs. - * - * \note This is mainly useful for clients. Servers will usually - * want to use \c mbedtls_ssl_conf_psk_cb() instead. - * - * \note A PSK set by \c mbedtls_ssl_set_hs_psk() in the PSK callback - * takes precedence over a PSK configured by this function. - * - * \param conf The SSL configuration to register the PSK with. - * \param psk The pointer to the pre-shared key to use. - * \param psk_len The length of the pre-shared key in bytes. - * \param psk_identity The pointer to the pre-shared key identity. - * \param psk_identity_len The length of the pre-shared key identity - * in bytes. - * - * \note The PSK and its identity are copied internally and - * hence need not be preserved by the caller for the lifetime - * of the SSL configuration. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no more PSKs - * can be configured. In this case, the old PSK(s) remain intact. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ssl_conf_psk(mbedtls_ssl_config *conf, - const unsigned char *psk, size_t psk_len, - const unsigned char *psk_identity, size_t psk_identity_len); - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * \brief Configure one or more opaque pre-shared keys (PSKs) and - * their identities to be used in PSK-based ciphersuites. - * - * Only one PSK can be registered, through either - * mbedtls_ssl_conf_psk() or mbedtls_ssl_conf_psk_opaque(). - * If you attempt to register more than one PSK, this function - * fails, though this may change in future versions, which - * may add support for multiple PSKs. - * - * \note This is mainly useful for clients. Servers will usually - * want to use \c mbedtls_ssl_conf_psk_cb() instead. - * - * \note An opaque PSK set by \c mbedtls_ssl_set_hs_psk_opaque() in - * the PSK callback takes precedence over an opaque PSK - * configured by this function. - * - * \param conf The SSL configuration to register the PSK with. - * \param psk The identifier of the key slot holding the PSK. - * Until \p conf is destroyed or this function is successfully - * called again, the key slot \p psk must be populated with a - * key of type PSA_ALG_CATEGORY_KEY_DERIVATION whose policy - * allows its use for the key derivation algorithm applied - * in the handshake. - * \param psk_identity The pointer to the pre-shared key identity. - * \param psk_identity_len The length of the pre-shared key identity - * in bytes. - * - * \note The PSK identity hint is copied internally and hence need - * not be preserved by the caller for the lifetime of the - * SSL configuration. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no more PSKs - * can be configured. In this case, the old PSK(s) remain intact. - * \return Another negative error code on other kinds of failure. - */ -int mbedtls_ssl_conf_psk_opaque(mbedtls_ssl_config *conf, - mbedtls_svc_key_id_t psk, - const unsigned char *psk_identity, - size_t psk_identity_len); -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/** - * \brief Set the pre-shared Key (PSK) for the current handshake. - * - * \note This should only be called inside the PSK callback, - * i.e. the function passed to \c mbedtls_ssl_conf_psk_cb(). - * - * \note A PSK set by this function takes precedence over a PSK - * configured by \c mbedtls_ssl_conf_psk(). - * - * \param ssl The SSL context to configure a PSK for. - * \param psk The pointer to the pre-shared key. - * \param psk_len The length of the pre-shared key in bytes. - * - * \return \c 0 if successful. - * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. - */ -int mbedtls_ssl_set_hs_psk(mbedtls_ssl_context *ssl, - const unsigned char *psk, size_t psk_len); - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * \brief Set an opaque pre-shared Key (PSK) for the current handshake. - * - * \note This should only be called inside the PSK callback, - * i.e. the function passed to \c mbedtls_ssl_conf_psk_cb(). - * - * \note An opaque PSK set by this function takes precedence over an - * opaque PSK configured by \c mbedtls_ssl_conf_psk_opaque(). - * - * \param ssl The SSL context to configure a PSK for. - * \param psk The identifier of the key slot holding the PSK. - * For the duration of the current handshake, the key slot - * must be populated with a key of type - * PSA_ALG_CATEGORY_KEY_DERIVATION whose policy allows its - * use for the key derivation algorithm - * applied in the handshake. - * - * \return \c 0 if successful. - * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. - */ -int mbedtls_ssl_set_hs_psk_opaque(mbedtls_ssl_context *ssl, - mbedtls_svc_key_id_t psk); -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Set the PSK callback (server-side only). - * - * If set, the PSK callback is called for each - * handshake where a PSK-based ciphersuite was negotiated. - * The caller provides the identity received and wants to - * receive the actual PSK data and length. - * - * The callback has the following parameters: - * - \c void*: The opaque pointer \p p_psk. - * - \c mbedtls_ssl_context*: The SSL context to which - * the operation applies. - * - \c const unsigned char*: The PSK identity - * selected by the client. - * - \c size_t: The length of the PSK identity - * selected by the client. - * - * If a valid PSK identity is found, the callback should use - * \c mbedtls_ssl_set_hs_psk() or - * \c mbedtls_ssl_set_hs_psk_opaque() - * on the SSL context to set the correct PSK and return \c 0. - * Any other return value will result in a denied PSK identity. - * - * \note A dynamic PSK (i.e. set by the PSK callback) takes - * precedence over a static PSK (i.e. set by - * \c mbedtls_ssl_conf_psk() or - * \c mbedtls_ssl_conf_psk_opaque()). - * This means that if you set a PSK callback using this - * function, you don't need to set a PSK using - * \c mbedtls_ssl_conf_psk() or - * \c mbedtls_ssl_conf_psk_opaque()). - * - * \param conf The SSL configuration to register the callback with. - * \param f_psk The callback for selecting and setting the PSK based - * in the PSK identity chosen by the client. - * \param p_psk A pointer to an opaque structure to be passed to - * the callback, for example a PSK store. - */ -void mbedtls_ssl_conf_psk_cb(mbedtls_ssl_config *conf, - int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *, - size_t), - void *p_psk); -#endif /* MBEDTLS_SSL_SRV_C */ -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ - -#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Set the Diffie-Hellman public P and G values - * from big-endian binary presentations. - * (Default values: MBEDTLS_DHM_RFC3526_MODP_2048_[PG]_BIN) - * - * \param conf SSL configuration - * \param dhm_P Diffie-Hellman-Merkle modulus in big-endian binary form - * \param P_len Length of DHM modulus - * \param dhm_G Diffie-Hellman-Merkle generator in big-endian binary form - * \param G_len Length of DHM generator - * - * \return 0 if successful - */ -int mbedtls_ssl_conf_dh_param_bin(mbedtls_ssl_config *conf, - const unsigned char *dhm_P, size_t P_len, - const unsigned char *dhm_G, size_t G_len); - -/** - * \brief Set the Diffie-Hellman public P and G values, - * read from existing context (server-side only) - * - * \param conf SSL configuration - * \param dhm_ctx Diffie-Hellman-Merkle context - * - * \return 0 if successful - */ -int mbedtls_ssl_conf_dh_param_ctx(mbedtls_ssl_config *conf, mbedtls_dhm_context *dhm_ctx); -#endif /* MBEDTLS_DHM_C && defined(MBEDTLS_SSL_SRV_C) */ - -#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C) -/** - * \brief Set the minimum length for Diffie-Hellman parameters. - * (Client-side only.) - * (Default: 1024 bits.) - * - * \param conf SSL configuration - * \param bitlen Minimum bit length of the DHM prime - */ -void mbedtls_ssl_conf_dhm_min_bitlen(mbedtls_ssl_config *conf, - unsigned int bitlen); -#endif /* MBEDTLS_DHM_C && MBEDTLS_SSL_CLI_C */ - -#if defined(MBEDTLS_ECP_C) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Set the allowed curves in order of preference. - * - * On server: this only affects selection of the ECDHE curve; - * the curves used for ECDH and ECDSA are determined by the - * list of available certificates instead. - * - * On client: this affects the list of curves offered for any - * use. The server can override our preference order. - * - * Both sides: limits the set of curves accepted for use in - * ECDHE and in the peer's end-entity certificate. - * - * \deprecated Superseded by mbedtls_ssl_conf_groups(). - * - * \note This has no influence on which curves are allowed inside the - * certificate chains, see \c mbedtls_ssl_conf_cert_profile() - * for that. For the end-entity certificate however, the key - * will be accepted only if it is allowed both by this list - * and by the cert profile. - * - * \note This list should be ordered by decreasing preference - * (preferred curve first). - * - * \note The default list is the same set of curves that - * #mbedtls_x509_crt_profile_default allows, plus - * ECDHE-only curves selected according to the same criteria. - * The order favors curves with the lowest resource usage. - * - * \note New minor versions of Mbed TLS may extend this list, - * for example if new curves are added to the library. - * New minor versions of Mbed TLS will not remove items - * from this list unless serious security concerns require it. - * New minor versions of Mbed TLS may change the order in - * keeping with the general principle of favoring the lowest - * resource usage. - * - * \param conf SSL configuration - * \param curves Ordered list of allowed curves, - * terminated by MBEDTLS_ECP_DP_NONE. - */ -void MBEDTLS_DEPRECATED mbedtls_ssl_conf_curves(mbedtls_ssl_config *conf, - const mbedtls_ecp_group_id *curves); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ -#endif /* MBEDTLS_ECP_C */ - -/** - * \brief Set the allowed groups in order of preference. - * - * On server: This only affects the choice of key agreement mechanism - * - * On client: this affects the list of groups offered for any - * use. The server can override our preference order. - * - * Both sides: limits the set of groups accepted for use in - * key sharing. - * - * \note This function replaces the deprecated mbedtls_ssl_conf_curves(), - * which only allows ECP curves to be configured. - * - * \note The most recent invocation of either mbedtls_ssl_conf_curves() - * or mbedtls_ssl_conf_groups() nullifies all previous invocations - * of both. - * - * \note This list should be ordered by decreasing preference - * (preferred group first). - * - * \note When this function is not called, a default list is used, - * consisting of all supported curves at 255 bits and above, - * and all supported finite fields at 2048 bits and above. - * The order favors groups with the lowest resource usage. - * - * \note New minor versions of Mbed TLS will not remove items - * from the default list unless serious security concerns require it. - * New minor versions of Mbed TLS may change the order in - * keeping with the general principle of favoring the lowest - * resource usage. - * - * \param conf SSL configuration - * \param groups List of allowed groups ordered by preference, terminated by 0. - * Must contain valid IANA NamedGroup IDs (provided via either an integer - * or using MBEDTLS_TLS1_3_NAMED_GROUP_XXX macros). - */ -void mbedtls_ssl_conf_groups(mbedtls_ssl_config *conf, - const uint16_t *groups); - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) && defined(MBEDTLS_SSL_PROTO_TLS1_2) -/** - * \brief Set the allowed hashes for signatures during the handshake. - * - * \note This only affects which hashes are offered and can be used - * for signatures during the handshake. Hashes for message - * authentication and the TLS PRF are controlled by the - * ciphersuite, see \c mbedtls_ssl_conf_ciphersuites(). Hashes - * used for certificate signature are controlled by the - * verification profile, see \c mbedtls_ssl_conf_cert_profile(). - * - * \note This list should be ordered by decreasing preference - * (preferred hash first). - * - * \note By default, all supported hashes whose length is at least - * 256 bits are allowed. This is the same set as the default - * for certificate verification - * (#mbedtls_x509_crt_profile_default). - * The preference order is currently unspecified and may - * change in future versions. - * - * \note New minor versions of Mbed TLS may extend this list, - * for example if new curves are added to the library. - * New minor versions of Mbed TLS will not remove items - * from this list unless serious security concerns require it. - * - * \param conf SSL configuration - * \param hashes Ordered list of allowed signature hashes, - * terminated by \c MBEDTLS_MD_NONE. - */ -void MBEDTLS_DEPRECATED mbedtls_ssl_conf_sig_hashes(mbedtls_ssl_config *conf, - const int *hashes); -#endif /* !MBEDTLS_DEPRECATED_REMOVED && MBEDTLS_SSL_PROTO_TLS1_2 */ - -/** - * \brief Configure allowed signature algorithms for use in TLS 1.3 - * - * \param conf The SSL configuration to use. - * \param sig_algs List of allowed IANA values for TLS 1.3 signature algorithms, - * terminated by \c MBEDTLS_TLS1_3_SIG_NONE. The list must remain - * available throughout the lifetime of the conf object. Supported - * values are available as \c MBEDTLS_TLS1_3_SIG_XXXX - */ -void mbedtls_ssl_conf_sig_algs(mbedtls_ssl_config *conf, - const uint16_t *sig_algs); -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Set or reset the hostname to check against the received - * server certificate. It sets the ServerName TLS extension, - * too, if that extension is enabled. (client-side only) - * - * \param ssl SSL context - * \param hostname the server hostname, may be NULL to clear hostname - - * \note Maximum hostname length MBEDTLS_SSL_MAX_HOST_NAME_LEN. - * - * \return 0 if successful, MBEDTLS_ERR_SSL_ALLOC_FAILED on - * allocation failure, MBEDTLS_ERR_SSL_BAD_INPUT_DATA on - * too long input hostname. - * - * Hostname set to the one provided on success (cleared - * when NULL). On allocation failure hostname is cleared. - * On too long input failure, old hostname is unchanged. - */ -int mbedtls_ssl_set_hostname(mbedtls_ssl_context *ssl, const char *hostname); - -/** - * \brief Get the hostname that checked against the received - * server certificate. It is used to set the ServerName - * TLS extension, too, if that extension is enabled. - * (client-side only) - * - * \param ssl SSL context - * - * \return const pointer to the hostname value - */ -static inline const char *mbedtls_ssl_get_hostname(mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(hostname); -} -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) -/** - * \brief Retrieve SNI extension value for the current handshake. - * Available in \c f_cert_cb of \c mbedtls_ssl_conf_cert_cb(), - * this is the same value passed to \c f_sni callback of - * \c mbedtls_ssl_conf_sni() and may be used instead of - * \c mbedtls_ssl_conf_sni(). - * - * \param ssl SSL context - * \param name_len pointer into which to store length of returned value. - * 0 if SNI extension is not present or not yet processed. - * - * \return const pointer to SNI extension value. - * - value is valid only when called in \c f_cert_cb - * registered with \c mbedtls_ssl_conf_cert_cb(). - * - value is NULL if SNI extension is not present. - * - value is not '\0'-terminated. Use \c name_len for len. - * - value must not be freed. - */ -const unsigned char *mbedtls_ssl_get_hs_sni(mbedtls_ssl_context *ssl, - size_t *name_len); - -/** - * \brief Set own certificate and key for the current handshake - * - * \note Same as \c mbedtls_ssl_conf_own_cert() but for use within - * the SNI callback or the certificate selection callback. - * - * \note Passing null \c own_cert clears the certificate list for - * the current handshake. - * - * \param ssl SSL context - * \param own_cert own public certificate chain - * \param pk_key own private key - * - * \return 0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED - */ -int mbedtls_ssl_set_hs_own_cert(mbedtls_ssl_context *ssl, - mbedtls_x509_crt *own_cert, - mbedtls_pk_context *pk_key); - -/** - * \brief Set the data required to verify peer certificate for the - * current handshake - * - * \note Same as \c mbedtls_ssl_conf_ca_chain() but for use within - * the SNI callback or the certificate selection callback. - * - * \param ssl SSL context - * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs) - * \param ca_crl trusted CA CRLs - */ -void mbedtls_ssl_set_hs_ca_chain(mbedtls_ssl_context *ssl, - mbedtls_x509_crt *ca_chain, - mbedtls_x509_crl *ca_crl); - -#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) -/** - * \brief Set DN hints sent to client in CertificateRequest message - * - * \note Same as \c mbedtls_ssl_conf_dn_hints() but for use within - * the SNI callback or the certificate selection callback. - * - * \param ssl SSL context - * \param crt crt chain whose subject DNs are issuer DNs of client certs - * from which the client should select client peer certificate. - */ -void mbedtls_ssl_set_hs_dn_hints(mbedtls_ssl_context *ssl, - const mbedtls_x509_crt *crt); -#endif /* MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED */ - -/** - * \brief Set authmode for the current handshake. - * - * \note Same as \c mbedtls_ssl_conf_authmode() but for use within - * the SNI callback or the certificate selection callback. - * - * \param ssl SSL context - * \param authmode MBEDTLS_SSL_VERIFY_NONE, MBEDTLS_SSL_VERIFY_OPTIONAL or - * MBEDTLS_SSL_VERIFY_REQUIRED - */ -void mbedtls_ssl_set_hs_authmode(mbedtls_ssl_context *ssl, - int authmode); - -/** - * \brief Set server side ServerName TLS extension callback - * (optional, server-side only). - * - * If set, the ServerName callback is called whenever the - * server receives a ServerName TLS extension from the client - * during a handshake. The ServerName callback has the - * following parameters: (void *parameter, mbedtls_ssl_context *ssl, - * const unsigned char *hostname, size_t len). If a suitable - * certificate is found, the callback must set the - * certificate(s) and key(s) to use with \c - * mbedtls_ssl_set_hs_own_cert() (can be called repeatedly), - * and may optionally adjust the CA and associated CRL with \c - * mbedtls_ssl_set_hs_ca_chain() as well as the client - * authentication mode with \c mbedtls_ssl_set_hs_authmode(), - * then must return 0. If no matching name is found, the - * callback may return non-zero to abort the handshake. - * - * \param conf SSL configuration - * \param f_sni verification function - * \param p_sni verification parameter - */ -void mbedtls_ssl_conf_sni(mbedtls_ssl_config *conf, - int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *, - size_t), - void *p_sni); -#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ - -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) -/** - * \brief Set the EC J-PAKE password for current handshake. - * - * \note An internal copy is made, and destroyed as soon as the - * handshake is completed, or when the SSL context is reset or - * freed. - * - * \note The SSL context needs to be already set up. The right place - * to call this function is between \c mbedtls_ssl_setup() or - * \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake(). - * Password cannot be empty (see RFC 8236). - * - * \param ssl SSL context - * \param pw EC J-PAKE password (pre-shared secret). It cannot be empty - * \param pw_len length of pw in bytes - * - * \return 0 on success, or a negative error code. - */ -int mbedtls_ssl_set_hs_ecjpake_password(mbedtls_ssl_context *ssl, - const unsigned char *pw, - size_t pw_len); - -/** - * \brief Set the EC J-PAKE opaque password for current handshake. - * - * \note The key must remain valid until the handshake is over. - * - * \note The SSL context needs to be already set up. The right place - * to call this function is between \c mbedtls_ssl_setup() or - * \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake(). - * - * \param ssl SSL context - * \param pwd EC J-PAKE opaque password - * - * \return 0 on success, or a negative error code. - */ -int mbedtls_ssl_set_hs_ecjpake_password_opaque(mbedtls_ssl_context *ssl, - mbedtls_svc_key_id_t pwd); -#endif /*MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ - -#if defined(MBEDTLS_SSL_ALPN) -/** - * \brief Set the supported Application Layer Protocols. - * - * \param conf SSL configuration - * \param protos Pointer to a NULL-terminated list of supported protocols, - * in decreasing preference order. The pointer to the list is - * recorded by the library for later reference as required, so - * the lifetime of the table must be at least as long as the - * lifetime of the SSL configuration structure. - * - * \return 0 on success, or MBEDTLS_ERR_SSL_BAD_INPUT_DATA. - */ -int mbedtls_ssl_conf_alpn_protocols(mbedtls_ssl_config *conf, const char **protos); - -/** - * \brief Get the name of the negotiated Application Layer Protocol. - * This function should be called after the handshake is - * completed. - * - * \param ssl SSL context - * - * \return Protocol name, or NULL if no protocol was negotiated. - */ -const char *mbedtls_ssl_get_alpn_protocol(const mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_ALPN */ - -#if defined(MBEDTLS_SSL_DTLS_SRTP) -#if defined(MBEDTLS_DEBUG_C) -static inline const char *mbedtls_ssl_get_srtp_profile_as_string(mbedtls_ssl_srtp_profile profile) -{ - switch (profile) { - case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: - return "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80"; - case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: - return "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32"; - case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: - return "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80"; - case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: - return "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32"; - default: break; - } - return ""; -} -#endif /* MBEDTLS_DEBUG_C */ -/** - * \brief Manage support for mki(master key id) value - * in use_srtp extension. - * MKI is an optional part of SRTP used for key management - * and re-keying. See RFC3711 section 3.1 for details. - * The default value is - * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED. - * - * \param conf The SSL configuration to manage mki support. - * \param support_mki_value Enable or disable mki usage. Values are - * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED - * or #MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED. - */ -void mbedtls_ssl_conf_srtp_mki_value_supported(mbedtls_ssl_config *conf, - int support_mki_value); - -/** - * \brief Set the supported DTLS-SRTP protection profiles. - * - * \param conf SSL configuration - * \param profiles Pointer to a List of MBEDTLS_TLS_SRTP_UNSET terminated - * supported protection profiles - * in decreasing preference order. - * The pointer to the list is recorded by the library - * for later reference as required, so the lifetime - * of the table must be at least as long as the lifetime - * of the SSL configuration structure. - * The list must not hold more than - * MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH elements - * (excluding the terminating MBEDTLS_TLS_SRTP_UNSET). - * - * \return 0 on success - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA when the list of - * protection profiles is incorrect. - */ -int mbedtls_ssl_conf_dtls_srtp_protection_profiles - (mbedtls_ssl_config *conf, - const mbedtls_ssl_srtp_profile *profiles); - -/** - * \brief Set the mki_value for the current DTLS-SRTP session. - * - * \param ssl SSL context to use. - * \param mki_value The MKI value to set. - * \param mki_len The length of the MKI value. - * - * \note This function is relevant on client side only. - * The server discovers the mki value during handshake. - * A mki value set on server side using this function - * is ignored. - * - * \return 0 on success - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA - * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE - */ -int mbedtls_ssl_dtls_srtp_set_mki_value(mbedtls_ssl_context *ssl, - unsigned char *mki_value, - uint16_t mki_len); -/** - * \brief Get the negotiated DTLS-SRTP information: - * Protection profile and MKI value. - * - * \warning This function must be called after the handshake is - * completed. The value returned by this function must - * not be trusted or acted upon before the handshake completes. - * - * \param ssl The SSL context to query. - * \param dtls_srtp_info The negotiated DTLS-SRTP information: - * - Protection profile in use. - * A direct mapping of the iana defined value for protection - * profile on an uint16_t. - http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml - * #MBEDTLS_TLS_SRTP_UNSET if the use of SRTP was not negotiated - * or peer's Hello packet was not parsed yet. - * - mki size and value( if size is > 0 ). - */ -void mbedtls_ssl_get_dtls_srtp_negotiation_result(const mbedtls_ssl_context *ssl, - mbedtls_dtls_srtp_info *dtls_srtp_info); -#endif /* MBEDTLS_SSL_DTLS_SRTP */ - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Set the maximum supported version sent from the client side - * and/or accepted at the server side. - * - * See also the documentation of mbedtls_ssl_conf_min_version(). - * - * \note This ignores ciphersuites from higher versions. - * - * \note This function is deprecated and has been replaced by - * \c mbedtls_ssl_conf_max_tls_version(). - * - * \param conf SSL configuration - * \param major Major version number (#MBEDTLS_SSL_MAJOR_VERSION_3) - * \param minor Minor version number - * (#MBEDTLS_SSL_MINOR_VERSION_3 for (D)TLS 1.2, - * #MBEDTLS_SSL_MINOR_VERSION_4 for TLS 1.3) - */ -void MBEDTLS_DEPRECATED mbedtls_ssl_conf_max_version(mbedtls_ssl_config *conf, int major, - int minor); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -/** - * \brief Set the maximum supported version sent from the client side - * and/or accepted at the server side. - * - * \note After the handshake, you can call - * mbedtls_ssl_get_version_number() to see what version was - * negotiated. - * - * \param conf SSL configuration - * \param tls_version TLS protocol version number (\c mbedtls_ssl_protocol_version) - * (#MBEDTLS_SSL_VERSION_UNKNOWN is not valid) - */ -static inline void mbedtls_ssl_conf_max_tls_version(mbedtls_ssl_config *conf, - mbedtls_ssl_protocol_version tls_version) -{ - conf->MBEDTLS_PRIVATE(max_tls_version) = tls_version; -} - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Set the minimum accepted SSL/TLS protocol version - * - * \note By default, all supported versions are accepted. - * Future versions of the library may disable older - * protocol versions by default if they become deprecated. - * - * \note The following versions are supported (if enabled at - * compile time): - * - (D)TLS 1.2: \p major = #MBEDTLS_SSL_MAJOR_VERSION_3, - * \p minor = #MBEDTLS_SSL_MINOR_VERSION_3 - * - TLS 1.3: \p major = #MBEDTLS_SSL_MAJOR_VERSION_3, - * \p minor = #MBEDTLS_SSL_MINOR_VERSION_4 - * - * Note that the numbers in the constant names are the - * TLS internal protocol numbers, and the minor versions - * differ by one from the human-readable versions! - * - * \note Input outside of the SSL_MAX_XXXXX_VERSION and - * SSL_MIN_XXXXX_VERSION range is ignored. - * - * \note After the handshake, you can call - * mbedtls_ssl_get_version_number() to see what version was - * negotiated. - * - * \note This function is deprecated and has been replaced by - * \c mbedtls_ssl_conf_min_tls_version(). - * - * \param conf SSL configuration - * \param major Major version number (#MBEDTLS_SSL_MAJOR_VERSION_3) - * \param minor Minor version number - * (#MBEDTLS_SSL_MINOR_VERSION_3 for (D)TLS 1.2, - * #MBEDTLS_SSL_MINOR_VERSION_4 for TLS 1.3) - */ -void MBEDTLS_DEPRECATED mbedtls_ssl_conf_min_version(mbedtls_ssl_config *conf, int major, - int minor); -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - -/** - * \brief Set the minimum supported version sent from the client side - * and/or accepted at the server side. - * - * \note After the handshake, you can call - * mbedtls_ssl_get_version_number() to see what version was - * negotiated. - * - * \param conf SSL configuration - * \param tls_version TLS protocol version number (\c mbedtls_ssl_protocol_version) - * (#MBEDTLS_SSL_VERSION_UNKNOWN is not valid) - */ -static inline void mbedtls_ssl_conf_min_tls_version(mbedtls_ssl_config *conf, - mbedtls_ssl_protocol_version tls_version) -{ - conf->MBEDTLS_PRIVATE(min_tls_version) = tls_version; -} - -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) -/** - * \brief Enable or disable Encrypt-then-MAC - * (Default: MBEDTLS_SSL_ETM_ENABLED) - * - * \note This should always be enabled, it is a security - * improvement, and should not cause any interoperability - * issue (used only if the peer supports it too). - * - * \param conf SSL configuration - * \param etm MBEDTLS_SSL_ETM_ENABLED or MBEDTLS_SSL_ETM_DISABLED - */ -void mbedtls_ssl_conf_encrypt_then_mac(mbedtls_ssl_config *conf, char etm); -#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ - -#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) -/** - * \brief Enable or disable Extended Master Secret negotiation. - * (Default: MBEDTLS_SSL_EXTENDED_MS_ENABLED) - * - * \note This should always be enabled, it is a security fix to the - * protocol, and should not cause any interoperability issue - * (used only if the peer supports it too). - * - * \param conf SSL configuration - * \param ems MBEDTLS_SSL_EXTENDED_MS_ENABLED or MBEDTLS_SSL_EXTENDED_MS_DISABLED - */ -void mbedtls_ssl_conf_extended_master_secret(mbedtls_ssl_config *conf, char ems); -#endif /* MBEDTLS_SSL_EXTENDED_MASTER_SECRET */ - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Whether to send a list of acceptable CAs in - * CertificateRequest messages. - * (Default: do send) - * - * \param conf SSL configuration - * \param cert_req_ca_list MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED or - * MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED - */ -void mbedtls_ssl_conf_cert_req_ca_list(mbedtls_ssl_config *conf, - char cert_req_ca_list); -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) -/** - * \brief Set the maximum fragment length to emit and/or negotiate. - * (Typical: the smaller of #MBEDTLS_SSL_IN_CONTENT_LEN and - * #MBEDTLS_SSL_OUT_CONTENT_LEN, usually `2^14` bytes) - * (Server: set maximum fragment length to emit, - * usually negotiated by the client during handshake) - * (Client: set maximum fragment length to emit *and* - * negotiate with the server during handshake) - * (Default: #MBEDTLS_SSL_MAX_FRAG_LEN_NONE) - * - * \note On the client side, the maximum fragment length extension - * *will not* be used, unless the maximum fragment length has - * been set via this function to a value different than - * #MBEDTLS_SSL_MAX_FRAG_LEN_NONE. - * - * \note With TLS, this currently only affects ApplicationData (sent - * with \c mbedtls_ssl_read()), not handshake messages. - * With DTLS, this affects both ApplicationData and handshake. - * - * \note This sets the maximum length for a record's payload, - * excluding record overhead that will be added to it, see - * \c mbedtls_ssl_get_record_expansion(). - * - * \note For DTLS, it is also possible to set a limit for the total - * size of datagrams passed to the transport layer, including - * record overhead, see \c mbedtls_ssl_set_mtu(). - * - * \param conf SSL configuration - * \param mfl_code Code for maximum fragment length (allowed values: - * MBEDTLS_SSL_MAX_FRAG_LEN_512, MBEDTLS_SSL_MAX_FRAG_LEN_1024, - * MBEDTLS_SSL_MAX_FRAG_LEN_2048, MBEDTLS_SSL_MAX_FRAG_LEN_4096) - * - * \return 0 if successful or MBEDTLS_ERR_SSL_BAD_INPUT_DATA - */ -int mbedtls_ssl_conf_max_frag_len(mbedtls_ssl_config *conf, unsigned char mfl_code); -#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Pick the ciphersuites order according to the second parameter - * in the SSL Server module (MBEDTLS_SSL_SRV_C). - * (Default, if never called: MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER) - * - * \param conf SSL configuration - * \param order Server or client (MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER - * or MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_CLIENT) - */ -void mbedtls_ssl_conf_preference_order(mbedtls_ssl_config *conf, int order); -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_CLI_C) -/** - * \brief Enable / Disable session tickets (client only). - * (Default: MBEDTLS_SSL_SESSION_TICKETS_ENABLED.) - * - * \note On server, use \c mbedtls_ssl_conf_session_tickets_cb(). - * - * \param conf SSL configuration - * \param use_tickets Enable or disable (MBEDTLS_SSL_SESSION_TICKETS_ENABLED or - * MBEDTLS_SSL_SESSION_TICKETS_DISABLED) - */ -void mbedtls_ssl_conf_session_tickets(mbedtls_ssl_config *conf, int use_tickets); -#endif /* MBEDTLS_SSL_SESSION_TICKETS && - MBEDTLS_SSL_CLI_C */ - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_SRV_C) && \ - defined(MBEDTLS_SSL_PROTO_TLS1_3) -/** - * \brief Number of NewSessionTicket messages for the server to send - * after handshake completion. - * - * \note The default value is - * \c MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS. - * - * \note In case of a session resumption, this setting only partially apply. - * At most one ticket is sent in that case to just renew the pool of - * tickets of the client. The rationale is to avoid the number of - * tickets on the server to become rapidly out of control when the - * server has the same configuration for all its connection instances. - * - * \param conf SSL configuration - * \param num_tickets Number of NewSessionTicket. - * - */ -void mbedtls_ssl_conf_new_session_tickets(mbedtls_ssl_config *conf, - uint16_t num_tickets); -#endif /* MBEDTLS_SSL_SESSION_TICKETS && - MBEDTLS_SSL_SRV_C && - MBEDTLS_SSL_PROTO_TLS1_3*/ - -#if defined(MBEDTLS_SSL_RENEGOTIATION) -/** - * \brief Enable / Disable renegotiation support for connection when - * initiated by peer - * (Default: MBEDTLS_SSL_RENEGOTIATION_DISABLED) - * - * \warning It is recommended to always disable renegotiation unless you - * know you need it and you know what you're doing. In the - * past, there have been several issues associated with - * renegotiation or a poor understanding of its properties. - * - * \note Server-side, enabling renegotiation also makes the server - * susceptible to a resource DoS by a malicious client. - * - * \param conf SSL configuration - * \param renegotiation Enable or disable (MBEDTLS_SSL_RENEGOTIATION_ENABLED or - * MBEDTLS_SSL_RENEGOTIATION_DISABLED) - */ -void mbedtls_ssl_conf_renegotiation(mbedtls_ssl_config *conf, int renegotiation); -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - -/** - * \brief Prevent or allow legacy renegotiation. - * (Default: MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION) - * - * MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION allows connections to - * be established even if the peer does not support - * secure renegotiation, but does not allow renegotiation - * to take place if not secure. - * (Interoperable and secure option) - * - * MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION allows renegotiations - * with non-upgraded peers. Allowing legacy renegotiation - * makes the connection vulnerable to specific man in the - * middle attacks. (See RFC 5746) - * (Most interoperable and least secure option) - * - * MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE breaks off connections - * if peer does not support secure renegotiation. Results - * in interoperability issues with non-upgraded peers - * that do not support renegotiation altogether. - * (Most secure option, interoperability issues) - * - * \param conf SSL configuration - * \param allow_legacy Prevent or allow (SSL_NO_LEGACY_RENEGOTIATION, - * SSL_ALLOW_LEGACY_RENEGOTIATION or - * MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE) - */ -void mbedtls_ssl_conf_legacy_renegotiation(mbedtls_ssl_config *conf, int allow_legacy); - -#if defined(MBEDTLS_SSL_RENEGOTIATION) -/** - * \brief Enforce renegotiation requests. - * (Default: enforced, max_records = 16) - * - * When we request a renegotiation, the peer can comply or - * ignore the request. This function allows us to decide - * whether to enforce our renegotiation requests by closing - * the connection if the peer doesn't comply. - * - * However, records could already be in transit from the peer - * when the request is emitted. In order to increase - * reliability, we can accept a number of records before the - * expected handshake records. - * - * The optimal value is highly dependent on the specific usage - * scenario. - * - * \note With DTLS and server-initiated renegotiation, the - * HelloRequest is retransmitted every time mbedtls_ssl_read() times - * out or receives Application Data, until: - * - max_records records have beens seen, if it is >= 0, or - * - the number of retransmits that would happen during an - * actual handshake has been reached. - * Please remember the request might be lost a few times - * if you consider setting max_records to a really low value. - * - * \warning On client, the grace period can only happen during - * mbedtls_ssl_read(), as opposed to mbedtls_ssl_write() and mbedtls_ssl_renegotiate() - * which always behave as if max_record was 0. The reason is, - * if we receive application data from the server, we need a - * place to write it, which only happens during mbedtls_ssl_read(). - * - * \param conf SSL configuration - * \param max_records Use MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED if you don't want to - * enforce renegotiation, or a non-negative value to enforce - * it but allow for a grace period of max_records records. - */ -void mbedtls_ssl_conf_renegotiation_enforced(mbedtls_ssl_config *conf, int max_records); - -/** - * \brief Set record counter threshold for periodic renegotiation. - * (Default: 2^48 - 1) - * - * Renegotiation is automatically triggered when a record - * counter (outgoing or incoming) crosses the defined - * threshold. The default value is meant to prevent the - * connection from being closed when the counter is about to - * reached its maximal value (it is not allowed to wrap). - * - * Lower values can be used to enforce policies such as "keys - * must be refreshed every N packets with cipher X". - * - * The renegotiation period can be disabled by setting - * conf->disable_renegotiation to - * MBEDTLS_SSL_RENEGOTIATION_DISABLED. - * - * \note When the configured transport is - * MBEDTLS_SSL_TRANSPORT_DATAGRAM the maximum renegotiation - * period is 2^48 - 1, and for MBEDTLS_SSL_TRANSPORT_STREAM, - * the maximum renegotiation period is 2^64 - 1. - * - * \param conf SSL configuration - * \param period The threshold value: a big-endian 64-bit number. - */ -void mbedtls_ssl_conf_renegotiation_period(mbedtls_ssl_config *conf, - const unsigned char period[8]); -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - -/** - * \brief Check if there is data already read from the - * underlying transport but not yet processed. - * - * \param ssl SSL context - * - * \return 0 if nothing's pending, 1 otherwise. - * - * \note This is different in purpose and behaviour from - * \c mbedtls_ssl_get_bytes_avail in that it considers - * any kind of unprocessed data, not only unread - * application data. If \c mbedtls_ssl_get_bytes - * returns a non-zero value, this function will - * also signal pending data, but the converse does - * not hold. For example, in DTLS there might be - * further records waiting to be processed from - * the current underlying transport's datagram. - * - * \note If this function returns 1 (data pending), this - * does not imply that a subsequent call to - * \c mbedtls_ssl_read will provide any data; - * e.g., the unprocessed data might turn out - * to be an alert or a handshake message. - * - * \note This function is useful in the following situation: - * If the SSL/TLS module successfully returns from an - * operation - e.g. a handshake or an application record - * read - and you're awaiting incoming data next, you - * must not immediately idle on the underlying transport - * to have data ready, but you need to check the value - * of this function first. The reason is that the desired - * data might already be read but not yet processed. - * If, in contrast, a previous call to the SSL/TLS module - * returned MBEDTLS_ERR_SSL_WANT_READ, it is not necessary - * to call this function, as the latter error code entails - * that all internal data has been processed. - * - */ -int mbedtls_ssl_check_pending(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the number of application data bytes - * remaining to be read from the current record. - * - * \param ssl SSL context - * - * \return How many bytes are available in the application - * data record read buffer. - * - * \note When working over a datagram transport, this is - * useful to detect the current datagram's boundary - * in case \c mbedtls_ssl_read has written the maximal - * amount of data fitting into the input buffer. - * - */ -size_t mbedtls_ssl_get_bytes_avail(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the result of the certificate verification - * - * \param ssl The SSL context to use. - * - * \return \c 0 if the certificate verification was successful. - * \return \c -1u if the result is not available. This may happen - * e.g. if the handshake aborts early, or a verification - * callback returned a fatal error. - * \return A bitwise combination of \c MBEDTLS_X509_BADCERT_XXX - * and \c MBEDTLS_X509_BADCRL_XXX failure flags; see x509.h. - */ -uint32_t mbedtls_ssl_get_verify_result(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the id of the current ciphersuite - * - * \param ssl SSL context - * - * \return a ciphersuite id - */ -int mbedtls_ssl_get_ciphersuite_id_from_ssl(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the name of the current ciphersuite - * - * \param ssl SSL context - * - * \return a string containing the ciphersuite name - */ -const char *mbedtls_ssl_get_ciphersuite(const mbedtls_ssl_context *ssl); - - -/** - * \brief Return the (D)TLS protocol version negotiated in the - * given connection. - * - * \note If you call this function too early during the initial - * handshake, before the two sides have agreed on a version, - * this function returns #MBEDTLS_SSL_VERSION_UNKNOWN. - * - * \param ssl The SSL context to query. - * \return The negotiated protocol version. - */ -static inline mbedtls_ssl_protocol_version mbedtls_ssl_get_version_number( - const mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(tls_version); -} - -/** - * \brief Return the current TLS version - * - * \param ssl SSL context - * - * \return a string containing the TLS version - */ -const char *mbedtls_ssl_get_version(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the (maximum) number of bytes added by the record - * layer: header + encryption/MAC overhead (inc. padding) - * - * \param ssl SSL context - * - * \return Current maximum record expansion in bytes - */ -int mbedtls_ssl_get_record_expansion(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the current maximum outgoing record payload in bytes. - * - * \note The logic to determine the maximum outgoing record payload is - * version-specific. It takes into account various factors, such as - * the mbedtls_config.h setting \c MBEDTLS_SSL_OUT_CONTENT_LEN, extensions - * such as the max fragment length or record size limit extension if - * used, and for DTLS the path MTU as configured and current - * record expansion. - * - * \note With DTLS, \c mbedtls_ssl_write() will return an error if - * called with a larger length value. - * With TLS, \c mbedtls_ssl_write() will fragment the input if - * necessary and return the number of bytes written; it is up - * to the caller to call \c mbedtls_ssl_write() again in - * order to send the remaining bytes if any. - * - * \sa mbedtls_ssl_get_max_out_record_payload() - * \sa mbedtls_ssl_get_record_expansion() - * - * \param ssl SSL context - * - * \return Current maximum payload for an outgoing record, - * or a negative error code. - */ -int mbedtls_ssl_get_max_out_record_payload(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the current maximum incoming record payload in bytes. - * - * \note The logic to determine the maximum incoming record payload is - * version-specific. It takes into account various factors, such as - * the mbedtls_config.h setting \c MBEDTLS_SSL_IN_CONTENT_LEN, extensions - * such as the max fragment length extension or record size limit - * extension if used, and the current record expansion. - * - * \sa mbedtls_ssl_set_mtu() - * \sa mbedtls_ssl_get_max_in_record_payload() - * \sa mbedtls_ssl_get_record_expansion() - * - * \param ssl SSL context - * - * \return Current maximum payload for an incoming record, - * or a negative error code. - */ -int mbedtls_ssl_get_max_in_record_payload(const mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * \brief Return the peer certificate from the current connection. - * - * \param ssl The SSL context to use. This must be initialized and setup. - * - * \return The current peer certificate, if available. - * The returned certificate is owned by the SSL context and - * is valid only until the next call to the SSL API. - * \return \c NULL if no peer certificate is available. This might - * be because the chosen ciphersuite doesn't use CRTs - * (PSK-based ciphersuites, for example), or because - * #MBEDTLS_SSL_KEEP_PEER_CERTIFICATE has been disabled, - * allowing the stack to free the peer's CRT to save memory. - * - * \note For one-time inspection of the peer's certificate during - * the handshake, consider registering an X.509 CRT verification - * callback through mbedtls_ssl_conf_verify() instead of calling - * this function. Using mbedtls_ssl_conf_verify() also comes at - * the benefit of allowing you to influence the verification - * process, for example by masking expected and tolerated - * verification failures. - * - * \warning You must not use the pointer returned by this function - * after any further call to the SSL API, including - * mbedtls_ssl_read() and mbedtls_ssl_write(); this is - * because the pointer might change during renegotiation, - * which happens transparently to the user. - * If you want to use the certificate across API calls, - * you must make a copy. - */ -const mbedtls_x509_crt *mbedtls_ssl_get_peer_cert(const mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_CLI_C) -/** - * \brief Export a session in order to resume it later. - * - * \param ssl The SSL context representing the connection for which to - * to export a session structure for later resumption. - * \param session The target structure in which to store the exported session. - * This must have been initialized with mbedtls_ssl_init_session() - * but otherwise be unused. - * - * \note This function can handle a variety of mechanisms for session - * resumption: For TLS 1.2, both session ID-based resumption and - * ticket-based resumption will be considered. For TLS 1.3, - * once implemented, sessions equate to tickets, and calling - * this function multiple times will export the available - * tickets one a time until no further tickets are available, - * in which case MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE will - * be returned. - * - * \note Calling this function multiple times will only be useful - * once TLS 1.3 is supported. For TLS 1.2 connections, this - * function should be called at most once. - * - * \return \c 0 if successful. In this case, \p session can be used for - * session resumption by passing it to mbedtls_ssl_set_session(), - * and serialized for storage via mbedtls_ssl_session_save(). - * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no further session - * is available for export. - * This error is a non-fatal, and has no observable effect on - * the SSL context or the destination session. - * \return Another negative error code on other kinds of failure. - * - * \sa mbedtls_ssl_set_session() - * \sa mbedtls_ssl_session_save() - */ -int mbedtls_ssl_get_session(const mbedtls_ssl_context *ssl, - mbedtls_ssl_session *session); -#endif /* MBEDTLS_SSL_CLI_C */ - -/** - * \brief Perform the SSL handshake - * - * \param ssl SSL context - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE - * if the handshake is incomplete and waiting for data to - * be available for reading from or writing to the underlying - * transport - in this case you must call this function again - * when the underlying transport is ready for the operation. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous - * operation is in progress (see - * mbedtls_ssl_conf_async_private_cb()) - in this case you - * must call this function again when the operation is ready. - * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic - * operation is in progress (see mbedtls_ecp_set_max_ops()) - - * in this case you must call this function again to complete - * the handshake when you're done attending other tasks. - * \return #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED if DTLS is in use - * and the client did not demonstrate reachability yet - in - * this case you must stop using the context (see below). - * \return Another SSL error code - in this case you must stop using - * the context (see below). - * - * \warning If this function returns something other than - * \c 0, - * #MBEDTLS_ERR_SSL_WANT_READ, - * #MBEDTLS_ERR_SSL_WANT_WRITE, - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, - * you must stop using the SSL context for reading or writing, - * and either free it or call \c mbedtls_ssl_session_reset() - * on it before re-using it for a new connection; the current - * connection must be closed. - * - * \note If DTLS is in use, then you may choose to handle - * #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED specially for logging - * purposes, as it is an expected return value rather than an - * actual error, but you still need to reset/free the context. - * - * \note Remarks regarding event-driven DTLS: - * If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram - * from the underlying transport layer is currently being processed, - * and it is safe to idle until the timer or the underlying transport - * signal a new event. This is not true for a successful handshake, - * in which case the datagram of the underlying transport that is - * currently being processed might or might not contain further - * DTLS records. - * - * \note If the context is configured to allow TLS 1.3, or if - * #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - */ -int mbedtls_ssl_handshake(mbedtls_ssl_context *ssl); - -/** - * \brief After calling mbedtls_ssl_handshake() to start the SSL - * handshake you can call this function to check whether the - * handshake is over for a given SSL context. This function - * should be also used to determine when to stop calling - * mbedtls_handshake_step() for that context. - * - * \param ssl SSL context - * - * \return \c 1 if handshake is over, \c 0 if it is still ongoing. - */ -static inline int mbedtls_ssl_is_handshake_over(mbedtls_ssl_context *ssl) -{ - return ssl->MBEDTLS_PRIVATE(state) >= MBEDTLS_SSL_HANDSHAKE_OVER; -} - -/** - * \brief Perform a single step of the SSL handshake - * - * \note The state of the context (ssl->state) will be at - * the next state after this function returns \c 0. Do not - * call this function if mbedtls_ssl_is_handshake_over() - * returns \c 1. - * - * \warning Whilst in the past you may have used direct access to the - * context state (ssl->state) in order to ascertain when to - * stop calling this function and although you can still do - * so with something like ssl->MBEDTLS_PRIVATE(state) or by - * defining MBEDTLS_ALLOW_PRIVATE_ACCESS, this is now - * considered deprecated and could be broken in any future - * release. If you still find you have good reason for such - * direct access, then please do contact the team to explain - * this (raise an issue or post to the mailing list), so that - * we can add a solution to your problem that will be - * guaranteed to work in the future. - * - * \param ssl SSL context - * - * \return See mbedtls_ssl_handshake(). - * - * \warning If this function returns something other than \c 0, - * #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE, - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using - * the SSL context for reading or writing, and either free it - * or call \c mbedtls_ssl_session_reset() on it before - * re-using it for a new connection; the current connection - * must be closed. - */ -int mbedtls_ssl_handshake_step(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_RENEGOTIATION) -/** - * \brief Initiate an SSL renegotiation on the running connection. - * Client: perform the renegotiation right now. - * Server: request renegotiation, which will be performed - * during the next call to mbedtls_ssl_read() if honored by - * client. - * - * \param ssl SSL context - * - * \return 0 if successful, or any mbedtls_ssl_handshake() return - * value except #MBEDTLS_ERR_SSL_CLIENT_RECONNECT that can't - * happen during a renegotiation. - * - * \warning If this function returns something other than \c 0, - * #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE, - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using - * the SSL context for reading or writing, and either free it - * or call \c mbedtls_ssl_session_reset() on it before - * re-using it for a new connection; the current connection - * must be closed. - * - */ -int mbedtls_ssl_renegotiate(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - -/** - * \brief Read at most 'len' application data bytes - * - * \param ssl SSL context - * \param buf buffer that will hold the data - * \param len maximum number of bytes to read - * - * \return The (positive) number of bytes read if successful. - * \return \c 0 if the read end of the underlying transport was closed - * without sending a CloseNotify beforehand, which might happen - * because of various reasons (internal error of an underlying - * stack, non-conformant peer not sending a CloseNotify and - * such) - in this case you must stop using the context - * (see below). - * \return #MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY if the underlying - * transport is still functional, but the peer has - * acknowledged to not send anything anymore. - * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE - * if the handshake is incomplete and waiting for data to - * be available for reading from or writing to the underlying - * transport - in this case you must call this function again - * when the underlying transport is ready for the operation. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous - * operation is in progress (see - * mbedtls_ssl_conf_async_private_cb()) - in this case you - * must call this function again when the operation is ready. - * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic - * operation is in progress (see mbedtls_ecp_set_max_ops()) - - * in this case you must call this function again to complete - * the handshake when you're done attending other tasks. - * \return #MBEDTLS_ERR_SSL_CLIENT_RECONNECT if we're at the server - * side of a DTLS connection and the client is initiating a - * new connection using the same source port. See below. - * \return Another SSL error code - in this case you must stop using - * the context (see below). - * - * \warning If this function returns something other than - * a positive value, - * #MBEDTLS_ERR_SSL_WANT_READ, - * #MBEDTLS_ERR_SSL_WANT_WRITE, - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or - * #MBEDTLS_ERR_SSL_CLIENT_RECONNECT, - * you must stop using the SSL context for reading or writing, - * and either free it or call \c mbedtls_ssl_session_reset() - * on it before re-using it for a new connection; the current - * connection must be closed. - * - * \note When this function returns #MBEDTLS_ERR_SSL_CLIENT_RECONNECT - * (which can only happen server-side), it means that a client - * is initiating a new connection using the same source port. - * You can either treat that as a connection close and wait - * for the client to resend a ClientHello, or directly - * continue with \c mbedtls_ssl_handshake() with the same - * context (as it has been reset internally). Either way, you - * must make sure this is seen by the application as a new - * connection: application state, if any, should be reset, and - * most importantly the identity of the client must be checked - * again. WARNING: not validating the identity of the client - * again, or not transmitting the new identity to the - * application layer, would allow authentication bypass! - * - * \note Remarks regarding event-driven DTLS: - * - If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram - * from the underlying transport layer is currently being processed, - * and it is safe to idle until the timer or the underlying transport - * signal a new event. - * - This function may return MBEDTLS_ERR_SSL_WANT_READ even if data was - * initially available on the underlying transport, as this data may have - * been only e.g. duplicated messages or a renegotiation request. - * Therefore, you must be prepared to receive MBEDTLS_ERR_SSL_WANT_READ even - * when reacting to an incoming-data event from the underlying transport. - * - On success, the datagram of the underlying transport that is currently - * being processed may contain further DTLS records. You should call - * \c mbedtls_ssl_check_pending to check for remaining records. - * - */ -int mbedtls_ssl_read(mbedtls_ssl_context *ssl, unsigned char *buf, size_t len); - -/** - * \brief Try to write exactly 'len' application data bytes - * - * \warning This function will do partial writes in some cases. If the - * return value is non-negative but less than length, the - * function must be called again with updated arguments: - * buf + ret, len - ret (if ret is the return value) until - * it returns a value equal to the last 'len' argument. - * - * \param ssl SSL context - * \param buf buffer holding the data - * \param len how many bytes must be written - * - * \return The (non-negative) number of bytes actually written if - * successful (may be less than \p len). - * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE - * if the handshake is incomplete and waiting for data to - * be available for reading from or writing to the underlying - * transport - in this case you must call this function again - * when the underlying transport is ready for the operation. - * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous - * operation is in progress (see - * mbedtls_ssl_conf_async_private_cb()) - in this case you - * must call this function again when the operation is ready. - * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic - * operation is in progress (see mbedtls_ecp_set_max_ops()) - - * in this case you must call this function again to complete - * the handshake when you're done attending other tasks. - * \return Another SSL error code - in this case you must stop using - * the context (see below). - * - * \warning If this function returns something other than - * a non-negative value, - * #MBEDTLS_ERR_SSL_WANT_READ, - * #MBEDTLS_ERR_SSL_WANT_WRITE, - * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or - * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, - * you must stop using the SSL context for reading or writing, - * and either free it or call \c mbedtls_ssl_session_reset() - * on it before re-using it for a new connection; the current - * connection must be closed. - * - * \note When this function returns #MBEDTLS_ERR_SSL_WANT_WRITE/READ, - * it must be called later with the *same* arguments, - * until it returns a value greater than or equal to 0. When - * the function returns #MBEDTLS_ERR_SSL_WANT_WRITE there may be - * some partial data in the output buffer, however this is not - * yet sent. - * - * \note If the requested length is greater than the maximum - * fragment length (either the built-in limit or the one set - * or negotiated with the peer), then: - * - with TLS, less bytes than requested are written. - * - with DTLS, MBEDTLS_ERR_SSL_BAD_INPUT_DATA is returned. - * \c mbedtls_ssl_get_max_out_record_payload() may be used to - * query the active maximum fragment length. - * - * \note Attempting to write 0 bytes will result in an empty TLS - * application record being sent. - */ -int mbedtls_ssl_write(mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len); - -/** - * \brief Send an alert message - * - * \param ssl SSL context - * \param level The alert level of the message - * (MBEDTLS_SSL_ALERT_LEVEL_WARNING or MBEDTLS_SSL_ALERT_LEVEL_FATAL) - * \param message The alert message (SSL_ALERT_MSG_*) - * - * \return 0 if successful, or a specific SSL error code. - * - * \note If this function returns something other than 0 or - * MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using - * the SSL context for reading or writing, and either free it or - * call \c mbedtls_ssl_session_reset() on it before re-using it - * for a new connection; the current connection must be closed. - */ -int mbedtls_ssl_send_alert_message(mbedtls_ssl_context *ssl, - unsigned char level, - unsigned char message); -/** - * \brief Notify the peer that the connection is being closed - * - * \param ssl SSL context - * - * \return 0 if successful, or a specific SSL error code. - * - * \note If this function returns something other than 0 or - * MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using - * the SSL context for reading or writing, and either free it or - * call \c mbedtls_ssl_session_reset() on it before re-using it - * for a new connection; the current connection must be closed. - */ -int mbedtls_ssl_close_notify(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_EARLY_DATA) - -#if defined(MBEDTLS_SSL_SRV_C) -/** - * \brief Read at most 'len' application data bytes while performing - * the handshake (early data). - * - * \note This function behaves mainly as mbedtls_ssl_read(). The - * specification of mbedtls_ssl_read() relevant to TLS 1.3 - * (thus not the parts specific to (D)TLS 1.2) applies to this - * function and the present documentation is restricted to the - * differences with mbedtls_ssl_read(). - * - * \param ssl SSL context - * \param buf buffer that will hold the data - * \param len maximum number of bytes to read - * - * \return One additional specific return value: - * #MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA. - * - * #MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA is returned when it - * is not possible to read early data for the SSL context - * \p ssl. - * - * It may have been possible and it is not possible - * anymore because the server received the End of Early Data - * message or the maximum number of allowed early data for the - * PSK in use has been reached. - * - * It may never have been possible and will never be possible - * for the SSL context \p ssl because the use of early data - * is disabled for that context or more generally the context - * is not suitably configured to enable early data or the - * client does not use early data or the first call to the - * function was done while the handshake was already too - * advanced to gather and accept early data. - * - * It is not possible to read early data for the SSL context - * \p ssl but this does not preclude for using it with - * mbedtls_ssl_write(), mbedtls_ssl_read() or - * mbedtls_ssl_handshake(). - * - * \note When a server wants to retrieve early data, it is expected - * that this function starts the handshake for the SSL context - * \p ssl. But this is not mandatory. - * - */ -int mbedtls_ssl_read_early_data(mbedtls_ssl_context *ssl, - unsigned char *buf, size_t len); -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_CLI_C) -/** - * \brief Try to write exactly 'len' application data bytes while - * performing the handshake (early data). - * - * \note This function behaves mainly as mbedtls_ssl_write(). The - * specification of mbedtls_ssl_write() relevant to TLS 1.3 - * (thus not the parts specific to (D)TLS1.2) applies to this - * function and the present documentation is restricted to the - * differences with mbedtls_ssl_write(). - * - * \param ssl SSL context - * \param buf buffer holding the data - * \param len how many bytes must be written - * - * \return One additional specific return value: - * #MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA. - * - * #MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA is returned when it - * is not possible to write early data for the SSL context - * \p ssl. - * - * It may have been possible and it is not possible - * anymore because the client received the server Finished - * message, the server rejected early data or the maximum - * number of allowed early data for the PSK in use has been - * reached. - * - * It may never have been possible and will never be possible - * for the SSL context \p ssl because the use of early data - * is disabled for that context or more generally the context - * is not suitably configured to enable early data or the first - * call to the function was done while the handshake was - * already completed. - * - * It is not possible to write early data for the SSL context - * \p ssl but this does not preclude for using it with - * mbedtls_ssl_write(), mbedtls_ssl_read() or - * mbedtls_ssl_handshake(). - * - * \note This function may write early data only if the SSL context - * has been configured for the handshake with a PSK for which - * early data is allowed. - * - * \note To maximize the number of early data that can be written in - * the course of the handshake, it is expected that this - * function starts the handshake for the SSL context \p ssl. - * But this is not mandatory. - * - * \note This function does not provide any information on whether - * the server has accepted or will accept early data or not. - * When it returns a positive value, it just means that it - * has written early data to the server. To know whether the - * server has accepted early data or not, you should call - * mbedtls_ssl_get_early_data_status() with the handshake - * completed. - */ -int mbedtls_ssl_write_early_data(mbedtls_ssl_context *ssl, - const unsigned char *buf, size_t len); - -#define MBEDTLS_SSL_EARLY_DATA_STATUS_NOT_SENT 0 -#define MBEDTLS_SSL_EARLY_DATA_STATUS_ACCEPTED 1 -#define MBEDTLS_SSL_EARLY_DATA_STATUS_REJECTED 2 -/** - * \brief Get the status of the negotiation of the use of early data. - * - * \param ssl The SSL context to query - * - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if this function is called - * from the server-side. - * - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if this function is called - * prior to completion of the handshake. - * - * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_NOT_SENT if the client has - * not indicated the use of early data to the server. - * - * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_ACCEPTED if the client has - * indicated the use of early data and the server has accepted - * it. - * - * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_REJECTED if the client has - * indicated the use of early data but the server has rejected - * it. In this situation, the client may want to re-send the - * early data it may have tried to send by calling - * mbedtls_ssl_write_early_data() as ordinary post-handshake - * application data by calling mbedtls_ssl_write(). - * - */ -int mbedtls_ssl_get_early_data_status(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_CLI_C */ - -#endif /* MBEDTLS_SSL_EARLY_DATA */ - -/** - * \brief Free referenced items in an SSL context and clear memory - * - * \param ssl SSL context - */ -void mbedtls_ssl_free(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) -/** - * \brief Save an active connection as serialized data in a buffer. - * This allows the freeing or re-using of the SSL context - * while still picking up the connection later in a way that - * it entirely transparent to the peer. - * - * \see mbedtls_ssl_context_load() - * - * \note The serialized data only contains the data that is - * necessary to resume the connection: negotiated protocol - * options, session identifier, keys, etc. - * Loading a saved SSL context does not restore settings and - * state related to how the application accesses the context, - * such as configured callback functions, user data, pending - * incoming or outgoing data, etc. - * - * \note This feature is currently only available under certain - * conditions, see the documentation of the return value - * #MBEDTLS_ERR_SSL_BAD_INPUT_DATA for details. - * - * \note When this function succeeds, it calls - * mbedtls_ssl_session_reset() on \p ssl which as a result is - * no longer associated with the connection that has been - * serialized. This avoids creating copies of the connection - * state. You're then free to either re-use the context - * structure for a different connection, or call - * mbedtls_ssl_free() on it. See the documentation of - * mbedtls_ssl_session_reset() for more details. - * - * \param ssl The SSL context to save. On success, it is no longer - * associated with the connection that has been serialized. - * \param buf The buffer to write the serialized data to. It must be a - * writeable buffer of at least \p buf_len bytes, or may be \c - * NULL if \p buf_len is \c 0. - * \param buf_len The number of bytes available for writing in \p buf. - * \param olen The size in bytes of the data that has been or would have - * been written. It must point to a valid \c size_t. - * - * \note \p olen is updated to the correct value regardless of - * whether \p buf_len was large enough. This makes it possible - * to determine the necessary size by calling this function - * with \p buf set to \c NULL and \p buf_len to \c 0. However, - * the value of \p olen is only guaranteed to be correct when - * the function returns #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL or - * \c 0. If the return value is different, then the value of - * \p olen is undefined. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL if \p buf is too small. - * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed - * while resetting the context. - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if a handshake is in - * progress, or there is pending data for reading or sending, - * or the connection does not use DTLS 1.2 with an AEAD - * ciphersuite, or renegotiation is enabled. - */ -int mbedtls_ssl_context_save(mbedtls_ssl_context *ssl, - unsigned char *buf, - size_t buf_len, - size_t *olen); - -/** - * \brief Load serialized connection data to an SSL context. - * - * \see mbedtls_ssl_context_save() - * - * \warning The same serialized data must never be loaded into more - * that one context. In order to ensure that, after - * successfully loading serialized data to an SSL context, you - * should immediately destroy or invalidate all copies of the - * serialized data that was loaded. Loading the same data in - * more than one context would cause severe security failures - * including but not limited to loss of confidentiality. - * - * \note Before calling this function, the SSL context must be - * prepared in one of the two following ways. The first way is - * to take a context freshly initialised with - * mbedtls_ssl_init() and call mbedtls_ssl_setup() on it with - * the same ::mbedtls_ssl_config structure that was used in - * the original connection. The second way is to - * call mbedtls_ssl_session_reset() on a context that was - * previously prepared as above but used in the meantime. - * Either way, you must not use the context to perform a - * handshake between calling mbedtls_ssl_setup() or - * mbedtls_ssl_session_reset() and calling this function. You - * may however call other setter functions in that time frame - * as indicated in the note below. - * - * \note Before or after calling this function successfully, you - * also need to configure some connection-specific callbacks - * and settings before you can use the connection again - * (unless they were already set before calling - * mbedtls_ssl_session_reset() and the values are suitable for - * the present connection). Specifically, you want to call - * at least mbedtls_ssl_set_bio(), - * mbedtls_ssl_set_timer_cb(), and - * mbedtls_ssl_set_user_data_n() or - * mbedtls_ssl_set_user_data_p() if they were set originally. - * All other SSL setter functions - * are not necessary to call, either because they're only used - * in handshakes, or because the setting is already saved. You - * might choose to call them anyway, for example in order to - * share code between the cases of establishing a new - * connection and the case of loading an already-established - * connection. - * - * \note If you have new information about the path MTU, you want to - * call mbedtls_ssl_set_mtu() after calling this function, as - * otherwise this function would overwrite your - * newly-configured value with the value that was active when - * the context was saved. - * - * \note When this function returns an error code, it calls - * mbedtls_ssl_free() on \p ssl. In this case, you need to - * prepare the context with the usual sequence starting with a - * call to mbedtls_ssl_init() if you want to use it again. - * - * \param ssl The SSL context structure to be populated. It must have - * been prepared as described in the note above. - * \param buf The buffer holding the serialized connection data. It must - * be a readable buffer of at least \p len bytes. - * \param len The size of the serialized data in bytes. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed. - * \return #MBEDTLS_ERR_SSL_VERSION_MISMATCH if the serialized data - * comes from a different Mbed TLS version or build. - * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if input data is invalid. - */ -int mbedtls_ssl_context_load(mbedtls_ssl_context *ssl, - const unsigned char *buf, - size_t len); -#endif /* MBEDTLS_SSL_CONTEXT_SERIALIZATION */ - -/** - * \brief Initialize an SSL configuration context - * Just makes the context ready for - * mbedtls_ssl_config_defaults() or mbedtls_ssl_config_free(). - * - * \note You need to call mbedtls_ssl_config_defaults() unless you - * manually set all of the relevant fields yourself. - * - * \param conf SSL configuration context - */ -void mbedtls_ssl_config_init(mbedtls_ssl_config *conf); - -/** - * \brief Load reasonable default SSL configuration values. - * (You need to call mbedtls_ssl_config_init() first.) - * - * \param conf SSL configuration context - * \param endpoint MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER - * \param transport MBEDTLS_SSL_TRANSPORT_STREAM for TLS, or - * MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS - * \param preset a MBEDTLS_SSL_PRESET_XXX value - * - * \note See \c mbedtls_ssl_conf_transport() for notes on DTLS. - * - * \return 0 if successful, or - * MBEDTLS_ERR_XXX_ALLOC_FAILED on memory allocation error. - */ -int mbedtls_ssl_config_defaults(mbedtls_ssl_config *conf, - int endpoint, int transport, int preset); - -/** - * \brief Free an SSL configuration context - * - * \param conf SSL configuration context - */ -void mbedtls_ssl_config_free(mbedtls_ssl_config *conf); - -/** - * \brief Initialize SSL session structure - * - * \param session SSL session - */ -void mbedtls_ssl_session_init(mbedtls_ssl_session *session); - -/** - * \brief Free referenced items in an SSL session including the - * peer certificate and clear memory - * - * \note A session object can be freed even if the SSL context - * that was used to retrieve the session is still in use. - * - * \param session SSL session - */ -void mbedtls_ssl_session_free(mbedtls_ssl_session *session); - -/** - * \brief TLS-PRF function for key derivation. - * - * \param prf The tls_prf type function type to be used. - * \param secret Secret for the key derivation function. - * \param slen Length of the secret. - * \param label String label for the key derivation function, - * terminated with null character. - * \param random Random bytes. - * \param rlen Length of the random bytes buffer. - * \param dstbuf The buffer holding the derived key. - * \param dlen Length of the output buffer. - * - * \return 0 on success. An SSL specific error on failure. - */ -int mbedtls_ssl_tls_prf(const mbedtls_tls_prf_types prf, - const unsigned char *secret, size_t slen, - const char *label, - const unsigned char *random, size_t rlen, - unsigned char *dstbuf, size_t dlen); - -#ifdef __cplusplus -} -#endif - -#endif /* ssl.h */ +/** + * \file ssl.h + * + * \brief SSL/TLS functions. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_H +#define MBEDTLS_SSL_H +#include "mbedtls/platform_util.h" +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/bignum.h" +#include "mbedtls/ecp.h" + +#include "mbedtls/ssl_ciphersuites.h" + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +#include "mbedtls/x509_crt.h" +#include "mbedtls/x509_crl.h" +#endif + +#if defined(MBEDTLS_DHM_C) +#include "mbedtls/dhm.h" +#endif + +#include "mbedtls/md.h" + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) +#include "mbedtls/ecdh.h" +#endif + +#if defined(MBEDTLS_HAVE_TIME) +#include "mbedtls/platform_time.h" +#endif + +#include "psa/crypto.h" + +/* + * SSL Error codes + */ +/** A cryptographic operation is in progress. Try again later. */ +#define MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS -0x7000 +/** The requested feature is not available. */ +#define MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE -0x7080 +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_SSL_BAD_INPUT_DATA -0x7100 +/** Verification of the message MAC failed. */ +#define MBEDTLS_ERR_SSL_INVALID_MAC -0x7180 +/** An invalid SSL record was received. */ +#define MBEDTLS_ERR_SSL_INVALID_RECORD -0x7200 +/** The connection indicated an EOF. */ +#define MBEDTLS_ERR_SSL_CONN_EOF -0x7280 +/** A message could not be parsed due to a syntactic error. */ +#define MBEDTLS_ERR_SSL_DECODE_ERROR -0x7300 +/* Error space gap */ +/** No RNG was provided to the SSL module. */ +#define MBEDTLS_ERR_SSL_NO_RNG -0x7400 +/** No client certification received from the client, but required by the authentication mode. */ +#define MBEDTLS_ERR_SSL_NO_CLIENT_CERTIFICATE -0x7480 +/** Client received an extended server hello containing an unsupported extension */ +#define MBEDTLS_ERR_SSL_UNSUPPORTED_EXTENSION -0x7500 +/** No ALPN protocols supported that the client advertises */ +#define MBEDTLS_ERR_SSL_NO_APPLICATION_PROTOCOL -0x7580 +/** The own private key or pre-shared key is not set, but needed. */ +#define MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED -0x7600 +/** No CA Chain is set, but required to operate. */ +#define MBEDTLS_ERR_SSL_CA_CHAIN_REQUIRED -0x7680 +/** An unexpected message was received from our peer. */ +#define MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE -0x7700 +/** A fatal alert message was received from our peer. */ +#define MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE -0x7780 +/** No server could be identified matching the client's SNI. */ +#define MBEDTLS_ERR_SSL_UNRECOGNIZED_NAME -0x7800 +/** The peer notified us that the connection is going to be closed. */ +#define MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY -0x7880 +/* Error space gap */ +/* Error space gap */ +/** Processing of the Certificate handshake message failed. */ +#define MBEDTLS_ERR_SSL_BAD_CERTIFICATE -0x7A00 +/* Error space gap */ +/** + * Received NewSessionTicket Post Handshake Message. + * This error code is experimental and may be changed or removed without notice. + */ +#define MBEDTLS_ERR_SSL_RECEIVED_NEW_SESSION_TICKET -0x7B00 +/** Not possible to read early data */ +#define MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA -0x7B80 +/** Not possible to write early data */ +#define MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA -0x7C00 +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/** Cache entry not found */ +#define MBEDTLS_ERR_SSL_CACHE_ENTRY_NOT_FOUND -0x7E80 +/** Memory allocation failed */ +#define MBEDTLS_ERR_SSL_ALLOC_FAILED -0x7F00 +/** Hardware acceleration function returned with error */ +#define MBEDTLS_ERR_SSL_HW_ACCEL_FAILED -0x7F80 +/** Hardware acceleration function skipped / left alone data */ +#define MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH -0x6F80 +/** Handshake protocol not within min/max boundaries */ +#define MBEDTLS_ERR_SSL_BAD_PROTOCOL_VERSION -0x6E80 +/** The handshake negotiation failed. */ +#define MBEDTLS_ERR_SSL_HANDSHAKE_FAILURE -0x6E00 +/** Session ticket has expired. */ +#define MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED -0x6D80 +/** Public key type mismatch (eg, asked for RSA key exchange and presented EC key) */ +#define MBEDTLS_ERR_SSL_PK_TYPE_MISMATCH -0x6D00 +/** Unknown identity received (eg, PSK identity) */ +#define MBEDTLS_ERR_SSL_UNKNOWN_IDENTITY -0x6C80 +/** Internal error (eg, unexpected failure in lower-level module) */ +#define MBEDTLS_ERR_SSL_INTERNAL_ERROR -0x6C00 +/** A counter would wrap (eg, too many messages exchanged). */ +#define MBEDTLS_ERR_SSL_COUNTER_WRAPPING -0x6B80 +/** Unexpected message at ServerHello in renegotiation. */ +#define MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO -0x6B00 +/** DTLS client must retry for hello verification */ +#define MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED -0x6A80 +/** A buffer is too small to receive or write a message */ +#define MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL -0x6A00 +/* Error space gap */ +/** No data of requested type currently available on underlying transport. */ +#define MBEDTLS_ERR_SSL_WANT_READ -0x6900 +/** Connection requires a write call. */ +#define MBEDTLS_ERR_SSL_WANT_WRITE -0x6880 +/** The operation timed out. */ +#define MBEDTLS_ERR_SSL_TIMEOUT -0x6800 +/** The client initiated a reconnect from the same port. */ +#define MBEDTLS_ERR_SSL_CLIENT_RECONNECT -0x6780 +/** Record header looks valid but is not expected. */ +#define MBEDTLS_ERR_SSL_UNEXPECTED_RECORD -0x6700 +/** The alert message received indicates a non-fatal error. */ +#define MBEDTLS_ERR_SSL_NON_FATAL -0x6680 +/** A field in a message was incorrect or inconsistent with other fields. */ +#define MBEDTLS_ERR_SSL_ILLEGAL_PARAMETER -0x6600 +/** Internal-only message signaling that further message-processing should be done */ +#define MBEDTLS_ERR_SSL_CONTINUE_PROCESSING -0x6580 +/** The asynchronous operation is not completed yet. */ +#define MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS -0x6500 +/** Internal-only message signaling that a message arrived early. */ +#define MBEDTLS_ERR_SSL_EARLY_MESSAGE -0x6480 +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/* Error space gap */ +/** An encrypted DTLS-frame with an unexpected CID was received. */ +#define MBEDTLS_ERR_SSL_UNEXPECTED_CID -0x6000 +/** An operation failed due to an unexpected version or configuration. */ +#define MBEDTLS_ERR_SSL_VERSION_MISMATCH -0x5F00 +/** Invalid value in SSL config */ +#define MBEDTLS_ERR_SSL_BAD_CONFIG -0x5E80 + +/* + * Constants from RFC 8446 for TLS 1.3 PSK modes + * + * Those are used in the Pre-Shared Key Exchange Modes extension. + * See Section 4.2.9 in RFC 8446. + */ +#define MBEDTLS_SSL_TLS1_3_PSK_MODE_PURE 0 /* Pure PSK-based exchange */ +#define MBEDTLS_SSL_TLS1_3_PSK_MODE_ECDHE 1 /* PSK+ECDHE-based exchange */ + +/* + * TLS 1.3 NamedGroup values + * + * From RF 8446 + * enum { + * // Elliptic Curve Groups (ECDHE) + * secp256r1(0x0017), secp384r1(0x0018), secp521r1(0x0019), + * x25519(0x001D), x448(0x001E), + * // Finite Field Groups (DHE) + * ffdhe2048(0x0100), ffdhe3072(0x0101), ffdhe4096(0x0102), + * ffdhe6144(0x0103), ffdhe8192(0x0104), + * // Reserved Code Points + * ffdhe_private_use(0x01FC..0x01FF), + * ecdhe_private_use(0xFE00..0xFEFF), + * (0xFFFF) + * } NamedGroup; + * + */ + +/* Elliptic Curve Groups (ECDHE) */ +#define MBEDTLS_SSL_IANA_TLS_GROUP_NONE 0 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP192K1 0x0012 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP192R1 0x0013 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP224K1 0x0014 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP224R1 0x0015 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP256K1 0x0016 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 0x0017 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 0x0018 +#define MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1 0x0019 +#define MBEDTLS_SSL_IANA_TLS_GROUP_BP256R1 0x001A +#define MBEDTLS_SSL_IANA_TLS_GROUP_BP384R1 0x001B +#define MBEDTLS_SSL_IANA_TLS_GROUP_BP512R1 0x001C +#define MBEDTLS_SSL_IANA_TLS_GROUP_X25519 0x001D +#define MBEDTLS_SSL_IANA_TLS_GROUP_X448 0x001E +/* Finite Field Groups (DHE) */ +#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE2048 0x0100 +#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE3072 0x0101 +#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE4096 0x0102 +#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE6144 0x0103 +#define MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE8192 0x0104 + +/* + * TLS 1.3 Key Exchange Modes + * + * Mbed TLS internal identifiers for use with the SSL configuration API + * mbedtls_ssl_conf_tls13_key_exchange_modes(). + */ + +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK (1u << 0) /*!< Pure-PSK TLS 1.3 key exchange, + * encompassing both externally agreed PSKs + * as well as resumption PSKs. */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL (1u << 1) /*!< Pure-Ephemeral TLS 1.3 key exchanges, + * including for example ECDHE and DHE + * key exchanges. */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL (1u << 2) /*!< PSK-Ephemeral TLS 1.3 key exchanges, + * using both a PSK and an ephemeral + * key exchange. */ + +/* Convenience macros for sets of key exchanges. */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_ALL \ + (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK | \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL | \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL) /*!< All TLS 1.3 key exchanges */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL \ + (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK | \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL) /*!< All PSK-based TLS 1.3 key exchanges */ +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL \ + (MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL | \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL) /*!< All ephemeral TLS 1.3 key exchanges */ + +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_NONE (0) + +/* + * Various constants + */ + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/* These are the high and low bytes of ProtocolVersion as defined by: + * - RFC 5246: ProtocolVersion version = { 3, 3 }; // TLS v1.2 + * - RFC 8446: see section 4.2.1 + */ +#define MBEDTLS_SSL_MAJOR_VERSION_3 3 +#define MBEDTLS_SSL_MINOR_VERSION_3 3 /*!< TLS v1.2 */ +#define MBEDTLS_SSL_MINOR_VERSION_4 4 /*!< TLS v1.3 */ +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +#define MBEDTLS_SSL_TRANSPORT_STREAM 0 /*!< TLS */ +#define MBEDTLS_SSL_TRANSPORT_DATAGRAM 1 /*!< DTLS */ + +#define MBEDTLS_SSL_MAX_HOST_NAME_LEN 255 /*!< Maximum host name defined in RFC 1035 */ +#define MBEDTLS_SSL_MAX_ALPN_NAME_LEN 255 /*!< Maximum size in bytes of a protocol name in alpn ext., RFC 7301 */ + +#define MBEDTLS_SSL_MAX_ALPN_LIST_LEN 65535 /*!< Maximum size in bytes of list in alpn ext., RFC 7301 */ + +/* RFC 6066 section 4, see also mfl_code_to_length in ssl_tls.c + * NONE must be zero so that memset()ing structure to zero works */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_NONE 0 /*!< don't use this extension */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_512 1 /*!< MaxFragmentLength 2^9 */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_1024 2 /*!< MaxFragmentLength 2^10 */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_2048 3 /*!< MaxFragmentLength 2^11 */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_4096 4 /*!< MaxFragmentLength 2^12 */ +#define MBEDTLS_SSL_MAX_FRAG_LEN_INVALID 5 /*!< first invalid value */ + +#define MBEDTLS_SSL_IS_CLIENT 0 +#define MBEDTLS_SSL_IS_SERVER 1 + +#define MBEDTLS_SSL_EXTENDED_MS_DISABLED 0 +#define MBEDTLS_SSL_EXTENDED_MS_ENABLED 1 + +#define MBEDTLS_SSL_CID_DISABLED 0 +#define MBEDTLS_SSL_CID_ENABLED 1 + +#define MBEDTLS_SSL_ETM_DISABLED 0 +#define MBEDTLS_SSL_ETM_ENABLED 1 + +#define MBEDTLS_SSL_COMPRESS_NULL 0 + +#define MBEDTLS_SSL_VERIFY_NONE 0 +#define MBEDTLS_SSL_VERIFY_OPTIONAL 1 +#define MBEDTLS_SSL_VERIFY_REQUIRED 2 +#define MBEDTLS_SSL_VERIFY_UNSET 3 /* Used only for sni_authmode */ + +#define MBEDTLS_SSL_LEGACY_RENEGOTIATION 0 +#define MBEDTLS_SSL_SECURE_RENEGOTIATION 1 + +#define MBEDTLS_SSL_RENEGOTIATION_DISABLED 0 +#define MBEDTLS_SSL_RENEGOTIATION_ENABLED 1 + +#define MBEDTLS_SSL_ANTI_REPLAY_DISABLED 0 +#define MBEDTLS_SSL_ANTI_REPLAY_ENABLED 1 + +#define MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED -1 +#define MBEDTLS_SSL_RENEGO_MAX_RECORDS_DEFAULT 16 + +#define MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION 0 +#define MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION 1 +#define MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE 2 + +#define MBEDTLS_SSL_TRUNC_HMAC_DISABLED 0 +#define MBEDTLS_SSL_TRUNC_HMAC_ENABLED 1 +#define MBEDTLS_SSL_TRUNCATED_HMAC_LEN 10 /* 80 bits, rfc 6066 section 7 */ + +#define MBEDTLS_SSL_SESSION_TICKETS_DISABLED 0 +#define MBEDTLS_SSL_SESSION_TICKETS_ENABLED 1 + +#define MBEDTLS_SSL_PRESET_DEFAULT 0 +#define MBEDTLS_SSL_PRESET_SUITEB 2 + +#define MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED 1 +#define MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED 0 + +#define MBEDTLS_SSL_EARLY_DATA_DISABLED 0 +#define MBEDTLS_SSL_EARLY_DATA_ENABLED 1 + +#define MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED 0 +#define MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED 1 + +#define MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_CLIENT 1 +#define MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER 0 + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +#if defined(PSA_WANT_ALG_SHA_384) +#define MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN 48 +#elif defined(PSA_WANT_ALG_SHA_256) +#define MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN 32 +#endif +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ +/* + * Default range for DTLS retransmission timer value, in milliseconds. + * RFC 6347 4.2.4.1 says from 1 second to 60 seconds. + */ +#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MIN 1000 +#define MBEDTLS_SSL_DTLS_TIMEOUT_DFL_MAX 60000 + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +/* + * Maximum fragment length in bytes, + * determines the size of each of the two internal I/O buffers. + * + * Note: the RFC defines the default size of SSL / TLS messages. If you + * change the value here, other clients / servers may not be able to + * communicate with you anymore. Only change this value if you control + * both sides of the connection and have it reduced at both sides, or + * if you're using the Max Fragment Length extension and you know all your + * peers are using it too! + */ +#if !defined(MBEDTLS_SSL_IN_CONTENT_LEN) +#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 +#endif + +#if !defined(MBEDTLS_SSL_OUT_CONTENT_LEN) +#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 +#endif + +/* + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + */ +#if !defined(MBEDTLS_SSL_DTLS_MAX_BUFFERING) +#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 +#endif + +/* + * Maximum length of CIDs for incoming and outgoing messages. + */ +#if !defined(MBEDTLS_SSL_CID_IN_LEN_MAX) +#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 +#endif + +#if !defined(MBEDTLS_SSL_CID_OUT_LEN_MAX) +#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 +#endif + +#if !defined(MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY) +#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 +#endif + +#if !defined(MBEDTLS_SSL_MAX_EARLY_DATA_SIZE) +#define MBEDTLS_SSL_MAX_EARLY_DATA_SIZE 1024 +#endif + +#if !defined(MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE) +#define MBEDTLS_SSL_TLS1_3_TICKET_AGE_TOLERANCE 6000 +#endif + +#if !defined(MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH) +#define MBEDTLS_SSL_TLS1_3_TICKET_NONCE_LENGTH 32 +#endif + +#if !defined(MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS) +#define MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS 1 +#endif + +/** \} name SECTION: Module settings */ + +/* + * Default to standard CID mode + */ +#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT) +#define MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT 0 +#endif + +/* + * Length of the verify data for secure renegotiation + */ +#define MBEDTLS_SSL_VERIFY_DATA_MAX_LEN 12 + +/* + * Signaling ciphersuite values (SCSV) + */ +#define MBEDTLS_SSL_EMPTY_RENEGOTIATION_INFO 0xFF /**< renegotiation info ext */ + +/* + * Supported Signature and Hash algorithms (For TLS 1.2) + * RFC 5246 section 7.4.1.4.1 + */ +#define MBEDTLS_SSL_HASH_NONE 0 +#define MBEDTLS_SSL_HASH_MD5 1 +#define MBEDTLS_SSL_HASH_SHA1 2 +#define MBEDTLS_SSL_HASH_SHA224 3 +#define MBEDTLS_SSL_HASH_SHA256 4 +#define MBEDTLS_SSL_HASH_SHA384 5 +#define MBEDTLS_SSL_HASH_SHA512 6 + +#define MBEDTLS_SSL_SIG_ANON 0 +#define MBEDTLS_SSL_SIG_RSA 1 +#define MBEDTLS_SSL_SIG_ECDSA 3 + +/* + * TLS 1.3 signature algorithms + * RFC 8446, Section 4.2.2 + */ + +/* RSASSA-PKCS1-v1_5 algorithms */ +#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA256 0x0401 +#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA384 0x0501 +#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA512 0x0601 + +/* ECDSA algorithms */ +#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP256R1_SHA256 0x0403 +#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP384R1_SHA384 0x0503 +#define MBEDTLS_TLS1_3_SIG_ECDSA_SECP521R1_SHA512 0x0603 + +/* RSASSA-PSS algorithms with public key OID rsaEncryption */ +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256 0x0804 +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384 0x0805 +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512 0x0806 + +/* EdDSA algorithms */ +#define MBEDTLS_TLS1_3_SIG_ED25519 0x0807 +#define MBEDTLS_TLS1_3_SIG_ED448 0x0808 + +/* RSASSA-PSS algorithms with public key OID RSASSA-PSS */ +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA256 0x0809 +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA384 0x080A +#define MBEDTLS_TLS1_3_SIG_RSA_PSS_PSS_SHA512 0x080B + +/* LEGACY ALGORITHMS */ +#define MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA1 0x0201 +#define MBEDTLS_TLS1_3_SIG_ECDSA_SHA1 0x0203 + +#define MBEDTLS_TLS1_3_SIG_NONE 0x0 + +/* + * Client Certificate Types + * RFC 5246 section 7.4.4 plus RFC 4492 section 5.5 + */ +#define MBEDTLS_SSL_CERT_TYPE_RSA_SIGN 1 +#define MBEDTLS_SSL_CERT_TYPE_ECDSA_SIGN 64 + +/* + * Message, alert and handshake types + */ +#define MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC 20 +#define MBEDTLS_SSL_MSG_ALERT 21 +#define MBEDTLS_SSL_MSG_HANDSHAKE 22 +#define MBEDTLS_SSL_MSG_APPLICATION_DATA 23 +#define MBEDTLS_SSL_MSG_CID 25 + +#define MBEDTLS_SSL_ALERT_LEVEL_WARNING 1 +#define MBEDTLS_SSL_ALERT_LEVEL_FATAL 2 + +#define MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY 0 /* 0x00 */ +#define MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE 10 /* 0x0A */ +#define MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC 20 /* 0x14 */ +#define MBEDTLS_SSL_ALERT_MSG_DECRYPTION_FAILED 21 /* 0x15 */ +#define MBEDTLS_SSL_ALERT_MSG_RECORD_OVERFLOW 22 /* 0x16 */ +#define MBEDTLS_SSL_ALERT_MSG_DECOMPRESSION_FAILURE 30 /* 0x1E */ +#define MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE 40 /* 0x28 */ +#define MBEDTLS_SSL_ALERT_MSG_NO_CERT 41 /* 0x29 */ +#define MBEDTLS_SSL_ALERT_MSG_BAD_CERT 42 /* 0x2A */ +#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_CERT 43 /* 0x2B */ +#define MBEDTLS_SSL_ALERT_MSG_CERT_REVOKED 44 /* 0x2C */ +#define MBEDTLS_SSL_ALERT_MSG_CERT_EXPIRED 45 /* 0x2D */ +#define MBEDTLS_SSL_ALERT_MSG_CERT_UNKNOWN 46 /* 0x2E */ +#define MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER 47 /* 0x2F */ +#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_CA 48 /* 0x30 */ +#define MBEDTLS_SSL_ALERT_MSG_ACCESS_DENIED 49 /* 0x31 */ +#define MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR 50 /* 0x32 */ +#define MBEDTLS_SSL_ALERT_MSG_DECRYPT_ERROR 51 /* 0x33 */ +#define MBEDTLS_SSL_ALERT_MSG_EXPORT_RESTRICTION 60 /* 0x3C */ +#define MBEDTLS_SSL_ALERT_MSG_PROTOCOL_VERSION 70 /* 0x46 */ +#define MBEDTLS_SSL_ALERT_MSG_INSUFFICIENT_SECURITY 71 /* 0x47 */ +#define MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR 80 /* 0x50 */ +#define MBEDTLS_SSL_ALERT_MSG_INAPROPRIATE_FALLBACK 86 /* 0x56 */ +#define MBEDTLS_SSL_ALERT_MSG_USER_CANCELED 90 /* 0x5A */ +#define MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION 100 /* 0x64 */ +#define MBEDTLS_SSL_ALERT_MSG_MISSING_EXTENSION 109 /* 0x6d -- new in TLS 1.3 */ +#define MBEDTLS_SSL_ALERT_MSG_UNSUPPORTED_EXT 110 /* 0x6E */ +#define MBEDTLS_SSL_ALERT_MSG_UNRECOGNIZED_NAME 112 /* 0x70 */ +#define MBEDTLS_SSL_ALERT_MSG_UNKNOWN_PSK_IDENTITY 115 /* 0x73 */ +#define MBEDTLS_SSL_ALERT_MSG_CERT_REQUIRED 116 /* 0x74 */ +#define MBEDTLS_SSL_ALERT_MSG_NO_APPLICATION_PROTOCOL 120 /* 0x78 */ + +#define MBEDTLS_SSL_HS_HELLO_REQUEST 0 +#define MBEDTLS_SSL_HS_CLIENT_HELLO 1 +#define MBEDTLS_SSL_HS_SERVER_HELLO 2 +#define MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST 3 +#define MBEDTLS_SSL_HS_NEW_SESSION_TICKET 4 +#define MBEDTLS_SSL_HS_END_OF_EARLY_DATA 5 +#define MBEDTLS_SSL_HS_ENCRYPTED_EXTENSIONS 8 +#define MBEDTLS_SSL_HS_CERTIFICATE 11 +#define MBEDTLS_SSL_HS_SERVER_KEY_EXCHANGE 12 +#define MBEDTLS_SSL_HS_CERTIFICATE_REQUEST 13 +#define MBEDTLS_SSL_HS_SERVER_HELLO_DONE 14 +#define MBEDTLS_SSL_HS_CERTIFICATE_VERIFY 15 +#define MBEDTLS_SSL_HS_CLIENT_KEY_EXCHANGE 16 +#define MBEDTLS_SSL_HS_FINISHED 20 +#define MBEDTLS_SSL_HS_MESSAGE_HASH 254 + +/* + * TLS extensions + */ +#define MBEDTLS_TLS_EXT_SERVERNAME 0 +#define MBEDTLS_TLS_EXT_SERVERNAME_HOSTNAME 0 + +#define MBEDTLS_TLS_EXT_MAX_FRAGMENT_LENGTH 1 + +#define MBEDTLS_TLS_EXT_TRUNCATED_HMAC 4 +#define MBEDTLS_TLS_EXT_STATUS_REQUEST 5 /* RFC 6066 TLS 1.2 and 1.3 */ + +#define MBEDTLS_TLS_EXT_SUPPORTED_ELLIPTIC_CURVES 10 +#define MBEDTLS_TLS_EXT_SUPPORTED_GROUPS 10 /* RFC 8422,7919 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS 11 + +#define MBEDTLS_TLS_EXT_SIG_ALG 13 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_USE_SRTP 14 +#define MBEDTLS_TLS_EXT_HEARTBEAT 15 /* RFC 6520 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_ALPN 16 + +#define MBEDTLS_TLS_EXT_SCT 18 /* RFC 6962 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_CLI_CERT_TYPE 19 /* RFC 7250 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_SERV_CERT_TYPE 20 /* RFC 7250 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_PADDING 21 /* RFC 7685 TLS 1.2 and 1.3 */ +#define MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC 22 /* 0x16 */ +#define MBEDTLS_TLS_EXT_EXTENDED_MASTER_SECRET 0x0017 /* 23 */ + +#define MBEDTLS_TLS_EXT_RECORD_SIZE_LIMIT 28 /* RFC 8449 (implemented for TLS 1.3 only) */ + +#define MBEDTLS_TLS_EXT_SESSION_TICKET 35 + +#define MBEDTLS_TLS_EXT_PRE_SHARED_KEY 41 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_EARLY_DATA 42 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_SUPPORTED_VERSIONS 43 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_COOKIE 44 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_PSK_KEY_EXCHANGE_MODES 45 /* RFC 8446 TLS 1.3 */ + +#define MBEDTLS_TLS_EXT_CERT_AUTH 47 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_OID_FILTERS 48 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_POST_HANDSHAKE_AUTH 49 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_SIG_ALG_CERT 50 /* RFC 8446 TLS 1.3 */ +#define MBEDTLS_TLS_EXT_KEY_SHARE 51 /* RFC 8446 TLS 1.3 */ + +#if MBEDTLS_SSL_DTLS_CONNECTION_ID_COMPAT == 0 +#define MBEDTLS_TLS_EXT_CID 54 /* RFC 9146 DTLS 1.2 CID */ +#else +#define MBEDTLS_TLS_EXT_CID 254 /* Pre-RFC 9146 DTLS 1.2 CID */ +#endif + +#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP 256 /* experimental */ + +#define MBEDTLS_TLS_EXT_RENEGOTIATION_INFO 0xFF01 + +/* + * Size defines + */ +#if !defined(MBEDTLS_PSK_MAX_LEN) +/* + * If the library supports TLS 1.3 tickets and the cipher suite + * TLS1-3-AES-256-GCM-SHA384, set the PSK maximum length to 48 instead of 32. + * That way, the TLS 1.3 client and server are able to resume sessions where + * the cipher suite is TLS1-3-AES-256-GCM-SHA384 (pre-shared keys are 48 + * bytes long in that case). + */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ + defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_AES_C) && defined(MBEDTLS_GCM_C) && \ + defined(MBEDTLS_MD_CAN_SHA384) +#define MBEDTLS_PSK_MAX_LEN 48 /* 384 bits */ +#else +#define MBEDTLS_PSK_MAX_LEN 32 /* 256 bits */ +#endif +#endif /* !MBEDTLS_PSK_MAX_LEN */ + +/* Dummy type used only for its size */ +union mbedtls_ssl_premaster_secret { + unsigned char dummy; /* Make the union non-empty even with SSL disabled */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) + unsigned char _pms_rsa[48]; /* RFC 5246 8.1.1 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) + unsigned char _pms_dhm[MBEDTLS_MPI_MAX_SIZE]; /* RFC 5246 8.1.2 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) + unsigned char _pms_ecdh[MBEDTLS_ECP_MAX_BYTES]; /* RFC 4492 5.10 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) + unsigned char _pms_psk[4 + 2 * MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 2 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) + unsigned char _pms_dhe_psk[4 + MBEDTLS_MPI_MAX_SIZE + + MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 3 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) + unsigned char _pms_rsa_psk[52 + MBEDTLS_PSK_MAX_LEN]; /* RFC 4279 4 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) + unsigned char _pms_ecdhe_psk[4 + MBEDTLS_ECP_MAX_BYTES + + MBEDTLS_PSK_MAX_LEN]; /* RFC 5489 2 */ +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) + unsigned char _pms_ecjpake[32]; /* Thread spec: SHA-256 output */ +#endif +}; + +#define MBEDTLS_PREMASTER_SIZE sizeof(union mbedtls_ssl_premaster_secret) + +#define MBEDTLS_TLS1_3_MD_MAX_SIZE PSA_HASH_MAX_SIZE + + +/* Length in number of bytes of the TLS sequence number */ +#define MBEDTLS_SSL_SEQUENCE_NUMBER_LEN 8 + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * SSL state machine + */ +typedef enum { + MBEDTLS_SSL_HELLO_REQUEST, + MBEDTLS_SSL_CLIENT_HELLO, + MBEDTLS_SSL_SERVER_HELLO, + MBEDTLS_SSL_SERVER_CERTIFICATE, + MBEDTLS_SSL_SERVER_KEY_EXCHANGE, + MBEDTLS_SSL_CERTIFICATE_REQUEST, + MBEDTLS_SSL_SERVER_HELLO_DONE, + MBEDTLS_SSL_CLIENT_CERTIFICATE, + MBEDTLS_SSL_CLIENT_KEY_EXCHANGE, + MBEDTLS_SSL_CERTIFICATE_VERIFY, + MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC, + MBEDTLS_SSL_CLIENT_FINISHED, + MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC, + MBEDTLS_SSL_SERVER_FINISHED, + MBEDTLS_SSL_FLUSH_BUFFERS, + MBEDTLS_SSL_HANDSHAKE_WRAPUP, + + MBEDTLS_SSL_NEW_SESSION_TICKET, + MBEDTLS_SSL_SERVER_HELLO_VERIFY_REQUEST_SENT, + MBEDTLS_SSL_HELLO_RETRY_REQUEST, + MBEDTLS_SSL_ENCRYPTED_EXTENSIONS, + MBEDTLS_SSL_END_OF_EARLY_DATA, + MBEDTLS_SSL_CLIENT_CERTIFICATE_VERIFY, + MBEDTLS_SSL_CLIENT_CCS_AFTER_SERVER_FINISHED, + MBEDTLS_SSL_CLIENT_CCS_BEFORE_2ND_CLIENT_HELLO, + MBEDTLS_SSL_SERVER_CCS_AFTER_SERVER_HELLO, + MBEDTLS_SSL_CLIENT_CCS_AFTER_CLIENT_HELLO, + MBEDTLS_SSL_SERVER_CCS_AFTER_HELLO_RETRY_REQUEST, + MBEDTLS_SSL_HANDSHAKE_OVER, + MBEDTLS_SSL_TLS1_3_NEW_SESSION_TICKET, + MBEDTLS_SSL_TLS1_3_NEW_SESSION_TICKET_FLUSH, +} +mbedtls_ssl_states; + +/** + * \brief Callback type: send data on the network. + * + * \note That callback may be either blocking or non-blocking. + * + * \param ctx Context for the send callback (typically a file descriptor) + * \param buf Buffer holding the data to send + * \param len Length of the data to send + * + * \return The callback must return the number of bytes sent if any, + * or a non-zero error code. + * If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_WRITE + * must be returned when the operation would block. + * + * \note The callback is allowed to send fewer bytes than requested. + * It must always return the number of bytes actually sent. + */ +typedef int mbedtls_ssl_send_t(void *ctx, + const unsigned char *buf, + size_t len); + +/** + * \brief Callback type: receive data from the network. + * + * \note That callback may be either blocking or non-blocking. + * + * \param ctx Context for the receive callback (typically a file + * descriptor) + * \param buf Buffer to write the received data to + * \param len Length of the receive buffer + * + * \returns If data has been received, the positive number of bytes received. + * \returns \c 0 if the connection has been closed. + * \returns If performing non-blocking I/O, \c MBEDTLS_ERR_SSL_WANT_READ + * must be returned when the operation would block. + * \returns Another negative error code on other kinds of failures. + * + * \note The callback may receive fewer bytes than the length of the + * buffer. It must always return the number of bytes actually + * received and written to the buffer. + */ +typedef int mbedtls_ssl_recv_t(void *ctx, + unsigned char *buf, + size_t len); + +/** + * \brief Callback type: receive data from the network, with timeout + * + * \note That callback must block until data is received, or the + * timeout delay expires, or the operation is interrupted by a + * signal. + * + * \param ctx Context for the receive callback (typically a file descriptor) + * \param buf Buffer to write the received data to + * \param len Length of the receive buffer + * \param timeout Maximum number of milliseconds to wait for data + * 0 means no timeout (potentially waiting forever) + * + * \return The callback must return the number of bytes received, + * or a non-zero error code: + * \c MBEDTLS_ERR_SSL_TIMEOUT if the operation timed out, + * \c MBEDTLS_ERR_SSL_WANT_READ if interrupted by a signal. + * + * \note The callback may receive fewer bytes than the length of the + * buffer. It must always return the number of bytes actually + * received and written to the buffer. + */ +typedef int mbedtls_ssl_recv_timeout_t(void *ctx, + unsigned char *buf, + size_t len, + uint32_t timeout); +/** + * \brief Callback type: set a pair of timers/delays to watch + * + * \param ctx Context pointer + * \param int_ms Intermediate delay in milliseconds + * \param fin_ms Final delay in milliseconds + * 0 cancels the current timer. + * + * \note This callback must at least store the necessary information + * for the associated \c mbedtls_ssl_get_timer_t callback to + * return correct information. + * + * \note If using an event-driven style of programming, an event must + * be generated when the final delay is passed. The event must + * cause a call to \c mbedtls_ssl_handshake() with the proper + * SSL context to be scheduled. Care must be taken to ensure + * that at most one such call happens at a time. + * + * \note Only one timer at a time must be running. Calling this + * function while a timer is running must cancel it. Cancelled + * timers must not generate any event. + */ +typedef void mbedtls_ssl_set_timer_t(void *ctx, + uint32_t int_ms, + uint32_t fin_ms); + +/** + * \brief Callback type: get status of timers/delays + * + * \param ctx Context pointer + * + * \return This callback must return: + * -1 if cancelled (fin_ms == 0), + * 0 if none of the delays have passed, + * 1 if only the intermediate delay has passed, + * 2 if the final delay has passed. + */ +typedef int mbedtls_ssl_get_timer_t(void *ctx); + +/* Defined below */ +typedef struct mbedtls_ssl_session mbedtls_ssl_session; +typedef struct mbedtls_ssl_context mbedtls_ssl_context; +typedef struct mbedtls_ssl_config mbedtls_ssl_config; + +/* Defined in library/ssl_misc.h */ +typedef struct mbedtls_ssl_transform mbedtls_ssl_transform; +typedef struct mbedtls_ssl_handshake_params mbedtls_ssl_handshake_params; +typedef struct mbedtls_ssl_sig_hash_set_t mbedtls_ssl_sig_hash_set_t; +#if defined(MBEDTLS_X509_CRT_PARSE_C) +typedef struct mbedtls_ssl_key_cert mbedtls_ssl_key_cert; +#endif +#if defined(MBEDTLS_SSL_PROTO_DTLS) +typedef struct mbedtls_ssl_flight_item mbedtls_ssl_flight_item; +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_RESUMPTION \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK /* 1U << 0 */ +#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_EPHEMERAL_RESUMPTION \ + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL /* 1U << 2 */ +#define MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_EARLY_DATA (1U << 3) + +#define MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK \ + (MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_RESUMPTION | \ + MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_PSK_EPHEMERAL_RESUMPTION | \ + MBEDTLS_SSL_TLS1_3_TICKET_ALLOW_EARLY_DATA) +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ + +/** + * \brief Callback type: server-side session cache getter + * + * The session cache is logically a key value store, with + * keys being session IDs and values being instances of + * mbedtls_ssl_session. + * + * This callback retrieves an entry in this key-value store. + * + * \param data The address of the session cache structure to query. + * \param session_id The buffer holding the session ID to query. + * \param session_id_len The length of \p session_id in Bytes. + * \param session The address of the session structure to populate. + * It is initialized with mbdtls_ssl_session_init(), + * and the callback must always leave it in a state + * where it can safely be freed via + * mbedtls_ssl_session_free() independent of the + * return code of this function. + * + * \return \c 0 on success + * \return A non-zero return value on failure. + * + */ +typedef int mbedtls_ssl_cache_get_t(void *data, + unsigned char const *session_id, + size_t session_id_len, + mbedtls_ssl_session *session); +/** + * \brief Callback type: server-side session cache setter + * + * The session cache is logically a key value store, with + * keys being session IDs and values being instances of + * mbedtls_ssl_session. + * + * This callback sets an entry in this key-value store. + * + * \param data The address of the session cache structure to modify. + * \param session_id The buffer holding the session ID to query. + * \param session_id_len The length of \p session_id in Bytes. + * \param session The address of the session to be stored in the + * session cache. + * + * \return \c 0 on success + * \return A non-zero return value on failure. + */ +typedef int mbedtls_ssl_cache_set_t(void *data, + unsigned char const *session_id, + size_t session_id_len, + const mbedtls_ssl_session *session); + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Callback type: start external signature operation. + * + * This callback is called during an SSL handshake to start + * a signature decryption operation using an + * external processor. The parameter \p cert contains + * the public key; it is up to the callback function to + * determine how to access the associated private key. + * + * This function typically sends or enqueues a request, and + * does not wait for the operation to complete. This allows + * the handshake step to be non-blocking. + * + * The parameters \p ssl and \p cert are guaranteed to remain + * valid throughout the handshake. On the other hand, this + * function must save the contents of \p hash if the value + * is needed for later processing, because the \p hash buffer + * is no longer valid after this function returns. + * + * This function may call mbedtls_ssl_set_async_operation_data() + * to store an operation context for later retrieval + * by the resume or cancel callback. + * + * \note For RSA signatures, this function must produce output + * that is consistent with PKCS#1 v1.5 in the same way as + * mbedtls_rsa_pkcs1_sign(). Before the private key operation, + * apply the padding steps described in RFC 8017, section 9.2 + * "EMSA-PKCS1-v1_5" as follows. + * - If \p md_alg is #MBEDTLS_MD_NONE, apply the PKCS#1 v1.5 + * encoding, treating \p hash as the DigestInfo to be + * padded. In other words, apply EMSA-PKCS1-v1_5 starting + * from step 3, with `T = hash` and `tLen = hash_len`. + * - If `md_alg != MBEDTLS_MD_NONE`, apply the PKCS#1 v1.5 + * encoding, treating \p hash as the hash to be encoded and + * padded. In other words, apply EMSA-PKCS1-v1_5 starting + * from step 2, with `digestAlgorithm` obtained by calling + * mbedtls_oid_get_oid_by_md() on \p md_alg. + * + * \note For ECDSA signatures, the output format is the DER encoding + * `Ecdsa-Sig-Value` defined in + * [RFC 4492 section 5.4](https://tools.ietf.org/html/rfc4492#section-5.4). + * + * \param ssl The SSL connection instance. It should not be + * modified other than via + * mbedtls_ssl_set_async_operation_data(). + * \param cert Certificate containing the public key. + * In simple cases, this is one of the pointers passed to + * mbedtls_ssl_conf_own_cert() when configuring the SSL + * connection. However, if other callbacks are used, this + * property may not hold. For example, if an SNI callback + * is registered with mbedtls_ssl_conf_sni(), then + * this callback determines what certificate is used. + * \param md_alg Hash algorithm. + * \param hash Buffer containing the hash. This buffer is + * no longer valid when the function returns. + * \param hash_len Size of the \c hash buffer in bytes. + * + * \return 0 if the operation was started successfully and the SSL + * stack should call the resume callback immediately. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation + * was started successfully and the SSL stack should return + * immediately without calling the resume callback yet. + * \return #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external + * processor does not support this key. The SSL stack will + * use the private key object instead. + * \return Any other error indicates a fatal failure and is + * propagated up the call chain. The callback should + * use \c MBEDTLS_ERR_PK_xxx error codes, and must not + * use \c MBEDTLS_ERR_SSL_xxx error codes except as + * directed in the documentation of this callback. + */ +typedef int mbedtls_ssl_async_sign_t(mbedtls_ssl_context *ssl, + mbedtls_x509_crt *cert, + mbedtls_md_type_t md_alg, + const unsigned char *hash, + size_t hash_len); + +/** + * \brief Callback type: start external decryption operation. + * + * This callback is called during an SSL handshake to start + * an RSA decryption operation using an + * external processor. The parameter \p cert contains + * the public key; it is up to the callback function to + * determine how to access the associated private key. + * + * This function typically sends or enqueues a request, and + * does not wait for the operation to complete. This allows + * the handshake step to be non-blocking. + * + * The parameters \p ssl and \p cert are guaranteed to remain + * valid throughout the handshake. On the other hand, this + * function must save the contents of \p input if the value + * is needed for later processing, because the \p input buffer + * is no longer valid after this function returns. + * + * This function may call mbedtls_ssl_set_async_operation_data() + * to store an operation context for later retrieval + * by the resume or cancel callback. + * + * \warning RSA decryption as used in TLS is subject to a potential + * timing side channel attack first discovered by Bleichenbacher + * in 1998. This attack can be remotely exploitable + * in practice. To avoid this attack, you must ensure that + * if the callback performs an RSA decryption, the time it + * takes to execute and return the result does not depend + * on whether the RSA decryption succeeded or reported + * invalid padding. + * + * \param ssl The SSL connection instance. It should not be + * modified other than via + * mbedtls_ssl_set_async_operation_data(). + * \param cert Certificate containing the public key. + * In simple cases, this is one of the pointers passed to + * mbedtls_ssl_conf_own_cert() when configuring the SSL + * connection. However, if other callbacks are used, this + * property may not hold. For example, if an SNI callback + * is registered with mbedtls_ssl_conf_sni(), then + * this callback determines what certificate is used. + * \param input Buffer containing the input ciphertext. This buffer + * is no longer valid when the function returns. + * \param input_len Size of the \p input buffer in bytes. + * + * \return 0 if the operation was started successfully and the SSL + * stack should call the resume callback immediately. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation + * was started successfully and the SSL stack should return + * immediately without calling the resume callback yet. + * \return #MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH if the external + * processor does not support this key. The SSL stack will + * use the private key object instead. + * \return Any other error indicates a fatal failure and is + * propagated up the call chain. The callback should + * use \c MBEDTLS_ERR_PK_xxx error codes, and must not + * use \c MBEDTLS_ERR_SSL_xxx error codes except as + * directed in the documentation of this callback. + */ +typedef int mbedtls_ssl_async_decrypt_t(mbedtls_ssl_context *ssl, + mbedtls_x509_crt *cert, + const unsigned char *input, + size_t input_len); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/** + * \brief Callback type: resume external operation. + * + * This callback is called during an SSL handshake to resume + * an external operation started by the + * ::mbedtls_ssl_async_sign_t or + * ::mbedtls_ssl_async_decrypt_t callback. + * + * This function typically checks the status of a pending + * request or causes the request queue to make progress, and + * does not wait for the operation to complete. This allows + * the handshake step to be non-blocking. + * + * This function may call mbedtls_ssl_get_async_operation_data() + * to retrieve an operation context set by the start callback. + * It may call mbedtls_ssl_set_async_operation_data() to modify + * this context. + * + * Note that when this function returns a status other than + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, it must free any + * resources associated with the operation. + * + * \param ssl The SSL connection instance. It should not be + * modified other than via + * mbedtls_ssl_set_async_operation_data(). + * \param output Buffer containing the output (signature or decrypted + * data) on success. + * \param output_len On success, number of bytes written to \p output. + * \param output_size Size of the \p output buffer in bytes. + * + * \return 0 if output of the operation is available in the + * \p output buffer. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if the operation + * is still in progress. Subsequent requests for progress + * on the SSL connection will call the resume callback + * again. + * \return Any other error means that the operation is aborted. + * The SSL handshake is aborted. The callback should + * use \c MBEDTLS_ERR_PK_xxx error codes, and must not + * use \c MBEDTLS_ERR_SSL_xxx error codes except as + * directed in the documentation of this callback. + */ +typedef int mbedtls_ssl_async_resume_t(mbedtls_ssl_context *ssl, + unsigned char *output, + size_t *output_len, + size_t output_size); + +/** + * \brief Callback type: cancel external operation. + * + * This callback is called if an SSL connection is closed + * while an asynchronous operation is in progress. Note that + * this callback is not called if the + * ::mbedtls_ssl_async_resume_t callback has run and has + * returned a value other than + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, since in that case + * the asynchronous operation has already completed. + * + * This function may call mbedtls_ssl_get_async_operation_data() + * to retrieve an operation context set by the start callback. + * + * \param ssl The SSL connection instance. It should not be + * modified. + */ +typedef void mbedtls_ssl_async_cancel_t(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ + +#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) && \ + !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) +#define MBEDTLS_SSL_PEER_CERT_DIGEST_MAX_LEN 48 +#if defined(MBEDTLS_MD_CAN_SHA256) +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA256 +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 32 +#elif defined(MBEDTLS_MD_CAN_SHA384) +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA384 +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 48 +#elif defined(MBEDTLS_MD_CAN_SHA1) +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_TYPE MBEDTLS_MD_SHA1 +#define MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN 20 +#else +/* This is already checked in check_config.h, but be sure. */ +#error "Bad configuration - need SHA-1, SHA-256 or SHA-512 enabled to compute digest of peer CRT." +#endif +#endif /* MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED && + !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ + +typedef struct { + unsigned char client_application_traffic_secret_N[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char server_application_traffic_secret_N[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char exporter_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char resumption_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; +} mbedtls_ssl_tls13_application_secrets; + +#if defined(MBEDTLS_SSL_DTLS_SRTP) + +#define MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH 255 +#define MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH 4 +/* + * For code readability use a typedef for DTLS-SRTP profiles + * + * Use_srtp extension protection profiles values as defined in + * http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml + * + * Reminder: if this list is expanded mbedtls_ssl_check_srtp_profile_value + * must be updated too. + */ +#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80 ((uint16_t) 0x0001) +#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32 ((uint16_t) 0x0002) +#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80 ((uint16_t) 0x0005) +#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32 ((uint16_t) 0x0006) +/* This one is not iana defined, but for code readability. */ +#define MBEDTLS_TLS_SRTP_UNSET ((uint16_t) 0x0000) + +typedef uint16_t mbedtls_ssl_srtp_profile; + +typedef struct mbedtls_dtls_srtp_info_t { + /*! The SRTP profile that was negotiated. */ + mbedtls_ssl_srtp_profile MBEDTLS_PRIVATE(chosen_dtls_srtp_profile); + /*! The length of mki_value. */ + uint16_t MBEDTLS_PRIVATE(mki_len); + /*! The mki_value used, with max size of 256 bytes. */ + unsigned char MBEDTLS_PRIVATE(mki_value)[MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH]; +} +mbedtls_dtls_srtp_info; + +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + +/** Human-friendly representation of the (D)TLS protocol version. */ +typedef enum { + MBEDTLS_SSL_VERSION_UNKNOWN, /*!< Context not in use or version not yet negotiated. */ + MBEDTLS_SSL_VERSION_TLS1_2 = 0x0303, /*!< (D)TLS 1.2 */ + MBEDTLS_SSL_VERSION_TLS1_3 = 0x0304, /*!< (D)TLS 1.3 */ +} mbedtls_ssl_protocol_version; + +/* + * This structure is used for storing current session data. + * + * Note: when changing this definition, we need to check and update: + * - in tests/suites/test_suite_ssl.function: + * ssl_populate_session() and ssl_serialize_session_save_load() + * - in library/ssl_tls.c: + * mbedtls_ssl_session_init() and mbedtls_ssl_session_free() + * mbedtls_ssl_session_save() and ssl_session_load() + * ssl_session_copy() + */ +struct mbedtls_ssl_session { +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + unsigned char MBEDTLS_PRIVATE(mfl_code); /*!< MaxFragmentLength negotiated by peer */ +#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ + + unsigned char MBEDTLS_PRIVATE(exported); + + /** TLS version negotiated in the session. Used if and when renegotiating + * or resuming a session instead of the configured minor TLS version. + */ + mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(tls_version); + +#if defined(MBEDTLS_HAVE_TIME) + mbedtls_time_t MBEDTLS_PRIVATE(start); /*!< starting time */ +#endif + int MBEDTLS_PRIVATE(ciphersuite); /*!< chosen ciphersuite */ + size_t MBEDTLS_PRIVATE(id_len); /*!< session id length */ + unsigned char MBEDTLS_PRIVATE(id)[32]; /*!< session identifier */ + unsigned char MBEDTLS_PRIVATE(master)[48]; /*!< the master secret */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +#if defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) + mbedtls_x509_crt *MBEDTLS_PRIVATE(peer_cert); /*!< peer X.509 cert chain */ +#else /* MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ + /*! The digest of the peer's end-CRT. This must be kept to detect CRT + * changes during renegotiation, mitigating the triple handshake attack. */ + unsigned char *MBEDTLS_PRIVATE(peer_cert_digest); + size_t MBEDTLS_PRIVATE(peer_cert_digest_len); + mbedtls_md_type_t MBEDTLS_PRIVATE(peer_cert_digest_type); +#endif /* !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + uint32_t MBEDTLS_PRIVATE(verify_result); /*!< verification result */ + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_CLI_C) + unsigned char *MBEDTLS_PRIVATE(ticket); /*!< RFC 5077 session ticket */ + size_t MBEDTLS_PRIVATE(ticket_len); /*!< session ticket length */ + uint32_t MBEDTLS_PRIVATE(ticket_lifetime); /*!< ticket lifetime hint */ +#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) + uint8_t MBEDTLS_PRIVATE(endpoint); /*!< 0: client, 1: server */ + uint8_t MBEDTLS_PRIVATE(ticket_flags); /*!< Ticket flags */ + uint32_t MBEDTLS_PRIVATE(ticket_age_add); /*!< Randomly generated value used to obscure the age of the ticket */ + uint8_t MBEDTLS_PRIVATE(resumption_key_len); /*!< resumption_key length */ + unsigned char MBEDTLS_PRIVATE(resumption_key)[MBEDTLS_SSL_TLS1_3_TICKET_RESUMPTION_KEY_LEN]; + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && defined(MBEDTLS_SSL_CLI_C) + char *MBEDTLS_PRIVATE(hostname); /*!< host name binded with tickets */ +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION && MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_HAVE_TIME) && defined(MBEDTLS_SSL_CLI_C) + mbedtls_time_t MBEDTLS_PRIVATE(ticket_received); /*!< time ticket was received */ +#endif /* MBEDTLS_HAVE_TIME && MBEDTLS_SSL_CLI_C */ + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + int MBEDTLS_PRIVATE(encrypt_then_mac); /*!< flag for EtM activation */ +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + mbedtls_ssl_tls13_application_secrets MBEDTLS_PRIVATE(app_secrets); +#endif +}; + +/* + * Identifiers for PRFs used in various versions of TLS. + */ +typedef enum { + MBEDTLS_SSL_TLS_PRF_NONE, + MBEDTLS_SSL_TLS_PRF_SHA384, + MBEDTLS_SSL_TLS_PRF_SHA256, + MBEDTLS_SSL_HKDF_EXPAND_SHA384, + MBEDTLS_SSL_HKDF_EXPAND_SHA256 +} +mbedtls_tls_prf_types; + +typedef enum { + MBEDTLS_SSL_KEY_EXPORT_TLS12_MASTER_SECRET = 0, +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_EARLY_SECRET, + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_EARLY_EXPORTER_SECRET, + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_HANDSHAKE_TRAFFIC_SECRET, + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_SERVER_HANDSHAKE_TRAFFIC_SECRET, + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_CLIENT_APPLICATION_TRAFFIC_SECRET, + MBEDTLS_SSL_KEY_EXPORT_TLS1_3_SERVER_APPLICATION_TRAFFIC_SECRET, +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ +} mbedtls_ssl_key_export_type; + +/** + * \brief Callback type: Export key alongside random values for + * session identification, and PRF for + * implementation of TLS key exporters. + * + * \param p_expkey Context for the callback. + * \param type The type of the key that is being exported. + * \param secret The address of the buffer holding the secret + * that's being exporterd. + * \param secret_len The length of \p secret in bytes. + * \param client_random The client random bytes. + * \param server_random The server random bytes. + * \param tls_prf_type The identifier for the PRF used in the handshake + * to which the key belongs. + */ +typedef void mbedtls_ssl_export_keys_t(void *p_expkey, + mbedtls_ssl_key_export_type type, + const unsigned char *secret, + size_t secret_len, + const unsigned char client_random[32], + const unsigned char server_random[32], + mbedtls_tls_prf_types tls_prf_type); + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Callback type: generic handshake callback + * + * \note Callbacks may use user_data funcs to set/get app user data. + * See \c mbedtls_ssl_get_user_data_p() + * \c mbedtls_ssl_get_user_data_n() + * \c mbedtls_ssl_conf_get_user_data_p() + * \c mbedtls_ssl_conf_get_user_data_n() + * + * \param ssl \c mbedtls_ssl_context on which the callback is run + * + * \return The return value of the callback is 0 if successful, + * or a specific MBEDTLS_ERR_XXX code, which will cause + * the handshake to be aborted. + */ +typedef int (*mbedtls_ssl_hs_cb_t)(mbedtls_ssl_context *ssl); +#endif + +/* A type for storing user data in a library structure. + * + * The representation of type may change in future versions of the library. + * Only the behaviors guaranteed by documented accessor functions are + * guaranteed to remain stable. + */ +typedef union { + uintptr_t n; /* typically a handle to an associated object */ + void *p; /* typically a pointer to extra data */ +} mbedtls_ssl_user_data_t; + +/** + * SSL/TLS configuration to be shared between mbedtls_ssl_context structures. + */ +struct mbedtls_ssl_config { + /* Group items mostly by size. This helps to reduce memory wasted to + * padding. It also helps to keep smaller fields early in the structure, + * so that elements tend to be in the 128-element direct access window + * on Arm Thumb, which reduces the code size. */ + + mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(max_tls_version); /*!< max. TLS version used */ + mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(min_tls_version); /*!< min. TLS version used */ + + /* + * Flags (could be bit-fields to save RAM, but separate bytes make + * the code smaller on architectures with an instruction for direct + * byte access). + */ + + uint8_t MBEDTLS_PRIVATE(endpoint); /*!< 0: client, 1: server */ + uint8_t MBEDTLS_PRIVATE(transport); /*!< 0: stream (TLS), 1: datagram (DTLS) */ + uint8_t MBEDTLS_PRIVATE(authmode); /*!< MBEDTLS_SSL_VERIFY_XXX */ + /* needed even with renego disabled for LEGACY_BREAK_HANDSHAKE */ + uint8_t MBEDTLS_PRIVATE(allow_legacy_renegotiation); /*!< MBEDTLS_LEGACY_XXX */ +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + uint8_t MBEDTLS_PRIVATE(mfl_code); /*!< desired fragment length indicator + (MBEDTLS_SSL_MAX_FRAG_LEN_XXX) */ +#endif +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + uint8_t MBEDTLS_PRIVATE(encrypt_then_mac); /*!< negotiate encrypt-then-mac? */ +#endif +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) + uint8_t MBEDTLS_PRIVATE(extended_ms); /*!< negotiate extended master secret? */ +#endif +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + uint8_t MBEDTLS_PRIVATE(anti_replay); /*!< detect and prevent replay? */ +#endif +#if defined(MBEDTLS_SSL_RENEGOTIATION) + uint8_t MBEDTLS_PRIVATE(disable_renegotiation); /*!< disable renegotiation? */ +#endif +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_SSL_CLI_C) + uint8_t MBEDTLS_PRIVATE(session_tickets); /*!< use session tickets? */ +#endif + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_SSL_SRV_C) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_3) + uint16_t MBEDTLS_PRIVATE(new_session_tickets_count); /*!< number of NewSessionTicket */ +#endif + +#if defined(MBEDTLS_SSL_SRV_C) + uint8_t MBEDTLS_PRIVATE(cert_req_ca_list); /*!< enable sending CA list in + Certificate Request messages? */ + uint8_t MBEDTLS_PRIVATE(respect_cli_pref); /*!< pick the ciphersuite according to + the client's preferences rather + than ours? */ +#endif +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + uint8_t MBEDTLS_PRIVATE(ignore_unexpected_cid); /*!< Should DTLS record with + * unexpected CID + * lead to failure? */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + uint8_t MBEDTLS_PRIVATE(dtls_srtp_mki_support); /* support having mki_value + in the use_srtp extension? */ +#endif + + /* + * Pointers + */ + + /** Allowed ciphersuites for (D)TLS 1.2 (0-terminated) */ + const int *MBEDTLS_PRIVATE(ciphersuite_list); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + /** Allowed TLS 1.3 key exchange modes. */ + int MBEDTLS_PRIVATE(tls13_kex_modes); +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + + /** Callback for printing debug output */ + void(*MBEDTLS_PRIVATE(f_dbg))(void *, int, const char *, int, const char *); + void *MBEDTLS_PRIVATE(p_dbg); /*!< context for the debug function */ + + /** Callback for getting (pseudo-)random numbers */ + int(*MBEDTLS_PRIVATE(f_rng))(void *, unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_rng); /*!< context for the RNG function */ + + /** Callback to retrieve a session from the cache */ + mbedtls_ssl_cache_get_t *MBEDTLS_PRIVATE(f_get_cache); + /** Callback to store a session into the cache */ + mbedtls_ssl_cache_set_t *MBEDTLS_PRIVATE(f_set_cache); + void *MBEDTLS_PRIVATE(p_cache); /*!< context for cache callbacks */ + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) + /** Callback for setting cert according to SNI extension */ + int(*MBEDTLS_PRIVATE(f_sni))(void *, mbedtls_ssl_context *, const unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_sni); /*!< context for SNI callback */ +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + /** Callback to customize X.509 certificate chain verification */ + int(*MBEDTLS_PRIVATE(f_vrfy))(void *, mbedtls_x509_crt *, int, uint32_t *); + void *MBEDTLS_PRIVATE(p_vrfy); /*!< context for X.509 verify calllback */ +#endif + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) +#if defined(MBEDTLS_SSL_SRV_C) + /** Callback to retrieve PSK key from identity */ + int(*MBEDTLS_PRIVATE(f_psk))(void *, mbedtls_ssl_context *, const unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_psk); /*!< context for PSK callback */ +#endif +#endif + +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) + /** Callback to create & write a cookie for ClientHello verification */ + int(*MBEDTLS_PRIVATE(f_cookie_write))(void *, unsigned char **, unsigned char *, + const unsigned char *, size_t); + /** Callback to verify validity of a ClientHello cookie */ + int(*MBEDTLS_PRIVATE(f_cookie_check))(void *, const unsigned char *, size_t, + const unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_cookie); /*!< context for the cookie callbacks */ +#endif + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C) + /** Callback to create & write a session ticket */ + int(*MBEDTLS_PRIVATE(f_ticket_write))(void *, const mbedtls_ssl_session *, + unsigned char *, const unsigned char *, size_t *, + uint32_t *); + /** Callback to parse a session ticket into a session structure */ + int(*MBEDTLS_PRIVATE(f_ticket_parse))(void *, mbedtls_ssl_session *, unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_ticket); /*!< context for the ticket callbacks */ +#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + size_t MBEDTLS_PRIVATE(cid_len); /*!< The length of CIDs for incoming DTLS records. */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + const mbedtls_x509_crt_profile *MBEDTLS_PRIVATE(cert_profile); /*!< verification profile */ + mbedtls_ssl_key_cert *MBEDTLS_PRIVATE(key_cert); /*!< own certificate/key pair(s) */ + mbedtls_x509_crt *MBEDTLS_PRIVATE(ca_chain); /*!< trusted CAs */ + mbedtls_x509_crl *MBEDTLS_PRIVATE(ca_crl); /*!< trusted CAs CRLs */ +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) + mbedtls_x509_crt_ca_cb_t MBEDTLS_PRIVATE(f_ca_cb); + void *MBEDTLS_PRIVATE(p_ca_cb); +#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) +#if defined(MBEDTLS_X509_CRT_PARSE_C) + mbedtls_ssl_async_sign_t *MBEDTLS_PRIVATE(f_async_sign_start); /*!< start asynchronous signature operation */ + mbedtls_ssl_async_decrypt_t *MBEDTLS_PRIVATE(f_async_decrypt_start); /*!< start asynchronous decryption operation */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + mbedtls_ssl_async_resume_t *MBEDTLS_PRIVATE(f_async_resume); /*!< resume asynchronous operation */ + mbedtls_ssl_async_cancel_t *MBEDTLS_PRIVATE(f_async_cancel); /*!< cancel asynchronous operation */ + void *MBEDTLS_PRIVATE(p_async_config_data); /*!< Configuration data set by mbedtls_ssl_conf_async_private_cb(). */ +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + const int *MBEDTLS_PRIVATE(sig_hashes); /*!< allowed signature hashes */ +#endif + const uint16_t *MBEDTLS_PRIVATE(sig_algs); /*!< allowed signature algorithms */ +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + +#if defined(MBEDTLS_ECP_C) && !defined(MBEDTLS_DEPRECATED_REMOVED) + const mbedtls_ecp_group_id *MBEDTLS_PRIVATE(curve_list); /*!< allowed curves */ +#endif + + const uint16_t *MBEDTLS_PRIVATE(group_list); /*!< allowed IANA NamedGroups */ + +#if defined(MBEDTLS_DHM_C) + mbedtls_mpi MBEDTLS_PRIVATE(dhm_P); /*!< prime modulus for DHM */ + mbedtls_mpi MBEDTLS_PRIVATE(dhm_G); /*!< generator for DHM */ +#endif + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) + +#if defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_svc_key_id_t MBEDTLS_PRIVATE(psk_opaque); /*!< PSA key slot holding opaque PSK. This field + * should only be set via + * mbedtls_ssl_conf_psk_opaque(). + * If either no PSK or a raw PSK have been + * configured, this has value \c 0. + */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + unsigned char *MBEDTLS_PRIVATE(psk); /*!< The raw pre-shared key. This field should + * only be set via mbedtls_ssl_conf_psk(). + * If either no PSK or an opaque PSK + * have been configured, this has value NULL. */ + size_t MBEDTLS_PRIVATE(psk_len); /*!< The length of the raw pre-shared key. + * This field should only be set via + * mbedtls_ssl_conf_psk(). + * Its value is non-zero if and only if + * \c psk is not \c NULL. */ + + unsigned char *MBEDTLS_PRIVATE(psk_identity); /*!< The PSK identity for PSK negotiation. + * This field should only be set via + * mbedtls_ssl_conf_psk(). + * This is set if and only if either + * \c psk or \c psk_opaque are set. */ + size_t MBEDTLS_PRIVATE(psk_identity_len);/*!< The length of PSK identity. + * This field should only be set via + * mbedtls_ssl_conf_psk(). + * Its value is non-zero if and only if + * \c psk is not \c NULL or \c psk_opaque + * is not \c 0. */ +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ + +#if defined(MBEDTLS_SSL_EARLY_DATA) + int MBEDTLS_PRIVATE(early_data_enabled); /*!< Early data enablement: + * - MBEDTLS_SSL_EARLY_DATA_DISABLED, + * - MBEDTLS_SSL_EARLY_DATA_ENABLED */ + +#if defined(MBEDTLS_SSL_SRV_C) + /* The maximum amount of 0-RTT data. RFC 8446 section 4.6.1 */ + uint32_t MBEDTLS_PRIVATE(max_early_data_size); +#endif /* MBEDTLS_SSL_SRV_C */ + +#endif /* MBEDTLS_SSL_EARLY_DATA */ + +#if defined(MBEDTLS_SSL_ALPN) + const char **MBEDTLS_PRIVATE(alpn_list); /*!< ordered list of protocols */ +#endif + +#if defined(MBEDTLS_SSL_DTLS_SRTP) + /*! ordered list of supported srtp profile */ + const mbedtls_ssl_srtp_profile *MBEDTLS_PRIVATE(dtls_srtp_profile_list); + /*! number of supported profiles */ + size_t MBEDTLS_PRIVATE(dtls_srtp_profile_list_len); +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + + /* + * Numerical settings (int) + */ + + uint32_t MBEDTLS_PRIVATE(read_timeout); /*!< timeout for mbedtls_ssl_read (ms) */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + uint32_t MBEDTLS_PRIVATE(hs_timeout_min); /*!< initial value of the handshake + retransmission timeout (ms) */ + uint32_t MBEDTLS_PRIVATE(hs_timeout_max); /*!< maximum value of the handshake + retransmission timeout (ms) */ +#endif + +#if defined(MBEDTLS_SSL_RENEGOTIATION) + int MBEDTLS_PRIVATE(renego_max_records); /*!< grace period for renegotiation */ + unsigned char MBEDTLS_PRIVATE(renego_period)[8]; /*!< value of the record counters + that triggers renegotiation */ +#endif + + unsigned int MBEDTLS_PRIVATE(badmac_limit); /*!< limit of records with a bad MAC */ + +#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C) + unsigned int MBEDTLS_PRIVATE(dhm_min_bitlen); /*!< min. bit length of the DHM prime */ +#endif + + /** User data pointer or handle. + * + * The library sets this to \p 0 when creating a context and does not + * access it afterwards. + */ + mbedtls_ssl_user_data_t MBEDTLS_PRIVATE(user_data); + +#if defined(MBEDTLS_SSL_SRV_C) + mbedtls_ssl_hs_cb_t MBEDTLS_PRIVATE(f_cert_cb); /*!< certificate selection callback */ +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) + const mbedtls_x509_crt *MBEDTLS_PRIVATE(dn_hints);/*!< acceptable client cert issuers */ +#endif +}; + +struct mbedtls_ssl_context { + const mbedtls_ssl_config *MBEDTLS_PRIVATE(conf); /*!< configuration information */ + + /* + * Miscellaneous + */ + int MBEDTLS_PRIVATE(state); /*!< SSL handshake: current state */ +#if defined(MBEDTLS_SSL_RENEGOTIATION) + int MBEDTLS_PRIVATE(renego_status); /*!< Initial, in progress, pending? */ + int MBEDTLS_PRIVATE(renego_records_seen); /*!< Records since renego request, or with DTLS, + number of retransmissions of request if + renego_max_records is < 0 */ +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + + /** + * Maximum TLS version to be negotiated, then negotiated TLS version. + * + * It is initialized as the configured maximum TLS version to be + * negotiated by mbedtls_ssl_setup(). + * + * When renegotiating or resuming a session, it is overwritten in the + * ClientHello writing preparation stage with the previously negotiated + * TLS version. + * + * On client side, it is updated to the TLS version selected by the server + * for the handshake when the ServerHello is received. + * + * On server side, it is updated to the TLS version the server selects for + * the handshake when the ClientHello is received. + */ + mbedtls_ssl_protocol_version MBEDTLS_PRIVATE(tls_version); + + unsigned MBEDTLS_PRIVATE(badmac_seen); /*!< records with a bad MAC received */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + /** Callback to customize X.509 certificate chain verification */ + int(*MBEDTLS_PRIVATE(f_vrfy))(void *, mbedtls_x509_crt *, int, uint32_t *); + void *MBEDTLS_PRIVATE(p_vrfy); /*!< context for X.509 verify callback */ +#endif + + mbedtls_ssl_send_t *MBEDTLS_PRIVATE(f_send); /*!< Callback for network send */ + mbedtls_ssl_recv_t *MBEDTLS_PRIVATE(f_recv); /*!< Callback for network receive */ + mbedtls_ssl_recv_timeout_t *MBEDTLS_PRIVATE(f_recv_timeout); + /*!< Callback for network receive with timeout */ + + void *MBEDTLS_PRIVATE(p_bio); /*!< context for I/O operations */ + + /* + * Session layer + */ + mbedtls_ssl_session *MBEDTLS_PRIVATE(session_in); /*!< current session data (in) */ + mbedtls_ssl_session *MBEDTLS_PRIVATE(session_out); /*!< current session data (out) */ + mbedtls_ssl_session *MBEDTLS_PRIVATE(session); /*!< negotiated session data */ + mbedtls_ssl_session *MBEDTLS_PRIVATE(session_negotiate); /*!< session data in negotiation */ + + mbedtls_ssl_handshake_params *MBEDTLS_PRIVATE(handshake); /*!< params required only during + the handshake process */ + + /* + * Record layer transformations + */ + mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_in); /*!< current transform params (in) + * This is always a reference, + * never an owning pointer. */ + mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_out); /*!< current transform params (out) + * This is always a reference, + * never an owning pointer. */ + mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform); /*!< negotiated transform params + * This pointer owns the transform + * it references. */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_negotiate); /*!< transform params in negotiation + * This pointer owns the transform + * it references. */ +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + /*! The application data transform in TLS 1.3. + * This pointer owns the transform it references. */ + mbedtls_ssl_transform *MBEDTLS_PRIVATE(transform_application); +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + + /* + * Timers + */ + void *MBEDTLS_PRIVATE(p_timer); /*!< context for the timer callbacks */ + + mbedtls_ssl_set_timer_t *MBEDTLS_PRIVATE(f_set_timer); /*!< set timer callback */ + mbedtls_ssl_get_timer_t *MBEDTLS_PRIVATE(f_get_timer); /*!< get timer callback */ + + /* + * Record layer (incoming data) + */ + unsigned char *MBEDTLS_PRIVATE(in_buf); /*!< input buffer */ + unsigned char *MBEDTLS_PRIVATE(in_ctr); /*!< 64-bit incoming message counter + TLS: maintained by us + DTLS: read from peer */ + unsigned char *MBEDTLS_PRIVATE(in_hdr); /*!< start of record header */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + unsigned char *MBEDTLS_PRIVATE(in_cid); /*!< The start of the CID; + * (the end is marked by in_len). */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + unsigned char *MBEDTLS_PRIVATE(in_len); /*!< two-bytes message length field */ + unsigned char *MBEDTLS_PRIVATE(in_iv); /*!< ivlen-byte IV */ + unsigned char *MBEDTLS_PRIVATE(in_msg); /*!< message contents (in_iv+ivlen) */ + unsigned char *MBEDTLS_PRIVATE(in_offt); /*!< read offset in application data */ + + int MBEDTLS_PRIVATE(in_msgtype); /*!< record header: message type */ + size_t MBEDTLS_PRIVATE(in_msglen); /*!< record header: message length */ + size_t MBEDTLS_PRIVATE(in_left); /*!< amount of data read so far */ +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) + size_t MBEDTLS_PRIVATE(in_buf_len); /*!< length of input buffer */ +#endif +#if defined(MBEDTLS_SSL_PROTO_DTLS) + uint16_t MBEDTLS_PRIVATE(in_epoch); /*!< DTLS epoch for incoming records */ + size_t MBEDTLS_PRIVATE(next_record_offset); /*!< offset of the next record in datagram + (equal to in_left if none) */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + uint64_t MBEDTLS_PRIVATE(in_window_top); /*!< last validated record seq_num */ + uint64_t MBEDTLS_PRIVATE(in_window); /*!< bitmask for replay detection */ +#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ + + size_t MBEDTLS_PRIVATE(in_hslen); /*!< current handshake message length, + including the handshake header */ + int MBEDTLS_PRIVATE(nb_zero); /*!< # of 0-length encrypted messages */ + + int MBEDTLS_PRIVATE(keep_current_message); /*!< drop or reuse current message + on next call to record layer? */ + + /* The following three variables indicate if and, if yes, + * what kind of alert is pending to be sent. + */ + unsigned char MBEDTLS_PRIVATE(send_alert); /*!< Determines if a fatal alert + should be sent. Values: + - \c 0 , no alert is to be sent. + - \c 1 , alert is to be sent. */ + unsigned char MBEDTLS_PRIVATE(alert_type); /*!< Type of alert if send_alert + != 0 */ + int MBEDTLS_PRIVATE(alert_reason); /*!< The error code to be returned + to the user once the fatal alert + has been sent. */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + uint8_t MBEDTLS_PRIVATE(disable_datagram_packing); /*!< Disable packing multiple records + * within a single datagram. */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* + * Record layer (outgoing data) + */ + unsigned char *MBEDTLS_PRIVATE(out_buf); /*!< output buffer */ + unsigned char *MBEDTLS_PRIVATE(out_ctr); /*!< 64-bit outgoing message counter */ + unsigned char *MBEDTLS_PRIVATE(out_hdr); /*!< start of record header */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + unsigned char *MBEDTLS_PRIVATE(out_cid); /*!< The start of the CID; + * (the end is marked by in_len). */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + unsigned char *MBEDTLS_PRIVATE(out_len); /*!< two-bytes message length field */ + unsigned char *MBEDTLS_PRIVATE(out_iv); /*!< ivlen-byte IV */ + unsigned char *MBEDTLS_PRIVATE(out_msg); /*!< message contents (out_iv+ivlen) */ + + int MBEDTLS_PRIVATE(out_msgtype); /*!< record header: message type */ + size_t MBEDTLS_PRIVATE(out_msglen); /*!< record header: message length */ + size_t MBEDTLS_PRIVATE(out_left); /*!< amount of data not yet written */ +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) + size_t MBEDTLS_PRIVATE(out_buf_len); /*!< length of output buffer */ +#endif + + unsigned char MBEDTLS_PRIVATE(cur_out_ctr)[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /*!< Outgoing record sequence number. */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + uint16_t MBEDTLS_PRIVATE(mtu); /*!< path mtu, used to fragment outgoing messages */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* + * User settings + */ +#if defined(MBEDTLS_X509_CRT_PARSE_C) + char *MBEDTLS_PRIVATE(hostname); /*!< expected peer CN for verification + (and SNI if available) */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_ALPN) + const char *MBEDTLS_PRIVATE(alpn_chosen); /*!< negotiated protocol */ +#endif /* MBEDTLS_SSL_ALPN */ + +#if defined(MBEDTLS_SSL_DTLS_SRTP) + /* + * use_srtp extension + */ + mbedtls_dtls_srtp_info MBEDTLS_PRIVATE(dtls_srtp_info); +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + + /* + * Information for DTLS hello verify + */ +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) + unsigned char *MBEDTLS_PRIVATE(cli_id); /*!< transport-level ID of the client */ + size_t MBEDTLS_PRIVATE(cli_id_len); /*!< length of cli_id */ +#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */ + + /* + * Secure renegotiation + */ + /* needed to know when to send extension on server */ + int MBEDTLS_PRIVATE(secure_renegotiation); /*!< does peer support legacy or + secure renegotiation */ +#if defined(MBEDTLS_SSL_RENEGOTIATION) + size_t MBEDTLS_PRIVATE(verify_data_len); /*!< length of verify data stored */ + char MBEDTLS_PRIVATE(own_verify_data)[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!< previous handshake verify data */ + char MBEDTLS_PRIVATE(peer_verify_data)[MBEDTLS_SSL_VERIFY_DATA_MAX_LEN]; /*!< previous handshake verify data */ +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* CID configuration to use in subsequent handshakes. */ + + /*! The next incoming CID, chosen by the user and applying to + * all subsequent handshakes. This may be different from the + * CID currently used in case the user has re-configured the CID + * after an initial handshake. */ + unsigned char MBEDTLS_PRIVATE(own_cid)[MBEDTLS_SSL_CID_IN_LEN_MAX]; + uint8_t MBEDTLS_PRIVATE(own_cid_len); /*!< The length of \c own_cid. */ + uint8_t MBEDTLS_PRIVATE(negotiate_cid); /*!< This indicates whether the CID extension should + * be negotiated in the next handshake or not. + * Possible values are #MBEDTLS_SSL_CID_ENABLED + * and #MBEDTLS_SSL_CID_DISABLED. */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +#if defined(MBEDTLS_SSL_EARLY_DATA) && defined(MBEDTLS_SSL_CLI_C) + int MBEDTLS_PRIVATE(early_data_status); +#endif /* MBEDTLS_SSL_EARLY_DATA && MBEDTLS_SSL_CLI_C */ + + /** Callback to export key block and master secret */ + mbedtls_ssl_export_keys_t *MBEDTLS_PRIVATE(f_export_keys); + void *MBEDTLS_PRIVATE(p_export_keys); /*!< context for key export callback */ + + /** User data pointer or handle. + * + * The library sets this to \p 0 when creating a context and does not + * access it afterwards. + * + * \warning Serializing and restoring an SSL context with + * mbedtls_ssl_context_save() and mbedtls_ssl_context_load() + * does not currently restore the user data. + */ + mbedtls_ssl_user_data_t MBEDTLS_PRIVATE(user_data); +}; + +/** + * \brief Return the name of the ciphersuite associated with the + * given ID + * + * \param ciphersuite_id SSL ciphersuite ID + * + * \return a string containing the ciphersuite name + */ +const char *mbedtls_ssl_get_ciphersuite_name(const int ciphersuite_id); + +/** + * \brief Return the ID of the ciphersuite associated with the + * given name + * + * \param ciphersuite_name SSL ciphersuite name + * + * \return the ID with the ciphersuite or 0 if not found + */ +int mbedtls_ssl_get_ciphersuite_id(const char *ciphersuite_name); + +/** + * \brief Initialize an SSL context + * Just makes the context ready for mbedtls_ssl_setup() or + * mbedtls_ssl_free() + * + * \param ssl SSL context + */ +void mbedtls_ssl_init(mbedtls_ssl_context *ssl); + +/** + * \brief Set up an SSL context for use + * + * \note No copy of the configuration context is made, it can be + * shared by many mbedtls_ssl_context structures. + * + * \warning The conf structure will be accessed during the session. + * It must not be modified or freed as long as the session + * is active. + * + * \warning This function must be called exactly once per context. + * Calling mbedtls_ssl_setup again is not supported, even + * if no session is active. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param ssl SSL context + * \param conf SSL configuration to use + * + * \return 0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED if + * memory allocation failed + */ +int mbedtls_ssl_setup(mbedtls_ssl_context *ssl, + const mbedtls_ssl_config *conf); + +/** + * \brief Reset an already initialized SSL context for re-use + * while retaining application-set variables, function + * pointers and data. + * + * \param ssl SSL context + * \return 0 if successful, or MBEDTLS_ERR_SSL_ALLOC_FAILED or + MBEDTLS_ERR_SSL_HW_ACCEL_FAILED + */ +int mbedtls_ssl_session_reset(mbedtls_ssl_context *ssl); + +/** + * \brief Set the current endpoint type + * + * \param conf SSL configuration + * \param endpoint must be MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER + */ +void mbedtls_ssl_conf_endpoint(mbedtls_ssl_config *conf, int endpoint); + +/** + * \brief Get the current endpoint type + * + * \param conf SSL configuration + * + * \return Endpoint type, either MBEDTLS_SSL_IS_CLIENT + * or MBEDTLS_SSL_IS_SERVER + */ +static inline int mbedtls_ssl_conf_get_endpoint(const mbedtls_ssl_config *conf) +{ + return conf->MBEDTLS_PRIVATE(endpoint); +} + +/** + * \brief Set the transport type (TLS or DTLS). + * Default: TLS + * + * \note For DTLS, you must either provide a recv callback that + * doesn't block, or one that handles timeouts, see + * \c mbedtls_ssl_set_bio(). You also need to provide timer + * callbacks with \c mbedtls_ssl_set_timer_cb(). + * + * \param conf SSL configuration + * \param transport transport type: + * MBEDTLS_SSL_TRANSPORT_STREAM for TLS, + * MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS. + */ +void mbedtls_ssl_conf_transport(mbedtls_ssl_config *conf, int transport); + +/** + * \brief Set the certificate verification mode + * Default: NONE on server, REQUIRED on client + * + * \param conf SSL configuration + * \param authmode can be: + * + * MBEDTLS_SSL_VERIFY_NONE: peer certificate is not checked + * (default on server) + * (insecure on client) + * + * MBEDTLS_SSL_VERIFY_OPTIONAL: peer certificate is checked, however the + * handshake continues even if verification failed; + * mbedtls_ssl_get_verify_result() can be called after the + * handshake is complete. + * + * MBEDTLS_SSL_VERIFY_REQUIRED: peer *must* present a valid certificate, + * handshake is aborted if verification failed. + * (default on client) + * + * \note On client, MBEDTLS_SSL_VERIFY_REQUIRED is the recommended mode. + * With MBEDTLS_SSL_VERIFY_OPTIONAL, the user needs to call mbedtls_ssl_get_verify_result() at + * the right time(s), which may not be obvious, while REQUIRED always perform + * the verification as soon as possible. For example, REQUIRED was protecting + * against the "triple handshake" attack even before it was found. + */ +void mbedtls_ssl_conf_authmode(mbedtls_ssl_config *conf, int authmode); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_EARLY_DATA) +/** + * \brief Set the early data mode + * Default: disabled on server and client + * + * \param conf The SSL configuration to use. + * \param early_data_enabled can be: + * + * MBEDTLS_SSL_EARLY_DATA_DISABLED: early data functionality is disabled + * This is the default on client and server. + * + * MBEDTLS_SSL_EARLY_DATA_ENABLED: early data functionality is enabled and + * may be negotiated in the handshake. Application using + * early data functionality needs to be aware of the + * lack of replay protection of the early data application + * payloads. + * + * \warning This interface is experimental and may change without notice. + * + */ +void mbedtls_ssl_tls13_conf_early_data(mbedtls_ssl_config *conf, + int early_data_enabled); + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Set the maximum amount of 0-RTT data in bytes + * Default: #MBEDTLS_SSL_MAX_EARLY_DATA_SIZE + * + * This function sets the value of the max_early_data_size + * field of the early data indication extension included in + * the NewSessionTicket messages that the server may send. + * + * The value defines the maximum amount of 0-RTT data + * in bytes that a client will be allowed to send when using + * one of the tickets defined by the NewSessionTicket messages. + * + * \note When resuming a session using a ticket, if the server receives more + * early data than allowed for the ticket, it terminates the connection. + * The maximum amount of 0-RTT data should thus be large enough + * to allow a minimum of early data to be exchanged. + * + * \param[in] conf The SSL configuration to use. + * \param[in] max_early_data_size The maximum amount of 0-RTT data. + * + * \warning This interface is experimental and may change without notice. + * + */ +void mbedtls_ssl_tls13_conf_max_early_data_size( + mbedtls_ssl_config *conf, uint32_t max_early_data_size); +#endif /* MBEDTLS_SSL_SRV_C */ + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_EARLY_DATA */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Set the verification callback (Optional). + * + * If set, the provided verify callback is called for each + * certificate in the peer's CRT chain, including the trusted + * root. For more information, please see the documentation of + * \c mbedtls_x509_crt_verify(). + * + * \note For per context callbacks and contexts, please use + * mbedtls_ssl_set_verify() instead. + * + * \param conf The SSL configuration to use. + * \param f_vrfy The verification callback to use during CRT verification. + * \param p_vrfy The opaque context to be passed to the callback. + */ +void mbedtls_ssl_conf_verify(mbedtls_ssl_config *conf, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/** + * \brief Set the random number generator callback + * + * \param conf SSL configuration + * \param f_rng RNG function (mandatory) + * \param p_rng RNG parameter + */ +void mbedtls_ssl_conf_rng(mbedtls_ssl_config *conf, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Set the debug callback + * + * The callback has the following argument: + * void * opaque context for the callback + * int debug level + * const char * file name + * int line number + * const char * message + * + * \param conf SSL configuration + * \param f_dbg debug function + * \param p_dbg debug parameter + */ +void mbedtls_ssl_conf_dbg(mbedtls_ssl_config *conf, + void (*f_dbg)(void *, int, const char *, int, const char *), + void *p_dbg); + +/** + * \brief Return the SSL configuration structure associated + * with the given SSL context. + * + * \note The pointer returned by this function is guaranteed to + * remain valid until the context is freed. + * + * \param ssl The SSL context to query. + * \return Pointer to the SSL configuration associated with \p ssl. + */ +static inline const mbedtls_ssl_config *mbedtls_ssl_context_get_config( + const mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(conf); +} + +/** + * \brief Set the underlying BIO callbacks for write, read and + * read-with-timeout. + * + * \param ssl SSL context + * \param p_bio parameter (context) shared by BIO callbacks + * \param f_send write callback + * \param f_recv read callback + * \param f_recv_timeout blocking read callback with timeout. + * + * \note One of f_recv or f_recv_timeout can be NULL, in which case + * the other is used. If both are non-NULL, f_recv_timeout is + * used and f_recv is ignored (as if it were NULL). + * + * \note The two most common use cases are: + * - non-blocking I/O, f_recv != NULL, f_recv_timeout == NULL + * - blocking I/O, f_recv == NULL, f_recv_timeout != NULL + * + * \note For DTLS, you need to provide either a non-NULL + * f_recv_timeout callback, or a f_recv that doesn't block. + * + * \note See the documentations of \c mbedtls_ssl_send_t, + * \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for + * the conventions those callbacks must follow. + * + * \note On some platforms, net_sockets.c provides + * \c mbedtls_net_send(), \c mbedtls_net_recv() and + * \c mbedtls_net_recv_timeout() that are suitable to be used + * here. + */ +void mbedtls_ssl_set_bio(mbedtls_ssl_context *ssl, + void *p_bio, + mbedtls_ssl_send_t *f_send, + mbedtls_ssl_recv_t *f_recv, + mbedtls_ssl_recv_timeout_t *f_recv_timeout); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + + +/** + * \brief Configure the use of the Connection ID (CID) + * extension in the next handshake. + * + * Reference: RFC 9146 (or draft-ietf-tls-dtls-connection-id-05 + * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05 + * for legacy version) + * + * The DTLS CID extension allows the reliable association of + * DTLS records to DTLS connections across changes in the + * underlying transport (changed IP and Port metadata) by + * adding explicit connection identifiers (CIDs) to the + * headers of encrypted DTLS records. The desired CIDs are + * configured by the application layer and are exchanged in + * new `ClientHello` / `ServerHello` extensions during the + * handshake, where each side indicates the CID it wants the + * peer to use when writing encrypted messages. The CIDs are + * put to use once records get encrypted: the stack discards + * any incoming records that don't include the configured CID + * in their header, and adds the peer's requested CID to the + * headers of outgoing messages. + * + * This API enables or disables the use of the CID extension + * in the next handshake and sets the value of the CID to + * be used for incoming messages. + * + * \param ssl The SSL context to configure. This must be initialized. + * \param enable This value determines whether the CID extension should + * be used or not. Possible values are: + * - MBEDTLS_SSL_CID_ENABLED to enable the use of the CID. + * - MBEDTLS_SSL_CID_DISABLED (default) to disable the use + * of the CID. + * \param own_cid The address of the readable buffer holding the CID we want + * the peer to use when sending encrypted messages to us. + * This may be \c NULL if \p own_cid_len is \c 0. + * This parameter is unused if \p enable is set to + * MBEDTLS_SSL_CID_DISABLED. + * \param own_cid_len The length of \p own_cid. + * This parameter is unused if \p enable is set to + * MBEDTLS_SSL_CID_DISABLED. + * + * \note The value of \p own_cid_len must match the value of the + * \c len parameter passed to mbedtls_ssl_conf_cid() + * when configuring the ::mbedtls_ssl_config that \p ssl + * is bound to. + * + * \note This CID configuration applies to subsequent handshakes + * performed on the SSL context \p ssl, but does not trigger + * one. You still have to call `mbedtls_ssl_handshake()` + * (for the initial handshake) or `mbedtls_ssl_renegotiate()` + * (for a renegotiation handshake) explicitly after a + * successful call to this function to run the handshake. + * + * \note This call cannot guarantee that the use of the CID + * will be successfully negotiated in the next handshake, + * because the peer might not support it. Specifically: + * - On the Client, enabling the use of the CID through + * this call implies that the `ClientHello` in the next + * handshake will include the CID extension, thereby + * offering the use of the CID to the server. Only if + * the `ServerHello` contains the CID extension, too, + * the CID extension will actually be put to use. + * - On the Server, enabling the use of the CID through + * this call implies that the server will look for + * the CID extension in a `ClientHello` from the client, + * and, if present, reply with a CID extension in its + * `ServerHello`. + * + * \note To check whether the use of the CID was negotiated + * after the subsequent handshake has completed, please + * use the API mbedtls_ssl_get_peer_cid(). + * + * \warning If the use of the CID extension is enabled in this call + * and the subsequent handshake negotiates its use, Mbed TLS + * will silently drop every packet whose CID does not match + * the CID configured in \p own_cid. It is the responsibility + * of the user to adapt the underlying transport to take care + * of CID-based demultiplexing before handing datagrams to + * Mbed TLS. + * + * \return \c 0 on success. In this case, the CID configuration + * applies to the next handshake. + * \return A negative error code on failure. + */ +int mbedtls_ssl_set_cid(mbedtls_ssl_context *ssl, + int enable, + unsigned char const *own_cid, + size_t own_cid_len); + +/** + * \brief Get information about our request for usage of the CID + * extension in the current connection. + * + * \param ssl The SSL context to query. + * \param enabled The address at which to store whether the CID extension + * is requested to be used or not. If the CID is + * requested, `*enabled` is set to + * MBEDTLS_SSL_CID_ENABLED; otherwise, it is set to + * MBEDTLS_SSL_CID_DISABLED. + * \param own_cid The address of the buffer in which to store our own + * CID (if the CID extension is requested). This may be + * \c NULL in case the value of our CID isn't needed. If + * it is not \c NULL, \p own_cid_len must not be \c NULL. + * \param own_cid_len The address at which to store the size of our own CID + * (if the CID extension is requested). This is also the + * number of Bytes in \p own_cid that have been written. + * This may be \c NULL in case the length of our own CID + * isn't needed. If it is \c NULL, \p own_cid must be + * \c NULL, too. + * + *\note If we are requesting an empty CID this function sets + * `*enabled` to #MBEDTLS_SSL_CID_DISABLED (the rationale + * for this is that the resulting outcome is the + * same as if the CID extensions wasn't requested). + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_ssl_get_own_cid(mbedtls_ssl_context *ssl, + int *enabled, + unsigned char own_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX], + size_t *own_cid_len); + +/** + * \brief Get information about the use of the CID extension + * in the current connection. + * + * \param ssl The SSL context to query. + * \param enabled The address at which to store whether the CID extension + * is currently in use or not. If the CID is in use, + * `*enabled` is set to MBEDTLS_SSL_CID_ENABLED; + * otherwise, it is set to MBEDTLS_SSL_CID_DISABLED. + * \param peer_cid The address of the buffer in which to store the CID + * chosen by the peer (if the CID extension is used). + * This may be \c NULL in case the value of peer CID + * isn't needed. If it is not \c NULL, \p peer_cid_len + * must not be \c NULL. + * \param peer_cid_len The address at which to store the size of the CID + * chosen by the peer (if the CID extension is used). + * This is also the number of Bytes in \p peer_cid that + * have been written. + * This may be \c NULL in case the length of the peer CID + * isn't needed. If it is \c NULL, \p peer_cid must be + * \c NULL, too. + * + * \note This applies to the state of the CID negotiated in + * the last complete handshake. If a handshake is in + * progress, this function will attempt to complete + * the handshake first. + * + * \note If CID extensions have been exchanged but both client + * and server chose to use an empty CID, this function + * sets `*enabled` to #MBEDTLS_SSL_CID_DISABLED + * (the rationale for this is that the resulting + * communication is the same as if the CID extensions + * hadn't been used). + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_ssl_get_peer_cid(mbedtls_ssl_context *ssl, + int *enabled, + unsigned char peer_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX], + size_t *peer_cid_len); + +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +/** + * \brief Set the Maximum Transport Unit (MTU). + * Special value: 0 means unset (no limit). + * This represents the maximum size of a datagram payload + * handled by the transport layer (usually UDP) as determined + * by the network link and stack. In practice, this controls + * the maximum size datagram the DTLS layer will pass to the + * \c f_send() callback set using \c mbedtls_ssl_set_bio(). + * + * \note The limit on datagram size is converted to a limit on + * record payload by subtracting the current overhead of + * encapsulation and encryption/authentication if any. + * + * \note This can be called at any point during the connection, for + * example when a Path Maximum Transfer Unit (PMTU) + * estimate becomes available from other sources, + * such as lower (or higher) protocol layers. + * + * \note This setting only controls the size of the packets we send, + * and does not restrict the size of the datagrams we're + * willing to receive. Client-side, you can request the + * server to use smaller records with \c + * mbedtls_ssl_conf_max_frag_len(). + * + * \note If both a MTU and a maximum fragment length have been + * configured (or negotiated with the peer), the resulting + * lower limit on record payload (see first note) is used. + * + * \note This can only be used to decrease the maximum size + * of datagrams (hence records, see first note) sent. It + * cannot be used to increase the maximum size of records over + * the limit set by #MBEDTLS_SSL_OUT_CONTENT_LEN. + * + * \note Values lower than the current record layer expansion will + * result in an error when trying to send data. + * + * \param ssl SSL context + * \param mtu Value of the path MTU in bytes + */ +void mbedtls_ssl_set_mtu(mbedtls_ssl_context *ssl, uint16_t mtu); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Set a connection-specific verification callback (optional). + * + * If set, the provided verify callback is called for each + * certificate in the peer's CRT chain, including the trusted + * root. For more information, please see the documentation of + * \c mbedtls_x509_crt_verify(). + * + * \note This call is analogous to mbedtls_ssl_conf_verify() but + * binds the verification callback and context to an SSL context + * as opposed to an SSL configuration. + * If mbedtls_ssl_conf_verify() and mbedtls_ssl_set_verify() + * are both used, mbedtls_ssl_set_verify() takes precedence. + * + * \param ssl The SSL context to use. + * \param f_vrfy The verification callback to use during CRT verification. + * \param p_vrfy The opaque context to be passed to the callback. + */ +void mbedtls_ssl_set_verify(mbedtls_ssl_context *ssl, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/** + * \brief Set the timeout period for mbedtls_ssl_read() + * (Default: no timeout.) + * + * \param conf SSL configuration context + * \param timeout Timeout value in milliseconds. + * Use 0 for no timeout (default). + * + * \note With blocking I/O, this will only work if a non-NULL + * \c f_recv_timeout was set with \c mbedtls_ssl_set_bio(). + * With non-blocking I/O, this will only work if timer + * callbacks were set with \c mbedtls_ssl_set_timer_cb(). + * + * \note With non-blocking I/O, you may also skip this function + * altogether and handle timeouts at the application layer. + */ +void mbedtls_ssl_conf_read_timeout(mbedtls_ssl_config *conf, uint32_t timeout); + +/** + * \brief Check whether a buffer contains a valid and authentic record + * that has not been seen before. (DTLS only). + * + * This function does not change the user-visible state + * of the SSL context. Its sole purpose is to provide + * an indication of the legitimacy of an incoming record. + * + * This can be useful e.g. in distributed server environments + * using the DTLS Connection ID feature, in which connections + * might need to be passed between service instances on a change + * of peer address, but where such disruptive operations should + * only happen after the validity of incoming records has been + * confirmed. + * + * \param ssl The SSL context to use. + * \param buf The address of the buffer holding the record to be checked. + * This must be a read/write buffer of length \p buflen Bytes. + * \param buflen The length of \p buf in Bytes. + * + * \note This routine only checks whether the provided buffer begins + * with a valid and authentic record that has not been seen + * before, but does not check potential data following the + * initial record. In particular, it is possible to pass DTLS + * datagrams containing multiple records, in which case only + * the first record is checked. + * + * \note This function modifies the input buffer \p buf. If you need + * to preserve the original record, you have to maintain a copy. + * + * \return \c 0 if the record is valid and authentic and has not been + * seen before. + * \return MBEDTLS_ERR_SSL_INVALID_MAC if the check completed + * successfully but the record was found to be not authentic. + * \return MBEDTLS_ERR_SSL_INVALID_RECORD if the check completed + * successfully but the record was found to be invalid for + * a reason different from authenticity checking. + * \return MBEDTLS_ERR_SSL_UNEXPECTED_RECORD if the check completed + * successfully but the record was found to be unexpected + * in the state of the SSL context, including replayed records. + * \return Another negative error code on different kinds of failure. + * In this case, the SSL context becomes unusable and needs + * to be freed or reset before reuse. + */ +int mbedtls_ssl_check_record(mbedtls_ssl_context const *ssl, + unsigned char *buf, + size_t buflen); + +/** + * \brief Set the timer callbacks (Mandatory for DTLS.) + * + * \param ssl SSL context + * \param p_timer parameter (context) shared by timer callbacks + * \param f_set_timer set timer callback + * \param f_get_timer get timer callback. Must return: + * + * \note See the documentation of \c mbedtls_ssl_set_timer_t and + * \c mbedtls_ssl_get_timer_t for the conventions this pair of + * callbacks must follow. + * + * \note On some platforms, timing.c provides + * \c mbedtls_timing_set_delay() and + * \c mbedtls_timing_get_delay() that are suitable for using + * here, except if using an event-driven style. + * + * \note See also the "DTLS tutorial" article in our knowledge base. + * https://mbed-tls.readthedocs.io/en/latest/kb/how-to/dtls-tutorial + */ +void mbedtls_ssl_set_timer_cb(mbedtls_ssl_context *ssl, + void *p_timer, + mbedtls_ssl_set_timer_t *f_set_timer, + mbedtls_ssl_get_timer_t *f_get_timer); + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Set the certificate selection callback (server-side only). + * + * If set, the callback is always called for each handshake, + * after `ClientHello` processing has finished. + * + * \param conf The SSL configuration to register the callback with. + * \param f_cert_cb The callback for selecting server certificate after + * `ClientHello` processing has finished. + */ +static inline void mbedtls_ssl_conf_cert_cb(mbedtls_ssl_config *conf, + mbedtls_ssl_hs_cb_t f_cert_cb) +{ + conf->MBEDTLS_PRIVATE(f_cert_cb) = f_cert_cb; +} +#endif /* MBEDTLS_SSL_SRV_C */ + +/** + * \brief Callback type: generate and write session ticket + * + * \note This describes what a callback implementation should do. + * This callback should generate an encrypted and + * authenticated ticket for the session and write it to the + * output buffer. Here, ticket means the opaque ticket part + * of the NewSessionTicket structure of RFC 5077. + * + * \param p_ticket Context for the callback + * \param session SSL session to be written in the ticket + * \param start Start of the output buffer + * \param end End of the output buffer + * \param tlen On exit, holds the length written + * \param lifetime On exit, holds the lifetime of the ticket in seconds + * + * \return 0 if successful, or + * a specific MBEDTLS_ERR_XXX code. + */ +typedef int mbedtls_ssl_ticket_write_t(void *p_ticket, + const mbedtls_ssl_session *session, + unsigned char *start, + const unsigned char *end, + size_t *tlen, + uint32_t *lifetime); + +/** + * \brief Callback type: parse and load session ticket + * + * \note This describes what a callback implementation should do. + * This callback should parse a session ticket as generated + * by the corresponding mbedtls_ssl_ticket_write_t function, + * and, if the ticket is authentic and valid, load the + * session. + * + * \note The implementation is allowed to modify the first len + * bytes of the input buffer, eg to use it as a temporary + * area for the decrypted ticket contents. + * + * \param p_ticket Context for the callback + * \param session SSL session to be loaded + * \param buf Start of the buffer containing the ticket + * \param len Length of the ticket. + * + * \return 0 if successful, or + * MBEDTLS_ERR_SSL_INVALID_MAC if not authentic, or + * MBEDTLS_ERR_SSL_SESSION_TICKET_EXPIRED if expired, or + * any other non-zero code for other failures. + */ +typedef int mbedtls_ssl_ticket_parse_t(void *p_ticket, + mbedtls_ssl_session *session, + unsigned char *buf, + size_t len); + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Configure SSL session ticket callbacks (server only). + * (Default: none.) + * + * \note On server, session tickets are enabled by providing + * non-NULL callbacks. + * + * \note On client, use \c mbedtls_ssl_conf_session_tickets(). + * + * \param conf SSL configuration context + * \param f_ticket_write Callback for writing a ticket + * \param f_ticket_parse Callback for parsing a ticket + * \param p_ticket Context shared by the two callbacks + */ +void mbedtls_ssl_conf_session_tickets_cb(mbedtls_ssl_config *conf, + mbedtls_ssl_ticket_write_t *f_ticket_write, + mbedtls_ssl_ticket_parse_t *f_ticket_parse, + void *p_ticket); +#endif /* MBEDTLS_SSL_SESSION_TICKETS && MBEDTLS_SSL_SRV_C */ + +/** + * \brief Configure a key export callback. + * (Default: none.) + * + * This API can be used for two purposes: + * - Debugging: Use this API to e.g. generate an NSSKeylog + * file and use it to inspect encrypted traffic in tools + * such as Wireshark. + * - Application-specific export: Use this API to implement + * key exporters, e.g. for EAP-TLS or DTLS-SRTP. + * + * + * \param ssl The SSL context to which the export + * callback should be attached. + * \param f_export_keys The callback for the key export. + * \param p_export_keys The opaque context pointer to be passed to the + * callback \p f_export_keys. + */ +void mbedtls_ssl_set_export_keys_cb(mbedtls_ssl_context *ssl, + mbedtls_ssl_export_keys_t *f_export_keys, + void *p_export_keys); + +/** \brief Set the user data in an SSL configuration to a pointer. + * + * You can retrieve this value later with mbedtls_ssl_conf_get_user_data_p(). + * + * \note The library stores \c p without accessing it. It is the responsibility + * of the caller to ensure that the pointer remains valid. + * + * \param conf The SSL configuration context to modify. + * \param p The new value of the user data. + */ +static inline void mbedtls_ssl_conf_set_user_data_p( + mbedtls_ssl_config *conf, + void *p) +{ + conf->MBEDTLS_PRIVATE(user_data).p = p; +} + +/** \brief Set the user data in an SSL configuration to an integer. + * + * You can retrieve this value later with mbedtls_ssl_conf_get_user_data_n(). + * + * \param conf The SSL configuration context to modify. + * \param n The new value of the user data. + */ +static inline void mbedtls_ssl_conf_set_user_data_n( + mbedtls_ssl_config *conf, + uintptr_t n) +{ + conf->MBEDTLS_PRIVATE(user_data).n = n; +} + +/** \brief Retrieve the user data in an SSL configuration as a pointer. + * + * This is the value last set with mbedtls_ssl_conf_set_user_data_p(), or + * \c NULL if mbedtls_ssl_conf_set_user_data_p() has not previously been + * called. The value is undefined if mbedtls_ssl_conf_set_user_data_n() has + * been called without a subsequent call to mbedtls_ssl_conf_set_user_data_p(). + * + * \param conf The SSL configuration context to modify. + * \return The current value of the user data. + */ +static inline void *mbedtls_ssl_conf_get_user_data_p( + mbedtls_ssl_config *conf) +{ + return conf->MBEDTLS_PRIVATE(user_data).p; +} + +/** \brief Retrieve the user data in an SSL configuration as an integer. + * + * This is the value last set with mbedtls_ssl_conf_set_user_data_n(), or + * \c 0 if mbedtls_ssl_conf_set_user_data_n() has not previously been + * called. The value is undefined if mbedtls_ssl_conf_set_user_data_p() has + * been called without a subsequent call to mbedtls_ssl_conf_set_user_data_n(). + * + * \param conf The SSL configuration context to modify. + * \return The current value of the user data. + */ +static inline uintptr_t mbedtls_ssl_conf_get_user_data_n( + mbedtls_ssl_config *conf) +{ + return conf->MBEDTLS_PRIVATE(user_data).n; +} + +/** \brief Set the user data in an SSL context to a pointer. + * + * You can retrieve this value later with mbedtls_ssl_get_user_data_p(). + * + * \note The library stores \c p without accessing it. It is the responsibility + * of the caller to ensure that the pointer remains valid. + * + * \param ssl The SSL context to modify. + * \param p The new value of the user data. + */ +static inline void mbedtls_ssl_set_user_data_p( + mbedtls_ssl_context *ssl, + void *p) +{ + ssl->MBEDTLS_PRIVATE(user_data).p = p; +} + +/** \brief Set the user data in an SSL context to an integer. + * + * You can retrieve this value later with mbedtls_ssl_get_user_data_n(). + * + * \param ssl The SSL context to modify. + * \param n The new value of the user data. + */ +static inline void mbedtls_ssl_set_user_data_n( + mbedtls_ssl_context *ssl, + uintptr_t n) +{ + ssl->MBEDTLS_PRIVATE(user_data).n = n; +} + +/** \brief Retrieve the user data in an SSL context as a pointer. + * + * This is the value last set with mbedtls_ssl_set_user_data_p(), or + * \c NULL if mbedtls_ssl_set_user_data_p() has not previously been + * called. The value is undefined if mbedtls_ssl_set_user_data_n() has + * been called without a subsequent call to mbedtls_ssl_set_user_data_p(). + * + * \param ssl The SSL context to modify. + * \return The current value of the user data. + */ +static inline void *mbedtls_ssl_get_user_data_p( + mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(user_data).p; +} + +/** \brief Retrieve the user data in an SSL context as an integer. + * + * This is the value last set with mbedtls_ssl_set_user_data_n(), or + * \c 0 if mbedtls_ssl_set_user_data_n() has not previously been + * called. The value is undefined if mbedtls_ssl_set_user_data_p() has + * been called without a subsequent call to mbedtls_ssl_set_user_data_n(). + * + * \param ssl The SSL context to modify. + * \return The current value of the user data. + */ +static inline uintptr_t mbedtls_ssl_get_user_data_n( + mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(user_data).n; +} + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) +/** + * \brief Configure asynchronous private key operation callbacks. + * + * \param conf SSL configuration context + * \param f_async_sign Callback to start a signature operation. See + * the description of ::mbedtls_ssl_async_sign_t + * for more information. This may be \c NULL if the + * external processor does not support any signature + * operation; in this case the private key object + * associated with the certificate will be used. + * \param f_async_decrypt Callback to start a decryption operation. See + * the description of ::mbedtls_ssl_async_decrypt_t + * for more information. This may be \c NULL if the + * external processor does not support any decryption + * operation; in this case the private key object + * associated with the certificate will be used. + * \param f_async_resume Callback to resume an asynchronous operation. See + * the description of ::mbedtls_ssl_async_resume_t + * for more information. This may not be \c NULL unless + * \p f_async_sign and \p f_async_decrypt are both + * \c NULL. + * \param f_async_cancel Callback to cancel an asynchronous operation. See + * the description of ::mbedtls_ssl_async_cancel_t + * for more information. This may be \c NULL if + * no cleanup is needed. + * \param config_data A pointer to configuration data which can be + * retrieved with + * mbedtls_ssl_conf_get_async_config_data(). The + * library stores this value without dereferencing it. + */ +void mbedtls_ssl_conf_async_private_cb(mbedtls_ssl_config *conf, + mbedtls_ssl_async_sign_t *f_async_sign, + mbedtls_ssl_async_decrypt_t *f_async_decrypt, + mbedtls_ssl_async_resume_t *f_async_resume, + mbedtls_ssl_async_cancel_t *f_async_cancel, + void *config_data); + +/** + * \brief Retrieve the configuration data set by + * mbedtls_ssl_conf_async_private_cb(). + * + * \param conf SSL configuration context + * \return The configuration data set by + * mbedtls_ssl_conf_async_private_cb(). + */ +void *mbedtls_ssl_conf_get_async_config_data(const mbedtls_ssl_config *conf); + +/** + * \brief Retrieve the asynchronous operation user context. + * + * \note This function may only be called while a handshake + * is in progress. + * + * \param ssl The SSL context to access. + * + * \return The asynchronous operation user context that was last + * set during the current handshake. If + * mbedtls_ssl_set_async_operation_data() has not yet been + * called during the current handshake, this function returns + * \c NULL. + */ +void *mbedtls_ssl_get_async_operation_data(const mbedtls_ssl_context *ssl); + +/** + * \brief Retrieve the asynchronous operation user context. + * + * \note This function may only be called while a handshake + * is in progress. + * + * \param ssl The SSL context to access. + * \param ctx The new value of the asynchronous operation user context. + * Call mbedtls_ssl_get_async_operation_data() later during the + * same handshake to retrieve this value. + */ +void mbedtls_ssl_set_async_operation_data(mbedtls_ssl_context *ssl, + void *ctx); +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ + +/** + * \brief Callback type: generate a cookie + * + * \param ctx Context for the callback + * \param p Buffer to write to, + * must be updated to point right after the cookie + * \param end Pointer to one past the end of the output buffer + * \param info Client ID info that was passed to + * \c mbedtls_ssl_set_client_transport_id() + * \param ilen Length of info in bytes + * + * \return The callback must return 0 on success, + * or a negative error code. + */ +typedef int mbedtls_ssl_cookie_write_t(void *ctx, + unsigned char **p, unsigned char *end, + const unsigned char *info, size_t ilen); + +/** + * \brief Callback type: verify a cookie + * + * \param ctx Context for the callback + * \param cookie Cookie to verify + * \param clen Length of cookie + * \param info Client ID info that was passed to + * \c mbedtls_ssl_set_client_transport_id() + * \param ilen Length of info in bytes + * + * \return The callback must return 0 if cookie is valid, + * or a negative error code. + */ +typedef int mbedtls_ssl_cookie_check_t(void *ctx, + const unsigned char *cookie, size_t clen, + const unsigned char *info, size_t ilen); + +#if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) && defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Register callbacks for DTLS cookies + * (Server only. DTLS only.) + * + * Default: dummy callbacks that fail, in order to force you to + * register working callbacks (and initialize their context). + * + * To disable HelloVerifyRequest, register NULL callbacks. + * + * \warning Disabling hello verification allows your server to be used + * for amplification in DoS attacks against other hosts. + * Only disable if you known this can't happen in your + * particular environment. + * + * \note See comments on \c mbedtls_ssl_handshake() about handling + * the MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED that is expected + * on the first handshake attempt when this is enabled. + * + * \note This is also necessary to handle client reconnection from + * the same port as described in RFC 6347 section 4.2.8 (only + * the variant with cookies is supported currently). See + * comments on \c mbedtls_ssl_read() for details. + * + * \param conf SSL configuration + * \param f_cookie_write Cookie write callback + * \param f_cookie_check Cookie check callback + * \param p_cookie Context for both callbacks + */ +void mbedtls_ssl_conf_dtls_cookies(mbedtls_ssl_config *conf, + mbedtls_ssl_cookie_write_t *f_cookie_write, + mbedtls_ssl_cookie_check_t *f_cookie_check, + void *p_cookie); + +/** + * \brief Set client's transport-level identification info. + * (Server only. DTLS only.) + * + * This is usually the IP address (and port), but could be + * anything identify the client depending on the underlying + * network stack. Used for HelloVerifyRequest with DTLS. + * This is *not* used to route the actual packets. + * + * \param ssl SSL context + * \param info Transport-level info identifying the client (eg IP + port) + * \param ilen Length of info in bytes + * + * \note An internal copy is made, so the info buffer can be reused. + * + * \return 0 on success, + * MBEDTLS_ERR_SSL_BAD_INPUT_DATA if used on client, + * MBEDTLS_ERR_SSL_ALLOC_FAILED if out of memory. + */ +int mbedtls_ssl_set_client_transport_id(mbedtls_ssl_context *ssl, + const unsigned char *info, + size_t ilen); + +#endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) +/** + * \brief Enable or disable anti-replay protection for DTLS. + * (DTLS only, no effect on TLS.) + * Default: enabled. + * + * \param conf SSL configuration + * \param mode MBEDTLS_SSL_ANTI_REPLAY_ENABLED or MBEDTLS_SSL_ANTI_REPLAY_DISABLED. + * + * \warning Disabling this is a security risk unless the application + * protocol handles duplicated packets in a safe way. You + * should not disable this without careful consideration. + * However, if your application already detects duplicated + * packets and needs information about them to adjust its + * transmission strategy, then you'll want to disable this. + */ +void mbedtls_ssl_conf_dtls_anti_replay(mbedtls_ssl_config *conf, char mode); +#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ + +/** + * \brief Set a limit on the number of records with a bad MAC + * before terminating the connection. + * (DTLS only, no effect on TLS.) + * Default: 0 (disabled). + * + * \param conf SSL configuration + * \param limit Limit, or 0 to disable. + * + * \note If the limit is N, then the connection is terminated when + * the Nth non-authentic record is seen. + * + * \note Records with an invalid header are not counted, only the + * ones going through the authentication-decryption phase. + * + * \note This is a security trade-off related to the fact that it's + * often relatively easy for an active attacker to inject UDP + * datagrams. On one hand, setting a low limit here makes it + * easier for such an attacker to forcibly terminated a + * connection. On the other hand, a high limit or no limit + * might make us waste resources checking authentication on + * many bogus packets. + */ +void mbedtls_ssl_conf_dtls_badmac_limit(mbedtls_ssl_config *conf, unsigned limit); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +/** + * \brief Allow or disallow packing of multiple handshake records + * within a single datagram. + * + * \param ssl The SSL context to configure. + * \param allow_packing This determines whether datagram packing may + * be used or not. A value of \c 0 means that every + * record will be sent in a separate datagram; a + * value of \c 1 means that, if space permits, + * multiple handshake messages (including CCS) belonging to + * a single flight may be packed within a single datagram. + * + * \note This is enabled by default and should only be disabled + * for test purposes, or if datagram packing causes + * interoperability issues with peers that don't support it. + * + * \note Allowing datagram packing reduces the network load since + * there's less overhead if multiple messages share the same + * datagram. Also, it increases the handshake efficiency + * since messages belonging to a single datagram will not + * be reordered in transit, and so future message buffering + * or flight retransmission (if no buffering is used) as + * means to deal with reordering are needed less frequently. + * + * \note Application records are not affected by this option and + * are currently always sent in separate datagrams. + * + */ +void mbedtls_ssl_set_datagram_packing(mbedtls_ssl_context *ssl, + unsigned allow_packing); + +/** + * \brief Set retransmit timeout values for the DTLS handshake. + * (DTLS only, no effect on TLS.) + * + * \param conf SSL configuration + * \param min Initial timeout value in milliseconds. + * Default: 1000 (1 second). + * \param max Maximum timeout value in milliseconds. + * Default: 60000 (60 seconds). + * + * \note Default values are from RFC 6347 section 4.2.4.1. + * + * \note The 'min' value should typically be slightly above the + * expected round-trip time to your peer, plus whatever time + * it takes for the peer to process the message. For example, + * if your RTT is about 600ms and you peer needs up to 1s to + * do the cryptographic operations in the handshake, then you + * should set 'min' slightly above 1600. Lower values of 'min' + * might cause spurious resends which waste network resources, + * while larger value of 'min' will increase overall latency + * on unreliable network links. + * + * \note The more unreliable your network connection is, the larger + * your max / min ratio needs to be in order to achieve + * reliable handshakes. + * + * \note Messages are retransmitted up to log2(ceil(max/min)) times. + * For example, if min = 1s and max = 5s, the retransmit plan + * goes: send ... 1s -> resend ... 2s -> resend ... 4s -> + * resend ... 5s -> give up and return a timeout error. + */ +void mbedtls_ssl_conf_handshake_timeout(mbedtls_ssl_config *conf, uint32_t min, uint32_t max); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Set the session cache callbacks (server-side only) + * If not set, no session resuming is done (except if session + * tickets are enabled too). + * + * The session cache has the responsibility to check for stale + * entries based on timeout. See RFC 5246 for recommendations. + * + * Warning: session.peer_cert is cleared by the SSL/TLS layer on + * connection shutdown, so do not cache the pointer! Either set + * it to NULL or make a full copy of the certificate. + * + * The get callback is called once during the initial handshake + * to enable session resuming. The get function has the + * following parameters: (void *parameter, mbedtls_ssl_session *session) + * If a valid entry is found, it should fill the master of + * the session object with the cached values and return 0, + * return 1 otherwise. Optionally peer_cert can be set as well + * if it is properly present in cache entry. + * + * The set callback is called once during the initial handshake + * to enable session resuming after the entire handshake has + * been finished. The set function has the following parameters: + * (void *parameter, const mbedtls_ssl_session *session). The function + * should create a cache entry for future retrieval based on + * the data in the session structure and should keep in mind + * that the mbedtls_ssl_session object presented (and all its referenced + * data) is cleared by the SSL/TLS layer when the connection is + * terminated. It is recommended to add metadata to determine if + * an entry is still valid in the future. Return 0 if + * successfully cached, return 1 otherwise. + * + * \param conf SSL configuration + * \param p_cache parameter (context) for both callbacks + * \param f_get_cache session get callback + * \param f_set_cache session set callback + */ +void mbedtls_ssl_conf_session_cache(mbedtls_ssl_config *conf, + void *p_cache, + mbedtls_ssl_cache_get_t *f_get_cache, + mbedtls_ssl_cache_set_t *f_set_cache); +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_CLI_C) +/** + * \brief Load a session for session resumption. + * + * Sessions loaded through this call will be considered + * for session resumption in the next handshake. + * + * \note Even if this call succeeds, it is not guaranteed that + * the next handshake will indeed be shortened through the + * use of session resumption: The server is always free + * to reject any attempt for resumption and fall back to + * a full handshake. + * + * \note This function can handle a variety of mechanisms for session + * resumption: For TLS 1.2, both session ID-based resumption and + * ticket-based resumption will be considered. For TLS 1.3, + * once implemented, sessions equate to tickets, and loading + * one or more sessions via this call will lead to their + * corresponding tickets being advertised as resumption PSKs + * by the client. + * + * \note Calling this function multiple times will only be useful + * once TLS 1.3 is supported. For TLS 1.2 connections, this + * function should be called at most once. + * + * \param ssl The SSL context representing the connection which should + * be attempted to be setup using session resumption. This + * must be initialized via mbedtls_ssl_init() and bound to + * an SSL configuration via mbedtls_ssl_setup(), but + * the handshake must not yet have been started. + * \param session The session to be considered for session resumption. + * This must be a session previously exported via + * mbedtls_ssl_get_session(), and potentially serialized and + * deserialized through mbedtls_ssl_session_save() and + * mbedtls_ssl_session_load() in the meantime. + * + * \return \c 0 if successful. + * \return \c MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if the session + * could not be loaded because of an implementation limitation. + * This error is non-fatal, and has no observable effect on + * the SSL context or the session that was attempted to be loaded. + * \return Another negative error code on other kinds of failure. + * + * \sa mbedtls_ssl_get_session() + * \sa mbedtls_ssl_session_load() + */ +int mbedtls_ssl_set_session(mbedtls_ssl_context *ssl, const mbedtls_ssl_session *session); +#endif /* MBEDTLS_SSL_CLI_C */ + +/** + * \brief Load serialized session data into a session structure. + * On client, this can be used for loading saved sessions + * before resuming them with mbedtls_ssl_set_session(). + * On server, this can be used for alternative implementations + * of session cache or session tickets. + * + * \warning If a peer certificate chain is associated with the session, + * the serialized state will only contain the peer's + * end-entity certificate and the result of the chain + * verification (unless verification was disabled), but not + * the rest of the chain. + * + * \see mbedtls_ssl_session_save() + * \see mbedtls_ssl_set_session() + * + * \param session The session structure to be populated. It must have been + * initialised with mbedtls_ssl_session_init() but not + * populated yet. + * \param buf The buffer holding the serialized session data. It must be a + * readable buffer of at least \p len bytes. + * \param len The size of the serialized data in bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if input data is invalid. + * \return #MBEDTLS_ERR_SSL_VERSION_MISMATCH if the serialized data + * was generated in a different version or configuration of + * Mbed TLS. + * \return Another negative value for other kinds of errors (for + * example, unsupported features in the embedded certificate). + */ +int mbedtls_ssl_session_load(mbedtls_ssl_session *session, + const unsigned char *buf, + size_t len); + +/** + * \brief Save session structure as serialized data in a buffer. + * On client, this can be used for saving session data, + * potentially in non-volatile storage, for resuming later. + * On server, this can be used for alternative implementations + * of session cache or session tickets. + * + * \see mbedtls_ssl_session_load() + * + * \param session The session structure to be saved. + * \param buf The buffer to write the serialized data to. It must be a + * writeable buffer of at least \p buf_len bytes, or may be \c + * NULL if \p buf_len is \c 0. + * \param buf_len The number of bytes available for writing in \p buf. + * \param olen The size in bytes of the data that has been or would have + * been written. It must point to a valid \c size_t. + * + * \note \p olen is updated to the correct value regardless of + * whether \p buf_len was large enough. This makes it possible + * to determine the necessary size by calling this function + * with \p buf set to \c NULL and \p buf_len to \c 0. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL if \p buf is too small. + */ +int mbedtls_ssl_session_save(const mbedtls_ssl_session *session, + unsigned char *buf, + size_t buf_len, + size_t *olen); + +/** + * \brief Set the list of allowed ciphersuites and the preference + * order. First in the list has the highest preference. + * + * For TLS 1.2, the notion of ciphersuite determines both + * the key exchange mechanism and the suite of symmetric + * algorithms to be used during and after the handshake. + * + * For TLS 1.3 (in development), the notion of ciphersuite + * only determines the suite of symmetric algorithms to be + * used during and after the handshake, while key exchange + * mechanisms are configured separately. + * + * In Mbed TLS, ciphersuites for both TLS 1.2 and TLS 1.3 + * are configured via this function. For users of TLS 1.3, + * there will be separate API for the configuration of key + * exchange mechanisms. + * + * The list of ciphersuites passed to this function may + * contain a mixture of TLS 1.2 and TLS 1.3 ciphersuite + * identifiers. This is useful if negotiation of TLS 1.3 + * should be attempted, but a fallback to TLS 1.2 would + * be tolerated. + * + * \note By default, the server chooses its preferred + * ciphersuite among those that the client supports. If + * mbedtls_ssl_conf_preference_order() is called to prefer + * the client's preferences, the server instead chooses + * the client's preferred ciphersuite among those that + * the server supports. + * + * \warning The ciphersuites array \p ciphersuites is not copied. + * It must remain valid for the lifetime of the SSL + * configuration \p conf. + * + * \param conf The SSL configuration to modify. + * \param ciphersuites A 0-terminated list of IANA identifiers of supported + * ciphersuites, accessible through \c MBEDTLS_TLS_XXX + * and \c MBEDTLS_TLS1_3_XXX macros defined in + * ssl_ciphersuites.h. + */ +void mbedtls_ssl_conf_ciphersuites(mbedtls_ssl_config *conf, + const int *ciphersuites); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) +/** + * \brief Set the supported key exchange modes for TLS 1.3 connections. + * + * In contrast to TLS 1.2, the ciphersuite concept in TLS 1.3 does not + * include the choice of key exchange mechanism. It is therefore not + * covered by the API mbedtls_ssl_conf_ciphersuites(). See the + * documentation of mbedtls_ssl_conf_ciphersuites() for more + * information on the ciphersuite concept in TLS 1.2 and TLS 1.3. + * + * The present function is specific to TLS 1.3 and allows users to + * configure the set of supported key exchange mechanisms in TLS 1.3. + * + * \param conf The SSL configuration the change should apply to. + * \param kex_modes A bitwise combination of one or more of the following: + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK + * This flag enables pure-PSK key exchanges. + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL + * This flag enables combined PSK-ephemeral key exchanges. + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL + * This flag enables pure-ephemeral key exchanges. + * For convenience, the following pre-defined macros are + * available for combinations of the above: + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_ALL + * Includes all of pure-PSK, PSK-ephemeral and pure-ephemeral. + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL + * Includes both pure-PSK and combined PSK-ephemeral + * key exchanges, but excludes pure-ephemeral key exchanges. + * - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL + * Includes both pure-ephemeral and combined PSK-ephemeral + * key exchanges. + * + * \note If a PSK-based key exchange mode shall be supported, applications + * must also use the APIs mbedtls_ssl_conf_psk() or + * mbedtls_ssl_conf_psk_cb() or mbedtls_ssl_conf_psk_opaque() + * to configure the PSKs to be used. + * + * \note If a pure-ephemeral key exchange mode shall be supported, + * server-side applications must also provide a certificate via + * mbedtls_ssl_conf_own_cert(). + * + */ + +void mbedtls_ssl_conf_tls13_key_exchange_modes(mbedtls_ssl_config *conf, + const int kex_modes); +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +#define MBEDTLS_SSL_UNEXPECTED_CID_IGNORE 0 +#define MBEDTLS_SSL_UNEXPECTED_CID_FAIL 1 +/** + * \brief Specify the length of Connection IDs for incoming + * encrypted DTLS records, as well as the behaviour + * on unexpected CIDs. + * + * By default, the CID length is set to \c 0, + * and unexpected CIDs are silently ignored. + * + * \param conf The SSL configuration to modify. + * \param len The length in Bytes of the CID fields in encrypted + * DTLS records using the CID mechanism. This must + * not be larger than #MBEDTLS_SSL_CID_OUT_LEN_MAX. + * \param ignore_other_cids This determines the stack's behaviour when + * receiving a record with an unexpected CID. + * Possible values are: + * - #MBEDTLS_SSL_UNEXPECTED_CID_IGNORE + * In this case, the record is silently ignored. + * - #MBEDTLS_SSL_UNEXPECTED_CID_FAIL + * In this case, the stack fails with the specific + * error code #MBEDTLS_ERR_SSL_UNEXPECTED_CID. + * + * \note The CID specification allows implementations to either + * use a common length for all incoming connection IDs or + * allow variable-length incoming IDs. Mbed TLS currently + * requires a common length for all connections sharing the + * same SSL configuration; this allows simpler parsing of + * record headers. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if \p len + * is too large. + */ +int mbedtls_ssl_conf_cid(mbedtls_ssl_config *conf, size_t len, + int ignore_other_cids); +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Set the X.509 security profile used for verification + * + * \note The restrictions are enforced for all certificates in the + * chain. However, signatures in the handshake are not covered + * by this setting but by \b mbedtls_ssl_conf_sig_hashes(). + * + * \param conf SSL configuration + * \param profile Profile to use + */ +void mbedtls_ssl_conf_cert_profile(mbedtls_ssl_config *conf, + const mbedtls_x509_crt_profile *profile); + +/** + * \brief Set the data required to verify peer certificate + * + * \note See \c mbedtls_x509_crt_verify() for notes regarding the + * parameters ca_chain (maps to trust_ca for that function) + * and ca_crl. + * + * \param conf SSL configuration + * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs) + * \param ca_crl trusted CA CRLs + */ +void mbedtls_ssl_conf_ca_chain(mbedtls_ssl_config *conf, + mbedtls_x509_crt *ca_chain, + mbedtls_x509_crl *ca_crl); + +#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) +/** + * \brief Set DN hints sent to client in CertificateRequest message + * + * \note If not set, subject distinguished names (DNs) are taken + * from \c mbedtls_ssl_conf_ca_chain() + * or \c mbedtls_ssl_set_hs_ca_chain()) + * + * \param conf SSL configuration + * \param crt crt chain whose subject DNs are issuer DNs of client certs + * from which the client should select client peer certificate. + */ +static inline +void mbedtls_ssl_conf_dn_hints(mbedtls_ssl_config *conf, + const mbedtls_x509_crt *crt) +{ + conf->MBEDTLS_PRIVATE(dn_hints) = crt; +} +#endif /* MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED */ + +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) +/** + * \brief Set the trusted certificate callback. + * + * This API allows to register the set of trusted certificates + * through a callback, instead of a linked list as configured + * by mbedtls_ssl_conf_ca_chain(). + * + * This is useful for example in contexts where a large number + * of CAs are used, and the inefficiency of maintaining them + * in a linked list cannot be tolerated. It is also useful when + * the set of trusted CAs needs to be modified frequently. + * + * See the documentation of `mbedtls_x509_crt_ca_cb_t` for + * more information. + * + * \param conf The SSL configuration to register the callback with. + * \param f_ca_cb The trusted certificate callback to use when verifying + * certificate chains. + * \param p_ca_cb The context to be passed to \p f_ca_cb (for example, + * a reference to a trusted CA database). + * + * \note This API is incompatible with mbedtls_ssl_conf_ca_chain(): + * Any call to this function overwrites the values set through + * earlier calls to mbedtls_ssl_conf_ca_chain() or + * mbedtls_ssl_conf_ca_cb(). + * + * \note This API is incompatible with CA indication in + * CertificateRequest messages: A server-side SSL context which + * is bound to an SSL configuration that uses a CA callback + * configured via mbedtls_ssl_conf_ca_cb(), and which requires + * client authentication, will send an empty CA list in the + * corresponding CertificateRequest message. + * + * \note This API is incompatible with mbedtls_ssl_set_hs_ca_chain(): + * If an SSL context is bound to an SSL configuration which uses + * CA callbacks configured via mbedtls_ssl_conf_ca_cb(), then + * calls to mbedtls_ssl_set_hs_ca_chain() have no effect. + * + * \note The use of this API disables the use of restartable ECC + * during X.509 CRT signature verification (but doesn't affect + * other uses). + * + * \warning This API is incompatible with the use of CRLs. Any call to + * mbedtls_ssl_conf_ca_cb() unsets CRLs configured through + * earlier calls to mbedtls_ssl_conf_ca_chain(). + * + * \warning In multi-threaded environments, the callback \p f_ca_cb + * must be thread-safe, and it is the user's responsibility + * to guarantee this (for example through a mutex + * contained in the callback context pointed to by \p p_ca_cb). + */ +void mbedtls_ssl_conf_ca_cb(mbedtls_ssl_config *conf, + mbedtls_x509_crt_ca_cb_t f_ca_cb, + void *p_ca_cb); +#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ + +/** + * \brief Set own certificate chain and private key + * + * \note own_cert should contain in order from the bottom up your + * certificate chain. The top certificate (self-signed) + * can be omitted. + * + * \note On server, this function can be called multiple times to + * provision more than one cert/key pair (eg one ECDSA, one + * RSA with SHA-256, one RSA with SHA-1). An adequate + * certificate will be selected according to the client's + * advertised capabilities. In case multiple certificates are + * adequate, preference is given to the one set by the first + * call to this function, then second, etc. + * + * \note On client, only the first call has any effect. That is, + * only one client certificate can be provisioned. The + * server's preferences in its CertificateRequest message will + * be ignored and our only cert will be sent regardless of + * whether it matches those preferences - the server can then + * decide what it wants to do with it. + * + * \note The provided \p pk_key needs to match the public key in the + * first certificate in \p own_cert, or all handshakes using + * that certificate will fail. It is your responsibility + * to ensure that; this function will not perform any check. + * You may use mbedtls_pk_check_pair() in order to perform + * this check yourself, but be aware that this function can + * be computationally expensive on some key types. + * + * \param conf SSL configuration + * \param own_cert own public certificate chain + * \param pk_key own private key + * + * \return 0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED + */ +int mbedtls_ssl_conf_own_cert(mbedtls_ssl_config *conf, + mbedtls_x509_crt *own_cert, + mbedtls_pk_context *pk_key); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) +/** + * \brief Configure pre-shared keys (PSKs) and their + * identities to be used in PSK-based ciphersuites. + * + * Only one PSK can be registered, through either + * mbedtls_ssl_conf_psk() or mbedtls_ssl_conf_psk_opaque(). + * If you attempt to register more than one PSK, this function + * fails, though this may change in future versions, which + * may add support for multiple PSKs. + * + * \note This is mainly useful for clients. Servers will usually + * want to use \c mbedtls_ssl_conf_psk_cb() instead. + * + * \note A PSK set by \c mbedtls_ssl_set_hs_psk() in the PSK callback + * takes precedence over a PSK configured by this function. + * + * \param conf The SSL configuration to register the PSK with. + * \param psk The pointer to the pre-shared key to use. + * \param psk_len The length of the pre-shared key in bytes. + * \param psk_identity The pointer to the pre-shared key identity. + * \param psk_identity_len The length of the pre-shared key identity + * in bytes. + * + * \note The PSK and its identity are copied internally and + * hence need not be preserved by the caller for the lifetime + * of the SSL configuration. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no more PSKs + * can be configured. In this case, the old PSK(s) remain intact. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ssl_conf_psk(mbedtls_ssl_config *conf, + const unsigned char *psk, size_t psk_len, + const unsigned char *psk_identity, size_t psk_identity_len); + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * \brief Configure one or more opaque pre-shared keys (PSKs) and + * their identities to be used in PSK-based ciphersuites. + * + * Only one PSK can be registered, through either + * mbedtls_ssl_conf_psk() or mbedtls_ssl_conf_psk_opaque(). + * If you attempt to register more than one PSK, this function + * fails, though this may change in future versions, which + * may add support for multiple PSKs. + * + * \note This is mainly useful for clients. Servers will usually + * want to use \c mbedtls_ssl_conf_psk_cb() instead. + * + * \note An opaque PSK set by \c mbedtls_ssl_set_hs_psk_opaque() in + * the PSK callback takes precedence over an opaque PSK + * configured by this function. + * + * \param conf The SSL configuration to register the PSK with. + * \param psk The identifier of the key slot holding the PSK. + * Until \p conf is destroyed or this function is successfully + * called again, the key slot \p psk must be populated with a + * key of type PSA_ALG_CATEGORY_KEY_DERIVATION whose policy + * allows its use for the key derivation algorithm applied + * in the handshake. + * \param psk_identity The pointer to the pre-shared key identity. + * \param psk_identity_len The length of the pre-shared key identity + * in bytes. + * + * \note The PSK identity hint is copied internally and hence need + * not be preserved by the caller for the lifetime of the + * SSL configuration. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no more PSKs + * can be configured. In this case, the old PSK(s) remain intact. + * \return Another negative error code on other kinds of failure. + */ +int mbedtls_ssl_conf_psk_opaque(mbedtls_ssl_config *conf, + mbedtls_svc_key_id_t psk, + const unsigned char *psk_identity, + size_t psk_identity_len); +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/** + * \brief Set the pre-shared Key (PSK) for the current handshake. + * + * \note This should only be called inside the PSK callback, + * i.e. the function passed to \c mbedtls_ssl_conf_psk_cb(). + * + * \note A PSK set by this function takes precedence over a PSK + * configured by \c mbedtls_ssl_conf_psk(). + * + * \param ssl The SSL context to configure a PSK for. + * \param psk The pointer to the pre-shared key. + * \param psk_len The length of the pre-shared key in bytes. + * + * \return \c 0 if successful. + * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. + */ +int mbedtls_ssl_set_hs_psk(mbedtls_ssl_context *ssl, + const unsigned char *psk, size_t psk_len); + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * \brief Set an opaque pre-shared Key (PSK) for the current handshake. + * + * \note This should only be called inside the PSK callback, + * i.e. the function passed to \c mbedtls_ssl_conf_psk_cb(). + * + * \note An opaque PSK set by this function takes precedence over an + * opaque PSK configured by \c mbedtls_ssl_conf_psk_opaque(). + * + * \param ssl The SSL context to configure a PSK for. + * \param psk The identifier of the key slot holding the PSK. + * For the duration of the current handshake, the key slot + * must be populated with a key of type + * PSA_ALG_CATEGORY_KEY_DERIVATION whose policy allows its + * use for the key derivation algorithm + * applied in the handshake. + * + * \return \c 0 if successful. + * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. + */ +int mbedtls_ssl_set_hs_psk_opaque(mbedtls_ssl_context *ssl, + mbedtls_svc_key_id_t psk); +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Set the PSK callback (server-side only). + * + * If set, the PSK callback is called for each + * handshake where a PSK-based ciphersuite was negotiated. + * The caller provides the identity received and wants to + * receive the actual PSK data and length. + * + * The callback has the following parameters: + * - \c void*: The opaque pointer \p p_psk. + * - \c mbedtls_ssl_context*: The SSL context to which + * the operation applies. + * - \c const unsigned char*: The PSK identity + * selected by the client. + * - \c size_t: The length of the PSK identity + * selected by the client. + * + * If a valid PSK identity is found, the callback should use + * \c mbedtls_ssl_set_hs_psk() or + * \c mbedtls_ssl_set_hs_psk_opaque() + * on the SSL context to set the correct PSK and return \c 0. + * Any other return value will result in a denied PSK identity. + * + * \note A dynamic PSK (i.e. set by the PSK callback) takes + * precedence over a static PSK (i.e. set by + * \c mbedtls_ssl_conf_psk() or + * \c mbedtls_ssl_conf_psk_opaque()). + * This means that if you set a PSK callback using this + * function, you don't need to set a PSK using + * \c mbedtls_ssl_conf_psk() or + * \c mbedtls_ssl_conf_psk_opaque()). + * + * \param conf The SSL configuration to register the callback with. + * \param f_psk The callback for selecting and setting the PSK based + * in the PSK identity chosen by the client. + * \param p_psk A pointer to an opaque structure to be passed to + * the callback, for example a PSK store. + */ +void mbedtls_ssl_conf_psk_cb(mbedtls_ssl_config *conf, + int (*f_psk)(void *, mbedtls_ssl_context *, const unsigned char *, + size_t), + void *p_psk); +#endif /* MBEDTLS_SSL_SRV_C */ +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ + +#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Set the Diffie-Hellman public P and G values + * from big-endian binary presentations. + * (Default values: MBEDTLS_DHM_RFC3526_MODP_2048_[PG]_BIN) + * + * \param conf SSL configuration + * \param dhm_P Diffie-Hellman-Merkle modulus in big-endian binary form + * \param P_len Length of DHM modulus + * \param dhm_G Diffie-Hellman-Merkle generator in big-endian binary form + * \param G_len Length of DHM generator + * + * \return 0 if successful + */ +int mbedtls_ssl_conf_dh_param_bin(mbedtls_ssl_config *conf, + const unsigned char *dhm_P, size_t P_len, + const unsigned char *dhm_G, size_t G_len); + +/** + * \brief Set the Diffie-Hellman public P and G values, + * read from existing context (server-side only) + * + * \param conf SSL configuration + * \param dhm_ctx Diffie-Hellman-Merkle context + * + * \return 0 if successful + */ +int mbedtls_ssl_conf_dh_param_ctx(mbedtls_ssl_config *conf, mbedtls_dhm_context *dhm_ctx); +#endif /* MBEDTLS_DHM_C && defined(MBEDTLS_SSL_SRV_C) */ + +#if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_CLI_C) +/** + * \brief Set the minimum length for Diffie-Hellman parameters. + * (Client-side only.) + * (Default: 1024 bits.) + * + * \param conf SSL configuration + * \param bitlen Minimum bit length of the DHM prime + */ +void mbedtls_ssl_conf_dhm_min_bitlen(mbedtls_ssl_config *conf, + unsigned int bitlen); +#endif /* MBEDTLS_DHM_C && MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_ECP_C) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Set the allowed curves in order of preference. + * + * On server: this only affects selection of the ECDHE curve; + * the curves used for ECDH and ECDSA are determined by the + * list of available certificates instead. + * + * On client: this affects the list of curves offered for any + * use. The server can override our preference order. + * + * Both sides: limits the set of curves accepted for use in + * ECDHE and in the peer's end-entity certificate. + * + * \deprecated Superseded by mbedtls_ssl_conf_groups(). + * + * \note This has no influence on which curves are allowed inside the + * certificate chains, see \c mbedtls_ssl_conf_cert_profile() + * for that. For the end-entity certificate however, the key + * will be accepted only if it is allowed both by this list + * and by the cert profile. + * + * \note This list should be ordered by decreasing preference + * (preferred curve first). + * + * \note The default list is the same set of curves that + * #mbedtls_x509_crt_profile_default allows, plus + * ECDHE-only curves selected according to the same criteria. + * The order favors curves with the lowest resource usage. + * + * \note New minor versions of Mbed TLS may extend this list, + * for example if new curves are added to the library. + * New minor versions of Mbed TLS will not remove items + * from this list unless serious security concerns require it. + * New minor versions of Mbed TLS may change the order in + * keeping with the general principle of favoring the lowest + * resource usage. + * + * \param conf SSL configuration + * \param curves Ordered list of allowed curves, + * terminated by MBEDTLS_ECP_DP_NONE. + */ +void MBEDTLS_DEPRECATED mbedtls_ssl_conf_curves(mbedtls_ssl_config *conf, + const mbedtls_ecp_group_id *curves); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_ECP_C */ + +/** + * \brief Set the allowed groups in order of preference. + * + * On server: This only affects the choice of key agreement mechanism + * + * On client: this affects the list of groups offered for any + * use. The server can override our preference order. + * + * Both sides: limits the set of groups accepted for use in + * key sharing. + * + * \note This function replaces the deprecated mbedtls_ssl_conf_curves(), + * which only allows ECP curves to be configured. + * + * \note The most recent invocation of either mbedtls_ssl_conf_curves() + * or mbedtls_ssl_conf_groups() nullifies all previous invocations + * of both. + * + * \note This list should be ordered by decreasing preference + * (preferred group first). + * + * \note When this function is not called, a default list is used, + * consisting of all supported curves at 255 bits and above, + * and all supported finite fields at 2048 bits and above. + * The order favors groups with the lowest resource usage. + * + * \note New minor versions of Mbed TLS will not remove items + * from the default list unless serious security concerns require it. + * New minor versions of Mbed TLS may change the order in + * keeping with the general principle of favoring the lowest + * resource usage. + * + * \param conf SSL configuration + * \param groups List of allowed groups ordered by preference, terminated by 0. + * Must contain valid IANA NamedGroup IDs (provided via either an integer + * or using MBEDTLS_TLS1_3_NAMED_GROUP_XXX macros). + */ +void mbedtls_ssl_conf_groups(mbedtls_ssl_config *conf, + const uint16_t *groups); + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) && defined(MBEDTLS_SSL_PROTO_TLS1_2) +/** + * \brief Set the allowed hashes for signatures during the handshake. + * + * \note This only affects which hashes are offered and can be used + * for signatures during the handshake. Hashes for message + * authentication and the TLS PRF are controlled by the + * ciphersuite, see \c mbedtls_ssl_conf_ciphersuites(). Hashes + * used for certificate signature are controlled by the + * verification profile, see \c mbedtls_ssl_conf_cert_profile(). + * + * \note This list should be ordered by decreasing preference + * (preferred hash first). + * + * \note By default, all supported hashes whose length is at least + * 256 bits are allowed. This is the same set as the default + * for certificate verification + * (#mbedtls_x509_crt_profile_default). + * The preference order is currently unspecified and may + * change in future versions. + * + * \note New minor versions of Mbed TLS may extend this list, + * for example if new curves are added to the library. + * New minor versions of Mbed TLS will not remove items + * from this list unless serious security concerns require it. + * + * \param conf SSL configuration + * \param hashes Ordered list of allowed signature hashes, + * terminated by \c MBEDTLS_MD_NONE. + */ +void MBEDTLS_DEPRECATED mbedtls_ssl_conf_sig_hashes(mbedtls_ssl_config *conf, + const int *hashes); +#endif /* !MBEDTLS_DEPRECATED_REMOVED && MBEDTLS_SSL_PROTO_TLS1_2 */ + +/** + * \brief Configure allowed signature algorithms for use in TLS 1.3 + * + * \param conf The SSL configuration to use. + * \param sig_algs List of allowed IANA values for TLS 1.3 signature algorithms, + * terminated by \c MBEDTLS_TLS1_3_SIG_NONE. The list must remain + * available throughout the lifetime of the conf object. Supported + * values are available as \c MBEDTLS_TLS1_3_SIG_XXXX + */ +void mbedtls_ssl_conf_sig_algs(mbedtls_ssl_config *conf, + const uint16_t *sig_algs); +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Set or reset the hostname to check against the received + * server certificate. It sets the ServerName TLS extension, + * too, if that extension is enabled. (client-side only) + * + * \param ssl SSL context + * \param hostname the server hostname, may be NULL to clear hostname + + * \note Maximum hostname length MBEDTLS_SSL_MAX_HOST_NAME_LEN. + * + * \return 0 if successful, MBEDTLS_ERR_SSL_ALLOC_FAILED on + * allocation failure, MBEDTLS_ERR_SSL_BAD_INPUT_DATA on + * too long input hostname. + * + * Hostname set to the one provided on success (cleared + * when NULL). On allocation failure hostname is cleared. + * On too long input failure, old hostname is unchanged. + */ +int mbedtls_ssl_set_hostname(mbedtls_ssl_context *ssl, const char *hostname); + +/** + * \brief Get the hostname that checked against the received + * server certificate. It is used to set the ServerName + * TLS extension, too, if that extension is enabled. + * (client-side only) + * + * \param ssl SSL context + * + * \return const pointer to the hostname value + */ +static inline const char *mbedtls_ssl_get_hostname(mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(hostname); +} +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) +/** + * \brief Retrieve SNI extension value for the current handshake. + * Available in \c f_cert_cb of \c mbedtls_ssl_conf_cert_cb(), + * this is the same value passed to \c f_sni callback of + * \c mbedtls_ssl_conf_sni() and may be used instead of + * \c mbedtls_ssl_conf_sni(). + * + * \param ssl SSL context + * \param name_len pointer into which to store length of returned value. + * 0 if SNI extension is not present or not yet processed. + * + * \return const pointer to SNI extension value. + * - value is valid only when called in \c f_cert_cb + * registered with \c mbedtls_ssl_conf_cert_cb(). + * - value is NULL if SNI extension is not present. + * - value is not '\0'-terminated. Use \c name_len for len. + * - value must not be freed. + */ +const unsigned char *mbedtls_ssl_get_hs_sni(mbedtls_ssl_context *ssl, + size_t *name_len); + +/** + * \brief Set own certificate and key for the current handshake + * + * \note Same as \c mbedtls_ssl_conf_own_cert() but for use within + * the SNI callback or the certificate selection callback. + * + * \note Passing null \c own_cert clears the certificate list for + * the current handshake. + * + * \param ssl SSL context + * \param own_cert own public certificate chain + * \param pk_key own private key + * + * \return 0 on success or MBEDTLS_ERR_SSL_ALLOC_FAILED + */ +int mbedtls_ssl_set_hs_own_cert(mbedtls_ssl_context *ssl, + mbedtls_x509_crt *own_cert, + mbedtls_pk_context *pk_key); + +/** + * \brief Set the data required to verify peer certificate for the + * current handshake + * + * \note Same as \c mbedtls_ssl_conf_ca_chain() but for use within + * the SNI callback or the certificate selection callback. + * + * \param ssl SSL context + * \param ca_chain trusted CA chain (meaning all fully trusted top-level CAs) + * \param ca_crl trusted CA CRLs + */ +void mbedtls_ssl_set_hs_ca_chain(mbedtls_ssl_context *ssl, + mbedtls_x509_crt *ca_chain, + mbedtls_x509_crl *ca_crl); + +#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) +/** + * \brief Set DN hints sent to client in CertificateRequest message + * + * \note Same as \c mbedtls_ssl_conf_dn_hints() but for use within + * the SNI callback or the certificate selection callback. + * + * \param ssl SSL context + * \param crt crt chain whose subject DNs are issuer DNs of client certs + * from which the client should select client peer certificate. + */ +void mbedtls_ssl_set_hs_dn_hints(mbedtls_ssl_context *ssl, + const mbedtls_x509_crt *crt); +#endif /* MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED */ + +/** + * \brief Set authmode for the current handshake. + * + * \note Same as \c mbedtls_ssl_conf_authmode() but for use within + * the SNI callback or the certificate selection callback. + * + * \param ssl SSL context + * \param authmode MBEDTLS_SSL_VERIFY_NONE, MBEDTLS_SSL_VERIFY_OPTIONAL or + * MBEDTLS_SSL_VERIFY_REQUIRED + */ +void mbedtls_ssl_set_hs_authmode(mbedtls_ssl_context *ssl, + int authmode); + +/** + * \brief Set server side ServerName TLS extension callback + * (optional, server-side only). + * + * If set, the ServerName callback is called whenever the + * server receives a ServerName TLS extension from the client + * during a handshake. The ServerName callback has the + * following parameters: (void *parameter, mbedtls_ssl_context *ssl, + * const unsigned char *hostname, size_t len). If a suitable + * certificate is found, the callback must set the + * certificate(s) and key(s) to use with \c + * mbedtls_ssl_set_hs_own_cert() (can be called repeatedly), + * and may optionally adjust the CA and associated CRL with \c + * mbedtls_ssl_set_hs_ca_chain() as well as the client + * authentication mode with \c mbedtls_ssl_set_hs_authmode(), + * then must return 0. If no matching name is found, the + * callback may return non-zero to abort the handshake. + * + * \param conf SSL configuration + * \param f_sni verification function + * \param p_sni verification parameter + */ +void mbedtls_ssl_conf_sni(mbedtls_ssl_config *conf, + int (*f_sni)(void *, mbedtls_ssl_context *, const unsigned char *, + size_t), + void *p_sni); +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) +/** + * \brief Set the EC J-PAKE password for current handshake. + * + * \note An internal copy is made, and destroyed as soon as the + * handshake is completed, or when the SSL context is reset or + * freed. + * + * \note The SSL context needs to be already set up. The right place + * to call this function is between \c mbedtls_ssl_setup() or + * \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake(). + * Password cannot be empty (see RFC 8236). + * + * \param ssl SSL context + * \param pw EC J-PAKE password (pre-shared secret). It cannot be empty + * \param pw_len length of pw in bytes + * + * \return 0 on success, or a negative error code. + */ +int mbedtls_ssl_set_hs_ecjpake_password(mbedtls_ssl_context *ssl, + const unsigned char *pw, + size_t pw_len); + +/** + * \brief Set the EC J-PAKE opaque password for current handshake. + * + * \note The key must remain valid until the handshake is over. + * + * \note The SSL context needs to be already set up. The right place + * to call this function is between \c mbedtls_ssl_setup() or + * \c mbedtls_ssl_reset() and \c mbedtls_ssl_handshake(). + * + * \param ssl SSL context + * \param pwd EC J-PAKE opaque password + * + * \return 0 on success, or a negative error code. + */ +int mbedtls_ssl_set_hs_ecjpake_password_opaque(mbedtls_ssl_context *ssl, + mbedtls_svc_key_id_t pwd); +#endif /*MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ + +#if defined(MBEDTLS_SSL_ALPN) +/** + * \brief Set the supported Application Layer Protocols. + * + * \param conf SSL configuration + * \param protos Pointer to a NULL-terminated list of supported protocols, + * in decreasing preference order. The pointer to the list is + * recorded by the library for later reference as required, so + * the lifetime of the table must be at least as long as the + * lifetime of the SSL configuration structure. + * + * \return 0 on success, or MBEDTLS_ERR_SSL_BAD_INPUT_DATA. + */ +int mbedtls_ssl_conf_alpn_protocols(mbedtls_ssl_config *conf, const char **protos); + +/** + * \brief Get the name of the negotiated Application Layer Protocol. + * This function should be called after the handshake is + * completed. + * + * \param ssl SSL context + * + * \return Protocol name, or NULL if no protocol was negotiated. + */ +const char *mbedtls_ssl_get_alpn_protocol(const mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_ALPN */ + +#if defined(MBEDTLS_SSL_DTLS_SRTP) +#if defined(MBEDTLS_DEBUG_C) +static inline const char *mbedtls_ssl_get_srtp_profile_as_string(mbedtls_ssl_srtp_profile profile) +{ + switch (profile) { + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: + return "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80"; + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: + return "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32"; + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: + return "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80"; + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: + return "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32"; + default: break; + } + return ""; +} +#endif /* MBEDTLS_DEBUG_C */ +/** + * \brief Manage support for mki(master key id) value + * in use_srtp extension. + * MKI is an optional part of SRTP used for key management + * and re-keying. See RFC3711 section 3.1 for details. + * The default value is + * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED. + * + * \param conf The SSL configuration to manage mki support. + * \param support_mki_value Enable or disable mki usage. Values are + * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED + * or #MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED. + */ +void mbedtls_ssl_conf_srtp_mki_value_supported(mbedtls_ssl_config *conf, + int support_mki_value); + +/** + * \brief Set the supported DTLS-SRTP protection profiles. + * + * \param conf SSL configuration + * \param profiles Pointer to a List of MBEDTLS_TLS_SRTP_UNSET terminated + * supported protection profiles + * in decreasing preference order. + * The pointer to the list is recorded by the library + * for later reference as required, so the lifetime + * of the table must be at least as long as the lifetime + * of the SSL configuration structure. + * The list must not hold more than + * MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH elements + * (excluding the terminating MBEDTLS_TLS_SRTP_UNSET). + * + * \return 0 on success + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA when the list of + * protection profiles is incorrect. + */ +int mbedtls_ssl_conf_dtls_srtp_protection_profiles + (mbedtls_ssl_config *conf, + const mbedtls_ssl_srtp_profile *profiles); + +/** + * \brief Set the mki_value for the current DTLS-SRTP session. + * + * \param ssl SSL context to use. + * \param mki_value The MKI value to set. + * \param mki_len The length of the MKI value. + * + * \note This function is relevant on client side only. + * The server discovers the mki value during handshake. + * A mki value set on server side using this function + * is ignored. + * + * \return 0 on success + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE + */ +int mbedtls_ssl_dtls_srtp_set_mki_value(mbedtls_ssl_context *ssl, + unsigned char *mki_value, + uint16_t mki_len); +/** + * \brief Get the negotiated DTLS-SRTP information: + * Protection profile and MKI value. + * + * \warning This function must be called after the handshake is + * completed. The value returned by this function must + * not be trusted or acted upon before the handshake completes. + * + * \param ssl The SSL context to query. + * \param dtls_srtp_info The negotiated DTLS-SRTP information: + * - Protection profile in use. + * A direct mapping of the iana defined value for protection + * profile on an uint16_t. + http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml + * #MBEDTLS_TLS_SRTP_UNSET if the use of SRTP was not negotiated + * or peer's Hello packet was not parsed yet. + * - mki size and value( if size is > 0 ). + */ +void mbedtls_ssl_get_dtls_srtp_negotiation_result(const mbedtls_ssl_context *ssl, + mbedtls_dtls_srtp_info *dtls_srtp_info); +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Set the maximum supported version sent from the client side + * and/or accepted at the server side. + * + * See also the documentation of mbedtls_ssl_conf_min_version(). + * + * \note This ignores ciphersuites from higher versions. + * + * \note This function is deprecated and has been replaced by + * \c mbedtls_ssl_conf_max_tls_version(). + * + * \param conf SSL configuration + * \param major Major version number (#MBEDTLS_SSL_MAJOR_VERSION_3) + * \param minor Minor version number + * (#MBEDTLS_SSL_MINOR_VERSION_3 for (D)TLS 1.2, + * #MBEDTLS_SSL_MINOR_VERSION_4 for TLS 1.3) + */ +void MBEDTLS_DEPRECATED mbedtls_ssl_conf_max_version(mbedtls_ssl_config *conf, int major, + int minor); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Set the maximum supported version sent from the client side + * and/or accepted at the server side. + * + * \note After the handshake, you can call + * mbedtls_ssl_get_version_number() to see what version was + * negotiated. + * + * \param conf SSL configuration + * \param tls_version TLS protocol version number (\c mbedtls_ssl_protocol_version) + * (#MBEDTLS_SSL_VERSION_UNKNOWN is not valid) + */ +static inline void mbedtls_ssl_conf_max_tls_version(mbedtls_ssl_config *conf, + mbedtls_ssl_protocol_version tls_version) +{ + conf->MBEDTLS_PRIVATE(max_tls_version) = tls_version; +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Set the minimum accepted SSL/TLS protocol version + * + * \note By default, all supported versions are accepted. + * Future versions of the library may disable older + * protocol versions by default if they become deprecated. + * + * \note The following versions are supported (if enabled at + * compile time): + * - (D)TLS 1.2: \p major = #MBEDTLS_SSL_MAJOR_VERSION_3, + * \p minor = #MBEDTLS_SSL_MINOR_VERSION_3 + * - TLS 1.3: \p major = #MBEDTLS_SSL_MAJOR_VERSION_3, + * \p minor = #MBEDTLS_SSL_MINOR_VERSION_4 + * + * Note that the numbers in the constant names are the + * TLS internal protocol numbers, and the minor versions + * differ by one from the human-readable versions! + * + * \note Input outside of the SSL_MAX_XXXXX_VERSION and + * SSL_MIN_XXXXX_VERSION range is ignored. + * + * \note After the handshake, you can call + * mbedtls_ssl_get_version_number() to see what version was + * negotiated. + * + * \note This function is deprecated and has been replaced by + * \c mbedtls_ssl_conf_min_tls_version(). + * + * \param conf SSL configuration + * \param major Major version number (#MBEDTLS_SSL_MAJOR_VERSION_3) + * \param minor Minor version number + * (#MBEDTLS_SSL_MINOR_VERSION_3 for (D)TLS 1.2, + * #MBEDTLS_SSL_MINOR_VERSION_4 for TLS 1.3) + */ +void MBEDTLS_DEPRECATED mbedtls_ssl_conf_min_version(mbedtls_ssl_config *conf, int major, + int minor); +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** + * \brief Set the minimum supported version sent from the client side + * and/or accepted at the server side. + * + * \note After the handshake, you can call + * mbedtls_ssl_get_version_number() to see what version was + * negotiated. + * + * \param conf SSL configuration + * \param tls_version TLS protocol version number (\c mbedtls_ssl_protocol_version) + * (#MBEDTLS_SSL_VERSION_UNKNOWN is not valid) + */ +static inline void mbedtls_ssl_conf_min_tls_version(mbedtls_ssl_config *conf, + mbedtls_ssl_protocol_version tls_version) +{ + conf->MBEDTLS_PRIVATE(min_tls_version) = tls_version; +} + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) +/** + * \brief Enable or disable Encrypt-then-MAC + * (Default: MBEDTLS_SSL_ETM_ENABLED) + * + * \note This should always be enabled, it is a security + * improvement, and should not cause any interoperability + * issue (used only if the peer supports it too). + * + * \param conf SSL configuration + * \param etm MBEDTLS_SSL_ETM_ENABLED or MBEDTLS_SSL_ETM_DISABLED + */ +void mbedtls_ssl_conf_encrypt_then_mac(mbedtls_ssl_config *conf, char etm); +#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) +/** + * \brief Enable or disable Extended Master Secret negotiation. + * (Default: MBEDTLS_SSL_EXTENDED_MS_ENABLED) + * + * \note This should always be enabled, it is a security fix to the + * protocol, and should not cause any interoperability issue + * (used only if the peer supports it too). + * + * \param conf SSL configuration + * \param ems MBEDTLS_SSL_EXTENDED_MS_ENABLED or MBEDTLS_SSL_EXTENDED_MS_DISABLED + */ +void mbedtls_ssl_conf_extended_master_secret(mbedtls_ssl_config *conf, char ems); +#endif /* MBEDTLS_SSL_EXTENDED_MASTER_SECRET */ + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Whether to send a list of acceptable CAs in + * CertificateRequest messages. + * (Default: do send) + * + * \param conf SSL configuration + * \param cert_req_ca_list MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED or + * MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED + */ +void mbedtls_ssl_conf_cert_req_ca_list(mbedtls_ssl_config *conf, + char cert_req_ca_list); +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) +/** + * \brief Set the maximum fragment length to emit and/or negotiate. + * (Typical: the smaller of #MBEDTLS_SSL_IN_CONTENT_LEN and + * #MBEDTLS_SSL_OUT_CONTENT_LEN, usually `2^14` bytes) + * (Server: set maximum fragment length to emit, + * usually negotiated by the client during handshake) + * (Client: set maximum fragment length to emit *and* + * negotiate with the server during handshake) + * (Default: #MBEDTLS_SSL_MAX_FRAG_LEN_NONE) + * + * \note On the client side, the maximum fragment length extension + * *will not* be used, unless the maximum fragment length has + * been set via this function to a value different than + * #MBEDTLS_SSL_MAX_FRAG_LEN_NONE. + * + * \note With TLS, this currently only affects ApplicationData (sent + * with \c mbedtls_ssl_read()), not handshake messages. + * With DTLS, this affects both ApplicationData and handshake. + * + * \note This sets the maximum length for a record's payload, + * excluding record overhead that will be added to it, see + * \c mbedtls_ssl_get_record_expansion(). + * + * \note For DTLS, it is also possible to set a limit for the total + * size of datagrams passed to the transport layer, including + * record overhead, see \c mbedtls_ssl_set_mtu(). + * + * \param conf SSL configuration + * \param mfl_code Code for maximum fragment length (allowed values: + * MBEDTLS_SSL_MAX_FRAG_LEN_512, MBEDTLS_SSL_MAX_FRAG_LEN_1024, + * MBEDTLS_SSL_MAX_FRAG_LEN_2048, MBEDTLS_SSL_MAX_FRAG_LEN_4096) + * + * \return 0 if successful or MBEDTLS_ERR_SSL_BAD_INPUT_DATA + */ +int mbedtls_ssl_conf_max_frag_len(mbedtls_ssl_config *conf, unsigned char mfl_code); +#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Pick the ciphersuites order according to the second parameter + * in the SSL Server module (MBEDTLS_SSL_SRV_C). + * (Default, if never called: MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER) + * + * \param conf SSL configuration + * \param order Server or client (MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_SERVER + * or MBEDTLS_SSL_SRV_CIPHERSUITE_ORDER_CLIENT) + */ +void mbedtls_ssl_conf_preference_order(mbedtls_ssl_config *conf, int order); +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_SSL_CLI_C) +/** + * \brief Enable / Disable session tickets (client only). + * (Default: MBEDTLS_SSL_SESSION_TICKETS_ENABLED.) + * + * \note On server, use \c mbedtls_ssl_conf_session_tickets_cb(). + * + * \param conf SSL configuration + * \param use_tickets Enable or disable (MBEDTLS_SSL_SESSION_TICKETS_ENABLED or + * MBEDTLS_SSL_SESSION_TICKETS_DISABLED) + */ +void mbedtls_ssl_conf_session_tickets(mbedtls_ssl_config *conf, int use_tickets); +#endif /* MBEDTLS_SSL_SESSION_TICKETS && + MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_SSL_SRV_C) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_3) +/** + * \brief Number of NewSessionTicket messages for the server to send + * after handshake completion. + * + * \note The default value is + * \c MBEDTLS_SSL_TLS1_3_DEFAULT_NEW_SESSION_TICKETS. + * + * \note In case of a session resumption, this setting only partially apply. + * At most one ticket is sent in that case to just renew the pool of + * tickets of the client. The rationale is to avoid the number of + * tickets on the server to become rapidly out of control when the + * server has the same configuration for all its connection instances. + * + * \param conf SSL configuration + * \param num_tickets Number of NewSessionTicket. + * + */ +void mbedtls_ssl_conf_new_session_tickets(mbedtls_ssl_config *conf, + uint16_t num_tickets); +#endif /* MBEDTLS_SSL_SESSION_TICKETS && + MBEDTLS_SSL_SRV_C && + MBEDTLS_SSL_PROTO_TLS1_3*/ + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +/** + * \brief Enable / Disable renegotiation support for connection when + * initiated by peer + * (Default: MBEDTLS_SSL_RENEGOTIATION_DISABLED) + * + * \warning It is recommended to always disable renegotiation unless you + * know you need it and you know what you're doing. In the + * past, there have been several issues associated with + * renegotiation or a poor understanding of its properties. + * + * \note Server-side, enabling renegotiation also makes the server + * susceptible to a resource DoS by a malicious client. + * + * \param conf SSL configuration + * \param renegotiation Enable or disable (MBEDTLS_SSL_RENEGOTIATION_ENABLED or + * MBEDTLS_SSL_RENEGOTIATION_DISABLED) + */ +void mbedtls_ssl_conf_renegotiation(mbedtls_ssl_config *conf, int renegotiation); +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +/** + * \brief Prevent or allow legacy renegotiation. + * (Default: MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION) + * + * MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION allows connections to + * be established even if the peer does not support + * secure renegotiation, but does not allow renegotiation + * to take place if not secure. + * (Interoperable and secure option) + * + * MBEDTLS_SSL_LEGACY_ALLOW_RENEGOTIATION allows renegotiations + * with non-upgraded peers. Allowing legacy renegotiation + * makes the connection vulnerable to specific man in the + * middle attacks. (See RFC 5746) + * (Most interoperable and least secure option) + * + * MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE breaks off connections + * if peer does not support secure renegotiation. Results + * in interoperability issues with non-upgraded peers + * that do not support renegotiation altogether. + * (Most secure option, interoperability issues) + * + * \param conf SSL configuration + * \param allow_legacy Prevent or allow (SSL_NO_LEGACY_RENEGOTIATION, + * SSL_ALLOW_LEGACY_RENEGOTIATION or + * MBEDTLS_SSL_LEGACY_BREAK_HANDSHAKE) + */ +void mbedtls_ssl_conf_legacy_renegotiation(mbedtls_ssl_config *conf, int allow_legacy); + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +/** + * \brief Enforce renegotiation requests. + * (Default: enforced, max_records = 16) + * + * When we request a renegotiation, the peer can comply or + * ignore the request. This function allows us to decide + * whether to enforce our renegotiation requests by closing + * the connection if the peer doesn't comply. + * + * However, records could already be in transit from the peer + * when the request is emitted. In order to increase + * reliability, we can accept a number of records before the + * expected handshake records. + * + * The optimal value is highly dependent on the specific usage + * scenario. + * + * \note With DTLS and server-initiated renegotiation, the + * HelloRequest is retransmitted every time mbedtls_ssl_read() times + * out or receives Application Data, until: + * - max_records records have beens seen, if it is >= 0, or + * - the number of retransmits that would happen during an + * actual handshake has been reached. + * Please remember the request might be lost a few times + * if you consider setting max_records to a really low value. + * + * \warning On client, the grace period can only happen during + * mbedtls_ssl_read(), as opposed to mbedtls_ssl_write() and mbedtls_ssl_renegotiate() + * which always behave as if max_record was 0. The reason is, + * if we receive application data from the server, we need a + * place to write it, which only happens during mbedtls_ssl_read(). + * + * \param conf SSL configuration + * \param max_records Use MBEDTLS_SSL_RENEGOTIATION_NOT_ENFORCED if you don't want to + * enforce renegotiation, or a non-negative value to enforce + * it but allow for a grace period of max_records records. + */ +void mbedtls_ssl_conf_renegotiation_enforced(mbedtls_ssl_config *conf, int max_records); + +/** + * \brief Set record counter threshold for periodic renegotiation. + * (Default: 2^48 - 1) + * + * Renegotiation is automatically triggered when a record + * counter (outgoing or incoming) crosses the defined + * threshold. The default value is meant to prevent the + * connection from being closed when the counter is about to + * reached its maximal value (it is not allowed to wrap). + * + * Lower values can be used to enforce policies such as "keys + * must be refreshed every N packets with cipher X". + * + * The renegotiation period can be disabled by setting + * conf->disable_renegotiation to + * MBEDTLS_SSL_RENEGOTIATION_DISABLED. + * + * \note When the configured transport is + * MBEDTLS_SSL_TRANSPORT_DATAGRAM the maximum renegotiation + * period is 2^48 - 1, and for MBEDTLS_SSL_TRANSPORT_STREAM, + * the maximum renegotiation period is 2^64 - 1. + * + * \param conf SSL configuration + * \param period The threshold value: a big-endian 64-bit number. + */ +void mbedtls_ssl_conf_renegotiation_period(mbedtls_ssl_config *conf, + const unsigned char period[8]); +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +/** + * \brief Check if there is data already read from the + * underlying transport but not yet processed. + * + * \param ssl SSL context + * + * \return 0 if nothing's pending, 1 otherwise. + * + * \note This is different in purpose and behaviour from + * \c mbedtls_ssl_get_bytes_avail in that it considers + * any kind of unprocessed data, not only unread + * application data. If \c mbedtls_ssl_get_bytes + * returns a non-zero value, this function will + * also signal pending data, but the converse does + * not hold. For example, in DTLS there might be + * further records waiting to be processed from + * the current underlying transport's datagram. + * + * \note If this function returns 1 (data pending), this + * does not imply that a subsequent call to + * \c mbedtls_ssl_read will provide any data; + * e.g., the unprocessed data might turn out + * to be an alert or a handshake message. + * + * \note This function is useful in the following situation: + * If the SSL/TLS module successfully returns from an + * operation - e.g. a handshake or an application record + * read - and you're awaiting incoming data next, you + * must not immediately idle on the underlying transport + * to have data ready, but you need to check the value + * of this function first. The reason is that the desired + * data might already be read but not yet processed. + * If, in contrast, a previous call to the SSL/TLS module + * returned MBEDTLS_ERR_SSL_WANT_READ, it is not necessary + * to call this function, as the latter error code entails + * that all internal data has been processed. + * + */ +int mbedtls_ssl_check_pending(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the number of application data bytes + * remaining to be read from the current record. + * + * \param ssl SSL context + * + * \return How many bytes are available in the application + * data record read buffer. + * + * \note When working over a datagram transport, this is + * useful to detect the current datagram's boundary + * in case \c mbedtls_ssl_read has written the maximal + * amount of data fitting into the input buffer. + * + */ +size_t mbedtls_ssl_get_bytes_avail(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the result of the certificate verification + * + * \param ssl The SSL context to use. + * + * \return \c 0 if the certificate verification was successful. + * \return \c -1u if the result is not available. This may happen + * e.g. if the handshake aborts early, or a verification + * callback returned a fatal error. + * \return A bitwise combination of \c MBEDTLS_X509_BADCERT_XXX + * and \c MBEDTLS_X509_BADCRL_XXX failure flags; see x509.h. + */ +uint32_t mbedtls_ssl_get_verify_result(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the id of the current ciphersuite + * + * \param ssl SSL context + * + * \return a ciphersuite id + */ +int mbedtls_ssl_get_ciphersuite_id_from_ssl(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the name of the current ciphersuite + * + * \param ssl SSL context + * + * \return a string containing the ciphersuite name + */ +const char *mbedtls_ssl_get_ciphersuite(const mbedtls_ssl_context *ssl); + + +/** + * \brief Return the (D)TLS protocol version negotiated in the + * given connection. + * + * \note If you call this function too early during the initial + * handshake, before the two sides have agreed on a version, + * this function returns #MBEDTLS_SSL_VERSION_UNKNOWN. + * + * \param ssl The SSL context to query. + * \return The negotiated protocol version. + */ +static inline mbedtls_ssl_protocol_version mbedtls_ssl_get_version_number( + const mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(tls_version); +} + +/** + * \brief Return the current TLS version + * + * \param ssl SSL context + * + * \return a string containing the TLS version + */ +const char *mbedtls_ssl_get_version(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the (maximum) number of bytes added by the record + * layer: header + encryption/MAC overhead (inc. padding) + * + * \param ssl SSL context + * + * \return Current maximum record expansion in bytes + */ +int mbedtls_ssl_get_record_expansion(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the current maximum outgoing record payload in bytes. + * + * \note The logic to determine the maximum outgoing record payload is + * version-specific. It takes into account various factors, such as + * the mbedtls_config.h setting \c MBEDTLS_SSL_OUT_CONTENT_LEN, extensions + * such as the max fragment length or record size limit extension if + * used, and for DTLS the path MTU as configured and current + * record expansion. + * + * \note With DTLS, \c mbedtls_ssl_write() will return an error if + * called with a larger length value. + * With TLS, \c mbedtls_ssl_write() will fragment the input if + * necessary and return the number of bytes written; it is up + * to the caller to call \c mbedtls_ssl_write() again in + * order to send the remaining bytes if any. + * + * \sa mbedtls_ssl_get_max_out_record_payload() + * \sa mbedtls_ssl_get_record_expansion() + * + * \param ssl SSL context + * + * \return Current maximum payload for an outgoing record, + * or a negative error code. + */ +int mbedtls_ssl_get_max_out_record_payload(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the current maximum incoming record payload in bytes. + * + * \note The logic to determine the maximum incoming record payload is + * version-specific. It takes into account various factors, such as + * the mbedtls_config.h setting \c MBEDTLS_SSL_IN_CONTENT_LEN, extensions + * such as the max fragment length extension or record size limit + * extension if used, and the current record expansion. + * + * \sa mbedtls_ssl_set_mtu() + * \sa mbedtls_ssl_get_max_in_record_payload() + * \sa mbedtls_ssl_get_record_expansion() + * + * \param ssl SSL context + * + * \return Current maximum payload for an incoming record, + * or a negative error code. + */ +int mbedtls_ssl_get_max_in_record_payload(const mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * \brief Return the peer certificate from the current connection. + * + * \param ssl The SSL context to use. This must be initialized and setup. + * + * \return The current peer certificate, if available. + * The returned certificate is owned by the SSL context and + * is valid only until the next call to the SSL API. + * \return \c NULL if no peer certificate is available. This might + * be because the chosen ciphersuite doesn't use CRTs + * (PSK-based ciphersuites, for example), or because + * #MBEDTLS_SSL_KEEP_PEER_CERTIFICATE has been disabled, + * allowing the stack to free the peer's CRT to save memory. + * + * \note For one-time inspection of the peer's certificate during + * the handshake, consider registering an X.509 CRT verification + * callback through mbedtls_ssl_conf_verify() instead of calling + * this function. Using mbedtls_ssl_conf_verify() also comes at + * the benefit of allowing you to influence the verification + * process, for example by masking expected and tolerated + * verification failures. + * + * \warning You must not use the pointer returned by this function + * after any further call to the SSL API, including + * mbedtls_ssl_read() and mbedtls_ssl_write(); this is + * because the pointer might change during renegotiation, + * which happens transparently to the user. + * If you want to use the certificate across API calls, + * you must make a copy. + */ +const mbedtls_x509_crt *mbedtls_ssl_get_peer_cert(const mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_CLI_C) +/** + * \brief Export a session in order to resume it later. + * + * \param ssl The SSL context representing the connection for which to + * to export a session structure for later resumption. + * \param session The target structure in which to store the exported session. + * This must have been initialized with mbedtls_ssl_init_session() + * but otherwise be unused. + * + * \note This function can handle a variety of mechanisms for session + * resumption: For TLS 1.2, both session ID-based resumption and + * ticket-based resumption will be considered. For TLS 1.3, + * once implemented, sessions equate to tickets, and calling + * this function multiple times will export the available + * tickets one a time until no further tickets are available, + * in which case MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE will + * be returned. + * + * \note Calling this function multiple times will only be useful + * once TLS 1.3 is supported. For TLS 1.2 connections, this + * function should be called at most once. + * + * \return \c 0 if successful. In this case, \p session can be used for + * session resumption by passing it to mbedtls_ssl_set_session(), + * and serialized for storage via mbedtls_ssl_session_save(). + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE if no further session + * is available for export. + * This error is a non-fatal, and has no observable effect on + * the SSL context or the destination session. + * \return Another negative error code on other kinds of failure. + * + * \sa mbedtls_ssl_set_session() + * \sa mbedtls_ssl_session_save() + */ +int mbedtls_ssl_get_session(const mbedtls_ssl_context *ssl, + mbedtls_ssl_session *session); +#endif /* MBEDTLS_SSL_CLI_C */ + +/** + * \brief Perform the SSL handshake + * + * \param ssl SSL context + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE + * if the handshake is incomplete and waiting for data to + * be available for reading from or writing to the underlying + * transport - in this case you must call this function again + * when the underlying transport is ready for the operation. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous + * operation is in progress (see + * mbedtls_ssl_conf_async_private_cb()) - in this case you + * must call this function again when the operation is ready. + * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic + * operation is in progress (see mbedtls_ecp_set_max_ops()) - + * in this case you must call this function again to complete + * the handshake when you're done attending other tasks. + * \return #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED if DTLS is in use + * and the client did not demonstrate reachability yet - in + * this case you must stop using the context (see below). + * \return Another SSL error code - in this case you must stop using + * the context (see below). + * + * \warning If this function returns something other than + * \c 0, + * #MBEDTLS_ERR_SSL_WANT_READ, + * #MBEDTLS_ERR_SSL_WANT_WRITE, + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, + * you must stop using the SSL context for reading or writing, + * and either free it or call \c mbedtls_ssl_session_reset() + * on it before re-using it for a new connection; the current + * connection must be closed. + * + * \note If DTLS is in use, then you may choose to handle + * #MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED specially for logging + * purposes, as it is an expected return value rather than an + * actual error, but you still need to reset/free the context. + * + * \note Remarks regarding event-driven DTLS: + * If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram + * from the underlying transport layer is currently being processed, + * and it is safe to idle until the timer or the underlying transport + * signal a new event. This is not true for a successful handshake, + * in which case the datagram of the underlying transport that is + * currently being processed might or might not contain further + * DTLS records. + * + * \note If the context is configured to allow TLS 1.3, or if + * #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + */ +int mbedtls_ssl_handshake(mbedtls_ssl_context *ssl); + +/** + * \brief After calling mbedtls_ssl_handshake() to start the SSL + * handshake you can call this function to check whether the + * handshake is over for a given SSL context. This function + * should be also used to determine when to stop calling + * mbedtls_handshake_step() for that context. + * + * \param ssl SSL context + * + * \return \c 1 if handshake is over, \c 0 if it is still ongoing. + */ +static inline int mbedtls_ssl_is_handshake_over(mbedtls_ssl_context *ssl) +{ + return ssl->MBEDTLS_PRIVATE(state) >= MBEDTLS_SSL_HANDSHAKE_OVER; +} + +/** + * \brief Perform a single step of the SSL handshake + * + * \note The state of the context (ssl->state) will be at + * the next state after this function returns \c 0. Do not + * call this function if mbedtls_ssl_is_handshake_over() + * returns \c 1. + * + * \warning Whilst in the past you may have used direct access to the + * context state (ssl->state) in order to ascertain when to + * stop calling this function and although you can still do + * so with something like ssl->MBEDTLS_PRIVATE(state) or by + * defining MBEDTLS_ALLOW_PRIVATE_ACCESS, this is now + * considered deprecated and could be broken in any future + * release. If you still find you have good reason for such + * direct access, then please do contact the team to explain + * this (raise an issue or post to the mailing list), so that + * we can add a solution to your problem that will be + * guaranteed to work in the future. + * + * \param ssl SSL context + * + * \return See mbedtls_ssl_handshake(). + * + * \warning If this function returns something other than \c 0, + * #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE, + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using + * the SSL context for reading or writing, and either free it + * or call \c mbedtls_ssl_session_reset() on it before + * re-using it for a new connection; the current connection + * must be closed. + */ +int mbedtls_ssl_handshake_step(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +/** + * \brief Initiate an SSL renegotiation on the running connection. + * Client: perform the renegotiation right now. + * Server: request renegotiation, which will be performed + * during the next call to mbedtls_ssl_read() if honored by + * client. + * + * \param ssl SSL context + * + * \return 0 if successful, or any mbedtls_ssl_handshake() return + * value except #MBEDTLS_ERR_SSL_CLIENT_RECONNECT that can't + * happen during a renegotiation. + * + * \warning If this function returns something other than \c 0, + * #MBEDTLS_ERR_SSL_WANT_READ, #MBEDTLS_ERR_SSL_WANT_WRITE, + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, you must stop using + * the SSL context for reading or writing, and either free it + * or call \c mbedtls_ssl_session_reset() on it before + * re-using it for a new connection; the current connection + * must be closed. + * + */ +int mbedtls_ssl_renegotiate(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +/** + * \brief Read at most 'len' application data bytes + * + * \param ssl SSL context + * \param buf buffer that will hold the data + * \param len maximum number of bytes to read + * + * \return The (positive) number of bytes read if successful. + * \return \c 0 if the read end of the underlying transport was closed + * without sending a CloseNotify beforehand, which might happen + * because of various reasons (internal error of an underlying + * stack, non-conformant peer not sending a CloseNotify and + * such) - in this case you must stop using the context + * (see below). + * \return #MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY if the underlying + * transport is still functional, but the peer has + * acknowledged to not send anything anymore. + * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE + * if the handshake is incomplete and waiting for data to + * be available for reading from or writing to the underlying + * transport - in this case you must call this function again + * when the underlying transport is ready for the operation. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous + * operation is in progress (see + * mbedtls_ssl_conf_async_private_cb()) - in this case you + * must call this function again when the operation is ready. + * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic + * operation is in progress (see mbedtls_ecp_set_max_ops()) - + * in this case you must call this function again to complete + * the handshake when you're done attending other tasks. + * \return #MBEDTLS_ERR_SSL_CLIENT_RECONNECT if we're at the server + * side of a DTLS connection and the client is initiating a + * new connection using the same source port. See below. + * \return Another SSL error code - in this case you must stop using + * the context (see below). + * + * \warning If this function returns something other than + * a positive value, + * #MBEDTLS_ERR_SSL_WANT_READ, + * #MBEDTLS_ERR_SSL_WANT_WRITE, + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS, + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_CLIENT_RECONNECT, + * you must stop using the SSL context for reading or writing, + * and either free it or call \c mbedtls_ssl_session_reset() + * on it before re-using it for a new connection; the current + * connection must be closed. + * + * \note When this function returns #MBEDTLS_ERR_SSL_CLIENT_RECONNECT + * (which can only happen server-side), it means that a client + * is initiating a new connection using the same source port. + * You can either treat that as a connection close and wait + * for the client to resend a ClientHello, or directly + * continue with \c mbedtls_ssl_handshake() with the same + * context (as it has been reset internally). Either way, you + * must make sure this is seen by the application as a new + * connection: application state, if any, should be reset, and + * most importantly the identity of the client must be checked + * again. WARNING: not validating the identity of the client + * again, or not transmitting the new identity to the + * application layer, would allow authentication bypass! + * + * \note Remarks regarding event-driven DTLS: + * - If the function returns #MBEDTLS_ERR_SSL_WANT_READ, no datagram + * from the underlying transport layer is currently being processed, + * and it is safe to idle until the timer or the underlying transport + * signal a new event. + * - This function may return MBEDTLS_ERR_SSL_WANT_READ even if data was + * initially available on the underlying transport, as this data may have + * been only e.g. duplicated messages or a renegotiation request. + * Therefore, you must be prepared to receive MBEDTLS_ERR_SSL_WANT_READ even + * when reacting to an incoming-data event from the underlying transport. + * - On success, the datagram of the underlying transport that is currently + * being processed may contain further DTLS records. You should call + * \c mbedtls_ssl_check_pending to check for remaining records. + * + */ +int mbedtls_ssl_read(mbedtls_ssl_context *ssl, unsigned char *buf, size_t len); + +/** + * \brief Try to write exactly 'len' application data bytes + * + * \warning This function will do partial writes in some cases. If the + * return value is non-negative but less than length, the + * function must be called again with updated arguments: + * buf + ret, len - ret (if ret is the return value) until + * it returns a value equal to the last 'len' argument. + * + * \param ssl SSL context + * \param buf buffer holding the data + * \param len how many bytes must be written + * + * \return The (non-negative) number of bytes actually written if + * successful (may be less than \p len). + * \return #MBEDTLS_ERR_SSL_WANT_READ or #MBEDTLS_ERR_SSL_WANT_WRITE + * if the handshake is incomplete and waiting for data to + * be available for reading from or writing to the underlying + * transport - in this case you must call this function again + * when the underlying transport is ready for the operation. + * \return #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS if an asynchronous + * operation is in progress (see + * mbedtls_ssl_conf_async_private_cb()) - in this case you + * must call this function again when the operation is ready. + * \return #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS if a cryptographic + * operation is in progress (see mbedtls_ecp_set_max_ops()) - + * in this case you must call this function again to complete + * the handshake when you're done attending other tasks. + * \return Another SSL error code - in this case you must stop using + * the context (see below). + * + * \warning If this function returns something other than + * a non-negative value, + * #MBEDTLS_ERR_SSL_WANT_READ, + * #MBEDTLS_ERR_SSL_WANT_WRITE, + * #MBEDTLS_ERR_SSL_ASYNC_IN_PROGRESS or + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS, + * you must stop using the SSL context for reading or writing, + * and either free it or call \c mbedtls_ssl_session_reset() + * on it before re-using it for a new connection; the current + * connection must be closed. + * + * \note When this function returns #MBEDTLS_ERR_SSL_WANT_WRITE/READ, + * it must be called later with the *same* arguments, + * until it returns a value greater than or equal to 0. When + * the function returns #MBEDTLS_ERR_SSL_WANT_WRITE there may be + * some partial data in the output buffer, however this is not + * yet sent. + * + * \note If the requested length is greater than the maximum + * fragment length (either the built-in limit or the one set + * or negotiated with the peer), then: + * - with TLS, less bytes than requested are written. + * - with DTLS, MBEDTLS_ERR_SSL_BAD_INPUT_DATA is returned. + * \c mbedtls_ssl_get_max_out_record_payload() may be used to + * query the active maximum fragment length. + * + * \note Attempting to write 0 bytes will result in an empty TLS + * application record being sent. + */ +int mbedtls_ssl_write(mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len); + +/** + * \brief Send an alert message + * + * \param ssl SSL context + * \param level The alert level of the message + * (MBEDTLS_SSL_ALERT_LEVEL_WARNING or MBEDTLS_SSL_ALERT_LEVEL_FATAL) + * \param message The alert message (SSL_ALERT_MSG_*) + * + * \return 0 if successful, or a specific SSL error code. + * + * \note If this function returns something other than 0 or + * MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using + * the SSL context for reading or writing, and either free it or + * call \c mbedtls_ssl_session_reset() on it before re-using it + * for a new connection; the current connection must be closed. + */ +int mbedtls_ssl_send_alert_message(mbedtls_ssl_context *ssl, + unsigned char level, + unsigned char message); +/** + * \brief Notify the peer that the connection is being closed + * + * \param ssl SSL context + * + * \return 0 if successful, or a specific SSL error code. + * + * \note If this function returns something other than 0 or + * MBEDTLS_ERR_SSL_WANT_READ/WRITE, you must stop using + * the SSL context for reading or writing, and either free it or + * call \c mbedtls_ssl_session_reset() on it before re-using it + * for a new connection; the current connection must be closed. + */ +int mbedtls_ssl_close_notify(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_EARLY_DATA) + +#if defined(MBEDTLS_SSL_SRV_C) +/** + * \brief Read at most 'len' application data bytes while performing + * the handshake (early data). + * + * \note This function behaves mainly as mbedtls_ssl_read(). The + * specification of mbedtls_ssl_read() relevant to TLS 1.3 + * (thus not the parts specific to (D)TLS 1.2) applies to this + * function and the present documentation is restricted to the + * differences with mbedtls_ssl_read(). + * + * \param ssl SSL context + * \param buf buffer that will hold the data + * \param len maximum number of bytes to read + * + * \return One additional specific return value: + * #MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA. + * + * #MBEDTLS_ERR_SSL_CANNOT_READ_EARLY_DATA is returned when it + * is not possible to read early data for the SSL context + * \p ssl. + * + * It may have been possible and it is not possible + * anymore because the server received the End of Early Data + * message or the maximum number of allowed early data for the + * PSK in use has been reached. + * + * It may never have been possible and will never be possible + * for the SSL context \p ssl because the use of early data + * is disabled for that context or more generally the context + * is not suitably configured to enable early data or the + * client does not use early data or the first call to the + * function was done while the handshake was already too + * advanced to gather and accept early data. + * + * It is not possible to read early data for the SSL context + * \p ssl but this does not preclude for using it with + * mbedtls_ssl_write(), mbedtls_ssl_read() or + * mbedtls_ssl_handshake(). + * + * \note When a server wants to retrieve early data, it is expected + * that this function starts the handshake for the SSL context + * \p ssl. But this is not mandatory. + * + */ +int mbedtls_ssl_read_early_data(mbedtls_ssl_context *ssl, + unsigned char *buf, size_t len); +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_CLI_C) +/** + * \brief Try to write exactly 'len' application data bytes while + * performing the handshake (early data). + * + * \note This function behaves mainly as mbedtls_ssl_write(). The + * specification of mbedtls_ssl_write() relevant to TLS 1.3 + * (thus not the parts specific to (D)TLS1.2) applies to this + * function and the present documentation is restricted to the + * differences with mbedtls_ssl_write(). + * + * \param ssl SSL context + * \param buf buffer holding the data + * \param len how many bytes must be written + * + * \return One additional specific return value: + * #MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA. + * + * #MBEDTLS_ERR_SSL_CANNOT_WRITE_EARLY_DATA is returned when it + * is not possible to write early data for the SSL context + * \p ssl. + * + * It may have been possible and it is not possible + * anymore because the client received the server Finished + * message, the server rejected early data or the maximum + * number of allowed early data for the PSK in use has been + * reached. + * + * It may never have been possible and will never be possible + * for the SSL context \p ssl because the use of early data + * is disabled for that context or more generally the context + * is not suitably configured to enable early data or the first + * call to the function was done while the handshake was + * already completed. + * + * It is not possible to write early data for the SSL context + * \p ssl but this does not preclude for using it with + * mbedtls_ssl_write(), mbedtls_ssl_read() or + * mbedtls_ssl_handshake(). + * + * \note This function may write early data only if the SSL context + * has been configured for the handshake with a PSK for which + * early data is allowed. + * + * \note To maximize the number of early data that can be written in + * the course of the handshake, it is expected that this + * function starts the handshake for the SSL context \p ssl. + * But this is not mandatory. + * + * \note This function does not provide any information on whether + * the server has accepted or will accept early data or not. + * When it returns a positive value, it just means that it + * has written early data to the server. To know whether the + * server has accepted early data or not, you should call + * mbedtls_ssl_get_early_data_status() with the handshake + * completed. + */ +int mbedtls_ssl_write_early_data(mbedtls_ssl_context *ssl, + const unsigned char *buf, size_t len); + +#define MBEDTLS_SSL_EARLY_DATA_STATUS_NOT_SENT 0 +#define MBEDTLS_SSL_EARLY_DATA_STATUS_ACCEPTED 1 +#define MBEDTLS_SSL_EARLY_DATA_STATUS_REJECTED 2 +/** + * \brief Get the status of the negotiation of the use of early data. + * + * \param ssl The SSL context to query + * + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if this function is called + * from the server-side. + * + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if this function is called + * prior to completion of the handshake. + * + * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_NOT_SENT if the client has + * not indicated the use of early data to the server. + * + * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_ACCEPTED if the client has + * indicated the use of early data and the server has accepted + * it. + * + * \return #MBEDTLS_SSL_EARLY_DATA_STATUS_REJECTED if the client has + * indicated the use of early data but the server has rejected + * it. In this situation, the client may want to re-send the + * early data it may have tried to send by calling + * mbedtls_ssl_write_early_data() as ordinary post-handshake + * application data by calling mbedtls_ssl_write(). + * + */ +int mbedtls_ssl_get_early_data_status(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_CLI_C */ + +#endif /* MBEDTLS_SSL_EARLY_DATA */ + +/** + * \brief Free referenced items in an SSL context and clear memory + * + * \param ssl SSL context + */ +void mbedtls_ssl_free(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) +/** + * \brief Save an active connection as serialized data in a buffer. + * This allows the freeing or re-using of the SSL context + * while still picking up the connection later in a way that + * it entirely transparent to the peer. + * + * \see mbedtls_ssl_context_load() + * + * \note The serialized data only contains the data that is + * necessary to resume the connection: negotiated protocol + * options, session identifier, keys, etc. + * Loading a saved SSL context does not restore settings and + * state related to how the application accesses the context, + * such as configured callback functions, user data, pending + * incoming or outgoing data, etc. + * + * \note This feature is currently only available under certain + * conditions, see the documentation of the return value + * #MBEDTLS_ERR_SSL_BAD_INPUT_DATA for details. + * + * \note When this function succeeds, it calls + * mbedtls_ssl_session_reset() on \p ssl which as a result is + * no longer associated with the connection that has been + * serialized. This avoids creating copies of the connection + * state. You're then free to either re-use the context + * structure for a different connection, or call + * mbedtls_ssl_free() on it. See the documentation of + * mbedtls_ssl_session_reset() for more details. + * + * \param ssl The SSL context to save. On success, it is no longer + * associated with the connection that has been serialized. + * \param buf The buffer to write the serialized data to. It must be a + * writeable buffer of at least \p buf_len bytes, or may be \c + * NULL if \p buf_len is \c 0. + * \param buf_len The number of bytes available for writing in \p buf. + * \param olen The size in bytes of the data that has been or would have + * been written. It must point to a valid \c size_t. + * + * \note \p olen is updated to the correct value regardless of + * whether \p buf_len was large enough. This makes it possible + * to determine the necessary size by calling this function + * with \p buf set to \c NULL and \p buf_len to \c 0. However, + * the value of \p olen is only guaranteed to be correct when + * the function returns #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL or + * \c 0. If the return value is different, then the value of + * \p olen is undefined. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL if \p buf is too small. + * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed + * while resetting the context. + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if a handshake is in + * progress, or there is pending data for reading or sending, + * or the connection does not use DTLS 1.2 with an AEAD + * ciphersuite, or renegotiation is enabled. + */ +int mbedtls_ssl_context_save(mbedtls_ssl_context *ssl, + unsigned char *buf, + size_t buf_len, + size_t *olen); + +/** + * \brief Load serialized connection data to an SSL context. + * + * \see mbedtls_ssl_context_save() + * + * \warning The same serialized data must never be loaded into more + * that one context. In order to ensure that, after + * successfully loading serialized data to an SSL context, you + * should immediately destroy or invalidate all copies of the + * serialized data that was loaded. Loading the same data in + * more than one context would cause severe security failures + * including but not limited to loss of confidentiality. + * + * \note Before calling this function, the SSL context must be + * prepared in one of the two following ways. The first way is + * to take a context freshly initialised with + * mbedtls_ssl_init() and call mbedtls_ssl_setup() on it with + * the same ::mbedtls_ssl_config structure that was used in + * the original connection. The second way is to + * call mbedtls_ssl_session_reset() on a context that was + * previously prepared as above but used in the meantime. + * Either way, you must not use the context to perform a + * handshake between calling mbedtls_ssl_setup() or + * mbedtls_ssl_session_reset() and calling this function. You + * may however call other setter functions in that time frame + * as indicated in the note below. + * + * \note Before or after calling this function successfully, you + * also need to configure some connection-specific callbacks + * and settings before you can use the connection again + * (unless they were already set before calling + * mbedtls_ssl_session_reset() and the values are suitable for + * the present connection). Specifically, you want to call + * at least mbedtls_ssl_set_bio(), + * mbedtls_ssl_set_timer_cb(), and + * mbedtls_ssl_set_user_data_n() or + * mbedtls_ssl_set_user_data_p() if they were set originally. + * All other SSL setter functions + * are not necessary to call, either because they're only used + * in handshakes, or because the setting is already saved. You + * might choose to call them anyway, for example in order to + * share code between the cases of establishing a new + * connection and the case of loading an already-established + * connection. + * + * \note If you have new information about the path MTU, you want to + * call mbedtls_ssl_set_mtu() after calling this function, as + * otherwise this function would overwrite your + * newly-configured value with the value that was active when + * the context was saved. + * + * \note When this function returns an error code, it calls + * mbedtls_ssl_free() on \p ssl. In this case, you need to + * prepare the context with the usual sequence starting with a + * call to mbedtls_ssl_init() if you want to use it again. + * + * \param ssl The SSL context structure to be populated. It must have + * been prepared as described in the note above. + * \param buf The buffer holding the serialized connection data. It must + * be a readable buffer of at least \p len bytes. + * \param len The size of the serialized data in bytes. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_SSL_ALLOC_FAILED if memory allocation failed. + * \return #MBEDTLS_ERR_SSL_VERSION_MISMATCH if the serialized data + * comes from a different Mbed TLS version or build. + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA if input data is invalid. + */ +int mbedtls_ssl_context_load(mbedtls_ssl_context *ssl, + const unsigned char *buf, + size_t len); +#endif /* MBEDTLS_SSL_CONTEXT_SERIALIZATION */ + +/** + * \brief Initialize an SSL configuration context + * Just makes the context ready for + * mbedtls_ssl_config_defaults() or mbedtls_ssl_config_free(). + * + * \note You need to call mbedtls_ssl_config_defaults() unless you + * manually set all of the relevant fields yourself. + * + * \param conf SSL configuration context + */ +void mbedtls_ssl_config_init(mbedtls_ssl_config *conf); + +/** + * \brief Load reasonable default SSL configuration values. + * (You need to call mbedtls_ssl_config_init() first.) + * + * \param conf SSL configuration context + * \param endpoint MBEDTLS_SSL_IS_CLIENT or MBEDTLS_SSL_IS_SERVER + * \param transport MBEDTLS_SSL_TRANSPORT_STREAM for TLS, or + * MBEDTLS_SSL_TRANSPORT_DATAGRAM for DTLS + * \param preset a MBEDTLS_SSL_PRESET_XXX value + * + * \note See \c mbedtls_ssl_conf_transport() for notes on DTLS. + * + * \return 0 if successful, or + * MBEDTLS_ERR_XXX_ALLOC_FAILED on memory allocation error. + */ +int mbedtls_ssl_config_defaults(mbedtls_ssl_config *conf, + int endpoint, int transport, int preset); + +/** + * \brief Free an SSL configuration context + * + * \param conf SSL configuration context + */ +void mbedtls_ssl_config_free(mbedtls_ssl_config *conf); + +/** + * \brief Initialize SSL session structure + * + * \param session SSL session + */ +void mbedtls_ssl_session_init(mbedtls_ssl_session *session); + +/** + * \brief Free referenced items in an SSL session including the + * peer certificate and clear memory + * + * \note A session object can be freed even if the SSL context + * that was used to retrieve the session is still in use. + * + * \param session SSL session + */ +void mbedtls_ssl_session_free(mbedtls_ssl_session *session); + +/** + * \brief TLS-PRF function for key derivation. + * + * \param prf The tls_prf type function type to be used. + * \param secret Secret for the key derivation function. + * \param slen Length of the secret. + * \param label String label for the key derivation function, + * terminated with null character. + * \param random Random bytes. + * \param rlen Length of the random bytes buffer. + * \param dstbuf The buffer holding the derived key. + * \param dlen Length of the output buffer. + * + * \return 0 on success. An SSL specific error on failure. + */ +int mbedtls_ssl_tls_prf(const mbedtls_tls_prf_types prf, + const unsigned char *secret, size_t slen, + const char *label, + const unsigned char *random, size_t rlen, + unsigned char *dstbuf, size_t dlen); + +#ifdef __cplusplus +} +#endif + +#endif /* ssl.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cache.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cache.h index 7a90191..c21ca06 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cache.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cache.h @@ -1,199 +1,199 @@ -/** - * \file ssl_cache.h - * - * \brief SSL session cache implementation - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_CACHE_H -#define MBEDTLS_SSL_CACHE_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/ssl.h" - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ - -#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT) -#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /*!< 1 day */ -#endif - -#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES) -#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */ -#endif - -/** \} name SECTION: Module settings */ - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct mbedtls_ssl_cache_context mbedtls_ssl_cache_context; -typedef struct mbedtls_ssl_cache_entry mbedtls_ssl_cache_entry; - -/** - * \brief This structure is used for storing cache entries - */ -struct mbedtls_ssl_cache_entry { -#if defined(MBEDTLS_HAVE_TIME) - mbedtls_time_t MBEDTLS_PRIVATE(timestamp); /*!< entry timestamp */ -#endif - - unsigned char MBEDTLS_PRIVATE(session_id)[32]; /*!< session ID */ - size_t MBEDTLS_PRIVATE(session_id_len); - - unsigned char *MBEDTLS_PRIVATE(session); /*!< serialized session */ - size_t MBEDTLS_PRIVATE(session_len); - - mbedtls_ssl_cache_entry *MBEDTLS_PRIVATE(next); /*!< chain pointer */ -}; - -/** - * \brief Cache context - */ -struct mbedtls_ssl_cache_context { - mbedtls_ssl_cache_entry *MBEDTLS_PRIVATE(chain); /*!< start of the chain */ - int MBEDTLS_PRIVATE(timeout); /*!< cache entry timeout */ - int MBEDTLS_PRIVATE(max_entries); /*!< maximum entries */ -#if defined(MBEDTLS_THREADING_C) - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< mutex */ -#endif -}; - -/** - * \brief Initialize an SSL cache context - * - * \param cache SSL cache context - */ -void mbedtls_ssl_cache_init(mbedtls_ssl_cache_context *cache); - -/** - * \brief Cache get callback implementation - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param data The SSL cache context to use. - * \param session_id The pointer to the buffer holding the session ID - * for the session to load. - * \param session_id_len The length of \p session_id in bytes. - * \param session The address at which to store the session - * associated with \p session_id, if present. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_SSL_CACHE_ENTRY_NOT_FOUND if there is - * no cache entry with specified session ID found, or - * any other negative error code for other failures. - */ -int mbedtls_ssl_cache_get(void *data, - unsigned char const *session_id, - size_t session_id_len, - mbedtls_ssl_session *session); - -/** - * \brief Cache set callback implementation - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param data The SSL cache context to use. - * \param session_id The pointer to the buffer holding the session ID - * associated to \p session. - * \param session_id_len The length of \p session_id in bytes. - * \param session The session to store. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -int mbedtls_ssl_cache_set(void *data, - unsigned char const *session_id, - size_t session_id_len, - const mbedtls_ssl_session *session); - -/** - * \brief Remove the cache entry by the session ID - * (Thread-safe if MBEDTLS_THREADING_C is enabled) - * - * \param data The SSL cache context to use. - * \param session_id The pointer to the buffer holding the session ID - * associated to session. - * \param session_id_len The length of \p session_id in bytes. - * - * \return \c 0 on success. This indicates the cache entry for - * the session with provided ID is removed or does not - * exist. - * \return A negative error code on failure. - */ -int mbedtls_ssl_cache_remove(void *data, - unsigned char const *session_id, - size_t session_id_len); - -#if defined(MBEDTLS_HAVE_TIME) -/** - * \brief Set the cache timeout - * (Default: MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT (1 day)) - * - * A timeout of 0 indicates no timeout. - * - * \param cache SSL cache context - * \param timeout cache entry timeout in seconds - */ -void mbedtls_ssl_cache_set_timeout(mbedtls_ssl_cache_context *cache, int timeout); - -/** - * \brief Get the cache timeout - * - * A timeout of 0 indicates no timeout. - * - * \param cache SSL cache context - * - * \return cache entry timeout in seconds - */ -static inline int mbedtls_ssl_cache_get_timeout(mbedtls_ssl_cache_context *cache) -{ - return cache->MBEDTLS_PRIVATE(timeout); -} -#endif /* MBEDTLS_HAVE_TIME */ - -/** - * \brief Set the maximum number of cache entries - * (Default: MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES (50)) - * - * \param cache SSL cache context - * \param max cache entry maximum - */ -void mbedtls_ssl_cache_set_max_entries(mbedtls_ssl_cache_context *cache, int max); - -/** - * \brief Free referenced items in a cache context and clear memory - * - * \param cache SSL cache context - */ -void mbedtls_ssl_cache_free(mbedtls_ssl_cache_context *cache); - -#ifdef __cplusplus -} -#endif - -#endif /* ssl_cache.h */ +/** + * \file ssl_cache.h + * + * \brief SSL session cache implementation + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_CACHE_H +#define MBEDTLS_SSL_CACHE_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/ssl.h" + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT) +#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /*!< 1 day */ +#endif + +#if !defined(MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES) +#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /*!< Maximum entries in cache */ +#endif + +/** \} name SECTION: Module settings */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mbedtls_ssl_cache_context mbedtls_ssl_cache_context; +typedef struct mbedtls_ssl_cache_entry mbedtls_ssl_cache_entry; + +/** + * \brief This structure is used for storing cache entries + */ +struct mbedtls_ssl_cache_entry { +#if defined(MBEDTLS_HAVE_TIME) + mbedtls_time_t MBEDTLS_PRIVATE(timestamp); /*!< entry timestamp */ +#endif + + unsigned char MBEDTLS_PRIVATE(session_id)[32]; /*!< session ID */ + size_t MBEDTLS_PRIVATE(session_id_len); + + unsigned char *MBEDTLS_PRIVATE(session); /*!< serialized session */ + size_t MBEDTLS_PRIVATE(session_len); + + mbedtls_ssl_cache_entry *MBEDTLS_PRIVATE(next); /*!< chain pointer */ +}; + +/** + * \brief Cache context + */ +struct mbedtls_ssl_cache_context { + mbedtls_ssl_cache_entry *MBEDTLS_PRIVATE(chain); /*!< start of the chain */ + int MBEDTLS_PRIVATE(timeout); /*!< cache entry timeout */ + int MBEDTLS_PRIVATE(max_entries); /*!< maximum entries */ +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); /*!< mutex */ +#endif +}; + +/** + * \brief Initialize an SSL cache context + * + * \param cache SSL cache context + */ +void mbedtls_ssl_cache_init(mbedtls_ssl_cache_context *cache); + +/** + * \brief Cache get callback implementation + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param data The SSL cache context to use. + * \param session_id The pointer to the buffer holding the session ID + * for the session to load. + * \param session_id_len The length of \p session_id in bytes. + * \param session The address at which to store the session + * associated with \p session_id, if present. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_SSL_CACHE_ENTRY_NOT_FOUND if there is + * no cache entry with specified session ID found, or + * any other negative error code for other failures. + */ +int mbedtls_ssl_cache_get(void *data, + unsigned char const *session_id, + size_t session_id_len, + mbedtls_ssl_session *session); + +/** + * \brief Cache set callback implementation + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param data The SSL cache context to use. + * \param session_id The pointer to the buffer holding the session ID + * associated to \p session. + * \param session_id_len The length of \p session_id in bytes. + * \param session The session to store. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +int mbedtls_ssl_cache_set(void *data, + unsigned char const *session_id, + size_t session_id_len, + const mbedtls_ssl_session *session); + +/** + * \brief Remove the cache entry by the session ID + * (Thread-safe if MBEDTLS_THREADING_C is enabled) + * + * \param data The SSL cache context to use. + * \param session_id The pointer to the buffer holding the session ID + * associated to session. + * \param session_id_len The length of \p session_id in bytes. + * + * \return \c 0 on success. This indicates the cache entry for + * the session with provided ID is removed or does not + * exist. + * \return A negative error code on failure. + */ +int mbedtls_ssl_cache_remove(void *data, + unsigned char const *session_id, + size_t session_id_len); + +#if defined(MBEDTLS_HAVE_TIME) +/** + * \brief Set the cache timeout + * (Default: MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT (1 day)) + * + * A timeout of 0 indicates no timeout. + * + * \param cache SSL cache context + * \param timeout cache entry timeout in seconds + */ +void mbedtls_ssl_cache_set_timeout(mbedtls_ssl_cache_context *cache, int timeout); + +/** + * \brief Get the cache timeout + * + * A timeout of 0 indicates no timeout. + * + * \param cache SSL cache context + * + * \return cache entry timeout in seconds + */ +static inline int mbedtls_ssl_cache_get_timeout(mbedtls_ssl_cache_context *cache) +{ + return cache->MBEDTLS_PRIVATE(timeout); +} +#endif /* MBEDTLS_HAVE_TIME */ + +/** + * \brief Set the maximum number of cache entries + * (Default: MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES (50)) + * + * \param cache SSL cache context + * \param max cache entry maximum + */ +void mbedtls_ssl_cache_set_max_entries(mbedtls_ssl_cache_context *cache, int max); + +/** + * \brief Free referenced items in a cache context and clear memory + * + * \param cache SSL cache context + */ +void mbedtls_ssl_cache_free(mbedtls_ssl_cache_context *cache); + +#ifdef __cplusplus +} +#endif + +#endif /* ssl_cache.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ciphersuites.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ciphersuites.h index 07f2fac..c6d8436 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ciphersuites.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ciphersuites.h @@ -1,628 +1,628 @@ -/** - * \file ssl_ciphersuites.h - * - * \brief SSL Ciphersuites for Mbed TLS - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_CIPHERSUITES_H -#define MBEDTLS_SSL_CIPHERSUITES_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/pk.h" -#include "mbedtls/cipher.h" -#include "mbedtls/md.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Supported ciphersuites (Official IANA names) - */ -#define MBEDTLS_TLS_RSA_WITH_NULL_MD5 0x01 /**< Weak! */ -#define MBEDTLS_TLS_RSA_WITH_NULL_SHA 0x02 /**< Weak! */ - -#define MBEDTLS_TLS_PSK_WITH_NULL_SHA 0x2C /**< Weak! */ -#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA 0x2D /**< Weak! */ -#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA 0x2E /**< Weak! */ -#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA 0x2F - -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA 0x33 -#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA 0x35 -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA 0x39 - -#define MBEDTLS_TLS_RSA_WITH_NULL_SHA256 0x3B /**< Weak! */ -#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 0x3C /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 0x3D /**< TLS 1.2 */ - -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA 0x41 -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA 0x45 - -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 0x67 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 0x6B /**< TLS 1.2 */ - -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA 0x84 -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA 0x88 - -#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA 0x8C -#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA 0x8D - -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA 0x90 -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA 0x91 - -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA 0x94 -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA 0x95 - -#define MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 0x9C /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 0x9D /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 0x9E /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 0x9F /**< TLS 1.2 */ - -#define MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 0xA8 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 0xA9 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 0xAA /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 0xAB /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 0xAC /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 0xAD /**< TLS 1.2 */ - -#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 0xAE -#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 0xAF -#define MBEDTLS_TLS_PSK_WITH_NULL_SHA256 0xB0 /**< Weak! */ -#define MBEDTLS_TLS_PSK_WITH_NULL_SHA384 0xB1 /**< Weak! */ - -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 0xB2 -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 0xB3 -#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 0xB4 /**< Weak! */ -#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 0xB5 /**< Weak! */ - -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 0xB6 -#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 0xB7 -#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 0xB8 /**< Weak! */ -#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 0xB9 /**< Weak! */ - -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBA /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBE /**< TLS 1.2 */ - -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC0 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC4 /**< TLS 1.2 */ - -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA 0xC001 /**< Weak! */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA 0xC004 -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA 0xC005 - -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA 0xC006 /**< Weak! */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA 0xC009 -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA 0xC00A - -#define MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA 0xC00B /**< Weak! */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA 0xC00E -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA 0xC00F - -#define MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA 0xC010 /**< Weak! */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA 0xC013 -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA 0xC014 - -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 0xC023 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 0xC024 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 0xC025 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 0xC026 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 0xC027 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 0xC028 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 0xC029 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 0xC02A /**< TLS 1.2 */ - -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 0xC02B /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 0xC02C /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 0xC02D /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 0xC02E /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 0xC02F /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 0xC030 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 0xC031 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 0xC032 /**< TLS 1.2 */ - -#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA 0xC035 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA 0xC036 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 0xC037 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 0xC038 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA 0xC039 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 0xC03A -#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 0xC03B - -#define MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 0xC03C /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 0xC03D /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 0xC044 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 0xC045 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 0xC048 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 0xC049 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 0xC04A /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 0xC04B /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 0xC04C /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 0xC04D /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 0xC04E /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 0xC04F /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 0xC050 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 0xC051 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 0xC052 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 0xC053 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 0xC05C /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 0xC05D /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 0xC05E /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 0xC05F /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 0xC060 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 0xC061 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 0xC062 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 0xC063 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 0xC064 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 0xC065 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 0xC066 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 0xC067 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 0xC068 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 0xC069 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 0xC06A /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 0xC06B /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 0xC06C /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 0xC06D /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 0xC06E /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 0xC06F /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 0xC070 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 0xC071 /**< TLS 1.2 */ - -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC072 -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC073 -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC074 -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC075 -#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xC076 -#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 0xC077 -#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xC078 -#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 0xC079 - -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC07A /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC07B /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC07C /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC07D /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC086 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC087 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC088 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC089 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC08A /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC08B /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC08C /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC08D /**< TLS 1.2 */ - -#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC08E /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC08F /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC090 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC091 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC092 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC093 /**< TLS 1.2 */ - -#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC094 -#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC095 -#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC096 -#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC097 -#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC098 -#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC099 -#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC09A -#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC09B - -#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM 0xC09C /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM 0xC09D /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM 0xC09E /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM 0xC09F /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8 0xC0A0 /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8 0xC0A1 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8 0xC0A2 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8 0xC0A3 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM 0xC0A4 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM 0xC0A5 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM 0xC0A6 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM 0xC0A7 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8 0xC0A8 /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8 0xC0A9 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8 0xC0AA /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8 0xC0AB /**< TLS 1.2 */ -/* The last two are named with PSK_DHE in the RFC, which looks like a typo */ - -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM 0xC0AC /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM 0xC0AD /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 0xC0AE /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 0xC0AF /**< TLS 1.2 */ - -#define MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 0xC0FF /**< experimental */ - -/* RFC 7905 */ -#define MBEDTLS_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 0xCCA8 /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 0xCCA9 /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 0xCCAA /**< TLS 1.2 */ -#define MBEDTLS_TLS_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAB /**< TLS 1.2 */ -#define MBEDTLS_TLS_ECDHE_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAC /**< TLS 1.2 */ -#define MBEDTLS_TLS_DHE_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAD /**< TLS 1.2 */ -#define MBEDTLS_TLS_RSA_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAE /**< TLS 1.2 */ - -/* RFC 8446, Appendix B.4 */ -#define MBEDTLS_TLS1_3_AES_128_GCM_SHA256 0x1301 /**< TLS 1.3 */ -#define MBEDTLS_TLS1_3_AES_256_GCM_SHA384 0x1302 /**< TLS 1.3 */ -#define MBEDTLS_TLS1_3_CHACHA20_POLY1305_SHA256 0x1303 /**< TLS 1.3 */ -#define MBEDTLS_TLS1_3_AES_128_CCM_SHA256 0x1304 /**< TLS 1.3 */ -#define MBEDTLS_TLS1_3_AES_128_CCM_8_SHA256 0x1305 /**< TLS 1.3 */ - -/* Reminder: update mbedtls_ssl_premaster_secret when adding a new key exchange. - * Reminder: update MBEDTLS_KEY_EXCHANGE__xxx below - */ -typedef enum { - MBEDTLS_KEY_EXCHANGE_NONE = 0, - MBEDTLS_KEY_EXCHANGE_RSA, - MBEDTLS_KEY_EXCHANGE_DHE_RSA, - MBEDTLS_KEY_EXCHANGE_ECDHE_RSA, - MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA, - MBEDTLS_KEY_EXCHANGE_PSK, - MBEDTLS_KEY_EXCHANGE_DHE_PSK, - MBEDTLS_KEY_EXCHANGE_RSA_PSK, - MBEDTLS_KEY_EXCHANGE_ECDHE_PSK, - MBEDTLS_KEY_EXCHANGE_ECDH_RSA, - MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA, - MBEDTLS_KEY_EXCHANGE_ECJPAKE, -} mbedtls_key_exchange_type_t; - -/* Key exchanges using a certificate */ -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED -#endif - -/* Key exchanges in either TLS 1.2 or 1.3 which are using an ECDSA - * signature */ -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_WITH_ECDSA_ANY_ENABLED -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -#define MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED -#endif - -/* Key exchanges allowing client certificate requests. - * - * Note: that's almost the same as MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED - * above, except RSA-PSK uses a server certificate but no client cert. - * - * Note: this difference is specific to TLS 1.2, as with TLS 1.3, things are - * more symmetrical: client certs and server certs are either both allowed - * (Ephemeral mode) or both disallowed (PSK and PKS-Ephemeral modes). - */ -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED -#endif - -/* Helper to state that certificate-based client authentication through ECDSA - * is supported in TLS 1.2 */ -#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) && \ - defined(MBEDTLS_PK_CAN_ECDSA_SIGN) && defined(MBEDTLS_PK_CAN_ECDSA_VERIFY) -#define MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED -#endif - -/* ECDSA required for certificates in either TLS 1.2 or 1.3 */ -#if defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ANY_ALLOWED_ENABLED -#endif - -/* Key exchanges involving server signature in ServerKeyExchange */ -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED -#endif - -/* Key exchanges using ECDH */ -#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED -#endif - -/* Key exchanges that don't involve ephemeral keys */ -#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED -#endif - -/* Key exchanges that involve ephemeral keys */ -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED -#endif - -/* Key exchanges using a PSK */ -#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED -#endif - -/* Key exchanges using DHE */ -#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED -#endif - -/* Key exchanges using ECDHE */ -#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED -#endif - -/* TLS 1.2 key exchanges using ECDH or ECDHE*/ -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED -#endif - -/* TLS 1.3 PSK key exchanges */ -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED -#endif - -/* TLS 1.2 or 1.3 key exchanges with PSK */ -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) -#define MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED -#endif - -/* TLS 1.3 ephemeral key exchanges */ -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED -#endif - -/* TLS 1.3 key exchanges using ECDHE */ -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED) && \ - defined(PSA_WANT_ALG_ECDH) -#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_ECDHE_ENABLED -#endif - -/* TLS 1.2 or 1.3 key exchanges using ECDH or ECDHE */ -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_ECDHE_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED -#endif - -/* TLS 1.2 XXDH key exchanges: ECDH or ECDHE or FFDH */ -#if (defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED)) -#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_1_2_ENABLED -#endif - -/* The handshake params structure has a set of fields called xxdh_psa which are used: - * - by TLS 1.2 with `USE_PSA` to do ECDH or ECDHE; - * - by TLS 1.3 to do ECDHE or FFDHE. - * The following macros can be used to guard their declaration and use. - */ -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) && \ - defined(MBEDTLS_USE_PSA_CRYPTO) -#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_1_2_ENABLED -#endif -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_1_2_ENABLED) || \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED) -#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED -#endif - -typedef struct mbedtls_ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t; - -#define MBEDTLS_CIPHERSUITE_WEAK 0x01 /**< Weak ciphersuite flag */ -#define MBEDTLS_CIPHERSUITE_SHORT_TAG 0x02 /**< Short authentication tag, - eg for CCM_8 */ -#define MBEDTLS_CIPHERSUITE_NODTLS 0x04 /**< Can't be used with DTLS */ - -/** - * \brief This structure is used for storing ciphersuite information - * - * \note members are defined using integral types instead of enums - * in order to pack structure and reduce memory usage by internal - * \c ciphersuite_definitions[] - */ -struct mbedtls_ssl_ciphersuite_t { - int MBEDTLS_PRIVATE(id); - const char *MBEDTLS_PRIVATE(name); - - uint8_t MBEDTLS_PRIVATE(cipher); /* mbedtls_cipher_type_t */ - uint8_t MBEDTLS_PRIVATE(mac); /* mbedtls_md_type_t */ - uint8_t MBEDTLS_PRIVATE(key_exchange); /* mbedtls_key_exchange_type_t */ - uint8_t MBEDTLS_PRIVATE(flags); - - uint16_t MBEDTLS_PRIVATE(min_tls_version); /* mbedtls_ssl_protocol_version */ - uint16_t MBEDTLS_PRIVATE(max_tls_version); /* mbedtls_ssl_protocol_version */ -}; - -const int *mbedtls_ssl_list_ciphersuites(void); - -const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_string(const char *ciphersuite_name); -const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_id(int ciphersuite_id); - -#if defined(MBEDTLS_PK_C) -mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_pk_alg(const mbedtls_ssl_ciphersuite_t *info); -#if defined(MBEDTLS_USE_PSA_CRYPTO) -psa_algorithm_t mbedtls_ssl_get_ciphersuite_sig_pk_psa_alg(const mbedtls_ssl_ciphersuite_t *info); -psa_key_usage_t mbedtls_ssl_get_ciphersuite_sig_pk_psa_usage(const mbedtls_ssl_ciphersuite_t *info); -#endif -mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_alg(const mbedtls_ssl_ciphersuite_t *info); -#endif - -int mbedtls_ssl_ciphersuite_uses_ec(const mbedtls_ssl_ciphersuite_t *info); -int mbedtls_ssl_ciphersuite_uses_psk(const mbedtls_ssl_ciphersuite_t *info); - -static inline const char *mbedtls_ssl_ciphersuite_get_name(const mbedtls_ssl_ciphersuite_t *info) -{ - return info->MBEDTLS_PRIVATE(name); -} - -size_t mbedtls_ssl_ciphersuite_get_cipher_key_bitlen(const mbedtls_ssl_ciphersuite_t *info); - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED) -static inline int mbedtls_ssl_ciphersuite_has_pfs(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_DHE_RSA: - case MBEDTLS_KEY_EXCHANGE_DHE_PSK: - case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK: - case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: - case MBEDTLS_KEY_EXCHANGE_ECJPAKE: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED */ - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED) -static inline int mbedtls_ssl_ciphersuite_no_pfs(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: - case MBEDTLS_KEY_EXCHANGE_RSA: - case MBEDTLS_KEY_EXCHANGE_PSK: - case MBEDTLS_KEY_EXCHANGE_RSA_PSK: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED */ - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) -static inline int mbedtls_ssl_ciphersuite_uses_ecdh(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED */ - -static inline int mbedtls_ssl_ciphersuite_cert_req_allowed(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_RSA: - case MBEDTLS_KEY_EXCHANGE_DHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: - return 1; - - default: - return 0; - } -} - -static inline int mbedtls_ssl_ciphersuite_uses_srv_cert(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_RSA: - case MBEDTLS_KEY_EXCHANGE_RSA_PSK: - case MBEDTLS_KEY_EXCHANGE_DHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: - return 1; - - default: - return 0; - } -} - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED) -static inline int mbedtls_ssl_ciphersuite_uses_dhe(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_DHE_RSA: - case MBEDTLS_KEY_EXCHANGE_DHE_PSK: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED) */ - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) -static inline int mbedtls_ssl_ciphersuite_uses_ecdhe(const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) */ - -#if defined(MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED) -static inline int mbedtls_ssl_ciphersuite_uses_server_signature( - const mbedtls_ssl_ciphersuite_t *info) -{ - switch (info->MBEDTLS_PRIVATE(key_exchange)) { - case MBEDTLS_KEY_EXCHANGE_DHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: - case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: - return 1; - - default: - return 0; - } -} -#endif /* MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED */ - -#ifdef __cplusplus -} -#endif - -#endif /* ssl_ciphersuites.h */ +/** + * \file ssl_ciphersuites.h + * + * \brief SSL Ciphersuites for Mbed TLS + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_CIPHERSUITES_H +#define MBEDTLS_SSL_CIPHERSUITES_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/pk.h" +#include "mbedtls/cipher.h" +#include "mbedtls/md.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Supported ciphersuites (Official IANA names) + */ +#define MBEDTLS_TLS_RSA_WITH_NULL_MD5 0x01 /**< Weak! */ +#define MBEDTLS_TLS_RSA_WITH_NULL_SHA 0x02 /**< Weak! */ + +#define MBEDTLS_TLS_PSK_WITH_NULL_SHA 0x2C /**< Weak! */ +#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA 0x2D /**< Weak! */ +#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA 0x2E /**< Weak! */ +#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA 0x2F + +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA 0x33 +#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA 0x35 +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA 0x39 + +#define MBEDTLS_TLS_RSA_WITH_NULL_SHA256 0x3B /**< Weak! */ +#define MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 0x3C /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 0x3D /**< TLS 1.2 */ + +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA 0x41 +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA 0x45 + +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 0x67 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 0x6B /**< TLS 1.2 */ + +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA 0x84 +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA 0x88 + +#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA 0x8C +#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA 0x8D + +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA 0x90 +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA 0x91 + +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA 0x94 +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA 0x95 + +#define MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 0x9C /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 0x9D /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 0x9E /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 0x9F /**< TLS 1.2 */ + +#define MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 0xA8 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 0xA9 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 0xAA /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 0xAB /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 0xAC /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 0xAD /**< TLS 1.2 */ + +#define MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 0xAE +#define MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 0xAF +#define MBEDTLS_TLS_PSK_WITH_NULL_SHA256 0xB0 /**< Weak! */ +#define MBEDTLS_TLS_PSK_WITH_NULL_SHA384 0xB1 /**< Weak! */ + +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 0xB2 +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 0xB3 +#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 0xB4 /**< Weak! */ +#define MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 0xB5 /**< Weak! */ + +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 0xB6 +#define MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 0xB7 +#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 0xB8 /**< Weak! */ +#define MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 0xB9 /**< Weak! */ + +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBA /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xBE /**< TLS 1.2 */ + +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC0 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 0xC4 /**< TLS 1.2 */ + +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA 0xC001 /**< Weak! */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA 0xC004 +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA 0xC005 + +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA 0xC006 /**< Weak! */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA 0xC009 +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA 0xC00A + +#define MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA 0xC00B /**< Weak! */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA 0xC00E +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA 0xC00F + +#define MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA 0xC010 /**< Weak! */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA 0xC013 +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA 0xC014 + +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 0xC023 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 0xC024 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 0xC025 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 0xC026 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 0xC027 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 0xC028 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 0xC029 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 0xC02A /**< TLS 1.2 */ + +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 0xC02B /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 0xC02C /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 0xC02D /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 0xC02E /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 0xC02F /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 0xC030 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 0xC031 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 0xC032 /**< TLS 1.2 */ + +#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA 0xC035 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA 0xC036 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 0xC037 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 0xC038 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA 0xC039 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 0xC03A +#define MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 0xC03B + +#define MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 0xC03C /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 0xC03D /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 0xC044 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 0xC045 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 0xC048 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 0xC049 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 0xC04A /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 0xC04B /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 0xC04C /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 0xC04D /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 0xC04E /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 0xC04F /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 0xC050 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 0xC051 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 0xC052 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 0xC053 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 0xC05C /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 0xC05D /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 0xC05E /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 0xC05F /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 0xC060 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 0xC061 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 0xC062 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 0xC063 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 0xC064 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 0xC065 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 0xC066 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 0xC067 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 0xC068 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 0xC069 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 0xC06A /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 0xC06B /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 0xC06C /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 0xC06D /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 0xC06E /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 0xC06F /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 0xC070 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 0xC071 /**< TLS 1.2 */ + +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC072 +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC073 +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 0xC074 +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 0xC075 +#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xC076 +#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 0xC077 +#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 0xC078 +#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 0xC079 + +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC07A /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC07B /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC07C /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC07D /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC086 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC087 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 0xC088 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 0xC089 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC08A /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC08B /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 0xC08C /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 0xC08D /**< TLS 1.2 */ + +#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC08E /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC08F /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC090 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC091 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 0xC092 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 0xC093 /**< TLS 1.2 */ + +#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC094 +#define MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC095 +#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC096 +#define MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC097 +#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC098 +#define MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC099 +#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 0xC09A +#define MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 0xC09B + +#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM 0xC09C /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM 0xC09D /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM 0xC09E /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM 0xC09F /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_AES_128_CCM_8 0xC0A0 /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_WITH_AES_256_CCM_8 0xC0A1 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CCM_8 0xC0A2 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CCM_8 0xC0A3 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM 0xC0A4 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM 0xC0A5 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM 0xC0A6 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM 0xC0A7 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8 0xC0A8 /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8 0xC0A9 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CCM_8 0xC0AA /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CCM_8 0xC0AB /**< TLS 1.2 */ +/* The last two are named with PSK_DHE in the RFC, which looks like a typo */ + +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM 0xC0AC /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM 0xC0AD /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8 0xC0AE /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8 0xC0AF /**< TLS 1.2 */ + +#define MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 0xC0FF /**< experimental */ + +/* RFC 7905 */ +#define MBEDTLS_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 0xCCA8 /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 0xCCA9 /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 0xCCAA /**< TLS 1.2 */ +#define MBEDTLS_TLS_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAB /**< TLS 1.2 */ +#define MBEDTLS_TLS_ECDHE_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAC /**< TLS 1.2 */ +#define MBEDTLS_TLS_DHE_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAD /**< TLS 1.2 */ +#define MBEDTLS_TLS_RSA_PSK_WITH_CHACHA20_POLY1305_SHA256 0xCCAE /**< TLS 1.2 */ + +/* RFC 8446, Appendix B.4 */ +#define MBEDTLS_TLS1_3_AES_128_GCM_SHA256 0x1301 /**< TLS 1.3 */ +#define MBEDTLS_TLS1_3_AES_256_GCM_SHA384 0x1302 /**< TLS 1.3 */ +#define MBEDTLS_TLS1_3_CHACHA20_POLY1305_SHA256 0x1303 /**< TLS 1.3 */ +#define MBEDTLS_TLS1_3_AES_128_CCM_SHA256 0x1304 /**< TLS 1.3 */ +#define MBEDTLS_TLS1_3_AES_128_CCM_8_SHA256 0x1305 /**< TLS 1.3 */ + +/* Reminder: update mbedtls_ssl_premaster_secret when adding a new key exchange. + * Reminder: update MBEDTLS_KEY_EXCHANGE__xxx below + */ +typedef enum { + MBEDTLS_KEY_EXCHANGE_NONE = 0, + MBEDTLS_KEY_EXCHANGE_RSA, + MBEDTLS_KEY_EXCHANGE_DHE_RSA, + MBEDTLS_KEY_EXCHANGE_ECDHE_RSA, + MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA, + MBEDTLS_KEY_EXCHANGE_PSK, + MBEDTLS_KEY_EXCHANGE_DHE_PSK, + MBEDTLS_KEY_EXCHANGE_RSA_PSK, + MBEDTLS_KEY_EXCHANGE_ECDHE_PSK, + MBEDTLS_KEY_EXCHANGE_ECDH_RSA, + MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA, + MBEDTLS_KEY_EXCHANGE_ECJPAKE, +} mbedtls_key_exchange_type_t; + +/* Key exchanges using a certificate */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED +#endif + +/* Key exchanges in either TLS 1.2 or 1.3 which are using an ECDSA + * signature */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_WITH_ECDSA_ANY_ENABLED +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +#define MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED +#endif + +/* Key exchanges allowing client certificate requests. + * + * Note: that's almost the same as MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED + * above, except RSA-PSK uses a server certificate but no client cert. + * + * Note: this difference is specific to TLS 1.2, as with TLS 1.3, things are + * more symmetrical: client certs and server certs are either both allowed + * (Ephemeral mode) or both disallowed (PSK and PKS-Ephemeral modes). + */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED +#endif + +/* Helper to state that certificate-based client authentication through ECDSA + * is supported in TLS 1.2 */ +#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) && \ + defined(MBEDTLS_PK_CAN_ECDSA_SIGN) && defined(MBEDTLS_PK_CAN_ECDSA_VERIFY) +#define MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED +#endif + +/* ECDSA required for certificates in either TLS 1.2 or 1.3 */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ANY_ALLOWED_ENABLED +#endif + +/* Key exchanges involving server signature in ServerKeyExchange */ +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED +#endif + +/* Key exchanges using ECDH */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED +#endif + +/* Key exchanges that don't involve ephemeral keys */ +#if defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED +#endif + +/* Key exchanges that involve ephemeral keys */ +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED +#endif + +/* Key exchanges using a PSK */ +#if defined(MBEDTLS_KEY_EXCHANGE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED +#endif + +/* Key exchanges using DHE */ +#if defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED +#endif + +/* Key exchanges using ECDHE */ +#if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED +#endif + +/* TLS 1.2 key exchanges using ECDH or ECDHE*/ +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED +#endif + +/* TLS 1.3 PSK key exchanges */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED +#endif + +/* TLS 1.2 or 1.3 key exchanges with PSK */ +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) +#define MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED +#endif + +/* TLS 1.3 ephemeral key exchanges */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED) +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED +#endif + +/* TLS 1.3 key exchanges using ECDHE */ +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED) && \ + defined(PSA_WANT_ALG_ECDH) +#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_ECDHE_ENABLED +#endif + +/* TLS 1.2 or 1.3 key exchanges using ECDH or ECDHE */ +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_ECDHE_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED +#endif + +/* TLS 1.2 XXDH key exchanges: ECDH or ECDHE or FFDH */ +#if (defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED)) +#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_1_2_ENABLED +#endif + +/* The handshake params structure has a set of fields called xxdh_psa which are used: + * - by TLS 1.2 with `USE_PSA` to do ECDH or ECDHE; + * - by TLS 1.3 to do ECDHE or FFDHE. + * The following macros can be used to guard their declaration and use. + */ +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) && \ + defined(MBEDTLS_USE_PSA_CRYPTO) +#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_1_2_ENABLED +#endif +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_1_2_ENABLED) || \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_EPHEMERAL_ENABLED) +#define MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED +#endif + +typedef struct mbedtls_ssl_ciphersuite_t mbedtls_ssl_ciphersuite_t; + +#define MBEDTLS_CIPHERSUITE_WEAK 0x01 /**< Weak ciphersuite flag */ +#define MBEDTLS_CIPHERSUITE_SHORT_TAG 0x02 /**< Short authentication tag, + eg for CCM_8 */ +#define MBEDTLS_CIPHERSUITE_NODTLS 0x04 /**< Can't be used with DTLS */ + +/** + * \brief This structure is used for storing ciphersuite information + * + * \note members are defined using integral types instead of enums + * in order to pack structure and reduce memory usage by internal + * \c ciphersuite_definitions[] + */ +struct mbedtls_ssl_ciphersuite_t { + int MBEDTLS_PRIVATE(id); + const char *MBEDTLS_PRIVATE(name); + + uint8_t MBEDTLS_PRIVATE(cipher); /* mbedtls_cipher_type_t */ + uint8_t MBEDTLS_PRIVATE(mac); /* mbedtls_md_type_t */ + uint8_t MBEDTLS_PRIVATE(key_exchange); /* mbedtls_key_exchange_type_t */ + uint8_t MBEDTLS_PRIVATE(flags); + + uint16_t MBEDTLS_PRIVATE(min_tls_version); /* mbedtls_ssl_protocol_version */ + uint16_t MBEDTLS_PRIVATE(max_tls_version); /* mbedtls_ssl_protocol_version */ +}; + +const int *mbedtls_ssl_list_ciphersuites(void); + +const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_string(const char *ciphersuite_name); +const mbedtls_ssl_ciphersuite_t *mbedtls_ssl_ciphersuite_from_id(int ciphersuite_id); + +#if defined(MBEDTLS_PK_C) +mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_pk_alg(const mbedtls_ssl_ciphersuite_t *info); +#if defined(MBEDTLS_USE_PSA_CRYPTO) +psa_algorithm_t mbedtls_ssl_get_ciphersuite_sig_pk_psa_alg(const mbedtls_ssl_ciphersuite_t *info); +psa_key_usage_t mbedtls_ssl_get_ciphersuite_sig_pk_psa_usage(const mbedtls_ssl_ciphersuite_t *info); +#endif +mbedtls_pk_type_t mbedtls_ssl_get_ciphersuite_sig_alg(const mbedtls_ssl_ciphersuite_t *info); +#endif + +int mbedtls_ssl_ciphersuite_uses_ec(const mbedtls_ssl_ciphersuite_t *info); +int mbedtls_ssl_ciphersuite_uses_psk(const mbedtls_ssl_ciphersuite_t *info); + +static inline const char *mbedtls_ssl_ciphersuite_get_name(const mbedtls_ssl_ciphersuite_t *info) +{ + return info->MBEDTLS_PRIVATE(name); +} + +size_t mbedtls_ssl_ciphersuite_get_cipher_key_bitlen(const mbedtls_ssl_ciphersuite_t *info); + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED) +static inline int mbedtls_ssl_ciphersuite_has_pfs(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_DHE_RSA: + case MBEDTLS_KEY_EXCHANGE_DHE_PSK: + case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK: + case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: + case MBEDTLS_KEY_EXCHANGE_ECJPAKE: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_PFS_ENABLED */ + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED) +static inline int mbedtls_ssl_ciphersuite_no_pfs(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: + case MBEDTLS_KEY_EXCHANGE_RSA: + case MBEDTLS_KEY_EXCHANGE_PSK: + case MBEDTLS_KEY_EXCHANGE_RSA_PSK: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_NON_PFS_ENABLED */ + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED) +static inline int mbedtls_ssl_ciphersuite_uses_ecdh(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDH_ENABLED */ + +static inline int mbedtls_ssl_ciphersuite_cert_req_allowed(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_RSA: + case MBEDTLS_KEY_EXCHANGE_DHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: + return 1; + + default: + return 0; + } +} + +static inline int mbedtls_ssl_ciphersuite_uses_srv_cert(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_RSA: + case MBEDTLS_KEY_EXCHANGE_RSA_PSK: + case MBEDTLS_KEY_EXCHANGE_DHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: + return 1; + + default: + return 0; + } +} + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED) +static inline int mbedtls_ssl_ciphersuite_uses_dhe(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_DHE_RSA: + case MBEDTLS_KEY_EXCHANGE_DHE_PSK: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_DHE_ENABLED) */ + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) +static inline int mbedtls_ssl_ciphersuite_uses_ecdhe(const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_PSK: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_ECDHE_ENABLED) */ + +#if defined(MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED) +static inline int mbedtls_ssl_ciphersuite_uses_server_signature( + const mbedtls_ssl_ciphersuite_t *info) +{ + switch (info->MBEDTLS_PRIVATE(key_exchange)) { + case MBEDTLS_KEY_EXCHANGE_DHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_RSA: + case MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA: + return 1; + + default: + return 0; + } +} +#endif /* MBEDTLS_KEY_EXCHANGE_WITH_SERVER_SIGNATURE_ENABLED */ + +#ifdef __cplusplus +} +#endif + +#endif /* ssl_ciphersuites.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cookie.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cookie.h index 5cd1847..a4fb418 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cookie.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_cookie.h @@ -1,118 +1,118 @@ -/** - * \file ssl_cookie.h - * - * \brief DTLS cookie callbacks implementation - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_COOKIE_H -#define MBEDTLS_SSL_COOKIE_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/ssl.h" - -#if !defined(MBEDTLS_USE_PSA_CRYPTO) -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif -#endif /* !MBEDTLS_USE_PSA_CRYPTO */ - -/** - * \name SECTION: Module settings - * - * The configuration options you can set for this module are in this section. - * Either change them in mbedtls_config.h or define them on the compiler command line. - * \{ - */ -#ifndef MBEDTLS_SSL_COOKIE_TIMEOUT -#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ -#endif - -/** \} name SECTION: Module settings */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Context for the default cookie functions. - */ -typedef struct mbedtls_ssl_cookie_ctx { -#if defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(psa_hmac_key); /*!< key id for the HMAC portion */ - psa_algorithm_t MBEDTLS_PRIVATE(psa_hmac_alg); /*!< key algorithm for the HMAC portion */ -#else - mbedtls_md_context_t MBEDTLS_PRIVATE(hmac_ctx); /*!< context for the HMAC portion */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ -#if !defined(MBEDTLS_HAVE_TIME) - unsigned long MBEDTLS_PRIVATE(serial); /*!< serial number for expiration */ -#endif - unsigned long MBEDTLS_PRIVATE(timeout); /*!< timeout delay, in seconds if HAVE_TIME, - or in number of tickets issued */ - -#if !defined(MBEDTLS_USE_PSA_CRYPTO) -#if defined(MBEDTLS_THREADING_C) - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); -#endif -#endif /* !MBEDTLS_USE_PSA_CRYPTO */ -} mbedtls_ssl_cookie_ctx; - -/** - * \brief Initialize cookie context - */ -void mbedtls_ssl_cookie_init(mbedtls_ssl_cookie_ctx *ctx); - -/** - * \brief Setup cookie context (generate keys) - */ -int mbedtls_ssl_cookie_setup(mbedtls_ssl_cookie_ctx *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Set expiration delay for cookies - * (Default MBEDTLS_SSL_COOKIE_TIMEOUT) - * - * \param ctx Cookie context - * \param delay Delay, in seconds if HAVE_TIME, or in number of cookies - * issued in the meantime. - * 0 to disable expiration (NOT recommended) - */ -void mbedtls_ssl_cookie_set_timeout(mbedtls_ssl_cookie_ctx *ctx, unsigned long delay); - -/** - * \brief Free cookie context - */ -void mbedtls_ssl_cookie_free(mbedtls_ssl_cookie_ctx *ctx); - -/** - * \brief Generate cookie, see \c mbedtls_ssl_cookie_write_t - */ -mbedtls_ssl_cookie_write_t mbedtls_ssl_cookie_write; - -/** - * \brief Verify cookie, see \c mbedtls_ssl_cookie_write_t - */ -mbedtls_ssl_cookie_check_t mbedtls_ssl_cookie_check; - -#ifdef __cplusplus -} -#endif - -#endif /* ssl_cookie.h */ +/** + * \file ssl_cookie.h + * + * \brief DTLS cookie callbacks implementation + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_COOKIE_H +#define MBEDTLS_SSL_COOKIE_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/ssl.h" + +#if !defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif +#endif /* !MBEDTLS_USE_PSA_CRYPTO */ + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in mbedtls_config.h or define them on the compiler command line. + * \{ + */ +#ifndef MBEDTLS_SSL_COOKIE_TIMEOUT +#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ +#endif + +/** \} name SECTION: Module settings */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Context for the default cookie functions. + */ +typedef struct mbedtls_ssl_cookie_ctx { +#if defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_svc_key_id_t MBEDTLS_PRIVATE(psa_hmac_key); /*!< key id for the HMAC portion */ + psa_algorithm_t MBEDTLS_PRIVATE(psa_hmac_alg); /*!< key algorithm for the HMAC portion */ +#else + mbedtls_md_context_t MBEDTLS_PRIVATE(hmac_ctx); /*!< context for the HMAC portion */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#if !defined(MBEDTLS_HAVE_TIME) + unsigned long MBEDTLS_PRIVATE(serial); /*!< serial number for expiration */ +#endif + unsigned long MBEDTLS_PRIVATE(timeout); /*!< timeout delay, in seconds if HAVE_TIME, + or in number of tickets issued */ + +#if !defined(MBEDTLS_USE_PSA_CRYPTO) +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); +#endif +#endif /* !MBEDTLS_USE_PSA_CRYPTO */ +} mbedtls_ssl_cookie_ctx; + +/** + * \brief Initialize cookie context + */ +void mbedtls_ssl_cookie_init(mbedtls_ssl_cookie_ctx *ctx); + +/** + * \brief Setup cookie context (generate keys) + */ +int mbedtls_ssl_cookie_setup(mbedtls_ssl_cookie_ctx *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Set expiration delay for cookies + * (Default MBEDTLS_SSL_COOKIE_TIMEOUT) + * + * \param ctx Cookie context + * \param delay Delay, in seconds if HAVE_TIME, or in number of cookies + * issued in the meantime. + * 0 to disable expiration (NOT recommended) + */ +void mbedtls_ssl_cookie_set_timeout(mbedtls_ssl_cookie_ctx *ctx, unsigned long delay); + +/** + * \brief Free cookie context + */ +void mbedtls_ssl_cookie_free(mbedtls_ssl_cookie_ctx *ctx); + +/** + * \brief Generate cookie, see \c mbedtls_ssl_cookie_write_t + */ +mbedtls_ssl_cookie_write_t mbedtls_ssl_cookie_write; + +/** + * \brief Verify cookie, see \c mbedtls_ssl_cookie_write_t + */ +mbedtls_ssl_cookie_check_t mbedtls_ssl_cookie_check; + +#ifdef __cplusplus +} +#endif + +#endif /* ssl_cookie.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ticket.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ticket.h index 0cefe43..bbaa7e9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ticket.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/ssl_ticket.h @@ -1,193 +1,193 @@ -/** - * \file ssl_ticket.h - * - * \brief TLS server ticket callbacks implementation - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_TICKET_H -#define MBEDTLS_SSL_TICKET_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -/* - * This implementation of the session ticket callbacks includes key - * management, rotating the keys periodically in order to preserve forward - * secrecy, when MBEDTLS_HAVE_TIME is defined. - */ - -#include "mbedtls/ssl.h" -#include "mbedtls/cipher.h" - -#if defined(MBEDTLS_HAVE_TIME) -#include "mbedtls/platform_time.h" -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#include "psa/crypto.h" -#endif - -#if defined(MBEDTLS_THREADING_C) -#include "mbedtls/threading.h" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#define MBEDTLS_SSL_TICKET_MAX_KEY_BYTES 32 /*!< Max supported key length in bytes */ -#define MBEDTLS_SSL_TICKET_KEY_NAME_BYTES 4 /*!< key name length in bytes */ - -/** - * \brief Information for session ticket protection - */ -typedef struct mbedtls_ssl_ticket_key { - unsigned char MBEDTLS_PRIVATE(name)[MBEDTLS_SSL_TICKET_KEY_NAME_BYTES]; - /*!< random key identifier */ -#if defined(MBEDTLS_HAVE_TIME) - mbedtls_time_t MBEDTLS_PRIVATE(generation_time); /*!< key generation timestamp (seconds) */ -#endif -#if !defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_cipher_context_t MBEDTLS_PRIVATE(ctx); /*!< context for auth enc/decryption */ -#else - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(key); /*!< key used for auth enc/decryption */ - psa_algorithm_t MBEDTLS_PRIVATE(alg); /*!< algorithm of auth enc/decryption */ - psa_key_type_t MBEDTLS_PRIVATE(key_type); /*!< key type */ - size_t MBEDTLS_PRIVATE(key_bits); /*!< key length in bits */ -#endif -} -mbedtls_ssl_ticket_key; - -/** - * \brief Context for session ticket handling functions - */ -typedef struct mbedtls_ssl_ticket_context { - mbedtls_ssl_ticket_key MBEDTLS_PRIVATE(keys)[2]; /*!< ticket protection keys */ - unsigned char MBEDTLS_PRIVATE(active); /*!< index of the currently active key */ - - uint32_t MBEDTLS_PRIVATE(ticket_lifetime); /*!< lifetime of tickets in seconds */ - - /** Callback for getting (pseudo-)random numbers */ - int(*MBEDTLS_PRIVATE(f_rng))(void *, unsigned char *, size_t); - void *MBEDTLS_PRIVATE(p_rng); /*!< context for the RNG function */ - -#if defined(MBEDTLS_THREADING_C) - mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); -#endif -} -mbedtls_ssl_ticket_context; - -/** - * \brief Initialize a ticket context. - * (Just make it ready for mbedtls_ssl_ticket_setup() - * or mbedtls_ssl_ticket_free().) - * - * \param ctx Context to be initialized - */ -void mbedtls_ssl_ticket_init(mbedtls_ssl_ticket_context *ctx); - -/** - * \brief Prepare context to be actually used - * - * \param ctx Context to be set up - * \param f_rng RNG callback function (mandatory) - * \param p_rng RNG callback context - * \param cipher AEAD cipher to use for ticket protection. - * Recommended value: MBEDTLS_CIPHER_AES_256_GCM. - * \param lifetime Tickets lifetime in seconds - * Recommended value: 86400 (one day). - * - * \note It is highly recommended to select a cipher that is at - * least as strong as the strongest ciphersuite - * supported. Usually that means a 256-bit key. - * - * \note The lifetime of the keys is twice the lifetime of tickets. - * It is recommended to pick a reasonable lifetime so as not - * to negate the benefits of forward secrecy. - * - * \return 0 if successful, - * or a specific MBEDTLS_ERR_XXX error code - */ -int mbedtls_ssl_ticket_setup(mbedtls_ssl_ticket_context *ctx, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, - mbedtls_cipher_type_t cipher, - uint32_t lifetime); - -/** - * \brief Rotate session ticket encryption key to new specified key. - * Provides for external control of session ticket encryption - * key rotation, e.g. for synchronization between different - * machines. If this function is not used, or if not called - * before ticket lifetime expires, then a new session ticket - * encryption key is generated internally in order to avoid - * unbounded session ticket encryption key lifetimes. - * - * \param ctx Context to be set up - * \param name Session ticket encryption key name - * \param nlength Session ticket encryption key name length in bytes - * \param k Session ticket encryption key - * \param klength Session ticket encryption key length in bytes - * \param lifetime Tickets lifetime in seconds - * Recommended value: 86400 (one day). - * - * \note \c name and \c k are recommended to be cryptographically - * random data. - * - * \note \c nlength must match sizeof( ctx->name ) - * - * \note \c klength must be sufficient for use by cipher specified - * to \c mbedtls_ssl_ticket_setup - * - * \note The lifetime of the keys is twice the lifetime of tickets. - * It is recommended to pick a reasonable lifetime so as not - * to negate the benefits of forward secrecy. - * - * \return 0 if successful, - * or a specific MBEDTLS_ERR_XXX error code - */ -int mbedtls_ssl_ticket_rotate(mbedtls_ssl_ticket_context *ctx, - const unsigned char *name, size_t nlength, - const unsigned char *k, size_t klength, - uint32_t lifetime); - -/** - * \brief Implementation of the ticket write callback - * - * \note See \c mbedtls_ssl_ticket_write_t for description - */ -mbedtls_ssl_ticket_write_t mbedtls_ssl_ticket_write; - -/** - * \brief Implementation of the ticket parse callback - * - * \note See \c mbedtls_ssl_ticket_parse_t for description - */ -mbedtls_ssl_ticket_parse_t mbedtls_ssl_ticket_parse; - -/** - * \brief Free a context's content and zeroize it. - * - * \param ctx Context to be cleaned up - */ -void mbedtls_ssl_ticket_free(mbedtls_ssl_ticket_context *ctx); - -#ifdef __cplusplus -} -#endif - -#endif /* ssl_ticket.h */ +/** + * \file ssl_ticket.h + * + * \brief TLS server ticket callbacks implementation + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_TICKET_H +#define MBEDTLS_SSL_TICKET_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +/* + * This implementation of the session ticket callbacks includes key + * management, rotating the keys periodically in order to preserve forward + * secrecy, when MBEDTLS_HAVE_TIME is defined. + */ + +#include "mbedtls/ssl.h" +#include "mbedtls/cipher.h" + +#if defined(MBEDTLS_HAVE_TIME) +#include "mbedtls/platform_time.h" +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#include "psa/crypto.h" +#endif + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define MBEDTLS_SSL_TICKET_MAX_KEY_BYTES 32 /*!< Max supported key length in bytes */ +#define MBEDTLS_SSL_TICKET_KEY_NAME_BYTES 4 /*!< key name length in bytes */ + +/** + * \brief Information for session ticket protection + */ +typedef struct mbedtls_ssl_ticket_key { + unsigned char MBEDTLS_PRIVATE(name)[MBEDTLS_SSL_TICKET_KEY_NAME_BYTES]; + /*!< random key identifier */ +#if defined(MBEDTLS_HAVE_TIME) + mbedtls_time_t MBEDTLS_PRIVATE(generation_time); /*!< key generation timestamp (seconds) */ +#endif +#if !defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_cipher_context_t MBEDTLS_PRIVATE(ctx); /*!< context for auth enc/decryption */ +#else + mbedtls_svc_key_id_t MBEDTLS_PRIVATE(key); /*!< key used for auth enc/decryption */ + psa_algorithm_t MBEDTLS_PRIVATE(alg); /*!< algorithm of auth enc/decryption */ + psa_key_type_t MBEDTLS_PRIVATE(key_type); /*!< key type */ + size_t MBEDTLS_PRIVATE(key_bits); /*!< key length in bits */ +#endif +} +mbedtls_ssl_ticket_key; + +/** + * \brief Context for session ticket handling functions + */ +typedef struct mbedtls_ssl_ticket_context { + mbedtls_ssl_ticket_key MBEDTLS_PRIVATE(keys)[2]; /*!< ticket protection keys */ + unsigned char MBEDTLS_PRIVATE(active); /*!< index of the currently active key */ + + uint32_t MBEDTLS_PRIVATE(ticket_lifetime); /*!< lifetime of tickets in seconds */ + + /** Callback for getting (pseudo-)random numbers */ + int(*MBEDTLS_PRIVATE(f_rng))(void *, unsigned char *, size_t); + void *MBEDTLS_PRIVATE(p_rng); /*!< context for the RNG function */ + +#if defined(MBEDTLS_THREADING_C) + mbedtls_threading_mutex_t MBEDTLS_PRIVATE(mutex); +#endif +} +mbedtls_ssl_ticket_context; + +/** + * \brief Initialize a ticket context. + * (Just make it ready for mbedtls_ssl_ticket_setup() + * or mbedtls_ssl_ticket_free().) + * + * \param ctx Context to be initialized + */ +void mbedtls_ssl_ticket_init(mbedtls_ssl_ticket_context *ctx); + +/** + * \brief Prepare context to be actually used + * + * \param ctx Context to be set up + * \param f_rng RNG callback function (mandatory) + * \param p_rng RNG callback context + * \param cipher AEAD cipher to use for ticket protection. + * Recommended value: MBEDTLS_CIPHER_AES_256_GCM. + * \param lifetime Tickets lifetime in seconds + * Recommended value: 86400 (one day). + * + * \note It is highly recommended to select a cipher that is at + * least as strong as the strongest ciphersuite + * supported. Usually that means a 256-bit key. + * + * \note The lifetime of the keys is twice the lifetime of tickets. + * It is recommended to pick a reasonable lifetime so as not + * to negate the benefits of forward secrecy. + * + * \return 0 if successful, + * or a specific MBEDTLS_ERR_XXX error code + */ +int mbedtls_ssl_ticket_setup(mbedtls_ssl_ticket_context *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_cipher_type_t cipher, + uint32_t lifetime); + +/** + * \brief Rotate session ticket encryption key to new specified key. + * Provides for external control of session ticket encryption + * key rotation, e.g. for synchronization between different + * machines. If this function is not used, or if not called + * before ticket lifetime expires, then a new session ticket + * encryption key is generated internally in order to avoid + * unbounded session ticket encryption key lifetimes. + * + * \param ctx Context to be set up + * \param name Session ticket encryption key name + * \param nlength Session ticket encryption key name length in bytes + * \param k Session ticket encryption key + * \param klength Session ticket encryption key length in bytes + * \param lifetime Tickets lifetime in seconds + * Recommended value: 86400 (one day). + * + * \note \c name and \c k are recommended to be cryptographically + * random data. + * + * \note \c nlength must match sizeof( ctx->name ) + * + * \note \c klength must be sufficient for use by cipher specified + * to \c mbedtls_ssl_ticket_setup + * + * \note The lifetime of the keys is twice the lifetime of tickets. + * It is recommended to pick a reasonable lifetime so as not + * to negate the benefits of forward secrecy. + * + * \return 0 if successful, + * or a specific MBEDTLS_ERR_XXX error code + */ +int mbedtls_ssl_ticket_rotate(mbedtls_ssl_ticket_context *ctx, + const unsigned char *name, size_t nlength, + const unsigned char *k, size_t klength, + uint32_t lifetime); + +/** + * \brief Implementation of the ticket write callback + * + * \note See \c mbedtls_ssl_ticket_write_t for description + */ +mbedtls_ssl_ticket_write_t mbedtls_ssl_ticket_write; + +/** + * \brief Implementation of the ticket parse callback + * + * \note See \c mbedtls_ssl_ticket_parse_t for description + */ +mbedtls_ssl_ticket_parse_t mbedtls_ssl_ticket_parse; + +/** + * \brief Free a context's content and zeroize it. + * + * \param ctx Context to be cleaned up + */ +void mbedtls_ssl_ticket_free(mbedtls_ssl_ticket_context *ctx); + +#ifdef __cplusplus +} +#endif + +#endif /* ssl_ticket.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/threading.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/threading.h index 8c87b90..c29cfcf 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/threading.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/threading.h @@ -1,138 +1,138 @@ -/** - * \file threading.h - * - * \brief Threading abstraction layer - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_THREADING_H -#define MBEDTLS_THREADING_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** Bad input parameters to function. */ -#define MBEDTLS_ERR_THREADING_BAD_INPUT_DATA -0x001C -/** Locking / unlocking / free failed with error code. */ -#define MBEDTLS_ERR_THREADING_MUTEX_ERROR -0x001E - -#if defined(MBEDTLS_THREADING_PTHREAD) -#include -typedef struct mbedtls_threading_mutex_t { - pthread_mutex_t MBEDTLS_PRIVATE(mutex); - /* is_valid is 0 after a failed init or a free, and nonzero after a - * successful init. This field is not considered part of the public - * API of Mbed TLS and may change without notice. */ - char MBEDTLS_PRIVATE(is_valid); -} mbedtls_threading_mutex_t; -#endif - -#if defined(MBEDTLS_THREADING_ALT) -/* You should define the mbedtls_threading_mutex_t type in your header */ -#include "threading_alt.h" - -/** - * \brief Set your alternate threading implementation function - * pointers and initialize global mutexes. If used, this - * function must be called once in the main thread before any - * other Mbed TLS function is called, and - * mbedtls_threading_free_alt() must be called once in the main - * thread after all other Mbed TLS functions. - * - * \note mutex_init() and mutex_free() don't return a status code. - * If mutex_init() fails, it should leave its argument (the - * mutex) in a state such that mutex_lock() will fail when - * called with this argument. - * - * \param mutex_init the init function implementation - * \param mutex_free the free function implementation - * \param mutex_lock the lock function implementation - * \param mutex_unlock the unlock function implementation - */ -void mbedtls_threading_set_alt(void (*mutex_init)(mbedtls_threading_mutex_t *), - void (*mutex_free)(mbedtls_threading_mutex_t *), - int (*mutex_lock)(mbedtls_threading_mutex_t *), - int (*mutex_unlock)(mbedtls_threading_mutex_t *)); - -/** - * \brief Free global mutexes. - */ -void mbedtls_threading_free_alt(void); -#endif /* MBEDTLS_THREADING_ALT */ - -#if defined(MBEDTLS_THREADING_C) -/* - * The function pointers for mutex_init, mutex_free, mutex_ and mutex_unlock - * - * All these functions are expected to work or the result will be undefined. - */ -extern void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *mutex); -extern void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *mutex); -extern int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *mutex); -extern int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *mutex); - -/* - * Global mutexes - */ -#if defined(MBEDTLS_FS_IO) -extern mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex; -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_C) -extern mbedtls_threading_mutex_t mbedtls_psa_slots_mutex; -#endif - -#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) -/* This mutex may or may not be used in the default definition of - * mbedtls_platform_gmtime_r(), but in order to determine that, - * we need to check POSIX features, hence modify _POSIX_C_SOURCE. - * With the current approach, this declaration is orphaned, lacking - * an accompanying definition, in case mbedtls_platform_gmtime_r() - * doesn't need it, but that's not a problem. */ -extern mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex; -#endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */ - -/* - * Helper macros for mutex handling - */ -#define MBEDTLS_MUTEX_LOCK_CHECK( mutex ) \ - do \ - { \ - if( mbedtls_mutex_lock( mutex ) != 0 ) \ - return( PSA_ERROR_BAD_STATE ); \ - } while( 0 ) -#define MBEDTLS_MUTEX_UNLOCK_CHECK( mutex ) \ - do \ - { \ - if( mbedtls_mutex_unlock( mutex ) != 0 ) \ - return( PSA_ERROR_BAD_STATE ); \ - } while( 0 ) -#else/* MBEDTLS_THREADING_C */ -#define MBEDTLS_MUTEX_LOCK_CHECK( mutex ) -#define MBEDTLS_MUTEX_UNLOCK_CHECK( mutex ) -#endif -#ifdef __cplusplus -} -#endif - -#endif /* threading.h */ +/** + * \file threading.h + * + * \brief Threading abstraction layer + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_THREADING_H +#define MBEDTLS_THREADING_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Bad input parameters to function. */ +#define MBEDTLS_ERR_THREADING_BAD_INPUT_DATA -0x001C +/** Locking / unlocking / free failed with error code. */ +#define MBEDTLS_ERR_THREADING_MUTEX_ERROR -0x001E + +#if defined(MBEDTLS_THREADING_PTHREAD) +#include +typedef struct mbedtls_threading_mutex_t { + pthread_mutex_t MBEDTLS_PRIVATE(mutex); + /* is_valid is 0 after a failed init or a free, and nonzero after a + * successful init. This field is not considered part of the public + * API of Mbed TLS and may change without notice. */ + char MBEDTLS_PRIVATE(is_valid); +} mbedtls_threading_mutex_t; +#endif + +#if defined(MBEDTLS_THREADING_ALT) +/* You should define the mbedtls_threading_mutex_t type in your header */ +#include "threading_alt.h" + +/** + * \brief Set your alternate threading implementation function + * pointers and initialize global mutexes. If used, this + * function must be called once in the main thread before any + * other Mbed TLS function is called, and + * mbedtls_threading_free_alt() must be called once in the main + * thread after all other Mbed TLS functions. + * + * \note mutex_init() and mutex_free() don't return a status code. + * If mutex_init() fails, it should leave its argument (the + * mutex) in a state such that mutex_lock() will fail when + * called with this argument. + * + * \param mutex_init the init function implementation + * \param mutex_free the free function implementation + * \param mutex_lock the lock function implementation + * \param mutex_unlock the unlock function implementation + */ +void mbedtls_threading_set_alt(void (*mutex_init)(mbedtls_threading_mutex_t *), + void (*mutex_free)(mbedtls_threading_mutex_t *), + int (*mutex_lock)(mbedtls_threading_mutex_t *), + int (*mutex_unlock)(mbedtls_threading_mutex_t *)); + +/** + * \brief Free global mutexes. + */ +void mbedtls_threading_free_alt(void); +#endif /* MBEDTLS_THREADING_ALT */ + +#if defined(MBEDTLS_THREADING_C) +/* + * The function pointers for mutex_init, mutex_free, mutex_ and mutex_unlock + * + * All these functions are expected to work or the result will be undefined. + */ +extern void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *mutex); +extern void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *mutex); +extern int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *mutex); +extern int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *mutex); + +/* + * Global mutexes + */ +#if defined(MBEDTLS_FS_IO) +extern mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex; +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_C) +extern mbedtls_threading_mutex_t mbedtls_psa_slots_mutex; +#endif + +#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) +/* This mutex may or may not be used in the default definition of + * mbedtls_platform_gmtime_r(), but in order to determine that, + * we need to check POSIX features, hence modify _POSIX_C_SOURCE. + * With the current approach, this declaration is orphaned, lacking + * an accompanying definition, in case mbedtls_platform_gmtime_r() + * doesn't need it, but that's not a problem. */ +extern mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex; +#endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */ + +/* + * Helper macros for mutex handling + */ +#define MBEDTLS_MUTEX_LOCK_CHECK( mutex ) \ + do \ + { \ + if( mbedtls_mutex_lock( mutex ) != 0 ) \ + return( PSA_ERROR_BAD_STATE ); \ + } while( 0 ) +#define MBEDTLS_MUTEX_UNLOCK_CHECK( mutex ) \ + do \ + { \ + if( mbedtls_mutex_unlock( mutex ) != 0 ) \ + return( PSA_ERROR_BAD_STATE ); \ + } while( 0 ) +#else/* MBEDTLS_THREADING_C */ +#define MBEDTLS_MUTEX_LOCK_CHECK( mutex ) +#define MBEDTLS_MUTEX_UNLOCK_CHECK( mutex ) +#endif +#ifdef __cplusplus +} +#endif + +#endif /* threading.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/timing.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/timing.h index 830dcee..a3d2bba 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/timing.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/timing.h @@ -1,106 +1,106 @@ -/** - * \file timing.h - * - * \brief Portable interface to timeouts and to the CPU cycle counter - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_TIMING_H -#define MBEDTLS_TIMING_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(MBEDTLS_TIMING_ALT) -// Regular implementation -// - -/** - * \brief timer structure - */ -struct mbedtls_timing_hr_time { - uint64_t MBEDTLS_PRIVATE(opaque)[4]; -}; - -/** - * \brief Context for mbedtls_timing_set/get_delay() - */ -typedef struct mbedtls_timing_delay_context { - struct mbedtls_timing_hr_time MBEDTLS_PRIVATE(timer); - uint32_t MBEDTLS_PRIVATE(int_ms); - uint32_t MBEDTLS_PRIVATE(fin_ms); -} mbedtls_timing_delay_context; - -#else /* MBEDTLS_TIMING_ALT */ -#include "timing_alt.h" -#endif /* MBEDTLS_TIMING_ALT */ - -/* Internal use */ -unsigned long mbedtls_timing_get_timer(struct mbedtls_timing_hr_time *val, int reset); - -/** - * \brief Set a pair of delays to watch - * (See \c mbedtls_timing_get_delay().) - * - * \param data Pointer to timing data. - * Must point to a valid \c mbedtls_timing_delay_context struct. - * \param int_ms First (intermediate) delay in milliseconds. - * The effect if int_ms > fin_ms is unspecified. - * \param fin_ms Second (final) delay in milliseconds. - * Pass 0 to cancel the current delay. - * - * \note To set a single delay, either use \c mbedtls_timing_set_timer - * directly or use this function with int_ms == fin_ms. - */ -void mbedtls_timing_set_delay(void *data, uint32_t int_ms, uint32_t fin_ms); - -/** - * \brief Get the status of delays - * (Memory helper: number of delays passed.) - * - * \param data Pointer to timing data - * Must point to a valid \c mbedtls_timing_delay_context struct. - * - * \return -1 if cancelled (fin_ms = 0), - * 0 if none of the delays are passed, - * 1 if only the intermediate delay is passed, - * 2 if the final delay is passed. - */ -int mbedtls_timing_get_delay(void *data); - -/** - * \brief Get the final timing delay - * - * \param data Pointer to timing data - * Must point to a valid \c mbedtls_timing_delay_context struct. - * - * \return Final timing delay in milliseconds. - */ -uint32_t mbedtls_timing_get_final_delay( - const mbedtls_timing_delay_context *data); - -#ifdef __cplusplus -} -#endif - -#endif /* timing.h */ +/** + * \file timing.h + * + * \brief Portable interface to timeouts and to the CPU cycle counter + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_TIMING_H +#define MBEDTLS_TIMING_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_TIMING_ALT) +// Regular implementation +// + +/** + * \brief timer structure + */ +struct mbedtls_timing_hr_time { + uint64_t MBEDTLS_PRIVATE(opaque)[4]; +}; + +/** + * \brief Context for mbedtls_timing_set/get_delay() + */ +typedef struct mbedtls_timing_delay_context { + struct mbedtls_timing_hr_time MBEDTLS_PRIVATE(timer); + uint32_t MBEDTLS_PRIVATE(int_ms); + uint32_t MBEDTLS_PRIVATE(fin_ms); +} mbedtls_timing_delay_context; + +#else /* MBEDTLS_TIMING_ALT */ +#include "timing_alt.h" +#endif /* MBEDTLS_TIMING_ALT */ + +/* Internal use */ +unsigned long mbedtls_timing_get_timer(struct mbedtls_timing_hr_time *val, int reset); + +/** + * \brief Set a pair of delays to watch + * (See \c mbedtls_timing_get_delay().) + * + * \param data Pointer to timing data. + * Must point to a valid \c mbedtls_timing_delay_context struct. + * \param int_ms First (intermediate) delay in milliseconds. + * The effect if int_ms > fin_ms is unspecified. + * \param fin_ms Second (final) delay in milliseconds. + * Pass 0 to cancel the current delay. + * + * \note To set a single delay, either use \c mbedtls_timing_set_timer + * directly or use this function with int_ms == fin_ms. + */ +void mbedtls_timing_set_delay(void *data, uint32_t int_ms, uint32_t fin_ms); + +/** + * \brief Get the status of delays + * (Memory helper: number of delays passed.) + * + * \param data Pointer to timing data + * Must point to a valid \c mbedtls_timing_delay_context struct. + * + * \return -1 if cancelled (fin_ms = 0), + * 0 if none of the delays are passed, + * 1 if only the intermediate delay is passed, + * 2 if the final delay is passed. + */ +int mbedtls_timing_get_delay(void *data); + +/** + * \brief Get the final timing delay + * + * \param data Pointer to timing data + * Must point to a valid \c mbedtls_timing_delay_context struct. + * + * \return Final timing delay in milliseconds. + */ +uint32_t mbedtls_timing_get_final_delay( + const mbedtls_timing_delay_context *data); + +#ifdef __cplusplus +} +#endif + +#endif /* timing.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/version.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/version.h index 073211a..4088962 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/version.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/version.h @@ -1,90 +1,90 @@ -/** - * \file version.h - * - * \brief Run-time version information - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * This set of run-time variables can be used to determine the version number of - * the Mbed TLS library used. Compile-time version defines for the same can be - * found in build_info.h - */ -#ifndef MBEDTLS_VERSION_H -#define MBEDTLS_VERSION_H - -#include "mbedtls/build_info.h" - -#if defined(MBEDTLS_VERSION_C) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Get the version number. - * - * \return The constructed version number in the format - * MMNNPP00 (Major, Minor, Patch). - */ -unsigned int mbedtls_version_get_number(void); - -/** - * Get the version string ("x.y.z"). - * - * \param string The string that will receive the value. - * (Should be at least 9 bytes in size) - */ -void mbedtls_version_get_string(char *string); - -/** - * Get the full version string ("Mbed TLS x.y.z"). - * - * \param string The string that will receive the value. The Mbed TLS version - * string will use 18 bytes AT MOST including a terminating - * null byte. - * (So the buffer should be at least 18 bytes to receive this - * version string). - */ -void mbedtls_version_get_string_full(char *string); - -/** - * \brief Check if support for a feature was compiled into this - * Mbed TLS binary. This allows you to see at runtime if the - * library was for instance compiled with or without - * Multi-threading support. - * - * \note only checks against defines in the sections "System - * support", "Mbed TLS modules" and "Mbed TLS feature - * support" in mbedtls_config.h - * - * \param feature The string for the define to check (e.g. "MBEDTLS_AES_C") - * - * \return 0 if the feature is present, - * -1 if the feature is not present and - * -2 if support for feature checking as a whole was not - * compiled in. - */ -int mbedtls_version_check_feature(const char *feature); - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_VERSION_C */ - -#endif /* version.h */ +/** + * \file version.h + * + * \brief Run-time version information + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This set of run-time variables can be used to determine the version number of + * the Mbed TLS library used. Compile-time version defines for the same can be + * found in build_info.h + */ +#ifndef MBEDTLS_VERSION_H +#define MBEDTLS_VERSION_H + +#include "mbedtls/build_info.h" + +#if defined(MBEDTLS_VERSION_C) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Get the version number. + * + * \return The constructed version number in the format + * MMNNPP00 (Major, Minor, Patch). + */ +unsigned int mbedtls_version_get_number(void); + +/** + * Get the version string ("x.y.z"). + * + * \param string The string that will receive the value. + * (Should be at least 9 bytes in size) + */ +void mbedtls_version_get_string(char *string); + +/** + * Get the full version string ("Mbed TLS x.y.z"). + * + * \param string The string that will receive the value. The Mbed TLS version + * string will use 18 bytes AT MOST including a terminating + * null byte. + * (So the buffer should be at least 18 bytes to receive this + * version string). + */ +void mbedtls_version_get_string_full(char *string); + +/** + * \brief Check if support for a feature was compiled into this + * Mbed TLS binary. This allows you to see at runtime if the + * library was for instance compiled with or without + * Multi-threading support. + * + * \note only checks against defines in the sections "System + * support", "Mbed TLS modules" and "Mbed TLS feature + * support" in mbedtls_config.h + * + * \param feature The string for the define to check (e.g. "MBEDTLS_AES_C") + * + * \return 0 if the feature is present, + * -1 if the feature is not present and + * -2 if support for feature checking as a whole was not + * compiled in. + */ +int mbedtls_version_check_feature(const char *feature); + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_VERSION_C */ + +#endif /* version.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509.h index a9267c7..d389584 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509.h @@ -1,562 +1,562 @@ -/** - * \file x509.h - * - * \brief X.509 generic defines and structures - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_X509_H -#define MBEDTLS_X509_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/asn1.h" -#include "mbedtls/pk.h" - -#if defined(MBEDTLS_RSA_C) -#include "mbedtls/rsa.h" -#endif - -/** - * \addtogroup x509_module - * \{ - */ - -#if !defined(MBEDTLS_X509_MAX_INTERMEDIATE_CA) -/** - * Maximum number of intermediate CAs in a verification chain. - * That is, maximum length of the chain, excluding the end-entity certificate - * and the trusted root certificate. - * - * Set this to a low value to prevent an adversary from making you waste - * resources verifying an overlong certificate chain. - */ -#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 -#endif - -/** - * \name X509 Error codes - * \{ - */ -/** Unavailable feature, e.g. RSA hashing/encryption combination. */ -#define MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE -0x2080 -/** Requested OID is unknown. */ -#define MBEDTLS_ERR_X509_UNKNOWN_OID -0x2100 -/** The CRT/CRL/CSR format is invalid, e.g. different type expected. */ -#define MBEDTLS_ERR_X509_INVALID_FORMAT -0x2180 -/** The CRT/CRL/CSR version element is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_VERSION -0x2200 -/** The serial tag or value is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_SERIAL -0x2280 -/** The algorithm tag or value is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_ALG -0x2300 -/** The name tag or value is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_NAME -0x2380 -/** The date tag or value is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_DATE -0x2400 -/** The signature tag or value invalid. */ -#define MBEDTLS_ERR_X509_INVALID_SIGNATURE -0x2480 -/** The extension tag or value is invalid. */ -#define MBEDTLS_ERR_X509_INVALID_EXTENSIONS -0x2500 -/** CRT/CRL/CSR has an unsupported version number. */ -#define MBEDTLS_ERR_X509_UNKNOWN_VERSION -0x2580 -/** Signature algorithm (oid) is unsupported. */ -#define MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG -0x2600 -/** Signature algorithms do not match. (see \c ::mbedtls_x509_crt sig_oid) */ -#define MBEDTLS_ERR_X509_SIG_MISMATCH -0x2680 -/** Certificate verification failed, e.g. CRL, CA or signature check failed. */ -#define MBEDTLS_ERR_X509_CERT_VERIFY_FAILED -0x2700 -/** Format not recognized as DER or PEM. */ -#define MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT -0x2780 -/** Input invalid. */ -#define MBEDTLS_ERR_X509_BAD_INPUT_DATA -0x2800 -/** Allocation of memory failed. */ -#define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 -/** Read/write of file failed. */ -#define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 -/** Destination buffer is too small. */ -#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 -/** A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ -#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 -/** \} name X509 Error codes */ - -/** - * \name X509 Verify codes - * \{ - */ -/* Reminder: update x509_crt_verify_strings[] in library/x509_crt.c */ -#define MBEDTLS_X509_BADCERT_EXPIRED 0x01 /**< The certificate validity has expired. */ -#define MBEDTLS_X509_BADCERT_REVOKED 0x02 /**< The certificate has been revoked (is on a CRL). */ -#define MBEDTLS_X509_BADCERT_CN_MISMATCH 0x04 /**< The certificate Common Name (CN) does not match with the expected CN. */ -#define MBEDTLS_X509_BADCERT_NOT_TRUSTED 0x08 /**< The certificate is not correctly signed by the trusted CA. */ -#define MBEDTLS_X509_BADCRL_NOT_TRUSTED 0x10 /**< The CRL is not correctly signed by the trusted CA. */ -#define MBEDTLS_X509_BADCRL_EXPIRED 0x20 /**< The CRL is expired. */ -#define MBEDTLS_X509_BADCERT_MISSING 0x40 /**< Certificate was missing. */ -#define MBEDTLS_X509_BADCERT_SKIP_VERIFY 0x80 /**< Certificate verification was skipped. */ -#define MBEDTLS_X509_BADCERT_OTHER 0x0100 /**< Other reason (can be used by verify callback) */ -#define MBEDTLS_X509_BADCERT_FUTURE 0x0200 /**< The certificate validity starts in the future. */ -#define MBEDTLS_X509_BADCRL_FUTURE 0x0400 /**< The CRL is from the future */ -#define MBEDTLS_X509_BADCERT_KEY_USAGE 0x0800 /**< Usage does not match the keyUsage extension. */ -#define MBEDTLS_X509_BADCERT_EXT_KEY_USAGE 0x1000 /**< Usage does not match the extendedKeyUsage extension. */ -#define MBEDTLS_X509_BADCERT_NS_CERT_TYPE 0x2000 /**< Usage does not match the nsCertType extension. */ -#define MBEDTLS_X509_BADCERT_BAD_MD 0x4000 /**< The certificate is signed with an unacceptable hash. */ -#define MBEDTLS_X509_BADCERT_BAD_PK 0x8000 /**< The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ -#define MBEDTLS_X509_BADCERT_BAD_KEY 0x010000 /**< The certificate is signed with an unacceptable key (eg bad curve, RSA too short). */ -#define MBEDTLS_X509_BADCRL_BAD_MD 0x020000 /**< The CRL is signed with an unacceptable hash. */ -#define MBEDTLS_X509_BADCRL_BAD_PK 0x040000 /**< The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ -#define MBEDTLS_X509_BADCRL_BAD_KEY 0x080000 /**< The CRL is signed with an unacceptable key (eg bad curve, RSA too short). */ - -/** \} name X509 Verify codes */ -/** \} addtogroup x509_module */ - -/* - * X.509 v3 Subject Alternative Name types. - * otherName [0] OtherName, - * rfc822Name [1] IA5String, - * dNSName [2] IA5String, - * x400Address [3] ORAddress, - * directoryName [4] Name, - * ediPartyName [5] EDIPartyName, - * uniformResourceIdentifier [6] IA5String, - * iPAddress [7] OCTET STRING, - * registeredID [8] OBJECT IDENTIFIER - */ -#define MBEDTLS_X509_SAN_OTHER_NAME 0 -#define MBEDTLS_X509_SAN_RFC822_NAME 1 -#define MBEDTLS_X509_SAN_DNS_NAME 2 -#define MBEDTLS_X509_SAN_X400_ADDRESS_NAME 3 -#define MBEDTLS_X509_SAN_DIRECTORY_NAME 4 -#define MBEDTLS_X509_SAN_EDI_PARTY_NAME 5 -#define MBEDTLS_X509_SAN_UNIFORM_RESOURCE_IDENTIFIER 6 -#define MBEDTLS_X509_SAN_IP_ADDRESS 7 -#define MBEDTLS_X509_SAN_REGISTERED_ID 8 - -/* - * X.509 v3 Key Usage Extension flags - * Reminder: update mbedtls_x509_info_key_usage() when adding new flags. - */ -#define MBEDTLS_X509_KU_DIGITAL_SIGNATURE (0x80) /* bit 0 */ -#define MBEDTLS_X509_KU_NON_REPUDIATION (0x40) /* bit 1 */ -#define MBEDTLS_X509_KU_KEY_ENCIPHERMENT (0x20) /* bit 2 */ -#define MBEDTLS_X509_KU_DATA_ENCIPHERMENT (0x10) /* bit 3 */ -#define MBEDTLS_X509_KU_KEY_AGREEMENT (0x08) /* bit 4 */ -#define MBEDTLS_X509_KU_KEY_CERT_SIGN (0x04) /* bit 5 */ -#define MBEDTLS_X509_KU_CRL_SIGN (0x02) /* bit 6 */ -#define MBEDTLS_X509_KU_ENCIPHER_ONLY (0x01) /* bit 7 */ -#define MBEDTLS_X509_KU_DECIPHER_ONLY (0x8000) /* bit 8 */ - -/* - * Netscape certificate types - * (http://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html) - */ - -#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT (0x80) /* bit 0 */ -#define MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER (0x40) /* bit 1 */ -#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL (0x20) /* bit 2 */ -#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING (0x10) /* bit 3 */ -#define MBEDTLS_X509_NS_CERT_TYPE_RESERVED (0x08) /* bit 4 */ -#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CA (0x04) /* bit 5 */ -#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA (0x02) /* bit 6 */ -#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA (0x01) /* bit 7 */ - -/* - * X.509 extension types - * - * Comments refer to the status for using certificates. Status can be - * different for writing certificates or reading CRLs or CSRs. - * - * Those are defined in oid.h as oid.c needs them in a data structure. Since - * these were previously defined here, let's have aliases for compatibility. - */ -#define MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_X509_EXT_AUTHORITY_KEY_IDENTIFIER -#define MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_X509_EXT_SUBJECT_KEY_IDENTIFIER -#define MBEDTLS_X509_EXT_KEY_USAGE MBEDTLS_OID_X509_EXT_KEY_USAGE -#define MBEDTLS_X509_EXT_CERTIFICATE_POLICIES MBEDTLS_OID_X509_EXT_CERTIFICATE_POLICIES -#define MBEDTLS_X509_EXT_POLICY_MAPPINGS MBEDTLS_OID_X509_EXT_POLICY_MAPPINGS -#define MBEDTLS_X509_EXT_SUBJECT_ALT_NAME MBEDTLS_OID_X509_EXT_SUBJECT_ALT_NAME /* Supported (DNS) */ -#define MBEDTLS_X509_EXT_ISSUER_ALT_NAME MBEDTLS_OID_X509_EXT_ISSUER_ALT_NAME -#define MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_X509_EXT_SUBJECT_DIRECTORY_ATTRS -#define MBEDTLS_X509_EXT_BASIC_CONSTRAINTS MBEDTLS_OID_X509_EXT_BASIC_CONSTRAINTS /* Supported */ -#define MBEDTLS_X509_EXT_NAME_CONSTRAINTS MBEDTLS_OID_X509_EXT_NAME_CONSTRAINTS -#define MBEDTLS_X509_EXT_POLICY_CONSTRAINTS MBEDTLS_OID_X509_EXT_POLICY_CONSTRAINTS -#define MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE MBEDTLS_OID_X509_EXT_EXTENDED_KEY_USAGE -#define MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_X509_EXT_CRL_DISTRIBUTION_POINTS -#define MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY MBEDTLS_OID_X509_EXT_INIHIBIT_ANYPOLICY -#define MBEDTLS_X509_EXT_FRESHEST_CRL MBEDTLS_OID_X509_EXT_FRESHEST_CRL -#define MBEDTLS_X509_EXT_NS_CERT_TYPE MBEDTLS_OID_X509_EXT_NS_CERT_TYPE - -/* - * Storage format identifiers - * Recognized formats: PEM and DER - */ -#define MBEDTLS_X509_FORMAT_DER 1 -#define MBEDTLS_X509_FORMAT_PEM 2 - -#define MBEDTLS_X509_MAX_DN_NAME_SIZE 256 /**< Maximum value size of a DN entry */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup x509_module - * \{ */ - -/** - * \name Structures for parsing X.509 certificates, CRLs and CSRs - * \{ - */ - -/** - * Type-length-value structure that allows for ASN1 using DER. - */ -typedef mbedtls_asn1_buf mbedtls_x509_buf; - -/** - * Container for ASN1 bit strings. - */ -typedef mbedtls_asn1_bitstring mbedtls_x509_bitstring; - -/** - * Container for ASN1 named information objects. - * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.). - */ -typedef mbedtls_asn1_named_data mbedtls_x509_name; - -/** - * Container for a sequence of ASN.1 items - */ -typedef mbedtls_asn1_sequence mbedtls_x509_sequence; - -/* - * Container for the fields of the Authority Key Identifier object - */ -typedef struct mbedtls_x509_authority { - mbedtls_x509_buf keyIdentifier; - mbedtls_x509_sequence authorityCertIssuer; - mbedtls_x509_buf authorityCertSerialNumber; - mbedtls_x509_buf raw; -} -mbedtls_x509_authority; - -/** Container for date and time (precision in seconds). */ -typedef struct mbedtls_x509_time { - int year, mon, day; /**< Date. */ - int hour, min, sec; /**< Time. */ -} -mbedtls_x509_time; - -/** - * From RFC 5280 section 4.2.1.6: - * OtherName ::= SEQUENCE { - * type-id OBJECT IDENTIFIER, - * value [0] EXPLICIT ANY DEFINED BY type-id } - * - * Future versions of the library may add new fields to this structure or - * to its embedded union and structure. - */ -typedef struct mbedtls_x509_san_other_name { - /** - * The type_id is an OID as defined in RFC 5280. - * To check the value of the type id, you should use - * \p MBEDTLS_OID_CMP with a known OID mbedtls_x509_buf. - */ - mbedtls_x509_buf type_id; /**< The type id. */ - union { - /** - * From RFC 4108 section 5: - * HardwareModuleName ::= SEQUENCE { - * hwType OBJECT IDENTIFIER, - * hwSerialNum OCTET STRING } - */ - struct { - mbedtls_x509_buf oid; /**< The object identifier. */ - mbedtls_x509_buf val; /**< The named value. */ - } - hardware_module_name; - } - value; -} -mbedtls_x509_san_other_name; - -/** - * A structure for holding the parsed Subject Alternative Name, - * according to type. - * - * Future versions of the library may add new fields to this structure or - * to its embedded union and structure. - */ -typedef struct mbedtls_x509_subject_alternative_name { - int type; /**< The SAN type, value of MBEDTLS_X509_SAN_XXX. */ - union { - mbedtls_x509_san_other_name other_name; - mbedtls_x509_name directory_name; - mbedtls_x509_buf unstructured_name; /**< The buffer for the unstructured types. rfc822Name, dnsName and uniformResourceIdentifier are currently supported. */ - } - san; /**< A union of the supported SAN types */ -} -mbedtls_x509_subject_alternative_name; - -typedef struct mbedtls_x509_san_list { - mbedtls_x509_subject_alternative_name node; - struct mbedtls_x509_san_list *next; -} -mbedtls_x509_san_list; - -/** \} name Structures for parsing X.509 certificates, CRLs and CSRs */ - -/** - * \brief Store the certificate DN in printable form into buf; - * no more than size characters will be written. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param dn The X509 name to represent - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_dn_gets(char *buf, size_t size, const mbedtls_x509_name *dn); - -/** - * \brief Return the next relative DN in an X509 name. - * - * \note Intended use is to compare function result to dn->next - * in order to detect boundaries of multi-valued RDNs. - * - * \param dn Current node in the X509 name - * - * \return Pointer to the first attribute-value pair of the - * next RDN in sequence, or NULL if end is reached. - */ -static inline mbedtls_x509_name *mbedtls_x509_dn_get_next( - mbedtls_x509_name *dn) -{ - while (dn->MBEDTLS_PRIVATE(next_merged) && dn->next != NULL) { - dn = dn->next; - } - return dn->next; -} - -/** - * \brief Store the certificate serial in printable form into buf; - * no more than size characters will be written. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param serial The X509 serial to represent - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_serial_gets(char *buf, size_t size, const mbedtls_x509_buf *serial); - -/** - * \brief Compare pair of mbedtls_x509_time. - * - * \param t1 mbedtls_x509_time to compare - * \param t2 mbedtls_x509_time to compare - * - * \return < 0 if t1 is before t2 - * 0 if t1 equals t2 - * > 0 if t1 is after t2 - */ -int mbedtls_x509_time_cmp(const mbedtls_x509_time *t1, const mbedtls_x509_time *t2); - -#if defined(MBEDTLS_HAVE_TIME_DATE) -/** - * \brief Fill mbedtls_x509_time with provided mbedtls_time_t. - * - * \param tt mbedtls_time_t to convert - * \param now mbedtls_x509_time to fill with converted mbedtls_time_t - * - * \return \c 0 on success - * \return A non-zero return value on failure. - */ -int mbedtls_x509_time_gmtime(mbedtls_time_t tt, mbedtls_x509_time *now); -#endif /* MBEDTLS_HAVE_TIME_DATE */ - -/** - * \brief Check a given mbedtls_x509_time against the system time - * and tell if it's in the past. - * - * \note Intended usage is "if( is_past( valid_to ) ) ERROR". - * Hence the return value of 1 if on internal errors. - * - * \param to mbedtls_x509_time to check - * - * \return 1 if the given time is in the past or an error occurred, - * 0 otherwise. - */ -int mbedtls_x509_time_is_past(const mbedtls_x509_time *to); - -/** - * \brief Check a given mbedtls_x509_time against the system time - * and tell if it's in the future. - * - * \note Intended usage is "if( is_future( valid_from ) ) ERROR". - * Hence the return value of 1 if on internal errors. - * - * \param from mbedtls_x509_time to check - * - * \return 1 if the given time is in the future or an error occurred, - * 0 otherwise. - */ -int mbedtls_x509_time_is_future(const mbedtls_x509_time *from); - -/** - * \brief This function parses an item in the SubjectAlternativeNames - * extension. Please note that this function might allocate - * additional memory for a subject alternative name, thus - * mbedtls_x509_free_subject_alt_name has to be called - * to dispose of this additional memory afterwards. - * - * \param san_buf The buffer holding the raw data item of the subject - * alternative name. - * \param san The target structure to populate with the parsed presentation - * of the subject alternative name encoded in \p san_buf. - * - * \note Supported GeneralName types, as defined in RFC 5280: - * "rfc822Name", "dnsName", "directoryName", - * "uniformResourceIdentifier" and "hardware_module_name" - * of type "otherName", as defined in RFC 4108. - * - * \note This function should be called on a single raw data of - * subject alternative name. For example, after successful - * certificate parsing, one must iterate on every item in the - * \c crt->subject_alt_names sequence, and pass it to - * this function. - * - * \warning The target structure contains pointers to the raw data of the - * parsed certificate, and its lifetime is restricted by the - * lifetime of the certificate. - * - * \return \c 0 on success - * \return #MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE for an unsupported - * SAN type. - * \return Another negative value for any other failure. - */ -int mbedtls_x509_parse_subject_alt_name(const mbedtls_x509_buf *san_buf, - mbedtls_x509_subject_alternative_name *san); -/** - * \brief Unallocate all data related to subject alternative name - * - * \param san SAN structure - extra memory owned by this structure will be freed - */ -void mbedtls_x509_free_subject_alt_name(mbedtls_x509_subject_alternative_name *san); - -/** \} addtogroup x509_module */ - -/* - * Internal module functions. You probably do not want to use these unless you - * know you do. - */ -int mbedtls_x509_get_name(unsigned char **p, const unsigned char *end, - mbedtls_x509_name *cur); -int mbedtls_x509_get_alg_null(unsigned char **p, const unsigned char *end, - mbedtls_x509_buf *alg); -int mbedtls_x509_get_alg(unsigned char **p, const unsigned char *end, - mbedtls_x509_buf *alg, mbedtls_x509_buf *params); -#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) -int mbedtls_x509_get_rsassa_pss_params(const mbedtls_x509_buf *params, - mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md, - int *salt_len); -#endif -int mbedtls_x509_get_sig(unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig); -int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params, - mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg, - void **sig_opts); -int mbedtls_x509_get_time(unsigned char **p, const unsigned char *end, - mbedtls_x509_time *t); -int mbedtls_x509_get_serial(unsigned char **p, const unsigned char *end, - mbedtls_x509_buf *serial); -int mbedtls_x509_get_ext(unsigned char **p, const unsigned char *end, - mbedtls_x509_buf *ext, int tag); -#if !defined(MBEDTLS_X509_REMOVE_INFO) -int mbedtls_x509_sig_alg_gets(char *buf, size_t size, const mbedtls_x509_buf *sig_oid, - mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, - const void *sig_opts); -#endif -int mbedtls_x509_key_size_helper(char *buf, size_t buf_size, const char *name); -int mbedtls_x509_string_to_names(mbedtls_asn1_named_data **head, const char *name); -int mbedtls_x509_set_extension(mbedtls_asn1_named_data **head, const char *oid, size_t oid_len, - int critical, const unsigned char *val, - size_t val_len); -int mbedtls_x509_write_extensions(unsigned char **p, unsigned char *start, - mbedtls_asn1_named_data *first); -int mbedtls_x509_write_names(unsigned char **p, unsigned char *start, - mbedtls_asn1_named_data *first); -int mbedtls_x509_write_sig(unsigned char **p, unsigned char *start, - const char *oid, size_t oid_len, - unsigned char *sig, size_t size, - mbedtls_pk_type_t pk_alg); -int mbedtls_x509_get_ns_cert_type(unsigned char **p, - const unsigned char *end, - unsigned char *ns_cert_type); -int mbedtls_x509_get_key_usage(unsigned char **p, - const unsigned char *end, - unsigned int *key_usage); -int mbedtls_x509_get_subject_alt_name(unsigned char **p, - const unsigned char *end, - mbedtls_x509_sequence *subject_alt_name); -int mbedtls_x509_get_subject_alt_name_ext(unsigned char **p, - const unsigned char *end, - mbedtls_x509_sequence *subject_alt_name); -int mbedtls_x509_info_subject_alt_name(char **buf, size_t *size, - const mbedtls_x509_sequence - *subject_alt_name, - const char *prefix); -int mbedtls_x509_info_cert_type(char **buf, size_t *size, - unsigned char ns_cert_type); -int mbedtls_x509_info_key_usage(char **buf, size_t *size, - unsigned int key_usage); - -int mbedtls_x509_write_set_san_common(mbedtls_asn1_named_data **extensions, - const mbedtls_x509_san_list *san_list); - -/** - * \brief This function parses a CN string as an IP address. - * - * \param cn The CN string to parse. CN string MUST be null-terminated. - * \param dst The target buffer to populate with the binary IP address. - * The buffer MUST be 16 bytes to save IPv6, and should be - * 4-byte aligned if the result will be used as struct in_addr. - * e.g. uint32_t dst[4] - * - * \note \p cn is parsed as an IPv6 address if string contains ':', - * else \p cn is parsed as an IPv4 address. - * - * \return Length of binary IP address; num bytes written to target. - * \return \c 0 on failure to parse CN string as an IP address. - */ -size_t mbedtls_x509_crt_parse_cn_inet_pton(const char *cn, void *dst); - -#define MBEDTLS_X509_SAFE_SNPRINTF \ - do { \ - if (ret < 0 || (size_t) ret >= n) \ - return MBEDTLS_ERR_X509_BUFFER_TOO_SMALL; \ - \ - n -= (size_t) ret; \ - p += (size_t) ret; \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* x509.h */ +/** + * \file x509.h + * + * \brief X.509 generic defines and structures + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_X509_H +#define MBEDTLS_X509_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/asn1.h" +#include "mbedtls/pk.h" + +#if defined(MBEDTLS_RSA_C) +#include "mbedtls/rsa.h" +#endif + +/** + * \addtogroup x509_module + * \{ + */ + +#if !defined(MBEDTLS_X509_MAX_INTERMEDIATE_CA) +/** + * Maximum number of intermediate CAs in a verification chain. + * That is, maximum length of the chain, excluding the end-entity certificate + * and the trusted root certificate. + * + * Set this to a low value to prevent an adversary from making you waste + * resources verifying an overlong certificate chain. + */ +#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 +#endif + +/** + * \name X509 Error codes + * \{ + */ +/** Unavailable feature, e.g. RSA hashing/encryption combination. */ +#define MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE -0x2080 +/** Requested OID is unknown. */ +#define MBEDTLS_ERR_X509_UNKNOWN_OID -0x2100 +/** The CRT/CRL/CSR format is invalid, e.g. different type expected. */ +#define MBEDTLS_ERR_X509_INVALID_FORMAT -0x2180 +/** The CRT/CRL/CSR version element is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_VERSION -0x2200 +/** The serial tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_SERIAL -0x2280 +/** The algorithm tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_ALG -0x2300 +/** The name tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_NAME -0x2380 +/** The date tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_DATE -0x2400 +/** The signature tag or value invalid. */ +#define MBEDTLS_ERR_X509_INVALID_SIGNATURE -0x2480 +/** The extension tag or value is invalid. */ +#define MBEDTLS_ERR_X509_INVALID_EXTENSIONS -0x2500 +/** CRT/CRL/CSR has an unsupported version number. */ +#define MBEDTLS_ERR_X509_UNKNOWN_VERSION -0x2580 +/** Signature algorithm (oid) is unsupported. */ +#define MBEDTLS_ERR_X509_UNKNOWN_SIG_ALG -0x2600 +/** Signature algorithms do not match. (see \c ::mbedtls_x509_crt sig_oid) */ +#define MBEDTLS_ERR_X509_SIG_MISMATCH -0x2680 +/** Certificate verification failed, e.g. CRL, CA or signature check failed. */ +#define MBEDTLS_ERR_X509_CERT_VERIFY_FAILED -0x2700 +/** Format not recognized as DER or PEM. */ +#define MBEDTLS_ERR_X509_CERT_UNKNOWN_FORMAT -0x2780 +/** Input invalid. */ +#define MBEDTLS_ERR_X509_BAD_INPUT_DATA -0x2800 +/** Allocation of memory failed. */ +#define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 +/** Read/write of file failed. */ +#define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 +/** Destination buffer is too small. */ +#define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 +/** A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ +#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 +/** \} name X509 Error codes */ + +/** + * \name X509 Verify codes + * \{ + */ +/* Reminder: update x509_crt_verify_strings[] in library/x509_crt.c */ +#define MBEDTLS_X509_BADCERT_EXPIRED 0x01 /**< The certificate validity has expired. */ +#define MBEDTLS_X509_BADCERT_REVOKED 0x02 /**< The certificate has been revoked (is on a CRL). */ +#define MBEDTLS_X509_BADCERT_CN_MISMATCH 0x04 /**< The certificate Common Name (CN) does not match with the expected CN. */ +#define MBEDTLS_X509_BADCERT_NOT_TRUSTED 0x08 /**< The certificate is not correctly signed by the trusted CA. */ +#define MBEDTLS_X509_BADCRL_NOT_TRUSTED 0x10 /**< The CRL is not correctly signed by the trusted CA. */ +#define MBEDTLS_X509_BADCRL_EXPIRED 0x20 /**< The CRL is expired. */ +#define MBEDTLS_X509_BADCERT_MISSING 0x40 /**< Certificate was missing. */ +#define MBEDTLS_X509_BADCERT_SKIP_VERIFY 0x80 /**< Certificate verification was skipped. */ +#define MBEDTLS_X509_BADCERT_OTHER 0x0100 /**< Other reason (can be used by verify callback) */ +#define MBEDTLS_X509_BADCERT_FUTURE 0x0200 /**< The certificate validity starts in the future. */ +#define MBEDTLS_X509_BADCRL_FUTURE 0x0400 /**< The CRL is from the future */ +#define MBEDTLS_X509_BADCERT_KEY_USAGE 0x0800 /**< Usage does not match the keyUsage extension. */ +#define MBEDTLS_X509_BADCERT_EXT_KEY_USAGE 0x1000 /**< Usage does not match the extendedKeyUsage extension. */ +#define MBEDTLS_X509_BADCERT_NS_CERT_TYPE 0x2000 /**< Usage does not match the nsCertType extension. */ +#define MBEDTLS_X509_BADCERT_BAD_MD 0x4000 /**< The certificate is signed with an unacceptable hash. */ +#define MBEDTLS_X509_BADCERT_BAD_PK 0x8000 /**< The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ +#define MBEDTLS_X509_BADCERT_BAD_KEY 0x010000 /**< The certificate is signed with an unacceptable key (eg bad curve, RSA too short). */ +#define MBEDTLS_X509_BADCRL_BAD_MD 0x020000 /**< The CRL is signed with an unacceptable hash. */ +#define MBEDTLS_X509_BADCRL_BAD_PK 0x040000 /**< The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA). */ +#define MBEDTLS_X509_BADCRL_BAD_KEY 0x080000 /**< The CRL is signed with an unacceptable key (eg bad curve, RSA too short). */ + +/** \} name X509 Verify codes */ +/** \} addtogroup x509_module */ + +/* + * X.509 v3 Subject Alternative Name types. + * otherName [0] OtherName, + * rfc822Name [1] IA5String, + * dNSName [2] IA5String, + * x400Address [3] ORAddress, + * directoryName [4] Name, + * ediPartyName [5] EDIPartyName, + * uniformResourceIdentifier [6] IA5String, + * iPAddress [7] OCTET STRING, + * registeredID [8] OBJECT IDENTIFIER + */ +#define MBEDTLS_X509_SAN_OTHER_NAME 0 +#define MBEDTLS_X509_SAN_RFC822_NAME 1 +#define MBEDTLS_X509_SAN_DNS_NAME 2 +#define MBEDTLS_X509_SAN_X400_ADDRESS_NAME 3 +#define MBEDTLS_X509_SAN_DIRECTORY_NAME 4 +#define MBEDTLS_X509_SAN_EDI_PARTY_NAME 5 +#define MBEDTLS_X509_SAN_UNIFORM_RESOURCE_IDENTIFIER 6 +#define MBEDTLS_X509_SAN_IP_ADDRESS 7 +#define MBEDTLS_X509_SAN_REGISTERED_ID 8 + +/* + * X.509 v3 Key Usage Extension flags + * Reminder: update mbedtls_x509_info_key_usage() when adding new flags. + */ +#define MBEDTLS_X509_KU_DIGITAL_SIGNATURE (0x80) /* bit 0 */ +#define MBEDTLS_X509_KU_NON_REPUDIATION (0x40) /* bit 1 */ +#define MBEDTLS_X509_KU_KEY_ENCIPHERMENT (0x20) /* bit 2 */ +#define MBEDTLS_X509_KU_DATA_ENCIPHERMENT (0x10) /* bit 3 */ +#define MBEDTLS_X509_KU_KEY_AGREEMENT (0x08) /* bit 4 */ +#define MBEDTLS_X509_KU_KEY_CERT_SIGN (0x04) /* bit 5 */ +#define MBEDTLS_X509_KU_CRL_SIGN (0x02) /* bit 6 */ +#define MBEDTLS_X509_KU_ENCIPHER_ONLY (0x01) /* bit 7 */ +#define MBEDTLS_X509_KU_DECIPHER_ONLY (0x8000) /* bit 8 */ + +/* + * Netscape certificate types + * (http://www.mozilla.org/projects/security/pki/nss/tech-notes/tn3.html) + */ + +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT (0x80) /* bit 0 */ +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_SERVER (0x40) /* bit 1 */ +#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL (0x20) /* bit 2 */ +#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING (0x10) /* bit 3 */ +#define MBEDTLS_X509_NS_CERT_TYPE_RESERVED (0x08) /* bit 4 */ +#define MBEDTLS_X509_NS_CERT_TYPE_SSL_CA (0x04) /* bit 5 */ +#define MBEDTLS_X509_NS_CERT_TYPE_EMAIL_CA (0x02) /* bit 6 */ +#define MBEDTLS_X509_NS_CERT_TYPE_OBJECT_SIGNING_CA (0x01) /* bit 7 */ + +/* + * X.509 extension types + * + * Comments refer to the status for using certificates. Status can be + * different for writing certificates or reading CRLs or CSRs. + * + * Those are defined in oid.h as oid.c needs them in a data structure. Since + * these were previously defined here, let's have aliases for compatibility. + */ +#define MBEDTLS_X509_EXT_AUTHORITY_KEY_IDENTIFIER MBEDTLS_OID_X509_EXT_AUTHORITY_KEY_IDENTIFIER +#define MBEDTLS_X509_EXT_SUBJECT_KEY_IDENTIFIER MBEDTLS_OID_X509_EXT_SUBJECT_KEY_IDENTIFIER +#define MBEDTLS_X509_EXT_KEY_USAGE MBEDTLS_OID_X509_EXT_KEY_USAGE +#define MBEDTLS_X509_EXT_CERTIFICATE_POLICIES MBEDTLS_OID_X509_EXT_CERTIFICATE_POLICIES +#define MBEDTLS_X509_EXT_POLICY_MAPPINGS MBEDTLS_OID_X509_EXT_POLICY_MAPPINGS +#define MBEDTLS_X509_EXT_SUBJECT_ALT_NAME MBEDTLS_OID_X509_EXT_SUBJECT_ALT_NAME /* Supported (DNS) */ +#define MBEDTLS_X509_EXT_ISSUER_ALT_NAME MBEDTLS_OID_X509_EXT_ISSUER_ALT_NAME +#define MBEDTLS_X509_EXT_SUBJECT_DIRECTORY_ATTRS MBEDTLS_OID_X509_EXT_SUBJECT_DIRECTORY_ATTRS +#define MBEDTLS_X509_EXT_BASIC_CONSTRAINTS MBEDTLS_OID_X509_EXT_BASIC_CONSTRAINTS /* Supported */ +#define MBEDTLS_X509_EXT_NAME_CONSTRAINTS MBEDTLS_OID_X509_EXT_NAME_CONSTRAINTS +#define MBEDTLS_X509_EXT_POLICY_CONSTRAINTS MBEDTLS_OID_X509_EXT_POLICY_CONSTRAINTS +#define MBEDTLS_X509_EXT_EXTENDED_KEY_USAGE MBEDTLS_OID_X509_EXT_EXTENDED_KEY_USAGE +#define MBEDTLS_X509_EXT_CRL_DISTRIBUTION_POINTS MBEDTLS_OID_X509_EXT_CRL_DISTRIBUTION_POINTS +#define MBEDTLS_X509_EXT_INIHIBIT_ANYPOLICY MBEDTLS_OID_X509_EXT_INIHIBIT_ANYPOLICY +#define MBEDTLS_X509_EXT_FRESHEST_CRL MBEDTLS_OID_X509_EXT_FRESHEST_CRL +#define MBEDTLS_X509_EXT_NS_CERT_TYPE MBEDTLS_OID_X509_EXT_NS_CERT_TYPE + +/* + * Storage format identifiers + * Recognized formats: PEM and DER + */ +#define MBEDTLS_X509_FORMAT_DER 1 +#define MBEDTLS_X509_FORMAT_PEM 2 + +#define MBEDTLS_X509_MAX_DN_NAME_SIZE 256 /**< Maximum value size of a DN entry */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures for parsing X.509 certificates, CRLs and CSRs + * \{ + */ + +/** + * Type-length-value structure that allows for ASN1 using DER. + */ +typedef mbedtls_asn1_buf mbedtls_x509_buf; + +/** + * Container for ASN1 bit strings. + */ +typedef mbedtls_asn1_bitstring mbedtls_x509_bitstring; + +/** + * Container for ASN1 named information objects. + * It allows for Relative Distinguished Names (e.g. cn=localhost,ou=code,etc.). + */ +typedef mbedtls_asn1_named_data mbedtls_x509_name; + +/** + * Container for a sequence of ASN.1 items + */ +typedef mbedtls_asn1_sequence mbedtls_x509_sequence; + +/* + * Container for the fields of the Authority Key Identifier object + */ +typedef struct mbedtls_x509_authority { + mbedtls_x509_buf keyIdentifier; + mbedtls_x509_sequence authorityCertIssuer; + mbedtls_x509_buf authorityCertSerialNumber; + mbedtls_x509_buf raw; +} +mbedtls_x509_authority; + +/** Container for date and time (precision in seconds). */ +typedef struct mbedtls_x509_time { + int year, mon, day; /**< Date. */ + int hour, min, sec; /**< Time. */ +} +mbedtls_x509_time; + +/** + * From RFC 5280 section 4.2.1.6: + * OtherName ::= SEQUENCE { + * type-id OBJECT IDENTIFIER, + * value [0] EXPLICIT ANY DEFINED BY type-id } + * + * Future versions of the library may add new fields to this structure or + * to its embedded union and structure. + */ +typedef struct mbedtls_x509_san_other_name { + /** + * The type_id is an OID as defined in RFC 5280. + * To check the value of the type id, you should use + * \p MBEDTLS_OID_CMP with a known OID mbedtls_x509_buf. + */ + mbedtls_x509_buf type_id; /**< The type id. */ + union { + /** + * From RFC 4108 section 5: + * HardwareModuleName ::= SEQUENCE { + * hwType OBJECT IDENTIFIER, + * hwSerialNum OCTET STRING } + */ + struct { + mbedtls_x509_buf oid; /**< The object identifier. */ + mbedtls_x509_buf val; /**< The named value. */ + } + hardware_module_name; + } + value; +} +mbedtls_x509_san_other_name; + +/** + * A structure for holding the parsed Subject Alternative Name, + * according to type. + * + * Future versions of the library may add new fields to this structure or + * to its embedded union and structure. + */ +typedef struct mbedtls_x509_subject_alternative_name { + int type; /**< The SAN type, value of MBEDTLS_X509_SAN_XXX. */ + union { + mbedtls_x509_san_other_name other_name; + mbedtls_x509_name directory_name; + mbedtls_x509_buf unstructured_name; /**< The buffer for the unstructured types. rfc822Name, dnsName and uniformResourceIdentifier are currently supported. */ + } + san; /**< A union of the supported SAN types */ +} +mbedtls_x509_subject_alternative_name; + +typedef struct mbedtls_x509_san_list { + mbedtls_x509_subject_alternative_name node; + struct mbedtls_x509_san_list *next; +} +mbedtls_x509_san_list; + +/** \} name Structures for parsing X.509 certificates, CRLs and CSRs */ + +/** + * \brief Store the certificate DN in printable form into buf; + * no more than size characters will be written. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param dn The X509 name to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_dn_gets(char *buf, size_t size, const mbedtls_x509_name *dn); + +/** + * \brief Return the next relative DN in an X509 name. + * + * \note Intended use is to compare function result to dn->next + * in order to detect boundaries of multi-valued RDNs. + * + * \param dn Current node in the X509 name + * + * \return Pointer to the first attribute-value pair of the + * next RDN in sequence, or NULL if end is reached. + */ +static inline mbedtls_x509_name *mbedtls_x509_dn_get_next( + mbedtls_x509_name *dn) +{ + while (dn->MBEDTLS_PRIVATE(next_merged) && dn->next != NULL) { + dn = dn->next; + } + return dn->next; +} + +/** + * \brief Store the certificate serial in printable form into buf; + * no more than size characters will be written. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param serial The X509 serial to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_serial_gets(char *buf, size_t size, const mbedtls_x509_buf *serial); + +/** + * \brief Compare pair of mbedtls_x509_time. + * + * \param t1 mbedtls_x509_time to compare + * \param t2 mbedtls_x509_time to compare + * + * \return < 0 if t1 is before t2 + * 0 if t1 equals t2 + * > 0 if t1 is after t2 + */ +int mbedtls_x509_time_cmp(const mbedtls_x509_time *t1, const mbedtls_x509_time *t2); + +#if defined(MBEDTLS_HAVE_TIME_DATE) +/** + * \brief Fill mbedtls_x509_time with provided mbedtls_time_t. + * + * \param tt mbedtls_time_t to convert + * \param now mbedtls_x509_time to fill with converted mbedtls_time_t + * + * \return \c 0 on success + * \return A non-zero return value on failure. + */ +int mbedtls_x509_time_gmtime(mbedtls_time_t tt, mbedtls_x509_time *now); +#endif /* MBEDTLS_HAVE_TIME_DATE */ + +/** + * \brief Check a given mbedtls_x509_time against the system time + * and tell if it's in the past. + * + * \note Intended usage is "if( is_past( valid_to ) ) ERROR". + * Hence the return value of 1 if on internal errors. + * + * \param to mbedtls_x509_time to check + * + * \return 1 if the given time is in the past or an error occurred, + * 0 otherwise. + */ +int mbedtls_x509_time_is_past(const mbedtls_x509_time *to); + +/** + * \brief Check a given mbedtls_x509_time against the system time + * and tell if it's in the future. + * + * \note Intended usage is "if( is_future( valid_from ) ) ERROR". + * Hence the return value of 1 if on internal errors. + * + * \param from mbedtls_x509_time to check + * + * \return 1 if the given time is in the future or an error occurred, + * 0 otherwise. + */ +int mbedtls_x509_time_is_future(const mbedtls_x509_time *from); + +/** + * \brief This function parses an item in the SubjectAlternativeNames + * extension. Please note that this function might allocate + * additional memory for a subject alternative name, thus + * mbedtls_x509_free_subject_alt_name has to be called + * to dispose of this additional memory afterwards. + * + * \param san_buf The buffer holding the raw data item of the subject + * alternative name. + * \param san The target structure to populate with the parsed presentation + * of the subject alternative name encoded in \p san_buf. + * + * \note Supported GeneralName types, as defined in RFC 5280: + * "rfc822Name", "dnsName", "directoryName", + * "uniformResourceIdentifier" and "hardware_module_name" + * of type "otherName", as defined in RFC 4108. + * + * \note This function should be called on a single raw data of + * subject alternative name. For example, after successful + * certificate parsing, one must iterate on every item in the + * \c crt->subject_alt_names sequence, and pass it to + * this function. + * + * \warning The target structure contains pointers to the raw data of the + * parsed certificate, and its lifetime is restricted by the + * lifetime of the certificate. + * + * \return \c 0 on success + * \return #MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE for an unsupported + * SAN type. + * \return Another negative value for any other failure. + */ +int mbedtls_x509_parse_subject_alt_name(const mbedtls_x509_buf *san_buf, + mbedtls_x509_subject_alternative_name *san); +/** + * \brief Unallocate all data related to subject alternative name + * + * \param san SAN structure - extra memory owned by this structure will be freed + */ +void mbedtls_x509_free_subject_alt_name(mbedtls_x509_subject_alternative_name *san); + +/** \} addtogroup x509_module */ + +/* + * Internal module functions. You probably do not want to use these unless you + * know you do. + */ +int mbedtls_x509_get_name(unsigned char **p, const unsigned char *end, + mbedtls_x509_name *cur); +int mbedtls_x509_get_alg_null(unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg); +int mbedtls_x509_get_alg(unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *alg, mbedtls_x509_buf *params); +#if defined(MBEDTLS_X509_RSASSA_PSS_SUPPORT) +int mbedtls_x509_get_rsassa_pss_params(const mbedtls_x509_buf *params, + mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md, + int *salt_len); +#endif +int mbedtls_x509_get_sig(unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig); +int mbedtls_x509_get_sig_alg(const mbedtls_x509_buf *sig_oid, const mbedtls_x509_buf *sig_params, + mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg, + void **sig_opts); +int mbedtls_x509_get_time(unsigned char **p, const unsigned char *end, + mbedtls_x509_time *t); +int mbedtls_x509_get_serial(unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *serial); +int mbedtls_x509_get_ext(unsigned char **p, const unsigned char *end, + mbedtls_x509_buf *ext, int tag); +#if !defined(MBEDTLS_X509_REMOVE_INFO) +int mbedtls_x509_sig_alg_gets(char *buf, size_t size, const mbedtls_x509_buf *sig_oid, + mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, + const void *sig_opts); +#endif +int mbedtls_x509_key_size_helper(char *buf, size_t buf_size, const char *name); +int mbedtls_x509_string_to_names(mbedtls_asn1_named_data **head, const char *name); +int mbedtls_x509_set_extension(mbedtls_asn1_named_data **head, const char *oid, size_t oid_len, + int critical, const unsigned char *val, + size_t val_len); +int mbedtls_x509_write_extensions(unsigned char **p, unsigned char *start, + mbedtls_asn1_named_data *first); +int mbedtls_x509_write_names(unsigned char **p, unsigned char *start, + mbedtls_asn1_named_data *first); +int mbedtls_x509_write_sig(unsigned char **p, unsigned char *start, + const char *oid, size_t oid_len, + unsigned char *sig, size_t size, + mbedtls_pk_type_t pk_alg); +int mbedtls_x509_get_ns_cert_type(unsigned char **p, + const unsigned char *end, + unsigned char *ns_cert_type); +int mbedtls_x509_get_key_usage(unsigned char **p, + const unsigned char *end, + unsigned int *key_usage); +int mbedtls_x509_get_subject_alt_name(unsigned char **p, + const unsigned char *end, + mbedtls_x509_sequence *subject_alt_name); +int mbedtls_x509_get_subject_alt_name_ext(unsigned char **p, + const unsigned char *end, + mbedtls_x509_sequence *subject_alt_name); +int mbedtls_x509_info_subject_alt_name(char **buf, size_t *size, + const mbedtls_x509_sequence + *subject_alt_name, + const char *prefix); +int mbedtls_x509_info_cert_type(char **buf, size_t *size, + unsigned char ns_cert_type); +int mbedtls_x509_info_key_usage(char **buf, size_t *size, + unsigned int key_usage); + +int mbedtls_x509_write_set_san_common(mbedtls_asn1_named_data **extensions, + const mbedtls_x509_san_list *san_list); + +/** + * \brief This function parses a CN string as an IP address. + * + * \param cn The CN string to parse. CN string MUST be null-terminated. + * \param dst The target buffer to populate with the binary IP address. + * The buffer MUST be 16 bytes to save IPv6, and should be + * 4-byte aligned if the result will be used as struct in_addr. + * e.g. uint32_t dst[4] + * + * \note \p cn is parsed as an IPv6 address if string contains ':', + * else \p cn is parsed as an IPv4 address. + * + * \return Length of binary IP address; num bytes written to target. + * \return \c 0 on failure to parse CN string as an IP address. + */ +size_t mbedtls_x509_crt_parse_cn_inet_pton(const char *cn, void *dst); + +#define MBEDTLS_X509_SAFE_SNPRINTF \ + do { \ + if (ret < 0 || (size_t) ret >= n) \ + return MBEDTLS_ERR_X509_BUFFER_TOO_SMALL; \ + \ + n -= (size_t) ret; \ + p += (size_t) ret; \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* x509.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crl.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crl.h index 62694ae..db2ce5f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crl.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crl.h @@ -1,196 +1,196 @@ -/** - * \file x509_crl.h - * - * \brief X.509 certificate revocation list parsing - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_X509_CRL_H -#define MBEDTLS_X509_CRL_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/x509.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup x509_module - * \{ */ - -/** - * \name Structures and functions for parsing CRLs - * \{ - */ - -/** - * Certificate revocation list entry. - * Contains the CA-specific serial numbers and revocation dates. - * - * Some fields of this structure are publicly readable. Do not modify - * them except via Mbed TLS library functions: the effect of modifying - * those fields or the data that those fields points to is unspecified. - */ -typedef struct mbedtls_x509_crl_entry { - /** Direct access to the whole entry inside the containing buffer. */ - mbedtls_x509_buf raw; - /** The serial number of the revoked certificate. */ - mbedtls_x509_buf serial; - /** The revocation date of this entry. */ - mbedtls_x509_time revocation_date; - /** Direct access to the list of CRL entry extensions - * (an ASN.1 constructed sequence). - * - * If there are no extensions, `entry_ext.len == 0` and - * `entry_ext.p == NULL`. */ - mbedtls_x509_buf entry_ext; - - /** Next element in the linked list of entries. - * \p NULL indicates the end of the list. - * Do not modify this field directly. */ - struct mbedtls_x509_crl_entry *next; -} -mbedtls_x509_crl_entry; - -/** - * Certificate revocation list structure. - * Every CRL may have multiple entries. - */ -typedef struct mbedtls_x509_crl { - mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ - mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ - - int version; /**< CRL version (1=v1, 2=v2) */ - mbedtls_x509_buf sig_oid; /**< CRL signature type identifier */ - - mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). */ - - mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ - - mbedtls_x509_time this_update; - mbedtls_x509_time next_update; - - mbedtls_x509_crl_entry entry; /**< The CRL entries containing the certificate revocation times for this CA. */ - - mbedtls_x509_buf crl_ext; - - mbedtls_x509_buf MBEDTLS_PRIVATE(sig_oid2); - mbedtls_x509_buf MBEDTLS_PRIVATE(sig); - mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ - mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ - void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ - - /** Next element in the linked list of CRL. - * \p NULL indicates the end of the list. - * Do not modify this field directly. */ - struct mbedtls_x509_crl *next; -} -mbedtls_x509_crl; - -/** - * \brief Parse a DER-encoded CRL and append it to the chained list - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain points to the start of the chain - * \param buf buffer holding the CRL data in DER format - * \param buflen size of the buffer - * (including the terminating null byte for PEM data) - * - * \return 0 if successful, or a specific X509 or PEM error code - */ -int mbedtls_x509_crl_parse_der(mbedtls_x509_crl *chain, - const unsigned char *buf, size_t buflen); -/** - * \brief Parse one or more CRLs and append them to the chained list - * - * \note Multiple CRLs are accepted only if using PEM format - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain points to the start of the chain - * \param buf buffer holding the CRL data in PEM or DER format - * \param buflen size of the buffer - * (including the terminating null byte for PEM data) - * - * \return 0 if successful, or a specific X509 or PEM error code - */ -int mbedtls_x509_crl_parse(mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief Load one or more CRLs and append them to the chained list - * - * \note Multiple CRLs are accepted only if using PEM format - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain points to the start of the chain - * \param path filename to read the CRLs from (in PEM or DER encoding) - * - * \return 0 if successful, or a specific X509 or PEM error code - */ -int mbedtls_x509_crl_parse_file(mbedtls_x509_crl *chain, const char *path); -#endif /* MBEDTLS_FS_IO */ - -#if !defined(MBEDTLS_X509_REMOVE_INFO) -/** - * \brief Returns an informational string about the CRL. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param prefix A line prefix - * \param crl The X509 CRL to represent - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_crl_info(char *buf, size_t size, const char *prefix, - const mbedtls_x509_crl *crl); -#endif /* !MBEDTLS_X509_REMOVE_INFO */ - -/** - * \brief Initialize a CRL (chain) - * - * \param crl CRL chain to initialize - */ -void mbedtls_x509_crl_init(mbedtls_x509_crl *crl); - -/** - * \brief Unallocate all CRL data - * - * \param crl CRL chain to free - */ -void mbedtls_x509_crl_free(mbedtls_x509_crl *crl); - -/** \} name Structures and functions for parsing CRLs */ -/** \} addtogroup x509_module */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_x509_crl.h */ +/** + * \file x509_crl.h + * + * \brief X.509 certificate revocation list parsing + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_X509_CRL_H +#define MBEDTLS_X509_CRL_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/x509.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures and functions for parsing CRLs + * \{ + */ + +/** + * Certificate revocation list entry. + * Contains the CA-specific serial numbers and revocation dates. + * + * Some fields of this structure are publicly readable. Do not modify + * them except via Mbed TLS library functions: the effect of modifying + * those fields or the data that those fields points to is unspecified. + */ +typedef struct mbedtls_x509_crl_entry { + /** Direct access to the whole entry inside the containing buffer. */ + mbedtls_x509_buf raw; + /** The serial number of the revoked certificate. */ + mbedtls_x509_buf serial; + /** The revocation date of this entry. */ + mbedtls_x509_time revocation_date; + /** Direct access to the list of CRL entry extensions + * (an ASN.1 constructed sequence). + * + * If there are no extensions, `entry_ext.len == 0` and + * `entry_ext.p == NULL`. */ + mbedtls_x509_buf entry_ext; + + /** Next element in the linked list of entries. + * \p NULL indicates the end of the list. + * Do not modify this field directly. */ + struct mbedtls_x509_crl_entry *next; +} +mbedtls_x509_crl_entry; + +/** + * Certificate revocation list structure. + * Every CRL may have multiple entries. + */ +typedef struct mbedtls_x509_crl { + mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ + mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ + + int version; /**< CRL version (1=v1, 2=v2) */ + mbedtls_x509_buf sig_oid; /**< CRL signature type identifier */ + + mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). */ + + mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ + + mbedtls_x509_time this_update; + mbedtls_x509_time next_update; + + mbedtls_x509_crl_entry entry; /**< The CRL entries containing the certificate revocation times for this CA. */ + + mbedtls_x509_buf crl_ext; + + mbedtls_x509_buf MBEDTLS_PRIVATE(sig_oid2); + mbedtls_x509_buf MBEDTLS_PRIVATE(sig); + mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ + + /** Next element in the linked list of CRL. + * \p NULL indicates the end of the list. + * Do not modify this field directly. */ + struct mbedtls_x509_crl *next; +} +mbedtls_x509_crl; + +/** + * \brief Parse a DER-encoded CRL and append it to the chained list + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain points to the start of the chain + * \param buf buffer holding the CRL data in DER format + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse_der(mbedtls_x509_crl *chain, + const unsigned char *buf, size_t buflen); +/** + * \brief Parse one or more CRLs and append them to the chained list + * + * \note Multiple CRLs are accepted only if using PEM format + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain points to the start of the chain + * \param buf buffer holding the CRL data in PEM or DER format + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse(mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load one or more CRLs and append them to the chained list + * + * \note Multiple CRLs are accepted only if using PEM format + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain points to the start of the chain + * \param path filename to read the CRLs from (in PEM or DER encoding) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_crl_parse_file(mbedtls_x509_crl *chain, const char *path); +#endif /* MBEDTLS_FS_IO */ + +#if !defined(MBEDTLS_X509_REMOVE_INFO) +/** + * \brief Returns an informational string about the CRL. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param crl The X509 CRL to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crl_info(char *buf, size_t size, const char *prefix, + const mbedtls_x509_crl *crl); +#endif /* !MBEDTLS_X509_REMOVE_INFO */ + +/** + * \brief Initialize a CRL (chain) + * + * \param crl CRL chain to initialize + */ +void mbedtls_x509_crl_init(mbedtls_x509_crl *crl); + +/** + * \brief Unallocate all CRL data + * + * \param crl CRL chain to free + */ +void mbedtls_x509_crl_free(mbedtls_x509_crl *crl); + +/** \} name Structures and functions for parsing CRLs */ +/** \} addtogroup x509_module */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_crl.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crt.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crt.h index 3f9b250..4655cf5 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crt.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_crt.h @@ -1,1208 +1,1208 @@ -/** - * \file x509_crt.h - * - * \brief X.509 certificate parsing and writing - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_X509_CRT_H -#define MBEDTLS_X509_CRT_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/x509.h" -#include "mbedtls/x509_crl.h" -#include "mbedtls/bignum.h" - -/** - * \addtogroup x509_module - * \{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Structures and functions for parsing and writing X.509 certificates - * \{ - */ - -/** - * Container for an X.509 certificate. The certificate may be chained. - * - * Some fields of this structure are publicly readable. Do not modify - * them except via Mbed TLS library functions: the effect of modifying - * those fields or the data that those fields points to is unspecified. - */ -typedef struct mbedtls_x509_crt { - int MBEDTLS_PRIVATE(own_buffer); /**< Indicates if \c raw is owned - * by the structure or not. */ - mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ - mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ - - int version; /**< The X.509 version. (1=v1, 2=v2, 3=v3) */ - mbedtls_x509_buf serial; /**< Unique id for certificate issued by a specific CA. */ - mbedtls_x509_buf sig_oid; /**< Signature algorithm, e.g. sha1RSA */ - - mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). Used for quick comparison. */ - mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). Used for quick comparison. */ - - mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ - mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ - - mbedtls_x509_time valid_from; /**< Start time of certificate validity. */ - mbedtls_x509_time valid_to; /**< End time of certificate validity. */ - - mbedtls_x509_buf pk_raw; - mbedtls_pk_context pk; /**< Container for the public key context. */ - - mbedtls_x509_buf issuer_id; /**< Optional X.509 v2/v3 issuer unique identifier. */ - mbedtls_x509_buf subject_id; /**< Optional X.509 v2/v3 subject unique identifier. */ - mbedtls_x509_buf v3_ext; /**< Optional X.509 v3 extensions. */ - mbedtls_x509_sequence subject_alt_names; /**< Optional list of raw entries of Subject Alternative Names extension. These can be later parsed by mbedtls_x509_parse_subject_alt_name. */ - mbedtls_x509_buf subject_key_id; /**< Optional X.509 v3 extension subject key identifier. */ - mbedtls_x509_authority authority_key_id; /**< Optional X.509 v3 extension authority key identifier. */ - - mbedtls_x509_sequence certificate_policies; /**< Optional list of certificate policies (Only anyPolicy is printed and enforced, however the rest of the policies are still listed). */ - - int MBEDTLS_PRIVATE(ext_types); /**< Bit string containing detected and parsed extensions */ - int MBEDTLS_PRIVATE(ca_istrue); /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */ - int MBEDTLS_PRIVATE(max_pathlen); /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. Path length is 1 higher than RFC 5280 'meaning', so 1+ */ - - unsigned int MBEDTLS_PRIVATE(key_usage); /**< Optional key usage extension value: See the values in x509.h */ - - mbedtls_x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */ - - unsigned char MBEDTLS_PRIVATE(ns_cert_type); /**< Optional Netscape certificate type extension value: See the values in x509.h */ - - mbedtls_x509_buf MBEDTLS_PRIVATE(sig); /**< Signature: hash of the tbs part signed with the private key. */ - mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ - mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ - void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ - - /** Next certificate in the linked list that constitutes the CA chain. - * \p NULL indicates the end of the list. - * Do not modify this field directly. */ - struct mbedtls_x509_crt *next; -} -mbedtls_x509_crt; - -/** - * Build flag from an algorithm/curve identifier (pk, md, ecp) - * Since 0 is always XXX_NONE, ignore it. - */ -#define MBEDTLS_X509_ID_FLAG(id) (1 << ((id) - 1)) - -/** - * Security profile for certificate verification. - * - * All lists are bitfields, built by ORing flags from MBEDTLS_X509_ID_FLAG(). - * - * The fields of this structure are part of the public API and can be - * manipulated directly by applications. Future versions of the library may - * add extra fields or reorder existing fields. - * - * You can create custom profiles by starting from a copy of - * an existing profile, such as mbedtls_x509_crt_profile_default or - * mbedtls_x509_ctr_profile_none and then tune it to your needs. - * - * For example to allow SHA-224 in addition to the default: - * - * mbedtls_x509_crt_profile my_profile = mbedtls_x509_crt_profile_default; - * my_profile.allowed_mds |= MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA224 ); - * - * Or to allow only RSA-3072+ with SHA-256: - * - * mbedtls_x509_crt_profile my_profile = mbedtls_x509_crt_profile_none; - * my_profile.allowed_mds = MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA256 ); - * my_profile.allowed_pks = MBEDTLS_X509_ID_FLAG( MBEDTLS_PK_RSA ); - * my_profile.rsa_min_bitlen = 3072; - */ -typedef struct mbedtls_x509_crt_profile { - uint32_t allowed_mds; /**< MDs for signatures */ - uint32_t allowed_pks; /**< PK algs for public keys; - * this applies to all certificates - * in the provided chain. */ - uint32_t allowed_curves; /**< Elliptic curves for ECDSA */ - uint32_t rsa_min_bitlen; /**< Minimum size for RSA keys */ -} -mbedtls_x509_crt_profile; - -#define MBEDTLS_X509_CRT_VERSION_1 0 -#define MBEDTLS_X509_CRT_VERSION_2 1 -#define MBEDTLS_X509_CRT_VERSION_3 2 - -#define MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN 20 -#define MBEDTLS_X509_RFC5280_UTC_TIME_LEN 15 - -#if !defined(MBEDTLS_X509_MAX_FILE_PATH_LEN) -#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 -#endif - -/* This macro unfolds to the concatenation of macro invocations - * X509_CRT_ERROR_INFO( error code, - * error code as string, - * human readable description ) - * where X509_CRT_ERROR_INFO is defined by the user. - * See x509_crt.c for an example of how to use this. */ -#define MBEDTLS_X509_CRT_ERROR_INFO_LIST \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_EXPIRED, \ - "MBEDTLS_X509_BADCERT_EXPIRED", \ - "The certificate validity has expired") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_REVOKED, \ - "MBEDTLS_X509_BADCERT_REVOKED", \ - "The certificate has been revoked (is on a CRL)") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_CN_MISMATCH, \ - "MBEDTLS_X509_BADCERT_CN_MISMATCH", \ - "The certificate Common Name (CN) does not match with the expected CN") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_NOT_TRUSTED, \ - "MBEDTLS_X509_BADCERT_NOT_TRUSTED", \ - "The certificate is not correctly signed by the trusted CA") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_NOT_TRUSTED, \ - "MBEDTLS_X509_BADCRL_NOT_TRUSTED", \ - "The CRL is not correctly signed by the trusted CA") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_EXPIRED, \ - "MBEDTLS_X509_BADCRL_EXPIRED", \ - "The CRL is expired") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_MISSING, \ - "MBEDTLS_X509_BADCERT_MISSING", \ - "Certificate was missing") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_SKIP_VERIFY, \ - "MBEDTLS_X509_BADCERT_SKIP_VERIFY", \ - "Certificate verification was skipped") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_OTHER, \ - "MBEDTLS_X509_BADCERT_OTHER", \ - "Other reason (can be used by verify callback)") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_FUTURE, \ - "MBEDTLS_X509_BADCERT_FUTURE", \ - "The certificate validity starts in the future") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_FUTURE, \ - "MBEDTLS_X509_BADCRL_FUTURE", \ - "The CRL is from the future") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_KEY_USAGE, \ - "MBEDTLS_X509_BADCERT_KEY_USAGE", \ - "Usage does not match the keyUsage extension") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_EXT_KEY_USAGE, \ - "MBEDTLS_X509_BADCERT_EXT_KEY_USAGE", \ - "Usage does not match the extendedKeyUsage extension") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_NS_CERT_TYPE, \ - "MBEDTLS_X509_BADCERT_NS_CERT_TYPE", \ - "Usage does not match the nsCertType extension") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_MD, \ - "MBEDTLS_X509_BADCERT_BAD_MD", \ - "The certificate is signed with an unacceptable hash.") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_PK, \ - "MBEDTLS_X509_BADCERT_BAD_PK", \ - "The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA).") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_KEY, \ - "MBEDTLS_X509_BADCERT_BAD_KEY", \ - "The certificate is signed with an unacceptable key (eg bad curve, RSA too short).") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_MD, \ - "MBEDTLS_X509_BADCRL_BAD_MD", \ - "The CRL is signed with an unacceptable hash.") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_PK, \ - "MBEDTLS_X509_BADCRL_BAD_PK", \ - "The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA).") \ - X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_KEY, \ - "MBEDTLS_X509_BADCRL_BAD_KEY", \ - "The CRL is signed with an unacceptable key (eg bad curve, RSA too short).") - -/** - * Container for writing a certificate (CRT) - */ -typedef struct mbedtls_x509write_cert { - int MBEDTLS_PRIVATE(version); - unsigned char MBEDTLS_PRIVATE(serial)[MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN]; - size_t MBEDTLS_PRIVATE(serial_len); - mbedtls_pk_context *MBEDTLS_PRIVATE(subject_key); - mbedtls_pk_context *MBEDTLS_PRIVATE(issuer_key); - mbedtls_asn1_named_data *MBEDTLS_PRIVATE(subject); - mbedtls_asn1_named_data *MBEDTLS_PRIVATE(issuer); - mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); - char MBEDTLS_PRIVATE(not_before)[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; - char MBEDTLS_PRIVATE(not_after)[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; - mbedtls_asn1_named_data *MBEDTLS_PRIVATE(extensions); -} -mbedtls_x509write_cert; - -/** - * \brief Set Subject Alternative Name - * - * \param ctx Certificate context to use - * \param san_list List of SAN values - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - * - * \note "dnsName", "uniformResourceIdentifier", "IP address", - * "otherName", and "DirectoryName", as defined in RFC 5280, - * are supported. - */ -int mbedtls_x509write_crt_set_subject_alternative_name(mbedtls_x509write_cert *ctx, - const mbedtls_x509_san_list *san_list); - -/** - * Item in a verification chain: cert and flags for it - */ -typedef struct { - mbedtls_x509_crt *MBEDTLS_PRIVATE(crt); - uint32_t MBEDTLS_PRIVATE(flags); -} mbedtls_x509_crt_verify_chain_item; - -/** - * Max size of verification chain: end-entity + intermediates + trusted root - */ -#define MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE (MBEDTLS_X509_MAX_INTERMEDIATE_CA + 2) - -/** - * Verification chain as built by \c mbedtls_crt_verify_chain() - */ -typedef struct { - mbedtls_x509_crt_verify_chain_item MBEDTLS_PRIVATE(items)[MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE]; - unsigned MBEDTLS_PRIVATE(len); - -#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) - /* This stores the list of potential trusted signers obtained from - * the CA callback used for the CRT verification, if configured. - * We must track it somewhere because the callback passes its - * ownership to the caller. */ - mbedtls_x509_crt *MBEDTLS_PRIVATE(trust_ca_cb_result); -#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ -} mbedtls_x509_crt_verify_chain; - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) - -/** - * \brief Context for resuming X.509 verify operations - */ -typedef struct { - /* for check_signature() */ - mbedtls_pk_restart_ctx MBEDTLS_PRIVATE(pk); - - /* for find_parent_in() */ - mbedtls_x509_crt *MBEDTLS_PRIVATE(parent); /* non-null iff parent_in in progress */ - mbedtls_x509_crt *MBEDTLS_PRIVATE(fallback_parent); - int MBEDTLS_PRIVATE(fallback_signature_is_good); - - /* for find_parent() */ - int MBEDTLS_PRIVATE(parent_is_trusted); /* -1 if find_parent is not in progress */ - - /* for verify_chain() */ - enum { - x509_crt_rs_none, - x509_crt_rs_find_parent, - } MBEDTLS_PRIVATE(in_progress); /* none if no operation is in progress */ - int MBEDTLS_PRIVATE(self_cnt); - mbedtls_x509_crt_verify_chain MBEDTLS_PRIVATE(ver_chain); - -} mbedtls_x509_crt_restart_ctx; - -#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - -/* Now we can declare functions that take a pointer to that */ -typedef void mbedtls_x509_crt_restart_ctx; - -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/** - * Default security profile. Should provide a good balance between security - * and compatibility with current deployments. - * - * This profile permits: - * - SHA2 hashes with at least 256 bits: SHA-256, SHA-384, SHA-512. - * - Elliptic curves with 255 bits and above except secp256k1. - * - RSA with 2048 bits and above. - * - * New minor versions of Mbed TLS may extend this profile, for example if - * new algorithms are added to the library. New minor versions of Mbed TLS will - * not reduce this profile unless serious security concerns require it. - */ -extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default; - -/** - * Expected next default profile. Recommended for new deployments. - * Currently targets a 128-bit security level, except for allowing RSA-2048. - * This profile may change at any time. - */ -extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next; - -/** - * NSA Suite B profile. - */ -extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb; - -/** - * Empty profile that allows nothing. Useful as a basis for constructing - * custom profiles. - */ -extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_none; - -/** - * \brief Parse a single DER formatted certificate and add it - * to the end of the provided chained list. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain The pointer to the start of the CRT chain to attach to. - * When parsing the first CRT in a chain, this should point - * to an instance of ::mbedtls_x509_crt initialized through - * mbedtls_x509_crt_init(). - * \param buf The buffer holding the DER encoded certificate. - * \param buflen The size in Bytes of \p buf. - * - * \note This function makes an internal copy of the CRT buffer - * \p buf. In particular, \p buf may be destroyed or reused - * after this call returns. To avoid duplicating the CRT - * buffer (at the cost of stricter lifetime constraints), - * use mbedtls_x509_crt_parse_der_nocopy() instead. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_x509_crt_parse_der(mbedtls_x509_crt *chain, - const unsigned char *buf, - size_t buflen); - -/** - * \brief The type of certificate extension callbacks. - * - * Callbacks of this type are passed to and used by the - * mbedtls_x509_crt_parse_der_with_ext_cb() routine when - * it encounters either an unsupported extension or a - * "certificate policies" extension containing any - * unsupported certificate policies. - * Future versions of the library may invoke the callback - * in other cases, if and when the need arises. - * - * \param p_ctx An opaque context passed to the callback. - * \param crt The certificate being parsed. - * \param oid The OID of the extension. - * \param critical Whether the extension is critical. - * \param p Pointer to the start of the extension value - * (the content of the OCTET STRING). - * \param end End of extension value. - * - * \note The callback must fail and return a negative error code - * if it can not parse or does not support the extension. - * When the callback fails to parse a critical extension - * mbedtls_x509_crt_parse_der_with_ext_cb() also fails. - * When the callback fails to parse a non critical extension - * mbedtls_x509_crt_parse_der_with_ext_cb() simply skips - * the extension and continues parsing. - * - * \return \c 0 on success. - * \return A negative error code on failure. - */ -typedef int (*mbedtls_x509_crt_ext_cb_t)(void *p_ctx, - mbedtls_x509_crt const *crt, - mbedtls_x509_buf const *oid, - int critical, - const unsigned char *p, - const unsigned char *end); - -/** - * \brief Parse a single DER formatted certificate and add it - * to the end of the provided chained list. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain The pointer to the start of the CRT chain to attach to. - * When parsing the first CRT in a chain, this should point - * to an instance of ::mbedtls_x509_crt initialized through - * mbedtls_x509_crt_init(). - * \param buf The buffer holding the DER encoded certificate. - * \param buflen The size in Bytes of \p buf. - * \param make_copy When not zero this function makes an internal copy of the - * CRT buffer \p buf. In particular, \p buf may be destroyed - * or reused after this call returns. - * When zero this function avoids duplicating the CRT buffer - * by taking temporary ownership thereof until the CRT - * is destroyed (like mbedtls_x509_crt_parse_der_nocopy()) - * \param cb A callback invoked for every unsupported certificate - * extension. - * \param p_ctx An opaque context passed to the callback. - * - * \note This call is functionally equivalent to - * mbedtls_x509_crt_parse_der(), and/or - * mbedtls_x509_crt_parse_der_nocopy() - * but it calls the callback with every unsupported - * certificate extension and additionally the - * "certificate policies" extension if it contains any - * unsupported certificate policies. - * The callback must return a negative error code if it - * does not know how to handle such an extension. - * When the callback fails to parse a critical extension - * mbedtls_x509_crt_parse_der_with_ext_cb() also fails. - * When the callback fails to parse a non critical extension - * mbedtls_x509_crt_parse_der_with_ext_cb() simply skips - * the extension and continues parsing. - * Future versions of the library may invoke the callback - * in other cases, if and when the need arises. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_x509_crt_parse_der_with_ext_cb(mbedtls_x509_crt *chain, - const unsigned char *buf, - size_t buflen, - int make_copy, - mbedtls_x509_crt_ext_cb_t cb, - void *p_ctx); - -/** - * \brief Parse a single DER formatted certificate and add it - * to the end of the provided chained list. This is a - * variant of mbedtls_x509_crt_parse_der() which takes - * temporary ownership of the CRT buffer until the CRT - * is destroyed. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain The pointer to the start of the CRT chain to attach to. - * When parsing the first CRT in a chain, this should point - * to an instance of ::mbedtls_x509_crt initialized through - * mbedtls_x509_crt_init(). - * \param buf The address of the readable buffer holding the DER encoded - * certificate to use. On success, this buffer must be - * retained and not be changed for the lifetime of the - * CRT chain \p chain, that is, until \p chain is destroyed - * through a call to mbedtls_x509_crt_free(). - * \param buflen The size in Bytes of \p buf. - * - * \note This call is functionally equivalent to - * mbedtls_x509_crt_parse_der(), but it avoids creating a - * copy of the input buffer at the cost of stronger lifetime - * constraints. This is useful in constrained environments - * where duplication of the CRT cannot be tolerated. - * - * \return \c 0 if successful. - * \return A negative error code on failure. - */ -int mbedtls_x509_crt_parse_der_nocopy(mbedtls_x509_crt *chain, - const unsigned char *buf, - size_t buflen); - -/** - * \brief Parse one DER-encoded or one or more concatenated PEM-encoded - * certificates and add them to the chained list. - * - * For CRTs in PEM encoding, the function parses permissively: - * if at least one certificate can be parsed, the function - * returns the number of certificates for which parsing failed - * (hence \c 0 if all certificates were parsed successfully). - * If no certificate could be parsed, the function returns - * the first (negative) error encountered during parsing. - * - * PEM encoded certificates may be interleaved by other data - * such as human readable descriptions of their content, as - * long as the certificates are enclosed in the PEM specific - * '-----{BEGIN/END} CERTIFICATE-----' delimiters. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain The chain to which to add the parsed certificates. - * \param buf The buffer holding the certificate data in PEM or DER format. - * For certificates in PEM encoding, this may be a concatenation - * of multiple certificates; for DER encoding, the buffer must - * comprise exactly one certificate. - * \param buflen The size of \p buf, including the terminating \c NULL byte - * in case of PEM encoded data. - * - * \return \c 0 if all certificates were parsed successfully. - * \return The (positive) number of certificates that couldn't - * be parsed if parsing was partly successful (see above). - * \return A negative X509 or PEM error code otherwise. - * - */ -int mbedtls_x509_crt_parse(mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief Load one or more certificates and add them - * to the chained list. Parses permissively. If some - * certificates can be parsed, the result is the number - * of failed certificates it encountered. If none complete - * correctly, the first error is returned. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param chain points to the start of the chain - * \param path filename to read the certificates from - * - * \return 0 if all certificates parsed successfully, a positive number - * if partly successful or a specific X509 or PEM error code - */ -int mbedtls_x509_crt_parse_file(mbedtls_x509_crt *chain, const char *path); - -/** - * \brief Load one or more certificate files from a path and add them - * to the chained list. Parses permissively. If some - * certificates can be parsed, the result is the number - * of failed certificates it encountered. If none complete - * correctly, the first error is returned. - * - * \param chain points to the start of the chain - * \param path directory / folder to read the certificate files from - * - * \return 0 if all certificates parsed successfully, a positive number - * if partly successful or a specific X509 or PEM error code - */ -int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *chain, const char *path); - -#endif /* MBEDTLS_FS_IO */ - -#if !defined(MBEDTLS_X509_REMOVE_INFO) -/** - * \brief Returns an informational string about the - * certificate. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param prefix A line prefix - * \param crt The X509 certificate to represent - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_crt_info(char *buf, size_t size, const char *prefix, - const mbedtls_x509_crt *crt); - -/** - * \brief Returns an informational string about the - * verification status of a certificate. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param prefix A line prefix - * \param flags Verification flags created by mbedtls_x509_crt_verify() - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_crt_verify_info(char *buf, size_t size, const char *prefix, - uint32_t flags); -#endif /* !MBEDTLS_X509_REMOVE_INFO */ - -/** - * \brief Verify a chain of certificates. - * - * The verify callback is a user-supplied callback that - * can clear / modify / add flags for a certificate. If set, - * the verification callback is called for each - * certificate in the chain (from the trust-ca down to the - * presented crt). The parameters for the callback are: - * (void *parameter, mbedtls_x509_crt *crt, int certificate_depth, - * int *flags). With the flags representing current flags for - * that specific certificate and the certificate depth from - * the bottom (Peer cert depth = 0). - * - * All flags left after returning from the callback - * are also returned to the application. The function should - * return 0 for anything (including invalid certificates) - * other than fatal error, as a non-zero return code - * immediately aborts the verification process. For fatal - * errors, a specific error code should be used (different - * from MBEDTLS_ERR_X509_CERT_VERIFY_FAILED which should not - * be returned at this point), or MBEDTLS_ERR_X509_FATAL_ERROR - * can be used if no better code is available. - * - * \note In case verification failed, the results can be displayed - * using \c mbedtls_x509_crt_verify_info() - * - * \note Same as \c mbedtls_x509_crt_verify_with_profile() with the - * default security profile. - * - * \note It is your responsibility to provide up-to-date CRLs for - * all trusted CAs. If no CRL is provided for the CA that was - * used to sign the certificate, CRL verification is skipped - * silently, that is *without* setting any flag. - * - * \note The \c trust_ca list can contain two types of certificates: - * (1) those of trusted root CAs, so that certificates - * chaining up to those CAs will be trusted, and (2) - * self-signed end-entity certificates to be trusted (for - * specific peers you know) - in that case, the self-signed - * certificate doesn't need to have the CA bit set. - * - * \param crt The certificate chain to be verified. - * \param trust_ca The list of trusted CAs. - * \param ca_crl The list of CRLs for trusted CAs. - * \param cn The expected Common Name. This will be checked to be - * present in the certificate's subjectAltNames extension or, - * if this extension is absent, as a CN component in its - * Subject name. DNS names and IP addresses are fully - * supported, while the URI subtype is partially supported: - * only exact matching, without any normalization procedures - * described in 7.4 of RFC5280, will result in a positive - * URI verification. - * This may be \c NULL if the CN need not be verified. - * \param flags The address at which to store the result of the verification. - * If the verification couldn't be completed, the flag value is - * set to (uint32_t) -1. - * \param f_vrfy The verification callback to use. See the documentation - * of mbedtls_x509_crt_verify() for more information. - * \param p_vrfy The context to be passed to \p f_vrfy. - * - * \return \c 0 if the chain is valid with respect to the - * passed CN, CAs, CRLs and security profile. - * \return #MBEDTLS_ERR_X509_CERT_VERIFY_FAILED in case the - * certificate chain verification failed. In this case, - * \c *flags will have one or more - * \c MBEDTLS_X509_BADCERT_XXX or \c MBEDTLS_X509_BADCRL_XXX - * flags set. - * \return Another negative error code in case of a fatal error - * encountered during the verification process. - */ -int mbedtls_x509_crt_verify(mbedtls_x509_crt *crt, - mbedtls_x509_crt *trust_ca, - mbedtls_x509_crl *ca_crl, - const char *cn, uint32_t *flags, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy); - -/** - * \brief Verify a chain of certificates with respect to - * a configurable security profile. - * - * \note Same as \c mbedtls_x509_crt_verify(), but with explicit - * security profile. - * - * \note The restrictions on keys (RSA minimum size, allowed curves - * for ECDSA) apply to all certificates: trusted root, - * intermediate CAs if any, and end entity certificate. - * - * \param crt The certificate chain to be verified. - * \param trust_ca The list of trusted CAs. - * \param ca_crl The list of CRLs for trusted CAs. - * \param profile The security profile to use for the verification. - * \param cn The expected Common Name. This may be \c NULL if the - * CN need not be verified. - * \param flags The address at which to store the result of the verification. - * If the verification couldn't be completed, the flag value is - * set to (uint32_t) -1. - * \param f_vrfy The verification callback to use. See the documentation - * of mbedtls_x509_crt_verify() for more information. - * \param p_vrfy The context to be passed to \p f_vrfy. - * - * \return \c 0 if the chain is valid with respect to the - * passed CN, CAs, CRLs and security profile. - * \return #MBEDTLS_ERR_X509_CERT_VERIFY_FAILED in case the - * certificate chain verification failed. In this case, - * \c *flags will have one or more - * \c MBEDTLS_X509_BADCERT_XXX or \c MBEDTLS_X509_BADCRL_XXX - * flags set. - * \return Another negative error code in case of a fatal error - * encountered during the verification process. - */ -int mbedtls_x509_crt_verify_with_profile(mbedtls_x509_crt *crt, - mbedtls_x509_crt *trust_ca, - mbedtls_x509_crl *ca_crl, - const mbedtls_x509_crt_profile *profile, - const char *cn, uint32_t *flags, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy); - -/** - * \brief Restartable version of \c mbedtls_crt_verify_with_profile() - * - * \note Performs the same job as \c mbedtls_crt_verify_with_profile() - * but can return early and restart according to the limit - * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. - * - * \param crt The certificate chain to be verified. - * \param trust_ca The list of trusted CAs. - * \param ca_crl The list of CRLs for trusted CAs. - * \param profile The security profile to use for the verification. - * \param cn The expected Common Name. This may be \c NULL if the - * CN need not be verified. - * \param flags The address at which to store the result of the verification. - * If the verification couldn't be completed, the flag value is - * set to (uint32_t) -1. - * \param f_vrfy The verification callback to use. See the documentation - * of mbedtls_x509_crt_verify() for more information. - * \param p_vrfy The context to be passed to \p f_vrfy. - * \param rs_ctx The restart context to use. This may be set to \c NULL - * to disable restartable ECC. - * - * \return See \c mbedtls_crt_verify_with_profile(), or - * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of - * operations was reached: see \c mbedtls_ecp_set_max_ops(). - */ -int mbedtls_x509_crt_verify_restartable(mbedtls_x509_crt *crt, - mbedtls_x509_crt *trust_ca, - mbedtls_x509_crl *ca_crl, - const mbedtls_x509_crt_profile *profile, - const char *cn, uint32_t *flags, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy, - mbedtls_x509_crt_restart_ctx *rs_ctx); - -/** - * \brief The type of trusted certificate callbacks. - * - * Callbacks of this type are passed to and used by the CRT - * verification routine mbedtls_x509_crt_verify_with_ca_cb() - * when looking for trusted signers of a given certificate. - * - * On success, the callback returns a list of trusted - * certificates to be considered as potential signers - * for the input certificate. - * - * \param p_ctx An opaque context passed to the callback. - * \param child The certificate for which to search a potential signer. - * This will point to a readable certificate. - * \param candidate_cas The address at which to store the address of the first - * entry in the generated linked list of candidate signers. - * This will not be \c NULL. - * - * \note The callback must only return a non-zero value on a - * fatal error. If, in contrast, the search for a potential - * signer completes without a single candidate, the - * callback must return \c 0 and set \c *candidate_cas - * to \c NULL. - * - * \return \c 0 on success. In this case, \c *candidate_cas points - * to a heap-allocated linked list of instances of - * ::mbedtls_x509_crt, and ownership of this list is passed - * to the caller. - * \return A negative error code on failure. - */ -typedef int (*mbedtls_x509_crt_ca_cb_t)(void *p_ctx, - mbedtls_x509_crt const *child, - mbedtls_x509_crt **candidate_cas); - -#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) -/** - * \brief Version of \c mbedtls_x509_crt_verify_with_profile() which - * uses a callback to acquire the list of trusted CA - * certificates. - * - * \param crt The certificate chain to be verified. - * \param f_ca_cb The callback to be used to query for potential signers - * of a given child certificate. See the documentation of - * ::mbedtls_x509_crt_ca_cb_t for more information. - * \param p_ca_cb The opaque context to be passed to \p f_ca_cb. - * \param profile The security profile for the verification. - * \param cn The expected Common Name. This may be \c NULL if the - * CN need not be verified. - * \param flags The address at which to store the result of the verification. - * If the verification couldn't be completed, the flag value is - * set to (uint32_t) -1. - * \param f_vrfy The verification callback to use. See the documentation - * of mbedtls_x509_crt_verify() for more information. - * \param p_vrfy The context to be passed to \p f_vrfy. - * - * \return See \c mbedtls_crt_verify_with_profile(). - */ -int mbedtls_x509_crt_verify_with_ca_cb(mbedtls_x509_crt *crt, - mbedtls_x509_crt_ca_cb_t f_ca_cb, - void *p_ca_cb, - const mbedtls_x509_crt_profile *profile, - const char *cn, uint32_t *flags, - int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), - void *p_vrfy); - -#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ - -/** - * \brief Check usage of certificate against keyUsage extension. - * - * \param crt Leaf certificate used. - * \param usage Intended usage(s) (eg MBEDTLS_X509_KU_KEY_ENCIPHERMENT - * before using the certificate to perform an RSA key - * exchange). - * - * \note Except for decipherOnly and encipherOnly, a bit set in the - * usage argument means this bit MUST be set in the - * certificate. For decipherOnly and encipherOnly, it means - * that bit MAY be set. - * - * \return 0 is these uses of the certificate are allowed, - * MBEDTLS_ERR_X509_BAD_INPUT_DATA if the keyUsage extension - * is present but does not match the usage argument. - * - * \note You should only call this function on leaf certificates, on - * (intermediate) CAs the keyUsage extension is automatically - * checked by \c mbedtls_x509_crt_verify(). - */ -int mbedtls_x509_crt_check_key_usage(const mbedtls_x509_crt *crt, - unsigned int usage); - -/** - * \brief Check usage of certificate against extendedKeyUsage. - * - * \param crt Leaf certificate used. - * \param usage_oid Intended usage (eg MBEDTLS_OID_SERVER_AUTH or - * MBEDTLS_OID_CLIENT_AUTH). - * \param usage_len Length of usage_oid (eg given by MBEDTLS_OID_SIZE()). - * - * \return 0 if this use of the certificate is allowed, - * MBEDTLS_ERR_X509_BAD_INPUT_DATA if not. - * - * \note Usually only makes sense on leaf certificates. - */ -int mbedtls_x509_crt_check_extended_key_usage(const mbedtls_x509_crt *crt, - const char *usage_oid, - size_t usage_len); - -#if defined(MBEDTLS_X509_CRL_PARSE_C) -/** - * \brief Verify the certificate revocation status - * - * \param crt a certificate to be verified - * \param crl the CRL to verify against - * - * \return 1 if the certificate is revoked, 0 otherwise - * - */ -int mbedtls_x509_crt_is_revoked(const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl); -#endif /* MBEDTLS_X509_CRL_PARSE_C */ - -/** - * \brief Initialize a certificate (chain) - * - * \param crt Certificate chain to initialize - */ -void mbedtls_x509_crt_init(mbedtls_x509_crt *crt); - -/** - * \brief Unallocate all certificate data - * - * \param crt Certificate chain to free - */ -void mbedtls_x509_crt_free(mbedtls_x509_crt *crt); - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) -/** - * \brief Initialize a restart context - */ -void mbedtls_x509_crt_restart_init(mbedtls_x509_crt_restart_ctx *ctx); - -/** - * \brief Free the components of a restart context - */ -void mbedtls_x509_crt_restart_free(mbedtls_x509_crt_restart_ctx *ctx); -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -/** - * \brief Query certificate for given extension type - * - * \param[in] ctx Certificate context to be queried, must not be \c NULL - * \param ext_type Extension type being queried for, must be a valid - * extension type. Must be one of the MBEDTLS_X509_EXT_XXX - * values - * - * \return 0 if the given extension type is not present, - * non-zero otherwise - */ -static inline int mbedtls_x509_crt_has_ext_type(const mbedtls_x509_crt *ctx, - int ext_type) -{ - return ctx->MBEDTLS_PRIVATE(ext_types) & ext_type; -} - -/** \} name Structures and functions for parsing and writing X.509 certificates */ - -#if defined(MBEDTLS_X509_CRT_WRITE_C) -/** - * \brief Initialize a CRT writing context - * - * \param ctx CRT context to initialize - */ -void mbedtls_x509write_crt_init(mbedtls_x509write_cert *ctx); - -/** - * \brief Set the version for a Certificate - * Default: MBEDTLS_X509_CRT_VERSION_3 - * - * \param ctx CRT context to use - * \param version version to set (MBEDTLS_X509_CRT_VERSION_1, MBEDTLS_X509_CRT_VERSION_2 or - * MBEDTLS_X509_CRT_VERSION_3) - */ -void mbedtls_x509write_crt_set_version(mbedtls_x509write_cert *ctx, int version); - -#if defined(MBEDTLS_BIGNUM_C) && !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Set the serial number for a Certificate. - * - * \deprecated This function is deprecated and will be removed in a - * future version of the library. Please use - * mbedtls_x509write_crt_set_serial_raw() instead. - * - * \note Even though the MBEDTLS_BIGNUM_C guard looks redundant since - * X509 depends on PK and PK depends on BIGNUM, this emphasizes - * a direct dependency between X509 and BIGNUM which is going - * to be deprecated in the future. - * - * \param ctx CRT context to use - * \param serial serial number to set - * - * \return 0 if successful - */ -int MBEDTLS_DEPRECATED mbedtls_x509write_crt_set_serial( - mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial); -#endif // MBEDTLS_BIGNUM_C && !MBEDTLS_DEPRECATED_REMOVED - -/** - * \brief Set the serial number for a Certificate. - * - * \param ctx CRT context to use - * \param serial A raw array of bytes containing the serial number in big - * endian format - * \param serial_len Length of valid bytes (expressed in bytes) in \p serial - * input buffer - * - * \return 0 if successful, or - * MBEDTLS_ERR_X509_BAD_INPUT_DATA if the provided input buffer - * is too big (longer than MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN) - */ -int mbedtls_x509write_crt_set_serial_raw(mbedtls_x509write_cert *ctx, - unsigned char *serial, size_t serial_len); - -/** - * \brief Set the validity period for a Certificate - * Timestamps should be in string format for UTC timezone - * i.e. "YYYYMMDDhhmmss" - * e.g. "20131231235959" for December 31st 2013 - * at 23:59:59 - * - * \param ctx CRT context to use - * \param not_before not_before timestamp - * \param not_after not_after timestamp - * - * \return 0 if timestamp was parsed successfully, or - * a specific error code - */ -int mbedtls_x509write_crt_set_validity(mbedtls_x509write_cert *ctx, const char *not_before, - const char *not_after); - -/** - * \brief Set the issuer name for a Certificate - * Issuer names should contain a comma-separated list - * of OID types and values: - * e.g. "C=UK,O=ARM,CN=Mbed TLS CA" - * - * \param ctx CRT context to use - * \param issuer_name issuer name to set - * - * \return 0 if issuer name was parsed successfully, or - * a specific error code - */ -int mbedtls_x509write_crt_set_issuer_name(mbedtls_x509write_cert *ctx, - const char *issuer_name); - -/** - * \brief Set the subject name for a Certificate - * Subject names should contain a comma-separated list - * of OID types and values: - * e.g. "C=UK,O=ARM,CN=Mbed TLS Server 1" - * - * \param ctx CRT context to use - * \param subject_name subject name to set - * - * \return 0 if subject name was parsed successfully, or - * a specific error code - */ -int mbedtls_x509write_crt_set_subject_name(mbedtls_x509write_cert *ctx, - const char *subject_name); - -/** - * \brief Set the subject public key for the certificate - * - * \param ctx CRT context to use - * \param key public key to include - */ -void mbedtls_x509write_crt_set_subject_key(mbedtls_x509write_cert *ctx, mbedtls_pk_context *key); - -/** - * \brief Set the issuer key used for signing the certificate - * - * \param ctx CRT context to use - * \param key private key to sign with - */ -void mbedtls_x509write_crt_set_issuer_key(mbedtls_x509write_cert *ctx, mbedtls_pk_context *key); - -/** - * \brief Set the MD algorithm to use for the signature - * (e.g. MBEDTLS_MD_SHA1) - * - * \param ctx CRT context to use - * \param md_alg MD algorithm to use - */ -void mbedtls_x509write_crt_set_md_alg(mbedtls_x509write_cert *ctx, mbedtls_md_type_t md_alg); - -/** - * \brief Generic function to add to or replace an extension in the - * CRT - * - * \param ctx CRT context to use - * \param oid OID of the extension - * \param oid_len length of the OID - * \param critical if the extension is critical (per the RFC's definition) - * \param val value of the extension OCTET STRING - * \param val_len length of the value data - * - * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_extension(mbedtls_x509write_cert *ctx, - const char *oid, size_t oid_len, - int critical, - const unsigned char *val, size_t val_len); - -/** - * \brief Set the basicConstraints extension for a CRT - * - * \param ctx CRT context to use - * \param is_ca is this a CA certificate - * \param max_pathlen maximum length of certificate chains below this - * certificate (only for CA certificates, -1 is - * unlimited) - * - * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_basic_constraints(mbedtls_x509write_cert *ctx, - int is_ca, int max_pathlen); - -#if defined(MBEDTLS_MD_CAN_SHA1) -/** - * \brief Set the subjectKeyIdentifier extension for a CRT - * Requires that mbedtls_x509write_crt_set_subject_key() has been - * called before - * - * \param ctx CRT context to use - * - * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_subject_key_identifier(mbedtls_x509write_cert *ctx); - -/** - * \brief Set the authorityKeyIdentifier extension for a CRT - * Requires that mbedtls_x509write_crt_set_issuer_key() has been - * called before - * - * \param ctx CRT context to use - * - * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_authority_key_identifier(mbedtls_x509write_cert *ctx); -#endif /* MBEDTLS_MD_CAN_SHA1 */ - -/** - * \brief Set the Key Usage Extension flags - * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) - * - * \param ctx CRT context to use - * \param key_usage key usage flags to set - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_key_usage(mbedtls_x509write_cert *ctx, - unsigned int key_usage); - -/** - * \brief Set the Extended Key Usage Extension - * (e.g. MBEDTLS_OID_SERVER_AUTH) - * - * \param ctx CRT context to use - * \param exts extended key usage extensions to set, a sequence of - * MBEDTLS_ASN1_OID objects - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_ext_key_usage(mbedtls_x509write_cert *ctx, - const mbedtls_asn1_sequence *exts); - -/** - * \brief Set the Netscape Cert Type flags - * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) - * - * \param ctx CRT context to use - * \param ns_cert_type Netscape Cert Type flags to set - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_crt_set_ns_cert_type(mbedtls_x509write_cert *ctx, - unsigned char ns_cert_type); - -/** - * \brief Free the contents of a CRT write context - * - * \param ctx CRT context to free - */ -void mbedtls_x509write_crt_free(mbedtls_x509write_cert *ctx); - -/** - * \brief Write a built up certificate to a X509 DER structure - * Note: data is written at the end of the buffer! Use the - * return value to determine where you should start - * using the buffer - * - * \param ctx certificate to write away - * \param buf buffer to write to - * \param size size of the buffer - * \param f_rng RNG function. This must not be \c NULL. - * \param p_rng RNG parameter - * - * \return length of data written if successful, or a specific - * error code - * - * \note \p f_rng is used for the signature operation. - */ -int mbedtls_x509write_crt_der(mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#if defined(MBEDTLS_PEM_WRITE_C) -/** - * \brief Write a built up certificate to a X509 PEM string - * - * \param ctx certificate to write away - * \param buf buffer to write to - * \param size size of the buffer - * \param f_rng RNG function. This must not be \c NULL. - * \param p_rng RNG parameter - * - * \return 0 if successful, or a specific error code - * - * \note \p f_rng is used for the signature operation. - */ -int mbedtls_x509write_crt_pem(mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); -#endif /* MBEDTLS_PEM_WRITE_C */ -#endif /* MBEDTLS_X509_CRT_WRITE_C */ - -/** \} addtogroup x509_module */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_x509_crt.h */ +/** + * \file x509_crt.h + * + * \brief X.509 certificate parsing and writing + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_X509_CRT_H +#define MBEDTLS_X509_CRT_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/x509.h" +#include "mbedtls/x509_crl.h" +#include "mbedtls/bignum.h" + +/** + * \addtogroup x509_module + * \{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name Structures and functions for parsing and writing X.509 certificates + * \{ + */ + +/** + * Container for an X.509 certificate. The certificate may be chained. + * + * Some fields of this structure are publicly readable. Do not modify + * them except via Mbed TLS library functions: the effect of modifying + * those fields or the data that those fields points to is unspecified. + */ +typedef struct mbedtls_x509_crt { + int MBEDTLS_PRIVATE(own_buffer); /**< Indicates if \c raw is owned + * by the structure or not. */ + mbedtls_x509_buf raw; /**< The raw certificate data (DER). */ + mbedtls_x509_buf tbs; /**< The raw certificate body (DER). The part that is To Be Signed. */ + + int version; /**< The X.509 version. (1=v1, 2=v2, 3=v3) */ + mbedtls_x509_buf serial; /**< Unique id for certificate issued by a specific CA. */ + mbedtls_x509_buf sig_oid; /**< Signature algorithm, e.g. sha1RSA */ + + mbedtls_x509_buf issuer_raw; /**< The raw issuer data (DER). Used for quick comparison. */ + mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). Used for quick comparison. */ + + mbedtls_x509_name issuer; /**< The parsed issuer data (named information object). */ + mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ + + mbedtls_x509_time valid_from; /**< Start time of certificate validity. */ + mbedtls_x509_time valid_to; /**< End time of certificate validity. */ + + mbedtls_x509_buf pk_raw; + mbedtls_pk_context pk; /**< Container for the public key context. */ + + mbedtls_x509_buf issuer_id; /**< Optional X.509 v2/v3 issuer unique identifier. */ + mbedtls_x509_buf subject_id; /**< Optional X.509 v2/v3 subject unique identifier. */ + mbedtls_x509_buf v3_ext; /**< Optional X.509 v3 extensions. */ + mbedtls_x509_sequence subject_alt_names; /**< Optional list of raw entries of Subject Alternative Names extension. These can be later parsed by mbedtls_x509_parse_subject_alt_name. */ + mbedtls_x509_buf subject_key_id; /**< Optional X.509 v3 extension subject key identifier. */ + mbedtls_x509_authority authority_key_id; /**< Optional X.509 v3 extension authority key identifier. */ + + mbedtls_x509_sequence certificate_policies; /**< Optional list of certificate policies (Only anyPolicy is printed and enforced, however the rest of the policies are still listed). */ + + int MBEDTLS_PRIVATE(ext_types); /**< Bit string containing detected and parsed extensions */ + int MBEDTLS_PRIVATE(ca_istrue); /**< Optional Basic Constraint extension value: 1 if this certificate belongs to a CA, 0 otherwise. */ + int MBEDTLS_PRIVATE(max_pathlen); /**< Optional Basic Constraint extension value: The maximum path length to the root certificate. Path length is 1 higher than RFC 5280 'meaning', so 1+ */ + + unsigned int MBEDTLS_PRIVATE(key_usage); /**< Optional key usage extension value: See the values in x509.h */ + + mbedtls_x509_sequence ext_key_usage; /**< Optional list of extended key usage OIDs. */ + + unsigned char MBEDTLS_PRIVATE(ns_cert_type); /**< Optional Netscape certificate type extension value: See the values in x509.h */ + + mbedtls_x509_buf MBEDTLS_PRIVATE(sig); /**< Signature: hash of the tbs part signed with the private key. */ + mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ + + /** Next certificate in the linked list that constitutes the CA chain. + * \p NULL indicates the end of the list. + * Do not modify this field directly. */ + struct mbedtls_x509_crt *next; +} +mbedtls_x509_crt; + +/** + * Build flag from an algorithm/curve identifier (pk, md, ecp) + * Since 0 is always XXX_NONE, ignore it. + */ +#define MBEDTLS_X509_ID_FLAG(id) (1 << ((id) - 1)) + +/** + * Security profile for certificate verification. + * + * All lists are bitfields, built by ORing flags from MBEDTLS_X509_ID_FLAG(). + * + * The fields of this structure are part of the public API and can be + * manipulated directly by applications. Future versions of the library may + * add extra fields or reorder existing fields. + * + * You can create custom profiles by starting from a copy of + * an existing profile, such as mbedtls_x509_crt_profile_default or + * mbedtls_x509_ctr_profile_none and then tune it to your needs. + * + * For example to allow SHA-224 in addition to the default: + * + * mbedtls_x509_crt_profile my_profile = mbedtls_x509_crt_profile_default; + * my_profile.allowed_mds |= MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA224 ); + * + * Or to allow only RSA-3072+ with SHA-256: + * + * mbedtls_x509_crt_profile my_profile = mbedtls_x509_crt_profile_none; + * my_profile.allowed_mds = MBEDTLS_X509_ID_FLAG( MBEDTLS_MD_SHA256 ); + * my_profile.allowed_pks = MBEDTLS_X509_ID_FLAG( MBEDTLS_PK_RSA ); + * my_profile.rsa_min_bitlen = 3072; + */ +typedef struct mbedtls_x509_crt_profile { + uint32_t allowed_mds; /**< MDs for signatures */ + uint32_t allowed_pks; /**< PK algs for public keys; + * this applies to all certificates + * in the provided chain. */ + uint32_t allowed_curves; /**< Elliptic curves for ECDSA */ + uint32_t rsa_min_bitlen; /**< Minimum size for RSA keys */ +} +mbedtls_x509_crt_profile; + +#define MBEDTLS_X509_CRT_VERSION_1 0 +#define MBEDTLS_X509_CRT_VERSION_2 1 +#define MBEDTLS_X509_CRT_VERSION_3 2 + +#define MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN 20 +#define MBEDTLS_X509_RFC5280_UTC_TIME_LEN 15 + +#if !defined(MBEDTLS_X509_MAX_FILE_PATH_LEN) +#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 +#endif + +/* This macro unfolds to the concatenation of macro invocations + * X509_CRT_ERROR_INFO( error code, + * error code as string, + * human readable description ) + * where X509_CRT_ERROR_INFO is defined by the user. + * See x509_crt.c for an example of how to use this. */ +#define MBEDTLS_X509_CRT_ERROR_INFO_LIST \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_EXPIRED, \ + "MBEDTLS_X509_BADCERT_EXPIRED", \ + "The certificate validity has expired") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_REVOKED, \ + "MBEDTLS_X509_BADCERT_REVOKED", \ + "The certificate has been revoked (is on a CRL)") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_CN_MISMATCH, \ + "MBEDTLS_X509_BADCERT_CN_MISMATCH", \ + "The certificate Common Name (CN) does not match with the expected CN") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_NOT_TRUSTED, \ + "MBEDTLS_X509_BADCERT_NOT_TRUSTED", \ + "The certificate is not correctly signed by the trusted CA") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_NOT_TRUSTED, \ + "MBEDTLS_X509_BADCRL_NOT_TRUSTED", \ + "The CRL is not correctly signed by the trusted CA") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_EXPIRED, \ + "MBEDTLS_X509_BADCRL_EXPIRED", \ + "The CRL is expired") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_MISSING, \ + "MBEDTLS_X509_BADCERT_MISSING", \ + "Certificate was missing") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_SKIP_VERIFY, \ + "MBEDTLS_X509_BADCERT_SKIP_VERIFY", \ + "Certificate verification was skipped") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_OTHER, \ + "MBEDTLS_X509_BADCERT_OTHER", \ + "Other reason (can be used by verify callback)") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_FUTURE, \ + "MBEDTLS_X509_BADCERT_FUTURE", \ + "The certificate validity starts in the future") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_FUTURE, \ + "MBEDTLS_X509_BADCRL_FUTURE", \ + "The CRL is from the future") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_KEY_USAGE, \ + "MBEDTLS_X509_BADCERT_KEY_USAGE", \ + "Usage does not match the keyUsage extension") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_EXT_KEY_USAGE, \ + "MBEDTLS_X509_BADCERT_EXT_KEY_USAGE", \ + "Usage does not match the extendedKeyUsage extension") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_NS_CERT_TYPE, \ + "MBEDTLS_X509_BADCERT_NS_CERT_TYPE", \ + "Usage does not match the nsCertType extension") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_MD, \ + "MBEDTLS_X509_BADCERT_BAD_MD", \ + "The certificate is signed with an unacceptable hash.") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_PK, \ + "MBEDTLS_X509_BADCERT_BAD_PK", \ + "The certificate is signed with an unacceptable PK alg (eg RSA vs ECDSA).") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCERT_BAD_KEY, \ + "MBEDTLS_X509_BADCERT_BAD_KEY", \ + "The certificate is signed with an unacceptable key (eg bad curve, RSA too short).") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_MD, \ + "MBEDTLS_X509_BADCRL_BAD_MD", \ + "The CRL is signed with an unacceptable hash.") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_PK, \ + "MBEDTLS_X509_BADCRL_BAD_PK", \ + "The CRL is signed with an unacceptable PK alg (eg RSA vs ECDSA).") \ + X509_CRT_ERROR_INFO(MBEDTLS_X509_BADCRL_BAD_KEY, \ + "MBEDTLS_X509_BADCRL_BAD_KEY", \ + "The CRL is signed with an unacceptable key (eg bad curve, RSA too short).") + +/** + * Container for writing a certificate (CRT) + */ +typedef struct mbedtls_x509write_cert { + int MBEDTLS_PRIVATE(version); + unsigned char MBEDTLS_PRIVATE(serial)[MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN]; + size_t MBEDTLS_PRIVATE(serial_len); + mbedtls_pk_context *MBEDTLS_PRIVATE(subject_key); + mbedtls_pk_context *MBEDTLS_PRIVATE(issuer_key); + mbedtls_asn1_named_data *MBEDTLS_PRIVATE(subject); + mbedtls_asn1_named_data *MBEDTLS_PRIVATE(issuer); + mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); + char MBEDTLS_PRIVATE(not_before)[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; + char MBEDTLS_PRIVATE(not_after)[MBEDTLS_X509_RFC5280_UTC_TIME_LEN + 1]; + mbedtls_asn1_named_data *MBEDTLS_PRIVATE(extensions); +} +mbedtls_x509write_cert; + +/** + * \brief Set Subject Alternative Name + * + * \param ctx Certificate context to use + * \param san_list List of SAN values + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + * + * \note "dnsName", "uniformResourceIdentifier", "IP address", + * "otherName", and "DirectoryName", as defined in RFC 5280, + * are supported. + */ +int mbedtls_x509write_crt_set_subject_alternative_name(mbedtls_x509write_cert *ctx, + const mbedtls_x509_san_list *san_list); + +/** + * Item in a verification chain: cert and flags for it + */ +typedef struct { + mbedtls_x509_crt *MBEDTLS_PRIVATE(crt); + uint32_t MBEDTLS_PRIVATE(flags); +} mbedtls_x509_crt_verify_chain_item; + +/** + * Max size of verification chain: end-entity + intermediates + trusted root + */ +#define MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE (MBEDTLS_X509_MAX_INTERMEDIATE_CA + 2) + +/** + * Verification chain as built by \c mbedtls_crt_verify_chain() + */ +typedef struct { + mbedtls_x509_crt_verify_chain_item MBEDTLS_PRIVATE(items)[MBEDTLS_X509_MAX_VERIFY_CHAIN_SIZE]; + unsigned MBEDTLS_PRIVATE(len); + +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) + /* This stores the list of potential trusted signers obtained from + * the CA callback used for the CRT verification, if configured. + * We must track it somewhere because the callback passes its + * ownership to the caller. */ + mbedtls_x509_crt *MBEDTLS_PRIVATE(trust_ca_cb_result); +#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ +} mbedtls_x509_crt_verify_chain; + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + +/** + * \brief Context for resuming X.509 verify operations + */ +typedef struct { + /* for check_signature() */ + mbedtls_pk_restart_ctx MBEDTLS_PRIVATE(pk); + + /* for find_parent_in() */ + mbedtls_x509_crt *MBEDTLS_PRIVATE(parent); /* non-null iff parent_in in progress */ + mbedtls_x509_crt *MBEDTLS_PRIVATE(fallback_parent); + int MBEDTLS_PRIVATE(fallback_signature_is_good); + + /* for find_parent() */ + int MBEDTLS_PRIVATE(parent_is_trusted); /* -1 if find_parent is not in progress */ + + /* for verify_chain() */ + enum { + x509_crt_rs_none, + x509_crt_rs_find_parent, + } MBEDTLS_PRIVATE(in_progress); /* none if no operation is in progress */ + int MBEDTLS_PRIVATE(self_cnt); + mbedtls_x509_crt_verify_chain MBEDTLS_PRIVATE(ver_chain); + +} mbedtls_x509_crt_restart_ctx; + +#else /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +/* Now we can declare functions that take a pointer to that */ +typedef void mbedtls_x509_crt_restart_ctx; + +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/** + * Default security profile. Should provide a good balance between security + * and compatibility with current deployments. + * + * This profile permits: + * - SHA2 hashes with at least 256 bits: SHA-256, SHA-384, SHA-512. + * - Elliptic curves with 255 bits and above except secp256k1. + * - RSA with 2048 bits and above. + * + * New minor versions of Mbed TLS may extend this profile, for example if + * new algorithms are added to the library. New minor versions of Mbed TLS will + * not reduce this profile unless serious security concerns require it. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_default; + +/** + * Expected next default profile. Recommended for new deployments. + * Currently targets a 128-bit security level, except for allowing RSA-2048. + * This profile may change at any time. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_next; + +/** + * NSA Suite B profile. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_suiteb; + +/** + * Empty profile that allows nothing. Useful as a basis for constructing + * custom profiles. + */ +extern const mbedtls_x509_crt_profile mbedtls_x509_crt_profile_none; + +/** + * \brief Parse a single DER formatted certificate and add it + * to the end of the provided chained list. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain The pointer to the start of the CRT chain to attach to. + * When parsing the first CRT in a chain, this should point + * to an instance of ::mbedtls_x509_crt initialized through + * mbedtls_x509_crt_init(). + * \param buf The buffer holding the DER encoded certificate. + * \param buflen The size in Bytes of \p buf. + * + * \note This function makes an internal copy of the CRT buffer + * \p buf. In particular, \p buf may be destroyed or reused + * after this call returns. To avoid duplicating the CRT + * buffer (at the cost of stricter lifetime constraints), + * use mbedtls_x509_crt_parse_der_nocopy() instead. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_x509_crt_parse_der(mbedtls_x509_crt *chain, + const unsigned char *buf, + size_t buflen); + +/** + * \brief The type of certificate extension callbacks. + * + * Callbacks of this type are passed to and used by the + * mbedtls_x509_crt_parse_der_with_ext_cb() routine when + * it encounters either an unsupported extension or a + * "certificate policies" extension containing any + * unsupported certificate policies. + * Future versions of the library may invoke the callback + * in other cases, if and when the need arises. + * + * \param p_ctx An opaque context passed to the callback. + * \param crt The certificate being parsed. + * \param oid The OID of the extension. + * \param critical Whether the extension is critical. + * \param p Pointer to the start of the extension value + * (the content of the OCTET STRING). + * \param end End of extension value. + * + * \note The callback must fail and return a negative error code + * if it can not parse or does not support the extension. + * When the callback fails to parse a critical extension + * mbedtls_x509_crt_parse_der_with_ext_cb() also fails. + * When the callback fails to parse a non critical extension + * mbedtls_x509_crt_parse_der_with_ext_cb() simply skips + * the extension and continues parsing. + * + * \return \c 0 on success. + * \return A negative error code on failure. + */ +typedef int (*mbedtls_x509_crt_ext_cb_t)(void *p_ctx, + mbedtls_x509_crt const *crt, + mbedtls_x509_buf const *oid, + int critical, + const unsigned char *p, + const unsigned char *end); + +/** + * \brief Parse a single DER formatted certificate and add it + * to the end of the provided chained list. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain The pointer to the start of the CRT chain to attach to. + * When parsing the first CRT in a chain, this should point + * to an instance of ::mbedtls_x509_crt initialized through + * mbedtls_x509_crt_init(). + * \param buf The buffer holding the DER encoded certificate. + * \param buflen The size in Bytes of \p buf. + * \param make_copy When not zero this function makes an internal copy of the + * CRT buffer \p buf. In particular, \p buf may be destroyed + * or reused after this call returns. + * When zero this function avoids duplicating the CRT buffer + * by taking temporary ownership thereof until the CRT + * is destroyed (like mbedtls_x509_crt_parse_der_nocopy()) + * \param cb A callback invoked for every unsupported certificate + * extension. + * \param p_ctx An opaque context passed to the callback. + * + * \note This call is functionally equivalent to + * mbedtls_x509_crt_parse_der(), and/or + * mbedtls_x509_crt_parse_der_nocopy() + * but it calls the callback with every unsupported + * certificate extension and additionally the + * "certificate policies" extension if it contains any + * unsupported certificate policies. + * The callback must return a negative error code if it + * does not know how to handle such an extension. + * When the callback fails to parse a critical extension + * mbedtls_x509_crt_parse_der_with_ext_cb() also fails. + * When the callback fails to parse a non critical extension + * mbedtls_x509_crt_parse_der_with_ext_cb() simply skips + * the extension and continues parsing. + * Future versions of the library may invoke the callback + * in other cases, if and when the need arises. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_x509_crt_parse_der_with_ext_cb(mbedtls_x509_crt *chain, + const unsigned char *buf, + size_t buflen, + int make_copy, + mbedtls_x509_crt_ext_cb_t cb, + void *p_ctx); + +/** + * \brief Parse a single DER formatted certificate and add it + * to the end of the provided chained list. This is a + * variant of mbedtls_x509_crt_parse_der() which takes + * temporary ownership of the CRT buffer until the CRT + * is destroyed. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain The pointer to the start of the CRT chain to attach to. + * When parsing the first CRT in a chain, this should point + * to an instance of ::mbedtls_x509_crt initialized through + * mbedtls_x509_crt_init(). + * \param buf The address of the readable buffer holding the DER encoded + * certificate to use. On success, this buffer must be + * retained and not be changed for the lifetime of the + * CRT chain \p chain, that is, until \p chain is destroyed + * through a call to mbedtls_x509_crt_free(). + * \param buflen The size in Bytes of \p buf. + * + * \note This call is functionally equivalent to + * mbedtls_x509_crt_parse_der(), but it avoids creating a + * copy of the input buffer at the cost of stronger lifetime + * constraints. This is useful in constrained environments + * where duplication of the CRT cannot be tolerated. + * + * \return \c 0 if successful. + * \return A negative error code on failure. + */ +int mbedtls_x509_crt_parse_der_nocopy(mbedtls_x509_crt *chain, + const unsigned char *buf, + size_t buflen); + +/** + * \brief Parse one DER-encoded or one or more concatenated PEM-encoded + * certificates and add them to the chained list. + * + * For CRTs in PEM encoding, the function parses permissively: + * if at least one certificate can be parsed, the function + * returns the number of certificates for which parsing failed + * (hence \c 0 if all certificates were parsed successfully). + * If no certificate could be parsed, the function returns + * the first (negative) error encountered during parsing. + * + * PEM encoded certificates may be interleaved by other data + * such as human readable descriptions of their content, as + * long as the certificates are enclosed in the PEM specific + * '-----{BEGIN/END} CERTIFICATE-----' delimiters. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain The chain to which to add the parsed certificates. + * \param buf The buffer holding the certificate data in PEM or DER format. + * For certificates in PEM encoding, this may be a concatenation + * of multiple certificates; for DER encoding, the buffer must + * comprise exactly one certificate. + * \param buflen The size of \p buf, including the terminating \c NULL byte + * in case of PEM encoded data. + * + * \return \c 0 if all certificates were parsed successfully. + * \return The (positive) number of certificates that couldn't + * be parsed if parsing was partly successful (see above). + * \return A negative X509 or PEM error code otherwise. + * + */ +int mbedtls_x509_crt_parse(mbedtls_x509_crt *chain, const unsigned char *buf, size_t buflen); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load one or more certificates and add them + * to the chained list. Parses permissively. If some + * certificates can be parsed, the result is the number + * of failed certificates it encountered. If none complete + * correctly, the first error is returned. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param chain points to the start of the chain + * \param path filename to read the certificates from + * + * \return 0 if all certificates parsed successfully, a positive number + * if partly successful or a specific X509 or PEM error code + */ +int mbedtls_x509_crt_parse_file(mbedtls_x509_crt *chain, const char *path); + +/** + * \brief Load one or more certificate files from a path and add them + * to the chained list. Parses permissively. If some + * certificates can be parsed, the result is the number + * of failed certificates it encountered. If none complete + * correctly, the first error is returned. + * + * \param chain points to the start of the chain + * \param path directory / folder to read the certificate files from + * + * \return 0 if all certificates parsed successfully, a positive number + * if partly successful or a specific X509 or PEM error code + */ +int mbedtls_x509_crt_parse_path(mbedtls_x509_crt *chain, const char *path); + +#endif /* MBEDTLS_FS_IO */ + +#if !defined(MBEDTLS_X509_REMOVE_INFO) +/** + * \brief Returns an informational string about the + * certificate. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param crt The X509 certificate to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crt_info(char *buf, size_t size, const char *prefix, + const mbedtls_x509_crt *crt); + +/** + * \brief Returns an informational string about the + * verification status of a certificate. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param flags Verification flags created by mbedtls_x509_crt_verify() + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_crt_verify_info(char *buf, size_t size, const char *prefix, + uint32_t flags); +#endif /* !MBEDTLS_X509_REMOVE_INFO */ + +/** + * \brief Verify a chain of certificates. + * + * The verify callback is a user-supplied callback that + * can clear / modify / add flags for a certificate. If set, + * the verification callback is called for each + * certificate in the chain (from the trust-ca down to the + * presented crt). The parameters for the callback are: + * (void *parameter, mbedtls_x509_crt *crt, int certificate_depth, + * int *flags). With the flags representing current flags for + * that specific certificate and the certificate depth from + * the bottom (Peer cert depth = 0). + * + * All flags left after returning from the callback + * are also returned to the application. The function should + * return 0 for anything (including invalid certificates) + * other than fatal error, as a non-zero return code + * immediately aborts the verification process. For fatal + * errors, a specific error code should be used (different + * from MBEDTLS_ERR_X509_CERT_VERIFY_FAILED which should not + * be returned at this point), or MBEDTLS_ERR_X509_FATAL_ERROR + * can be used if no better code is available. + * + * \note In case verification failed, the results can be displayed + * using \c mbedtls_x509_crt_verify_info() + * + * \note Same as \c mbedtls_x509_crt_verify_with_profile() with the + * default security profile. + * + * \note It is your responsibility to provide up-to-date CRLs for + * all trusted CAs. If no CRL is provided for the CA that was + * used to sign the certificate, CRL verification is skipped + * silently, that is *without* setting any flag. + * + * \note The \c trust_ca list can contain two types of certificates: + * (1) those of trusted root CAs, so that certificates + * chaining up to those CAs will be trusted, and (2) + * self-signed end-entity certificates to be trusted (for + * specific peers you know) - in that case, the self-signed + * certificate doesn't need to have the CA bit set. + * + * \param crt The certificate chain to be verified. + * \param trust_ca The list of trusted CAs. + * \param ca_crl The list of CRLs for trusted CAs. + * \param cn The expected Common Name. This will be checked to be + * present in the certificate's subjectAltNames extension or, + * if this extension is absent, as a CN component in its + * Subject name. DNS names and IP addresses are fully + * supported, while the URI subtype is partially supported: + * only exact matching, without any normalization procedures + * described in 7.4 of RFC5280, will result in a positive + * URI verification. + * This may be \c NULL if the CN need not be verified. + * \param flags The address at which to store the result of the verification. + * If the verification couldn't be completed, the flag value is + * set to (uint32_t) -1. + * \param f_vrfy The verification callback to use. See the documentation + * of mbedtls_x509_crt_verify() for more information. + * \param p_vrfy The context to be passed to \p f_vrfy. + * + * \return \c 0 if the chain is valid with respect to the + * passed CN, CAs, CRLs and security profile. + * \return #MBEDTLS_ERR_X509_CERT_VERIFY_FAILED in case the + * certificate chain verification failed. In this case, + * \c *flags will have one or more + * \c MBEDTLS_X509_BADCERT_XXX or \c MBEDTLS_X509_BADCRL_XXX + * flags set. + * \return Another negative error code in case of a fatal error + * encountered during the verification process. + */ +int mbedtls_x509_crt_verify(mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy); + +/** + * \brief Verify a chain of certificates with respect to + * a configurable security profile. + * + * \note Same as \c mbedtls_x509_crt_verify(), but with explicit + * security profile. + * + * \note The restrictions on keys (RSA minimum size, allowed curves + * for ECDSA) apply to all certificates: trusted root, + * intermediate CAs if any, and end entity certificate. + * + * \param crt The certificate chain to be verified. + * \param trust_ca The list of trusted CAs. + * \param ca_crl The list of CRLs for trusted CAs. + * \param profile The security profile to use for the verification. + * \param cn The expected Common Name. This may be \c NULL if the + * CN need not be verified. + * \param flags The address at which to store the result of the verification. + * If the verification couldn't be completed, the flag value is + * set to (uint32_t) -1. + * \param f_vrfy The verification callback to use. See the documentation + * of mbedtls_x509_crt_verify() for more information. + * \param p_vrfy The context to be passed to \p f_vrfy. + * + * \return \c 0 if the chain is valid with respect to the + * passed CN, CAs, CRLs and security profile. + * \return #MBEDTLS_ERR_X509_CERT_VERIFY_FAILED in case the + * certificate chain verification failed. In this case, + * \c *flags will have one or more + * \c MBEDTLS_X509_BADCERT_XXX or \c MBEDTLS_X509_BADCRL_XXX + * flags set. + * \return Another negative error code in case of a fatal error + * encountered during the verification process. + */ +int mbedtls_x509_crt_verify_with_profile(mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy); + +/** + * \brief Restartable version of \c mbedtls_crt_verify_with_profile() + * + * \note Performs the same job as \c mbedtls_crt_verify_with_profile() + * but can return early and restart according to the limit + * set with \c mbedtls_ecp_set_max_ops() to reduce blocking. + * + * \param crt The certificate chain to be verified. + * \param trust_ca The list of trusted CAs. + * \param ca_crl The list of CRLs for trusted CAs. + * \param profile The security profile to use for the verification. + * \param cn The expected Common Name. This may be \c NULL if the + * CN need not be verified. + * \param flags The address at which to store the result of the verification. + * If the verification couldn't be completed, the flag value is + * set to (uint32_t) -1. + * \param f_vrfy The verification callback to use. See the documentation + * of mbedtls_x509_crt_verify() for more information. + * \param p_vrfy The context to be passed to \p f_vrfy. + * \param rs_ctx The restart context to use. This may be set to \c NULL + * to disable restartable ECC. + * + * \return See \c mbedtls_crt_verify_with_profile(), or + * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of + * operations was reached: see \c mbedtls_ecp_set_max_ops(). + */ +int mbedtls_x509_crt_verify_restartable(mbedtls_x509_crt *crt, + mbedtls_x509_crt *trust_ca, + mbedtls_x509_crl *ca_crl, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy, + mbedtls_x509_crt_restart_ctx *rs_ctx); + +/** + * \brief The type of trusted certificate callbacks. + * + * Callbacks of this type are passed to and used by the CRT + * verification routine mbedtls_x509_crt_verify_with_ca_cb() + * when looking for trusted signers of a given certificate. + * + * On success, the callback returns a list of trusted + * certificates to be considered as potential signers + * for the input certificate. + * + * \param p_ctx An opaque context passed to the callback. + * \param child The certificate for which to search a potential signer. + * This will point to a readable certificate. + * \param candidate_cas The address at which to store the address of the first + * entry in the generated linked list of candidate signers. + * This will not be \c NULL. + * + * \note The callback must only return a non-zero value on a + * fatal error. If, in contrast, the search for a potential + * signer completes without a single candidate, the + * callback must return \c 0 and set \c *candidate_cas + * to \c NULL. + * + * \return \c 0 on success. In this case, \c *candidate_cas points + * to a heap-allocated linked list of instances of + * ::mbedtls_x509_crt, and ownership of this list is passed + * to the caller. + * \return A negative error code on failure. + */ +typedef int (*mbedtls_x509_crt_ca_cb_t)(void *p_ctx, + mbedtls_x509_crt const *child, + mbedtls_x509_crt **candidate_cas); + +#if defined(MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK) +/** + * \brief Version of \c mbedtls_x509_crt_verify_with_profile() which + * uses a callback to acquire the list of trusted CA + * certificates. + * + * \param crt The certificate chain to be verified. + * \param f_ca_cb The callback to be used to query for potential signers + * of a given child certificate. See the documentation of + * ::mbedtls_x509_crt_ca_cb_t for more information. + * \param p_ca_cb The opaque context to be passed to \p f_ca_cb. + * \param profile The security profile for the verification. + * \param cn The expected Common Name. This may be \c NULL if the + * CN need not be verified. + * \param flags The address at which to store the result of the verification. + * If the verification couldn't be completed, the flag value is + * set to (uint32_t) -1. + * \param f_vrfy The verification callback to use. See the documentation + * of mbedtls_x509_crt_verify() for more information. + * \param p_vrfy The context to be passed to \p f_vrfy. + * + * \return See \c mbedtls_crt_verify_with_profile(). + */ +int mbedtls_x509_crt_verify_with_ca_cb(mbedtls_x509_crt *crt, + mbedtls_x509_crt_ca_cb_t f_ca_cb, + void *p_ca_cb, + const mbedtls_x509_crt_profile *profile, + const char *cn, uint32_t *flags, + int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), + void *p_vrfy); + +#endif /* MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK */ + +/** + * \brief Check usage of certificate against keyUsage extension. + * + * \param crt Leaf certificate used. + * \param usage Intended usage(s) (eg MBEDTLS_X509_KU_KEY_ENCIPHERMENT + * before using the certificate to perform an RSA key + * exchange). + * + * \note Except for decipherOnly and encipherOnly, a bit set in the + * usage argument means this bit MUST be set in the + * certificate. For decipherOnly and encipherOnly, it means + * that bit MAY be set. + * + * \return 0 is these uses of the certificate are allowed, + * MBEDTLS_ERR_X509_BAD_INPUT_DATA if the keyUsage extension + * is present but does not match the usage argument. + * + * \note You should only call this function on leaf certificates, on + * (intermediate) CAs the keyUsage extension is automatically + * checked by \c mbedtls_x509_crt_verify(). + */ +int mbedtls_x509_crt_check_key_usage(const mbedtls_x509_crt *crt, + unsigned int usage); + +/** + * \brief Check usage of certificate against extendedKeyUsage. + * + * \param crt Leaf certificate used. + * \param usage_oid Intended usage (eg MBEDTLS_OID_SERVER_AUTH or + * MBEDTLS_OID_CLIENT_AUTH). + * \param usage_len Length of usage_oid (eg given by MBEDTLS_OID_SIZE()). + * + * \return 0 if this use of the certificate is allowed, + * MBEDTLS_ERR_X509_BAD_INPUT_DATA if not. + * + * \note Usually only makes sense on leaf certificates. + */ +int mbedtls_x509_crt_check_extended_key_usage(const mbedtls_x509_crt *crt, + const char *usage_oid, + size_t usage_len); + +#if defined(MBEDTLS_X509_CRL_PARSE_C) +/** + * \brief Verify the certificate revocation status + * + * \param crt a certificate to be verified + * \param crl the CRL to verify against + * + * \return 1 if the certificate is revoked, 0 otherwise + * + */ +int mbedtls_x509_crt_is_revoked(const mbedtls_x509_crt *crt, const mbedtls_x509_crl *crl); +#endif /* MBEDTLS_X509_CRL_PARSE_C */ + +/** + * \brief Initialize a certificate (chain) + * + * \param crt Certificate chain to initialize + */ +void mbedtls_x509_crt_init(mbedtls_x509_crt *crt); + +/** + * \brief Unallocate all certificate data + * + * \param crt Certificate chain to free + */ +void mbedtls_x509_crt_free(mbedtls_x509_crt *crt); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) +/** + * \brief Initialize a restart context + */ +void mbedtls_x509_crt_restart_init(mbedtls_x509_crt_restart_ctx *ctx); + +/** + * \brief Free the components of a restart context + */ +void mbedtls_x509_crt_restart_free(mbedtls_x509_crt_restart_ctx *ctx); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +/** + * \brief Query certificate for given extension type + * + * \param[in] ctx Certificate context to be queried, must not be \c NULL + * \param ext_type Extension type being queried for, must be a valid + * extension type. Must be one of the MBEDTLS_X509_EXT_XXX + * values + * + * \return 0 if the given extension type is not present, + * non-zero otherwise + */ +static inline int mbedtls_x509_crt_has_ext_type(const mbedtls_x509_crt *ctx, + int ext_type) +{ + return ctx->MBEDTLS_PRIVATE(ext_types) & ext_type; +} + +/** \} name Structures and functions for parsing and writing X.509 certificates */ + +#if defined(MBEDTLS_X509_CRT_WRITE_C) +/** + * \brief Initialize a CRT writing context + * + * \param ctx CRT context to initialize + */ +void mbedtls_x509write_crt_init(mbedtls_x509write_cert *ctx); + +/** + * \brief Set the version for a Certificate + * Default: MBEDTLS_X509_CRT_VERSION_3 + * + * \param ctx CRT context to use + * \param version version to set (MBEDTLS_X509_CRT_VERSION_1, MBEDTLS_X509_CRT_VERSION_2 or + * MBEDTLS_X509_CRT_VERSION_3) + */ +void mbedtls_x509write_crt_set_version(mbedtls_x509write_cert *ctx, int version); + +#if defined(MBEDTLS_BIGNUM_C) && !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Set the serial number for a Certificate. + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. Please use + * mbedtls_x509write_crt_set_serial_raw() instead. + * + * \note Even though the MBEDTLS_BIGNUM_C guard looks redundant since + * X509 depends on PK and PK depends on BIGNUM, this emphasizes + * a direct dependency between X509 and BIGNUM which is going + * to be deprecated in the future. + * + * \param ctx CRT context to use + * \param serial serial number to set + * + * \return 0 if successful + */ +int MBEDTLS_DEPRECATED mbedtls_x509write_crt_set_serial( + mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial); +#endif // MBEDTLS_BIGNUM_C && !MBEDTLS_DEPRECATED_REMOVED + +/** + * \brief Set the serial number for a Certificate. + * + * \param ctx CRT context to use + * \param serial A raw array of bytes containing the serial number in big + * endian format + * \param serial_len Length of valid bytes (expressed in bytes) in \p serial + * input buffer + * + * \return 0 if successful, or + * MBEDTLS_ERR_X509_BAD_INPUT_DATA if the provided input buffer + * is too big (longer than MBEDTLS_X509_RFC5280_MAX_SERIAL_LEN) + */ +int mbedtls_x509write_crt_set_serial_raw(mbedtls_x509write_cert *ctx, + unsigned char *serial, size_t serial_len); + +/** + * \brief Set the validity period for a Certificate + * Timestamps should be in string format for UTC timezone + * i.e. "YYYYMMDDhhmmss" + * e.g. "20131231235959" for December 31st 2013 + * at 23:59:59 + * + * \param ctx CRT context to use + * \param not_before not_before timestamp + * \param not_after not_after timestamp + * + * \return 0 if timestamp was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_validity(mbedtls_x509write_cert *ctx, const char *not_before, + const char *not_after); + +/** + * \brief Set the issuer name for a Certificate + * Issuer names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=Mbed TLS CA" + * + * \param ctx CRT context to use + * \param issuer_name issuer name to set + * + * \return 0 if issuer name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_issuer_name(mbedtls_x509write_cert *ctx, + const char *issuer_name); + +/** + * \brief Set the subject name for a Certificate + * Subject names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=Mbed TLS Server 1" + * + * \param ctx CRT context to use + * \param subject_name subject name to set + * + * \return 0 if subject name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_crt_set_subject_name(mbedtls_x509write_cert *ctx, + const char *subject_name); + +/** + * \brief Set the subject public key for the certificate + * + * \param ctx CRT context to use + * \param key public key to include + */ +void mbedtls_x509write_crt_set_subject_key(mbedtls_x509write_cert *ctx, mbedtls_pk_context *key); + +/** + * \brief Set the issuer key used for signing the certificate + * + * \param ctx CRT context to use + * \param key private key to sign with + */ +void mbedtls_x509write_crt_set_issuer_key(mbedtls_x509write_cert *ctx, mbedtls_pk_context *key); + +/** + * \brief Set the MD algorithm to use for the signature + * (e.g. MBEDTLS_MD_SHA1) + * + * \param ctx CRT context to use + * \param md_alg MD algorithm to use + */ +void mbedtls_x509write_crt_set_md_alg(mbedtls_x509write_cert *ctx, mbedtls_md_type_t md_alg); + +/** + * \brief Generic function to add to or replace an extension in the + * CRT + * + * \param ctx CRT context to use + * \param oid OID of the extension + * \param oid_len length of the OID + * \param critical if the extension is critical (per the RFC's definition) + * \param val value of the extension OCTET STRING + * \param val_len length of the value data + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_extension(mbedtls_x509write_cert *ctx, + const char *oid, size_t oid_len, + int critical, + const unsigned char *val, size_t val_len); + +/** + * \brief Set the basicConstraints extension for a CRT + * + * \param ctx CRT context to use + * \param is_ca is this a CA certificate + * \param max_pathlen maximum length of certificate chains below this + * certificate (only for CA certificates, -1 is + * unlimited) + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_basic_constraints(mbedtls_x509write_cert *ctx, + int is_ca, int max_pathlen); + +#if defined(MBEDTLS_MD_CAN_SHA1) +/** + * \brief Set the subjectKeyIdentifier extension for a CRT + * Requires that mbedtls_x509write_crt_set_subject_key() has been + * called before + * + * \param ctx CRT context to use + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_subject_key_identifier(mbedtls_x509write_cert *ctx); + +/** + * \brief Set the authorityKeyIdentifier extension for a CRT + * Requires that mbedtls_x509write_crt_set_issuer_key() has been + * called before + * + * \param ctx CRT context to use + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_authority_key_identifier(mbedtls_x509write_cert *ctx); +#endif /* MBEDTLS_MD_CAN_SHA1 */ + +/** + * \brief Set the Key Usage Extension flags + * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) + * + * \param ctx CRT context to use + * \param key_usage key usage flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_key_usage(mbedtls_x509write_cert *ctx, + unsigned int key_usage); + +/** + * \brief Set the Extended Key Usage Extension + * (e.g. MBEDTLS_OID_SERVER_AUTH) + * + * \param ctx CRT context to use + * \param exts extended key usage extensions to set, a sequence of + * MBEDTLS_ASN1_OID objects + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_ext_key_usage(mbedtls_x509write_cert *ctx, + const mbedtls_asn1_sequence *exts); + +/** + * \brief Set the Netscape Cert Type flags + * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) + * + * \param ctx CRT context to use + * \param ns_cert_type Netscape Cert Type flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_crt_set_ns_cert_type(mbedtls_x509write_cert *ctx, + unsigned char ns_cert_type); + +/** + * \brief Free the contents of a CRT write context + * + * \param ctx CRT context to free + */ +void mbedtls_x509write_crt_free(mbedtls_x509write_cert *ctx); + +/** + * \brief Write a built up certificate to a X509 DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx certificate to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function. This must not be \c NULL. + * \param p_rng RNG parameter + * + * \return length of data written if successful, or a specific + * error code + * + * \note \p f_rng is used for the signature operation. + */ +int mbedtls_x509write_crt_der(mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a built up certificate to a X509 PEM string + * + * \param ctx certificate to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function. This must not be \c NULL. + * \param p_rng RNG parameter + * + * \return 0 if successful, or a specific error code + * + * \note \p f_rng is used for the signature operation. + */ +int mbedtls_x509write_crt_pem(mbedtls_x509write_cert *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_X509_CRT_WRITE_C */ + +/** \} addtogroup x509_module */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_crt.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_csr.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_csr.h index 513a83e..5ad6a27 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_csr.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/mbedtls/x509_csr.h @@ -1,331 +1,331 @@ -/** - * \file x509_csr.h - * - * \brief X.509 certificate signing request parsing and writing - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_X509_CSR_H -#define MBEDTLS_X509_CSR_H -#include "mbedtls/private_access.h" - -#include "mbedtls/build_info.h" - -#include "mbedtls/x509.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup x509_module - * \{ */ - -/** - * \name Structures and functions for X.509 Certificate Signing Requests (CSR) - * \{ - */ - -/** - * Certificate Signing Request (CSR) structure. - * - * Some fields of this structure are publicly readable. Do not modify - * them except via Mbed TLS library functions: the effect of modifying - * those fields or the data that those fields point to is unspecified. - */ -typedef struct mbedtls_x509_csr { - mbedtls_x509_buf raw; /**< The raw CSR data (DER). */ - mbedtls_x509_buf cri; /**< The raw CertificateRequestInfo body (DER). */ - - int version; /**< CSR version (1=v1). */ - - mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). */ - mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ - - mbedtls_pk_context pk; /**< Container for the public key context. */ - - unsigned int key_usage; /**< Optional key usage extension value: See the values in x509.h */ - unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values in x509.h */ - mbedtls_x509_sequence subject_alt_names; /**< Optional list of raw entries of Subject Alternative Names extension. These can be later parsed by mbedtls_x509_parse_subject_alt_name. */ - - int MBEDTLS_PRIVATE(ext_types); /**< Bit string containing detected and parsed extensions */ - - mbedtls_x509_buf sig_oid; - mbedtls_x509_buf MBEDTLS_PRIVATE(sig); - mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ - mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ - void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ -} -mbedtls_x509_csr; - -/** - * Container for writing a CSR - */ -typedef struct mbedtls_x509write_csr { - mbedtls_pk_context *MBEDTLS_PRIVATE(key); - mbedtls_asn1_named_data *MBEDTLS_PRIVATE(subject); - mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); - mbedtls_asn1_named_data *MBEDTLS_PRIVATE(extensions); -} -mbedtls_x509write_csr; - -#if defined(MBEDTLS_X509_CSR_PARSE_C) -/** - * \brief Load a Certificate Signing Request (CSR) in DER format - * - * \note CSR attributes (if any) are currently silently ignored. - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param csr CSR context to fill - * \param buf buffer holding the CRL data - * \param buflen size of the buffer - * - * \return 0 if successful, or a specific X509 error code - */ -int mbedtls_x509_csr_parse_der(mbedtls_x509_csr *csr, - const unsigned char *buf, size_t buflen); - -/** - * \brief Load a Certificate Signing Request (CSR), DER or PEM format - * - * \note See notes for \c mbedtls_x509_csr_parse_der() - * - * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto - * subsystem must have been initialized by calling - * psa_crypto_init() before calling this function. - * - * \param csr CSR context to fill - * \param buf buffer holding the CRL data - * \param buflen size of the buffer - * (including the terminating null byte for PEM data) - * - * \return 0 if successful, or a specific X509 or PEM error code - */ -int mbedtls_x509_csr_parse(mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen); - -#if defined(MBEDTLS_FS_IO) -/** - * \brief Load a Certificate Signing Request (CSR) - * - * \note See notes for \c mbedtls_x509_csr_parse() - * - * \param csr CSR context to fill - * \param path filename to read the CSR from - * - * \return 0 if successful, or a specific X509 or PEM error code - */ -int mbedtls_x509_csr_parse_file(mbedtls_x509_csr *csr, const char *path); -#endif /* MBEDTLS_FS_IO */ - -#if !defined(MBEDTLS_X509_REMOVE_INFO) -/** - * \brief Returns an informational string about the - * CSR. - * - * \param buf Buffer to write to - * \param size Maximum size of buffer - * \param prefix A line prefix - * \param csr The X509 CSR to represent - * - * \return The length of the string written (not including the - * terminated nul byte), or a negative error code. - */ -int mbedtls_x509_csr_info(char *buf, size_t size, const char *prefix, - const mbedtls_x509_csr *csr); -#endif /* !MBEDTLS_X509_REMOVE_INFO */ - -/** - * \brief Initialize a CSR - * - * \param csr CSR to initialize - */ -void mbedtls_x509_csr_init(mbedtls_x509_csr *csr); - -/** - * \brief Unallocate all CSR data - * - * \param csr CSR to free - */ -void mbedtls_x509_csr_free(mbedtls_x509_csr *csr); -#endif /* MBEDTLS_X509_CSR_PARSE_C */ - -/** \} name Structures and functions for X.509 Certificate Signing Requests (CSR) */ - -#if defined(MBEDTLS_X509_CSR_WRITE_C) -/** - * \brief Initialize a CSR context - * - * \param ctx CSR context to initialize - */ -void mbedtls_x509write_csr_init(mbedtls_x509write_csr *ctx); - -/** - * \brief Set the subject name for a CSR - * Subject names should contain a comma-separated list - * of OID types and values: - * e.g. "C=UK,O=ARM,CN=Mbed TLS Server 1" - * - * \param ctx CSR context to use - * \param subject_name subject name to set - * - * \return 0 if subject name was parsed successfully, or - * a specific error code - */ -int mbedtls_x509write_csr_set_subject_name(mbedtls_x509write_csr *ctx, - const char *subject_name); - -/** - * \brief Set the key for a CSR (public key will be included, - * private key used to sign the CSR when writing it) - * - * \param ctx CSR context to use - * \param key Asymmetric key to include - */ -void mbedtls_x509write_csr_set_key(mbedtls_x509write_csr *ctx, mbedtls_pk_context *key); - -/** - * \brief Set the MD algorithm to use for the signature - * (e.g. MBEDTLS_MD_SHA1) - * - * \param ctx CSR context to use - * \param md_alg MD algorithm to use - */ -void mbedtls_x509write_csr_set_md_alg(mbedtls_x509write_csr *ctx, mbedtls_md_type_t md_alg); - -/** - * \brief Set the Key Usage Extension flags - * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) - * - * \param ctx CSR context to use - * \param key_usage key usage flags to set - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - * - * \note The decipherOnly flag from the Key Usage - * extension is represented by bit 8 (i.e. - * 0x8000), which cannot typically be represented - * in an unsigned char. Therefore, the flag - * decipherOnly (i.e. - * #MBEDTLS_X509_KU_DECIPHER_ONLY) cannot be set using this - * function. - */ -int mbedtls_x509write_csr_set_key_usage(mbedtls_x509write_csr *ctx, unsigned char key_usage); - -/** - * \brief Set Subject Alternative Name - * - * \param ctx CSR context to use - * \param san_list List of SAN values - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - * - * \note Only "dnsName", "uniformResourceIdentifier" and "otherName", - * as defined in RFC 5280, are supported. - */ -int mbedtls_x509write_csr_set_subject_alternative_name(mbedtls_x509write_csr *ctx, - const mbedtls_x509_san_list *san_list); - -/** - * \brief Set the Netscape Cert Type flags - * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) - * - * \param ctx CSR context to use - * \param ns_cert_type Netscape Cert Type flags to set - * - * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_csr_set_ns_cert_type(mbedtls_x509write_csr *ctx, - unsigned char ns_cert_type); - -/** - * \brief Generic function to add to or replace an extension in the - * CSR - * - * \param ctx CSR context to use - * \param oid OID of the extension - * \param oid_len length of the OID - * \param critical Set to 1 to mark the extension as critical, 0 otherwise. - * \param val value of the extension OCTET STRING - * \param val_len length of the value data - * - * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED - */ -int mbedtls_x509write_csr_set_extension(mbedtls_x509write_csr *ctx, - const char *oid, size_t oid_len, - int critical, - const unsigned char *val, size_t val_len); - -/** - * \brief Free the contents of a CSR context - * - * \param ctx CSR context to free - */ -void mbedtls_x509write_csr_free(mbedtls_x509write_csr *ctx); - -/** - * \brief Write a CSR (Certificate Signing Request) to a - * DER structure - * Note: data is written at the end of the buffer! Use the - * return value to determine where you should start - * using the buffer - * - * \param ctx CSR to write away - * \param buf buffer to write to - * \param size size of the buffer - * \param f_rng RNG function. This must not be \c NULL. - * \param p_rng RNG parameter - * - * \return length of data written if successful, or a specific - * error code - * - * \note \p f_rng is used for the signature operation. - */ -int mbedtls_x509write_csr_der(mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#if defined(MBEDTLS_PEM_WRITE_C) -/** - * \brief Write a CSR (Certificate Signing Request) to a - * PEM string - * - * \param ctx CSR to write away - * \param buf buffer to write to - * \param size size of the buffer - * \param f_rng RNG function. This must not be \c NULL. - * \param p_rng RNG parameter - * - * \return 0 if successful, or a specific error code - * - * \note \p f_rng is used for the signature operation. - */ -int mbedtls_x509write_csr_pem(mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); -#endif /* MBEDTLS_PEM_WRITE_C */ -#endif /* MBEDTLS_X509_CSR_WRITE_C */ - -/** \} addtogroup x509_module */ - -#ifdef __cplusplus -} -#endif - -#endif /* mbedtls_x509_csr.h */ +/** + * \file x509_csr.h + * + * \brief X.509 certificate signing request parsing and writing + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_X509_CSR_H +#define MBEDTLS_X509_CSR_H +#include "mbedtls/private_access.h" + +#include "mbedtls/build_info.h" + +#include "mbedtls/x509.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup x509_module + * \{ */ + +/** + * \name Structures and functions for X.509 Certificate Signing Requests (CSR) + * \{ + */ + +/** + * Certificate Signing Request (CSR) structure. + * + * Some fields of this structure are publicly readable. Do not modify + * them except via Mbed TLS library functions: the effect of modifying + * those fields or the data that those fields point to is unspecified. + */ +typedef struct mbedtls_x509_csr { + mbedtls_x509_buf raw; /**< The raw CSR data (DER). */ + mbedtls_x509_buf cri; /**< The raw CertificateRequestInfo body (DER). */ + + int version; /**< CSR version (1=v1). */ + + mbedtls_x509_buf subject_raw; /**< The raw subject data (DER). */ + mbedtls_x509_name subject; /**< The parsed subject data (named information object). */ + + mbedtls_pk_context pk; /**< Container for the public key context. */ + + unsigned int key_usage; /**< Optional key usage extension value: See the values in x509.h */ + unsigned char ns_cert_type; /**< Optional Netscape certificate type extension value: See the values in x509.h */ + mbedtls_x509_sequence subject_alt_names; /**< Optional list of raw entries of Subject Alternative Names extension. These can be later parsed by mbedtls_x509_parse_subject_alt_name. */ + + int MBEDTLS_PRIVATE(ext_types); /**< Bit string containing detected and parsed extensions */ + + mbedtls_x509_buf sig_oid; + mbedtls_x509_buf MBEDTLS_PRIVATE(sig); + mbedtls_md_type_t MBEDTLS_PRIVATE(sig_md); /**< Internal representation of the MD algorithm of the signature algorithm, e.g. MBEDTLS_MD_SHA256 */ + mbedtls_pk_type_t MBEDTLS_PRIVATE(sig_pk); /**< Internal representation of the Public Key algorithm of the signature algorithm, e.g. MBEDTLS_PK_RSA */ + void *MBEDTLS_PRIVATE(sig_opts); /**< Signature options to be passed to mbedtls_pk_verify_ext(), e.g. for RSASSA-PSS */ +} +mbedtls_x509_csr; + +/** + * Container for writing a CSR + */ +typedef struct mbedtls_x509write_csr { + mbedtls_pk_context *MBEDTLS_PRIVATE(key); + mbedtls_asn1_named_data *MBEDTLS_PRIVATE(subject); + mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); + mbedtls_asn1_named_data *MBEDTLS_PRIVATE(extensions); +} +mbedtls_x509write_csr; + +#if defined(MBEDTLS_X509_CSR_PARSE_C) +/** + * \brief Load a Certificate Signing Request (CSR) in DER format + * + * \note CSR attributes (if any) are currently silently ignored. + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param csr CSR context to fill + * \param buf buffer holding the CRL data + * \param buflen size of the buffer + * + * \return 0 if successful, or a specific X509 error code + */ +int mbedtls_x509_csr_parse_der(mbedtls_x509_csr *csr, + const unsigned char *buf, size_t buflen); + +/** + * \brief Load a Certificate Signing Request (CSR), DER or PEM format + * + * \note See notes for \c mbedtls_x509_csr_parse_der() + * + * \note If #MBEDTLS_USE_PSA_CRYPTO is enabled, the PSA crypto + * subsystem must have been initialized by calling + * psa_crypto_init() before calling this function. + * + * \param csr CSR context to fill + * \param buf buffer holding the CRL data + * \param buflen size of the buffer + * (including the terminating null byte for PEM data) + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_csr_parse(mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen); + +#if defined(MBEDTLS_FS_IO) +/** + * \brief Load a Certificate Signing Request (CSR) + * + * \note See notes for \c mbedtls_x509_csr_parse() + * + * \param csr CSR context to fill + * \param path filename to read the CSR from + * + * \return 0 if successful, or a specific X509 or PEM error code + */ +int mbedtls_x509_csr_parse_file(mbedtls_x509_csr *csr, const char *path); +#endif /* MBEDTLS_FS_IO */ + +#if !defined(MBEDTLS_X509_REMOVE_INFO) +/** + * \brief Returns an informational string about the + * CSR. + * + * \param buf Buffer to write to + * \param size Maximum size of buffer + * \param prefix A line prefix + * \param csr The X509 CSR to represent + * + * \return The length of the string written (not including the + * terminated nul byte), or a negative error code. + */ +int mbedtls_x509_csr_info(char *buf, size_t size, const char *prefix, + const mbedtls_x509_csr *csr); +#endif /* !MBEDTLS_X509_REMOVE_INFO */ + +/** + * \brief Initialize a CSR + * + * \param csr CSR to initialize + */ +void mbedtls_x509_csr_init(mbedtls_x509_csr *csr); + +/** + * \brief Unallocate all CSR data + * + * \param csr CSR to free + */ +void mbedtls_x509_csr_free(mbedtls_x509_csr *csr); +#endif /* MBEDTLS_X509_CSR_PARSE_C */ + +/** \} name Structures and functions for X.509 Certificate Signing Requests (CSR) */ + +#if defined(MBEDTLS_X509_CSR_WRITE_C) +/** + * \brief Initialize a CSR context + * + * \param ctx CSR context to initialize + */ +void mbedtls_x509write_csr_init(mbedtls_x509write_csr *ctx); + +/** + * \brief Set the subject name for a CSR + * Subject names should contain a comma-separated list + * of OID types and values: + * e.g. "C=UK,O=ARM,CN=Mbed TLS Server 1" + * + * \param ctx CSR context to use + * \param subject_name subject name to set + * + * \return 0 if subject name was parsed successfully, or + * a specific error code + */ +int mbedtls_x509write_csr_set_subject_name(mbedtls_x509write_csr *ctx, + const char *subject_name); + +/** + * \brief Set the key for a CSR (public key will be included, + * private key used to sign the CSR when writing it) + * + * \param ctx CSR context to use + * \param key Asymmetric key to include + */ +void mbedtls_x509write_csr_set_key(mbedtls_x509write_csr *ctx, mbedtls_pk_context *key); + +/** + * \brief Set the MD algorithm to use for the signature + * (e.g. MBEDTLS_MD_SHA1) + * + * \param ctx CSR context to use + * \param md_alg MD algorithm to use + */ +void mbedtls_x509write_csr_set_md_alg(mbedtls_x509write_csr *ctx, mbedtls_md_type_t md_alg); + +/** + * \brief Set the Key Usage Extension flags + * (e.g. MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_KEY_CERT_SIGN) + * + * \param ctx CSR context to use + * \param key_usage key usage flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + * + * \note The decipherOnly flag from the Key Usage + * extension is represented by bit 8 (i.e. + * 0x8000), which cannot typically be represented + * in an unsigned char. Therefore, the flag + * decipherOnly (i.e. + * #MBEDTLS_X509_KU_DECIPHER_ONLY) cannot be set using this + * function. + */ +int mbedtls_x509write_csr_set_key_usage(mbedtls_x509write_csr *ctx, unsigned char key_usage); + +/** + * \brief Set Subject Alternative Name + * + * \param ctx CSR context to use + * \param san_list List of SAN values + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + * + * \note Only "dnsName", "uniformResourceIdentifier" and "otherName", + * as defined in RFC 5280, are supported. + */ +int mbedtls_x509write_csr_set_subject_alternative_name(mbedtls_x509write_csr *ctx, + const mbedtls_x509_san_list *san_list); + +/** + * \brief Set the Netscape Cert Type flags + * (e.g. MBEDTLS_X509_NS_CERT_TYPE_SSL_CLIENT | MBEDTLS_X509_NS_CERT_TYPE_EMAIL) + * + * \param ctx CSR context to use + * \param ns_cert_type Netscape Cert Type flags to set + * + * \return 0 if successful, or MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_csr_set_ns_cert_type(mbedtls_x509write_csr *ctx, + unsigned char ns_cert_type); + +/** + * \brief Generic function to add to or replace an extension in the + * CSR + * + * \param ctx CSR context to use + * \param oid OID of the extension + * \param oid_len length of the OID + * \param critical Set to 1 to mark the extension as critical, 0 otherwise. + * \param val value of the extension OCTET STRING + * \param val_len length of the value data + * + * \return 0 if successful, or a MBEDTLS_ERR_X509_ALLOC_FAILED + */ +int mbedtls_x509write_csr_set_extension(mbedtls_x509write_csr *ctx, + const char *oid, size_t oid_len, + int critical, + const unsigned char *val, size_t val_len); + +/** + * \brief Free the contents of a CSR context + * + * \param ctx CSR context to free + */ +void mbedtls_x509write_csr_free(mbedtls_x509write_csr *ctx); + +/** + * \brief Write a CSR (Certificate Signing Request) to a + * DER structure + * Note: data is written at the end of the buffer! Use the + * return value to determine where you should start + * using the buffer + * + * \param ctx CSR to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function. This must not be \c NULL. + * \param p_rng RNG parameter + * + * \return length of data written if successful, or a specific + * error code + * + * \note \p f_rng is used for the signature operation. + */ +int mbedtls_x509write_csr_der(mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#if defined(MBEDTLS_PEM_WRITE_C) +/** + * \brief Write a CSR (Certificate Signing Request) to a + * PEM string + * + * \param ctx CSR to write away + * \param buf buffer to write to + * \param size size of the buffer + * \param f_rng RNG function. This must not be \c NULL. + * \param p_rng RNG parameter + * + * \return 0 if successful, or a specific error code + * + * \note \p f_rng is used for the signature operation. + */ +int mbedtls_x509write_csr_pem(mbedtls_x509write_csr *ctx, unsigned char *buf, size_t size, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +#endif /* MBEDTLS_PEM_WRITE_C */ +#endif /* MBEDTLS_X509_CSR_WRITE_C */ + +/** \} addtogroup x509_module */ + +#ifdef __cplusplus +} +#endif + +#endif /* mbedtls_x509_csr.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/build_info.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/build_info.h index 34a138d..b8ea62d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/build_info.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/build_info.h @@ -1,32 +1,32 @@ -/** - * \file psa/build_info.h - * - * \brief Build-time PSA configuration info - * - * Include this file if you need to depend on the - * configuration options defined in mbedtls_config.h or MBEDTLS_CONFIG_FILE - * in PSA cryptography core specific files. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_BUILD_INFO_H -#define PSA_CRYPTO_BUILD_INFO_H - -#include "mbedtls/build_info.h" - -#endif /* PSA_CRYPTO_BUILD_INFO_H */ +/** + * \file psa/build_info.h + * + * \brief Build-time PSA configuration info + * + * Include this file if you need to depend on the + * configuration options defined in mbedtls_config.h or MBEDTLS_CONFIG_FILE + * in PSA cryptography core specific files. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_BUILD_INFO_H +#define PSA_CRYPTO_BUILD_INFO_H + +#include "mbedtls/build_info.h" + +#endif /* PSA_CRYPTO_BUILD_INFO_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto.h index b5f105d..35a6eaa 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto.h @@ -1,4772 +1,4772 @@ -/** - * \file psa/crypto.h - * \brief Platform Security Architecture cryptography module - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_H -#define PSA_CRYPTO_H - -#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) -#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE -#else -#include "crypto_platform.h" -#endif - -#include - -#ifdef __DOXYGEN_ONLY__ -/* This __DOXYGEN_ONLY__ block contains mock definitions for things that - * must be defined in the crypto_platform.h header. These mock definitions - * are present in this file as a convenience to generate pretty-printed - * documentation that includes those definitions. */ - -/** \defgroup platform Implementation-specific definitions - * @{ - */ - -/**@}*/ -#endif /* __DOXYGEN_ONLY__ */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The file "crypto_types.h" declares types that encode errors, - * algorithms, key types, policies, etc. */ -#include "crypto_types.h" - -/** \defgroup version API version - * @{ - */ - -/** - * The major version of this implementation of the PSA Crypto API - */ -#define PSA_CRYPTO_API_VERSION_MAJOR 1 - -/** - * The minor version of this implementation of the PSA Crypto API - */ -#define PSA_CRYPTO_API_VERSION_MINOR 0 - -/**@}*/ - -/* The file "crypto_values.h" declares macros to build and analyze values - * of integral types defined in "crypto_types.h". */ -#include "crypto_values.h" - -/** \defgroup initialization Library initialization - * @{ - */ - -/** - * \brief Library initialization. - * - * Applications must call this function before calling any other - * function in this module. - * - * Applications may call this function more than once. Once a call - * succeeds, subsequent calls are guaranteed to succeed. - * - * If the application calls other functions before calling psa_crypto_init(), - * the behavior is undefined. Implementations are encouraged to either perform - * the operation as if the library had been initialized or to return - * #PSA_ERROR_BAD_STATE or some other applicable error. In particular, - * implementations should not return a success status if the lack of - * initialization may have security implications, for example due to improper - * seeding of the random number generator. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -psa_status_t psa_crypto_init(void); - -/**@}*/ - -/** \addtogroup attributes - * @{ - */ - -/** \def PSA_KEY_ATTRIBUTES_INIT - * - * This macro returns a suitable initializer for a key attribute structure - * of type #psa_key_attributes_t. - */ - -/** Return an initial value for a key attributes structure. - */ -static psa_key_attributes_t psa_key_attributes_init(void); - -/** Declare a key as persistent and set its key identifier. - * - * If the attribute structure currently declares the key as volatile (which - * is the default content of an attribute structure), this function sets - * the lifetime attribute to #PSA_KEY_LIFETIME_PERSISTENT. - * - * This function does not access storage, it merely stores the given - * value in the structure. - * The persistent key will be written to storage when the attribute - * structure is passed to a key creation function such as - * psa_import_key(), psa_generate_key(), - * psa_key_derivation_output_key() or psa_copy_key(). - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param key The persistent identifier for the key. - */ -static void psa_set_key_id(psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t key); - -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER -/** Set the owner identifier of a key. - * - * When key identifiers encode key owner identifiers, psa_set_key_id() does - * not allow to define in key attributes the owner of volatile keys as - * psa_set_key_id() enforces the key to be persistent. - * - * This function allows to set in key attributes the owner identifier of a - * key. It is intended to be used for volatile keys. For persistent keys, - * it is recommended to use the PSA Cryptography API psa_set_key_id() to define - * the owner of a key. - * - * \param[out] attributes The attribute structure to write to. - * \param owner The key owner identifier. - */ -static void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, - mbedtls_key_owner_id_t owner); -#endif - -/** Set the location of a persistent key. - * - * To make a key persistent, you must give it a persistent key identifier - * with psa_set_key_id(). By default, a key that has a persistent identifier - * is stored in the default storage area identifier by - * #PSA_KEY_LIFETIME_PERSISTENT. Call this function to choose a storage - * area, or to explicitly declare the key as volatile. - * - * This function does not access storage, it merely stores the given - * value in the structure. - * The persistent key will be written to storage when the attribute - * structure is passed to a key creation function such as - * psa_import_key(), psa_generate_key(), - * psa_key_derivation_output_key() or psa_copy_key(). - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param lifetime The lifetime for the key. - * If this is #PSA_KEY_LIFETIME_VOLATILE, the - * key will be volatile, and the key identifier - * attribute is reset to 0. - */ -static void psa_set_key_lifetime(psa_key_attributes_t *attributes, - psa_key_lifetime_t lifetime); - -/** Retrieve the key identifier from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The persistent identifier stored in the attribute structure. - * This value is unspecified if the attribute structure declares - * the key as volatile. - */ -static mbedtls_svc_key_id_t psa_get_key_id( - const psa_key_attributes_t *attributes); - -/** Retrieve the lifetime from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The lifetime value stored in the attribute structure. - */ -static psa_key_lifetime_t psa_get_key_lifetime( - const psa_key_attributes_t *attributes); - -/** Declare usage flags for a key. - * - * Usage flags are part of a key's usage policy. They encode what - * kind of operations are permitted on the key. For more details, - * refer to the documentation of the type #psa_key_usage_t. - * - * This function overwrites any usage flags - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param usage_flags The usage flags to write. - */ -static void psa_set_key_usage_flags(psa_key_attributes_t *attributes, - psa_key_usage_t usage_flags); - -/** Retrieve the usage flags from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The usage flags stored in the attribute structure. - */ -static psa_key_usage_t psa_get_key_usage_flags( - const psa_key_attributes_t *attributes); - -/** Declare the permitted algorithm policy for a key. - * - * The permitted algorithm policy of a key encodes which algorithm or - * algorithms are permitted to be used with this key. The following - * algorithm policies are supported: - * - 0 does not allow any cryptographic operation with the key. The key - * may be used for non-cryptographic actions such as exporting (if - * permitted by the usage flags). - * - An algorithm value permits this particular algorithm. - * - An algorithm wildcard built from #PSA_ALG_ANY_HASH allows the specified - * signature scheme with any hash algorithm. - * - An algorithm built from #PSA_ALG_AT_LEAST_THIS_LENGTH_MAC allows - * any MAC algorithm from the same base class (e.g. CMAC) which - * generates/verifies a MAC length greater than or equal to the length - * encoded in the wildcard algorithm. - * - An algorithm built from #PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG - * allows any AEAD algorithm from the same base class (e.g. CCM) which - * generates/verifies a tag length greater than or equal to the length - * encoded in the wildcard algorithm. - * - * This function overwrites any algorithm policy - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param alg The permitted algorithm policy to write. - */ -static void psa_set_key_algorithm(psa_key_attributes_t *attributes, - psa_algorithm_t alg); - - -/** Retrieve the algorithm policy from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The algorithm stored in the attribute structure. - */ -static psa_algorithm_t psa_get_key_algorithm( - const psa_key_attributes_t *attributes); - -/** Declare the type of a key. - * - * This function overwrites any key type - * previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param type The key type to write. - * If this is 0, the key type in \p attributes - * becomes unspecified. - */ -static void psa_set_key_type(psa_key_attributes_t *attributes, - psa_key_type_t type); - - -/** Declare the size of a key. - * - * This function overwrites any key size previously set in \p attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate each of its arguments exactly once. - * - * \param[out] attributes The attribute structure to write to. - * \param bits The key size in bits. - * If this is 0, the key size in \p attributes - * becomes unspecified. Keys of size 0 are - * not supported. - */ -static void psa_set_key_bits(psa_key_attributes_t *attributes, - size_t bits); - -/** Retrieve the key type from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The key type stored in the attribute structure. - */ -static psa_key_type_t psa_get_key_type(const psa_key_attributes_t *attributes); - -/** Retrieve the key size from key attributes. - * - * This function may be declared as `static` (i.e. without external - * linkage). This function may be provided as a function-like macro, - * but in this case it must evaluate its argument exactly once. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The key size stored in the attribute structure, in bits. - */ -static size_t psa_get_key_bits(const psa_key_attributes_t *attributes); - -/** Retrieve the attributes of a key. - * - * This function first resets the attribute structure as with - * psa_reset_key_attributes(). It then copies the attributes of - * the given key into the given attribute structure. - * - * \note This function may allocate memory or other resources. - * Once you have called this function on an attribute structure, - * you must call psa_reset_key_attributes() to free these resources. - * - * \param[in] key Identifier of the key to query. - * \param[in,out] attributes On success, the attributes of the key. - * On failure, equivalent to a - * freshly-initialized structure. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, - psa_key_attributes_t *attributes); - -/** Reset a key attribute structure to a freshly initialized state. - * - * You must initialize the attribute structure as described in the - * documentation of the type #psa_key_attributes_t before calling this - * function. Once the structure has been initialized, you may call this - * function at any time. - * - * This function frees any auxiliary resources that the structure - * may contain. - * - * \param[in,out] attributes The attribute structure to reset. - */ -void psa_reset_key_attributes(psa_key_attributes_t *attributes); - -/**@}*/ - -/** \defgroup key_management Key management - * @{ - */ - -/** Remove non-essential copies of key material from memory. - * - * If the key identifier designates a volatile key, this functions does not do - * anything and returns successfully. - * - * If the key identifier designates a persistent key, then this function will - * free all resources associated with the key in volatile memory. The key - * data in persistent storage is not affected and the key can still be used. - * - * \param key Identifier of the key to purge. - * - * \retval #PSA_SUCCESS - * The key material will have been removed from memory if it is not - * currently required. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not a valid key identifier. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_purge_key(mbedtls_svc_key_id_t key); - -/** Make a copy of a key. - * - * Copy key material from one location to another. - * - * This function is primarily useful to copy a key from one location - * to another, since it populates a key using the material from - * another key which may have a different lifetime. - * - * This function may be used to share a key with a different party, - * subject to implementation-defined restrictions on key sharing. - * - * The policy on the source key must have the usage flag - * #PSA_KEY_USAGE_COPY set. - * This flag is sufficient to permit the copy if the key has the lifetime - * #PSA_KEY_LIFETIME_VOLATILE or #PSA_KEY_LIFETIME_PERSISTENT. - * Some secure elements do not provide a way to copy a key without - * making it extractable from the secure element. If a key is located - * in such a secure element, then the key must have both usage flags - * #PSA_KEY_USAGE_COPY and #PSA_KEY_USAGE_EXPORT in order to make - * a copy of the key outside the secure element. - * - * The resulting key may only be used in a way that conforms to - * both the policy of the original key and the policy specified in - * the \p attributes parameter: - * - The usage flags on the resulting key are the bitwise-and of the - * usage flags on the source policy and the usage flags in \p attributes. - * - If both allow the same algorithm or wildcard-based - * algorithm policy, the resulting key has the same algorithm policy. - * - If either of the policies allows an algorithm and the other policy - * allows a wildcard-based algorithm policy that includes this algorithm, - * the resulting key allows the same algorithm. - * - If the policies do not allow any algorithm in common, this function - * fails with the status #PSA_ERROR_INVALID_ARGUMENT. - * - * The effect of this function on implementation-defined attributes is - * implementation-defined. - * - * \param source_key The key to copy. It must allow the usage - * #PSA_KEY_USAGE_COPY. If a private or secret key is - * being copied outside of a secure element it must - * also allow #PSA_KEY_USAGE_EXPORT. - * \param[in] attributes The attributes for the new key. - * They are used as follows: - * - The key type and size may be 0. If either is - * nonzero, it must match the corresponding - * attribute of the source key. - * - The key location (the lifetime and, for - * persistent keys, the key identifier) is - * used directly. - * - The policy constraints (usage flags and - * algorithm policy) are combined from - * the source key and \p attributes so that - * both sets of restrictions apply, as - * described in the documentation of this function. - * \param[out] target_key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE - * \p source_key is invalid. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The lifetime or identifier in \p attributes are invalid, or - * the policy constraints on the source and specified in - * \p attributes are incompatible, or - * \p attributes specifies a key type or key size - * which does not match the attributes of the source key. - * \retval #PSA_ERROR_NOT_PERMITTED - * The source key does not have the #PSA_KEY_USAGE_COPY usage flag, or - * the source key is not exportable and its lifetime does not - * allow copying it to the target's lifetime. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, - const psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t *target_key); - - -/** - * \brief Destroy a key. - * - * This function destroys a key from both volatile - * memory and, if applicable, non-volatile storage. Implementations shall - * make a best effort to ensure that the key material cannot be recovered. - * - * This function also erases any metadata such as policies and frees - * resources associated with the key. - * - * If a key is currently in use in a multipart operation, then destroying the - * key will cause the multipart operation to fail. - * - * \param key Identifier of the key to erase. If this is \c 0, do nothing and - * return #PSA_SUCCESS. - * - * \retval #PSA_SUCCESS - * \p key was a valid identifier and the key material that it - * referred to has been erased. Alternatively, \p key is \c 0. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key cannot be erased because it is - * read-only, either due to a policy or due to physical restrictions. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p key is not a valid identifier nor \c 0. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * There was a failure in communication with the cryptoprocessor. - * The key material may still be present in the cryptoprocessor. - * \retval #PSA_ERROR_DATA_INVALID - * This error is typically a result of either storage corruption on a - * cleartext storage backend, or an attempt to read data that was - * written by an incompatible version of the library. - * \retval #PSA_ERROR_STORAGE_FAILURE - * The storage is corrupted. Implementations shall make a best effort - * to erase key material even in this stage, however applications - * should be aware that it may be impossible to guarantee that the - * key material is not recoverable in such cases. - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * An unexpected condition which is not a storage corruption or - * a communication failure occurred. The cryptoprocessor may have - * been compromised. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(), - * or the library was not able to move the key slot to the - * PSA_STATE_DESTROYING state. - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_destroy_key(mbedtls_svc_key_id_t key); - -/**@}*/ - -/** \defgroup import_export Key import and export - * @{ - */ - -/** - * \brief Import a key in binary format. - * - * This function supports any output from psa_export_key(). Refer to the - * documentation of psa_export_public_key() for the format of public keys - * and to the documentation of psa_export_key() for the format for - * other key types. - * - * The key data determines the key size. The attributes may optionally - * specify a key size; in this case it must match the size determined - * from the key data. A key size of 0 in \p attributes indicates that - * the key size is solely determined by the key data. - * - * Implementations must reject an attempt to import a key of size 0. - * - * This specification supports a single format for each key type. - * Implementations may support other formats as long as the standard - * format is supported. Implementations that support other formats - * should ensure that the formats are clearly unambiguous so as to - * minimize the risk that an invalid input is accidentally interpreted - * according to a different format. - * - * \param[in] attributes The attributes for the new key. - * The key size is always determined from the - * \p data buffer. - * If the key size in \p attributes is nonzero, - * it must be equal to the size from \p data. - * \param[out] key On success, an identifier to the newly created key. - * For persistent keys, this is the key identifier - * defined in \p attributes. - * \c 0 on failure. - * \param[in] data Buffer containing the key data. The content of this - * buffer is interpreted according to the type declared - * in \p attributes. - * All implementations must support at least the format - * described in the documentation - * of psa_export_key() or psa_export_public_key() for - * the chosen type. Implementations may allow other - * formats, but should be conservative: implementations - * should err on the side of rejecting content if it - * may be erroneous (e.g. wrong type or truncated data). - * \param data_length Size of the \p data buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size is not supported, either by the - * implementation in general or in this particular persistent location. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key attributes, as a whole, are invalid, or - * the key data is not correctly formatted, or - * the size in \p attributes is nonzero and does not match the size - * of the key data. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_import_key(const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - mbedtls_svc_key_id_t *key); - - - -/** - * \brief Export a key in binary format. - * - * The output of this function can be passed to psa_import_key() to - * create an equivalent object. - * - * If the implementation of psa_import_key() supports other formats - * beyond the format specified here, the output from psa_export_key() - * must use the representation specified here, not the original - * representation. - * - * For standard key types, the output format is as follows: - * - * - For symmetric keys (including MAC keys), the format is the - * raw bytes of the key. - * - For DES, the key data consists of 8 bytes. The parity bits must be - * correct. - * - For Triple-DES, the format is the concatenation of the - * two or three DES keys. - * - For RSA key pairs (#PSA_KEY_TYPE_RSA_KEY_PAIR), the format - * is the non-encrypted DER encoding of the representation defined by - * PKCS\#1 (RFC 8017) as `RSAPrivateKey`, version 0. - * ``` - * RSAPrivateKey ::= SEQUENCE { - * version INTEGER, -- must be 0 - * modulus INTEGER, -- n - * publicExponent INTEGER, -- e - * privateExponent INTEGER, -- d - * prime1 INTEGER, -- p - * prime2 INTEGER, -- q - * exponent1 INTEGER, -- d mod (p-1) - * exponent2 INTEGER, -- d mod (q-1) - * coefficient INTEGER, -- (inverse of q) mod p - * } - * ``` - * - For elliptic curve key pairs (key types for which - * #PSA_KEY_TYPE_IS_ECC_KEY_PAIR is true), the format is - * a representation of the private value as a `ceiling(m/8)`-byte string - * where `m` is the bit size associated with the curve, i.e. the bit size - * of the order of the curve's coordinate field. This byte string is - * in little-endian order for Montgomery curves (curve types - * `PSA_ECC_FAMILY_CURVEXXX`), and in big-endian order for Weierstrass - * curves (curve types `PSA_ECC_FAMILY_SECTXXX`, `PSA_ECC_FAMILY_SECPXXX` - * and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`). - * For Weierstrass curves, this is the content of the `privateKey` field of - * the `ECPrivateKey` format defined by RFC 5915. For Montgomery curves, - * the format is defined by RFC 7748, and output is masked according to §5. - * For twisted Edwards curves, the private key is as defined by RFC 8032 - * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). - * - For Diffie-Hellman key exchange key pairs (key types for which - * #PSA_KEY_TYPE_IS_DH_KEY_PAIR is true), the - * format is the representation of the private key `x` as a big-endian byte - * string. The length of the byte string is the private key size in bytes - * (leading zeroes are not stripped). - * - For public keys (key types for which #PSA_KEY_TYPE_IS_PUBLIC_KEY is - * true), the format is the same as for psa_export_public_key(). - * - * The policy on the key must have the usage flag #PSA_KEY_USAGE_EXPORT set. - * - * \param key Identifier of the key to export. It must allow the - * usage #PSA_KEY_USAGE_EXPORT, unless it is a public - * key. - * \param[out] data Buffer where the key data is to be written. - * \param data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_EXPORT flag. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p data buffer is too small. You can determine a - * sufficient buffer size by calling - * #PSA_EXPORT_KEY_OUTPUT_SIZE(\c type, \c bits) - * where \c type is the key type - * and \c bits is the key size in bits. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_export_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** - * \brief Export a public key or the public part of a key pair in binary format. - * - * The output of this function can be passed to psa_import_key() to - * create an object that is equivalent to the public key. - * - * This specification supports a single format for each key type. - * Implementations may support other formats as long as the standard - * format is supported. Implementations that support other formats - * should ensure that the formats are clearly unambiguous so as to - * minimize the risk that an invalid input is accidentally interpreted - * according to a different format. - * - * For standard key types, the output format is as follows: - * - For RSA public keys (#PSA_KEY_TYPE_RSA_PUBLIC_KEY), the DER encoding of - * the representation defined by RFC 3279 §2.3.1 as `RSAPublicKey`. - * ``` - * RSAPublicKey ::= SEQUENCE { - * modulus INTEGER, -- n - * publicExponent INTEGER } -- e - * ``` - * - For elliptic curve keys on a twisted Edwards curve (key types for which - * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true and #PSA_KEY_TYPE_ECC_GET_FAMILY - * returns #PSA_ECC_FAMILY_TWISTED_EDWARDS), the public key is as defined - * by RFC 8032 - * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). - * - For other elliptic curve public keys (key types for which - * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true), the format is the uncompressed - * representation defined by SEC1 §2.3.3 as the content of an ECPoint. - * Let `m` be the bit size associated with the curve, i.e. the bit size of - * `q` for a curve over `F_q`. The representation consists of: - * - The byte 0x04; - * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; - * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. - * - For Diffie-Hellman key exchange public keys (key types for which - * #PSA_KEY_TYPE_IS_DH_PUBLIC_KEY is true), - * the format is the representation of the public key `y = g^x mod p` as a - * big-endian byte string. The length of the byte string is the length of the - * base prime `p` in bytes. - * - * Exporting a public key object or the public part of a key pair is - * always permitted, regardless of the key's usage flags. - * - * \param key Identifier of the key to export. - * \param[out] data Buffer where the key data is to be written. - * \param data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key is neither a public key nor a key pair. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p data buffer is too small. You can determine a - * sufficient buffer size by calling - * #PSA_EXPORT_KEY_OUTPUT_SIZE(#PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\c type), \c bits) - * where \c type is the key type - * and \c bits is the key size in bits. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length); - - - -/**@}*/ - -/** \defgroup hash Message digests - * @{ - */ - -/** Calculate the hash (digest) of a message. - * - * \note To verify the hash of a message against an - * expected value, use psa_hash_compare() instead. - * - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * \param[in] input Buffer containing the message to hash. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\p alg). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p hash_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_compute(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Calculate the hash (digest) of a message and compare it with a - * reference value. - * - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * \param[in] input Buffer containing the message to hash. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] hash Buffer containing the expected hash value. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected hash is identical to the actual hash of the input. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The hash of the message was calculated successfully, but it - * differs from the expected hash. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p input_length or \p hash_length do not match the hash size for \p alg - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_compare(psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *hash, - size_t hash_length); - -/** The type of the state data structure for multipart hash operations. - * - * Before calling any function on a hash operation object, the application must - * initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_hash_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_hash_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_HASH_OPERATION_INIT, - * for example: - * \code - * psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_hash_operation_init() - * to the structure, for example: - * \code - * psa_hash_operation_t operation; - * operation = psa_hash_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_hash_operation_s psa_hash_operation_t; - -/** \def PSA_HASH_OPERATION_INIT - * - * This macro returns a suitable initializer for a hash operation object - * of type #psa_hash_operation_t. - */ - -/** Return an initial value for a hash operation object. - */ -static psa_hash_operation_t psa_hash_operation_init(void); - -/** Set up a multipart hash operation. - * - * The sequence of operations to calculate a hash (message digest) - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_hash_operation_t, e.g. #PSA_HASH_OPERATION_INIT. - * -# Call psa_hash_setup() to specify the algorithm. - * -# Call psa_hash_update() zero, one or more times, passing a fragment - * of the message each time. The hash that is calculated is the hash - * of the concatenation of these messages in order. - * -# To calculate the hash, call psa_hash_finish(). - * To compare the hash with an expected value, call psa_hash_verify(). - * - * If an error occurs at any step after a call to psa_hash_setup(), the - * operation will need to be reset by a call to psa_hash_abort(). The - * application may call psa_hash_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_hash_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_hash_finish() or psa_hash_verify(). - * - A call to psa_hash_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_hash_operation_t and not yet in use. - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported hash algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a hash algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_setup(psa_hash_operation_t *operation, - psa_algorithm_t alg); - -/** Add a message fragment to a multipart hash operation. - * - * The application must call psa_hash_setup() before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \param[in,out] operation Active hash operation. - * \param[in] input Buffer containing the message fragment to hash. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_update(psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the hash of a message. - * - * The application must call psa_hash_setup() before calling this function. - * This function calculates the hash of the message formed by concatenating - * the inputs passed to preceding calls to psa_hash_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \warning Applications should not call this function if they expect - * a specific value for the hash. Call psa_hash_verify() instead. - * Beware that comparing integrity or authenticity data such as - * hash values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the hashed data which could allow an attacker to guess - * a valid hash and thereby bypass security controls. - * - * \param[in,out] operation Active hash operation. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\c alg) where \c alg is the - * hash algorithm that is calculated. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p hash buffer is too small. You can determine a - * sufficient buffer size by calling #PSA_HASH_LENGTH(\c alg) - * where \c alg is the hash algorithm that is calculated. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_finish(psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Finish the calculation of the hash of a message and compare it with - * an expected value. - * - * The application must call psa_hash_setup() before calling this function. - * This function calculates the hash of the message formed by concatenating - * the inputs passed to preceding calls to psa_hash_update(). It then - * compares the calculated hash with the expected hash passed as a - * parameter to this function. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_hash_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual hash and the expected hash is performed - * in constant time. - * - * \param[in,out] operation Active hash operation. - * \param[in] hash Buffer containing the expected hash value. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected hash is identical to the actual hash of the message. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The hash of the message was calculated successfully, but it - * differs from the expected hash. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_verify(psa_hash_operation_t *operation, - const uint8_t *hash, - size_t hash_length); - -/** Abort a hash operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_hash_setup() again. - * - * You may call this function any time after the operation object has - * been initialized by one of the methods described in #psa_hash_operation_t. - * - * In particular, calling psa_hash_abort() after the operation has been - * terminated by a call to psa_hash_abort(), psa_hash_finish() or - * psa_hash_verify() is safe and has no effect. - * - * \param[in,out] operation Initialized hash operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_abort(psa_hash_operation_t *operation); - -/** Clone a hash operation. - * - * This function copies the state of an ongoing hash operation to - * a new operation object. In other words, this function is equivalent - * to calling psa_hash_setup() on \p target_operation with the same - * algorithm that \p source_operation was set up for, then - * psa_hash_update() on \p target_operation with the same input that - * that was passed to \p source_operation. After this function returns, the - * two objects are independent, i.e. subsequent calls involving one of - * the objects do not affect the other object. - * - * \param[in] source_operation The active hash operation to clone. - * \param[in,out] target_operation The operation object to set up. - * It must be initialized but not active. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The \p source_operation state is not valid (it must be active), or - * the \p target_operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, - psa_hash_operation_t *target_operation); - -/**@}*/ - -/** \defgroup MAC Message authentication codes - * @{ - */ - -/** Calculate the MAC (message authentication code) of a message. - * - * \note To verify the MAC of a message against an - * expected value, use psa_mac_verify() instead. - * Beware that comparing integrity or authenticity data such as - * MAC values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the MAC value which could allow an attacker to guess - * a valid MAC and thereby bypass security controls. - * - * \param key Identifier of the key to use for the operation. It - * must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * \param[in] input Buffer containing the input message. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Size of the \p mac buffer in bytes. - * \param[out] mac_length On success, the number of bytes - * that make up the MAC value. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p mac_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Calculate the MAC of a message and compare it with a reference value. - * - * \param key Identifier of the key to use for the operation. It - * must allow the usage PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * \param[in] input Buffer containing the input message. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] mac Buffer containing the expected MAC value. - * \param mac_length Size of the \p mac buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected MAC is identical to the actual MAC of the input. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The MAC of the message was calculated successfully, but it - * differs from the expected value. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *mac, - size_t mac_length); - -/** The type of the state data structure for multipart MAC operations. - * - * Before calling any function on a MAC operation object, the application must - * initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_mac_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_mac_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_MAC_OPERATION_INIT, - * for example: - * \code - * psa_mac_operation_t operation = PSA_MAC_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_mac_operation_init() - * to the structure, for example: - * \code - * psa_mac_operation_t operation; - * operation = psa_mac_operation_init(); - * \endcode - * - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_mac_operation_s psa_mac_operation_t; - -/** \def PSA_MAC_OPERATION_INIT - * - * This macro returns a suitable initializer for a MAC operation object of type - * #psa_mac_operation_t. - */ - -/** Return an initial value for a MAC operation object. - */ -static psa_mac_operation_t psa_mac_operation_init(void); - -/** Set up a multipart MAC calculation operation. - * - * This function sets up the calculation of the MAC - * (message authentication code) of a byte string. - * To verify the MAC of a message against an - * expected value, use psa_mac_verify_setup() instead. - * - * The sequence of operations to calculate a MAC is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. - * -# Call psa_mac_sign_setup() to specify the algorithm and key. - * -# Call psa_mac_update() zero, one or more times, passing a fragment - * of the message each time. The MAC that is calculated is the MAC - * of the concatenation of these messages in order. - * -# At the end of the message, call psa_mac_sign_finish() to finish - * calculating the MAC value and retrieve it. - * - * If an error occurs at any step after a call to psa_mac_sign_setup(), the - * operation will need to be reset by a call to psa_mac_abort(). The - * application may call psa_mac_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_mac_sign_setup(), the application must - * eventually terminate the operation through one of the following methods: - * - A successful call to psa_mac_sign_finish(). - * - A call to psa_mac_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_mac_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. It - * must remain valid until the operation terminates. - * It must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set up a multipart MAC verification operation. - * - * This function sets up the verification of the MAC - * (message authentication code) of a byte string against an expected value. - * - * The sequence of operations to verify a MAC is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. - * -# Call psa_mac_verify_setup() to specify the algorithm and key. - * -# Call psa_mac_update() zero, one or more times, passing a fragment - * of the message each time. The MAC that is calculated is the MAC - * of the concatenation of these messages in order. - * -# At the end of the message, call psa_mac_verify_finish() to finish - * calculating the actual MAC of the message and verify it against - * the expected value. - * - * If an error occurs at any step after a call to psa_mac_verify_setup(), the - * operation will need to be reset by a call to psa_mac_abort(). The - * application may call psa_mac_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_mac_verify_setup(), the application must - * eventually terminate the operation through one of the following methods: - * - A successful call to psa_mac_verify_finish(). - * - A call to psa_mac_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_mac_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. It - * must remain valid until the operation terminates. - * It must allow the usage - * PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c key is not compatible with \c alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a MAC algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The key could not be retrieved from storage. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Add a message fragment to a multipart MAC operation. - * - * The application must call psa_mac_sign_setup() or psa_mac_verify_setup() - * before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \param[in,out] operation Active MAC operation. - * \param[in] input Buffer containing the message fragment to add to - * the MAC calculation. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_update(psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the MAC of a message. - * - * The application must call psa_mac_sign_setup() before calling this function. - * This function calculates the MAC of the message formed by concatenating - * the inputs passed to preceding calls to psa_mac_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \warning Applications should not call this function if they expect - * a specific value for the MAC. Call psa_mac_verify_finish() instead. - * Beware that comparing integrity or authenticity data such as - * MAC values with a function such as \c memcmp is risky - * because the time taken by the comparison may leak information - * about the MAC value which could allow an attacker to guess - * a valid MAC and thereby bypass security controls. - * - * \param[in,out] operation Active MAC operation. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Size of the \p mac buffer in bytes. - * \param[out] mac_length On success, the number of bytes - * that make up the MAC value. This is always - * #PSA_MAC_LENGTH(\c key_type, \c key_bits, \c alg) - * where \c key_type and \c key_bits are the type and - * bit-size respectively of the key and \c alg is the - * MAC algorithm that is calculated. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p mac buffer is too small. You can determine a - * sufficient buffer size by calling PSA_MAC_LENGTH(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac sign - * operation), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_sign_finish(psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Finish the calculation of the MAC of a message and compare it with - * an expected value. - * - * The application must call psa_mac_verify_setup() before calling this function. - * This function calculates the MAC of the message formed by concatenating - * the inputs passed to preceding calls to psa_mac_update(). It then - * compares the calculated MAC with the expected MAC passed as a - * parameter to this function. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_mac_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual MAC and the expected MAC is performed - * in constant time. - * - * \param[in,out] operation Active MAC operation. - * \param[in] mac Buffer containing the expected MAC value. - * \param mac_length Size of the \p mac buffer in bytes. - * - * \retval #PSA_SUCCESS - * The expected MAC is identical to the actual MAC of the message. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The MAC of the message was calculated successfully, but it - * differs from the expected MAC. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac verify - * operation), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_verify_finish(psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length); - -/** Abort a MAC operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_mac_sign_setup() or psa_mac_verify_setup() again. - * - * You may call this function any time after the operation object has - * been initialized by one of the methods described in #psa_mac_operation_t. - * - * In particular, calling psa_mac_abort() after the operation has been - * terminated by a call to psa_mac_abort(), psa_mac_sign_finish() or - * psa_mac_verify_finish() is safe and has no effect. - * - * \param[in,out] operation Initialized MAC operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_mac_abort(psa_mac_operation_t *operation); - -/**@}*/ - -/** \defgroup cipher Symmetric ciphers - * @{ - */ - -/** Encrypt a message using a symmetric cipher. - * - * This function encrypts a message with a random IV (initialization - * vector). Use the multipart operation interface with a - * #psa_cipher_operation_t object to provide other forms of IV. - * - * \param key Identifier of the key to use for the operation. - * It must allow the usage #PSA_KEY_USAGE_ENCRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to encrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * The output contains the IV followed by - * the ciphertext proper. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Decrypt a message using a symmetric cipher. - * - * This function decrypts a message encrypted with a symmetric cipher. - * - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the message to decrypt. - * This consists of the IV followed by the - * ciphertext proper. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the plaintext is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** The type of the state data structure for multipart cipher operations. - * - * Before calling any function on a cipher operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_cipher_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_cipher_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_CIPHER_OPERATION_INIT, - * for example: - * \code - * psa_cipher_operation_t operation = PSA_CIPHER_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_cipher_operation_init() - * to the structure, for example: - * \code - * psa_cipher_operation_t operation; - * operation = psa_cipher_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_cipher_operation_s psa_cipher_operation_t; - -/** \def PSA_CIPHER_OPERATION_INIT - * - * This macro returns a suitable initializer for a cipher operation object of - * type #psa_cipher_operation_t. - */ - -/** Return an initial value for a cipher operation object. - */ -static psa_cipher_operation_t psa_cipher_operation_init(void); - -/** Set the key for a multipart symmetric encryption operation. - * - * The sequence of operations to encrypt a message with a symmetric cipher - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_cipher_operation_t, e.g. - * #PSA_CIPHER_OPERATION_INIT. - * -# Call psa_cipher_encrypt_setup() to specify the algorithm and key. - * -# Call either psa_cipher_generate_iv() or psa_cipher_set_iv() to - * generate or set the IV (initialization vector). You should use - * psa_cipher_generate_iv() unless the protocol you are implementing - * requires a specific IV value. - * -# Call psa_cipher_update() zero, one or more times, passing a fragment - * of the message each time. - * -# Call psa_cipher_finish(). - * - * If an error occurs at any step after a call to psa_cipher_encrypt_setup(), - * the operation will need to be reset by a call to psa_cipher_abort(). The - * application may call psa_cipher_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_cipher_encrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_cipher_finish(). - * - A call to psa_cipher_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set the key for a multipart symmetric decryption operation. - * - * The sequence of operations to decrypt a message with a symmetric cipher - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_cipher_operation_t, e.g. - * #PSA_CIPHER_OPERATION_INIT. - * -# Call psa_cipher_decrypt_setup() to specify the algorithm and key. - * -# Call psa_cipher_set_iv() with the IV (initialization vector) for the - * decryption. If the IV is prepended to the ciphertext, you can call - * psa_cipher_update() on a buffer containing the IV followed by the - * beginning of the message. - * -# Call psa_cipher_update() zero, one or more times, passing a fragment - * of the message each time. - * -# Call psa_cipher_finish(). - * - * If an error occurs at any step after a call to psa_cipher_decrypt_setup(), - * the operation will need to be reset by a call to psa_cipher_abort(). The - * application may call psa_cipher_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_cipher_decrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_cipher_finish(). - * - A call to psa_cipher_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not a cipher algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Generate an IV for a symmetric encryption operation. - * - * This function generates a random IV (initialization vector), nonce - * or initial counter value for the encryption operation as appropriate - * for the chosen algorithm, key type and key size. - * - * The application must call psa_cipher_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[out] iv Buffer where the generated IV is to be written. - * \param iv_size Size of the \p iv buffer in bytes. - * \param[out] iv_length On success, the number of bytes of the - * generated IV. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p iv buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with no IV set), - * or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_generate_iv(psa_cipher_operation_t *operation, - uint8_t *iv, - size_t iv_size, - size_t *iv_length); - -/** Set the IV for a symmetric encryption or decryption operation. - * - * This function sets the IV (initialization vector), nonce - * or initial counter value for the encryption or decryption operation. - * - * The application must call psa_cipher_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \note When encrypting, applications should use psa_cipher_generate_iv() - * instead of this function, unless implementing a protocol that requires - * a non-random IV. - * - * \param[in,out] operation Active cipher operation. - * \param[in] iv Buffer containing the IV to use. - * \param iv_length Size of the IV in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p iv is not acceptable for the chosen algorithm, - * or the chosen algorithm does not use an IV. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active cipher - * encrypt operation, with no IV set), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_set_iv(psa_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length); - -/** Encrypt or decrypt a message fragment in an active cipher operation. - * - * Before calling this function, you must: - * 1. Call either psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup(). - * The choice of setup function determines whether this function - * encrypts or decrypts its input. - * 2. If the algorithm requires an IV, call psa_cipher_generate_iv() - * (recommended when encrypting) or psa_cipher_set_iv(). - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with an IV set - * if required for the algorithm), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_update(psa_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Finish encrypting or decrypting a message in a cipher operation. - * - * The application must call psa_cipher_encrypt_setup() or - * psa_cipher_decrypt_setup() before calling this function. The choice - * of setup function determines whether this function encrypts or - * decrypts its input. - * - * This function finishes the encryption or decryption of the message - * formed by concatenating the inputs passed to preceding calls to - * psa_cipher_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_cipher_abort(). - * - * \param[in,out] operation Active cipher operation. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total input size passed to this operation is not valid for - * this particular algorithm. For example, the algorithm is a based - * on block cipher and requires a whole number of blocks, but the - * total input size is not a multiple of the block size. - * \retval #PSA_ERROR_INVALID_PADDING - * This is a decryption operation for an algorithm that includes - * padding, and the ciphertext does not contain valid padding. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with an IV set - * if required for the algorithm), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_finish(psa_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Abort a cipher operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup() again. - * - * You may call this function any time after the operation object has - * been initialized as described in #psa_cipher_operation_t. - * - * In particular, calling psa_cipher_abort() after the operation has been - * terminated by a call to psa_cipher_abort() or psa_cipher_finish() - * is safe and has no effect. - * - * \param[in,out] operation Initialized cipher operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); - -/**@}*/ - -/** \defgroup aead Authenticated encryption with associated data (AEAD) - * @{ - */ - -/** Process an authenticated encryption operation. - * - * \param key Identifier of the key to use for the - * operation. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the \p nonce buffer in bytes. - * \param[in] additional_data Additional data that will be authenticated - * but not encrypted. - * \param additional_data_length Size of \p additional_data in bytes. - * \param[in] plaintext Data that will be authenticated and - * encrypted. - * \param plaintext_length Size of \p plaintext in bytes. - * \param[out] ciphertext Output buffer for the authenticated and - * encrypted data. The additional data is not - * part of this output. For algorithms where the - * encrypted data and the authentication tag - * are defined as separate outputs, the - * authentication tag is appended to the - * encrypted data. - * \param ciphertext_size Size of the \p ciphertext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, - * \p alg, \p plaintext_length) where - * \c key_type is the type of \p key. - * - #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p - * plaintext_length) evaluates to the maximum - * ciphertext size of any supported AEAD - * encryption. - * \param[out] ciphertext_length On success, the size of the output - * in the \p ciphertext buffer. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p ciphertext_size is too small. - * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, \p alg, - * \p plaintext_length) or - * #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length) can be used to - * determine the required buffer size. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length); - -/** Process an authenticated decryption operation. - * - * \param key Identifier of the key to use for the - * operation. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the \p nonce buffer in bytes. - * \param[in] additional_data Additional data that has been authenticated - * but not encrypted. - * \param additional_data_length Size of \p additional_data in bytes. - * \param[in] ciphertext Data that has been authenticated and - * encrypted. For algorithms where the - * encrypted data and the authentication tag - * are defined as separate inputs, the buffer - * must contain the encrypted data followed - * by the authentication tag. - * \param ciphertext_length Size of \p ciphertext in bytes. - * \param[out] plaintext Output buffer for the decrypted data. - * \param plaintext_size Size of the \p plaintext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, - * \p alg, \p ciphertext_length) where - * \c key_type is the type of \p key. - * - #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p - * ciphertext_length) evaluates to the maximum - * plaintext size of any supported AEAD - * decryption. - * \param[out] plaintext_length On success, the size of the output - * in the \p plaintext buffer. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The ciphertext is not authentic. - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p plaintext_size is too small. - * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, \p alg, - * \p ciphertext_length) or - * #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length) can be used - * to determine the required buffer size. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length); - -/** The type of the state data structure for multipart AEAD operations. - * - * Before calling any function on an AEAD operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_aead_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_aead_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_AEAD_OPERATION_INIT, - * for example: - * \code - * psa_aead_operation_t operation = PSA_AEAD_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_aead_operation_init() - * to the structure, for example: - * \code - * psa_aead_operation_t operation; - * operation = psa_aead_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_aead_operation_s psa_aead_operation_t; - -/** \def PSA_AEAD_OPERATION_INIT - * - * This macro returns a suitable initializer for an AEAD operation object of - * type #psa_aead_operation_t. - */ - -/** Return an initial value for an AEAD operation object. - */ -static psa_aead_operation_t psa_aead_operation_init(void); - -/** Set the key for a multipart authenticated encryption operation. - * - * The sequence of operations to encrypt a message with authentication - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_aead_operation_t, e.g. - * #PSA_AEAD_OPERATION_INIT. - * -# Call psa_aead_encrypt_setup() to specify the algorithm and key. - * -# If needed, call psa_aead_set_lengths() to specify the length of the - * inputs to the subsequent calls to psa_aead_update_ad() and - * psa_aead_update(). See the documentation of psa_aead_set_lengths() - * for details. - * -# Call either psa_aead_generate_nonce() or psa_aead_set_nonce() to - * generate or set the nonce. You should use - * psa_aead_generate_nonce() unless the protocol you are implementing - * requires a specific nonce value. - * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment - * of the non-encrypted additional authenticated data each time. - * -# Call psa_aead_update() zero, one or more times, passing a fragment - * of the message to encrypt each time. - * -# Call psa_aead_finish(). - * - * If an error occurs at any step after a call to psa_aead_encrypt_setup(), - * the operation will need to be reset by a call to psa_aead_abort(). The - * application may call psa_aead_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_aead_encrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_aead_finish(). - * - A call to psa_aead_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_aead_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Set the key for a multipart authenticated decryption operation. - * - * The sequence of operations to decrypt a message with authentication - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_aead_operation_t, e.g. - * #PSA_AEAD_OPERATION_INIT. - * -# Call psa_aead_decrypt_setup() to specify the algorithm and key. - * -# If needed, call psa_aead_set_lengths() to specify the length of the - * inputs to the subsequent calls to psa_aead_update_ad() and - * psa_aead_update(). See the documentation of psa_aead_set_lengths() - * for details. - * -# Call psa_aead_set_nonce() with the nonce for the decryption. - * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment - * of the non-encrypted additional authenticated data each time. - * -# Call psa_aead_update() zero, one or more times, passing a fragment - * of the ciphertext to decrypt each time. - * -# Call psa_aead_verify(). - * - * If an error occurs at any step after a call to psa_aead_decrypt_setup(), - * the operation will need to be reset by a call to psa_aead_abort(). The - * application may call psa_aead_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_aead_decrypt_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to psa_aead_verify(). - * - A call to psa_aead_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #psa_aead_operation_t and not yet in use. - * \param key Identifier of the key to use for the operation. - * It must remain valid until the operation - * terminates. It must allow the usage - * #PSA_KEY_USAGE_DECRYPT. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not compatible with \p alg. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported or is not an AEAD algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg); - -/** Generate a random nonce for an authenticated encryption operation. - * - * This function generates a random nonce for the authenticated encryption - * operation with an appropriate size for the chosen algorithm, key type - * and key size. - * - * The application must call psa_aead_encrypt_setup() before - * calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[out] nonce Buffer where the generated nonce is to be - * written. - * \param nonce_size Size of the \p nonce buffer in bytes. - * \param[out] nonce_length On success, the number of bytes of the - * generated nonce. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p nonce buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active aead encrypt - * operation, with no nonce set), or the library has not been - * previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_generate_nonce(psa_aead_operation_t *operation, - uint8_t *nonce, - size_t nonce_size, - size_t *nonce_length); - -/** Set the nonce for an authenticated encryption or decryption operation. - * - * This function sets the nonce for the authenticated - * encryption or decryption operation. - * - * The application must call psa_aead_encrypt_setup() or - * psa_aead_decrypt_setup() before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \note When encrypting, applications should use psa_aead_generate_nonce() - * instead of this function, unless implementing a protocol that requires - * a non-random IV. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] nonce Buffer containing the nonce to use. - * \param nonce_length Size of the nonce in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p nonce is not acceptable for the chosen algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, with no nonce - * set), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_set_nonce(psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length); - -/** Declare the lengths of the message and additional data for AEAD. - * - * The application must call this function before calling - * psa_aead_update_ad() or psa_aead_update() if the algorithm for - * the operation requires it. If the algorithm does not require it, - * calling this function is optional, but if this function is called - * then the implementation must enforce the lengths. - * - * You may call this function before or after setting the nonce with - * psa_aead_set_nonce() or psa_aead_generate_nonce(). - * - * - For #PSA_ALG_CCM, calling this function is required. - * - For the other AEAD algorithms defined in this specification, calling - * this function is not required. - * - For vendor-defined algorithm, refer to the vendor documentation. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param ad_length Size of the non-encrypted additional - * authenticated data in bytes. - * \param plaintext_length Size of the plaintext to encrypt in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * At least one of the lengths is not acceptable for the chosen - * algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and - * psa_aead_update_ad() and psa_aead_update() must not have been - * called yet), or the library has not been previously initialized - * by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_set_lengths(psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length); - -/** Pass additional data to an active AEAD operation. - * - * Additional data is authenticated, but not encrypted. - * - * You may call this function multiple times to pass successive fragments - * of the additional data. You may not call this function after passing - * data to encrypt or decrypt with psa_aead_update(). - * - * Before calling this function, you must: - * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). - * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, - * there is no guarantee that the input is valid. Therefore, until - * you have called psa_aead_verify() and it has returned #PSA_SUCCESS, - * treat the input as untrusted and prepare to undo any action that - * depends on the input if psa_aead_verify() returns an error status. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the fragment of - * additional data. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total input length overflows the additional data length that - * was previously specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, have a nonce - * set, have lengths set if required by the algorithm, and - * psa_aead_update() must not have been called yet), or the library - * has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_update_ad(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Encrypt or decrypt a message fragment in an active AEAD operation. - * - * Before calling this function, you must: - * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). - * The choice of setup function determines whether this function - * encrypts or decrypts its input. - * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). - * 3. Call psa_aead_update_ad() to pass all the additional data. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, - * there is no guarantee that the input is valid. Therefore, until - * you have called psa_aead_verify() and it has returned #PSA_SUCCESS: - * - Do not use the output in any way other than storing it in a - * confidential location. If you take any action that depends - * on the tentative decrypted data, this action will need to be - * undone if the input turns out not to be valid. Furthermore, - * if an adversary can observe that this action took place - * (for example through timing), they may be able to use this - * fact as an oracle to decrypt any message encrypted with the - * same key. - * - In particular, do not copy the output anywhere but to a - * memory or storage space that you have exclusive access to. - * - * This function does not require the input to be aligned to any - * particular block boundary. If the implementation can only process - * a whole block at a time, it must consume all the input provided, but - * it may delay the end of the corresponding output until a subsequent - * call to psa_aead_update(), psa_aead_finish() or psa_aead_verify() - * provides sufficient input. The amount of data that can be delayed - * in this way is bounded by #PSA_AEAD_UPDATE_OUTPUT_SIZE. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, - * \c alg, \p input_length) where - * \c key_type is the type of key and \c alg is - * the algorithm that were used to set up the - * operation. - * - #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p - * input_length) evaluates to the maximum - * output size of any supported AEAD - * algorithm. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, \c alg, \p input_length) or - * #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length) can be used to - * determine the required buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total input length overflows the plaintext length that - * was previously specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, have a nonce - * set, and have lengths set if required by the algorithm), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_update(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Finish encrypting a message in an AEAD operation. - * - * The operation must have been set up with psa_aead_encrypt_setup(). - * - * This function finishes the authentication of the additional data - * formed by concatenating the inputs passed to preceding calls to - * psa_aead_update_ad() with the plaintext formed by concatenating the - * inputs passed to preceding calls to psa_aead_update(). - * - * This function has two output buffers: - * - \p ciphertext contains trailing ciphertext that was buffered from - * preceding calls to psa_aead_update(). - * - \p tag contains the authentication tag. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[out] ciphertext Buffer where the last part of the ciphertext - * is to be written. - * \param ciphertext_size Size of the \p ciphertext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, - * \c alg) where \c key_type is the type of key - * and \c alg is the algorithm that were used to - * set up the operation. - * - #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE evaluates to - * the maximum output size of any supported AEAD - * algorithm. - * \param[out] ciphertext_length On success, the number of bytes of - * returned ciphertext. - * \param[out] tag Buffer where the authentication tag is - * to be written. - * \param tag_size Size of the \p tag buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - The exact tag size is #PSA_AEAD_TAG_LENGTH(\c - * key_type, \c key_bits, \c alg) where - * \c key_type and \c key_bits are the type and - * bit-size of the key, and \c alg is the - * algorithm that were used in the call to - * psa_aead_encrypt_setup(). - * - #PSA_AEAD_TAG_MAX_SIZE evaluates to the - * maximum tag size of any supported AEAD - * algorithm. - * \param[out] tag_length On success, the number of bytes - * that make up the returned tag. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p ciphertext or \p tag buffer is too small. - * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, \c alg) or - * #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE can be used to determine the - * required \p ciphertext buffer size. #PSA_AEAD_TAG_LENGTH(\c key_type, - * \c key_bits, \c alg) or #PSA_AEAD_TAG_MAX_SIZE can be used to - * determine the required \p tag buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total length of input to psa_aead_update() so far is - * less than the plaintext length that was previously - * specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active encryption - * operation with a nonce set), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_finish(psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length); - -/** Finish authenticating and decrypting a message in an AEAD operation. - * - * The operation must have been set up with psa_aead_decrypt_setup(). - * - * This function finishes the authenticated decryption of the message - * components: - * - * - The additional data consisting of the concatenation of the inputs - * passed to preceding calls to psa_aead_update_ad(). - * - The ciphertext consisting of the concatenation of the inputs passed to - * preceding calls to psa_aead_update(). - * - The tag passed to this function call. - * - * If the authentication tag is correct, this function outputs any remaining - * plaintext and reports success. If the authentication tag is not correct, - * this function returns #PSA_ERROR_INVALID_SIGNATURE. - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_aead_abort(). - * - * \note Implementations shall make the best effort to ensure that the - * comparison between the actual tag and the expected tag is performed - * in constant time. - * - * \param[in,out] operation Active AEAD operation. - * \param[out] plaintext Buffer where the last part of the plaintext - * is to be written. This is the remaining data - * from previous calls to psa_aead_update() - * that could not be processed until the end - * of the input. - * \param plaintext_size Size of the \p plaintext buffer in bytes. - * This must be appropriate for the selected algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, - * \c alg) where \c key_type is the type of key - * and \c alg is the algorithm that were used to - * set up the operation. - * - #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE evaluates to - * the maximum output size of any supported AEAD - * algorithm. - * \param[out] plaintext_length On success, the number of bytes of - * returned plaintext. - * \param[in] tag Buffer containing the authentication tag. - * \param tag_length Size of the \p tag buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculations were successful, but the authentication tag is - * not correct. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p plaintext buffer is too small. - * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, \c alg) or - * #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE can be used to determine the - * required buffer size. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total length of input to psa_aead_update_ad() so far is - * less than the additional data length that was previously - * specified with psa_aead_set_lengths(), or - * the total length of input to psa_aead_update() so far is - * less than the plaintext length that was previously - * specified with psa_aead_set_lengths(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active decryption - * operation with a nonce set), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_verify(psa_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length); - -/** Abort an AEAD operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * psa_aead_encrypt_setup() or psa_aead_decrypt_setup() again. - * - * You may call this function any time after the operation object has - * been initialized as described in #psa_aead_operation_t. - * - * In particular, calling psa_aead_abort() after the operation has been - * terminated by a call to psa_aead_abort(), psa_aead_finish() or - * psa_aead_verify() is safe and has no effect. - * - * \param[in,out] operation Initialized AEAD operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_aead_abort(psa_aead_operation_t *operation); - -/**@}*/ - -/** \defgroup asymmetric Asymmetric cryptography - * @{ - */ - -/** - * \brief Sign a message with a private key. For hash-and-sign algorithms, - * this includes the hashing step. - * - * \note To perform a multi-part hash-and-sign signature algorithm, first use - * a multi-part hash operation and then pass the resulting hash to - * psa_sign_hash(). PSA_ALG_GET_HASH(\p alg) can be used to determine the - * hash algorithm to use. - * - * \param[in] key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_MESSAGE. - * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) - * is true), that is compatible with the type of - * \p key. - * \param[in] input The input message to sign. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. This - * must be appropriate for the selected - * algorithm and key: - * - The required signature size is - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and - * bit-size respectively of key. - * - #PSA_SIGNATURE_MAX_SIZE evaluates to the - * maximum signature size of any supported - * signature algorithm. - * \param[out] signature_length On success, the number of bytes that make up - * the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, - * or it does not permit the requested algorithm. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); - -/** \brief Verify the signature of a message with a public key, using - * a hash-and-sign verification algorithm. - * - * \note To perform a multi-part hash-and-sign signature verification - * algorithm, first use a multi-part hash operation to hash the message - * and then pass the resulting hash to psa_verify_hash(). - * PSA_ALG_GET_HASH(\p alg) can be used to determine the hash algorithm - * to use. - * - * \param[in] key Identifier of the key to use for the operation. - * It must be a public key or an asymmetric key - * pair. The key must allow the usage - * #PSA_KEY_USAGE_VERIFY_MESSAGE. - * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) - * is true), that is compatible with the type of - * \p key. - * \param[in] input The message whose signature is to be verified. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, - * or it does not permit the requested algorithm. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed signature - * is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length); - -/** - * \brief Sign a hash or short message with a private key. - * - * Note that to perform a hash-and-sign signature algorithm, you must - * first calculate the hash by calling psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). - * Then pass the resulting hash as the \p hash - * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) - * to determine the hash algorithm to use. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_HASH. - * \param alg A signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message to sign. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); - -/** - * \brief Verify the signature of a hash or short message using a public key. - * - * Note that to perform a hash-and-sign signature algorithm, you must - * first calculate the hash by calling psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). - * Then pass the resulting hash as the \p hash - * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) - * to determine the hash algorithm to use. - * - * \param key Identifier of the key to use for the operation. It - * must be a public key or an asymmetric key pair. The - * key must allow the usage - * #PSA_KEY_USAGE_VERIFY_HASH. - * \param alg A signature algorithm (PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message whose signature is to be - * verified. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length); - -/** - * \brief Encrypt a short message with a public key. - * - * \param key Identifier of the key to use for the operation. - * It must be a public key or an asymmetric key - * pair. It must allow the usage - * #PSA_KEY_USAGE_ENCRYPT. - * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p key. - * \param[in] input The message to encrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the encrypted message is to - * be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** - * \brief Decrypt a short message with a private key. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. It must - * allow the usage #PSA_KEY_USAGE_DECRYPT. - * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p key. - * \param[in] input The message to decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the decrypted message is to - * be written. - * \param output_size Size of the \c output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INVALID_PADDING \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/**@}*/ - -/** \defgroup key_derivation Key derivation and pseudorandom generation - * @{ - */ - -/** The type of the state data structure for key derivation operations. - * - * Before calling any function on a key derivation operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_key_derivation_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_key_derivation_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_KEY_DERIVATION_OPERATION_INIT, - * for example: - * \code - * psa_key_derivation_operation_t operation = PSA_KEY_DERIVATION_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_key_derivation_operation_init() - * to the structure, for example: - * \code - * psa_key_derivation_operation_t operation; - * operation = psa_key_derivation_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. - */ -typedef struct psa_key_derivation_s psa_key_derivation_operation_t; - -/** \def PSA_KEY_DERIVATION_OPERATION_INIT - * - * This macro returns a suitable initializer for a key derivation operation - * object of type #psa_key_derivation_operation_t. - */ - -/** Return an initial value for a key derivation operation object. - */ -static psa_key_derivation_operation_t psa_key_derivation_operation_init(void); - -/** Set up a key derivation operation. - * - * A key derivation algorithm takes some inputs and uses them to generate - * a byte stream in a deterministic way. - * This byte stream can be used to produce keys and other - * cryptographic material. - * - * To derive a key: - * -# Start with an initialized object of type #psa_key_derivation_operation_t. - * -# Call psa_key_derivation_setup() to select the algorithm. - * -# Provide the inputs for the key derivation by calling - * psa_key_derivation_input_bytes() or psa_key_derivation_input_key() - * as appropriate. Which inputs are needed, in what order, and whether - * they may be keys and if so of what type depends on the algorithm. - * -# Optionally set the operation's maximum capacity with - * psa_key_derivation_set_capacity(). You may do this before, in the middle - * of or after providing inputs. For some algorithms, this step is mandatory - * because the output depends on the maximum capacity. - * -# To derive a key, call psa_key_derivation_output_key(). - * To derive a byte string for a different purpose, call - * psa_key_derivation_output_bytes(). - * Successive calls to these functions use successive output bytes - * calculated by the key derivation algorithm. - * -# Clean up the key derivation operation object with - * psa_key_derivation_abort(). - * - * If this function returns an error, the key derivation operation object is - * not changed. - * - * If an error occurs at any step after a call to psa_key_derivation_setup(), - * the operation will need to be reset by a call to psa_key_derivation_abort(). - * - * Implementations must reject an attempt to derive a key of size 0. - * - * \param[in,out] operation The key derivation operation object - * to set up. It must - * have been initialized but not set up yet. - * \param alg The key derivation algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c alg is not a key derivation algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a key derivation algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_setup( - psa_key_derivation_operation_t *operation, - psa_algorithm_t alg); - -/** Retrieve the current capacity of a key derivation operation. - * - * The capacity of a key derivation is the maximum number of bytes that it can - * return. When you get *N* bytes of output from a key derivation operation, - * this reduces its capacity by *N*. - * - * \param[in] operation The operation to query. - * \param[out] capacity On success, the capacity of the operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_get_capacity( - const psa_key_derivation_operation_t *operation, - size_t *capacity); - -/** Set the maximum capacity of a key derivation operation. - * - * The capacity of a key derivation operation is the maximum number of bytes - * that the key derivation operation can return from this point onwards. - * - * \param[in,out] operation The key derivation operation object to modify. - * \param capacity The new capacity of the operation. - * It must be less or equal to the operation's - * current capacity. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p capacity is larger than the operation's current capacity. - * In this case, the operation object remains valid and its capacity - * remains unchanged. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active), or the - * library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_set_capacity( - psa_key_derivation_operation_t *operation, - size_t capacity); - -/** Use the maximum possible capacity for a key derivation operation. - * - * Use this value as the capacity argument when setting up a key derivation - * to indicate that the operation should have the maximum possible capacity. - * The value of the maximum possible capacity depends on the key derivation - * algorithm. - */ -#define PSA_KEY_DERIVATION_UNLIMITED_CAPACITY ((size_t) (-1)) - -/** Provide an input for key derivation or key agreement. - * - * Which inputs are required and in what order depends on the algorithm. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function passes direct inputs, which is usually correct for - * non-secret inputs. To pass a secret input, which should be in a key - * object, call psa_key_derivation_input_key() instead of this function. - * Refer to the documentation of individual step types - * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) - * for more information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param[in] data Input data to use. - * \param data_length Size of the \p data buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow direct inputs. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_bytes( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length); - -/** Provide a numeric input for key derivation or key agreement. - * - * Which inputs are required and in what order depends on the algorithm. - * However, when an algorithm requires a particular order, numeric inputs - * usually come first as they tend to be configuration parameters. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function is used for inputs which are fixed-size non-negative - * integers. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param[in] value The value of the numeric input. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow numeric inputs. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_integer( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - uint64_t value); - -/** Provide an input for key derivation in the form of a key. - * - * Which inputs are required and in what order depends on the algorithm. - * Refer to the documentation of each key derivation or key agreement - * algorithm for information. - * - * This function obtains input from a key object, which is usually correct for - * secret inputs or for non-secret personalization strings kept in the key - * store. To pass a non-secret parameter which is not in the key store, - * call psa_key_derivation_input_bytes() instead of this function. - * Refer to the documentation of individual step types - * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) - * for more information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() and must not - * have produced any output yet. - * \param step Which step the input data is for. - * \param key Identifier of the key. It must have an - * appropriate type for step and must allow the - * usage #PSA_KEY_USAGE_DERIVE or - * #PSA_KEY_USAGE_VERIFY_DERIVATION (see note) - * and the algorithm used by the operation. - * - * \note Once all inputs steps are completed, the operations will allow: - * - psa_key_derivation_output_bytes() if each input was either a direct input - * or a key with #PSA_KEY_USAGE_DERIVE set; - * - psa_key_derivation_output_key() if the input for step - * #PSA_KEY_DERIVATION_INPUT_SECRET or #PSA_KEY_DERIVATION_INPUT_PASSWORD - * was from a key slot with #PSA_KEY_USAGE_DERIVE and each other input was - * either a direct input or a key with #PSA_KEY_USAGE_DERIVE set; - * - psa_key_derivation_verify_bytes() if each input was either a direct input - * or a key with #PSA_KEY_USAGE_VERIFY_DERIVATION set; - * - psa_key_derivation_verify_key() under the same conditions as - * psa_key_derivation_verify_bytes(). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key allows neither #PSA_KEY_USAGE_DERIVE nor - * #PSA_KEY_USAGE_VERIFY_DERIVATION, or it doesn't allow this - * algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c step is not compatible with the operation's algorithm, or - * \c step does not allow key inputs of the given type - * or does not allow key inputs at all. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this input \p step, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_input_key( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t key); - -/** Perform a single-shot key derivation operation and output the resulting key. - * - * NOTE: this is a Silicon Labs custom API, and is not a part of the official - * PSA Cryptography specification. - * - * This function supports HKDF and PBKDF2. - * - * This function obtains its secret input from a key object, and any additional - * inputs such as buffers and integers. The output of this function is a key - * object containing the output of the selected key derivation function. - * - * \param alg The key derivation algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). - * \param key_in Identifier of the secret key to input to the - * operation. It must allow the usage - * PSA_KEY_USAGE_DERIVE and be of a symmetric - * type. - * \param[in] info A context- and application specific - * information string. Only used for HKDF, but - * can be omitted. - * \param info_length The length of the provided info in bytes. - * \param[in] salt An optional salt value (a non-secret random value). - * Used for both HKDF and PBKDF2. Recommended for - * PBKDF2. - * \param salt_length The length of the provided salt in bytes. - * \param iterations The number of iterations to use. Maximum - * supported value is 16384. Only used for PBKDF2. - * \param[in] key_out_attributes The attributes for the new key output by the - * derivation operation. The key must be of a - * symmetric type. - * \param[out] key_out The identifier of the new key output by the - * derivation operation. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE - * \retval #PSA_ERROR_NOT_PERMITTED - * The input key does not have the required usage policy set. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The input- or output key is not of a symmetric type. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The input- or output key is larger than what the SE can handle. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The requested algorithm is not supported. - * \retval #PSA_ERROR_HARDWARE_FAILURE - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * \retval #PSA_ERROR_STORAGE_FAILURE - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t sl_psa_key_derivation_single_shot( - psa_algorithm_t alg, - mbedtls_svc_key_id_t key_in, - const uint8_t *info, - size_t info_length, - const uint8_t *salt, - size_t salt_length, - size_t iterations, - const psa_key_attributes_t *key_out_attributes, - mbedtls_svc_key_id_t *key_out); - -/** Perform a key agreement and use the shared secret as input to a key - * derivation. - * - * A key agreement algorithm takes two inputs: a private key \p private_key - * a public key \p peer_key. - * The result of this function is passed as input to a key derivation. - * The output of this key derivation can be extracted by reading from the - * resulting operation to produce keys and other cryptographic material. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to use. - * It must have been set up with - * psa_key_derivation_setup() with a - * key agreement and derivation algorithm - * \c alg (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_KEY_AGREEMENT(\c alg) is true - * and #PSA_ALG_IS_RAW_KEY_AGREEMENT(\c alg) - * is false). - * The operation must be ready for an - * input of the type given by \p step. - * \param step Which step the input data is for. - * \param private_key Identifier of the private key to use. It must - * allow the usage #PSA_KEY_USAGE_DERIVE. - * \param[in] peer_key Public key of the peer. The peer key must be in the - * same format that psa_import_key() accepts for the - * public key type corresponding to the type of - * private_key. That is, this function performs the - * equivalent of - * #psa_import_key(..., - * `peer_key`, `peer_key_length`) where - * with key attributes indicating the public key - * type corresponding to the type of `private_key`. - * For example, for EC keys, this means that peer_key - * is interpreted as a point on the curve that the - * private key is on. The standard formats for public - * keys are documented in the documentation of - * psa_export_public_key(). - * \param peer_key_length Size of \p peer_key in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c private_key is not compatible with \c alg, - * or \p peer_key is not valid for \c alg or not compatible with - * \c private_key, or \c step does not allow an input resulting - * from a key agreement. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \c alg is not supported or is not a key derivation algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid for this key agreement \p step, - * or the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_key_agreement( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length); - -/** Read some data from a key derivation operation. - * - * This function calculates output bytes from a key derivation algorithm and - * return those bytes. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the requested number of bytes from the - * stream. - * The operation's capacity decreases by the number of bytes read. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[out] output Buffer where the output will be written. - * \param output_length Number of bytes to output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * One of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_DERIVE. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * \p output_length bytes. Note that in this case, - * no output is written to the output buffer. - * The operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller output buffer. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_output_bytes( - psa_key_derivation_operation_t *operation, - uint8_t *output, - size_t output_length); - -/** Derive a key from an ongoing key derivation operation. - * - * This function calculates output bytes from a key derivation algorithm - * and uses those bytes to generate a key deterministically. - * The key's location, usage policy, type and size are taken from - * \p attributes. - * - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads as many bytes as required from the - * stream. - * The operation's capacity decreases by the number of bytes read. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error - * state and must be aborted by calling psa_key_derivation_abort(). - * - * How much output is produced and consumed from the operation, and how - * the key is derived, depends on the key type and on the key size - * (denoted \c bits below): - * - * - For key types for which the key is an arbitrary sequence of bytes - * of a given size, this function is functionally equivalent to - * calling #psa_key_derivation_output_bytes - * and passing the resulting output to #psa_import_key. - * However, this function has a security benefit: - * if the implementation provides an isolation boundary then - * the key material is not exposed outside the isolation boundary. - * As a consequence, for these key types, this function always consumes - * exactly (\c bits / 8) bytes from the operation. - * The following key types defined in this specification follow this scheme: - * - * - #PSA_KEY_TYPE_AES; - * - #PSA_KEY_TYPE_ARIA; - * - #PSA_KEY_TYPE_CAMELLIA; - * - #PSA_KEY_TYPE_DERIVE; - * - #PSA_KEY_TYPE_HMAC; - * - #PSA_KEY_TYPE_PASSWORD_HASH. - * - * - For ECC keys on a Montgomery elliptic curve - * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a - * Montgomery curve), this function always draws a byte string whose - * length is determined by the curve, and sets the mandatory bits - * accordingly. That is: - * - * - Curve25519 (#PSA_ECC_FAMILY_MONTGOMERY, 255 bits): draw a 32-byte - * string and process it as specified in RFC 7748 §5. - * - Curve448 (#PSA_ECC_FAMILY_MONTGOMERY, 448 bits): draw a 56-byte - * string and process it as specified in RFC 7748 §5. - * - * - For key types for which the key is represented by a single sequence of - * \c bits bits with constraints as to which bit sequences are acceptable, - * this function draws a byte string of length (\c bits / 8) bytes rounded - * up to the nearest whole number of bytes. If the resulting byte string - * is acceptable, it becomes the key, otherwise the drawn bytes are discarded. - * This process is repeated until an acceptable byte string is drawn. - * The byte string drawn from the operation is interpreted as specified - * for the output produced by psa_export_key(). - * The following key types defined in this specification follow this scheme: - * - * - #PSA_KEY_TYPE_DES. - * Force-set the parity bits, but discard forbidden weak keys. - * For 2-key and 3-key triple-DES, the three keys are generated - * successively (for example, for 3-key triple-DES, - * if the first 8 bytes specify a weak key and the next 8 bytes do not, - * discard the first 8 bytes, use the next 8 bytes as the first key, - * and continue reading output from the operation to derive the other - * two keys). - * - Finite-field Diffie-Hellman keys (#PSA_KEY_TYPE_DH_KEY_PAIR(\c group) - * where \c group designates any Diffie-Hellman group) and - * ECC keys on a Weierstrass elliptic curve - * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a - * Weierstrass curve). - * For these key types, interpret the byte string as integer - * in big-endian order. Discard it if it is not in the range - * [0, *N* - 2] where *N* is the boundary of the private key domain - * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, - * or the order of the curve's base point for ECC). - * Add 1 to the resulting integer and use this as the private key *x*. - * This method allows compliance to NIST standards, specifically - * the methods titled "key-pair generation by testing candidates" - * in NIST SP 800-56A §5.6.1.1.4 for Diffie-Hellman, - * in FIPS 186-4 §B.1.2 for DSA, and - * in NIST SP 800-56A §5.6.1.2.2 or - * FIPS 186-4 §B.4.2 for elliptic curve keys. - * - * - For other key types, including #PSA_KEY_TYPE_RSA_KEY_PAIR, - * the way in which the operation output is consumed is - * implementation-defined. - * - * In all cases, the data that is read is discarded from the operation. - * The operation's capacity is decreased by the number of bytes read. - * - * For algorithms that take an input step #PSA_KEY_DERIVATION_INPUT_SECRET, - * the input to that step must be provided with psa_key_derivation_input_key(). - * Future versions of this specification may include additional restrictions - * on the derived key based on the attributes and strength of the secret key. - * - * \param[in] attributes The attributes for the new key. - * If the key type to be created is - * #PSA_KEY_TYPE_PASSWORD_HASH then the algorithm in - * the policy must be the same as in the current - * operation. - * \param[in,out] operation The key derivation operation object to read from. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * There was not enough data to create the desired key. - * Note that in this case, no output is written to the output buffer. - * The operation's capacity is set to 0, thus subsequent calls to - * this function will not succeed, even with a smaller output buffer. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size is not supported, either by the - * implementation in general or in this particular location. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The provided key attributes are not valid for the operation. - * \retval #PSA_ERROR_NOT_PERMITTED - * The #PSA_KEY_DERIVATION_INPUT_SECRET or - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input was not provided through a - * key; or one of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_DERIVE. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_output_key( - const psa_key_attributes_t *attributes, - psa_key_derivation_operation_t *operation, - mbedtls_svc_key_id_t *key); - -/** Compare output data from a key derivation operation to an expected value. - * - * This function calculates output bytes from a key derivation algorithm and - * compares those bytes to an expected value in constant time. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the expected number of bytes from the - * stream before comparing them. - * The operation's capacity decreases by the number of bytes read. - * - * This is functionally equivalent to the following code: - * \code - * psa_key_derivation_output_bytes(operation, tmp, output_length); - * if (memcmp(output, tmp, output_length) != 0) - * return PSA_ERROR_INVALID_SIGNATURE; - * \endcode - * except (1) it works even if the key's policy does not allow outputting the - * bytes, and (2) the comparison will be done in constant time. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, - * the operation enters an error state and must be aborted by calling - * psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[in] expected_output Buffer containing the expected derivation output. - * \param output_length Length of the expected output; this is also the - * number of bytes that will be read. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The output was read successfully, but it differs from the expected - * output. - * \retval #PSA_ERROR_NOT_PERMITTED - * One of the inputs was a key whose policy didn't allow - * #PSA_KEY_USAGE_VERIFY_DERIVATION. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * \p output_length bytes. Note that in this case, - * the operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller expected output. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_verify_bytes( - psa_key_derivation_operation_t *operation, - const uint8_t *expected_output, - size_t output_length); - -/** Compare output data from a key derivation operation to an expected value - * stored in a key object. - * - * This function calculates output bytes from a key derivation algorithm and - * compares those bytes to an expected value, provided as key of type - * #PSA_KEY_TYPE_PASSWORD_HASH. - * If you view the key derivation's output as a stream of bytes, this - * function destructively reads the number of bytes corresponding to the - * length of the expected value from the stream before comparing them. - * The operation's capacity decreases by the number of bytes read. - * - * This is functionally equivalent to exporting the key and calling - * psa_key_derivation_verify_bytes() on the result, except that it - * works even if the key cannot be exported. - * - * If this function returns an error status other than - * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, - * the operation enters an error state and must be aborted by calling - * psa_key_derivation_abort(). - * - * \param[in,out] operation The key derivation operation object to read from. - * \param[in] expected A key of type #PSA_KEY_TYPE_PASSWORD_HASH - * containing the expected output. Its policy must - * include the #PSA_KEY_USAGE_VERIFY_DERIVATION flag - * and the permitted algorithm must match the - * operation. The value of this key was likely - * computed by a previous call to - * psa_key_derivation_output_key(). - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The output was read successfully, but if differs from the expected - * output. - * \retval #PSA_ERROR_INVALID_HANDLE - * The key passed as the expected value does not exist. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key passed as the expected value has an invalid type. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key passed as the expected value does not allow this usage or - * this algorithm; or one of the inputs was a key whose policy didn't - * allow #PSA_KEY_USAGE_VERIFY_DERIVATION. - * \retval #PSA_ERROR_INSUFFICIENT_DATA - * The operation's capacity was less than - * the length of the expected value. In this case, - * the operation's capacity is set to 0, thus - * subsequent calls to this function will not - * succeed, even with a smaller expected output. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active and completed - * all required input steps), or the library has not been previously - * initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_verify_key( - psa_key_derivation_operation_t *operation, - psa_key_id_t expected); - -/** Abort a key derivation operation. - * - * Aborting an operation frees all associated resources except for the \c - * operation structure itself. Once aborted, the operation object can be reused - * for another operation by calling psa_key_derivation_setup() again. - * - * This function may be called at any time after the operation - * object has been initialized as described in #psa_key_derivation_operation_t. - * - * In particular, it is valid to call psa_key_derivation_abort() twice, or to - * call psa_key_derivation_abort() on an operation that has not been set up. - * - * \param[in,out] operation The operation to abort. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_key_derivation_abort( - psa_key_derivation_operation_t *operation); - -/** Perform a key agreement and return the raw shared secret. - * - * \warning The raw result of a key agreement algorithm such as finite-field - * Diffie-Hellman or elliptic curve Diffie-Hellman has biases and should - * not be used directly as key material. It should instead be passed as - * input to a key derivation algorithm. To chain a key agreement with - * a key derivation, use psa_key_derivation_key_agreement() and other - * functions from the key derivation interface. - * - * \param alg The key agreement algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_RAW_KEY_AGREEMENT(\p alg) - * is true). - * \param private_key Identifier of the private key to use. It must - * allow the usage #PSA_KEY_USAGE_DERIVE. - * \param[in] peer_key Public key of the peer. It must be - * in the same format that psa_import_key() - * accepts. The standard formats for public - * keys are documented in the documentation - * of psa_export_public_key(). - * \param peer_key_length Size of \p peer_key in bytes. - * \param[out] output Buffer where the decrypted message is to - * be written. - * \param output_size Size of the \c output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a key agreement algorithm, or - * \p private_key is not compatible with \p alg, - * or \p peer_key is not valid for \p alg or not compatible with - * \p private_key. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p output_size is too small - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported key agreement algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/**@}*/ - -/** \defgroup random Random generation - * @{ - */ - -/** - * \brief Generate random bytes. - * - * \warning This function **can** fail! Callers MUST check the return status - * and MUST NOT use the content of the output buffer if the return - * status is not #PSA_SUCCESS. - * - * \note To generate a key, use psa_generate_key() instead. - * - * \param[out] output Output buffer for the generated data. - * \param output_size Number of bytes to generate and output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_generate_random(uint8_t *output, - size_t output_size); - -/** - * \brief Generate a key or key pair. - * - * The key is generated randomly. - * Its location, usage policy, type and size are taken from \p attributes. - * - * Implementations must reject an attempt to generate a key of size 0. - * - * The following type-specific considerations apply: - * - For RSA keys (#PSA_KEY_TYPE_RSA_KEY_PAIR), - * the public exponent is 65537. - * The modulus is a product of two probabilistic primes - * between 2^{n-1} and 2^n where n is the bit size specified in the - * attributes. - * - * \param[in] attributes The attributes for the new key. - * \param[out] key On success, an identifier for the newly created - * key. For persistent keys, this is the key - * identifier defined in \p attributes. - * \c 0 on failure. - * - * \retval #PSA_SUCCESS - * Success. - * If the key is persistent, the key material and the key's metadata - * have been saved to persistent storage. - * \retval #PSA_ERROR_ALREADY_EXISTS - * This is an attempt to create a persistent key, and there is - * already a persistent key with the given identifier. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t *key); - -/**@}*/ - -/** \defgroup interruptible_hash Interruptible sign/verify hash - * @{ - */ - -/** The type of the state data structure for interruptible hash - * signing operations. - * - * Before calling any function on a sign hash operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer - * #PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: - * \code - * psa_sign_hash_interruptible_operation_t operation = - * PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; - * \endcode - * - Assign the result of the function - * psa_sign_hash_interruptible_operation_init() to the structure, for - * example: - * \code - * psa_sign_hash_interruptible_operation_t operation; - * operation = psa_sign_hash_interruptible_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_sign_hash_interruptible_operation_s psa_sign_hash_interruptible_operation_t; - -/** The type of the state data structure for interruptible hash - * verification operations. - * - * Before calling any function on a sign hash operation object, the - * application must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer - * #PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: - * \code - * psa_verify_hash_interruptible_operation_t operation = - * PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; - * \endcode - * - Assign the result of the function - * psa_verify_hash_interruptible_operation_init() to the structure, for - * example: - * \code - * psa_verify_hash_interruptible_operation_t operation; - * operation = psa_verify_hash_interruptible_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_verify_hash_interruptible_operation_s psa_verify_hash_interruptible_operation_t; - -/** - * \brief Set the maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note The time taken to execute a single op is - * implementation specific and depends on - * software, hardware, the algorithm, key type and - * curve chosen. Even within a single operation, - * successive ops can take differing amounts of - * time. The only guarantee is that lower values - * for \p max_ops means functions will block for a - * lesser maximum amount of time. The functions - * \c psa_sign_interruptible_get_num_ops() and - * \c psa_verify_interruptible_get_num_ops() are - * provided to help with tuning this value. - * - * \note This value defaults to - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, which - * means the whole operation will be done in one - * go, regardless of the number of ops required. - * - * \note If more ops are needed to complete a - * computation, #PSA_OPERATION_INCOMPLETE will be - * returned by the function performing the - * computation. It is then the caller's - * responsibility to either call again with the - * same operation context until it returns 0 or an - * error code; or to call the relevant abort - * function if the answer is no longer required. - * - * \note The interpretation of \p max_ops is also - * implementation defined. On a hard real time - * system, this can indicate a hard deadline, as a - * real-time system needs a guarantee of not - * spending more than X time, however care must be - * taken in such an implementation to avoid the - * situation whereby calls just return, not being - * able to do any actual work within the allotted - * time. On a non-real-time system, the - * implementation can be more relaxed, but again - * whether this number should be interpreted as as - * hard or soft limit or even whether a less than - * or equals as regards to ops executed in a - * single call is implementation defined. - * - * \note For keys in local storage when no accelerator - * driver applies, please see also the - * documentation for \c mbedtls_ecp_set_max_ops(), - * which is the internal implementation in these - * cases. - * - * \warning With implementations that interpret this number - * as a hard limit, setting this number too small - * may result in an infinite loop, whereby each - * call results in immediate return with no ops - * done (as there is not enough time to execute - * any), and thus no result will ever be achieved. - * - * \note This only applies to functions whose - * documentation mentions they may return - * #PSA_OPERATION_INCOMPLETE. - * - * \param max_ops The maximum number of ops to be executed in a - * single call. This can be a number from 0 to - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, where 0 - * is the least amount of work done per call. - */ -void psa_interruptible_set_max_ops(uint32_t max_ops); - -/** - * \brief Get the maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. This will return the last - * value set by - * \c psa_interruptible_set_max_ops() or - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED if - * that function has never been called. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \return Maximum number of ops allowed to be - * executed by an interruptible function in a - * single call. - */ -uint32_t psa_interruptible_get_max_ops(void); - -/** - * \brief Get the number of ops that a hash signing - * operation has taken so far. If the operation - * has completed, then this will represent the - * number of ops required for the entire - * operation. After initialization or calling - * \c psa_sign_hash_interruptible_abort() on - * the operation, a value of 0 will be returned. - * - * \note This interface is guaranteed re-entrant and - * thus may be called from driver code. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * This is a helper provided to help you tune the - * value passed to \c - * psa_interruptible_set_max_ops(). - * - * \param operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \return Number of ops that the operation has taken so - * far. - */ -uint32_t psa_sign_hash_get_num_ops( - const psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Get the number of ops that a hash verification - * operation has taken so far. If the operation - * has completed, then this will represent the - * number of ops required for the entire - * operation. After initialization or calling \c - * psa_verify_hash_interruptible_abort() on the - * operation, a value of 0 will be returned. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * This is a helper provided to help you tune the - * value passed to \c - * psa_interruptible_set_max_ops(). - * - * \param operation The \c - * psa_verify_hash_interruptible_operation_t to - * use. This must be initialized first. - * - * \return Number of ops that the operation has taken so - * far. - */ -uint32_t psa_verify_hash_get_num_ops( - const psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Start signing a hash or short message with a - * private key, in an interruptible manner. - * - * \see \c psa_sign_hash_complete() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_sign_hash_complete() is equivalent to - * \c psa_sign_hash() but - * \c psa_sign_hash_complete() can return early and - * resume according to the limit set with \c - * psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function call. - * - * \note Users should call \c psa_sign_hash_complete() - * repeatedly on the same context after a - * successful call to this function until \c - * psa_sign_hash_complete() either returns 0 or an - * error. \c psa_sign_hash_complete() will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_sign_hash_abort() at any point if they no - * longer want the result. - * - * \note If this function returns an error status, the - * operation enters an error state and must be - * aborted by calling \c psa_sign_hash_abort(). - * - * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \param key Identifier of the key to use for the operation. - * It must be an asymmetric key pair. The key must - * allow the usage #PSA_KEY_USAGE_SIGN_HASH. - * \param alg A signature algorithm (\c PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash or message to sign. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - call \c psa_sign_hash_complete() - * with the same context to complete the operation - * - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_SIGN_HASH flag, or it does - * not permit the requested algorithm. - * \retval #PSA_ERROR_BAD_STATE - * An operation has previously been started on this context, and is - * still in progress. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash_start( - psa_sign_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length); - -/** - * \brief Continue and eventually complete the action of - * signing a hash or short message with a private - * key, in an interruptible manner. - * - * \see \c psa_sign_hash_start() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_sign_hash_start() is equivalent to - * \c psa_sign_hash() but this function can return - * early and resume according to the limit set with - * \c psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function call. - * - * \note Users should call this function on the same - * operation object repeatedly until it either - * returns 0 or an error. This function will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_sign_hash_abort() at any point if they no - * longer want the result. - * - * \note When this function returns successfully, the - * operation becomes inactive. If this function - * returns an error status, the operation enters an - * error state and must be aborted by calling - * \c psa_sign_hash_abort(). - * - * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first, and have - * had \c psa_sign_hash_start() called with it - * first. - * - * \param[out] signature Buffer where the signature is to be written. - * \param signature_size Size of the \p signature buffer in bytes. This - * must be appropriate for the selected - * algorithm and key: - * - The required signature size is - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c - * key_bits, \c alg) where \c key_type and \c - * key_bits are the type and bit-size - * respectively of key. - * - #PSA_SIGNATURE_MAX_SIZE evaluates to the - * maximum signature size of any supported - * signature algorithm. - * \param[out] signature_length On success, the number of bytes that make up - * the returned signature value. - * - * \retval #PSA_SUCCESS - * Operation completed successfully - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(). There is still work to be done. - * Call this function again with the same operation object. - * - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \c alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \c key. - * - * \retval #PSA_ERROR_BAD_STATE - * An operation was not previously started on this context via - * \c psa_sign_hash_start(). - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has either not been previously initialized by - * psa_crypto_init() or you did not previously call - * psa_sign_hash_start() with this operation object. It is - * implementation-dependent whether a failure to initialize results in - * this error code. - */ -psa_status_t psa_sign_hash_complete( - psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length); - -/** - * \brief Abort a sign hash operation. - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function is the only function that clears - * the number of ops completed as part of the - * operation. Please ensure you copy this value via - * \c psa_sign_hash_get_num_ops() if required - * before calling. - * - * \note Aborting an operation frees all associated - * resources except for the \p operation structure - * itself. Once aborted, the operation object can - * be reused for another operation by calling \c - * psa_sign_hash_start() again. - * - * \note You may call this function any time after the - * operation object has been initialized. In - * particular, calling \c psa_sign_hash_abort() - * after the operation has already been terminated - * by a call to \c psa_sign_hash_abort() or - * psa_sign_hash_complete() is safe. - * - * \param[in,out] operation Initialized sign hash operation. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_sign_hash_abort( - psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Start reading and verifying a hash or short - * message, in an interruptible manner. - * - * \see \c psa_verify_hash_complete() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_verify_hash_complete() is equivalent to - * \c psa_verify_hash() but \c - * psa_verify_hash_complete() can return early and - * resume according to the limit set with \c - * psa_interruptible_set_max_ops() to reduce the - * maximum time spent in a function. - * - * \note Users should call \c psa_verify_hash_complete() - * repeatedly on the same operation object after a - * successful call to this function until \c - * psa_verify_hash_complete() either returns 0 or - * an error. \c psa_verify_hash_complete() will - * return #PSA_OPERATION_INCOMPLETE if there is - * more work to do. Alternatively users can call - * \c psa_verify_hash_abort() at any point if they - * no longer want the result. - * - * \note If this function returns an error status, the - * operation enters an error state and must be - * aborted by calling \c psa_verify_hash_abort(). - * - * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \param key Identifier of the key to use for the operation. - * The key must allow the usage - * #PSA_KEY_USAGE_VERIFY_HASH. - * \param alg A signature algorithm (\c PSA_ALG_XXX - * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) - * is true), that is compatible with - * the type of \p key. - * \param[in] hash The hash whose signature is to be verified. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - please call \c - * psa_verify_hash_complete() with the same context to complete the - * operation. - * - * \retval #PSA_ERROR_BAD_STATE - * Another operation has already been started on this context, and is - * still in progress. - * - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_VERIFY_HASH flag, or it does - * not permit the requested algorithm. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash_start( - psa_verify_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - -/** - * \brief Continue and eventually complete the action of - * reading and verifying a hash or short message - * signed with a private key, in an interruptible - * manner. - * - * \see \c psa_verify_hash_start() - * - * \warning This is a beta API, and thus subject to change - * at any point. It is not bound by the usual - * interface stability promises. - * - * \note This function combined with \c - * psa_verify_hash_start() is equivalent to - * \c psa_verify_hash() but this function can - * return early and resume according to the limit - * set with \c psa_interruptible_set_max_ops() to - * reduce the maximum time spent in a function - * call. - * - * \note Users should call this function on the same - * operation object repeatedly until it either - * returns 0 or an error. This function will return - * #PSA_OPERATION_INCOMPLETE if there is more work - * to do. Alternatively users can call - * \c psa_verify_hash_abort() at any point if they - * no longer want the result. - * - * \note When this function returns successfully, the - * operation becomes inactive. If this function - * returns an error status, the operation enters an - * error state and must be aborted by calling - * \c psa_verify_hash_abort(). - * - * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first, and have - * had \c psa_verify_hash_start() called with it - * first. - * - * \retval #PSA_SUCCESS - * Operation completed successfully, and the passed signature is valid. - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(). There is still work to be done. - * Call this function again with the same operation object. - * - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_BAD_STATE - * An operation was not previously started on this context via - * \c psa_verify_hash_start(). - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has either not been previously initialized by - * psa_crypto_init() or you did not previously call - * psa_verify_hash_start() on this object. It is - * implementation-dependent whether a failure to initialize results in - * this error code. - */ -psa_status_t psa_verify_hash_complete( - psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Abort a verify hash operation. - * - * \warning This is a beta API, and thus subject to change at - * any point. It is not bound by the usual interface - * stability promises. - * - * \note This function is the only function that clears the - * number of ops completed as part of the operation. - * Please ensure you copy this value via - * \c psa_verify_hash_get_num_ops() if required - * before calling. - * - * \note Aborting an operation frees all associated - * resources except for the operation structure - * itself. Once aborted, the operation object can be - * reused for another operation by calling \c - * psa_verify_hash_start() again. - * - * \note You may call this function any time after the - * operation object has been initialized. - * In particular, calling \c psa_verify_hash_abort() - * after the operation has already been terminated by - * a call to \c psa_verify_hash_abort() or - * psa_verify_hash_complete() is safe. - * - * \param[in,out] operation Initialized verify hash operation. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_verify_hash_abort( - psa_verify_hash_interruptible_operation_t *operation); - - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -/* The file "crypto_sizes.h" contains definitions for size calculation - * macros whose definitions are implementation-specific. */ -#include "crypto_sizes.h" - -/* The file "crypto_struct.h" contains definitions for - * implementation-specific structs that are declared above. */ -#if defined(MBEDTLS_PSA_CRYPTO_STRUCT_FILE) -#include MBEDTLS_PSA_CRYPTO_STRUCT_FILE -#else -#include "crypto_struct.h" -#endif - -/* The file "crypto_extra.h" contains vendor-specific definitions. This - * can include vendor-defined algorithms, extra functions, etc. */ -#include "crypto_extra.h" - -#endif /* PSA_CRYPTO_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto.h + * \brief Platform Security Architecture cryptography module + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_H +#define PSA_CRYPTO_H + +#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) +#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE +#else +#include "crypto_platform.h" +#endif + +#include + +#ifdef __DOXYGEN_ONLY__ +/* This __DOXYGEN_ONLY__ block contains mock definitions for things that + * must be defined in the crypto_platform.h header. These mock definitions + * are present in this file as a convenience to generate pretty-printed + * documentation that includes those definitions. */ + +/** \defgroup platform Implementation-specific definitions + * @{ + */ + +/**@}*/ +#endif /* __DOXYGEN_ONLY__ */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* The file "crypto_types.h" declares types that encode errors, + * algorithms, key types, policies, etc. */ +#include "crypto_types.h" + +/** \defgroup version API version + * @{ + */ + +/** + * The major version of this implementation of the PSA Crypto API + */ +#define PSA_CRYPTO_API_VERSION_MAJOR 1 + +/** + * The minor version of this implementation of the PSA Crypto API + */ +#define PSA_CRYPTO_API_VERSION_MINOR 0 + +/**@}*/ + +/* The file "crypto_values.h" declares macros to build and analyze values + * of integral types defined in "crypto_types.h". */ +#include "crypto_values.h" + +/** \defgroup initialization Library initialization + * @{ + */ + +/** + * \brief Library initialization. + * + * Applications must call this function before calling any other + * function in this module. + * + * Applications may call this function more than once. Once a call + * succeeds, subsequent calls are guaranteed to succeed. + * + * If the application calls other functions before calling psa_crypto_init(), + * the behavior is undefined. Implementations are encouraged to either perform + * the operation as if the library had been initialized or to return + * #PSA_ERROR_BAD_STATE or some other applicable error. In particular, + * implementations should not return a success status if the lack of + * initialization may have security implications, for example due to improper + * seeding of the random number generator. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + */ +psa_status_t psa_crypto_init(void); + +/**@}*/ + +/** \addtogroup attributes + * @{ + */ + +/** \def PSA_KEY_ATTRIBUTES_INIT + * + * This macro returns a suitable initializer for a key attribute structure + * of type #psa_key_attributes_t. + */ + +/** Return an initial value for a key attributes structure. + */ +static psa_key_attributes_t psa_key_attributes_init(void); + +/** Declare a key as persistent and set its key identifier. + * + * If the attribute structure currently declares the key as volatile (which + * is the default content of an attribute structure), this function sets + * the lifetime attribute to #PSA_KEY_LIFETIME_PERSISTENT. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * psa_import_key(), psa_generate_key(), + * psa_key_derivation_output_key() or psa_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param key The persistent identifier for the key. + */ +static void psa_set_key_id(psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t key); + +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER +/** Set the owner identifier of a key. + * + * When key identifiers encode key owner identifiers, psa_set_key_id() does + * not allow to define in key attributes the owner of volatile keys as + * psa_set_key_id() enforces the key to be persistent. + * + * This function allows to set in key attributes the owner identifier of a + * key. It is intended to be used for volatile keys. For persistent keys, + * it is recommended to use the PSA Cryptography API psa_set_key_id() to define + * the owner of a key. + * + * \param[out] attributes The attribute structure to write to. + * \param owner The key owner identifier. + */ +static void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, + mbedtls_key_owner_id_t owner); +#endif + +/** Set the location of a persistent key. + * + * To make a key persistent, you must give it a persistent key identifier + * with psa_set_key_id(). By default, a key that has a persistent identifier + * is stored in the default storage area identifier by + * #PSA_KEY_LIFETIME_PERSISTENT. Call this function to choose a storage + * area, or to explicitly declare the key as volatile. + * + * This function does not access storage, it merely stores the given + * value in the structure. + * The persistent key will be written to storage when the attribute + * structure is passed to a key creation function such as + * psa_import_key(), psa_generate_key(), + * psa_key_derivation_output_key() or psa_copy_key(). + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param lifetime The lifetime for the key. + * If this is #PSA_KEY_LIFETIME_VOLATILE, the + * key will be volatile, and the key identifier + * attribute is reset to 0. + */ +static void psa_set_key_lifetime(psa_key_attributes_t *attributes, + psa_key_lifetime_t lifetime); + +/** Retrieve the key identifier from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The persistent identifier stored in the attribute structure. + * This value is unspecified if the attribute structure declares + * the key as volatile. + */ +static mbedtls_svc_key_id_t psa_get_key_id( + const psa_key_attributes_t *attributes); + +/** Retrieve the lifetime from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The lifetime value stored in the attribute structure. + */ +static psa_key_lifetime_t psa_get_key_lifetime( + const psa_key_attributes_t *attributes); + +/** Declare usage flags for a key. + * + * Usage flags are part of a key's usage policy. They encode what + * kind of operations are permitted on the key. For more details, + * refer to the documentation of the type #psa_key_usage_t. + * + * This function overwrites any usage flags + * previously set in \p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param usage_flags The usage flags to write. + */ +static void psa_set_key_usage_flags(psa_key_attributes_t *attributes, + psa_key_usage_t usage_flags); + +/** Retrieve the usage flags from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The usage flags stored in the attribute structure. + */ +static psa_key_usage_t psa_get_key_usage_flags( + const psa_key_attributes_t *attributes); + +/** Declare the permitted algorithm policy for a key. + * + * The permitted algorithm policy of a key encodes which algorithm or + * algorithms are permitted to be used with this key. The following + * algorithm policies are supported: + * - 0 does not allow any cryptographic operation with the key. The key + * may be used for non-cryptographic actions such as exporting (if + * permitted by the usage flags). + * - An algorithm value permits this particular algorithm. + * - An algorithm wildcard built from #PSA_ALG_ANY_HASH allows the specified + * signature scheme with any hash algorithm. + * - An algorithm built from #PSA_ALG_AT_LEAST_THIS_LENGTH_MAC allows + * any MAC algorithm from the same base class (e.g. CMAC) which + * generates/verifies a MAC length greater than or equal to the length + * encoded in the wildcard algorithm. + * - An algorithm built from #PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG + * allows any AEAD algorithm from the same base class (e.g. CCM) which + * generates/verifies a tag length greater than or equal to the length + * encoded in the wildcard algorithm. + * + * This function overwrites any algorithm policy + * previously set in \p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param alg The permitted algorithm policy to write. + */ +static void psa_set_key_algorithm(psa_key_attributes_t *attributes, + psa_algorithm_t alg); + + +/** Retrieve the algorithm policy from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The algorithm stored in the attribute structure. + */ +static psa_algorithm_t psa_get_key_algorithm( + const psa_key_attributes_t *attributes); + +/** Declare the type of a key. + * + * This function overwrites any key type + * previously set in \p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param type The key type to write. + * If this is 0, the key type in \p attributes + * becomes unspecified. + */ +static void psa_set_key_type(psa_key_attributes_t *attributes, + psa_key_type_t type); + + +/** Declare the size of a key. + * + * This function overwrites any key size previously set in \p attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate each of its arguments exactly once. + * + * \param[out] attributes The attribute structure to write to. + * \param bits The key size in bits. + * If this is 0, the key size in \p attributes + * becomes unspecified. Keys of size 0 are + * not supported. + */ +static void psa_set_key_bits(psa_key_attributes_t *attributes, + size_t bits); + +/** Retrieve the key type from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The key type stored in the attribute structure. + */ +static psa_key_type_t psa_get_key_type(const psa_key_attributes_t *attributes); + +/** Retrieve the key size from key attributes. + * + * This function may be declared as `static` (i.e. without external + * linkage). This function may be provided as a function-like macro, + * but in this case it must evaluate its argument exactly once. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The key size stored in the attribute structure, in bits. + */ +static size_t psa_get_key_bits(const psa_key_attributes_t *attributes); + +/** Retrieve the attributes of a key. + * + * This function first resets the attribute structure as with + * psa_reset_key_attributes(). It then copies the attributes of + * the given key into the given attribute structure. + * + * \note This function may allocate memory or other resources. + * Once you have called this function on an attribute structure, + * you must call psa_reset_key_attributes() to free these resources. + * + * \param[in] key Identifier of the key to query. + * \param[in,out] attributes On success, the attributes of the key. + * On failure, equivalent to a + * freshly-initialized structure. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, + psa_key_attributes_t *attributes); + +/** Reset a key attribute structure to a freshly initialized state. + * + * You must initialize the attribute structure as described in the + * documentation of the type #psa_key_attributes_t before calling this + * function. Once the structure has been initialized, you may call this + * function at any time. + * + * This function frees any auxiliary resources that the structure + * may contain. + * + * \param[in,out] attributes The attribute structure to reset. + */ +void psa_reset_key_attributes(psa_key_attributes_t *attributes); + +/**@}*/ + +/** \defgroup key_management Key management + * @{ + */ + +/** Remove non-essential copies of key material from memory. + * + * If the key identifier designates a volatile key, this functions does not do + * anything and returns successfully. + * + * If the key identifier designates a persistent key, then this function will + * free all resources associated with the key in volatile memory. The key + * data in persistent storage is not affected and the key can still be used. + * + * \param key Identifier of the key to purge. + * + * \retval #PSA_SUCCESS + * The key material will have been removed from memory if it is not + * currently required. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not a valid key identifier. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_purge_key(mbedtls_svc_key_id_t key); + +/** Make a copy of a key. + * + * Copy key material from one location to another. + * + * This function is primarily useful to copy a key from one location + * to another, since it populates a key using the material from + * another key which may have a different lifetime. + * + * This function may be used to share a key with a different party, + * subject to implementation-defined restrictions on key sharing. + * + * The policy on the source key must have the usage flag + * #PSA_KEY_USAGE_COPY set. + * This flag is sufficient to permit the copy if the key has the lifetime + * #PSA_KEY_LIFETIME_VOLATILE or #PSA_KEY_LIFETIME_PERSISTENT. + * Some secure elements do not provide a way to copy a key without + * making it extractable from the secure element. If a key is located + * in such a secure element, then the key must have both usage flags + * #PSA_KEY_USAGE_COPY and #PSA_KEY_USAGE_EXPORT in order to make + * a copy of the key outside the secure element. + * + * The resulting key may only be used in a way that conforms to + * both the policy of the original key and the policy specified in + * the \p attributes parameter: + * - The usage flags on the resulting key are the bitwise-and of the + * usage flags on the source policy and the usage flags in \p attributes. + * - If both allow the same algorithm or wildcard-based + * algorithm policy, the resulting key has the same algorithm policy. + * - If either of the policies allows an algorithm and the other policy + * allows a wildcard-based algorithm policy that includes this algorithm, + * the resulting key allows the same algorithm. + * - If the policies do not allow any algorithm in common, this function + * fails with the status #PSA_ERROR_INVALID_ARGUMENT. + * + * The effect of this function on implementation-defined attributes is + * implementation-defined. + * + * \param source_key The key to copy. It must allow the usage + * #PSA_KEY_USAGE_COPY. If a private or secret key is + * being copied outside of a secure element it must + * also allow #PSA_KEY_USAGE_EXPORT. + * \param[in] attributes The attributes for the new key. + * They are used as follows: + * - The key type and size may be 0. If either is + * nonzero, it must match the corresponding + * attribute of the source key. + * - The key location (the lifetime and, for + * persistent keys, the key identifier) is + * used directly. + * - The policy constraints (usage flags and + * algorithm policy) are combined from + * the source key and \p attributes so that + * both sets of restrictions apply, as + * described in the documentation of this function. + * \param[out] target_key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. + * \c 0 on failure. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE + * \p source_key is invalid. + * \retval #PSA_ERROR_ALREADY_EXISTS + * This is an attempt to create a persistent key, and there is + * already a persistent key with the given identifier. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The lifetime or identifier in \p attributes are invalid, or + * the policy constraints on the source and specified in + * \p attributes are incompatible, or + * \p attributes specifies a key type or key size + * which does not match the attributes of the source key. + * \retval #PSA_ERROR_NOT_PERMITTED + * The source key does not have the #PSA_KEY_USAGE_COPY usage flag, or + * the source key is not exportable and its lifetime does not + * allow copying it to the target's lifetime. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, + const psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t *target_key); + + +/** + * \brief Destroy a key. + * + * This function destroys a key from both volatile + * memory and, if applicable, non-volatile storage. Implementations shall + * make a best effort to ensure that the key material cannot be recovered. + * + * This function also erases any metadata such as policies and frees + * resources associated with the key. + * + * If a key is currently in use in a multipart operation, then destroying the + * key will cause the multipart operation to fail. + * + * \param key Identifier of the key to erase. If this is \c 0, do nothing and + * return #PSA_SUCCESS. + * + * \retval #PSA_SUCCESS + * \p key was a valid identifier and the key material that it + * referred to has been erased. Alternatively, \p key is \c 0. + * \retval #PSA_ERROR_NOT_PERMITTED + * The key cannot be erased because it is + * read-only, either due to a policy or due to physical restrictions. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p key is not a valid identifier nor \c 0. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * There was a failure in communication with the cryptoprocessor. + * The key material may still be present in the cryptoprocessor. + * \retval #PSA_ERROR_DATA_INVALID + * This error is typically a result of either storage corruption on a + * cleartext storage backend, or an attempt to read data that was + * written by an incompatible version of the library. + * \retval #PSA_ERROR_STORAGE_FAILURE + * The storage is corrupted. Implementations shall make a best effort + * to erase key material even in this stage, however applications + * should be aware that it may be impossible to guarantee that the + * key material is not recoverable in such cases. + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * An unexpected condition which is not a storage corruption or + * a communication failure occurred. The cryptoprocessor may have + * been compromised. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(), + * or the library was not able to move the key slot to the + * PSA_STATE_DESTROYING state. + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_destroy_key(mbedtls_svc_key_id_t key); + +/**@}*/ + +/** \defgroup import_export Key import and export + * @{ + */ + +/** + * \brief Import a key in binary format. + * + * This function supports any output from psa_export_key(). Refer to the + * documentation of psa_export_public_key() for the format of public keys + * and to the documentation of psa_export_key() for the format for + * other key types. + * + * The key data determines the key size. The attributes may optionally + * specify a key size; in this case it must match the size determined + * from the key data. A key size of 0 in \p attributes indicates that + * the key size is solely determined by the key data. + * + * Implementations must reject an attempt to import a key of size 0. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * \param[in] attributes The attributes for the new key. + * The key size is always determined from the + * \p data buffer. + * If the key size in \p attributes is nonzero, + * it must be equal to the size from \p data. + * \param[out] key On success, an identifier to the newly created key. + * For persistent keys, this is the key identifier + * defined in \p attributes. + * \c 0 on failure. + * \param[in] data Buffer containing the key data. The content of this + * buffer is interpreted according to the type declared + * in \p attributes. + * All implementations must support at least the format + * described in the documentation + * of psa_export_key() or psa_export_public_key() for + * the chosen type. Implementations may allow other + * formats, but should be conservative: implementations + * should err on the side of rejecting content if it + * may be erroneous (e.g. wrong type or truncated data). + * \param data_length Size of the \p data buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * If the key is persistent, the key material and the key's metadata + * have been saved to persistent storage. + * \retval #PSA_ERROR_ALREADY_EXISTS + * This is an attempt to create a persistent key, and there is + * already a persistent key with the given identifier. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The key type or key size is not supported, either by the + * implementation in general or in this particular persistent location. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key attributes, as a whole, are invalid, or + * the key data is not correctly formatted, or + * the size in \p attributes is nonzero and does not match the size + * of the key data. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + mbedtls_svc_key_id_t *key); + + + +/** + * \brief Export a key in binary format. + * + * The output of this function can be passed to psa_import_key() to + * create an equivalent object. + * + * If the implementation of psa_import_key() supports other formats + * beyond the format specified here, the output from psa_export_key() + * must use the representation specified here, not the original + * representation. + * + * For standard key types, the output format is as follows: + * + * - For symmetric keys (including MAC keys), the format is the + * raw bytes of the key. + * - For DES, the key data consists of 8 bytes. The parity bits must be + * correct. + * - For Triple-DES, the format is the concatenation of the + * two or three DES keys. + * - For RSA key pairs (#PSA_KEY_TYPE_RSA_KEY_PAIR), the format + * is the non-encrypted DER encoding of the representation defined by + * PKCS\#1 (RFC 8017) as `RSAPrivateKey`, version 0. + * ``` + * RSAPrivateKey ::= SEQUENCE { + * version INTEGER, -- must be 0 + * modulus INTEGER, -- n + * publicExponent INTEGER, -- e + * privateExponent INTEGER, -- d + * prime1 INTEGER, -- p + * prime2 INTEGER, -- q + * exponent1 INTEGER, -- d mod (p-1) + * exponent2 INTEGER, -- d mod (q-1) + * coefficient INTEGER, -- (inverse of q) mod p + * } + * ``` + * - For elliptic curve key pairs (key types for which + * #PSA_KEY_TYPE_IS_ECC_KEY_PAIR is true), the format is + * a representation of the private value as a `ceiling(m/8)`-byte string + * where `m` is the bit size associated with the curve, i.e. the bit size + * of the order of the curve's coordinate field. This byte string is + * in little-endian order for Montgomery curves (curve types + * `PSA_ECC_FAMILY_CURVEXXX`), and in big-endian order for Weierstrass + * curves (curve types `PSA_ECC_FAMILY_SECTXXX`, `PSA_ECC_FAMILY_SECPXXX` + * and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`). + * For Weierstrass curves, this is the content of the `privateKey` field of + * the `ECPrivateKey` format defined by RFC 5915. For Montgomery curves, + * the format is defined by RFC 7748, and output is masked according to §5. + * For twisted Edwards curves, the private key is as defined by RFC 8032 + * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). + * - For Diffie-Hellman key exchange key pairs (key types for which + * #PSA_KEY_TYPE_IS_DH_KEY_PAIR is true), the + * format is the representation of the private key `x` as a big-endian byte + * string. The length of the byte string is the private key size in bytes + * (leading zeroes are not stripped). + * - For public keys (key types for which #PSA_KEY_TYPE_IS_PUBLIC_KEY is + * true), the format is the same as for psa_export_public_key(). + * + * The policy on the key must have the usage flag #PSA_KEY_USAGE_EXPORT set. + * + * \param key Identifier of the key to export. It must allow the + * usage #PSA_KEY_USAGE_EXPORT, unless it is a public + * key. + * \param[out] data Buffer where the key data is to be written. + * \param data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes + * that make up the key data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_EXPORT flag. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p data buffer is too small. You can determine a + * sufficient buffer size by calling + * #PSA_EXPORT_KEY_OUTPUT_SIZE(\c type, \c bits) + * where \c type is the key type + * and \c bits is the key size in bits. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_export_key(mbedtls_svc_key_id_t key, + uint8_t *data, + size_t data_size, + size_t *data_length); + +/** + * \brief Export a public key or the public part of a key pair in binary format. + * + * The output of this function can be passed to psa_import_key() to + * create an object that is equivalent to the public key. + * + * This specification supports a single format for each key type. + * Implementations may support other formats as long as the standard + * format is supported. Implementations that support other formats + * should ensure that the formats are clearly unambiguous so as to + * minimize the risk that an invalid input is accidentally interpreted + * according to a different format. + * + * For standard key types, the output format is as follows: + * - For RSA public keys (#PSA_KEY_TYPE_RSA_PUBLIC_KEY), the DER encoding of + * the representation defined by RFC 3279 §2.3.1 as `RSAPublicKey`. + * ``` + * RSAPublicKey ::= SEQUENCE { + * modulus INTEGER, -- n + * publicExponent INTEGER } -- e + * ``` + * - For elliptic curve keys on a twisted Edwards curve (key types for which + * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true and #PSA_KEY_TYPE_ECC_GET_FAMILY + * returns #PSA_ECC_FAMILY_TWISTED_EDWARDS), the public key is as defined + * by RFC 8032 + * (a 32-byte string for Edwards25519, a 57-byte string for Edwards448). + * - For other elliptic curve public keys (key types for which + * #PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY is true), the format is the uncompressed + * representation defined by SEC1 §2.3.3 as the content of an ECPoint. + * Let `m` be the bit size associated with the curve, i.e. the bit size of + * `q` for a curve over `F_q`. The representation consists of: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. + * - For Diffie-Hellman key exchange public keys (key types for which + * #PSA_KEY_TYPE_IS_DH_PUBLIC_KEY is true), + * the format is the representation of the public key `y = g^x mod p` as a + * big-endian byte string. The length of the byte string is the length of the + * base prime `p` in bytes. + * + * Exporting a public key object or the public part of a key pair is + * always permitted, regardless of the key's usage flags. + * + * \param key Identifier of the key to export. + * \param[out] data Buffer where the key data is to be written. + * \param data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes + * that make up the key data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key is neither a public key nor a key pair. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p data buffer is too small. You can determine a + * sufficient buffer size by calling + * #PSA_EXPORT_KEY_OUTPUT_SIZE(#PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\c type), \c bits) + * where \c type is the key type + * and \c bits is the key size in bits. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, + uint8_t *data, + size_t data_size, + size_t *data_length); + + + +/**@}*/ + +/** \defgroup hash Message digests + * @{ + */ + +/** Calculate the hash (digest) of a message. + * + * \note To verify the hash of a message against an + * expected value, use psa_hash_compare() instead. + * + * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_HASH(\p alg) is true). + * \param[in] input Buffer containing the message to hash. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] hash Buffer where the hash is to be written. + * \param hash_size Size of the \p hash buffer in bytes. + * \param[out] hash_length On success, the number of bytes + * that make up the hash value. This is always + * #PSA_HASH_LENGTH(\p alg). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a hash algorithm. + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p hash_size is too small + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_compute(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +/** Calculate the hash (digest) of a message and compare it with a + * reference value. + * + * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_HASH(\p alg) is true). + * \param[in] input Buffer containing the message to hash. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] hash Buffer containing the expected hash value. + * \param hash_length Size of the \p hash buffer in bytes. + * + * \retval #PSA_SUCCESS + * The expected hash is identical to the actual hash of the input. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The hash of the message was calculated successfully, but it + * differs from the expected hash. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a hash algorithm. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p input_length or \p hash_length do not match the hash size for \p alg + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_compare(psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *hash, + size_t hash_length); + +/** The type of the state data structure for multipart hash operations. + * + * Before calling any function on a hash operation object, the application must + * initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_hash_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_hash_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_HASH_OPERATION_INIT, + * for example: + * \code + * psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_hash_operation_init() + * to the structure, for example: + * \code + * psa_hash_operation_t operation; + * operation = psa_hash_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_hash_operation_s psa_hash_operation_t; + +/** \def PSA_HASH_OPERATION_INIT + * + * This macro returns a suitable initializer for a hash operation object + * of type #psa_hash_operation_t. + */ + +/** Return an initial value for a hash operation object. + */ +static psa_hash_operation_t psa_hash_operation_init(void); + +/** Set up a multipart hash operation. + * + * The sequence of operations to calculate a hash (message digest) + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_hash_operation_t, e.g. #PSA_HASH_OPERATION_INIT. + * -# Call psa_hash_setup() to specify the algorithm. + * -# Call psa_hash_update() zero, one or more times, passing a fragment + * of the message each time. The hash that is calculated is the hash + * of the concatenation of these messages in order. + * -# To calculate the hash, call psa_hash_finish(). + * To compare the hash with an expected value, call psa_hash_verify(). + * + * If an error occurs at any step after a call to psa_hash_setup(), the + * operation will need to be reset by a call to psa_hash_abort(). The + * application may call psa_hash_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_hash_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to psa_hash_finish() or psa_hash_verify(). + * - A call to psa_hash_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_hash_operation_t and not yet in use. + * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_HASH(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not a supported hash algorithm. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p alg is not a hash algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_setup(psa_hash_operation_t *operation, + psa_algorithm_t alg); + +/** Add a message fragment to a multipart hash operation. + * + * The application must call psa_hash_setup() before calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_hash_abort(). + * + * \param[in,out] operation Active hash operation. + * \param[in] input Buffer containing the message fragment to hash. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_update(psa_hash_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Finish the calculation of the hash of a message. + * + * The application must call psa_hash_setup() before calling this function. + * This function calculates the hash of the message formed by concatenating + * the inputs passed to preceding calls to psa_hash_update(). + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_hash_abort(). + * + * \warning Applications should not call this function if they expect + * a specific value for the hash. Call psa_hash_verify() instead. + * Beware that comparing integrity or authenticity data such as + * hash values with a function such as \c memcmp is risky + * because the time taken by the comparison may leak information + * about the hashed data which could allow an attacker to guess + * a valid hash and thereby bypass security controls. + * + * \param[in,out] operation Active hash operation. + * \param[out] hash Buffer where the hash is to be written. + * \param hash_size Size of the \p hash buffer in bytes. + * \param[out] hash_length On success, the number of bytes + * that make up the hash value. This is always + * #PSA_HASH_LENGTH(\c alg) where \c alg is the + * hash algorithm that is calculated. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p hash buffer is too small. You can determine a + * sufficient buffer size by calling #PSA_HASH_LENGTH(\c alg) + * where \c alg is the hash algorithm that is calculated. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_finish(psa_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +/** Finish the calculation of the hash of a message and compare it with + * an expected value. + * + * The application must call psa_hash_setup() before calling this function. + * This function calculates the hash of the message formed by concatenating + * the inputs passed to preceding calls to psa_hash_update(). It then + * compares the calculated hash with the expected hash passed as a + * parameter to this function. + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_hash_abort(). + * + * \note Implementations shall make the best effort to ensure that the + * comparison between the actual hash and the expected hash is performed + * in constant time. + * + * \param[in,out] operation Active hash operation. + * \param[in] hash Buffer containing the expected hash value. + * \param hash_length Size of the \p hash buffer in bytes. + * + * \retval #PSA_SUCCESS + * The expected hash is identical to the actual hash of the message. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The hash of the message was calculated successfully, but it + * differs from the expected hash. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_verify(psa_hash_operation_t *operation, + const uint8_t *hash, + size_t hash_length); + +/** Abort a hash operation. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * psa_hash_setup() again. + * + * You may call this function any time after the operation object has + * been initialized by one of the methods described in #psa_hash_operation_t. + * + * In particular, calling psa_hash_abort() after the operation has been + * terminated by a call to psa_hash_abort(), psa_hash_finish() or + * psa_hash_verify() is safe and has no effect. + * + * \param[in,out] operation Initialized hash operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_abort(psa_hash_operation_t *operation); + +/** Clone a hash operation. + * + * This function copies the state of an ongoing hash operation to + * a new operation object. In other words, this function is equivalent + * to calling psa_hash_setup() on \p target_operation with the same + * algorithm that \p source_operation was set up for, then + * psa_hash_update() on \p target_operation with the same input that + * that was passed to \p source_operation. After this function returns, the + * two objects are independent, i.e. subsequent calls involving one of + * the objects do not affect the other object. + * + * \param[in] source_operation The active hash operation to clone. + * \param[in,out] target_operation The operation object to set up. + * It must be initialized but not active. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The \p source_operation state is not valid (it must be active), or + * the \p target_operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, + psa_hash_operation_t *target_operation); + +/**@}*/ + +/** \defgroup MAC Message authentication codes + * @{ + */ + +/** Calculate the MAC (message authentication code) of a message. + * + * \note To verify the MAC of a message against an + * expected value, use psa_mac_verify() instead. + * Beware that comparing integrity or authenticity data such as + * MAC values with a function such as \c memcmp is risky + * because the time taken by the comparison may leak information + * about the MAC value which could allow an attacker to guess + * a valid MAC and thereby bypass security controls. + * + * \param key Identifier of the key to use for the operation. It + * must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. + * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * \param[in] input Buffer containing the input message. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] mac Buffer where the MAC value is to be written. + * \param mac_size Size of the \p mac buffer in bytes. + * \param[out] mac_length On success, the number of bytes + * that make up the MAC value. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a MAC algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p mac_size is too small + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE + * The key could not be retrieved from storage. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +/** Calculate the MAC of a message and compare it with a reference value. + * + * \param key Identifier of the key to use for the operation. It + * must allow the usage PSA_KEY_USAGE_VERIFY_MESSAGE. + * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * \param[in] input Buffer containing the input message. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] mac Buffer containing the expected MAC value. + * \param mac_length Size of the \p mac buffer in bytes. + * + * \retval #PSA_SUCCESS + * The expected MAC is identical to the actual MAC of the input. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The MAC of the message was calculated successfully, but it + * differs from the expected value. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a MAC algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE + * The key could not be retrieved from storage. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *mac, + size_t mac_length); + +/** The type of the state data structure for multipart MAC operations. + * + * Before calling any function on a MAC operation object, the application must + * initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_mac_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_mac_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_MAC_OPERATION_INIT, + * for example: + * \code + * psa_mac_operation_t operation = PSA_MAC_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_mac_operation_init() + * to the structure, for example: + * \code + * psa_mac_operation_t operation; + * operation = psa_mac_operation_init(); + * \endcode + * + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_mac_operation_s psa_mac_operation_t; + +/** \def PSA_MAC_OPERATION_INIT + * + * This macro returns a suitable initializer for a MAC operation object of type + * #psa_mac_operation_t. + */ + +/** Return an initial value for a MAC operation object. + */ +static psa_mac_operation_t psa_mac_operation_init(void); + +/** Set up a multipart MAC calculation operation. + * + * This function sets up the calculation of the MAC + * (message authentication code) of a byte string. + * To verify the MAC of a message against an + * expected value, use psa_mac_verify_setup() instead. + * + * The sequence of operations to calculate a MAC is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. + * -# Call psa_mac_sign_setup() to specify the algorithm and key. + * -# Call psa_mac_update() zero, one or more times, passing a fragment + * of the message each time. The MAC that is calculated is the MAC + * of the concatenation of these messages in order. + * -# At the end of the message, call psa_mac_sign_finish() to finish + * calculating the MAC value and retrieve it. + * + * If an error occurs at any step after a call to psa_mac_sign_setup(), the + * operation will need to be reset by a call to psa_mac_abort(). The + * application may call psa_mac_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_mac_sign_setup(), the application must + * eventually terminate the operation through one of the following methods: + * - A successful call to psa_mac_sign_finish(). + * - A call to psa_mac_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_mac_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. It + * must remain valid until the operation terminates. + * It must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. + * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a MAC algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE + * The key could not be retrieved from storage. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Set up a multipart MAC verification operation. + * + * This function sets up the verification of the MAC + * (message authentication code) of a byte string against an expected value. + * + * The sequence of operations to verify a MAC is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_mac_operation_t, e.g. #PSA_MAC_OPERATION_INIT. + * -# Call psa_mac_verify_setup() to specify the algorithm and key. + * -# Call psa_mac_update() zero, one or more times, passing a fragment + * of the message each time. The MAC that is calculated is the MAC + * of the concatenation of these messages in order. + * -# At the end of the message, call psa_mac_verify_finish() to finish + * calculating the actual MAC of the message and verify it against + * the expected value. + * + * If an error occurs at any step after a call to psa_mac_verify_setup(), the + * operation will need to be reset by a call to psa_mac_abort(). The + * application may call psa_mac_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_mac_verify_setup(), the application must + * eventually terminate the operation through one of the following methods: + * - A successful call to psa_mac_verify_finish(). + * - A call to psa_mac_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_mac_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. It + * must remain valid until the operation terminates. + * It must allow the usage + * PSA_KEY_USAGE_VERIFY_MESSAGE. + * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c key is not compatible with \c alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \c alg is not supported or is not a MAC algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE + * The key could not be retrieved from storage. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Add a message fragment to a multipart MAC operation. + * + * The application must call psa_mac_sign_setup() or psa_mac_verify_setup() + * before calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_mac_abort(). + * + * \param[in,out] operation Active MAC operation. + * \param[in] input Buffer containing the message fragment to add to + * the MAC calculation. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_update(psa_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Finish the calculation of the MAC of a message. + * + * The application must call psa_mac_sign_setup() before calling this function. + * This function calculates the MAC of the message formed by concatenating + * the inputs passed to preceding calls to psa_mac_update(). + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_mac_abort(). + * + * \warning Applications should not call this function if they expect + * a specific value for the MAC. Call psa_mac_verify_finish() instead. + * Beware that comparing integrity or authenticity data such as + * MAC values with a function such as \c memcmp is risky + * because the time taken by the comparison may leak information + * about the MAC value which could allow an attacker to guess + * a valid MAC and thereby bypass security controls. + * + * \param[in,out] operation Active MAC operation. + * \param[out] mac Buffer where the MAC value is to be written. + * \param mac_size Size of the \p mac buffer in bytes. + * \param[out] mac_length On success, the number of bytes + * that make up the MAC value. This is always + * #PSA_MAC_LENGTH(\c key_type, \c key_bits, \c alg) + * where \c key_type and \c key_bits are the type and + * bit-size respectively of the key and \c alg is the + * MAC algorithm that is calculated. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p mac buffer is too small. You can determine a + * sufficient buffer size by calling PSA_MAC_LENGTH(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active mac sign + * operation), or the library has not been previously initialized + * by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_sign_finish(psa_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +/** Finish the calculation of the MAC of a message and compare it with + * an expected value. + * + * The application must call psa_mac_verify_setup() before calling this function. + * This function calculates the MAC of the message formed by concatenating + * the inputs passed to preceding calls to psa_mac_update(). It then + * compares the calculated MAC with the expected MAC passed as a + * parameter to this function. + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_mac_abort(). + * + * \note Implementations shall make the best effort to ensure that the + * comparison between the actual MAC and the expected MAC is performed + * in constant time. + * + * \param[in,out] operation Active MAC operation. + * \param[in] mac Buffer containing the expected MAC value. + * \param mac_length Size of the \p mac buffer in bytes. + * + * \retval #PSA_SUCCESS + * The expected MAC is identical to the actual MAC of the message. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The MAC of the message was calculated successfully, but it + * differs from the expected MAC. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active mac verify + * operation), or the library has not been previously initialized + * by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_verify_finish(psa_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +/** Abort a MAC operation. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * psa_mac_sign_setup() or psa_mac_verify_setup() again. + * + * You may call this function any time after the operation object has + * been initialized by one of the methods described in #psa_mac_operation_t. + * + * In particular, calling psa_mac_abort() after the operation has been + * terminated by a call to psa_mac_abort(), psa_mac_sign_finish() or + * psa_mac_verify_finish() is safe and has no effect. + * + * \param[in,out] operation Initialized MAC operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_mac_abort(psa_mac_operation_t *operation); + +/**@}*/ + +/** \defgroup cipher Symmetric ciphers + * @{ + */ + +/** Encrypt a message using a symmetric cipher. + * + * This function encrypts a message with a random IV (initialization + * vector). Use the multipart operation interface with a + * #psa_cipher_operation_t object to provide other forms of IV. + * + * \param key Identifier of the key to use for the operation. + * It must allow the usage #PSA_KEY_USAGE_ENCRYPT. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to encrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * The output contains the IV followed by + * the ciphertext proper. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Decrypt a message using a symmetric cipher. + * + * This function decrypts a message encrypted with a symmetric cipher. + * + * \param key Identifier of the key to use for the operation. + * It must remain valid until the operation + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the message to decrypt. + * This consists of the IV followed by the + * ciphertext proper. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the plaintext is to be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** The type of the state data structure for multipart cipher operations. + * + * Before calling any function on a cipher operation object, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_cipher_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_cipher_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_CIPHER_OPERATION_INIT, + * for example: + * \code + * psa_cipher_operation_t operation = PSA_CIPHER_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_cipher_operation_init() + * to the structure, for example: + * \code + * psa_cipher_operation_t operation; + * operation = psa_cipher_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_cipher_operation_s psa_cipher_operation_t; + +/** \def PSA_CIPHER_OPERATION_INIT + * + * This macro returns a suitable initializer for a cipher operation object of + * type #psa_cipher_operation_t. + */ + +/** Return an initial value for a cipher operation object. + */ +static psa_cipher_operation_t psa_cipher_operation_init(void); + +/** Set the key for a multipart symmetric encryption operation. + * + * The sequence of operations to encrypt a message with a symmetric cipher + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_cipher_operation_t, e.g. + * #PSA_CIPHER_OPERATION_INIT. + * -# Call psa_cipher_encrypt_setup() to specify the algorithm and key. + * -# Call either psa_cipher_generate_iv() or psa_cipher_set_iv() to + * generate or set the IV (initialization vector). You should use + * psa_cipher_generate_iv() unless the protocol you are implementing + * requires a specific IV value. + * -# Call psa_cipher_update() zero, one or more times, passing a fragment + * of the message each time. + * -# Call psa_cipher_finish(). + * + * If an error occurs at any step after a call to psa_cipher_encrypt_setup(), + * the operation will need to be reset by a call to psa_cipher_abort(). The + * application may call psa_cipher_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_cipher_encrypt_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to psa_cipher_finish(). + * - A call to psa_cipher_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_cipher_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. + * It must remain valid until the operation + * terminates. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Set the key for a multipart symmetric decryption operation. + * + * The sequence of operations to decrypt a message with a symmetric cipher + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_cipher_operation_t, e.g. + * #PSA_CIPHER_OPERATION_INIT. + * -# Call psa_cipher_decrypt_setup() to specify the algorithm and key. + * -# Call psa_cipher_set_iv() with the IV (initialization vector) for the + * decryption. If the IV is prepended to the ciphertext, you can call + * psa_cipher_update() on a buffer containing the IV followed by the + * beginning of the message. + * -# Call psa_cipher_update() zero, one or more times, passing a fragment + * of the message each time. + * -# Call psa_cipher_finish(). + * + * If an error occurs at any step after a call to psa_cipher_decrypt_setup(), + * the operation will need to be reset by a call to psa_cipher_abort(). The + * application may call psa_cipher_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_cipher_decrypt_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to psa_cipher_finish(). + * - A call to psa_cipher_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_cipher_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. + * It must remain valid until the operation + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. + * \param alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not a cipher algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Generate an IV for a symmetric encryption operation. + * + * This function generates a random IV (initialization vector), nonce + * or initial counter value for the encryption operation as appropriate + * for the chosen algorithm, key type and key size. + * + * The application must call psa_cipher_encrypt_setup() before + * calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_cipher_abort(). + * + * \param[in,out] operation Active cipher operation. + * \param[out] iv Buffer where the generated IV is to be written. + * \param iv_size Size of the \p iv buffer in bytes. + * \param[out] iv_length On success, the number of bytes of the + * generated IV. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p iv buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, with no IV set), + * or the library has not been previously initialized + * by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_generate_iv(psa_cipher_operation_t *operation, + uint8_t *iv, + size_t iv_size, + size_t *iv_length); + +/** Set the IV for a symmetric encryption or decryption operation. + * + * This function sets the IV (initialization vector), nonce + * or initial counter value for the encryption or decryption operation. + * + * The application must call psa_cipher_encrypt_setup() before + * calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_cipher_abort(). + * + * \note When encrypting, applications should use psa_cipher_generate_iv() + * instead of this function, unless implementing a protocol that requires + * a non-random IV. + * + * \param[in,out] operation Active cipher operation. + * \param[in] iv Buffer containing the IV to use. + * \param iv_length Size of the IV in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size of \p iv is not acceptable for the chosen algorithm, + * or the chosen algorithm does not use an IV. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active cipher + * encrypt operation, with no IV set), or the library has not been + * previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_set_iv(psa_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length); + +/** Encrypt or decrypt a message fragment in an active cipher operation. + * + * Before calling this function, you must: + * 1. Call either psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup(). + * The choice of setup function determines whether this function + * encrypts or decrypts its input. + * 2. If the algorithm requires an IV, call psa_cipher_generate_iv() + * (recommended when encrypting) or psa_cipher_set_iv(). + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_cipher_abort(). + * + * \param[in,out] operation Active cipher operation. + * \param[in] input Buffer containing the message fragment to + * encrypt or decrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, with an IV set + * if required for the algorithm), or the library has not been + * previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_update(psa_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Finish encrypting or decrypting a message in a cipher operation. + * + * The application must call psa_cipher_encrypt_setup() or + * psa_cipher_decrypt_setup() before calling this function. The choice + * of setup function determines whether this function encrypts or + * decrypts its input. + * + * This function finishes the encryption or decryption of the message + * formed by concatenating the inputs passed to preceding calls to + * psa_cipher_update(). + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_cipher_abort(). + * + * \param[in,out] operation Active cipher operation. + * \param[out] output Buffer where the output is to be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total input size passed to this operation is not valid for + * this particular algorithm. For example, the algorithm is a based + * on block cipher and requires a whole number of blocks, but the + * total input size is not a multiple of the block size. + * \retval #PSA_ERROR_INVALID_PADDING + * This is a decryption operation for an algorithm that includes + * padding, and the ciphertext does not contain valid padding. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, with an IV set + * if required for the algorithm), or the library has not been + * previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_finish(psa_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Abort a cipher operation. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * psa_cipher_encrypt_setup() or psa_cipher_decrypt_setup() again. + * + * You may call this function any time after the operation object has + * been initialized as described in #psa_cipher_operation_t. + * + * In particular, calling psa_cipher_abort() after the operation has been + * terminated by a call to psa_cipher_abort() or psa_cipher_finish() + * is safe and has no effect. + * + * \param[in,out] operation Initialized cipher operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); + +/**@}*/ + +/** \defgroup aead Authenticated encryption with associated data (AEAD) + * @{ + */ + +/** Process an authenticated encryption operation. + * + * \param key Identifier of the key to use for the + * operation. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * \param[in] nonce Nonce or IV to use. + * \param nonce_length Size of the \p nonce buffer in bytes. + * \param[in] additional_data Additional data that will be authenticated + * but not encrypted. + * \param additional_data_length Size of \p additional_data in bytes. + * \param[in] plaintext Data that will be authenticated and + * encrypted. + * \param plaintext_length Size of \p plaintext in bytes. + * \param[out] ciphertext Output buffer for the authenticated and + * encrypted data. The additional data is not + * part of this output. For algorithms where the + * encrypted data and the authentication tag + * are defined as separate outputs, the + * authentication tag is appended to the + * encrypted data. + * \param ciphertext_size Size of the \p ciphertext buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, + * \p alg, \p plaintext_length) where + * \c key_type is the type of \p key. + * - #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p + * plaintext_length) evaluates to the maximum + * ciphertext size of any supported AEAD + * encryption. + * \param[out] ciphertext_length On success, the size of the output + * in the \p ciphertext buffer. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not an AEAD algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p ciphertext_size is too small. + * #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\c key_type, \p alg, + * \p plaintext_length) or + * #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length) can be used to + * determine the required buffer size. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length); + +/** Process an authenticated decryption operation. + * + * \param key Identifier of the key to use for the + * operation. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * \param[in] nonce Nonce or IV to use. + * \param nonce_length Size of the \p nonce buffer in bytes. + * \param[in] additional_data Additional data that has been authenticated + * but not encrypted. + * \param additional_data_length Size of \p additional_data in bytes. + * \param[in] ciphertext Data that has been authenticated and + * encrypted. For algorithms where the + * encrypted data and the authentication tag + * are defined as separate inputs, the buffer + * must contain the encrypted data followed + * by the authentication tag. + * \param ciphertext_length Size of \p ciphertext in bytes. + * \param[out] plaintext Output buffer for the decrypted data. + * \param plaintext_size Size of the \p plaintext buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, + * \p alg, \p ciphertext_length) where + * \c key_type is the type of \p key. + * - #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p + * ciphertext_length) evaluates to the maximum + * plaintext size of any supported AEAD + * decryption. + * \param[out] plaintext_length On success, the size of the output + * in the \p plaintext buffer. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The ciphertext is not authentic. + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not an AEAD algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p plaintext_size is too small. + * #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\c key_type, \p alg, + * \p ciphertext_length) or + * #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length) can be used + * to determine the required buffer size. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length); + +/** The type of the state data structure for multipart AEAD operations. + * + * Before calling any function on an AEAD operation object, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_aead_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_aead_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_AEAD_OPERATION_INIT, + * for example: + * \code + * psa_aead_operation_t operation = PSA_AEAD_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_aead_operation_init() + * to the structure, for example: + * \code + * psa_aead_operation_t operation; + * operation = psa_aead_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_aead_operation_s psa_aead_operation_t; + +/** \def PSA_AEAD_OPERATION_INIT + * + * This macro returns a suitable initializer for an AEAD operation object of + * type #psa_aead_operation_t. + */ + +/** Return an initial value for an AEAD operation object. + */ +static psa_aead_operation_t psa_aead_operation_init(void); + +/** Set the key for a multipart authenticated encryption operation. + * + * The sequence of operations to encrypt a message with authentication + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_aead_operation_t, e.g. + * #PSA_AEAD_OPERATION_INIT. + * -# Call psa_aead_encrypt_setup() to specify the algorithm and key. + * -# If needed, call psa_aead_set_lengths() to specify the length of the + * inputs to the subsequent calls to psa_aead_update_ad() and + * psa_aead_update(). See the documentation of psa_aead_set_lengths() + * for details. + * -# Call either psa_aead_generate_nonce() or psa_aead_set_nonce() to + * generate or set the nonce. You should use + * psa_aead_generate_nonce() unless the protocol you are implementing + * requires a specific nonce value. + * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment + * of the non-encrypted additional authenticated data each time. + * -# Call psa_aead_update() zero, one or more times, passing a fragment + * of the message to encrypt each time. + * -# Call psa_aead_finish(). + * + * If an error occurs at any step after a call to psa_aead_encrypt_setup(), + * the operation will need to be reset by a call to psa_aead_abort(). The + * application may call psa_aead_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_aead_encrypt_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to psa_aead_finish(). + * - A call to psa_aead_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_aead_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. + * It must remain valid until the operation + * terminates. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not an AEAD algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Set the key for a multipart authenticated decryption operation. + * + * The sequence of operations to decrypt a message with authentication + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_aead_operation_t, e.g. + * #PSA_AEAD_OPERATION_INIT. + * -# Call psa_aead_decrypt_setup() to specify the algorithm and key. + * -# If needed, call psa_aead_set_lengths() to specify the length of the + * inputs to the subsequent calls to psa_aead_update_ad() and + * psa_aead_update(). See the documentation of psa_aead_set_lengths() + * for details. + * -# Call psa_aead_set_nonce() with the nonce for the decryption. + * -# Call psa_aead_update_ad() zero, one or more times, passing a fragment + * of the non-encrypted additional authenticated data each time. + * -# Call psa_aead_update() zero, one or more times, passing a fragment + * of the ciphertext to decrypt each time. + * -# Call psa_aead_verify(). + * + * If an error occurs at any step after a call to psa_aead_decrypt_setup(), + * the operation will need to be reset by a call to psa_aead_abort(). The + * application may call psa_aead_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_aead_decrypt_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to psa_aead_verify(). + * - A call to psa_aead_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #psa_aead_operation_t and not yet in use. + * \param key Identifier of the key to use for the operation. + * It must remain valid until the operation + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not compatible with \p alg. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported or is not an AEAD algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or the + * library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg); + +/** Generate a random nonce for an authenticated encryption operation. + * + * This function generates a random nonce for the authenticated encryption + * operation with an appropriate size for the chosen algorithm, key type + * and key size. + * + * The application must call psa_aead_encrypt_setup() before + * calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param[out] nonce Buffer where the generated nonce is to be + * written. + * \param nonce_size Size of the \p nonce buffer in bytes. + * \param[out] nonce_length On success, the number of bytes of the + * generated nonce. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p nonce buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active aead encrypt + * operation, with no nonce set), or the library has not been + * previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_generate_nonce(psa_aead_operation_t *operation, + uint8_t *nonce, + size_t nonce_size, + size_t *nonce_length); + +/** Set the nonce for an authenticated encryption or decryption operation. + * + * This function sets the nonce for the authenticated + * encryption or decryption operation. + * + * The application must call psa_aead_encrypt_setup() or + * psa_aead_decrypt_setup() before calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \note When encrypting, applications should use psa_aead_generate_nonce() + * instead of this function, unless implementing a protocol that requires + * a non-random IV. + * + * \param[in,out] operation Active AEAD operation. + * \param[in] nonce Buffer containing the nonce to use. + * \param nonce_length Size of the nonce in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size of \p nonce is not acceptable for the chosen algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, with no nonce + * set), or the library has not been previously initialized + * by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_set_nonce(psa_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length); + +/** Declare the lengths of the message and additional data for AEAD. + * + * The application must call this function before calling + * psa_aead_update_ad() or psa_aead_update() if the algorithm for + * the operation requires it. If the algorithm does not require it, + * calling this function is optional, but if this function is called + * then the implementation must enforce the lengths. + * + * You may call this function before or after setting the nonce with + * psa_aead_set_nonce() or psa_aead_generate_nonce(). + * + * - For #PSA_ALG_CCM, calling this function is required. + * - For the other AEAD algorithms defined in this specification, calling + * this function is not required. + * - For vendor-defined algorithm, refer to the vendor documentation. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param ad_length Size of the non-encrypted additional + * authenticated data in bytes. + * \param plaintext_length Size of the plaintext to encrypt in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * At least one of the lengths is not acceptable for the chosen + * algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, and + * psa_aead_update_ad() and psa_aead_update() must not have been + * called yet), or the library has not been previously initialized + * by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_set_lengths(psa_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +/** Pass additional data to an active AEAD operation. + * + * Additional data is authenticated, but not encrypted. + * + * You may call this function multiple times to pass successive fragments + * of the additional data. You may not call this function after passing + * data to encrypt or decrypt with psa_aead_update(). + * + * Before calling this function, you must: + * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). + * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, + * there is no guarantee that the input is valid. Therefore, until + * you have called psa_aead_verify() and it has returned #PSA_SUCCESS, + * treat the input as untrusted and prepare to undo any action that + * depends on the input if psa_aead_verify() returns an error status. + * + * \param[in,out] operation Active AEAD operation. + * \param[in] input Buffer containing the fragment of + * additional data. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total input length overflows the additional data length that + * was previously specified with psa_aead_set_lengths(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, have a nonce + * set, have lengths set if required by the algorithm, and + * psa_aead_update() must not have been called yet), or the library + * has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_update_ad(psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Encrypt or decrypt a message fragment in an active AEAD operation. + * + * Before calling this function, you must: + * 1. Call either psa_aead_encrypt_setup() or psa_aead_decrypt_setup(). + * The choice of setup function determines whether this function + * encrypts or decrypts its input. + * 2. Set the nonce with psa_aead_generate_nonce() or psa_aead_set_nonce(). + * 3. Call psa_aead_update_ad() to pass all the additional data. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \warning When decrypting, until psa_aead_verify() has returned #PSA_SUCCESS, + * there is no guarantee that the input is valid. Therefore, until + * you have called psa_aead_verify() and it has returned #PSA_SUCCESS: + * - Do not use the output in any way other than storing it in a + * confidential location. If you take any action that depends + * on the tentative decrypted data, this action will need to be + * undone if the input turns out not to be valid. Furthermore, + * if an adversary can observe that this action took place + * (for example through timing), they may be able to use this + * fact as an oracle to decrypt any message encrypted with the + * same key. + * - In particular, do not copy the output anywhere but to a + * memory or storage space that you have exclusive access to. + * + * This function does not require the input to be aligned to any + * particular block boundary. If the implementation can only process + * a whole block at a time, it must consume all the input provided, but + * it may delay the end of the corresponding output until a subsequent + * call to psa_aead_update(), psa_aead_finish() or psa_aead_verify() + * provides sufficient input. The amount of data that can be delayed + * in this way is bounded by #PSA_AEAD_UPDATE_OUTPUT_SIZE. + * + * \param[in,out] operation Active AEAD operation. + * \param[in] input Buffer containing the message fragment to + * encrypt or decrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * \param output_size Size of the \p output buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, + * \c alg, \p input_length) where + * \c key_type is the type of key and \c alg is + * the algorithm that were used to set up the + * operation. + * - #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p + * input_length) evaluates to the maximum + * output size of any supported AEAD + * algorithm. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, \c alg, \p input_length) or + * #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length) can be used to + * determine the required buffer size. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total length of input to psa_aead_update_ad() so far is + * less than the additional data length that was previously + * specified with psa_aead_set_lengths(), or + * the total input length overflows the plaintext length that + * was previously specified with psa_aead_set_lengths(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, have a nonce + * set, and have lengths set if required by the algorithm), or the + * library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_update(psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Finish encrypting a message in an AEAD operation. + * + * The operation must have been set up with psa_aead_encrypt_setup(). + * + * This function finishes the authentication of the additional data + * formed by concatenating the inputs passed to preceding calls to + * psa_aead_update_ad() with the plaintext formed by concatenating the + * inputs passed to preceding calls to psa_aead_update(). + * + * This function has two output buffers: + * - \p ciphertext contains trailing ciphertext that was buffered from + * preceding calls to psa_aead_update(). + * - \p tag contains the authentication tag. + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param[out] ciphertext Buffer where the last part of the ciphertext + * is to be written. + * \param ciphertext_size Size of the \p ciphertext buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, + * \c alg) where \c key_type is the type of key + * and \c alg is the algorithm that were used to + * set up the operation. + * - #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE evaluates to + * the maximum output size of any supported AEAD + * algorithm. + * \param[out] ciphertext_length On success, the number of bytes of + * returned ciphertext. + * \param[out] tag Buffer where the authentication tag is + * to be written. + * \param tag_size Size of the \p tag buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - The exact tag size is #PSA_AEAD_TAG_LENGTH(\c + * key_type, \c key_bits, \c alg) where + * \c key_type and \c key_bits are the type and + * bit-size of the key, and \c alg is the + * algorithm that were used in the call to + * psa_aead_encrypt_setup(). + * - #PSA_AEAD_TAG_MAX_SIZE evaluates to the + * maximum tag size of any supported AEAD + * algorithm. + * \param[out] tag_length On success, the number of bytes + * that make up the returned tag. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p ciphertext or \p tag buffer is too small. + * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, \c alg) or + * #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE can be used to determine the + * required \p ciphertext buffer size. #PSA_AEAD_TAG_LENGTH(\c key_type, + * \c key_bits, \c alg) or #PSA_AEAD_TAG_MAX_SIZE can be used to + * determine the required \p tag buffer size. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total length of input to psa_aead_update_ad() so far is + * less than the additional data length that was previously + * specified with psa_aead_set_lengths(), or + * the total length of input to psa_aead_update() so far is + * less than the plaintext length that was previously + * specified with psa_aead_set_lengths(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active encryption + * operation with a nonce set), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_finish(psa_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +/** Finish authenticating and decrypting a message in an AEAD operation. + * + * The operation must have been set up with psa_aead_decrypt_setup(). + * + * This function finishes the authenticated decryption of the message + * components: + * + * - The additional data consisting of the concatenation of the inputs + * passed to preceding calls to psa_aead_update_ad(). + * - The ciphertext consisting of the concatenation of the inputs passed to + * preceding calls to psa_aead_update(). + * - The tag passed to this function call. + * + * If the authentication tag is correct, this function outputs any remaining + * plaintext and reports success. If the authentication tag is not correct, + * this function returns #PSA_ERROR_INVALID_SIGNATURE. + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_aead_abort(). + * + * \note Implementations shall make the best effort to ensure that the + * comparison between the actual tag and the expected tag is performed + * in constant time. + * + * \param[in,out] operation Active AEAD operation. + * \param[out] plaintext Buffer where the last part of the plaintext + * is to be written. This is the remaining data + * from previous calls to psa_aead_update() + * that could not be processed until the end + * of the input. + * \param plaintext_size Size of the \p plaintext buffer in bytes. + * This must be appropriate for the selected algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, + * \c alg) where \c key_type is the type of key + * and \c alg is the algorithm that were used to + * set up the operation. + * - #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE evaluates to + * the maximum output size of any supported AEAD + * algorithm. + * \param[out] plaintext_length On success, the number of bytes of + * returned plaintext. + * \param[in] tag Buffer containing the authentication tag. + * \param tag_length Size of the \p tag buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculations were successful, but the authentication tag is + * not correct. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p plaintext buffer is too small. + * #PSA_AEAD_VERIFY_OUTPUT_SIZE(\c key_type, \c alg) or + * #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE can be used to determine the + * required buffer size. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total length of input to psa_aead_update_ad() so far is + * less than the additional data length that was previously + * specified with psa_aead_set_lengths(), or + * the total length of input to psa_aead_update() so far is + * less than the plaintext length that was previously + * specified with psa_aead_set_lengths(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active decryption + * operation with a nonce set), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_verify(psa_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length); + +/** Abort an AEAD operation. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * psa_aead_encrypt_setup() or psa_aead_decrypt_setup() again. + * + * You may call this function any time after the operation object has + * been initialized as described in #psa_aead_operation_t. + * + * In particular, calling psa_aead_abort() after the operation has been + * terminated by a call to psa_aead_abort(), psa_aead_finish() or + * psa_aead_verify() is safe and has no effect. + * + * \param[in,out] operation Initialized AEAD operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_aead_abort(psa_aead_operation_t *operation); + +/**@}*/ + +/** \defgroup asymmetric Asymmetric cryptography + * @{ + */ + +/** + * \brief Sign a message with a private key. For hash-and-sign algorithms, + * this includes the hashing step. + * + * \note To perform a multi-part hash-and-sign signature algorithm, first use + * a multi-part hash operation and then pass the resulting hash to + * psa_sign_hash(). PSA_ALG_GET_HASH(\p alg) can be used to determine the + * hash algorithm to use. + * + * \param[in] key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. The key must + * allow the usage #PSA_KEY_USAGE_SIGN_MESSAGE. + * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) + * is true), that is compatible with the type of + * \p key. + * \param[in] input The input message to sign. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param[in] signature_size Size of the \p signature buffer in bytes. This + * must be appropriate for the selected + * algorithm and key: + * - The required signature size is + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and + * bit-size respectively of key. + * - #PSA_SIGNATURE_MAX_SIZE evaluates to the + * maximum signature size of any supported + * signature algorithm. + * \param[out] signature_length On success, the number of bytes that make up + * the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, + * or it does not permit the requested algorithm. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_sign_message(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +/** \brief Verify the signature of a message with a public key, using + * a hash-and-sign verification algorithm. + * + * \note To perform a multi-part hash-and-sign signature verification + * algorithm, first use a multi-part hash operation to hash the message + * and then pass the resulting hash to psa_verify_hash(). + * PSA_ALG_GET_HASH(\p alg) can be used to determine the hash algorithm + * to use. + * + * \param[in] key Identifier of the key to use for the operation. + * It must be a public key or an asymmetric key + * pair. The key must allow the usage + * #PSA_KEY_USAGE_VERIFY_MESSAGE. + * \param[in] alg An asymmetric signature algorithm (PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_MESSAGE(\p alg) + * is true), that is compatible with the type of + * \p key. + * \param[in] input The message whose signature is to be verified. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[out] signature Buffer containing the signature to verify. + * \param[in] signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_SIGN_MESSAGE flag, + * or it does not permit the requested algorithm. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed signature + * is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_verify_message(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length); + +/** + * \brief Sign a hash or short message with a private key. + * + * Note that to perform a hash-and-sign signature algorithm, you must + * first calculate the hash by calling psa_hash_setup(), psa_hash_update() + * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). + * Then pass the resulting hash as the \p hash + * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) + * to determine the hash algorithm to use. + * + * \param key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. The key must + * allow the usage #PSA_KEY_USAGE_SIGN_HASH. + * \param alg A signature algorithm (PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) + * is true), that is compatible with + * the type of \p key. + * \param[in] hash The hash or message to sign. + * \param hash_length Size of the \p hash buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param signature_size Size of the \p signature buffer in bytes. + * \param[out] signature_length On success, the number of bytes + * that make up the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); + +/** + * \brief Verify the signature of a hash or short message using a public key. + * + * Note that to perform a hash-and-sign signature algorithm, you must + * first calculate the hash by calling psa_hash_setup(), psa_hash_update() + * and psa_hash_finish(), or alternatively by calling psa_hash_compute(). + * Then pass the resulting hash as the \p hash + * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) + * to determine the hash algorithm to use. + * + * \param key Identifier of the key to use for the operation. It + * must be a public key or an asymmetric key pair. The + * key must allow the usage + * #PSA_KEY_USAGE_VERIFY_HASH. + * \param alg A signature algorithm (PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) + * is true), that is compatible with + * the type of \p key. + * \param[in] hash The hash or message whose signature is to be + * verified. + * \param hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The signature is valid. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); + +/** + * \brief Encrypt a short message with a public key. + * + * \param key Identifier of the key to use for the operation. + * It must be a public key or an asymmetric key + * pair. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. + * \param alg An asymmetric encryption algorithm that is + * compatible with the type of \p key. + * \param[in] input The message to encrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[in] salt A salt or label, if supported by the + * encryption algorithm. + * If the algorithm does not support a + * salt, pass \c NULL. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass \c NULL. + * + * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param salt_length Size of the \p salt buffer in bytes. + * If \p salt is \c NULL, pass 0. + * \param[out] output Buffer where the encrypted message is to + * be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** + * \brief Decrypt a short message with a private key. + * + * \param key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. It must + * allow the usage #PSA_KEY_USAGE_DECRYPT. + * \param alg An asymmetric encryption algorithm that is + * compatible with the type of \p key. + * \param[in] input The message to decrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[in] salt A salt or label, if supported by the + * encryption algorithm. + * If the algorithm does not support a + * salt, pass \c NULL. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass \c NULL. + * + * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param salt_length Size of the \p salt buffer in bytes. + * If \p salt is \c NULL, pass 0. + * \param[out] output Buffer where the decrypted message is to + * be written. + * \param output_size Size of the \c output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_INVALID_PADDING \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/**@}*/ + +/** \defgroup key_derivation Key derivation and pseudorandom generation + * @{ + */ + +/** The type of the state data structure for key derivation operations. + * + * Before calling any function on a key derivation operation object, the + * application must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_key_derivation_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_key_derivation_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_KEY_DERIVATION_OPERATION_INIT, + * for example: + * \code + * psa_key_derivation_operation_t operation = PSA_KEY_DERIVATION_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_key_derivation_operation_init() + * to the structure, for example: + * \code + * psa_key_derivation_operation_t operation; + * operation = psa_key_derivation_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. + */ +typedef struct psa_key_derivation_s psa_key_derivation_operation_t; + +/** \def PSA_KEY_DERIVATION_OPERATION_INIT + * + * This macro returns a suitable initializer for a key derivation operation + * object of type #psa_key_derivation_operation_t. + */ + +/** Return an initial value for a key derivation operation object. + */ +static psa_key_derivation_operation_t psa_key_derivation_operation_init(void); + +/** Set up a key derivation operation. + * + * A key derivation algorithm takes some inputs and uses them to generate + * a byte stream in a deterministic way. + * This byte stream can be used to produce keys and other + * cryptographic material. + * + * To derive a key: + * -# Start with an initialized object of type #psa_key_derivation_operation_t. + * -# Call psa_key_derivation_setup() to select the algorithm. + * -# Provide the inputs for the key derivation by calling + * psa_key_derivation_input_bytes() or psa_key_derivation_input_key() + * as appropriate. Which inputs are needed, in what order, and whether + * they may be keys and if so of what type depends on the algorithm. + * -# Optionally set the operation's maximum capacity with + * psa_key_derivation_set_capacity(). You may do this before, in the middle + * of or after providing inputs. For some algorithms, this step is mandatory + * because the output depends on the maximum capacity. + * -# To derive a key, call psa_key_derivation_output_key(). + * To derive a byte string for a different purpose, call + * psa_key_derivation_output_bytes(). + * Successive calls to these functions use successive output bytes + * calculated by the key derivation algorithm. + * -# Clean up the key derivation operation object with + * psa_key_derivation_abort(). + * + * If this function returns an error, the key derivation operation object is + * not changed. + * + * If an error occurs at any step after a call to psa_key_derivation_setup(), + * the operation will need to be reset by a call to psa_key_derivation_abort(). + * + * Implementations must reject an attempt to derive a key of size 0. + * + * \param[in,out] operation The key derivation operation object + * to set up. It must + * have been initialized but not set up yet. + * \param alg The key derivation algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c alg is not a key derivation algorithm. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \c alg is not supported or is not a key derivation algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_setup( + psa_key_derivation_operation_t *operation, + psa_algorithm_t alg); + +/** Retrieve the current capacity of a key derivation operation. + * + * The capacity of a key derivation is the maximum number of bytes that it can + * return. When you get *N* bytes of output from a key derivation operation, + * this reduces its capacity by *N*. + * + * \param[in] operation The operation to query. + * \param[out] capacity On success, the capacity of the operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_get_capacity( + const psa_key_derivation_operation_t *operation, + size_t *capacity); + +/** Set the maximum capacity of a key derivation operation. + * + * The capacity of a key derivation operation is the maximum number of bytes + * that the key derivation operation can return from this point onwards. + * + * \param[in,out] operation The key derivation operation object to modify. + * \param capacity The new capacity of the operation. + * It must be less or equal to the operation's + * current capacity. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p capacity is larger than the operation's current capacity. + * In this case, the operation object remains valid and its capacity + * remains unchanged. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active), or the + * library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_set_capacity( + psa_key_derivation_operation_t *operation, + size_t capacity); + +/** Use the maximum possible capacity for a key derivation operation. + * + * Use this value as the capacity argument when setting up a key derivation + * to indicate that the operation should have the maximum possible capacity. + * The value of the maximum possible capacity depends on the key derivation + * algorithm. + */ +#define PSA_KEY_DERIVATION_UNLIMITED_CAPACITY ((size_t) (-1)) + +/** Provide an input for key derivation or key agreement. + * + * Which inputs are required and in what order depends on the algorithm. + * Refer to the documentation of each key derivation or key agreement + * algorithm for information. + * + * This function passes direct inputs, which is usually correct for + * non-secret inputs. To pass a secret input, which should be in a key + * object, call psa_key_derivation_input_key() instead of this function. + * Refer to the documentation of individual step types + * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) + * for more information. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to use. + * It must have been set up with + * psa_key_derivation_setup() and must not + * have produced any output yet. + * \param step Which step the input data is for. + * \param[in] data Input data to use. + * \param data_length Size of the \p data buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c step is not compatible with the operation's algorithm, or + * \c step does not allow direct inputs. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid for this input \p step, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_input_bytes( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length); + +/** Provide a numeric input for key derivation or key agreement. + * + * Which inputs are required and in what order depends on the algorithm. + * However, when an algorithm requires a particular order, numeric inputs + * usually come first as they tend to be configuration parameters. + * Refer to the documentation of each key derivation or key agreement + * algorithm for information. + * + * This function is used for inputs which are fixed-size non-negative + * integers. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to use. + * It must have been set up with + * psa_key_derivation_setup() and must not + * have produced any output yet. + * \param step Which step the input data is for. + * \param[in] value The value of the numeric input. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c step is not compatible with the operation's algorithm, or + * \c step does not allow numeric inputs. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid for this input \p step, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_input_integer( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + uint64_t value); + +/** Provide an input for key derivation in the form of a key. + * + * Which inputs are required and in what order depends on the algorithm. + * Refer to the documentation of each key derivation or key agreement + * algorithm for information. + * + * This function obtains input from a key object, which is usually correct for + * secret inputs or for non-secret personalization strings kept in the key + * store. To pass a non-secret parameter which is not in the key store, + * call psa_key_derivation_input_bytes() instead of this function. + * Refer to the documentation of individual step types + * (`PSA_KEY_DERIVATION_INPUT_xxx` values of type ::psa_key_derivation_step_t) + * for more information. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to use. + * It must have been set up with + * psa_key_derivation_setup() and must not + * have produced any output yet. + * \param step Which step the input data is for. + * \param key Identifier of the key. It must have an + * appropriate type for step and must allow the + * usage #PSA_KEY_USAGE_DERIVE or + * #PSA_KEY_USAGE_VERIFY_DERIVATION (see note) + * and the algorithm used by the operation. + * + * \note Once all inputs steps are completed, the operations will allow: + * - psa_key_derivation_output_bytes() if each input was either a direct input + * or a key with #PSA_KEY_USAGE_DERIVE set; + * - psa_key_derivation_output_key() if the input for step + * #PSA_KEY_DERIVATION_INPUT_SECRET or #PSA_KEY_DERIVATION_INPUT_PASSWORD + * was from a key slot with #PSA_KEY_USAGE_DERIVE and each other input was + * either a direct input or a key with #PSA_KEY_USAGE_DERIVE set; + * - psa_key_derivation_verify_bytes() if each input was either a direct input + * or a key with #PSA_KEY_USAGE_VERIFY_DERIVATION set; + * - psa_key_derivation_verify_key() under the same conditions as + * psa_key_derivation_verify_bytes(). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The key allows neither #PSA_KEY_USAGE_DERIVE nor + * #PSA_KEY_USAGE_VERIFY_DERIVATION, or it doesn't allow this + * algorithm. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c step is not compatible with the operation's algorithm, or + * \c step does not allow key inputs of the given type + * or does not allow key inputs at all. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid for this input \p step, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_input_key( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + mbedtls_svc_key_id_t key); + +/** Perform a single-shot key derivation operation and output the resulting key. + * + * NOTE: this is a Silicon Labs custom API, and is not a part of the official + * PSA Cryptography specification. + * + * This function supports HKDF and PBKDF2. + * + * This function obtains its secret input from a key object, and any additional + * inputs such as buffers and integers. The output of this function is a key + * object containing the output of the selected key derivation function. + * + * \param alg The key derivation algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_KEY_DERIVATION(\p alg) is true). + * \param key_in Identifier of the secret key to input to the + * operation. It must allow the usage + * PSA_KEY_USAGE_DERIVE and be of a symmetric + * type. + * \param[in] info A context- and application specific + * information string. Only used for HKDF, but + * can be omitted. + * \param info_length The length of the provided info in bytes. + * \param[in] salt An optional salt value (a non-secret random value). + * Used for both HKDF and PBKDF2. Recommended for + * PBKDF2. + * \param salt_length The length of the provided salt in bytes. + * \param iterations The number of iterations to use. Maximum + * supported value is 16384. Only used for PBKDF2. + * \param[in] key_out_attributes The attributes for the new key output by the + * derivation operation. The key must be of a + * symmetric type. + * \param[out] key_out The identifier of the new key output by the + * derivation operation. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_NOT_PERMITTED + * The input key does not have the required usage policy set. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The input- or output key is not of a symmetric type. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The input- or output key is larger than what the SE can handle. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The requested algorithm is not supported. + * \retval #PSA_ERROR_HARDWARE_FAILURE + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t sl_psa_key_derivation_single_shot( + psa_algorithm_t alg, + mbedtls_svc_key_id_t key_in, + const uint8_t *info, + size_t info_length, + const uint8_t *salt, + size_t salt_length, + size_t iterations, + const psa_key_attributes_t *key_out_attributes, + mbedtls_svc_key_id_t *key_out); + +/** Perform a key agreement and use the shared secret as input to a key + * derivation. + * + * A key agreement algorithm takes two inputs: a private key \p private_key + * a public key \p peer_key. + * The result of this function is passed as input to a key derivation. + * The output of this key derivation can be extracted by reading from the + * resulting operation to produce keys and other cryptographic material. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to use. + * It must have been set up with + * psa_key_derivation_setup() with a + * key agreement and derivation algorithm + * \c alg (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_KEY_AGREEMENT(\c alg) is true + * and #PSA_ALG_IS_RAW_KEY_AGREEMENT(\c alg) + * is false). + * The operation must be ready for an + * input of the type given by \p step. + * \param step Which step the input data is for. + * \param private_key Identifier of the private key to use. It must + * allow the usage #PSA_KEY_USAGE_DERIVE. + * \param[in] peer_key Public key of the peer. The peer key must be in the + * same format that psa_import_key() accepts for the + * public key type corresponding to the type of + * private_key. That is, this function performs the + * equivalent of + * #psa_import_key(..., + * `peer_key`, `peer_key_length`) where + * with key attributes indicating the public key + * type corresponding to the type of `private_key`. + * For example, for EC keys, this means that peer_key + * is interpreted as a point on the curve that the + * private key is on. The standard formats for public + * keys are documented in the documentation of + * psa_export_public_key(). + * \param peer_key_length Size of \p peer_key in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c private_key is not compatible with \c alg, + * or \p peer_key is not valid for \c alg or not compatible with + * \c private_key, or \c step does not allow an input resulting + * from a key agreement. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \c alg is not supported or is not a key derivation algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid for this key agreement \p step, + * or the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_key_agreement( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + mbedtls_svc_key_id_t private_key, + const uint8_t *peer_key, + size_t peer_key_length); + +/** Read some data from a key derivation operation. + * + * This function calculates output bytes from a key derivation algorithm and + * return those bytes. + * If you view the key derivation's output as a stream of bytes, this + * function destructively reads the requested number of bytes from the + * stream. + * The operation's capacity decreases by the number of bytes read. + * + * If this function returns an error status other than + * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to read from. + * \param[out] output Buffer where the output will be written. + * \param output_length Number of bytes to output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * One of the inputs was a key whose policy didn't allow + * #PSA_KEY_USAGE_DERIVE. + * \retval #PSA_ERROR_INSUFFICIENT_DATA + * The operation's capacity was less than + * \p output_length bytes. Note that in this case, + * no output is written to the output buffer. + * The operation's capacity is set to 0, thus + * subsequent calls to this function will not + * succeed, even with a smaller output buffer. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active and completed + * all required input steps), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_output_bytes( + psa_key_derivation_operation_t *operation, + uint8_t *output, + size_t output_length); + +/** Derive a key from an ongoing key derivation operation. + * + * This function calculates output bytes from a key derivation algorithm + * and uses those bytes to generate a key deterministically. + * The key's location, usage policy, type and size are taken from + * \p attributes. + * + * If you view the key derivation's output as a stream of bytes, this + * function destructively reads as many bytes as required from the + * stream. + * The operation's capacity decreases by the number of bytes read. + * + * If this function returns an error status other than + * #PSA_ERROR_INSUFFICIENT_DATA, the operation enters an error + * state and must be aborted by calling psa_key_derivation_abort(). + * + * How much output is produced and consumed from the operation, and how + * the key is derived, depends on the key type and on the key size + * (denoted \c bits below): + * + * - For key types for which the key is an arbitrary sequence of bytes + * of a given size, this function is functionally equivalent to + * calling #psa_key_derivation_output_bytes + * and passing the resulting output to #psa_import_key. + * However, this function has a security benefit: + * if the implementation provides an isolation boundary then + * the key material is not exposed outside the isolation boundary. + * As a consequence, for these key types, this function always consumes + * exactly (\c bits / 8) bytes from the operation. + * The following key types defined in this specification follow this scheme: + * + * - #PSA_KEY_TYPE_AES; + * - #PSA_KEY_TYPE_ARIA; + * - #PSA_KEY_TYPE_CAMELLIA; + * - #PSA_KEY_TYPE_DERIVE; + * - #PSA_KEY_TYPE_HMAC; + * - #PSA_KEY_TYPE_PASSWORD_HASH. + * + * - For ECC keys on a Montgomery elliptic curve + * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a + * Montgomery curve), this function always draws a byte string whose + * length is determined by the curve, and sets the mandatory bits + * accordingly. That is: + * + * - Curve25519 (#PSA_ECC_FAMILY_MONTGOMERY, 255 bits): draw a 32-byte + * string and process it as specified in RFC 7748 §5. + * - Curve448 (#PSA_ECC_FAMILY_MONTGOMERY, 448 bits): draw a 56-byte + * string and process it as specified in RFC 7748 §5. + * + * - For key types for which the key is represented by a single sequence of + * \c bits bits with constraints as to which bit sequences are acceptable, + * this function draws a byte string of length (\c bits / 8) bytes rounded + * up to the nearest whole number of bytes. If the resulting byte string + * is acceptable, it becomes the key, otherwise the drawn bytes are discarded. + * This process is repeated until an acceptable byte string is drawn. + * The byte string drawn from the operation is interpreted as specified + * for the output produced by psa_export_key(). + * The following key types defined in this specification follow this scheme: + * + * - #PSA_KEY_TYPE_DES. + * Force-set the parity bits, but discard forbidden weak keys. + * For 2-key and 3-key triple-DES, the three keys are generated + * successively (for example, for 3-key triple-DES, + * if the first 8 bytes specify a weak key and the next 8 bytes do not, + * discard the first 8 bytes, use the next 8 bytes as the first key, + * and continue reading output from the operation to derive the other + * two keys). + * - Finite-field Diffie-Hellman keys (#PSA_KEY_TYPE_DH_KEY_PAIR(\c group) + * where \c group designates any Diffie-Hellman group) and + * ECC keys on a Weierstrass elliptic curve + * (#PSA_KEY_TYPE_ECC_KEY_PAIR(\c curve) where \c curve designates a + * Weierstrass curve). + * For these key types, interpret the byte string as integer + * in big-endian order. Discard it if it is not in the range + * [0, *N* - 2] where *N* is the boundary of the private key domain + * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, + * or the order of the curve's base point for ECC). + * Add 1 to the resulting integer and use this as the private key *x*. + * This method allows compliance to NIST standards, specifically + * the methods titled "key-pair generation by testing candidates" + * in NIST SP 800-56A §5.6.1.1.4 for Diffie-Hellman, + * in FIPS 186-4 §B.1.2 for DSA, and + * in NIST SP 800-56A §5.6.1.2.2 or + * FIPS 186-4 §B.4.2 for elliptic curve keys. + * + * - For other key types, including #PSA_KEY_TYPE_RSA_KEY_PAIR, + * the way in which the operation output is consumed is + * implementation-defined. + * + * In all cases, the data that is read is discarded from the operation. + * The operation's capacity is decreased by the number of bytes read. + * + * For algorithms that take an input step #PSA_KEY_DERIVATION_INPUT_SECRET, + * the input to that step must be provided with psa_key_derivation_input_key(). + * Future versions of this specification may include additional restrictions + * on the derived key based on the attributes and strength of the secret key. + * + * \param[in] attributes The attributes for the new key. + * If the key type to be created is + * #PSA_KEY_TYPE_PASSWORD_HASH then the algorithm in + * the policy must be the same as in the current + * operation. + * \param[in,out] operation The key derivation operation object to read from. + * \param[out] key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. + * \c 0 on failure. + * + * \retval #PSA_SUCCESS + * Success. + * If the key is persistent, the key material and the key's metadata + * have been saved to persistent storage. + * \retval #PSA_ERROR_ALREADY_EXISTS + * This is an attempt to create a persistent key, and there is + * already a persistent key with the given identifier. + * \retval #PSA_ERROR_INSUFFICIENT_DATA + * There was not enough data to create the desired key. + * Note that in this case, no output is written to the output buffer. + * The operation's capacity is set to 0, thus subsequent calls to + * this function will not succeed, even with a smaller output buffer. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The key type or key size is not supported, either by the + * implementation in general or in this particular location. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The provided key attributes are not valid for the operation. + * \retval #PSA_ERROR_NOT_PERMITTED + * The #PSA_KEY_DERIVATION_INPUT_SECRET or + * #PSA_KEY_DERIVATION_INPUT_PASSWORD input was not provided through a + * key; or one of the inputs was a key whose policy didn't allow + * #PSA_KEY_USAGE_DERIVE. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active and completed + * all required input steps), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_output_key( + const psa_key_attributes_t *attributes, + psa_key_derivation_operation_t *operation, + mbedtls_svc_key_id_t *key); + +/** Compare output data from a key derivation operation to an expected value. + * + * This function calculates output bytes from a key derivation algorithm and + * compares those bytes to an expected value in constant time. + * If you view the key derivation's output as a stream of bytes, this + * function destructively reads the expected number of bytes from the + * stream before comparing them. + * The operation's capacity decreases by the number of bytes read. + * + * This is functionally equivalent to the following code: + * \code + * psa_key_derivation_output_bytes(operation, tmp, output_length); + * if (memcmp(output, tmp, output_length) != 0) + * return PSA_ERROR_INVALID_SIGNATURE; + * \endcode + * except (1) it works even if the key's policy does not allow outputting the + * bytes, and (2) the comparison will be done in constant time. + * + * If this function returns an error status other than + * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, + * the operation enters an error state and must be aborted by calling + * psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to read from. + * \param[in] expected_output Buffer containing the expected derivation output. + * \param output_length Length of the expected output; this is also the + * number of bytes that will be read. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The output was read successfully, but it differs from the expected + * output. + * \retval #PSA_ERROR_NOT_PERMITTED + * One of the inputs was a key whose policy didn't allow + * #PSA_KEY_USAGE_VERIFY_DERIVATION. + * \retval #PSA_ERROR_INSUFFICIENT_DATA + * The operation's capacity was less than + * \p output_length bytes. Note that in this case, + * the operation's capacity is set to 0, thus + * subsequent calls to this function will not + * succeed, even with a smaller expected output. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active and completed + * all required input steps), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_verify_bytes( + psa_key_derivation_operation_t *operation, + const uint8_t *expected_output, + size_t output_length); + +/** Compare output data from a key derivation operation to an expected value + * stored in a key object. + * + * This function calculates output bytes from a key derivation algorithm and + * compares those bytes to an expected value, provided as key of type + * #PSA_KEY_TYPE_PASSWORD_HASH. + * If you view the key derivation's output as a stream of bytes, this + * function destructively reads the number of bytes corresponding to the + * length of the expected value from the stream before comparing them. + * The operation's capacity decreases by the number of bytes read. + * + * This is functionally equivalent to exporting the key and calling + * psa_key_derivation_verify_bytes() on the result, except that it + * works even if the key cannot be exported. + * + * If this function returns an error status other than + * #PSA_ERROR_INSUFFICIENT_DATA or #PSA_ERROR_INVALID_SIGNATURE, + * the operation enters an error state and must be aborted by calling + * psa_key_derivation_abort(). + * + * \param[in,out] operation The key derivation operation object to read from. + * \param[in] expected A key of type #PSA_KEY_TYPE_PASSWORD_HASH + * containing the expected output. Its policy must + * include the #PSA_KEY_USAGE_VERIFY_DERIVATION flag + * and the permitted algorithm must match the + * operation. The value of this key was likely + * computed by a previous call to + * psa_key_derivation_output_key(). + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The output was read successfully, but if differs from the expected + * output. + * \retval #PSA_ERROR_INVALID_HANDLE + * The key passed as the expected value does not exist. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key passed as the expected value has an invalid type. + * \retval #PSA_ERROR_NOT_PERMITTED + * The key passed as the expected value does not allow this usage or + * this algorithm; or one of the inputs was a key whose policy didn't + * allow #PSA_KEY_USAGE_VERIFY_DERIVATION. + * \retval #PSA_ERROR_INSUFFICIENT_DATA + * The operation's capacity was less than + * the length of the expected value. In this case, + * the operation's capacity is set to 0, thus + * subsequent calls to this function will not + * succeed, even with a smaller expected output. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active and completed + * all required input steps), or the library has not been previously + * initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_verify_key( + psa_key_derivation_operation_t *operation, + psa_key_id_t expected); + +/** Abort a key derivation operation. + * + * Aborting an operation frees all associated resources except for the \c + * operation structure itself. Once aborted, the operation object can be reused + * for another operation by calling psa_key_derivation_setup() again. + * + * This function may be called at any time after the operation + * object has been initialized as described in #psa_key_derivation_operation_t. + * + * In particular, it is valid to call psa_key_derivation_abort() twice, or to + * call psa_key_derivation_abort() on an operation that has not been set up. + * + * \param[in,out] operation The operation to abort. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_key_derivation_abort( + psa_key_derivation_operation_t *operation); + +/** Perform a key agreement and return the raw shared secret. + * + * \warning The raw result of a key agreement algorithm such as finite-field + * Diffie-Hellman or elliptic curve Diffie-Hellman has biases and should + * not be used directly as key material. It should instead be passed as + * input to a key derivation algorithm. To chain a key agreement with + * a key derivation, use psa_key_derivation_key_agreement() and other + * functions from the key derivation interface. + * + * \param alg The key agreement algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_RAW_KEY_AGREEMENT(\p alg) + * is true). + * \param private_key Identifier of the private key to use. It must + * allow the usage #PSA_KEY_USAGE_DERIVE. + * \param[in] peer_key Public key of the peer. It must be + * in the same format that psa_import_key() + * accepts. The standard formats for public + * keys are documented in the documentation + * of psa_export_public_key(). + * \param peer_key_length Size of \p peer_key in bytes. + * \param[out] output Buffer where the decrypted message is to + * be written. + * \param output_size Size of the \c output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p alg is not a key agreement algorithm, or + * \p private_key is not compatible with \p alg, + * or \p peer_key is not valid for \p alg or not compatible with + * \p private_key. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p output_size is too small + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not a supported key agreement algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, + mbedtls_svc_key_id_t private_key, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/**@}*/ + +/** \defgroup random Random generation + * @{ + */ + +/** + * \brief Generate random bytes. + * + * \warning This function **can** fail! Callers MUST check the return status + * and MUST NOT use the content of the output buffer if the return + * status is not #PSA_SUCCESS. + * + * \note To generate a key, use psa_generate_key() instead. + * + * \param[out] output Output buffer for the generated data. + * \param output_size Number of bytes to generate and output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_generate_random(uint8_t *output, + size_t output_size); + +/** + * \brief Generate a key or key pair. + * + * The key is generated randomly. + * Its location, usage policy, type and size are taken from \p attributes. + * + * Implementations must reject an attempt to generate a key of size 0. + * + * The following type-specific considerations apply: + * - For RSA keys (#PSA_KEY_TYPE_RSA_KEY_PAIR), + * the public exponent is 65537. + * The modulus is a product of two probabilistic primes + * between 2^{n-1} and 2^n where n is the bit size specified in the + * attributes. + * + * \param[in] attributes The attributes for the new key. + * \param[out] key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. + * \c 0 on failure. + * + * \retval #PSA_SUCCESS + * Success. + * If the key is persistent, the key material and the key's metadata + * have been saved to persistent storage. + * \retval #PSA_ERROR_ALREADY_EXISTS + * This is an attempt to create a persistent key, and there is + * already a persistent key with the given identifier. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t *key); + +/**@}*/ + +/** \defgroup interruptible_hash Interruptible sign/verify hash + * @{ + */ + +/** The type of the state data structure for interruptible hash + * signing operations. + * + * Before calling any function on a sign hash operation object, the + * application must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_sign_hash_interruptible_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_sign_hash_interruptible_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer + * #PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: + * \code + * psa_sign_hash_interruptible_operation_t operation = + * PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; + * \endcode + * - Assign the result of the function + * psa_sign_hash_interruptible_operation_init() to the structure, for + * example: + * \code + * psa_sign_hash_interruptible_operation_t operation; + * operation = psa_sign_hash_interruptible_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_sign_hash_interruptible_operation_s psa_sign_hash_interruptible_operation_t; + +/** The type of the state data structure for interruptible hash + * verification operations. + * + * Before calling any function on a sign hash operation object, the + * application must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_verify_hash_interruptible_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_verify_hash_interruptible_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer + * #PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT, for example: + * \code + * psa_verify_hash_interruptible_operation_t operation = + * PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; + * \endcode + * - Assign the result of the function + * psa_verify_hash_interruptible_operation_init() to the structure, for + * example: + * \code + * psa_verify_hash_interruptible_operation_t operation; + * operation = psa_verify_hash_interruptible_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_verify_hash_interruptible_operation_s psa_verify_hash_interruptible_operation_t; + +/** + * \brief Set the maximum number of ops allowed to be + * executed by an interruptible function in a + * single call. + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note The time taken to execute a single op is + * implementation specific and depends on + * software, hardware, the algorithm, key type and + * curve chosen. Even within a single operation, + * successive ops can take differing amounts of + * time. The only guarantee is that lower values + * for \p max_ops means functions will block for a + * lesser maximum amount of time. The functions + * \c psa_sign_interruptible_get_num_ops() and + * \c psa_verify_interruptible_get_num_ops() are + * provided to help with tuning this value. + * + * \note This value defaults to + * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, which + * means the whole operation will be done in one + * go, regardless of the number of ops required. + * + * \note If more ops are needed to complete a + * computation, #PSA_OPERATION_INCOMPLETE will be + * returned by the function performing the + * computation. It is then the caller's + * responsibility to either call again with the + * same operation context until it returns 0 or an + * error code; or to call the relevant abort + * function if the answer is no longer required. + * + * \note The interpretation of \p max_ops is also + * implementation defined. On a hard real time + * system, this can indicate a hard deadline, as a + * real-time system needs a guarantee of not + * spending more than X time, however care must be + * taken in such an implementation to avoid the + * situation whereby calls just return, not being + * able to do any actual work within the allotted + * time. On a non-real-time system, the + * implementation can be more relaxed, but again + * whether this number should be interpreted as as + * hard or soft limit or even whether a less than + * or equals as regards to ops executed in a + * single call is implementation defined. + * + * \note For keys in local storage when no accelerator + * driver applies, please see also the + * documentation for \c mbedtls_ecp_set_max_ops(), + * which is the internal implementation in these + * cases. + * + * \warning With implementations that interpret this number + * as a hard limit, setting this number too small + * may result in an infinite loop, whereby each + * call results in immediate return with no ops + * done (as there is not enough time to execute + * any), and thus no result will ever be achieved. + * + * \note This only applies to functions whose + * documentation mentions they may return + * #PSA_OPERATION_INCOMPLETE. + * + * \param max_ops The maximum number of ops to be executed in a + * single call. This can be a number from 0 to + * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, where 0 + * is the least amount of work done per call. + */ +void psa_interruptible_set_max_ops(uint32_t max_ops); + +/** + * \brief Get the maximum number of ops allowed to be + * executed by an interruptible function in a + * single call. This will return the last + * value set by + * \c psa_interruptible_set_max_ops() or + * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED if + * that function has never been called. + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \return Maximum number of ops allowed to be + * executed by an interruptible function in a + * single call. + */ +uint32_t psa_interruptible_get_max_ops(void); + +/** + * \brief Get the number of ops that a hash signing + * operation has taken so far. If the operation + * has completed, then this will represent the + * number of ops required for the entire + * operation. After initialization or calling + * \c psa_sign_hash_interruptible_abort() on + * the operation, a value of 0 will be returned. + * + * \note This interface is guaranteed re-entrant and + * thus may be called from driver code. + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * This is a helper provided to help you tune the + * value passed to \c + * psa_interruptible_set_max_ops(). + * + * \param operation The \c psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \return Number of ops that the operation has taken so + * far. + */ +uint32_t psa_sign_hash_get_num_ops( + const psa_sign_hash_interruptible_operation_t *operation); + +/** + * \brief Get the number of ops that a hash verification + * operation has taken so far. If the operation + * has completed, then this will represent the + * number of ops required for the entire + * operation. After initialization or calling \c + * psa_verify_hash_interruptible_abort() on the + * operation, a value of 0 will be returned. + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * This is a helper provided to help you tune the + * value passed to \c + * psa_interruptible_set_max_ops(). + * + * \param operation The \c + * psa_verify_hash_interruptible_operation_t to + * use. This must be initialized first. + * + * \return Number of ops that the operation has taken so + * far. + */ +uint32_t psa_verify_hash_get_num_ops( + const psa_verify_hash_interruptible_operation_t *operation); + +/** + * \brief Start signing a hash or short message with a + * private key, in an interruptible manner. + * + * \see \c psa_sign_hash_complete() + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note This function combined with \c + * psa_sign_hash_complete() is equivalent to + * \c psa_sign_hash() but + * \c psa_sign_hash_complete() can return early and + * resume according to the limit set with \c + * psa_interruptible_set_max_ops() to reduce the + * maximum time spent in a function call. + * + * \note Users should call \c psa_sign_hash_complete() + * repeatedly on the same context after a + * successful call to this function until \c + * psa_sign_hash_complete() either returns 0 or an + * error. \c psa_sign_hash_complete() will return + * #PSA_OPERATION_INCOMPLETE if there is more work + * to do. Alternatively users can call + * \c psa_sign_hash_abort() at any point if they no + * longer want the result. + * + * \note If this function returns an error status, the + * operation enters an error state and must be + * aborted by calling \c psa_sign_hash_abort(). + * + * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \param key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. The key must + * allow the usage #PSA_KEY_USAGE_SIGN_HASH. + * \param alg A signature algorithm (\c PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) + * is true), that is compatible with + * the type of \p key. + * \param[in] hash The hash or message to sign. + * \param hash_length Size of the \p hash buffer in bytes. + * + * \retval #PSA_SUCCESS + * The operation started successfully - call \c psa_sign_hash_complete() + * with the same context to complete the operation + * + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_SIGN_HASH flag, or it does + * not permit the requested algorithm. + * \retval #PSA_ERROR_BAD_STATE + * An operation has previously been started on this context, and is + * still in progress. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_sign_hash_start( + psa_sign_hash_interruptible_operation_t *operation, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length); + +/** + * \brief Continue and eventually complete the action of + * signing a hash or short message with a private + * key, in an interruptible manner. + * + * \see \c psa_sign_hash_start() + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note This function combined with \c + * psa_sign_hash_start() is equivalent to + * \c psa_sign_hash() but this function can return + * early and resume according to the limit set with + * \c psa_interruptible_set_max_ops() to reduce the + * maximum time spent in a function call. + * + * \note Users should call this function on the same + * operation object repeatedly until it either + * returns 0 or an error. This function will return + * #PSA_OPERATION_INCOMPLETE if there is more work + * to do. Alternatively users can call + * \c psa_sign_hash_abort() at any point if they no + * longer want the result. + * + * \note When this function returns successfully, the + * operation becomes inactive. If this function + * returns an error status, the operation enters an + * error state and must be aborted by calling + * \c psa_sign_hash_abort(). + * + * \param[in, out] operation The \c psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first, and have + * had \c psa_sign_hash_start() called with it + * first. + * + * \param[out] signature Buffer where the signature is to be written. + * \param signature_size Size of the \p signature buffer in bytes. This + * must be appropriate for the selected + * algorithm and key: + * - The required signature size is + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c + * key_bits, \c alg) where \c key_type and \c + * key_bits are the type and bit-size + * respectively of key. + * - #PSA_SIGNATURE_MAX_SIZE evaluates to the + * maximum signature size of any supported + * signature algorithm. + * \param[out] signature_length On success, the number of bytes that make up + * the returned signature value. + * + * \retval #PSA_SUCCESS + * Operation completed successfully + * + * \retval #PSA_OPERATION_INCOMPLETE + * Operation was interrupted due to the setting of \c + * psa_interruptible_set_max_ops(). There is still work to be done. + * Call this function again with the same operation object. + * + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \c alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \c key. + * + * \retval #PSA_ERROR_BAD_STATE + * An operation was not previously started on this context via + * \c psa_sign_hash_start(). + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has either not been previously initialized by + * psa_crypto_init() or you did not previously call + * psa_sign_hash_start() with this operation object. It is + * implementation-dependent whether a failure to initialize results in + * this error code. + */ +psa_status_t psa_sign_hash_complete( + psa_sign_hash_interruptible_operation_t *operation, + uint8_t *signature, size_t signature_size, + size_t *signature_length); + +/** + * \brief Abort a sign hash operation. + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note This function is the only function that clears + * the number of ops completed as part of the + * operation. Please ensure you copy this value via + * \c psa_sign_hash_get_num_ops() if required + * before calling. + * + * \note Aborting an operation frees all associated + * resources except for the \p operation structure + * itself. Once aborted, the operation object can + * be reused for another operation by calling \c + * psa_sign_hash_start() again. + * + * \note You may call this function any time after the + * operation object has been initialized. In + * particular, calling \c psa_sign_hash_abort() + * after the operation has already been terminated + * by a call to \c psa_sign_hash_abort() or + * psa_sign_hash_complete() is safe. + * + * \param[in,out] operation Initialized sign hash operation. + * + * \retval #PSA_SUCCESS + * The operation was aborted successfully. + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_sign_hash_abort( + psa_sign_hash_interruptible_operation_t *operation); + +/** + * \brief Start reading and verifying a hash or short + * message, in an interruptible manner. + * + * \see \c psa_verify_hash_complete() + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note This function combined with \c + * psa_verify_hash_complete() is equivalent to + * \c psa_verify_hash() but \c + * psa_verify_hash_complete() can return early and + * resume according to the limit set with \c + * psa_interruptible_set_max_ops() to reduce the + * maximum time spent in a function. + * + * \note Users should call \c psa_verify_hash_complete() + * repeatedly on the same operation object after a + * successful call to this function until \c + * psa_verify_hash_complete() either returns 0 or + * an error. \c psa_verify_hash_complete() will + * return #PSA_OPERATION_INCOMPLETE if there is + * more work to do. Alternatively users can call + * \c psa_verify_hash_abort() at any point if they + * no longer want the result. + * + * \note If this function returns an error status, the + * operation enters an error state and must be + * aborted by calling \c psa_verify_hash_abort(). + * + * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \param key Identifier of the key to use for the operation. + * The key must allow the usage + * #PSA_KEY_USAGE_VERIFY_HASH. + * \param alg A signature algorithm (\c PSA_ALG_XXX + * value such that #PSA_ALG_IS_SIGN_HASH(\p alg) + * is true), that is compatible with + * the type of \p key. + * \param[in] hash The hash whose signature is to be verified. + * \param hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The operation started successfully - please call \c + * psa_verify_hash_complete() with the same context to complete the + * operation. + * + * \retval #PSA_ERROR_BAD_STATE + * Another operation has already been started on this context, and is + * still in progress. + * + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_VERIFY_HASH flag, or it does + * not permit the requested algorithm. + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_verify_hash_start( + psa_verify_hash_interruptible_operation_t *operation, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length); + +/** + * \brief Continue and eventually complete the action of + * reading and verifying a hash or short message + * signed with a private key, in an interruptible + * manner. + * + * \see \c psa_verify_hash_start() + * + * \warning This is a beta API, and thus subject to change + * at any point. It is not bound by the usual + * interface stability promises. + * + * \note This function combined with \c + * psa_verify_hash_start() is equivalent to + * \c psa_verify_hash() but this function can + * return early and resume according to the limit + * set with \c psa_interruptible_set_max_ops() to + * reduce the maximum time spent in a function + * call. + * + * \note Users should call this function on the same + * operation object repeatedly until it either + * returns 0 or an error. This function will return + * #PSA_OPERATION_INCOMPLETE if there is more work + * to do. Alternatively users can call + * \c psa_verify_hash_abort() at any point if they + * no longer want the result. + * + * \note When this function returns successfully, the + * operation becomes inactive. If this function + * returns an error status, the operation enters an + * error state and must be aborted by calling + * \c psa_verify_hash_abort(). + * + * \param[in, out] operation The \c psa_verify_hash_interruptible_operation_t + * to use. This must be initialized first, and have + * had \c psa_verify_hash_start() called with it + * first. + * + * \retval #PSA_SUCCESS + * Operation completed successfully, and the passed signature is valid. + * + * \retval #PSA_OPERATION_INCOMPLETE + * Operation was interrupted due to the setting of \c + * psa_interruptible_set_max_ops(). There is still work to be done. + * Call this function again with the same operation object. + * + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_BAD_STATE + * An operation was not previously started on this context via + * \c psa_verify_hash_start(). + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has either not been previously initialized by + * psa_crypto_init() or you did not previously call + * psa_verify_hash_start() on this object. It is + * implementation-dependent whether a failure to initialize results in + * this error code. + */ +psa_status_t psa_verify_hash_complete( + psa_verify_hash_interruptible_operation_t *operation); + +/** + * \brief Abort a verify hash operation. + * + * \warning This is a beta API, and thus subject to change at + * any point. It is not bound by the usual interface + * stability promises. + * + * \note This function is the only function that clears the + * number of ops completed as part of the operation. + * Please ensure you copy this value via + * \c psa_verify_hash_get_num_ops() if required + * before calling. + * + * \note Aborting an operation frees all associated + * resources except for the operation structure + * itself. Once aborted, the operation object can be + * reused for another operation by calling \c + * psa_verify_hash_start() again. + * + * \note You may call this function any time after the + * operation object has been initialized. + * In particular, calling \c psa_verify_hash_abort() + * after the operation has already been terminated by + * a call to \c psa_verify_hash_abort() or + * psa_verify_hash_complete() is safe. + * + * \param[in,out] operation Initialized verify hash operation. + * + * \retval #PSA_SUCCESS + * The operation was aborted successfully. + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_verify_hash_abort( + psa_verify_hash_interruptible_operation_t *operation); + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +/* The file "crypto_sizes.h" contains definitions for size calculation + * macros whose definitions are implementation-specific. */ +#include "crypto_sizes.h" + +/* The file "crypto_struct.h" contains definitions for + * implementation-specific structs that are declared above. */ +#if defined(MBEDTLS_PSA_CRYPTO_STRUCT_FILE) +#include MBEDTLS_PSA_CRYPTO_STRUCT_FILE +#else +#include "crypto_struct.h" +#endif + +/* The file "crypto_extra.h" contains vendor-specific definitions. This + * can include vendor-defined algorithms, extra functions, etc. */ +#include "crypto_extra.h" + +#endif /* PSA_CRYPTO_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_auto_enabled.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_auto_enabled.h index 5e18298..b1f9d9f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_auto_enabled.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_auto_enabled.h @@ -1,33 +1,33 @@ -/** - * \file psa/crypto_adjust_auto_enabled.h - * \brief Adjust PSA configuration: enable always-on features - * - * Always enable certain features which require a negligible amount of code - * to implement, to avoid some edge cases in the configuration combinatorics. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_ADJUST_AUTO_ENABLED_H -#define PSA_CRYPTO_ADJUST_AUTO_ENABLED_H - -#define PSA_WANT_KEY_TYPE_DERIVE 1 -#define PSA_WANT_KEY_TYPE_PASSWORD 1 -#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 -#define PSA_WANT_KEY_TYPE_RAW_DATA 1 - -#endif /* PSA_CRYPTO_ADJUST_AUTO_ENABLED_H */ +/** + * \file psa/crypto_adjust_auto_enabled.h + * \brief Adjust PSA configuration: enable always-on features + * + * Always enable certain features which require a negligible amount of code + * to implement, to avoid some edge cases in the configuration combinatorics. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_ADJUST_AUTO_ENABLED_H +#define PSA_CRYPTO_ADJUST_AUTO_ENABLED_H + +#define PSA_WANT_KEY_TYPE_DERIVE 1 +#define PSA_WANT_KEY_TYPE_PASSWORD 1 +#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 +#define PSA_WANT_KEY_TYPE_RAW_DATA 1 + +#endif /* PSA_CRYPTO_ADJUST_AUTO_ENABLED_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_key_pair_types.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_key_pair_types.h index 7736e75..03e46aa 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_key_pair_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_key_pair_types.h @@ -1,103 +1,103 @@ -/** - * \file psa/crypto_adjust_config_key_pair_types.h - * \brief Adjust PSA configuration for key pair types. - * - * See docs/proposed/psa-conditional-inclusion-c.md. - * - Support non-basic operations in a keypair type implicitly enables basic - * support for that keypair type. - * - Support for a keypair type implicitly enables the corresponding public - * key type. - * - Basic support for a keypair type implicilty enables import/export support - * for that keypair type. Warning: this is implementation-specific (mainly - * for the benefit of testing) and may change in the future! - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H -#define PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H - -/***************************************************************** - * ANYTHING -> BASIC - ****************************************************************/ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#endif - -/***************************************************************** - * BASIC -> corresponding PUBLIC - ****************************************************************/ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 -#endif - -/***************************************************************** - * BASIC -> IMPORT+EXPORT - * - * (Implementation-specific, may change in the future.) - ****************************************************************/ - -/* Even though KEY_PAIR symbols' feature several level of support (BASIC, IMPORT, - * EXPORT, GENERATE, DERIVE) we're not planning to have support only for BASIC - * without IMPORT/EXPORT since these last 2 features are strongly used in tests. - * In general it is allowed to include more feature than what is strictly - * requested. - * As a consequence IMPORT and EXPORT features will be automatically enabled - * as soon as the BASIC one is. */ -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#endif - -#endif /* PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H */ +/** + * \file psa/crypto_adjust_config_key_pair_types.h + * \brief Adjust PSA configuration for key pair types. + * + * See docs/proposed/psa-conditional-inclusion-c.md. + * - Support non-basic operations in a keypair type implicitly enables basic + * support for that keypair type. + * - Support for a keypair type implicitly enables the corresponding public + * key type. + * - Basic support for a keypair type implicilty enables import/export support + * for that keypair type. Warning: this is implementation-specific (mainly + * for the benefit of testing) and may change in the future! + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H +#define PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H + +/***************************************************************** + * ANYTHING -> BASIC + ****************************************************************/ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE) +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#endif + +/***************************************************************** + * BASIC -> corresponding PUBLIC + ****************************************************************/ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 +#endif + +/***************************************************************** + * BASIC -> IMPORT+EXPORT + * + * (Implementation-specific, may change in the future.) + ****************************************************************/ + +/* Even though KEY_PAIR symbols' feature several level of support (BASIC, IMPORT, + * EXPORT, GENERATE, DERIVE) we're not planning to have support only for BASIC + * without IMPORT/EXPORT since these last 2 features are strongly used in tests. + * In general it is allowed to include more feature than what is strictly + * requested. + * As a consequence IMPORT and EXPORT features will be automatically enabled + * as soon as the BASIC one is. */ +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#endif + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#endif + +#endif /* PSA_CRYPTO_ADJUST_KEYPAIR_TYPES_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_synonyms.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_synonyms.h index 5142ef0..5f1e5df 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_synonyms.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_adjust_config_synonyms.h @@ -1,57 +1,57 @@ -/** - * \file psa/crypto_adjust_config_synonyms.h - * \brief Adjust PSA configuration: enable quasi-synonyms - * - * When two features require almost the same code, we automatically enable - * both when either one is requested, to reduce the combinatorics of - * possible configurations. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H -#define PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H - -/****************************************************************/ -/* De facto synonyms */ -/****************************************************************/ - -#if defined(PSA_WANT_ALG_ECDSA_ANY) && !defined(PSA_WANT_ALG_ECDSA) -#define PSA_WANT_ALG_ECDSA PSA_WANT_ALG_ECDSA_ANY -#elif !defined(PSA_WANT_ALG_ECDSA_ANY) && defined(PSA_WANT_ALG_ECDSA) -#define PSA_WANT_ALG_ECDSA_ANY PSA_WANT_ALG_ECDSA -#endif - -#if defined(PSA_WANT_ALG_CCM_STAR_NO_TAG) && !defined(PSA_WANT_ALG_CCM) -#define PSA_WANT_ALG_CCM PSA_WANT_ALG_CCM_STAR_NO_TAG -#elif !defined(PSA_WANT_ALG_CCM_STAR_NO_TAG) && defined(PSA_WANT_ALG_CCM) -#define PSA_WANT_ALG_CCM_STAR_NO_TAG PSA_WANT_ALG_CCM -#endif - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW -#elif !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW PSA_WANT_ALG_RSA_PKCS1V15_SIGN -#endif - -#if defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && !defined(PSA_WANT_ALG_RSA_PSS) -#define PSA_WANT_ALG_RSA_PSS PSA_WANT_ALG_RSA_PSS_ANY_SALT -#elif !defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && defined(PSA_WANT_ALG_RSA_PSS) -#define PSA_WANT_ALG_RSA_PSS_ANY_SALT PSA_WANT_ALG_RSA_PSS -#endif - -#endif /* PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H */ +/** + * \file psa/crypto_adjust_config_synonyms.h + * \brief Adjust PSA configuration: enable quasi-synonyms + * + * When two features require almost the same code, we automatically enable + * both when either one is requested, to reduce the combinatorics of + * possible configurations. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H +#define PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H + +/****************************************************************/ +/* De facto synonyms */ +/****************************************************************/ + +#if defined(PSA_WANT_ALG_ECDSA_ANY) && !defined(PSA_WANT_ALG_ECDSA) +#define PSA_WANT_ALG_ECDSA PSA_WANT_ALG_ECDSA_ANY +#elif !defined(PSA_WANT_ALG_ECDSA_ANY) && defined(PSA_WANT_ALG_ECDSA) +#define PSA_WANT_ALG_ECDSA_ANY PSA_WANT_ALG_ECDSA +#endif + +#if defined(PSA_WANT_ALG_CCM_STAR_NO_TAG) && !defined(PSA_WANT_ALG_CCM) +#define PSA_WANT_ALG_CCM PSA_WANT_ALG_CCM_STAR_NO_TAG +#elif !defined(PSA_WANT_ALG_CCM_STAR_NO_TAG) && defined(PSA_WANT_ALG_CCM) +#define PSA_WANT_ALG_CCM_STAR_NO_TAG PSA_WANT_ALG_CCM +#endif + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW +#elif !defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW) && defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN_RAW PSA_WANT_ALG_RSA_PKCS1V15_SIGN +#endif + +#if defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && !defined(PSA_WANT_ALG_RSA_PSS) +#define PSA_WANT_ALG_RSA_PSS PSA_WANT_ALG_RSA_PSS_ANY_SALT +#elif !defined(PSA_WANT_ALG_RSA_PSS_ANY_SALT) && defined(PSA_WANT_ALG_RSA_PSS) +#define PSA_WANT_ALG_RSA_PSS_ANY_SALT PSA_WANT_ALG_RSA_PSS +#endif + +#endif /* PSA_CRYPTO_ADJUST_CONFIG_SYNONYMS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_composites.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_composites.h index d9473ac..a53801a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_composites.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_composites.h @@ -1,222 +1,222 @@ -/* - * Context structure declaration of the Mbed TLS software-based PSA drivers - * called through the PSA Crypto driver dispatch layer. - * This file contains the context structures of those algorithms which need to - * rely on other algorithms, i.e. are 'composite' algorithms. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the Mbed TLS software-based PSA drivers. The - * definitions of these objects are then used by crypto_struct.h to define the - * implementation-defined types of PSA multi-part state objects. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_BUILTIN_COMPOSITES_H -#define PSA_CRYPTO_BUILTIN_COMPOSITES_H -#include "mbedtls/private_access.h" - -#include - -#include "mbedtls/cmac.h" -#include "mbedtls/gcm.h" -#include "mbedtls/ccm.h" -#include "mbedtls/chachapoly.h" - -/* - * MAC multi-part operation definitions. - */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) -#define MBEDTLS_PSA_BUILTIN_MAC -#endif - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || defined(PSA_CRYPTO_DRIVER_TEST) -typedef struct { - /** The HMAC algorithm in use */ - psa_algorithm_t MBEDTLS_PRIVATE(alg); - /** The hash context. */ - struct psa_hash_operation_s hash_ctx; - /** The HMAC part of the context. */ - uint8_t MBEDTLS_PRIVATE(opad)[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; -} mbedtls_psa_hmac_operation_t; - -#define MBEDTLS_PSA_HMAC_OPERATION_INIT { 0, PSA_HASH_OPERATION_INIT, { 0 } } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - -typedef struct { - psa_algorithm_t MBEDTLS_PRIVATE(alg); - union { - unsigned MBEDTLS_PRIVATE(dummy); /* Make the union non-empty even with no supported algorithms. */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_psa_hmac_operation_t MBEDTLS_PRIVATE(hmac); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) || defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_cipher_context_t MBEDTLS_PRIVATE(cmac); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ - } MBEDTLS_PRIVATE(ctx); -} mbedtls_psa_mac_operation_t; - -#define MBEDTLS_PSA_MAC_OPERATION_INIT { 0, { 0 } } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) -#define MBEDTLS_PSA_BUILTIN_AEAD 1 -#endif - -/* Context structure for the Mbed TLS AEAD implementation. */ -typedef struct { - psa_algorithm_t MBEDTLS_PRIVATE(alg); - psa_key_type_t MBEDTLS_PRIVATE(key_type); - - unsigned int MBEDTLS_PRIVATE(is_encrypt) : 1; - - uint8_t MBEDTLS_PRIVATE(tag_length); - - union { - unsigned dummy; /* Enable easier initializing of the union. */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - mbedtls_ccm_context MBEDTLS_PRIVATE(ccm); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - mbedtls_gcm_context MBEDTLS_PRIVATE(gcm); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - mbedtls_chachapoly_context MBEDTLS_PRIVATE(chachapoly); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - - } ctx; - -} mbedtls_psa_aead_operation_t; - -#define MBEDTLS_PSA_AEAD_OPERATION_INIT { 0, 0, 0, 0, { 0 } } - -#include "mbedtls/ecdsa.h" - -/* Context structure for the Mbed TLS interruptible sign hash implementation. */ -typedef struct { -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - mbedtls_ecdsa_context *MBEDTLS_PRIVATE(ctx); - mbedtls_ecdsa_restart_ctx MBEDTLS_PRIVATE(restart_ctx); - - uint32_t MBEDTLS_PRIVATE(num_ops); - - size_t MBEDTLS_PRIVATE(coordinate_bytes); - psa_algorithm_t MBEDTLS_PRIVATE(alg); - mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); - uint8_t MBEDTLS_PRIVATE(hash)[PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS)]; - size_t MBEDTLS_PRIVATE(hash_length); - -#else - /* Make the struct non-empty if algs not supported. */ - unsigned MBEDTLS_PRIVATE(dummy); - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} mbedtls_psa_sign_hash_interruptible_operation_t; - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) -#define MBEDTLS_PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { { 0 }, { 0 }, 0, 0, 0, 0, 0, 0 } -#else -#define MBEDTLS_PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } -#endif - -/* Context structure for the Mbed TLS interruptible verify hash - * implementation.*/ -typedef struct { -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - mbedtls_ecdsa_context *MBEDTLS_PRIVATE(ctx); - mbedtls_ecdsa_restart_ctx MBEDTLS_PRIVATE(restart_ctx); - - uint32_t MBEDTLS_PRIVATE(num_ops); - - uint8_t MBEDTLS_PRIVATE(hash)[PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS)]; - size_t MBEDTLS_PRIVATE(hash_length); - - mbedtls_mpi MBEDTLS_PRIVATE(r); - mbedtls_mpi MBEDTLS_PRIVATE(s); - -#else - /* Make the struct non-empty if algs not supported. */ - unsigned MBEDTLS_PRIVATE(dummy); - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ - -} mbedtls_psa_verify_hash_interruptible_operation_t; - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) -#define MBEDTLS_VERIFY_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { { 0 }, { 0 }, 0, 0, 0, 0, { 0 }, \ - { 0 } } -#else -#define MBEDTLS_VERIFY_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } -#endif - - -/* EC-JPAKE operation definitions */ - -#include "mbedtls/ecjpake.h" - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) -#define MBEDTLS_PSA_BUILTIN_PAKE 1 -#endif - -/* Note: the format for mbedtls_ecjpake_read/write function has an extra - * length byte for each step, plus an extra 3 bytes for ECParameters in the - * server's 2nd round. */ -#define MBEDTLS_PSA_JPAKE_BUFFER_SIZE ((3 + 1 + 65 + 1 + 65 + 1 + 32) * 2) - -typedef struct { - psa_algorithm_t MBEDTLS_PRIVATE(alg); - - uint8_t *MBEDTLS_PRIVATE(password); - size_t MBEDTLS_PRIVATE(password_len); -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - mbedtls_ecjpake_role MBEDTLS_PRIVATE(role); - uint8_t MBEDTLS_PRIVATE(buffer[MBEDTLS_PSA_JPAKE_BUFFER_SIZE]); - size_t MBEDTLS_PRIVATE(buffer_length); - size_t MBEDTLS_PRIVATE(buffer_offset); -#endif - /* Context structure for the Mbed TLS EC-JPAKE implementation. */ - union { - unsigned int MBEDTLS_PRIVATE(dummy); -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - mbedtls_ecjpake_context MBEDTLS_PRIVATE(jpake); -#endif - } MBEDTLS_PRIVATE(ctx); - -} mbedtls_psa_pake_operation_t; - -#define MBEDTLS_PSA_PAKE_OPERATION_INIT { { 0 } } - -#endif /* PSA_CRYPTO_BUILTIN_COMPOSITES_H */ +/* + * Context structure declaration of the Mbed TLS software-based PSA drivers + * called through the PSA Crypto driver dispatch layer. + * This file contains the context structures of those algorithms which need to + * rely on other algorithms, i.e. are 'composite' algorithms. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the Mbed TLS software-based PSA drivers. The + * definitions of these objects are then used by crypto_struct.h to define the + * implementation-defined types of PSA multi-part state objects. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_BUILTIN_COMPOSITES_H +#define PSA_CRYPTO_BUILTIN_COMPOSITES_H +#include "mbedtls/private_access.h" + +#include + +#include "mbedtls/cmac.h" +#include "mbedtls/gcm.h" +#include "mbedtls/ccm.h" +#include "mbedtls/chachapoly.h" + +/* + * MAC multi-part operation definitions. + */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) +#define MBEDTLS_PSA_BUILTIN_MAC +#endif + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || defined(PSA_CRYPTO_DRIVER_TEST) +typedef struct { + /** The HMAC algorithm in use */ + psa_algorithm_t MBEDTLS_PRIVATE(alg); + /** The hash context. */ + struct psa_hash_operation_s hash_ctx; + /** The HMAC part of the context. */ + uint8_t MBEDTLS_PRIVATE(opad)[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; +} mbedtls_psa_hmac_operation_t; + +#define MBEDTLS_PSA_HMAC_OPERATION_INIT { 0, PSA_HASH_OPERATION_INIT, { 0 } } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + +typedef struct { + psa_algorithm_t MBEDTLS_PRIVATE(alg); + union { + unsigned MBEDTLS_PRIVATE(dummy); /* Make the union non-empty even with no supported algorithms. */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_psa_hmac_operation_t MBEDTLS_PRIVATE(hmac); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) || defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cmac); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ + } MBEDTLS_PRIVATE(ctx); +} mbedtls_psa_mac_operation_t; + +#define MBEDTLS_PSA_MAC_OPERATION_INIT { 0, { 0 } } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) +#define MBEDTLS_PSA_BUILTIN_AEAD 1 +#endif + +/* Context structure for the Mbed TLS AEAD implementation. */ +typedef struct { + psa_algorithm_t MBEDTLS_PRIVATE(alg); + psa_key_type_t MBEDTLS_PRIVATE(key_type); + + unsigned int MBEDTLS_PRIVATE(is_encrypt) : 1; + + uint8_t MBEDTLS_PRIVATE(tag_length); + + union { + unsigned dummy; /* Enable easier initializing of the union. */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + mbedtls_ccm_context MBEDTLS_PRIVATE(ccm); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + mbedtls_gcm_context MBEDTLS_PRIVATE(gcm); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + mbedtls_chachapoly_context MBEDTLS_PRIVATE(chachapoly); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + + } ctx; + +} mbedtls_psa_aead_operation_t; + +#define MBEDTLS_PSA_AEAD_OPERATION_INIT { 0, 0, 0, 0, { 0 } } + +#include "mbedtls/ecdsa.h" + +/* Context structure for the Mbed TLS interruptible sign hash implementation. */ +typedef struct { +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + mbedtls_ecdsa_context *MBEDTLS_PRIVATE(ctx); + mbedtls_ecdsa_restart_ctx MBEDTLS_PRIVATE(restart_ctx); + + uint32_t MBEDTLS_PRIVATE(num_ops); + + size_t MBEDTLS_PRIVATE(coordinate_bytes); + psa_algorithm_t MBEDTLS_PRIVATE(alg); + mbedtls_md_type_t MBEDTLS_PRIVATE(md_alg); + uint8_t MBEDTLS_PRIVATE(hash)[PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS)]; + size_t MBEDTLS_PRIVATE(hash_length); + +#else + /* Make the struct non-empty if algs not supported. */ + unsigned MBEDTLS_PRIVATE(dummy); + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} mbedtls_psa_sign_hash_interruptible_operation_t; + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) +#define MBEDTLS_PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { { 0 }, { 0 }, 0, 0, 0, 0, 0, 0 } +#else +#define MBEDTLS_PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } +#endif + +/* Context structure for the Mbed TLS interruptible verify hash + * implementation.*/ +typedef struct { +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + mbedtls_ecdsa_context *MBEDTLS_PRIVATE(ctx); + mbedtls_ecdsa_restart_ctx MBEDTLS_PRIVATE(restart_ctx); + + uint32_t MBEDTLS_PRIVATE(num_ops); + + uint8_t MBEDTLS_PRIVATE(hash)[PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS)]; + size_t MBEDTLS_PRIVATE(hash_length); + + mbedtls_mpi MBEDTLS_PRIVATE(r); + mbedtls_mpi MBEDTLS_PRIVATE(s); + +#else + /* Make the struct non-empty if algs not supported. */ + unsigned MBEDTLS_PRIVATE(dummy); + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ + +} mbedtls_psa_verify_hash_interruptible_operation_t; + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) +#define MBEDTLS_VERIFY_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { { 0 }, { 0 }, 0, 0, 0, 0, { 0 }, \ + { 0 } } +#else +#define MBEDTLS_VERIFY_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0 } +#endif + + +/* EC-JPAKE operation definitions */ + +#include "mbedtls/ecjpake.h" + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) +#define MBEDTLS_PSA_BUILTIN_PAKE 1 +#endif + +/* Note: the format for mbedtls_ecjpake_read/write function has an extra + * length byte for each step, plus an extra 3 bytes for ECParameters in the + * server's 2nd round. */ +#define MBEDTLS_PSA_JPAKE_BUFFER_SIZE ((3 + 1 + 65 + 1 + 65 + 1 + 32) * 2) + +typedef struct { + psa_algorithm_t MBEDTLS_PRIVATE(alg); + + uint8_t *MBEDTLS_PRIVATE(password); + size_t MBEDTLS_PRIVATE(password_len); +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + mbedtls_ecjpake_role MBEDTLS_PRIVATE(role); + uint8_t MBEDTLS_PRIVATE(buffer[MBEDTLS_PSA_JPAKE_BUFFER_SIZE]); + size_t MBEDTLS_PRIVATE(buffer_length); + size_t MBEDTLS_PRIVATE(buffer_offset); +#endif + /* Context structure for the Mbed TLS EC-JPAKE implementation. */ + union { + unsigned int MBEDTLS_PRIVATE(dummy); +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + mbedtls_ecjpake_context MBEDTLS_PRIVATE(jpake); +#endif + } MBEDTLS_PRIVATE(ctx); + +} mbedtls_psa_pake_operation_t; + +#define MBEDTLS_PSA_PAKE_OPERATION_INIT { { 0 } } + +#endif /* PSA_CRYPTO_BUILTIN_COMPOSITES_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_key_derivation.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_key_derivation.h index 8a2143a..f150f9d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_key_derivation.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_key_derivation.h @@ -1,130 +1,130 @@ -/* - * Context structure declaration of the Mbed TLS software-based PSA drivers - * called through the PSA Crypto driver dispatch layer. - * This file contains the context structures of key derivation algorithms - * which need to rely on other algorithms. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the Mbed TLS software-based PSA drivers. The - * definitions of these objects are then used by crypto_struct.h to define the - * implementation-defined types of PSA multi-part state objects. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H -#define PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H -#include "mbedtls/private_access.h" - -#include - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) -typedef struct { - uint8_t *MBEDTLS_PRIVATE(info); - size_t MBEDTLS_PRIVATE(info_length); -#if PSA_HASH_MAX_SIZE > 0xff -#error "PSA_HASH_MAX_SIZE does not fit in uint8_t" -#endif - uint8_t MBEDTLS_PRIVATE(offset_in_block); - uint8_t MBEDTLS_PRIVATE(block_number); - unsigned int MBEDTLS_PRIVATE(state) : 2; - unsigned int MBEDTLS_PRIVATE(info_set) : 1; - uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; - uint8_t MBEDTLS_PRIVATE(prk)[PSA_HASH_MAX_SIZE]; - struct psa_mac_operation_s MBEDTLS_PRIVATE(hmac); -} psa_hkdf_key_derivation_t; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF || - MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT || - MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) -typedef struct { - uint8_t MBEDTLS_PRIVATE(data)[PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE]; -} psa_tls12_ecjpake_to_pms_t; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) -typedef enum { - PSA_TLS12_PRF_STATE_INIT, /* no input provided */ - PSA_TLS12_PRF_STATE_SEED_SET, /* seed has been set */ - PSA_TLS12_PRF_STATE_OTHER_KEY_SET, /* other key has been set - optional */ - PSA_TLS12_PRF_STATE_KEY_SET, /* key has been set */ - PSA_TLS12_PRF_STATE_LABEL_SET, /* label has been set */ - PSA_TLS12_PRF_STATE_OUTPUT /* output has been started */ -} psa_tls12_prf_key_derivation_state_t; - -typedef struct psa_tls12_prf_key_derivation_s { -#if PSA_HASH_MAX_SIZE > 0xff -#error "PSA_HASH_MAX_SIZE does not fit in uint8_t" -#endif - - /* Indicates how many bytes in the current HMAC block have - * not yet been read by the user. */ - uint8_t MBEDTLS_PRIVATE(left_in_block); - - /* The 1-based number of the block. */ - uint8_t MBEDTLS_PRIVATE(block_number); - - psa_tls12_prf_key_derivation_state_t MBEDTLS_PRIVATE(state); - - uint8_t *MBEDTLS_PRIVATE(secret); - size_t MBEDTLS_PRIVATE(secret_length); - uint8_t *MBEDTLS_PRIVATE(seed); - size_t MBEDTLS_PRIVATE(seed_length); - uint8_t *MBEDTLS_PRIVATE(label); - size_t MBEDTLS_PRIVATE(label_length); -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - uint8_t *MBEDTLS_PRIVATE(other_secret); - size_t MBEDTLS_PRIVATE(other_secret_length); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ - - uint8_t MBEDTLS_PRIVATE(Ai)[PSA_HASH_MAX_SIZE]; - - /* `HMAC_hash( prk, A( i ) + seed )` in the notation of RFC 5246, Sect. 5. */ - uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; -} psa_tls12_prf_key_derivation_t; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || - * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ -#if defined(PSA_HAVE_SOFT_PBKDF2) -typedef enum { - PSA_PBKDF2_STATE_INIT, /* no input provided */ - PSA_PBKDF2_STATE_INPUT_COST_SET, /* input cost has been set */ - PSA_PBKDF2_STATE_SALT_SET, /* salt has been set */ - PSA_PBKDF2_STATE_PASSWORD_SET, /* password has been set */ - PSA_PBKDF2_STATE_OUTPUT /* output has been started */ -} psa_pbkdf2_key_derivation_state_t; - -typedef struct { - psa_pbkdf2_key_derivation_state_t MBEDTLS_PRIVATE(state); - uint64_t MBEDTLS_PRIVATE(input_cost); - uint8_t *MBEDTLS_PRIVATE(salt); - size_t MBEDTLS_PRIVATE(salt_length); - uint8_t MBEDTLS_PRIVATE(password)[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; - size_t MBEDTLS_PRIVATE(password_length); - uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; - uint8_t MBEDTLS_PRIVATE(bytes_used); - uint32_t MBEDTLS_PRIVATE(block_number); -} psa_pbkdf2_key_derivation_t; -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - -#endif /* PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H */ +/* + * Context structure declaration of the Mbed TLS software-based PSA drivers + * called through the PSA Crypto driver dispatch layer. + * This file contains the context structures of key derivation algorithms + * which need to rely on other algorithms. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the Mbed TLS software-based PSA drivers. The + * definitions of these objects are then used by crypto_struct.h to define the + * implementation-defined types of PSA multi-part state objects. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H +#define PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H +#include "mbedtls/private_access.h" + +#include + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) +typedef struct { + uint8_t *MBEDTLS_PRIVATE(info); + size_t MBEDTLS_PRIVATE(info_length); +#if PSA_HASH_MAX_SIZE > 0xff +#error "PSA_HASH_MAX_SIZE does not fit in uint8_t" +#endif + uint8_t MBEDTLS_PRIVATE(offset_in_block); + uint8_t MBEDTLS_PRIVATE(block_number); + unsigned int MBEDTLS_PRIVATE(state) : 2; + unsigned int MBEDTLS_PRIVATE(info_set) : 1; + uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; + uint8_t MBEDTLS_PRIVATE(prk)[PSA_HASH_MAX_SIZE]; + struct psa_mac_operation_s MBEDTLS_PRIVATE(hmac); +} psa_hkdf_key_derivation_t; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF || + MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT || + MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) +typedef struct { + uint8_t MBEDTLS_PRIVATE(data)[PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE]; +} psa_tls12_ecjpake_to_pms_t; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +typedef enum { + PSA_TLS12_PRF_STATE_INIT, /* no input provided */ + PSA_TLS12_PRF_STATE_SEED_SET, /* seed has been set */ + PSA_TLS12_PRF_STATE_OTHER_KEY_SET, /* other key has been set - optional */ + PSA_TLS12_PRF_STATE_KEY_SET, /* key has been set */ + PSA_TLS12_PRF_STATE_LABEL_SET, /* label has been set */ + PSA_TLS12_PRF_STATE_OUTPUT /* output has been started */ +} psa_tls12_prf_key_derivation_state_t; + +typedef struct psa_tls12_prf_key_derivation_s { +#if PSA_HASH_MAX_SIZE > 0xff +#error "PSA_HASH_MAX_SIZE does not fit in uint8_t" +#endif + + /* Indicates how many bytes in the current HMAC block have + * not yet been read by the user. */ + uint8_t MBEDTLS_PRIVATE(left_in_block); + + /* The 1-based number of the block. */ + uint8_t MBEDTLS_PRIVATE(block_number); + + psa_tls12_prf_key_derivation_state_t MBEDTLS_PRIVATE(state); + + uint8_t *MBEDTLS_PRIVATE(secret); + size_t MBEDTLS_PRIVATE(secret_length); + uint8_t *MBEDTLS_PRIVATE(seed); + size_t MBEDTLS_PRIVATE(seed_length); + uint8_t *MBEDTLS_PRIVATE(label); + size_t MBEDTLS_PRIVATE(label_length); +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + uint8_t *MBEDTLS_PRIVATE(other_secret); + size_t MBEDTLS_PRIVATE(other_secret_length); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + + uint8_t MBEDTLS_PRIVATE(Ai)[PSA_HASH_MAX_SIZE]; + + /* `HMAC_hash( prk, A( i ) + seed )` in the notation of RFC 5246, Sect. 5. */ + uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; +} psa_tls12_prf_key_derivation_t; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ +#if defined(PSA_HAVE_SOFT_PBKDF2) +typedef enum { + PSA_PBKDF2_STATE_INIT, /* no input provided */ + PSA_PBKDF2_STATE_INPUT_COST_SET, /* input cost has been set */ + PSA_PBKDF2_STATE_SALT_SET, /* salt has been set */ + PSA_PBKDF2_STATE_PASSWORD_SET, /* password has been set */ + PSA_PBKDF2_STATE_OUTPUT /* output has been started */ +} psa_pbkdf2_key_derivation_state_t; + +typedef struct { + psa_pbkdf2_key_derivation_state_t MBEDTLS_PRIVATE(state); + uint64_t MBEDTLS_PRIVATE(input_cost); + uint8_t *MBEDTLS_PRIVATE(salt); + size_t MBEDTLS_PRIVATE(salt_length); + uint8_t MBEDTLS_PRIVATE(password)[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; + size_t MBEDTLS_PRIVATE(password_length); + uint8_t MBEDTLS_PRIVATE(output_block)[PSA_HASH_MAX_SIZE]; + uint8_t MBEDTLS_PRIVATE(bytes_used); + uint32_t MBEDTLS_PRIVATE(block_number); +} psa_pbkdf2_key_derivation_t; +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + +#endif /* PSA_CRYPTO_BUILTIN_KEY_DERIVATION_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_primitives.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_primitives.h index d3e0692..ea42ea7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_primitives.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_builtin_primitives.h @@ -1,126 +1,126 @@ -/* - * Context structure declaration of the Mbed TLS software-based PSA drivers - * called through the PSA Crypto driver dispatch layer. - * This file contains the context structures of those algorithms which do not - * rely on other algorithms, i.e. are 'primitive' algorithms. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the Mbed TLS software-based PSA drivers. The - * definitions of these objects are then used by crypto_struct.h to define the - * implementation-defined types of PSA multi-part state objects. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_BUILTIN_PRIMITIVES_H -#define PSA_CRYPTO_BUILTIN_PRIMITIVES_H -#include "mbedtls/private_access.h" - -#include - -/* - * Hash multi-part operation definitions. - */ - -#include "mbedtls/md5.h" -#include "mbedtls/ripemd160.h" -#include "mbedtls/sha1.h" -#include "mbedtls/sha256.h" -#include "mbedtls/sha512.h" -#include "mbedtls/sha3.h" - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) -#define MBEDTLS_PSA_BUILTIN_HASH -#endif - -typedef struct { - psa_algorithm_t MBEDTLS_PRIVATE(alg); - union { - unsigned dummy; /* Make the union non-empty even with no supported algorithms. */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - mbedtls_md5_context md5; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - mbedtls_ripemd160_context ripemd160; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - mbedtls_sha1_context sha1; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - mbedtls_sha256_context sha256; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - mbedtls_sha512_context sha512; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - mbedtls_sha3_context sha3; -#endif - } MBEDTLS_PRIVATE(ctx); -} mbedtls_psa_hash_operation_t; - -#define MBEDTLS_PSA_HASH_OPERATION_INIT { 0, { 0 } } - -/* - * Cipher multi-part operation definitions. - */ - -#include "mbedtls/cipher.h" - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CTR) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CFB) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_OFB) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG) -#define MBEDTLS_PSA_BUILTIN_CIPHER 1 -#endif - -typedef struct { - /* Context structure for the Mbed TLS cipher implementation. */ - psa_algorithm_t MBEDTLS_PRIVATE(alg); - uint8_t MBEDTLS_PRIVATE(iv_length); - uint8_t MBEDTLS_PRIVATE(block_length); - union { - unsigned int MBEDTLS_PRIVATE(dummy); - mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher); - } MBEDTLS_PRIVATE(ctx); -} mbedtls_psa_cipher_operation_t; - -#define MBEDTLS_PSA_CIPHER_OPERATION_INIT { 0, 0, 0, { 0 } } - -#endif /* PSA_CRYPTO_BUILTIN_PRIMITIVES_H */ +/* + * Context structure declaration of the Mbed TLS software-based PSA drivers + * called through the PSA Crypto driver dispatch layer. + * This file contains the context structures of those algorithms which do not + * rely on other algorithms, i.e. are 'primitive' algorithms. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the Mbed TLS software-based PSA drivers. The + * definitions of these objects are then used by crypto_struct.h to define the + * implementation-defined types of PSA multi-part state objects. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_BUILTIN_PRIMITIVES_H +#define PSA_CRYPTO_BUILTIN_PRIMITIVES_H +#include "mbedtls/private_access.h" + +#include + +/* + * Hash multi-part operation definitions. + */ + +#include "mbedtls/md5.h" +#include "mbedtls/ripemd160.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" +#include "mbedtls/sha3.h" + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) +#define MBEDTLS_PSA_BUILTIN_HASH +#endif + +typedef struct { + psa_algorithm_t MBEDTLS_PRIVATE(alg); + union { + unsigned dummy; /* Make the union non-empty even with no supported algorithms. */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + mbedtls_md5_context md5; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + mbedtls_ripemd160_context ripemd160; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + mbedtls_sha1_context sha1; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + mbedtls_sha256_context sha256; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + mbedtls_sha512_context sha512; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + mbedtls_sha3_context sha3; +#endif + } MBEDTLS_PRIVATE(ctx); +} mbedtls_psa_hash_operation_t; + +#define MBEDTLS_PSA_HASH_OPERATION_INIT { 0, { 0 } } + +/* + * Cipher multi-part operation definitions. + */ + +#include "mbedtls/cipher.h" + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CTR) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CFB) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_OFB) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG) +#define MBEDTLS_PSA_BUILTIN_CIPHER 1 +#endif + +typedef struct { + /* Context structure for the Mbed TLS cipher implementation. */ + psa_algorithm_t MBEDTLS_PRIVATE(alg); + uint8_t MBEDTLS_PRIVATE(iv_length); + uint8_t MBEDTLS_PRIVATE(block_length); + union { + unsigned int MBEDTLS_PRIVATE(dummy); + mbedtls_cipher_context_t MBEDTLS_PRIVATE(cipher); + } MBEDTLS_PRIVATE(ctx); +} mbedtls_psa_cipher_operation_t; + +#define MBEDTLS_PSA_CIPHER_OPERATION_INIT { 0, 0, 0, { 0 } } + +#endif /* PSA_CRYPTO_BUILTIN_PRIMITIVES_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_compat.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_compat.h index 64ca4d0..ea0a399 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_compat.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_compat.h @@ -1,174 +1,174 @@ -/** - * \file psa/crypto_compat.h - * - * \brief PSA cryptography module: Backward compatibility aliases - * - * This header declares alternative names for macro and functions. - * New application code should not use these names. - * These names may be removed in a future version of Mbed TLS. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_compat.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_compat.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_COMPAT_H -#define PSA_CRYPTO_COMPAT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * To support both openless APIs and psa_open_key() temporarily, define - * psa_key_handle_t to be equal to mbedtls_svc_key_id_t. Do not mark the - * type and its utility macros and functions deprecated yet. This will be done - * in a subsequent phase. - */ -typedef mbedtls_svc_key_id_t psa_key_handle_t; - -#define PSA_KEY_HANDLE_INIT MBEDTLS_SVC_KEY_ID_INIT - -/** Check whether a handle is null. - * - * \param handle Handle - * - * \return Non-zero if the handle is null, zero otherwise. - */ -static inline int psa_key_handle_is_null(psa_key_handle_t handle) -{ - return mbedtls_svc_key_id_is_null(handle); -} - -/** Open a handle to an existing persistent key. - * - * Open a handle to a persistent key. A key is persistent if it was created - * with a lifetime other than #PSA_KEY_LIFETIME_VOLATILE. A persistent key - * always has a nonzero key identifier, set with psa_set_key_id() when - * creating the key. Implementations may provide additional pre-provisioned - * keys that can be opened with psa_open_key(). Such keys have an application - * key identifier in the vendor range, as documented in the description of - * #psa_key_id_t. - * - * The application must eventually close the handle with psa_close_key() or - * psa_destroy_key() to release associated resources. If the application dies - * without calling one of these functions, the implementation should perform - * the equivalent of a call to psa_close_key(). - * - * Some implementations permit an application to open the same key multiple - * times. If this is successful, each call to psa_open_key() will return a - * different key handle. - * - * \note This API is not part of the PSA Cryptography API Release 1.0.0 - * specification. It was defined in the 1.0 Beta 3 version of the - * specification but was removed in the 1.0.0 released version. This API is - * kept for the time being to not break applications relying on it. It is not - * deprecated yet but will be in the near future. - * - * \note Applications that rely on opening a key multiple times will not be - * portable to implementations that only permit a single key handle to be - * opened. See also :ref:\`key-handles\`. - * - * - * \param key The persistent identifier of the key. - * \param[out] handle On success, a handle to the key. - * - * \retval #PSA_SUCCESS - * Success. The application can now use the value of `*handle` - * to access the key. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * The implementation does not have sufficient resources to open the - * key. This can be due to reaching an implementation limit on the - * number of open keys, the number of open key handles, or available - * memory. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no persistent key with key identifier \p key. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key is not a valid persistent key identifier. - * \retval #PSA_ERROR_NOT_PERMITTED - * The specified key exists, but the application does not have the - * permission to access it. Note that this specification does not - * define any way to create such a key, but it may be possible - * through implementation-specific means. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_open_key(mbedtls_svc_key_id_t key, - psa_key_handle_t *handle); - -/** Close a key handle. - * - * If the handle designates a volatile key, this will destroy the key material - * and free all associated resources, just like psa_destroy_key(). - * - * If this is the last open handle to a persistent key, then closing the handle - * will free all resources associated with the key in volatile memory. The key - * data in persistent storage is not affected and can be opened again later - * with a call to psa_open_key(). - * - * Closing the key handle makes the handle invalid, and the key handle - * must not be used again by the application. - * - * \note This API is not part of the PSA Cryptography API Release 1.0.0 - * specification. It was defined in the 1.0 Beta 3 version of the - * specification but was removed in the 1.0.0 released version. This API is - * kept for the time being to not break applications relying on it. It is not - * deprecated yet but will be in the near future. - * - * \note If the key handle was used to set up an active - * :ref:\`multipart operation \`, then closing the - * key handle can cause the multipart operation to fail. Applications should - * maintain the key handle until after the multipart operation has finished. - * - * \param handle The key handle to close. - * If this is \c 0, do nothing and return \c PSA_SUCCESS. - * - * \retval #PSA_SUCCESS - * \p handle was a valid handle or \c 0. It is now closed. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p handle is not a valid handle nor \c 0. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_close_key(psa_key_handle_t handle); - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_COMPAT_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_compat.h + * + * \brief PSA cryptography module: Backward compatibility aliases + * + * This header declares alternative names for macro and functions. + * New application code should not use these names. + * These names may be removed in a future version of Mbed TLS. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_compat.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_compat.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_COMPAT_H +#define PSA_CRYPTO_COMPAT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * To support both openless APIs and psa_open_key() temporarily, define + * psa_key_handle_t to be equal to mbedtls_svc_key_id_t. Do not mark the + * type and its utility macros and functions deprecated yet. This will be done + * in a subsequent phase. + */ +typedef mbedtls_svc_key_id_t psa_key_handle_t; + +#define PSA_KEY_HANDLE_INIT MBEDTLS_SVC_KEY_ID_INIT + +/** Check whether a handle is null. + * + * \param handle Handle + * + * \return Non-zero if the handle is null, zero otherwise. + */ +static inline int psa_key_handle_is_null(psa_key_handle_t handle) +{ + return mbedtls_svc_key_id_is_null(handle); +} + +/** Open a handle to an existing persistent key. + * + * Open a handle to a persistent key. A key is persistent if it was created + * with a lifetime other than #PSA_KEY_LIFETIME_VOLATILE. A persistent key + * always has a nonzero key identifier, set with psa_set_key_id() when + * creating the key. Implementations may provide additional pre-provisioned + * keys that can be opened with psa_open_key(). Such keys have an application + * key identifier in the vendor range, as documented in the description of + * #psa_key_id_t. + * + * The application must eventually close the handle with psa_close_key() or + * psa_destroy_key() to release associated resources. If the application dies + * without calling one of these functions, the implementation should perform + * the equivalent of a call to psa_close_key(). + * + * Some implementations permit an application to open the same key multiple + * times. If this is successful, each call to psa_open_key() will return a + * different key handle. + * + * \note This API is not part of the PSA Cryptography API Release 1.0.0 + * specification. It was defined in the 1.0 Beta 3 version of the + * specification but was removed in the 1.0.0 released version. This API is + * kept for the time being to not break applications relying on it. It is not + * deprecated yet but will be in the near future. + * + * \note Applications that rely on opening a key multiple times will not be + * portable to implementations that only permit a single key handle to be + * opened. See also :ref:\`key-handles\`. + * + * + * \param key The persistent identifier of the key. + * \param[out] handle On success, a handle to the key. + * + * \retval #PSA_SUCCESS + * Success. The application can now use the value of `*handle` + * to access the key. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * The implementation does not have sufficient resources to open the + * key. This can be due to reaching an implementation limit on the + * number of open keys, the number of open key handles, or available + * memory. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no persistent key with key identifier \p key. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key is not a valid persistent key identifier. + * \retval #PSA_ERROR_NOT_PERMITTED + * The specified key exists, but the application does not have the + * permission to access it. Note that this specification does not + * define any way to create such a key, but it may be possible + * through implementation-specific means. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_open_key(mbedtls_svc_key_id_t key, + psa_key_handle_t *handle); + +/** Close a key handle. + * + * If the handle designates a volatile key, this will destroy the key material + * and free all associated resources, just like psa_destroy_key(). + * + * If this is the last open handle to a persistent key, then closing the handle + * will free all resources associated with the key in volatile memory. The key + * data in persistent storage is not affected and can be opened again later + * with a call to psa_open_key(). + * + * Closing the key handle makes the handle invalid, and the key handle + * must not be used again by the application. + * + * \note This API is not part of the PSA Cryptography API Release 1.0.0 + * specification. It was defined in the 1.0 Beta 3 version of the + * specification but was removed in the 1.0.0 released version. This API is + * kept for the time being to not break applications relying on it. It is not + * deprecated yet but will be in the near future. + * + * \note If the key handle was used to set up an active + * :ref:\`multipart operation \`, then closing the + * key handle can cause the multipart operation to fail. Applications should + * maintain the key handle until after the multipart operation has finished. + * + * \param handle The key handle to close. + * If this is \c 0, do nothing and return \c PSA_SUCCESS. + * + * \retval #PSA_SUCCESS + * \p handle was a valid handle or \c 0. It is now closed. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p handle is not a valid handle nor \c 0. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_close_key(psa_key_handle_t handle); + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_COMPAT_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_config.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_config.h index d34cbf3..8194dda 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_config.h @@ -1,165 +1,165 @@ -/** - * \file psa/crypto_config.h - * \brief PSA crypto configuration options (set of defines) - * - */ -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) -/** - * When #MBEDTLS_PSA_CRYPTO_CONFIG is enabled in mbedtls_config.h, - * this file determines which cryptographic mechanisms are enabled - * through the PSA Cryptography API (\c psa_xxx() functions). - * - * To enable a cryptographic mechanism, uncomment the definition of - * the corresponding \c PSA_WANT_xxx preprocessor symbol. - * To disable a cryptographic mechanism, comment out the definition of - * the corresponding \c PSA_WANT_xxx preprocessor symbol. - * The names of cryptographic mechanisms correspond to values - * defined in psa/crypto_values.h, with the prefix \c PSA_WANT_ instead - * of \c PSA_. - * - * Note that many cryptographic mechanisms involve two symbols: one for - * the key type (\c PSA_WANT_KEY_TYPE_xxx) and one for the algorithm - * (\c PSA_WANT_ALG_xxx). Mechanisms with additional parameters may involve - * additional symbols. - */ -#else -/** - * When \c MBEDTLS_PSA_CRYPTO_CONFIG is disabled in mbedtls_config.h, - * this file is not used, and cryptographic mechanisms are supported - * through the PSA API if and only if they are supported through the - * mbedtls_xxx API. - */ -#endif -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_CONFIG_H -#define PSA_CRYPTO_CONFIG_H - -/* - * CBC-MAC is not yet supported via the PSA API in Mbed TLS. - */ -//#define PSA_WANT_ALG_CBC_MAC 1 -#define PSA_WANT_ALG_CBC_NO_PADDING 1 -#define PSA_WANT_ALG_CBC_PKCS7 1 -#define PSA_WANT_ALG_CCM 1 -#define PSA_WANT_ALG_CCM_STAR_NO_TAG 1 -#define PSA_WANT_ALG_CMAC 1 -#define PSA_WANT_ALG_CFB 1 -#define PSA_WANT_ALG_CHACHA20_POLY1305 1 -#define PSA_WANT_ALG_CTR 1 -#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 -#define PSA_WANT_ALG_ECB_NO_PADDING 1 -#define PSA_WANT_ALG_ECDH 1 -#define PSA_WANT_ALG_FFDH 1 -#define PSA_WANT_ALG_ECDSA 1 -#define PSA_WANT_ALG_JPAKE 1 -#define PSA_WANT_ALG_GCM 1 -#define PSA_WANT_ALG_HKDF 1 -#define PSA_WANT_ALG_HKDF_EXTRACT 1 -#define PSA_WANT_ALG_HKDF_EXPAND 1 -#define PSA_WANT_ALG_HMAC 1 -#define PSA_WANT_ALG_MD5 1 -#define PSA_WANT_ALG_OFB 1 -#define PSA_WANT_ALG_PBKDF2_HMAC 1 -#define PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128 1 -#define PSA_WANT_ALG_RIPEMD160 1 -#define PSA_WANT_ALG_RSA_OAEP 1 -#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 -#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 -#define PSA_WANT_ALG_RSA_PSS 1 -#define PSA_WANT_ALG_SHA_1 1 -#define PSA_WANT_ALG_SHA_224 1 -#define PSA_WANT_ALG_SHA_256 1 -#define PSA_WANT_ALG_SHA_384 1 -#define PSA_WANT_ALG_SHA_512 1 -#define PSA_WANT_ALG_SHA3_224 1 -#define PSA_WANT_ALG_SHA3_256 1 -#define PSA_WANT_ALG_SHA3_384 1 -#define PSA_WANT_ALG_SHA3_512 1 -#define PSA_WANT_ALG_STREAM_CIPHER 1 -#define PSA_WANT_ALG_TLS12_PRF 1 -#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 -#define PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS 1 - -/* XTS is not yet supported via the PSA API in Mbed TLS. - * Note: when adding support, also adjust include/mbedtls/config_psa.h */ -//#define PSA_WANT_ALG_XTS 1 - -#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 -#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 -#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 -#define PSA_WANT_ECC_MONTGOMERY_255 1 -#define PSA_WANT_ECC_MONTGOMERY_448 1 -#define PSA_WANT_ECC_SECP_K1_192 1 -/* - * SECP224K1 is buggy via the PSA API in Mbed TLS - * (https://github.com/Mbed-TLS/mbedtls/issues/3541). Thus, do not enable it by - * default. - */ -//#define PSA_WANT_ECC_SECP_K1_224 1 -#define PSA_WANT_ECC_SECP_K1_256 1 -#define PSA_WANT_ECC_SECP_R1_192 1 -#define PSA_WANT_ECC_SECP_R1_224 1 -/* For secp256r1, consider enabling #MBEDTLS_PSA_P256M_DRIVER_ENABLED - * (see the description in mbedtls/mbedtls_config.h for details). */ -#define PSA_WANT_ECC_SECP_R1_256 1 -#define PSA_WANT_ECC_SECP_R1_384 1 -#define PSA_WANT_ECC_SECP_R1_521 1 - -#define PSA_WANT_KEY_TYPE_DERIVE 1 -#define PSA_WANT_KEY_TYPE_PASSWORD 1 -#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 -#define PSA_WANT_KEY_TYPE_HMAC 1 -#define PSA_WANT_KEY_TYPE_AES 1 -#define PSA_WANT_KEY_TYPE_ARIA 1 -#define PSA_WANT_KEY_TYPE_CAMELLIA 1 -#define PSA_WANT_KEY_TYPE_CHACHA20 1 -#define PSA_WANT_KEY_TYPE_DES 1 -//#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR 1 /* Deprecated */ -#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 -#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 -#define PSA_WANT_KEY_TYPE_RAW_DATA 1 -//#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR 1 /* Deprecated */ -#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 - -/* - * The following symbols extend and deprecate the legacy - * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR ones. They include the usage of that key in - * the name's suffix. "_USE" is the most generic and it can be used to describe - * a generic suport, whereas other ones add more features on top of that and - * they are more specific. - */ -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 - -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -//#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE 1 /* Not supported */ - -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 -#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 -//#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE 1 /* Not supported */ - -#endif /* PSA_CRYPTO_CONFIG_H */ +/** + * \file psa/crypto_config.h + * \brief PSA crypto configuration options (set of defines) + * + */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +/** + * When #MBEDTLS_PSA_CRYPTO_CONFIG is enabled in mbedtls_config.h, + * this file determines which cryptographic mechanisms are enabled + * through the PSA Cryptography API (\c psa_xxx() functions). + * + * To enable a cryptographic mechanism, uncomment the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * To disable a cryptographic mechanism, comment out the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * The names of cryptographic mechanisms correspond to values + * defined in psa/crypto_values.h, with the prefix \c PSA_WANT_ instead + * of \c PSA_. + * + * Note that many cryptographic mechanisms involve two symbols: one for + * the key type (\c PSA_WANT_KEY_TYPE_xxx) and one for the algorithm + * (\c PSA_WANT_ALG_xxx). Mechanisms with additional parameters may involve + * additional symbols. + */ +#else +/** + * When \c MBEDTLS_PSA_CRYPTO_CONFIG is disabled in mbedtls_config.h, + * this file is not used, and cryptographic mechanisms are supported + * through the PSA API if and only if they are supported through the + * mbedtls_xxx API. + */ +#endif +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +/* + * CBC-MAC is not yet supported via the PSA API in Mbed TLS. + */ +//#define PSA_WANT_ALG_CBC_MAC 1 +#define PSA_WANT_ALG_CBC_NO_PADDING 1 +#define PSA_WANT_ALG_CBC_PKCS7 1 +#define PSA_WANT_ALG_CCM 1 +#define PSA_WANT_ALG_CCM_STAR_NO_TAG 1 +#define PSA_WANT_ALG_CMAC 1 +#define PSA_WANT_ALG_CFB 1 +#define PSA_WANT_ALG_CHACHA20_POLY1305 1 +#define PSA_WANT_ALG_CTR 1 +#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_ECB_NO_PADDING 1 +#define PSA_WANT_ALG_ECDH 1 +#define PSA_WANT_ALG_FFDH 1 +#define PSA_WANT_ALG_ECDSA 1 +#define PSA_WANT_ALG_JPAKE 1 +#define PSA_WANT_ALG_GCM 1 +#define PSA_WANT_ALG_HKDF 1 +#define PSA_WANT_ALG_HKDF_EXTRACT 1 +#define PSA_WANT_ALG_HKDF_EXPAND 1 +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_ALG_MD5 1 +#define PSA_WANT_ALG_OFB 1 +#define PSA_WANT_ALG_PBKDF2_HMAC 1 +#define PSA_WANT_ALG_PBKDF2_AES_CMAC_PRF_128 1 +#define PSA_WANT_ALG_RIPEMD160 1 +#define PSA_WANT_ALG_RSA_OAEP 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PSS 1 +#define PSA_WANT_ALG_SHA_1 1 +#define PSA_WANT_ALG_SHA_224 1 +#define PSA_WANT_ALG_SHA_256 1 +#define PSA_WANT_ALG_SHA_384 1 +#define PSA_WANT_ALG_SHA_512 1 +#define PSA_WANT_ALG_SHA3_224 1 +#define PSA_WANT_ALG_SHA3_256 1 +#define PSA_WANT_ALG_SHA3_384 1 +#define PSA_WANT_ALG_SHA3_512 1 +#define PSA_WANT_ALG_STREAM_CIPHER 1 +#define PSA_WANT_ALG_TLS12_PRF 1 +#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 +#define PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS 1 + +/* XTS is not yet supported via the PSA API in Mbed TLS. + * Note: when adding support, also adjust include/mbedtls/config_psa.h */ +//#define PSA_WANT_ALG_XTS 1 + +#define PSA_WANT_ECC_BRAINPOOL_P_R1_256 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_384 1 +#define PSA_WANT_ECC_BRAINPOOL_P_R1_512 1 +#define PSA_WANT_ECC_MONTGOMERY_255 1 +#define PSA_WANT_ECC_MONTGOMERY_448 1 +#define PSA_WANT_ECC_SECP_K1_192 1 +/* + * SECP224K1 is buggy via the PSA API in Mbed TLS + * (https://github.com/Mbed-TLS/mbedtls/issues/3541). Thus, do not enable it by + * default. + */ +//#define PSA_WANT_ECC_SECP_K1_224 1 +#define PSA_WANT_ECC_SECP_K1_256 1 +#define PSA_WANT_ECC_SECP_R1_192 1 +#define PSA_WANT_ECC_SECP_R1_224 1 +/* For secp256r1, consider enabling #MBEDTLS_PSA_P256M_DRIVER_ENABLED + * (see the description in mbedtls/mbedtls_config.h for details). */ +#define PSA_WANT_ECC_SECP_R1_256 1 +#define PSA_WANT_ECC_SECP_R1_384 1 +#define PSA_WANT_ECC_SECP_R1_521 1 + +#define PSA_WANT_KEY_TYPE_DERIVE 1 +#define PSA_WANT_KEY_TYPE_PASSWORD 1 +#define PSA_WANT_KEY_TYPE_PASSWORD_HASH 1 +#define PSA_WANT_KEY_TYPE_HMAC 1 +#define PSA_WANT_KEY_TYPE_AES 1 +#define PSA_WANT_KEY_TYPE_ARIA 1 +#define PSA_WANT_KEY_TYPE_CAMELLIA 1 +#define PSA_WANT_KEY_TYPE_CHACHA20 1 +#define PSA_WANT_KEY_TYPE_DES 1 +//#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR 1 /* Deprecated */ +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_RAW_DATA 1 +//#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR 1 /* Deprecated */ +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 + +/* + * The following symbols extend and deprecate the legacy + * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR ones. They include the usage of that key in + * the name's suffix. "_USE" is the most generic and it can be used to describe + * a generic suport, whereas other ones add more features on top of that and + * they are more specific. + */ +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 + +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +//#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE 1 /* Not supported */ + +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT 1 +#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE 1 +//#define PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE 1 /* Not supported */ + +#endif /* PSA_CRYPTO_CONFIG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_common.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_common.h index 26363c6..c1323ab 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_common.h @@ -1,56 +1,56 @@ -/** - * \file psa/crypto_driver_common.h - * \brief Definitions for all PSA crypto drivers - * - * This file contains common definitions shared by all PSA crypto drivers. - * Do not include it directly: instead, include the header file(s) for - * the type(s) of driver that you are implementing. For example, if - * you are writing a dynamically registered driver for a secure element, - * include `psa/crypto_se_driver.h`. - * - * This file is part of the PSA Crypto Driver Model, containing functions for - * driver developers to implement to enable hardware to be called in a - * standardized way by a PSA Cryptographic API implementation. The functions - * comprising the driver model, which driver authors implement, are not - * intended to be called by application developers. - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PSA_CRYPTO_DRIVER_COMMON_H -#define PSA_CRYPTO_DRIVER_COMMON_H - -#include -#include - -/* Include type definitions (psa_status_t, psa_algorithm_t, - * psa_key_type_t, etc.) and macros to build and analyze values - * of these types. */ -#include "crypto_types.h" -#include "crypto_values.h" -/* Include size definitions which are used to size some arrays in operation - * structures. */ -#include - -/** For encrypt-decrypt functions, whether the operation is an encryption - * or a decryption. */ -typedef enum { - PSA_CRYPTO_DRIVER_DECRYPT, - PSA_CRYPTO_DRIVER_ENCRYPT -} psa_encrypt_or_decrypt_t; - -#endif /* PSA_CRYPTO_DRIVER_COMMON_H */ +/** + * \file psa/crypto_driver_common.h + * \brief Definitions for all PSA crypto drivers + * + * This file contains common definitions shared by all PSA crypto drivers. + * Do not include it directly: instead, include the header file(s) for + * the type(s) of driver that you are implementing. For example, if + * you are writing a dynamically registered driver for a secure element, + * include `psa/crypto_se_driver.h`. + * + * This file is part of the PSA Crypto Driver Model, containing functions for + * driver developers to implement to enable hardware to be called in a + * standardized way by a PSA Cryptographic API implementation. The functions + * comprising the driver model, which driver authors implement, are not + * intended to be called by application developers. + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PSA_CRYPTO_DRIVER_COMMON_H +#define PSA_CRYPTO_DRIVER_COMMON_H + +#include +#include + +/* Include type definitions (psa_status_t, psa_algorithm_t, + * psa_key_type_t, etc.) and macros to build and analyze values + * of these types. */ +#include "crypto_types.h" +#include "crypto_values.h" +/* Include size definitions which are used to size some arrays in operation + * structures. */ +#include + +/** For encrypt-decrypt functions, whether the operation is an encryption + * or a decryption. */ +typedef enum { + PSA_CRYPTO_DRIVER_DECRYPT, + PSA_CRYPTO_DRIVER_ENCRYPT +} psa_encrypt_or_decrypt_t; + +#endif /* PSA_CRYPTO_DRIVER_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h index d2d9f1f..6a8938a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_composites.h @@ -1,191 +1,191 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for 'composite' - * operations, i.e. those operations which need to make use of other operations - * from the primitives (crypto_driver_contexts_primitives.h) - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_composites.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) -#include -#endif - -#if defined(PSA_CRYPTO_DRIVER_TEST) -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC) -typedef libtestdriver1_mbedtls_psa_mac_operation_t - mbedtls_transparent_test_driver_mac_operation_t; -typedef libtestdriver1_mbedtls_psa_mac_operation_t - mbedtls_opaque_test_driver_mac_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT - -#else -typedef mbedtls_psa_mac_operation_t - mbedtls_transparent_test_driver_mac_operation_t; -typedef mbedtls_psa_mac_operation_t - mbedtls_opaque_test_driver_mac_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ - MBEDTLS_PSA_MAC_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ - MBEDTLS_PSA_MAC_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD) -typedef libtestdriver1_mbedtls_psa_aead_operation_t - mbedtls_transparent_test_driver_aead_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_AEAD_OPERATION_INIT -#else -typedef mbedtls_psa_aead_operation_t - mbedtls_transparent_test_driver_aead_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ - MBEDTLS_PSA_AEAD_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE) - -typedef libtestdriver1_mbedtls_psa_pake_operation_t - mbedtls_transparent_test_driver_pake_operation_t; -typedef libtestdriver1_mbedtls_psa_pake_operation_t - mbedtls_opaque_test_driver_pake_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT - -#else -typedef mbedtls_psa_pake_operation_t - mbedtls_transparent_test_driver_pake_operation_t; -typedef mbedtls_psa_pake_operation_t - mbedtls_opaque_test_driver_pake_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ - MBEDTLS_PSA_PAKE_OPERATION_INIT -#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ - MBEDTLS_PSA_PAKE_OPERATION_INIT - -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ - -/* Define the context to be used for an operation that is executed through the - * PSA Driver wrapper layer as the union of all possible driver's contexts. - * - * The union members are the driver's context structures, and the member names - * are formatted as `'drivername'_ctx`. This allows for procedural generation - * of both this file and the content of psa_crypto_driver_wrappers.h */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_mac_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_mac_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_mac_operation_t opaque_test_driver_ctx; -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - sli_se_transparent_mac_operation_t sli_se_transparent_ctx; -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - sli_se_opaque_mac_operation_t sli_se_opaque_ctx; -#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - sli_cryptoacc_transparent_mac_operation_t sli_cryptoacc_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#if defined(SLI_MBEDTLS_DEVICE_S1) - sli_crypto_transparent_mac_operation_t sli_crypto_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_S1 */ -#endif -} psa_driver_mac_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_aead_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_aead_operation_t transparent_test_driver_ctx; -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - sli_se_transparent_aead_operation_t sli_se_transparent_ctx; -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - sli_se_opaque_aead_operation_t sli_se_opaque_ctx; -#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - sli_cryptoacc_transparent_aead_operation_t sli_cryptoacc_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#if defined(SLI_MBEDTLS_DEVICE_S1) - sli_crypto_transparent_aead_operation_t sli_crypto_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_S1 */ -#endif -} psa_driver_aead_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_sign_hash_interruptible_operation_t mbedtls_ctx; -} psa_driver_sign_hash_interruptible_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_verify_hash_interruptible_operation_t mbedtls_ctx; -} psa_driver_verify_hash_interruptible_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_pake_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_pake_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_pake_operation_t opaque_test_driver_ctx; -#endif -} psa_driver_pake_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H */ -/* End of automatically generated file. */ +/* + * Declaration of context structures for use with the PSA driver wrapper + * interface. This file contains the context structures for 'composite' + * operations, i.e. those operations which need to make use of other operations + * from the primitives (crypto_driver_contexts_primitives.h) + * + * Warning: This file will be auto-generated in the future. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the PSA drivers included in the cryptographic + * library. The definitions of these objects are then used by crypto_struct.h + * to define the implementation-defined types of PSA multi-part state objects. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H +#define PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H + +#include "psa/crypto_driver_common.h" + +/* Include the context structure definitions for the Mbed TLS software drivers */ +#include "psa/crypto_builtin_composites.h" + +/* Include the context structure definitions for those drivers that were + * declared during the autogeneration process. */ + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) +#include +#endif + +#if defined(PSA_CRYPTO_DRIVER_TEST) +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ + defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC) +typedef libtestdriver1_mbedtls_psa_mac_operation_t + mbedtls_transparent_test_driver_mac_operation_t; +typedef libtestdriver1_mbedtls_psa_mac_operation_t + mbedtls_opaque_test_driver_mac_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT +#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_MAC_OPERATION_INIT + +#else +typedef mbedtls_psa_mac_operation_t + mbedtls_transparent_test_driver_mac_operation_t; +typedef mbedtls_psa_mac_operation_t + mbedtls_opaque_test_driver_mac_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_MAC_OPERATION_INIT \ + MBEDTLS_PSA_MAC_OPERATION_INIT +#define MBEDTLS_OPAQUE_TEST_DRIVER_MAC_OPERATION_INIT \ + MBEDTLS_PSA_MAC_OPERATION_INIT + +#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_MAC */ + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ + defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD) +typedef libtestdriver1_mbedtls_psa_aead_operation_t + mbedtls_transparent_test_driver_aead_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_AEAD_OPERATION_INIT +#else +typedef mbedtls_psa_aead_operation_t + mbedtls_transparent_test_driver_aead_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_AEAD_OPERATION_INIT \ + MBEDTLS_PSA_AEAD_OPERATION_INIT + +#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ + defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE) + +typedef libtestdriver1_mbedtls_psa_pake_operation_t + mbedtls_transparent_test_driver_pake_operation_t; +typedef libtestdriver1_mbedtls_psa_pake_operation_t + mbedtls_opaque_test_driver_pake_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT +#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_PAKE_OPERATION_INIT + +#else +typedef mbedtls_psa_pake_operation_t + mbedtls_transparent_test_driver_pake_operation_t; +typedef mbedtls_psa_pake_operation_t + mbedtls_opaque_test_driver_pake_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_PAKE_OPERATION_INIT \ + MBEDTLS_PSA_PAKE_OPERATION_INIT +#define MBEDTLS_OPAQUE_TEST_DRIVER_PAKE_OPERATION_INIT \ + MBEDTLS_PSA_PAKE_OPERATION_INIT + +#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_PAKE */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ + +/* Define the context to be used for an operation that is executed through the + * PSA Driver wrapper layer as the union of all possible driver's contexts. + * + * The union members are the driver's context structures, and the member names + * are formatted as `'drivername'_ctx`. This allows for procedural generation + * of both this file and the content of psa_crypto_driver_wrappers.h */ + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_mac_operation_t mbedtls_ctx; +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_transparent_test_driver_mac_operation_t transparent_test_driver_ctx; + mbedtls_opaque_test_driver_mac_operation_t opaque_test_driver_ctx; +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + sli_se_transparent_mac_operation_t sli_se_transparent_ctx; +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + sli_se_opaque_mac_operation_t sli_se_opaque_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + sli_cryptoacc_transparent_mac_operation_t sli_cryptoacc_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#if defined(SLI_MBEDTLS_DEVICE_S1) + sli_crypto_transparent_mac_operation_t sli_crypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_S1 */ +#endif +} psa_driver_mac_context_t; + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_aead_operation_t mbedtls_ctx; +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_transparent_test_driver_aead_operation_t transparent_test_driver_ctx; +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + sli_se_transparent_aead_operation_t sli_se_transparent_ctx; +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + sli_se_opaque_aead_operation_t sli_se_opaque_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + sli_cryptoacc_transparent_aead_operation_t sli_cryptoacc_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#if defined(SLI_MBEDTLS_DEVICE_S1) + sli_crypto_transparent_aead_operation_t sli_crypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_S1 */ +#endif +} psa_driver_aead_context_t; + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_sign_hash_interruptible_operation_t mbedtls_ctx; +} psa_driver_sign_hash_interruptible_context_t; + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_verify_hash_interruptible_operation_t mbedtls_ctx; +} psa_driver_verify_hash_interruptible_context_t; + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_pake_operation_t mbedtls_ctx; +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_transparent_test_driver_pake_operation_t transparent_test_driver_ctx; + mbedtls_opaque_test_driver_pake_operation_t opaque_test_driver_ctx; +#endif +} psa_driver_pake_context_t; + +#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_COMPOSITES_H */ +/* End of automatically generated file. */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_key_derivation.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_key_derivation.h index 3fb29ff..d775edc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_key_derivation.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_key_derivation.h @@ -1,64 +1,64 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for key derivation - * operations. - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_key_derivation.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - psa_hkdf_key_derivation_t MBEDTLS_PRIVATE(hkdf); -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - psa_tls12_prf_key_derivation_t MBEDTLS_PRIVATE(tls12_prf); -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - psa_tls12_ecjpake_to_pms_t MBEDTLS_PRIVATE(tls12_ecjpake_to_pms); -#endif -#if defined(PSA_HAVE_SOFT_PBKDF2) - psa_pbkdf2_key_derivation_t MBEDTLS_PRIVATE(pbkdf2); -#endif -} psa_driver_key_derivation_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H */ -/* End of automatically generated file. */ +/* + * Declaration of context structures for use with the PSA driver wrapper + * interface. This file contains the context structures for key derivation + * operations. + * + * Warning: This file will be auto-generated in the future. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the PSA drivers included in the cryptographic + * library. The definitions of these objects are then used by crypto_struct.h + * to define the implementation-defined types of PSA multi-part state objects. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H +#define PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H + +#include "psa/crypto_driver_common.h" + +/* Include the context structure definitions for the Mbed TLS software drivers */ +#include "psa/crypto_builtin_key_derivation.h" + +/* Include the context structure definitions for those drivers that were + * declared during the autogeneration process. */ + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) + psa_hkdf_key_derivation_t MBEDTLS_PRIVATE(hkdf); +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + psa_tls12_prf_key_derivation_t MBEDTLS_PRIVATE(tls12_prf); +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + psa_tls12_ecjpake_to_pms_t MBEDTLS_PRIVATE(tls12_ecjpake_to_pms); +#endif +#if defined(PSA_HAVE_SOFT_PBKDF2) + psa_pbkdf2_key_derivation_t MBEDTLS_PRIVATE(pbkdf2); +#endif +} psa_driver_key_derivation_context_t; + +#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_KEY_DERIVATION_H */ +/* End of automatically generated file. */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h index 2db0120..0e3264c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_driver_contexts_primitives.h @@ -1,165 +1,165 @@ -/* - * Declaration of context structures for use with the PSA driver wrapper - * interface. This file contains the context structures for 'primitive' - * operations, i.e. those operations which do not rely on other contexts. - * - * Warning: This file will be auto-generated in the future. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * \note This header and its content are not part of the Mbed TLS API and - * applications must not depend on it. Its main purpose is to define the - * multi-part state objects of the PSA drivers included in the cryptographic - * library. The definitions of these objects are then used by crypto_struct.h - * to define the implementation-defined types of PSA multi-part state objects. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H -#define PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H - -#include "psa/crypto_driver_common.h" - -/* Include the context structure definitions for the Mbed TLS software drivers */ -#include "psa/crypto_builtin_primitives.h" - -/* Include the context structure definitions for those drivers that were - * declared during the autogeneration process. */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) -#include -#endif - -#if defined(PSA_CRYPTO_DRIVER_TEST) - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER) -typedef libtestdriver1_mbedtls_psa_cipher_operation_t - mbedtls_transparent_test_driver_cipher_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_CIPHER_OPERATION_INIT -#else -typedef mbedtls_psa_cipher_operation_t - mbedtls_transparent_test_driver_cipher_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ - MBEDTLS_PSA_CIPHER_OPERATION_INIT -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && - LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ - defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH) -typedef libtestdriver1_mbedtls_psa_hash_operation_t - mbedtls_transparent_test_driver_hash_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ - LIBTESTDRIVER1_MBEDTLS_PSA_HASH_OPERATION_INIT -#else -typedef mbedtls_psa_hash_operation_t - mbedtls_transparent_test_driver_hash_operation_t; - -#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ - MBEDTLS_PSA_HASH_OPERATION_INIT -#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && - LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH */ - -typedef struct { - unsigned int initialised : 1; - mbedtls_transparent_test_driver_cipher_operation_t ctx; -} mbedtls_opaque_test_driver_cipher_operation_t; - -#define MBEDTLS_OPAQUE_TEST_DRIVER_CIPHER_OPERATION_INIT \ - { 0, MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT } - -#endif /* PSA_CRYPTO_DRIVER_TEST */ - -/* Include the context structures for all declared hardware drivers */ -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) - -#include "sli_psa_driver_features.h" - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - #include "sli_se_transparent_types.h" - - #if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - #include "sli_se_opaque_types.h" - #endif -#endif - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - #include "sli_cryptoacc_transparent_types.h" -#endif - -#if defined(SLI_MBEDTLS_DEVICE_S1) - #include "sli_crypto_transparent_types.h" -#endif - -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - -/* Define the context to be used for an operation that is executed through the - * PSA Driver wrapper layer as the union of all possible driver's contexts. - * - * The union members are the driver's context structures, and the member names - * are formatted as `'drivername'_ctx`. This allows for procedural generation - * of both this file and the content of psa_crypto_driver_wrappers.h */ - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_hash_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_hash_operation_t test_driver_ctx; -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - sli_se_transparent_hash_operation_t sli_se_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - sli_cryptoacc_transparent_hash_operation_t sli_cryptoacc_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#if defined(SLI_MBEDTLS_DEVICE_S1) - sli_crypto_transparent_hash_operation_t sli_crypto_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_S1 */ -#endif -} psa_driver_hash_context_t; - -typedef union { - unsigned dummy; /* Make sure this union is always non-empty */ - mbedtls_psa_cipher_operation_t mbedtls_ctx; -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_transparent_test_driver_cipher_operation_t transparent_test_driver_ctx; - mbedtls_opaque_test_driver_cipher_operation_t opaque_test_driver_ctx; -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - sli_se_transparent_cipher_operation_t sli_se_transparent_ctx; -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - sli_se_opaque_cipher_operation_t sli_se_opaque_ctx; -#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - sli_cryptoacc_transparent_cipher_operation_t sli_cryptoacc_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#if defined(SLI_MBEDTLS_DEVICE_S1) - sli_crypto_transparent_cipher_operation_t sli_crypto_transparent_ctx; -#endif /* SLI_MBEDTLS_DEVICE_S1 */ -#endif -} psa_driver_cipher_context_t; - -#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H */ -/* End of automatically generated file. */ +/* + * Declaration of context structures for use with the PSA driver wrapper + * interface. This file contains the context structures for 'primitive' + * operations, i.e. those operations which do not rely on other contexts. + * + * Warning: This file will be auto-generated in the future. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * \note This header and its content are not part of the Mbed TLS API and + * applications must not depend on it. Its main purpose is to define the + * multi-part state objects of the PSA drivers included in the cryptographic + * library. The definitions of these objects are then used by crypto_struct.h + * to define the implementation-defined types of PSA multi-part state objects. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H +#define PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H + +#include "psa/crypto_driver_common.h" + +/* Include the context structure definitions for the Mbed TLS software drivers */ +#include "psa/crypto_builtin_primitives.h" + +/* Include the context structure definitions for those drivers that were + * declared during the autogeneration process. */ + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) +#include +#endif + +#if defined(PSA_CRYPTO_DRIVER_TEST) + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ + defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER) +typedef libtestdriver1_mbedtls_psa_cipher_operation_t + mbedtls_transparent_test_driver_cipher_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_CIPHER_OPERATION_INIT +#else +typedef mbedtls_psa_cipher_operation_t + mbedtls_transparent_test_driver_cipher_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT \ + MBEDTLS_PSA_CIPHER_OPERATION_INIT +#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && + LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_CIPHER */ + +#if defined(MBEDTLS_TEST_LIBTESTDRIVER1) && \ + defined(LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH) +typedef libtestdriver1_mbedtls_psa_hash_operation_t + mbedtls_transparent_test_driver_hash_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ + LIBTESTDRIVER1_MBEDTLS_PSA_HASH_OPERATION_INIT +#else +typedef mbedtls_psa_hash_operation_t + mbedtls_transparent_test_driver_hash_operation_t; + +#define MBEDTLS_TRANSPARENT_TEST_DRIVER_HASH_OPERATION_INIT \ + MBEDTLS_PSA_HASH_OPERATION_INIT +#endif /* MBEDTLS_TEST_LIBTESTDRIVER1 && + LIBTESTDRIVER1_MBEDTLS_PSA_BUILTIN_HASH */ + +typedef struct { + unsigned int initialised : 1; + mbedtls_transparent_test_driver_cipher_operation_t ctx; +} mbedtls_opaque_test_driver_cipher_operation_t; + +#define MBEDTLS_OPAQUE_TEST_DRIVER_CIPHER_OPERATION_INIT \ + { 0, MBEDTLS_TRANSPARENT_TEST_DRIVER_CIPHER_OPERATION_INIT } + +#endif /* PSA_CRYPTO_DRIVER_TEST */ + +/* Include the context structures for all declared hardware drivers */ +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) + +#include "sli_psa_driver_features.h" + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + #include "sli_se_transparent_types.h" + + #if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + #include "sli_se_opaque_types.h" + #endif +#endif + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + #include "sli_cryptoacc_transparent_types.h" +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S1) + #include "sli_crypto_transparent_types.h" +#endif + +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + +/* Define the context to be used for an operation that is executed through the + * PSA Driver wrapper layer as the union of all possible driver's contexts. + * + * The union members are the driver's context structures, and the member names + * are formatted as `'drivername'_ctx`. This allows for procedural generation + * of both this file and the content of psa_crypto_driver_wrappers.h */ + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_hash_operation_t mbedtls_ctx; +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_transparent_test_driver_hash_operation_t test_driver_ctx; +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + sli_se_transparent_hash_operation_t sli_se_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + sli_cryptoacc_transparent_hash_operation_t sli_cryptoacc_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#if defined(SLI_MBEDTLS_DEVICE_S1) + sli_crypto_transparent_hash_operation_t sli_crypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_S1 */ +#endif +} psa_driver_hash_context_t; + +typedef union { + unsigned dummy; /* Make sure this union is always non-empty */ + mbedtls_psa_cipher_operation_t mbedtls_ctx; +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_transparent_test_driver_cipher_operation_t transparent_test_driver_ctx; + mbedtls_opaque_test_driver_cipher_operation_t opaque_test_driver_ctx; +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + sli_se_transparent_cipher_operation_t sli_se_transparent_ctx; +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + sli_se_opaque_cipher_operation_t sli_se_opaque_ctx; +#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + sli_cryptoacc_transparent_cipher_operation_t sli_cryptoacc_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#if defined(SLI_MBEDTLS_DEVICE_S1) + sli_crypto_transparent_cipher_operation_t sli_crypto_transparent_ctx; +#endif /* SLI_MBEDTLS_DEVICE_S1 */ +#endif +} psa_driver_cipher_context_t; + +#endif /* PSA_CRYPTO_DRIVER_CONTEXTS_PRIMITIVES_H */ +/* End of automatically generated file. */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_extra.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_extra.h index 2c000c2..cc2cf7c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_extra.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_extra.h @@ -1,2089 +1,2089 @@ -/** - * \file psa/crypto_extra.h - * - * \brief PSA cryptography module: Mbed TLS vendor extensions - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file is reserved for vendor-specific definitions. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_extra.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_extra.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_EXTRA_H -#define PSA_CRYPTO_EXTRA_H -#include "mbedtls/private_access.h" - -#include "crypto_types.h" -#include "crypto_compat.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* UID for secure storage seed */ -#define PSA_CRYPTO_ITS_RANDOM_SEED_UID 0xFFFFFF52 - -/* See mbedtls_config.h for definition */ -#if !defined(MBEDTLS_PSA_KEY_SLOT_COUNT) -#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 -#endif - -/** \addtogroup attributes - * @{ - */ - -/** \brief Declare the enrollment algorithm for a key. - * - * An operation on a key may indifferently use the algorithm set with - * psa_set_key_algorithm() or with this function. - * - * \param[out] attributes The attribute structure to write to. - * \param alg2 A second algorithm that the key may be used - * for, in addition to the algorithm set with - * psa_set_key_algorithm(). - * - * \warning Setting an enrollment algorithm is not recommended, because - * using the same key with different algorithms can allow some - * attacks based on arithmetic relations between different - * computations made with the same key, or can escalate harmless - * side channels into exploitable ones. Use this function only - * if it is necessary to support a protocol for which it has been - * verified that the usage of the key with multiple algorithms - * is safe. - */ -static inline void psa_set_key_enrollment_algorithm( - psa_key_attributes_t *attributes, - psa_algorithm_t alg2) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2) = alg2; -} - -/** Retrieve the enrollment algorithm policy from key attributes. - * - * \param[in] attributes The key attribute structure to query. - * - * \return The enrollment algorithm stored in the attribute structure. - */ -static inline psa_algorithm_t psa_get_key_enrollment_algorithm( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2); -} - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - -/** Retrieve the slot number where a key is stored. - * - * A slot number is only defined for keys that are stored in a secure - * element. - * - * This information is only useful if the secure element is not entirely - * managed through the PSA Cryptography API. It is up to the secure - * element driver to decide how PSA slot numbers map to any other interface - * that the secure element may have. - * - * \param[in] attributes The key attribute structure to query. - * \param[out] slot_number On success, the slot number containing the key. - * - * \retval #PSA_SUCCESS - * The key is located in a secure element, and \p *slot_number - * indicates the slot number that contains it. - * \retval #PSA_ERROR_NOT_PERMITTED - * The caller is not permitted to query the slot number. - * Mbed TLS currently does not return this error. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key is not located in a secure element. - */ -psa_status_t psa_get_key_slot_number( - const psa_key_attributes_t *attributes, - psa_key_slot_number_t *slot_number); - -/** Choose the slot number where a key is stored. - * - * This function declares a slot number in the specified attribute - * structure. - * - * A slot number is only meaningful for keys that are stored in a secure - * element. It is up to the secure element driver to decide how PSA slot - * numbers map to any other interface that the secure element may have. - * - * \note Setting a slot number in key attributes for a key creation can - * cause the following errors when creating the key: - * - #PSA_ERROR_NOT_SUPPORTED if the selected secure element does - * not support choosing a specific slot number. - * - #PSA_ERROR_NOT_PERMITTED if the caller is not permitted to - * choose slot numbers in general or to choose this specific slot. - * - #PSA_ERROR_INVALID_ARGUMENT if the chosen slot number is not - * valid in general or not valid for this specific key. - * - #PSA_ERROR_ALREADY_EXISTS if there is already a key in the - * selected slot. - * - * \param[out] attributes The attribute structure to write to. - * \param slot_number The slot number to set. - */ -static inline void psa_set_key_slot_number( - psa_key_attributes_t *attributes, - psa_key_slot_number_t slot_number) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(flags) |= MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER; - attributes->MBEDTLS_PRIVATE(slot_number) = slot_number; -} - -/** Remove the slot number attribute from a key attribute structure. - * - * This function undoes the action of psa_set_key_slot_number(). - * - * \param[out] attributes The attribute structure to write to. - */ -static inline void psa_clear_key_slot_number( - psa_key_attributes_t *attributes) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(flags) &= - ~MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER; -} - -/** Register a key that is already present in a secure element. - * - * The key must be located in a secure element designated by the - * lifetime field in \p attributes, in the slot set with - * psa_set_key_slot_number() in the attribute structure. - * This function makes the key available through the key identifier - * specified in \p attributes. - * - * \param[in] attributes The attributes of the existing key. - * - * \retval #PSA_SUCCESS - * The key was successfully registered. - * Note that depending on the design of the driver, this may or may - * not guarantee that a key actually exists in the designated slot - * and is compatible with the specified attributes. - * \retval #PSA_ERROR_ALREADY_EXISTS - * There is already a key with the identifier specified in - * \p attributes. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The secure element driver for the specified lifetime does not - * support registering a key. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The identifier in \p attributes is invalid, namely the identifier is - * not in the user range, or - * \p attributes specifies a lifetime which is not located - * in a secure element, or no slot number is specified in \p attributes, - * or the specified slot number is not valid. - * \retval #PSA_ERROR_NOT_PERMITTED - * The caller is not authorized to register the specified key slot. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t mbedtls_psa_register_se_key( - const psa_key_attributes_t *attributes); - -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -/**@}*/ - -/** - * \brief Library deinitialization. - * - * This function clears all data associated with the PSA layer, - * including the whole key store. - * - * This is an Mbed TLS extension. - */ -void mbedtls_psa_crypto_free(void); - -/** \brief Statistics about - * resource consumption related to the PSA keystore. - * - * \note The content of this structure is not part of the stable API and ABI - * of Mbed TLS and may change arbitrarily from version to version. - */ -typedef struct mbedtls_psa_stats_s { - /** Number of slots containing key material for a volatile key. */ - size_t MBEDTLS_PRIVATE(volatile_slots); - /** Number of slots containing key material for a key which is in - * internal persistent storage. */ - size_t MBEDTLS_PRIVATE(persistent_slots); - /** Number of slots containing a reference to a key in a - * secure element. */ - size_t MBEDTLS_PRIVATE(external_slots); - /** Number of slots which are occupied, but do not contain - * key material yet. */ - size_t MBEDTLS_PRIVATE(half_filled_slots); - /** Number of slots that contain cache data. */ - size_t MBEDTLS_PRIVATE(cache_slots); - /** Number of slots that are not used for anything. */ - size_t MBEDTLS_PRIVATE(empty_slots); - /** Number of slots that are locked. */ - size_t MBEDTLS_PRIVATE(locked_slots); - /** Largest key id value among open keys in internal persistent storage. */ - psa_key_id_t MBEDTLS_PRIVATE(max_open_internal_key_id); - /** Largest key id value among open keys in secure elements. */ - psa_key_id_t MBEDTLS_PRIVATE(max_open_external_key_id); -} mbedtls_psa_stats_t; - -/** \brief Get statistics about - * resource consumption related to the PSA keystore. - * - * \note When Mbed TLS is built as part of a service, with isolation - * between the application and the keystore, the service may or - * may not expose this function. - */ -void mbedtls_psa_get_stats(mbedtls_psa_stats_t *stats); - -/** - * \brief Inject an initial entropy seed for the random generator into - * secure storage. - * - * This function injects data to be used as a seed for the random generator - * used by the PSA Crypto implementation. On devices that lack a trusted - * entropy source (preferably a hardware random number generator), - * the Mbed PSA Crypto implementation uses this value to seed its - * random generator. - * - * On devices without a trusted entropy source, this function must be - * called exactly once in the lifetime of the device. On devices with - * a trusted entropy source, calling this function is optional. - * In all cases, this function may only be called before calling any - * other function in the PSA Crypto API, including psa_crypto_init(). - * - * When this function returns successfully, it populates a file in - * persistent storage. Once the file has been created, this function - * can no longer succeed. - * - * If any error occurs, this function does not change the system state. - * You can call this function again after correcting the reason for the - * error if possible. - * - * \warning This function **can** fail! Callers MUST check the return status. - * - * \warning If you use this function, you should use it as part of a - * factory provisioning process. The value of the injected seed - * is critical to the security of the device. It must be - * *secret*, *unpredictable* and (statistically) *unique per device*. - * You should be generate it randomly using a cryptographically - * secure random generator seeded from trusted entropy sources. - * You should transmit it securely to the device and ensure - * that its value is not leaked or stored anywhere beyond the - * needs of transmitting it from the point of generation to - * the call of this function, and erase all copies of the value - * once this function returns. - * - * This is an Mbed TLS extension. - * - * \note This function is only available on the following platforms: - * * If the compile-time option MBEDTLS_PSA_INJECT_ENTROPY is enabled. - * Note that you must provide compatible implementations of - * mbedtls_nv_seed_read and mbedtls_nv_seed_write. - * * In a client-server integration of PSA Cryptography, on the client side, - * if the server supports this feature. - * \param[in] seed Buffer containing the seed value to inject. - * \param[in] seed_size Size of the \p seed buffer. - * The size of the seed in bytes must be greater - * or equal to both #MBEDTLS_ENTROPY_BLOCK_SIZE - * and the value of \c MBEDTLS_ENTROPY_MIN_PLATFORM - * in `library/entropy_poll.h` in the Mbed TLS source - * code. - * It must be less or equal to - * #MBEDTLS_ENTROPY_MAX_SEED_SIZE. - * - * \retval #PSA_SUCCESS - * The seed value was injected successfully. The random generator - * of the PSA Crypto implementation is now ready for use. - * You may now call psa_crypto_init() and use the PSA Crypto - * implementation. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p seed_size is out of range. - * \retval #PSA_ERROR_STORAGE_FAILURE - * There was a failure reading or writing from storage. - * \retval #PSA_ERROR_NOT_PERMITTED - * The library has already been initialized. It is no longer - * possible to call this function. - */ -psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, - size_t seed_size); - -/** \addtogroup crypto_types - * @{ - */ - -/** DSA public key. - * - * The import and export format is the - * representation of the public key `y = g^x mod p` as a big-endian byte - * string. The length of the byte string is the length of the base prime `p` - * in bytes. - */ -#define PSA_KEY_TYPE_DSA_PUBLIC_KEY ((psa_key_type_t) 0x4002) - -/** DSA key pair (private and public key). - * - * The import and export format is the - * representation of the private key `x` as a big-endian byte string. The - * length of the byte string is the private key size in bytes (leading zeroes - * are not stripped). - * - * Deterministic DSA key derivation with psa_generate_derived_key follows - * FIPS 186-4 §B.1.2: interpret the byte string as integer - * in big-endian order. Discard it if it is not in the range - * [0, *N* - 2] where *N* is the boundary of the private key domain - * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, - * or the order of the curve's base point for ECC). - * Add 1 to the resulting integer and use this as the private key *x*. - * - */ -#define PSA_KEY_TYPE_DSA_KEY_PAIR ((psa_key_type_t) 0x7002) - -/** Whether a key type is a DSA key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_DSA(type) \ - (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY) - -#define PSA_ALG_DSA_BASE ((psa_algorithm_t) 0x06000400) -/** DSA signature with hashing. - * - * This is the signature scheme defined by FIPS 186-4, - * with a random per-message secret number (*k*). - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding DSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DSA(hash_alg) \ - (PSA_ALG_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t) 0x06000500) -#define PSA_ALG_DSA_DETERMINISTIC_FLAG PSA_ALG_ECDSA_DETERMINISTIC_FLAG -/** Deterministic DSA signature with hashing. - * - * This is the deterministic variant defined by RFC 6979 of - * the signature scheme defined by FIPS 186-4. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding DSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DETERMINISTIC_DSA(hash_alg) \ - (PSA_ALG_DETERMINISTIC_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_IS_DSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_DSA_DETERMINISTIC_FLAG) == \ - PSA_ALG_DSA_BASE) -#define PSA_ALG_DSA_IS_DETERMINISTIC(alg) \ - (((alg) & PSA_ALG_DSA_DETERMINISTIC_FLAG) != 0) -#define PSA_ALG_IS_DETERMINISTIC_DSA(alg) \ - (PSA_ALG_IS_DSA(alg) && PSA_ALG_DSA_IS_DETERMINISTIC(alg)) -#define PSA_ALG_IS_RANDOMIZED_DSA(alg) \ - (PSA_ALG_IS_DSA(alg) && !PSA_ALG_DSA_IS_DETERMINISTIC(alg)) - - -/* We need to expand the sample definition of this macro from - * the API definition. */ -#undef PSA_ALG_IS_VENDOR_HASH_AND_SIGN -#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) \ - PSA_ALG_IS_DSA(alg) - -/**@}*/ - -/** \addtogroup attributes - * @{ - */ - -/** Custom Diffie-Hellman group. - * - * For keys of type #PSA_KEY_TYPE_DH_PUBLIC_KEY(#PSA_DH_FAMILY_CUSTOM) or - * #PSA_KEY_TYPE_DH_KEY_PAIR(#PSA_DH_FAMILY_CUSTOM), the group data comes - * from domain parameters set by psa_set_key_domain_parameters(). - */ -#define PSA_DH_FAMILY_CUSTOM ((psa_dh_family_t) 0x7e) - -/** PAKE operation stages. */ -#define PSA_PAKE_OPERATION_STAGE_SETUP 0 -#define PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS 1 -#define PSA_PAKE_OPERATION_STAGE_COMPUTATION 2 - -/** - * \brief Set domain parameters for a key. - * - * Some key types require additional domain parameters in addition to - * the key type identifier and the key size. Use this function instead - * of psa_set_key_type() when you need to specify domain parameters. - * - * The format for the required domain parameters varies based on the key type. - * - * - For RSA keys (#PSA_KEY_TYPE_RSA_PUBLIC_KEY or #PSA_KEY_TYPE_RSA_KEY_PAIR), - * the domain parameter data consists of the public exponent, - * represented as a big-endian integer with no leading zeros. - * This information is used when generating an RSA key pair. - * When importing a key, the public exponent is read from the imported - * key data and the exponent recorded in the attribute structure is ignored. - * As an exception, the public exponent 65537 is represented by an empty - * byte string. - * - For DSA keys (#PSA_KEY_TYPE_DSA_PUBLIC_KEY or #PSA_KEY_TYPE_DSA_KEY_PAIR), - * the `Dss-Params` format as defined by RFC 3279 §2.3.2. - * ``` - * Dss-Params ::= SEQUENCE { - * p INTEGER, - * q INTEGER, - * g INTEGER - * } - * ``` - * - For Diffie-Hellman key exchange keys - * (#PSA_KEY_TYPE_DH_PUBLIC_KEY(#PSA_DH_FAMILY_CUSTOM) or - * #PSA_KEY_TYPE_DH_KEY_PAIR(#PSA_DH_FAMILY_CUSTOM)), the - * `DomainParameters` format as defined by RFC 3279 §2.3.3. - * ``` - * DomainParameters ::= SEQUENCE { - * p INTEGER, -- odd prime, p=jq +1 - * g INTEGER, -- generator, g - * q INTEGER, -- factor of p-1 - * j INTEGER OPTIONAL, -- subgroup factor - * validationParams ValidationParams OPTIONAL - * } - * ValidationParams ::= SEQUENCE { - * seed BIT STRING, - * pgenCounter INTEGER - * } - * ``` - * - * \note This function may allocate memory or other resources. - * Once you have called this function on an attribute structure, - * you must call psa_reset_key_attributes() to free these resources. - * - * \note This is an experimental extension to the interface. It may change - * in future versions of the library. - * - * \param[in,out] attributes Attribute structure where the specified domain - * parameters will be stored. - * If this function fails, the content of - * \p attributes is not modified. - * \param type Key type (a \c PSA_KEY_TYPE_XXX value). - * \param[in] data Buffer containing the key domain parameters. - * The content of this buffer is interpreted - * according to \p type as described above. - * \param data_length Size of the \p data buffer in bytes. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, - psa_key_type_t type, - const uint8_t *data, - size_t data_length); - -/** - * \brief Get domain parameters for a key. - * - * Get the domain parameters for a key with this function, if any. The format - * of the domain parameters written to \p data is specified in the - * documentation for psa_set_key_domain_parameters(). - * - * \note This is an experimental extension to the interface. It may change - * in future versions of the library. - * - * \param[in] attributes The key attribute structure to query. - * \param[out] data On success, the key domain parameters. - * \param data_size Size of the \p data buffer in bytes. - * The buffer is guaranteed to be large - * enough if its size in bytes is at least - * the value given by - * PSA_KEY_DOMAIN_PARAMETERS_SIZE(). - * \param[out] data_length On success, the number of bytes - * that make up the key domain parameters data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription - */ -psa_status_t psa_get_key_domain_parameters( - const psa_key_attributes_t *attributes, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** Safe output buffer size for psa_get_key_domain_parameters(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \note This is an experimental extension to the interface. It may change - * in future versions of the library. - * - * \param key_type A supported key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_get_key_domain_parameters() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported - * by the implementation, this macro shall return either a - * sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_KEY_DOMAIN_PARAMETERS_SIZE(key_type, key_bits) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? sizeof(int) : \ - PSA_KEY_TYPE_IS_DH(key_type) ? PSA_DH_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_DSA(key_type) ? PSA_DSA_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) : \ - 0) -#define PSA_DH_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) \ - (4 + (PSA_BITS_TO_BYTES(key_bits) + 5) * 3 /*without optional parts*/) -#define PSA_DSA_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) \ - (4 + (PSA_BITS_TO_BYTES(key_bits) + 5) * 2 /*p, g*/ + 34 /*q*/) - -/**@}*/ - -/** \defgroup psa_tls_helpers TLS helper functions - * @{ - */ -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -#include - -/** Convert an ECC curve identifier from the Mbed TLS encoding to PSA. - * - * \note This function is provided solely for the convenience of - * Mbed TLS and may be removed at any time without notice. - * - * \param grpid An Mbed TLS elliptic curve identifier - * (`MBEDTLS_ECP_DP_xxx`). - * \param[out] bits On success, the bit size of the curve. - * - * \return The corresponding PSA elliptic curve identifier - * (`PSA_ECC_FAMILY_xxx`). - * \return \c 0 on failure (\p grpid is not recognized). - */ -psa_ecc_family_t mbedtls_ecc_group_to_psa(mbedtls_ecp_group_id grpid, - size_t *bits); - -/** Convert an ECC curve identifier from the PSA encoding to Mbed TLS. - * - * \note This function is provided solely for the convenience of - * Mbed TLS and may be removed at any time without notice. - * - * \param curve A PSA elliptic curve identifier - * (`PSA_ECC_FAMILY_xxx`). - * \param bits The bit-length of a private key on \p curve. - * \param bits_is_sloppy If true, \p bits may be the bit-length rounded up - * to the nearest multiple of 8. This allows the caller - * to infer the exact curve from the length of a key - * which is supplied as a byte string. - * - * \return The corresponding Mbed TLS elliptic curve identifier - * (`MBEDTLS_ECP_DP_xxx`). - * \return #MBEDTLS_ECP_DP_NONE if \c curve is not recognized. - * \return #MBEDTLS_ECP_DP_NONE if \p bits is not - * correct for \p curve. - */ -mbedtls_ecp_group_id mbedtls_ecc_group_of_psa(psa_ecc_family_t curve, - size_t bits, - int bits_is_sloppy); -#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ - -/**@}*/ - -/** \defgroup psa_external_rng External random generator - * @{ - */ - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -/** External random generator function, implemented by the platform. - * - * When the compile-time option #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is enabled, - * this function replaces Mbed TLS's entropy and DRBG modules for all - * random generation triggered via PSA crypto interfaces. - * - * \note This random generator must deliver random numbers with cryptographic - * quality and high performance. It must supply unpredictable numbers - * with a uniform distribution. The implementation of this function - * is responsible for ensuring that the random generator is seeded - * with sufficient entropy. If you have a hardware TRNG which is slow - * or delivers non-uniform output, declare it as an entropy source - * with mbedtls_entropy_add_source() instead of enabling this option. - * - * \param[in,out] context Pointer to the random generator context. - * This is all-bits-zero on the first call - * and preserved between successive calls. - * \param[out] output Output buffer. On success, this buffer - * contains random data with a uniform - * distribution. - * \param output_size The size of the \p output buffer in bytes. - * \param[out] output_length On success, set this value to \p output_size. - * - * \retval #PSA_SUCCESS - * Success. The output buffer contains \p output_size bytes of - * cryptographic-quality random data, and \c *output_length is - * set to \p output_size. - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY - * The random generator requires extra entropy and there is no - * way to obtain entropy under current environment conditions. - * This error should not happen under normal circumstances since - * this function is responsible for obtaining as much entropy as - * it needs. However implementations of this function may return - * #PSA_ERROR_INSUFFICIENT_ENTROPY if there is no way to obtain - * entropy without blocking indefinitely. - * \retval #PSA_ERROR_HARDWARE_FAILURE - * A failure of the random generator hardware that isn't covered - * by #PSA_ERROR_INSUFFICIENT_ENTROPY. - */ -psa_status_t mbedtls_psa_external_get_random( - mbedtls_psa_external_random_context_t *context, - uint8_t *output, size_t output_size, size_t *output_length); -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -/**@}*/ - -/** \defgroup psa_builtin_keys Built-in keys - * @{ - */ - -/** The minimum value for a key identifier that is built into the - * implementation. - * - * The range of key identifiers from #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN - * to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX within the range from - * #PSA_KEY_ID_VENDOR_MIN and #PSA_KEY_ID_VENDOR_MAX and must not intersect - * with any other set of implementation-chosen key identifiers. - * - * This value is part of the library's ABI since changing it would invalidate - * the values of built-in key identifiers in applications. - */ -#define MBEDTLS_PSA_KEY_ID_BUILTIN_MIN ((psa_key_id_t) 0x7fff0000) - -/** The maximum value for a key identifier that is built into the - * implementation. - * - * See #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN for more information. - */ -#define MBEDTLS_PSA_KEY_ID_BUILTIN_MAX ((psa_key_id_t) 0x7fffefff) - -/** A slot number identifying a key in a driver. - * - * Values of this type are used to identify built-in keys. - */ -typedef uint64_t psa_drv_slot_number_t; - -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) -/** Test whether a key identifier belongs to the builtin key range. - * - * \param key_id Key identifier to test. - * - * \retval 1 - * The key identifier is a builtin key identifier. - * \retval 0 - * The key identifier is not a builtin key identifier. - */ -static inline int psa_key_id_is_builtin(psa_key_id_t key_id) -{ - return (key_id >= MBEDTLS_PSA_KEY_ID_BUILTIN_MIN) && - (key_id <= MBEDTLS_PSA_KEY_ID_BUILTIN_MAX); -} - -/** Platform function to obtain the location and slot number of a built-in key. - * - * An application-specific implementation of this function must be provided if - * #MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS is enabled. This would typically be provided - * as part of a platform's system image. - * - * #MBEDTLS_SVC_KEY_ID_GET_KEY_ID(\p key_id) needs to be in the range from - * #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX. - * - * In a multi-application configuration - * (\c MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER is defined), - * this function should check that #MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(\p key_id) - * is allowed to use the given key. - * - * \param key_id The key ID for which to retrieve the - * location and slot attributes. - * \param[out] lifetime On success, the lifetime associated with the key - * corresponding to \p key_id. Lifetime is a - * combination of which driver contains the key, - * and with what persistence level the key is - * intended to be used. If the platform - * implementation does not contain specific - * information about the intended key persistence - * level, the persistence level may be reported as - * #PSA_KEY_PERSISTENCE_DEFAULT. - * \param[out] slot_number On success, the slot number known to the driver - * registered at the lifetime location reported - * through \p lifetime which corresponds to the - * requested built-in key. - * - * \retval #PSA_SUCCESS - * The requested key identifier designates a built-in key. - * In a multi-application configuration, the requested owner - * is allowed to access it. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * The requested key identifier is not a built-in key which is known - * to this function. If a key exists in the key storage with this - * identifier, the data from the storage will be used. - * \return (any other error) - * Any other error is propagated to the function that requested the key. - * Common errors include: - * - #PSA_ERROR_NOT_PERMITTED: the key exists but the requested owner - * is not allowed to access it. - */ -psa_status_t mbedtls_psa_platform_get_builtin_key( - mbedtls_svc_key_id_t key_id, - psa_key_lifetime_t *lifetime, - psa_drv_slot_number_t *slot_number); -#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - -/** @} */ - -/** \addtogroup crypto_types - * @{ - */ - -#define PSA_ALG_CATEGORY_PAKE ((psa_algorithm_t) 0x0a000000) - -/** Whether the specified algorithm is a password-authenticated key exchange. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a password-authenticated key exchange (PAKE) - * algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_PAKE(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_PAKE) - -/** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. - * - * This is J-PAKE as defined by RFC 8236, instantiated with the following - * parameters: - * - * - The group can be either an elliptic curve or defined over a finite field. - * - Schnorr NIZK proof as defined by RFC 8235 and using the same group as the - * J-PAKE algorithm. - * - A cryptographic hash function. - * - * To select these parameters and set up the cipher suite, call these functions - * in any order: - * - * \code - * psa_pake_cs_set_algorithm(cipher_suite, PSA_ALG_JPAKE); - * psa_pake_cs_set_primitive(cipher_suite, - * PSA_PAKE_PRIMITIVE(type, family, bits)); - * psa_pake_cs_set_hash(cipher_suite, hash); - * \endcode - * - * For more information on how to set a specific curve or field, refer to the - * documentation of the individual \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - * - * After initializing a J-PAKE operation, call - * - * \code - * psa_pake_setup(operation, cipher_suite); - * psa_pake_set_user(operation, ...); - * psa_pake_set_peer(operation, ...); - * psa_pake_set_password_key(operation, ...); - * \endcode - * - * The password is provided as a key. This can be the password text itself, - * in an agreed character encoding, or some value derived from the password - * as required by a higher level protocol. - * - * (The implementation converts the key material to a number as described in - * Section 2.3.8 of _SEC 1: Elliptic Curve Cryptography_ - * (https://www.secg.org/sec1-v2.pdf), before reducing it modulo \c q. Here - * \c q is order of the group defined by the primitive set in the cipher suite. - * The \c psa_pake_set_password_key() function returns an error if the result - * of the reduction is 0.) - * - * The key exchange flow for J-PAKE is as follows: - * -# To get the first round data that needs to be sent to the peer, call - * \code - * // Get g1 - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get the ZKP public key for x1 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get the ZKP proof for x1 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * // Get g2 - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get the ZKP public key for x2 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get the ZKP proof for x2 - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To provide the first round data received from the peer to the operation, - * call - * \code - * // Set g3 - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set the ZKP public key for x3 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set the ZKP proof for x3 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * // Set g4 - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set the ZKP public key for x4 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set the ZKP proof for x4 - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To get the second round data that needs to be sent to the peer, call - * \code - * // Get A - * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Get ZKP public key for x2*s - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Get ZKP proof for x2*s - * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To provide the second round data received from the peer to the operation, - * call - * \code - * // Set B - * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); - * // Set ZKP public key for x4*s - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); - * // Set ZKP proof for x4*s - * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); - * \endcode - * -# To access the shared secret call - * \code - * // Get Ka=Kb=K - * psa_pake_get_implicit_key() - * \endcode - * - * For more information consult the documentation of the individual - * \c PSA_PAKE_STEP_XXX constants. - * - * At this point there is a cryptographic guarantee that only the authenticated - * party who used the same password is able to compute the key. But there is no - * guarantee that the peer is the party it claims to be and was able to do so. - * - * That is, the authentication is only implicit (the peer is not authenticated - * at this point, and no action should be taken that assume that they are - like - * for example accessing restricted files). - * - * To make the authentication explicit there are various methods, see Section 5 - * of RFC 8236 for two examples. - * - */ -#define PSA_ALG_JPAKE ((psa_algorithm_t) 0x0a000100) - -/** @} */ - -/** \defgroup pake Password-authenticated key exchange (PAKE) - * - * This is a proposed PAKE interface for the PSA Crypto API. It is not part of - * the official PSA Crypto API yet. - * - * \note The content of this section is not part of the stable API and ABI - * of Mbed TLS and may change arbitrarily from version to version. - * Same holds for the corresponding macros #PSA_ALG_CATEGORY_PAKE and - * #PSA_ALG_JPAKE. - * @{ - */ - -/** \brief Encoding of the application role of PAKE - * - * Encodes the application's role in the algorithm is being executed. For more - * information see the documentation of individual \c PSA_PAKE_ROLE_XXX - * constants. - */ -typedef uint8_t psa_pake_role_t; - -/** Encoding of input and output indicators for PAKE. - * - * Some PAKE algorithms need to exchange more data than just a single key share. - * This type is for encoding additional input and output data for such - * algorithms. - */ -typedef uint8_t psa_pake_step_t; - -/** Encoding of the type of the PAKE's primitive. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional types must use an encoding in this range. - * - * For more information see the documentation of individual - * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - */ -typedef uint8_t psa_pake_primitive_type_t; - -/** \brief Encoding of the family of the primitive associated with the PAKE. - * - * For more information see the documentation of individual - * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. - */ -typedef uint8_t psa_pake_family_t; - -/** \brief Encoding of the primitive associated with the PAKE. - * - * For more information see the documentation of the #PSA_PAKE_PRIMITIVE macro. - */ -typedef uint32_t psa_pake_primitive_t; - -/** A value to indicate no role in a PAKE algorithm. - * This value can be used in a call to psa_pake_set_role() for symmetric PAKE - * algorithms which do not assign roles. - */ -#define PSA_PAKE_ROLE_NONE ((psa_pake_role_t) 0x00) - -/** The first peer in a balanced PAKE. - * - * Although balanced PAKE algorithms are symmetric, some of them needs an - * ordering of peers for the transcript calculations. If the algorithm does not - * need this, both #PSA_PAKE_ROLE_FIRST and #PSA_PAKE_ROLE_SECOND are - * accepted. - */ -#define PSA_PAKE_ROLE_FIRST ((psa_pake_role_t) 0x01) - -/** The second peer in a balanced PAKE. - * - * Although balanced PAKE algorithms are symmetric, some of them needs an - * ordering of peers for the transcript calculations. If the algorithm does not - * need this, either #PSA_PAKE_ROLE_FIRST or #PSA_PAKE_ROLE_SECOND are - * accepted. - */ -#define PSA_PAKE_ROLE_SECOND ((psa_pake_role_t) 0x02) - -/** The client in an augmented PAKE. - * - * Augmented PAKE algorithms need to differentiate between client and server. - */ -#define PSA_PAKE_ROLE_CLIENT ((psa_pake_role_t) 0x11) - -/** The server in an augmented PAKE. - * - * Augmented PAKE algorithms need to differentiate between client and server. - */ -#define PSA_PAKE_ROLE_SERVER ((psa_pake_role_t) 0x12) - -/** The PAKE primitive type indicating the use of elliptic curves. - * - * The values of the \c family and \c bits fields of the cipher suite identify a - * specific elliptic curve, using the same mapping that is used for ECC - * (::psa_ecc_family_t) keys. - * - * (Here \c family means the value returned by psa_pake_cs_get_family() and - * \c bits means the value returned by psa_pake_cs_get_bits().) - * - * Input and output during the operation can involve group elements and scalar - * values: - * -# The format for group elements is the same as for public keys on the - * specific curve would be. For more information, consult the documentation of - * psa_export_public_key(). - * -# The format for scalars is the same as for private keys on the specific - * curve would be. For more information, consult the documentation of - * psa_export_key(). - */ -#define PSA_PAKE_PRIMITIVE_TYPE_ECC ((psa_pake_primitive_type_t) 0x01) - -/** The PAKE primitive type indicating the use of Diffie-Hellman groups. - * - * The values of the \c family and \c bits fields of the cipher suite identify - * a specific Diffie-Hellman group, using the same mapping that is used for - * Diffie-Hellman (::psa_dh_family_t) keys. - * - * (Here \c family means the value returned by psa_pake_cs_get_family() and - * \c bits means the value returned by psa_pake_cs_get_bits().) - * - * Input and output during the operation can involve group elements and scalar - * values: - * -# The format for group elements is the same as for public keys on the - * specific group would be. For more information, consult the documentation of - * psa_export_public_key(). - * -# The format for scalars is the same as for private keys on the specific - * group would be. For more information, consult the documentation of - * psa_export_key(). - */ -#define PSA_PAKE_PRIMITIVE_TYPE_DH ((psa_pake_primitive_type_t) 0x02) - -/** Construct a PAKE primitive from type, family and bit-size. - * - * \param pake_type The type of the primitive - * (value of type ::psa_pake_primitive_type_t). - * \param pake_family The family of the primitive - * (the type and interpretation of this parameter depends - * on \p pake_type, for more information consult the - * documentation of individual ::psa_pake_primitive_type_t - * constants). - * \param pake_bits The bit-size of the primitive - * (Value of type \c size_t. The interpretation - * of this parameter depends on \p pake_family, for more - * information consult the documentation of individual - * ::psa_pake_primitive_type_t constants). - * - * \return The constructed primitive value of type ::psa_pake_primitive_t. - * Return 0 if the requested primitive can't be encoded as - * ::psa_pake_primitive_t. - */ -#define PSA_PAKE_PRIMITIVE(pake_type, pake_family, pake_bits) \ - ((pake_bits & 0xFFFF) != pake_bits) ? 0 : \ - ((psa_pake_primitive_t) (((pake_type) << 24 | \ - (pake_family) << 16) | (pake_bits))) - -/** The key share being sent to or received from the peer. - * - * The format for both input and output at this step is the same as for public - * keys on the group determined by the primitive (::psa_pake_primitive_t) would - * be. - * - * For more information on the format, consult the documentation of - * psa_export_public_key(). - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_KEY_SHARE ((psa_pake_step_t) 0x01) - -/** A Schnorr NIZKP public key. - * - * This is the ephemeral public key in the Schnorr Non-Interactive - * Zero-Knowledge Proof (the value denoted by the letter 'V' in RFC 8235). - * - * The format for both input and output at this step is the same as for public - * keys on the group determined by the primitive (::psa_pake_primitive_t) would - * be. - * - * For more information on the format, consult the documentation of - * psa_export_public_key(). - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_ZK_PUBLIC ((psa_pake_step_t) 0x02) - -/** A Schnorr NIZKP proof. - * - * This is the proof in the Schnorr Non-Interactive Zero-Knowledge Proof (the - * value denoted by the letter 'r' in RFC 8235). - * - * Both for input and output, the value at this step is an integer less than - * the order of the group selected in the cipher suite. The format depends on - * the group as well: - * - * - For Montgomery curves, the encoding is little endian. - * - For everything else the encoding is big endian (see Section 2.3.8 of - * _SEC 1: Elliptic Curve Cryptography_ at https://www.secg.org/sec1-v2.pdf). - * - * In both cases leading zeroes are allowed as long as the length in bytes does - * not exceed the byte length of the group order. - * - * For information regarding how the group is determined, consult the - * documentation #PSA_PAKE_PRIMITIVE. - */ -#define PSA_PAKE_STEP_ZK_PROOF ((psa_pake_step_t) 0x03) - -/** The type of the data structure for PAKE cipher suites. - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. - */ -typedef struct psa_pake_cipher_suite_s psa_pake_cipher_suite_t; - -/** Return an initial value for a PAKE cipher suite object. - */ -static psa_pake_cipher_suite_t psa_pake_cipher_suite_init(void); - -/** Retrieve the PAKE algorithm from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE algorithm stored in the cipher suite structure. - */ -static psa_algorithm_t psa_pake_cs_get_algorithm( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the PAKE algorithm for the cipher suite. - * - * This function overwrites any PAKE algorithm - * previously set in \p cipher_suite. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param algorithm The PAKE algorithm to write. - * (`PSA_ALG_XXX` values of type ::psa_algorithm_t - * such that #PSA_ALG_IS_PAKE(\c alg) is true.) - * If this is 0, the PAKE algorithm in - * \p cipher_suite becomes unspecified. - */ -static void psa_pake_cs_set_algorithm(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t algorithm); - -/** Retrieve the primitive from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The primitive stored in the cipher suite structure. - */ -static psa_pake_primitive_t psa_pake_cs_get_primitive( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the primitive for a PAKE cipher suite. - * - * This function overwrites any primitive previously set in \p cipher_suite. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param primitive The primitive to write. If this is 0, the - * primitive type in \p cipher_suite becomes - * unspecified. - */ -static void psa_pake_cs_set_primitive(psa_pake_cipher_suite_t *cipher_suite, - psa_pake_primitive_t primitive); - -/** Retrieve the PAKE family from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE family stored in the cipher suite structure. - */ -static psa_pake_family_t psa_pake_cs_get_family( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Retrieve the PAKE primitive bit-size from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The PAKE primitive bit-size stored in the cipher suite structure. - */ -static uint16_t psa_pake_cs_get_bits( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Retrieve the hash algorithm from a PAKE cipher suite. - * - * \param[in] cipher_suite The cipher suite structure to query. - * - * \return The hash algorithm stored in the cipher suite structure. The return - * value is 0 if the PAKE is not parametrised by a hash algorithm or if - * the hash algorithm is not set. - */ -static psa_algorithm_t psa_pake_cs_get_hash( - const psa_pake_cipher_suite_t *cipher_suite); - -/** Declare the hash algorithm for a PAKE cipher suite. - * - * This function overwrites any hash algorithm - * previously set in \p cipher_suite. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[out] cipher_suite The cipher suite structure to write to. - * \param hash The hash involved in the cipher suite. - * (`PSA_ALG_XXX` values of type ::psa_algorithm_t - * such that #PSA_ALG_IS_HASH(\c alg) is true.) - * If this is 0, the hash algorithm in - * \p cipher_suite becomes unspecified. - */ -static void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t hash); - -/** The type of the state data structure for PAKE operations. - * - * Before calling any function on a PAKE operation object, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_pake_operation_t operation; - * memset(&operation, 0, sizeof(operation)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_pake_operation_t operation = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_PAKE_OPERATION_INIT, - * for example: - * \code - * psa_pake_operation_t operation = PSA_PAKE_OPERATION_INIT; - * \endcode - * - Assign the result of the function psa_pake_operation_init() - * to the structure, for example: - * \code - * psa_pake_operation_t operation; - * operation = psa_pake_operation_init(); - * \endcode - * - * This is an implementation-defined \c struct. Applications should not - * make any assumptions about the content of this structure. - * Implementation details can change in future versions without notice. */ -typedef struct psa_pake_operation_s psa_pake_operation_t; - -/** The type of input values for PAKE operations. */ -typedef struct psa_crypto_driver_pake_inputs_s psa_crypto_driver_pake_inputs_t; - -/** The type of computation stage for J-PAKE operations. */ -typedef struct psa_jpake_computation_stage_s psa_jpake_computation_stage_t; - -/** Return an initial value for a PAKE operation object. - */ -static psa_pake_operation_t psa_pake_operation_init(void); - -/** Get the length of the password in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] password_len Password length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Password hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_password_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *password_len); - -/** Get the password from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] buffer Return buffer for password. - * \param buffer_size Size of the return buffer in bytes. - * \param[out] buffer_length Actual size of the password in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Password hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_password( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *buffer, size_t buffer_size, size_t *buffer_length); - -/** Get the length of the user id in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] user_len User id length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * User id hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_user_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *user_len); - -/** Get the length of the peer id in bytes from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] peer_len Peer id length. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Peer id hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_peer_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *peer_len); - -/** Get the user id from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] user_id User id. - * \param user_id_size Size of \p user_id in bytes. - * \param[out] user_id_len Size of the user id in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * User id hasn't been set yet. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p user_id is too small. - */ -psa_status_t psa_crypto_driver_pake_get_user( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *user_id, size_t user_id_size, size_t *user_id_len); - -/** Get the peer id from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] peer_id Peer id. - * \param peer_id_size Size of \p peer_id in bytes. - * \param[out] peer_id_length Size of the peer id in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Peer id hasn't been set yet. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p peer_id is too small. - */ -psa_status_t psa_crypto_driver_pake_get_peer( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *peer_id, size_t peer_id_size, size_t *peer_id_length); - -/** Get the cipher suite from given inputs. - * - * \param[in] inputs Operation inputs. - * \param[out] cipher_suite Return buffer for role. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * Cipher_suite hasn't been set yet. - */ -psa_status_t psa_crypto_driver_pake_get_cipher_suite( - const psa_crypto_driver_pake_inputs_t *inputs, - psa_pake_cipher_suite_t *cipher_suite); - -/** Set the session information for a password-authenticated key exchange. - * - * The sequence of operations to set up a password-authenticated key exchange - * is as follows: - * -# Allocate an operation object which will be passed to all the functions - * listed here. - * -# Initialize the operation object with one of the methods described in the - * documentation for #psa_pake_operation_t, e.g. - * #PSA_PAKE_OPERATION_INIT. - * -# Call psa_pake_setup() to specify the cipher suite. - * -# Call \c psa_pake_set_xxx() functions on the operation to complete the - * setup. The exact sequence of \c psa_pake_set_xxx() functions that needs - * to be called depends on the algorithm in use. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * A typical sequence of calls to perform a password-authenticated key - * exchange: - * -# Call psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to get the - * key share that needs to be sent to the peer. - * -# Call psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to provide - * the key share that was received from the peer. - * -# Depending on the algorithm additional calls to psa_pake_output() and - * psa_pake_input() might be necessary. - * -# Call psa_pake_get_implicit_key() for accessing the shared secret. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * If an error occurs at any step after a call to psa_pake_setup(), - * the operation will need to be reset by a call to psa_pake_abort(). The - * application may call psa_pake_abort() at any time after the operation - * has been initialized. - * - * After a successful call to psa_pake_setup(), the application must - * eventually terminate the operation. The following events terminate an - * operation: - * - A call to psa_pake_abort(). - * - A successful call to psa_pake_get_implicit_key(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized but not set up yet. - * \param[in] cipher_suite The cipher suite to use. (A cipher suite fully - * characterizes a PAKE algorithm and determines - * the algorithm as well.) - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The algorithm in \p cipher_suite is not a PAKE algorithm, or the - * PAKE primitive in \p cipher_suite is not compatible with the - * PAKE algorithm, or the hash algorithm in \p cipher_suite is invalid - * or not compatible with the PAKE algorithm and primitive. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The algorithm in \p cipher_suite is not a supported PAKE algorithm, - * or the PAKE primitive in \p cipher_suite is not supported or not - * compatible with the PAKE algorithm, or the hash algorithm in - * \p cipher_suite is not supported or not compatible with the PAKE - * algorithm and primitive. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_setup(psa_pake_operation_t *operation, - const psa_pake_cipher_suite_t *cipher_suite); - -/** Set the password for a password-authenticated key exchange from key ID. - * - * Call this function when the password, or a value derived from the password, - * is already present in the key store. - * - * \param[in,out] operation The operation object to set the password for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the password hasn't - * been set yet (psa_pake_set_password_key() - * hasn't been called yet). - * \param password Identifier of the key holding the password or a - * value derived from the password (eg. by a - * memory-hard function). It must remain valid - * until the operation terminates. It must be of - * type #PSA_KEY_TYPE_PASSWORD or - * #PSA_KEY_TYPE_PASSWORD_HASH. It has to allow - * the usage #PSA_KEY_USAGE_DERIVE. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p password is not a valid key identifier. - * \retval #PSA_ERROR_NOT_PERMITTED - * The key does not have the #PSA_KEY_USAGE_DERIVE flag, or it does not - * permit the \p operation's algorithm. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key type for \p password is not #PSA_KEY_TYPE_PASSWORD or - * #PSA_KEY_TYPE_PASSWORD_HASH, or \p password is not compatible with - * the \p operation's cipher suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The key type or key size of \p password is not supported with the - * \p operation's cipher suite. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must have been set up.), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_password_key(psa_pake_operation_t *operation, - mbedtls_svc_key_id_t password); - -/** Set the user ID for a password-authenticated key exchange. - * - * Call this function to set the user ID. For PAKE algorithms that associate a - * user identifier with each side of the session you need to call - * psa_pake_set_peer() as well. For PAKE algorithms that associate a single - * user identifier with the session, call psa_pake_set_user() only. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to set the user ID for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the user ID hasn't - * been set (psa_pake_set_user() hasn't been - * called yet). - * \param[in] user_id The user ID to authenticate with. - * \param user_id_len Size of the \p user_id buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p user_id is not valid for the \p operation's algorithm and cipher - * suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The value of \p user_id is not supported by the implementation. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_user(psa_pake_operation_t *operation, - const uint8_t *user_id, - size_t user_id_len); - -/** Set the peer ID for a password-authenticated key exchange. - * - * Call this function in addition to psa_pake_set_user() for PAKE algorithms - * that associate a user identifier with each side of the session. For PAKE - * algorithms that associate a single user identifier with the session, call - * psa_pake_set_user() only. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to set the peer ID for. It - * must have been set up by psa_pake_setup() and - * not yet in use (neither psa_pake_output() nor - * psa_pake_input() has been called yet). It must - * be on operation for which the peer ID hasn't - * been set (psa_pake_set_peer() hasn't been - * called yet). - * \param[in] peer_id The peer's ID to authenticate. - * \param peer_id_len Size of the \p peer_id buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p peer_id is not valid for the \p operation's algorithm and cipher - * suite. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The algorithm doesn't associate a second identity with the session. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * Calling psa_pake_set_peer() is invalid with the \p operation's - * algorithm, the operation state is not valid, or the library has not - * been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_peer(psa_pake_operation_t *operation, - const uint8_t *peer_id, - size_t peer_id_len); - -/** Set the application role for a password-authenticated key exchange. - * - * Not all PAKE algorithms need to differentiate the communicating entities. - * It is optional to call this function for PAKEs that don't require a role - * to be specified. For such PAKEs the application role parameter is ignored, - * or #PSA_PAKE_ROLE_NONE can be passed as \c role. - * - * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` - * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) - * for more information. - * - * \param[in,out] operation The operation object to specify the - * application's role for. It must have been set up - * by psa_pake_setup() and not yet in use (neither - * psa_pake_output() nor psa_pake_input() has been - * called yet). It must be on operation for which - * the application's role hasn't been specified - * (psa_pake_set_role() hasn't been called yet). - * \param role A value of type ::psa_pake_role_t indicating the - * application's role in the PAKE the algorithm - * that is being set up. For more information see - * the documentation of \c PSA_PAKE_ROLE_XXX - * constants. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The \p role is not a valid PAKE role in the \p operation’s algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The \p role for this algorithm is not supported or is not valid. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid, or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_set_role(psa_pake_operation_t *operation, - psa_pake_role_t role); - -/** Get output for a step of a password-authenticated key exchange. - * - * Depending on the algorithm being executed, you might need to call this - * function several times or you might not need to call this at all. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_pake_abort(). - * - * \param[in,out] operation Active PAKE operation. - * \param step The step of the algorithm for which the output is - * requested. - * \param[out] output Buffer where the output is to be written in the - * format appropriate for this \p step. Refer to - * the documentation of the individual - * \c PSA_PAKE_STEP_XXX constants for more - * information. - * \param output_size Size of the \p output buffer in bytes. This must - * be at least #PSA_PAKE_OUTPUT_SIZE(\c alg, \c - * primitive, \p output_step) where \c alg and - * \p primitive are the PAKE algorithm and primitive - * in the operation's cipher suite, and \p step is - * the output step. - * - * \param[out] output_length On success, the number of bytes of the returned - * output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p step is not compatible with the operation's algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p step is not supported with the operation's algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and fully set - * up, and this call must conform to the algorithm's requirements - * for ordering of input and output steps), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_output(psa_pake_operation_t *operation, - psa_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Provide input for a step of a password-authenticated key exchange. - * - * Depending on the algorithm being executed, you might need to call this - * function several times or you might not need to call this at all. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling psa_pake_abort(). - * - * \param[in,out] operation Active PAKE operation. - * \param step The step for which the input is provided. - * \param[in] input Buffer containing the input in the format - * appropriate for this \p step. Refer to the - * documentation of the individual - * \c PSA_PAKE_STEP_XXX constants for more - * information. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The verification fails for a #PSA_PAKE_STEP_ZK_PROOF input step. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p input_length is not compatible with the \p operation’s algorithm, - * or the \p input is not valid for the \p operation's algorithm, - * cipher suite or \p step. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p step p is not supported with the \p operation's algorithm, or the - * \p input is not supported for the \p operation's algorithm, cipher - * suite or \p step. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active, and fully set - * up, and this call must conform to the algorithm's requirements - * for ordering of input and output steps), or - * the library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_input(psa_pake_operation_t *operation, - psa_pake_step_t step, - const uint8_t *input, - size_t input_length); - -/** Get implicitly confirmed shared secret from a PAKE. - * - * At this point there is a cryptographic guarantee that only the authenticated - * party who used the same password is able to compute the key. But there is no - * guarantee that the peer is the party it claims to be and was able to do so. - * - * That is, the authentication is only implicit. Since the peer is not - * authenticated yet, no action should be taken yet that assumes that the peer - * is who it claims to be. For example, do not access restricted files on the - * peer's behalf until an explicit authentication has succeeded. - * - * This function can be called after the key exchange phase of the operation - * has completed. It imports the shared secret output of the PAKE into the - * provided derivation operation. The input step - * #PSA_KEY_DERIVATION_INPUT_SECRET is used when placing the shared key - * material in the key derivation operation. - * - * The exact sequence of calls to perform a password-authenticated key - * exchange depends on the algorithm in use. Refer to the documentation of - * individual PAKE algorithm types (`PSA_ALG_XXX` values of type - * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more - * information. - * - * When this function returns successfully, \p operation becomes inactive. - * If this function returns an error status, both \p operation - * and \c key_derivation operations enter an error state and must be aborted by - * calling psa_pake_abort() and psa_key_derivation_abort() respectively. - * - * \param[in,out] operation Active PAKE operation. - * \param[out] output A key derivation operation that is ready - * for an input step of type - * #PSA_KEY_DERIVATION_INPUT_SECRET. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * #PSA_KEY_DERIVATION_INPUT_SECRET is not compatible with the - * algorithm in the \p output key derivation operation. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Input from a PAKE is not supported by the algorithm in the \p output - * key derivation operation. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The PAKE operation state is not valid (it must be active, but beyond - * that validity is specific to the algorithm), or - * the library has not been previously initialized by psa_crypto_init(), - * or the state of \p output is not valid for - * the #PSA_KEY_DERIVATION_INPUT_SECRET step. This can happen if the - * step is out of order or the application has done this step already - * and it may not be repeated. - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_get_implicit_key(psa_pake_operation_t *operation, - psa_key_derivation_operation_t *output); - -psa_status_t psa_pake_derive_secret(psa_pake_operation_t *operation, - uint8_t *key_buf, - size_t key_length); - -/** Abort a PAKE operation. - * - * Aborting an operation frees all associated resources except for the \c - * operation structure itself. Once aborted, the operation object can be reused - * for another operation by calling psa_pake_setup() again. - * - * This function may be called at any time after the operation - * object has been initialized as described in #psa_pake_operation_t. - * - * In particular, calling psa_pake_abort() after the operation has been - * terminated by a call to psa_pake_abort() or psa_pake_get_implicit_key() - * is safe and has no effect. - * - * \param[in,out] operation The operation to abort. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_pake_abort(psa_pake_operation_t *operation); - -/**@}*/ - -/** A sufficient output buffer size for psa_pake_output(). - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_pake_output() will not fail due to an insufficient output buffer - * size. The actual size of the output might be smaller in any given call. - * - * See also #PSA_PAKE_OUTPUT_MAX_SIZE - * - * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_PAKE(\p alg) is true). - * \param primitive A primitive of type ::psa_pake_primitive_t that is - * compatible with algorithm \p alg. - * \param output_step A value of type ::psa_pake_step_t that is valid for the - * algorithm \p alg. - * \return A sufficient output buffer size for the specified - * PAKE algorithm, primitive, and output step. If the - * PAKE algorithm, primitive, or output step is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_PAKE_OUTPUT_SIZE(alg, primitive, output_step) \ - (alg == PSA_ALG_JPAKE && \ - primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ - PSA_ECC_FAMILY_SECP_R1, 256) ? \ - ( \ - output_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ - output_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ - 32 \ - ) : \ - 0) - -/** A sufficient input buffer size for psa_pake_input(). - * - * The value returned by this macro is guaranteed to be large enough for any - * valid input to psa_pake_input() in an operation with the specified - * parameters. - * - * See also #PSA_PAKE_INPUT_MAX_SIZE - * - * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_PAKE(\p alg) is true). - * \param primitive A primitive of type ::psa_pake_primitive_t that is - * compatible with algorithm \p alg. - * \param input_step A value of type ::psa_pake_step_t that is valid for the - * algorithm \p alg. - * \return A sufficient input buffer size for the specified - * input, cipher suite and algorithm. If the cipher suite, - * the input type or PAKE algorithm is not recognized, or - * the parameters are incompatible, return 0. - */ -#define PSA_PAKE_INPUT_SIZE(alg, primitive, input_step) \ - (alg == PSA_ALG_JPAKE && \ - primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ - PSA_ECC_FAMILY_SECP_R1, 256) ? \ - ( \ - input_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ - input_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ - 32 \ - ) : \ - 0) - -/** Output buffer size for psa_pake_output() for any of the supported PAKE - * algorithm and primitive suites and output step. - * - * This macro must expand to a compile-time constant integer. - * - * The value of this macro must be at least as large as the largest value - * returned by PSA_PAKE_OUTPUT_SIZE() - * - * See also #PSA_PAKE_OUTPUT_SIZE(\p alg, \p primitive, \p output_step). - */ -#define PSA_PAKE_OUTPUT_MAX_SIZE 65 - -/** Input buffer size for psa_pake_input() for any of the supported PAKE - * algorithm and primitive suites and input step. - * - * This macro must expand to a compile-time constant integer. - * - * The value of this macro must be at least as large as the largest value - * returned by PSA_PAKE_INPUT_SIZE() - * - * See also #PSA_PAKE_INPUT_SIZE(\p alg, \p primitive, \p output_step). - */ -#define PSA_PAKE_INPUT_MAX_SIZE 65 - -/** Returns a suitable initializer for a PAKE cipher suite object of type - * psa_pake_cipher_suite_t. - */ -#define PSA_PAKE_CIPHER_SUITE_INIT { PSA_ALG_NONE, 0, 0, 0, PSA_ALG_NONE } - -/** Returns a suitable initializer for a PAKE operation object of type - * psa_pake_operation_t. - */ -#define PSA_PAKE_OPERATION_INIT { 0, PSA_ALG_NONE, 0, PSA_PAKE_OPERATION_STAGE_SETUP, \ - { 0 }, { { 0 } } } - -struct psa_pake_cipher_suite_s { - psa_algorithm_t algorithm; - psa_pake_primitive_type_t type; - psa_pake_family_t family; - uint16_t bits; - psa_algorithm_t hash; -}; - -static inline psa_algorithm_t psa_pake_cs_get_algorithm( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->algorithm; -} - -static inline void psa_pake_cs_set_algorithm( - psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t algorithm) -{ - if (!PSA_ALG_IS_PAKE(algorithm)) { - cipher_suite->algorithm = 0; - } else { - cipher_suite->algorithm = algorithm; - } -} - -static inline psa_pake_primitive_t psa_pake_cs_get_primitive( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return PSA_PAKE_PRIMITIVE(cipher_suite->type, cipher_suite->family, - cipher_suite->bits); -} - -static inline void psa_pake_cs_set_primitive( - psa_pake_cipher_suite_t *cipher_suite, - psa_pake_primitive_t primitive) -{ - cipher_suite->type = (psa_pake_primitive_type_t) (primitive >> 24); - cipher_suite->family = (psa_pake_family_t) (0xFF & (primitive >> 16)); - cipher_suite->bits = (uint16_t) (0xFFFF & primitive); -} - -static inline psa_pake_family_t psa_pake_cs_get_family( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->family; -} - -static inline uint16_t psa_pake_cs_get_bits( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->bits; -} - -static inline psa_algorithm_t psa_pake_cs_get_hash( - const psa_pake_cipher_suite_t *cipher_suite) -{ - return cipher_suite->hash; -} - -static inline void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, - psa_algorithm_t hash) -{ - if (!PSA_ALG_IS_HASH(hash)) { - cipher_suite->hash = 0; - } else { - cipher_suite->hash = hash; - } -} - -struct psa_crypto_driver_pake_inputs_s { - uint8_t *MBEDTLS_PRIVATE(password); - size_t MBEDTLS_PRIVATE(password_len); - uint8_t *MBEDTLS_PRIVATE(user); - size_t MBEDTLS_PRIVATE(user_len); - uint8_t *MBEDTLS_PRIVATE(peer); - size_t MBEDTLS_PRIVATE(peer_len); - psa_key_attributes_t MBEDTLS_PRIVATE(attributes); - psa_pake_cipher_suite_t MBEDTLS_PRIVATE(cipher_suite); -}; - -typedef enum psa_crypto_driver_pake_step { - PSA_JPAKE_STEP_INVALID = 0, /* Invalid step */ - PSA_JPAKE_X1_STEP_KEY_SHARE = 1, /* Round 1: input/output key share (for ephemeral private key X1).*/ - PSA_JPAKE_X1_STEP_ZK_PUBLIC = 2, /* Round 1: input/output Schnorr NIZKP public key for the X1 key */ - PSA_JPAKE_X1_STEP_ZK_PROOF = 3, /* Round 1: input/output Schnorr NIZKP proof for the X1 key */ - PSA_JPAKE_X2_STEP_KEY_SHARE = 4, /* Round 1: input/output key share (for ephemeral private key X2).*/ - PSA_JPAKE_X2_STEP_ZK_PUBLIC = 5, /* Round 1: input/output Schnorr NIZKP public key for the X2 key */ - PSA_JPAKE_X2_STEP_ZK_PROOF = 6, /* Round 1: input/output Schnorr NIZKP proof for the X2 key */ - PSA_JPAKE_X2S_STEP_KEY_SHARE = 7, /* Round 2: output X2S key (our key) */ - PSA_JPAKE_X2S_STEP_ZK_PUBLIC = 8, /* Round 2: output Schnorr NIZKP public key for the X2S key (our key) */ - PSA_JPAKE_X2S_STEP_ZK_PROOF = 9, /* Round 2: output Schnorr NIZKP proof for the X2S key (our key) */ - PSA_JPAKE_X4S_STEP_KEY_SHARE = 10, /* Round 2: input X4S key (from peer) */ - PSA_JPAKE_X4S_STEP_ZK_PUBLIC = 11, /* Round 2: input Schnorr NIZKP public key for the X4S key (from peer) */ - PSA_JPAKE_X4S_STEP_ZK_PROOF = 12 /* Round 2: input Schnorr NIZKP proof for the X4S key (from peer) */ -} psa_crypto_driver_pake_step_t; - -typedef enum psa_jpake_round { - PSA_JPAKE_FIRST = 0, - PSA_JPAKE_SECOND = 1, - PSA_JPAKE_FINISHED = 2 -} psa_jpake_round_t; - -typedef enum psa_jpake_io_mode { - PSA_JPAKE_INPUT = 0, - PSA_JPAKE_OUTPUT = 1 -} psa_jpake_io_mode_t; - -struct psa_jpake_computation_stage_s { - /* The J-PAKE round we are currently on */ - psa_jpake_round_t MBEDTLS_PRIVATE(round); - /* The 'mode' we are currently in (inputting or outputting) */ - psa_jpake_io_mode_t MBEDTLS_PRIVATE(io_mode); - /* The number of completed inputs so far this round */ - uint8_t MBEDTLS_PRIVATE(inputs); - /* The number of completed outputs so far this round */ - uint8_t MBEDTLS_PRIVATE(outputs); - /* The next expected step (KEY_SHARE, ZK_PUBLIC or ZK_PROOF) */ - psa_pake_step_t MBEDTLS_PRIVATE(step); -}; - -#define PSA_JPAKE_EXPECTED_INPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ - ((round) == PSA_JPAKE_FIRST ? 2 : 1)) -#define PSA_JPAKE_EXPECTED_OUTPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ - ((round) == PSA_JPAKE_FIRST ? 2 : 1)) - -struct psa_pake_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - /* Algorithm of the PAKE operation */ - psa_algorithm_t MBEDTLS_PRIVATE(alg); - /* A primitive of type compatible with algorithm */ - psa_pake_primitive_t MBEDTLS_PRIVATE(primitive); - /* Stage of the PAKE operation: waiting for the setup, collecting inputs - * or computing. */ - uint8_t MBEDTLS_PRIVATE(stage); - /* Holds computation stage of the PAKE algorithms. */ - union { - uint8_t MBEDTLS_PRIVATE(dummy); -#if defined(PSA_WANT_ALG_JPAKE) - psa_jpake_computation_stage_t MBEDTLS_PRIVATE(jpake); -#endif - } MBEDTLS_PRIVATE(computation_stage); - union { - psa_driver_pake_context_t MBEDTLS_PRIVATE(ctx); - psa_crypto_driver_pake_inputs_t MBEDTLS_PRIVATE(inputs); - } MBEDTLS_PRIVATE(data); -}; - -static inline struct psa_pake_cipher_suite_s psa_pake_cipher_suite_init(void) -{ - const struct psa_pake_cipher_suite_s v = PSA_PAKE_CIPHER_SUITE_INIT; - return v; -} - -static inline struct psa_pake_operation_s psa_pake_operation_init(void) -{ - const struct psa_pake_operation_s v = PSA_PAKE_OPERATION_INIT; - return v; -} - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_EXTRA_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_extra.h + * + * \brief PSA cryptography module: Mbed TLS vendor extensions + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * This file is reserved for vendor-specific definitions. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_extra.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_extra.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_EXTRA_H +#define PSA_CRYPTO_EXTRA_H +#include "mbedtls/private_access.h" + +#include "crypto_types.h" +#include "crypto_compat.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* UID for secure storage seed */ +#define PSA_CRYPTO_ITS_RANDOM_SEED_UID 0xFFFFFF52 + +/* See mbedtls_config.h for definition */ +#if !defined(MBEDTLS_PSA_KEY_SLOT_COUNT) +#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 +#endif + +/** \addtogroup attributes + * @{ + */ + +/** \brief Declare the enrollment algorithm for a key. + * + * An operation on a key may indifferently use the algorithm set with + * psa_set_key_algorithm() or with this function. + * + * \param[out] attributes The attribute structure to write to. + * \param alg2 A second algorithm that the key may be used + * for, in addition to the algorithm set with + * psa_set_key_algorithm(). + * + * \warning Setting an enrollment algorithm is not recommended, because + * using the same key with different algorithms can allow some + * attacks based on arithmetic relations between different + * computations made with the same key, or can escalate harmless + * side channels into exploitable ones. Use this function only + * if it is necessary to support a protocol for which it has been + * verified that the usage of the key with multiple algorithms + * is safe. + */ +static inline void psa_set_key_enrollment_algorithm( + psa_key_attributes_t *attributes, + psa_algorithm_t alg2) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2) = alg2; +} + +/** Retrieve the enrollment algorithm policy from key attributes. + * + * \param[in] attributes The key attribute structure to query. + * + * \return The enrollment algorithm stored in the attribute structure. + */ +static inline psa_algorithm_t psa_get_key_enrollment_algorithm( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg2); +} + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + +/** Retrieve the slot number where a key is stored. + * + * A slot number is only defined for keys that are stored in a secure + * element. + * + * This information is only useful if the secure element is not entirely + * managed through the PSA Cryptography API. It is up to the secure + * element driver to decide how PSA slot numbers map to any other interface + * that the secure element may have. + * + * \param[in] attributes The key attribute structure to query. + * \param[out] slot_number On success, the slot number containing the key. + * + * \retval #PSA_SUCCESS + * The key is located in a secure element, and \p *slot_number + * indicates the slot number that contains it. + * \retval #PSA_ERROR_NOT_PERMITTED + * The caller is not permitted to query the slot number. + * Mbed TLS currently does not return this error. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key is not located in a secure element. + */ +psa_status_t psa_get_key_slot_number( + const psa_key_attributes_t *attributes, + psa_key_slot_number_t *slot_number); + +/** Choose the slot number where a key is stored. + * + * This function declares a slot number in the specified attribute + * structure. + * + * A slot number is only meaningful for keys that are stored in a secure + * element. It is up to the secure element driver to decide how PSA slot + * numbers map to any other interface that the secure element may have. + * + * \note Setting a slot number in key attributes for a key creation can + * cause the following errors when creating the key: + * - #PSA_ERROR_NOT_SUPPORTED if the selected secure element does + * not support choosing a specific slot number. + * - #PSA_ERROR_NOT_PERMITTED if the caller is not permitted to + * choose slot numbers in general or to choose this specific slot. + * - #PSA_ERROR_INVALID_ARGUMENT if the chosen slot number is not + * valid in general or not valid for this specific key. + * - #PSA_ERROR_ALREADY_EXISTS if there is already a key in the + * selected slot. + * + * \param[out] attributes The attribute structure to write to. + * \param slot_number The slot number to set. + */ +static inline void psa_set_key_slot_number( + psa_key_attributes_t *attributes, + psa_key_slot_number_t slot_number) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(flags) |= MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER; + attributes->MBEDTLS_PRIVATE(slot_number) = slot_number; +} + +/** Remove the slot number attribute from a key attribute structure. + * + * This function undoes the action of psa_set_key_slot_number(). + * + * \param[out] attributes The attribute structure to write to. + */ +static inline void psa_clear_key_slot_number( + psa_key_attributes_t *attributes) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(flags) &= + ~MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER; +} + +/** Register a key that is already present in a secure element. + * + * The key must be located in a secure element designated by the + * lifetime field in \p attributes, in the slot set with + * psa_set_key_slot_number() in the attribute structure. + * This function makes the key available through the key identifier + * specified in \p attributes. + * + * \param[in] attributes The attributes of the existing key. + * + * \retval #PSA_SUCCESS + * The key was successfully registered. + * Note that depending on the design of the driver, this may or may + * not guarantee that a key actually exists in the designated slot + * and is compatible with the specified attributes. + * \retval #PSA_ERROR_ALREADY_EXISTS + * There is already a key with the identifier specified in + * \p attributes. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The secure element driver for the specified lifetime does not + * support registering a key. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The identifier in \p attributes is invalid, namely the identifier is + * not in the user range, or + * \p attributes specifies a lifetime which is not located + * in a secure element, or no slot number is specified in \p attributes, + * or the specified slot number is not valid. + * \retval #PSA_ERROR_NOT_PERMITTED + * The caller is not authorized to register the specified key slot. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t mbedtls_psa_register_se_key( + const psa_key_attributes_t *attributes); + +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +/**@}*/ + +/** + * \brief Library deinitialization. + * + * This function clears all data associated with the PSA layer, + * including the whole key store. + * + * This is an Mbed TLS extension. + */ +void mbedtls_psa_crypto_free(void); + +/** \brief Statistics about + * resource consumption related to the PSA keystore. + * + * \note The content of this structure is not part of the stable API and ABI + * of Mbed TLS and may change arbitrarily from version to version. + */ +typedef struct mbedtls_psa_stats_s { + /** Number of slots containing key material for a volatile key. */ + size_t MBEDTLS_PRIVATE(volatile_slots); + /** Number of slots containing key material for a key which is in + * internal persistent storage. */ + size_t MBEDTLS_PRIVATE(persistent_slots); + /** Number of slots containing a reference to a key in a + * secure element. */ + size_t MBEDTLS_PRIVATE(external_slots); + /** Number of slots which are occupied, but do not contain + * key material yet. */ + size_t MBEDTLS_PRIVATE(half_filled_slots); + /** Number of slots that contain cache data. */ + size_t MBEDTLS_PRIVATE(cache_slots); + /** Number of slots that are not used for anything. */ + size_t MBEDTLS_PRIVATE(empty_slots); + /** Number of slots that are locked. */ + size_t MBEDTLS_PRIVATE(locked_slots); + /** Largest key id value among open keys in internal persistent storage. */ + psa_key_id_t MBEDTLS_PRIVATE(max_open_internal_key_id); + /** Largest key id value among open keys in secure elements. */ + psa_key_id_t MBEDTLS_PRIVATE(max_open_external_key_id); +} mbedtls_psa_stats_t; + +/** \brief Get statistics about + * resource consumption related to the PSA keystore. + * + * \note When Mbed TLS is built as part of a service, with isolation + * between the application and the keystore, the service may or + * may not expose this function. + */ +void mbedtls_psa_get_stats(mbedtls_psa_stats_t *stats); + +/** + * \brief Inject an initial entropy seed for the random generator into + * secure storage. + * + * This function injects data to be used as a seed for the random generator + * used by the PSA Crypto implementation. On devices that lack a trusted + * entropy source (preferably a hardware random number generator), + * the Mbed PSA Crypto implementation uses this value to seed its + * random generator. + * + * On devices without a trusted entropy source, this function must be + * called exactly once in the lifetime of the device. On devices with + * a trusted entropy source, calling this function is optional. + * In all cases, this function may only be called before calling any + * other function in the PSA Crypto API, including psa_crypto_init(). + * + * When this function returns successfully, it populates a file in + * persistent storage. Once the file has been created, this function + * can no longer succeed. + * + * If any error occurs, this function does not change the system state. + * You can call this function again after correcting the reason for the + * error if possible. + * + * \warning This function **can** fail! Callers MUST check the return status. + * + * \warning If you use this function, you should use it as part of a + * factory provisioning process. The value of the injected seed + * is critical to the security of the device. It must be + * *secret*, *unpredictable* and (statistically) *unique per device*. + * You should be generate it randomly using a cryptographically + * secure random generator seeded from trusted entropy sources. + * You should transmit it securely to the device and ensure + * that its value is not leaked or stored anywhere beyond the + * needs of transmitting it from the point of generation to + * the call of this function, and erase all copies of the value + * once this function returns. + * + * This is an Mbed TLS extension. + * + * \note This function is only available on the following platforms: + * * If the compile-time option MBEDTLS_PSA_INJECT_ENTROPY is enabled. + * Note that you must provide compatible implementations of + * mbedtls_nv_seed_read and mbedtls_nv_seed_write. + * * In a client-server integration of PSA Cryptography, on the client side, + * if the server supports this feature. + * \param[in] seed Buffer containing the seed value to inject. + * \param[in] seed_size Size of the \p seed buffer. + * The size of the seed in bytes must be greater + * or equal to both #MBEDTLS_ENTROPY_BLOCK_SIZE + * and the value of \c MBEDTLS_ENTROPY_MIN_PLATFORM + * in `library/entropy_poll.h` in the Mbed TLS source + * code. + * It must be less or equal to + * #MBEDTLS_ENTROPY_MAX_SEED_SIZE. + * + * \retval #PSA_SUCCESS + * The seed value was injected successfully. The random generator + * of the PSA Crypto implementation is now ready for use. + * You may now call psa_crypto_init() and use the PSA Crypto + * implementation. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p seed_size is out of range. + * \retval #PSA_ERROR_STORAGE_FAILURE + * There was a failure reading or writing from storage. + * \retval #PSA_ERROR_NOT_PERMITTED + * The library has already been initialized. It is no longer + * possible to call this function. + */ +psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, + size_t seed_size); + +/** \addtogroup crypto_types + * @{ + */ + +/** DSA public key. + * + * The import and export format is the + * representation of the public key `y = g^x mod p` as a big-endian byte + * string. The length of the byte string is the length of the base prime `p` + * in bytes. + */ +#define PSA_KEY_TYPE_DSA_PUBLIC_KEY ((psa_key_type_t) 0x4002) + +/** DSA key pair (private and public key). + * + * The import and export format is the + * representation of the private key `x` as a big-endian byte string. The + * length of the byte string is the private key size in bytes (leading zeroes + * are not stripped). + * + * Deterministic DSA key derivation with psa_generate_derived_key follows + * FIPS 186-4 §B.1.2: interpret the byte string as integer + * in big-endian order. Discard it if it is not in the range + * [0, *N* - 2] where *N* is the boundary of the private key domain + * (the prime *p* for Diffie-Hellman, the subprime *q* for DSA, + * or the order of the curve's base point for ECC). + * Add 1 to the resulting integer and use this as the private key *x*. + * + */ +#define PSA_KEY_TYPE_DSA_KEY_PAIR ((psa_key_type_t) 0x7002) + +/** Whether a key type is a DSA key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_DSA(type) \ + (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY) + +#define PSA_ALG_DSA_BASE ((psa_algorithm_t) 0x06000400) +/** DSA signature with hashing. + * + * This is the signature scheme defined by FIPS 186-4, + * with a random per-message secret number (*k*). + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding DSA signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_DSA(hash_alg) \ + (PSA_ALG_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +#define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t) 0x06000500) +#define PSA_ALG_DSA_DETERMINISTIC_FLAG PSA_ALG_ECDSA_DETERMINISTIC_FLAG +/** Deterministic DSA signature with hashing. + * + * This is the deterministic variant defined by RFC 6979 of + * the signature scheme defined by FIPS 186-4. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding DSA signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_DETERMINISTIC_DSA(hash_alg) \ + (PSA_ALG_DETERMINISTIC_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +#define PSA_ALG_IS_DSA(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_DSA_DETERMINISTIC_FLAG) == \ + PSA_ALG_DSA_BASE) +#define PSA_ALG_DSA_IS_DETERMINISTIC(alg) \ + (((alg) & PSA_ALG_DSA_DETERMINISTIC_FLAG) != 0) +#define PSA_ALG_IS_DETERMINISTIC_DSA(alg) \ + (PSA_ALG_IS_DSA(alg) && PSA_ALG_DSA_IS_DETERMINISTIC(alg)) +#define PSA_ALG_IS_RANDOMIZED_DSA(alg) \ + (PSA_ALG_IS_DSA(alg) && !PSA_ALG_DSA_IS_DETERMINISTIC(alg)) + + +/* We need to expand the sample definition of this macro from + * the API definition. */ +#undef PSA_ALG_IS_VENDOR_HASH_AND_SIGN +#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) \ + PSA_ALG_IS_DSA(alg) + +/**@}*/ + +/** \addtogroup attributes + * @{ + */ + +/** Custom Diffie-Hellman group. + * + * For keys of type #PSA_KEY_TYPE_DH_PUBLIC_KEY(#PSA_DH_FAMILY_CUSTOM) or + * #PSA_KEY_TYPE_DH_KEY_PAIR(#PSA_DH_FAMILY_CUSTOM), the group data comes + * from domain parameters set by psa_set_key_domain_parameters(). + */ +#define PSA_DH_FAMILY_CUSTOM ((psa_dh_family_t) 0x7e) + +/** PAKE operation stages. */ +#define PSA_PAKE_OPERATION_STAGE_SETUP 0 +#define PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS 1 +#define PSA_PAKE_OPERATION_STAGE_COMPUTATION 2 + +/** + * \brief Set domain parameters for a key. + * + * Some key types require additional domain parameters in addition to + * the key type identifier and the key size. Use this function instead + * of psa_set_key_type() when you need to specify domain parameters. + * + * The format for the required domain parameters varies based on the key type. + * + * - For RSA keys (#PSA_KEY_TYPE_RSA_PUBLIC_KEY or #PSA_KEY_TYPE_RSA_KEY_PAIR), + * the domain parameter data consists of the public exponent, + * represented as a big-endian integer with no leading zeros. + * This information is used when generating an RSA key pair. + * When importing a key, the public exponent is read from the imported + * key data and the exponent recorded in the attribute structure is ignored. + * As an exception, the public exponent 65537 is represented by an empty + * byte string. + * - For DSA keys (#PSA_KEY_TYPE_DSA_PUBLIC_KEY or #PSA_KEY_TYPE_DSA_KEY_PAIR), + * the `Dss-Params` format as defined by RFC 3279 §2.3.2. + * ``` + * Dss-Params ::= SEQUENCE { + * p INTEGER, + * q INTEGER, + * g INTEGER + * } + * ``` + * - For Diffie-Hellman key exchange keys + * (#PSA_KEY_TYPE_DH_PUBLIC_KEY(#PSA_DH_FAMILY_CUSTOM) or + * #PSA_KEY_TYPE_DH_KEY_PAIR(#PSA_DH_FAMILY_CUSTOM)), the + * `DomainParameters` format as defined by RFC 3279 §2.3.3. + * ``` + * DomainParameters ::= SEQUENCE { + * p INTEGER, -- odd prime, p=jq +1 + * g INTEGER, -- generator, g + * q INTEGER, -- factor of p-1 + * j INTEGER OPTIONAL, -- subgroup factor + * validationParams ValidationParams OPTIONAL + * } + * ValidationParams ::= SEQUENCE { + * seed BIT STRING, + * pgenCounter INTEGER + * } + * ``` + * + * \note This function may allocate memory or other resources. + * Once you have called this function on an attribute structure, + * you must call psa_reset_key_attributes() to free these resources. + * + * \note This is an experimental extension to the interface. It may change + * in future versions of the library. + * + * \param[in,out] attributes Attribute structure where the specified domain + * parameters will be stored. + * If this function fails, the content of + * \p attributes is not modified. + * \param type Key type (a \c PSA_KEY_TYPE_XXX value). + * \param[in] data Buffer containing the key domain parameters. + * The content of this buffer is interpreted + * according to \p type as described above. + * \param data_length Size of the \p data buffer in bytes. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, + psa_key_type_t type, + const uint8_t *data, + size_t data_length); + +/** + * \brief Get domain parameters for a key. + * + * Get the domain parameters for a key with this function, if any. The format + * of the domain parameters written to \p data is specified in the + * documentation for psa_set_key_domain_parameters(). + * + * \note This is an experimental extension to the interface. It may change + * in future versions of the library. + * + * \param[in] attributes The key attribute structure to query. + * \param[out] data On success, the key domain parameters. + * \param data_size Size of the \p data buffer in bytes. + * The buffer is guaranteed to be large + * enough if its size in bytes is at least + * the value given by + * PSA_KEY_DOMAIN_PARAMETERS_SIZE(). + * \param[out] data_length On success, the number of bytes + * that make up the key domain parameters data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL \emptydescription + */ +psa_status_t psa_get_key_domain_parameters( + const psa_key_attributes_t *attributes, + uint8_t *data, + size_t data_size, + size_t *data_length); + +/** Safe output buffer size for psa_get_key_domain_parameters(). + * + * This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * \warning This function may call its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \note This is an experimental extension to the interface. It may change + * in future versions of the library. + * + * \param key_type A supported key type. + * \param key_bits The size of the key in bits. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_get_key_domain_parameters() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not supported + * by the implementation, this macro shall return either a + * sensible size or 0. + * If the parameters are not valid, the + * return value is unspecified. + */ +#define PSA_KEY_DOMAIN_PARAMETERS_SIZE(key_type, key_bits) \ + (PSA_KEY_TYPE_IS_RSA(key_type) ? sizeof(int) : \ + PSA_KEY_TYPE_IS_DH(key_type) ? PSA_DH_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) : \ + PSA_KEY_TYPE_IS_DSA(key_type) ? PSA_DSA_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) : \ + 0) +#define PSA_DH_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) \ + (4 + (PSA_BITS_TO_BYTES(key_bits) + 5) * 3 /*without optional parts*/) +#define PSA_DSA_KEY_DOMAIN_PARAMETERS_SIZE(key_bits) \ + (4 + (PSA_BITS_TO_BYTES(key_bits) + 5) * 2 /*p, g*/ + 34 /*q*/) + +/**@}*/ + +/** \defgroup psa_tls_helpers TLS helper functions + * @{ + */ +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#include + +/** Convert an ECC curve identifier from the Mbed TLS encoding to PSA. + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param grpid An Mbed TLS elliptic curve identifier + * (`MBEDTLS_ECP_DP_xxx`). + * \param[out] bits On success, the bit size of the curve. + * + * \return The corresponding PSA elliptic curve identifier + * (`PSA_ECC_FAMILY_xxx`). + * \return \c 0 on failure (\p grpid is not recognized). + */ +psa_ecc_family_t mbedtls_ecc_group_to_psa(mbedtls_ecp_group_id grpid, + size_t *bits); + +/** Convert an ECC curve identifier from the PSA encoding to Mbed TLS. + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param curve A PSA elliptic curve identifier + * (`PSA_ECC_FAMILY_xxx`). + * \param bits The bit-length of a private key on \p curve. + * \param bits_is_sloppy If true, \p bits may be the bit-length rounded up + * to the nearest multiple of 8. This allows the caller + * to infer the exact curve from the length of a key + * which is supplied as a byte string. + * + * \return The corresponding Mbed TLS elliptic curve identifier + * (`MBEDTLS_ECP_DP_xxx`). + * \return #MBEDTLS_ECP_DP_NONE if \c curve is not recognized. + * \return #MBEDTLS_ECP_DP_NONE if \p bits is not + * correct for \p curve. + */ +mbedtls_ecp_group_id mbedtls_ecc_group_of_psa(psa_ecc_family_t curve, + size_t bits, + int bits_is_sloppy); +#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ + +/**@}*/ + +/** \defgroup psa_external_rng External random generator + * @{ + */ + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +/** External random generator function, implemented by the platform. + * + * When the compile-time option #MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is enabled, + * this function replaces Mbed TLS's entropy and DRBG modules for all + * random generation triggered via PSA crypto interfaces. + * + * \note This random generator must deliver random numbers with cryptographic + * quality and high performance. It must supply unpredictable numbers + * with a uniform distribution. The implementation of this function + * is responsible for ensuring that the random generator is seeded + * with sufficient entropy. If you have a hardware TRNG which is slow + * or delivers non-uniform output, declare it as an entropy source + * with mbedtls_entropy_add_source() instead of enabling this option. + * + * \param[in,out] context Pointer to the random generator context. + * This is all-bits-zero on the first call + * and preserved between successive calls. + * \param[out] output Output buffer. On success, this buffer + * contains random data with a uniform + * distribution. + * \param output_size The size of the \p output buffer in bytes. + * \param[out] output_length On success, set this value to \p output_size. + * + * \retval #PSA_SUCCESS + * Success. The output buffer contains \p output_size bytes of + * cryptographic-quality random data, and \c *output_length is + * set to \p output_size. + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY + * The random generator requires extra entropy and there is no + * way to obtain entropy under current environment conditions. + * This error should not happen under normal circumstances since + * this function is responsible for obtaining as much entropy as + * it needs. However implementations of this function may return + * #PSA_ERROR_INSUFFICIENT_ENTROPY if there is no way to obtain + * entropy without blocking indefinitely. + * \retval #PSA_ERROR_HARDWARE_FAILURE + * A failure of the random generator hardware that isn't covered + * by #PSA_ERROR_INSUFFICIENT_ENTROPY. + */ +psa_status_t mbedtls_psa_external_get_random( + mbedtls_psa_external_random_context_t *context, + uint8_t *output, size_t output_size, size_t *output_length); +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + +/**@}*/ + +/** \defgroup psa_builtin_keys Built-in keys + * @{ + */ + +/** The minimum value for a key identifier that is built into the + * implementation. + * + * The range of key identifiers from #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN + * to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX within the range from + * #PSA_KEY_ID_VENDOR_MIN and #PSA_KEY_ID_VENDOR_MAX and must not intersect + * with any other set of implementation-chosen key identifiers. + * + * This value is part of the library's ABI since changing it would invalidate + * the values of built-in key identifiers in applications. + */ +#define MBEDTLS_PSA_KEY_ID_BUILTIN_MIN ((psa_key_id_t) 0x7fff0000) + +/** The maximum value for a key identifier that is built into the + * implementation. + * + * See #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN for more information. + */ +#define MBEDTLS_PSA_KEY_ID_BUILTIN_MAX ((psa_key_id_t) 0x7fffefff) + +/** A slot number identifying a key in a driver. + * + * Values of this type are used to identify built-in keys. + */ +typedef uint64_t psa_drv_slot_number_t; + +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) +/** Test whether a key identifier belongs to the builtin key range. + * + * \param key_id Key identifier to test. + * + * \retval 1 + * The key identifier is a builtin key identifier. + * \retval 0 + * The key identifier is not a builtin key identifier. + */ +static inline int psa_key_id_is_builtin(psa_key_id_t key_id) +{ + return (key_id >= MBEDTLS_PSA_KEY_ID_BUILTIN_MIN) && + (key_id <= MBEDTLS_PSA_KEY_ID_BUILTIN_MAX); +} + +/** Platform function to obtain the location and slot number of a built-in key. + * + * An application-specific implementation of this function must be provided if + * #MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS is enabled. This would typically be provided + * as part of a platform's system image. + * + * #MBEDTLS_SVC_KEY_ID_GET_KEY_ID(\p key_id) needs to be in the range from + * #MBEDTLS_PSA_KEY_ID_BUILTIN_MIN to #MBEDTLS_PSA_KEY_ID_BUILTIN_MAX. + * + * In a multi-application configuration + * (\c MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER is defined), + * this function should check that #MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(\p key_id) + * is allowed to use the given key. + * + * \param key_id The key ID for which to retrieve the + * location and slot attributes. + * \param[out] lifetime On success, the lifetime associated with the key + * corresponding to \p key_id. Lifetime is a + * combination of which driver contains the key, + * and with what persistence level the key is + * intended to be used. If the platform + * implementation does not contain specific + * information about the intended key persistence + * level, the persistence level may be reported as + * #PSA_KEY_PERSISTENCE_DEFAULT. + * \param[out] slot_number On success, the slot number known to the driver + * registered at the lifetime location reported + * through \p lifetime which corresponds to the + * requested built-in key. + * + * \retval #PSA_SUCCESS + * The requested key identifier designates a built-in key. + * In a multi-application configuration, the requested owner + * is allowed to access it. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * The requested key identifier is not a built-in key which is known + * to this function. If a key exists in the key storage with this + * identifier, the data from the storage will be used. + * \return (any other error) + * Any other error is propagated to the function that requested the key. + * Common errors include: + * - #PSA_ERROR_NOT_PERMITTED: the key exists but the requested owner + * is not allowed to access it. + */ +psa_status_t mbedtls_psa_platform_get_builtin_key( + mbedtls_svc_key_id_t key_id, + psa_key_lifetime_t *lifetime, + psa_drv_slot_number_t *slot_number); +#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + +/** @} */ + +/** \addtogroup crypto_types + * @{ + */ + +#define PSA_ALG_CATEGORY_PAKE ((psa_algorithm_t) 0x0a000000) + +/** Whether the specified algorithm is a password-authenticated key exchange. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a password-authenticated key exchange (PAKE) + * algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_PAKE(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_PAKE) + +/** The Password-authenticated key exchange by juggling (J-PAKE) algorithm. + * + * This is J-PAKE as defined by RFC 8236, instantiated with the following + * parameters: + * + * - The group can be either an elliptic curve or defined over a finite field. + * - Schnorr NIZK proof as defined by RFC 8235 and using the same group as the + * J-PAKE algorithm. + * - A cryptographic hash function. + * + * To select these parameters and set up the cipher suite, call these functions + * in any order: + * + * \code + * psa_pake_cs_set_algorithm(cipher_suite, PSA_ALG_JPAKE); + * psa_pake_cs_set_primitive(cipher_suite, + * PSA_PAKE_PRIMITIVE(type, family, bits)); + * psa_pake_cs_set_hash(cipher_suite, hash); + * \endcode + * + * For more information on how to set a specific curve or field, refer to the + * documentation of the individual \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. + * + * After initializing a J-PAKE operation, call + * + * \code + * psa_pake_setup(operation, cipher_suite); + * psa_pake_set_user(operation, ...); + * psa_pake_set_peer(operation, ...); + * psa_pake_set_password_key(operation, ...); + * \endcode + * + * The password is provided as a key. This can be the password text itself, + * in an agreed character encoding, or some value derived from the password + * as required by a higher level protocol. + * + * (The implementation converts the key material to a number as described in + * Section 2.3.8 of _SEC 1: Elliptic Curve Cryptography_ + * (https://www.secg.org/sec1-v2.pdf), before reducing it modulo \c q. Here + * \c q is order of the group defined by the primitive set in the cipher suite. + * The \c psa_pake_set_password_key() function returns an error if the result + * of the reduction is 0.) + * + * The key exchange flow for J-PAKE is as follows: + * -# To get the first round data that needs to be sent to the peer, call + * \code + * // Get g1 + * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Get the ZKP public key for x1 + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Get the ZKP proof for x1 + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * // Get g2 + * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Get the ZKP public key for x2 + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Get the ZKP proof for x2 + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * \endcode + * -# To provide the first round data received from the peer to the operation, + * call + * \code + * // Set g3 + * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Set the ZKP public key for x3 + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Set the ZKP proof for x3 + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * // Set g4 + * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Set the ZKP public key for x4 + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Set the ZKP proof for x4 + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * \endcode + * -# To get the second round data that needs to be sent to the peer, call + * \code + * // Get A + * psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Get ZKP public key for x2*s + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Get ZKP proof for x2*s + * psa_pake_output(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * \endcode + * -# To provide the second round data received from the peer to the operation, + * call + * \code + * // Set B + * psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...); + * // Set ZKP public key for x4*s + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PUBLIC, ...); + * // Set ZKP proof for x4*s + * psa_pake_input(operation, #PSA_PAKE_STEP_ZK_PROOF, ...); + * \endcode + * -# To access the shared secret call + * \code + * // Get Ka=Kb=K + * psa_pake_get_implicit_key() + * \endcode + * + * For more information consult the documentation of the individual + * \c PSA_PAKE_STEP_XXX constants. + * + * At this point there is a cryptographic guarantee that only the authenticated + * party who used the same password is able to compute the key. But there is no + * guarantee that the peer is the party it claims to be and was able to do so. + * + * That is, the authentication is only implicit (the peer is not authenticated + * at this point, and no action should be taken that assume that they are - like + * for example accessing restricted files). + * + * To make the authentication explicit there are various methods, see Section 5 + * of RFC 8236 for two examples. + * + */ +#define PSA_ALG_JPAKE ((psa_algorithm_t) 0x0a000100) + +/** @} */ + +/** \defgroup pake Password-authenticated key exchange (PAKE) + * + * This is a proposed PAKE interface for the PSA Crypto API. It is not part of + * the official PSA Crypto API yet. + * + * \note The content of this section is not part of the stable API and ABI + * of Mbed TLS and may change arbitrarily from version to version. + * Same holds for the corresponding macros #PSA_ALG_CATEGORY_PAKE and + * #PSA_ALG_JPAKE. + * @{ + */ + +/** \brief Encoding of the application role of PAKE + * + * Encodes the application's role in the algorithm is being executed. For more + * information see the documentation of individual \c PSA_PAKE_ROLE_XXX + * constants. + */ +typedef uint8_t psa_pake_role_t; + +/** Encoding of input and output indicators for PAKE. + * + * Some PAKE algorithms need to exchange more data than just a single key share. + * This type is for encoding additional input and output data for such + * algorithms. + */ +typedef uint8_t psa_pake_step_t; + +/** Encoding of the type of the PAKE's primitive. + * + * Values defined by this standard will never be in the range 0x80-0xff. + * Vendors who define additional types must use an encoding in this range. + * + * For more information see the documentation of individual + * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. + */ +typedef uint8_t psa_pake_primitive_type_t; + +/** \brief Encoding of the family of the primitive associated with the PAKE. + * + * For more information see the documentation of individual + * \c PSA_PAKE_PRIMITIVE_TYPE_XXX constants. + */ +typedef uint8_t psa_pake_family_t; + +/** \brief Encoding of the primitive associated with the PAKE. + * + * For more information see the documentation of the #PSA_PAKE_PRIMITIVE macro. + */ +typedef uint32_t psa_pake_primitive_t; + +/** A value to indicate no role in a PAKE algorithm. + * This value can be used in a call to psa_pake_set_role() for symmetric PAKE + * algorithms which do not assign roles. + */ +#define PSA_PAKE_ROLE_NONE ((psa_pake_role_t) 0x00) + +/** The first peer in a balanced PAKE. + * + * Although balanced PAKE algorithms are symmetric, some of them needs an + * ordering of peers for the transcript calculations. If the algorithm does not + * need this, both #PSA_PAKE_ROLE_FIRST and #PSA_PAKE_ROLE_SECOND are + * accepted. + */ +#define PSA_PAKE_ROLE_FIRST ((psa_pake_role_t) 0x01) + +/** The second peer in a balanced PAKE. + * + * Although balanced PAKE algorithms are symmetric, some of them needs an + * ordering of peers for the transcript calculations. If the algorithm does not + * need this, either #PSA_PAKE_ROLE_FIRST or #PSA_PAKE_ROLE_SECOND are + * accepted. + */ +#define PSA_PAKE_ROLE_SECOND ((psa_pake_role_t) 0x02) + +/** The client in an augmented PAKE. + * + * Augmented PAKE algorithms need to differentiate between client and server. + */ +#define PSA_PAKE_ROLE_CLIENT ((psa_pake_role_t) 0x11) + +/** The server in an augmented PAKE. + * + * Augmented PAKE algorithms need to differentiate between client and server. + */ +#define PSA_PAKE_ROLE_SERVER ((psa_pake_role_t) 0x12) + +/** The PAKE primitive type indicating the use of elliptic curves. + * + * The values of the \c family and \c bits fields of the cipher suite identify a + * specific elliptic curve, using the same mapping that is used for ECC + * (::psa_ecc_family_t) keys. + * + * (Here \c family means the value returned by psa_pake_cs_get_family() and + * \c bits means the value returned by psa_pake_cs_get_bits().) + * + * Input and output during the operation can involve group elements and scalar + * values: + * -# The format for group elements is the same as for public keys on the + * specific curve would be. For more information, consult the documentation of + * psa_export_public_key(). + * -# The format for scalars is the same as for private keys on the specific + * curve would be. For more information, consult the documentation of + * psa_export_key(). + */ +#define PSA_PAKE_PRIMITIVE_TYPE_ECC ((psa_pake_primitive_type_t) 0x01) + +/** The PAKE primitive type indicating the use of Diffie-Hellman groups. + * + * The values of the \c family and \c bits fields of the cipher suite identify + * a specific Diffie-Hellman group, using the same mapping that is used for + * Diffie-Hellman (::psa_dh_family_t) keys. + * + * (Here \c family means the value returned by psa_pake_cs_get_family() and + * \c bits means the value returned by psa_pake_cs_get_bits().) + * + * Input and output during the operation can involve group elements and scalar + * values: + * -# The format for group elements is the same as for public keys on the + * specific group would be. For more information, consult the documentation of + * psa_export_public_key(). + * -# The format for scalars is the same as for private keys on the specific + * group would be. For more information, consult the documentation of + * psa_export_key(). + */ +#define PSA_PAKE_PRIMITIVE_TYPE_DH ((psa_pake_primitive_type_t) 0x02) + +/** Construct a PAKE primitive from type, family and bit-size. + * + * \param pake_type The type of the primitive + * (value of type ::psa_pake_primitive_type_t). + * \param pake_family The family of the primitive + * (the type and interpretation of this parameter depends + * on \p pake_type, for more information consult the + * documentation of individual ::psa_pake_primitive_type_t + * constants). + * \param pake_bits The bit-size of the primitive + * (Value of type \c size_t. The interpretation + * of this parameter depends on \p pake_family, for more + * information consult the documentation of individual + * ::psa_pake_primitive_type_t constants). + * + * \return The constructed primitive value of type ::psa_pake_primitive_t. + * Return 0 if the requested primitive can't be encoded as + * ::psa_pake_primitive_t. + */ +#define PSA_PAKE_PRIMITIVE(pake_type, pake_family, pake_bits) \ + ((pake_bits & 0xFFFF) != pake_bits) ? 0 : \ + ((psa_pake_primitive_t) (((pake_type) << 24 | \ + (pake_family) << 16) | (pake_bits))) + +/** The key share being sent to or received from the peer. + * + * The format for both input and output at this step is the same as for public + * keys on the group determined by the primitive (::psa_pake_primitive_t) would + * be. + * + * For more information on the format, consult the documentation of + * psa_export_public_key(). + * + * For information regarding how the group is determined, consult the + * documentation #PSA_PAKE_PRIMITIVE. + */ +#define PSA_PAKE_STEP_KEY_SHARE ((psa_pake_step_t) 0x01) + +/** A Schnorr NIZKP public key. + * + * This is the ephemeral public key in the Schnorr Non-Interactive + * Zero-Knowledge Proof (the value denoted by the letter 'V' in RFC 8235). + * + * The format for both input and output at this step is the same as for public + * keys on the group determined by the primitive (::psa_pake_primitive_t) would + * be. + * + * For more information on the format, consult the documentation of + * psa_export_public_key(). + * + * For information regarding how the group is determined, consult the + * documentation #PSA_PAKE_PRIMITIVE. + */ +#define PSA_PAKE_STEP_ZK_PUBLIC ((psa_pake_step_t) 0x02) + +/** A Schnorr NIZKP proof. + * + * This is the proof in the Schnorr Non-Interactive Zero-Knowledge Proof (the + * value denoted by the letter 'r' in RFC 8235). + * + * Both for input and output, the value at this step is an integer less than + * the order of the group selected in the cipher suite. The format depends on + * the group as well: + * + * - For Montgomery curves, the encoding is little endian. + * - For everything else the encoding is big endian (see Section 2.3.8 of + * _SEC 1: Elliptic Curve Cryptography_ at https://www.secg.org/sec1-v2.pdf). + * + * In both cases leading zeroes are allowed as long as the length in bytes does + * not exceed the byte length of the group order. + * + * For information regarding how the group is determined, consult the + * documentation #PSA_PAKE_PRIMITIVE. + */ +#define PSA_PAKE_STEP_ZK_PROOF ((psa_pake_step_t) 0x03) + +/** The type of the data structure for PAKE cipher suites. + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. + */ +typedef struct psa_pake_cipher_suite_s psa_pake_cipher_suite_t; + +/** Return an initial value for a PAKE cipher suite object. + */ +static psa_pake_cipher_suite_t psa_pake_cipher_suite_init(void); + +/** Retrieve the PAKE algorithm from a PAKE cipher suite. + * + * \param[in] cipher_suite The cipher suite structure to query. + * + * \return The PAKE algorithm stored in the cipher suite structure. + */ +static psa_algorithm_t psa_pake_cs_get_algorithm( + const psa_pake_cipher_suite_t *cipher_suite); + +/** Declare the PAKE algorithm for the cipher suite. + * + * This function overwrites any PAKE algorithm + * previously set in \p cipher_suite. + * + * \param[out] cipher_suite The cipher suite structure to write to. + * \param algorithm The PAKE algorithm to write. + * (`PSA_ALG_XXX` values of type ::psa_algorithm_t + * such that #PSA_ALG_IS_PAKE(\c alg) is true.) + * If this is 0, the PAKE algorithm in + * \p cipher_suite becomes unspecified. + */ +static void psa_pake_cs_set_algorithm(psa_pake_cipher_suite_t *cipher_suite, + psa_algorithm_t algorithm); + +/** Retrieve the primitive from a PAKE cipher suite. + * + * \param[in] cipher_suite The cipher suite structure to query. + * + * \return The primitive stored in the cipher suite structure. + */ +static psa_pake_primitive_t psa_pake_cs_get_primitive( + const psa_pake_cipher_suite_t *cipher_suite); + +/** Declare the primitive for a PAKE cipher suite. + * + * This function overwrites any primitive previously set in \p cipher_suite. + * + * \param[out] cipher_suite The cipher suite structure to write to. + * \param primitive The primitive to write. If this is 0, the + * primitive type in \p cipher_suite becomes + * unspecified. + */ +static void psa_pake_cs_set_primitive(psa_pake_cipher_suite_t *cipher_suite, + psa_pake_primitive_t primitive); + +/** Retrieve the PAKE family from a PAKE cipher suite. + * + * \param[in] cipher_suite The cipher suite structure to query. + * + * \return The PAKE family stored in the cipher suite structure. + */ +static psa_pake_family_t psa_pake_cs_get_family( + const psa_pake_cipher_suite_t *cipher_suite); + +/** Retrieve the PAKE primitive bit-size from a PAKE cipher suite. + * + * \param[in] cipher_suite The cipher suite structure to query. + * + * \return The PAKE primitive bit-size stored in the cipher suite structure. + */ +static uint16_t psa_pake_cs_get_bits( + const psa_pake_cipher_suite_t *cipher_suite); + +/** Retrieve the hash algorithm from a PAKE cipher suite. + * + * \param[in] cipher_suite The cipher suite structure to query. + * + * \return The hash algorithm stored in the cipher suite structure. The return + * value is 0 if the PAKE is not parametrised by a hash algorithm or if + * the hash algorithm is not set. + */ +static psa_algorithm_t psa_pake_cs_get_hash( + const psa_pake_cipher_suite_t *cipher_suite); + +/** Declare the hash algorithm for a PAKE cipher suite. + * + * This function overwrites any hash algorithm + * previously set in \p cipher_suite. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * \param[out] cipher_suite The cipher suite structure to write to. + * \param hash The hash involved in the cipher suite. + * (`PSA_ALG_XXX` values of type ::psa_algorithm_t + * such that #PSA_ALG_IS_HASH(\c alg) is true.) + * If this is 0, the hash algorithm in + * \p cipher_suite becomes unspecified. + */ +static void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, + psa_algorithm_t hash); + +/** The type of the state data structure for PAKE operations. + * + * Before calling any function on a PAKE operation object, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_pake_operation_t operation; + * memset(&operation, 0, sizeof(operation)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_pake_operation_t operation = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_PAKE_OPERATION_INIT, + * for example: + * \code + * psa_pake_operation_t operation = PSA_PAKE_OPERATION_INIT; + * \endcode + * - Assign the result of the function psa_pake_operation_init() + * to the structure, for example: + * \code + * psa_pake_operation_t operation; + * operation = psa_pake_operation_init(); + * \endcode + * + * This is an implementation-defined \c struct. Applications should not + * make any assumptions about the content of this structure. + * Implementation details can change in future versions without notice. */ +typedef struct psa_pake_operation_s psa_pake_operation_t; + +/** The type of input values for PAKE operations. */ +typedef struct psa_crypto_driver_pake_inputs_s psa_crypto_driver_pake_inputs_t; + +/** The type of computation stage for J-PAKE operations. */ +typedef struct psa_jpake_computation_stage_s psa_jpake_computation_stage_t; + +/** Return an initial value for a PAKE operation object. + */ +static psa_pake_operation_t psa_pake_operation_init(void); + +/** Get the length of the password in bytes from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] password_len Password length. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * Password hasn't been set yet. + */ +psa_status_t psa_crypto_driver_pake_get_password_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *password_len); + +/** Get the password from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] buffer Return buffer for password. + * \param buffer_size Size of the return buffer in bytes. + * \param[out] buffer_length Actual size of the password in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * Password hasn't been set yet. + */ +psa_status_t psa_crypto_driver_pake_get_password( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *buffer, size_t buffer_size, size_t *buffer_length); + +/** Get the length of the user id in bytes from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] user_len User id length. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * User id hasn't been set yet. + */ +psa_status_t psa_crypto_driver_pake_get_user_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *user_len); + +/** Get the length of the peer id in bytes from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] peer_len Peer id length. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * Peer id hasn't been set yet. + */ +psa_status_t psa_crypto_driver_pake_get_peer_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *peer_len); + +/** Get the user id from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] user_id User id. + * \param user_id_size Size of \p user_id in bytes. + * \param[out] user_id_len Size of the user id in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * User id hasn't been set yet. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p user_id is too small. + */ +psa_status_t psa_crypto_driver_pake_get_user( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *user_id, size_t user_id_size, size_t *user_id_len); + +/** Get the peer id from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] peer_id Peer id. + * \param peer_id_size Size of \p peer_id in bytes. + * \param[out] peer_id_length Size of the peer id in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * Peer id hasn't been set yet. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p peer_id is too small. + */ +psa_status_t psa_crypto_driver_pake_get_peer( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *peer_id, size_t peer_id_size, size_t *peer_id_length); + +/** Get the cipher suite from given inputs. + * + * \param[in] inputs Operation inputs. + * \param[out] cipher_suite Return buffer for role. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * Cipher_suite hasn't been set yet. + */ +psa_status_t psa_crypto_driver_pake_get_cipher_suite( + const psa_crypto_driver_pake_inputs_t *inputs, + psa_pake_cipher_suite_t *cipher_suite); + +/** Set the session information for a password-authenticated key exchange. + * + * The sequence of operations to set up a password-authenticated key exchange + * is as follows: + * -# Allocate an operation object which will be passed to all the functions + * listed here. + * -# Initialize the operation object with one of the methods described in the + * documentation for #psa_pake_operation_t, e.g. + * #PSA_PAKE_OPERATION_INIT. + * -# Call psa_pake_setup() to specify the cipher suite. + * -# Call \c psa_pake_set_xxx() functions on the operation to complete the + * setup. The exact sequence of \c psa_pake_set_xxx() functions that needs + * to be called depends on the algorithm in use. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * A typical sequence of calls to perform a password-authenticated key + * exchange: + * -# Call psa_pake_output(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to get the + * key share that needs to be sent to the peer. + * -# Call psa_pake_input(operation, #PSA_PAKE_STEP_KEY_SHARE, ...) to provide + * the key share that was received from the peer. + * -# Depending on the algorithm additional calls to psa_pake_output() and + * psa_pake_input() might be necessary. + * -# Call psa_pake_get_implicit_key() for accessing the shared secret. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * If an error occurs at any step after a call to psa_pake_setup(), + * the operation will need to be reset by a call to psa_pake_abort(). The + * application may call psa_pake_abort() at any time after the operation + * has been initialized. + * + * After a successful call to psa_pake_setup(), the application must + * eventually terminate the operation. The following events terminate an + * operation: + * - A call to psa_pake_abort(). + * - A successful call to psa_pake_get_implicit_key(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized but not set up yet. + * \param[in] cipher_suite The cipher suite to use. (A cipher suite fully + * characterizes a PAKE algorithm and determines + * the algorithm as well.) + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The algorithm in \p cipher_suite is not a PAKE algorithm, or the + * PAKE primitive in \p cipher_suite is not compatible with the + * PAKE algorithm, or the hash algorithm in \p cipher_suite is invalid + * or not compatible with the PAKE algorithm and primitive. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The algorithm in \p cipher_suite is not a supported PAKE algorithm, + * or the PAKE primitive in \p cipher_suite is not supported or not + * compatible with the PAKE algorithm, or the hash algorithm in + * \p cipher_suite is not supported or not compatible with the PAKE + * algorithm and primitive. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_setup(psa_pake_operation_t *operation, + const psa_pake_cipher_suite_t *cipher_suite); + +/** Set the password for a password-authenticated key exchange from key ID. + * + * Call this function when the password, or a value derived from the password, + * is already present in the key store. + * + * \param[in,out] operation The operation object to set the password for. It + * must have been set up by psa_pake_setup() and + * not yet in use (neither psa_pake_output() nor + * psa_pake_input() has been called yet). It must + * be on operation for which the password hasn't + * been set yet (psa_pake_set_password_key() + * hasn't been called yet). + * \param password Identifier of the key holding the password or a + * value derived from the password (eg. by a + * memory-hard function). It must remain valid + * until the operation terminates. It must be of + * type #PSA_KEY_TYPE_PASSWORD or + * #PSA_KEY_TYPE_PASSWORD_HASH. It has to allow + * the usage #PSA_KEY_USAGE_DERIVE. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p password is not a valid key identifier. + * \retval #PSA_ERROR_NOT_PERMITTED + * The key does not have the #PSA_KEY_USAGE_DERIVE flag, or it does not + * permit the \p operation's algorithm. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key type for \p password is not #PSA_KEY_TYPE_PASSWORD or + * #PSA_KEY_TYPE_PASSWORD_HASH, or \p password is not compatible with + * the \p operation's cipher suite. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The key type or key size of \p password is not supported with the + * \p operation's cipher suite. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must have been set up.), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_set_password_key(psa_pake_operation_t *operation, + mbedtls_svc_key_id_t password); + +/** Set the user ID for a password-authenticated key exchange. + * + * Call this function to set the user ID. For PAKE algorithms that associate a + * user identifier with each side of the session you need to call + * psa_pake_set_peer() as well. For PAKE algorithms that associate a single + * user identifier with the session, call psa_pake_set_user() only. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * \param[in,out] operation The operation object to set the user ID for. It + * must have been set up by psa_pake_setup() and + * not yet in use (neither psa_pake_output() nor + * psa_pake_input() has been called yet). It must + * be on operation for which the user ID hasn't + * been set (psa_pake_set_user() hasn't been + * called yet). + * \param[in] user_id The user ID to authenticate with. + * \param user_id_len Size of the \p user_id buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p user_id is not valid for the \p operation's algorithm and cipher + * suite. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The value of \p user_id is not supported by the implementation. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_set_user(psa_pake_operation_t *operation, + const uint8_t *user_id, + size_t user_id_len); + +/** Set the peer ID for a password-authenticated key exchange. + * + * Call this function in addition to psa_pake_set_user() for PAKE algorithms + * that associate a user identifier with each side of the session. For PAKE + * algorithms that associate a single user identifier with the session, call + * psa_pake_set_user() only. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * \param[in,out] operation The operation object to set the peer ID for. It + * must have been set up by psa_pake_setup() and + * not yet in use (neither psa_pake_output() nor + * psa_pake_input() has been called yet). It must + * be on operation for which the peer ID hasn't + * been set (psa_pake_set_peer() hasn't been + * called yet). + * \param[in] peer_id The peer's ID to authenticate. + * \param peer_id_len Size of the \p peer_id buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p peer_id is not valid for the \p operation's algorithm and cipher + * suite. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The algorithm doesn't associate a second identity with the session. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * Calling psa_pake_set_peer() is invalid with the \p operation's + * algorithm, the operation state is not valid, or the library has not + * been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_set_peer(psa_pake_operation_t *operation, + const uint8_t *peer_id, + size_t peer_id_len); + +/** Set the application role for a password-authenticated key exchange. + * + * Not all PAKE algorithms need to differentiate the communicating entities. + * It is optional to call this function for PAKEs that don't require a role + * to be specified. For such PAKEs the application role parameter is ignored, + * or #PSA_PAKE_ROLE_NONE can be passed as \c role. + * + * Refer to the documentation of individual PAKE algorithm types (`PSA_ALG_XXX` + * values of type ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) + * for more information. + * + * \param[in,out] operation The operation object to specify the + * application's role for. It must have been set up + * by psa_pake_setup() and not yet in use (neither + * psa_pake_output() nor psa_pake_input() has been + * called yet). It must be on operation for which + * the application's role hasn't been specified + * (psa_pake_set_role() hasn't been called yet). + * \param role A value of type ::psa_pake_role_t indicating the + * application's role in the PAKE the algorithm + * that is being set up. For more information see + * the documentation of \c PSA_PAKE_ROLE_XXX + * constants. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The \p role is not a valid PAKE role in the \p operation’s algorithm. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The \p role for this algorithm is not supported or is not valid. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid, or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_set_role(psa_pake_operation_t *operation, + psa_pake_role_t role); + +/** Get output for a step of a password-authenticated key exchange. + * + * Depending on the algorithm being executed, you might need to call this + * function several times or you might not need to call this at all. + * + * The exact sequence of calls to perform a password-authenticated key + * exchange depends on the algorithm in use. Refer to the documentation of + * individual PAKE algorithm types (`PSA_ALG_XXX` values of type + * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more + * information. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_pake_abort(). + * + * \param[in,out] operation Active PAKE operation. + * \param step The step of the algorithm for which the output is + * requested. + * \param[out] output Buffer where the output is to be written in the + * format appropriate for this \p step. Refer to + * the documentation of the individual + * \c PSA_PAKE_STEP_XXX constants for more + * information. + * \param output_size Size of the \p output buffer in bytes. This must + * be at least #PSA_PAKE_OUTPUT_SIZE(\c alg, \c + * primitive, \p output_step) where \c alg and + * \p primitive are the PAKE algorithm and primitive + * in the operation's cipher suite, and \p step is + * the output step. + * + * \param[out] output_length On success, the number of bytes of the returned + * output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p step is not compatible with the operation's algorithm. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p step is not supported with the operation's algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, and fully set + * up, and this call must conform to the algorithm's requirements + * for ordering of input and output steps), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_output(psa_pake_operation_t *operation, + psa_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Provide input for a step of a password-authenticated key exchange. + * + * Depending on the algorithm being executed, you might need to call this + * function several times or you might not need to call this at all. + * + * The exact sequence of calls to perform a password-authenticated key + * exchange depends on the algorithm in use. Refer to the documentation of + * individual PAKE algorithm types (`PSA_ALG_XXX` values of type + * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more + * information. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling psa_pake_abort(). + * + * \param[in,out] operation Active PAKE operation. + * \param step The step for which the input is provided. + * \param[in] input Buffer containing the input in the format + * appropriate for this \p step. Refer to the + * documentation of the individual + * \c PSA_PAKE_STEP_XXX constants for more + * information. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The verification fails for a #PSA_PAKE_STEP_ZK_PROOF input step. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p input_length is not compatible with the \p operation’s algorithm, + * or the \p input is not valid for the \p operation's algorithm, + * cipher suite or \p step. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p step p is not supported with the \p operation's algorithm, or the + * \p input is not supported for the \p operation's algorithm, cipher + * suite or \p step. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active, and fully set + * up, and this call must conform to the algorithm's requirements + * for ordering of input and output steps), or + * the library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_input(psa_pake_operation_t *operation, + psa_pake_step_t step, + const uint8_t *input, + size_t input_length); + +/** Get implicitly confirmed shared secret from a PAKE. + * + * At this point there is a cryptographic guarantee that only the authenticated + * party who used the same password is able to compute the key. But there is no + * guarantee that the peer is the party it claims to be and was able to do so. + * + * That is, the authentication is only implicit. Since the peer is not + * authenticated yet, no action should be taken yet that assumes that the peer + * is who it claims to be. For example, do not access restricted files on the + * peer's behalf until an explicit authentication has succeeded. + * + * This function can be called after the key exchange phase of the operation + * has completed. It imports the shared secret output of the PAKE into the + * provided derivation operation. The input step + * #PSA_KEY_DERIVATION_INPUT_SECRET is used when placing the shared key + * material in the key derivation operation. + * + * The exact sequence of calls to perform a password-authenticated key + * exchange depends on the algorithm in use. Refer to the documentation of + * individual PAKE algorithm types (`PSA_ALG_XXX` values of type + * ::psa_algorithm_t such that #PSA_ALG_IS_PAKE(\c alg) is true) for more + * information. + * + * When this function returns successfully, \p operation becomes inactive. + * If this function returns an error status, both \p operation + * and \c key_derivation operations enter an error state and must be aborted by + * calling psa_pake_abort() and psa_key_derivation_abort() respectively. + * + * \param[in,out] operation Active PAKE operation. + * \param[out] output A key derivation operation that is ready + * for an input step of type + * #PSA_KEY_DERIVATION_INPUT_SECRET. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * #PSA_KEY_DERIVATION_INPUT_SECRET is not compatible with the + * algorithm in the \p output key derivation operation. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Input from a PAKE is not supported by the algorithm in the \p output + * key derivation operation. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The PAKE operation state is not valid (it must be active, but beyond + * that validity is specific to the algorithm), or + * the library has not been previously initialized by psa_crypto_init(), + * or the state of \p output is not valid for + * the #PSA_KEY_DERIVATION_INPUT_SECRET step. This can happen if the + * step is out of order or the application has done this step already + * and it may not be repeated. + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_get_implicit_key(psa_pake_operation_t *operation, + psa_key_derivation_operation_t *output); + +psa_status_t psa_pake_derive_secret(psa_pake_operation_t *operation, + uint8_t *key_buf, + size_t key_length); + +/** Abort a PAKE operation. + * + * Aborting an operation frees all associated resources except for the \c + * operation structure itself. Once aborted, the operation object can be reused + * for another operation by calling psa_pake_setup() again. + * + * This function may be called at any time after the operation + * object has been initialized as described in #psa_pake_operation_t. + * + * In particular, calling psa_pake_abort() after the operation has been + * terminated by a call to psa_pake_abort() or psa_pake_get_implicit_key() + * is safe and has no effect. + * + * \param[in,out] operation The operation to abort. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_pake_abort(psa_pake_operation_t *operation); + +/**@}*/ + +/** A sufficient output buffer size for psa_pake_output(). + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_pake_output() will not fail due to an insufficient output buffer + * size. The actual size of the output might be smaller in any given call. + * + * See also #PSA_PAKE_OUTPUT_MAX_SIZE + * + * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_PAKE(\p alg) is true). + * \param primitive A primitive of type ::psa_pake_primitive_t that is + * compatible with algorithm \p alg. + * \param output_step A value of type ::psa_pake_step_t that is valid for the + * algorithm \p alg. + * \return A sufficient output buffer size for the specified + * PAKE algorithm, primitive, and output step. If the + * PAKE algorithm, primitive, or output step is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_PAKE_OUTPUT_SIZE(alg, primitive, output_step) \ + (alg == PSA_ALG_JPAKE && \ + primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ + PSA_ECC_FAMILY_SECP_R1, 256) ? \ + ( \ + output_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ + output_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ + 32 \ + ) : \ + 0) + +/** A sufficient input buffer size for psa_pake_input(). + * + * The value returned by this macro is guaranteed to be large enough for any + * valid input to psa_pake_input() in an operation with the specified + * parameters. + * + * See also #PSA_PAKE_INPUT_MAX_SIZE + * + * \param alg A PAKE algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_PAKE(\p alg) is true). + * \param primitive A primitive of type ::psa_pake_primitive_t that is + * compatible with algorithm \p alg. + * \param input_step A value of type ::psa_pake_step_t that is valid for the + * algorithm \p alg. + * \return A sufficient input buffer size for the specified + * input, cipher suite and algorithm. If the cipher suite, + * the input type or PAKE algorithm is not recognized, or + * the parameters are incompatible, return 0. + */ +#define PSA_PAKE_INPUT_SIZE(alg, primitive, input_step) \ + (alg == PSA_ALG_JPAKE && \ + primitive == PSA_PAKE_PRIMITIVE(PSA_PAKE_PRIMITIVE_TYPE_ECC, \ + PSA_ECC_FAMILY_SECP_R1, 256) ? \ + ( \ + input_step == PSA_PAKE_STEP_KEY_SHARE ? 65 : \ + input_step == PSA_PAKE_STEP_ZK_PUBLIC ? 65 : \ + 32 \ + ) : \ + 0) + +/** Output buffer size for psa_pake_output() for any of the supported PAKE + * algorithm and primitive suites and output step. + * + * This macro must expand to a compile-time constant integer. + * + * The value of this macro must be at least as large as the largest value + * returned by PSA_PAKE_OUTPUT_SIZE() + * + * See also #PSA_PAKE_OUTPUT_SIZE(\p alg, \p primitive, \p output_step). + */ +#define PSA_PAKE_OUTPUT_MAX_SIZE 65 + +/** Input buffer size for psa_pake_input() for any of the supported PAKE + * algorithm and primitive suites and input step. + * + * This macro must expand to a compile-time constant integer. + * + * The value of this macro must be at least as large as the largest value + * returned by PSA_PAKE_INPUT_SIZE() + * + * See also #PSA_PAKE_INPUT_SIZE(\p alg, \p primitive, \p output_step). + */ +#define PSA_PAKE_INPUT_MAX_SIZE 65 + +/** Returns a suitable initializer for a PAKE cipher suite object of type + * psa_pake_cipher_suite_t. + */ +#define PSA_PAKE_CIPHER_SUITE_INIT { PSA_ALG_NONE, 0, 0, 0, PSA_ALG_NONE } + +/** Returns a suitable initializer for a PAKE operation object of type + * psa_pake_operation_t. + */ +#define PSA_PAKE_OPERATION_INIT { 0, PSA_ALG_NONE, 0, PSA_PAKE_OPERATION_STAGE_SETUP, \ + { 0 }, { { 0 } } } + +struct psa_pake_cipher_suite_s { + psa_algorithm_t algorithm; + psa_pake_primitive_type_t type; + psa_pake_family_t family; + uint16_t bits; + psa_algorithm_t hash; +}; + +static inline psa_algorithm_t psa_pake_cs_get_algorithm( + const psa_pake_cipher_suite_t *cipher_suite) +{ + return cipher_suite->algorithm; +} + +static inline void psa_pake_cs_set_algorithm( + psa_pake_cipher_suite_t *cipher_suite, + psa_algorithm_t algorithm) +{ + if (!PSA_ALG_IS_PAKE(algorithm)) { + cipher_suite->algorithm = 0; + } else { + cipher_suite->algorithm = algorithm; + } +} + +static inline psa_pake_primitive_t psa_pake_cs_get_primitive( + const psa_pake_cipher_suite_t *cipher_suite) +{ + return PSA_PAKE_PRIMITIVE(cipher_suite->type, cipher_suite->family, + cipher_suite->bits); +} + +static inline void psa_pake_cs_set_primitive( + psa_pake_cipher_suite_t *cipher_suite, + psa_pake_primitive_t primitive) +{ + cipher_suite->type = (psa_pake_primitive_type_t) (primitive >> 24); + cipher_suite->family = (psa_pake_family_t) (0xFF & (primitive >> 16)); + cipher_suite->bits = (uint16_t) (0xFFFF & primitive); +} + +static inline psa_pake_family_t psa_pake_cs_get_family( + const psa_pake_cipher_suite_t *cipher_suite) +{ + return cipher_suite->family; +} + +static inline uint16_t psa_pake_cs_get_bits( + const psa_pake_cipher_suite_t *cipher_suite) +{ + return cipher_suite->bits; +} + +static inline psa_algorithm_t psa_pake_cs_get_hash( + const psa_pake_cipher_suite_t *cipher_suite) +{ + return cipher_suite->hash; +} + +static inline void psa_pake_cs_set_hash(psa_pake_cipher_suite_t *cipher_suite, + psa_algorithm_t hash) +{ + if (!PSA_ALG_IS_HASH(hash)) { + cipher_suite->hash = 0; + } else { + cipher_suite->hash = hash; + } +} + +struct psa_crypto_driver_pake_inputs_s { + uint8_t *MBEDTLS_PRIVATE(password); + size_t MBEDTLS_PRIVATE(password_len); + uint8_t *MBEDTLS_PRIVATE(user); + size_t MBEDTLS_PRIVATE(user_len); + uint8_t *MBEDTLS_PRIVATE(peer); + size_t MBEDTLS_PRIVATE(peer_len); + psa_key_attributes_t MBEDTLS_PRIVATE(attributes); + psa_pake_cipher_suite_t MBEDTLS_PRIVATE(cipher_suite); +}; + +typedef enum psa_crypto_driver_pake_step { + PSA_JPAKE_STEP_INVALID = 0, /* Invalid step */ + PSA_JPAKE_X1_STEP_KEY_SHARE = 1, /* Round 1: input/output key share (for ephemeral private key X1).*/ + PSA_JPAKE_X1_STEP_ZK_PUBLIC = 2, /* Round 1: input/output Schnorr NIZKP public key for the X1 key */ + PSA_JPAKE_X1_STEP_ZK_PROOF = 3, /* Round 1: input/output Schnorr NIZKP proof for the X1 key */ + PSA_JPAKE_X2_STEP_KEY_SHARE = 4, /* Round 1: input/output key share (for ephemeral private key X2).*/ + PSA_JPAKE_X2_STEP_ZK_PUBLIC = 5, /* Round 1: input/output Schnorr NIZKP public key for the X2 key */ + PSA_JPAKE_X2_STEP_ZK_PROOF = 6, /* Round 1: input/output Schnorr NIZKP proof for the X2 key */ + PSA_JPAKE_X2S_STEP_KEY_SHARE = 7, /* Round 2: output X2S key (our key) */ + PSA_JPAKE_X2S_STEP_ZK_PUBLIC = 8, /* Round 2: output Schnorr NIZKP public key for the X2S key (our key) */ + PSA_JPAKE_X2S_STEP_ZK_PROOF = 9, /* Round 2: output Schnorr NIZKP proof for the X2S key (our key) */ + PSA_JPAKE_X4S_STEP_KEY_SHARE = 10, /* Round 2: input X4S key (from peer) */ + PSA_JPAKE_X4S_STEP_ZK_PUBLIC = 11, /* Round 2: input Schnorr NIZKP public key for the X4S key (from peer) */ + PSA_JPAKE_X4S_STEP_ZK_PROOF = 12 /* Round 2: input Schnorr NIZKP proof for the X4S key (from peer) */ +} psa_crypto_driver_pake_step_t; + +typedef enum psa_jpake_round { + PSA_JPAKE_FIRST = 0, + PSA_JPAKE_SECOND = 1, + PSA_JPAKE_FINISHED = 2 +} psa_jpake_round_t; + +typedef enum psa_jpake_io_mode { + PSA_JPAKE_INPUT = 0, + PSA_JPAKE_OUTPUT = 1 +} psa_jpake_io_mode_t; + +struct psa_jpake_computation_stage_s { + /* The J-PAKE round we are currently on */ + psa_jpake_round_t MBEDTLS_PRIVATE(round); + /* The 'mode' we are currently in (inputting or outputting) */ + psa_jpake_io_mode_t MBEDTLS_PRIVATE(io_mode); + /* The number of completed inputs so far this round */ + uint8_t MBEDTLS_PRIVATE(inputs); + /* The number of completed outputs so far this round */ + uint8_t MBEDTLS_PRIVATE(outputs); + /* The next expected step (KEY_SHARE, ZK_PUBLIC or ZK_PROOF) */ + psa_pake_step_t MBEDTLS_PRIVATE(step); +}; + +#define PSA_JPAKE_EXPECTED_INPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ + ((round) == PSA_JPAKE_FIRST ? 2 : 1)) +#define PSA_JPAKE_EXPECTED_OUTPUTS(round) ((round) == PSA_JPAKE_FINISHED ? 0 : \ + ((round) == PSA_JPAKE_FIRST ? 2 : 1)) + +struct psa_pake_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_crypto_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + /* Algorithm of the PAKE operation */ + psa_algorithm_t MBEDTLS_PRIVATE(alg); + /* A primitive of type compatible with algorithm */ + psa_pake_primitive_t MBEDTLS_PRIVATE(primitive); + /* Stage of the PAKE operation: waiting for the setup, collecting inputs + * or computing. */ + uint8_t MBEDTLS_PRIVATE(stage); + /* Holds computation stage of the PAKE algorithms. */ + union { + uint8_t MBEDTLS_PRIVATE(dummy); +#if defined(PSA_WANT_ALG_JPAKE) + psa_jpake_computation_stage_t MBEDTLS_PRIVATE(jpake); +#endif + } MBEDTLS_PRIVATE(computation_stage); + union { + psa_driver_pake_context_t MBEDTLS_PRIVATE(ctx); + psa_crypto_driver_pake_inputs_t MBEDTLS_PRIVATE(inputs); + } MBEDTLS_PRIVATE(data); +}; + +static inline struct psa_pake_cipher_suite_s psa_pake_cipher_suite_init(void) +{ + const struct psa_pake_cipher_suite_s v = PSA_PAKE_CIPHER_SUITE_INIT; + return v; +} + +static inline struct psa_pake_operation_s psa_pake_operation_init(void) +{ + const struct psa_pake_operation_s v = PSA_PAKE_OPERATION_INIT; + return v; +} + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_EXTRA_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_legacy.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_legacy.h index 7a038d9..5317ce7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_legacy.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_legacy.h @@ -1,100 +1,100 @@ -/** - * \file psa/crypto_legacy.h - * - * \brief Add temporary suppport for deprecated symbols before they are - * removed from the library. - * - * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR and MBEDTLS_PSA_ACCEL_KEY_TYPE_xxx_KEY_PAIR - * symbols are deprecated. - * New symols add a suffix to that base name in order to clearly state what is - * the expected use for the key (use, import, export, generate, derive). - * Here we define some backward compatibility support for uses stil using - * the legacy symbols. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PSA_CRYPTO_LEGACY_H -#define MBEDTLS_PSA_CRYPTO_LEGACY_H - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) //no-check-names -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 -#endif -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) //no-check-names -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 -#endif -#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 -#endif -#endif - -#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) //no-check-names -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE -#endif -#endif - -#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR) //no-check-names -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT -#endif -#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE -#endif -#endif - -#endif /* MBEDTLS_PSA_CRYPTO_LEGACY_H */ +/** + * \file psa/crypto_legacy.h + * + * \brief Add temporary suppport for deprecated symbols before they are + * removed from the library. + * + * PSA_WANT_KEY_TYPE_xxx_KEY_PAIR and MBEDTLS_PSA_ACCEL_KEY_TYPE_xxx_KEY_PAIR + * symbols are deprecated. + * New symols add a suffix to that base name in order to clearly state what is + * the expected use for the key (use, import, export, generate, derive). + * Here we define some backward compatibility support for uses stil using + * the legacy symbols. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PSA_CRYPTO_LEGACY_H +#define MBEDTLS_PSA_CRYPTO_LEGACY_H + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) //no-check-names +#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE 1 +#endif +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) //no-check-names +#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT 1 +#endif +#if !defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE 1 +#endif +#endif + +#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) //no-check-names +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_BASIC +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_IMPORT +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_EXPORT +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_GENERATE +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR_DERIVE +#endif +#endif + +#if defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR) //no-check-names +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_BASIC +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_IMPORT +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_EXPORT +#endif +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE) +#define MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR_GENERATE +#endif +#endif + +#endif /* MBEDTLS_PSA_CRYPTO_LEGACY_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_platform.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_platform.h index ee41c89..355f71c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_platform.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_platform.h @@ -1,104 +1,104 @@ -/** - * \file psa/crypto_platform.h - * - * \brief PSA cryptography module: Mbed TLS platform definitions - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains platform-dependent type definitions. - * - * In implementations with isolation between the application and the - * cryptography module, implementers should take care to ensure that - * the definitions that are exposed to applications match what the - * module implements. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_PLATFORM_H -#define PSA_CRYPTO_PLATFORM_H -#include "mbedtls/private_access.h" - -/* - * Include the build-time configuration information file. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * PSA cryptography repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -/* PSA requires several types which C99 provides in stdint.h. */ -#include - -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - -/* Building for the PSA Crypto service on a PSA platform, a key owner is a PSA - * partition identifier. - * - * The function psa_its_identifier_of_slot() in psa_crypto_storage.c that - * translates a key identifier to a key storage file name assumes that - * mbedtls_key_owner_id_t is a 32-bit integer. This function thus needs - * reworking if mbedtls_key_owner_id_t is not defined as a 32-bit integer - * here anymore. - */ -typedef int32_t mbedtls_key_owner_id_t; - -/** Compare two key owner identifiers. - * - * \param id1 First key owner identifier. - * \param id2 Second key owner identifier. - * - * \return Non-zero if the two key owner identifiers are equal, zero otherwise. - */ -static inline int mbedtls_key_owner_id_equal(mbedtls_key_owner_id_t id1, - mbedtls_key_owner_id_t id2) -{ - return id1 == id2; -} - -#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/* - * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is being built for SPM - * (Secure Partition Manager) integration which separates the code into two - * parts: NSPE (Non-Secure Processing Environment) and SPE (Secure Processing - * Environment). When building for the SPE, an additional header file should be - * included. - */ -#if defined(MBEDTLS_PSA_CRYPTO_SPM) -#define PSA_CRYPTO_SECURE 1 -#include "crypto_spe.h" -#endif // MBEDTLS_PSA_CRYPTO_SPM - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -/** The type of the context passed to mbedtls_psa_external_get_random(). - * - * Mbed TLS initializes the context to all-bits-zero before calling - * mbedtls_psa_external_get_random() for the first time. - * - * The definition of this type in the Mbed TLS source code is for - * demonstration purposes. Implementers of mbedtls_psa_external_get_random() - * are expected to replace it with a custom definition. - */ -typedef struct { - uintptr_t MBEDTLS_PRIVATE(opaque)[2]; -} mbedtls_psa_external_random_context_t; -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -#endif /* PSA_CRYPTO_PLATFORM_H */ +/** + * \file psa/crypto_platform.h + * + * \brief PSA cryptography module: Mbed TLS platform definitions + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * This file contains platform-dependent type definitions. + * + * In implementations with isolation between the application and the + * cryptography module, implementers should take care to ensure that + * the definitions that are exposed to applications match what the + * module implements. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_PLATFORM_H +#define PSA_CRYPTO_PLATFORM_H +#include "mbedtls/private_access.h" + +/* + * Include the build-time configuration information file. Here, we do not + * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which + * is basically just an alias to it. This is to ease the maintenance of the + * PSA cryptography repository which has a different build system and + * configuration. + */ +#include "psa/build_info.h" + +/* PSA requires several types which C99 provides in stdint.h. */ +#include + +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + +/* Building for the PSA Crypto service on a PSA platform, a key owner is a PSA + * partition identifier. + * + * The function psa_its_identifier_of_slot() in psa_crypto_storage.c that + * translates a key identifier to a key storage file name assumes that + * mbedtls_key_owner_id_t is a 32-bit integer. This function thus needs + * reworking if mbedtls_key_owner_id_t is not defined as a 32-bit integer + * here anymore. + */ +typedef int32_t mbedtls_key_owner_id_t; + +/** Compare two key owner identifiers. + * + * \param id1 First key owner identifier. + * \param id2 Second key owner identifier. + * + * \return Non-zero if the two key owner identifiers are equal, zero otherwise. + */ +static inline int mbedtls_key_owner_id_equal(mbedtls_key_owner_id_t id1, + mbedtls_key_owner_id_t id2) +{ + return id1 == id2; +} + +#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ + +/* + * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is being built for SPM + * (Secure Partition Manager) integration which separates the code into two + * parts: NSPE (Non-Secure Processing Environment) and SPE (Secure Processing + * Environment). When building for the SPE, an additional header file should be + * included. + */ +#if defined(MBEDTLS_PSA_CRYPTO_SPM) +#define PSA_CRYPTO_SECURE 1 +#include "crypto_spe.h" +#endif // MBEDTLS_PSA_CRYPTO_SPM + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +/** The type of the context passed to mbedtls_psa_external_get_random(). + * + * Mbed TLS initializes the context to all-bits-zero before calling + * mbedtls_psa_external_get_random() for the first time. + * + * The definition of this type in the Mbed TLS source code is for + * demonstration purposes. Implementers of mbedtls_psa_external_get_random() + * are expected to replace it with a custom definition. + */ +typedef struct { + uintptr_t MBEDTLS_PRIVATE(opaque)[2]; +} mbedtls_psa_external_random_context_t; +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + +#endif /* PSA_CRYPTO_PLATFORM_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_se_driver.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_se_driver.h index f39e229..30677e7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_se_driver.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_se_driver.h @@ -1,1395 +1,1395 @@ -/** - * \file psa/crypto_se_driver.h - * \brief PSA external cryptoprocessor driver module - * - * This header declares types and function signatures for cryptography - * drivers that access key material via opaque references. - * This is meant for cryptoprocessors that have a separate key storage from the - * space in which the PSA Crypto implementation runs, typically secure - * elements (SEs). - * - * This file is part of the PSA Crypto Driver HAL (hardware abstraction layer), - * containing functions for driver developers to implement to enable hardware - * to be called in a standardized way by a PSA Cryptography API - * implementation. The functions comprising the driver HAL, which driver - * authors implement, are not intended to be called by application developers. - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef PSA_CRYPTO_SE_DRIVER_H -#define PSA_CRYPTO_SE_DRIVER_H -#include "mbedtls/private_access.h" - -#include "crypto_driver_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** \defgroup se_init Secure element driver initialization - */ -/**@{*/ - -/** \brief Driver context structure - * - * Driver functions receive a pointer to this structure. - * Each registered driver has one instance of this structure. - * - * Implementations must include the fields specified here and - * may include other fields. - */ -typedef struct { - /** A read-only pointer to the driver's persistent data. - * - * Drivers typically use this persistent data to keep track of - * which slot numbers are available. This is only a guideline: - * drivers may use the persistent data for any purpose, keeping - * in mind the restrictions on when the persistent data is saved - * to storage: the persistent data is only saved after calling - * certain functions that receive a writable pointer to the - * persistent data. - * - * The core allocates a memory buffer for the persistent data. - * The pointer is guaranteed to be suitably aligned for any data type, - * like a pointer returned by `malloc` (but the core can use any - * method to allocate the buffer, not necessarily `malloc`). - * - * The size of this buffer is in the \c persistent_data_size field of - * this structure. - * - * Before the driver is initialized for the first time, the content of - * the persistent data is all-bits-zero. After a driver upgrade, if the - * size of the persistent data has increased, the original data is padded - * on the right with zeros; if the size has decreased, the original data - * is truncated to the new size. - * - * This pointer is to read-only data. Only a few driver functions are - * allowed to modify the persistent data. These functions receive a - * writable pointer. These functions are: - * - psa_drv_se_t::p_init - * - psa_drv_se_key_management_t::p_allocate - * - psa_drv_se_key_management_t::p_destroy - * - * The PSA Cryptography core saves the persistent data from one - * session to the next. It does this before returning from API functions - * that call a driver method that is allowed to modify the persistent - * data, specifically: - * - psa_crypto_init() causes a call to psa_drv_se_t::p_init, and may call - * psa_drv_se_key_management_t::p_destroy to complete an action - * that was interrupted by a power failure. - * - Key creation functions cause a call to - * psa_drv_se_key_management_t::p_allocate, and may cause a call to - * psa_drv_se_key_management_t::p_destroy in case an error occurs. - * - psa_destroy_key() causes a call to - * psa_drv_se_key_management_t::p_destroy. - */ - const void *const MBEDTLS_PRIVATE(persistent_data); - - /** The size of \c persistent_data in bytes. - * - * This is always equal to the value of the `persistent_data_size` field - * of the ::psa_drv_se_t structure when the driver is registered. - */ - const size_t MBEDTLS_PRIVATE(persistent_data_size); - - /** Driver transient data. - * - * The core initializes this value to 0 and does not read or modify it - * afterwards. The driver may store whatever it wants in this field. - */ - uintptr_t MBEDTLS_PRIVATE(transient_data); -} psa_drv_se_context_t; - -/** \brief A driver initialization function. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param location The location value for which this driver - * is registered. The driver will be invoked - * for all keys whose lifetime is in this - * location. - * - * \retval #PSA_SUCCESS - * The driver is operational. - * The core will update the persistent data in storage. - * \return - * Any other return value prevents the driver from being used in - * this session. - * The core will NOT update the persistent data in storage. - */ -typedef psa_status_t (*psa_drv_se_init_t)(psa_drv_se_context_t *drv_context, - void *persistent_data, - psa_key_location_t location); - -#if defined(__DOXYGEN_ONLY__) || !defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* Mbed TLS with secure element support enabled defines this type in - * crypto_types.h because it is also visible to applications through an - * implementation-specific extension. - * For the PSA Cryptography specification, this type is only visible - * via crypto_se_driver.h. */ -/** An internal designation of a key slot between the core part of the - * PSA Crypto implementation and the driver. The meaning of this value - * is driver-dependent. */ -typedef uint64_t psa_key_slot_number_t; -#endif /* __DOXYGEN_ONLY__ || !MBEDTLS_PSA_CRYPTO_SE_C */ - -/**@}*/ - -/** \defgroup se_mac Secure Element Message Authentication Codes - * Generation and authentication of Message Authentication Codes (MACs) using - * a secure element can be done either as a single function call (via the - * `psa_drv_se_mac_generate_t` or `psa_drv_se_mac_verify_t` functions), or in - * parts using the following sequence: - * - `psa_drv_se_mac_setup_t` - * - `psa_drv_se_mac_update_t` - * - `psa_drv_se_mac_update_t` - * - ... - * - `psa_drv_se_mac_finish_t` or `psa_drv_se_mac_finish_verify_t` - * - * If a previously started secure element MAC operation needs to be terminated, - * it should be done so by the `psa_drv_se_mac_abort_t`. Failure to do so may - * result in allocated resources not being freed or in other undefined - * behavior. - */ -/**@{*/ -/** \brief A function that starts a secure element MAC operation for a PSA - * Crypto Driver implementation - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A structure that will contain the - * hardware-specific MAC context - * \param[in] key_slot The slot of the key to be used for the - * operation - * \param[in] algorithm The algorithm to be used to underly the MAC - * operation - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm); - -/** \brief A function that continues a previously started secure element MAC - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously-established MAC operation to be - * updated - * \param[in] p_input A buffer containing the message to be appended - * to the MAC operation - * \param[in] input_length The size in bytes of the input message buffer - */ -typedef psa_status_t (*psa_drv_se_mac_update_t)(void *op_context, - const uint8_t *p_input, - size_t input_length); - -/** \brief a function that completes a previously started secure element MAC - * operation by returning the resulting MAC. - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started MAC operation to be - * finished - * \param[out] p_mac A buffer where the generated MAC will be - * placed - * \param[in] mac_size The size in bytes of the buffer that has been - * allocated for the `output` buffer - * \param[out] p_mac_length After completion, will contain the number of - * bytes placed in the `p_mac` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_finish_t)(void *op_context, - uint8_t *p_mac, - size_t mac_size, - size_t *p_mac_length); - -/** \brief A function that completes a previously started secure element MAC - * operation by comparing the resulting MAC against a provided value - * - * \param[in,out] op_context A hardware-specific structure for the previously - * started MAC operation to be finished - * \param[in] p_mac The MAC value against which the resulting MAC - * will be compared against - * \param[in] mac_length The size in bytes of the value stored in `p_mac` - * - * \retval #PSA_SUCCESS - * The operation completed successfully and the MACs matched each - * other - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The operation completed successfully, but the calculated MAC did - * not match the provided MAC - */ -typedef psa_status_t (*psa_drv_se_mac_finish_verify_t)(void *op_context, - const uint8_t *p_mac, - size_t mac_length); - -/** \brief A function that aborts a previous started secure element MAC - * operation - * - * \param[in,out] op_context A hardware-specific structure for the previously - * started MAC operation to be aborted - */ -typedef psa_status_t (*psa_drv_se_mac_abort_t)(void *op_context); - -/** \brief A function that performs a secure element MAC operation in one - * command and returns the calculated MAC - * - * \param[in,out] drv_context The driver context structure. - * \param[in] p_input A buffer containing the message to be MACed - * \param[in] input_length The size in bytes of `p_input` - * \param[in] key_slot The slot of the key to be used - * \param[in] alg The algorithm to be used to underlie the MAC - * operation - * \param[out] p_mac A buffer where the generated MAC will be - * placed - * \param[in] mac_size The size in bytes of the `p_mac` buffer - * \param[out] p_mac_length After completion, will contain the number of - * bytes placed in the `output` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_mac_generate_t)(psa_drv_se_context_t *drv_context, - const uint8_t *p_input, - size_t input_length, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - uint8_t *p_mac, - size_t mac_size, - size_t *p_mac_length); - -/** \brief A function that performs a secure element MAC operation in one - * command and compares the resulting MAC against a provided value - * - * \param[in,out] drv_context The driver context structure. - * \param[in] p_input A buffer containing the message to be MACed - * \param[in] input_length The size in bytes of `input` - * \param[in] key_slot The slot of the key to be used - * \param[in] alg The algorithm to be used to underlie the MAC - * operation - * \param[in] p_mac The MAC value against which the resulting MAC will - * be compared against - * \param[in] mac_length The size in bytes of `mac` - * - * \retval #PSA_SUCCESS - * The operation completed successfully and the MACs matched each - * other - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The operation completed successfully, but the calculated MAC did - * not match the provided MAC - */ -typedef psa_status_t (*psa_drv_se_mac_verify_t)(psa_drv_se_context_t *drv_context, - const uint8_t *p_input, - size_t input_length, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_mac, - size_t mac_length); - -/** \brief A struct containing all of the function pointers needed to - * perform secure element MAC operations - * - * PSA Crypto API implementations should populate the table as appropriate - * upon startup. - * - * If one of the functions is not implemented (such as - * `psa_drv_se_mac_generate_t`), it should be set to NULL. - * - * Driver implementers should ensure that they implement all of the functions - * that make sense for their hardware, and that they provide a full solution - * (for example, if they support `p_setup`, they should also support - * `p_update` and at least one of `p_finish` or `p_finish_verify`). - * - */ -typedef struct { - /**The size in bytes of the hardware-specific secure element MAC context - * structure - */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a MAC setup operation - */ - psa_drv_se_mac_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that performs a MAC update operation - */ - psa_drv_se_mac_update_t MBEDTLS_PRIVATE(p_update); - /** Function that completes a MAC operation - */ - psa_drv_se_mac_finish_t MBEDTLS_PRIVATE(p_finish); - /** Function that completes a MAC operation with a verify check - */ - psa_drv_se_mac_finish_verify_t MBEDTLS_PRIVATE(p_finish_verify); - /** Function that aborts a previously started MAC operation - */ - psa_drv_se_mac_abort_t MBEDTLS_PRIVATE(p_abort); - /** Function that performs a MAC operation in one call - */ - psa_drv_se_mac_generate_t MBEDTLS_PRIVATE(p_mac); - /** Function that performs a MAC and verify operation in one call - */ - psa_drv_se_mac_verify_t MBEDTLS_PRIVATE(p_mac_verify); -} psa_drv_se_mac_t; -/**@}*/ - -/** \defgroup se_cipher Secure Element Symmetric Ciphers - * - * Encryption and Decryption using secure element keys in block modes other - * than ECB must be done in multiple parts, using the following flow: - * - `psa_drv_se_cipher_setup_t` - * - `psa_drv_se_cipher_set_iv_t` (optional depending upon block mode) - * - `psa_drv_se_cipher_update_t` - * - `psa_drv_se_cipher_update_t` - * - ... - * - `psa_drv_se_cipher_finish_t` - * - * If a previously started secure element Cipher operation needs to be - * terminated, it should be done so by the `psa_drv_se_cipher_abort_t`. Failure - * to do so may result in allocated resources not being freed or in other - * undefined behavior. - * - * In situations where a PSA Cryptographic API implementation is using a block - * mode not-supported by the underlying hardware or driver, it can construct - * the block mode itself, while calling the `psa_drv_se_cipher_ecb_t` function - * for the cipher operations. - */ -/**@{*/ - -/** \brief A function that provides the cipher setup function for a - * secure element driver - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A structure that will contain the - * hardware-specific cipher context. - * \param[in] key_slot The slot of the key to be used for the - * operation - * \param[in] algorithm The algorithm to be used in the cipher - * operation - * \param[in] direction Indicates whether the operation is an encrypt - * or decrypt - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - psa_encrypt_or_decrypt_t direction); - -/** \brief A function that sets the initialization vector (if - * necessary) for a secure element cipher operation - * - * Rationale: The `psa_se_cipher_*` operation in the PSA Cryptographic API has - * two IV functions: one to set the IV, and one to generate it internally. The - * generate function is not necessary for the drivers to implement as the PSA - * Crypto implementation can do the generation using its RNG features. - * - * \param[in,out] op_context A structure that contains the previously set up - * hardware-specific cipher context - * \param[in] p_iv A buffer containing the initialization vector - * \param[in] iv_length The size (in bytes) of the `p_iv` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_set_iv_t)(void *op_context, - const uint8_t *p_iv, - size_t iv_length); - -/** \brief A function that continues a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - * \param[in] p_input A buffer containing the data to be - * encrypted/decrypted - * \param[in] input_size The size in bytes of the buffer pointed to - * by `p_input` - * \param[out] p_output The caller-allocated buffer where the - * output will be placed - * \param[in] output_size The allocated size in bytes of the - * `p_output` buffer - * \param[out] p_output_length After completion, will contain the number - * of bytes placed in the `p_output` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_update_t)(void *op_context, - const uint8_t *p_input, - size_t input_size, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** \brief A function that completes a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - * \param[out] p_output The caller-allocated buffer where the output - * will be placed - * \param[in] output_size The allocated size in bytes of the `p_output` - * buffer - * \param[out] p_output_length After completion, will contain the number of - * bytes placed in the `p_output` buffer - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_finish_t)(void *op_context, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** \brief A function that aborts a previously started secure element cipher - * operation - * - * \param[in,out] op_context A hardware-specific structure for the - * previously started cipher operation - */ -typedef psa_status_t (*psa_drv_se_cipher_abort_t)(void *op_context); - -/** \brief A function that performs the ECB block mode for secure element - * cipher operations - * - * Note: this function should only be used with implementations that do not - * provide a needed higher-level operation. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot The slot of the key to be used for the operation - * \param[in] algorithm The algorithm to be used in the cipher operation - * \param[in] direction Indicates whether the operation is an encrypt or - * decrypt - * \param[in] p_input A buffer containing the data to be - * encrypted/decrypted - * \param[in] input_size The size in bytes of the buffer pointed to by - * `p_input` - * \param[out] p_output The caller-allocated buffer where the output - * will be placed - * \param[in] output_size The allocated size in bytes of the `p_output` - * buffer - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_cipher_ecb_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - psa_encrypt_or_decrypt_t direction, - const uint8_t *p_input, - size_t input_size, - uint8_t *p_output, - size_t output_size); - -/** - * \brief A struct containing all of the function pointers needed to implement - * cipher operations using secure elements. - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented (such as - * `psa_drv_se_cipher_ecb_t`), it should be set to NULL. - */ -typedef struct { - /** The size in bytes of the hardware-specific secure element cipher - * context structure - */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a cipher setup operation */ - psa_drv_se_cipher_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that sets a cipher IV (if necessary) */ - psa_drv_se_cipher_set_iv_t MBEDTLS_PRIVATE(p_set_iv); - /** Function that performs a cipher update operation */ - psa_drv_se_cipher_update_t MBEDTLS_PRIVATE(p_update); - /** Function that completes a cipher operation */ - psa_drv_se_cipher_finish_t MBEDTLS_PRIVATE(p_finish); - /** Function that aborts a cipher operation */ - psa_drv_se_cipher_abort_t MBEDTLS_PRIVATE(p_abort); - /** Function that performs ECB mode for a cipher operation - * (Danger: ECB mode should not be used directly by clients of the PSA - * Crypto Client API) - */ - psa_drv_se_cipher_ecb_t MBEDTLS_PRIVATE(p_ecb); -} psa_drv_se_cipher_t; - -/**@}*/ - -/** \defgroup se_asymmetric Secure Element Asymmetric Cryptography - * - * Since the amount of data that can (or should) be encrypted or signed using - * asymmetric keys is limited by the key size, asymmetric key operations using - * keys in a secure element must be done in single function calls. - */ -/**@{*/ - -/** - * \brief A function that signs a hash or short message with a private key in - * a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of an asymmetric key pair - * \param[in] alg A signature algorithm that is compatible - * with the type of `key` - * \param[in] p_hash The hash to sign - * \param[in] hash_length Size of the `p_hash` buffer in bytes - * \param[out] p_signature Buffer where the signature is to be written - * \param[in] signature_size Size of the `p_signature` buffer in bytes - * \param[out] p_signature_length On success, the number of bytes - * that make up the returned signature value - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_sign_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_hash, - size_t hash_length, - uint8_t *p_signature, - size_t signature_size, - size_t *p_signature_length); - -/** - * \brief A function that verifies the signature a hash or short message using - * an asymmetric public key in a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of a public key or an asymmetric key - * pair - * \param[in] alg A signature algorithm that is compatible with - * the type of `key` - * \param[in] p_hash The hash whose signature is to be verified - * \param[in] hash_length Size of the `p_hash` buffer in bytes - * \param[in] p_signature Buffer containing the signature to verify - * \param[in] signature_length Size of the `p_signature` buffer in bytes - * - * \retval #PSA_SUCCESS - * The signature is valid. - */ -typedef psa_status_t (*psa_drv_se_asymmetric_verify_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_hash, - size_t hash_length, - const uint8_t *p_signature, - size_t signature_length); - -/** - * \brief A function that encrypts a short message with an asymmetric public - * key in a secure element - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of a public key or an asymmetric key - * pair - * \param[in] alg An asymmetric encryption algorithm that is - * compatible with the type of `key` - * \param[in] p_input The message to encrypt - * \param[in] input_length Size of the `p_input` buffer in bytes - * \param[in] p_salt A salt or label, if supported by the - * encryption algorithm - * If the algorithm does not support a - * salt, pass `NULL`. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass `NULL`. - * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param[in] salt_length Size of the `p_salt` buffer in bytes - * If `p_salt` is `NULL`, pass 0. - * \param[out] p_output Buffer where the encrypted message is to - * be written - * \param[in] output_size Size of the `p_output` buffer in bytes - * \param[out] p_output_length On success, the number of bytes that make up - * the returned output - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_encrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_input, - size_t input_length, - const uint8_t *p_salt, - size_t salt_length, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A function that decrypts a short message with an asymmetric private - * key in a secure element. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Key slot of an asymmetric key pair - * \param[in] alg An asymmetric encryption algorithm that is - * compatible with the type of `key` - * \param[in] p_input The message to decrypt - * \param[in] input_length Size of the `p_input` buffer in bytes - * \param[in] p_salt A salt or label, if supported by the - * encryption algorithm - * If the algorithm does not support a - * salt, pass `NULL`. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass `NULL`. - * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param[in] salt_length Size of the `p_salt` buffer in bytes - * If `p_salt` is `NULL`, pass 0. - * \param[out] p_output Buffer where the decrypted message is to - * be written - * \param[in] output_size Size of the `p_output` buffer in bytes - * \param[out] p_output_length On success, the number of bytes - * that make up the returned output - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_asymmetric_decrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t alg, - const uint8_t *p_input, - size_t input_length, - const uint8_t *p_salt, - size_t salt_length, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A struct containing all of the function pointers needed to implement - * asymmetric cryptographic operations using secure elements. - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that performs an asymmetric sign operation */ - psa_drv_se_asymmetric_sign_t MBEDTLS_PRIVATE(p_sign); - /** Function that performs an asymmetric verify operation */ - psa_drv_se_asymmetric_verify_t MBEDTLS_PRIVATE(p_verify); - /** Function that performs an asymmetric encrypt operation */ - psa_drv_se_asymmetric_encrypt_t MBEDTLS_PRIVATE(p_encrypt); - /** Function that performs an asymmetric decrypt operation */ - psa_drv_se_asymmetric_decrypt_t MBEDTLS_PRIVATE(p_decrypt); -} psa_drv_se_asymmetric_t; - -/**@}*/ - -/** \defgroup se_aead Secure Element Authenticated Encryption with Additional Data - * Authenticated Encryption with Additional Data (AEAD) operations with secure - * elements must be done in one function call. While this creates a burden for - * implementers as there must be sufficient space in memory for the entire - * message, it prevents decrypted data from being made available before the - * authentication operation is complete and the data is known to be authentic. - */ -/**@{*/ - -/** \brief A function that performs a secure element authenticated encryption - * operation - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Slot containing the key to use. - * \param[in] algorithm The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(`alg`) is true) - * \param[in] p_nonce Nonce or IV to use - * \param[in] nonce_length Size of the `p_nonce` buffer in bytes - * \param[in] p_additional_data Additional data that will be - * authenticated but not encrypted - * \param[in] additional_data_length Size of `p_additional_data` in bytes - * \param[in] p_plaintext Data that will be authenticated and - * encrypted - * \param[in] plaintext_length Size of `p_plaintext` in bytes - * \param[out] p_ciphertext Output buffer for the authenticated and - * encrypted data. The additional data is - * not part of this output. For algorithms - * where the encrypted data and the - * authentication tag are defined as - * separate outputs, the authentication - * tag is appended to the encrypted data. - * \param[in] ciphertext_size Size of the `p_ciphertext` buffer in - * bytes - * \param[out] p_ciphertext_length On success, the size of the output in - * the `p_ciphertext` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_aead_encrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - const uint8_t *p_nonce, - size_t nonce_length, - const uint8_t *p_additional_data, - size_t additional_data_length, - const uint8_t *p_plaintext, - size_t plaintext_length, - uint8_t *p_ciphertext, - size_t ciphertext_size, - size_t *p_ciphertext_length); - -/** A function that performs a secure element authenticated decryption operation - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key_slot Slot containing the key to use - * \param[in] algorithm The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(`alg`) is true) - * \param[in] p_nonce Nonce or IV to use - * \param[in] nonce_length Size of the `p_nonce` buffer in bytes - * \param[in] p_additional_data Additional data that has been - * authenticated but not encrypted - * \param[in] additional_data_length Size of `p_additional_data` in bytes - * \param[in] p_ciphertext Data that has been authenticated and - * encrypted. - * For algorithms where the encrypted data - * and the authentication tag are defined - * as separate inputs, the buffer must - * contain the encrypted data followed by - * the authentication tag. - * \param[in] ciphertext_length Size of `p_ciphertext` in bytes - * \param[out] p_plaintext Output buffer for the decrypted data - * \param[in] plaintext_size Size of the `p_plaintext` buffer in - * bytes - * \param[out] p_plaintext_length On success, the size of the output in - * the `p_plaintext` buffer - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_aead_decrypt_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - psa_algorithm_t algorithm, - const uint8_t *p_nonce, - size_t nonce_length, - const uint8_t *p_additional_data, - size_t additional_data_length, - const uint8_t *p_ciphertext, - size_t ciphertext_length, - uint8_t *p_plaintext, - size_t plaintext_size, - size_t *p_plaintext_length); - -/** - * \brief A struct containing all of the function pointers needed to implement - * secure element Authenticated Encryption with Additional Data operations - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that performs the AEAD encrypt operation */ - psa_drv_se_aead_encrypt_t MBEDTLS_PRIVATE(p_encrypt); - /** Function that performs the AEAD decrypt operation */ - psa_drv_se_aead_decrypt_t MBEDTLS_PRIVATE(p_decrypt); -} psa_drv_se_aead_t; -/**@}*/ - -/** \defgroup se_key_management Secure Element Key Management - * Currently, key management is limited to importing keys in the clear, - * destroying keys, and exporting keys in the clear. - * Whether a key may be exported is determined by the key policies in place - * on the key slot. - */ -/**@{*/ - -/** An enumeration indicating how a key is created. - */ -typedef enum { - PSA_KEY_CREATION_IMPORT, /**< During psa_import_key() */ - PSA_KEY_CREATION_GENERATE, /**< During psa_generate_key() */ - PSA_KEY_CREATION_DERIVE, /**< During psa_key_derivation_output_key() */ - PSA_KEY_CREATION_COPY, /**< During psa_copy_key() */ - -#ifndef __DOXYGEN_ONLY__ - /** A key is being registered with mbedtls_psa_register_se_key(). - * - * The core only passes this value to - * psa_drv_se_key_management_t::p_validate_slot_number, not to - * psa_drv_se_key_management_t::p_allocate. The call to - * `p_validate_slot_number` is not followed by any other call to the - * driver: the key is considered successfully registered if the call to - * `p_validate_slot_number` succeeds, or if `p_validate_slot_number` is - * null. - * - * With this creation method, the driver must return #PSA_SUCCESS if - * the given attributes are compatible with the existing key in the slot, - * and #PSA_ERROR_DOES_NOT_EXIST if the driver can determine that there - * is no key with the specified slot number. - * - * This is an Mbed TLS extension. - */ - PSA_KEY_CREATION_REGISTER, -#endif -} psa_key_creation_method_t; - -/** \brief A function that allocates a slot for a key. - * - * To create a key in a specific slot in a secure element, the core - * first calls this function to determine a valid slot number, - * then calls a function to create the key material in that slot. - * In nominal conditions (that is, if no error occurs), - * the effect of a call to a key creation function in the PSA Cryptography - * API with a lifetime that places the key in a secure element is the - * following: - * -# The core calls psa_drv_se_key_management_t::p_allocate - * (or in some implementations - * psa_drv_se_key_management_t::p_validate_slot_number). The driver - * selects (or validates) a suitable slot number given the key attributes - * and the state of the secure element. - * -# The core calls a key creation function in the driver. - * - * The key creation functions in the PSA Cryptography API are: - * - psa_import_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_IMPORT - * then a call to psa_drv_se_key_management_t::p_import. - * - psa_generate_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_GENERATE - * then a call to psa_drv_se_key_management_t::p_import. - * - psa_key_derivation_output_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_DERIVE - * then a call to psa_drv_se_key_derivation_t::p_derive. - * - psa_copy_key(), which causes - * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_COPY - * then a call to psa_drv_se_key_management_t::p_export. - * - * In case of errors, other behaviors are possible. - * - If the PSA Cryptography subsystem dies after the first step, - * for example because the device has lost power abruptly, - * the second step may never happen, or may happen after a reset - * and re-initialization. Alternatively, after a reset and - * re-initialization, the core may call - * psa_drv_se_key_management_t::p_destroy on the slot number that - * was allocated (or validated) instead of calling a key creation function. - * - If an error occurs, the core may call - * psa_drv_se_key_management_t::p_destroy on the slot number that - * was allocated (or validated) instead of calling a key creation function. - * - * Errors and system resets also have an impact on the driver's persistent - * data. If a reset happens before the overall key creation process is - * completed (before or after the second step above), it is unspecified - * whether the persistent data after the reset is identical to what it - * was before or after the call to `p_allocate` (or `p_validate_slot_number`). - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param[in] attributes Attributes of the key. - * \param method The way in which the key is being created. - * \param[out] key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * - * \retval #PSA_SUCCESS - * Success. - * The core will record \c *key_slot as the key slot where the key - * is stored and will update the persistent data in storage. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - */ -typedef psa_status_t (*psa_drv_se_allocate_key_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_key_slot_number_t *key_slot); - -/** \brief A function that determines whether a slot number is valid - * for a key. - * - * To create a key in a specific slot in a secure element, the core - * first calls this function to validate the choice of slot number, - * then calls a function to create the key material in that slot. - * See the documentation of #psa_drv_se_allocate_key_t for more details. - * - * As of the PSA Cryptography API specification version 1.0, there is no way - * for applications to trigger a call to this function. However some - * implementations offer the capability to create or declare a key in - * a specific slot via implementation-specific means, generally for the - * sake of initial device provisioning or onboarding. Such a mechanism may - * be added to a future version of the PSA Cryptography API specification. - * - * This function may update the driver's persistent data through - * \p persistent_data. The core will save the updated persistent data at the - * end of the key creation process. See the description of - * ::psa_drv_se_allocate_key_t for more information. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param[in] attributes Attributes of the key. - * \param method The way in which the key is being created. - * \param[in] key_slot Slot where the key is to be stored. - * - * \retval #PSA_SUCCESS - * The given slot number is valid for a key with the given - * attributes. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The given slot number is not valid for a key with the - * given attributes. This includes the case where the slot - * number is not valid at all. - * \retval #PSA_ERROR_ALREADY_EXISTS - * There is already a key with the specified slot number. - * Drivers may choose to return this error from the key - * creation function instead. - */ -typedef psa_status_t (*psa_drv_se_validate_slot_number_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_key_slot_number_t key_slot); - -/** \brief A function that imports a key into a secure element in binary format - * - * This function can support any output from psa_export_key(). Refer to the - * documentation of psa_export_key() for the format for each key type. - * - * \param[in,out] drv_context The driver context structure. - * \param key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * \param[in] attributes The key attributes, including the lifetime, - * the key type and the usage policy. - * Drivers should not access the key size stored - * in the attributes: it may not match the - * data passed in \p data. - * Drivers can call psa_get_key_lifetime(), - * psa_get_key_type(), - * psa_get_key_usage_flags() and - * psa_get_key_algorithm() to access this - * information. - * \param[in] data Buffer containing the key data. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] bits On success, the key size in bits. The driver - * must determine this value after parsing the - * key according to the key type. - * This value is not used if the function fails. - * - * \retval #PSA_SUCCESS - * Success. - */ -typedef psa_status_t (*psa_drv_se_import_key_t)( - psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - size_t *bits); - -/** - * \brief A function that destroys a secure element key and restore the slot to - * its default state - * - * This function destroys the content of the key from a secure element. - * Implementations shall make a best effort to ensure that any previous content - * of the slot is unrecoverable. - * - * This function returns the specified slot to its default state. - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] persistent_data A pointer to the persistent data - * that allows writing. - * \param key_slot The key slot to erase. - * - * \retval #PSA_SUCCESS - * The slot's content, if any, has been erased. - */ -typedef psa_status_t (*psa_drv_se_destroy_key_t)( - psa_drv_se_context_t *drv_context, - void *persistent_data, - psa_key_slot_number_t key_slot); - -/** - * \brief A function that exports a secure element key in binary format - * - * The output of this function can be passed to psa_import_key() to - * create an equivalent object. - * - * If a key is created with `psa_import_key()` and then exported with - * this function, it is not guaranteed that the resulting data is - * identical: the implementation may choose a different representation - * of the same key if the format permits it. - * - * This function should generate output in the same format that - * `psa_export_key()` does. Refer to the - * documentation of `psa_export_key()` for the format for each key type. - * - * \param[in,out] drv_context The driver context structure. - * \param[in] key Slot whose content is to be exported. This must - * be an occupied key slot. - * \param[out] p_data Buffer where the key data is to be written. - * \param[in] data_size Size of the `p_data` buffer in bytes. - * \param[out] p_data_length On success, the number of bytes - * that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -typedef psa_status_t (*psa_drv_se_export_key_t)(psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key, - uint8_t *p_data, - size_t data_size, - size_t *p_data_length); - -/** - * \brief A function that generates a symmetric or asymmetric key on a secure - * element - * - * If the key type \c type recorded in \p attributes - * is asymmetric (#PSA_KEY_TYPE_IS_ASYMMETRIC(\c type) = 1), - * the driver may export the public key at the time of generation, - * in the format documented for psa_export_public_key() by writing it - * to the \p pubkey buffer. - * This is optional, intended for secure elements that output the - * public key at generation time and that cannot export the public key - * later. Drivers that do not need this feature should leave - * \p *pubkey_length set to 0 and should - * implement the psa_drv_key_management_t::p_export_public function. - * Some implementations do not support this feature, in which case - * \p pubkey is \c NULL and \p pubkey_size is 0. - * - * \param[in,out] drv_context The driver context structure. - * \param key_slot Slot where the key will be stored. - * This must be a valid slot for a key of the - * chosen type. It must be unoccupied. - * \param[in] attributes The key attributes, including the lifetime, - * the key type and size, and the usage policy. - * Drivers can call psa_get_key_lifetime(), - * psa_get_key_type(), psa_get_key_bits(), - * psa_get_key_usage_flags() and - * psa_get_key_algorithm() to access this - * information. - * \param[out] pubkey A buffer where the driver can write the - * public key, when generating an asymmetric - * key pair. - * This is \c NULL when generating a symmetric - * key or if the core does not support - * exporting the public key at generation time. - * \param pubkey_size The size of the `pubkey` buffer in bytes. - * This is 0 when generating a symmetric - * key or if the core does not support - * exporting the public key at generation time. - * \param[out] pubkey_length On entry, this is always 0. - * On success, the number of bytes written to - * \p pubkey. If this is 0 or unchanged on return, - * the core will not read the \p pubkey buffer, - * and will instead call the driver's - * psa_drv_key_management_t::p_export_public - * function to export the public key when needed. - */ -typedef psa_status_t (*psa_drv_se_generate_key_t)( - psa_drv_se_context_t *drv_context, - psa_key_slot_number_t key_slot, - const psa_key_attributes_t *attributes, - uint8_t *pubkey, size_t pubkey_size, size_t *pubkey_length); - -/** - * \brief A struct containing all of the function pointers needed to for secure - * element key management - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup or at build time. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** Function that allocates a slot for a key. */ - psa_drv_se_allocate_key_t MBEDTLS_PRIVATE(p_allocate); - /** Function that checks the validity of a slot for a key. */ - psa_drv_se_validate_slot_number_t MBEDTLS_PRIVATE(p_validate_slot_number); - /** Function that performs a key import operation */ - psa_drv_se_import_key_t MBEDTLS_PRIVATE(p_import); - /** Function that performs a generation */ - psa_drv_se_generate_key_t MBEDTLS_PRIVATE(p_generate); - /** Function that performs a key destroy operation */ - psa_drv_se_destroy_key_t MBEDTLS_PRIVATE(p_destroy); - /** Function that performs a key export operation */ - psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export); - /** Function that performs a public key export operation */ - psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export_public); -} psa_drv_se_key_management_t; - -/**@}*/ - -/** \defgroup driver_derivation Secure Element Key Derivation and Agreement - * Key derivation is the process of generating new key material using an - * existing key and additional parameters, iterating through a basic - * cryptographic function, such as a hash. - * Key agreement is a part of cryptographic protocols that allows two parties - * to agree on the same key value, but starting from different original key - * material. - * The flows are similar, and the PSA Crypto Driver Model uses the same functions - * for both of the flows. - * - * There are two different final functions for the flows, - * `psa_drv_se_key_derivation_derive` and `psa_drv_se_key_derivation_export`. - * `psa_drv_se_key_derivation_derive` is used when the key material should be - * placed in a slot on the hardware and not exposed to the caller. - * `psa_drv_se_key_derivation_export` is used when the key material should be - * returned to the PSA Cryptographic API implementation. - * - * Different key derivation algorithms require a different number of inputs. - * Instead of having an API that takes as input variable length arrays, which - * can be problematic to manage on embedded platforms, the inputs are passed - * to the driver via a function, `psa_drv_se_key_derivation_collateral`, that - * is called multiple times with different `collateral_id`s. Thus, for a key - * derivation algorithm that required 3 parameter inputs, the flow would look - * something like: - * ~~~~~~~~~~~~~{.c} - * psa_drv_se_key_derivation_setup(kdf_algorithm, source_key, dest_key_size_bytes); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_0, - * p_collateral_0, - * collateral_0_size); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_1, - * p_collateral_1, - * collateral_1_size); - * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_2, - * p_collateral_2, - * collateral_2_size); - * psa_drv_se_key_derivation_derive(); - * ~~~~~~~~~~~~~ - * - * key agreement example: - * ~~~~~~~~~~~~~{.c} - * psa_drv_se_key_derivation_setup(alg, source_key. dest_key_size_bytes); - * psa_drv_se_key_derivation_collateral(DHE_PUBKEY, p_pubkey, pubkey_size); - * psa_drv_se_key_derivation_export(p_session_key, - * session_key_size, - * &session_key_length); - * ~~~~~~~~~~~~~ - */ -/**@{*/ - -/** \brief A function that Sets up a secure element key derivation operation by - * specifying the algorithm and the source key sot - * - * \param[in,out] drv_context The driver context structure. - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] kdf_alg The algorithm to be used for the key derivation - * \param[in] source_key The key to be used as the source material for - * the key derivation - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_setup_t)(psa_drv_se_context_t *drv_context, - void *op_context, - psa_algorithm_t kdf_alg, - psa_key_slot_number_t source_key); - -/** \brief A function that provides collateral (parameters) needed for a secure - * element key derivation or key agreement operation - * - * Since many key derivation algorithms require multiple parameters, it is - * expected that this function may be called multiple times for the same - * operation, each with a different algorithm-specific `collateral_id` - * - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] collateral_id An ID for the collateral being provided - * \param[in] p_collateral A buffer containing the collateral data - * \param[in] collateral_size The size in bytes of the collateral - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_collateral_t)(void *op_context, - uint32_t collateral_id, - const uint8_t *p_collateral, - size_t collateral_size); - -/** \brief A function that performs the final secure element key derivation - * step and place the generated key material in a slot - * - * \param[in,out] op_context A hardware-specific structure containing any - * context information for the implementation - * \param[in] dest_key The slot where the generated key material - * should be placed - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_derive_t)(void *op_context, - psa_key_slot_number_t dest_key); - -/** \brief A function that performs the final step of a secure element key - * agreement and place the generated key material in a buffer - * - * \param[out] p_output Buffer in which to place the generated key - * material - * \param[in] output_size The size in bytes of `p_output` - * \param[out] p_output_length Upon success, contains the number of bytes of - * key material placed in `p_output` - * - * \retval #PSA_SUCCESS \emptydescription - */ -typedef psa_status_t (*psa_drv_se_key_derivation_export_t)(void *op_context, - uint8_t *p_output, - size_t output_size, - size_t *p_output_length); - -/** - * \brief A struct containing all of the function pointers needed to for secure - * element key derivation and agreement - * - * PSA Crypto API implementations should populate instances of the table as - * appropriate upon startup. - * - * If one of the functions is not implemented, it should be set to NULL. - */ -typedef struct { - /** The driver-specific size of the key derivation context */ - size_t MBEDTLS_PRIVATE(context_size); - /** Function that performs a key derivation setup */ - psa_drv_se_key_derivation_setup_t MBEDTLS_PRIVATE(p_setup); - /** Function that sets key derivation collateral */ - psa_drv_se_key_derivation_collateral_t MBEDTLS_PRIVATE(p_collateral); - /** Function that performs a final key derivation step */ - psa_drv_se_key_derivation_derive_t MBEDTLS_PRIVATE(p_derive); - /** Function that performs a final key derivation or agreement and - * exports the key */ - psa_drv_se_key_derivation_export_t MBEDTLS_PRIVATE(p_export); -} psa_drv_se_key_derivation_t; - -/**@}*/ - -/** \defgroup se_registration Secure element driver registration - */ -/**@{*/ - -/** A structure containing pointers to all the entry points of a - * secure element driver. - * - * Future versions of this specification may add extra substructures at - * the end of this structure. - */ -typedef struct { - /** The version of the driver HAL that this driver implements. - * This is a protection against loading driver binaries built against - * a different version of this specification. - * Use #PSA_DRV_SE_HAL_VERSION. - */ - uint32_t MBEDTLS_PRIVATE(hal_version); - - /** The size of the driver's persistent data in bytes. - * - * This can be 0 if the driver does not need persistent data. - * - * See the documentation of psa_drv_se_context_t::persistent_data - * for more information about why and how a driver can use - * persistent data. - */ - size_t MBEDTLS_PRIVATE(persistent_data_size); - - /** The driver initialization function. - * - * This function is called once during the initialization of the - * PSA Cryptography subsystem, before any other function of the - * driver is called. If this function returns a failure status, - * the driver will be unusable, at least until the next system reset. - * - * If this field is \c NULL, it is equivalent to a function that does - * nothing and returns #PSA_SUCCESS. - */ - psa_drv_se_init_t MBEDTLS_PRIVATE(p_init); - - const psa_drv_se_key_management_t *MBEDTLS_PRIVATE(key_management); - const psa_drv_se_mac_t *MBEDTLS_PRIVATE(mac); - const psa_drv_se_cipher_t *MBEDTLS_PRIVATE(cipher); - const psa_drv_se_aead_t *MBEDTLS_PRIVATE(aead); - const psa_drv_se_asymmetric_t *MBEDTLS_PRIVATE(asymmetric); - const psa_drv_se_key_derivation_t *MBEDTLS_PRIVATE(derivation); -} psa_drv_se_t; - -/** The current version of the secure element driver HAL. - */ -/* 0.0.0 patchlevel 5 */ -#define PSA_DRV_SE_HAL_VERSION 0x00000005 - -/** Register an external cryptoprocessor (secure element) driver. - * - * This function is only intended to be used by driver code, not by - * application code. In implementations with separation between the - * PSA cryptography module and applications, this function should - * only be available to callers that run in the same memory space as - * the cryptography module, and should not be exposed to applications - * running in a different memory space. - * - * This function may be called before psa_crypto_init(). It is - * implementation-defined whether this function may be called - * after psa_crypto_init(). - * - * \note Implementations store metadata about keys including the lifetime - * value, which contains the driver's location indicator. Therefore, - * from one instantiation of the PSA Cryptography - * library to the next one, if there is a key in storage with a certain - * lifetime value, you must always register the same driver (or an - * updated version that communicates with the same secure element) - * with the same location value. - * - * \param location The location value through which this driver will - * be exposed to applications. - * This driver will be used for all keys such that - * `location == #PSA_KEY_LIFETIME_GET_LOCATION( lifetime )`. - * The value #PSA_KEY_LOCATION_LOCAL_STORAGE is reserved - * and may not be used for drivers. Implementations - * may reserve other values. - * \param[in] methods The method table of the driver. This structure must - * remain valid for as long as the cryptography - * module keeps running. It is typically a global - * constant. - * - * \return #PSA_SUCCESS - * The driver was successfully registered. Applications can now - * use \p location to access keys through the methods passed to - * this function. - * \return #PSA_ERROR_BAD_STATE - * This function was called after the initialization of the - * cryptography module, and this implementation does not support - * driver registration at this stage. - * \return #PSA_ERROR_ALREADY_EXISTS - * There is already a registered driver for this value of \p location. - * \return #PSA_ERROR_INVALID_ARGUMENT - * \p location is a reserved value. - * \return #PSA_ERROR_NOT_SUPPORTED - * `methods->hal_version` is not supported by this implementation. - * \return #PSA_ERROR_INSUFFICIENT_MEMORY - * \return #PSA_ERROR_NOT_PERMITTED - * \return #PSA_ERROR_STORAGE_FAILURE - * \return #PSA_ERROR_DATA_CORRUPT - */ -psa_status_t psa_register_se_driver( - psa_key_location_t location, - const psa_drv_se_t *methods); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_SE_DRIVER_H */ +/** + * \file psa/crypto_se_driver.h + * \brief PSA external cryptoprocessor driver module + * + * This header declares types and function signatures for cryptography + * drivers that access key material via opaque references. + * This is meant for cryptoprocessors that have a separate key storage from the + * space in which the PSA Crypto implementation runs, typically secure + * elements (SEs). + * + * This file is part of the PSA Crypto Driver HAL (hardware abstraction layer), + * containing functions for driver developers to implement to enable hardware + * to be called in a standardized way by a PSA Cryptography API + * implementation. The functions comprising the driver HAL, which driver + * authors implement, are not intended to be called by application developers. + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef PSA_CRYPTO_SE_DRIVER_H +#define PSA_CRYPTO_SE_DRIVER_H +#include "mbedtls/private_access.h" + +#include "crypto_driver_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** \defgroup se_init Secure element driver initialization + */ +/**@{*/ + +/** \brief Driver context structure + * + * Driver functions receive a pointer to this structure. + * Each registered driver has one instance of this structure. + * + * Implementations must include the fields specified here and + * may include other fields. + */ +typedef struct { + /** A read-only pointer to the driver's persistent data. + * + * Drivers typically use this persistent data to keep track of + * which slot numbers are available. This is only a guideline: + * drivers may use the persistent data for any purpose, keeping + * in mind the restrictions on when the persistent data is saved + * to storage: the persistent data is only saved after calling + * certain functions that receive a writable pointer to the + * persistent data. + * + * The core allocates a memory buffer for the persistent data. + * The pointer is guaranteed to be suitably aligned for any data type, + * like a pointer returned by `malloc` (but the core can use any + * method to allocate the buffer, not necessarily `malloc`). + * + * The size of this buffer is in the \c persistent_data_size field of + * this structure. + * + * Before the driver is initialized for the first time, the content of + * the persistent data is all-bits-zero. After a driver upgrade, if the + * size of the persistent data has increased, the original data is padded + * on the right with zeros; if the size has decreased, the original data + * is truncated to the new size. + * + * This pointer is to read-only data. Only a few driver functions are + * allowed to modify the persistent data. These functions receive a + * writable pointer. These functions are: + * - psa_drv_se_t::p_init + * - psa_drv_se_key_management_t::p_allocate + * - psa_drv_se_key_management_t::p_destroy + * + * The PSA Cryptography core saves the persistent data from one + * session to the next. It does this before returning from API functions + * that call a driver method that is allowed to modify the persistent + * data, specifically: + * - psa_crypto_init() causes a call to psa_drv_se_t::p_init, and may call + * psa_drv_se_key_management_t::p_destroy to complete an action + * that was interrupted by a power failure. + * - Key creation functions cause a call to + * psa_drv_se_key_management_t::p_allocate, and may cause a call to + * psa_drv_se_key_management_t::p_destroy in case an error occurs. + * - psa_destroy_key() causes a call to + * psa_drv_se_key_management_t::p_destroy. + */ + const void *const MBEDTLS_PRIVATE(persistent_data); + + /** The size of \c persistent_data in bytes. + * + * This is always equal to the value of the `persistent_data_size` field + * of the ::psa_drv_se_t structure when the driver is registered. + */ + const size_t MBEDTLS_PRIVATE(persistent_data_size); + + /** Driver transient data. + * + * The core initializes this value to 0 and does not read or modify it + * afterwards. The driver may store whatever it wants in this field. + */ + uintptr_t MBEDTLS_PRIVATE(transient_data); +} psa_drv_se_context_t; + +/** \brief A driver initialization function. + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] persistent_data A pointer to the persistent data + * that allows writing. + * \param location The location value for which this driver + * is registered. The driver will be invoked + * for all keys whose lifetime is in this + * location. + * + * \retval #PSA_SUCCESS + * The driver is operational. + * The core will update the persistent data in storage. + * \return + * Any other return value prevents the driver from being used in + * this session. + * The core will NOT update the persistent data in storage. + */ +typedef psa_status_t (*psa_drv_se_init_t)(psa_drv_se_context_t *drv_context, + void *persistent_data, + psa_key_location_t location); + +#if defined(__DOXYGEN_ONLY__) || !defined(MBEDTLS_PSA_CRYPTO_SE_C) +/* Mbed TLS with secure element support enabled defines this type in + * crypto_types.h because it is also visible to applications through an + * implementation-specific extension. + * For the PSA Cryptography specification, this type is only visible + * via crypto_se_driver.h. */ +/** An internal designation of a key slot between the core part of the + * PSA Crypto implementation and the driver. The meaning of this value + * is driver-dependent. */ +typedef uint64_t psa_key_slot_number_t; +#endif /* __DOXYGEN_ONLY__ || !MBEDTLS_PSA_CRYPTO_SE_C */ + +/**@}*/ + +/** \defgroup se_mac Secure Element Message Authentication Codes + * Generation and authentication of Message Authentication Codes (MACs) using + * a secure element can be done either as a single function call (via the + * `psa_drv_se_mac_generate_t` or `psa_drv_se_mac_verify_t` functions), or in + * parts using the following sequence: + * - `psa_drv_se_mac_setup_t` + * - `psa_drv_se_mac_update_t` + * - `psa_drv_se_mac_update_t` + * - ... + * - `psa_drv_se_mac_finish_t` or `psa_drv_se_mac_finish_verify_t` + * + * If a previously started secure element MAC operation needs to be terminated, + * it should be done so by the `psa_drv_se_mac_abort_t`. Failure to do so may + * result in allocated resources not being freed or in other undefined + * behavior. + */ +/**@{*/ +/** \brief A function that starts a secure element MAC operation for a PSA + * Crypto Driver implementation + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] op_context A structure that will contain the + * hardware-specific MAC context + * \param[in] key_slot The slot of the key to be used for the + * operation + * \param[in] algorithm The algorithm to be used to underly the MAC + * operation + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_mac_setup_t)(psa_drv_se_context_t *drv_context, + void *op_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t algorithm); + +/** \brief A function that continues a previously started secure element MAC + * operation + * + * \param[in,out] op_context A hardware-specific structure for the + * previously-established MAC operation to be + * updated + * \param[in] p_input A buffer containing the message to be appended + * to the MAC operation + * \param[in] input_length The size in bytes of the input message buffer + */ +typedef psa_status_t (*psa_drv_se_mac_update_t)(void *op_context, + const uint8_t *p_input, + size_t input_length); + +/** \brief a function that completes a previously started secure element MAC + * operation by returning the resulting MAC. + * + * \param[in,out] op_context A hardware-specific structure for the + * previously started MAC operation to be + * finished + * \param[out] p_mac A buffer where the generated MAC will be + * placed + * \param[in] mac_size The size in bytes of the buffer that has been + * allocated for the `output` buffer + * \param[out] p_mac_length After completion, will contain the number of + * bytes placed in the `p_mac` buffer + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_mac_finish_t)(void *op_context, + uint8_t *p_mac, + size_t mac_size, + size_t *p_mac_length); + +/** \brief A function that completes a previously started secure element MAC + * operation by comparing the resulting MAC against a provided value + * + * \param[in,out] op_context A hardware-specific structure for the previously + * started MAC operation to be finished + * \param[in] p_mac The MAC value against which the resulting MAC + * will be compared against + * \param[in] mac_length The size in bytes of the value stored in `p_mac` + * + * \retval #PSA_SUCCESS + * The operation completed successfully and the MACs matched each + * other + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The operation completed successfully, but the calculated MAC did + * not match the provided MAC + */ +typedef psa_status_t (*psa_drv_se_mac_finish_verify_t)(void *op_context, + const uint8_t *p_mac, + size_t mac_length); + +/** \brief A function that aborts a previous started secure element MAC + * operation + * + * \param[in,out] op_context A hardware-specific structure for the previously + * started MAC operation to be aborted + */ +typedef psa_status_t (*psa_drv_se_mac_abort_t)(void *op_context); + +/** \brief A function that performs a secure element MAC operation in one + * command and returns the calculated MAC + * + * \param[in,out] drv_context The driver context structure. + * \param[in] p_input A buffer containing the message to be MACed + * \param[in] input_length The size in bytes of `p_input` + * \param[in] key_slot The slot of the key to be used + * \param[in] alg The algorithm to be used to underlie the MAC + * operation + * \param[out] p_mac A buffer where the generated MAC will be + * placed + * \param[in] mac_size The size in bytes of the `p_mac` buffer + * \param[out] p_mac_length After completion, will contain the number of + * bytes placed in the `output` buffer + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_mac_generate_t)(psa_drv_se_context_t *drv_context, + const uint8_t *p_input, + size_t input_length, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + uint8_t *p_mac, + size_t mac_size, + size_t *p_mac_length); + +/** \brief A function that performs a secure element MAC operation in one + * command and compares the resulting MAC against a provided value + * + * \param[in,out] drv_context The driver context structure. + * \param[in] p_input A buffer containing the message to be MACed + * \param[in] input_length The size in bytes of `input` + * \param[in] key_slot The slot of the key to be used + * \param[in] alg The algorithm to be used to underlie the MAC + * operation + * \param[in] p_mac The MAC value against which the resulting MAC will + * be compared against + * \param[in] mac_length The size in bytes of `mac` + * + * \retval #PSA_SUCCESS + * The operation completed successfully and the MACs matched each + * other + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The operation completed successfully, but the calculated MAC did + * not match the provided MAC + */ +typedef psa_status_t (*psa_drv_se_mac_verify_t)(psa_drv_se_context_t *drv_context, + const uint8_t *p_input, + size_t input_length, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + const uint8_t *p_mac, + size_t mac_length); + +/** \brief A struct containing all of the function pointers needed to + * perform secure element MAC operations + * + * PSA Crypto API implementations should populate the table as appropriate + * upon startup. + * + * If one of the functions is not implemented (such as + * `psa_drv_se_mac_generate_t`), it should be set to NULL. + * + * Driver implementers should ensure that they implement all of the functions + * that make sense for their hardware, and that they provide a full solution + * (for example, if they support `p_setup`, they should also support + * `p_update` and at least one of `p_finish` or `p_finish_verify`). + * + */ +typedef struct { + /**The size in bytes of the hardware-specific secure element MAC context + * structure + */ + size_t MBEDTLS_PRIVATE(context_size); + /** Function that performs a MAC setup operation + */ + psa_drv_se_mac_setup_t MBEDTLS_PRIVATE(p_setup); + /** Function that performs a MAC update operation + */ + psa_drv_se_mac_update_t MBEDTLS_PRIVATE(p_update); + /** Function that completes a MAC operation + */ + psa_drv_se_mac_finish_t MBEDTLS_PRIVATE(p_finish); + /** Function that completes a MAC operation with a verify check + */ + psa_drv_se_mac_finish_verify_t MBEDTLS_PRIVATE(p_finish_verify); + /** Function that aborts a previously started MAC operation + */ + psa_drv_se_mac_abort_t MBEDTLS_PRIVATE(p_abort); + /** Function that performs a MAC operation in one call + */ + psa_drv_se_mac_generate_t MBEDTLS_PRIVATE(p_mac); + /** Function that performs a MAC and verify operation in one call + */ + psa_drv_se_mac_verify_t MBEDTLS_PRIVATE(p_mac_verify); +} psa_drv_se_mac_t; +/**@}*/ + +/** \defgroup se_cipher Secure Element Symmetric Ciphers + * + * Encryption and Decryption using secure element keys in block modes other + * than ECB must be done in multiple parts, using the following flow: + * - `psa_drv_se_cipher_setup_t` + * - `psa_drv_se_cipher_set_iv_t` (optional depending upon block mode) + * - `psa_drv_se_cipher_update_t` + * - `psa_drv_se_cipher_update_t` + * - ... + * - `psa_drv_se_cipher_finish_t` + * + * If a previously started secure element Cipher operation needs to be + * terminated, it should be done so by the `psa_drv_se_cipher_abort_t`. Failure + * to do so may result in allocated resources not being freed or in other + * undefined behavior. + * + * In situations where a PSA Cryptographic API implementation is using a block + * mode not-supported by the underlying hardware or driver, it can construct + * the block mode itself, while calling the `psa_drv_se_cipher_ecb_t` function + * for the cipher operations. + */ +/**@{*/ + +/** \brief A function that provides the cipher setup function for a + * secure element driver + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] op_context A structure that will contain the + * hardware-specific cipher context. + * \param[in] key_slot The slot of the key to be used for the + * operation + * \param[in] algorithm The algorithm to be used in the cipher + * operation + * \param[in] direction Indicates whether the operation is an encrypt + * or decrypt + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + */ +typedef psa_status_t (*psa_drv_se_cipher_setup_t)(psa_drv_se_context_t *drv_context, + void *op_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t algorithm, + psa_encrypt_or_decrypt_t direction); + +/** \brief A function that sets the initialization vector (if + * necessary) for a secure element cipher operation + * + * Rationale: The `psa_se_cipher_*` operation in the PSA Cryptographic API has + * two IV functions: one to set the IV, and one to generate it internally. The + * generate function is not necessary for the drivers to implement as the PSA + * Crypto implementation can do the generation using its RNG features. + * + * \param[in,out] op_context A structure that contains the previously set up + * hardware-specific cipher context + * \param[in] p_iv A buffer containing the initialization vector + * \param[in] iv_length The size (in bytes) of the `p_iv` buffer + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_cipher_set_iv_t)(void *op_context, + const uint8_t *p_iv, + size_t iv_length); + +/** \brief A function that continues a previously started secure element cipher + * operation + * + * \param[in,out] op_context A hardware-specific structure for the + * previously started cipher operation + * \param[in] p_input A buffer containing the data to be + * encrypted/decrypted + * \param[in] input_size The size in bytes of the buffer pointed to + * by `p_input` + * \param[out] p_output The caller-allocated buffer where the + * output will be placed + * \param[in] output_size The allocated size in bytes of the + * `p_output` buffer + * \param[out] p_output_length After completion, will contain the number + * of bytes placed in the `p_output` buffer + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_cipher_update_t)(void *op_context, + const uint8_t *p_input, + size_t input_size, + uint8_t *p_output, + size_t output_size, + size_t *p_output_length); + +/** \brief A function that completes a previously started secure element cipher + * operation + * + * \param[in,out] op_context A hardware-specific structure for the + * previously started cipher operation + * \param[out] p_output The caller-allocated buffer where the output + * will be placed + * \param[in] output_size The allocated size in bytes of the `p_output` + * buffer + * \param[out] p_output_length After completion, will contain the number of + * bytes placed in the `p_output` buffer + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_cipher_finish_t)(void *op_context, + uint8_t *p_output, + size_t output_size, + size_t *p_output_length); + +/** \brief A function that aborts a previously started secure element cipher + * operation + * + * \param[in,out] op_context A hardware-specific structure for the + * previously started cipher operation + */ +typedef psa_status_t (*psa_drv_se_cipher_abort_t)(void *op_context); + +/** \brief A function that performs the ECB block mode for secure element + * cipher operations + * + * Note: this function should only be used with implementations that do not + * provide a needed higher-level operation. + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot The slot of the key to be used for the operation + * \param[in] algorithm The algorithm to be used in the cipher operation + * \param[in] direction Indicates whether the operation is an encrypt or + * decrypt + * \param[in] p_input A buffer containing the data to be + * encrypted/decrypted + * \param[in] input_size The size in bytes of the buffer pointed to by + * `p_input` + * \param[out] p_output The caller-allocated buffer where the output + * will be placed + * \param[in] output_size The allocated size in bytes of the `p_output` + * buffer + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + */ +typedef psa_status_t (*psa_drv_se_cipher_ecb_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t algorithm, + psa_encrypt_or_decrypt_t direction, + const uint8_t *p_input, + size_t input_size, + uint8_t *p_output, + size_t output_size); + +/** + * \brief A struct containing all of the function pointers needed to implement + * cipher operations using secure elements. + * + * PSA Crypto API implementations should populate instances of the table as + * appropriate upon startup or at build time. + * + * If one of the functions is not implemented (such as + * `psa_drv_se_cipher_ecb_t`), it should be set to NULL. + */ +typedef struct { + /** The size in bytes of the hardware-specific secure element cipher + * context structure + */ + size_t MBEDTLS_PRIVATE(context_size); + /** Function that performs a cipher setup operation */ + psa_drv_se_cipher_setup_t MBEDTLS_PRIVATE(p_setup); + /** Function that sets a cipher IV (if necessary) */ + psa_drv_se_cipher_set_iv_t MBEDTLS_PRIVATE(p_set_iv); + /** Function that performs a cipher update operation */ + psa_drv_se_cipher_update_t MBEDTLS_PRIVATE(p_update); + /** Function that completes a cipher operation */ + psa_drv_se_cipher_finish_t MBEDTLS_PRIVATE(p_finish); + /** Function that aborts a cipher operation */ + psa_drv_se_cipher_abort_t MBEDTLS_PRIVATE(p_abort); + /** Function that performs ECB mode for a cipher operation + * (Danger: ECB mode should not be used directly by clients of the PSA + * Crypto Client API) + */ + psa_drv_se_cipher_ecb_t MBEDTLS_PRIVATE(p_ecb); +} psa_drv_se_cipher_t; + +/**@}*/ + +/** \defgroup se_asymmetric Secure Element Asymmetric Cryptography + * + * Since the amount of data that can (or should) be encrypted or signed using + * asymmetric keys is limited by the key size, asymmetric key operations using + * keys in a secure element must be done in single function calls. + */ +/**@{*/ + +/** + * \brief A function that signs a hash or short message with a private key in + * a secure element + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Key slot of an asymmetric key pair + * \param[in] alg A signature algorithm that is compatible + * with the type of `key` + * \param[in] p_hash The hash to sign + * \param[in] hash_length Size of the `p_hash` buffer in bytes + * \param[out] p_signature Buffer where the signature is to be written + * \param[in] signature_size Size of the `p_signature` buffer in bytes + * \param[out] p_signature_length On success, the number of bytes + * that make up the returned signature value + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_asymmetric_sign_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + const uint8_t *p_hash, + size_t hash_length, + uint8_t *p_signature, + size_t signature_size, + size_t *p_signature_length); + +/** + * \brief A function that verifies the signature a hash or short message using + * an asymmetric public key in a secure element + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Key slot of a public key or an asymmetric key + * pair + * \param[in] alg A signature algorithm that is compatible with + * the type of `key` + * \param[in] p_hash The hash whose signature is to be verified + * \param[in] hash_length Size of the `p_hash` buffer in bytes + * \param[in] p_signature Buffer containing the signature to verify + * \param[in] signature_length Size of the `p_signature` buffer in bytes + * + * \retval #PSA_SUCCESS + * The signature is valid. + */ +typedef psa_status_t (*psa_drv_se_asymmetric_verify_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + const uint8_t *p_hash, + size_t hash_length, + const uint8_t *p_signature, + size_t signature_length); + +/** + * \brief A function that encrypts a short message with an asymmetric public + * key in a secure element + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Key slot of a public key or an asymmetric key + * pair + * \param[in] alg An asymmetric encryption algorithm that is + * compatible with the type of `key` + * \param[in] p_input The message to encrypt + * \param[in] input_length Size of the `p_input` buffer in bytes + * \param[in] p_salt A salt or label, if supported by the + * encryption algorithm + * If the algorithm does not support a + * salt, pass `NULL`. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass `NULL`. + * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param[in] salt_length Size of the `p_salt` buffer in bytes + * If `p_salt` is `NULL`, pass 0. + * \param[out] p_output Buffer where the encrypted message is to + * be written + * \param[in] output_size Size of the `p_output` buffer in bytes + * \param[out] p_output_length On success, the number of bytes that make up + * the returned output + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_asymmetric_encrypt_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + const uint8_t *p_input, + size_t input_length, + const uint8_t *p_salt, + size_t salt_length, + uint8_t *p_output, + size_t output_size, + size_t *p_output_length); + +/** + * \brief A function that decrypts a short message with an asymmetric private + * key in a secure element. + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Key slot of an asymmetric key pair + * \param[in] alg An asymmetric encryption algorithm that is + * compatible with the type of `key` + * \param[in] p_input The message to decrypt + * \param[in] input_length Size of the `p_input` buffer in bytes + * \param[in] p_salt A salt or label, if supported by the + * encryption algorithm + * If the algorithm does not support a + * salt, pass `NULL`. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass `NULL`. + * For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param[in] salt_length Size of the `p_salt` buffer in bytes + * If `p_salt` is `NULL`, pass 0. + * \param[out] p_output Buffer where the decrypted message is to + * be written + * \param[in] output_size Size of the `p_output` buffer in bytes + * \param[out] p_output_length On success, the number of bytes + * that make up the returned output + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_asymmetric_decrypt_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t alg, + const uint8_t *p_input, + size_t input_length, + const uint8_t *p_salt, + size_t salt_length, + uint8_t *p_output, + size_t output_size, + size_t *p_output_length); + +/** + * \brief A struct containing all of the function pointers needed to implement + * asymmetric cryptographic operations using secure elements. + * + * PSA Crypto API implementations should populate instances of the table as + * appropriate upon startup or at build time. + * + * If one of the functions is not implemented, it should be set to NULL. + */ +typedef struct { + /** Function that performs an asymmetric sign operation */ + psa_drv_se_asymmetric_sign_t MBEDTLS_PRIVATE(p_sign); + /** Function that performs an asymmetric verify operation */ + psa_drv_se_asymmetric_verify_t MBEDTLS_PRIVATE(p_verify); + /** Function that performs an asymmetric encrypt operation */ + psa_drv_se_asymmetric_encrypt_t MBEDTLS_PRIVATE(p_encrypt); + /** Function that performs an asymmetric decrypt operation */ + psa_drv_se_asymmetric_decrypt_t MBEDTLS_PRIVATE(p_decrypt); +} psa_drv_se_asymmetric_t; + +/**@}*/ + +/** \defgroup se_aead Secure Element Authenticated Encryption with Additional Data + * Authenticated Encryption with Additional Data (AEAD) operations with secure + * elements must be done in one function call. While this creates a burden for + * implementers as there must be sufficient space in memory for the entire + * message, it prevents decrypted data from being made available before the + * authentication operation is complete and the data is known to be authentic. + */ +/**@{*/ + +/** \brief A function that performs a secure element authenticated encryption + * operation + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Slot containing the key to use. + * \param[in] algorithm The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(`alg`) is true) + * \param[in] p_nonce Nonce or IV to use + * \param[in] nonce_length Size of the `p_nonce` buffer in bytes + * \param[in] p_additional_data Additional data that will be + * authenticated but not encrypted + * \param[in] additional_data_length Size of `p_additional_data` in bytes + * \param[in] p_plaintext Data that will be authenticated and + * encrypted + * \param[in] plaintext_length Size of `p_plaintext` in bytes + * \param[out] p_ciphertext Output buffer for the authenticated and + * encrypted data. The additional data is + * not part of this output. For algorithms + * where the encrypted data and the + * authentication tag are defined as + * separate outputs, the authentication + * tag is appended to the encrypted data. + * \param[in] ciphertext_size Size of the `p_ciphertext` buffer in + * bytes + * \param[out] p_ciphertext_length On success, the size of the output in + * the `p_ciphertext` buffer + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_aead_encrypt_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t algorithm, + const uint8_t *p_nonce, + size_t nonce_length, + const uint8_t *p_additional_data, + size_t additional_data_length, + const uint8_t *p_plaintext, + size_t plaintext_length, + uint8_t *p_ciphertext, + size_t ciphertext_size, + size_t *p_ciphertext_length); + +/** A function that performs a secure element authenticated decryption operation + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key_slot Slot containing the key to use + * \param[in] algorithm The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(`alg`) is true) + * \param[in] p_nonce Nonce or IV to use + * \param[in] nonce_length Size of the `p_nonce` buffer in bytes + * \param[in] p_additional_data Additional data that has been + * authenticated but not encrypted + * \param[in] additional_data_length Size of `p_additional_data` in bytes + * \param[in] p_ciphertext Data that has been authenticated and + * encrypted. + * For algorithms where the encrypted data + * and the authentication tag are defined + * as separate inputs, the buffer must + * contain the encrypted data followed by + * the authentication tag. + * \param[in] ciphertext_length Size of `p_ciphertext` in bytes + * \param[out] p_plaintext Output buffer for the decrypted data + * \param[in] plaintext_size Size of the `p_plaintext` buffer in + * bytes + * \param[out] p_plaintext_length On success, the size of the output in + * the `p_plaintext` buffer + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_aead_decrypt_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + psa_algorithm_t algorithm, + const uint8_t *p_nonce, + size_t nonce_length, + const uint8_t *p_additional_data, + size_t additional_data_length, + const uint8_t *p_ciphertext, + size_t ciphertext_length, + uint8_t *p_plaintext, + size_t plaintext_size, + size_t *p_plaintext_length); + +/** + * \brief A struct containing all of the function pointers needed to implement + * secure element Authenticated Encryption with Additional Data operations + * + * PSA Crypto API implementations should populate instances of the table as + * appropriate upon startup. + * + * If one of the functions is not implemented, it should be set to NULL. + */ +typedef struct { + /** Function that performs the AEAD encrypt operation */ + psa_drv_se_aead_encrypt_t MBEDTLS_PRIVATE(p_encrypt); + /** Function that performs the AEAD decrypt operation */ + psa_drv_se_aead_decrypt_t MBEDTLS_PRIVATE(p_decrypt); +} psa_drv_se_aead_t; +/**@}*/ + +/** \defgroup se_key_management Secure Element Key Management + * Currently, key management is limited to importing keys in the clear, + * destroying keys, and exporting keys in the clear. + * Whether a key may be exported is determined by the key policies in place + * on the key slot. + */ +/**@{*/ + +/** An enumeration indicating how a key is created. + */ +typedef enum { + PSA_KEY_CREATION_IMPORT, /**< During psa_import_key() */ + PSA_KEY_CREATION_GENERATE, /**< During psa_generate_key() */ + PSA_KEY_CREATION_DERIVE, /**< During psa_key_derivation_output_key() */ + PSA_KEY_CREATION_COPY, /**< During psa_copy_key() */ + +#ifndef __DOXYGEN_ONLY__ + /** A key is being registered with mbedtls_psa_register_se_key(). + * + * The core only passes this value to + * psa_drv_se_key_management_t::p_validate_slot_number, not to + * psa_drv_se_key_management_t::p_allocate. The call to + * `p_validate_slot_number` is not followed by any other call to the + * driver: the key is considered successfully registered if the call to + * `p_validate_slot_number` succeeds, or if `p_validate_slot_number` is + * null. + * + * With this creation method, the driver must return #PSA_SUCCESS if + * the given attributes are compatible with the existing key in the slot, + * and #PSA_ERROR_DOES_NOT_EXIST if the driver can determine that there + * is no key with the specified slot number. + * + * This is an Mbed TLS extension. + */ + PSA_KEY_CREATION_REGISTER, +#endif +} psa_key_creation_method_t; + +/** \brief A function that allocates a slot for a key. + * + * To create a key in a specific slot in a secure element, the core + * first calls this function to determine a valid slot number, + * then calls a function to create the key material in that slot. + * In nominal conditions (that is, if no error occurs), + * the effect of a call to a key creation function in the PSA Cryptography + * API with a lifetime that places the key in a secure element is the + * following: + * -# The core calls psa_drv_se_key_management_t::p_allocate + * (or in some implementations + * psa_drv_se_key_management_t::p_validate_slot_number). The driver + * selects (or validates) a suitable slot number given the key attributes + * and the state of the secure element. + * -# The core calls a key creation function in the driver. + * + * The key creation functions in the PSA Cryptography API are: + * - psa_import_key(), which causes + * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_IMPORT + * then a call to psa_drv_se_key_management_t::p_import. + * - psa_generate_key(), which causes + * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_GENERATE + * then a call to psa_drv_se_key_management_t::p_import. + * - psa_key_derivation_output_key(), which causes + * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_DERIVE + * then a call to psa_drv_se_key_derivation_t::p_derive. + * - psa_copy_key(), which causes + * a call to `p_allocate` with \p method = #PSA_KEY_CREATION_COPY + * then a call to psa_drv_se_key_management_t::p_export. + * + * In case of errors, other behaviors are possible. + * - If the PSA Cryptography subsystem dies after the first step, + * for example because the device has lost power abruptly, + * the second step may never happen, or may happen after a reset + * and re-initialization. Alternatively, after a reset and + * re-initialization, the core may call + * psa_drv_se_key_management_t::p_destroy on the slot number that + * was allocated (or validated) instead of calling a key creation function. + * - If an error occurs, the core may call + * psa_drv_se_key_management_t::p_destroy on the slot number that + * was allocated (or validated) instead of calling a key creation function. + * + * Errors and system resets also have an impact on the driver's persistent + * data. If a reset happens before the overall key creation process is + * completed (before or after the second step above), it is unspecified + * whether the persistent data after the reset is identical to what it + * was before or after the call to `p_allocate` (or `p_validate_slot_number`). + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] persistent_data A pointer to the persistent data + * that allows writing. + * \param[in] attributes Attributes of the key. + * \param method The way in which the key is being created. + * \param[out] key_slot Slot where the key will be stored. + * This must be a valid slot for a key of the + * chosen type. It must be unoccupied. + * + * \retval #PSA_SUCCESS + * Success. + * The core will record \c *key_slot as the key slot where the key + * is stored and will update the persistent data in storage. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + */ +typedef psa_status_t (*psa_drv_se_allocate_key_t)( + psa_drv_se_context_t *drv_context, + void *persistent_data, + const psa_key_attributes_t *attributes, + psa_key_creation_method_t method, + psa_key_slot_number_t *key_slot); + +/** \brief A function that determines whether a slot number is valid + * for a key. + * + * To create a key in a specific slot in a secure element, the core + * first calls this function to validate the choice of slot number, + * then calls a function to create the key material in that slot. + * See the documentation of #psa_drv_se_allocate_key_t for more details. + * + * As of the PSA Cryptography API specification version 1.0, there is no way + * for applications to trigger a call to this function. However some + * implementations offer the capability to create or declare a key in + * a specific slot via implementation-specific means, generally for the + * sake of initial device provisioning or onboarding. Such a mechanism may + * be added to a future version of the PSA Cryptography API specification. + * + * This function may update the driver's persistent data through + * \p persistent_data. The core will save the updated persistent data at the + * end of the key creation process. See the description of + * ::psa_drv_se_allocate_key_t for more information. + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] persistent_data A pointer to the persistent data + * that allows writing. + * \param[in] attributes Attributes of the key. + * \param method The way in which the key is being created. + * \param[in] key_slot Slot where the key is to be stored. + * + * \retval #PSA_SUCCESS + * The given slot number is valid for a key with the given + * attributes. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The given slot number is not valid for a key with the + * given attributes. This includes the case where the slot + * number is not valid at all. + * \retval #PSA_ERROR_ALREADY_EXISTS + * There is already a key with the specified slot number. + * Drivers may choose to return this error from the key + * creation function instead. + */ +typedef psa_status_t (*psa_drv_se_validate_slot_number_t)( + psa_drv_se_context_t *drv_context, + void *persistent_data, + const psa_key_attributes_t *attributes, + psa_key_creation_method_t method, + psa_key_slot_number_t key_slot); + +/** \brief A function that imports a key into a secure element in binary format + * + * This function can support any output from psa_export_key(). Refer to the + * documentation of psa_export_key() for the format for each key type. + * + * \param[in,out] drv_context The driver context structure. + * \param key_slot Slot where the key will be stored. + * This must be a valid slot for a key of the + * chosen type. It must be unoccupied. + * \param[in] attributes The key attributes, including the lifetime, + * the key type and the usage policy. + * Drivers should not access the key size stored + * in the attributes: it may not match the + * data passed in \p data. + * Drivers can call psa_get_key_lifetime(), + * psa_get_key_type(), + * psa_get_key_usage_flags() and + * psa_get_key_algorithm() to access this + * information. + * \param[in] data Buffer containing the key data. + * \param[in] data_length Size of the \p data buffer in bytes. + * \param[out] bits On success, the key size in bits. The driver + * must determine this value after parsing the + * key according to the key type. + * This value is not used if the function fails. + * + * \retval #PSA_SUCCESS + * Success. + */ +typedef psa_status_t (*psa_drv_se_import_key_t)( + psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + size_t *bits); + +/** + * \brief A function that destroys a secure element key and restore the slot to + * its default state + * + * This function destroys the content of the key from a secure element. + * Implementations shall make a best effort to ensure that any previous content + * of the slot is unrecoverable. + * + * This function returns the specified slot to its default state. + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] persistent_data A pointer to the persistent data + * that allows writing. + * \param key_slot The key slot to erase. + * + * \retval #PSA_SUCCESS + * The slot's content, if any, has been erased. + */ +typedef psa_status_t (*psa_drv_se_destroy_key_t)( + psa_drv_se_context_t *drv_context, + void *persistent_data, + psa_key_slot_number_t key_slot); + +/** + * \brief A function that exports a secure element key in binary format + * + * The output of this function can be passed to psa_import_key() to + * create an equivalent object. + * + * If a key is created with `psa_import_key()` and then exported with + * this function, it is not guaranteed that the resulting data is + * identical: the implementation may choose a different representation + * of the same key if the format permits it. + * + * This function should generate output in the same format that + * `psa_export_key()` does. Refer to the + * documentation of `psa_export_key()` for the format for each key type. + * + * \param[in,out] drv_context The driver context structure. + * \param[in] key Slot whose content is to be exported. This must + * be an occupied key slot. + * \param[out] p_data Buffer where the key data is to be written. + * \param[in] data_size Size of the `p_data` buffer in bytes. + * \param[out] p_data_length On success, the number of bytes + * that make up the key data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +typedef psa_status_t (*psa_drv_se_export_key_t)(psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key, + uint8_t *p_data, + size_t data_size, + size_t *p_data_length); + +/** + * \brief A function that generates a symmetric or asymmetric key on a secure + * element + * + * If the key type \c type recorded in \p attributes + * is asymmetric (#PSA_KEY_TYPE_IS_ASYMMETRIC(\c type) = 1), + * the driver may export the public key at the time of generation, + * in the format documented for psa_export_public_key() by writing it + * to the \p pubkey buffer. + * This is optional, intended for secure elements that output the + * public key at generation time and that cannot export the public key + * later. Drivers that do not need this feature should leave + * \p *pubkey_length set to 0 and should + * implement the psa_drv_key_management_t::p_export_public function. + * Some implementations do not support this feature, in which case + * \p pubkey is \c NULL and \p pubkey_size is 0. + * + * \param[in,out] drv_context The driver context structure. + * \param key_slot Slot where the key will be stored. + * This must be a valid slot for a key of the + * chosen type. It must be unoccupied. + * \param[in] attributes The key attributes, including the lifetime, + * the key type and size, and the usage policy. + * Drivers can call psa_get_key_lifetime(), + * psa_get_key_type(), psa_get_key_bits(), + * psa_get_key_usage_flags() and + * psa_get_key_algorithm() to access this + * information. + * \param[out] pubkey A buffer where the driver can write the + * public key, when generating an asymmetric + * key pair. + * This is \c NULL when generating a symmetric + * key or if the core does not support + * exporting the public key at generation time. + * \param pubkey_size The size of the `pubkey` buffer in bytes. + * This is 0 when generating a symmetric + * key or if the core does not support + * exporting the public key at generation time. + * \param[out] pubkey_length On entry, this is always 0. + * On success, the number of bytes written to + * \p pubkey. If this is 0 or unchanged on return, + * the core will not read the \p pubkey buffer, + * and will instead call the driver's + * psa_drv_key_management_t::p_export_public + * function to export the public key when needed. + */ +typedef psa_status_t (*psa_drv_se_generate_key_t)( + psa_drv_se_context_t *drv_context, + psa_key_slot_number_t key_slot, + const psa_key_attributes_t *attributes, + uint8_t *pubkey, size_t pubkey_size, size_t *pubkey_length); + +/** + * \brief A struct containing all of the function pointers needed to for secure + * element key management + * + * PSA Crypto API implementations should populate instances of the table as + * appropriate upon startup or at build time. + * + * If one of the functions is not implemented, it should be set to NULL. + */ +typedef struct { + /** Function that allocates a slot for a key. */ + psa_drv_se_allocate_key_t MBEDTLS_PRIVATE(p_allocate); + /** Function that checks the validity of a slot for a key. */ + psa_drv_se_validate_slot_number_t MBEDTLS_PRIVATE(p_validate_slot_number); + /** Function that performs a key import operation */ + psa_drv_se_import_key_t MBEDTLS_PRIVATE(p_import); + /** Function that performs a generation */ + psa_drv_se_generate_key_t MBEDTLS_PRIVATE(p_generate); + /** Function that performs a key destroy operation */ + psa_drv_se_destroy_key_t MBEDTLS_PRIVATE(p_destroy); + /** Function that performs a key export operation */ + psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export); + /** Function that performs a public key export operation */ + psa_drv_se_export_key_t MBEDTLS_PRIVATE(p_export_public); +} psa_drv_se_key_management_t; + +/**@}*/ + +/** \defgroup driver_derivation Secure Element Key Derivation and Agreement + * Key derivation is the process of generating new key material using an + * existing key and additional parameters, iterating through a basic + * cryptographic function, such as a hash. + * Key agreement is a part of cryptographic protocols that allows two parties + * to agree on the same key value, but starting from different original key + * material. + * The flows are similar, and the PSA Crypto Driver Model uses the same functions + * for both of the flows. + * + * There are two different final functions for the flows, + * `psa_drv_se_key_derivation_derive` and `psa_drv_se_key_derivation_export`. + * `psa_drv_se_key_derivation_derive` is used when the key material should be + * placed in a slot on the hardware and not exposed to the caller. + * `psa_drv_se_key_derivation_export` is used when the key material should be + * returned to the PSA Cryptographic API implementation. + * + * Different key derivation algorithms require a different number of inputs. + * Instead of having an API that takes as input variable length arrays, which + * can be problematic to manage on embedded platforms, the inputs are passed + * to the driver via a function, `psa_drv_se_key_derivation_collateral`, that + * is called multiple times with different `collateral_id`s. Thus, for a key + * derivation algorithm that required 3 parameter inputs, the flow would look + * something like: + * ~~~~~~~~~~~~~{.c} + * psa_drv_se_key_derivation_setup(kdf_algorithm, source_key, dest_key_size_bytes); + * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_0, + * p_collateral_0, + * collateral_0_size); + * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_1, + * p_collateral_1, + * collateral_1_size); + * psa_drv_se_key_derivation_collateral(kdf_algorithm_collateral_id_2, + * p_collateral_2, + * collateral_2_size); + * psa_drv_se_key_derivation_derive(); + * ~~~~~~~~~~~~~ + * + * key agreement example: + * ~~~~~~~~~~~~~{.c} + * psa_drv_se_key_derivation_setup(alg, source_key. dest_key_size_bytes); + * psa_drv_se_key_derivation_collateral(DHE_PUBKEY, p_pubkey, pubkey_size); + * psa_drv_se_key_derivation_export(p_session_key, + * session_key_size, + * &session_key_length); + * ~~~~~~~~~~~~~ + */ +/**@{*/ + +/** \brief A function that Sets up a secure element key derivation operation by + * specifying the algorithm and the source key sot + * + * \param[in,out] drv_context The driver context structure. + * \param[in,out] op_context A hardware-specific structure containing any + * context information for the implementation + * \param[in] kdf_alg The algorithm to be used for the key derivation + * \param[in] source_key The key to be used as the source material for + * the key derivation + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_key_derivation_setup_t)(psa_drv_se_context_t *drv_context, + void *op_context, + psa_algorithm_t kdf_alg, + psa_key_slot_number_t source_key); + +/** \brief A function that provides collateral (parameters) needed for a secure + * element key derivation or key agreement operation + * + * Since many key derivation algorithms require multiple parameters, it is + * expected that this function may be called multiple times for the same + * operation, each with a different algorithm-specific `collateral_id` + * + * \param[in,out] op_context A hardware-specific structure containing any + * context information for the implementation + * \param[in] collateral_id An ID for the collateral being provided + * \param[in] p_collateral A buffer containing the collateral data + * \param[in] collateral_size The size in bytes of the collateral + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_key_derivation_collateral_t)(void *op_context, + uint32_t collateral_id, + const uint8_t *p_collateral, + size_t collateral_size); + +/** \brief A function that performs the final secure element key derivation + * step and place the generated key material in a slot + * + * \param[in,out] op_context A hardware-specific structure containing any + * context information for the implementation + * \param[in] dest_key The slot where the generated key material + * should be placed + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_key_derivation_derive_t)(void *op_context, + psa_key_slot_number_t dest_key); + +/** \brief A function that performs the final step of a secure element key + * agreement and place the generated key material in a buffer + * + * \param[out] p_output Buffer in which to place the generated key + * material + * \param[in] output_size The size in bytes of `p_output` + * \param[out] p_output_length Upon success, contains the number of bytes of + * key material placed in `p_output` + * + * \retval #PSA_SUCCESS \emptydescription + */ +typedef psa_status_t (*psa_drv_se_key_derivation_export_t)(void *op_context, + uint8_t *p_output, + size_t output_size, + size_t *p_output_length); + +/** + * \brief A struct containing all of the function pointers needed to for secure + * element key derivation and agreement + * + * PSA Crypto API implementations should populate instances of the table as + * appropriate upon startup. + * + * If one of the functions is not implemented, it should be set to NULL. + */ +typedef struct { + /** The driver-specific size of the key derivation context */ + size_t MBEDTLS_PRIVATE(context_size); + /** Function that performs a key derivation setup */ + psa_drv_se_key_derivation_setup_t MBEDTLS_PRIVATE(p_setup); + /** Function that sets key derivation collateral */ + psa_drv_se_key_derivation_collateral_t MBEDTLS_PRIVATE(p_collateral); + /** Function that performs a final key derivation step */ + psa_drv_se_key_derivation_derive_t MBEDTLS_PRIVATE(p_derive); + /** Function that performs a final key derivation or agreement and + * exports the key */ + psa_drv_se_key_derivation_export_t MBEDTLS_PRIVATE(p_export); +} psa_drv_se_key_derivation_t; + +/**@}*/ + +/** \defgroup se_registration Secure element driver registration + */ +/**@{*/ + +/** A structure containing pointers to all the entry points of a + * secure element driver. + * + * Future versions of this specification may add extra substructures at + * the end of this structure. + */ +typedef struct { + /** The version of the driver HAL that this driver implements. + * This is a protection against loading driver binaries built against + * a different version of this specification. + * Use #PSA_DRV_SE_HAL_VERSION. + */ + uint32_t MBEDTLS_PRIVATE(hal_version); + + /** The size of the driver's persistent data in bytes. + * + * This can be 0 if the driver does not need persistent data. + * + * See the documentation of psa_drv_se_context_t::persistent_data + * for more information about why and how a driver can use + * persistent data. + */ + size_t MBEDTLS_PRIVATE(persistent_data_size); + + /** The driver initialization function. + * + * This function is called once during the initialization of the + * PSA Cryptography subsystem, before any other function of the + * driver is called. If this function returns a failure status, + * the driver will be unusable, at least until the next system reset. + * + * If this field is \c NULL, it is equivalent to a function that does + * nothing and returns #PSA_SUCCESS. + */ + psa_drv_se_init_t MBEDTLS_PRIVATE(p_init); + + const psa_drv_se_key_management_t *MBEDTLS_PRIVATE(key_management); + const psa_drv_se_mac_t *MBEDTLS_PRIVATE(mac); + const psa_drv_se_cipher_t *MBEDTLS_PRIVATE(cipher); + const psa_drv_se_aead_t *MBEDTLS_PRIVATE(aead); + const psa_drv_se_asymmetric_t *MBEDTLS_PRIVATE(asymmetric); + const psa_drv_se_key_derivation_t *MBEDTLS_PRIVATE(derivation); +} psa_drv_se_t; + +/** The current version of the secure element driver HAL. + */ +/* 0.0.0 patchlevel 5 */ +#define PSA_DRV_SE_HAL_VERSION 0x00000005 + +/** Register an external cryptoprocessor (secure element) driver. + * + * This function is only intended to be used by driver code, not by + * application code. In implementations with separation between the + * PSA cryptography module and applications, this function should + * only be available to callers that run in the same memory space as + * the cryptography module, and should not be exposed to applications + * running in a different memory space. + * + * This function may be called before psa_crypto_init(). It is + * implementation-defined whether this function may be called + * after psa_crypto_init(). + * + * \note Implementations store metadata about keys including the lifetime + * value, which contains the driver's location indicator. Therefore, + * from one instantiation of the PSA Cryptography + * library to the next one, if there is a key in storage with a certain + * lifetime value, you must always register the same driver (or an + * updated version that communicates with the same secure element) + * with the same location value. + * + * \param location The location value through which this driver will + * be exposed to applications. + * This driver will be used for all keys such that + * `location == #PSA_KEY_LIFETIME_GET_LOCATION( lifetime )`. + * The value #PSA_KEY_LOCATION_LOCAL_STORAGE is reserved + * and may not be used for drivers. Implementations + * may reserve other values. + * \param[in] methods The method table of the driver. This structure must + * remain valid for as long as the cryptography + * module keeps running. It is typically a global + * constant. + * + * \return #PSA_SUCCESS + * The driver was successfully registered. Applications can now + * use \p location to access keys through the methods passed to + * this function. + * \return #PSA_ERROR_BAD_STATE + * This function was called after the initialization of the + * cryptography module, and this implementation does not support + * driver registration at this stage. + * \return #PSA_ERROR_ALREADY_EXISTS + * There is already a registered driver for this value of \p location. + * \return #PSA_ERROR_INVALID_ARGUMENT + * \p location is a reserved value. + * \return #PSA_ERROR_NOT_SUPPORTED + * `methods->hal_version` is not supported by this implementation. + * \return #PSA_ERROR_INSUFFICIENT_MEMORY + * \return #PSA_ERROR_NOT_PERMITTED + * \return #PSA_ERROR_STORAGE_FAILURE + * \return #PSA_ERROR_DATA_CORRUPT + */ +psa_status_t psa_register_se_driver( + psa_key_location_t location, + const psa_drv_se_t *methods); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_SE_DRIVER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_sizes.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_sizes.h index 35983ce..c071688 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_sizes.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_sizes.h @@ -1,1303 +1,1303 @@ -/** - * \file psa/crypto_sizes.h - * - * \brief PSA cryptography module: Mbed TLS buffer size macros - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains the definitions of macros that are useful to - * compute buffer sizes. The signatures and semantics of these macros - * are standardized, but the definitions are not, because they depend on - * the available algorithms and, in some cases, on permitted tolerances - * on buffer sizes. - * - * In implementations with isolation between the application and the - * cryptography module, implementers should take care to ensure that - * the definitions that are exposed to applications match what the - * module implements. - * - * Macros that compute sizes whose values do not depend on the - * implementation are in crypto.h. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_sizes.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_sizes.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_SIZES_H -#define PSA_CRYPTO_SIZES_H - -/* - * Include the build-time configuration information file. Here, we do not - * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which - * is basically just an alias to it. This is to ease the maintenance of the - * PSA cryptography repository which has a different build system and - * configuration. - */ -#include "psa/build_info.h" - -#define PSA_BITS_TO_BYTES(bits) (((bits) + 7u) / 8u) -#define PSA_BYTES_TO_BITS(bytes) ((bytes) * 8u) -#define PSA_MAX_OF_THREE(a, b, c) ((a) <= (b) ? (b) <= (c) ? \ - (c) : (b) : (a) <= (c) ? (c) : (a)) - -#define PSA_ROUND_UP_TO_MULTIPLE(block_size, length) \ - (((length) + (block_size) - 1) / (block_size) * (block_size)) - -/** The size of the output of psa_hash_finish(), in bytes. - * - * This is also the hash size that psa_hash_verify() expects. - * - * \param alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p alg) is true), or an HMAC algorithm - * (#PSA_ALG_HMAC(\c hash_alg) where \c hash_alg is a - * hash algorithm). - * - * \return The hash size for the specified hash algorithm. - * If the hash algorithm is not recognized, return 0. - */ -#define PSA_HASH_LENGTH(alg) \ - ( \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 16u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 20u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 20u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 48u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 28u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 32u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 48u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 64u : \ - 0u) - -/** The input block size of a hash algorithm, in bytes. - * - * Hash algorithms process their input data in blocks. Hash operations will - * retain any partial blocks until they have enough input to fill the block or - * until the operation is finished. - * This affects the output from psa_hash_suspend(). - * - * \param alg A hash algorithm (\c PSA_ALG_XXX value such that - * PSA_ALG_IS_HASH(\p alg) is true). - * - * \return The block size in bytes for the specified hash algorithm. - * If the hash algorithm is not recognized, return 0. - * An implementation can return either 0 or the correct size for a - * hash algorithm that it recognizes, but does not support. - */ -#define PSA_HASH_BLOCK_LENGTH(alg) \ - ( \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 64u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 128u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 144u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 136u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 104u : \ - PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 72u : \ - 0u) - -/** \def PSA_HASH_MAX_SIZE - * - * Maximum size of a hash. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a hash in bytes. - */ -/* Note: for HMAC-SHA-3, the block size is 144 bytes for HMAC-SHA3-224, - * 136 bytes for HMAC-SHA3-256, 104 bytes for SHA3-384, 72 bytes for - * HMAC-SHA3-512. */ -/* Note: PSA_HASH_MAX_SIZE should be kept in sync with MBEDTLS_MD_MAX_SIZE, - * see the note on MBEDTLS_MD_MAX_SIZE for details. */ -#if defined(PSA_WANT_ALG_SHA3_224) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 144u -#elif defined(PSA_WANT_ALG_SHA3_256) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 136u -#elif defined(PSA_WANT_ALG_SHA_512) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u -#elif defined(PSA_WANT_ALG_SHA_384) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u -#elif defined(PSA_WANT_ALG_SHA3_384) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 104u -#elif defined(PSA_WANT_ALG_SHA3_512) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 72u -#elif defined(PSA_WANT_ALG_SHA_256) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#elif defined(PSA_WANT_ALG_SHA_224) -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#else /* SHA-1 or smaller */ -#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u -#endif - -#if defined(PSA_WANT_ALG_SHA_512) || defined(PSA_WANT_ALG_SHA3_512) -#define PSA_HASH_MAX_SIZE 64u -#elif defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA3_384) -#define PSA_HASH_MAX_SIZE 48u -#elif defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA3_256) -#define PSA_HASH_MAX_SIZE 32u -#elif defined(PSA_WANT_ALG_SHA_224) || defined(PSA_WANT_ALG_SHA3_224) -#define PSA_HASH_MAX_SIZE 28u -#else /* SHA-1 or smaller */ -#define PSA_HASH_MAX_SIZE 20u -#endif - -/** \def PSA_MAC_MAX_SIZE - * - * Maximum size of a MAC. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a MAC in bytes. - */ -/* All non-HMAC MACs have a maximum size that's smaller than the - * minimum possible value of PSA_HASH_MAX_SIZE in this implementation. */ -/* Note that the encoding of truncated MAC algorithms limits this value - * to 64 bytes. - */ -#define PSA_MAC_MAX_SIZE PSA_HASH_MAX_SIZE - -/** The length of a tag for an AEAD algorithm, in bytes. - * - * This macro can be used to allocate a buffer of sufficient size to store the - * tag output from psa_aead_finish(). - * - * See also #PSA_AEAD_TAG_MAX_SIZE. - * - * \param key_type The type of the AEAD key. - * \param key_bits The size of the AEAD key in bits. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return The tag length for the specified algorithm and key. - * If the AEAD algorithm does not have an identified - * tag that can be distinguished from the rest of - * the ciphertext, return 0. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_TAG_LENGTH(key_type, key_bits, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - ((void) (key_bits), 0u)) - -/** The maximum tag size for all supported AEAD algorithms, in bytes. - * - * See also #PSA_AEAD_TAG_LENGTH(\p key_type, \p key_bits, \p alg). - */ -#define PSA_AEAD_TAG_MAX_SIZE 16u - -/* The maximum size of an RSA key on this implementation, in bits. - * This is a vendor-specific macro. - * - * Mbed TLS does not set a hard limit on the size of RSA keys: any key - * whose parameters fit in a bignum is accepted. However large keys can - * induce a large memory usage and long computation times. Unlike other - * auxiliary macros in this file and in crypto.h, which reflect how the - * library is configured, this macro defines how the library is - * configured. This implementation refuses to import or generate an - * RSA key whose size is larger than the value defined here. - * - * Note that an implementation may set different size limits for different - * operations, and does not need to accept all key sizes up to the limit. */ -#define PSA_VENDOR_RSA_MAX_KEY_BITS 4096u - -/* The minimum size of an RSA key on this implementation, in bits. - * This is a vendor-specific macro. - * - * Limits RSA key generation to a minimum due to avoid accidental misuse. - * This value cannot be less than 128 bits. - */ -#if defined(MBEDTLS_RSA_GEN_KEY_MIN_BITS) -#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS MBEDTLS_RSA_GEN_KEY_MIN_BITS -#else -#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS 1024 -#endif - -/* The maximum size of an DH key on this implementation, in bits. - * - * Note that an implementation may set different size limits for different - * operations, and does not need to accept all key sizes up to the limit. */ -#define PSA_VENDOR_FFDH_MAX_KEY_BITS 8192u - -/* The maximum size of an ECC key on this implementation, in bits. - * This is a vendor-specific macro. */ -#if defined(PSA_WANT_ECC_SECP_R1_521) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 521u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 512u -#elif defined(PSA_WANT_ECC_MONTGOMERY_448) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 448u -#elif defined(PSA_WANT_ECC_SECP_R1_384) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u -#elif defined(PSA_WANT_ECC_SECP_R1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_SECP_K1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u -#elif defined(PSA_WANT_ECC_MONTGOMERY_255) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 255u -#elif defined(PSA_WANT_ECC_SECP_R1_224) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u -#elif defined(PSA_WANT_ECC_SECP_K1_224) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u -#elif defined(PSA_WANT_ECC_SECP_R1_192) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u -#elif defined(PSA_WANT_ECC_SECP_K1_192) -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u -#else -#define PSA_VENDOR_ECC_MAX_CURVE_BITS 0u -#endif - -/** This macro returns the maximum supported length of the PSK for the - * TLS-1.2 PSK-to-MS key derivation - * (#PSA_ALG_TLS12_PSK_TO_MS(\c hash_alg)). - * - * The maximum supported length does not depend on the chosen hash algorithm. - * - * Quoting RFC 4279, Sect 5.3: - * TLS implementations supporting these ciphersuites MUST support - * arbitrary PSK identities up to 128 octets in length, and arbitrary - * PSKs up to 64 octets in length. Supporting longer identities and - * keys is RECOMMENDED. - * - * Therefore, no implementation should define a value smaller than 64 - * for #PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE. - */ -#define PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE 128u - -/* The expected size of input passed to psa_tls12_ecjpake_to_pms_input, - * which is expected to work with P-256 curve only. */ -#define PSA_TLS12_ECJPAKE_TO_PMS_INPUT_SIZE 65u - -/* The size of a serialized K.X coordinate to be used in - * psa_tls12_ecjpake_to_pms_input. This function only accepts the P-256 - * curve. */ -#define PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE 32u - -/* The maximum number of iterations for PBKDF2 on this implementation, in bits. - * This is a vendor-specific macro. This can be configured if necessary */ -#define PSA_VENDOR_PBKDF2_MAX_ITERATIONS (0xffffffffu - 1) - -/** The maximum size of a block cipher. */ -#define PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE 16u - -/** The size of the output of psa_mac_sign_finish(), in bytes. - * - * This is also the MAC size that psa_mac_verify_finish() expects. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type The type of the MAC key. - * \param key_bits The size of the MAC key in bits. - * \param alg A MAC algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_MAC(\p alg) is true). - * - * \return The MAC size for the specified algorithm with - * the specified key parameters. - * \return 0 if the MAC algorithm is not recognized. - * \return Either 0 or the correct size for a MAC algorithm that - * the implementation recognizes, but does not support. - * \return Unspecified if the key parameters are not consistent - * with the algorithm. - */ -#define PSA_MAC_LENGTH(key_type, key_bits, alg) \ - ((alg) & PSA_ALG_MAC_TRUNCATION_MASK ? PSA_MAC_TRUNCATED_LENGTH(alg) : \ - PSA_ALG_IS_HMAC(alg) ? PSA_HASH_LENGTH(PSA_ALG_HMAC_GET_HASH(alg)) : \ - PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - ((void) (key_type), (void) (key_bits), 0u)) - -/** The maximum size of the output of psa_aead_encrypt(), in bytes. - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_aead_encrypt() will not fail due to an - * insufficient buffer size. Depending on the algorithm, the actual size of - * the ciphertext may be smaller. - * - * See also #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param plaintext_length Size of the plaintext in bytes. - * - * \return The AEAD ciphertext size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_ENCRYPT_OUTPUT_SIZE(key_type, alg, plaintext_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - (plaintext_length) + PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_encrypt(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the ciphertext buffer is at least this large, it is guaranteed - * that psa_aead_encrypt() will not fail due to an insufficient buffer size. - * - * \note This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * See also #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, - * \p plaintext_length). - * - * \param plaintext_length Size of the plaintext in bytes. - * - * \return A sufficient output buffer size for any of the - * supported key types and AEAD algorithms. - * - */ -#define PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(plaintext_length) \ - ((plaintext_length) + PSA_AEAD_TAG_MAX_SIZE) - - -/** The maximum size of the output of psa_aead_decrypt(), in bytes. - * - * If the size of the plaintext buffer is at least this large, it is - * guaranteed that psa_aead_decrypt() will not fail due to an - * insufficient buffer size. Depending on the algorithm, the actual size of - * the plaintext may be smaller. - * - * See also #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param ciphertext_length Size of the plaintext in bytes. - * - * \return The AEAD ciphertext size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_DECRYPT_OUTPUT_SIZE(key_type, alg, ciphertext_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - (ciphertext_length) > PSA_ALG_AEAD_GET_TAG_LENGTH(alg) ? \ - (ciphertext_length) - PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_decrypt(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the plaintext buffer is at least this large, it is guaranteed - * that psa_aead_decrypt() will not fail due to an insufficient buffer size. - * - * \note This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * See also #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, - * \p ciphertext_length). - * - * \param ciphertext_length Size of the ciphertext in bytes. - * - * \return A sufficient output buffer size for any of the - * supported key types and AEAD algorithms. - * - */ -#define PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(ciphertext_length) \ - (ciphertext_length) - -/** The default nonce size for an AEAD algorithm, in bytes. - * - * This macro can be used to allocate a buffer of sufficient size to - * store the nonce output from #psa_aead_generate_nonce(). - * - * See also #PSA_AEAD_NONCE_MAX_SIZE. - * - * \note This is not the maximum size of nonce supported as input to - * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), - * just the default size that is generated by #psa_aead_generate_nonce(). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with - * algorithm \p alg. - * - * \param alg An AEAD algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return The default nonce size for the specified key type and algorithm. - * If the key type or AEAD algorithm is not recognized, - * or the parameters are incompatible, return 0. - */ -#define PSA_AEAD_NONCE_LENGTH(key_type, alg) \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) == 16 ? \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CCM) ? 13u : \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_GCM) ? 12u : \ - 0u : \ - (key_type) == PSA_KEY_TYPE_CHACHA20 && \ - MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CHACHA20_POLY1305) ? 12u : \ - 0u) - -/** The maximum default nonce size among all supported pairs of key types and - * AEAD algorithms, in bytes. - * - * This is equal to or greater than any value that #PSA_AEAD_NONCE_LENGTH() - * may return. - * - * \note This is not the maximum size of nonce supported as input to - * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), - * just the largest size that may be generated by - * #psa_aead_generate_nonce(). - */ -#define PSA_AEAD_NONCE_MAX_SIZE 13u - -/** A sufficient output buffer size for psa_aead_update(). - * - * If the size of the output buffer is at least this large, it is - * guaranteed that psa_aead_update() will not fail due to an - * insufficient buffer size. The actual size of the output may be smaller - * in any given call. - * - * See also #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output buffer size for the specified - * algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -/* For all the AEAD modes defined in this specification, it is possible - * to emit output without delay. However, hardware may not always be - * capable of this. So for modes based on a block cipher, allow the - * implementation to delay the output until it has a full block. */ -#define PSA_AEAD_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), (input_length)) : \ - (input_length) : \ - 0u) - -/** A sufficient output buffer size for psa_aead_update(), for any of the - * supported key types and AEAD algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_aead_update() will not fail due to an insufficient buffer size. - * - * See also #PSA_AEAD_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, (input_length))) - -/** A sufficient ciphertext buffer size for psa_aead_finish(). - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_aead_finish() will not fail due to an - * insufficient ciphertext buffer size. The actual size of the output may - * be smaller in any given call. - * - * See also #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE. - * - * \param key_type A symmetric key type that is - compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return A sufficient ciphertext buffer size for the - * specified algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_FINISH_OUTPUT_SIZE(key_type, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) - -/** A sufficient ciphertext buffer size for psa_aead_finish(), for any of the - * supported key types and AEAD algorithms. - * - * See also #PSA_AEAD_FINISH_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_AEAD_FINISH_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -/** A sufficient plaintext buffer size for psa_aead_verify(). - * - * If the size of the plaintext buffer is at least this large, it is - * guaranteed that psa_aead_verify() will not fail due to an - * insufficient plaintext buffer size. The actual size of the output may - * be smaller in any given call. - * - * See also #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE. - * - * \param key_type A symmetric key type that is - * compatible with algorithm \p alg. - * \param alg An AEAD algorithm - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \return A sufficient plaintext buffer size for the - * specified algorithm. - * If the key type or AEAD algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_AEAD_VERIFY_OUTPUT_SIZE(key_type, alg) \ - (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ - PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) - -/** A sufficient plaintext buffer size for psa_aead_verify(), for any of the - * supported key types and AEAD algorithms. - * - * See also #PSA_AEAD_VERIFY_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -#define PSA_RSA_MINIMUM_PADDING_SIZE(alg) \ - (PSA_ALG_IS_RSA_OAEP(alg) ? \ - 2u * PSA_HASH_LENGTH(PSA_ALG_RSA_OAEP_GET_HASH(alg)) + 1u : \ - 11u /*PKCS#1v1.5*/) - -/** - * \brief ECDSA signature size for a given curve bit size - * - * \param curve_bits Curve size in bits. - * \return Signature size in bytes. - * - * \note This macro returns a compile-time constant if its argument is one. - */ -#define PSA_ECDSA_SIGNATURE_SIZE(curve_bits) \ - (PSA_BITS_TO_BYTES(curve_bits) * 2u) - -/** Sufficient signature buffer size for psa_sign_hash(). - * - * This macro returns a sufficient buffer size for a signature using a key - * of the specified type and size, with the specified algorithm. - * Note that the actual size of the signature may be smaller - * (some algorithms produce a variable-size signature). - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The signature algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_sign_hash() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_SIGN_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ - PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_ECDSA_SIGNATURE_SIZE(key_bits) : \ - ((void) alg, 0u)) - -#define PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE \ - PSA_ECDSA_SIGNATURE_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) - -/** \def PSA_SIGNATURE_MAX_SIZE - * - * Maximum size of an asymmetric signature. - * - * This macro expands to a compile-time constant integer. This value - * is the maximum size of a signature in bytes. - */ -#define PSA_SIGNATURE_MAX_SIZE 1 - -#if (defined(PSA_WANT_ALG_ECDSA) || defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA)) && \ - (PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE > PSA_SIGNATURE_MAX_SIZE) -#undef PSA_SIGNATURE_MAX_SIZE -#define PSA_SIGNATURE_MAX_SIZE PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE -#endif -#if (defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) || defined(PSA_WANT_ALG_RSA_PSS)) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) > PSA_SIGNATURE_MAX_SIZE) -#undef PSA_SIGNATURE_MAX_SIZE -#define PSA_SIGNATURE_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif - -/** Sufficient output buffer size for psa_asymmetric_encrypt(). - * - * This macro returns a sufficient buffer size for a ciphertext produced using - * a key of the specified type and size, with the specified algorithm. - * Note that the actual size of the ciphertext may be smaller, depending - * on the algorithm. - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The asymmetric encryption algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_asymmetric_encrypt() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? \ - ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ - 0u) - -/** A sufficient output buffer size for psa_asymmetric_encrypt(), for any - * supported asymmetric encryption. - * - * See also #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). - */ -/* This macro assumes that RSA is the only supported asymmetric encryption. */ -#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_MAX_SIZE \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) - -/** Sufficient output buffer size for psa_asymmetric_decrypt(). - * - * This macro returns a sufficient buffer size for a plaintext produced using - * a key of the specified type and size, with the specified algorithm. - * Note that the actual size of the plaintext may be smaller, depending - * on the algorithm. - * - * \warning This function may call its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type An asymmetric key type (this may indifferently be a - * key pair type or a public key type). - * \param key_bits The size of the key in bits. - * \param alg The asymmetric encryption algorithm. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_asymmetric_decrypt() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the - * return value is unspecified. - */ -#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? \ - PSA_BITS_TO_BYTES(key_bits) - PSA_RSA_MINIMUM_PADDING_SIZE(alg) : \ - 0u) - -/** A sufficient output buffer size for psa_asymmetric_decrypt(), for any - * supported asymmetric decryption. - * - * This macro assumes that RSA is the only supported asymmetric encryption. - * - * See also #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). - */ -#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_MAX_SIZE \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) - -/* Maximum size of the ASN.1 encoding of an INTEGER with the specified - * number of bits. - * - * This definition assumes that bits <= 2^19 - 9 so that the length field - * is at most 3 bytes. The length of the encoding is the length of the - * bit string padded to a whole number of bytes plus: - * - 1 type byte; - * - 1 to 3 length bytes; - * - 0 to 1 bytes of leading 0 due to the sign bit. - */ -#define PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(bits) \ - ((bits) / 8u + 5u) - -/* Maximum size of the export encoding of an RSA public key. - * Assumes that the public exponent is less than 2^32. - * - * RSAPublicKey ::= SEQUENCE { - * modulus INTEGER, -- n - * publicExponent INTEGER } -- e - * - * - 4 bytes of SEQUENCE overhead; - * - n : INTEGER; - * - 7 bytes for the public exponent. - */ -#define PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) + 11u) - -/* Maximum size of the export encoding of an RSA key pair. - * Assumes that the public exponent is less than 2^32 and that the size - * difference between the two primes is at most 1 bit. - * - * RSAPrivateKey ::= SEQUENCE { - * version Version, -- 0 - * modulus INTEGER, -- N-bit - * publicExponent INTEGER, -- 32-bit - * privateExponent INTEGER, -- N-bit - * prime1 INTEGER, -- N/2-bit - * prime2 INTEGER, -- N/2-bit - * exponent1 INTEGER, -- N/2-bit - * exponent2 INTEGER, -- N/2-bit - * coefficient INTEGER, -- N/2-bit - * } - * - * - 4 bytes of SEQUENCE overhead; - * - 3 bytes of version; - * - 7 half-size INTEGERs plus 2 full-size INTEGERs, - * overapproximated as 9 half-size INTEGERS; - * - 7 bytes for the public exponent. - */ -#define PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) \ - (9u * PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE((key_bits) / 2u + 1u) + 14u) - -/* Maximum size of the export encoding of a DSA public key. - * - * SubjectPublicKeyInfo ::= SEQUENCE { - * algorithm AlgorithmIdentifier, - * subjectPublicKey BIT STRING } -- contains DSAPublicKey - * AlgorithmIdentifier ::= SEQUENCE { - * algorithm OBJECT IDENTIFIER, - * parameters Dss-Params } -- SEQUENCE of 3 INTEGERs - * DSAPublicKey ::= INTEGER -- public key, Y - * - * - 3 * 4 bytes of SEQUENCE overhead; - * - 1 + 1 + 7 bytes of algorithm (DSA OID); - * - 4 bytes of BIT STRING overhead; - * - 3 full-size INTEGERs (p, g, y); - * - 1 + 1 + 32 bytes for 1 sub-size INTEGER (q <= 256 bits). - */ -#define PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 59u) - -/* Maximum size of the export encoding of a DSA key pair. - * - * DSAPrivateKey ::= SEQUENCE { - * version Version, -- 0 - * prime INTEGER, -- p - * subprime INTEGER, -- q - * generator INTEGER, -- g - * public INTEGER, -- y - * private INTEGER, -- x - * } - * - * - 4 bytes of SEQUENCE overhead; - * - 3 bytes of version; - * - 3 full-size INTEGERs (p, g, y); - * - 2 * (1 + 1 + 32) bytes for 2 sub-size INTEGERs (q, x <= 256 bits). - */ -#define PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 75u) - -/* Maximum size of the export encoding of an ECC public key. - * - * The representation of an ECC public key is: - * - The byte 0x04; - * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; - * - `y_P` as a `ceiling(m/8)`-byte string, big-endian; - * - where m is the bit size associated with the curve. - * - * - 1 byte + 2 * point size. - */ -#define PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (2u * PSA_BITS_TO_BYTES(key_bits) + 1u) - -/* Maximum size of the export encoding of an ECC key pair. - * - * An ECC key pair is represented by the secret value. - */ -#define PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/* Maximum size of the export encoding of an DH key pair. - * - * An DH key pair is represented by the secret value. - */ -#define PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/* Maximum size of the export encoding of an DH public key. - */ -#define PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(key_bits) \ - (PSA_BITS_TO_BYTES(key_bits)) - -/** Sufficient output buffer size for psa_export_key() or - * psa_export_public_key(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * The following code illustrates how to allocate enough memory to export - * a key by querying the key type and size at runtime. - * \code{c} - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * psa_status_t status; - * status = psa_get_key_attributes(key, &attributes); - * if (status != PSA_SUCCESS) handle_error(...); - * psa_key_type_t key_type = psa_get_key_type(&attributes); - * size_t key_bits = psa_get_key_bits(&attributes); - * size_t buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits); - * psa_reset_key_attributes(&attributes); - * uint8_t *buffer = malloc(buffer_size); - * if (buffer == NULL) handle_error(...); - * size_t buffer_length; - * status = psa_export_key(key, buffer, buffer_size, &buffer_length); - * if (status != PSA_SUCCESS) handle_error(...); - * \endcode - * - * \param key_type A supported key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_export_key() or psa_export_public_key() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not supported, - * return either a sensible size or 0. - * If the parameters are not valid, the return value is unspecified. - */ -#define PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits) \ - (PSA_KEY_TYPE_IS_UNSTRUCTURED(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - (key_type) == PSA_KEY_TYPE_RSA_KEY_PAIR ? PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_DSA_KEY_PAIR ? PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) : \ - (key_type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY ? PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) ? PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - 0u) - -/** Sufficient output buffer size for psa_export_public_key(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * The following code illustrates how to allocate enough memory to export - * a public key by querying the key type and size at runtime. - * \code{c} - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * psa_status_t status; - * status = psa_get_key_attributes(key, &attributes); - * if (status != PSA_SUCCESS) handle_error(...); - * psa_key_type_t key_type = psa_get_key_type(&attributes); - * size_t key_bits = psa_get_key_bits(&attributes); - * size_t buffer_size = PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits); - * psa_reset_key_attributes(&attributes); - * uint8_t *buffer = malloc(buffer_size); - * if (buffer == NULL) handle_error(...); - * size_t buffer_length; - * status = psa_export_public_key(key, buffer, buffer_size, &buffer_length); - * if (status != PSA_SUCCESS) handle_error(...); - * \endcode - * - * \param key_type A public key or key pair key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_export_public_key() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that is not - * supported, return either a sensible size or 0. - * If the parameters are not valid, - * the return value is unspecified. - * - * If the parameters are valid and supported, - * return the same result as - * #PSA_EXPORT_KEY_OUTPUT_SIZE( - * \p #PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\p key_type), - * \p key_bits). - */ -#define PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits) \ - (PSA_KEY_TYPE_IS_RSA(key_type) ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ - PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ - 0u) - -/** Sufficient buffer size for exporting any asymmetric key pair. - * - * This macro expands to a compile-time constant integer. This value is - * a sufficient buffer size when calling psa_export_key() to export any - * asymmetric key pair, regardless of the exact key type and key size. - * - * See also #PSA_EXPORT_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE 1 - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) && \ - (PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ - PSA_EXPORT_KEY_PAIR_MAX_SIZE) -#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE -#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ - PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** Sufficient buffer size for exporting any asymmetric public key. - * - * This macro expands to a compile-time constant integer. This value is - * a sufficient buffer size when calling psa_export_key() or - * psa_export_public_key() to export any asymmetric public key, - * regardless of the exact key type and key size. - * - * See also #PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE 1 - -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) -#endif -#if defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) && \ - (PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ - PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) -#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE -#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ - PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** Sufficient output buffer size for psa_raw_key_agreement(). - * - * This macro returns a compile-time constant if its arguments are - * compile-time constants. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE. - * - * \param key_type A supported key type. - * \param key_bits The size of the key in bits. - * - * \return If the parameters are valid and supported, return - * a buffer size in bytes that guarantees that - * psa_raw_key_agreement() will not fail with - * #PSA_ERROR_BUFFER_TOO_SMALL. - * If the parameters are a valid combination that - * is not supported, return either a sensible size or 0. - * If the parameters are not valid, - * the return value is unspecified. - */ -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(key_type, key_bits) \ - ((PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) || \ - PSA_KEY_TYPE_IS_DH_KEY_PAIR(key_type)) ? PSA_BITS_TO_BYTES(key_bits) : 0u) - -/** Maximum size of the output from psa_raw_key_agreement(). - * - * This macro expands to a compile-time constant integer. This value is the - * maximum size of the output any raw key agreement algorithm, in bytes. - * - * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(\p key_type, \p key_bits). - */ -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE 1 - -#if defined(PSA_WANT_ALG_ECDH) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) -#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) -#endif -#if defined(PSA_WANT_ALG_FFDH) && \ - (PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) -#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE -#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) -#endif - -/** The default IV size for a cipher algorithm, in bytes. - * - * The IV that is generated as part of a call to #psa_cipher_encrypt() is always - * the default IV length for the algorithm. - * - * This macro can be used to allocate a buffer of sufficient size to - * store the IV output from #psa_cipher_generate_iv() when using - * a multi-part cipher operation. - * - * See also #PSA_CIPHER_IV_MAX_SIZE. - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with algorithm \p alg. - * - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \return The default IV size for the specified key type and algorithm. - * If the algorithm does not use an IV, return 0. - * If the key type or cipher algorithm is not recognized, - * or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_IV_LENGTH(key_type, alg) \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) > 1 && \ - ((alg) == PSA_ALG_CTR || \ - (alg) == PSA_ALG_CFB || \ - (alg) == PSA_ALG_OFB || \ - (alg) == PSA_ALG_XTS || \ - (alg) == PSA_ALG_CBC_NO_PADDING || \ - (alg) == PSA_ALG_CBC_PKCS7) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - (key_type) == PSA_KEY_TYPE_CHACHA20 && \ - (alg) == PSA_ALG_STREAM_CIPHER ? 12u : \ - (alg) == PSA_ALG_CCM_STAR_NO_TAG ? 13u : \ - 0u) - -/** The maximum IV size for all supported cipher algorithms, in bytes. - * - * See also #PSA_CIPHER_IV_LENGTH(). - */ -#define PSA_CIPHER_IV_MAX_SIZE 16u - -/** The maximum size of the output of psa_cipher_encrypt(), in bytes. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. - * Depending on the algorithm, the actual size of the output might be smaller. - * - * See also #PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(\p input_length). - * - * \warning This macro may evaluate its arguments multiple times or - * zero times, so you should not pass arguments that contain - * side effects. - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ - (alg == PSA_ALG_CBC_PKCS7 ? \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ - (input_length) + 1u) + \ - PSA_CIPHER_IV_LENGTH((key_type), (alg)) : 0u) : \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (input_length) + PSA_CIPHER_IV_LENGTH((key_type), (alg)) : \ - 0u)) - -/** A sufficient output buffer size for psa_cipher_encrypt(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - * - */ -#define PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, \ - (input_length) + 1u) + \ - PSA_CIPHER_IV_MAX_SIZE) - -/** The maximum size of the output of psa_cipher_decrypt(), in bytes. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. - * Depending on the algorithm, the actual size of the output might be smaller. - * - * See also #PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(\p input_length). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, - * return 0. - */ -#define PSA_CIPHER_DECRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_ALG_IS_CIPHER(alg) && \ - ((key_type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ - (input_length) : \ - 0u) - -/** A sufficient output buffer size for psa_cipher_decrypt(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(input_length) \ - (input_length) - -/** A sufficient output buffer size for psa_cipher_update(). - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_update() will not fail due to an insufficient buffer size. - * The actual size of the output might be smaller in any given call. - * - * See also #PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(\p input_length). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param input_length Size of the input in bytes. - * - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ - (((alg) == PSA_ALG_CBC_PKCS7 || \ - (alg) == PSA_ALG_CBC_NO_PADDING || \ - (alg) == PSA_ALG_ECB_NO_PADDING) ? \ - PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ - input_length) : \ - (input_length)) : 0u) : \ - 0u) - -/** A sufficient output buffer size for psa_cipher_update(), for any of the - * supported key types and cipher algorithms. - * - * If the size of the output buffer is at least this large, it is guaranteed - * that psa_cipher_update() will not fail due to an insufficient buffer size. - * - * See also #PSA_CIPHER_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). - * - * \param input_length Size of the input in bytes. - */ -#define PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(input_length) \ - (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, input_length)) - -/** A sufficient ciphertext buffer size for psa_cipher_finish(). - * - * If the size of the ciphertext buffer is at least this large, it is - * guaranteed that psa_cipher_finish() will not fail due to an insufficient - * ciphertext buffer size. The actual size of the output might be smaller in - * any given call. - * - * See also #PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE(). - * - * \param key_type A symmetric key type that is compatible with algorithm - * alg. - * \param alg A cipher algorithm (PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \return A sufficient output size for the specified key type and - * algorithm. If the key type or cipher algorithm is not - * recognized, or the parameters are incompatible, return 0. - */ -#define PSA_CIPHER_FINISH_OUTPUT_SIZE(key_type, alg) \ - (PSA_ALG_IS_CIPHER(alg) ? \ - (alg == PSA_ALG_CBC_PKCS7 ? \ - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ - 0u) : \ - 0u) - -/** A sufficient ciphertext buffer size for psa_cipher_finish(), for any of the - * supported key types and cipher algorithms. - * - * See also #PSA_CIPHER_FINISH_OUTPUT_SIZE(\p key_type, \p alg). - */ -#define PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE \ - (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) - -#endif /* PSA_CRYPTO_SIZES_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_sizes.h + * + * \brief PSA cryptography module: Mbed TLS buffer size macros + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * This file contains the definitions of macros that are useful to + * compute buffer sizes. The signatures and semantics of these macros + * are standardized, but the definitions are not, because they depend on + * the available algorithms and, in some cases, on permitted tolerances + * on buffer sizes. + * + * In implementations with isolation between the application and the + * cryptography module, implementers should take care to ensure that + * the definitions that are exposed to applications match what the + * module implements. + * + * Macros that compute sizes whose values do not depend on the + * implementation are in crypto.h. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_sizes.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_sizes.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_SIZES_H +#define PSA_CRYPTO_SIZES_H + +/* + * Include the build-time configuration information file. Here, we do not + * include `"mbedtls/build_info.h"` directly but `"psa/build_info.h"`, which + * is basically just an alias to it. This is to ease the maintenance of the + * PSA cryptography repository which has a different build system and + * configuration. + */ +#include "psa/build_info.h" + +#define PSA_BITS_TO_BYTES(bits) (((bits) + 7u) / 8u) +#define PSA_BYTES_TO_BITS(bytes) ((bytes) * 8u) +#define PSA_MAX_OF_THREE(a, b, c) ((a) <= (b) ? (b) <= (c) ? \ + (c) : (b) : (a) <= (c) ? (c) : (a)) + +#define PSA_ROUND_UP_TO_MULTIPLE(block_size, length) \ + (((length) + (block_size) - 1) / (block_size) * (block_size)) + +/** The size of the output of psa_hash_finish(), in bytes. + * + * This is also the hash size that psa_hash_verify() expects. + * + * \param alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p alg) is true), or an HMAC algorithm + * (#PSA_ALG_HMAC(\c hash_alg) where \c hash_alg is a + * hash algorithm). + * + * \return The hash size for the specified hash algorithm. + * If the hash algorithm is not recognized, return 0. + */ +#define PSA_HASH_LENGTH(alg) \ + ( \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 16u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 20u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 20u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 28u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 32u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 48u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 28u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 32u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 28u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 32u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 48u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 64u : \ + 0u) + +/** The input block size of a hash algorithm, in bytes. + * + * Hash algorithms process their input data in blocks. Hash operations will + * retain any partial blocks until they have enough input to fill the block or + * until the operation is finished. + * This affects the output from psa_hash_suspend(). + * + * \param alg A hash algorithm (\c PSA_ALG_XXX value such that + * PSA_ALG_IS_HASH(\p alg) is true). + * + * \return The block size in bytes for the specified hash algorithm. + * If the hash algorithm is not recognized, return 0. + * An implementation can return either 0 or the correct size for a + * hash algorithm that it recognizes, but does not support. + */ +#define PSA_HASH_BLOCK_LENGTH(alg) \ + ( \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_MD5 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_RIPEMD160 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_1 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_224 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_256 ? 64u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_384 ? 128u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512 ? 128u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_224 ? 128u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA_512_256 ? 128u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_224 ? 144u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_256 ? 136u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_384 ? 104u : \ + PSA_ALG_HMAC_GET_HASH(alg) == PSA_ALG_SHA3_512 ? 72u : \ + 0u) + +/** \def PSA_HASH_MAX_SIZE + * + * Maximum size of a hash. + * + * This macro expands to a compile-time constant integer. This value + * is the maximum size of a hash in bytes. + */ +/* Note: for HMAC-SHA-3, the block size is 144 bytes for HMAC-SHA3-224, + * 136 bytes for HMAC-SHA3-256, 104 bytes for SHA3-384, 72 bytes for + * HMAC-SHA3-512. */ +/* Note: PSA_HASH_MAX_SIZE should be kept in sync with MBEDTLS_MD_MAX_SIZE, + * see the note on MBEDTLS_MD_MAX_SIZE for details. */ +#if defined(PSA_WANT_ALG_SHA3_224) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 144u +#elif defined(PSA_WANT_ALG_SHA3_256) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 136u +#elif defined(PSA_WANT_ALG_SHA_512) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u +#elif defined(PSA_WANT_ALG_SHA_384) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 128u +#elif defined(PSA_WANT_ALG_SHA3_384) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 104u +#elif defined(PSA_WANT_ALG_SHA3_512) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 72u +#elif defined(PSA_WANT_ALG_SHA_256) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u +#elif defined(PSA_WANT_ALG_SHA_224) +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u +#else /* SHA-1 or smaller */ +#define PSA_HMAC_MAX_HASH_BLOCK_SIZE 64u +#endif + +#if defined(PSA_WANT_ALG_SHA_512) || defined(PSA_WANT_ALG_SHA3_512) +#define PSA_HASH_MAX_SIZE 64u +#elif defined(PSA_WANT_ALG_SHA_384) || defined(PSA_WANT_ALG_SHA3_384) +#define PSA_HASH_MAX_SIZE 48u +#elif defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA3_256) +#define PSA_HASH_MAX_SIZE 32u +#elif defined(PSA_WANT_ALG_SHA_224) || defined(PSA_WANT_ALG_SHA3_224) +#define PSA_HASH_MAX_SIZE 28u +#else /* SHA-1 or smaller */ +#define PSA_HASH_MAX_SIZE 20u +#endif + +/** \def PSA_MAC_MAX_SIZE + * + * Maximum size of a MAC. + * + * This macro expands to a compile-time constant integer. This value + * is the maximum size of a MAC in bytes. + */ +/* All non-HMAC MACs have a maximum size that's smaller than the + * minimum possible value of PSA_HASH_MAX_SIZE in this implementation. */ +/* Note that the encoding of truncated MAC algorithms limits this value + * to 64 bytes. + */ +#define PSA_MAC_MAX_SIZE PSA_HASH_MAX_SIZE + +/** The length of a tag for an AEAD algorithm, in bytes. + * + * This macro can be used to allocate a buffer of sufficient size to store the + * tag output from psa_aead_finish(). + * + * See also #PSA_AEAD_TAG_MAX_SIZE. + * + * \param key_type The type of the AEAD key. + * \param key_bits The size of the AEAD key in bits. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \return The tag length for the specified algorithm and key. + * If the AEAD algorithm does not have an identified + * tag that can be distinguished from the rest of + * the ciphertext, return 0. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_AEAD_TAG_LENGTH(key_type, key_bits, alg) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ + PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ + ((void) (key_bits), 0u)) + +/** The maximum tag size for all supported AEAD algorithms, in bytes. + * + * See also #PSA_AEAD_TAG_LENGTH(\p key_type, \p key_bits, \p alg). + */ +#define PSA_AEAD_TAG_MAX_SIZE 16u + +/* The maximum size of an RSA key on this implementation, in bits. + * This is a vendor-specific macro. + * + * Mbed TLS does not set a hard limit on the size of RSA keys: any key + * whose parameters fit in a bignum is accepted. However large keys can + * induce a large memory usage and long computation times. Unlike other + * auxiliary macros in this file and in crypto.h, which reflect how the + * library is configured, this macro defines how the library is + * configured. This implementation refuses to import or generate an + * RSA key whose size is larger than the value defined here. + * + * Note that an implementation may set different size limits for different + * operations, and does not need to accept all key sizes up to the limit. */ +#define PSA_VENDOR_RSA_MAX_KEY_BITS 4096u + +/* The minimum size of an RSA key on this implementation, in bits. + * This is a vendor-specific macro. + * + * Limits RSA key generation to a minimum due to avoid accidental misuse. + * This value cannot be less than 128 bits. + */ +#if defined(MBEDTLS_RSA_GEN_KEY_MIN_BITS) +#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS MBEDTLS_RSA_GEN_KEY_MIN_BITS +#else +#define PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS 1024 +#endif + +/* The maximum size of an DH key on this implementation, in bits. + * + * Note that an implementation may set different size limits for different + * operations, and does not need to accept all key sizes up to the limit. */ +#define PSA_VENDOR_FFDH_MAX_KEY_BITS 8192u + +/* The maximum size of an ECC key on this implementation, in bits. + * This is a vendor-specific macro. */ +#if defined(PSA_WANT_ECC_SECP_R1_521) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 521u +#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 512u +#elif defined(PSA_WANT_ECC_MONTGOMERY_448) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 448u +#elif defined(PSA_WANT_ECC_SECP_R1_384) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u +#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 384u +#elif defined(PSA_WANT_ECC_SECP_R1_256) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u +#elif defined(PSA_WANT_ECC_SECP_K1_256) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u +#elif defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 256u +#elif defined(PSA_WANT_ECC_MONTGOMERY_255) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 255u +#elif defined(PSA_WANT_ECC_SECP_R1_224) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u +#elif defined(PSA_WANT_ECC_SECP_K1_224) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 224u +#elif defined(PSA_WANT_ECC_SECP_R1_192) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u +#elif defined(PSA_WANT_ECC_SECP_K1_192) +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 192u +#else +#define PSA_VENDOR_ECC_MAX_CURVE_BITS 0u +#endif + +/** This macro returns the maximum supported length of the PSK for the + * TLS-1.2 PSK-to-MS key derivation + * (#PSA_ALG_TLS12_PSK_TO_MS(\c hash_alg)). + * + * The maximum supported length does not depend on the chosen hash algorithm. + * + * Quoting RFC 4279, Sect 5.3: + * TLS implementations supporting these ciphersuites MUST support + * arbitrary PSK identities up to 128 octets in length, and arbitrary + * PSKs up to 64 octets in length. Supporting longer identities and + * keys is RECOMMENDED. + * + * Therefore, no implementation should define a value smaller than 64 + * for #PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE. + */ +#define PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE 128u + +/* The expected size of input passed to psa_tls12_ecjpake_to_pms_input, + * which is expected to work with P-256 curve only. */ +#define PSA_TLS12_ECJPAKE_TO_PMS_INPUT_SIZE 65u + +/* The size of a serialized K.X coordinate to be used in + * psa_tls12_ecjpake_to_pms_input. This function only accepts the P-256 + * curve. */ +#define PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE 32u + +/* The maximum number of iterations for PBKDF2 on this implementation, in bits. + * This is a vendor-specific macro. This can be configured if necessary */ +#define PSA_VENDOR_PBKDF2_MAX_ITERATIONS (0xffffffffu - 1) + +/** The maximum size of a block cipher. */ +#define PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE 16u + +/** The size of the output of psa_mac_sign_finish(), in bytes. + * + * This is also the MAC size that psa_mac_verify_finish() expects. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type The type of the MAC key. + * \param key_bits The size of the MAC key in bits. + * \param alg A MAC algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_MAC(\p alg) is true). + * + * \return The MAC size for the specified algorithm with + * the specified key parameters. + * \return 0 if the MAC algorithm is not recognized. + * \return Either 0 or the correct size for a MAC algorithm that + * the implementation recognizes, but does not support. + * \return Unspecified if the key parameters are not consistent + * with the algorithm. + */ +#define PSA_MAC_LENGTH(key_type, key_bits, alg) \ + ((alg) & PSA_ALG_MAC_TRUNCATION_MASK ? PSA_MAC_TRUNCATED_LENGTH(alg) : \ + PSA_ALG_IS_HMAC(alg) ? PSA_HASH_LENGTH(PSA_ALG_HMAC_GET_HASH(alg)) : \ + PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ + ((void) (key_type), (void) (key_bits), 0u)) + +/** The maximum size of the output of psa_aead_encrypt(), in bytes. + * + * If the size of the ciphertext buffer is at least this large, it is + * guaranteed that psa_aead_encrypt() will not fail due to an + * insufficient buffer size. Depending on the algorithm, the actual size of + * the ciphertext may be smaller. + * + * See also #PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(\p plaintext_length). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is + * compatible with algorithm \p alg. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * \param plaintext_length Size of the plaintext in bytes. + * + * \return The AEAD ciphertext size for the specified + * algorithm. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_AEAD_ENCRYPT_OUTPUT_SIZE(key_type, alg, plaintext_length) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ + (plaintext_length) + PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ + 0u) + +/** A sufficient output buffer size for psa_aead_encrypt(), for any of the + * supported key types and AEAD algorithms. + * + * If the size of the ciphertext buffer is at least this large, it is guaranteed + * that psa_aead_encrypt() will not fail due to an insufficient buffer size. + * + * \note This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * See also #PSA_AEAD_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, + * \p plaintext_length). + * + * \param plaintext_length Size of the plaintext in bytes. + * + * \return A sufficient output buffer size for any of the + * supported key types and AEAD algorithms. + * + */ +#define PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE(plaintext_length) \ + ((plaintext_length) + PSA_AEAD_TAG_MAX_SIZE) + + +/** The maximum size of the output of psa_aead_decrypt(), in bytes. + * + * If the size of the plaintext buffer is at least this large, it is + * guaranteed that psa_aead_decrypt() will not fail due to an + * insufficient buffer size. Depending on the algorithm, the actual size of + * the plaintext may be smaller. + * + * See also #PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(\p ciphertext_length). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is + * compatible with algorithm \p alg. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * \param ciphertext_length Size of the plaintext in bytes. + * + * \return The AEAD ciphertext size for the specified + * algorithm. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_AEAD_DECRYPT_OUTPUT_SIZE(key_type, alg, ciphertext_length) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ + (ciphertext_length) > PSA_ALG_AEAD_GET_TAG_LENGTH(alg) ? \ + (ciphertext_length) - PSA_ALG_AEAD_GET_TAG_LENGTH(alg) : \ + 0u) + +/** A sufficient output buffer size for psa_aead_decrypt(), for any of the + * supported key types and AEAD algorithms. + * + * If the size of the plaintext buffer is at least this large, it is guaranteed + * that psa_aead_decrypt() will not fail due to an insufficient buffer size. + * + * \note This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * See also #PSA_AEAD_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, + * \p ciphertext_length). + * + * \param ciphertext_length Size of the ciphertext in bytes. + * + * \return A sufficient output buffer size for any of the + * supported key types and AEAD algorithms. + * + */ +#define PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE(ciphertext_length) \ + (ciphertext_length) + +/** The default nonce size for an AEAD algorithm, in bytes. + * + * This macro can be used to allocate a buffer of sufficient size to + * store the nonce output from #psa_aead_generate_nonce(). + * + * See also #PSA_AEAD_NONCE_MAX_SIZE. + * + * \note This is not the maximum size of nonce supported as input to + * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), + * just the default size that is generated by #psa_aead_generate_nonce(). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is compatible with + * algorithm \p alg. + * + * \param alg An AEAD algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \return The default nonce size for the specified key type and algorithm. + * If the key type or AEAD algorithm is not recognized, + * or the parameters are incompatible, return 0. + */ +#define PSA_AEAD_NONCE_LENGTH(key_type, alg) \ + (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) == 16 ? \ + MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CCM) ? 13u : \ + MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_GCM) ? 12u : \ + 0u : \ + (key_type) == PSA_KEY_TYPE_CHACHA20 && \ + MBEDTLS_PSA_ALG_AEAD_EQUAL(alg, PSA_ALG_CHACHA20_POLY1305) ? 12u : \ + 0u) + +/** The maximum default nonce size among all supported pairs of key types and + * AEAD algorithms, in bytes. + * + * This is equal to or greater than any value that #PSA_AEAD_NONCE_LENGTH() + * may return. + * + * \note This is not the maximum size of nonce supported as input to + * #psa_aead_set_nonce(), #psa_aead_encrypt() or #psa_aead_decrypt(), + * just the largest size that may be generated by + * #psa_aead_generate_nonce(). + */ +#define PSA_AEAD_NONCE_MAX_SIZE 13u + +/** A sufficient output buffer size for psa_aead_update(). + * + * If the size of the output buffer is at least this large, it is + * guaranteed that psa_aead_update() will not fail due to an + * insufficient buffer size. The actual size of the output may be smaller + * in any given call. + * + * See also #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is + * compatible with algorithm \p alg. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * \param input_length Size of the input in bytes. + * + * \return A sufficient output buffer size for the specified + * algorithm. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +/* For all the AEAD modes defined in this specification, it is possible + * to emit output without delay. However, hardware may not always be + * capable of this. So for modes based on a block cipher, allow the + * implementation to delay the output until it has a full block. */ +#define PSA_AEAD_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 ? \ + PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ + PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), (input_length)) : \ + (input_length) : \ + 0u) + +/** A sufficient output buffer size for psa_aead_update(), for any of the + * supported key types and AEAD algorithms. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_aead_update() will not fail due to an insufficient buffer size. + * + * See also #PSA_AEAD_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). + * + * \param input_length Size of the input in bytes. + */ +#define PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(input_length) \ + (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, (input_length))) + +/** A sufficient ciphertext buffer size for psa_aead_finish(). + * + * If the size of the ciphertext buffer is at least this large, it is + * guaranteed that psa_aead_finish() will not fail due to an + * insufficient ciphertext buffer size. The actual size of the output may + * be smaller in any given call. + * + * See also #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE. + * + * \param key_type A symmetric key type that is + compatible with algorithm \p alg. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \return A sufficient ciphertext buffer size for the + * specified algorithm. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_AEAD_FINISH_OUTPUT_SIZE(key_type, alg) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ + PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ + PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ + 0u) + +/** A sufficient ciphertext buffer size for psa_aead_finish(), for any of the + * supported key types and AEAD algorithms. + * + * See also #PSA_AEAD_FINISH_OUTPUT_SIZE(\p key_type, \p alg). + */ +#define PSA_AEAD_FINISH_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) + +/** A sufficient plaintext buffer size for psa_aead_verify(). + * + * If the size of the plaintext buffer is at least this large, it is + * guaranteed that psa_aead_verify() will not fail due to an + * insufficient plaintext buffer size. The actual size of the output may + * be smaller in any given call. + * + * See also #PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE. + * + * \param key_type A symmetric key type that is + * compatible with algorithm \p alg. + * \param alg An AEAD algorithm + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \return A sufficient plaintext buffer size for the + * specified algorithm. + * If the key type or AEAD algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_AEAD_VERIFY_OUTPUT_SIZE(key_type, alg) \ + (PSA_AEAD_NONCE_LENGTH(key_type, alg) != 0 && \ + PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) ? \ + PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ + 0u) + +/** A sufficient plaintext buffer size for psa_aead_verify(), for any of the + * supported key types and AEAD algorithms. + * + * See also #PSA_AEAD_VERIFY_OUTPUT_SIZE(\p key_type, \p alg). + */ +#define PSA_AEAD_VERIFY_OUTPUT_MAX_SIZE (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) + +#define PSA_RSA_MINIMUM_PADDING_SIZE(alg) \ + (PSA_ALG_IS_RSA_OAEP(alg) ? \ + 2u * PSA_HASH_LENGTH(PSA_ALG_RSA_OAEP_GET_HASH(alg)) + 1u : \ + 11u /*PKCS#1v1.5*/) + +/** + * \brief ECDSA signature size for a given curve bit size + * + * \param curve_bits Curve size in bits. + * \return Signature size in bytes. + * + * \note This macro returns a compile-time constant if its argument is one. + */ +#define PSA_ECDSA_SIGNATURE_SIZE(curve_bits) \ + (PSA_BITS_TO_BYTES(curve_bits) * 2u) + +/** Sufficient signature buffer size for psa_sign_hash(). + * + * This macro returns a sufficient buffer size for a signature using a key + * of the specified type and size, with the specified algorithm. + * Note that the actual size of the signature may be smaller + * (some algorithms produce a variable-size signature). + * + * \warning This function may call its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type An asymmetric key type (this may indifferently be a + * key pair type or a public key type). + * \param key_bits The size of the key in bits. + * \param alg The signature algorithm. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_sign_hash() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not supported, + * return either a sensible size or 0. + * If the parameters are not valid, the + * return value is unspecified. + */ +#define PSA_SIGN_OUTPUT_SIZE(key_type, key_bits, alg) \ + (PSA_KEY_TYPE_IS_RSA(key_type) ? ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ + PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_ECDSA_SIGNATURE_SIZE(key_bits) : \ + ((void) alg, 0u)) + +#define PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE \ + PSA_ECDSA_SIGNATURE_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) + +/** \def PSA_SIGNATURE_MAX_SIZE + * + * Maximum size of an asymmetric signature. + * + * This macro expands to a compile-time constant integer. This value + * is the maximum size of a signature in bytes. + */ +#define PSA_SIGNATURE_MAX_SIZE 1 + +#if (defined(PSA_WANT_ALG_ECDSA) || defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA)) && \ + (PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE > PSA_SIGNATURE_MAX_SIZE) +#undef PSA_SIGNATURE_MAX_SIZE +#define PSA_SIGNATURE_MAX_SIZE PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE +#endif +#if (defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) || defined(PSA_WANT_ALG_RSA_PSS)) && \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) > PSA_SIGNATURE_MAX_SIZE) +#undef PSA_SIGNATURE_MAX_SIZE +#define PSA_SIGNATURE_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) +#endif + +/** Sufficient output buffer size for psa_asymmetric_encrypt(). + * + * This macro returns a sufficient buffer size for a ciphertext produced using + * a key of the specified type and size, with the specified algorithm. + * Note that the actual size of the ciphertext may be smaller, depending + * on the algorithm. + * + * \warning This function may call its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type An asymmetric key type (this may indifferently be a + * key pair type or a public key type). + * \param key_bits The size of the key in bits. + * \param alg The asymmetric encryption algorithm. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_asymmetric_encrypt() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not supported, + * return either a sensible size or 0. + * If the parameters are not valid, the + * return value is unspecified. + */ +#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ + (PSA_KEY_TYPE_IS_RSA(key_type) ? \ + ((void) alg, PSA_BITS_TO_BYTES(key_bits)) : \ + 0u) + +/** A sufficient output buffer size for psa_asymmetric_encrypt(), for any + * supported asymmetric encryption. + * + * See also #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). + */ +/* This macro assumes that RSA is the only supported asymmetric encryption. */ +#define PSA_ASYMMETRIC_ENCRYPT_OUTPUT_MAX_SIZE \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) + +/** Sufficient output buffer size for psa_asymmetric_decrypt(). + * + * This macro returns a sufficient buffer size for a plaintext produced using + * a key of the specified type and size, with the specified algorithm. + * Note that the actual size of the plaintext may be smaller, depending + * on the algorithm. + * + * \warning This function may call its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type An asymmetric key type (this may indifferently be a + * key pair type or a public key type). + * \param key_bits The size of the key in bits. + * \param alg The asymmetric encryption algorithm. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_asymmetric_decrypt() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not supported, + * return either a sensible size or 0. + * If the parameters are not valid, the + * return value is unspecified. + */ +#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(key_type, key_bits, alg) \ + (PSA_KEY_TYPE_IS_RSA(key_type) ? \ + PSA_BITS_TO_BYTES(key_bits) - PSA_RSA_MINIMUM_PADDING_SIZE(alg) : \ + 0u) + +/** A sufficient output buffer size for psa_asymmetric_decrypt(), for any + * supported asymmetric decryption. + * + * This macro assumes that RSA is the only supported asymmetric encryption. + * + * See also #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\p key_type, \p key_bits, \p alg). + */ +#define PSA_ASYMMETRIC_DECRYPT_OUTPUT_MAX_SIZE \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS)) + +/* Maximum size of the ASN.1 encoding of an INTEGER with the specified + * number of bits. + * + * This definition assumes that bits <= 2^19 - 9 so that the length field + * is at most 3 bytes. The length of the encoding is the length of the + * bit string padded to a whole number of bytes plus: + * - 1 type byte; + * - 1 to 3 length bytes; + * - 0 to 1 bytes of leading 0 due to the sign bit. + */ +#define PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(bits) \ + ((bits) / 8u + 5u) + +/* Maximum size of the export encoding of an RSA public key. + * Assumes that the public exponent is less than 2^32. + * + * RSAPublicKey ::= SEQUENCE { + * modulus INTEGER, -- n + * publicExponent INTEGER } -- e + * + * - 4 bytes of SEQUENCE overhead; + * - n : INTEGER; + * - 7 bytes for the public exponent. + */ +#define PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ + (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) + 11u) + +/* Maximum size of the export encoding of an RSA key pair. + * Assumes that the public exponent is less than 2^32 and that the size + * difference between the two primes is at most 1 bit. + * + * RSAPrivateKey ::= SEQUENCE { + * version Version, -- 0 + * modulus INTEGER, -- N-bit + * publicExponent INTEGER, -- 32-bit + * privateExponent INTEGER, -- N-bit + * prime1 INTEGER, -- N/2-bit + * prime2 INTEGER, -- N/2-bit + * exponent1 INTEGER, -- N/2-bit + * exponent2 INTEGER, -- N/2-bit + * coefficient INTEGER, -- N/2-bit + * } + * + * - 4 bytes of SEQUENCE overhead; + * - 3 bytes of version; + * - 7 half-size INTEGERs plus 2 full-size INTEGERs, + * overapproximated as 9 half-size INTEGERS; + * - 7 bytes for the public exponent. + */ +#define PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) \ + (9u * PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE((key_bits) / 2u + 1u) + 14u) + +/* Maximum size of the export encoding of a DSA public key. + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING } -- contains DSAPublicKey + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters Dss-Params } -- SEQUENCE of 3 INTEGERs + * DSAPublicKey ::= INTEGER -- public key, Y + * + * - 3 * 4 bytes of SEQUENCE overhead; + * - 1 + 1 + 7 bytes of algorithm (DSA OID); + * - 4 bytes of BIT STRING overhead; + * - 3 full-size INTEGERs (p, g, y); + * - 1 + 1 + 32 bytes for 1 sub-size INTEGER (q <= 256 bits). + */ +#define PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) \ + (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 59u) + +/* Maximum size of the export encoding of a DSA key pair. + * + * DSAPrivateKey ::= SEQUENCE { + * version Version, -- 0 + * prime INTEGER, -- p + * subprime INTEGER, -- q + * generator INTEGER, -- g + * public INTEGER, -- y + * private INTEGER, -- x + * } + * + * - 4 bytes of SEQUENCE overhead; + * - 3 bytes of version; + * - 3 full-size INTEGERs (p, g, y); + * - 2 * (1 + 1 + 32) bytes for 2 sub-size INTEGERs (q, x <= 256 bits). + */ +#define PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) \ + (PSA_KEY_EXPORT_ASN1_INTEGER_MAX_SIZE(key_bits) * 3u + 75u) + +/* Maximum size of the export encoding of an ECC public key. + * + * The representation of an ECC public key is: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian; + * - where m is the bit size associated with the curve. + * + * - 1 byte + 2 * point size. + */ +#define PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) \ + (2u * PSA_BITS_TO_BYTES(key_bits) + 1u) + +/* Maximum size of the export encoding of an ECC key pair. + * + * An ECC key pair is represented by the secret value. + */ +#define PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) \ + (PSA_BITS_TO_BYTES(key_bits)) + +/* Maximum size of the export encoding of an DH key pair. + * + * An DH key pair is represented by the secret value. + */ +#define PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(key_bits) \ + (PSA_BITS_TO_BYTES(key_bits)) + +/* Maximum size of the export encoding of an DH public key. + */ +#define PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(key_bits) \ + (PSA_BITS_TO_BYTES(key_bits)) + +/** Sufficient output buffer size for psa_export_key() or + * psa_export_public_key(). + * + * This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * The following code illustrates how to allocate enough memory to export + * a key by querying the key type and size at runtime. + * \code{c} + * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + * psa_status_t status; + * status = psa_get_key_attributes(key, &attributes); + * if (status != PSA_SUCCESS) handle_error(...); + * psa_key_type_t key_type = psa_get_key_type(&attributes); + * size_t key_bits = psa_get_key_bits(&attributes); + * size_t buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits); + * psa_reset_key_attributes(&attributes); + * uint8_t *buffer = malloc(buffer_size); + * if (buffer == NULL) handle_error(...); + * size_t buffer_length; + * status = psa_export_key(key, buffer, buffer_size, &buffer_length); + * if (status != PSA_SUCCESS) handle_error(...); + * \endcode + * + * \param key_type A supported key type. + * \param key_bits The size of the key in bits. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_export_key() or psa_export_public_key() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not supported, + * return either a sensible size or 0. + * If the parameters are not valid, the return value is unspecified. + */ +#define PSA_EXPORT_KEY_OUTPUT_SIZE(key_type, key_bits) \ + (PSA_KEY_TYPE_IS_UNSTRUCTURED(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ + PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ + (key_type) == PSA_KEY_TYPE_RSA_KEY_PAIR ? PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(key_bits) : \ + (key_type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ + (key_type) == PSA_KEY_TYPE_DSA_KEY_PAIR ? PSA_KEY_EXPORT_DSA_KEY_PAIR_MAX_SIZE(key_bits) : \ + (key_type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY ? PSA_KEY_EXPORT_DSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ + PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) ? PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(key_bits) : \ + PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ + 0u) + +/** Sufficient output buffer size for psa_export_public_key(). + * + * This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * The following code illustrates how to allocate enough memory to export + * a public key by querying the key type and size at runtime. + * \code{c} + * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + * psa_status_t status; + * status = psa_get_key_attributes(key, &attributes); + * if (status != PSA_SUCCESS) handle_error(...); + * psa_key_type_t key_type = psa_get_key_type(&attributes); + * size_t key_bits = psa_get_key_bits(&attributes); + * size_t buffer_size = PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits); + * psa_reset_key_attributes(&attributes); + * uint8_t *buffer = malloc(buffer_size); + * if (buffer == NULL) handle_error(...); + * size_t buffer_length; + * status = psa_export_public_key(key, buffer, buffer_size, &buffer_length); + * if (status != PSA_SUCCESS) handle_error(...); + * \endcode + * + * \param key_type A public key or key pair key type. + * \param key_bits The size of the key in bits. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_export_public_key() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that is not + * supported, return either a sensible size or 0. + * If the parameters are not valid, + * the return value is unspecified. + * + * If the parameters are valid and supported, + * return the same result as + * #PSA_EXPORT_KEY_OUTPUT_SIZE( + * \p #PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(\p key_type), + * \p key_bits). + */ +#define PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(key_type, key_bits) \ + (PSA_KEY_TYPE_IS_RSA(key_type) ? PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(key_bits) : \ + PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ + PSA_KEY_TYPE_IS_DH(key_type) ? PSA_BITS_TO_BYTES(key_bits) : \ + 0u) + +/** Sufficient buffer size for exporting any asymmetric key pair. + * + * This macro expands to a compile-time constant integer. This value is + * a sufficient buffer size when calling psa_export_key() to export any + * asymmetric key pair, regardless of the exact key type and key size. + * + * See also #PSA_EXPORT_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). + */ +#define PSA_EXPORT_KEY_PAIR_MAX_SIZE 1 + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) && \ + (PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ + PSA_EXPORT_KEY_PAIR_MAX_SIZE) +#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE +#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ + PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) +#endif +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) && \ + (PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ + PSA_EXPORT_KEY_PAIR_MAX_SIZE) +#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE +#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ + PSA_KEY_EXPORT_RSA_KEY_PAIR_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) +#endif +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) && \ + (PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ + PSA_EXPORT_KEY_PAIR_MAX_SIZE) +#undef PSA_EXPORT_KEY_PAIR_MAX_SIZE +#define PSA_EXPORT_KEY_PAIR_MAX_SIZE \ + PSA_KEY_EXPORT_FFDH_KEY_PAIR_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) +#endif + +/** Sufficient buffer size for exporting any asymmetric public key. + * + * This macro expands to a compile-time constant integer. This value is + * a sufficient buffer size when calling psa_export_key() or + * psa_export_public_key() to export any asymmetric public key, + * regardless of the exact key type and key size. + * + * See also #PSA_EXPORT_PUBLIC_KEY_OUTPUT_SIZE(\p key_type, \p key_bits). + */ +#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE 1 + +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) && \ + (PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ + PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) +#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE +#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ + PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) +#endif +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) && \ + (PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) > \ + PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) +#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE +#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ + PSA_KEY_EXPORT_RSA_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_RSA_MAX_KEY_BITS) +#endif +#if defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) && \ + (PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) > \ + PSA_EXPORT_PUBLIC_KEY_MAX_SIZE) +#undef PSA_EXPORT_PUBLIC_KEY_MAX_SIZE +#define PSA_EXPORT_PUBLIC_KEY_MAX_SIZE \ + PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) +#endif + +/** Sufficient output buffer size for psa_raw_key_agreement(). + * + * This macro returns a compile-time constant if its arguments are + * compile-time constants. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE. + * + * \param key_type A supported key type. + * \param key_bits The size of the key in bits. + * + * \return If the parameters are valid and supported, return + * a buffer size in bytes that guarantees that + * psa_raw_key_agreement() will not fail with + * #PSA_ERROR_BUFFER_TOO_SMALL. + * If the parameters are a valid combination that + * is not supported, return either a sensible size or 0. + * If the parameters are not valid, + * the return value is unspecified. + */ +#define PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(key_type, key_bits) \ + ((PSA_KEY_TYPE_IS_ECC_KEY_PAIR(key_type) || \ + PSA_KEY_TYPE_IS_DH_KEY_PAIR(key_type)) ? PSA_BITS_TO_BYTES(key_bits) : 0u) + +/** Maximum size of the output from psa_raw_key_agreement(). + * + * This macro expands to a compile-time constant integer. This value is the + * maximum size of the output any raw key agreement algorithm, in bytes. + * + * See also #PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(\p key_type, \p key_bits). + */ +#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE 1 + +#if defined(PSA_WANT_ALG_ECDH) && \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) +#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE +#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) +#endif +#if defined(PSA_WANT_ALG_FFDH) && \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) > PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE) +#undef PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE +#define PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE PSA_BITS_TO_BYTES(PSA_VENDOR_FFDH_MAX_KEY_BITS) +#endif + +/** The default IV size for a cipher algorithm, in bytes. + * + * The IV that is generated as part of a call to #psa_cipher_encrypt() is always + * the default IV length for the algorithm. + * + * This macro can be used to allocate a buffer of sufficient size to + * store the IV output from #psa_cipher_generate_iv() when using + * a multi-part cipher operation. + * + * See also #PSA_CIPHER_IV_MAX_SIZE. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is compatible with algorithm \p alg. + * + * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \return The default IV size for the specified key type and algorithm. + * If the algorithm does not use an IV, return 0. + * If the key type or cipher algorithm is not recognized, + * or the parameters are incompatible, return 0. + */ +#define PSA_CIPHER_IV_LENGTH(key_type, alg) \ + (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) > 1 && \ + ((alg) == PSA_ALG_CTR || \ + (alg) == PSA_ALG_CFB || \ + (alg) == PSA_ALG_OFB || \ + (alg) == PSA_ALG_XTS || \ + (alg) == PSA_ALG_CBC_NO_PADDING || \ + (alg) == PSA_ALG_CBC_PKCS7) ? PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ + (key_type) == PSA_KEY_TYPE_CHACHA20 && \ + (alg) == PSA_ALG_STREAM_CIPHER ? 12u : \ + (alg) == PSA_ALG_CCM_STAR_NO_TAG ? 13u : \ + 0u) + +/** The maximum IV size for all supported cipher algorithms, in bytes. + * + * See also #PSA_CIPHER_IV_LENGTH(). + */ +#define PSA_CIPHER_IV_MAX_SIZE 16u + +/** The maximum size of the output of psa_cipher_encrypt(), in bytes. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. + * Depending on the algorithm, the actual size of the output might be smaller. + * + * See also #PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(\p input_length). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is compatible with algorithm + * alg. + * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param input_length Size of the input in bytes. + * + * \return A sufficient output size for the specified key type and + * algorithm. If the key type or cipher algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ + (alg == PSA_ALG_CBC_PKCS7 ? \ + (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ + PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ + (input_length) + 1u) + \ + PSA_CIPHER_IV_LENGTH((key_type), (alg)) : 0u) : \ + (PSA_ALG_IS_CIPHER(alg) ? \ + (input_length) + PSA_CIPHER_IV_LENGTH((key_type), (alg)) : \ + 0u)) + +/** A sufficient output buffer size for psa_cipher_encrypt(), for any of the + * supported key types and cipher algorithms. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_encrypt() will not fail due to an insufficient buffer size. + * + * See also #PSA_CIPHER_ENCRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). + * + * \param input_length Size of the input in bytes. + * + */ +#define PSA_CIPHER_ENCRYPT_OUTPUT_MAX_SIZE(input_length) \ + (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, \ + (input_length) + 1u) + \ + PSA_CIPHER_IV_MAX_SIZE) + +/** The maximum size of the output of psa_cipher_decrypt(), in bytes. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. + * Depending on the algorithm, the actual size of the output might be smaller. + * + * See also #PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(\p input_length). + * + * \param key_type A symmetric key type that is compatible with algorithm + * alg. + * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param input_length Size of the input in bytes. + * + * \return A sufficient output size for the specified key type and + * algorithm. If the key type or cipher algorithm is not + * recognized, or the parameters are incompatible, + * return 0. + */ +#define PSA_CIPHER_DECRYPT_OUTPUT_SIZE(key_type, alg, input_length) \ + (PSA_ALG_IS_CIPHER(alg) && \ + ((key_type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ + (input_length) : \ + 0u) + +/** A sufficient output buffer size for psa_cipher_decrypt(), for any of the + * supported key types and cipher algorithms. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_decrypt() will not fail due to an insufficient buffer size. + * + * See also #PSA_CIPHER_DECRYPT_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). + * + * \param input_length Size of the input in bytes. + */ +#define PSA_CIPHER_DECRYPT_OUTPUT_MAX_SIZE(input_length) \ + (input_length) + +/** A sufficient output buffer size for psa_cipher_update(). + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_update() will not fail due to an insufficient buffer size. + * The actual size of the output might be smaller in any given call. + * + * See also #PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(\p input_length). + * + * \param key_type A symmetric key type that is compatible with algorithm + * alg. + * \param alg A cipher algorithm (PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param input_length Size of the input in bytes. + * + * \return A sufficient output size for the specified key type and + * algorithm. If the key type or cipher algorithm is not + * recognized, or the parameters are incompatible, return 0. + */ +#define PSA_CIPHER_UPDATE_OUTPUT_SIZE(key_type, alg, input_length) \ + (PSA_ALG_IS_CIPHER(alg) ? \ + (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) != 0 ? \ + (((alg) == PSA_ALG_CBC_PKCS7 || \ + (alg) == PSA_ALG_CBC_NO_PADDING || \ + (alg) == PSA_ALG_ECB_NO_PADDING) ? \ + PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type), \ + input_length) : \ + (input_length)) : 0u) : \ + 0u) + +/** A sufficient output buffer size for psa_cipher_update(), for any of the + * supported key types and cipher algorithms. + * + * If the size of the output buffer is at least this large, it is guaranteed + * that psa_cipher_update() will not fail due to an insufficient buffer size. + * + * See also #PSA_CIPHER_UPDATE_OUTPUT_SIZE(\p key_type, \p alg, \p input_length). + * + * \param input_length Size of the input in bytes. + */ +#define PSA_CIPHER_UPDATE_OUTPUT_MAX_SIZE(input_length) \ + (PSA_ROUND_UP_TO_MULTIPLE(PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE, input_length)) + +/** A sufficient ciphertext buffer size for psa_cipher_finish(). + * + * If the size of the ciphertext buffer is at least this large, it is + * guaranteed that psa_cipher_finish() will not fail due to an insufficient + * ciphertext buffer size. The actual size of the output might be smaller in + * any given call. + * + * See also #PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE(). + * + * \param key_type A symmetric key type that is compatible with algorithm + * alg. + * \param alg A cipher algorithm (PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \return A sufficient output size for the specified key type and + * algorithm. If the key type or cipher algorithm is not + * recognized, or the parameters are incompatible, return 0. + */ +#define PSA_CIPHER_FINISH_OUTPUT_SIZE(key_type, alg) \ + (PSA_ALG_IS_CIPHER(alg) ? \ + (alg == PSA_ALG_CBC_PKCS7 ? \ + PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) : \ + 0u) : \ + 0u) + +/** A sufficient ciphertext buffer size for psa_cipher_finish(), for any of the + * supported key types and cipher algorithms. + * + * See also #PSA_CIPHER_FINISH_OUTPUT_SIZE(\p key_type, \p alg). + */ +#define PSA_CIPHER_FINISH_OUTPUT_MAX_SIZE \ + (PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE) + +#endif /* PSA_CRYPTO_SIZES_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_struct.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_struct.h index ffd4c48..71c5914 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_struct.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_struct.h @@ -1,483 +1,483 @@ -/** - * \file psa/crypto_struct.h - * - * \brief PSA cryptography module: Mbed TLS structured type implementations - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. - * - * This file contains the definitions of some data structures with - * implementation-specific definitions. - * - * In implementations with isolation between the application and the - * cryptography module, it is expected that the front-end and the back-end - * would have different versions of this file. - * - *

Design notes about multipart operation structures

- * - * For multipart operations without driver delegation support, each multipart - * operation structure contains a `psa_algorithm_t alg` field which indicates - * which specific algorithm the structure is for. When the structure is not in - * use, `alg` is 0. Most of the structure consists of a union which is - * discriminated by `alg`. - * - * For multipart operations with driver delegation support, each multipart - * operation structure contains an `unsigned int id` field indicating which - * driver got assigned to do the operation. When the structure is not in use, - * 'id' is 0. The structure contains also a driver context which is the union - * of the contexts of all drivers able to handle the type of multipart - * operation. - * - * Note that when `alg` or `id` is 0, the content of other fields is undefined. - * In particular, it is not guaranteed that a freshly-initialized structure - * is all-zero: we initialize structures to something like `{0, 0}`, which - * is only guaranteed to initializes the first member of the union; - * GCC and Clang initialize the whole structure to 0 (at the time of writing), - * but MSVC and CompCert don't. - * - * In Mbed TLS, multipart operation structures live independently from - * the key. This allows Mbed TLS to free the key objects when destroying - * a key slot. If a multipart operation needs to remember the key after - * the setup function returns, the operation structure needs to contain a - * copy of the key. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_struct.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_struct.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_STRUCT_H -#define PSA_CRYPTO_STRUCT_H -#include "mbedtls/private_access.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* Include the Mbed TLS configuration file, the way Mbed TLS does it - * in each of its header files. */ -#include "mbedtls/build_info.h" - -/* Include the context definition for the compiled-in drivers for the primitive - * algorithms. */ -#include "psa/crypto_driver_contexts_primitives.h" - -struct psa_hash_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_driver_wrappers.h. - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. the driver context is not active, in use). */ - unsigned int MBEDTLS_PRIVATE(id); - psa_driver_hash_context_t MBEDTLS_PRIVATE(ctx); -}; - -#define PSA_HASH_OPERATION_INIT { 0, { 0 } } -static inline struct psa_hash_operation_s psa_hash_operation_init(void) -{ - const struct psa_hash_operation_s v = PSA_HASH_OPERATION_INIT; - return v; -} - -struct psa_cipher_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - unsigned int MBEDTLS_PRIVATE(iv_required) : 1; - unsigned int MBEDTLS_PRIVATE(iv_set) : 1; - - uint8_t MBEDTLS_PRIVATE(default_iv_length); - - psa_driver_cipher_context_t MBEDTLS_PRIVATE(ctx); -}; - -#define PSA_CIPHER_OPERATION_INIT { 0, 0, 0, 0, { 0 } } -static inline struct psa_cipher_operation_s psa_cipher_operation_init(void) -{ - const struct psa_cipher_operation_s v = PSA_CIPHER_OPERATION_INIT; - return v; -} - -/* Include the context definition for the compiled-in drivers for the composite - * algorithms. */ -#include "psa/crypto_driver_contexts_composites.h" - -struct psa_mac_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - uint8_t MBEDTLS_PRIVATE(mac_size); - unsigned int MBEDTLS_PRIVATE(is_sign) : 1; - psa_driver_mac_context_t MBEDTLS_PRIVATE(ctx); -}; - -#define PSA_MAC_OPERATION_INIT { 0, 0, 0, { 0 } } -static inline struct psa_mac_operation_s psa_mac_operation_init(void) -{ - const struct psa_mac_operation_s v = PSA_MAC_OPERATION_INIT; - return v; -} - -struct psa_aead_operation_s { - - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_algorithm_t MBEDTLS_PRIVATE(alg); - psa_key_type_t MBEDTLS_PRIVATE(key_type); - - size_t MBEDTLS_PRIVATE(ad_remaining); - size_t MBEDTLS_PRIVATE(body_remaining); - - unsigned int MBEDTLS_PRIVATE(nonce_set) : 1; - unsigned int MBEDTLS_PRIVATE(lengths_set) : 1; - unsigned int MBEDTLS_PRIVATE(ad_started) : 1; - unsigned int MBEDTLS_PRIVATE(body_started) : 1; - unsigned int MBEDTLS_PRIVATE(is_encrypt) : 1; - - psa_driver_aead_context_t MBEDTLS_PRIVATE(ctx); -}; - -#define PSA_AEAD_OPERATION_INIT { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 } } -static inline struct psa_aead_operation_s psa_aead_operation_init(void) -{ - const struct psa_aead_operation_s v = PSA_AEAD_OPERATION_INIT; - return v; -} - -/* Include the context definition for the compiled-in drivers for the key - * derivation algorithms. */ -#include "psa/crypto_driver_contexts_key_derivation.h" - -struct psa_key_derivation_s { - psa_algorithm_t MBEDTLS_PRIVATE(alg); - unsigned int MBEDTLS_PRIVATE(can_output_key) : 1; - size_t MBEDTLS_PRIVATE(capacity); - psa_driver_key_derivation_context_t MBEDTLS_PRIVATE(ctx); -}; - -/* This only zeroes out the first byte in the union, the rest is unspecified. */ -#define PSA_KEY_DERIVATION_OPERATION_INIT { 0, 0, 0, { 0 } } -static inline struct psa_key_derivation_s psa_key_derivation_operation_init( - void) -{ - const struct psa_key_derivation_s v = PSA_KEY_DERIVATION_OPERATION_INIT; - return v; -} - -struct psa_key_policy_s { - psa_key_usage_t MBEDTLS_PRIVATE(usage); - psa_algorithm_t MBEDTLS_PRIVATE(alg); - psa_algorithm_t MBEDTLS_PRIVATE(alg2); -}; -typedef struct psa_key_policy_s psa_key_policy_t; - -#define PSA_KEY_POLICY_INIT { 0, 0, 0 } -static inline struct psa_key_policy_s psa_key_policy_init(void) -{ - const struct psa_key_policy_s v = PSA_KEY_POLICY_INIT; - return v; -} - -/* The type used internally for key sizes. - * Public interfaces use size_t, but internally we use a smaller type. */ -typedef uint16_t psa_key_bits_t; -/* The maximum value of the type used to represent bit-sizes. - * This is used to mark an invalid key size. */ -#define PSA_KEY_BITS_TOO_LARGE ((psa_key_bits_t) -1) -/* The maximum size of a key in bits. - * Currently defined as the maximum that can be represented, rounded down - * to a whole number of bytes. - * This is an uncast value so that it can be used in preprocessor - * conditionals. */ -#ifndef PSA_MAX_KEY_BITS -#define PSA_MAX_KEY_BITS 0xfff8 -#endif - -/** A mask of flags that can be stored in key attributes. - * - * This type is also used internally to store flags in slots. Internal - * flags are defined in library/psa_crypto_core.h. Internal flags may have - * the same value as external flags if they are properly handled during - * key creation and in psa_get_key_attributes. - */ -typedef uint16_t psa_key_attributes_flag_t; - -#define MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER \ - ((psa_key_attributes_flag_t) 0x0001) - -/* A mask of key attribute flags used externally only. - * Only meant for internal checks inside the library. */ -#define MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY ( \ - MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER | \ - 0) - -/* A mask of key attribute flags used both internally and externally. - * Currently there aren't any. */ -#define MBEDTLS_PSA_KA_MASK_DUAL_USE ( \ - 0) - -typedef struct { - psa_key_type_t MBEDTLS_PRIVATE(type); - psa_key_bits_t MBEDTLS_PRIVATE(bits); - psa_key_lifetime_t MBEDTLS_PRIVATE(lifetime); - mbedtls_svc_key_id_t MBEDTLS_PRIVATE(id); - psa_key_policy_t MBEDTLS_PRIVATE(policy); - psa_key_attributes_flag_t MBEDTLS_PRIVATE(flags); -} psa_core_key_attributes_t; - -#define PSA_CORE_KEY_ATTRIBUTES_INIT { PSA_KEY_TYPE_NONE, 0, \ - PSA_KEY_LIFETIME_VOLATILE, \ - MBEDTLS_SVC_KEY_ID_INIT, \ - PSA_KEY_POLICY_INIT, 0 } - -struct psa_key_attributes_s { - psa_core_key_attributes_t MBEDTLS_PRIVATE(core); -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - psa_key_slot_number_t MBEDTLS_PRIVATE(slot_number); -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - void *MBEDTLS_PRIVATE(domain_parameters); - size_t MBEDTLS_PRIVATE(domain_parameters_size); -}; - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -#define PSA_KEY_ATTRIBUTES_INIT { PSA_CORE_KEY_ATTRIBUTES_INIT, 0, NULL, 0 } -#else -#define PSA_KEY_ATTRIBUTES_INIT { PSA_CORE_KEY_ATTRIBUTES_INIT, NULL, 0 } -#endif - -static inline struct psa_key_attributes_s psa_key_attributes_init(void) -{ - const struct psa_key_attributes_s v = PSA_KEY_ATTRIBUTES_INIT; - return v; -} - -static inline void psa_set_key_id(psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t key) -{ - psa_key_lifetime_t lifetime = attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); - - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = key; - - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = - PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( - PSA_KEY_LIFETIME_PERSISTENT, - PSA_KEY_LIFETIME_GET_LOCATION(lifetime)); - } -} - -static inline mbedtls_svc_key_id_t psa_get_key_id( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id); -} - -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER -static inline void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, - mbedtls_key_owner_id_t owner) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = owner; -} -#endif - -static inline void psa_set_key_lifetime(psa_key_attributes_t *attributes, - psa_key_lifetime_t lifetime) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = lifetime; - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { -#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = 0; -#else - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = 0; -#endif - } -} - -static inline psa_key_lifetime_t psa_get_key_lifetime( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); -} - -static inline void psa_extend_key_usage_flags(psa_key_usage_t *usage_flags) -{ - if (*usage_flags & PSA_KEY_USAGE_SIGN_HASH) { - *usage_flags |= PSA_KEY_USAGE_SIGN_MESSAGE; - } - - if (*usage_flags & PSA_KEY_USAGE_VERIFY_HASH) { - *usage_flags |= PSA_KEY_USAGE_VERIFY_MESSAGE; - } -} - -static inline void psa_set_key_usage_flags(psa_key_attributes_t *attributes, - psa_key_usage_t usage_flags) -{ - psa_extend_key_usage_flags(&usage_flags); - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage) = usage_flags; -} - -static inline psa_key_usage_t psa_get_key_usage_flags( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage); -} - -static inline void psa_set_key_algorithm(psa_key_attributes_t *attributes, - psa_algorithm_t alg) -{ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg) = alg; -} - -static inline psa_algorithm_t psa_get_key_algorithm( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg); -} - -/* This function is declared in crypto_extra.h, which comes after this - * header file, but we need the function here, so repeat the declaration. */ -psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, - psa_key_type_t type, - const uint8_t *data, - size_t data_length); - -static inline void psa_set_key_type(psa_key_attributes_t *attributes, - psa_key_type_t type) -{ - if (attributes->MBEDTLS_PRIVATE(domain_parameters) == NULL) { - /* Common case: quick path */ - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = type; - } else { - /* Call the bigger function to free the old domain parameters. - * Ignore any errors which may arise due to type requiring - * non-default domain parameters, since this function can't - * report errors. */ - (void) psa_set_key_domain_parameters(attributes, type, NULL, 0); - } -} - -static inline psa_key_type_t psa_get_key_type( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type); -} - -static inline void psa_set_key_bits(psa_key_attributes_t *attributes, - size_t bits) -{ - if (bits > PSA_MAX_KEY_BITS) { - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = PSA_KEY_BITS_TOO_LARGE; - } else { - attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = (psa_key_bits_t) bits; - } -} - -static inline size_t psa_get_key_bits( - const psa_key_attributes_t *attributes) -{ - return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits); -} - -/** - * \brief The context for PSA interruptible hash signing. - */ -struct psa_sign_hash_interruptible_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_driver_sign_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); - - unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; - - uint32_t MBEDTLS_PRIVATE(num_ops); -}; - -#define PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } - -static inline struct psa_sign_hash_interruptible_operation_s -psa_sign_hash_interruptible_operation_init(void) -{ - const struct psa_sign_hash_interruptible_operation_s v = - PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; - - return v; -} - -/** - * \brief The context for PSA interruptible hash verification. - */ -struct psa_verify_hash_interruptible_operation_s { - /** Unique ID indicating which driver got assigned to do the - * operation. Since driver contexts are driver-specific, swapping - * drivers halfway through the operation is not supported. - * ID values are auto-generated in psa_crypto_driver_wrappers.h - * ID value zero means the context is not valid or not assigned to - * any driver (i.e. none of the driver contexts are active). */ - unsigned int MBEDTLS_PRIVATE(id); - - psa_driver_verify_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); - - unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; - - uint32_t MBEDTLS_PRIVATE(num_ops); -}; - -#define PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } - -static inline struct psa_verify_hash_interruptible_operation_s -psa_verify_hash_interruptible_operation_init(void) -{ - const struct psa_verify_hash_interruptible_operation_s v = - PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; - - return v; -} - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_STRUCT_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_struct.h + * + * \brief PSA cryptography module: Mbed TLS structured type implementations + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + * + * This file contains the definitions of some data structures with + * implementation-specific definitions. + * + * In implementations with isolation between the application and the + * cryptography module, it is expected that the front-end and the back-end + * would have different versions of this file. + * + *

Design notes about multipart operation structures

+ * + * For multipart operations without driver delegation support, each multipart + * operation structure contains a `psa_algorithm_t alg` field which indicates + * which specific algorithm the structure is for. When the structure is not in + * use, `alg` is 0. Most of the structure consists of a union which is + * discriminated by `alg`. + * + * For multipart operations with driver delegation support, each multipart + * operation structure contains an `unsigned int id` field indicating which + * driver got assigned to do the operation. When the structure is not in use, + * 'id' is 0. The structure contains also a driver context which is the union + * of the contexts of all drivers able to handle the type of multipart + * operation. + * + * Note that when `alg` or `id` is 0, the content of other fields is undefined. + * In particular, it is not guaranteed that a freshly-initialized structure + * is all-zero: we initialize structures to something like `{0, 0}`, which + * is only guaranteed to initializes the first member of the union; + * GCC and Clang initialize the whole structure to 0 (at the time of writing), + * but MSVC and CompCert don't. + * + * In Mbed TLS, multipart operation structures live independently from + * the key. This allows Mbed TLS to free the key objects when destroying + * a key slot. If a multipart operation needs to remember the key after + * the setup function returns, the operation structure needs to contain a + * copy of the key. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_struct.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_struct.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_STRUCT_H +#define PSA_CRYPTO_STRUCT_H +#include "mbedtls/private_access.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include the Mbed TLS configuration file, the way Mbed TLS does it + * in each of its header files. */ +#include "mbedtls/build_info.h" + +/* Include the context definition for the compiled-in drivers for the primitive + * algorithms. */ +#include "psa/crypto_driver_contexts_primitives.h" + +struct psa_hash_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_driver_wrappers.h. + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. the driver context is not active, in use). */ + unsigned int MBEDTLS_PRIVATE(id); + psa_driver_hash_context_t MBEDTLS_PRIVATE(ctx); +}; + +#define PSA_HASH_OPERATION_INIT { 0, { 0 } } +static inline struct psa_hash_operation_s psa_hash_operation_init(void) +{ + const struct psa_hash_operation_s v = PSA_HASH_OPERATION_INIT; + return v; +} + +struct psa_cipher_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_crypto_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + + unsigned int MBEDTLS_PRIVATE(iv_required) : 1; + unsigned int MBEDTLS_PRIVATE(iv_set) : 1; + + uint8_t MBEDTLS_PRIVATE(default_iv_length); + + psa_driver_cipher_context_t MBEDTLS_PRIVATE(ctx); +}; + +#define PSA_CIPHER_OPERATION_INIT { 0, 0, 0, 0, { 0 } } +static inline struct psa_cipher_operation_s psa_cipher_operation_init(void) +{ + const struct psa_cipher_operation_s v = PSA_CIPHER_OPERATION_INIT; + return v; +} + +/* Include the context definition for the compiled-in drivers for the composite + * algorithms. */ +#include "psa/crypto_driver_contexts_composites.h" + +struct psa_mac_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + uint8_t MBEDTLS_PRIVATE(mac_size); + unsigned int MBEDTLS_PRIVATE(is_sign) : 1; + psa_driver_mac_context_t MBEDTLS_PRIVATE(ctx); +}; + +#define PSA_MAC_OPERATION_INIT { 0, 0, 0, { 0 } } +static inline struct psa_mac_operation_s psa_mac_operation_init(void) +{ + const struct psa_mac_operation_s v = PSA_MAC_OPERATION_INIT; + return v; +} + +struct psa_aead_operation_s { + + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_crypto_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + + psa_algorithm_t MBEDTLS_PRIVATE(alg); + psa_key_type_t MBEDTLS_PRIVATE(key_type); + + size_t MBEDTLS_PRIVATE(ad_remaining); + size_t MBEDTLS_PRIVATE(body_remaining); + + unsigned int MBEDTLS_PRIVATE(nonce_set) : 1; + unsigned int MBEDTLS_PRIVATE(lengths_set) : 1; + unsigned int MBEDTLS_PRIVATE(ad_started) : 1; + unsigned int MBEDTLS_PRIVATE(body_started) : 1; + unsigned int MBEDTLS_PRIVATE(is_encrypt) : 1; + + psa_driver_aead_context_t MBEDTLS_PRIVATE(ctx); +}; + +#define PSA_AEAD_OPERATION_INIT { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0 } } +static inline struct psa_aead_operation_s psa_aead_operation_init(void) +{ + const struct psa_aead_operation_s v = PSA_AEAD_OPERATION_INIT; + return v; +} + +/* Include the context definition for the compiled-in drivers for the key + * derivation algorithms. */ +#include "psa/crypto_driver_contexts_key_derivation.h" + +struct psa_key_derivation_s { + psa_algorithm_t MBEDTLS_PRIVATE(alg); + unsigned int MBEDTLS_PRIVATE(can_output_key) : 1; + size_t MBEDTLS_PRIVATE(capacity); + psa_driver_key_derivation_context_t MBEDTLS_PRIVATE(ctx); +}; + +/* This only zeroes out the first byte in the union, the rest is unspecified. */ +#define PSA_KEY_DERIVATION_OPERATION_INIT { 0, 0, 0, { 0 } } +static inline struct psa_key_derivation_s psa_key_derivation_operation_init( + void) +{ + const struct psa_key_derivation_s v = PSA_KEY_DERIVATION_OPERATION_INIT; + return v; +} + +struct psa_key_policy_s { + psa_key_usage_t MBEDTLS_PRIVATE(usage); + psa_algorithm_t MBEDTLS_PRIVATE(alg); + psa_algorithm_t MBEDTLS_PRIVATE(alg2); +}; +typedef struct psa_key_policy_s psa_key_policy_t; + +#define PSA_KEY_POLICY_INIT { 0, 0, 0 } +static inline struct psa_key_policy_s psa_key_policy_init(void) +{ + const struct psa_key_policy_s v = PSA_KEY_POLICY_INIT; + return v; +} + +/* The type used internally for key sizes. + * Public interfaces use size_t, but internally we use a smaller type. */ +typedef uint16_t psa_key_bits_t; +/* The maximum value of the type used to represent bit-sizes. + * This is used to mark an invalid key size. */ +#define PSA_KEY_BITS_TOO_LARGE ((psa_key_bits_t) -1) +/* The maximum size of a key in bits. + * Currently defined as the maximum that can be represented, rounded down + * to a whole number of bytes. + * This is an uncast value so that it can be used in preprocessor + * conditionals. */ +#ifndef PSA_MAX_KEY_BITS +#define PSA_MAX_KEY_BITS 0xfff8 +#endif + +/** A mask of flags that can be stored in key attributes. + * + * This type is also used internally to store flags in slots. Internal + * flags are defined in library/psa_crypto_core.h. Internal flags may have + * the same value as external flags if they are properly handled during + * key creation and in psa_get_key_attributes. + */ +typedef uint16_t psa_key_attributes_flag_t; + +#define MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER \ + ((psa_key_attributes_flag_t) 0x0001) + +/* A mask of key attribute flags used externally only. + * Only meant for internal checks inside the library. */ +#define MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY ( \ + MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER | \ + 0) + +/* A mask of key attribute flags used both internally and externally. + * Currently there aren't any. */ +#define MBEDTLS_PSA_KA_MASK_DUAL_USE ( \ + 0) + +typedef struct { + psa_key_type_t MBEDTLS_PRIVATE(type); + psa_key_bits_t MBEDTLS_PRIVATE(bits); + psa_key_lifetime_t MBEDTLS_PRIVATE(lifetime); + mbedtls_svc_key_id_t MBEDTLS_PRIVATE(id); + psa_key_policy_t MBEDTLS_PRIVATE(policy); + psa_key_attributes_flag_t MBEDTLS_PRIVATE(flags); +} psa_core_key_attributes_t; + +#define PSA_CORE_KEY_ATTRIBUTES_INIT { PSA_KEY_TYPE_NONE, 0, \ + PSA_KEY_LIFETIME_VOLATILE, \ + MBEDTLS_SVC_KEY_ID_INIT, \ + PSA_KEY_POLICY_INIT, 0 } + +struct psa_key_attributes_s { + psa_core_key_attributes_t MBEDTLS_PRIVATE(core); +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + psa_key_slot_number_t MBEDTLS_PRIVATE(slot_number); +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + void *MBEDTLS_PRIVATE(domain_parameters); + size_t MBEDTLS_PRIVATE(domain_parameters_size); +}; + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +#define PSA_KEY_ATTRIBUTES_INIT { PSA_CORE_KEY_ATTRIBUTES_INIT, 0, NULL, 0 } +#else +#define PSA_KEY_ATTRIBUTES_INIT { PSA_CORE_KEY_ATTRIBUTES_INIT, NULL, 0 } +#endif + +static inline struct psa_key_attributes_s psa_key_attributes_init(void) +{ + const struct psa_key_attributes_s v = PSA_KEY_ATTRIBUTES_INIT; + return v; +} + +static inline void psa_set_key_id(psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t key) +{ + psa_key_lifetime_t lifetime = attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); + + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = key; + + if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_LIFETIME_PERSISTENT, + PSA_KEY_LIFETIME_GET_LOCATION(lifetime)); + } +} + +static inline mbedtls_svc_key_id_t psa_get_key_id( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id); +} + +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER +static inline void mbedtls_set_key_owner_id(psa_key_attributes_t *attributes, + mbedtls_key_owner_id_t owner) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(owner) = owner; +} +#endif + +static inline void psa_set_key_lifetime(psa_key_attributes_t *attributes, + psa_key_lifetime_t lifetime) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime) = lifetime; + if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id).MBEDTLS_PRIVATE(key_id) = 0; +#else + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(id) = 0; +#endif + } +} + +static inline psa_key_lifetime_t psa_get_key_lifetime( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(lifetime); +} + +static inline void psa_extend_key_usage_flags(psa_key_usage_t *usage_flags) +{ + if (*usage_flags & PSA_KEY_USAGE_SIGN_HASH) { + *usage_flags |= PSA_KEY_USAGE_SIGN_MESSAGE; + } + + if (*usage_flags & PSA_KEY_USAGE_VERIFY_HASH) { + *usage_flags |= PSA_KEY_USAGE_VERIFY_MESSAGE; + } +} + +static inline void psa_set_key_usage_flags(psa_key_attributes_t *attributes, + psa_key_usage_t usage_flags) +{ + psa_extend_key_usage_flags(&usage_flags); + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage) = usage_flags; +} + +static inline psa_key_usage_t psa_get_key_usage_flags( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(usage); +} + +static inline void psa_set_key_algorithm(psa_key_attributes_t *attributes, + psa_algorithm_t alg) +{ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg) = alg; +} + +static inline psa_algorithm_t psa_get_key_algorithm( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(policy).MBEDTLS_PRIVATE(alg); +} + +/* This function is declared in crypto_extra.h, which comes after this + * header file, but we need the function here, so repeat the declaration. */ +psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, + psa_key_type_t type, + const uint8_t *data, + size_t data_length); + +static inline void psa_set_key_type(psa_key_attributes_t *attributes, + psa_key_type_t type) +{ + if (attributes->MBEDTLS_PRIVATE(domain_parameters) == NULL) { + /* Common case: quick path */ + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type) = type; + } else { + /* Call the bigger function to free the old domain parameters. + * Ignore any errors which may arise due to type requiring + * non-default domain parameters, since this function can't + * report errors. */ + (void) psa_set_key_domain_parameters(attributes, type, NULL, 0); + } +} + +static inline psa_key_type_t psa_get_key_type( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(type); +} + +static inline void psa_set_key_bits(psa_key_attributes_t *attributes, + size_t bits) +{ + if (bits > PSA_MAX_KEY_BITS) { + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = PSA_KEY_BITS_TOO_LARGE; + } else { + attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits) = (psa_key_bits_t) bits; + } +} + +static inline size_t psa_get_key_bits( + const psa_key_attributes_t *attributes) +{ + return attributes->MBEDTLS_PRIVATE(core).MBEDTLS_PRIVATE(bits); +} + +/** + * \brief The context for PSA interruptible hash signing. + */ +struct psa_sign_hash_interruptible_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_crypto_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + + psa_driver_sign_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); + + unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; + + uint32_t MBEDTLS_PRIVATE(num_ops); +}; + +#define PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } + +static inline struct psa_sign_hash_interruptible_operation_s +psa_sign_hash_interruptible_operation_init(void) +{ + const struct psa_sign_hash_interruptible_operation_s v = + PSA_SIGN_HASH_INTERRUPTIBLE_OPERATION_INIT; + + return v; +} + +/** + * \brief The context for PSA interruptible hash verification. + */ +struct psa_verify_hash_interruptible_operation_s { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_crypto_driver_wrappers.h + * ID value zero means the context is not valid or not assigned to + * any driver (i.e. none of the driver contexts are active). */ + unsigned int MBEDTLS_PRIVATE(id); + + psa_driver_verify_hash_interruptible_context_t MBEDTLS_PRIVATE(ctx); + + unsigned int MBEDTLS_PRIVATE(error_occurred) : 1; + + uint32_t MBEDTLS_PRIVATE(num_ops); +}; + +#define PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT { 0, { 0 }, 0, 0 } + +static inline struct psa_verify_hash_interruptible_operation_s +psa_verify_hash_interruptible_operation_init(void) +{ + const struct psa_verify_hash_interruptible_operation_s v = + PSA_VERIFY_HASH_INTERRUPTIBLE_OPERATION_INIT; + + return v; +} + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_STRUCT_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_types.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_types.h index 130d845..ed3d601 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_types.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_types.h @@ -1,479 +1,479 @@ -/** - * \file psa/crypto_types.h - * - * \brief PSA cryptography module: type aliases. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. Drivers must include the appropriate driver - * header file. - * - * This file contains portable definitions of integral types for properties - * of cryptographic keys, designations of cryptographic algorithms, and - * error codes returned by the library. - * - * This header file does not declare any function. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_types.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_types.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_TYPES_H -#define PSA_CRYPTO_TYPES_H - -/* Make sure the Mbed TLS configuration is visible. */ -#include "mbedtls/build_info.h" -/* Define the MBEDTLS_PRIVATE macro. */ -#include "mbedtls/private_access.h" - -#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) -#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE -#else -#include "crypto_platform.h" -#endif - -#include - -/** \defgroup error Error codes - * @{ - */ - -/** - * \brief Function return status. - * - * This is either #PSA_SUCCESS (which is zero), indicating success, - * or a small negative value indicating that an error occurred. Errors are - * encoded as one of the \c PSA_ERROR_xxx values defined here. */ -/* If #PSA_SUCCESS is already defined, it means that #psa_status_t - * is also defined in an external header, so prevent its multiple - * definition. - */ -#ifndef PSA_SUCCESS -typedef int32_t psa_status_t; -#endif - -/**@}*/ - -/** \defgroup crypto_types Key and algorithm types - * @{ - */ - -/** \brief Encoding of a key type. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_TYPE_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint16_t psa_key_type_t; - -/** The type of PSA elliptic curve family identifiers. - * - * Values of this type are generally constructed by macros called - * `PSA_ECC_FAMILY_xxx`. - * - * The curve identifier is required to create an ECC key using the - * PSA_KEY_TYPE_ECC_KEY_PAIR() or PSA_KEY_TYPE_ECC_PUBLIC_KEY() - * macros. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional families must use an encoding in this range. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_ecc_family_t; - -/** The type of PSA Diffie-Hellman group family identifiers. - * - * Values of this type are generally constructed by macros called - * `PSA_DH_FAMILY_xxx`. - * - * The group identifier is required to create a Diffie-Hellman key using the - * PSA_KEY_TYPE_DH_KEY_PAIR() or PSA_KEY_TYPE_DH_PUBLIC_KEY() - * macros. - * - * Values defined by this standard will never be in the range 0x80-0xff. - * Vendors who define additional families must use an encoding in this range. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_dh_family_t; - -/** \brief Encoding of a cryptographic algorithm. - * - * Values of this type are generally constructed by macros called - * `PSA_ALG_xxx`. - * - * For algorithms that can be applied to multiple key types, this type - * does not encode the key type. For example, for symmetric ciphers - * based on a block cipher, #psa_algorithm_t encodes the block cipher - * mode and the padding mode while the block cipher itself is encoded - * via #psa_key_type_t. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_algorithm_t; - -/**@}*/ - -/** \defgroup key_lifetimes Key lifetimes - * @{ - */ - -/** Encoding of key lifetimes. - * - * The lifetime of a key indicates where it is stored and what system actions - * may create and destroy it. - * - * Lifetime values have the following structure: - * - Bits 0-7 (#PSA_KEY_LIFETIME_GET_PERSISTENCE(\c lifetime)): - * persistence level. This value indicates what device management - * actions can cause it to be destroyed. In particular, it indicates - * whether the key is _volatile_ or _persistent_. - * See ::psa_key_persistence_t for more information. - * - Bits 8-31 (#PSA_KEY_LIFETIME_GET_LOCATION(\c lifetime)): - * location indicator. This value indicates which part of the system - * has access to the key material and can perform operations using the key. - * See ::psa_key_location_t for more information. - * - * Volatile keys are automatically destroyed when the application instance - * terminates or on a power reset of the device. Persistent keys are - * preserved until the application explicitly destroys them or until an - * integration-specific device management event occurs (for example, - * a factory reset). - * - * Persistent keys have a key identifier of type #mbedtls_svc_key_id_t. - * This identifier remains valid throughout the lifetime of the key, - * even if the application instance that created the key terminates. - * The application can call psa_open_key() to open a persistent key that - * it created previously. - * - * The default lifetime of a key is #PSA_KEY_LIFETIME_VOLATILE. The lifetime - * #PSA_KEY_LIFETIME_PERSISTENT is supported if persistent storage is - * available. Other lifetime values may be supported depending on the - * library configuration. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_LIFETIME_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_lifetime_t; - -/** Encoding of key persistence levels. - * - * What distinguishes different persistence levels is what device management - * events may cause keys to be destroyed. _Volatile_ keys are destroyed - * by a power reset. Persistent keys may be destroyed by events such as - * a transfer of ownership or a factory reset. What management events - * actually affect persistent keys at different levels is outside the - * scope of the PSA Cryptography specification. - * - * The PSA Cryptography specification defines the following values of - * persistence levels: - * - \c 0 = #PSA_KEY_PERSISTENCE_VOLATILE: volatile key. - * A volatile key is automatically destroyed by the implementation when - * the application instance terminates. In particular, a volatile key - * is automatically destroyed on a power reset of the device. - * - \c 1 = #PSA_KEY_PERSISTENCE_DEFAULT: - * persistent key with a default lifetime. - * - \c 2-254: currently not supported by Mbed TLS. - * - \c 255 = #PSA_KEY_PERSISTENCE_READ_ONLY: - * read-only or write-once key. - * A key with this persistence level cannot be destroyed. - * Mbed TLS does not currently offer a way to create such keys, but - * integrations of Mbed TLS can use it for built-in keys that the - * application cannot modify (for example, a hardware unique key (HUK)). - * - * \note Key persistence levels are 8-bit values. Key management - * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which - * encode the persistence as the lower 8 bits of a 32-bit value. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint8_t psa_key_persistence_t; - -/** Encoding of key location indicators. - * - * If an integration of Mbed TLS can make calls to external - * cryptoprocessors such as secure elements, the location of a key - * indicates which secure element performs the operations on the key. - * Depending on the design of the secure element, the key - * material may be stored either in the secure element, or - * in wrapped (encrypted) form alongside the key metadata in the - * primary local storage. - * - * The PSA Cryptography API specification defines the following values of - * location indicators: - * - \c 0: primary local storage. - * This location is always available. - * The primary local storage is typically the same storage area that - * contains the key metadata. - * - \c 1: primary secure element. - * Integrations of Mbed TLS should support this value if there is a secure - * element attached to the operating environment. - * As a guideline, secure elements may provide higher resistance against - * side channel and physical attacks than the primary local storage, but may - * have restrictions on supported key types, sizes, policies and operations - * and may have different performance characteristics. - * - \c 2-0x7fffff: other locations defined by a PSA specification. - * The PSA Cryptography API does not currently assign any meaning to these - * locations, but future versions of that specification or other PSA - * specifications may do so. - * - \c 0x800000-0xffffff: vendor-defined locations. - * No PSA specification will assign a meaning to locations in this range. - * - * \note Key location indicators are 24-bit values. Key management - * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which - * encode the location as the upper 24 bits of a 32-bit value. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_location_t; - -/** Encoding of identifiers of persistent keys. - * - * - Applications may freely choose key identifiers in the range - * #PSA_KEY_ID_USER_MIN to #PSA_KEY_ID_USER_MAX. - * \note This file was shipped as part of the Silicon Labs SDK. Users of the - * Silicon Labs SDK need to be aware that the entire SDK is considered - * the 'application' from the mbed TLS / PSA documentation perspective. - * Please refer to \ref sl_psa_usage_key_namespacing to see which key - * identifiers are available to Silicon Labs SDK users. - * - The implementation may define additional key identifiers in the range - * #PSA_KEY_ID_VENDOR_MIN to #PSA_KEY_ID_VENDOR_MAX. - * - 0 is reserved as an invalid key identifier. - * - Key identifiers outside these ranges are reserved for future use. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to how values are allocated must require careful - * consideration to allow backward compatibility. - */ -typedef uint32_t psa_key_id_t; - -/** Encoding of key identifiers as seen inside the PSA Crypto implementation. - * - * When PSA Crypto is built as a library inside an application, this type - * is identical to #psa_key_id_t. When PSA Crypto is built as a service - * that can store keys on behalf of multiple clients, this type - * encodes the #psa_key_id_t value seen by each client application as - * well as extra information that identifies the client that owns - * the key. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) -typedef psa_key_id_t mbedtls_svc_key_id_t; - -#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ -/* Implementation-specific: The Mbed TLS library can be built as - * part of a multi-client service that exposes the PSA Cryptography API in each - * client and encodes the client identity in the key identifier argument of - * functions such as psa_open_key(). - */ -typedef struct { - psa_key_id_t MBEDTLS_PRIVATE(key_id); - mbedtls_key_owner_id_t MBEDTLS_PRIVATE(owner); -} mbedtls_svc_key_id_t; - -#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/**@}*/ - -/** \defgroup policy Key policies - * @{ - */ - -/** \brief Encoding of permitted usage on a key. - * - * Values of this type are generally constructed as bitwise-ors of macros - * called `PSA_KEY_USAGE_xxx`. - * - * \note Values of this type are encoded in the persistent key store. - * Any changes to existing values will require bumping the storage - * format version and providing a translation when reading the old - * format. - */ -typedef uint32_t psa_key_usage_t; - -/**@}*/ - -/** \defgroup attributes Key attributes - * @{ - */ - -/** The type of a structure containing key attributes. - * - * This is an opaque structure that can represent the metadata of a key - * object. Metadata that can be stored in attributes includes: - * - The location of the key in storage, indicated by its key identifier - * and its lifetime. - * - The key's policy, comprising usage flags and a specification of - * the permitted algorithm(s). - * - Information about the key itself: the key type and its size. - * - Additional implementation-defined attributes. - * - * The actual key material is not considered an attribute of a key. - * Key attributes do not contain information that is generally considered - * highly confidential. - * - * An attribute structure works like a simple data structure where each function - * `psa_set_key_xxx` sets a field and the corresponding function - * `psa_get_key_xxx` retrieves the value of the corresponding field. - * However, a future version of the library may report values that are - * equivalent to the original one, but have a different encoding. Invalid - * values may be mapped to different, also invalid values. - * - * An attribute structure may contain references to auxiliary resources, - * for example pointers to allocated memory or indirect references to - * pre-calculated values. In order to free such resources, the application - * must call psa_reset_key_attributes(). As an exception, calling - * psa_reset_key_attributes() on an attribute structure is optional if - * the structure has only been modified by the following functions - * since it was initialized or last reset with psa_reset_key_attributes(): - * - psa_set_key_id() - * - psa_set_key_lifetime() - * - psa_set_key_type() - * - psa_set_key_bits() - * - psa_set_key_usage_flags() - * - psa_set_key_algorithm() - * - * Before calling any function on a key attribute structure, the application - * must initialize it by any of the following means: - * - Set the structure to all-bits-zero, for example: - * \code - * psa_key_attributes_t attributes; - * memset(&attributes, 0, sizeof(attributes)); - * \endcode - * - Initialize the structure to logical zero values, for example: - * \code - * psa_key_attributes_t attributes = {0}; - * \endcode - * - Initialize the structure to the initializer #PSA_KEY_ATTRIBUTES_INIT, - * for example: - * \code - * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - * \endcode - * - Assign the result of the function psa_key_attributes_init() - * to the structure, for example: - * \code - * psa_key_attributes_t attributes; - * attributes = psa_key_attributes_init(); - * \endcode - * - * A freshly initialized attribute structure contains the following - * values: - * - * - lifetime: #PSA_KEY_LIFETIME_VOLATILE. - * - key identifier: 0 (which is not a valid key identifier). - * - type: \c 0 (meaning that the type is unspecified). - * - key size: \c 0 (meaning that the size is unspecified). - * - usage flags: \c 0 (which allows no usage except exporting a public key). - * - algorithm: \c 0 (which allows no cryptographic usage, but allows - * exporting). - * - * A typical sequence to create a key is as follows: - * -# Create and initialize an attribute structure. - * -# If the key is persistent, call psa_set_key_id(). - * Also call psa_set_key_lifetime() to place the key in a non-default - * location. - * -# Set the key policy with psa_set_key_usage_flags() and - * psa_set_key_algorithm(). - * -# Set the key type with psa_set_key_type(). - * Skip this step if copying an existing key with psa_copy_key(). - * -# When generating a random key with psa_generate_key() or deriving a key - * with psa_key_derivation_output_key(), set the desired key size with - * psa_set_key_bits(). - * -# Call a key creation function: psa_import_key(), psa_generate_key(), - * psa_key_derivation_output_key() or psa_copy_key(). This function reads - * the attribute structure, creates a key with these attributes, and - * outputs a key identifier to the newly created key. - * -# The attribute structure is now no longer necessary. - * You may call psa_reset_key_attributes(), although this is optional - * with the workflow presented here because the attributes currently - * defined in this specification do not require any additional resources - * beyond the structure itself. - * - * A typical sequence to query a key's attributes is as follows: - * -# Call psa_get_key_attributes(). - * -# Call `psa_get_key_xxx` functions to retrieve the attribute(s) that - * you are interested in. - * -# Call psa_reset_key_attributes() to free any resources that may be - * used by the attribute structure. - * - * Once a key has been created, it is impossible to change its attributes. - */ -typedef struct psa_key_attributes_s psa_key_attributes_t; - - -#ifndef __DOXYGEN_ONLY__ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* Mbed TLS defines this type in crypto_types.h because it is also - * visible to applications through an implementation-specific extension. - * For the PSA Cryptography specification, this type is only visible - * via crypto_se_driver.h. */ -typedef uint64_t psa_key_slot_number_t; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ -#endif /* !__DOXYGEN_ONLY__ */ - -/**@}*/ - -/** \defgroup derivation Key derivation - * @{ - */ - -/** \brief Encoding of the step of a key derivation. - * - * Values of this type are generally constructed by macros called - * `PSA_KEY_DERIVATION_INPUT_xxx`. - */ -typedef uint16_t psa_key_derivation_step_t; - -/**@}*/ - -#endif /* PSA_CRYPTO_TYPES_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_types.h + * + * \brief PSA cryptography module: type aliases. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. Drivers must include the appropriate driver + * header file. + * + * This file contains portable definitions of integral types for properties + * of cryptographic keys, designations of cryptographic algorithms, and + * error codes returned by the library. + * + * This header file does not declare any function. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_types.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_types.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_TYPES_H +#define PSA_CRYPTO_TYPES_H + +/* Make sure the Mbed TLS configuration is visible. */ +#include "mbedtls/build_info.h" +/* Define the MBEDTLS_PRIVATE macro. */ +#include "mbedtls/private_access.h" + +#if defined(MBEDTLS_PSA_CRYPTO_PLATFORM_FILE) +#include MBEDTLS_PSA_CRYPTO_PLATFORM_FILE +#else +#include "crypto_platform.h" +#endif + +#include + +/** \defgroup error Error codes + * @{ + */ + +/** + * \brief Function return status. + * + * This is either #PSA_SUCCESS (which is zero), indicating success, + * or a small negative value indicating that an error occurred. Errors are + * encoded as one of the \c PSA_ERROR_xxx values defined here. */ +/* If #PSA_SUCCESS is already defined, it means that #psa_status_t + * is also defined in an external header, so prevent its multiple + * definition. + */ +#ifndef PSA_SUCCESS +typedef int32_t psa_status_t; +#endif + +/**@}*/ + +/** \defgroup crypto_types Key and algorithm types + * @{ + */ + +/** \brief Encoding of a key type. + * + * Values of this type are generally constructed by macros called + * `PSA_KEY_TYPE_xxx`. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint16_t psa_key_type_t; + +/** The type of PSA elliptic curve family identifiers. + * + * Values of this type are generally constructed by macros called + * `PSA_ECC_FAMILY_xxx`. + * + * The curve identifier is required to create an ECC key using the + * PSA_KEY_TYPE_ECC_KEY_PAIR() or PSA_KEY_TYPE_ECC_PUBLIC_KEY() + * macros. + * + * Values defined by this standard will never be in the range 0x80-0xff. + * Vendors who define additional families must use an encoding in this range. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint8_t psa_ecc_family_t; + +/** The type of PSA Diffie-Hellman group family identifiers. + * + * Values of this type are generally constructed by macros called + * `PSA_DH_FAMILY_xxx`. + * + * The group identifier is required to create a Diffie-Hellman key using the + * PSA_KEY_TYPE_DH_KEY_PAIR() or PSA_KEY_TYPE_DH_PUBLIC_KEY() + * macros. + * + * Values defined by this standard will never be in the range 0x80-0xff. + * Vendors who define additional families must use an encoding in this range. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint8_t psa_dh_family_t; + +/** \brief Encoding of a cryptographic algorithm. + * + * Values of this type are generally constructed by macros called + * `PSA_ALG_xxx`. + * + * For algorithms that can be applied to multiple key types, this type + * does not encode the key type. For example, for symmetric ciphers + * based on a block cipher, #psa_algorithm_t encodes the block cipher + * mode and the padding mode while the block cipher itself is encoded + * via #psa_key_type_t. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint32_t psa_algorithm_t; + +/**@}*/ + +/** \defgroup key_lifetimes Key lifetimes + * @{ + */ + +/** Encoding of key lifetimes. + * + * The lifetime of a key indicates where it is stored and what system actions + * may create and destroy it. + * + * Lifetime values have the following structure: + * - Bits 0-7 (#PSA_KEY_LIFETIME_GET_PERSISTENCE(\c lifetime)): + * persistence level. This value indicates what device management + * actions can cause it to be destroyed. In particular, it indicates + * whether the key is _volatile_ or _persistent_. + * See ::psa_key_persistence_t for more information. + * - Bits 8-31 (#PSA_KEY_LIFETIME_GET_LOCATION(\c lifetime)): + * location indicator. This value indicates which part of the system + * has access to the key material and can perform operations using the key. + * See ::psa_key_location_t for more information. + * + * Volatile keys are automatically destroyed when the application instance + * terminates or on a power reset of the device. Persistent keys are + * preserved until the application explicitly destroys them or until an + * integration-specific device management event occurs (for example, + * a factory reset). + * + * Persistent keys have a key identifier of type #mbedtls_svc_key_id_t. + * This identifier remains valid throughout the lifetime of the key, + * even if the application instance that created the key terminates. + * The application can call psa_open_key() to open a persistent key that + * it created previously. + * + * The default lifetime of a key is #PSA_KEY_LIFETIME_VOLATILE. The lifetime + * #PSA_KEY_LIFETIME_PERSISTENT is supported if persistent storage is + * available. Other lifetime values may be supported depending on the + * library configuration. + * + * Values of this type are generally constructed by macros called + * `PSA_KEY_LIFETIME_xxx`. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint32_t psa_key_lifetime_t; + +/** Encoding of key persistence levels. + * + * What distinguishes different persistence levels is what device management + * events may cause keys to be destroyed. _Volatile_ keys are destroyed + * by a power reset. Persistent keys may be destroyed by events such as + * a transfer of ownership or a factory reset. What management events + * actually affect persistent keys at different levels is outside the + * scope of the PSA Cryptography specification. + * + * The PSA Cryptography specification defines the following values of + * persistence levels: + * - \c 0 = #PSA_KEY_PERSISTENCE_VOLATILE: volatile key. + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * - \c 1 = #PSA_KEY_PERSISTENCE_DEFAULT: + * persistent key with a default lifetime. + * - \c 2-254: currently not supported by Mbed TLS. + * - \c 255 = #PSA_KEY_PERSISTENCE_READ_ONLY: + * read-only or write-once key. + * A key with this persistence level cannot be destroyed. + * Mbed TLS does not currently offer a way to create such keys, but + * integrations of Mbed TLS can use it for built-in keys that the + * application cannot modify (for example, a hardware unique key (HUK)). + * + * \note Key persistence levels are 8-bit values. Key management + * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which + * encode the persistence as the lower 8 bits of a 32-bit value. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint8_t psa_key_persistence_t; + +/** Encoding of key location indicators. + * + * If an integration of Mbed TLS can make calls to external + * cryptoprocessors such as secure elements, the location of a key + * indicates which secure element performs the operations on the key. + * Depending on the design of the secure element, the key + * material may be stored either in the secure element, or + * in wrapped (encrypted) form alongside the key metadata in the + * primary local storage. + * + * The PSA Cryptography API specification defines the following values of + * location indicators: + * - \c 0: primary local storage. + * This location is always available. + * The primary local storage is typically the same storage area that + * contains the key metadata. + * - \c 1: primary secure element. + * Integrations of Mbed TLS should support this value if there is a secure + * element attached to the operating environment. + * As a guideline, secure elements may provide higher resistance against + * side channel and physical attacks than the primary local storage, but may + * have restrictions on supported key types, sizes, policies and operations + * and may have different performance characteristics. + * - \c 2-0x7fffff: other locations defined by a PSA specification. + * The PSA Cryptography API does not currently assign any meaning to these + * locations, but future versions of that specification or other PSA + * specifications may do so. + * - \c 0x800000-0xffffff: vendor-defined locations. + * No PSA specification will assign a meaning to locations in this range. + * + * \note Key location indicators are 24-bit values. Key management + * interfaces operate on lifetimes (type ::psa_key_lifetime_t) which + * encode the location as the upper 24 bits of a 32-bit value. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint32_t psa_key_location_t; + +/** Encoding of identifiers of persistent keys. + * + * - Applications may freely choose key identifiers in the range + * #PSA_KEY_ID_USER_MIN to #PSA_KEY_ID_USER_MAX. + * \note This file was shipped as part of the Silicon Labs SDK. Users of the + * Silicon Labs SDK need to be aware that the entire SDK is considered + * the 'application' from the mbed TLS / PSA documentation perspective. + * Please refer to \ref sl_psa_usage_key_namespacing to see which key + * identifiers are available to Silicon Labs SDK users. + * - The implementation may define additional key identifiers in the range + * #PSA_KEY_ID_VENDOR_MIN to #PSA_KEY_ID_VENDOR_MAX. + * - 0 is reserved as an invalid key identifier. + * - Key identifiers outside these ranges are reserved for future use. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to how values are allocated must require careful + * consideration to allow backward compatibility. + */ +typedef uint32_t psa_key_id_t; + +/** Encoding of key identifiers as seen inside the PSA Crypto implementation. + * + * When PSA Crypto is built as a library inside an application, this type + * is identical to #psa_key_id_t. When PSA Crypto is built as a service + * that can store keys on behalf of multiple clients, this type + * encodes the #psa_key_id_t value seen by each client application as + * well as extra information that identifies the client that owns + * the key. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) +typedef psa_key_id_t mbedtls_svc_key_id_t; + +#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ +/* Implementation-specific: The Mbed TLS library can be built as + * part of a multi-client service that exposes the PSA Cryptography API in each + * client and encodes the client identity in the key identifier argument of + * functions such as psa_open_key(). + */ +typedef struct { + psa_key_id_t MBEDTLS_PRIVATE(key_id); + mbedtls_key_owner_id_t MBEDTLS_PRIVATE(owner); +} mbedtls_svc_key_id_t; + +#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ + +/**@}*/ + +/** \defgroup policy Key policies + * @{ + */ + +/** \brief Encoding of permitted usage on a key. + * + * Values of this type are generally constructed as bitwise-ors of macros + * called `PSA_KEY_USAGE_xxx`. + * + * \note Values of this type are encoded in the persistent key store. + * Any changes to existing values will require bumping the storage + * format version and providing a translation when reading the old + * format. + */ +typedef uint32_t psa_key_usage_t; + +/**@}*/ + +/** \defgroup attributes Key attributes + * @{ + */ + +/** The type of a structure containing key attributes. + * + * This is an opaque structure that can represent the metadata of a key + * object. Metadata that can be stored in attributes includes: + * - The location of the key in storage, indicated by its key identifier + * and its lifetime. + * - The key's policy, comprising usage flags and a specification of + * the permitted algorithm(s). + * - Information about the key itself: the key type and its size. + * - Additional implementation-defined attributes. + * + * The actual key material is not considered an attribute of a key. + * Key attributes do not contain information that is generally considered + * highly confidential. + * + * An attribute structure works like a simple data structure where each function + * `psa_set_key_xxx` sets a field and the corresponding function + * `psa_get_key_xxx` retrieves the value of the corresponding field. + * However, a future version of the library may report values that are + * equivalent to the original one, but have a different encoding. Invalid + * values may be mapped to different, also invalid values. + * + * An attribute structure may contain references to auxiliary resources, + * for example pointers to allocated memory or indirect references to + * pre-calculated values. In order to free such resources, the application + * must call psa_reset_key_attributes(). As an exception, calling + * psa_reset_key_attributes() on an attribute structure is optional if + * the structure has only been modified by the following functions + * since it was initialized or last reset with psa_reset_key_attributes(): + * - psa_set_key_id() + * - psa_set_key_lifetime() + * - psa_set_key_type() + * - psa_set_key_bits() + * - psa_set_key_usage_flags() + * - psa_set_key_algorithm() + * + * Before calling any function on a key attribute structure, the application + * must initialize it by any of the following means: + * - Set the structure to all-bits-zero, for example: + * \code + * psa_key_attributes_t attributes; + * memset(&attributes, 0, sizeof(attributes)); + * \endcode + * - Initialize the structure to logical zero values, for example: + * \code + * psa_key_attributes_t attributes = {0}; + * \endcode + * - Initialize the structure to the initializer #PSA_KEY_ATTRIBUTES_INIT, + * for example: + * \code + * psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + * \endcode + * - Assign the result of the function psa_key_attributes_init() + * to the structure, for example: + * \code + * psa_key_attributes_t attributes; + * attributes = psa_key_attributes_init(); + * \endcode + * + * A freshly initialized attribute structure contains the following + * values: + * + * - lifetime: #PSA_KEY_LIFETIME_VOLATILE. + * - key identifier: 0 (which is not a valid key identifier). + * - type: \c 0 (meaning that the type is unspecified). + * - key size: \c 0 (meaning that the size is unspecified). + * - usage flags: \c 0 (which allows no usage except exporting a public key). + * - algorithm: \c 0 (which allows no cryptographic usage, but allows + * exporting). + * + * A typical sequence to create a key is as follows: + * -# Create and initialize an attribute structure. + * -# If the key is persistent, call psa_set_key_id(). + * Also call psa_set_key_lifetime() to place the key in a non-default + * location. + * -# Set the key policy with psa_set_key_usage_flags() and + * psa_set_key_algorithm(). + * -# Set the key type with psa_set_key_type(). + * Skip this step if copying an existing key with psa_copy_key(). + * -# When generating a random key with psa_generate_key() or deriving a key + * with psa_key_derivation_output_key(), set the desired key size with + * psa_set_key_bits(). + * -# Call a key creation function: psa_import_key(), psa_generate_key(), + * psa_key_derivation_output_key() or psa_copy_key(). This function reads + * the attribute structure, creates a key with these attributes, and + * outputs a key identifier to the newly created key. + * -# The attribute structure is now no longer necessary. + * You may call psa_reset_key_attributes(), although this is optional + * with the workflow presented here because the attributes currently + * defined in this specification do not require any additional resources + * beyond the structure itself. + * + * A typical sequence to query a key's attributes is as follows: + * -# Call psa_get_key_attributes(). + * -# Call `psa_get_key_xxx` functions to retrieve the attribute(s) that + * you are interested in. + * -# Call psa_reset_key_attributes() to free any resources that may be + * used by the attribute structure. + * + * Once a key has been created, it is impossible to change its attributes. + */ +typedef struct psa_key_attributes_s psa_key_attributes_t; + + +#ifndef __DOXYGEN_ONLY__ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/* Mbed TLS defines this type in crypto_types.h because it is also + * visible to applications through an implementation-specific extension. + * For the PSA Cryptography specification, this type is only visible + * via crypto_se_driver.h. */ +typedef uint64_t psa_key_slot_number_t; +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ +#endif /* !__DOXYGEN_ONLY__ */ + +/**@}*/ + +/** \defgroup derivation Key derivation + * @{ + */ + +/** \brief Encoding of the step of a key derivation. + * + * Values of this type are generally constructed by macros called + * `PSA_KEY_DERIVATION_INPUT_xxx`. + */ +typedef uint16_t psa_key_derivation_step_t; + +/**@}*/ + +#endif /* PSA_CRYPTO_TYPES_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_values.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_values.h index b961e3e..bccd7bd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_values.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/include/psa/crypto_values.h @@ -1,2785 +1,2785 @@ -/** - * \file psa/crypto_values.h - * - * \brief PSA cryptography module: macros to build and analyze integer values. - * - * \note This file may not be included directly. Applications must - * include psa/crypto.h. Drivers must include the appropriate driver - * header file. - * - * This file contains portable definitions of macros to build and analyze - * values of integral types that encode properties of cryptographic keys, - * designations of cryptographic algorithms, and error codes returned by - * the library. - * - * Note that many of the constants defined in this file are embedded in - * the persistent key store, as part of key metadata (including usage - * policies). As a consequence, they must not be changed (unless the storage - * format version changes). - * - * This header file only defines preprocessor macros. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined(SL_TRUSTZONE_NONSECURE) - -/* The NonSecure app must use the crypto_values.h from the trusted-firmware-m repo. */ -#include "../../trusted-firmware-m/interface/include/psa/crypto_values.h" - -#else /* SL_TRUSTZONE_NONSECURE */ - -#ifndef PSA_CRYPTO_VALUES_H -#define PSA_CRYPTO_VALUES_H -#include "mbedtls/private_access.h" - -/** \defgroup error Error codes - * @{ - */ - -/* PSA error codes */ - -/* Error codes are standardized across PSA domains (framework, crypto, storage, - * etc.). Do not change the values in this section or even the expansions - * of each macro: it must be possible to `#include` both this header - * and some other PSA component's headers in the same C source, - * which will lead to duplicate definitions of the `PSA_SUCCESS` and - * `PSA_ERROR_xxx` macros, which is ok if and only if the macros expand - * to the same sequence of tokens. - * - * If you must add a new - * value, check with the Arm PSA framework group to pick one that other - * domains aren't already using. */ - -/* Tell uncrustify not to touch the constant definitions, otherwise - * it might change the spacing to something that is not PSA-compliant - * (e.g. adding a space after casts). - * - * *INDENT-OFF* - */ - -/** The action was completed successfully. */ -#define PSA_SUCCESS ((psa_status_t)0) - -/** An error occurred that does not correspond to any defined - * failure cause. - * - * Implementations may use this error code if none of the other standard - * error codes are applicable. */ -#define PSA_ERROR_GENERIC_ERROR ((psa_status_t)-132) - -/** The requested operation or a parameter is not supported - * by this implementation. - * - * Implementations should return this error code when an enumeration - * parameter such as a key type, algorithm, etc. is not recognized. - * If a combination of parameters is recognized and identified as - * not valid, return #PSA_ERROR_INVALID_ARGUMENT instead. */ -#define PSA_ERROR_NOT_SUPPORTED ((psa_status_t)-134) - -/** The requested action is denied by a policy. - * - * Implementations should return this error code when the parameters - * are recognized as valid and supported, and a policy explicitly - * denies the requested operation. - * - * If a subset of the parameters of a function call identify a - * forbidden operation, and another subset of the parameters are - * not valid or not supported, it is unspecified whether the function - * returns #PSA_ERROR_NOT_PERMITTED, #PSA_ERROR_NOT_SUPPORTED or - * #PSA_ERROR_INVALID_ARGUMENT. */ -#define PSA_ERROR_NOT_PERMITTED ((psa_status_t)-133) - -/** An output buffer is too small. - * - * Applications can call the \c PSA_xxx_SIZE macro listed in the function - * description to determine a sufficient buffer size. - * - * Implementations should preferably return this error code only - * in cases when performing the operation with a larger output - * buffer would succeed. However implementations may return this - * error if a function has invalid or unsupported parameters in addition - * to the parameters that determine the necessary output buffer size. */ -#define PSA_ERROR_BUFFER_TOO_SMALL ((psa_status_t)-138) - -/** Asking for an item that already exists - * - * Implementations should return this error, when attempting - * to write an item (like a key) that already exists. */ -#define PSA_ERROR_ALREADY_EXISTS ((psa_status_t)-139) - -/** Asking for an item that doesn't exist - * - * Implementations should return this error, if a requested item (like - * a key) does not exist. */ -#define PSA_ERROR_DOES_NOT_EXIST ((psa_status_t)-140) - -/** The requested action cannot be performed in the current state. - * - * Multipart operations return this error when one of the - * functions is called out of sequence. Refer to the function - * descriptions for permitted sequencing of functions. - * - * Implementations shall not return this error code to indicate - * that a key either exists or not, - * but shall instead return #PSA_ERROR_ALREADY_EXISTS or #PSA_ERROR_DOES_NOT_EXIST - * as applicable. - * - * Implementations shall not return this error code to indicate that a - * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE - * instead. */ -#define PSA_ERROR_BAD_STATE ((psa_status_t)-137) - -/** The parameters passed to the function are invalid. - * - * Implementations may return this error any time a parameter or - * combination of parameters are recognized as invalid. - * - * Implementations shall not return this error code to indicate that a - * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE - * instead. - */ -#define PSA_ERROR_INVALID_ARGUMENT ((psa_status_t)-135) - -/** There is not enough runtime memory. - * - * If the action is carried out across multiple security realms, this - * error can refer to available memory in any of the security realms. */ -#define PSA_ERROR_INSUFFICIENT_MEMORY ((psa_status_t)-141) - -/** There is not enough persistent storage. - * - * Functions that modify the key storage return this error code if - * there is insufficient storage space on the host media. In addition, - * many functions that do not otherwise access storage may return this - * error code if the implementation requires a mandatory log entry for - * the requested action and the log storage space is full. */ -#define PSA_ERROR_INSUFFICIENT_STORAGE ((psa_status_t)-142) - -/** There was a communication failure inside the implementation. - * - * This can indicate a communication failure between the application - * and an external cryptoprocessor or between the cryptoprocessor and - * an external volatile or persistent memory. A communication failure - * may be transient or permanent depending on the cause. - * - * \warning If a function returns this error, it is undetermined - * whether the requested action has completed or not. Implementations - * should return #PSA_SUCCESS on successful completion whenever - * possible, however functions may return #PSA_ERROR_COMMUNICATION_FAILURE - * if the requested action was completed successfully in an external - * cryptoprocessor but there was a breakdown of communication before - * the cryptoprocessor could report the status to the application. - */ -#define PSA_ERROR_COMMUNICATION_FAILURE ((psa_status_t)-145) - -/** There was a storage failure that may have led to data loss. - * - * This error indicates that some persistent storage is corrupted. - * It should not be used for a corruption of volatile memory - * (use #PSA_ERROR_CORRUPTION_DETECTED), for a communication error - * between the cryptoprocessor and its external storage (use - * #PSA_ERROR_COMMUNICATION_FAILURE), or when the storage is - * in a valid state but is full (use #PSA_ERROR_INSUFFICIENT_STORAGE). - * - * Note that a storage failure does not indicate that any data that was - * previously read is invalid. However this previously read data may no - * longer be readable from storage. - * - * When a storage failure occurs, it is no longer possible to ensure - * the global integrity of the keystore. Depending on the global - * integrity guarantees offered by the implementation, access to other - * data may or may not fail even if the data is still readable but - * its integrity cannot be guaranteed. - * - * Implementations should only use this error code to report a - * permanent storage corruption. However application writers should - * keep in mind that transient errors while reading the storage may be - * reported using this error code. */ -#define PSA_ERROR_STORAGE_FAILURE ((psa_status_t)-146) - -/** A hardware failure was detected. - * - * A hardware failure may be transient or permanent depending on the - * cause. */ -#define PSA_ERROR_HARDWARE_FAILURE ((psa_status_t)-147) - -/** A tampering attempt was detected. - * - * If an application receives this error code, there is no guarantee - * that previously accessed or computed data was correct and remains - * confidential. Applications should not perform any security function - * and should enter a safe failure state. - * - * Implementations may return this error code if they detect an invalid - * state that cannot happen during normal operation and that indicates - * that the implementation's security guarantees no longer hold. Depending - * on the implementation architecture and on its security and safety goals, - * the implementation may forcibly terminate the application. - * - * This error code is intended as a last resort when a security breach - * is detected and it is unsure whether the keystore data is still - * protected. Implementations shall only return this error code - * to report an alarm from a tampering detector, to indicate that - * the confidentiality of stored data can no longer be guaranteed, - * or to indicate that the integrity of previously returned data is now - * considered compromised. Implementations shall not use this error code - * to indicate a hardware failure that merely makes it impossible to - * perform the requested operation (use #PSA_ERROR_COMMUNICATION_FAILURE, - * #PSA_ERROR_STORAGE_FAILURE, #PSA_ERROR_HARDWARE_FAILURE, - * #PSA_ERROR_INSUFFICIENT_ENTROPY or other applicable error code - * instead). - * - * This error indicates an attack against the application. Implementations - * shall not return this error code as a consequence of the behavior of - * the application itself. */ -#define PSA_ERROR_CORRUPTION_DETECTED ((psa_status_t)-151) - -/** There is not enough entropy to generate random data needed - * for the requested action. - * - * This error indicates a failure of a hardware random generator. - * Application writers should note that this error can be returned not - * only by functions whose purpose is to generate random data, such - * as key, IV or nonce generation, but also by functions that execute - * an algorithm with a randomized result, as well as functions that - * use randomization of intermediate computations as a countermeasure - * to certain attacks. - * - * Implementations should avoid returning this error after psa_crypto_init() - * has succeeded. Implementations should generate sufficient - * entropy during initialization and subsequently use a cryptographically - * secure pseudorandom generator (PRNG). However implementations may return - * this error at any time if a policy requires the PRNG to be reseeded - * during normal operation. */ -#define PSA_ERROR_INSUFFICIENT_ENTROPY ((psa_status_t)-148) - -/** The signature, MAC or hash is incorrect. - * - * Verification functions return this error if the verification - * calculations completed successfully, and the value to be verified - * was determined to be incorrect. - * - * If the value to verify has an invalid size, implementations may return - * either #PSA_ERROR_INVALID_ARGUMENT or #PSA_ERROR_INVALID_SIGNATURE. */ -#define PSA_ERROR_INVALID_SIGNATURE ((psa_status_t)-149) - -/** The decrypted padding is incorrect. - * - * \warning In some protocols, when decrypting data, it is essential that - * the behavior of the application does not depend on whether the padding - * is correct, down to precise timing. Applications should prefer - * protocols that use authenticated encryption rather than plain - * encryption. If the application must perform a decryption of - * unauthenticated data, the application writer should take care not - * to reveal whether the padding is invalid. - * - * Implementations should strive to make valid and invalid padding - * as close as possible to indistinguishable to an external observer. - * In particular, the timing of a decryption operation should not - * depend on the validity of the padding. */ -#define PSA_ERROR_INVALID_PADDING ((psa_status_t)-150) - -/** Return this error when there's insufficient data when attempting - * to read from a resource. */ -#define PSA_ERROR_INSUFFICIENT_DATA ((psa_status_t)-143) - -/** The key identifier is not valid. See also :ref:\`key-handles\`. - */ -#define PSA_ERROR_INVALID_HANDLE ((psa_status_t)-136) - -/** Stored data has been corrupted. - * - * This error indicates that some persistent storage has suffered corruption. - * It does not indicate the following situations, which have specific error - * codes: - * - * - A corruption of volatile memory - use #PSA_ERROR_CORRUPTION_DETECTED. - * - A communication error between the cryptoprocessor and its external - * storage - use #PSA_ERROR_COMMUNICATION_FAILURE. - * - When the storage is in a valid state but is full - use - * #PSA_ERROR_INSUFFICIENT_STORAGE. - * - When the storage fails for other reasons - use - * #PSA_ERROR_STORAGE_FAILURE. - * - When the stored data is not valid - use #PSA_ERROR_DATA_INVALID. - * - * \note A storage corruption does not indicate that any data that was - * previously read is invalid. However this previously read data might no - * longer be readable from storage. - * - * When a storage failure occurs, it is no longer possible to ensure the - * global integrity of the keystore. - */ -#define PSA_ERROR_DATA_CORRUPT ((psa_status_t)-152) - -/** Data read from storage is not valid for the implementation. - * - * This error indicates that some data read from storage does not have a valid - * format. It does not indicate the following situations, which have specific - * error codes: - * - * - When the storage or stored data is corrupted - use #PSA_ERROR_DATA_CORRUPT - * - When the storage fails for other reasons - use #PSA_ERROR_STORAGE_FAILURE - * - An invalid argument to the API - use #PSA_ERROR_INVALID_ARGUMENT - * - * This error is typically a result of either storage corruption on a - * cleartext storage backend, or an attempt to read data that was - * written by an incompatible version of the library. - */ -#define PSA_ERROR_DATA_INVALID ((psa_status_t)-153) - -/** The function that returns this status is defined as interruptible and - * still has work to do, thus the user should call the function again with the - * same operation context until it either returns #PSA_SUCCESS or any other - * error. This is not an error per se, more a notification of status. - */ -#define PSA_OPERATION_INCOMPLETE ((psa_status_t)-248) - -/** Requested operation has been delayed until the slot will be no longer in use. - * - * This error indicates that the requested operation could not be performed - * at the time. It is returned from psa_close_key, psa_purge_key, and - * psa_destroy_key for a call with a slot that is still used by a different - * thread. It will be performed by the thread that stops using the key last. - */ -#define PSA_ERROR_DELAYED ((psa_status_t)-154) - -/* *INDENT-ON* */ -/**@}*/ - -/** \defgroup crypto_types Key and algorithm types - * @{ - */ - -/* Note that key type values, including ECC family and DH group values, are - * embedded in the persistent key store, as part of key metadata. As a - * consequence, they must not be changed (unless the storage format version - * changes). - */ - -/** An invalid key type value. - * - * Zero is not the encoding of any key type. - */ -#define PSA_KEY_TYPE_NONE ((psa_key_type_t) 0x0000) - -/** Vendor-defined key type flag. - * - * Key types defined by this standard will never have the - * #PSA_KEY_TYPE_VENDOR_FLAG bit set. Vendors who define additional key types - * must use an encoding with the #PSA_KEY_TYPE_VENDOR_FLAG bit set and should - * respect the bitwise structure used by standard encodings whenever practical. - */ -#define PSA_KEY_TYPE_VENDOR_FLAG ((psa_key_type_t) 0x8000) - -#define PSA_KEY_TYPE_CATEGORY_MASK ((psa_key_type_t) 0x7000) -#define PSA_KEY_TYPE_CATEGORY_RAW ((psa_key_type_t) 0x1000) -#define PSA_KEY_TYPE_CATEGORY_SYMMETRIC ((psa_key_type_t) 0x2000) -#define PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY ((psa_key_type_t) 0x4000) -#define PSA_KEY_TYPE_CATEGORY_KEY_PAIR ((psa_key_type_t) 0x7000) - -#define PSA_KEY_TYPE_CATEGORY_FLAG_PAIR ((psa_key_type_t) 0x3000) - -/** Whether a key type is vendor-defined. - * - * See also #PSA_KEY_TYPE_VENDOR_FLAG. - */ -#define PSA_KEY_TYPE_IS_VENDOR_DEFINED(type) \ - (((type) & PSA_KEY_TYPE_VENDOR_FLAG) != 0) - -/** Whether a key type is an unstructured array of bytes. - * - * This encompasses both symmetric keys and non-key data. - */ -#define PSA_KEY_TYPE_IS_UNSTRUCTURED(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_RAW || \ - ((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC) - -/** Whether a key type is asymmetric: either a key pair or a public key. */ -#define PSA_KEY_TYPE_IS_ASYMMETRIC(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK \ - & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) == \ - PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) -/** Whether a key type is the public part of a key pair. */ -#define PSA_KEY_TYPE_IS_PUBLIC_KEY(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) -/** Whether a key type is a key pair containing a private part and a public - * part. */ -#define PSA_KEY_TYPE_IS_KEY_PAIR(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_KEY_PAIR) -/** The key pair type corresponding to a public key type. - * - * You may also pass a key pair type as \p type, it will be left unchanged. - * - * \param type A public key type or key pair type. - * - * \return The corresponding key pair type. - * If \p type is not a public key or a key pair, - * the return value is undefined. - */ -#define PSA_KEY_TYPE_KEY_PAIR_OF_PUBLIC_KEY(type) \ - ((type) | PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) -/** The public key type corresponding to a key pair type. - * - * You may also pass a key pair type as \p type, it will be left unchanged. - * - * \param type A public key type or key pair type. - * - * \return The corresponding public key type. - * If \p type is not a public key or a key pair, - * the return value is undefined. - */ -#define PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) \ - ((type) & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) - -/** Raw data. - * - * A "key" of this type cannot be used for any cryptographic operation. - * Applications may use this type to store arbitrary data in the keystore. */ -#define PSA_KEY_TYPE_RAW_DATA ((psa_key_type_t) 0x1001) - -/** HMAC key. - * - * The key policy determines which underlying hash algorithm the key can be - * used for. - * - * HMAC keys should generally have the same size as the underlying hash. - * This size can be calculated with #PSA_HASH_LENGTH(\c alg) where - * \c alg is the HMAC algorithm or the underlying hash algorithm. */ -#define PSA_KEY_TYPE_HMAC ((psa_key_type_t) 0x1100) - -/** A secret for key derivation. - * - * This key type is for high-entropy secrets only. For low-entropy secrets, - * #PSA_KEY_TYPE_PASSWORD should be used instead. - * - * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_SECRET or - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input of key derivation algorithms. - * - * The key policy determines which key derivation algorithm the key - * can be used for. - */ -#define PSA_KEY_TYPE_DERIVE ((psa_key_type_t) 0x1200) - -/** A low-entropy secret for password hashing or key derivation. - * - * This key type is suitable for passwords and passphrases which are typically - * intended to be memorizable by humans, and have a low entropy relative to - * their size. It can be used for randomly generated or derived keys with - * maximum or near-maximum entropy, but #PSA_KEY_TYPE_DERIVE is more suitable - * for such keys. It is not suitable for passwords with extremely low entropy, - * such as numerical PINs. - * - * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_PASSWORD input of - * key derivation algorithms. Algorithms that accept such an input were - * designed to accept low-entropy secret and are known as password hashing or - * key stretching algorithms. - * - * These keys cannot be used as the #PSA_KEY_DERIVATION_INPUT_SECRET input of - * key derivation algorithms, as the algorithms that take such an input expect - * it to be high-entropy. - * - * The key policy determines which key derivation algorithm the key can be - * used for, among the permissible subset defined above. - */ -#define PSA_KEY_TYPE_PASSWORD ((psa_key_type_t) 0x1203) - -/** A secret value that can be used to verify a password hash. - * - * The key policy determines which key derivation algorithm the key - * can be used for, among the same permissible subset as for - * #PSA_KEY_TYPE_PASSWORD. - */ -#define PSA_KEY_TYPE_PASSWORD_HASH ((psa_key_type_t) 0x1205) - -/** A secret value that can be used in when computing a password hash. - * - * The key policy determines which key derivation algorithm the key - * can be used for, among the subset of algorithms that can use pepper. - */ -#define PSA_KEY_TYPE_PEPPER ((psa_key_type_t) 0x1206) - -/** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. - * - * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or - * 32 bytes (AES-256). - */ -#define PSA_KEY_TYPE_AES ((psa_key_type_t) 0x2400) - -/** Key for a cipher, AEAD or MAC algorithm based on the - * ARIA block cipher. */ -#define PSA_KEY_TYPE_ARIA ((psa_key_type_t) 0x2406) - -/** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). - * - * The size of the key can be 64 bits (single DES), 128 bits (2-key 3DES) or - * 192 bits (3-key 3DES). - * - * Note that single DES and 2-key 3DES are weak and strongly - * deprecated and should only be used to decrypt legacy data. 3-key 3DES - * is weak and deprecated and should only be used in legacy protocols. - */ -#define PSA_KEY_TYPE_DES ((psa_key_type_t) 0x2301) - -/** Key for a cipher, AEAD or MAC algorithm based on the - * Camellia block cipher. */ -#define PSA_KEY_TYPE_CAMELLIA ((psa_key_type_t) 0x2403) - -/** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. - * - * ChaCha20 and the ChaCha20_Poly1305 construction are defined in RFC 7539. - * - * \note For ChaCha20 and ChaCha20_Poly1305, Mbed TLS only supports - * 12-byte nonces. - * - * \note For ChaCha20, the initial counter value is 0. To encrypt or decrypt - * with the initial counter value 1, you can process and discard a - * 64-byte block before the real data. - */ -#define PSA_KEY_TYPE_CHACHA20 ((psa_key_type_t) 0x2004) - -/** RSA public key. - * - * The size of an RSA key is the bit size of the modulus. - */ -#define PSA_KEY_TYPE_RSA_PUBLIC_KEY ((psa_key_type_t) 0x4001) -/** RSA key pair (private and public key). - * - * The size of an RSA key is the bit size of the modulus. - */ -#define PSA_KEY_TYPE_RSA_KEY_PAIR ((psa_key_type_t) 0x7001) -/** Whether a key type is an RSA key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_RSA(type) \ - (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) - -#define PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4100) -#define PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((psa_key_type_t) 0x7100) -#define PSA_KEY_TYPE_ECC_CURVE_MASK ((psa_key_type_t) 0x00ff) -/** Elliptic curve key pair. - * - * The size of an elliptic curve key is the bit size associated with the curve, - * i.e. the bit size of *q* for a curve over a field *Fq*. - * See the documentation of `PSA_ECC_FAMILY_xxx` curve families for details. - * - * \param curve A value of type ::psa_ecc_family_t that - * identifies the ECC curve to be used. - */ -#define PSA_KEY_TYPE_ECC_KEY_PAIR(curve) \ - (PSA_KEY_TYPE_ECC_KEY_PAIR_BASE | (curve)) -/** Elliptic curve public key. - * - * The size of an elliptic curve public key is the same as the corresponding - * private key (see #PSA_KEY_TYPE_ECC_KEY_PAIR and the documentation of - * `PSA_ECC_FAMILY_xxx` curve families). - * - * \param curve A value of type ::psa_ecc_family_t that - * identifies the ECC curve to be used. - */ -#define PSA_KEY_TYPE_ECC_PUBLIC_KEY(curve) \ - (PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE | (curve)) - -/** Whether a key type is an elliptic curve key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_ECC(type) \ - ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ - ~PSA_KEY_TYPE_ECC_CURVE_MASK) == PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) -/** Whether a key type is an elliptic curve key pair. */ -#define PSA_KEY_TYPE_IS_ECC_KEY_PAIR(type) \ - (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ - PSA_KEY_TYPE_ECC_KEY_PAIR_BASE) -/** Whether a key type is an elliptic curve public key. */ -#define PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(type) \ - (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ - PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) - -/** Extract the curve from an elliptic curve key type. */ -#define PSA_KEY_TYPE_ECC_GET_FAMILY(type) \ - ((psa_ecc_family_t) (PSA_KEY_TYPE_IS_ECC(type) ? \ - ((type) & PSA_KEY_TYPE_ECC_CURVE_MASK) : \ - 0)) - -/** Check if the curve of given family is Weierstrass elliptic curve. */ -#define PSA_ECC_FAMILY_IS_WEIERSTRASS(family) ((family & 0xc0) == 0) - -/** SEC Koblitz curves over prime fields. - * - * This family comprises the following curves: - * secp192k1, secp224k1, secp256k1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECP_K1 ((psa_ecc_family_t) 0x17) - -/** SEC random curves over prime fields. - * - * This family comprises the following curves: - * secp192k1, secp224r1, secp256r1, secp384r1, secp521r1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECP_R1 ((psa_ecc_family_t) 0x12) -/* SECP160R2 (SEC2 v1, obsolete) */ -#define PSA_ECC_FAMILY_SECP_R2 ((psa_ecc_family_t) 0x1b) - -/** SEC Koblitz curves over binary fields. - * - * This family comprises the following curves: - * sect163k1, sect233k1, sect239k1, sect283k1, sect409k1, sect571k1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECT_K1 ((psa_ecc_family_t) 0x27) - -/** SEC random curves over binary fields. - * - * This family comprises the following curves: - * sect163r1, sect233r1, sect283r1, sect409r1, sect571r1. - * They are defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECT_R1 ((psa_ecc_family_t) 0x22) - -/** SEC additional random curves over binary fields. - * - * This family comprises the following curve: - * sect163r2. - * It is defined in _Standards for Efficient Cryptography_, - * _SEC 2: Recommended Elliptic Curve Domain Parameters_. - * https://www.secg.org/sec2-v2.pdf - */ -#define PSA_ECC_FAMILY_SECT_R2 ((psa_ecc_family_t) 0x2b) - -/** Brainpool P random curves. - * - * This family comprises the following curves: - * brainpoolP160r1, brainpoolP192r1, brainpoolP224r1, brainpoolP256r1, - * brainpoolP320r1, brainpoolP384r1, brainpoolP512r1. - * It is defined in RFC 5639. - */ -#define PSA_ECC_FAMILY_BRAINPOOL_P_R1 ((psa_ecc_family_t) 0x30) - -/** Curve25519 and Curve448. - * - * This family comprises the following Montgomery curves: - * - 255-bit: Bernstein et al., - * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. - * The algorithm #PSA_ALG_ECDH performs X25519 when used with this curve. - * - 448-bit: Hamburg, - * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. - * The algorithm #PSA_ALG_ECDH performs X448 when used with this curve. - */ -#define PSA_ECC_FAMILY_MONTGOMERY ((psa_ecc_family_t) 0x41) - -/** The twisted Edwards curves Ed25519 and Ed448. - * - * These curves are suitable for EdDSA (#PSA_ALG_PURE_EDDSA for both curves, - * #PSA_ALG_ED25519PH for the 255-bit curve, - * #PSA_ALG_ED448PH for the 448-bit curve). - * - * This family comprises the following twisted Edwards curves: - * - 255-bit: Edwards25519, the twisted Edwards curve birationally equivalent - * to Curve25519. - * Bernstein et al., _Twisted Edwards curves_, Africacrypt 2008. - * - 448-bit: Edwards448, the twisted Edwards curve birationally equivalent - * to Curve448. - * Hamburg, _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. - */ -#define PSA_ECC_FAMILY_TWISTED_EDWARDS ((psa_ecc_family_t) 0x42) - -#define PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4200) -#define PSA_KEY_TYPE_DH_KEY_PAIR_BASE ((psa_key_type_t) 0x7200) -#define PSA_KEY_TYPE_DH_GROUP_MASK ((psa_key_type_t) 0x00ff) -/** Diffie-Hellman key pair. - * - * \param group A value of type ::psa_dh_family_t that identifies the - * Diffie-Hellman group to be used. - */ -#define PSA_KEY_TYPE_DH_KEY_PAIR(group) \ - (PSA_KEY_TYPE_DH_KEY_PAIR_BASE | (group)) -/** Diffie-Hellman public key. - * - * \param group A value of type ::psa_dh_family_t that identifies the - * Diffie-Hellman group to be used. - */ -#define PSA_KEY_TYPE_DH_PUBLIC_KEY(group) \ - (PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE | (group)) - -/** Whether a key type is a Diffie-Hellman key (pair or public-only). */ -#define PSA_KEY_TYPE_IS_DH(type) \ - ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ - ~PSA_KEY_TYPE_DH_GROUP_MASK) == PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) -/** Whether a key type is a Diffie-Hellman key pair. */ -#define PSA_KEY_TYPE_IS_DH_KEY_PAIR(type) \ - (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ - PSA_KEY_TYPE_DH_KEY_PAIR_BASE) -/** Whether a key type is a Diffie-Hellman public key. */ -#define PSA_KEY_TYPE_IS_DH_PUBLIC_KEY(type) \ - (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ - PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) - -/** Extract the group from a Diffie-Hellman key type. */ -#define PSA_KEY_TYPE_DH_GET_FAMILY(type) \ - ((psa_dh_family_t) (PSA_KEY_TYPE_IS_DH(type) ? \ - ((type) & PSA_KEY_TYPE_DH_GROUP_MASK) : \ - 0)) - -/** Diffie-Hellman groups defined in RFC 7919 Appendix A. - * - * This family includes groups with the following key sizes (in bits): - * 2048, 3072, 4096, 6144, 8192. A given implementation may support - * all of these sizes or only a subset. - */ -#define PSA_DH_FAMILY_RFC7919 ((psa_dh_family_t) 0x03) - -#define PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) \ - (((type) >> 8) & 7) -/** The block size of a block cipher. - * - * \param type A cipher key type (value of type #psa_key_type_t). - * - * \return The block size for a block cipher, or 1 for a stream cipher. - * The return value is undefined if \p type is not a supported - * cipher key type. - * - * \note It is possible to build stream cipher algorithms on top of a block - * cipher, for example CTR mode (#PSA_ALG_CTR). - * This macro only takes the key type into account, so it cannot be - * used to determine the size of the data that #psa_cipher_update() - * might buffer for future processing in general. - * - * \note This macro returns a compile-time constant if its argument is one. - * - * \warning This macro may evaluate its argument multiple times. - */ -#define PSA_BLOCK_CIPHER_BLOCK_LENGTH(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ - 1u << PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) : \ - 0u) - -/* Note that algorithm values are embedded in the persistent key store, - * as part of key metadata. As a consequence, they must not be changed - * (unless the storage format version changes). - */ - -/** Vendor-defined algorithm flag. - * - * Algorithms defined by this standard will never have the #PSA_ALG_VENDOR_FLAG - * bit set. Vendors who define additional algorithms must use an encoding with - * the #PSA_ALG_VENDOR_FLAG bit set and should respect the bitwise structure - * used by standard encodings whenever practical. - */ -#define PSA_ALG_VENDOR_FLAG ((psa_algorithm_t) 0x80000000) - -#define PSA_ALG_CATEGORY_MASK ((psa_algorithm_t) 0x7f000000) -#define PSA_ALG_CATEGORY_HASH ((psa_algorithm_t) 0x02000000) -#define PSA_ALG_CATEGORY_MAC ((psa_algorithm_t) 0x03000000) -#define PSA_ALG_CATEGORY_CIPHER ((psa_algorithm_t) 0x04000000) -#define PSA_ALG_CATEGORY_AEAD ((psa_algorithm_t) 0x05000000) -#define PSA_ALG_CATEGORY_SIGN ((psa_algorithm_t) 0x06000000) -#define PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION ((psa_algorithm_t) 0x07000000) -#define PSA_ALG_CATEGORY_KEY_DERIVATION ((psa_algorithm_t) 0x08000000) -#define PSA_ALG_CATEGORY_KEY_AGREEMENT ((psa_algorithm_t) 0x09000000) - -/** Whether an algorithm is vendor-defined. - * - * See also #PSA_ALG_VENDOR_FLAG. - */ -#define PSA_ALG_IS_VENDOR_DEFINED(alg) \ - (((alg) & PSA_ALG_VENDOR_FLAG) != 0) - -/** Whether the specified algorithm is a hash algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a hash algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HASH(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_HASH) - -/** Whether the specified algorithm is a MAC algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a MAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_MAC(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_MAC) - -/** Whether the specified algorithm is a symmetric cipher algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a symmetric cipher algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_CIPHER(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_CIPHER) - -/** Whether the specified algorithm is an authenticated encryption - * with associated data (AEAD) algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an AEAD algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_AEAD(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_AEAD) - -/** Whether the specified algorithm is an asymmetric signature algorithm, - * also known as public-key signature algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an asymmetric signature algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_SIGN(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_SIGN) - -/** Whether the specified algorithm is an asymmetric encryption algorithm, - * also known as public-key encryption algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an asymmetric encryption algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_ASYMMETRIC_ENCRYPTION(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION) - -/** Whether the specified algorithm is a key agreement algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key agreement algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_KEY_AGREEMENT(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_AGREEMENT) - -/** Whether the specified algorithm is a key derivation algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key derivation algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_KEY_DERIVATION(alg) \ - (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_DERIVATION) - -/** Whether the specified algorithm is a key stretching / password hashing - * algorithm. - * - * A key stretching / password hashing algorithm is a key derivation algorithm - * that is suitable for use with a low-entropy secret such as a password. - * Equivalently, it's a key derivation algorithm that uses a - * #PSA_KEY_DERIVATION_INPUT_PASSWORD input step. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a key stretching / password hashing algorithm, 0 - * otherwise. This macro may return either 0 or 1 if \p alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_KEY_DERIVATION_STRETCHING(alg) \ - (PSA_ALG_IS_KEY_DERIVATION(alg) && \ - (alg) & PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG) - -/** An invalid algorithm identifier value. */ -/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ -#define PSA_ALG_NONE ((psa_algorithm_t)0) -/* *INDENT-ON* */ - -#define PSA_ALG_HASH_MASK ((psa_algorithm_t) 0x000000ff) -/** MD5 */ -#define PSA_ALG_MD5 ((psa_algorithm_t) 0x02000003) -/** PSA_ALG_RIPEMD160 */ -#define PSA_ALG_RIPEMD160 ((psa_algorithm_t) 0x02000004) -/** SHA1 */ -#define PSA_ALG_SHA_1 ((psa_algorithm_t) 0x02000005) -/** SHA2-224 */ -#define PSA_ALG_SHA_224 ((psa_algorithm_t) 0x02000008) -/** SHA2-256 */ -#define PSA_ALG_SHA_256 ((psa_algorithm_t) 0x02000009) -/** SHA2-384 */ -#define PSA_ALG_SHA_384 ((psa_algorithm_t) 0x0200000a) -/** SHA2-512 */ -#define PSA_ALG_SHA_512 ((psa_algorithm_t) 0x0200000b) -/** SHA2-512/224 */ -#define PSA_ALG_SHA_512_224 ((psa_algorithm_t) 0x0200000c) -/** SHA2-512/256 */ -#define PSA_ALG_SHA_512_256 ((psa_algorithm_t) 0x0200000d) -/** SHA3-224 */ -#define PSA_ALG_SHA3_224 ((psa_algorithm_t) 0x02000010) -/** SHA3-256 */ -#define PSA_ALG_SHA3_256 ((psa_algorithm_t) 0x02000011) -/** SHA3-384 */ -#define PSA_ALG_SHA3_384 ((psa_algorithm_t) 0x02000012) -/** SHA3-512 */ -#define PSA_ALG_SHA3_512 ((psa_algorithm_t) 0x02000013) -/** The first 512 bits (64 bytes) of the SHAKE256 output. - * - * This is the prehashing for Ed448ph (see #PSA_ALG_ED448PH). For other - * scenarios where a hash function based on SHA3/SHAKE is desired, SHA3-512 - * has the same output size and a (theoretically) higher security strength. - */ -#define PSA_ALG_SHAKE256_512 ((psa_algorithm_t) 0x02000015) - -/** In a hash-and-sign algorithm policy, allow any hash algorithm. - * - * This value may be used to form the algorithm usage field of a policy - * for a signature algorithm that is parametrized by a hash. The key - * may then be used to perform operations using the same signature - * algorithm parametrized with any supported hash. - * - * That is, suppose that `PSA_xxx_SIGNATURE` is one of the following macros: - * - #PSA_ALG_RSA_PKCS1V15_SIGN, #PSA_ALG_RSA_PSS, #PSA_ALG_RSA_PSS_ANY_SALT, - * - #PSA_ALG_ECDSA, #PSA_ALG_DETERMINISTIC_ECDSA. - * Then you may create and use a key as follows: - * - Set the key usage field using #PSA_ALG_ANY_HASH, for example: - * ``` - * psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); // or VERIFY - * psa_set_key_algorithm(&attributes, PSA_xxx_SIGNATURE(PSA_ALG_ANY_HASH)); - * ``` - * - Import or generate key material. - * - Call psa_sign_hash() or psa_verify_hash(), passing - * an algorithm built from `PSA_xxx_SIGNATURE` and a specific hash. Each - * call to sign or verify a message may use a different hash. - * ``` - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); - * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); - * ``` - * - * This value may not be used to build other algorithms that are - * parametrized over a hash. For any valid use of this macro to build - * an algorithm \c alg, #PSA_ALG_IS_HASH_AND_SIGN(\c alg) is true. - * - * This value may not be used to build an algorithm specification to - * perform an operation. It is only valid to build policies. - */ -#define PSA_ALG_ANY_HASH ((psa_algorithm_t) 0x020000ff) - -#define PSA_ALG_MAC_SUBCATEGORY_MASK ((psa_algorithm_t) 0x00c00000) -#define PSA_ALG_HMAC_BASE ((psa_algorithm_t) 0x03800000) -/** Macro to build an HMAC algorithm. - * - * For example, #PSA_ALG_HMAC(#PSA_ALG_SHA_256) is HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HMAC algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HMAC(hash_alg) \ - (PSA_ALG_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_HMAC_GET_HASH(hmac_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hmac_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is an HMAC algorithm. - * - * HMAC is a family of MAC algorithms that are based on a hash function. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an HMAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HMAC(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ - PSA_ALG_HMAC_BASE) - -/* In the encoding of a MAC algorithm, the bits corresponding to - * PSA_ALG_MAC_TRUNCATION_MASK encode the length to which the MAC is - * truncated. As an exception, the value 0 means the untruncated algorithm, - * whatever its length is. The length is encoded in 6 bits, so it can - * reach up to 63; the largest MAC is 64 bytes so its trivial truncation - * to full length is correctly encoded as 0 and any non-trivial truncation - * is correctly encoded as a value between 1 and 63. */ -#define PSA_ALG_MAC_TRUNCATION_MASK ((psa_algorithm_t) 0x003f0000) -#define PSA_MAC_TRUNCATION_OFFSET 16 - -/* In the encoding of a MAC algorithm, the bit corresponding to - * #PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm - * is a wildcard algorithm. A key with such wildcard algorithm as permitted - * algorithm policy can be used with any algorithm corresponding to the - * same base class and having a (potentially truncated) MAC length greater or - * equal than the one encoded in #PSA_ALG_MAC_TRUNCATION_MASK. */ -#define PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) - -/** Macro to build a truncated MAC algorithm. - * - * A truncated MAC algorithm is identical to the corresponding MAC - * algorithm except that the MAC value for the truncated algorithm - * consists of only the first \p mac_length bytes of the MAC value - * for the untruncated algorithm. - * - * \note This macro may allow constructing algorithm identifiers that - * are not valid, either because the specified length is larger - * than the untruncated MAC or because the specified length is - * smaller than permitted by the implementation. - * - * \note It is implementation-defined whether a truncated MAC that - * is truncated to the same length as the MAC of the untruncated - * algorithm is considered identical to the untruncated algorithm - * for policy comparison purposes. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). This may be a truncated or untruncated - * MAC algorithm. - * \param mac_length Desired length of the truncated MAC in bytes. - * This must be at most the full length of the MAC - * and must be at least an implementation-specified - * minimum. The implementation-specified minimum - * shall not be zero. - * - * \return The corresponding MAC algorithm with the specified - * length. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm or if \p mac_length is too small or - * too large for the specified MAC algorithm. - */ -#define PSA_ALG_TRUNCATED_MAC(mac_alg, mac_length) \ - (((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) | \ - ((mac_length) << PSA_MAC_TRUNCATION_OFFSET & PSA_ALG_MAC_TRUNCATION_MASK)) - -/** Macro to build the base MAC algorithm corresponding to a truncated - * MAC algorithm. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). This may be a truncated or untruncated - * MAC algorithm. - * - * \return The corresponding base MAC algorithm. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm. - */ -#define PSA_ALG_FULL_LENGTH_MAC(mac_alg) \ - ((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) - -/** Length to which a MAC algorithm is truncated. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). - * - * \return Length of the truncated MAC in bytes. - * \return 0 if \p mac_alg is a non-truncated MAC algorithm. - * \return Unspecified if \p mac_alg is not a supported - * MAC algorithm. - */ -#define PSA_MAC_TRUNCATED_LENGTH(mac_alg) \ - (((mac_alg) & PSA_ALG_MAC_TRUNCATION_MASK) >> PSA_MAC_TRUNCATION_OFFSET) - -/** Macro to build a MAC minimum-MAC-length wildcard algorithm. - * - * A minimum-MAC-length MAC wildcard algorithm permits all MAC algorithms - * sharing the same base algorithm, and where the (potentially truncated) MAC - * length of the specific algorithm is equal to or larger then the wildcard - * algorithm's minimum MAC length. - * - * \note When setting the minimum required MAC length to less than the - * smallest MAC length allowed by the base algorithm, this effectively - * becomes an 'any-MAC-length-allowed' policy for that base algorithm. - * - * \param mac_alg A MAC algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) - * is true). - * \param min_mac_length Desired minimum length of the message authentication - * code in bytes. This must be at most the untruncated - * length of the MAC and must be at least 1. - * - * \return The corresponding MAC wildcard algorithm with the - * specified minimum length. - * \return Unspecified if \p mac_alg is not a supported MAC - * algorithm or if \p min_mac_length is less than 1 or - * too large for the specified MAC algorithm. - */ -#define PSA_ALG_AT_LEAST_THIS_LENGTH_MAC(mac_alg, min_mac_length) \ - (PSA_ALG_TRUNCATED_MAC(mac_alg, min_mac_length) | \ - PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) - -#define PSA_ALG_CIPHER_MAC_BASE ((psa_algorithm_t) 0x03c00000) -/** The CBC-MAC construction over a block cipher - * - * \warning CBC-MAC is insecure in many cases. - * A more secure mode, such as #PSA_ALG_CMAC, is recommended. - */ -#define PSA_ALG_CBC_MAC ((psa_algorithm_t) 0x03c00100) -/** The CMAC construction over a block cipher */ -#define PSA_ALG_CMAC ((psa_algorithm_t) 0x03c00200) - -/** Whether the specified algorithm is a MAC algorithm based on a block cipher. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a MAC algorithm based on a block cipher, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ - PSA_ALG_CIPHER_MAC_BASE) - -#define PSA_ALG_CIPHER_STREAM_FLAG ((psa_algorithm_t) 0x00800000) -#define PSA_ALG_CIPHER_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) - -/** Whether the specified algorithm is a stream cipher. - * - * A stream cipher is a symmetric cipher that encrypts or decrypts messages - * by applying a bitwise-xor with a stream of bytes that is generated - * from a key. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a stream cipher algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier or if it is not a symmetric cipher algorithm. - */ -#define PSA_ALG_IS_STREAM_CIPHER(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_CIPHER_STREAM_FLAG)) == \ - (PSA_ALG_CATEGORY_CIPHER | PSA_ALG_CIPHER_STREAM_FLAG)) - -/** The stream cipher mode of a stream cipher algorithm. - * - * The underlying stream cipher is determined by the key type. - * - To use ChaCha20, use a key type of #PSA_KEY_TYPE_CHACHA20. - */ -#define PSA_ALG_STREAM_CIPHER ((psa_algorithm_t) 0x04800100) - -/** The CTR stream cipher mode. - * - * CTR is a stream cipher which is built from a block cipher. - * The underlying block cipher is determined by the key type. - * For example, to use AES-128-CTR, use this algorithm with - * a key of type #PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). - */ -#define PSA_ALG_CTR ((psa_algorithm_t) 0x04c01000) - -/** The CFB stream cipher mode. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_CFB ((psa_algorithm_t) 0x04c01100) - -/** The OFB stream cipher mode. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_OFB ((psa_algorithm_t) 0x04c01200) - -/** The XTS cipher mode. - * - * XTS is a cipher mode which is built from a block cipher. It requires at - * least one full block of input, but beyond this minimum the input - * does not need to be a whole number of blocks. - */ -#define PSA_ALG_XTS ((psa_algorithm_t) 0x0440ff00) - -/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. - * - * \warning ECB mode does not protect the confidentiality of the encrypted data - * except in extremely narrow circumstances. It is recommended that applications - * only use ECB if they need to construct an operating mode that the - * implementation does not provide. Implementations are encouraged to provide - * the modes that applications need in preference to supporting direct access - * to ECB. - * - * The underlying block cipher is determined by the key type. - * - * This symmetric cipher mode can only be used with messages whose lengths are a - * multiple of the block size of the chosen block cipher. - * - * ECB mode does not accept an initialization vector (IV). When using a - * multi-part cipher operation with this algorithm, psa_cipher_generate_iv() - * and psa_cipher_set_iv() must not be called. - */ -#define PSA_ALG_ECB_NO_PADDING ((psa_algorithm_t) 0x04404400) - -/** The CBC block cipher chaining mode, with no padding. - * - * The underlying block cipher is determined by the key type. - * - * This symmetric cipher mode can only be used with messages whose lengths - * are whole number of blocks for the chosen block cipher. - */ -#define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t) 0x04404000) - -/** The CBC block cipher chaining mode with PKCS#7 padding. - * - * The underlying block cipher is determined by the key type. - * - * This is the padding method defined by PKCS#7 (RFC 2315) §10.3. - */ -#define PSA_ALG_CBC_PKCS7 ((psa_algorithm_t) 0x04404100) - -#define PSA_ALG_AEAD_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) - -/** Whether the specified algorithm is an AEAD mode on a block cipher. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is an AEAD algorithm which is an AEAD mode based on - * a block cipher, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) \ - (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) == \ - (PSA_ALG_CATEGORY_AEAD | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) - -/** The CCM authenticated encryption algorithm. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_CCM ((psa_algorithm_t) 0x05500100) - -/** The CCM* cipher mode without authentication. - * - * This is CCM* as specified in IEEE 802.15.4 §7, with a tag length of 0. - * For CCM* with a nonzero tag length, use the AEAD algorithm #PSA_ALG_CCM. - * - * The underlying block cipher is determined by the key type. - * - * Currently only 13-byte long IV's are supported. - */ -#define PSA_ALG_CCM_STAR_NO_TAG ((psa_algorithm_t) 0x04c01300) - -/** The GCM authenticated encryption algorithm. - * - * The underlying block cipher is determined by the key type. - */ -#define PSA_ALG_GCM ((psa_algorithm_t) 0x05500200) - -/** The Chacha20-Poly1305 AEAD algorithm. - * - * The ChaCha20_Poly1305 construction is defined in RFC 7539. - * - * Implementations must support 12-byte nonces, may support 8-byte nonces, - * and should reject other sizes. - * - * Implementations must support 16-byte tags and should reject other sizes. - */ -#define PSA_ALG_CHACHA20_POLY1305 ((psa_algorithm_t) 0x05100500) - -/* In the encoding of an AEAD algorithm, the bits corresponding to - * PSA_ALG_AEAD_TAG_LENGTH_MASK encode the length of the AEAD tag. - * The constants for default lengths follow this encoding. - */ -#define PSA_ALG_AEAD_TAG_LENGTH_MASK ((psa_algorithm_t) 0x003f0000) -#define PSA_AEAD_TAG_LENGTH_OFFSET 16 - -/* In the encoding of an AEAD algorithm, the bit corresponding to - * #PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm - * is a wildcard algorithm. A key with such wildcard algorithm as permitted - * algorithm policy can be used with any algorithm corresponding to the - * same base class and having a tag length greater than or equal to the one - * encoded in #PSA_ALG_AEAD_TAG_LENGTH_MASK. */ -#define PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) - -/** Macro to build a shortened AEAD algorithm. - * - * A shortened AEAD algorithm is similar to the corresponding AEAD - * algorithm, but has an authentication tag that consists of fewer bytes. - * Depending on the algorithm, the tag length may affect the calculation - * of the ciphertext. - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) - * is true). - * \param tag_length Desired length of the authentication tag in bytes. - * - * \return The corresponding AEAD algorithm with the specified - * length. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm or if \p tag_length is not valid - * for the specified AEAD algorithm. - */ -#define PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, tag_length) \ - (((aead_alg) & ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | \ - PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG)) | \ - ((tag_length) << PSA_AEAD_TAG_LENGTH_OFFSET & \ - PSA_ALG_AEAD_TAG_LENGTH_MASK)) - -/** Retrieve the tag length of a specified AEAD algorithm - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) - * is true). - * - * \return The tag length specified by the input algorithm. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm. - */ -#define PSA_ALG_AEAD_GET_TAG_LENGTH(aead_alg) \ - (((aead_alg) & PSA_ALG_AEAD_TAG_LENGTH_MASK) >> \ - PSA_AEAD_TAG_LENGTH_OFFSET) - -/** Calculate the corresponding AEAD algorithm with the default tag length. - * - * \param aead_alg An AEAD algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p aead_alg) is true). - * - * \return The corresponding AEAD algorithm with the default - * tag length for that algorithm. - */ -#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(aead_alg) \ - ( \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CCM) \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_GCM) \ - PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CHACHA20_POLY1305) \ - 0) -#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, ref) \ - PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, 0) == \ - PSA_ALG_AEAD_WITH_SHORTENED_TAG(ref, 0) ? \ - ref : - -/** Macro to build an AEAD minimum-tag-length wildcard algorithm. - * - * A minimum-tag-length AEAD wildcard algorithm permits all AEAD algorithms - * sharing the same base algorithm, and where the tag length of the specific - * algorithm is equal to or larger then the minimum tag length specified by the - * wildcard algorithm. - * - * \note When setting the minimum required tag length to less than the - * smallest tag length allowed by the base algorithm, this effectively - * becomes an 'any-tag-length-allowed' policy for that base algorithm. - * - * \param aead_alg An AEAD algorithm identifier (value of type - * #psa_algorithm_t such that - * #PSA_ALG_IS_AEAD(\p aead_alg) is true). - * \param min_tag_length Desired minimum length of the authentication tag in - * bytes. This must be at least 1 and at most the largest - * allowed tag length of the algorithm. - * - * \return The corresponding AEAD wildcard algorithm with the - * specified minimum length. - * \return Unspecified if \p aead_alg is not a supported - * AEAD algorithm or if \p min_tag_length is less than 1 - * or too large for the specified AEAD algorithm. - */ -#define PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG(aead_alg, min_tag_length) \ - (PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, min_tag_length) | \ - PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) - -#define PSA_ALG_RSA_PKCS1V15_SIGN_BASE ((psa_algorithm_t) 0x06000200) -/** RSA PKCS#1 v1.5 signature with hashing. - * - * This is the signature scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSASSA-PKCS1-v1_5. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PKCS#1 v1.5 signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PKCS1V15_SIGN(hash_alg) \ - (PSA_ALG_RSA_PKCS1V15_SIGN_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Raw PKCS#1 v1.5 signature. - * - * The input to this algorithm is the DigestInfo structure used by - * RFC 8017 (PKCS#1: RSA Cryptography Specifications), §9.2 - * steps 3–6. - */ -#define PSA_ALG_RSA_PKCS1V15_SIGN_RAW PSA_ALG_RSA_PKCS1V15_SIGN_BASE -#define PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PKCS1V15_SIGN_BASE) - -#define PSA_ALG_RSA_PSS_BASE ((psa_algorithm_t) 0x06000300) -#define PSA_ALG_RSA_PSS_ANY_SALT_BASE ((psa_algorithm_t) 0x06001300) -/** RSA PSS signature with hashing. - * - * This is the signature scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSASSA-PSS, with the message generation function MGF1, and with - * a salt length equal to the length of the hash, or the largest - * possible salt length for the algorithm and key size if that is - * smaller than the hash length. The specified hash algorithm is - * used to hash the input message, to create the salted hash, and - * for the mask generation. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PSS signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PSS(hash_alg) \ - (PSA_ALG_RSA_PSS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** RSA PSS signature with hashing with relaxed verification. - * - * This algorithm has the same behavior as #PSA_ALG_RSA_PSS when signing, - * but allows an arbitrary salt length (including \c 0) when verifying a - * signature. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding RSA PSS signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_PSS_ANY_SALT(hash_alg) \ - (PSA_ALG_RSA_PSS_ANY_SALT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is RSA PSS with standard salt. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_BASE) - -/** Whether the specified algorithm is RSA PSS with any salt. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS_ANY_SALT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_ANY_SALT_BASE) - -/** Whether the specified algorithm is RSA PSS. - * - * This includes any of the RSA PSS algorithm variants, regardless of the - * constraints on salt length. - * - * \param alg An algorithm value or an algorithm policy wildcard. - * - * \return 1 if \p alg is of the form - * #PSA_ALG_RSA_PSS(\c hash_alg) or - * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), - * where \c hash_alg is a hash algorithm or - * #PSA_ALG_ANY_HASH. 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not - * a supported algorithm identifier or policy. - */ -#define PSA_ALG_IS_RSA_PSS(alg) \ - (PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) || \ - PSA_ALG_IS_RSA_PSS_ANY_SALT(alg)) - -#define PSA_ALG_ECDSA_BASE ((psa_algorithm_t) 0x06000600) -/** ECDSA signature with hashing. - * - * This is the ECDSA signature scheme defined by ANSI X9.62, - * with a random per-message secret number (*k*). - * - * The representation of the signature as a byte string consists of - * the concatenation of the signature values *r* and *s*. Each of - * *r* and *s* is encoded as an *N*-octet string, where *N* is the length - * of the base point of the curve in octets. Each value is represented - * in big-endian order (most significant octet first). - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding ECDSA signature algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_ECDSA(hash_alg) \ - (PSA_ALG_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** ECDSA signature without hashing. - * - * This is the same signature scheme as #PSA_ALG_ECDSA(), but - * without specifying a hash algorithm. This algorithm may only be - * used to sign or verify a sequence of bytes that should be an - * already-calculated hash. Note that the input is padded with - * zeros on the left or truncated on the left as required to fit - * the curve size. - */ -#define PSA_ALG_ECDSA_ANY PSA_ALG_ECDSA_BASE -#define PSA_ALG_DETERMINISTIC_ECDSA_BASE ((psa_algorithm_t) 0x06000700) -/** Deterministic ECDSA signature with hashing. - * - * This is the deterministic ECDSA signature scheme defined by RFC 6979. - * - * The representation of a signature is the same as with #PSA_ALG_ECDSA(). - * - * Note that when this algorithm is used for verification, signatures - * made with randomized ECDSA (#PSA_ALG_ECDSA(\p hash_alg)) with the - * same private key are accepted. In other words, - * #PSA_ALG_DETERMINISTIC_ECDSA(\p hash_alg) differs from - * #PSA_ALG_ECDSA(\p hash_alg) only for signature, not for verification. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * This includes #PSA_ALG_ANY_HASH - * when specifying the algorithm in a usage policy. - * - * \return The corresponding deterministic ECDSA signature - * algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_DETERMINISTIC_ECDSA(hash_alg) \ - (PSA_ALG_DETERMINISTIC_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t) 0x00000100) -#define PSA_ALG_IS_ECDSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_ECDSA_DETERMINISTIC_FLAG) == \ - PSA_ALG_ECDSA_BASE) -#define PSA_ALG_ECDSA_IS_DETERMINISTIC(alg) \ - (((alg) & PSA_ALG_ECDSA_DETERMINISTIC_FLAG) != 0) -#define PSA_ALG_IS_DETERMINISTIC_ECDSA(alg) \ - (PSA_ALG_IS_ECDSA(alg) && PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) -#define PSA_ALG_IS_RANDOMIZED_ECDSA(alg) \ - (PSA_ALG_IS_ECDSA(alg) && !PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) - -/** Edwards-curve digital signature algorithm without prehashing (PureEdDSA), - * using standard parameters. - * - * Contexts are not supported in the current version of this specification - * because there is no suitable signature interface that can take the - * context as a parameter. A future version of this specification may add - * suitable functions and extend this algorithm to support contexts. - * - * PureEdDSA requires an elliptic curve key on a twisted Edwards curve. - * In this specification, the following curves are supported: - * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 255-bit: Ed25519 as specified - * in RFC 8032. - * The curve is Edwards25519. - * The hash function used internally is SHA-512. - * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 448-bit: Ed448 as specified - * in RFC 8032. - * The curve is Edwards448. - * The hash function used internally is the first 114 bytes of the - * SHAKE256 output. - * - * This algorithm can be used with psa_sign_message() and - * psa_verify_message(). Since there is no prehashing, it cannot be used - * with psa_sign_hash() or psa_verify_hash(). - * - * The signature format is the concatenation of R and S as defined by - * RFC 8032 §5.1.6 and §5.2.6 (a 64-byte string for Ed25519, a 114-byte - * string for Ed448). - */ -#define PSA_ALG_PURE_EDDSA ((psa_algorithm_t) 0x06000800) - -#define PSA_ALG_HASH_EDDSA_BASE ((psa_algorithm_t) 0x06000900) -#define PSA_ALG_IS_HASH_EDDSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HASH_EDDSA_BASE) - -/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), - * using SHA-512 and the Edwards25519 curve. - * - * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. - * - * This algorithm is Ed25519 as specified in RFC 8032. - * The curve is Edwards25519. - * The prehash is SHA-512. - * The hash function used internally is SHA-512. - * - * This is a hash-and-sign algorithm: to calculate a signature, - * you can either: - * - call psa_sign_message() on the message; - * - or calculate the SHA-512 hash of the message - * with psa_hash_compute() - * or with a multi-part hash operation started with psa_hash_setup(), - * using the hash algorithm #PSA_ALG_SHA_512, - * then sign the calculated hash with psa_sign_hash(). - * Verifying a signature is similar, using psa_verify_message() or - * psa_verify_hash() instead of the signature function. - */ -#define PSA_ALG_ED25519PH \ - (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHA_512 & PSA_ALG_HASH_MASK)) - -/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), - * using SHAKE256 and the Edwards448 curve. - * - * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. - * - * This algorithm is Ed448 as specified in RFC 8032. - * The curve is Edwards448. - * The prehash is the first 64 bytes of the SHAKE256 output. - * The hash function used internally is the first 114 bytes of the - * SHAKE256 output. - * - * This is a hash-and-sign algorithm: to calculate a signature, - * you can either: - * - call psa_sign_message() on the message; - * - or calculate the first 64 bytes of the SHAKE256 output of the message - * with psa_hash_compute() - * or with a multi-part hash operation started with psa_hash_setup(), - * using the hash algorithm #PSA_ALG_SHAKE256_512, - * then sign the calculated hash with psa_sign_hash(). - * Verifying a signature is similar, using psa_verify_message() or - * psa_verify_hash() instead of the signature function. - */ -#define PSA_ALG_ED448PH \ - (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHAKE256_512 & PSA_ALG_HASH_MASK)) - -/* Default definition, to be overridden if the library is extended with - * more hash-and-sign algorithms that we want to keep out of this header - * file. */ -#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) 0 - -/** Whether the specified algorithm is a signature algorithm that can be used - * with psa_sign_hash() and psa_verify_hash(). - * - * This encompasses all strict hash-and-sign algorithms categorized by - * PSA_ALG_IS_HASH_AND_SIGN(), as well as algorithms that follow the - * paradigm more loosely: - * - #PSA_ALG_RSA_PKCS1V15_SIGN_RAW (expects its input to be an encoded hash) - * - #PSA_ALG_ECDSA_ANY (doesn't specify what kind of hash the input is) - * - * \param alg An algorithm identifier (value of type psa_algorithm_t). - * - * \return 1 if alg is a signature algorithm that can be used to sign a - * hash. 0 if alg is a signature algorithm that can only be used - * to sign a message. 0 if alg is not a signature algorithm. - * This macro can return either 0 or 1 if alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_SIGN_HASH(alg) \ - (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || \ - PSA_ALG_IS_ECDSA(alg) || PSA_ALG_IS_HASH_EDDSA(alg) || \ - PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg)) - -/** Whether the specified algorithm is a signature algorithm that can be used - * with psa_sign_message() and psa_verify_message(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if alg is a signature algorithm that can be used to sign a - * message. 0 if \p alg is a signature algorithm that can only be used - * to sign an already-calculated hash. 0 if \p alg is not a signature - * algorithm. This macro can return either 0 or 1 if \p alg is not a - * supported algorithm identifier. - */ -#define PSA_ALG_IS_SIGN_MESSAGE(alg) \ - (PSA_ALG_IS_SIGN_HASH(alg) || (alg) == PSA_ALG_PURE_EDDSA) - -/** Whether the specified algorithm is a hash-and-sign algorithm. - * - * Hash-and-sign algorithms are asymmetric (public-key) signature algorithms - * structured in two parts: first the calculation of a hash in a way that - * does not depend on the key, then the calculation of a signature from the - * hash value and the key. Hash-and-sign algorithms encode the hash - * used for the hashing step, and you can call #PSA_ALG_SIGN_GET_HASH - * to extract this algorithm. - * - * Thus, for a hash-and-sign algorithm, - * `psa_sign_message(key, alg, input, ...)` is equivalent to - * ``` - * psa_hash_compute(PSA_ALG_SIGN_GET_HASH(alg), input, ..., hash, ...); - * psa_sign_hash(key, alg, hash, ..., signature, ...); - * ``` - * Most usefully, separating the hash from the signature allows the hash - * to be calculated in multiple steps with psa_hash_setup(), psa_hash_update() - * and psa_hash_finish(). Likewise psa_verify_message() is equivalent to - * calculating the hash and then calling psa_verify_hash(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a hash-and-sign algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_HASH_AND_SIGN(alg) \ - (PSA_ALG_IS_SIGN_HASH(alg) && \ - ((alg) & PSA_ALG_HASH_MASK) != 0) - -/** Get the hash used by a hash-and-sign signature algorithm. - * - * A hash-and-sign algorithm is a signature algorithm which is - * composed of two phases: first a hashing phase which does not use - * the key and produces a hash of the input message, then a signing - * phase which only uses the hash and the key and not the message - * itself. - * - * \param alg A signature algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_SIGN(\p alg) is true). - * - * \return The underlying hash algorithm if \p alg is a hash-and-sign - * algorithm. - * \return 0 if \p alg is a signature algorithm that does not - * follow the hash-and-sign structure. - * \return Unspecified if \p alg is not a signature algorithm or - * if it is not supported by the implementation. - */ -#define PSA_ALG_SIGN_GET_HASH(alg) \ - (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ - ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ - 0) - -/** RSA PKCS#1 v1.5 encryption. - */ -#define PSA_ALG_RSA_PKCS1V15_CRYPT ((psa_algorithm_t) 0x07000200) - -#define PSA_ALG_RSA_OAEP_BASE ((psa_algorithm_t) 0x07000300) -/** RSA OAEP encryption. - * - * This is the encryption scheme defined by RFC 8017 - * (PKCS#1: RSA Cryptography Specifications) under the name - * RSAES-OAEP, with the message generation function MGF1. - * - * \param hash_alg The hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true) to use - * for MGF1. - * - * \return The corresponding RSA OAEP encryption algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_RSA_OAEP(hash_alg) \ - (PSA_ALG_RSA_OAEP_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_IS_RSA_OAEP(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_OAEP_BASE) -#define PSA_ALG_RSA_OAEP_GET_HASH(alg) \ - (PSA_ALG_IS_RSA_OAEP(alg) ? \ - ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ - 0) - -#define PSA_ALG_HKDF_BASE ((psa_algorithm_t) 0x08000100) -/** Macro to build an HKDF algorithm. - * - * For example, `PSA_ALG_HKDF(PSA_ALG_SHA_256)` is HKDF using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt used in the "extract" step. - * It is optional; if omitted, the derivation uses an empty salt. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key used in the "extract" step. - * - #PSA_KEY_DERIVATION_INPUT_INFO is the info string used in the "expand" step. - * You must pass #PSA_KEY_DERIVATION_INPUT_SALT before #PSA_KEY_DERIVATION_INPUT_SECRET. - * You may pass #PSA_KEY_DERIVATION_INPUT_INFO at any time after steup and before - * starting to generate output. - * - * \warning HKDF processes the salt as follows: first hash it with hash_alg - * if the salt is longer than the block size of the hash algorithm; then - * pad with null bytes up to the block size. As a result, it is possible - * for distinct salt inputs to result in the same outputs. To ensure - * unique outputs, it is recommended to use a fixed length for salt values. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF(hash_alg) \ - (PSA_ALG_HKDF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF algorithm. - * - * HKDF is a family of key derivation algorithms that are based on a hash - * function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE) -#define PSA_ALG_HKDF_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_HKDF_EXTRACT_BASE ((psa_algorithm_t) 0x08000400) -/** Macro to build an HKDF-Extract algorithm. - * - * For example, `PSA_ALG_HKDF_EXTRACT(PSA_ALG_SHA_256)` is - * HKDF-Extract using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - PSA_KEY_DERIVATION_INPUT_SALT is the salt. - * - PSA_KEY_DERIVATION_INPUT_SECRET is the input keying material used in the - * "extract" step. - * The inputs are mandatory and must be passed in the order above. - * Each input may only be passed once. - * - * \warning HKDF-Extract is not meant to be used on its own. PSA_ALG_HKDF - * should be used instead if possible. PSA_ALG_HKDF_EXTRACT is provided - * as a separate algorithm for the sake of protocols that use it as a - * building block. It may also be a slight performance optimization - * in applications that use HKDF with the same salt and key but many - * different info strings. - * - * \warning HKDF processes the salt as follows: first hash it with hash_alg - * if the salt is longer than the block size of the hash algorithm; then - * pad with null bytes up to the block size. As a result, it is possible - * for distinct salt inputs to result in the same outputs. To ensure - * unique outputs, it is recommended to use a fixed length for salt values. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF-Extract algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF_EXTRACT(hash_alg) \ - (PSA_ALG_HKDF_EXTRACT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF-Extract algorithm. - * - * HKDF-Extract is a family of key derivation algorithms that are based - * on a hash function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF-Extract algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF_EXTRACT(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE) - -#define PSA_ALG_HKDF_EXPAND_BASE ((psa_algorithm_t) 0x08000500) -/** Macro to build an HKDF-Expand algorithm. - * - * For example, `PSA_ALG_HKDF_EXPAND(PSA_ALG_SHA_256)` is - * HKDF-Expand using HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs: - * - PSA_KEY_DERIVATION_INPUT_SECRET is the pseudorandom key (PRK). - * - PSA_KEY_DERIVATION_INPUT_INFO is the info string. - * - * The inputs are mandatory and must be passed in the order above. - * Each input may only be passed once. - * - * \warning HKDF-Expand is not meant to be used on its own. `PSA_ALG_HKDF` - * should be used instead if possible. `PSA_ALG_HKDF_EXPAND` is provided as - * a separate algorithm for the sake of protocols that use it as a building - * block. It may also be a slight performance optimization in applications - * that use HKDF with the same salt and key but many different info strings. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding HKDF-Expand algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_HKDF_EXPAND(hash_alg) \ - (PSA_ALG_HKDF_EXPAND_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -/** Whether the specified algorithm is an HKDF-Expand algorithm. - * - * HKDF-Expand is a family of key derivation algorithms that are based - * on a hash function and the HMAC construction. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an HKDF-Expand algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_HKDF_EXPAND(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) - -/** Whether the specified algorithm is an HKDF or HKDF-Extract or - * HKDF-Expand algorithm. - * - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is any HKDF type algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_ANY_HKDF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE || \ - ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE || \ - ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) - -#define PSA_ALG_TLS12_PRF_BASE ((psa_algorithm_t) 0x08000200) -/** Macro to build a TLS-1.2 PRF algorithm. - * - * TLS 1.2 uses a custom pseudorandom function (PRF) for key schedule, - * specified in Section 5 of RFC 5246. It is based on HMAC and can be - * used with either SHA-256 or SHA-384. - * - * This key derivation algorithm uses the following inputs, which must be - * passed in the order given here: - * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. - * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. - * - * For the application to TLS-1.2 key expansion, the seed is the - * concatenation of ServerHello.Random + ClientHello.Random, - * and the label is "key expansion". - * - * For example, `PSA_ALG_TLS12_PRF(PSA_ALG_SHA_256)` represents the - * TLS 1.2 PRF using HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding TLS-1.2 PRF algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_TLS12_PRF(hash_alg) \ - (PSA_ALG_TLS12_PRF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a TLS-1.2 PRF algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a TLS-1.2 PRF algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_TLS12_PRF(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PRF_BASE) -#define PSA_ALG_TLS12_PRF_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -#define PSA_ALG_TLS12_PSK_TO_MS_BASE ((psa_algorithm_t) 0x08000300) -/** Macro to build a TLS-1.2 PSK-to-MasterSecret algorithm. - * - * In a pure-PSK handshake in TLS 1.2, the master secret is derived - * from the PreSharedKey (PSK) through the application of padding - * (RFC 4279, Section 2) and the TLS-1.2 PRF (RFC 5246, Section 5). - * The latter is based on HMAC and can be used with either SHA-256 - * or SHA-384. - * - * This key derivation algorithm uses the following inputs, which must be - * passed in the order given here: - * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. - * - #PSA_KEY_DERIVATION_INPUT_OTHER_SECRET is the other secret for the - * computation of the premaster secret. This input is optional; - * if omitted, it defaults to a string of null bytes with the same length - * as the secret (PSK) input. - * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. - * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. - * - * For the application to TLS-1.2, the seed (which is - * forwarded to the TLS-1.2 PRF) is the concatenation of the - * ClientHello.Random + ServerHello.Random, - * the label is "master secret" or "extended master secret" and - * the other secret depends on the key exchange specified in the cipher suite: - * - for a plain PSK cipher suite (RFC 4279, Section 2), omit - * PSA_KEY_DERIVATION_INPUT_OTHER_SECRET - * - for a DHE-PSK (RFC 4279, Section 3) or ECDHE-PSK cipher suite - * (RFC 5489, Section 2), the other secret should be the output of the - * PSA_ALG_FFDH or PSA_ALG_ECDH key agreement performed with the peer. - * The recommended way to pass this input is to use a key derivation - * algorithm constructed as - * PSA_ALG_KEY_AGREEMENT(ka_alg, PSA_ALG_TLS12_PSK_TO_MS(hash_alg)) - * and to call psa_key_derivation_key_agreement(). Alternatively, - * this input may be an output of `psa_raw_key_agreement()` passed with - * psa_key_derivation_input_bytes(), or an equivalent input passed with - * psa_key_derivation_input_bytes() or psa_key_derivation_input_key(). - * - for a RSA-PSK cipher suite (RFC 4279, Section 4), the other secret - * should be the 48-byte client challenge (the PreMasterSecret of - * (RFC 5246, Section 7.4.7.1)) concatenation of the TLS version and - * a 46-byte random string chosen by the client. On the server, this is - * typically an output of psa_asymmetric_decrypt() using - * PSA_ALG_RSA_PKCS1V15_CRYPT, passed to the key derivation operation - * with `psa_key_derivation_input_bytes()`. - * - * For example, `PSA_ALG_TLS12_PSK_TO_MS(PSA_ALG_SHA_256)` represents the - * TLS-1.2 PSK to MasterSecret derivation PRF using HMAC-SHA-256. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding TLS-1.2 PSK to MS algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_TLS12_PSK_TO_MS(hash_alg) \ - (PSA_ALG_TLS12_PSK_TO_MS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a TLS-1.2 PSK to MS algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a TLS-1.2 PSK to MS algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_TLS12_PSK_TO_MS(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PSK_TO_MS_BASE) -#define PSA_ALG_TLS12_PSK_TO_MS_GET_HASH(hkdf_alg) \ - (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) - -/* The TLS 1.2 ECJPAKE-to-PMS KDF. It takes the shared secret K (an EC point - * in case of EC J-PAKE) and calculates SHA256(K.X) that the rest of TLS 1.2 - * will use to derive the session secret, as defined by step 2 of - * https://datatracker.ietf.org/doc/html/draft-cragie-tls-ecjpake-01#section-8.7. - * Uses PSA_ALG_SHA_256. - * This function takes a single input: - * #PSA_KEY_DERIVATION_INPUT_SECRET is the shared secret K from EC J-PAKE. - * The only supported curve is secp256r1 (the 256-bit curve in - * #PSA_ECC_FAMILY_SECP_R1), so the input must be exactly 65 bytes. - * The output has to be read as a single chunk of 32 bytes, defined as - * PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE. - */ -#define PSA_ALG_TLS12_ECJPAKE_TO_PMS ((psa_algorithm_t) 0x08000609) - -/* This flag indicates whether the key derivation algorithm is suitable for - * use on low-entropy secrets such as password - these algorithms are also - * known as key stretching or password hashing schemes. These are also the - * algorithms that accepts inputs of type #PSA_KEY_DERIVATION_INPUT_PASSWORD. - * - * Those algorithms cannot be combined with a key agreement algorithm. - */ -#define PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG ((psa_algorithm_t) 0x00800000) - -#define PSA_ALG_PBKDF2_HMAC_BASE ((psa_algorithm_t) 0x08800100) -/** Macro to build a PBKDF2-HMAC password hashing / key stretching algorithm. - * - * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). - * This macro specifies the PBKDF2 algorithm constructed using a PRF based on - * HMAC with the specified hash. - * For example, `PSA_ALG_PBKDF2_HMAC(PSA_ALG_SHA_256)` specifies PBKDF2 - * using the PRF HMAC-SHA-256. - * - * This key derivation algorithm uses the following inputs, which must be - * provided in the following order: - * - #PSA_KEY_DERIVATION_INPUT_COST is the iteration count. - * This input step must be used exactly once. - * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt. - * This input step must be used one or more times; if used several times, the - * inputs will be concatenated. This can be used to build the final salt - * from multiple sources, both public and secret (also known as pepper). - * - #PSA_KEY_DERIVATION_INPUT_PASSWORD is the password to be hashed. - * This input step must be used exactly once. - * - * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_HASH(\p hash_alg) is true). - * - * \return The corresponding PBKDF2-HMAC-XXX algorithm. - * \return Unspecified if \p hash_alg is not a supported - * hash algorithm. - */ -#define PSA_ALG_PBKDF2_HMAC(hash_alg) \ - (PSA_ALG_PBKDF2_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) - -/** Whether the specified algorithm is a PBKDF2-HMAC algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a PBKDF2-HMAC algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key derivation algorithm identifier. - */ -#define PSA_ALG_IS_PBKDF2_HMAC(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_PBKDF2_HMAC_BASE) -#define PSA_ALG_PBKDF2_HMAC_GET_HASH(pbkdf2_alg) \ - (PSA_ALG_CATEGORY_HASH | ((pbkdf2_alg) & PSA_ALG_HASH_MASK)) -/** The PBKDF2-AES-CMAC-PRF-128 password hashing / key stretching algorithm. - * - * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). - * This macro specifies the PBKDF2 algorithm constructed using the - * AES-CMAC-PRF-128 PRF specified by RFC 4615. - * - * This key derivation algorithm uses the same inputs as - * #PSA_ALG_PBKDF2_HMAC() with the same constraints. - */ -#define PSA_ALG_PBKDF2_AES_CMAC_PRF_128 ((psa_algorithm_t) 0x08800200) - -#define PSA_ALG_IS_PBKDF2(kdf_alg) \ - (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg) || \ - ((kdf_alg) == PSA_ALG_PBKDF2_AES_CMAC_PRF_128)) - -#define PSA_ALG_KEY_DERIVATION_MASK ((psa_algorithm_t) 0xfe00ffff) -#define PSA_ALG_KEY_AGREEMENT_MASK ((psa_algorithm_t) 0xffff0000) - -/** Macro to build a combined algorithm that chains a key agreement with - * a key derivation. - * - * \param ka_alg A key agreement algorithm (\c PSA_ALG_XXX value such - * that #PSA_ALG_IS_KEY_AGREEMENT(\p ka_alg) is true). - * \param kdf_alg A key derivation algorithm (\c PSA_ALG_XXX value such - * that #PSA_ALG_IS_KEY_DERIVATION(\p kdf_alg) is true). - * - * \return The corresponding key agreement and derivation - * algorithm. - * \return Unspecified if \p ka_alg is not a supported - * key agreement algorithm or \p kdf_alg is not a - * supported key derivation algorithm. - */ -#define PSA_ALG_KEY_AGREEMENT(ka_alg, kdf_alg) \ - ((ka_alg) | (kdf_alg)) - -#define PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) \ - (((alg) & PSA_ALG_KEY_DERIVATION_MASK) | PSA_ALG_CATEGORY_KEY_DERIVATION) - -#define PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) \ - (((alg) & PSA_ALG_KEY_AGREEMENT_MASK) | PSA_ALG_CATEGORY_KEY_AGREEMENT) - -/** Whether the specified algorithm is a raw key agreement algorithm. - * - * A raw key agreement algorithm is one that does not specify - * a key derivation function. - * Usually, raw key agreement algorithms are constructed directly with - * a \c PSA_ALG_xxx macro while non-raw key agreement algorithms are - * constructed with #PSA_ALG_KEY_AGREEMENT(). - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \p alg is a raw key agreement algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \p alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_RAW_KEY_AGREEMENT(alg) \ - (PSA_ALG_IS_KEY_AGREEMENT(alg) && \ - PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) == PSA_ALG_CATEGORY_KEY_DERIVATION) - -#define PSA_ALG_IS_KEY_DERIVATION_OR_AGREEMENT(alg) \ - ((PSA_ALG_IS_KEY_DERIVATION(alg) || PSA_ALG_IS_KEY_AGREEMENT(alg))) - -/** The finite-field Diffie-Hellman (DH) key agreement algorithm. - * - * The shared secret produced by key agreement is - * `g^{ab}` in big-endian format. - * It is `ceiling(m / 8)` bytes long where `m` is the size of the prime `p` - * in bits. - */ -#define PSA_ALG_FFDH ((psa_algorithm_t) 0x09010000) - -/** Whether the specified algorithm is a finite field Diffie-Hellman algorithm. - * - * This includes the raw finite field Diffie-Hellman algorithm as well as - * finite-field Diffie-Hellman followed by any supporter key derivation - * algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a finite field Diffie-Hellman algorithm, 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key agreement algorithm identifier. - */ -#define PSA_ALG_IS_FFDH(alg) \ - (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_FFDH) - -/** The elliptic curve Diffie-Hellman (ECDH) key agreement algorithm. - * - * The shared secret produced by key agreement is the x-coordinate of - * the shared secret point. It is always `ceiling(m / 8)` bytes long where - * `m` is the bit size associated with the curve, i.e. the bit size of the - * order of the curve's coordinate field. When `m` is not a multiple of 8, - * the byte containing the most significant bit of the shared secret - * is padded with zero bits. The byte order is either little-endian - * or big-endian depending on the curve type. - * - * - For Montgomery curves (curve types `PSA_ECC_FAMILY_CURVEXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in little-endian byte order. - * The bit size is 448 for Curve448 and 255 for Curve25519. - * - For Weierstrass curves over prime fields (curve types - * `PSA_ECC_FAMILY_SECPXXX` and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in big-endian byte order. - * The bit size is `m = ceiling(log_2(p))` for the field `F_p`. - * - For Weierstrass curves over binary fields (curve types - * `PSA_ECC_FAMILY_SECTXXX`), - * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` - * in big-endian byte order. - * The bit size is `m` for the field `F_{2^m}`. - */ -#define PSA_ALG_ECDH ((psa_algorithm_t) 0x09020000) - -/** Whether the specified algorithm is an elliptic curve Diffie-Hellman - * algorithm. - * - * This includes the raw elliptic curve Diffie-Hellman algorithm as well as - * elliptic curve Diffie-Hellman followed by any supporter key derivation - * algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is an elliptic curve Diffie-Hellman algorithm, - * 0 otherwise. - * This macro may return either 0 or 1 if \c alg is not a supported - * key agreement algorithm identifier. - */ -#define PSA_ALG_IS_ECDH(alg) \ - (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_ECDH) - -/** Whether the specified algorithm encoding is a wildcard. - * - * Wildcard values may only be used to set the usage algorithm field in - * a policy, not to perform an operation. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return 1 if \c alg is a wildcard algorithm encoding. - * \return 0 if \c alg is a non-wildcard algorithm encoding (suitable for - * an operation). - * \return This macro may return either 0 or 1 if \c alg is not a supported - * algorithm identifier. - */ -#define PSA_ALG_IS_WILDCARD(alg) \ - (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ - PSA_ALG_SIGN_GET_HASH(alg) == PSA_ALG_ANY_HASH : \ - PSA_ALG_IS_MAC(alg) ? \ - (alg & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ - PSA_ALG_IS_AEAD(alg) ? \ - (alg & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ - (alg) == PSA_ALG_ANY_HASH) - -/** Get the hash used by a composite algorithm. - * - * \param alg An algorithm identifier (value of type #psa_algorithm_t). - * - * \return The underlying hash algorithm if alg is a composite algorithm that - * uses a hash algorithm. - * - * \return \c 0 if alg is not a composite algorithm that uses a hash. - */ -#define PSA_ALG_GET_HASH(alg) \ - (((alg) & 0x000000ff) == 0 ? ((psa_algorithm_t) 0) : 0x02000000 | ((alg) & 0x000000ff)) - -/**@}*/ - -/** \defgroup key_lifetimes Key lifetimes - * @{ - */ - -/* Note that location and persistence level values are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** The default lifetime for volatile keys. - * - * A volatile key only exists as long as the identifier to it is not destroyed. - * The key material is guaranteed to be erased on a power reset. - * - * A key with this lifetime is typically stored in the RAM area of the - * PSA Crypto subsystem. However this is an implementation choice. - * If an implementation stores data about the key in a non-volatile memory, - * it must release all the resources associated with the key and erase the - * key material if the calling application terminates. - */ -#define PSA_KEY_LIFETIME_VOLATILE ((psa_key_lifetime_t) 0x00000000) - -/** The default lifetime for persistent keys. - * - * A persistent key remains in storage until it is explicitly destroyed or - * until the corresponding storage area is wiped. This specification does - * not define any mechanism to wipe a storage area, but integrations may - * provide their own mechanism (for example to perform a factory reset, - * to prepare for device refurbishment, or to uninstall an application). - * - * This lifetime value is the default storage area for the calling - * application. Integrations of Mbed TLS may support other persistent lifetimes. - * See ::psa_key_lifetime_t for more information. - */ -#define PSA_KEY_LIFETIME_PERSISTENT ((psa_key_lifetime_t) 0x00000001) - -/** The persistence level of volatile keys. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_VOLATILE ((psa_key_persistence_t) 0x00) - -/** The default persistence level for persistent keys. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_DEFAULT ((psa_key_persistence_t) 0x01) - -/** A persistence level indicating that a key is never destroyed. - * - * See ::psa_key_persistence_t for more information. - */ -#define PSA_KEY_PERSISTENCE_READ_ONLY ((psa_key_persistence_t) 0xff) - -#define PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) \ - ((psa_key_persistence_t) ((lifetime) & 0x000000ff)) - -#define PSA_KEY_LIFETIME_GET_LOCATION(lifetime) \ - ((psa_key_location_t) ((lifetime) >> 8)) - -/** Whether a key lifetime indicates that the key is volatile. - * - * A volatile key is automatically destroyed by the implementation when - * the application instance terminates. In particular, a volatile key - * is automatically destroyed on a power reset of the device. - * - * A key that is not volatile is persistent. Persistent keys are - * preserved until the application explicitly destroys them or until an - * implementation-specific device management event occurs (for example, - * a factory reset). - * - * \param lifetime The lifetime value to query (value of type - * ::psa_key_lifetime_t). - * - * \return \c 1 if the key is volatile, otherwise \c 0. - */ -#define PSA_KEY_LIFETIME_IS_VOLATILE(lifetime) \ - (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ - PSA_KEY_PERSISTENCE_VOLATILE) - -/** Whether a key lifetime indicates that the key is read-only. - * - * Read-only keys cannot be created or destroyed through the PSA Crypto API. - * They must be created through platform-specific means that bypass the API. - * - * Some platforms may offer ways to destroy read-only keys. For example, - * consider a platform with multiple levels of privilege, where a - * low-privilege application can use a key but is not allowed to destroy - * it, and the platform exposes the key to the application with a read-only - * lifetime. High-privilege code can destroy the key even though the - * application sees the key as read-only. - * - * \param lifetime The lifetime value to query (value of type - * ::psa_key_lifetime_t). - * - * \return \c 1 if the key is read-only, otherwise \c 0. - */ -#define PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime) \ - (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ - PSA_KEY_PERSISTENCE_READ_ONLY) - -/** Construct a lifetime from a persistence level and a location. - * - * \param persistence The persistence level - * (value of type ::psa_key_persistence_t). - * \param location The location indicator - * (value of type ::psa_key_location_t). - * - * \return The constructed lifetime value. - */ -#define PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location) \ - ((location) << 8 | (persistence)) - -/** The local storage area for persistent keys. - * - * This storage area is available on all systems that can store persistent - * keys without delegating the storage to a third-party cryptoprocessor. - * - * See ::psa_key_location_t for more information. - */ -#define PSA_KEY_LOCATION_LOCAL_STORAGE ((psa_key_location_t) 0x000000) - -#define PSA_KEY_LOCATION_VENDOR_FLAG ((psa_key_location_t) 0x800000) - -/* Note that key identifier values are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** The null key identifier. - */ -/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ -#define PSA_KEY_ID_NULL ((psa_key_id_t)0) -/* *INDENT-ON* */ -/** The minimum value for a key identifier chosen by the application. - */ -#define PSA_KEY_ID_USER_MIN ((psa_key_id_t) 0x00000001) -/** The maximum value for a key identifier chosen by the application. - */ -#define PSA_KEY_ID_USER_MAX ((psa_key_id_t) 0x3fffffff) -/** The minimum value for a key identifier chosen by the implementation. - */ -#define PSA_KEY_ID_VENDOR_MIN ((psa_key_id_t) 0x40000000) -/** The maximum value for a key identifier chosen by the implementation. - */ -#define PSA_KEY_ID_VENDOR_MAX ((psa_key_id_t) 0x7fffffff) - - -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - -#define MBEDTLS_SVC_KEY_ID_INIT ((psa_key_id_t) 0) -#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) (id) -#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) (0) - -/** Utility to initialize a key identifier at runtime. - * - * \param unused Unused parameter. - * \param key_id Identifier of the key. - */ -static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( - unsigned int unused, psa_key_id_t key_id) -{ - (void) unused; - - return key_id; -} - -/** Compare two key identifiers. - * - * \param id1 First key identifier. - * \param id2 Second key identifier. - * - * \return Non-zero if the two key identifier are equal, zero otherwise. - */ -static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, - mbedtls_svc_key_id_t id2) -{ - return id1 == id2; -} - -/** Check whether a key identifier is null. - * - * \param key Key identifier. - * - * \return Non-zero if the key identifier is null, zero otherwise. - */ -static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) -{ - return key == 0; -} - -#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -#define MBEDTLS_SVC_KEY_ID_INIT ((mbedtls_svc_key_id_t){ 0, 0 }) -#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) ((id).MBEDTLS_PRIVATE(key_id)) -#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) ((id).MBEDTLS_PRIVATE(owner)) - -/** Utility to initialize a key identifier at runtime. - * - * \param owner_id Identifier of the key owner. - * \param key_id Identifier of the key. - */ -static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( - mbedtls_key_owner_id_t owner_id, psa_key_id_t key_id) -{ - return (mbedtls_svc_key_id_t){ .MBEDTLS_PRIVATE(key_id) = key_id, - .MBEDTLS_PRIVATE(owner) = owner_id }; -} - -/** Compare two key identifiers. - * - * \param id1 First key identifier. - * \param id2 Second key identifier. - * - * \return Non-zero if the two key identifier are equal, zero otherwise. - */ -static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, - mbedtls_svc_key_id_t id2) -{ - return (id1.MBEDTLS_PRIVATE(key_id) == id2.MBEDTLS_PRIVATE(key_id)) && - mbedtls_key_owner_id_equal(id1.MBEDTLS_PRIVATE(owner), id2.MBEDTLS_PRIVATE(owner)); -} - -/** Check whether a key identifier is null. - * - * \param key Key identifier. - * - * \return Non-zero if the key identifier is null, zero otherwise. - */ -static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) -{ - return key.MBEDTLS_PRIVATE(key_id) == 0; -} - -#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ - -/**@}*/ - -/** \defgroup policy Key policies - * @{ - */ - -/* Note that key usage flags are embedded in the - * persistent key store, as part of key metadata. As a consequence, they - * must not be changed (unless the storage format version changes). - */ - -/** Whether the key may be exported. - * - * A public key or the public part of a key pair may always be exported - * regardless of the value of this permission flag. - * - * If a key does not have export permission, implementations shall not - * allow the key to be exported in plain form from the cryptoprocessor, - * whether through psa_export_key() or through a proprietary interface. - * The key may however be exportable in a wrapped form, i.e. in a form - * where it is encrypted by another key. - */ -#define PSA_KEY_USAGE_EXPORT ((psa_key_usage_t) 0x00000001) - -/** Whether the key may be copied. - * - * This flag allows the use of psa_copy_key() to make a copy of the key - * with the same policy or a more restrictive policy. - * - * For lifetimes for which the key is located in a secure element which - * enforce the non-exportability of keys, copying a key outside the secure - * element also requires the usage flag #PSA_KEY_USAGE_EXPORT. - * Copying the key inside the secure element is permitted with just - * #PSA_KEY_USAGE_COPY if the secure element supports it. - * For keys with the lifetime #PSA_KEY_LIFETIME_VOLATILE or - * #PSA_KEY_LIFETIME_PERSISTENT, the usage flag #PSA_KEY_USAGE_COPY - * is sufficient to permit the copy. - */ -#define PSA_KEY_USAGE_COPY ((psa_key_usage_t) 0x00000002) - -/** Whether the key may be used to encrypt a message. - * - * This flag allows the key to be used for a symmetric encryption operation, - * for an AEAD encryption-and-authentication operation, - * or for an asymmetric encryption operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_ENCRYPT ((psa_key_usage_t) 0x00000100) - -/** Whether the key may be used to decrypt a message. - * - * This flag allows the key to be used for a symmetric decryption operation, - * for an AEAD decryption-and-verification operation, - * or for an asymmetric decryption operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_DECRYPT ((psa_key_usage_t) 0x00000200) - -/** Whether the key may be used to sign a message. - * - * This flag allows the key to be used for a MAC calculation operation or for - * an asymmetric message signature operation, if otherwise permitted by the - * key’s type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_SIGN_MESSAGE ((psa_key_usage_t) 0x00000400) - -/** Whether the key may be used to verify a message. - * - * This flag allows the key to be used for a MAC verification operation or for - * an asymmetric message signature verification operation, if otherwise - * permitted by the key’s type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_VERIFY_MESSAGE ((psa_key_usage_t) 0x00000800) - -/** Whether the key may be used to sign a message. - * - * This flag allows the key to be used for a MAC calculation operation - * or for an asymmetric signature operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the private key. - */ -#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t) 0x00001000) - -/** Whether the key may be used to verify a message signature. - * - * This flag allows the key to be used for a MAC verification operation - * or for an asymmetric signature verification operation, - * if otherwise permitted by the key's type and policy. - * - * For a key pair, this concerns the public key. - */ -#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t) 0x00002000) - -/** Whether the key may be used to derive other keys or produce a password - * hash. - * - * This flag allows the key to be used for a key derivation operation or for - * a key agreement operation, if otherwise permitted by the key's type and - * policy. - * - * If this flag is present on all keys used in calls to - * psa_key_derivation_input_key() for a key derivation operation, then it - * permits calling psa_key_derivation_output_bytes() or - * psa_key_derivation_output_key() at the end of the operation. - */ -#define PSA_KEY_USAGE_DERIVE ((psa_key_usage_t) 0x00004000) - -/** Whether the key may be used to verify the result of a key derivation, - * including password hashing. - * - * This flag allows the key to be used: - * - * This flag allows the key to be used in a key derivation operation, if - * otherwise permitted by the key's type and policy. - * - * If this flag is present on all keys used in calls to - * psa_key_derivation_input_key() for a key derivation operation, then it - * permits calling psa_key_derivation_verify_bytes() or - * psa_key_derivation_verify_key() at the end of the operation. - */ -#define PSA_KEY_USAGE_VERIFY_DERIVATION ((psa_key_usage_t) 0x00008000) - -/**@}*/ - -/** \defgroup derivation Key derivation - * @{ - */ - -/* Key input steps are not embedded in the persistent storage, so you can - * change them if needed: it's only an ABI change. */ - -/** A secret input for key derivation. - * - * This should be a key of type #PSA_KEY_TYPE_DERIVE - * (passed to psa_key_derivation_input_key()) - * or the shared secret resulting from a key agreement - * (obtained via psa_key_derivation_key_agreement()). - * - * The secret can also be a direct input (passed to - * key_derivation_input_bytes()). In this case, the derivation operation - * may not be used to derive keys: the operation will only allow - * psa_key_derivation_output_bytes(), - * psa_key_derivation_verify_bytes(), or - * psa_key_derivation_verify_key(), but not - * psa_key_derivation_output_key(). - */ -#define PSA_KEY_DERIVATION_INPUT_SECRET ((psa_key_derivation_step_t) 0x0101) - -/** A low-entropy secret input for password hashing / key stretching. - * - * This is usually a key of type #PSA_KEY_TYPE_PASSWORD (passed to - * psa_key_derivation_input_key()) or a direct input (passed to - * psa_key_derivation_input_bytes()) that is a password or passphrase. It can - * also be high-entropy secret such as a key of type #PSA_KEY_TYPE_DERIVE or - * the shared secret resulting from a key agreement. - * - * The secret can also be a direct input (passed to - * key_derivation_input_bytes()). In this case, the derivation operation - * may not be used to derive keys: the operation will only allow - * psa_key_derivation_output_bytes(), - * psa_key_derivation_verify_bytes(), or - * psa_key_derivation_verify_key(), but not - * psa_key_derivation_output_key(). - */ -#define PSA_KEY_DERIVATION_INPUT_PASSWORD ((psa_key_derivation_step_t) 0x0102) - -/** A high-entropy additional secret input for key derivation. - * - * This is typically the shared secret resulting from a key agreement obtained - * via `psa_key_derivation_key_agreement()`. It may alternatively be a key of - * type `PSA_KEY_TYPE_DERIVE` passed to `psa_key_derivation_input_key()`, or - * a direct input passed to `psa_key_derivation_input_bytes()`. - */ -#define PSA_KEY_DERIVATION_INPUT_OTHER_SECRET \ - ((psa_key_derivation_step_t) 0x0103) - -/** A label for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_LABEL ((psa_key_derivation_step_t) 0x0201) - -/** A salt for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA or - * #PSA_KEY_TYPE_PEPPER. - */ -#define PSA_KEY_DERIVATION_INPUT_SALT ((psa_key_derivation_step_t) 0x0202) - -/** An information string for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_INFO ((psa_key_derivation_step_t) 0x0203) - -/** A seed for key derivation. - * - * This should be a direct input. - * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. - */ -#define PSA_KEY_DERIVATION_INPUT_SEED ((psa_key_derivation_step_t) 0x0204) - -/** A cost parameter for password hashing / key stretching. - * - * This must be a direct input, passed to psa_key_derivation_input_integer(). - */ -#define PSA_KEY_DERIVATION_INPUT_COST ((psa_key_derivation_step_t) 0x0205) - -/**@}*/ - -/** \defgroup helper_macros Helper macros - * @{ - */ - -/* Helper macros */ - -/** Check if two AEAD algorithm identifiers refer to the same AEAD algorithm - * regardless of the tag length they encode. - * - * \param aead_alg_1 An AEAD algorithm identifier. - * \param aead_alg_2 An AEAD algorithm identifier. - * - * \return 1 if both identifiers refer to the same AEAD algorithm, - * 0 otherwise. - * Unspecified if neither \p aead_alg_1 nor \p aead_alg_2 are - * a supported AEAD algorithm. - */ -#define MBEDTLS_PSA_ALG_AEAD_EQUAL(aead_alg_1, aead_alg_2) \ - (!(((aead_alg_1) ^ (aead_alg_2)) & \ - ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG))) - -/**@}*/ - -/**@}*/ - -/** \defgroup interruptible Interruptible operations - * @{ - */ - -/** Maximum value for use with \c psa_interruptible_set_max_ops() to determine - * the maximum number of ops allowed to be executed by an interruptible - * function in a single call. - */ -#define PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED UINT32_MAX - -/**@}*/ - -#endif /* PSA_CRYPTO_VALUES_H */ - -#endif /* SL_TRUSTZONE_NONSECURE */ +/** + * \file psa/crypto_values.h + * + * \brief PSA cryptography module: macros to build and analyze integer values. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. Drivers must include the appropriate driver + * header file. + * + * This file contains portable definitions of macros to build and analyze + * values of integral types that encode properties of cryptographic keys, + * designations of cryptographic algorithms, and error codes returned by + * the library. + * + * Note that many of the constants defined in this file are embedded in + * the persistent key store, as part of key metadata (including usage + * policies). As a consequence, they must not be changed (unless the storage + * format version changes). + * + * This header file only defines preprocessor macros. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(SL_TRUSTZONE_NONSECURE) + +/* The NonSecure app must use the crypto_values.h from the trusted-firmware-m repo. */ +#include "../../trusted-firmware-m/interface/include/psa/crypto_values.h" + +#else /* SL_TRUSTZONE_NONSECURE */ + +#ifndef PSA_CRYPTO_VALUES_H +#define PSA_CRYPTO_VALUES_H +#include "mbedtls/private_access.h" + +/** \defgroup error Error codes + * @{ + */ + +/* PSA error codes */ + +/* Error codes are standardized across PSA domains (framework, crypto, storage, + * etc.). Do not change the values in this section or even the expansions + * of each macro: it must be possible to `#include` both this header + * and some other PSA component's headers in the same C source, + * which will lead to duplicate definitions of the `PSA_SUCCESS` and + * `PSA_ERROR_xxx` macros, which is ok if and only if the macros expand + * to the same sequence of tokens. + * + * If you must add a new + * value, check with the Arm PSA framework group to pick one that other + * domains aren't already using. */ + +/* Tell uncrustify not to touch the constant definitions, otherwise + * it might change the spacing to something that is not PSA-compliant + * (e.g. adding a space after casts). + * + * *INDENT-OFF* + */ + +/** The action was completed successfully. */ +#define PSA_SUCCESS ((psa_status_t)0) + +/** An error occurred that does not correspond to any defined + * failure cause. + * + * Implementations may use this error code if none of the other standard + * error codes are applicable. */ +#define PSA_ERROR_GENERIC_ERROR ((psa_status_t)-132) + +/** The requested operation or a parameter is not supported + * by this implementation. + * + * Implementations should return this error code when an enumeration + * parameter such as a key type, algorithm, etc. is not recognized. + * If a combination of parameters is recognized and identified as + * not valid, return #PSA_ERROR_INVALID_ARGUMENT instead. */ +#define PSA_ERROR_NOT_SUPPORTED ((psa_status_t)-134) + +/** The requested action is denied by a policy. + * + * Implementations should return this error code when the parameters + * are recognized as valid and supported, and a policy explicitly + * denies the requested operation. + * + * If a subset of the parameters of a function call identify a + * forbidden operation, and another subset of the parameters are + * not valid or not supported, it is unspecified whether the function + * returns #PSA_ERROR_NOT_PERMITTED, #PSA_ERROR_NOT_SUPPORTED or + * #PSA_ERROR_INVALID_ARGUMENT. */ +#define PSA_ERROR_NOT_PERMITTED ((psa_status_t)-133) + +/** An output buffer is too small. + * + * Applications can call the \c PSA_xxx_SIZE macro listed in the function + * description to determine a sufficient buffer size. + * + * Implementations should preferably return this error code only + * in cases when performing the operation with a larger output + * buffer would succeed. However implementations may return this + * error if a function has invalid or unsupported parameters in addition + * to the parameters that determine the necessary output buffer size. */ +#define PSA_ERROR_BUFFER_TOO_SMALL ((psa_status_t)-138) + +/** Asking for an item that already exists + * + * Implementations should return this error, when attempting + * to write an item (like a key) that already exists. */ +#define PSA_ERROR_ALREADY_EXISTS ((psa_status_t)-139) + +/** Asking for an item that doesn't exist + * + * Implementations should return this error, if a requested item (like + * a key) does not exist. */ +#define PSA_ERROR_DOES_NOT_EXIST ((psa_status_t)-140) + +/** The requested action cannot be performed in the current state. + * + * Multipart operations return this error when one of the + * functions is called out of sequence. Refer to the function + * descriptions for permitted sequencing of functions. + * + * Implementations shall not return this error code to indicate + * that a key either exists or not, + * but shall instead return #PSA_ERROR_ALREADY_EXISTS or #PSA_ERROR_DOES_NOT_EXIST + * as applicable. + * + * Implementations shall not return this error code to indicate that a + * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE + * instead. */ +#define PSA_ERROR_BAD_STATE ((psa_status_t)-137) + +/** The parameters passed to the function are invalid. + * + * Implementations may return this error any time a parameter or + * combination of parameters are recognized as invalid. + * + * Implementations shall not return this error code to indicate that a + * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE + * instead. + */ +#define PSA_ERROR_INVALID_ARGUMENT ((psa_status_t)-135) + +/** There is not enough runtime memory. + * + * If the action is carried out across multiple security realms, this + * error can refer to available memory in any of the security realms. */ +#define PSA_ERROR_INSUFFICIENT_MEMORY ((psa_status_t)-141) + +/** There is not enough persistent storage. + * + * Functions that modify the key storage return this error code if + * there is insufficient storage space on the host media. In addition, + * many functions that do not otherwise access storage may return this + * error code if the implementation requires a mandatory log entry for + * the requested action and the log storage space is full. */ +#define PSA_ERROR_INSUFFICIENT_STORAGE ((psa_status_t)-142) + +/** There was a communication failure inside the implementation. + * + * This can indicate a communication failure between the application + * and an external cryptoprocessor or between the cryptoprocessor and + * an external volatile or persistent memory. A communication failure + * may be transient or permanent depending on the cause. + * + * \warning If a function returns this error, it is undetermined + * whether the requested action has completed or not. Implementations + * should return #PSA_SUCCESS on successful completion whenever + * possible, however functions may return #PSA_ERROR_COMMUNICATION_FAILURE + * if the requested action was completed successfully in an external + * cryptoprocessor but there was a breakdown of communication before + * the cryptoprocessor could report the status to the application. + */ +#define PSA_ERROR_COMMUNICATION_FAILURE ((psa_status_t)-145) + +/** There was a storage failure that may have led to data loss. + * + * This error indicates that some persistent storage is corrupted. + * It should not be used for a corruption of volatile memory + * (use #PSA_ERROR_CORRUPTION_DETECTED), for a communication error + * between the cryptoprocessor and its external storage (use + * #PSA_ERROR_COMMUNICATION_FAILURE), or when the storage is + * in a valid state but is full (use #PSA_ERROR_INSUFFICIENT_STORAGE). + * + * Note that a storage failure does not indicate that any data that was + * previously read is invalid. However this previously read data may no + * longer be readable from storage. + * + * When a storage failure occurs, it is no longer possible to ensure + * the global integrity of the keystore. Depending on the global + * integrity guarantees offered by the implementation, access to other + * data may or may not fail even if the data is still readable but + * its integrity cannot be guaranteed. + * + * Implementations should only use this error code to report a + * permanent storage corruption. However application writers should + * keep in mind that transient errors while reading the storage may be + * reported using this error code. */ +#define PSA_ERROR_STORAGE_FAILURE ((psa_status_t)-146) + +/** A hardware failure was detected. + * + * A hardware failure may be transient or permanent depending on the + * cause. */ +#define PSA_ERROR_HARDWARE_FAILURE ((psa_status_t)-147) + +/** A tampering attempt was detected. + * + * If an application receives this error code, there is no guarantee + * that previously accessed or computed data was correct and remains + * confidential. Applications should not perform any security function + * and should enter a safe failure state. + * + * Implementations may return this error code if they detect an invalid + * state that cannot happen during normal operation and that indicates + * that the implementation's security guarantees no longer hold. Depending + * on the implementation architecture and on its security and safety goals, + * the implementation may forcibly terminate the application. + * + * This error code is intended as a last resort when a security breach + * is detected and it is unsure whether the keystore data is still + * protected. Implementations shall only return this error code + * to report an alarm from a tampering detector, to indicate that + * the confidentiality of stored data can no longer be guaranteed, + * or to indicate that the integrity of previously returned data is now + * considered compromised. Implementations shall not use this error code + * to indicate a hardware failure that merely makes it impossible to + * perform the requested operation (use #PSA_ERROR_COMMUNICATION_FAILURE, + * #PSA_ERROR_STORAGE_FAILURE, #PSA_ERROR_HARDWARE_FAILURE, + * #PSA_ERROR_INSUFFICIENT_ENTROPY or other applicable error code + * instead). + * + * This error indicates an attack against the application. Implementations + * shall not return this error code as a consequence of the behavior of + * the application itself. */ +#define PSA_ERROR_CORRUPTION_DETECTED ((psa_status_t)-151) + +/** There is not enough entropy to generate random data needed + * for the requested action. + * + * This error indicates a failure of a hardware random generator. + * Application writers should note that this error can be returned not + * only by functions whose purpose is to generate random data, such + * as key, IV or nonce generation, but also by functions that execute + * an algorithm with a randomized result, as well as functions that + * use randomization of intermediate computations as a countermeasure + * to certain attacks. + * + * Implementations should avoid returning this error after psa_crypto_init() + * has succeeded. Implementations should generate sufficient + * entropy during initialization and subsequently use a cryptographically + * secure pseudorandom generator (PRNG). However implementations may return + * this error at any time if a policy requires the PRNG to be reseeded + * during normal operation. */ +#define PSA_ERROR_INSUFFICIENT_ENTROPY ((psa_status_t)-148) + +/** The signature, MAC or hash is incorrect. + * + * Verification functions return this error if the verification + * calculations completed successfully, and the value to be verified + * was determined to be incorrect. + * + * If the value to verify has an invalid size, implementations may return + * either #PSA_ERROR_INVALID_ARGUMENT or #PSA_ERROR_INVALID_SIGNATURE. */ +#define PSA_ERROR_INVALID_SIGNATURE ((psa_status_t)-149) + +/** The decrypted padding is incorrect. + * + * \warning In some protocols, when decrypting data, it is essential that + * the behavior of the application does not depend on whether the padding + * is correct, down to precise timing. Applications should prefer + * protocols that use authenticated encryption rather than plain + * encryption. If the application must perform a decryption of + * unauthenticated data, the application writer should take care not + * to reveal whether the padding is invalid. + * + * Implementations should strive to make valid and invalid padding + * as close as possible to indistinguishable to an external observer. + * In particular, the timing of a decryption operation should not + * depend on the validity of the padding. */ +#define PSA_ERROR_INVALID_PADDING ((psa_status_t)-150) + +/** Return this error when there's insufficient data when attempting + * to read from a resource. */ +#define PSA_ERROR_INSUFFICIENT_DATA ((psa_status_t)-143) + +/** The key identifier is not valid. See also :ref:\`key-handles\`. + */ +#define PSA_ERROR_INVALID_HANDLE ((psa_status_t)-136) + +/** Stored data has been corrupted. + * + * This error indicates that some persistent storage has suffered corruption. + * It does not indicate the following situations, which have specific error + * codes: + * + * - A corruption of volatile memory - use #PSA_ERROR_CORRUPTION_DETECTED. + * - A communication error between the cryptoprocessor and its external + * storage - use #PSA_ERROR_COMMUNICATION_FAILURE. + * - When the storage is in a valid state but is full - use + * #PSA_ERROR_INSUFFICIENT_STORAGE. + * - When the storage fails for other reasons - use + * #PSA_ERROR_STORAGE_FAILURE. + * - When the stored data is not valid - use #PSA_ERROR_DATA_INVALID. + * + * \note A storage corruption does not indicate that any data that was + * previously read is invalid. However this previously read data might no + * longer be readable from storage. + * + * When a storage failure occurs, it is no longer possible to ensure the + * global integrity of the keystore. + */ +#define PSA_ERROR_DATA_CORRUPT ((psa_status_t)-152) + +/** Data read from storage is not valid for the implementation. + * + * This error indicates that some data read from storage does not have a valid + * format. It does not indicate the following situations, which have specific + * error codes: + * + * - When the storage or stored data is corrupted - use #PSA_ERROR_DATA_CORRUPT + * - When the storage fails for other reasons - use #PSA_ERROR_STORAGE_FAILURE + * - An invalid argument to the API - use #PSA_ERROR_INVALID_ARGUMENT + * + * This error is typically a result of either storage corruption on a + * cleartext storage backend, or an attempt to read data that was + * written by an incompatible version of the library. + */ +#define PSA_ERROR_DATA_INVALID ((psa_status_t)-153) + +/** The function that returns this status is defined as interruptible and + * still has work to do, thus the user should call the function again with the + * same operation context until it either returns #PSA_SUCCESS or any other + * error. This is not an error per se, more a notification of status. + */ +#define PSA_OPERATION_INCOMPLETE ((psa_status_t)-248) + +/** Requested operation has been delayed until the slot will be no longer in use. + * + * This error indicates that the requested operation could not be performed + * at the time. It is returned from psa_close_key, psa_purge_key, and + * psa_destroy_key for a call with a slot that is still used by a different + * thread. It will be performed by the thread that stops using the key last. + */ +#define PSA_ERROR_DELAYED ((psa_status_t)-154) + +/* *INDENT-ON* */ +/**@}*/ + +/** \defgroup crypto_types Key and algorithm types + * @{ + */ + +/* Note that key type values, including ECC family and DH group values, are + * embedded in the persistent key store, as part of key metadata. As a + * consequence, they must not be changed (unless the storage format version + * changes). + */ + +/** An invalid key type value. + * + * Zero is not the encoding of any key type. + */ +#define PSA_KEY_TYPE_NONE ((psa_key_type_t) 0x0000) + +/** Vendor-defined key type flag. + * + * Key types defined by this standard will never have the + * #PSA_KEY_TYPE_VENDOR_FLAG bit set. Vendors who define additional key types + * must use an encoding with the #PSA_KEY_TYPE_VENDOR_FLAG bit set and should + * respect the bitwise structure used by standard encodings whenever practical. + */ +#define PSA_KEY_TYPE_VENDOR_FLAG ((psa_key_type_t) 0x8000) + +#define PSA_KEY_TYPE_CATEGORY_MASK ((psa_key_type_t) 0x7000) +#define PSA_KEY_TYPE_CATEGORY_RAW ((psa_key_type_t) 0x1000) +#define PSA_KEY_TYPE_CATEGORY_SYMMETRIC ((psa_key_type_t) 0x2000) +#define PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY ((psa_key_type_t) 0x4000) +#define PSA_KEY_TYPE_CATEGORY_KEY_PAIR ((psa_key_type_t) 0x7000) + +#define PSA_KEY_TYPE_CATEGORY_FLAG_PAIR ((psa_key_type_t) 0x3000) + +/** Whether a key type is vendor-defined. + * + * See also #PSA_KEY_TYPE_VENDOR_FLAG. + */ +#define PSA_KEY_TYPE_IS_VENDOR_DEFINED(type) \ + (((type) & PSA_KEY_TYPE_VENDOR_FLAG) != 0) + +/** Whether a key type is an unstructured array of bytes. + * + * This encompasses both symmetric keys and non-key data. + */ +#define PSA_KEY_TYPE_IS_UNSTRUCTURED(type) \ + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_RAW || \ + ((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC) + +/** Whether a key type is asymmetric: either a key pair or a public key. */ +#define PSA_KEY_TYPE_IS_ASYMMETRIC(type) \ + (((type) & PSA_KEY_TYPE_CATEGORY_MASK \ + & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) == \ + PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) +/** Whether a key type is the public part of a key pair. */ +#define PSA_KEY_TYPE_IS_PUBLIC_KEY(type) \ + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY) +/** Whether a key type is a key pair containing a private part and a public + * part. */ +#define PSA_KEY_TYPE_IS_KEY_PAIR(type) \ + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_KEY_PAIR) +/** The key pair type corresponding to a public key type. + * + * You may also pass a key pair type as \p type, it will be left unchanged. + * + * \param type A public key type or key pair type. + * + * \return The corresponding key pair type. + * If \p type is not a public key or a key pair, + * the return value is undefined. + */ +#define PSA_KEY_TYPE_KEY_PAIR_OF_PUBLIC_KEY(type) \ + ((type) | PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) +/** The public key type corresponding to a key pair type. + * + * You may also pass a key pair type as \p type, it will be left unchanged. + * + * \param type A public key type or key pair type. + * + * \return The corresponding public key type. + * If \p type is not a public key or a key pair, + * the return value is undefined. + */ +#define PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) \ + ((type) & ~PSA_KEY_TYPE_CATEGORY_FLAG_PAIR) + +/** Raw data. + * + * A "key" of this type cannot be used for any cryptographic operation. + * Applications may use this type to store arbitrary data in the keystore. */ +#define PSA_KEY_TYPE_RAW_DATA ((psa_key_type_t) 0x1001) + +/** HMAC key. + * + * The key policy determines which underlying hash algorithm the key can be + * used for. + * + * HMAC keys should generally have the same size as the underlying hash. + * This size can be calculated with #PSA_HASH_LENGTH(\c alg) where + * \c alg is the HMAC algorithm or the underlying hash algorithm. */ +#define PSA_KEY_TYPE_HMAC ((psa_key_type_t) 0x1100) + +/** A secret for key derivation. + * + * This key type is for high-entropy secrets only. For low-entropy secrets, + * #PSA_KEY_TYPE_PASSWORD should be used instead. + * + * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_SECRET or + * #PSA_KEY_DERIVATION_INPUT_PASSWORD input of key derivation algorithms. + * + * The key policy determines which key derivation algorithm the key + * can be used for. + */ +#define PSA_KEY_TYPE_DERIVE ((psa_key_type_t) 0x1200) + +/** A low-entropy secret for password hashing or key derivation. + * + * This key type is suitable for passwords and passphrases which are typically + * intended to be memorizable by humans, and have a low entropy relative to + * their size. It can be used for randomly generated or derived keys with + * maximum or near-maximum entropy, but #PSA_KEY_TYPE_DERIVE is more suitable + * for such keys. It is not suitable for passwords with extremely low entropy, + * such as numerical PINs. + * + * These keys can be used as the #PSA_KEY_DERIVATION_INPUT_PASSWORD input of + * key derivation algorithms. Algorithms that accept such an input were + * designed to accept low-entropy secret and are known as password hashing or + * key stretching algorithms. + * + * These keys cannot be used as the #PSA_KEY_DERIVATION_INPUT_SECRET input of + * key derivation algorithms, as the algorithms that take such an input expect + * it to be high-entropy. + * + * The key policy determines which key derivation algorithm the key can be + * used for, among the permissible subset defined above. + */ +#define PSA_KEY_TYPE_PASSWORD ((psa_key_type_t) 0x1203) + +/** A secret value that can be used to verify a password hash. + * + * The key policy determines which key derivation algorithm the key + * can be used for, among the same permissible subset as for + * #PSA_KEY_TYPE_PASSWORD. + */ +#define PSA_KEY_TYPE_PASSWORD_HASH ((psa_key_type_t) 0x1205) + +/** A secret value that can be used in when computing a password hash. + * + * The key policy determines which key derivation algorithm the key + * can be used for, among the subset of algorithms that can use pepper. + */ +#define PSA_KEY_TYPE_PEPPER ((psa_key_type_t) 0x1206) + +/** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. + * + * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or + * 32 bytes (AES-256). + */ +#define PSA_KEY_TYPE_AES ((psa_key_type_t) 0x2400) + +/** Key for a cipher, AEAD or MAC algorithm based on the + * ARIA block cipher. */ +#define PSA_KEY_TYPE_ARIA ((psa_key_type_t) 0x2406) + +/** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). + * + * The size of the key can be 64 bits (single DES), 128 bits (2-key 3DES) or + * 192 bits (3-key 3DES). + * + * Note that single DES and 2-key 3DES are weak and strongly + * deprecated and should only be used to decrypt legacy data. 3-key 3DES + * is weak and deprecated and should only be used in legacy protocols. + */ +#define PSA_KEY_TYPE_DES ((psa_key_type_t) 0x2301) + +/** Key for a cipher, AEAD or MAC algorithm based on the + * Camellia block cipher. */ +#define PSA_KEY_TYPE_CAMELLIA ((psa_key_type_t) 0x2403) + +/** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. + * + * ChaCha20 and the ChaCha20_Poly1305 construction are defined in RFC 7539. + * + * \note For ChaCha20 and ChaCha20_Poly1305, Mbed TLS only supports + * 12-byte nonces. + * + * \note For ChaCha20, the initial counter value is 0. To encrypt or decrypt + * with the initial counter value 1, you can process and discard a + * 64-byte block before the real data. + */ +#define PSA_KEY_TYPE_CHACHA20 ((psa_key_type_t) 0x2004) + +/** RSA public key. + * + * The size of an RSA key is the bit size of the modulus. + */ +#define PSA_KEY_TYPE_RSA_PUBLIC_KEY ((psa_key_type_t) 0x4001) +/** RSA key pair (private and public key). + * + * The size of an RSA key is the bit size of the modulus. + */ +#define PSA_KEY_TYPE_RSA_KEY_PAIR ((psa_key_type_t) 0x7001) +/** Whether a key type is an RSA key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_RSA(type) \ + (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) + +#define PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4100) +#define PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((psa_key_type_t) 0x7100) +#define PSA_KEY_TYPE_ECC_CURVE_MASK ((psa_key_type_t) 0x00ff) +/** Elliptic curve key pair. + * + * The size of an elliptic curve key is the bit size associated with the curve, + * i.e. the bit size of *q* for a curve over a field *Fq*. + * See the documentation of `PSA_ECC_FAMILY_xxx` curve families for details. + * + * \param curve A value of type ::psa_ecc_family_t that + * identifies the ECC curve to be used. + */ +#define PSA_KEY_TYPE_ECC_KEY_PAIR(curve) \ + (PSA_KEY_TYPE_ECC_KEY_PAIR_BASE | (curve)) +/** Elliptic curve public key. + * + * The size of an elliptic curve public key is the same as the corresponding + * private key (see #PSA_KEY_TYPE_ECC_KEY_PAIR and the documentation of + * `PSA_ECC_FAMILY_xxx` curve families). + * + * \param curve A value of type ::psa_ecc_family_t that + * identifies the ECC curve to be used. + */ +#define PSA_KEY_TYPE_ECC_PUBLIC_KEY(curve) \ + (PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE | (curve)) + +/** Whether a key type is an elliptic curve key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_ECC(type) \ + ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ + ~PSA_KEY_TYPE_ECC_CURVE_MASK) == PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) +/** Whether a key type is an elliptic curve key pair. */ +#define PSA_KEY_TYPE_IS_ECC_KEY_PAIR(type) \ + (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ + PSA_KEY_TYPE_ECC_KEY_PAIR_BASE) +/** Whether a key type is an elliptic curve public key. */ +#define PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(type) \ + (((type) & ~PSA_KEY_TYPE_ECC_CURVE_MASK) == \ + PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE) + +/** Extract the curve from an elliptic curve key type. */ +#define PSA_KEY_TYPE_ECC_GET_FAMILY(type) \ + ((psa_ecc_family_t) (PSA_KEY_TYPE_IS_ECC(type) ? \ + ((type) & PSA_KEY_TYPE_ECC_CURVE_MASK) : \ + 0)) + +/** Check if the curve of given family is Weierstrass elliptic curve. */ +#define PSA_ECC_FAMILY_IS_WEIERSTRASS(family) ((family & 0xc0) == 0) + +/** SEC Koblitz curves over prime fields. + * + * This family comprises the following curves: + * secp192k1, secp224k1, secp256k1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_FAMILY_SECP_K1 ((psa_ecc_family_t) 0x17) + +/** SEC random curves over prime fields. + * + * This family comprises the following curves: + * secp192k1, secp224r1, secp256r1, secp384r1, secp521r1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_FAMILY_SECP_R1 ((psa_ecc_family_t) 0x12) +/* SECP160R2 (SEC2 v1, obsolete) */ +#define PSA_ECC_FAMILY_SECP_R2 ((psa_ecc_family_t) 0x1b) + +/** SEC Koblitz curves over binary fields. + * + * This family comprises the following curves: + * sect163k1, sect233k1, sect239k1, sect283k1, sect409k1, sect571k1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_FAMILY_SECT_K1 ((psa_ecc_family_t) 0x27) + +/** SEC random curves over binary fields. + * + * This family comprises the following curves: + * sect163r1, sect233r1, sect283r1, sect409r1, sect571r1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_FAMILY_SECT_R1 ((psa_ecc_family_t) 0x22) + +/** SEC additional random curves over binary fields. + * + * This family comprises the following curve: + * sect163r2. + * It is defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_FAMILY_SECT_R2 ((psa_ecc_family_t) 0x2b) + +/** Brainpool P random curves. + * + * This family comprises the following curves: + * brainpoolP160r1, brainpoolP192r1, brainpoolP224r1, brainpoolP256r1, + * brainpoolP320r1, brainpoolP384r1, brainpoolP512r1. + * It is defined in RFC 5639. + */ +#define PSA_ECC_FAMILY_BRAINPOOL_P_R1 ((psa_ecc_family_t) 0x30) + +/** Curve25519 and Curve448. + * + * This family comprises the following Montgomery curves: + * - 255-bit: Bernstein et al., + * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. + * The algorithm #PSA_ALG_ECDH performs X25519 when used with this curve. + * - 448-bit: Hamburg, + * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. + * The algorithm #PSA_ALG_ECDH performs X448 when used with this curve. + */ +#define PSA_ECC_FAMILY_MONTGOMERY ((psa_ecc_family_t) 0x41) + +/** The twisted Edwards curves Ed25519 and Ed448. + * + * These curves are suitable for EdDSA (#PSA_ALG_PURE_EDDSA for both curves, + * #PSA_ALG_ED25519PH for the 255-bit curve, + * #PSA_ALG_ED448PH for the 448-bit curve). + * + * This family comprises the following twisted Edwards curves: + * - 255-bit: Edwards25519, the twisted Edwards curve birationally equivalent + * to Curve25519. + * Bernstein et al., _Twisted Edwards curves_, Africacrypt 2008. + * - 448-bit: Edwards448, the twisted Edwards curve birationally equivalent + * to Curve448. + * Hamburg, _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. + */ +#define PSA_ECC_FAMILY_TWISTED_EDWARDS ((psa_ecc_family_t) 0x42) + +#define PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE ((psa_key_type_t) 0x4200) +#define PSA_KEY_TYPE_DH_KEY_PAIR_BASE ((psa_key_type_t) 0x7200) +#define PSA_KEY_TYPE_DH_GROUP_MASK ((psa_key_type_t) 0x00ff) +/** Diffie-Hellman key pair. + * + * \param group A value of type ::psa_dh_family_t that identifies the + * Diffie-Hellman group to be used. + */ +#define PSA_KEY_TYPE_DH_KEY_PAIR(group) \ + (PSA_KEY_TYPE_DH_KEY_PAIR_BASE | (group)) +/** Diffie-Hellman public key. + * + * \param group A value of type ::psa_dh_family_t that identifies the + * Diffie-Hellman group to be used. + */ +#define PSA_KEY_TYPE_DH_PUBLIC_KEY(group) \ + (PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE | (group)) + +/** Whether a key type is a Diffie-Hellman key (pair or public-only). */ +#define PSA_KEY_TYPE_IS_DH(type) \ + ((PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) & \ + ~PSA_KEY_TYPE_DH_GROUP_MASK) == PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) +/** Whether a key type is a Diffie-Hellman key pair. */ +#define PSA_KEY_TYPE_IS_DH_KEY_PAIR(type) \ + (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ + PSA_KEY_TYPE_DH_KEY_PAIR_BASE) +/** Whether a key type is a Diffie-Hellman public key. */ +#define PSA_KEY_TYPE_IS_DH_PUBLIC_KEY(type) \ + (((type) & ~PSA_KEY_TYPE_DH_GROUP_MASK) == \ + PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE) + +/** Extract the group from a Diffie-Hellman key type. */ +#define PSA_KEY_TYPE_DH_GET_FAMILY(type) \ + ((psa_dh_family_t) (PSA_KEY_TYPE_IS_DH(type) ? \ + ((type) & PSA_KEY_TYPE_DH_GROUP_MASK) : \ + 0)) + +/** Diffie-Hellman groups defined in RFC 7919 Appendix A. + * + * This family includes groups with the following key sizes (in bits): + * 2048, 3072, 4096, 6144, 8192. A given implementation may support + * all of these sizes or only a subset. + */ +#define PSA_DH_FAMILY_RFC7919 ((psa_dh_family_t) 0x03) + +#define PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) \ + (((type) >> 8) & 7) +/** The block size of a block cipher. + * + * \param type A cipher key type (value of type #psa_key_type_t). + * + * \return The block size for a block cipher, or 1 for a stream cipher. + * The return value is undefined if \p type is not a supported + * cipher key type. + * + * \note It is possible to build stream cipher algorithms on top of a block + * cipher, for example CTR mode (#PSA_ALG_CTR). + * This macro only takes the key type into account, so it cannot be + * used to determine the size of the data that #psa_cipher_update() + * might buffer for future processing in general. + * + * \note This macro returns a compile-time constant if its argument is one. + * + * \warning This macro may evaluate its argument multiple times. + */ +#define PSA_BLOCK_CIPHER_BLOCK_LENGTH(type) \ + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ + 1u << PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) : \ + 0u) + +/* Note that algorithm values are embedded in the persistent key store, + * as part of key metadata. As a consequence, they must not be changed + * (unless the storage format version changes). + */ + +/** Vendor-defined algorithm flag. + * + * Algorithms defined by this standard will never have the #PSA_ALG_VENDOR_FLAG + * bit set. Vendors who define additional algorithms must use an encoding with + * the #PSA_ALG_VENDOR_FLAG bit set and should respect the bitwise structure + * used by standard encodings whenever practical. + */ +#define PSA_ALG_VENDOR_FLAG ((psa_algorithm_t) 0x80000000) + +#define PSA_ALG_CATEGORY_MASK ((psa_algorithm_t) 0x7f000000) +#define PSA_ALG_CATEGORY_HASH ((psa_algorithm_t) 0x02000000) +#define PSA_ALG_CATEGORY_MAC ((psa_algorithm_t) 0x03000000) +#define PSA_ALG_CATEGORY_CIPHER ((psa_algorithm_t) 0x04000000) +#define PSA_ALG_CATEGORY_AEAD ((psa_algorithm_t) 0x05000000) +#define PSA_ALG_CATEGORY_SIGN ((psa_algorithm_t) 0x06000000) +#define PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION ((psa_algorithm_t) 0x07000000) +#define PSA_ALG_CATEGORY_KEY_DERIVATION ((psa_algorithm_t) 0x08000000) +#define PSA_ALG_CATEGORY_KEY_AGREEMENT ((psa_algorithm_t) 0x09000000) + +/** Whether an algorithm is vendor-defined. + * + * See also #PSA_ALG_VENDOR_FLAG. + */ +#define PSA_ALG_IS_VENDOR_DEFINED(alg) \ + (((alg) & PSA_ALG_VENDOR_FLAG) != 0) + +/** Whether the specified algorithm is a hash algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a hash algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_HASH(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_HASH) + +/** Whether the specified algorithm is a MAC algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a MAC algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_MAC(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_MAC) + +/** Whether the specified algorithm is a symmetric cipher algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a symmetric cipher algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_CIPHER(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_CIPHER) + +/** Whether the specified algorithm is an authenticated encryption + * with associated data (AEAD) algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is an AEAD algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_AEAD(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_AEAD) + +/** Whether the specified algorithm is an asymmetric signature algorithm, + * also known as public-key signature algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is an asymmetric signature algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_SIGN(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_SIGN) + +/** Whether the specified algorithm is an asymmetric encryption algorithm, + * also known as public-key encryption algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is an asymmetric encryption algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_ASYMMETRIC_ENCRYPTION(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION) + +/** Whether the specified algorithm is a key agreement algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a key agreement algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_KEY_AGREEMENT(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_AGREEMENT) + +/** Whether the specified algorithm is a key derivation algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a key derivation algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_KEY_DERIVATION(alg) \ + (((alg) & PSA_ALG_CATEGORY_MASK) == PSA_ALG_CATEGORY_KEY_DERIVATION) + +/** Whether the specified algorithm is a key stretching / password hashing + * algorithm. + * + * A key stretching / password hashing algorithm is a key derivation algorithm + * that is suitable for use with a low-entropy secret such as a password. + * Equivalently, it's a key derivation algorithm that uses a + * #PSA_KEY_DERIVATION_INPUT_PASSWORD input step. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a key stretching / password hashing algorithm, 0 + * otherwise. This macro may return either 0 or 1 if \p alg is not a + * supported algorithm identifier. + */ +#define PSA_ALG_IS_KEY_DERIVATION_STRETCHING(alg) \ + (PSA_ALG_IS_KEY_DERIVATION(alg) && \ + (alg) & PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG) + +/** An invalid algorithm identifier value. */ +/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ +#define PSA_ALG_NONE ((psa_algorithm_t)0) +/* *INDENT-ON* */ + +#define PSA_ALG_HASH_MASK ((psa_algorithm_t) 0x000000ff) +/** MD5 */ +#define PSA_ALG_MD5 ((psa_algorithm_t) 0x02000003) +/** PSA_ALG_RIPEMD160 */ +#define PSA_ALG_RIPEMD160 ((psa_algorithm_t) 0x02000004) +/** SHA1 */ +#define PSA_ALG_SHA_1 ((psa_algorithm_t) 0x02000005) +/** SHA2-224 */ +#define PSA_ALG_SHA_224 ((psa_algorithm_t) 0x02000008) +/** SHA2-256 */ +#define PSA_ALG_SHA_256 ((psa_algorithm_t) 0x02000009) +/** SHA2-384 */ +#define PSA_ALG_SHA_384 ((psa_algorithm_t) 0x0200000a) +/** SHA2-512 */ +#define PSA_ALG_SHA_512 ((psa_algorithm_t) 0x0200000b) +/** SHA2-512/224 */ +#define PSA_ALG_SHA_512_224 ((psa_algorithm_t) 0x0200000c) +/** SHA2-512/256 */ +#define PSA_ALG_SHA_512_256 ((psa_algorithm_t) 0x0200000d) +/** SHA3-224 */ +#define PSA_ALG_SHA3_224 ((psa_algorithm_t) 0x02000010) +/** SHA3-256 */ +#define PSA_ALG_SHA3_256 ((psa_algorithm_t) 0x02000011) +/** SHA3-384 */ +#define PSA_ALG_SHA3_384 ((psa_algorithm_t) 0x02000012) +/** SHA3-512 */ +#define PSA_ALG_SHA3_512 ((psa_algorithm_t) 0x02000013) +/** The first 512 bits (64 bytes) of the SHAKE256 output. + * + * This is the prehashing for Ed448ph (see #PSA_ALG_ED448PH). For other + * scenarios where a hash function based on SHA3/SHAKE is desired, SHA3-512 + * has the same output size and a (theoretically) higher security strength. + */ +#define PSA_ALG_SHAKE256_512 ((psa_algorithm_t) 0x02000015) + +/** In a hash-and-sign algorithm policy, allow any hash algorithm. + * + * This value may be used to form the algorithm usage field of a policy + * for a signature algorithm that is parametrized by a hash. The key + * may then be used to perform operations using the same signature + * algorithm parametrized with any supported hash. + * + * That is, suppose that `PSA_xxx_SIGNATURE` is one of the following macros: + * - #PSA_ALG_RSA_PKCS1V15_SIGN, #PSA_ALG_RSA_PSS, #PSA_ALG_RSA_PSS_ANY_SALT, + * - #PSA_ALG_ECDSA, #PSA_ALG_DETERMINISTIC_ECDSA. + * Then you may create and use a key as follows: + * - Set the key usage field using #PSA_ALG_ANY_HASH, for example: + * ``` + * psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); // or VERIFY + * psa_set_key_algorithm(&attributes, PSA_xxx_SIGNATURE(PSA_ALG_ANY_HASH)); + * ``` + * - Import or generate key material. + * - Call psa_sign_hash() or psa_verify_hash(), passing + * an algorithm built from `PSA_xxx_SIGNATURE` and a specific hash. Each + * call to sign or verify a message may use a different hash. + * ``` + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); + * ``` + * + * This value may not be used to build other algorithms that are + * parametrized over a hash. For any valid use of this macro to build + * an algorithm \c alg, #PSA_ALG_IS_HASH_AND_SIGN(\c alg) is true. + * + * This value may not be used to build an algorithm specification to + * perform an operation. It is only valid to build policies. + */ +#define PSA_ALG_ANY_HASH ((psa_algorithm_t) 0x020000ff) + +#define PSA_ALG_MAC_SUBCATEGORY_MASK ((psa_algorithm_t) 0x00c00000) +#define PSA_ALG_HMAC_BASE ((psa_algorithm_t) 0x03800000) +/** Macro to build an HMAC algorithm. + * + * For example, #PSA_ALG_HMAC(#PSA_ALG_SHA_256) is HMAC-SHA-256. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding HMAC algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_HMAC(hash_alg) \ + (PSA_ALG_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +#define PSA_ALG_HMAC_GET_HASH(hmac_alg) \ + (PSA_ALG_CATEGORY_HASH | ((hmac_alg) & PSA_ALG_HASH_MASK)) + +/** Whether the specified algorithm is an HMAC algorithm. + * + * HMAC is a family of MAC algorithms that are based on a hash function. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is an HMAC algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_HMAC(alg) \ + (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ + PSA_ALG_HMAC_BASE) + +/* In the encoding of a MAC algorithm, the bits corresponding to + * PSA_ALG_MAC_TRUNCATION_MASK encode the length to which the MAC is + * truncated. As an exception, the value 0 means the untruncated algorithm, + * whatever its length is. The length is encoded in 6 bits, so it can + * reach up to 63; the largest MAC is 64 bytes so its trivial truncation + * to full length is correctly encoded as 0 and any non-trivial truncation + * is correctly encoded as a value between 1 and 63. */ +#define PSA_ALG_MAC_TRUNCATION_MASK ((psa_algorithm_t) 0x003f0000) +#define PSA_MAC_TRUNCATION_OFFSET 16 + +/* In the encoding of a MAC algorithm, the bit corresponding to + * #PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm + * is a wildcard algorithm. A key with such wildcard algorithm as permitted + * algorithm policy can be used with any algorithm corresponding to the + * same base class and having a (potentially truncated) MAC length greater or + * equal than the one encoded in #PSA_ALG_MAC_TRUNCATION_MASK. */ +#define PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) + +/** Macro to build a truncated MAC algorithm. + * + * A truncated MAC algorithm is identical to the corresponding MAC + * algorithm except that the MAC value for the truncated algorithm + * consists of only the first \p mac_length bytes of the MAC value + * for the untruncated algorithm. + * + * \note This macro may allow constructing algorithm identifiers that + * are not valid, either because the specified length is larger + * than the untruncated MAC or because the specified length is + * smaller than permitted by the implementation. + * + * \note It is implementation-defined whether a truncated MAC that + * is truncated to the same length as the MAC of the untruncated + * algorithm is considered identical to the untruncated algorithm + * for policy comparison purposes. + * + * \param mac_alg A MAC algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) + * is true). This may be a truncated or untruncated + * MAC algorithm. + * \param mac_length Desired length of the truncated MAC in bytes. + * This must be at most the full length of the MAC + * and must be at least an implementation-specified + * minimum. The implementation-specified minimum + * shall not be zero. + * + * \return The corresponding MAC algorithm with the specified + * length. + * \return Unspecified if \p mac_alg is not a supported + * MAC algorithm or if \p mac_length is too small or + * too large for the specified MAC algorithm. + */ +#define PSA_ALG_TRUNCATED_MAC(mac_alg, mac_length) \ + (((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ + PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) | \ + ((mac_length) << PSA_MAC_TRUNCATION_OFFSET & PSA_ALG_MAC_TRUNCATION_MASK)) + +/** Macro to build the base MAC algorithm corresponding to a truncated + * MAC algorithm. + * + * \param mac_alg A MAC algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) + * is true). This may be a truncated or untruncated + * MAC algorithm. + * + * \return The corresponding base MAC algorithm. + * \return Unspecified if \p mac_alg is not a supported + * MAC algorithm. + */ +#define PSA_ALG_FULL_LENGTH_MAC(mac_alg) \ + ((mac_alg) & ~(PSA_ALG_MAC_TRUNCATION_MASK | \ + PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG)) + +/** Length to which a MAC algorithm is truncated. + * + * \param mac_alg A MAC algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) + * is true). + * + * \return Length of the truncated MAC in bytes. + * \return 0 if \p mac_alg is a non-truncated MAC algorithm. + * \return Unspecified if \p mac_alg is not a supported + * MAC algorithm. + */ +#define PSA_MAC_TRUNCATED_LENGTH(mac_alg) \ + (((mac_alg) & PSA_ALG_MAC_TRUNCATION_MASK) >> PSA_MAC_TRUNCATION_OFFSET) + +/** Macro to build a MAC minimum-MAC-length wildcard algorithm. + * + * A minimum-MAC-length MAC wildcard algorithm permits all MAC algorithms + * sharing the same base algorithm, and where the (potentially truncated) MAC + * length of the specific algorithm is equal to or larger then the wildcard + * algorithm's minimum MAC length. + * + * \note When setting the minimum required MAC length to less than the + * smallest MAC length allowed by the base algorithm, this effectively + * becomes an 'any-MAC-length-allowed' policy for that base algorithm. + * + * \param mac_alg A MAC algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_MAC(\p mac_alg) + * is true). + * \param min_mac_length Desired minimum length of the message authentication + * code in bytes. This must be at most the untruncated + * length of the MAC and must be at least 1. + * + * \return The corresponding MAC wildcard algorithm with the + * specified minimum length. + * \return Unspecified if \p mac_alg is not a supported MAC + * algorithm or if \p min_mac_length is less than 1 or + * too large for the specified MAC algorithm. + */ +#define PSA_ALG_AT_LEAST_THIS_LENGTH_MAC(mac_alg, min_mac_length) \ + (PSA_ALG_TRUNCATED_MAC(mac_alg, min_mac_length) | \ + PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) + +#define PSA_ALG_CIPHER_MAC_BASE ((psa_algorithm_t) 0x03c00000) +/** The CBC-MAC construction over a block cipher + * + * \warning CBC-MAC is insecure in many cases. + * A more secure mode, such as #PSA_ALG_CMAC, is recommended. + */ +#define PSA_ALG_CBC_MAC ((psa_algorithm_t) 0x03c00100) +/** The CMAC construction over a block cipher */ +#define PSA_ALG_CMAC ((psa_algorithm_t) 0x03c00200) + +/** Whether the specified algorithm is a MAC algorithm based on a block cipher. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a MAC algorithm based on a block cipher, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_BLOCK_CIPHER_MAC(alg) \ + (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_MAC_SUBCATEGORY_MASK)) == \ + PSA_ALG_CIPHER_MAC_BASE) + +#define PSA_ALG_CIPHER_STREAM_FLAG ((psa_algorithm_t) 0x00800000) +#define PSA_ALG_CIPHER_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) + +/** Whether the specified algorithm is a stream cipher. + * + * A stream cipher is a symmetric cipher that encrypts or decrypts messages + * by applying a bitwise-xor with a stream of bytes that is generated + * from a key. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a stream cipher algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier or if it is not a symmetric cipher algorithm. + */ +#define PSA_ALG_IS_STREAM_CIPHER(alg) \ + (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_CIPHER_STREAM_FLAG)) == \ + (PSA_ALG_CATEGORY_CIPHER | PSA_ALG_CIPHER_STREAM_FLAG)) + +/** The stream cipher mode of a stream cipher algorithm. + * + * The underlying stream cipher is determined by the key type. + * - To use ChaCha20, use a key type of #PSA_KEY_TYPE_CHACHA20. + */ +#define PSA_ALG_STREAM_CIPHER ((psa_algorithm_t) 0x04800100) + +/** The CTR stream cipher mode. + * + * CTR is a stream cipher which is built from a block cipher. + * The underlying block cipher is determined by the key type. + * For example, to use AES-128-CTR, use this algorithm with + * a key of type #PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). + */ +#define PSA_ALG_CTR ((psa_algorithm_t) 0x04c01000) + +/** The CFB stream cipher mode. + * + * The underlying block cipher is determined by the key type. + */ +#define PSA_ALG_CFB ((psa_algorithm_t) 0x04c01100) + +/** The OFB stream cipher mode. + * + * The underlying block cipher is determined by the key type. + */ +#define PSA_ALG_OFB ((psa_algorithm_t) 0x04c01200) + +/** The XTS cipher mode. + * + * XTS is a cipher mode which is built from a block cipher. It requires at + * least one full block of input, but beyond this minimum the input + * does not need to be a whole number of blocks. + */ +#define PSA_ALG_XTS ((psa_algorithm_t) 0x0440ff00) + +/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. + * + * \warning ECB mode does not protect the confidentiality of the encrypted data + * except in extremely narrow circumstances. It is recommended that applications + * only use ECB if they need to construct an operating mode that the + * implementation does not provide. Implementations are encouraged to provide + * the modes that applications need in preference to supporting direct access + * to ECB. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths are a + * multiple of the block size of the chosen block cipher. + * + * ECB mode does not accept an initialization vector (IV). When using a + * multi-part cipher operation with this algorithm, psa_cipher_generate_iv() + * and psa_cipher_set_iv() must not be called. + */ +#define PSA_ALG_ECB_NO_PADDING ((psa_algorithm_t) 0x04404400) + +/** The CBC block cipher chaining mode, with no padding. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths + * are whole number of blocks for the chosen block cipher. + */ +#define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t) 0x04404000) + +/** The CBC block cipher chaining mode with PKCS#7 padding. + * + * The underlying block cipher is determined by the key type. + * + * This is the padding method defined by PKCS#7 (RFC 2315) §10.3. + */ +#define PSA_ALG_CBC_PKCS7 ((psa_algorithm_t) 0x04404100) + +#define PSA_ALG_AEAD_FROM_BLOCK_FLAG ((psa_algorithm_t) 0x00400000) + +/** Whether the specified algorithm is an AEAD mode on a block cipher. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is an AEAD algorithm which is an AEAD mode based on + * a block cipher, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_AEAD_ON_BLOCK_CIPHER(alg) \ + (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) == \ + (PSA_ALG_CATEGORY_AEAD | PSA_ALG_AEAD_FROM_BLOCK_FLAG)) + +/** The CCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define PSA_ALG_CCM ((psa_algorithm_t) 0x05500100) + +/** The CCM* cipher mode without authentication. + * + * This is CCM* as specified in IEEE 802.15.4 §7, with a tag length of 0. + * For CCM* with a nonzero tag length, use the AEAD algorithm #PSA_ALG_CCM. + * + * The underlying block cipher is determined by the key type. + * + * Currently only 13-byte long IV's are supported. + */ +#define PSA_ALG_CCM_STAR_NO_TAG ((psa_algorithm_t) 0x04c01300) + +/** The GCM authenticated encryption algorithm. + * + * The underlying block cipher is determined by the key type. + */ +#define PSA_ALG_GCM ((psa_algorithm_t) 0x05500200) + +/** The Chacha20-Poly1305 AEAD algorithm. + * + * The ChaCha20_Poly1305 construction is defined in RFC 7539. + * + * Implementations must support 12-byte nonces, may support 8-byte nonces, + * and should reject other sizes. + * + * Implementations must support 16-byte tags and should reject other sizes. + */ +#define PSA_ALG_CHACHA20_POLY1305 ((psa_algorithm_t) 0x05100500) + +/* In the encoding of an AEAD algorithm, the bits corresponding to + * PSA_ALG_AEAD_TAG_LENGTH_MASK encode the length of the AEAD tag. + * The constants for default lengths follow this encoding. + */ +#define PSA_ALG_AEAD_TAG_LENGTH_MASK ((psa_algorithm_t) 0x003f0000) +#define PSA_AEAD_TAG_LENGTH_OFFSET 16 + +/* In the encoding of an AEAD algorithm, the bit corresponding to + * #PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG encodes the fact that the algorithm + * is a wildcard algorithm. A key with such wildcard algorithm as permitted + * algorithm policy can be used with any algorithm corresponding to the + * same base class and having a tag length greater than or equal to the one + * encoded in #PSA_ALG_AEAD_TAG_LENGTH_MASK. */ +#define PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG ((psa_algorithm_t) 0x00008000) + +/** Macro to build a shortened AEAD algorithm. + * + * A shortened AEAD algorithm is similar to the corresponding AEAD + * algorithm, but has an authentication tag that consists of fewer bytes. + * Depending on the algorithm, the tag length may affect the calculation + * of the ciphertext. + * + * \param aead_alg An AEAD algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) + * is true). + * \param tag_length Desired length of the authentication tag in bytes. + * + * \return The corresponding AEAD algorithm with the specified + * length. + * \return Unspecified if \p aead_alg is not a supported + * AEAD algorithm or if \p tag_length is not valid + * for the specified AEAD algorithm. + */ +#define PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, tag_length) \ + (((aead_alg) & ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | \ + PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG)) | \ + ((tag_length) << PSA_AEAD_TAG_LENGTH_OFFSET & \ + PSA_ALG_AEAD_TAG_LENGTH_MASK)) + +/** Retrieve the tag length of a specified AEAD algorithm + * + * \param aead_alg An AEAD algorithm identifier (value of type + * #psa_algorithm_t such that #PSA_ALG_IS_AEAD(\p aead_alg) + * is true). + * + * \return The tag length specified by the input algorithm. + * \return Unspecified if \p aead_alg is not a supported + * AEAD algorithm. + */ +#define PSA_ALG_AEAD_GET_TAG_LENGTH(aead_alg) \ + (((aead_alg) & PSA_ALG_AEAD_TAG_LENGTH_MASK) >> \ + PSA_AEAD_TAG_LENGTH_OFFSET) + +/** Calculate the corresponding AEAD algorithm with the default tag length. + * + * \param aead_alg An AEAD algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p aead_alg) is true). + * + * \return The corresponding AEAD algorithm with the default + * tag length for that algorithm. + */ +#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(aead_alg) \ + ( \ + PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CCM) \ + PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_GCM) \ + PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, PSA_ALG_CHACHA20_POLY1305) \ + 0) +#define PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG_CASE(aead_alg, ref) \ + PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, 0) == \ + PSA_ALG_AEAD_WITH_SHORTENED_TAG(ref, 0) ? \ + ref : + +/** Macro to build an AEAD minimum-tag-length wildcard algorithm. + * + * A minimum-tag-length AEAD wildcard algorithm permits all AEAD algorithms + * sharing the same base algorithm, and where the tag length of the specific + * algorithm is equal to or larger then the minimum tag length specified by the + * wildcard algorithm. + * + * \note When setting the minimum required tag length to less than the + * smallest tag length allowed by the base algorithm, this effectively + * becomes an 'any-tag-length-allowed' policy for that base algorithm. + * + * \param aead_alg An AEAD algorithm identifier (value of type + * #psa_algorithm_t such that + * #PSA_ALG_IS_AEAD(\p aead_alg) is true). + * \param min_tag_length Desired minimum length of the authentication tag in + * bytes. This must be at least 1 and at most the largest + * allowed tag length of the algorithm. + * + * \return The corresponding AEAD wildcard algorithm with the + * specified minimum length. + * \return Unspecified if \p aead_alg is not a supported + * AEAD algorithm or if \p min_tag_length is less than 1 + * or too large for the specified AEAD algorithm. + */ +#define PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG(aead_alg, min_tag_length) \ + (PSA_ALG_AEAD_WITH_SHORTENED_TAG(aead_alg, min_tag_length) | \ + PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) + +#define PSA_ALG_RSA_PKCS1V15_SIGN_BASE ((psa_algorithm_t) 0x06000200) +/** RSA PKCS#1 v1.5 signature with hashing. + * + * This is the signature scheme defined by RFC 8017 + * (PKCS#1: RSA Cryptography Specifications) under the name + * RSASSA-PKCS1-v1_5. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding RSA PKCS#1 v1.5 signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_RSA_PKCS1V15_SIGN(hash_alg) \ + (PSA_ALG_RSA_PKCS1V15_SIGN_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +/** Raw PKCS#1 v1.5 signature. + * + * The input to this algorithm is the DigestInfo structure used by + * RFC 8017 (PKCS#1: RSA Cryptography Specifications), §9.2 + * steps 3–6. + */ +#define PSA_ALG_RSA_PKCS1V15_SIGN_RAW PSA_ALG_RSA_PKCS1V15_SIGN_BASE +#define PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PKCS1V15_SIGN_BASE) + +#define PSA_ALG_RSA_PSS_BASE ((psa_algorithm_t) 0x06000300) +#define PSA_ALG_RSA_PSS_ANY_SALT_BASE ((psa_algorithm_t) 0x06001300) +/** RSA PSS signature with hashing. + * + * This is the signature scheme defined by RFC 8017 + * (PKCS#1: RSA Cryptography Specifications) under the name + * RSASSA-PSS, with the message generation function MGF1, and with + * a salt length equal to the length of the hash, or the largest + * possible salt length for the algorithm and key size if that is + * smaller than the hash length. The specified hash algorithm is + * used to hash the input message, to create the salted hash, and + * for the mask generation. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding RSA PSS signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_RSA_PSS(hash_alg) \ + (PSA_ALG_RSA_PSS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +/** RSA PSS signature with hashing with relaxed verification. + * + * This algorithm has the same behavior as #PSA_ALG_RSA_PSS when signing, + * but allows an arbitrary salt length (including \c 0) when verifying a + * signature. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding RSA PSS signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_RSA_PSS_ANY_SALT(hash_alg) \ + (PSA_ALG_RSA_PSS_ANY_SALT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +/** Whether the specified algorithm is RSA PSS with standard salt. + * + * \param alg An algorithm value or an algorithm policy wildcard. + * + * \return 1 if \p alg is of the form + * #PSA_ALG_RSA_PSS(\c hash_alg), + * where \c hash_alg is a hash algorithm or + * #PSA_ALG_ANY_HASH. 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not + * a supported algorithm identifier or policy. + */ +#define PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_BASE) + +/** Whether the specified algorithm is RSA PSS with any salt. + * + * \param alg An algorithm value or an algorithm policy wildcard. + * + * \return 1 if \p alg is of the form + * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), + * where \c hash_alg is a hash algorithm or + * #PSA_ALG_ANY_HASH. 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not + * a supported algorithm identifier or policy. + */ +#define PSA_ALG_IS_RSA_PSS_ANY_SALT(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_ANY_SALT_BASE) + +/** Whether the specified algorithm is RSA PSS. + * + * This includes any of the RSA PSS algorithm variants, regardless of the + * constraints on salt length. + * + * \param alg An algorithm value or an algorithm policy wildcard. + * + * \return 1 if \p alg is of the form + * #PSA_ALG_RSA_PSS(\c hash_alg) or + * #PSA_ALG_RSA_PSS_ANY_SALT_BASE(\c hash_alg), + * where \c hash_alg is a hash algorithm or + * #PSA_ALG_ANY_HASH. 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not + * a supported algorithm identifier or policy. + */ +#define PSA_ALG_IS_RSA_PSS(alg) \ + (PSA_ALG_IS_RSA_PSS_STANDARD_SALT(alg) || \ + PSA_ALG_IS_RSA_PSS_ANY_SALT(alg)) + +#define PSA_ALG_ECDSA_BASE ((psa_algorithm_t) 0x06000600) +/** ECDSA signature with hashing. + * + * This is the ECDSA signature scheme defined by ANSI X9.62, + * with a random per-message secret number (*k*). + * + * The representation of the signature as a byte string consists of + * the concatenation of the signature values *r* and *s*. Each of + * *r* and *s* is encoded as an *N*-octet string, where *N* is the length + * of the base point of the curve in octets. Each value is represented + * in big-endian order (most significant octet first). + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding ECDSA signature algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_ECDSA(hash_alg) \ + (PSA_ALG_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +/** ECDSA signature without hashing. + * + * This is the same signature scheme as #PSA_ALG_ECDSA(), but + * without specifying a hash algorithm. This algorithm may only be + * used to sign or verify a sequence of bytes that should be an + * already-calculated hash. Note that the input is padded with + * zeros on the left or truncated on the left as required to fit + * the curve size. + */ +#define PSA_ALG_ECDSA_ANY PSA_ALG_ECDSA_BASE +#define PSA_ALG_DETERMINISTIC_ECDSA_BASE ((psa_algorithm_t) 0x06000700) +/** Deterministic ECDSA signature with hashing. + * + * This is the deterministic ECDSA signature scheme defined by RFC 6979. + * + * The representation of a signature is the same as with #PSA_ALG_ECDSA(). + * + * Note that when this algorithm is used for verification, signatures + * made with randomized ECDSA (#PSA_ALG_ECDSA(\p hash_alg)) with the + * same private key are accepted. In other words, + * #PSA_ALG_DETERMINISTIC_ECDSA(\p hash_alg) differs from + * #PSA_ALG_ECDSA(\p hash_alg) only for signature, not for verification. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * This includes #PSA_ALG_ANY_HASH + * when specifying the algorithm in a usage policy. + * + * \return The corresponding deterministic ECDSA signature + * algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_DETERMINISTIC_ECDSA(hash_alg) \ + (PSA_ALG_DETERMINISTIC_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t) 0x00000100) +#define PSA_ALG_IS_ECDSA(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_ECDSA_DETERMINISTIC_FLAG) == \ + PSA_ALG_ECDSA_BASE) +#define PSA_ALG_ECDSA_IS_DETERMINISTIC(alg) \ + (((alg) & PSA_ALG_ECDSA_DETERMINISTIC_FLAG) != 0) +#define PSA_ALG_IS_DETERMINISTIC_ECDSA(alg) \ + (PSA_ALG_IS_ECDSA(alg) && PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) +#define PSA_ALG_IS_RANDOMIZED_ECDSA(alg) \ + (PSA_ALG_IS_ECDSA(alg) && !PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) + +/** Edwards-curve digital signature algorithm without prehashing (PureEdDSA), + * using standard parameters. + * + * Contexts are not supported in the current version of this specification + * because there is no suitable signature interface that can take the + * context as a parameter. A future version of this specification may add + * suitable functions and extend this algorithm to support contexts. + * + * PureEdDSA requires an elliptic curve key on a twisted Edwards curve. + * In this specification, the following curves are supported: + * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 255-bit: Ed25519 as specified + * in RFC 8032. + * The curve is Edwards25519. + * The hash function used internally is SHA-512. + * - #PSA_ECC_FAMILY_TWISTED_EDWARDS, 448-bit: Ed448 as specified + * in RFC 8032. + * The curve is Edwards448. + * The hash function used internally is the first 114 bytes of the + * SHAKE256 output. + * + * This algorithm can be used with psa_sign_message() and + * psa_verify_message(). Since there is no prehashing, it cannot be used + * with psa_sign_hash() or psa_verify_hash(). + * + * The signature format is the concatenation of R and S as defined by + * RFC 8032 §5.1.6 and §5.2.6 (a 64-byte string for Ed25519, a 114-byte + * string for Ed448). + */ +#define PSA_ALG_PURE_EDDSA ((psa_algorithm_t) 0x06000800) + +#define PSA_ALG_HASH_EDDSA_BASE ((psa_algorithm_t) 0x06000900) +#define PSA_ALG_IS_HASH_EDDSA(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HASH_EDDSA_BASE) + +/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), + * using SHA-512 and the Edwards25519 curve. + * + * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. + * + * This algorithm is Ed25519 as specified in RFC 8032. + * The curve is Edwards25519. + * The prehash is SHA-512. + * The hash function used internally is SHA-512. + * + * This is a hash-and-sign algorithm: to calculate a signature, + * you can either: + * - call psa_sign_message() on the message; + * - or calculate the SHA-512 hash of the message + * with psa_hash_compute() + * or with a multi-part hash operation started with psa_hash_setup(), + * using the hash algorithm #PSA_ALG_SHA_512, + * then sign the calculated hash with psa_sign_hash(). + * Verifying a signature is similar, using psa_verify_message() or + * psa_verify_hash() instead of the signature function. + */ +#define PSA_ALG_ED25519PH \ + (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHA_512 & PSA_ALG_HASH_MASK)) + +/** Edwards-curve digital signature algorithm with prehashing (HashEdDSA), + * using SHAKE256 and the Edwards448 curve. + * + * See #PSA_ALG_PURE_EDDSA regarding context support and the signature format. + * + * This algorithm is Ed448 as specified in RFC 8032. + * The curve is Edwards448. + * The prehash is the first 64 bytes of the SHAKE256 output. + * The hash function used internally is the first 114 bytes of the + * SHAKE256 output. + * + * This is a hash-and-sign algorithm: to calculate a signature, + * you can either: + * - call psa_sign_message() on the message; + * - or calculate the first 64 bytes of the SHAKE256 output of the message + * with psa_hash_compute() + * or with a multi-part hash operation started with psa_hash_setup(), + * using the hash algorithm #PSA_ALG_SHAKE256_512, + * then sign the calculated hash with psa_sign_hash(). + * Verifying a signature is similar, using psa_verify_message() or + * psa_verify_hash() instead of the signature function. + */ +#define PSA_ALG_ED448PH \ + (PSA_ALG_HASH_EDDSA_BASE | (PSA_ALG_SHAKE256_512 & PSA_ALG_HASH_MASK)) + +/* Default definition, to be overridden if the library is extended with + * more hash-and-sign algorithms that we want to keep out of this header + * file. */ +#define PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg) 0 + +/** Whether the specified algorithm is a signature algorithm that can be used + * with psa_sign_hash() and psa_verify_hash(). + * + * This encompasses all strict hash-and-sign algorithms categorized by + * PSA_ALG_IS_HASH_AND_SIGN(), as well as algorithms that follow the + * paradigm more loosely: + * - #PSA_ALG_RSA_PKCS1V15_SIGN_RAW (expects its input to be an encoded hash) + * - #PSA_ALG_ECDSA_ANY (doesn't specify what kind of hash the input is) + * + * \param alg An algorithm identifier (value of type psa_algorithm_t). + * + * \return 1 if alg is a signature algorithm that can be used to sign a + * hash. 0 if alg is a signature algorithm that can only be used + * to sign a message. 0 if alg is not a signature algorithm. + * This macro can return either 0 or 1 if alg is not a + * supported algorithm identifier. + */ +#define PSA_ALG_IS_SIGN_HASH(alg) \ + (PSA_ALG_IS_RSA_PSS(alg) || PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || \ + PSA_ALG_IS_ECDSA(alg) || PSA_ALG_IS_HASH_EDDSA(alg) || \ + PSA_ALG_IS_VENDOR_HASH_AND_SIGN(alg)) + +/** Whether the specified algorithm is a signature algorithm that can be used + * with psa_sign_message() and psa_verify_message(). + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if alg is a signature algorithm that can be used to sign a + * message. 0 if \p alg is a signature algorithm that can only be used + * to sign an already-calculated hash. 0 if \p alg is not a signature + * algorithm. This macro can return either 0 or 1 if \p alg is not a + * supported algorithm identifier. + */ +#define PSA_ALG_IS_SIGN_MESSAGE(alg) \ + (PSA_ALG_IS_SIGN_HASH(alg) || (alg) == PSA_ALG_PURE_EDDSA) + +/** Whether the specified algorithm is a hash-and-sign algorithm. + * + * Hash-and-sign algorithms are asymmetric (public-key) signature algorithms + * structured in two parts: first the calculation of a hash in a way that + * does not depend on the key, then the calculation of a signature from the + * hash value and the key. Hash-and-sign algorithms encode the hash + * used for the hashing step, and you can call #PSA_ALG_SIGN_GET_HASH + * to extract this algorithm. + * + * Thus, for a hash-and-sign algorithm, + * `psa_sign_message(key, alg, input, ...)` is equivalent to + * ``` + * psa_hash_compute(PSA_ALG_SIGN_GET_HASH(alg), input, ..., hash, ...); + * psa_sign_hash(key, alg, hash, ..., signature, ...); + * ``` + * Most usefully, separating the hash from the signature allows the hash + * to be calculated in multiple steps with psa_hash_setup(), psa_hash_update() + * and psa_hash_finish(). Likewise psa_verify_message() is equivalent to + * calculating the hash and then calling psa_verify_hash(). + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a hash-and-sign algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_HASH_AND_SIGN(alg) \ + (PSA_ALG_IS_SIGN_HASH(alg) && \ + ((alg) & PSA_ALG_HASH_MASK) != 0) + +/** Get the hash used by a hash-and-sign signature algorithm. + * + * A hash-and-sign algorithm is a signature algorithm which is + * composed of two phases: first a hashing phase which does not use + * the key and produces a hash of the input message, then a signing + * phase which only uses the hash and the key and not the message + * itself. + * + * \param alg A signature algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_SIGN(\p alg) is true). + * + * \return The underlying hash algorithm if \p alg is a hash-and-sign + * algorithm. + * \return 0 if \p alg is a signature algorithm that does not + * follow the hash-and-sign structure. + * \return Unspecified if \p alg is not a signature algorithm or + * if it is not supported by the implementation. + */ +#define PSA_ALG_SIGN_GET_HASH(alg) \ + (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ + ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ + 0) + +/** RSA PKCS#1 v1.5 encryption. + */ +#define PSA_ALG_RSA_PKCS1V15_CRYPT ((psa_algorithm_t) 0x07000200) + +#define PSA_ALG_RSA_OAEP_BASE ((psa_algorithm_t) 0x07000300) +/** RSA OAEP encryption. + * + * This is the encryption scheme defined by RFC 8017 + * (PKCS#1: RSA Cryptography Specifications) under the name + * RSAES-OAEP, with the message generation function MGF1. + * + * \param hash_alg The hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true) to use + * for MGF1. + * + * \return The corresponding RSA OAEP encryption algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_RSA_OAEP(hash_alg) \ + (PSA_ALG_RSA_OAEP_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +#define PSA_ALG_IS_RSA_OAEP(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_OAEP_BASE) +#define PSA_ALG_RSA_OAEP_GET_HASH(alg) \ + (PSA_ALG_IS_RSA_OAEP(alg) ? \ + ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ + 0) + +#define PSA_ALG_HKDF_BASE ((psa_algorithm_t) 0x08000100) +/** Macro to build an HKDF algorithm. + * + * For example, `PSA_ALG_HKDF(PSA_ALG_SHA_256)` is HKDF using HMAC-SHA-256. + * + * This key derivation algorithm uses the following inputs: + * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt used in the "extract" step. + * It is optional; if omitted, the derivation uses an empty salt. + * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key used in the "extract" step. + * - #PSA_KEY_DERIVATION_INPUT_INFO is the info string used in the "expand" step. + * You must pass #PSA_KEY_DERIVATION_INPUT_SALT before #PSA_KEY_DERIVATION_INPUT_SECRET. + * You may pass #PSA_KEY_DERIVATION_INPUT_INFO at any time after steup and before + * starting to generate output. + * + * \warning HKDF processes the salt as follows: first hash it with hash_alg + * if the salt is longer than the block size of the hash algorithm; then + * pad with null bytes up to the block size. As a result, it is possible + * for distinct salt inputs to result in the same outputs. To ensure + * unique outputs, it is recommended to use a fixed length for salt values. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding HKDF algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_HKDF(hash_alg) \ + (PSA_ALG_HKDF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +/** Whether the specified algorithm is an HKDF algorithm. + * + * HKDF is a family of key derivation algorithms that are based on a hash + * function and the HMAC construction. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is an HKDF algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_HKDF(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE) +#define PSA_ALG_HKDF_GET_HASH(hkdf_alg) \ + (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) + +#define PSA_ALG_HKDF_EXTRACT_BASE ((psa_algorithm_t) 0x08000400) +/** Macro to build an HKDF-Extract algorithm. + * + * For example, `PSA_ALG_HKDF_EXTRACT(PSA_ALG_SHA_256)` is + * HKDF-Extract using HMAC-SHA-256. + * + * This key derivation algorithm uses the following inputs: + * - PSA_KEY_DERIVATION_INPUT_SALT is the salt. + * - PSA_KEY_DERIVATION_INPUT_SECRET is the input keying material used in the + * "extract" step. + * The inputs are mandatory and must be passed in the order above. + * Each input may only be passed once. + * + * \warning HKDF-Extract is not meant to be used on its own. PSA_ALG_HKDF + * should be used instead if possible. PSA_ALG_HKDF_EXTRACT is provided + * as a separate algorithm for the sake of protocols that use it as a + * building block. It may also be a slight performance optimization + * in applications that use HKDF with the same salt and key but many + * different info strings. + * + * \warning HKDF processes the salt as follows: first hash it with hash_alg + * if the salt is longer than the block size of the hash algorithm; then + * pad with null bytes up to the block size. As a result, it is possible + * for distinct salt inputs to result in the same outputs. To ensure + * unique outputs, it is recommended to use a fixed length for salt values. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding HKDF-Extract algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_HKDF_EXTRACT(hash_alg) \ + (PSA_ALG_HKDF_EXTRACT_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +/** Whether the specified algorithm is an HKDF-Extract algorithm. + * + * HKDF-Extract is a family of key derivation algorithms that are based + * on a hash function and the HMAC construction. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is an HKDF-Extract algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_HKDF_EXTRACT(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE) + +#define PSA_ALG_HKDF_EXPAND_BASE ((psa_algorithm_t) 0x08000500) +/** Macro to build an HKDF-Expand algorithm. + * + * For example, `PSA_ALG_HKDF_EXPAND(PSA_ALG_SHA_256)` is + * HKDF-Expand using HMAC-SHA-256. + * + * This key derivation algorithm uses the following inputs: + * - PSA_KEY_DERIVATION_INPUT_SECRET is the pseudorandom key (PRK). + * - PSA_KEY_DERIVATION_INPUT_INFO is the info string. + * + * The inputs are mandatory and must be passed in the order above. + * Each input may only be passed once. + * + * \warning HKDF-Expand is not meant to be used on its own. `PSA_ALG_HKDF` + * should be used instead if possible. `PSA_ALG_HKDF_EXPAND` is provided as + * a separate algorithm for the sake of protocols that use it as a building + * block. It may also be a slight performance optimization in applications + * that use HKDF with the same salt and key but many different info strings. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding HKDF-Expand algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_HKDF_EXPAND(hash_alg) \ + (PSA_ALG_HKDF_EXPAND_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +/** Whether the specified algorithm is an HKDF-Expand algorithm. + * + * HKDF-Expand is a family of key derivation algorithms that are based + * on a hash function and the HMAC construction. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is an HKDF-Expand algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_HKDF_EXPAND(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) + +/** Whether the specified algorithm is an HKDF or HKDF-Extract or + * HKDF-Expand algorithm. + * + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is any HKDF type algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_ANY_HKDF(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_BASE || \ + ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXTRACT_BASE || \ + ((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_HKDF_EXPAND_BASE) + +#define PSA_ALG_TLS12_PRF_BASE ((psa_algorithm_t) 0x08000200) +/** Macro to build a TLS-1.2 PRF algorithm. + * + * TLS 1.2 uses a custom pseudorandom function (PRF) for key schedule, + * specified in Section 5 of RFC 5246. It is based on HMAC and can be + * used with either SHA-256 or SHA-384. + * + * This key derivation algorithm uses the following inputs, which must be + * passed in the order given here: + * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. + * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. + * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. + * + * For the application to TLS-1.2 key expansion, the seed is the + * concatenation of ServerHello.Random + ClientHello.Random, + * and the label is "key expansion". + * + * For example, `PSA_ALG_TLS12_PRF(PSA_ALG_SHA_256)` represents the + * TLS 1.2 PRF using HMAC-SHA-256. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding TLS-1.2 PRF algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_TLS12_PRF(hash_alg) \ + (PSA_ALG_TLS12_PRF_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +/** Whether the specified algorithm is a TLS-1.2 PRF algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is a TLS-1.2 PRF algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_TLS12_PRF(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PRF_BASE) +#define PSA_ALG_TLS12_PRF_GET_HASH(hkdf_alg) \ + (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) + +#define PSA_ALG_TLS12_PSK_TO_MS_BASE ((psa_algorithm_t) 0x08000300) +/** Macro to build a TLS-1.2 PSK-to-MasterSecret algorithm. + * + * In a pure-PSK handshake in TLS 1.2, the master secret is derived + * from the PreSharedKey (PSK) through the application of padding + * (RFC 4279, Section 2) and the TLS-1.2 PRF (RFC 5246, Section 5). + * The latter is based on HMAC and can be used with either SHA-256 + * or SHA-384. + * + * This key derivation algorithm uses the following inputs, which must be + * passed in the order given here: + * - #PSA_KEY_DERIVATION_INPUT_SEED is the seed. + * - #PSA_KEY_DERIVATION_INPUT_OTHER_SECRET is the other secret for the + * computation of the premaster secret. This input is optional; + * if omitted, it defaults to a string of null bytes with the same length + * as the secret (PSK) input. + * - #PSA_KEY_DERIVATION_INPUT_SECRET is the secret key. + * - #PSA_KEY_DERIVATION_INPUT_LABEL is the label. + * + * For the application to TLS-1.2, the seed (which is + * forwarded to the TLS-1.2 PRF) is the concatenation of the + * ClientHello.Random + ServerHello.Random, + * the label is "master secret" or "extended master secret" and + * the other secret depends on the key exchange specified in the cipher suite: + * - for a plain PSK cipher suite (RFC 4279, Section 2), omit + * PSA_KEY_DERIVATION_INPUT_OTHER_SECRET + * - for a DHE-PSK (RFC 4279, Section 3) or ECDHE-PSK cipher suite + * (RFC 5489, Section 2), the other secret should be the output of the + * PSA_ALG_FFDH or PSA_ALG_ECDH key agreement performed with the peer. + * The recommended way to pass this input is to use a key derivation + * algorithm constructed as + * PSA_ALG_KEY_AGREEMENT(ka_alg, PSA_ALG_TLS12_PSK_TO_MS(hash_alg)) + * and to call psa_key_derivation_key_agreement(). Alternatively, + * this input may be an output of `psa_raw_key_agreement()` passed with + * psa_key_derivation_input_bytes(), or an equivalent input passed with + * psa_key_derivation_input_bytes() or psa_key_derivation_input_key(). + * - for a RSA-PSK cipher suite (RFC 4279, Section 4), the other secret + * should be the 48-byte client challenge (the PreMasterSecret of + * (RFC 5246, Section 7.4.7.1)) concatenation of the TLS version and + * a 46-byte random string chosen by the client. On the server, this is + * typically an output of psa_asymmetric_decrypt() using + * PSA_ALG_RSA_PKCS1V15_CRYPT, passed to the key derivation operation + * with `psa_key_derivation_input_bytes()`. + * + * For example, `PSA_ALG_TLS12_PSK_TO_MS(PSA_ALG_SHA_256)` represents the + * TLS-1.2 PSK to MasterSecret derivation PRF using HMAC-SHA-256. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding TLS-1.2 PSK to MS algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_TLS12_PSK_TO_MS(hash_alg) \ + (PSA_ALG_TLS12_PSK_TO_MS_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +/** Whether the specified algorithm is a TLS-1.2 PSK to MS algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is a TLS-1.2 PSK to MS algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_TLS12_PSK_TO_MS(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_TLS12_PSK_TO_MS_BASE) +#define PSA_ALG_TLS12_PSK_TO_MS_GET_HASH(hkdf_alg) \ + (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) + +/* The TLS 1.2 ECJPAKE-to-PMS KDF. It takes the shared secret K (an EC point + * in case of EC J-PAKE) and calculates SHA256(K.X) that the rest of TLS 1.2 + * will use to derive the session secret, as defined by step 2 of + * https://datatracker.ietf.org/doc/html/draft-cragie-tls-ecjpake-01#section-8.7. + * Uses PSA_ALG_SHA_256. + * This function takes a single input: + * #PSA_KEY_DERIVATION_INPUT_SECRET is the shared secret K from EC J-PAKE. + * The only supported curve is secp256r1 (the 256-bit curve in + * #PSA_ECC_FAMILY_SECP_R1), so the input must be exactly 65 bytes. + * The output has to be read as a single chunk of 32 bytes, defined as + * PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE. + */ +#define PSA_ALG_TLS12_ECJPAKE_TO_PMS ((psa_algorithm_t) 0x08000609) + +/* This flag indicates whether the key derivation algorithm is suitable for + * use on low-entropy secrets such as password - these algorithms are also + * known as key stretching or password hashing schemes. These are also the + * algorithms that accepts inputs of type #PSA_KEY_DERIVATION_INPUT_PASSWORD. + * + * Those algorithms cannot be combined with a key agreement algorithm. + */ +#define PSA_ALG_KEY_DERIVATION_STRETCHING_FLAG ((psa_algorithm_t) 0x00800000) + +#define PSA_ALG_PBKDF2_HMAC_BASE ((psa_algorithm_t) 0x08800100) +/** Macro to build a PBKDF2-HMAC password hashing / key stretching algorithm. + * + * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). + * This macro specifies the PBKDF2 algorithm constructed using a PRF based on + * HMAC with the specified hash. + * For example, `PSA_ALG_PBKDF2_HMAC(PSA_ALG_SHA_256)` specifies PBKDF2 + * using the PRF HMAC-SHA-256. + * + * This key derivation algorithm uses the following inputs, which must be + * provided in the following order: + * - #PSA_KEY_DERIVATION_INPUT_COST is the iteration count. + * This input step must be used exactly once. + * - #PSA_KEY_DERIVATION_INPUT_SALT is the salt. + * This input step must be used one or more times; if used several times, the + * inputs will be concatenated. This can be used to build the final salt + * from multiple sources, both public and secret (also known as pepper). + * - #PSA_KEY_DERIVATION_INPUT_PASSWORD is the password to be hashed. + * This input step must be used exactly once. + * + * \param hash_alg A hash algorithm (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_HASH(\p hash_alg) is true). + * + * \return The corresponding PBKDF2-HMAC-XXX algorithm. + * \return Unspecified if \p hash_alg is not a supported + * hash algorithm. + */ +#define PSA_ALG_PBKDF2_HMAC(hash_alg) \ + (PSA_ALG_PBKDF2_HMAC_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) + +/** Whether the specified algorithm is a PBKDF2-HMAC algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is a PBKDF2-HMAC algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key derivation algorithm identifier. + */ +#define PSA_ALG_IS_PBKDF2_HMAC(alg) \ + (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_PBKDF2_HMAC_BASE) +#define PSA_ALG_PBKDF2_HMAC_GET_HASH(pbkdf2_alg) \ + (PSA_ALG_CATEGORY_HASH | ((pbkdf2_alg) & PSA_ALG_HASH_MASK)) +/** The PBKDF2-AES-CMAC-PRF-128 password hashing / key stretching algorithm. + * + * PBKDF2 is defined by PKCS#5, republished as RFC 8018 (section 5.2). + * This macro specifies the PBKDF2 algorithm constructed using the + * AES-CMAC-PRF-128 PRF specified by RFC 4615. + * + * This key derivation algorithm uses the same inputs as + * #PSA_ALG_PBKDF2_HMAC() with the same constraints. + */ +#define PSA_ALG_PBKDF2_AES_CMAC_PRF_128 ((psa_algorithm_t) 0x08800200) + +#define PSA_ALG_IS_PBKDF2(kdf_alg) \ + (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg) || \ + ((kdf_alg) == PSA_ALG_PBKDF2_AES_CMAC_PRF_128)) + +#define PSA_ALG_KEY_DERIVATION_MASK ((psa_algorithm_t) 0xfe00ffff) +#define PSA_ALG_KEY_AGREEMENT_MASK ((psa_algorithm_t) 0xffff0000) + +/** Macro to build a combined algorithm that chains a key agreement with + * a key derivation. + * + * \param ka_alg A key agreement algorithm (\c PSA_ALG_XXX value such + * that #PSA_ALG_IS_KEY_AGREEMENT(\p ka_alg) is true). + * \param kdf_alg A key derivation algorithm (\c PSA_ALG_XXX value such + * that #PSA_ALG_IS_KEY_DERIVATION(\p kdf_alg) is true). + * + * \return The corresponding key agreement and derivation + * algorithm. + * \return Unspecified if \p ka_alg is not a supported + * key agreement algorithm or \p kdf_alg is not a + * supported key derivation algorithm. + */ +#define PSA_ALG_KEY_AGREEMENT(ka_alg, kdf_alg) \ + ((ka_alg) | (kdf_alg)) + +#define PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) \ + (((alg) & PSA_ALG_KEY_DERIVATION_MASK) | PSA_ALG_CATEGORY_KEY_DERIVATION) + +#define PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) \ + (((alg) & PSA_ALG_KEY_AGREEMENT_MASK) | PSA_ALG_CATEGORY_KEY_AGREEMENT) + +/** Whether the specified algorithm is a raw key agreement algorithm. + * + * A raw key agreement algorithm is one that does not specify + * a key derivation function. + * Usually, raw key agreement algorithms are constructed directly with + * a \c PSA_ALG_xxx macro while non-raw key agreement algorithms are + * constructed with #PSA_ALG_KEY_AGREEMENT(). + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \p alg is a raw key agreement algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \p alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_RAW_KEY_AGREEMENT(alg) \ + (PSA_ALG_IS_KEY_AGREEMENT(alg) && \ + PSA_ALG_KEY_AGREEMENT_GET_KDF(alg) == PSA_ALG_CATEGORY_KEY_DERIVATION) + +#define PSA_ALG_IS_KEY_DERIVATION_OR_AGREEMENT(alg) \ + ((PSA_ALG_IS_KEY_DERIVATION(alg) || PSA_ALG_IS_KEY_AGREEMENT(alg))) + +/** The finite-field Diffie-Hellman (DH) key agreement algorithm. + * + * The shared secret produced by key agreement is + * `g^{ab}` in big-endian format. + * It is `ceiling(m / 8)` bytes long where `m` is the size of the prime `p` + * in bits. + */ +#define PSA_ALG_FFDH ((psa_algorithm_t) 0x09010000) + +/** Whether the specified algorithm is a finite field Diffie-Hellman algorithm. + * + * This includes the raw finite field Diffie-Hellman algorithm as well as + * finite-field Diffie-Hellman followed by any supporter key derivation + * algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is a finite field Diffie-Hellman algorithm, 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key agreement algorithm identifier. + */ +#define PSA_ALG_IS_FFDH(alg) \ + (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_FFDH) + +/** The elliptic curve Diffie-Hellman (ECDH) key agreement algorithm. + * + * The shared secret produced by key agreement is the x-coordinate of + * the shared secret point. It is always `ceiling(m / 8)` bytes long where + * `m` is the bit size associated with the curve, i.e. the bit size of the + * order of the curve's coordinate field. When `m` is not a multiple of 8, + * the byte containing the most significant bit of the shared secret + * is padded with zero bits. The byte order is either little-endian + * or big-endian depending on the curve type. + * + * - For Montgomery curves (curve types `PSA_ECC_FAMILY_CURVEXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in little-endian byte order. + * The bit size is 448 for Curve448 and 255 for Curve25519. + * - For Weierstrass curves over prime fields (curve types + * `PSA_ECC_FAMILY_SECPXXX` and `PSA_ECC_FAMILY_BRAINPOOL_PXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m = ceiling(log_2(p))` for the field `F_p`. + * - For Weierstrass curves over binary fields (curve types + * `PSA_ECC_FAMILY_SECTXXX`), + * the shared secret is the x-coordinate of `d_A Q_B = d_B Q_A` + * in big-endian byte order. + * The bit size is `m` for the field `F_{2^m}`. + */ +#define PSA_ALG_ECDH ((psa_algorithm_t) 0x09020000) + +/** Whether the specified algorithm is an elliptic curve Diffie-Hellman + * algorithm. + * + * This includes the raw elliptic curve Diffie-Hellman algorithm as well as + * elliptic curve Diffie-Hellman followed by any supporter key derivation + * algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is an elliptic curve Diffie-Hellman algorithm, + * 0 otherwise. + * This macro may return either 0 or 1 if \c alg is not a supported + * key agreement algorithm identifier. + */ +#define PSA_ALG_IS_ECDH(alg) \ + (PSA_ALG_KEY_AGREEMENT_GET_BASE(alg) == PSA_ALG_ECDH) + +/** Whether the specified algorithm encoding is a wildcard. + * + * Wildcard values may only be used to set the usage algorithm field in + * a policy, not to perform an operation. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return 1 if \c alg is a wildcard algorithm encoding. + * \return 0 if \c alg is a non-wildcard algorithm encoding (suitable for + * an operation). + * \return This macro may return either 0 or 1 if \c alg is not a supported + * algorithm identifier. + */ +#define PSA_ALG_IS_WILDCARD(alg) \ + (PSA_ALG_IS_HASH_AND_SIGN(alg) ? \ + PSA_ALG_SIGN_GET_HASH(alg) == PSA_ALG_ANY_HASH : \ + PSA_ALG_IS_MAC(alg) ? \ + (alg & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ + PSA_ALG_IS_AEAD(alg) ? \ + (alg & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0 : \ + (alg) == PSA_ALG_ANY_HASH) + +/** Get the hash used by a composite algorithm. + * + * \param alg An algorithm identifier (value of type #psa_algorithm_t). + * + * \return The underlying hash algorithm if alg is a composite algorithm that + * uses a hash algorithm. + * + * \return \c 0 if alg is not a composite algorithm that uses a hash. + */ +#define PSA_ALG_GET_HASH(alg) \ + (((alg) & 0x000000ff) == 0 ? ((psa_algorithm_t) 0) : 0x02000000 | ((alg) & 0x000000ff)) + +/**@}*/ + +/** \defgroup key_lifetimes Key lifetimes + * @{ + */ + +/* Note that location and persistence level values are embedded in the + * persistent key store, as part of key metadata. As a consequence, they + * must not be changed (unless the storage format version changes). + */ + +/** The default lifetime for volatile keys. + * + * A volatile key only exists as long as the identifier to it is not destroyed. + * The key material is guaranteed to be erased on a power reset. + * + * A key with this lifetime is typically stored in the RAM area of the + * PSA Crypto subsystem. However this is an implementation choice. + * If an implementation stores data about the key in a non-volatile memory, + * it must release all the resources associated with the key and erase the + * key material if the calling application terminates. + */ +#define PSA_KEY_LIFETIME_VOLATILE ((psa_key_lifetime_t) 0x00000000) + +/** The default lifetime for persistent keys. + * + * A persistent key remains in storage until it is explicitly destroyed or + * until the corresponding storage area is wiped. This specification does + * not define any mechanism to wipe a storage area, but integrations may + * provide their own mechanism (for example to perform a factory reset, + * to prepare for device refurbishment, or to uninstall an application). + * + * This lifetime value is the default storage area for the calling + * application. Integrations of Mbed TLS may support other persistent lifetimes. + * See ::psa_key_lifetime_t for more information. + */ +#define PSA_KEY_LIFETIME_PERSISTENT ((psa_key_lifetime_t) 0x00000001) + +/** The persistence level of volatile keys. + * + * See ::psa_key_persistence_t for more information. + */ +#define PSA_KEY_PERSISTENCE_VOLATILE ((psa_key_persistence_t) 0x00) + +/** The default persistence level for persistent keys. + * + * See ::psa_key_persistence_t for more information. + */ +#define PSA_KEY_PERSISTENCE_DEFAULT ((psa_key_persistence_t) 0x01) + +/** A persistence level indicating that a key is never destroyed. + * + * See ::psa_key_persistence_t for more information. + */ +#define PSA_KEY_PERSISTENCE_READ_ONLY ((psa_key_persistence_t) 0xff) + +#define PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) \ + ((psa_key_persistence_t) ((lifetime) & 0x000000ff)) + +#define PSA_KEY_LIFETIME_GET_LOCATION(lifetime) \ + ((psa_key_location_t) ((lifetime) >> 8)) + +/** Whether a key lifetime indicates that the key is volatile. + * + * A volatile key is automatically destroyed by the implementation when + * the application instance terminates. In particular, a volatile key + * is automatically destroyed on a power reset of the device. + * + * A key that is not volatile is persistent. Persistent keys are + * preserved until the application explicitly destroys them or until an + * implementation-specific device management event occurs (for example, + * a factory reset). + * + * \param lifetime The lifetime value to query (value of type + * ::psa_key_lifetime_t). + * + * \return \c 1 if the key is volatile, otherwise \c 0. + */ +#define PSA_KEY_LIFETIME_IS_VOLATILE(lifetime) \ + (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ + PSA_KEY_PERSISTENCE_VOLATILE) + +/** Whether a key lifetime indicates that the key is read-only. + * + * Read-only keys cannot be created or destroyed through the PSA Crypto API. + * They must be created through platform-specific means that bypass the API. + * + * Some platforms may offer ways to destroy read-only keys. For example, + * consider a platform with multiple levels of privilege, where a + * low-privilege application can use a key but is not allowed to destroy + * it, and the platform exposes the key to the application with a read-only + * lifetime. High-privilege code can destroy the key even though the + * application sees the key as read-only. + * + * \param lifetime The lifetime value to query (value of type + * ::psa_key_lifetime_t). + * + * \return \c 1 if the key is read-only, otherwise \c 0. + */ +#define PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime) \ + (PSA_KEY_LIFETIME_GET_PERSISTENCE(lifetime) == \ + PSA_KEY_PERSISTENCE_READ_ONLY) + +/** Construct a lifetime from a persistence level and a location. + * + * \param persistence The persistence level + * (value of type ::psa_key_persistence_t). + * \param location The location indicator + * (value of type ::psa_key_location_t). + * + * \return The constructed lifetime value. + */ +#define PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION(persistence, location) \ + ((location) << 8 | (persistence)) + +/** The local storage area for persistent keys. + * + * This storage area is available on all systems that can store persistent + * keys without delegating the storage to a third-party cryptoprocessor. + * + * See ::psa_key_location_t for more information. + */ +#define PSA_KEY_LOCATION_LOCAL_STORAGE ((psa_key_location_t) 0x000000) + +#define PSA_KEY_LOCATION_VENDOR_FLAG ((psa_key_location_t) 0x800000) + +/* Note that key identifier values are embedded in the + * persistent key store, as part of key metadata. As a consequence, they + * must not be changed (unless the storage format version changes). + */ + +/** The null key identifier. + */ +/* *INDENT-OFF* (https://github.com/ARM-software/psa-arch-tests/issues/337) */ +#define PSA_KEY_ID_NULL ((psa_key_id_t)0) +/* *INDENT-ON* */ +/** The minimum value for a key identifier chosen by the application. + */ +#define PSA_KEY_ID_USER_MIN ((psa_key_id_t) 0x00000001) +/** The maximum value for a key identifier chosen by the application. + */ +#define PSA_KEY_ID_USER_MAX ((psa_key_id_t) 0x3fffffff) +/** The minimum value for a key identifier chosen by the implementation. + */ +#define PSA_KEY_ID_VENDOR_MIN ((psa_key_id_t) 0x40000000) +/** The maximum value for a key identifier chosen by the implementation. + */ +#define PSA_KEY_ID_VENDOR_MAX ((psa_key_id_t) 0x7fffffff) + + +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + +#define MBEDTLS_SVC_KEY_ID_INIT ((psa_key_id_t) 0) +#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) (id) +#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) (0) + +/** Utility to initialize a key identifier at runtime. + * + * \param unused Unused parameter. + * \param key_id Identifier of the key. + */ +static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( + unsigned int unused, psa_key_id_t key_id) +{ + (void) unused; + + return key_id; +} + +/** Compare two key identifiers. + * + * \param id1 First key identifier. + * \param id2 Second key identifier. + * + * \return Non-zero if the two key identifier are equal, zero otherwise. + */ +static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, + mbedtls_svc_key_id_t id2) +{ + return id1 == id2; +} + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) +{ + return key == 0; +} + +#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ + +#define MBEDTLS_SVC_KEY_ID_INIT ((mbedtls_svc_key_id_t){ 0, 0 }) +#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID(id) ((id).MBEDTLS_PRIVATE(key_id)) +#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(id) ((id).MBEDTLS_PRIVATE(owner)) + +/** Utility to initialize a key identifier at runtime. + * + * \param owner_id Identifier of the key owner. + * \param key_id Identifier of the key. + */ +static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( + mbedtls_key_owner_id_t owner_id, psa_key_id_t key_id) +{ + return (mbedtls_svc_key_id_t){ .MBEDTLS_PRIVATE(key_id) = key_id, + .MBEDTLS_PRIVATE(owner) = owner_id }; +} + +/** Compare two key identifiers. + * + * \param id1 First key identifier. + * \param id2 Second key identifier. + * + * \return Non-zero if the two key identifier are equal, zero otherwise. + */ +static inline int mbedtls_svc_key_id_equal(mbedtls_svc_key_id_t id1, + mbedtls_svc_key_id_t id2) +{ + return (id1.MBEDTLS_PRIVATE(key_id) == id2.MBEDTLS_PRIVATE(key_id)) && + mbedtls_key_owner_id_equal(id1.MBEDTLS_PRIVATE(owner), id2.MBEDTLS_PRIVATE(owner)); +} + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null(mbedtls_svc_key_id_t key) +{ + return key.MBEDTLS_PRIVATE(key_id) == 0; +} + +#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ + +/**@}*/ + +/** \defgroup policy Key policies + * @{ + */ + +/* Note that key usage flags are embedded in the + * persistent key store, as part of key metadata. As a consequence, they + * must not be changed (unless the storage format version changes). + */ + +/** Whether the key may be exported. + * + * A public key or the public part of a key pair may always be exported + * regardless of the value of this permission flag. + * + * If a key does not have export permission, implementations shall not + * allow the key to be exported in plain form from the cryptoprocessor, + * whether through psa_export_key() or through a proprietary interface. + * The key may however be exportable in a wrapped form, i.e. in a form + * where it is encrypted by another key. + */ +#define PSA_KEY_USAGE_EXPORT ((psa_key_usage_t) 0x00000001) + +/** Whether the key may be copied. + * + * This flag allows the use of psa_copy_key() to make a copy of the key + * with the same policy or a more restrictive policy. + * + * For lifetimes for which the key is located in a secure element which + * enforce the non-exportability of keys, copying a key outside the secure + * element also requires the usage flag #PSA_KEY_USAGE_EXPORT. + * Copying the key inside the secure element is permitted with just + * #PSA_KEY_USAGE_COPY if the secure element supports it. + * For keys with the lifetime #PSA_KEY_LIFETIME_VOLATILE or + * #PSA_KEY_LIFETIME_PERSISTENT, the usage flag #PSA_KEY_USAGE_COPY + * is sufficient to permit the copy. + */ +#define PSA_KEY_USAGE_COPY ((psa_key_usage_t) 0x00000002) + +/** Whether the key may be used to encrypt a message. + * + * This flag allows the key to be used for a symmetric encryption operation, + * for an AEAD encryption-and-authentication operation, + * or for an asymmetric encryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define PSA_KEY_USAGE_ENCRYPT ((psa_key_usage_t) 0x00000100) + +/** Whether the key may be used to decrypt a message. + * + * This flag allows the key to be used for a symmetric decryption operation, + * for an AEAD decryption-and-verification operation, + * or for an asymmetric decryption operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define PSA_KEY_USAGE_DECRYPT ((psa_key_usage_t) 0x00000200) + +/** Whether the key may be used to sign a message. + * + * This flag allows the key to be used for a MAC calculation operation or for + * an asymmetric message signature operation, if otherwise permitted by the + * key’s type and policy. + * + * For a key pair, this concerns the private key. + */ +#define PSA_KEY_USAGE_SIGN_MESSAGE ((psa_key_usage_t) 0x00000400) + +/** Whether the key may be used to verify a message. + * + * This flag allows the key to be used for a MAC verification operation or for + * an asymmetric message signature verification operation, if otherwise + * permitted by the key’s type and policy. + * + * For a key pair, this concerns the public key. + */ +#define PSA_KEY_USAGE_VERIFY_MESSAGE ((psa_key_usage_t) 0x00000800) + +/** Whether the key may be used to sign a message. + * + * This flag allows the key to be used for a MAC calculation operation + * or for an asymmetric signature operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the private key. + */ +#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t) 0x00001000) + +/** Whether the key may be used to verify a message signature. + * + * This flag allows the key to be used for a MAC verification operation + * or for an asymmetric signature verification operation, + * if otherwise permitted by the key's type and policy. + * + * For a key pair, this concerns the public key. + */ +#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t) 0x00002000) + +/** Whether the key may be used to derive other keys or produce a password + * hash. + * + * This flag allows the key to be used for a key derivation operation or for + * a key agreement operation, if otherwise permitted by the key's type and + * policy. + * + * If this flag is present on all keys used in calls to + * psa_key_derivation_input_key() for a key derivation operation, then it + * permits calling psa_key_derivation_output_bytes() or + * psa_key_derivation_output_key() at the end of the operation. + */ +#define PSA_KEY_USAGE_DERIVE ((psa_key_usage_t) 0x00004000) + +/** Whether the key may be used to verify the result of a key derivation, + * including password hashing. + * + * This flag allows the key to be used: + * + * This flag allows the key to be used in a key derivation operation, if + * otherwise permitted by the key's type and policy. + * + * If this flag is present on all keys used in calls to + * psa_key_derivation_input_key() for a key derivation operation, then it + * permits calling psa_key_derivation_verify_bytes() or + * psa_key_derivation_verify_key() at the end of the operation. + */ +#define PSA_KEY_USAGE_VERIFY_DERIVATION ((psa_key_usage_t) 0x00008000) + +/**@}*/ + +/** \defgroup derivation Key derivation + * @{ + */ + +/* Key input steps are not embedded in the persistent storage, so you can + * change them if needed: it's only an ABI change. */ + +/** A secret input for key derivation. + * + * This should be a key of type #PSA_KEY_TYPE_DERIVE + * (passed to psa_key_derivation_input_key()) + * or the shared secret resulting from a key agreement + * (obtained via psa_key_derivation_key_agreement()). + * + * The secret can also be a direct input (passed to + * key_derivation_input_bytes()). In this case, the derivation operation + * may not be used to derive keys: the operation will only allow + * psa_key_derivation_output_bytes(), + * psa_key_derivation_verify_bytes(), or + * psa_key_derivation_verify_key(), but not + * psa_key_derivation_output_key(). + */ +#define PSA_KEY_DERIVATION_INPUT_SECRET ((psa_key_derivation_step_t) 0x0101) + +/** A low-entropy secret input for password hashing / key stretching. + * + * This is usually a key of type #PSA_KEY_TYPE_PASSWORD (passed to + * psa_key_derivation_input_key()) or a direct input (passed to + * psa_key_derivation_input_bytes()) that is a password or passphrase. It can + * also be high-entropy secret such as a key of type #PSA_KEY_TYPE_DERIVE or + * the shared secret resulting from a key agreement. + * + * The secret can also be a direct input (passed to + * key_derivation_input_bytes()). In this case, the derivation operation + * may not be used to derive keys: the operation will only allow + * psa_key_derivation_output_bytes(), + * psa_key_derivation_verify_bytes(), or + * psa_key_derivation_verify_key(), but not + * psa_key_derivation_output_key(). + */ +#define PSA_KEY_DERIVATION_INPUT_PASSWORD ((psa_key_derivation_step_t) 0x0102) + +/** A high-entropy additional secret input for key derivation. + * + * This is typically the shared secret resulting from a key agreement obtained + * via `psa_key_derivation_key_agreement()`. It may alternatively be a key of + * type `PSA_KEY_TYPE_DERIVE` passed to `psa_key_derivation_input_key()`, or + * a direct input passed to `psa_key_derivation_input_bytes()`. + */ +#define PSA_KEY_DERIVATION_INPUT_OTHER_SECRET \ + ((psa_key_derivation_step_t) 0x0103) + +/** A label for key derivation. + * + * This should be a direct input. + * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. + */ +#define PSA_KEY_DERIVATION_INPUT_LABEL ((psa_key_derivation_step_t) 0x0201) + +/** A salt for key derivation. + * + * This should be a direct input. + * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA or + * #PSA_KEY_TYPE_PEPPER. + */ +#define PSA_KEY_DERIVATION_INPUT_SALT ((psa_key_derivation_step_t) 0x0202) + +/** An information string for key derivation. + * + * This should be a direct input. + * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. + */ +#define PSA_KEY_DERIVATION_INPUT_INFO ((psa_key_derivation_step_t) 0x0203) + +/** A seed for key derivation. + * + * This should be a direct input. + * It can also be a key of type #PSA_KEY_TYPE_RAW_DATA. + */ +#define PSA_KEY_DERIVATION_INPUT_SEED ((psa_key_derivation_step_t) 0x0204) + +/** A cost parameter for password hashing / key stretching. + * + * This must be a direct input, passed to psa_key_derivation_input_integer(). + */ +#define PSA_KEY_DERIVATION_INPUT_COST ((psa_key_derivation_step_t) 0x0205) + +/**@}*/ + +/** \defgroup helper_macros Helper macros + * @{ + */ + +/* Helper macros */ + +/** Check if two AEAD algorithm identifiers refer to the same AEAD algorithm + * regardless of the tag length they encode. + * + * \param aead_alg_1 An AEAD algorithm identifier. + * \param aead_alg_2 An AEAD algorithm identifier. + * + * \return 1 if both identifiers refer to the same AEAD algorithm, + * 0 otherwise. + * Unspecified if neither \p aead_alg_1 nor \p aead_alg_2 are + * a supported AEAD algorithm. + */ +#define MBEDTLS_PSA_ALG_AEAD_EQUAL(aead_alg_1, aead_alg_2) \ + (!(((aead_alg_1) ^ (aead_alg_2)) & \ + ~(PSA_ALG_AEAD_TAG_LENGTH_MASK | PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG))) + +/**@}*/ + +/**@}*/ + +/** \defgroup interruptible Interruptible operations + * @{ + */ + +/** Maximum value for use with \c psa_interruptible_set_max_ops() to determine + * the maximum number of ops allowed to be executed by an interruptible + * function in a single call. + */ +#define PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED UINT32_MAX + +/**@}*/ + +#endif /* PSA_CRYPTO_VALUES_H */ + +#endif /* SL_TRUSTZONE_NONSECURE */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/alignment.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/alignment.h index ab15986..b0ceec7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/alignment.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/alignment.h @@ -1,521 +1,521 @@ -/** - * \file alignment.h - * - * \brief Utility code for dealing with unaligned memory accesses - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_LIBRARY_ALIGNMENT_H -#define MBEDTLS_LIBRARY_ALIGNMENT_H - -#include -#include -#include - -/* - * Define MBEDTLS_EFFICIENT_UNALIGNED_ACCESS for architectures where unaligned memory - * accesses are known to be efficient. - * - * All functions defined here will behave correctly regardless, but might be less - * efficient when this is not defined. - */ -#if defined(__ARM_FEATURE_UNALIGNED) \ - || defined(__i386__) || defined(__amd64__) || defined(__x86_64__) -/* - * __ARM_FEATURE_UNALIGNED is defined where appropriate by armcc, gcc 7, clang 9 - * (and later versions) for Arm v7 and later; all x86 platforms should have - * efficient unaligned access. - */ -#define MBEDTLS_EFFICIENT_UNALIGNED_ACCESS -#endif - -/** - * Read the unsigned 16 bits integer from the given address, which need not - * be aligned. - * - * \param p pointer to 2 bytes of data - * \return Data at the given address - */ -inline uint16_t mbedtls_get_unaligned_uint16(const void *p) -{ - uint16_t r; - memcpy(&r, p, sizeof(r)); - return r; -} - -/** - * Write the unsigned 16 bits integer to the given address, which need not - * be aligned. - * - * \param p pointer to 2 bytes of data - * \param x data to write - */ -inline void mbedtls_put_unaligned_uint16(void *p, uint16_t x) -{ - memcpy(p, &x, sizeof(x)); -} - -/** - * Read the unsigned 32 bits integer from the given address, which need not - * be aligned. - * - * \param p pointer to 4 bytes of data - * \return Data at the given address - */ -inline uint32_t mbedtls_get_unaligned_uint32(const void *p) -{ - uint32_t r; - memcpy(&r, p, sizeof(r)); - return r; -} - -/** - * Write the unsigned 32 bits integer to the given address, which need not - * be aligned. - * - * \param p pointer to 4 bytes of data - * \param x data to write - */ -inline void mbedtls_put_unaligned_uint32(void *p, uint32_t x) -{ - memcpy(p, &x, sizeof(x)); -} - -/** - * Read the unsigned 64 bits integer from the given address, which need not - * be aligned. - * - * \param p pointer to 8 bytes of data - * \return Data at the given address - */ -inline uint64_t mbedtls_get_unaligned_uint64(const void *p) -{ - uint64_t r; - memcpy(&r, p, sizeof(r)); - return r; -} - -/** - * Write the unsigned 64 bits integer to the given address, which need not - * be aligned. - * - * \param p pointer to 8 bytes of data - * \param x data to write - */ -inline void mbedtls_put_unaligned_uint64(void *p, uint64_t x) -{ - memcpy(p, &x, sizeof(x)); -} - -/** Byte Reading Macros - * - * Given a multi-byte integer \p x, MBEDTLS_BYTE_n retrieves the n-th - * byte from x, where byte 0 is the least significant byte. - */ -#define MBEDTLS_BYTE_0(x) ((uint8_t) ((x) & 0xff)) -#define MBEDTLS_BYTE_1(x) ((uint8_t) (((x) >> 8) & 0xff)) -#define MBEDTLS_BYTE_2(x) ((uint8_t) (((x) >> 16) & 0xff)) -#define MBEDTLS_BYTE_3(x) ((uint8_t) (((x) >> 24) & 0xff)) -#define MBEDTLS_BYTE_4(x) ((uint8_t) (((x) >> 32) & 0xff)) -#define MBEDTLS_BYTE_5(x) ((uint8_t) (((x) >> 40) & 0xff)) -#define MBEDTLS_BYTE_6(x) ((uint8_t) (((x) >> 48) & 0xff)) -#define MBEDTLS_BYTE_7(x) ((uint8_t) (((x) >> 56) & 0xff)) - -/* - * Detect GCC built-in byteswap routines - */ -#if defined(__GNUC__) && defined(__GNUC_PREREQ) -#if __GNUC_PREREQ(4, 8) -#define MBEDTLS_BSWAP16 __builtin_bswap16 -#endif /* __GNUC_PREREQ(4,8) */ -#if __GNUC_PREREQ(4, 3) -#define MBEDTLS_BSWAP32 __builtin_bswap32 -#define MBEDTLS_BSWAP64 __builtin_bswap64 -#endif /* __GNUC_PREREQ(4,3) */ -#endif /* defined(__GNUC__) && defined(__GNUC_PREREQ) */ - -/* - * Detect Clang built-in byteswap routines - */ -#if defined(__clang__) && defined(__has_builtin) -#if __has_builtin(__builtin_bswap16) && !defined(MBEDTLS_BSWAP16) -#define MBEDTLS_BSWAP16 __builtin_bswap16 -#endif /* __has_builtin(__builtin_bswap16) */ -#if __has_builtin(__builtin_bswap32) && !defined(MBEDTLS_BSWAP32) -#define MBEDTLS_BSWAP32 __builtin_bswap32 -#endif /* __has_builtin(__builtin_bswap32) */ -#if __has_builtin(__builtin_bswap64) && !defined(MBEDTLS_BSWAP64) -#define MBEDTLS_BSWAP64 __builtin_bswap64 -#endif /* __has_builtin(__builtin_bswap64) */ -#endif /* defined(__clang__) && defined(__has_builtin) */ - -/* - * Detect MSVC built-in byteswap routines - */ -#if defined(_MSC_VER) -#if !defined(MBEDTLS_BSWAP16) -#define MBEDTLS_BSWAP16 _byteswap_ushort -#endif -#if !defined(MBEDTLS_BSWAP32) -#define MBEDTLS_BSWAP32 _byteswap_ulong -#endif -#if !defined(MBEDTLS_BSWAP64) -#define MBEDTLS_BSWAP64 _byteswap_uint64 -#endif -#endif /* defined(_MSC_VER) */ - -/* Detect armcc built-in byteswap routine */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 410000) && !defined(MBEDTLS_BSWAP32) -#if defined(__ARM_ACLE) /* ARM Compiler 6 - earlier versions don't need a header */ -#include -#endif -#define MBEDTLS_BSWAP32 __rev -#endif - -/* - * Where compiler built-ins are not present, fall back to C code that the - * compiler may be able to detect and transform into the relevant bswap or - * similar instruction. - */ -#if !defined(MBEDTLS_BSWAP16) -static inline uint16_t mbedtls_bswap16(uint16_t x) -{ - return - (x & 0x00ff) << 8 | - (x & 0xff00) >> 8; -} -#define MBEDTLS_BSWAP16 mbedtls_bswap16 -#endif /* !defined(MBEDTLS_BSWAP16) */ - -#if !defined(MBEDTLS_BSWAP32) -static inline uint32_t mbedtls_bswap32(uint32_t x) -{ - return - (x & 0x000000ff) << 24 | - (x & 0x0000ff00) << 8 | - (x & 0x00ff0000) >> 8 | - (x & 0xff000000) >> 24; -} -#define MBEDTLS_BSWAP32 mbedtls_bswap32 -#endif /* !defined(MBEDTLS_BSWAP32) */ - -#if !defined(MBEDTLS_BSWAP64) -static inline uint64_t mbedtls_bswap64(uint64_t x) -{ - return - (x & 0x00000000000000ffULL) << 56 | - (x & 0x000000000000ff00ULL) << 40 | - (x & 0x0000000000ff0000ULL) << 24 | - (x & 0x00000000ff000000ULL) << 8 | - (x & 0x000000ff00000000ULL) >> 8 | - (x & 0x0000ff0000000000ULL) >> 24 | - (x & 0x00ff000000000000ULL) >> 40 | - (x & 0xff00000000000000ULL) >> 56; -} -#define MBEDTLS_BSWAP64 mbedtls_bswap64 -#endif /* !defined(MBEDTLS_BSWAP64) */ - -#if !defined(__BYTE_ORDER__) -static const uint16_t mbedtls_byte_order_detector = { 0x100 }; -#define MBEDTLS_IS_BIG_ENDIAN (*((unsigned char *) (&mbedtls_byte_order_detector)) == 0x01) -#else -#define MBEDTLS_IS_BIG_ENDIAN ((__BYTE_ORDER__) == (__ORDER_BIG_ENDIAN__)) -#endif /* !defined(__BYTE_ORDER__) */ - -/** - * Get the unsigned 32 bits integer corresponding to four bytes in - * big-endian order (MSB first). - * - * \param data Base address of the memory to get the four bytes from. - * \param offset Offset from \p data of the first and most significant - * byte of the four bytes to build the 32 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT32_BE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? mbedtls_get_unaligned_uint32((data) + (offset)) \ - : MBEDTLS_BSWAP32(mbedtls_get_unaligned_uint32((data) + (offset))) \ - ) - -/** - * Put in memory a 32 bits unsigned integer in big-endian order. - * - * \param n 32 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 32 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the most significant - * byte of the 32 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT32_BE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint32((data) + (offset), (uint32_t) (n)); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint32((data) + (offset), MBEDTLS_BSWAP32((uint32_t) (n))); \ - } \ - } - -/** - * Get the unsigned 32 bits integer corresponding to four bytes in - * little-endian order (LSB first). - * - * \param data Base address of the memory to get the four bytes from. - * \param offset Offset from \p data of the first and least significant - * byte of the four bytes to build the 32 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT32_LE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? MBEDTLS_BSWAP32(mbedtls_get_unaligned_uint32((data) + (offset))) \ - : mbedtls_get_unaligned_uint32((data) + (offset)) \ - ) - - -/** - * Put in memory a 32 bits unsigned integer in little-endian order. - * - * \param n 32 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 32 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the least significant - * byte of the 32 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT32_LE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint32((data) + (offset), MBEDTLS_BSWAP32((uint32_t) (n))); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint32((data) + (offset), ((uint32_t) (n))); \ - } \ - } - -/** - * Get the unsigned 16 bits integer corresponding to two bytes in - * little-endian order (LSB first). - * - * \param data Base address of the memory to get the two bytes from. - * \param offset Offset from \p data of the first and least significant - * byte of the two bytes to build the 16 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT16_LE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? MBEDTLS_BSWAP16(mbedtls_get_unaligned_uint16((data) + (offset))) \ - : mbedtls_get_unaligned_uint16((data) + (offset)) \ - ) - -/** - * Put in memory a 16 bits unsigned integer in little-endian order. - * - * \param n 16 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 16 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the least significant - * byte of the 16 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT16_LE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint16((data) + (offset), MBEDTLS_BSWAP16((uint16_t) (n))); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint16((data) + (offset), (uint16_t) (n)); \ - } \ - } - -/** - * Get the unsigned 16 bits integer corresponding to two bytes in - * big-endian order (MSB first). - * - * \param data Base address of the memory to get the two bytes from. - * \param offset Offset from \p data of the first and most significant - * byte of the two bytes to build the 16 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT16_BE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? mbedtls_get_unaligned_uint16((data) + (offset)) \ - : MBEDTLS_BSWAP16(mbedtls_get_unaligned_uint16((data) + (offset))) \ - ) - -/** - * Put in memory a 16 bits unsigned integer in big-endian order. - * - * \param n 16 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 16 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the most significant - * byte of the 16 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT16_BE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint16((data) + (offset), (uint16_t) (n)); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint16((data) + (offset), MBEDTLS_BSWAP16((uint16_t) (n))); \ - } \ - } - -/** - * Get the unsigned 24 bits integer corresponding to three bytes in - * big-endian order (MSB first). - * - * \param data Base address of the memory to get the three bytes from. - * \param offset Offset from \p data of the first and most significant - * byte of the three bytes to build the 24 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT24_BE(data, offset) \ - ( \ - ((uint32_t) (data)[(offset)] << 16) \ - | ((uint32_t) (data)[(offset) + 1] << 8) \ - | ((uint32_t) (data)[(offset) + 2]) \ - ) - -/** - * Put in memory a 24 bits unsigned integer in big-endian order. - * - * \param n 24 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 24 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the most significant - * byte of the 24 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT24_BE(n, data, offset) \ - { \ - (data)[(offset)] = MBEDTLS_BYTE_2(n); \ - (data)[(offset) + 1] = MBEDTLS_BYTE_1(n); \ - (data)[(offset) + 2] = MBEDTLS_BYTE_0(n); \ - } - -/** - * Get the unsigned 24 bits integer corresponding to three bytes in - * little-endian order (LSB first). - * - * \param data Base address of the memory to get the three bytes from. - * \param offset Offset from \p data of the first and least significant - * byte of the three bytes to build the 24 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT24_LE(data, offset) \ - ( \ - ((uint32_t) (data)[(offset)]) \ - | ((uint32_t) (data)[(offset) + 1] << 8) \ - | ((uint32_t) (data)[(offset) + 2] << 16) \ - ) - -/** - * Put in memory a 24 bits unsigned integer in little-endian order. - * - * \param n 24 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 24 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the least significant - * byte of the 24 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT24_LE(n, data, offset) \ - { \ - (data)[(offset)] = MBEDTLS_BYTE_0(n); \ - (data)[(offset) + 1] = MBEDTLS_BYTE_1(n); \ - (data)[(offset) + 2] = MBEDTLS_BYTE_2(n); \ - } - -/** - * Get the unsigned 64 bits integer corresponding to eight bytes in - * big-endian order (MSB first). - * - * \param data Base address of the memory to get the eight bytes from. - * \param offset Offset from \p data of the first and most significant - * byte of the eight bytes to build the 64 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT64_BE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? mbedtls_get_unaligned_uint64((data) + (offset)) \ - : MBEDTLS_BSWAP64(mbedtls_get_unaligned_uint64((data) + (offset))) \ - ) - -/** - * Put in memory a 64 bits unsigned integer in big-endian order. - * - * \param n 64 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 64 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the most significant - * byte of the 64 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT64_BE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint64((data) + (offset), (uint64_t) (n)); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint64((data) + (offset), MBEDTLS_BSWAP64((uint64_t) (n))); \ - } \ - } - -/** - * Get the unsigned 64 bits integer corresponding to eight bytes in - * little-endian order (LSB first). - * - * \param data Base address of the memory to get the eight bytes from. - * \param offset Offset from \p data of the first and least significant - * byte of the eight bytes to build the 64 bits unsigned - * integer from. - */ -#define MBEDTLS_GET_UINT64_LE(data, offset) \ - ((MBEDTLS_IS_BIG_ENDIAN) \ - ? MBEDTLS_BSWAP64(mbedtls_get_unaligned_uint64((data) + (offset))) \ - : mbedtls_get_unaligned_uint64((data) + (offset)) \ - ) - -/** - * Put in memory a 64 bits unsigned integer in little-endian order. - * - * \param n 64 bits unsigned integer to put in memory. - * \param data Base address of the memory where to put the 64 - * bits unsigned integer in. - * \param offset Offset from \p data where to put the least significant - * byte of the 64 bits unsigned integer \p n. - */ -#define MBEDTLS_PUT_UINT64_LE(n, data, offset) \ - { \ - if (MBEDTLS_IS_BIG_ENDIAN) \ - { \ - mbedtls_put_unaligned_uint64((data) + (offset), MBEDTLS_BSWAP64((uint64_t) (n))); \ - } \ - else \ - { \ - mbedtls_put_unaligned_uint64((data) + (offset), (uint64_t) (n)); \ - } \ - } - -#endif /* MBEDTLS_LIBRARY_ALIGNMENT_H */ +/** + * \file alignment.h + * + * \brief Utility code for dealing with unaligned memory accesses + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_LIBRARY_ALIGNMENT_H +#define MBEDTLS_LIBRARY_ALIGNMENT_H + +#include +#include +#include + +/* + * Define MBEDTLS_EFFICIENT_UNALIGNED_ACCESS for architectures where unaligned memory + * accesses are known to be efficient. + * + * All functions defined here will behave correctly regardless, but might be less + * efficient when this is not defined. + */ +#if defined(__ARM_FEATURE_UNALIGNED) \ + || defined(__i386__) || defined(__amd64__) || defined(__x86_64__) +/* + * __ARM_FEATURE_UNALIGNED is defined where appropriate by armcc, gcc 7, clang 9 + * (and later versions) for Arm v7 and later; all x86 platforms should have + * efficient unaligned access. + */ +#define MBEDTLS_EFFICIENT_UNALIGNED_ACCESS +#endif + +/** + * Read the unsigned 16 bits integer from the given address, which need not + * be aligned. + * + * \param p pointer to 2 bytes of data + * \return Data at the given address + */ +inline uint16_t mbedtls_get_unaligned_uint16(const void *p) +{ + uint16_t r; + memcpy(&r, p, sizeof(r)); + return r; +} + +/** + * Write the unsigned 16 bits integer to the given address, which need not + * be aligned. + * + * \param p pointer to 2 bytes of data + * \param x data to write + */ +inline void mbedtls_put_unaligned_uint16(void *p, uint16_t x) +{ + memcpy(p, &x, sizeof(x)); +} + +/** + * Read the unsigned 32 bits integer from the given address, which need not + * be aligned. + * + * \param p pointer to 4 bytes of data + * \return Data at the given address + */ +inline uint32_t mbedtls_get_unaligned_uint32(const void *p) +{ + uint32_t r; + memcpy(&r, p, sizeof(r)); + return r; +} + +/** + * Write the unsigned 32 bits integer to the given address, which need not + * be aligned. + * + * \param p pointer to 4 bytes of data + * \param x data to write + */ +inline void mbedtls_put_unaligned_uint32(void *p, uint32_t x) +{ + memcpy(p, &x, sizeof(x)); +} + +/** + * Read the unsigned 64 bits integer from the given address, which need not + * be aligned. + * + * \param p pointer to 8 bytes of data + * \return Data at the given address + */ +inline uint64_t mbedtls_get_unaligned_uint64(const void *p) +{ + uint64_t r; + memcpy(&r, p, sizeof(r)); + return r; +} + +/** + * Write the unsigned 64 bits integer to the given address, which need not + * be aligned. + * + * \param p pointer to 8 bytes of data + * \param x data to write + */ +inline void mbedtls_put_unaligned_uint64(void *p, uint64_t x) +{ + memcpy(p, &x, sizeof(x)); +} + +/** Byte Reading Macros + * + * Given a multi-byte integer \p x, MBEDTLS_BYTE_n retrieves the n-th + * byte from x, where byte 0 is the least significant byte. + */ +#define MBEDTLS_BYTE_0(x) ((uint8_t) ((x) & 0xff)) +#define MBEDTLS_BYTE_1(x) ((uint8_t) (((x) >> 8) & 0xff)) +#define MBEDTLS_BYTE_2(x) ((uint8_t) (((x) >> 16) & 0xff)) +#define MBEDTLS_BYTE_3(x) ((uint8_t) (((x) >> 24) & 0xff)) +#define MBEDTLS_BYTE_4(x) ((uint8_t) (((x) >> 32) & 0xff)) +#define MBEDTLS_BYTE_5(x) ((uint8_t) (((x) >> 40) & 0xff)) +#define MBEDTLS_BYTE_6(x) ((uint8_t) (((x) >> 48) & 0xff)) +#define MBEDTLS_BYTE_7(x) ((uint8_t) (((x) >> 56) & 0xff)) + +/* + * Detect GCC built-in byteswap routines + */ +#if defined(__GNUC__) && defined(__GNUC_PREREQ) +#if __GNUC_PREREQ(4, 8) +#define MBEDTLS_BSWAP16 __builtin_bswap16 +#endif /* __GNUC_PREREQ(4,8) */ +#if __GNUC_PREREQ(4, 3) +#define MBEDTLS_BSWAP32 __builtin_bswap32 +#define MBEDTLS_BSWAP64 __builtin_bswap64 +#endif /* __GNUC_PREREQ(4,3) */ +#endif /* defined(__GNUC__) && defined(__GNUC_PREREQ) */ + +/* + * Detect Clang built-in byteswap routines + */ +#if defined(__clang__) && defined(__has_builtin) +#if __has_builtin(__builtin_bswap16) && !defined(MBEDTLS_BSWAP16) +#define MBEDTLS_BSWAP16 __builtin_bswap16 +#endif /* __has_builtin(__builtin_bswap16) */ +#if __has_builtin(__builtin_bswap32) && !defined(MBEDTLS_BSWAP32) +#define MBEDTLS_BSWAP32 __builtin_bswap32 +#endif /* __has_builtin(__builtin_bswap32) */ +#if __has_builtin(__builtin_bswap64) && !defined(MBEDTLS_BSWAP64) +#define MBEDTLS_BSWAP64 __builtin_bswap64 +#endif /* __has_builtin(__builtin_bswap64) */ +#endif /* defined(__clang__) && defined(__has_builtin) */ + +/* + * Detect MSVC built-in byteswap routines + */ +#if defined(_MSC_VER) +#if !defined(MBEDTLS_BSWAP16) +#define MBEDTLS_BSWAP16 _byteswap_ushort +#endif +#if !defined(MBEDTLS_BSWAP32) +#define MBEDTLS_BSWAP32 _byteswap_ulong +#endif +#if !defined(MBEDTLS_BSWAP64) +#define MBEDTLS_BSWAP64 _byteswap_uint64 +#endif +#endif /* defined(_MSC_VER) */ + +/* Detect armcc built-in byteswap routine */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 410000) && !defined(MBEDTLS_BSWAP32) +#if defined(__ARM_ACLE) /* ARM Compiler 6 - earlier versions don't need a header */ +#include +#endif +#define MBEDTLS_BSWAP32 __rev +#endif + +/* + * Where compiler built-ins are not present, fall back to C code that the + * compiler may be able to detect and transform into the relevant bswap or + * similar instruction. + */ +#if !defined(MBEDTLS_BSWAP16) +static inline uint16_t mbedtls_bswap16(uint16_t x) +{ + return + (x & 0x00ff) << 8 | + (x & 0xff00) >> 8; +} +#define MBEDTLS_BSWAP16 mbedtls_bswap16 +#endif /* !defined(MBEDTLS_BSWAP16) */ + +#if !defined(MBEDTLS_BSWAP32) +static inline uint32_t mbedtls_bswap32(uint32_t x) +{ + return + (x & 0x000000ff) << 24 | + (x & 0x0000ff00) << 8 | + (x & 0x00ff0000) >> 8 | + (x & 0xff000000) >> 24; +} +#define MBEDTLS_BSWAP32 mbedtls_bswap32 +#endif /* !defined(MBEDTLS_BSWAP32) */ + +#if !defined(MBEDTLS_BSWAP64) +static inline uint64_t mbedtls_bswap64(uint64_t x) +{ + return + (x & 0x00000000000000ffULL) << 56 | + (x & 0x000000000000ff00ULL) << 40 | + (x & 0x0000000000ff0000ULL) << 24 | + (x & 0x00000000ff000000ULL) << 8 | + (x & 0x000000ff00000000ULL) >> 8 | + (x & 0x0000ff0000000000ULL) >> 24 | + (x & 0x00ff000000000000ULL) >> 40 | + (x & 0xff00000000000000ULL) >> 56; +} +#define MBEDTLS_BSWAP64 mbedtls_bswap64 +#endif /* !defined(MBEDTLS_BSWAP64) */ + +#if !defined(__BYTE_ORDER__) +static const uint16_t mbedtls_byte_order_detector = { 0x100 }; +#define MBEDTLS_IS_BIG_ENDIAN (*((unsigned char *) (&mbedtls_byte_order_detector)) == 0x01) +#else +#define MBEDTLS_IS_BIG_ENDIAN ((__BYTE_ORDER__) == (__ORDER_BIG_ENDIAN__)) +#endif /* !defined(__BYTE_ORDER__) */ + +/** + * Get the unsigned 32 bits integer corresponding to four bytes in + * big-endian order (MSB first). + * + * \param data Base address of the memory to get the four bytes from. + * \param offset Offset from \p data of the first and most significant + * byte of the four bytes to build the 32 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT32_BE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? mbedtls_get_unaligned_uint32((data) + (offset)) \ + : MBEDTLS_BSWAP32(mbedtls_get_unaligned_uint32((data) + (offset))) \ + ) + +/** + * Put in memory a 32 bits unsigned integer in big-endian order. + * + * \param n 32 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 32 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the most significant + * byte of the 32 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT32_BE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint32((data) + (offset), (uint32_t) (n)); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint32((data) + (offset), MBEDTLS_BSWAP32((uint32_t) (n))); \ + } \ + } + +/** + * Get the unsigned 32 bits integer corresponding to four bytes in + * little-endian order (LSB first). + * + * \param data Base address of the memory to get the four bytes from. + * \param offset Offset from \p data of the first and least significant + * byte of the four bytes to build the 32 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT32_LE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? MBEDTLS_BSWAP32(mbedtls_get_unaligned_uint32((data) + (offset))) \ + : mbedtls_get_unaligned_uint32((data) + (offset)) \ + ) + + +/** + * Put in memory a 32 bits unsigned integer in little-endian order. + * + * \param n 32 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 32 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the least significant + * byte of the 32 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT32_LE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint32((data) + (offset), MBEDTLS_BSWAP32((uint32_t) (n))); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint32((data) + (offset), ((uint32_t) (n))); \ + } \ + } + +/** + * Get the unsigned 16 bits integer corresponding to two bytes in + * little-endian order (LSB first). + * + * \param data Base address of the memory to get the two bytes from. + * \param offset Offset from \p data of the first and least significant + * byte of the two bytes to build the 16 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT16_LE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? MBEDTLS_BSWAP16(mbedtls_get_unaligned_uint16((data) + (offset))) \ + : mbedtls_get_unaligned_uint16((data) + (offset)) \ + ) + +/** + * Put in memory a 16 bits unsigned integer in little-endian order. + * + * \param n 16 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 16 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the least significant + * byte of the 16 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT16_LE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint16((data) + (offset), MBEDTLS_BSWAP16((uint16_t) (n))); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint16((data) + (offset), (uint16_t) (n)); \ + } \ + } + +/** + * Get the unsigned 16 bits integer corresponding to two bytes in + * big-endian order (MSB first). + * + * \param data Base address of the memory to get the two bytes from. + * \param offset Offset from \p data of the first and most significant + * byte of the two bytes to build the 16 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT16_BE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? mbedtls_get_unaligned_uint16((data) + (offset)) \ + : MBEDTLS_BSWAP16(mbedtls_get_unaligned_uint16((data) + (offset))) \ + ) + +/** + * Put in memory a 16 bits unsigned integer in big-endian order. + * + * \param n 16 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 16 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the most significant + * byte of the 16 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT16_BE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint16((data) + (offset), (uint16_t) (n)); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint16((data) + (offset), MBEDTLS_BSWAP16((uint16_t) (n))); \ + } \ + } + +/** + * Get the unsigned 24 bits integer corresponding to three bytes in + * big-endian order (MSB first). + * + * \param data Base address of the memory to get the three bytes from. + * \param offset Offset from \p data of the first and most significant + * byte of the three bytes to build the 24 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT24_BE(data, offset) \ + ( \ + ((uint32_t) (data)[(offset)] << 16) \ + | ((uint32_t) (data)[(offset) + 1] << 8) \ + | ((uint32_t) (data)[(offset) + 2]) \ + ) + +/** + * Put in memory a 24 bits unsigned integer in big-endian order. + * + * \param n 24 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 24 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the most significant + * byte of the 24 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT24_BE(n, data, offset) \ + { \ + (data)[(offset)] = MBEDTLS_BYTE_2(n); \ + (data)[(offset) + 1] = MBEDTLS_BYTE_1(n); \ + (data)[(offset) + 2] = MBEDTLS_BYTE_0(n); \ + } + +/** + * Get the unsigned 24 bits integer corresponding to three bytes in + * little-endian order (LSB first). + * + * \param data Base address of the memory to get the three bytes from. + * \param offset Offset from \p data of the first and least significant + * byte of the three bytes to build the 24 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT24_LE(data, offset) \ + ( \ + ((uint32_t) (data)[(offset)]) \ + | ((uint32_t) (data)[(offset) + 1] << 8) \ + | ((uint32_t) (data)[(offset) + 2] << 16) \ + ) + +/** + * Put in memory a 24 bits unsigned integer in little-endian order. + * + * \param n 24 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 24 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the least significant + * byte of the 24 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT24_LE(n, data, offset) \ + { \ + (data)[(offset)] = MBEDTLS_BYTE_0(n); \ + (data)[(offset) + 1] = MBEDTLS_BYTE_1(n); \ + (data)[(offset) + 2] = MBEDTLS_BYTE_2(n); \ + } + +/** + * Get the unsigned 64 bits integer corresponding to eight bytes in + * big-endian order (MSB first). + * + * \param data Base address of the memory to get the eight bytes from. + * \param offset Offset from \p data of the first and most significant + * byte of the eight bytes to build the 64 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT64_BE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? mbedtls_get_unaligned_uint64((data) + (offset)) \ + : MBEDTLS_BSWAP64(mbedtls_get_unaligned_uint64((data) + (offset))) \ + ) + +/** + * Put in memory a 64 bits unsigned integer in big-endian order. + * + * \param n 64 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 64 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the most significant + * byte of the 64 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT64_BE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint64((data) + (offset), (uint64_t) (n)); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint64((data) + (offset), MBEDTLS_BSWAP64((uint64_t) (n))); \ + } \ + } + +/** + * Get the unsigned 64 bits integer corresponding to eight bytes in + * little-endian order (LSB first). + * + * \param data Base address of the memory to get the eight bytes from. + * \param offset Offset from \p data of the first and least significant + * byte of the eight bytes to build the 64 bits unsigned + * integer from. + */ +#define MBEDTLS_GET_UINT64_LE(data, offset) \ + ((MBEDTLS_IS_BIG_ENDIAN) \ + ? MBEDTLS_BSWAP64(mbedtls_get_unaligned_uint64((data) + (offset))) \ + : mbedtls_get_unaligned_uint64((data) + (offset)) \ + ) + +/** + * Put in memory a 64 bits unsigned integer in little-endian order. + * + * \param n 64 bits unsigned integer to put in memory. + * \param data Base address of the memory where to put the 64 + * bits unsigned integer in. + * \param offset Offset from \p data where to put the least significant + * byte of the 64 bits unsigned integer \p n. + */ +#define MBEDTLS_PUT_UINT64_LE(n, data, offset) \ + { \ + if (MBEDTLS_IS_BIG_ENDIAN) \ + { \ + mbedtls_put_unaligned_uint64((data) + (offset), MBEDTLS_BSWAP64((uint64_t) (n))); \ + } \ + else \ + { \ + mbedtls_put_unaligned_uint64((data) + (offset), (uint64_t) (n)); \ + } \ + } + +#endif /* MBEDTLS_LIBRARY_ALIGNMENT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/base64_internal.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/base64_internal.h index f9f56d7..627fed9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/base64_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/base64_internal.h @@ -1,57 +1,57 @@ -/** - * \file base64_internal.h - * - * \brief RFC 1521 base64 encoding/decoding: interfaces for invasive testing - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BASE64_INTERNAL -#define MBEDTLS_BASE64_INTERNAL - -#include "common.h" - -#if defined(MBEDTLS_TEST_HOOKS) - -/** Given a value in the range 0..63, return the corresponding Base64 digit. - * - * The implementation assumes that letters are consecutive (e.g. ASCII - * but not EBCDIC). - * - * \param value A value in the range 0..63. - * - * \return A base64 digit converted from \p value. - */ -unsigned char mbedtls_ct_base64_enc_char(unsigned char value); - -/** Given a Base64 digit, return its value. - * - * If c is not a Base64 digit ('A'..'Z', 'a'..'z', '0'..'9', '+' or '/'), - * return -1. - * - * The implementation assumes that letters are consecutive (e.g. ASCII - * but not EBCDIC). - * - * \param c A base64 digit. - * - * \return The value of the base64 digit \p c. - */ -signed char mbedtls_ct_base64_dec_value(unsigned char c); - -#endif /* MBEDTLS_TEST_HOOKS */ - -#endif /* MBEDTLS_BASE64_INTERNAL */ +/** + * \file base64_internal.h + * + * \brief RFC 1521 base64 encoding/decoding: interfaces for invasive testing + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BASE64_INTERNAL +#define MBEDTLS_BASE64_INTERNAL + +#include "common.h" + +#if defined(MBEDTLS_TEST_HOOKS) + +/** Given a value in the range 0..63, return the corresponding Base64 digit. + * + * The implementation assumes that letters are consecutive (e.g. ASCII + * but not EBCDIC). + * + * \param value A value in the range 0..63. + * + * \return A base64 digit converted from \p value. + */ +unsigned char mbedtls_ct_base64_enc_char(unsigned char value); + +/** Given a Base64 digit, return its value. + * + * If c is not a Base64 digit ('A'..'Z', 'a'..'z', '0'..'9', '+' or '/'), + * return -1. + * + * The implementation assumes that letters are consecutive (e.g. ASCII + * but not EBCDIC). + * + * \param c A base64 digit. + * + * \return The value of the base64 digit \p c. + */ +signed char mbedtls_ct_base64_dec_value(unsigned char c); + +#endif /* MBEDTLS_TEST_HOOKS */ + +#endif /* MBEDTLS_BASE64_INTERNAL */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_core.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_core.h index e5500f1..ebcfc07 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_core.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_core.h @@ -1,775 +1,775 @@ -/** - * Core bignum functions - * - * This interface should only be used by the legacy bignum module (bignum.h) - * and the modular bignum modules (bignum_mod.c, bignum_mod_raw.c). All other - * modules should use the high-level modular bignum interface (bignum_mod.h) - * or the legacy bignum interface (bignum.h). - * - * This module is about processing non-negative integers with a fixed upper - * bound that's of the form 2^n-1 where n is a multiple of #biL. - * These can be thought of integers written in base 2^#biL with a fixed - * number of digits. Digits in this base are called *limbs*. - * Many operations treat these numbers as the principal representation of - * a number modulo 2^n or a smaller bound. - * - * The functions in this module obey the following conventions unless - * explicitly indicated otherwise: - * - * - **Overflow**: some functions indicate overflow from the range - * [0, 2^n-1] by returning carry parameters, while others operate - * modulo and so cannot overflow. This should be clear from the function - * documentation. - * - **Bignum parameters**: Bignums are passed as pointers to an array of - * limbs. A limb has the type #mbedtls_mpi_uint. Unless otherwise specified: - * - Bignum parameters called \p A, \p B, ... are inputs, and are - * not modified by the function. - * - For operations modulo some number, the modulus is called \p N - * and is input-only. - * - Bignum parameters called \p X, \p Y are outputs or input-output. - * The initial content of output-only parameters is ignored. - * - Some functions use different names that reflect traditional - * naming of operands of certain operations (e.g. - * divisor/dividend/quotient/remainder). - * - \p T is a temporary storage area. The initial content of such - * parameter is ignored and the final content is unspecified. - * - **Bignum sizes**: bignum sizes are always expressed in limbs. - * Most functions work on bignums of a given size and take a single - * \p limbs parameter that applies to all parameters that are limb arrays. - * All bignum sizes must be at least 1 and must be significantly less than - * #SIZE_MAX. The behavior if a size is 0 is undefined. The behavior if the - * total size of all parameters overflows #SIZE_MAX is undefined. - * - **Parameter ordering**: for bignum parameters, outputs come before inputs. - * Temporaries come last. - * - **Aliasing**: in general, output bignums may be aliased to one or more - * inputs. As an exception, parameters that are documented as a modulus value - * may not be aliased to an output. Outputs may not be aliased to one another. - * Temporaries may not be aliased to any other parameter. - * - **Overlap**: apart from aliasing of limb array pointers (where two - * arguments are equal pointers), overlap is not supported and may result - * in undefined behavior. - * - **Error handling**: This is a low-level module. Functions generally do not - * try to protect against invalid arguments such as nonsensical sizes or - * null pointers. Note that some functions that operate on bignums of - * different sizes have constraints about their size, and violating those - * constraints may lead to buffer overflows. - * - **Modular representatives**: functions that operate modulo \p N expect - * all modular inputs to be in the range [0, \p N - 1] and guarantee outputs - * in the range [0, \p N - 1]. If an input is out of range, outputs are - * fully unspecified, though bignum values out of range should not cause - * buffer overflows (beware that this is not extensively tested). - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BIGNUM_CORE_H -#define MBEDTLS_BIGNUM_CORE_H - -#include "common.h" - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -#include "constant_time_internal.h" - -#define ciL (sizeof(mbedtls_mpi_uint)) /** chars in limb */ -#define biL (ciL << 3) /** bits in limb */ -#define biH (ciL << 2) /** half limb size */ - -/* - * Convert between bits/chars and number of limbs - * Divide first in order to avoid potential overflows - */ -#define BITS_TO_LIMBS(i) ((i) / biL + ((i) % biL != 0)) -#define CHARS_TO_LIMBS(i) ((i) / ciL + ((i) % ciL != 0)) -/* Get a specific byte, without range checks. */ -#define GET_BYTE(X, i) \ - (((X)[(i) / ciL] >> (((i) % ciL) * 8)) & 0xff) - -/** Count leading zero bits in a given integer. - * - * \warning The result is undefined if \p a == 0 - * - * \param a Integer to count leading zero bits. - * - * \return The number of leading zero bits in \p a, if \p a != 0. - * If \p a == 0, the result is undefined. - */ -size_t mbedtls_mpi_core_clz(mbedtls_mpi_uint a); - -/** Return the minimum number of bits required to represent the value held - * in the MPI. - * - * \note This function returns 0 if all the limbs of \p A are 0. - * - * \param[in] A The address of the MPI. - * \param A_limbs The number of limbs of \p A. - * - * \return The number of bits in \p A. - */ -size_t mbedtls_mpi_core_bitlen(const mbedtls_mpi_uint *A, size_t A_limbs); - -/** Convert a big-endian byte array aligned to the size of mbedtls_mpi_uint - * into the storage form used by mbedtls_mpi. - * - * \param[in,out] A The address of the MPI. - * \param A_limbs The number of limbs of \p A. - */ -void mbedtls_mpi_core_bigendian_to_host(mbedtls_mpi_uint *A, - size_t A_limbs); - -/** \brief Compare a machine integer with an MPI. - * - * This function operates in constant time with respect - * to the values of \p min and \p A. - * - * \param min A machine integer. - * \param[in] A An MPI. - * \param A_limbs The number of limbs of \p A. - * This must be at least 1. - * - * \return MBEDTLS_CT_TRUE if \p min is less than or equal to \p A, otherwise MBEDTLS_CT_FALSE. - */ -mbedtls_ct_condition_t mbedtls_mpi_core_uint_le_mpi(mbedtls_mpi_uint min, - const mbedtls_mpi_uint *A, - size_t A_limbs); - -/** - * \brief Check if one unsigned MPI is less than another in constant - * time. - * - * \param A The left-hand MPI. This must point to an array of limbs - * with the same allocated length as \p B. - * \param B The right-hand MPI. This must point to an array of limbs - * with the same allocated length as \p A. - * \param limbs The number of limbs in \p A and \p B. - * This must not be 0. - * - * \return MBEDTLS_CT_TRUE if \p A is less than \p B. - * MBEDTLS_CT_FALSE if \p A is greater than or equal to \p B. - */ -mbedtls_ct_condition_t mbedtls_mpi_core_lt_ct(const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - size_t limbs); - -/** - * \brief Perform a safe conditional copy of an MPI which doesn't reveal - * whether assignment was done or not. - * - * \param[out] X The address of the destination MPI. - * This must be initialized. Must have enough limbs to - * store the full value of \p A. - * \param[in] A The address of the source MPI. This must be initialized. - * \param limbs The number of limbs of \p A. - * \param assign The condition deciding whether to perform the - * assignment or not. Callers will need to use - * the constant time interface (e.g. `mbedtls_ct_bool()`) - * to construct this argument. - * - * \note This function avoids leaking any information about whether - * the assignment was done or not. - */ -void mbedtls_mpi_core_cond_assign(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - size_t limbs, - mbedtls_ct_condition_t assign); - -/** - * \brief Perform a safe conditional swap of two MPIs which doesn't reveal - * whether the swap was done or not. - * - * \param[in,out] X The address of the first MPI. - * This must be initialized. - * \param[in,out] Y The address of the second MPI. - * This must be initialized. - * \param limbs The number of limbs of \p X and \p Y. - * \param swap The condition deciding whether to perform - * the swap or not. - * - * \note This function avoids leaking any information about whether - * the swap was done or not. - */ -void mbedtls_mpi_core_cond_swap(mbedtls_mpi_uint *X, - mbedtls_mpi_uint *Y, - size_t limbs, - mbedtls_ct_condition_t swap); - -/** Import X from unsigned binary data, little-endian. - * - * The MPI needs to have enough limbs to store the full value (including any - * most significant zero bytes in the input). - * - * \param[out] X The address of the MPI. - * \param X_limbs The number of limbs of \p X. - * \param[in] input The input buffer to import from. - * \param input_length The length bytes of \p input. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't - * large enough to hold the value in \p input. - */ -int mbedtls_mpi_core_read_le(mbedtls_mpi_uint *X, - size_t X_limbs, - const unsigned char *input, - size_t input_length); - -/** Import X from unsigned binary data, big-endian. - * - * The MPI needs to have enough limbs to store the full value (including any - * most significant zero bytes in the input). - * - * \param[out] X The address of the MPI. - * May only be #NULL if \p X_limbs is 0 and \p input_length - * is 0. - * \param X_limbs The number of limbs of \p X. - * \param[in] input The input buffer to import from. - * May only be #NULL if \p input_length is 0. - * \param input_length The length in bytes of \p input. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't - * large enough to hold the value in \p input. - */ -int mbedtls_mpi_core_read_be(mbedtls_mpi_uint *X, - size_t X_limbs, - const unsigned char *input, - size_t input_length); - -/** Export A into unsigned binary data, little-endian. - * - * \note If \p output is shorter than \p A the export is still successful if the - * value held in \p A fits in the buffer (that is, if enough of the most - * significant bytes of \p A are 0). - * - * \param[in] A The address of the MPI. - * \param A_limbs The number of limbs of \p A. - * \param[out] output The output buffer to export to. - * \param output_length The length in bytes of \p output. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't - * large enough to hold the value of \p A. - */ -int mbedtls_mpi_core_write_le(const mbedtls_mpi_uint *A, - size_t A_limbs, - unsigned char *output, - size_t output_length); - -/** Export A into unsigned binary data, big-endian. - * - * \note If \p output is shorter than \p A the export is still successful if the - * value held in \p A fits in the buffer (that is, if enough of the most - * significant bytes of \p A are 0). - * - * \param[in] A The address of the MPI. - * \param A_limbs The number of limbs of \p A. - * \param[out] output The output buffer to export to. - * \param output_length The length in bytes of \p output. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't - * large enough to hold the value of \p A. - */ -int mbedtls_mpi_core_write_be(const mbedtls_mpi_uint *A, - size_t A_limbs, - unsigned char *output, - size_t output_length); - -/** \brief Shift an MPI in-place right by a number of bits. - * - * Shifting by more bits than there are bit positions - * in \p X is valid and results in setting \p X to 0. - * - * This function's execution time depends on the value - * of \p count (and of course \p limbs). - * - * \param[in,out] X The number to shift. - * \param limbs The number of limbs of \p X. This must be at least 1. - * \param count The number of bits to shift by. - */ -void mbedtls_mpi_core_shift_r(mbedtls_mpi_uint *X, size_t limbs, - size_t count); - -/** - * \brief Shift an MPI in-place left by a number of bits. - * - * Shifting by more bits than there are bit positions - * in \p X will produce an unspecified result. - * - * This function's execution time depends on the value - * of \p count (and of course \p limbs). - * \param[in,out] X The number to shift. - * \param limbs The number of limbs of \p X. This must be at least 1. - * \param count The number of bits to shift by. - */ -void mbedtls_mpi_core_shift_l(mbedtls_mpi_uint *X, size_t limbs, - size_t count); - -/** - * \brief Add two fixed-size large unsigned integers, returning the carry. - * - * Calculates `A + B` where `A` and `B` have the same size. - * - * This function operates modulo `2^(biL*limbs)` and returns the carry - * (1 if there was a wraparound, and 0 otherwise). - * - * \p X may be aliased to \p A or \p B. - * - * \param[out] X The result of the addition. - * \param[in] A Little-endian presentation of the left operand. - * \param[in] B Little-endian presentation of the right operand. - * \param limbs Number of limbs of \p X, \p A and \p B. - * - * \return 1 if `A + B >= 2^(biL*limbs)`, 0 otherwise. - */ -mbedtls_mpi_uint mbedtls_mpi_core_add(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - size_t limbs); - -/** - * \brief Conditional addition of two fixed-size large unsigned integers, - * returning the carry. - * - * Functionally equivalent to - * - * ``` - * if( cond ) - * X += A; - * return carry; - * ``` - * - * This function operates modulo `2^(biL*limbs)`. - * - * \param[in,out] X The pointer to the (little-endian) array - * representing the bignum to accumulate onto. - * \param[in] A The pointer to the (little-endian) array - * representing the bignum to conditionally add - * to \p X. This may be aliased to \p X but may not - * overlap otherwise. - * \param limbs Number of limbs of \p X and \p A. - * \param cond Condition bit dictating whether addition should - * happen or not. This must be \c 0 or \c 1. - * - * \warning If \p cond is neither 0 nor 1, the result of this function - * is unspecified, and the resulting value in \p X might be - * neither its original value nor \p X + \p A. - * - * \return 1 if `X + cond * A >= 2^(biL*limbs)`, 0 otherwise. - */ -mbedtls_mpi_uint mbedtls_mpi_core_add_if(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - size_t limbs, - unsigned cond); - -/** - * \brief Subtract two fixed-size large unsigned integers, returning the borrow. - * - * Calculate `A - B` where \p A and \p B have the same size. - * This function operates modulo `2^(biL*limbs)` and returns the carry - * (1 if there was a wraparound, i.e. if `A < B`, and 0 otherwise). - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. - * - * \param[out] X The result of the subtraction. - * \param[in] A Little-endian presentation of left operand. - * \param[in] B Little-endian presentation of right operand. - * \param limbs Number of limbs of \p X, \p A and \p B. - * - * \return 1 if `A < B`. - * 0 if `A >= B`. - */ -mbedtls_mpi_uint mbedtls_mpi_core_sub(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - size_t limbs); - -/** - * \brief Perform a fixed-size multiply accumulate operation: X += b * A - * - * \p X may be aliased to \p A (when \p X_limbs == \p A_limbs), but may not - * otherwise overlap. - * - * This function operates modulo `2^(biL*X_limbs)`. - * - * \param[in,out] X The pointer to the (little-endian) array - * representing the bignum to accumulate onto. - * \param X_limbs The number of limbs of \p X. This must be - * at least \p A_limbs. - * \param[in] A The pointer to the (little-endian) array - * representing the bignum to multiply with. - * This may be aliased to \p X but may not overlap - * otherwise. - * \param A_limbs The number of limbs of \p A. - * \param b X scalar to multiply with. - * - * \return The carry at the end of the operation. - */ -mbedtls_mpi_uint mbedtls_mpi_core_mla(mbedtls_mpi_uint *X, size_t X_limbs, - const mbedtls_mpi_uint *A, size_t A_limbs, - mbedtls_mpi_uint b); - -/** - * \brief Perform a known-size multiplication - * - * \p X may not be aliased to any of the inputs for this function. - * \p A may be aliased to \p B. - * - * \param[out] X The pointer to the (little-endian) array to receive - * the product of \p A_limbs and \p B_limbs. - * This must be of length \p A_limbs + \p B_limbs. - * \param[in] A The pointer to the (little-endian) array - * representing the first factor. - * \param A_limbs The number of limbs in \p A. - * \param[in] B The pointer to the (little-endian) array - * representing the second factor. - * \param B_limbs The number of limbs in \p B. - */ -void mbedtls_mpi_core_mul(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, size_t A_limbs, - const mbedtls_mpi_uint *B, size_t B_limbs); - -/** - * \brief Calculate initialisation value for fast Montgomery modular - * multiplication - * - * \param[in] N Little-endian presentation of the modulus. This must have - * at least one limb. - * - * \return The initialisation value for fast Montgomery modular multiplication - */ -mbedtls_mpi_uint mbedtls_mpi_core_montmul_init(const mbedtls_mpi_uint *N); - -/** - * \brief Montgomery multiplication: X = A * B * R^-1 mod N (HAC 14.36) - * - * \p A and \p B must be in canonical form. That is, < \p N. - * - * \p X may be aliased to \p A or \p N, or even \p B (if \p AN_limbs == - * \p B_limbs) but may not overlap any parameters otherwise. - * - * \p A and \p B may alias each other, if \p AN_limbs == \p B_limbs. They may - * not alias \p N (since they must be in canonical form, they cannot == \p N). - * - * \param[out] X The destination MPI, as a little-endian array of - * length \p AN_limbs. - * On successful completion, X contains the result of - * the multiplication `A * B * R^-1` mod N where - * `R = 2^(biL*AN_limbs)`. - * \param[in] A Little-endian presentation of first operand. - * Must have the same number of limbs as \p N. - * \param[in] B Little-endian presentation of second operand. - * \param[in] B_limbs The number of limbs in \p B. - * Must be <= \p AN_limbs. - * \param[in] N Little-endian presentation of the modulus. - * This must be odd, and have exactly the same number - * of limbs as \p A. - * It may alias \p X, but must not alias or otherwise - * overlap any of the other parameters. - * \param[in] AN_limbs The number of limbs in \p X, \p A and \p N. - * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. - * This can be calculated by `mbedtls_mpi_core_montmul_init()`. - * \param[in,out] T Temporary storage of size at least 2*AN_limbs+1 limbs. - * Its initial content is unused and - * its final content is indeterminate. - * It must not alias or otherwise overlap any of the - * other parameters. - */ -void mbedtls_mpi_core_montmul(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, size_t B_limbs, - const mbedtls_mpi_uint *N, size_t AN_limbs, - mbedtls_mpi_uint mm, mbedtls_mpi_uint *T); - -/** - * \brief Calculate the square of the Montgomery constant. (Needed - * for conversion and operations in Montgomery form.) - * - * \param[out] X A pointer to the result of the calculation of - * the square of the Montgomery constant: - * 2^{2*n*biL} mod N. - * \param[in] N Little-endian presentation of the modulus, which must be odd. - * - * \return 0 if successful. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if there is not enough space - * to store the value of Montgomery constant squared. - * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p N modulus is zero. - * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p N modulus is negative. - */ -int mbedtls_mpi_core_get_mont_r2_unsafe(mbedtls_mpi *X, - const mbedtls_mpi *N); - -#if defined(MBEDTLS_TEST_HOOKS) -/** - * Copy an MPI from a table without leaking the index. - * - * \param dest The destination buffer. This must point to a writable - * buffer of at least \p limbs limbs. - * \param table The address of the table. This must point to a readable - * array of \p count elements of \p limbs limbs each. - * \param limbs The number of limbs in each table entry. - * \param count The number of entries in \p table. - * \param index The (secret) table index to look up. This must be in the - * range `0 .. count-1`. - */ -void mbedtls_mpi_core_ct_uint_table_lookup(mbedtls_mpi_uint *dest, - const mbedtls_mpi_uint *table, - size_t limbs, - size_t count, - size_t index); -#endif /* MBEDTLS_TEST_HOOKS */ - -/** - * \brief Fill an integer with a number of random bytes. - * - * \param X The destination MPI. - * \param X_limbs The number of limbs of \p X. - * \param bytes The number of random bytes to generate. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. This may be - * \c NULL if \p f_rng doesn't need a context argument. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p X does not have - * enough room for \p bytes bytes. - * \return A negative error code on RNG failure. - * - * \note The bytes obtained from the RNG are interpreted - * as a big-endian representation of an MPI; this can - * be relevant in applications like deterministic ECDSA. - */ -int mbedtls_mpi_core_fill_random(mbedtls_mpi_uint *X, size_t X_limbs, - size_t bytes, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** Generate a random number uniformly in a range. - * - * This function generates a random number between \p min inclusive and - * \p N exclusive. - * - * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) - * when the RNG is a suitably parametrized instance of HMAC_DRBG - * and \p min is \c 1. - * - * \note There are `N - min` possible outputs. The lower bound - * \p min can be reached, but the upper bound \p N cannot. - * - * \param X The destination MPI, with \p limbs limbs. - * It must not be aliased with \p N or otherwise overlap it. - * \param min The minimum value to return. - * \param N The upper bound of the range, exclusive, with \p limbs limbs. - * In other words, this is one plus the maximum value to return. - * \p N must be strictly larger than \p min. - * \param limbs The number of limbs of \p N and \p X. - * This must not be 0. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was - * unable to find a suitable value within a limited number - * of attempts. This has a negligible probability if \p N - * is significantly larger than \p min, which is the case - * for all usual cryptographic applications. - */ -int mbedtls_mpi_core_random(mbedtls_mpi_uint *X, - mbedtls_mpi_uint min, - const mbedtls_mpi_uint *N, - size_t limbs, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Returns the number of limbs of working memory required for - * a call to `mbedtls_mpi_core_exp_mod()`. - * - * \note This will always be at least - * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)`, - * i.e. sufficient for a call to `mbedtls_mpi_core_montmul()`. - * - * \param AN_limbs The number of limbs in the input `A` and the modulus `N` - * (they must be the same size) that will be given to - * `mbedtls_mpi_core_exp_mod()`. - * \param E_limbs The number of limbs in the exponent `E` that will be given - * to `mbedtls_mpi_core_exp_mod()`. - * - * \return The number of limbs of working memory required by - * `mbedtls_mpi_core_exp_mod()`. - */ -size_t mbedtls_mpi_core_exp_mod_working_limbs(size_t AN_limbs, size_t E_limbs); - -/** - * \brief Perform a modular exponentiation with secret exponent: - * X = A^E mod N, where \p A is already in Montgomery form. - * - * \p X may be aliased to \p A, but not to \p RR or \p E, even if \p E_limbs == - * \p AN_limbs. - * - * \param[out] X The destination MPI, as a little endian array of length - * \p AN_limbs. - * \param[in] A The base MPI, as a little endian array of length \p AN_limbs. - * Must be in Montgomery form. - * \param[in] N The modulus, as a little endian array of length \p AN_limbs. - * \param AN_limbs The number of limbs in \p X, \p A, \p N, \p RR. - * \param[in] E The exponent, as a little endian array of length \p E_limbs. - * \param E_limbs The number of limbs in \p E. - * \param[in] RR The precomputed residue of 2^{2*biL} modulo N, as a little - * endian array of length \p AN_limbs. - * \param[in,out] T Temporary storage of at least the number of limbs returned - * by `mbedtls_mpi_core_exp_mod_working_limbs()`. - * Its initial content is unused and its final content is - * indeterminate. - * It must not alias or otherwise overlap any of the other - * parameters. - * It is up to the caller to zeroize \p T when it is no - * longer needed, and before freeing it if it was dynamically - * allocated. - */ -void mbedtls_mpi_core_exp_mod(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *N, size_t AN_limbs, - const mbedtls_mpi_uint *E, size_t E_limbs, - const mbedtls_mpi_uint *RR, - mbedtls_mpi_uint *T); - -/** - * \brief Subtract unsigned integer from known-size large unsigned integers. - * Return the borrow. - * - * \param[out] X The result of the subtraction. - * \param[in] A The left operand. - * \param b The unsigned scalar to subtract. - * \param limbs Number of limbs of \p X and \p A. - * - * \return 1 if `A < b`. - * 0 if `A >= b`. - */ -mbedtls_mpi_uint mbedtls_mpi_core_sub_int(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - mbedtls_mpi_uint b, - size_t limbs); - -/** - * \brief Determine if a given MPI has the value \c 0 in constant time with - * respect to the value (but not with respect to the number of limbs). - * - * \param[in] A The MPI to test. - * \param limbs Number of limbs in \p A. - * - * \return 0 if `A == 0` - * non-0 (may be any value) if `A != 0`. - */ -mbedtls_mpi_uint mbedtls_mpi_core_check_zero_ct(const mbedtls_mpi_uint *A, - size_t limbs); - -/** - * \brief Returns the number of limbs of working memory required for - * a call to `mbedtls_mpi_core_montmul()`. - * - * \param AN_limbs The number of limbs in the input `A` and the modulus `N` - * (they must be the same size) that will be given to - * `mbedtls_mpi_core_montmul()` or one of the other functions - * that specifies this as the amount of working memory needed. - * - * \return The number of limbs of working memory required by - * `mbedtls_mpi_core_montmul()` (or other similar function). - */ -static inline size_t mbedtls_mpi_core_montmul_working_limbs(size_t AN_limbs) -{ - return 2 * AN_limbs + 1; -} - -/** Convert an MPI into Montgomery form. - * - * \p X may be aliased to \p A, but may not otherwise overlap it. - * - * \p X may not alias \p N (it is in canonical form, so must be strictly less - * than \p N). Nor may it alias or overlap \p rr (this is unlikely to be - * required in practice.) - * - * This function is a thin wrapper around `mbedtls_mpi_core_montmul()` that is - * an alternative to calling `mbedtls_mpi_mod_raw_to_mont_rep()` when we - * don't want to allocate memory. - * - * \param[out] X The result of the conversion. - * Must have the same number of limbs as \p A. - * \param[in] A The MPI to convert into Montgomery form. - * Must have the same number of limbs as the modulus. - * \param[in] N The address of the modulus, which gives the size of - * the base `R` = 2^(biL*N->limbs). - * \param[in] AN_limbs The number of limbs in \p X, \p A, \p N and \p rr. - * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. - * This can be determined by calling - * `mbedtls_mpi_core_montmul_init()`. - * \param[in] rr The residue for `2^{2*n*biL} mod N`. - * \param[in,out] T Temporary storage of size at least - * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)` - * limbs. - * Its initial content is unused and - * its final content is indeterminate. - * It must not alias or otherwise overlap any of the - * other parameters. - */ -void mbedtls_mpi_core_to_mont_rep(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *N, - size_t AN_limbs, - mbedtls_mpi_uint mm, - const mbedtls_mpi_uint *rr, - mbedtls_mpi_uint *T); - -/** Convert an MPI from Montgomery form. - * - * \p X may be aliased to \p A, but may not otherwise overlap it. - * - * \p X may not alias \p N (it is in canonical form, so must be strictly less - * than \p N). - * - * This function is a thin wrapper around `mbedtls_mpi_core_montmul()` that is - * an alternative to calling `mbedtls_mpi_mod_raw_from_mont_rep()` when we - * don't want to allocate memory. - * - * \param[out] X The result of the conversion. - * Must have the same number of limbs as \p A. - * \param[in] A The MPI to convert from Montgomery form. - * Must have the same number of limbs as the modulus. - * \param[in] N The address of the modulus, which gives the size of - * the base `R` = 2^(biL*N->limbs). - * \param[in] AN_limbs The number of limbs in \p X, \p A and \p N. - * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. - * This can be determined by calling - * `mbedtls_mpi_core_montmul_init()`. - * \param[in,out] T Temporary storage of size at least - * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)` - * limbs. - * Its initial content is unused and - * its final content is indeterminate. - * It must not alias or otherwise overlap any of the - * other parameters. - */ -void mbedtls_mpi_core_from_mont_rep(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *N, - size_t AN_limbs, - mbedtls_mpi_uint mm, - mbedtls_mpi_uint *T); - -#endif /* MBEDTLS_BIGNUM_CORE_H */ +/** + * Core bignum functions + * + * This interface should only be used by the legacy bignum module (bignum.h) + * and the modular bignum modules (bignum_mod.c, bignum_mod_raw.c). All other + * modules should use the high-level modular bignum interface (bignum_mod.h) + * or the legacy bignum interface (bignum.h). + * + * This module is about processing non-negative integers with a fixed upper + * bound that's of the form 2^n-1 where n is a multiple of #biL. + * These can be thought of integers written in base 2^#biL with a fixed + * number of digits. Digits in this base are called *limbs*. + * Many operations treat these numbers as the principal representation of + * a number modulo 2^n or a smaller bound. + * + * The functions in this module obey the following conventions unless + * explicitly indicated otherwise: + * + * - **Overflow**: some functions indicate overflow from the range + * [0, 2^n-1] by returning carry parameters, while others operate + * modulo and so cannot overflow. This should be clear from the function + * documentation. + * - **Bignum parameters**: Bignums are passed as pointers to an array of + * limbs. A limb has the type #mbedtls_mpi_uint. Unless otherwise specified: + * - Bignum parameters called \p A, \p B, ... are inputs, and are + * not modified by the function. + * - For operations modulo some number, the modulus is called \p N + * and is input-only. + * - Bignum parameters called \p X, \p Y are outputs or input-output. + * The initial content of output-only parameters is ignored. + * - Some functions use different names that reflect traditional + * naming of operands of certain operations (e.g. + * divisor/dividend/quotient/remainder). + * - \p T is a temporary storage area. The initial content of such + * parameter is ignored and the final content is unspecified. + * - **Bignum sizes**: bignum sizes are always expressed in limbs. + * Most functions work on bignums of a given size and take a single + * \p limbs parameter that applies to all parameters that are limb arrays. + * All bignum sizes must be at least 1 and must be significantly less than + * #SIZE_MAX. The behavior if a size is 0 is undefined. The behavior if the + * total size of all parameters overflows #SIZE_MAX is undefined. + * - **Parameter ordering**: for bignum parameters, outputs come before inputs. + * Temporaries come last. + * - **Aliasing**: in general, output bignums may be aliased to one or more + * inputs. As an exception, parameters that are documented as a modulus value + * may not be aliased to an output. Outputs may not be aliased to one another. + * Temporaries may not be aliased to any other parameter. + * - **Overlap**: apart from aliasing of limb array pointers (where two + * arguments are equal pointers), overlap is not supported and may result + * in undefined behavior. + * - **Error handling**: This is a low-level module. Functions generally do not + * try to protect against invalid arguments such as nonsensical sizes or + * null pointers. Note that some functions that operate on bignums of + * different sizes have constraints about their size, and violating those + * constraints may lead to buffer overflows. + * - **Modular representatives**: functions that operate modulo \p N expect + * all modular inputs to be in the range [0, \p N - 1] and guarantee outputs + * in the range [0, \p N - 1]. If an input is out of range, outputs are + * fully unspecified, though bignum values out of range should not cause + * buffer overflows (beware that this is not extensively tested). + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BIGNUM_CORE_H +#define MBEDTLS_BIGNUM_CORE_H + +#include "common.h" + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +#include "constant_time_internal.h" + +#define ciL (sizeof(mbedtls_mpi_uint)) /** chars in limb */ +#define biL (ciL << 3) /** bits in limb */ +#define biH (ciL << 2) /** half limb size */ + +/* + * Convert between bits/chars and number of limbs + * Divide first in order to avoid potential overflows + */ +#define BITS_TO_LIMBS(i) ((i) / biL + ((i) % biL != 0)) +#define CHARS_TO_LIMBS(i) ((i) / ciL + ((i) % ciL != 0)) +/* Get a specific byte, without range checks. */ +#define GET_BYTE(X, i) \ + (((X)[(i) / ciL] >> (((i) % ciL) * 8)) & 0xff) + +/** Count leading zero bits in a given integer. + * + * \warning The result is undefined if \p a == 0 + * + * \param a Integer to count leading zero bits. + * + * \return The number of leading zero bits in \p a, if \p a != 0. + * If \p a == 0, the result is undefined. + */ +size_t mbedtls_mpi_core_clz(mbedtls_mpi_uint a); + +/** Return the minimum number of bits required to represent the value held + * in the MPI. + * + * \note This function returns 0 if all the limbs of \p A are 0. + * + * \param[in] A The address of the MPI. + * \param A_limbs The number of limbs of \p A. + * + * \return The number of bits in \p A. + */ +size_t mbedtls_mpi_core_bitlen(const mbedtls_mpi_uint *A, size_t A_limbs); + +/** Convert a big-endian byte array aligned to the size of mbedtls_mpi_uint + * into the storage form used by mbedtls_mpi. + * + * \param[in,out] A The address of the MPI. + * \param A_limbs The number of limbs of \p A. + */ +void mbedtls_mpi_core_bigendian_to_host(mbedtls_mpi_uint *A, + size_t A_limbs); + +/** \brief Compare a machine integer with an MPI. + * + * This function operates in constant time with respect + * to the values of \p min and \p A. + * + * \param min A machine integer. + * \param[in] A An MPI. + * \param A_limbs The number of limbs of \p A. + * This must be at least 1. + * + * \return MBEDTLS_CT_TRUE if \p min is less than or equal to \p A, otherwise MBEDTLS_CT_FALSE. + */ +mbedtls_ct_condition_t mbedtls_mpi_core_uint_le_mpi(mbedtls_mpi_uint min, + const mbedtls_mpi_uint *A, + size_t A_limbs); + +/** + * \brief Check if one unsigned MPI is less than another in constant + * time. + * + * \param A The left-hand MPI. This must point to an array of limbs + * with the same allocated length as \p B. + * \param B The right-hand MPI. This must point to an array of limbs + * with the same allocated length as \p A. + * \param limbs The number of limbs in \p A and \p B. + * This must not be 0. + * + * \return MBEDTLS_CT_TRUE if \p A is less than \p B. + * MBEDTLS_CT_FALSE if \p A is greater than or equal to \p B. + */ +mbedtls_ct_condition_t mbedtls_mpi_core_lt_ct(const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + size_t limbs); + +/** + * \brief Perform a safe conditional copy of an MPI which doesn't reveal + * whether assignment was done or not. + * + * \param[out] X The address of the destination MPI. + * This must be initialized. Must have enough limbs to + * store the full value of \p A. + * \param[in] A The address of the source MPI. This must be initialized. + * \param limbs The number of limbs of \p A. + * \param assign The condition deciding whether to perform the + * assignment or not. Callers will need to use + * the constant time interface (e.g. `mbedtls_ct_bool()`) + * to construct this argument. + * + * \note This function avoids leaking any information about whether + * the assignment was done or not. + */ +void mbedtls_mpi_core_cond_assign(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + size_t limbs, + mbedtls_ct_condition_t assign); + +/** + * \brief Perform a safe conditional swap of two MPIs which doesn't reveal + * whether the swap was done or not. + * + * \param[in,out] X The address of the first MPI. + * This must be initialized. + * \param[in,out] Y The address of the second MPI. + * This must be initialized. + * \param limbs The number of limbs of \p X and \p Y. + * \param swap The condition deciding whether to perform + * the swap or not. + * + * \note This function avoids leaking any information about whether + * the swap was done or not. + */ +void mbedtls_mpi_core_cond_swap(mbedtls_mpi_uint *X, + mbedtls_mpi_uint *Y, + size_t limbs, + mbedtls_ct_condition_t swap); + +/** Import X from unsigned binary data, little-endian. + * + * The MPI needs to have enough limbs to store the full value (including any + * most significant zero bytes in the input). + * + * \param[out] X The address of the MPI. + * \param X_limbs The number of limbs of \p X. + * \param[in] input The input buffer to import from. + * \param input_length The length bytes of \p input. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't + * large enough to hold the value in \p input. + */ +int mbedtls_mpi_core_read_le(mbedtls_mpi_uint *X, + size_t X_limbs, + const unsigned char *input, + size_t input_length); + +/** Import X from unsigned binary data, big-endian. + * + * The MPI needs to have enough limbs to store the full value (including any + * most significant zero bytes in the input). + * + * \param[out] X The address of the MPI. + * May only be #NULL if \p X_limbs is 0 and \p input_length + * is 0. + * \param X_limbs The number of limbs of \p X. + * \param[in] input The input buffer to import from. + * May only be #NULL if \p input_length is 0. + * \param input_length The length in bytes of \p input. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't + * large enough to hold the value in \p input. + */ +int mbedtls_mpi_core_read_be(mbedtls_mpi_uint *X, + size_t X_limbs, + const unsigned char *input, + size_t input_length); + +/** Export A into unsigned binary data, little-endian. + * + * \note If \p output is shorter than \p A the export is still successful if the + * value held in \p A fits in the buffer (that is, if enough of the most + * significant bytes of \p A are 0). + * + * \param[in] A The address of the MPI. + * \param A_limbs The number of limbs of \p A. + * \param[out] output The output buffer to export to. + * \param output_length The length in bytes of \p output. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't + * large enough to hold the value of \p A. + */ +int mbedtls_mpi_core_write_le(const mbedtls_mpi_uint *A, + size_t A_limbs, + unsigned char *output, + size_t output_length); + +/** Export A into unsigned binary data, big-endian. + * + * \note If \p output is shorter than \p A the export is still successful if the + * value held in \p A fits in the buffer (that is, if enough of the most + * significant bytes of \p A are 0). + * + * \param[in] A The address of the MPI. + * \param A_limbs The number of limbs of \p A. + * \param[out] output The output buffer to export to. + * \param output_length The length in bytes of \p output. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't + * large enough to hold the value of \p A. + */ +int mbedtls_mpi_core_write_be(const mbedtls_mpi_uint *A, + size_t A_limbs, + unsigned char *output, + size_t output_length); + +/** \brief Shift an MPI in-place right by a number of bits. + * + * Shifting by more bits than there are bit positions + * in \p X is valid and results in setting \p X to 0. + * + * This function's execution time depends on the value + * of \p count (and of course \p limbs). + * + * \param[in,out] X The number to shift. + * \param limbs The number of limbs of \p X. This must be at least 1. + * \param count The number of bits to shift by. + */ +void mbedtls_mpi_core_shift_r(mbedtls_mpi_uint *X, size_t limbs, + size_t count); + +/** + * \brief Shift an MPI in-place left by a number of bits. + * + * Shifting by more bits than there are bit positions + * in \p X will produce an unspecified result. + * + * This function's execution time depends on the value + * of \p count (and of course \p limbs). + * \param[in,out] X The number to shift. + * \param limbs The number of limbs of \p X. This must be at least 1. + * \param count The number of bits to shift by. + */ +void mbedtls_mpi_core_shift_l(mbedtls_mpi_uint *X, size_t limbs, + size_t count); + +/** + * \brief Add two fixed-size large unsigned integers, returning the carry. + * + * Calculates `A + B` where `A` and `B` have the same size. + * + * This function operates modulo `2^(biL*limbs)` and returns the carry + * (1 if there was a wraparound, and 0 otherwise). + * + * \p X may be aliased to \p A or \p B. + * + * \param[out] X The result of the addition. + * \param[in] A Little-endian presentation of the left operand. + * \param[in] B Little-endian presentation of the right operand. + * \param limbs Number of limbs of \p X, \p A and \p B. + * + * \return 1 if `A + B >= 2^(biL*limbs)`, 0 otherwise. + */ +mbedtls_mpi_uint mbedtls_mpi_core_add(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + size_t limbs); + +/** + * \brief Conditional addition of two fixed-size large unsigned integers, + * returning the carry. + * + * Functionally equivalent to + * + * ``` + * if( cond ) + * X += A; + * return carry; + * ``` + * + * This function operates modulo `2^(biL*limbs)`. + * + * \param[in,out] X The pointer to the (little-endian) array + * representing the bignum to accumulate onto. + * \param[in] A The pointer to the (little-endian) array + * representing the bignum to conditionally add + * to \p X. This may be aliased to \p X but may not + * overlap otherwise. + * \param limbs Number of limbs of \p X and \p A. + * \param cond Condition bit dictating whether addition should + * happen or not. This must be \c 0 or \c 1. + * + * \warning If \p cond is neither 0 nor 1, the result of this function + * is unspecified, and the resulting value in \p X might be + * neither its original value nor \p X + \p A. + * + * \return 1 if `X + cond * A >= 2^(biL*limbs)`, 0 otherwise. + */ +mbedtls_mpi_uint mbedtls_mpi_core_add_if(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + size_t limbs, + unsigned cond); + +/** + * \brief Subtract two fixed-size large unsigned integers, returning the borrow. + * + * Calculate `A - B` where \p A and \p B have the same size. + * This function operates modulo `2^(biL*limbs)` and returns the carry + * (1 if there was a wraparound, i.e. if `A < B`, and 0 otherwise). + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. + * + * \param[out] X The result of the subtraction. + * \param[in] A Little-endian presentation of left operand. + * \param[in] B Little-endian presentation of right operand. + * \param limbs Number of limbs of \p X, \p A and \p B. + * + * \return 1 if `A < B`. + * 0 if `A >= B`. + */ +mbedtls_mpi_uint mbedtls_mpi_core_sub(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + size_t limbs); + +/** + * \brief Perform a fixed-size multiply accumulate operation: X += b * A + * + * \p X may be aliased to \p A (when \p X_limbs == \p A_limbs), but may not + * otherwise overlap. + * + * This function operates modulo `2^(biL*X_limbs)`. + * + * \param[in,out] X The pointer to the (little-endian) array + * representing the bignum to accumulate onto. + * \param X_limbs The number of limbs of \p X. This must be + * at least \p A_limbs. + * \param[in] A The pointer to the (little-endian) array + * representing the bignum to multiply with. + * This may be aliased to \p X but may not overlap + * otherwise. + * \param A_limbs The number of limbs of \p A. + * \param b X scalar to multiply with. + * + * \return The carry at the end of the operation. + */ +mbedtls_mpi_uint mbedtls_mpi_core_mla(mbedtls_mpi_uint *X, size_t X_limbs, + const mbedtls_mpi_uint *A, size_t A_limbs, + mbedtls_mpi_uint b); + +/** + * \brief Perform a known-size multiplication + * + * \p X may not be aliased to any of the inputs for this function. + * \p A may be aliased to \p B. + * + * \param[out] X The pointer to the (little-endian) array to receive + * the product of \p A_limbs and \p B_limbs. + * This must be of length \p A_limbs + \p B_limbs. + * \param[in] A The pointer to the (little-endian) array + * representing the first factor. + * \param A_limbs The number of limbs in \p A. + * \param[in] B The pointer to the (little-endian) array + * representing the second factor. + * \param B_limbs The number of limbs in \p B. + */ +void mbedtls_mpi_core_mul(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, size_t A_limbs, + const mbedtls_mpi_uint *B, size_t B_limbs); + +/** + * \brief Calculate initialisation value for fast Montgomery modular + * multiplication + * + * \param[in] N Little-endian presentation of the modulus. This must have + * at least one limb. + * + * \return The initialisation value for fast Montgomery modular multiplication + */ +mbedtls_mpi_uint mbedtls_mpi_core_montmul_init(const mbedtls_mpi_uint *N); + +/** + * \brief Montgomery multiplication: X = A * B * R^-1 mod N (HAC 14.36) + * + * \p A and \p B must be in canonical form. That is, < \p N. + * + * \p X may be aliased to \p A or \p N, or even \p B (if \p AN_limbs == + * \p B_limbs) but may not overlap any parameters otherwise. + * + * \p A and \p B may alias each other, if \p AN_limbs == \p B_limbs. They may + * not alias \p N (since they must be in canonical form, they cannot == \p N). + * + * \param[out] X The destination MPI, as a little-endian array of + * length \p AN_limbs. + * On successful completion, X contains the result of + * the multiplication `A * B * R^-1` mod N where + * `R = 2^(biL*AN_limbs)`. + * \param[in] A Little-endian presentation of first operand. + * Must have the same number of limbs as \p N. + * \param[in] B Little-endian presentation of second operand. + * \param[in] B_limbs The number of limbs in \p B. + * Must be <= \p AN_limbs. + * \param[in] N Little-endian presentation of the modulus. + * This must be odd, and have exactly the same number + * of limbs as \p A. + * It may alias \p X, but must not alias or otherwise + * overlap any of the other parameters. + * \param[in] AN_limbs The number of limbs in \p X, \p A and \p N. + * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. + * This can be calculated by `mbedtls_mpi_core_montmul_init()`. + * \param[in,out] T Temporary storage of size at least 2*AN_limbs+1 limbs. + * Its initial content is unused and + * its final content is indeterminate. + * It must not alias or otherwise overlap any of the + * other parameters. + */ +void mbedtls_mpi_core_montmul(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, size_t B_limbs, + const mbedtls_mpi_uint *N, size_t AN_limbs, + mbedtls_mpi_uint mm, mbedtls_mpi_uint *T); + +/** + * \brief Calculate the square of the Montgomery constant. (Needed + * for conversion and operations in Montgomery form.) + * + * \param[out] X A pointer to the result of the calculation of + * the square of the Montgomery constant: + * 2^{2*n*biL} mod N. + * \param[in] N Little-endian presentation of the modulus, which must be odd. + * + * \return 0 if successful. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if there is not enough space + * to store the value of Montgomery constant squared. + * \return #MBEDTLS_ERR_MPI_DIVISION_BY_ZERO if \p N modulus is zero. + * \return #MBEDTLS_ERR_MPI_NEGATIVE_VALUE if \p N modulus is negative. + */ +int mbedtls_mpi_core_get_mont_r2_unsafe(mbedtls_mpi *X, + const mbedtls_mpi *N); + +#if defined(MBEDTLS_TEST_HOOKS) +/** + * Copy an MPI from a table without leaking the index. + * + * \param dest The destination buffer. This must point to a writable + * buffer of at least \p limbs limbs. + * \param table The address of the table. This must point to a readable + * array of \p count elements of \p limbs limbs each. + * \param limbs The number of limbs in each table entry. + * \param count The number of entries in \p table. + * \param index The (secret) table index to look up. This must be in the + * range `0 .. count-1`. + */ +void mbedtls_mpi_core_ct_uint_table_lookup(mbedtls_mpi_uint *dest, + const mbedtls_mpi_uint *table, + size_t limbs, + size_t count, + size_t index); +#endif /* MBEDTLS_TEST_HOOKS */ + +/** + * \brief Fill an integer with a number of random bytes. + * + * \param X The destination MPI. + * \param X_limbs The number of limbs of \p X. + * \param bytes The number of random bytes to generate. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. This may be + * \c NULL if \p f_rng doesn't need a context argument. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p X does not have + * enough room for \p bytes bytes. + * \return A negative error code on RNG failure. + * + * \note The bytes obtained from the RNG are interpreted + * as a big-endian representation of an MPI; this can + * be relevant in applications like deterministic ECDSA. + */ +int mbedtls_mpi_core_fill_random(mbedtls_mpi_uint *X, size_t X_limbs, + size_t bytes, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** Generate a random number uniformly in a range. + * + * This function generates a random number between \p min inclusive and + * \p N exclusive. + * + * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) + * when the RNG is a suitably parametrized instance of HMAC_DRBG + * and \p min is \c 1. + * + * \note There are `N - min` possible outputs. The lower bound + * \p min can be reached, but the upper bound \p N cannot. + * + * \param X The destination MPI, with \p limbs limbs. + * It must not be aliased with \p N or otherwise overlap it. + * \param min The minimum value to return. + * \param N The upper bound of the range, exclusive, with \p limbs limbs. + * In other words, this is one plus the maximum value to return. + * \p N must be strictly larger than \p min. + * \param limbs The number of limbs of \p N and \p X. + * This must not be 0. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was + * unable to find a suitable value within a limited number + * of attempts. This has a negligible probability if \p N + * is significantly larger than \p min, which is the case + * for all usual cryptographic applications. + */ +int mbedtls_mpi_core_random(mbedtls_mpi_uint *X, + mbedtls_mpi_uint min, + const mbedtls_mpi_uint *N, + size_t limbs, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Returns the number of limbs of working memory required for + * a call to `mbedtls_mpi_core_exp_mod()`. + * + * \note This will always be at least + * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)`, + * i.e. sufficient for a call to `mbedtls_mpi_core_montmul()`. + * + * \param AN_limbs The number of limbs in the input `A` and the modulus `N` + * (they must be the same size) that will be given to + * `mbedtls_mpi_core_exp_mod()`. + * \param E_limbs The number of limbs in the exponent `E` that will be given + * to `mbedtls_mpi_core_exp_mod()`. + * + * \return The number of limbs of working memory required by + * `mbedtls_mpi_core_exp_mod()`. + */ +size_t mbedtls_mpi_core_exp_mod_working_limbs(size_t AN_limbs, size_t E_limbs); + +/** + * \brief Perform a modular exponentiation with secret exponent: + * X = A^E mod N, where \p A is already in Montgomery form. + * + * \p X may be aliased to \p A, but not to \p RR or \p E, even if \p E_limbs == + * \p AN_limbs. + * + * \param[out] X The destination MPI, as a little endian array of length + * \p AN_limbs. + * \param[in] A The base MPI, as a little endian array of length \p AN_limbs. + * Must be in Montgomery form. + * \param[in] N The modulus, as a little endian array of length \p AN_limbs. + * \param AN_limbs The number of limbs in \p X, \p A, \p N, \p RR. + * \param[in] E The exponent, as a little endian array of length \p E_limbs. + * \param E_limbs The number of limbs in \p E. + * \param[in] RR The precomputed residue of 2^{2*biL} modulo N, as a little + * endian array of length \p AN_limbs. + * \param[in,out] T Temporary storage of at least the number of limbs returned + * by `mbedtls_mpi_core_exp_mod_working_limbs()`. + * Its initial content is unused and its final content is + * indeterminate. + * It must not alias or otherwise overlap any of the other + * parameters. + * It is up to the caller to zeroize \p T when it is no + * longer needed, and before freeing it if it was dynamically + * allocated. + */ +void mbedtls_mpi_core_exp_mod(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *N, size_t AN_limbs, + const mbedtls_mpi_uint *E, size_t E_limbs, + const mbedtls_mpi_uint *RR, + mbedtls_mpi_uint *T); + +/** + * \brief Subtract unsigned integer from known-size large unsigned integers. + * Return the borrow. + * + * \param[out] X The result of the subtraction. + * \param[in] A The left operand. + * \param b The unsigned scalar to subtract. + * \param limbs Number of limbs of \p X and \p A. + * + * \return 1 if `A < b`. + * 0 if `A >= b`. + */ +mbedtls_mpi_uint mbedtls_mpi_core_sub_int(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + mbedtls_mpi_uint b, + size_t limbs); + +/** + * \brief Determine if a given MPI has the value \c 0 in constant time with + * respect to the value (but not with respect to the number of limbs). + * + * \param[in] A The MPI to test. + * \param limbs Number of limbs in \p A. + * + * \return 0 if `A == 0` + * non-0 (may be any value) if `A != 0`. + */ +mbedtls_mpi_uint mbedtls_mpi_core_check_zero_ct(const mbedtls_mpi_uint *A, + size_t limbs); + +/** + * \brief Returns the number of limbs of working memory required for + * a call to `mbedtls_mpi_core_montmul()`. + * + * \param AN_limbs The number of limbs in the input `A` and the modulus `N` + * (they must be the same size) that will be given to + * `mbedtls_mpi_core_montmul()` or one of the other functions + * that specifies this as the amount of working memory needed. + * + * \return The number of limbs of working memory required by + * `mbedtls_mpi_core_montmul()` (or other similar function). + */ +static inline size_t mbedtls_mpi_core_montmul_working_limbs(size_t AN_limbs) +{ + return 2 * AN_limbs + 1; +} + +/** Convert an MPI into Montgomery form. + * + * \p X may be aliased to \p A, but may not otherwise overlap it. + * + * \p X may not alias \p N (it is in canonical form, so must be strictly less + * than \p N). Nor may it alias or overlap \p rr (this is unlikely to be + * required in practice.) + * + * This function is a thin wrapper around `mbedtls_mpi_core_montmul()` that is + * an alternative to calling `mbedtls_mpi_mod_raw_to_mont_rep()` when we + * don't want to allocate memory. + * + * \param[out] X The result of the conversion. + * Must have the same number of limbs as \p A. + * \param[in] A The MPI to convert into Montgomery form. + * Must have the same number of limbs as the modulus. + * \param[in] N The address of the modulus, which gives the size of + * the base `R` = 2^(biL*N->limbs). + * \param[in] AN_limbs The number of limbs in \p X, \p A, \p N and \p rr. + * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. + * This can be determined by calling + * `mbedtls_mpi_core_montmul_init()`. + * \param[in] rr The residue for `2^{2*n*biL} mod N`. + * \param[in,out] T Temporary storage of size at least + * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)` + * limbs. + * Its initial content is unused and + * its final content is indeterminate. + * It must not alias or otherwise overlap any of the + * other parameters. + */ +void mbedtls_mpi_core_to_mont_rep(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *N, + size_t AN_limbs, + mbedtls_mpi_uint mm, + const mbedtls_mpi_uint *rr, + mbedtls_mpi_uint *T); + +/** Convert an MPI from Montgomery form. + * + * \p X may be aliased to \p A, but may not otherwise overlap it. + * + * \p X may not alias \p N (it is in canonical form, so must be strictly less + * than \p N). + * + * This function is a thin wrapper around `mbedtls_mpi_core_montmul()` that is + * an alternative to calling `mbedtls_mpi_mod_raw_from_mont_rep()` when we + * don't want to allocate memory. + * + * \param[out] X The result of the conversion. + * Must have the same number of limbs as \p A. + * \param[in] A The MPI to convert from Montgomery form. + * Must have the same number of limbs as the modulus. + * \param[in] N The address of the modulus, which gives the size of + * the base `R` = 2^(biL*N->limbs). + * \param[in] AN_limbs The number of limbs in \p X, \p A and \p N. + * \param mm The Montgomery constant for \p N: -N^-1 mod 2^biL. + * This can be determined by calling + * `mbedtls_mpi_core_montmul_init()`. + * \param[in,out] T Temporary storage of size at least + * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)` + * limbs. + * Its initial content is unused and + * its final content is indeterminate. + * It must not alias or otherwise overlap any of the + * other parameters. + */ +void mbedtls_mpi_core_from_mont_rep(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *N, + size_t AN_limbs, + mbedtls_mpi_uint mm, + mbedtls_mpi_uint *T); + +#endif /* MBEDTLS_BIGNUM_CORE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod.h index 39e8fd2..ffc9cc1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod.h @@ -1,464 +1,464 @@ -/** - * Modular bignum functions - * - * This module implements operations on integers modulo some fixed modulus. - * - * The functions in this module obey the following conventions unless - * explicitly indicated otherwise: - * - * - **Modulus parameters**: the modulus is passed as a pointer to a structure - * of type #mbedtls_mpi_mod_modulus. The structure must be set up with an - * array of limbs storing the bignum value of the modulus. The modulus must - * be odd and is assumed to have no leading zeroes. The modulus is usually - * named \c N and is usually input-only. Functions which take a parameter - * of type \c const #mbedtls_mpi_mod_modulus* must not modify its value. - * - **Bignum parameters**: Bignums are passed as pointers to an array of - * limbs or to a #mbedtls_mpi_mod_residue structure. A limb has the type - * #mbedtls_mpi_uint. Residues must be initialized before use, and must be - * associated with the modulus \c N. Unless otherwise specified: - * - Bignum parameters called \c A, \c B, ... are inputs and are not - * modified by the function. Functions which take a parameter of - * type \c const #mbedtls_mpi_mod_residue* must not modify its value. - * - Bignum parameters called \c X, \c Y, ... are outputs or input-output. - * The initial bignum value of output-only parameters is ignored, but - * they must be set up and associated with the modulus \c N. Some - * functions (typically constant-flow) require that the limbs in an - * output residue are initialized. - * - Bignum parameters called \c p are inputs used to set up a modulus or - * residue. These must be pointers to an array of limbs. - * - \c T is a temporary storage area. The initial content of such a - * parameter is ignored and the final content is unspecified. - * - Some functions use different names, such as \c r for the residue. - * - **Bignum sizes**: bignum sizes are always expressed in limbs. Both - * #mbedtls_mpi_mod_modulus and #mbedtls_mpi_mod_residue have a \c limbs - * member storing its size. All bignum parameters must have the same - * number of limbs as the modulus. All bignum sizes must be at least 1 and - * must be significantly less than #SIZE_MAX. The behavior if a size is 0 is - * undefined. - * - **Bignum representation**: the representation of inputs and outputs is - * specified by the \c int_rep field of the modulus. - * - **Parameter ordering**: for bignum parameters, outputs come before inputs. - * The modulus is passed after residues. Temporaries come last. - * - **Aliasing**: in general, output bignums may be aliased to one or more - * inputs. Modulus values may not be aliased to any other parameter. Outputs - * may not be aliased to one another. Temporaries may not be aliased to any - * other parameter. - * - **Overlap**: apart from aliasing of residue pointers (where two residue - * arguments are equal pointers), overlap is not supported and may result - * in undefined behavior. - * - **Error handling**: functions generally check compatibility of input - * sizes. Most functions will not check that input values are in canonical - * form (i.e. that \c A < \c N), this is only checked during setup of a - * residue structure. - * - **Modular representatives**: all functions expect inputs to be in the - * range [0, \c N - 1] and guarantee outputs in the range [0, \c N - 1]. - * Residues are set up with an associated modulus, and operations are only - * guaranteed to work if the modulus is associated with all residue - * parameters. If a residue is passed with a modulus other than the one it - * is associated with, then it may be out of range. If an input is out of - * range, outputs are fully unspecified, though bignum values out of range - * should not cause buffer overflows (beware that this is not extensively - * tested). - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BIGNUM_MOD_H -#define MBEDTLS_BIGNUM_MOD_H - -#include "common.h" - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -/** How residues associated with a modulus are represented. - * - * This also determines which fields of the modulus structure are valid and - * what their contents are (see #mbedtls_mpi_mod_modulus). - */ -typedef enum { - /** Representation not chosen (makes the modulus structure invalid). */ - MBEDTLS_MPI_MOD_REP_INVALID = 0, - /* Skip 1 as it is slightly easier to accidentally pass to functions. */ - /** Montgomery representation. */ - MBEDTLS_MPI_MOD_REP_MONTGOMERY = 2, - /* Optimised reduction available. This indicates a coordinate modulus (P) - * and one or more of the following have been configured: - * - A nist curve (MBEDTLS_ECP_DP_SECPXXXR1_ENABLED) & MBEDTLS_ECP_NIST_OPTIM. - * - A Kobliz Curve. - * - A Fast Reduction Curve CURVE25519 or CURVE448. */ - MBEDTLS_MPI_MOD_REP_OPT_RED, -} mbedtls_mpi_mod_rep_selector; - -/* Make mbedtls_mpi_mod_rep_selector and mbedtls_mpi_mod_ext_rep disjoint to - * make it easier to catch when they are accidentally swapped. */ -typedef enum { - MBEDTLS_MPI_MOD_EXT_REP_INVALID = 0, - MBEDTLS_MPI_MOD_EXT_REP_LE = 8, - MBEDTLS_MPI_MOD_EXT_REP_BE -} mbedtls_mpi_mod_ext_rep; - -typedef struct { - mbedtls_mpi_uint *p; - size_t limbs; -} mbedtls_mpi_mod_residue; - -typedef struct { - mbedtls_mpi_uint const *rr; /* The residue for 2^{2*n*biL} mod N */ - mbedtls_mpi_uint mm; /* Montgomery const for -N^{-1} mod 2^{ciL} */ -} mbedtls_mpi_mont_struct; - -typedef int (*mbedtls_mpi_modp_fn)(mbedtls_mpi_uint *X, size_t X_limbs); - -typedef struct { - mbedtls_mpi_modp_fn modp; /* The optimised reduction function pointer */ -} mbedtls_mpi_opt_red_struct; - -typedef struct { - const mbedtls_mpi_uint *p; - size_t limbs; // number of limbs - size_t bits; // bitlen of p - mbedtls_mpi_mod_rep_selector int_rep; // selector to signal the active member of the union - union rep { - /* if int_rep == #MBEDTLS_MPI_MOD_REP_MONTGOMERY */ - mbedtls_mpi_mont_struct mont; - /* if int_rep == #MBEDTLS_MPI_MOD_REP_OPT_RED */ - mbedtls_mpi_opt_red_struct ored; - } rep; -} mbedtls_mpi_mod_modulus; - -/** Setup a residue structure. - * - * The residue will be set up with the buffer \p p and modulus \p N. - * - * The memory pointed to by \p p will be used by the resulting residue structure. - * The value at the pointed-to memory will be the initial value of \p r and must - * hold a value that is less than the modulus. This value will be used as-is - * and interpreted according to the value of the `N->int_rep` field. - * - * The modulus \p N will be the modulus associated with \p r. The residue \p r - * should only be used in operations where the modulus is \p N. - * - * \param[out] r The address of the residue to setup. - * \param[in] N The address of the modulus related to \p r. - * \param[in] p The address of the limb array containing the value of \p r. - * The memory pointed to by \p p will be used by \p r and must - * not be modified in any way until after - * mbedtls_mpi_mod_residue_release() is called. The data - * pointed to by \p p must be less than the modulus (the value - * pointed to by `N->p`) and already in the representation - * indicated by `N->int_rep`. - * \param p_limbs The number of limbs of \p p. Must be the same as the number - * of limbs in the modulus \p N. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p p_limbs is less than the - * limbs in \p N or if \p p is not less than \p N. - */ -int mbedtls_mpi_mod_residue_setup(mbedtls_mpi_mod_residue *r, - const mbedtls_mpi_mod_modulus *N, - mbedtls_mpi_uint *p, - size_t p_limbs); - -/** Unbind elements of a residue structure. - * - * This function removes the reference to the limb array that was passed to - * mbedtls_mpi_mod_residue_setup() to make it safe to free or use again. - * - * This function invalidates \p r and it must not be used until after - * mbedtls_mpi_mod_residue_setup() is called on it again. - * - * \param[out] r The address of residue to release. - */ -void mbedtls_mpi_mod_residue_release(mbedtls_mpi_mod_residue *r); - -/** Initialize a modulus structure. - * - * \param[out] N The address of the modulus structure to initialize. - */ -void mbedtls_mpi_mod_modulus_init(mbedtls_mpi_mod_modulus *N); - -/** Setup a modulus structure. - * - * \param[out] N The address of the modulus structure to populate. - * \param[in] p The address of the limb array storing the value of \p N. - * The memory pointed to by \p p will be used by \p N and must - * not be modified in any way until after - * mbedtls_mpi_mod_modulus_free() is called. - * \param p_limbs The number of limbs of \p p. - * - * \return \c 0 if successful. - */ -int mbedtls_mpi_mod_modulus_setup(mbedtls_mpi_mod_modulus *N, - const mbedtls_mpi_uint *p, - size_t p_limbs); - -/** Setup an optimised-reduction compatible modulus structure. - * - * \param[out] N The address of the modulus structure to populate. - * \param[in] p The address of the limb array storing the value of \p N. - * The memory pointed to by \p p will be used by \p N and must - * not be modified in any way until after - * mbedtls_mpi_mod_modulus_free() is called. - * \param p_limbs The number of limbs of \p p. - * \param modp A pointer to the optimised reduction function to use. \p p. - * - * \return \c 0 if successful. - */ -int mbedtls_mpi_mod_optred_modulus_setup(mbedtls_mpi_mod_modulus *N, - const mbedtls_mpi_uint *p, - size_t p_limbs, - mbedtls_mpi_modp_fn modp); - -/** Free elements of a modulus structure. - * - * This function frees any memory allocated by mbedtls_mpi_mod_modulus_setup(). - * - * \warning This function does not free the limb array passed to - * mbedtls_mpi_mod_modulus_setup() only removes the reference to it, - * making it safe to free or to use it again. - * - * \param[in,out] N The address of the modulus structure to free. - */ -void mbedtls_mpi_mod_modulus_free(mbedtls_mpi_mod_modulus *N); - -/** \brief Multiply two residues, returning the residue modulo the specified - * modulus. - * - * \note Currently handles the case when `N->int_rep` is - * MBEDTLS_MPI_MOD_REP_MONTGOMERY. - * - * The size of the operation is determined by \p N. \p A, \p B and \p X must - * all be associated with the modulus \p N and must all have the same number - * of limbs as \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. They may not alias \p N (since they must be in canonical - * form, they cannot == \p N). - * - * \param[out] X The address of the result MPI. Must have the same - * number of limbs as \p N. - * On successful completion, \p X contains the result of - * the multiplication `A * B * R^-1` mod N where - * `R = 2^(biL * N->limbs)`. - * \param[in] A The address of the first MPI. - * \param[in] B The address of the second MPI. - * \param[in] N The address of the modulus. Used to perform a modulo - * operation on the result of the multiplication. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if all the parameters do not - * have the same number of limbs or \p N is invalid. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. - */ -int mbedtls_mpi_mod_mul(mbedtls_mpi_mod_residue *X, - const mbedtls_mpi_mod_residue *A, - const mbedtls_mpi_mod_residue *B, - const mbedtls_mpi_mod_modulus *N); - -/** - * \brief Perform a fixed-size modular subtraction. - * - * Calculate `A - B modulo N`. - * - * \p A, \p B and \p X must all have the same number of limbs as \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. - * - * \note This function does not check that \p A or \p B are in canonical - * form (that is, are < \p N) - that will have been done by - * mbedtls_mpi_mod_residue_setup(). - * - * \param[out] X The address of the result MPI. Must be initialized. - * Must have the same number of limbs as the modulus \p N. - * \param[in] A The address of the first MPI. - * \param[in] B The address of the second MPI. - * \param[in] N The address of the modulus. Used to perform a modulo - * operation on the result of the subtraction. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the given MPIs do not - * have the correct number of limbs. - */ -int mbedtls_mpi_mod_sub(mbedtls_mpi_mod_residue *X, - const mbedtls_mpi_mod_residue *A, - const mbedtls_mpi_mod_residue *B, - const mbedtls_mpi_mod_modulus *N); - -/** - * \brief Perform modular inversion of an MPI with respect to a modulus \p N. - * - * \p A and \p X must be associated with the modulus \p N and will therefore - * have the same number of limbs as \p N. - * - * \p X may be aliased to \p A. - * - * \warning Currently only supports prime moduli, but does not check for them. - * - * \param[out] X The modular inverse of \p A with respect to \p N. - * \param[in] A The number to calculate the modular inverse of. - * Must not be 0. - * \param[in] N The modulus to use. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p A and \p N do not - * have the same number of limbs. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p A is zero. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if couldn't allocate enough - * memory (needed for conversion to and from Mongtomery form - * when not in Montgomery form already, and for temporary use - * by the inversion calculation itself). - */ - -int mbedtls_mpi_mod_inv(mbedtls_mpi_mod_residue *X, - const mbedtls_mpi_mod_residue *A, - const mbedtls_mpi_mod_modulus *N); -/** - * \brief Perform a fixed-size modular addition. - * - * Calculate `A + B modulo N`. - * - * \p A, \p B and \p X must all be associated with the modulus \p N and must - * all have the same number of limbs as \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. - * - * \note This function does not check that \p A or \p B are in canonical - * form (that is, are < \p N) - that will have been done by - * mbedtls_mpi_mod_residue_setup(). - * - * \param[out] X The address of the result residue. Must be initialized. - * Must have the same number of limbs as the modulus \p N. - * \param[in] A The address of the first input residue. - * \param[in] B The address of the second input residue. - * \param[in] N The address of the modulus. Used to perform a modulo - * operation on the result of the addition. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the given MPIs do not - * have the correct number of limbs. - */ -int mbedtls_mpi_mod_add(mbedtls_mpi_mod_residue *X, - const mbedtls_mpi_mod_residue *A, - const mbedtls_mpi_mod_residue *B, - const mbedtls_mpi_mod_modulus *N); - -/** Generate a random number uniformly in a range. - * - * This function generates a random number between \p min inclusive and - * \p N exclusive. - * - * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) - * when the RNG is a suitably parametrized instance of HMAC_DRBG - * and \p min is \c 1. - * - * \note There are `N - min` possible outputs. The lower bound - * \p min can be reached, but the upper bound \p N cannot. - * - * \param X The destination residue. - * \param min The minimum value to return. It must be strictly smaller - * than \b N. - * \param N The modulus. - * This is the upper bound of the output range, exclusive. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was - * unable to find a suitable value within a limited number - * of attempts. This has a negligible probability if \p N - * is significantly larger than \p min, which is the case - * for all usual cryptographic applications. - */ -int mbedtls_mpi_mod_random(mbedtls_mpi_mod_residue *X, - mbedtls_mpi_uint min, - const mbedtls_mpi_mod_modulus *N, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** Read a residue from a byte buffer. - * - * The residue will be automatically converted to the internal representation - * based on the value of the `N->int_rep` field. - * - * The modulus \p N will be the modulus associated with \p r. The residue \p r - * should only be used in operations where the modulus is \p N or a modulus - * equivalent to \p N (in the sense that all their fields or memory pointed by - * their fields hold the same value). - * - * \param[out] r The address of the residue. It must have exactly the same - * number of limbs as the modulus \p N. - * \param[in] N The address of the modulus. - * \param[in] buf The input buffer to import from. - * \param buflen The length in bytes of \p buf. - * \param ext_rep The endianness of the number in the input buffer. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p r isn't - * large enough to hold the value in \p buf. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p ext_rep - * is invalid or the value in the buffer is not less than \p N. - */ -int mbedtls_mpi_mod_read(mbedtls_mpi_mod_residue *r, - const mbedtls_mpi_mod_modulus *N, - const unsigned char *buf, - size_t buflen, - mbedtls_mpi_mod_ext_rep ext_rep); - -/** Write a residue into a byte buffer. - * - * The modulus \p N must be the modulus associated with \p r (see - * mbedtls_mpi_mod_residue_setup() and mbedtls_mpi_mod_read()). - * - * The residue will be automatically converted from the internal representation - * based on the value of `N->int_rep` field. - * - * \warning If the buffer is smaller than `N->bits`, the number of - * leading zeroes is leaked through timing. If \p r is - * secret, the caller must ensure that \p buflen is at least - * (`N->bits`+7)/8. - * - * \param[in] r The address of the residue. It must have the same number of - * limbs as the modulus \p N. (\p r is an input parameter, but - * its value will be modified during execution and restored - * before the function returns.) - * \param[in] N The address of the modulus associated with \p r. - * \param[out] buf The output buffer to export to. - * \param buflen The length in bytes of \p buf. - * \param ext_rep The endianness in which the number should be written into - * the output buffer. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't - * large enough to hold the value of \p r (without leading - * zeroes). - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p ext_rep is invalid. - * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if couldn't allocate enough - * memory for conversion. Can occur only for moduli with - * MBEDTLS_MPI_MOD_REP_MONTGOMERY. - */ -int mbedtls_mpi_mod_write(const mbedtls_mpi_mod_residue *r, - const mbedtls_mpi_mod_modulus *N, - unsigned char *buf, - size_t buflen, - mbedtls_mpi_mod_ext_rep ext_rep); - -#endif /* MBEDTLS_BIGNUM_MOD_H */ +/** + * Modular bignum functions + * + * This module implements operations on integers modulo some fixed modulus. + * + * The functions in this module obey the following conventions unless + * explicitly indicated otherwise: + * + * - **Modulus parameters**: the modulus is passed as a pointer to a structure + * of type #mbedtls_mpi_mod_modulus. The structure must be set up with an + * array of limbs storing the bignum value of the modulus. The modulus must + * be odd and is assumed to have no leading zeroes. The modulus is usually + * named \c N and is usually input-only. Functions which take a parameter + * of type \c const #mbedtls_mpi_mod_modulus* must not modify its value. + * - **Bignum parameters**: Bignums are passed as pointers to an array of + * limbs or to a #mbedtls_mpi_mod_residue structure. A limb has the type + * #mbedtls_mpi_uint. Residues must be initialized before use, and must be + * associated with the modulus \c N. Unless otherwise specified: + * - Bignum parameters called \c A, \c B, ... are inputs and are not + * modified by the function. Functions which take a parameter of + * type \c const #mbedtls_mpi_mod_residue* must not modify its value. + * - Bignum parameters called \c X, \c Y, ... are outputs or input-output. + * The initial bignum value of output-only parameters is ignored, but + * they must be set up and associated with the modulus \c N. Some + * functions (typically constant-flow) require that the limbs in an + * output residue are initialized. + * - Bignum parameters called \c p are inputs used to set up a modulus or + * residue. These must be pointers to an array of limbs. + * - \c T is a temporary storage area. The initial content of such a + * parameter is ignored and the final content is unspecified. + * - Some functions use different names, such as \c r for the residue. + * - **Bignum sizes**: bignum sizes are always expressed in limbs. Both + * #mbedtls_mpi_mod_modulus and #mbedtls_mpi_mod_residue have a \c limbs + * member storing its size. All bignum parameters must have the same + * number of limbs as the modulus. All bignum sizes must be at least 1 and + * must be significantly less than #SIZE_MAX. The behavior if a size is 0 is + * undefined. + * - **Bignum representation**: the representation of inputs and outputs is + * specified by the \c int_rep field of the modulus. + * - **Parameter ordering**: for bignum parameters, outputs come before inputs. + * The modulus is passed after residues. Temporaries come last. + * - **Aliasing**: in general, output bignums may be aliased to one or more + * inputs. Modulus values may not be aliased to any other parameter. Outputs + * may not be aliased to one another. Temporaries may not be aliased to any + * other parameter. + * - **Overlap**: apart from aliasing of residue pointers (where two residue + * arguments are equal pointers), overlap is not supported and may result + * in undefined behavior. + * - **Error handling**: functions generally check compatibility of input + * sizes. Most functions will not check that input values are in canonical + * form (i.e. that \c A < \c N), this is only checked during setup of a + * residue structure. + * - **Modular representatives**: all functions expect inputs to be in the + * range [0, \c N - 1] and guarantee outputs in the range [0, \c N - 1]. + * Residues are set up with an associated modulus, and operations are only + * guaranteed to work if the modulus is associated with all residue + * parameters. If a residue is passed with a modulus other than the one it + * is associated with, then it may be out of range. If an input is out of + * range, outputs are fully unspecified, though bignum values out of range + * should not cause buffer overflows (beware that this is not extensively + * tested). + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BIGNUM_MOD_H +#define MBEDTLS_BIGNUM_MOD_H + +#include "common.h" + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +/** How residues associated with a modulus are represented. + * + * This also determines which fields of the modulus structure are valid and + * what their contents are (see #mbedtls_mpi_mod_modulus). + */ +typedef enum { + /** Representation not chosen (makes the modulus structure invalid). */ + MBEDTLS_MPI_MOD_REP_INVALID = 0, + /* Skip 1 as it is slightly easier to accidentally pass to functions. */ + /** Montgomery representation. */ + MBEDTLS_MPI_MOD_REP_MONTGOMERY = 2, + /* Optimised reduction available. This indicates a coordinate modulus (P) + * and one or more of the following have been configured: + * - A nist curve (MBEDTLS_ECP_DP_SECPXXXR1_ENABLED) & MBEDTLS_ECP_NIST_OPTIM. + * - A Kobliz Curve. + * - A Fast Reduction Curve CURVE25519 or CURVE448. */ + MBEDTLS_MPI_MOD_REP_OPT_RED, +} mbedtls_mpi_mod_rep_selector; + +/* Make mbedtls_mpi_mod_rep_selector and mbedtls_mpi_mod_ext_rep disjoint to + * make it easier to catch when they are accidentally swapped. */ +typedef enum { + MBEDTLS_MPI_MOD_EXT_REP_INVALID = 0, + MBEDTLS_MPI_MOD_EXT_REP_LE = 8, + MBEDTLS_MPI_MOD_EXT_REP_BE +} mbedtls_mpi_mod_ext_rep; + +typedef struct { + mbedtls_mpi_uint *p; + size_t limbs; +} mbedtls_mpi_mod_residue; + +typedef struct { + mbedtls_mpi_uint const *rr; /* The residue for 2^{2*n*biL} mod N */ + mbedtls_mpi_uint mm; /* Montgomery const for -N^{-1} mod 2^{ciL} */ +} mbedtls_mpi_mont_struct; + +typedef int (*mbedtls_mpi_modp_fn)(mbedtls_mpi_uint *X, size_t X_limbs); + +typedef struct { + mbedtls_mpi_modp_fn modp; /* The optimised reduction function pointer */ +} mbedtls_mpi_opt_red_struct; + +typedef struct { + const mbedtls_mpi_uint *p; + size_t limbs; // number of limbs + size_t bits; // bitlen of p + mbedtls_mpi_mod_rep_selector int_rep; // selector to signal the active member of the union + union rep { + /* if int_rep == #MBEDTLS_MPI_MOD_REP_MONTGOMERY */ + mbedtls_mpi_mont_struct mont; + /* if int_rep == #MBEDTLS_MPI_MOD_REP_OPT_RED */ + mbedtls_mpi_opt_red_struct ored; + } rep; +} mbedtls_mpi_mod_modulus; + +/** Setup a residue structure. + * + * The residue will be set up with the buffer \p p and modulus \p N. + * + * The memory pointed to by \p p will be used by the resulting residue structure. + * The value at the pointed-to memory will be the initial value of \p r and must + * hold a value that is less than the modulus. This value will be used as-is + * and interpreted according to the value of the `N->int_rep` field. + * + * The modulus \p N will be the modulus associated with \p r. The residue \p r + * should only be used in operations where the modulus is \p N. + * + * \param[out] r The address of the residue to setup. + * \param[in] N The address of the modulus related to \p r. + * \param[in] p The address of the limb array containing the value of \p r. + * The memory pointed to by \p p will be used by \p r and must + * not be modified in any way until after + * mbedtls_mpi_mod_residue_release() is called. The data + * pointed to by \p p must be less than the modulus (the value + * pointed to by `N->p`) and already in the representation + * indicated by `N->int_rep`. + * \param p_limbs The number of limbs of \p p. Must be the same as the number + * of limbs in the modulus \p N. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p p_limbs is less than the + * limbs in \p N or if \p p is not less than \p N. + */ +int mbedtls_mpi_mod_residue_setup(mbedtls_mpi_mod_residue *r, + const mbedtls_mpi_mod_modulus *N, + mbedtls_mpi_uint *p, + size_t p_limbs); + +/** Unbind elements of a residue structure. + * + * This function removes the reference to the limb array that was passed to + * mbedtls_mpi_mod_residue_setup() to make it safe to free or use again. + * + * This function invalidates \p r and it must not be used until after + * mbedtls_mpi_mod_residue_setup() is called on it again. + * + * \param[out] r The address of residue to release. + */ +void mbedtls_mpi_mod_residue_release(mbedtls_mpi_mod_residue *r); + +/** Initialize a modulus structure. + * + * \param[out] N The address of the modulus structure to initialize. + */ +void mbedtls_mpi_mod_modulus_init(mbedtls_mpi_mod_modulus *N); + +/** Setup a modulus structure. + * + * \param[out] N The address of the modulus structure to populate. + * \param[in] p The address of the limb array storing the value of \p N. + * The memory pointed to by \p p will be used by \p N and must + * not be modified in any way until after + * mbedtls_mpi_mod_modulus_free() is called. + * \param p_limbs The number of limbs of \p p. + * + * \return \c 0 if successful. + */ +int mbedtls_mpi_mod_modulus_setup(mbedtls_mpi_mod_modulus *N, + const mbedtls_mpi_uint *p, + size_t p_limbs); + +/** Setup an optimised-reduction compatible modulus structure. + * + * \param[out] N The address of the modulus structure to populate. + * \param[in] p The address of the limb array storing the value of \p N. + * The memory pointed to by \p p will be used by \p N and must + * not be modified in any way until after + * mbedtls_mpi_mod_modulus_free() is called. + * \param p_limbs The number of limbs of \p p. + * \param modp A pointer to the optimised reduction function to use. \p p. + * + * \return \c 0 if successful. + */ +int mbedtls_mpi_mod_optred_modulus_setup(mbedtls_mpi_mod_modulus *N, + const mbedtls_mpi_uint *p, + size_t p_limbs, + mbedtls_mpi_modp_fn modp); + +/** Free elements of a modulus structure. + * + * This function frees any memory allocated by mbedtls_mpi_mod_modulus_setup(). + * + * \warning This function does not free the limb array passed to + * mbedtls_mpi_mod_modulus_setup() only removes the reference to it, + * making it safe to free or to use it again. + * + * \param[in,out] N The address of the modulus structure to free. + */ +void mbedtls_mpi_mod_modulus_free(mbedtls_mpi_mod_modulus *N); + +/** \brief Multiply two residues, returning the residue modulo the specified + * modulus. + * + * \note Currently handles the case when `N->int_rep` is + * MBEDTLS_MPI_MOD_REP_MONTGOMERY. + * + * The size of the operation is determined by \p N. \p A, \p B and \p X must + * all be associated with the modulus \p N and must all have the same number + * of limbs as \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. They may not alias \p N (since they must be in canonical + * form, they cannot == \p N). + * + * \param[out] X The address of the result MPI. Must have the same + * number of limbs as \p N. + * On successful completion, \p X contains the result of + * the multiplication `A * B * R^-1` mod N where + * `R = 2^(biL * N->limbs)`. + * \param[in] A The address of the first MPI. + * \param[in] B The address of the second MPI. + * \param[in] N The address of the modulus. Used to perform a modulo + * operation on the result of the multiplication. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if all the parameters do not + * have the same number of limbs or \p N is invalid. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED on memory-allocation failure. + */ +int mbedtls_mpi_mod_mul(mbedtls_mpi_mod_residue *X, + const mbedtls_mpi_mod_residue *A, + const mbedtls_mpi_mod_residue *B, + const mbedtls_mpi_mod_modulus *N); + +/** + * \brief Perform a fixed-size modular subtraction. + * + * Calculate `A - B modulo N`. + * + * \p A, \p B and \p X must all have the same number of limbs as \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. + * + * \note This function does not check that \p A or \p B are in canonical + * form (that is, are < \p N) - that will have been done by + * mbedtls_mpi_mod_residue_setup(). + * + * \param[out] X The address of the result MPI. Must be initialized. + * Must have the same number of limbs as the modulus \p N. + * \param[in] A The address of the first MPI. + * \param[in] B The address of the second MPI. + * \param[in] N The address of the modulus. Used to perform a modulo + * operation on the result of the subtraction. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the given MPIs do not + * have the correct number of limbs. + */ +int mbedtls_mpi_mod_sub(mbedtls_mpi_mod_residue *X, + const mbedtls_mpi_mod_residue *A, + const mbedtls_mpi_mod_residue *B, + const mbedtls_mpi_mod_modulus *N); + +/** + * \brief Perform modular inversion of an MPI with respect to a modulus \p N. + * + * \p A and \p X must be associated with the modulus \p N and will therefore + * have the same number of limbs as \p N. + * + * \p X may be aliased to \p A. + * + * \warning Currently only supports prime moduli, but does not check for them. + * + * \param[out] X The modular inverse of \p A with respect to \p N. + * \param[in] A The number to calculate the modular inverse of. + * Must not be 0. + * \param[in] N The modulus to use. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p A and \p N do not + * have the same number of limbs. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p A is zero. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if couldn't allocate enough + * memory (needed for conversion to and from Mongtomery form + * when not in Montgomery form already, and for temporary use + * by the inversion calculation itself). + */ + +int mbedtls_mpi_mod_inv(mbedtls_mpi_mod_residue *X, + const mbedtls_mpi_mod_residue *A, + const mbedtls_mpi_mod_modulus *N); +/** + * \brief Perform a fixed-size modular addition. + * + * Calculate `A + B modulo N`. + * + * \p A, \p B and \p X must all be associated with the modulus \p N and must + * all have the same number of limbs as \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. + * + * \note This function does not check that \p A or \p B are in canonical + * form (that is, are < \p N) - that will have been done by + * mbedtls_mpi_mod_residue_setup(). + * + * \param[out] X The address of the result residue. Must be initialized. + * Must have the same number of limbs as the modulus \p N. + * \param[in] A The address of the first input residue. + * \param[in] B The address of the second input residue. + * \param[in] N The address of the modulus. Used to perform a modulo + * operation on the result of the addition. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the given MPIs do not + * have the correct number of limbs. + */ +int mbedtls_mpi_mod_add(mbedtls_mpi_mod_residue *X, + const mbedtls_mpi_mod_residue *A, + const mbedtls_mpi_mod_residue *B, + const mbedtls_mpi_mod_modulus *N); + +/** Generate a random number uniformly in a range. + * + * This function generates a random number between \p min inclusive and + * \p N exclusive. + * + * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) + * when the RNG is a suitably parametrized instance of HMAC_DRBG + * and \p min is \c 1. + * + * \note There are `N - min` possible outputs. The lower bound + * \p min can be reached, but the upper bound \p N cannot. + * + * \param X The destination residue. + * \param min The minimum value to return. It must be strictly smaller + * than \b N. + * \param N The modulus. + * This is the upper bound of the output range, exclusive. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was + * unable to find a suitable value within a limited number + * of attempts. This has a negligible probability if \p N + * is significantly larger than \p min, which is the case + * for all usual cryptographic applications. + */ +int mbedtls_mpi_mod_random(mbedtls_mpi_mod_residue *X, + mbedtls_mpi_uint min, + const mbedtls_mpi_mod_modulus *N, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** Read a residue from a byte buffer. + * + * The residue will be automatically converted to the internal representation + * based on the value of the `N->int_rep` field. + * + * The modulus \p N will be the modulus associated with \p r. The residue \p r + * should only be used in operations where the modulus is \p N or a modulus + * equivalent to \p N (in the sense that all their fields or memory pointed by + * their fields hold the same value). + * + * \param[out] r The address of the residue. It must have exactly the same + * number of limbs as the modulus \p N. + * \param[in] N The address of the modulus. + * \param[in] buf The input buffer to import from. + * \param buflen The length in bytes of \p buf. + * \param ext_rep The endianness of the number in the input buffer. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p r isn't + * large enough to hold the value in \p buf. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p ext_rep + * is invalid or the value in the buffer is not less than \p N. + */ +int mbedtls_mpi_mod_read(mbedtls_mpi_mod_residue *r, + const mbedtls_mpi_mod_modulus *N, + const unsigned char *buf, + size_t buflen, + mbedtls_mpi_mod_ext_rep ext_rep); + +/** Write a residue into a byte buffer. + * + * The modulus \p N must be the modulus associated with \p r (see + * mbedtls_mpi_mod_residue_setup() and mbedtls_mpi_mod_read()). + * + * The residue will be automatically converted from the internal representation + * based on the value of `N->int_rep` field. + * + * \warning If the buffer is smaller than `N->bits`, the number of + * leading zeroes is leaked through timing. If \p r is + * secret, the caller must ensure that \p buflen is at least + * (`N->bits`+7)/8. + * + * \param[in] r The address of the residue. It must have the same number of + * limbs as the modulus \p N. (\p r is an input parameter, but + * its value will be modified during execution and restored + * before the function returns.) + * \param[in] N The address of the modulus associated with \p r. + * \param[out] buf The output buffer to export to. + * \param buflen The length in bytes of \p buf. + * \param ext_rep The endianness in which the number should be written into + * the output buffer. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p buf isn't + * large enough to hold the value of \p r (without leading + * zeroes). + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if \p ext_rep is invalid. + * \return #MBEDTLS_ERR_MPI_ALLOC_FAILED if couldn't allocate enough + * memory for conversion. Can occur only for moduli with + * MBEDTLS_MPI_MOD_REP_MONTGOMERY. + */ +int mbedtls_mpi_mod_write(const mbedtls_mpi_mod_residue *r, + const mbedtls_mpi_mod_modulus *N, + unsigned char *buf, + size_t buflen, + mbedtls_mpi_mod_ext_rep ext_rep); + +#endif /* MBEDTLS_BIGNUM_MOD_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw.h index c5ff937..9b535f9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw.h @@ -1,428 +1,428 @@ -/** - * Low-level modular bignum functions - * - * This interface should only be used by the higher-level modular bignum - * module (bignum_mod.c) and the ECP module (ecp.c, ecp_curves.c). All other - * modules should use the high-level modular bignum interface (bignum_mod.h) - * or the legacy bignum interface (bignum.h). - * - * This is a low-level interface to operations on integers modulo which - * has no protection against passing invalid arguments such as arrays of - * the wrong size. The functions in bignum_mod.h provide a higher-level - * interface that includes protections against accidental misuse, at the - * expense of code size and sometimes more cumbersome memory management. - * - * The functions in this module obey the following conventions unless - * explicitly indicated otherwise: - * - **Modulus parameters**: the modulus is passed as a pointer to a structure - * of type #mbedtls_mpi_mod_modulus. The structure must be set up with an - * array of limbs storing the bignum value of the modulus. The modulus must - * be odd and is assumed to have no leading zeroes. The modulus is usually - * named \c N and is usually input-only. - * - **Bignum parameters**: Bignums are passed as pointers to an array of - * limbs. A limb has the type #mbedtls_mpi_uint. Unless otherwise specified: - * - Bignum parameters called \c A, \c B, ... are inputs, and are not - * modified by the function. - * - Bignum parameters called \c X, \c Y are outputs or input-output. - * The initial content of output-only parameters is ignored. - * - \c T is a temporary storage area. The initial content of such a - * parameter is ignored and the final content is unspecified. - * - **Bignum sizes**: bignum sizes are usually expressed by the \c limbs - * member of the modulus argument. All bignum parameters must have the same - * number of limbs as the modulus. All bignum sizes must be at least 1 and - * must be significantly less than #SIZE_MAX. The behavior if a size is 0 is - * undefined. - * - **Bignum representation**: the representation of inputs and outputs is - * specified by the \c int_rep field of the modulus for arithmetic - * functions. Utility functions may allow for different representation. - * - **Parameter ordering**: for bignum parameters, outputs come before inputs. - * The modulus is passed after other bignum input parameters. Temporaries - * come last. - * - **Aliasing**: in general, output bignums may be aliased to one or more - * inputs. Modulus values may not be aliased to any other parameter. Outputs - * may not be aliased to one another. Temporaries may not be aliased to any - * other parameter. - * - **Overlap**: apart from aliasing of limb array pointers (where two - * arguments are equal pointers), overlap is not supported and may result - * in undefined behavior. - * - **Error handling**: This is a low-level module. Functions generally do not - * try to protect against invalid arguments such as nonsensical sizes or - * null pointers. Note that passing bignums with a different size than the - * modulus may lead to buffer overflows. Some functions which allocate - * memory or handle reading/writing of bignums will return an error if - * memory allocation fails or if buffer sizes are invalid. - * - **Modular representatives**: all functions expect inputs to be in the - * range [0, \c N - 1] and guarantee outputs in the range [0, \c N - 1]. If - * an input is out of range, outputs are fully unspecified, though bignum - * values out of range should not cause buffer overflows (beware that this is - * not extensively tested). - */ - -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BIGNUM_MOD_RAW_H -#define MBEDTLS_BIGNUM_MOD_RAW_H - -#include "common.h" - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -#include "bignum_mod.h" - -/** - * \brief Perform a safe conditional copy of an MPI which doesn't reveal - * whether the assignment was done or not. - * - * The size to copy is determined by \p N. - * - * \param[out] X The address of the destination MPI. - * This must be initialized. Must have enough limbs to - * store the full value of \p A. - * \param[in] A The address of the source MPI. This must be initialized. - * \param[in] N The address of the modulus related to \p X and \p A. - * \param assign The condition deciding whether to perform the - * assignment or not. Must be either 0 or 1: - * * \c 1: Perform the assignment `X = A`. - * * \c 0: Keep the original value of \p X. - * - * \note This function avoids leaking any information about whether - * the assignment was done or not. - * - * \warning If \p assign is neither 0 nor 1, the result of this function - * is indeterminate, and the resulting value in \p X might be - * neither its original value nor the value in \p A. - */ -void mbedtls_mpi_mod_raw_cond_assign(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_mod_modulus *N, - unsigned char assign); - -/** - * \brief Perform a safe conditional swap of two MPIs which doesn't reveal - * whether the swap was done or not. - * - * The size to swap is determined by \p N. - * - * \param[in,out] X The address of the first MPI. This must be initialized. - * \param[in,out] Y The address of the second MPI. This must be initialized. - * \param[in] N The address of the modulus related to \p X and \p Y. - * \param swap The condition deciding whether to perform - * the swap or not. Must be either 0 or 1: - * * \c 1: Swap the values of \p X and \p Y. - * * \c 0: Keep the original values of \p X and \p Y. - * - * \note This function avoids leaking any information about whether - * the swap was done or not. - * - * \warning If \p swap is neither 0 nor 1, the result of this function - * is indeterminate, and both \p X and \p Y might end up with - * values different to either of the original ones. - */ -void mbedtls_mpi_mod_raw_cond_swap(mbedtls_mpi_uint *X, - mbedtls_mpi_uint *Y, - const mbedtls_mpi_mod_modulus *N, - unsigned char swap); - -/** Import X from unsigned binary data. - * - * The MPI needs to have enough limbs to store the full value (including any - * most significant zero bytes in the input). - * - * \param[out] X The address of the MPI. The size is determined by \p N. - * (In particular, it must have at least as many limbs as - * the modulus \p N.) - * \param[in] N The address of the modulus related to \p X. - * \param[in] input The input buffer to import from. - * \param input_length The length in bytes of \p input. - * \param ext_rep The endianness of the number in the input buffer. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't - * large enough to hold the value in \p input. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the external representation - * of \p N is invalid or \p X is not less than \p N. - */ -int mbedtls_mpi_mod_raw_read(mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N, - const unsigned char *input, - size_t input_length, - mbedtls_mpi_mod_ext_rep ext_rep); - -/** Export A into unsigned binary data. - * - * \param[in] A The address of the MPI. The size is determined by \p N. - * (In particular, it must have at least as many limbs as - * the modulus \p N.) - * \param[in] N The address of the modulus related to \p A. - * \param[out] output The output buffer to export to. - * \param output_length The length in bytes of \p output. - * \param ext_rep The endianness in which the number should be written into the output buffer. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't - * large enough to hold the value of \p A. - * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the external representation - * of \p N is invalid. - */ -int mbedtls_mpi_mod_raw_write(const mbedtls_mpi_uint *A, - const mbedtls_mpi_mod_modulus *N, - unsigned char *output, - size_t output_length, - mbedtls_mpi_mod_ext_rep ext_rep); - -/** \brief Subtract two MPIs, returning the residue modulo the specified - * modulus. - * - * The size of the operation is determined by \p N. \p A and \p B must have - * the same number of limbs as \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. - * - * \param[out] X The address of the result MPI. - * This must be initialized. Must have enough limbs to - * store the full value of the result. - * \param[in] A The address of the first MPI. This must be initialized. - * \param[in] B The address of the second MPI. This must be initialized. - * \param[in] N The address of the modulus. Used to perform a modulo - * operation on the result of the subtraction. - */ -void mbedtls_mpi_mod_raw_sub(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - const mbedtls_mpi_mod_modulus *N); - -/** \brief Multiply two MPIs, returning the residue modulo the specified - * modulus. - * - * \note Currently handles the case when `N->int_rep` is - * MBEDTLS_MPI_MOD_REP_MONTGOMERY. - * - * The size of the operation is determined by \p N. \p A, \p B and \p X must - * all be associated with the modulus \p N and must all have the same number - * of limbs as \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. They may not alias \p N (since they must be in canonical - * form, they cannot == \p N). - * - * \param[out] X The address of the result MPI. Must have the same - * number of limbs as \p N. - * On successful completion, \p X contains the result of - * the multiplication `A * B * R^-1` mod N where - * `R = 2^(biL * N->limbs)`. - * \param[in] A The address of the first MPI. - * \param[in] B The address of the second MPI. - * \param[in] N The address of the modulus. Used to perform a modulo - * operation on the result of the multiplication. - * \param[in,out] T Temporary storage of size at least 2 * N->limbs + 1 - * limbs. Its initial content is unused and - * its final content is indeterminate. - * It must not alias or otherwise overlap any of the - * other parameters. - */ -void mbedtls_mpi_mod_raw_mul(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - const mbedtls_mpi_mod_modulus *N, - mbedtls_mpi_uint *T); - -/** - * \brief Returns the number of limbs of working memory required for - * a call to `mbedtls_mpi_mod_raw_inv_prime()`. - * - * \note This will always be at least - * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)`, - * i.e. sufficient for a call to `mbedtls_mpi_core_montmul()`. - * - * \param AN_limbs The number of limbs in the input `A` and the modulus `N` - * (they must be the same size) that will be given to - * `mbedtls_mpi_mod_raw_inv_prime()`. - * - * \return The number of limbs of working memory required by - * `mbedtls_mpi_mod_raw_inv_prime()`. - */ -size_t mbedtls_mpi_mod_raw_inv_prime_working_limbs(size_t AN_limbs); - -/** - * \brief Perform fixed-width modular inversion of a Montgomery-form MPI with - * respect to a modulus \p N that must be prime. - * - * \p X may be aliased to \p A, but not to \p N or \p RR. - * - * \param[out] X The modular inverse of \p A with respect to \p N. - * Will be in Montgomery form. - * \param[in] A The number to calculate the modular inverse of. - * Must be in Montgomery form. Must not be 0. - * \param[in] N The modulus, as a little-endian array of length \p AN_limbs. - * Must be prime. - * \param AN_limbs The number of limbs in \p A, \p N and \p RR. - * \param[in] RR The precomputed residue of 2^{2*biL} modulo N, as a little- - * endian array of length \p AN_limbs. - * \param[in,out] T Temporary storage of at least the number of limbs returned - * by `mbedtls_mpi_mod_raw_inv_prime_working_limbs()`. - * Its initial content is unused and its final content is - * indeterminate. - * It must not alias or otherwise overlap any of the other - * parameters. - * It is up to the caller to zeroize \p T when it is no - * longer needed, and before freeing it if it was dynamically - * allocated. - */ -void mbedtls_mpi_mod_raw_inv_prime(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *N, - size_t AN_limbs, - const mbedtls_mpi_uint *RR, - mbedtls_mpi_uint *T); - -/** - * \brief Perform a known-size modular addition. - * - * Calculate `A + B modulo N`. - * - * The number of limbs in each operand, and the result, is given by the - * modulus \p N. - * - * \p X may be aliased to \p A or \p B, or even both, but may not overlap - * either otherwise. - * - * \param[out] X The result of the modular addition. - * \param[in] A Little-endian presentation of the left operand. This - * must be smaller than \p N. - * \param[in] B Little-endian presentation of the right operand. This - * must be smaller than \p N. - * \param[in] N The address of the modulus. - */ -void mbedtls_mpi_mod_raw_add(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_uint *B, - const mbedtls_mpi_mod_modulus *N); - -/** Convert an MPI from canonical representation (little-endian limb array) - * to the representation associated with the modulus. - * - * \param[in,out] X The limb array to convert. - * It must have as many limbs as \p N. - * It is converted in place. - * If this function returns an error, the content of \p X - * is unspecified. - * \param[in] N The modulus structure. - * - * \return \c 0 if successful. - * Otherwise an \c MBEDTLS_ERR_MPI_xxx error code. - */ -int mbedtls_mpi_mod_raw_canonical_to_modulus_rep( - mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N); - -/** Convert an MPI from the representation associated with the modulus - * to canonical representation (little-endian limb array). - * - * \param[in,out] X The limb array to convert. - * It must have as many limbs as \p N. - * It is converted in place. - * If this function returns an error, the content of \p X - * is unspecified. - * \param[in] N The modulus structure. - * - * \return \c 0 if successful. - * Otherwise an \c MBEDTLS_ERR_MPI_xxx error code. - */ -int mbedtls_mpi_mod_raw_modulus_to_canonical_rep( - mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N); - -/** Generate a random number uniformly in a range. - * - * This function generates a random number between \p min inclusive and - * \p N exclusive. - * - * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) - * when the RNG is a suitably parametrized instance of HMAC_DRBG - * and \p min is \c 1. - * - * \note There are `N - min` possible outputs. The lower bound - * \p min can be reached, but the upper bound \p N cannot. - * - * \param X The destination MPI, in canonical representation modulo \p N. - * It must not be aliased with \p N or otherwise overlap it. - * \param min The minimum value to return. It must be strictly smaller - * than \b N. - * \param N The modulus. - * This is the upper bound of the output range, exclusive. - * \param f_rng The RNG function to use. This must not be \c NULL. - * \param p_rng The RNG parameter to be passed to \p f_rng. - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was - * unable to find a suitable value within a limited number - * of attempts. This has a negligible probability if \p N - * is significantly larger than \p min, which is the case - * for all usual cryptographic applications. - */ -int mbedtls_mpi_mod_raw_random(mbedtls_mpi_uint *X, - mbedtls_mpi_uint min, - const mbedtls_mpi_mod_modulus *N, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** Convert an MPI into Montgomery form. - * - * \param X The address of the MPI. - * Must have the same number of limbs as \p N. - * \param N The address of the modulus, which gives the size of - * the base `R` = 2^(biL*N->limbs). - * - * \return \c 0 if successful. - */ -int mbedtls_mpi_mod_raw_to_mont_rep(mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N); - -/** Convert an MPI back from Montgomery representation. - * - * \param X The address of the MPI. - * Must have the same number of limbs as \p N. - * \param N The address of the modulus, which gives the size of - * the base `R`= 2^(biL*N->limbs). - * - * \return \c 0 if successful. - */ -int mbedtls_mpi_mod_raw_from_mont_rep(mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N); - -/** \brief Perform fixed width modular negation. - * - * The size of the operation is determined by \p N. \p A must have - * the same number of limbs as \p N. - * - * \p X may be aliased to \p A. - * - * \param[out] X The result of the modular negation. - * This must be initialized. - * \param[in] A Little-endian presentation of the input operand. This - * must be less than or equal to \p N. - * \param[in] N The modulus to use. - */ -void mbedtls_mpi_mod_raw_neg(mbedtls_mpi_uint *X, - const mbedtls_mpi_uint *A, - const mbedtls_mpi_mod_modulus *N); - -#endif /* MBEDTLS_BIGNUM_MOD_RAW_H */ +/** + * Low-level modular bignum functions + * + * This interface should only be used by the higher-level modular bignum + * module (bignum_mod.c) and the ECP module (ecp.c, ecp_curves.c). All other + * modules should use the high-level modular bignum interface (bignum_mod.h) + * or the legacy bignum interface (bignum.h). + * + * This is a low-level interface to operations on integers modulo which + * has no protection against passing invalid arguments such as arrays of + * the wrong size. The functions in bignum_mod.h provide a higher-level + * interface that includes protections against accidental misuse, at the + * expense of code size and sometimes more cumbersome memory management. + * + * The functions in this module obey the following conventions unless + * explicitly indicated otherwise: + * - **Modulus parameters**: the modulus is passed as a pointer to a structure + * of type #mbedtls_mpi_mod_modulus. The structure must be set up with an + * array of limbs storing the bignum value of the modulus. The modulus must + * be odd and is assumed to have no leading zeroes. The modulus is usually + * named \c N and is usually input-only. + * - **Bignum parameters**: Bignums are passed as pointers to an array of + * limbs. A limb has the type #mbedtls_mpi_uint. Unless otherwise specified: + * - Bignum parameters called \c A, \c B, ... are inputs, and are not + * modified by the function. + * - Bignum parameters called \c X, \c Y are outputs or input-output. + * The initial content of output-only parameters is ignored. + * - \c T is a temporary storage area. The initial content of such a + * parameter is ignored and the final content is unspecified. + * - **Bignum sizes**: bignum sizes are usually expressed by the \c limbs + * member of the modulus argument. All bignum parameters must have the same + * number of limbs as the modulus. All bignum sizes must be at least 1 and + * must be significantly less than #SIZE_MAX. The behavior if a size is 0 is + * undefined. + * - **Bignum representation**: the representation of inputs and outputs is + * specified by the \c int_rep field of the modulus for arithmetic + * functions. Utility functions may allow for different representation. + * - **Parameter ordering**: for bignum parameters, outputs come before inputs. + * The modulus is passed after other bignum input parameters. Temporaries + * come last. + * - **Aliasing**: in general, output bignums may be aliased to one or more + * inputs. Modulus values may not be aliased to any other parameter. Outputs + * may not be aliased to one another. Temporaries may not be aliased to any + * other parameter. + * - **Overlap**: apart from aliasing of limb array pointers (where two + * arguments are equal pointers), overlap is not supported and may result + * in undefined behavior. + * - **Error handling**: This is a low-level module. Functions generally do not + * try to protect against invalid arguments such as nonsensical sizes or + * null pointers. Note that passing bignums with a different size than the + * modulus may lead to buffer overflows. Some functions which allocate + * memory or handle reading/writing of bignums will return an error if + * memory allocation fails or if buffer sizes are invalid. + * - **Modular representatives**: all functions expect inputs to be in the + * range [0, \c N - 1] and guarantee outputs in the range [0, \c N - 1]. If + * an input is out of range, outputs are fully unspecified, though bignum + * values out of range should not cause buffer overflows (beware that this is + * not extensively tested). + */ + +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BIGNUM_MOD_RAW_H +#define MBEDTLS_BIGNUM_MOD_RAW_H + +#include "common.h" + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +#include "bignum_mod.h" + +/** + * \brief Perform a safe conditional copy of an MPI which doesn't reveal + * whether the assignment was done or not. + * + * The size to copy is determined by \p N. + * + * \param[out] X The address of the destination MPI. + * This must be initialized. Must have enough limbs to + * store the full value of \p A. + * \param[in] A The address of the source MPI. This must be initialized. + * \param[in] N The address of the modulus related to \p X and \p A. + * \param assign The condition deciding whether to perform the + * assignment or not. Must be either 0 or 1: + * * \c 1: Perform the assignment `X = A`. + * * \c 0: Keep the original value of \p X. + * + * \note This function avoids leaking any information about whether + * the assignment was done or not. + * + * \warning If \p assign is neither 0 nor 1, the result of this function + * is indeterminate, and the resulting value in \p X might be + * neither its original value nor the value in \p A. + */ +void mbedtls_mpi_mod_raw_cond_assign(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_mod_modulus *N, + unsigned char assign); + +/** + * \brief Perform a safe conditional swap of two MPIs which doesn't reveal + * whether the swap was done or not. + * + * The size to swap is determined by \p N. + * + * \param[in,out] X The address of the first MPI. This must be initialized. + * \param[in,out] Y The address of the second MPI. This must be initialized. + * \param[in] N The address of the modulus related to \p X and \p Y. + * \param swap The condition deciding whether to perform + * the swap or not. Must be either 0 or 1: + * * \c 1: Swap the values of \p X and \p Y. + * * \c 0: Keep the original values of \p X and \p Y. + * + * \note This function avoids leaking any information about whether + * the swap was done or not. + * + * \warning If \p swap is neither 0 nor 1, the result of this function + * is indeterminate, and both \p X and \p Y might end up with + * values different to either of the original ones. + */ +void mbedtls_mpi_mod_raw_cond_swap(mbedtls_mpi_uint *X, + mbedtls_mpi_uint *Y, + const mbedtls_mpi_mod_modulus *N, + unsigned char swap); + +/** Import X from unsigned binary data. + * + * The MPI needs to have enough limbs to store the full value (including any + * most significant zero bytes in the input). + * + * \param[out] X The address of the MPI. The size is determined by \p N. + * (In particular, it must have at least as many limbs as + * the modulus \p N.) + * \param[in] N The address of the modulus related to \p X. + * \param[in] input The input buffer to import from. + * \param input_length The length in bytes of \p input. + * \param ext_rep The endianness of the number in the input buffer. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p X isn't + * large enough to hold the value in \p input. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the external representation + * of \p N is invalid or \p X is not less than \p N. + */ +int mbedtls_mpi_mod_raw_read(mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N, + const unsigned char *input, + size_t input_length, + mbedtls_mpi_mod_ext_rep ext_rep); + +/** Export A into unsigned binary data. + * + * \param[in] A The address of the MPI. The size is determined by \p N. + * (In particular, it must have at least as many limbs as + * the modulus \p N.) + * \param[in] N The address of the modulus related to \p A. + * \param[out] output The output buffer to export to. + * \param output_length The length in bytes of \p output. + * \param ext_rep The endianness in which the number should be written into the output buffer. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL if \p output isn't + * large enough to hold the value of \p A. + * \return #MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the external representation + * of \p N is invalid. + */ +int mbedtls_mpi_mod_raw_write(const mbedtls_mpi_uint *A, + const mbedtls_mpi_mod_modulus *N, + unsigned char *output, + size_t output_length, + mbedtls_mpi_mod_ext_rep ext_rep); + +/** \brief Subtract two MPIs, returning the residue modulo the specified + * modulus. + * + * The size of the operation is determined by \p N. \p A and \p B must have + * the same number of limbs as \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. + * + * \param[out] X The address of the result MPI. + * This must be initialized. Must have enough limbs to + * store the full value of the result. + * \param[in] A The address of the first MPI. This must be initialized. + * \param[in] B The address of the second MPI. This must be initialized. + * \param[in] N The address of the modulus. Used to perform a modulo + * operation on the result of the subtraction. + */ +void mbedtls_mpi_mod_raw_sub(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + const mbedtls_mpi_mod_modulus *N); + +/** \brief Multiply two MPIs, returning the residue modulo the specified + * modulus. + * + * \note Currently handles the case when `N->int_rep` is + * MBEDTLS_MPI_MOD_REP_MONTGOMERY. + * + * The size of the operation is determined by \p N. \p A, \p B and \p X must + * all be associated with the modulus \p N and must all have the same number + * of limbs as \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. They may not alias \p N (since they must be in canonical + * form, they cannot == \p N). + * + * \param[out] X The address of the result MPI. Must have the same + * number of limbs as \p N. + * On successful completion, \p X contains the result of + * the multiplication `A * B * R^-1` mod N where + * `R = 2^(biL * N->limbs)`. + * \param[in] A The address of the first MPI. + * \param[in] B The address of the second MPI. + * \param[in] N The address of the modulus. Used to perform a modulo + * operation on the result of the multiplication. + * \param[in,out] T Temporary storage of size at least 2 * N->limbs + 1 + * limbs. Its initial content is unused and + * its final content is indeterminate. + * It must not alias or otherwise overlap any of the + * other parameters. + */ +void mbedtls_mpi_mod_raw_mul(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + const mbedtls_mpi_mod_modulus *N, + mbedtls_mpi_uint *T); + +/** + * \brief Returns the number of limbs of working memory required for + * a call to `mbedtls_mpi_mod_raw_inv_prime()`. + * + * \note This will always be at least + * `mbedtls_mpi_core_montmul_working_limbs(AN_limbs)`, + * i.e. sufficient for a call to `mbedtls_mpi_core_montmul()`. + * + * \param AN_limbs The number of limbs in the input `A` and the modulus `N` + * (they must be the same size) that will be given to + * `mbedtls_mpi_mod_raw_inv_prime()`. + * + * \return The number of limbs of working memory required by + * `mbedtls_mpi_mod_raw_inv_prime()`. + */ +size_t mbedtls_mpi_mod_raw_inv_prime_working_limbs(size_t AN_limbs); + +/** + * \brief Perform fixed-width modular inversion of a Montgomery-form MPI with + * respect to a modulus \p N that must be prime. + * + * \p X may be aliased to \p A, but not to \p N or \p RR. + * + * \param[out] X The modular inverse of \p A with respect to \p N. + * Will be in Montgomery form. + * \param[in] A The number to calculate the modular inverse of. + * Must be in Montgomery form. Must not be 0. + * \param[in] N The modulus, as a little-endian array of length \p AN_limbs. + * Must be prime. + * \param AN_limbs The number of limbs in \p A, \p N and \p RR. + * \param[in] RR The precomputed residue of 2^{2*biL} modulo N, as a little- + * endian array of length \p AN_limbs. + * \param[in,out] T Temporary storage of at least the number of limbs returned + * by `mbedtls_mpi_mod_raw_inv_prime_working_limbs()`. + * Its initial content is unused and its final content is + * indeterminate. + * It must not alias or otherwise overlap any of the other + * parameters. + * It is up to the caller to zeroize \p T when it is no + * longer needed, and before freeing it if it was dynamically + * allocated. + */ +void mbedtls_mpi_mod_raw_inv_prime(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *N, + size_t AN_limbs, + const mbedtls_mpi_uint *RR, + mbedtls_mpi_uint *T); + +/** + * \brief Perform a known-size modular addition. + * + * Calculate `A + B modulo N`. + * + * The number of limbs in each operand, and the result, is given by the + * modulus \p N. + * + * \p X may be aliased to \p A or \p B, or even both, but may not overlap + * either otherwise. + * + * \param[out] X The result of the modular addition. + * \param[in] A Little-endian presentation of the left operand. This + * must be smaller than \p N. + * \param[in] B Little-endian presentation of the right operand. This + * must be smaller than \p N. + * \param[in] N The address of the modulus. + */ +void mbedtls_mpi_mod_raw_add(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_uint *B, + const mbedtls_mpi_mod_modulus *N); + +/** Convert an MPI from canonical representation (little-endian limb array) + * to the representation associated with the modulus. + * + * \param[in,out] X The limb array to convert. + * It must have as many limbs as \p N. + * It is converted in place. + * If this function returns an error, the content of \p X + * is unspecified. + * \param[in] N The modulus structure. + * + * \return \c 0 if successful. + * Otherwise an \c MBEDTLS_ERR_MPI_xxx error code. + */ +int mbedtls_mpi_mod_raw_canonical_to_modulus_rep( + mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N); + +/** Convert an MPI from the representation associated with the modulus + * to canonical representation (little-endian limb array). + * + * \param[in,out] X The limb array to convert. + * It must have as many limbs as \p N. + * It is converted in place. + * If this function returns an error, the content of \p X + * is unspecified. + * \param[in] N The modulus structure. + * + * \return \c 0 if successful. + * Otherwise an \c MBEDTLS_ERR_MPI_xxx error code. + */ +int mbedtls_mpi_mod_raw_modulus_to_canonical_rep( + mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N); + +/** Generate a random number uniformly in a range. + * + * This function generates a random number between \p min inclusive and + * \p N exclusive. + * + * The procedure complies with RFC 6979 §3.3 (deterministic ECDSA) + * when the RNG is a suitably parametrized instance of HMAC_DRBG + * and \p min is \c 1. + * + * \note There are `N - min` possible outputs. The lower bound + * \p min can be reached, but the upper bound \p N cannot. + * + * \param X The destination MPI, in canonical representation modulo \p N. + * It must not be aliased with \p N or otherwise overlap it. + * \param min The minimum value to return. It must be strictly smaller + * than \b N. + * \param N The modulus. + * This is the upper bound of the output range, exclusive. + * \param f_rng The RNG function to use. This must not be \c NULL. + * \param p_rng The RNG parameter to be passed to \p f_rng. + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_MPI_NOT_ACCEPTABLE if the implementation was + * unable to find a suitable value within a limited number + * of attempts. This has a negligible probability if \p N + * is significantly larger than \p min, which is the case + * for all usual cryptographic applications. + */ +int mbedtls_mpi_mod_raw_random(mbedtls_mpi_uint *X, + mbedtls_mpi_uint min, + const mbedtls_mpi_mod_modulus *N, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** Convert an MPI into Montgomery form. + * + * \param X The address of the MPI. + * Must have the same number of limbs as \p N. + * \param N The address of the modulus, which gives the size of + * the base `R` = 2^(biL*N->limbs). + * + * \return \c 0 if successful. + */ +int mbedtls_mpi_mod_raw_to_mont_rep(mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N); + +/** Convert an MPI back from Montgomery representation. + * + * \param X The address of the MPI. + * Must have the same number of limbs as \p N. + * \param N The address of the modulus, which gives the size of + * the base `R`= 2^(biL*N->limbs). + * + * \return \c 0 if successful. + */ +int mbedtls_mpi_mod_raw_from_mont_rep(mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N); + +/** \brief Perform fixed width modular negation. + * + * The size of the operation is determined by \p N. \p A must have + * the same number of limbs as \p N. + * + * \p X may be aliased to \p A. + * + * \param[out] X The result of the modular negation. + * This must be initialized. + * \param[in] A Little-endian presentation of the input operand. This + * must be less than or equal to \p N. + * \param[in] N The modulus to use. + */ +void mbedtls_mpi_mod_raw_neg(mbedtls_mpi_uint *X, + const mbedtls_mpi_uint *A, + const mbedtls_mpi_mod_modulus *N); + +#endif /* MBEDTLS_BIGNUM_MOD_RAW_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw_invasive.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw_invasive.h index ead8394..d0b0f3e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw_invasive.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bignum_mod_raw_invasive.h @@ -1,46 +1,46 @@ -/** - * \file bignum_mod_raw_invasive.h - * - * \brief Function declarations for invasive functions of Low-level - * modular bignum. - */ -/** - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H -#define MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H - -#include "common.h" -#include "mbedtls/bignum.h" -#include "bignum_mod.h" - -#if defined(MBEDTLS_TEST_HOOKS) - -/** Convert the result of a quasi-reduction to its canonical representative. - * - * \param[in,out] X The address of the MPI to be converted. Must have the - * same number of limbs as \p N. The input value must - * be in range 0 <= X < 2N. - * \param[in] N The address of the modulus. - */ -MBEDTLS_STATIC_TESTABLE -void mbedtls_mpi_mod_raw_fix_quasi_reduction(mbedtls_mpi_uint *X, - const mbedtls_mpi_mod_modulus *N); - -#endif /* MBEDTLS_TEST_HOOKS */ - -#endif /* MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H */ +/** + * \file bignum_mod_raw_invasive.h + * + * \brief Function declarations for invasive functions of Low-level + * modular bignum. + */ +/** + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H +#define MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H + +#include "common.h" +#include "mbedtls/bignum.h" +#include "bignum_mod.h" + +#if defined(MBEDTLS_TEST_HOOKS) + +/** Convert the result of a quasi-reduction to its canonical representative. + * + * \param[in,out] X The address of the MPI to be converted. Must have the + * same number of limbs as \p N. The input value must + * be in range 0 <= X < 2N. + * \param[in] N The address of the modulus. + */ +MBEDTLS_STATIC_TESTABLE +void mbedtls_mpi_mod_raw_fix_quasi_reduction(mbedtls_mpi_uint *X, + const mbedtls_mpi_mod_modulus *N); + +#endif /* MBEDTLS_TEST_HOOKS */ + +#endif /* MBEDTLS_BIGNUM_MOD_RAW_INVASIVE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bn_mul.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bn_mul.h index ab1a66a..2c60848 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bn_mul.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/bn_mul.h @@ -1,1106 +1,1106 @@ -/** - * \file bn_mul.h - * - * \brief Multi-precision integer library - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -/* - * Multiply source vector [s] with b, add result - * to destination vector [d] and set carry c. - * - * Currently supports: - * - * . IA-32 (386+) . AMD64 / EM64T - * . IA-32 (SSE2) . Motorola 68000 - * . PowerPC, 32-bit . MicroBlaze - * . PowerPC, 64-bit . TriCore - * . SPARC v8 . ARM v3+ - * . Alpha . MIPS32 - * . C, longlong . C, generic - */ -#ifndef MBEDTLS_BN_MUL_H -#define MBEDTLS_BN_MUL_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/bignum.h" - - -/* - * Conversion macros for embedded constants: - * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 - */ -#if defined(MBEDTLS_HAVE_INT32) - -#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \ - ((mbedtls_mpi_uint) (a) << 0) | \ - ((mbedtls_mpi_uint) (b) << 8) | \ - ((mbedtls_mpi_uint) (c) << 16) | \ - ((mbedtls_mpi_uint) (d) << 24) - -#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \ - MBEDTLS_BYTES_TO_T_UINT_4(a, b, 0, 0) - -#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \ - MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d), \ - MBEDTLS_BYTES_TO_T_UINT_4(e, f, g, h) - -#else /* 64-bits */ - -#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \ - ((mbedtls_mpi_uint) (a) << 0) | \ - ((mbedtls_mpi_uint) (b) << 8) | \ - ((mbedtls_mpi_uint) (c) << 16) | \ - ((mbedtls_mpi_uint) (d) << 24) | \ - ((mbedtls_mpi_uint) (e) << 32) | \ - ((mbedtls_mpi_uint) (f) << 40) | \ - ((mbedtls_mpi_uint) (g) << 48) | \ - ((mbedtls_mpi_uint) (h) << 56) - -#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \ - MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, 0, 0, 0, 0) - -#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \ - MBEDTLS_BYTES_TO_T_UINT_8(a, b, 0, 0, 0, 0, 0, 0) - -#endif /* bits in mbedtls_mpi_uint */ - -/* *INDENT-OFF* */ -#if defined(MBEDTLS_HAVE_ASM) - -/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */ -#if defined(__GNUC__) && \ - ( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 ) - -/* - * GCC < 5.0 treated the x86 ebx (which is used for the GOT) as a - * fixed reserved register when building as PIC, leading to errors - * like: bn_mul.h:46:13: error: PIC register clobbered by 'ebx' in 'asm' - * - * This is fixed by an improved register allocator in GCC 5+. From the - * release notes: - * Register allocation improvements: Reuse of the PIC hard register, - * instead of using a fixed register, was implemented on x86/x86-64 - * targets. This improves generated PIC code performance as more hard - * registers can be used. - */ -#if defined(__GNUC__) && __GNUC__ < 5 && defined(__PIC__) -#define MULADDC_CANNOT_USE_EBX -#endif - -/* - * Disable use of the i386 assembly code below if option -O0, to disable all - * compiler optimisations, is passed, detected with __OPTIMIZE__ - * This is done as the number of registers used in the assembly code doesn't - * work with the -O0 option. - */ -#if defined(__i386__) && defined(__OPTIMIZE__) && !defined(MULADDC_CANNOT_USE_EBX) - -#define MULADDC_X1_INIT \ - { mbedtls_mpi_uint t; \ - asm( \ - "movl %%ebx, %0 \n\t" \ - "movl %5, %%esi \n\t" \ - "movl %6, %%edi \n\t" \ - "movl %7, %%ecx \n\t" \ - "movl %8, %%ebx \n\t" - -#define MULADDC_X1_CORE \ - "lodsl \n\t" \ - "mull %%ebx \n\t" \ - "addl %%ecx, %%eax \n\t" \ - "adcl $0, %%edx \n\t" \ - "addl (%%edi), %%eax \n\t" \ - "adcl $0, %%edx \n\t" \ - "movl %%edx, %%ecx \n\t" \ - "stosl \n\t" - -#define MULADDC_X1_STOP \ - "movl %4, %%ebx \n\t" \ - "movl %%ecx, %1 \n\t" \ - "movl %%edi, %2 \n\t" \ - "movl %%esi, %3 \n\t" \ - : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ - : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ - : "eax", "ebx", "ecx", "edx", "esi", "edi" \ - ); } - -#if defined(MBEDTLS_HAVE_SSE2) - -#define MULADDC_X8_INIT MULADDC_X1_INIT - -#define MULADDC_X8_CORE \ - "movd %%ecx, %%mm1 \n\t" \ - "movd %%ebx, %%mm0 \n\t" \ - "movd (%%edi), %%mm3 \n\t" \ - "paddq %%mm3, %%mm1 \n\t" \ - "movd (%%esi), %%mm2 \n\t" \ - "pmuludq %%mm0, %%mm2 \n\t" \ - "movd 4(%%esi), %%mm4 \n\t" \ - "pmuludq %%mm0, %%mm4 \n\t" \ - "movd 8(%%esi), %%mm6 \n\t" \ - "pmuludq %%mm0, %%mm6 \n\t" \ - "movd 12(%%esi), %%mm7 \n\t" \ - "pmuludq %%mm0, %%mm7 \n\t" \ - "paddq %%mm2, %%mm1 \n\t" \ - "movd 4(%%edi), %%mm3 \n\t" \ - "paddq %%mm4, %%mm3 \n\t" \ - "movd 8(%%edi), %%mm5 \n\t" \ - "paddq %%mm6, %%mm5 \n\t" \ - "movd 12(%%edi), %%mm4 \n\t" \ - "paddq %%mm4, %%mm7 \n\t" \ - "movd %%mm1, (%%edi) \n\t" \ - "movd 16(%%esi), %%mm2 \n\t" \ - "pmuludq %%mm0, %%mm2 \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "movd 20(%%esi), %%mm4 \n\t" \ - "pmuludq %%mm0, %%mm4 \n\t" \ - "paddq %%mm3, %%mm1 \n\t" \ - "movd 24(%%esi), %%mm6 \n\t" \ - "pmuludq %%mm0, %%mm6 \n\t" \ - "movd %%mm1, 4(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "movd 28(%%esi), %%mm3 \n\t" \ - "pmuludq %%mm0, %%mm3 \n\t" \ - "paddq %%mm5, %%mm1 \n\t" \ - "movd 16(%%edi), %%mm5 \n\t" \ - "paddq %%mm5, %%mm2 \n\t" \ - "movd %%mm1, 8(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "paddq %%mm7, %%mm1 \n\t" \ - "movd 20(%%edi), %%mm5 \n\t" \ - "paddq %%mm5, %%mm4 \n\t" \ - "movd %%mm1, 12(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "paddq %%mm2, %%mm1 \n\t" \ - "movd 24(%%edi), %%mm5 \n\t" \ - "paddq %%mm5, %%mm6 \n\t" \ - "movd %%mm1, 16(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "paddq %%mm4, %%mm1 \n\t" \ - "movd 28(%%edi), %%mm5 \n\t" \ - "paddq %%mm5, %%mm3 \n\t" \ - "movd %%mm1, 20(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "paddq %%mm6, %%mm1 \n\t" \ - "movd %%mm1, 24(%%edi) \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "paddq %%mm3, %%mm1 \n\t" \ - "movd %%mm1, 28(%%edi) \n\t" \ - "addl $32, %%edi \n\t" \ - "addl $32, %%esi \n\t" \ - "psrlq $32, %%mm1 \n\t" \ - "movd %%mm1, %%ecx \n\t" - -#define MULADDC_X8_STOP \ - "emms \n\t" \ - "movl %4, %%ebx \n\t" \ - "movl %%ecx, %1 \n\t" \ - "movl %%edi, %2 \n\t" \ - "movl %%esi, %3 \n\t" \ - : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ - : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ - : "eax", "ebx", "ecx", "edx", "esi", "edi" \ - ); } \ - -#endif /* SSE2 */ - -#endif /* i386 */ - -#if defined(__amd64__) || defined (__x86_64__) - -#define MULADDC_X1_INIT \ - asm( \ - "xorq %%r8, %%r8\n" - -#define MULADDC_X1_CORE \ - "movq (%%rsi), %%rax\n" \ - "mulq %%rbx\n" \ - "addq $8, %%rsi\n" \ - "addq %%rcx, %%rax\n" \ - "movq %%r8, %%rcx\n" \ - "adcq $0, %%rdx\n" \ - "nop \n" \ - "addq %%rax, (%%rdi)\n" \ - "adcq %%rdx, %%rcx\n" \ - "addq $8, %%rdi\n" - -#define MULADDC_X1_STOP \ - : "+c" (c), "+D" (d), "+S" (s), "+m" (*(uint64_t (*)[16]) d) \ - : "b" (b), "m" (*(const uint64_t (*)[16]) s) \ - : "rax", "rdx", "r8" \ - ); - -#endif /* AMD64 */ - -// The following assembly code assumes that a pointer will fit in a 64-bit register -// (including ILP32 __aarch64__ ABIs such as on watchOS, hence the 2^32 - 1) -#if defined(__aarch64__) && (UINTPTR_MAX == 0xfffffffful || UINTPTR_MAX == 0xfffffffffffffffful) - -/* - * There are some issues around different compilers requiring different constraint - * syntax for updating pointers from assembly code (see notes for - * MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT in common.h), especially on aarch64_32 (aka ILP32). - * - * For this reason we cast the pointers to/from uintptr_t here. - */ -#define MULADDC_X1_INIT \ - do { uintptr_t muladdc_d = (uintptr_t) d, muladdc_s = (uintptr_t) s; asm( - -#define MULADDC_X1_CORE \ - "ldr x4, [%x2], #8 \n\t" \ - "ldr x5, [%x1] \n\t" \ - "mul x6, x4, %4 \n\t" \ - "umulh x7, x4, %4 \n\t" \ - "adds x5, x5, x6 \n\t" \ - "adc x7, x7, xzr \n\t" \ - "adds x5, x5, %0 \n\t" \ - "adc %0, x7, xzr \n\t" \ - "str x5, [%x1], #8 \n\t" - -#define MULADDC_X1_STOP \ - : "+r" (c), \ - "+r" (muladdc_d), \ - "+r" (muladdc_s), \ - "+m" (*(uint64_t (*)[16]) d) \ - : "r" (b), "m" (*(const uint64_t (*)[16]) s) \ - : "x4", "x5", "x6", "x7", "cc" \ - ); d = (mbedtls_mpi_uint *)muladdc_d; s = (mbedtls_mpi_uint *)muladdc_s; } while (0); - -#endif /* Aarch64 */ - -#if defined(__mc68020__) || defined(__mcpu32__) - -#define MULADDC_X1_INIT \ - asm( \ - "movl %3, %%a2 \n\t" \ - "movl %4, %%a3 \n\t" \ - "movl %5, %%d3 \n\t" \ - "movl %6, %%d2 \n\t" \ - "moveq #0, %%d0 \n\t" - -#define MULADDC_X1_CORE \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d4:%%d1 \n\t" \ - "addl %%d3, %%d1 \n\t" \ - "addxl %%d0, %%d4 \n\t" \ - "moveq #0, %%d3 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "addxl %%d4, %%d3 \n\t" - -#define MULADDC_X1_STOP \ - "movl %%d3, %0 \n\t" \ - "movl %%a3, %1 \n\t" \ - "movl %%a2, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "d0", "d1", "d2", "d3", "d4", "a2", "a3" \ - ); - -#define MULADDC_X8_INIT MULADDC_X1_INIT - -#define MULADDC_X8_CORE \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d4:%%d1 \n\t" \ - "addxl %%d3, %%d1 \n\t" \ - "addxl %%d0, %%d4 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d3:%%d1 \n\t" \ - "addxl %%d4, %%d1 \n\t" \ - "addxl %%d0, %%d3 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d4:%%d1 \n\t" \ - "addxl %%d3, %%d1 \n\t" \ - "addxl %%d0, %%d4 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d3:%%d1 \n\t" \ - "addxl %%d4, %%d1 \n\t" \ - "addxl %%d0, %%d3 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d4:%%d1 \n\t" \ - "addxl %%d3, %%d1 \n\t" \ - "addxl %%d0, %%d4 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d3:%%d1 \n\t" \ - "addxl %%d4, %%d1 \n\t" \ - "addxl %%d0, %%d3 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d4:%%d1 \n\t" \ - "addxl %%d3, %%d1 \n\t" \ - "addxl %%d0, %%d4 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "movel %%a2@+, %%d1 \n\t" \ - "mulul %%d2, %%d3:%%d1 \n\t" \ - "addxl %%d4, %%d1 \n\t" \ - "addxl %%d0, %%d3 \n\t" \ - "addl %%d1, %%a3@+ \n\t" \ - "addxl %%d0, %%d3 \n\t" - -#define MULADDC_X8_STOP MULADDC_X1_STOP - -#endif /* MC68000 */ - -#if defined(__powerpc64__) || defined(__ppc64__) - -#if defined(__MACH__) && defined(__APPLE__) - -#define MULADDC_X1_INIT \ - asm( \ - "ld r3, %3 \n\t" \ - "ld r4, %4 \n\t" \ - "ld r5, %5 \n\t" \ - "ld r6, %6 \n\t" \ - "addi r3, r3, -8 \n\t" \ - "addi r4, r4, -8 \n\t" \ - "addic r5, r5, 0 \n\t" - -#define MULADDC_X1_CORE \ - "ldu r7, 8(r3) \n\t" \ - "mulld r8, r7, r6 \n\t" \ - "mulhdu r9, r7, r6 \n\t" \ - "adde r8, r8, r5 \n\t" \ - "ld r7, 8(r4) \n\t" \ - "addze r5, r9 \n\t" \ - "addc r8, r8, r7 \n\t" \ - "stdu r8, 8(r4) \n\t" - -#define MULADDC_X1_STOP \ - "addze r5, r5 \n\t" \ - "addi r4, r4, 8 \n\t" \ - "addi r3, r3, 8 \n\t" \ - "std r5, %0 \n\t" \ - "std r4, %1 \n\t" \ - "std r3, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ - ); - - -#else /* __MACH__ && __APPLE__ */ - -#define MULADDC_X1_INIT \ - asm( \ - "ld %%r3, %3 \n\t" \ - "ld %%r4, %4 \n\t" \ - "ld %%r5, %5 \n\t" \ - "ld %%r6, %6 \n\t" \ - "addi %%r3, %%r3, -8 \n\t" \ - "addi %%r4, %%r4, -8 \n\t" \ - "addic %%r5, %%r5, 0 \n\t" - -#define MULADDC_X1_CORE \ - "ldu %%r7, 8(%%r3) \n\t" \ - "mulld %%r8, %%r7, %%r6 \n\t" \ - "mulhdu %%r9, %%r7, %%r6 \n\t" \ - "adde %%r8, %%r8, %%r5 \n\t" \ - "ld %%r7, 8(%%r4) \n\t" \ - "addze %%r5, %%r9 \n\t" \ - "addc %%r8, %%r8, %%r7 \n\t" \ - "stdu %%r8, 8(%%r4) \n\t" - -#define MULADDC_X1_STOP \ - "addze %%r5, %%r5 \n\t" \ - "addi %%r4, %%r4, 8 \n\t" \ - "addi %%r3, %%r3, 8 \n\t" \ - "std %%r5, %0 \n\t" \ - "std %%r4, %1 \n\t" \ - "std %%r3, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ - ); - -#endif /* __MACH__ && __APPLE__ */ - -#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32 */ - -#if defined(__MACH__) && defined(__APPLE__) - -#define MULADDC_X1_INIT \ - asm( \ - "lwz r3, %3 \n\t" \ - "lwz r4, %4 \n\t" \ - "lwz r5, %5 \n\t" \ - "lwz r6, %6 \n\t" \ - "addi r3, r3, -4 \n\t" \ - "addi r4, r4, -4 \n\t" \ - "addic r5, r5, 0 \n\t" - -#define MULADDC_X1_CORE \ - "lwzu r7, 4(r3) \n\t" \ - "mullw r8, r7, r6 \n\t" \ - "mulhwu r9, r7, r6 \n\t" \ - "adde r8, r8, r5 \n\t" \ - "lwz r7, 4(r4) \n\t" \ - "addze r5, r9 \n\t" \ - "addc r8, r8, r7 \n\t" \ - "stwu r8, 4(r4) \n\t" - -#define MULADDC_X1_STOP \ - "addze r5, r5 \n\t" \ - "addi r4, r4, 4 \n\t" \ - "addi r3, r3, 4 \n\t" \ - "stw r5, %0 \n\t" \ - "stw r4, %1 \n\t" \ - "stw r3, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ - ); - -#else /* __MACH__ && __APPLE__ */ - -#define MULADDC_X1_INIT \ - asm( \ - "lwz %%r3, %3 \n\t" \ - "lwz %%r4, %4 \n\t" \ - "lwz %%r5, %5 \n\t" \ - "lwz %%r6, %6 \n\t" \ - "addi %%r3, %%r3, -4 \n\t" \ - "addi %%r4, %%r4, -4 \n\t" \ - "addic %%r5, %%r5, 0 \n\t" - -#define MULADDC_X1_CORE \ - "lwzu %%r7, 4(%%r3) \n\t" \ - "mullw %%r8, %%r7, %%r6 \n\t" \ - "mulhwu %%r9, %%r7, %%r6 \n\t" \ - "adde %%r8, %%r8, %%r5 \n\t" \ - "lwz %%r7, 4(%%r4) \n\t" \ - "addze %%r5, %%r9 \n\t" \ - "addc %%r8, %%r8, %%r7 \n\t" \ - "stwu %%r8, 4(%%r4) \n\t" - -#define MULADDC_X1_STOP \ - "addze %%r5, %%r5 \n\t" \ - "addi %%r4, %%r4, 4 \n\t" \ - "addi %%r3, %%r3, 4 \n\t" \ - "stw %%r5, %0 \n\t" \ - "stw %%r4, %1 \n\t" \ - "stw %%r3, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ - ); - -#endif /* __MACH__ && __APPLE__ */ - -#endif /* PPC32 */ - -/* - * The Sparc(64) assembly is reported to be broken. - * Disable it for now, until we're able to fix it. - */ -#if 0 && defined(__sparc__) -#if defined(__sparc64__) - -#define MULADDC_X1_INIT \ - asm( \ - "ldx %3, %%o0 \n\t" \ - "ldx %4, %%o1 \n\t" \ - "ld %5, %%o2 \n\t" \ - "ld %6, %%o3 \n\t" - -#define MULADDC_X1_CORE \ - "ld [%%o0], %%o4 \n\t" \ - "inc 4, %%o0 \n\t" \ - "ld [%%o1], %%o5 \n\t" \ - "umul %%o3, %%o4, %%o4 \n\t" \ - "addcc %%o4, %%o2, %%o4 \n\t" \ - "rd %%y, %%g1 \n\t" \ - "addx %%g1, 0, %%g1 \n\t" \ - "addcc %%o4, %%o5, %%o4 \n\t" \ - "st %%o4, [%%o1] \n\t" \ - "addx %%g1, 0, %%o2 \n\t" \ - "inc 4, %%o1 \n\t" - -#define MULADDC_X1_STOP \ - "st %%o2, %0 \n\t" \ - "stx %%o1, %1 \n\t" \ - "stx %%o0, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "g1", "o0", "o1", "o2", "o3", "o4", \ - "o5" \ - ); - -#else /* __sparc64__ */ - -#define MULADDC_X1_INIT \ - asm( \ - "ld %3, %%o0 \n\t" \ - "ld %4, %%o1 \n\t" \ - "ld %5, %%o2 \n\t" \ - "ld %6, %%o3 \n\t" - -#define MULADDC_X1_CORE \ - "ld [%%o0], %%o4 \n\t" \ - "inc 4, %%o0 \n\t" \ - "ld [%%o1], %%o5 \n\t" \ - "umul %%o3, %%o4, %%o4 \n\t" \ - "addcc %%o4, %%o2, %%o4 \n\t" \ - "rd %%y, %%g1 \n\t" \ - "addx %%g1, 0, %%g1 \n\t" \ - "addcc %%o4, %%o5, %%o4 \n\t" \ - "st %%o4, [%%o1] \n\t" \ - "addx %%g1, 0, %%o2 \n\t" \ - "inc 4, %%o1 \n\t" - -#define MULADDC_X1_STOP \ - "st %%o2, %0 \n\t" \ - "st %%o1, %1 \n\t" \ - "st %%o0, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "g1", "o0", "o1", "o2", "o3", "o4", \ - "o5" \ - ); - -#endif /* __sparc64__ */ -#endif /* __sparc__ */ - -#if defined(__microblaze__) || defined(microblaze) - -#define MULADDC_X1_INIT \ - asm( \ - "lwi r3, %3 \n\t" \ - "lwi r4, %4 \n\t" \ - "lwi r5, %5 \n\t" \ - "lwi r6, %6 \n\t" \ - "andi r7, r6, 0xffff \n\t" \ - "bsrli r6, r6, 16 \n\t" - -#if(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) -#define MULADDC_LHUI \ - "lhui r9, r3, 0 \n\t" \ - "addi r3, r3, 2 \n\t" \ - "lhui r8, r3, 0 \n\t" -#else -#define MULADDC_LHUI \ - "lhui r8, r3, 0 \n\t" \ - "addi r3, r3, 2 \n\t" \ - "lhui r9, r3, 0 \n\t" -#endif - -#define MULADDC_X1_CORE \ - MULADDC_LHUI \ - "addi r3, r3, 2 \n\t" \ - "mul r10, r9, r6 \n\t" \ - "mul r11, r8, r7 \n\t" \ - "mul r12, r9, r7 \n\t" \ - "mul r13, r8, r6 \n\t" \ - "bsrli r8, r10, 16 \n\t" \ - "bsrli r9, r11, 16 \n\t" \ - "add r13, r13, r8 \n\t" \ - "add r13, r13, r9 \n\t" \ - "bslli r10, r10, 16 \n\t" \ - "bslli r11, r11, 16 \n\t" \ - "add r12, r12, r10 \n\t" \ - "addc r13, r13, r0 \n\t" \ - "add r12, r12, r11 \n\t" \ - "addc r13, r13, r0 \n\t" \ - "lwi r10, r4, 0 \n\t" \ - "add r12, r12, r10 \n\t" \ - "addc r13, r13, r0 \n\t" \ - "add r12, r12, r5 \n\t" \ - "addc r5, r13, r0 \n\t" \ - "swi r12, r4, 0 \n\t" \ - "addi r4, r4, 4 \n\t" - -#define MULADDC_X1_STOP \ - "swi r5, %0 \n\t" \ - "swi r4, %1 \n\t" \ - "swi r3, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r3", "r4", "r5", "r6", "r7", "r8", \ - "r9", "r10", "r11", "r12", "r13" \ - ); - -#endif /* MicroBlaze */ - -#if defined(__tricore__) - -#define MULADDC_X1_INIT \ - asm( \ - "ld.a %%a2, %3 \n\t" \ - "ld.a %%a3, %4 \n\t" \ - "ld.w %%d4, %5 \n\t" \ - "ld.w %%d1, %6 \n\t" \ - "xor %%d5, %%d5 \n\t" - -#define MULADDC_X1_CORE \ - "ld.w %%d0, [%%a2+] \n\t" \ - "madd.u %%e2, %%e4, %%d0, %%d1 \n\t" \ - "ld.w %%d0, [%%a3] \n\t" \ - "addx %%d2, %%d2, %%d0 \n\t" \ - "addc %%d3, %%d3, 0 \n\t" \ - "mov %%d4, %%d3 \n\t" \ - "st.w [%%a3+], %%d2 \n\t" - -#define MULADDC_X1_STOP \ - "st.w %0, %%d4 \n\t" \ - "st.a %1, %%a3 \n\t" \ - "st.a %2, %%a2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "d0", "d1", "e2", "d4", "a2", "a3" \ - ); - -#endif /* TriCore */ - -#if defined(__arm__) - -#if defined(__thumb__) && !defined(__thumb2__) -#if defined(MBEDTLS_COMPILER_IS_GCC) -/* - * Thumb 1 ISA. This code path has only been tested successfully on gcc; - * it does not compile on clang or armclang. - */ - -#if !defined(__OPTIMIZE__) && defined(__GNUC__) -/* - * Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about - * our use of r7 below, unless -fomit-frame-pointer is passed. - * - * On the other hand, -fomit-frame-pointer is implied by any -Ox options with - * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by - * clang and armcc5 under the same conditions). - * - * If gcc needs to use r7, we use r1 as a scratch register and have a few extra - * instructions to preserve/restore it; otherwise, we can use r7 and avoid - * the preserve/restore overhead. - */ -#define MULADDC_SCRATCH "RS .req r1 \n\t" -#define MULADDC_PRESERVE_SCRATCH "mov r10, r1 \n\t" -#define MULADDC_RESTORE_SCRATCH "mov r1, r10 \n\t" -#define MULADDC_SCRATCH_CLOBBER "r10" -#else /* !defined(__OPTIMIZE__) && defined(__GNUC__) */ -#define MULADDC_SCRATCH "RS .req r7 \n\t" -#define MULADDC_PRESERVE_SCRATCH "" -#define MULADDC_RESTORE_SCRATCH "" -#define MULADDC_SCRATCH_CLOBBER "r7" -#endif /* !defined(__OPTIMIZE__) && defined(__GNUC__) */ - -#define MULADDC_X1_INIT \ - asm( \ - MULADDC_SCRATCH \ - "ldr r0, %3 \n\t" \ - "ldr r1, %4 \n\t" \ - "ldr r2, %5 \n\t" \ - "ldr r3, %6 \n\t" \ - "lsr r4, r3, #16 \n\t" \ - "mov r9, r4 \n\t" \ - "lsl r4, r3, #16 \n\t" \ - "lsr r4, r4, #16 \n\t" \ - "mov r8, r4 \n\t" \ - - -#define MULADDC_X1_CORE \ - MULADDC_PRESERVE_SCRATCH \ - "ldmia r0!, {r6} \n\t" \ - "lsr RS, r6, #16 \n\t" \ - "lsl r6, r6, #16 \n\t" \ - "lsr r6, r6, #16 \n\t" \ - "mov r4, r8 \n\t" \ - "mul r4, r6 \n\t" \ - "mov r3, r9 \n\t" \ - "mul r6, r3 \n\t" \ - "mov r5, r9 \n\t" \ - "mul r5, RS \n\t" \ - "mov r3, r8 \n\t" \ - "mul RS, r3 \n\t" \ - "lsr r3, r6, #16 \n\t" \ - "add r5, r5, r3 \n\t" \ - "lsr r3, RS, #16 \n\t" \ - "add r5, r5, r3 \n\t" \ - "add r4, r4, r2 \n\t" \ - "mov r2, #0 \n\t" \ - "adc r5, r2 \n\t" \ - "lsl r3, r6, #16 \n\t" \ - "add r4, r4, r3 \n\t" \ - "adc r5, r2 \n\t" \ - "lsl r3, RS, #16 \n\t" \ - "add r4, r4, r3 \n\t" \ - "adc r5, r2 \n\t" \ - MULADDC_RESTORE_SCRATCH \ - "ldr r3, [r1] \n\t" \ - "add r4, r4, r3 \n\t" \ - "adc r2, r5 \n\t" \ - "stmia r1!, {r4} \n\t" - -#define MULADDC_X1_STOP \ - "str r2, %0 \n\t" \ - "str r1, %1 \n\t" \ - "str r0, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r0", "r1", "r2", "r3", "r4", "r5", \ - "r6", MULADDC_SCRATCH_CLOBBER, "r8", "r9", "cc" \ - ); -#endif /* !defined(__ARMCC_VERSION) && !defined(__clang__) */ - -#elif (__ARM_ARCH >= 6) && \ - defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1) -/* Armv6-M (or later) with DSP Instruction Set Extensions. - * Requires support for either Thumb 2 or Arm ISA. - */ - -#define MULADDC_X1_INIT \ - { \ - mbedtls_mpi_uint tmp_a, tmp_b; \ - asm volatile ( - -#define MULADDC_X1_CORE \ - ".p2align 2 \n\t" \ - "ldr %[a], [%[in]], #4 \n\t" \ - "ldr %[b], [%[acc]] \n\t" \ - "umaal %[b], %[carry], %[scalar], %[a] \n\t" \ - "str %[b], [%[acc]], #4 \n\t" - -#define MULADDC_X1_STOP \ - : [a] "=&r" (tmp_a), \ - [b] "=&r" (tmp_b), \ - [in] "+r" (s), \ - [acc] "+r" (d), \ - [carry] "+l" (c) \ - : [scalar] "r" (b) \ - : "memory" \ - ); \ - } - -#define MULADDC_X2_INIT \ - { \ - mbedtls_mpi_uint tmp_a0, tmp_b0; \ - mbedtls_mpi_uint tmp_a1, tmp_b1; \ - asm volatile ( - - /* - Make sure loop is 4-byte aligned to avoid stalls - * upon repeated non-word aligned instructions in - * some microarchitectures. - * - Don't use ldm with post-increment or back-to-back - * loads with post-increment and same address register - * to avoid stalls on some microarchitectures. - * - Bunch loads and stores to reduce latency on some - * microarchitectures. E.g., on Cortex-M4, the first - * in a series of load/store operations has latency - * 2 cycles, while subsequent loads/stores are single-cycle. */ -#define MULADDC_X2_CORE \ - ".p2align 2 \n\t" \ - "ldr %[a0], [%[in]], #+8 \n\t" \ - "ldr %[b0], [%[acc]], #+8 \n\t" \ - "ldr %[a1], [%[in], #-4] \n\t" \ - "ldr %[b1], [%[acc], #-4] \n\t" \ - "umaal %[b0], %[carry], %[scalar], %[a0] \n\t" \ - "umaal %[b1], %[carry], %[scalar], %[a1] \n\t" \ - "str %[b0], [%[acc], #-8] \n\t" \ - "str %[b1], [%[acc], #-4] \n\t" - -#define MULADDC_X2_STOP \ - : [a0] "=&r" (tmp_a0), \ - [b0] "=&r" (tmp_b0), \ - [a1] "=&r" (tmp_a1), \ - [b1] "=&r" (tmp_b1), \ - [in] "+r" (s), \ - [acc] "+r" (d), \ - [carry] "+l" (c) \ - : [scalar] "r" (b) \ - : "memory" \ - ); \ - } - -#else /* Thumb 2 or Arm ISA, without DSP extensions */ - -#define MULADDC_X1_INIT \ - asm( \ - "ldr r0, %3 \n\t" \ - "ldr r1, %4 \n\t" \ - "ldr r2, %5 \n\t" \ - "ldr r3, %6 \n\t" - -#define MULADDC_X1_CORE \ - "ldr r4, [r0], #4 \n\t" \ - "mov r5, #0 \n\t" \ - "ldr r6, [r1] \n\t" \ - "umlal r2, r5, r3, r4 \n\t" \ - "adds r4, r6, r2 \n\t" \ - "adc r2, r5, #0 \n\t" \ - "str r4, [r1], #4 \n\t" - -#define MULADDC_X1_STOP \ - "str r2, %0 \n\t" \ - "str r1, %1 \n\t" \ - "str r0, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "r0", "r1", "r2", "r3", "r4", "r5", \ - "r6", "cc" \ - ); - -#endif /* ISA codepath selection */ - -#endif /* defined(__arm__) */ - -#if defined(__alpha__) - -#define MULADDC_X1_INIT \ - asm( \ - "ldq $1, %3 \n\t" \ - "ldq $2, %4 \n\t" \ - "ldq $3, %5 \n\t" \ - "ldq $4, %6 \n\t" - -#define MULADDC_X1_CORE \ - "ldq $6, 0($1) \n\t" \ - "addq $1, 8, $1 \n\t" \ - "mulq $6, $4, $7 \n\t" \ - "umulh $6, $4, $6 \n\t" \ - "addq $7, $3, $7 \n\t" \ - "cmpult $7, $3, $3 \n\t" \ - "ldq $5, 0($2) \n\t" \ - "addq $7, $5, $7 \n\t" \ - "cmpult $7, $5, $5 \n\t" \ - "stq $7, 0($2) \n\t" \ - "addq $2, 8, $2 \n\t" \ - "addq $6, $3, $3 \n\t" \ - "addq $5, $3, $3 \n\t" - -#define MULADDC_X1_STOP \ - "stq $3, %0 \n\t" \ - "stq $2, %1 \n\t" \ - "stq $1, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "$1", "$2", "$3", "$4", "$5", "$6", "$7" \ - ); -#endif /* Alpha */ - -#if defined(__mips__) && !defined(__mips64) - -#define MULADDC_X1_INIT \ - asm( \ - "lw $10, %3 \n\t" \ - "lw $11, %4 \n\t" \ - "lw $12, %5 \n\t" \ - "lw $13, %6 \n\t" - -#define MULADDC_X1_CORE \ - "lw $14, 0($10) \n\t" \ - "multu $13, $14 \n\t" \ - "addi $10, $10, 4 \n\t" \ - "mflo $14 \n\t" \ - "mfhi $9 \n\t" \ - "addu $14, $12, $14 \n\t" \ - "lw $15, 0($11) \n\t" \ - "sltu $12, $14, $12 \n\t" \ - "addu $15, $14, $15 \n\t" \ - "sltu $14, $15, $14 \n\t" \ - "addu $12, $12, $9 \n\t" \ - "sw $15, 0($11) \n\t" \ - "addu $12, $12, $14 \n\t" \ - "addi $11, $11, 4 \n\t" - -#define MULADDC_X1_STOP \ - "sw $12, %0 \n\t" \ - "sw $11, %1 \n\t" \ - "sw $10, %2 \n\t" \ - : "=m" (c), "=m" (d), "=m" (s) \ - : "m" (s), "m" (d), "m" (c), "m" (b) \ - : "$9", "$10", "$11", "$12", "$13", "$14", "$15", "lo", "hi" \ - ); - -#endif /* MIPS */ -#endif /* GNUC */ - -#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) - -#define MULADDC_X1_INIT \ - __asm mov esi, s \ - __asm mov edi, d \ - __asm mov ecx, c \ - __asm mov ebx, b - -#define MULADDC_X1_CORE \ - __asm lodsd \ - __asm mul ebx \ - __asm add eax, ecx \ - __asm adc edx, 0 \ - __asm add eax, [edi] \ - __asm adc edx, 0 \ - __asm mov ecx, edx \ - __asm stosd - -#define MULADDC_X1_STOP \ - __asm mov c, ecx \ - __asm mov d, edi \ - __asm mov s, esi - -#if defined(MBEDTLS_HAVE_SSE2) - -#define EMIT __asm _emit - -#define MULADDC_X8_INIT MULADDC_X1_INIT - -#define MULADDC_X8_CORE \ - EMIT 0x0F EMIT 0x6E EMIT 0xC9 \ - EMIT 0x0F EMIT 0x6E EMIT 0xC3 \ - EMIT 0x0F EMIT 0x6E EMIT 0x1F \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ - EMIT 0x0F EMIT 0x6E EMIT 0x16 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ - EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x04 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ - EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x08 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ - EMIT 0x0F EMIT 0x6E EMIT 0x7E EMIT 0x0C \ - EMIT 0x0F EMIT 0xF4 EMIT 0xF8 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ - EMIT 0x0F EMIT 0x6E EMIT 0x5F EMIT 0x04 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xDC \ - EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x08 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xEE \ - EMIT 0x0F EMIT 0x6E EMIT 0x67 EMIT 0x0C \ - EMIT 0x0F EMIT 0xD4 EMIT 0xFC \ - EMIT 0x0F EMIT 0x7E EMIT 0x0F \ - EMIT 0x0F EMIT 0x6E EMIT 0x56 EMIT 0x10 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x14 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ - EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x18 \ - EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x04 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0x6E EMIT 0x5E EMIT 0x1C \ - EMIT 0x0F EMIT 0xF4 EMIT 0xD8 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCD \ - EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x10 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xD5 \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x08 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCF \ - EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x14 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xE5 \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x0C \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ - EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x18 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xF5 \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x10 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCC \ - EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x1C \ - EMIT 0x0F EMIT 0xD4 EMIT 0xDD \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x14 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCE \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x18 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ - EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x1C \ - EMIT 0x83 EMIT 0xC7 EMIT 0x20 \ - EMIT 0x83 EMIT 0xC6 EMIT 0x20 \ - EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ - EMIT 0x0F EMIT 0x7E EMIT 0xC9 - -#define MULADDC_X8_STOP \ - EMIT 0x0F EMIT 0x77 \ - __asm mov c, ecx \ - __asm mov d, edi \ - __asm mov s, esi - -#endif /* SSE2 */ -#endif /* MSVC */ - -#endif /* MBEDTLS_HAVE_ASM */ - -#if !defined(MULADDC_X1_CORE) -#if defined(MBEDTLS_HAVE_UDBL) - -#define MULADDC_X1_INIT \ -{ \ - mbedtls_t_udbl r; \ - mbedtls_mpi_uint r0, r1; - -#define MULADDC_X1_CORE \ - r = *(s++) * (mbedtls_t_udbl) b; \ - r0 = (mbedtls_mpi_uint) r; \ - r1 = (mbedtls_mpi_uint)( r >> biL ); \ - r0 += c; r1 += (r0 < c); \ - r0 += *d; r1 += (r0 < *d); \ - c = r1; *(d++) = r0; - -#define MULADDC_X1_STOP \ -} - -#else /* MBEDTLS_HAVE_UDBL */ - -#define MULADDC_X1_INIT \ -{ \ - mbedtls_mpi_uint s0, s1, b0, b1; \ - mbedtls_mpi_uint r0, r1, rx, ry; \ - b0 = ( b << biH ) >> biH; \ - b1 = ( b >> biH ); - -#define MULADDC_X1_CORE \ - s0 = ( *s << biH ) >> biH; \ - s1 = ( *s >> biH ); s++; \ - rx = s0 * b1; r0 = s0 * b0; \ - ry = s1 * b0; r1 = s1 * b1; \ - r1 += ( rx >> biH ); \ - r1 += ( ry >> biH ); \ - rx <<= biH; ry <<= biH; \ - r0 += rx; r1 += (r0 < rx); \ - r0 += ry; r1 += (r0 < ry); \ - r0 += c; r1 += (r0 < c); \ - r0 += *d; r1 += (r0 < *d); \ - c = r1; *(d++) = r0; - -#define MULADDC_X1_STOP \ -} - -#endif /* C (longlong) */ -#endif /* C (generic) */ - -#if !defined(MULADDC_X2_CORE) -#define MULADDC_X2_INIT MULADDC_X1_INIT -#define MULADDC_X2_STOP MULADDC_X1_STOP -#define MULADDC_X2_CORE MULADDC_X1_CORE MULADDC_X1_CORE -#endif /* MULADDC_X2_CORE */ - -#if !defined(MULADDC_X4_CORE) -#define MULADDC_X4_INIT MULADDC_X2_INIT -#define MULADDC_X4_STOP MULADDC_X2_STOP -#define MULADDC_X4_CORE MULADDC_X2_CORE MULADDC_X2_CORE -#endif /* MULADDC_X4_CORE */ - -#if !defined(MULADDC_X8_CORE) -#define MULADDC_X8_INIT MULADDC_X4_INIT -#define MULADDC_X8_STOP MULADDC_X4_STOP -#define MULADDC_X8_CORE MULADDC_X4_CORE MULADDC_X4_CORE -#endif /* MULADDC_X8_CORE */ - -/* *INDENT-ON* */ -#endif /* bn_mul.h */ +/** + * \file bn_mul.h + * + * \brief Multi-precision integer library + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * Multiply source vector [s] with b, add result + * to destination vector [d] and set carry c. + * + * Currently supports: + * + * . IA-32 (386+) . AMD64 / EM64T + * . IA-32 (SSE2) . Motorola 68000 + * . PowerPC, 32-bit . MicroBlaze + * . PowerPC, 64-bit . TriCore + * . SPARC v8 . ARM v3+ + * . Alpha . MIPS32 + * . C, longlong . C, generic + */ +#ifndef MBEDTLS_BN_MUL_H +#define MBEDTLS_BN_MUL_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/bignum.h" + + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \ + ((mbedtls_mpi_uint) (a) << 0) | \ + ((mbedtls_mpi_uint) (b) << 8) | \ + ((mbedtls_mpi_uint) (c) << 16) | \ + ((mbedtls_mpi_uint) (d) << 24) + +#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \ + MBEDTLS_BYTES_TO_T_UINT_4(a, b, 0, 0) + +#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \ + MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d), \ + MBEDTLS_BYTES_TO_T_UINT_4(e, f, g, h) + +#else /* 64-bits */ + +#define MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, e, f, g, h) \ + ((mbedtls_mpi_uint) (a) << 0) | \ + ((mbedtls_mpi_uint) (b) << 8) | \ + ((mbedtls_mpi_uint) (c) << 16) | \ + ((mbedtls_mpi_uint) (d) << 24) | \ + ((mbedtls_mpi_uint) (e) << 32) | \ + ((mbedtls_mpi_uint) (f) << 40) | \ + ((mbedtls_mpi_uint) (g) << 48) | \ + ((mbedtls_mpi_uint) (h) << 56) + +#define MBEDTLS_BYTES_TO_T_UINT_4(a, b, c, d) \ + MBEDTLS_BYTES_TO_T_UINT_8(a, b, c, d, 0, 0, 0, 0) + +#define MBEDTLS_BYTES_TO_T_UINT_2(a, b) \ + MBEDTLS_BYTES_TO_T_UINT_8(a, b, 0, 0, 0, 0, 0, 0) + +#endif /* bits in mbedtls_mpi_uint */ + +/* *INDENT-OFF* */ +#if defined(MBEDTLS_HAVE_ASM) + +/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */ +#if defined(__GNUC__) && \ + ( !defined(__ARMCC_VERSION) || __ARMCC_VERSION >= 6000000 ) + +/* + * GCC < 5.0 treated the x86 ebx (which is used for the GOT) as a + * fixed reserved register when building as PIC, leading to errors + * like: bn_mul.h:46:13: error: PIC register clobbered by 'ebx' in 'asm' + * + * This is fixed by an improved register allocator in GCC 5+. From the + * release notes: + * Register allocation improvements: Reuse of the PIC hard register, + * instead of using a fixed register, was implemented on x86/x86-64 + * targets. This improves generated PIC code performance as more hard + * registers can be used. + */ +#if defined(__GNUC__) && __GNUC__ < 5 && defined(__PIC__) +#define MULADDC_CANNOT_USE_EBX +#endif + +/* + * Disable use of the i386 assembly code below if option -O0, to disable all + * compiler optimisations, is passed, detected with __OPTIMIZE__ + * This is done as the number of registers used in the assembly code doesn't + * work with the -O0 option. + */ +#if defined(__i386__) && defined(__OPTIMIZE__) && !defined(MULADDC_CANNOT_USE_EBX) + +#define MULADDC_X1_INIT \ + { mbedtls_mpi_uint t; \ + asm( \ + "movl %%ebx, %0 \n\t" \ + "movl %5, %%esi \n\t" \ + "movl %6, %%edi \n\t" \ + "movl %7, %%ecx \n\t" \ + "movl %8, %%ebx \n\t" + +#define MULADDC_X1_CORE \ + "lodsl \n\t" \ + "mull %%ebx \n\t" \ + "addl %%ecx, %%eax \n\t" \ + "adcl $0, %%edx \n\t" \ + "addl (%%edi), %%eax \n\t" \ + "adcl $0, %%edx \n\t" \ + "movl %%edx, %%ecx \n\t" \ + "stosl \n\t" + +#define MULADDC_X1_STOP \ + "movl %4, %%ebx \n\t" \ + "movl %%ecx, %1 \n\t" \ + "movl %%edi, %2 \n\t" \ + "movl %%esi, %3 \n\t" \ + : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ + : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ + : "eax", "ebx", "ecx", "edx", "esi", "edi" \ + ); } + +#if defined(MBEDTLS_HAVE_SSE2) + +#define MULADDC_X8_INIT MULADDC_X1_INIT + +#define MULADDC_X8_CORE \ + "movd %%ecx, %%mm1 \n\t" \ + "movd %%ebx, %%mm0 \n\t" \ + "movd (%%edi), %%mm3 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd (%%esi), %%mm2 \n\t" \ + "pmuludq %%mm0, %%mm2 \n\t" \ + "movd 4(%%esi), %%mm4 \n\t" \ + "pmuludq %%mm0, %%mm4 \n\t" \ + "movd 8(%%esi), %%mm6 \n\t" \ + "pmuludq %%mm0, %%mm6 \n\t" \ + "movd 12(%%esi), %%mm7 \n\t" \ + "pmuludq %%mm0, %%mm7 \n\t" \ + "paddq %%mm2, %%mm1 \n\t" \ + "movd 4(%%edi), %%mm3 \n\t" \ + "paddq %%mm4, %%mm3 \n\t" \ + "movd 8(%%edi), %%mm5 \n\t" \ + "paddq %%mm6, %%mm5 \n\t" \ + "movd 12(%%edi), %%mm4 \n\t" \ + "paddq %%mm4, %%mm7 \n\t" \ + "movd %%mm1, (%%edi) \n\t" \ + "movd 16(%%esi), %%mm2 \n\t" \ + "pmuludq %%mm0, %%mm2 \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd 20(%%esi), %%mm4 \n\t" \ + "pmuludq %%mm0, %%mm4 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd 24(%%esi), %%mm6 \n\t" \ + "pmuludq %%mm0, %%mm6 \n\t" \ + "movd %%mm1, 4(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd 28(%%esi), %%mm3 \n\t" \ + "pmuludq %%mm0, %%mm3 \n\t" \ + "paddq %%mm5, %%mm1 \n\t" \ + "movd 16(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm2 \n\t" \ + "movd %%mm1, 8(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm7, %%mm1 \n\t" \ + "movd 20(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm4 \n\t" \ + "movd %%mm1, 12(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm2, %%mm1 \n\t" \ + "movd 24(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm6 \n\t" \ + "movd %%mm1, 16(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm4, %%mm1 \n\t" \ + "movd 28(%%edi), %%mm5 \n\t" \ + "paddq %%mm5, %%mm3 \n\t" \ + "movd %%mm1, 20(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm6, %%mm1 \n\t" \ + "movd %%mm1, 24(%%edi) \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "paddq %%mm3, %%mm1 \n\t" \ + "movd %%mm1, 28(%%edi) \n\t" \ + "addl $32, %%edi \n\t" \ + "addl $32, %%esi \n\t" \ + "psrlq $32, %%mm1 \n\t" \ + "movd %%mm1, %%ecx \n\t" + +#define MULADDC_X8_STOP \ + "emms \n\t" \ + "movl %4, %%ebx \n\t" \ + "movl %%ecx, %1 \n\t" \ + "movl %%edi, %2 \n\t" \ + "movl %%esi, %3 \n\t" \ + : "=m" (t), "=m" (c), "=m" (d), "=m" (s) \ + : "m" (t), "m" (s), "m" (d), "m" (c), "m" (b) \ + : "eax", "ebx", "ecx", "edx", "esi", "edi" \ + ); } \ + +#endif /* SSE2 */ + +#endif /* i386 */ + +#if defined(__amd64__) || defined (__x86_64__) + +#define MULADDC_X1_INIT \ + asm( \ + "xorq %%r8, %%r8\n" + +#define MULADDC_X1_CORE \ + "movq (%%rsi), %%rax\n" \ + "mulq %%rbx\n" \ + "addq $8, %%rsi\n" \ + "addq %%rcx, %%rax\n" \ + "movq %%r8, %%rcx\n" \ + "adcq $0, %%rdx\n" \ + "nop \n" \ + "addq %%rax, (%%rdi)\n" \ + "adcq %%rdx, %%rcx\n" \ + "addq $8, %%rdi\n" + +#define MULADDC_X1_STOP \ + : "+c" (c), "+D" (d), "+S" (s), "+m" (*(uint64_t (*)[16]) d) \ + : "b" (b), "m" (*(const uint64_t (*)[16]) s) \ + : "rax", "rdx", "r8" \ + ); + +#endif /* AMD64 */ + +// The following assembly code assumes that a pointer will fit in a 64-bit register +// (including ILP32 __aarch64__ ABIs such as on watchOS, hence the 2^32 - 1) +#if defined(__aarch64__) && (UINTPTR_MAX == 0xfffffffful || UINTPTR_MAX == 0xfffffffffffffffful) + +/* + * There are some issues around different compilers requiring different constraint + * syntax for updating pointers from assembly code (see notes for + * MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT in common.h), especially on aarch64_32 (aka ILP32). + * + * For this reason we cast the pointers to/from uintptr_t here. + */ +#define MULADDC_X1_INIT \ + do { uintptr_t muladdc_d = (uintptr_t) d, muladdc_s = (uintptr_t) s; asm( + +#define MULADDC_X1_CORE \ + "ldr x4, [%x2], #8 \n\t" \ + "ldr x5, [%x1] \n\t" \ + "mul x6, x4, %4 \n\t" \ + "umulh x7, x4, %4 \n\t" \ + "adds x5, x5, x6 \n\t" \ + "adc x7, x7, xzr \n\t" \ + "adds x5, x5, %0 \n\t" \ + "adc %0, x7, xzr \n\t" \ + "str x5, [%x1], #8 \n\t" + +#define MULADDC_X1_STOP \ + : "+r" (c), \ + "+r" (muladdc_d), \ + "+r" (muladdc_s), \ + "+m" (*(uint64_t (*)[16]) d) \ + : "r" (b), "m" (*(const uint64_t (*)[16]) s) \ + : "x4", "x5", "x6", "x7", "cc" \ + ); d = (mbedtls_mpi_uint *)muladdc_d; s = (mbedtls_mpi_uint *)muladdc_s; } while (0); + +#endif /* Aarch64 */ + +#if defined(__mc68020__) || defined(__mcpu32__) + +#define MULADDC_X1_INIT \ + asm( \ + "movl %3, %%a2 \n\t" \ + "movl %4, %%a3 \n\t" \ + "movl %5, %%d3 \n\t" \ + "movl %6, %%d2 \n\t" \ + "moveq #0, %%d0 \n\t" + +#define MULADDC_X1_CORE \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "moveq #0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "addxl %%d4, %%d3 \n\t" + +#define MULADDC_X1_STOP \ + "movl %%d3, %0 \n\t" \ + "movl %%a3, %1 \n\t" \ + "movl %%a2, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "d0", "d1", "d2", "d3", "d4", "a2", "a3" \ + ); + +#define MULADDC_X8_INIT MULADDC_X1_INIT + +#define MULADDC_X8_CORE \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d4:%%d1 \n\t" \ + "addxl %%d3, %%d1 \n\t" \ + "addxl %%d0, %%d4 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "movel %%a2@+, %%d1 \n\t" \ + "mulul %%d2, %%d3:%%d1 \n\t" \ + "addxl %%d4, %%d1 \n\t" \ + "addxl %%d0, %%d3 \n\t" \ + "addl %%d1, %%a3@+ \n\t" \ + "addxl %%d0, %%d3 \n\t" + +#define MULADDC_X8_STOP MULADDC_X1_STOP + +#endif /* MC68000 */ + +#if defined(__powerpc64__) || defined(__ppc64__) + +#if defined(__MACH__) && defined(__APPLE__) + +#define MULADDC_X1_INIT \ + asm( \ + "ld r3, %3 \n\t" \ + "ld r4, %4 \n\t" \ + "ld r5, %5 \n\t" \ + "ld r6, %6 \n\t" \ + "addi r3, r3, -8 \n\t" \ + "addi r4, r4, -8 \n\t" \ + "addic r5, r5, 0 \n\t" + +#define MULADDC_X1_CORE \ + "ldu r7, 8(r3) \n\t" \ + "mulld r8, r7, r6 \n\t" \ + "mulhdu r9, r7, r6 \n\t" \ + "adde r8, r8, r5 \n\t" \ + "ld r7, 8(r4) \n\t" \ + "addze r5, r9 \n\t" \ + "addc r8, r8, r7 \n\t" \ + "stdu r8, 8(r4) \n\t" + +#define MULADDC_X1_STOP \ + "addze r5, r5 \n\t" \ + "addi r4, r4, 8 \n\t" \ + "addi r3, r3, 8 \n\t" \ + "std r5, %0 \n\t" \ + "std r4, %1 \n\t" \ + "std r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + + +#else /* __MACH__ && __APPLE__ */ + +#define MULADDC_X1_INIT \ + asm( \ + "ld %%r3, %3 \n\t" \ + "ld %%r4, %4 \n\t" \ + "ld %%r5, %5 \n\t" \ + "ld %%r6, %6 \n\t" \ + "addi %%r3, %%r3, -8 \n\t" \ + "addi %%r4, %%r4, -8 \n\t" \ + "addic %%r5, %%r5, 0 \n\t" + +#define MULADDC_X1_CORE \ + "ldu %%r7, 8(%%r3) \n\t" \ + "mulld %%r8, %%r7, %%r6 \n\t" \ + "mulhdu %%r9, %%r7, %%r6 \n\t" \ + "adde %%r8, %%r8, %%r5 \n\t" \ + "ld %%r7, 8(%%r4) \n\t" \ + "addze %%r5, %%r9 \n\t" \ + "addc %%r8, %%r8, %%r7 \n\t" \ + "stdu %%r8, 8(%%r4) \n\t" + +#define MULADDC_X1_STOP \ + "addze %%r5, %%r5 \n\t" \ + "addi %%r4, %%r4, 8 \n\t" \ + "addi %%r3, %%r3, 8 \n\t" \ + "std %%r5, %0 \n\t" \ + "std %%r4, %1 \n\t" \ + "std %%r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#endif /* __MACH__ && __APPLE__ */ + +#elif defined(__powerpc__) || defined(__ppc__) /* end PPC64/begin PPC32 */ + +#if defined(__MACH__) && defined(__APPLE__) + +#define MULADDC_X1_INIT \ + asm( \ + "lwz r3, %3 \n\t" \ + "lwz r4, %4 \n\t" \ + "lwz r5, %5 \n\t" \ + "lwz r6, %6 \n\t" \ + "addi r3, r3, -4 \n\t" \ + "addi r4, r4, -4 \n\t" \ + "addic r5, r5, 0 \n\t" + +#define MULADDC_X1_CORE \ + "lwzu r7, 4(r3) \n\t" \ + "mullw r8, r7, r6 \n\t" \ + "mulhwu r9, r7, r6 \n\t" \ + "adde r8, r8, r5 \n\t" \ + "lwz r7, 4(r4) \n\t" \ + "addze r5, r9 \n\t" \ + "addc r8, r8, r7 \n\t" \ + "stwu r8, 4(r4) \n\t" + +#define MULADDC_X1_STOP \ + "addze r5, r5 \n\t" \ + "addi r4, r4, 4 \n\t" \ + "addi r3, r3, 4 \n\t" \ + "stw r5, %0 \n\t" \ + "stw r4, %1 \n\t" \ + "stw r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#else /* __MACH__ && __APPLE__ */ + +#define MULADDC_X1_INIT \ + asm( \ + "lwz %%r3, %3 \n\t" \ + "lwz %%r4, %4 \n\t" \ + "lwz %%r5, %5 \n\t" \ + "lwz %%r6, %6 \n\t" \ + "addi %%r3, %%r3, -4 \n\t" \ + "addi %%r4, %%r4, -4 \n\t" \ + "addic %%r5, %%r5, 0 \n\t" + +#define MULADDC_X1_CORE \ + "lwzu %%r7, 4(%%r3) \n\t" \ + "mullw %%r8, %%r7, %%r6 \n\t" \ + "mulhwu %%r9, %%r7, %%r6 \n\t" \ + "adde %%r8, %%r8, %%r5 \n\t" \ + "lwz %%r7, 4(%%r4) \n\t" \ + "addze %%r5, %%r9 \n\t" \ + "addc %%r8, %%r8, %%r7 \n\t" \ + "stwu %%r8, 4(%%r4) \n\t" + +#define MULADDC_X1_STOP \ + "addze %%r5, %%r5 \n\t" \ + "addi %%r4, %%r4, 4 \n\t" \ + "addi %%r3, %%r3, 4 \n\t" \ + "stw %%r5, %0 \n\t" \ + "stw %%r4, %1 \n\t" \ + "stw %%r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", "r9" \ + ); + +#endif /* __MACH__ && __APPLE__ */ + +#endif /* PPC32 */ + +/* + * The Sparc(64) assembly is reported to be broken. + * Disable it for now, until we're able to fix it. + */ +#if 0 && defined(__sparc__) +#if defined(__sparc64__) + +#define MULADDC_X1_INIT \ + asm( \ + "ldx %3, %%o0 \n\t" \ + "ldx %4, %%o1 \n\t" \ + "ld %5, %%o2 \n\t" \ + "ld %6, %%o3 \n\t" + +#define MULADDC_X1_CORE \ + "ld [%%o0], %%o4 \n\t" \ + "inc 4, %%o0 \n\t" \ + "ld [%%o1], %%o5 \n\t" \ + "umul %%o3, %%o4, %%o4 \n\t" \ + "addcc %%o4, %%o2, %%o4 \n\t" \ + "rd %%y, %%g1 \n\t" \ + "addx %%g1, 0, %%g1 \n\t" \ + "addcc %%o4, %%o5, %%o4 \n\t" \ + "st %%o4, [%%o1] \n\t" \ + "addx %%g1, 0, %%o2 \n\t" \ + "inc 4, %%o1 \n\t" + +#define MULADDC_X1_STOP \ + "st %%o2, %0 \n\t" \ + "stx %%o1, %1 \n\t" \ + "stx %%o0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "g1", "o0", "o1", "o2", "o3", "o4", \ + "o5" \ + ); + +#else /* __sparc64__ */ + +#define MULADDC_X1_INIT \ + asm( \ + "ld %3, %%o0 \n\t" \ + "ld %4, %%o1 \n\t" \ + "ld %5, %%o2 \n\t" \ + "ld %6, %%o3 \n\t" + +#define MULADDC_X1_CORE \ + "ld [%%o0], %%o4 \n\t" \ + "inc 4, %%o0 \n\t" \ + "ld [%%o1], %%o5 \n\t" \ + "umul %%o3, %%o4, %%o4 \n\t" \ + "addcc %%o4, %%o2, %%o4 \n\t" \ + "rd %%y, %%g1 \n\t" \ + "addx %%g1, 0, %%g1 \n\t" \ + "addcc %%o4, %%o5, %%o4 \n\t" \ + "st %%o4, [%%o1] \n\t" \ + "addx %%g1, 0, %%o2 \n\t" \ + "inc 4, %%o1 \n\t" + +#define MULADDC_X1_STOP \ + "st %%o2, %0 \n\t" \ + "st %%o1, %1 \n\t" \ + "st %%o0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "g1", "o0", "o1", "o2", "o3", "o4", \ + "o5" \ + ); + +#endif /* __sparc64__ */ +#endif /* __sparc__ */ + +#if defined(__microblaze__) || defined(microblaze) + +#define MULADDC_X1_INIT \ + asm( \ + "lwi r3, %3 \n\t" \ + "lwi r4, %4 \n\t" \ + "lwi r5, %5 \n\t" \ + "lwi r6, %6 \n\t" \ + "andi r7, r6, 0xffff \n\t" \ + "bsrli r6, r6, 16 \n\t" + +#if(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) +#define MULADDC_LHUI \ + "lhui r9, r3, 0 \n\t" \ + "addi r3, r3, 2 \n\t" \ + "lhui r8, r3, 0 \n\t" +#else +#define MULADDC_LHUI \ + "lhui r8, r3, 0 \n\t" \ + "addi r3, r3, 2 \n\t" \ + "lhui r9, r3, 0 \n\t" +#endif + +#define MULADDC_X1_CORE \ + MULADDC_LHUI \ + "addi r3, r3, 2 \n\t" \ + "mul r10, r9, r6 \n\t" \ + "mul r11, r8, r7 \n\t" \ + "mul r12, r9, r7 \n\t" \ + "mul r13, r8, r6 \n\t" \ + "bsrli r8, r10, 16 \n\t" \ + "bsrli r9, r11, 16 \n\t" \ + "add r13, r13, r8 \n\t" \ + "add r13, r13, r9 \n\t" \ + "bslli r10, r10, 16 \n\t" \ + "bslli r11, r11, 16 \n\t" \ + "add r12, r12, r10 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "add r12, r12, r11 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "lwi r10, r4, 0 \n\t" \ + "add r12, r12, r10 \n\t" \ + "addc r13, r13, r0 \n\t" \ + "add r12, r12, r5 \n\t" \ + "addc r5, r13, r0 \n\t" \ + "swi r12, r4, 0 \n\t" \ + "addi r4, r4, 4 \n\t" + +#define MULADDC_X1_STOP \ + "swi r5, %0 \n\t" \ + "swi r4, %1 \n\t" \ + "swi r3, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r3", "r4", "r5", "r6", "r7", "r8", \ + "r9", "r10", "r11", "r12", "r13" \ + ); + +#endif /* MicroBlaze */ + +#if defined(__tricore__) + +#define MULADDC_X1_INIT \ + asm( \ + "ld.a %%a2, %3 \n\t" \ + "ld.a %%a3, %4 \n\t" \ + "ld.w %%d4, %5 \n\t" \ + "ld.w %%d1, %6 \n\t" \ + "xor %%d5, %%d5 \n\t" + +#define MULADDC_X1_CORE \ + "ld.w %%d0, [%%a2+] \n\t" \ + "madd.u %%e2, %%e4, %%d0, %%d1 \n\t" \ + "ld.w %%d0, [%%a3] \n\t" \ + "addx %%d2, %%d2, %%d0 \n\t" \ + "addc %%d3, %%d3, 0 \n\t" \ + "mov %%d4, %%d3 \n\t" \ + "st.w [%%a3+], %%d2 \n\t" + +#define MULADDC_X1_STOP \ + "st.w %0, %%d4 \n\t" \ + "st.a %1, %%a3 \n\t" \ + "st.a %2, %%a2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "d0", "d1", "e2", "d4", "a2", "a3" \ + ); + +#endif /* TriCore */ + +#if defined(__arm__) + +#if defined(__thumb__) && !defined(__thumb2__) +#if defined(MBEDTLS_COMPILER_IS_GCC) +/* + * Thumb 1 ISA. This code path has only been tested successfully on gcc; + * it does not compile on clang or armclang. + */ + +#if !defined(__OPTIMIZE__) && defined(__GNUC__) +/* + * Note, gcc -O0 by default uses r7 for the frame pointer, so it complains about + * our use of r7 below, unless -fomit-frame-pointer is passed. + * + * On the other hand, -fomit-frame-pointer is implied by any -Ox options with + * x !=0, which we can detect using __OPTIMIZE__ (which is also defined by + * clang and armcc5 under the same conditions). + * + * If gcc needs to use r7, we use r1 as a scratch register and have a few extra + * instructions to preserve/restore it; otherwise, we can use r7 and avoid + * the preserve/restore overhead. + */ +#define MULADDC_SCRATCH "RS .req r1 \n\t" +#define MULADDC_PRESERVE_SCRATCH "mov r10, r1 \n\t" +#define MULADDC_RESTORE_SCRATCH "mov r1, r10 \n\t" +#define MULADDC_SCRATCH_CLOBBER "r10" +#else /* !defined(__OPTIMIZE__) && defined(__GNUC__) */ +#define MULADDC_SCRATCH "RS .req r7 \n\t" +#define MULADDC_PRESERVE_SCRATCH "" +#define MULADDC_RESTORE_SCRATCH "" +#define MULADDC_SCRATCH_CLOBBER "r7" +#endif /* !defined(__OPTIMIZE__) && defined(__GNUC__) */ + +#define MULADDC_X1_INIT \ + asm( \ + MULADDC_SCRATCH \ + "ldr r0, %3 \n\t" \ + "ldr r1, %4 \n\t" \ + "ldr r2, %5 \n\t" \ + "ldr r3, %6 \n\t" \ + "lsr r4, r3, #16 \n\t" \ + "mov r9, r4 \n\t" \ + "lsl r4, r3, #16 \n\t" \ + "lsr r4, r4, #16 \n\t" \ + "mov r8, r4 \n\t" \ + + +#define MULADDC_X1_CORE \ + MULADDC_PRESERVE_SCRATCH \ + "ldmia r0!, {r6} \n\t" \ + "lsr RS, r6, #16 \n\t" \ + "lsl r6, r6, #16 \n\t" \ + "lsr r6, r6, #16 \n\t" \ + "mov r4, r8 \n\t" \ + "mul r4, r6 \n\t" \ + "mov r3, r9 \n\t" \ + "mul r6, r3 \n\t" \ + "mov r5, r9 \n\t" \ + "mul r5, RS \n\t" \ + "mov r3, r8 \n\t" \ + "mul RS, r3 \n\t" \ + "lsr r3, r6, #16 \n\t" \ + "add r5, r5, r3 \n\t" \ + "lsr r3, RS, #16 \n\t" \ + "add r5, r5, r3 \n\t" \ + "add r4, r4, r2 \n\t" \ + "mov r2, #0 \n\t" \ + "adc r5, r2 \n\t" \ + "lsl r3, r6, #16 \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r5, r2 \n\t" \ + "lsl r3, RS, #16 \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r5, r2 \n\t" \ + MULADDC_RESTORE_SCRATCH \ + "ldr r3, [r1] \n\t" \ + "add r4, r4, r3 \n\t" \ + "adc r2, r5 \n\t" \ + "stmia r1!, {r4} \n\t" + +#define MULADDC_X1_STOP \ + "str r2, %0 \n\t" \ + "str r1, %1 \n\t" \ + "str r0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r0", "r1", "r2", "r3", "r4", "r5", \ + "r6", MULADDC_SCRATCH_CLOBBER, "r8", "r9", "cc" \ + ); +#endif /* !defined(__ARMCC_VERSION) && !defined(__clang__) */ + +#elif (__ARM_ARCH >= 6) && \ + defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1) +/* Armv6-M (or later) with DSP Instruction Set Extensions. + * Requires support for either Thumb 2 or Arm ISA. + */ + +#define MULADDC_X1_INIT \ + { \ + mbedtls_mpi_uint tmp_a, tmp_b; \ + asm volatile ( + +#define MULADDC_X1_CORE \ + ".p2align 2 \n\t" \ + "ldr %[a], [%[in]], #4 \n\t" \ + "ldr %[b], [%[acc]] \n\t" \ + "umaal %[b], %[carry], %[scalar], %[a] \n\t" \ + "str %[b], [%[acc]], #4 \n\t" + +#define MULADDC_X1_STOP \ + : [a] "=&r" (tmp_a), \ + [b] "=&r" (tmp_b), \ + [in] "+r" (s), \ + [acc] "+r" (d), \ + [carry] "+l" (c) \ + : [scalar] "r" (b) \ + : "memory" \ + ); \ + } + +#define MULADDC_X2_INIT \ + { \ + mbedtls_mpi_uint tmp_a0, tmp_b0; \ + mbedtls_mpi_uint tmp_a1, tmp_b1; \ + asm volatile ( + + /* - Make sure loop is 4-byte aligned to avoid stalls + * upon repeated non-word aligned instructions in + * some microarchitectures. + * - Don't use ldm with post-increment or back-to-back + * loads with post-increment and same address register + * to avoid stalls on some microarchitectures. + * - Bunch loads and stores to reduce latency on some + * microarchitectures. E.g., on Cortex-M4, the first + * in a series of load/store operations has latency + * 2 cycles, while subsequent loads/stores are single-cycle. */ +#define MULADDC_X2_CORE \ + ".p2align 2 \n\t" \ + "ldr %[a0], [%[in]], #+8 \n\t" \ + "ldr %[b0], [%[acc]], #+8 \n\t" \ + "ldr %[a1], [%[in], #-4] \n\t" \ + "ldr %[b1], [%[acc], #-4] \n\t" \ + "umaal %[b0], %[carry], %[scalar], %[a0] \n\t" \ + "umaal %[b1], %[carry], %[scalar], %[a1] \n\t" \ + "str %[b0], [%[acc], #-8] \n\t" \ + "str %[b1], [%[acc], #-4] \n\t" + +#define MULADDC_X2_STOP \ + : [a0] "=&r" (tmp_a0), \ + [b0] "=&r" (tmp_b0), \ + [a1] "=&r" (tmp_a1), \ + [b1] "=&r" (tmp_b1), \ + [in] "+r" (s), \ + [acc] "+r" (d), \ + [carry] "+l" (c) \ + : [scalar] "r" (b) \ + : "memory" \ + ); \ + } + +#else /* Thumb 2 or Arm ISA, without DSP extensions */ + +#define MULADDC_X1_INIT \ + asm( \ + "ldr r0, %3 \n\t" \ + "ldr r1, %4 \n\t" \ + "ldr r2, %5 \n\t" \ + "ldr r3, %6 \n\t" + +#define MULADDC_X1_CORE \ + "ldr r4, [r0], #4 \n\t" \ + "mov r5, #0 \n\t" \ + "ldr r6, [r1] \n\t" \ + "umlal r2, r5, r3, r4 \n\t" \ + "adds r4, r6, r2 \n\t" \ + "adc r2, r5, #0 \n\t" \ + "str r4, [r1], #4 \n\t" + +#define MULADDC_X1_STOP \ + "str r2, %0 \n\t" \ + "str r1, %1 \n\t" \ + "str r0, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "r0", "r1", "r2", "r3", "r4", "r5", \ + "r6", "cc" \ + ); + +#endif /* ISA codepath selection */ + +#endif /* defined(__arm__) */ + +#if defined(__alpha__) + +#define MULADDC_X1_INIT \ + asm( \ + "ldq $1, %3 \n\t" \ + "ldq $2, %4 \n\t" \ + "ldq $3, %5 \n\t" \ + "ldq $4, %6 \n\t" + +#define MULADDC_X1_CORE \ + "ldq $6, 0($1) \n\t" \ + "addq $1, 8, $1 \n\t" \ + "mulq $6, $4, $7 \n\t" \ + "umulh $6, $4, $6 \n\t" \ + "addq $7, $3, $7 \n\t" \ + "cmpult $7, $3, $3 \n\t" \ + "ldq $5, 0($2) \n\t" \ + "addq $7, $5, $7 \n\t" \ + "cmpult $7, $5, $5 \n\t" \ + "stq $7, 0($2) \n\t" \ + "addq $2, 8, $2 \n\t" \ + "addq $6, $3, $3 \n\t" \ + "addq $5, $3, $3 \n\t" + +#define MULADDC_X1_STOP \ + "stq $3, %0 \n\t" \ + "stq $2, %1 \n\t" \ + "stq $1, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "$1", "$2", "$3", "$4", "$5", "$6", "$7" \ + ); +#endif /* Alpha */ + +#if defined(__mips__) && !defined(__mips64) + +#define MULADDC_X1_INIT \ + asm( \ + "lw $10, %3 \n\t" \ + "lw $11, %4 \n\t" \ + "lw $12, %5 \n\t" \ + "lw $13, %6 \n\t" + +#define MULADDC_X1_CORE \ + "lw $14, 0($10) \n\t" \ + "multu $13, $14 \n\t" \ + "addi $10, $10, 4 \n\t" \ + "mflo $14 \n\t" \ + "mfhi $9 \n\t" \ + "addu $14, $12, $14 \n\t" \ + "lw $15, 0($11) \n\t" \ + "sltu $12, $14, $12 \n\t" \ + "addu $15, $14, $15 \n\t" \ + "sltu $14, $15, $14 \n\t" \ + "addu $12, $12, $9 \n\t" \ + "sw $15, 0($11) \n\t" \ + "addu $12, $12, $14 \n\t" \ + "addi $11, $11, 4 \n\t" + +#define MULADDC_X1_STOP \ + "sw $12, %0 \n\t" \ + "sw $11, %1 \n\t" \ + "sw $10, %2 \n\t" \ + : "=m" (c), "=m" (d), "=m" (s) \ + : "m" (s), "m" (d), "m" (c), "m" (b) \ + : "$9", "$10", "$11", "$12", "$13", "$14", "$15", "lo", "hi" \ + ); + +#endif /* MIPS */ +#endif /* GNUC */ + +#if (defined(_MSC_VER) && defined(_M_IX86)) || defined(__WATCOMC__) + +#define MULADDC_X1_INIT \ + __asm mov esi, s \ + __asm mov edi, d \ + __asm mov ecx, c \ + __asm mov ebx, b + +#define MULADDC_X1_CORE \ + __asm lodsd \ + __asm mul ebx \ + __asm add eax, ecx \ + __asm adc edx, 0 \ + __asm add eax, [edi] \ + __asm adc edx, 0 \ + __asm mov ecx, edx \ + __asm stosd + +#define MULADDC_X1_STOP \ + __asm mov c, ecx \ + __asm mov d, edi \ + __asm mov s, esi + +#if defined(MBEDTLS_HAVE_SSE2) + +#define EMIT __asm _emit + +#define MULADDC_X8_INIT MULADDC_X1_INIT + +#define MULADDC_X8_CORE \ + EMIT 0x0F EMIT 0x6E EMIT 0xC9 \ + EMIT 0x0F EMIT 0x6E EMIT 0xC3 \ + EMIT 0x0F EMIT 0x6E EMIT 0x1F \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x6E EMIT 0x16 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x04 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x08 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ + EMIT 0x0F EMIT 0x6E EMIT 0x7E EMIT 0x0C \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF8 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ + EMIT 0x0F EMIT 0x6E EMIT 0x5F EMIT 0x04 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xDC \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x08 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xEE \ + EMIT 0x0F EMIT 0x6E EMIT 0x67 EMIT 0x0C \ + EMIT 0x0F EMIT 0xD4 EMIT 0xFC \ + EMIT 0x0F EMIT 0x7E EMIT 0x0F \ + EMIT 0x0F EMIT 0x6E EMIT 0x56 EMIT 0x10 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD0 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x6E EMIT 0x66 EMIT 0x14 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xE0 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x6E EMIT 0x76 EMIT 0x18 \ + EMIT 0x0F EMIT 0xF4 EMIT 0xF0 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x04 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x6E EMIT 0x5E EMIT 0x1C \ + EMIT 0x0F EMIT 0xF4 EMIT 0xD8 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCD \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x10 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xD5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x08 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCF \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x14 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xE5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x0C \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCA \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x18 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xF5 \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x10 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCC \ + EMIT 0x0F EMIT 0x6E EMIT 0x6F EMIT 0x1C \ + EMIT 0x0F EMIT 0xD4 EMIT 0xDD \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x14 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCE \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x18 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0xD4 EMIT 0xCB \ + EMIT 0x0F EMIT 0x7E EMIT 0x4F EMIT 0x1C \ + EMIT 0x83 EMIT 0xC7 EMIT 0x20 \ + EMIT 0x83 EMIT 0xC6 EMIT 0x20 \ + EMIT 0x0F EMIT 0x73 EMIT 0xD1 EMIT 0x20 \ + EMIT 0x0F EMIT 0x7E EMIT 0xC9 + +#define MULADDC_X8_STOP \ + EMIT 0x0F EMIT 0x77 \ + __asm mov c, ecx \ + __asm mov d, edi \ + __asm mov s, esi + +#endif /* SSE2 */ +#endif /* MSVC */ + +#endif /* MBEDTLS_HAVE_ASM */ + +#if !defined(MULADDC_X1_CORE) +#if defined(MBEDTLS_HAVE_UDBL) + +#define MULADDC_X1_INIT \ +{ \ + mbedtls_t_udbl r; \ + mbedtls_mpi_uint r0, r1; + +#define MULADDC_X1_CORE \ + r = *(s++) * (mbedtls_t_udbl) b; \ + r0 = (mbedtls_mpi_uint) r; \ + r1 = (mbedtls_mpi_uint)( r >> biL ); \ + r0 += c; r1 += (r0 < c); \ + r0 += *d; r1 += (r0 < *d); \ + c = r1; *(d++) = r0; + +#define MULADDC_X1_STOP \ +} + +#else /* MBEDTLS_HAVE_UDBL */ + +#define MULADDC_X1_INIT \ +{ \ + mbedtls_mpi_uint s0, s1, b0, b1; \ + mbedtls_mpi_uint r0, r1, rx, ry; \ + b0 = ( b << biH ) >> biH; \ + b1 = ( b >> biH ); + +#define MULADDC_X1_CORE \ + s0 = ( *s << biH ) >> biH; \ + s1 = ( *s >> biH ); s++; \ + rx = s0 * b1; r0 = s0 * b0; \ + ry = s1 * b0; r1 = s1 * b1; \ + r1 += ( rx >> biH ); \ + r1 += ( ry >> biH ); \ + rx <<= biH; ry <<= biH; \ + r0 += rx; r1 += (r0 < rx); \ + r0 += ry; r1 += (r0 < ry); \ + r0 += c; r1 += (r0 < c); \ + r0 += *d; r1 += (r0 < *d); \ + c = r1; *(d++) = r0; + +#define MULADDC_X1_STOP \ +} + +#endif /* C (longlong) */ +#endif /* C (generic) */ + +#if !defined(MULADDC_X2_CORE) +#define MULADDC_X2_INIT MULADDC_X1_INIT +#define MULADDC_X2_STOP MULADDC_X1_STOP +#define MULADDC_X2_CORE MULADDC_X1_CORE MULADDC_X1_CORE +#endif /* MULADDC_X2_CORE */ + +#if !defined(MULADDC_X4_CORE) +#define MULADDC_X4_INIT MULADDC_X2_INIT +#define MULADDC_X4_STOP MULADDC_X2_STOP +#define MULADDC_X4_CORE MULADDC_X2_CORE MULADDC_X2_CORE +#endif /* MULADDC_X4_CORE */ + +#if !defined(MULADDC_X8_CORE) +#define MULADDC_X8_INIT MULADDC_X4_INIT +#define MULADDC_X8_STOP MULADDC_X4_STOP +#define MULADDC_X8_CORE MULADDC_X4_CORE MULADDC_X4_CORE +#endif /* MULADDC_X8_CORE */ + +/* *INDENT-ON* */ +#endif /* bn_mul.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/check_crypto_config.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/check_crypto_config.h index b7d87fe..1f545b1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/check_crypto_config.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/check_crypto_config.h @@ -1,153 +1,153 @@ -/** - * \file check_crypto_config.h - * - * \brief Consistency checks for PSA configuration options - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * It is recommended to include this file from your crypto_config.h - * in order to catch dependency issues early. - */ - -#ifndef MBEDTLS_CHECK_CRYPTO_CONFIG_H -#define MBEDTLS_CHECK_CRYPTO_CONFIG_H - -#if defined(PSA_WANT_ALG_CCM) && \ - !(defined(PSA_WANT_KEY_TYPE_AES) || \ - defined(PSA_WANT_KEY_TYPE_CAMELLIA)) -#error "PSA_WANT_ALG_CCM defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_CMAC) && \ - !(defined(PSA_WANT_KEY_TYPE_AES) || \ - defined(PSA_WANT_KEY_TYPE_CAMELLIA) || \ - defined(PSA_WANT_KEY_TYPE_DES)) -#error "PSA_WANT_ALG_CMAC defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) && \ - !(defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) -#error "PSA_WANT_ALG_DETERMINISTIC_ECDSA defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_ECDSA) && \ - !(defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) -#error "PSA_WANT_ALG_ECDSA defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_GCM) && \ - !(defined(PSA_WANT_KEY_TYPE_AES) || \ - defined(PSA_WANT_KEY_TYPE_CAMELLIA)) -#error "PSA_WANT_ALG_GCM defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) && \ - !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) -#error "PSA_WANT_ALG_RSA_PKCS1V15_CRYPT defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) && \ - !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) -#error "PSA_WANT_ALG_RSA_PKCS1V15_SIGN defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_RSA_OAEP) && \ - !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) -#error "PSA_WANT_ALG_RSA_OAEP defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_RSA_PSS) && \ - !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) -#error "PSA_WANT_ALG_RSA_PSS defined, but not all prerequisites" -#endif - -#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ - defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE)) && \ - !defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -#error "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx defined, but not all prerequisites" -#endif - -#if (defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE)) && \ - !defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) -#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx defined, but not all prerequisites" -#endif - -#if (defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE)) && \ - !defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) -#error "PSA_WANT_KEY_TYPE_DH_KEY_PAIR_xxx defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) -#if defined(MBEDTLS_DEPRECATED_REMOVED) -#error "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR is deprecated and will be removed in a \ - future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx \ - symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" -#elif defined(MBEDTLS_DEPRECATED_WARNING) -#warning "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR is deprecated and will be removed in a \ - future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx \ - symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" -#endif /* MBEDTLS_DEPRECATED_WARNING */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) -#if defined(MBEDTLS_DEPRECATED_REMOVED) -#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR is deprecated and will be removed in a \ - future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx \ - symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" -#elif defined(MBEDTLS_DEPRECATED_WARNING) -#warning "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR is deprecated and will be removed in a \ - future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx \ - symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" -#endif /* MBEDTLS_DEPRECATED_WARNING */ -#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR */ - -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE) -#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE defined, but feature is not supported" -#endif - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE) -#error "PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE defined, but feature is not supported" -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && defined(MBEDTLS_USE_PSA_CRYPTO) && \ - !(defined(PSA_WANT_ALG_SHA_1) || defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_512)) -#error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites" -#endif - -#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) && \ - !defined(PSA_WANT_ALG_SHA_256) -#error "PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS defined, but not all prerequisites" -#endif - -#endif /* MBEDTLS_CHECK_CRYPTO_CONFIG_H */ +/** + * \file check_crypto_config.h + * + * \brief Consistency checks for PSA configuration options + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * It is recommended to include this file from your crypto_config.h + * in order to catch dependency issues early. + */ + +#ifndef MBEDTLS_CHECK_CRYPTO_CONFIG_H +#define MBEDTLS_CHECK_CRYPTO_CONFIG_H + +#if defined(PSA_WANT_ALG_CCM) && \ + !(defined(PSA_WANT_KEY_TYPE_AES) || \ + defined(PSA_WANT_KEY_TYPE_CAMELLIA)) +#error "PSA_WANT_ALG_CCM defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_CMAC) && \ + !(defined(PSA_WANT_KEY_TYPE_AES) || \ + defined(PSA_WANT_KEY_TYPE_CAMELLIA) || \ + defined(PSA_WANT_KEY_TYPE_DES)) +#error "PSA_WANT_ALG_CMAC defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) && \ + !(defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) +#error "PSA_WANT_ALG_DETERMINISTIC_ECDSA defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_ECDSA) && \ + !(defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY)) +#error "PSA_WANT_ALG_ECDSA defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_GCM) && \ + !(defined(PSA_WANT_KEY_TYPE_AES) || \ + defined(PSA_WANT_KEY_TYPE_CAMELLIA)) +#error "PSA_WANT_ALG_GCM defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) && \ + !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) +#error "PSA_WANT_ALG_RSA_PKCS1V15_CRYPT defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) && \ + !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) +#error "PSA_WANT_ALG_RSA_PKCS1V15_SIGN defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_OAEP) && \ + !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) +#error "PSA_WANT_ALG_RSA_OAEP defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PSS) && \ + !(defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY)) +#error "PSA_WANT_ALG_RSA_PSS defined, but not all prerequisites" +#endif + +#if (defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) || \ + defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE)) && \ + !defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#error "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx defined, but not all prerequisites" +#endif + +#if (defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE)) && \ + !defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) +#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx defined, but not all prerequisites" +#endif + +#if (defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_BASIC) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE)) && \ + !defined(PSA_WANT_KEY_TYPE_DH_PUBLIC_KEY) +#error "PSA_WANT_KEY_TYPE_DH_KEY_PAIR_xxx defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR is deprecated and will be removed in a \ + future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx \ + symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR is deprecated and will be removed in a \ + future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_xxx \ + symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" +#endif /* MBEDTLS_DEPRECATED_WARNING */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR is deprecated and will be removed in a \ + future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx \ + symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR is deprecated and will be removed in a \ + future version of Mbed TLS. Please switch to new PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_xxx \ + symbols, where xxx can be: USE, IMPORT, EXPORT, GENERATE, DERIVE" +#endif /* MBEDTLS_DEPRECATED_WARNING */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE) +#error "PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE defined, but feature is not supported" +#endif + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE) +#error "PSA_WANT_KEY_TYPE_DH_KEY_PAIR_DERIVE defined, but feature is not supported" +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && defined(MBEDTLS_USE_PSA_CRYPTO) && \ + !(defined(PSA_WANT_ALG_SHA_1) || defined(PSA_WANT_ALG_SHA_256) || defined(PSA_WANT_ALG_SHA_512)) +#error "MBEDTLS_SSL_PROTO_TLS1_2 defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) && \ + !defined(PSA_WANT_ALG_SHA_256) +#error "PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS defined, but not all prerequisites" +#endif + +#endif /* MBEDTLS_CHECK_CRYPTO_CONFIG_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher.c index b5bff2a..a140423 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher.c @@ -1,1682 +1,1682 @@ -/** - * \file cipher.c - * - * \brief Generic cipher wrapper for Mbed TLS - * - * \author Adriaan de Jong - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_CIPHER_C) - -#include "mbedtls/cipher.h" -#include "cipher_wrap.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/error.h" -#include "mbedtls/constant_time.h" -#include "constant_time_internal.h" - -#include -#include - -#if defined(MBEDTLS_CHACHAPOLY_C) -#include "mbedtls/chachapoly.h" -#endif - -#if defined(MBEDTLS_GCM_C) -#include "mbedtls/gcm.h" -#endif - -#if defined(MBEDTLS_CCM_C) -#include "mbedtls/ccm.h" -#endif - -#if defined(MBEDTLS_CHACHA20_C) -#include "mbedtls/chacha20.h" -#endif - -#if defined(MBEDTLS_CMAC_C) -#include "mbedtls/cmac.h" -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) -#include "psa/crypto.h" -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_NIST_KW_C) -#include "mbedtls/nist_kw.h" -#endif - -#include "mbedtls/platform.h" - -static int supported_init = 0; - -static inline const mbedtls_cipher_base_t *mbedtls_cipher_get_base( - const mbedtls_cipher_info_t *info) -{ - return mbedtls_cipher_base_lookup_table[info->base_idx]; -} - -const int *mbedtls_cipher_list(void) -{ - const mbedtls_cipher_definition_t *def; - int *type; - - if (!supported_init) { - def = mbedtls_cipher_definitions; - type = mbedtls_cipher_supported; - - while (def->type != 0) { - *type++ = (*def++).type; - } - - *type = 0; - - supported_init = 1; - } - - return mbedtls_cipher_supported; -} - -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( - const mbedtls_cipher_type_t cipher_type) -{ - const mbedtls_cipher_definition_t *def; - - for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { - if (def->type == cipher_type) { - return def->info; - } - } - - return NULL; -} - -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( - const char *cipher_name) -{ - const mbedtls_cipher_definition_t *def; - - if (NULL == cipher_name) { - return NULL; - } - - for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { - if (!strcmp(def->info->name, cipher_name)) { - return def->info; - } - } - - return NULL; -} - -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( - const mbedtls_cipher_id_t cipher_id, - int key_bitlen, - const mbedtls_cipher_mode_t mode) -{ - const mbedtls_cipher_definition_t *def; - - for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { - if (mbedtls_cipher_get_base(def->info)->cipher == cipher_id && - mbedtls_cipher_info_get_key_bitlen(def->info) == (unsigned) key_bitlen && - def->info->mode == mode) { - return def->info; - } - } - - return NULL; -} - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) -static inline psa_key_type_t mbedtls_psa_translate_cipher_type( - mbedtls_cipher_type_t cipher) -{ - switch (cipher) { - case MBEDTLS_CIPHER_AES_128_CCM: - case MBEDTLS_CIPHER_AES_192_CCM: - case MBEDTLS_CIPHER_AES_256_CCM: - case MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_AES_128_GCM: - case MBEDTLS_CIPHER_AES_192_GCM: - case MBEDTLS_CIPHER_AES_256_GCM: - case MBEDTLS_CIPHER_AES_128_CBC: - case MBEDTLS_CIPHER_AES_192_CBC: - case MBEDTLS_CIPHER_AES_256_CBC: - case MBEDTLS_CIPHER_AES_128_ECB: - case MBEDTLS_CIPHER_AES_192_ECB: - case MBEDTLS_CIPHER_AES_256_ECB: - return PSA_KEY_TYPE_AES; - - /* ARIA not yet supported in PSA. */ - /* case MBEDTLS_CIPHER_ARIA_128_CCM: - case MBEDTLS_CIPHER_ARIA_192_CCM: - case MBEDTLS_CIPHER_ARIA_256_CCM: - case MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG: - case MBEDTLS_CIPHER_ARIA_128_GCM: - case MBEDTLS_CIPHER_ARIA_192_GCM: - case MBEDTLS_CIPHER_ARIA_256_GCM: - case MBEDTLS_CIPHER_ARIA_128_CBC: - case MBEDTLS_CIPHER_ARIA_192_CBC: - case MBEDTLS_CIPHER_ARIA_256_CBC: - return( PSA_KEY_TYPE_ARIA ); */ - - default: - return 0; - } -} - -static inline psa_algorithm_t mbedtls_psa_translate_cipher_mode( - mbedtls_cipher_mode_t mode, size_t taglen) -{ - switch (mode) { - case MBEDTLS_MODE_ECB: - return PSA_ALG_ECB_NO_PADDING; - case MBEDTLS_MODE_GCM: - return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, taglen); - case MBEDTLS_MODE_CCM: - return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, taglen); - case MBEDTLS_MODE_CCM_STAR_NO_TAG: - return PSA_ALG_CCM_STAR_NO_TAG; - case MBEDTLS_MODE_CBC: - if (taglen == 0) { - return PSA_ALG_CBC_NO_PADDING; - } else { - return 0; - } - default: - return 0; - } -} -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -void mbedtls_cipher_init(mbedtls_cipher_context_t *ctx) -{ - memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); -} - -void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx) -{ - if (ctx == NULL) { - return; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - if (ctx->cipher_ctx != NULL) { - mbedtls_cipher_context_psa * const cipher_psa = - (mbedtls_cipher_context_psa *) ctx->cipher_ctx; - - if (cipher_psa->slot_state == MBEDTLS_CIPHER_PSA_KEY_OWNED) { - /* xxx_free() doesn't allow to return failures. */ - (void) psa_destroy_key(cipher_psa->slot); - } - - mbedtls_zeroize_and_free(cipher_psa, sizeof(*cipher_psa)); - } - - mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); - return; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_CMAC_C) - if (ctx->cmac_ctx) { - mbedtls_zeroize_and_free(ctx->cmac_ctx, - sizeof(mbedtls_cmac_context_t)); - } -#endif - - if (ctx->cipher_ctx) { - mbedtls_cipher_get_base(ctx->cipher_info)->ctx_free_func(ctx->cipher_ctx); - } - - mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); -} - -int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, - const mbedtls_cipher_info_t *cipher_info) -{ - if (cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); - - if (NULL == (ctx->cipher_ctx = mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func())) { - return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; - } - - ctx->cipher_info = cipher_info; - - return 0; -} - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) -int mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, - const mbedtls_cipher_info_t *cipher_info, - size_t taglen) -{ - psa_algorithm_t alg; - mbedtls_cipher_context_psa *cipher_psa; - - if (NULL == cipher_info || NULL == ctx) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - /* Check that the underlying cipher mode and cipher type are - * supported by the underlying PSA Crypto implementation. */ - alg = mbedtls_psa_translate_cipher_mode(((mbedtls_cipher_mode_t) cipher_info->mode), taglen); - if (alg == 0) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - if (mbedtls_psa_translate_cipher_type(((mbedtls_cipher_type_t) cipher_info->type)) == 0) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); - - cipher_psa = mbedtls_calloc(1, sizeof(mbedtls_cipher_context_psa)); - if (cipher_psa == NULL) { - return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; - } - cipher_psa->alg = alg; - ctx->cipher_ctx = cipher_psa; - ctx->cipher_info = cipher_info; - ctx->psa_enabled = 1; - return 0; -} -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, - const unsigned char *key, - int key_bitlen, - const mbedtls_operation_t operation) -{ - if (operation != MBEDTLS_ENCRYPT && operation != MBEDTLS_DECRYPT) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - mbedtls_cipher_context_psa * const cipher_psa = - (mbedtls_cipher_context_psa *) ctx->cipher_ctx; - - size_t const key_bytelen = ((size_t) key_bitlen + 7) / 8; - - psa_status_t status; - psa_key_type_t key_type; - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - - /* PSA Crypto API only accepts byte-aligned keys. */ - if (key_bitlen % 8 != 0) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - /* Don't allow keys to be set multiple times. */ - if (cipher_psa->slot_state != MBEDTLS_CIPHER_PSA_KEY_UNSET) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - key_type = mbedtls_psa_translate_cipher_type( - ((mbedtls_cipher_type_t) ctx->cipher_info->type)); - if (key_type == 0) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - psa_set_key_type(&attributes, key_type); - - /* Mbed TLS' cipher layer doesn't enforce the mode of operation - * (encrypt vs. decrypt): it is possible to setup a key for encryption - * and use it for AEAD decryption. Until tests relying on this - * are changed, allow any usage in PSA. */ - psa_set_key_usage_flags(&attributes, - PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT); - psa_set_key_algorithm(&attributes, cipher_psa->alg); - - status = psa_import_key(&attributes, key, key_bytelen, - &cipher_psa->slot); - switch (status) { - case PSA_SUCCESS: - break; - case PSA_ERROR_INSUFFICIENT_MEMORY: - return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - default: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - /* Indicate that we own the key slot and need to - * destroy it in mbedtls_cipher_free(). */ - cipher_psa->slot_state = MBEDTLS_CIPHER_PSA_KEY_OWNED; - - ctx->key_bitlen = key_bitlen; - ctx->operation = operation; - return 0; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_KEY_LEN) == 0 && - (int) mbedtls_cipher_info_get_key_bitlen(ctx->cipher_info) != key_bitlen) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - ctx->key_bitlen = key_bitlen; - ctx->operation = operation; - - /* - * For OFB, CFB and CTR mode always use the encryption key schedule - */ - if (MBEDTLS_ENCRYPT == operation || - MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_CTR == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_enc_func(ctx->cipher_ctx, key, - ctx->key_bitlen); - } - - if (MBEDTLS_DECRYPT == operation) { - return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_dec_func(ctx->cipher_ctx, key, - ctx->key_bitlen); - } - - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; -} - -int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, - size_t iv_len) -{ - size_t actual_iv_size; - - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - /* avoid buffer overflow in ctx->iv */ - if (iv_len > MBEDTLS_MAX_IV_LENGTH) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_IV_LEN) != 0) { - actual_iv_size = iv_len; - } else { - actual_iv_size = mbedtls_cipher_info_get_iv_size(ctx->cipher_info); - - /* avoid reading past the end of input buffer */ - if (actual_iv_size > iv_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - } - -#if defined(MBEDTLS_CHACHA20_C) - if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20) { - /* Even though the actual_iv_size is overwritten with a correct value - * of 12 from the cipher info, return an error to indicate that - * the input iv_len is wrong. */ - if (iv_len != 12) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (0 != mbedtls_chacha20_starts((mbedtls_chacha20_context *) ctx->cipher_ctx, - iv, - 0U)) { /* Initial counter value */ - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - } -#if defined(MBEDTLS_CHACHAPOLY_C) - if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305 && - iv_len != 12) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } -#endif -#endif - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - return mbedtls_gcm_starts((mbedtls_gcm_context *) ctx->cipher_ctx, - ctx->operation, - iv, iv_len); - } -#endif - -#if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - int set_lengths_result; - int ccm_star_mode; - - set_lengths_result = mbedtls_ccm_set_lengths( - (mbedtls_ccm_context *) ctx->cipher_ctx, - 0, 0, 0); - if (set_lengths_result != 0) { - return set_lengths_result; - } - - if (ctx->operation == MBEDTLS_DECRYPT) { - ccm_star_mode = MBEDTLS_CCM_STAR_DECRYPT; - } else if (ctx->operation == MBEDTLS_ENCRYPT) { - ccm_star_mode = MBEDTLS_CCM_STAR_ENCRYPT; - } else { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return mbedtls_ccm_starts((mbedtls_ccm_context *) ctx->cipher_ctx, - ccm_star_mode, - iv, iv_len); - } -#endif - - if (actual_iv_size != 0) { - memcpy(ctx->iv, iv, actual_iv_size); - ctx->iv_size = actual_iv_size; - } - - return 0; -} - -int mbedtls_cipher_reset(mbedtls_cipher_context_t *ctx) -{ - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* We don't support resetting PSA-based - * cipher contexts, yet. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - ctx->unprocessed_len = 0; - - return 0; -} - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) -int mbedtls_cipher_update_ad(mbedtls_cipher_context_t *ctx, - const unsigned char *ad, size_t ad_len) -{ - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - return mbedtls_gcm_update_ad((mbedtls_gcm_context *) ctx->cipher_ctx, - ad, ad_len); - } -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { - int result; - mbedtls_chachapoly_mode_t mode; - - mode = (ctx->operation == MBEDTLS_ENCRYPT) - ? MBEDTLS_CHACHAPOLY_ENCRYPT - : MBEDTLS_CHACHAPOLY_DECRYPT; - - result = mbedtls_chachapoly_starts((mbedtls_chachapoly_context *) ctx->cipher_ctx, - ctx->iv, - mode); - if (result != 0) { - return result; - } - - return mbedtls_chachapoly_update_aad((mbedtls_chachapoly_context *) ctx->cipher_ctx, - ad, ad_len); - } -#endif - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} -#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ - -int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *input, - size_t ilen, unsigned char *output, size_t *olen) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t block_size; - - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - *olen = 0; - block_size = mbedtls_cipher_get_block_size(ctx); - if (0 == block_size) { - return MBEDTLS_ERR_CIPHER_INVALID_CONTEXT; - } - - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_ECB) { - if (ilen != block_size) { - return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; - } - - *olen = ilen; - - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ecb_func(ctx->cipher_ctx, - ctx->operation, input, - output))) { - return ret; - } - - return 0; - } - -#if defined(MBEDTLS_GCM_C) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_GCM) { - return mbedtls_gcm_update((mbedtls_gcm_context *) ctx->cipher_ctx, - input, ilen, - output, ilen, olen); - } -#endif - -#if defined(MBEDTLS_CCM_C) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CCM_STAR_NO_TAG) { - return mbedtls_ccm_update((mbedtls_ccm_context *) ctx->cipher_ctx, - input, ilen, - output, ilen, olen); - } -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) - if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305) { - *olen = ilen; - return mbedtls_chachapoly_update((mbedtls_chachapoly_context *) ctx->cipher_ctx, - ilen, input, output); - } -#endif - - if (input == output && - (ctx->unprocessed_len != 0 || ilen % block_size)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_CIPHER_MODE_CBC) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CBC) { - size_t copy_len = 0; - - /* - * If there is not enough data for a full block, cache it. - */ - if ((ctx->operation == MBEDTLS_DECRYPT && NULL != ctx->add_padding && - ilen <= block_size - ctx->unprocessed_len) || - (ctx->operation == MBEDTLS_DECRYPT && NULL == ctx->add_padding && - ilen < block_size - ctx->unprocessed_len) || - (ctx->operation == MBEDTLS_ENCRYPT && - ilen < block_size - ctx->unprocessed_len)) { - memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), input, - ilen); - - ctx->unprocessed_len += ilen; - return 0; - } - - /* - * Process cached data first - */ - if (0 != ctx->unprocessed_len) { - copy_len = block_size - ctx->unprocessed_len; - - memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), input, - copy_len); - - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, - ctx->operation, - block_size, ctx->iv, - ctx-> - unprocessed_data, - output))) { - return ret; - } - - *olen += block_size; - output += block_size; - ctx->unprocessed_len = 0; - - input += copy_len; - ilen -= copy_len; - } - - /* - * Cache final, incomplete block - */ - if (0 != ilen) { - /* Encryption: only cache partial blocks - * Decryption w/ padding: always keep at least one whole block - * Decryption w/o padding: only cache partial blocks - */ - copy_len = ilen % block_size; - if (copy_len == 0 && - ctx->operation == MBEDTLS_DECRYPT && - NULL != ctx->add_padding) { - copy_len = block_size; - } - - memcpy(ctx->unprocessed_data, &(input[ilen - copy_len]), - copy_len); - - ctx->unprocessed_len += copy_len; - ilen -= copy_len; - } - - /* - * Process remaining full blocks - */ - if (ilen) { - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, - ctx->operation, - ilen, ctx->iv, - input, - output))) { - return ret; - } - - *olen += ilen; - } - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CFB) { - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cfb_func(ctx->cipher_ctx, - ctx->operation, ilen, - &ctx->unprocessed_len, - ctx->iv, - input, output))) { - return ret; - } - - *olen = ilen; - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_OFB) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_OFB) { - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ofb_func(ctx->cipher_ctx, - ilen, - &ctx->unprocessed_len, - ctx->iv, - input, output))) { - return ret; - } - - *olen = ilen; - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_OFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CTR) { - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func(ctx->cipher_ctx, - ilen, - &ctx->unprocessed_len, - ctx->iv, - ctx->unprocessed_data, - input, output))) { - return ret; - } - - *olen = ilen; - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_CIPHER_MODE_XTS) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_XTS) { - if (ctx->unprocessed_len > 0) { - /* We can only process an entire data unit at a time. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - ret = mbedtls_cipher_get_base(ctx->cipher_info)->xts_func(ctx->cipher_ctx, - ctx->operation, - ilen, - ctx->iv, - input, - output); - if (ret != 0) { - return ret; - } - - *olen = ilen; - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_STREAM) { - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->stream_func(ctx->cipher_ctx, - ilen, input, - output))) { - return ret; - } - - *olen = ilen; - - return 0; - } -#endif /* MBEDTLS_CIPHER_MODE_STREAM */ - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} - -#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) -/* - * PKCS7 (and PKCS5) padding: fill with ll bytes, with ll = padding_len - */ -static void add_pkcs_padding(unsigned char *output, size_t output_len, - size_t data_len) -{ - size_t padding_len = output_len - data_len; - unsigned char i; - - for (i = 0; i < padding_len; i++) { - output[data_len + i] = (unsigned char) padding_len; - } -} - -static int get_pkcs_padding(unsigned char *input, size_t input_len, - size_t *data_len) -{ - size_t i, pad_idx; - unsigned char padding_len; - - if (NULL == input || NULL == data_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - padding_len = input[input_len - 1]; - *data_len = input_len - padding_len; - - mbedtls_ct_condition_t bad = mbedtls_ct_uint_gt(padding_len, input_len); - bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); - - /* The number of bytes checked must be independent of padding_len, - * so pick input_len, which is usually 8 or 16 (one block) */ - pad_idx = input_len - padding_len; - for (i = 0; i < input_len; i++) { - mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); - mbedtls_ct_condition_t different = mbedtls_ct_uint_ne(input[i], padding_len); - bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); - } - - return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); -} -#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ - -#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) -/* - * One and zeros padding: fill with 80 00 ... 00 - */ -static void add_one_and_zeros_padding(unsigned char *output, - size_t output_len, size_t data_len) -{ - size_t padding_len = output_len - data_len; - unsigned char i = 0; - - output[data_len] = 0x80; - for (i = 1; i < padding_len; i++) { - output[data_len + i] = 0x00; - } -} - -static int get_one_and_zeros_padding(unsigned char *input, size_t input_len, - size_t *data_len) -{ - if (NULL == input || NULL == data_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - mbedtls_ct_condition_t in_padding = MBEDTLS_CT_TRUE; - mbedtls_ct_condition_t bad = MBEDTLS_CT_TRUE; - - *data_len = 0; - - for (ptrdiff_t i = (ptrdiff_t) (input_len) - 1; i >= 0; i--) { - mbedtls_ct_condition_t is_nonzero = mbedtls_ct_bool(input[i]); - - mbedtls_ct_condition_t hit_first_nonzero = mbedtls_ct_bool_and(is_nonzero, in_padding); - - *data_len = mbedtls_ct_size_if(hit_first_nonzero, i, *data_len); - - bad = mbedtls_ct_bool_if(hit_first_nonzero, mbedtls_ct_uint_ne(input[i], 0x80), bad); - - in_padding = mbedtls_ct_bool_and(in_padding, mbedtls_ct_bool_not(is_nonzero)); - } - - return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); -} -#endif /* MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS */ - -#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) -/* - * Zeros and len padding: fill with 00 ... 00 ll, where ll is padding length - */ -static void add_zeros_and_len_padding(unsigned char *output, - size_t output_len, size_t data_len) -{ - size_t padding_len = output_len - data_len; - unsigned char i = 0; - - for (i = 1; i < padding_len; i++) { - output[data_len + i - 1] = 0x00; - } - output[output_len - 1] = (unsigned char) padding_len; -} - -static int get_zeros_and_len_padding(unsigned char *input, size_t input_len, - size_t *data_len) -{ - size_t i, pad_idx; - unsigned char padding_len; - mbedtls_ct_condition_t bad; - - if (NULL == input || NULL == data_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - padding_len = input[input_len - 1]; - *data_len = input_len - padding_len; - - /* Avoid logical || since it results in a branch */ - bad = mbedtls_ct_uint_gt(padding_len, input_len); - bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); - - /* The number of bytes checked must be independent of padding_len */ - pad_idx = input_len - padding_len; - for (i = 0; i < input_len - 1; i++) { - mbedtls_ct_condition_t is_padding = mbedtls_ct_uint_ge(i, pad_idx); - mbedtls_ct_condition_t nonzero_pad_byte; - nonzero_pad_byte = mbedtls_ct_bool_if_else_0(is_padding, mbedtls_ct_bool(input[i])); - bad = mbedtls_ct_bool_or(bad, nonzero_pad_byte); - } - - return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); -} -#endif /* MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN */ - -#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) -/* - * Zero padding: fill with 00 ... 00 - */ -static void add_zeros_padding(unsigned char *output, - size_t output_len, size_t data_len) -{ - memset(output + data_len, 0, output_len - data_len); -} - -static int get_zeros_padding(unsigned char *input, size_t input_len, - size_t *data_len) -{ - size_t i; - mbedtls_ct_condition_t done = MBEDTLS_CT_FALSE, prev_done; - - if (NULL == input || NULL == data_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - *data_len = 0; - for (i = input_len; i > 0; i--) { - prev_done = done; - done = mbedtls_ct_bool_or(done, mbedtls_ct_uint_ne(input[i-1], 0)); - *data_len = mbedtls_ct_size_if(mbedtls_ct_bool_ne(done, prev_done), i, *data_len); - } - - return 0; -} -#endif /* MBEDTLS_CIPHER_PADDING_ZEROS */ - -/* - * No padding: don't pad :) - * - * There is no add_padding function (check for NULL in mbedtls_cipher_finish) - * but a trivial get_padding function - */ -static int get_no_padding(unsigned char *input, size_t input_len, - size_t *data_len) -{ - if (NULL == input || NULL == data_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - *data_len = input_len; - - return 0; -} -#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ - -int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, - unsigned char *output, size_t *olen) -{ - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - *olen = 0; - -#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) - /* CBC mode requires padding so we make sure a call to - * mbedtls_cipher_set_padding_mode has been done successfully. */ - if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - if (ctx->get_padding == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - } -#endif - - if (MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_CTR == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_XTS == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_STREAM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - return 0; - } - - if ((MBEDTLS_CIPHER_CHACHA20 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) || - (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type))) { - return 0; - } - - if (MBEDTLS_MODE_ECB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - if (ctx->unprocessed_len != 0) { - return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; - } - - return 0; - } - -#if defined(MBEDTLS_CIPHER_MODE_CBC) - if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - int ret = 0; - - if (MBEDTLS_ENCRYPT == ctx->operation) { - /* check for 'no padding' mode */ - if (NULL == ctx->add_padding) { - if (0 != ctx->unprocessed_len) { - return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; - } - - return 0; - } - - ctx->add_padding(ctx->unprocessed_data, mbedtls_cipher_get_iv_size(ctx), - ctx->unprocessed_len); - } else if (mbedtls_cipher_get_block_size(ctx) != ctx->unprocessed_len) { - /* - * For decrypt operations, expect a full block, - * or an empty block if no padding - */ - if (NULL == ctx->add_padding && 0 == ctx->unprocessed_len) { - return 0; - } - - return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; - } - - /* cipher block */ - if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, - ctx->operation, - mbedtls_cipher_get_block_size( - ctx), - ctx->iv, - ctx->unprocessed_data, - output))) { - return ret; - } - - /* Set output size for decryption */ - if (MBEDTLS_DECRYPT == ctx->operation) { - return ctx->get_padding(output, mbedtls_cipher_get_block_size(ctx), - olen); - } - - /* Set output size for encryption */ - *olen = mbedtls_cipher_get_block_size(ctx); - return 0; - } -#else - ((void) output); -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} - -#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) -int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, - mbedtls_cipher_padding_t mode) -{ - if (NULL == ctx->cipher_info || - MBEDTLS_MODE_CBC != ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto knows about CBC padding - * schemes, we currently don't make them - * accessible through the cipher layer. */ - if (mode != MBEDTLS_PADDING_NONE) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - return 0; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - switch (mode) { -#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) - case MBEDTLS_PADDING_PKCS7: - ctx->add_padding = add_pkcs_padding; - ctx->get_padding = get_pkcs_padding; - break; -#endif -#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) - case MBEDTLS_PADDING_ONE_AND_ZEROS: - ctx->add_padding = add_one_and_zeros_padding; - ctx->get_padding = get_one_and_zeros_padding; - break; -#endif -#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) - case MBEDTLS_PADDING_ZEROS_AND_LEN: - ctx->add_padding = add_zeros_and_len_padding; - ctx->get_padding = get_zeros_and_len_padding; - break; -#endif -#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) - case MBEDTLS_PADDING_ZEROS: - ctx->add_padding = add_zeros_padding; - ctx->get_padding = get_zeros_padding; - break; -#endif - case MBEDTLS_PADDING_NONE: - ctx->add_padding = NULL; - ctx->get_padding = get_no_padding; - break; - - default: - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - return 0; -} -#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) -int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, - unsigned char *tag, size_t tag_len) -{ - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (MBEDTLS_ENCRYPT != ctx->operation) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - size_t output_length; - /* The code here doesn't yet support alternative implementations - * that can delay up to a block of output. */ - return mbedtls_gcm_finish((mbedtls_gcm_context *) ctx->cipher_ctx, - NULL, 0, &output_length, - tag, tag_len); - } -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { - /* Don't allow truncated MAC for Poly1305 */ - if (tag_len != 16U) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return mbedtls_chachapoly_finish( - (mbedtls_chachapoly_context *) ctx->cipher_ctx, tag); - } -#endif - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} - -int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, - const unsigned char *tag, size_t tag_len) -{ - unsigned char check_tag[16]; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - if (ctx->cipher_info == NULL) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (MBEDTLS_DECRYPT != ctx->operation) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* While PSA Crypto has an API for multipart - * operations, we currently don't make it - * accessible through the cipher layer. */ - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - /* Status to return on a non-authenticated algorithm. */ - ret = MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - size_t output_length; - /* The code here doesn't yet support alternative implementations - * that can delay up to a block of output. */ - - if (tag_len > sizeof(check_tag)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (0 != (ret = mbedtls_gcm_finish( - (mbedtls_gcm_context *) ctx->cipher_ctx, - NULL, 0, &output_length, - check_tag, tag_len))) { - return ret; - } - - /* Check the tag in "constant-time" */ - if (mbedtls_ct_memcmp(tag, check_tag, tag_len) != 0) { - ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; - goto exit; - } - } -#endif /* MBEDTLS_GCM_C */ - -#if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { - /* Don't allow truncated MAC for Poly1305 */ - if (tag_len != sizeof(check_tag)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - ret = mbedtls_chachapoly_finish( - (mbedtls_chachapoly_context *) ctx->cipher_ctx, check_tag); - if (ret != 0) { - return ret; - } - - /* Check the tag in "constant-time" */ - if (mbedtls_ct_memcmp(tag, check_tag, tag_len) != 0) { - ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; - goto exit; - } - } -#endif /* MBEDTLS_CHACHAPOLY_C */ - -exit: - mbedtls_platform_zeroize(check_tag, tag_len); - return ret; -} -#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ - -/* - * Packet-oriented wrapper for non-AEAD modes - */ -int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t finish_olen; - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* As in the non-PSA case, we don't check that - * a key has been set. If not, the key slot will - * still be in its default state of 0, which is - * guaranteed to be invalid, hence the PSA-call - * below will gracefully fail. */ - mbedtls_cipher_context_psa * const cipher_psa = - (mbedtls_cipher_context_psa *) ctx->cipher_ctx; - - psa_status_t status; - psa_cipher_operation_t cipher_op = PSA_CIPHER_OPERATION_INIT; - size_t part_len; - - if (ctx->operation == MBEDTLS_DECRYPT) { - status = psa_cipher_decrypt_setup(&cipher_op, - cipher_psa->slot, - cipher_psa->alg); - } else if (ctx->operation == MBEDTLS_ENCRYPT) { - status = psa_cipher_encrypt_setup(&cipher_op, - cipher_psa->slot, - cipher_psa->alg); - } else { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - /* In the following, we can immediately return on an error, - * because the PSA Crypto API guarantees that cipher operations - * are terminated by unsuccessful calls to psa_cipher_update(), - * and by any call to psa_cipher_finish(). */ - if (status == PSA_ERROR_NOT_SUPPORTED) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } else if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) != MBEDTLS_MODE_ECB) { - status = psa_cipher_set_iv(&cipher_op, iv, iv_len); - if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - } - - status = psa_cipher_update(&cipher_op, - input, ilen, - output, ilen, olen); - if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - status = psa_cipher_finish(&cipher_op, - output + *olen, ilen - *olen, - &part_len); - if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - *olen += part_len; - return 0; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - - if ((ret = mbedtls_cipher_set_iv(ctx, iv, iv_len)) != 0) { - return ret; - } - - if ((ret = mbedtls_cipher_reset(ctx)) != 0) { - return ret; - } - - if ((ret = mbedtls_cipher_update(ctx, input, ilen, - output, olen)) != 0) { - return ret; - } - - if ((ret = mbedtls_cipher_finish(ctx, output + *olen, - &finish_olen)) != 0) { - return ret; - } - - *olen += finish_olen; - - return 0; -} - -#if defined(MBEDTLS_CIPHER_MODE_AEAD) -/* - * Packet-oriented encryption for AEAD modes: internal function used by - * mbedtls_cipher_auth_encrypt_ext(). - */ -static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, - unsigned char *tag, size_t tag_len) -{ -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* As in the non-PSA case, we don't check that - * a key has been set. If not, the key slot will - * still be in its default state of 0, which is - * guaranteed to be invalid, hence the PSA-call - * below will gracefully fail. */ - mbedtls_cipher_context_psa * const cipher_psa = - (mbedtls_cipher_context_psa *) ctx->cipher_ctx; - - psa_status_t status; - - /* PSA Crypto API always writes the authentication tag - * at the end of the encrypted message. */ - if (output == NULL || tag != output + ilen) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - status = psa_aead_encrypt(cipher_psa->slot, - cipher_psa->alg, - iv, iv_len, - ad, ad_len, - input, ilen, - output, ilen + tag_len, olen); - if (status == PSA_ERROR_NOT_SUPPORTED) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } else if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - *olen -= tag_len; - return 0; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - *olen = ilen; - return mbedtls_gcm_crypt_and_tag(ctx->cipher_ctx, MBEDTLS_GCM_ENCRYPT, - ilen, iv, iv_len, ad, ad_len, - input, output, tag_len, tag); - } -#endif /* MBEDTLS_GCM_C */ -#if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - *olen = ilen; - return mbedtls_ccm_encrypt_and_tag(ctx->cipher_ctx, ilen, - iv, iv_len, ad, ad_len, input, output, - tag, tag_len); - } -#endif /* MBEDTLS_CCM_C */ -#if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { - /* ChachaPoly has fixed length nonce and MAC (tag) */ - if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || - (tag_len != 16U)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - *olen = ilen; - return mbedtls_chachapoly_encrypt_and_tag(ctx->cipher_ctx, - ilen, iv, ad, ad_len, input, output, tag); - } -#endif /* MBEDTLS_CHACHAPOLY_C */ - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} - -/* - * Packet-oriented encryption for AEAD modes: internal function used by - * mbedtls_cipher_auth_encrypt_ext(). - */ -static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, - const unsigned char *tag, size_t tag_len) -{ -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ctx->psa_enabled == 1) { - /* As in the non-PSA case, we don't check that - * a key has been set. If not, the key slot will - * still be in its default state of 0, which is - * guaranteed to be invalid, hence the PSA-call - * below will gracefully fail. */ - mbedtls_cipher_context_psa * const cipher_psa = - (mbedtls_cipher_context_psa *) ctx->cipher_ctx; - - psa_status_t status; - - /* PSA Crypto API always writes the authentication tag - * at the end of the encrypted message. */ - if (input == NULL || tag != input + ilen) { - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; - } - - status = psa_aead_decrypt(cipher_psa->slot, - cipher_psa->alg, - iv, iv_len, - ad, ad_len, - input, ilen + tag_len, - output, ilen, olen); - if (status == PSA_ERROR_INVALID_SIGNATURE) { - return MBEDTLS_ERR_CIPHER_AUTH_FAILED; - } else if (status == PSA_ERROR_NOT_SUPPORTED) { - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - } else if (status != PSA_SUCCESS) { - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } - - return 0; - } -#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_GCM_C) - if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - *olen = ilen; - ret = mbedtls_gcm_auth_decrypt(ctx->cipher_ctx, ilen, - iv, iv_len, ad, ad_len, - tag, tag_len, input, output); - - if (ret == MBEDTLS_ERR_GCM_AUTH_FAILED) { - ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; - } - - return ret; - } -#endif /* MBEDTLS_GCM_C */ -#if defined(MBEDTLS_CCM_C) - if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - *olen = ilen; - ret = mbedtls_ccm_auth_decrypt(ctx->cipher_ctx, ilen, - iv, iv_len, ad, ad_len, - input, output, tag, tag_len); - - if (ret == MBEDTLS_ERR_CCM_AUTH_FAILED) { - ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; - } - - return ret; - } -#endif /* MBEDTLS_CCM_C */ -#if defined(MBEDTLS_CHACHAPOLY_C) - if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - /* ChachaPoly has fixed length nonce and MAC (tag) */ - if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || - (tag_len != 16U)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - *olen = ilen; - ret = mbedtls_chachapoly_auth_decrypt(ctx->cipher_ctx, ilen, - iv, ad, ad_len, tag, input, output); - - if (ret == MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED) { - ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; - } - - return ret; - } -#endif /* MBEDTLS_CHACHAPOLY_C */ - - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -} -#endif /* MBEDTLS_CIPHER_MODE_AEAD */ - -#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) -/* - * Packet-oriented encryption for AEAD/NIST_KW: public function. - */ -int mbedtls_cipher_auth_encrypt_ext(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t output_len, - size_t *olen, size_t tag_len) -{ -#if defined(MBEDTLS_NIST_KW_C) - if ( -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - ctx->psa_enabled == 0 && -#endif - (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { - mbedtls_nist_kw_mode_t mode = - (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? - MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; - - /* There is no iv, tag or ad associated with KW and KWP, - * so these length should be 0 as documented. */ - if (iv_len != 0 || tag_len != 0 || ad_len != 0) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - (void) iv; - (void) ad; - - return mbedtls_nist_kw_wrap(ctx->cipher_ctx, mode, input, ilen, - output, olen, output_len); - } -#endif /* MBEDTLS_NIST_KW_C */ - -#if defined(MBEDTLS_CIPHER_MODE_AEAD) - /* AEAD case: check length before passing on to shared function */ - if (output_len < ilen + tag_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - int ret = mbedtls_cipher_aead_encrypt(ctx, iv, iv_len, ad, ad_len, - input, ilen, output, olen, - output + ilen, tag_len); - *olen += tag_len; - return ret; -#else - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -#endif /* MBEDTLS_CIPHER_MODE_AEAD */ -} - -/* - * Packet-oriented decryption for AEAD/NIST_KW: public function. - */ -int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, - const unsigned char *iv, size_t iv_len, - const unsigned char *ad, size_t ad_len, - const unsigned char *input, size_t ilen, - unsigned char *output, size_t output_len, - size_t *olen, size_t tag_len) -{ -#if defined(MBEDTLS_NIST_KW_C) - if ( -#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) - ctx->psa_enabled == 0 && -#endif - (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || - MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { - mbedtls_nist_kw_mode_t mode = - (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? - MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; - - /* There is no iv, tag or ad associated with KW and KWP, - * so these length should be 0 as documented. */ - if (iv_len != 0 || tag_len != 0 || ad_len != 0) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - (void) iv; - (void) ad; - - return mbedtls_nist_kw_unwrap(ctx->cipher_ctx, mode, input, ilen, - output, olen, output_len); - } -#endif /* MBEDTLS_NIST_KW_C */ - -#if defined(MBEDTLS_CIPHER_MODE_AEAD) - /* AEAD case: check length before passing on to shared function */ - if (ilen < tag_len || output_len < ilen - tag_len) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return mbedtls_cipher_aead_decrypt(ctx, iv, iv_len, ad, ad_len, - input, ilen - tag_len, output, olen, - input + ilen - tag_len, tag_len); -#else - return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; -#endif /* MBEDTLS_CIPHER_MODE_AEAD */ -} -#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ - -#endif /* MBEDTLS_CIPHER_C */ +/** + * \file cipher.c + * + * \brief Generic cipher wrapper for Mbed TLS + * + * \author Adriaan de Jong + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_CIPHER_C) + +#include "mbedtls/cipher.h" +#include "cipher_wrap.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" +#include "mbedtls/constant_time.h" +#include "constant_time_internal.h" + +#include +#include + +#if defined(MBEDTLS_CHACHAPOLY_C) +#include "mbedtls/chachapoly.h" +#endif + +#if defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#endif + +#if defined(MBEDTLS_CCM_C) +#include "mbedtls/ccm.h" +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#include "mbedtls/chacha20.h" +#endif + +#if defined(MBEDTLS_CMAC_C) +#include "mbedtls/cmac.h" +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) +#include "psa/crypto.h" +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_NIST_KW_C) +#include "mbedtls/nist_kw.h" +#endif + +#include "mbedtls/platform.h" + +static int supported_init = 0; + +static inline const mbedtls_cipher_base_t *mbedtls_cipher_get_base( + const mbedtls_cipher_info_t *info) +{ + return mbedtls_cipher_base_lookup_table[info->base_idx]; +} + +const int *mbedtls_cipher_list(void) +{ + const mbedtls_cipher_definition_t *def; + int *type; + + if (!supported_init) { + def = mbedtls_cipher_definitions; + type = mbedtls_cipher_supported; + + while (def->type != 0) { + *type++ = (*def++).type; + } + + *type = 0; + + supported_init = 1; + } + + return mbedtls_cipher_supported; +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_type( + const mbedtls_cipher_type_t cipher_type) +{ + const mbedtls_cipher_definition_t *def; + + for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { + if (def->type == cipher_type) { + return def->info; + } + } + + return NULL; +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_string( + const char *cipher_name) +{ + const mbedtls_cipher_definition_t *def; + + if (NULL == cipher_name) { + return NULL; + } + + for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { + if (!strcmp(def->info->name, cipher_name)) { + return def->info; + } + } + + return NULL; +} + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_values( + const mbedtls_cipher_id_t cipher_id, + int key_bitlen, + const mbedtls_cipher_mode_t mode) +{ + const mbedtls_cipher_definition_t *def; + + for (def = mbedtls_cipher_definitions; def->info != NULL; def++) { + if (mbedtls_cipher_get_base(def->info)->cipher == cipher_id && + mbedtls_cipher_info_get_key_bitlen(def->info) == (unsigned) key_bitlen && + def->info->mode == mode) { + return def->info; + } + } + + return NULL; +} + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) +static inline psa_key_type_t mbedtls_psa_translate_cipher_type( + mbedtls_cipher_type_t cipher) +{ + switch (cipher) { + case MBEDTLS_CIPHER_AES_128_CCM: + case MBEDTLS_CIPHER_AES_192_CCM: + case MBEDTLS_CIPHER_AES_256_CCM: + case MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_AES_128_GCM: + case MBEDTLS_CIPHER_AES_192_GCM: + case MBEDTLS_CIPHER_AES_256_GCM: + case MBEDTLS_CIPHER_AES_128_CBC: + case MBEDTLS_CIPHER_AES_192_CBC: + case MBEDTLS_CIPHER_AES_256_CBC: + case MBEDTLS_CIPHER_AES_128_ECB: + case MBEDTLS_CIPHER_AES_192_ECB: + case MBEDTLS_CIPHER_AES_256_ECB: + return PSA_KEY_TYPE_AES; + + /* ARIA not yet supported in PSA. */ + /* case MBEDTLS_CIPHER_ARIA_128_CCM: + case MBEDTLS_CIPHER_ARIA_192_CCM: + case MBEDTLS_CIPHER_ARIA_256_CCM: + case MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG: + case MBEDTLS_CIPHER_ARIA_128_GCM: + case MBEDTLS_CIPHER_ARIA_192_GCM: + case MBEDTLS_CIPHER_ARIA_256_GCM: + case MBEDTLS_CIPHER_ARIA_128_CBC: + case MBEDTLS_CIPHER_ARIA_192_CBC: + case MBEDTLS_CIPHER_ARIA_256_CBC: + return( PSA_KEY_TYPE_ARIA ); */ + + default: + return 0; + } +} + +static inline psa_algorithm_t mbedtls_psa_translate_cipher_mode( + mbedtls_cipher_mode_t mode, size_t taglen) +{ + switch (mode) { + case MBEDTLS_MODE_ECB: + return PSA_ALG_ECB_NO_PADDING; + case MBEDTLS_MODE_GCM: + return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, taglen); + case MBEDTLS_MODE_CCM: + return PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, taglen); + case MBEDTLS_MODE_CCM_STAR_NO_TAG: + return PSA_ALG_CCM_STAR_NO_TAG; + case MBEDTLS_MODE_CBC: + if (taglen == 0) { + return PSA_ALG_CBC_NO_PADDING; + } else { + return 0; + } + default: + return 0; + } +} +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +void mbedtls_cipher_init(mbedtls_cipher_context_t *ctx) +{ + memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); +} + +void mbedtls_cipher_free(mbedtls_cipher_context_t *ctx) +{ + if (ctx == NULL) { + return; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + if (ctx->cipher_ctx != NULL) { + mbedtls_cipher_context_psa * const cipher_psa = + (mbedtls_cipher_context_psa *) ctx->cipher_ctx; + + if (cipher_psa->slot_state == MBEDTLS_CIPHER_PSA_KEY_OWNED) { + /* xxx_free() doesn't allow to return failures. */ + (void) psa_destroy_key(cipher_psa->slot); + } + + mbedtls_zeroize_and_free(cipher_psa, sizeof(*cipher_psa)); + } + + mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); + return; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_CMAC_C) + if (ctx->cmac_ctx) { + mbedtls_zeroize_and_free(ctx->cmac_ctx, + sizeof(mbedtls_cmac_context_t)); + } +#endif + + if (ctx->cipher_ctx) { + mbedtls_cipher_get_base(ctx->cipher_info)->ctx_free_func(ctx->cipher_ctx); + } + + mbedtls_platform_zeroize(ctx, sizeof(mbedtls_cipher_context_t)); +} + +int mbedtls_cipher_setup(mbedtls_cipher_context_t *ctx, + const mbedtls_cipher_info_t *cipher_info) +{ + if (cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); + + if (NULL == (ctx->cipher_ctx = mbedtls_cipher_get_base(cipher_info)->ctx_alloc_func())) { + return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; + } + + ctx->cipher_info = cipher_info; + + return 0; +} + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) +int mbedtls_cipher_setup_psa(mbedtls_cipher_context_t *ctx, + const mbedtls_cipher_info_t *cipher_info, + size_t taglen) +{ + psa_algorithm_t alg; + mbedtls_cipher_context_psa *cipher_psa; + + if (NULL == cipher_info || NULL == ctx) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + /* Check that the underlying cipher mode and cipher type are + * supported by the underlying PSA Crypto implementation. */ + alg = mbedtls_psa_translate_cipher_mode(((mbedtls_cipher_mode_t) cipher_info->mode), taglen); + if (alg == 0) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + if (mbedtls_psa_translate_cipher_type(((mbedtls_cipher_type_t) cipher_info->type)) == 0) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + memset(ctx, 0, sizeof(mbedtls_cipher_context_t)); + + cipher_psa = mbedtls_calloc(1, sizeof(mbedtls_cipher_context_psa)); + if (cipher_psa == NULL) { + return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; + } + cipher_psa->alg = alg; + ctx->cipher_ctx = cipher_psa; + ctx->cipher_info = cipher_info; + ctx->psa_enabled = 1; + return 0; +} +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +int mbedtls_cipher_setkey(mbedtls_cipher_context_t *ctx, + const unsigned char *key, + int key_bitlen, + const mbedtls_operation_t operation) +{ + if (operation != MBEDTLS_ENCRYPT && operation != MBEDTLS_DECRYPT) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + mbedtls_cipher_context_psa * const cipher_psa = + (mbedtls_cipher_context_psa *) ctx->cipher_ctx; + + size_t const key_bytelen = ((size_t) key_bitlen + 7) / 8; + + psa_status_t status; + psa_key_type_t key_type; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + + /* PSA Crypto API only accepts byte-aligned keys. */ + if (key_bitlen % 8 != 0) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + /* Don't allow keys to be set multiple times. */ + if (cipher_psa->slot_state != MBEDTLS_CIPHER_PSA_KEY_UNSET) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + key_type = mbedtls_psa_translate_cipher_type( + ((mbedtls_cipher_type_t) ctx->cipher_info->type)); + if (key_type == 0) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + psa_set_key_type(&attributes, key_type); + + /* Mbed TLS' cipher layer doesn't enforce the mode of operation + * (encrypt vs. decrypt): it is possible to setup a key for encryption + * and use it for AEAD decryption. Until tests relying on this + * are changed, allow any usage in PSA. */ + psa_set_key_usage_flags(&attributes, + PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT); + psa_set_key_algorithm(&attributes, cipher_psa->alg); + + status = psa_import_key(&attributes, key, key_bytelen, + &cipher_psa->slot); + switch (status) { + case PSA_SUCCESS: + break; + case PSA_ERROR_INSUFFICIENT_MEMORY: + return MBEDTLS_ERR_CIPHER_ALLOC_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + default: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + /* Indicate that we own the key slot and need to + * destroy it in mbedtls_cipher_free(). */ + cipher_psa->slot_state = MBEDTLS_CIPHER_PSA_KEY_OWNED; + + ctx->key_bitlen = key_bitlen; + ctx->operation = operation; + return 0; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_KEY_LEN) == 0 && + (int) mbedtls_cipher_info_get_key_bitlen(ctx->cipher_info) != key_bitlen) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + ctx->key_bitlen = key_bitlen; + ctx->operation = operation; + + /* + * For OFB, CFB and CTR mode always use the encryption key schedule + */ + if (MBEDTLS_ENCRYPT == operation || + MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_CTR == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_enc_func(ctx->cipher_ctx, key, + ctx->key_bitlen); + } + + if (MBEDTLS_DECRYPT == operation) { + return mbedtls_cipher_get_base(ctx->cipher_info)->setkey_dec_func(ctx->cipher_ctx, key, + ctx->key_bitlen); + } + + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; +} + +int mbedtls_cipher_set_iv(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, + size_t iv_len) +{ + size_t actual_iv_size; + + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + /* avoid buffer overflow in ctx->iv */ + if (iv_len > MBEDTLS_MAX_IV_LENGTH) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + if ((ctx->cipher_info->flags & MBEDTLS_CIPHER_VARIABLE_IV_LEN) != 0) { + actual_iv_size = iv_len; + } else { + actual_iv_size = mbedtls_cipher_info_get_iv_size(ctx->cipher_info); + + /* avoid reading past the end of input buffer */ + if (actual_iv_size > iv_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + } + +#if defined(MBEDTLS_CHACHA20_C) + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20) { + /* Even though the actual_iv_size is overwritten with a correct value + * of 12 from the cipher info, return an error to indicate that + * the input iv_len is wrong. */ + if (iv_len != 12) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (0 != mbedtls_chacha20_starts((mbedtls_chacha20_context *) ctx->cipher_ctx, + iv, + 0U)) { /* Initial counter value */ + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + } +#if defined(MBEDTLS_CHACHAPOLY_C) + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305 && + iv_len != 12) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } +#endif +#endif + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return mbedtls_gcm_starts((mbedtls_gcm_context *) ctx->cipher_ctx, + ctx->operation, + iv, iv_len); + } +#endif + +#if defined(MBEDTLS_CCM_C) + if (MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + int set_lengths_result; + int ccm_star_mode; + + set_lengths_result = mbedtls_ccm_set_lengths( + (mbedtls_ccm_context *) ctx->cipher_ctx, + 0, 0, 0); + if (set_lengths_result != 0) { + return set_lengths_result; + } + + if (ctx->operation == MBEDTLS_DECRYPT) { + ccm_star_mode = MBEDTLS_CCM_STAR_DECRYPT; + } else if (ctx->operation == MBEDTLS_ENCRYPT) { + ccm_star_mode = MBEDTLS_CCM_STAR_ENCRYPT; + } else { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return mbedtls_ccm_starts((mbedtls_ccm_context *) ctx->cipher_ctx, + ccm_star_mode, + iv, iv_len); + } +#endif + + if (actual_iv_size != 0) { + memcpy(ctx->iv, iv, actual_iv_size); + ctx->iv_size = actual_iv_size; + } + + return 0; +} + +int mbedtls_cipher_reset(mbedtls_cipher_context_t *ctx) +{ + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* We don't support resetting PSA-based + * cipher contexts, yet. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + ctx->unprocessed_len = 0; + + return 0; +} + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +int mbedtls_cipher_update_ad(mbedtls_cipher_context_t *ctx, + const unsigned char *ad, size_t ad_len) +{ + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return mbedtls_gcm_update_ad((mbedtls_gcm_context *) ctx->cipher_ctx, + ad, ad_len); + } +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { + int result; + mbedtls_chachapoly_mode_t mode; + + mode = (ctx->operation == MBEDTLS_ENCRYPT) + ? MBEDTLS_CHACHAPOLY_ENCRYPT + : MBEDTLS_CHACHAPOLY_DECRYPT; + + result = mbedtls_chachapoly_starts((mbedtls_chachapoly_context *) ctx->cipher_ctx, + ctx->iv, + mode); + if (result != 0) { + return result; + } + + return mbedtls_chachapoly_update_aad((mbedtls_chachapoly_context *) ctx->cipher_ctx, + ad, ad_len); + } +#endif + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +int mbedtls_cipher_update(mbedtls_cipher_context_t *ctx, const unsigned char *input, + size_t ilen, unsigned char *output, size_t *olen) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t block_size; + + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + *olen = 0; + block_size = mbedtls_cipher_get_block_size(ctx); + if (0 == block_size) { + return MBEDTLS_ERR_CIPHER_INVALID_CONTEXT; + } + + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_ECB) { + if (ilen != block_size) { + return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; + } + + *olen = ilen; + + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ecb_func(ctx->cipher_ctx, + ctx->operation, input, + output))) { + return ret; + } + + return 0; + } + +#if defined(MBEDTLS_GCM_C) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_GCM) { + return mbedtls_gcm_update((mbedtls_gcm_context *) ctx->cipher_ctx, + input, ilen, + output, ilen, olen); + } +#endif + +#if defined(MBEDTLS_CCM_C) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CCM_STAR_NO_TAG) { + return mbedtls_ccm_update((mbedtls_ccm_context *) ctx->cipher_ctx, + input, ilen, + output, ilen, olen); + } +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if (((mbedtls_cipher_type_t) ctx->cipher_info->type) == MBEDTLS_CIPHER_CHACHA20_POLY1305) { + *olen = ilen; + return mbedtls_chachapoly_update((mbedtls_chachapoly_context *) ctx->cipher_ctx, + ilen, input, output); + } +#endif + + if (input == output && + (ctx->unprocessed_len != 0 || ilen % block_size)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CBC) { + size_t copy_len = 0; + + /* + * If there is not enough data for a full block, cache it. + */ + if ((ctx->operation == MBEDTLS_DECRYPT && NULL != ctx->add_padding && + ilen <= block_size - ctx->unprocessed_len) || + (ctx->operation == MBEDTLS_DECRYPT && NULL == ctx->add_padding && + ilen < block_size - ctx->unprocessed_len) || + (ctx->operation == MBEDTLS_ENCRYPT && + ilen < block_size - ctx->unprocessed_len)) { + memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), input, + ilen); + + ctx->unprocessed_len += ilen; + return 0; + } + + /* + * Process cached data first + */ + if (0 != ctx->unprocessed_len) { + copy_len = block_size - ctx->unprocessed_len; + + memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), input, + copy_len); + + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, + ctx->operation, + block_size, ctx->iv, + ctx-> + unprocessed_data, + output))) { + return ret; + } + + *olen += block_size; + output += block_size; + ctx->unprocessed_len = 0; + + input += copy_len; + ilen -= copy_len; + } + + /* + * Cache final, incomplete block + */ + if (0 != ilen) { + /* Encryption: only cache partial blocks + * Decryption w/ padding: always keep at least one whole block + * Decryption w/o padding: only cache partial blocks + */ + copy_len = ilen % block_size; + if (copy_len == 0 && + ctx->operation == MBEDTLS_DECRYPT && + NULL != ctx->add_padding) { + copy_len = block_size; + } + + memcpy(ctx->unprocessed_data, &(input[ilen - copy_len]), + copy_len); + + ctx->unprocessed_len += copy_len; + ilen -= copy_len; + } + + /* + * Process remaining full blocks + */ + if (ilen) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, + ctx->operation, + ilen, ctx->iv, + input, + output))) { + return ret; + } + + *olen += ilen; + } + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CFB) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cfb_func(ctx->cipher_ctx, + ctx->operation, ilen, + &ctx->unprocessed_len, + ctx->iv, + input, output))) { + return ret; + } + + *olen = ilen; + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_OFB) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ofb_func(ctx->cipher_ctx, + ilen, + &ctx->unprocessed_len, + ctx->iv, + input, output))) { + return ret; + } + + *olen = ilen; + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_CTR) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->ctr_func(ctx->cipher_ctx, + ilen, + &ctx->unprocessed_len, + ctx->iv, + ctx->unprocessed_data, + input, output))) { + return ret; + } + + *olen = ilen; + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_XTS) { + if (ctx->unprocessed_len > 0) { + /* We can only process an entire data unit at a time. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + ret = mbedtls_cipher_get_base(ctx->cipher_info)->xts_func(ctx->cipher_ctx, + ctx->operation, + ilen, + ctx->iv, + input, + output); + if (ret != 0) { + return ret; + } + + *olen = ilen; + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) == MBEDTLS_MODE_STREAM) { + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->stream_func(ctx->cipher_ctx, + ilen, input, + output))) { + return ret; + } + + *olen = ilen; + + return 0; + } +#endif /* MBEDTLS_CIPHER_MODE_STREAM */ + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) +/* + * PKCS7 (and PKCS5) padding: fill with ll bytes, with ll = padding_len + */ +static void add_pkcs_padding(unsigned char *output, size_t output_len, + size_t data_len) +{ + size_t padding_len = output_len - data_len; + unsigned char i; + + for (i = 0; i < padding_len; i++) { + output[data_len + i] = (unsigned char) padding_len; + } +} + +static int get_pkcs_padding(unsigned char *input, size_t input_len, + size_t *data_len) +{ + size_t i, pad_idx; + unsigned char padding_len; + + if (NULL == input || NULL == data_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + padding_len = input[input_len - 1]; + *data_len = input_len - padding_len; + + mbedtls_ct_condition_t bad = mbedtls_ct_uint_gt(padding_len, input_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); + + /* The number of bytes checked must be independent of padding_len, + * so pick input_len, which is usually 8 or 16 (one block) */ + pad_idx = input_len - padding_len; + for (i = 0; i < input_len; i++) { + mbedtls_ct_condition_t in_padding = mbedtls_ct_uint_ge(i, pad_idx); + mbedtls_ct_condition_t different = mbedtls_ct_uint_ne(input[i], padding_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_bool_and(in_padding, different)); + } + + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); +} +#endif /* MBEDTLS_CIPHER_PADDING_PKCS7 */ + +#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) +/* + * One and zeros padding: fill with 80 00 ... 00 + */ +static void add_one_and_zeros_padding(unsigned char *output, + size_t output_len, size_t data_len) +{ + size_t padding_len = output_len - data_len; + unsigned char i = 0; + + output[data_len] = 0x80; + for (i = 1; i < padding_len; i++) { + output[data_len + i] = 0x00; + } +} + +static int get_one_and_zeros_padding(unsigned char *input, size_t input_len, + size_t *data_len) +{ + if (NULL == input || NULL == data_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + mbedtls_ct_condition_t in_padding = MBEDTLS_CT_TRUE; + mbedtls_ct_condition_t bad = MBEDTLS_CT_TRUE; + + *data_len = 0; + + for (ptrdiff_t i = (ptrdiff_t) (input_len) - 1; i >= 0; i--) { + mbedtls_ct_condition_t is_nonzero = mbedtls_ct_bool(input[i]); + + mbedtls_ct_condition_t hit_first_nonzero = mbedtls_ct_bool_and(is_nonzero, in_padding); + + *data_len = mbedtls_ct_size_if(hit_first_nonzero, i, *data_len); + + bad = mbedtls_ct_bool_if(hit_first_nonzero, mbedtls_ct_uint_ne(input[i], 0x80), bad); + + in_padding = mbedtls_ct_bool_and(in_padding, mbedtls_ct_bool_not(is_nonzero)); + } + + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); +} +#endif /* MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS */ + +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) +/* + * Zeros and len padding: fill with 00 ... 00 ll, where ll is padding length + */ +static void add_zeros_and_len_padding(unsigned char *output, + size_t output_len, size_t data_len) +{ + size_t padding_len = output_len - data_len; + unsigned char i = 0; + + for (i = 1; i < padding_len; i++) { + output[data_len + i - 1] = 0x00; + } + output[output_len - 1] = (unsigned char) padding_len; +} + +static int get_zeros_and_len_padding(unsigned char *input, size_t input_len, + size_t *data_len) +{ + size_t i, pad_idx; + unsigned char padding_len; + mbedtls_ct_condition_t bad; + + if (NULL == input || NULL == data_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + padding_len = input[input_len - 1]; + *data_len = input_len - padding_len; + + /* Avoid logical || since it results in a branch */ + bad = mbedtls_ct_uint_gt(padding_len, input_len); + bad = mbedtls_ct_bool_or(bad, mbedtls_ct_uint_eq(padding_len, 0)); + + /* The number of bytes checked must be independent of padding_len */ + pad_idx = input_len - padding_len; + for (i = 0; i < input_len - 1; i++) { + mbedtls_ct_condition_t is_padding = mbedtls_ct_uint_ge(i, pad_idx); + mbedtls_ct_condition_t nonzero_pad_byte; + nonzero_pad_byte = mbedtls_ct_bool_if_else_0(is_padding, mbedtls_ct_bool(input[i])); + bad = mbedtls_ct_bool_or(bad, nonzero_pad_byte); + } + + return mbedtls_ct_error_if_else_0(bad, MBEDTLS_ERR_CIPHER_INVALID_PADDING); +} +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN */ + +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) +/* + * Zero padding: fill with 00 ... 00 + */ +static void add_zeros_padding(unsigned char *output, + size_t output_len, size_t data_len) +{ + memset(output + data_len, 0, output_len - data_len); +} + +static int get_zeros_padding(unsigned char *input, size_t input_len, + size_t *data_len) +{ + size_t i; + mbedtls_ct_condition_t done = MBEDTLS_CT_FALSE, prev_done; + + if (NULL == input || NULL == data_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + *data_len = 0; + for (i = input_len; i > 0; i--) { + prev_done = done; + done = mbedtls_ct_bool_or(done, mbedtls_ct_uint_ne(input[i-1], 0)); + *data_len = mbedtls_ct_size_if(mbedtls_ct_bool_ne(done, prev_done), i, *data_len); + } + + return 0; +} +#endif /* MBEDTLS_CIPHER_PADDING_ZEROS */ + +/* + * No padding: don't pad :) + * + * There is no add_padding function (check for NULL in mbedtls_cipher_finish) + * but a trivial get_padding function + */ +static int get_no_padding(unsigned char *input, size_t input_len, + size_t *data_len) +{ + if (NULL == input || NULL == data_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + *data_len = input_len; + + return 0; +} +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +int mbedtls_cipher_finish(mbedtls_cipher_context_t *ctx, + unsigned char *output, size_t *olen) +{ + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + *olen = 0; + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) + /* CBC mode requires padding so we make sure a call to + * mbedtls_cipher_set_padding_mode has been done successfully. */ + if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + if (ctx->get_padding == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + } +#endif + + if (MBEDTLS_MODE_CFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_OFB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_CTR == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_CCM_STAR_NO_TAG == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_XTS == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_STREAM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return 0; + } + + if ((MBEDTLS_CIPHER_CHACHA20 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) || + (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type))) { + return 0; + } + + if (MBEDTLS_MODE_ECB == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + if (ctx->unprocessed_len != 0) { + return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; + } + + return 0; + } + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + if (MBEDTLS_MODE_CBC == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + int ret = 0; + + if (MBEDTLS_ENCRYPT == ctx->operation) { + /* check for 'no padding' mode */ + if (NULL == ctx->add_padding) { + if (0 != ctx->unprocessed_len) { + return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; + } + + return 0; + } + + ctx->add_padding(ctx->unprocessed_data, mbedtls_cipher_get_iv_size(ctx), + ctx->unprocessed_len); + } else if (mbedtls_cipher_get_block_size(ctx) != ctx->unprocessed_len) { + /* + * For decrypt operations, expect a full block, + * or an empty block if no padding + */ + if (NULL == ctx->add_padding && 0 == ctx->unprocessed_len) { + return 0; + } + + return MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED; + } + + /* cipher block */ + if (0 != (ret = mbedtls_cipher_get_base(ctx->cipher_info)->cbc_func(ctx->cipher_ctx, + ctx->operation, + mbedtls_cipher_get_block_size( + ctx), + ctx->iv, + ctx->unprocessed_data, + output))) { + return ret; + } + + /* Set output size for decryption */ + if (MBEDTLS_DECRYPT == ctx->operation) { + return ctx->get_padding(output, mbedtls_cipher_get_block_size(ctx), + olen); + } + + /* Set output size for encryption */ + *olen = mbedtls_cipher_get_block_size(ctx); + return 0; + } +#else + ((void) output); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} + +#if defined(MBEDTLS_CIPHER_MODE_WITH_PADDING) +int mbedtls_cipher_set_padding_mode(mbedtls_cipher_context_t *ctx, + mbedtls_cipher_padding_t mode) +{ + if (NULL == ctx->cipher_info || + MBEDTLS_MODE_CBC != ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto knows about CBC padding + * schemes, we currently don't make them + * accessible through the cipher layer. */ + if (mode != MBEDTLS_PADDING_NONE) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + return 0; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + switch (mode) { +#if defined(MBEDTLS_CIPHER_PADDING_PKCS7) + case MBEDTLS_PADDING_PKCS7: + ctx->add_padding = add_pkcs_padding; + ctx->get_padding = get_pkcs_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS) + case MBEDTLS_PADDING_ONE_AND_ZEROS: + ctx->add_padding = add_one_and_zeros_padding; + ctx->get_padding = get_one_and_zeros_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN) + case MBEDTLS_PADDING_ZEROS_AND_LEN: + ctx->add_padding = add_zeros_and_len_padding; + ctx->get_padding = get_zeros_and_len_padding; + break; +#endif +#if defined(MBEDTLS_CIPHER_PADDING_ZEROS) + case MBEDTLS_PADDING_ZEROS: + ctx->add_padding = add_zeros_padding; + ctx->get_padding = get_zeros_padding; + break; +#endif + case MBEDTLS_PADDING_NONE: + ctx->add_padding = NULL; + ctx->get_padding = get_no_padding; + break; + + default: + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + return 0; +} +#endif /* MBEDTLS_CIPHER_MODE_WITH_PADDING */ + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CHACHAPOLY_C) +int mbedtls_cipher_write_tag(mbedtls_cipher_context_t *ctx, + unsigned char *tag, size_t tag_len) +{ + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (MBEDTLS_ENCRYPT != ctx->operation) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + size_t output_length; + /* The code here doesn't yet support alternative implementations + * that can delay up to a block of output. */ + return mbedtls_gcm_finish((mbedtls_gcm_context *) ctx->cipher_ctx, + NULL, 0, &output_length, + tag, tag_len); + } +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { + /* Don't allow truncated MAC for Poly1305 */ + if (tag_len != 16U) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return mbedtls_chachapoly_finish( + (mbedtls_chachapoly_context *) ctx->cipher_ctx, tag); + } +#endif + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} + +int mbedtls_cipher_check_tag(mbedtls_cipher_context_t *ctx, + const unsigned char *tag, size_t tag_len) +{ + unsigned char check_tag[16]; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if (ctx->cipher_info == NULL) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (MBEDTLS_DECRYPT != ctx->operation) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* While PSA Crypto has an API for multipart + * operations, we currently don't make it + * accessible through the cipher layer. */ + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + /* Status to return on a non-authenticated algorithm. */ + ret = MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + size_t output_length; + /* The code here doesn't yet support alternative implementations + * that can delay up to a block of output. */ + + if (tag_len > sizeof(check_tag)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (0 != (ret = mbedtls_gcm_finish( + (mbedtls_gcm_context *) ctx->cipher_ctx, + NULL, 0, &output_length, + check_tag, tag_len))) { + return ret; + } + + /* Check the tag in "constant-time" */ + if (mbedtls_ct_memcmp(tag, check_tag, tag_len) != 0) { + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + goto exit; + } + } +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { + /* Don't allow truncated MAC for Poly1305 */ + if (tag_len != sizeof(check_tag)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + ret = mbedtls_chachapoly_finish( + (mbedtls_chachapoly_context *) ctx->cipher_ctx, check_tag); + if (ret != 0) { + return ret; + } + + /* Check the tag in "constant-time" */ + if (mbedtls_ct_memcmp(tag, check_tag, tag_len) != 0) { + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + goto exit; + } + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + +exit: + mbedtls_platform_zeroize(check_tag, tag_len); + return ret; +} +#endif /* MBEDTLS_GCM_C || MBEDTLS_CHACHAPOLY_C */ + +/* + * Packet-oriented wrapper for non-AEAD modes + */ +int mbedtls_cipher_crypt(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t finish_olen; + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* As in the non-PSA case, we don't check that + * a key has been set. If not, the key slot will + * still be in its default state of 0, which is + * guaranteed to be invalid, hence the PSA-call + * below will gracefully fail. */ + mbedtls_cipher_context_psa * const cipher_psa = + (mbedtls_cipher_context_psa *) ctx->cipher_ctx; + + psa_status_t status; + psa_cipher_operation_t cipher_op = PSA_CIPHER_OPERATION_INIT; + size_t part_len; + + if (ctx->operation == MBEDTLS_DECRYPT) { + status = psa_cipher_decrypt_setup(&cipher_op, + cipher_psa->slot, + cipher_psa->alg); + } else if (ctx->operation == MBEDTLS_ENCRYPT) { + status = psa_cipher_encrypt_setup(&cipher_op, + cipher_psa->slot, + cipher_psa->alg); + } else { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + /* In the following, we can immediately return on an error, + * because the PSA Crypto API guarantees that cipher operations + * are terminated by unsuccessful calls to psa_cipher_update(), + * and by any call to psa_cipher_finish(). */ + if (status == PSA_ERROR_NOT_SUPPORTED) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } else if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + if (((mbedtls_cipher_mode_t) ctx->cipher_info->mode) != MBEDTLS_MODE_ECB) { + status = psa_cipher_set_iv(&cipher_op, iv, iv_len); + if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + } + + status = psa_cipher_update(&cipher_op, + input, ilen, + output, ilen, olen); + if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + status = psa_cipher_finish(&cipher_op, + output + *olen, ilen - *olen, + &part_len); + if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + *olen += part_len; + return 0; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + + if ((ret = mbedtls_cipher_set_iv(ctx, iv, iv_len)) != 0) { + return ret; + } + + if ((ret = mbedtls_cipher_reset(ctx)) != 0) { + return ret; + } + + if ((ret = mbedtls_cipher_update(ctx, input, ilen, + output, olen)) != 0) { + return ret; + } + + if ((ret = mbedtls_cipher_finish(ctx, output + *olen, + &finish_olen)) != 0) { + return ret; + } + + *olen += finish_olen; + + return 0; +} + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) +/* + * Packet-oriented encryption for AEAD modes: internal function used by + * mbedtls_cipher_auth_encrypt_ext(). + */ +static int mbedtls_cipher_aead_encrypt(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + unsigned char *tag, size_t tag_len) +{ +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* As in the non-PSA case, we don't check that + * a key has been set. If not, the key slot will + * still be in its default state of 0, which is + * guaranteed to be invalid, hence the PSA-call + * below will gracefully fail. */ + mbedtls_cipher_context_psa * const cipher_psa = + (mbedtls_cipher_context_psa *) ctx->cipher_ctx; + + psa_status_t status; + + /* PSA Crypto API always writes the authentication tag + * at the end of the encrypted message. */ + if (output == NULL || tag != output + ilen) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + status = psa_aead_encrypt(cipher_psa->slot, + cipher_psa->alg, + iv, iv_len, + ad, ad_len, + input, ilen, + output, ilen + tag_len, olen); + if (status == PSA_ERROR_NOT_SUPPORTED) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } else if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + *olen -= tag_len; + return 0; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + *olen = ilen; + return mbedtls_gcm_crypt_and_tag(ctx->cipher_ctx, MBEDTLS_GCM_ENCRYPT, + ilen, iv, iv_len, ad, ad_len, + input, output, tag_len, tag); + } +#endif /* MBEDTLS_GCM_C */ +#if defined(MBEDTLS_CCM_C) + if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + *olen = ilen; + return mbedtls_ccm_encrypt_and_tag(ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, input, output, + tag, tag_len); + } +#endif /* MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { + /* ChachaPoly has fixed length nonce and MAC (tag) */ + if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || + (tag_len != 16U)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + *olen = ilen; + return mbedtls_chachapoly_encrypt_and_tag(ctx->cipher_ctx, + ilen, iv, ad, ad_len, input, output, tag); + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} + +/* + * Packet-oriented encryption for AEAD modes: internal function used by + * mbedtls_cipher_auth_encrypt_ext(). + */ +static int mbedtls_cipher_aead_decrypt(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + const unsigned char *tag, size_t tag_len) +{ +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ctx->psa_enabled == 1) { + /* As in the non-PSA case, we don't check that + * a key has been set. If not, the key slot will + * still be in its default state of 0, which is + * guaranteed to be invalid, hence the PSA-call + * below will gracefully fail. */ + mbedtls_cipher_context_psa * const cipher_psa = + (mbedtls_cipher_context_psa *) ctx->cipher_ctx; + + psa_status_t status; + + /* PSA Crypto API always writes the authentication tag + * at the end of the encrypted message. */ + if (input == NULL || tag != input + ilen) { + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; + } + + status = psa_aead_decrypt(cipher_psa->slot, + cipher_psa->alg, + iv, iv_len, + ad, ad_len, + input, ilen + tag_len, + output, ilen, olen); + if (status == PSA_ERROR_INVALID_SIGNATURE) { + return MBEDTLS_ERR_CIPHER_AUTH_FAILED; + } else if (status == PSA_ERROR_NOT_SUPPORTED) { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } else if (status != PSA_SUCCESS) { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return 0; + } +#endif /* MBEDTLS_USE_PSA_CRYPTO && !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_GCM_C) + if (MBEDTLS_MODE_GCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + *olen = ilen; + ret = mbedtls_gcm_auth_decrypt(ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, + tag, tag_len, input, output); + + if (ret == MBEDTLS_ERR_GCM_AUTH_FAILED) { + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + } + + return ret; + } +#endif /* MBEDTLS_GCM_C */ +#if defined(MBEDTLS_CCM_C) + if (MBEDTLS_MODE_CCM == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + *olen = ilen; + ret = mbedtls_ccm_auth_decrypt(ctx->cipher_ctx, ilen, + iv, iv_len, ad, ad_len, + input, output, tag, tag_len); + + if (ret == MBEDTLS_ERR_CCM_AUTH_FAILED) { + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + } + + return ret; + } +#endif /* MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + if (MBEDTLS_CIPHER_CHACHA20_POLY1305 == ((mbedtls_cipher_type_t) ctx->cipher_info->type)) { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* ChachaPoly has fixed length nonce and MAC (tag) */ + if ((iv_len != mbedtls_cipher_info_get_iv_size(ctx->cipher_info)) || + (tag_len != 16U)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + *olen = ilen; + ret = mbedtls_chachapoly_auth_decrypt(ctx->cipher_ctx, ilen, + iv, ad, ad_len, tag, input, output); + + if (ret == MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED) { + ret = MBEDTLS_ERR_CIPHER_AUTH_FAILED; + } + + return ret; + } +#endif /* MBEDTLS_CHACHAPOLY_C */ + + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +} +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) +/* + * Packet-oriented encryption for AEAD/NIST_KW: public function. + */ +int mbedtls_cipher_auth_encrypt_ext(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len) +{ +#if defined(MBEDTLS_NIST_KW_C) + if ( +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + ctx->psa_enabled == 0 && +#endif + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { + mbedtls_nist_kw_mode_t mode = + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? + MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; + + /* There is no iv, tag or ad associated with KW and KWP, + * so these length should be 0 as documented. */ + if (iv_len != 0 || tag_len != 0 || ad_len != 0) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + (void) iv; + (void) ad; + + return mbedtls_nist_kw_wrap(ctx->cipher_ctx, mode, input, ilen, + output, olen, output_len); + } +#endif /* MBEDTLS_NIST_KW_C */ + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) + /* AEAD case: check length before passing on to shared function */ + if (output_len < ilen + tag_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + int ret = mbedtls_cipher_aead_encrypt(ctx, iv, iv_len, ad, ad_len, + input, ilen, output, olen, + output + ilen, tag_len); + *olen += tag_len; + return ret; +#else + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ +} + +/* + * Packet-oriented decryption for AEAD/NIST_KW: public function. + */ +int mbedtls_cipher_auth_decrypt_ext(mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len) +{ +#if defined(MBEDTLS_NIST_KW_C) + if ( +#if defined(MBEDTLS_USE_PSA_CRYPTO) && !defined(MBEDTLS_DEPRECATED_REMOVED) + ctx->psa_enabled == 0 && +#endif + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode) || + MBEDTLS_MODE_KWP == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode))) { + mbedtls_nist_kw_mode_t mode = + (MBEDTLS_MODE_KW == ((mbedtls_cipher_mode_t) ctx->cipher_info->mode)) ? + MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; + + /* There is no iv, tag or ad associated with KW and KWP, + * so these length should be 0 as documented. */ + if (iv_len != 0 || tag_len != 0 || ad_len != 0) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + (void) iv; + (void) ad; + + return mbedtls_nist_kw_unwrap(ctx->cipher_ctx, mode, input, ilen, + output, olen, output_len); + } +#endif /* MBEDTLS_NIST_KW_C */ + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) + /* AEAD case: check length before passing on to shared function */ + if (ilen < tag_len || output_len < ilen - tag_len) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return mbedtls_cipher_aead_decrypt(ctx, iv, iv_len, ad, ad_len, + input, ilen - tag_len, output, olen, + input + ilen - tag_len, tag_len); +#else + return MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ +} +#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ + +#endif /* MBEDTLS_CIPHER_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.c index e71539a..067304d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.c @@ -1,2435 +1,2435 @@ -/** - * \file cipher_wrap.c - * - * \brief Generic cipher wrapper for Mbed TLS - * - * \author Adriaan de Jong - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_CIPHER_C) - -#include "cipher_wrap.h" -#include "mbedtls/error.h" - -#if defined(MBEDTLS_CHACHAPOLY_C) -#include "mbedtls/chachapoly.h" -#endif - -#if defined(MBEDTLS_AES_C) -#include "mbedtls/aes.h" -#endif - -#if defined(MBEDTLS_CAMELLIA_C) -#include "mbedtls/camellia.h" -#endif - -#if defined(MBEDTLS_ARIA_C) -#include "mbedtls/aria.h" -#endif - -#if defined(MBEDTLS_DES_C) -#include "mbedtls/des.h" -#endif - -#if defined(MBEDTLS_CHACHA20_C) -#include "mbedtls/chacha20.h" -#endif - -#if defined(MBEDTLS_GCM_C) -#include "mbedtls/gcm.h" -#endif - -#if defined(MBEDTLS_CCM_C) -#include "mbedtls/ccm.h" -#endif - -#if defined(MBEDTLS_NIST_KW_C) -#include "mbedtls/nist_kw.h" -#endif - -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) -#include -#endif - -#include "mbedtls/platform.h" - -enum mbedtls_cipher_base_index { -#if defined(MBEDTLS_AES_C) - MBEDTLS_CIPHER_BASE_INDEX_AES, -#endif -#if defined(MBEDTLS_ARIA_C) - MBEDTLS_CIPHER_BASE_INDEX_ARIA, -#endif -#if defined(MBEDTLS_CAMELLIA_C) - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_AES_C) - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_ARIA_C) - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CAMELLIA_C) - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA, -#endif -#if defined(MBEDTLS_CHACHA20_C) - MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE, -#endif -#if defined(MBEDTLS_CHACHAPOLY_C) - MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE, -#endif -#if defined(MBEDTLS_DES_C) - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3, -#endif -#if defined(MBEDTLS_DES_C) - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE, -#endif -#if defined(MBEDTLS_DES_C) - MBEDTLS_CIPHER_BASE_INDEX_DES, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_AES_C) - MBEDTLS_CIPHER_BASE_INDEX_GCM_AES, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_ARIA_C) - MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_CAMELLIA_C) - MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA, -#endif -#if defined(MBEDTLS_NIST_KW_C) - MBEDTLS_CIPHER_BASE_INDEX_KW_AES, -#endif -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) - MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) && defined(MBEDTLS_AES_C) - MBEDTLS_CIPHER_BASE_INDEX_XTS_AES, -#endif - /* Prevent compile failure due to empty enum */ - MBEDTLS_CIPHER_BASE_PREVENT_EMPTY_ENUM -}; - -#if defined(MBEDTLS_GCM_C) -/* shared by all GCM ciphers */ -static void *gcm_ctx_alloc(void) -{ - void *ctx = mbedtls_calloc(1, sizeof(mbedtls_gcm_context)); - - if (ctx != NULL) { - mbedtls_gcm_init((mbedtls_gcm_context *) ctx); - } - - return ctx; -} - -static void gcm_ctx_free(void *ctx) -{ - mbedtls_gcm_free(ctx); - mbedtls_free(ctx); -} -#endif /* MBEDTLS_GCM_C */ - -#if defined(MBEDTLS_CCM_C) -/* shared by all CCM ciphers */ -static void *ccm_ctx_alloc(void) -{ - void *ctx = mbedtls_calloc(1, sizeof(mbedtls_ccm_context)); - - if (ctx != NULL) { - mbedtls_ccm_init((mbedtls_ccm_context *) ctx); - } - - return ctx; -} - -static void ccm_ctx_free(void *ctx) -{ - mbedtls_ccm_free(ctx); - mbedtls_free(ctx); -} -#endif /* MBEDTLS_CCM_C */ - -#if defined(MBEDTLS_AES_C) - -static int aes_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aes_crypt_ecb((mbedtls_aes_context *) ctx, operation, input, output); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static int aes_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, - unsigned char *iv, const unsigned char *input, unsigned char *output) -{ - return mbedtls_aes_crypt_cbc((mbedtls_aes_context *) ctx, operation, length, iv, input, - output); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static int aes_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, size_t *iv_off, unsigned char *iv, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aes_crypt_cfb128((mbedtls_aes_context *) ctx, operation, length, iv_off, iv, - input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_OFB) -static int aes_crypt_ofb_wrap(void *ctx, size_t length, size_t *iv_off, - unsigned char *iv, const unsigned char *input, unsigned char *output) -{ - return mbedtls_aes_crypt_ofb((mbedtls_aes_context *) ctx, length, iv_off, - iv, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_OFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static int aes_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, - unsigned char *nonce_counter, unsigned char *stream_block, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aes_crypt_ctr((mbedtls_aes_context *) ctx, length, nc_off, nonce_counter, - stream_block, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -static int aes_crypt_xts_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, - const unsigned char data_unit[16], - const unsigned char *input, - unsigned char *output) -{ - mbedtls_aes_xts_context *xts_ctx = ctx; - int mode; - - switch (operation) { - case MBEDTLS_ENCRYPT: - mode = MBEDTLS_AES_ENCRYPT; - break; - case MBEDTLS_DECRYPT: - mode = MBEDTLS_AES_DECRYPT; - break; - default: - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return mbedtls_aes_crypt_xts(xts_ctx, mode, length, - data_unit, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -static int aes_setkey_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_aes_setkey_dec((mbedtls_aes_context *) ctx, key, key_bitlen); -} - -static int aes_setkey_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_aes_setkey_enc((mbedtls_aes_context *) ctx, key, key_bitlen); -} - -static void *aes_ctx_alloc(void) -{ - mbedtls_aes_context *aes = mbedtls_calloc(1, sizeof(mbedtls_aes_context)); - - if (aes == NULL) { - return NULL; - } - - mbedtls_aes_init(aes); - - return aes; -} - -static void aes_ctx_free(void *ctx) -{ - mbedtls_aes_free((mbedtls_aes_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t aes_info = { - MBEDTLS_CIPHER_ID_AES, - aes_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - aes_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - aes_crypt_cfb128_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - aes_crypt_ofb_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - aes_crypt_ctr_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - aes_setkey_enc_wrap, - aes_setkey_dec_wrap, - aes_ctx_alloc, - aes_ctx_free -}; - -static const mbedtls_cipher_info_t aes_128_ecb_info = { - "AES-128-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_AES_128_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_ecb_info = { - "AES-192-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_AES_192_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -static const mbedtls_cipher_info_t aes_256_ecb_info = { - "AES-256-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_AES_256_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t aes_128_cbc_info = { - "AES-128-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_AES_128_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_cbc_info = { - "AES-192-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_AES_192_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -static const mbedtls_cipher_info_t aes_256_cbc_info = { - "AES-256-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_AES_256_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; -#endif -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static const mbedtls_cipher_info_t aes_128_cfb128_info = { - "AES-128-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_AES_128_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_cfb128_info = { - "AES-192-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_AES_192_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -static const mbedtls_cipher_info_t aes_256_cfb128_info = { - "AES-256-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_AES_256_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; -#endif -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_OFB) -static const mbedtls_cipher_info_t aes_128_ofb_info = { - "AES-128-OFB", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_OFB, - MBEDTLS_CIPHER_AES_128_OFB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_ofb_info = { - "AES-192-OFB", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_OFB, - MBEDTLS_CIPHER_AES_192_OFB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -static const mbedtls_cipher_info_t aes_256_ofb_info = { - "AES-256-OFB", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_OFB, - MBEDTLS_CIPHER_AES_256_OFB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; -#endif -#endif /* MBEDTLS_CIPHER_MODE_OFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static const mbedtls_cipher_info_t aes_128_ctr_info = { - "AES-128-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_AES_128_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_ctr_info = { - "AES-192-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_AES_192_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; - -static const mbedtls_cipher_info_t aes_256_ctr_info = { - "AES-256-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_AES_256_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_AES -}; -#endif -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_CIPHER_MODE_XTS) -static int xts_aes_setkey_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - mbedtls_aes_xts_context *xts_ctx = ctx; - return mbedtls_aes_xts_setkey_enc(xts_ctx, key, key_bitlen); -} - -static int xts_aes_setkey_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - mbedtls_aes_xts_context *xts_ctx = ctx; - return mbedtls_aes_xts_setkey_dec(xts_ctx, key, key_bitlen); -} - -static void *xts_aes_ctx_alloc(void) -{ - mbedtls_aes_xts_context *xts_ctx = mbedtls_calloc(1, sizeof(*xts_ctx)); - - if (xts_ctx != NULL) { - mbedtls_aes_xts_init(xts_ctx); - } - - return xts_ctx; -} - -static void xts_aes_ctx_free(void *ctx) -{ - mbedtls_aes_xts_context *xts_ctx = ctx; - - if (xts_ctx == NULL) { - return; - } - - mbedtls_aes_xts_free(xts_ctx); - mbedtls_free(xts_ctx); -} - -static const mbedtls_cipher_base_t xts_aes_info = { - MBEDTLS_CIPHER_ID_AES, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - aes_crypt_xts_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - xts_aes_setkey_enc_wrap, - xts_aes_setkey_dec_wrap, - xts_aes_ctx_alloc, - xts_aes_ctx_free -}; - -static const mbedtls_cipher_info_t aes_128_xts_info = { - "AES-128-XTS", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_XTS, - MBEDTLS_CIPHER_AES_128_XTS, - 0, - MBEDTLS_CIPHER_BASE_INDEX_XTS_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_256_xts_info = { - "AES-256-XTS", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 512 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_XTS, - MBEDTLS_CIPHER_AES_256_XTS, - 0, - MBEDTLS_CIPHER_BASE_INDEX_XTS_AES -}; -#endif -#endif /* MBEDTLS_CIPHER_MODE_XTS */ - -#if defined(MBEDTLS_GCM_C) -static int gcm_aes_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_AES, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t gcm_aes_info = { - MBEDTLS_CIPHER_ID_AES, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - gcm_aes_setkey_wrap, - gcm_aes_setkey_wrap, - gcm_ctx_alloc, - gcm_ctx_free, -}; - -static const mbedtls_cipher_info_t aes_128_gcm_info = { - "AES-128-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_AES_128_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_gcm_info = { - "AES-192-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_AES_192_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_AES -}; - -static const mbedtls_cipher_info_t aes_256_gcm_info = { - "AES-256-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_AES_256_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_AES -}; -#endif -#endif /* MBEDTLS_GCM_C */ - -#if defined(MBEDTLS_CCM_C) -static int ccm_aes_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_AES, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t ccm_aes_info = { - MBEDTLS_CIPHER_ID_AES, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - ccm_aes_setkey_wrap, - ccm_aes_setkey_wrap, - ccm_ctx_alloc, - ccm_ctx_free, -}; - -static const mbedtls_cipher_info_t aes_128_ccm_info = { - "AES-128-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_AES_128_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_ccm_info = { - "AES-192-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_AES_192_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; - -static const mbedtls_cipher_info_t aes_256_ccm_info = { - "AES-256-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_AES_256_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; -#endif - -static const mbedtls_cipher_info_t aes_128_ccm_star_no_tag_info = { - "AES-128-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_ccm_star_no_tag_info = { - "AES-192-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; - -static const mbedtls_cipher_info_t aes_256_ccm_star_no_tag_info = { - "AES-256-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_AES -}; -#endif -#endif /* MBEDTLS_CCM_C */ - -#endif /* MBEDTLS_AES_C */ - -#if defined(MBEDTLS_CAMELLIA_C) - -static int camellia_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_camellia_crypt_ecb((mbedtls_camellia_context *) ctx, operation, input, - output); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static int camellia_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, unsigned char *iv, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_camellia_crypt_cbc((mbedtls_camellia_context *) ctx, operation, length, iv, - input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static int camellia_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, size_t *iv_off, unsigned char *iv, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_camellia_crypt_cfb128((mbedtls_camellia_context *) ctx, operation, length, - iv_off, iv, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static int camellia_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, - unsigned char *nonce_counter, unsigned char *stream_block, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_camellia_crypt_ctr((mbedtls_camellia_context *) ctx, length, nc_off, - nonce_counter, stream_block, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -static int camellia_setkey_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_camellia_setkey_dec((mbedtls_camellia_context *) ctx, key, key_bitlen); -} - -static int camellia_setkey_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_camellia_setkey_enc((mbedtls_camellia_context *) ctx, key, key_bitlen); -} - -static void *camellia_ctx_alloc(void) -{ - mbedtls_camellia_context *ctx; - ctx = mbedtls_calloc(1, sizeof(mbedtls_camellia_context)); - - if (ctx == NULL) { - return NULL; - } - - mbedtls_camellia_init(ctx); - - return ctx; -} - -static void camellia_ctx_free(void *ctx) -{ - mbedtls_camellia_free((mbedtls_camellia_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t camellia_info = { - MBEDTLS_CIPHER_ID_CAMELLIA, - camellia_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - camellia_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - camellia_crypt_cfb128_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - camellia_crypt_ctr_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - camellia_setkey_enc_wrap, - camellia_setkey_dec_wrap, - camellia_ctx_alloc, - camellia_ctx_free -}; - -static const mbedtls_cipher_info_t camellia_128_ecb_info = { - "CAMELLIA-128-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_CAMELLIA_128_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_ecb_info = { - "CAMELLIA-192-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_CAMELLIA_192_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_ecb_info = { - "CAMELLIA-256-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_CAMELLIA_256_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t camellia_128_cbc_info = { - "CAMELLIA-128-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_CAMELLIA_128_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_cbc_info = { - "CAMELLIA-192-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_CAMELLIA_192_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_cbc_info = { - "CAMELLIA-256-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_CAMELLIA_256_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static const mbedtls_cipher_info_t camellia_128_cfb128_info = { - "CAMELLIA-128-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_CAMELLIA_128_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_cfb128_info = { - "CAMELLIA-192-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_CAMELLIA_192_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_cfb128_info = { - "CAMELLIA-256-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_CAMELLIA_256_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static const mbedtls_cipher_info_t camellia_128_ctr_info = { - "CAMELLIA-128-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_CAMELLIA_128_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_ctr_info = { - "CAMELLIA-192-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_CAMELLIA_192_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_ctr_info = { - "CAMELLIA-256-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_CAMELLIA_256_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_GCM_C) -static int gcm_camellia_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t gcm_camellia_info = { - MBEDTLS_CIPHER_ID_CAMELLIA, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - gcm_camellia_setkey_wrap, - gcm_camellia_setkey_wrap, - gcm_ctx_alloc, - gcm_ctx_free, -}; - -static const mbedtls_cipher_info_t camellia_128_gcm_info = { - "CAMELLIA-128-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_CAMELLIA_128_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_gcm_info = { - "CAMELLIA-192-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_CAMELLIA_192_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_gcm_info = { - "CAMELLIA-256-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_CAMELLIA_256_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA -}; -#endif /* MBEDTLS_GCM_C */ - -#if defined(MBEDTLS_CCM_C) -static int ccm_camellia_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t ccm_camellia_info = { - MBEDTLS_CIPHER_ID_CAMELLIA, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - ccm_camellia_setkey_wrap, - ccm_camellia_setkey_wrap, - ccm_ctx_alloc, - ccm_ctx_free, -}; - -static const mbedtls_cipher_info_t camellia_128_ccm_info = { - "CAMELLIA-128-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_CAMELLIA_128_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_ccm_info = { - "CAMELLIA-192-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_CAMELLIA_192_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_ccm_info = { - "CAMELLIA-256-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_CAMELLIA_256_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_128_ccm_star_no_tag_info = { - "CAMELLIA-128-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_192_ccm_star_no_tag_info = { - "CAMELLIA-192-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; - -static const mbedtls_cipher_info_t camellia_256_ccm_star_no_tag_info = { - "CAMELLIA-256-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA -}; -#endif /* MBEDTLS_CCM_C */ - -#endif /* MBEDTLS_CAMELLIA_C */ - -#if defined(MBEDTLS_ARIA_C) - -static int aria_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, - const unsigned char *input, unsigned char *output) -{ - (void) operation; - return mbedtls_aria_crypt_ecb((mbedtls_aria_context *) ctx, input, - output); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static int aria_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, unsigned char *iv, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aria_crypt_cbc((mbedtls_aria_context *) ctx, operation, length, iv, - input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static int aria_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, - size_t length, size_t *iv_off, unsigned char *iv, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aria_crypt_cfb128((mbedtls_aria_context *) ctx, operation, length, - iv_off, iv, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static int aria_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, - unsigned char *nonce_counter, unsigned char *stream_block, - const unsigned char *input, unsigned char *output) -{ - return mbedtls_aria_crypt_ctr((mbedtls_aria_context *) ctx, length, nc_off, - nonce_counter, stream_block, input, output); -} -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -static int aria_setkey_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_aria_setkey_dec((mbedtls_aria_context *) ctx, key, key_bitlen); -} - -static int aria_setkey_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_aria_setkey_enc((mbedtls_aria_context *) ctx, key, key_bitlen); -} - -static void *aria_ctx_alloc(void) -{ - mbedtls_aria_context *ctx; - ctx = mbedtls_calloc(1, sizeof(mbedtls_aria_context)); - - if (ctx == NULL) { - return NULL; - } - - mbedtls_aria_init(ctx); - - return ctx; -} - -static void aria_ctx_free(void *ctx) -{ - mbedtls_aria_free((mbedtls_aria_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t aria_info = { - MBEDTLS_CIPHER_ID_ARIA, - aria_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - aria_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - aria_crypt_cfb128_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - aria_crypt_ctr_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - aria_setkey_enc_wrap, - aria_setkey_dec_wrap, - aria_ctx_alloc, - aria_ctx_free -}; - -static const mbedtls_cipher_info_t aria_128_ecb_info = { - "ARIA-128-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_ARIA_128_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_ecb_info = { - "ARIA-192-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_ARIA_192_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_ecb_info = { - "ARIA-256-ECB", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_ARIA_256_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t aria_128_cbc_info = { - "ARIA-128-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_ARIA_128_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_cbc_info = { - "ARIA-192-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_ARIA_192_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_cbc_info = { - "ARIA-256-CBC", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_ARIA_256_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CFB) -static const mbedtls_cipher_info_t aria_128_cfb128_info = { - "ARIA-128-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_ARIA_128_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_cfb128_info = { - "ARIA-192-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_ARIA_192_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_cfb128_info = { - "ARIA-256-CFB128", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CFB, - MBEDTLS_CIPHER_ARIA_256_CFB128, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CFB */ - -#if defined(MBEDTLS_CIPHER_MODE_CTR) -static const mbedtls_cipher_info_t aria_128_ctr_info = { - "ARIA-128-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_ARIA_128_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_ctr_info = { - "ARIA-192-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_ARIA_192_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_ctr_info = { - "ARIA-256-CTR", - 16, - 16 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CTR, - MBEDTLS_CIPHER_ARIA_256_CTR, - 0, - MBEDTLS_CIPHER_BASE_INDEX_ARIA -}; -#endif /* MBEDTLS_CIPHER_MODE_CTR */ - -#if defined(MBEDTLS_GCM_C) -static int gcm_aria_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t gcm_aria_info = { - MBEDTLS_CIPHER_ID_ARIA, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - gcm_aria_setkey_wrap, - gcm_aria_setkey_wrap, - gcm_ctx_alloc, - gcm_ctx_free, -}; - -static const mbedtls_cipher_info_t aria_128_gcm_info = { - "ARIA-128-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_ARIA_128_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_gcm_info = { - "ARIA-192-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_ARIA_192_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_gcm_info = { - "ARIA-256-GCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_GCM, - MBEDTLS_CIPHER_ARIA_256_GCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA -}; -#endif /* MBEDTLS_GCM_C */ - -#if defined(MBEDTLS_CCM_C) -static int ccm_aria_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, - key, key_bitlen); -} - -static const mbedtls_cipher_base_t ccm_aria_info = { - MBEDTLS_CIPHER_ID_ARIA, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - ccm_aria_setkey_wrap, - ccm_aria_setkey_wrap, - ccm_ctx_alloc, - ccm_ctx_free, -}; - -static const mbedtls_cipher_info_t aria_128_ccm_info = { - "ARIA-128-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_ARIA_128_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_ccm_info = { - "ARIA-192-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_ARIA_192_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_ccm_info = { - "ARIA-256-CCM", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM, - MBEDTLS_CIPHER_ARIA_256_CCM, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_128_ccm_star_no_tag_info = { - "ARIA-128-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_192_ccm_star_no_tag_info = { - "ARIA-192-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; - -static const mbedtls_cipher_info_t aria_256_ccm_star_no_tag_info = { - "ARIA-256-CCM*-NO-TAG", - 16, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, - MBEDTLS_CIPHER_VARIABLE_IV_LEN, - MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA -}; -#endif /* MBEDTLS_CCM_C */ - -#endif /* MBEDTLS_ARIA_C */ - -#if defined(MBEDTLS_DES_C) - -static int des_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, - const unsigned char *input, unsigned char *output) -{ - ((void) operation); - return mbedtls_des_crypt_ecb((mbedtls_des_context *) ctx, input, output); -} - -static int des3_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, - const unsigned char *input, unsigned char *output) -{ - ((void) operation); - return mbedtls_des3_crypt_ecb((mbedtls_des3_context *) ctx, input, output); -} - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static int des_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, - unsigned char *iv, const unsigned char *input, unsigned char *output) -{ - return mbedtls_des_crypt_cbc((mbedtls_des_context *) ctx, operation, length, iv, input, - output); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static int des3_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, - unsigned char *iv, const unsigned char *input, unsigned char *output) -{ - return mbedtls_des3_crypt_cbc((mbedtls_des3_context *) ctx, operation, length, iv, input, - output); -} -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -static int des_setkey_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des_setkey_dec((mbedtls_des_context *) ctx, key); -} - -static int des_setkey_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des_setkey_enc((mbedtls_des_context *) ctx, key); -} - -static int des3_set2key_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des3_set2key_dec((mbedtls_des3_context *) ctx, key); -} - -static int des3_set2key_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des3_set2key_enc((mbedtls_des3_context *) ctx, key); -} - -static int des3_set3key_dec_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des3_set3key_dec((mbedtls_des3_context *) ctx, key); -} - -static int des3_set3key_enc_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) key_bitlen); - - return mbedtls_des3_set3key_enc((mbedtls_des3_context *) ctx, key); -} - -static void *des_ctx_alloc(void) -{ - mbedtls_des_context *des = mbedtls_calloc(1, sizeof(mbedtls_des_context)); - - if (des == NULL) { - return NULL; - } - - mbedtls_des_init(des); - - return des; -} - -static void des_ctx_free(void *ctx) -{ - mbedtls_des_free((mbedtls_des_context *) ctx); - mbedtls_free(ctx); -} - -static void *des3_ctx_alloc(void) -{ - mbedtls_des3_context *des3; - des3 = mbedtls_calloc(1, sizeof(mbedtls_des3_context)); - - if (des3 == NULL) { - return NULL; - } - - mbedtls_des3_init(des3); - - return des3; -} - -static void des3_ctx_free(void *ctx) -{ - mbedtls_des3_free((mbedtls_des3_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t des_info = { - MBEDTLS_CIPHER_ID_DES, - des_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - des_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - des_setkey_enc_wrap, - des_setkey_dec_wrap, - des_ctx_alloc, - des_ctx_free -}; - -static const mbedtls_cipher_info_t des_ecb_info = { - "DES-ECB", - 8, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_DES_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES -}; - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t des_cbc_info = { - "DES-CBC", - 8, - 8 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_DES_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES -}; -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -static const mbedtls_cipher_base_t des_ede_info = { - MBEDTLS_CIPHER_ID_DES, - des3_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - des3_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - des3_set2key_enc_wrap, - des3_set2key_dec_wrap, - des3_ctx_alloc, - des3_ctx_free -}; - -static const mbedtls_cipher_info_t des_ede_ecb_info = { - "DES-EDE-ECB", - 8, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES_EDE >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_DES_EDE_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE -}; - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t des_ede_cbc_info = { - "DES-EDE-CBC", - 8, - 8 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES_EDE >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_DES_EDE_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE -}; -#endif /* MBEDTLS_CIPHER_MODE_CBC */ - -static const mbedtls_cipher_base_t des_ede3_info = { - MBEDTLS_CIPHER_ID_3DES, - des3_crypt_ecb_wrap, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - des3_crypt_cbc_wrap, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - des3_set3key_enc_wrap, - des3_set3key_dec_wrap, - des3_ctx_alloc, - des3_ctx_free -}; - -static const mbedtls_cipher_info_t des_ede3_ecb_info = { - "DES-EDE3-ECB", - 8, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES_EDE3 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_ECB, - MBEDTLS_CIPHER_DES_EDE3_ECB, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3 -}; -#if defined(MBEDTLS_CIPHER_MODE_CBC) -static const mbedtls_cipher_info_t des_ede3_cbc_info = { - "DES-EDE3-CBC", - 8, - 8 >> MBEDTLS_IV_SIZE_SHIFT, - MBEDTLS_KEY_LENGTH_DES_EDE3 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CBC, - MBEDTLS_CIPHER_DES_EDE3_CBC, - 0, - MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3 -}; -#endif /* MBEDTLS_CIPHER_MODE_CBC */ -#endif /* MBEDTLS_DES_C */ - -#if defined(MBEDTLS_CHACHA20_C) - -static int chacha20_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - if (key_bitlen != 256U) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (0 != mbedtls_chacha20_setkey((mbedtls_chacha20_context *) ctx, key)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return 0; -} - -static int chacha20_stream_wrap(void *ctx, size_t length, - const unsigned char *input, - unsigned char *output) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - ret = mbedtls_chacha20_update(ctx, length, input, output); - if (ret == MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return ret; -} - -static void *chacha20_ctx_alloc(void) -{ - mbedtls_chacha20_context *ctx; - ctx = mbedtls_calloc(1, sizeof(mbedtls_chacha20_context)); - - if (ctx == NULL) { - return NULL; - } - - mbedtls_chacha20_init(ctx); - - return ctx; -} - -static void chacha20_ctx_free(void *ctx) -{ - mbedtls_chacha20_free((mbedtls_chacha20_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t chacha20_base_info = { - MBEDTLS_CIPHER_ID_CHACHA20, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - chacha20_stream_wrap, -#endif - chacha20_setkey_wrap, - chacha20_setkey_wrap, - chacha20_ctx_alloc, - chacha20_ctx_free -}; -static const mbedtls_cipher_info_t chacha20_info = { - "CHACHA20", - 1, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_STREAM, - MBEDTLS_CIPHER_CHACHA20, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE -}; -#endif /* MBEDTLS_CHACHA20_C */ - -#if defined(MBEDTLS_CHACHAPOLY_C) - -static int chachapoly_setkey_wrap(void *ctx, - const unsigned char *key, - unsigned int key_bitlen) -{ - if (key_bitlen != 256U) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - if (0 != mbedtls_chachapoly_setkey((mbedtls_chachapoly_context *) ctx, key)) { - return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; - } - - return 0; -} - -static void *chachapoly_ctx_alloc(void) -{ - mbedtls_chachapoly_context *ctx; - ctx = mbedtls_calloc(1, sizeof(mbedtls_chachapoly_context)); - - if (ctx == NULL) { - return NULL; - } - - mbedtls_chachapoly_init(ctx); - - return ctx; -} - -static void chachapoly_ctx_free(void *ctx) -{ - mbedtls_chachapoly_free((mbedtls_chachapoly_context *) ctx); - mbedtls_free(ctx); -} - -static const mbedtls_cipher_base_t chachapoly_base_info = { - MBEDTLS_CIPHER_ID_CHACHA20, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - chachapoly_setkey_wrap, - chachapoly_setkey_wrap, - chachapoly_ctx_alloc, - chachapoly_ctx_free -}; -static const mbedtls_cipher_info_t chachapoly_info = { - "CHACHA20-POLY1305", - 1, - 12 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_CHACHAPOLY, - MBEDTLS_CIPHER_CHACHA20_POLY1305, - 0, - MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE -}; -#endif /* MBEDTLS_CHACHAPOLY_C */ - -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) -static int null_crypt_stream(void *ctx, size_t length, - const unsigned char *input, - unsigned char *output) -{ - ((void) ctx); - memmove(output, input, length); - return 0; -} - -static int null_setkey(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - ((void) ctx); - ((void) key); - ((void) key_bitlen); - - return 0; -} - -static void *null_ctx_alloc(void) -{ - return (void *) 1; -} - -static void null_ctx_free(void *ctx) -{ - ((void) ctx); -} - -static const mbedtls_cipher_base_t null_base_info = { - MBEDTLS_CIPHER_ID_NULL, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - null_crypt_stream, -#endif - null_setkey, - null_setkey, - null_ctx_alloc, - null_ctx_free -}; - -static const mbedtls_cipher_info_t null_cipher_info = { - "NULL", - 1, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 0 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_STREAM, - MBEDTLS_CIPHER_NULL, - 0, - MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE -}; -#endif /* defined(MBEDTLS_CIPHER_NULL_CIPHER) */ - -#if defined(MBEDTLS_NIST_KW_C) -static void *kw_ctx_alloc(void) -{ - void *ctx = mbedtls_calloc(1, sizeof(mbedtls_nist_kw_context)); - - if (ctx != NULL) { - mbedtls_nist_kw_init((mbedtls_nist_kw_context *) ctx); - } - - return ctx; -} - -static void kw_ctx_free(void *ctx) -{ - mbedtls_nist_kw_free(ctx); - mbedtls_free(ctx); -} - -static int kw_aes_setkey_wrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_nist_kw_setkey((mbedtls_nist_kw_context *) ctx, - MBEDTLS_CIPHER_ID_AES, key, key_bitlen, 1); -} - -static int kw_aes_setkey_unwrap(void *ctx, const unsigned char *key, - unsigned int key_bitlen) -{ - return mbedtls_nist_kw_setkey((mbedtls_nist_kw_context *) ctx, - MBEDTLS_CIPHER_ID_AES, key, key_bitlen, 0); -} - -static const mbedtls_cipher_base_t kw_aes_info = { - MBEDTLS_CIPHER_ID_AES, - NULL, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - NULL, -#endif -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - NULL, -#endif - kw_aes_setkey_wrap, - kw_aes_setkey_unwrap, - kw_ctx_alloc, - kw_ctx_free, -}; - -static const mbedtls_cipher_info_t aes_128_nist_kw_info = { - "AES-128-KW", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KW, - MBEDTLS_CIPHER_AES_128_KW, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_nist_kw_info = { - "AES-192-KW", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KW, - MBEDTLS_CIPHER_AES_192_KW, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; - -static const mbedtls_cipher_info_t aes_256_nist_kw_info = { - "AES-256-KW", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KW, - MBEDTLS_CIPHER_AES_256_KW, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; -#endif - -static const mbedtls_cipher_info_t aes_128_nist_kwp_info = { - "AES-128-KWP", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 128 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KWP, - MBEDTLS_CIPHER_AES_128_KWP, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; - -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) -static const mbedtls_cipher_info_t aes_192_nist_kwp_info = { - "AES-192-KWP", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 192 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KWP, - MBEDTLS_CIPHER_AES_192_KWP, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; - -static const mbedtls_cipher_info_t aes_256_nist_kwp_info = { - "AES-256-KWP", - 16, - 0 >> MBEDTLS_IV_SIZE_SHIFT, - 256 >> MBEDTLS_KEY_BITLEN_SHIFT, - MBEDTLS_MODE_KWP, - MBEDTLS_CIPHER_AES_256_KWP, - 0, - MBEDTLS_CIPHER_BASE_INDEX_KW_AES -}; -#endif -#endif /* MBEDTLS_NIST_KW_C */ - -const mbedtls_cipher_definition_t mbedtls_cipher_definitions[] = -{ -#if defined(MBEDTLS_AES_C) - { MBEDTLS_CIPHER_AES_128_ECB, &aes_128_ecb_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_ECB, &aes_192_ecb_info }, - { MBEDTLS_CIPHER_AES_256_ECB, &aes_256_ecb_info }, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CBC) - { MBEDTLS_CIPHER_AES_128_CBC, &aes_128_cbc_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_CBC, &aes_192_cbc_info }, - { MBEDTLS_CIPHER_AES_256_CBC, &aes_256_cbc_info }, -#endif -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - { MBEDTLS_CIPHER_AES_128_CFB128, &aes_128_cfb128_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_CFB128, &aes_192_cfb128_info }, - { MBEDTLS_CIPHER_AES_256_CFB128, &aes_256_cfb128_info }, -#endif -#endif -#if defined(MBEDTLS_CIPHER_MODE_OFB) - { MBEDTLS_CIPHER_AES_128_OFB, &aes_128_ofb_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_OFB, &aes_192_ofb_info }, - { MBEDTLS_CIPHER_AES_256_OFB, &aes_256_ofb_info }, -#endif -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - { MBEDTLS_CIPHER_AES_128_CTR, &aes_128_ctr_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_CTR, &aes_192_ctr_info }, - { MBEDTLS_CIPHER_AES_256_CTR, &aes_256_ctr_info }, -#endif -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) - { MBEDTLS_CIPHER_AES_128_XTS, &aes_128_xts_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_256_XTS, &aes_256_xts_info }, -#endif -#endif -#if defined(MBEDTLS_GCM_C) - { MBEDTLS_CIPHER_AES_128_GCM, &aes_128_gcm_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_GCM, &aes_192_gcm_info }, - { MBEDTLS_CIPHER_AES_256_GCM, &aes_256_gcm_info }, -#endif -#endif -#if defined(MBEDTLS_CCM_C) - { MBEDTLS_CIPHER_AES_128_CCM, &aes_128_ccm_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_CCM, &aes_192_ccm_info }, - { MBEDTLS_CIPHER_AES_256_CCM, &aes_256_ccm_info }, -#endif - { MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, &aes_128_ccm_star_no_tag_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, &aes_192_ccm_star_no_tag_info }, - { MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, &aes_256_ccm_star_no_tag_info }, -#endif -#endif -#endif /* MBEDTLS_AES_C */ - -#if defined(MBEDTLS_CAMELLIA_C) - { MBEDTLS_CIPHER_CAMELLIA_128_ECB, &camellia_128_ecb_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_ECB, &camellia_192_ecb_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_ECB, &camellia_256_ecb_info }, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - { MBEDTLS_CIPHER_CAMELLIA_128_CBC, &camellia_128_cbc_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_CBC, &camellia_192_cbc_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_CBC, &camellia_256_cbc_info }, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - { MBEDTLS_CIPHER_CAMELLIA_128_CFB128, &camellia_128_cfb128_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_CFB128, &camellia_192_cfb128_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_CFB128, &camellia_256_cfb128_info }, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - { MBEDTLS_CIPHER_CAMELLIA_128_CTR, &camellia_128_ctr_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_CTR, &camellia_192_ctr_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_CTR, &camellia_256_ctr_info }, -#endif -#if defined(MBEDTLS_GCM_C) - { MBEDTLS_CIPHER_CAMELLIA_128_GCM, &camellia_128_gcm_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_GCM, &camellia_192_gcm_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_GCM, &camellia_256_gcm_info }, -#endif -#if defined(MBEDTLS_CCM_C) - { MBEDTLS_CIPHER_CAMELLIA_128_CCM, &camellia_128_ccm_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_CCM, &camellia_192_ccm_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_CCM, &camellia_256_ccm_info }, - { MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, &camellia_128_ccm_star_no_tag_info }, - { MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, &camellia_192_ccm_star_no_tag_info }, - { MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, &camellia_256_ccm_star_no_tag_info }, -#endif -#endif /* MBEDTLS_CAMELLIA_C */ - -#if defined(MBEDTLS_ARIA_C) - { MBEDTLS_CIPHER_ARIA_128_ECB, &aria_128_ecb_info }, - { MBEDTLS_CIPHER_ARIA_192_ECB, &aria_192_ecb_info }, - { MBEDTLS_CIPHER_ARIA_256_ECB, &aria_256_ecb_info }, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - { MBEDTLS_CIPHER_ARIA_128_CBC, &aria_128_cbc_info }, - { MBEDTLS_CIPHER_ARIA_192_CBC, &aria_192_cbc_info }, - { MBEDTLS_CIPHER_ARIA_256_CBC, &aria_256_cbc_info }, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CFB) - { MBEDTLS_CIPHER_ARIA_128_CFB128, &aria_128_cfb128_info }, - { MBEDTLS_CIPHER_ARIA_192_CFB128, &aria_192_cfb128_info }, - { MBEDTLS_CIPHER_ARIA_256_CFB128, &aria_256_cfb128_info }, -#endif -#if defined(MBEDTLS_CIPHER_MODE_CTR) - { MBEDTLS_CIPHER_ARIA_128_CTR, &aria_128_ctr_info }, - { MBEDTLS_CIPHER_ARIA_192_CTR, &aria_192_ctr_info }, - { MBEDTLS_CIPHER_ARIA_256_CTR, &aria_256_ctr_info }, -#endif -#if defined(MBEDTLS_GCM_C) - { MBEDTLS_CIPHER_ARIA_128_GCM, &aria_128_gcm_info }, - { MBEDTLS_CIPHER_ARIA_192_GCM, &aria_192_gcm_info }, - { MBEDTLS_CIPHER_ARIA_256_GCM, &aria_256_gcm_info }, -#endif -#if defined(MBEDTLS_CCM_C) - { MBEDTLS_CIPHER_ARIA_128_CCM, &aria_128_ccm_info }, - { MBEDTLS_CIPHER_ARIA_192_CCM, &aria_192_ccm_info }, - { MBEDTLS_CIPHER_ARIA_256_CCM, &aria_256_ccm_info }, - { MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, &aria_128_ccm_star_no_tag_info }, - { MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, &aria_192_ccm_star_no_tag_info }, - { MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, &aria_256_ccm_star_no_tag_info }, -#endif -#endif /* MBEDTLS_ARIA_C */ - -#if defined(MBEDTLS_DES_C) - { MBEDTLS_CIPHER_DES_ECB, &des_ecb_info }, - { MBEDTLS_CIPHER_DES_EDE_ECB, &des_ede_ecb_info }, - { MBEDTLS_CIPHER_DES_EDE3_ECB, &des_ede3_ecb_info }, -#if defined(MBEDTLS_CIPHER_MODE_CBC) - { MBEDTLS_CIPHER_DES_CBC, &des_cbc_info }, - { MBEDTLS_CIPHER_DES_EDE_CBC, &des_ede_cbc_info }, - { MBEDTLS_CIPHER_DES_EDE3_CBC, &des_ede3_cbc_info }, -#endif -#endif /* MBEDTLS_DES_C */ - -#if defined(MBEDTLS_CHACHA20_C) - { MBEDTLS_CIPHER_CHACHA20, &chacha20_info }, -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) - { MBEDTLS_CIPHER_CHACHA20_POLY1305, &chachapoly_info }, -#endif - -#if defined(MBEDTLS_NIST_KW_C) - { MBEDTLS_CIPHER_AES_128_KW, &aes_128_nist_kw_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_KW, &aes_192_nist_kw_info }, - { MBEDTLS_CIPHER_AES_256_KW, &aes_256_nist_kw_info }, -#endif - { MBEDTLS_CIPHER_AES_128_KWP, &aes_128_nist_kwp_info }, -#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) - { MBEDTLS_CIPHER_AES_192_KWP, &aes_192_nist_kwp_info }, - { MBEDTLS_CIPHER_AES_256_KWP, &aes_256_nist_kwp_info }, -#endif -#endif - -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) - { MBEDTLS_CIPHER_NULL, &null_cipher_info }, -#endif /* MBEDTLS_CIPHER_NULL_CIPHER */ - - { MBEDTLS_CIPHER_NONE, NULL } -}; - -#define NUM_CIPHERS (sizeof(mbedtls_cipher_definitions) / \ - sizeof(mbedtls_cipher_definitions[0])) -int mbedtls_cipher_supported[NUM_CIPHERS]; - -const mbedtls_cipher_base_t *mbedtls_cipher_base_lookup_table[] = { -#if defined(MBEDTLS_AES_C) - [MBEDTLS_CIPHER_BASE_INDEX_AES] = &aes_info, -#endif -#if defined(MBEDTLS_ARIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_ARIA] = &aria_info, -#endif -#if defined(MBEDTLS_CAMELLIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA] = &camellia_info, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_AES_C) - [MBEDTLS_CIPHER_BASE_INDEX_CCM_AES] = &ccm_aes_info, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_ARIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA] = &ccm_aria_info, -#endif -#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CAMELLIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA] = &ccm_camellia_info, -#endif -#if defined(MBEDTLS_CHACHA20_C) - [MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE] = &chacha20_base_info, -#endif -#if defined(MBEDTLS_CHACHAPOLY_C) - [MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE] = &chachapoly_base_info, -#endif -#if defined(MBEDTLS_DES_C) - [MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3] = &des_ede3_info, -#endif -#if defined(MBEDTLS_DES_C) - [MBEDTLS_CIPHER_BASE_INDEX_DES_EDE] = &des_ede_info, -#endif -#if defined(MBEDTLS_DES_C) - [MBEDTLS_CIPHER_BASE_INDEX_DES] = &des_info, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_AES_C) - [MBEDTLS_CIPHER_BASE_INDEX_GCM_AES] = &gcm_aes_info, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_ARIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA] = &gcm_aria_info, -#endif -#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_CAMELLIA_C) - [MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA] = &gcm_camellia_info, -#endif -#if defined(MBEDTLS_NIST_KW_C) - [MBEDTLS_CIPHER_BASE_INDEX_KW_AES] = &kw_aes_info, -#endif -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) - [MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE] = &null_base_info, -#endif -#if defined(MBEDTLS_CIPHER_MODE_XTS) && defined(MBEDTLS_AES_C) - [MBEDTLS_CIPHER_BASE_INDEX_XTS_AES] = &xts_aes_info, -#endif - [MBEDTLS_CIPHER_BASE_PREVENT_EMPTY_ENUM] = NULL -}; - -#endif /* MBEDTLS_CIPHER_C */ +/** + * \file cipher_wrap.c + * + * \brief Generic cipher wrapper for Mbed TLS + * + * \author Adriaan de Jong + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_CIPHER_C) + +#include "cipher_wrap.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_CHACHAPOLY_C) +#include "mbedtls/chachapoly.h" +#endif + +#if defined(MBEDTLS_AES_C) +#include "mbedtls/aes.h" +#endif + +#if defined(MBEDTLS_CAMELLIA_C) +#include "mbedtls/camellia.h" +#endif + +#if defined(MBEDTLS_ARIA_C) +#include "mbedtls/aria.h" +#endif + +#if defined(MBEDTLS_DES_C) +#include "mbedtls/des.h" +#endif + +#if defined(MBEDTLS_CHACHA20_C) +#include "mbedtls/chacha20.h" +#endif + +#if defined(MBEDTLS_GCM_C) +#include "mbedtls/gcm.h" +#endif + +#if defined(MBEDTLS_CCM_C) +#include "mbedtls/ccm.h" +#endif + +#if defined(MBEDTLS_NIST_KW_C) +#include "mbedtls/nist_kw.h" +#endif + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) +#include +#endif + +#include "mbedtls/platform.h" + +enum mbedtls_cipher_base_index { +#if defined(MBEDTLS_AES_C) + MBEDTLS_CIPHER_BASE_INDEX_AES, +#endif +#if defined(MBEDTLS_ARIA_C) + MBEDTLS_CIPHER_BASE_INDEX_ARIA, +#endif +#if defined(MBEDTLS_CAMELLIA_C) + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_AES_C) + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_ARIA_C) + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CAMELLIA_C) + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA, +#endif +#if defined(MBEDTLS_CHACHA20_C) + MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE, +#endif +#if defined(MBEDTLS_CHACHAPOLY_C) + MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE, +#endif +#if defined(MBEDTLS_DES_C) + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3, +#endif +#if defined(MBEDTLS_DES_C) + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE, +#endif +#if defined(MBEDTLS_DES_C) + MBEDTLS_CIPHER_BASE_INDEX_DES, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_AES_C) + MBEDTLS_CIPHER_BASE_INDEX_GCM_AES, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_ARIA_C) + MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_CAMELLIA_C) + MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA, +#endif +#if defined(MBEDTLS_NIST_KW_C) + MBEDTLS_CIPHER_BASE_INDEX_KW_AES, +#endif +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) + MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) && defined(MBEDTLS_AES_C) + MBEDTLS_CIPHER_BASE_INDEX_XTS_AES, +#endif + /* Prevent compile failure due to empty enum */ + MBEDTLS_CIPHER_BASE_PREVENT_EMPTY_ENUM +}; + +#if defined(MBEDTLS_GCM_C) +/* shared by all GCM ciphers */ +static void *gcm_ctx_alloc(void) +{ + void *ctx = mbedtls_calloc(1, sizeof(mbedtls_gcm_context)); + + if (ctx != NULL) { + mbedtls_gcm_init((mbedtls_gcm_context *) ctx); + } + + return ctx; +} + +static void gcm_ctx_free(void *ctx) +{ + mbedtls_gcm_free(ctx); + mbedtls_free(ctx); +} +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +/* shared by all CCM ciphers */ +static void *ccm_ctx_alloc(void) +{ + void *ctx = mbedtls_calloc(1, sizeof(mbedtls_ccm_context)); + + if (ctx != NULL) { + mbedtls_ccm_init((mbedtls_ccm_context *) ctx); + } + + return ctx; +} + +static void ccm_ctx_free(void *ctx) +{ + mbedtls_ccm_free(ctx); + mbedtls_free(ctx); +} +#endif /* MBEDTLS_CCM_C */ + +#if defined(MBEDTLS_AES_C) + +static int aes_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aes_crypt_ecb((mbedtls_aes_context *) ctx, operation, input, output); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int aes_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output) +{ + return mbedtls_aes_crypt_cbc((mbedtls_aes_context *) ctx, operation, length, iv, input, + output); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int aes_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aes_crypt_cfb128((mbedtls_aes_context *) ctx, operation, length, iv_off, iv, + input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +static int aes_crypt_ofb_wrap(void *ctx, size_t length, size_t *iv_off, + unsigned char *iv, const unsigned char *input, unsigned char *output) +{ + return mbedtls_aes_crypt_ofb((mbedtls_aes_context *) ctx, length, iv_off, + iv, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int aes_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aes_crypt_ctr((mbedtls_aes_context *) ctx, length, nc_off, nonce_counter, + stream_block, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int aes_crypt_xts_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + int mode; + + switch (operation) { + case MBEDTLS_ENCRYPT: + mode = MBEDTLS_AES_ENCRYPT; + break; + case MBEDTLS_DECRYPT: + mode = MBEDTLS_AES_DECRYPT; + break; + default: + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return mbedtls_aes_crypt_xts(xts_ctx, mode, length, + data_unit, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +static int aes_setkey_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_aes_setkey_dec((mbedtls_aes_context *) ctx, key, key_bitlen); +} + +static int aes_setkey_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_aes_setkey_enc((mbedtls_aes_context *) ctx, key, key_bitlen); +} + +static void *aes_ctx_alloc(void) +{ + mbedtls_aes_context *aes = mbedtls_calloc(1, sizeof(mbedtls_aes_context)); + + if (aes == NULL) { + return NULL; + } + + mbedtls_aes_init(aes); + + return aes; +} + +static void aes_ctx_free(void *ctx) +{ + mbedtls_aes_free((mbedtls_aes_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t aes_info = { + MBEDTLS_CIPHER_ID_AES, + aes_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + aes_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + aes_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + aes_crypt_ofb_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + aes_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + aes_setkey_enc_wrap, + aes_setkey_dec_wrap, + aes_ctx_alloc, + aes_ctx_free +}; + +static const mbedtls_cipher_info_t aes_128_ecb_info = { + "AES-128-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_AES_128_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_ecb_info = { + "AES-192-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_AES_192_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +static const mbedtls_cipher_info_t aes_256_ecb_info = { + "AES-256-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_AES_256_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t aes_128_cbc_info = { + "AES-128-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_AES_128_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_cbc_info = { + "AES-192-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_AES_192_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +static const mbedtls_cipher_info_t aes_256_cbc_info = { + "AES-256-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_AES_256_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; +#endif +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t aes_128_cfb128_info = { + "AES-128-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_AES_128_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_cfb128_info = { + "AES-192-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_AES_192_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +static const mbedtls_cipher_info_t aes_256_cfb128_info = { + "AES-256-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_AES_256_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; +#endif +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +static const mbedtls_cipher_info_t aes_128_ofb_info = { + "AES-128-OFB", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_OFB, + MBEDTLS_CIPHER_AES_128_OFB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_ofb_info = { + "AES-192-OFB", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_OFB, + MBEDTLS_CIPHER_AES_192_OFB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +static const mbedtls_cipher_info_t aes_256_ofb_info = { + "AES-256-OFB", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_OFB, + MBEDTLS_CIPHER_AES_256_OFB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; +#endif +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t aes_128_ctr_info = { + "AES-128-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_AES_128_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_ctr_info = { + "AES-192-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_AES_192_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; + +static const mbedtls_cipher_info_t aes_256_ctr_info = { + "AES-256-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_AES_256_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_AES +}; +#endif +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int xts_aes_setkey_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + return mbedtls_aes_xts_setkey_enc(xts_ctx, key, key_bitlen); +} + +static int xts_aes_setkey_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + return mbedtls_aes_xts_setkey_dec(xts_ctx, key, key_bitlen); +} + +static void *xts_aes_ctx_alloc(void) +{ + mbedtls_aes_xts_context *xts_ctx = mbedtls_calloc(1, sizeof(*xts_ctx)); + + if (xts_ctx != NULL) { + mbedtls_aes_xts_init(xts_ctx); + } + + return xts_ctx; +} + +static void xts_aes_ctx_free(void *ctx) +{ + mbedtls_aes_xts_context *xts_ctx = ctx; + + if (xts_ctx == NULL) { + return; + } + + mbedtls_aes_xts_free(xts_ctx); + mbedtls_free(xts_ctx); +} + +static const mbedtls_cipher_base_t xts_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + aes_crypt_xts_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + xts_aes_setkey_enc_wrap, + xts_aes_setkey_dec_wrap, + xts_aes_ctx_alloc, + xts_aes_ctx_free +}; + +static const mbedtls_cipher_info_t aes_128_xts_info = { + "AES-128-XTS", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_XTS, + MBEDTLS_CIPHER_AES_128_XTS, + 0, + MBEDTLS_CIPHER_BASE_INDEX_XTS_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_256_xts_info = { + "AES-256-XTS", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 512 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_XTS, + MBEDTLS_CIPHER_AES_256_XTS, + 0, + MBEDTLS_CIPHER_BASE_INDEX_XTS_AES +}; +#endif +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_aes_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_AES, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t gcm_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_aes_setkey_wrap, + gcm_aes_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t aes_128_gcm_info = { + "AES-128-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_AES_128_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_gcm_info = { + "AES-192-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_AES_192_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_AES +}; + +static const mbedtls_cipher_info_t aes_256_gcm_info = { + "AES-256-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_AES_256_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_AES +}; +#endif +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_aes_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_AES, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t ccm_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_aes_setkey_wrap, + ccm_aes_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t aes_128_ccm_info = { + "AES-128-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_AES_128_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_ccm_info = { + "AES-192-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_AES_192_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; + +static const mbedtls_cipher_info_t aes_256_ccm_info = { + "AES-256-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_AES_256_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; +#endif + +static const mbedtls_cipher_info_t aes_128_ccm_star_no_tag_info = { + "AES-128-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_ccm_star_no_tag_info = { + "AES-192-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; + +static const mbedtls_cipher_info_t aes_256_ccm_star_no_tag_info = { + "AES-256-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_AES +}; +#endif +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_CAMELLIA_C) + +static int camellia_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_camellia_crypt_ecb((mbedtls_camellia_context *) ctx, operation, input, + output); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int camellia_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, unsigned char *iv, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_camellia_crypt_cbc((mbedtls_camellia_context *) ctx, operation, length, iv, + input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int camellia_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_camellia_crypt_cfb128((mbedtls_camellia_context *) ctx, operation, length, + iv_off, iv, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int camellia_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_camellia_crypt_ctr((mbedtls_camellia_context *) ctx, length, nc_off, + nonce_counter, stream_block, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +static int camellia_setkey_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_camellia_setkey_dec((mbedtls_camellia_context *) ctx, key, key_bitlen); +} + +static int camellia_setkey_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_camellia_setkey_enc((mbedtls_camellia_context *) ctx, key, key_bitlen); +} + +static void *camellia_ctx_alloc(void) +{ + mbedtls_camellia_context *ctx; + ctx = mbedtls_calloc(1, sizeof(mbedtls_camellia_context)); + + if (ctx == NULL) { + return NULL; + } + + mbedtls_camellia_init(ctx); + + return ctx; +} + +static void camellia_ctx_free(void *ctx) +{ + mbedtls_camellia_free((mbedtls_camellia_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + camellia_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + camellia_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + camellia_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + camellia_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + camellia_setkey_enc_wrap, + camellia_setkey_dec_wrap, + camellia_ctx_alloc, + camellia_ctx_free +}; + +static const mbedtls_cipher_info_t camellia_128_ecb_info = { + "CAMELLIA-128-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_CAMELLIA_128_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_ecb_info = { + "CAMELLIA-192-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_CAMELLIA_192_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_ecb_info = { + "CAMELLIA-256-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_CAMELLIA_256_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t camellia_128_cbc_info = { + "CAMELLIA-128-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_CAMELLIA_128_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_cbc_info = { + "CAMELLIA-192-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_CAMELLIA_192_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_cbc_info = { + "CAMELLIA-256-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_CAMELLIA_256_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t camellia_128_cfb128_info = { + "CAMELLIA-128-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_CAMELLIA_128_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_cfb128_info = { + "CAMELLIA-192-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_CAMELLIA_192_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_cfb128_info = { + "CAMELLIA-256-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_CAMELLIA_256_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t camellia_128_ctr_info = { + "CAMELLIA-128-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_CAMELLIA_128_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_ctr_info = { + "CAMELLIA-192-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_CAMELLIA_192_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_ctr_info = { + "CAMELLIA-256-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_CAMELLIA_256_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_camellia_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t gcm_camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_camellia_setkey_wrap, + gcm_camellia_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t camellia_128_gcm_info = { + "CAMELLIA-128-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_CAMELLIA_128_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_gcm_info = { + "CAMELLIA-192-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_CAMELLIA_192_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_gcm_info = { + "CAMELLIA-256-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_CAMELLIA_256_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA +}; +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_camellia_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_CAMELLIA, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t ccm_camellia_info = { + MBEDTLS_CIPHER_ID_CAMELLIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_camellia_setkey_wrap, + ccm_camellia_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t camellia_128_ccm_info = { + "CAMELLIA-128-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_CAMELLIA_128_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_ccm_info = { + "CAMELLIA-192-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_CAMELLIA_192_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_ccm_info = { + "CAMELLIA-256-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_CAMELLIA_256_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_128_ccm_star_no_tag_info = { + "CAMELLIA-128-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_192_ccm_star_no_tag_info = { + "CAMELLIA-192-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; + +static const mbedtls_cipher_info_t camellia_256_ccm_star_no_tag_info = { + "CAMELLIA-256-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA +}; +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_CAMELLIA_C */ + +#if defined(MBEDTLS_ARIA_C) + +static int aria_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output) +{ + (void) operation; + return mbedtls_aria_crypt_ecb((mbedtls_aria_context *) ctx, input, + output); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int aria_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, unsigned char *iv, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aria_crypt_cbc((mbedtls_aria_context *) ctx, operation, length, iv, + input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static int aria_crypt_cfb128_wrap(void *ctx, mbedtls_operation_t operation, + size_t length, size_t *iv_off, unsigned char *iv, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aria_crypt_cfb128((mbedtls_aria_context *) ctx, operation, length, + iv_off, iv, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static int aria_crypt_ctr_wrap(void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output) +{ + return mbedtls_aria_crypt_ctr((mbedtls_aria_context *) ctx, length, nc_off, + nonce_counter, stream_block, input, output); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +static int aria_setkey_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_aria_setkey_dec((mbedtls_aria_context *) ctx, key, key_bitlen); +} + +static int aria_setkey_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_aria_setkey_enc((mbedtls_aria_context *) ctx, key, key_bitlen); +} + +static void *aria_ctx_alloc(void) +{ + mbedtls_aria_context *ctx; + ctx = mbedtls_calloc(1, sizeof(mbedtls_aria_context)); + + if (ctx == NULL) { + return NULL; + } + + mbedtls_aria_init(ctx); + + return ctx; +} + +static void aria_ctx_free(void *ctx) +{ + mbedtls_aria_free((mbedtls_aria_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + aria_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + aria_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + aria_crypt_cfb128_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + aria_crypt_ctr_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + aria_setkey_enc_wrap, + aria_setkey_dec_wrap, + aria_ctx_alloc, + aria_ctx_free +}; + +static const mbedtls_cipher_info_t aria_128_ecb_info = { + "ARIA-128-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_ARIA_128_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_ecb_info = { + "ARIA-192-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_ARIA_192_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_ecb_info = { + "ARIA-256-ECB", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_ARIA_256_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t aria_128_cbc_info = { + "ARIA-128-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_ARIA_128_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_cbc_info = { + "ARIA-192-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_ARIA_192_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_cbc_info = { + "ARIA-256-CBC", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_ARIA_256_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +static const mbedtls_cipher_info_t aria_128_cfb128_info = { + "ARIA-128-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_ARIA_128_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_cfb128_info = { + "ARIA-192-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_ARIA_192_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_cfb128_info = { + "ARIA-256-CFB128", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CFB, + MBEDTLS_CIPHER_ARIA_256_CFB128, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +static const mbedtls_cipher_info_t aria_128_ctr_info = { + "ARIA-128-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_ARIA_128_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_ctr_info = { + "ARIA-192-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_ARIA_192_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_ctr_info = { + "ARIA-256-CTR", + 16, + 16 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CTR, + MBEDTLS_CIPHER_ARIA_256_CTR, + 0, + MBEDTLS_CIPHER_BASE_INDEX_ARIA +}; +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#if defined(MBEDTLS_GCM_C) +static int gcm_aria_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_gcm_setkey((mbedtls_gcm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t gcm_aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + gcm_aria_setkey_wrap, + gcm_aria_setkey_wrap, + gcm_ctx_alloc, + gcm_ctx_free, +}; + +static const mbedtls_cipher_info_t aria_128_gcm_info = { + "ARIA-128-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_ARIA_128_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_gcm_info = { + "ARIA-192-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_ARIA_192_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_gcm_info = { + "ARIA-256-GCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_GCM, + MBEDTLS_CIPHER_ARIA_256_GCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA +}; +#endif /* MBEDTLS_GCM_C */ + +#if defined(MBEDTLS_CCM_C) +static int ccm_aria_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_ccm_setkey((mbedtls_ccm_context *) ctx, MBEDTLS_CIPHER_ID_ARIA, + key, key_bitlen); +} + +static const mbedtls_cipher_base_t ccm_aria_info = { + MBEDTLS_CIPHER_ID_ARIA, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + ccm_aria_setkey_wrap, + ccm_aria_setkey_wrap, + ccm_ctx_alloc, + ccm_ctx_free, +}; + +static const mbedtls_cipher_info_t aria_128_ccm_info = { + "ARIA-128-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_ARIA_128_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_ccm_info = { + "ARIA-192-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_ARIA_192_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_ccm_info = { + "ARIA-256-CCM", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM, + MBEDTLS_CIPHER_ARIA_256_CCM, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_128_ccm_star_no_tag_info = { + "ARIA-128-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_192_ccm_star_no_tag_info = { + "ARIA-192-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; + +static const mbedtls_cipher_info_t aria_256_ccm_star_no_tag_info = { + "ARIA-256-CCM*-NO-TAG", + 16, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, + MBEDTLS_CIPHER_VARIABLE_IV_LEN, + MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA +}; +#endif /* MBEDTLS_CCM_C */ + +#endif /* MBEDTLS_ARIA_C */ + +#if defined(MBEDTLS_DES_C) + +static int des_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output) +{ + ((void) operation); + return mbedtls_des_crypt_ecb((mbedtls_des_context *) ctx, input, output); +} + +static int des3_crypt_ecb_wrap(void *ctx, mbedtls_operation_t operation, + const unsigned char *input, unsigned char *output) +{ + ((void) operation); + return mbedtls_des3_crypt_ecb((mbedtls_des3_context *) ctx, input, output); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int des_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output) +{ + return mbedtls_des_crypt_cbc((mbedtls_des_context *) ctx, operation, length, iv, input, + output); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static int des3_crypt_cbc_wrap(void *ctx, mbedtls_operation_t operation, size_t length, + unsigned char *iv, const unsigned char *input, unsigned char *output) +{ + return mbedtls_des3_crypt_cbc((mbedtls_des3_context *) ctx, operation, length, iv, input, + output); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static int des_setkey_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des_setkey_dec((mbedtls_des_context *) ctx, key); +} + +static int des_setkey_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des_setkey_enc((mbedtls_des_context *) ctx, key); +} + +static int des3_set2key_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des3_set2key_dec((mbedtls_des3_context *) ctx, key); +} + +static int des3_set2key_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des3_set2key_enc((mbedtls_des3_context *) ctx, key); +} + +static int des3_set3key_dec_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des3_set3key_dec((mbedtls_des3_context *) ctx, key); +} + +static int des3_set3key_enc_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) key_bitlen); + + return mbedtls_des3_set3key_enc((mbedtls_des3_context *) ctx, key); +} + +static void *des_ctx_alloc(void) +{ + mbedtls_des_context *des = mbedtls_calloc(1, sizeof(mbedtls_des_context)); + + if (des == NULL) { + return NULL; + } + + mbedtls_des_init(des); + + return des; +} + +static void des_ctx_free(void *ctx) +{ + mbedtls_des_free((mbedtls_des_context *) ctx); + mbedtls_free(ctx); +} + +static void *des3_ctx_alloc(void) +{ + mbedtls_des3_context *des3; + des3 = mbedtls_calloc(1, sizeof(mbedtls_des3_context)); + + if (des3 == NULL) { + return NULL; + } + + mbedtls_des3_init(des3); + + return des3; +} + +static void des3_ctx_free(void *ctx) +{ + mbedtls_des3_free((mbedtls_des3_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t des_info = { + MBEDTLS_CIPHER_ID_DES, + des_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des_setkey_enc_wrap, + des_setkey_dec_wrap, + des_ctx_alloc, + des_ctx_free +}; + +static const mbedtls_cipher_info_t des_ecb_info = { + "DES-ECB", + 8, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_DES_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_cbc_info = { + "DES-CBC", + 8, + 8 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_DES_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static const mbedtls_cipher_base_t des_ede_info = { + MBEDTLS_CIPHER_ID_DES, + des3_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des3_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des3_set2key_enc_wrap, + des3_set2key_dec_wrap, + des3_ctx_alloc, + des3_ctx_free +}; + +static const mbedtls_cipher_info_t des_ede_ecb_info = { + "DES-EDE-ECB", + 8, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES_EDE >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_DES_EDE_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE +}; + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_ede_cbc_info = { + "DES-EDE-CBC", + 8, + 8 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES_EDE >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_DES_EDE_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +static const mbedtls_cipher_base_t des_ede3_info = { + MBEDTLS_CIPHER_ID_3DES, + des3_crypt_ecb_wrap, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + des3_crypt_cbc_wrap, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + des3_set3key_enc_wrap, + des3_set3key_dec_wrap, + des3_ctx_alloc, + des3_ctx_free +}; + +static const mbedtls_cipher_info_t des_ede3_ecb_info = { + "DES-EDE3-ECB", + 8, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES_EDE3 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_ECB, + MBEDTLS_CIPHER_DES_EDE3_ECB, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3 +}; +#if defined(MBEDTLS_CIPHER_MODE_CBC) +static const mbedtls_cipher_info_t des_ede3_cbc_info = { + "DES-EDE3-CBC", + 8, + 8 >> MBEDTLS_IV_SIZE_SHIFT, + MBEDTLS_KEY_LENGTH_DES_EDE3 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CBC, + MBEDTLS_CIPHER_DES_EDE3_CBC, + 0, + MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3 +}; +#endif /* MBEDTLS_CIPHER_MODE_CBC */ +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_CHACHA20_C) + +static int chacha20_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + if (key_bitlen != 256U) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (0 != mbedtls_chacha20_setkey((mbedtls_chacha20_context *) ctx, key)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return 0; +} + +static int chacha20_stream_wrap(void *ctx, size_t length, + const unsigned char *input, + unsigned char *output) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + ret = mbedtls_chacha20_update(ctx, length, input, output); + if (ret == MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return ret; +} + +static void *chacha20_ctx_alloc(void) +{ + mbedtls_chacha20_context *ctx; + ctx = mbedtls_calloc(1, sizeof(mbedtls_chacha20_context)); + + if (ctx == NULL) { + return NULL; + } + + mbedtls_chacha20_init(ctx); + + return ctx; +} + +static void chacha20_ctx_free(void *ctx) +{ + mbedtls_chacha20_free((mbedtls_chacha20_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t chacha20_base_info = { + MBEDTLS_CIPHER_ID_CHACHA20, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + chacha20_stream_wrap, +#endif + chacha20_setkey_wrap, + chacha20_setkey_wrap, + chacha20_ctx_alloc, + chacha20_ctx_free +}; +static const mbedtls_cipher_info_t chacha20_info = { + "CHACHA20", + 1, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_STREAM, + MBEDTLS_CIPHER_CHACHA20, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE +}; +#endif /* MBEDTLS_CHACHA20_C */ + +#if defined(MBEDTLS_CHACHAPOLY_C) + +static int chachapoly_setkey_wrap(void *ctx, + const unsigned char *key, + unsigned int key_bitlen) +{ + if (key_bitlen != 256U) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + if (0 != mbedtls_chachapoly_setkey((mbedtls_chachapoly_context *) ctx, key)) { + return MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA; + } + + return 0; +} + +static void *chachapoly_ctx_alloc(void) +{ + mbedtls_chachapoly_context *ctx; + ctx = mbedtls_calloc(1, sizeof(mbedtls_chachapoly_context)); + + if (ctx == NULL) { + return NULL; + } + + mbedtls_chachapoly_init(ctx); + + return ctx; +} + +static void chachapoly_ctx_free(void *ctx) +{ + mbedtls_chachapoly_free((mbedtls_chachapoly_context *) ctx); + mbedtls_free(ctx); +} + +static const mbedtls_cipher_base_t chachapoly_base_info = { + MBEDTLS_CIPHER_ID_CHACHA20, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + chachapoly_setkey_wrap, + chachapoly_setkey_wrap, + chachapoly_ctx_alloc, + chachapoly_ctx_free +}; +static const mbedtls_cipher_info_t chachapoly_info = { + "CHACHA20-POLY1305", + 1, + 12 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_CHACHAPOLY, + MBEDTLS_CIPHER_CHACHA20_POLY1305, + 0, + MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE +}; +#endif /* MBEDTLS_CHACHAPOLY_C */ + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) +static int null_crypt_stream(void *ctx, size_t length, + const unsigned char *input, + unsigned char *output) +{ + ((void) ctx); + memmove(output, input, length); + return 0; +} + +static int null_setkey(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + ((void) ctx); + ((void) key); + ((void) key_bitlen); + + return 0; +} + +static void *null_ctx_alloc(void) +{ + return (void *) 1; +} + +static void null_ctx_free(void *ctx) +{ + ((void) ctx); +} + +static const mbedtls_cipher_base_t null_base_info = { + MBEDTLS_CIPHER_ID_NULL, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + null_crypt_stream, +#endif + null_setkey, + null_setkey, + null_ctx_alloc, + null_ctx_free +}; + +static const mbedtls_cipher_info_t null_cipher_info = { + "NULL", + 1, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 0 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_STREAM, + MBEDTLS_CIPHER_NULL, + 0, + MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE +}; +#endif /* defined(MBEDTLS_CIPHER_NULL_CIPHER) */ + +#if defined(MBEDTLS_NIST_KW_C) +static void *kw_ctx_alloc(void) +{ + void *ctx = mbedtls_calloc(1, sizeof(mbedtls_nist_kw_context)); + + if (ctx != NULL) { + mbedtls_nist_kw_init((mbedtls_nist_kw_context *) ctx); + } + + return ctx; +} + +static void kw_ctx_free(void *ctx) +{ + mbedtls_nist_kw_free(ctx); + mbedtls_free(ctx); +} + +static int kw_aes_setkey_wrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_nist_kw_setkey((mbedtls_nist_kw_context *) ctx, + MBEDTLS_CIPHER_ID_AES, key, key_bitlen, 1); +} + +static int kw_aes_setkey_unwrap(void *ctx, const unsigned char *key, + unsigned int key_bitlen) +{ + return mbedtls_nist_kw_setkey((mbedtls_nist_kw_context *) ctx, + MBEDTLS_CIPHER_ID_AES, key, key_bitlen, 0); +} + +static const mbedtls_cipher_base_t kw_aes_info = { + MBEDTLS_CIPHER_ID_AES, + NULL, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + NULL, +#endif +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + NULL, +#endif + kw_aes_setkey_wrap, + kw_aes_setkey_unwrap, + kw_ctx_alloc, + kw_ctx_free, +}; + +static const mbedtls_cipher_info_t aes_128_nist_kw_info = { + "AES-128-KW", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KW, + MBEDTLS_CIPHER_AES_128_KW, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_nist_kw_info = { + "AES-192-KW", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KW, + MBEDTLS_CIPHER_AES_192_KW, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; + +static const mbedtls_cipher_info_t aes_256_nist_kw_info = { + "AES-256-KW", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KW, + MBEDTLS_CIPHER_AES_256_KW, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; +#endif + +static const mbedtls_cipher_info_t aes_128_nist_kwp_info = { + "AES-128-KWP", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 128 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KWP, + MBEDTLS_CIPHER_AES_128_KWP, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; + +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) +static const mbedtls_cipher_info_t aes_192_nist_kwp_info = { + "AES-192-KWP", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 192 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KWP, + MBEDTLS_CIPHER_AES_192_KWP, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; + +static const mbedtls_cipher_info_t aes_256_nist_kwp_info = { + "AES-256-KWP", + 16, + 0 >> MBEDTLS_IV_SIZE_SHIFT, + 256 >> MBEDTLS_KEY_BITLEN_SHIFT, + MBEDTLS_MODE_KWP, + MBEDTLS_CIPHER_AES_256_KWP, + 0, + MBEDTLS_CIPHER_BASE_INDEX_KW_AES +}; +#endif +#endif /* MBEDTLS_NIST_KW_C */ + +const mbedtls_cipher_definition_t mbedtls_cipher_definitions[] = +{ +#if defined(MBEDTLS_AES_C) + { MBEDTLS_CIPHER_AES_128_ECB, &aes_128_ecb_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_ECB, &aes_192_ecb_info }, + { MBEDTLS_CIPHER_AES_256_ECB, &aes_256_ecb_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_AES_128_CBC, &aes_128_cbc_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_CBC, &aes_192_cbc_info }, + { MBEDTLS_CIPHER_AES_256_CBC, &aes_256_cbc_info }, +#endif +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_AES_128_CFB128, &aes_128_cfb128_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_CFB128, &aes_192_cfb128_info }, + { MBEDTLS_CIPHER_AES_256_CFB128, &aes_256_cfb128_info }, +#endif +#endif +#if defined(MBEDTLS_CIPHER_MODE_OFB) + { MBEDTLS_CIPHER_AES_128_OFB, &aes_128_ofb_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_OFB, &aes_192_ofb_info }, + { MBEDTLS_CIPHER_AES_256_OFB, &aes_256_ofb_info }, +#endif +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_AES_128_CTR, &aes_128_ctr_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_CTR, &aes_192_ctr_info }, + { MBEDTLS_CIPHER_AES_256_CTR, &aes_256_ctr_info }, +#endif +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) + { MBEDTLS_CIPHER_AES_128_XTS, &aes_128_xts_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_256_XTS, &aes_256_xts_info }, +#endif +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_AES_128_GCM, &aes_128_gcm_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_GCM, &aes_192_gcm_info }, + { MBEDTLS_CIPHER_AES_256_GCM, &aes_256_gcm_info }, +#endif +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_AES_128_CCM, &aes_128_ccm_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_CCM, &aes_192_ccm_info }, + { MBEDTLS_CIPHER_AES_256_CCM, &aes_256_ccm_info }, +#endif + { MBEDTLS_CIPHER_AES_128_CCM_STAR_NO_TAG, &aes_128_ccm_star_no_tag_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_CCM_STAR_NO_TAG, &aes_192_ccm_star_no_tag_info }, + { MBEDTLS_CIPHER_AES_256_CCM_STAR_NO_TAG, &aes_256_ccm_star_no_tag_info }, +#endif +#endif +#endif /* MBEDTLS_AES_C */ + +#if defined(MBEDTLS_CAMELLIA_C) + { MBEDTLS_CIPHER_CAMELLIA_128_ECB, &camellia_128_ecb_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_ECB, &camellia_192_ecb_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_ECB, &camellia_256_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_CAMELLIA_128_CBC, &camellia_128_cbc_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CBC, &camellia_192_cbc_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CBC, &camellia_256_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_CAMELLIA_128_CFB128, &camellia_128_cfb128_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CFB128, &camellia_192_cfb128_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CFB128, &camellia_256_cfb128_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_CAMELLIA_128_CTR, &camellia_128_ctr_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CTR, &camellia_192_ctr_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CTR, &camellia_256_ctr_info }, +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_CAMELLIA_128_GCM, &camellia_128_gcm_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_GCM, &camellia_192_gcm_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_GCM, &camellia_256_gcm_info }, +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_CAMELLIA_128_CCM, &camellia_128_ccm_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CCM, &camellia_192_ccm_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CCM, &camellia_256_ccm_info }, + { MBEDTLS_CIPHER_CAMELLIA_128_CCM_STAR_NO_TAG, &camellia_128_ccm_star_no_tag_info }, + { MBEDTLS_CIPHER_CAMELLIA_192_CCM_STAR_NO_TAG, &camellia_192_ccm_star_no_tag_info }, + { MBEDTLS_CIPHER_CAMELLIA_256_CCM_STAR_NO_TAG, &camellia_256_ccm_star_no_tag_info }, +#endif +#endif /* MBEDTLS_CAMELLIA_C */ + +#if defined(MBEDTLS_ARIA_C) + { MBEDTLS_CIPHER_ARIA_128_ECB, &aria_128_ecb_info }, + { MBEDTLS_CIPHER_ARIA_192_ECB, &aria_192_ecb_info }, + { MBEDTLS_CIPHER_ARIA_256_ECB, &aria_256_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_ARIA_128_CBC, &aria_128_cbc_info }, + { MBEDTLS_CIPHER_ARIA_192_CBC, &aria_192_cbc_info }, + { MBEDTLS_CIPHER_ARIA_256_CBC, &aria_256_cbc_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CFB) + { MBEDTLS_CIPHER_ARIA_128_CFB128, &aria_128_cfb128_info }, + { MBEDTLS_CIPHER_ARIA_192_CFB128, &aria_192_cfb128_info }, + { MBEDTLS_CIPHER_ARIA_256_CFB128, &aria_256_cfb128_info }, +#endif +#if defined(MBEDTLS_CIPHER_MODE_CTR) + { MBEDTLS_CIPHER_ARIA_128_CTR, &aria_128_ctr_info }, + { MBEDTLS_CIPHER_ARIA_192_CTR, &aria_192_ctr_info }, + { MBEDTLS_CIPHER_ARIA_256_CTR, &aria_256_ctr_info }, +#endif +#if defined(MBEDTLS_GCM_C) + { MBEDTLS_CIPHER_ARIA_128_GCM, &aria_128_gcm_info }, + { MBEDTLS_CIPHER_ARIA_192_GCM, &aria_192_gcm_info }, + { MBEDTLS_CIPHER_ARIA_256_GCM, &aria_256_gcm_info }, +#endif +#if defined(MBEDTLS_CCM_C) + { MBEDTLS_CIPHER_ARIA_128_CCM, &aria_128_ccm_info }, + { MBEDTLS_CIPHER_ARIA_192_CCM, &aria_192_ccm_info }, + { MBEDTLS_CIPHER_ARIA_256_CCM, &aria_256_ccm_info }, + { MBEDTLS_CIPHER_ARIA_128_CCM_STAR_NO_TAG, &aria_128_ccm_star_no_tag_info }, + { MBEDTLS_CIPHER_ARIA_192_CCM_STAR_NO_TAG, &aria_192_ccm_star_no_tag_info }, + { MBEDTLS_CIPHER_ARIA_256_CCM_STAR_NO_TAG, &aria_256_ccm_star_no_tag_info }, +#endif +#endif /* MBEDTLS_ARIA_C */ + +#if defined(MBEDTLS_DES_C) + { MBEDTLS_CIPHER_DES_ECB, &des_ecb_info }, + { MBEDTLS_CIPHER_DES_EDE_ECB, &des_ede_ecb_info }, + { MBEDTLS_CIPHER_DES_EDE3_ECB, &des_ede3_ecb_info }, +#if defined(MBEDTLS_CIPHER_MODE_CBC) + { MBEDTLS_CIPHER_DES_CBC, &des_cbc_info }, + { MBEDTLS_CIPHER_DES_EDE_CBC, &des_ede_cbc_info }, + { MBEDTLS_CIPHER_DES_EDE3_CBC, &des_ede3_cbc_info }, +#endif +#endif /* MBEDTLS_DES_C */ + +#if defined(MBEDTLS_CHACHA20_C) + { MBEDTLS_CIPHER_CHACHA20, &chacha20_info }, +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + { MBEDTLS_CIPHER_CHACHA20_POLY1305, &chachapoly_info }, +#endif + +#if defined(MBEDTLS_NIST_KW_C) + { MBEDTLS_CIPHER_AES_128_KW, &aes_128_nist_kw_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_KW, &aes_192_nist_kw_info }, + { MBEDTLS_CIPHER_AES_256_KW, &aes_256_nist_kw_info }, +#endif + { MBEDTLS_CIPHER_AES_128_KWP, &aes_128_nist_kwp_info }, +#if !defined(MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH) + { MBEDTLS_CIPHER_AES_192_KWP, &aes_192_nist_kwp_info }, + { MBEDTLS_CIPHER_AES_256_KWP, &aes_256_nist_kwp_info }, +#endif +#endif + +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) + { MBEDTLS_CIPHER_NULL, &null_cipher_info }, +#endif /* MBEDTLS_CIPHER_NULL_CIPHER */ + + { MBEDTLS_CIPHER_NONE, NULL } +}; + +#define NUM_CIPHERS (sizeof(mbedtls_cipher_definitions) / \ + sizeof(mbedtls_cipher_definitions[0])) +int mbedtls_cipher_supported[NUM_CIPHERS]; + +const mbedtls_cipher_base_t *mbedtls_cipher_base_lookup_table[] = { +#if defined(MBEDTLS_AES_C) + [MBEDTLS_CIPHER_BASE_INDEX_AES] = &aes_info, +#endif +#if defined(MBEDTLS_ARIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_ARIA] = &aria_info, +#endif +#if defined(MBEDTLS_CAMELLIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_CAMELLIA] = &camellia_info, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_AES_C) + [MBEDTLS_CIPHER_BASE_INDEX_CCM_AES] = &ccm_aes_info, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_ARIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_CCM_ARIA] = &ccm_aria_info, +#endif +#if defined(MBEDTLS_CCM_C) && defined(MBEDTLS_CAMELLIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_CCM_CAMELLIA] = &ccm_camellia_info, +#endif +#if defined(MBEDTLS_CHACHA20_C) + [MBEDTLS_CIPHER_BASE_INDEX_CHACHA20_BASE] = &chacha20_base_info, +#endif +#if defined(MBEDTLS_CHACHAPOLY_C) + [MBEDTLS_CIPHER_BASE_INDEX_CHACHAPOLY_BASE] = &chachapoly_base_info, +#endif +#if defined(MBEDTLS_DES_C) + [MBEDTLS_CIPHER_BASE_INDEX_DES_EDE3] = &des_ede3_info, +#endif +#if defined(MBEDTLS_DES_C) + [MBEDTLS_CIPHER_BASE_INDEX_DES_EDE] = &des_ede_info, +#endif +#if defined(MBEDTLS_DES_C) + [MBEDTLS_CIPHER_BASE_INDEX_DES] = &des_info, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_AES_C) + [MBEDTLS_CIPHER_BASE_INDEX_GCM_AES] = &gcm_aes_info, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_ARIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_GCM_ARIA] = &gcm_aria_info, +#endif +#if defined(MBEDTLS_GCM_C) && defined(MBEDTLS_CAMELLIA_C) + [MBEDTLS_CIPHER_BASE_INDEX_GCM_CAMELLIA] = &gcm_camellia_info, +#endif +#if defined(MBEDTLS_NIST_KW_C) + [MBEDTLS_CIPHER_BASE_INDEX_KW_AES] = &kw_aes_info, +#endif +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) + [MBEDTLS_CIPHER_BASE_INDEX_NULL_BASE] = &null_base_info, +#endif +#if defined(MBEDTLS_CIPHER_MODE_XTS) && defined(MBEDTLS_AES_C) + [MBEDTLS_CIPHER_BASE_INDEX_XTS_AES] = &xts_aes_info, +#endif + [MBEDTLS_CIPHER_BASE_PREVENT_EMPTY_ENUM] = NULL +}; + +#endif /* MBEDTLS_CIPHER_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.h index c85a4ef..75fabd3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/cipher_wrap.h @@ -1,144 +1,144 @@ -/** - * \file cipher_wrap.h - * - * \brief Cipher wrappers. - * - * \author Adriaan de Jong - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_CIPHER_WRAP_H -#define MBEDTLS_CIPHER_WRAP_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/cipher.h" - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#include "psa/crypto.h" -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Base cipher information. The non-mode specific functions and values. - */ -struct mbedtls_cipher_base_t { - /** Base Cipher type (e.g. MBEDTLS_CIPHER_ID_AES) */ - mbedtls_cipher_id_t cipher; - - /** Encrypt using ECB */ - int (*ecb_func)(void *ctx, mbedtls_operation_t mode, - const unsigned char *input, unsigned char *output); - -#if defined(MBEDTLS_CIPHER_MODE_CBC) - /** Encrypt using CBC */ - int (*cbc_func)(void *ctx, mbedtls_operation_t mode, size_t length, - unsigned char *iv, const unsigned char *input, - unsigned char *output); -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CFB) - /** Encrypt using CFB (Full length) */ - int (*cfb_func)(void *ctx, mbedtls_operation_t mode, size_t length, size_t *iv_off, - unsigned char *iv, const unsigned char *input, - unsigned char *output); -#endif - -#if defined(MBEDTLS_CIPHER_MODE_OFB) - /** Encrypt using OFB (Full length) */ - int (*ofb_func)(void *ctx, size_t length, size_t *iv_off, - unsigned char *iv, - const unsigned char *input, - unsigned char *output); -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CTR) - /** Encrypt using CTR */ - int (*ctr_func)(void *ctx, size_t length, size_t *nc_off, - unsigned char *nonce_counter, unsigned char *stream_block, - const unsigned char *input, unsigned char *output); -#endif - -#if defined(MBEDTLS_CIPHER_MODE_XTS) - /** Encrypt or decrypt using XTS. */ - int (*xts_func)(void *ctx, mbedtls_operation_t mode, size_t length, - const unsigned char data_unit[16], - const unsigned char *input, unsigned char *output); -#endif - -#if defined(MBEDTLS_CIPHER_MODE_STREAM) - /** Encrypt using STREAM */ - int (*stream_func)(void *ctx, size_t length, - const unsigned char *input, unsigned char *output); -#endif - - /** Set key for encryption purposes */ - int (*setkey_enc_func)(void *ctx, const unsigned char *key, - unsigned int key_bitlen); - - /** Set key for decryption purposes */ - int (*setkey_dec_func)(void *ctx, const unsigned char *key, - unsigned int key_bitlen); - - /** Allocate a new context */ - void * (*ctx_alloc_func)(void); - - /** Free the given context */ - void (*ctx_free_func)(void *ctx); - -}; - -typedef struct { - mbedtls_cipher_type_t type; - const mbedtls_cipher_info_t *info; -} mbedtls_cipher_definition_t; - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -typedef enum { - MBEDTLS_CIPHER_PSA_KEY_UNSET = 0, - MBEDTLS_CIPHER_PSA_KEY_OWNED, /* Used for PSA-based cipher contexts which */ - /* use raw key material internally imported */ - /* as a volatile key, and which hence need */ - /* to destroy that key when the context is */ - /* freed. */ - MBEDTLS_CIPHER_PSA_KEY_NOT_OWNED, /* Used for PSA-based cipher contexts */ - /* which use a key provided by the */ - /* user, and which hence will not be */ - /* destroyed when the context is freed. */ -} mbedtls_cipher_psa_key_ownership; - -typedef struct { - psa_algorithm_t alg; - mbedtls_svc_key_id_t slot; - mbedtls_cipher_psa_key_ownership slot_state; -} mbedtls_cipher_context_psa; -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -extern const mbedtls_cipher_definition_t mbedtls_cipher_definitions[]; - -extern int mbedtls_cipher_supported[]; - -extern const mbedtls_cipher_base_t *mbedtls_cipher_base_lookup_table[]; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_CIPHER_WRAP_H */ +/** + * \file cipher_wrap.h + * + * \brief Cipher wrappers. + * + * \author Adriaan de Jong + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_CIPHER_WRAP_H +#define MBEDTLS_CIPHER_WRAP_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/cipher.h" + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#include "psa/crypto.h" +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Base cipher information. The non-mode specific functions and values. + */ +struct mbedtls_cipher_base_t { + /** Base Cipher type (e.g. MBEDTLS_CIPHER_ID_AES) */ + mbedtls_cipher_id_t cipher; + + /** Encrypt using ECB */ + int (*ecb_func)(void *ctx, mbedtls_operation_t mode, + const unsigned char *input, unsigned char *output); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + /** Encrypt using CBC */ + int (*cbc_func)(void *ctx, mbedtls_operation_t mode, size_t length, + unsigned char *iv, const unsigned char *input, + unsigned char *output); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CFB) + /** Encrypt using CFB (Full length) */ + int (*cfb_func)(void *ctx, mbedtls_operation_t mode, size_t length, size_t *iv_off, + unsigned char *iv, const unsigned char *input, + unsigned char *output); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_OFB) + /** Encrypt using OFB (Full length) */ + int (*ofb_func)(void *ctx, size_t length, size_t *iv_off, + unsigned char *iv, + const unsigned char *input, + unsigned char *output); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CTR) + /** Encrypt using CTR */ + int (*ctr_func)(void *ctx, size_t length, size_t *nc_off, + unsigned char *nonce_counter, unsigned char *stream_block, + const unsigned char *input, unsigned char *output); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + /** Encrypt or decrypt using XTS. */ + int (*xts_func)(void *ctx, mbedtls_operation_t mode, size_t length, + const unsigned char data_unit[16], + const unsigned char *input, unsigned char *output); +#endif + +#if defined(MBEDTLS_CIPHER_MODE_STREAM) + /** Encrypt using STREAM */ + int (*stream_func)(void *ctx, size_t length, + const unsigned char *input, unsigned char *output); +#endif + + /** Set key for encryption purposes */ + int (*setkey_enc_func)(void *ctx, const unsigned char *key, + unsigned int key_bitlen); + + /** Set key for decryption purposes */ + int (*setkey_dec_func)(void *ctx, const unsigned char *key, + unsigned int key_bitlen); + + /** Allocate a new context */ + void * (*ctx_alloc_func)(void); + + /** Free the given context */ + void (*ctx_free_func)(void *ctx); + +}; + +typedef struct { + mbedtls_cipher_type_t type; + const mbedtls_cipher_info_t *info; +} mbedtls_cipher_definition_t; + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +typedef enum { + MBEDTLS_CIPHER_PSA_KEY_UNSET = 0, + MBEDTLS_CIPHER_PSA_KEY_OWNED, /* Used for PSA-based cipher contexts which */ + /* use raw key material internally imported */ + /* as a volatile key, and which hence need */ + /* to destroy that key when the context is */ + /* freed. */ + MBEDTLS_CIPHER_PSA_KEY_NOT_OWNED, /* Used for PSA-based cipher contexts */ + /* which use a key provided by the */ + /* user, and which hence will not be */ + /* destroyed when the context is freed. */ +} mbedtls_cipher_psa_key_ownership; + +typedef struct { + psa_algorithm_t alg; + mbedtls_svc_key_id_t slot; + mbedtls_cipher_psa_key_ownership slot_state; +} mbedtls_cipher_context_psa; +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +extern const mbedtls_cipher_definition_t mbedtls_cipher_definitions[]; + +extern int mbedtls_cipher_supported[]; + +extern const mbedtls_cipher_base_t *mbedtls_cipher_base_lookup_table[]; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CIPHER_WRAP_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/common.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/common.h index 3c472c6..ecd483a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/common.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/common.h @@ -1,337 +1,337 @@ -/** - * \file common.h - * - * \brief Utility macros for internal use in the library - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_LIBRARY_COMMON_H -#define MBEDTLS_LIBRARY_COMMON_H - -#include "mbedtls/build_info.h" -#include "alignment.h" - -#include -#include -#include -#include - -#if defined(__ARM_NEON) -#include -#endif /* __ARM_NEON */ - -/** Helper to define a function as static except when building invasive tests. - * - * If a function is only used inside its own source file and should be - * declared `static` to allow the compiler to optimize for code size, - * but that function has unit tests, define it with - * ``` - * MBEDTLS_STATIC_TESTABLE int mbedtls_foo(...) { ... } - * ``` - * and declare it in a header in the `library/` directory with - * ``` - * #if defined(MBEDTLS_TEST_HOOKS) - * int mbedtls_foo(...); - * #endif - * ``` - */ -#if defined(MBEDTLS_TEST_HOOKS) -#define MBEDTLS_STATIC_TESTABLE -#else -#define MBEDTLS_STATIC_TESTABLE static -#endif - -#if defined(MBEDTLS_TEST_HOOKS) -extern void (*mbedtls_test_hook_test_fail)(const char *test, int line, const char *file); -#define MBEDTLS_TEST_HOOK_TEST_ASSERT(TEST) \ - do { \ - if ((!(TEST)) && ((*mbedtls_test_hook_test_fail) != NULL)) \ - { \ - (*mbedtls_test_hook_test_fail)( #TEST, __LINE__, __FILE__); \ - } \ - } while (0) -#else -#define MBEDTLS_TEST_HOOK_TEST_ASSERT(TEST) -#endif /* defined(MBEDTLS_TEST_HOOKS) */ - -/** \def ARRAY_LENGTH - * Return the number of elements of a static or stack array. - * - * \param array A value of array (not pointer) type. - * - * \return The number of elements of the array. - */ -/* A correct implementation of ARRAY_LENGTH, but which silently gives - * a nonsensical result if called with a pointer rather than an array. */ -#define ARRAY_LENGTH_UNSAFE(array) \ - (sizeof(array) / sizeof(*(array))) - -#if defined(__GNUC__) -/* Test if arg and &(arg)[0] have the same type. This is true if arg is - * an array but not if it's a pointer. */ -#define IS_ARRAY_NOT_POINTER(arg) \ - (!__builtin_types_compatible_p(__typeof__(arg), \ - __typeof__(&(arg)[0]))) -/* A compile-time constant with the value 0. If `const_expr` is not a - * compile-time constant with a nonzero value, cause a compile-time error. */ -#define STATIC_ASSERT_EXPR(const_expr) \ - (0 && sizeof(struct { unsigned int STATIC_ASSERT : 1 - 2 * !(const_expr); })) - -/* Return the scalar value `value` (possibly promoted). This is a compile-time - * constant if `value` is. `condition` must be a compile-time constant. - * If `condition` is false, arrange to cause a compile-time error. */ -#define STATIC_ASSERT_THEN_RETURN(condition, value) \ - (STATIC_ASSERT_EXPR(condition) ? 0 : (value)) - -#define ARRAY_LENGTH(array) \ - (STATIC_ASSERT_THEN_RETURN(IS_ARRAY_NOT_POINTER(array), \ - ARRAY_LENGTH_UNSAFE(array))) - -#else -/* If we aren't sure the compiler supports our non-standard tricks, - * fall back to the unsafe implementation. */ -#define ARRAY_LENGTH(array) ARRAY_LENGTH_UNSAFE(array) -#endif -/** Allow library to access its structs' private members. - * - * Although structs defined in header files are publicly available, - * their members are private and should not be accessed by the user. - */ -#define MBEDTLS_ALLOW_PRIVATE_ACCESS - -/** - * \brief Securely zeroize a buffer then free it. - * - * Similar to making consecutive calls to - * \c mbedtls_platform_zeroize() and \c mbedtls_free(), but has - * code size savings, and potential for optimisation in the future. - * - * Guaranteed to be a no-op if \p buf is \c NULL and \p len is 0. - * - * \param buf Buffer to be zeroized then freed. - * \param len Length of the buffer in bytes - */ -void mbedtls_zeroize_and_free(void *buf, size_t len); - -/** Return an offset into a buffer. - * - * This is just the addition of an offset to a pointer, except that this - * function also accepts an offset of 0 into a buffer whose pointer is null. - * (`p + n` has undefined behavior when `p` is null, even when `n == 0`. - * A null pointer is a valid buffer pointer when the size is 0, for example - * as the result of `malloc(0)` on some platforms.) - * - * \param p Pointer to a buffer of at least n bytes. - * This may be \p NULL if \p n is zero. - * \param n An offset in bytes. - * \return Pointer to offset \p n in the buffer \p p. - * Note that this is only a valid pointer if the size of the - * buffer is at least \p n + 1. - */ -static inline unsigned char *mbedtls_buffer_offset( - unsigned char *p, size_t n) -{ - return p == NULL ? NULL : p + n; -} - -/** Return an offset into a read-only buffer. - * - * Similar to mbedtls_buffer_offset(), but for const pointers. - * - * \param p Pointer to a buffer of at least n bytes. - * This may be \p NULL if \p n is zero. - * \param n An offset in bytes. - * \return Pointer to offset \p n in the buffer \p p. - * Note that this is only a valid pointer if the size of the - * buffer is at least \p n + 1. - */ -static inline const unsigned char *mbedtls_buffer_offset_const( - const unsigned char *p, size_t n) -{ - return p == NULL ? NULL : p + n; -} - -/** - * Perform a fast block XOR operation, such that - * r[i] = a[i] ^ b[i] where 0 <= i < n - * - * \param r Pointer to result (buffer of at least \p n bytes). \p r - * may be equal to either \p a or \p b, but behaviour when - * it overlaps in other ways is undefined. - * \param a Pointer to input (buffer of at least \p n bytes) - * \param b Pointer to input (buffer of at least \p n bytes) - * \param n Number of bytes to process. - */ -inline void mbedtls_xor(unsigned char *r, const unsigned char *a, const unsigned char *b, size_t n) -{ - size_t i = 0; -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) -#if defined(__ARM_NEON) - for (; (i + 16) <= n; i += 16) { - uint8x16_t v1 = vld1q_u8(a + i); - uint8x16_t v2 = vld1q_u8(b + i); - uint8x16_t x = veorq_u8(v1, v2); - vst1q_u8(r + i, x); - } -#elif defined(__amd64__) || defined(__x86_64__) || defined(__aarch64__) - /* This codepath probably only makes sense on architectures with 64-bit registers */ - for (; (i + 8) <= n; i += 8) { - uint64_t x = mbedtls_get_unaligned_uint64(a + i) ^ mbedtls_get_unaligned_uint64(b + i); - mbedtls_put_unaligned_uint64(r + i, x); - } -#else - for (; (i + 4) <= n; i += 4) { - uint32_t x = mbedtls_get_unaligned_uint32(a + i) ^ mbedtls_get_unaligned_uint32(b + i); - mbedtls_put_unaligned_uint32(r + i, x); - } -#endif -#endif - for (; i < n; i++) { - r[i] = a[i] ^ b[i]; - } -} - -/** - * Perform a fast block XOR operation, such that - * r[i] = a[i] ^ b[i] where 0 <= i < n - * - * In some situations, this can perform better than mbedtls_xor (e.g., it's about 5% - * better in AES-CBC). - * - * \param r Pointer to result (buffer of at least \p n bytes). \p r - * may be equal to either \p a or \p b, but behaviour when - * it overlaps in other ways is undefined. - * \param a Pointer to input (buffer of at least \p n bytes) - * \param b Pointer to input (buffer of at least \p n bytes) - * \param n Number of bytes to process. - */ -static inline void mbedtls_xor_no_simd(unsigned char *r, - const unsigned char *a, - const unsigned char *b, - size_t n) -{ - size_t i = 0; -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) -#if defined(__amd64__) || defined(__x86_64__) || defined(__aarch64__) - /* This codepath probably only makes sense on architectures with 64-bit registers */ - for (; (i + 8) <= n; i += 8) { - uint64_t x = mbedtls_get_unaligned_uint64(a + i) ^ mbedtls_get_unaligned_uint64(b + i); - mbedtls_put_unaligned_uint64(r + i, x); - } -#else - for (; (i + 4) <= n; i += 4) { - uint32_t x = mbedtls_get_unaligned_uint32(a + i) ^ mbedtls_get_unaligned_uint32(b + i); - mbedtls_put_unaligned_uint32(r + i, x); - } -#endif -#endif - for (; i < n; i++) { - r[i] = a[i] ^ b[i]; - } -} - -/* Fix MSVC C99 compatible issue - * MSVC support __func__ from visual studio 2015( 1900 ) - * Use MSVC predefine macro to avoid name check fail. - */ -#if (defined(_MSC_VER) && (_MSC_VER <= 1900)) -#define /*no-check-names*/ __func__ __FUNCTION__ -#endif - -/* Define `asm` for compilers which don't define it. */ -/* *INDENT-OFF* */ -#ifndef asm -#if defined(__IAR_SYSTEMS_ICC__) -#define asm __asm -#else -#define asm __asm__ -#endif -#endif -/* *INDENT-ON* */ - -/* - * Define the constraint used for read-only pointer operands to aarch64 asm. - * - * This is normally the usual "r", but for aarch64_32 (aka ILP32, - * as found in watchos), "p" is required to avoid warnings from clang. - * - * Note that clang does not recognise '+p' or '=p', and armclang - * does not recognise 'p' at all. Therefore, to update a pointer from - * aarch64 assembly, it is necessary to use something like: - * - * uintptr_t uptr = (uintptr_t) ptr; - * asm( "ldr x4, [%x0], #8" ... : "+r" (uptr) : : ) - * ptr = (void*) uptr; - * - * Note that the "x" in "%x0" is neccessary; writing "%0" will cause warnings. - */ -#if defined(__aarch64__) && defined(MBEDTLS_HAVE_ASM) -#if UINTPTR_MAX == 0xfffffffful -/* ILP32: Specify the pointer operand slightly differently, as per #7787. */ -#define MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT "p" -#elif UINTPTR_MAX == 0xfffffffffffffffful -/* Normal case (64-bit pointers): use "r" as the constraint for pointer operands to asm */ -#define MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT "r" -#else -#error "Unrecognised pointer size for aarch64" -#endif -#endif - -/* Always provide a static assert macro, so it can be used unconditionally. - * It will expand to nothing on some systems. - * Can be used outside functions (but don't add a trailing ';' in that case: - * the semicolon is included here to avoid triggering -Wextra-semi when - * MBEDTLS_STATIC_ASSERT() expands to nothing). - * Can't use the C11-style `defined(static_assert)` on FreeBSD, since it - * defines static_assert even with -std=c99, but then complains about it. - */ -#if defined(static_assert) && !defined(__FreeBSD__) -#define MBEDTLS_STATIC_ASSERT(expr, msg) static_assert(expr, msg); -#else -#define MBEDTLS_STATIC_ASSERT(expr, msg) -#endif - -/* Define compiler branch hints */ -#if defined(__has_builtin) -#if __has_builtin(__builtin_expect) -#define MBEDTLS_LIKELY(x) __builtin_expect(!!(x), 1) -#define MBEDTLS_UNLIKELY(x) __builtin_expect(!!(x), 0) -#endif -#endif -#if !defined(MBEDTLS_LIKELY) -#define MBEDTLS_LIKELY(x) x -#define MBEDTLS_UNLIKELY(x) x -#endif - -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__clang__) \ - && !defined(__llvm__) && !defined(__INTEL_COMPILER) -/* Defined if the compiler really is gcc and not clang, etc */ -#define MBEDTLS_COMPILER_IS_GCC -#endif - -/* For gcc -Os, override with -O2 for a given function. - * - * This will not affect behaviour for other optimisation settings, e.g. -O0. - */ -#if defined(MBEDTLS_COMPILER_IS_GCC) && defined(__OPTIMIZE_SIZE__) -#define MBEDTLS_OPTIMIZE_FOR_PERFORMANCE __attribute__((optimize("-O2"))) -#else -#define MBEDTLS_OPTIMIZE_FOR_PERFORMANCE -#endif - -#endif /* MBEDTLS_LIBRARY_COMMON_H */ +/** + * \file common.h + * + * \brief Utility macros for internal use in the library + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_LIBRARY_COMMON_H +#define MBEDTLS_LIBRARY_COMMON_H + +#include "mbedtls/build_info.h" +#include "alignment.h" + +#include +#include +#include +#include + +#if defined(__ARM_NEON) +#include +#endif /* __ARM_NEON */ + +/** Helper to define a function as static except when building invasive tests. + * + * If a function is only used inside its own source file and should be + * declared `static` to allow the compiler to optimize for code size, + * but that function has unit tests, define it with + * ``` + * MBEDTLS_STATIC_TESTABLE int mbedtls_foo(...) { ... } + * ``` + * and declare it in a header in the `library/` directory with + * ``` + * #if defined(MBEDTLS_TEST_HOOKS) + * int mbedtls_foo(...); + * #endif + * ``` + */ +#if defined(MBEDTLS_TEST_HOOKS) +#define MBEDTLS_STATIC_TESTABLE +#else +#define MBEDTLS_STATIC_TESTABLE static +#endif + +#if defined(MBEDTLS_TEST_HOOKS) +extern void (*mbedtls_test_hook_test_fail)(const char *test, int line, const char *file); +#define MBEDTLS_TEST_HOOK_TEST_ASSERT(TEST) \ + do { \ + if ((!(TEST)) && ((*mbedtls_test_hook_test_fail) != NULL)) \ + { \ + (*mbedtls_test_hook_test_fail)( #TEST, __LINE__, __FILE__); \ + } \ + } while (0) +#else +#define MBEDTLS_TEST_HOOK_TEST_ASSERT(TEST) +#endif /* defined(MBEDTLS_TEST_HOOKS) */ + +/** \def ARRAY_LENGTH + * Return the number of elements of a static or stack array. + * + * \param array A value of array (not pointer) type. + * + * \return The number of elements of the array. + */ +/* A correct implementation of ARRAY_LENGTH, but which silently gives + * a nonsensical result if called with a pointer rather than an array. */ +#define ARRAY_LENGTH_UNSAFE(array) \ + (sizeof(array) / sizeof(*(array))) + +#if defined(__GNUC__) +/* Test if arg and &(arg)[0] have the same type. This is true if arg is + * an array but not if it's a pointer. */ +#define IS_ARRAY_NOT_POINTER(arg) \ + (!__builtin_types_compatible_p(__typeof__(arg), \ + __typeof__(&(arg)[0]))) +/* A compile-time constant with the value 0. If `const_expr` is not a + * compile-time constant with a nonzero value, cause a compile-time error. */ +#define STATIC_ASSERT_EXPR(const_expr) \ + (0 && sizeof(struct { unsigned int STATIC_ASSERT : 1 - 2 * !(const_expr); })) + +/* Return the scalar value `value` (possibly promoted). This is a compile-time + * constant if `value` is. `condition` must be a compile-time constant. + * If `condition` is false, arrange to cause a compile-time error. */ +#define STATIC_ASSERT_THEN_RETURN(condition, value) \ + (STATIC_ASSERT_EXPR(condition) ? 0 : (value)) + +#define ARRAY_LENGTH(array) \ + (STATIC_ASSERT_THEN_RETURN(IS_ARRAY_NOT_POINTER(array), \ + ARRAY_LENGTH_UNSAFE(array))) + +#else +/* If we aren't sure the compiler supports our non-standard tricks, + * fall back to the unsafe implementation. */ +#define ARRAY_LENGTH(array) ARRAY_LENGTH_UNSAFE(array) +#endif +/** Allow library to access its structs' private members. + * + * Although structs defined in header files are publicly available, + * their members are private and should not be accessed by the user. + */ +#define MBEDTLS_ALLOW_PRIVATE_ACCESS + +/** + * \brief Securely zeroize a buffer then free it. + * + * Similar to making consecutive calls to + * \c mbedtls_platform_zeroize() and \c mbedtls_free(), but has + * code size savings, and potential for optimisation in the future. + * + * Guaranteed to be a no-op if \p buf is \c NULL and \p len is 0. + * + * \param buf Buffer to be zeroized then freed. + * \param len Length of the buffer in bytes + */ +void mbedtls_zeroize_and_free(void *buf, size_t len); + +/** Return an offset into a buffer. + * + * This is just the addition of an offset to a pointer, except that this + * function also accepts an offset of 0 into a buffer whose pointer is null. + * (`p + n` has undefined behavior when `p` is null, even when `n == 0`. + * A null pointer is a valid buffer pointer when the size is 0, for example + * as the result of `malloc(0)` on some platforms.) + * + * \param p Pointer to a buffer of at least n bytes. + * This may be \p NULL if \p n is zero. + * \param n An offset in bytes. + * \return Pointer to offset \p n in the buffer \p p. + * Note that this is only a valid pointer if the size of the + * buffer is at least \p n + 1. + */ +static inline unsigned char *mbedtls_buffer_offset( + unsigned char *p, size_t n) +{ + return p == NULL ? NULL : p + n; +} + +/** Return an offset into a read-only buffer. + * + * Similar to mbedtls_buffer_offset(), but for const pointers. + * + * \param p Pointer to a buffer of at least n bytes. + * This may be \p NULL if \p n is zero. + * \param n An offset in bytes. + * \return Pointer to offset \p n in the buffer \p p. + * Note that this is only a valid pointer if the size of the + * buffer is at least \p n + 1. + */ +static inline const unsigned char *mbedtls_buffer_offset_const( + const unsigned char *p, size_t n) +{ + return p == NULL ? NULL : p + n; +} + +/** + * Perform a fast block XOR operation, such that + * r[i] = a[i] ^ b[i] where 0 <= i < n + * + * \param r Pointer to result (buffer of at least \p n bytes). \p r + * may be equal to either \p a or \p b, but behaviour when + * it overlaps in other ways is undefined. + * \param a Pointer to input (buffer of at least \p n bytes) + * \param b Pointer to input (buffer of at least \p n bytes) + * \param n Number of bytes to process. + */ +inline void mbedtls_xor(unsigned char *r, const unsigned char *a, const unsigned char *b, size_t n) +{ + size_t i = 0; +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) +#if defined(__ARM_NEON) + for (; (i + 16) <= n; i += 16) { + uint8x16_t v1 = vld1q_u8(a + i); + uint8x16_t v2 = vld1q_u8(b + i); + uint8x16_t x = veorq_u8(v1, v2); + vst1q_u8(r + i, x); + } +#elif defined(__amd64__) || defined(__x86_64__) || defined(__aarch64__) + /* This codepath probably only makes sense on architectures with 64-bit registers */ + for (; (i + 8) <= n; i += 8) { + uint64_t x = mbedtls_get_unaligned_uint64(a + i) ^ mbedtls_get_unaligned_uint64(b + i); + mbedtls_put_unaligned_uint64(r + i, x); + } +#else + for (; (i + 4) <= n; i += 4) { + uint32_t x = mbedtls_get_unaligned_uint32(a + i) ^ mbedtls_get_unaligned_uint32(b + i); + mbedtls_put_unaligned_uint32(r + i, x); + } +#endif +#endif + for (; i < n; i++) { + r[i] = a[i] ^ b[i]; + } +} + +/** + * Perform a fast block XOR operation, such that + * r[i] = a[i] ^ b[i] where 0 <= i < n + * + * In some situations, this can perform better than mbedtls_xor (e.g., it's about 5% + * better in AES-CBC). + * + * \param r Pointer to result (buffer of at least \p n bytes). \p r + * may be equal to either \p a or \p b, but behaviour when + * it overlaps in other ways is undefined. + * \param a Pointer to input (buffer of at least \p n bytes) + * \param b Pointer to input (buffer of at least \p n bytes) + * \param n Number of bytes to process. + */ +static inline void mbedtls_xor_no_simd(unsigned char *r, + const unsigned char *a, + const unsigned char *b, + size_t n) +{ + size_t i = 0; +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) +#if defined(__amd64__) || defined(__x86_64__) || defined(__aarch64__) + /* This codepath probably only makes sense on architectures with 64-bit registers */ + for (; (i + 8) <= n; i += 8) { + uint64_t x = mbedtls_get_unaligned_uint64(a + i) ^ mbedtls_get_unaligned_uint64(b + i); + mbedtls_put_unaligned_uint64(r + i, x); + } +#else + for (; (i + 4) <= n; i += 4) { + uint32_t x = mbedtls_get_unaligned_uint32(a + i) ^ mbedtls_get_unaligned_uint32(b + i); + mbedtls_put_unaligned_uint32(r + i, x); + } +#endif +#endif + for (; i < n; i++) { + r[i] = a[i] ^ b[i]; + } +} + +/* Fix MSVC C99 compatible issue + * MSVC support __func__ from visual studio 2015( 1900 ) + * Use MSVC predefine macro to avoid name check fail. + */ +#if (defined(_MSC_VER) && (_MSC_VER <= 1900)) +#define /*no-check-names*/ __func__ __FUNCTION__ +#endif + +/* Define `asm` for compilers which don't define it. */ +/* *INDENT-OFF* */ +#ifndef asm +#if defined(__IAR_SYSTEMS_ICC__) +#define asm __asm +#else +#define asm __asm__ +#endif +#endif +/* *INDENT-ON* */ + +/* + * Define the constraint used for read-only pointer operands to aarch64 asm. + * + * This is normally the usual "r", but for aarch64_32 (aka ILP32, + * as found in watchos), "p" is required to avoid warnings from clang. + * + * Note that clang does not recognise '+p' or '=p', and armclang + * does not recognise 'p' at all. Therefore, to update a pointer from + * aarch64 assembly, it is necessary to use something like: + * + * uintptr_t uptr = (uintptr_t) ptr; + * asm( "ldr x4, [%x0], #8" ... : "+r" (uptr) : : ) + * ptr = (void*) uptr; + * + * Note that the "x" in "%x0" is neccessary; writing "%0" will cause warnings. + */ +#if defined(__aarch64__) && defined(MBEDTLS_HAVE_ASM) +#if UINTPTR_MAX == 0xfffffffful +/* ILP32: Specify the pointer operand slightly differently, as per #7787. */ +#define MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT "p" +#elif UINTPTR_MAX == 0xfffffffffffffffful +/* Normal case (64-bit pointers): use "r" as the constraint for pointer operands to asm */ +#define MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT "r" +#else +#error "Unrecognised pointer size for aarch64" +#endif +#endif + +/* Always provide a static assert macro, so it can be used unconditionally. + * It will expand to nothing on some systems. + * Can be used outside functions (but don't add a trailing ';' in that case: + * the semicolon is included here to avoid triggering -Wextra-semi when + * MBEDTLS_STATIC_ASSERT() expands to nothing). + * Can't use the C11-style `defined(static_assert)` on FreeBSD, since it + * defines static_assert even with -std=c99, but then complains about it. + */ +#if defined(static_assert) && !defined(__FreeBSD__) +#define MBEDTLS_STATIC_ASSERT(expr, msg) static_assert(expr, msg); +#else +#define MBEDTLS_STATIC_ASSERT(expr, msg) +#endif + +/* Define compiler branch hints */ +#if defined(__has_builtin) +#if __has_builtin(__builtin_expect) +#define MBEDTLS_LIKELY(x) __builtin_expect(!!(x), 1) +#define MBEDTLS_UNLIKELY(x) __builtin_expect(!!(x), 0) +#endif +#endif +#if !defined(MBEDTLS_LIKELY) +#define MBEDTLS_LIKELY(x) x +#define MBEDTLS_UNLIKELY(x) x +#endif + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) && !defined(__clang__) \ + && !defined(__llvm__) && !defined(__INTEL_COMPILER) +/* Defined if the compiler really is gcc and not clang, etc */ +#define MBEDTLS_COMPILER_IS_GCC +#endif + +/* For gcc -Os, override with -O2 for a given function. + * + * This will not affect behaviour for other optimisation settings, e.g. -O0. + */ +#if defined(MBEDTLS_COMPILER_IS_GCC) && defined(__OPTIMIZE_SIZE__) +#define MBEDTLS_OPTIMIZE_FOR_PERFORMANCE __attribute__((optimize("-O2"))) +#else +#define MBEDTLS_OPTIMIZE_FOR_PERFORMANCE +#endif + +#endif /* MBEDTLS_LIBRARY_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time.c index 8b41aed..07b35bc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time.c @@ -1,273 +1,273 @@ -/** - * Constant-time functions - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * The following functions are implemented without using comparison operators, as those - * might be translated to branches by some compilers on some platforms. - */ - -#include -#include - -#include "common.h" -#include "constant_time_internal.h" -#include "mbedtls/constant_time.h" -#include "mbedtls/error.h" -#include "mbedtls/platform_util.h" - -#include - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) -#include "psa/crypto.h" -/* Define a local translating function to save code size by not using too many - * arguments in each translating place. */ -static int local_err_translation(psa_status_t status) -{ - return psa_status_to_mbedtls(status, psa_to_ssl_errors, - ARRAY_LENGTH(psa_to_ssl_errors), - psa_generic_status_to_mbedtls); -} -#define PSA_TO_MBEDTLS_ERR(status) local_err_translation(status) -#endif - -#if !defined(MBEDTLS_CT_ASM) -/* - * Define an object with the value zero, such that the compiler cannot prove that it - * has the value zero (because it is volatile, it "may be modified in ways unknown to - * the implementation"). - */ -volatile mbedtls_ct_uint_t mbedtls_ct_zero = 0; -#endif - -/* - * Define MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS where assembly is present to - * perform fast unaligned access to volatile data. - * - * This is needed because mbedtls_get_unaligned_uintXX etc don't support volatile - * memory accesses. - * - * Some of these definitions could be moved into alignment.h but for now they are - * only used here. - */ -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) && \ - ((defined(MBEDTLS_CT_ARM_ASM) && (UINTPTR_MAX == 0xfffffffful)) || \ - defined(MBEDTLS_CT_AARCH64_ASM)) -/* We check pointer sizes to avoid issues with them not matching register size requirements */ -#define MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS - -static inline uint32_t mbedtls_get_unaligned_volatile_uint32(volatile const unsigned char *p) -{ - /* This is UB, even where it's safe: - * return *((volatile uint32_t*)p); - * so instead the same thing is expressed in assembly below. - */ - uint32_t r; -#if defined(MBEDTLS_CT_ARM_ASM) - asm volatile ("ldr %0, [%1]" : "=r" (r) : "r" (p) :); -#elif defined(MBEDTLS_CT_AARCH64_ASM) - asm volatile ("ldr %w0, [%1]" : "=r" (r) : MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT(p) :); -#else -#error "No assembly defined for mbedtls_get_unaligned_volatile_uint32" -#endif - return r; -} -#endif /* defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) && - (defined(MBEDTLS_CT_ARM_ASM) || defined(MBEDTLS_CT_AARCH64_ASM)) */ - -int mbedtls_ct_memcmp(const void *a, - const void *b, - size_t n) -{ - size_t i = 0; - /* - * `A` and `B` are cast to volatile to ensure that the compiler - * generates code that always fully reads both buffers. - * Otherwise it could generate a test to exit early if `diff` has all - * bits set early in the loop. - */ - volatile const unsigned char *A = (volatile const unsigned char *) a; - volatile const unsigned char *B = (volatile const unsigned char *) b; - uint32_t diff = 0; - -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS) - for (; (i + 4) <= n; i += 4) { - uint32_t x = mbedtls_get_unaligned_volatile_uint32(A + i); - uint32_t y = mbedtls_get_unaligned_volatile_uint32(B + i); - diff |= x ^ y; - } -#endif - - for (; i < n; i++) { - /* Read volatile data in order before computing diff. - * This avoids IAR compiler warning: - * 'the order of volatile accesses is undefined ..' */ - unsigned char x = A[i], y = B[i]; - diff |= x ^ y; - } - - -#if (INT_MAX < INT32_MAX) - /* We don't support int smaller than 32-bits, but if someone tried to build - * with this configuration, there is a risk that, for differing data, the - * only bits set in diff are in the top 16-bits, and would be lost by a - * simple cast from uint32 to int. - * This would have significant security implications, so protect against it. */ -#error "mbedtls_ct_memcmp() requires minimum 32-bit ints" -#else - /* The bit-twiddling ensures that when we cast uint32_t to int, we are casting - * a value that is in the range 0..INT_MAX - a value larger than this would - * result in implementation defined behaviour. - * - * This ensures that the value returned by the function is non-zero iff - * diff is non-zero. - */ - return (int) ((diff & 0xffff) | (diff >> 16)); -#endif -} - -#if defined(MBEDTLS_NIST_KW_C) - -int mbedtls_ct_memcmp_partial(const void *a, - const void *b, - size_t n, - size_t skip_head, - size_t skip_tail) -{ - unsigned int diff = 0; - - volatile const unsigned char *A = (volatile const unsigned char *) a; - volatile const unsigned char *B = (volatile const unsigned char *) b; - - size_t valid_end = n - skip_tail; - - for (size_t i = 0; i < n; i++) { - unsigned char x = A[i], y = B[i]; - unsigned int d = x ^ y; - mbedtls_ct_condition_t valid = mbedtls_ct_bool_and(mbedtls_ct_uint_ge(i, skip_head), - mbedtls_ct_uint_lt(i, valid_end)); - diff |= mbedtls_ct_uint_if_else_0(valid, d); - } - - /* Since we go byte-by-byte, the only bits set will be in the bottom 8 bits, so the - * cast from uint to int is safe. */ - return (int) diff; -} - -#endif - -#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) - -void mbedtls_ct_memmove_left(void *start, size_t total, size_t offset) -{ - volatile unsigned char *buf = start; - for (size_t i = 0; i < total; i++) { - mbedtls_ct_condition_t no_op = mbedtls_ct_uint_gt(total - offset, i); - /* The first `total - offset` passes are a no-op. The last - * `offset` passes shift the data one byte to the left and - * zero out the last byte. */ - for (size_t n = 0; n < total - 1; n++) { - unsigned char current = buf[n]; - unsigned char next = buf[n+1]; - buf[n] = mbedtls_ct_uint_if(no_op, current, next); - } - buf[total-1] = mbedtls_ct_uint_if_else_0(no_op, buf[total-1]); - } -} - -#endif /* MBEDTLS_PKCS1_V15 && MBEDTLS_RSA_C && ! MBEDTLS_RSA_ALT */ - -void mbedtls_ct_memcpy_if(mbedtls_ct_condition_t condition, - unsigned char *dest, - const unsigned char *src1, - const unsigned char *src2, - size_t len) -{ -#if defined(MBEDTLS_CT_SIZE_64) - const uint64_t mask = (uint64_t) condition; - const uint64_t not_mask = (uint64_t) ~mbedtls_ct_compiler_opaque(condition); -#else - const uint32_t mask = (uint32_t) condition; - const uint32_t not_mask = (uint32_t) ~mbedtls_ct_compiler_opaque(condition); -#endif - - /* If src2 is NULL, setup src2 so that we read from the destination address. - * - * This means that if src2 == NULL && condition is false, the result will be a - * no-op because we read from dest and write the same data back into dest. - */ - if (src2 == NULL) { - src2 = dest; - } - - /* dest[i] = c1 == c2 ? src[i] : dest[i] */ - size_t i = 0; -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) -#if defined(MBEDTLS_CT_SIZE_64) - for (; (i + 8) <= len; i += 8) { - uint64_t a = mbedtls_get_unaligned_uint64(src1 + i) & mask; - uint64_t b = mbedtls_get_unaligned_uint64(src2 + i) & not_mask; - mbedtls_put_unaligned_uint64(dest + i, a | b); - } -#else - for (; (i + 4) <= len; i += 4) { - uint32_t a = mbedtls_get_unaligned_uint32(src1 + i) & mask; - uint32_t b = mbedtls_get_unaligned_uint32(src2 + i) & not_mask; - mbedtls_put_unaligned_uint32(dest + i, a | b); - } -#endif /* defined(MBEDTLS_CT_SIZE_64) */ -#endif /* MBEDTLS_EFFICIENT_UNALIGNED_ACCESS */ - for (; i < len; i++) { - dest[i] = (src1[i] & mask) | (src2[i] & not_mask); - } -} - -void mbedtls_ct_memcpy_offset(unsigned char *dest, - const unsigned char *src, - size_t offset, - size_t offset_min, - size_t offset_max, - size_t len) -{ - size_t offsetval; - - for (offsetval = offset_min; offsetval <= offset_max; offsetval++) { - mbedtls_ct_memcpy_if(mbedtls_ct_uint_eq(offsetval, offset), dest, src + offsetval, NULL, - len); - } -} - -#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) - -void mbedtls_ct_zeroize_if(mbedtls_ct_condition_t condition, void *buf, size_t len) -{ - uint32_t mask = (uint32_t) ~condition; - uint8_t *p = (uint8_t *) buf; - size_t i = 0; -#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) - for (; (i + 4) <= len; i += 4) { - mbedtls_put_unaligned_uint32((void *) (p + i), - mbedtls_get_unaligned_uint32((void *) (p + i)) & mask); - } -#endif - for (; i < len; i++) { - p[i] = p[i] & mask; - } -} - -#endif /* defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) */ +/** + * Constant-time functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * The following functions are implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ + +#include +#include + +#include "common.h" +#include "constant_time_internal.h" +#include "mbedtls/constant_time.h" +#include "mbedtls/error.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) +#include "psa/crypto.h" +/* Define a local translating function to save code size by not using too many + * arguments in each translating place. */ +static int local_err_translation(psa_status_t status) +{ + return psa_status_to_mbedtls(status, psa_to_ssl_errors, + ARRAY_LENGTH(psa_to_ssl_errors), + psa_generic_status_to_mbedtls); +} +#define PSA_TO_MBEDTLS_ERR(status) local_err_translation(status) +#endif + +#if !defined(MBEDTLS_CT_ASM) +/* + * Define an object with the value zero, such that the compiler cannot prove that it + * has the value zero (because it is volatile, it "may be modified in ways unknown to + * the implementation"). + */ +volatile mbedtls_ct_uint_t mbedtls_ct_zero = 0; +#endif + +/* + * Define MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS where assembly is present to + * perform fast unaligned access to volatile data. + * + * This is needed because mbedtls_get_unaligned_uintXX etc don't support volatile + * memory accesses. + * + * Some of these definitions could be moved into alignment.h but for now they are + * only used here. + */ +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) && \ + ((defined(MBEDTLS_CT_ARM_ASM) && (UINTPTR_MAX == 0xfffffffful)) || \ + defined(MBEDTLS_CT_AARCH64_ASM)) +/* We check pointer sizes to avoid issues with them not matching register size requirements */ +#define MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS + +static inline uint32_t mbedtls_get_unaligned_volatile_uint32(volatile const unsigned char *p) +{ + /* This is UB, even where it's safe: + * return *((volatile uint32_t*)p); + * so instead the same thing is expressed in assembly below. + */ + uint32_t r; +#if defined(MBEDTLS_CT_ARM_ASM) + asm volatile ("ldr %0, [%1]" : "=r" (r) : "r" (p) :); +#elif defined(MBEDTLS_CT_AARCH64_ASM) + asm volatile ("ldr %w0, [%1]" : "=r" (r) : MBEDTLS_ASM_AARCH64_PTR_CONSTRAINT(p) :); +#else +#error "No assembly defined for mbedtls_get_unaligned_volatile_uint32" +#endif + return r; +} +#endif /* defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) && + (defined(MBEDTLS_CT_ARM_ASM) || defined(MBEDTLS_CT_AARCH64_ASM)) */ + +int mbedtls_ct_memcmp(const void *a, + const void *b, + size_t n) +{ + size_t i = 0; + /* + * `A` and `B` are cast to volatile to ensure that the compiler + * generates code that always fully reads both buffers. + * Otherwise it could generate a test to exit early if `diff` has all + * bits set early in the loop. + */ + volatile const unsigned char *A = (volatile const unsigned char *) a; + volatile const unsigned char *B = (volatile const unsigned char *) b; + uint32_t diff = 0; + +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_VOLATILE_ACCESS) + for (; (i + 4) <= n; i += 4) { + uint32_t x = mbedtls_get_unaligned_volatile_uint32(A + i); + uint32_t y = mbedtls_get_unaligned_volatile_uint32(B + i); + diff |= x ^ y; + } +#endif + + for (; i < n; i++) { + /* Read volatile data in order before computing diff. + * This avoids IAR compiler warning: + * 'the order of volatile accesses is undefined ..' */ + unsigned char x = A[i], y = B[i]; + diff |= x ^ y; + } + + +#if (INT_MAX < INT32_MAX) + /* We don't support int smaller than 32-bits, but if someone tried to build + * with this configuration, there is a risk that, for differing data, the + * only bits set in diff are in the top 16-bits, and would be lost by a + * simple cast from uint32 to int. + * This would have significant security implications, so protect against it. */ +#error "mbedtls_ct_memcmp() requires minimum 32-bit ints" +#else + /* The bit-twiddling ensures that when we cast uint32_t to int, we are casting + * a value that is in the range 0..INT_MAX - a value larger than this would + * result in implementation defined behaviour. + * + * This ensures that the value returned by the function is non-zero iff + * diff is non-zero. + */ + return (int) ((diff & 0xffff) | (diff >> 16)); +#endif +} + +#if defined(MBEDTLS_NIST_KW_C) + +int mbedtls_ct_memcmp_partial(const void *a, + const void *b, + size_t n, + size_t skip_head, + size_t skip_tail) +{ + unsigned int diff = 0; + + volatile const unsigned char *A = (volatile const unsigned char *) a; + volatile const unsigned char *B = (volatile const unsigned char *) b; + + size_t valid_end = n - skip_tail; + + for (size_t i = 0; i < n; i++) { + unsigned char x = A[i], y = B[i]; + unsigned int d = x ^ y; + mbedtls_ct_condition_t valid = mbedtls_ct_bool_and(mbedtls_ct_uint_ge(i, skip_head), + mbedtls_ct_uint_lt(i, valid_end)); + diff |= mbedtls_ct_uint_if_else_0(valid, d); + } + + /* Since we go byte-by-byte, the only bits set will be in the bottom 8 bits, so the + * cast from uint to int is safe. */ + return (int) diff; +} + +#endif + +#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) + +void mbedtls_ct_memmove_left(void *start, size_t total, size_t offset) +{ + volatile unsigned char *buf = start; + for (size_t i = 0; i < total; i++) { + mbedtls_ct_condition_t no_op = mbedtls_ct_uint_gt(total - offset, i); + /* The first `total - offset` passes are a no-op. The last + * `offset` passes shift the data one byte to the left and + * zero out the last byte. */ + for (size_t n = 0; n < total - 1; n++) { + unsigned char current = buf[n]; + unsigned char next = buf[n+1]; + buf[n] = mbedtls_ct_uint_if(no_op, current, next); + } + buf[total-1] = mbedtls_ct_uint_if_else_0(no_op, buf[total-1]); + } +} + +#endif /* MBEDTLS_PKCS1_V15 && MBEDTLS_RSA_C && ! MBEDTLS_RSA_ALT */ + +void mbedtls_ct_memcpy_if(mbedtls_ct_condition_t condition, + unsigned char *dest, + const unsigned char *src1, + const unsigned char *src2, + size_t len) +{ +#if defined(MBEDTLS_CT_SIZE_64) + const uint64_t mask = (uint64_t) condition; + const uint64_t not_mask = (uint64_t) ~mbedtls_ct_compiler_opaque(condition); +#else + const uint32_t mask = (uint32_t) condition; + const uint32_t not_mask = (uint32_t) ~mbedtls_ct_compiler_opaque(condition); +#endif + + /* If src2 is NULL, setup src2 so that we read from the destination address. + * + * This means that if src2 == NULL && condition is false, the result will be a + * no-op because we read from dest and write the same data back into dest. + */ + if (src2 == NULL) { + src2 = dest; + } + + /* dest[i] = c1 == c2 ? src[i] : dest[i] */ + size_t i = 0; +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) +#if defined(MBEDTLS_CT_SIZE_64) + for (; (i + 8) <= len; i += 8) { + uint64_t a = mbedtls_get_unaligned_uint64(src1 + i) & mask; + uint64_t b = mbedtls_get_unaligned_uint64(src2 + i) & not_mask; + mbedtls_put_unaligned_uint64(dest + i, a | b); + } +#else + for (; (i + 4) <= len; i += 4) { + uint32_t a = mbedtls_get_unaligned_uint32(src1 + i) & mask; + uint32_t b = mbedtls_get_unaligned_uint32(src2 + i) & not_mask; + mbedtls_put_unaligned_uint32(dest + i, a | b); + } +#endif /* defined(MBEDTLS_CT_SIZE_64) */ +#endif /* MBEDTLS_EFFICIENT_UNALIGNED_ACCESS */ + for (; i < len; i++) { + dest[i] = (src1[i] & mask) | (src2[i] & not_mask); + } +} + +void mbedtls_ct_memcpy_offset(unsigned char *dest, + const unsigned char *src, + size_t offset, + size_t offset_min, + size_t offset_max, + size_t len) +{ + size_t offsetval; + + for (offsetval = offset_min; offsetval <= offset_max; offsetval++) { + mbedtls_ct_memcpy_if(mbedtls_ct_uint_eq(offsetval, offset), dest, src + offsetval, NULL, + len); + } +} + +#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) + +void mbedtls_ct_zeroize_if(mbedtls_ct_condition_t condition, void *buf, size_t len) +{ + uint32_t mask = (uint32_t) ~condition; + uint8_t *p = (uint8_t *) buf; + size_t i = 0; +#if defined(MBEDTLS_EFFICIENT_UNALIGNED_ACCESS) + for (; (i + 4) <= len; i += 4) { + mbedtls_put_unaligned_uint32((void *) (p + i), + mbedtls_get_unaligned_uint32((void *) (p + i)) & mask); + } +#endif + for (; i < len; i++) { + p[i] = p[i] & mask; + } +} + +#endif /* defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_impl.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_impl.h index 7759ac3..6b13f2a 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_impl.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_impl.h @@ -1,566 +1,566 @@ -/** - * Constant-time functions - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONSTANT_TIME_IMPL_H -#define MBEDTLS_CONSTANT_TIME_IMPL_H - -#include - -#include "common.h" - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -/* - * To improve readability of constant_time_internal.h, the static inline - * definitions are here, and constant_time_internal.h has only the declarations. - * - * This results in duplicate declarations of the form: - * static inline void f(); // from constant_time_internal.h - * static inline void f() { ... } // from constant_time_impl.h - * when constant_time_internal.h is included. - * - * This appears to behave as if the declaration-without-definition was not present - * (except for warnings if gcc -Wredundant-decls or similar is used). - * - * Disable -Wredundant-decls so that gcc does not warn about this. This is re-enabled - * at the bottom of this file. - */ -#ifdef __GNUC__ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wredundant-decls" -#endif - -/* Disable asm under Memsan because it confuses Memsan and generates false errors. - * - * We also disable under Valgrind by default, because it's more useful - * for Valgrind to test the plain C implementation. MBEDTLS_TEST_CONSTANT_FLOW_ASM //no-check-names - * may be set to permit building asm under Valgrind. - */ -#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) || \ - (defined(MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND) && !defined(MBEDTLS_TEST_CONSTANT_FLOW_ASM)) //no-check-names -#define MBEDTLS_CT_NO_ASM -#elif defined(__has_feature) -#if __has_feature(memory_sanitizer) -#define MBEDTLS_CT_NO_ASM -#endif -#endif - -/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */ -#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) && (!defined(__ARMCC_VERSION) || \ - __ARMCC_VERSION >= 6000000) && !defined(MBEDTLS_CT_NO_ASM) -#define MBEDTLS_CT_ASM -#if (defined(__arm__) || defined(__thumb__) || defined(__thumb2__)) -#define MBEDTLS_CT_ARM_ASM -#elif defined(__aarch64__) -#define MBEDTLS_CT_AARCH64_ASM -#elif defined(__amd64__) || defined(__x86_64__) -#define MBEDTLS_CT_X86_64_ASM -#elif defined(__i386__) -#define MBEDTLS_CT_X86_ASM -#endif -#endif - -#define MBEDTLS_CT_SIZE (sizeof(mbedtls_ct_uint_t) * 8) - - -/* ============================================================================ - * Core const-time primitives - */ - -/* Ensure that the compiler cannot know the value of x (i.e., cannot optimise - * based on its value) after this function is called. - * - * If we are not using assembly, this will be fairly inefficient, so its use - * should be minimised. - */ - -#if !defined(MBEDTLS_CT_ASM) -extern volatile mbedtls_ct_uint_t mbedtls_ct_zero; -#endif - -/** - * \brief Ensure that a value cannot be known at compile time. - * - * \param x The value to hide from the compiler. - * \return The same value that was passed in, such that the compiler - * cannot prove its value (even for calls of the form - * x = mbedtls_ct_compiler_opaque(1), x will be unknown). - * - * \note This is mainly used in constructing mbedtls_ct_condition_t - * values and performing operations over them, to ensure that - * there is no way for the compiler to ever know anything about - * the value of an mbedtls_ct_condition_t. - */ -static inline mbedtls_ct_uint_t mbedtls_ct_compiler_opaque(mbedtls_ct_uint_t x) -{ -#if defined(MBEDTLS_CT_ASM) - asm volatile ("" : [x] "+r" (x) :); - return x; -#else - return x ^ mbedtls_ct_zero; -#endif -} - -/* - * Selecting unified syntax is needed for gcc, and harmless on clang. - * - * This is needed because on Thumb 1, condition flags are always set, so - * e.g. "negs" is supported but "neg" is not (on Thumb 2, both exist). - * - * Under Thumb 1 unified syntax, only the "negs" form is accepted, and - * under divided syntax, only the "neg" form is accepted. clang only - * supports unified syntax. - * - * On Thumb 2 and Arm, both compilers are happy with the "s" suffix, - * although we don't actually care about setting the flags. - * - * For gcc, restore divided syntax afterwards - otherwise old versions of gcc - * seem to apply unified syntax globally, which breaks other asm code. - */ -#if !defined(__clang__) -#define RESTORE_ASM_SYNTAX ".syntax divided \n\t" -#else -#define RESTORE_ASM_SYNTAX -#endif - -/* Convert a number into a condition in constant time. */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool(mbedtls_ct_uint_t x) -{ - /* - * Define mask-generation code that, as far as possible, will not use branches or conditional instructions. - * - * For some platforms / type sizes, we define assembly to assure this. - * - * Otherwise, we define a plain C fallback which (in May 2023) does not get optimised into - * conditional instructions or branches by trunk clang, gcc, or MSVC v19. - */ -#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - mbedtls_ct_uint_t s; - asm volatile ("neg %x[s], %x[x] \n\t" - "orr %x[x], %x[s], %x[x] \n\t" - "asr %x[x], %x[x], 63 \n\t" - : - [s] "=&r" (s), - [x] "+&r" (x) - : - : - ); - return (mbedtls_ct_condition_t) x; -#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) - uint32_t s; - asm volatile (".syntax unified \n\t" - "negs %[s], %[x] \n\t" - "orrs %[x], %[x], %[s] \n\t" - "asrs %[x], %[x], #31 \n\t" - RESTORE_ASM_SYNTAX - : - [s] "=&l" (s), - [x] "+&l" (x) - : - : - "cc" /* clobbers flag bits */ - ); - return (mbedtls_ct_condition_t) x; -#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - uint64_t s; - asm volatile ("mov %[x], %[s] \n\t" - "neg %[s] \n\t" - "or %[x], %[s] \n\t" - "sar $63, %[s] \n\t" - : - [s] "=&a" (s) - : - [x] "D" (x) - : - ); - return (mbedtls_ct_condition_t) s; -#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) - uint32_t s; - asm volatile ("mov %[x], %[s] \n\t" - "neg %[s] \n\t" - "or %[s], %[x] \n\t" - "sar $31, %[x] \n\t" - : - [s] "=&c" (s), - [x] "+&a" (x) - : - : - ); - return (mbedtls_ct_condition_t) x; -#else - const mbedtls_ct_uint_t xo = mbedtls_ct_compiler_opaque(x); -#if defined(_MSC_VER) - /* MSVC has a warning about unary minus on unsigned, but this is - * well-defined and precisely what we want to do here */ -#pragma warning( push ) -#pragma warning( disable : 4146 ) -#endif - // y is negative (i.e., top bit set) iff x is non-zero - mbedtls_ct_int_t y = (-xo) | -(xo >> 1); - - // extract only the sign bit of y so that y == 1 (if x is non-zero) or 0 (if x is zero) - y = (((mbedtls_ct_uint_t) y) >> (MBEDTLS_CT_SIZE - 1)); - - // -y has all bits set (if x is non-zero), or all bits clear (if x is zero) - return (mbedtls_ct_condition_t) (-y); -#if defined(_MSC_VER) -#pragma warning( pop ) -#endif -#endif -} - -static inline mbedtls_ct_uint_t mbedtls_ct_if(mbedtls_ct_condition_t condition, - mbedtls_ct_uint_t if1, - mbedtls_ct_uint_t if0) -{ -#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - asm volatile ("and %x[if1], %x[if1], %x[condition] \n\t" - "mvn %x[condition], %x[condition] \n\t" - "and %x[condition], %x[condition], %x[if0] \n\t" - "orr %x[condition], %x[if1], %x[condition]" - : - [condition] "+&r" (condition), - [if1] "+&r" (if1) - : - [if0] "r" (if0) - : - ); - return (mbedtls_ct_uint_t) condition; -#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) - asm volatile (".syntax unified \n\t" - "ands %[if1], %[if1], %[condition] \n\t" - "mvns %[condition], %[condition] \n\t" - "ands %[condition], %[condition], %[if0] \n\t" - "orrs %[condition], %[if1], %[condition] \n\t" - RESTORE_ASM_SYNTAX - : - [condition] "+&l" (condition), - [if1] "+&l" (if1) - : - [if0] "l" (if0) - : - "cc" - ); - return (mbedtls_ct_uint_t) condition; -#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - asm volatile ("and %[condition], %[if1] \n\t" - "not %[condition] \n\t" - "and %[condition], %[if0] \n\t" - "or %[if1], %[if0] \n\t" - : - [condition] "+&D" (condition), - [if1] "+&S" (if1), - [if0] "+&a" (if0) - : - : - ); - return if0; -#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) - asm volatile ("and %[condition], %[if1] \n\t" - "not %[condition] \n\t" - "and %[if0], %[condition] \n\t" - "or %[condition], %[if1] \n\t" - : - [condition] "+&c" (condition), - [if1] "+&a" (if1) - : - [if0] "b" (if0) - : - ); - return if1; -#else - mbedtls_ct_condition_t not_cond = - (mbedtls_ct_condition_t) (~mbedtls_ct_compiler_opaque(condition)); - return (mbedtls_ct_uint_t) ((condition & if1) | (not_cond & if0)); -#endif -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_lt(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y) -{ -#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - uint64_t s1; - asm volatile ("eor %x[s1], %x[y], %x[x] \n\t" - "sub %x[x], %x[x], %x[y] \n\t" - "bic %x[x], %x[x], %x[s1] \n\t" - "and %x[s1], %x[s1], %x[y] \n\t" - "orr %x[s1], %x[x], %x[s1] \n\t" - "asr %x[x], %x[s1], 63" - : - [s1] "=&r" (s1), - [x] "+&r" (x) - : - [y] "r" (y) - : - ); - return (mbedtls_ct_condition_t) x; -#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) - uint32_t s1; - asm volatile ( - ".syntax unified \n\t" -#if defined(__thumb__) && !defined(__thumb2__) - "movs %[s1], %[x] \n\t" - "eors %[s1], %[s1], %[y] \n\t" -#else - "eors %[s1], %[x], %[y] \n\t" -#endif - "subs %[x], %[x], %[y] \n\t" - "bics %[x], %[x], %[s1] \n\t" - "ands %[y], %[s1], %[y] \n\t" - "orrs %[x], %[x], %[y] \n\t" - "asrs %[x], %[x], #31 \n\t" - RESTORE_ASM_SYNTAX - : - [s1] "=&l" (s1), - [x] "+&l" (x), - [y] "+&l" (y) - : - : - "cc" - ); - return (mbedtls_ct_condition_t) x; -#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) - uint64_t s; - asm volatile ("mov %[x], %[s] \n\t" - "xor %[y], %[s] \n\t" - "sub %[y], %[x] \n\t" - "and %[s], %[y] \n\t" - "not %[s] \n\t" - "and %[s], %[x] \n\t" - "or %[y], %[x] \n\t" - "sar $63, %[x] \n\t" - : - [s] "=&a" (s), - [x] "+&D" (x), - [y] "+&S" (y) - : - : - ); - return (mbedtls_ct_condition_t) x; -#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) - uint32_t s; - asm volatile ("mov %[x], %[s] \n\t" - "xor %[y], %[s] \n\t" - "sub %[y], %[x] \n\t" - "and %[s], %[y] \n\t" - "not %[s] \n\t" - "and %[s], %[x] \n\t" - "or %[y], %[x] \n\t" - "sar $31, %[x] \n\t" - : - [s] "=&b" (s), - [x] "+&a" (x), - [y] "+&c" (y) - : - : - ); - return (mbedtls_ct_condition_t) x; -#else - /* Ensure that the compiler cannot optimise the following operations over x and y, - * even if it knows the value of x and y. - */ - const mbedtls_ct_uint_t xo = mbedtls_ct_compiler_opaque(x); - const mbedtls_ct_uint_t yo = mbedtls_ct_compiler_opaque(y); - /* - * Check if the most significant bits (MSB) of the operands are different. - * cond is true iff the MSBs differ. - */ - mbedtls_ct_condition_t cond = mbedtls_ct_bool((xo ^ yo) >> (MBEDTLS_CT_SIZE - 1)); - - /* - * If the MSB are the same then the difference x-y will be negative (and - * have its MSB set to 1 during conversion to unsigned) if and only if x> (MBEDTLS_CT_SIZE - 1); - - // Convert to a condition (i.e., all bits set iff non-zero) - return mbedtls_ct_bool(ret); -#endif -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_ne(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y) -{ - /* diff = 0 if x == y, non-zero otherwise */ - const mbedtls_ct_uint_t diff = mbedtls_ct_compiler_opaque(x) ^ mbedtls_ct_compiler_opaque(y); - - /* all ones if x != y, 0 otherwise */ - return mbedtls_ct_bool(diff); -} - -static inline unsigned char mbedtls_ct_uchar_in_range_if(unsigned char low, - unsigned char high, - unsigned char c, - unsigned char t) -{ - const unsigned char co = (unsigned char) mbedtls_ct_compiler_opaque(c); - const unsigned char to = (unsigned char) mbedtls_ct_compiler_opaque(t); - - /* low_mask is: 0 if low <= c, 0x...ff if low > c */ - unsigned low_mask = ((unsigned) co - low) >> 8; - /* high_mask is: 0 if c <= high, 0x...ff if c > high */ - unsigned high_mask = ((unsigned) high - co) >> 8; - - return (unsigned char) (~(low_mask | high_mask)) & to; -} - -/* ============================================================================ - * Everything below here is trivial wrapper functions - */ - -static inline size_t mbedtls_ct_size_if(mbedtls_ct_condition_t condition, - size_t if1, - size_t if0) -{ - return (size_t) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, (mbedtls_ct_uint_t) if0); -} - -static inline unsigned mbedtls_ct_uint_if(mbedtls_ct_condition_t condition, - unsigned if1, - unsigned if0) -{ - return (unsigned) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, (mbedtls_ct_uint_t) if0); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_if(mbedtls_ct_condition_t condition, - mbedtls_ct_condition_t if1, - mbedtls_ct_condition_t if0) -{ - return (mbedtls_ct_condition_t) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, - (mbedtls_ct_uint_t) if0); -} - -#if defined(MBEDTLS_BIGNUM_C) - -static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if(mbedtls_ct_condition_t condition, - mbedtls_mpi_uint if1, - mbedtls_mpi_uint if0) -{ - return (mbedtls_mpi_uint) mbedtls_ct_if(condition, - (mbedtls_ct_uint_t) if1, - (mbedtls_ct_uint_t) if0); -} - -#endif - -static inline size_t mbedtls_ct_size_if_else_0(mbedtls_ct_condition_t condition, size_t if1) -{ - return (size_t) (condition & if1); -} - -static inline unsigned mbedtls_ct_uint_if_else_0(mbedtls_ct_condition_t condition, unsigned if1) -{ - return (unsigned) (condition & if1); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_if_else_0(mbedtls_ct_condition_t condition, - mbedtls_ct_condition_t if1) -{ - return (mbedtls_ct_condition_t) (condition & if1); -} - -#if defined(MBEDTLS_BIGNUM_C) - -static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if_else_0(mbedtls_ct_condition_t condition, - mbedtls_mpi_uint if1) -{ - return (mbedtls_mpi_uint) (condition & if1); -} - -#endif /* MBEDTLS_BIGNUM_C */ - -static inline int mbedtls_ct_error_if(mbedtls_ct_condition_t condition, int if1, int if0) -{ - /* Coverting int -> uint -> int here is safe, because we require if1 and if0 to be - * in the range -32767..0, and we require 32-bit int and uint types. - * - * This means that (0 <= -if0 < INT_MAX), so negating if0 is safe, and similarly for - * converting back to int. - */ - return -((int) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) (-if1), - (mbedtls_ct_uint_t) (-if0))); -} - -static inline int mbedtls_ct_error_if_else_0(mbedtls_ct_condition_t condition, int if1) -{ - return -((int) (condition & (-if1))); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_eq(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y) -{ - return ~mbedtls_ct_uint_ne(x, y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_gt(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y) -{ - return mbedtls_ct_uint_lt(y, x); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_ge(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y) -{ - return ~mbedtls_ct_uint_lt(x, y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_uint_le(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y) -{ - return ~mbedtls_ct_uint_gt(x, y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_ne(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y) -{ - return (mbedtls_ct_condition_t) (x ^ y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_and(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y) -{ - return (mbedtls_ct_condition_t) (x & y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_or(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y) -{ - return (mbedtls_ct_condition_t) (x | y); -} - -static inline mbedtls_ct_condition_t mbedtls_ct_bool_not(mbedtls_ct_condition_t x) -{ - return (mbedtls_ct_condition_t) (~x); -} - -#ifdef __GNUC__ -/* Restore warnings for -Wredundant-decls on gcc */ - #pragma GCC diagnostic pop -#endif - -#endif /* MBEDTLS_CONSTANT_TIME_IMPL_H */ +/** + * Constant-time functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONSTANT_TIME_IMPL_H +#define MBEDTLS_CONSTANT_TIME_IMPL_H + +#include + +#include "common.h" + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +/* + * To improve readability of constant_time_internal.h, the static inline + * definitions are here, and constant_time_internal.h has only the declarations. + * + * This results in duplicate declarations of the form: + * static inline void f(); // from constant_time_internal.h + * static inline void f() { ... } // from constant_time_impl.h + * when constant_time_internal.h is included. + * + * This appears to behave as if the declaration-without-definition was not present + * (except for warnings if gcc -Wredundant-decls or similar is used). + * + * Disable -Wredundant-decls so that gcc does not warn about this. This is re-enabled + * at the bottom of this file. + */ +#ifdef __GNUC__ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wredundant-decls" +#endif + +/* Disable asm under Memsan because it confuses Memsan and generates false errors. + * + * We also disable under Valgrind by default, because it's more useful + * for Valgrind to test the plain C implementation. MBEDTLS_TEST_CONSTANT_FLOW_ASM //no-check-names + * may be set to permit building asm under Valgrind. + */ +#if defined(MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN) || \ + (defined(MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND) && !defined(MBEDTLS_TEST_CONSTANT_FLOW_ASM)) //no-check-names +#define MBEDTLS_CT_NO_ASM +#elif defined(__has_feature) +#if __has_feature(memory_sanitizer) +#define MBEDTLS_CT_NO_ASM +#endif +#endif + +/* armcc5 --gnu defines __GNUC__ but doesn't support GNU's extended asm */ +#if defined(MBEDTLS_HAVE_ASM) && defined(__GNUC__) && (!defined(__ARMCC_VERSION) || \ + __ARMCC_VERSION >= 6000000) && !defined(MBEDTLS_CT_NO_ASM) +#define MBEDTLS_CT_ASM +#if (defined(__arm__) || defined(__thumb__) || defined(__thumb2__)) +#define MBEDTLS_CT_ARM_ASM +#elif defined(__aarch64__) +#define MBEDTLS_CT_AARCH64_ASM +#elif defined(__amd64__) || defined(__x86_64__) +#define MBEDTLS_CT_X86_64_ASM +#elif defined(__i386__) +#define MBEDTLS_CT_X86_ASM +#endif +#endif + +#define MBEDTLS_CT_SIZE (sizeof(mbedtls_ct_uint_t) * 8) + + +/* ============================================================================ + * Core const-time primitives + */ + +/* Ensure that the compiler cannot know the value of x (i.e., cannot optimise + * based on its value) after this function is called. + * + * If we are not using assembly, this will be fairly inefficient, so its use + * should be minimised. + */ + +#if !defined(MBEDTLS_CT_ASM) +extern volatile mbedtls_ct_uint_t mbedtls_ct_zero; +#endif + +/** + * \brief Ensure that a value cannot be known at compile time. + * + * \param x The value to hide from the compiler. + * \return The same value that was passed in, such that the compiler + * cannot prove its value (even for calls of the form + * x = mbedtls_ct_compiler_opaque(1), x will be unknown). + * + * \note This is mainly used in constructing mbedtls_ct_condition_t + * values and performing operations over them, to ensure that + * there is no way for the compiler to ever know anything about + * the value of an mbedtls_ct_condition_t. + */ +static inline mbedtls_ct_uint_t mbedtls_ct_compiler_opaque(mbedtls_ct_uint_t x) +{ +#if defined(MBEDTLS_CT_ASM) + asm volatile ("" : [x] "+r" (x) :); + return x; +#else + return x ^ mbedtls_ct_zero; +#endif +} + +/* + * Selecting unified syntax is needed for gcc, and harmless on clang. + * + * This is needed because on Thumb 1, condition flags are always set, so + * e.g. "negs" is supported but "neg" is not (on Thumb 2, both exist). + * + * Under Thumb 1 unified syntax, only the "negs" form is accepted, and + * under divided syntax, only the "neg" form is accepted. clang only + * supports unified syntax. + * + * On Thumb 2 and Arm, both compilers are happy with the "s" suffix, + * although we don't actually care about setting the flags. + * + * For gcc, restore divided syntax afterwards - otherwise old versions of gcc + * seem to apply unified syntax globally, which breaks other asm code. + */ +#if !defined(__clang__) +#define RESTORE_ASM_SYNTAX ".syntax divided \n\t" +#else +#define RESTORE_ASM_SYNTAX +#endif + +/* Convert a number into a condition in constant time. */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool(mbedtls_ct_uint_t x) +{ + /* + * Define mask-generation code that, as far as possible, will not use branches or conditional instructions. + * + * For some platforms / type sizes, we define assembly to assure this. + * + * Otherwise, we define a plain C fallback which (in May 2023) does not get optimised into + * conditional instructions or branches by trunk clang, gcc, or MSVC v19. + */ +#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + mbedtls_ct_uint_t s; + asm volatile ("neg %x[s], %x[x] \n\t" + "orr %x[x], %x[s], %x[x] \n\t" + "asr %x[x], %x[x], 63 \n\t" + : + [s] "=&r" (s), + [x] "+&r" (x) + : + : + ); + return (mbedtls_ct_condition_t) x; +#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) + uint32_t s; + asm volatile (".syntax unified \n\t" + "negs %[s], %[x] \n\t" + "orrs %[x], %[x], %[s] \n\t" + "asrs %[x], %[x], #31 \n\t" + RESTORE_ASM_SYNTAX + : + [s] "=&l" (s), + [x] "+&l" (x) + : + : + "cc" /* clobbers flag bits */ + ); + return (mbedtls_ct_condition_t) x; +#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + uint64_t s; + asm volatile ("mov %[x], %[s] \n\t" + "neg %[s] \n\t" + "or %[x], %[s] \n\t" + "sar $63, %[s] \n\t" + : + [s] "=&a" (s) + : + [x] "D" (x) + : + ); + return (mbedtls_ct_condition_t) s; +#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) + uint32_t s; + asm volatile ("mov %[x], %[s] \n\t" + "neg %[s] \n\t" + "or %[s], %[x] \n\t" + "sar $31, %[x] \n\t" + : + [s] "=&c" (s), + [x] "+&a" (x) + : + : + ); + return (mbedtls_ct_condition_t) x; +#else + const mbedtls_ct_uint_t xo = mbedtls_ct_compiler_opaque(x); +#if defined(_MSC_VER) + /* MSVC has a warning about unary minus on unsigned, but this is + * well-defined and precisely what we want to do here */ +#pragma warning( push ) +#pragma warning( disable : 4146 ) +#endif + // y is negative (i.e., top bit set) iff x is non-zero + mbedtls_ct_int_t y = (-xo) | -(xo >> 1); + + // extract only the sign bit of y so that y == 1 (if x is non-zero) or 0 (if x is zero) + y = (((mbedtls_ct_uint_t) y) >> (MBEDTLS_CT_SIZE - 1)); + + // -y has all bits set (if x is non-zero), or all bits clear (if x is zero) + return (mbedtls_ct_condition_t) (-y); +#if defined(_MSC_VER) +#pragma warning( pop ) +#endif +#endif +} + +static inline mbedtls_ct_uint_t mbedtls_ct_if(mbedtls_ct_condition_t condition, + mbedtls_ct_uint_t if1, + mbedtls_ct_uint_t if0) +{ +#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + asm volatile ("and %x[if1], %x[if1], %x[condition] \n\t" + "mvn %x[condition], %x[condition] \n\t" + "and %x[condition], %x[condition], %x[if0] \n\t" + "orr %x[condition], %x[if1], %x[condition]" + : + [condition] "+&r" (condition), + [if1] "+&r" (if1) + : + [if0] "r" (if0) + : + ); + return (mbedtls_ct_uint_t) condition; +#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) + asm volatile (".syntax unified \n\t" + "ands %[if1], %[if1], %[condition] \n\t" + "mvns %[condition], %[condition] \n\t" + "ands %[condition], %[condition], %[if0] \n\t" + "orrs %[condition], %[if1], %[condition] \n\t" + RESTORE_ASM_SYNTAX + : + [condition] "+&l" (condition), + [if1] "+&l" (if1) + : + [if0] "l" (if0) + : + "cc" + ); + return (mbedtls_ct_uint_t) condition; +#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + asm volatile ("and %[condition], %[if1] \n\t" + "not %[condition] \n\t" + "and %[condition], %[if0] \n\t" + "or %[if1], %[if0] \n\t" + : + [condition] "+&D" (condition), + [if1] "+&S" (if1), + [if0] "+&a" (if0) + : + : + ); + return if0; +#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) + asm volatile ("and %[condition], %[if1] \n\t" + "not %[condition] \n\t" + "and %[if0], %[condition] \n\t" + "or %[condition], %[if1] \n\t" + : + [condition] "+&c" (condition), + [if1] "+&a" (if1) + : + [if0] "b" (if0) + : + ); + return if1; +#else + mbedtls_ct_condition_t not_cond = + (mbedtls_ct_condition_t) (~mbedtls_ct_compiler_opaque(condition)); + return (mbedtls_ct_uint_t) ((condition & if1) | (not_cond & if0)); +#endif +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_lt(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y) +{ +#if defined(MBEDTLS_CT_AARCH64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + uint64_t s1; + asm volatile ("eor %x[s1], %x[y], %x[x] \n\t" + "sub %x[x], %x[x], %x[y] \n\t" + "bic %x[x], %x[x], %x[s1] \n\t" + "and %x[s1], %x[s1], %x[y] \n\t" + "orr %x[s1], %x[x], %x[s1] \n\t" + "asr %x[x], %x[s1], 63" + : + [s1] "=&r" (s1), + [x] "+&r" (x) + : + [y] "r" (y) + : + ); + return (mbedtls_ct_condition_t) x; +#elif defined(MBEDTLS_CT_ARM_ASM) && defined(MBEDTLS_CT_SIZE_32) + uint32_t s1; + asm volatile ( + ".syntax unified \n\t" +#if defined(__thumb__) && !defined(__thumb2__) + "movs %[s1], %[x] \n\t" + "eors %[s1], %[s1], %[y] \n\t" +#else + "eors %[s1], %[x], %[y] \n\t" +#endif + "subs %[x], %[x], %[y] \n\t" + "bics %[x], %[x], %[s1] \n\t" + "ands %[y], %[s1], %[y] \n\t" + "orrs %[x], %[x], %[y] \n\t" + "asrs %[x], %[x], #31 \n\t" + RESTORE_ASM_SYNTAX + : + [s1] "=&l" (s1), + [x] "+&l" (x), + [y] "+&l" (y) + : + : + "cc" + ); + return (mbedtls_ct_condition_t) x; +#elif defined(MBEDTLS_CT_X86_64_ASM) && (defined(MBEDTLS_CT_SIZE_32) || defined(MBEDTLS_CT_SIZE_64)) + uint64_t s; + asm volatile ("mov %[x], %[s] \n\t" + "xor %[y], %[s] \n\t" + "sub %[y], %[x] \n\t" + "and %[s], %[y] \n\t" + "not %[s] \n\t" + "and %[s], %[x] \n\t" + "or %[y], %[x] \n\t" + "sar $63, %[x] \n\t" + : + [s] "=&a" (s), + [x] "+&D" (x), + [y] "+&S" (y) + : + : + ); + return (mbedtls_ct_condition_t) x; +#elif defined(MBEDTLS_CT_X86_ASM) && defined(MBEDTLS_CT_SIZE_32) + uint32_t s; + asm volatile ("mov %[x], %[s] \n\t" + "xor %[y], %[s] \n\t" + "sub %[y], %[x] \n\t" + "and %[s], %[y] \n\t" + "not %[s] \n\t" + "and %[s], %[x] \n\t" + "or %[y], %[x] \n\t" + "sar $31, %[x] \n\t" + : + [s] "=&b" (s), + [x] "+&a" (x), + [y] "+&c" (y) + : + : + ); + return (mbedtls_ct_condition_t) x; +#else + /* Ensure that the compiler cannot optimise the following operations over x and y, + * even if it knows the value of x and y. + */ + const mbedtls_ct_uint_t xo = mbedtls_ct_compiler_opaque(x); + const mbedtls_ct_uint_t yo = mbedtls_ct_compiler_opaque(y); + /* + * Check if the most significant bits (MSB) of the operands are different. + * cond is true iff the MSBs differ. + */ + mbedtls_ct_condition_t cond = mbedtls_ct_bool((xo ^ yo) >> (MBEDTLS_CT_SIZE - 1)); + + /* + * If the MSB are the same then the difference x-y will be negative (and + * have its MSB set to 1 during conversion to unsigned) if and only if x> (MBEDTLS_CT_SIZE - 1); + + // Convert to a condition (i.e., all bits set iff non-zero) + return mbedtls_ct_bool(ret); +#endif +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_ne(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y) +{ + /* diff = 0 if x == y, non-zero otherwise */ + const mbedtls_ct_uint_t diff = mbedtls_ct_compiler_opaque(x) ^ mbedtls_ct_compiler_opaque(y); + + /* all ones if x != y, 0 otherwise */ + return mbedtls_ct_bool(diff); +} + +static inline unsigned char mbedtls_ct_uchar_in_range_if(unsigned char low, + unsigned char high, + unsigned char c, + unsigned char t) +{ + const unsigned char co = (unsigned char) mbedtls_ct_compiler_opaque(c); + const unsigned char to = (unsigned char) mbedtls_ct_compiler_opaque(t); + + /* low_mask is: 0 if low <= c, 0x...ff if low > c */ + unsigned low_mask = ((unsigned) co - low) >> 8; + /* high_mask is: 0 if c <= high, 0x...ff if c > high */ + unsigned high_mask = ((unsigned) high - co) >> 8; + + return (unsigned char) (~(low_mask | high_mask)) & to; +} + +/* ============================================================================ + * Everything below here is trivial wrapper functions + */ + +static inline size_t mbedtls_ct_size_if(mbedtls_ct_condition_t condition, + size_t if1, + size_t if0) +{ + return (size_t) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, (mbedtls_ct_uint_t) if0); +} + +static inline unsigned mbedtls_ct_uint_if(mbedtls_ct_condition_t condition, + unsigned if1, + unsigned if0) +{ + return (unsigned) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, (mbedtls_ct_uint_t) if0); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_if(mbedtls_ct_condition_t condition, + mbedtls_ct_condition_t if1, + mbedtls_ct_condition_t if0) +{ + return (mbedtls_ct_condition_t) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) if1, + (mbedtls_ct_uint_t) if0); +} + +#if defined(MBEDTLS_BIGNUM_C) + +static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if(mbedtls_ct_condition_t condition, + mbedtls_mpi_uint if1, + mbedtls_mpi_uint if0) +{ + return (mbedtls_mpi_uint) mbedtls_ct_if(condition, + (mbedtls_ct_uint_t) if1, + (mbedtls_ct_uint_t) if0); +} + +#endif + +static inline size_t mbedtls_ct_size_if_else_0(mbedtls_ct_condition_t condition, size_t if1) +{ + return (size_t) (condition & if1); +} + +static inline unsigned mbedtls_ct_uint_if_else_0(mbedtls_ct_condition_t condition, unsigned if1) +{ + return (unsigned) (condition & if1); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_if_else_0(mbedtls_ct_condition_t condition, + mbedtls_ct_condition_t if1) +{ + return (mbedtls_ct_condition_t) (condition & if1); +} + +#if defined(MBEDTLS_BIGNUM_C) + +static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if_else_0(mbedtls_ct_condition_t condition, + mbedtls_mpi_uint if1) +{ + return (mbedtls_mpi_uint) (condition & if1); +} + +#endif /* MBEDTLS_BIGNUM_C */ + +static inline int mbedtls_ct_error_if(mbedtls_ct_condition_t condition, int if1, int if0) +{ + /* Coverting int -> uint -> int here is safe, because we require if1 and if0 to be + * in the range -32767..0, and we require 32-bit int and uint types. + * + * This means that (0 <= -if0 < INT_MAX), so negating if0 is safe, and similarly for + * converting back to int. + */ + return -((int) mbedtls_ct_if(condition, (mbedtls_ct_uint_t) (-if1), + (mbedtls_ct_uint_t) (-if0))); +} + +static inline int mbedtls_ct_error_if_else_0(mbedtls_ct_condition_t condition, int if1) +{ + return -((int) (condition & (-if1))); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_eq(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y) +{ + return ~mbedtls_ct_uint_ne(x, y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_gt(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y) +{ + return mbedtls_ct_uint_lt(y, x); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_ge(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y) +{ + return ~mbedtls_ct_uint_lt(x, y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_uint_le(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y) +{ + return ~mbedtls_ct_uint_gt(x, y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_ne(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y) +{ + return (mbedtls_ct_condition_t) (x ^ y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_and(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y) +{ + return (mbedtls_ct_condition_t) (x & y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_or(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y) +{ + return (mbedtls_ct_condition_t) (x | y); +} + +static inline mbedtls_ct_condition_t mbedtls_ct_bool_not(mbedtls_ct_condition_t x) +{ + return (mbedtls_ct_condition_t) (~x); +} + +#ifdef __GNUC__ +/* Restore warnings for -Wredundant-decls on gcc */ + #pragma GCC diagnostic pop +#endif + +#endif /* MBEDTLS_CONSTANT_TIME_IMPL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_internal.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_internal.h index cc26edc..e95632d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/constant_time_internal.h @@ -1,591 +1,591 @@ -/** - * Constant-time functions - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_CONSTANT_TIME_INTERNAL_H -#define MBEDTLS_CONSTANT_TIME_INTERNAL_H - -#include -#include - -#include "common.h" - -#if defined(MBEDTLS_BIGNUM_C) -#include "mbedtls/bignum.h" -#endif - -/* The constant-time interface provides various operations that are likely - * to result in constant-time code that does not branch or use conditional - * instructions for secret data (for secret pointers, this also applies to - * the data pointed to). - * - * It has three main parts: - * - * - boolean operations - * These are all named mbedtls_ct__. - * They operate over and return mbedtls_ct_condition_t. - * All arguments are considered secret. - * example: bool x = y | z => x = mbedtls_ct_bool_or(y, z) - * example: bool x = y == z => x = mbedtls_ct_uint_eq(y, z) - * - * - conditional data selection - * These are all named mbedtls_ct__if and mbedtls_ct__if_else_0 - * All arguments are considered secret. - * example: size_t a = x ? b : c => a = mbedtls_ct_size_if(x, b, c) - * example: unsigned a = x ? b : 0 => a = mbedtls_ct_uint_if_else_0(x, b) - * - * - block memory operations - * Only some arguments are considered secret, as documented for each - * function. - * example: if (x) memcpy(...) => mbedtls_ct_memcpy_if(x, ...) - * - * mbedtls_ct_condition_t must be treated as opaque and only created and - * manipulated via the functions in this header. The compiler should never - * be able to prove anything about its value at compile-time. - * - * mbedtls_ct_uint_t is an unsigned integer type over which constant time - * operations may be performed via the functions in this header. It is as big - * as the larger of size_t and mbedtls_mpi_uint, i.e. it is safe to cast - * to/from "unsigned int", "size_t", and "mbedtls_mpi_uint" (and any other - * not-larger integer types). - * - * For Arm (32-bit, 64-bit and Thumb), x86 and x86-64, assembly implementations - * are used to ensure that the generated code is constant time. For other - * architectures, it uses a plain C fallback designed to yield constant-time code - * (this has been observed to be constant-time on latest gcc, clang and MSVC - * as of May 2023). - * - * For readability, the static inline definitions are separated out into - * constant_time_impl.h. - */ - -#if (SIZE_MAX > 0xffffffffffffffffULL) -/* Pointer size > 64-bit */ -typedef size_t mbedtls_ct_condition_t; -typedef size_t mbedtls_ct_uint_t; -typedef ptrdiff_t mbedtls_ct_int_t; -#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(SIZE_MAX)) -#elif (SIZE_MAX > 0xffffffff) || defined(MBEDTLS_HAVE_INT64) -/* 32-bit < pointer size <= 64-bit, or 64-bit MPI */ -typedef uint64_t mbedtls_ct_condition_t; -typedef uint64_t mbedtls_ct_uint_t; -typedef int64_t mbedtls_ct_int_t; -#define MBEDTLS_CT_SIZE_64 -#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(UINT64_MAX)) -#else -/* Pointer size <= 32-bit, and no 64-bit MPIs */ -typedef uint32_t mbedtls_ct_condition_t; -typedef uint32_t mbedtls_ct_uint_t; -typedef int32_t mbedtls_ct_int_t; -#define MBEDTLS_CT_SIZE_32 -#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(UINT32_MAX)) -#endif -#define MBEDTLS_CT_FALSE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(0)) - -/* ============================================================================ - * Boolean operations - */ - -/** Convert a number into a mbedtls_ct_condition_t. - * - * \param x Number to convert. - * - * \return MBEDTLS_CT_TRUE if \p x != 0, or MBEDTLS_CT_FALSE if \p x == 0 - * - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool(mbedtls_ct_uint_t x); - -/** Boolean "not equal" operation. - * - * Functionally equivalent to: - * - * \p x != \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x != \p y, otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_ne(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y); - -/** Boolean "equals" operation. - * - * Functionally equivalent to: - * - * \p x == \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x == \p y, otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_eq(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y); - -/** Boolean "less than" operation. - * - * Functionally equivalent to: - * - * \p x < \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x < \p y, otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_lt(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y); - -/** Boolean "greater than" operation. - * - * Functionally equivalent to: - * - * \p x > \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x > \p y, otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_gt(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y); - -/** Boolean "greater or equal" operation. - * - * Functionally equivalent to: - * - * \p x >= \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x >= \p y, - * otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_ge(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y); - -/** Boolean "less than or equal" operation. - * - * Functionally equivalent to: - * - * \p x <= \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x <= \p y, - * otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_uint_le(mbedtls_ct_uint_t x, - mbedtls_ct_uint_t y); - -/** Boolean not-equals operation. - * - * Functionally equivalent to: - * - * \p x != \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \note This is more efficient than mbedtls_ct_uint_ne if both arguments are - * mbedtls_ct_condition_t. - * - * \return MBEDTLS_CT_TRUE if \p x != \p y, - * otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_ne(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y); - -/** Boolean "and" operation. - * - * Functionally equivalent to: - * - * \p x && \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x && \p y, - * otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_and(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y); - -/** Boolean "or" operation. - * - * Functionally equivalent to: - * - * \p x || \p y - * - * \param x The first value to analyze. - * \param y The second value to analyze. - * - * \return MBEDTLS_CT_TRUE if \p x || \p y, - * otherwise MBEDTLS_CT_FALSE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_or(mbedtls_ct_condition_t x, - mbedtls_ct_condition_t y); - -/** Boolean "not" operation. - * - * Functionally equivalent to: - * - * ! \p x - * - * \param x The value to invert - * - * \return MBEDTLS_CT_FALSE if \p x, otherwise MBEDTLS_CT_TRUE. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_not(mbedtls_ct_condition_t x); - - -/* ============================================================================ - * Data selection operations - */ - -/** Choose between two size_t values. - * - * Functionally equivalent to: - * - * condition ? if1 : if0. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. - */ -static inline size_t mbedtls_ct_size_if(mbedtls_ct_condition_t condition, - size_t if1, - size_t if0); - -/** Choose between two unsigned values. - * - * Functionally equivalent to: - * - * condition ? if1 : if0. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. - */ -static inline unsigned mbedtls_ct_uint_if(mbedtls_ct_condition_t condition, - unsigned if1, - unsigned if0); - -/** Choose between two mbedtls_ct_condition_t values. - * - * Functionally equivalent to: - * - * condition ? if1 : if0. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_if(mbedtls_ct_condition_t condition, - mbedtls_ct_condition_t if1, - mbedtls_ct_condition_t if0); - -#if defined(MBEDTLS_BIGNUM_C) - -/** Choose between two mbedtls_mpi_uint values. - * - * Functionally equivalent to: - * - * condition ? if1 : if0. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. - */ -static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if(mbedtls_ct_condition_t condition, \ - mbedtls_mpi_uint if1, \ - mbedtls_mpi_uint if0); - -#endif - -/** Choose between an unsigned value and 0. - * - * Functionally equivalent to: - * - * condition ? if1 : 0. - * - * Functionally equivalent to mbedtls_ct_uint_if(condition, if1, 0) but - * results in smaller code size. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. - */ -static inline unsigned mbedtls_ct_uint_if_else_0(mbedtls_ct_condition_t condition, unsigned if1); - -/** Choose between an mbedtls_ct_condition_t and 0. - * - * Functionally equivalent to: - * - * condition ? if1 : 0. - * - * Functionally equivalent to mbedtls_ct_bool_if(condition, if1, 0) but - * results in smaller code size. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. - */ -static inline mbedtls_ct_condition_t mbedtls_ct_bool_if_else_0(mbedtls_ct_condition_t condition, - mbedtls_ct_condition_t if1); - -/** Choose between a size_t value and 0. - * - * Functionally equivalent to: - * - * condition ? if1 : 0. - * - * Functionally equivalent to mbedtls_ct_size_if(condition, if1, 0) but - * results in smaller code size. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. - */ -static inline size_t mbedtls_ct_size_if_else_0(mbedtls_ct_condition_t condition, size_t if1); - -#if defined(MBEDTLS_BIGNUM_C) - -/** Choose between an mbedtls_mpi_uint value and 0. - * - * Functionally equivalent to: - * - * condition ? if1 : 0. - * - * Functionally equivalent to mbedtls_ct_mpi_uint_if(condition, if1, 0) but - * results in smaller code size. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. - */ -static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if_else_0(mbedtls_ct_condition_t condition, - mbedtls_mpi_uint if1); - -#endif - -/** Constant-flow char selection - * - * \param low Secret. Bottom of range - * \param high Secret. Top of range - * \param c Secret. Value to compare to range - * \param t Secret. Value to return, if in range - * - * \return \p t if \p low <= \p c <= \p high, 0 otherwise. - */ -static inline unsigned char mbedtls_ct_uchar_in_range_if(unsigned char low, - unsigned char high, - unsigned char c, - unsigned char t); - -/** Choose between two error values. The values must be in the range [-32767..0]. - * - * Functionally equivalent to: - * - * condition ? if1 : if0. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. - */ -static inline int mbedtls_ct_error_if(mbedtls_ct_condition_t condition, int if1, int if0); - -/** Choose between an error value and 0. The error value must be in the range [-32767..0]. - * - * Functionally equivalent to: - * - * condition ? if1 : 0. - * - * Functionally equivalent to mbedtls_ct_error_if(condition, if1, 0) but - * results in smaller code size. - * - * \param condition Condition to test. - * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. - * - * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. - */ -static inline int mbedtls_ct_error_if_else_0(mbedtls_ct_condition_t condition, int if1); - -/* ============================================================================ - * Block memory operations - */ - -#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) - -/** Conditionally set a block of memory to zero. - * - * Regardless of the condition, every byte will be read once and written to - * once. - * - * \param condition Secret. Condition to test. - * \param buf Secret. Pointer to the start of the buffer. - * \param len Number of bytes to set to zero. - * - * \warning Unlike mbedtls_platform_zeroize, this does not have the same guarantees - * about not being optimised away if the memory is never read again. - */ -void mbedtls_ct_zeroize_if(mbedtls_ct_condition_t condition, void *buf, size_t len); - -/** Shift some data towards the left inside a buffer. - * - * Functionally equivalent to: - * - * memmove(start, start + offset, total - offset); - * memset(start + (total - offset), 0, offset); - * - * Timing independence comes at the expense of performance. - * - * \param start Secret. Pointer to the start of the buffer. - * \param total Total size of the buffer. - * \param offset Secret. Offset from which to copy \p total - \p offset bytes. - */ -void mbedtls_ct_memmove_left(void *start, - size_t total, - size_t offset); - -#endif /* defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) */ - -/** Conditional memcpy. - * - * Functionally equivalent to: - * - * if (condition) { - * memcpy(dest, src1, len); - * } else { - * if (src2 != NULL) - * memcpy(dest, src2, len); - * } - * - * It will always read len bytes from src1. - * If src2 != NULL, it will always read len bytes from src2. - * If src2 == NULL, it will instead read len bytes from dest (as if src2 == dest). - * - * \param condition The condition - * \param dest Secret. Destination pointer. - * \param src1 Secret. Pointer to copy from (if \p condition == MBEDTLS_CT_TRUE). - * This may be equal to \p dest, but may not overlap in other ways. - * \param src2 Secret (contents only - may branch to determine if this parameter is NULL). - * Pointer to copy from (if \p condition == MBEDTLS_CT_FALSE and \p src2 is not NULL). May be NULL. - * This may be equal to \p dest, but may not overlap it in other ways. It may overlap with \p src1. - * \param len Number of bytes to copy. - */ -void mbedtls_ct_memcpy_if(mbedtls_ct_condition_t condition, - unsigned char *dest, - const unsigned char *src1, - const unsigned char *src2, - size_t len - ); - -/** Copy data from a secret position. - * - * Functionally equivalent to: - * - * memcpy(dst, src + offset, len) - * - * This function copies \p len bytes from \p src + \p offset to - * \p dst, with a code flow and memory access pattern that does not depend on - * \p offset, but only on \p offset_min, \p offset_max and \p len. - * - * \note This function reads from \p dest, but the value that - * is read does not influence the result and this - * function's behavior is well-defined regardless of the - * contents of the buffers. This may result in false - * positives from static or dynamic analyzers, especially - * if \p dest is not initialized. - * - * \param dest Secret. The destination buffer. This must point to a writable - * buffer of at least \p len bytes. - * \param src Secret. The base of the source buffer. This must point to a - * readable buffer of at least \p offset_max + \p len - * bytes. Shouldn't overlap with \p dest - * \param offset Secret. The offset in the source buffer from which to copy. - * This must be no less than \p offset_min and no greater - * than \p offset_max. - * \param offset_min The minimal value of \p offset. - * \param offset_max The maximal value of \p offset. - * \param len The number of bytes to copy. - */ -void mbedtls_ct_memcpy_offset(unsigned char *dest, - const unsigned char *src, - size_t offset, - size_t offset_min, - size_t offset_max, - size_t len); - -/* Documented in include/mbedtls/constant_time.h. a and b are secret. - - int mbedtls_ct_memcmp(const void *a, - const void *b, - size_t n); - */ - -#if defined(MBEDTLS_NIST_KW_C) - -/** Constant-time buffer comparison without branches. - * - * Similar to mbedtls_ct_memcmp, except that the result only depends on part of - * the input data - differences in the head or tail are ignored. Functionally equivalent to: - * - * memcmp(a + skip_head, b + skip_head, size - skip_head - skip_tail) - * - * Time taken depends on \p n, but not on \p skip_head or \p skip_tail . - * - * Behaviour is undefined if ( \p skip_head + \p skip_tail) > \p n. - * - * \param a Secret. Pointer to the first buffer, containing at least \p n bytes. May not be NULL. - * \param b Secret. Pointer to the second buffer, containing at least \p n bytes. May not be NULL. - * \param n The number of bytes to examine (total size of the buffers). - * \param skip_head Secret. The number of bytes to treat as non-significant at the start of the buffer. - * These bytes will still be read. - * \param skip_tail Secret. The number of bytes to treat as non-significant at the end of the buffer. - * These bytes will still be read. - * - * \return Zero if the contents of the two buffers are the same, otherwise non-zero. - */ -int mbedtls_ct_memcmp_partial(const void *a, - const void *b, - size_t n, - size_t skip_head, - size_t skip_tail); - -#endif - -/* Include the implementation of static inline functions above. */ -#include "constant_time_impl.h" - -#endif /* MBEDTLS_CONSTANT_TIME_INTERNAL_H */ +/** + * Constant-time functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONSTANT_TIME_INTERNAL_H +#define MBEDTLS_CONSTANT_TIME_INTERNAL_H + +#include +#include + +#include "common.h" + +#if defined(MBEDTLS_BIGNUM_C) +#include "mbedtls/bignum.h" +#endif + +/* The constant-time interface provides various operations that are likely + * to result in constant-time code that does not branch or use conditional + * instructions for secret data (for secret pointers, this also applies to + * the data pointed to). + * + * It has three main parts: + * + * - boolean operations + * These are all named mbedtls_ct__. + * They operate over and return mbedtls_ct_condition_t. + * All arguments are considered secret. + * example: bool x = y | z => x = mbedtls_ct_bool_or(y, z) + * example: bool x = y == z => x = mbedtls_ct_uint_eq(y, z) + * + * - conditional data selection + * These are all named mbedtls_ct__if and mbedtls_ct__if_else_0 + * All arguments are considered secret. + * example: size_t a = x ? b : c => a = mbedtls_ct_size_if(x, b, c) + * example: unsigned a = x ? b : 0 => a = mbedtls_ct_uint_if_else_0(x, b) + * + * - block memory operations + * Only some arguments are considered secret, as documented for each + * function. + * example: if (x) memcpy(...) => mbedtls_ct_memcpy_if(x, ...) + * + * mbedtls_ct_condition_t must be treated as opaque and only created and + * manipulated via the functions in this header. The compiler should never + * be able to prove anything about its value at compile-time. + * + * mbedtls_ct_uint_t is an unsigned integer type over which constant time + * operations may be performed via the functions in this header. It is as big + * as the larger of size_t and mbedtls_mpi_uint, i.e. it is safe to cast + * to/from "unsigned int", "size_t", and "mbedtls_mpi_uint" (and any other + * not-larger integer types). + * + * For Arm (32-bit, 64-bit and Thumb), x86 and x86-64, assembly implementations + * are used to ensure that the generated code is constant time. For other + * architectures, it uses a plain C fallback designed to yield constant-time code + * (this has been observed to be constant-time on latest gcc, clang and MSVC + * as of May 2023). + * + * For readability, the static inline definitions are separated out into + * constant_time_impl.h. + */ + +#if (SIZE_MAX > 0xffffffffffffffffULL) +/* Pointer size > 64-bit */ +typedef size_t mbedtls_ct_condition_t; +typedef size_t mbedtls_ct_uint_t; +typedef ptrdiff_t mbedtls_ct_int_t; +#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(SIZE_MAX)) +#elif (SIZE_MAX > 0xffffffff) || defined(MBEDTLS_HAVE_INT64) +/* 32-bit < pointer size <= 64-bit, or 64-bit MPI */ +typedef uint64_t mbedtls_ct_condition_t; +typedef uint64_t mbedtls_ct_uint_t; +typedef int64_t mbedtls_ct_int_t; +#define MBEDTLS_CT_SIZE_64 +#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(UINT64_MAX)) +#else +/* Pointer size <= 32-bit, and no 64-bit MPIs */ +typedef uint32_t mbedtls_ct_condition_t; +typedef uint32_t mbedtls_ct_uint_t; +typedef int32_t mbedtls_ct_int_t; +#define MBEDTLS_CT_SIZE_32 +#define MBEDTLS_CT_TRUE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(UINT32_MAX)) +#endif +#define MBEDTLS_CT_FALSE ((mbedtls_ct_condition_t) mbedtls_ct_compiler_opaque(0)) + +/* ============================================================================ + * Boolean operations + */ + +/** Convert a number into a mbedtls_ct_condition_t. + * + * \param x Number to convert. + * + * \return MBEDTLS_CT_TRUE if \p x != 0, or MBEDTLS_CT_FALSE if \p x == 0 + * + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool(mbedtls_ct_uint_t x); + +/** Boolean "not equal" operation. + * + * Functionally equivalent to: + * + * \p x != \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x != \p y, otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_ne(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y); + +/** Boolean "equals" operation. + * + * Functionally equivalent to: + * + * \p x == \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x == \p y, otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_eq(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y); + +/** Boolean "less than" operation. + * + * Functionally equivalent to: + * + * \p x < \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x < \p y, otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_lt(mbedtls_ct_uint_t x, mbedtls_ct_uint_t y); + +/** Boolean "greater than" operation. + * + * Functionally equivalent to: + * + * \p x > \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x > \p y, otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_gt(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y); + +/** Boolean "greater or equal" operation. + * + * Functionally equivalent to: + * + * \p x >= \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x >= \p y, + * otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_ge(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y); + +/** Boolean "less than or equal" operation. + * + * Functionally equivalent to: + * + * \p x <= \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x <= \p y, + * otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_uint_le(mbedtls_ct_uint_t x, + mbedtls_ct_uint_t y); + +/** Boolean not-equals operation. + * + * Functionally equivalent to: + * + * \p x != \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \note This is more efficient than mbedtls_ct_uint_ne if both arguments are + * mbedtls_ct_condition_t. + * + * \return MBEDTLS_CT_TRUE if \p x != \p y, + * otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_ne(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y); + +/** Boolean "and" operation. + * + * Functionally equivalent to: + * + * \p x && \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x && \p y, + * otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_and(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y); + +/** Boolean "or" operation. + * + * Functionally equivalent to: + * + * \p x || \p y + * + * \param x The first value to analyze. + * \param y The second value to analyze. + * + * \return MBEDTLS_CT_TRUE if \p x || \p y, + * otherwise MBEDTLS_CT_FALSE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_or(mbedtls_ct_condition_t x, + mbedtls_ct_condition_t y); + +/** Boolean "not" operation. + * + * Functionally equivalent to: + * + * ! \p x + * + * \param x The value to invert + * + * \return MBEDTLS_CT_FALSE if \p x, otherwise MBEDTLS_CT_TRUE. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_not(mbedtls_ct_condition_t x); + + +/* ============================================================================ + * Data selection operations + */ + +/** Choose between two size_t values. + * + * Functionally equivalent to: + * + * condition ? if1 : if0. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. + */ +static inline size_t mbedtls_ct_size_if(mbedtls_ct_condition_t condition, + size_t if1, + size_t if0); + +/** Choose between two unsigned values. + * + * Functionally equivalent to: + * + * condition ? if1 : if0. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. + */ +static inline unsigned mbedtls_ct_uint_if(mbedtls_ct_condition_t condition, + unsigned if1, + unsigned if0); + +/** Choose between two mbedtls_ct_condition_t values. + * + * Functionally equivalent to: + * + * condition ? if1 : if0. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_if(mbedtls_ct_condition_t condition, + mbedtls_ct_condition_t if1, + mbedtls_ct_condition_t if0); + +#if defined(MBEDTLS_BIGNUM_C) + +/** Choose between two mbedtls_mpi_uint values. + * + * Functionally equivalent to: + * + * condition ? if1 : if0. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. + */ +static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if(mbedtls_ct_condition_t condition, \ + mbedtls_mpi_uint if1, \ + mbedtls_mpi_uint if0); + +#endif + +/** Choose between an unsigned value and 0. + * + * Functionally equivalent to: + * + * condition ? if1 : 0. + * + * Functionally equivalent to mbedtls_ct_uint_if(condition, if1, 0) but + * results in smaller code size. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. + */ +static inline unsigned mbedtls_ct_uint_if_else_0(mbedtls_ct_condition_t condition, unsigned if1); + +/** Choose between an mbedtls_ct_condition_t and 0. + * + * Functionally equivalent to: + * + * condition ? if1 : 0. + * + * Functionally equivalent to mbedtls_ct_bool_if(condition, if1, 0) but + * results in smaller code size. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. + */ +static inline mbedtls_ct_condition_t mbedtls_ct_bool_if_else_0(mbedtls_ct_condition_t condition, + mbedtls_ct_condition_t if1); + +/** Choose between a size_t value and 0. + * + * Functionally equivalent to: + * + * condition ? if1 : 0. + * + * Functionally equivalent to mbedtls_ct_size_if(condition, if1, 0) but + * results in smaller code size. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. + */ +static inline size_t mbedtls_ct_size_if_else_0(mbedtls_ct_condition_t condition, size_t if1); + +#if defined(MBEDTLS_BIGNUM_C) + +/** Choose between an mbedtls_mpi_uint value and 0. + * + * Functionally equivalent to: + * + * condition ? if1 : 0. + * + * Functionally equivalent to mbedtls_ct_mpi_uint_if(condition, if1, 0) but + * results in smaller code size. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. + */ +static inline mbedtls_mpi_uint mbedtls_ct_mpi_uint_if_else_0(mbedtls_ct_condition_t condition, + mbedtls_mpi_uint if1); + +#endif + +/** Constant-flow char selection + * + * \param low Secret. Bottom of range + * \param high Secret. Top of range + * \param c Secret. Value to compare to range + * \param t Secret. Value to return, if in range + * + * \return \p t if \p low <= \p c <= \p high, 0 otherwise. + */ +static inline unsigned char mbedtls_ct_uchar_in_range_if(unsigned char low, + unsigned char high, + unsigned char c, + unsigned char t); + +/** Choose between two error values. The values must be in the range [-32767..0]. + * + * Functionally equivalent to: + * + * condition ? if1 : if0. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * \param if0 Value to use if \p condition == MBEDTLS_CT_FALSE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise \c if0. + */ +static inline int mbedtls_ct_error_if(mbedtls_ct_condition_t condition, int if1, int if0); + +/** Choose between an error value and 0. The error value must be in the range [-32767..0]. + * + * Functionally equivalent to: + * + * condition ? if1 : 0. + * + * Functionally equivalent to mbedtls_ct_error_if(condition, if1, 0) but + * results in smaller code size. + * + * \param condition Condition to test. + * \param if1 Value to use if \p condition == MBEDTLS_CT_TRUE. + * + * \return \c if1 if \p condition == MBEDTLS_CT_TRUE, otherwise 0. + */ +static inline int mbedtls_ct_error_if_else_0(mbedtls_ct_condition_t condition, int if1); + +/* ============================================================================ + * Block memory operations + */ + +#if defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) + +/** Conditionally set a block of memory to zero. + * + * Regardless of the condition, every byte will be read once and written to + * once. + * + * \param condition Secret. Condition to test. + * \param buf Secret. Pointer to the start of the buffer. + * \param len Number of bytes to set to zero. + * + * \warning Unlike mbedtls_platform_zeroize, this does not have the same guarantees + * about not being optimised away if the memory is never read again. + */ +void mbedtls_ct_zeroize_if(mbedtls_ct_condition_t condition, void *buf, size_t len); + +/** Shift some data towards the left inside a buffer. + * + * Functionally equivalent to: + * + * memmove(start, start + offset, total - offset); + * memset(start + (total - offset), 0, offset); + * + * Timing independence comes at the expense of performance. + * + * \param start Secret. Pointer to the start of the buffer. + * \param total Total size of the buffer. + * \param offset Secret. Offset from which to copy \p total - \p offset bytes. + */ +void mbedtls_ct_memmove_left(void *start, + size_t total, + size_t offset); + +#endif /* defined(MBEDTLS_PKCS1_V15) && defined(MBEDTLS_RSA_C) && !defined(MBEDTLS_RSA_ALT) */ + +/** Conditional memcpy. + * + * Functionally equivalent to: + * + * if (condition) { + * memcpy(dest, src1, len); + * } else { + * if (src2 != NULL) + * memcpy(dest, src2, len); + * } + * + * It will always read len bytes from src1. + * If src2 != NULL, it will always read len bytes from src2. + * If src2 == NULL, it will instead read len bytes from dest (as if src2 == dest). + * + * \param condition The condition + * \param dest Secret. Destination pointer. + * \param src1 Secret. Pointer to copy from (if \p condition == MBEDTLS_CT_TRUE). + * This may be equal to \p dest, but may not overlap in other ways. + * \param src2 Secret (contents only - may branch to determine if this parameter is NULL). + * Pointer to copy from (if \p condition == MBEDTLS_CT_FALSE and \p src2 is not NULL). May be NULL. + * This may be equal to \p dest, but may not overlap it in other ways. It may overlap with \p src1. + * \param len Number of bytes to copy. + */ +void mbedtls_ct_memcpy_if(mbedtls_ct_condition_t condition, + unsigned char *dest, + const unsigned char *src1, + const unsigned char *src2, + size_t len + ); + +/** Copy data from a secret position. + * + * Functionally equivalent to: + * + * memcpy(dst, src + offset, len) + * + * This function copies \p len bytes from \p src + \p offset to + * \p dst, with a code flow and memory access pattern that does not depend on + * \p offset, but only on \p offset_min, \p offset_max and \p len. + * + * \note This function reads from \p dest, but the value that + * is read does not influence the result and this + * function's behavior is well-defined regardless of the + * contents of the buffers. This may result in false + * positives from static or dynamic analyzers, especially + * if \p dest is not initialized. + * + * \param dest Secret. The destination buffer. This must point to a writable + * buffer of at least \p len bytes. + * \param src Secret. The base of the source buffer. This must point to a + * readable buffer of at least \p offset_max + \p len + * bytes. Shouldn't overlap with \p dest + * \param offset Secret. The offset in the source buffer from which to copy. + * This must be no less than \p offset_min and no greater + * than \p offset_max. + * \param offset_min The minimal value of \p offset. + * \param offset_max The maximal value of \p offset. + * \param len The number of bytes to copy. + */ +void mbedtls_ct_memcpy_offset(unsigned char *dest, + const unsigned char *src, + size_t offset, + size_t offset_min, + size_t offset_max, + size_t len); + +/* Documented in include/mbedtls/constant_time.h. a and b are secret. + + int mbedtls_ct_memcmp(const void *a, + const void *b, + size_t n); + */ + +#if defined(MBEDTLS_NIST_KW_C) + +/** Constant-time buffer comparison without branches. + * + * Similar to mbedtls_ct_memcmp, except that the result only depends on part of + * the input data - differences in the head or tail are ignored. Functionally equivalent to: + * + * memcmp(a + skip_head, b + skip_head, size - skip_head - skip_tail) + * + * Time taken depends on \p n, but not on \p skip_head or \p skip_tail . + * + * Behaviour is undefined if ( \p skip_head + \p skip_tail) > \p n. + * + * \param a Secret. Pointer to the first buffer, containing at least \p n bytes. May not be NULL. + * \param b Secret. Pointer to the second buffer, containing at least \p n bytes. May not be NULL. + * \param n The number of bytes to examine (total size of the buffers). + * \param skip_head Secret. The number of bytes to treat as non-significant at the start of the buffer. + * These bytes will still be read. + * \param skip_tail Secret. The number of bytes to treat as non-significant at the end of the buffer. + * These bytes will still be read. + * + * \return Zero if the contents of the two buffers are the same, otherwise non-zero. + */ +int mbedtls_ct_memcmp_partial(const void *a, + const void *b, + size_t n, + size_t skip_head, + size_t skip_tail); + +#endif + +/* Include the implementation of static inline functions above. */ +#include "constant_time_impl.h" + +#endif /* MBEDTLS_CONSTANT_TIME_INTERNAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_internal_alt.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_internal_alt.h index f663d67..dca784d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_internal_alt.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_internal_alt.h @@ -1,299 +1,299 @@ -/** - * \file ecp_internal_alt.h - * - * \brief Function declarations for alternative implementation of elliptic curve - * point arithmetic. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * References: - * - * [1] BERNSTEIN, Daniel J. Curve25519: new Diffie-Hellman speed records. - * - * - * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis - * for elliptic curve cryptosystems. In : Cryptographic Hardware and - * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. - * - * - * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to - * render ECC resistant against Side Channel Attacks. IACR Cryptology - * ePrint Archive, 2004, vol. 2004, p. 342. - * - * - * [4] Certicom Research. SEC 2: Recommended Elliptic Curve Domain Parameters. - * - * - * [5] HANKERSON, Darrel, MENEZES, Alfred J., VANSTONE, Scott. Guide to Elliptic - * Curve Cryptography. - * - * [6] Digital Signature Standard (DSS), FIPS 186-4. - * - * - * [7] Elliptic Curve Cryptography (ECC) Cipher Suites for Transport Layer - * Security (TLS), RFC 4492. - * - * - * [8] - * - * [9] COHEN, Henri. A Course in Computational Algebraic Number Theory. - * Springer Science & Business Media, 1 Aug 2000 - */ - -#ifndef MBEDTLS_ECP_INTERNAL_H -#define MBEDTLS_ECP_INTERNAL_H - -#include "mbedtls/build_info.h" - -#if defined(MBEDTLS_ECP_INTERNAL_ALT) - -/** - * \brief Indicate if the Elliptic Curve Point module extension can - * handle the group. - * - * \param grp The pointer to the elliptic curve group that will be the - * basis of the cryptographic computations. - * - * \return Non-zero if successful. - */ -unsigned char mbedtls_internal_ecp_grp_capable(const mbedtls_ecp_group *grp); - -/** - * \brief Initialise the Elliptic Curve Point module extension. - * - * If mbedtls_internal_ecp_grp_capable returns true for a - * group, this function has to be able to initialise the - * module for it. - * - * This module can be a driver to a crypto hardware - * accelerator, for which this could be an initialise function. - * - * \param grp The pointer to the group the module needs to be - * initialised for. - * - * \return 0 if successful. - */ -int mbedtls_internal_ecp_init(const mbedtls_ecp_group *grp); - -/** - * \brief Frees and deallocates the Elliptic Curve Point module - * extension. - * - * \param grp The pointer to the group the module was initialised for. - */ -void mbedtls_internal_ecp_free(const mbedtls_ecp_group *grp); - -#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) - -#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) -/** - * \brief Randomize jacobian coordinates: - * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l. - * - * \param grp Pointer to the group representing the curve. - * - * \param pt The point on the curve to be randomised, given with Jacobian - * coordinates. - * - * \param f_rng A function pointer to the random number generator. - * - * \param p_rng A pointer to the random number generator state. - * - * \return 0 if successful. - */ -int mbedtls_internal_ecp_randomize_jac(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *pt, int (*f_rng)(void *, - unsigned char *, - size_t), - void *p_rng); -#endif - -#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) -/** - * \brief Addition: R = P + Q, mixed affine-Jacobian coordinates. - * - * The coordinates of Q must be normalized (= affine), - * but those of P don't need to. R is not normalized. - * - * This function is used only as a subrutine of - * ecp_mul_comb(). - * - * Special cases: (1) P or Q is zero, (2) R is zero, - * (3) P == Q. - * None of these cases can happen as intermediate step in - * ecp_mul_comb(): - * - at each step, P, Q and R are multiples of the base - * point, the factor being less than its order, so none of - * them is zero; - * - Q is an odd multiple of the base point, P an even - * multiple, due to the choice of precomputed points in the - * modified comb method. - * So branches for these cases do not leak secret information. - * - * We accept Q->Z being unset (saving memory in tables) as - * meaning 1. - * - * Cost in field operations if done by [5] 3.22: - * 1A := 8M + 3S - * - * \param grp Pointer to the group representing the curve. - * - * \param R Pointer to a point structure to hold the result. - * - * \param P Pointer to the first summand, given with Jacobian - * coordinates - * - * \param Q Pointer to the second summand, given with affine - * coordinates. - * - * \return 0 if successful. - */ -int mbedtls_internal_ecp_add_mixed(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *R, const mbedtls_ecp_point *P, - const mbedtls_ecp_point *Q); -#endif - -/** - * \brief Point doubling R = 2 P, Jacobian coordinates. - * - * Cost: 1D := 3M + 4S (A == 0) - * 4M + 4S (A == -3) - * 3M + 6S + 1a otherwise - * when the implementation is based on the "dbl-1998-cmo-2" - * doubling formulas in [8] and standard optimizations are - * applied when curve parameter A is one of { 0, -3 }. - * - * \param grp Pointer to the group representing the curve. - * - * \param R Pointer to a point structure to hold the result. - * - * \param P Pointer to the point that has to be doubled, given with - * Jacobian coordinates. - * - * \return 0 if successful. - */ -#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) -int mbedtls_internal_ecp_double_jac(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *R, const mbedtls_ecp_point *P); -#endif - -/** - * \brief Normalize jacobian coordinates of an array of (pointers to) - * points. - * - * Using Montgomery's trick to perform only one inversion mod P - * the cost is: - * 1N(t) := 1I + (6t - 3)M + 1S - * (See for example Algorithm 10.3.4. in [9]) - * - * This function is used only as a subrutine of - * ecp_mul_comb(). - * - * Warning: fails (returning an error) if one of the points is - * zero! - * This should never happen, see choice of w in ecp_mul_comb(). - * - * \param grp Pointer to the group representing the curve. - * - * \param T Array of pointers to the points to normalise. - * - * \param t_len Number of elements in the array. - * - * \return 0 if successful, - * an error if one of the points is zero. - */ -#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) -int mbedtls_internal_ecp_normalize_jac_many(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *T[], size_t t_len); -#endif - -/** - * \brief Normalize jacobian coordinates so that Z == 0 || Z == 1. - * - * Cost in field operations if done by [5] 3.2.1: - * 1N := 1I + 3M + 1S - * - * \param grp Pointer to the group representing the curve. - * - * \param pt pointer to the point to be normalised. This is an - * input/output parameter. - * - * \return 0 if successful. - */ -#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) -int mbedtls_internal_ecp_normalize_jac(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *pt); -#endif - -#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ - -#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) - -#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) -int mbedtls_internal_ecp_double_add_mxz(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *R, - mbedtls_ecp_point *S, - const mbedtls_ecp_point *P, - const mbedtls_ecp_point *Q, - const mbedtls_mpi *d); -#endif - -/** - * \brief Randomize projective x/z coordinates: - * (X, Z) -> (l X, l Z) for random l - * - * \param grp pointer to the group representing the curve - * - * \param P the point on the curve to be randomised given with - * projective coordinates. This is an input/output parameter. - * - * \param f_rng a function pointer to the random number generator - * - * \param p_rng a pointer to the random number generator state - * - * \return 0 if successful - */ -#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) -int mbedtls_internal_ecp_randomize_mxz(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *P, int (*f_rng)(void *, - unsigned char *, - size_t), - void *p_rng); -#endif - -/** - * \brief Normalize Montgomery x/z coordinates: X = X/Z, Z = 1. - * - * \param grp pointer to the group representing the curve - * - * \param P pointer to the point to be normalised. This is an - * input/output parameter. - * - * \return 0 if successful - */ -#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) -int mbedtls_internal_ecp_normalize_mxz(const mbedtls_ecp_group *grp, - mbedtls_ecp_point *P); -#endif - -#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ - -#endif /* MBEDTLS_ECP_INTERNAL_ALT */ - -#endif /* ecp_internal_alt.h */ +/** + * \file ecp_internal_alt.h + * + * \brief Function declarations for alternative implementation of elliptic curve + * point arithmetic. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * References: + * + * [1] BERNSTEIN, Daniel J. Curve25519: new Diffie-Hellman speed records. + * + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + * + * [4] Certicom Research. SEC 2: Recommended Elliptic Curve Domain Parameters. + * + * + * [5] HANKERSON, Darrel, MENEZES, Alfred J., VANSTONE, Scott. Guide to Elliptic + * Curve Cryptography. + * + * [6] Digital Signature Standard (DSS), FIPS 186-4. + * + * + * [7] Elliptic Curve Cryptography (ECC) Cipher Suites for Transport Layer + * Security (TLS), RFC 4492. + * + * + * [8] + * + * [9] COHEN, Henri. A Course in Computational Algebraic Number Theory. + * Springer Science & Business Media, 1 Aug 2000 + */ + +#ifndef MBEDTLS_ECP_INTERNAL_H +#define MBEDTLS_ECP_INTERNAL_H + +#include "mbedtls/build_info.h" + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + +/** + * \brief Indicate if the Elliptic Curve Point module extension can + * handle the group. + * + * \param grp The pointer to the elliptic curve group that will be the + * basis of the cryptographic computations. + * + * \return Non-zero if successful. + */ +unsigned char mbedtls_internal_ecp_grp_capable(const mbedtls_ecp_group *grp); + +/** + * \brief Initialise the Elliptic Curve Point module extension. + * + * If mbedtls_internal_ecp_grp_capable returns true for a + * group, this function has to be able to initialise the + * module for it. + * + * This module can be a driver to a crypto hardware + * accelerator, for which this could be an initialise function. + * + * \param grp The pointer to the group the module needs to be + * initialised for. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_init(const mbedtls_ecp_group *grp); + +/** + * \brief Frees and deallocates the Elliptic Curve Point module + * extension. + * + * \param grp The pointer to the group the module was initialised for. + */ +void mbedtls_internal_ecp_free(const mbedtls_ecp_group *grp); + +#if defined(MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED) + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) +/** + * \brief Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l. + * + * \param grp Pointer to the group representing the curve. + * + * \param pt The point on the curve to be randomised, given with Jacobian + * coordinates. + * + * \param f_rng A function pointer to the random number generator. + * + * \param p_rng A pointer to the random number generator state. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_randomize_jac(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng); +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) +/** + * \brief Addition: R = P + Q, mixed affine-Jacobian coordinates. + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Special cases: (1) P or Q is zero, (2) R is zero, + * (3) P == Q. + * None of these cases can happen as intermediate step in + * ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base + * point, the factor being less than its order, so none of + * them is zero; + * - Q is an odd multiple of the base point, P an even + * multiple, due to the choice of precomputed points in the + * modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as + * meaning 1. + * + * Cost in field operations if done by [5] 3.22: + * 1A := 8M + 3S + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the first summand, given with Jacobian + * coordinates + * + * \param Q Pointer to the second summand, given with affine + * coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_add_mixed(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q); +#endif + +/** + * \brief Point doubling R = 2 P, Jacobian coordinates. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + * when the implementation is based on the "dbl-1998-cmo-2" + * doubling formulas in [8] and standard optimizations are + * applied when curve parameter A is one of { 0, -3 }. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the point that has to be doubled, given with + * Jacobian coordinates. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) +int mbedtls_internal_ecp_double_jac(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, const mbedtls_ecp_point *P); +#endif + +/** + * \brief Normalize jacobian coordinates of an array of (pointers to) + * points. + * + * Using Montgomery's trick to perform only one inversion mod P + * the cost is: + * 1N(t) := 1I + (6t - 3)M + 1S + * (See for example Algorithm 10.3.4. in [9]) + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Warning: fails (returning an error) if one of the points is + * zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * \param grp Pointer to the group representing the curve. + * + * \param T Array of pointers to the points to normalise. + * + * \param t_len Number of elements in the array. + * + * \return 0 if successful, + * an error if one of the points is zero. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) +int mbedtls_internal_ecp_normalize_jac_many(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t t_len); +#endif + +/** + * \brief Normalize jacobian coordinates so that Z == 0 || Z == 1. + * + * Cost in field operations if done by [5] 3.2.1: + * 1N := 1I + 3M + 1S + * + * \param grp Pointer to the group representing the curve. + * + * \param pt pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) +int mbedtls_internal_ecp_normalize_jac(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt); +#endif + +#endif /* MBEDTLS_ECP_SHORT_WEIERSTRASS_ENABLED */ + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) +int mbedtls_internal_ecp_double_add_mxz(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + mbedtls_ecp_point *S, + const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q, + const mbedtls_mpi *d); +#endif + +/** + * \brief Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * + * \param grp pointer to the group representing the curve + * + * \param P the point on the curve to be randomised given with + * projective coordinates. This is an input/output parameter. + * + * \param f_rng a function pointer to the random number generator + * + * \param p_rng a pointer to the random number generator state + * + * \return 0 if successful + */ +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) +int mbedtls_internal_ecp_randomize_mxz(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P, int (*f_rng)(void *, + unsigned char *, + size_t), + void *p_rng); +#endif + +/** + * \brief Normalize Montgomery x/z coordinates: X = X/Z, Z = 1. + * + * \param grp pointer to the group representing the curve + * + * \param P pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful + */ +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) +int mbedtls_internal_ecp_normalize_mxz(const mbedtls_ecp_group *grp, + mbedtls_ecp_point *P); +#endif + +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#endif /* ecp_internal_alt.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_invasive.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_invasive.h index bb3b127..aff1fc3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_invasive.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ecp_invasive.h @@ -1,337 +1,337 @@ -/** - * \file ecp_invasive.h - * - * \brief ECP module: interfaces for invasive testing only. - * - * The interfaces in this file are intended for testing purposes only. - * They SHOULD NOT be made available in library integrations except when - * building the library for testing. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ECP_INVASIVE_H -#define MBEDTLS_ECP_INVASIVE_H - -#include "common.h" -#include "mbedtls/bignum.h" -#include "bignum_mod.h" -#include "mbedtls/ecp.h" - -/* - * Curve modulus types - */ -typedef enum { - MBEDTLS_ECP_MOD_NONE = 0, - MBEDTLS_ECP_MOD_COORDINATE, - MBEDTLS_ECP_MOD_SCALAR -} mbedtls_ecp_modulus_type; - -typedef enum { - MBEDTLS_ECP_VARIANT_NONE = 0, - MBEDTLS_ECP_VARIANT_WITH_MPI_STRUCT, - MBEDTLS_ECP_VARIANT_WITH_MPI_UINT -} mbedtls_ecp_variant; - -#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_ECP_LIGHT) - -/** Queries the ecp variant. - * - * \return The id of the ecp variant. - */ -MBEDTLS_STATIC_TESTABLE -mbedtls_ecp_variant mbedtls_ecp_get_variant(void); - -#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) -/** Generate a private key on a Montgomery curve (Curve25519 or Curve448). - * - * This function implements key generation for the set of secret keys - * specified in [Curve25519] p. 5 and in [Curve448]. The resulting value - * has the lower bits masked but is not necessarily canonical. - * - * \note - [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf - * - [RFC7748] https://tools.ietf.org/html/rfc7748 - * - * \p high_bit The position of the high-order bit of the key to generate. - * This is the bit-size of the key minus 1: - * 254 for Curve25519 or 447 for Curve448. - * \param d The randomly generated key. This is a number of size - * exactly \p high_bit + 1 bits, with the least significant bits - * masked as specified in [Curve25519] and in [RFC7748] §5. - * \param f_rng The RNG function. - * \param p_rng The RNG context to be passed to \p f_rng. - * - * \return \c 0 on success. - * \return \c MBEDTLS_ERR_ECP_xxx or MBEDTLS_ERR_MPI_xxx on failure. - */ -int mbedtls_ecp_gen_privkey_mx(size_t high_bit, - mbedtls_mpi *d, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) - -/** Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) - * - * This operation expects a 384 bit MPI and the result of the reduction - * is a 192 bit MPI. - * - * \param[in,out] Np The address of the MPI to be converted. - * Must have twice as many limbs as the modulus. - * Upon return this holds the reduced value. The bitlength - * of the reduced value is the same as that of the modulus - * (192 bits). - * \param[in] Nn The length of \p Np in limbs. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p192_raw(mbedtls_mpi_uint *Np, size_t Nn); - -#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) - -/** Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 448-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (224 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs is not the - * limb size that sores a 448-bit MPI. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p224_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) - -/** Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 512-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (256 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs is not the - * limb size that sores a 512-bit MPI. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p256_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif - -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) - -/** Fast quasi-reduction modulo p521 = 2^521 - 1 (FIPS 186-3 D.2.5) - * - * \param[in,out] X The address of the MPI to be converted. - * Must have twice as many limbs as the modulus - * (the modulus is 521 bits long). Upon return this - * holds the reduced value. The reduced value is - * in range `0 <= X < 2 * N` (where N is the modulus). - * and its the bitlength is one plus the bitlength - * of the modulus. - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs does not have - * twice as many limbs as the modulus. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p521_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) - -/** Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 768-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (384 bits). - * \param[in] X_limbs The length of \p N in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p N_n does not have - * twice as many limbs as the modulus. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p384_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) - -/** Fast quasi-reduction modulo p192k1 = 2^192 - R, - * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x01000011C9 - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 384-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (192 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have - * twice as many limbs as the modulus. - * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p192k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) - -/** Fast quasi-reduction modulo p224k1 = 2^224 - R, - * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 448-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (224 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have - * twice as many limbs as the modulus. - * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p224k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) - -/** Fast quasi-reduction modulo p256k1 = 2^256 - R, - * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 512-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * The bitlength of the reduced value is the same as - * that of the modulus (256 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have - * twice as many limbs as the modulus. - * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p256k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) - -/** Fast quasi-reduction modulo p255 = 2^255 - 19 - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 510-bit MPI - * (double the bitlength of the modulus). - * Upon return holds the reduced value which is - * in range `0 <= X < 2 * N` (where N is the modulus). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have - * twice as many limbs as the modulus. - * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p255_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ - -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) - -/** Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 - * Write X as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return A0 + A1 + B1 + - * (B0 + B1) * 2^224. - * - * \param[in,out] X The address of the MPI to be converted. - * Must have exact limb size that stores a 896-bit MPI - * (double the bitlength of the modulus). Upon return - * holds the reduced value which is in range `0 <= X < - * N` (where N is the modulus). The bitlength of the - * reduced value is the same as that of the modulus - * (448 bits). - * \param[in] X_limbs The length of \p X in limbs. - * - * \return \c 0 on Success. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have - * twice as many limbs as the modulus. - * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation - * failed. - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_mod_p448_raw(mbedtls_mpi_uint *X, size_t X_limbs); - -#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ - -/** Initialise a modulus with hard-coded const curve data. - * - * \note The caller is responsible for the \p N modulus' memory. - * mbedtls_mpi_mod_modulus_free(&N) should be invoked at the - * end of its lifecycle. - * - * \param[in,out] N The address of the modulus structure to populate. - * Must be initialized. - * \param[in] id The mbedtls_ecp_group_id for which to initialise the modulus. - * \param[in] ctype The mbedtls_ecp_modulus_type identifier for a coordinate modulus (P) - * or a scalar modulus (N). - * - * \return \c 0 if successful. - * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the given MPIs do not - * have the correct number of limbs. - * - */ -MBEDTLS_STATIC_TESTABLE -int mbedtls_ecp_modulus_setup(mbedtls_mpi_mod_modulus *N, - const mbedtls_ecp_group_id id, - const mbedtls_ecp_modulus_type ctype); - -#endif /* MBEDTLS_TEST_HOOKS && MBEDTLS_ECP_C */ - -#endif /* MBEDTLS_ECP_INVASIVE_H */ +/** + * \file ecp_invasive.h + * + * \brief ECP module: interfaces for invasive testing only. + * + * The interfaces in this file are intended for testing purposes only. + * They SHOULD NOT be made available in library integrations except when + * building the library for testing. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ECP_INVASIVE_H +#define MBEDTLS_ECP_INVASIVE_H + +#include "common.h" +#include "mbedtls/bignum.h" +#include "bignum_mod.h" +#include "mbedtls/ecp.h" + +/* + * Curve modulus types + */ +typedef enum { + MBEDTLS_ECP_MOD_NONE = 0, + MBEDTLS_ECP_MOD_COORDINATE, + MBEDTLS_ECP_MOD_SCALAR +} mbedtls_ecp_modulus_type; + +typedef enum { + MBEDTLS_ECP_VARIANT_NONE = 0, + MBEDTLS_ECP_VARIANT_WITH_MPI_STRUCT, + MBEDTLS_ECP_VARIANT_WITH_MPI_UINT +} mbedtls_ecp_variant; + +#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_ECP_LIGHT) + +/** Queries the ecp variant. + * + * \return The id of the ecp variant. + */ +MBEDTLS_STATIC_TESTABLE +mbedtls_ecp_variant mbedtls_ecp_get_variant(void); + +#if defined(MBEDTLS_ECP_MONTGOMERY_ENABLED) +/** Generate a private key on a Montgomery curve (Curve25519 or Curve448). + * + * This function implements key generation for the set of secret keys + * specified in [Curve25519] p. 5 and in [Curve448]. The resulting value + * has the lower bits masked but is not necessarily canonical. + * + * \note - [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * - [RFC7748] https://tools.ietf.org/html/rfc7748 + * + * \p high_bit The position of the high-order bit of the key to generate. + * This is the bit-size of the key minus 1: + * 254 for Curve25519 or 447 for Curve448. + * \param d The randomly generated key. This is a number of size + * exactly \p high_bit + 1 bits, with the least significant bits + * masked as specified in [Curve25519] and in [RFC7748] §5. + * \param f_rng The RNG function. + * \param p_rng The RNG context to be passed to \p f_rng. + * + * \return \c 0 on success. + * \return \c MBEDTLS_ERR_ECP_xxx or MBEDTLS_ERR_MPI_xxx on failure. + */ +int mbedtls_ecp_gen_privkey_mx(size_t high_bit, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#endif /* MBEDTLS_ECP_MONTGOMERY_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + +/** Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) + * + * This operation expects a 384 bit MPI and the result of the reduction + * is a 192 bit MPI. + * + * \param[in,out] Np The address of the MPI to be converted. + * Must have twice as many limbs as the modulus. + * Upon return this holds the reduced value. The bitlength + * of the reduced value is the same as that of the modulus + * (192 bits). + * \param[in] Nn The length of \p Np in limbs. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p192_raw(mbedtls_mpi_uint *Np, size_t Nn); + +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + +/** Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 448-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (224 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs is not the + * limb size that sores a 448-bit MPI. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p224_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + +/** Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 512-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (256 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs is not the + * limb size that sores a 512-bit MPI. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p256_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + +/** Fast quasi-reduction modulo p521 = 2^521 - 1 (FIPS 186-3 D.2.5) + * + * \param[in,out] X The address of the MPI to be converted. + * Must have twice as many limbs as the modulus + * (the modulus is 521 bits long). Upon return this + * holds the reduced value. The reduced value is + * in range `0 <= X < 2 * N` (where N is the modulus). + * and its the bitlength is one plus the bitlength + * of the modulus. + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X_limbs does not have + * twice as many limbs as the modulus. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p521_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + +/** Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 768-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (384 bits). + * \param[in] X_limbs The length of \p N in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p N_n does not have + * twice as many limbs as the modulus. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p384_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + +/** Fast quasi-reduction modulo p192k1 = 2^192 - R, + * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x01000011C9 + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 384-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (192 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have + * twice as many limbs as the modulus. + * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p192k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + +/** Fast quasi-reduction modulo p224k1 = 2^224 - R, + * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 448-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (224 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have + * twice as many limbs as the modulus. + * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p224k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + +/** Fast quasi-reduction modulo p256k1 = 2^256 - R, + * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 512-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * The bitlength of the reduced value is the same as + * that of the modulus (256 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have + * twice as many limbs as the modulus. + * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p256k1_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +/** Fast quasi-reduction modulo p255 = 2^255 - 19 + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 510-bit MPI + * (double the bitlength of the modulus). + * Upon return holds the reduced value which is + * in range `0 <= X < 2 * N` (where N is the modulus). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have + * twice as many limbs as the modulus. + * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation failed. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p255_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/** Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 + * Write X as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return A0 + A1 + B1 + + * (B0 + B1) * 2^224. + * + * \param[in,out] X The address of the MPI to be converted. + * Must have exact limb size that stores a 896-bit MPI + * (double the bitlength of the modulus). Upon return + * holds the reduced value which is in range `0 <= X < + * N` (where N is the modulus). The bitlength of the + * reduced value is the same as that of the modulus + * (448 bits). + * \param[in] X_limbs The length of \p X in limbs. + * + * \return \c 0 on Success. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if \p X does not have + * twice as many limbs as the modulus. + * \return #MBEDTLS_ERR_ECP_ALLOC_FAILED if memory allocation + * failed. + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_mod_p448_raw(mbedtls_mpi_uint *X, size_t X_limbs); + +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +/** Initialise a modulus with hard-coded const curve data. + * + * \note The caller is responsible for the \p N modulus' memory. + * mbedtls_mpi_mod_modulus_free(&N) should be invoked at the + * end of its lifecycle. + * + * \param[in,out] N The address of the modulus structure to populate. + * Must be initialized. + * \param[in] id The mbedtls_ecp_group_id for which to initialise the modulus. + * \param[in] ctype The mbedtls_ecp_modulus_type identifier for a coordinate modulus (P) + * or a scalar modulus (N). + * + * \return \c 0 if successful. + * \return #MBEDTLS_ERR_ECP_BAD_INPUT_DATA if the given MPIs do not + * have the correct number of limbs. + * + */ +MBEDTLS_STATIC_TESTABLE +int mbedtls_ecp_modulus_setup(mbedtls_mpi_mod_modulus *N, + const mbedtls_ecp_group_id id, + const mbedtls_ecp_modulus_type ctype); + +#endif /* MBEDTLS_TEST_HOOKS && MBEDTLS_ECP_C */ + +#endif /* MBEDTLS_ECP_INVASIVE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/entropy_poll.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/entropy_poll.h index be4943c..b852ae7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/entropy_poll.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/entropy_poll.h @@ -1,76 +1,76 @@ -/** - * \file entropy_poll.h - * - * \brief Platform-specific and custom entropy polling functions - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_ENTROPY_POLL_H -#define MBEDTLS_ENTROPY_POLL_H - -#include "mbedtls/build_info.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * Default thresholds for built-in sources, in bytes - */ -#define MBEDTLS_ENTROPY_MIN_PLATFORM 32 /**< Minimum for platform source */ -#if !defined(MBEDTLS_ENTROPY_MIN_HARDWARE) -#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Minimum for the hardware source */ -#endif - -#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY) -/** - * \brief Platform-specific entropy poll callback - */ -int mbedtls_platform_entropy_poll(void *data, - unsigned char *output, size_t len, size_t *olen); -#endif - -#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) -/** - * \brief Entropy poll callback for a hardware source - * - * \warning This is not provided by Mbed TLS! - * See \c MBEDTLS_ENTROPY_HARDWARE_ALT in mbedtls_config.h. - * - * \note This must accept NULL as its first argument. - */ -int mbedtls_hardware_poll(void *data, - unsigned char *output, size_t len, size_t *olen); -#endif - -#if defined(MBEDTLS_ENTROPY_NV_SEED) -/** - * \brief Entropy poll callback for a non-volatile seed file - * - * \note This must accept NULL as its first argument. - */ -int mbedtls_nv_seed_poll(void *data, - unsigned char *output, size_t len, size_t *olen); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* entropy_poll.h */ +/** + * \file entropy_poll.h + * + * \brief Platform-specific and custom entropy polling functions + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_ENTROPY_POLL_H +#define MBEDTLS_ENTROPY_POLL_H + +#include "mbedtls/build_info.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Default thresholds for built-in sources, in bytes + */ +#define MBEDTLS_ENTROPY_MIN_PLATFORM 32 /**< Minimum for platform source */ +#if !defined(MBEDTLS_ENTROPY_MIN_HARDWARE) +#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Minimum for the hardware source */ +#endif + +#if !defined(MBEDTLS_NO_PLATFORM_ENTROPY) +/** + * \brief Platform-specific entropy poll callback + */ +int mbedtls_platform_entropy_poll(void *data, + unsigned char *output, size_t len, size_t *olen); +#endif + +#if defined(MBEDTLS_ENTROPY_HARDWARE_ALT) +/** + * \brief Entropy poll callback for a hardware source + * + * \warning This is not provided by Mbed TLS! + * See \c MBEDTLS_ENTROPY_HARDWARE_ALT in mbedtls_config.h. + * + * \note This must accept NULL as its first argument. + */ +int mbedtls_hardware_poll(void *data, + unsigned char *output, size_t len, size_t *olen); +#endif + +#if defined(MBEDTLS_ENTROPY_NV_SEED) +/** + * \brief Entropy poll callback for a non-volatile seed file + * + * \note This must accept NULL as its first argument. + */ +int mbedtls_nv_seed_poll(void *data, + unsigned char *output, size_t len, size_t *olen); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* entropy_poll.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/lmots.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/lmots.h index 98d1941..11e0e97 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/lmots.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/lmots.h @@ -1,323 +1,323 @@ -/** - * \file lmots.h - * - * \brief This file provides an API for the LM-OTS post-quantum-safe one-time - * public-key signature scheme as defined in RFC8554 and NIST.SP.200-208. - * This implementation currently only supports a single parameter set - * MBEDTLS_LMOTS_SHA256_N32_W8 in order to reduce complexity. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_LMOTS_H -#define MBEDTLS_LMOTS_H - -#include "mbedtls/build_info.h" - -#include "psa/crypto.h" - -#include "mbedtls/lms.h" - -#include -#include - - -#define MBEDTLS_LMOTS_PUBLIC_KEY_LEN(type) (MBEDTLS_LMOTS_TYPE_LEN + \ - MBEDTLS_LMOTS_I_KEY_ID_LEN + \ - MBEDTLS_LMOTS_Q_LEAF_ID_LEN + \ - MBEDTLS_LMOTS_N_HASH_LEN(type)) - -#define MBEDTLS_LMOTS_SIG_TYPE_OFFSET (0) -#define MBEDTLS_LMOTS_SIG_C_RANDOM_OFFSET (MBEDTLS_LMOTS_SIG_TYPE_OFFSET + \ - MBEDTLS_LMOTS_TYPE_LEN) -#define MBEDTLS_LMOTS_SIG_SIGNATURE_OFFSET(type) (MBEDTLS_LMOTS_SIG_C_RANDOM_OFFSET + \ - MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type)) - -#ifdef __cplusplus -extern "C" { -#endif - - -#if defined(MBEDTLS_TEST_HOOKS) -extern int (*mbedtls_lmots_sign_private_key_invalidated_hook)(unsigned char *); -#endif /* defined(MBEDTLS_TEST_HOOKS) */ - -/** - * \brief This function converts an unsigned int into a - * network-byte-order (big endian) string. - * - * \param val The unsigned integer value - * \param len The length of the string. - * \param bytes The string to output into. - */ -void mbedtls_lms_unsigned_int_to_network_bytes(unsigned int val, size_t len, - unsigned char *bytes); - -/** - * \brief This function converts a network-byte-order - * (big endian) string into an unsigned integer. - * - * \param len The length of the string. - * \param bytes The string. - * - * \return The corresponding LMS error code. - */ -unsigned int mbedtls_lms_network_bytes_to_unsigned_int(size_t len, - const unsigned char *bytes); - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief This function converts a \ref psa_status_t to a - * low-level LMS error code. - * - * \param status The psa_status_t to convert - * - * \return The corresponding LMS error code. - */ -int MBEDTLS_DEPRECATED mbedtls_lms_error_from_psa(psa_status_t status); -#endif - -/** - * \brief This function initializes a public LMOTS context - * - * \param ctx The uninitialized LMOTS context that will then be - * initialized. - */ -void mbedtls_lmots_public_init(mbedtls_lmots_public_t *ctx); - -/** - * \brief This function uninitializes a public LMOTS context - * - * \param ctx The initialized LMOTS context that will then be - * uninitialized. - */ -void mbedtls_lmots_public_free(mbedtls_lmots_public_t *ctx); - -/** - * \brief This function imports an LMOTS public key into a - * LMOTS context. - * - * \note Before this function is called, the context must - * have been initialized. - * - * \note See IETF RFC8554 for details of the encoding of - * this public key. - * - * \param ctx The initialized LMOTS context store the key in. - * \param key The buffer from which the key will be read. - * #MBEDTLS_LMOTS_PUBLIC_KEY_LEN bytes will be read - * from this. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_import_public_key(mbedtls_lmots_public_t *ctx, - const unsigned char *key, size_t key_size); - -/** - * \brief This function exports an LMOTS public key from a - * LMOTS context that already contains a public key. - * - * \note Before this function is called, the context must - * have been initialized and the context must contain - * a public key. - * - * \note See IETF RFC8554 for details of the encoding of - * this public key. - * - * \param ctx The initialized LMOTS context that contains the - * public key. - * \param key The buffer into which the key will be output. Must - * be at least #MBEDTLS_LMOTS_PUBLIC_KEY_LEN in size. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_export_public_key(const mbedtls_lmots_public_t *ctx, - unsigned char *key, size_t key_size, - size_t *key_len); - -/** - * \brief This function creates a candidate public key from - * an LMOTS signature. This can then be compared to - * the real public key to determine the validity of - * the signature. - * - * \note This function is exposed publicly to be used in LMS - * signature verification, it is expected that - * mbedtls_lmots_verify will be used for LMOTS - * signature verification. - * - * \param params The LMOTS parameter set, q and I values as an - * mbedtls_lmots_parameters_t struct. - * \param msg The buffer from which the message will be read. - * \param msg_size The size of the message that will be read. - * \param sig The buffer from which the signature will be read. - * #MBEDTLS_LMOTS_SIG_LEN bytes will be read from - * this. - * \param out The buffer where the candidate public key will be - * stored. Must be at least #MBEDTLS_LMOTS_N_HASH_LEN - * bytes in size. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_calculate_public_key_candidate(const mbedtls_lmots_parameters_t *params, - const unsigned char *msg, - size_t msg_size, - const unsigned char *sig, - size_t sig_size, - unsigned char *out, - size_t out_size, - size_t *out_len); - -/** - * \brief This function verifies a LMOTS signature, using a - * LMOTS context that contains a public key. - * - * \warning This function is **not intended for use in - * production**, due to as-yet unsolved problems with - * handling stateful keys. The API for this function - * may change considerably in future versions. - * - * \note Before this function is called, the context must - * have been initialized and must contain a public key - * (either by import or calculation from a private - * key). - * - * \param ctx The initialized LMOTS context from which the public - * key will be read. - * \param msg The buffer from which the message will be read. - * \param msg_size The size of the message that will be read. - * \param sig The buf from which the signature will be read. - * #MBEDTLS_LMOTS_SIG_LEN bytes will be read from - * this. - * - * \return \c 0 on successful verification. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_verify(const mbedtls_lmots_public_t *ctx, - const unsigned char *msg, - size_t msg_size, const unsigned char *sig, - size_t sig_size); - -#if defined(MBEDTLS_LMS_PRIVATE) - -/** - * \brief This function initializes a private LMOTS context - * - * \param ctx The uninitialized LMOTS context that will then be - * initialized. - */ -void mbedtls_lmots_private_init(mbedtls_lmots_private_t *ctx); - -/** - * \brief This function uninitializes a private LMOTS context - * - * \param ctx The initialized LMOTS context that will then be - * uninitialized. - */ -void mbedtls_lmots_private_free(mbedtls_lmots_private_t *ctx); - -/** - * \brief This function calculates an LMOTS private key, and - * stores in into an LMOTS context. - * - * \warning This function is **not intended for use in - * production**, due to as-yet unsolved problems with - * handling stateful keys. The API for this function - * may change considerably in future versions. - * - * \note The seed must have at least 256 bits of entropy. - * - * \param ctx The initialized LMOTS context to generate the key - * into. - * \param I_key_identifier The key identifier of the key, as a 16-byte string. - * \param q_leaf_identifier The leaf identifier of key. If this LMOTS key is - * not being used as part of an LMS key, this should - * be set to 0. - * \param seed The seed used to deterministically generate the - * key. - * \param seed_size The length of the seed. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_generate_private_key(mbedtls_lmots_private_t *ctx, - mbedtls_lmots_algorithm_type_t type, - const unsigned char I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN], - uint32_t q_leaf_identifier, - const unsigned char *seed, - size_t seed_size); - -/** - * \brief This function generates an LMOTS public key from a - * LMOTS context that already contains a private key. - * - * \note Before this function is called, the context must - * have been initialized and the context must contain - * a private key. - * - * \param ctx The initialized LMOTS context to generate the key - * from and store it into. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_calculate_public_key(mbedtls_lmots_public_t *ctx, - const mbedtls_lmots_private_t *priv_ctx); - -/** - * \brief This function creates a LMOTS signature, using a - * LMOTS context that contains a private key. - * - * \note Before this function is called, the context must - * have been initialized and must contain a private - * key. - * - * \note LMOTS private keys can only be used once, otherwise - * attackers may be able to create forged signatures. - * If the signing operation is successful, the private - * key in the context will be erased, and no further - * signing will be possible until another private key - * is loaded - * - * \param ctx The initialized LMOTS context from which the - * private key will be read. - * \param f_rng The RNG function to be used for signature - * generation. - * \param p_rng The RNG context to be passed to f_rng - * \param msg The buffer from which the message will be read. - * \param msg_size The size of the message that will be read. - * \param sig The buf into which the signature will be stored. - * Must be at least #MBEDTLS_LMOTS_SIG_LEN in size. - * - * \return \c 0 on success. - * \return A non-zero error code on failure. - */ -int mbedtls_lmots_sign(mbedtls_lmots_private_t *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, const unsigned char *msg, size_t msg_size, - unsigned char *sig, size_t sig_size, size_t *sig_len); - -#endif /* defined(MBEDTLS_LMS_PRIVATE) */ - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_LMOTS_H */ +/** + * \file lmots.h + * + * \brief This file provides an API for the LM-OTS post-quantum-safe one-time + * public-key signature scheme as defined in RFC8554 and NIST.SP.200-208. + * This implementation currently only supports a single parameter set + * MBEDTLS_LMOTS_SHA256_N32_W8 in order to reduce complexity. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_LMOTS_H +#define MBEDTLS_LMOTS_H + +#include "mbedtls/build_info.h" + +#include "psa/crypto.h" + +#include "mbedtls/lms.h" + +#include +#include + + +#define MBEDTLS_LMOTS_PUBLIC_KEY_LEN(type) (MBEDTLS_LMOTS_TYPE_LEN + \ + MBEDTLS_LMOTS_I_KEY_ID_LEN + \ + MBEDTLS_LMOTS_Q_LEAF_ID_LEN + \ + MBEDTLS_LMOTS_N_HASH_LEN(type)) + +#define MBEDTLS_LMOTS_SIG_TYPE_OFFSET (0) +#define MBEDTLS_LMOTS_SIG_C_RANDOM_OFFSET (MBEDTLS_LMOTS_SIG_TYPE_OFFSET + \ + MBEDTLS_LMOTS_TYPE_LEN) +#define MBEDTLS_LMOTS_SIG_SIGNATURE_OFFSET(type) (MBEDTLS_LMOTS_SIG_C_RANDOM_OFFSET + \ + MBEDTLS_LMOTS_C_RANDOM_VALUE_LEN(type)) + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(MBEDTLS_TEST_HOOKS) +extern int (*mbedtls_lmots_sign_private_key_invalidated_hook)(unsigned char *); +#endif /* defined(MBEDTLS_TEST_HOOKS) */ + +/** + * \brief This function converts an unsigned int into a + * network-byte-order (big endian) string. + * + * \param val The unsigned integer value + * \param len The length of the string. + * \param bytes The string to output into. + */ +void mbedtls_lms_unsigned_int_to_network_bytes(unsigned int val, size_t len, + unsigned char *bytes); + +/** + * \brief This function converts a network-byte-order + * (big endian) string into an unsigned integer. + * + * \param len The length of the string. + * \param bytes The string. + * + * \return The corresponding LMS error code. + */ +unsigned int mbedtls_lms_network_bytes_to_unsigned_int(size_t len, + const unsigned char *bytes); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief This function converts a \ref psa_status_t to a + * low-level LMS error code. + * + * \param status The psa_status_t to convert + * + * \return The corresponding LMS error code. + */ +int MBEDTLS_DEPRECATED mbedtls_lms_error_from_psa(psa_status_t status); +#endif + +/** + * \brief This function initializes a public LMOTS context + * + * \param ctx The uninitialized LMOTS context that will then be + * initialized. + */ +void mbedtls_lmots_public_init(mbedtls_lmots_public_t *ctx); + +/** + * \brief This function uninitializes a public LMOTS context + * + * \param ctx The initialized LMOTS context that will then be + * uninitialized. + */ +void mbedtls_lmots_public_free(mbedtls_lmots_public_t *ctx); + +/** + * \brief This function imports an LMOTS public key into a + * LMOTS context. + * + * \note Before this function is called, the context must + * have been initialized. + * + * \note See IETF RFC8554 for details of the encoding of + * this public key. + * + * \param ctx The initialized LMOTS context store the key in. + * \param key The buffer from which the key will be read. + * #MBEDTLS_LMOTS_PUBLIC_KEY_LEN bytes will be read + * from this. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_import_public_key(mbedtls_lmots_public_t *ctx, + const unsigned char *key, size_t key_size); + +/** + * \brief This function exports an LMOTS public key from a + * LMOTS context that already contains a public key. + * + * \note Before this function is called, the context must + * have been initialized and the context must contain + * a public key. + * + * \note See IETF RFC8554 for details of the encoding of + * this public key. + * + * \param ctx The initialized LMOTS context that contains the + * public key. + * \param key The buffer into which the key will be output. Must + * be at least #MBEDTLS_LMOTS_PUBLIC_KEY_LEN in size. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_export_public_key(const mbedtls_lmots_public_t *ctx, + unsigned char *key, size_t key_size, + size_t *key_len); + +/** + * \brief This function creates a candidate public key from + * an LMOTS signature. This can then be compared to + * the real public key to determine the validity of + * the signature. + * + * \note This function is exposed publicly to be used in LMS + * signature verification, it is expected that + * mbedtls_lmots_verify will be used for LMOTS + * signature verification. + * + * \param params The LMOTS parameter set, q and I values as an + * mbedtls_lmots_parameters_t struct. + * \param msg The buffer from which the message will be read. + * \param msg_size The size of the message that will be read. + * \param sig The buffer from which the signature will be read. + * #MBEDTLS_LMOTS_SIG_LEN bytes will be read from + * this. + * \param out The buffer where the candidate public key will be + * stored. Must be at least #MBEDTLS_LMOTS_N_HASH_LEN + * bytes in size. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_calculate_public_key_candidate(const mbedtls_lmots_parameters_t *params, + const unsigned char *msg, + size_t msg_size, + const unsigned char *sig, + size_t sig_size, + unsigned char *out, + size_t out_size, + size_t *out_len); + +/** + * \brief This function verifies a LMOTS signature, using a + * LMOTS context that contains a public key. + * + * \warning This function is **not intended for use in + * production**, due to as-yet unsolved problems with + * handling stateful keys. The API for this function + * may change considerably in future versions. + * + * \note Before this function is called, the context must + * have been initialized and must contain a public key + * (either by import or calculation from a private + * key). + * + * \param ctx The initialized LMOTS context from which the public + * key will be read. + * \param msg The buffer from which the message will be read. + * \param msg_size The size of the message that will be read. + * \param sig The buf from which the signature will be read. + * #MBEDTLS_LMOTS_SIG_LEN bytes will be read from + * this. + * + * \return \c 0 on successful verification. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_verify(const mbedtls_lmots_public_t *ctx, + const unsigned char *msg, + size_t msg_size, const unsigned char *sig, + size_t sig_size); + +#if defined(MBEDTLS_LMS_PRIVATE) + +/** + * \brief This function initializes a private LMOTS context + * + * \param ctx The uninitialized LMOTS context that will then be + * initialized. + */ +void mbedtls_lmots_private_init(mbedtls_lmots_private_t *ctx); + +/** + * \brief This function uninitializes a private LMOTS context + * + * \param ctx The initialized LMOTS context that will then be + * uninitialized. + */ +void mbedtls_lmots_private_free(mbedtls_lmots_private_t *ctx); + +/** + * \brief This function calculates an LMOTS private key, and + * stores in into an LMOTS context. + * + * \warning This function is **not intended for use in + * production**, due to as-yet unsolved problems with + * handling stateful keys. The API for this function + * may change considerably in future versions. + * + * \note The seed must have at least 256 bits of entropy. + * + * \param ctx The initialized LMOTS context to generate the key + * into. + * \param I_key_identifier The key identifier of the key, as a 16-byte string. + * \param q_leaf_identifier The leaf identifier of key. If this LMOTS key is + * not being used as part of an LMS key, this should + * be set to 0. + * \param seed The seed used to deterministically generate the + * key. + * \param seed_size The length of the seed. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_generate_private_key(mbedtls_lmots_private_t *ctx, + mbedtls_lmots_algorithm_type_t type, + const unsigned char I_key_identifier[MBEDTLS_LMOTS_I_KEY_ID_LEN], + uint32_t q_leaf_identifier, + const unsigned char *seed, + size_t seed_size); + +/** + * \brief This function generates an LMOTS public key from a + * LMOTS context that already contains a private key. + * + * \note Before this function is called, the context must + * have been initialized and the context must contain + * a private key. + * + * \param ctx The initialized LMOTS context to generate the key + * from and store it into. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_calculate_public_key(mbedtls_lmots_public_t *ctx, + const mbedtls_lmots_private_t *priv_ctx); + +/** + * \brief This function creates a LMOTS signature, using a + * LMOTS context that contains a private key. + * + * \note Before this function is called, the context must + * have been initialized and must contain a private + * key. + * + * \note LMOTS private keys can only be used once, otherwise + * attackers may be able to create forged signatures. + * If the signing operation is successful, the private + * key in the context will be erased, and no further + * signing will be possible until another private key + * is loaded + * + * \param ctx The initialized LMOTS context from which the + * private key will be read. + * \param f_rng The RNG function to be used for signature + * generation. + * \param p_rng The RNG context to be passed to f_rng + * \param msg The buffer from which the message will be read. + * \param msg_size The size of the message that will be read. + * \param sig The buf into which the signature will be stored. + * Must be at least #MBEDTLS_LMOTS_SIG_LEN in size. + * + * \return \c 0 on success. + * \return A non-zero error code on failure. + */ +int mbedtls_lmots_sign(mbedtls_lmots_private_t *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, const unsigned char *msg, size_t msg_size, + unsigned char *sig, size_t sig_size, size_t *sig_len); + +#endif /* defined(MBEDTLS_LMS_PRIVATE) */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_LMOTS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_psa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_psa.h index 8e00bb1..71fdfb1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_psa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_psa.h @@ -1,75 +1,75 @@ -/** - * Translation between MD and PSA identifiers (algorithms, errors). - * - * Note: this internal module will go away when everything becomes based on - * PSA Crypto; it is a helper for the transition period. - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_MD_PSA_H -#define MBEDTLS_MD_PSA_H - -#include "common.h" - -#include "mbedtls/md.h" -#include "psa/crypto.h" - -/** - * \brief This function returns the PSA algorithm identifier - * associated with the given digest type. - * - * \param md_type The type of digest to search for. Must not be NONE. - * - * \warning If \p md_type is \c MBEDTLS_MD_NONE, this function will - * not return \c PSA_ALG_NONE, but an invalid algorithm. - * - * \warning This function does not check if the algorithm is - * supported, it always returns the corresponding identifier. - * - * \return The PSA algorithm identifier associated with \p md_type, - * regardless of whether it is supported or not. - */ -static inline psa_algorithm_t mbedtls_md_psa_alg_from_type(mbedtls_md_type_t md_type) -{ - return PSA_ALG_CATEGORY_HASH | (psa_algorithm_t) md_type; -} - -/** - * \brief This function returns the given digest type - * associated with the PSA algorithm identifier. - * - * \param psa_alg The PSA algorithm identifier to search for. - * - * \warning This function does not check if the algorithm is - * supported, it always returns the corresponding identifier. - * - * \return The MD type associated with \p psa_alg, - * regardless of whether it is supported or not. - */ -static inline mbedtls_md_type_t mbedtls_md_type_from_psa_alg(psa_algorithm_t psa_alg) -{ - return (mbedtls_md_type_t) (psa_alg & PSA_ALG_HASH_MASK); -} - -/** Convert PSA status to MD error code. - * - * \param status PSA status. - * - * \return The corresponding MD error code, - */ -int mbedtls_md_error_from_psa(psa_status_t status); - -#endif /* MBEDTLS_MD_PSA_H */ +/** + * Translation between MD and PSA identifiers (algorithms, errors). + * + * Note: this internal module will go away when everything becomes based on + * PSA Crypto; it is a helper for the transition period. + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_MD_PSA_H +#define MBEDTLS_MD_PSA_H + +#include "common.h" + +#include "mbedtls/md.h" +#include "psa/crypto.h" + +/** + * \brief This function returns the PSA algorithm identifier + * associated with the given digest type. + * + * \param md_type The type of digest to search for. Must not be NONE. + * + * \warning If \p md_type is \c MBEDTLS_MD_NONE, this function will + * not return \c PSA_ALG_NONE, but an invalid algorithm. + * + * \warning This function does not check if the algorithm is + * supported, it always returns the corresponding identifier. + * + * \return The PSA algorithm identifier associated with \p md_type, + * regardless of whether it is supported or not. + */ +static inline psa_algorithm_t mbedtls_md_psa_alg_from_type(mbedtls_md_type_t md_type) +{ + return PSA_ALG_CATEGORY_HASH | (psa_algorithm_t) md_type; +} + +/** + * \brief This function returns the given digest type + * associated with the PSA algorithm identifier. + * + * \param psa_alg The PSA algorithm identifier to search for. + * + * \warning This function does not check if the algorithm is + * supported, it always returns the corresponding identifier. + * + * \return The MD type associated with \p psa_alg, + * regardless of whether it is supported or not. + */ +static inline mbedtls_md_type_t mbedtls_md_type_from_psa_alg(psa_algorithm_t psa_alg) +{ + return (mbedtls_md_type_t) (psa_alg & PSA_ALG_HASH_MASK); +} + +/** Convert PSA status to MD error code. + * + * \param status PSA status. + * + * \return The corresponding MD error code, + */ +int mbedtls_md_error_from_psa(psa_status_t status); + +#endif /* MBEDTLS_MD_PSA_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_wrap.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_wrap.h index 166b43b..0ec5906 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_wrap.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/md_wrap.h @@ -1,58 +1,58 @@ -/** - * \file md_wrap.h - * - * \brief Message digest wrappers. - * - * \warning This in an internal header. Do not include directly. - * - * \author Adriaan de Jong - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_MD_WRAP_H -#define MBEDTLS_MD_WRAP_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/md.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * Message digest information. - * Allows message digest functions to be called in a generic way. - */ -struct mbedtls_md_info_t { - /** Digest identifier */ - mbedtls_md_type_t type; - - /** Output length of the digest function in bytes */ - unsigned char size; - -#if defined(MBEDTLS_MD_C) - /** Block length of the digest function in bytes */ - unsigned char block_size; -#endif -}; - -#ifdef __cplusplus -} -#endif - -#endif /* MBEDTLS_MD_WRAP_H */ +/** + * \file md_wrap.h + * + * \brief Message digest wrappers. + * + * \warning This in an internal header. Do not include directly. + * + * \author Adriaan de Jong + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_MD_WRAP_H +#define MBEDTLS_MD_WRAP_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/md.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Message digest information. + * Allows message digest functions to be called in a generic way. + */ +struct mbedtls_md_info_t { + /** Digest identifier */ + mbedtls_md_type_t type; + + /** Output length of the digest function in bytes */ + unsigned char size; + +#if defined(MBEDTLS_MD_C) + /** Block length of the digest function in bytes */ + unsigned char block_size; +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_MD_WRAP_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_common.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_common.h index 301d525..1cbd8ed 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_common.h @@ -1,195 +1,195 @@ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of Mbed TLS (https://tls.mbed.org) - */ - -/** - * \file mps_common.h - * - * \brief Common functions and macros used by MPS - */ - -#ifndef MBEDTLS_MPS_COMMON_H -#define MBEDTLS_MPS_COMMON_H - -#include "mps_error.h" - -#include - -/** - * \name SECTION: MPS Configuration - * - * \{ - */ - -/*! This flag controls whether the MPS-internal components - * (reader, writer, Layer 1-3) perform validation of the - * expected abstract state at the entry of API calls. - * - * Context: All MPS API functions impose assumptions/preconditions on the - * context on which they operate. For example, every structure has a notion of - * state integrity which is established by `xxx_init()` and preserved by any - * calls to the MPS API which satisfy their preconditions and either succeed, - * or fail with an error code which is explicitly documented to not corrupt - * structure integrity (such as WANT_READ and WANT_WRITE); - * apart from `xxx_init()` any function assumes state integrity as a - * precondition (but usually more). If any of the preconditions is violated, - * the function's behavior is entirely undefined. - * In addition to state integrity, all MPS structures have a more refined - * notion of abstract state that the API operates on. For example, all layers - * have a notion of 'abstract read state' which indicates if incoming data has - * been passed to the user, e.g. through mps_l2_read_start() for Layer 2 - * or mps_l3_read() in Layer 3. After such a call, it doesn't make sense to - * call these reading functions again until the incoming data has been - * explicitly 'consumed', e.g. through mps_l2_read_consume() for Layer 2 or - * mps_l3_read_consume() on Layer 3. However, even if it doesn't make sense, - * it's a design choice whether the API should fail gracefully on such - * non-sensical calls or not, and that's what this option is about: - * - * This option determines whether the expected abstract state - * is part of the API preconditions or not: If the option is set, - * then the abstract state is not part of the precondition and is - * thus required to be validated by the implementation. If an unexpected - * abstract state is encountered, the implementation must fail gracefully - * with error #MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED. - * Conversely, if this option is not set, then the expected abstract state - * is included in the preconditions of the respective API calls, and - * an implementation's behaviour is undefined if the abstract state is - * not as expected. - * - * For example: Enabling this makes mps_l2_read_done() fail if - * no incoming record is currently open; disabling this would - * lead to undefined behavior in this case. - * - * Comment this to remove state validation. - */ -#define MBEDTLS_MPS_STATE_VALIDATION - -/*! This flag enables/disables assertions on the internal state of MPS. - * - * Assertions are sanity checks that should never trigger when MPS - * is used within the bounds of its API and preconditions. - * - * Enabling this increases security by limiting the scope of - * potential bugs, but comes at the cost of increased code size. - * - * Note: So far, there is no guiding principle as to what - * expected conditions merit an assertion, and which don't. - * - * Comment this to disable assertions. - */ -#define MBEDTLS_MPS_ENABLE_ASSERTIONS - -/*! This flag controls whether tracing for MPS should be enabled. */ -//#define MBEDTLS_MPS_ENABLE_TRACE - -#if defined(MBEDTLS_MPS_STATE_VALIDATION) - -#define MBEDTLS_MPS_STATE_VALIDATE_RAW(cond, string) \ - do \ - { \ - if (!(cond)) \ - { \ - MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_ERROR, string); \ - MBEDTLS_MPS_TRACE_RETURN(MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED); \ - } \ - } while (0) - -#else /* MBEDTLS_MPS_STATE_VALIDATION */ - -#define MBEDTLS_MPS_STATE_VALIDATE_RAW(cond, string) \ - do \ - { \ - (cond); \ - } while (0) - -#endif /* MBEDTLS_MPS_STATE_VALIDATION */ - -#if defined(MBEDTLS_MPS_ENABLE_ASSERTIONS) - -#define MBEDTLS_MPS_ASSERT_RAW(cond, string) \ - do \ - { \ - if (!(cond)) \ - { \ - MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_ERROR, string); \ - MBEDTLS_MPS_TRACE_RETURN(MBEDTLS_ERR_MPS_INTERNAL_ERROR); \ - } \ - } while (0) - -#else /* MBEDTLS_MPS_ENABLE_ASSERTIONS */ - -#define MBEDTLS_MPS_ASSERT_RAW(cond, string) do {} while (0) - -#endif /* MBEDTLS_MPS_ENABLE_ASSERTIONS */ - - -/* \} name SECTION: MPS Configuration */ - -/** - * \name SECTION: Common types - * - * Various common types used throughout MPS. - * \{ - */ - -/** \brief The type of buffer sizes and offsets used in MPS structures. - * - * This is an unsigned integer type that should be large enough to - * hold the length of any buffer or message processed by MPS. - * - * The reason to pick a value as small as possible here is - * to reduce the size of MPS structures. - * - * \warning Care has to be taken when using a narrower type - * than ::mbedtls_mps_size_t here because of - * potential truncation during conversion. - * - * \warning Handshake messages in TLS may be up to 2^24 ~ 16Mb in size. - * If mbedtls_mps_[opt_]stored_size_t is smaller than that, the - * maximum handshake message is restricted accordingly. - * - * For now, we use the default type of size_t throughout, and the use of - * smaller types or different types for ::mbedtls_mps_size_t and - * ::mbedtls_mps_stored_size_t is not yet supported. - * - */ -typedef size_t mbedtls_mps_stored_size_t; -#define MBEDTLS_MPS_STORED_SIZE_MAX (SIZE_MAX) - -/** \brief The type of buffer sizes and offsets used in the MPS API - * and implementation. - * - * This must be at least as wide as ::mbedtls_stored_size_t but - * may be chosen to be strictly larger if more suitable for the - * target architecture. - * - * For example, in a test build for ARM Thumb, using uint_fast16_t - * instead of uint16_t reduced the code size from 1060 Byte to 962 Byte, - * so almost 10%. - */ -typedef size_t mbedtls_mps_size_t; -#define MBEDTLS_MPS_SIZE_MAX (SIZE_MAX) - -#if MBEDTLS_MPS_STORED_SIZE_MAX > MBEDTLS_MPS_SIZE_MAX -#error "Misconfiguration of mbedtls_mps_size_t and mbedtls_mps_stored_size_t." -#endif - -/* \} SECTION: Common types */ - - -#endif /* MBEDTLS_MPS_COMMON_H */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +/** + * \file mps_common.h + * + * \brief Common functions and macros used by MPS + */ + +#ifndef MBEDTLS_MPS_COMMON_H +#define MBEDTLS_MPS_COMMON_H + +#include "mps_error.h" + +#include + +/** + * \name SECTION: MPS Configuration + * + * \{ + */ + +/*! This flag controls whether the MPS-internal components + * (reader, writer, Layer 1-3) perform validation of the + * expected abstract state at the entry of API calls. + * + * Context: All MPS API functions impose assumptions/preconditions on the + * context on which they operate. For example, every structure has a notion of + * state integrity which is established by `xxx_init()` and preserved by any + * calls to the MPS API which satisfy their preconditions and either succeed, + * or fail with an error code which is explicitly documented to not corrupt + * structure integrity (such as WANT_READ and WANT_WRITE); + * apart from `xxx_init()` any function assumes state integrity as a + * precondition (but usually more). If any of the preconditions is violated, + * the function's behavior is entirely undefined. + * In addition to state integrity, all MPS structures have a more refined + * notion of abstract state that the API operates on. For example, all layers + * have a notion of 'abstract read state' which indicates if incoming data has + * been passed to the user, e.g. through mps_l2_read_start() for Layer 2 + * or mps_l3_read() in Layer 3. After such a call, it doesn't make sense to + * call these reading functions again until the incoming data has been + * explicitly 'consumed', e.g. through mps_l2_read_consume() for Layer 2 or + * mps_l3_read_consume() on Layer 3. However, even if it doesn't make sense, + * it's a design choice whether the API should fail gracefully on such + * non-sensical calls or not, and that's what this option is about: + * + * This option determines whether the expected abstract state + * is part of the API preconditions or not: If the option is set, + * then the abstract state is not part of the precondition and is + * thus required to be validated by the implementation. If an unexpected + * abstract state is encountered, the implementation must fail gracefully + * with error #MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED. + * Conversely, if this option is not set, then the expected abstract state + * is included in the preconditions of the respective API calls, and + * an implementation's behaviour is undefined if the abstract state is + * not as expected. + * + * For example: Enabling this makes mps_l2_read_done() fail if + * no incoming record is currently open; disabling this would + * lead to undefined behavior in this case. + * + * Comment this to remove state validation. + */ +#define MBEDTLS_MPS_STATE_VALIDATION + +/*! This flag enables/disables assertions on the internal state of MPS. + * + * Assertions are sanity checks that should never trigger when MPS + * is used within the bounds of its API and preconditions. + * + * Enabling this increases security by limiting the scope of + * potential bugs, but comes at the cost of increased code size. + * + * Note: So far, there is no guiding principle as to what + * expected conditions merit an assertion, and which don't. + * + * Comment this to disable assertions. + */ +#define MBEDTLS_MPS_ENABLE_ASSERTIONS + +/*! This flag controls whether tracing for MPS should be enabled. */ +//#define MBEDTLS_MPS_ENABLE_TRACE + +#if defined(MBEDTLS_MPS_STATE_VALIDATION) + +#define MBEDTLS_MPS_STATE_VALIDATE_RAW(cond, string) \ + do \ + { \ + if (!(cond)) \ + { \ + MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_ERROR, string); \ + MBEDTLS_MPS_TRACE_RETURN(MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED); \ + } \ + } while (0) + +#else /* MBEDTLS_MPS_STATE_VALIDATION */ + +#define MBEDTLS_MPS_STATE_VALIDATE_RAW(cond, string) \ + do \ + { \ + (cond); \ + } while (0) + +#endif /* MBEDTLS_MPS_STATE_VALIDATION */ + +#if defined(MBEDTLS_MPS_ENABLE_ASSERTIONS) + +#define MBEDTLS_MPS_ASSERT_RAW(cond, string) \ + do \ + { \ + if (!(cond)) \ + { \ + MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_ERROR, string); \ + MBEDTLS_MPS_TRACE_RETURN(MBEDTLS_ERR_MPS_INTERNAL_ERROR); \ + } \ + } while (0) + +#else /* MBEDTLS_MPS_ENABLE_ASSERTIONS */ + +#define MBEDTLS_MPS_ASSERT_RAW(cond, string) do {} while (0) + +#endif /* MBEDTLS_MPS_ENABLE_ASSERTIONS */ + + +/* \} name SECTION: MPS Configuration */ + +/** + * \name SECTION: Common types + * + * Various common types used throughout MPS. + * \{ + */ + +/** \brief The type of buffer sizes and offsets used in MPS structures. + * + * This is an unsigned integer type that should be large enough to + * hold the length of any buffer or message processed by MPS. + * + * The reason to pick a value as small as possible here is + * to reduce the size of MPS structures. + * + * \warning Care has to be taken when using a narrower type + * than ::mbedtls_mps_size_t here because of + * potential truncation during conversion. + * + * \warning Handshake messages in TLS may be up to 2^24 ~ 16Mb in size. + * If mbedtls_mps_[opt_]stored_size_t is smaller than that, the + * maximum handshake message is restricted accordingly. + * + * For now, we use the default type of size_t throughout, and the use of + * smaller types or different types for ::mbedtls_mps_size_t and + * ::mbedtls_mps_stored_size_t is not yet supported. + * + */ +typedef size_t mbedtls_mps_stored_size_t; +#define MBEDTLS_MPS_STORED_SIZE_MAX (SIZE_MAX) + +/** \brief The type of buffer sizes and offsets used in the MPS API + * and implementation. + * + * This must be at least as wide as ::mbedtls_stored_size_t but + * may be chosen to be strictly larger if more suitable for the + * target architecture. + * + * For example, in a test build for ARM Thumb, using uint_fast16_t + * instead of uint16_t reduced the code size from 1060 Byte to 962 Byte, + * so almost 10%. + */ +typedef size_t mbedtls_mps_size_t; +#define MBEDTLS_MPS_SIZE_MAX (SIZE_MAX) + +#if MBEDTLS_MPS_STORED_SIZE_MAX > MBEDTLS_MPS_SIZE_MAX +#error "Misconfiguration of mbedtls_mps_size_t and mbedtls_mps_stored_size_t." +#endif + +/* \} SECTION: Common types */ + + +#endif /* MBEDTLS_MPS_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_error.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_error.h index 5113959..4e2f10e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_error.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_error.h @@ -1,103 +1,103 @@ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of Mbed TLS (https://tls.mbed.org) - */ - -/** - * \file mps_error.h - * - * \brief Error codes used by MPS - */ - -#ifndef MBEDTLS_MPS_ERROR_H -#define MBEDTLS_MPS_ERROR_H - - -/* TODO: The error code allocation needs to be revisited: - * - * - Should we make (some of) the MPS Reader error codes public? - * If so, we need to adjust MBEDTLS_MPS_READER_MAKE_ERROR() to hit - * a gap in the Mbed TLS public error space. - * If not, we have to make sure we don't forward those errors - * at the level of the public API -- no risk at the moment as - * long as MPS is an experimental component not accessible from - * public API. - */ - -/** - * \name SECTION: MPS general error codes - * - * \{ - */ - -#ifndef MBEDTLS_MPS_ERR_BASE -#define MBEDTLS_MPS_ERR_BASE (0) -#endif - -#define MBEDTLS_MPS_MAKE_ERROR(code) \ - (-(MBEDTLS_MPS_ERR_BASE | (code))) - -#define MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED MBEDTLS_MPS_MAKE_ERROR(0x1) -#define MBEDTLS_ERR_MPS_INTERNAL_ERROR MBEDTLS_MPS_MAKE_ERROR(0x2) - -/* \} name SECTION: MPS general error codes */ - -/** - * \name SECTION: MPS Reader error codes - * - * \{ - */ - -#ifndef MBEDTLS_MPS_READER_ERR_BASE -#define MBEDTLS_MPS_READER_ERR_BASE (1 << 8) -#endif - -#define MBEDTLS_MPS_READER_MAKE_ERROR(code) \ - (-(MBEDTLS_MPS_READER_ERR_BASE | (code))) - -/*! An attempt to reclaim the data buffer from a reader failed because - * the user hasn't yet read and committed all of it. */ -#define MBEDTLS_ERR_MPS_READER_DATA_LEFT MBEDTLS_MPS_READER_MAKE_ERROR(0x1) - -/*! An invalid argument was passed to the reader. */ -#define MBEDTLS_ERR_MPS_READER_INVALID_ARG MBEDTLS_MPS_READER_MAKE_ERROR(0x2) - -/*! An attempt to move a reader to consuming mode through mbedtls_mps_reader_feed() - * after pausing failed because the provided data is not sufficient to serve the - * read requests that led to the pausing. */ -#define MBEDTLS_ERR_MPS_READER_NEED_MORE MBEDTLS_MPS_READER_MAKE_ERROR(0x3) - -/*! A get request failed because not enough data is available in the reader. */ -#define MBEDTLS_ERR_MPS_READER_OUT_OF_DATA MBEDTLS_MPS_READER_MAKE_ERROR(0x4) - -/*!< A get request after pausing and reactivating the reader failed because - * the request is not in line with the request made prior to pausing. The user - * must not change it's 'strategy' after pausing and reactivating a reader. */ -#define MBEDTLS_ERR_MPS_READER_INCONSISTENT_REQUESTS MBEDTLS_MPS_READER_MAKE_ERROR(0x5) - -/*! An attempt to reclaim the data buffer from a reader failed because the reader - * has no accumulator it can use to backup the data that hasn't been processed. */ -#define MBEDTLS_ERR_MPS_READER_NEED_ACCUMULATOR MBEDTLS_MPS_READER_MAKE_ERROR(0x6) - -/*! An attempt to reclaim the data buffer from a reader failed because the - * accumulator passed to the reader is not large enough to hold both the - * data that hasn't been processed and the excess of the last read-request. */ -#define MBEDTLS_ERR_MPS_READER_ACCUMULATOR_TOO_SMALL MBEDTLS_MPS_READER_MAKE_ERROR(0x7) - -/* \} name SECTION: MPS Reader error codes */ - -#endif /* MBEDTLS_MPS_ERROR_H */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +/** + * \file mps_error.h + * + * \brief Error codes used by MPS + */ + +#ifndef MBEDTLS_MPS_ERROR_H +#define MBEDTLS_MPS_ERROR_H + + +/* TODO: The error code allocation needs to be revisited: + * + * - Should we make (some of) the MPS Reader error codes public? + * If so, we need to adjust MBEDTLS_MPS_READER_MAKE_ERROR() to hit + * a gap in the Mbed TLS public error space. + * If not, we have to make sure we don't forward those errors + * at the level of the public API -- no risk at the moment as + * long as MPS is an experimental component not accessible from + * public API. + */ + +/** + * \name SECTION: MPS general error codes + * + * \{ + */ + +#ifndef MBEDTLS_MPS_ERR_BASE +#define MBEDTLS_MPS_ERR_BASE (0) +#endif + +#define MBEDTLS_MPS_MAKE_ERROR(code) \ + (-(MBEDTLS_MPS_ERR_BASE | (code))) + +#define MBEDTLS_ERR_MPS_OPERATION_UNEXPECTED MBEDTLS_MPS_MAKE_ERROR(0x1) +#define MBEDTLS_ERR_MPS_INTERNAL_ERROR MBEDTLS_MPS_MAKE_ERROR(0x2) + +/* \} name SECTION: MPS general error codes */ + +/** + * \name SECTION: MPS Reader error codes + * + * \{ + */ + +#ifndef MBEDTLS_MPS_READER_ERR_BASE +#define MBEDTLS_MPS_READER_ERR_BASE (1 << 8) +#endif + +#define MBEDTLS_MPS_READER_MAKE_ERROR(code) \ + (-(MBEDTLS_MPS_READER_ERR_BASE | (code))) + +/*! An attempt to reclaim the data buffer from a reader failed because + * the user hasn't yet read and committed all of it. */ +#define MBEDTLS_ERR_MPS_READER_DATA_LEFT MBEDTLS_MPS_READER_MAKE_ERROR(0x1) + +/*! An invalid argument was passed to the reader. */ +#define MBEDTLS_ERR_MPS_READER_INVALID_ARG MBEDTLS_MPS_READER_MAKE_ERROR(0x2) + +/*! An attempt to move a reader to consuming mode through mbedtls_mps_reader_feed() + * after pausing failed because the provided data is not sufficient to serve the + * read requests that led to the pausing. */ +#define MBEDTLS_ERR_MPS_READER_NEED_MORE MBEDTLS_MPS_READER_MAKE_ERROR(0x3) + +/*! A get request failed because not enough data is available in the reader. */ +#define MBEDTLS_ERR_MPS_READER_OUT_OF_DATA MBEDTLS_MPS_READER_MAKE_ERROR(0x4) + +/*!< A get request after pausing and reactivating the reader failed because + * the request is not in line with the request made prior to pausing. The user + * must not change it's 'strategy' after pausing and reactivating a reader. */ +#define MBEDTLS_ERR_MPS_READER_INCONSISTENT_REQUESTS MBEDTLS_MPS_READER_MAKE_ERROR(0x5) + +/*! An attempt to reclaim the data buffer from a reader failed because the reader + * has no accumulator it can use to backup the data that hasn't been processed. */ +#define MBEDTLS_ERR_MPS_READER_NEED_ACCUMULATOR MBEDTLS_MPS_READER_MAKE_ERROR(0x6) + +/*! An attempt to reclaim the data buffer from a reader failed because the + * accumulator passed to the reader is not large enough to hold both the + * data that hasn't been processed and the excess of the last read-request. */ +#define MBEDTLS_ERR_MPS_READER_ACCUMULATOR_TOO_SMALL MBEDTLS_MPS_READER_MAKE_ERROR(0x7) + +/* \} name SECTION: MPS Reader error codes */ + +#endif /* MBEDTLS_MPS_ERROR_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_reader.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_reader.h index bb912ec..83523cb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_reader.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_reader.h @@ -1,380 +1,380 @@ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of Mbed TLS (https://tls.mbed.org) - */ - -/** - * \file mps_reader.h - * - * \brief This file defines reader objects, which together with their - * sibling writer objects form the basis for the communication - * between the various layers of the Mbed TLS messaging stack, - * as well as the communication between the messaging stack and - * the (D)TLS handshake protocol implementation. - * - * Readers provide a means of transferring incoming data from - * a 'producer' providing it in chunks of arbitrary size, to - * a 'consumer' which fetches and processes it in chunks of - * again arbitrary, and potentially different, size. - * - * Readers can thus be seen as datagram-to-stream converters, - * and they abstract away the following two tasks from the user: - * 1. The pointer arithmetic of stepping through a producer- - * provided chunk in smaller chunks. - * 2. The merging of incoming data chunks in case the - * consumer requests data in larger chunks than what the - * producer provides. - * - * The basic abstract flow of operation is the following: - * - Initially, the reader is in 'producing mode'. - * - The producer hands an incoming data buffer to the reader, - * moving it from 'producing' to 'consuming' mode. - * - The consumer subsequently fetches and processes the buffer - * content. Once that's done -- or partially done and a consumer's - * request can't be fulfilled -- the producer revokes the reader's - * access to the incoming data buffer, putting the reader back to - * producing mode. - * - The producer subsequently gathers more incoming data and hands - * it to the reader until it switches back to consuming mode - * if enough data is available for the last consumer request to - * be satisfiable. - * - Repeat the above. - * - * The abstract states of the reader from the producer's and - * consumer's perspective are as follows: - * - * - From the perspective of the consumer, the state of the - * reader consists of the following: - * - A byte stream representing (concatenation of) the data - * received through calls to mbedtls_mps_reader_get(), - * - A marker within that byte stream indicating which data - * can be considered processed, and hence need not be retained, - * when the reader is passed back to the producer via - * mbedtls_mps_reader_reclaim(). - * The marker is set via mbedtls_mps_reader_commit() - * which places it at the end of the current byte stream. - * The consumer need not be aware of the distinction between consumer - * and producer mode, because it only interfaces with the reader - * when the latter is in consuming mode. - * - * - From the perspective of the producer, the reader's state is one of: - * - Attached: The reader is in consuming mode. - * - Unset: No incoming data buffer is currently managed by the reader, - * and all previously handed incoming data buffers have been - * fully processed. More data needs to be fed into the reader - * via mbedtls_mps_reader_feed(). - * - * - Accumulating: No incoming data buffer is currently managed by the - * reader, but some data from the previous incoming data - * buffer hasn't been processed yet and is internally - * held back. - * The Attached state belongs to consuming mode, while the Unset and - * Accumulating states belong to producing mode. - * - * Transitioning from the Unset or Accumulating state to Attached is - * done via successful calls to mbedtls_mps_reader_feed(), while - * transitioning from Attached to either Unset or Accumulating (depending - * on what has been processed) is done via mbedtls_mps_reader_reclaim(). - * - * The following diagram depicts the producer-state progression: - * - * +------------------+ reclaim - * | Unset +<-------------------------------------+ get - * +--------|---------+ | +------+ - * | | | | - * | | | | - * | feed +---------+---+--+ | - * +--------------------------------------> <---+ - * | Attached | - * +--------------------------------------> <---+ - * | feed, enough data available +---------+---+--+ | - * | to serve previous consumer request | | | - * | | | | - * +--------+---------+ | +------+ - * +----> Accumulating |<-------------------------------------+ commit - * | +---+--------------+ reclaim, previous read request - * | | couldn't be fulfilled - * | | - * +--------+ - * feed, need more data to serve - * previous consumer request - * | - * | - * producing mode | consuming mode - * | - * - */ - -#ifndef MBEDTLS_READER_H -#define MBEDTLS_READER_H - -#include - -#include "mps_common.h" -#include "mps_error.h" - -struct mbedtls_mps_reader; -typedef struct mbedtls_mps_reader mbedtls_mps_reader; - -/* - * Structure definitions - */ - -struct mbedtls_mps_reader { - unsigned char *frag; /*!< The fragment of incoming data managed by - * the reader; it is provided to the reader - * through mbedtls_mps_reader_feed(). The reader - * does not own the fragment and does not - * perform any allocation operations on it, - * but does have read and write access to it. - * - * The reader is in consuming mode if - * and only if \c frag is not \c NULL. */ - mbedtls_mps_stored_size_t frag_len; - /*!< The length of the current fragment. - * Must be 0 if \c frag == \c NULL. */ - mbedtls_mps_stored_size_t commit; - /*!< The offset of the last commit, relative - * to the first byte in the fragment, if - * no accumulator is present. If an accumulator - * is present, it is viewed as a prefix to the - * current fragment, and this variable contains - * an offset from the beginning of the accumulator. - * - * This is only used when the reader is in - * consuming mode, i.e. \c frag != \c NULL; - * otherwise, its value is \c 0. */ - mbedtls_mps_stored_size_t end; - /*!< The offset of the end of the last chunk - * passed to the user through a call to - * mbedtls_mps_reader_get(), relative to the first - * byte in the fragment, if no accumulator is - * present. If an accumulator is present, it is - * viewed as a prefix to the current fragment, and - * this variable contains an offset from the - * beginning of the accumulator. - * - * This is only used when the reader is in - * consuming mode, i.e. \c frag != \c NULL; - * otherwise, its value is \c 0. */ - mbedtls_mps_stored_size_t pending; - /*!< The amount of incoming data missing on the - * last call to mbedtls_mps_reader_get(). - * In particular, it is \c 0 if the last call - * was successful. - * If a reader is reclaimed after an - * unsuccessful call to mbedtls_mps_reader_get(), - * this variable is used to have the reader - * remember how much data should be accumulated - * so that the call to mbedtls_mps_reader_get() - * succeeds next time. - * This is only used when the reader is in - * consuming mode, i.e. \c frag != \c NULL; - * otherwise, its value is \c 0. */ - - /* The accumulator is only needed if we need to be able to pause - * the reader. A few bytes could be saved by moving this to a - * separate struct and using a pointer here. */ - - unsigned char *acc; /*!< The accumulator is used to gather incoming - * data if a read-request via mbedtls_mps_reader_get() - * cannot be served from the current fragment. */ - mbedtls_mps_stored_size_t acc_len; - /*!< The total size of the accumulator. */ - mbedtls_mps_stored_size_t acc_available; - /*!< The number of bytes currently gathered in - * the accumulator. This is both used in - * producing and in consuming mode: - * While producing, it is increased until - * it reaches the value of \c acc_remaining below. - * While consuming, it is used to judge if a - * get request can be served from the - * accumulator or not. - * Must not be larger than \c acc_len. */ - union { - mbedtls_mps_stored_size_t acc_remaining; - /*!< This indicates the amount of data still - * to be gathered in the accumulator. It is - * only used in producing mode. - * Must be at most acc_len - acc_available. */ - mbedtls_mps_stored_size_t frag_offset; - /*!< If an accumulator is present and in use, this - * field indicates the offset of the current - * fragment from the beginning of the - * accumulator. If no accumulator is present - * or the accumulator is not in use, this is \c 0. - * It is only used in consuming mode. - * Must not be larger than \c acc_available. */ - } acc_share; -}; - -/* - * API organization: - * A reader object is usually prepared and maintained - * by some lower layer and passed for usage to an upper - * layer, and the API naturally splits according to which - * layer is supposed to use the respective functions. - */ - -/* - * Maintenance API (Lower layer) - */ - -/** - * \brief Initialize a reader object - * - * \param reader The reader to be initialized. - * \param acc The buffer to be used as a temporary accumulator - * in case get requests through mbedtls_mps_reader_get() - * exceed the buffer provided by mbedtls_mps_reader_feed(). - * This buffer is owned by the caller and exclusive use - * for reading and writing is given to the reader for the - * duration of the reader's lifetime. It is thus the caller's - * responsibility to maintain (and not touch) the buffer for - * the lifetime of the reader, and to properly zeroize and - * free the memory after the reader has been destroyed. - * \param acc_len The size in Bytes of \p acc. - * - * \return \c 0 on success. - * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. - */ -int mbedtls_mps_reader_init(mbedtls_mps_reader *reader, - unsigned char *acc, - mbedtls_mps_size_t acc_len); - -/** - * \brief Free a reader object - * - * \param reader The reader to be freed. - * - * \return \c 0 on success. - * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. - */ -int mbedtls_mps_reader_free(mbedtls_mps_reader *reader); - -/** - * \brief Pass chunk of data for the reader to manage. - * - * \param reader The reader context to use. The reader must be - * in producing mode. - * \param buf The buffer to be managed by the reader. - * \param buflen The size in Bytes of \p buffer. - * - * \return \c 0 on success. In this case, the reader will be - * moved to consuming mode and obtains read access - * of \p buf until mbedtls_mps_reader_reclaim() - * is called. It is the responsibility of the caller - * to ensure that the \p buf persists and is not changed - * between successful calls to mbedtls_mps_reader_feed() - * and mbedtls_mps_reader_reclaim(). - * \return \c MBEDTLS_ERR_MPS_READER_NEED_MORE if more input data is - * required to fulfill a previous request to mbedtls_mps_reader_get(). - * In this case, the reader remains in producing mode and - * takes no ownership of the provided buffer (an internal copy - * is made instead). - * \return Another negative \c MBEDTLS_ERR_READER_XXX error code on - * different kinds of failures. - */ -int mbedtls_mps_reader_feed(mbedtls_mps_reader *reader, - unsigned char *buf, - mbedtls_mps_size_t buflen); - -/** - * \brief Reclaim reader's access to the current input buffer. - * - * \param reader The reader context to use. The reader must be - * in consuming mode. - * \param paused If not \c NULL, the integer at address \p paused will be - * modified to indicate whether the reader has been paused - * (value \c 1) or not (value \c 0). Pausing happens if there - * is uncommitted data and a previous request to - * mbedtls_mps_reader_get() has exceeded the bounds of the - * input buffer. - * - * \return \c 0 on success. - * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. - */ -int mbedtls_mps_reader_reclaim(mbedtls_mps_reader *reader, - int *paused); - -/* - * Usage API (Upper layer) - */ - -/** - * \brief Request data from the reader. - * - * \param reader The reader context to use. The reader must - * be in consuming mode. - * \param desired The desired amount of data to be read, in Bytes. - * \param buffer The address to store the buffer pointer in. - * This must not be \c NULL. - * \param buflen The address to store the actual buffer - * length in, or \c NULL. - * - * \return \c 0 on success. In this case, \c *buf holds the - * address of a buffer of size \c *buflen - * (if \c buflen != \c NULL) or \c desired - * (if \c buflen == \c NULL). The user has read access - * to the buffer and guarantee of stability of the data - * until the next call to mbedtls_mps_reader_reclaim(). - * \return #MBEDTLS_ERR_MPS_READER_OUT_OF_DATA if there is not enough - * data available to serve the get request. In this case, the - * reader remains intact and in consuming mode, and the consumer - * should retry the call after a successful cycle of - * mbedtls_mps_reader_reclaim() and mbedtls_mps_reader_feed(). - * If, after such a cycle, the consumer requests a different - * amount of data, the result is implementation-defined; - * progress is guaranteed only if the same amount of data - * is requested after a mbedtls_mps_reader_reclaim() and - * mbedtls_mps_reader_feed() cycle. - * \return Another negative \c MBEDTLS_ERR_READER_XXX error - * code for different kinds of failure. - * - * \note Passing \c NULL as \p buflen is a convenient way to - * indicate that fragmentation is not tolerated. - * It's functionally equivalent to passing a valid - * address as buflen and checking \c *buflen == \c desired - * afterwards. - */ -int mbedtls_mps_reader_get(mbedtls_mps_reader *reader, - mbedtls_mps_size_t desired, - unsigned char **buffer, - mbedtls_mps_size_t *buflen); - -/** - * \brief Mark data obtained from mbedtls_mps_reader_get() as processed. - * - * This call indicates that all data received from prior calls to - * mbedtls_mps_reader_get() has been or will have been - * processed when mbedtls_mps_reader_reclaim() is called, - * and thus need not be backed up. - * - * This function has no user observable effect until - * mbedtls_mps_reader_reclaim() is called. In particular, - * buffers received from mbedtls_mps_reader_get() remain - * valid until mbedtls_mps_reader_reclaim() is called. - * - * \param reader The reader context to use. - * - * \return \c 0 on success. - * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. - * - */ -int mbedtls_mps_reader_commit(mbedtls_mps_reader *reader); - -#endif /* MBEDTLS_READER_H */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +/** + * \file mps_reader.h + * + * \brief This file defines reader objects, which together with their + * sibling writer objects form the basis for the communication + * between the various layers of the Mbed TLS messaging stack, + * as well as the communication between the messaging stack and + * the (D)TLS handshake protocol implementation. + * + * Readers provide a means of transferring incoming data from + * a 'producer' providing it in chunks of arbitrary size, to + * a 'consumer' which fetches and processes it in chunks of + * again arbitrary, and potentially different, size. + * + * Readers can thus be seen as datagram-to-stream converters, + * and they abstract away the following two tasks from the user: + * 1. The pointer arithmetic of stepping through a producer- + * provided chunk in smaller chunks. + * 2. The merging of incoming data chunks in case the + * consumer requests data in larger chunks than what the + * producer provides. + * + * The basic abstract flow of operation is the following: + * - Initially, the reader is in 'producing mode'. + * - The producer hands an incoming data buffer to the reader, + * moving it from 'producing' to 'consuming' mode. + * - The consumer subsequently fetches and processes the buffer + * content. Once that's done -- or partially done and a consumer's + * request can't be fulfilled -- the producer revokes the reader's + * access to the incoming data buffer, putting the reader back to + * producing mode. + * - The producer subsequently gathers more incoming data and hands + * it to the reader until it switches back to consuming mode + * if enough data is available for the last consumer request to + * be satisfiable. + * - Repeat the above. + * + * The abstract states of the reader from the producer's and + * consumer's perspective are as follows: + * + * - From the perspective of the consumer, the state of the + * reader consists of the following: + * - A byte stream representing (concatenation of) the data + * received through calls to mbedtls_mps_reader_get(), + * - A marker within that byte stream indicating which data + * can be considered processed, and hence need not be retained, + * when the reader is passed back to the producer via + * mbedtls_mps_reader_reclaim(). + * The marker is set via mbedtls_mps_reader_commit() + * which places it at the end of the current byte stream. + * The consumer need not be aware of the distinction between consumer + * and producer mode, because it only interfaces with the reader + * when the latter is in consuming mode. + * + * - From the perspective of the producer, the reader's state is one of: + * - Attached: The reader is in consuming mode. + * - Unset: No incoming data buffer is currently managed by the reader, + * and all previously handed incoming data buffers have been + * fully processed. More data needs to be fed into the reader + * via mbedtls_mps_reader_feed(). + * + * - Accumulating: No incoming data buffer is currently managed by the + * reader, but some data from the previous incoming data + * buffer hasn't been processed yet and is internally + * held back. + * The Attached state belongs to consuming mode, while the Unset and + * Accumulating states belong to producing mode. + * + * Transitioning from the Unset or Accumulating state to Attached is + * done via successful calls to mbedtls_mps_reader_feed(), while + * transitioning from Attached to either Unset or Accumulating (depending + * on what has been processed) is done via mbedtls_mps_reader_reclaim(). + * + * The following diagram depicts the producer-state progression: + * + * +------------------+ reclaim + * | Unset +<-------------------------------------+ get + * +--------|---------+ | +------+ + * | | | | + * | | | | + * | feed +---------+---+--+ | + * +--------------------------------------> <---+ + * | Attached | + * +--------------------------------------> <---+ + * | feed, enough data available +---------+---+--+ | + * | to serve previous consumer request | | | + * | | | | + * +--------+---------+ | +------+ + * +----> Accumulating |<-------------------------------------+ commit + * | +---+--------------+ reclaim, previous read request + * | | couldn't be fulfilled + * | | + * +--------+ + * feed, need more data to serve + * previous consumer request + * | + * | + * producing mode | consuming mode + * | + * + */ + +#ifndef MBEDTLS_READER_H +#define MBEDTLS_READER_H + +#include + +#include "mps_common.h" +#include "mps_error.h" + +struct mbedtls_mps_reader; +typedef struct mbedtls_mps_reader mbedtls_mps_reader; + +/* + * Structure definitions + */ + +struct mbedtls_mps_reader { + unsigned char *frag; /*!< The fragment of incoming data managed by + * the reader; it is provided to the reader + * through mbedtls_mps_reader_feed(). The reader + * does not own the fragment and does not + * perform any allocation operations on it, + * but does have read and write access to it. + * + * The reader is in consuming mode if + * and only if \c frag is not \c NULL. */ + mbedtls_mps_stored_size_t frag_len; + /*!< The length of the current fragment. + * Must be 0 if \c frag == \c NULL. */ + mbedtls_mps_stored_size_t commit; + /*!< The offset of the last commit, relative + * to the first byte in the fragment, if + * no accumulator is present. If an accumulator + * is present, it is viewed as a prefix to the + * current fragment, and this variable contains + * an offset from the beginning of the accumulator. + * + * This is only used when the reader is in + * consuming mode, i.e. \c frag != \c NULL; + * otherwise, its value is \c 0. */ + mbedtls_mps_stored_size_t end; + /*!< The offset of the end of the last chunk + * passed to the user through a call to + * mbedtls_mps_reader_get(), relative to the first + * byte in the fragment, if no accumulator is + * present. If an accumulator is present, it is + * viewed as a prefix to the current fragment, and + * this variable contains an offset from the + * beginning of the accumulator. + * + * This is only used when the reader is in + * consuming mode, i.e. \c frag != \c NULL; + * otherwise, its value is \c 0. */ + mbedtls_mps_stored_size_t pending; + /*!< The amount of incoming data missing on the + * last call to mbedtls_mps_reader_get(). + * In particular, it is \c 0 if the last call + * was successful. + * If a reader is reclaimed after an + * unsuccessful call to mbedtls_mps_reader_get(), + * this variable is used to have the reader + * remember how much data should be accumulated + * so that the call to mbedtls_mps_reader_get() + * succeeds next time. + * This is only used when the reader is in + * consuming mode, i.e. \c frag != \c NULL; + * otherwise, its value is \c 0. */ + + /* The accumulator is only needed if we need to be able to pause + * the reader. A few bytes could be saved by moving this to a + * separate struct and using a pointer here. */ + + unsigned char *acc; /*!< The accumulator is used to gather incoming + * data if a read-request via mbedtls_mps_reader_get() + * cannot be served from the current fragment. */ + mbedtls_mps_stored_size_t acc_len; + /*!< The total size of the accumulator. */ + mbedtls_mps_stored_size_t acc_available; + /*!< The number of bytes currently gathered in + * the accumulator. This is both used in + * producing and in consuming mode: + * While producing, it is increased until + * it reaches the value of \c acc_remaining below. + * While consuming, it is used to judge if a + * get request can be served from the + * accumulator or not. + * Must not be larger than \c acc_len. */ + union { + mbedtls_mps_stored_size_t acc_remaining; + /*!< This indicates the amount of data still + * to be gathered in the accumulator. It is + * only used in producing mode. + * Must be at most acc_len - acc_available. */ + mbedtls_mps_stored_size_t frag_offset; + /*!< If an accumulator is present and in use, this + * field indicates the offset of the current + * fragment from the beginning of the + * accumulator. If no accumulator is present + * or the accumulator is not in use, this is \c 0. + * It is only used in consuming mode. + * Must not be larger than \c acc_available. */ + } acc_share; +}; + +/* + * API organization: + * A reader object is usually prepared and maintained + * by some lower layer and passed for usage to an upper + * layer, and the API naturally splits according to which + * layer is supposed to use the respective functions. + */ + +/* + * Maintenance API (Lower layer) + */ + +/** + * \brief Initialize a reader object + * + * \param reader The reader to be initialized. + * \param acc The buffer to be used as a temporary accumulator + * in case get requests through mbedtls_mps_reader_get() + * exceed the buffer provided by mbedtls_mps_reader_feed(). + * This buffer is owned by the caller and exclusive use + * for reading and writing is given to the reader for the + * duration of the reader's lifetime. It is thus the caller's + * responsibility to maintain (and not touch) the buffer for + * the lifetime of the reader, and to properly zeroize and + * free the memory after the reader has been destroyed. + * \param acc_len The size in Bytes of \p acc. + * + * \return \c 0 on success. + * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. + */ +int mbedtls_mps_reader_init(mbedtls_mps_reader *reader, + unsigned char *acc, + mbedtls_mps_size_t acc_len); + +/** + * \brief Free a reader object + * + * \param reader The reader to be freed. + * + * \return \c 0 on success. + * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. + */ +int mbedtls_mps_reader_free(mbedtls_mps_reader *reader); + +/** + * \brief Pass chunk of data for the reader to manage. + * + * \param reader The reader context to use. The reader must be + * in producing mode. + * \param buf The buffer to be managed by the reader. + * \param buflen The size in Bytes of \p buffer. + * + * \return \c 0 on success. In this case, the reader will be + * moved to consuming mode and obtains read access + * of \p buf until mbedtls_mps_reader_reclaim() + * is called. It is the responsibility of the caller + * to ensure that the \p buf persists and is not changed + * between successful calls to mbedtls_mps_reader_feed() + * and mbedtls_mps_reader_reclaim(). + * \return \c MBEDTLS_ERR_MPS_READER_NEED_MORE if more input data is + * required to fulfill a previous request to mbedtls_mps_reader_get(). + * In this case, the reader remains in producing mode and + * takes no ownership of the provided buffer (an internal copy + * is made instead). + * \return Another negative \c MBEDTLS_ERR_READER_XXX error code on + * different kinds of failures. + */ +int mbedtls_mps_reader_feed(mbedtls_mps_reader *reader, + unsigned char *buf, + mbedtls_mps_size_t buflen); + +/** + * \brief Reclaim reader's access to the current input buffer. + * + * \param reader The reader context to use. The reader must be + * in consuming mode. + * \param paused If not \c NULL, the integer at address \p paused will be + * modified to indicate whether the reader has been paused + * (value \c 1) or not (value \c 0). Pausing happens if there + * is uncommitted data and a previous request to + * mbedtls_mps_reader_get() has exceeded the bounds of the + * input buffer. + * + * \return \c 0 on success. + * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. + */ +int mbedtls_mps_reader_reclaim(mbedtls_mps_reader *reader, + int *paused); + +/* + * Usage API (Upper layer) + */ + +/** + * \brief Request data from the reader. + * + * \param reader The reader context to use. The reader must + * be in consuming mode. + * \param desired The desired amount of data to be read, in Bytes. + * \param buffer The address to store the buffer pointer in. + * This must not be \c NULL. + * \param buflen The address to store the actual buffer + * length in, or \c NULL. + * + * \return \c 0 on success. In this case, \c *buf holds the + * address of a buffer of size \c *buflen + * (if \c buflen != \c NULL) or \c desired + * (if \c buflen == \c NULL). The user has read access + * to the buffer and guarantee of stability of the data + * until the next call to mbedtls_mps_reader_reclaim(). + * \return #MBEDTLS_ERR_MPS_READER_OUT_OF_DATA if there is not enough + * data available to serve the get request. In this case, the + * reader remains intact and in consuming mode, and the consumer + * should retry the call after a successful cycle of + * mbedtls_mps_reader_reclaim() and mbedtls_mps_reader_feed(). + * If, after such a cycle, the consumer requests a different + * amount of data, the result is implementation-defined; + * progress is guaranteed only if the same amount of data + * is requested after a mbedtls_mps_reader_reclaim() and + * mbedtls_mps_reader_feed() cycle. + * \return Another negative \c MBEDTLS_ERR_READER_XXX error + * code for different kinds of failure. + * + * \note Passing \c NULL as \p buflen is a convenient way to + * indicate that fragmentation is not tolerated. + * It's functionally equivalent to passing a valid + * address as buflen and checking \c *buflen == \c desired + * afterwards. + */ +int mbedtls_mps_reader_get(mbedtls_mps_reader *reader, + mbedtls_mps_size_t desired, + unsigned char **buffer, + mbedtls_mps_size_t *buflen); + +/** + * \brief Mark data obtained from mbedtls_mps_reader_get() as processed. + * + * This call indicates that all data received from prior calls to + * mbedtls_mps_reader_get() has been or will have been + * processed when mbedtls_mps_reader_reclaim() is called, + * and thus need not be backed up. + * + * This function has no user observable effect until + * mbedtls_mps_reader_reclaim() is called. In particular, + * buffers received from mbedtls_mps_reader_get() remain + * valid until mbedtls_mps_reader_reclaim() is called. + * + * \param reader The reader context to use. + * + * \return \c 0 on success. + * \return A negative \c MBEDTLS_ERR_READER_XXX error code on failure. + * + */ +int mbedtls_mps_reader_commit(mbedtls_mps_reader *reader); + +#endif /* MBEDTLS_READER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_trace.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_trace.h index f8e0a5d..d68b023 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_trace.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/mps_trace.h @@ -1,168 +1,168 @@ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is part of Mbed TLS (https://tls.mbed.org) - */ - -/** - * \file mps_trace.h - * - * \brief Tracing module for MPS - */ - -#ifndef MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H -#define MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H - -#include "common.h" -#include "mps_common.h" -#include "mps_trace.h" - -#include "mbedtls/platform.h" - -#if defined(MBEDTLS_MPS_ENABLE_TRACE) - -/* - * Adapt this to enable/disable tracing output - * from the various layers of the MPS. - */ - -#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_1 -#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_2 -#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_3 -#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_4 -#define MBEDTLS_MPS_TRACE_ENABLE_READER -#define MBEDTLS_MPS_TRACE_ENABLE_WRITER - -/* - * To use the existing trace module, only change - * MBEDTLS_MPS_TRACE_ENABLE_XXX above, but don't modify the - * rest of this file. - */ - -typedef enum { - MBEDTLS_MPS_TRACE_TYPE_COMMENT, - MBEDTLS_MPS_TRACE_TYPE_CALL, - MBEDTLS_MPS_TRACE_TYPE_ERROR, - MBEDTLS_MPS_TRACE_TYPE_RETURN -} mbedtls_mps_trace_type; - -#define MBEDTLS_MPS_TRACE_BIT_LAYER_1 1 -#define MBEDTLS_MPS_TRACE_BIT_LAYER_2 2 -#define MBEDTLS_MPS_TRACE_BIT_LAYER_3 3 -#define MBEDTLS_MPS_TRACE_BIT_LAYER_4 4 -#define MBEDTLS_MPS_TRACE_BIT_WRITER 5 -#define MBEDTLS_MPS_TRACE_BIT_READER 6 - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_1) -#define MBEDTLS_MPS_TRACE_MASK_LAYER_1 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_1) -#else -#define MBEDTLS_MPS_TRACE_MASK_LAYER_1 0 -#endif - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_2) -#define MBEDTLS_MPS_TRACE_MASK_LAYER_2 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_2) -#else -#define MBEDTLS_MPS_TRACE_MASK_LAYER_2 0 -#endif - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_3) -#define MBEDTLS_MPS_TRACE_MASK_LAYER_3 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_3) -#else -#define MBEDTLS_MPS_TRACE_MASK_LAYER_3 0 -#endif - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_4) -#define MBEDTLS_MPS_TRACE_MASK_LAYER_4 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_4) -#else -#define MBEDTLS_MPS_TRACE_MASK_LAYER_4 0 -#endif - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_READER) -#define MBEDTLS_MPS_TRACE_MASK_READER (1u << MBEDTLS_MPS_TRACE_BIT_READER) -#else -#define MBEDTLS_MPS_TRACE_MASK_READER 0 -#endif - -#if defined(MBEDTLS_MPS_TRACE_ENABLE_WRITER) -#define MBEDTLS_MPS_TRACE_MASK_WRITER (1u << MBEDTLS_MPS_TRACE_BIT_WRITER) -#else -#define MBEDTLS_MPS_TRACE_MASK_WRITER 0 -#endif - -#define MBEDTLS_MPS_TRACE_MASK (MBEDTLS_MPS_TRACE_MASK_LAYER_1 | \ - MBEDTLS_MPS_TRACE_MASK_LAYER_2 | \ - MBEDTLS_MPS_TRACE_MASK_LAYER_3 | \ - MBEDTLS_MPS_TRACE_MASK_LAYER_4 | \ - MBEDTLS_MPS_TRACE_MASK_READER | \ - MBEDTLS_MPS_TRACE_MASK_WRITER) - -/* We have to avoid globals because E-ACSL chokes on them... - * Wrap everything in stub functions. */ -int mbedtls_mps_trace_get_depth(void); -void mbedtls_mps_trace_inc_depth(void); -void mbedtls_mps_trace_dec_depth(void); - -void mbedtls_mps_trace_color(int id); -void mbedtls_mps_trace_indent(int level, mbedtls_mps_trace_type ty); - -void mbedtls_mps_trace_print_msg(int id, int line, const char *format, ...); - -#define MBEDTLS_MPS_TRACE(type, ...) \ - do { \ - if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ - break; \ - mbedtls_mps_trace_indent(mbedtls_mps_trace_get_depth(), type); \ - mbedtls_mps_trace_color(mbedtls_mps_trace_id); \ - mbedtls_mps_trace_print_msg(mbedtls_mps_trace_id, __LINE__, __VA_ARGS__); \ - mbedtls_mps_trace_color(0); \ - } while (0) - -#define MBEDTLS_MPS_TRACE_INIT(...) \ - do { \ - if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ - break; \ - MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_CALL, __VA_ARGS__); \ - mbedtls_mps_trace_inc_depth(); \ - } while (0) - -#define MBEDTLS_MPS_TRACE_END(val) \ - do { \ - if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ - break; \ - MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_RETURN, "%d (-%#04x)", \ - (int) (val), -((unsigned) (val))); \ - mbedtls_mps_trace_dec_depth(); \ - } while (0) - -#define MBEDTLS_MPS_TRACE_RETURN(val) \ - do { \ - /* Breaks tail recursion. */ \ - int ret__ = val; \ - MBEDTLS_MPS_TRACE_END(ret__); \ - return ret__; \ - } while (0) - -#else /* MBEDTLS_MPS_TRACE */ - -#define MBEDTLS_MPS_TRACE(type, ...) do { } while (0) -#define MBEDTLS_MPS_TRACE_INIT(...) do { } while (0) -#define MBEDTLS_MPS_TRACE_END do { } while (0) - -#define MBEDTLS_MPS_TRACE_RETURN(val) return val; - -#endif /* MBEDTLS_MPS_TRACE */ - -#endif /* MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of Mbed TLS (https://tls.mbed.org) + */ + +/** + * \file mps_trace.h + * + * \brief Tracing module for MPS + */ + +#ifndef MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H +#define MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H + +#include "common.h" +#include "mps_common.h" +#include "mps_trace.h" + +#include "mbedtls/platform.h" + +#if defined(MBEDTLS_MPS_ENABLE_TRACE) + +/* + * Adapt this to enable/disable tracing output + * from the various layers of the MPS. + */ + +#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_1 +#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_2 +#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_3 +#define MBEDTLS_MPS_TRACE_ENABLE_LAYER_4 +#define MBEDTLS_MPS_TRACE_ENABLE_READER +#define MBEDTLS_MPS_TRACE_ENABLE_WRITER + +/* + * To use the existing trace module, only change + * MBEDTLS_MPS_TRACE_ENABLE_XXX above, but don't modify the + * rest of this file. + */ + +typedef enum { + MBEDTLS_MPS_TRACE_TYPE_COMMENT, + MBEDTLS_MPS_TRACE_TYPE_CALL, + MBEDTLS_MPS_TRACE_TYPE_ERROR, + MBEDTLS_MPS_TRACE_TYPE_RETURN +} mbedtls_mps_trace_type; + +#define MBEDTLS_MPS_TRACE_BIT_LAYER_1 1 +#define MBEDTLS_MPS_TRACE_BIT_LAYER_2 2 +#define MBEDTLS_MPS_TRACE_BIT_LAYER_3 3 +#define MBEDTLS_MPS_TRACE_BIT_LAYER_4 4 +#define MBEDTLS_MPS_TRACE_BIT_WRITER 5 +#define MBEDTLS_MPS_TRACE_BIT_READER 6 + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_1) +#define MBEDTLS_MPS_TRACE_MASK_LAYER_1 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_1) +#else +#define MBEDTLS_MPS_TRACE_MASK_LAYER_1 0 +#endif + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_2) +#define MBEDTLS_MPS_TRACE_MASK_LAYER_2 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_2) +#else +#define MBEDTLS_MPS_TRACE_MASK_LAYER_2 0 +#endif + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_3) +#define MBEDTLS_MPS_TRACE_MASK_LAYER_3 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_3) +#else +#define MBEDTLS_MPS_TRACE_MASK_LAYER_3 0 +#endif + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_LAYER_4) +#define MBEDTLS_MPS_TRACE_MASK_LAYER_4 (1u << MBEDTLS_MPS_TRACE_BIT_LAYER_4) +#else +#define MBEDTLS_MPS_TRACE_MASK_LAYER_4 0 +#endif + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_READER) +#define MBEDTLS_MPS_TRACE_MASK_READER (1u << MBEDTLS_MPS_TRACE_BIT_READER) +#else +#define MBEDTLS_MPS_TRACE_MASK_READER 0 +#endif + +#if defined(MBEDTLS_MPS_TRACE_ENABLE_WRITER) +#define MBEDTLS_MPS_TRACE_MASK_WRITER (1u << MBEDTLS_MPS_TRACE_BIT_WRITER) +#else +#define MBEDTLS_MPS_TRACE_MASK_WRITER 0 +#endif + +#define MBEDTLS_MPS_TRACE_MASK (MBEDTLS_MPS_TRACE_MASK_LAYER_1 | \ + MBEDTLS_MPS_TRACE_MASK_LAYER_2 | \ + MBEDTLS_MPS_TRACE_MASK_LAYER_3 | \ + MBEDTLS_MPS_TRACE_MASK_LAYER_4 | \ + MBEDTLS_MPS_TRACE_MASK_READER | \ + MBEDTLS_MPS_TRACE_MASK_WRITER) + +/* We have to avoid globals because E-ACSL chokes on them... + * Wrap everything in stub functions. */ +int mbedtls_mps_trace_get_depth(void); +void mbedtls_mps_trace_inc_depth(void); +void mbedtls_mps_trace_dec_depth(void); + +void mbedtls_mps_trace_color(int id); +void mbedtls_mps_trace_indent(int level, mbedtls_mps_trace_type ty); + +void mbedtls_mps_trace_print_msg(int id, int line, const char *format, ...); + +#define MBEDTLS_MPS_TRACE(type, ...) \ + do { \ + if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ + break; \ + mbedtls_mps_trace_indent(mbedtls_mps_trace_get_depth(), type); \ + mbedtls_mps_trace_color(mbedtls_mps_trace_id); \ + mbedtls_mps_trace_print_msg(mbedtls_mps_trace_id, __LINE__, __VA_ARGS__); \ + mbedtls_mps_trace_color(0); \ + } while (0) + +#define MBEDTLS_MPS_TRACE_INIT(...) \ + do { \ + if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ + break; \ + MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_CALL, __VA_ARGS__); \ + mbedtls_mps_trace_inc_depth(); \ + } while (0) + +#define MBEDTLS_MPS_TRACE_END(val) \ + do { \ + if (!(MBEDTLS_MPS_TRACE_MASK & (1u << mbedtls_mps_trace_id))) \ + break; \ + MBEDTLS_MPS_TRACE(MBEDTLS_MPS_TRACE_TYPE_RETURN, "%d (-%#04x)", \ + (int) (val), -((unsigned) (val))); \ + mbedtls_mps_trace_dec_depth(); \ + } while (0) + +#define MBEDTLS_MPS_TRACE_RETURN(val) \ + do { \ + /* Breaks tail recursion. */ \ + int ret__ = val; \ + MBEDTLS_MPS_TRACE_END(ret__); \ + return ret__; \ + } while (0) + +#else /* MBEDTLS_MPS_TRACE */ + +#define MBEDTLS_MPS_TRACE(type, ...) do { } while (0) +#define MBEDTLS_MPS_TRACE_INIT(...) do { } while (0) +#define MBEDTLS_MPS_TRACE_END do { } while (0) + +#define MBEDTLS_MPS_TRACE_RETURN(val) return val; + +#endif /* MBEDTLS_MPS_TRACE */ + +#endif /* MBEDTLS_MPS_MBEDTLS_MPS_TRACE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/padlock.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/padlock.h index a00afe0..6027f1f 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/padlock.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/padlock.h @@ -1,123 +1,123 @@ -/** - * \file padlock.h - * - * \brief VIA PadLock ACE for HW encryption/decryption supported by some - * processors - * - * \warning These functions are only for internal use by other library - * functions; you must not call them directly. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PADLOCK_H -#define MBEDTLS_PADLOCK_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/aes.h" - -#define MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED -0x0030 /**< Input data should be aligned. */ - -#if defined(__has_feature) -#if __has_feature(address_sanitizer) -#define MBEDTLS_HAVE_ASAN -#endif -#endif - -/* - * - `padlock` is implements with GNUC assembly for x86 target. - * - Some versions of ASan result in errors about not enough registers. - */ -#if defined(MBEDTLS_PADLOCK_C) && \ - defined(__GNUC__) && defined(MBEDTLS_ARCH_IS_X86) && \ - defined(MBEDTLS_HAVE_ASM) && \ - !defined(MBEDTLS_HAVE_ASAN) - -#define MBEDTLS_VIA_PADLOCK_HAVE_CODE - -#include - -#define MBEDTLS_PADLOCK_RNG 0x000C -#define MBEDTLS_PADLOCK_ACE 0x00C0 -#define MBEDTLS_PADLOCK_PHE 0x0C00 -#define MBEDTLS_PADLOCK_PMM 0x3000 - -#define MBEDTLS_PADLOCK_ALIGN16(x) (uint32_t *) (16 + ((int32_t) (x) & ~15)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Internal PadLock detection routine - * - * \note This function is only for internal use by other library - * functions; you must not call it directly. - * - * \param feature The feature to detect - * - * \return non-zero if CPU has support for the feature, 0 otherwise - */ -int mbedtls_padlock_has_support(int feature); - -/** - * \brief Internal PadLock AES-ECB block en(de)cryption - * - * \note This function is only for internal use by other library - * functions; you must not call it directly. - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param input 16-byte input block - * \param output 16-byte output block - * - * \return 0 if success, 1 if operation failed - */ -int mbedtls_padlock_xcryptecb(mbedtls_aes_context *ctx, - int mode, - const unsigned char input[16], - unsigned char output[16]); - -/** - * \brief Internal PadLock AES-CBC buffer en(de)cryption - * - * \note This function is only for internal use by other library - * functions; you must not call it directly. - * - * \param ctx AES context - * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT - * \param length length of the input data - * \param iv initialization vector (updated after use) - * \param input buffer holding the input data - * \param output buffer holding the output data - * - * \return 0 if success, 1 if operation failed - */ -int mbedtls_padlock_xcryptcbc(mbedtls_aes_context *ctx, - int mode, - size_t length, - unsigned char iv[16], - const unsigned char *input, - unsigned char *output); - -#ifdef __cplusplus -} -#endif - -#endif /* HAVE_X86 */ - -#endif /* padlock.h */ +/** + * \file padlock.h + * + * \brief VIA PadLock ACE for HW encryption/decryption supported by some + * processors + * + * \warning These functions are only for internal use by other library + * functions; you must not call them directly. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PADLOCK_H +#define MBEDTLS_PADLOCK_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/aes.h" + +#define MBEDTLS_ERR_PADLOCK_DATA_MISALIGNED -0x0030 /**< Input data should be aligned. */ + +#if defined(__has_feature) +#if __has_feature(address_sanitizer) +#define MBEDTLS_HAVE_ASAN +#endif +#endif + +/* + * - `padlock` is implements with GNUC assembly for x86 target. + * - Some versions of ASan result in errors about not enough registers. + */ +#if defined(MBEDTLS_PADLOCK_C) && \ + defined(__GNUC__) && defined(MBEDTLS_ARCH_IS_X86) && \ + defined(MBEDTLS_HAVE_ASM) && \ + !defined(MBEDTLS_HAVE_ASAN) + +#define MBEDTLS_VIA_PADLOCK_HAVE_CODE + +#include + +#define MBEDTLS_PADLOCK_RNG 0x000C +#define MBEDTLS_PADLOCK_ACE 0x00C0 +#define MBEDTLS_PADLOCK_PHE 0x0C00 +#define MBEDTLS_PADLOCK_PMM 0x3000 + +#define MBEDTLS_PADLOCK_ALIGN16(x) (uint32_t *) (16 + ((int32_t) (x) & ~15)) + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Internal PadLock detection routine + * + * \note This function is only for internal use by other library + * functions; you must not call it directly. + * + * \param feature The feature to detect + * + * \return non-zero if CPU has support for the feature, 0 otherwise + */ +int mbedtls_padlock_has_support(int feature); + +/** + * \brief Internal PadLock AES-ECB block en(de)cryption + * + * \note This function is only for internal use by other library + * functions; you must not call it directly. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if success, 1 if operation failed + */ +int mbedtls_padlock_xcryptecb(mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16]); + +/** + * \brief Internal PadLock AES-CBC buffer en(de)cryption + * + * \note This function is only for internal use by other library + * functions; you must not call it directly. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if success, 1 if operation failed + */ +int mbedtls_padlock_xcryptcbc(mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output); + +#ifdef __cplusplus +} +#endif + +#endif /* HAVE_X86 */ + +#endif /* padlock.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_internal.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_internal.h index 004660e..419df98 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_internal.h @@ -1,130 +1,130 @@ -/** - * \file pk_internal.h - * - * \brief Public Key abstraction layer: internal (i.e. library only) functions - * and definitions. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_PK_INTERNAL_H -#define MBEDTLS_PK_INTERNAL_H - -#include "mbedtls/pk.h" - -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) -#include "mbedtls/ecp.h" -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#include "psa/crypto.h" -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_C) -#include "psa_util_internal.h" -#define PSA_PK_TO_MBEDTLS_ERR(status) psa_pk_status_to_mbedtls(status) -#define PSA_PK_RSA_TO_MBEDTLS_ERR(status) PSA_TO_MBEDTLS_ERR_LIST(status, \ - psa_to_pk_rsa_errors, \ - psa_pk_status_to_mbedtls) -#define PSA_PK_ECDSA_TO_MBEDTLS_ERR(status) PSA_TO_MBEDTLS_ERR_LIST(status, \ - psa_to_pk_ecdsa_errors, \ - psa_pk_status_to_mbedtls) -#endif - -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) -/** - * Public function mbedtls_pk_ec() can be used to get direct access to the - * wrapped ecp_keypair structure pointed to the pk_ctx. However this is not - * ideal because it bypasses the PK module on the control of its internal - * structure (pk_context) fields. - * For backward compatibility we keep mbedtls_pk_ec() when ECP_C is defined, but - * we provide 2 very similar functions when only ECP_LIGHT is enabled and not - * ECP_C. - * These variants embed the "ro" or "rw" keywords in their name to make the - * usage of the returned pointer explicit. Of course the returned value is - * const or non-const accordingly. - */ -static inline const mbedtls_ecp_keypair *mbedtls_pk_ec_ro(const mbedtls_pk_context pk) -{ - switch (mbedtls_pk_get_type(&pk)) { - case MBEDTLS_PK_ECKEY: - case MBEDTLS_PK_ECKEY_DH: - case MBEDTLS_PK_ECDSA: - return (const mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); - default: - return NULL; - } -} - -static inline mbedtls_ecp_keypair *mbedtls_pk_ec_rw(const mbedtls_pk_context pk) -{ - switch (mbedtls_pk_get_type(&pk)) { - case MBEDTLS_PK_ECKEY: - case MBEDTLS_PK_ECKEY_DH: - case MBEDTLS_PK_ECDSA: - return (mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); - default: - return NULL; - } -} - -static inline mbedtls_ecp_group_id mbedtls_pk_get_group_id(const mbedtls_pk_context *pk) -{ - mbedtls_ecp_group_id id; - -#if defined(MBEDTLS_USE_PSA_CRYPTO) - if (mbedtls_pk_get_type(pk) == MBEDTLS_PK_OPAQUE) { - psa_key_attributes_t opaque_attrs = PSA_KEY_ATTRIBUTES_INIT; - psa_key_type_t opaque_key_type; - psa_ecc_family_t curve; - - if (psa_get_key_attributes(pk->priv_id, &opaque_attrs) != PSA_SUCCESS) { - return MBEDTLS_ECP_DP_NONE; - } - opaque_key_type = psa_get_key_type(&opaque_attrs); - curve = PSA_KEY_TYPE_ECC_GET_FAMILY(opaque_key_type); - id = mbedtls_ecc_group_of_psa(curve, psa_get_key_bits(&opaque_attrs), 0); - psa_reset_key_attributes(&opaque_attrs); - } else -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - { -#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) - id = mbedtls_ecc_group_of_psa(pk->ec_family, pk->ec_bits, 0); -#else /* MBEDTLS_PK_USE_PSA_EC_DATA */ - id = mbedtls_pk_ec_ro(*pk)->grp.id; -#endif /* MBEDTLS_PK_USE_PSA_EC_DATA */ - } - - return id; -} - -/* Helper for Montgomery curves */ -#if defined(MBEDTLS_ECP_HAVE_CURVE25519) || defined(MBEDTLS_ECP_HAVE_CURVE448) -#define MBEDTLS_PK_HAVE_RFC8410_CURVES -#endif /* MBEDTLS_ECP_HAVE_CURVE25519 || MBEDTLS_ECP_DP_CURVE448 */ -#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ - -#if defined(MBEDTLS_TEST_HOOKS) - -MBEDTLS_STATIC_TESTABLE int mbedtls_pk_parse_key_pkcs8_encrypted_der( - mbedtls_pk_context *pk, - unsigned char *key, size_t keylen, - const unsigned char *pwd, size_t pwdlen, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); - -#endif - -#endif /* MBEDTLS_PK_INTERNAL_H */ +/** + * \file pk_internal.h + * + * \brief Public Key abstraction layer: internal (i.e. library only) functions + * and definitions. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_PK_INTERNAL_H +#define MBEDTLS_PK_INTERNAL_H + +#include "mbedtls/pk.h" + +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) +#include "mbedtls/ecp.h" +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#include "psa/crypto.h" +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_C) +#include "psa_util_internal.h" +#define PSA_PK_TO_MBEDTLS_ERR(status) psa_pk_status_to_mbedtls(status) +#define PSA_PK_RSA_TO_MBEDTLS_ERR(status) PSA_TO_MBEDTLS_ERR_LIST(status, \ + psa_to_pk_rsa_errors, \ + psa_pk_status_to_mbedtls) +#define PSA_PK_ECDSA_TO_MBEDTLS_ERR(status) PSA_TO_MBEDTLS_ERR_LIST(status, \ + psa_to_pk_ecdsa_errors, \ + psa_pk_status_to_mbedtls) +#endif + +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) +/** + * Public function mbedtls_pk_ec() can be used to get direct access to the + * wrapped ecp_keypair structure pointed to the pk_ctx. However this is not + * ideal because it bypasses the PK module on the control of its internal + * structure (pk_context) fields. + * For backward compatibility we keep mbedtls_pk_ec() when ECP_C is defined, but + * we provide 2 very similar functions when only ECP_LIGHT is enabled and not + * ECP_C. + * These variants embed the "ro" or "rw" keywords in their name to make the + * usage of the returned pointer explicit. Of course the returned value is + * const or non-const accordingly. + */ +static inline const mbedtls_ecp_keypair *mbedtls_pk_ec_ro(const mbedtls_pk_context pk) +{ + switch (mbedtls_pk_get_type(&pk)) { + case MBEDTLS_PK_ECKEY: + case MBEDTLS_PK_ECKEY_DH: + case MBEDTLS_PK_ECDSA: + return (const mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); + default: + return NULL; + } +} + +static inline mbedtls_ecp_keypair *mbedtls_pk_ec_rw(const mbedtls_pk_context pk) +{ + switch (mbedtls_pk_get_type(&pk)) { + case MBEDTLS_PK_ECKEY: + case MBEDTLS_PK_ECKEY_DH: + case MBEDTLS_PK_ECDSA: + return (mbedtls_ecp_keypair *) (pk).MBEDTLS_PRIVATE(pk_ctx); + default: + return NULL; + } +} + +static inline mbedtls_ecp_group_id mbedtls_pk_get_group_id(const mbedtls_pk_context *pk) +{ + mbedtls_ecp_group_id id; + +#if defined(MBEDTLS_USE_PSA_CRYPTO) + if (mbedtls_pk_get_type(pk) == MBEDTLS_PK_OPAQUE) { + psa_key_attributes_t opaque_attrs = PSA_KEY_ATTRIBUTES_INIT; + psa_key_type_t opaque_key_type; + psa_ecc_family_t curve; + + if (psa_get_key_attributes(pk->priv_id, &opaque_attrs) != PSA_SUCCESS) { + return MBEDTLS_ECP_DP_NONE; + } + opaque_key_type = psa_get_key_type(&opaque_attrs); + curve = PSA_KEY_TYPE_ECC_GET_FAMILY(opaque_key_type); + id = mbedtls_ecc_group_of_psa(curve, psa_get_key_bits(&opaque_attrs), 0); + psa_reset_key_attributes(&opaque_attrs); + } else +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + { +#if defined(MBEDTLS_PK_USE_PSA_EC_DATA) + id = mbedtls_ecc_group_of_psa(pk->ec_family, pk->ec_bits, 0); +#else /* MBEDTLS_PK_USE_PSA_EC_DATA */ + id = mbedtls_pk_ec_ro(*pk)->grp.id; +#endif /* MBEDTLS_PK_USE_PSA_EC_DATA */ + } + + return id; +} + +/* Helper for Montgomery curves */ +#if defined(MBEDTLS_ECP_HAVE_CURVE25519) || defined(MBEDTLS_ECP_HAVE_CURVE448) +#define MBEDTLS_PK_HAVE_RFC8410_CURVES +#endif /* MBEDTLS_ECP_HAVE_CURVE25519 || MBEDTLS_ECP_DP_CURVE448 */ +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ + +#if defined(MBEDTLS_TEST_HOOKS) + +MBEDTLS_STATIC_TESTABLE int mbedtls_pk_parse_key_pkcs8_encrypted_der( + mbedtls_pk_context *pk, + unsigned char *key, size_t keylen, + const unsigned char *pwd, size_t pwdlen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng); + +#endif + +#endif /* MBEDTLS_PK_INTERNAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_wrap.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_wrap.h index b1e0218..48f83fb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_wrap.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pk_wrap.h @@ -1,168 +1,168 @@ -/** - * \file pk_wrap.h - * - * \brief Public Key abstraction layer: wrapper functions - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PK_WRAP_H -#define MBEDTLS_PK_WRAP_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/pk.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) -#include "psa/crypto.h" -#endif /* MBEDTLS_PSA_CRYPTO_C */ - -struct mbedtls_pk_info_t { - /** Public key type */ - mbedtls_pk_type_t type; - - /** Type name */ - const char *name; - - /** Get key size in bits */ - size_t (*get_bitlen)(mbedtls_pk_context *pk); - - /** Tell if the context implements this type (e.g. ECKEY can do ECDSA) */ - int (*can_do)(mbedtls_pk_type_t type); - - /** Verify signature */ - int (*verify_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - const unsigned char *sig, size_t sig_len); - - /** Make signature */ - int (*sign_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, size_t *sig_len, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) - /** Verify signature (restartable) */ - int (*verify_rs_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - const unsigned char *sig, size_t sig_len, - void *rs_ctx); - - /** Make signature (restartable) */ - int (*sign_rs_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, size_t *sig_len, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, void *rs_ctx); -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - - /** Decrypt message */ - int (*decrypt_func)(mbedtls_pk_context *pk, const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, size_t osize, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - - /** Encrypt message */ - int (*encrypt_func)(mbedtls_pk_context *pk, const unsigned char *input, size_t ilen, - unsigned char *output, size_t *olen, size_t osize, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - - /** Check public-private key pair */ - int (*check_pair_func)(mbedtls_pk_context *pub, mbedtls_pk_context *prv, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - - /** Allocate a new context */ - void * (*ctx_alloc_func)(void); - - /** Free the given context */ - void (*ctx_free_func)(void *ctx); - -#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) - /** Allocate the restart context */ - void *(*rs_alloc_func)(void); - - /** Free the restart context */ - void (*rs_free_func)(void *rs_ctx); -#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ - - /** Interface with the debug module */ - void (*debug_func)(mbedtls_pk_context *pk, mbedtls_pk_debug_item *items); - -}; -#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) -/* Container for RSA-alt */ -typedef struct { - void *key; - mbedtls_pk_rsa_alt_decrypt_func decrypt_func; - mbedtls_pk_rsa_alt_sign_func sign_func; - mbedtls_pk_rsa_alt_key_len_func key_len_func; -} mbedtls_rsa_alt_context; -#endif - -#if defined(MBEDTLS_RSA_C) -extern const mbedtls_pk_info_t mbedtls_rsa_info; -#endif - -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) -extern const mbedtls_pk_info_t mbedtls_eckey_info; -extern const mbedtls_pk_info_t mbedtls_eckeydh_info; -#endif - -#if defined(MBEDTLS_PK_CAN_ECDSA_SOME) -extern const mbedtls_pk_info_t mbedtls_ecdsa_info; -#endif - -#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) -extern const mbedtls_pk_info_t mbedtls_rsa_alt_info; -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -extern const mbedtls_pk_info_t mbedtls_ecdsa_opaque_info; -extern const mbedtls_pk_info_t mbedtls_rsa_opaque_info; - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa_ecdsa(psa_status_t status); -#endif -#endif - -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_PSA_CRYPTO_C) -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa(psa_status_t status); - -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa_rsa(psa_status_t status); -#endif /* PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY || PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC */ -#endif /* !MBEDTLS_DEPRECATED_REMOVED */ - -#if defined(MBEDTLS_RSA_C) -int mbedtls_pk_psa_rsa_sign_ext(psa_algorithm_t psa_alg_md, - mbedtls_rsa_context *rsa_ctx, - const unsigned char *hash, size_t hash_len, - unsigned char *sig, size_t sig_size, - size_t *sig_len); -#endif /* MBEDTLS_RSA_C */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ - -#endif /* MBEDTLS_PK_WRAP_H */ +/** + * \file pk_wrap.h + * + * \brief Public Key abstraction layer: wrapper functions + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PK_WRAP_H +#define MBEDTLS_PK_WRAP_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/pk.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) +#include "psa/crypto.h" +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +struct mbedtls_pk_info_t { + /** Public key type */ + mbedtls_pk_type_t type; + + /** Type name */ + const char *name; + + /** Get key size in bits */ + size_t (*get_bitlen)(mbedtls_pk_context *pk); + + /** Tell if the context implements this type (e.g. ECKEY can do ECDSA) */ + int (*can_do)(mbedtls_pk_type_t type); + + /** Verify signature */ + int (*verify_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len); + + /** Make signature */ + int (*sign_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /** Verify signature (restartable) */ + int (*verify_rs_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + const unsigned char *sig, size_t sig_len, + void *rs_ctx); + + /** Make signature (restartable) */ + int (*sign_rs_func)(mbedtls_pk_context *pk, mbedtls_md_type_t md_alg, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, size_t *sig_len, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, void *rs_ctx); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + /** Decrypt message */ + int (*decrypt_func)(mbedtls_pk_context *pk, const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + + /** Encrypt message */ + int (*encrypt_func)(mbedtls_pk_context *pk, const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, size_t osize, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + + /** Check public-private key pair */ + int (*check_pair_func)(mbedtls_pk_context *pub, mbedtls_pk_context *prv, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + + /** Allocate a new context */ + void * (*ctx_alloc_func)(void); + + /** Free the given context */ + void (*ctx_free_func)(void *ctx); + +#if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) + /** Allocate the restart context */ + void *(*rs_alloc_func)(void); + + /** Free the restart context */ + void (*rs_free_func)(void *rs_ctx); +#endif /* MBEDTLS_ECDSA_C && MBEDTLS_ECP_RESTARTABLE */ + + /** Interface with the debug module */ + void (*debug_func)(mbedtls_pk_context *pk, mbedtls_pk_debug_item *items); + +}; +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +/* Container for RSA-alt */ +typedef struct { + void *key; + mbedtls_pk_rsa_alt_decrypt_func decrypt_func; + mbedtls_pk_rsa_alt_sign_func sign_func; + mbedtls_pk_rsa_alt_key_len_func key_len_func; +} mbedtls_rsa_alt_context; +#endif + +#if defined(MBEDTLS_RSA_C) +extern const mbedtls_pk_info_t mbedtls_rsa_info; +#endif + +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) +extern const mbedtls_pk_info_t mbedtls_eckey_info; +extern const mbedtls_pk_info_t mbedtls_eckeydh_info; +#endif + +#if defined(MBEDTLS_PK_CAN_ECDSA_SOME) +extern const mbedtls_pk_info_t mbedtls_ecdsa_info; +#endif + +#if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) +extern const mbedtls_pk_info_t mbedtls_rsa_alt_info; +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +extern const mbedtls_pk_info_t mbedtls_ecdsa_opaque_info; +extern const mbedtls_pk_info_t mbedtls_rsa_opaque_info; + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa_ecdsa(psa_status_t status); +#endif +#endif + +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_PSA_CRYPTO_C) +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa(psa_status_t status); + +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +int MBEDTLS_DEPRECATED mbedtls_pk_error_from_psa_rsa(psa_status_t status); +#endif /* PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY || PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC */ +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#if defined(MBEDTLS_RSA_C) +int mbedtls_pk_psa_rsa_sign_ext(psa_algorithm_t psa_alg_md, + mbedtls_rsa_context *rsa_ctx, + const unsigned char *hash, size_t hash_len, + unsigned char *sig, size_t sig_size, + size_t *sig_len); +#endif /* MBEDTLS_RSA_C */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ + +#endif /* MBEDTLS_PK_WRAP_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pkwrite.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pkwrite.h index 8cfa64b..92c0021 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pkwrite.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/pkwrite.h @@ -1,124 +1,124 @@ -/** - * \file pkwrite.h - * - * \brief Internal defines shared by the PK write module - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PK_WRITE_H -#define MBEDTLS_PK_WRITE_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/pk.h" - -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#include "psa/crypto.h" -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/* - * Max sizes of key per types. Shown as tag + len (+ content). - */ - -#if defined(MBEDTLS_RSA_C) -/* - * RSA public keys: - * SubjectPublicKeyInfo ::= SEQUENCE { 1 + 3 - * algorithm AlgorithmIdentifier, 1 + 1 (sequence) - * + 1 + 1 + 9 (rsa oid) - * + 1 + 1 (params null) - * subjectPublicKey BIT STRING } 1 + 3 + (1 + below) - * RSAPublicKey ::= SEQUENCE { 1 + 3 - * modulus INTEGER, -- n 1 + 3 + MPI_MAX + 1 - * publicExponent INTEGER -- e 1 + 3 + MPI_MAX + 1 - * } - */ -#define MBEDTLS_PK_RSA_PUB_DER_MAX_BYTES (38 + 2 * MBEDTLS_MPI_MAX_SIZE) - -/* - * RSA private keys: - * RSAPrivateKey ::= SEQUENCE { 1 + 3 - * version Version, 1 + 1 + 1 - * modulus INTEGER, 1 + 3 + MPI_MAX + 1 - * publicExponent INTEGER, 1 + 3 + MPI_MAX + 1 - * privateExponent INTEGER, 1 + 3 + MPI_MAX + 1 - * prime1 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 - * prime2 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 - * exponent1 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 - * exponent2 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 - * coefficient INTEGER, 1 + 3 + MPI_MAX / 2 + 1 - * otherPrimeInfos OtherPrimeInfos OPTIONAL 0 (not supported) - * } - */ -#define MBEDTLS_MPI_MAX_SIZE_2 (MBEDTLS_MPI_MAX_SIZE / 2 + \ - MBEDTLS_MPI_MAX_SIZE % 2) -#define MBEDTLS_PK_RSA_PRV_DER_MAX_BYTES (47 + 3 * MBEDTLS_MPI_MAX_SIZE \ - + 5 * MBEDTLS_MPI_MAX_SIZE_2) - -#else /* MBEDTLS_RSA_C */ - -#define MBEDTLS_PK_RSA_PUB_DER_MAX_BYTES 0 -#define MBEDTLS_PK_RSA_PRV_DER_MAX_BYTES 0 - -#endif /* MBEDTLS_RSA_C */ - -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) - -/* Find the maximum number of bytes necessary to store an EC point. When USE_PSA - * is defined this means looking for the maximum between PSA and built-in - * supported curves. */ -#if defined(MBEDTLS_USE_PSA_CRYPTO) -#define MBEDTLS_PK_MAX_ECC_BYTES (PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ - MBEDTLS_ECP_MAX_BYTES ? \ - PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) : \ - MBEDTLS_ECP_MAX_BYTES) -#else /* MBEDTLS_USE_PSA_CRYPTO */ -#define MBEDTLS_PK_MAX_ECC_BYTES MBEDTLS_ECP_MAX_BYTES -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -/* - * EC public keys: - * SubjectPublicKeyInfo ::= SEQUENCE { 1 + 2 - * algorithm AlgorithmIdentifier, 1 + 1 (sequence) - * + 1 + 1 + 7 (ec oid) - * + 1 + 1 + 9 (namedCurve oid) - * subjectPublicKey BIT STRING 1 + 2 + 1 [1] - * + 1 (point format) [1] - * + 2 * ECP_MAX (coords) [1] - * } - */ -#define MBEDTLS_PK_ECP_PUB_DER_MAX_BYTES (30 + 2 * MBEDTLS_PK_MAX_ECC_BYTES) - -/* - * EC private keys: - * ECPrivateKey ::= SEQUENCE { 1 + 2 - * version INTEGER , 1 + 1 + 1 - * privateKey OCTET STRING, 1 + 1 + ECP_MAX - * parameters [0] ECParameters OPTIONAL, 1 + 1 + (1 + 1 + 9) - * publicKey [1] BIT STRING OPTIONAL 1 + 2 + [1] above - * } - */ -#define MBEDTLS_PK_ECP_PRV_DER_MAX_BYTES (29 + 3 * MBEDTLS_PK_MAX_ECC_BYTES) - -#else /* MBEDTLS_PK_HAVE_ECC_KEYS */ - -#define MBEDTLS_PK_ECP_PUB_DER_MAX_BYTES 0 -#define MBEDTLS_PK_ECP_PRV_DER_MAX_BYTES 0 - -#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ -#endif /* MBEDTLS_PK_WRITE_H */ +/** + * \file pkwrite.h + * + * \brief Internal defines shared by the PK write module + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PK_WRITE_H +#define MBEDTLS_PK_WRITE_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/pk.h" + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#include "psa/crypto.h" +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/* + * Max sizes of key per types. Shown as tag + len (+ content). + */ + +#if defined(MBEDTLS_RSA_C) +/* + * RSA public keys: + * SubjectPublicKeyInfo ::= SEQUENCE { 1 + 3 + * algorithm AlgorithmIdentifier, 1 + 1 (sequence) + * + 1 + 1 + 9 (rsa oid) + * + 1 + 1 (params null) + * subjectPublicKey BIT STRING } 1 + 3 + (1 + below) + * RSAPublicKey ::= SEQUENCE { 1 + 3 + * modulus INTEGER, -- n 1 + 3 + MPI_MAX + 1 + * publicExponent INTEGER -- e 1 + 3 + MPI_MAX + 1 + * } + */ +#define MBEDTLS_PK_RSA_PUB_DER_MAX_BYTES (38 + 2 * MBEDTLS_MPI_MAX_SIZE) + +/* + * RSA private keys: + * RSAPrivateKey ::= SEQUENCE { 1 + 3 + * version Version, 1 + 1 + 1 + * modulus INTEGER, 1 + 3 + MPI_MAX + 1 + * publicExponent INTEGER, 1 + 3 + MPI_MAX + 1 + * privateExponent INTEGER, 1 + 3 + MPI_MAX + 1 + * prime1 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 + * prime2 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 + * exponent1 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 + * exponent2 INTEGER, 1 + 3 + MPI_MAX / 2 + 1 + * coefficient INTEGER, 1 + 3 + MPI_MAX / 2 + 1 + * otherPrimeInfos OtherPrimeInfos OPTIONAL 0 (not supported) + * } + */ +#define MBEDTLS_MPI_MAX_SIZE_2 (MBEDTLS_MPI_MAX_SIZE / 2 + \ + MBEDTLS_MPI_MAX_SIZE % 2) +#define MBEDTLS_PK_RSA_PRV_DER_MAX_BYTES (47 + 3 * MBEDTLS_MPI_MAX_SIZE \ + + 5 * MBEDTLS_MPI_MAX_SIZE_2) + +#else /* MBEDTLS_RSA_C */ + +#define MBEDTLS_PK_RSA_PUB_DER_MAX_BYTES 0 +#define MBEDTLS_PK_RSA_PRV_DER_MAX_BYTES 0 + +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) + +/* Find the maximum number of bytes necessary to store an EC point. When USE_PSA + * is defined this means looking for the maximum between PSA and built-in + * supported curves. */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#define MBEDTLS_PK_MAX_ECC_BYTES (PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) > \ + MBEDTLS_ECP_MAX_BYTES ? \ + PSA_BITS_TO_BYTES(PSA_VENDOR_ECC_MAX_CURVE_BITS) : \ + MBEDTLS_ECP_MAX_BYTES) +#else /* MBEDTLS_USE_PSA_CRYPTO */ +#define MBEDTLS_PK_MAX_ECC_BYTES MBEDTLS_ECP_MAX_BYTES +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +/* + * EC public keys: + * SubjectPublicKeyInfo ::= SEQUENCE { 1 + 2 + * algorithm AlgorithmIdentifier, 1 + 1 (sequence) + * + 1 + 1 + 7 (ec oid) + * + 1 + 1 + 9 (namedCurve oid) + * subjectPublicKey BIT STRING 1 + 2 + 1 [1] + * + 1 (point format) [1] + * + 2 * ECP_MAX (coords) [1] + * } + */ +#define MBEDTLS_PK_ECP_PUB_DER_MAX_BYTES (30 + 2 * MBEDTLS_PK_MAX_ECC_BYTES) + +/* + * EC private keys: + * ECPrivateKey ::= SEQUENCE { 1 + 2 + * version INTEGER , 1 + 1 + 1 + * privateKey OCTET STRING, 1 + 1 + ECP_MAX + * parameters [0] ECParameters OPTIONAL, 1 + 1 + (1 + 1 + 9) + * publicKey [1] BIT STRING OPTIONAL 1 + 2 + [1] above + * } + */ +#define MBEDTLS_PK_ECP_PRV_DER_MAX_BYTES (29 + 3 * MBEDTLS_PK_MAX_ECC_BYTES) + +#else /* MBEDTLS_PK_HAVE_ECC_KEYS */ + +#define MBEDTLS_PK_ECP_PUB_DER_MAX_BYTES 0 +#define MBEDTLS_PK_ECP_PRV_DER_MAX_BYTES 0 + +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ +#endif /* MBEDTLS_PK_WRITE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform.c index b15b7b2..64d6162 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform.c @@ -1,414 +1,414 @@ -/* - * Platform abstraction layer - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PLATFORM_C) - -#include "mbedtls/platform.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/error.h" - -/* The compile time configuration of memory allocation via the macros - * MBEDTLS_PLATFORM_{FREE/CALLOC}_MACRO takes precedence over the runtime - * configuration via mbedtls_platform_set_calloc_free(). So, omit everything - * related to the latter if MBEDTLS_PLATFORM_{FREE/CALLOC}_MACRO are defined. */ -#if defined(MBEDTLS_PLATFORM_MEMORY) && \ - !(defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && \ - defined(MBEDTLS_PLATFORM_FREE_MACRO)) - -#if !defined(MBEDTLS_PLATFORM_STD_CALLOC) -static void *platform_calloc_uninit(size_t n, size_t size) -{ - ((void) n); - ((void) size); - return NULL; -} - -#define MBEDTLS_PLATFORM_STD_CALLOC platform_calloc_uninit -#endif /* !MBEDTLS_PLATFORM_STD_CALLOC */ - -#if !defined(MBEDTLS_PLATFORM_STD_FREE) -static void platform_free_uninit(void *ptr) -{ - ((void) ptr); -} - -#define MBEDTLS_PLATFORM_STD_FREE platform_free_uninit -#endif /* !MBEDTLS_PLATFORM_STD_FREE */ - -static void * (*mbedtls_calloc_func)(size_t, size_t) = MBEDTLS_PLATFORM_STD_CALLOC; -static void (*mbedtls_free_func)(void *) = MBEDTLS_PLATFORM_STD_FREE; - -void *mbedtls_calloc(size_t nmemb, size_t size) -{ - return (*mbedtls_calloc_func)(nmemb, size); -} - -void mbedtls_free(void *ptr) -{ - (*mbedtls_free_func)(ptr); -} - -int mbedtls_platform_set_calloc_free(void *(*calloc_func)(size_t, size_t), - void (*free_func)(void *)) -{ - mbedtls_calloc_func = calloc_func; - mbedtls_free_func = free_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_MEMORY && - !( defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && - defined(MBEDTLS_PLATFORM_FREE_MACRO) ) */ - -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) -#include -int mbedtls_platform_win32_snprintf(char *s, size_t n, const char *fmt, ...) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - va_list argp; - - va_start(argp, fmt); - ret = mbedtls_vsnprintf(s, n, fmt, argp); - va_end(argp); - - return ret; -} -#endif - -#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_snprintf_uninit(char *s, size_t n, - const char *format, ...) -{ - ((void) s); - ((void) n); - ((void) format); - return 0; -} - -#define MBEDTLS_PLATFORM_STD_SNPRINTF platform_snprintf_uninit -#endif /* !MBEDTLS_PLATFORM_STD_SNPRINTF */ - -int (*mbedtls_snprintf)(char *s, size_t n, - const char *format, - ...) = MBEDTLS_PLATFORM_STD_SNPRINTF; - -int mbedtls_platform_set_snprintf(int (*snprintf_func)(char *s, size_t n, - const char *format, - ...)) -{ - mbedtls_snprintf = snprintf_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ - -#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) -#include -int mbedtls_platform_win32_vsnprintf(char *s, size_t n, const char *fmt, va_list arg) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - /* Avoid calling the invalid parameter handler by checking ourselves */ - if (s == NULL || n == 0 || fmt == NULL) { - return -1; - } - -#if defined(_TRUNCATE) - ret = vsnprintf_s(s, n, _TRUNCATE, fmt, arg); -#else - ret = vsnprintf(s, n, fmt, arg); - if (ret < 0 || (size_t) ret == n) { - s[n-1] = '\0'; - ret = -1; - } -#endif - - return ret; -} -#endif - -#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_vsnprintf_uninit(char *s, size_t n, - const char *format, va_list arg) -{ - ((void) s); - ((void) n); - ((void) format); - ((void) arg); - return -1; -} - -#define MBEDTLS_PLATFORM_STD_VSNPRINTF platform_vsnprintf_uninit -#endif /* !MBEDTLS_PLATFORM_STD_VSNPRINTF */ - -int (*mbedtls_vsnprintf)(char *s, size_t n, - const char *format, - va_list arg) = MBEDTLS_PLATFORM_STD_VSNPRINTF; - -int mbedtls_platform_set_vsnprintf(int (*vsnprintf_func)(char *s, size_t n, - const char *format, - va_list arg)) -{ - mbedtls_vsnprintf = vsnprintf_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ - -#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_PRINTF) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_printf_uninit(const char *format, ...) -{ - ((void) format); - return 0; -} - -#define MBEDTLS_PLATFORM_STD_PRINTF platform_printf_uninit -#endif /* !MBEDTLS_PLATFORM_STD_PRINTF */ - -int (*mbedtls_printf)(const char *, ...) = MBEDTLS_PLATFORM_STD_PRINTF; - -int mbedtls_platform_set_printf(int (*printf_func)(const char *, ...)) -{ - mbedtls_printf = printf_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ - -#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_fprintf_uninit(FILE *stream, const char *format, ...) -{ - ((void) stream); - ((void) format); - return 0; -} - -#define MBEDTLS_PLATFORM_STD_FPRINTF platform_fprintf_uninit -#endif /* !MBEDTLS_PLATFORM_STD_FPRINTF */ - -int (*mbedtls_fprintf)(FILE *, const char *, ...) = - MBEDTLS_PLATFORM_STD_FPRINTF; - -int mbedtls_platform_set_fprintf(int (*fprintf_func)(FILE *, const char *, ...)) -{ - mbedtls_fprintf = fprintf_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ - -#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_SETBUF) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static void platform_setbuf_uninit(FILE *stream, char *buf) -{ - ((void) stream); - ((void) buf); -} - -#define MBEDTLS_PLATFORM_STD_SETBUF platform_setbuf_uninit -#endif /* !MBEDTLS_PLATFORM_STD_SETBUF */ -void (*mbedtls_setbuf)(FILE *stream, char *buf) = MBEDTLS_PLATFORM_STD_SETBUF; - -int mbedtls_platform_set_setbuf(void (*setbuf_func)(FILE *stream, char *buf)) -{ - mbedtls_setbuf = setbuf_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_SETBUF_ALT */ - -#if defined(MBEDTLS_PLATFORM_EXIT_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_EXIT) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static void platform_exit_uninit(int status) -{ - ((void) status); -} - -#define MBEDTLS_PLATFORM_STD_EXIT platform_exit_uninit -#endif /* !MBEDTLS_PLATFORM_STD_EXIT */ - -void (*mbedtls_exit)(int status) = MBEDTLS_PLATFORM_STD_EXIT; - -int mbedtls_platform_set_exit(void (*exit_func)(int status)) -{ - mbedtls_exit = exit_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ - -#if defined(MBEDTLS_HAVE_TIME) - -#if defined(MBEDTLS_PLATFORM_TIME_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_TIME) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static mbedtls_time_t platform_time_uninit(mbedtls_time_t *timer) -{ - ((void) timer); - return 0; -} - -#define MBEDTLS_PLATFORM_STD_TIME platform_time_uninit -#endif /* !MBEDTLS_PLATFORM_STD_TIME */ - -mbedtls_time_t (*mbedtls_time)(mbedtls_time_t *timer) = MBEDTLS_PLATFORM_STD_TIME; - -int mbedtls_platform_set_time(mbedtls_time_t (*time_func)(mbedtls_time_t *timer)) -{ - mbedtls_time = time_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_TIME_ALT */ - -#endif /* MBEDTLS_HAVE_TIME */ - -#if defined(MBEDTLS_ENTROPY_NV_SEED) -#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO) -/* Default implementations for the platform independent seed functions use - * standard libc file functions to read from and write to a pre-defined filename - */ -int mbedtls_platform_std_nv_seed_read(unsigned char *buf, size_t buf_len) -{ - FILE *file; - size_t n; - - if ((file = fopen(MBEDTLS_PLATFORM_STD_NV_SEED_FILE, "rb")) == NULL) { - return -1; - } - - /* Ensure no stdio buffering of secrets, as such buffers cannot be wiped. */ - mbedtls_setbuf(file, NULL); - - if ((n = fread(buf, 1, buf_len, file)) != buf_len) { - fclose(file); - mbedtls_platform_zeroize(buf, buf_len); - return -1; - } - - fclose(file); - return (int) n; -} - -int mbedtls_platform_std_nv_seed_write(unsigned char *buf, size_t buf_len) -{ - FILE *file; - size_t n; - - if ((file = fopen(MBEDTLS_PLATFORM_STD_NV_SEED_FILE, "w")) == NULL) { - return -1; - } - - /* Ensure no stdio buffering of secrets, as such buffers cannot be wiped. */ - mbedtls_setbuf(file, NULL); - - if ((n = fwrite(buf, 1, buf_len, file)) != buf_len) { - fclose(file); - return -1; - } - - fclose(file); - return (int) n; -} -#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ - -#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) -#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_nv_seed_read_uninit(unsigned char *buf, size_t buf_len) -{ - ((void) buf); - ((void) buf_len); - return -1; -} - -#define MBEDTLS_PLATFORM_STD_NV_SEED_READ platform_nv_seed_read_uninit -#endif /* !MBEDTLS_PLATFORM_STD_NV_SEED_READ */ - -#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) -/* - * Make dummy function to prevent NULL pointer dereferences - */ -static int platform_nv_seed_write_uninit(unsigned char *buf, size_t buf_len) -{ - ((void) buf); - ((void) buf_len); - return -1; -} - -#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE platform_nv_seed_write_uninit -#endif /* !MBEDTLS_PLATFORM_STD_NV_SEED_WRITE */ - -int (*mbedtls_nv_seed_read)(unsigned char *buf, size_t buf_len) = - MBEDTLS_PLATFORM_STD_NV_SEED_READ; -int (*mbedtls_nv_seed_write)(unsigned char *buf, size_t buf_len) = - MBEDTLS_PLATFORM_STD_NV_SEED_WRITE; - -int mbedtls_platform_set_nv_seed( - int (*nv_seed_read_func)(unsigned char *buf, size_t buf_len), - int (*nv_seed_write_func)(unsigned char *buf, size_t buf_len)) -{ - mbedtls_nv_seed_read = nv_seed_read_func; - mbedtls_nv_seed_write = nv_seed_write_func; - return 0; -} -#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ -#endif /* MBEDTLS_ENTROPY_NV_SEED */ - -#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) -/* - * Placeholder platform setup that does nothing by default - */ -int mbedtls_platform_setup(mbedtls_platform_context *ctx) -{ - (void) ctx; - - return 0; -} - -/* - * Placeholder platform teardown that does nothing by default - */ -void mbedtls_platform_teardown(mbedtls_platform_context *ctx) -{ - (void) ctx; -} -#endif /* MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ - -#endif /* MBEDTLS_PLATFORM_C */ +/* + * Platform abstraction layer + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PLATFORM_C) + +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/error.h" + +/* The compile time configuration of memory allocation via the macros + * MBEDTLS_PLATFORM_{FREE/CALLOC}_MACRO takes precedence over the runtime + * configuration via mbedtls_platform_set_calloc_free(). So, omit everything + * related to the latter if MBEDTLS_PLATFORM_{FREE/CALLOC}_MACRO are defined. */ +#if defined(MBEDTLS_PLATFORM_MEMORY) && \ + !(defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && \ + defined(MBEDTLS_PLATFORM_FREE_MACRO)) + +#if !defined(MBEDTLS_PLATFORM_STD_CALLOC) +static void *platform_calloc_uninit(size_t n, size_t size) +{ + ((void) n); + ((void) size); + return NULL; +} + +#define MBEDTLS_PLATFORM_STD_CALLOC platform_calloc_uninit +#endif /* !MBEDTLS_PLATFORM_STD_CALLOC */ + +#if !defined(MBEDTLS_PLATFORM_STD_FREE) +static void platform_free_uninit(void *ptr) +{ + ((void) ptr); +} + +#define MBEDTLS_PLATFORM_STD_FREE platform_free_uninit +#endif /* !MBEDTLS_PLATFORM_STD_FREE */ + +static void * (*mbedtls_calloc_func)(size_t, size_t) = MBEDTLS_PLATFORM_STD_CALLOC; +static void (*mbedtls_free_func)(void *) = MBEDTLS_PLATFORM_STD_FREE; + +void *mbedtls_calloc(size_t nmemb, size_t size) +{ + return (*mbedtls_calloc_func)(nmemb, size); +} + +void mbedtls_free(void *ptr) +{ + (*mbedtls_free_func)(ptr); +} + +int mbedtls_platform_set_calloc_free(void *(*calloc_func)(size_t, size_t), + void (*free_func)(void *)) +{ + mbedtls_calloc_func = calloc_func; + mbedtls_free_func = free_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_MEMORY && + !( defined(MBEDTLS_PLATFORM_CALLOC_MACRO) && + defined(MBEDTLS_PLATFORM_FREE_MACRO) ) */ + +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_SNPRINTF) +#include +int mbedtls_platform_win32_snprintf(char *s, size_t n, const char *fmt, ...) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + va_list argp; + + va_start(argp, fmt); + ret = mbedtls_vsnprintf(s, n, fmt, argp); + va_end(argp); + + return ret; +} +#endif + +#if defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_SNPRINTF) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_snprintf_uninit(char *s, size_t n, + const char *format, ...) +{ + ((void) s); + ((void) n); + ((void) format); + return 0; +} + +#define MBEDTLS_PLATFORM_STD_SNPRINTF platform_snprintf_uninit +#endif /* !MBEDTLS_PLATFORM_STD_SNPRINTF */ + +int (*mbedtls_snprintf)(char *s, size_t n, + const char *format, + ...) = MBEDTLS_PLATFORM_STD_SNPRINTF; + +int mbedtls_platform_set_snprintf(int (*snprintf_func)(char *s, size_t n, + const char *format, + ...)) +{ + mbedtls_snprintf = snprintf_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_SNPRINTF_ALT */ + +#if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) +#include +int mbedtls_platform_win32_vsnprintf(char *s, size_t n, const char *fmt, va_list arg) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* Avoid calling the invalid parameter handler by checking ourselves */ + if (s == NULL || n == 0 || fmt == NULL) { + return -1; + } + +#if defined(_TRUNCATE) + ret = vsnprintf_s(s, n, _TRUNCATE, fmt, arg); +#else + ret = vsnprintf(s, n, fmt, arg); + if (ret < 0 || (size_t) ret == n) { + s[n-1] = '\0'; + ret = -1; + } +#endif + + return ret; +} +#endif + +#if defined(MBEDTLS_PLATFORM_VSNPRINTF_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_VSNPRINTF) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_vsnprintf_uninit(char *s, size_t n, + const char *format, va_list arg) +{ + ((void) s); + ((void) n); + ((void) format); + ((void) arg); + return -1; +} + +#define MBEDTLS_PLATFORM_STD_VSNPRINTF platform_vsnprintf_uninit +#endif /* !MBEDTLS_PLATFORM_STD_VSNPRINTF */ + +int (*mbedtls_vsnprintf)(char *s, size_t n, + const char *format, + va_list arg) = MBEDTLS_PLATFORM_STD_VSNPRINTF; + +int mbedtls_platform_set_vsnprintf(int (*vsnprintf_func)(char *s, size_t n, + const char *format, + va_list arg)) +{ + mbedtls_vsnprintf = vsnprintf_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_VSNPRINTF_ALT */ + +#if defined(MBEDTLS_PLATFORM_PRINTF_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_PRINTF) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_printf_uninit(const char *format, ...) +{ + ((void) format); + return 0; +} + +#define MBEDTLS_PLATFORM_STD_PRINTF platform_printf_uninit +#endif /* !MBEDTLS_PLATFORM_STD_PRINTF */ + +int (*mbedtls_printf)(const char *, ...) = MBEDTLS_PLATFORM_STD_PRINTF; + +int mbedtls_platform_set_printf(int (*printf_func)(const char *, ...)) +{ + mbedtls_printf = printf_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_PRINTF_ALT */ + +#if defined(MBEDTLS_PLATFORM_FPRINTF_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_FPRINTF) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_fprintf_uninit(FILE *stream, const char *format, ...) +{ + ((void) stream); + ((void) format); + return 0; +} + +#define MBEDTLS_PLATFORM_STD_FPRINTF platform_fprintf_uninit +#endif /* !MBEDTLS_PLATFORM_STD_FPRINTF */ + +int (*mbedtls_fprintf)(FILE *, const char *, ...) = + MBEDTLS_PLATFORM_STD_FPRINTF; + +int mbedtls_platform_set_fprintf(int (*fprintf_func)(FILE *, const char *, ...)) +{ + mbedtls_fprintf = fprintf_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_FPRINTF_ALT */ + +#if defined(MBEDTLS_PLATFORM_SETBUF_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_SETBUF) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static void platform_setbuf_uninit(FILE *stream, char *buf) +{ + ((void) stream); + ((void) buf); +} + +#define MBEDTLS_PLATFORM_STD_SETBUF platform_setbuf_uninit +#endif /* !MBEDTLS_PLATFORM_STD_SETBUF */ +void (*mbedtls_setbuf)(FILE *stream, char *buf) = MBEDTLS_PLATFORM_STD_SETBUF; + +int mbedtls_platform_set_setbuf(void (*setbuf_func)(FILE *stream, char *buf)) +{ + mbedtls_setbuf = setbuf_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_SETBUF_ALT */ + +#if defined(MBEDTLS_PLATFORM_EXIT_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_EXIT) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static void platform_exit_uninit(int status) +{ + ((void) status); +} + +#define MBEDTLS_PLATFORM_STD_EXIT platform_exit_uninit +#endif /* !MBEDTLS_PLATFORM_STD_EXIT */ + +void (*mbedtls_exit)(int status) = MBEDTLS_PLATFORM_STD_EXIT; + +int mbedtls_platform_set_exit(void (*exit_func)(int status)) +{ + mbedtls_exit = exit_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_EXIT_ALT */ + +#if defined(MBEDTLS_HAVE_TIME) + +#if defined(MBEDTLS_PLATFORM_TIME_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_TIME) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static mbedtls_time_t platform_time_uninit(mbedtls_time_t *timer) +{ + ((void) timer); + return 0; +} + +#define MBEDTLS_PLATFORM_STD_TIME platform_time_uninit +#endif /* !MBEDTLS_PLATFORM_STD_TIME */ + +mbedtls_time_t (*mbedtls_time)(mbedtls_time_t *timer) = MBEDTLS_PLATFORM_STD_TIME; + +int mbedtls_platform_set_time(mbedtls_time_t (*time_func)(mbedtls_time_t *timer)) +{ + mbedtls_time = time_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_TIME_ALT */ + +#endif /* MBEDTLS_HAVE_TIME */ + +#if defined(MBEDTLS_ENTROPY_NV_SEED) +#if !defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) && defined(MBEDTLS_FS_IO) +/* Default implementations for the platform independent seed functions use + * standard libc file functions to read from and write to a pre-defined filename + */ +int mbedtls_platform_std_nv_seed_read(unsigned char *buf, size_t buf_len) +{ + FILE *file; + size_t n; + + if ((file = fopen(MBEDTLS_PLATFORM_STD_NV_SEED_FILE, "rb")) == NULL) { + return -1; + } + + /* Ensure no stdio buffering of secrets, as such buffers cannot be wiped. */ + mbedtls_setbuf(file, NULL); + + if ((n = fread(buf, 1, buf_len, file)) != buf_len) { + fclose(file); + mbedtls_platform_zeroize(buf, buf_len); + return -1; + } + + fclose(file); + return (int) n; +} + +int mbedtls_platform_std_nv_seed_write(unsigned char *buf, size_t buf_len) +{ + FILE *file; + size_t n; + + if ((file = fopen(MBEDTLS_PLATFORM_STD_NV_SEED_FILE, "w")) == NULL) { + return -1; + } + + /* Ensure no stdio buffering of secrets, as such buffers cannot be wiped. */ + mbedtls_setbuf(file, NULL); + + if ((n = fwrite(buf, 1, buf_len, file)) != buf_len) { + fclose(file); + return -1; + } + + fclose(file); + return (int) n; +} +#endif /* MBEDTLS_PLATFORM_NO_STD_FUNCTIONS */ + +#if defined(MBEDTLS_PLATFORM_NV_SEED_ALT) +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_READ) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_nv_seed_read_uninit(unsigned char *buf, size_t buf_len) +{ + ((void) buf); + ((void) buf_len); + return -1; +} + +#define MBEDTLS_PLATFORM_STD_NV_SEED_READ platform_nv_seed_read_uninit +#endif /* !MBEDTLS_PLATFORM_STD_NV_SEED_READ */ + +#if !defined(MBEDTLS_PLATFORM_STD_NV_SEED_WRITE) +/* + * Make dummy function to prevent NULL pointer dereferences + */ +static int platform_nv_seed_write_uninit(unsigned char *buf, size_t buf_len) +{ + ((void) buf); + ((void) buf_len); + return -1; +} + +#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE platform_nv_seed_write_uninit +#endif /* !MBEDTLS_PLATFORM_STD_NV_SEED_WRITE */ + +int (*mbedtls_nv_seed_read)(unsigned char *buf, size_t buf_len) = + MBEDTLS_PLATFORM_STD_NV_SEED_READ; +int (*mbedtls_nv_seed_write)(unsigned char *buf, size_t buf_len) = + MBEDTLS_PLATFORM_STD_NV_SEED_WRITE; + +int mbedtls_platform_set_nv_seed( + int (*nv_seed_read_func)(unsigned char *buf, size_t buf_len), + int (*nv_seed_write_func)(unsigned char *buf, size_t buf_len)) +{ + mbedtls_nv_seed_read = nv_seed_read_func; + mbedtls_nv_seed_write = nv_seed_write_func; + return 0; +} +#endif /* MBEDTLS_PLATFORM_NV_SEED_ALT */ +#endif /* MBEDTLS_ENTROPY_NV_SEED */ + +#if !defined(MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT) +/* + * Placeholder platform setup that does nothing by default + */ +int mbedtls_platform_setup(mbedtls_platform_context *ctx) +{ + (void) ctx; + + return 0; +} + +/* + * Placeholder platform teardown that does nothing by default + */ +void mbedtls_platform_teardown(mbedtls_platform_context *ctx) +{ + (void) ctx; +} +#endif /* MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT */ + +#endif /* MBEDTLS_PLATFORM_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform_util.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform_util.c index 09216ed..1f2b191 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform_util.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/platform_util.c @@ -1,297 +1,297 @@ -/* - * Common and shared functions used by multiple modules in the Mbed TLS - * library. - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Ensure gmtime_r is available even with -std=c99; must be defined before - * mbedtls_config.h, which pulls in glibc's features.h. Harmless on other platforms - * except OpenBSD, where it stops us accessing explicit_bzero. - */ -#if !defined(_POSIX_C_SOURCE) && !defined(__OpenBSD__) -#define _POSIX_C_SOURCE 200112L -#endif - -#if !defined(_GNU_SOURCE) -/* Clang requires this to get support for explicit_bzero */ -#define _GNU_SOURCE -#endif - -#include "common.h" - -#include "mbedtls/platform_util.h" -#include "mbedtls/platform.h" -#include "mbedtls/threading.h" - -#include - -#ifndef __STDC_WANT_LIB_EXT1__ -#define __STDC_WANT_LIB_EXT1__ 1 /* Ask for the C11 gmtime_s() and memset_s() if available */ -#endif -#include - -#if defined(_WIN32) -#include -#endif - -// Detect platforms known to support explicit_bzero() -#if defined(__GLIBC__) && (__GLIBC__ >= 2) && (__GLIBC_MINOR__ >= 25) -#define MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO 1 -#elif (defined(__FreeBSD__) && (__FreeBSD_version >= 1100037)) || defined(__OpenBSD__) -#define MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO 1 -#endif - -#if !defined(MBEDTLS_PLATFORM_ZEROIZE_ALT) - -#undef HAVE_MEMORY_SANITIZER -#if defined(__has_feature) -#if __has_feature(memory_sanitizer) -#include -#define HAVE_MEMORY_SANITIZER -#endif -#endif - -/* - * Where possible, we try to detect the presence of a platform-provided - * secure memset, such as explicit_bzero(), that is safe against being optimized - * out, and use that. - * - * For other platforms, we provide an implementation that aims not to be - * optimized out by the compiler. - * - * This implementation for mbedtls_platform_zeroize() was inspired from Colin - * Percival's blog article at: - * - * http://www.daemonology.net/blog/2014-09-04-how-to-zero-a-buffer.html - * - * It uses a volatile function pointer to the standard memset(). Because the - * pointer is volatile the compiler expects it to change at - * any time and will not optimize out the call that could potentially perform - * other operations on the input buffer instead of just setting it to 0. - * Nevertheless, as pointed out by davidtgoldblatt on Hacker News - * (refer to http://www.daemonology.net/blog/2014-09-05-erratum.html for - * details), optimizations of the following form are still possible: - * - * if (memset_func != memset) - * memset_func(buf, 0, len); - * - * Note that it is extremely difficult to guarantee that - * the memset() call will not be optimized out by aggressive compilers - * in a portable way. For this reason, Mbed TLS also provides the configuration - * option MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure - * mbedtls_platform_zeroize() to use a suitable implementation for their - * platform and needs. - */ -#if !defined(MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO) && !(defined(__STDC_LIB_EXT1__) && \ - !defined(__IAR_SYSTEMS_ICC__)) \ - && !defined(_WIN32) -static void *(*const volatile memset_func)(void *, int, size_t) = memset; -#endif - -void mbedtls_platform_zeroize(void *buf, size_t len) -{ - MBEDTLS_INTERNAL_VALIDATE(len == 0 || buf != NULL); - - if (len > 0) { -#if defined(MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO) - explicit_bzero(buf, len); -#if defined(HAVE_MEMORY_SANITIZER) - /* You'd think that Msan would recognize explicit_bzero() as - * equivalent to bzero(), but it actually doesn't on several - * platforms, including Linux (Ubuntu 20.04). - * https://github.com/google/sanitizers/issues/1507 - * https://github.com/openssh/openssh-portable/commit/74433a19bb6f4cef607680fa4d1d7d81ca3826aa - */ - __msan_unpoison(buf, len); -#endif -#elif defined(__STDC_LIB_EXT1__) && !defined(__IAR_SYSTEMS_ICC__) - memset_s(buf, len, 0, len); -#elif defined(_WIN32) - SecureZeroMemory(buf, len); -#else - memset_func(buf, 0, len); -#endif - -#if defined(__GNUC__) - /* For clang and recent gcc, pretend that we have some assembly that reads the - * zero'd memory as an additional protection against being optimised away. */ -#if defined(__clang__) || (__GNUC__ >= 10) -#if defined(__clang__) -#pragma clang diagnostic push -#pragma clang diagnostic ignored "-Wvla" -#elif defined(MBEDTLS_COMPILER_IS_GCC) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wvla" -#endif - asm volatile ("" : : "m" (*(char (*)[len]) buf) :); -#if defined(__clang__) -#pragma clang diagnostic pop -#elif defined(MBEDTLS_COMPILER_IS_GCC) -#pragma GCC diagnostic pop -#endif -#endif -#endif - } -} -#endif /* MBEDTLS_PLATFORM_ZEROIZE_ALT */ - -void mbedtls_zeroize_and_free(void *buf, size_t len) -{ - if (buf != NULL) { - mbedtls_platform_zeroize(buf, len); - } - - mbedtls_free(buf); -} - -#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) -#include -#if !defined(_WIN32) && (defined(unix) || \ - defined(__unix) || defined(__unix__) || (defined(__APPLE__) && \ - defined(__MACH__))) -#include -#endif /* !_WIN32 && (unix || __unix || __unix__ || - * (__APPLE__ && __MACH__)) */ - -#if !((defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L) || \ - (defined(_POSIX_THREAD_SAFE_FUNCTIONS) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L)) -/* - * This is a convenience shorthand macro to avoid checking the long - * preprocessor conditions above. Ideally, we could expose this macro in - * platform_util.h and simply use it in platform_util.c, threading.c and - * threading.h. However, this macro is not part of the Mbed TLS public API, so - * we keep it private by only defining it in this file - */ -#if !(defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)) || \ - (defined(__MINGW32__) && !defined(__MINGW64_VERSION_MAJOR)) -#define PLATFORM_UTIL_USE_GMTIME -#endif - -#endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ - ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ - -struct tm *mbedtls_platform_gmtime_r(const mbedtls_time_t *tt, - struct tm *tm_buf) -{ -#if defined(_WIN32) && !defined(PLATFORM_UTIL_USE_GMTIME) -#if defined(__STDC_LIB_EXT1__) - return (gmtime_s(tt, tm_buf) == 0) ? NULL : tm_buf; -#else - /* MSVC and mingw64 argument order and return value are inconsistent with the C11 standard */ - return (gmtime_s(tm_buf, tt) == 0) ? tm_buf : NULL; -#endif -#elif !defined(PLATFORM_UTIL_USE_GMTIME) - return gmtime_r(tt, tm_buf); -#else - struct tm *lt; - -#if defined(MBEDTLS_THREADING_C) - if (mbedtls_mutex_lock(&mbedtls_threading_gmtime_mutex) != 0) { - return NULL; - } -#endif /* MBEDTLS_THREADING_C */ - - lt = gmtime(tt); - - if (lt != NULL) { - memcpy(tm_buf, lt, sizeof(struct tm)); - } - -#if defined(MBEDTLS_THREADING_C) - if (mbedtls_mutex_unlock(&mbedtls_threading_gmtime_mutex) != 0) { - return NULL; - } -#endif /* MBEDTLS_THREADING_C */ - - return (lt == NULL) ? NULL : tm_buf; -#endif /* _WIN32 && !EFIX64 && !EFI32 */ -} -#endif /* MBEDTLS_HAVE_TIME_DATE && MBEDTLS_PLATFORM_GMTIME_R_ALT */ - -#if defined(MBEDTLS_TEST_HOOKS) -void (*mbedtls_test_hook_test_fail)(const char *, int, const char *); -#endif /* MBEDTLS_TEST_HOOKS */ - -/* - * Provide external definitions of some inline functions so that the compiler - * has the option to not inline them - */ -extern inline void mbedtls_xor(unsigned char *r, - const unsigned char *a, - const unsigned char *b, - size_t n); - -extern inline uint16_t mbedtls_get_unaligned_uint16(const void *p); - -extern inline void mbedtls_put_unaligned_uint16(void *p, uint16_t x); - -extern inline uint32_t mbedtls_get_unaligned_uint32(const void *p); - -extern inline void mbedtls_put_unaligned_uint32(void *p, uint32_t x); - -extern inline uint64_t mbedtls_get_unaligned_uint64(const void *p); - -extern inline void mbedtls_put_unaligned_uint64(void *p, uint64_t x); - -#if defined(MBEDTLS_HAVE_TIME) && !defined(MBEDTLS_PLATFORM_MS_TIME_ALT) - -#include -#if !defined(_WIN32) && \ - (defined(unix) || defined(__unix) || defined(__unix__) || \ - (defined(__APPLE__) && defined(__MACH__))) -#include -#endif /* !_WIN32 && (unix || __unix || __unix__ || (__APPLE__ && __MACH__)) */ -#if (defined(_POSIX_VERSION) && _POSIX_VERSION >= 199309L) -mbedtls_ms_time_t mbedtls_ms_time(void) -{ - int ret; - struct timespec tv; - mbedtls_ms_time_t current_ms; - -#if defined(__linux__) - ret = clock_gettime(CLOCK_BOOTTIME, &tv); -#else - ret = clock_gettime(CLOCK_MONOTONIC, &tv); -#endif - if (ret) { - return time(NULL) * 1000; - } - - current_ms = tv.tv_sec; - - return current_ms*1000 + tv.tv_nsec / 1000000; -} -#elif defined(_WIN32) || defined(WIN32) || defined(__CYGWIN__) || \ - defined(__MINGW32__) || defined(_WIN64) -#include -mbedtls_ms_time_t mbedtls_ms_time(void) -{ - FILETIME ct; - mbedtls_ms_time_t current_ms; - - GetSystemTimeAsFileTime(&ct); - current_ms = ((mbedtls_ms_time_t) ct.dwLowDateTime + - ((mbedtls_ms_time_t) (ct.dwHighDateTime) << 32LL))/10000; - return current_ms; -} -#else -#error "No mbedtls_ms_time available" -#endif -#endif /* MBEDTLS_HAVE_TIME && !MBEDTLS_PLATFORM_MS_TIME_ALT */ +/* + * Common and shared functions used by multiple modules in the Mbed TLS + * library. + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Ensure gmtime_r is available even with -std=c99; must be defined before + * mbedtls_config.h, which pulls in glibc's features.h. Harmless on other platforms + * except OpenBSD, where it stops us accessing explicit_bzero. + */ +#if !defined(_POSIX_C_SOURCE) && !defined(__OpenBSD__) +#define _POSIX_C_SOURCE 200112L +#endif + +#if !defined(_GNU_SOURCE) +/* Clang requires this to get support for explicit_bzero */ +#define _GNU_SOURCE +#endif + +#include "common.h" + +#include "mbedtls/platform_util.h" +#include "mbedtls/platform.h" +#include "mbedtls/threading.h" + +#include + +#ifndef __STDC_WANT_LIB_EXT1__ +#define __STDC_WANT_LIB_EXT1__ 1 /* Ask for the C11 gmtime_s() and memset_s() if available */ +#endif +#include + +#if defined(_WIN32) +#include +#endif + +// Detect platforms known to support explicit_bzero() +#if defined(__GLIBC__) && (__GLIBC__ >= 2) && (__GLIBC_MINOR__ >= 25) +#define MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO 1 +#elif (defined(__FreeBSD__) && (__FreeBSD_version >= 1100037)) || defined(__OpenBSD__) +#define MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO 1 +#endif + +#if !defined(MBEDTLS_PLATFORM_ZEROIZE_ALT) + +#undef HAVE_MEMORY_SANITIZER +#if defined(__has_feature) +#if __has_feature(memory_sanitizer) +#include +#define HAVE_MEMORY_SANITIZER +#endif +#endif + +/* + * Where possible, we try to detect the presence of a platform-provided + * secure memset, such as explicit_bzero(), that is safe against being optimized + * out, and use that. + * + * For other platforms, we provide an implementation that aims not to be + * optimized out by the compiler. + * + * This implementation for mbedtls_platform_zeroize() was inspired from Colin + * Percival's blog article at: + * + * http://www.daemonology.net/blog/2014-09-04-how-to-zero-a-buffer.html + * + * It uses a volatile function pointer to the standard memset(). Because the + * pointer is volatile the compiler expects it to change at + * any time and will not optimize out the call that could potentially perform + * other operations on the input buffer instead of just setting it to 0. + * Nevertheless, as pointed out by davidtgoldblatt on Hacker News + * (refer to http://www.daemonology.net/blog/2014-09-05-erratum.html for + * details), optimizations of the following form are still possible: + * + * if (memset_func != memset) + * memset_func(buf, 0, len); + * + * Note that it is extremely difficult to guarantee that + * the memset() call will not be optimized out by aggressive compilers + * in a portable way. For this reason, Mbed TLS also provides the configuration + * option MBEDTLS_PLATFORM_ZEROIZE_ALT, which allows users to configure + * mbedtls_platform_zeroize() to use a suitable implementation for their + * platform and needs. + */ +#if !defined(MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO) && !(defined(__STDC_LIB_EXT1__) && \ + !defined(__IAR_SYSTEMS_ICC__)) \ + && !defined(_WIN32) +static void *(*const volatile memset_func)(void *, int, size_t) = memset; +#endif + +void mbedtls_platform_zeroize(void *buf, size_t len) +{ + MBEDTLS_INTERNAL_VALIDATE(len == 0 || buf != NULL); + + if (len > 0) { +#if defined(MBEDTLS_PLATFORM_HAS_EXPLICIT_BZERO) + explicit_bzero(buf, len); +#if defined(HAVE_MEMORY_SANITIZER) + /* You'd think that Msan would recognize explicit_bzero() as + * equivalent to bzero(), but it actually doesn't on several + * platforms, including Linux (Ubuntu 20.04). + * https://github.com/google/sanitizers/issues/1507 + * https://github.com/openssh/openssh-portable/commit/74433a19bb6f4cef607680fa4d1d7d81ca3826aa + */ + __msan_unpoison(buf, len); +#endif +#elif defined(__STDC_LIB_EXT1__) && !defined(__IAR_SYSTEMS_ICC__) + memset_s(buf, len, 0, len); +#elif defined(_WIN32) + SecureZeroMemory(buf, len); +#else + memset_func(buf, 0, len); +#endif + +#if defined(__GNUC__) + /* For clang and recent gcc, pretend that we have some assembly that reads the + * zero'd memory as an additional protection against being optimised away. */ +#if defined(__clang__) || (__GNUC__ >= 10) +#if defined(__clang__) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wvla" +#elif defined(MBEDTLS_COMPILER_IS_GCC) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wvla" +#endif + asm volatile ("" : : "m" (*(char (*)[len]) buf) :); +#if defined(__clang__) +#pragma clang diagnostic pop +#elif defined(MBEDTLS_COMPILER_IS_GCC) +#pragma GCC diagnostic pop +#endif +#endif +#endif + } +} +#endif /* MBEDTLS_PLATFORM_ZEROIZE_ALT */ + +void mbedtls_zeroize_and_free(void *buf, size_t len) +{ + if (buf != NULL) { + mbedtls_platform_zeroize(buf, len); + } + + mbedtls_free(buf); +} + +#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) +#include +#if !defined(_WIN32) && (defined(unix) || \ + defined(__unix) || defined(__unix__) || (defined(__APPLE__) && \ + defined(__MACH__))) +#include +#endif /* !_WIN32 && (unix || __unix || __unix__ || + * (__APPLE__ && __MACH__)) */ + +#if !((defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L) || \ + (defined(_POSIX_THREAD_SAFE_FUNCTIONS) && \ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L)) +/* + * This is a convenience shorthand macro to avoid checking the long + * preprocessor conditions above. Ideally, we could expose this macro in + * platform_util.h and simply use it in platform_util.c, threading.c and + * threading.h. However, this macro is not part of the Mbed TLS public API, so + * we keep it private by only defining it in this file + */ +#if !(defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)) || \ + (defined(__MINGW32__) && !defined(__MINGW64_VERSION_MAJOR)) +#define PLATFORM_UTIL_USE_GMTIME +#endif + +#endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ + ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ + +struct tm *mbedtls_platform_gmtime_r(const mbedtls_time_t *tt, + struct tm *tm_buf) +{ +#if defined(_WIN32) && !defined(PLATFORM_UTIL_USE_GMTIME) +#if defined(__STDC_LIB_EXT1__) + return (gmtime_s(tt, tm_buf) == 0) ? NULL : tm_buf; +#else + /* MSVC and mingw64 argument order and return value are inconsistent with the C11 standard */ + return (gmtime_s(tm_buf, tt) == 0) ? tm_buf : NULL; +#endif +#elif !defined(PLATFORM_UTIL_USE_GMTIME) + return gmtime_r(tt, tm_buf); +#else + struct tm *lt; + +#if defined(MBEDTLS_THREADING_C) + if (mbedtls_mutex_lock(&mbedtls_threading_gmtime_mutex) != 0) { + return NULL; + } +#endif /* MBEDTLS_THREADING_C */ + + lt = gmtime(tt); + + if (lt != NULL) { + memcpy(tm_buf, lt, sizeof(struct tm)); + } + +#if defined(MBEDTLS_THREADING_C) + if (mbedtls_mutex_unlock(&mbedtls_threading_gmtime_mutex) != 0) { + return NULL; + } +#endif /* MBEDTLS_THREADING_C */ + + return (lt == NULL) ? NULL : tm_buf; +#endif /* _WIN32 && !EFIX64 && !EFI32 */ +} +#endif /* MBEDTLS_HAVE_TIME_DATE && MBEDTLS_PLATFORM_GMTIME_R_ALT */ + +#if defined(MBEDTLS_TEST_HOOKS) +void (*mbedtls_test_hook_test_fail)(const char *, int, const char *); +#endif /* MBEDTLS_TEST_HOOKS */ + +/* + * Provide external definitions of some inline functions so that the compiler + * has the option to not inline them + */ +extern inline void mbedtls_xor(unsigned char *r, + const unsigned char *a, + const unsigned char *b, + size_t n); + +extern inline uint16_t mbedtls_get_unaligned_uint16(const void *p); + +extern inline void mbedtls_put_unaligned_uint16(void *p, uint16_t x); + +extern inline uint32_t mbedtls_get_unaligned_uint32(const void *p); + +extern inline void mbedtls_put_unaligned_uint32(void *p, uint32_t x); + +extern inline uint64_t mbedtls_get_unaligned_uint64(const void *p); + +extern inline void mbedtls_put_unaligned_uint64(void *p, uint64_t x); + +#if defined(MBEDTLS_HAVE_TIME) && !defined(MBEDTLS_PLATFORM_MS_TIME_ALT) + +#include +#if !defined(_WIN32) && \ + (defined(unix) || defined(__unix) || defined(__unix__) || \ + (defined(__APPLE__) && defined(__MACH__))) +#include +#endif /* !_WIN32 && (unix || __unix || __unix__ || (__APPLE__ && __MACH__)) */ +#if (defined(_POSIX_VERSION) && _POSIX_VERSION >= 199309L) +mbedtls_ms_time_t mbedtls_ms_time(void) +{ + int ret; + struct timespec tv; + mbedtls_ms_time_t current_ms; + +#if defined(__linux__) + ret = clock_gettime(CLOCK_BOOTTIME, &tv); +#else + ret = clock_gettime(CLOCK_MONOTONIC, &tv); +#endif + if (ret) { + return time(NULL) * 1000; + } + + current_ms = tv.tv_sec; + + return current_ms*1000 + tv.tv_nsec / 1000000; +} +#elif defined(_WIN32) || defined(WIN32) || defined(__CYGWIN__) || \ + defined(__MINGW32__) || defined(_WIN64) +#include +mbedtls_ms_time_t mbedtls_ms_time(void) +{ + FILETIME ct; + mbedtls_ms_time_t current_ms; + + GetSystemTimeAsFileTime(&ct); + current_ms = ((mbedtls_ms_time_t) ct.dwLowDateTime + + ((mbedtls_ms_time_t) (ct.dwHighDateTime) << 32LL))/10000; + return current_ms; +} +#else +#error "No mbedtls_ms_time available" +#endif +#endif /* MBEDTLS_HAVE_TIME && !MBEDTLS_PLATFORM_MS_TIME_ALT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto.c index ba81061..b6199fd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto.c @@ -1,8752 +1,8752 @@ -/* - * PSA crypto layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" -#include "psa_crypto_core_common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) -#include "check_crypto_config.h" -#endif - -#include "psa/crypto.h" -#include "psa/crypto_values.h" - -#include "psa_crypto_cipher.h" -#include "psa_crypto_core.h" -#include "psa_crypto_invasive.h" -#include "psa_crypto_driver_wrappers.h" -#include "psa_crypto_driver_wrappers_no_static.h" -#include "psa_crypto_ecp.h" -#include "psa_crypto_ffdh.h" -#include "psa_crypto_hash.h" -#include "psa_crypto_mac.h" -#include "psa_crypto_rsa.h" -#include "psa_crypto_ecp.h" -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -#include "psa_crypto_se.h" -#endif -#include "psa_crypto_slot_management.h" -/* Include internal declarations that are useful for implementing persistently - * stored keys. */ -#include "psa_crypto_storage.h" - -#include "psa_crypto_random_impl.h" - -#include -#include -#include "mbedtls/platform.h" - -#include "mbedtls/aes.h" -#include "mbedtls/asn1.h" -#include "mbedtls/asn1write.h" -#include "mbedtls/bignum.h" -#include "mbedtls/camellia.h" -#include "mbedtls/chacha20.h" -#include "mbedtls/chachapoly.h" -#include "mbedtls/cipher.h" -#include "mbedtls/ccm.h" -#include "mbedtls/cmac.h" -#include "mbedtls/constant_time.h" -#include "mbedtls/des.h" -#include "mbedtls/ecdh.h" -#include "mbedtls/ecp.h" -#include "mbedtls/entropy.h" -#include "mbedtls/error.h" -#include "mbedtls/gcm.h" -#include "mbedtls/md5.h" -#include "mbedtls/md.h" -#include "mbedtls/pk.h" -#include "pk_wrap.h" -#include "mbedtls/platform_util.h" -#include "mbedtls/psa_util.h" -#include "mbedtls/error.h" -#include "mbedtls/ripemd160.h" -#include "mbedtls/rsa.h" -#include "mbedtls/sha1.h" -#include "mbedtls/sha256.h" -#include "mbedtls/sha512.h" -#include "mbedtls/threading.h" -#include "md_psa.h" - -#include "sli_psa_crypto.h" - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) -#define BUILTIN_ALG_ANY_HKDF 1 -#endif - -/****************************************************************/ -/* Global data, support functions and library management */ -/****************************************************************/ - -static int key_type_is_raw_bytes(psa_key_type_t type) -{ - return PSA_KEY_TYPE_IS_UNSTRUCTURED(type); -} - -/* Values for psa_global_data_t::rng_state */ -#define RNG_NOT_INITIALIZED 0 -#define RNG_INITIALIZED 1 -#define RNG_SEEDED 2 - -typedef struct { - uint8_t initialized; - uint8_t rng_state; - uint8_t drivers_initialized; - mbedtls_psa_random_context_t rng; -} psa_global_data_t; - -static psa_global_data_t global_data; - -#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state = - &global_data.rng.drbg; -#endif - -#define GUARD_MODULE_INITIALIZED \ - if (global_data.initialized == 0) \ - return PSA_ERROR_BAD_STATE; - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) || \ - defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) -static int psa_is_dh_key_size_valid(size_t bits) -{ - if (bits != 2048 && bits != 3072 && bits != 4096 && - bits != 6144 && bits != 8192) { - return 0; - } - - return 1; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT || - MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY || - PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE */ - -psa_status_t mbedtls_to_psa_error(int ret) -{ - /* Mbed TLS error codes can combine a high-level error code and a - * low-level error code. The low-level error usually reflects the - * root cause better, so dispatch on that preferably. */ - int low_level_ret = -(-ret & 0x007f); - switch (low_level_ret != 0 ? low_level_ret : ret) { - case 0: - return PSA_SUCCESS; - -#if defined(MBEDTLS_AES_C) - case MBEDTLS_ERR_AES_INVALID_KEY_LENGTH: - case MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_AES_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; -#endif - -#if defined(MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_ASN1_WRITE_C) - case MBEDTLS_ERR_ASN1_OUT_OF_DATA: - case MBEDTLS_ERR_ASN1_UNEXPECTED_TAG: - case MBEDTLS_ERR_ASN1_INVALID_LENGTH: - case MBEDTLS_ERR_ASN1_LENGTH_MISMATCH: - case MBEDTLS_ERR_ASN1_INVALID_DATA: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_ASN1_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; - case MBEDTLS_ERR_ASN1_BUF_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; -#endif - -#if defined(MBEDTLS_CAMELLIA_C) - case MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA: - case MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH: - return PSA_ERROR_NOT_SUPPORTED; -#endif - -#if defined(MBEDTLS_CCM_C) - case MBEDTLS_ERR_CCM_BAD_INPUT: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_CCM_AUTH_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; -#endif - -#if defined(MBEDTLS_CHACHA20_C) - case MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; -#endif - -#if defined(MBEDTLS_CHACHAPOLY_C) - case MBEDTLS_ERR_CHACHAPOLY_BAD_STATE: - return PSA_ERROR_BAD_STATE; - case MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; -#endif - -#if defined(MBEDTLS_CIPHER_C) - case MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_CIPHER_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; - case MBEDTLS_ERR_CIPHER_INVALID_PADDING: - return PSA_ERROR_INVALID_PADDING; - case MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_CIPHER_AUTH_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; - case MBEDTLS_ERR_CIPHER_INVALID_CONTEXT: - return PSA_ERROR_CORRUPTION_DETECTED; -#endif - -#if !(defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) || \ - defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE)) - /* Only check CTR_DRBG error codes if underlying mbedtls_xxx - * functions are passed a CTR_DRBG instance. */ - case MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED: - return PSA_ERROR_INSUFFICIENT_ENTROPY; - case MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG: - case MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR: - return PSA_ERROR_INSUFFICIENT_ENTROPY; -#endif - -#if defined(MBEDTLS_DES_C) - case MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH: - return PSA_ERROR_NOT_SUPPORTED; -#endif - - case MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED: - case MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE: - case MBEDTLS_ERR_ENTROPY_SOURCE_FAILED: - return PSA_ERROR_INSUFFICIENT_ENTROPY; - -#if defined(MBEDTLS_GCM_C) - case MBEDTLS_ERR_GCM_AUTH_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; - case MBEDTLS_ERR_GCM_BUFFER_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; - case MBEDTLS_ERR_GCM_BAD_INPUT: - return PSA_ERROR_INVALID_ARGUMENT; -#endif - -#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) && \ - defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE) - /* Only check HMAC_DRBG error codes if underlying mbedtls_xxx - * functions are passed a HMAC_DRBG instance. */ - case MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED: - return PSA_ERROR_INSUFFICIENT_ENTROPY; - case MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG: - case MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR: - return PSA_ERROR_INSUFFICIENT_ENTROPY; -#endif - -#if defined(MBEDTLS_MD_LIGHT) - case MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_MD_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MD_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; -#if defined(MBEDTLS_FS_IO) - case MBEDTLS_ERR_MD_FILE_IO_ERROR: - return PSA_ERROR_STORAGE_FAILURE; -#endif -#endif - -#if defined(MBEDTLS_BIGNUM_C) -#if defined(MBEDTLS_FS_IO) - case MBEDTLS_ERR_MPI_FILE_IO_ERROR: - return PSA_ERROR_STORAGE_FAILURE; -#endif - case MBEDTLS_ERR_MPI_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MPI_INVALID_CHARACTER: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; - case MBEDTLS_ERR_MPI_NEGATIVE_VALUE: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MPI_DIVISION_BY_ZERO: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MPI_NOT_ACCEPTABLE: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_MPI_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; -#endif - -#if defined(MBEDTLS_PK_C) - case MBEDTLS_ERR_PK_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; - case MBEDTLS_ERR_PK_TYPE_MISMATCH: - case MBEDTLS_ERR_PK_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || defined(MBEDTLS_FS_IO) || \ - defined(MBEDTLS_PSA_ITS_FILE_C) - case MBEDTLS_ERR_PK_FILE_IO_ERROR: - return PSA_ERROR_STORAGE_FAILURE; -#endif - case MBEDTLS_ERR_PK_KEY_INVALID_VERSION: - case MBEDTLS_ERR_PK_KEY_INVALID_FORMAT: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_PK_UNKNOWN_PK_ALG: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_PK_PASSWORD_REQUIRED: - case MBEDTLS_ERR_PK_PASSWORD_MISMATCH: - return PSA_ERROR_NOT_PERMITTED; - case MBEDTLS_ERR_PK_INVALID_PUBKEY: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_PK_INVALID_ALG: - case MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE: - case MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_PK_SIG_LEN_MISMATCH: - return PSA_ERROR_INVALID_SIGNATURE; - case MBEDTLS_ERR_PK_BUFFER_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; -#endif - - case MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED: - return PSA_ERROR_HARDWARE_FAILURE; - case MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED: - return PSA_ERROR_NOT_SUPPORTED; - -#if defined(MBEDTLS_RSA_C) - case MBEDTLS_ERR_RSA_BAD_INPUT_DATA: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_RSA_INVALID_PADDING: - return PSA_ERROR_INVALID_PADDING; - case MBEDTLS_ERR_RSA_KEY_GEN_FAILED: - return PSA_ERROR_HARDWARE_FAILURE; - case MBEDTLS_ERR_RSA_KEY_CHECK_FAILED: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_RSA_PUBLIC_FAILED: - case MBEDTLS_ERR_RSA_PRIVATE_FAILED: - return PSA_ERROR_CORRUPTION_DETECTED; - case MBEDTLS_ERR_RSA_VERIFY_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; - case MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE: - return PSA_ERROR_BUFFER_TOO_SMALL; - case MBEDTLS_ERR_RSA_RNG_FAILED: - return PSA_ERROR_INSUFFICIENT_ENTROPY; -#endif - -#if defined(MBEDTLS_ECP_LIGHT) - case MBEDTLS_ERR_ECP_BAD_INPUT_DATA: - case MBEDTLS_ERR_ECP_INVALID_KEY: - return PSA_ERROR_INVALID_ARGUMENT; - case MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; - case MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH: - case MBEDTLS_ERR_ECP_VERIFY_FAILED: - return PSA_ERROR_INVALID_SIGNATURE; - case MBEDTLS_ERR_ECP_ALLOC_FAILED: - return PSA_ERROR_INSUFFICIENT_MEMORY; - case MBEDTLS_ERR_ECP_RANDOM_FAILED: - return PSA_ERROR_INSUFFICIENT_ENTROPY; - -#if defined(MBEDTLS_ECP_RESTARTABLE) - case MBEDTLS_ERR_ECP_IN_PROGRESS: - return PSA_OPERATION_INCOMPLETE; -#endif -#endif - - case MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: - return PSA_ERROR_CORRUPTION_DETECTED; - - default: - return PSA_ERROR_GENERIC_ERROR; - } -} - -/** - * \brief For output buffers which contain "tags" - * (outputs that may be checked for validity like - * hashes, MACs and signatures), fill the unused - * part of the output buffer (the whole buffer on - * error, the trailing part on success) with - * something that isn't a valid tag (barring an - * attack on the tag and deliberately-crafted - * input), in case the caller doesn't check the - * return status properly. - * - * \param output_buffer Pointer to buffer to wipe. May not be NULL - * unless \p output_buffer_size is zero. - * \param status Status of function called to generate - * output_buffer originally - * \param output_buffer_size Size of output buffer. If zero, \p output_buffer - * could be NULL. - * \param output_buffer_length Length of data written to output_buffer, must be - * less than \p output_buffer_size - */ -static void psa_wipe_tag_output_buffer(uint8_t *output_buffer, psa_status_t status, - size_t output_buffer_size, size_t output_buffer_length) -{ - size_t offset = 0; - - if (output_buffer_size == 0) { - /* If output_buffer_size is 0 then we have nothing to do. We must not - call memset because output_buffer may be NULL in this case */ - return; - } - - if (status == PSA_SUCCESS) { - offset = output_buffer_length; - } - - memset(output_buffer + offset, '!', output_buffer_size - offset); -} - - - - -/****************************************************************/ -/* Key management */ -/****************************************************************/ - -#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -psa_ecc_family_t mbedtls_ecc_group_to_psa(mbedtls_ecp_group_id grpid, - size_t *bits) -{ - switch (grpid) { -#if defined(MBEDTLS_ECP_HAVE_SECP192R1) - case MBEDTLS_ECP_DP_SECP192R1: - *bits = 192; - return PSA_ECC_FAMILY_SECP_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP224R1) - case MBEDTLS_ECP_DP_SECP224R1: - *bits = 224; - return PSA_ECC_FAMILY_SECP_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP256R1) - case MBEDTLS_ECP_DP_SECP256R1: - *bits = 256; - return PSA_ECC_FAMILY_SECP_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP384R1) - case MBEDTLS_ECP_DP_SECP384R1: - *bits = 384; - return PSA_ECC_FAMILY_SECP_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP521R1) - case MBEDTLS_ECP_DP_SECP521R1: - *bits = 521; - return PSA_ECC_FAMILY_SECP_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_BP256R1) - case MBEDTLS_ECP_DP_BP256R1: - *bits = 256; - return PSA_ECC_FAMILY_BRAINPOOL_P_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_BP384R1) - case MBEDTLS_ECP_DP_BP384R1: - *bits = 384; - return PSA_ECC_FAMILY_BRAINPOOL_P_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_BP512R1) - case MBEDTLS_ECP_DP_BP512R1: - *bits = 512; - return PSA_ECC_FAMILY_BRAINPOOL_P_R1; -#endif -#if defined(MBEDTLS_ECP_HAVE_CURVE25519) - case MBEDTLS_ECP_DP_CURVE25519: - *bits = 255; - return PSA_ECC_FAMILY_MONTGOMERY; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP192K1) - case MBEDTLS_ECP_DP_SECP192K1: - *bits = 192; - return PSA_ECC_FAMILY_SECP_K1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP224K1) - case MBEDTLS_ECP_DP_SECP224K1: - *bits = 224; - return PSA_ECC_FAMILY_SECP_K1; -#endif -#if defined(MBEDTLS_ECP_HAVE_SECP256K1) - case MBEDTLS_ECP_DP_SECP256K1: - *bits = 256; - return PSA_ECC_FAMILY_SECP_K1; -#endif -#if defined(MBEDTLS_ECP_HAVE_CURVE448) - case MBEDTLS_ECP_DP_CURVE448: - *bits = 448; - return PSA_ECC_FAMILY_MONTGOMERY; -#endif - default: - *bits = 0; - return 0; - } -} - -mbedtls_ecp_group_id mbedtls_ecc_group_of_psa(psa_ecc_family_t curve, - size_t bits, - int bits_is_sloppy) -{ - switch (curve) { - case PSA_ECC_FAMILY_SECP_R1: - switch (bits) { -#if defined(PSA_WANT_ECC_SECP_R1_192) - case 192: - return MBEDTLS_ECP_DP_SECP192R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_224) - case 224: - return MBEDTLS_ECP_DP_SECP224R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_256) - case 256: - return MBEDTLS_ECP_DP_SECP256R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_384) - case 384: - return MBEDTLS_ECP_DP_SECP384R1; -#endif -#if defined(PSA_WANT_ECC_SECP_R1_521) - case 521: - return MBEDTLS_ECP_DP_SECP521R1; - case 528: - if (bits_is_sloppy) { - return MBEDTLS_ECP_DP_SECP521R1; - } - break; -#endif - } - break; - - case PSA_ECC_FAMILY_BRAINPOOL_P_R1: - switch (bits) { -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) - case 256: - return MBEDTLS_ECP_DP_BP256R1; -#endif -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) - case 384: - return MBEDTLS_ECP_DP_BP384R1; -#endif -#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) - case 512: - return MBEDTLS_ECP_DP_BP512R1; -#endif - } - break; - - case PSA_ECC_FAMILY_MONTGOMERY: - switch (bits) { -#if defined(PSA_WANT_ECC_MONTGOMERY_255) - case 255: - return MBEDTLS_ECP_DP_CURVE25519; - case 256: - if (bits_is_sloppy) { - return MBEDTLS_ECP_DP_CURVE25519; - } - break; -#endif -#if defined(PSA_WANT_ECC_MONTGOMERY_448) - case 448: - return MBEDTLS_ECP_DP_CURVE448; -#endif - } - break; - - case PSA_ECC_FAMILY_SECP_K1: - switch (bits) { -#if defined(PSA_WANT_ECC_SECP_K1_192) - case 192: - return MBEDTLS_ECP_DP_SECP192K1; -#endif -#if defined(PSA_WANT_ECC_SECP_K1_224) - case 224: - return MBEDTLS_ECP_DP_SECP224K1; -#endif -#if defined(PSA_WANT_ECC_SECP_K1_256) - case 256: - return MBEDTLS_ECP_DP_SECP256K1; -#endif - } - break; - } - - (void) bits_is_sloppy; - return MBEDTLS_ECP_DP_NONE; -} -#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ - -psa_status_t psa_validate_unstructured_key_bit_size(psa_key_type_t type, - size_t bits) -{ - /* Check that the bit size is acceptable for the key type */ - switch (type) { - case PSA_KEY_TYPE_RAW_DATA: - case PSA_KEY_TYPE_HMAC: - case PSA_KEY_TYPE_DERIVE: - case PSA_KEY_TYPE_PASSWORD: - case PSA_KEY_TYPE_PASSWORD_HASH: - break; -#if defined(PSA_WANT_KEY_TYPE_AES) - case PSA_KEY_TYPE_AES: - if (bits != 128 && bits != 192 && bits != 256) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif -#if defined(PSA_WANT_KEY_TYPE_ARIA) - case PSA_KEY_TYPE_ARIA: - if (bits != 128 && bits != 192 && bits != 256) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif -#if defined(PSA_WANT_KEY_TYPE_CAMELLIA) - case PSA_KEY_TYPE_CAMELLIA: - if (bits != 128 && bits != 192 && bits != 256) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif -#if defined(PSA_WANT_KEY_TYPE_DES) - case PSA_KEY_TYPE_DES: - if (bits != 64 && bits != 128 && bits != 192) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif -#if defined(PSA_WANT_KEY_TYPE_CHACHA20) - case PSA_KEY_TYPE_CHACHA20: - if (bits != 256) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif - default: - return PSA_ERROR_NOT_SUPPORTED; - } - if (bits % 8 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -/** Check whether a given key type is valid for use with a given MAC algorithm - * - * Upon successful return of this function, the behavior of #PSA_MAC_LENGTH - * when called with the validated \p algorithm and \p key_type is well-defined. - * - * \param[in] algorithm The specific MAC algorithm (can be wildcard). - * \param[in] key_type The key type of the key to be used with the - * \p algorithm. - * - * \retval #PSA_SUCCESS - * The \p key_type is valid for use with the \p algorithm - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The \p key_type is not valid for use with the \p algorithm - */ -MBEDTLS_STATIC_TESTABLE psa_status_t psa_mac_key_can_do( - psa_algorithm_t algorithm, - psa_key_type_t key_type) -{ - if (PSA_ALG_IS_HMAC(algorithm)) { - if (key_type == PSA_KEY_TYPE_HMAC) { - return PSA_SUCCESS; - } - } - - if (PSA_ALG_IS_BLOCK_CIPHER_MAC(algorithm)) { - /* Check that we're calling PSA_BLOCK_CIPHER_BLOCK_LENGTH with a cipher - * key. */ - if ((key_type & PSA_KEY_TYPE_CATEGORY_MASK) == - PSA_KEY_TYPE_CATEGORY_SYMMETRIC) { - /* PSA_BLOCK_CIPHER_BLOCK_LENGTH returns 1 for stream ciphers and - * the block length (larger than 1) for block ciphers. */ - if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) > 1) { - return PSA_SUCCESS; - } - } - } - - return PSA_ERROR_INVALID_ARGUMENT; -} - -psa_status_t psa_allocate_buffer_to_slot(psa_key_slot_t *slot, - size_t buffer_length) -{ - if (slot->key.data != NULL) { - return PSA_ERROR_ALREADY_EXISTS; - } - - slot->key.data = mbedtls_calloc(1, buffer_length); - if (slot->key.data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - slot->key.bytes = buffer_length; - return PSA_SUCCESS; -} - -psa_status_t psa_copy_key_material_into_slot(psa_key_slot_t *slot, - const uint8_t *data, - size_t data_length) -{ - psa_status_t status = psa_allocate_buffer_to_slot(slot, - data_length); - if (status != PSA_SUCCESS) { - return status; - } - - memcpy(slot->key.data, data, data_length); - return PSA_SUCCESS; -} - -psa_status_t psa_import_key_into_slot( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_type_t type = attributes->core.type; - - /* zero-length keys are never supported. */ - if (data_length == 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (key_type_is_raw_bytes(type)) { - if (*bits == 0) { - *bits = PSA_BYTES_TO_BITS(data_length); - } - - status = psa_validate_unstructured_key_bit_size(attributes->core.type, - *bits); - if (status != PSA_SUCCESS) { - return status; - } - - /* Copy the key material. */ - if (PSA_BITS_TO_BYTES(*bits) != data_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (PSA_BITS_TO_BYTES(*bits) > key_buffer_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(key_buffer, data, PSA_BITS_TO_BYTES(*bits)); - *key_buffer_length = PSA_BITS_TO_BYTES(*bits); - - return PSA_SUCCESS; - } - else if( PSA_KEY_TYPE_IS_ASYMMETRIC( type ) ) - { -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) - if( PSA_KEY_TYPE_IS_ECC( type ) ) - { - return( mbedtls_psa_ecp_import_key( attributes, - data, data_length, - key_buffer, key_buffer_size, - key_buffer_length, - bits ) ); - } -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ -#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) - if (PSA_KEY_TYPE_IS_RSA(type)) { - return mbedtls_psa_rsa_import_key(attributes, - data, data_length, - key_buffer, key_buffer_size, - key_buffer_length, - bits); - } -#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - } - - return PSA_ERROR_NOT_SUPPORTED; -} - -/** Calculate the intersection of two algorithm usage policies. - * - * Return 0 (which allows no operation) on incompatibility. - */ -static psa_algorithm_t psa_key_policy_algorithm_intersection( - psa_key_type_t key_type, - psa_algorithm_t alg1, - psa_algorithm_t alg2) -{ - /* Common case: both sides actually specify the same policy. */ - if (alg1 == alg2) { - return alg1; - } - /* If the policies are from the same hash-and-sign family, check - * if one is a wildcard. If so the other has the specific algorithm. */ - if (PSA_ALG_IS_SIGN_HASH(alg1) && - PSA_ALG_IS_SIGN_HASH(alg2) && - (alg1 & ~PSA_ALG_HASH_MASK) == (alg2 & ~PSA_ALG_HASH_MASK)) { - if (PSA_ALG_SIGN_GET_HASH(alg1) == PSA_ALG_ANY_HASH) { - return alg2; - } - if (PSA_ALG_SIGN_GET_HASH(alg2) == PSA_ALG_ANY_HASH) { - return alg1; - } - } - /* If the policies are from the same AEAD family, check whether - * one of them is a minimum-tag-length wildcard. Calculate the most - * restrictive tag length. */ - if (PSA_ALG_IS_AEAD(alg1) && PSA_ALG_IS_AEAD(alg2) && - (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg1, 0) == - PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg2, 0))) { - size_t alg1_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg1); - size_t alg2_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg2); - size_t restricted_len = alg1_len > alg2_len ? alg1_len : alg2_len; - - /* If both are wildcards, return most restrictive wildcard */ - if (((alg1 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && - ((alg2 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { - return PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG( - alg1, restricted_len); - } - /* If only one is a wildcard, return specific algorithm if compatible. */ - if (((alg1 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && - (alg1_len <= alg2_len)) { - return alg2; - } - if (((alg2 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && - (alg2_len <= alg1_len)) { - return alg1; - } - } - /* If the policies are from the same MAC family, check whether one - * of them is a minimum-MAC-length policy. Calculate the most - * restrictive tag length. */ - if (PSA_ALG_IS_MAC(alg1) && PSA_ALG_IS_MAC(alg2) && - (PSA_ALG_FULL_LENGTH_MAC(alg1) == - PSA_ALG_FULL_LENGTH_MAC(alg2))) { - /* Validate the combination of key type and algorithm. Since the base - * algorithm of alg1 and alg2 are the same, we only need this once. */ - if (PSA_SUCCESS != psa_mac_key_can_do(alg1, key_type)) { - return 0; - } - - /* Get the (exact or at-least) output lengths for both sides of the - * requested intersection. None of the currently supported algorithms - * have an output length dependent on the actual key size, so setting it - * to a bogus value of 0 is currently OK. - * - * Note that for at-least-this-length wildcard algorithms, the output - * length is set to the shortest allowed length, which allows us to - * calculate the most restrictive tag length for the intersection. */ - size_t alg1_len = PSA_MAC_LENGTH(key_type, 0, alg1); - size_t alg2_len = PSA_MAC_LENGTH(key_type, 0, alg2); - size_t restricted_len = alg1_len > alg2_len ? alg1_len : alg2_len; - - /* If both are wildcards, return most restrictive wildcard */ - if (((alg1 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) && - ((alg2 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { - return PSA_ALG_AT_LEAST_THIS_LENGTH_MAC(alg1, restricted_len); - } - - /* If only one is an at-least-this-length policy, the intersection would - * be the other (fixed-length) policy as long as said fixed length is - * equal to or larger than the shortest allowed length. */ - if ((alg1 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { - return (alg1_len <= alg2_len) ? alg2 : 0; - } - if ((alg2 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { - return (alg2_len <= alg1_len) ? alg1 : 0; - } - - /* If none of them are wildcards, check whether they define the same tag - * length. This is still possible here when one is default-length and - * the other specific-length. Ensure to always return the - * specific-length version for the intersection. */ - if (alg1_len == alg2_len) { - return PSA_ALG_TRUNCATED_MAC(alg1, alg1_len); - } - } - /* If the policies are incompatible, allow nothing. */ - return 0; -} - -static int psa_key_algorithm_permits(psa_key_type_t key_type, - psa_algorithm_t policy_alg, - psa_algorithm_t requested_alg) -{ - /* Common case: the policy only allows requested_alg. */ - if (requested_alg == policy_alg) { - return 1; - } - /* If policy_alg is a hash-and-sign with a wildcard for the hash, - * and requested_alg is the same hash-and-sign family with any hash, - * then requested_alg is compliant with policy_alg. */ - if (PSA_ALG_IS_SIGN_HASH(requested_alg) && - PSA_ALG_SIGN_GET_HASH(policy_alg) == PSA_ALG_ANY_HASH) { - return (policy_alg & ~PSA_ALG_HASH_MASK) == - (requested_alg & ~PSA_ALG_HASH_MASK); - } - /* If policy_alg is a wildcard AEAD algorithm of the same base as - * the requested algorithm, check the requested tag length to be - * equal-length or longer than the wildcard-specified length. */ - if (PSA_ALG_IS_AEAD(policy_alg) && - PSA_ALG_IS_AEAD(requested_alg) && - (PSA_ALG_AEAD_WITH_SHORTENED_TAG(policy_alg, 0) == - PSA_ALG_AEAD_WITH_SHORTENED_TAG(requested_alg, 0)) && - ((policy_alg & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { - return PSA_ALG_AEAD_GET_TAG_LENGTH(policy_alg) <= - PSA_ALG_AEAD_GET_TAG_LENGTH(requested_alg); - } - /* If policy_alg is a MAC algorithm of the same base as the requested - * algorithm, check whether their MAC lengths are compatible. */ - if (PSA_ALG_IS_MAC(policy_alg) && - PSA_ALG_IS_MAC(requested_alg) && - (PSA_ALG_FULL_LENGTH_MAC(policy_alg) == - PSA_ALG_FULL_LENGTH_MAC(requested_alg))) { - /* Validate the combination of key type and algorithm. Since the policy - * and requested algorithms are the same, we only need this once. */ - if (PSA_SUCCESS != psa_mac_key_can_do(policy_alg, key_type)) { - return 0; - } - - /* Get both the requested output length for the algorithm which is to be - * verified, and the default output length for the base algorithm. - * Note that none of the currently supported algorithms have an output - * length dependent on actual key size, so setting it to a bogus value - * of 0 is currently OK. */ - size_t requested_output_length = PSA_MAC_LENGTH( - key_type, 0, requested_alg); - size_t default_output_length = PSA_MAC_LENGTH( - key_type, 0, - PSA_ALG_FULL_LENGTH_MAC(requested_alg)); - - /* If the policy is default-length, only allow an algorithm with - * a declared exact-length matching the default. */ - if (PSA_MAC_TRUNCATED_LENGTH(policy_alg) == 0) { - return requested_output_length == default_output_length; - } - - /* If the requested algorithm is default-length, allow it if the policy - * length exactly matches the default length. */ - if (PSA_MAC_TRUNCATED_LENGTH(requested_alg) == 0 && - PSA_MAC_TRUNCATED_LENGTH(policy_alg) == default_output_length) { - return 1; - } - - /* If policy_alg is an at-least-this-length wildcard MAC algorithm, - * check for the requested MAC length to be equal to or longer than the - * minimum allowed length. */ - if ((policy_alg & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { - return PSA_MAC_TRUNCATED_LENGTH(policy_alg) <= - requested_output_length; - } - } - /* If policy_alg is a generic key agreement operation, then using it for - * a key derivation with that key agreement should also be allowed. This - * behaviour is expected to be defined in a future specification version. */ - if (PSA_ALG_IS_RAW_KEY_AGREEMENT(policy_alg) && - PSA_ALG_IS_KEY_AGREEMENT(requested_alg)) { - return PSA_ALG_KEY_AGREEMENT_GET_BASE(requested_alg) == - policy_alg; - } - /* If it isn't explicitly permitted, it's forbidden. */ - return 0; -} - -/** Test whether a policy permits an algorithm. - * - * The caller must test usage flags separately. - * - * \note This function requires providing the key type for which the policy is - * being validated, since some algorithm policy definitions (e.g. MAC) - * have different properties depending on what kind of cipher it is - * combined with. - * - * \retval PSA_SUCCESS When \p alg is a specific algorithm - * allowed by the \p policy. - * \retval PSA_ERROR_INVALID_ARGUMENT When \p alg is not a specific algorithm - * \retval PSA_ERROR_NOT_PERMITTED When \p alg is a specific algorithm, but - * the \p policy does not allow it. - */ -static psa_status_t psa_key_policy_permits(const psa_key_policy_t *policy, - psa_key_type_t key_type, - psa_algorithm_t alg) -{ - /* '0' is not a valid algorithm */ - if (alg == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* A requested algorithm cannot be a wildcard. */ - if (PSA_ALG_IS_WILDCARD(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (psa_key_algorithm_permits(key_type, policy->alg, alg) || - psa_key_algorithm_permits(key_type, policy->alg2, alg)) { - return PSA_SUCCESS; - } else { - return PSA_ERROR_NOT_PERMITTED; - } -} - -/** Restrict a key policy based on a constraint. - * - * \note This function requires providing the key type for which the policy is - * being restricted, since some algorithm policy definitions (e.g. MAC) - * have different properties depending on what kind of cipher it is - * combined with. - * - * \param[in] key_type The key type for which to restrict the policy - * \param[in,out] policy The policy to restrict. - * \param[in] constraint The policy constraint to apply. - * - * \retval #PSA_SUCCESS - * \c *policy contains the intersection of the original value of - * \c *policy and \c *constraint. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \c key_type, \c *policy and \c *constraint are incompatible. - * \c *policy is unchanged. - */ -static psa_status_t psa_restrict_key_policy( - psa_key_type_t key_type, - psa_key_policy_t *policy, - const psa_key_policy_t *constraint) -{ - psa_algorithm_t intersection_alg = - psa_key_policy_algorithm_intersection(key_type, policy->alg, - constraint->alg); - psa_algorithm_t intersection_alg2 = - psa_key_policy_algorithm_intersection(key_type, policy->alg2, - constraint->alg2); - if (intersection_alg == 0 && policy->alg != 0 && constraint->alg != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (intersection_alg2 == 0 && policy->alg2 != 0 && constraint->alg2 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - policy->usage &= constraint->usage; - policy->alg = intersection_alg; - policy->alg2 = intersection_alg2; - return PSA_SUCCESS; -} - -/** Get the description of a key given its identifier and policy constraints - * and lock it. - * - * The key must have allow all the usage flags set in \p usage. If \p alg is - * nonzero, the key must allow operations with this algorithm. If \p alg is - * zero, the algorithm is not checked. - * - * In case of a persistent key, the function loads the description of the key - * into a key slot if not already done. - * - * On success, the returned key slot is locked. It is the responsibility of - * the caller to unlock the key slot when it does not access it anymore. - */ -static psa_status_t psa_get_and_lock_key_slot_with_policy( - mbedtls_svc_key_id_t key, - psa_key_slot_t **p_slot, - psa_key_usage_t usage, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - - status = psa_get_and_lock_key_slot( key, p_slot, PSA_INTENT_READ ); - if( status != PSA_SUCCESS ) - return( status ); - slot = *p_slot; - - /* Enforce that usage policy for the key slot contains all the flags - * required by the usage parameter. There is one exception: public - * keys can always be exported, so we treat public key objects as - * if they had the export flag. */ - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type)) { - usage &= ~PSA_KEY_USAGE_EXPORT; - } - - if ((slot->attr.policy.usage & usage) != usage) { - status = PSA_ERROR_NOT_PERMITTED; - goto error; - } - - /* Enforce that the usage policy permits the requested algorithm. */ - if (alg != 0) { - status = psa_key_policy_permits(&slot->attr.policy, - slot->attr.type, - alg); - if (status != PSA_SUCCESS) { - goto error; - } - } - - return PSA_SUCCESS; - -error: - *p_slot = NULL; - psa_unlock_key_slot(slot); - - return status; -} - -/** Get a key slot containing a transparent key and lock it. - * - * A transparent key is a key for which the key material is directly - * available, as opposed to a key in a secure element and/or to be used - * by a secure element. - * - * This is a temporary function that may be used instead of - * psa_get_and_lock_key_slot_with_policy() when there is no opaque key support - * for a cryptographic operation. - * - * On success, the returned key slot is locked. It is the responsibility of the - * caller to unlock the key slot when it does not access it anymore. - */ -static psa_status_t psa_get_and_lock_transparent_key_slot_with_policy( - mbedtls_svc_key_id_t key, - psa_key_slot_t **p_slot, - psa_key_usage_t usage, - psa_algorithm_t alg) -{ - psa_status_t status = psa_get_and_lock_key_slot_with_policy(key, p_slot, - usage, alg); - if (status != PSA_SUCCESS) { - return status; - } - - if (psa_key_lifetime_is_external((*p_slot)->attr.lifetime)) { - psa_unlock_key_slot(*p_slot); - *p_slot = NULL; - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; -} - -psa_status_t psa_remove_key_data_from_memory(psa_key_slot_t *slot) -{ - if (slot->key.data != NULL) { - mbedtls_zeroize_and_free(slot->key.data, slot->key.bytes); - } - - slot->key.data = NULL; - slot->key.bytes = 0; - - return PSA_SUCCESS; -} - -/** Completely wipe a slot in memory, including its policy. - * Persistent storage is not affected. */ -psa_status_t psa_wipe_key_slot( psa_key_slot_t *slot ) -{ - psa_status_t status = psa_remove_key_data_from_memory( slot ); - - /* - * As the return error code may not be handled in case of multiple errors, - * do our best to report an unexpected state. Assert with - * MBEDTLS_TEST_HOOK_TEST_ASSERT that the state is as expected: - * if the MBEDTLS_TEST_HOOKS configuration option is enabled and the - * function is called as part of the execution of a test suite, the - * execution of the test suite is stopped in error if the assertion fails. - */ - - if( ( slot->state != PSA_STATE_WIPING && slot->state != PSA_STATE_DESTROYING ) || - slot->reader_count != 0 ) - { - MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->state == PSA_STATE_WIPING || - slot->state == PSA_STATE_DESTROYING ); - MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->reader_count == 0 ); - status = PSA_ERROR_CORRUPTION_DETECTED; - } - - /* Multipart operations may still be using the key. This is safe - * because all multipart operation objects are independent from - * the key slot: if they need to access the key after the setup - * phase, they have a copy of the key. Note that this means that - * key material can linger until all operations are completed. */ - /* At this point, key material and other type-specific content has - * been wiped. Clear remaining metadata. We can call memset and not - * zeroize because the metadata is not particularly sensitive. */ - memset(slot, 0, sizeof(*slot)); - return status; -} - -psa_status_t psa_finish_key_destruction( psa_key_slot_t *slot ) -{ - psa_status_t status; /* status of the last operation */ - psa_status_t overall_status = PSA_SUCCESS; -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - psa_se_drv_table_entry_t *driver; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - if( slot->state != PSA_STATE_DESTROYING ) - return( PSA_ERROR_BAD_STATE ); - - if (PSA_KEY_LIFETIME_IS_READ_ONLY(slot->attr.lifetime)) { - /* Refuse the destruction of a read-only key (which may or may not work - * if we attempt it, depending on whether the key is merely read-only - * by policy or actually physically read-only). - * Just do the best we can, which is to wipe the copy in memory - * (done in this function's cleanup code). */ - overall_status = PSA_ERROR_NOT_PERMITTED; - - status = psa_wipe_key_slot( slot ); - /* Prioritize CORRUPTION_DETECTED from wiping over a storage error */ - if( status != PSA_SUCCESS ) - overall_status = status; - - return( overall_status ); - } - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - driver = psa_get_se_driver_entry(slot->attr.lifetime); - if (driver != NULL) { - /* For a key in a secure element, we need to do three things: - * remove the key file in internal storage, destroy the - * key inside the secure element, and update the driver's - * persistent data. Start a transaction that will encompass these - * three actions. */ - psa_crypto_prepare_transaction(PSA_CRYPTO_TRANSACTION_DESTROY_KEY); - psa_crypto_transaction.key.lifetime = slot->attr.lifetime; - psa_crypto_transaction.key.slot = psa_key_slot_get_slot_number(slot); - psa_crypto_transaction.key.id = slot->attr.id; - status = psa_crypto_save_transaction(); - if (status != PSA_SUCCESS) { - (void) psa_crypto_stop_transaction(); - /* We should still try to destroy the key in the secure - * element and the key metadata in storage. This is especially - * important if the error is that the storage is full. - * But how to do it exactly without risking an inconsistent - * state after a reset? - * https://github.com/ARMmbed/mbed-crypto/issues/215 - */ - overall_status = status; - goto exit; - } - - status = psa_destroy_se_key(driver, - psa_key_slot_get_slot_number(slot)); - if (overall_status == PSA_SUCCESS) { - overall_status = status; - } - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if (!PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { - status = psa_destroy_persistent_key(slot->attr.id); - if (overall_status == PSA_SUCCESS) { - overall_status = status; - } - - /* TODO: other slots may have a copy of the same key. We should - * invalidate them. - * https://github.com/ARMmbed/mbed-crypto/issues/214 - */ - } -#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if (driver != NULL) { - status = psa_save_se_persistent_data(driver); - if (overall_status == PSA_SUCCESS) { - overall_status = status; - } - status = psa_crypto_stop_transaction(); - if (overall_status == PSA_SUCCESS) { - overall_status = status; - } - } -exit: -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - status = psa_wipe_key_slot( slot ); - /* Prioritize CORRUPTION_DETECTED from wiping over a storage error */ - if (status != PSA_SUCCESS) { - overall_status = status; - } - return overall_status; -} - -psa_status_t psa_destroy_key( mbedtls_svc_key_id_t key ) -{ - psa_key_slot_t *slot; - psa_status_t status; /* status of the last operation */ - - if( mbedtls_svc_key_id_is_null( key ) ) - return( PSA_SUCCESS ); - - /* - * Get the description of the key in a key slot. In case of a persistent - * key, this will load the key description from persistent memory if not - * done yet. We cannot avoid this loading as without it we don't know if - * the key is operated by an SE or not and this information is needed by - * the current implementation. - */ - status = psa_get_and_lock_key_slot( key, &slot, PSA_INTENT_DESTROY ); - if( status != PSA_SUCCESS ) - return( status ); - - if( psa_slot_has_no_readers( slot ) ) - { - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - status = psa_finish_key_destruction( slot ); - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - } - else - status = PSA_ERROR_DELAYED; - - return( status ); -} - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) -static psa_status_t psa_get_rsa_public_exponent( - const mbedtls_rsa_context *rsa, - psa_key_attributes_t *attributes) -{ - mbedtls_mpi mpi; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - uint8_t *buffer = NULL; - size_t buflen; - mbedtls_mpi_init(&mpi); - - ret = mbedtls_rsa_export(rsa, NULL, NULL, NULL, NULL, &mpi); - if (ret != 0) { - goto exit; - } - if (mbedtls_mpi_cmp_int(&mpi, 65537) == 0) { - /* It's the default value, which is reported as an empty string, - * so there's nothing to do. */ - goto exit; - } - - buflen = mbedtls_mpi_size(&mpi); - buffer = mbedtls_calloc(1, buflen); - if (buffer == NULL) { - ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; - goto exit; - } - ret = mbedtls_mpi_write_binary(&mpi, buffer, buflen); - if (ret != 0) { - goto exit; - } - attributes->domain_parameters = buffer; - attributes->domain_parameters_size = buflen; - -exit: - mbedtls_mpi_free(&mpi); - if (ret != 0) { - mbedtls_free(buffer); - } - return mbedtls_to_psa_error(ret); -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - -/** Retrieve all the publicly-accessible attributes of a key. - */ -psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, - psa_key_attributes_t *attributes) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - psa_reset_key_attributes(attributes); - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, 0, 0); - if (status != PSA_SUCCESS) { - return status; - } - - attributes->core = slot->attr; - attributes->core.flags &= (MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY | - MBEDTLS_PSA_KA_MASK_DUAL_USE); - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if (psa_get_se_driver_entry(slot->attr.lifetime) != NULL) { - psa_set_key_slot_number(attributes, - psa_key_slot_get_slot_number(slot)); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch (slot->attr.type) { -#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) - case PSA_KEY_TYPE_RSA_KEY_PAIR: - case PSA_KEY_TYPE_RSA_PUBLIC_KEY: - /* TODO: reporting the public exponent for opaque keys - * is not yet implemented. - * https://github.com/ARMmbed/mbed-crypto/issues/216 - */ - if (!psa_key_lifetime_is_external(slot->attr.lifetime)) { - mbedtls_rsa_context *rsa = NULL; - - status = mbedtls_psa_rsa_load_representation( - slot->attr.type, - slot->key.data, - slot->key.bytes, - &rsa); - if (status != PSA_SUCCESS) { - break; - } - - status = psa_get_rsa_public_exponent(rsa, - attributes); - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - } - break; -#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - default: - /* Nothing else to do. */ - break; - } - - if (status != PSA_SUCCESS) { - psa_reset_key_attributes(attributes); - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -psa_status_t psa_get_key_slot_number( - const psa_key_attributes_t *attributes, - psa_key_slot_number_t *slot_number) -{ - if (attributes->core.flags & MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER) { - *slot_number = attributes->slot_number; - return PSA_SUCCESS; - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } -} -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -static psa_status_t psa_export_key_buffer_internal(const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - if (key_buffer_size > data_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - memcpy(data, key_buffer, key_buffer_size); - memset(data + key_buffer_size, 0, - data_size - key_buffer_size); - *data_length = key_buffer_size; - return PSA_SUCCESS; -} - -psa_status_t psa_export_key_internal( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length) -{ - psa_key_type_t type = attributes->core.type; - - if (key_type_is_raw_bytes(type) || - PSA_KEY_TYPE_IS_RSA(type) || - PSA_KEY_TYPE_IS_ECC(type) || - PSA_KEY_TYPE_IS_DH(type)) { - return psa_export_key_buffer_internal( - key_buffer, key_buffer_size, - data, data_size, data_length); - } else { - /* This shouldn't happen in the reference implementation, but - it is valid for a special-purpose implementation to omit - support for exporting certain key types. */ - return PSA_ERROR_NOT_SUPPORTED; - } -} - -psa_status_t psa_export_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - /* Reject a zero-length output buffer now, since this can never be a - * valid key representation. This way we know that data must be a valid - * pointer and we can do things like memset(data, ..., data_size). */ - if (data_size == 0) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - /* Set the key to empty now, so that even when there are errors, we always - * set data_length to a value between 0 and data_size. On error, setting - * the key to empty is a good choice because an empty key representation is - * unlikely to be accepted anywhere. */ - *data_length = 0; - - /* Export requires the EXPORT flag. There is an exception for public keys, - * which don't require any flag, but - * psa_get_and_lock_key_slot_with_policy() takes care of this. - */ - status = psa_get_and_lock_key_slot_with_policy(key, &slot, - PSA_KEY_USAGE_EXPORT, 0); - if (status != PSA_SUCCESS) { - return status; - } - - psa_key_attributes_t attributes = { - .core = slot->attr - }; - status = psa_driver_wrapper_export_key(&attributes, - slot->key.data, slot->key.bytes, - data, data_size, data_length); - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_export_public_key_internal( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - psa_key_type_t type = attributes->core.type; - - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type) && - (PSA_KEY_TYPE_IS_RSA(type) || PSA_KEY_TYPE_IS_ECC(type) || - PSA_KEY_TYPE_IS_DH(type))) { - /* Exporting public -> public */ - return psa_export_key_buffer_internal( - key_buffer, key_buffer_size, - data, data_size, data_length); - } else if (PSA_KEY_TYPE_IS_RSA(type)) { -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) - return mbedtls_psa_rsa_export_public_key(attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length); -#else - /* We don't know how to convert a private RSA key to public. */ - return PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - } else if (PSA_KEY_TYPE_IS_ECC(type)) { -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) - return mbedtls_psa_ecp_export_public_key(attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length); -#else - /* We don't know how to convert a private ECC key to public */ - return PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ - } else if (PSA_KEY_TYPE_IS_DH(type)) { -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) - return mbedtls_psa_ffdh_export_public_key(attributes, - key_buffer, - key_buffer_size, - data, data_size, - data_length); -#else - return PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) */ - } else { - (void) key_buffer; - (void) key_buffer_size; - (void) data; - (void) data_size; - (void) data_length; - return PSA_ERROR_NOT_SUPPORTED; - } -} - -psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - psa_key_attributes_t attributes; - - /* Reject a zero-length output buffer now, since this can never be a - * valid key representation. This way we know that data must be a valid - * pointer and we can do things like memset(data, ..., data_size). */ - if (data_size == 0) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - /* Set the key to empty now, so that even when there are errors, we always - * set data_length to a value between 0 and data_size. On error, setting - * the key to empty is a good choice because an empty key representation is - * unlikely to be accepted anywhere. */ - *data_length = 0; - - /* Exporting a public key doesn't require a usage flag. */ - status = psa_get_and_lock_key_slot_with_policy(key, &slot, 0, 0); - if (status != PSA_SUCCESS) { - return status; - } - - if (!PSA_KEY_TYPE_IS_ASYMMETRIC(slot->attr.type)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - status = psa_driver_wrapper_export_public_key( - &attributes, slot->key.data, slot->key.bytes, - data, data_size, data_length); - -exit: - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -MBEDTLS_STATIC_ASSERT( - (MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_DUAL_USE) == 0, - "One or more key attribute flag is listed as both external-only and dual-use") -MBEDTLS_STATIC_ASSERT( - (PSA_KA_MASK_INTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_DUAL_USE) == 0, - "One or more key attribute flag is listed as both internal-only and dual-use") -MBEDTLS_STATIC_ASSERT( - (PSA_KA_MASK_INTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY) == 0, - "One or more key attribute flag is listed as both internal-only and external-only") - -/** Validate that a key policy is internally well-formed. - * - * This function only rejects invalid policies. It does not validate the - * consistency of the policy with respect to other attributes of the key - * such as the key type. - */ -static psa_status_t psa_validate_key_policy(const psa_key_policy_t *policy) -{ - if ((policy->usage & ~(PSA_KEY_USAGE_EXPORT | - PSA_KEY_USAGE_COPY | - PSA_KEY_USAGE_ENCRYPT | - PSA_KEY_USAGE_DECRYPT | - PSA_KEY_USAGE_SIGN_MESSAGE | - PSA_KEY_USAGE_VERIFY_MESSAGE | - PSA_KEY_USAGE_SIGN_HASH | - PSA_KEY_USAGE_VERIFY_HASH | - PSA_KEY_USAGE_VERIFY_DERIVATION | - PSA_KEY_USAGE_DERIVE)) != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -/** Validate the internal consistency of key attributes. - * - * This function only rejects invalid attribute values. If does not - * validate the consistency of the attributes with any key data that may - * be involved in the creation of the key. - * - * Call this function early in the key creation process. - * - * \param[in] attributes Key attributes for the new key. - * \param[out] p_drv On any return, the driver for the key, if any. - * NULL for a transparent key. - * - */ -static psa_status_t psa_validate_key_attributes( - const psa_key_attributes_t *attributes, - psa_se_drv_table_entry_t **p_drv) -{ - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - psa_key_lifetime_t lifetime = psa_get_key_lifetime(attributes); - mbedtls_svc_key_id_t key = psa_get_key_id(attributes); - - status = psa_validate_key_location(lifetime, p_drv); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_validate_key_persistence(lifetime); - if (status != PSA_SUCCESS) { - return status; - } - - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { - if (MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key) != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } else { - if (!psa_is_valid_key_id(psa_get_key_id(attributes), 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - status = psa_validate_key_policy(&attributes->core.policy); - if (status != PSA_SUCCESS) { - return status; - } - - /* Refuse to create overly large keys. - * Note that this doesn't trigger on import if the attributes don't - * explicitly specify a size (so psa_get_key_bits returns 0), so - * psa_import_key() needs its own checks. */ - if (psa_get_key_bits(attributes) > PSA_MAX_KEY_BITS) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* Reject invalid flags. These should not be reachable through the API. */ - if (attributes->core.flags & ~(MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY | - MBEDTLS_PSA_KA_MASK_DUAL_USE)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -/** Prepare a key slot to receive key material. - * - * This function allocates a key slot and sets its metadata. - * - * If this function fails, call psa_fail_key_creation(). - * - * This function is intended to be used as follows: - * -# Call psa_start_key_creation() to allocate a key slot, prepare - * it with the specified attributes, and in case of a volatile key assign it - * a volatile key identifier. - * -# Populate the slot with the key material. - * -# Call psa_finish_key_creation() to finalize the creation of the slot. - * In case of failure at any step, stop the sequence and call - * psa_fail_key_creation(). - * - * On success, the key slot is locked. It is the responsibility of the caller - * to unlock the key slot when it does not access it anymore. - * - * \param method An identification of the calling function. - * \param[in] attributes Key attributes for the new key. - * \param[out] p_slot On success, a pointer to the prepared slot. - * \param[out] p_drv On any return, the driver for the key, if any. - * NULL for a transparent key. - * - * \retval #PSA_SUCCESS - * The key slot is ready to receive key material. - * \return If this function fails, the key slot is an invalid state. - * You must call psa_fail_key_creation() to wipe and free the slot. - */ -static psa_status_t psa_start_key_creation( - psa_key_creation_method_t method, - const psa_key_attributes_t *attributes, - psa_key_slot_t **p_slot, - psa_se_drv_table_entry_t **p_drv) -{ - psa_status_t status; - psa_key_id_t volatile_key_id; - psa_key_slot_t *slot; - - (void) method; - *p_drv = NULL; - - status = psa_validate_key_attributes(attributes, p_drv); - if (status != PSA_SUCCESS) { - return status; - } - - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - slot = *p_slot; - - /* We're storing the declared bit-size of the key. It's up to each - * creation mechanism to verify that this information is correct. - * It's automatically correct for mechanisms that use the bit-size as - * an input (generate, device) but not for those where the bit-size - * is optional (import, copy). In case of a volatile key, assign it the - * volatile key identifier associated to the slot returned to contain its - * definition. */ - - slot->attr = attributes->core; - if (PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - slot->attr.id = volatile_key_id; -#else - slot->attr.id.key_id = volatile_key_id; -#endif - } - - /* Erase external-only flags from the internal copy. To access - * external-only flags, query `attributes`. Thanks to the check - * in psa_validate_key_attributes(), this leaves the dual-use - * flags and any internal flag that psa_get_empty_key_slot() - * may have set. */ - slot->attr.flags &= ~MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY; - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* For a key in a secure element, we need to do three things - * when creating or registering a persistent key: - * create the key file in internal storage, create the - * key inside the secure element, and update the driver's - * persistent data. This is done by starting a transaction that will - * encompass these three actions. - * For registering a volatile key, we just need to find an appropriate - * slot number inside the SE. Since the key is designated volatile, creating - * a transaction is not required. */ - /* The first thing to do is to find a slot number for the new key. - * We save the slot number in persistent storage as part of the - * transaction data. It will be needed to recover if the power - * fails during the key creation process, to clean up on the secure - * element side after restarting. Obtaining a slot number from the - * secure element driver updates its persistent state, but we do not yet - * save the driver's persistent state, so that if the power fails, - * we can roll back to a state where the key doesn't exist. */ - if (*p_drv != NULL) { - psa_key_slot_number_t slot_number; - status = psa_find_se_slot_for_key( attributes, method, *p_drv, - &slot_number ); - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - if (!PSA_KEY_LIFETIME_IS_VOLATILE(attributes->core.lifetime)) { - psa_crypto_prepare_transaction(PSA_CRYPTO_TRANSACTION_CREATE_KEY); - psa_crypto_transaction.key.lifetime = slot->attr.lifetime; - psa_crypto_transaction.key.slot = slot_number; - psa_crypto_transaction.key.id = slot->attr.id; - status = psa_crypto_save_transaction( ); - if( status != PSA_SUCCESS ) - { - (void) psa_crypto_stop_transaction( ); - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - } - - status = psa_copy_key_material_into_slot( - slot, (uint8_t *) (&slot_number), sizeof(slot_number)); - } - - if (*p_drv == NULL && method == PSA_KEY_CREATION_REGISTER) { - /* Key registration only makes sense with a secure element. */ - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_ERROR_INVALID_ARGUMENT ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - psa_slot_change_state( slot, PSA_STATE_CREATING ); - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_SUCCESS ); -} - -/** Finalize the creation of a key once its key material has been set. - * - * This entails writing the key to persistent storage. - * - * If this function fails, call psa_fail_key_creation(). - * See the documentation of psa_start_key_creation() for the intended use - * of this function. - * - * If the finalization succeeds, the function unlocks the key slot (it was - * locked by psa_start_key_creation()) and the key slot cannot be accessed - * anymore as part of the key creation process. - * - * \param[in,out] slot Pointer to the slot with key material. - * \param[in] driver The secure element driver for the key, - * or NULL for a transparent key. - * \param[out] key On success, identifier of the key. Note that the - * key identifier is also stored in the key slot. - * - * \retval #PSA_SUCCESS - * The key was successfully created. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * - * \return If this function fails, the key slot is an invalid state. - * You must call psa_fail_key_creation() to wipe and free the slot. - */ -static psa_status_t psa_finish_key_creation( - psa_key_slot_t *slot, - psa_se_drv_table_entry_t *driver, - mbedtls_svc_key_id_t *key) -{ - psa_status_t status = PSA_SUCCESS; - (void) slot; - (void) driver; - - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if (!PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if (driver != NULL) { - psa_se_key_data_storage_t data; - psa_key_slot_number_t slot_number = - psa_key_slot_get_slot_number(slot); - - MBEDTLS_STATIC_ASSERT(sizeof(slot_number) == - sizeof(data.slot_number), - "Slot number size does not match psa_se_key_data_storage_t"); - - memcpy(&data.slot_number, &slot_number, sizeof(slot_number)); - status = psa_save_persistent_key(&slot->attr, - (uint8_t *) &data, - sizeof(data)); - } else -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - { - /* Key material is saved in export representation in the slot, so - * just pass the slot buffer for storage. */ - status = psa_save_persistent_key(&slot->attr, - slot->key.data, - slot->key.bytes); - } - } - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } -#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* Finish the transaction for a key creation. This does not - * happen when registering an existing key. Detect this case - * by checking whether a transaction is in progress (actual - * creation of a persistent key in a secure element requires a transaction, - * but registration or volatile key creation doesn't use one). */ - if( driver != NULL && - psa_crypto_transaction.unknown.type == PSA_CRYPTO_TRANSACTION_CREATE_KEY ) - { - status = psa_save_se_persistent_data( driver ); - if( status != PSA_SUCCESS ) - { - psa_destroy_persistent_key( slot->attr.id ); - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - status = psa_crypto_stop_transaction(); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - if (status == PSA_SUCCESS) { - *key = slot->attr.id; - status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); - if( status != PSA_SUCCESS ) { - *key = MBEDTLS_SVC_KEY_ID_INIT; - } - } - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); -} - -/** Abort the creation of a key. - * - * You may call this function after calling psa_start_key_creation(), - * or after psa_finish_key_creation() fails. In other circumstances, this - * function may not clean up persistent storage. - * See the documentation of psa_start_key_creation() for the intended use - * of this function. - * - * \param[in,out] slot Pointer to the slot with key material. - * \param[in] driver The secure element driver for the key, - * or NULL for a transparent key. - */ -static void psa_fail_key_creation(psa_key_slot_t *slot, - psa_se_drv_table_entry_t *driver) -{ - (void) driver; - - if (slot == NULL) { - return; - } - -#if defined(MBEDTLS_THREADING_C) - (void) mbedtls_mutex_lock( &mbedtls_psa_slots_mutex ); -#endif - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* TODO: If the key has already been created in the secure - * element, and the failure happened later (when saving metadata - * to internal storage), we need to destroy the key in the secure - * element. - * https://github.com/ARMmbed/mbed-crypto/issues/217 - */ - - /* Abort the ongoing transaction if any (there may not be one if - * the creation process failed before starting one, or if the - * key creation is a registration of a key in a secure element). - * Earlier functions must already have done what it takes to undo any - * partial creation. All that's left is to update the transaction data - * itself. */ - (void) psa_crypto_stop_transaction(); -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - (void) psa_slot_change_state( slot, PSA_STATE_WIPING ); - (void) psa_wipe_key_slot( slot ); -#if defined(MBEDTLS_THREADING_C) - (void) mbedtls_mutex_unlock( &mbedtls_psa_slots_mutex ); -#endif -} - -/** Validate optional attributes during key creation. - * - * Some key attributes are optional during key creation. If they are - * specified in the attributes structure, check that they are consistent - * with the data in the slot. - * - * This function should be called near the end of key creation, after - * the slot in memory is fully populated but before saving persistent data. - */ -static psa_status_t psa_validate_optional_attributes( - const psa_key_slot_t *slot, - const psa_key_attributes_t *attributes) -{ - if (attributes->core.type != 0) { - if (attributes->core.type != slot->attr.type) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - if (attributes->domain_parameters_size != 0) { -#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) - if (PSA_KEY_TYPE_IS_RSA(slot->attr.type)) { - mbedtls_rsa_context *rsa = NULL; - mbedtls_mpi actual, required; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - psa_status_t status = mbedtls_psa_rsa_load_representation( - slot->attr.type, - slot->key.data, - slot->key.bytes, - &rsa); - if (status != PSA_SUCCESS) { - return status; - } - - mbedtls_mpi_init(&actual); - mbedtls_mpi_init(&required); - ret = mbedtls_rsa_export(rsa, - NULL, NULL, NULL, NULL, &actual); - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - if (ret != 0) { - goto rsa_exit; - } - ret = mbedtls_mpi_read_binary(&required, - attributes->domain_parameters, - attributes->domain_parameters_size); - if (ret != 0) { - goto rsa_exit; - } - if (mbedtls_mpi_cmp_mpi(&actual, &required) != 0) { - ret = MBEDTLS_ERR_RSA_BAD_INPUT_DATA; - } -rsa_exit: - mbedtls_mpi_free(&actual); - mbedtls_mpi_free(&required); - if (ret != 0) { - return mbedtls_to_psa_error(ret); - } - } else -#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - if (attributes->core.bits != 0) { - if (attributes->core.bits != slot->attr.bits) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - return PSA_SUCCESS; -} - -psa_status_t psa_import_key(const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - mbedtls_svc_key_id_t *key) -{ - psa_status_t status; - psa_key_slot_t *slot = NULL; - psa_se_drv_table_entry_t *driver = NULL; - size_t bits; - size_t storage_size = data_length; - - *key = MBEDTLS_SVC_KEY_ID_INIT; - - /* Reject zero-length symmetric keys (including raw data key objects). - * This also rejects any key which might be encoded as an empty string, - * which is never valid. */ - if (data_length == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* Ensure that the bytes-to-bits conversion cannot overflow. */ - if (data_length > SIZE_MAX / 8) { - return PSA_ERROR_NOT_SUPPORTED; - } - - status = psa_start_key_creation(PSA_KEY_CREATION_IMPORT, attributes, - &slot, &driver); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* In the case of a transparent key or an opaque key stored in local - * storage ( thus not in the case of importing a key in a secure element - * with storage ( MBEDTLS_PSA_CRYPTO_SE_C ) ),we have to allocate a - * buffer to hold the imported key material. */ - if (slot->key.data == NULL) { - if (psa_key_lifetime_is_external(attributes->core.lifetime)) { - status = psa_driver_wrapper_get_key_buffer_size_from_key_data( - attributes, data, data_length, &storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - } - status = psa_allocate_buffer_to_slot(slot, storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - bits = slot->attr.bits; - status = psa_driver_wrapper_import_key(attributes, - data, data_length, - slot->key.data, - slot->key.bytes, - &slot->key.bytes, &bits); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (slot->attr.bits == 0) { - slot->attr.bits = (psa_key_bits_t) bits; - } else if (bits != slot->attr.bits) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - /* Enforce a size limit, and in particular ensure that the bit - * size fits in its representation type.*/ - if (bits > PSA_MAX_KEY_BITS) { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = psa_validate_optional_attributes(slot, attributes); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_finish_key_creation(slot, driver, key); -exit: - if (status != PSA_SUCCESS) { - psa_fail_key_creation(slot, driver); - } - - return status; -} - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -psa_status_t mbedtls_psa_register_se_key( - const psa_key_attributes_t *attributes) -{ - psa_status_t status; - psa_key_slot_t *slot = NULL; - psa_se_drv_table_entry_t *driver = NULL; - mbedtls_svc_key_id_t key = MBEDTLS_SVC_KEY_ID_INIT; - - /* Leaving attributes unspecified is not currently supported. - * It could make sense to query the key type and size from the - * secure element, but not all secure elements support this - * and the driver HAL doesn't currently support it. */ - if (psa_get_key_type(attributes) == PSA_KEY_TYPE_NONE) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (psa_get_key_bits(attributes) == 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - - status = psa_start_key_creation(PSA_KEY_CREATION_REGISTER, attributes, - &slot, &driver); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_finish_key_creation(slot, driver, &key); - -exit: - if (status != PSA_SUCCESS) { - psa_fail_key_creation(slot, driver); - } - - /* Registration doesn't keep the key in RAM. */ - psa_close_key(key); - return status; -} -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, - const psa_key_attributes_t *specified_attributes, - mbedtls_svc_key_id_t *target_key) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *source_slot = NULL; - psa_key_slot_t *target_slot = NULL; - psa_key_attributes_t actual_attributes = *specified_attributes; - psa_se_drv_table_entry_t *driver = NULL; - size_t storage_size = 0; - bool source_key_is_unconditionally_copyable = false; - - *target_key = MBEDTLS_SVC_KEY_ID_INIT; - - status = psa_get_and_lock_key_slot_with_policy( - source_key, &source_slot, 0, 0); - if (status != PSA_SUCCESS) { - goto exit; - } - - source_key_is_unconditionally_copyable = - sli_psa_key_is_unconditionally_copyable(source_slot->attr.id); - - if (!source_key_is_unconditionally_copyable && - ((source_slot->attr.policy.usage & PSA_KEY_USAGE_COPY) - != PSA_KEY_USAGE_COPY)) { - status = PSA_ERROR_NOT_PERMITTED; - goto exit; - } - - status = psa_validate_optional_attributes(source_slot, - specified_attributes); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* The target key type and number of bits have been validated by - * psa_validate_optional_attributes() to be either equal to zero or - * equal to the ones of the source key. So it is safe to inherit - * them from the source key now." - * */ - actual_attributes.core.bits = source_slot->attr.bits; - actual_attributes.core.type = source_slot->attr.type; - - - status = psa_restrict_key_policy(source_slot->attr.type, - &actual_attributes.core.policy, - &source_slot->attr.policy); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_start_key_creation(PSA_KEY_CREATION_COPY, &actual_attributes, - &target_slot, &driver); - if (status != PSA_SUCCESS) { - goto exit; - } - if (!source_key_is_unconditionally_copyable && - PSA_KEY_LIFETIME_GET_LOCATION(target_slot->attr.lifetime) != - PSA_KEY_LIFETIME_GET_LOCATION(source_slot->attr.lifetime)) { - /* - * If the source and target keys are stored in different locations, - * the source key would need to be exported as plaintext and re-imported - * in the other location. This has security implications which have not - * been fully mapped. For now, this can be achieved through - * appropriate API invocations from the application, if needed. - * */ - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - /* - * When the source and target keys are within the same location, - * - For transparent keys it is a blind copy without any driver invocation, - * - For opaque keys this translates to an invocation of the drivers' - * copy_key entry point through the dispatch layer. - * */ - if (psa_key_lifetime_is_external(actual_attributes.core.lifetime)) { - status = psa_driver_wrapper_get_key_buffer_size(&actual_attributes, - &storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_allocate_buffer_to_slot(target_slot, storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (psa_key_lifetime_is_external(source_slot->attr.lifetime)) { - // Silicon Labs's opaque driver for key copying is only able to - // import transparent keys. - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - status = psa_driver_wrapper_copy_key(&actual_attributes, - source_slot->key.data, - source_slot->key.bytes, - target_slot->key.data, - target_slot->key.bytes, - &target_slot->key.bytes); - if (status != PSA_SUCCESS) { - goto exit; - } - } else if (source_key_is_unconditionally_copyable && - psa_key_lifetime_is_external(source_slot->attr.lifetime)) { - /* We can't copy from an opaque key into a transparent one. */ - status = PSA_ERROR_NOT_PERMITTED; - goto exit; - } else { - status = psa_copy_key_material_into_slot(target_slot, - source_slot->key.data, - source_slot->key.bytes); - if (status != PSA_SUCCESS) { - goto exit; - } - } - status = psa_finish_key_creation(target_slot, driver, target_key); -exit: - if (status != PSA_SUCCESS) { - psa_fail_key_creation(target_slot, driver); - } - - unlock_status = psa_unlock_key_slot(source_slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - - - -/****************************************************************/ -/* Message digests */ -/****************************************************************/ - -psa_status_t psa_hash_abort(psa_hash_operation_t *operation) -{ - /* Aborting a non-active operation is allowed */ - if (operation->id == 0) { - return PSA_SUCCESS; - } - - psa_status_t status = psa_driver_wrapper_hash_abort(operation); - operation->id = 0; - - return status; -} - -psa_status_t psa_hash_setup(psa_hash_operation_t *operation, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* A context must be freshly initialized before it can be set up. */ - if (operation->id != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (!PSA_ALG_IS_HASH(alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - /* Ensure all of the context is zeroized, since PSA_HASH_OPERATION_INIT only - * directly zeroes the int-sized dummy member of the context union. */ - memset(&operation->ctx, 0, sizeof(operation->ctx)); - - status = psa_driver_wrapper_hash_setup(operation, alg); - -exit: - if (status != PSA_SUCCESS) { - psa_hash_abort(operation); - } - - return status; -} - -psa_status_t psa_hash_update(psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - /* Don't require hash implementations to behave correctly on a - * zero-length input, which may have an invalid pointer. */ - if (input_length == 0) { - return PSA_SUCCESS; - } - - status = psa_driver_wrapper_hash_update(operation, input, input_length); - -exit: - if (status != PSA_SUCCESS) { - psa_hash_abort(operation); - } - - return status; -} - -psa_status_t psa_hash_finish(psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ - *hash_length = 0; - if (operation->id == 0) { - return PSA_ERROR_BAD_STATE; - } - - psa_status_t status = psa_driver_wrapper_hash_finish( - operation, hash, hash_size, hash_length); - psa_hash_abort(operation); - return status; -} - -psa_status_t psa_hash_verify(psa_hash_operation_t *operation, - const uint8_t *hash, - size_t hash_length) -{ - uint8_t actual_hash[PSA_HASH_MAX_SIZE]; - size_t actual_hash_length; - psa_status_t status = psa_hash_finish( - operation, - actual_hash, sizeof(actual_hash), - &actual_hash_length); - - if (status != PSA_SUCCESS) { - goto exit; - } - - if (actual_hash_length != hash_length) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - - if (mbedtls_ct_memcmp(hash, actual_hash, actual_hash_length) != 0) { - status = PSA_ERROR_INVALID_SIGNATURE; - } - -exit: - mbedtls_platform_zeroize(actual_hash, sizeof(actual_hash)); - if (status != PSA_SUCCESS) { - psa_hash_abort(operation); - } - - return status; -} - -psa_status_t psa_hash_compute(psa_algorithm_t alg, - const uint8_t *input, size_t input_length, - uint8_t *hash, size_t hash_size, - size_t *hash_length) -{ - *hash_length = 0; - if (!PSA_ALG_IS_HASH(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return psa_driver_wrapper_hash_compute(alg, input, input_length, - hash, hash_size, hash_length); -} - -psa_status_t psa_hash_compare(psa_algorithm_t alg, - const uint8_t *input, size_t input_length, - const uint8_t *hash, size_t hash_length) -{ - uint8_t actual_hash[PSA_HASH_MAX_SIZE]; - size_t actual_hash_length; - - if (!PSA_ALG_IS_HASH(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_status_t status = psa_driver_wrapper_hash_compute( - alg, input, input_length, - actual_hash, sizeof(actual_hash), - &actual_hash_length); - if (status != PSA_SUCCESS) { - goto exit; - } - if (actual_hash_length != hash_length) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - if (mbedtls_ct_memcmp(hash, actual_hash, actual_hash_length) != 0) { - status = PSA_ERROR_INVALID_SIGNATURE; - } - -exit: - mbedtls_platform_zeroize(actual_hash, sizeof(actual_hash)); - return status; -} - -psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, - psa_hash_operation_t *target_operation) -{ - if (source_operation->id == 0 || - target_operation->id != 0) { - return PSA_ERROR_BAD_STATE; - } - - psa_status_t status = psa_driver_wrapper_hash_clone(source_operation, - target_operation); - if (status != PSA_SUCCESS) { - psa_hash_abort(target_operation); - } - - return status; -} - - -/****************************************************************/ -/* MAC */ -/****************************************************************/ - -psa_status_t psa_mac_abort(psa_mac_operation_t *operation) -{ - /* Aborting a non-active operation is allowed */ - if (operation->id == 0) { - return PSA_SUCCESS; - } - - psa_status_t status = psa_driver_wrapper_mac_abort(operation); - operation->mac_size = 0; - operation->is_sign = 0; - operation->id = 0; - - return status; -} - -static psa_status_t psa_mac_finalize_alg_and_key_validation( - psa_algorithm_t alg, - const psa_key_attributes_t *attributes, - uint8_t *mac_size) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_type_t key_type = psa_get_key_type(attributes); - size_t key_bits = psa_get_key_bits(attributes); - - if (!PSA_ALG_IS_MAC(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* Validate the combination of key type and algorithm */ - status = psa_mac_key_can_do(alg, key_type); - if (status != PSA_SUCCESS) { - return status; - } - - /* Get the output length for the algorithm and key combination */ - *mac_size = PSA_MAC_LENGTH(key_type, key_bits, alg); - - if (*mac_size < 4) { - /* A very short MAC is too short for security since it can be - * brute-forced. Ancient protocols with 32-bit MACs do exist, - * so we make this our minimum, even though 32 bits is still - * too small for security. */ - return PSA_ERROR_NOT_SUPPORTED; - } - - if (*mac_size > PSA_MAC_LENGTH(key_type, key_bits, - PSA_ALG_FULL_LENGTH_MAC(alg))) { - /* It's impossible to "truncate" to a larger length than the full length - * of the algorithm. */ - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (*mac_size > PSA_MAC_MAX_SIZE) { - /* PSA_MAC_LENGTH returns the correct length even for a MAC algorithm - * that is disabled in the compile-time configuration. The result can - * therefore be larger than PSA_MAC_MAX_SIZE, which does take the - * configuration into account. In this case, force a return of - * PSA_ERROR_NOT_SUPPORTED here. Otherwise psa_mac_verify(), or - * psa_mac_compute(mac_size=PSA_MAC_MAX_SIZE), would return - * PSA_ERROR_BUFFER_TOO_SMALL for an unsupported algorithm whose MAC size - * is larger than PSA_MAC_MAX_SIZE, which is misleading and which breaks - * systematically generated tests. */ - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; -} - -static psa_status_t psa_mac_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - int is_sign) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - psa_key_attributes_t attributes; - - /* A context must be freshly initialized before it can be set up. */ - if (operation->id != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_get_and_lock_key_slot_with_policy( - key, - &slot, - is_sign ? PSA_KEY_USAGE_SIGN_MESSAGE : PSA_KEY_USAGE_VERIFY_MESSAGE, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - status = psa_mac_finalize_alg_and_key_validation(alg, &attributes, - &operation->mac_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - operation->is_sign = is_sign; - /* Dispatch the MAC setup call with validated input */ - if (is_sign) { - status = psa_driver_wrapper_mac_sign_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } else { - status = psa_driver_wrapper_mac_verify_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } - -exit: - if (status != PSA_SUCCESS) { - psa_mac_abort(operation); - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_mac_setup(operation, key, alg, 1); -} - -psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_mac_setup(operation, key, alg, 0); -} - -psa_status_t psa_mac_update(psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - if (operation->id == 0) { - return PSA_ERROR_BAD_STATE; - } - - /* Don't require hash implementations to behave correctly on a - * zero-length input, which may have an invalid pointer. */ - if (input_length == 0) { - return PSA_SUCCESS; - } - - psa_status_t status = psa_driver_wrapper_mac_update(operation, - input, input_length); - if (status != PSA_SUCCESS) { - psa_mac_abort(operation); - } - - return status; -} - -psa_status_t psa_mac_sign_finish(psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (!operation->is_sign) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - /* Sanity check. This will guarantee that mac_size != 0 (and so mac != NULL) - * once all the error checks are done. */ - if (operation->mac_size == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (mac_size < operation->mac_size) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_driver_wrapper_mac_sign_finish(operation, - mac, operation->mac_size, - mac_length); - -exit: - /* In case of success, set the potential excess room in the output buffer - * to an invalid value, to avoid potentially leaking a longer MAC. - * In case of error, set the output length and content to a safe default, - * such that in case the caller misses an error check, the output would be - * an unachievable MAC. - */ - if (status != PSA_SUCCESS) { - *mac_length = mac_size; - operation->mac_size = 0; - } - - psa_wipe_tag_output_buffer(mac, status, mac_size, *mac_length); - - abort_status = psa_mac_abort(operation); - - return status == PSA_SUCCESS ? abort_status : status; -} - -psa_status_t psa_mac_verify_finish(psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->is_sign) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->mac_size != mac_length) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - - status = psa_driver_wrapper_mac_verify_finish(operation, - mac, mac_length); - -exit: - abort_status = psa_mac_abort(operation); - - return status == PSA_SUCCESS ? abort_status : status; -} - -static psa_status_t psa_mac_compute_internal(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length, - int is_sign) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - uint8_t operation_mac_size = 0; - psa_key_attributes_t attributes; - - status = psa_get_and_lock_key_slot_with_policy( - key, - &slot, - is_sign ? PSA_KEY_USAGE_SIGN_MESSAGE : PSA_KEY_USAGE_VERIFY_MESSAGE, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - status = psa_mac_finalize_alg_and_key_validation(alg, &attributes, - &operation_mac_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (mac_size < operation_mac_size) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_driver_wrapper_mac_compute( - &attributes, - slot->key.data, slot->key.bytes, - alg, - input, input_length, - mac, operation_mac_size, mac_length); - -exit: - /* In case of success, set the potential excess room in the output buffer - * to an invalid value, to avoid potentially leaking a longer MAC. - * In case of error, set the output length and content to a safe default, - * such that in case the caller misses an error check, the output would be - * an unachievable MAC. - */ - if (status != PSA_SUCCESS) { - *mac_length = mac_size; - operation_mac_size = 0; - } - - psa_wipe_tag_output_buffer(mac, status, mac_size, *mac_length); - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ - return psa_mac_compute_internal(key, alg, - input, input_length, - mac, mac_size, mac_length, 1); -} - -psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *mac, - size_t mac_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t actual_mac[PSA_MAC_MAX_SIZE]; - size_t actual_mac_length; - - status = psa_mac_compute_internal(key, alg, - input, input_length, - actual_mac, sizeof(actual_mac), - &actual_mac_length, 0); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (mac_length != actual_mac_length) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - if (mbedtls_ct_memcmp(mac, actual_mac, actual_mac_length) != 0) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - -exit: - mbedtls_platform_zeroize(actual_mac, sizeof(actual_mac)); - - return status; -} - -/****************************************************************/ -/* Asymmetric cryptography */ -/****************************************************************/ - -static psa_status_t psa_sign_verify_check_alg(int input_is_message, - psa_algorithm_t alg) -{ - if (input_is_message) { - if (!PSA_ALG_IS_SIGN_MESSAGE(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (PSA_ALG_IS_SIGN_HASH(alg)) { - if (!PSA_ALG_IS_HASH(PSA_ALG_SIGN_GET_HASH(alg))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - } else { - if (!PSA_ALG_IS_SIGN_HASH(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - return PSA_SUCCESS; -} - -static psa_status_t psa_sign_internal(mbedtls_svc_key_id_t key, - int input_is_message, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - psa_key_attributes_t attributes; - - *signature_length = 0; - - status = psa_sign_verify_check_alg(input_is_message, alg); - if (status != PSA_SUCCESS) { - return status; - } - - /* Immediately reject a zero-length signature buffer. This guarantees - * that signature must be a valid pointer. (On the other hand, the input - * buffer can in principle be empty since it doesn't actually have - * to be a hash.) */ - if (signature_size == 0) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = psa_get_and_lock_key_slot_with_policy( - key, &slot, - input_is_message ? PSA_KEY_USAGE_SIGN_MESSAGE : - PSA_KEY_USAGE_SIGN_HASH, - alg); - - if (status != PSA_SUCCESS) { - goto exit; - } - - if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - if (input_is_message) { - status = psa_driver_wrapper_sign_message( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, - signature, signature_size, signature_length); - } else { - - status = psa_driver_wrapper_sign_hash( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, - signature, signature_size, signature_length); - } - - -exit: - psa_wipe_tag_output_buffer(signature, status, signature_size, - *signature_length); - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -static psa_status_t psa_verify_internal(mbedtls_svc_key_id_t key, - int input_is_message, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - status = psa_sign_verify_check_alg(input_is_message, alg); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_get_and_lock_key_slot_with_policy( - key, &slot, - input_is_message ? PSA_KEY_USAGE_VERIFY_MESSAGE : - PSA_KEY_USAGE_VERIFY_HASH, - alg); - - if (status != PSA_SUCCESS) { - return status; - } - - psa_key_attributes_t attributes = { - .core = slot->attr - }; - - if (input_is_message) { - status = psa_driver_wrapper_verify_message( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, - signature, signature_length); - } else { - status = psa_driver_wrapper_verify_hash( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, - signature, signature_length); - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; - -} - -psa_status_t psa_sign_message_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (PSA_ALG_IS_SIGN_HASH(alg)) { - size_t hash_length; - uint8_t hash[PSA_HASH_MAX_SIZE]; - - status = psa_driver_wrapper_hash_compute( - PSA_ALG_SIGN_GET_HASH(alg), - input, input_length, - hash, sizeof(hash), &hash_length); - - if (status != PSA_SUCCESS) { - return status; - } - - return psa_driver_wrapper_sign_hash( - attributes, key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_size, signature_length); - } - - return PSA_ERROR_NOT_SUPPORTED; -} - -psa_status_t psa_sign_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) -{ - return psa_sign_internal( - key, 1, alg, input, input_length, - signature, signature_size, signature_length); -} - -psa_status_t psa_verify_message_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (PSA_ALG_IS_SIGN_HASH(alg)) { - size_t hash_length; - uint8_t hash[PSA_HASH_MAX_SIZE]; - - status = psa_driver_wrapper_hash_compute( - PSA_ALG_SIGN_GET_HASH(alg), - input, input_length, - hash, sizeof(hash), &hash_length); - - if (status != PSA_SUCCESS) { - return status; - } - - return psa_driver_wrapper_verify_hash( - attributes, key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_length); - } - - return PSA_ERROR_NOT_SUPPORTED; -} - -psa_status_t psa_verify_message(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length) -{ - return psa_verify_internal( - key, 1, alg, input, input_length, - signature, signature_length); -} - -psa_status_t psa_sign_hash_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length) -{ - if (attributes->core.type == PSA_KEY_TYPE_RSA_KEY_PAIR) { - if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || - PSA_ALG_IS_RSA_PSS(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) - return mbedtls_psa_rsa_sign_hash( - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_size, signature_length); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } - } else if (PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { - if (PSA_ALG_IS_ECDSA(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) - return mbedtls_psa_ecdsa_sign_hash( - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_size, signature_length); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - (void) key_buffer; - (void) key_buffer_size; - (void) hash; - (void) hash_length; - (void) signature; - (void) signature_size; - (void) signature_length; - - return PSA_ERROR_NOT_SUPPORTED; -} - -psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) -{ - return psa_sign_internal( - key, 0, alg, hash, hash_length, - signature, signature_size, signature_length); -} - -psa_status_t psa_verify_hash_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length) -{ - if (PSA_KEY_TYPE_IS_RSA(attributes->core.type)) { - if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || - PSA_ALG_IS_RSA_PSS(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) - return mbedtls_psa_rsa_verify_hash( - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_length); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } - } else if (PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { - if (PSA_ALG_IS_ECDSA(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) - return mbedtls_psa_ecdsa_verify_hash( - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_length); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - (void) key_buffer; - (void) key_buffer_size; - (void) hash; - (void) hash_length; - (void) signature; - (void) signature_length; - - return PSA_ERROR_NOT_SUPPORTED; -} - -psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length) -{ - return psa_verify_internal( - key, 0, alg, hash, hash_length, - signature, signature_length); -} - -psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - psa_key_attributes_t attributes; - - (void) input; - (void) input_length; - (void) salt; - (void) output; - (void) output_size; - - *output_length = 0; - - if (!PSA_ALG_IS_RSA_OAEP(alg) && salt_length != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = psa_get_and_lock_transparent_key_slot_with_policy( - key, &slot, PSA_KEY_USAGE_ENCRYPT, alg); - if (status != PSA_SUCCESS) { - return status; - } - if (!(PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type) || - PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type))) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - status = psa_driver_wrapper_asymmetric_encrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, salt, salt_length, - output, output_size, output_length); -exit: - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - psa_key_attributes_t attributes; - - (void) input; - (void) input_length; - (void) salt; - (void) output; - (void) output_size; - - *output_length = 0; - - if (!PSA_ALG_IS_RSA_OAEP(alg) && salt_length != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = psa_get_and_lock_transparent_key_slot_with_policy( - key, &slot, PSA_KEY_USAGE_DECRYPT, alg); - if (status != PSA_SUCCESS) { - return status; - } - if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - status = psa_driver_wrapper_asymmetric_decrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, salt, salt_length, - output, output_size, output_length); - -exit: - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -/****************************************************************/ -/* Asymmetric interruptible cryptography */ -/****************************************************************/ - -static uint32_t psa_interruptible_max_ops = PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED; - -void psa_interruptible_set_max_ops(uint32_t max_ops) -{ - psa_interruptible_max_ops = max_ops; -} - -uint32_t psa_interruptible_get_max_ops(void) -{ - return psa_interruptible_max_ops; -} - -uint32_t psa_sign_hash_get_num_ops( - const psa_sign_hash_interruptible_operation_t *operation) -{ - return operation->num_ops; -} - -uint32_t psa_verify_hash_get_num_ops( - const psa_verify_hash_interruptible_operation_t *operation) -{ - return operation->num_ops; -} - -static psa_status_t psa_sign_hash_abort_internal( - psa_sign_hash_interruptible_operation_t *operation) -{ - if (operation->id == 0) { - /* The object has (apparently) been initialized but it is not (yet) - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - return PSA_SUCCESS; - } - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_driver_wrapper_sign_hash_abort(operation); - - operation->id = 0; - - /* Do not clear either the error_occurred or num_ops elements here as they - * only want to be cleared by the application calling abort, not by abort - * being called at completion of an operation. */ - - return status; -} - -psa_status_t psa_sign_hash_start( - psa_sign_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - psa_key_attributes_t attributes; - - /* Check that start has not been previously called, or operation has not - * previously errored. */ - if (operation->id != 0 || operation->error_occurred) { - return PSA_ERROR_BAD_STATE; - } - - status = psa_sign_verify_check_alg(0, alg); - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - return status; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, - PSA_KEY_USAGE_SIGN_HASH, - alg); - - if (status != PSA_SUCCESS) { - goto exit; - } - - if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - /* Ensure ops count gets reset, in case of operation re-use. */ - operation->num_ops = 0; - - status = psa_driver_wrapper_sign_hash_start(operation, &attributes, - slot->key.data, - slot->key.bytes, alg, - hash, hash_length); -exit: - - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - psa_sign_hash_abort_internal(operation); - } - - unlock_status = psa_unlock_key_slot(slot); - - if (unlock_status != PSA_SUCCESS) { - operation->error_occurred = 1; - } - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - - -psa_status_t psa_sign_hash_complete( - psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - *signature_length = 0; - - /* Check that start has been called first, and that operation has not - * previously errored. */ - if (operation->id == 0 || operation->error_occurred) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - /* Immediately reject a zero-length signature buffer. This guarantees that - * signature must be a valid pointer. */ - if (signature_size == 0) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_driver_wrapper_sign_hash_complete(operation, signature, - signature_size, - signature_length); - - /* Update ops count with work done. */ - operation->num_ops = psa_driver_wrapper_sign_hash_get_num_ops(operation); - -exit: - - psa_wipe_tag_output_buffer(signature, status, signature_size, - *signature_length); - - if (status != PSA_OPERATION_INCOMPLETE) { - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - } - - psa_sign_hash_abort_internal(operation); - } - - return status; -} - -psa_status_t psa_sign_hash_abort( - psa_sign_hash_interruptible_operation_t *operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_sign_hash_abort_internal(operation); - - /* We clear the number of ops done here, so that it is not cleared when - * the operation fails or succeeds, only on manual abort. */ - operation->num_ops = 0; - - /* Likewise, failure state. */ - operation->error_occurred = 0; - - return status; -} - -static psa_status_t psa_verify_hash_abort_internal( - psa_verify_hash_interruptible_operation_t *operation) -{ - if (operation->id == 0) { - /* The object has (apparently) been initialized but it is not (yet) - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - return PSA_SUCCESS; - } - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_driver_wrapper_verify_hash_abort(operation); - - operation->id = 0; - - /* Do not clear either the error_occurred or num_ops elements here as they - * only want to be cleared by the application calling abort, not by abort - * being called at completion of an operation. */ - - return status; -} - -psa_status_t psa_verify_hash_start( - psa_verify_hash_interruptible_operation_t *operation, - mbedtls_svc_key_id_t key, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - /* Check that start has not been previously called, or operation has not - * previously errored. */ - if (operation->id != 0 || operation->error_occurred) { - return PSA_ERROR_BAD_STATE; - } - - status = psa_sign_verify_check_alg(0, alg); - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - return status; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, - PSA_KEY_USAGE_VERIFY_HASH, - alg); - - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - return status; - } - - psa_key_attributes_t attributes = { - .core = slot->attr - }; - - /* Ensure ops count gets reset, in case of operation re-use. */ - operation->num_ops = 0; - - status = psa_driver_wrapper_verify_hash_start(operation, &attributes, - slot->key.data, - slot->key.bytes, - alg, hash, hash_length, - signature, signature_length); - - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - psa_verify_hash_abort_internal(operation); - } - - unlock_status = psa_unlock_key_slot(slot); - - if (unlock_status != PSA_SUCCESS) { - operation->error_occurred = 1; - } - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_verify_hash_complete( - psa_verify_hash_interruptible_operation_t *operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* Check that start has been called first, and that operation has not - * previously errored. */ - if (operation->id == 0 || operation->error_occurred) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_driver_wrapper_verify_hash_complete(operation); - - /* Update ops count with work done. */ - operation->num_ops = psa_driver_wrapper_verify_hash_get_num_ops( - operation); - -exit: - - if (status != PSA_OPERATION_INCOMPLETE) { - if (status != PSA_SUCCESS) { - operation->error_occurred = 1; - } - - psa_verify_hash_abort_internal(operation); - } - - return status; -} - -psa_status_t psa_verify_hash_abort( - psa_verify_hash_interruptible_operation_t *operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_verify_hash_abort_internal(operation); - - /* We clear the number of ops done here, so that it is not cleared when - * the operation fails or succeeds, only on manual abort. */ - operation->num_ops = 0; - - /* Likewise, failure state. */ - operation->error_occurred = 0; - - return status; -} - -/****************************************************************/ -/* Asymmetric interruptible cryptography internal */ -/* implementations */ -/****************************************************************/ - -void mbedtls_psa_interruptible_set_max_ops(uint32_t max_ops) -{ - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - /* Internal implementation uses zero to indicate infinite number max ops, - * therefore avoid this value, and set to minimum possible. */ - if (max_ops == 0) { - max_ops = 1; - } - - mbedtls_ecp_set_max_ops(max_ops); -#else - (void) max_ops; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -uint32_t mbedtls_psa_sign_hash_get_num_ops( - const mbedtls_psa_sign_hash_interruptible_operation_t *operation) -{ -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - return operation->num_ops; -#else - (void) operation; - return 0; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -uint32_t mbedtls_psa_verify_hash_get_num_ops( - const mbedtls_psa_verify_hash_interruptible_operation_t *operation) -{ - #if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - return operation->num_ops; -#else - (void) operation; - return 0; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_sign_hash_start( - mbedtls_psa_sign_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t required_hash_length = 0; - - if (!PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (!PSA_ALG_IS_ECDSA(alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - mbedtls_ecdsa_restart_init(&operation->restart_ctx); - - /* Ensure num_ops is zero'ed in case of context re-use. */ - operation->num_ops = 0; - - status = mbedtls_psa_ecp_load_representation(attributes->core.type, - attributes->core.bits, - key_buffer, - key_buffer_size, - &operation->ctx); - - if (status != PSA_SUCCESS) { - return status; - } - - operation->coordinate_bytes = PSA_BITS_TO_BYTES( - operation->ctx->grp.nbits); - - psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); - operation->md_alg = mbedtls_md_type_from_psa_alg(hash_alg); - operation->alg = alg; - - /* We only need to store the same length of hash as the private key size - * here, it would be truncated by the internal implementation anyway. */ - required_hash_length = (hash_length < operation->coordinate_bytes ? - hash_length : operation->coordinate_bytes); - - if (required_hash_length > sizeof(operation->hash)) { - /* Shouldn't happen, but better safe than sorry. */ - return PSA_ERROR_CORRUPTION_DETECTED; - } - - memcpy(operation->hash, hash, required_hash_length); - operation->hash_length = required_hash_length; - - return PSA_SUCCESS; - -#else - (void) operation; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - (void) hash; - (void) hash_length; - (void) status; - (void) required_hash_length; - - return PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_sign_hash_complete( - mbedtls_psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length) -{ -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_mpi r; - mbedtls_mpi s; - - mbedtls_mpi_init(&r); - mbedtls_mpi_init(&s); - - /* Ensure max_ops is set to the current value (or default). */ - mbedtls_psa_interruptible_set_max_ops(psa_interruptible_get_max_ops()); - - if (signature_size < 2 * operation->coordinate_bytes) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - if (PSA_ALG_ECDSA_IS_DETERMINISTIC(operation->alg)) { - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) - status = mbedtls_to_psa_error( - mbedtls_ecdsa_sign_det_restartable(&operation->ctx->grp, - &r, - &s, - &operation->ctx->d, - operation->hash, - operation->hash_length, - operation->md_alg, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - &operation->restart_ctx)); -#else /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - } else { - status = mbedtls_to_psa_error( - mbedtls_ecdsa_sign_restartable(&operation->ctx->grp, - &r, - &s, - &operation->ctx->d, - operation->hash, - operation->hash_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - &operation->restart_ctx)); - } - - /* Hide the fact that the restart context only holds a delta of number of - * ops done during the last operation, not an absolute value. */ - operation->num_ops += operation->restart_ctx.ecp.ops_done; - - if (status == PSA_SUCCESS) { - status = mbedtls_to_psa_error( - mbedtls_mpi_write_binary(&r, - signature, - operation->coordinate_bytes) - ); - - if (status != PSA_SUCCESS) { - goto exit; - } - - status = mbedtls_to_psa_error( - mbedtls_mpi_write_binary(&s, - signature + - operation->coordinate_bytes, - operation->coordinate_bytes) - ); - - if (status != PSA_SUCCESS) { - goto exit; - } - - *signature_length = operation->coordinate_bytes * 2; - - status = PSA_SUCCESS; - } - -exit: - - mbedtls_mpi_free(&r); - mbedtls_mpi_free(&s); - return status; - - #else - - (void) operation; - (void) signature; - (void) signature_size; - (void) signature_length; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_sign_hash_abort( - mbedtls_psa_sign_hash_interruptible_operation_t *operation) -{ - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - if (operation->ctx) { - mbedtls_ecdsa_free(operation->ctx); - mbedtls_free(operation->ctx); - operation->ctx = NULL; - } - - mbedtls_ecdsa_restart_free(&operation->restart_ctx); - - operation->num_ops = 0; - - return PSA_SUCCESS; - -#else - - (void) operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_verify_hash_start( - mbedtls_psa_verify_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t coordinate_bytes = 0; - size_t required_hash_length = 0; - - if (!PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (!PSA_ALG_IS_ECDSA(alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - mbedtls_ecdsa_restart_init(&operation->restart_ctx); - mbedtls_mpi_init(&operation->r); - mbedtls_mpi_init(&operation->s); - - /* Ensure num_ops is zero'ed in case of context re-use. */ - operation->num_ops = 0; - - status = mbedtls_psa_ecp_load_representation(attributes->core.type, - attributes->core.bits, - key_buffer, - key_buffer_size, - &operation->ctx); - - if (status != PSA_SUCCESS) { - return status; - } - - coordinate_bytes = PSA_BITS_TO_BYTES(operation->ctx->grp.nbits); - - if (signature_length != 2 * coordinate_bytes) { - return PSA_ERROR_INVALID_SIGNATURE; - } - - status = mbedtls_to_psa_error( - mbedtls_mpi_read_binary(&operation->r, - signature, - coordinate_bytes)); - - if (status != PSA_SUCCESS) { - return status; - } - - status = mbedtls_to_psa_error( - mbedtls_mpi_read_binary(&operation->s, - signature + - coordinate_bytes, - coordinate_bytes)); - - if (status != PSA_SUCCESS) { - return status; - } - - status = mbedtls_psa_ecp_load_public_part(operation->ctx); - - if (status != PSA_SUCCESS) { - return status; - } - - /* We only need to store the same length of hash as the private key size - * here, it would be truncated by the internal implementation anyway. */ - required_hash_length = (hash_length < coordinate_bytes ? hash_length : - coordinate_bytes); - - if (required_hash_length > sizeof(operation->hash)) { - /* Shouldn't happen, but better safe than sorry. */ - return PSA_ERROR_CORRUPTION_DETECTED; - } - - memcpy(operation->hash, hash, required_hash_length); - operation->hash_length = required_hash_length; - - return PSA_SUCCESS; -#else - (void) operation; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - (void) hash; - (void) hash_length; - (void) signature; - (void) signature_length; - (void) status; - (void) coordinate_bytes; - (void) required_hash_length; - - return PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_verify_hash_complete( - mbedtls_psa_verify_hash_interruptible_operation_t *operation) -{ - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* Ensure max_ops is set to the current value (or default). */ - mbedtls_psa_interruptible_set_max_ops(psa_interruptible_get_max_ops()); - - status = mbedtls_to_psa_error( - mbedtls_ecdsa_verify_restartable(&operation->ctx->grp, - operation->hash, - operation->hash_length, - &operation->ctx->Q, - &operation->r, - &operation->s, - &operation->restart_ctx)); - - /* Hide the fact that the restart context only holds a delta of number of - * ops done during the last operation, not an absolute value. */ - operation->num_ops += operation->restart_ctx.ecp.ops_done; - - return status; -#else - (void) operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -psa_status_t mbedtls_psa_verify_hash_abort( - mbedtls_psa_verify_hash_interruptible_operation_t *operation) -{ - -#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ - defined(MBEDTLS_ECP_RESTARTABLE) - - if (operation->ctx) { - mbedtls_ecdsa_free(operation->ctx); - mbedtls_free(operation->ctx); - operation->ctx = NULL; - } - - mbedtls_ecdsa_restart_free(&operation->restart_ctx); - - operation->num_ops = 0; - - mbedtls_mpi_free(&operation->r); - mbedtls_mpi_free(&operation->s); - - return PSA_SUCCESS; - -#else - (void) operation; - - return PSA_ERROR_NOT_SUPPORTED; - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && - * defined( MBEDTLS_ECP_RESTARTABLE ) */ -} - -/****************************************************************/ -/* Symmetric cryptography */ -/****************************************************************/ - -static psa_status_t psa_cipher_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - mbedtls_operation_t cipher_operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - psa_key_usage_t usage = (cipher_operation == MBEDTLS_ENCRYPT ? - PSA_KEY_USAGE_ENCRYPT : - PSA_KEY_USAGE_DECRYPT); - psa_key_attributes_t attributes; - - /* A context must be freshly initialized before it can be set up. */ - if (operation->id != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (!PSA_ALG_IS_CIPHER(alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, usage, alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Initialize the operation struct members, except for id. The id member - * is used to indicate to psa_cipher_abort that there are resources to free, - * so we only set it (in the driver wrapper) after resources have been - * allocated/initialized. */ - operation->iv_set = 0; - if (alg == PSA_ALG_ECB_NO_PADDING) { - operation->iv_required = 0; - } else { - operation->iv_required = 1; - } - operation->default_iv_length = PSA_CIPHER_IV_LENGTH(slot->attr.type, alg); - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - /* Try doing the operation through a driver before using software fallback. */ - if (cipher_operation == MBEDTLS_ENCRYPT) { - status = psa_driver_wrapper_cipher_encrypt_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } else { - status = psa_driver_wrapper_cipher_decrypt_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } - -exit: - if (status != PSA_SUCCESS) { - psa_cipher_abort(operation); - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_cipher_setup(operation, key, alg, MBEDTLS_ENCRYPT); -} - -psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_cipher_setup(operation, key, alg, MBEDTLS_DECRYPT); -} - -psa_status_t psa_cipher_generate_iv(psa_cipher_operation_t *operation, - uint8_t *iv, - size_t iv_size, - size_t *iv_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t local_iv[PSA_CIPHER_IV_MAX_SIZE]; - size_t default_iv_length = 0; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->iv_set || !operation->iv_required) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - default_iv_length = operation->default_iv_length; - if (iv_size < default_iv_length) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - if (default_iv_length > PSA_CIPHER_IV_MAX_SIZE) { - status = PSA_ERROR_GENERIC_ERROR; - goto exit; - } - - status = psa_generate_random(local_iv, default_iv_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_driver_wrapper_cipher_set_iv(operation, - local_iv, default_iv_length); - -exit: - if (status == PSA_SUCCESS) { - memcpy(iv, local_iv, default_iv_length); - *iv_length = default_iv_length; - operation->iv_set = 1; - } else { - *iv_length = 0; - psa_cipher_abort(operation); - } - - return status; -} - -psa_status_t psa_cipher_set_iv(psa_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->iv_set || !operation->iv_required) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (iv_length > PSA_CIPHER_IV_MAX_SIZE) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_driver_wrapper_cipher_set_iv(operation, - iv, - iv_length); - -exit: - if (status == PSA_SUCCESS) { - operation->iv_set = 1; - } else { - psa_cipher_abort(operation); - } - return status; -} - -psa_status_t psa_cipher_update(psa_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->iv_required && !operation->iv_set) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_driver_wrapper_cipher_update(operation, - input, - input_length, - output, - output_size, - output_length); - -exit: - if (status != PSA_SUCCESS) { - psa_cipher_abort(operation); - } - - return status; -} - -psa_status_t psa_cipher_finish(psa_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->iv_required && !operation->iv_set) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_driver_wrapper_cipher_finish(operation, - output, - output_size, - output_length); - -exit: - if (status == PSA_SUCCESS) { - return psa_cipher_abort(operation); - } else { - *output_length = 0; - (void) psa_cipher_abort(operation); - - return status; - } -} - -psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation) -{ - if (operation->id == 0) { - /* The object has (apparently) been initialized but it is not (yet) - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - return PSA_SUCCESS; - } - - psa_driver_wrapper_cipher_abort(operation); - - operation->id = 0; - operation->iv_set = 0; - operation->iv_required = 0; - - return PSA_SUCCESS; -} - -psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - uint8_t local_iv[PSA_CIPHER_IV_MAX_SIZE]; - size_t default_iv_length = 0; - psa_key_attributes_t attributes; - - if (!PSA_ALG_IS_CIPHER(alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, - PSA_KEY_USAGE_ENCRYPT, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - default_iv_length = PSA_CIPHER_IV_LENGTH(slot->attr.type, alg); - if (default_iv_length > PSA_CIPHER_IV_MAX_SIZE) { - status = PSA_ERROR_GENERIC_ERROR; - goto exit; - } - - if (default_iv_length > 0) { - if (output_size < default_iv_length) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_generate_random(local_iv, default_iv_length); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = psa_driver_wrapper_cipher_encrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, local_iv, default_iv_length, input, input_length, - psa_crypto_buffer_offset(output, default_iv_length), - output_size - default_iv_length, output_length); - -exit: - unlock_status = psa_unlock_key_slot(slot); - if (status == PSA_SUCCESS) { - status = unlock_status; - } - - if (status == PSA_SUCCESS) { - if (default_iv_length > 0) { - memcpy(output, local_iv, default_iv_length); - } - *output_length += default_iv_length; - } else { - *output_length = 0; - } - - return status; -} - -psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - psa_key_attributes_t attributes; - - if (!PSA_ALG_IS_CIPHER(alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, - PSA_KEY_USAGE_DECRYPT, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - if (alg == PSA_ALG_CCM_STAR_NO_TAG && - input_length < PSA_BLOCK_CIPHER_BLOCK_LENGTH(slot->attr.type)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } else if (input_length < PSA_CIPHER_IV_LENGTH(slot->attr.type, alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_driver_wrapper_cipher_decrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, input, input_length, - output, output_size, output_length); - -exit: - unlock_status = psa_unlock_key_slot(slot); - if (status == PSA_SUCCESS) { - status = unlock_status; - } - - if (status != PSA_SUCCESS) { - *output_length = 0; - } - - return status; -} - - -/****************************************************************/ -/* AEAD */ -/****************************************************************/ - -/* Helper function to get the base algorithm from its variants. */ -static psa_algorithm_t psa_aead_get_base_algorithm(psa_algorithm_t alg) -{ - return PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(alg); -} - -/* Helper function to perform common nonce length checks. */ -static psa_status_t psa_aead_check_nonce_length(psa_algorithm_t alg, - size_t nonce_length) -{ - psa_algorithm_t base_alg = psa_aead_get_base_algorithm(alg); - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - - switch (base_alg) { -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_GCM: - /* Not checking max nonce size here as GCM spec allows almost - * arbitrarily large nonces. Please note that we do not generally - * recommend the usage of nonces of greater length than - * PSA_AEAD_NONCE_MAX_SIZE, as large nonces are hashed to a shorter - * size, which can then lead to collisions if you encrypt a very - * large number of messages.*/ - if (nonce_length != 0) { - return PSA_SUCCESS; - } - break; -#endif /* PSA_WANT_ALG_GCM */ -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM: - if (nonce_length >= 7 && nonce_length <= 13) { - return PSA_SUCCESS; - } - break; -#endif /* PSA_WANT_ALG_CCM */ -#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) - case PSA_ALG_CHACHA20_POLY1305: - if (nonce_length == 12) { - return PSA_SUCCESS; - } else if (nonce_length == 8) { - return PSA_ERROR_NOT_SUPPORTED; - } - break; -#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ - default: - (void)nonce_length; - status = PSA_ERROR_NOT_SUPPORTED; - break; - } - - return status; -} - -static psa_status_t psa_aead_check_algorithm(psa_algorithm_t alg) -{ - if (!PSA_ALG_IS_AEAD(alg) || PSA_ALG_IS_WILDCARD(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *plaintext, - size_t plaintext_length, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - *ciphertext_length = 0; - - status = psa_aead_check_algorithm(alg); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_get_and_lock_key_slot_with_policy( - key, &slot, PSA_KEY_USAGE_ENCRYPT, alg); - if (status != PSA_SUCCESS) { - return status; - } - - psa_key_attributes_t attributes = { - .core = slot->attr - }; - - status = psa_aead_check_nonce_length(alg, nonce_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_driver_wrapper_aead_encrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length); - - if (status != PSA_SUCCESS && ciphertext_size != 0) { - memset(ciphertext, 0, ciphertext_size); - } - -exit: - psa_unlock_key_slot(slot); - - return status; -} - -psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, - psa_algorithm_t alg, - const uint8_t *nonce, - size_t nonce_length, - const uint8_t *additional_data, - size_t additional_data_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - *plaintext_length = 0; - - status = psa_aead_check_algorithm(alg); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_get_and_lock_key_slot_with_policy( - key, &slot, PSA_KEY_USAGE_DECRYPT, alg); - if (status != PSA_SUCCESS) { - return status; - } - - psa_key_attributes_t attributes = { - .core = slot->attr - }; - - status = psa_aead_check_nonce_length(alg, nonce_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_driver_wrapper_aead_decrypt( - &attributes, slot->key.data, slot->key.bytes, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length); - - if (status != PSA_SUCCESS && plaintext_size != 0) { - memset(plaintext, 0, plaintext_size); - } - -exit: - psa_unlock_key_slot(slot); - - return status; -} - -static psa_status_t psa_validate_tag_length(psa_algorithm_t alg) -{ - const uint8_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg); - psa_status_t status = PSA_SUCCESS; - - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - /* CCM allows the following tag lengths: 4, 6, 8, 10, 12, 14, 16.*/ - if (tag_len < 4 || tag_len > 16 || tag_len % 2) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif /* PSA_WANT_ALG_CCM */ - -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - /* GCM allows the following tag lengths: 4, 8, 12, 13, 14, 15, 16. */ - if (tag_len != 4 && tag_len != 8 && (tag_len < 12 || tag_len > 16)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif /* PSA_WANT_ALG_GCM */ - -#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): - /* We only support the default tag length. */ - if (tag_len != 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - break; -#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ - - default: - (void) tag_len; - status = PSA_ERROR_NOT_SUPPORTED; - } - return status; -} - -/* Set the key for a multipart authenticated operation. */ -static psa_status_t psa_aead_setup(psa_aead_operation_t *operation, - int is_encrypt, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - psa_key_usage_t key_usage = 0; - psa_key_attributes_t attributes; - - status = psa_aead_check_algorithm(alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (operation->id != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->nonce_set || operation->lengths_set || - operation->ad_started || operation->body_started) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (is_encrypt) { - key_usage = PSA_KEY_USAGE_ENCRYPT; - } else { - key_usage = PSA_KEY_USAGE_DECRYPT; - } - - status = psa_get_and_lock_key_slot_with_policy(key, &slot, key_usage, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - if ((status = psa_validate_tag_length(alg)) != PSA_SUCCESS) { - goto exit; - } - - if (is_encrypt) { - status = psa_driver_wrapper_aead_encrypt_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } else { - status = psa_driver_wrapper_aead_decrypt_setup(operation, - &attributes, - slot->key.data, - slot->key.bytes, - alg); - } - if (status != PSA_SUCCESS) { - goto exit; - } - - operation->key_type = psa_get_key_type(&attributes); - -exit: - unlock_status = psa_unlock_key_slot(slot); - - if (status == PSA_SUCCESS) { - status = unlock_status; - operation->alg = psa_aead_get_base_algorithm(alg); - operation->is_encrypt = is_encrypt; - } else { - psa_aead_abort(operation); - } - - return status; -} - -/* Set the key for a multipart authenticated encryption operation. */ -psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_aead_setup(operation, 1, key, alg); -} - -/* Set the key for a multipart authenticated decryption operation. */ -psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, - mbedtls_svc_key_id_t key, - psa_algorithm_t alg) -{ - return psa_aead_setup(operation, 0, key, alg); -} - -/* Generate a random nonce / IV for multipart AEAD operation */ -psa_status_t psa_aead_generate_nonce(psa_aead_operation_t *operation, - uint8_t *nonce, - size_t nonce_size, - size_t *nonce_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t local_nonce[PSA_AEAD_NONCE_MAX_SIZE]; - size_t required_nonce_size = 0; - - *nonce_length = 0; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->nonce_set || !operation->is_encrypt) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - /* For CCM, this size may not be correct according to the PSA - * specification. The PSA Crypto 1.0.1 specification states: - * - * CCM encodes the plaintext length pLen in L octets, with L the smallest - * integer >= 2 where pLen < 2^(8L). The nonce length is then 15 - L bytes. - * - * However this restriction that L has to be the smallest integer is not - * applied in practice, and it is not implementable here since the - * plaintext length may or may not be known at this time. */ - required_nonce_size = PSA_AEAD_NONCE_LENGTH(operation->key_type, - operation->alg); - if (nonce_size < required_nonce_size) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_generate_random(local_nonce, required_nonce_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_aead_set_nonce(operation, local_nonce, required_nonce_size); - -exit: - if (status == PSA_SUCCESS) { - memcpy(nonce, local_nonce, required_nonce_size); - *nonce_length = required_nonce_size; - } else { - psa_aead_abort(operation); - } - - return status; -} - -/* Set the nonce for a multipart authenticated encryption or decryption - operation.*/ -psa_status_t psa_aead_set_nonce(psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->nonce_set) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_aead_check_nonce_length(operation->alg, nonce_length); - if (status != PSA_SUCCESS) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - status = psa_driver_wrapper_aead_set_nonce(operation, nonce, - nonce_length); - -exit: - if (status == PSA_SUCCESS) { - operation->nonce_set = 1; - } else { - psa_aead_abort(operation); - } - - return status; -} - -/* Declare the lengths of the message and additional data for multipart AEAD. */ -psa_status_t psa_aead_set_lengths(psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->lengths_set || operation->ad_started || - operation->body_started) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_GCM) - case PSA_ALG_GCM: - /* Lengths can only be too large for GCM if size_t is bigger than 32 - * bits. Without the guard this code will generate warnings on 32bit - * builds. */ -#if SIZE_MAX > UINT32_MAX - if (((uint64_t) ad_length) >> 61 != 0 || - ((uint64_t) plaintext_length) > 0xFFFFFFFE0ull) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } -#endif - break; -#endif /* PSA_WANT_ALG_GCM */ -#if defined(PSA_WANT_ALG_CCM) - case PSA_ALG_CCM: - if (ad_length > 0xFF00) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - break; -#endif /* PSA_WANT_ALG_CCM */ -#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) - case PSA_ALG_CHACHA20_POLY1305: - /* No length restrictions for ChaChaPoly. */ - break; -#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ - default: - break; - } - - status = psa_driver_wrapper_aead_set_lengths(operation, ad_length, - plaintext_length); - -exit: - if (status == PSA_SUCCESS) { - operation->ad_remaining = ad_length; - operation->body_remaining = plaintext_length; - operation->lengths_set = 1; - } else { - psa_aead_abort(operation); - } - - return status; -} - -/* Pass additional data to an active multipart AEAD operation. */ -psa_status_t psa_aead_update_ad(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (!operation->nonce_set || operation->body_started) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->lengths_set) { - if (operation->ad_remaining < input_length) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - operation->ad_remaining -= input_length; - } -#if defined(PSA_WANT_ALG_CCM) - else if (operation->alg == PSA_ALG_CCM) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } -#endif /* PSA_WANT_ALG_CCM */ - - status = psa_driver_wrapper_aead_update_ad(operation, input, - input_length); - -exit: - if (status == PSA_SUCCESS) { - operation->ad_started = 1; - } else { - psa_aead_abort(operation); - } - - return status; -} - -/* Encrypt or decrypt a message fragment in an active multipart AEAD - operation.*/ -psa_status_t psa_aead_update(psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - *output_length = 0; - - if (operation->id == 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (!operation->nonce_set) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->lengths_set) { - /* Additional data length was supplied, but not all the additional - data was supplied.*/ - if (operation->ad_remaining != 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - /* Too much data provided. */ - if (operation->body_remaining < input_length) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - operation->body_remaining -= input_length; - } -#if defined(PSA_WANT_ALG_CCM) - else if (operation->alg == PSA_ALG_CCM) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } -#endif /* PSA_WANT_ALG_CCM */ - - status = psa_driver_wrapper_aead_update(operation, input, input_length, - output, output_size, - output_length); - -exit: - if (status == PSA_SUCCESS) { - operation->body_started = 1; - } else { - psa_aead_abort(operation); - } - - return status; -} - -static psa_status_t psa_aead_final_checks(const psa_aead_operation_t *operation) -{ - if (operation->id == 0 || !operation->nonce_set) { - return PSA_ERROR_BAD_STATE; - } - - if (operation->lengths_set && (operation->ad_remaining != 0 || - operation->body_remaining != 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return PSA_SUCCESS; -} - -/* Finish encrypting a message in a multipart AEAD operation. */ -psa_status_t psa_aead_finish(psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - *ciphertext_length = 0; - *tag_length = tag_size; - - status = psa_aead_final_checks(operation); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (!operation->is_encrypt) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_driver_wrapper_aead_finish(operation, ciphertext, - ciphertext_size, - ciphertext_length, - tag, tag_size, tag_length); - -exit: - - - /* In case the operation fails and the user fails to check for failure or - * the zero tag size, make sure the tag is set to something implausible. - * Even if the operation succeeds, make sure we clear the rest of the - * buffer to prevent potential leakage of anything previously placed in - * the same buffer.*/ - psa_wipe_tag_output_buffer(tag, status, tag_size, *tag_length); - - psa_aead_abort(operation); - - return status; -} - -/* Finish authenticating and decrypting a message in a multipart AEAD - operation.*/ -psa_status_t psa_aead_verify(psa_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - *plaintext_length = 0; - - status = psa_aead_final_checks(operation); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (operation->is_encrypt) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_driver_wrapper_aead_verify(operation, plaintext, - plaintext_size, - plaintext_length, - tag, tag_length); - -exit: - psa_aead_abort(operation); - - return status; -} - -/* Abort an AEAD operation. */ -psa_status_t psa_aead_abort(psa_aead_operation_t *operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->id == 0) { - /* The object has (apparently) been initialized but it is not (yet) - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - return PSA_SUCCESS; - } - - status = psa_driver_wrapper_aead_abort(operation); - - memset(operation, 0, sizeof(*operation)); - - return status; -} - -/****************************************************************/ -/* Generators */ -/****************************************************************/ - -#if defined(BUILTIN_ALG_ANY_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) || \ - defined(PSA_HAVE_SOFT_PBKDF2) -#define AT_LEAST_ONE_BUILTIN_KDF -#endif /* At least one builtin KDF */ - -#if defined(BUILTIN_ALG_ANY_HKDF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) -static psa_status_t psa_key_derivation_start_hmac( - psa_mac_operation_t *operation, - psa_algorithm_t hash_alg, - const uint8_t *hmac_key, - size_t hmac_key_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_type(&attributes, PSA_KEY_TYPE_HMAC); - psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(hmac_key_length)); - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); - - operation->is_sign = 1; - operation->mac_size = PSA_HASH_LENGTH(hash_alg); - - status = psa_driver_wrapper_mac_sign_setup(operation, - &attributes, - hmac_key, hmac_key_length, - PSA_ALG_HMAC(hash_alg)); - - psa_reset_key_attributes(&attributes); - return status; -} -#endif /* KDF algorithms reliant on HMAC */ - -#define HKDF_STATE_INIT 0 /* no input yet */ -#define HKDF_STATE_STARTED 1 /* got salt */ -#define HKDF_STATE_KEYED 2 /* got key */ -#define HKDF_STATE_OUTPUT 3 /* output started */ - -static psa_algorithm_t psa_key_derivation_get_kdf_alg( - const psa_key_derivation_operation_t *operation) -{ - if (PSA_ALG_IS_KEY_AGREEMENT(operation->alg)) { - return PSA_ALG_KEY_AGREEMENT_GET_KDF(operation->alg); - } else { - return operation->alg; - } -} - -psa_status_t psa_key_derivation_abort(psa_key_derivation_operation_t *operation) -{ - psa_status_t status = PSA_SUCCESS; - psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); - if (kdf_alg == 0) { - /* The object has (apparently) been initialized but it is not - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - } else -#if defined(BUILTIN_ALG_ANY_HKDF) - if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { - mbedtls_free(operation->ctx.hkdf.info); - status = psa_mac_abort(&operation->ctx.hkdf.hmac); - } else -#endif /* BUILTIN_ALG_ANY_HKDF */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - if (PSA_ALG_IS_TLS12_PRF(kdf_alg) || - /* TLS-1.2 PSK-to-MS KDF uses the same core as TLS-1.2 PRF */ - PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { - if (operation->ctx.tls12_prf.secret != NULL) { - mbedtls_zeroize_and_free(operation->ctx.tls12_prf.secret, - operation->ctx.tls12_prf.secret_length); - } - - if (operation->ctx.tls12_prf.seed != NULL) { - mbedtls_zeroize_and_free(operation->ctx.tls12_prf.seed, - operation->ctx.tls12_prf.seed_length); - } - - if (operation->ctx.tls12_prf.label != NULL) { - mbedtls_zeroize_and_free(operation->ctx.tls12_prf.label, - operation->ctx.tls12_prf.label_length); - } -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - if (operation->ctx.tls12_prf.other_secret != NULL) { - mbedtls_zeroize_and_free(operation->ctx.tls12_prf.other_secret, - operation->ctx.tls12_prf.other_secret_length); - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ - status = PSA_SUCCESS; - - /* We leave the fields Ai and output_block to be erased safely by the - * mbedtls_platform_zeroize() in the end of this function. */ - } else -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - mbedtls_platform_zeroize(operation->ctx.tls12_ecjpake_to_pms.data, - sizeof(operation->ctx.tls12_ecjpake_to_pms.data)); - } else -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) */ -#if defined(PSA_HAVE_SOFT_PBKDF2) - if (PSA_ALG_IS_PBKDF2(kdf_alg)) { - if (operation->ctx.pbkdf2.salt != NULL) { - mbedtls_zeroize_and_free(operation->ctx.pbkdf2.salt, - operation->ctx.pbkdf2.salt_length); - } - - status = PSA_SUCCESS; - } else -#endif /* defined(PSA_HAVE_SOFT_PBKDF2) */ - { - status = PSA_ERROR_BAD_STATE; - } - mbedtls_platform_zeroize(operation, sizeof(*operation)); - return status; -} - -psa_status_t psa_key_derivation_get_capacity(const psa_key_derivation_operation_t *operation, - size_t *capacity) -{ - if (operation->alg == 0) { - /* This is a blank key derivation operation. */ - return PSA_ERROR_BAD_STATE; - } - - *capacity = operation->capacity; - return PSA_SUCCESS; -} - -psa_status_t psa_key_derivation_set_capacity(psa_key_derivation_operation_t *operation, - size_t capacity) -{ - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - if (capacity > operation->capacity) { - return PSA_ERROR_INVALID_ARGUMENT; - } - operation->capacity = capacity; - return PSA_SUCCESS; -} - -#if defined(BUILTIN_ALG_ANY_HKDF) -/* Read some bytes from an HKDF-based operation. */ -static psa_status_t psa_key_derivation_hkdf_read(psa_hkdf_key_derivation_t *hkdf, - psa_algorithm_t kdf_alg, - uint8_t *output, - size_t output_length) -{ - psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); - uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); - size_t hmac_output_length; - psa_status_t status; -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - const uint8_t last_block = PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) ? 0 : 0xff; -#else - const uint8_t last_block = 0xff; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ - - if (hkdf->state < HKDF_STATE_KEYED || - (!hkdf->info_set -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - && !PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ - )) { - return PSA_ERROR_BAD_STATE; - } - hkdf->state = HKDF_STATE_OUTPUT; - - while (output_length != 0) { - /* Copy what remains of the current block */ - uint8_t n = hash_length - hkdf->offset_in_block; - if (n > output_length) { - n = (uint8_t) output_length; - } - memcpy(output, hkdf->output_block + hkdf->offset_in_block, n); - output += n; - output_length -= n; - hkdf->offset_in_block += n; - if (output_length == 0) { - break; - } - /* We can't be wanting more output after the last block, otherwise - * the capacity check in psa_key_derivation_output_bytes() would have - * prevented this call. It could happen only if the operation - * object was corrupted or if this function is called directly - * inside the library. */ - if (hkdf->block_number == last_block) { - return PSA_ERROR_BAD_STATE; - } - - /* We need a new block */ - ++hkdf->block_number; - hkdf->offset_in_block = 0; - - status = psa_key_derivation_start_hmac(&hkdf->hmac, - hash_alg, - hkdf->prk, - hash_length); - if (status != PSA_SUCCESS) { - return status; - } - - if (hkdf->block_number != 1) { - status = psa_mac_update(&hkdf->hmac, - hkdf->output_block, - hash_length); - if (status != PSA_SUCCESS) { - return status; - } - } - status = psa_mac_update(&hkdf->hmac, - hkdf->info, - hkdf->info_length); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_mac_update(&hkdf->hmac, - &hkdf->block_number, 1); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_mac_sign_finish(&hkdf->hmac, - hkdf->output_block, - sizeof(hkdf->output_block), - &hmac_output_length); - if (status != PSA_SUCCESS) { - return status; - } - } - - return PSA_SUCCESS; -} -#endif /* BUILTIN_ALG_ANY_HKDF */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) -static psa_status_t psa_key_derivation_tls12_prf_generate_next_block( - psa_tls12_prf_key_derivation_t *tls12_prf, - psa_algorithm_t alg) -{ - psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(alg); - uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); - psa_mac_operation_t hmac = PSA_MAC_OPERATION_INIT; - size_t hmac_output_length; - psa_status_t status, cleanup_status; - - /* We can't be wanting more output after block 0xff, otherwise - * the capacity check in psa_key_derivation_output_bytes() would have - * prevented this call. It could happen only if the operation - * object was corrupted or if this function is called directly - * inside the library. */ - if (tls12_prf->block_number == 0xff) { - return PSA_ERROR_CORRUPTION_DETECTED; - } - - /* We need a new block */ - ++tls12_prf->block_number; - tls12_prf->left_in_block = hash_length; - - /* Recall the definition of the TLS-1.2-PRF from RFC 5246: - * - * PRF(secret, label, seed) = P_(secret, label + seed) - * - * P_hash(secret, seed) = HMAC_hash(secret, A(1) + seed) + - * HMAC_hash(secret, A(2) + seed) + - * HMAC_hash(secret, A(3) + seed) + ... - * - * A(0) = seed - * A(i) = HMAC_hash(secret, A(i-1)) - * - * The `psa_tls12_prf_key_derivation` structure saves the block - * `HMAC_hash(secret, A(i) + seed)` from which the output - * is currently extracted as `output_block` and where i is - * `block_number`. - */ - - status = psa_key_derivation_start_hmac(&hmac, - hash_alg, - tls12_prf->secret, - tls12_prf->secret_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - /* Calculate A(i) where i = tls12_prf->block_number. */ - if (tls12_prf->block_number == 1) { - /* A(1) = HMAC_hash(secret, A(0)), where A(0) = seed. (The RFC overloads - * the variable seed and in this instance means it in the context of the - * P_hash function, where seed = label + seed.) */ - status = psa_mac_update(&hmac, - tls12_prf->label, - tls12_prf->label_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&hmac, - tls12_prf->seed, - tls12_prf->seed_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - } else { - /* A(i) = HMAC_hash(secret, A(i-1)) */ - status = psa_mac_update(&hmac, tls12_prf->Ai, hash_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - } - - status = psa_mac_sign_finish(&hmac, - tls12_prf->Ai, hash_length, - &hmac_output_length); - if (hmac_output_length != hash_length) { - status = PSA_ERROR_CORRUPTION_DETECTED; - } - if (status != PSA_SUCCESS) { - goto cleanup; - } - - /* Calculate HMAC_hash(secret, A(i) + label + seed). */ - status = psa_key_derivation_start_hmac(&hmac, - hash_alg, - tls12_prf->secret, - tls12_prf->secret_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&hmac, tls12_prf->Ai, hash_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&hmac, tls12_prf->label, tls12_prf->label_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&hmac, tls12_prf->seed, tls12_prf->seed_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_sign_finish(&hmac, - tls12_prf->output_block, hash_length, - &hmac_output_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - -cleanup: - cleanup_status = psa_mac_abort(&hmac); - if (status == PSA_SUCCESS && cleanup_status != PSA_SUCCESS) { - status = cleanup_status; - } - - return status; -} - -static psa_status_t psa_key_derivation_tls12_prf_read( - psa_tls12_prf_key_derivation_t *tls12_prf, - psa_algorithm_t alg, - uint8_t *output, - size_t output_length) -{ - psa_algorithm_t hash_alg = PSA_ALG_TLS12_PRF_GET_HASH(alg); - uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); - psa_status_t status; - uint8_t offset, length; - - switch (tls12_prf->state) { - case PSA_TLS12_PRF_STATE_LABEL_SET: - tls12_prf->state = PSA_TLS12_PRF_STATE_OUTPUT; - break; - case PSA_TLS12_PRF_STATE_OUTPUT: - break; - default: - return PSA_ERROR_BAD_STATE; - } - - while (output_length != 0) { - /* Check if we have fully processed the current block. */ - if (tls12_prf->left_in_block == 0) { - status = psa_key_derivation_tls12_prf_generate_next_block(tls12_prf, - alg); - if (status != PSA_SUCCESS) { - return status; - } - - continue; - } - - if (tls12_prf->left_in_block > output_length) { - length = (uint8_t) output_length; - } else { - length = tls12_prf->left_in_block; - } - - offset = hash_length - tls12_prf->left_in_block; - memcpy(output, tls12_prf->output_block + offset, length); - output += length; - output_length -= length; - tls12_prf->left_in_block -= length; - } - - return PSA_SUCCESS; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || - * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) -static psa_status_t psa_key_derivation_tls12_ecjpake_to_pms_read( - psa_tls12_ecjpake_to_pms_t *ecjpake, - uint8_t *output, - size_t output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t output_size = 0; - - if (output_length != 32) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = psa_hash_compute(PSA_ALG_SHA_256, ecjpake->data, - PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE, output, output_length, - &output_size); - if (status != PSA_SUCCESS) { - return status; - } - - if (output_size != output_length) { - return PSA_ERROR_GENERIC_ERROR; - } - - return PSA_SUCCESS; -} -#endif - -#if defined(PSA_HAVE_SOFT_PBKDF2) -static psa_status_t psa_key_derivation_pbkdf2_generate_block( - psa_pbkdf2_key_derivation_t *pbkdf2, - psa_algorithm_t prf_alg, - uint8_t prf_output_length, - psa_key_attributes_t *attributes) -{ - psa_status_t status; - psa_mac_operation_t mac_operation = PSA_MAC_OPERATION_INIT; - size_t mac_output_length; - uint8_t U_i[PSA_MAC_MAX_SIZE]; - uint8_t *U_accumulator = pbkdf2->output_block; - uint64_t i; - uint8_t block_counter[4]; - - mac_operation.is_sign = 1; - mac_operation.mac_size = prf_output_length; - MBEDTLS_PUT_UINT32_BE(pbkdf2->block_number, block_counter, 0); - - status = psa_driver_wrapper_mac_sign_setup(&mac_operation, - attributes, - pbkdf2->password, - pbkdf2->password_length, - prf_alg); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&mac_operation, pbkdf2->salt, pbkdf2->salt_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_update(&mac_operation, block_counter, sizeof(block_counter)); - if (status != PSA_SUCCESS) { - goto cleanup; - } - status = psa_mac_sign_finish(&mac_operation, U_i, sizeof(U_i), - &mac_output_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - if (mac_output_length != prf_output_length) { - status = PSA_ERROR_CORRUPTION_DETECTED; - goto cleanup; - } - - memcpy(U_accumulator, U_i, prf_output_length); - - for (i = 1; i < pbkdf2->input_cost; i++) { - /* We are passing prf_output_length as mac_size because the driver - * function directly sets mac_output_length as mac_size upon success. - * See https://github.com/Mbed-TLS/mbedtls/issues/7801 */ - status = psa_driver_wrapper_mac_compute(attributes, - pbkdf2->password, - pbkdf2->password_length, - prf_alg, U_i, prf_output_length, - U_i, prf_output_length, - &mac_output_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - mbedtls_xor(U_accumulator, U_accumulator, U_i, prf_output_length); - } - -cleanup: - /* Zeroise buffers to clear sensitive data from memory. */ - mbedtls_platform_zeroize(U_i, PSA_MAC_MAX_SIZE); - return status; -} - -static psa_status_t psa_key_derivation_pbkdf2_read( - psa_pbkdf2_key_derivation_t *pbkdf2, - psa_algorithm_t kdf_alg, - uint8_t *output, - size_t output_length) -{ - psa_status_t status; - psa_algorithm_t prf_alg; - uint8_t prf_output_length; - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(pbkdf2->password_length)); - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_MESSAGE); - - if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { - prf_alg = PSA_ALG_HMAC(PSA_ALG_PBKDF2_HMAC_GET_HASH(kdf_alg)); - prf_output_length = PSA_HASH_LENGTH(prf_alg); - psa_set_key_type(&attributes, PSA_KEY_TYPE_HMAC); - } else if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { - prf_alg = PSA_ALG_CMAC; - prf_output_length = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - } else { - return PSA_ERROR_INVALID_ARGUMENT; - } - - switch (pbkdf2->state) { - case PSA_PBKDF2_STATE_PASSWORD_SET: - /* Initially we need a new block so bytes_used is equal to block size*/ - pbkdf2->bytes_used = prf_output_length; - pbkdf2->state = PSA_PBKDF2_STATE_OUTPUT; - break; - case PSA_PBKDF2_STATE_OUTPUT: - break; - default: - return PSA_ERROR_BAD_STATE; - } - - while (output_length != 0) { - uint8_t n = prf_output_length - pbkdf2->bytes_used; - if (n > output_length) { - n = (uint8_t) output_length; - } - memcpy(output, pbkdf2->output_block + pbkdf2->bytes_used, n); - output += n; - output_length -= n; - pbkdf2->bytes_used += n; - - if (output_length == 0) { - break; - } - - /* We need a new block */ - pbkdf2->bytes_used = 0; - pbkdf2->block_number++; - - status = psa_key_derivation_pbkdf2_generate_block(pbkdf2, prf_alg, - prf_output_length, - &attributes); - if (status != PSA_SUCCESS) { - return status; - } - } - - return PSA_SUCCESS; -} -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - -psa_status_t psa_key_derivation_output_bytes( - psa_key_derivation_operation_t *operation, - uint8_t *output, - size_t output_length) -{ - psa_status_t status; - psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); - - if (operation->alg == 0) { - /* This is a blank operation. */ - return PSA_ERROR_BAD_STATE; - } - - if (output_length > operation->capacity) { - operation->capacity = 0; - /* Go through the error path to wipe all confidential data now - * that the operation object is useless. */ - status = PSA_ERROR_INSUFFICIENT_DATA; - goto exit; - } - if (output_length == 0 && operation->capacity == 0) { - /* Edge case: this is a finished operation, and 0 bytes - * were requested. The right error in this case could - * be either INSUFFICIENT_CAPACITY or BAD_STATE. Return - * INSUFFICIENT_CAPACITY, which is right for a finished - * operation, for consistency with the case when - * output_length > 0. */ - return PSA_ERROR_INSUFFICIENT_DATA; - } - operation->capacity -= output_length; - -#if defined(BUILTIN_ALG_ANY_HKDF) - if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { - status = psa_key_derivation_hkdf_read(&operation->ctx.hkdf, kdf_alg, - output, output_length); - } else -#endif /* BUILTIN_ALG_ANY_HKDF */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - if (PSA_ALG_IS_TLS12_PRF(kdf_alg) || - PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { - status = psa_key_derivation_tls12_prf_read(&operation->ctx.tls12_prf, - kdf_alg, output, - output_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || - * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - status = psa_key_derivation_tls12_ecjpake_to_pms_read( - &operation->ctx.tls12_ecjpake_to_pms, output, output_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ -#if defined(PSA_HAVE_SOFT_PBKDF2) - if (PSA_ALG_IS_PBKDF2(kdf_alg)) { - status = psa_key_derivation_pbkdf2_read(&operation->ctx.pbkdf2, kdf_alg, - output, output_length); - } else -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - - { - (void) kdf_alg; - return PSA_ERROR_BAD_STATE; - } - -exit: - if (status != PSA_SUCCESS) { - /* Preserve the algorithm upon errors, but clear all sensitive state. - * This allows us to differentiate between exhausted operations and - * blank operations, so we can return PSA_ERROR_BAD_STATE on blank - * operations. */ - psa_algorithm_t alg = operation->alg; - psa_key_derivation_abort(operation); - operation->alg = alg; - memset(output, '!', output_length); - } - return status; -} - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) -static void psa_des_set_key_parity(uint8_t *data, size_t data_size) -{ - if (data_size >= 8) { - mbedtls_des_key_set_parity(data); - } - if (data_size >= 16) { - mbedtls_des_key_set_parity(data + 8); - } - if (data_size >= 24) { - mbedtls_des_key_set_parity(data + 16); - } -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES */ - -/* - * ECC keys on a Weierstrass elliptic curve require the generation - * of a private key which is an integer - * in the range [1, N - 1], where N is the boundary of the private key domain: - * N is the prime p for Diffie-Hellman, or the order of the - * curve’s base point for ECC. - * - * Let m be the bit size of N, such that 2^m > N >= 2^(m-1). - * This function generates the private key using the following process: - * - * 1. Draw a byte string of length ceiling(m/8) bytes. - * 2. If m is not a multiple of 8, set the most significant - * (8 * ceiling(m/8) - m) bits of the first byte in the string to zero. - * 3. Convert the string to integer k by decoding it as a big-endian byte string. - * 4. If k > N - 2, discard the result and return to step 1. - * 5. Output k + 1 as the private key. - * - * This method allows compliance to NIST standards, specifically the methods titled - * Key-Pair Generation by Testing Candidates in the following publications: - * - NIST Special Publication 800-56A: Recommendation for Pair-Wise Key-Establishment - * Schemes Using Discrete Logarithm Cryptography [SP800-56A] §5.6.1.1.4 for - * Diffie-Hellman keys. - * - * - [SP800-56A] §5.6.1.2.2 or FIPS Publication 186-4: Digital Signature - * Standard (DSS) [FIPS186-4] §B.4.2 for elliptic curve keys. - * - * Note: Function allocates memory for *data buffer, so given *data should be - * always NULL. - */ -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) -static psa_status_t psa_generate_derived_ecc_key_weierstrass_helper( - psa_key_slot_t *slot, - size_t bits, - psa_key_derivation_operation_t *operation, - uint8_t **data - ) -{ - unsigned key_out_of_range = 1; - mbedtls_mpi k; - mbedtls_mpi diff_N_2; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t m; - size_t m_bytes; - - mbedtls_mpi_init(&k); - mbedtls_mpi_init(&diff_N_2); - - psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY( - slot->attr.type); - mbedtls_ecp_group_id grp_id = - mbedtls_ecc_group_of_psa(curve, bits, 0); - - if (grp_id == MBEDTLS_ECP_DP_NONE) { - ret = MBEDTLS_ERR_ASN1_INVALID_DATA; - goto cleanup; - } - - mbedtls_ecp_group ecp_group; - mbedtls_ecp_group_init(&ecp_group); - - MBEDTLS_MPI_CHK(mbedtls_ecp_group_load(&ecp_group, grp_id)); - - /* N is the boundary of the private key domain (ecp_group.N). */ - /* Let m be the bit size of N. */ - m = ecp_group.nbits; - - m_bytes = PSA_BITS_TO_BYTES(m); - - /* Calculate N - 2 - it will be needed later. */ - MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&diff_N_2, &ecp_group.N, 2)); - - /* Note: This function is always called with *data == NULL and it - * allocates memory for the data buffer. */ - *data = mbedtls_calloc(1, m_bytes); - if (*data == NULL) { - ret = MBEDTLS_ERR_ASN1_ALLOC_FAILED; - goto cleanup; - } - - while (key_out_of_range) { - /* 1. Draw a byte string of length ceiling(m/8) bytes. */ - if ((status = psa_key_derivation_output_bytes(operation, *data, m_bytes)) != 0) { - goto cleanup; - } - - /* 2. If m is not a multiple of 8 */ - if (m % 8 != 0) { - /* Set the most significant - * (8 * ceiling(m/8) - m) bits of the first byte in - * the string to zero. - */ - uint8_t clear_bit_mask = (1 << (m % 8)) - 1; - (*data)[0] &= clear_bit_mask; - } - - /* 3. Convert the string to integer k by decoding it as a - * big-endian byte string. - */ - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&k, *data, m_bytes)); - - /* 4. If k > N - 2, discard the result and return to step 1. - * Result of comparison is returned. When it indicates error - * then this function is called again. - */ - MBEDTLS_MPI_CHK(mbedtls_mpi_lt_mpi_ct(&diff_N_2, &k, &key_out_of_range)); - } - - /* 5. Output k + 1 as the private key. */ - MBEDTLS_MPI_CHK(mbedtls_mpi_add_int(&k, &k, 1)); - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&k, *data, m_bytes)); -cleanup: - if (ret != 0) { - status = mbedtls_to_psa_error(ret); - } - if (status != PSA_SUCCESS) { - mbedtls_free(*data); - *data = NULL; - } - mbedtls_mpi_free(&k); - mbedtls_mpi_free(&diff_N_2); - return status; -} - -/* ECC keys on a Montgomery elliptic curve draws a byte string whose length - * is determined by the curve, and sets the mandatory bits accordingly. That is: - * - * - Curve25519 (PSA_ECC_FAMILY_MONTGOMERY, 255 bits): - * draw a 32-byte string and process it as specified in - * Elliptic Curves for Security [RFC7748] §5. - * - * - Curve448 (PSA_ECC_FAMILY_MONTGOMERY, 448 bits): - * draw a 56-byte string and process it as specified in [RFC7748] §5. - * - * Note: Function allocates memory for *data buffer, so given *data should be - * always NULL. - */ - -static psa_status_t psa_generate_derived_ecc_key_montgomery_helper( - size_t bits, - psa_key_derivation_operation_t *operation, - uint8_t **data - ) -{ - size_t output_length; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - switch (bits) { - case 255: - output_length = 32; - break; - case 448: - output_length = 56; - break; - default: - return PSA_ERROR_INVALID_ARGUMENT; - break; - } - - *data = mbedtls_calloc(1, output_length); - - if (*data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - status = psa_key_derivation_output_bytes(operation, *data, output_length); - - if (status != PSA_SUCCESS) { - return status; - } - - switch (bits) { - case 255: - (*data)[0] &= 248; - (*data)[31] &= 127; - (*data)[31] |= 64; - break; - case 448: - (*data)[0] &= 252; - (*data)[55] |= 128; - break; - default: - return PSA_ERROR_CORRUPTION_DETECTED; - break; - } - - return status; -} -#else /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ -static psa_status_t psa_generate_derived_ecc_key_weierstrass_helper( - psa_key_slot_t *slot, size_t bits, - psa_key_derivation_operation_t *operation, uint8_t **data) -{ - (void) slot; - (void) bits; - (void) operation; - (void) data; - return PSA_ERROR_NOT_SUPPORTED; -} - -static psa_status_t psa_generate_derived_ecc_key_montgomery_helper( - size_t bits, psa_key_derivation_operation_t *operation, uint8_t **data) -{ - (void) bits; - (void) operation; - (void) data; - return PSA_ERROR_NOT_SUPPORTED; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ -#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ - -static psa_status_t psa_generate_derived_key_internal( - psa_key_slot_t *slot, - size_t bits, - psa_key_derivation_operation_t *operation) -{ - uint8_t *data = NULL; - size_t bytes = PSA_BITS_TO_BYTES(bits); - size_t storage_size = bytes; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_attributes_t attributes; - - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) - if (PSA_KEY_TYPE_IS_ECC(slot->attr.type)) { - psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY(slot->attr.type); - if (PSA_ECC_FAMILY_IS_WEIERSTRASS(curve)) { - /* Weierstrass elliptic curve */ - status = psa_generate_derived_ecc_key_weierstrass_helper(slot, bits, operation, &data); - if (status != PSA_SUCCESS) { - goto exit; - } - } else { - /* Montgomery elliptic curve */ - status = psa_generate_derived_ecc_key_montgomery_helper(bits, operation, &data); - if (status != PSA_SUCCESS) { - goto exit; - } - } - } else -#endif /* defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) */ - if (key_type_is_raw_bytes(slot->attr.type)) { - if (bits % 8 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - data = mbedtls_calloc(1, bytes); - if (data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - status = psa_key_derivation_output_bytes(operation, data, bytes); - if (status != PSA_SUCCESS) { - goto exit; - } -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) - if (slot->attr.type == PSA_KEY_TYPE_DES) { - psa_des_set_key_parity(data, bytes); - } -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) */ - } else { - return PSA_ERROR_NOT_SUPPORTED; - } - - slot->attr.bits = (psa_key_bits_t) bits; - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - if (psa_key_lifetime_is_external(attributes.core.lifetime)) { - status = psa_driver_wrapper_get_key_buffer_size(&attributes, - &storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - } - status = psa_allocate_buffer_to_slot(slot, storage_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_driver_wrapper_import_key(&attributes, - data, bytes, - slot->key.data, - slot->key.bytes, - &slot->key.bytes, &bits); - if (bits != slot->attr.bits) { - status = PSA_ERROR_INVALID_ARGUMENT; - } - -exit: - mbedtls_free(data); - return status; -} - -psa_status_t psa_key_derivation_output_key(const psa_key_attributes_t *attributes, - psa_key_derivation_operation_t *operation, - mbedtls_svc_key_id_t *key) -{ - psa_status_t status; - psa_key_slot_t *slot = NULL; - psa_se_drv_table_entry_t *driver = NULL; - - *key = MBEDTLS_SVC_KEY_ID_INIT; - - /* Reject any attempt to create a zero-length key so that we don't - * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ - if (psa_get_key_bits(attributes) > PSA_MAX_KEY_BITS) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (psa_get_key_bits(attributes) == 0 || - psa_get_key_bits(attributes) % 8 != 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (!key_type_is_raw_bytes(psa_get_key_type(attributes))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (operation->alg == PSA_ALG_NONE) { - return PSA_ERROR_BAD_STATE; - } - - if (!operation->can_output_key) { - return PSA_ERROR_NOT_PERMITTED; - } - - status = psa_start_key_creation(PSA_KEY_CREATION_DERIVE, attributes, - &slot, &driver); -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if (driver != NULL) { - /* Deriving a key in a secure element is not implemented yet. */ - status = PSA_ERROR_NOT_SUPPORTED; - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - if (status == PSA_SUCCESS) { - status = psa_generate_derived_key_internal(slot, - attributes->core.bits, - operation); - } - if (status == PSA_SUCCESS) { - status = psa_finish_key_creation(slot, driver, key); - } - if (status != PSA_SUCCESS) { - psa_fail_key_creation(slot, driver); - } - - return status; -} - - - -/****************************************************************/ -/* Key derivation */ -/****************************************************************/ - -#if defined(AT_LEAST_ONE_BUILTIN_KDF) -static int is_kdf_alg_supported(psa_algorithm_t kdf_alg) -{ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) - if (PSA_ALG_IS_HKDF(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) - if (PSA_ALG_IS_TLS12_PRF(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - if (PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) - if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { - return 1; - } -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) - if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { - return 1; - } -#endif - return 0; -} - -static psa_status_t psa_hash_try_support(psa_algorithm_t alg) -{ - psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; - psa_status_t status = psa_hash_setup(&operation, alg); - psa_hash_abort(&operation); - return status; -} - -static psa_status_t psa_key_derivation_setup_kdf( - psa_key_derivation_operation_t *operation, - psa_algorithm_t kdf_alg) -{ - /* Make sure that operation->ctx is properly zero-initialised. (Macro - * initialisers for this union leave some bytes unspecified.) */ - memset(&operation->ctx, 0, sizeof(operation->ctx)); - - /* Make sure that kdf_alg is a supported key derivation algorithm. */ - if (!is_kdf_alg_supported(kdf_alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* All currently supported key derivation algorithms (apart from - * ecjpake to pms and pbkdf2_aes_cmac_128) are based on a hash algorithm. */ - psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); - size_t hash_size = PSA_HASH_LENGTH(hash_alg); - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - hash_size = PSA_HASH_LENGTH(PSA_ALG_SHA_256); - } else if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { - hash_size = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); - } else { - if (hash_size == 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* Make sure that hash_alg is a supported hash algorithm. Otherwise - * we might fail later, which is somewhat unfriendly and potentially - * risk-prone. */ - psa_status_t status = psa_hash_try_support(hash_alg); - if (status != PSA_SUCCESS) { - return status; - } - } - - if ((PSA_ALG_IS_TLS12_PRF(kdf_alg) || - PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) && - !(hash_alg == PSA_ALG_SHA_256 || hash_alg == PSA_ALG_SHA_384)) { - return PSA_ERROR_NOT_SUPPORTED; - } -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) || - (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS)) { - operation->capacity = hash_size; - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT || - MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ - operation->capacity = 255 * hash_size; - return PSA_SUCCESS; -} - -static psa_status_t psa_key_agreement_try_support(psa_algorithm_t alg) -{ -#if defined(PSA_WANT_ALG_ECDH) - if (alg == PSA_ALG_ECDH) { - return PSA_SUCCESS; - } -#endif -#if defined(PSA_WANT_ALG_FFDH) - if (alg == PSA_ALG_FFDH) { - return PSA_SUCCESS; - } -#endif - (void) alg; - return PSA_ERROR_NOT_SUPPORTED; -} - -static int psa_key_derivation_allows_free_form_secret_input( - psa_algorithm_t kdf_alg) -{ -#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - return 0; - } -#endif - (void) kdf_alg; - return 1; -} -#endif /* AT_LEAST_ONE_BUILTIN_KDF */ - -psa_status_t psa_key_derivation_setup(psa_key_derivation_operation_t *operation, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->alg != 0) { - return PSA_ERROR_BAD_STATE; - } - - if (PSA_ALG_IS_RAW_KEY_AGREEMENT(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } else if (PSA_ALG_IS_KEY_AGREEMENT(alg)) { -#if defined(AT_LEAST_ONE_BUILTIN_KDF) - psa_algorithm_t kdf_alg = PSA_ALG_KEY_AGREEMENT_GET_KDF(alg); - psa_algorithm_t ka_alg = PSA_ALG_KEY_AGREEMENT_GET_BASE(alg); - status = psa_key_agreement_try_support(ka_alg); - if (status != PSA_SUCCESS) { - return status; - } - if (!psa_key_derivation_allows_free_form_secret_input(kdf_alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - status = psa_key_derivation_setup_kdf(operation, kdf_alg); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* AT_LEAST_ONE_BUILTIN_KDF */ - } else if (PSA_ALG_IS_KEY_DERIVATION(alg)) { -#if defined(AT_LEAST_ONE_BUILTIN_KDF) - status = psa_key_derivation_setup_kdf(operation, alg); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* AT_LEAST_ONE_BUILTIN_KDF */ - } else { - status = PSA_ERROR_INVALID_ARGUMENT; - } - - if (status == PSA_SUCCESS) { - operation->alg = alg; - } - return status; -} - -#if defined(BUILTIN_ALG_ANY_HKDF) -static psa_status_t psa_hkdf_input(psa_hkdf_key_derivation_t *hkdf, - psa_algorithm_t kdf_alg, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); - psa_status_t status; - switch (step) { - case PSA_KEY_DERIVATION_INPUT_SALT: -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ - if (hkdf->state != HKDF_STATE_INIT) { - return PSA_ERROR_BAD_STATE; - } else { - status = psa_key_derivation_start_hmac(&hkdf->hmac, - hash_alg, - data, data_length); - if (status != PSA_SUCCESS) { - return status; - } - hkdf->state = HKDF_STATE_STARTED; - return PSA_SUCCESS; - } - case PSA_KEY_DERIVATION_INPUT_SECRET: -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { - /* We shouldn't be in different state as HKDF_EXPAND only allows - * two inputs: SECRET (this case) and INFO which does not modify - * the state. It could happen only if the hkdf - * object was corrupted. */ - if (hkdf->state != HKDF_STATE_INIT) { - return PSA_ERROR_BAD_STATE; - } - - /* Allow only input that fits expected prk size */ - if (data_length != PSA_HASH_LENGTH(hash_alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - memcpy(hkdf->prk, data, data_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ - { - /* HKDF: If no salt was provided, use an empty salt. - * HKDF-EXTRACT: salt is mandatory. */ - if (hkdf->state == HKDF_STATE_INIT) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { - return PSA_ERROR_BAD_STATE; - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ - status = psa_key_derivation_start_hmac(&hkdf->hmac, - hash_alg, - NULL, 0); - if (status != PSA_SUCCESS) { - return status; - } - hkdf->state = HKDF_STATE_STARTED; - } - if (hkdf->state != HKDF_STATE_STARTED) { - return PSA_ERROR_BAD_STATE; - } - status = psa_mac_update(&hkdf->hmac, - data, data_length); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_mac_sign_finish(&hkdf->hmac, - hkdf->prk, - sizeof(hkdf->prk), - &data_length); - if (status != PSA_SUCCESS) { - return status; - } - } - - hkdf->state = HKDF_STATE_KEYED; - hkdf->block_number = 0; -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { - /* The only block of output is the PRK. */ - memcpy(hkdf->output_block, hkdf->prk, PSA_HASH_LENGTH(hash_alg)); - hkdf->offset_in_block = 0; - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ - { - /* Block 0 is empty, and the next block will be - * generated by psa_key_derivation_hkdf_read(). */ - hkdf->offset_in_block = PSA_HASH_LENGTH(hash_alg); - } - - return PSA_SUCCESS; - case PSA_KEY_DERIVATION_INPUT_INFO: -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) - if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) - if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg) && - hkdf->state == HKDF_STATE_INIT) { - return PSA_ERROR_BAD_STATE; - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ - if (hkdf->state == HKDF_STATE_OUTPUT) { - return PSA_ERROR_BAD_STATE; - } - if (hkdf->info_set) { - return PSA_ERROR_BAD_STATE; - } - hkdf->info_length = data_length; - if (data_length != 0) { - hkdf->info = mbedtls_calloc(1, data_length); - if (hkdf->info == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memcpy(hkdf->info, data, data_length); - } - hkdf->info_set = 1; - return PSA_SUCCESS; - default: - return PSA_ERROR_INVALID_ARGUMENT; - } -} -#endif /* BUILTIN_ALG_ANY_HKDF */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) -static psa_status_t psa_tls12_prf_set_seed(psa_tls12_prf_key_derivation_t *prf, - const uint8_t *data, - size_t data_length) -{ - if (prf->state != PSA_TLS12_PRF_STATE_INIT) { - return PSA_ERROR_BAD_STATE; - } - - if (data_length != 0) { - prf->seed = mbedtls_calloc(1, data_length); - if (prf->seed == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - memcpy(prf->seed, data, data_length); - prf->seed_length = data_length; - } - - prf->state = PSA_TLS12_PRF_STATE_SEED_SET; - - return PSA_SUCCESS; -} - -static psa_status_t psa_tls12_prf_set_key(psa_tls12_prf_key_derivation_t *prf, - const uint8_t *data, - size_t data_length) -{ - if (prf->state != PSA_TLS12_PRF_STATE_SEED_SET && - prf->state != PSA_TLS12_PRF_STATE_OTHER_KEY_SET) { - return PSA_ERROR_BAD_STATE; - } - - if (data_length != 0) { - prf->secret = mbedtls_calloc(1, data_length); - if (prf->secret == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - memcpy(prf->secret, data, data_length); - prf->secret_length = data_length; - } - - prf->state = PSA_TLS12_PRF_STATE_KEY_SET; - - return PSA_SUCCESS; -} - -static psa_status_t psa_tls12_prf_set_label(psa_tls12_prf_key_derivation_t *prf, - const uint8_t *data, - size_t data_length) -{ - if (prf->state != PSA_TLS12_PRF_STATE_KEY_SET) { - return PSA_ERROR_BAD_STATE; - } - - if (data_length != 0) { - prf->label = mbedtls_calloc(1, data_length); - if (prf->label == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - memcpy(prf->label, data, data_length); - prf->label_length = data_length; - } - - prf->state = PSA_TLS12_PRF_STATE_LABEL_SET; - - return PSA_SUCCESS; -} - -static psa_status_t psa_tls12_prf_input(psa_tls12_prf_key_derivation_t *prf, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - switch (step) { - case PSA_KEY_DERIVATION_INPUT_SEED: - return psa_tls12_prf_set_seed(prf, data, data_length); - case PSA_KEY_DERIVATION_INPUT_SECRET: - return psa_tls12_prf_set_key(prf, data, data_length); - case PSA_KEY_DERIVATION_INPUT_LABEL: - return psa_tls12_prf_set_label(prf, data, data_length); - default: - return PSA_ERROR_INVALID_ARGUMENT; - } -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || - * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) -static psa_status_t psa_tls12_prf_psk_to_ms_set_key( - psa_tls12_prf_key_derivation_t *prf, - const uint8_t *data, - size_t data_length) -{ - psa_status_t status; - const size_t pms_len = (prf->state == PSA_TLS12_PRF_STATE_OTHER_KEY_SET ? - 4 + data_length + prf->other_secret_length : - 4 + 2 * data_length); - - if (data_length > PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - uint8_t *pms = mbedtls_calloc(1, pms_len); - if (pms == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - uint8_t *cur = pms; - - /* pure-PSK: - * Quoting RFC 4279, Section 2: - * - * The premaster secret is formed as follows: if the PSK is N octets - * long, concatenate a uint16 with the value N, N zero octets, a second - * uint16 with the value N, and the PSK itself. - * - * mixed-PSK: - * In a DHE-PSK, RSA-PSK, ECDHE-PSK the premaster secret is formed as - * follows: concatenate a uint16 with the length of the other secret, - * the other secret itself, uint16 with the length of PSK, and the - * PSK itself. - * For details please check: - * - RFC 4279, Section 4 for the definition of RSA-PSK, - * - RFC 4279, Section 3 for the definition of DHE-PSK, - * - RFC 5489 for the definition of ECDHE-PSK. - */ - - if (prf->state == PSA_TLS12_PRF_STATE_OTHER_KEY_SET) { - *cur++ = MBEDTLS_BYTE_1(prf->other_secret_length); - *cur++ = MBEDTLS_BYTE_0(prf->other_secret_length); - if (prf->other_secret_length != 0) { - memcpy(cur, prf->other_secret, prf->other_secret_length); - mbedtls_platform_zeroize(prf->other_secret, prf->other_secret_length); - cur += prf->other_secret_length; - } - } else { - *cur++ = MBEDTLS_BYTE_1(data_length); - *cur++ = MBEDTLS_BYTE_0(data_length); - memset(cur, 0, data_length); - cur += data_length; - } - - *cur++ = MBEDTLS_BYTE_1(data_length); - *cur++ = MBEDTLS_BYTE_0(data_length); - memcpy(cur, data, data_length); - cur += data_length; - - status = psa_tls12_prf_set_key(prf, pms, cur - pms); - - mbedtls_zeroize_and_free(pms, pms_len); - return status; -} - -static psa_status_t psa_tls12_prf_psk_to_ms_set_other_key( - psa_tls12_prf_key_derivation_t *prf, - const uint8_t *data, - size_t data_length) -{ - if (prf->state != PSA_TLS12_PRF_STATE_SEED_SET) { - return PSA_ERROR_BAD_STATE; - } - - if (data_length != 0) { - prf->other_secret = mbedtls_calloc(1, data_length); - if (prf->other_secret == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - memcpy(prf->other_secret, data, data_length); - prf->other_secret_length = data_length; - } else { - prf->other_secret_length = 0; - } - - prf->state = PSA_TLS12_PRF_STATE_OTHER_KEY_SET; - - return PSA_SUCCESS; -} - -static psa_status_t psa_tls12_prf_psk_to_ms_input( - psa_tls12_prf_key_derivation_t *prf, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - switch (step) { - case PSA_KEY_DERIVATION_INPUT_SECRET: - return psa_tls12_prf_psk_to_ms_set_key(prf, - data, data_length); - break; - case PSA_KEY_DERIVATION_INPUT_OTHER_SECRET: - return psa_tls12_prf_psk_to_ms_set_other_key(prf, - data, - data_length); - break; - default: - return psa_tls12_prf_input(prf, step, data, data_length); - break; - - } -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) -static psa_status_t psa_tls12_ecjpake_to_pms_input( - psa_tls12_ecjpake_to_pms_t *ecjpake, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - if (data_length != PSA_TLS12_ECJPAKE_TO_PMS_INPUT_SIZE || - step != PSA_KEY_DERIVATION_INPUT_SECRET) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* Check if the passed point is in an uncompressed form */ - if (data[0] != 0x04) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* Only K.X has to be extracted - bytes 1 to 32 inclusive. */ - memcpy(ecjpake->data, data + 1, PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE); - - return PSA_SUCCESS; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ - -#if defined(PSA_HAVE_SOFT_PBKDF2) -static psa_status_t psa_pbkdf2_set_input_cost( - psa_pbkdf2_key_derivation_t *pbkdf2, - psa_key_derivation_step_t step, - uint64_t data) -{ - if (step != PSA_KEY_DERIVATION_INPUT_COST) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (pbkdf2->state != PSA_PBKDF2_STATE_INIT) { - return PSA_ERROR_BAD_STATE; - } - - if (data > PSA_VENDOR_PBKDF2_MAX_ITERATIONS) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (data == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - pbkdf2->input_cost = data; - pbkdf2->state = PSA_PBKDF2_STATE_INPUT_COST_SET; - - return PSA_SUCCESS; -} - -static psa_status_t psa_pbkdf2_set_salt(psa_pbkdf2_key_derivation_t *pbkdf2, - const uint8_t *data, - size_t data_length) -{ - if (pbkdf2->state == PSA_PBKDF2_STATE_INPUT_COST_SET) { - pbkdf2->state = PSA_PBKDF2_STATE_SALT_SET; - } else if (pbkdf2->state == PSA_PBKDF2_STATE_SALT_SET) { - /* Appending to existing salt. No state change. */ - } else { - return PSA_ERROR_BAD_STATE; - } - - if (data_length == 0) { - /* Appending an empty string, nothing to do. */ - } else { - uint8_t *next_salt; - - next_salt = mbedtls_calloc(1, data_length + pbkdf2->salt_length); - if (next_salt == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - if (pbkdf2->salt_length != 0) { - memcpy(next_salt, pbkdf2->salt, pbkdf2->salt_length); - } - memcpy(next_salt + pbkdf2->salt_length, data, data_length); - pbkdf2->salt_length += data_length; - mbedtls_free(pbkdf2->salt); - pbkdf2->salt = next_salt; - } - return PSA_SUCCESS; -} - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) -static psa_status_t psa_pbkdf2_hmac_set_password(psa_algorithm_t hash_alg, - const uint8_t *input, - size_t input_len, - uint8_t *output, - size_t *output_len) -{ - psa_status_t status = PSA_SUCCESS; - if (input_len > PSA_HASH_BLOCK_LENGTH(hash_alg)) { - status = psa_hash_compute(hash_alg, input, input_len, output, - PSA_HMAC_MAX_HASH_BLOCK_SIZE, output_len); - } else { - memcpy(output, input, input_len); - *output_len = PSA_HASH_BLOCK_LENGTH(hash_alg); - } - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) -static psa_status_t psa_pbkdf2_cmac_set_password(const uint8_t *input, - size_t input_len, - uint8_t *output, - size_t *output_len) -{ - psa_status_t status = PSA_SUCCESS; - if (input_len != PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC)) { - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - uint8_t zeros[16] = { 0 }; - psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); - psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(sizeof(zeros))); - psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_MESSAGE); - /* Passing PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC) as - * mac_size as the driver function sets mac_output_length = mac_size - * on success. See https://github.com/Mbed-TLS/mbedtls/issues/7801 */ - status = psa_driver_wrapper_mac_compute(&attributes, - zeros, sizeof(zeros), - PSA_ALG_CMAC, input, input_len, - output, - PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, - 128U, - PSA_ALG_CMAC), - output_len); - } else { - memcpy(output, input, input_len); - *output_len = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); - } - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 */ - -static psa_status_t psa_pbkdf2_set_password(psa_pbkdf2_key_derivation_t *pbkdf2, - psa_algorithm_t kdf_alg, - const uint8_t *data, - size_t data_length) -{ - psa_status_t status = PSA_SUCCESS; - if (pbkdf2->state != PSA_PBKDF2_STATE_SALT_SET) { - return PSA_ERROR_BAD_STATE; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) - if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { - psa_algorithm_t hash_alg = PSA_ALG_PBKDF2_HMAC_GET_HASH(kdf_alg); - status = psa_pbkdf2_hmac_set_password(hash_alg, data, data_length, - pbkdf2->password, - &pbkdf2->password_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) - if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { - status = psa_pbkdf2_cmac_set_password(data, data_length, - pbkdf2->password, - &pbkdf2->password_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 */ - { - return PSA_ERROR_INVALID_ARGUMENT; - } - - pbkdf2->state = PSA_PBKDF2_STATE_PASSWORD_SET; - - return status; -} - -static psa_status_t psa_pbkdf2_input(psa_pbkdf2_key_derivation_t *pbkdf2, - psa_algorithm_t kdf_alg, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - switch (step) { - case PSA_KEY_DERIVATION_INPUT_SALT: - return psa_pbkdf2_set_salt(pbkdf2, data, data_length); - case PSA_KEY_DERIVATION_INPUT_PASSWORD: - return psa_pbkdf2_set_password(pbkdf2, kdf_alg, data, data_length); - default: - return PSA_ERROR_INVALID_ARGUMENT; - } -} -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - -/** Check whether the given key type is acceptable for the given - * input step of a key derivation. - * - * Secret inputs must have the type #PSA_KEY_TYPE_DERIVE. - * Non-secret inputs must have the type #PSA_KEY_TYPE_RAW_DATA. - * Both secret and non-secret inputs can alternatively have the type - * #PSA_KEY_TYPE_NONE, which is never the type of a key object, meaning - * that the input was passed as a buffer rather than via a key object. - */ -static int psa_key_derivation_check_input_type( - psa_key_derivation_step_t step, - psa_key_type_t key_type) -{ - switch (step) { - case PSA_KEY_DERIVATION_INPUT_SECRET: - if (key_type == PSA_KEY_TYPE_DERIVE) { - return PSA_SUCCESS; - } - if (key_type == PSA_KEY_TYPE_NONE) { - return PSA_SUCCESS; - } - break; - case PSA_KEY_DERIVATION_INPUT_OTHER_SECRET: - if (key_type == PSA_KEY_TYPE_DERIVE) { - return PSA_SUCCESS; - } - if (key_type == PSA_KEY_TYPE_NONE) { - return PSA_SUCCESS; - } - break; - case PSA_KEY_DERIVATION_INPUT_LABEL: - case PSA_KEY_DERIVATION_INPUT_SALT: - case PSA_KEY_DERIVATION_INPUT_INFO: - case PSA_KEY_DERIVATION_INPUT_SEED: - if (key_type == PSA_KEY_TYPE_RAW_DATA) { - return PSA_SUCCESS; - } - if (key_type == PSA_KEY_TYPE_NONE) { - return PSA_SUCCESS; - } - break; - case PSA_KEY_DERIVATION_INPUT_PASSWORD: - if (key_type == PSA_KEY_TYPE_PASSWORD) { - return PSA_SUCCESS; - } - if (key_type == PSA_KEY_TYPE_DERIVE) { - return PSA_SUCCESS; - } - if (key_type == PSA_KEY_TYPE_NONE) { - return PSA_SUCCESS; - } - break; - } - return PSA_ERROR_INVALID_ARGUMENT; -} - -static psa_status_t psa_key_derivation_input_internal( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - psa_key_type_t key_type, - const uint8_t *data, - size_t data_length) -{ - psa_status_t status; - psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); - - status = psa_key_derivation_check_input_type(step, key_type); - if (status != PSA_SUCCESS) { - goto exit; - } - -#if defined(BUILTIN_ALG_ANY_HKDF) - if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { - status = psa_hkdf_input(&operation->ctx.hkdf, kdf_alg, - step, data, data_length); - } else -#endif /* BUILTIN_ALG_ANY_HKDF */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) - if (PSA_ALG_IS_TLS12_PRF(kdf_alg)) { - status = psa_tls12_prf_input(&operation->ctx.tls12_prf, - step, data, data_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) - if (PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { - status = psa_tls12_prf_psk_to_ms_input(&operation->ctx.tls12_prf, - step, data, data_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) - if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { - status = psa_tls12_ecjpake_to_pms_input( - &operation->ctx.tls12_ecjpake_to_pms, step, data, data_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ -#if defined(PSA_HAVE_SOFT_PBKDF2) - if (PSA_ALG_IS_PBKDF2(kdf_alg)) { - status = psa_pbkdf2_input(&operation->ctx.pbkdf2, kdf_alg, - step, data, data_length); - } else -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - { - /* This can't happen unless the operation object was not initialized */ - (void) data; - (void) data_length; - (void) kdf_alg; - return PSA_ERROR_BAD_STATE; - } - -exit: - if (status != PSA_SUCCESS) { - psa_key_derivation_abort(operation); - } - return status; -} - -static psa_status_t psa_key_derivation_input_integer_internal( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - uint64_t value) -{ - psa_status_t status; - psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); - -#if defined(PSA_HAVE_SOFT_PBKDF2) - if (PSA_ALG_IS_PBKDF2(kdf_alg)) { - status = psa_pbkdf2_set_input_cost( - &operation->ctx.pbkdf2, step, value); - } else -#endif /* PSA_HAVE_SOFT_PBKDF2 */ - { - (void) step; - (void) value; - (void) kdf_alg; - status = PSA_ERROR_INVALID_ARGUMENT; - } - - if (status != PSA_SUCCESS) { - psa_key_derivation_abort(operation); - } - return status; -} - -psa_status_t psa_key_derivation_input_bytes( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - const uint8_t *data, - size_t data_length) -{ - return psa_key_derivation_input_internal(operation, step, - PSA_KEY_TYPE_NONE, - data, data_length); -} - -psa_status_t psa_key_derivation_input_integer( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - uint64_t value) -{ - return psa_key_derivation_input_integer_internal(operation, step, value); -} - -psa_status_t psa_key_derivation_input_key( - psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t key) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - status = psa_get_and_lock_transparent_key_slot_with_policy( - key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg); - if (status != PSA_SUCCESS) { - psa_key_derivation_abort(operation); - return status; - } - - /* Passing a key object as a SECRET or PASSWORD input unlocks the - * permission to output to a key object. */ - if (step == PSA_KEY_DERIVATION_INPUT_SECRET || - step == PSA_KEY_DERIVATION_INPUT_PASSWORD) { - operation->can_output_key = 1; - } - - status = psa_key_derivation_input_internal(operation, - step, slot->attr.type, - slot->key.data, - slot->key.bytes); - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) - -#include "sli_psa_driver_features.h" - -psa_status_t sli_se_driver_single_shot_hkdf( - psa_algorithm_t alg, - const psa_key_attributes_t *key_in_attributes, - const uint8_t *key_in_buffer, - size_t key_in_buffer_size, - const uint8_t* info, - size_t info_length, - const uint8_t* salt, - size_t salt_length, - const psa_key_attributes_t *key_out_attributes, - uint8_t *key_out_buffer, - size_t key_out_buffer_size); - -psa_status_t sli_se_driver_single_shot_pbkdf2( - psa_algorithm_t alg, - const psa_key_attributes_t *key_in_attributes, - const uint8_t *key_in_buffer, - size_t key_in_buffer_size, - const uint8_t* salt, - size_t salt_length, - const psa_key_attributes_t *key_out_attributes, - uint32_t iterations, - uint8_t *key_out_buffer, - size_t key_out_buffer_size); - -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) -psa_status_t sli_cryptoacc_driver_single_shot_pbkdf2( - psa_algorithm_t alg, - const psa_key_attributes_t *key_in_attributes, - const uint8_t *key_in_buffer, - size_t key_in_buffer_size, - const uint8_t* salt, - size_t salt_length, - const psa_key_attributes_t *key_out_attributes, - uint32_t iterations, - uint8_t *key_out_buffer, - size_t key_out_buffer_size); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - -psa_status_t sl_psa_key_derivation_single_shot( - psa_algorithm_t alg, - mbedtls_svc_key_id_t key_in, - const uint8_t *info, - size_t info_length, - const uint8_t *salt, - size_t salt_length, - size_t iterations, - const psa_key_attributes_t *key_out_attributes, - mbedtls_svc_key_id_t *key_out ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *input_key_slot = NULL; - psa_key_slot_t *output_key_slot = NULL; - psa_se_drv_table_entry_t *driver = NULL; - *key_out = MBEDTLS_SVC_KEY_ID_INIT; - size_t storage_size = 0; - - /* Reject any attempt to create a zero-length key so that we don't - * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ - if( psa_get_key_bits( key_out_attributes ) == 0 ) - return( PSA_ERROR_INVALID_ARGUMENT ); - - status = psa_get_and_lock_key_slot_with_policy( - key_in, &input_key_slot, PSA_KEY_USAGE_DERIVE, alg ); - if( status != PSA_SUCCESS ) - return( status ); - - status = psa_start_key_creation( PSA_KEY_CREATION_DERIVE, key_out_attributes, - &output_key_slot, &driver ); - if( status != PSA_SUCCESS ) - goto exit; - - status = psa_driver_wrapper_get_key_buffer_size( key_out_attributes, &storage_size ); - if( status != PSA_SUCCESS ) - goto exit; - - /* In the case of a transparent key or an opaque key stored in local - * storage (thus not in the case of generating a key in a secure element - * or cryptoprocessor with storage), we have to allocate a buffer to - * hold the generated key material. */ - if( output_key_slot->key.data == NULL ) - { - status = psa_allocate_buffer_to_slot( output_key_slot, storage_size ); - if( status != PSA_SUCCESS ) - goto exit; - } - - { - psa_key_attributes_t key_in_attributes = { - .core = input_key_slot->attr - }; - - /* Call the appropriate driver. Since this function is used exclusively with - * the SE as an accelerator, we can skip the wrapper layer and call the - * driver functions directly. */ - if (PSA_ALG_IS_HKDF(alg)) -#if defined(SLI_PSA_DRIVER_FEATURE_HKDF) - { - status = sli_se_driver_single_shot_hkdf( - alg, &key_in_attributes, input_key_slot->key.data, - input_key_slot->key.bytes, info, info_length, salt, salt_length, - key_out_attributes, output_key_slot->key.data, - output_key_slot->key.bytes); - } -#else /* SLI_PSA_DRIVER_FEATURE_HKDF */ - { - (void)info; - (void)info_length; - (void)salt; - (void)salt_length; - (void)key_in_attributes; - - status = PSA_ERROR_NOT_SUPPORTED; - } -#endif /* SLI_PSA_DRIVER_FEATURE_HKDF */ - else if ( (PSA_ALG_IS_PBKDF2_HMAC(alg) || (alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128)) ) -#if defined(SLI_PSA_DRIVER_FEATURE_PBKDF2) -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - { - if (alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) - { - status = sli_cryptoacc_driver_single_shot_pbkdf2( - alg, &key_in_attributes, input_key_slot->key.data, - input_key_slot->key.bytes, salt, salt_length, - key_out_attributes, iterations, output_key_slot->key.data, - output_key_slot->key.bytes); - } - else - { - (void)salt; - (void)salt_length; - (void)iterations; - (void)key_in_attributes; - - status = PSA_ERROR_NOT_SUPPORTED; - } - } -#else /* SLI_MBEDTLS_DEVICE_VSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ - { - status = sli_se_driver_single_shot_pbkdf2( - alg, &key_in_attributes, input_key_slot->key.data, - input_key_slot->key.bytes, salt, salt_length, - key_out_attributes, iterations, output_key_slot->key.data, - output_key_slot->key.bytes); - } -#endif /* SLI_MBEDTLS_DEVICE_VSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#else /* SLI_PSA_DRIVER_FEATURE_PBKDF2 */ - { - (void)salt; - (void)salt_length; - (void)iterations; - (void)key_in_attributes; - - status = PSA_ERROR_NOT_SUPPORTED; - } -#endif /* SLI_PSA_DRIVER_FEATURE_PBKDF2 */ - else - { - status = PSA_ERROR_NOT_SUPPORTED; - } - } - -exit: - - /* Finish (or fail) key creation. */ - if( status == PSA_SUCCESS ) - status = psa_finish_key_creation( output_key_slot, driver, key_out ); - if( status != PSA_SUCCESS ) - psa_fail_key_creation( output_key_slot, driver ); - - /* Release input key slot. */ - unlock_status = psa_unlock_key_slot( input_key_slot ); - - return( ( status == PSA_SUCCESS ) ? unlock_status : status ); -} - - - -/****************************************************************/ -/* Key agreement */ -/****************************************************************/ - -psa_status_t psa_key_agreement_raw_builtin(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length) -{ - switch (alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) - case PSA_ALG_ECDH: - return mbedtls_psa_key_agreement_ecdh(attributes, key_buffer, - key_buffer_size, alg, - peer_key, peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) - case PSA_ALG_FFDH: - return mbedtls_psa_ffdh_key_agreement(attributes, - peer_key, - peer_key_length, - key_buffer, - key_buffer_size, - shared_secret, - shared_secret_size, - shared_secret_length); -#endif /* MBEDTLS_PSA_BUILTIN_ALG_FFDH */ - - default: - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) peer_key; - (void) peer_key_length; - (void) shared_secret; - (void) shared_secret_size; - (void) shared_secret_length; - return PSA_ERROR_NOT_SUPPORTED; - } -} - -/** Internal function for raw key agreement - * Calls the driver wrapper which will hand off key agreement task - * to the driver's implementation if a driver is present. - * Fallback specified in the driver wrapper is built-in raw key agreement - * (psa_key_agreement_raw_builtin). - */ -static psa_status_t psa_key_agreement_raw_internal(psa_algorithm_t alg, - psa_key_slot_t *private_key, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length) -{ - if (!PSA_ALG_IS_RAW_KEY_AGREEMENT(alg)) { - return PSA_ERROR_NOT_SUPPORTED; - } - - psa_key_attributes_t attributes = { - .core = private_key->attr - }; - - return psa_driver_wrapper_key_agreement(&attributes, - private_key->key.data, - private_key->key.bytes, alg, - peer_key, peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length); -} - -/* Note that if this function fails, you must call psa_key_derivation_abort() - * to potentially free embedded data structures and wipe confidential data. - */ -static psa_status_t psa_key_agreement_internal(psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - psa_key_slot_t *private_key, - const uint8_t *peer_key, - size_t peer_key_length) -{ - psa_status_t status; - uint8_t shared_secret[PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE]; - size_t shared_secret_length = 0; - psa_algorithm_t ka_alg = PSA_ALG_KEY_AGREEMENT_GET_BASE(operation->alg); - - /* Step 1: run the secret agreement algorithm to generate the shared - * secret. */ - status = psa_key_agreement_raw_internal(ka_alg, - private_key, - peer_key, peer_key_length, - shared_secret, - sizeof(shared_secret), - &shared_secret_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Step 2: set up the key derivation to generate key material from - * the shared secret. A shared secret is permitted wherever a key - * of type DERIVE is permitted. */ - status = psa_key_derivation_input_internal(operation, step, - PSA_KEY_TYPE_DERIVE, - shared_secret, - shared_secret_length); -exit: - mbedtls_platform_zeroize(shared_secret, shared_secret_length); - return status; -} - -psa_status_t psa_key_derivation_key_agreement(psa_key_derivation_operation_t *operation, - psa_key_derivation_step_t step, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot; - - if (!PSA_ALG_IS_KEY_AGREEMENT(operation->alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - status = psa_get_and_lock_key_slot_with_policy( - private_key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_key_agreement_internal(operation, step, - slot, - peer_key, peer_key_length); - if (status != PSA_SUCCESS) { - psa_key_derivation_abort(operation); - } else { - /* If a private key has been added as SECRET, we allow the derived - * key material to be used as a key in PSA Crypto. */ - if (step == PSA_KEY_DERIVATION_INPUT_SECRET) { - operation->can_output_key = 1; - } - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, - mbedtls_svc_key_id_t private_key, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - size_t expected_length; - - if (!PSA_ALG_IS_KEY_AGREEMENT(alg)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - status = psa_get_and_lock_key_slot_with_policy( - private_key, &slot, PSA_KEY_USAGE_DERIVE, alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() is in general an upper bound - * for the output size. The PSA specification only guarantees that this - * function works if output_size >= PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(...), - * but it might be nice to allow smaller buffers if the output fits. - * At the time of writing this comment, with only ECDH implemented, - * PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() is exact so the point is moot. - * If FFDH is implemented, PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() can easily - * be exact for it as well. */ - expected_length = - PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(slot->attr.type, slot->attr.bits); - if (output_size < expected_length) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - status = psa_key_agreement_raw_internal(alg, slot, - peer_key, peer_key_length, - output, output_size, - output_length); - -exit: - if (status != PSA_SUCCESS) { - /* If an error happens and is not handled properly, the output - * may be used as a key to protect sensitive data. Arrange for such - * a key to be random, which is likely to result in decryption or - * verification errors. This is better than filling the buffer with - * some constant data such as zeros, which would result in the data - * being protected with a reproducible, easily knowable key. - */ - psa_generate_random(output, output_size); - *output_length = output_size; - } - - unlock_status = psa_unlock_key_slot(slot); - - return (status == PSA_SUCCESS) ? unlock_status : status; -} - - - -/****************************************************************/ -/* Random generation */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) -#include "entropy_poll.h" -#endif - -/** Initialize the PSA random generator. - */ -static void mbedtls_psa_random_init(mbedtls_psa_random_context_t *rng) -{ -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - memset(rng, 0, sizeof(*rng)); -#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - - /* Set default configuration if - * mbedtls_psa_crypto_configure_entropy_sources() hasn't been called. */ - if (rng->entropy_init == NULL) { - rng->entropy_init = mbedtls_entropy_init; - } - if (rng->entropy_free == NULL) { - rng->entropy_free = mbedtls_entropy_free; - } - - rng->entropy_init(&rng->entropy); -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ - defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) - /* The PSA entropy injection feature depends on using NV seed as an entropy - * source. Add NV seed as an entropy source for PSA entropy injection. */ - mbedtls_entropy_add_source(&rng->entropy, - mbedtls_nv_seed_poll, NULL, - MBEDTLS_ENTROPY_BLOCK_SIZE, - MBEDTLS_ENTROPY_SOURCE_STRONG); -#endif - - mbedtls_psa_drbg_init(MBEDTLS_PSA_RANDOM_STATE); -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ -} - -/** Deinitialize the PSA random generator. - */ -static void mbedtls_psa_random_free(mbedtls_psa_random_context_t *rng) -{ -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - memset(rng, 0, sizeof(*rng)); -#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - mbedtls_psa_drbg_free(MBEDTLS_PSA_RANDOM_STATE); - rng->entropy_free(&rng->entropy); -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ -} - -/** Seed the PSA random generator. - */ -static psa_status_t mbedtls_psa_random_seed(mbedtls_psa_random_context_t *rng) -{ -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - /* Do nothing: the external RNG seeds itself. */ - (void) rng; - return PSA_SUCCESS; -#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - const unsigned char drbg_seed[] = "PSA"; - int ret = mbedtls_psa_drbg_seed(&rng->entropy, - drbg_seed, sizeof(drbg_seed) - 1); - return mbedtls_to_psa_error(ret); -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ -} - -psa_status_t psa_generate_random(uint8_t *output, - size_t output_size) -{ - GUARD_MODULE_INITIALIZED; - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - - size_t output_length = 0; - psa_status_t status = mbedtls_psa_external_get_random(&global_data.rng, - output, output_size, - &output_length); - if (status != PSA_SUCCESS) { - return status; - } - /* Breaking up a request into smaller chunks is currently not supported - * for the external RNG interface. */ - if (output_length != output_size) { - return PSA_ERROR_INSUFFICIENT_ENTROPY; - } - return PSA_SUCCESS; - -#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - - while (output_size > 0) { - size_t request_size = - (output_size > MBEDTLS_PSA_RANDOM_MAX_REQUEST ? - MBEDTLS_PSA_RANDOM_MAX_REQUEST : - output_size); - int ret = mbedtls_psa_get_random(MBEDTLS_PSA_RANDOM_STATE, - output, request_size); - if (ret != 0) { - return mbedtls_to_psa_error(ret); - } - output_size -= request_size; - output += request_size; - } - return PSA_SUCCESS; -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ -} - -/* Wrapper function allowing the classic API to use the PSA RNG. - * - * `mbedtls_psa_get_random(MBEDTLS_PSA_RANDOM_STATE, ...)` calls - * `psa_generate_random(...)`. The state parameter is ignored since the - * PSA API doesn't support passing an explicit state. - * - * In the non-external case, psa_generate_random() calls an - * `mbedtls_xxx_drbg_random` function which has exactly the same signature - * and semantics as mbedtls_psa_get_random(). As an optimization, - * instead of doing this back-and-forth between the PSA API and the - * classic API, psa_crypto_random_impl.h defines `mbedtls_psa_get_random` - * as a constant function pointer to `mbedtls_xxx_drbg_random`. - */ -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -int mbedtls_psa_get_random(void *p_rng, - unsigned char *output, - size_t output_size) -{ - /* This function takes a pointer to the RNG state because that's what - * classic mbedtls functions using an RNG expect. The PSA RNG manages - * its own state internally and doesn't let the caller access that state. - * So we just ignore the state parameter, and in practice we'll pass - * NULL. */ - (void) p_rng; - psa_status_t status = psa_generate_random(output, output_size); - if (status == PSA_SUCCESS) { - return 0; - } else { - return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; - } -} -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) -psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, - size_t seed_size) -{ - if (global_data.initialized) { - return PSA_ERROR_NOT_PERMITTED; - } - - if (((seed_size < MBEDTLS_ENTROPY_MIN_PLATFORM) || - (seed_size < MBEDTLS_ENTROPY_BLOCK_SIZE)) || - (seed_size > MBEDTLS_ENTROPY_MAX_SEED_SIZE)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return mbedtls_psa_storage_inject_entropy(seed, seed_size); -} -#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ - -/** Validate the key type and size for key generation - * - * \param type The key type - * \param bits The number of bits of the key - * - * \retval #PSA_SUCCESS - * The key type and size are valid. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size in bits of the key is not valid. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The type and/or the size in bits of the key or the combination of - * the two is not supported. - */ -static psa_status_t psa_validate_key_type_and_size_for_key_generation( - psa_key_type_t type, size_t bits) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (key_type_is_raw_bytes(type)) { - status = psa_validate_unstructured_key_bit_size(type, bits); - if (status != PSA_SUCCESS) { - return status; - } - } else -#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) - if (PSA_KEY_TYPE_IS_RSA(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - if (bits > PSA_VENDOR_RSA_MAX_KEY_BITS) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (bits < PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* Accept only byte-aligned keys, for the same reasons as - * in psa_import_rsa_key(). */ - if (bits % 8 != 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - } else -#endif /* defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ - -#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) - if (PSA_KEY_TYPE_IS_ECC(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - /* To avoid empty block, return successfully here. */ - return PSA_SUCCESS; - } else -#endif /* defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) */ - -#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) - if (PSA_KEY_TYPE_IS_DH(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - if (psa_is_dh_key_size_valid(bits) == 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - } else -#endif /* defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) */ - { - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; -} - -psa_status_t psa_generate_key_internal( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_type_t type = attributes->core.type; - - if ((attributes->domain_parameters == NULL) && - (attributes->domain_parameters_size != 0)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (key_type_is_raw_bytes(type)) { - status = psa_generate_random(key_buffer, key_buffer_size); - if (status != PSA_SUCCESS) { - return status; - } - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) - if (type == PSA_KEY_TYPE_DES) { - psa_des_set_key_parity(key_buffer, key_buffer_size); - } -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES */ - } else - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) - if (type == PSA_KEY_TYPE_RSA_KEY_PAIR) { - return mbedtls_psa_rsa_generate_key(attributes, - key_buffer, - key_buffer_size, - key_buffer_length); - } else -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) - if (PSA_KEY_TYPE_IS_ECC(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - return mbedtls_psa_ecp_generate_key(attributes, - key_buffer, - key_buffer_size, - key_buffer_length); - } else -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) - if (PSA_KEY_TYPE_IS_DH(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - return mbedtls_psa_ffdh_generate_key(attributes, - key_buffer, - key_buffer_size, - key_buffer_length); - } else -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) */ - { - (void) key_buffer_length; - return PSA_ERROR_NOT_SUPPORTED; - } - - return PSA_SUCCESS; -} - -psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, - mbedtls_svc_key_id_t *key) -{ - psa_status_t status; - psa_key_slot_t *slot = NULL; - psa_se_drv_table_entry_t *driver = NULL; - size_t key_buffer_size; - - *key = MBEDTLS_SVC_KEY_ID_INIT; - - /* Reject any attempt to create a zero-length key so that we don't - * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ - if (psa_get_key_bits(attributes) == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - /* Reject any attempt to create a public key. */ - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(attributes->core.type)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = psa_start_key_creation(PSA_KEY_CREATION_GENERATE, attributes, - &slot, &driver); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* In the case of a transparent key or an opaque key stored in local - * storage ( thus not in the case of generating a key in a secure element - * with storage ( MBEDTLS_PSA_CRYPTO_SE_C ) ),we have to allocate a - * buffer to hold the generated key material. */ - if (slot->key.data == NULL) { - if (PSA_KEY_LIFETIME_GET_LOCATION(attributes->core.lifetime) == - PSA_KEY_LOCATION_LOCAL_STORAGE) { - status = psa_validate_key_type_and_size_for_key_generation( - attributes->core.type, attributes->core.bits); - if (status != PSA_SUCCESS) { - goto exit; - } - - key_buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( - attributes->core.type, - attributes->core.bits); - } else { - status = psa_driver_wrapper_get_key_buffer_size( - attributes, &key_buffer_size); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = psa_allocate_buffer_to_slot(slot, key_buffer_size); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = psa_driver_wrapper_generate_key(attributes, - slot->key.data, slot->key.bytes, &slot->key.bytes); - - if (status != PSA_SUCCESS) { - psa_remove_key_data_from_memory(slot); - } - -exit: - if (status == PSA_SUCCESS) { - status = psa_finish_key_creation(slot, driver, key); - } - if (status != PSA_SUCCESS) { - psa_fail_key_creation(slot, driver); - } - - return status; -} - -/****************************************************************/ -/* Module setup */ -/****************************************************************/ - -#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -psa_status_t mbedtls_psa_crypto_configure_entropy_sources( - void (* entropy_init)(mbedtls_entropy_context *ctx), - void (* entropy_free)(mbedtls_entropy_context *ctx)) -{ - if (global_data.rng_state != RNG_NOT_INITIALIZED) { - return PSA_ERROR_BAD_STATE; - } - global_data.rng.entropy_init = entropy_init; - global_data.rng.entropy_free = entropy_free; - return PSA_SUCCESS; -} -#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ - -void mbedtls_psa_crypto_free(void) -{ - psa_wipe_all_key_slots(); - if (global_data.rng_state != RNG_NOT_INITIALIZED) { - mbedtls_psa_random_free(&global_data.rng); - } - /* Wipe all remaining data, including configuration. - * In particular, this sets all state indicator to the value - * indicating "uninitialized". */ - mbedtls_platform_zeroize(&global_data, sizeof(global_data)); - - /* Terminate drivers */ - psa_driver_wrapper_free(); -} - -#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) -/** Recover a transaction that was interrupted by a power failure. - * - * This function is called during initialization, before psa_crypto_init() - * returns. If this function returns a failure status, the initialization - * fails. - */ -static psa_status_t psa_crypto_recover_transaction( - const psa_crypto_transaction_t *transaction) -{ - switch (transaction->unknown.type) { - case PSA_CRYPTO_TRANSACTION_CREATE_KEY: - case PSA_CRYPTO_TRANSACTION_DESTROY_KEY: - /* TODO - fall through to the failure case until this - * is implemented. - * https://github.com/ARMmbed/mbed-crypto/issues/218 - */ - default: - /* We found an unsupported transaction in the storage. - * We don't know what state the storage is in. Give up. */ - return PSA_ERROR_DATA_INVALID; - } -} -#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ - -psa_status_t psa_crypto_init(void) -{ - psa_status_t status; - - /* Double initialization is explicitly allowed. */ - if (global_data.initialized != 0) { - return PSA_SUCCESS; - } - - /* Init drivers */ - status = psa_driver_wrapper_init(); - if (status != PSA_SUCCESS) { - goto exit; - } - global_data.drivers_initialized = 1; - - /* Initialize and seed the random generator. */ - mbedtls_psa_random_init(&global_data.rng); - global_data.rng_state = RNG_INITIALIZED; - status = mbedtls_psa_random_seed(&global_data.rng); - if (status != PSA_SUCCESS) { - goto exit; - } - global_data.rng_state = RNG_SEEDED; - - status = psa_initialize_key_slots(); - if (status != PSA_SUCCESS) { - goto exit; - } - -#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) - status = psa_crypto_load_transaction(); - if (status == PSA_SUCCESS) { - status = psa_crypto_recover_transaction(&psa_crypto_transaction); - if (status != PSA_SUCCESS) { - goto exit; - } - status = psa_crypto_stop_transaction(); - } else if (status == PSA_ERROR_DOES_NOT_EXIST) { - /* There's no transaction to complete. It's all good. */ - status = PSA_SUCCESS; - } -#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ - - /* All done. */ - global_data.initialized = 1; - -exit: - if (status != PSA_SUCCESS) { - mbedtls_psa_crypto_free(); - } - return status; -} - -#if defined(PSA_WANT_ALG_SOME_PAKE) -psa_status_t psa_crypto_driver_pake_get_password_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *password_len) -{ - if (inputs->password_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - *password_len = inputs->password_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_password( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *buffer, size_t buffer_size, size_t *buffer_length) -{ - if (inputs->password_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - if (buffer_size < inputs->password_len) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(buffer, inputs->password, inputs->password_len); - *buffer_length = inputs->password_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_user_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *user_len) -{ - if (inputs->user_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - *user_len = inputs->user_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_user( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *user_id, size_t user_id_size, size_t *user_id_len) -{ - if (inputs->user_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - if (user_id_size < inputs->user_len) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(user_id, inputs->user, inputs->user_len); - *user_id_len = inputs->user_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_peer_len( - const psa_crypto_driver_pake_inputs_t *inputs, - size_t *peer_len) -{ - if (inputs->peer_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - *peer_len = inputs->peer_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_peer( - const psa_crypto_driver_pake_inputs_t *inputs, - uint8_t *peer_id, size_t peer_id_size, size_t *peer_id_length) -{ - if (inputs->peer_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - if (peer_id_size < inputs->peer_len) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(peer_id, inputs->peer, inputs->peer_len); - *peer_id_length = inputs->peer_len; - - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_driver_pake_get_cipher_suite( - const psa_crypto_driver_pake_inputs_t *inputs, - psa_pake_cipher_suite_t *cipher_suite) -{ - if (inputs->cipher_suite.algorithm == PSA_ALG_NONE) { - return PSA_ERROR_BAD_STATE; - } - - *cipher_suite = inputs->cipher_suite; - - return PSA_SUCCESS; -} - -psa_status_t psa_pake_setup( - psa_pake_operation_t *operation, - const psa_pake_cipher_suite_t *cipher_suite) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_SETUP) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (PSA_ALG_IS_PAKE(cipher_suite->algorithm) == 0 || - PSA_ALG_IS_HASH(cipher_suite->hash) == 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - memset(&operation->data.inputs, 0, sizeof(operation->data.inputs)); - - operation->alg = cipher_suite->algorithm; - operation->primitive = PSA_PAKE_PRIMITIVE(cipher_suite->type, - cipher_suite->family, cipher_suite->bits); - operation->data.inputs.cipher_suite = *cipher_suite; - -#if defined(PSA_WANT_ALG_JPAKE) - if (operation->alg == PSA_ALG_JPAKE) { - psa_jpake_computation_stage_t *computation_stage = - &operation->computation_stage.jpake; - - memset(computation_stage, 0, sizeof(*computation_stage)); - computation_stage->step = PSA_PAKE_STEP_KEY_SHARE; - } else -#endif /* PSA_WANT_ALG_JPAKE */ - { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - operation->stage = PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS; - - return PSA_SUCCESS; -exit: - psa_pake_abort(operation); - return status; -} - -psa_status_t psa_pake_set_password_key( - psa_pake_operation_t *operation, - mbedtls_svc_key_id_t password) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_slot_t *slot = NULL; - psa_key_attributes_t attributes; - psa_key_type_t type; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - status = psa_get_and_lock_key_slot_with_policy(password, &slot, - PSA_KEY_USAGE_DERIVE, - operation->alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - attributes = (psa_key_attributes_t) { - .core = slot->attr - }; - - type = psa_get_key_type(&attributes); - - if (type != PSA_KEY_TYPE_PASSWORD && - type != PSA_KEY_TYPE_PASSWORD_HASH) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - operation->data.inputs.password = mbedtls_calloc(1, slot->key.bytes); - if (operation->data.inputs.password == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - - memcpy(operation->data.inputs.password, slot->key.data, slot->key.bytes); - operation->data.inputs.password_len = slot->key.bytes; - operation->data.inputs.attributes = attributes; -exit: - if (status != PSA_SUCCESS) { - psa_pake_abort(operation); - } - unlock_status = psa_unlock_key_slot(slot); - return (status == PSA_SUCCESS) ? unlock_status : status; -} - -psa_status_t psa_pake_set_user( - psa_pake_operation_t *operation, - const uint8_t *user_id, - size_t user_id_len) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (user_id_len == 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if (operation->data.inputs.user_len != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - operation->data.inputs.user = mbedtls_calloc(1, user_id_len); - if (operation->data.inputs.user == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - - memcpy(operation->data.inputs.user, user_id, user_id_len); - operation->data.inputs.user_len = user_id_len; - - return PSA_SUCCESS; -exit: - psa_pake_abort(operation); - return status; -} - -psa_status_t psa_pake_set_peer( - psa_pake_operation_t *operation, - const uint8_t *peer_id, - size_t peer_id_len) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (peer_id_len == 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if (operation->data.inputs.peer_len != 0) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - operation->data.inputs.peer = mbedtls_calloc(1, peer_id_len); - if (operation->data.inputs.peer == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto exit; - } - - memcpy(operation->data.inputs.peer, peer_id, peer_id_len); - operation->data.inputs.peer_len = peer_id_len; - - return PSA_SUCCESS; -exit: - psa_pake_abort(operation); - return status; -} - -psa_status_t psa_pake_set_role( - psa_pake_operation_t *operation, - psa_pake_role_t role) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_JPAKE) - case PSA_ALG_JPAKE: - if (role == PSA_PAKE_ROLE_NONE) { - return PSA_SUCCESS; - } - status = PSA_ERROR_INVALID_ARGUMENT; - break; -#endif - default: - (void) role; - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } -exit: - psa_pake_abort(operation); - return status; -} - -/* Auxiliary function to convert core computation stage to single driver step. */ -#if defined(PSA_WANT_ALG_JPAKE) -static psa_crypto_driver_pake_step_t convert_jpake_computation_stage_to_driver_step( - psa_jpake_computation_stage_t *stage) -{ - psa_crypto_driver_pake_step_t key_share_step; - if (stage->round == PSA_JPAKE_FIRST) { - int is_x1; - - if (stage->io_mode == PSA_JPAKE_OUTPUT) { - is_x1 = (stage->outputs < 1); - } else { - is_x1 = (stage->inputs < 1); - } - - key_share_step = is_x1 ? - PSA_JPAKE_X1_STEP_KEY_SHARE : - PSA_JPAKE_X2_STEP_KEY_SHARE; - } else if (stage->round == PSA_JPAKE_SECOND) { - key_share_step = (stage->io_mode == PSA_JPAKE_OUTPUT) ? - PSA_JPAKE_X2S_STEP_KEY_SHARE : - PSA_JPAKE_X4S_STEP_KEY_SHARE; - } else { - return PSA_JPAKE_STEP_INVALID; - } - return (psa_crypto_driver_pake_step_t) (key_share_step + stage->step - PSA_PAKE_STEP_KEY_SHARE); -} -#endif /* PSA_WANT_ALG_JPAKE */ - -static psa_status_t psa_pake_complete_inputs( - psa_pake_operation_t *operation) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - /* Create copy of the inputs on stack as inputs share memory - with the driver context which will be setup by the driver. */ - psa_crypto_driver_pake_inputs_t inputs = operation->data.inputs; - - if (inputs.password_len == 0) { - return PSA_ERROR_BAD_STATE; - } - - if (operation->alg == PSA_ALG_JPAKE) { - if (inputs.user_len == 0 || inputs.peer_len == 0) { - return PSA_ERROR_BAD_STATE; - } - } - - /* Clear driver context */ - mbedtls_platform_zeroize(&operation->data, sizeof(operation->data)); - - status = psa_driver_wrapper_pake_setup(operation, &inputs); - - /* Driver is responsible for creating its own copy of the password. */ - mbedtls_zeroize_and_free(inputs.password, inputs.password_len); - - /* User and peer are translated to role. */ - mbedtls_free(inputs.user); - mbedtls_free(inputs.peer); - - if (status == PSA_SUCCESS) { -#if defined(PSA_WANT_ALG_JPAKE) - if (operation->alg == PSA_ALG_JPAKE) { - operation->stage = PSA_PAKE_OPERATION_STAGE_COMPUTATION; - } else -#endif /* PSA_WANT_ALG_JPAKE */ - { - status = PSA_ERROR_NOT_SUPPORTED; - } - } - return status; -} - -#if defined(PSA_WANT_ALG_JPAKE) -static psa_status_t psa_jpake_prologue( - psa_pake_operation_t *operation, - psa_pake_step_t step, - psa_jpake_io_mode_t io_mode) -{ - if (step != PSA_PAKE_STEP_KEY_SHARE && - step != PSA_PAKE_STEP_ZK_PUBLIC && - step != PSA_PAKE_STEP_ZK_PROOF) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - psa_jpake_computation_stage_t *computation_stage = - &operation->computation_stage.jpake; - - if (computation_stage->round != PSA_JPAKE_FIRST && - computation_stage->round != PSA_JPAKE_SECOND) { - return PSA_ERROR_BAD_STATE; - } - - /* Check that the step we are given is the one we were expecting */ - if (step != computation_stage->step) { - return PSA_ERROR_BAD_STATE; - } - - if (step == PSA_PAKE_STEP_KEY_SHARE && - computation_stage->inputs == 0 && - computation_stage->outputs == 0) { - /* Start of the round, so function decides whether we are inputting - * or outputting */ - computation_stage->io_mode = io_mode; - } else if (computation_stage->io_mode != io_mode) { - /* Middle of the round so the mode we are in must match the function - * called by the user */ - return PSA_ERROR_BAD_STATE; - } - - return PSA_SUCCESS; -} - -static psa_status_t psa_jpake_epilogue( - psa_pake_operation_t *operation, - psa_jpake_io_mode_t io_mode) -{ - psa_jpake_computation_stage_t *stage = - &operation->computation_stage.jpake; - - if (stage->step == PSA_PAKE_STEP_ZK_PROOF) { - /* End of an input/output */ - if (io_mode == PSA_JPAKE_INPUT) { - stage->inputs++; - if (stage->inputs == PSA_JPAKE_EXPECTED_INPUTS(stage->round)) { - stage->io_mode = PSA_JPAKE_OUTPUT; - } - } - if (io_mode == PSA_JPAKE_OUTPUT) { - stage->outputs++; - if (stage->outputs == PSA_JPAKE_EXPECTED_OUTPUTS(stage->round)) { - stage->io_mode = PSA_JPAKE_INPUT; - } - } - if (stage->inputs == PSA_JPAKE_EXPECTED_INPUTS(stage->round) && - stage->outputs == PSA_JPAKE_EXPECTED_OUTPUTS(stage->round)) { - /* End of a round, move to the next round */ - stage->inputs = 0; - stage->outputs = 0; - stage->round++; - } - stage->step = PSA_PAKE_STEP_KEY_SHARE; - } else { - stage->step++; - } - return PSA_SUCCESS; -} - -#endif /* PSA_WANT_ALG_JPAKE */ - -psa_status_t psa_pake_output( - psa_pake_operation_t *operation, - psa_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_crypto_driver_pake_step_t driver_step = PSA_JPAKE_STEP_INVALID; - *output_length = 0; - - if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = psa_pake_complete_inputs(operation); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (output_size == 0) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_JPAKE) - case PSA_ALG_JPAKE: - status = psa_jpake_prologue(operation, step, PSA_JPAKE_OUTPUT); - if (status != PSA_SUCCESS) { - goto exit; - } - driver_step = convert_jpake_computation_stage_to_driver_step( - &operation->computation_stage.jpake); - break; -#endif /* PSA_WANT_ALG_JPAKE */ - default: - (void) step; - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - status = psa_driver_wrapper_pake_output(operation, driver_step, - output, output_size, output_length); - - if (status != PSA_SUCCESS) { - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_JPAKE) - case PSA_ALG_JPAKE: - status = psa_jpake_epilogue(operation, PSA_JPAKE_OUTPUT); - if (status != PSA_SUCCESS) { - goto exit; - } - break; -#endif /* PSA_WANT_ALG_JPAKE */ - default: - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - return PSA_SUCCESS; -exit: - psa_pake_abort(operation); - return status; -} - -psa_status_t psa_pake_input( - psa_pake_operation_t *operation, - psa_pake_step_t step, - const uint8_t *input, - size_t input_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_crypto_driver_pake_step_t driver_step = PSA_JPAKE_STEP_INVALID; - const size_t max_input_length = (size_t) PSA_PAKE_INPUT_SIZE(operation->alg, - operation->primitive, - step); - - if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - status = psa_pake_complete_inputs(operation); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (input_length == 0 || input_length > max_input_length) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_JPAKE) - case PSA_ALG_JPAKE: - status = psa_jpake_prologue(operation, step, PSA_JPAKE_INPUT); - if (status != PSA_SUCCESS) { - goto exit; - } - driver_step = convert_jpake_computation_stage_to_driver_step( - &operation->computation_stage.jpake); - break; -#endif /* PSA_WANT_ALG_JPAKE */ - default: - (void) step; - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - status = psa_driver_wrapper_pake_input(operation, driver_step, - input, input_length); - - if (status != PSA_SUCCESS) { - goto exit; - } - - switch (operation->alg) { -#if defined(PSA_WANT_ALG_JPAKE) - case PSA_ALG_JPAKE: - status = psa_jpake_epilogue(operation, PSA_JPAKE_INPUT); - if (status != PSA_SUCCESS) { - goto exit; - } - break; -#endif /* PSA_WANT_ALG_JPAKE */ - default: - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - return PSA_SUCCESS; -exit: - psa_pake_abort(operation); - return status; -} - -psa_status_t psa_pake_get_implicit_key( - psa_pake_operation_t *operation, - psa_key_derivation_operation_t *output) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t shared_key[MBEDTLS_PSA_JPAKE_BUFFER_SIZE]; - size_t shared_key_len = 0; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - -#if defined(PSA_WANT_ALG_JPAKE) - if (operation->alg == PSA_ALG_JPAKE) { - psa_jpake_computation_stage_t *computation_stage = - &operation->computation_stage.jpake; - if (computation_stage->round != PSA_JPAKE_FINISHED) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - } else -#endif /* PSA_WANT_ALG_JPAKE */ - { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - status = psa_driver_wrapper_pake_get_implicit_key(operation, - shared_key, - sizeof(shared_key), - &shared_key_len); - - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_key_derivation_input_bytes(output, - PSA_KEY_DERIVATION_INPUT_SECRET, - shared_key, - shared_key_len); - - mbedtls_platform_zeroize(shared_key, sizeof(shared_key)); -exit: - abort_status = psa_pake_abort(operation); - return status == PSA_SUCCESS ? abort_status : status; -} - -#if defined(SLI_MBEDTLS_PSA_EC_JPAKE_TLS_WORKAROUND) - -psa_status_t psa_pake_derive_secret( - psa_pake_operation_t *operation, - uint8_t *key_buf, - size_t key_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; - size_t key_output_length = 0; - int ret = 0; - - if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - - if (operation->alg == PSA_ALG_JPAKE) { - psa_jpake_computation_stage_t *computation_stage = - &operation->computation_stage.jpake; - if (computation_stage->round != PSA_JPAKE_FINISHED) { - status = PSA_ERROR_BAD_STATE; - goto exit; - } - } else { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - ret = mbedtls_ecjpake_derive_secret( - &(&operation->data.ctx.mbedtls_ctx)->ctx.jpake, - key_buf, - key_length, - &key_output_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - - if (key_output_length != key_length || - ret != 0) { - status = PSA_ERROR_HARDWARE_FAILURE; - goto exit; - } - - status = PSA_SUCCESS; - -exit: - abort_status = psa_pake_abort(operation); - return status == PSA_SUCCESS ? abort_status : status; -} - -#endif // SLI_MBEDTLS_PSA_EC_JPAKE_TLS_WORKAROUND - -psa_status_t psa_pake_abort( - psa_pake_operation_t *operation) -{ - psa_status_t status = PSA_SUCCESS; - - if (operation->stage == PSA_PAKE_OPERATION_STAGE_COMPUTATION) { - status = psa_driver_wrapper_pake_abort(operation); - } - - if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { - if (operation->data.inputs.password != NULL) { - mbedtls_zeroize_and_free(operation->data.inputs.password, - operation->data.inputs.password_len); - } - if (operation->data.inputs.user != NULL) { - mbedtls_free(operation->data.inputs.user); - } - if (operation->data.inputs.peer != NULL) { - mbedtls_free(operation->data.inputs.peer); - } - } - memset(operation, 0, sizeof(psa_pake_operation_t)); - - return status; -} -#endif /* PSA_WANT_ALG_SOME_PAKE */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA crypto layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" +#include "psa_crypto_core_common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +#include "check_crypto_config.h" +#endif + +#include "psa/crypto.h" +#include "psa/crypto_values.h" + +#include "psa_crypto_cipher.h" +#include "psa_crypto_core.h" +#include "psa_crypto_invasive.h" +#include "psa_crypto_driver_wrappers.h" +#include "psa_crypto_driver_wrappers_no_static.h" +#include "psa_crypto_ecp.h" +#include "psa_crypto_ffdh.h" +#include "psa_crypto_hash.h" +#include "psa_crypto_mac.h" +#include "psa_crypto_rsa.h" +#include "psa_crypto_ecp.h" +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +#include "psa_crypto_se.h" +#endif +#include "psa_crypto_slot_management.h" +/* Include internal declarations that are useful for implementing persistently + * stored keys. */ +#include "psa_crypto_storage.h" + +#include "psa_crypto_random_impl.h" + +#include +#include +#include "mbedtls/platform.h" + +#include "mbedtls/aes.h" +#include "mbedtls/asn1.h" +#include "mbedtls/asn1write.h" +#include "mbedtls/bignum.h" +#include "mbedtls/camellia.h" +#include "mbedtls/chacha20.h" +#include "mbedtls/chachapoly.h" +#include "mbedtls/cipher.h" +#include "mbedtls/ccm.h" +#include "mbedtls/cmac.h" +#include "mbedtls/constant_time.h" +#include "mbedtls/des.h" +#include "mbedtls/ecdh.h" +#include "mbedtls/ecp.h" +#include "mbedtls/entropy.h" +#include "mbedtls/error.h" +#include "mbedtls/gcm.h" +#include "mbedtls/md5.h" +#include "mbedtls/md.h" +#include "mbedtls/pk.h" +#include "pk_wrap.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/psa_util.h" +#include "mbedtls/error.h" +#include "mbedtls/ripemd160.h" +#include "mbedtls/rsa.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" +#include "mbedtls/threading.h" +#include "md_psa.h" + +#include "sli_psa_crypto.h" + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) +#define BUILTIN_ALG_ANY_HKDF 1 +#endif + +/****************************************************************/ +/* Global data, support functions and library management */ +/****************************************************************/ + +static int key_type_is_raw_bytes(psa_key_type_t type) +{ + return PSA_KEY_TYPE_IS_UNSTRUCTURED(type); +} + +/* Values for psa_global_data_t::rng_state */ +#define RNG_NOT_INITIALIZED 0 +#define RNG_INITIALIZED 1 +#define RNG_SEEDED 2 + +typedef struct { + uint8_t initialized; + uint8_t rng_state; + uint8_t drivers_initialized; + mbedtls_psa_random_context_t rng; +} psa_global_data_t; + +static psa_global_data_t global_data; + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state = + &global_data.rng.drbg; +#endif + +#define GUARD_MODULE_INITIALIZED \ + if (global_data.initialized == 0) \ + return PSA_ERROR_BAD_STATE; + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) || \ + defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) +static int psa_is_dh_key_size_valid(size_t bits) +{ + if (bits != 2048 && bits != 3072 && bits != 4096 && + bits != 6144 && bits != 8192) { + return 0; + } + + return 1; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT || + MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY || + PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE */ + +psa_status_t mbedtls_to_psa_error(int ret) +{ + /* Mbed TLS error codes can combine a high-level error code and a + * low-level error code. The low-level error usually reflects the + * root cause better, so dispatch on that preferably. */ + int low_level_ret = -(-ret & 0x007f); + switch (low_level_ret != 0 ? low_level_ret : ret) { + case 0: + return PSA_SUCCESS; + +#if defined(MBEDTLS_AES_C) + case MBEDTLS_ERR_AES_INVALID_KEY_LENGTH: + case MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_AES_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; +#endif + +#if defined(MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_ASN1_WRITE_C) + case MBEDTLS_ERR_ASN1_OUT_OF_DATA: + case MBEDTLS_ERR_ASN1_UNEXPECTED_TAG: + case MBEDTLS_ERR_ASN1_INVALID_LENGTH: + case MBEDTLS_ERR_ASN1_LENGTH_MISMATCH: + case MBEDTLS_ERR_ASN1_INVALID_DATA: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_ASN1_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; + case MBEDTLS_ERR_ASN1_BUF_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; +#endif + +#if defined(MBEDTLS_CAMELLIA_C) + case MBEDTLS_ERR_CAMELLIA_BAD_INPUT_DATA: + case MBEDTLS_ERR_CAMELLIA_INVALID_INPUT_LENGTH: + return PSA_ERROR_NOT_SUPPORTED; +#endif + +#if defined(MBEDTLS_CCM_C) + case MBEDTLS_ERR_CCM_BAD_INPUT: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_CCM_AUTH_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; +#endif + +#if defined(MBEDTLS_CHACHA20_C) + case MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; +#endif + +#if defined(MBEDTLS_CHACHAPOLY_C) + case MBEDTLS_ERR_CHACHAPOLY_BAD_STATE: + return PSA_ERROR_BAD_STATE; + case MBEDTLS_ERR_CHACHAPOLY_AUTH_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; +#endif + +#if defined(MBEDTLS_CIPHER_C) + case MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_CIPHER_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; + case MBEDTLS_ERR_CIPHER_INVALID_PADDING: + return PSA_ERROR_INVALID_PADDING; + case MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_CIPHER_AUTH_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; + case MBEDTLS_ERR_CIPHER_INVALID_CONTEXT: + return PSA_ERROR_CORRUPTION_DETECTED; +#endif + +#if !(defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) || \ + defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE)) + /* Only check CTR_DRBG error codes if underlying mbedtls_xxx + * functions are passed a CTR_DRBG instance. */ + case MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED: + return PSA_ERROR_INSUFFICIENT_ENTROPY; + case MBEDTLS_ERR_CTR_DRBG_REQUEST_TOO_BIG: + case MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_CTR_DRBG_FILE_IO_ERROR: + return PSA_ERROR_INSUFFICIENT_ENTROPY; +#endif + +#if defined(MBEDTLS_DES_C) + case MBEDTLS_ERR_DES_INVALID_INPUT_LENGTH: + return PSA_ERROR_NOT_SUPPORTED; +#endif + + case MBEDTLS_ERR_ENTROPY_NO_SOURCES_DEFINED: + case MBEDTLS_ERR_ENTROPY_NO_STRONG_SOURCE: + case MBEDTLS_ERR_ENTROPY_SOURCE_FAILED: + return PSA_ERROR_INSUFFICIENT_ENTROPY; + +#if defined(MBEDTLS_GCM_C) + case MBEDTLS_ERR_GCM_AUTH_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; + case MBEDTLS_ERR_GCM_BUFFER_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; + case MBEDTLS_ERR_GCM_BAD_INPUT: + return PSA_ERROR_INVALID_ARGUMENT; +#endif + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) && \ + defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE) + /* Only check HMAC_DRBG error codes if underlying mbedtls_xxx + * functions are passed a HMAC_DRBG instance. */ + case MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED: + return PSA_ERROR_INSUFFICIENT_ENTROPY; + case MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG: + case MBEDTLS_ERR_HMAC_DRBG_INPUT_TOO_BIG: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_HMAC_DRBG_FILE_IO_ERROR: + return PSA_ERROR_INSUFFICIENT_ENTROPY; +#endif + +#if defined(MBEDTLS_MD_LIGHT) + case MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_MD_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MD_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; +#if defined(MBEDTLS_FS_IO) + case MBEDTLS_ERR_MD_FILE_IO_ERROR: + return PSA_ERROR_STORAGE_FAILURE; +#endif +#endif + +#if defined(MBEDTLS_BIGNUM_C) +#if defined(MBEDTLS_FS_IO) + case MBEDTLS_ERR_MPI_FILE_IO_ERROR: + return PSA_ERROR_STORAGE_FAILURE; +#endif + case MBEDTLS_ERR_MPI_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MPI_INVALID_CHARACTER: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; + case MBEDTLS_ERR_MPI_NEGATIVE_VALUE: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MPI_DIVISION_BY_ZERO: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MPI_NOT_ACCEPTABLE: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_MPI_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; +#endif + +#if defined(MBEDTLS_PK_C) + case MBEDTLS_ERR_PK_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; + case MBEDTLS_ERR_PK_TYPE_MISMATCH: + case MBEDTLS_ERR_PK_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || defined(MBEDTLS_FS_IO) || \ + defined(MBEDTLS_PSA_ITS_FILE_C) + case MBEDTLS_ERR_PK_FILE_IO_ERROR: + return PSA_ERROR_STORAGE_FAILURE; +#endif + case MBEDTLS_ERR_PK_KEY_INVALID_VERSION: + case MBEDTLS_ERR_PK_KEY_INVALID_FORMAT: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_PK_UNKNOWN_PK_ALG: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_PK_PASSWORD_REQUIRED: + case MBEDTLS_ERR_PK_PASSWORD_MISMATCH: + return PSA_ERROR_NOT_PERMITTED; + case MBEDTLS_ERR_PK_INVALID_PUBKEY: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_PK_INVALID_ALG: + case MBEDTLS_ERR_PK_UNKNOWN_NAMED_CURVE: + case MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_PK_SIG_LEN_MISMATCH: + return PSA_ERROR_INVALID_SIGNATURE; + case MBEDTLS_ERR_PK_BUFFER_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; +#endif + + case MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED: + return PSA_ERROR_HARDWARE_FAILURE; + case MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED: + return PSA_ERROR_NOT_SUPPORTED; + +#if defined(MBEDTLS_RSA_C) + case MBEDTLS_ERR_RSA_BAD_INPUT_DATA: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_RSA_INVALID_PADDING: + return PSA_ERROR_INVALID_PADDING; + case MBEDTLS_ERR_RSA_KEY_GEN_FAILED: + return PSA_ERROR_HARDWARE_FAILURE; + case MBEDTLS_ERR_RSA_KEY_CHECK_FAILED: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_RSA_PUBLIC_FAILED: + case MBEDTLS_ERR_RSA_PRIVATE_FAILED: + return PSA_ERROR_CORRUPTION_DETECTED; + case MBEDTLS_ERR_RSA_VERIFY_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; + case MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE: + return PSA_ERROR_BUFFER_TOO_SMALL; + case MBEDTLS_ERR_RSA_RNG_FAILED: + return PSA_ERROR_INSUFFICIENT_ENTROPY; +#endif + +#if defined(MBEDTLS_ECP_LIGHT) + case MBEDTLS_ERR_ECP_BAD_INPUT_DATA: + case MBEDTLS_ERR_ECP_INVALID_KEY: + return PSA_ERROR_INVALID_ARGUMENT; + case MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; + case MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_ECP_SIG_LEN_MISMATCH: + case MBEDTLS_ERR_ECP_VERIFY_FAILED: + return PSA_ERROR_INVALID_SIGNATURE; + case MBEDTLS_ERR_ECP_ALLOC_FAILED: + return PSA_ERROR_INSUFFICIENT_MEMORY; + case MBEDTLS_ERR_ECP_RANDOM_FAILED: + return PSA_ERROR_INSUFFICIENT_ENTROPY; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + case MBEDTLS_ERR_ECP_IN_PROGRESS: + return PSA_OPERATION_INCOMPLETE; +#endif +#endif + + case MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: + return PSA_ERROR_CORRUPTION_DETECTED; + + default: + return PSA_ERROR_GENERIC_ERROR; + } +} + +/** + * \brief For output buffers which contain "tags" + * (outputs that may be checked for validity like + * hashes, MACs and signatures), fill the unused + * part of the output buffer (the whole buffer on + * error, the trailing part on success) with + * something that isn't a valid tag (barring an + * attack on the tag and deliberately-crafted + * input), in case the caller doesn't check the + * return status properly. + * + * \param output_buffer Pointer to buffer to wipe. May not be NULL + * unless \p output_buffer_size is zero. + * \param status Status of function called to generate + * output_buffer originally + * \param output_buffer_size Size of output buffer. If zero, \p output_buffer + * could be NULL. + * \param output_buffer_length Length of data written to output_buffer, must be + * less than \p output_buffer_size + */ +static void psa_wipe_tag_output_buffer(uint8_t *output_buffer, psa_status_t status, + size_t output_buffer_size, size_t output_buffer_length) +{ + size_t offset = 0; + + if (output_buffer_size == 0) { + /* If output_buffer_size is 0 then we have nothing to do. We must not + call memset because output_buffer may be NULL in this case */ + return; + } + + if (status == PSA_SUCCESS) { + offset = output_buffer_length; + } + + memset(output_buffer + offset, '!', output_buffer_size - offset); +} + + + + +/****************************************************************/ +/* Key management */ +/****************************************************************/ + +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +psa_ecc_family_t mbedtls_ecc_group_to_psa(mbedtls_ecp_group_id grpid, + size_t *bits) +{ + switch (grpid) { +#if defined(MBEDTLS_ECP_HAVE_SECP192R1) + case MBEDTLS_ECP_DP_SECP192R1: + *bits = 192; + return PSA_ECC_FAMILY_SECP_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP224R1) + case MBEDTLS_ECP_DP_SECP224R1: + *bits = 224; + return PSA_ECC_FAMILY_SECP_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP256R1) + case MBEDTLS_ECP_DP_SECP256R1: + *bits = 256; + return PSA_ECC_FAMILY_SECP_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP384R1) + case MBEDTLS_ECP_DP_SECP384R1: + *bits = 384; + return PSA_ECC_FAMILY_SECP_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP521R1) + case MBEDTLS_ECP_DP_SECP521R1: + *bits = 521; + return PSA_ECC_FAMILY_SECP_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_BP256R1) + case MBEDTLS_ECP_DP_BP256R1: + *bits = 256; + return PSA_ECC_FAMILY_BRAINPOOL_P_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_BP384R1) + case MBEDTLS_ECP_DP_BP384R1: + *bits = 384; + return PSA_ECC_FAMILY_BRAINPOOL_P_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_BP512R1) + case MBEDTLS_ECP_DP_BP512R1: + *bits = 512; + return PSA_ECC_FAMILY_BRAINPOOL_P_R1; +#endif +#if defined(MBEDTLS_ECP_HAVE_CURVE25519) + case MBEDTLS_ECP_DP_CURVE25519: + *bits = 255; + return PSA_ECC_FAMILY_MONTGOMERY; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP192K1) + case MBEDTLS_ECP_DP_SECP192K1: + *bits = 192; + return PSA_ECC_FAMILY_SECP_K1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP224K1) + case MBEDTLS_ECP_DP_SECP224K1: + *bits = 224; + return PSA_ECC_FAMILY_SECP_K1; +#endif +#if defined(MBEDTLS_ECP_HAVE_SECP256K1) + case MBEDTLS_ECP_DP_SECP256K1: + *bits = 256; + return PSA_ECC_FAMILY_SECP_K1; +#endif +#if defined(MBEDTLS_ECP_HAVE_CURVE448) + case MBEDTLS_ECP_DP_CURVE448: + *bits = 448; + return PSA_ECC_FAMILY_MONTGOMERY; +#endif + default: + *bits = 0; + return 0; + } +} + +mbedtls_ecp_group_id mbedtls_ecc_group_of_psa(psa_ecc_family_t curve, + size_t bits, + int bits_is_sloppy) +{ + switch (curve) { + case PSA_ECC_FAMILY_SECP_R1: + switch (bits) { +#if defined(PSA_WANT_ECC_SECP_R1_192) + case 192: + return MBEDTLS_ECP_DP_SECP192R1; +#endif +#if defined(PSA_WANT_ECC_SECP_R1_224) + case 224: + return MBEDTLS_ECP_DP_SECP224R1; +#endif +#if defined(PSA_WANT_ECC_SECP_R1_256) + case 256: + return MBEDTLS_ECP_DP_SECP256R1; +#endif +#if defined(PSA_WANT_ECC_SECP_R1_384) + case 384: + return MBEDTLS_ECP_DP_SECP384R1; +#endif +#if defined(PSA_WANT_ECC_SECP_R1_521) + case 521: + return MBEDTLS_ECP_DP_SECP521R1; + case 528: + if (bits_is_sloppy) { + return MBEDTLS_ECP_DP_SECP521R1; + } + break; +#endif + } + break; + + case PSA_ECC_FAMILY_BRAINPOOL_P_R1: + switch (bits) { +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_256) + case 256: + return MBEDTLS_ECP_DP_BP256R1; +#endif +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_384) + case 384: + return MBEDTLS_ECP_DP_BP384R1; +#endif +#if defined(PSA_WANT_ECC_BRAINPOOL_P_R1_512) + case 512: + return MBEDTLS_ECP_DP_BP512R1; +#endif + } + break; + + case PSA_ECC_FAMILY_MONTGOMERY: + switch (bits) { +#if defined(PSA_WANT_ECC_MONTGOMERY_255) + case 255: + return MBEDTLS_ECP_DP_CURVE25519; + case 256: + if (bits_is_sloppy) { + return MBEDTLS_ECP_DP_CURVE25519; + } + break; +#endif +#if defined(PSA_WANT_ECC_MONTGOMERY_448) + case 448: + return MBEDTLS_ECP_DP_CURVE448; +#endif + } + break; + + case PSA_ECC_FAMILY_SECP_K1: + switch (bits) { +#if defined(PSA_WANT_ECC_SECP_K1_192) + case 192: + return MBEDTLS_ECP_DP_SECP192K1; +#endif +#if defined(PSA_WANT_ECC_SECP_K1_224) + case 224: + return MBEDTLS_ECP_DP_SECP224K1; +#endif +#if defined(PSA_WANT_ECC_SECP_K1_256) + case 256: + return MBEDTLS_ECP_DP_SECP256K1; +#endif + } + break; + } + + (void) bits_is_sloppy; + return MBEDTLS_ECP_DP_NONE; +} +#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ + +psa_status_t psa_validate_unstructured_key_bit_size(psa_key_type_t type, + size_t bits) +{ + /* Check that the bit size is acceptable for the key type */ + switch (type) { + case PSA_KEY_TYPE_RAW_DATA: + case PSA_KEY_TYPE_HMAC: + case PSA_KEY_TYPE_DERIVE: + case PSA_KEY_TYPE_PASSWORD: + case PSA_KEY_TYPE_PASSWORD_HASH: + break; +#if defined(PSA_WANT_KEY_TYPE_AES) + case PSA_KEY_TYPE_AES: + if (bits != 128 && bits != 192 && bits != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif +#if defined(PSA_WANT_KEY_TYPE_ARIA) + case PSA_KEY_TYPE_ARIA: + if (bits != 128 && bits != 192 && bits != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif +#if defined(PSA_WANT_KEY_TYPE_CAMELLIA) + case PSA_KEY_TYPE_CAMELLIA: + if (bits != 128 && bits != 192 && bits != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif +#if defined(PSA_WANT_KEY_TYPE_DES) + case PSA_KEY_TYPE_DES: + if (bits != 64 && bits != 128 && bits != 192) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif +#if defined(PSA_WANT_KEY_TYPE_CHACHA20) + case PSA_KEY_TYPE_CHACHA20: + if (bits != 256) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif + default: + return PSA_ERROR_NOT_SUPPORTED; + } + if (bits % 8 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +/** Check whether a given key type is valid for use with a given MAC algorithm + * + * Upon successful return of this function, the behavior of #PSA_MAC_LENGTH + * when called with the validated \p algorithm and \p key_type is well-defined. + * + * \param[in] algorithm The specific MAC algorithm (can be wildcard). + * \param[in] key_type The key type of the key to be used with the + * \p algorithm. + * + * \retval #PSA_SUCCESS + * The \p key_type is valid for use with the \p algorithm + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The \p key_type is not valid for use with the \p algorithm + */ +MBEDTLS_STATIC_TESTABLE psa_status_t psa_mac_key_can_do( + psa_algorithm_t algorithm, + psa_key_type_t key_type) +{ + if (PSA_ALG_IS_HMAC(algorithm)) { + if (key_type == PSA_KEY_TYPE_HMAC) { + return PSA_SUCCESS; + } + } + + if (PSA_ALG_IS_BLOCK_CIPHER_MAC(algorithm)) { + /* Check that we're calling PSA_BLOCK_CIPHER_BLOCK_LENGTH with a cipher + * key. */ + if ((key_type & PSA_KEY_TYPE_CATEGORY_MASK) == + PSA_KEY_TYPE_CATEGORY_SYMMETRIC) { + /* PSA_BLOCK_CIPHER_BLOCK_LENGTH returns 1 for stream ciphers and + * the block length (larger than 1) for block ciphers. */ + if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type) > 1) { + return PSA_SUCCESS; + } + } + } + + return PSA_ERROR_INVALID_ARGUMENT; +} + +psa_status_t psa_allocate_buffer_to_slot(psa_key_slot_t *slot, + size_t buffer_length) +{ + if (slot->key.data != NULL) { + return PSA_ERROR_ALREADY_EXISTS; + } + + slot->key.data = mbedtls_calloc(1, buffer_length); + if (slot->key.data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + slot->key.bytes = buffer_length; + return PSA_SUCCESS; +} + +psa_status_t psa_copy_key_material_into_slot(psa_key_slot_t *slot, + const uint8_t *data, + size_t data_length) +{ + psa_status_t status = psa_allocate_buffer_to_slot(slot, + data_length); + if (status != PSA_SUCCESS) { + return status; + } + + memcpy(slot->key.data, data, data_length); + return PSA_SUCCESS; +} + +psa_status_t psa_import_key_into_slot( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_type_t type = attributes->core.type; + + /* zero-length keys are never supported. */ + if (data_length == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_type_is_raw_bytes(type)) { + if (*bits == 0) { + *bits = PSA_BYTES_TO_BITS(data_length); + } + + status = psa_validate_unstructured_key_bit_size(attributes->core.type, + *bits); + if (status != PSA_SUCCESS) { + return status; + } + + /* Copy the key material. */ + if (PSA_BITS_TO_BYTES(*bits) != data_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (PSA_BITS_TO_BYTES(*bits) > key_buffer_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(key_buffer, data, PSA_BITS_TO_BYTES(*bits)); + *key_buffer_length = PSA_BITS_TO_BYTES(*bits); + + return PSA_SUCCESS; + } + else if( PSA_KEY_TYPE_IS_ASYMMETRIC( type ) ) + { +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) + if( PSA_KEY_TYPE_IS_ECC( type ) ) + { + return( mbedtls_psa_ecp_import_key( attributes, + data, data_length, + key_buffer, key_buffer_size, + key_buffer_length, + bits ) ); + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ +#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + if (PSA_KEY_TYPE_IS_RSA(type)) { + return mbedtls_psa_rsa_import_key(attributes, + data, data_length, + key_buffer, key_buffer_size, + key_buffer_length, + bits); + } +#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + } + + return PSA_ERROR_NOT_SUPPORTED; +} + +/** Calculate the intersection of two algorithm usage policies. + * + * Return 0 (which allows no operation) on incompatibility. + */ +static psa_algorithm_t psa_key_policy_algorithm_intersection( + psa_key_type_t key_type, + psa_algorithm_t alg1, + psa_algorithm_t alg2) +{ + /* Common case: both sides actually specify the same policy. */ + if (alg1 == alg2) { + return alg1; + } + /* If the policies are from the same hash-and-sign family, check + * if one is a wildcard. If so the other has the specific algorithm. */ + if (PSA_ALG_IS_SIGN_HASH(alg1) && + PSA_ALG_IS_SIGN_HASH(alg2) && + (alg1 & ~PSA_ALG_HASH_MASK) == (alg2 & ~PSA_ALG_HASH_MASK)) { + if (PSA_ALG_SIGN_GET_HASH(alg1) == PSA_ALG_ANY_HASH) { + return alg2; + } + if (PSA_ALG_SIGN_GET_HASH(alg2) == PSA_ALG_ANY_HASH) { + return alg1; + } + } + /* If the policies are from the same AEAD family, check whether + * one of them is a minimum-tag-length wildcard. Calculate the most + * restrictive tag length. */ + if (PSA_ALG_IS_AEAD(alg1) && PSA_ALG_IS_AEAD(alg2) && + (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg1, 0) == + PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg2, 0))) { + size_t alg1_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg1); + size_t alg2_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg2); + size_t restricted_len = alg1_len > alg2_len ? alg1_len : alg2_len; + + /* If both are wildcards, return most restrictive wildcard */ + if (((alg1 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && + ((alg2 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { + return PSA_ALG_AEAD_WITH_AT_LEAST_THIS_LENGTH_TAG( + alg1, restricted_len); + } + /* If only one is a wildcard, return specific algorithm if compatible. */ + if (((alg1 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && + (alg1_len <= alg2_len)) { + return alg2; + } + if (((alg2 & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0) && + (alg2_len <= alg1_len)) { + return alg1; + } + } + /* If the policies are from the same MAC family, check whether one + * of them is a minimum-MAC-length policy. Calculate the most + * restrictive tag length. */ + if (PSA_ALG_IS_MAC(alg1) && PSA_ALG_IS_MAC(alg2) && + (PSA_ALG_FULL_LENGTH_MAC(alg1) == + PSA_ALG_FULL_LENGTH_MAC(alg2))) { + /* Validate the combination of key type and algorithm. Since the base + * algorithm of alg1 and alg2 are the same, we only need this once. */ + if (PSA_SUCCESS != psa_mac_key_can_do(alg1, key_type)) { + return 0; + } + + /* Get the (exact or at-least) output lengths for both sides of the + * requested intersection. None of the currently supported algorithms + * have an output length dependent on the actual key size, so setting it + * to a bogus value of 0 is currently OK. + * + * Note that for at-least-this-length wildcard algorithms, the output + * length is set to the shortest allowed length, which allows us to + * calculate the most restrictive tag length for the intersection. */ + size_t alg1_len = PSA_MAC_LENGTH(key_type, 0, alg1); + size_t alg2_len = PSA_MAC_LENGTH(key_type, 0, alg2); + size_t restricted_len = alg1_len > alg2_len ? alg1_len : alg2_len; + + /* If both are wildcards, return most restrictive wildcard */ + if (((alg1 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) && + ((alg2 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { + return PSA_ALG_AT_LEAST_THIS_LENGTH_MAC(alg1, restricted_len); + } + + /* If only one is an at-least-this-length policy, the intersection would + * be the other (fixed-length) policy as long as said fixed length is + * equal to or larger than the shortest allowed length. */ + if ((alg1 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { + return (alg1_len <= alg2_len) ? alg2 : 0; + } + if ((alg2 & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { + return (alg2_len <= alg1_len) ? alg1 : 0; + } + + /* If none of them are wildcards, check whether they define the same tag + * length. This is still possible here when one is default-length and + * the other specific-length. Ensure to always return the + * specific-length version for the intersection. */ + if (alg1_len == alg2_len) { + return PSA_ALG_TRUNCATED_MAC(alg1, alg1_len); + } + } + /* If the policies are incompatible, allow nothing. */ + return 0; +} + +static int psa_key_algorithm_permits(psa_key_type_t key_type, + psa_algorithm_t policy_alg, + psa_algorithm_t requested_alg) +{ + /* Common case: the policy only allows requested_alg. */ + if (requested_alg == policy_alg) { + return 1; + } + /* If policy_alg is a hash-and-sign with a wildcard for the hash, + * and requested_alg is the same hash-and-sign family with any hash, + * then requested_alg is compliant with policy_alg. */ + if (PSA_ALG_IS_SIGN_HASH(requested_alg) && + PSA_ALG_SIGN_GET_HASH(policy_alg) == PSA_ALG_ANY_HASH) { + return (policy_alg & ~PSA_ALG_HASH_MASK) == + (requested_alg & ~PSA_ALG_HASH_MASK); + } + /* If policy_alg is a wildcard AEAD algorithm of the same base as + * the requested algorithm, check the requested tag length to be + * equal-length or longer than the wildcard-specified length. */ + if (PSA_ALG_IS_AEAD(policy_alg) && + PSA_ALG_IS_AEAD(requested_alg) && + (PSA_ALG_AEAD_WITH_SHORTENED_TAG(policy_alg, 0) == + PSA_ALG_AEAD_WITH_SHORTENED_TAG(requested_alg, 0)) && + ((policy_alg & PSA_ALG_AEAD_AT_LEAST_THIS_LENGTH_FLAG) != 0)) { + return PSA_ALG_AEAD_GET_TAG_LENGTH(policy_alg) <= + PSA_ALG_AEAD_GET_TAG_LENGTH(requested_alg); + } + /* If policy_alg is a MAC algorithm of the same base as the requested + * algorithm, check whether their MAC lengths are compatible. */ + if (PSA_ALG_IS_MAC(policy_alg) && + PSA_ALG_IS_MAC(requested_alg) && + (PSA_ALG_FULL_LENGTH_MAC(policy_alg) == + PSA_ALG_FULL_LENGTH_MAC(requested_alg))) { + /* Validate the combination of key type and algorithm. Since the policy + * and requested algorithms are the same, we only need this once. */ + if (PSA_SUCCESS != psa_mac_key_can_do(policy_alg, key_type)) { + return 0; + } + + /* Get both the requested output length for the algorithm which is to be + * verified, and the default output length for the base algorithm. + * Note that none of the currently supported algorithms have an output + * length dependent on actual key size, so setting it to a bogus value + * of 0 is currently OK. */ + size_t requested_output_length = PSA_MAC_LENGTH( + key_type, 0, requested_alg); + size_t default_output_length = PSA_MAC_LENGTH( + key_type, 0, + PSA_ALG_FULL_LENGTH_MAC(requested_alg)); + + /* If the policy is default-length, only allow an algorithm with + * a declared exact-length matching the default. */ + if (PSA_MAC_TRUNCATED_LENGTH(policy_alg) == 0) { + return requested_output_length == default_output_length; + } + + /* If the requested algorithm is default-length, allow it if the policy + * length exactly matches the default length. */ + if (PSA_MAC_TRUNCATED_LENGTH(requested_alg) == 0 && + PSA_MAC_TRUNCATED_LENGTH(policy_alg) == default_output_length) { + return 1; + } + + /* If policy_alg is an at-least-this-length wildcard MAC algorithm, + * check for the requested MAC length to be equal to or longer than the + * minimum allowed length. */ + if ((policy_alg & PSA_ALG_MAC_AT_LEAST_THIS_LENGTH_FLAG) != 0) { + return PSA_MAC_TRUNCATED_LENGTH(policy_alg) <= + requested_output_length; + } + } + /* If policy_alg is a generic key agreement operation, then using it for + * a key derivation with that key agreement should also be allowed. This + * behaviour is expected to be defined in a future specification version. */ + if (PSA_ALG_IS_RAW_KEY_AGREEMENT(policy_alg) && + PSA_ALG_IS_KEY_AGREEMENT(requested_alg)) { + return PSA_ALG_KEY_AGREEMENT_GET_BASE(requested_alg) == + policy_alg; + } + /* If it isn't explicitly permitted, it's forbidden. */ + return 0; +} + +/** Test whether a policy permits an algorithm. + * + * The caller must test usage flags separately. + * + * \note This function requires providing the key type for which the policy is + * being validated, since some algorithm policy definitions (e.g. MAC) + * have different properties depending on what kind of cipher it is + * combined with. + * + * \retval PSA_SUCCESS When \p alg is a specific algorithm + * allowed by the \p policy. + * \retval PSA_ERROR_INVALID_ARGUMENT When \p alg is not a specific algorithm + * \retval PSA_ERROR_NOT_PERMITTED When \p alg is a specific algorithm, but + * the \p policy does not allow it. + */ +static psa_status_t psa_key_policy_permits(const psa_key_policy_t *policy, + psa_key_type_t key_type, + psa_algorithm_t alg) +{ + /* '0' is not a valid algorithm */ + if (alg == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* A requested algorithm cannot be a wildcard. */ + if (PSA_ALG_IS_WILDCARD(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (psa_key_algorithm_permits(key_type, policy->alg, alg) || + psa_key_algorithm_permits(key_type, policy->alg2, alg)) { + return PSA_SUCCESS; + } else { + return PSA_ERROR_NOT_PERMITTED; + } +} + +/** Restrict a key policy based on a constraint. + * + * \note This function requires providing the key type for which the policy is + * being restricted, since some algorithm policy definitions (e.g. MAC) + * have different properties depending on what kind of cipher it is + * combined with. + * + * \param[in] key_type The key type for which to restrict the policy + * \param[in,out] policy The policy to restrict. + * \param[in] constraint The policy constraint to apply. + * + * \retval #PSA_SUCCESS + * \c *policy contains the intersection of the original value of + * \c *policy and \c *constraint. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \c key_type, \c *policy and \c *constraint are incompatible. + * \c *policy is unchanged. + */ +static psa_status_t psa_restrict_key_policy( + psa_key_type_t key_type, + psa_key_policy_t *policy, + const psa_key_policy_t *constraint) +{ + psa_algorithm_t intersection_alg = + psa_key_policy_algorithm_intersection(key_type, policy->alg, + constraint->alg); + psa_algorithm_t intersection_alg2 = + psa_key_policy_algorithm_intersection(key_type, policy->alg2, + constraint->alg2); + if (intersection_alg == 0 && policy->alg != 0 && constraint->alg != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (intersection_alg2 == 0 && policy->alg2 != 0 && constraint->alg2 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + policy->usage &= constraint->usage; + policy->alg = intersection_alg; + policy->alg2 = intersection_alg2; + return PSA_SUCCESS; +} + +/** Get the description of a key given its identifier and policy constraints + * and lock it. + * + * The key must have allow all the usage flags set in \p usage. If \p alg is + * nonzero, the key must allow operations with this algorithm. If \p alg is + * zero, the algorithm is not checked. + * + * In case of a persistent key, the function loads the description of the key + * into a key slot if not already done. + * + * On success, the returned key slot is locked. It is the responsibility of + * the caller to unlock the key slot when it does not access it anymore. + */ +static psa_status_t psa_get_and_lock_key_slot_with_policy( + mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + + status = psa_get_and_lock_key_slot( key, p_slot, PSA_INTENT_READ ); + if( status != PSA_SUCCESS ) + return( status ); + slot = *p_slot; + + /* Enforce that usage policy for the key slot contains all the flags + * required by the usage parameter. There is one exception: public + * keys can always be exported, so we treat public key objects as + * if they had the export flag. */ + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type)) { + usage &= ~PSA_KEY_USAGE_EXPORT; + } + + if ((slot->attr.policy.usage & usage) != usage) { + status = PSA_ERROR_NOT_PERMITTED; + goto error; + } + + /* Enforce that the usage policy permits the requested algorithm. */ + if (alg != 0) { + status = psa_key_policy_permits(&slot->attr.policy, + slot->attr.type, + alg); + if (status != PSA_SUCCESS) { + goto error; + } + } + + return PSA_SUCCESS; + +error: + *p_slot = NULL; + psa_unlock_key_slot(slot); + + return status; +} + +/** Get a key slot containing a transparent key and lock it. + * + * A transparent key is a key for which the key material is directly + * available, as opposed to a key in a secure element and/or to be used + * by a secure element. + * + * This is a temporary function that may be used instead of + * psa_get_and_lock_key_slot_with_policy() when there is no opaque key support + * for a cryptographic operation. + * + * On success, the returned key slot is locked. It is the responsibility of the + * caller to unlock the key slot when it does not access it anymore. + */ +static psa_status_t psa_get_and_lock_transparent_key_slot_with_policy( + mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg) +{ + psa_status_t status = psa_get_and_lock_key_slot_with_policy(key, p_slot, + usage, alg); + if (status != PSA_SUCCESS) { + return status; + } + + if (psa_key_lifetime_is_external((*p_slot)->attr.lifetime)) { + psa_unlock_key_slot(*p_slot); + *p_slot = NULL; + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +psa_status_t psa_remove_key_data_from_memory(psa_key_slot_t *slot) +{ + if (slot->key.data != NULL) { + mbedtls_zeroize_and_free(slot->key.data, slot->key.bytes); + } + + slot->key.data = NULL; + slot->key.bytes = 0; + + return PSA_SUCCESS; +} + +/** Completely wipe a slot in memory, including its policy. + * Persistent storage is not affected. */ +psa_status_t psa_wipe_key_slot( psa_key_slot_t *slot ) +{ + psa_status_t status = psa_remove_key_data_from_memory( slot ); + + /* + * As the return error code may not be handled in case of multiple errors, + * do our best to report an unexpected state. Assert with + * MBEDTLS_TEST_HOOK_TEST_ASSERT that the state is as expected: + * if the MBEDTLS_TEST_HOOKS configuration option is enabled and the + * function is called as part of the execution of a test suite, the + * execution of the test suite is stopped in error if the assertion fails. + */ + + if( ( slot->state != PSA_STATE_WIPING && slot->state != PSA_STATE_DESTROYING ) || + slot->reader_count != 0 ) + { + MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->state == PSA_STATE_WIPING || + slot->state == PSA_STATE_DESTROYING ); + MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->reader_count == 0 ); + status = PSA_ERROR_CORRUPTION_DETECTED; + } + + /* Multipart operations may still be using the key. This is safe + * because all multipart operation objects are independent from + * the key slot: if they need to access the key after the setup + * phase, they have a copy of the key. Note that this means that + * key material can linger until all operations are completed. */ + /* At this point, key material and other type-specific content has + * been wiped. Clear remaining metadata. We can call memset and not + * zeroize because the metadata is not particularly sensitive. */ + memset(slot, 0, sizeof(*slot)); + return status; +} + +psa_status_t psa_finish_key_destruction( psa_key_slot_t *slot ) +{ + psa_status_t status; /* status of the last operation */ + psa_status_t overall_status = PSA_SUCCESS; +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + psa_se_drv_table_entry_t *driver; +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + if( slot->state != PSA_STATE_DESTROYING ) + return( PSA_ERROR_BAD_STATE ); + + if (PSA_KEY_LIFETIME_IS_READ_ONLY(slot->attr.lifetime)) { + /* Refuse the destruction of a read-only key (which may or may not work + * if we attempt it, depending on whether the key is merely read-only + * by policy or actually physically read-only). + * Just do the best we can, which is to wipe the copy in memory + * (done in this function's cleanup code). */ + overall_status = PSA_ERROR_NOT_PERMITTED; + + status = psa_wipe_key_slot( slot ); + /* Prioritize CORRUPTION_DETECTED from wiping over a storage error */ + if( status != PSA_SUCCESS ) + overall_status = status; + + return( overall_status ); + } + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + driver = psa_get_se_driver_entry(slot->attr.lifetime); + if (driver != NULL) { + /* For a key in a secure element, we need to do three things: + * remove the key file in internal storage, destroy the + * key inside the secure element, and update the driver's + * persistent data. Start a transaction that will encompass these + * three actions. */ + psa_crypto_prepare_transaction(PSA_CRYPTO_TRANSACTION_DESTROY_KEY); + psa_crypto_transaction.key.lifetime = slot->attr.lifetime; + psa_crypto_transaction.key.slot = psa_key_slot_get_slot_number(slot); + psa_crypto_transaction.key.id = slot->attr.id; + status = psa_crypto_save_transaction(); + if (status != PSA_SUCCESS) { + (void) psa_crypto_stop_transaction(); + /* We should still try to destroy the key in the secure + * element and the key metadata in storage. This is especially + * important if the error is that the storage is full. + * But how to do it exactly without risking an inconsistent + * state after a reset? + * https://github.com/ARMmbed/mbed-crypto/issues/215 + */ + overall_status = status; + goto exit; + } + + status = psa_destroy_se_key(driver, + psa_key_slot_get_slot_number(slot)); + if (overall_status == PSA_SUCCESS) { + overall_status = status; + } + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + if (!PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { + status = psa_destroy_persistent_key(slot->attr.id); + if (overall_status == PSA_SUCCESS) { + overall_status = status; + } + + /* TODO: other slots may have a copy of the same key. We should + * invalidate them. + * https://github.com/ARMmbed/mbed-crypto/issues/214 + */ + } +#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + if (driver != NULL) { + status = psa_save_se_persistent_data(driver); + if (overall_status == PSA_SUCCESS) { + overall_status = status; + } + status = psa_crypto_stop_transaction(); + if (overall_status == PSA_SUCCESS) { + overall_status = status; + } + } +exit: +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + status = psa_wipe_key_slot( slot ); + /* Prioritize CORRUPTION_DETECTED from wiping over a storage error */ + if (status != PSA_SUCCESS) { + overall_status = status; + } + return overall_status; +} + +psa_status_t psa_destroy_key( mbedtls_svc_key_id_t key ) +{ + psa_key_slot_t *slot; + psa_status_t status; /* status of the last operation */ + + if( mbedtls_svc_key_id_is_null( key ) ) + return( PSA_SUCCESS ); + + /* + * Get the description of the key in a key slot. In case of a persistent + * key, this will load the key description from persistent memory if not + * done yet. We cannot avoid this loading as without it we don't know if + * the key is operated by an SE or not and this information is needed by + * the current implementation. + */ + status = psa_get_and_lock_key_slot( key, &slot, PSA_INTENT_DESTROY ); + if( status != PSA_SUCCESS ) + return( status ); + + if( psa_slot_has_no_readers( slot ) ) + { + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + status = psa_finish_key_destruction( slot ); + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + } + else + status = PSA_ERROR_DELAYED; + + return( status ); +} + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) +static psa_status_t psa_get_rsa_public_exponent( + const mbedtls_rsa_context *rsa, + psa_key_attributes_t *attributes) +{ + mbedtls_mpi mpi; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + uint8_t *buffer = NULL; + size_t buflen; + mbedtls_mpi_init(&mpi); + + ret = mbedtls_rsa_export(rsa, NULL, NULL, NULL, NULL, &mpi); + if (ret != 0) { + goto exit; + } + if (mbedtls_mpi_cmp_int(&mpi, 65537) == 0) { + /* It's the default value, which is reported as an empty string, + * so there's nothing to do. */ + goto exit; + } + + buflen = mbedtls_mpi_size(&mpi); + buffer = mbedtls_calloc(1, buflen); + if (buffer == NULL) { + ret = MBEDTLS_ERR_MPI_ALLOC_FAILED; + goto exit; + } + ret = mbedtls_mpi_write_binary(&mpi, buffer, buflen); + if (ret != 0) { + goto exit; + } + attributes->domain_parameters = buffer; + attributes->domain_parameters_size = buflen; + +exit: + mbedtls_mpi_free(&mpi); + if (ret != 0) { + mbedtls_free(buffer); + } + return mbedtls_to_psa_error(ret); +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +/** Retrieve all the publicly-accessible attributes of a key. + */ +psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, + psa_key_attributes_t *attributes) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + psa_reset_key_attributes(attributes); + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, 0, 0); + if (status != PSA_SUCCESS) { + return status; + } + + attributes->core = slot->attr; + attributes->core.flags &= (MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY | + MBEDTLS_PSA_KA_MASK_DUAL_USE); + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + if (psa_get_se_driver_entry(slot->attr.lifetime) != NULL) { + psa_set_key_slot_number(attributes, + psa_key_slot_get_slot_number(slot)); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch (slot->attr.type) { +#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + case PSA_KEY_TYPE_RSA_KEY_PAIR: + case PSA_KEY_TYPE_RSA_PUBLIC_KEY: + /* TODO: reporting the public exponent for opaque keys + * is not yet implemented. + * https://github.com/ARMmbed/mbed-crypto/issues/216 + */ + if (!psa_key_lifetime_is_external(slot->attr.lifetime)) { + mbedtls_rsa_context *rsa = NULL; + + status = mbedtls_psa_rsa_load_representation( + slot->attr.type, + slot->key.data, + slot->key.bytes, + &rsa); + if (status != PSA_SUCCESS) { + break; + } + + status = psa_get_rsa_public_exponent(rsa, + attributes); + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + } + break; +#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + default: + /* Nothing else to do. */ + break; + } + + if (status != PSA_SUCCESS) { + psa_reset_key_attributes(attributes); + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +psa_status_t psa_get_key_slot_number( + const psa_key_attributes_t *attributes, + psa_key_slot_number_t *slot_number) +{ + if (attributes->core.flags & MBEDTLS_PSA_KA_FLAG_HAS_SLOT_NUMBER) { + *slot_number = attributes->slot_number; + return PSA_SUCCESS; + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } +} +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +static psa_status_t psa_export_key_buffer_internal(const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + if (key_buffer_size > data_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + memcpy(data, key_buffer, key_buffer_size); + memset(data + key_buffer_size, 0, + data_size - key_buffer_size); + *data_length = key_buffer_size; + return PSA_SUCCESS; +} + +psa_status_t psa_export_key_internal( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length) +{ + psa_key_type_t type = attributes->core.type; + + if (key_type_is_raw_bytes(type) || + PSA_KEY_TYPE_IS_RSA(type) || + PSA_KEY_TYPE_IS_ECC(type) || + PSA_KEY_TYPE_IS_DH(type)) { + return psa_export_key_buffer_internal( + key_buffer, key_buffer_size, + data, data_size, data_length); + } else { + /* This shouldn't happen in the reference implementation, but + it is valid for a special-purpose implementation to omit + support for exporting certain key types. */ + return PSA_ERROR_NOT_SUPPORTED; + } +} + +psa_status_t psa_export_key(mbedtls_svc_key_id_t key, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + /* Reject a zero-length output buffer now, since this can never be a + * valid key representation. This way we know that data must be a valid + * pointer and we can do things like memset(data, ..., data_size). */ + if (data_size == 0) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + /* Set the key to empty now, so that even when there are errors, we always + * set data_length to a value between 0 and data_size. On error, setting + * the key to empty is a good choice because an empty key representation is + * unlikely to be accepted anywhere. */ + *data_length = 0; + + /* Export requires the EXPORT flag. There is an exception for public keys, + * which don't require any flag, but + * psa_get_and_lock_key_slot_with_policy() takes care of this. + */ + status = psa_get_and_lock_key_slot_with_policy(key, &slot, + PSA_KEY_USAGE_EXPORT, 0); + if (status != PSA_SUCCESS) { + return status; + } + + psa_key_attributes_t attributes = { + .core = slot->attr + }; + status = psa_driver_wrapper_export_key(&attributes, + slot->key.data, slot->key.bytes, + data, data_size, data_length); + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_export_public_key_internal( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + psa_key_type_t type = attributes->core.type; + + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type) && + (PSA_KEY_TYPE_IS_RSA(type) || PSA_KEY_TYPE_IS_ECC(type) || + PSA_KEY_TYPE_IS_DH(type))) { + /* Exporting public -> public */ + return psa_export_key_buffer_internal( + key_buffer, key_buffer_size, + data, data_size, data_length); + } else if (PSA_KEY_TYPE_IS_RSA(type)) { +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + return mbedtls_psa_rsa_export_public_key(attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length); +#else + /* We don't know how to convert a private RSA key to public. */ + return PSA_ERROR_NOT_SUPPORTED; +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + } else if (PSA_KEY_TYPE_IS_ECC(type)) { +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) + return mbedtls_psa_ecp_export_public_key(attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length); +#else + /* We don't know how to convert a private ECC key to public */ + return PSA_ERROR_NOT_SUPPORTED; +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ + } else if (PSA_KEY_TYPE_IS_DH(type)) { +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) + return mbedtls_psa_ffdh_export_public_key(attributes, + key_buffer, + key_buffer_size, + data, data_size, + data_length); +#else + return PSA_ERROR_NOT_SUPPORTED; +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) */ + } else { + (void) key_buffer; + (void) key_buffer_size; + (void) data; + (void) data_size; + (void) data_length; + return PSA_ERROR_NOT_SUPPORTED; + } +} + +psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + psa_key_attributes_t attributes; + + /* Reject a zero-length output buffer now, since this can never be a + * valid key representation. This way we know that data must be a valid + * pointer and we can do things like memset(data, ..., data_size). */ + if (data_size == 0) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + /* Set the key to empty now, so that even when there are errors, we always + * set data_length to a value between 0 and data_size. On error, setting + * the key to empty is a good choice because an empty key representation is + * unlikely to be accepted anywhere. */ + *data_length = 0; + + /* Exporting a public key doesn't require a usage flag. */ + status = psa_get_and_lock_key_slot_with_policy(key, &slot, 0, 0); + if (status != PSA_SUCCESS) { + return status; + } + + if (!PSA_KEY_TYPE_IS_ASYMMETRIC(slot->attr.type)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + status = psa_driver_wrapper_export_public_key( + &attributes, slot->key.data, slot->key.bytes, + data, data_size, data_length); + +exit: + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +MBEDTLS_STATIC_ASSERT( + (MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_DUAL_USE) == 0, + "One or more key attribute flag is listed as both external-only and dual-use") +MBEDTLS_STATIC_ASSERT( + (PSA_KA_MASK_INTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_DUAL_USE) == 0, + "One or more key attribute flag is listed as both internal-only and dual-use") +MBEDTLS_STATIC_ASSERT( + (PSA_KA_MASK_INTERNAL_ONLY & MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY) == 0, + "One or more key attribute flag is listed as both internal-only and external-only") + +/** Validate that a key policy is internally well-formed. + * + * This function only rejects invalid policies. It does not validate the + * consistency of the policy with respect to other attributes of the key + * such as the key type. + */ +static psa_status_t psa_validate_key_policy(const psa_key_policy_t *policy) +{ + if ((policy->usage & ~(PSA_KEY_USAGE_EXPORT | + PSA_KEY_USAGE_COPY | + PSA_KEY_USAGE_ENCRYPT | + PSA_KEY_USAGE_DECRYPT | + PSA_KEY_USAGE_SIGN_MESSAGE | + PSA_KEY_USAGE_VERIFY_MESSAGE | + PSA_KEY_USAGE_SIGN_HASH | + PSA_KEY_USAGE_VERIFY_HASH | + PSA_KEY_USAGE_VERIFY_DERIVATION | + PSA_KEY_USAGE_DERIVE)) != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +/** Validate the internal consistency of key attributes. + * + * This function only rejects invalid attribute values. If does not + * validate the consistency of the attributes with any key data that may + * be involved in the creation of the key. + * + * Call this function early in the key creation process. + * + * \param[in] attributes Key attributes for the new key. + * \param[out] p_drv On any return, the driver for the key, if any. + * NULL for a transparent key. + * + */ +static psa_status_t psa_validate_key_attributes( + const psa_key_attributes_t *attributes, + psa_se_drv_table_entry_t **p_drv) +{ + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_lifetime_t lifetime = psa_get_key_lifetime(attributes); + mbedtls_svc_key_id_t key = psa_get_key_id(attributes); + + status = psa_validate_key_location(lifetime, p_drv); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_validate_key_persistence(lifetime); + if (status != PSA_SUCCESS) { + return status; + } + + if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { + if (MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key) != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } else { + if (!psa_is_valid_key_id(psa_get_key_id(attributes), 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + status = psa_validate_key_policy(&attributes->core.policy); + if (status != PSA_SUCCESS) { + return status; + } + + /* Refuse to create overly large keys. + * Note that this doesn't trigger on import if the attributes don't + * explicitly specify a size (so psa_get_key_bits returns 0), so + * psa_import_key() needs its own checks. */ + if (psa_get_key_bits(attributes) > PSA_MAX_KEY_BITS) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* Reject invalid flags. These should not be reachable through the API. */ + if (attributes->core.flags & ~(MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY | + MBEDTLS_PSA_KA_MASK_DUAL_USE)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +/** Prepare a key slot to receive key material. + * + * This function allocates a key slot and sets its metadata. + * + * If this function fails, call psa_fail_key_creation(). + * + * This function is intended to be used as follows: + * -# Call psa_start_key_creation() to allocate a key slot, prepare + * it with the specified attributes, and in case of a volatile key assign it + * a volatile key identifier. + * -# Populate the slot with the key material. + * -# Call psa_finish_key_creation() to finalize the creation of the slot. + * In case of failure at any step, stop the sequence and call + * psa_fail_key_creation(). + * + * On success, the key slot is locked. It is the responsibility of the caller + * to unlock the key slot when it does not access it anymore. + * + * \param method An identification of the calling function. + * \param[in] attributes Key attributes for the new key. + * \param[out] p_slot On success, a pointer to the prepared slot. + * \param[out] p_drv On any return, the driver for the key, if any. + * NULL for a transparent key. + * + * \retval #PSA_SUCCESS + * The key slot is ready to receive key material. + * \return If this function fails, the key slot is an invalid state. + * You must call psa_fail_key_creation() to wipe and free the slot. + */ +static psa_status_t psa_start_key_creation( + psa_key_creation_method_t method, + const psa_key_attributes_t *attributes, + psa_key_slot_t **p_slot, + psa_se_drv_table_entry_t **p_drv) +{ + psa_status_t status; + psa_key_id_t volatile_key_id; + psa_key_slot_t *slot; + + (void) method; + *p_drv = NULL; + + status = psa_validate_key_attributes(attributes, p_drv); + if (status != PSA_SUCCESS) { + return status; + } + + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + slot = *p_slot; + + /* We're storing the declared bit-size of the key. It's up to each + * creation mechanism to verify that this information is correct. + * It's automatically correct for mechanisms that use the bit-size as + * an input (generate, device) but not for those where the bit-size + * is optional (import, copy). In case of a volatile key, assign it the + * volatile key identifier associated to the slot returned to contain its + * definition. */ + + slot->attr = attributes->core; + if (PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + slot->attr.id = volatile_key_id; +#else + slot->attr.id.key_id = volatile_key_id; +#endif + } + + /* Erase external-only flags from the internal copy. To access + * external-only flags, query `attributes`. Thanks to the check + * in psa_validate_key_attributes(), this leaves the dual-use + * flags and any internal flag that psa_get_empty_key_slot() + * may have set. */ + slot->attr.flags &= ~MBEDTLS_PSA_KA_MASK_EXTERNAL_ONLY; + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* For a key in a secure element, we need to do three things + * when creating or registering a persistent key: + * create the key file in internal storage, create the + * key inside the secure element, and update the driver's + * persistent data. This is done by starting a transaction that will + * encompass these three actions. + * For registering a volatile key, we just need to find an appropriate + * slot number inside the SE. Since the key is designated volatile, creating + * a transaction is not required. */ + /* The first thing to do is to find a slot number for the new key. + * We save the slot number in persistent storage as part of the + * transaction data. It will be needed to recover if the power + * fails during the key creation process, to clean up on the secure + * element side after restarting. Obtaining a slot number from the + * secure element driver updates its persistent state, but we do not yet + * save the driver's persistent state, so that if the power fails, + * we can roll back to a state where the key doesn't exist. */ + if (*p_drv != NULL) { + psa_key_slot_number_t slot_number; + status = psa_find_se_slot_for_key( attributes, method, *p_drv, + &slot_number ); + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + if (!PSA_KEY_LIFETIME_IS_VOLATILE(attributes->core.lifetime)) { + psa_crypto_prepare_transaction(PSA_CRYPTO_TRANSACTION_CREATE_KEY); + psa_crypto_transaction.key.lifetime = slot->attr.lifetime; + psa_crypto_transaction.key.slot = slot_number; + psa_crypto_transaction.key.id = slot->attr.id; + status = psa_crypto_save_transaction( ); + if( status != PSA_SUCCESS ) + { + (void) psa_crypto_stop_transaction( ); + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + } + + status = psa_copy_key_material_into_slot( + slot, (uint8_t *) (&slot_number), sizeof(slot_number)); + } + + if (*p_drv == NULL && method == PSA_KEY_CREATION_REGISTER) { + /* Key registration only makes sense with a secure element. */ + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_ERROR_INVALID_ARGUMENT ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + psa_slot_change_state( slot, PSA_STATE_CREATING ); + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_SUCCESS ); +} + +/** Finalize the creation of a key once its key material has been set. + * + * This entails writing the key to persistent storage. + * + * If this function fails, call psa_fail_key_creation(). + * See the documentation of psa_start_key_creation() for the intended use + * of this function. + * + * If the finalization succeeds, the function unlocks the key slot (it was + * locked by psa_start_key_creation()) and the key slot cannot be accessed + * anymore as part of the key creation process. + * + * \param[in,out] slot Pointer to the slot with key material. + * \param[in] driver The secure element driver for the key, + * or NULL for a transparent key. + * \param[out] key On success, identifier of the key. Note that the + * key identifier is also stored in the key slot. + * + * \retval #PSA_SUCCESS + * The key was successfully created. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * + * \return If this function fails, the key slot is an invalid state. + * You must call psa_fail_key_creation() to wipe and free the slot. + */ +static psa_status_t psa_finish_key_creation( + psa_key_slot_t *slot, + psa_se_drv_table_entry_t *driver, + mbedtls_svc_key_id_t *key) +{ + psa_status_t status = PSA_SUCCESS; + (void) slot; + (void) driver; + + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + if (!PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + if (driver != NULL) { + psa_se_key_data_storage_t data; + psa_key_slot_number_t slot_number = + psa_key_slot_get_slot_number(slot); + + MBEDTLS_STATIC_ASSERT(sizeof(slot_number) == + sizeof(data.slot_number), + "Slot number size does not match psa_se_key_data_storage_t"); + + memcpy(&data.slot_number, &slot_number, sizeof(slot_number)); + status = psa_save_persistent_key(&slot->attr, + (uint8_t *) &data, + sizeof(data)); + } else +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + { + /* Key material is saved in export representation in the slot, so + * just pass the slot buffer for storage. */ + status = psa_save_persistent_key(&slot->attr, + slot->key.data, + slot->key.bytes); + } + } + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } +#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* Finish the transaction for a key creation. This does not + * happen when registering an existing key. Detect this case + * by checking whether a transaction is in progress (actual + * creation of a persistent key in a secure element requires a transaction, + * but registration or volatile key creation doesn't use one). */ + if( driver != NULL && + psa_crypto_transaction.unknown.type == PSA_CRYPTO_TRANSACTION_CREATE_KEY ) + { + status = psa_save_se_persistent_data( driver ); + if( status != PSA_SUCCESS ) + { + psa_destroy_persistent_key( slot->attr.id ); + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + status = psa_crypto_stop_transaction(); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + if (status == PSA_SUCCESS) { + *key = slot->attr.id; + status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); + if( status != PSA_SUCCESS ) { + *key = MBEDTLS_SVC_KEY_ID_INIT; + } + } + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); +} + +/** Abort the creation of a key. + * + * You may call this function after calling psa_start_key_creation(), + * or after psa_finish_key_creation() fails. In other circumstances, this + * function may not clean up persistent storage. + * See the documentation of psa_start_key_creation() for the intended use + * of this function. + * + * \param[in,out] slot Pointer to the slot with key material. + * \param[in] driver The secure element driver for the key, + * or NULL for a transparent key. + */ +static void psa_fail_key_creation(psa_key_slot_t *slot, + psa_se_drv_table_entry_t *driver) +{ + (void) driver; + + if (slot == NULL) { + return; + } + +#if defined(MBEDTLS_THREADING_C) + (void) mbedtls_mutex_lock( &mbedtls_psa_slots_mutex ); +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* TODO: If the key has already been created in the secure + * element, and the failure happened later (when saving metadata + * to internal storage), we need to destroy the key in the secure + * element. + * https://github.com/ARMmbed/mbed-crypto/issues/217 + */ + + /* Abort the ongoing transaction if any (there may not be one if + * the creation process failed before starting one, or if the + * key creation is a registration of a key in a secure element). + * Earlier functions must already have done what it takes to undo any + * partial creation. All that's left is to update the transaction data + * itself. */ + (void) psa_crypto_stop_transaction(); +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + (void) psa_slot_change_state( slot, PSA_STATE_WIPING ); + (void) psa_wipe_key_slot( slot ); +#if defined(MBEDTLS_THREADING_C) + (void) mbedtls_mutex_unlock( &mbedtls_psa_slots_mutex ); +#endif +} + +/** Validate optional attributes during key creation. + * + * Some key attributes are optional during key creation. If they are + * specified in the attributes structure, check that they are consistent + * with the data in the slot. + * + * This function should be called near the end of key creation, after + * the slot in memory is fully populated but before saving persistent data. + */ +static psa_status_t psa_validate_optional_attributes( + const psa_key_slot_t *slot, + const psa_key_attributes_t *attributes) +{ + if (attributes->core.type != 0) { + if (attributes->core.type != slot->attr.type) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + if (attributes->domain_parameters_size != 0) { +#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + if (PSA_KEY_TYPE_IS_RSA(slot->attr.type)) { + mbedtls_rsa_context *rsa = NULL; + mbedtls_mpi actual, required; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + psa_status_t status = mbedtls_psa_rsa_load_representation( + slot->attr.type, + slot->key.data, + slot->key.bytes, + &rsa); + if (status != PSA_SUCCESS) { + return status; + } + + mbedtls_mpi_init(&actual); + mbedtls_mpi_init(&required); + ret = mbedtls_rsa_export(rsa, + NULL, NULL, NULL, NULL, &actual); + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + if (ret != 0) { + goto rsa_exit; + } + ret = mbedtls_mpi_read_binary(&required, + attributes->domain_parameters, + attributes->domain_parameters_size); + if (ret != 0) { + goto rsa_exit; + } + if (mbedtls_mpi_cmp_mpi(&actual, &required) != 0) { + ret = MBEDTLS_ERR_RSA_BAD_INPUT_DATA; + } +rsa_exit: + mbedtls_mpi_free(&actual); + mbedtls_mpi_free(&required); + if (ret != 0) { + return mbedtls_to_psa_error(ret); + } + } else +#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + if (attributes->core.bits != 0) { + if (attributes->core.bits != slot->attr.bits) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + return PSA_SUCCESS; +} + +psa_status_t psa_import_key(const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + mbedtls_svc_key_id_t *key) +{ + psa_status_t status; + psa_key_slot_t *slot = NULL; + psa_se_drv_table_entry_t *driver = NULL; + size_t bits; + size_t storage_size = data_length; + + *key = MBEDTLS_SVC_KEY_ID_INIT; + + /* Reject zero-length symmetric keys (including raw data key objects). + * This also rejects any key which might be encoded as an empty string, + * which is never valid. */ + if (data_length == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Ensure that the bytes-to-bits conversion cannot overflow. */ + if (data_length > SIZE_MAX / 8) { + return PSA_ERROR_NOT_SUPPORTED; + } + + status = psa_start_key_creation(PSA_KEY_CREATION_IMPORT, attributes, + &slot, &driver); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* In the case of a transparent key or an opaque key stored in local + * storage ( thus not in the case of importing a key in a secure element + * with storage ( MBEDTLS_PSA_CRYPTO_SE_C ) ),we have to allocate a + * buffer to hold the imported key material. */ + if (slot->key.data == NULL) { + if (psa_key_lifetime_is_external(attributes->core.lifetime)) { + status = psa_driver_wrapper_get_key_buffer_size_from_key_data( + attributes, data, data_length, &storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + } + status = psa_allocate_buffer_to_slot(slot, storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + bits = slot->attr.bits; + status = psa_driver_wrapper_import_key(attributes, + data, data_length, + slot->key.data, + slot->key.bytes, + &slot->key.bytes, &bits); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (slot->attr.bits == 0) { + slot->attr.bits = (psa_key_bits_t) bits; + } else if (bits != slot->attr.bits) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + /* Enforce a size limit, and in particular ensure that the bit + * size fits in its representation type.*/ + if (bits > PSA_MAX_KEY_BITS) { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + status = psa_validate_optional_attributes(slot, attributes); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_finish_key_creation(slot, driver, key); +exit: + if (status != PSA_SUCCESS) { + psa_fail_key_creation(slot, driver); + } + + return status; +} + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +psa_status_t mbedtls_psa_register_se_key( + const psa_key_attributes_t *attributes) +{ + psa_status_t status; + psa_key_slot_t *slot = NULL; + psa_se_drv_table_entry_t *driver = NULL; + mbedtls_svc_key_id_t key = MBEDTLS_SVC_KEY_ID_INIT; + + /* Leaving attributes unspecified is not currently supported. + * It could make sense to query the key type and size from the + * secure element, but not all secure elements support this + * and the driver HAL doesn't currently support it. */ + if (psa_get_key_type(attributes) == PSA_KEY_TYPE_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (psa_get_key_bits(attributes) == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + status = psa_start_key_creation(PSA_KEY_CREATION_REGISTER, attributes, + &slot, &driver); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_finish_key_creation(slot, driver, &key); + +exit: + if (status != PSA_SUCCESS) { + psa_fail_key_creation(slot, driver); + } + + /* Registration doesn't keep the key in RAM. */ + psa_close_key(key); + return status; +} +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, + const psa_key_attributes_t *specified_attributes, + mbedtls_svc_key_id_t *target_key) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *source_slot = NULL; + psa_key_slot_t *target_slot = NULL; + psa_key_attributes_t actual_attributes = *specified_attributes; + psa_se_drv_table_entry_t *driver = NULL; + size_t storage_size = 0; + bool source_key_is_unconditionally_copyable = false; + + *target_key = MBEDTLS_SVC_KEY_ID_INIT; + + status = psa_get_and_lock_key_slot_with_policy( + source_key, &source_slot, 0, 0); + if (status != PSA_SUCCESS) { + goto exit; + } + + source_key_is_unconditionally_copyable = + sli_psa_key_is_unconditionally_copyable(source_slot->attr.id); + + if (!source_key_is_unconditionally_copyable && + ((source_slot->attr.policy.usage & PSA_KEY_USAGE_COPY) + != PSA_KEY_USAGE_COPY)) { + status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } + + status = psa_validate_optional_attributes(source_slot, + specified_attributes); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* The target key type and number of bits have been validated by + * psa_validate_optional_attributes() to be either equal to zero or + * equal to the ones of the source key. So it is safe to inherit + * them from the source key now." + * */ + actual_attributes.core.bits = source_slot->attr.bits; + actual_attributes.core.type = source_slot->attr.type; + + + status = psa_restrict_key_policy(source_slot->attr.type, + &actual_attributes.core.policy, + &source_slot->attr.policy); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_start_key_creation(PSA_KEY_CREATION_COPY, &actual_attributes, + &target_slot, &driver); + if (status != PSA_SUCCESS) { + goto exit; + } + if (!source_key_is_unconditionally_copyable && + PSA_KEY_LIFETIME_GET_LOCATION(target_slot->attr.lifetime) != + PSA_KEY_LIFETIME_GET_LOCATION(source_slot->attr.lifetime)) { + /* + * If the source and target keys are stored in different locations, + * the source key would need to be exported as plaintext and re-imported + * in the other location. This has security implications which have not + * been fully mapped. For now, this can be achieved through + * appropriate API invocations from the application, if needed. + * */ + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + /* + * When the source and target keys are within the same location, + * - For transparent keys it is a blind copy without any driver invocation, + * - For opaque keys this translates to an invocation of the drivers' + * copy_key entry point through the dispatch layer. + * */ + if (psa_key_lifetime_is_external(actual_attributes.core.lifetime)) { + status = psa_driver_wrapper_get_key_buffer_size(&actual_attributes, + &storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_allocate_buffer_to_slot(target_slot, storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (psa_key_lifetime_is_external(source_slot->attr.lifetime)) { + // Silicon Labs's opaque driver for key copying is only able to + // import transparent keys. + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + status = psa_driver_wrapper_copy_key(&actual_attributes, + source_slot->key.data, + source_slot->key.bytes, + target_slot->key.data, + target_slot->key.bytes, + &target_slot->key.bytes); + if (status != PSA_SUCCESS) { + goto exit; + } + } else if (source_key_is_unconditionally_copyable && + psa_key_lifetime_is_external(source_slot->attr.lifetime)) { + /* We can't copy from an opaque key into a transparent one. */ + status = PSA_ERROR_NOT_PERMITTED; + goto exit; + } else { + status = psa_copy_key_material_into_slot(target_slot, + source_slot->key.data, + source_slot->key.bytes); + if (status != PSA_SUCCESS) { + goto exit; + } + } + status = psa_finish_key_creation(target_slot, driver, target_key); +exit: + if (status != PSA_SUCCESS) { + psa_fail_key_creation(target_slot, driver); + } + + unlock_status = psa_unlock_key_slot(source_slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + + + +/****************************************************************/ +/* Message digests */ +/****************************************************************/ + +psa_status_t psa_hash_abort(psa_hash_operation_t *operation) +{ + /* Aborting a non-active operation is allowed */ + if (operation->id == 0) { + return PSA_SUCCESS; + } + + psa_status_t status = psa_driver_wrapper_hash_abort(operation); + operation->id = 0; + + return status; +} + +psa_status_t psa_hash_setup(psa_hash_operation_t *operation, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* A context must be freshly initialized before it can be set up. */ + if (operation->id != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (!PSA_ALG_IS_HASH(alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + /* Ensure all of the context is zeroized, since PSA_HASH_OPERATION_INIT only + * directly zeroes the int-sized dummy member of the context union. */ + memset(&operation->ctx, 0, sizeof(operation->ctx)); + + status = psa_driver_wrapper_hash_setup(operation, alg); + +exit: + if (status != PSA_SUCCESS) { + psa_hash_abort(operation); + } + + return status; +} + +psa_status_t psa_hash_update(psa_hash_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + /* Don't require hash implementations to behave correctly on a + * zero-length input, which may have an invalid pointer. */ + if (input_length == 0) { + return PSA_SUCCESS; + } + + status = psa_driver_wrapper_hash_update(operation, input, input_length); + +exit: + if (status != PSA_SUCCESS) { + psa_hash_abort(operation); + } + + return status; +} + +psa_status_t psa_hash_finish(psa_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + *hash_length = 0; + if (operation->id == 0) { + return PSA_ERROR_BAD_STATE; + } + + psa_status_t status = psa_driver_wrapper_hash_finish( + operation, hash, hash_size, hash_length); + psa_hash_abort(operation); + return status; +} + +psa_status_t psa_hash_verify(psa_hash_operation_t *operation, + const uint8_t *hash, + size_t hash_length) +{ + uint8_t actual_hash[PSA_HASH_MAX_SIZE]; + size_t actual_hash_length; + psa_status_t status = psa_hash_finish( + operation, + actual_hash, sizeof(actual_hash), + &actual_hash_length); + + if (status != PSA_SUCCESS) { + goto exit; + } + + if (actual_hash_length != hash_length) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + if (mbedtls_ct_memcmp(hash, actual_hash, actual_hash_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } + +exit: + mbedtls_platform_zeroize(actual_hash, sizeof(actual_hash)); + if (status != PSA_SUCCESS) { + psa_hash_abort(operation); + } + + return status; +} + +psa_status_t psa_hash_compute(psa_algorithm_t alg, + const uint8_t *input, size_t input_length, + uint8_t *hash, size_t hash_size, + size_t *hash_length) +{ + *hash_length = 0; + if (!PSA_ALG_IS_HASH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return psa_driver_wrapper_hash_compute(alg, input, input_length, + hash, hash_size, hash_length); +} + +psa_status_t psa_hash_compare(psa_algorithm_t alg, + const uint8_t *input, size_t input_length, + const uint8_t *hash, size_t hash_length) +{ + uint8_t actual_hash[PSA_HASH_MAX_SIZE]; + size_t actual_hash_length; + + if (!PSA_ALG_IS_HASH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_status_t status = psa_driver_wrapper_hash_compute( + alg, input, input_length, + actual_hash, sizeof(actual_hash), + &actual_hash_length); + if (status != PSA_SUCCESS) { + goto exit; + } + if (actual_hash_length != hash_length) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + if (mbedtls_ct_memcmp(hash, actual_hash, actual_hash_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } + +exit: + mbedtls_platform_zeroize(actual_hash, sizeof(actual_hash)); + return status; +} + +psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, + psa_hash_operation_t *target_operation) +{ + if (source_operation->id == 0 || + target_operation->id != 0) { + return PSA_ERROR_BAD_STATE; + } + + psa_status_t status = psa_driver_wrapper_hash_clone(source_operation, + target_operation); + if (status != PSA_SUCCESS) { + psa_hash_abort(target_operation); + } + + return status; +} + + +/****************************************************************/ +/* MAC */ +/****************************************************************/ + +psa_status_t psa_mac_abort(psa_mac_operation_t *operation) +{ + /* Aborting a non-active operation is allowed */ + if (operation->id == 0) { + return PSA_SUCCESS; + } + + psa_status_t status = psa_driver_wrapper_mac_abort(operation); + operation->mac_size = 0; + operation->is_sign = 0; + operation->id = 0; + + return status; +} + +static psa_status_t psa_mac_finalize_alg_and_key_validation( + psa_algorithm_t alg, + const psa_key_attributes_t *attributes, + uint8_t *mac_size) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_type_t key_type = psa_get_key_type(attributes); + size_t key_bits = psa_get_key_bits(attributes); + + if (!PSA_ALG_IS_MAC(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Validate the combination of key type and algorithm */ + status = psa_mac_key_can_do(alg, key_type); + if (status != PSA_SUCCESS) { + return status; + } + + /* Get the output length for the algorithm and key combination */ + *mac_size = PSA_MAC_LENGTH(key_type, key_bits, alg); + + if (*mac_size < 4) { + /* A very short MAC is too short for security since it can be + * brute-forced. Ancient protocols with 32-bit MACs do exist, + * so we make this our minimum, even though 32 bits is still + * too small for security. */ + return PSA_ERROR_NOT_SUPPORTED; + } + + if (*mac_size > PSA_MAC_LENGTH(key_type, key_bits, + PSA_ALG_FULL_LENGTH_MAC(alg))) { + /* It's impossible to "truncate" to a larger length than the full length + * of the algorithm. */ + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (*mac_size > PSA_MAC_MAX_SIZE) { + /* PSA_MAC_LENGTH returns the correct length even for a MAC algorithm + * that is disabled in the compile-time configuration. The result can + * therefore be larger than PSA_MAC_MAX_SIZE, which does take the + * configuration into account. In this case, force a return of + * PSA_ERROR_NOT_SUPPORTED here. Otherwise psa_mac_verify(), or + * psa_mac_compute(mac_size=PSA_MAC_MAX_SIZE), would return + * PSA_ERROR_BUFFER_TOO_SMALL for an unsupported algorithm whose MAC size + * is larger than PSA_MAC_MAX_SIZE, which is misleading and which breaks + * systematically generated tests. */ + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +static psa_status_t psa_mac_setup(psa_mac_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + int is_sign) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + psa_key_attributes_t attributes; + + /* A context must be freshly initialized before it can be set up. */ + if (operation->id != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_get_and_lock_key_slot_with_policy( + key, + &slot, + is_sign ? PSA_KEY_USAGE_SIGN_MESSAGE : PSA_KEY_USAGE_VERIFY_MESSAGE, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + status = psa_mac_finalize_alg_and_key_validation(alg, &attributes, + &operation->mac_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + operation->is_sign = is_sign; + /* Dispatch the MAC setup call with validated input */ + if (is_sign) { + status = psa_driver_wrapper_mac_sign_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } else { + status = psa_driver_wrapper_mac_verify_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } + +exit: + if (status != PSA_SUCCESS) { + psa_mac_abort(operation); + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_mac_setup(operation, key, alg, 1); +} + +psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_mac_setup(operation, key, alg, 0); +} + +psa_status_t psa_mac_update(psa_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + if (operation->id == 0) { + return PSA_ERROR_BAD_STATE; + } + + /* Don't require hash implementations to behave correctly on a + * zero-length input, which may have an invalid pointer. */ + if (input_length == 0) { + return PSA_SUCCESS; + } + + psa_status_t status = psa_driver_wrapper_mac_update(operation, + input, input_length); + if (status != PSA_SUCCESS) { + psa_mac_abort(operation); + } + + return status; +} + +psa_status_t psa_mac_sign_finish(psa_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (!operation->is_sign) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + /* Sanity check. This will guarantee that mac_size != 0 (and so mac != NULL) + * once all the error checks are done. */ + if (operation->mac_size == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (mac_size < operation->mac_size) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_driver_wrapper_mac_sign_finish(operation, + mac, operation->mac_size, + mac_length); + +exit: + /* In case of success, set the potential excess room in the output buffer + * to an invalid value, to avoid potentially leaking a longer MAC. + * In case of error, set the output length and content to a safe default, + * such that in case the caller misses an error check, the output would be + * an unachievable MAC. + */ + if (status != PSA_SUCCESS) { + *mac_length = mac_size; + operation->mac_size = 0; + } + + psa_wipe_tag_output_buffer(mac, status, mac_size, *mac_length); + + abort_status = psa_mac_abort(operation); + + return status == PSA_SUCCESS ? abort_status : status; +} + +psa_status_t psa_mac_verify_finish(psa_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->is_sign) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->mac_size != mac_length) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + + status = psa_driver_wrapper_mac_verify_finish(operation, + mac, mac_length); + +exit: + abort_status = psa_mac_abort(operation); + + return status == PSA_SUCCESS ? abort_status : status; +} + +static psa_status_t psa_mac_compute_internal(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length, + int is_sign) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + uint8_t operation_mac_size = 0; + psa_key_attributes_t attributes; + + status = psa_get_and_lock_key_slot_with_policy( + key, + &slot, + is_sign ? PSA_KEY_USAGE_SIGN_MESSAGE : PSA_KEY_USAGE_VERIFY_MESSAGE, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + status = psa_mac_finalize_alg_and_key_validation(alg, &attributes, + &operation_mac_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (mac_size < operation_mac_size) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_driver_wrapper_mac_compute( + &attributes, + slot->key.data, slot->key.bytes, + alg, + input, input_length, + mac, operation_mac_size, mac_length); + +exit: + /* In case of success, set the potential excess room in the output buffer + * to an invalid value, to avoid potentially leaking a longer MAC. + * In case of error, set the output length and content to a safe default, + * such that in case the caller misses an error check, the output would be + * an unachievable MAC. + */ + if (status != PSA_SUCCESS) { + *mac_length = mac_size; + operation_mac_size = 0; + } + + psa_wipe_tag_output_buffer(mac, status, mac_size, *mac_length); + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + return psa_mac_compute_internal(key, alg, + input, input_length, + mac, mac_size, mac_length, 1); +} + +psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *mac, + size_t mac_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t actual_mac[PSA_MAC_MAX_SIZE]; + size_t actual_mac_length; + + status = psa_mac_compute_internal(key, alg, + input, input_length, + actual_mac, sizeof(actual_mac), + &actual_mac_length, 0); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (mac_length != actual_mac_length) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + if (mbedtls_ct_memcmp(mac, actual_mac, actual_mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + +exit: + mbedtls_platform_zeroize(actual_mac, sizeof(actual_mac)); + + return status; +} + +/****************************************************************/ +/* Asymmetric cryptography */ +/****************************************************************/ + +static psa_status_t psa_sign_verify_check_alg(int input_is_message, + psa_algorithm_t alg) +{ + if (input_is_message) { + if (!PSA_ALG_IS_SIGN_MESSAGE(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (PSA_ALG_IS_SIGN_HASH(alg)) { + if (!PSA_ALG_IS_HASH(PSA_ALG_SIGN_GET_HASH(alg))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + } else { + if (!PSA_ALG_IS_SIGN_HASH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + return PSA_SUCCESS; +} + +static psa_status_t psa_sign_internal(mbedtls_svc_key_id_t key, + int input_is_message, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + psa_key_attributes_t attributes; + + *signature_length = 0; + + status = psa_sign_verify_check_alg(input_is_message, alg); + if (status != PSA_SUCCESS) { + return status; + } + + /* Immediately reject a zero-length signature buffer. This guarantees + * that signature must be a valid pointer. (On the other hand, the input + * buffer can in principle be empty since it doesn't actually have + * to be a hash.) */ + if (signature_size == 0) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = psa_get_and_lock_key_slot_with_policy( + key, &slot, + input_is_message ? PSA_KEY_USAGE_SIGN_MESSAGE : + PSA_KEY_USAGE_SIGN_HASH, + alg); + + if (status != PSA_SUCCESS) { + goto exit; + } + + if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + if (input_is_message) { + status = psa_driver_wrapper_sign_message( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, + signature, signature_size, signature_length); + } else { + + status = psa_driver_wrapper_sign_hash( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, + signature, signature_size, signature_length); + } + + +exit: + psa_wipe_tag_output_buffer(signature, status, signature_size, + *signature_length); + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +static psa_status_t psa_verify_internal(mbedtls_svc_key_id_t key, + int input_is_message, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + status = psa_sign_verify_check_alg(input_is_message, alg); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_get_and_lock_key_slot_with_policy( + key, &slot, + input_is_message ? PSA_KEY_USAGE_VERIFY_MESSAGE : + PSA_KEY_USAGE_VERIFY_HASH, + alg); + + if (status != PSA_SUCCESS) { + return status; + } + + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + if (input_is_message) { + status = psa_driver_wrapper_verify_message( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, + signature, signature_length); + } else { + status = psa_driver_wrapper_verify_hash( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, + signature, signature_length); + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; + +} + +psa_status_t psa_sign_message_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (PSA_ALG_IS_SIGN_HASH(alg)) { + size_t hash_length; + uint8_t hash[PSA_HASH_MAX_SIZE]; + + status = psa_driver_wrapper_hash_compute( + PSA_ALG_SIGN_GET_HASH(alg), + input, input_length, + hash, sizeof(hash), &hash_length); + + if (status != PSA_SUCCESS) { + return status; + } + + return psa_driver_wrapper_sign_hash( + attributes, key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_size, signature_length); + } + + return PSA_ERROR_NOT_SUPPORTED; +} + +psa_status_t psa_sign_message(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return psa_sign_internal( + key, 1, alg, input, input_length, + signature, signature_size, signature_length); +} + +psa_status_t psa_verify_message_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (PSA_ALG_IS_SIGN_HASH(alg)) { + size_t hash_length; + uint8_t hash[PSA_HASH_MAX_SIZE]; + + status = psa_driver_wrapper_hash_compute( + PSA_ALG_SIGN_GET_HASH(alg), + input, input_length, + hash, sizeof(hash), &hash_length); + + if (status != PSA_SUCCESS) { + return status; + } + + return psa_driver_wrapper_verify_hash( + attributes, key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_length); + } + + return PSA_ERROR_NOT_SUPPORTED; +} + +psa_status_t psa_verify_message(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length) +{ + return psa_verify_internal( + key, 1, alg, input, input_length, + signature, signature_length); +} + +psa_status_t psa_sign_hash_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length) +{ + if (attributes->core.type == PSA_KEY_TYPE_RSA_KEY_PAIR) { + if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || + PSA_ALG_IS_RSA_PSS(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) + return mbedtls_psa_rsa_sign_hash( + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_size, signature_length); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + } else if (PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { + if (PSA_ALG_IS_ECDSA(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) + return mbedtls_psa_ecdsa_sign_hash( + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_size, signature_length); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + (void) key_buffer; + (void) key_buffer_size; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; +} + +psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) +{ + return psa_sign_internal( + key, 0, alg, hash, hash_length, + signature, signature_size, signature_length); +} + +psa_status_t psa_verify_hash_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length) +{ + if (PSA_KEY_TYPE_IS_RSA(attributes->core.type)) { + if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) || + PSA_ALG_IS_RSA_PSS(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) + return mbedtls_psa_rsa_verify_hash( + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_length); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + } else if (PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { + if (PSA_ALG_IS_ECDSA(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) + return mbedtls_psa_ecdsa_verify_hash( + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_length); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + (void) key_buffer; + (void) key_buffer_size; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; +} + +psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length) +{ + return psa_verify_internal( + key, 0, alg, hash, hash_length, + signature, signature_length); +} + +psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + psa_key_attributes_t attributes; + + (void) input; + (void) input_length; + (void) salt; + (void) output; + (void) output_size; + + *output_length = 0; + + if (!PSA_ALG_IS_RSA_OAEP(alg) && salt_length != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_ENCRYPT, alg); + if (status != PSA_SUCCESS) { + return status; + } + if (!(PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type) || + PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type))) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + status = psa_driver_wrapper_asymmetric_encrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, salt, salt_length, + output, output_size, output_length); +exit: + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + psa_key_attributes_t attributes; + + (void) input; + (void) input_length; + (void) salt; + (void) output; + (void) output_size; + + *output_length = 0; + + if (!PSA_ALG_IS_RSA_OAEP(alg) && salt_length != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_DECRYPT, alg); + if (status != PSA_SUCCESS) { + return status; + } + if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + status = psa_driver_wrapper_asymmetric_decrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, salt, salt_length, + output, output_size, output_length); + +exit: + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +/****************************************************************/ +/* Asymmetric interruptible cryptography */ +/****************************************************************/ + +static uint32_t psa_interruptible_max_ops = PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED; + +void psa_interruptible_set_max_ops(uint32_t max_ops) +{ + psa_interruptible_max_ops = max_ops; +} + +uint32_t psa_interruptible_get_max_ops(void) +{ + return psa_interruptible_max_ops; +} + +uint32_t psa_sign_hash_get_num_ops( + const psa_sign_hash_interruptible_operation_t *operation) +{ + return operation->num_ops; +} + +uint32_t psa_verify_hash_get_num_ops( + const psa_verify_hash_interruptible_operation_t *operation) +{ + return operation->num_ops; +} + +static psa_status_t psa_sign_hash_abort_internal( + psa_sign_hash_interruptible_operation_t *operation) +{ + if (operation->id == 0) { + /* The object has (apparently) been initialized but it is not (yet) + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + return PSA_SUCCESS; + } + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_driver_wrapper_sign_hash_abort(operation); + + operation->id = 0; + + /* Do not clear either the error_occurred or num_ops elements here as they + * only want to be cleared by the application calling abort, not by abort + * being called at completion of an operation. */ + + return status; +} + +psa_status_t psa_sign_hash_start( + psa_sign_hash_interruptible_operation_t *operation, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + psa_key_attributes_t attributes; + + /* Check that start has not been previously called, or operation has not + * previously errored. */ + if (operation->id != 0 || operation->error_occurred) { + return PSA_ERROR_BAD_STATE; + } + + status = psa_sign_verify_check_alg(0, alg); + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + return status; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, + PSA_KEY_USAGE_SIGN_HASH, + alg); + + if (status != PSA_SUCCESS) { + goto exit; + } + + if (!PSA_KEY_TYPE_IS_KEY_PAIR(slot->attr.type)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + /* Ensure ops count gets reset, in case of operation re-use. */ + operation->num_ops = 0; + + status = psa_driver_wrapper_sign_hash_start(operation, &attributes, + slot->key.data, + slot->key.bytes, alg, + hash, hash_length); +exit: + + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + psa_sign_hash_abort_internal(operation); + } + + unlock_status = psa_unlock_key_slot(slot); + + if (unlock_status != PSA_SUCCESS) { + operation->error_occurred = 1; + } + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + + +psa_status_t psa_sign_hash_complete( + psa_sign_hash_interruptible_operation_t *operation, + uint8_t *signature, size_t signature_size, + size_t *signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *signature_length = 0; + + /* Check that start has been called first, and that operation has not + * previously errored. */ + if (operation->id == 0 || operation->error_occurred) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + /* Immediately reject a zero-length signature buffer. This guarantees that + * signature must be a valid pointer. */ + if (signature_size == 0) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_driver_wrapper_sign_hash_complete(operation, signature, + signature_size, + signature_length); + + /* Update ops count with work done. */ + operation->num_ops = psa_driver_wrapper_sign_hash_get_num_ops(operation); + +exit: + + psa_wipe_tag_output_buffer(signature, status, signature_size, + *signature_length); + + if (status != PSA_OPERATION_INCOMPLETE) { + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + } + + psa_sign_hash_abort_internal(operation); + } + + return status; +} + +psa_status_t psa_sign_hash_abort( + psa_sign_hash_interruptible_operation_t *operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_sign_hash_abort_internal(operation); + + /* We clear the number of ops done here, so that it is not cleared when + * the operation fails or succeeds, only on manual abort. */ + operation->num_ops = 0; + + /* Likewise, failure state. */ + operation->error_occurred = 0; + + return status; +} + +static psa_status_t psa_verify_hash_abort_internal( + psa_verify_hash_interruptible_operation_t *operation) +{ + if (operation->id == 0) { + /* The object has (apparently) been initialized but it is not (yet) + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + return PSA_SUCCESS; + } + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_driver_wrapper_verify_hash_abort(operation); + + operation->id = 0; + + /* Do not clear either the error_occurred or num_ops elements here as they + * only want to be cleared by the application calling abort, not by abort + * being called at completion of an operation. */ + + return status; +} + +psa_status_t psa_verify_hash_start( + psa_verify_hash_interruptible_operation_t *operation, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + /* Check that start has not been previously called, or operation has not + * previously errored. */ + if (operation->id != 0 || operation->error_occurred) { + return PSA_ERROR_BAD_STATE; + } + + status = psa_sign_verify_check_alg(0, alg); + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + return status; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, + PSA_KEY_USAGE_VERIFY_HASH, + alg); + + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + return status; + } + + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + /* Ensure ops count gets reset, in case of operation re-use. */ + operation->num_ops = 0; + + status = psa_driver_wrapper_verify_hash_start(operation, &attributes, + slot->key.data, + slot->key.bytes, + alg, hash, hash_length, + signature, signature_length); + + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + psa_verify_hash_abort_internal(operation); + } + + unlock_status = psa_unlock_key_slot(slot); + + if (unlock_status != PSA_SUCCESS) { + operation->error_occurred = 1; + } + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_verify_hash_complete( + psa_verify_hash_interruptible_operation_t *operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* Check that start has been called first, and that operation has not + * previously errored. */ + if (operation->id == 0 || operation->error_occurred) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_driver_wrapper_verify_hash_complete(operation); + + /* Update ops count with work done. */ + operation->num_ops = psa_driver_wrapper_verify_hash_get_num_ops( + operation); + +exit: + + if (status != PSA_OPERATION_INCOMPLETE) { + if (status != PSA_SUCCESS) { + operation->error_occurred = 1; + } + + psa_verify_hash_abort_internal(operation); + } + + return status; +} + +psa_status_t psa_verify_hash_abort( + psa_verify_hash_interruptible_operation_t *operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_verify_hash_abort_internal(operation); + + /* We clear the number of ops done here, so that it is not cleared when + * the operation fails or succeeds, only on manual abort. */ + operation->num_ops = 0; + + /* Likewise, failure state. */ + operation->error_occurred = 0; + + return status; +} + +/****************************************************************/ +/* Asymmetric interruptible cryptography internal */ +/* implementations */ +/****************************************************************/ + +void mbedtls_psa_interruptible_set_max_ops(uint32_t max_ops) +{ + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + /* Internal implementation uses zero to indicate infinite number max ops, + * therefore avoid this value, and set to minimum possible. */ + if (max_ops == 0) { + max_ops = 1; + } + + mbedtls_ecp_set_max_ops(max_ops); +#else + (void) max_ops; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +uint32_t mbedtls_psa_sign_hash_get_num_ops( + const mbedtls_psa_sign_hash_interruptible_operation_t *operation) +{ +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + return operation->num_ops; +#else + (void) operation; + return 0; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +uint32_t mbedtls_psa_verify_hash_get_num_ops( + const mbedtls_psa_verify_hash_interruptible_operation_t *operation) +{ + #if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + return operation->num_ops; +#else + (void) operation; + return 0; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_sign_hash_start( + mbedtls_psa_sign_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t required_hash_length = 0; + + if (!PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (!PSA_ALG_IS_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + mbedtls_ecdsa_restart_init(&operation->restart_ctx); + + /* Ensure num_ops is zero'ed in case of context re-use. */ + operation->num_ops = 0; + + status = mbedtls_psa_ecp_load_representation(attributes->core.type, + attributes->core.bits, + key_buffer, + key_buffer_size, + &operation->ctx); + + if (status != PSA_SUCCESS) { + return status; + } + + operation->coordinate_bytes = PSA_BITS_TO_BYTES( + operation->ctx->grp.nbits); + + psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); + operation->md_alg = mbedtls_md_type_from_psa_alg(hash_alg); + operation->alg = alg; + + /* We only need to store the same length of hash as the private key size + * here, it would be truncated by the internal implementation anyway. */ + required_hash_length = (hash_length < operation->coordinate_bytes ? + hash_length : operation->coordinate_bytes); + + if (required_hash_length > sizeof(operation->hash)) { + /* Shouldn't happen, but better safe than sorry. */ + return PSA_ERROR_CORRUPTION_DETECTED; + } + + memcpy(operation->hash, hash, required_hash_length); + operation->hash_length = required_hash_length; + + return PSA_SUCCESS; + +#else + (void) operation; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) status; + (void) required_hash_length; + + return PSA_ERROR_NOT_SUPPORTED; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_sign_hash_complete( + mbedtls_psa_sign_hash_interruptible_operation_t *operation, + uint8_t *signature, size_t signature_size, + size_t *signature_length) +{ +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi r; + mbedtls_mpi s; + + mbedtls_mpi_init(&r); + mbedtls_mpi_init(&s); + + /* Ensure max_ops is set to the current value (or default). */ + mbedtls_psa_interruptible_set_max_ops(psa_interruptible_get_max_ops()); + + if (signature_size < 2 * operation->coordinate_bytes) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + if (PSA_ALG_ECDSA_IS_DETERMINISTIC(operation->alg)) { + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) + status = mbedtls_to_psa_error( + mbedtls_ecdsa_sign_det_restartable(&operation->ctx->grp, + &r, + &s, + &operation->ctx->d, + operation->hash, + operation->hash_length, + operation->md_alg, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + &operation->restart_ctx)); +#else /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + } else { + status = mbedtls_to_psa_error( + mbedtls_ecdsa_sign_restartable(&operation->ctx->grp, + &r, + &s, + &operation->ctx->d, + operation->hash, + operation->hash_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + &operation->restart_ctx)); + } + + /* Hide the fact that the restart context only holds a delta of number of + * ops done during the last operation, not an absolute value. */ + operation->num_ops += operation->restart_ctx.ecp.ops_done; + + if (status == PSA_SUCCESS) { + status = mbedtls_to_psa_error( + mbedtls_mpi_write_binary(&r, + signature, + operation->coordinate_bytes) + ); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = mbedtls_to_psa_error( + mbedtls_mpi_write_binary(&s, + signature + + operation->coordinate_bytes, + operation->coordinate_bytes) + ); + + if (status != PSA_SUCCESS) { + goto exit; + } + + *signature_length = operation->coordinate_bytes * 2; + + status = PSA_SUCCESS; + } + +exit: + + mbedtls_mpi_free(&r); + mbedtls_mpi_free(&s); + return status; + + #else + + (void) operation; + (void) signature; + (void) signature_size; + (void) signature_length; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_sign_hash_abort( + mbedtls_psa_sign_hash_interruptible_operation_t *operation) +{ + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + if (operation->ctx) { + mbedtls_ecdsa_free(operation->ctx); + mbedtls_free(operation->ctx); + operation->ctx = NULL; + } + + mbedtls_ecdsa_restart_free(&operation->restart_ctx); + + operation->num_ops = 0; + + return PSA_SUCCESS; + +#else + + (void) operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_verify_hash_start( + mbedtls_psa_verify_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t coordinate_bytes = 0; + size_t required_hash_length = 0; + + if (!PSA_KEY_TYPE_IS_ECC(attributes->core.type)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (!PSA_ALG_IS_ECDSA(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + mbedtls_ecdsa_restart_init(&operation->restart_ctx); + mbedtls_mpi_init(&operation->r); + mbedtls_mpi_init(&operation->s); + + /* Ensure num_ops is zero'ed in case of context re-use. */ + operation->num_ops = 0; + + status = mbedtls_psa_ecp_load_representation(attributes->core.type, + attributes->core.bits, + key_buffer, + key_buffer_size, + &operation->ctx); + + if (status != PSA_SUCCESS) { + return status; + } + + coordinate_bytes = PSA_BITS_TO_BYTES(operation->ctx->grp.nbits); + + if (signature_length != 2 * coordinate_bytes) { + return PSA_ERROR_INVALID_SIGNATURE; + } + + status = mbedtls_to_psa_error( + mbedtls_mpi_read_binary(&operation->r, + signature, + coordinate_bytes)); + + if (status != PSA_SUCCESS) { + return status; + } + + status = mbedtls_to_psa_error( + mbedtls_mpi_read_binary(&operation->s, + signature + + coordinate_bytes, + coordinate_bytes)); + + if (status != PSA_SUCCESS) { + return status; + } + + status = mbedtls_psa_ecp_load_public_part(operation->ctx); + + if (status != PSA_SUCCESS) { + return status; + } + + /* We only need to store the same length of hash as the private key size + * here, it would be truncated by the internal implementation anyway. */ + required_hash_length = (hash_length < coordinate_bytes ? hash_length : + coordinate_bytes); + + if (required_hash_length > sizeof(operation->hash)) { + /* Shouldn't happen, but better safe than sorry. */ + return PSA_ERROR_CORRUPTION_DETECTED; + } + + memcpy(operation->hash, hash, required_hash_length); + operation->hash_length = required_hash_length; + + return PSA_SUCCESS; +#else + (void) operation; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) hash; + (void) hash_length; + (void) signature; + (void) signature_length; + (void) status; + (void) coordinate_bytes; + (void) required_hash_length; + + return PSA_ERROR_NOT_SUPPORTED; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_verify_hash_complete( + mbedtls_psa_verify_hash_interruptible_operation_t *operation) +{ + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* Ensure max_ops is set to the current value (or default). */ + mbedtls_psa_interruptible_set_max_ops(psa_interruptible_get_max_ops()); + + status = mbedtls_to_psa_error( + mbedtls_ecdsa_verify_restartable(&operation->ctx->grp, + operation->hash, + operation->hash_length, + &operation->ctx->Q, + &operation->r, + &operation->s, + &operation->restart_ctx)); + + /* Hide the fact that the restart context only holds a delta of number of + * ops done during the last operation, not an absolute value. */ + operation->num_ops += operation->restart_ctx.ecp.ops_done; + + return status; +#else + (void) operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +psa_status_t mbedtls_psa_verify_hash_abort( + mbedtls_psa_verify_hash_interruptible_operation_t *operation) +{ + +#if (defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA)) && \ + defined(MBEDTLS_ECP_RESTARTABLE) + + if (operation->ctx) { + mbedtls_ecdsa_free(operation->ctx); + mbedtls_free(operation->ctx); + operation->ctx = NULL; + } + + mbedtls_ecdsa_restart_free(&operation->restart_ctx); + + operation->num_ops = 0; + + mbedtls_mpi_free(&operation->r); + mbedtls_mpi_free(&operation->s); + + return PSA_SUCCESS; + +#else + (void) operation; + + return PSA_ERROR_NOT_SUPPORTED; + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) && + * defined( MBEDTLS_ECP_RESTARTABLE ) */ +} + +/****************************************************************/ +/* Symmetric cryptography */ +/****************************************************************/ + +static psa_status_t psa_cipher_setup(psa_cipher_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + mbedtls_operation_t cipher_operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + psa_key_usage_t usage = (cipher_operation == MBEDTLS_ENCRYPT ? + PSA_KEY_USAGE_ENCRYPT : + PSA_KEY_USAGE_DECRYPT); + psa_key_attributes_t attributes; + + /* A context must be freshly initialized before it can be set up. */ + if (operation->id != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (!PSA_ALG_IS_CIPHER(alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, usage, alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Initialize the operation struct members, except for id. The id member + * is used to indicate to psa_cipher_abort that there are resources to free, + * so we only set it (in the driver wrapper) after resources have been + * allocated/initialized. */ + operation->iv_set = 0; + if (alg == PSA_ALG_ECB_NO_PADDING) { + operation->iv_required = 0; + } else { + operation->iv_required = 1; + } + operation->default_iv_length = PSA_CIPHER_IV_LENGTH(slot->attr.type, alg); + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + /* Try doing the operation through a driver before using software fallback. */ + if (cipher_operation == MBEDTLS_ENCRYPT) { + status = psa_driver_wrapper_cipher_encrypt_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } else { + status = psa_driver_wrapper_cipher_decrypt_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } + +exit: + if (status != PSA_SUCCESS) { + psa_cipher_abort(operation); + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_cipher_setup(operation, key, alg, MBEDTLS_ENCRYPT); +} + +psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_cipher_setup(operation, key, alg, MBEDTLS_DECRYPT); +} + +psa_status_t psa_cipher_generate_iv(psa_cipher_operation_t *operation, + uint8_t *iv, + size_t iv_size, + size_t *iv_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t local_iv[PSA_CIPHER_IV_MAX_SIZE]; + size_t default_iv_length = 0; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->iv_set || !operation->iv_required) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + default_iv_length = operation->default_iv_length; + if (iv_size < default_iv_length) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + if (default_iv_length > PSA_CIPHER_IV_MAX_SIZE) { + status = PSA_ERROR_GENERIC_ERROR; + goto exit; + } + + status = psa_generate_random(local_iv, default_iv_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_driver_wrapper_cipher_set_iv(operation, + local_iv, default_iv_length); + +exit: + if (status == PSA_SUCCESS) { + memcpy(iv, local_iv, default_iv_length); + *iv_length = default_iv_length; + operation->iv_set = 1; + } else { + *iv_length = 0; + psa_cipher_abort(operation); + } + + return status; +} + +psa_status_t psa_cipher_set_iv(psa_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->iv_set || !operation->iv_required) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (iv_length > PSA_CIPHER_IV_MAX_SIZE) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_driver_wrapper_cipher_set_iv(operation, + iv, + iv_length); + +exit: + if (status == PSA_SUCCESS) { + operation->iv_set = 1; + } else { + psa_cipher_abort(operation); + } + return status; +} + +psa_status_t psa_cipher_update(psa_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->iv_required && !operation->iv_set) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_driver_wrapper_cipher_update(operation, + input, + input_length, + output, + output_size, + output_length); + +exit: + if (status != PSA_SUCCESS) { + psa_cipher_abort(operation); + } + + return status; +} + +psa_status_t psa_cipher_finish(psa_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->iv_required && !operation->iv_set) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_driver_wrapper_cipher_finish(operation, + output, + output_size, + output_length); + +exit: + if (status == PSA_SUCCESS) { + return psa_cipher_abort(operation); + } else { + *output_length = 0; + (void) psa_cipher_abort(operation); + + return status; + } +} + +psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation) +{ + if (operation->id == 0) { + /* The object has (apparently) been initialized but it is not (yet) + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + return PSA_SUCCESS; + } + + psa_driver_wrapper_cipher_abort(operation); + + operation->id = 0; + operation->iv_set = 0; + operation->iv_required = 0; + + return PSA_SUCCESS; +} + +psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + uint8_t local_iv[PSA_CIPHER_IV_MAX_SIZE]; + size_t default_iv_length = 0; + psa_key_attributes_t attributes; + + if (!PSA_ALG_IS_CIPHER(alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, + PSA_KEY_USAGE_ENCRYPT, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + default_iv_length = PSA_CIPHER_IV_LENGTH(slot->attr.type, alg); + if (default_iv_length > PSA_CIPHER_IV_MAX_SIZE) { + status = PSA_ERROR_GENERIC_ERROR; + goto exit; + } + + if (default_iv_length > 0) { + if (output_size < default_iv_length) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_generate_random(local_iv, default_iv_length); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = psa_driver_wrapper_cipher_encrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, local_iv, default_iv_length, input, input_length, + psa_crypto_buffer_offset(output, default_iv_length), + output_size - default_iv_length, output_length); + +exit: + unlock_status = psa_unlock_key_slot(slot); + if (status == PSA_SUCCESS) { + status = unlock_status; + } + + if (status == PSA_SUCCESS) { + if (default_iv_length > 0) { + memcpy(output, local_iv, default_iv_length); + } + *output_length += default_iv_length; + } else { + *output_length = 0; + } + + return status; +} + +psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + psa_key_attributes_t attributes; + + if (!PSA_ALG_IS_CIPHER(alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, + PSA_KEY_USAGE_DECRYPT, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + if (alg == PSA_ALG_CCM_STAR_NO_TAG && + input_length < PSA_BLOCK_CIPHER_BLOCK_LENGTH(slot->attr.type)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } else if (input_length < PSA_CIPHER_IV_LENGTH(slot->attr.type, alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_driver_wrapper_cipher_decrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, input, input_length, + output, output_size, output_length); + +exit: + unlock_status = psa_unlock_key_slot(slot); + if (status == PSA_SUCCESS) { + status = unlock_status; + } + + if (status != PSA_SUCCESS) { + *output_length = 0; + } + + return status; +} + + +/****************************************************************/ +/* AEAD */ +/****************************************************************/ + +/* Helper function to get the base algorithm from its variants. */ +static psa_algorithm_t psa_aead_get_base_algorithm(psa_algorithm_t alg) +{ + return PSA_ALG_AEAD_WITH_DEFAULT_LENGTH_TAG(alg); +} + +/* Helper function to perform common nonce length checks. */ +static psa_status_t psa_aead_check_nonce_length(psa_algorithm_t alg, + size_t nonce_length) +{ + psa_algorithm_t base_alg = psa_aead_get_base_algorithm(alg); + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + + switch (base_alg) { +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_GCM: + /* Not checking max nonce size here as GCM spec allows almost + * arbitrarily large nonces. Please note that we do not generally + * recommend the usage of nonces of greater length than + * PSA_AEAD_NONCE_MAX_SIZE, as large nonces are hashed to a shorter + * size, which can then lead to collisions if you encrypt a very + * large number of messages.*/ + if (nonce_length != 0) { + return PSA_SUCCESS; + } + break; +#endif /* PSA_WANT_ALG_GCM */ +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM: + if (nonce_length >= 7 && nonce_length <= 13) { + return PSA_SUCCESS; + } + break; +#endif /* PSA_WANT_ALG_CCM */ +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) + case PSA_ALG_CHACHA20_POLY1305: + if (nonce_length == 12) { + return PSA_SUCCESS; + } else if (nonce_length == 8) { + return PSA_ERROR_NOT_SUPPORTED; + } + break; +#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ + default: + (void)nonce_length; + status = PSA_ERROR_NOT_SUPPORTED; + break; + } + + return status; +} + +static psa_status_t psa_aead_check_algorithm(psa_algorithm_t alg) +{ + if (!PSA_ALG_IS_AEAD(alg) || PSA_ALG_IS_WILDCARD(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *plaintext, + size_t plaintext_length, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + *ciphertext_length = 0; + + status = psa_aead_check_algorithm(alg); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_get_and_lock_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_ENCRYPT, alg); + if (status != PSA_SUCCESS) { + return status; + } + + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + status = psa_aead_check_nonce_length(alg, nonce_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_driver_wrapper_aead_encrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length); + + if (status != PSA_SUCCESS && ciphertext_size != 0) { + memset(ciphertext, 0, ciphertext_size); + } + +exit: + psa_unlock_key_slot(slot); + + return status; +} + +psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, + psa_algorithm_t alg, + const uint8_t *nonce, + size_t nonce_length, + const uint8_t *additional_data, + size_t additional_data_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + *plaintext_length = 0; + + status = psa_aead_check_algorithm(alg); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_get_and_lock_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_DECRYPT, alg); + if (status != PSA_SUCCESS) { + return status; + } + + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + status = psa_aead_check_nonce_length(alg, nonce_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_driver_wrapper_aead_decrypt( + &attributes, slot->key.data, slot->key.bytes, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length); + + if (status != PSA_SUCCESS && plaintext_size != 0) { + memset(plaintext, 0, plaintext_size); + } + +exit: + psa_unlock_key_slot(slot); + + return status; +} + +static psa_status_t psa_validate_tag_length(psa_algorithm_t alg) +{ + const uint8_t tag_len = PSA_ALG_AEAD_GET_TAG_LENGTH(alg); + psa_status_t status = PSA_SUCCESS; + + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + /* CCM allows the following tag lengths: 4, 6, 8, 10, 12, 14, 16.*/ + if (tag_len < 4 || tag_len > 16 || tag_len % 2) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif /* PSA_WANT_ALG_CCM */ + +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + /* GCM allows the following tag lengths: 4, 8, 12, 13, 14, 15, 16. */ + if (tag_len != 4 && tag_len != 8 && (tag_len < 12 || tag_len > 16)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif /* PSA_WANT_ALG_GCM */ + +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + /* We only support the default tag length. */ + if (tag_len != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + break; +#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ + + default: + (void) tag_len; + status = PSA_ERROR_NOT_SUPPORTED; + } + return status; +} + +/* Set the key for a multipart authenticated operation. */ +static psa_status_t psa_aead_setup(psa_aead_operation_t *operation, + int is_encrypt, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + psa_key_usage_t key_usage = 0; + psa_key_attributes_t attributes; + + status = psa_aead_check_algorithm(alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (operation->id != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->nonce_set || operation->lengths_set || + operation->ad_started || operation->body_started) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (is_encrypt) { + key_usage = PSA_KEY_USAGE_ENCRYPT; + } else { + key_usage = PSA_KEY_USAGE_DECRYPT; + } + + status = psa_get_and_lock_key_slot_with_policy(key, &slot, key_usage, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + if ((status = psa_validate_tag_length(alg)) != PSA_SUCCESS) { + goto exit; + } + + if (is_encrypt) { + status = psa_driver_wrapper_aead_encrypt_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } else { + status = psa_driver_wrapper_aead_decrypt_setup(operation, + &attributes, + slot->key.data, + slot->key.bytes, + alg); + } + if (status != PSA_SUCCESS) { + goto exit; + } + + operation->key_type = psa_get_key_type(&attributes); + +exit: + unlock_status = psa_unlock_key_slot(slot); + + if (status == PSA_SUCCESS) { + status = unlock_status; + operation->alg = psa_aead_get_base_algorithm(alg); + operation->is_encrypt = is_encrypt; + } else { + psa_aead_abort(operation); + } + + return status; +} + +/* Set the key for a multipart authenticated encryption operation. */ +psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_aead_setup(operation, 1, key, alg); +} + +/* Set the key for a multipart authenticated decryption operation. */ +psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, + mbedtls_svc_key_id_t key, + psa_algorithm_t alg) +{ + return psa_aead_setup(operation, 0, key, alg); +} + +/* Generate a random nonce / IV for multipart AEAD operation */ +psa_status_t psa_aead_generate_nonce(psa_aead_operation_t *operation, + uint8_t *nonce, + size_t nonce_size, + size_t *nonce_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t local_nonce[PSA_AEAD_NONCE_MAX_SIZE]; + size_t required_nonce_size = 0; + + *nonce_length = 0; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->nonce_set || !operation->is_encrypt) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + /* For CCM, this size may not be correct according to the PSA + * specification. The PSA Crypto 1.0.1 specification states: + * + * CCM encodes the plaintext length pLen in L octets, with L the smallest + * integer >= 2 where pLen < 2^(8L). The nonce length is then 15 - L bytes. + * + * However this restriction that L has to be the smallest integer is not + * applied in practice, and it is not implementable here since the + * plaintext length may or may not be known at this time. */ + required_nonce_size = PSA_AEAD_NONCE_LENGTH(operation->key_type, + operation->alg); + if (nonce_size < required_nonce_size) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_generate_random(local_nonce, required_nonce_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_aead_set_nonce(operation, local_nonce, required_nonce_size); + +exit: + if (status == PSA_SUCCESS) { + memcpy(nonce, local_nonce, required_nonce_size); + *nonce_length = required_nonce_size; + } else { + psa_aead_abort(operation); + } + + return status; +} + +/* Set the nonce for a multipart authenticated encryption or decryption + operation.*/ +psa_status_t psa_aead_set_nonce(psa_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->nonce_set) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_aead_check_nonce_length(operation->alg, nonce_length); + if (status != PSA_SUCCESS) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + status = psa_driver_wrapper_aead_set_nonce(operation, nonce, + nonce_length); + +exit: + if (status == PSA_SUCCESS) { + operation->nonce_set = 1; + } else { + psa_aead_abort(operation); + } + + return status; +} + +/* Declare the lengths of the message and additional data for multipart AEAD. */ +psa_status_t psa_aead_set_lengths(psa_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->lengths_set || operation->ad_started || + operation->body_started) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_GCM) + case PSA_ALG_GCM: + /* Lengths can only be too large for GCM if size_t is bigger than 32 + * bits. Without the guard this code will generate warnings on 32bit + * builds. */ +#if SIZE_MAX > UINT32_MAX + if (((uint64_t) ad_length) >> 61 != 0 || + ((uint64_t) plaintext_length) > 0xFFFFFFFE0ull) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } +#endif + break; +#endif /* PSA_WANT_ALG_GCM */ +#if defined(PSA_WANT_ALG_CCM) + case PSA_ALG_CCM: + if (ad_length > 0xFF00) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + break; +#endif /* PSA_WANT_ALG_CCM */ +#if defined(PSA_WANT_ALG_CHACHA20_POLY1305) + case PSA_ALG_CHACHA20_POLY1305: + /* No length restrictions for ChaChaPoly. */ + break; +#endif /* PSA_WANT_ALG_CHACHA20_POLY1305 */ + default: + break; + } + + status = psa_driver_wrapper_aead_set_lengths(operation, ad_length, + plaintext_length); + +exit: + if (status == PSA_SUCCESS) { + operation->ad_remaining = ad_length; + operation->body_remaining = plaintext_length; + operation->lengths_set = 1; + } else { + psa_aead_abort(operation); + } + + return status; +} + +/* Pass additional data to an active multipart AEAD operation. */ +psa_status_t psa_aead_update_ad(psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (!operation->nonce_set || operation->body_started) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->lengths_set) { + if (operation->ad_remaining < input_length) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + operation->ad_remaining -= input_length; + } +#if defined(PSA_WANT_ALG_CCM) + else if (operation->alg == PSA_ALG_CCM) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } +#endif /* PSA_WANT_ALG_CCM */ + + status = psa_driver_wrapper_aead_update_ad(operation, input, + input_length); + +exit: + if (status == PSA_SUCCESS) { + operation->ad_started = 1; + } else { + psa_aead_abort(operation); + } + + return status; +} + +/* Encrypt or decrypt a message fragment in an active multipart AEAD + operation.*/ +psa_status_t psa_aead_update(psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *output_length = 0; + + if (operation->id == 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (!operation->nonce_set) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->lengths_set) { + /* Additional data length was supplied, but not all the additional + data was supplied.*/ + if (operation->ad_remaining != 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + /* Too much data provided. */ + if (operation->body_remaining < input_length) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + operation->body_remaining -= input_length; + } +#if defined(PSA_WANT_ALG_CCM) + else if (operation->alg == PSA_ALG_CCM) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } +#endif /* PSA_WANT_ALG_CCM */ + + status = psa_driver_wrapper_aead_update(operation, input, input_length, + output, output_size, + output_length); + +exit: + if (status == PSA_SUCCESS) { + operation->body_started = 1; + } else { + psa_aead_abort(operation); + } + + return status; +} + +static psa_status_t psa_aead_final_checks(const psa_aead_operation_t *operation) +{ + if (operation->id == 0 || !operation->nonce_set) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->lengths_set && (operation->ad_remaining != 0 || + operation->body_remaining != 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return PSA_SUCCESS; +} + +/* Finish encrypting a message in a multipart AEAD operation. */ +psa_status_t psa_aead_finish(psa_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *ciphertext_length = 0; + *tag_length = tag_size; + + status = psa_aead_final_checks(operation); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (!operation->is_encrypt) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_driver_wrapper_aead_finish(operation, ciphertext, + ciphertext_size, + ciphertext_length, + tag, tag_size, tag_length); + +exit: + + + /* In case the operation fails and the user fails to check for failure or + * the zero tag size, make sure the tag is set to something implausible. + * Even if the operation succeeds, make sure we clear the rest of the + * buffer to prevent potential leakage of anything previously placed in + * the same buffer.*/ + psa_wipe_tag_output_buffer(tag, status, tag_size, *tag_length); + + psa_aead_abort(operation); + + return status; +} + +/* Finish authenticating and decrypting a message in a multipart AEAD + operation.*/ +psa_status_t psa_aead_verify(psa_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *plaintext_length = 0; + + status = psa_aead_final_checks(operation); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (operation->is_encrypt) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_driver_wrapper_aead_verify(operation, plaintext, + plaintext_size, + plaintext_length, + tag, tag_length); + +exit: + psa_aead_abort(operation); + + return status; +} + +/* Abort an AEAD operation. */ +psa_status_t psa_aead_abort(psa_aead_operation_t *operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->id == 0) { + /* The object has (apparently) been initialized but it is not (yet) + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + return PSA_SUCCESS; + } + + status = psa_driver_wrapper_aead_abort(operation); + + memset(operation, 0, sizeof(*operation)); + + return status; +} + +/****************************************************************/ +/* Generators */ +/****************************************************************/ + +#if defined(BUILTIN_ALG_ANY_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) || \ + defined(PSA_HAVE_SOFT_PBKDF2) +#define AT_LEAST_ONE_BUILTIN_KDF +#endif /* At least one builtin KDF */ + +#if defined(BUILTIN_ALG_ANY_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +static psa_status_t psa_key_derivation_start_hmac( + psa_mac_operation_t *operation, + psa_algorithm_t hash_alg, + const uint8_t *hmac_key, + size_t hmac_key_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_type(&attributes, PSA_KEY_TYPE_HMAC); + psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(hmac_key_length)); + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); + + operation->is_sign = 1; + operation->mac_size = PSA_HASH_LENGTH(hash_alg); + + status = psa_driver_wrapper_mac_sign_setup(operation, + &attributes, + hmac_key, hmac_key_length, + PSA_ALG_HMAC(hash_alg)); + + psa_reset_key_attributes(&attributes); + return status; +} +#endif /* KDF algorithms reliant on HMAC */ + +#define HKDF_STATE_INIT 0 /* no input yet */ +#define HKDF_STATE_STARTED 1 /* got salt */ +#define HKDF_STATE_KEYED 2 /* got key */ +#define HKDF_STATE_OUTPUT 3 /* output started */ + +static psa_algorithm_t psa_key_derivation_get_kdf_alg( + const psa_key_derivation_operation_t *operation) +{ + if (PSA_ALG_IS_KEY_AGREEMENT(operation->alg)) { + return PSA_ALG_KEY_AGREEMENT_GET_KDF(operation->alg); + } else { + return operation->alg; + } +} + +psa_status_t psa_key_derivation_abort(psa_key_derivation_operation_t *operation) +{ + psa_status_t status = PSA_SUCCESS; + psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); + if (kdf_alg == 0) { + /* The object has (apparently) been initialized but it is not + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + } else +#if defined(BUILTIN_ALG_ANY_HKDF) + if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { + mbedtls_free(operation->ctx.hkdf.info); + status = psa_mac_abort(&operation->ctx.hkdf.hmac); + } else +#endif /* BUILTIN_ALG_ANY_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if (PSA_ALG_IS_TLS12_PRF(kdf_alg) || + /* TLS-1.2 PSK-to-MS KDF uses the same core as TLS-1.2 PRF */ + PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { + if (operation->ctx.tls12_prf.secret != NULL) { + mbedtls_zeroize_and_free(operation->ctx.tls12_prf.secret, + operation->ctx.tls12_prf.secret_length); + } + + if (operation->ctx.tls12_prf.seed != NULL) { + mbedtls_zeroize_and_free(operation->ctx.tls12_prf.seed, + operation->ctx.tls12_prf.seed_length); + } + + if (operation->ctx.tls12_prf.label != NULL) { + mbedtls_zeroize_and_free(operation->ctx.tls12_prf.label, + operation->ctx.tls12_prf.label_length); + } +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if (operation->ctx.tls12_prf.other_secret != NULL) { + mbedtls_zeroize_and_free(operation->ctx.tls12_prf.other_secret, + operation->ctx.tls12_prf.other_secret_length); + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + status = PSA_SUCCESS; + + /* We leave the fields Ai and output_block to be erased safely by the + * mbedtls_platform_zeroize() in the end of this function. */ + } else +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + mbedtls_platform_zeroize(operation->ctx.tls12_ecjpake_to_pms.data, + sizeof(operation->ctx.tls12_ecjpake_to_pms.data)); + } else +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) */ +#if defined(PSA_HAVE_SOFT_PBKDF2) + if (PSA_ALG_IS_PBKDF2(kdf_alg)) { + if (operation->ctx.pbkdf2.salt != NULL) { + mbedtls_zeroize_and_free(operation->ctx.pbkdf2.salt, + operation->ctx.pbkdf2.salt_length); + } + + status = PSA_SUCCESS; + } else +#endif /* defined(PSA_HAVE_SOFT_PBKDF2) */ + { + status = PSA_ERROR_BAD_STATE; + } + mbedtls_platform_zeroize(operation, sizeof(*operation)); + return status; +} + +psa_status_t psa_key_derivation_get_capacity(const psa_key_derivation_operation_t *operation, + size_t *capacity) +{ + if (operation->alg == 0) { + /* This is a blank key derivation operation. */ + return PSA_ERROR_BAD_STATE; + } + + *capacity = operation->capacity; + return PSA_SUCCESS; +} + +psa_status_t psa_key_derivation_set_capacity(psa_key_derivation_operation_t *operation, + size_t capacity) +{ + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + if (capacity > operation->capacity) { + return PSA_ERROR_INVALID_ARGUMENT; + } + operation->capacity = capacity; + return PSA_SUCCESS; +} + +#if defined(BUILTIN_ALG_ANY_HKDF) +/* Read some bytes from an HKDF-based operation. */ +static psa_status_t psa_key_derivation_hkdf_read(psa_hkdf_key_derivation_t *hkdf, + psa_algorithm_t kdf_alg, + uint8_t *output, + size_t output_length) +{ + psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); + uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); + size_t hmac_output_length; + psa_status_t status; +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + const uint8_t last_block = PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) ? 0 : 0xff; +#else + const uint8_t last_block = 0xff; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ + + if (hkdf->state < HKDF_STATE_KEYED || + (!hkdf->info_set +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + && !PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ + )) { + return PSA_ERROR_BAD_STATE; + } + hkdf->state = HKDF_STATE_OUTPUT; + + while (output_length != 0) { + /* Copy what remains of the current block */ + uint8_t n = hash_length - hkdf->offset_in_block; + if (n > output_length) { + n = (uint8_t) output_length; + } + memcpy(output, hkdf->output_block + hkdf->offset_in_block, n); + output += n; + output_length -= n; + hkdf->offset_in_block += n; + if (output_length == 0) { + break; + } + /* We can't be wanting more output after the last block, otherwise + * the capacity check in psa_key_derivation_output_bytes() would have + * prevented this call. It could happen only if the operation + * object was corrupted or if this function is called directly + * inside the library. */ + if (hkdf->block_number == last_block) { + return PSA_ERROR_BAD_STATE; + } + + /* We need a new block */ + ++hkdf->block_number; + hkdf->offset_in_block = 0; + + status = psa_key_derivation_start_hmac(&hkdf->hmac, + hash_alg, + hkdf->prk, + hash_length); + if (status != PSA_SUCCESS) { + return status; + } + + if (hkdf->block_number != 1) { + status = psa_mac_update(&hkdf->hmac, + hkdf->output_block, + hash_length); + if (status != PSA_SUCCESS) { + return status; + } + } + status = psa_mac_update(&hkdf->hmac, + hkdf->info, + hkdf->info_length); + if (status != PSA_SUCCESS) { + return status; + } + status = psa_mac_update(&hkdf->hmac, + &hkdf->block_number, 1); + if (status != PSA_SUCCESS) { + return status; + } + status = psa_mac_sign_finish(&hkdf->hmac, + hkdf->output_block, + sizeof(hkdf->output_block), + &hmac_output_length); + if (status != PSA_SUCCESS) { + return status; + } + } + + return PSA_SUCCESS; +} +#endif /* BUILTIN_ALG_ANY_HKDF */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +static psa_status_t psa_key_derivation_tls12_prf_generate_next_block( + psa_tls12_prf_key_derivation_t *tls12_prf, + psa_algorithm_t alg) +{ + psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(alg); + uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); + psa_mac_operation_t hmac = PSA_MAC_OPERATION_INIT; + size_t hmac_output_length; + psa_status_t status, cleanup_status; + + /* We can't be wanting more output after block 0xff, otherwise + * the capacity check in psa_key_derivation_output_bytes() would have + * prevented this call. It could happen only if the operation + * object was corrupted or if this function is called directly + * inside the library. */ + if (tls12_prf->block_number == 0xff) { + return PSA_ERROR_CORRUPTION_DETECTED; + } + + /* We need a new block */ + ++tls12_prf->block_number; + tls12_prf->left_in_block = hash_length; + + /* Recall the definition of the TLS-1.2-PRF from RFC 5246: + * + * PRF(secret, label, seed) = P_(secret, label + seed) + * + * P_hash(secret, seed) = HMAC_hash(secret, A(1) + seed) + + * HMAC_hash(secret, A(2) + seed) + + * HMAC_hash(secret, A(3) + seed) + ... + * + * A(0) = seed + * A(i) = HMAC_hash(secret, A(i-1)) + * + * The `psa_tls12_prf_key_derivation` structure saves the block + * `HMAC_hash(secret, A(i) + seed)` from which the output + * is currently extracted as `output_block` and where i is + * `block_number`. + */ + + status = psa_key_derivation_start_hmac(&hmac, + hash_alg, + tls12_prf->secret, + tls12_prf->secret_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + /* Calculate A(i) where i = tls12_prf->block_number. */ + if (tls12_prf->block_number == 1) { + /* A(1) = HMAC_hash(secret, A(0)), where A(0) = seed. (The RFC overloads + * the variable seed and in this instance means it in the context of the + * P_hash function, where seed = label + seed.) */ + status = psa_mac_update(&hmac, + tls12_prf->label, + tls12_prf->label_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&hmac, + tls12_prf->seed, + tls12_prf->seed_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + } else { + /* A(i) = HMAC_hash(secret, A(i-1)) */ + status = psa_mac_update(&hmac, tls12_prf->Ai, hash_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + } + + status = psa_mac_sign_finish(&hmac, + tls12_prf->Ai, hash_length, + &hmac_output_length); + if (hmac_output_length != hash_length) { + status = PSA_ERROR_CORRUPTION_DETECTED; + } + if (status != PSA_SUCCESS) { + goto cleanup; + } + + /* Calculate HMAC_hash(secret, A(i) + label + seed). */ + status = psa_key_derivation_start_hmac(&hmac, + hash_alg, + tls12_prf->secret, + tls12_prf->secret_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&hmac, tls12_prf->Ai, hash_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&hmac, tls12_prf->label, tls12_prf->label_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&hmac, tls12_prf->seed, tls12_prf->seed_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_sign_finish(&hmac, + tls12_prf->output_block, hash_length, + &hmac_output_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + +cleanup: + cleanup_status = psa_mac_abort(&hmac); + if (status == PSA_SUCCESS && cleanup_status != PSA_SUCCESS) { + status = cleanup_status; + } + + return status; +} + +static psa_status_t psa_key_derivation_tls12_prf_read( + psa_tls12_prf_key_derivation_t *tls12_prf, + psa_algorithm_t alg, + uint8_t *output, + size_t output_length) +{ + psa_algorithm_t hash_alg = PSA_ALG_TLS12_PRF_GET_HASH(alg); + uint8_t hash_length = PSA_HASH_LENGTH(hash_alg); + psa_status_t status; + uint8_t offset, length; + + switch (tls12_prf->state) { + case PSA_TLS12_PRF_STATE_LABEL_SET: + tls12_prf->state = PSA_TLS12_PRF_STATE_OUTPUT; + break; + case PSA_TLS12_PRF_STATE_OUTPUT: + break; + default: + return PSA_ERROR_BAD_STATE; + } + + while (output_length != 0) { + /* Check if we have fully processed the current block. */ + if (tls12_prf->left_in_block == 0) { + status = psa_key_derivation_tls12_prf_generate_next_block(tls12_prf, + alg); + if (status != PSA_SUCCESS) { + return status; + } + + continue; + } + + if (tls12_prf->left_in_block > output_length) { + length = (uint8_t) output_length; + } else { + length = tls12_prf->left_in_block; + } + + offset = hash_length - tls12_prf->left_in_block; + memcpy(output, tls12_prf->output_block + offset, length); + output += length; + output_length -= length; + tls12_prf->left_in_block -= length; + } + + return PSA_SUCCESS; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) +static psa_status_t psa_key_derivation_tls12_ecjpake_to_pms_read( + psa_tls12_ecjpake_to_pms_t *ecjpake, + uint8_t *output, + size_t output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t output_size = 0; + + if (output_length != 32) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_hash_compute(PSA_ALG_SHA_256, ecjpake->data, + PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE, output, output_length, + &output_size); + if (status != PSA_SUCCESS) { + return status; + } + + if (output_size != output_length) { + return PSA_ERROR_GENERIC_ERROR; + } + + return PSA_SUCCESS; +} +#endif + +#if defined(PSA_HAVE_SOFT_PBKDF2) +static psa_status_t psa_key_derivation_pbkdf2_generate_block( + psa_pbkdf2_key_derivation_t *pbkdf2, + psa_algorithm_t prf_alg, + uint8_t prf_output_length, + psa_key_attributes_t *attributes) +{ + psa_status_t status; + psa_mac_operation_t mac_operation = PSA_MAC_OPERATION_INIT; + size_t mac_output_length; + uint8_t U_i[PSA_MAC_MAX_SIZE]; + uint8_t *U_accumulator = pbkdf2->output_block; + uint64_t i; + uint8_t block_counter[4]; + + mac_operation.is_sign = 1; + mac_operation.mac_size = prf_output_length; + MBEDTLS_PUT_UINT32_BE(pbkdf2->block_number, block_counter, 0); + + status = psa_driver_wrapper_mac_sign_setup(&mac_operation, + attributes, + pbkdf2->password, + pbkdf2->password_length, + prf_alg); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&mac_operation, pbkdf2->salt, pbkdf2->salt_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_update(&mac_operation, block_counter, sizeof(block_counter)); + if (status != PSA_SUCCESS) { + goto cleanup; + } + status = psa_mac_sign_finish(&mac_operation, U_i, sizeof(U_i), + &mac_output_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + if (mac_output_length != prf_output_length) { + status = PSA_ERROR_CORRUPTION_DETECTED; + goto cleanup; + } + + memcpy(U_accumulator, U_i, prf_output_length); + + for (i = 1; i < pbkdf2->input_cost; i++) { + /* We are passing prf_output_length as mac_size because the driver + * function directly sets mac_output_length as mac_size upon success. + * See https://github.com/Mbed-TLS/mbedtls/issues/7801 */ + status = psa_driver_wrapper_mac_compute(attributes, + pbkdf2->password, + pbkdf2->password_length, + prf_alg, U_i, prf_output_length, + U_i, prf_output_length, + &mac_output_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + mbedtls_xor(U_accumulator, U_accumulator, U_i, prf_output_length); + } + +cleanup: + /* Zeroise buffers to clear sensitive data from memory. */ + mbedtls_platform_zeroize(U_i, PSA_MAC_MAX_SIZE); + return status; +} + +static psa_status_t psa_key_derivation_pbkdf2_read( + psa_pbkdf2_key_derivation_t *pbkdf2, + psa_algorithm_t kdf_alg, + uint8_t *output, + size_t output_length) +{ + psa_status_t status; + psa_algorithm_t prf_alg; + uint8_t prf_output_length; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(pbkdf2->password_length)); + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_MESSAGE); + + if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { + prf_alg = PSA_ALG_HMAC(PSA_ALG_PBKDF2_HMAC_GET_HASH(kdf_alg)); + prf_output_length = PSA_HASH_LENGTH(prf_alg); + psa_set_key_type(&attributes, PSA_KEY_TYPE_HMAC); + } else if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { + prf_alg = PSA_ALG_CMAC; + prf_output_length = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + } else { + return PSA_ERROR_INVALID_ARGUMENT; + } + + switch (pbkdf2->state) { + case PSA_PBKDF2_STATE_PASSWORD_SET: + /* Initially we need a new block so bytes_used is equal to block size*/ + pbkdf2->bytes_used = prf_output_length; + pbkdf2->state = PSA_PBKDF2_STATE_OUTPUT; + break; + case PSA_PBKDF2_STATE_OUTPUT: + break; + default: + return PSA_ERROR_BAD_STATE; + } + + while (output_length != 0) { + uint8_t n = prf_output_length - pbkdf2->bytes_used; + if (n > output_length) { + n = (uint8_t) output_length; + } + memcpy(output, pbkdf2->output_block + pbkdf2->bytes_used, n); + output += n; + output_length -= n; + pbkdf2->bytes_used += n; + + if (output_length == 0) { + break; + } + + /* We need a new block */ + pbkdf2->bytes_used = 0; + pbkdf2->block_number++; + + status = psa_key_derivation_pbkdf2_generate_block(pbkdf2, prf_alg, + prf_output_length, + &attributes); + if (status != PSA_SUCCESS) { + return status; + } + } + + return PSA_SUCCESS; +} +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + +psa_status_t psa_key_derivation_output_bytes( + psa_key_derivation_operation_t *operation, + uint8_t *output, + size_t output_length) +{ + psa_status_t status; + psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); + + if (operation->alg == 0) { + /* This is a blank operation. */ + return PSA_ERROR_BAD_STATE; + } + + if (output_length > operation->capacity) { + operation->capacity = 0; + /* Go through the error path to wipe all confidential data now + * that the operation object is useless. */ + status = PSA_ERROR_INSUFFICIENT_DATA; + goto exit; + } + if (output_length == 0 && operation->capacity == 0) { + /* Edge case: this is a finished operation, and 0 bytes + * were requested. The right error in this case could + * be either INSUFFICIENT_CAPACITY or BAD_STATE. Return + * INSUFFICIENT_CAPACITY, which is right for a finished + * operation, for consistency with the case when + * output_length > 0. */ + return PSA_ERROR_INSUFFICIENT_DATA; + } + operation->capacity -= output_length; + +#if defined(BUILTIN_ALG_ANY_HKDF) + if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { + status = psa_key_derivation_hkdf_read(&operation->ctx.hkdf, kdf_alg, + output, output_length); + } else +#endif /* BUILTIN_ALG_ANY_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if (PSA_ALG_IS_TLS12_PRF(kdf_alg) || + PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { + status = psa_key_derivation_tls12_prf_read(&operation->ctx.tls12_prf, + kdf_alg, output, + output_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + status = psa_key_derivation_tls12_ecjpake_to_pms_read( + &operation->ctx.tls12_ecjpake_to_pms, output, output_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ +#if defined(PSA_HAVE_SOFT_PBKDF2) + if (PSA_ALG_IS_PBKDF2(kdf_alg)) { + status = psa_key_derivation_pbkdf2_read(&operation->ctx.pbkdf2, kdf_alg, + output, output_length); + } else +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + + { + (void) kdf_alg; + return PSA_ERROR_BAD_STATE; + } + +exit: + if (status != PSA_SUCCESS) { + /* Preserve the algorithm upon errors, but clear all sensitive state. + * This allows us to differentiate between exhausted operations and + * blank operations, so we can return PSA_ERROR_BAD_STATE on blank + * operations. */ + psa_algorithm_t alg = operation->alg; + psa_key_derivation_abort(operation); + operation->alg = alg; + memset(output, '!', output_length); + } + return status; +} + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) +static void psa_des_set_key_parity(uint8_t *data, size_t data_size) +{ + if (data_size >= 8) { + mbedtls_des_key_set_parity(data); + } + if (data_size >= 16) { + mbedtls_des_key_set_parity(data + 8); + } + if (data_size >= 24) { + mbedtls_des_key_set_parity(data + 16); + } +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES */ + +/* + * ECC keys on a Weierstrass elliptic curve require the generation + * of a private key which is an integer + * in the range [1, N - 1], where N is the boundary of the private key domain: + * N is the prime p for Diffie-Hellman, or the order of the + * curve’s base point for ECC. + * + * Let m be the bit size of N, such that 2^m > N >= 2^(m-1). + * This function generates the private key using the following process: + * + * 1. Draw a byte string of length ceiling(m/8) bytes. + * 2. If m is not a multiple of 8, set the most significant + * (8 * ceiling(m/8) - m) bits of the first byte in the string to zero. + * 3. Convert the string to integer k by decoding it as a big-endian byte string. + * 4. If k > N - 2, discard the result and return to step 1. + * 5. Output k + 1 as the private key. + * + * This method allows compliance to NIST standards, specifically the methods titled + * Key-Pair Generation by Testing Candidates in the following publications: + * - NIST Special Publication 800-56A: Recommendation for Pair-Wise Key-Establishment + * Schemes Using Discrete Logarithm Cryptography [SP800-56A] §5.6.1.1.4 for + * Diffie-Hellman keys. + * + * - [SP800-56A] §5.6.1.2.2 or FIPS Publication 186-4: Digital Signature + * Standard (DSS) [FIPS186-4] §B.4.2 for elliptic curve keys. + * + * Note: Function allocates memory for *data buffer, so given *data should be + * always NULL. + */ +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) +static psa_status_t psa_generate_derived_ecc_key_weierstrass_helper( + psa_key_slot_t *slot, + size_t bits, + psa_key_derivation_operation_t *operation, + uint8_t **data + ) +{ + unsigned key_out_of_range = 1; + mbedtls_mpi k; + mbedtls_mpi diff_N_2; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t m; + size_t m_bytes; + + mbedtls_mpi_init(&k); + mbedtls_mpi_init(&diff_N_2); + + psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY( + slot->attr.type); + mbedtls_ecp_group_id grp_id = + mbedtls_ecc_group_of_psa(curve, bits, 0); + + if (grp_id == MBEDTLS_ECP_DP_NONE) { + ret = MBEDTLS_ERR_ASN1_INVALID_DATA; + goto cleanup; + } + + mbedtls_ecp_group ecp_group; + mbedtls_ecp_group_init(&ecp_group); + + MBEDTLS_MPI_CHK(mbedtls_ecp_group_load(&ecp_group, grp_id)); + + /* N is the boundary of the private key domain (ecp_group.N). */ + /* Let m be the bit size of N. */ + m = ecp_group.nbits; + + m_bytes = PSA_BITS_TO_BYTES(m); + + /* Calculate N - 2 - it will be needed later. */ + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&diff_N_2, &ecp_group.N, 2)); + + /* Note: This function is always called with *data == NULL and it + * allocates memory for the data buffer. */ + *data = mbedtls_calloc(1, m_bytes); + if (*data == NULL) { + ret = MBEDTLS_ERR_ASN1_ALLOC_FAILED; + goto cleanup; + } + + while (key_out_of_range) { + /* 1. Draw a byte string of length ceiling(m/8) bytes. */ + if ((status = psa_key_derivation_output_bytes(operation, *data, m_bytes)) != 0) { + goto cleanup; + } + + /* 2. If m is not a multiple of 8 */ + if (m % 8 != 0) { + /* Set the most significant + * (8 * ceiling(m/8) - m) bits of the first byte in + * the string to zero. + */ + uint8_t clear_bit_mask = (1 << (m % 8)) - 1; + (*data)[0] &= clear_bit_mask; + } + + /* 3. Convert the string to integer k by decoding it as a + * big-endian byte string. + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&k, *data, m_bytes)); + + /* 4. If k > N - 2, discard the result and return to step 1. + * Result of comparison is returned. When it indicates error + * then this function is called again. + */ + MBEDTLS_MPI_CHK(mbedtls_mpi_lt_mpi_ct(&diff_N_2, &k, &key_out_of_range)); + } + + /* 5. Output k + 1 as the private key. */ + MBEDTLS_MPI_CHK(mbedtls_mpi_add_int(&k, &k, 1)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&k, *data, m_bytes)); +cleanup: + if (ret != 0) { + status = mbedtls_to_psa_error(ret); + } + if (status != PSA_SUCCESS) { + mbedtls_free(*data); + *data = NULL; + } + mbedtls_mpi_free(&k); + mbedtls_mpi_free(&diff_N_2); + return status; +} + +/* ECC keys on a Montgomery elliptic curve draws a byte string whose length + * is determined by the curve, and sets the mandatory bits accordingly. That is: + * + * - Curve25519 (PSA_ECC_FAMILY_MONTGOMERY, 255 bits): + * draw a 32-byte string and process it as specified in + * Elliptic Curves for Security [RFC7748] §5. + * + * - Curve448 (PSA_ECC_FAMILY_MONTGOMERY, 448 bits): + * draw a 56-byte string and process it as specified in [RFC7748] §5. + * + * Note: Function allocates memory for *data buffer, so given *data should be + * always NULL. + */ + +static psa_status_t psa_generate_derived_ecc_key_montgomery_helper( + size_t bits, + psa_key_derivation_operation_t *operation, + uint8_t **data + ) +{ + size_t output_length; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + switch (bits) { + case 255: + output_length = 32; + break; + case 448: + output_length = 56; + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + break; + } + + *data = mbedtls_calloc(1, output_length); + + if (*data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + status = psa_key_derivation_output_bytes(operation, *data, output_length); + + if (status != PSA_SUCCESS) { + return status; + } + + switch (bits) { + case 255: + (*data)[0] &= 248; + (*data)[31] &= 127; + (*data)[31] |= 64; + break; + case 448: + (*data)[0] &= 252; + (*data)[55] |= 128; + break; + default: + return PSA_ERROR_CORRUPTION_DETECTED; + break; + } + + return status; +} +#else /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ +static psa_status_t psa_generate_derived_ecc_key_weierstrass_helper( + psa_key_slot_t *slot, size_t bits, + psa_key_derivation_operation_t *operation, uint8_t **data) +{ + (void) slot; + (void) bits; + (void) operation; + (void) data; + return PSA_ERROR_NOT_SUPPORTED; +} + +static psa_status_t psa_generate_derived_ecc_key_montgomery_helper( + size_t bits, psa_key_derivation_operation_t *operation, uint8_t **data) +{ + (void) bits; + (void) operation; + (void) data; + return PSA_ERROR_NOT_SUPPORTED; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE */ + +static psa_status_t psa_generate_derived_key_internal( + psa_key_slot_t *slot, + size_t bits, + psa_key_derivation_operation_t *operation) +{ + uint8_t *data = NULL; + size_t bytes = PSA_BITS_TO_BYTES(bits); + size_t storage_size = bytes; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_attributes_t attributes; + + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(slot->attr.type)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) + if (PSA_KEY_TYPE_IS_ECC(slot->attr.type)) { + psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY(slot->attr.type); + if (PSA_ECC_FAMILY_IS_WEIERSTRASS(curve)) { + /* Weierstrass elliptic curve */ + status = psa_generate_derived_ecc_key_weierstrass_helper(slot, bits, operation, &data); + if (status != PSA_SUCCESS) { + goto exit; + } + } else { + /* Montgomery elliptic curve */ + status = psa_generate_derived_ecc_key_montgomery_helper(bits, operation, &data); + if (status != PSA_SUCCESS) { + goto exit; + } + } + } else +#endif /* defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_DERIVE) || + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_DERIVE) */ + if (key_type_is_raw_bytes(slot->attr.type)) { + if (bits % 8 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + data = mbedtls_calloc(1, bytes); + if (data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + status = psa_key_derivation_output_bytes(operation, data, bytes); + if (status != PSA_SUCCESS) { + goto exit; + } +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) + if (slot->attr.type == PSA_KEY_TYPE_DES) { + psa_des_set_key_parity(data, bytes); + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) */ + } else { + return PSA_ERROR_NOT_SUPPORTED; + } + + slot->attr.bits = (psa_key_bits_t) bits; + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + if (psa_key_lifetime_is_external(attributes.core.lifetime)) { + status = psa_driver_wrapper_get_key_buffer_size(&attributes, + &storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + } + status = psa_allocate_buffer_to_slot(slot, storage_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_driver_wrapper_import_key(&attributes, + data, bytes, + slot->key.data, + slot->key.bytes, + &slot->key.bytes, &bits); + if (bits != slot->attr.bits) { + status = PSA_ERROR_INVALID_ARGUMENT; + } + +exit: + mbedtls_free(data); + return status; +} + +psa_status_t psa_key_derivation_output_key(const psa_key_attributes_t *attributes, + psa_key_derivation_operation_t *operation, + mbedtls_svc_key_id_t *key) +{ + psa_status_t status; + psa_key_slot_t *slot = NULL; + psa_se_drv_table_entry_t *driver = NULL; + + *key = MBEDTLS_SVC_KEY_ID_INIT; + + /* Reject any attempt to create a zero-length key so that we don't + * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ + if (psa_get_key_bits(attributes) > PSA_MAX_KEY_BITS) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (psa_get_key_bits(attributes) == 0 || + psa_get_key_bits(attributes) % 8 != 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (!key_type_is_raw_bytes(psa_get_key_type(attributes))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (operation->alg == PSA_ALG_NONE) { + return PSA_ERROR_BAD_STATE; + } + + if (!operation->can_output_key) { + return PSA_ERROR_NOT_PERMITTED; + } + + status = psa_start_key_creation(PSA_KEY_CREATION_DERIVE, attributes, + &slot, &driver); +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + if (driver != NULL) { + /* Deriving a key in a secure element is not implemented yet. */ + status = PSA_ERROR_NOT_SUPPORTED; + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + if (status == PSA_SUCCESS) { + status = psa_generate_derived_key_internal(slot, + attributes->core.bits, + operation); + } + if (status == PSA_SUCCESS) { + status = psa_finish_key_creation(slot, driver, key); + } + if (status != PSA_SUCCESS) { + psa_fail_key_creation(slot, driver); + } + + return status; +} + + + +/****************************************************************/ +/* Key derivation */ +/****************************************************************/ + +#if defined(AT_LEAST_ONE_BUILTIN_KDF) +static int is_kdf_alg_supported(psa_algorithm_t kdf_alg) +{ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) + if (PSA_ALG_IS_HKDF(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) + if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) + if (PSA_ALG_IS_TLS12_PRF(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if (PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) + if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { + return 1; + } +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) + if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { + return 1; + } +#endif + return 0; +} + +static psa_status_t psa_hash_try_support(psa_algorithm_t alg) +{ + psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; + psa_status_t status = psa_hash_setup(&operation, alg); + psa_hash_abort(&operation); + return status; +} + +static psa_status_t psa_key_derivation_setup_kdf( + psa_key_derivation_operation_t *operation, + psa_algorithm_t kdf_alg) +{ + /* Make sure that operation->ctx is properly zero-initialised. (Macro + * initialisers for this union leave some bytes unspecified.) */ + memset(&operation->ctx, 0, sizeof(operation->ctx)); + + /* Make sure that kdf_alg is a supported key derivation algorithm. */ + if (!is_kdf_alg_supported(kdf_alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* All currently supported key derivation algorithms (apart from + * ecjpake to pms and pbkdf2_aes_cmac_128) are based on a hash algorithm. */ + psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); + size_t hash_size = PSA_HASH_LENGTH(hash_alg); + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + hash_size = PSA_HASH_LENGTH(PSA_ALG_SHA_256); + } else if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { + hash_size = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); + } else { + if (hash_size == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* Make sure that hash_alg is a supported hash algorithm. Otherwise + * we might fail later, which is somewhat unfriendly and potentially + * risk-prone. */ + psa_status_t status = psa_hash_try_support(hash_alg); + if (status != PSA_SUCCESS) { + return status; + } + } + + if ((PSA_ALG_IS_TLS12_PRF(kdf_alg) || + PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) && + !(hash_alg == PSA_ALG_SHA_256 || hash_alg == PSA_ALG_SHA_384)) { + return PSA_ERROR_NOT_SUPPORTED; + } +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg) || + (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS)) { + operation->capacity = hash_size; + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT || + MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ + operation->capacity = 255 * hash_size; + return PSA_SUCCESS; +} + +static psa_status_t psa_key_agreement_try_support(psa_algorithm_t alg) +{ +#if defined(PSA_WANT_ALG_ECDH) + if (alg == PSA_ALG_ECDH) { + return PSA_SUCCESS; + } +#endif +#if defined(PSA_WANT_ALG_FFDH) + if (alg == PSA_ALG_FFDH) { + return PSA_SUCCESS; + } +#endif + (void) alg; + return PSA_ERROR_NOT_SUPPORTED; +} + +static int psa_key_derivation_allows_free_form_secret_input( + psa_algorithm_t kdf_alg) +{ +#if defined(PSA_WANT_ALG_TLS12_ECJPAKE_TO_PMS) + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + return 0; + } +#endif + (void) kdf_alg; + return 1; +} +#endif /* AT_LEAST_ONE_BUILTIN_KDF */ + +psa_status_t psa_key_derivation_setup(psa_key_derivation_operation_t *operation, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->alg != 0) { + return PSA_ERROR_BAD_STATE; + } + + if (PSA_ALG_IS_RAW_KEY_AGREEMENT(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } else if (PSA_ALG_IS_KEY_AGREEMENT(alg)) { +#if defined(AT_LEAST_ONE_BUILTIN_KDF) + psa_algorithm_t kdf_alg = PSA_ALG_KEY_AGREEMENT_GET_KDF(alg); + psa_algorithm_t ka_alg = PSA_ALG_KEY_AGREEMENT_GET_BASE(alg); + status = psa_key_agreement_try_support(ka_alg); + if (status != PSA_SUCCESS) { + return status; + } + if (!psa_key_derivation_allows_free_form_secret_input(kdf_alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + status = psa_key_derivation_setup_kdf(operation, kdf_alg); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* AT_LEAST_ONE_BUILTIN_KDF */ + } else if (PSA_ALG_IS_KEY_DERIVATION(alg)) { +#if defined(AT_LEAST_ONE_BUILTIN_KDF) + status = psa_key_derivation_setup_kdf(operation, alg); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* AT_LEAST_ONE_BUILTIN_KDF */ + } else { + status = PSA_ERROR_INVALID_ARGUMENT; + } + + if (status == PSA_SUCCESS) { + operation->alg = alg; + } + return status; +} + +#if defined(BUILTIN_ALG_ANY_HKDF) +static psa_status_t psa_hkdf_input(psa_hkdf_key_derivation_t *hkdf, + psa_algorithm_t kdf_alg, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH(kdf_alg); + psa_status_t status; + switch (step) { + case PSA_KEY_DERIVATION_INPUT_SALT: +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) + if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ + if (hkdf->state != HKDF_STATE_INIT) { + return PSA_ERROR_BAD_STATE; + } else { + status = psa_key_derivation_start_hmac(&hkdf->hmac, + hash_alg, + data, data_length); + if (status != PSA_SUCCESS) { + return status; + } + hkdf->state = HKDF_STATE_STARTED; + return PSA_SUCCESS; + } + case PSA_KEY_DERIVATION_INPUT_SECRET: +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) + if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg)) { + /* We shouldn't be in different state as HKDF_EXPAND only allows + * two inputs: SECRET (this case) and INFO which does not modify + * the state. It could happen only if the hkdf + * object was corrupted. */ + if (hkdf->state != HKDF_STATE_INIT) { + return PSA_ERROR_BAD_STATE; + } + + /* Allow only input that fits expected prk size */ + if (data_length != PSA_HASH_LENGTH(hash_alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + memcpy(hkdf->prk, data, data_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND */ + { + /* HKDF: If no salt was provided, use an empty salt. + * HKDF-EXTRACT: salt is mandatory. */ + if (hkdf->state == HKDF_STATE_INIT) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { + return PSA_ERROR_BAD_STATE; + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ + status = psa_key_derivation_start_hmac(&hkdf->hmac, + hash_alg, + NULL, 0); + if (status != PSA_SUCCESS) { + return status; + } + hkdf->state = HKDF_STATE_STARTED; + } + if (hkdf->state != HKDF_STATE_STARTED) { + return PSA_ERROR_BAD_STATE; + } + status = psa_mac_update(&hkdf->hmac, + data, data_length); + if (status != PSA_SUCCESS) { + return status; + } + status = psa_mac_sign_finish(&hkdf->hmac, + hkdf->prk, + sizeof(hkdf->prk), + &data_length); + if (status != PSA_SUCCESS) { + return status; + } + } + + hkdf->state = HKDF_STATE_KEYED; + hkdf->block_number = 0; +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { + /* The only block of output is the PRK. */ + memcpy(hkdf->output_block, hkdf->prk, PSA_HASH_LENGTH(hash_alg)); + hkdf->offset_in_block = 0; + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ + { + /* Block 0 is empty, and the next block will be + * generated by psa_key_derivation_hkdf_read(). */ + hkdf->offset_in_block = PSA_HASH_LENGTH(hash_alg); + } + + return PSA_SUCCESS; + case PSA_KEY_DERIVATION_INPUT_INFO: +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT) + if (PSA_ALG_IS_HKDF_EXTRACT(kdf_alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXPAND) + if (PSA_ALG_IS_HKDF_EXPAND(kdf_alg) && + hkdf->state == HKDF_STATE_INIT) { + return PSA_ERROR_BAD_STATE; + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF_EXTRACT */ + if (hkdf->state == HKDF_STATE_OUTPUT) { + return PSA_ERROR_BAD_STATE; + } + if (hkdf->info_set) { + return PSA_ERROR_BAD_STATE; + } + hkdf->info_length = data_length; + if (data_length != 0) { + hkdf->info = mbedtls_calloc(1, data_length); + if (hkdf->info == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memcpy(hkdf->info, data, data_length); + } + hkdf->info_set = 1; + return PSA_SUCCESS; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } +} +#endif /* BUILTIN_ALG_ANY_HKDF */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +static psa_status_t psa_tls12_prf_set_seed(psa_tls12_prf_key_derivation_t *prf, + const uint8_t *data, + size_t data_length) +{ + if (prf->state != PSA_TLS12_PRF_STATE_INIT) { + return PSA_ERROR_BAD_STATE; + } + + if (data_length != 0) { + prf->seed = mbedtls_calloc(1, data_length); + if (prf->seed == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + memcpy(prf->seed, data, data_length); + prf->seed_length = data_length; + } + + prf->state = PSA_TLS12_PRF_STATE_SEED_SET; + + return PSA_SUCCESS; +} + +static psa_status_t psa_tls12_prf_set_key(psa_tls12_prf_key_derivation_t *prf, + const uint8_t *data, + size_t data_length) +{ + if (prf->state != PSA_TLS12_PRF_STATE_SEED_SET && + prf->state != PSA_TLS12_PRF_STATE_OTHER_KEY_SET) { + return PSA_ERROR_BAD_STATE; + } + + if (data_length != 0) { + prf->secret = mbedtls_calloc(1, data_length); + if (prf->secret == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + memcpy(prf->secret, data, data_length); + prf->secret_length = data_length; + } + + prf->state = PSA_TLS12_PRF_STATE_KEY_SET; + + return PSA_SUCCESS; +} + +static psa_status_t psa_tls12_prf_set_label(psa_tls12_prf_key_derivation_t *prf, + const uint8_t *data, + size_t data_length) +{ + if (prf->state != PSA_TLS12_PRF_STATE_KEY_SET) { + return PSA_ERROR_BAD_STATE; + } + + if (data_length != 0) { + prf->label = mbedtls_calloc(1, data_length); + if (prf->label == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + memcpy(prf->label, data, data_length); + prf->label_length = data_length; + } + + prf->state = PSA_TLS12_PRF_STATE_LABEL_SET; + + return PSA_SUCCESS; +} + +static psa_status_t psa_tls12_prf_input(psa_tls12_prf_key_derivation_t *prf, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + switch (step) { + case PSA_KEY_DERIVATION_INPUT_SEED: + return psa_tls12_prf_set_seed(prf, data, data_length); + case PSA_KEY_DERIVATION_INPUT_SECRET: + return psa_tls12_prf_set_key(prf, data, data_length); + case PSA_KEY_DERIVATION_INPUT_LABEL: + return psa_tls12_prf_set_label(prf, data, data_length); + default: + return PSA_ERROR_INVALID_ARGUMENT; + } +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +static psa_status_t psa_tls12_prf_psk_to_ms_set_key( + psa_tls12_prf_key_derivation_t *prf, + const uint8_t *data, + size_t data_length) +{ + psa_status_t status; + const size_t pms_len = (prf->state == PSA_TLS12_PRF_STATE_OTHER_KEY_SET ? + 4 + data_length + prf->other_secret_length : + 4 + 2 * data_length); + + if (data_length > PSA_TLS12_PSK_TO_MS_PSK_MAX_SIZE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + uint8_t *pms = mbedtls_calloc(1, pms_len); + if (pms == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + uint8_t *cur = pms; + + /* pure-PSK: + * Quoting RFC 4279, Section 2: + * + * The premaster secret is formed as follows: if the PSK is N octets + * long, concatenate a uint16 with the value N, N zero octets, a second + * uint16 with the value N, and the PSK itself. + * + * mixed-PSK: + * In a DHE-PSK, RSA-PSK, ECDHE-PSK the premaster secret is formed as + * follows: concatenate a uint16 with the length of the other secret, + * the other secret itself, uint16 with the length of PSK, and the + * PSK itself. + * For details please check: + * - RFC 4279, Section 4 for the definition of RSA-PSK, + * - RFC 4279, Section 3 for the definition of DHE-PSK, + * - RFC 5489 for the definition of ECDHE-PSK. + */ + + if (prf->state == PSA_TLS12_PRF_STATE_OTHER_KEY_SET) { + *cur++ = MBEDTLS_BYTE_1(prf->other_secret_length); + *cur++ = MBEDTLS_BYTE_0(prf->other_secret_length); + if (prf->other_secret_length != 0) { + memcpy(cur, prf->other_secret, prf->other_secret_length); + mbedtls_platform_zeroize(prf->other_secret, prf->other_secret_length); + cur += prf->other_secret_length; + } + } else { + *cur++ = MBEDTLS_BYTE_1(data_length); + *cur++ = MBEDTLS_BYTE_0(data_length); + memset(cur, 0, data_length); + cur += data_length; + } + + *cur++ = MBEDTLS_BYTE_1(data_length); + *cur++ = MBEDTLS_BYTE_0(data_length); + memcpy(cur, data, data_length); + cur += data_length; + + status = psa_tls12_prf_set_key(prf, pms, cur - pms); + + mbedtls_zeroize_and_free(pms, pms_len); + return status; +} + +static psa_status_t psa_tls12_prf_psk_to_ms_set_other_key( + psa_tls12_prf_key_derivation_t *prf, + const uint8_t *data, + size_t data_length) +{ + if (prf->state != PSA_TLS12_PRF_STATE_SEED_SET) { + return PSA_ERROR_BAD_STATE; + } + + if (data_length != 0) { + prf->other_secret = mbedtls_calloc(1, data_length); + if (prf->other_secret == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + memcpy(prf->other_secret, data, data_length); + prf->other_secret_length = data_length; + } else { + prf->other_secret_length = 0; + } + + prf->state = PSA_TLS12_PRF_STATE_OTHER_KEY_SET; + + return PSA_SUCCESS; +} + +static psa_status_t psa_tls12_prf_psk_to_ms_input( + psa_tls12_prf_key_derivation_t *prf, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + switch (step) { + case PSA_KEY_DERIVATION_INPUT_SECRET: + return psa_tls12_prf_psk_to_ms_set_key(prf, + data, data_length); + break; + case PSA_KEY_DERIVATION_INPUT_OTHER_SECRET: + return psa_tls12_prf_psk_to_ms_set_other_key(prf, + data, + data_length); + break; + default: + return psa_tls12_prf_input(prf, step, data, data_length); + break; + + } +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) +static psa_status_t psa_tls12_ecjpake_to_pms_input( + psa_tls12_ecjpake_to_pms_t *ecjpake, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + if (data_length != PSA_TLS12_ECJPAKE_TO_PMS_INPUT_SIZE || + step != PSA_KEY_DERIVATION_INPUT_SECRET) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Check if the passed point is in an uncompressed form */ + if (data[0] != 0x04) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Only K.X has to be extracted - bytes 1 to 32 inclusive. */ + memcpy(ecjpake->data, data + 1, PSA_TLS12_ECJPAKE_TO_PMS_DATA_SIZE); + + return PSA_SUCCESS; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ + +#if defined(PSA_HAVE_SOFT_PBKDF2) +static psa_status_t psa_pbkdf2_set_input_cost( + psa_pbkdf2_key_derivation_t *pbkdf2, + psa_key_derivation_step_t step, + uint64_t data) +{ + if (step != PSA_KEY_DERIVATION_INPUT_COST) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (pbkdf2->state != PSA_PBKDF2_STATE_INIT) { + return PSA_ERROR_BAD_STATE; + } + + if (data > PSA_VENDOR_PBKDF2_MAX_ITERATIONS) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (data == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + pbkdf2->input_cost = data; + pbkdf2->state = PSA_PBKDF2_STATE_INPUT_COST_SET; + + return PSA_SUCCESS; +} + +static psa_status_t psa_pbkdf2_set_salt(psa_pbkdf2_key_derivation_t *pbkdf2, + const uint8_t *data, + size_t data_length) +{ + if (pbkdf2->state == PSA_PBKDF2_STATE_INPUT_COST_SET) { + pbkdf2->state = PSA_PBKDF2_STATE_SALT_SET; + } else if (pbkdf2->state == PSA_PBKDF2_STATE_SALT_SET) { + /* Appending to existing salt. No state change. */ + } else { + return PSA_ERROR_BAD_STATE; + } + + if (data_length == 0) { + /* Appending an empty string, nothing to do. */ + } else { + uint8_t *next_salt; + + next_salt = mbedtls_calloc(1, data_length + pbkdf2->salt_length); + if (next_salt == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + if (pbkdf2->salt_length != 0) { + memcpy(next_salt, pbkdf2->salt, pbkdf2->salt_length); + } + memcpy(next_salt + pbkdf2->salt_length, data, data_length); + pbkdf2->salt_length += data_length; + mbedtls_free(pbkdf2->salt); + pbkdf2->salt = next_salt; + } + return PSA_SUCCESS; +} + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) +static psa_status_t psa_pbkdf2_hmac_set_password(psa_algorithm_t hash_alg, + const uint8_t *input, + size_t input_len, + uint8_t *output, + size_t *output_len) +{ + psa_status_t status = PSA_SUCCESS; + if (input_len > PSA_HASH_BLOCK_LENGTH(hash_alg)) { + status = psa_hash_compute(hash_alg, input, input_len, output, + PSA_HMAC_MAX_HASH_BLOCK_SIZE, output_len); + } else { + memcpy(output, input, input_len); + *output_len = PSA_HASH_BLOCK_LENGTH(hash_alg); + } + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) +static psa_status_t psa_pbkdf2_cmac_set_password(const uint8_t *input, + size_t input_len, + uint8_t *output, + size_t *output_len) +{ + psa_status_t status = PSA_SUCCESS; + if (input_len != PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC)) { + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + uint8_t zeros[16] = { 0 }; + psa_set_key_type(&attributes, PSA_KEY_TYPE_AES); + psa_set_key_bits(&attributes, PSA_BYTES_TO_BITS(sizeof(zeros))); + psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_MESSAGE); + /* Passing PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC) as + * mac_size as the driver function sets mac_output_length = mac_size + * on success. See https://github.com/Mbed-TLS/mbedtls/issues/7801 */ + status = psa_driver_wrapper_mac_compute(&attributes, + zeros, sizeof(zeros), + PSA_ALG_CMAC, input, input_len, + output, + PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, + 128U, + PSA_ALG_CMAC), + output_len); + } else { + memcpy(output, input, input_len); + *output_len = PSA_MAC_LENGTH(PSA_KEY_TYPE_AES, 128U, PSA_ALG_CMAC); + } + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 */ + +static psa_status_t psa_pbkdf2_set_password(psa_pbkdf2_key_derivation_t *pbkdf2, + psa_algorithm_t kdf_alg, + const uint8_t *data, + size_t data_length) +{ + psa_status_t status = PSA_SUCCESS; + if (pbkdf2->state != PSA_PBKDF2_STATE_SALT_SET) { + return PSA_ERROR_BAD_STATE; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC) + if (PSA_ALG_IS_PBKDF2_HMAC(kdf_alg)) { + psa_algorithm_t hash_alg = PSA_ALG_PBKDF2_HMAC_GET_HASH(kdf_alg); + status = psa_pbkdf2_hmac_set_password(hash_alg, data, data_length, + pbkdf2->password, + &pbkdf2->password_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_HMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128) + if (kdf_alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) { + status = psa_pbkdf2_cmac_set_password(data, data_length, + pbkdf2->password, + &pbkdf2->password_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_PBKDF2_AES_CMAC_PRF_128 */ + { + return PSA_ERROR_INVALID_ARGUMENT; + } + + pbkdf2->state = PSA_PBKDF2_STATE_PASSWORD_SET; + + return status; +} + +static psa_status_t psa_pbkdf2_input(psa_pbkdf2_key_derivation_t *pbkdf2, + psa_algorithm_t kdf_alg, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + switch (step) { + case PSA_KEY_DERIVATION_INPUT_SALT: + return psa_pbkdf2_set_salt(pbkdf2, data, data_length); + case PSA_KEY_DERIVATION_INPUT_PASSWORD: + return psa_pbkdf2_set_password(pbkdf2, kdf_alg, data, data_length); + default: + return PSA_ERROR_INVALID_ARGUMENT; + } +} +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + +/** Check whether the given key type is acceptable for the given + * input step of a key derivation. + * + * Secret inputs must have the type #PSA_KEY_TYPE_DERIVE. + * Non-secret inputs must have the type #PSA_KEY_TYPE_RAW_DATA. + * Both secret and non-secret inputs can alternatively have the type + * #PSA_KEY_TYPE_NONE, which is never the type of a key object, meaning + * that the input was passed as a buffer rather than via a key object. + */ +static int psa_key_derivation_check_input_type( + psa_key_derivation_step_t step, + psa_key_type_t key_type) +{ + switch (step) { + case PSA_KEY_DERIVATION_INPUT_SECRET: + if (key_type == PSA_KEY_TYPE_DERIVE) { + return PSA_SUCCESS; + } + if (key_type == PSA_KEY_TYPE_NONE) { + return PSA_SUCCESS; + } + break; + case PSA_KEY_DERIVATION_INPUT_OTHER_SECRET: + if (key_type == PSA_KEY_TYPE_DERIVE) { + return PSA_SUCCESS; + } + if (key_type == PSA_KEY_TYPE_NONE) { + return PSA_SUCCESS; + } + break; + case PSA_KEY_DERIVATION_INPUT_LABEL: + case PSA_KEY_DERIVATION_INPUT_SALT: + case PSA_KEY_DERIVATION_INPUT_INFO: + case PSA_KEY_DERIVATION_INPUT_SEED: + if (key_type == PSA_KEY_TYPE_RAW_DATA) { + return PSA_SUCCESS; + } + if (key_type == PSA_KEY_TYPE_NONE) { + return PSA_SUCCESS; + } + break; + case PSA_KEY_DERIVATION_INPUT_PASSWORD: + if (key_type == PSA_KEY_TYPE_PASSWORD) { + return PSA_SUCCESS; + } + if (key_type == PSA_KEY_TYPE_DERIVE) { + return PSA_SUCCESS; + } + if (key_type == PSA_KEY_TYPE_NONE) { + return PSA_SUCCESS; + } + break; + } + return PSA_ERROR_INVALID_ARGUMENT; +} + +static psa_status_t psa_key_derivation_input_internal( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + psa_key_type_t key_type, + const uint8_t *data, + size_t data_length) +{ + psa_status_t status; + psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); + + status = psa_key_derivation_check_input_type(step, key_type); + if (status != PSA_SUCCESS) { + goto exit; + } + +#if defined(BUILTIN_ALG_ANY_HKDF) + if (PSA_ALG_IS_ANY_HKDF(kdf_alg)) { + status = psa_hkdf_input(&operation->ctx.hkdf, kdf_alg, + step, data, data_length); + } else +#endif /* BUILTIN_ALG_ANY_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) + if (PSA_ALG_IS_TLS12_PRF(kdf_alg)) { + status = psa_tls12_prf_input(&operation->ctx.tls12_prf, + step, data, data_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if (PSA_ALG_IS_TLS12_PSK_TO_MS(kdf_alg)) { + status = psa_tls12_prf_psk_to_ms_input(&operation->ctx.tls12_prf, + step, data, data_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS) + if (kdf_alg == PSA_ALG_TLS12_ECJPAKE_TO_PMS) { + status = psa_tls12_ecjpake_to_pms_input( + &operation->ctx.tls12_ecjpake_to_pms, step, data, data_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_ECJPAKE_TO_PMS */ +#if defined(PSA_HAVE_SOFT_PBKDF2) + if (PSA_ALG_IS_PBKDF2(kdf_alg)) { + status = psa_pbkdf2_input(&operation->ctx.pbkdf2, kdf_alg, + step, data, data_length); + } else +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + { + /* This can't happen unless the operation object was not initialized */ + (void) data; + (void) data_length; + (void) kdf_alg; + return PSA_ERROR_BAD_STATE; + } + +exit: + if (status != PSA_SUCCESS) { + psa_key_derivation_abort(operation); + } + return status; +} + +static psa_status_t psa_key_derivation_input_integer_internal( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + uint64_t value) +{ + psa_status_t status; + psa_algorithm_t kdf_alg = psa_key_derivation_get_kdf_alg(operation); + +#if defined(PSA_HAVE_SOFT_PBKDF2) + if (PSA_ALG_IS_PBKDF2(kdf_alg)) { + status = psa_pbkdf2_set_input_cost( + &operation->ctx.pbkdf2, step, value); + } else +#endif /* PSA_HAVE_SOFT_PBKDF2 */ + { + (void) step; + (void) value; + (void) kdf_alg; + status = PSA_ERROR_INVALID_ARGUMENT; + } + + if (status != PSA_SUCCESS) { + psa_key_derivation_abort(operation); + } + return status; +} + +psa_status_t psa_key_derivation_input_bytes( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + const uint8_t *data, + size_t data_length) +{ + return psa_key_derivation_input_internal(operation, step, + PSA_KEY_TYPE_NONE, + data, data_length); +} + +psa_status_t psa_key_derivation_input_integer( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + uint64_t value) +{ + return psa_key_derivation_input_integer_internal(operation, step, value); +} + +psa_status_t psa_key_derivation_input_key( + psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + mbedtls_svc_key_id_t key) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg); + if (status != PSA_SUCCESS) { + psa_key_derivation_abort(operation); + return status; + } + + /* Passing a key object as a SECRET or PASSWORD input unlocks the + * permission to output to a key object. */ + if (step == PSA_KEY_DERIVATION_INPUT_SECRET || + step == PSA_KEY_DERIVATION_INPUT_PASSWORD) { + operation->can_output_key = 1; + } + + status = psa_key_derivation_input_internal(operation, + step, slot->attr.type, + slot->key.data, + slot->key.bytes); + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) + +#include "sli_psa_driver_features.h" + +psa_status_t sli_se_driver_single_shot_hkdf( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* info, + size_t info_length, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint8_t *key_out_buffer, + size_t key_out_buffer_size); + +psa_status_t sli_se_driver_single_shot_pbkdf2( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint32_t iterations, + uint8_t *key_out_buffer, + size_t key_out_buffer_size); + +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) +psa_status_t sli_cryptoacc_driver_single_shot_pbkdf2( + psa_algorithm_t alg, + const psa_key_attributes_t *key_in_attributes, + const uint8_t *key_in_buffer, + size_t key_in_buffer_size, + const uint8_t* salt, + size_t salt_length, + const psa_key_attributes_t *key_out_attributes, + uint32_t iterations, + uint8_t *key_out_buffer, + size_t key_out_buffer_size); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + +psa_status_t sl_psa_key_derivation_single_shot( + psa_algorithm_t alg, + mbedtls_svc_key_id_t key_in, + const uint8_t *info, + size_t info_length, + const uint8_t *salt, + size_t salt_length, + size_t iterations, + const psa_key_attributes_t *key_out_attributes, + mbedtls_svc_key_id_t *key_out ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *input_key_slot = NULL; + psa_key_slot_t *output_key_slot = NULL; + psa_se_drv_table_entry_t *driver = NULL; + *key_out = MBEDTLS_SVC_KEY_ID_INIT; + size_t storage_size = 0; + + /* Reject any attempt to create a zero-length key so that we don't + * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ + if( psa_get_key_bits( key_out_attributes ) == 0 ) + return( PSA_ERROR_INVALID_ARGUMENT ); + + status = psa_get_and_lock_key_slot_with_policy( + key_in, &input_key_slot, PSA_KEY_USAGE_DERIVE, alg ); + if( status != PSA_SUCCESS ) + return( status ); + + status = psa_start_key_creation( PSA_KEY_CREATION_DERIVE, key_out_attributes, + &output_key_slot, &driver ); + if( status != PSA_SUCCESS ) + goto exit; + + status = psa_driver_wrapper_get_key_buffer_size( key_out_attributes, &storage_size ); + if( status != PSA_SUCCESS ) + goto exit; + + /* In the case of a transparent key or an opaque key stored in local + * storage (thus not in the case of generating a key in a secure element + * or cryptoprocessor with storage), we have to allocate a buffer to + * hold the generated key material. */ + if( output_key_slot->key.data == NULL ) + { + status = psa_allocate_buffer_to_slot( output_key_slot, storage_size ); + if( status != PSA_SUCCESS ) + goto exit; + } + + { + psa_key_attributes_t key_in_attributes = { + .core = input_key_slot->attr + }; + + /* Call the appropriate driver. Since this function is used exclusively with + * the SE as an accelerator, we can skip the wrapper layer and call the + * driver functions directly. */ + if (PSA_ALG_IS_HKDF(alg)) +#if defined(SLI_PSA_DRIVER_FEATURE_HKDF) + { + status = sli_se_driver_single_shot_hkdf( + alg, &key_in_attributes, input_key_slot->key.data, + input_key_slot->key.bytes, info, info_length, salt, salt_length, + key_out_attributes, output_key_slot->key.data, + output_key_slot->key.bytes); + } +#else /* SLI_PSA_DRIVER_FEATURE_HKDF */ + { + (void)info; + (void)info_length; + (void)salt; + (void)salt_length; + (void)key_in_attributes; + + status = PSA_ERROR_NOT_SUPPORTED; + } +#endif /* SLI_PSA_DRIVER_FEATURE_HKDF */ + else if ( (PSA_ALG_IS_PBKDF2_HMAC(alg) || (alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128)) ) +#if defined(SLI_PSA_DRIVER_FEATURE_PBKDF2) +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + { + if (alg == PSA_ALG_PBKDF2_AES_CMAC_PRF_128) + { + status = sli_cryptoacc_driver_single_shot_pbkdf2( + alg, &key_in_attributes, input_key_slot->key.data, + input_key_slot->key.bytes, salt, salt_length, + key_out_attributes, iterations, output_key_slot->key.data, + output_key_slot->key.bytes); + } + else + { + (void)salt; + (void)salt_length; + (void)iterations; + (void)key_in_attributes; + + status = PSA_ERROR_NOT_SUPPORTED; + } + } +#else /* SLI_MBEDTLS_DEVICE_VSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ + { + status = sli_se_driver_single_shot_pbkdf2( + alg, &key_in_attributes, input_key_slot->key.data, + input_key_slot->key.bytes, salt, salt_length, + key_out_attributes, iterations, output_key_slot->key.data, + output_key_slot->key.bytes); + } +#endif /* SLI_MBEDTLS_DEVICE_VSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#else /* SLI_PSA_DRIVER_FEATURE_PBKDF2 */ + { + (void)salt; + (void)salt_length; + (void)iterations; + (void)key_in_attributes; + + status = PSA_ERROR_NOT_SUPPORTED; + } +#endif /* SLI_PSA_DRIVER_FEATURE_PBKDF2 */ + else + { + status = PSA_ERROR_NOT_SUPPORTED; + } + } + +exit: + + /* Finish (or fail) key creation. */ + if( status == PSA_SUCCESS ) + status = psa_finish_key_creation( output_key_slot, driver, key_out ); + if( status != PSA_SUCCESS ) + psa_fail_key_creation( output_key_slot, driver ); + + /* Release input key slot. */ + unlock_status = psa_unlock_key_slot( input_key_slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); +} + + + +/****************************************************************/ +/* Key agreement */ +/****************************************************************/ + +psa_status_t psa_key_agreement_raw_builtin(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length) +{ + switch (alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) + case PSA_ALG_ECDH: + return mbedtls_psa_key_agreement_ecdh(attributes, key_buffer, + key_buffer_size, alg, + peer_key, peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) + case PSA_ALG_FFDH: + return mbedtls_psa_ffdh_key_agreement(attributes, + peer_key, + peer_key_length, + key_buffer, + key_buffer_size, + shared_secret, + shared_secret_size, + shared_secret_length); +#endif /* MBEDTLS_PSA_BUILTIN_ALG_FFDH */ + + default: + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) peer_key; + (void) peer_key_length; + (void) shared_secret; + (void) shared_secret_size; + (void) shared_secret_length; + return PSA_ERROR_NOT_SUPPORTED; + } +} + +/** Internal function for raw key agreement + * Calls the driver wrapper which will hand off key agreement task + * to the driver's implementation if a driver is present. + * Fallback specified in the driver wrapper is built-in raw key agreement + * (psa_key_agreement_raw_builtin). + */ +static psa_status_t psa_key_agreement_raw_internal(psa_algorithm_t alg, + psa_key_slot_t *private_key, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length) +{ + if (!PSA_ALG_IS_RAW_KEY_AGREEMENT(alg)) { + return PSA_ERROR_NOT_SUPPORTED; + } + + psa_key_attributes_t attributes = { + .core = private_key->attr + }; + + return psa_driver_wrapper_key_agreement(&attributes, + private_key->key.data, + private_key->key.bytes, alg, + peer_key, peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length); +} + +/* Note that if this function fails, you must call psa_key_derivation_abort() + * to potentially free embedded data structures and wipe confidential data. + */ +static psa_status_t psa_key_agreement_internal(psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + psa_key_slot_t *private_key, + const uint8_t *peer_key, + size_t peer_key_length) +{ + psa_status_t status; + uint8_t shared_secret[PSA_RAW_KEY_AGREEMENT_OUTPUT_MAX_SIZE]; + size_t shared_secret_length = 0; + psa_algorithm_t ka_alg = PSA_ALG_KEY_AGREEMENT_GET_BASE(operation->alg); + + /* Step 1: run the secret agreement algorithm to generate the shared + * secret. */ + status = psa_key_agreement_raw_internal(ka_alg, + private_key, + peer_key, peer_key_length, + shared_secret, + sizeof(shared_secret), + &shared_secret_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Step 2: set up the key derivation to generate key material from + * the shared secret. A shared secret is permitted wherever a key + * of type DERIVE is permitted. */ + status = psa_key_derivation_input_internal(operation, step, + PSA_KEY_TYPE_DERIVE, + shared_secret, + shared_secret_length); +exit: + mbedtls_platform_zeroize(shared_secret, shared_secret_length); + return status; +} + +psa_status_t psa_key_derivation_key_agreement(psa_key_derivation_operation_t *operation, + psa_key_derivation_step_t step, + mbedtls_svc_key_id_t private_key, + const uint8_t *peer_key, + size_t peer_key_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; + + if (!PSA_ALG_IS_KEY_AGREEMENT(operation->alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + status = psa_get_and_lock_key_slot_with_policy( + private_key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg); + if (status != PSA_SUCCESS) { + return status; + } + status = psa_key_agreement_internal(operation, step, + slot, + peer_key, peer_key_length); + if (status != PSA_SUCCESS) { + psa_key_derivation_abort(operation); + } else { + /* If a private key has been added as SECRET, we allow the derived + * key material to be used as a key in PSA Crypto. */ + if (step == PSA_KEY_DERIVATION_INPUT_SECRET) { + operation->can_output_key = 1; + } + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, + mbedtls_svc_key_id_t private_key, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + size_t expected_length; + + if (!PSA_ALG_IS_KEY_AGREEMENT(alg)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + status = psa_get_and_lock_key_slot_with_policy( + private_key, &slot, PSA_KEY_USAGE_DERIVE, alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() is in general an upper bound + * for the output size. The PSA specification only guarantees that this + * function works if output_size >= PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(...), + * but it might be nice to allow smaller buffers if the output fits. + * At the time of writing this comment, with only ECDH implemented, + * PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() is exact so the point is moot. + * If FFDH is implemented, PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE() can easily + * be exact for it as well. */ + expected_length = + PSA_RAW_KEY_AGREEMENT_OUTPUT_SIZE(slot->attr.type, slot->attr.bits); + if (output_size < expected_length) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + status = psa_key_agreement_raw_internal(alg, slot, + peer_key, peer_key_length, + output, output_size, + output_length); + +exit: + if (status != PSA_SUCCESS) { + /* If an error happens and is not handled properly, the output + * may be used as a key to protect sensitive data. Arrange for such + * a key to be random, which is likely to result in decryption or + * verification errors. This is better than filling the buffer with + * some constant data such as zeros, which would result in the data + * being protected with a reproducible, easily knowable key. + */ + psa_generate_random(output, output_size); + *output_length = output_size; + } + + unlock_status = psa_unlock_key_slot(slot); + + return (status == PSA_SUCCESS) ? unlock_status : status; +} + + + +/****************************************************************/ +/* Random generation */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) +#include "entropy_poll.h" +#endif + +/** Initialize the PSA random generator. + */ +static void mbedtls_psa_random_init(mbedtls_psa_random_context_t *rng) +{ +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + memset(rng, 0, sizeof(*rng)); +#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + + /* Set default configuration if + * mbedtls_psa_crypto_configure_entropy_sources() hasn't been called. */ + if (rng->entropy_init == NULL) { + rng->entropy_init = mbedtls_entropy_init; + } + if (rng->entropy_free == NULL) { + rng->entropy_free = mbedtls_entropy_free; + } + + rng->entropy_init(&rng->entropy); +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) && \ + defined(MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES) + /* The PSA entropy injection feature depends on using NV seed as an entropy + * source. Add NV seed as an entropy source for PSA entropy injection. */ + mbedtls_entropy_add_source(&rng->entropy, + mbedtls_nv_seed_poll, NULL, + MBEDTLS_ENTROPY_BLOCK_SIZE, + MBEDTLS_ENTROPY_SOURCE_STRONG); +#endif + + mbedtls_psa_drbg_init(MBEDTLS_PSA_RANDOM_STATE); +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +} + +/** Deinitialize the PSA random generator. + */ +static void mbedtls_psa_random_free(mbedtls_psa_random_context_t *rng) +{ +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + memset(rng, 0, sizeof(*rng)); +#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + mbedtls_psa_drbg_free(MBEDTLS_PSA_RANDOM_STATE); + rng->entropy_free(&rng->entropy); +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +} + +/** Seed the PSA random generator. + */ +static psa_status_t mbedtls_psa_random_seed(mbedtls_psa_random_context_t *rng) +{ +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + /* Do nothing: the external RNG seeds itself. */ + (void) rng; + return PSA_SUCCESS; +#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + const unsigned char drbg_seed[] = "PSA"; + int ret = mbedtls_psa_drbg_seed(&rng->entropy, + drbg_seed, sizeof(drbg_seed) - 1); + return mbedtls_to_psa_error(ret); +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +} + +psa_status_t psa_generate_random(uint8_t *output, + size_t output_size) +{ + GUARD_MODULE_INITIALIZED; + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + + size_t output_length = 0; + psa_status_t status = mbedtls_psa_external_get_random(&global_data.rng, + output, output_size, + &output_length); + if (status != PSA_SUCCESS) { + return status; + } + /* Breaking up a request into smaller chunks is currently not supported + * for the external RNG interface. */ + if (output_length != output_size) { + return PSA_ERROR_INSUFFICIENT_ENTROPY; + } + return PSA_SUCCESS; + +#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + + while (output_size > 0) { + size_t request_size = + (output_size > MBEDTLS_PSA_RANDOM_MAX_REQUEST ? + MBEDTLS_PSA_RANDOM_MAX_REQUEST : + output_size); + int ret = mbedtls_psa_get_random(MBEDTLS_PSA_RANDOM_STATE, + output, request_size); + if (ret != 0) { + return mbedtls_to_psa_error(ret); + } + output_size -= request_size; + output += request_size; + } + return PSA_SUCCESS; +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ +} + +/* Wrapper function allowing the classic API to use the PSA RNG. + * + * `mbedtls_psa_get_random(MBEDTLS_PSA_RANDOM_STATE, ...)` calls + * `psa_generate_random(...)`. The state parameter is ignored since the + * PSA API doesn't support passing an explicit state. + * + * In the non-external case, psa_generate_random() calls an + * `mbedtls_xxx_drbg_random` function which has exactly the same signature + * and semantics as mbedtls_psa_get_random(). As an optimization, + * instead of doing this back-and-forth between the PSA API and the + * classic API, psa_crypto_random_impl.h defines `mbedtls_psa_get_random` + * as a constant function pointer to `mbedtls_xxx_drbg_random`. + */ +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +int mbedtls_psa_get_random(void *p_rng, + unsigned char *output, + size_t output_size) +{ + /* This function takes a pointer to the RNG state because that's what + * classic mbedtls functions using an RNG expect. The PSA RNG manages + * its own state internally and doesn't let the caller access that state. + * So we just ignore the state parameter, and in practice we'll pass + * NULL. */ + (void) p_rng; + psa_status_t status = psa_generate_random(output, output_size); + if (status == PSA_SUCCESS) { + return 0; + } else { + return MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; + } +} +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) +psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, + size_t seed_size) +{ + if (global_data.initialized) { + return PSA_ERROR_NOT_PERMITTED; + } + + if (((seed_size < MBEDTLS_ENTROPY_MIN_PLATFORM) || + (seed_size < MBEDTLS_ENTROPY_BLOCK_SIZE)) || + (seed_size > MBEDTLS_ENTROPY_MAX_SEED_SIZE)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return mbedtls_psa_storage_inject_entropy(seed, seed_size); +} +#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ + +/** Validate the key type and size for key generation + * + * \param type The key type + * \param bits The number of bits of the key + * + * \retval #PSA_SUCCESS + * The key type and size are valid. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size in bits of the key is not valid. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The type and/or the size in bits of the key or the combination of + * the two is not supported. + */ +static psa_status_t psa_validate_key_type_and_size_for_key_generation( + psa_key_type_t type, size_t bits) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (key_type_is_raw_bytes(type)) { + status = psa_validate_unstructured_key_bit_size(type, bits); + if (status != PSA_SUCCESS) { + return status; + } + } else +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) + if (PSA_KEY_TYPE_IS_RSA(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + if (bits > PSA_VENDOR_RSA_MAX_KEY_BITS) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (bits < PSA_VENDOR_RSA_GENERATE_MIN_KEY_BITS) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* Accept only byte-aligned keys, for the same reasons as + * in psa_import_rsa_key(). */ + if (bits % 8 != 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + } else +#endif /* defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) + if (PSA_KEY_TYPE_IS_ECC(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + /* To avoid empty block, return successfully here. */ + return PSA_SUCCESS; + } else +#endif /* defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE) */ + +#if defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) + if (PSA_KEY_TYPE_IS_DH(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + if (psa_is_dh_key_size_valid(bits) == 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + } else +#endif /* defined(PSA_WANT_KEY_TYPE_DH_KEY_PAIR_GENERATE) */ + { + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +psa_status_t psa_generate_key_internal( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_type_t type = attributes->core.type; + + if ((attributes->domain_parameters == NULL) && + (attributes->domain_parameters_size != 0)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (key_type_is_raw_bytes(type)) { + status = psa_generate_random(key_buffer, key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) + if (type == PSA_KEY_TYPE_DES) { + psa_des_set_key_parity(key_buffer, key_buffer_size); + } +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES */ + } else + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) + if (type == PSA_KEY_TYPE_RSA_KEY_PAIR) { + return mbedtls_psa_rsa_generate_key(attributes, + key_buffer, + key_buffer_size, + key_buffer_length); + } else +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) + if (PSA_KEY_TYPE_IS_ECC(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + return mbedtls_psa_ecp_generate_key(attributes, + key_buffer, + key_buffer_size, + key_buffer_length); + } else +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) + if (PSA_KEY_TYPE_IS_DH(type) && PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + return mbedtls_psa_ffdh_generate_key(attributes, + key_buffer, + key_buffer_size, + key_buffer_length); + } else +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) */ + { + (void) key_buffer_length; + return PSA_ERROR_NOT_SUPPORTED; + } + + return PSA_SUCCESS; +} + +psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t *key) +{ + psa_status_t status; + psa_key_slot_t *slot = NULL; + psa_se_drv_table_entry_t *driver = NULL; + size_t key_buffer_size; + + *key = MBEDTLS_SVC_KEY_ID_INIT; + + /* Reject any attempt to create a zero-length key so that we don't + * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ + if (psa_get_key_bits(attributes) == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + /* Reject any attempt to create a public key. */ + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(attributes->core.type)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_start_key_creation(PSA_KEY_CREATION_GENERATE, attributes, + &slot, &driver); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* In the case of a transparent key or an opaque key stored in local + * storage ( thus not in the case of generating a key in a secure element + * with storage ( MBEDTLS_PSA_CRYPTO_SE_C ) ),we have to allocate a + * buffer to hold the generated key material. */ + if (slot->key.data == NULL) { + if (PSA_KEY_LIFETIME_GET_LOCATION(attributes->core.lifetime) == + PSA_KEY_LOCATION_LOCAL_STORAGE) { + status = psa_validate_key_type_and_size_for_key_generation( + attributes->core.type, attributes->core.bits); + if (status != PSA_SUCCESS) { + goto exit; + } + + key_buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( + attributes->core.type, + attributes->core.bits); + } else { + status = psa_driver_wrapper_get_key_buffer_size( + attributes, &key_buffer_size); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = psa_allocate_buffer_to_slot(slot, key_buffer_size); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = psa_driver_wrapper_generate_key(attributes, + slot->key.data, slot->key.bytes, &slot->key.bytes); + + if (status != PSA_SUCCESS) { + psa_remove_key_data_from_memory(slot); + } + +exit: + if (status == PSA_SUCCESS) { + status = psa_finish_key_creation(slot, driver, key); + } + if (status != PSA_SUCCESS) { + psa_fail_key_creation(slot, driver); + } + + return status; +} + +/****************************************************************/ +/* Module setup */ +/****************************************************************/ + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +psa_status_t mbedtls_psa_crypto_configure_entropy_sources( + void (* entropy_init)(mbedtls_entropy_context *ctx), + void (* entropy_free)(mbedtls_entropy_context *ctx)) +{ + if (global_data.rng_state != RNG_NOT_INITIALIZED) { + return PSA_ERROR_BAD_STATE; + } + global_data.rng.entropy_init = entropy_init; + global_data.rng.entropy_free = entropy_free; + return PSA_SUCCESS; +} +#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ + +void mbedtls_psa_crypto_free(void) +{ + psa_wipe_all_key_slots(); + if (global_data.rng_state != RNG_NOT_INITIALIZED) { + mbedtls_psa_random_free(&global_data.rng); + } + /* Wipe all remaining data, including configuration. + * In particular, this sets all state indicator to the value + * indicating "uninitialized". */ + mbedtls_platform_zeroize(&global_data, sizeof(global_data)); + + /* Terminate drivers */ + psa_driver_wrapper_free(); +} + +#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) +/** Recover a transaction that was interrupted by a power failure. + * + * This function is called during initialization, before psa_crypto_init() + * returns. If this function returns a failure status, the initialization + * fails. + */ +static psa_status_t psa_crypto_recover_transaction( + const psa_crypto_transaction_t *transaction) +{ + switch (transaction->unknown.type) { + case PSA_CRYPTO_TRANSACTION_CREATE_KEY: + case PSA_CRYPTO_TRANSACTION_DESTROY_KEY: + /* TODO - fall through to the failure case until this + * is implemented. + * https://github.com/ARMmbed/mbed-crypto/issues/218 + */ + default: + /* We found an unsupported transaction in the storage. + * We don't know what state the storage is in. Give up. */ + return PSA_ERROR_DATA_INVALID; + } +} +#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ + +psa_status_t psa_crypto_init(void) +{ + psa_status_t status; + + /* Double initialization is explicitly allowed. */ + if (global_data.initialized != 0) { + return PSA_SUCCESS; + } + + /* Init drivers */ + status = psa_driver_wrapper_init(); + if (status != PSA_SUCCESS) { + goto exit; + } + global_data.drivers_initialized = 1; + + /* Initialize and seed the random generator. */ + mbedtls_psa_random_init(&global_data.rng); + global_data.rng_state = RNG_INITIALIZED; + status = mbedtls_psa_random_seed(&global_data.rng); + if (status != PSA_SUCCESS) { + goto exit; + } + global_data.rng_state = RNG_SEEDED; + + status = psa_initialize_key_slots(); + if (status != PSA_SUCCESS) { + goto exit; + } + +#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) + status = psa_crypto_load_transaction(); + if (status == PSA_SUCCESS) { + status = psa_crypto_recover_transaction(&psa_crypto_transaction); + if (status != PSA_SUCCESS) { + goto exit; + } + status = psa_crypto_stop_transaction(); + } else if (status == PSA_ERROR_DOES_NOT_EXIST) { + /* There's no transaction to complete. It's all good. */ + status = PSA_SUCCESS; + } +#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ + + /* All done. */ + global_data.initialized = 1; + +exit: + if (status != PSA_SUCCESS) { + mbedtls_psa_crypto_free(); + } + return status; +} + +#if defined(PSA_WANT_ALG_SOME_PAKE) +psa_status_t psa_crypto_driver_pake_get_password_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *password_len) +{ + if (inputs->password_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + *password_len = inputs->password_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_password( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *buffer, size_t buffer_size, size_t *buffer_length) +{ + if (inputs->password_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (buffer_size < inputs->password_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(buffer, inputs->password, inputs->password_len); + *buffer_length = inputs->password_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_user_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *user_len) +{ + if (inputs->user_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + *user_len = inputs->user_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_user( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *user_id, size_t user_id_size, size_t *user_id_len) +{ + if (inputs->user_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (user_id_size < inputs->user_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(user_id, inputs->user, inputs->user_len); + *user_id_len = inputs->user_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_peer_len( + const psa_crypto_driver_pake_inputs_t *inputs, + size_t *peer_len) +{ + if (inputs->peer_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + *peer_len = inputs->peer_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_peer( + const psa_crypto_driver_pake_inputs_t *inputs, + uint8_t *peer_id, size_t peer_id_size, size_t *peer_id_length) +{ + if (inputs->peer_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (peer_id_size < inputs->peer_len) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(peer_id, inputs->peer, inputs->peer_len); + *peer_id_length = inputs->peer_len; + + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_driver_pake_get_cipher_suite( + const psa_crypto_driver_pake_inputs_t *inputs, + psa_pake_cipher_suite_t *cipher_suite) +{ + if (inputs->cipher_suite.algorithm == PSA_ALG_NONE) { + return PSA_ERROR_BAD_STATE; + } + + *cipher_suite = inputs->cipher_suite; + + return PSA_SUCCESS; +} + +psa_status_t psa_pake_setup( + psa_pake_operation_t *operation, + const psa_pake_cipher_suite_t *cipher_suite) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_SETUP) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (PSA_ALG_IS_PAKE(cipher_suite->algorithm) == 0 || + PSA_ALG_IS_HASH(cipher_suite->hash) == 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + memset(&operation->data.inputs, 0, sizeof(operation->data.inputs)); + + operation->alg = cipher_suite->algorithm; + operation->primitive = PSA_PAKE_PRIMITIVE(cipher_suite->type, + cipher_suite->family, cipher_suite->bits); + operation->data.inputs.cipher_suite = *cipher_suite; + +#if defined(PSA_WANT_ALG_JPAKE) + if (operation->alg == PSA_ALG_JPAKE) { + psa_jpake_computation_stage_t *computation_stage = + &operation->computation_stage.jpake; + + memset(computation_stage, 0, sizeof(*computation_stage)); + computation_stage->step = PSA_PAKE_STEP_KEY_SHARE; + } else +#endif /* PSA_WANT_ALG_JPAKE */ + { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + operation->stage = PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS; + + return PSA_SUCCESS; +exit: + psa_pake_abort(operation); + return status; +} + +psa_status_t psa_pake_set_password_key( + psa_pake_operation_t *operation, + mbedtls_svc_key_id_t password) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; + psa_key_attributes_t attributes; + psa_key_type_t type; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + status = psa_get_and_lock_key_slot_with_policy(password, &slot, + PSA_KEY_USAGE_DERIVE, + operation->alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + attributes = (psa_key_attributes_t) { + .core = slot->attr + }; + + type = psa_get_key_type(&attributes); + + if (type != PSA_KEY_TYPE_PASSWORD && + type != PSA_KEY_TYPE_PASSWORD_HASH) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + operation->data.inputs.password = mbedtls_calloc(1, slot->key.bytes); + if (operation->data.inputs.password == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + + memcpy(operation->data.inputs.password, slot->key.data, slot->key.bytes); + operation->data.inputs.password_len = slot->key.bytes; + operation->data.inputs.attributes = attributes; +exit: + if (status != PSA_SUCCESS) { + psa_pake_abort(operation); + } + unlock_status = psa_unlock_key_slot(slot); + return (status == PSA_SUCCESS) ? unlock_status : status; +} + +psa_status_t psa_pake_set_user( + psa_pake_operation_t *operation, + const uint8_t *user_id, + size_t user_id_len) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (user_id_len == 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (operation->data.inputs.user_len != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + operation->data.inputs.user = mbedtls_calloc(1, user_id_len); + if (operation->data.inputs.user == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + + memcpy(operation->data.inputs.user, user_id, user_id_len); + operation->data.inputs.user_len = user_id_len; + + return PSA_SUCCESS; +exit: + psa_pake_abort(operation); + return status; +} + +psa_status_t psa_pake_set_peer( + psa_pake_operation_t *operation, + const uint8_t *peer_id, + size_t peer_id_len) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (peer_id_len == 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (operation->data.inputs.peer_len != 0) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + operation->data.inputs.peer = mbedtls_calloc(1, peer_id_len); + if (operation->data.inputs.peer == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto exit; + } + + memcpy(operation->data.inputs.peer, peer_id, peer_id_len); + operation->data.inputs.peer_len = peer_id_len; + + return PSA_SUCCESS; +exit: + psa_pake_abort(operation); + return status; +} + +psa_status_t psa_pake_set_role( + psa_pake_operation_t *operation, + psa_pake_role_t role) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_JPAKE) + case PSA_ALG_JPAKE: + if (role == PSA_PAKE_ROLE_NONE) { + return PSA_SUCCESS; + } + status = PSA_ERROR_INVALID_ARGUMENT; + break; +#endif + default: + (void) role; + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } +exit: + psa_pake_abort(operation); + return status; +} + +/* Auxiliary function to convert core computation stage to single driver step. */ +#if defined(PSA_WANT_ALG_JPAKE) +static psa_crypto_driver_pake_step_t convert_jpake_computation_stage_to_driver_step( + psa_jpake_computation_stage_t *stage) +{ + psa_crypto_driver_pake_step_t key_share_step; + if (stage->round == PSA_JPAKE_FIRST) { + int is_x1; + + if (stage->io_mode == PSA_JPAKE_OUTPUT) { + is_x1 = (stage->outputs < 1); + } else { + is_x1 = (stage->inputs < 1); + } + + key_share_step = is_x1 ? + PSA_JPAKE_X1_STEP_KEY_SHARE : + PSA_JPAKE_X2_STEP_KEY_SHARE; + } else if (stage->round == PSA_JPAKE_SECOND) { + key_share_step = (stage->io_mode == PSA_JPAKE_OUTPUT) ? + PSA_JPAKE_X2S_STEP_KEY_SHARE : + PSA_JPAKE_X4S_STEP_KEY_SHARE; + } else { + return PSA_JPAKE_STEP_INVALID; + } + return (psa_crypto_driver_pake_step_t) (key_share_step + stage->step - PSA_PAKE_STEP_KEY_SHARE); +} +#endif /* PSA_WANT_ALG_JPAKE */ + +static psa_status_t psa_pake_complete_inputs( + psa_pake_operation_t *operation) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + /* Create copy of the inputs on stack as inputs share memory + with the driver context which will be setup by the driver. */ + psa_crypto_driver_pake_inputs_t inputs = operation->data.inputs; + + if (inputs.password_len == 0) { + return PSA_ERROR_BAD_STATE; + } + + if (operation->alg == PSA_ALG_JPAKE) { + if (inputs.user_len == 0 || inputs.peer_len == 0) { + return PSA_ERROR_BAD_STATE; + } + } + + /* Clear driver context */ + mbedtls_platform_zeroize(&operation->data, sizeof(operation->data)); + + status = psa_driver_wrapper_pake_setup(operation, &inputs); + + /* Driver is responsible for creating its own copy of the password. */ + mbedtls_zeroize_and_free(inputs.password, inputs.password_len); + + /* User and peer are translated to role. */ + mbedtls_free(inputs.user); + mbedtls_free(inputs.peer); + + if (status == PSA_SUCCESS) { +#if defined(PSA_WANT_ALG_JPAKE) + if (operation->alg == PSA_ALG_JPAKE) { + operation->stage = PSA_PAKE_OPERATION_STAGE_COMPUTATION; + } else +#endif /* PSA_WANT_ALG_JPAKE */ + { + status = PSA_ERROR_NOT_SUPPORTED; + } + } + return status; +} + +#if defined(PSA_WANT_ALG_JPAKE) +static psa_status_t psa_jpake_prologue( + psa_pake_operation_t *operation, + psa_pake_step_t step, + psa_jpake_io_mode_t io_mode) +{ + if (step != PSA_PAKE_STEP_KEY_SHARE && + step != PSA_PAKE_STEP_ZK_PUBLIC && + step != PSA_PAKE_STEP_ZK_PROOF) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + psa_jpake_computation_stage_t *computation_stage = + &operation->computation_stage.jpake; + + if (computation_stage->round != PSA_JPAKE_FIRST && + computation_stage->round != PSA_JPAKE_SECOND) { + return PSA_ERROR_BAD_STATE; + } + + /* Check that the step we are given is the one we were expecting */ + if (step != computation_stage->step) { + return PSA_ERROR_BAD_STATE; + } + + if (step == PSA_PAKE_STEP_KEY_SHARE && + computation_stage->inputs == 0 && + computation_stage->outputs == 0) { + /* Start of the round, so function decides whether we are inputting + * or outputting */ + computation_stage->io_mode = io_mode; + } else if (computation_stage->io_mode != io_mode) { + /* Middle of the round so the mode we are in must match the function + * called by the user */ + return PSA_ERROR_BAD_STATE; + } + + return PSA_SUCCESS; +} + +static psa_status_t psa_jpake_epilogue( + psa_pake_operation_t *operation, + psa_jpake_io_mode_t io_mode) +{ + psa_jpake_computation_stage_t *stage = + &operation->computation_stage.jpake; + + if (stage->step == PSA_PAKE_STEP_ZK_PROOF) { + /* End of an input/output */ + if (io_mode == PSA_JPAKE_INPUT) { + stage->inputs++; + if (stage->inputs == PSA_JPAKE_EXPECTED_INPUTS(stage->round)) { + stage->io_mode = PSA_JPAKE_OUTPUT; + } + } + if (io_mode == PSA_JPAKE_OUTPUT) { + stage->outputs++; + if (stage->outputs == PSA_JPAKE_EXPECTED_OUTPUTS(stage->round)) { + stage->io_mode = PSA_JPAKE_INPUT; + } + } + if (stage->inputs == PSA_JPAKE_EXPECTED_INPUTS(stage->round) && + stage->outputs == PSA_JPAKE_EXPECTED_OUTPUTS(stage->round)) { + /* End of a round, move to the next round */ + stage->inputs = 0; + stage->outputs = 0; + stage->round++; + } + stage->step = PSA_PAKE_STEP_KEY_SHARE; + } else { + stage->step++; + } + return PSA_SUCCESS; +} + +#endif /* PSA_WANT_ALG_JPAKE */ + +psa_status_t psa_pake_output( + psa_pake_operation_t *operation, + psa_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_crypto_driver_pake_step_t driver_step = PSA_JPAKE_STEP_INVALID; + *output_length = 0; + + if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = psa_pake_complete_inputs(operation); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (output_size == 0) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_JPAKE) + case PSA_ALG_JPAKE: + status = psa_jpake_prologue(operation, step, PSA_JPAKE_OUTPUT); + if (status != PSA_SUCCESS) { + goto exit; + } + driver_step = convert_jpake_computation_stage_to_driver_step( + &operation->computation_stage.jpake); + break; +#endif /* PSA_WANT_ALG_JPAKE */ + default: + (void) step; + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + status = psa_driver_wrapper_pake_output(operation, driver_step, + output, output_size, output_length); + + if (status != PSA_SUCCESS) { + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_JPAKE) + case PSA_ALG_JPAKE: + status = psa_jpake_epilogue(operation, PSA_JPAKE_OUTPUT); + if (status != PSA_SUCCESS) { + goto exit; + } + break; +#endif /* PSA_WANT_ALG_JPAKE */ + default: + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + return PSA_SUCCESS; +exit: + psa_pake_abort(operation); + return status; +} + +psa_status_t psa_pake_input( + psa_pake_operation_t *operation, + psa_pake_step_t step, + const uint8_t *input, + size_t input_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_crypto_driver_pake_step_t driver_step = PSA_JPAKE_STEP_INVALID; + const size_t max_input_length = (size_t) PSA_PAKE_INPUT_SIZE(operation->alg, + operation->primitive, + step); + + if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + status = psa_pake_complete_inputs(operation); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (input_length == 0 || input_length > max_input_length) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_JPAKE) + case PSA_ALG_JPAKE: + status = psa_jpake_prologue(operation, step, PSA_JPAKE_INPUT); + if (status != PSA_SUCCESS) { + goto exit; + } + driver_step = convert_jpake_computation_stage_to_driver_step( + &operation->computation_stage.jpake); + break; +#endif /* PSA_WANT_ALG_JPAKE */ + default: + (void) step; + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + status = psa_driver_wrapper_pake_input(operation, driver_step, + input, input_length); + + if (status != PSA_SUCCESS) { + goto exit; + } + + switch (operation->alg) { +#if defined(PSA_WANT_ALG_JPAKE) + case PSA_ALG_JPAKE: + status = psa_jpake_epilogue(operation, PSA_JPAKE_INPUT); + if (status != PSA_SUCCESS) { + goto exit; + } + break; +#endif /* PSA_WANT_ALG_JPAKE */ + default: + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + return PSA_SUCCESS; +exit: + psa_pake_abort(operation); + return status; +} + +psa_status_t psa_pake_get_implicit_key( + psa_pake_operation_t *operation, + psa_key_derivation_operation_t *output) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t shared_key[MBEDTLS_PSA_JPAKE_BUFFER_SIZE]; + size_t shared_key_len = 0; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + +#if defined(PSA_WANT_ALG_JPAKE) + if (operation->alg == PSA_ALG_JPAKE) { + psa_jpake_computation_stage_t *computation_stage = + &operation->computation_stage.jpake; + if (computation_stage->round != PSA_JPAKE_FINISHED) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + } else +#endif /* PSA_WANT_ALG_JPAKE */ + { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + status = psa_driver_wrapper_pake_get_implicit_key(operation, + shared_key, + sizeof(shared_key), + &shared_key_len); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_key_derivation_input_bytes(output, + PSA_KEY_DERIVATION_INPUT_SECRET, + shared_key, + shared_key_len); + + mbedtls_platform_zeroize(shared_key, sizeof(shared_key)); +exit: + abort_status = psa_pake_abort(operation); + return status == PSA_SUCCESS ? abort_status : status; +} + +#if defined(SLI_MBEDTLS_PSA_EC_JPAKE_TLS_WORKAROUND) + +psa_status_t psa_pake_derive_secret( + psa_pake_operation_t *operation, + uint8_t *key_buf, + size_t key_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; + size_t key_output_length = 0; + int ret = 0; + + if (operation->stage != PSA_PAKE_OPERATION_STAGE_COMPUTATION) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + + if (operation->alg == PSA_ALG_JPAKE) { + psa_jpake_computation_stage_t *computation_stage = + &operation->computation_stage.jpake; + if (computation_stage->round != PSA_JPAKE_FINISHED) { + status = PSA_ERROR_BAD_STATE; + goto exit; + } + } else { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + ret = mbedtls_ecjpake_derive_secret( + &(&operation->data.ctx.mbedtls_ctx)->ctx.jpake, + key_buf, + key_length, + &key_output_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + + if (key_output_length != key_length || + ret != 0) { + status = PSA_ERROR_HARDWARE_FAILURE; + goto exit; + } + + status = PSA_SUCCESS; + +exit: + abort_status = psa_pake_abort(operation); + return status == PSA_SUCCESS ? abort_status : status; +} + +#endif // SLI_MBEDTLS_PSA_EC_JPAKE_TLS_WORKAROUND + +psa_status_t psa_pake_abort( + psa_pake_operation_t *operation) +{ + psa_status_t status = PSA_SUCCESS; + + if (operation->stage == PSA_PAKE_OPERATION_STAGE_COMPUTATION) { + status = psa_driver_wrapper_pake_abort(operation); + } + + if (operation->stage == PSA_PAKE_OPERATION_STAGE_COLLECT_INPUTS) { + if (operation->data.inputs.password != NULL) { + mbedtls_zeroize_and_free(operation->data.inputs.password, + operation->data.inputs.password_len); + } + if (operation->data.inputs.user != NULL) { + mbedtls_free(operation->data.inputs.user); + } + if (operation->data.inputs.peer != NULL) { + mbedtls_free(operation->data.inputs.peer); + } + } + memset(operation, 0, sizeof(psa_pake_operation_t)); + + return status; +} +#endif /* PSA_WANT_ALG_SOME_PAKE */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.c index 3902911..60ffd0d 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.c @@ -1,667 +1,667 @@ -/* - * PSA AEAD entry points - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include "psa_crypto_aead.h" -#include "psa_crypto_core.h" -#include "psa_crypto_cipher.h" - -#include -#include "mbedtls/platform.h" - -#include "mbedtls/ccm.h" -#include "mbedtls/chachapoly.h" -#include "mbedtls/cipher.h" -#include "mbedtls/gcm.h" -#include "mbedtls/error.h" - -static psa_status_t psa_aead_setup( - mbedtls_psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t key_bits; - const mbedtls_cipher_info_t *cipher_info; - mbedtls_cipher_id_t cipher_id; - - (void) key_buffer_size; - - key_bits = attributes->core.bits; - - cipher_info = mbedtls_cipher_info_from_psa(alg, - attributes->core.type, key_bits, - &cipher_id); - if (cipher_info == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - operation->alg = PSA_ALG_CCM; - /* CCM allows the following tag lengths: 4, 6, 8, 10, 12, 14, 16. - * The call to mbedtls_ccm_encrypt_and_tag or - * mbedtls_ccm_auth_decrypt will validate the tag length. */ - if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(attributes->core.type) != 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - mbedtls_ccm_init(&operation->ctx.ccm); - status = mbedtls_to_psa_error( - mbedtls_ccm_setkey(&operation->ctx.ccm, cipher_id, - key_buffer, (unsigned int) key_bits)); - if (status != PSA_SUCCESS) { - return status; - } - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - operation->alg = PSA_ALG_GCM; - /* GCM allows the following tag lengths: 4, 8, 12, 13, 14, 15, 16. - * The call to mbedtls_gcm_crypt_and_tag or - * mbedtls_gcm_auth_decrypt will validate the tag length. */ - if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(attributes->core.type) != 16) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - mbedtls_gcm_init(&operation->ctx.gcm); - status = mbedtls_to_psa_error( - mbedtls_gcm_setkey(&operation->ctx.gcm, cipher_id, - key_buffer, (unsigned int) key_bits)); - if (status != PSA_SUCCESS) { - return status; - } - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): - operation->alg = PSA_ALG_CHACHA20_POLY1305; - /* We only support the default tag length. */ - if (alg != PSA_ALG_CHACHA20_POLY1305) { - return PSA_ERROR_NOT_SUPPORTED; - } - - mbedtls_chachapoly_init(&operation->ctx.chachapoly); - status = mbedtls_to_psa_error( - mbedtls_chachapoly_setkey(&operation->ctx.chachapoly, - key_buffer)); - if (status != PSA_SUCCESS) { - return status; - } - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - - default: - (void) status; - (void) key_buffer; - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status == PSA_SUCCESS) { - operation->key_type = psa_get_key_type(attributes); - - operation->tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(alg); - } - - return status; -} - -psa_status_t mbedtls_psa_aead_encrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *plaintext, size_t plaintext_length, - uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_psa_aead_operation_t operation = MBEDTLS_PSA_AEAD_OPERATION_INIT; - uint8_t *tag; - - status = psa_aead_setup(&operation, attributes, key_buffer, - key_buffer_size, alg); - - if (status != PSA_SUCCESS) { - goto exit; - } - - /* For all currently supported modes, the tag is at the end of the - * ciphertext. */ - if (ciphertext_size < (plaintext_length + operation.tag_length)) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - tag = ciphertext + plaintext_length; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation.alg == PSA_ALG_CCM) { - status = mbedtls_to_psa_error( - mbedtls_ccm_encrypt_and_tag(&operation.ctx.ccm, - plaintext_length, - nonce, nonce_length, - additional_data, - additional_data_length, - plaintext, ciphertext, - tag, operation.tag_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation.alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_crypt_and_tag(&operation.ctx.gcm, - MBEDTLS_GCM_ENCRYPT, - plaintext_length, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, ciphertext, - operation.tag_length, tag)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation.alg == PSA_ALG_CHACHA20_POLY1305) { - if (operation.tag_length != 16) { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = mbedtls_to_psa_error( - mbedtls_chachapoly_encrypt_and_tag(&operation.ctx.chachapoly, - plaintext_length, - nonce, - additional_data, - additional_data_length, - plaintext, - ciphertext, - tag)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) tag; - (void) nonce; - (void) nonce_length; - (void) additional_data; - (void) additional_data_length; - (void) plaintext; - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status == PSA_SUCCESS) { - *ciphertext_length = plaintext_length + operation.tag_length; - } - -exit: - mbedtls_psa_aead_abort(&operation); - - return status; -} - -/* Locate the tag in a ciphertext buffer containing the encrypted data - * followed by the tag. Return the length of the part preceding the tag in - * *plaintext_length. This is the size of the plaintext in modes where - * the encrypted data has the same size as the plaintext, such as - * CCM and GCM. */ -static psa_status_t psa_aead_unpadded_locate_tag(size_t tag_length, - const uint8_t *ciphertext, - size_t ciphertext_length, - size_t plaintext_size, - const uint8_t **p_tag) -{ - size_t payload_length; - if (tag_length > ciphertext_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - payload_length = ciphertext_length - tag_length; - if (payload_length > plaintext_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - *p_tag = ciphertext + payload_length; - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_aead_decrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *ciphertext, size_t ciphertext_length, - uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_psa_aead_operation_t operation = MBEDTLS_PSA_AEAD_OPERATION_INIT; - const uint8_t *tag = NULL; - - status = psa_aead_setup(&operation, attributes, key_buffer, - key_buffer_size, alg); - - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_aead_unpadded_locate_tag(operation.tag_length, - ciphertext, ciphertext_length, - plaintext_size, &tag); - if (status != PSA_SUCCESS) { - goto exit; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation.alg == PSA_ALG_CCM) { - status = mbedtls_to_psa_error( - mbedtls_ccm_auth_decrypt(&operation.ctx.ccm, - ciphertext_length - operation.tag_length, - nonce, nonce_length, - additional_data, - additional_data_length, - ciphertext, plaintext, - tag, operation.tag_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation.alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_auth_decrypt(&operation.ctx.gcm, - ciphertext_length - operation.tag_length, - nonce, nonce_length, - additional_data, - additional_data_length, - tag, operation.tag_length, - ciphertext, plaintext)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation.alg == PSA_ALG_CHACHA20_POLY1305) { - if (operation.tag_length != 16) { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = mbedtls_to_psa_error( - mbedtls_chachapoly_auth_decrypt(&operation.ctx.chachapoly, - ciphertext_length - operation.tag_length, - nonce, - additional_data, - additional_data_length, - tag, - ciphertext, - plaintext)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) nonce; - (void) nonce_length; - (void) additional_data; - (void) additional_data_length; - (void) plaintext; - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status == PSA_SUCCESS) { - *plaintext_length = ciphertext_length - operation.tag_length; - } - -exit: - mbedtls_psa_aead_abort(&operation); - - if (status == PSA_SUCCESS) { - *plaintext_length = ciphertext_length - operation.tag_length; - } - return status; -} - -/* Set the key and algorithm for a multipart authenticated encryption - * operation. */ -psa_status_t mbedtls_psa_aead_encrypt_setup( - mbedtls_psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_aead_setup(operation, attributes, key_buffer, - key_buffer_size, alg); - - if (status == PSA_SUCCESS) { - operation->is_encrypt = 1; - } - - return status; -} - -/* Set the key and algorithm for a multipart authenticated decryption - * operation. */ -psa_status_t mbedtls_psa_aead_decrypt_setup( - mbedtls_psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_aead_setup(operation, attributes, key_buffer, - key_buffer_size, alg); - - if (status == PSA_SUCCESS) { - operation->is_encrypt = 0; - } - - return status; -} - -/* Set a nonce for the multipart AEAD operation*/ -psa_status_t mbedtls_psa_aead_set_nonce( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation->alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_starts(&operation->ctx.gcm, - operation->is_encrypt ? - MBEDTLS_GCM_ENCRYPT : MBEDTLS_GCM_DECRYPT, - nonce, - nonce_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation->alg == PSA_ALG_CCM) { - status = mbedtls_to_psa_error( - mbedtls_ccm_starts(&operation->ctx.ccm, - operation->is_encrypt ? - MBEDTLS_CCM_ENCRYPT : MBEDTLS_CCM_DECRYPT, - nonce, - nonce_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { - /* Note - ChaChaPoly allows an 8 byte nonce, but we would have to - * allocate a buffer in the operation, copy the nonce to it and pad - * it, so for now check the nonce is 12 bytes, as - * mbedtls_chachapoly_starts() assumes it can read 12 bytes from the - * passed in buffer. */ - if (nonce_length != 12) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = mbedtls_to_psa_error( - mbedtls_chachapoly_starts(&operation->ctx.chachapoly, - nonce, - operation->is_encrypt ? - MBEDTLS_CHACHAPOLY_ENCRYPT : - MBEDTLS_CHACHAPOLY_DECRYPT)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) operation; - (void) nonce; - (void) nonce_length; - - status = PSA_ERROR_NOT_SUPPORTED; - } - - return status; -} - -/* Declare the lengths of the message and additional data for AEAD. */ -psa_status_t mbedtls_psa_aead_set_lengths( - mbedtls_psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length) -{ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation->alg == PSA_ALG_CCM) { - return mbedtls_to_psa_error( - mbedtls_ccm_set_lengths(&operation->ctx.ccm, - ad_length, - plaintext_length, - operation->tag_length)); - - } -#else /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ - (void) operation; - (void) ad_length; - (void) plaintext_length; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ - - return PSA_SUCCESS; -} - -/* Pass additional data to an active multipart AEAD operation. */ -psa_status_t mbedtls_psa_aead_update_ad( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation->alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_update_ad(&operation->ctx.gcm, input, input_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation->alg == PSA_ALG_CCM) { - status = mbedtls_to_psa_error( - mbedtls_ccm_update_ad(&operation->ctx.ccm, input, input_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { - status = mbedtls_to_psa_error( - mbedtls_chachapoly_update_aad(&operation->ctx.chachapoly, - input, - input_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) operation; - (void) input; - (void) input_length; - - status = PSA_ERROR_NOT_SUPPORTED; - } - - return status; -} - -/* Encrypt or decrypt a message fragment in an active multipart AEAD - * operation.*/ -psa_status_t mbedtls_psa_aead_update( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - size_t update_output_length; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - update_output_length = input_length; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation->alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_update(&operation->ctx.gcm, - input, input_length, - output, output_size, - &update_output_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation->alg == PSA_ALG_CCM) { - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = mbedtls_to_psa_error( - mbedtls_ccm_update(&operation->ctx.ccm, - input, input_length, - output, output_size, - &update_output_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { - if (output_size < input_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = mbedtls_to_psa_error( - mbedtls_chachapoly_update(&operation->ctx.chachapoly, - input_length, - input, - output)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) operation; - (void) input; - (void) output; - (void) output_size; - - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status == PSA_SUCCESS) { - *output_length = update_output_length; - } - - return status; -} - -/* Finish encrypting a message in a multipart AEAD operation. */ -psa_status_t mbedtls_psa_aead_finish( - mbedtls_psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t finish_output_size = 0; - - if (tag_size < operation->tag_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - if (operation->alg == PSA_ALG_GCM) { - status = mbedtls_to_psa_error( - mbedtls_gcm_finish(&operation->ctx.gcm, - ciphertext, ciphertext_size, ciphertext_length, - tag, operation->tag_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - if (operation->alg == PSA_ALG_CCM) { - /* tag must be big enough to store a tag of size passed into set - * lengths. */ - if (tag_size < operation->tag_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = mbedtls_to_psa_error( - mbedtls_ccm_finish(&operation->ctx.ccm, - tag, operation->tag_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { - /* Belt and braces. Although the above tag_size check should have - * already done this, if we later start supporting smaller tag sizes - * for chachapoly, then passing a tag buffer smaller than 16 into here - * could cause a buffer overflow, so better safe than sorry. */ - if (tag_size < 16) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = mbedtls_to_psa_error( - mbedtls_chachapoly_finish(&operation->ctx.chachapoly, - tag)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - { - (void) ciphertext; - (void) ciphertext_size; - (void) ciphertext_length; - (void) tag; - (void) tag_size; - (void) tag_length; - - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status == PSA_SUCCESS) { - /* This will be zero for all supported algorithms currently, but left - * here for future support. */ - *ciphertext_length = finish_output_size; - *tag_length = operation->tag_length; - } - - return status; -} - -/* Abort an AEAD operation */ -psa_status_t mbedtls_psa_aead_abort( - mbedtls_psa_aead_operation_t *operation) -{ - switch (operation->alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - case PSA_ALG_CCM: - mbedtls_ccm_free(&operation->ctx.ccm); - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - case PSA_ALG_GCM: - mbedtls_gcm_free(&operation->ctx.gcm); - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - case PSA_ALG_CHACHA20_POLY1305: - mbedtls_chachapoly_free(&operation->ctx.chachapoly); - break; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ - } - - operation->is_encrypt = 0; - - return PSA_SUCCESS; -} - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA AEAD entry points + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include "psa_crypto_aead.h" +#include "psa_crypto_core.h" +#include "psa_crypto_cipher.h" + +#include +#include "mbedtls/platform.h" + +#include "mbedtls/ccm.h" +#include "mbedtls/chachapoly.h" +#include "mbedtls/cipher.h" +#include "mbedtls/gcm.h" +#include "mbedtls/error.h" + +static psa_status_t psa_aead_setup( + mbedtls_psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t key_bits; + const mbedtls_cipher_info_t *cipher_info; + mbedtls_cipher_id_t cipher_id; + + (void) key_buffer_size; + + key_bits = attributes->core.bits; + + cipher_info = mbedtls_cipher_info_from_psa(alg, + attributes->core.type, key_bits, + &cipher_id); + if (cipher_info == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + switch (PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + operation->alg = PSA_ALG_CCM; + /* CCM allows the following tag lengths: 4, 6, 8, 10, 12, 14, 16. + * The call to mbedtls_ccm_encrypt_and_tag or + * mbedtls_ccm_auth_decrypt will validate the tag length. */ + if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(attributes->core.type) != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + mbedtls_ccm_init(&operation->ctx.ccm); + status = mbedtls_to_psa_error( + mbedtls_ccm_setkey(&operation->ctx.ccm, cipher_id, + key_buffer, (unsigned int) key_bits)); + if (status != PSA_SUCCESS) { + return status; + } + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + operation->alg = PSA_ALG_GCM; + /* GCM allows the following tag lengths: 4, 8, 12, 13, 14, 15, 16. + * The call to mbedtls_gcm_crypt_and_tag or + * mbedtls_gcm_auth_decrypt will validate the tag length. */ + if (PSA_BLOCK_CIPHER_BLOCK_LENGTH(attributes->core.type) != 16) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + mbedtls_gcm_init(&operation->ctx.gcm); + status = mbedtls_to_psa_error( + mbedtls_gcm_setkey(&operation->ctx.gcm, cipher_id, + key_buffer, (unsigned int) key_bits)); + if (status != PSA_SUCCESS) { + return status; + } + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + operation->alg = PSA_ALG_CHACHA20_POLY1305; + /* We only support the default tag length. */ + if (alg != PSA_ALG_CHACHA20_POLY1305) { + return PSA_ERROR_NOT_SUPPORTED; + } + + mbedtls_chachapoly_init(&operation->ctx.chachapoly); + status = mbedtls_to_psa_error( + mbedtls_chachapoly_setkey(&operation->ctx.chachapoly, + key_buffer)); + if (status != PSA_SUCCESS) { + return status; + } + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + + default: + (void) status; + (void) key_buffer; + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status == PSA_SUCCESS) { + operation->key_type = psa_get_key_type(attributes); + + operation->tag_length = PSA_ALG_AEAD_GET_TAG_LENGTH(alg); + } + + return status; +} + +psa_status_t mbedtls_psa_aead_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *plaintext, size_t plaintext_length, + uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_psa_aead_operation_t operation = MBEDTLS_PSA_AEAD_OPERATION_INIT; + uint8_t *tag; + + status = psa_aead_setup(&operation, attributes, key_buffer, + key_buffer_size, alg); + + if (status != PSA_SUCCESS) { + goto exit; + } + + /* For all currently supported modes, the tag is at the end of the + * ciphertext. */ + if (ciphertext_size < (plaintext_length + operation.tag_length)) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + tag = ciphertext + plaintext_length; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation.alg == PSA_ALG_CCM) { + status = mbedtls_to_psa_error( + mbedtls_ccm_encrypt_and_tag(&operation.ctx.ccm, + plaintext_length, + nonce, nonce_length, + additional_data, + additional_data_length, + plaintext, ciphertext, + tag, operation.tag_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation.alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_crypt_and_tag(&operation.ctx.gcm, + MBEDTLS_GCM_ENCRYPT, + plaintext_length, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, ciphertext, + operation.tag_length, tag)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation.alg == PSA_ALG_CHACHA20_POLY1305) { + if (operation.tag_length != 16) { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + status = mbedtls_to_psa_error( + mbedtls_chachapoly_encrypt_and_tag(&operation.ctx.chachapoly, + plaintext_length, + nonce, + additional_data, + additional_data_length, + plaintext, + ciphertext, + tag)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) tag; + (void) nonce; + (void) nonce_length; + (void) additional_data; + (void) additional_data_length; + (void) plaintext; + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status == PSA_SUCCESS) { + *ciphertext_length = plaintext_length + operation.tag_length; + } + +exit: + mbedtls_psa_aead_abort(&operation); + + return status; +} + +/* Locate the tag in a ciphertext buffer containing the encrypted data + * followed by the tag. Return the length of the part preceding the tag in + * *plaintext_length. This is the size of the plaintext in modes where + * the encrypted data has the same size as the plaintext, such as + * CCM and GCM. */ +static psa_status_t psa_aead_unpadded_locate_tag(size_t tag_length, + const uint8_t *ciphertext, + size_t ciphertext_length, + size_t plaintext_size, + const uint8_t **p_tag) +{ + size_t payload_length; + if (tag_length > ciphertext_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + payload_length = ciphertext_length - tag_length; + if (payload_length > plaintext_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + *p_tag = ciphertext + payload_length; + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_aead_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *ciphertext, size_t ciphertext_length, + uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_psa_aead_operation_t operation = MBEDTLS_PSA_AEAD_OPERATION_INIT; + const uint8_t *tag = NULL; + + status = psa_aead_setup(&operation, attributes, key_buffer, + key_buffer_size, alg); + + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_aead_unpadded_locate_tag(operation.tag_length, + ciphertext, ciphertext_length, + plaintext_size, &tag); + if (status != PSA_SUCCESS) { + goto exit; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation.alg == PSA_ALG_CCM) { + status = mbedtls_to_psa_error( + mbedtls_ccm_auth_decrypt(&operation.ctx.ccm, + ciphertext_length - operation.tag_length, + nonce, nonce_length, + additional_data, + additional_data_length, + ciphertext, plaintext, + tag, operation.tag_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation.alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_auth_decrypt(&operation.ctx.gcm, + ciphertext_length - operation.tag_length, + nonce, nonce_length, + additional_data, + additional_data_length, + tag, operation.tag_length, + ciphertext, plaintext)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation.alg == PSA_ALG_CHACHA20_POLY1305) { + if (operation.tag_length != 16) { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + status = mbedtls_to_psa_error( + mbedtls_chachapoly_auth_decrypt(&operation.ctx.chachapoly, + ciphertext_length - operation.tag_length, + nonce, + additional_data, + additional_data_length, + tag, + ciphertext, + plaintext)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) nonce; + (void) nonce_length; + (void) additional_data; + (void) additional_data_length; + (void) plaintext; + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status == PSA_SUCCESS) { + *plaintext_length = ciphertext_length - operation.tag_length; + } + +exit: + mbedtls_psa_aead_abort(&operation); + + if (status == PSA_SUCCESS) { + *plaintext_length = ciphertext_length - operation.tag_length; + } + return status; +} + +/* Set the key and algorithm for a multipart authenticated encryption + * operation. */ +psa_status_t mbedtls_psa_aead_encrypt_setup( + mbedtls_psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_aead_setup(operation, attributes, key_buffer, + key_buffer_size, alg); + + if (status == PSA_SUCCESS) { + operation->is_encrypt = 1; + } + + return status; +} + +/* Set the key and algorithm for a multipart authenticated decryption + * operation. */ +psa_status_t mbedtls_psa_aead_decrypt_setup( + mbedtls_psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_aead_setup(operation, attributes, key_buffer, + key_buffer_size, alg); + + if (status == PSA_SUCCESS) { + operation->is_encrypt = 0; + } + + return status; +} + +/* Set a nonce for the multipart AEAD operation*/ +psa_status_t mbedtls_psa_aead_set_nonce( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation->alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_starts(&operation->ctx.gcm, + operation->is_encrypt ? + MBEDTLS_GCM_ENCRYPT : MBEDTLS_GCM_DECRYPT, + nonce, + nonce_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation->alg == PSA_ALG_CCM) { + status = mbedtls_to_psa_error( + mbedtls_ccm_starts(&operation->ctx.ccm, + operation->is_encrypt ? + MBEDTLS_CCM_ENCRYPT : MBEDTLS_CCM_DECRYPT, + nonce, + nonce_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { + /* Note - ChaChaPoly allows an 8 byte nonce, but we would have to + * allocate a buffer in the operation, copy the nonce to it and pad + * it, so for now check the nonce is 12 bytes, as + * mbedtls_chachapoly_starts() assumes it can read 12 bytes from the + * passed in buffer. */ + if (nonce_length != 12) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = mbedtls_to_psa_error( + mbedtls_chachapoly_starts(&operation->ctx.chachapoly, + nonce, + operation->is_encrypt ? + MBEDTLS_CHACHAPOLY_ENCRYPT : + MBEDTLS_CHACHAPOLY_DECRYPT)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) operation; + (void) nonce; + (void) nonce_length; + + status = PSA_ERROR_NOT_SUPPORTED; + } + + return status; +} + +/* Declare the lengths of the message and additional data for AEAD. */ +psa_status_t mbedtls_psa_aead_set_lengths( + mbedtls_psa_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length) +{ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation->alg == PSA_ALG_CCM) { + return mbedtls_to_psa_error( + mbedtls_ccm_set_lengths(&operation->ctx.ccm, + ad_length, + plaintext_length, + operation->tag_length)); + + } +#else /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ + (void) operation; + (void) ad_length; + (void) plaintext_length; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ + + return PSA_SUCCESS; +} + +/* Pass additional data to an active multipart AEAD operation. */ +psa_status_t mbedtls_psa_aead_update_ad( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation->alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_update_ad(&operation->ctx.gcm, input, input_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation->alg == PSA_ALG_CCM) { + status = mbedtls_to_psa_error( + mbedtls_ccm_update_ad(&operation->ctx.ccm, input, input_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { + status = mbedtls_to_psa_error( + mbedtls_chachapoly_update_aad(&operation->ctx.chachapoly, + input, + input_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) operation; + (void) input; + (void) input_length; + + status = PSA_ERROR_NOT_SUPPORTED; + } + + return status; +} + +/* Encrypt or decrypt a message fragment in an active multipart AEAD + * operation.*/ +psa_status_t mbedtls_psa_aead_update( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + size_t update_output_length; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + update_output_length = input_length; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation->alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_update(&operation->ctx.gcm, + input, input_length, + output, output_size, + &update_output_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation->alg == PSA_ALG_CCM) { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = mbedtls_to_psa_error( + mbedtls_ccm_update(&operation->ctx.ccm, + input, input_length, + output, output_size, + &update_output_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { + if (output_size < input_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = mbedtls_to_psa_error( + mbedtls_chachapoly_update(&operation->ctx.chachapoly, + input_length, + input, + output)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) operation; + (void) input; + (void) output; + (void) output_size; + + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status == PSA_SUCCESS) { + *output_length = update_output_length; + } + + return status; +} + +/* Finish encrypting a message in a multipart AEAD operation. */ +psa_status_t mbedtls_psa_aead_finish( + mbedtls_psa_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t finish_output_size = 0; + + if (tag_size < operation->tag_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + if (operation->alg == PSA_ALG_GCM) { + status = mbedtls_to_psa_error( + mbedtls_gcm_finish(&operation->ctx.gcm, + ciphertext, ciphertext_size, ciphertext_length, + tag, operation->tag_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + if (operation->alg == PSA_ALG_CCM) { + /* tag must be big enough to store a tag of size passed into set + * lengths. */ + if (tag_size < operation->tag_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = mbedtls_to_psa_error( + mbedtls_ccm_finish(&operation->ctx.ccm, + tag, operation->tag_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + if (operation->alg == PSA_ALG_CHACHA20_POLY1305) { + /* Belt and braces. Although the above tag_size check should have + * already done this, if we later start supporting smaller tag sizes + * for chachapoly, then passing a tag buffer smaller than 16 into here + * could cause a buffer overflow, so better safe than sorry. */ + if (tag_size < 16) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = mbedtls_to_psa_error( + mbedtls_chachapoly_finish(&operation->ctx.chachapoly, + tag)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + { + (void) ciphertext; + (void) ciphertext_size; + (void) ciphertext_length; + (void) tag; + (void) tag_size; + (void) tag_length; + + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status == PSA_SUCCESS) { + /* This will be zero for all supported algorithms currently, but left + * here for future support. */ + *ciphertext_length = finish_output_size; + *tag_length = operation->tag_length; + } + + return status; +} + +/* Abort an AEAD operation */ +psa_status_t mbedtls_psa_aead_abort( + mbedtls_psa_aead_operation_t *operation) +{ + switch (operation->alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + case PSA_ALG_CCM: + mbedtls_ccm_free(&operation->ctx.ccm); + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + case PSA_ALG_GCM: + mbedtls_gcm_free(&operation->ctx.gcm); + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_GCM */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + case PSA_ALG_CHACHA20_POLY1305: + mbedtls_chachapoly_free(&operation->ctx.chachapoly); + break; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305 */ + } + + operation->is_encrypt = 0; + + return PSA_SUCCESS; +} + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.h index 4b24b0f..95c7488 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_aead.h @@ -1,511 +1,511 @@ -/* - * PSA AEAD driver entry points - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_AEAD_H -#define PSA_CRYPTO_AEAD_H - -#include - -/** - * \brief Process an authenticated encryption operation. - * - * \note The signature of this function is that of a PSA driver - * aead_encrypt entry point. This function behaves as an aead_encrypt - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param alg The AEAD algorithm to compute. - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the nonce buffer in bytes. This must - * be appropriate for the selected algorithm. - * The default nonce size is - * PSA_AEAD_NONCE_LENGTH(key_type, alg) where - * key_type is the type of key. - * \param[in] additional_data Additional data that will be authenticated - * but not encrypted. - * \param additional_data_length Size of additional_data in bytes. - * \param[in] plaintext Data that will be authenticated and encrypted. - * \param plaintext_length Size of plaintext in bytes. - * \param[out] ciphertext Output buffer for the authenticated and - * encrypted data. The additional data is not - * part of this output. For algorithms where the - * encrypted data and the authentication tag are - * defined as separate outputs, the - * authentication tag is appended to the - * encrypted data. - * \param ciphertext_size Size of the ciphertext buffer in bytes. This - * must be appropriate for the selected algorithm - * and key: - * - A sufficient output size is - * PSA_AEAD_ENCRYPT_OUTPUT_SIZE(key_type, alg, - * plaintext_length) where key_type is the type - * of key. - * - PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE( - * plaintext_length) evaluates to the maximum - * ciphertext size of any supported AEAD - * encryption. - * \param[out] ciphertext_length On success, the size of the output in the - * ciphertext buffer. - * - * \retval #PSA_SUCCESS Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * ciphertext_size is too small. - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_aead_encrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *plaintext, size_t plaintext_length, - uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length); - -/** - * \brief Process an authenticated decryption operation. - * - * \note The signature of this function is that of a PSA driver - * aead_decrypt entry point. This function behaves as an aead_decrypt - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param alg The AEAD algorithm to compute. - * \param[in] nonce Nonce or IV to use. - * \param nonce_length Size of the nonce buffer in bytes. This must - * be appropriate for the selected algorithm. - * The default nonce size is - * PSA_AEAD_NONCE_LENGTH(key_type, alg) where - * key_type is the type of key. - * \param[in] additional_data Additional data that has been authenticated - * but not encrypted. - * \param additional_data_length Size of additional_data in bytes. - * \param[in] ciphertext Data that has been authenticated and - * encrypted. For algorithms where the encrypted - * data and the authentication tag are defined - * as separate inputs, the buffer contains - * encrypted data followed by the authentication - * tag. - * \param ciphertext_length Size of ciphertext in bytes. - * \param[out] plaintext Output buffer for the decrypted data. - * \param plaintext_size Size of the plaintext buffer in bytes. This - * must be appropriate for the selected algorithm - * and key: - * - A sufficient output size is - * PSA_AEAD_DECRYPT_OUTPUT_SIZE(key_type, alg, - * ciphertext_length) where key_type is the - * type of key. - * - PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE( - * ciphertext_length) evaluates to the maximum - * plaintext size of any supported AEAD - * decryption. - * \param[out] plaintext_length On success, the size of the output in the - * plaintext buffer. - * - * \retval #PSA_SUCCESS Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The cipher is not authentic. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * plaintext_size is too small. - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_aead_decrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *ciphertext, size_t ciphertext_length, - uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length); - -/** Set the key for a multipart authenticated encryption operation. - * - * \note The signature of this function is that of a PSA driver - * aead_encrypt_setup entry point. This function behaves as an - * aead_encrypt_setup entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * If an error occurs at any step after a call to - * mbedtls_psa_aead_encrypt_setup(), the operation is reset by the PSA core by a - * call to mbedtls_psa_aead_abort(). The PSA core may call - * mbedtls_psa_aead_abort() at any time after the operation has been - * initialized, and is required to when the operation is no longer needed. - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #mbedtls_psa_aead_operation_t and not yet in - * use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - It must be consistent with the size in bits - recorded in \p attributes. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * An invalid block length was supplied. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * Failed to allocate memory for key material - */ -psa_status_t mbedtls_psa_aead_encrypt_setup( - mbedtls_psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -/** Set the key for a multipart authenticated decryption operation. - * - * \note The signature of this function is that of a PSA driver - * aead_decrypt_setup entry point. This function behaves as an - * aead_decrypt_setup entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * If an error occurs at any step after a call to - * mbedtls_psa_aead_decrypt_setup(), the PSA core resets the operation by a - * call to mbedtls_psa_aead_abort(). The PSA core may call - * mbedtls_psa_aead_abort() at any time after the operation has been - * initialized, and is required to when the operation is no longer needed. - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized as per the documentation for - * #mbedtls_psa_aead_operation_t and not yet in - * use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - It must be consistent with the size in bits - recorded in \p attributes. - * \param alg The AEAD algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_AEAD(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * An invalid block length was supplied. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * Failed to allocate memory for key material - */ -psa_status_t mbedtls_psa_aead_decrypt_setup( - mbedtls_psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -/** Set the nonce for an authenticated encryption or decryption operation. - * - * \note The signature of this function is that of a PSA driver aead_set_nonce - * entry point. This function behaves as an aead_set_nonce entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * This function sets the nonce for the authenticated - * encryption or decryption operation. - * - * The PSA core calls mbedtls_psa_aead_encrypt_setup() or - * mbedtls_psa_aead_decrypt_setup() before calling this function. - * - * If this function returns an error status, the PSA core will call - * mbedtls_psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[in] nonce Buffer containing the nonce to use. - * \param nonce_length Size of the nonce in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p nonce is not acceptable for the chosen algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Algorithm previously set is not supported in this configuration of - * the library. - */ -psa_status_t mbedtls_psa_aead_set_nonce( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length); - -/** Declare the lengths of the message and additional data for AEAD. - * - * \note The signature of this function is that of a PSA driver aead_set_lengths - * entry point. This function behaves as an aead_set_lengths entry point - * as defined in the PSA driver interface specification for transparent - * drivers. - * - * The PSA core calls this function before calling mbedtls_psa_aead_update_ad() - * or mbedtls_psa_aead_update() if the algorithm for the operation requires it. - * If the algorithm does not require it, calling this function is optional, but - * if this function is called then the implementation must enforce the lengths. - * - * The PSA core may call this function before or after setting the nonce with - * mbedtls_psa_aead_set_nonce(). - * - * - For #PSA_ALG_CCM, calling this function is required. - * - For the other AEAD algorithms defined in this specification, calling - * this function is not required. - * - * If this function returns an error status, the PSA core calls - * mbedtls_psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param ad_length Size of the non-encrypted additional - * authenticated data in bytes. - * \param plaintext_length Size of the plaintext to encrypt in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * At least one of the lengths is not acceptable for the chosen - * algorithm. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Algorithm previously set is not supported in this configuration of - * the library. - */ -psa_status_t mbedtls_psa_aead_set_lengths( - mbedtls_psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length); - -/** Pass additional data to an active AEAD operation. - * - * \note The signature of this function is that of a PSA driver - * aead_update_ad entry point. This function behaves as an aead_update_ad - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * Additional data is authenticated, but not encrypted. - * - * The PSA core can call this function multiple times to pass successive - * fragments of the additional data. It will not call this function after - * passing data to encrypt or decrypt with mbedtls_psa_aead_update(). - * - * Before calling this function, the PSA core will: - * 1. Call either mbedtls_psa_aead_encrypt_setup() or - * mbedtls_psa_aead_decrypt_setup(). - * 2. Set the nonce with mbedtls_psa_aead_set_nonce(). - * - * If this function returns an error status, the PSA core will call - * mbedtls_psa_aead_abort(). - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the fragment of - * additional data. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Algorithm previously set is not supported in this configuration of - * the library. - */ -psa_status_t mbedtls_psa_aead_update_ad( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Encrypt or decrypt a message fragment in an active AEAD operation. - * - * \note The signature of this function is that of a PSA driver - * aead_update entry point. This function behaves as an aead_update entry - * point as defined in the PSA driver interface specification for - * transparent drivers. - * - * Before calling this function, the PSA core will: - * 1. Call either mbedtls_psa_aead_encrypt_setup() or - * mbedtls_psa_aead_decrypt_setup(). The choice of setup function - * determines whether this function encrypts or decrypts its input. - * 2. Set the nonce with mbedtls_psa_aead_set_nonce(). - * 3. Call mbedtls_psa_aead_update_ad() to pass all the additional data. - * - * If this function returns an error status, the PSA core will call - * mbedtls_psa_aead_abort(). - * - * This function does not require the input to be aligned to any - * particular block boundary. If the implementation can only process - * a whole block at a time, it must consume all the input provided, but - * it may delay the end of the corresponding output until a subsequent - * call to mbedtls_psa_aead_update(), mbedtls_psa_aead_finish() provides - * sufficient input. The amount of data that can be delayed in this way is - * bounded by #PSA_AEAD_UPDATE_OUTPUT_SIZE. - * - * \param[in,out] operation Active AEAD operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param output_size Size of the \p output buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, - * \c alg, \p input_length) where - * \c key_type is the type of key and \c alg is - * the algorithm that were used to set up the - * operation. - * - #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p - * input_length) evaluates to the maximum - * output size of any supported AEAD - * algorithm. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS - * Success. - * - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, \c alg, \p input_length) or - * #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length) can be used to - * determine the required buffer size. - */ -psa_status_t mbedtls_psa_aead_update( - mbedtls_psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Finish encrypting a message in an AEAD operation. - * - * \note The signature of this function is that of a PSA driver - * aead_finish entry point. This function behaves as an aead_finish entry - * point as defined in the PSA driver interface specification for - * transparent drivers. - * - * The operation must have been set up by the PSA core with - * mbedtls_psa_aead_encrypt_setup(). - * - * This function finishes the authentication of the additional data - * formed by concatenating the inputs passed to preceding calls to - * mbedtls_psa_aead_update_ad() with the plaintext formed by concatenating the - * inputs passed to preceding calls to mbedtls_psa_aead_update(). - * - * This function has two output buffers: - * - \p ciphertext contains trailing ciphertext that was buffered from - * preceding calls to mbedtls_psa_aead_update(). - * - \p tag contains the authentication tag. - * - * Whether or not this function returns successfully, the PSA core subsequently - * calls mbedtls_psa_aead_abort() to deactivate the operation. - * - * \param[in,out] operation Active AEAD operation. - * \param[out] ciphertext Buffer where the last part of the ciphertext - * is to be written. - * \param ciphertext_size Size of the \p ciphertext buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - A sufficient output size is - * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, - * \c alg) where \c key_type is the type of key - * and \c alg is the algorithm that were used to - * set up the operation. - * - #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE evaluates to - * the maximum output size of any supported AEAD - * algorithm. - * \param[out] ciphertext_length On success, the number of bytes of - * returned ciphertext. - * \param[out] tag Buffer where the authentication tag is - * to be written. - * \param tag_size Size of the \p tag buffer in bytes. - * This must be appropriate for the selected - * algorithm and key: - * - The exact tag size is #PSA_AEAD_TAG_LENGTH(\c - * key_type, \c key_bits, \c alg) where - * \c key_type and \c key_bits are the type and - * bit-size of the key, and \c alg are the - * algorithm that were used in the call to - * mbedtls_psa_aead_encrypt_setup(). - * - #PSA_AEAD_TAG_MAX_SIZE evaluates to the - * maximum tag size of any supported AEAD - * algorithm. - * \param[out] tag_length On success, the number of bytes - * that make up the returned tag. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p tag buffer is too small. - * #PSA_AEAD_TAG_LENGTH(\c key_type, key_bits, \c alg) or - * #PSA_AEAD_TAG_MAX_SIZE can be used to determine the required \p tag - * buffer size. - */ -psa_status_t mbedtls_psa_aead_finish( - mbedtls_psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length); - -/** Abort an AEAD operation. - * - * \note The signature of this function is that of a PSA driver - * aead_abort entry point. This function behaves as an aead_abort entry - * point as defined in the PSA driver interface specification for - * transparent drivers. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by the PSA core by it calling - * mbedtls_psa_aead_encrypt_setup() or mbedtls_psa_aead_decrypt_setup() again. - * - * The PSA core may call this function any time after the operation object has - * been initialized as described in #mbedtls_psa_aead_operation_t. - * - * In particular, calling mbedtls_psa_aead_abort() after the operation has been - * terminated by a call to mbedtls_psa_aead_abort() or - * mbedtls_psa_aead_finish() is safe and has no effect. - * - * \param[in,out] operation Initialized AEAD operation. - * - * \retval #PSA_SUCCESS - * Success. - */ -psa_status_t mbedtls_psa_aead_abort( - mbedtls_psa_aead_operation_t *operation); - -#endif /* PSA_CRYPTO_AEAD_H */ +/* + * PSA AEAD driver entry points + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_AEAD_H +#define PSA_CRYPTO_AEAD_H + +#include + +/** + * \brief Process an authenticated encryption operation. + * + * \note The signature of this function is that of a PSA driver + * aead_encrypt entry point. This function behaves as an aead_encrypt + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param alg The AEAD algorithm to compute. + * \param[in] nonce Nonce or IV to use. + * \param nonce_length Size of the nonce buffer in bytes. This must + * be appropriate for the selected algorithm. + * The default nonce size is + * PSA_AEAD_NONCE_LENGTH(key_type, alg) where + * key_type is the type of key. + * \param[in] additional_data Additional data that will be authenticated + * but not encrypted. + * \param additional_data_length Size of additional_data in bytes. + * \param[in] plaintext Data that will be authenticated and encrypted. + * \param plaintext_length Size of plaintext in bytes. + * \param[out] ciphertext Output buffer for the authenticated and + * encrypted data. The additional data is not + * part of this output. For algorithms where the + * encrypted data and the authentication tag are + * defined as separate outputs, the + * authentication tag is appended to the + * encrypted data. + * \param ciphertext_size Size of the ciphertext buffer in bytes. This + * must be appropriate for the selected algorithm + * and key: + * - A sufficient output size is + * PSA_AEAD_ENCRYPT_OUTPUT_SIZE(key_type, alg, + * plaintext_length) where key_type is the type + * of key. + * - PSA_AEAD_ENCRYPT_OUTPUT_MAX_SIZE( + * plaintext_length) evaluates to the maximum + * ciphertext size of any supported AEAD + * encryption. + * \param[out] ciphertext_length On success, the size of the output in the + * ciphertext buffer. + * + * \retval #PSA_SUCCESS Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * ciphertext_size is too small. + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_aead_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *plaintext, size_t plaintext_length, + uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length); + +/** + * \brief Process an authenticated decryption operation. + * + * \note The signature of this function is that of a PSA driver + * aead_decrypt entry point. This function behaves as an aead_decrypt + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param alg The AEAD algorithm to compute. + * \param[in] nonce Nonce or IV to use. + * \param nonce_length Size of the nonce buffer in bytes. This must + * be appropriate for the selected algorithm. + * The default nonce size is + * PSA_AEAD_NONCE_LENGTH(key_type, alg) where + * key_type is the type of key. + * \param[in] additional_data Additional data that has been authenticated + * but not encrypted. + * \param additional_data_length Size of additional_data in bytes. + * \param[in] ciphertext Data that has been authenticated and + * encrypted. For algorithms where the encrypted + * data and the authentication tag are defined + * as separate inputs, the buffer contains + * encrypted data followed by the authentication + * tag. + * \param ciphertext_length Size of ciphertext in bytes. + * \param[out] plaintext Output buffer for the decrypted data. + * \param plaintext_size Size of the plaintext buffer in bytes. This + * must be appropriate for the selected algorithm + * and key: + * - A sufficient output size is + * PSA_AEAD_DECRYPT_OUTPUT_SIZE(key_type, alg, + * ciphertext_length) where key_type is the + * type of key. + * - PSA_AEAD_DECRYPT_OUTPUT_MAX_SIZE( + * ciphertext_length) evaluates to the maximum + * plaintext size of any supported AEAD + * decryption. + * \param[out] plaintext_length On success, the size of the output in the + * plaintext buffer. + * + * \retval #PSA_SUCCESS Success. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The cipher is not authentic. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * plaintext_size is too small. + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_aead_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *ciphertext, size_t ciphertext_length, + uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length); + +/** Set the key for a multipart authenticated encryption operation. + * + * \note The signature of this function is that of a PSA driver + * aead_encrypt_setup entry point. This function behaves as an + * aead_encrypt_setup entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * If an error occurs at any step after a call to + * mbedtls_psa_aead_encrypt_setup(), the operation is reset by the PSA core by a + * call to mbedtls_psa_aead_abort(). The PSA core may call + * mbedtls_psa_aead_abort() at any time after the operation has been + * initialized, and is required to when the operation is no longer needed. + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #mbedtls_psa_aead_operation_t and not yet in + * use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + It must be consistent with the size in bits + recorded in \p attributes. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * An invalid block length was supplied. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * Failed to allocate memory for key material + */ +psa_status_t mbedtls_psa_aead_encrypt_setup( + mbedtls_psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +/** Set the key for a multipart authenticated decryption operation. + * + * \note The signature of this function is that of a PSA driver + * aead_decrypt_setup entry point. This function behaves as an + * aead_decrypt_setup entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * If an error occurs at any step after a call to + * mbedtls_psa_aead_decrypt_setup(), the PSA core resets the operation by a + * call to mbedtls_psa_aead_abort(). The PSA core may call + * mbedtls_psa_aead_abort() at any time after the operation has been + * initialized, and is required to when the operation is no longer needed. + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized as per the documentation for + * #mbedtls_psa_aead_operation_t and not yet in + * use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + It must be consistent with the size in bits + recorded in \p attributes. + * \param alg The AEAD algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * An invalid block length was supplied. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * Failed to allocate memory for key material + */ +psa_status_t mbedtls_psa_aead_decrypt_setup( + mbedtls_psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +/** Set the nonce for an authenticated encryption or decryption operation. + * + * \note The signature of this function is that of a PSA driver aead_set_nonce + * entry point. This function behaves as an aead_set_nonce entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * This function sets the nonce for the authenticated + * encryption or decryption operation. + * + * The PSA core calls mbedtls_psa_aead_encrypt_setup() or + * mbedtls_psa_aead_decrypt_setup() before calling this function. + * + * If this function returns an error status, the PSA core will call + * mbedtls_psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param[in] nonce Buffer containing the nonce to use. + * \param nonce_length Size of the nonce in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size of \p nonce is not acceptable for the chosen algorithm. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Algorithm previously set is not supported in this configuration of + * the library. + */ +psa_status_t mbedtls_psa_aead_set_nonce( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length); + +/** Declare the lengths of the message and additional data for AEAD. + * + * \note The signature of this function is that of a PSA driver aead_set_lengths + * entry point. This function behaves as an aead_set_lengths entry point + * as defined in the PSA driver interface specification for transparent + * drivers. + * + * The PSA core calls this function before calling mbedtls_psa_aead_update_ad() + * or mbedtls_psa_aead_update() if the algorithm for the operation requires it. + * If the algorithm does not require it, calling this function is optional, but + * if this function is called then the implementation must enforce the lengths. + * + * The PSA core may call this function before or after setting the nonce with + * mbedtls_psa_aead_set_nonce(). + * + * - For #PSA_ALG_CCM, calling this function is required. + * - For the other AEAD algorithms defined in this specification, calling + * this function is not required. + * + * If this function returns an error status, the PSA core calls + * mbedtls_psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param ad_length Size of the non-encrypted additional + * authenticated data in bytes. + * \param plaintext_length Size of the plaintext to encrypt in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * At least one of the lengths is not acceptable for the chosen + * algorithm. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Algorithm previously set is not supported in this configuration of + * the library. + */ +psa_status_t mbedtls_psa_aead_set_lengths( + mbedtls_psa_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length); + +/** Pass additional data to an active AEAD operation. + * + * \note The signature of this function is that of a PSA driver + * aead_update_ad entry point. This function behaves as an aead_update_ad + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * Additional data is authenticated, but not encrypted. + * + * The PSA core can call this function multiple times to pass successive + * fragments of the additional data. It will not call this function after + * passing data to encrypt or decrypt with mbedtls_psa_aead_update(). + * + * Before calling this function, the PSA core will: + * 1. Call either mbedtls_psa_aead_encrypt_setup() or + * mbedtls_psa_aead_decrypt_setup(). + * 2. Set the nonce with mbedtls_psa_aead_set_nonce(). + * + * If this function returns an error status, the PSA core will call + * mbedtls_psa_aead_abort(). + * + * \param[in,out] operation Active AEAD operation. + * \param[in] input Buffer containing the fragment of + * additional data. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Algorithm previously set is not supported in this configuration of + * the library. + */ +psa_status_t mbedtls_psa_aead_update_ad( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Encrypt or decrypt a message fragment in an active AEAD operation. + * + * \note The signature of this function is that of a PSA driver + * aead_update entry point. This function behaves as an aead_update entry + * point as defined in the PSA driver interface specification for + * transparent drivers. + * + * Before calling this function, the PSA core will: + * 1. Call either mbedtls_psa_aead_encrypt_setup() or + * mbedtls_psa_aead_decrypt_setup(). The choice of setup function + * determines whether this function encrypts or decrypts its input. + * 2. Set the nonce with mbedtls_psa_aead_set_nonce(). + * 3. Call mbedtls_psa_aead_update_ad() to pass all the additional data. + * + * If this function returns an error status, the PSA core will call + * mbedtls_psa_aead_abort(). + * + * This function does not require the input to be aligned to any + * particular block boundary. If the implementation can only process + * a whole block at a time, it must consume all the input provided, but + * it may delay the end of the corresponding output until a subsequent + * call to mbedtls_psa_aead_update(), mbedtls_psa_aead_finish() provides + * sufficient input. The amount of data that can be delayed in this way is + * bounded by #PSA_AEAD_UPDATE_OUTPUT_SIZE. + * + * \param[in,out] operation Active AEAD operation. + * \param[in] input Buffer containing the message fragment to + * encrypt or decrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * \param output_size Size of the \p output buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, + * \c alg, \p input_length) where + * \c key_type is the type of key and \c alg is + * the algorithm that were used to set up the + * operation. + * - #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p + * input_length) evaluates to the maximum + * output size of any supported AEAD + * algorithm. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS + * Success. + * + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * #PSA_AEAD_UPDATE_OUTPUT_SIZE(\c key_type, \c alg, \p input_length) or + * #PSA_AEAD_UPDATE_OUTPUT_MAX_SIZE(\p input_length) can be used to + * determine the required buffer size. + */ +psa_status_t mbedtls_psa_aead_update( + mbedtls_psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Finish encrypting a message in an AEAD operation. + * + * \note The signature of this function is that of a PSA driver + * aead_finish entry point. This function behaves as an aead_finish entry + * point as defined in the PSA driver interface specification for + * transparent drivers. + * + * The operation must have been set up by the PSA core with + * mbedtls_psa_aead_encrypt_setup(). + * + * This function finishes the authentication of the additional data + * formed by concatenating the inputs passed to preceding calls to + * mbedtls_psa_aead_update_ad() with the plaintext formed by concatenating the + * inputs passed to preceding calls to mbedtls_psa_aead_update(). + * + * This function has two output buffers: + * - \p ciphertext contains trailing ciphertext that was buffered from + * preceding calls to mbedtls_psa_aead_update(). + * - \p tag contains the authentication tag. + * + * Whether or not this function returns successfully, the PSA core subsequently + * calls mbedtls_psa_aead_abort() to deactivate the operation. + * + * \param[in,out] operation Active AEAD operation. + * \param[out] ciphertext Buffer where the last part of the ciphertext + * is to be written. + * \param ciphertext_size Size of the \p ciphertext buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - A sufficient output size is + * #PSA_AEAD_FINISH_OUTPUT_SIZE(\c key_type, + * \c alg) where \c key_type is the type of key + * and \c alg is the algorithm that were used to + * set up the operation. + * - #PSA_AEAD_FINISH_OUTPUT_MAX_SIZE evaluates to + * the maximum output size of any supported AEAD + * algorithm. + * \param[out] ciphertext_length On success, the number of bytes of + * returned ciphertext. + * \param[out] tag Buffer where the authentication tag is + * to be written. + * \param tag_size Size of the \p tag buffer in bytes. + * This must be appropriate for the selected + * algorithm and key: + * - The exact tag size is #PSA_AEAD_TAG_LENGTH(\c + * key_type, \c key_bits, \c alg) where + * \c key_type and \c key_bits are the type and + * bit-size of the key, and \c alg are the + * algorithm that were used in the call to + * mbedtls_psa_aead_encrypt_setup(). + * - #PSA_AEAD_TAG_MAX_SIZE evaluates to the + * maximum tag size of any supported AEAD + * algorithm. + * \param[out] tag_length On success, the number of bytes + * that make up the returned tag. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p tag buffer is too small. + * #PSA_AEAD_TAG_LENGTH(\c key_type, key_bits, \c alg) or + * #PSA_AEAD_TAG_MAX_SIZE can be used to determine the required \p tag + * buffer size. + */ +psa_status_t mbedtls_psa_aead_finish( + mbedtls_psa_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length); + +/** Abort an AEAD operation. + * + * \note The signature of this function is that of a PSA driver + * aead_abort entry point. This function behaves as an aead_abort entry + * point as defined in the PSA driver interface specification for + * transparent drivers. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by the PSA core by it calling + * mbedtls_psa_aead_encrypt_setup() or mbedtls_psa_aead_decrypt_setup() again. + * + * The PSA core may call this function any time after the operation object has + * been initialized as described in #mbedtls_psa_aead_operation_t. + * + * In particular, calling mbedtls_psa_aead_abort() after the operation has been + * terminated by a call to mbedtls_psa_aead_abort() or + * mbedtls_psa_aead_finish() is safe and has no effect. + * + * \param[in,out] operation Initialized AEAD operation. + * + * \retval #PSA_SUCCESS + * Success. + */ +psa_status_t mbedtls_psa_aead_abort( + mbedtls_psa_aead_operation_t *operation); + +#endif /* PSA_CRYPTO_AEAD_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.c index 1475a9c..e94f3de 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.c @@ -1,616 +1,616 @@ -/* - * PSA cipher driver entry points - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include "psa_crypto_cipher.h" -#include "psa_crypto_core.h" -#include "psa_crypto_random_impl.h" - -#include "mbedtls/cipher.h" -#include "mbedtls/error.h" - -#include - -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( - psa_algorithm_t alg, - psa_key_type_t key_type, - size_t key_bits, - mbedtls_cipher_id_t *cipher_id) -{ -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20) - - mbedtls_cipher_mode_t mode; - mbedtls_cipher_id_t cipher_id_tmp; - - if (PSA_ALG_IS_AEAD(alg)) { - alg = PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0); - } - - if (PSA_ALG_IS_CIPHER(alg) || PSA_ALG_IS_AEAD(alg)) { - switch (alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER) - case PSA_ALG_STREAM_CIPHER: - mode = MBEDTLS_MODE_STREAM; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CTR) - case PSA_ALG_CTR: - mode = MBEDTLS_MODE_CTR; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CFB) - case PSA_ALG_CFB: - mode = MBEDTLS_MODE_CFB; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_OFB) - case PSA_ALG_OFB: - mode = MBEDTLS_MODE_OFB; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) - case PSA_ALG_ECB_NO_PADDING: - mode = MBEDTLS_MODE_ECB; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) - case PSA_ALG_CBC_NO_PADDING: - mode = MBEDTLS_MODE_CBC; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) - case PSA_ALG_CBC_PKCS7: - mode = MBEDTLS_MODE_CBC; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG) - case PSA_ALG_CCM_STAR_NO_TAG: - mode = MBEDTLS_MODE_CCM_STAR_NO_TAG; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): - mode = MBEDTLS_MODE_CCM; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): - mode = MBEDTLS_MODE_GCM; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) - case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): - mode = MBEDTLS_MODE_CHACHAPOLY; - break; -#endif - default: - return NULL; - } - } else if (alg == PSA_ALG_CMAC) { - mode = MBEDTLS_MODE_ECB; - } else { - return NULL; - } - - switch (key_type) { -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES) - case PSA_KEY_TYPE_AES: - cipher_id_tmp = MBEDTLS_CIPHER_ID_AES; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA) - case PSA_KEY_TYPE_ARIA: - cipher_id_tmp = MBEDTLS_CIPHER_ID_ARIA; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) - case PSA_KEY_TYPE_DES: - /* key_bits is 64 for Single-DES, 128 for two-key Triple-DES, - * and 192 for three-key Triple-DES. */ - if (key_bits == 64) { - cipher_id_tmp = MBEDTLS_CIPHER_ID_DES; - } else { - cipher_id_tmp = MBEDTLS_CIPHER_ID_3DES; - } - /* mbedtls doesn't recognize two-key Triple-DES as an algorithm, - * but two-key Triple-DES is functionally three-key Triple-DES - * with K1=K3, so that's how we present it to mbedtls. */ - if (key_bits == 128) { - key_bits = 192; - } - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA) - case PSA_KEY_TYPE_CAMELLIA: - cipher_id_tmp = MBEDTLS_CIPHER_ID_CAMELLIA; - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20) - case PSA_KEY_TYPE_CHACHA20: - cipher_id_tmp = MBEDTLS_CIPHER_ID_CHACHA20; - break; -#endif - default: - return NULL; - } - if (cipher_id != NULL) { - *cipher_id = cipher_id_tmp; - } - - return mbedtls_cipher_info_from_values(cipher_id_tmp, - (int) key_bits, mode); -#else - (void) alg; - (void) key_type; - (void) key_bits; - (void) cipher_id; - - return NULL; -#endif -} - -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - -static psa_status_t psa_cipher_setup( - mbedtls_psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - mbedtls_operation_t cipher_operation) -{ - int ret = 0; - size_t key_bits; - const mbedtls_cipher_info_t *cipher_info = NULL; - psa_key_type_t key_type = attributes->core.type; - - (void) key_buffer_size; - - mbedtls_cipher_init(&operation->ctx.cipher); - - operation->alg = alg; - key_bits = attributes->core.bits; - cipher_info = mbedtls_cipher_info_from_psa(alg, key_type, - key_bits, NULL); - if (cipher_info == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - ret = mbedtls_cipher_setup(&operation->ctx.cipher, cipher_info); - if (ret != 0) { - goto exit; - } - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) - if (key_type == PSA_KEY_TYPE_DES && key_bits == 128) { - /* Two-key Triple-DES is 3-key Triple-DES with K1=K3 */ - uint8_t keys[24]; - memcpy(keys, key_buffer, 16); - memcpy(keys + 16, key_buffer, 8); - ret = mbedtls_cipher_setkey(&operation->ctx.cipher, - keys, - 192, cipher_operation); - } else -#endif - { - ret = mbedtls_cipher_setkey(&operation->ctx.cipher, key_buffer, - (int) key_bits, cipher_operation); - } - if (ret != 0) { - goto exit; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) - switch (alg) { - case PSA_ALG_CBC_NO_PADDING: - ret = mbedtls_cipher_set_padding_mode(&operation->ctx.cipher, - MBEDTLS_PADDING_NONE); - break; - case PSA_ALG_CBC_PKCS7: - ret = mbedtls_cipher_set_padding_mode(&operation->ctx.cipher, - MBEDTLS_PADDING_PKCS7); - break; - default: - /* The algorithm doesn't involve padding. */ - ret = 0; - break; - } - if (ret != 0) { - goto exit; - } -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING || - MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 */ - - operation->block_length = (PSA_ALG_IS_STREAM_CIPHER(alg) ? 1 : - PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type)); - operation->iv_length = PSA_CIPHER_IV_LENGTH(key_type, alg); - -exit: - return mbedtls_to_psa_error(ret); -} - -psa_status_t mbedtls_psa_cipher_encrypt_setup( - mbedtls_psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg) -{ - return psa_cipher_setup(operation, attributes, - key_buffer, key_buffer_size, - alg, MBEDTLS_ENCRYPT); -} - -psa_status_t mbedtls_psa_cipher_decrypt_setup( - mbedtls_psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg) -{ - return psa_cipher_setup(operation, attributes, - key_buffer, key_buffer_size, - alg, MBEDTLS_DECRYPT); -} - -psa_status_t mbedtls_psa_cipher_set_iv( - mbedtls_psa_cipher_operation_t *operation, - const uint8_t *iv, size_t iv_length) -{ - if (iv_length != operation->iv_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - return mbedtls_to_psa_error( - mbedtls_cipher_set_iv(&operation->ctx.cipher, - iv, iv_length)); -} - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) -/** Process input for which the algorithm is set to ECB mode. - * - * This requires manual processing, since the PSA API is defined as being - * able to process arbitrary-length calls to psa_cipher_update() with ECB mode, - * but the underlying mbedtls_cipher_update only takes full blocks. - * - * \param ctx The mbedtls cipher context to use. It must have been - * set up for ECB. - * \param[in] input The input plaintext or ciphertext to process. - * \param input_length The number of bytes to process from \p input. - * This does not need to be aligned to a block boundary. - * If there is a partial block at the end of the input, - * it is stored in \p ctx for future processing. - * \param output The buffer where the output is written. It must be - * at least `BS * floor((p + input_length) / BS)` bytes - * long, where `p` is the number of bytes in the - * unprocessed partial block in \p ctx (with - * `0 <= p <= BS - 1`) and `BS` is the block size. - * \param output_length On success, the number of bytes written to \p output. - * \c 0 on error. - * - * \return #PSA_SUCCESS or an error from a hardware accelerator - */ -static psa_status_t psa_cipher_update_ecb( - mbedtls_cipher_context_t *ctx, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); - size_t internal_output_length = 0; - *output_length = 0; - - if (input_length == 0) { - status = PSA_SUCCESS; - goto exit; - } - - if (ctx->unprocessed_len > 0) { - /* Fill up to block size, and run the block if there's a full one. */ - size_t bytes_to_copy = block_size - ctx->unprocessed_len; - - if (input_length < bytes_to_copy) { - bytes_to_copy = input_length; - } - - memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), - input, bytes_to_copy); - input_length -= bytes_to_copy; - input += bytes_to_copy; - ctx->unprocessed_len += bytes_to_copy; - - if (ctx->unprocessed_len == block_size) { - status = mbedtls_to_psa_error( - mbedtls_cipher_update(ctx, - ctx->unprocessed_data, - block_size, - output, &internal_output_length)); - - if (status != PSA_SUCCESS) { - goto exit; - } - - output += internal_output_length; - *output_length += internal_output_length; - ctx->unprocessed_len = 0; - } - } - - while (input_length >= block_size) { - /* Run all full blocks we have, one by one */ - status = mbedtls_to_psa_error( - mbedtls_cipher_update(ctx, input, - block_size, - output, &internal_output_length)); - - if (status != PSA_SUCCESS) { - goto exit; - } - - input_length -= block_size; - input += block_size; - - output += internal_output_length; - *output_length += internal_output_length; - } - - if (input_length > 0) { - /* Save unprocessed bytes for later processing */ - memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), - input, input_length); - ctx->unprocessed_len += input_length; - } - - status = PSA_SUCCESS; - -exit: - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING */ - -psa_status_t mbedtls_psa_cipher_update( - mbedtls_psa_cipher_operation_t *operation, - const uint8_t *input, size_t input_length, - uint8_t *output, size_t output_size, size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t expected_output_size; - - if (!PSA_ALG_IS_STREAM_CIPHER(operation->alg)) { - /* Take the unprocessed partial block left over from previous - * update calls, if any, plus the input to this call. Remove - * the last partial block, if any. You get the data that will be - * output in this call. */ - expected_output_size = - (operation->ctx.cipher.unprocessed_len + input_length) - / operation->block_length * operation->block_length; - } else { - expected_output_size = input_length; - } - - if (output_size < expected_output_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) - if (operation->alg == PSA_ALG_ECB_NO_PADDING) { - /* mbedtls_cipher_update has an API inconsistency: it will only - * process a single block at a time in ECB mode. Abstract away that - * inconsistency here to match the PSA API behaviour. */ - status = psa_cipher_update_ecb(&operation->ctx.cipher, - input, - input_length, - output, - output_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING */ - { - status = mbedtls_to_psa_error( - mbedtls_cipher_update(&operation->ctx.cipher, input, - input_length, output, output_length)); - - if (*output_length > output_size) { - return PSA_ERROR_CORRUPTION_DETECTED; - } - } - - return status; -} - -psa_status_t mbedtls_psa_cipher_finish( - mbedtls_psa_cipher_operation_t *operation, - uint8_t *output, size_t output_size, size_t *output_length) -{ - psa_status_t status = PSA_ERROR_GENERIC_ERROR; - uint8_t temp_output_buffer[MBEDTLS_MAX_BLOCK_LENGTH]; - - if (operation->ctx.cipher.unprocessed_len != 0) { - if (operation->alg == PSA_ALG_ECB_NO_PADDING || - operation->alg == PSA_ALG_CBC_NO_PADDING) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - } - - status = mbedtls_to_psa_error( - mbedtls_cipher_finish(&operation->ctx.cipher, - temp_output_buffer, - output_length)); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (*output_length == 0) { - ; /* Nothing to copy. Note that output may be NULL in this case. */ - } else if (output_size >= *output_length) { - memcpy(output, temp_output_buffer, *output_length); - } else { - status = PSA_ERROR_BUFFER_TOO_SMALL; - } - -exit: - mbedtls_platform_zeroize(temp_output_buffer, - sizeof(temp_output_buffer)); - - return status; -} - -psa_status_t mbedtls_psa_cipher_abort( - mbedtls_psa_cipher_operation_t *operation) -{ - /* Sanity check (shouldn't happen: operation->alg should - * always have been initialized to a valid value). */ - if (!PSA_ALG_IS_CIPHER(operation->alg)) { - return PSA_ERROR_BAD_STATE; - } - - mbedtls_cipher_free(&operation->ctx.cipher); - - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_cipher_encrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *iv, - size_t iv_length, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_psa_cipher_operation_t operation = MBEDTLS_PSA_CIPHER_OPERATION_INIT; - size_t update_output_length, finish_output_length; - - status = mbedtls_psa_cipher_encrypt_setup(&operation, attributes, - key_buffer, key_buffer_size, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (iv_length > 0) { - status = mbedtls_psa_cipher_set_iv(&operation, iv, iv_length); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = mbedtls_psa_cipher_update(&operation, input, input_length, - output, output_size, - &update_output_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = mbedtls_psa_cipher_finish( - &operation, - mbedtls_buffer_offset(output, update_output_length), - output_size - update_output_length, &finish_output_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - *output_length = update_output_length + finish_output_length; - -exit: - if (status == PSA_SUCCESS) { - status = mbedtls_psa_cipher_abort(&operation); - } else { - mbedtls_psa_cipher_abort(&operation); - } - - return status; -} - -psa_status_t mbedtls_psa_cipher_decrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_psa_cipher_operation_t operation = MBEDTLS_PSA_CIPHER_OPERATION_INIT; - size_t olength, accumulated_length; - - status = mbedtls_psa_cipher_decrypt_setup(&operation, attributes, - key_buffer, key_buffer_size, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (operation.iv_length > 0) { - status = mbedtls_psa_cipher_set_iv(&operation, - input, operation.iv_length); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = mbedtls_psa_cipher_update( - &operation, - mbedtls_buffer_offset_const(input, operation.iv_length), - input_length - operation.iv_length, - output, output_size, &olength); - if (status != PSA_SUCCESS) { - goto exit; - } - - accumulated_length = olength; - - status = mbedtls_psa_cipher_finish( - &operation, - mbedtls_buffer_offset(output, accumulated_length), - output_size - accumulated_length, &olength); - if (status != PSA_SUCCESS) { - goto exit; - } - - *output_length = accumulated_length + olength; - -exit: - if (status == PSA_SUCCESS) { - status = mbedtls_psa_cipher_abort(&operation); - } else { - mbedtls_psa_cipher_abort(&operation); - } - - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA cipher driver entry points + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include "psa_crypto_cipher.h" +#include "psa_crypto_core.h" +#include "psa_crypto_random_impl.h" + +#include "mbedtls/cipher.h" +#include "mbedtls/error.h" + +#include + +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( + psa_algorithm_t alg, + psa_key_type_t key_type, + size_t key_bits, + mbedtls_cipher_id_t *cipher_id) +{ +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20) + + mbedtls_cipher_mode_t mode; + mbedtls_cipher_id_t cipher_id_tmp; + + if (PSA_ALG_IS_AEAD(alg)) { + alg = PSA_ALG_AEAD_WITH_SHORTENED_TAG(alg, 0); + } + + if (PSA_ALG_IS_CIPHER(alg) || PSA_ALG_IS_AEAD(alg)) { + switch (alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_STREAM_CIPHER) + case PSA_ALG_STREAM_CIPHER: + mode = MBEDTLS_MODE_STREAM; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CTR) + case PSA_ALG_CTR: + mode = MBEDTLS_MODE_CTR; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CFB) + case PSA_ALG_CFB: + mode = MBEDTLS_MODE_CFB; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_OFB) + case PSA_ALG_OFB: + mode = MBEDTLS_MODE_OFB; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) + case PSA_ALG_ECB_NO_PADDING: + mode = MBEDTLS_MODE_ECB; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) + case PSA_ALG_CBC_NO_PADDING: + mode = MBEDTLS_MODE_CBC; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) + case PSA_ALG_CBC_PKCS7: + mode = MBEDTLS_MODE_CBC; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM_STAR_NO_TAG) + case PSA_ALG_CCM_STAR_NO_TAG: + mode = MBEDTLS_MODE_CCM_STAR_NO_TAG; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CCM, 0): + mode = MBEDTLS_MODE_CCM; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_GCM) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_GCM, 0): + mode = MBEDTLS_MODE_GCM; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CHACHA20_POLY1305) + case PSA_ALG_AEAD_WITH_SHORTENED_TAG(PSA_ALG_CHACHA20_POLY1305, 0): + mode = MBEDTLS_MODE_CHACHAPOLY; + break; +#endif + default: + return NULL; + } + } else if (alg == PSA_ALG_CMAC) { + mode = MBEDTLS_MODE_ECB; + } else { + return NULL; + } + + switch (key_type) { +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_AES) + case PSA_KEY_TYPE_AES: + cipher_id_tmp = MBEDTLS_CIPHER_ID_AES; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ARIA) + case PSA_KEY_TYPE_ARIA: + cipher_id_tmp = MBEDTLS_CIPHER_ID_ARIA; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) + case PSA_KEY_TYPE_DES: + /* key_bits is 64 for Single-DES, 128 for two-key Triple-DES, + * and 192 for three-key Triple-DES. */ + if (key_bits == 64) { + cipher_id_tmp = MBEDTLS_CIPHER_ID_DES; + } else { + cipher_id_tmp = MBEDTLS_CIPHER_ID_3DES; + } + /* mbedtls doesn't recognize two-key Triple-DES as an algorithm, + * but two-key Triple-DES is functionally three-key Triple-DES + * with K1=K3, so that's how we present it to mbedtls. */ + if (key_bits == 128) { + key_bits = 192; + } + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CAMELLIA) + case PSA_KEY_TYPE_CAMELLIA: + cipher_id_tmp = MBEDTLS_CIPHER_ID_CAMELLIA; + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_CHACHA20) + case PSA_KEY_TYPE_CHACHA20: + cipher_id_tmp = MBEDTLS_CIPHER_ID_CHACHA20; + break; +#endif + default: + return NULL; + } + if (cipher_id != NULL) { + *cipher_id = cipher_id_tmp; + } + + return mbedtls_cipher_info_from_values(cipher_id_tmp, + (int) key_bits, mode); +#else + (void) alg; + (void) key_type; + (void) key_bits; + (void) cipher_id; + + return NULL; +#endif +} + +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + +static psa_status_t psa_cipher_setup( + mbedtls_psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + mbedtls_operation_t cipher_operation) +{ + int ret = 0; + size_t key_bits; + const mbedtls_cipher_info_t *cipher_info = NULL; + psa_key_type_t key_type = attributes->core.type; + + (void) key_buffer_size; + + mbedtls_cipher_init(&operation->ctx.cipher); + + operation->alg = alg; + key_bits = attributes->core.bits; + cipher_info = mbedtls_cipher_info_from_psa(alg, key_type, + key_bits, NULL); + if (cipher_info == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + ret = mbedtls_cipher_setup(&operation->ctx.cipher, cipher_info); + if (ret != 0) { + goto exit; + } + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DES) + if (key_type == PSA_KEY_TYPE_DES && key_bits == 128) { + /* Two-key Triple-DES is 3-key Triple-DES with K1=K3 */ + uint8_t keys[24]; + memcpy(keys, key_buffer, 16); + memcpy(keys + 16, key_buffer, 8); + ret = mbedtls_cipher_setkey(&operation->ctx.cipher, + keys, + 192, cipher_operation); + } else +#endif + { + ret = mbedtls_cipher_setkey(&operation->ctx.cipher, key_buffer, + (int) key_bits, cipher_operation); + } + if (ret != 0) { + goto exit; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7) + switch (alg) { + case PSA_ALG_CBC_NO_PADDING: + ret = mbedtls_cipher_set_padding_mode(&operation->ctx.cipher, + MBEDTLS_PADDING_NONE); + break; + case PSA_ALG_CBC_PKCS7: + ret = mbedtls_cipher_set_padding_mode(&operation->ctx.cipher, + MBEDTLS_PADDING_PKCS7); + break; + default: + /* The algorithm doesn't involve padding. */ + ret = 0; + break; + } + if (ret != 0) { + goto exit; + } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CBC_NO_PADDING || + MBEDTLS_PSA_BUILTIN_ALG_CBC_PKCS7 */ + + operation->block_length = (PSA_ALG_IS_STREAM_CIPHER(alg) ? 1 : + PSA_BLOCK_CIPHER_BLOCK_LENGTH(key_type)); + operation->iv_length = PSA_CIPHER_IV_LENGTH(key_type, alg); + +exit: + return mbedtls_to_psa_error(ret); +} + +psa_status_t mbedtls_psa_cipher_encrypt_setup( + mbedtls_psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg) +{ + return psa_cipher_setup(operation, attributes, + key_buffer, key_buffer_size, + alg, MBEDTLS_ENCRYPT); +} + +psa_status_t mbedtls_psa_cipher_decrypt_setup( + mbedtls_psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg) +{ + return psa_cipher_setup(operation, attributes, + key_buffer, key_buffer_size, + alg, MBEDTLS_DECRYPT); +} + +psa_status_t mbedtls_psa_cipher_set_iv( + mbedtls_psa_cipher_operation_t *operation, + const uint8_t *iv, size_t iv_length) +{ + if (iv_length != operation->iv_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + return mbedtls_to_psa_error( + mbedtls_cipher_set_iv(&operation->ctx.cipher, + iv, iv_length)); +} + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) +/** Process input for which the algorithm is set to ECB mode. + * + * This requires manual processing, since the PSA API is defined as being + * able to process arbitrary-length calls to psa_cipher_update() with ECB mode, + * but the underlying mbedtls_cipher_update only takes full blocks. + * + * \param ctx The mbedtls cipher context to use. It must have been + * set up for ECB. + * \param[in] input The input plaintext or ciphertext to process. + * \param input_length The number of bytes to process from \p input. + * This does not need to be aligned to a block boundary. + * If there is a partial block at the end of the input, + * it is stored in \p ctx for future processing. + * \param output The buffer where the output is written. It must be + * at least `BS * floor((p + input_length) / BS)` bytes + * long, where `p` is the number of bytes in the + * unprocessed partial block in \p ctx (with + * `0 <= p <= BS - 1`) and `BS` is the block size. + * \param output_length On success, the number of bytes written to \p output. + * \c 0 on error. + * + * \return #PSA_SUCCESS or an error from a hardware accelerator + */ +static psa_status_t psa_cipher_update_ecb( + mbedtls_cipher_context_t *ctx, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t block_size = mbedtls_cipher_info_get_block_size(ctx->cipher_info); + size_t internal_output_length = 0; + *output_length = 0; + + if (input_length == 0) { + status = PSA_SUCCESS; + goto exit; + } + + if (ctx->unprocessed_len > 0) { + /* Fill up to block size, and run the block if there's a full one. */ + size_t bytes_to_copy = block_size - ctx->unprocessed_len; + + if (input_length < bytes_to_copy) { + bytes_to_copy = input_length; + } + + memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), + input, bytes_to_copy); + input_length -= bytes_to_copy; + input += bytes_to_copy; + ctx->unprocessed_len += bytes_to_copy; + + if (ctx->unprocessed_len == block_size) { + status = mbedtls_to_psa_error( + mbedtls_cipher_update(ctx, + ctx->unprocessed_data, + block_size, + output, &internal_output_length)); + + if (status != PSA_SUCCESS) { + goto exit; + } + + output += internal_output_length; + *output_length += internal_output_length; + ctx->unprocessed_len = 0; + } + } + + while (input_length >= block_size) { + /* Run all full blocks we have, one by one */ + status = mbedtls_to_psa_error( + mbedtls_cipher_update(ctx, input, + block_size, + output, &internal_output_length)); + + if (status != PSA_SUCCESS) { + goto exit; + } + + input_length -= block_size; + input += block_size; + + output += internal_output_length; + *output_length += internal_output_length; + } + + if (input_length > 0) { + /* Save unprocessed bytes for later processing */ + memcpy(&(ctx->unprocessed_data[ctx->unprocessed_len]), + input, input_length); + ctx->unprocessed_len += input_length; + } + + status = PSA_SUCCESS; + +exit: + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING */ + +psa_status_t mbedtls_psa_cipher_update( + mbedtls_psa_cipher_operation_t *operation, + const uint8_t *input, size_t input_length, + uint8_t *output, size_t output_size, size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t expected_output_size; + + if (!PSA_ALG_IS_STREAM_CIPHER(operation->alg)) { + /* Take the unprocessed partial block left over from previous + * update calls, if any, plus the input to this call. Remove + * the last partial block, if any. You get the data that will be + * output in this call. */ + expected_output_size = + (operation->ctx.cipher.unprocessed_len + input_length) + / operation->block_length * operation->block_length; + } else { + expected_output_size = input_length; + } + + if (output_size < expected_output_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING) + if (operation->alg == PSA_ALG_ECB_NO_PADDING) { + /* mbedtls_cipher_update has an API inconsistency: it will only + * process a single block at a time in ECB mode. Abstract away that + * inconsistency here to match the PSA API behaviour. */ + status = psa_cipher_update_ecb(&operation->ctx.cipher, + input, + input_length, + output, + output_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECB_NO_PADDING */ + { + status = mbedtls_to_psa_error( + mbedtls_cipher_update(&operation->ctx.cipher, input, + input_length, output, output_length)); + + if (*output_length > output_size) { + return PSA_ERROR_CORRUPTION_DETECTED; + } + } + + return status; +} + +psa_status_t mbedtls_psa_cipher_finish( + mbedtls_psa_cipher_operation_t *operation, + uint8_t *output, size_t output_size, size_t *output_length) +{ + psa_status_t status = PSA_ERROR_GENERIC_ERROR; + uint8_t temp_output_buffer[MBEDTLS_MAX_BLOCK_LENGTH]; + + if (operation->ctx.cipher.unprocessed_len != 0) { + if (operation->alg == PSA_ALG_ECB_NO_PADDING || + operation->alg == PSA_ALG_CBC_NO_PADDING) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + } + + status = mbedtls_to_psa_error( + mbedtls_cipher_finish(&operation->ctx.cipher, + temp_output_buffer, + output_length)); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (*output_length == 0) { + ; /* Nothing to copy. Note that output may be NULL in this case. */ + } else if (output_size >= *output_length) { + memcpy(output, temp_output_buffer, *output_length); + } else { + status = PSA_ERROR_BUFFER_TOO_SMALL; + } + +exit: + mbedtls_platform_zeroize(temp_output_buffer, + sizeof(temp_output_buffer)); + + return status; +} + +psa_status_t mbedtls_psa_cipher_abort( + mbedtls_psa_cipher_operation_t *operation) +{ + /* Sanity check (shouldn't happen: operation->alg should + * always have been initialized to a valid value). */ + if (!PSA_ALG_IS_CIPHER(operation->alg)) { + return PSA_ERROR_BAD_STATE; + } + + mbedtls_cipher_free(&operation->ctx.cipher); + + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_psa_cipher_operation_t operation = MBEDTLS_PSA_CIPHER_OPERATION_INIT; + size_t update_output_length, finish_output_length; + + status = mbedtls_psa_cipher_encrypt_setup(&operation, attributes, + key_buffer, key_buffer_size, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (iv_length > 0) { + status = mbedtls_psa_cipher_set_iv(&operation, iv, iv_length); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = mbedtls_psa_cipher_update(&operation, input, input_length, + output, output_size, + &update_output_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = mbedtls_psa_cipher_finish( + &operation, + mbedtls_buffer_offset(output, update_output_length), + output_size - update_output_length, &finish_output_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + *output_length = update_output_length + finish_output_length; + +exit: + if (status == PSA_SUCCESS) { + status = mbedtls_psa_cipher_abort(&operation); + } else { + mbedtls_psa_cipher_abort(&operation); + } + + return status; +} + +psa_status_t mbedtls_psa_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_psa_cipher_operation_t operation = MBEDTLS_PSA_CIPHER_OPERATION_INIT; + size_t olength, accumulated_length; + + status = mbedtls_psa_cipher_decrypt_setup(&operation, attributes, + key_buffer, key_buffer_size, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (operation.iv_length > 0) { + status = mbedtls_psa_cipher_set_iv(&operation, + input, operation.iv_length); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = mbedtls_psa_cipher_update( + &operation, + mbedtls_buffer_offset_const(input, operation.iv_length), + input_length - operation.iv_length, + output, output_size, &olength); + if (status != PSA_SUCCESS) { + goto exit; + } + + accumulated_length = olength; + + status = mbedtls_psa_cipher_finish( + &operation, + mbedtls_buffer_offset(output, accumulated_length), + output_size - accumulated_length, &olength); + if (status != PSA_SUCCESS) { + goto exit; + } + + *output_length = accumulated_length + olength; + +exit: + if (status == PSA_SUCCESS) { + status = mbedtls_psa_cipher_abort(&operation); + } else { + mbedtls_psa_cipher_abort(&operation); + } + + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.h index bf43ff0..7b8db6e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_cipher.h @@ -1,305 +1,305 @@ -/* - * PSA cipher driver entry points and associated auxiliary functions - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_CIPHER_H -#define PSA_CRYPTO_CIPHER_H - -#include -#include - -/** Get Mbed TLS cipher information given the cipher algorithm PSA identifier - * as well as the PSA type and size of the key to be used with the cipher - * algorithm. - * - * \param alg PSA cipher algorithm identifier - * \param key_type PSA key type - * \param key_bits Size of the key in bits - * \param[out] cipher_id Mbed TLS cipher algorithm identifier - * - * \return The Mbed TLS cipher information of the cipher algorithm. - * \c NULL if the PSA cipher algorithm is not supported. - */ -const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( - psa_algorithm_t alg, psa_key_type_t key_type, size_t key_bits, - mbedtls_cipher_id_t *cipher_id); - -/** - * \brief Set the key for a multipart symmetric encryption operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_encrypt_setup entry point. This function behaves as a - * cipher_encrypt_setup entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation The operation object to set up. It has been - * initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_cipher_encrypt_setup( - mbedtls_psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg); - -/** - * \brief Set the key for a multipart symmetric decryption operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_decrypt_setup entry point. This function behaves as a - * cipher_decrypt_setup entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation The operation object to set up. It has been - * initialized as per the documentation for - * #psa_cipher_operation_t and not yet in use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_cipher_decrypt_setup( - mbedtls_psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg); - -/** Set the IV for a symmetric encryption or decryption operation. - * - * This function sets the IV (initialization vector), nonce - * or initial counter value for the encryption or decryption operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_set_iv entry point. This function behaves as a - * cipher_set_iv entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation Active cipher operation. - * \param[in] iv Buffer containing the IV to use. - * \param[in] iv_length Size of the IV in bytes. It is guaranteed by - * the core to be less or equal to - * PSA_CIPHER_IV_MAX_SIZE. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p iv is not acceptable for the chosen algorithm, - * or the chosen algorithm does not use an IV. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_cipher_set_iv( - mbedtls_psa_cipher_operation_t *operation, - const uint8_t *iv, size_t iv_length); - -/** Encrypt or decrypt a message fragment in an active cipher operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_update entry point. This function behaves as a - * cipher_update entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation Active cipher operation. - * \param[in] input Buffer containing the message fragment to - * encrypt or decrypt. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param[in] output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_cipher_update( - mbedtls_psa_cipher_operation_t *operation, - const uint8_t *input, size_t input_length, - uint8_t *output, size_t output_size, size_t *output_length); - -/** Finish encrypting or decrypting a message in a cipher operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_finish entry point. This function behaves as a - * cipher_finish entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation Active cipher operation. - * \param[out] output Buffer where the output is to be written. - * \param[in] output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The total input size passed to this operation is not valid for - * this particular algorithm. For example, the algorithm is a based - * on block cipher and requires a whole number of blocks, but the - * total input size is not a multiple of the block size. - * \retval #PSA_ERROR_INVALID_PADDING - * This is a decryption operation for an algorithm that includes - * padding, and the ciphertext does not contain valid padding. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_cipher_finish( - mbedtls_psa_cipher_operation_t *operation, - uint8_t *output, size_t output_size, size_t *output_length); - -/** Abort a cipher operation. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation. - * - * \note The signature of this function is that of a PSA driver - * cipher_abort entry point. This function behaves as a - * cipher_abort entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation Initialized cipher operation. - * - * \retval #PSA_SUCCESS \emptydescription - */ -psa_status_t mbedtls_psa_cipher_abort(mbedtls_psa_cipher_operation_t *operation); - -/** Encrypt a message using a symmetric cipher. - * - * \note The signature of this function is that of a PSA driver - * cipher_encrypt entry point. This function behaves as a - * cipher_encrypt entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] iv Buffer containing the IV for encryption. The - * IV has been generated by the core. - * \param[in] iv_length Size of the \p iv in bytes. - * \param[in] input Buffer containing the message to encrypt. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[in,out] output Buffer where the output is to be written. - * \param[in] output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes that make up - * the returned output. Initialized to zero - * by the core. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size \p iv_length is not acceptable for the chosen algorithm, - * or the chosen algorithm does not use an IV. - * The total input size passed to this operation is not valid for - * this particular algorithm. For example, the algorithm is a based - * on block cipher and requires a whole number of blocks, but the - * total input size is not a multiple of the block size. - * \retval #PSA_ERROR_INVALID_PADDING - * This is a decryption operation for an algorithm that includes - * padding, and the ciphertext does not contain valid padding. - */ -psa_status_t mbedtls_psa_cipher_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *iv, - size_t iv_length, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Decrypt a message using a symmetric cipher. - * - * \note The signature of this function is that of a PSA driver - * cipher_decrypt entry point. This function behaves as a - * cipher_decrypt entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg The cipher algorithm to compute - * (\c PSA_ALG_XXX value such that - * #PSA_ALG_IS_CIPHER(\p alg) is true). - * \param[in] input Buffer containing the iv and the ciphertext. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] output Buffer where the output is to be written. - * \param[in] output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes that make up - * the returned output. Initialized to zero - * by the core. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size of \p iv is not acceptable for the chosen algorithm, - * or the chosen algorithm does not use an IV. - * The total input size passed to this operation is not valid for - * this particular algorithm. For example, the algorithm is a based - * on block cipher and requires a whole number of blocks, but the - * total input size is not a multiple of the block size. - * \retval #PSA_ERROR_INVALID_PADDING - * This is a decryption operation for an algorithm that includes - * padding, and the ciphertext does not contain valid padding. - */ -psa_status_t mbedtls_psa_cipher_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -#endif /* PSA_CRYPTO_CIPHER_H */ +/* + * PSA cipher driver entry points and associated auxiliary functions + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_CIPHER_H +#define PSA_CRYPTO_CIPHER_H + +#include +#include + +/** Get Mbed TLS cipher information given the cipher algorithm PSA identifier + * as well as the PSA type and size of the key to be used with the cipher + * algorithm. + * + * \param alg PSA cipher algorithm identifier + * \param key_type PSA key type + * \param key_bits Size of the key in bits + * \param[out] cipher_id Mbed TLS cipher algorithm identifier + * + * \return The Mbed TLS cipher information of the cipher algorithm. + * \c NULL if the PSA cipher algorithm is not supported. + */ +const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( + psa_algorithm_t alg, psa_key_type_t key_type, size_t key_bits, + mbedtls_cipher_id_t *cipher_id); + +/** + * \brief Set the key for a multipart symmetric encryption operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_encrypt_setup entry point. This function behaves as a + * cipher_encrypt_setup entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation The operation object to set up. It has been + * initialized as per the documentation for + * #psa_cipher_operation_t and not yet in use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_cipher_encrypt_setup( + mbedtls_psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg); + +/** + * \brief Set the key for a multipart symmetric decryption operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_decrypt_setup entry point. This function behaves as a + * cipher_decrypt_setup entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation The operation object to set up. It has been + * initialized as per the documentation for + * #psa_cipher_operation_t and not yet in use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_cipher_decrypt_setup( + mbedtls_psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg); + +/** Set the IV for a symmetric encryption or decryption operation. + * + * This function sets the IV (initialization vector), nonce + * or initial counter value for the encryption or decryption operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_set_iv entry point. This function behaves as a + * cipher_set_iv entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation Active cipher operation. + * \param[in] iv Buffer containing the IV to use. + * \param[in] iv_length Size of the IV in bytes. It is guaranteed by + * the core to be less or equal to + * PSA_CIPHER_IV_MAX_SIZE. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size of \p iv is not acceptable for the chosen algorithm, + * or the chosen algorithm does not use an IV. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_cipher_set_iv( + mbedtls_psa_cipher_operation_t *operation, + const uint8_t *iv, size_t iv_length); + +/** Encrypt or decrypt a message fragment in an active cipher operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_update entry point. This function behaves as a + * cipher_update entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation Active cipher operation. + * \param[in] input Buffer containing the message fragment to + * encrypt or decrypt. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * \param[in] output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_cipher_update( + mbedtls_psa_cipher_operation_t *operation, + const uint8_t *input, size_t input_length, + uint8_t *output, size_t output_size, size_t *output_length); + +/** Finish encrypting or decrypting a message in a cipher operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_finish entry point. This function behaves as a + * cipher_finish entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation Active cipher operation. + * \param[out] output Buffer where the output is to be written. + * \param[in] output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The total input size passed to this operation is not valid for + * this particular algorithm. For example, the algorithm is a based + * on block cipher and requires a whole number of blocks, but the + * total input size is not a multiple of the block size. + * \retval #PSA_ERROR_INVALID_PADDING + * This is a decryption operation for an algorithm that includes + * padding, and the ciphertext does not contain valid padding. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_cipher_finish( + mbedtls_psa_cipher_operation_t *operation, + uint8_t *output, size_t output_size, size_t *output_length); + +/** Abort a cipher operation. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation. + * + * \note The signature of this function is that of a PSA driver + * cipher_abort entry point. This function behaves as a + * cipher_abort entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation Initialized cipher operation. + * + * \retval #PSA_SUCCESS \emptydescription + */ +psa_status_t mbedtls_psa_cipher_abort(mbedtls_psa_cipher_operation_t *operation); + +/** Encrypt a message using a symmetric cipher. + * + * \note The signature of this function is that of a PSA driver + * cipher_encrypt entry point. This function behaves as a + * cipher_encrypt entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] iv Buffer containing the IV for encryption. The + * IV has been generated by the core. + * \param[in] iv_length Size of the \p iv in bytes. + * \param[in] input Buffer containing the message to encrypt. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[in,out] output Buffer where the output is to be written. + * \param[in] output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes that make up + * the returned output. Initialized to zero + * by the core. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size \p iv_length is not acceptable for the chosen algorithm, + * or the chosen algorithm does not use an IV. + * The total input size passed to this operation is not valid for + * this particular algorithm. For example, the algorithm is a based + * on block cipher and requires a whole number of blocks, but the + * total input size is not a multiple of the block size. + * \retval #PSA_ERROR_INVALID_PADDING + * This is a decryption operation for an algorithm that includes + * padding, and the ciphertext does not contain valid padding. + */ +psa_status_t mbedtls_psa_cipher_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Decrypt a message using a symmetric cipher. + * + * \note The signature of this function is that of a PSA driver + * cipher_decrypt entry point. This function behaves as a + * cipher_decrypt entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg The cipher algorithm to compute + * (\c PSA_ALG_XXX value such that + * #PSA_ALG_IS_CIPHER(\p alg) is true). + * \param[in] input Buffer containing the iv and the ciphertext. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[out] output Buffer where the output is to be written. + * \param[in] output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes that make up + * the returned output. Initialized to zero + * by the core. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size of \p iv is not acceptable for the chosen algorithm, + * or the chosen algorithm does not use an IV. + * The total input size passed to this operation is not valid for + * this particular algorithm. For example, the algorithm is a based + * on block cipher and requires a whole number of blocks, but the + * total input size is not a multiple of the block size. + * \retval #PSA_ERROR_INVALID_PADDING + * This is a decryption operation for an algorithm that includes + * padding, and the ciphertext does not contain valid padding. + */ +psa_status_t mbedtls_psa_cipher_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#endif /* PSA_CRYPTO_CIPHER_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_client.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_client.c index c323427..c187ecc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_client.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_client.c @@ -1,79 +1,79 @@ -/* - * PSA crypto client code - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" -#include "psa/crypto.h" - -#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) - -#include -#include "mbedtls/platform.h" - -void psa_reset_key_attributes(psa_key_attributes_t *attributes) -{ - mbedtls_free(attributes->domain_parameters); - memset(attributes, 0, sizeof(*attributes)); -} - -psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, - psa_key_type_t type, - const uint8_t *data, - size_t data_length) -{ - uint8_t *copy = NULL; - - if (data_length != 0) { - copy = mbedtls_calloc(1, data_length); - if (copy == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memcpy(copy, data, data_length); - } - /* After this point, this function is guaranteed to succeed, so it - * can start modifying `*attributes`. */ - - if (attributes->domain_parameters != NULL) { - mbedtls_free(attributes->domain_parameters); - attributes->domain_parameters = NULL; - attributes->domain_parameters_size = 0; - } - - attributes->domain_parameters = copy; - attributes->domain_parameters_size = data_length; - attributes->core.type = type; - return PSA_SUCCESS; -} - -psa_status_t psa_get_key_domain_parameters( - const psa_key_attributes_t *attributes, - uint8_t *data, size_t data_size, size_t *data_length) -{ - if (attributes->domain_parameters_size > data_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - *data_length = attributes->domain_parameters_size; - if (attributes->domain_parameters_size != 0) { - memcpy(data, attributes->domain_parameters, - attributes->domain_parameters_size); - } - return PSA_SUCCESS; -} - -#endif /* MBEDTLS_PSA_CRYPTO_CLIENT */ +/* + * PSA crypto client code + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" +#include "psa/crypto.h" + +#if defined(MBEDTLS_PSA_CRYPTO_CLIENT) + +#include +#include "mbedtls/platform.h" + +void psa_reset_key_attributes(psa_key_attributes_t *attributes) +{ + mbedtls_free(attributes->domain_parameters); + memset(attributes, 0, sizeof(*attributes)); +} + +psa_status_t psa_set_key_domain_parameters(psa_key_attributes_t *attributes, + psa_key_type_t type, + const uint8_t *data, + size_t data_length) +{ + uint8_t *copy = NULL; + + if (data_length != 0) { + copy = mbedtls_calloc(1, data_length); + if (copy == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memcpy(copy, data, data_length); + } + /* After this point, this function is guaranteed to succeed, so it + * can start modifying `*attributes`. */ + + if (attributes->domain_parameters != NULL) { + mbedtls_free(attributes->domain_parameters); + attributes->domain_parameters = NULL; + attributes->domain_parameters_size = 0; + } + + attributes->domain_parameters = copy; + attributes->domain_parameters_size = data_length; + attributes->core.type = type; + return PSA_SUCCESS; +} + +psa_status_t psa_get_key_domain_parameters( + const psa_key_attributes_t *attributes, + uint8_t *data, size_t data_size, size_t *data_length) +{ + if (attributes->domain_parameters_size > data_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + *data_length = attributes->domain_parameters_size; + if (attributes->domain_parameters_size != 0) { + memcpy(data, attributes->domain_parameters, + attributes->domain_parameters_size); + } + return PSA_SUCCESS; +} + +#endif /* MBEDTLS_PSA_CRYPTO_CLIENT */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core.h index 24259fa..5fa48c3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core.h @@ -1,893 +1,893 @@ -/* - * PSA crypto core internal interfaces - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_CORE_H -#define PSA_CRYPTO_CORE_H - -#include "mbedtls/build_info.h" - -#include "psa/crypto.h" -#include "psa/crypto_se_driver.h" - -/** - * Tell if PSA is ready for this hash. - * - * \note For now, only checks the state of the driver subsystem, - * not the algorithm. Might do more in the future. - * - * \param hash_alg The hash algorithm (ignored for now). - * - * \return 1 if the driver subsytem is ready, 0 otherwise. - */ -int psa_can_do_hash(psa_algorithm_t hash_alg); - -typedef enum -{ - PSA_STATE_EMPTY, /* No key loaded yet. */ - PSA_STATE_CREATING, /* Key creation has been started. */ - PSA_STATE_UNUSED, /* Key present, but unused. */ - PSA_STATE_READING, /* Key material used in an operation. */ - PSA_STATE_WIPING, /* Purging key data from memory in progress. */ - PSA_STATE_DESTROYING /* Persistent and volatile key material destruction in progress. */ -} psa_key_slot_state_t; - -/** Intention behind locking a key slot */ -typedef enum -{ - PSA_INTENT_READ, - PSA_INTENT_DESTROY, - PSA_INTENT_OPEN /* Only used by psa_open_key, to be deprecated */ -} psa_slot_locking_intent_t; - -/** The data structure representing a key slot, containing key material - * and metadata for one key. - */ -typedef struct { - psa_core_key_attributes_t attr; - - /* - * Number of active readers of the key slot. - * - * This counter is incremented by one each time a library function - * retrieves through one of the dedicated internal API a pointer to the - * key slot. - * - * This counter is decremented by one each time a library function stops - * accessing the key slot and states it by calling the - * psa_unlock_key_slot() API. - * - * This counter is used to prevent resetting the key slot while the library - * may access it. For example, such control is needed in the following - * scenarios: - * . In case of key slot starvation, all key slots contain the description - * of a key, and the library asks for the description of a persistent - * key not present in the key slots, the key slots currently accessed by - * the library cannot be reclaimed to free a key slot to load the - * persistent key. - * . In case of a multi-threaded application where one thread asks to close - * or purge or destroy a key while it is in used by the library through - * another thread. - */ - size_t reader_count; - - psa_key_slot_state_t state; - - /* Dynamically allocated key data buffer. - * Format as specified in psa_export_key(). */ - struct key_data { - uint8_t *data; - size_t bytes; - } key; -} psa_key_slot_t; - -/* A mask of key attribute flags used only internally. - * Currently there aren't any. */ -#define PSA_KA_MASK_INTERNAL_ONLY ( \ - 0) - -/** Retrieve flags from psa_key_slot_t::attr::core::flags. - * - * \param[in] slot The key slot to query. - * \param mask The mask of bits to extract. - * - * \return The key attribute flags in the given slot, - * bitwise-anded with \p mask. - */ -static inline uint16_t psa_key_slot_get_flags(const psa_key_slot_t *slot, - uint16_t mask) -{ - return slot->attr.MBEDTLS_PRIVATE(flags) & mask; -} - -/** Set flags in psa_key_slot_t::attr::core::flags. - * - * \param[in,out] slot The key slot to modify. - * \param mask The mask of bits to modify. - * \param value The new value of the selected bits. - */ -static inline void psa_key_slot_set_flags(psa_key_slot_t *slot, - uint16_t mask, - uint16_t value) -{ - slot->attr.MBEDTLS_PRIVATE(flags) = ((~mask & slot->attr.MBEDTLS_PRIVATE(flags)) | - (mask & value)); -} - -/** Turn on flags in psa_key_slot_t::attr::core::flags. - * - * \param[in,out] slot The key slot to modify. - * \param mask The mask of bits to set. - */ -static inline void psa_key_slot_set_bits_in_flags(psa_key_slot_t *slot, - uint16_t mask) -{ - slot->attr.MBEDTLS_PRIVATE(flags) |= mask; -} - -/** Turn off flags in psa_key_slot_t::attr::core::flags. - * - * \param[in,out] slot The key slot to modify. - * \param mask The mask of bits to clear. - */ -static inline void psa_key_slot_clear_bits(psa_key_slot_t *slot, - uint16_t mask) -{ - slot->attr.MBEDTLS_PRIVATE(flags) &= ~mask; -} - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/** Get the SE slot number of a key from the key slot storing its description. - * - * \param[in] slot The key slot to query. This must be a key slot storing - * the description of a key of a dynamically registered - * secure element, otherwise the behaviour is undefined. - */ -static inline psa_key_slot_number_t psa_key_slot_get_slot_number( - const psa_key_slot_t *slot) -{ - return *((psa_key_slot_number_t *) (slot->key.data)); -} -#endif - -/** Completely wipe a slot in memory, including its policy. - * - * Persistent storage is not affected. - * - * Please note that, if MBEDTLS_THREADING_C is enabled, this function should - * be called with locked mbedtls_psa_slots_mutex. - * - * \param[in,out] slot The key slot to wipe. - * - * \retval #PSA_SUCCESS - * Success. This includes the case of a key slot that was - * already fully wiped. - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t psa_wipe_key_slot(psa_key_slot_t *slot); - -/** Perform key destruction in both volatile and persistent memory. - * - * See psa_destroy_key for information on return errors. - * - * Please note that, if MBEDTLS_THREADING_C is enabled, this function should - * be called with locked mbedtls_psa_slots_mutex. - * - * \param[in,out] slot The key slot to wipe. - */ -psa_status_t psa_finish_key_destruction( psa_key_slot_t *slot ); - -/** Try to allocate a buffer to an empty key slot. - * - * \param[in,out] slot Key slot to attach buffer to. - * \param[in] buffer_length Requested size of the buffer. - * - * \retval #PSA_SUCCESS - * The buffer has been successfully allocated. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * Not enough memory was available for allocation. - * \retval #PSA_ERROR_ALREADY_EXISTS - * Trying to allocate a buffer to a non-empty key slot. - */ -psa_status_t psa_allocate_buffer_to_slot(psa_key_slot_t *slot, - size_t buffer_length); - -/** Wipe key data from a slot. Preserves metadata such as the policy. */ -psa_status_t psa_remove_key_data_from_memory(psa_key_slot_t *slot); - -/** Copy key data (in export format) into an empty key slot. - * - * This function assumes that the slot does not contain - * any key material yet. On failure, the slot content is unchanged. - * - * \param[in,out] slot Key slot to copy the key into. - * \param[in] data Buffer containing the key material. - * \param data_length Size of the key buffer. - * - * \retval #PSA_SUCCESS - * The key has been copied successfully. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * Not enough memory was available for allocation of the - * copy buffer. - * \retval #PSA_ERROR_ALREADY_EXISTS - * There was other key material already present in the slot. - */ -psa_status_t psa_copy_key_material_into_slot(psa_key_slot_t *slot, - const uint8_t *data, - size_t data_length); - -/** Convert an Mbed TLS error code to a PSA error code - * - * \note This function is provided solely for the convenience of - * Mbed TLS and may be removed at any time without notice. - * - * \param ret An Mbed TLS-thrown error code - * - * \return The corresponding PSA error code - */ -psa_status_t mbedtls_to_psa_error(int ret); - -/** Import a key in binary format. - * - * \note The signature of this function is that of a PSA driver - * import_key entry point. This function behaves as an import_key - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes for the key to import. - * \param[in] data The buffer containing the key data in import - * format. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] key_buffer The buffer to contain the key data in output - * format upon successful return. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This - * size is greater or equal to \p data_length. - * \param[out] key_buffer_length The length of the data written in \p - * key_buffer in bytes. - * \param[out] bits The key size in number of bits. - * - * \retval #PSA_SUCCESS The key was imported successfully. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key data is not correctly formatted. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t psa_import_key_into_slot( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits); - -/** Export a key in binary format - * - * \note The signature of this function is that of a PSA driver export_key - * entry point. This function behaves as an export_key entry point as - * defined in the PSA driver interface specification. - * - * \param[in] attributes The attributes for the key to export. - * \param[in] key_buffer Material or context of the key to export. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[out] data Buffer where the key data is to be written. - * \param[in] data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes written in - * \p data - * - * \retval #PSA_SUCCESS The key was exported successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t psa_export_key_internal( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length); - -/** Export a public key or the public part of a key pair in binary format. - * - * \note The signature of this function is that of a PSA driver - * export_public_key entry point. This function behaves as an - * export_public_key entry point as defined in the PSA driver interface - * specification. - * - * \param[in] attributes The attributes for the key to export. - * \param[in] key_buffer Material or context of the key to export. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[out] data Buffer where the key data is to be written. - * \param[in] data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes written in - * \p data - * - * \retval #PSA_SUCCESS The public key was exported successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t psa_export_public_key_internal( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length); - -/** - * \brief Generate a key. - * - * \note The signature of the function is that of a PSA driver generate_key - * entry point. - * - * \param[in] attributes The attributes for the key to generate. - * \param[out] key_buffer Buffer where the key data is to be written. - * \param[in] key_buffer_size Size of \p key_buffer in bytes. - * \param[out] key_buffer_length On success, the number of bytes written in - * \p key_buffer. - * - * \retval #PSA_SUCCESS - * The key was generated successfully. - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED - * Key size in bits or type not supported. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - */ -psa_status_t psa_generate_key_internal(const psa_key_attributes_t *attributes, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_buffer_length); - -/** Sign a message with a private key. For hash-and-sign algorithms, - * this includes the hashing step. - * - * \note The signature of this function is that of a PSA driver - * sign_message entry point. This function behaves as a sign_message - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \note This function will call the driver for psa_sign_hash - * and go through driver dispatch again. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] input The input message to sign. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of the key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - */ -psa_status_t psa_sign_message_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *input, size_t input_length, - uint8_t *signature, size_t signature_size, size_t *signature_length); - -/** Verify the signature of a message with a public key, using - * a hash-and-sign verification algorithm. - * - * \note The signature of this function is that of a PSA driver - * verify_message entry point. This function behaves as a verify_message - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \note This function will call the driver for psa_verify_hash - * and go through driver dispatch again. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] input The message whose signature is to be verified. - * \param[in] input_length Size of the \p input buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t psa_verify_message_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *input, size_t input_length, - const uint8_t *signature, size_t signature_length); - -/** Sign an already-calculated hash with a private key. - * - * \note The signature of this function is that of a PSA driver - * sign_hash entry point. This function behaves as a sign_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] hash The hash or message to sign. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of the key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - */ -psa_status_t psa_sign_hash_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length); - -/** - * \brief Verify the signature a hash or short message using a public key. - * - * \note The signature of this function is that of a PSA driver - * verify_hash entry point. This function behaves as a verify_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] hash The hash or message whose signature is to be - * verified. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t psa_verify_hash_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - -/** - * \brief Validate the key bit size for unstructured keys. - * - * \note Check that the bit size is acceptable for a given key type for - * unstructured keys. - * - * \param[in] type The key type - * \param[in] bits The number of bits of the key - * - * \retval #PSA_SUCCESS - * The key type and size are valid. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The size in bits of the key is not valid. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The type and/or the size in bits of the key or the combination of - * the two is not supported. - */ -psa_status_t psa_validate_unstructured_key_bit_size(psa_key_type_t type, - size_t bits); - -/** Perform a key agreement and return the raw shared secret, using - built-in raw key agreement functions. - * - * \note The signature of this function is that of a PSA driver - * key_agreement entry point. This function behaves as a key_agreement - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the private key - * context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in - * bytes. - * \param[in] alg A key agreement algorithm that is - * compatible with the type of the key. - * \param[in] peer_key The buffer containing the key context - * of the peer's public key. - * \param[in] peer_key_length Size of the \p peer_key buffer in - * bytes. - * \param[out] shared_secret The buffer to which the shared secret - * is to be written. - * \param[in] shared_secret_size Size of the \p shared_secret buffer in - * bytes. - * \param[out] shared_secret_length On success, the number of bytes that make - * up the returned shared secret. - * \retval #PSA_SUCCESS - * Success. Shared secret successfully calculated. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a key agreement algorithm, or - * \p private_key is not compatible with \p alg, - * or \p peer_key is not valid for \p alg or not compatible with - * \p private_key. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p shared_secret_size is too small - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported key agreement algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_BAD_STATE \emptydescription - */ -psa_status_t psa_key_agreement_raw_builtin( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length); - -/** - * \brief Set the maximum number of ops allowed to be executed by an - * interruptible function in a single call. - * - * \note The signature of this function is that of a PSA driver - * interruptible_set_max_ops entry point. This function behaves as an - * interruptible_set_max_ops entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in] max_ops The maximum number of ops to be executed in a - * single call, this can be a number from 0 to - * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, where 0 - * is obviously the least amount of work done per - * call. - */ -void mbedtls_psa_interruptible_set_max_ops(uint32_t max_ops); - -/** - * \brief Get the maximum number of ops allowed to be executed by an - * interruptible function in a single call. - * - * \note The signature of this function is that of a PSA driver - * interruptible_get_max_ops entry point. This function behaves as an - * interruptible_get_max_ops entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \return Maximum number of ops allowed to be executed - * by an interruptible function in a single call. - */ -uint32_t mbedtls_psa_interruptible_get_max_ops(void); - -/** - * \brief Get the number of ops that a hash signing operation has taken for the - * previous call. If no call or work has taken place, this will return - * zero. - * - * \note The signature of this function is that of a PSA driver - * sign_hash_get_num_ops entry point. This function behaves as an - * sign_hash_get_num_ops entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param operation The \c - * mbedtls_psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \return Number of ops that were completed - * in the last call to \c - * mbedtls_psa_sign_hash_complete(). - */ -uint32_t mbedtls_psa_sign_hash_get_num_ops( - const mbedtls_psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Get the number of ops that a hash verification operation has taken for - * the previous call. If no call or work has taken place, this will - * return zero. - * - * \note The signature of this function is that of a PSA driver - * verify_hash_get_num_ops entry point. This function behaves as an - * verify_hash_get_num_ops entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param operation The \c - * mbedtls_psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \return Number of ops that were completed - * in the last call to \c - * mbedtls_psa_verify_hash_complete(). - */ -uint32_t mbedtls_psa_verify_hash_get_num_ops( - const mbedtls_psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Start signing a hash or short message with a private key, in an - * interruptible manner. - * - * \note The signature of this function is that of a PSA driver - * sign_hash_start entry point. This function behaves as a - * sign_hash_start entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * \param[in] operation The \c - * mbedtls_psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] hash The hash or message to sign. - * \param hash_length Size of the \p hash buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - call \c psa_sign_hash_complete() - * with the same context to complete the operation - * \retval #PSA_ERROR_INVALID_ARGUMENT - * An unsupported, incorrectly formatted or incorrect type of key was - * used. - * \retval #PSA_ERROR_NOT_SUPPORTED Either no internal interruptible operations - * are currently supported, or the key type is currently unsupported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * There was insufficient memory to load the key representation. - */ -psa_status_t mbedtls_psa_sign_hash_start( - mbedtls_psa_sign_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length); - -/** - * \brief Continue and eventually complete the action of signing a hash or - * short message with a private key, in an interruptible manner. - * - * \note The signature of this function is that of a PSA driver - * sign_hash_complete entry point. This function behaves as a - * sign_hash_complete entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * \param[in] operation The \c - * mbedtls_psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \param[out] signature Buffer where the signature is to be written. - * \param signature_size Size of the \p signature buffer in bytes. This - * must be appropriate for the selected - * algorithm and key. - * \param[out] signature_length On success, the number of bytes that make up - * the returned signature value. - * - * \retval #PSA_SUCCESS - * Operation completed successfully - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(), there is still work to be done, - * please call this function again with the same operation object. - * - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - */ -psa_status_t mbedtls_psa_sign_hash_complete( - mbedtls_psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length); - -/** - * \brief Abort a sign hash operation. - * - * \note The signature of this function is that of a PSA driver sign_hash_abort - * entry point. This function behaves as a sign_hash_abort entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * \param[in] operation The \c - * mbedtls_psa_sign_hash_interruptible_operation_t - * to abort. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - */ -psa_status_t mbedtls_psa_sign_hash_abort( - mbedtls_psa_sign_hash_interruptible_operation_t *operation); - -/** - * \brief Start reading and verifying a hash or short message, in an - * interruptible manner. - * - * \note The signature of this function is that of a PSA driver - * verify_hash_start entry point. This function behaves as a - * verify_hash_start entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * \param[in] operation The \c - * mbedtls_psa_verify_hash_interruptible_operation_t - * to use. This must be initialized first. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * the type of the key. - * \param[in] hash The hash whose signature is to be verified. - * \param hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The operation started successfully - call \c psa_sign_hash_complete() - * with the same context to complete the operation - * \retval #PSA_ERROR_INVALID_ARGUMENT - * An unsupported or incorrect type of key was used. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Either no internal interruptible operations are currently supported, - * or the key type is currently unsupported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * There was insufficient memory either to load the key representation, - * or to prepare the operation. - */ -psa_status_t mbedtls_psa_verify_hash_start( - mbedtls_psa_verify_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - -/** - * \brief Continue and eventually complete the action of signing a hash or - * short message with a private key, in an interruptible manner. - * - * \note The signature of this function is that of a PSA driver - * sign_hash_complete entry point. This function behaves as a - * sign_hash_complete entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * \param[in] operation The \c - * mbedtls_psa_sign_hash_interruptible_operation_t - * to use. This must be initialized first. - * - * \retval #PSA_SUCCESS - * Operation completed successfully, and the passed signature is valid. - * - * \retval #PSA_OPERATION_INCOMPLETE - * Operation was interrupted due to the setting of \c - * psa_interruptible_set_max_ops(), there is still work to be done, - * please call this function again with the same operation object. - * - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_verify_hash_complete( - mbedtls_psa_verify_hash_interruptible_operation_t *operation); - -/** - * \brief Abort a verify signed hash operation. - * - * \note The signature of this function is that of a PSA driver - * verify_hash_abort entry point. This function behaves as a - * verify_hash_abort entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * \param[in] operation The \c - * mbedtls_psa_verify_hash_interruptible_operation_t - * to abort. - * - * \retval #PSA_SUCCESS - * The operation was aborted successfully. - */ -psa_status_t mbedtls_psa_verify_hash_abort( - mbedtls_psa_verify_hash_interruptible_operation_t *operation); - -/** Test whether the number of readers of this lock is equal to 0. - * - * \param[in] slot The key slot to test. - * \retval 0 - * The key slot has at least one active reader. - * \retval 1 - * The key slot has no active readers. - */ -int psa_slot_has_no_readers( psa_key_slot_t *slot ); - -/** Transition the slot to a given state - * - * \param[in] slot The key slot. - * \param[in] target_state The desired slot state. - * - * Please note that, if MBEDTLS_THREADING_C is enabled, this function should - * be called with locked mbedtls_psa_slots_mutex. - * - * \retval #PSA_ERROR_INVALID_HANDLE - * \p slot is empty and a bad state change was requested. - * \retval #PSA_ERROR_BAD_STATE - * The requested state transition could not be performed. - * \retval #PSA_SUCCESS - * The transition succeeded and \p slot is now in \p target_state. - */ -psa_status_t psa_slot_change_state( psa_key_slot_t *slot, - psa_key_slot_state_t target_state ); - -#if defined(MBEDTLS_TEST_HOOKS) -/** - * \brief Get a key slot from global data. Used in tests to check slot state - * without locking it. - */ -psa_key_slot_t* mbedtls_psa_get_key_slot( uint32_t num ); -#endif - -#endif /* PSA_CRYPTO_CORE_H */ +/* + * PSA crypto core internal interfaces + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_CORE_H +#define PSA_CRYPTO_CORE_H + +#include "mbedtls/build_info.h" + +#include "psa/crypto.h" +#include "psa/crypto_se_driver.h" + +/** + * Tell if PSA is ready for this hash. + * + * \note For now, only checks the state of the driver subsystem, + * not the algorithm. Might do more in the future. + * + * \param hash_alg The hash algorithm (ignored for now). + * + * \return 1 if the driver subsytem is ready, 0 otherwise. + */ +int psa_can_do_hash(psa_algorithm_t hash_alg); + +typedef enum +{ + PSA_STATE_EMPTY, /* No key loaded yet. */ + PSA_STATE_CREATING, /* Key creation has been started. */ + PSA_STATE_UNUSED, /* Key present, but unused. */ + PSA_STATE_READING, /* Key material used in an operation. */ + PSA_STATE_WIPING, /* Purging key data from memory in progress. */ + PSA_STATE_DESTROYING /* Persistent and volatile key material destruction in progress. */ +} psa_key_slot_state_t; + +/** Intention behind locking a key slot */ +typedef enum +{ + PSA_INTENT_READ, + PSA_INTENT_DESTROY, + PSA_INTENT_OPEN /* Only used by psa_open_key, to be deprecated */ +} psa_slot_locking_intent_t; + +/** The data structure representing a key slot, containing key material + * and metadata for one key. + */ +typedef struct { + psa_core_key_attributes_t attr; + + /* + * Number of active readers of the key slot. + * + * This counter is incremented by one each time a library function + * retrieves through one of the dedicated internal API a pointer to the + * key slot. + * + * This counter is decremented by one each time a library function stops + * accessing the key slot and states it by calling the + * psa_unlock_key_slot() API. + * + * This counter is used to prevent resetting the key slot while the library + * may access it. For example, such control is needed in the following + * scenarios: + * . In case of key slot starvation, all key slots contain the description + * of a key, and the library asks for the description of a persistent + * key not present in the key slots, the key slots currently accessed by + * the library cannot be reclaimed to free a key slot to load the + * persistent key. + * . In case of a multi-threaded application where one thread asks to close + * or purge or destroy a key while it is in used by the library through + * another thread. + */ + size_t reader_count; + + psa_key_slot_state_t state; + + /* Dynamically allocated key data buffer. + * Format as specified in psa_export_key(). */ + struct key_data { + uint8_t *data; + size_t bytes; + } key; +} psa_key_slot_t; + +/* A mask of key attribute flags used only internally. + * Currently there aren't any. */ +#define PSA_KA_MASK_INTERNAL_ONLY ( \ + 0) + +/** Retrieve flags from psa_key_slot_t::attr::core::flags. + * + * \param[in] slot The key slot to query. + * \param mask The mask of bits to extract. + * + * \return The key attribute flags in the given slot, + * bitwise-anded with \p mask. + */ +static inline uint16_t psa_key_slot_get_flags(const psa_key_slot_t *slot, + uint16_t mask) +{ + return slot->attr.MBEDTLS_PRIVATE(flags) & mask; +} + +/** Set flags in psa_key_slot_t::attr::core::flags. + * + * \param[in,out] slot The key slot to modify. + * \param mask The mask of bits to modify. + * \param value The new value of the selected bits. + */ +static inline void psa_key_slot_set_flags(psa_key_slot_t *slot, + uint16_t mask, + uint16_t value) +{ + slot->attr.MBEDTLS_PRIVATE(flags) = ((~mask & slot->attr.MBEDTLS_PRIVATE(flags)) | + (mask & value)); +} + +/** Turn on flags in psa_key_slot_t::attr::core::flags. + * + * \param[in,out] slot The key slot to modify. + * \param mask The mask of bits to set. + */ +static inline void psa_key_slot_set_bits_in_flags(psa_key_slot_t *slot, + uint16_t mask) +{ + slot->attr.MBEDTLS_PRIVATE(flags) |= mask; +} + +/** Turn off flags in psa_key_slot_t::attr::core::flags. + * + * \param[in,out] slot The key slot to modify. + * \param mask The mask of bits to clear. + */ +static inline void psa_key_slot_clear_bits(psa_key_slot_t *slot, + uint16_t mask) +{ + slot->attr.MBEDTLS_PRIVATE(flags) &= ~mask; +} + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/** Get the SE slot number of a key from the key slot storing its description. + * + * \param[in] slot The key slot to query. This must be a key slot storing + * the description of a key of a dynamically registered + * secure element, otherwise the behaviour is undefined. + */ +static inline psa_key_slot_number_t psa_key_slot_get_slot_number( + const psa_key_slot_t *slot) +{ + return *((psa_key_slot_number_t *) (slot->key.data)); +} +#endif + +/** Completely wipe a slot in memory, including its policy. + * + * Persistent storage is not affected. + * + * Please note that, if MBEDTLS_THREADING_C is enabled, this function should + * be called with locked mbedtls_psa_slots_mutex. + * + * \param[in,out] slot The key slot to wipe. + * + * \retval #PSA_SUCCESS + * Success. This includes the case of a key slot that was + * already fully wiped. + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t psa_wipe_key_slot(psa_key_slot_t *slot); + +/** Perform key destruction in both volatile and persistent memory. + * + * See psa_destroy_key for information on return errors. + * + * Please note that, if MBEDTLS_THREADING_C is enabled, this function should + * be called with locked mbedtls_psa_slots_mutex. + * + * \param[in,out] slot The key slot to wipe. + */ +psa_status_t psa_finish_key_destruction( psa_key_slot_t *slot ); + +/** Try to allocate a buffer to an empty key slot. + * + * \param[in,out] slot Key slot to attach buffer to. + * \param[in] buffer_length Requested size of the buffer. + * + * \retval #PSA_SUCCESS + * The buffer has been successfully allocated. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * Not enough memory was available for allocation. + * \retval #PSA_ERROR_ALREADY_EXISTS + * Trying to allocate a buffer to a non-empty key slot. + */ +psa_status_t psa_allocate_buffer_to_slot(psa_key_slot_t *slot, + size_t buffer_length); + +/** Wipe key data from a slot. Preserves metadata such as the policy. */ +psa_status_t psa_remove_key_data_from_memory(psa_key_slot_t *slot); + +/** Copy key data (in export format) into an empty key slot. + * + * This function assumes that the slot does not contain + * any key material yet. On failure, the slot content is unchanged. + * + * \param[in,out] slot Key slot to copy the key into. + * \param[in] data Buffer containing the key material. + * \param data_length Size of the key buffer. + * + * \retval #PSA_SUCCESS + * The key has been copied successfully. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * Not enough memory was available for allocation of the + * copy buffer. + * \retval #PSA_ERROR_ALREADY_EXISTS + * There was other key material already present in the slot. + */ +psa_status_t psa_copy_key_material_into_slot(psa_key_slot_t *slot, + const uint8_t *data, + size_t data_length); + +/** Convert an Mbed TLS error code to a PSA error code + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param ret An Mbed TLS-thrown error code + * + * \return The corresponding PSA error code + */ +psa_status_t mbedtls_to_psa_error(int ret); + +/** Import a key in binary format. + * + * \note The signature of this function is that of a PSA driver + * import_key entry point. This function behaves as an import_key + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes for the key to import. + * \param[in] data The buffer containing the key data in import + * format. + * \param[in] data_length Size of the \p data buffer in bytes. + * \param[out] key_buffer The buffer to contain the key data in output + * format upon successful return. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This + * size is greater or equal to \p data_length. + * \param[out] key_buffer_length The length of the data written in \p + * key_buffer in bytes. + * \param[out] bits The key size in number of bits. + * + * \retval #PSA_SUCCESS The key was imported successfully. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key data is not correctly formatted. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t psa_import_key_into_slot( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits); + +/** Export a key in binary format + * + * \note The signature of this function is that of a PSA driver export_key + * entry point. This function behaves as an export_key entry point as + * defined in the PSA driver interface specification. + * + * \param[in] attributes The attributes for the key to export. + * \param[in] key_buffer Material or context of the key to export. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[out] data Buffer where the key data is to be written. + * \param[in] data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes written in + * \p data + * + * \retval #PSA_SUCCESS The key was exported successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t psa_export_key_internal( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length); + +/** Export a public key or the public part of a key pair in binary format. + * + * \note The signature of this function is that of a PSA driver + * export_public_key entry point. This function behaves as an + * export_public_key entry point as defined in the PSA driver interface + * specification. + * + * \param[in] attributes The attributes for the key to export. + * \param[in] key_buffer Material or context of the key to export. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[out] data Buffer where the key data is to be written. + * \param[in] data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes written in + * \p data + * + * \retval #PSA_SUCCESS The public key was exported successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t psa_export_public_key_internal( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length); + +/** + * \brief Generate a key. + * + * \note The signature of the function is that of a PSA driver generate_key + * entry point. + * + * \param[in] attributes The attributes for the key to generate. + * \param[out] key_buffer Buffer where the key data is to be written. + * \param[in] key_buffer_size Size of \p key_buffer in bytes. + * \param[out] key_buffer_length On success, the number of bytes written in + * \p key_buffer. + * + * \retval #PSA_SUCCESS + * The key was generated successfully. + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED + * Key size in bits or type not supported. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + */ +psa_status_t psa_generate_key_internal(const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length); + +/** Sign a message with a private key. For hash-and-sign algorithms, + * this includes the hashing step. + * + * \note The signature of this function is that of a PSA driver + * sign_message entry point. This function behaves as a sign_message + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \note This function will call the driver for psa_sign_hash + * and go through driver dispatch again. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] input The input message to sign. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param[in] signature_size Size of the \p signature buffer in bytes. + * \param[out] signature_length On success, the number of bytes + * that make up the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of the key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + */ +psa_status_t psa_sign_message_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *input, size_t input_length, + uint8_t *signature, size_t signature_size, size_t *signature_length); + +/** Verify the signature of a message with a public key, using + * a hash-and-sign verification algorithm. + * + * \note The signature of this function is that of a PSA driver + * verify_message entry point. This function behaves as a verify_message + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \note This function will call the driver for psa_verify_hash + * and go through driver dispatch again. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] input The message whose signature is to be verified. + * \param[in] input_length Size of the \p input buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param[in] signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The signature is valid. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t psa_verify_message_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *input, size_t input_length, + const uint8_t *signature, size_t signature_length); + +/** Sign an already-calculated hash with a private key. + * + * \note The signature of this function is that of a PSA driver + * sign_hash entry point. This function behaves as a sign_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] hash The hash or message to sign. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param[in] signature_size Size of the \p signature buffer in bytes. + * \param[out] signature_length On success, the number of bytes + * that make up the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of the key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + */ +psa_status_t psa_sign_hash_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length); + +/** + * \brief Verify the signature a hash or short message using a public key. + * + * \note The signature of this function is that of a PSA driver + * verify_hash entry point. This function behaves as a verify_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] hash The hash or message whose signature is to be + * verified. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param[in] signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The signature is valid. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t psa_verify_hash_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length); + +/** + * \brief Validate the key bit size for unstructured keys. + * + * \note Check that the bit size is acceptable for a given key type for + * unstructured keys. + * + * \param[in] type The key type + * \param[in] bits The number of bits of the key + * + * \retval #PSA_SUCCESS + * The key type and size are valid. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The size in bits of the key is not valid. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The type and/or the size in bits of the key or the combination of + * the two is not supported. + */ +psa_status_t psa_validate_unstructured_key_bit_size(psa_key_type_t type, + size_t bits); + +/** Perform a key agreement and return the raw shared secret, using + built-in raw key agreement functions. + * + * \note The signature of this function is that of a PSA driver + * key_agreement entry point. This function behaves as a key_agreement + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the private key + * context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in + * bytes. + * \param[in] alg A key agreement algorithm that is + * compatible with the type of the key. + * \param[in] peer_key The buffer containing the key context + * of the peer's public key. + * \param[in] peer_key_length Size of the \p peer_key buffer in + * bytes. + * \param[out] shared_secret The buffer to which the shared secret + * is to be written. + * \param[in] shared_secret_size Size of the \p shared_secret buffer in + * bytes. + * \param[out] shared_secret_length On success, the number of bytes that make + * up the returned shared secret. + * \retval #PSA_SUCCESS + * Success. Shared secret successfully calculated. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p alg is not a key agreement algorithm, or + * \p private_key is not compatible with \p alg, + * or \p peer_key is not valid for \p alg or not compatible with + * \p private_key. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p shared_secret_size is too small + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not a supported key agreement algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_BAD_STATE \emptydescription + */ +psa_status_t psa_key_agreement_raw_builtin( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length); + +/** + * \brief Set the maximum number of ops allowed to be executed by an + * interruptible function in a single call. + * + * \note The signature of this function is that of a PSA driver + * interruptible_set_max_ops entry point. This function behaves as an + * interruptible_set_max_ops entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in] max_ops The maximum number of ops to be executed in a + * single call, this can be a number from 0 to + * #PSA_INTERRUPTIBLE_MAX_OPS_UNLIMITED, where 0 + * is obviously the least amount of work done per + * call. + */ +void mbedtls_psa_interruptible_set_max_ops(uint32_t max_ops); + +/** + * \brief Get the maximum number of ops allowed to be executed by an + * interruptible function in a single call. + * + * \note The signature of this function is that of a PSA driver + * interruptible_get_max_ops entry point. This function behaves as an + * interruptible_get_max_ops entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \return Maximum number of ops allowed to be executed + * by an interruptible function in a single call. + */ +uint32_t mbedtls_psa_interruptible_get_max_ops(void); + +/** + * \brief Get the number of ops that a hash signing operation has taken for the + * previous call. If no call or work has taken place, this will return + * zero. + * + * \note The signature of this function is that of a PSA driver + * sign_hash_get_num_ops entry point. This function behaves as an + * sign_hash_get_num_ops entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param operation The \c + * mbedtls_psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \return Number of ops that were completed + * in the last call to \c + * mbedtls_psa_sign_hash_complete(). + */ +uint32_t mbedtls_psa_sign_hash_get_num_ops( + const mbedtls_psa_sign_hash_interruptible_operation_t *operation); + +/** + * \brief Get the number of ops that a hash verification operation has taken for + * the previous call. If no call or work has taken place, this will + * return zero. + * + * \note The signature of this function is that of a PSA driver + * verify_hash_get_num_ops entry point. This function behaves as an + * verify_hash_get_num_ops entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param operation The \c + * mbedtls_psa_verify_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \return Number of ops that were completed + * in the last call to \c + * mbedtls_psa_verify_hash_complete(). + */ +uint32_t mbedtls_psa_verify_hash_get_num_ops( + const mbedtls_psa_verify_hash_interruptible_operation_t *operation); + +/** + * \brief Start signing a hash or short message with a private key, in an + * interruptible manner. + * + * \note The signature of this function is that of a PSA driver + * sign_hash_start entry point. This function behaves as a + * sign_hash_start entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * \param[in] operation The \c + * mbedtls_psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] hash The hash or message to sign. + * \param hash_length Size of the \p hash buffer in bytes. + * + * \retval #PSA_SUCCESS + * The operation started successfully - call \c psa_sign_hash_complete() + * with the same context to complete the operation + * \retval #PSA_ERROR_INVALID_ARGUMENT + * An unsupported, incorrectly formatted or incorrect type of key was + * used. + * \retval #PSA_ERROR_NOT_SUPPORTED Either no internal interruptible operations + * are currently supported, or the key type is currently unsupported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * There was insufficient memory to load the key representation. + */ +psa_status_t mbedtls_psa_sign_hash_start( + mbedtls_psa_sign_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length); + +/** + * \brief Continue and eventually complete the action of signing a hash or + * short message with a private key, in an interruptible manner. + * + * \note The signature of this function is that of a PSA driver + * sign_hash_complete entry point. This function behaves as a + * sign_hash_complete entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * \param[in] operation The \c + * mbedtls_psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \param[out] signature Buffer where the signature is to be written. + * \param signature_size Size of the \p signature buffer in bytes. This + * must be appropriate for the selected + * algorithm and key. + * \param[out] signature_length On success, the number of bytes that make up + * the returned signature value. + * + * \retval #PSA_SUCCESS + * Operation completed successfully + * + * \retval #PSA_OPERATION_INCOMPLETE + * Operation was interrupted due to the setting of \c + * psa_interruptible_set_max_ops(), there is still work to be done, + * please call this function again with the same operation object. + * + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + */ +psa_status_t mbedtls_psa_sign_hash_complete( + mbedtls_psa_sign_hash_interruptible_operation_t *operation, + uint8_t *signature, size_t signature_size, + size_t *signature_length); + +/** + * \brief Abort a sign hash operation. + * + * \note The signature of this function is that of a PSA driver sign_hash_abort + * entry point. This function behaves as a sign_hash_abort entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * \param[in] operation The \c + * mbedtls_psa_sign_hash_interruptible_operation_t + * to abort. + * + * \retval #PSA_SUCCESS + * The operation was aborted successfully. + */ +psa_status_t mbedtls_psa_sign_hash_abort( + mbedtls_psa_sign_hash_interruptible_operation_t *operation); + +/** + * \brief Start reading and verifying a hash or short message, in an + * interruptible manner. + * + * \note The signature of this function is that of a PSA driver + * verify_hash_start entry point. This function behaves as a + * verify_hash_start entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * \param[in] operation The \c + * mbedtls_psa_verify_hash_interruptible_operation_t + * to use. This must be initialized first. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * the type of the key. + * \param[in] hash The hash whose signature is to be verified. + * \param hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The operation started successfully - call \c psa_sign_hash_complete() + * with the same context to complete the operation + * \retval #PSA_ERROR_INVALID_ARGUMENT + * An unsupported or incorrect type of key was used. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Either no internal interruptible operations are currently supported, + * or the key type is currently unsupported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * There was insufficient memory either to load the key representation, + * or to prepare the operation. + */ +psa_status_t mbedtls_psa_verify_hash_start( + mbedtls_psa_verify_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length); + +/** + * \brief Continue and eventually complete the action of signing a hash or + * short message with a private key, in an interruptible manner. + * + * \note The signature of this function is that of a PSA driver + * sign_hash_complete entry point. This function behaves as a + * sign_hash_complete entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * \param[in] operation The \c + * mbedtls_psa_sign_hash_interruptible_operation_t + * to use. This must be initialized first. + * + * \retval #PSA_SUCCESS + * Operation completed successfully, and the passed signature is valid. + * + * \retval #PSA_OPERATION_INCOMPLETE + * Operation was interrupted due to the setting of \c + * psa_interruptible_set_max_ops(), there is still work to be done, + * please call this function again with the same operation object. + * + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_verify_hash_complete( + mbedtls_psa_verify_hash_interruptible_operation_t *operation); + +/** + * \brief Abort a verify signed hash operation. + * + * \note The signature of this function is that of a PSA driver + * verify_hash_abort entry point. This function behaves as a + * verify_hash_abort entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * \param[in] operation The \c + * mbedtls_psa_verify_hash_interruptible_operation_t + * to abort. + * + * \retval #PSA_SUCCESS + * The operation was aborted successfully. + */ +psa_status_t mbedtls_psa_verify_hash_abort( + mbedtls_psa_verify_hash_interruptible_operation_t *operation); + +/** Test whether the number of readers of this lock is equal to 0. + * + * \param[in] slot The key slot to test. + * \retval 0 + * The key slot has at least one active reader. + * \retval 1 + * The key slot has no active readers. + */ +int psa_slot_has_no_readers( psa_key_slot_t *slot ); + +/** Transition the slot to a given state + * + * \param[in] slot The key slot. + * \param[in] target_state The desired slot state. + * + * Please note that, if MBEDTLS_THREADING_C is enabled, this function should + * be called with locked mbedtls_psa_slots_mutex. + * + * \retval #PSA_ERROR_INVALID_HANDLE + * \p slot is empty and a bad state change was requested. + * \retval #PSA_ERROR_BAD_STATE + * The requested state transition could not be performed. + * \retval #PSA_SUCCESS + * The transition succeeded and \p slot is now in \p target_state. + */ +psa_status_t psa_slot_change_state( psa_key_slot_t *slot, + psa_key_slot_state_t target_state ); + +#if defined(MBEDTLS_TEST_HOOKS) +/** + * \brief Get a key slot from global data. Used in tests to check slot state + * without locking it. + */ +psa_key_slot_t* mbedtls_psa_get_key_slot( uint32_t num ); +#endif + +#endif /* PSA_CRYPTO_CORE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core_common.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core_common.h index dd72ab1..c5575da 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core_common.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_core_common.h @@ -1,64 +1,64 @@ -/** - * \file psa_crypto_core_common.h - * - * \brief Utility macros for internal use in the PSA cryptography core. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_CORE_COMMON_H -#define PSA_CRYPTO_CORE_COMMON_H - -/** Return an offset into a buffer. - * - * This is just the addition of an offset to a pointer, except that this - * function also accepts an offset of 0 into a buffer whose pointer is null. - * (`p + n` has undefined behavior when `p` is null, even when `n == 0`. - * A null pointer is a valid buffer pointer when the size is 0, for example - * as the result of `malloc(0)` on some platforms.) - * - * \param p Pointer to a buffer of at least n bytes. - * This may be \p NULL if \p n is zero. - * \param n An offset in bytes. - * \return Pointer to offset \p n in the buffer \p p. - * Note that this is only a valid pointer if the size of the - * buffer is at least \p n + 1. - */ -static inline unsigned char *psa_crypto_buffer_offset( - unsigned char *p, size_t n) -{ - return p == NULL ? NULL : p + n; -} - -/** Return an offset into a read-only buffer. - * - * Similar to mbedtls_buffer_offset(), but for const pointers. - * - * \param p Pointer to a buffer of at least n bytes. - * This may be \p NULL if \p n is zero. - * \param n An offset in bytes. - * \return Pointer to offset \p n in the buffer \p p. - * Note that this is only a valid pointer if the size of the - * buffer is at least \p n + 1. - */ -static inline const unsigned char *psa_crypto_buffer_offset_const( - const unsigned char *p, size_t n) -{ - return p == NULL ? NULL : p + n; -} - -#endif /* PSA_CRYPTO_CORE_COMMON_H */ +/** + * \file psa_crypto_core_common.h + * + * \brief Utility macros for internal use in the PSA cryptography core. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_CORE_COMMON_H +#define PSA_CRYPTO_CORE_COMMON_H + +/** Return an offset into a buffer. + * + * This is just the addition of an offset to a pointer, except that this + * function also accepts an offset of 0 into a buffer whose pointer is null. + * (`p + n` has undefined behavior when `p` is null, even when `n == 0`. + * A null pointer is a valid buffer pointer when the size is 0, for example + * as the result of `malloc(0)` on some platforms.) + * + * \param p Pointer to a buffer of at least n bytes. + * This may be \p NULL if \p n is zero. + * \param n An offset in bytes. + * \return Pointer to offset \p n in the buffer \p p. + * Note that this is only a valid pointer if the size of the + * buffer is at least \p n + 1. + */ +static inline unsigned char *psa_crypto_buffer_offset( + unsigned char *p, size_t n) +{ + return p == NULL ? NULL : p + n; +} + +/** Return an offset into a read-only buffer. + * + * Similar to mbedtls_buffer_offset(), but for const pointers. + * + * \param p Pointer to a buffer of at least n bytes. + * This may be \p NULL if \p n is zero. + * \param n An offset in bytes. + * \return Pointer to offset \p n in the buffer \p p. + * Note that this is only a valid pointer if the size of the + * buffer is at least \p n + 1. + */ +static inline const unsigned char *psa_crypto_buffer_offset_const( + const unsigned char *p, size_t n) +{ + return p == NULL ? NULL : p + n; +} + +#endif /* PSA_CRYPTO_CORE_COMMON_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h index 18715fd..ec52d89 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers.h @@ -1,4444 +1,4444 @@ -/* - * Functions to delegate cryptographic operations to an available - * and appropriate accelerator. - * Warning: This file is now auto-generated. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -/* BEGIN-common headers */ -#include "common.h" -#include "psa_crypto_aead.h" -#include "psa_crypto_cipher.h" -#include "psa_crypto_core.h" -#include "psa_crypto_driver_wrappers_no_static.h" -#include "psa_crypto_hash.h" -#include "psa_crypto_mac.h" -#include "psa_crypto_pake.h" -#include "psa_crypto_rsa.h" - -#include "mbedtls/platform.h" -#include "mbedtls/constant_time.h" -/* END-common headers */ - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -/* BEGIN-driver headers */ -/* Headers for mbedtls_test opaque driver */ -#if defined(PSA_CRYPTO_DRIVER_TEST) -#include "test/drivers/test_driver.h" - -#endif -/* Headers for mbedtls_test transparent driver */ -#if defined(PSA_CRYPTO_DRIVER_TEST) -#include "test/drivers/test_driver.h" - -#endif -/* Headers for p256 transparent driver */ -#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) -#include "../3rdparty/p256-m/p256-m_driver_entrypoints.h" - -#endif - - -/* SiLabs Driver Headers */ -#include "sli_psa_driver_features.h" - -#include - -#if defined(SLI_MBEDTLS_DEVICE_HSE) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_se_transparent_types.h" -#include "sli_se_transparent_functions.h" -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_se_opaque_types.h" -#include "sli_se_opaque_functions.h" -#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ - -#if defined(SLI_MBEDTLS_DEVICE_VSE) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" -#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) -#include "sli_cryptoacc_opaque_types.h" -#include "sli_cryptoacc_opaque_functions.h" -#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif - -#if defined(SLI_MBEDTLS_DEVICE_S1) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_crypto_transparent_types.h" -#include "sli_crypto_transparent_functions.h" -#endif - -#if defined(SLI_MBEDTLS_DEVICE_SI91X) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_si91x_crypto_driver_functions.h" -#endif - -#ifdef SLI_SECURE_KEY_STORAGE_DEVICE_SI91X -#include "sl_si91x_psa_wrap.h" -#endif /* Secure key storage driver **/ - -/* END-driver headers */ - -/* Auto-generated values depending on which drivers are registered. - * ID 0 is reserved for unallocated operations. - * ID 1 is reserved for the Mbed TLS software driver. */ -/* BEGIN-driver id definition */ -#define PSA_CRYPTO_MBED_TLS_DRIVER_ID (1) -#define MBEDTLS_TEST_OPAQUE_DRIVER_ID (2) -#define MBEDTLS_TEST_TRANSPARENT_DRIVER_ID (3) -#define P256_TRANSPARENT_DRIVER_ID (4) - - -/* SiLabs Driver IDs */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#define SLI_SE_TRANSPARENT_DRIVER_ID (4) -#define SLI_SE_OPAQUE_DRIVER_ID (5) -#define SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID (6) -#define SLI_CRYPTO_TRANSPARENT_DRIVER_ID (7) -#endif - -/* END-driver id */ - -/* BEGIN-Common Macro definitions */ - -/* END-Common Macro definitions */ - -/* Support the 'old' SE interface when asked to */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* PSA_CRYPTO_DRIVER_PRESENT is defined when either a new-style or old-style - * SE driver is present, to avoid unused argument errors at compile time. */ -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#include "psa_crypto_se.h" -#endif - -static inline psa_status_t psa_driver_wrapper_init( void ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - status = psa_init_all_se_drivers( ); - if( status != PSA_SUCCESS ) - return( status ); -#endif - -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_init( ); - if( status != PSA_SUCCESS ) - return( status ); - - status = mbedtls_test_opaque_init( ); - if( status != PSA_SUCCESS ) - return( status ); -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_driver_init(); - if( status != PSA_SUCCESS ) - return( status ); -#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - status = sli_se_opaque_driver_init(); - if( status != PSA_SUCCESS ) - return( status ); -#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_driver_init(); - if( status != PSA_SUCCESS ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_driver_init(); - if( status != PSA_SUCCESS ) - return( status ); -#endif -#if defined(SLI_TRNG_DEVICE_SI91X) - status = sli_si91x_crypto_trng_init(); - if( status != PSA_SUCCESS ) - return( status ); -#endif - - (void) status; - return( PSA_SUCCESS ); -} - -static inline void psa_driver_wrapper_free( void ) -{ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* Unregister all secure element drivers, so that we restart from - * a pristine state. */ - psa_unregister_all_se_drivers( ); -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - -#if defined(PSA_CRYPTO_DRIVER_TEST) - mbedtls_test_transparent_free( ); - mbedtls_test_opaque_free( ); -#endif -} - -/* Start delegation functions */ -static inline psa_status_t psa_driver_wrapper_sign_message( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_signature_sign_message( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_size, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_sign_message( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_size, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - break; - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_signature_sign_message( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_size, - signature_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); - break; -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_sign_message( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_size, - signature_length ); - /* No fallback for opaque */ - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - break; - } - - return( psa_sign_message_builtin( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_size, - signature_length ) ); -} - -static inline psa_status_t psa_driver_wrapper_verify_message( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *signature, - size_t signature_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_signature_verify_message( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_verify_message( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - break; - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_signature_verify_message( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_verify_message( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_length ); - /* No fallback for opaque */ - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - break; - } - - return( psa_verify_message_builtin( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - signature, - signature_length ) ); -} - -static inline psa_status_t psa_driver_wrapper_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length ) -{ - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - if( drv->asymmetric == NULL || - drv->asymmetric->p_sign == NULL ) - { - /* Key is defined in SE, but we have no way to exercise it */ - return( PSA_ERROR_NOT_SUPPORTED ); - } - return( drv->asymmetric->p_sign( - drv_context, *( (psa_key_slot_number_t *)key_buffer ), - alg, hash, hash_length, - signature, signature_size, signature_length ) ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_signature_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) - if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && - PSA_ALG_IS_ECDSA(alg) && - !PSA_ALG_ECDSA_IS_DETERMINISTIC( alg ) && - PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && - attributes->core.bits == 256 ) - { - status = p256_transparent_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); - } -#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - /* Fell through, meaning no accelerator supports this operation */ - return( psa_sign_hash_builtin( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ) ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_signature_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_sign_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_size, - signature_length ); - /* No fallback for opaque */ - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length ) -{ - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - if( drv->asymmetric == NULL || - drv->asymmetric->p_verify == NULL ) - { - /* Key is defined in SE, but we have no way to exercise it */ - return( PSA_ERROR_NOT_SUPPORTED ); - } - return( drv->asymmetric->p_verify( - drv_context, *( (psa_key_slot_number_t *)key_buffer ), - alg, hash, hash_length, - signature, signature_length ) ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_signature_verify_hash( - attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) - if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && - PSA_ALG_IS_ECDSA(alg) && - !PSA_ALG_ECDSA_IS_DETERMINISTIC( alg ) && - PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && - attributes->core.bits == 256 ) - { - status = p256_transparent_verify_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); - } -#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_verify_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_MBEDTLS_DEVICE_HSE */ -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_verify_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_MBEDTLS_DEVICE_VSE */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - return( psa_verify_hash_builtin( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ) ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_signature_verify_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_verify_hash( attributes, - key_buffer, - key_buffer_size, - alg, - hash, - hash_length, - signature, - signature_length ); - /* No fallback for opaque */ - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline uint32_t psa_driver_wrapper_sign_hash_get_num_ops( - psa_sign_hash_interruptible_operation_t *operation ) -{ - switch( operation->id ) - { - /* If uninitialised, return 0, as no work can have been done. */ - case 0: - return 0; - - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return(mbedtls_psa_sign_hash_get_num_ops(&operation->ctx.mbedtls_ctx)); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - /* Can't happen (see discussion in #8271) */ - return 0; -} - -static inline uint32_t psa_driver_wrapper_verify_hash_get_num_ops( - psa_verify_hash_interruptible_operation_t *operation ) -{ - switch( operation->id ) - { - /* If uninitialised, return 0, as no work can have been done. */ - case 0: - return 0; - - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return (mbedtls_psa_verify_hash_get_num_ops(&operation->ctx.mbedtls_ctx)); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - } - - /* Can't happen (see discussion in #8271) */ - return 0; -} - -static inline psa_status_t psa_driver_wrapper_sign_hash_start( - psa_sign_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length ) -{ - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( - attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - - /* Add test driver tests here */ - - /* Declared with fallback == true */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - return( mbedtls_psa_sign_hash_start( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length ) ); - break; - - /* Add cases for opaque driver here */ - - default: - /* Key is declared with a lifetime not known to us */ - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_sign_hash_complete( - psa_sign_hash_interruptible_operation_t *operation, - uint8_t *signature, size_t signature_size, - size_t *signature_length ) -{ - switch( operation->id ) - { - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_sign_hash_complete( &operation->ctx.mbedtls_ctx, - signature, signature_size, - signature_length ) ); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - ( void ) signature; - ( void ) signature_size; - ( void ) signature_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_sign_hash_abort( - psa_sign_hash_interruptible_operation_t *operation ) -{ - switch( operation->id ) - { - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_sign_hash_abort( &operation->ctx.mbedtls_ctx ) ); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_verify_hash_start( - psa_verify_hash_interruptible_operation_t *operation, - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, - const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length ) -{ - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( - attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - - /* Add test driver tests here */ - - /* Declared with fallback == true */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - return( mbedtls_psa_verify_hash_start( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, key_buffer_size, - alg, hash, hash_length, - signature, signature_length - ) ); - break; - - /* Add cases for opaque driver here */ - - default: - /* Key is declared with a lifetime not known to us */ - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_verify_hash_complete( - psa_verify_hash_interruptible_operation_t *operation ) -{ - switch( operation->id ) - { - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_verify_hash_complete( - &operation->ctx.mbedtls_ctx - ) ); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_verify_hash_abort( - psa_verify_hash_interruptible_operation_t *operation ) -{ - switch( operation->id ) - { - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_verify_hash_abort( &operation->ctx.mbedtls_ctx - ) ); - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - /* Add test driver tests here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -/** Calculate the key buffer size required to store the key material of a key - * associated with an opaque driver from input key data. - * - * \param[in] attributes The key attributes - * \param[in] data The input key data. - * \param[in] data_length The input data length. - * \param[out] key_buffer_size Minimum buffer size to contain the key material. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - */ -static inline psa_status_t psa_driver_wrapper_get_key_buffer_size_from_key_data( - const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - size_t *key_buffer_size ) -{ - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - psa_key_type_t key_type = attributes->core.type; - - *key_buffer_size = 0; - switch( location ) - { -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - *key_buffer_size = mbedtls_test_opaque_size_function( key_type, - PSA_BYTES_TO_BITS( data_length ) ); - return( ( *key_buffer_size != 0 ) ? - PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - *key_buffer_size = data_length; - return( psa_driver_wrapper_get_key_buffer_size( attributes, key_buffer_size ) ); -#endif -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - *key_buffer_size = data_length; - return( ( *key_buffer_size != 0 ) ? - PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); - break; -#endif - - default: - (void)key_type; - (void)data; - (void)data_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION(attributes->core.lifetime); - - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - size_t pubkey_length = 0; /* We don't support this feature yet */ - if( drv->key_management == NULL || - drv->key_management->p_generate == NULL ) - { - /* Key is defined as being in SE, but we have no way to generate it */ - return( PSA_ERROR_NOT_SUPPORTED ); - } - return( drv->key_management->p_generate( - drv_context, - *( (psa_key_slot_number_t *)key_buffer ), - attributes, NULL, 0, &pubkey_length ) ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - /* Transparent drivers are limited to generating asymmetric keys */ - if( PSA_KEY_TYPE_IS_ASYMMETRIC( attributes->core.type ) ) - { - /* Cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_generate_key( - attributes, key_buffer, key_buffer_size, - key_buffer_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - break; -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) - if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && - attributes->core.type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1) && - attributes->core.bits == 256 ) - { - status = p256_transparent_generate_key( attributes, - key_buffer, - key_buffer_size, - key_buffer_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - break; - } - -#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_generate_key( attributes, - key_buffer, - key_buffer_size, - key_buffer_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - break; -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_generate_key( attributes, - key_buffer, - key_buffer_size, - key_buffer_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - break; -#endif -#if defined(SLI_ECDH_DEVICE_SI91X) - status = sli_si91x_psa_generate_key_ecdh( attributes, - key_buffer, - key_buffer_size, - key_buffer_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - break; -#endif // SLI_ECDH_DEVICE_SI91X - } -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Software fallback */ - status = psa_generate_key_internal( - attributes, key_buffer, key_buffer_size, key_buffer_length ); - break; - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_generate_key( - attributes, key_buffer, key_buffer_size, key_buffer_length ); - break; -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - // Call opaque driver API - status = sli_se_opaque_generate_key( attributes, - key_buffer, - key_buffer_size, - key_buffer_length ); - /* No fallback for opaque drivers */ - return status; -#endif -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - if( PSA_KEY_TYPE_IS_ASYMMETRIC( attributes->core.type ) ) - { - /* Software fallback for Si91x Devices */ - status = psa_generate_key_internal( - attributes, key_buffer, key_buffer_size, key_buffer_length ); - if( status == PSA_SUCCESS ){ - status = sli_si91x_crypto_wrap_key(key_buffer, - *key_buffer_length, - SL_SI91X_WRAP_IV_CBC_MODE, - WRAP_IV); - } - } else { - /* symmetric key generation */ - status = sli_si91x_crypto_generate_symm_key(key_buffer, - key_buffer_size, - SL_SI91X_WRAP_IV_CBC_MODE, - WRAP_IV); - } - return status; - break; -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - /* Key is declared with a lifetime not known to us */ - status = PSA_ERROR_INVALID_ARGUMENT; - break; - } - - return( status ); -} - -static inline psa_status_t psa_driver_wrapper_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, - size_t data_length, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_buffer_length, - size_t *bits ) -{ - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( - psa_get_key_lifetime( attributes ) ); - - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - if( drv->key_management == NULL || - drv->key_management->p_import == NULL ) - return( PSA_ERROR_NOT_SUPPORTED ); - - /* The driver should set the number of key bits, however in - * case it doesn't, we initialize bits to an invalid value. */ - *bits = PSA_MAX_KEY_BITS + 1; - status = drv->key_management->p_import( - drv_context, - *( (psa_key_slot_number_t *)key_buffer ), - attributes, data, data_length, bits ); - - if( status != PSA_SUCCESS ) - return( status ); - - if( (*bits) > PSA_MAX_KEY_BITS ) - return( PSA_ERROR_NOT_SUPPORTED ); - - return( PSA_SUCCESS ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - status = mbedtls_test_transparent_import_key - (attributes, - data, - data_length, - key_buffer, - key_buffer_size, - key_buffer_length, - bits - ); - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - -#if (defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) ) - status = p256_transparent_import_key - (attributes, - data, - data_length, - key_buffer, - key_buffer_size, - key_buffer_length, - bits - ); - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - - -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_import_key( attributes, - data, data_length, - key_buffer, - key_buffer_size, - key_buffer_length, - bits ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_import_key( attributes, - data, data_length, - key_buffer, - key_buffer_size, - key_buffer_length, - bits ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - return( psa_import_key_into_slot( attributes, - data, data_length, - key_buffer, key_buffer_size, - key_buffer_length, bits ) ); - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - case 0x7fffff: - return( mbedtls_test_opaque_import_key - (attributes, - data, - data_length, - key_buffer, - key_buffer_size, - key_buffer_length, - bits - )); -#endif - - -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return( sli_se_opaque_import_key( - attributes, - data, data_length, - key_buffer, key_buffer_size, - key_buffer_length, bits ) ); -#endif -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - status = psa_import_key_into_slot( attributes, - data, data_length, - key_buffer, key_buffer_size, - key_buffer_length, bits ); - if( status == PSA_SUCCESS ){ - status = sli_si91x_crypto_wrap_key(key_buffer, - *key_buffer_length, - SL_SI91X_WRAP_IV_CBC_MODE, - WRAP_IV); - } - return( status ); - break; -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } - -} - -static inline psa_status_t psa_driver_wrapper_export_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length ) - -{ - - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( - psa_get_key_lifetime( attributes ) ); - - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - if( ( drv->key_management == NULL ) || - ( drv->key_management->p_export == NULL ) ) - { - return( PSA_ERROR_NOT_SUPPORTED ); - } - - return( drv->key_management->p_export( - drv_context, - *( (psa_key_slot_number_t *)key_buffer ), - data, data_size, data_length ) ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - return( psa_export_key_internal( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ) ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - case 0x7fffff: - return( mbedtls_test_opaque_export_key - (attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length - )); -#endif - - -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - // We are on a vault device, call opaque driver - return( sli_se_opaque_export_key( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ) ); -#endif -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - return( psa_export_key_internal( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ) ); - break; -#endif - default: - /* Key is declared with a lifetime not known to us */ - return( status ); - } - -} - -static inline psa_status_t psa_driver_wrapper_copy_key( - psa_key_attributes_t *attributes, - const uint8_t *source_key, size_t source_key_length, - uint8_t *target_key_buffer, size_t target_key_buffer_size, - size_t *target_key_buffer_length ) -{ - - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - /* Copying to a secure element is not implemented yet. */ - return( PSA_ERROR_NOT_SUPPORTED ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch( location ) - { -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - case 0x7fffff: - return( mbedtls_test_opaque_copy_key - (attributes, - source_key, - source_key_length, - target_key_buffer, - target_key_buffer_size, - target_key_buffer_length - )); -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE) \ - && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return sli_se_opaque_copy_key(attributes, - source_key, - source_key_length, - target_key_buffer, - target_key_buffer_size, - target_key_buffer_length); -#endif - -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void)source_key; - (void)source_key_length; - (void)target_key_buffer; - (void)target_key_buffer_size; - (void)target_key_buffer_length; - status = PSA_ERROR_INVALID_ARGUMENT; - } - return( status ); - -} - -/* - * Cipher functions - */ -static inline psa_status_t psa_driver_wrapper_cipher_encrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *iv, - size_t iv_length, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_cipher_encrypt( attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_cipher_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_cipher_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_cipher_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_CIPHER_DEVICE_SI91X) - status = sli_si91x_crypto_cipher_encrypt( attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_CIPHER_DEVICE_SI91X */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - return( mbedtls_psa_cipher_encrypt( attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ) ); -#else - return( PSA_ERROR_NOT_SUPPORTED ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_cipher_encrypt( attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return ( sli_se_opaque_cipher_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - iv, - iv_length, - input, - input_length, - output, - output_size, - output_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)iv; - (void)iv_length; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_cipher_decrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_cipher_decrypt( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_cipher_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_cipher_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_cipher_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_CIPHER_DEVICE_SI91X) - status = sli_si91x_crypto_cipher_decrypt( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_CIPHER_DEVICE_SI91X */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - return( mbedtls_psa_cipher_decrypt( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ) ); -#else - return( PSA_ERROR_NOT_SUPPORTED ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_cipher_decrypt( attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return ( sli_se_opaque_cipher_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - input, - input_length, - output, - output_size, - output_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( - psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_cipher_encrypt_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_cipher_encrypt_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_cipher_encrypt_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_cipher_encrypt_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - /* Fell through, meaning no accelerator supports this operation */ - status = mbedtls_psa_cipher_encrypt_setup( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - return( PSA_ERROR_NOT_SUPPORTED ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_cipher_encrypt_setup( - &operation->ctx.opaque_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; - - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_cipher_encrypt_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)operation; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( - psa_cipher_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_cipher_decrypt_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_cipher_decrypt_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_cipher_decrypt_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_cipher_decrypt_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - /* Fell through, meaning no accelerator supports this operation */ - status = mbedtls_psa_cipher_decrypt_setup( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - - return( status ); -#else /* MBEDTLS_PSA_BUILTIN_CIPHER */ - return( PSA_ERROR_NOT_SUPPORTED ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_cipher_decrypt_setup( - &operation->ctx.opaque_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; - - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_cipher_decrypt_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, - key_buffer, - key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)operation; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_cipher_set_iv( - psa_cipher_operation_t *operation, - const uint8_t *iv, - size_t iv_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_cipher_set_iv( &operation->ctx.mbedtls_ctx, - iv, - iv_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_cipher_set_iv( - &operation->ctx.transparent_test_driver_ctx, - iv, iv_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_cipher_set_iv( - &operation->ctx.opaque_test_driver_ctx, - iv, iv_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_cipher_set_iv( - &operation->ctx.sli_se_transparent_ctx, - iv, iv_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_cipher_set_iv( - &operation->ctx.sli_cryptoacc_transparent_ctx, - iv, iv_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_cipher_set_iv( - &operation->ctx.sli_crypto_transparent_ctx, - iv, iv_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_cipher_set_iv( - &operation->ctx.sli_se_opaque_ctx, - iv, iv_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)iv; - (void)iv_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_cipher_update( - psa_cipher_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_cipher_update( &operation->ctx.mbedtls_ctx, - input, - input_length, - output, - output_size, - output_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_cipher_update( - &operation->ctx.transparent_test_driver_ctx, - input, input_length, - output, output_size, output_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_cipher_update( - &operation->ctx.opaque_test_driver_ctx, - input, input_length, - output, output_size, output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_cipher_update( - &operation->ctx.sli_se_transparent_ctx, - input, input_length, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_cipher_update( - &operation->ctx.sli_cryptoacc_transparent_ctx, - input, input_length, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_cipher_update( - &operation->ctx.sli_crypto_transparent_ctx, - input, input_length, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_cipher_update( - &operation->ctx.sli_se_opaque_ctx, - input, input_length, - output, output_size, output_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_cipher_finish( - psa_cipher_operation_t *operation, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_cipher_finish( &operation->ctx.mbedtls_ctx, - output, - output_size, - output_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_cipher_finish( - &operation->ctx.transparent_test_driver_ctx, - output, output_size, output_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_cipher_finish( - &operation->ctx.opaque_test_driver_ctx, - output, output_size, output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_cipher_finish( - &operation->ctx.sli_se_transparent_ctx, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_cipher_finish( - &operation->ctx.sli_cryptoacc_transparent_ctx, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_cipher_finish( - &operation->ctx.sli_crypto_transparent_ctx, - output, output_size, output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_cipher_finish( - &operation->ctx.sli_se_opaque_ctx, - output, output_size, output_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)output; - (void)output_size; - (void)output_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_cipher_abort( - psa_cipher_operation_t *operation ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_cipher_abort( &operation->ctx.mbedtls_ctx ) ); -#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - status = mbedtls_test_transparent_cipher_abort( - &operation->ctx.transparent_test_driver_ctx ); - mbedtls_platform_zeroize( - &operation->ctx.transparent_test_driver_ctx, - sizeof( operation->ctx.transparent_test_driver_ctx ) ); - return( status ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - status = mbedtls_test_opaque_cipher_abort( - &operation->ctx.opaque_test_driver_ctx ); - mbedtls_platform_zeroize( - &operation->ctx.opaque_test_driver_ctx, - sizeof( operation->ctx.opaque_test_driver_ctx ) ); - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_cipher_abort( - &operation->ctx.sli_se_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_cipher_abort( - &operation->ctx.sli_cryptoacc_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_cipher_abort( - &operation->ctx.sli_crypto_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_cipher_abort( - &operation->ctx.sli_se_opaque_ctx ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -/* - * Hashing functions - */ -static inline psa_status_t psa_driver_wrapper_hash_compute( - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* Try accelerators first */ -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_hash_compute( - alg, input, input_length, hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_hash_compute( - alg, input, input_length, hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_hash_compute( - alg, input, input_length, hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_hash_compute( - alg, input, input_length, hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_SHA_DEVICE_SI91X) - status = sli_si91x_crypto_hash_compute( - alg, input, input_length, hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - - /* If software fallback is compiled in, try fallback */ -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - status = mbedtls_psa_hash_compute( alg, input, input_length, - hash, hash_size, hash_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - (void) status; - (void) alg; - (void) input; - (void) input_length; - (void) hash; - (void) hash_size; - (void) hash_length; - - return( PSA_ERROR_NOT_SUPPORTED ); -} - -static inline psa_status_t psa_driver_wrapper_hash_setup( - psa_hash_operation_t *operation, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* Try setup on accelerators first */ -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_hash_setup( - &operation->ctx.test_driver_ctx, alg ); - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_hash_setup( - &operation->ctx.sli_se_transparent_ctx, alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_hash_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_hash_setup( - &operation->ctx.sli_crypto_transparent_ctx, alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif - - /* If software fallback is compiled in, try fallback */ -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - status = mbedtls_psa_hash_setup( &operation->ctx.mbedtls_ctx, alg ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - /* Nothing left to try if we fall through here */ - (void) status; - (void) operation; - (void) alg; - return( PSA_ERROR_NOT_SUPPORTED ); -} - -static inline psa_status_t psa_driver_wrapper_hash_clone( - const psa_hash_operation_t *source_operation, - psa_hash_operation_t *target_operation ) -{ - switch( source_operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - target_operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - return( mbedtls_psa_hash_clone( &source_operation->ctx.mbedtls_ctx, - &target_operation->ctx.mbedtls_ctx ) ); -#endif -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - target_operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - return( mbedtls_test_transparent_hash_clone( - &source_operation->ctx.test_driver_ctx, - &target_operation->ctx.test_driver_ctx ) ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - target_operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - return( sli_se_transparent_hash_clone( - &source_operation->ctx.sli_se_transparent_ctx, - &target_operation->ctx.sli_se_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - target_operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - return( sli_cryptoacc_transparent_hash_clone( - &source_operation->ctx.sli_cryptoacc_transparent_ctx, - &target_operation->ctx.sli_cryptoacc_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - target_operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - return( sli_crypto_transparent_hash_clone( - &source_operation->ctx.sli_crypto_transparent_ctx, - &target_operation->ctx.sli_crypto_transparent_ctx ) ); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - default: - (void) target_operation; - return( PSA_ERROR_BAD_STATE ); - } -} - -static inline psa_status_t psa_driver_wrapper_hash_update( - psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_hash_update( &operation->ctx.mbedtls_ctx, - input, input_length ) ); -#endif -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_hash_update( - &operation->ctx.test_driver_ctx, - input, input_length ) ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_hash_update( - &operation->ctx.sli_se_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_hash_update( - &operation->ctx.sli_cryptoacc_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_hash_update( - &operation->ctx.sli_crypto_transparent_ctx, - input, input_length ) ); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - default: - (void) input; - (void) input_length; - return( PSA_ERROR_BAD_STATE ); - } -} - -static inline psa_status_t psa_driver_wrapper_hash_finish( - psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_hash_finish( &operation->ctx.mbedtls_ctx, - hash, hash_size, hash_length ) ); -#endif -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_hash_finish( - &operation->ctx.test_driver_ctx, - hash, hash_size, hash_length ) ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_hash_finish( - &operation->ctx.sli_se_transparent_ctx, - hash, hash_size, hash_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_hash_finish( - &operation->ctx.sli_cryptoacc_transparent_ctx, - hash, hash_size, hash_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_hash_finish( - &operation->ctx.sli_crypto_transparent_ctx, - hash, hash_size, hash_length ) ); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - default: - (void) hash; - (void) hash_size; - (void) hash_length; - return( PSA_ERROR_BAD_STATE ); - } -} - -static inline psa_status_t psa_driver_wrapper_hash_abort( - psa_hash_operation_t *operation ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_HASH) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_hash_abort( &operation->ctx.mbedtls_ctx ) ); -#endif -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_hash_abort( - &operation->ctx.test_driver_ctx ) ); -#endif -#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_hash_abort( - &operation->ctx.sli_se_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_hash_abort( - &operation->ctx.sli_cryptoacc_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_hash_abort( - &operation->ctx.sli_crypto_transparent_ctx ) ); -#endif -#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ - default: - return( PSA_ERROR_BAD_STATE ); - } -} - -static inline psa_status_t psa_driver_wrapper_aead_encrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *plaintext, size_t plaintext_length, - uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_AEAD_DEVICE_SI91X) - status = sli_si91x_crypto_aead_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - nonce, - nonce_length, - additional_data, - additional_data_length, - plaintext, - plaintext_length, - ciphertext, - ciphertext_size, - ciphertext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return status; -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - return( mbedtls_psa_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ) ); - - /* Add cases for opaque driver here */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return ( sli_se_opaque_aead_encrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - plaintext, plaintext_length, - ciphertext, ciphertext_size, ciphertext_length ) ); -#endif -#if defined(SLI_AEAD_DEVICE_SI91X) -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - status = sli_si91x_crypto_aead_encrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - nonce, - nonce_length, - additional_data, - additional_data_length, - plaintext, - plaintext_length, - ciphertext, - ciphertext_size, - ciphertext_length ); - return status; -#endif -#endif - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_aead_decrypt( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *nonce, size_t nonce_length, - const uint8_t *additional_data, size_t additional_data_length, - const uint8_t *ciphertext, size_t ciphertext_length, - uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_AEAD_DEVICE_SI91X) - status = sli_si91x_crypto_aead_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - nonce, - nonce_length, - additional_data, - additional_data_length, - ciphertext, - ciphertext_length, - plaintext, - plaintext_size, - plaintext_length); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return status; -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - return( mbedtls_psa_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ) ); - - /* Add cases for opaque driver here */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return ( sli_se_opaque_aead_decrypt( - attributes, key_buffer, key_buffer_size, - alg, - nonce, nonce_length, - additional_data, additional_data_length, - ciphertext, ciphertext_length, - plaintext, plaintext_size, plaintext_length ) ); -#endif -#if defined(SLI_AEAD_DEVICE_SI91X) -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - status = sli_si91x_crypto_aead_decrypt( - attributes, - key_buffer, - key_buffer_size, - alg, - nonce, - nonce_length, - additional_data, - additional_data_length, - ciphertext, - ciphertext_length, - plaintext, - plaintext_size, - plaintext_length); - return status; -#endif -#endif - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( - psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - status = mbedtls_test_transparent_aead_encrypt_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - status = sli_se_transparent_aead_encrypt_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - status = sli_cryptoacc_transparent_aead_encrypt_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - status = sli_crypto_transparent_aead_encrypt_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - status = mbedtls_psa_aead_encrypt_setup( - &operation->ctx.mbedtls_ctx, attributes, - key_buffer, key_buffer_size, - alg ); - - return( status ); - - /* Add cases for opaque driver here */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_aead_encrypt_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( - psa_aead_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - status = mbedtls_test_transparent_aead_decrypt_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - status = sli_se_transparent_aead_decrypt_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - status = sli_cryptoacc_transparent_aead_decrypt_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - status = sli_crypto_transparent_aead_decrypt_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Fell through, meaning no accelerator supports this operation */ - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - status = mbedtls_psa_aead_decrypt_setup( - &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - return( status ); - - /* Add cases for opaque driver here */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_aead_decrypt_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_aead_set_nonce( - psa_aead_operation_t *operation, - const uint8_t *nonce, - size_t nonce_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_set_nonce( &operation->ctx.mbedtls_ctx, - nonce, - nonce_length ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_set_nonce( - &operation->ctx.transparent_test_driver_ctx, - nonce, nonce_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_set_nonce( - &operation->ctx.sli_se_transparent_ctx, - nonce, nonce_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_set_nonce( - &operation->ctx.sli_cryptoacc_transparent_ctx, - nonce, nonce_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_set_nonce( - &operation->ctx.sli_crypto_transparent_ctx, - nonce, nonce_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_set_nonce( - &operation->ctx.sli_se_opaque_ctx, - nonce, nonce_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)nonce; - (void)nonce_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_set_lengths( - psa_aead_operation_t *operation, - size_t ad_length, - size_t plaintext_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_set_lengths( &operation->ctx.mbedtls_ctx, - ad_length, - plaintext_length ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_set_lengths( - &operation->ctx.transparent_test_driver_ctx, - ad_length, plaintext_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_set_lengths( - &operation->ctx.sli_se_transparent_ctx, - ad_length, plaintext_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_set_lengths( - &operation->ctx.sli_cryptoacc_transparent_ctx, - ad_length, plaintext_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_set_lengths( - &operation->ctx.sli_crypto_transparent_ctx, - ad_length, plaintext_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_set_lengths( - &operation->ctx.sli_se_opaque_ctx, - ad_length, plaintext_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)ad_length; - (void)plaintext_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_update_ad( - psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_update_ad( &operation->ctx.mbedtls_ctx, - input, - input_length ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_update_ad( - &operation->ctx.transparent_test_driver_ctx, - input, input_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_update_ad( - &operation->ctx.sli_se_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_update_ad( - &operation->ctx.sli_cryptoacc_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_update_ad( - &operation->ctx.sli_crypto_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_update_ad( - &operation->ctx.sli_se_opaque_ctx, - input, input_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)input; - (void)input_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_update( - psa_aead_operation_t *operation, - const uint8_t *input, - size_t input_length, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_update( &operation->ctx.mbedtls_ctx, - input, input_length, - output, output_size, - output_length ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_update( - &operation->ctx.transparent_test_driver_ctx, - input, input_length, output, output_size, - output_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_update( - &operation->ctx.sli_se_transparent_ctx, - input, input_length, output, output_size, - output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_update( - &operation->ctx.sli_cryptoacc_transparent_ctx, - input, input_length, output, output_size, - output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_update( - &operation->ctx.sli_crypto_transparent_ctx, - input, input_length, output, output_size, - output_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_update( - &operation->ctx.sli_se_opaque_ctx, - input, input_length, output, output_size, - output_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)input; - (void)input_length; - (void)output; - (void)output_size; - (void)output_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_finish( - psa_aead_operation_t *operation, - uint8_t *ciphertext, - size_t ciphertext_size, - size_t *ciphertext_length, - uint8_t *tag, - size_t tag_size, - size_t *tag_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_finish( &operation->ctx.mbedtls_ctx, - ciphertext, - ciphertext_size, - ciphertext_length, tag, - tag_size, tag_length ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_finish( - &operation->ctx.transparent_test_driver_ctx, - ciphertext, ciphertext_size, - ciphertext_length, tag, tag_size, tag_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_finish( - &operation->ctx.sli_se_transparent_ctx, - ciphertext, ciphertext_size, - ciphertext_length, tag, tag_size, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_finish( - &operation->ctx.sli_cryptoacc_transparent_ctx, - ciphertext, ciphertext_size, - ciphertext_length, tag, tag_size, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_finish( - &operation->ctx.sli_crypto_transparent_ctx, - ciphertext, ciphertext_size, - ciphertext_length, tag, tag_size, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_finish( - &operation->ctx.sli_se_opaque_ctx, - ciphertext, ciphertext_size, - ciphertext_length, tag, tag_size, tag_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)ciphertext; - (void)ciphertext_size; - (void)ciphertext_length; - (void)tag; - (void)tag_size; - (void)tag_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_verify( - psa_aead_operation_t *operation, - uint8_t *plaintext, - size_t plaintext_size, - size_t *plaintext_length, - const uint8_t *tag, - size_t tag_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - { - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - uint8_t check_tag[PSA_AEAD_TAG_MAX_SIZE]; - size_t check_tag_length; - - status = mbedtls_psa_aead_finish( &operation->ctx.mbedtls_ctx, - plaintext, - plaintext_size, - plaintext_length, - check_tag, - sizeof( check_tag ), - &check_tag_length ); - - if( status == PSA_SUCCESS ) - { - if( tag_length != check_tag_length || - mbedtls_ct_memcmp( tag, check_tag, tag_length ) - != 0 ) - status = PSA_ERROR_INVALID_SIGNATURE; - } - - mbedtls_platform_zeroize( check_tag, sizeof( check_tag ) ); - - return( status ); - } - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_verify( - &operation->ctx.transparent_test_driver_ctx, - plaintext, plaintext_size, - plaintext_length, tag, tag_length ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_verify( - &operation->ctx.sli_se_transparent_ctx, - plaintext, plaintext_size, - plaintext_length, tag, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_verify( - &operation->ctx.sli_cryptoacc_transparent_ctx, - plaintext, plaintext_size, - plaintext_length, tag, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_verify( - &operation->ctx.sli_crypto_transparent_ctx, - plaintext, plaintext_size, - plaintext_length, tag, tag_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_verify( - &operation->ctx.sli_se_opaque_ctx, - plaintext, plaintext_size, - plaintext_length, tag, tag_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - (void)plaintext; - (void)plaintext_size; - (void)plaintext_length; - (void)tag; - (void)tag_length; - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -static inline psa_status_t psa_driver_wrapper_aead_abort( - psa_aead_operation_t *operation ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_AEAD) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_aead_abort( &operation->ctx.mbedtls_ctx ) ); - -#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_aead_abort( - &operation->ctx.transparent_test_driver_ctx ) ); - - /* Add cases for opaque driver here */ - -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_aead_abort( - &operation->ctx.sli_se_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_aead_abort( - &operation->ctx.sli_cryptoacc_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_aead_abort( - &operation->ctx.sli_crypto_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_aead_abort( - &operation->ctx.sli_se_opaque_ctx ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - } - - return( PSA_ERROR_INVALID_ARGUMENT ); -} - -/* - * MAC functions - */ -static inline psa_status_t psa_driver_wrapper_mac_compute( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MAC_DEVICE_SI91X) - status = sli_si91x_crypto_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, mac, mac_size, mac_length - ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* SLI_MAC_DEVICE_SI91X */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - /* Fell through, meaning no accelerator supports this operation */ - status = mbedtls_psa_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - return( PSA_ERROR_NOT_SUPPORTED ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ); - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return ( sli_se_opaque_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: - return ( sli_cryptoacc_opaque_mac_compute( - attributes, key_buffer, key_buffer_size, alg, - input, input_length, - mac, mac_size, mac_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - (void) input; - (void) input_length; - (void) mac; - (void) mac_size; - (void) mac_length; - (void) status; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_sign_setup( - psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_mac_sign_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_mac_sign_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_mac_sign_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_mac_sign_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - /* Fell through, meaning no accelerator supports this operation */ - status = mbedtls_psa_mac_sign_setup( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - return( PSA_ERROR_NOT_SUPPORTED ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_mac_sign_setup( - &operation->ctx.opaque_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; - - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_mac_sign_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void) status; - (void) operation; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_verify_setup( - psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_mac_verify_setup( - &operation->ctx.transparent_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_mac_verify_setup( - &operation->ctx.sli_se_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_mac_verify_setup( - &operation->ctx.sli_cryptoacc_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - status = sli_crypto_transparent_mac_verify_setup( - &operation->ctx.sli_crypto_transparent_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - /* Declared with fallback == true */ - if( status == PSA_SUCCESS ) - operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - /* Fell through, meaning no accelerator supports this operation */ - status = mbedtls_psa_mac_verify_setup( &operation->ctx.mbedtls_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - return( PSA_ERROR_NOT_SUPPORTED ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - status = mbedtls_test_opaque_mac_verify_setup( - &operation->ctx.opaque_test_driver_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; - - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_mac_verify_setup( - &operation->ctx.sli_se_opaque_ctx, - attributes, - key_buffer, key_buffer_size, - alg ); - if( status == PSA_SUCCESS ) - operation->id = SLI_SE_OPAQUE_DRIVER_ID; - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - (void) status; - (void) operation; - (void) key_buffer; - (void) key_buffer_size; - (void) alg; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_update( - psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_mac_update( &operation->ctx.mbedtls_ctx, - input, input_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_mac_update( - &operation->ctx.transparent_test_driver_ctx, - input, input_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_mac_update( - &operation->ctx.opaque_test_driver_ctx, - input, input_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_mac_update( - &operation->ctx.sli_se_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_mac_update( - &operation->ctx.sli_cryptoacc_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_mac_update( - &operation->ctx.sli_crypto_transparent_ctx, - input, input_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_mac_update( - &operation->ctx.sli_se_opaque_ctx, - input, input_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) input; - (void) input_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_sign_finish( - psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_mac_sign_finish( &operation->ctx.mbedtls_ctx, - mac, mac_size, mac_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_mac_sign_finish( - &operation->ctx.transparent_test_driver_ctx, - mac, mac_size, mac_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_mac_sign_finish( - &operation->ctx.opaque_test_driver_ctx, - mac, mac_size, mac_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_mac_sign_finish( - &operation->ctx.sli_se_transparent_ctx, - mac, mac_size, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_mac_sign_finish( - &operation->ctx.sli_cryptoacc_transparent_ctx, - mac, mac_size, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_mac_sign_finish( - &operation->ctx.sli_crypto_transparent_ctx, - mac, mac_size, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_mac_sign_finish( - &operation->ctx.sli_se_opaque_ctx, - mac, mac_size, mac_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) mac; - (void) mac_size; - (void) mac_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_verify_finish( - psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_mac_verify_finish( &operation->ctx.mbedtls_ctx, - mac, mac_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_mac_verify_finish( - &operation->ctx.transparent_test_driver_ctx, - mac, mac_length ) ); - - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_mac_verify_finish( - &operation->ctx.opaque_test_driver_ctx, - mac, mac_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_mac_verify_finish( - &operation->ctx.sli_se_transparent_ctx, - mac, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_mac_verify_finish( - &operation->ctx.sli_cryptoacc_transparent_ctx, - mac, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_mac_verify_finish( - &operation->ctx.sli_crypto_transparent_ctx, - mac, mac_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_mac_verify_finish( - &operation->ctx.sli_se_opaque_ctx, - mac, mac_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) mac; - (void) mac_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_mac_abort( - psa_mac_operation_t *operation ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_MAC) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_mac_abort( &operation->ctx.mbedtls_ctx ) ); -#endif /* MBEDTLS_PSA_BUILTIN_MAC */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_mac_abort( - &operation->ctx.transparent_test_driver_ctx ) ); - case MBEDTLS_TEST_OPAQUE_DRIVER_ID: - return( mbedtls_test_opaque_mac_abort( - &operation->ctx.opaque_test_driver_ctx ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - case SLI_SE_TRANSPARENT_DRIVER_ID: - return( sli_se_transparent_mac_abort( - &operation->ctx.sli_se_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: - return( sli_cryptoacc_transparent_mac_abort( - &operation->ctx.sli_cryptoacc_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_S1) - case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: - return( sli_crypto_transparent_mac_abort( - &operation->ctx.sli_crypto_transparent_ctx ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case SLI_SE_OPAQUE_DRIVER_ID: - return( sli_se_opaque_mac_abort( - &operation->ctx.sli_se_opaque_ctx ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -/* - * Asymmetric cryptography - */ -static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, const uint8_t *input, - size_t input_length, const uint8_t *salt, size_t salt_length, - uint8_t *output, size_t output_size, size_t *output_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_asymmetric_encrypt( attributes, - key_buffer, key_buffer_size, alg, input, input_length, - salt, salt_length, output, output_size, - output_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - return( mbedtls_psa_asymmetric_encrypt( attributes, - key_buffer, key_buffer_size, alg, input, input_length, - salt, salt_length, output, output_size, output_length ) - ); - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_asymmetric_encrypt( attributes, - key_buffer, key_buffer_size, alg, input, input_length, - salt, salt_length, output, output_size, output_length ) - ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)input; - (void)input_length; - (void)salt; - (void)salt_length; - (void)output; - (void)output_size; - (void)output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( - const psa_key_attributes_t *attributes, const uint8_t *key_buffer, - size_t key_buffer_size, psa_algorithm_t alg, const uint8_t *input, - size_t input_length, const uint8_t *salt, size_t salt_length, - uint8_t *output, size_t output_size, size_t *output_length ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_asymmetric_decrypt( attributes, - key_buffer, key_buffer_size, alg, input, input_length, - salt, salt_length, output, output_size, - output_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - return( mbedtls_psa_asymmetric_decrypt( attributes, - key_buffer, key_buffer_size, alg,input, input_length, - salt, salt_length, output, output_size, - output_length ) ); - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_asymmetric_decrypt( attributes, - key_buffer, key_buffer_size, alg, input, input_length, - salt, salt_length, output, output_size, - output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - /* Key is declared with a lifetime not known to us */ - (void)status; - (void)key_buffer; - (void)key_buffer_size; - (void)alg; - (void)input; - (void)input_length; - (void)salt; - (void)salt_length; - (void)output; - (void)output_size; - (void)output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_key_agreement( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *peer_key, - size_t peer_key_length, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length - ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = - mbedtls_test_transparent_key_agreement( attributes, - key_buffer, key_buffer_size, alg, peer_key, - peer_key_length, shared_secret, shared_secret_size, - shared_secret_length ); - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) - if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && - PSA_ALG_IS_ECDH(alg) && - PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && - attributes->core.bits == 256 ) - { - status = p256_transparent_key_agreement( attributes, - key_buffer, - key_buffer_size, - alg, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - if( status != PSA_ERROR_NOT_SUPPORTED) - return( status ); - } -#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_key_agreement( alg, - attributes, - key_buffer, - key_buffer_size, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_key_agreement( alg, - attributes, - key_buffer, - key_buffer_size, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#if defined(SLI_ECDH_DEVICE_SI91X) - status = sli_si91x_psa_ecdh_key_agreement( alg, - attributes, - key_buffer, - key_buffer_size, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - /* Software Fallback */ - status = psa_key_agreement_raw_builtin( attributes, - key_buffer, - key_buffer_size, - alg, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - return( status ); -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: - return( mbedtls_test_opaque_key_agreement( attributes, - key_buffer, key_buffer_size, alg, peer_key, - peer_key_length, shared_secret, shared_secret_size, - shared_secret_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - status = sli_se_opaque_key_agreement( alg, - attributes, - key_buffer, - key_buffer_size, - peer_key, - peer_key_length, - shared_secret, - shared_secret_size, - shared_secret_length ); - // Cannot have fallback for opaque drivers: - return ( status ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - - default: - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - (void) peer_key; - (void) peer_key_length; - (void) shared_secret; - (void) shared_secret_size; - (void) shared_secret_length; - return( PSA_ERROR_NOT_SUPPORTED ); - - } -} - -static inline psa_status_t psa_driver_wrapper_pake_setup( - psa_pake_operation_t *operation, - const psa_crypto_driver_pake_inputs_t *inputs ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - psa_key_location_t location = - PSA_KEY_LIFETIME_GET_LOCATION( psa_get_key_lifetime( &inputs->attributes ) ); - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ - status = PSA_ERROR_NOT_SUPPORTED; -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - status = mbedtls_test_transparent_pake_setup( - &operation->data.ctx.transparent_test_driver_ctx, - inputs ); - if( status == PSA_SUCCESS ) - operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) - status = mbedtls_psa_pake_setup( &operation->data.ctx.mbedtls_ctx, - inputs ); - if( status == PSA_SUCCESS ) - operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; -#endif - return status; - /* Add cases for opaque driver here */ - default: - /* Key is declared with a lifetime not known to us */ - (void)operation; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_pake_output( - psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_pake_output( &operation->data.ctx.mbedtls_ctx, step, - output, output_size, output_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_pake_output( - &operation->data.ctx.transparent_test_driver_ctx, - step, output, output_size, output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) step; - (void) output; - (void) output_size; - (void) output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_pake_input( - psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - const uint8_t *input, - size_t input_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_pake_input( &operation->data.ctx.mbedtls_ctx, - step, input, - input_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_pake_input( - &operation->data.ctx.transparent_test_driver_ctx, - step, - input, input_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) step; - (void) input; - (void) input_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_pake_get_implicit_key( - psa_pake_operation_t *operation, - uint8_t *output, size_t output_size, - size_t *output_length ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_pake_get_implicit_key( &operation->data.ctx.mbedtls_ctx, - output, output_size, output_length ) ); -#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_pake_get_implicit_key( - &operation->data.ctx.transparent_test_driver_ctx, - output, output_size, output_length ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) output; - (void) output_size; - (void) output_length; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -static inline psa_status_t psa_driver_wrapper_pake_abort( - psa_pake_operation_t * operation ) -{ - switch( operation->id ) - { -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) - case PSA_CRYPTO_MBED_TLS_DRIVER_ID: - return( mbedtls_psa_pake_abort( &operation->data.ctx.mbedtls_ctx ) ); -#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ - -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#if defined(PSA_CRYPTO_DRIVER_TEST) - case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: - return( mbedtls_test_transparent_pake_abort( - &operation->data.ctx.transparent_test_driver_ctx ) ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * Functions to delegate cryptographic operations to an available + * and appropriate accelerator. + * Warning: This file is now auto-generated. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* BEGIN-common headers */ +#include "common.h" +#include "psa_crypto_aead.h" +#include "psa_crypto_cipher.h" +#include "psa_crypto_core.h" +#include "psa_crypto_driver_wrappers_no_static.h" +#include "psa_crypto_hash.h" +#include "psa_crypto_mac.h" +#include "psa_crypto_pake.h" +#include "psa_crypto_rsa.h" + +#include "mbedtls/platform.h" +#include "mbedtls/constant_time.h" +/* END-common headers */ + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +/* BEGIN-driver headers */ +/* Headers for mbedtls_test opaque driver */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#include "test/drivers/test_driver.h" + +#endif +/* Headers for mbedtls_test transparent driver */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#include "test/drivers/test_driver.h" + +#endif +/* Headers for p256 transparent driver */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) +#include "../3rdparty/p256-m/p256-m_driver_entrypoints.h" + +#endif + + +/* SiLabs Driver Headers */ +#include "sli_psa_driver_features.h" + +#include + +#if defined(SLI_MBEDTLS_DEVICE_HSE) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" +#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ + +#if defined(SLI_MBEDTLS_DEVICE_VSE) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) +#include "sli_cryptoacc_opaque_types.h" +#include "sli_cryptoacc_opaque_functions.h" +#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S1) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_crypto_transparent_types.h" +#include "sli_crypto_transparent_functions.h" +#endif + +#if defined(SLI_MBEDTLS_DEVICE_SI91X) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_si91x_crypto_driver_functions.h" +#endif + +#ifdef SLI_SECURE_KEY_STORAGE_DEVICE_SI91X +#include "sl_si91x_psa_wrap.h" +#endif /* Secure key storage driver **/ + +/* END-driver headers */ + +/* Auto-generated values depending on which drivers are registered. + * ID 0 is reserved for unallocated operations. + * ID 1 is reserved for the Mbed TLS software driver. */ +/* BEGIN-driver id definition */ +#define PSA_CRYPTO_MBED_TLS_DRIVER_ID (1) +#define MBEDTLS_TEST_OPAQUE_DRIVER_ID (2) +#define MBEDTLS_TEST_TRANSPARENT_DRIVER_ID (3) +#define P256_TRANSPARENT_DRIVER_ID (4) + + +/* SiLabs Driver IDs */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#define SLI_SE_TRANSPARENT_DRIVER_ID (4) +#define SLI_SE_OPAQUE_DRIVER_ID (5) +#define SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID (6) +#define SLI_CRYPTO_TRANSPARENT_DRIVER_ID (7) +#endif + +/* END-driver id */ + +/* BEGIN-Common Macro definitions */ + +/* END-Common Macro definitions */ + +/* Support the 'old' SE interface when asked to */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/* PSA_CRYPTO_DRIVER_PRESENT is defined when either a new-style or old-style + * SE driver is present, to avoid unused argument errors at compile time. */ +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#include "psa_crypto_se.h" +#endif + +static inline psa_status_t psa_driver_wrapper_init( void ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + status = psa_init_all_se_drivers( ); + if( status != PSA_SUCCESS ) + return( status ); +#endif + +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_init( ); + if( status != PSA_SUCCESS ) + return( status ); + + status = mbedtls_test_opaque_init( ); + if( status != PSA_SUCCESS ) + return( status ); +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_driver_init(); + if( status != PSA_SUCCESS ) + return( status ); +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + status = sli_se_opaque_driver_init(); + if( status != PSA_SUCCESS ) + return( status ); +#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_driver_init(); + if( status != PSA_SUCCESS ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_driver_init(); + if( status != PSA_SUCCESS ) + return( status ); +#endif +#if defined(SLI_TRNG_DEVICE_SI91X) + status = sli_si91x_crypto_trng_init(); + if( status != PSA_SUCCESS ) + return( status ); +#endif + + (void) status; + return( PSA_SUCCESS ); +} + +static inline void psa_driver_wrapper_free( void ) +{ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* Unregister all secure element drivers, so that we restart from + * a pristine state. */ + psa_unregister_all_se_drivers( ); +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + +#if defined(PSA_CRYPTO_DRIVER_TEST) + mbedtls_test_transparent_free( ); + mbedtls_test_opaque_free( ); +#endif +} + +/* Start delegation functions */ +static inline psa_status_t psa_driver_wrapper_sign_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_signature_sign_message( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_sign_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + break; + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_signature_sign_message( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); + break; +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_sign_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length ); + /* No fallback for opaque */ + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + break; + } + + return( psa_sign_message_builtin( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_size, + signature_length ) ); +} + +static inline psa_status_t psa_driver_wrapper_verify_message( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *signature, + size_t signature_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_signature_verify_message( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_verify_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + break; + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_signature_verify_message( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_verify_message( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length ); + /* No fallback for opaque */ + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + break; + } + + return( psa_verify_message_builtin( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + signature, + signature_length ) ); +} + +static inline psa_status_t psa_driver_wrapper_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length ) +{ + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + if( drv->asymmetric == NULL || + drv->asymmetric->p_sign == NULL ) + { + /* Key is defined in SE, but we have no way to exercise it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->asymmetric->p_sign( + drv_context, *( (psa_key_slot_number_t *)key_buffer ), + alg, hash, hash_length, + signature, signature_size, signature_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_signature_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) + if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && + PSA_ALG_IS_ECDSA(alg) && + !PSA_ALG_ECDSA_IS_DETERMINISTIC( alg ) && + PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && + attributes->core.bits == 256 ) + { + status = p256_transparent_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); + } +#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Fell through, meaning no accelerator supports this operation */ + return( psa_sign_hash_builtin( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ) ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_signature_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_sign_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + /* No fallback for opaque */ + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length ) +{ + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + if( drv->asymmetric == NULL || + drv->asymmetric->p_verify == NULL ) + { + /* Key is defined in SE, but we have no way to exercise it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->asymmetric->p_verify( + drv_context, *( (psa_key_slot_number_t *)key_buffer ), + alg, hash, hash_length, + signature, signature_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_signature_verify_hash( + attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined (MBEDTLS_PSA_P256M_DRIVER_ENABLED) + if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && + PSA_ALG_IS_ECDSA(alg) && + !PSA_ALG_ECDSA_IS_DETERMINISTIC( alg ) && + PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && + attributes->core.bits == 256 ) + { + status = p256_transparent_verify_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); + } +#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_verify_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_MBEDTLS_DEVICE_HSE */ +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_verify_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_MBEDTLS_DEVICE_VSE */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + return( psa_verify_hash_builtin( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ) ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_signature_verify_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_verify_hash( attributes, + key_buffer, + key_buffer_size, + alg, + hash, + hash_length, + signature, + signature_length ); + /* No fallback for opaque */ + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline uint32_t psa_driver_wrapper_sign_hash_get_num_ops( + psa_sign_hash_interruptible_operation_t *operation ) +{ + switch( operation->id ) + { + /* If uninitialised, return 0, as no work can have been done. */ + case 0: + return 0; + + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return(mbedtls_psa_sign_hash_get_num_ops(&operation->ctx.mbedtls_ctx)); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + /* Can't happen (see discussion in #8271) */ + return 0; +} + +static inline uint32_t psa_driver_wrapper_verify_hash_get_num_ops( + psa_verify_hash_interruptible_operation_t *operation ) +{ + switch( operation->id ) + { + /* If uninitialised, return 0, as no work can have been done. */ + case 0: + return 0; + + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return (mbedtls_psa_verify_hash_get_num_ops(&operation->ctx.mbedtls_ctx)); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + } + + /* Can't happen (see discussion in #8271) */ + return 0; +} + +static inline psa_status_t psa_driver_wrapper_sign_hash_start( + psa_sign_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length ) +{ + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( + attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + + /* Add test driver tests here */ + + /* Declared with fallback == true */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + return( mbedtls_psa_sign_hash_start( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length ) ); + break; + + /* Add cases for opaque driver here */ + + default: + /* Key is declared with a lifetime not known to us */ + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_sign_hash_complete( + psa_sign_hash_interruptible_operation_t *operation, + uint8_t *signature, size_t signature_size, + size_t *signature_length ) +{ + switch( operation->id ) + { + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_sign_hash_complete( &operation->ctx.mbedtls_ctx, + signature, signature_size, + signature_length ) ); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + ( void ) signature; + ( void ) signature_size; + ( void ) signature_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_sign_hash_abort( + psa_sign_hash_interruptible_operation_t *operation ) +{ + switch( operation->id ) + { + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_sign_hash_abort( &operation->ctx.mbedtls_ctx ) ); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_verify_hash_start( + psa_verify_hash_interruptible_operation_t *operation, + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, + const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length ) +{ + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( + attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + + /* Add test driver tests here */ + + /* Declared with fallback == true */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + return( mbedtls_psa_verify_hash_start( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, key_buffer_size, + alg, hash, hash_length, + signature, signature_length + ) ); + break; + + /* Add cases for opaque driver here */ + + default: + /* Key is declared with a lifetime not known to us */ + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_verify_hash_complete( + psa_verify_hash_interruptible_operation_t *operation ) +{ + switch( operation->id ) + { + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_verify_hash_complete( + &operation->ctx.mbedtls_ctx + ) ); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_verify_hash_abort( + psa_verify_hash_interruptible_operation_t *operation ) +{ + switch( operation->id ) + { + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_verify_hash_abort( &operation->ctx.mbedtls_ctx + ) ); + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + /* Add test driver tests here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +/** Calculate the key buffer size required to store the key material of a key + * associated with an opaque driver from input key data. + * + * \param[in] attributes The key attributes + * \param[in] data The input key data. + * \param[in] data_length The input data length. + * \param[out] key_buffer_size Minimum buffer size to contain the key material. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + */ +static inline psa_status_t psa_driver_wrapper_get_key_buffer_size_from_key_data( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + size_t *key_buffer_size ) +{ + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + psa_key_type_t key_type = attributes->core.type; + + *key_buffer_size = 0; + switch( location ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + *key_buffer_size = mbedtls_test_opaque_size_function( key_type, + PSA_BYTES_TO_BITS( data_length ) ); + return( ( *key_buffer_size != 0 ) ? + PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + *key_buffer_size = data_length; + return( psa_driver_wrapper_get_key_buffer_size( attributes, key_buffer_size ) ); +#endif +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + *key_buffer_size = data_length; + return( ( *key_buffer_size != 0 ) ? + PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); + break; +#endif + + default: + (void)key_type; + (void)data; + (void)data_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION(attributes->core.lifetime); + + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + size_t pubkey_length = 0; /* We don't support this feature yet */ + if( drv->key_management == NULL || + drv->key_management->p_generate == NULL ) + { + /* Key is defined as being in SE, but we have no way to generate it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->key_management->p_generate( + drv_context, + *( (psa_key_slot_number_t *)key_buffer ), + attributes, NULL, 0, &pubkey_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + /* Transparent drivers are limited to generating asymmetric keys */ + if( PSA_KEY_TYPE_IS_ASYMMETRIC( attributes->core.type ) ) + { + /* Cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_generate_key( + attributes, key_buffer, key_buffer_size, + key_buffer_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) + if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && + attributes->core.type == PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_FAMILY_SECP_R1) && + attributes->core.bits == 256 ) + { + status = p256_transparent_generate_key( attributes, + key_buffer, + key_buffer_size, + key_buffer_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; + } + +#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_generate_key( attributes, + key_buffer, + key_buffer_size, + key_buffer_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_generate_key( attributes, + key_buffer, + key_buffer_size, + key_buffer_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; +#endif +#if defined(SLI_ECDH_DEVICE_SI91X) + status = sli_si91x_psa_generate_key_ecdh( attributes, + key_buffer, + key_buffer_size, + key_buffer_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; +#endif // SLI_ECDH_DEVICE_SI91X + } +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Software fallback */ + status = psa_generate_key_internal( + attributes, key_buffer, key_buffer_size, key_buffer_length ); + break; + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_generate_key( + attributes, key_buffer, key_buffer_size, key_buffer_length ); + break; +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + // Call opaque driver API + status = sli_se_opaque_generate_key( attributes, + key_buffer, + key_buffer_size, + key_buffer_length ); + /* No fallback for opaque drivers */ + return status; +#endif +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + if( PSA_KEY_TYPE_IS_ASYMMETRIC( attributes->core.type ) ) + { + /* Software fallback for Si91x Devices */ + status = psa_generate_key_internal( + attributes, key_buffer, key_buffer_size, key_buffer_length ); + if( status == PSA_SUCCESS ){ + status = sli_si91x_crypto_wrap_key(key_buffer, + *key_buffer_length, + SL_SI91X_WRAP_IV_CBC_MODE, + WRAP_IV); + } + } else { + /* symmetric key generation */ + status = sli_si91x_crypto_generate_symm_key(key_buffer, + key_buffer_size, + SL_SI91X_WRAP_IV_CBC_MODE, + WRAP_IV); + } + return status; + break; +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + /* Key is declared with a lifetime not known to us */ + status = PSA_ERROR_INVALID_ARGUMENT; + break; + } + + return( status ); +} + +static inline psa_status_t psa_driver_wrapper_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length, + size_t *bits ) +{ + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( + psa_get_key_lifetime( attributes ) ); + + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + if( drv->key_management == NULL || + drv->key_management->p_import == NULL ) + return( PSA_ERROR_NOT_SUPPORTED ); + + /* The driver should set the number of key bits, however in + * case it doesn't, we initialize bits to an invalid value. */ + *bits = PSA_MAX_KEY_BITS + 1; + status = drv->key_management->p_import( + drv_context, + *( (psa_key_slot_number_t *)key_buffer ), + attributes, data, data_length, bits ); + + if( status != PSA_SUCCESS ) + return( status ); + + if( (*bits) > PSA_MAX_KEY_BITS ) + return( PSA_ERROR_NOT_SUPPORTED ); + + return( PSA_SUCCESS ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + status = mbedtls_test_transparent_import_key + (attributes, + data, + data_length, + key_buffer, + key_buffer_size, + key_buffer_length, + bits + ); + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + +#if (defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) ) + status = p256_transparent_import_key + (attributes, + data, + data_length, + key_buffer, + key_buffer_size, + key_buffer_length, + bits + ); + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + + +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_import_key( attributes, + data, data_length, + key_buffer, + key_buffer_size, + key_buffer_length, + bits ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_import_key( attributes, + data, data_length, + key_buffer, + key_buffer_size, + key_buffer_length, + bits ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + return( psa_import_key_into_slot( attributes, + data, data_length, + key_buffer, key_buffer_size, + key_buffer_length, bits ) ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + case 0x7fffff: + return( mbedtls_test_opaque_import_key + (attributes, + data, + data_length, + key_buffer, + key_buffer_size, + key_buffer_length, + bits + )); +#endif + + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return( sli_se_opaque_import_key( + attributes, + data, data_length, + key_buffer, key_buffer_size, + key_buffer_length, bits ) ); +#endif +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + status = psa_import_key_into_slot( attributes, + data, data_length, + key_buffer, key_buffer_size, + key_buffer_length, bits ); + if( status == PSA_SUCCESS ){ + status = sli_si91x_crypto_wrap_key(key_buffer, + *key_buffer_length, + SL_SI91X_WRAP_IV_CBC_MODE, + WRAP_IV); + } + return( status ); + break; +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } + +} + +static inline psa_status_t psa_driver_wrapper_export_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length ) + +{ + + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( + psa_get_key_lifetime( attributes ) ); + + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + if( ( drv->key_management == NULL ) || + ( drv->key_management->p_export == NULL ) ) + { + return( PSA_ERROR_NOT_SUPPORTED ); + } + + return( drv->key_management->p_export( + drv_context, + *( (psa_key_slot_number_t *)key_buffer ), + data, data_size, data_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + return( psa_export_key_internal( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ) ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + case 0x7fffff: + return( mbedtls_test_opaque_export_key + (attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length + )); +#endif + + +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + // We are on a vault device, call opaque driver + return( sli_se_opaque_export_key( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ) ); +#endif +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + return( psa_export_key_internal( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ) ); + break; +#endif + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } + +} + +static inline psa_status_t psa_driver_wrapper_copy_key( + psa_key_attributes_t *attributes, + const uint8_t *source_key, size_t source_key_length, + uint8_t *target_key_buffer, size_t target_key_buffer_size, + size_t *target_key_buffer_length ) +{ + + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + /* Copying to a secure element is not implemented yet. */ + return( PSA_ERROR_NOT_SUPPORTED ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch( location ) + { +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + case 0x7fffff: + return( mbedtls_test_opaque_copy_key + (attributes, + source_key, + source_key_length, + target_key_buffer, + target_key_buffer_size, + target_key_buffer_length + )); +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE) \ + && defined(SLI_PSA_DRIVER_FEATURE_WRAPPED_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return sli_se_opaque_copy_key(attributes, + source_key, + source_key_length, + target_key_buffer, + target_key_buffer_size, + target_key_buffer_length); +#endif + +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void)source_key; + (void)source_key_length; + (void)target_key_buffer; + (void)target_key_buffer_size; + (void)target_key_buffer_length; + status = PSA_ERROR_INVALID_ARGUMENT; + } + return( status ); + +} + +/* + * Cipher functions + */ +static inline psa_status_t psa_driver_wrapper_cipher_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *iv, + size_t iv_length, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_cipher_encrypt( attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_CIPHER_DEVICE_SI91X) + status = sli_si91x_crypto_cipher_encrypt( attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_CIPHER_DEVICE_SI91X */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + return( mbedtls_psa_cipher_encrypt( attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ) ); +#else + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_cipher_encrypt( attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return ( sli_se_opaque_cipher_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + iv, + iv_length, + input, + input_length, + output, + output_size, + output_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)iv; + (void)iv_length; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_cipher_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_cipher_decrypt( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_CIPHER_DEVICE_SI91X) + status = sli_si91x_crypto_cipher_decrypt( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_CIPHER_DEVICE_SI91X */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + return( mbedtls_psa_cipher_decrypt( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ) ); +#else + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_cipher_decrypt( attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return ( sli_se_opaque_cipher_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + input, + input_length, + output, + output_size, + output_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_cipher_encrypt_setup( + psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_cipher_encrypt_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_cipher_encrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_cipher_encrypt_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_cipher_encrypt_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + /* Fell through, meaning no accelerator supports this operation */ + status = mbedtls_psa_cipher_encrypt_setup( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + return( PSA_ERROR_NOT_SUPPORTED ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_cipher_encrypt_setup( + &operation->ctx.opaque_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_cipher_encrypt_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)operation; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_cipher_decrypt_setup( + psa_cipher_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_cipher_decrypt_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_cipher_decrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_cipher_decrypt_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_cipher_decrypt_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + /* Fell through, meaning no accelerator supports this operation */ + status = mbedtls_psa_cipher_decrypt_setup( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + + return( status ); +#else /* MBEDTLS_PSA_BUILTIN_CIPHER */ + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_cipher_decrypt_setup( + &operation->ctx.opaque_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_cipher_decrypt_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, + key_buffer, + key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)operation; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_cipher_set_iv( + psa_cipher_operation_t *operation, + const uint8_t *iv, + size_t iv_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_cipher_set_iv( &operation->ctx.mbedtls_ctx, + iv, + iv_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_cipher_set_iv( + &operation->ctx.transparent_test_driver_ctx, + iv, iv_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_cipher_set_iv( + &operation->ctx.opaque_test_driver_ctx, + iv, iv_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_cipher_set_iv( + &operation->ctx.sli_se_transparent_ctx, + iv, iv_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_cipher_set_iv( + &operation->ctx.sli_cryptoacc_transparent_ctx, + iv, iv_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_cipher_set_iv( + &operation->ctx.sli_crypto_transparent_ctx, + iv, iv_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_cipher_set_iv( + &operation->ctx.sli_se_opaque_ctx, + iv, iv_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)iv; + (void)iv_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_cipher_update( + psa_cipher_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_cipher_update( &operation->ctx.mbedtls_ctx, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_cipher_update( + &operation->ctx.transparent_test_driver_ctx, + input, input_length, + output, output_size, output_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_cipher_update( + &operation->ctx.opaque_test_driver_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_cipher_update( + &operation->ctx.sli_se_transparent_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_cipher_update( + &operation->ctx.sli_cryptoacc_transparent_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_cipher_update( + &operation->ctx.sli_crypto_transparent_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_cipher_update( + &operation->ctx.sli_se_opaque_ctx, + input, input_length, + output, output_size, output_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_cipher_finish( + psa_cipher_operation_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_cipher_finish( &operation->ctx.mbedtls_ctx, + output, + output_size, + output_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_cipher_finish( + &operation->ctx.transparent_test_driver_ctx, + output, output_size, output_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_cipher_finish( + &operation->ctx.opaque_test_driver_ctx, + output, output_size, output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_cipher_finish( + &operation->ctx.sli_se_transparent_ctx, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_cipher_finish( + &operation->ctx.sli_cryptoacc_transparent_ctx, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_cipher_finish( + &operation->ctx.sli_crypto_transparent_ctx, + output, output_size, output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_cipher_finish( + &operation->ctx.sli_se_opaque_ctx, + output, output_size, output_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)output; + (void)output_size; + (void)output_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_cipher_abort( + psa_cipher_operation_t *operation ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_CIPHER) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_cipher_abort( &operation->ctx.mbedtls_ctx ) ); +#endif /* MBEDTLS_PSA_BUILTIN_CIPHER */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + status = mbedtls_test_transparent_cipher_abort( + &operation->ctx.transparent_test_driver_ctx ); + mbedtls_platform_zeroize( + &operation->ctx.transparent_test_driver_ctx, + sizeof( operation->ctx.transparent_test_driver_ctx ) ); + return( status ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + status = mbedtls_test_opaque_cipher_abort( + &operation->ctx.opaque_test_driver_ctx ); + mbedtls_platform_zeroize( + &operation->ctx.opaque_test_driver_ctx, + sizeof( operation->ctx.opaque_test_driver_ctx ) ); + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_cipher_abort( + &operation->ctx.sli_se_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_cipher_abort( + &operation->ctx.sli_cryptoacc_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_cipher_abort( + &operation->ctx.sli_crypto_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_cipher_abort( + &operation->ctx.sli_se_opaque_ctx ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +/* + * Hashing functions + */ +static inline psa_status_t psa_driver_wrapper_hash_compute( + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* Try accelerators first */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_SHA_DEVICE_SI91X) + status = sli_si91x_crypto_hash_compute( + alg, input, input_length, hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + + /* If software fallback is compiled in, try fallback */ +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + status = mbedtls_psa_hash_compute( alg, input, input_length, + hash, hash_size, hash_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + (void) status; + (void) alg; + (void) input; + (void) input_length; + (void) hash; + (void) hash_size; + (void) hash_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +} + +static inline psa_status_t psa_driver_wrapper_hash_setup( + psa_hash_operation_t *operation, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* Try setup on accelerators first */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_hash_setup( + &operation->ctx.test_driver_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_hash_setup( + &operation->ctx.sli_se_transparent_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_hash_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_hash_setup( + &operation->ctx.sli_crypto_transparent_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif + + /* If software fallback is compiled in, try fallback */ +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + status = mbedtls_psa_hash_setup( &operation->ctx.mbedtls_ctx, alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + /* Nothing left to try if we fall through here */ + (void) status; + (void) operation; + (void) alg; + return( PSA_ERROR_NOT_SUPPORTED ); +} + +static inline psa_status_t psa_driver_wrapper_hash_clone( + const psa_hash_operation_t *source_operation, + psa_hash_operation_t *target_operation ) +{ + switch( source_operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + target_operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + return( mbedtls_psa_hash_clone( &source_operation->ctx.mbedtls_ctx, + &target_operation->ctx.mbedtls_ctx ) ); +#endif +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + target_operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + return( mbedtls_test_transparent_hash_clone( + &source_operation->ctx.test_driver_ctx, + &target_operation->ctx.test_driver_ctx ) ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + target_operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + return( sli_se_transparent_hash_clone( + &source_operation->ctx.sli_se_transparent_ctx, + &target_operation->ctx.sli_se_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + target_operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + return( sli_cryptoacc_transparent_hash_clone( + &source_operation->ctx.sli_cryptoacc_transparent_ctx, + &target_operation->ctx.sli_cryptoacc_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + target_operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + return( sli_crypto_transparent_hash_clone( + &source_operation->ctx.sli_crypto_transparent_ctx, + &target_operation->ctx.sli_crypto_transparent_ctx ) ); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + default: + (void) target_operation; + return( PSA_ERROR_BAD_STATE ); + } +} + +static inline psa_status_t psa_driver_wrapper_hash_update( + psa_hash_operation_t *operation, + const uint8_t *input, + size_t input_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_hash_update( &operation->ctx.mbedtls_ctx, + input, input_length ) ); +#endif +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_hash_update( + &operation->ctx.test_driver_ctx, + input, input_length ) ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_hash_update( + &operation->ctx.sli_se_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_hash_update( + &operation->ctx.sli_cryptoacc_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_hash_update( + &operation->ctx.sli_crypto_transparent_ctx, + input, input_length ) ); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + default: + (void) input; + (void) input_length; + return( PSA_ERROR_BAD_STATE ); + } +} + +static inline psa_status_t psa_driver_wrapper_hash_finish( + psa_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_hash_finish( &operation->ctx.mbedtls_ctx, + hash, hash_size, hash_length ) ); +#endif +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_hash_finish( + &operation->ctx.test_driver_ctx, + hash, hash_size, hash_length ) ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_hash_finish( + &operation->ctx.sli_se_transparent_ctx, + hash, hash_size, hash_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_hash_finish( + &operation->ctx.sli_cryptoacc_transparent_ctx, + hash, hash_size, hash_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_hash_finish( + &operation->ctx.sli_crypto_transparent_ctx, + hash, hash_size, hash_length ) ); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + default: + (void) hash; + (void) hash_size; + (void) hash_length; + return( PSA_ERROR_BAD_STATE ); + } +} + +static inline psa_status_t psa_driver_wrapper_hash_abort( + psa_hash_operation_t *operation ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_HASH) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_hash_abort( &operation->ctx.mbedtls_ctx ) ); +#endif +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_hash_abort( + &operation->ctx.test_driver_ctx ) ); +#endif +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_hash_abort( + &operation->ctx.sli_se_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_hash_abort( + &operation->ctx.sli_cryptoacc_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_hash_abort( + &operation->ctx.sli_crypto_transparent_ctx ) ); +#endif +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + default: + return( PSA_ERROR_BAD_STATE ); + } +} + +static inline psa_status_t psa_driver_wrapper_aead_encrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *plaintext, size_t plaintext_length, + uint8_t *ciphertext, size_t ciphertext_size, size_t *ciphertext_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_AEAD_DEVICE_SI91X) + status = sli_si91x_crypto_aead_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + plaintext_length, + ciphertext, + ciphertext_size, + ciphertext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return status; +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + return( mbedtls_psa_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ) ); + + /* Add cases for opaque driver here */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return ( sli_se_opaque_aead_encrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + plaintext, plaintext_length, + ciphertext, ciphertext_size, ciphertext_length ) ); +#endif +#if defined(SLI_AEAD_DEVICE_SI91X) +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + status = sli_si91x_crypto_aead_encrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + plaintext, + plaintext_length, + ciphertext, + ciphertext_size, + ciphertext_length ); + return status; +#endif +#endif + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_aead_decrypt( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *nonce, size_t nonce_length, + const uint8_t *additional_data, size_t additional_data_length, + const uint8_t *ciphertext, size_t ciphertext_length, + uint8_t *plaintext, size_t plaintext_size, size_t *plaintext_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_AEAD_DEVICE_SI91X) + status = sli_si91x_crypto_aead_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + ciphertext_length, + plaintext, + plaintext_size, + plaintext_length); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return status; +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + return( mbedtls_psa_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ) ); + + /* Add cases for opaque driver here */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return ( sli_se_opaque_aead_decrypt( + attributes, key_buffer, key_buffer_size, + alg, + nonce, nonce_length, + additional_data, additional_data_length, + ciphertext, ciphertext_length, + plaintext, plaintext_size, plaintext_length ) ); +#endif +#if defined(SLI_AEAD_DEVICE_SI91X) +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + status = sli_si91x_crypto_aead_decrypt( + attributes, + key_buffer, + key_buffer_size, + alg, + nonce, + nonce_length, + additional_data, + additional_data_length, + ciphertext, + ciphertext_length, + plaintext, + plaintext_size, + plaintext_length); + return status; +#endif +#endif + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_aead_encrypt_setup( + psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + status = mbedtls_test_transparent_aead_encrypt_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + status = sli_se_transparent_aead_encrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + status = sli_cryptoacc_transparent_aead_encrypt_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_crypto_transparent_aead_encrypt_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + status = mbedtls_psa_aead_encrypt_setup( + &operation->ctx.mbedtls_ctx, attributes, + key_buffer, key_buffer_size, + alg ); + + return( status ); + + /* Add cases for opaque driver here */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_aead_encrypt_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_aead_decrypt_setup( + psa_aead_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + status = mbedtls_test_transparent_aead_decrypt_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + status = sli_se_transparent_aead_decrypt_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + status = sli_cryptoacc_transparent_aead_decrypt_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + status = sli_crypto_transparent_aead_decrypt_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Fell through, meaning no accelerator supports this operation */ + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + status = mbedtls_psa_aead_decrypt_setup( + &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + return( status ); + + /* Add cases for opaque driver here */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_aead_decrypt_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_aead_set_nonce( + psa_aead_operation_t *operation, + const uint8_t *nonce, + size_t nonce_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_set_nonce( &operation->ctx.mbedtls_ctx, + nonce, + nonce_length ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_set_nonce( + &operation->ctx.transparent_test_driver_ctx, + nonce, nonce_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_set_nonce( + &operation->ctx.sli_se_transparent_ctx, + nonce, nonce_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_set_nonce( + &operation->ctx.sli_cryptoacc_transparent_ctx, + nonce, nonce_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_set_nonce( + &operation->ctx.sli_crypto_transparent_ctx, + nonce, nonce_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_set_nonce( + &operation->ctx.sli_se_opaque_ctx, + nonce, nonce_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)nonce; + (void)nonce_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_set_lengths( + psa_aead_operation_t *operation, + size_t ad_length, + size_t plaintext_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_set_lengths( &operation->ctx.mbedtls_ctx, + ad_length, + plaintext_length ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_set_lengths( + &operation->ctx.transparent_test_driver_ctx, + ad_length, plaintext_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_set_lengths( + &operation->ctx.sli_se_transparent_ctx, + ad_length, plaintext_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_set_lengths( + &operation->ctx.sli_cryptoacc_transparent_ctx, + ad_length, plaintext_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_set_lengths( + &operation->ctx.sli_crypto_transparent_ctx, + ad_length, plaintext_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_set_lengths( + &operation->ctx.sli_se_opaque_ctx, + ad_length, plaintext_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)ad_length; + (void)plaintext_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_update_ad( + psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_update_ad( &operation->ctx.mbedtls_ctx, + input, + input_length ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_update_ad( + &operation->ctx.transparent_test_driver_ctx, + input, input_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_update_ad( + &operation->ctx.sli_se_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_update_ad( + &operation->ctx.sli_cryptoacc_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_update_ad( + &operation->ctx.sli_crypto_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_update_ad( + &operation->ctx.sli_se_opaque_ctx, + input, input_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)input; + (void)input_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_update( + psa_aead_operation_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_update( &operation->ctx.mbedtls_ctx, + input, input_length, + output, output_size, + output_length ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_update( + &operation->ctx.transparent_test_driver_ctx, + input, input_length, output, output_size, + output_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_update( + &operation->ctx.sli_se_transparent_ctx, + input, input_length, output, output_size, + output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_update( + &operation->ctx.sli_cryptoacc_transparent_ctx, + input, input_length, output, output_size, + output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_update( + &operation->ctx.sli_crypto_transparent_ctx, + input, input_length, output, output_size, + output_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_update( + &operation->ctx.sli_se_opaque_ctx, + input, input_length, output, output_size, + output_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)input; + (void)input_length; + (void)output; + (void)output_size; + (void)output_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_finish( + psa_aead_operation_t *operation, + uint8_t *ciphertext, + size_t ciphertext_size, + size_t *ciphertext_length, + uint8_t *tag, + size_t tag_size, + size_t *tag_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_finish( &operation->ctx.mbedtls_ctx, + ciphertext, + ciphertext_size, + ciphertext_length, tag, + tag_size, tag_length ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_finish( + &operation->ctx.transparent_test_driver_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_finish( + &operation->ctx.sli_se_transparent_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_finish( + &operation->ctx.sli_cryptoacc_transparent_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_finish( + &operation->ctx.sli_crypto_transparent_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_finish( + &operation->ctx.sli_se_opaque_ctx, + ciphertext, ciphertext_size, + ciphertext_length, tag, tag_size, tag_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)ciphertext; + (void)ciphertext_size; + (void)ciphertext_length; + (void)tag; + (void)tag_size; + (void)tag_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_verify( + psa_aead_operation_t *operation, + uint8_t *plaintext, + size_t plaintext_size, + size_t *plaintext_length, + const uint8_t *tag, + size_t tag_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + uint8_t check_tag[PSA_AEAD_TAG_MAX_SIZE]; + size_t check_tag_length; + + status = mbedtls_psa_aead_finish( &operation->ctx.mbedtls_ctx, + plaintext, + plaintext_size, + plaintext_length, + check_tag, + sizeof( check_tag ), + &check_tag_length ); + + if( status == PSA_SUCCESS ) + { + if( tag_length != check_tag_length || + mbedtls_ct_memcmp( tag, check_tag, tag_length ) + != 0 ) + status = PSA_ERROR_INVALID_SIGNATURE; + } + + mbedtls_platform_zeroize( check_tag, sizeof( check_tag ) ); + + return( status ); + } + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_verify( + &operation->ctx.transparent_test_driver_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_verify( + &operation->ctx.sli_se_transparent_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_verify( + &operation->ctx.sli_cryptoacc_transparent_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_verify( + &operation->ctx.sli_crypto_transparent_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_verify( + &operation->ctx.sli_se_opaque_ctx, + plaintext, plaintext_size, + plaintext_length, tag, tag_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + (void)plaintext; + (void)plaintext_size; + (void)plaintext_length; + (void)tag; + (void)tag_length; + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +static inline psa_status_t psa_driver_wrapper_aead_abort( + psa_aead_operation_t *operation ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_AEAD) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_aead_abort( &operation->ctx.mbedtls_ctx ) ); + +#endif /* MBEDTLS_PSA_BUILTIN_AEAD */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_aead_abort( + &operation->ctx.transparent_test_driver_ctx ) ); + + /* Add cases for opaque driver here */ + +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_aead_abort( + &operation->ctx.sli_se_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_aead_abort( + &operation->ctx.sli_cryptoacc_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_aead_abort( + &operation->ctx.sli_crypto_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_aead_abort( + &operation->ctx.sli_se_opaque_ctx ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + } + + return( PSA_ERROR_INVALID_ARGUMENT ); +} + +/* + * MAC functions + */ +static inline psa_status_t psa_driver_wrapper_mac_compute( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MAC_DEVICE_SI91X) + status = sli_si91x_crypto_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, mac, mac_size, mac_length + ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* SLI_MAC_DEVICE_SI91X */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + /* Fell through, meaning no accelerator supports this operation */ + status = mbedtls_psa_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + return( PSA_ERROR_NOT_SUPPORTED ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ); + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return ( sli_se_opaque_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: + return ( sli_cryptoacc_opaque_mac_compute( + attributes, key_buffer, key_buffer_size, alg, + input, input_length, + mac, mac_size, mac_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + (void) input; + (void) input_length; + (void) mac; + (void) mac_size; + (void) mac_length; + (void) status; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_sign_setup( + psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_mac_sign_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_mac_sign_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_mac_sign_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_mac_sign_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + /* Fell through, meaning no accelerator supports this operation */ + status = mbedtls_psa_mac_sign_setup( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + return( PSA_ERROR_NOT_SUPPORTED ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_mac_sign_setup( + &operation->ctx.opaque_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_mac_sign_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void) status; + (void) operation; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_verify_setup( + psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_mac_verify_setup( + &operation->ctx.transparent_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_mac_verify_setup( + &operation->ctx.sli_se_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_mac_verify_setup( + &operation->ctx.sli_cryptoacc_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + status = sli_crypto_transparent_mac_verify_setup( + &operation->ctx.sli_crypto_transparent_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = SLI_CRYPTO_TRANSPARENT_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + /* Fell through, meaning no accelerator supports this operation */ + status = mbedtls_psa_mac_verify_setup( &operation->ctx.mbedtls_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + return( PSA_ERROR_NOT_SUPPORTED ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + status = mbedtls_test_opaque_mac_verify_setup( + &operation->ctx.opaque_test_driver_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_OPAQUE_DRIVER_ID; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_mac_verify_setup( + &operation->ctx.sli_se_opaque_ctx, + attributes, + key_buffer, key_buffer_size, + alg ); + if( status == PSA_SUCCESS ) + operation->id = SLI_SE_OPAQUE_DRIVER_ID; + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + (void) status; + (void) operation; + (void) key_buffer; + (void) key_buffer_size; + (void) alg; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_update( + psa_mac_operation_t *operation, + const uint8_t *input, + size_t input_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_mac_update( &operation->ctx.mbedtls_ctx, + input, input_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_mac_update( + &operation->ctx.transparent_test_driver_ctx, + input, input_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_mac_update( + &operation->ctx.opaque_test_driver_ctx, + input, input_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_mac_update( + &operation->ctx.sli_se_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_mac_update( + &operation->ctx.sli_cryptoacc_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_mac_update( + &operation->ctx.sli_crypto_transparent_ctx, + input, input_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_mac_update( + &operation->ctx.sli_se_opaque_ctx, + input, input_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) input; + (void) input_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_sign_finish( + psa_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_mac_sign_finish( &operation->ctx.mbedtls_ctx, + mac, mac_size, mac_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_mac_sign_finish( + &operation->ctx.transparent_test_driver_ctx, + mac, mac_size, mac_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_mac_sign_finish( + &operation->ctx.opaque_test_driver_ctx, + mac, mac_size, mac_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_mac_sign_finish( + &operation->ctx.sli_se_transparent_ctx, + mac, mac_size, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_mac_sign_finish( + &operation->ctx.sli_cryptoacc_transparent_ctx, + mac, mac_size, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_mac_sign_finish( + &operation->ctx.sli_crypto_transparent_ctx, + mac, mac_size, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_mac_sign_finish( + &operation->ctx.sli_se_opaque_ctx, + mac, mac_size, mac_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) mac; + (void) mac_size; + (void) mac_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_verify_finish( + psa_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_mac_verify_finish( &operation->ctx.mbedtls_ctx, + mac, mac_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_mac_verify_finish( + &operation->ctx.transparent_test_driver_ctx, + mac, mac_length ) ); + + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_mac_verify_finish( + &operation->ctx.opaque_test_driver_ctx, + mac, mac_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_mac_verify_finish( + &operation->ctx.sli_se_transparent_ctx, + mac, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_mac_verify_finish( + &operation->ctx.sli_cryptoacc_transparent_ctx, + mac, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_mac_verify_finish( + &operation->ctx.sli_crypto_transparent_ctx, + mac, mac_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_mac_verify_finish( + &operation->ctx.sli_se_opaque_ctx, + mac, mac_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) mac; + (void) mac_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_mac_abort( + psa_mac_operation_t *operation ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_MAC) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_mac_abort( &operation->ctx.mbedtls_ctx ) ); +#endif /* MBEDTLS_PSA_BUILTIN_MAC */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_mac_abort( + &operation->ctx.transparent_test_driver_ctx ) ); + case MBEDTLS_TEST_OPAQUE_DRIVER_ID: + return( mbedtls_test_opaque_mac_abort( + &operation->ctx.opaque_test_driver_ctx ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + case SLI_SE_TRANSPARENT_DRIVER_ID: + return( sli_se_transparent_mac_abort( + &operation->ctx.sli_se_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + case SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID: + return( sli_cryptoacc_transparent_mac_abort( + &operation->ctx.sli_cryptoacc_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_S1) + case SLI_CRYPTO_TRANSPARENT_DRIVER_ID: + return( sli_crypto_transparent_mac_abort( + &operation->ctx.sli_crypto_transparent_ctx ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case SLI_SE_OPAQUE_DRIVER_ID: + return( sli_se_opaque_mac_abort( + &operation->ctx.sli_se_opaque_ctx ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +/* + * Asymmetric cryptography + */ +static inline psa_status_t psa_driver_wrapper_asymmetric_encrypt( + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, const uint8_t *input, + size_t input_length, const uint8_t *salt, size_t salt_length, + uint8_t *output, size_t output_size, size_t *output_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_asymmetric_encrypt( attributes, + key_buffer, key_buffer_size, alg, input, input_length, + salt, salt_length, output, output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + return( mbedtls_psa_asymmetric_encrypt( attributes, + key_buffer, key_buffer_size, alg, input, input_length, + salt, salt_length, output, output_size, output_length ) + ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_asymmetric_encrypt( attributes, + key_buffer, key_buffer_size, alg, input, input_length, + salt, salt_length, output, output_size, output_length ) + ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)salt; + (void)salt_length; + (void)output; + (void)output_size; + (void)output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_asymmetric_decrypt( + const psa_key_attributes_t *attributes, const uint8_t *key_buffer, + size_t key_buffer_size, psa_algorithm_t alg, const uint8_t *input, + size_t input_length, const uint8_t *salt, size_t salt_length, + uint8_t *output, size_t output_size, size_t *output_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_asymmetric_decrypt( attributes, + key_buffer, key_buffer_size, alg, input, input_length, + salt, salt_length, output, output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + return( mbedtls_psa_asymmetric_decrypt( attributes, + key_buffer, key_buffer_size, alg,input, input_length, + salt, salt_length, output, output_size, + output_length ) ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_asymmetric_decrypt( attributes, + key_buffer, key_buffer_size, alg, input, input_length, + salt, salt_length, output, output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + /* Key is declared with a lifetime not known to us */ + (void)status; + (void)key_buffer; + (void)key_buffer_size; + (void)alg; + (void)input; + (void)input_length; + (void)salt; + (void)salt_length; + (void)output; + (void)output_size; + (void)output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_key_agreement( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *peer_key, + size_t peer_key_length, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length + ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = + mbedtls_test_transparent_key_agreement( attributes, + key_buffer, key_buffer_size, alg, peer_key, + peer_key_length, shared_secret, shared_secret_size, + shared_secret_length ); + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) + if( PSA_KEY_TYPE_IS_ECC( attributes->core.type ) && + PSA_ALG_IS_ECDH(alg) && + PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == PSA_ECC_FAMILY_SECP_R1 && + attributes->core.bits == 256 ) + { + status = p256_transparent_key_agreement( attributes, + key_buffer, + key_buffer_size, + alg, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + if( status != PSA_ERROR_NOT_SUPPORTED) + return( status ); + } +#endif /* MBEDTLS_PSA_P256M_DRIVER_ENABLED */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_key_agreement( alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_key_agreement( alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#if defined(SLI_ECDH_DEVICE_SI91X) + status = sli_si91x_psa_ecdh_key_agreement( alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + /* Software Fallback */ + status = psa_key_agreement_raw_builtin( attributes, + key_buffer, + key_buffer_size, + alg, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + return( status ); +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: + return( mbedtls_test_opaque_key_agreement( attributes, + key_buffer, key_buffer_size, alg, peer_key, + peer_key_length, shared_secret, shared_secret_size, + shared_secret_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + status = sli_se_opaque_key_agreement( alg, + attributes, + key_buffer, + key_buffer_size, + peer_key, + peer_key_length, + shared_secret, + shared_secret_size, + shared_secret_length ); + // Cannot have fallback for opaque drivers: + return ( status ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + + default: + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + (void) peer_key; + (void) peer_key_length; + (void) shared_secret; + (void) shared_secret_size; + (void) shared_secret_length; + return( PSA_ERROR_NOT_SUPPORTED ); + + } +} + +static inline psa_status_t psa_driver_wrapper_pake_setup( + psa_pake_operation_t *operation, + const psa_crypto_driver_pake_inputs_t *inputs ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + psa_key_location_t location = + PSA_KEY_LIFETIME_GET_LOCATION( psa_get_key_lifetime( &inputs->attributes ) ); + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + status = PSA_ERROR_NOT_SUPPORTED; +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = mbedtls_test_transparent_pake_setup( + &operation->data.ctx.transparent_test_driver_ctx, + inputs ); + if( status == PSA_SUCCESS ) + operation->id = MBEDTLS_TEST_TRANSPARENT_DRIVER_ID; + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) + status = mbedtls_psa_pake_setup( &operation->data.ctx.mbedtls_ctx, + inputs ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_MBED_TLS_DRIVER_ID; +#endif + return status; + /* Add cases for opaque driver here */ + default: + /* Key is declared with a lifetime not known to us */ + (void)operation; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_pake_output( + psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_pake_output( &operation->data.ctx.mbedtls_ctx, step, + output, output_size, output_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_pake_output( + &operation->data.ctx.transparent_test_driver_ctx, + step, output, output_size, output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) step; + (void) output; + (void) output_size; + (void) output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_pake_input( + psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + const uint8_t *input, + size_t input_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_pake_input( &operation->data.ctx.mbedtls_ctx, + step, input, + input_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_pake_input( + &operation->data.ctx.transparent_test_driver_ctx, + step, + input, input_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) step; + (void) input; + (void) input_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_pake_get_implicit_key( + psa_pake_operation_t *operation, + uint8_t *output, size_t output_size, + size_t *output_length ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_pake_get_implicit_key( &operation->data.ctx.mbedtls_ctx, + output, output_size, output_length ) ); +#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_pake_get_implicit_key( + &operation->data.ctx.transparent_test_driver_ctx, + output, output_size, output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) output; + (void) output_size; + (void) output_length; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +static inline psa_status_t psa_driver_wrapper_pake_abort( + psa_pake_operation_t * operation ) +{ + switch( operation->id ) + { +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) + case PSA_CRYPTO_MBED_TLS_DRIVER_ID: + return( mbedtls_psa_pake_abort( &operation->data.ctx.mbedtls_ctx ) ); +#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#if defined(PSA_CRYPTO_DRIVER_TEST) + case MBEDTLS_TEST_TRANSPARENT_DRIVER_ID: + return( mbedtls_test_transparent_pake_abort( + &operation->data.ctx.transparent_test_driver_ctx ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c index e7242dd..d0bf54c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c @@ -1,449 +1,449 @@ -/* - * Functions to delegate cryptographic operations to an available - * and appropriate accelerator. - * Warning: This file is now auto-generated. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -/* BEGIN-common headers */ -#include "common.h" -#include "psa_crypto_aead.h" -#include "psa_crypto_cipher.h" -#include "psa_crypto_core.h" -#include "psa_crypto_driver_wrappers_no_static.h" -#include "psa_crypto_hash.h" -#include "psa_crypto_mac.h" -#include "psa_crypto_pake.h" -#include "psa_crypto_rsa.h" - -#include "mbedtls/platform.h" -/* END-common headers */ - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -/* BEGIN-driver headers */ -/* Headers for mbedtls_test opaque driver */ -#if defined(PSA_CRYPTO_DRIVER_TEST) -#include "test/drivers/test_driver.h" - -#endif -/* Headers for mbedtls_test transparent driver */ -#if defined(PSA_CRYPTO_DRIVER_TEST) -#include "test/drivers/test_driver.h" - -#endif -/* Headers for p256 transparent driver */ -#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) -#include "../3rdparty/p256-m/p256-m_driver_entrypoints.h" - -#endif - - -/* SiLabs Driver Headers */ -#include "sli_psa_driver_features.h" - -#include - -#if defined(SLI_MBEDTLS_DEVICE_HSE) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_se_transparent_types.h" -#include "sli_se_transparent_functions.h" -#endif - -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_se_opaque_types.h" -#include "sli_se_opaque_functions.h" -#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ - -#if defined(SLI_MBEDTLS_DEVICE_VSE) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_cryptoacc_transparent_types.h" -#include "sli_cryptoacc_transparent_functions.h" -#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) -#include "sli_cryptoacc_opaque_types.h" -#include "sli_cryptoacc_opaque_functions.h" -#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ -#endif - -#if defined(SLI_MBEDTLS_DEVICE_S1) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_crypto_transparent_types.h" -#include "sli_crypto_transparent_functions.h" -#endif - -#if defined(SLI_MBEDTLS_DEVICE_SI91X) -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT -#endif -#include "sli_si91x_crypto_driver_functions.h" -#endif - -#ifdef SLI_SECURE_KEY_STORAGE_DEVICE_SI91X -#include "sl_si91x_psa_wrap.h" -#endif /* Secure key storage driver **/ - -/* END-driver headers */ - -/* Auto-generated values depending on which drivers are registered. - * ID 0 is reserved for unallocated operations. - * ID 1 is reserved for the Mbed TLS software driver. */ -/* BEGIN-driver id definition */ -#define PSA_CRYPTO_MBED_TLS_DRIVER_ID (1) -#define MBEDTLS_TEST_OPAQUE_DRIVER_ID (2) -#define MBEDTLS_TEST_TRANSPARENT_DRIVER_ID (3) -#define P256_TRANSPARENT_DRIVER_ID (4) - - -/* SiLabs Driver IDs */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) -#define SLI_SE_TRANSPARENT_DRIVER_ID (4) -#define SLI_SE_OPAQUE_DRIVER_ID (5) -#define SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID (6) -#define SLI_CRYPTO_TRANSPARENT_DRIVER_ID (7) -#endif - -/* END-driver id */ - -/* BEGIN-Common Macro definitions */ - -/* END-Common Macro definitions */ - -/* Support the 'old' SE interface when asked to */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/* PSA_CRYPTO_DRIVER_PRESENT is defined when either a new-style or old-style - * SE driver is present, to avoid unused argument errors at compile time. */ -#ifndef PSA_CRYPTO_DRIVER_PRESENT -#define PSA_CRYPTO_DRIVER_PRESENT -#endif -#include "psa_crypto_se.h" -#endif - -/** Get the key buffer size required to store the key material of a key - * associated with an opaque driver. - * - * \param[in] attributes The key attributes. - * \param[out] key_buffer_size Minimum buffer size to contain the key material - * - * \retval #PSA_SUCCESS - * The minimum size for a buffer to contain the key material has been - * returned successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The type and/or the size in bits of the key or the combination of - * the two is not supported. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key is declared with a lifetime not known to us. - */ -psa_status_t psa_driver_wrapper_get_key_buffer_size( - const psa_key_attributes_t *attributes, - size_t *key_buffer_size ) -{ - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - psa_key_type_t key_type = attributes->core.type; - size_t key_bits = attributes->core.bits; - size_t buffer_size = 0; - - switch( location ) - { -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: - buffer_size = sizeof(sli_cryptoacc_opaque_key_context_t); - *key_buffer_size = buffer_size; - return ( PSA_SUCCESS ); -#endif -#if defined(PSA_CRYPTO_DRIVER_TEST) - case PSA_CRYPTO_TEST_DRIVER_LOCATION: -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) - /* Emulate property 'builtin_key_size' */ - if( psa_key_id_is_builtin( - MBEDTLS_SVC_KEY_ID_GET_KEY_ID( - psa_get_key_id( attributes ) ) ) ) - { - *key_buffer_size = sizeof( psa_drv_slot_number_t ); - return( PSA_SUCCESS ); - } -#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - *key_buffer_size = mbedtls_test_opaque_size_function( key_type, - key_bits ); - return( ( *key_buffer_size != 0 ) ? - PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); -#endif /* PSA_CRYPTO_DRIVER_TEST */ - case PSA_KEY_LOCATION_LOCAL_STORAGE: - buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); - if( buffer_size == 0 || - ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) - return( PSA_ERROR_NOT_SUPPORTED ); - *key_buffer_size = buffer_size; - return( PSA_SUCCESS ); -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); - if( buffer_size == 0 || - ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) - buffer_size = *key_buffer_size; - // Remove public key format byte - if( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY( key_type ) ) { - buffer_size--; - } - // Compensate for word alignment demands - buffer_size = sli_se_word_align( buffer_size ); - if( PSA_BITS_TO_BYTES( key_bits ) & 0x3 || PSA_BITS_TO_BYTES( key_bits ) == 0 ) { - if( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ) { - // Allocate extra word for public keys, since alignment constrains - // May require that - buffer_size += sizeof(uint32_t); - } - } - // Add wrapped context overhead - buffer_size += sizeof(sli_se_opaque_wrapped_key_context_t); - *key_buffer_size = buffer_size; - return ( PSA_SUCCESS ); -#endif -#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) - case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: - buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); - if( buffer_size == 0 || - ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) - return( PSA_ERROR_NOT_SUPPORTED ); - *key_buffer_size = buffer_size; - return( PSA_SUCCESS ); - break; -#endif - - default: - (void)key_type; - (void)key_bits; - *key_buffer_size = 0; - return( PSA_ERROR_INVALID_ARGUMENT ); - } -} - -psa_status_t psa_driver_wrapper_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length ) - -{ - - psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( - psa_get_key_lifetime( attributes ) ); - - /* Try dynamically-registered SE interface first */ -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - - if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) - { - if( ( drv->key_management == NULL ) || - ( drv->key_management->p_export_public == NULL ) ) - { - return( PSA_ERROR_NOT_SUPPORTED ); - } - - return( drv->key_management->p_export_public( - drv_context, - *( (psa_key_slot_number_t *)key_buffer ), - data, data_size, data_length ) ); - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - switch( location ) - { - case PSA_KEY_LOCATION_LOCAL_STORAGE: - /* Key is stored in the slot in export representation, so - * cycle through all known transparent accelerators */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - status = mbedtls_test_transparent_export_public_key - (attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length - ); - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - -#if (defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) ) - status = p256_transparent_export_public_key - (attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length - ); - - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif - - -#if defined(SLI_MBEDTLS_DEVICE_HSE) - status = sli_se_transparent_export_public_key( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif // SLI_MBEDTLS_DEVICE_HSE -#if defined(SLI_MBEDTLS_DEVICE_VSE) - status = sli_cryptoacc_transparent_export_public_key( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif // SLI_MBEDTLS_DEVICE_VSE -#if defined(SLI_ECDH_DEVICE_SI91X) - status = sli_si91x_psa_export_public_key_ecdh( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ); - /* Declared with fallback == true */ - if( status != PSA_ERROR_NOT_SUPPORTED ) - return( status ); -#endif // SLI_ECDH_DEVICE_SI91X -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - /* Fell through, meaning no accelerator supports this operation */ - return( psa_export_public_key_internal( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ) ); - - /* Add cases for opaque driver here */ -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - case 0x7fffff: - return( mbedtls_test_opaque_export_public_key - (attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length - )); -#endif - - -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return( sli_se_opaque_export_public_key( attributes, - key_buffer, - key_buffer_size, - data, - data_size, - data_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - /* Key is declared with a lifetime not known to us */ - return( status ); - } - -} - -psa_status_t psa_driver_wrapper_get_builtin_key( - psa_drv_slot_number_t slot_number, - psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length ) -{ - - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); - switch( location ) - { -#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) - -#if (defined(PSA_CRYPTO_DRIVER_TEST) ) - case 0x7fffff: - return( mbedtls_test_opaque_get_builtin_key - (slot_number, - attributes, - key_buffer, - key_buffer_size, - key_buffer_length - )); -#endif - - -#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) - case PSA_KEY_LOCATION_SLI_SE_OPAQUE: - return( sli_se_opaque_get_builtin_key( - slot_number, - attributes, - key_buffer, key_buffer_size, key_buffer_length ) ); -#endif -#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) - case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: - return( sli_cryptoacc_opaque_get_builtin_key( - slot_number, - attributes, - key_buffer, key_buffer_size, key_buffer_length ) ); -#endif -#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ - default: - (void) slot_number; - (void) key_buffer; - (void) key_buffer_size; - (void) key_buffer_length; - return( PSA_ERROR_DOES_NOT_EXIST ); - } - -} - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * Functions to delegate cryptographic operations to an available + * and appropriate accelerator. + * Warning: This file is now auto-generated. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* BEGIN-common headers */ +#include "common.h" +#include "psa_crypto_aead.h" +#include "psa_crypto_cipher.h" +#include "psa_crypto_core.h" +#include "psa_crypto_driver_wrappers_no_static.h" +#include "psa_crypto_hash.h" +#include "psa_crypto_mac.h" +#include "psa_crypto_pake.h" +#include "psa_crypto_rsa.h" + +#include "mbedtls/platform.h" +/* END-common headers */ + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +/* BEGIN-driver headers */ +/* Headers for mbedtls_test opaque driver */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#include "test/drivers/test_driver.h" + +#endif +/* Headers for mbedtls_test transparent driver */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#include "test/drivers/test_driver.h" + +#endif +/* Headers for p256 transparent driver */ +#if defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) +#include "../3rdparty/p256-m/p256-m_driver_entrypoints.h" + +#endif + + +/* SiLabs Driver Headers */ +#include "sli_psa_driver_features.h" + +#include + +#if defined(SLI_MBEDTLS_DEVICE_HSE) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_se_transparent_types.h" +#include "sli_se_transparent_functions.h" +#endif + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_se_opaque_types.h" +#include "sli_se_opaque_functions.h" +#endif /* SLI_MBEDTLS_DEVICE_HSE && SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ + +#if defined(SLI_MBEDTLS_DEVICE_VSE) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_cryptoacc_transparent_types.h" +#include "sli_cryptoacc_transparent_functions.h" +#if defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) +#include "sli_cryptoacc_opaque_types.h" +#include "sli_cryptoacc_opaque_functions.h" +#endif /* SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS */ +#endif + +#if defined(SLI_MBEDTLS_DEVICE_S1) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_crypto_transparent_types.h" +#include "sli_crypto_transparent_functions.h" +#endif + +#if defined(SLI_MBEDTLS_DEVICE_SI91X) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "sli_si91x_crypto_driver_functions.h" +#endif + +#ifdef SLI_SECURE_KEY_STORAGE_DEVICE_SI91X +#include "sl_si91x_psa_wrap.h" +#endif /* Secure key storage driver **/ + +/* END-driver headers */ + +/* Auto-generated values depending on which drivers are registered. + * ID 0 is reserved for unallocated operations. + * ID 1 is reserved for the Mbed TLS software driver. */ +/* BEGIN-driver id definition */ +#define PSA_CRYPTO_MBED_TLS_DRIVER_ID (1) +#define MBEDTLS_TEST_OPAQUE_DRIVER_ID (2) +#define MBEDTLS_TEST_TRANSPARENT_DRIVER_ID (3) +#define P256_TRANSPARENT_DRIVER_ID (4) + + +/* SiLabs Driver IDs */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +#define SLI_SE_TRANSPARENT_DRIVER_ID (4) +#define SLI_SE_OPAQUE_DRIVER_ID (5) +#define SLI_CRYPTOACC_TRANSPARENT_DRIVER_ID (6) +#define SLI_CRYPTO_TRANSPARENT_DRIVER_ID (7) +#endif + +/* END-driver id */ + +/* BEGIN-Common Macro definitions */ + +/* END-Common Macro definitions */ + +/* Support the 'old' SE interface when asked to */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/* PSA_CRYPTO_DRIVER_PRESENT is defined when either a new-style or old-style + * SE driver is present, to avoid unused argument errors at compile time. */ +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#include "psa_crypto_se.h" +#endif + +/** Get the key buffer size required to store the key material of a key + * associated with an opaque driver. + * + * \param[in] attributes The key attributes. + * \param[out] key_buffer_size Minimum buffer size to contain the key material + * + * \retval #PSA_SUCCESS + * The minimum size for a buffer to contain the key material has been + * returned successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The type and/or the size in bits of the key or the combination of + * the two is not supported. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key is declared with a lifetime not known to us. + */ +psa_status_t psa_driver_wrapper_get_key_buffer_size( + const psa_key_attributes_t *attributes, + size_t *key_buffer_size ) +{ + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + psa_key_type_t key_type = attributes->core.type; + size_t key_bits = attributes->core.bits; + size_t buffer_size = 0; + + switch( location ) + { +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: + buffer_size = sizeof(sli_cryptoacc_opaque_key_context_t); + *key_buffer_size = buffer_size; + return ( PSA_SUCCESS ); +#endif +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LOCATION: +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + /* Emulate property 'builtin_key_size' */ + if( psa_key_id_is_builtin( + MBEDTLS_SVC_KEY_ID_GET_KEY_ID( + psa_get_key_id( attributes ) ) ) ) + { + *key_buffer_size = sizeof( psa_drv_slot_number_t ); + return( PSA_SUCCESS ); + } +#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + *key_buffer_size = mbedtls_test_opaque_size_function( key_type, + key_bits ); + return( ( *key_buffer_size != 0 ) ? + PSA_SUCCESS : PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + case PSA_KEY_LOCATION_LOCAL_STORAGE: + buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); + if( buffer_size == 0 || + ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) + return( PSA_ERROR_NOT_SUPPORTED ); + *key_buffer_size = buffer_size; + return( PSA_SUCCESS ); +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); + if( buffer_size == 0 || + ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) + buffer_size = *key_buffer_size; + // Remove public key format byte + if( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY( key_type ) ) { + buffer_size--; + } + // Compensate for word alignment demands + buffer_size = sli_se_word_align( buffer_size ); + if( PSA_BITS_TO_BYTES( key_bits ) & 0x3 || PSA_BITS_TO_BYTES( key_bits ) == 0 ) { + if( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ) { + // Allocate extra word for public keys, since alignment constrains + // May require that + buffer_size += sizeof(uint32_t); + } + } + // Add wrapped context overhead + buffer_size += sizeof(sli_se_opaque_wrapped_key_context_t); + *key_buffer_size = buffer_size; + return ( PSA_SUCCESS ); +#endif +#if defined(SLI_SECURE_KEY_STORAGE_DEVICE_SI91X) + case PSA_KEY_VOLATILE_PERSISTENT_WRAPPED: + buffer_size = PSA_EXPORT_KEY_OUTPUT_SIZE( key_type, key_bits ); + if( buffer_size == 0 || + ( PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) && buffer_size == 1 ) ) + return( PSA_ERROR_NOT_SUPPORTED ); + *key_buffer_size = buffer_size; + return( PSA_SUCCESS ); + break; +#endif + + default: + (void)key_type; + (void)key_bits; + *key_buffer_size = 0; + return( PSA_ERROR_INVALID_ARGUMENT ); + } +} + +psa_status_t psa_driver_wrapper_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length ) + +{ + + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( + psa_get_key_lifetime( attributes ) ); + + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( attributes->core.lifetime, &drv, &drv_context ) ) + { + if( ( drv->key_management == NULL ) || + ( drv->key_management->p_export_public == NULL ) ) + { + return( PSA_ERROR_NOT_SUPPORTED ); + } + + return( drv->key_management->p_export_public( + drv_context, + *( (psa_key_slot_number_t *)key_buffer ), + data, data_size, data_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + status = mbedtls_test_transparent_export_public_key + (attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length + ); + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + +#if (defined(MBEDTLS_PSA_P256M_DRIVER_ENABLED) ) + status = p256_transparent_export_public_key + (attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length + ); + + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif + + +#if defined(SLI_MBEDTLS_DEVICE_HSE) + status = sli_se_transparent_export_public_key( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif // SLI_MBEDTLS_DEVICE_HSE +#if defined(SLI_MBEDTLS_DEVICE_VSE) + status = sli_cryptoacc_transparent_export_public_key( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif // SLI_MBEDTLS_DEVICE_VSE +#if defined(SLI_ECDH_DEVICE_SI91X) + status = sli_si91x_psa_export_public_key_ecdh( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif // SLI_ECDH_DEVICE_SI91X +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + /* Fell through, meaning no accelerator supports this operation */ + return( psa_export_public_key_internal( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ) ); + + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + case 0x7fffff: + return( mbedtls_test_opaque_export_public_key + (attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length + )); +#endif + + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_OPAQUE_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return( sli_se_opaque_export_public_key( attributes, + key_buffer, + key_buffer_size, + data, + data_size, + data_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } + +} + +psa_status_t psa_driver_wrapper_get_builtin_key( + psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length ) +{ + + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + switch( location ) + { +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + +#if (defined(PSA_CRYPTO_DRIVER_TEST) ) + case 0x7fffff: + return( mbedtls_test_opaque_get_builtin_key + (slot_number, + attributes, + key_buffer, + key_buffer_size, + key_buffer_length + )); +#endif + + +#if defined(SLI_MBEDTLS_DEVICE_HSE) && defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) + case PSA_KEY_LOCATION_SLI_SE_OPAQUE: + return( sli_se_opaque_get_builtin_key( + slot_number, + attributes, + key_buffer, key_buffer_size, key_buffer_length ) ); +#endif +#if defined(SLI_MBEDTLS_DEVICE_VSE) && defined(SLI_PSA_DRIVER_FEATURE_BUILTIN_KEYS) + case PSA_KEY_LOCATION_SL_CRYPTOACC_OPAQUE: + return( sli_cryptoacc_opaque_get_builtin_key( + slot_number, + attributes, + key_buffer, key_buffer_size, key_buffer_length ) ); +#endif +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + default: + (void) slot_number; + (void) key_buffer; + (void) key_buffer_size; + (void) key_buffer_length; + return( PSA_ERROR_DOES_NOT_EXIST ); + } + +} + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.h index 4985403..69a3dc4 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.h @@ -1,43 +1,43 @@ -/* - * Function signatures for functionality that can be provided by - * cryptographic accelerators. - */ -/* Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H -#define PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H - -#include "psa/crypto.h" -#include "psa/crypto_driver_common.h" - -psa_status_t psa_driver_wrapper_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length); - -psa_status_t psa_driver_wrapper_get_key_buffer_size( - const psa_key_attributes_t *attributes, - size_t *key_buffer_size); - -psa_status_t psa_driver_wrapper_get_builtin_key( - psa_drv_slot_number_t slot_number, - psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); - -#endif /* PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H */ - -/* End of automatically generated file. */ +/* + * Function signatures for functionality that can be provided by + * cryptographic accelerators. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H +#define PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H + +#include "psa/crypto.h" +#include "psa/crypto_driver_common.h" + +psa_status_t psa_driver_wrapper_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length); + +psa_status_t psa_driver_wrapper_get_key_buffer_size( + const psa_key_attributes_t *attributes, + size_t *key_buffer_size); + +psa_status_t psa_driver_wrapper_get_builtin_key( + psa_drv_slot_number_t slot_number, + psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); + +#endif /* PSA_CRYPTO_DRIVER_WRAPPERS_NO_STATIC_H */ + +/* End of automatically generated file. */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.c index 5c77865..0e6883e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.c @@ -1,573 +1,573 @@ -/* - * PSA ECP layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa_crypto_core.h" -#include "psa_crypto_ecp.h" -#include "psa_crypto_random_impl.h" -#include "md_psa.h" - -#include -#include -#include "mbedtls/platform.h" - -#include -#include -#include -#include - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) -psa_status_t mbedtls_psa_ecp_load_representation( - psa_key_type_t type, size_t curve_bits, - const uint8_t *data, size_t data_length, - mbedtls_ecp_keypair **p_ecp) -{ - mbedtls_ecp_group_id grp_id = MBEDTLS_ECP_DP_NONE; - psa_status_t status; - mbedtls_ecp_keypair *ecp = NULL; - size_t curve_bytes = data_length; - int explicit_bits = (curve_bits != 0); - - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type) && - PSA_KEY_TYPE_ECC_GET_FAMILY(type) != PSA_ECC_FAMILY_MONTGOMERY) { - /* A Weierstrass public key is represented as: - * - The byte 0x04; - * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; - * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. - * So its data length is 2m+1 where m is the curve size in bits. - */ - if ((data_length & 1) == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - curve_bytes = data_length / 2; - - /* Montgomery public keys are represented in compressed format, meaning - * their curve_bytes is equal to the amount of input. */ - - /* Private keys are represented in uncompressed private random integer - * format, meaning their curve_bytes is equal to the amount of input. */ - } - - if (explicit_bits) { - /* With an explicit bit-size, the data must have the matching length. */ - if (curve_bytes != PSA_BITS_TO_BYTES(curve_bits)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } else { - /* We need to infer the bit-size from the data. Since the only - * information we have is the length in bytes, the value of curve_bits - * at this stage is rounded up to the nearest multiple of 8. */ - curve_bits = PSA_BYTES_TO_BITS(curve_bytes); - } - - /* Allocate and initialize a key representation. */ - ecp = mbedtls_calloc(1, sizeof(mbedtls_ecp_keypair)); - if (ecp == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - mbedtls_ecp_keypair_init(ecp); - - /* Load the group. */ - grp_id = mbedtls_ecc_group_of_psa(PSA_KEY_TYPE_ECC_GET_FAMILY(type), - curve_bits, !explicit_bits); - if (grp_id == MBEDTLS_ECP_DP_NONE) { - /* We can't distinguish between a nonsensical family/size combination - * (which would warrant PSA_ERROR_INVALID_ARGUMENT) and a - * well-regarded curve that Mbed TLS just doesn't know about (which - * would warrant PSA_ERROR_NOT_SUPPORTED). For uniformity with how - * curves that Mbed TLS knows about but for which support is disabled - * at build time, return NOT_SUPPORTED. */ - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - - status = mbedtls_to_psa_error( - mbedtls_ecp_group_load(&ecp->grp, grp_id)); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Load the key material. */ - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { - /* Load the public value. */ - status = mbedtls_to_psa_error( - mbedtls_ecp_point_read_binary(&ecp->grp, &ecp->Q, - data, - data_length)); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Check that the point is on the curve. */ - status = mbedtls_to_psa_error( - mbedtls_ecp_check_pubkey(&ecp->grp, &ecp->Q)); - if (status != PSA_SUCCESS) { - goto exit; - } - } else { - /* Load and validate the secret value. */ - status = mbedtls_to_psa_error( - mbedtls_ecp_read_key(ecp->grp.id, - ecp, - data, - data_length)); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - *p_ecp = ecp; -exit: - if (status != PSA_SUCCESS) { - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - } - - return status; -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) - -psa_status_t mbedtls_psa_ecp_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits) -{ - psa_status_t status; - mbedtls_ecp_keypair *ecp = NULL; - - /* Parse input */ - status = mbedtls_psa_ecp_load_representation(attributes->core.type, - attributes->core.bits, - data, - data_length, - &ecp); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == - PSA_ECC_FAMILY_MONTGOMERY) { - *bits = ecp->grp.nbits + 1; - } else { - *bits = ecp->grp.nbits; - } - - /* Re-export the data to PSA export format. There is currently no support - * for other input formats then the export format, so this is a 1-1 - * copy operation. */ - status = mbedtls_psa_ecp_export_key(attributes->core.type, - ecp, - key_buffer, - key_buffer_size, - key_buffer_length); -exit: - /* Always free the PK object (will also free contained ECP context) */ - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - - return status; -} - -psa_status_t mbedtls_psa_ecp_export_key(psa_key_type_t type, - mbedtls_ecp_keypair *ecp, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - psa_status_t status; - - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { - /* Check whether the public part is loaded */ - if (mbedtls_ecp_is_zero(&ecp->Q)) { - /* Calculate the public key */ - status = mbedtls_to_psa_error( - mbedtls_ecp_mul(&ecp->grp, &ecp->Q, &ecp->d, &ecp->grp.G, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE)); - if (status != PSA_SUCCESS) { - return status; - } - } - - status = mbedtls_to_psa_error( - mbedtls_ecp_point_write_binary(&ecp->grp, &ecp->Q, - MBEDTLS_ECP_PF_UNCOMPRESSED, - data_length, - data, - data_size)); - if (status != PSA_SUCCESS) { - memset(data, 0, data_size); - } - - return status; - } else { - if (data_size < PSA_BITS_TO_BYTES(ecp->grp.nbits)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - status = mbedtls_to_psa_error( - mbedtls_ecp_write_key(ecp, - data, - PSA_BITS_TO_BYTES(ecp->grp.nbits))); - if (status == PSA_SUCCESS) { - *data_length = PSA_BITS_TO_BYTES(ecp->grp.nbits); - } else { - memset(data, 0, data_size); - } - - return status; - } -} - -psa_status_t mbedtls_psa_ecp_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_ecp_keypair *ecp = NULL; - - status = mbedtls_psa_ecp_load_representation( - attributes->core.type, attributes->core.bits, - key_buffer, key_buffer_size, &ecp); - if (status != PSA_SUCCESS) { - return status; - } - - status = mbedtls_psa_ecp_export_key( - PSA_KEY_TYPE_ECC_PUBLIC_KEY( - PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type)), - ecp, data, data_size, data_length); - - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - - return status; -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) -psa_status_t mbedtls_psa_ecp_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY( - attributes->core.type); - mbedtls_ecp_group_id grp_id = - mbedtls_ecc_group_of_psa(curve, attributes->core.bits, 0); - - const mbedtls_ecp_curve_info *curve_info = - mbedtls_ecp_curve_info_from_grp_id(grp_id); - mbedtls_ecp_keypair ecp; - - if (attributes->domain_parameters_size != 0) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (grp_id == MBEDTLS_ECP_DP_NONE || curve_info == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - mbedtls_ecp_keypair_init(&ecp); - ret = mbedtls_ecp_gen_key(grp_id, &ecp, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - if (ret != 0) { - mbedtls_ecp_keypair_free(&ecp); - return mbedtls_to_psa_error(ret); - } - - status = mbedtls_to_psa_error( - mbedtls_ecp_write_key(&ecp, key_buffer, key_buffer_size)); - - mbedtls_ecp_keypair_free(&ecp); - - if (status == PSA_SUCCESS) { - *key_buffer_length = key_buffer_size; - } - - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE */ - -/****************************************************************/ -/* ECDSA sign/verify */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) -psa_status_t mbedtls_psa_ecdsa_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_ecp_keypair *ecp = NULL; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t curve_bytes; - mbedtls_mpi r, s; - - status = mbedtls_psa_ecp_load_representation(attributes->core.type, - attributes->core.bits, - key_buffer, - key_buffer_size, - &ecp); - if (status != PSA_SUCCESS) { - return status; - } - - curve_bytes = PSA_BITS_TO_BYTES(ecp->grp.pbits); - mbedtls_mpi_init(&r); - mbedtls_mpi_init(&s); - - if (signature_size < 2 * curve_bytes) { - ret = MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; - goto cleanup; - } - - if (PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) - psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); - mbedtls_md_type_t md_alg = mbedtls_md_type_from_psa_alg(hash_alg); - MBEDTLS_MPI_CHK(mbedtls_ecdsa_sign_det_ext( - &ecp->grp, &r, &s, - &ecp->d, hash, - hash_length, md_alg, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE)); -#else - ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; - goto cleanup; -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - } else { - (void) alg; - MBEDTLS_MPI_CHK(mbedtls_ecdsa_sign(&ecp->grp, &r, &s, &ecp->d, - hash, hash_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE)); - } - - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&r, - signature, - curve_bytes)); - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&s, - signature + curve_bytes, - curve_bytes)); -cleanup: - mbedtls_mpi_free(&r); - mbedtls_mpi_free(&s); - if (ret == 0) { - *signature_length = 2 * curve_bytes; - } - - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - - return mbedtls_to_psa_error(ret); -} - -psa_status_t mbedtls_psa_ecp_load_public_part(mbedtls_ecp_keypair *ecp) -{ - int ret = 0; - - /* Check whether the public part is loaded. If not, load it. */ - if (mbedtls_ecp_is_zero(&ecp->Q)) { - ret = mbedtls_ecp_mul(&ecp->grp, &ecp->Q, - &ecp->d, &ecp->grp.G, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - } - - return mbedtls_to_psa_error(ret); -} - -psa_status_t mbedtls_psa_ecdsa_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_ecp_keypair *ecp = NULL; - size_t curve_bytes; - mbedtls_mpi r, s; - - (void) alg; - - status = mbedtls_psa_ecp_load_representation(attributes->core.type, - attributes->core.bits, - key_buffer, - key_buffer_size, - &ecp); - if (status != PSA_SUCCESS) { - return status; - } - - curve_bytes = PSA_BITS_TO_BYTES(ecp->grp.pbits); - mbedtls_mpi_init(&r); - mbedtls_mpi_init(&s); - - if (signature_length != 2 * curve_bytes) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto cleanup; - } - - status = mbedtls_to_psa_error(mbedtls_mpi_read_binary(&r, - signature, - curve_bytes)); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - status = mbedtls_to_psa_error(mbedtls_mpi_read_binary(&s, - signature + curve_bytes, - curve_bytes)); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - status = mbedtls_psa_ecp_load_public_part(ecp); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - status = mbedtls_to_psa_error(mbedtls_ecdsa_verify(&ecp->grp, hash, - hash_length, &ecp->Q, - &r, &s)); -cleanup: - mbedtls_mpi_free(&r); - mbedtls_mpi_free(&s); - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - - return status; -} - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ - * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ - -/****************************************************************/ -/* ECDH Key Agreement */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) -psa_status_t mbedtls_psa_key_agreement_ecdh( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *peer_key, size_t peer_key_length, - uint8_t *shared_secret, size_t shared_secret_size, - size_t *shared_secret_length) -{ - psa_status_t status; - if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(attributes->core.type) || - !PSA_ALG_IS_ECDH(alg)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - mbedtls_ecp_keypair *ecp = NULL; - status = mbedtls_psa_ecp_load_representation( - attributes->core.type, - attributes->core.bits, - key_buffer, - key_buffer_size, - &ecp); - if (status != PSA_SUCCESS) { - return status; - } - mbedtls_ecp_keypair *their_key = NULL; - mbedtls_ecdh_context ecdh; - size_t bits = 0; - psa_ecc_family_t curve = mbedtls_ecc_group_to_psa(ecp->grp.id, &bits); - mbedtls_ecdh_init(&ecdh); - - status = mbedtls_psa_ecp_load_representation( - PSA_KEY_TYPE_ECC_PUBLIC_KEY(curve), - bits, - peer_key, - peer_key_length, - &their_key); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = mbedtls_to_psa_error( - mbedtls_ecdh_get_params(&ecdh, their_key, MBEDTLS_ECDH_THEIRS)); - if (status != PSA_SUCCESS) { - goto exit; - } - status = mbedtls_to_psa_error( - mbedtls_ecdh_get_params(&ecdh, ecp, MBEDTLS_ECDH_OURS)); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = mbedtls_to_psa_error( - mbedtls_ecdh_calc_secret(&ecdh, - shared_secret_length, - shared_secret, shared_secret_size, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE)); - if (status != PSA_SUCCESS) { - goto exit; - } - if (PSA_BITS_TO_BYTES(bits) != *shared_secret_length) { - status = PSA_ERROR_CORRUPTION_DETECTED; - } -exit: - if (status != PSA_SUCCESS) { - mbedtls_platform_zeroize(shared_secret, shared_secret_size); - } - mbedtls_ecdh_free(&ecdh); - mbedtls_ecp_keypair_free(their_key); - mbedtls_free(their_key); - mbedtls_ecp_keypair_free(ecp); - mbedtls_free(ecp); - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ - - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA ECP layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa_crypto_core.h" +#include "psa_crypto_ecp.h" +#include "psa_crypto_random_impl.h" +#include "md_psa.h" + +#include +#include +#include "mbedtls/platform.h" + +#include +#include +#include +#include + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) +psa_status_t mbedtls_psa_ecp_load_representation( + psa_key_type_t type, size_t curve_bits, + const uint8_t *data, size_t data_length, + mbedtls_ecp_keypair **p_ecp) +{ + mbedtls_ecp_group_id grp_id = MBEDTLS_ECP_DP_NONE; + psa_status_t status; + mbedtls_ecp_keypair *ecp = NULL; + size_t curve_bytes = data_length; + int explicit_bits = (curve_bits != 0); + + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type) && + PSA_KEY_TYPE_ECC_GET_FAMILY(type) != PSA_ECC_FAMILY_MONTGOMERY) { + /* A Weierstrass public key is represented as: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. + * So its data length is 2m+1 where m is the curve size in bits. + */ + if ((data_length & 1) == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + curve_bytes = data_length / 2; + + /* Montgomery public keys are represented in compressed format, meaning + * their curve_bytes is equal to the amount of input. */ + + /* Private keys are represented in uncompressed private random integer + * format, meaning their curve_bytes is equal to the amount of input. */ + } + + if (explicit_bits) { + /* With an explicit bit-size, the data must have the matching length. */ + if (curve_bytes != PSA_BITS_TO_BYTES(curve_bits)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } else { + /* We need to infer the bit-size from the data. Since the only + * information we have is the length in bytes, the value of curve_bits + * at this stage is rounded up to the nearest multiple of 8. */ + curve_bits = PSA_BYTES_TO_BITS(curve_bytes); + } + + /* Allocate and initialize a key representation. */ + ecp = mbedtls_calloc(1, sizeof(mbedtls_ecp_keypair)); + if (ecp == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + mbedtls_ecp_keypair_init(ecp); + + /* Load the group. */ + grp_id = mbedtls_ecc_group_of_psa(PSA_KEY_TYPE_ECC_GET_FAMILY(type), + curve_bits, !explicit_bits); + if (grp_id == MBEDTLS_ECP_DP_NONE) { + /* We can't distinguish between a nonsensical family/size combination + * (which would warrant PSA_ERROR_INVALID_ARGUMENT) and a + * well-regarded curve that Mbed TLS just doesn't know about (which + * would warrant PSA_ERROR_NOT_SUPPORTED). For uniformity with how + * curves that Mbed TLS knows about but for which support is disabled + * at build time, return NOT_SUPPORTED. */ + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + + status = mbedtls_to_psa_error( + mbedtls_ecp_group_load(&ecp->grp, grp_id)); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Load the key material. */ + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { + /* Load the public value. */ + status = mbedtls_to_psa_error( + mbedtls_ecp_point_read_binary(&ecp->grp, &ecp->Q, + data, + data_length)); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Check that the point is on the curve. */ + status = mbedtls_to_psa_error( + mbedtls_ecp_check_pubkey(&ecp->grp, &ecp->Q)); + if (status != PSA_SUCCESS) { + goto exit; + } + } else { + /* Load and validate the secret value. */ + status = mbedtls_to_psa_error( + mbedtls_ecp_read_key(ecp->grp.id, + ecp, + data, + data_length)); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + *p_ecp = ecp; +exit: + if (status != PSA_SUCCESS) { + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + } + + return status; +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_BASIC) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) + +psa_status_t mbedtls_psa_ecp_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits) +{ + psa_status_t status; + mbedtls_ecp_keypair *ecp = NULL; + + /* Parse input */ + status = mbedtls_psa_ecp_load_representation(attributes->core.type, + attributes->core.bits, + data, + data_length, + &ecp); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type) == + PSA_ECC_FAMILY_MONTGOMERY) { + *bits = ecp->grp.nbits + 1; + } else { + *bits = ecp->grp.nbits; + } + + /* Re-export the data to PSA export format. There is currently no support + * for other input formats then the export format, so this is a 1-1 + * copy operation. */ + status = mbedtls_psa_ecp_export_key(attributes->core.type, + ecp, + key_buffer, + key_buffer_size, + key_buffer_length); +exit: + /* Always free the PK object (will also free contained ECP context) */ + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + + return status; +} + +psa_status_t mbedtls_psa_ecp_export_key(psa_key_type_t type, + mbedtls_ecp_keypair *ecp, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + psa_status_t status; + + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { + /* Check whether the public part is loaded */ + if (mbedtls_ecp_is_zero(&ecp->Q)) { + /* Calculate the public key */ + status = mbedtls_to_psa_error( + mbedtls_ecp_mul(&ecp->grp, &ecp->Q, &ecp->d, &ecp->grp.G, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE)); + if (status != PSA_SUCCESS) { + return status; + } + } + + status = mbedtls_to_psa_error( + mbedtls_ecp_point_write_binary(&ecp->grp, &ecp->Q, + MBEDTLS_ECP_PF_UNCOMPRESSED, + data_length, + data, + data_size)); + if (status != PSA_SUCCESS) { + memset(data, 0, data_size); + } + + return status; + } else { + if (data_size < PSA_BITS_TO_BYTES(ecp->grp.nbits)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + status = mbedtls_to_psa_error( + mbedtls_ecp_write_key(ecp, + data, + PSA_BITS_TO_BYTES(ecp->grp.nbits))); + if (status == PSA_SUCCESS) { + *data_length = PSA_BITS_TO_BYTES(ecp->grp.nbits); + } else { + memset(data, 0, data_size); + } + + return status; + } +} + +psa_status_t mbedtls_psa_ecp_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_keypair *ecp = NULL; + + status = mbedtls_psa_ecp_load_representation( + attributes->core.type, attributes->core.bits, + key_buffer, key_buffer_size, &ecp); + if (status != PSA_SUCCESS) { + return status; + } + + status = mbedtls_psa_ecp_export_key( + PSA_KEY_TYPE_ECC_PUBLIC_KEY( + PSA_KEY_TYPE_ECC_GET_FAMILY(attributes->core.type)), + ecp, data, data_size, data_length); + + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + + return status; +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_IMPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE) +psa_status_t mbedtls_psa_ecp_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY( + attributes->core.type); + mbedtls_ecp_group_id grp_id = + mbedtls_ecc_group_of_psa(curve, attributes->core.bits, 0); + + const mbedtls_ecp_curve_info *curve_info = + mbedtls_ecp_curve_info_from_grp_id(grp_id); + mbedtls_ecp_keypair ecp; + + if (attributes->domain_parameters_size != 0) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (grp_id == MBEDTLS_ECP_DP_NONE || curve_info == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + mbedtls_ecp_keypair_init(&ecp); + ret = mbedtls_ecp_gen_key(grp_id, &ecp, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + if (ret != 0) { + mbedtls_ecp_keypair_free(&ecp); + return mbedtls_to_psa_error(ret); + } + + status = mbedtls_to_psa_error( + mbedtls_ecp_write_key(&ecp, key_buffer, key_buffer_size)); + + mbedtls_ecp_keypair_free(&ecp); + + if (status == PSA_SUCCESS) { + *key_buffer_length = key_buffer_size; + } + + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR_GENERATE */ + +/****************************************************************/ +/* ECDSA sign/verify */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) +psa_status_t mbedtls_psa_ecdsa_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_keypair *ecp = NULL; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t curve_bytes; + mbedtls_mpi r, s; + + status = mbedtls_psa_ecp_load_representation(attributes->core.type, + attributes->core.bits, + key_buffer, + key_buffer_size, + &ecp); + if (status != PSA_SUCCESS) { + return status; + } + + curve_bytes = PSA_BITS_TO_BYTES(ecp->grp.pbits); + mbedtls_mpi_init(&r); + mbedtls_mpi_init(&s); + + if (signature_size < 2 * curve_bytes) { + ret = MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL; + goto cleanup; + } + + if (PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) + psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); + mbedtls_md_type_t md_alg = mbedtls_md_type_from_psa_alg(hash_alg); + MBEDTLS_MPI_CHK(mbedtls_ecdsa_sign_det_ext( + &ecp->grp, &r, &s, + &ecp->d, hash, + hash_length, md_alg, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE)); +#else + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + goto cleanup; +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + } else { + (void) alg; + MBEDTLS_MPI_CHK(mbedtls_ecdsa_sign(&ecp->grp, &r, &s, &ecp->d, + hash, hash_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE)); + } + + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&r, + signature, + curve_bytes)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&s, + signature + curve_bytes, + curve_bytes)); +cleanup: + mbedtls_mpi_free(&r); + mbedtls_mpi_free(&s); + if (ret == 0) { + *signature_length = 2 * curve_bytes; + } + + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + + return mbedtls_to_psa_error(ret); +} + +psa_status_t mbedtls_psa_ecp_load_public_part(mbedtls_ecp_keypair *ecp) +{ + int ret = 0; + + /* Check whether the public part is loaded. If not, load it. */ + if (mbedtls_ecp_is_zero(&ecp->Q)) { + ret = mbedtls_ecp_mul(&ecp->grp, &ecp->Q, + &ecp->d, &ecp->grp.G, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + } + + return mbedtls_to_psa_error(ret); +} + +psa_status_t mbedtls_psa_ecdsa_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_ecp_keypair *ecp = NULL; + size_t curve_bytes; + mbedtls_mpi r, s; + + (void) alg; + + status = mbedtls_psa_ecp_load_representation(attributes->core.type, + attributes->core.bits, + key_buffer, + key_buffer_size, + &ecp); + if (status != PSA_SUCCESS) { + return status; + } + + curve_bytes = PSA_BITS_TO_BYTES(ecp->grp.pbits); + mbedtls_mpi_init(&r); + mbedtls_mpi_init(&s); + + if (signature_length != 2 * curve_bytes) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto cleanup; + } + + status = mbedtls_to_psa_error(mbedtls_mpi_read_binary(&r, + signature, + curve_bytes)); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + status = mbedtls_to_psa_error(mbedtls_mpi_read_binary(&s, + signature + curve_bytes, + curve_bytes)); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + status = mbedtls_psa_ecp_load_public_part(ecp); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + status = mbedtls_to_psa_error(mbedtls_ecdsa_verify(&ecp->grp, hash, + hash_length, &ecp->Q, + &r, &s)); +cleanup: + mbedtls_mpi_free(&r); + mbedtls_mpi_free(&s); + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + + return status; +} + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ + +/****************************************************************/ +/* ECDH Key Agreement */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) +psa_status_t mbedtls_psa_key_agreement_ecdh( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *peer_key, size_t peer_key_length, + uint8_t *shared_secret, size_t shared_secret_size, + size_t *shared_secret_length) +{ + psa_status_t status; + if (!PSA_KEY_TYPE_IS_ECC_KEY_PAIR(attributes->core.type) || + !PSA_ALG_IS_ECDH(alg)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + mbedtls_ecp_keypair *ecp = NULL; + status = mbedtls_psa_ecp_load_representation( + attributes->core.type, + attributes->core.bits, + key_buffer, + key_buffer_size, + &ecp); + if (status != PSA_SUCCESS) { + return status; + } + mbedtls_ecp_keypair *their_key = NULL; + mbedtls_ecdh_context ecdh; + size_t bits = 0; + psa_ecc_family_t curve = mbedtls_ecc_group_to_psa(ecp->grp.id, &bits); + mbedtls_ecdh_init(&ecdh); + + status = mbedtls_psa_ecp_load_representation( + PSA_KEY_TYPE_ECC_PUBLIC_KEY(curve), + bits, + peer_key, + peer_key_length, + &their_key); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = mbedtls_to_psa_error( + mbedtls_ecdh_get_params(&ecdh, their_key, MBEDTLS_ECDH_THEIRS)); + if (status != PSA_SUCCESS) { + goto exit; + } + status = mbedtls_to_psa_error( + mbedtls_ecdh_get_params(&ecdh, ecp, MBEDTLS_ECDH_OURS)); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = mbedtls_to_psa_error( + mbedtls_ecdh_calc_secret(&ecdh, + shared_secret_length, + shared_secret, shared_secret_size, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE)); + if (status != PSA_SUCCESS) { + goto exit; + } + if (PSA_BITS_TO_BYTES(bits) != *shared_secret_length) { + status = PSA_ERROR_CORRUPTION_DETECTED; + } +exit: + if (status != PSA_SUCCESS) { + mbedtls_platform_zeroize(shared_secret, shared_secret_size); + } + mbedtls_ecdh_free(&ecdh); + mbedtls_ecp_keypair_free(their_key); + mbedtls_free(their_key); + mbedtls_ecp_keypair_free(ecp); + mbedtls_free(ecp); + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ + + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.h index f4ad3d2..c0dac0e 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ecp.h @@ -1,279 +1,279 @@ -/* - * PSA ECP layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_ECP_H -#define PSA_CRYPTO_ECP_H - -#include -#include - -/** Load the contents of a key buffer into an internal ECP representation - * - * \param[in] type The type of key contained in \p data. - * \param[in] curve_bits The nominal bit-size of the curve. - * It must be consistent with the representation - * passed in \p data. - * This can be 0, in which case the bit-size - * is inferred from \p data_length (which is possible - * for all key types and representation formats - * formats that are currently supported or will - * be in the foreseeable future). - * \param[in] data The buffer from which to load the representation. - * \param[in] data_length The size in bytes of \p data. - * \param[out] p_ecp Returns a pointer to an ECP context on success. - * The caller is responsible for freeing both the - * contents of the context and the context itself - * when done. - */ -psa_status_t mbedtls_psa_ecp_load_representation(psa_key_type_t type, - size_t curve_bits, - const uint8_t *data, - size_t data_length, - mbedtls_ecp_keypair **p_ecp); - -/** Load the public part of an internal ECP, if required. - * - * \param ecp The ECP context to load the public part for. - * - * \return PSA_SUCCESS on success, otherwise an MPI error. - */ - -psa_status_t mbedtls_psa_ecp_load_public_part(mbedtls_ecp_keypair *ecp); - -/** Import an ECP key in binary format. - * - * \note The signature of this function is that of a PSA driver - * import_key entry point. This function behaves as an import_key - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes for the key to import. - * \param[in] data The buffer containing the key data in import - * format. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] key_buffer The buffer containing the key data in output - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This - * size is greater or equal to \p data_length. - * \param[out] key_buffer_length The length of the data written in \p - * key_buffer in bytes. - * \param[out] bits The key size in number of bits. - * - * \retval #PSA_SUCCESS The ECP key was imported successfully. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key data is not correctly formatted. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_ecp_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits); - -/** Export an ECP key to export representation - * - * \param[in] type The type of key (public/private) to export - * \param[in] ecp The internal ECP representation from which to export - * \param[out] data The buffer to export to - * \param[in] data_size The length of the buffer to export to - * \param[out] data_length The amount of bytes written to \p data - */ -psa_status_t mbedtls_psa_ecp_export_key(psa_key_type_t type, - mbedtls_ecp_keypair *ecp, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** Export an ECP public key or the public part of an ECP key pair in binary - * format. - * - * \note The signature of this function is that of a PSA driver - * export_public_key entry point. This function behaves as an - * export_public_key entry point as defined in the PSA driver interface - * specification. - * - * \param[in] attributes The attributes for the key to export. - * \param[in] key_buffer Material or context of the key to export. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[out] data Buffer where the key data is to be written. - * \param[in] data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes written in - * \p data - * - * \retval #PSA_SUCCESS The ECP public key was exported successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_ecp_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length); - -/** - * \brief Generate an ECP key. - * - * \note The signature of the function is that of a PSA driver generate_key - * entry point. - * - * \param[in] attributes The attributes for the ECP key to generate. - * \param[out] key_buffer Buffer where the key data is to be written. - * \param[in] key_buffer_size Size of \p key_buffer in bytes. - * \param[out] key_buffer_length On success, the number of bytes written in - * \p key_buffer. - * - * \retval #PSA_SUCCESS - * The key was successfully generated. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Key length or type not supported. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - */ -psa_status_t mbedtls_psa_ecp_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); - -/** Sign an already-calculated hash with ECDSA. - * - * \note The signature of this function is that of a PSA driver - * sign_hash entry point. This function behaves as a sign_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the ECC key to use for the - * operation. - * \param[in] key_buffer The buffer containing the ECC key context. - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg Randomized or deterministic ECDSA algorithm. - * \param[in] hash The hash or message to sign. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c PSA_KEY_TYPE_ECC_KEY_PAIR, \c key_bits, - * \p alg) where \c key_bits is the bit-size of the ECC key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - */ -psa_status_t mbedtls_psa_ecdsa_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length); - -/** - * \brief Verify an ECDSA hash or short message signature. - * - * \note The signature of this function is that of a PSA driver - * verify_hash entry point. This function behaves as a verify_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the ECC key to use for the - * operation. - * \param[in] key_buffer The buffer containing the ECC key context. - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg Randomized or deterministic ECDSA algorithm. - * \param[in] hash The hash or message whose signature is to be - * verified. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_ecdsa_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - - -/** Perform a key agreement and return the raw ECDH shared secret. - * - * \note The signature of this function is that of a PSA driver - * key_agreement entry point. This function behaves as a key_agreement - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the private key - * context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in - * bytes. - * \param[in] alg A key agreement algorithm that is - * compatible with the type of the key. - * \param[in] peer_key The buffer containing the key context - * of the peer's public key. - * \param[in] peer_key_length Size of the \p peer_key buffer in - * bytes. - * \param[out] shared_secret The buffer to which the shared secret - * is to be written. - * \param[in] shared_secret_size Size of the \p shared_secret buffer in - * bytes. - * \param[out] shared_secret_length On success, the number of bytes that make - * up the returned shared secret. - * \retval #PSA_SUCCESS - * Success. Shared secret successfully calculated. - * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p alg is not a key agreement algorithm, or - * \p private_key is not compatible with \p alg, - * or \p peer_key is not valid for \p alg or not compatible with - * \p private_key. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p shared_secret_size is too small - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not a supported key agreement algorithm. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_key_agreement_ecdh( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *peer_key, size_t peer_key_length, - uint8_t *shared_secret, size_t shared_secret_size, - size_t *shared_secret_length); -#endif /* PSA_CRYPTO_ECP_H */ +/* + * PSA ECP layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_ECP_H +#define PSA_CRYPTO_ECP_H + +#include +#include + +/** Load the contents of a key buffer into an internal ECP representation + * + * \param[in] type The type of key contained in \p data. + * \param[in] curve_bits The nominal bit-size of the curve. + * It must be consistent with the representation + * passed in \p data. + * This can be 0, in which case the bit-size + * is inferred from \p data_length (which is possible + * for all key types and representation formats + * formats that are currently supported or will + * be in the foreseeable future). + * \param[in] data The buffer from which to load the representation. + * \param[in] data_length The size in bytes of \p data. + * \param[out] p_ecp Returns a pointer to an ECP context on success. + * The caller is responsible for freeing both the + * contents of the context and the context itself + * when done. + */ +psa_status_t mbedtls_psa_ecp_load_representation(psa_key_type_t type, + size_t curve_bits, + const uint8_t *data, + size_t data_length, + mbedtls_ecp_keypair **p_ecp); + +/** Load the public part of an internal ECP, if required. + * + * \param ecp The ECP context to load the public part for. + * + * \return PSA_SUCCESS on success, otherwise an MPI error. + */ + +psa_status_t mbedtls_psa_ecp_load_public_part(mbedtls_ecp_keypair *ecp); + +/** Import an ECP key in binary format. + * + * \note The signature of this function is that of a PSA driver + * import_key entry point. This function behaves as an import_key + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes for the key to import. + * \param[in] data The buffer containing the key data in import + * format. + * \param[in] data_length Size of the \p data buffer in bytes. + * \param[out] key_buffer The buffer containing the key data in output + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This + * size is greater or equal to \p data_length. + * \param[out] key_buffer_length The length of the data written in \p + * key_buffer in bytes. + * \param[out] bits The key size in number of bits. + * + * \retval #PSA_SUCCESS The ECP key was imported successfully. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key data is not correctly formatted. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_ecp_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits); + +/** Export an ECP key to export representation + * + * \param[in] type The type of key (public/private) to export + * \param[in] ecp The internal ECP representation from which to export + * \param[out] data The buffer to export to + * \param[in] data_size The length of the buffer to export to + * \param[out] data_length The amount of bytes written to \p data + */ +psa_status_t mbedtls_psa_ecp_export_key(psa_key_type_t type, + mbedtls_ecp_keypair *ecp, + uint8_t *data, + size_t data_size, + size_t *data_length); + +/** Export an ECP public key or the public part of an ECP key pair in binary + * format. + * + * \note The signature of this function is that of a PSA driver + * export_public_key entry point. This function behaves as an + * export_public_key entry point as defined in the PSA driver interface + * specification. + * + * \param[in] attributes The attributes for the key to export. + * \param[in] key_buffer Material or context of the key to export. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[out] data Buffer where the key data is to be written. + * \param[in] data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes written in + * \p data + * + * \retval #PSA_SUCCESS The ECP public key was exported successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_ecp_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length); + +/** + * \brief Generate an ECP key. + * + * \note The signature of the function is that of a PSA driver generate_key + * entry point. + * + * \param[in] attributes The attributes for the ECP key to generate. + * \param[out] key_buffer Buffer where the key data is to be written. + * \param[in] key_buffer_size Size of \p key_buffer in bytes. + * \param[out] key_buffer_length On success, the number of bytes written in + * \p key_buffer. + * + * \retval #PSA_SUCCESS + * The key was successfully generated. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Key length or type not supported. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + */ +psa_status_t mbedtls_psa_ecp_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); + +/** Sign an already-calculated hash with ECDSA. + * + * \note The signature of this function is that of a PSA driver + * sign_hash entry point. This function behaves as a sign_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the ECC key to use for the + * operation. + * \param[in] key_buffer The buffer containing the ECC key context. + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg Randomized or deterministic ECDSA algorithm. + * \param[in] hash The hash or message to sign. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param[in] signature_size Size of the \p signature buffer in bytes. + * \param[out] signature_length On success, the number of bytes + * that make up the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c PSA_KEY_TYPE_ECC_KEY_PAIR, \c key_bits, + * \p alg) where \c key_bits is the bit-size of the ECC key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + */ +psa_status_t mbedtls_psa_ecdsa_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length); + +/** + * \brief Verify an ECDSA hash or short message signature. + * + * \note The signature of this function is that of a PSA driver + * verify_hash entry point. This function behaves as a verify_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the ECC key to use for the + * operation. + * \param[in] key_buffer The buffer containing the ECC key context. + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg Randomized or deterministic ECDSA algorithm. + * \param[in] hash The hash or message whose signature is to be + * verified. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param[in] signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The signature is valid. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_ecdsa_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length); + + +/** Perform a key agreement and return the raw ECDH shared secret. + * + * \note The signature of this function is that of a PSA driver + * key_agreement entry point. This function behaves as a key_agreement + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the private key + * context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in + * bytes. + * \param[in] alg A key agreement algorithm that is + * compatible with the type of the key. + * \param[in] peer_key The buffer containing the key context + * of the peer's public key. + * \param[in] peer_key_length Size of the \p peer_key buffer in + * bytes. + * \param[out] shared_secret The buffer to which the shared secret + * is to be written. + * \param[in] shared_secret_size Size of the \p shared_secret buffer in + * bytes. + * \param[out] shared_secret_length On success, the number of bytes that make + * up the returned shared secret. + * \retval #PSA_SUCCESS + * Success. Shared secret successfully calculated. + * \retval #PSA_ERROR_INVALID_HANDLE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p alg is not a key agreement algorithm, or + * \p private_key is not compatible with \p alg, + * or \p peer_key is not valid for \p alg or not compatible with + * \p private_key. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p shared_secret_size is too small + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not a supported key agreement algorithm. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_key_agreement_ecdh( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *peer_key, size_t peer_key_length, + uint8_t *shared_secret, size_t shared_secret_size, + size_t *shared_secret_length); +#endif /* PSA_CRYPTO_ECP_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.c index 20dfd2d..8a081c3 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.c @@ -1,307 +1,307 @@ -/* - * PSA FFDH layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa_crypto_core.h" -#include "psa_crypto_ffdh.h" -#include "psa_crypto_random_impl.h" -#include "mbedtls/platform.h" -#include "mbedtls/error.h" - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) -static psa_status_t mbedtls_psa_ffdh_set_prime_generator(size_t key_size, - mbedtls_mpi *P, - mbedtls_mpi *G) -{ - const unsigned char *dhm_P = NULL; - const unsigned char *dhm_G = NULL; - size_t dhm_size_P = 0; - size_t dhm_size_G = 0; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - if (P == NULL && G == NULL) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - static const unsigned char dhm_P_2048[] = - MBEDTLS_DHM_RFC7919_FFDHE2048_P_BIN; - static const unsigned char dhm_P_3072[] = - MBEDTLS_DHM_RFC7919_FFDHE3072_P_BIN; - static const unsigned char dhm_P_4096[] = - MBEDTLS_DHM_RFC7919_FFDHE4096_P_BIN; - static const unsigned char dhm_P_6144[] = - MBEDTLS_DHM_RFC7919_FFDHE6144_P_BIN; - static const unsigned char dhm_P_8192[] = - MBEDTLS_DHM_RFC7919_FFDHE8192_P_BIN; - static const unsigned char dhm_G_2048[] = - MBEDTLS_DHM_RFC7919_FFDHE2048_G_BIN; - static const unsigned char dhm_G_3072[] = - MBEDTLS_DHM_RFC7919_FFDHE3072_G_BIN; - static const unsigned char dhm_G_4096[] = - MBEDTLS_DHM_RFC7919_FFDHE4096_G_BIN; - static const unsigned char dhm_G_6144[] = - MBEDTLS_DHM_RFC7919_FFDHE6144_G_BIN; - static const unsigned char dhm_G_8192[] = - MBEDTLS_DHM_RFC7919_FFDHE8192_G_BIN; - - switch (key_size) { - case sizeof(dhm_P_2048): - dhm_P = dhm_P_2048; - dhm_G = dhm_G_2048; - dhm_size_P = sizeof(dhm_P_2048); - dhm_size_G = sizeof(dhm_G_2048); - break; - case sizeof(dhm_P_3072): - dhm_P = dhm_P_3072; - dhm_G = dhm_G_3072; - dhm_size_P = sizeof(dhm_P_3072); - dhm_size_G = sizeof(dhm_G_3072); - break; - case sizeof(dhm_P_4096): - dhm_P = dhm_P_4096; - dhm_G = dhm_G_4096; - dhm_size_P = sizeof(dhm_P_4096); - dhm_size_G = sizeof(dhm_G_4096); - break; - case sizeof(dhm_P_6144): - dhm_P = dhm_P_6144; - dhm_G = dhm_G_6144; - dhm_size_P = sizeof(dhm_P_6144); - dhm_size_G = sizeof(dhm_G_6144); - break; - case sizeof(dhm_P_8192): - dhm_P = dhm_P_8192; - dhm_G = dhm_G_8192; - dhm_size_P = sizeof(dhm_P_8192); - dhm_size_G = sizeof(dhm_G_8192); - break; - default: - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (P != NULL) { - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(P, dhm_P, - dhm_size_P)); - } - if (G != NULL) { - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(G, dhm_G, - dhm_size_G)); - } - -cleanup: - if (ret != 0) { - return mbedtls_to_psa_error(ret); - } - - return PSA_SUCCESS; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT || - MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE || - MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY || - MBEDTLS_PSA_BUILTIN_ALG_FFDH */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) -psa_status_t mbedtls_psa_ffdh_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_mpi GX, G, X, P; - psa_key_type_t type = attributes->core.type; - - if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { - if (key_buffer_size > data_size) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - memcpy(data, key_buffer, key_buffer_size); - memset(data + key_buffer_size, 0, - data_size - key_buffer_size); - *data_length = key_buffer_size; - return PSA_SUCCESS; - } - - mbedtls_mpi_init(&GX); mbedtls_mpi_init(&G); - mbedtls_mpi_init(&X); mbedtls_mpi_init(&P); - - size_t key_len = PSA_BITS_TO_BYTES(attributes->core.bits); - - status = mbedtls_psa_ffdh_set_prime_generator(key_len, &P, &G); - - if (status != PSA_SUCCESS) { - goto cleanup; - } - - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&X, key_buffer, - key_buffer_size)); - - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&GX, &G, &X, &P, NULL)); - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&GX, data, key_len)); - - *data_length = key_len; - - ret = 0; -cleanup: - mbedtls_mpi_free(&P); mbedtls_mpi_free(&G); - mbedtls_mpi_free(&X); mbedtls_mpi_free(&GX); - - if (status == PSA_SUCCESS && ret != 0) { - status = mbedtls_to_psa_error(ret); - } - - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT || - MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) -psa_status_t mbedtls_psa_ffdh_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) -{ - mbedtls_mpi X, P; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_mpi_init(&P); mbedtls_mpi_init(&X); - (void) attributes; - - status = mbedtls_psa_ffdh_set_prime_generator(key_buffer_size, &P, NULL); - - if (status != PSA_SUCCESS) { - goto cleanup; - } - - /* RFC7919: Traditional finite field Diffie-Hellman has each peer choose their - secret exponent from the range [2, P-2]. - Select random value in range [3, P-1] and decrease it by 1. */ - MBEDTLS_MPI_CHK(mbedtls_mpi_random(&X, 3, &P, mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE)); - MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&X, &X, 1)); - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&X, key_buffer, key_buffer_size)); - *key_buffer_length = key_buffer_size; - -cleanup: - mbedtls_mpi_free(&P); mbedtls_mpi_free(&X); - if (status == PSA_SUCCESS && ret != 0) { - return mbedtls_to_psa_error(ret); - } - - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT) -psa_status_t mbedtls_psa_ffdh_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits) -{ - (void) attributes; - - if (key_buffer_size < data_length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - memcpy(key_buffer, data, data_length); - *key_buffer_length = data_length; - *bits = PSA_BYTES_TO_BITS(data_length); - - return PSA_SUCCESS; -} -#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) -psa_status_t mbedtls_psa_ffdh_key_agreement( - const psa_key_attributes_t *attributes, - const uint8_t *peer_key, - size_t peer_key_length, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_mpi P, G, X, GY, K; - const size_t calculated_shared_secret_size = peer_key_length; - - if (peer_key_length != key_buffer_size || - calculated_shared_secret_size > shared_secret_size) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (!PSA_KEY_TYPE_IS_DH_KEY_PAIR(psa_get_key_type(attributes))) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - mbedtls_mpi_init(&P); mbedtls_mpi_init(&G); - mbedtls_mpi_init(&X); mbedtls_mpi_init(&GY); - mbedtls_mpi_init(&K); - - status = mbedtls_psa_ffdh_set_prime_generator( - PSA_BITS_TO_BYTES(attributes->core.bits), &P, &G); - - if (status != PSA_SUCCESS) { - goto cleanup; - } - - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&X, key_buffer, - key_buffer_size)); - - MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&GY, peer_key, - peer_key_length)); - - /* Calculate shared secret public key: K = G^(XY) mod P = GY^X mod P */ - MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&K, &GY, &X, &P, NULL)); - - MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&K, shared_secret, - calculated_shared_secret_size)); - - *shared_secret_length = calculated_shared_secret_size; - - ret = 0; - -cleanup: - mbedtls_mpi_free(&P); mbedtls_mpi_free(&G); - mbedtls_mpi_free(&X); mbedtls_mpi_free(&GY); - mbedtls_mpi_free(&K); - - if (status == PSA_SUCCESS && ret != 0) { - status = mbedtls_to_psa_error(ret); - } - - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_FFDH */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA FFDH layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa_crypto_core.h" +#include "psa_crypto_ffdh.h" +#include "psa_crypto_random_impl.h" +#include "mbedtls/platform.h" +#include "mbedtls/error.h" + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) +static psa_status_t mbedtls_psa_ffdh_set_prime_generator(size_t key_size, + mbedtls_mpi *P, + mbedtls_mpi *G) +{ + const unsigned char *dhm_P = NULL; + const unsigned char *dhm_G = NULL; + size_t dhm_size_P = 0; + size_t dhm_size_G = 0; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if (P == NULL && G == NULL) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + static const unsigned char dhm_P_2048[] = + MBEDTLS_DHM_RFC7919_FFDHE2048_P_BIN; + static const unsigned char dhm_P_3072[] = + MBEDTLS_DHM_RFC7919_FFDHE3072_P_BIN; + static const unsigned char dhm_P_4096[] = + MBEDTLS_DHM_RFC7919_FFDHE4096_P_BIN; + static const unsigned char dhm_P_6144[] = + MBEDTLS_DHM_RFC7919_FFDHE6144_P_BIN; + static const unsigned char dhm_P_8192[] = + MBEDTLS_DHM_RFC7919_FFDHE8192_P_BIN; + static const unsigned char dhm_G_2048[] = + MBEDTLS_DHM_RFC7919_FFDHE2048_G_BIN; + static const unsigned char dhm_G_3072[] = + MBEDTLS_DHM_RFC7919_FFDHE3072_G_BIN; + static const unsigned char dhm_G_4096[] = + MBEDTLS_DHM_RFC7919_FFDHE4096_G_BIN; + static const unsigned char dhm_G_6144[] = + MBEDTLS_DHM_RFC7919_FFDHE6144_G_BIN; + static const unsigned char dhm_G_8192[] = + MBEDTLS_DHM_RFC7919_FFDHE8192_G_BIN; + + switch (key_size) { + case sizeof(dhm_P_2048): + dhm_P = dhm_P_2048; + dhm_G = dhm_G_2048; + dhm_size_P = sizeof(dhm_P_2048); + dhm_size_G = sizeof(dhm_G_2048); + break; + case sizeof(dhm_P_3072): + dhm_P = dhm_P_3072; + dhm_G = dhm_G_3072; + dhm_size_P = sizeof(dhm_P_3072); + dhm_size_G = sizeof(dhm_G_3072); + break; + case sizeof(dhm_P_4096): + dhm_P = dhm_P_4096; + dhm_G = dhm_G_4096; + dhm_size_P = sizeof(dhm_P_4096); + dhm_size_G = sizeof(dhm_G_4096); + break; + case sizeof(dhm_P_6144): + dhm_P = dhm_P_6144; + dhm_G = dhm_G_6144; + dhm_size_P = sizeof(dhm_P_6144); + dhm_size_G = sizeof(dhm_G_6144); + break; + case sizeof(dhm_P_8192): + dhm_P = dhm_P_8192; + dhm_G = dhm_G_8192; + dhm_size_P = sizeof(dhm_P_8192); + dhm_size_G = sizeof(dhm_G_8192); + break; + default: + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (P != NULL) { + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(P, dhm_P, + dhm_size_P)); + } + if (G != NULL) { + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(G, dhm_G, + dhm_size_G)); + } + +cleanup: + if (ret != 0) { + return mbedtls_to_psa_error(ret); + } + + return PSA_SUCCESS; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT || + MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE || + MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY || + MBEDTLS_PSA_BUILTIN_ALG_FFDH */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY) +psa_status_t mbedtls_psa_ffdh_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi GX, G, X, P; + psa_key_type_t type = attributes->core.type; + + if (PSA_KEY_TYPE_IS_PUBLIC_KEY(type)) { + if (key_buffer_size > data_size) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + memcpy(data, key_buffer, key_buffer_size); + memset(data + key_buffer_size, 0, + data_size - key_buffer_size); + *data_length = key_buffer_size; + return PSA_SUCCESS; + } + + mbedtls_mpi_init(&GX); mbedtls_mpi_init(&G); + mbedtls_mpi_init(&X); mbedtls_mpi_init(&P); + + size_t key_len = PSA_BITS_TO_BYTES(attributes->core.bits); + + status = mbedtls_psa_ffdh_set_prime_generator(key_len, &P, &G); + + if (status != PSA_SUCCESS) { + goto cleanup; + } + + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&X, key_buffer, + key_buffer_size)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&GX, &G, &X, &P, NULL)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&GX, data, key_len)); + + *data_length = key_len; + + ret = 0; +cleanup: + mbedtls_mpi_free(&P); mbedtls_mpi_free(&G); + mbedtls_mpi_free(&X); mbedtls_mpi_free(&GX); + + if (status == PSA_SUCCESS && ret != 0) { + status = mbedtls_to_psa_error(ret); + } + + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_EXPORT || + MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_PUBLIC_KEY */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE) +psa_status_t mbedtls_psa_ffdh_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) +{ + mbedtls_mpi X, P; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi_init(&P); mbedtls_mpi_init(&X); + (void) attributes; + + status = mbedtls_psa_ffdh_set_prime_generator(key_buffer_size, &P, NULL); + + if (status != PSA_SUCCESS) { + goto cleanup; + } + + /* RFC7919: Traditional finite field Diffie-Hellman has each peer choose their + secret exponent from the range [2, P-2]. + Select random value in range [3, P-1] and decrease it by 1. */ + MBEDTLS_MPI_CHK(mbedtls_mpi_random(&X, 3, &P, mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE)); + MBEDTLS_MPI_CHK(mbedtls_mpi_sub_int(&X, &X, 1)); + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&X, key_buffer, key_buffer_size)); + *key_buffer_length = key_buffer_size; + +cleanup: + mbedtls_mpi_free(&P); mbedtls_mpi_free(&X); + if (status == PSA_SUCCESS && ret != 0) { + return mbedtls_to_psa_error(ret); + } + + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_GENERATE */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT) +psa_status_t mbedtls_psa_ffdh_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits) +{ + (void) attributes; + + if (key_buffer_size < data_length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + memcpy(key_buffer, data, data_length); + *key_buffer_length = data_length; + *bits = PSA_BYTES_TO_BITS(data_length); + + return PSA_SUCCESS; +} +#endif /* MBEDTLS_PSA_BUILTIN_KEY_TYPE_DH_KEY_PAIR_IMPORT */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_FFDH) +psa_status_t mbedtls_psa_ffdh_key_agreement( + const psa_key_attributes_t *attributes, + const uint8_t *peer_key, + size_t peer_key_length, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_mpi P, G, X, GY, K; + const size_t calculated_shared_secret_size = peer_key_length; + + if (peer_key_length != key_buffer_size || + calculated_shared_secret_size > shared_secret_size) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (!PSA_KEY_TYPE_IS_DH_KEY_PAIR(psa_get_key_type(attributes))) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + mbedtls_mpi_init(&P); mbedtls_mpi_init(&G); + mbedtls_mpi_init(&X); mbedtls_mpi_init(&GY); + mbedtls_mpi_init(&K); + + status = mbedtls_psa_ffdh_set_prime_generator( + PSA_BITS_TO_BYTES(attributes->core.bits), &P, &G); + + if (status != PSA_SUCCESS) { + goto cleanup; + } + + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&X, key_buffer, + key_buffer_size)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&GY, peer_key, + peer_key_length)); + + /* Calculate shared secret public key: K = G^(XY) mod P = GY^X mod P */ + MBEDTLS_MPI_CHK(mbedtls_mpi_exp_mod(&K, &GY, &X, &P, NULL)); + + MBEDTLS_MPI_CHK(mbedtls_mpi_write_binary(&K, shared_secret, + calculated_shared_secret_size)); + + *shared_secret_length = calculated_shared_secret_size; + + ret = 0; + +cleanup: + mbedtls_mpi_free(&P); mbedtls_mpi_free(&G); + mbedtls_mpi_free(&X); mbedtls_mpi_free(&GY); + mbedtls_mpi_free(&K); + + if (status == PSA_SUCCESS && ret != 0) { + status = mbedtls_to_psa_error(ret); + } + + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_FFDH */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.h index 67e5444..3ea9135 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_ffdh.h @@ -1,144 +1,144 @@ -/* - * PSA FFDH layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_FFDH_H -#define PSA_CRYPTO_FFDH_H - -#include -#include - -/** Perform a key agreement and return the FFDH shared secret. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] peer_key The buffer containing the key context - * of the peer's public key. - * \param[in] peer_key_length Size of the \p peer_key buffer in - * bytes. - * \param[in] key_buffer The buffer containing the private key - * context. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in - * bytes. - * \param[out] shared_secret The buffer to which the shared secret - * is to be written. - * \param[in] shared_secret_size Size of the \p shared_secret buffer in - * bytes. - * \param[out] shared_secret_length On success, the number of bytes that make - * up the returned shared secret. - * \retval #PSA_SUCCESS - * Success. Shared secret successfully calculated. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p key_buffer_size, \p peer_key_length, \p shared_secret_size - * do not match - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_ffdh_key_agreement( - const psa_key_attributes_t *attributes, - const uint8_t *peer_key, - size_t peer_key_length, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *shared_secret, - size_t shared_secret_size, - size_t *shared_secret_length); - -/** Export a public key or the public part of a DH key pair in binary format. - * - * \param[in] attributes The attributes for the key to export. - * \param[in] key_buffer Material or context of the key to export. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[out] data Buffer where the key data is to be written. - * \param[in] data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes written in - * \p data - * - * \retval #PSA_SUCCESS The public key was exported successfully. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_ffdh_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** - * \brief Generate DH key. - * - * \note The signature of the function is that of a PSA driver generate_key - * entry point. - * - * \param[in] attributes The attributes for the key to generate. - * \param[out] key_buffer Buffer where the key data is to be written. - * \param[in] key_buffer_size Size of \p key_buffer in bytes. - * \param[out] key_buffer_length On success, the number of bytes written in - * \p key_buffer. - * - * \retval #PSA_SUCCESS - * The key was generated successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Key size in bits is invalid. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_ffdh_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, - size_t key_buffer_size, - size_t *key_buffer_length); - -/** - * \brief Import DH key. - * - * \note The signature of the function is that of a PSA driver import_key - * entry point. - * - * \param[in] attributes The attributes for the key to import. - * \param[in] data The buffer containing the key data in import - * format. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] key_buffer The buffer containing the key data in output - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This - * size is greater or equal to \p data_length. - * \param[out] key_buffer_length The length of the data written in \p - * key_buffer in bytes. - * \param[out] bits The key size in number of bits. - * - * \retval #PSA_SUCCESS - * The key was generated successfully. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - */ -psa_status_t mbedtls_psa_ffdh_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits); - -#endif /* PSA_CRYPTO_FFDH_H */ +/* + * PSA FFDH layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_FFDH_H +#define PSA_CRYPTO_FFDH_H + +#include +#include + +/** Perform a key agreement and return the FFDH shared secret. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] peer_key The buffer containing the key context + * of the peer's public key. + * \param[in] peer_key_length Size of the \p peer_key buffer in + * bytes. + * \param[in] key_buffer The buffer containing the private key + * context. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in + * bytes. + * \param[out] shared_secret The buffer to which the shared secret + * is to be written. + * \param[in] shared_secret_size Size of the \p shared_secret buffer in + * bytes. + * \param[out] shared_secret_length On success, the number of bytes that make + * up the returned shared secret. + * \retval #PSA_SUCCESS + * Success. Shared secret successfully calculated. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p key_buffer_size, \p peer_key_length, \p shared_secret_size + * do not match + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_ffdh_key_agreement( + const psa_key_attributes_t *attributes, + const uint8_t *peer_key, + size_t peer_key_length, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *shared_secret, + size_t shared_secret_size, + size_t *shared_secret_length); + +/** Export a public key or the public part of a DH key pair in binary format. + * + * \param[in] attributes The attributes for the key to export. + * \param[in] key_buffer Material or context of the key to export. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[out] data Buffer where the key data is to be written. + * \param[in] data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes written in + * \p data + * + * \retval #PSA_SUCCESS The public key was exported successfully. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + * \retval #PSA_ERROR_NOT_PERMITTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_ffdh_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + uint8_t *data, + size_t data_size, + size_t *data_length); + +/** + * \brief Generate DH key. + * + * \note The signature of the function is that of a PSA driver generate_key + * entry point. + * + * \param[in] attributes The attributes for the key to generate. + * \param[out] key_buffer Buffer where the key data is to be written. + * \param[in] key_buffer_size Size of \p key_buffer in bytes. + * \param[out] key_buffer_length On success, the number of bytes written in + * \p key_buffer. + * + * \retval #PSA_SUCCESS + * The key was generated successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Key size in bits is invalid. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_ffdh_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, + size_t key_buffer_size, + size_t *key_buffer_length); + +/** + * \brief Import DH key. + * + * \note The signature of the function is that of a PSA driver import_key + * entry point. + * + * \param[in] attributes The attributes for the key to import. + * \param[in] data The buffer containing the key data in import + * format. + * \param[in] data_length Size of the \p data buffer in bytes. + * \param[out] key_buffer The buffer containing the key data in output + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This + * size is greater or equal to \p data_length. + * \param[out] key_buffer_length The length of the data written in \p + * key_buffer in bytes. + * \param[out] bits The key size in number of bits. + * + * \retval #PSA_SUCCESS + * The key was generated successfully. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + */ +psa_status_t mbedtls_psa_ffdh_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits); + +#endif /* PSA_CRYPTO_FFDH_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.c index dad1826..d223994 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.c @@ -1,482 +1,482 @@ -/* - * PSA hashing layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa_crypto_core.h" -#include "psa_crypto_hash.h" - -#include -#include - -#if defined(MBEDTLS_PSA_BUILTIN_HASH) -psa_status_t mbedtls_psa_hash_abort( - mbedtls_psa_hash_operation_t *operation) -{ - switch (operation->alg) { - case 0: - /* The object has (apparently) been initialized but it is not - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - break; -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - case PSA_ALG_MD5: - mbedtls_md5_free(&operation->ctx.md5); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - case PSA_ALG_RIPEMD160: - mbedtls_ripemd160_free(&operation->ctx.ripemd160); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - case PSA_ALG_SHA_1: - mbedtls_sha1_free(&operation->ctx.sha1); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - case PSA_ALG_SHA_224: - mbedtls_sha256_free(&operation->ctx.sha256); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) - case PSA_ALG_SHA_256: - mbedtls_sha256_free(&operation->ctx.sha256); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - case PSA_ALG_SHA_384: - mbedtls_sha512_free(&operation->ctx.sha512); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) - case PSA_ALG_SHA_512: - mbedtls_sha512_free(&operation->ctx.sha512); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) - case PSA_ALG_SHA3_224: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) - case PSA_ALG_SHA3_256: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) - case PSA_ALG_SHA3_384: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - case PSA_ALG_SHA3_512: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - mbedtls_sha3_free(&operation->ctx.sha3); - break; -#endif - default: - return PSA_ERROR_BAD_STATE; - } - operation->alg = 0; - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_hash_setup( - mbedtls_psa_hash_operation_t *operation, - psa_algorithm_t alg) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - /* A context must be freshly initialized before it can be set up. */ - if (operation->alg != 0) { - return PSA_ERROR_BAD_STATE; - } - - switch (alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - case PSA_ALG_MD5: - mbedtls_md5_init(&operation->ctx.md5); - ret = mbedtls_md5_starts(&operation->ctx.md5); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - case PSA_ALG_RIPEMD160: - mbedtls_ripemd160_init(&operation->ctx.ripemd160); - ret = mbedtls_ripemd160_starts(&operation->ctx.ripemd160); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - case PSA_ALG_SHA_1: - mbedtls_sha1_init(&operation->ctx.sha1); - ret = mbedtls_sha1_starts(&operation->ctx.sha1); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - case PSA_ALG_SHA_224: - mbedtls_sha256_init(&operation->ctx.sha256); - ret = mbedtls_sha256_starts(&operation->ctx.sha256, 1); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) - case PSA_ALG_SHA_256: - mbedtls_sha256_init(&operation->ctx.sha256); - ret = mbedtls_sha256_starts(&operation->ctx.sha256, 0); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - case PSA_ALG_SHA_384: - mbedtls_sha512_init(&operation->ctx.sha512); - ret = mbedtls_sha512_starts(&operation->ctx.sha512, 1); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) - case PSA_ALG_SHA_512: - mbedtls_sha512_init(&operation->ctx.sha512); - ret = mbedtls_sha512_starts(&operation->ctx.sha512, 0); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) - case PSA_ALG_SHA3_224: - mbedtls_sha3_init(&operation->ctx.sha3); - ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_224); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) - case PSA_ALG_SHA3_256: - mbedtls_sha3_init(&operation->ctx.sha3); - ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_256); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) - case PSA_ALG_SHA3_384: - mbedtls_sha3_init(&operation->ctx.sha3); - ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_384); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - case PSA_ALG_SHA3_512: - mbedtls_sha3_init(&operation->ctx.sha3); - ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_512); - break; -#endif - default: - return PSA_ALG_IS_HASH(alg) ? - PSA_ERROR_NOT_SUPPORTED : - PSA_ERROR_INVALID_ARGUMENT; - } - if (ret == 0) { - operation->alg = alg; - } else { - mbedtls_psa_hash_abort(operation); - } - return mbedtls_to_psa_error(ret); -} - -psa_status_t mbedtls_psa_hash_clone( - const mbedtls_psa_hash_operation_t *source_operation, - mbedtls_psa_hash_operation_t *target_operation) -{ - switch (source_operation->alg) { - case 0: - return PSA_ERROR_BAD_STATE; -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - case PSA_ALG_MD5: - mbedtls_md5_clone(&target_operation->ctx.md5, - &source_operation->ctx.md5); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - case PSA_ALG_RIPEMD160: - mbedtls_ripemd160_clone(&target_operation->ctx.ripemd160, - &source_operation->ctx.ripemd160); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - case PSA_ALG_SHA_1: - mbedtls_sha1_clone(&target_operation->ctx.sha1, - &source_operation->ctx.sha1); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - case PSA_ALG_SHA_224: - mbedtls_sha256_clone(&target_operation->ctx.sha256, - &source_operation->ctx.sha256); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) - case PSA_ALG_SHA_256: - mbedtls_sha256_clone(&target_operation->ctx.sha256, - &source_operation->ctx.sha256); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - case PSA_ALG_SHA_384: - mbedtls_sha512_clone(&target_operation->ctx.sha512, - &source_operation->ctx.sha512); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) - case PSA_ALG_SHA_512: - mbedtls_sha512_clone(&target_operation->ctx.sha512, - &source_operation->ctx.sha512); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) - case PSA_ALG_SHA3_224: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) - case PSA_ALG_SHA3_256: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) - case PSA_ALG_SHA3_384: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - case PSA_ALG_SHA3_512: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - mbedtls_sha3_clone(&target_operation->ctx.sha3, - &source_operation->ctx.sha3); - break; -#endif - default: - (void) source_operation; - (void) target_operation; - return PSA_ERROR_NOT_SUPPORTED; - } - - target_operation->alg = source_operation->alg; - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_hash_update( - mbedtls_psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - switch (operation->alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - case PSA_ALG_MD5: - ret = mbedtls_md5_update(&operation->ctx.md5, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - case PSA_ALG_RIPEMD160: - ret = mbedtls_ripemd160_update(&operation->ctx.ripemd160, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - case PSA_ALG_SHA_1: - ret = mbedtls_sha1_update(&operation->ctx.sha1, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - case PSA_ALG_SHA_224: - ret = mbedtls_sha256_update(&operation->ctx.sha256, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) - case PSA_ALG_SHA_256: - ret = mbedtls_sha256_update(&operation->ctx.sha256, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - case PSA_ALG_SHA_384: - ret = mbedtls_sha512_update(&operation->ctx.sha512, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) - case PSA_ALG_SHA_512: - ret = mbedtls_sha512_update(&operation->ctx.sha512, - input, input_length); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) - case PSA_ALG_SHA3_224: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) - case PSA_ALG_SHA3_256: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) - case PSA_ALG_SHA3_384: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - case PSA_ALG_SHA3_512: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - ret = mbedtls_sha3_update(&operation->ctx.sha3, - input, input_length); - break; -#endif - default: - (void) input; - (void) input_length; - return PSA_ERROR_BAD_STATE; - } - - return mbedtls_to_psa_error(ret); -} - -psa_status_t mbedtls_psa_hash_finish( - mbedtls_psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ - psa_status_t status; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t actual_hash_length = PSA_HASH_LENGTH(operation->alg); - - /* Fill the output buffer with something that isn't a valid hash - * (barring an attack on the hash and deliberately-crafted input), - * in case the caller doesn't check the return status properly. */ - *hash_length = hash_size; - /* If hash_size is 0 then hash may be NULL and then the - * call to memset would have undefined behavior. */ - if (hash_size != 0) { - memset(hash, '!', hash_size); - } - - if (hash_size < actual_hash_length) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - - switch (operation->alg) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) - case PSA_ALG_MD5: - ret = mbedtls_md5_finish(&operation->ctx.md5, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) - case PSA_ALG_RIPEMD160: - ret = mbedtls_ripemd160_finish(&operation->ctx.ripemd160, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) - case PSA_ALG_SHA_1: - ret = mbedtls_sha1_finish(&operation->ctx.sha1, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) - case PSA_ALG_SHA_224: - ret = mbedtls_sha256_finish(&operation->ctx.sha256, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) - case PSA_ALG_SHA_256: - ret = mbedtls_sha256_finish(&operation->ctx.sha256, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) - case PSA_ALG_SHA_384: - ret = mbedtls_sha512_finish(&operation->ctx.sha512, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) - case PSA_ALG_SHA_512: - ret = mbedtls_sha512_finish(&operation->ctx.sha512, hash); - break; -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) - case PSA_ALG_SHA3_224: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) - case PSA_ALG_SHA3_256: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) - case PSA_ALG_SHA3_384: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - case PSA_ALG_SHA3_512: -#endif -#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) - ret = mbedtls_sha3_finish(&operation->ctx.sha3, hash, hash_size); - break; -#endif - default: - (void) hash; - return PSA_ERROR_BAD_STATE; - } - status = mbedtls_to_psa_error(ret); - -exit: - if (status == PSA_SUCCESS) { - *hash_length = actual_hash_length; - } - return status; -} - -psa_status_t mbedtls_psa_hash_compute( - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length) -{ - mbedtls_psa_hash_operation_t operation = MBEDTLS_PSA_HASH_OPERATION_INIT; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; - - *hash_length = hash_size; - status = mbedtls_psa_hash_setup(&operation, alg); - if (status != PSA_SUCCESS) { - goto exit; - } - status = mbedtls_psa_hash_update(&operation, input, input_length); - if (status != PSA_SUCCESS) { - goto exit; - } - status = mbedtls_psa_hash_finish(&operation, hash, hash_size, hash_length); - if (status != PSA_SUCCESS) { - goto exit; - } - -exit: - abort_status = mbedtls_psa_hash_abort(&operation); - if (status == PSA_SUCCESS) { - return abort_status; - } else { - return status; - } - -} -#endif /* MBEDTLS_PSA_BUILTIN_HASH */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA hashing layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa_crypto_core.h" +#include "psa_crypto_hash.h" + +#include +#include + +#if defined(MBEDTLS_PSA_BUILTIN_HASH) +psa_status_t mbedtls_psa_hash_abort( + mbedtls_psa_hash_operation_t *operation) +{ + switch (operation->alg) { + case 0: + /* The object has (apparently) been initialized but it is not + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + break; +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + case PSA_ALG_MD5: + mbedtls_md5_free(&operation->ctx.md5); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + case PSA_ALG_RIPEMD160: + mbedtls_ripemd160_free(&operation->ctx.ripemd160); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + case PSA_ALG_SHA_1: + mbedtls_sha1_free(&operation->ctx.sha1); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + case PSA_ALG_SHA_224: + mbedtls_sha256_free(&operation->ctx.sha256); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) + case PSA_ALG_SHA_256: + mbedtls_sha256_free(&operation->ctx.sha256); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + case PSA_ALG_SHA_384: + mbedtls_sha512_free(&operation->ctx.sha512); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) + case PSA_ALG_SHA_512: + mbedtls_sha512_free(&operation->ctx.sha512); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) + case PSA_ALG_SHA3_224: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) + case PSA_ALG_SHA3_256: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) + case PSA_ALG_SHA3_384: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + case PSA_ALG_SHA3_512: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + mbedtls_sha3_free(&operation->ctx.sha3); + break; +#endif + default: + return PSA_ERROR_BAD_STATE; + } + operation->alg = 0; + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_hash_setup( + mbedtls_psa_hash_operation_t *operation, + psa_algorithm_t alg) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* A context must be freshly initialized before it can be set up. */ + if (operation->alg != 0) { + return PSA_ERROR_BAD_STATE; + } + + switch (alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + case PSA_ALG_MD5: + mbedtls_md5_init(&operation->ctx.md5); + ret = mbedtls_md5_starts(&operation->ctx.md5); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + case PSA_ALG_RIPEMD160: + mbedtls_ripemd160_init(&operation->ctx.ripemd160); + ret = mbedtls_ripemd160_starts(&operation->ctx.ripemd160); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + case PSA_ALG_SHA_1: + mbedtls_sha1_init(&operation->ctx.sha1); + ret = mbedtls_sha1_starts(&operation->ctx.sha1); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + case PSA_ALG_SHA_224: + mbedtls_sha256_init(&operation->ctx.sha256); + ret = mbedtls_sha256_starts(&operation->ctx.sha256, 1); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) + case PSA_ALG_SHA_256: + mbedtls_sha256_init(&operation->ctx.sha256); + ret = mbedtls_sha256_starts(&operation->ctx.sha256, 0); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + case PSA_ALG_SHA_384: + mbedtls_sha512_init(&operation->ctx.sha512); + ret = mbedtls_sha512_starts(&operation->ctx.sha512, 1); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) + case PSA_ALG_SHA_512: + mbedtls_sha512_init(&operation->ctx.sha512); + ret = mbedtls_sha512_starts(&operation->ctx.sha512, 0); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) + case PSA_ALG_SHA3_224: + mbedtls_sha3_init(&operation->ctx.sha3); + ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_224); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) + case PSA_ALG_SHA3_256: + mbedtls_sha3_init(&operation->ctx.sha3); + ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_256); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) + case PSA_ALG_SHA3_384: + mbedtls_sha3_init(&operation->ctx.sha3); + ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_384); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + case PSA_ALG_SHA3_512: + mbedtls_sha3_init(&operation->ctx.sha3); + ret = mbedtls_sha3_starts(&operation->ctx.sha3, MBEDTLS_SHA3_512); + break; +#endif + default: + return PSA_ALG_IS_HASH(alg) ? + PSA_ERROR_NOT_SUPPORTED : + PSA_ERROR_INVALID_ARGUMENT; + } + if (ret == 0) { + operation->alg = alg; + } else { + mbedtls_psa_hash_abort(operation); + } + return mbedtls_to_psa_error(ret); +} + +psa_status_t mbedtls_psa_hash_clone( + const mbedtls_psa_hash_operation_t *source_operation, + mbedtls_psa_hash_operation_t *target_operation) +{ + switch (source_operation->alg) { + case 0: + return PSA_ERROR_BAD_STATE; +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + case PSA_ALG_MD5: + mbedtls_md5_clone(&target_operation->ctx.md5, + &source_operation->ctx.md5); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + case PSA_ALG_RIPEMD160: + mbedtls_ripemd160_clone(&target_operation->ctx.ripemd160, + &source_operation->ctx.ripemd160); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + case PSA_ALG_SHA_1: + mbedtls_sha1_clone(&target_operation->ctx.sha1, + &source_operation->ctx.sha1); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + case PSA_ALG_SHA_224: + mbedtls_sha256_clone(&target_operation->ctx.sha256, + &source_operation->ctx.sha256); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) + case PSA_ALG_SHA_256: + mbedtls_sha256_clone(&target_operation->ctx.sha256, + &source_operation->ctx.sha256); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + case PSA_ALG_SHA_384: + mbedtls_sha512_clone(&target_operation->ctx.sha512, + &source_operation->ctx.sha512); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) + case PSA_ALG_SHA_512: + mbedtls_sha512_clone(&target_operation->ctx.sha512, + &source_operation->ctx.sha512); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) + case PSA_ALG_SHA3_224: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) + case PSA_ALG_SHA3_256: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) + case PSA_ALG_SHA3_384: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + case PSA_ALG_SHA3_512: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + mbedtls_sha3_clone(&target_operation->ctx.sha3, + &source_operation->ctx.sha3); + break; +#endif + default: + (void) source_operation; + (void) target_operation; + return PSA_ERROR_NOT_SUPPORTED; + } + + target_operation->alg = source_operation->alg; + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_hash_update( + mbedtls_psa_hash_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + switch (operation->alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + case PSA_ALG_MD5: + ret = mbedtls_md5_update(&operation->ctx.md5, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + case PSA_ALG_RIPEMD160: + ret = mbedtls_ripemd160_update(&operation->ctx.ripemd160, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + case PSA_ALG_SHA_1: + ret = mbedtls_sha1_update(&operation->ctx.sha1, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + case PSA_ALG_SHA_224: + ret = mbedtls_sha256_update(&operation->ctx.sha256, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) + case PSA_ALG_SHA_256: + ret = mbedtls_sha256_update(&operation->ctx.sha256, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + case PSA_ALG_SHA_384: + ret = mbedtls_sha512_update(&operation->ctx.sha512, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) + case PSA_ALG_SHA_512: + ret = mbedtls_sha512_update(&operation->ctx.sha512, + input, input_length); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) + case PSA_ALG_SHA3_224: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) + case PSA_ALG_SHA3_256: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) + case PSA_ALG_SHA3_384: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + case PSA_ALG_SHA3_512: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + ret = mbedtls_sha3_update(&operation->ctx.sha3, + input, input_length); + break; +#endif + default: + (void) input; + (void) input_length; + return PSA_ERROR_BAD_STATE; + } + + return mbedtls_to_psa_error(ret); +} + +psa_status_t mbedtls_psa_hash_finish( + mbedtls_psa_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + psa_status_t status; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t actual_hash_length = PSA_HASH_LENGTH(operation->alg); + + /* Fill the output buffer with something that isn't a valid hash + * (barring an attack on the hash and deliberately-crafted input), + * in case the caller doesn't check the return status properly. */ + *hash_length = hash_size; + /* If hash_size is 0 then hash may be NULL and then the + * call to memset would have undefined behavior. */ + if (hash_size != 0) { + memset(hash, '!', hash_size); + } + + if (hash_size < actual_hash_length) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + + switch (operation->alg) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) + case PSA_ALG_MD5: + ret = mbedtls_md5_finish(&operation->ctx.md5, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) + case PSA_ALG_RIPEMD160: + ret = mbedtls_ripemd160_finish(&operation->ctx.ripemd160, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) + case PSA_ALG_SHA_1: + ret = mbedtls_sha1_finish(&operation->ctx.sha1, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) + case PSA_ALG_SHA_224: + ret = mbedtls_sha256_finish(&operation->ctx.sha256, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) + case PSA_ALG_SHA_256: + ret = mbedtls_sha256_finish(&operation->ctx.sha256, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) + case PSA_ALG_SHA_384: + ret = mbedtls_sha512_finish(&operation->ctx.sha512, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) + case PSA_ALG_SHA_512: + ret = mbedtls_sha512_finish(&operation->ctx.sha512, hash); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) + case PSA_ALG_SHA3_224: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) + case PSA_ALG_SHA3_256: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) + case PSA_ALG_SHA3_384: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + case PSA_ALG_SHA3_512: +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_224) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_256) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_384) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_SHA3_512) + ret = mbedtls_sha3_finish(&operation->ctx.sha3, hash, hash_size); + break; +#endif + default: + (void) hash; + return PSA_ERROR_BAD_STATE; + } + status = mbedtls_to_psa_error(ret); + +exit: + if (status == PSA_SUCCESS) { + *hash_length = actual_hash_length; + } + return status; +} + +psa_status_t mbedtls_psa_hash_compute( + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length) +{ + mbedtls_psa_hash_operation_t operation = MBEDTLS_PSA_HASH_OPERATION_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t abort_status = PSA_ERROR_CORRUPTION_DETECTED; + + *hash_length = hash_size; + status = mbedtls_psa_hash_setup(&operation, alg); + if (status != PSA_SUCCESS) { + goto exit; + } + status = mbedtls_psa_hash_update(&operation, input, input_length); + if (status != PSA_SUCCESS) { + goto exit; + } + status = mbedtls_psa_hash_finish(&operation, hash, hash_size, hash_length); + if (status != PSA_SUCCESS) { + goto exit; + } + +exit: + abort_status = mbedtls_psa_hash_abort(&operation); + if (status == PSA_SUCCESS) { + return abort_status; + } else { + return status; + } + +} +#endif /* MBEDTLS_PSA_BUILTIN_HASH */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.h index 2dfb011..eeeb6fd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_hash.h @@ -1,223 +1,223 @@ -/* - * PSA hashing layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_HASH_H -#define PSA_CRYPTO_HASH_H - -#include - -/** Calculate the hash (digest) of a message using Mbed TLS routines. - * - * \note The signature of this function is that of a PSA driver hash_compute - * entry point. This function behaves as a hash_compute entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * \param[in] input Buffer containing the message to hash. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\p alg). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p hash_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_hash_compute( - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Set up a multipart hash operation using Mbed TLS routines. - * - * \note The signature of this function is that of a PSA driver hash_setup - * entry point. This function behaves as a hash_setup entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * If an error occurs at any step after a call to mbedtls_psa_hash_setup(), the - * operation will need to be reset by a call to mbedtls_psa_hash_abort(). The - * core may call mbedtls_psa_hash_abort() at any time after the operation - * has been initialized. - * - * After a successful call to mbedtls_psa_hash_setup(), the core must - * eventually terminate the operation. The following events terminate an - * operation: - * - A successful call to mbedtls_psa_hash_finish() or mbedtls_psa_hash_verify(). - * - A call to mbedtls_psa_hash_abort(). - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized to all-zero and not yet be in use. - * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_HASH(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_hash_setup( - mbedtls_psa_hash_operation_t *operation, - psa_algorithm_t alg); - -/** Clone an Mbed TLS hash operation. - * - * \note The signature of this function is that of a PSA driver hash_clone - * entry point. This function behaves as a hash_clone entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * This function copies the state of an ongoing hash operation to - * a new operation object. In other words, this function is equivalent - * to calling mbedtls_psa_hash_setup() on \p target_operation with the same - * algorithm that \p source_operation was set up for, then - * mbedtls_psa_hash_update() on \p target_operation with the same input that - * that was passed to \p source_operation. After this function returns, the - * two objects are independent, i.e. subsequent calls involving one of - * the objects do not affect the other object. - * - * \param[in] source_operation The active hash operation to clone. - * \param[in,out] target_operation The operation object to set up. - * It must be initialized but not active. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The \p source_operation state is not valid (it must be active). - * \retval #PSA_ERROR_BAD_STATE - * The \p target_operation state is not valid (it must be inactive). - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_hash_clone( - const mbedtls_psa_hash_operation_t *source_operation, - mbedtls_psa_hash_operation_t *target_operation); - -/** Add a message fragment to a multipart Mbed TLS hash operation. - * - * \note The signature of this function is that of a PSA driver hash_update - * entry point. This function behaves as a hash_update entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * The application must call mbedtls_psa_hash_setup() before calling this function. - * - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling mbedtls_psa_hash_abort(). - * - * \param[in,out] operation Active hash operation. - * \param[in] input Buffer containing the message fragment to hash. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_hash_update( - mbedtls_psa_hash_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the Mbed TLS-calculated hash of a message. - * - * \note The signature of this function is that of a PSA driver hash_finish - * entry point. This function behaves as a hash_finish entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * The application must call mbedtls_psa_hash_setup() before calling this function. - * This function calculates the hash of the message formed by concatenating - * the inputs passed to preceding calls to mbedtls_psa_hash_update(). - * - * When this function returns successfully, the operation becomes inactive. - * If this function returns an error status, the operation enters an error - * state and must be aborted by calling mbedtls_psa_hash_abort(). - * - * \param[in,out] operation Active hash operation. - * \param[out] hash Buffer where the hash is to be written. - * \param hash_size Size of the \p hash buffer in bytes. - * \param[out] hash_length On success, the number of bytes - * that make up the hash value. This is always - * #PSA_HASH_LENGTH(\c alg) where \c alg is the - * hash algorithm that is calculated. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active). - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p hash buffer is too small. You can determine a - * sufficient buffer size by calling #PSA_HASH_LENGTH(\c alg) - * where \c alg is the hash algorithm that is calculated. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_hash_finish( - mbedtls_psa_hash_operation_t *operation, - uint8_t *hash, - size_t hash_size, - size_t *hash_length); - -/** Abort an Mbed TLS hash operation. - * - * \note The signature of this function is that of a PSA driver hash_abort - * entry point. This function behaves as a hash_abort entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * mbedtls_psa_hash_setup() again. - * - * You may call this function any time after the operation object has - * been initialized by one of the methods described in #psa_hash_operation_t. - * - * In particular, calling mbedtls_psa_hash_abort() after the operation has been - * terminated by a call to mbedtls_psa_hash_abort(), mbedtls_psa_hash_finish() or - * mbedtls_psa_hash_verify() is safe and has no effect. - * - * \param[in,out] operation Initialized hash operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_hash_abort( - mbedtls_psa_hash_operation_t *operation); - -#endif /* PSA_CRYPTO_HASH_H */ +/* + * PSA hashing layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_HASH_H +#define PSA_CRYPTO_HASH_H + +#include + +/** Calculate the hash (digest) of a message using Mbed TLS routines. + * + * \note The signature of this function is that of a PSA driver hash_compute + * entry point. This function behaves as a hash_compute entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_HASH(\p alg) is true). + * \param[in] input Buffer containing the message to hash. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] hash Buffer where the hash is to be written. + * \param hash_size Size of the \p hash buffer in bytes. + * \param[out] hash_length On success, the number of bytes + * that make up the hash value. This is always + * #PSA_HASH_LENGTH(\p alg). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p hash_size is too small + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_hash_compute( + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +/** Set up a multipart hash operation using Mbed TLS routines. + * + * \note The signature of this function is that of a PSA driver hash_setup + * entry point. This function behaves as a hash_setup entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * If an error occurs at any step after a call to mbedtls_psa_hash_setup(), the + * operation will need to be reset by a call to mbedtls_psa_hash_abort(). The + * core may call mbedtls_psa_hash_abort() at any time after the operation + * has been initialized. + * + * After a successful call to mbedtls_psa_hash_setup(), the core must + * eventually terminate the operation. The following events terminate an + * operation: + * - A successful call to mbedtls_psa_hash_finish() or mbedtls_psa_hash_verify(). + * - A call to mbedtls_psa_hash_abort(). + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized to all-zero and not yet be in use. + * \param alg The hash algorithm to compute (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_HASH(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_hash_setup( + mbedtls_psa_hash_operation_t *operation, + psa_algorithm_t alg); + +/** Clone an Mbed TLS hash operation. + * + * \note The signature of this function is that of a PSA driver hash_clone + * entry point. This function behaves as a hash_clone entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * This function copies the state of an ongoing hash operation to + * a new operation object. In other words, this function is equivalent + * to calling mbedtls_psa_hash_setup() on \p target_operation with the same + * algorithm that \p source_operation was set up for, then + * mbedtls_psa_hash_update() on \p target_operation with the same input that + * that was passed to \p source_operation. After this function returns, the + * two objects are independent, i.e. subsequent calls involving one of + * the objects do not affect the other object. + * + * \param[in] source_operation The active hash operation to clone. + * \param[in,out] target_operation The operation object to set up. + * It must be initialized but not active. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The \p source_operation state is not valid (it must be active). + * \retval #PSA_ERROR_BAD_STATE + * The \p target_operation state is not valid (it must be inactive). + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_hash_clone( + const mbedtls_psa_hash_operation_t *source_operation, + mbedtls_psa_hash_operation_t *target_operation); + +/** Add a message fragment to a multipart Mbed TLS hash operation. + * + * \note The signature of this function is that of a PSA driver hash_update + * entry point. This function behaves as a hash_update entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * The application must call mbedtls_psa_hash_setup() before calling this function. + * + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling mbedtls_psa_hash_abort(). + * + * \param[in,out] operation Active hash operation. + * \param[in] input Buffer containing the message fragment to hash. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_hash_update( + mbedtls_psa_hash_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Finish the calculation of the Mbed TLS-calculated hash of a message. + * + * \note The signature of this function is that of a PSA driver hash_finish + * entry point. This function behaves as a hash_finish entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * The application must call mbedtls_psa_hash_setup() before calling this function. + * This function calculates the hash of the message formed by concatenating + * the inputs passed to preceding calls to mbedtls_psa_hash_update(). + * + * When this function returns successfully, the operation becomes inactive. + * If this function returns an error status, the operation enters an error + * state and must be aborted by calling mbedtls_psa_hash_abort(). + * + * \param[in,out] operation Active hash operation. + * \param[out] hash Buffer where the hash is to be written. + * \param hash_size Size of the \p hash buffer in bytes. + * \param[out] hash_length On success, the number of bytes + * that make up the hash value. This is always + * #PSA_HASH_LENGTH(\c alg) where \c alg is the + * hash algorithm that is calculated. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active). + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p hash buffer is too small. You can determine a + * sufficient buffer size by calling #PSA_HASH_LENGTH(\c alg) + * where \c alg is the hash algorithm that is calculated. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_hash_finish( + mbedtls_psa_hash_operation_t *operation, + uint8_t *hash, + size_t hash_size, + size_t *hash_length); + +/** Abort an Mbed TLS hash operation. + * + * \note The signature of this function is that of a PSA driver hash_abort + * entry point. This function behaves as a hash_abort entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * mbedtls_psa_hash_setup() again. + * + * You may call this function any time after the operation object has + * been initialized by one of the methods described in #psa_hash_operation_t. + * + * In particular, calling mbedtls_psa_hash_abort() after the operation has been + * terminated by a call to mbedtls_psa_hash_abort(), mbedtls_psa_hash_finish() or + * mbedtls_psa_hash_verify() is safe and has no effect. + * + * \param[in,out] operation Initialized hash operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_hash_abort( + mbedtls_psa_hash_operation_t *operation); + +#endif /* PSA_CRYPTO_HASH_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_invasive.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_invasive.h index a900dd8..22d130b 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_invasive.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_invasive.h @@ -1,82 +1,82 @@ -/** - * \file psa_crypto_invasive.h - * - * \brief PSA cryptography module: invasive interfaces for test only. - * - * The interfaces in this file are intended for testing purposes only. - * They MUST NOT be made available to clients over IPC in integrations - * with isolation, and they SHOULD NOT be made available in library - * integrations except when building the library for testing. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_INVASIVE_H -#define PSA_CRYPTO_INVASIVE_H - -#include "mbedtls/build_info.h" - -#include "psa/crypto.h" -#include "common.h" - -#include "mbedtls/entropy.h" - -#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) -/** \brief Configure entropy sources. - * - * This function may only be called before a call to psa_crypto_init(), - * or after a call to mbedtls_psa_crypto_free() and before any - * subsequent call to psa_crypto_init(). - * - * This function is only intended for test purposes. The functionality - * it provides is also useful for system integrators, but - * system integrators should configure entropy drivers instead of - * breaking through to the Mbed TLS API. - * - * \param entropy_init Function to initialize the entropy context - * and set up the desired entropy sources. - * It is called by psa_crypto_init(). - * By default this is mbedtls_entropy_init(). - * This function cannot report failures directly. - * To indicate a failure, set the entropy context - * to a state where mbedtls_entropy_func() will - * return an error. - * \param entropy_free Function to free the entropy context - * and associated resources. - * It is called by mbedtls_psa_crypto_free(). - * By default this is mbedtls_entropy_free(). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_PERMITTED - * The caller does not have the permission to configure - * entropy sources. - * \retval #PSA_ERROR_BAD_STATE - * The library has already been initialized. - */ -psa_status_t mbedtls_psa_crypto_configure_entropy_sources( - void (* entropy_init)(mbedtls_entropy_context *ctx), - void (* entropy_free)(mbedtls_entropy_context *ctx)); -#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ - -#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_PSA_CRYPTO_C) -psa_status_t psa_mac_key_can_do( - psa_algorithm_t algorithm, - psa_key_type_t key_type); -#endif /* MBEDTLS_TEST_HOOKS && MBEDTLS_PSA_CRYPTO_C */ - -#endif /* PSA_CRYPTO_INVASIVE_H */ +/** + * \file psa_crypto_invasive.h + * + * \brief PSA cryptography module: invasive interfaces for test only. + * + * The interfaces in this file are intended for testing purposes only. + * They MUST NOT be made available to clients over IPC in integrations + * with isolation, and they SHOULD NOT be made available in library + * integrations except when building the library for testing. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_INVASIVE_H +#define PSA_CRYPTO_INVASIVE_H + +#include "mbedtls/build_info.h" + +#include "psa/crypto.h" +#include "common.h" + +#include "mbedtls/entropy.h" + +#if !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) +/** \brief Configure entropy sources. + * + * This function may only be called before a call to psa_crypto_init(), + * or after a call to mbedtls_psa_crypto_free() and before any + * subsequent call to psa_crypto_init(). + * + * This function is only intended for test purposes. The functionality + * it provides is also useful for system integrators, but + * system integrators should configure entropy drivers instead of + * breaking through to the Mbed TLS API. + * + * \param entropy_init Function to initialize the entropy context + * and set up the desired entropy sources. + * It is called by psa_crypto_init(). + * By default this is mbedtls_entropy_init(). + * This function cannot report failures directly. + * To indicate a failure, set the entropy context + * to a state where mbedtls_entropy_func() will + * return an error. + * \param entropy_free Function to free the entropy context + * and associated resources. + * It is called by mbedtls_psa_crypto_free(). + * By default this is mbedtls_entropy_free(). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_PERMITTED + * The caller does not have the permission to configure + * entropy sources. + * \retval #PSA_ERROR_BAD_STATE + * The library has already been initialized. + */ +psa_status_t mbedtls_psa_crypto_configure_entropy_sources( + void (* entropy_init)(mbedtls_entropy_context *ctx), + void (* entropy_free)(mbedtls_entropy_context *ctx)); +#endif /* !defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) */ + +#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_PSA_CRYPTO_C) +psa_status_t psa_mac_key_can_do( + psa_algorithm_t algorithm, + psa_key_type_t key_type); +#endif /* MBEDTLS_TEST_HOOKS && MBEDTLS_PSA_CRYPTO_C */ + +#endif /* PSA_CRYPTO_INVASIVE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_its.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_its.h index 3ceee49..9f69fa9 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_its.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_its.h @@ -1,143 +1,143 @@ -/** \file psa_crypto_its.h - * \brief Interface of trusted storage that crypto is built on. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_ITS_H -#define PSA_CRYPTO_ITS_H - -#include -#include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \brief Flags used when creating a data entry - */ -typedef uint32_t psa_storage_create_flags_t; - -/** \brief A type for UIDs used for identifying data - */ -typedef uint64_t psa_storage_uid_t; - -#define PSA_STORAGE_FLAG_NONE 0 /**< No flags to pass */ -#define PSA_STORAGE_FLAG_WRITE_ONCE (1 << 0) /**< The data associated with the uid will not be able to be modified or deleted. Intended to be used to set bits in `psa_storage_create_flags_t`*/ - -/** - * \brief A container for metadata associated with a specific uid - */ -struct psa_storage_info_t { - uint32_t size; /**< The size of the data associated with a uid **/ - psa_storage_create_flags_t flags; /**< The flags set when the uid was created **/ -}; - -/** Flag indicating that \ref psa_storage_create and \ref psa_storage_set_extended are supported */ -#define PSA_STORAGE_SUPPORT_SET_EXTENDED (1 << 0) - -#define PSA_ITS_API_VERSION_MAJOR 1 /**< The major version number of the PSA ITS API. It will be incremented on significant updates that may include breaking changes */ -#define PSA_ITS_API_VERSION_MINOR 1 /**< The minor version number of the PSA ITS API. It will be incremented in small updates that are unlikely to include breaking changes */ - -/** - * \brief create a new or modify an existing uid/value pair - * - * \param[in] uid the identifier for the data - * \param[in] data_length The size in bytes of the data in `p_data` - * \param[in] p_data A buffer containing the data - * \param[in] create_flags The flags that the data will be stored with - * - * \return A status indicating the success/failure of the operation - * - * \retval #PSA_SUCCESS The operation completed successfully - * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval #PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium - * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) - * is invalid, for example is `NULL` or references memory the caller cannot access - */ -psa_status_t psa_its_set(psa_storage_uid_t uid, - uint32_t data_length, - const void *p_data, - psa_storage_create_flags_t create_flags); - -/** - * \brief Retrieve the value associated with a provided uid - * - * \param[in] uid The uid value - * \param[in] data_offset The starting offset of the data requested - * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) - * \param[out] p_data The buffer where the data will be placed upon successful completion - * \param[out] p_data_length The amount of data returned in the p_data buffer - * - * - * \return A status indicating the success/failure of the operation - * - * \retval #PSA_SUCCESS The operation completed successfully - * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage - * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval #PSA_ERROR_DATA_CORRUPT The operation failed because stored data has been corrupted - * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) - * is invalid. For example is `NULL` or references memory the caller cannot access. - * In addition, this can also happen if an invalid offset was provided. - */ -psa_status_t psa_its_get(psa_storage_uid_t uid, - uint32_t data_offset, - uint32_t data_length, - void *p_data, - size_t *p_data_length); - -/** - * \brief Retrieve the metadata about the provided uid - * - * \param[in] uid The uid value - * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata - * - * \return A status indicating the success/failure of the operation - * - * \retval #PSA_SUCCESS The operation completed successfully - * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage - * \retval #PSA_ERROR_DATA_CORRUPT The operation failed because stored data has been corrupted - * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) - * is invalid, for example is `NULL` or references memory the caller cannot access - */ -psa_status_t psa_its_get_info(psa_storage_uid_t uid, - struct psa_storage_info_t *p_info); - -/** - * \brief Remove the provided key and its associated data from the storage - * - * \param[in] uid The uid value - * - * \return A status indicating the success/failure of the operation - * - * \retval #PSA_SUCCESS The operation completed successfully - * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage - * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE - * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - */ -psa_status_t psa_its_remove(psa_storage_uid_t uid); - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_ITS_H */ +/** \file psa_crypto_its.h + * \brief Interface of trusted storage that crypto is built on. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_ITS_H +#define PSA_CRYPTO_ITS_H + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief Flags used when creating a data entry + */ +typedef uint32_t psa_storage_create_flags_t; + +/** \brief A type for UIDs used for identifying data + */ +typedef uint64_t psa_storage_uid_t; + +#define PSA_STORAGE_FLAG_NONE 0 /**< No flags to pass */ +#define PSA_STORAGE_FLAG_WRITE_ONCE (1 << 0) /**< The data associated with the uid will not be able to be modified or deleted. Intended to be used to set bits in `psa_storage_create_flags_t`*/ + +/** + * \brief A container for metadata associated with a specific uid + */ +struct psa_storage_info_t { + uint32_t size; /**< The size of the data associated with a uid **/ + psa_storage_create_flags_t flags; /**< The flags set when the uid was created **/ +}; + +/** Flag indicating that \ref psa_storage_create and \ref psa_storage_set_extended are supported */ +#define PSA_STORAGE_SUPPORT_SET_EXTENDED (1 << 0) + +#define PSA_ITS_API_VERSION_MAJOR 1 /**< The major version number of the PSA ITS API. It will be incremented on significant updates that may include breaking changes */ +#define PSA_ITS_API_VERSION_MINOR 1 /**< The minor version number of the PSA ITS API. It will be incremented in small updates that are unlikely to include breaking changes */ + +/** + * \brief create a new or modify an existing uid/value pair + * + * \param[in] uid the identifier for the data + * \param[in] data_length The size in bytes of the data in `p_data` + * \param[in] p_data A buffer containing the data + * \param[in] create_flags The flags that the data will be stored with + * + * \return A status indicating the success/failure of the operation + * + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval #PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * is invalid, for example is `NULL` or references memory the caller cannot access + */ +psa_status_t psa_its_set(psa_storage_uid_t uid, + uint32_t data_length, + const void *p_data, + psa_storage_create_flags_t create_flags); + +/** + * \brief Retrieve the value associated with a provided uid + * + * \param[in] uid The uid value + * \param[in] data_offset The starting offset of the data requested + * \param[in] data_length the amount of data requested (and the minimum allocated size of the `p_data` buffer) + * \param[out] p_data The buffer where the data will be placed upon successful completion + * \param[out] p_data_length The amount of data returned in the p_data buffer + * + * + * \return A status indicating the success/failure of the operation + * + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_ERROR_DATA_CORRUPT The operation failed because stored data has been corrupted + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * is invalid. For example is `NULL` or references memory the caller cannot access. + * In addition, this can also happen if an invalid offset was provided. + */ +psa_status_t psa_its_get(psa_storage_uid_t uid, + uint32_t data_offset, + uint32_t data_length, + void *p_data, + size_t *p_data_length); + +/** + * \brief Retrieve the metadata about the provided uid + * + * \param[in] uid The uid value + * \param[out] p_info A pointer to the `psa_storage_info_t` struct that will be populated with the metadata + * + * \return A status indicating the success/failure of the operation + * + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval #PSA_ERROR_DATA_CORRUPT The operation failed because stored data has been corrupted + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * is invalid, for example is `NULL` or references memory the caller cannot access + */ +psa_status_t psa_its_get_info(psa_storage_uid_t uid, + struct psa_storage_info_t *p_info); + +/** + * \brief Remove the provided key and its associated data from the storage + * + * \param[in] uid The uid value + * + * \return A status indicating the success/failure of the operation + * + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_FLAG_WRITE_ONCE + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + */ +psa_status_t psa_its_remove(psa_storage_uid_t uid); + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_ITS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.c index 2f2c51d..81557be 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.c @@ -1,508 +1,508 @@ -/* - * PSA MAC layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa_crypto_core.h" -#include "psa_crypto_cipher.h" -#include "psa_crypto_mac.h" -#include - -#include -#include "mbedtls/constant_time.h" -#include - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) -static psa_status_t psa_hmac_abort_internal( - mbedtls_psa_hmac_operation_t *hmac) -{ - mbedtls_platform_zeroize(hmac->opad, sizeof(hmac->opad)); - return psa_hash_abort(&hmac->hash_ctx); -} - -static psa_status_t psa_hmac_setup_internal( - mbedtls_psa_hmac_operation_t *hmac, - const uint8_t *key, - size_t key_length, - psa_algorithm_t hash_alg) -{ - uint8_t ipad[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; - size_t i; - size_t hash_size = PSA_HASH_LENGTH(hash_alg); - size_t block_size = PSA_HASH_BLOCK_LENGTH(hash_alg); - psa_status_t status; - - hmac->alg = hash_alg; - - /* Sanity checks on block_size, to guarantee that there won't be a buffer - * overflow below. This should never trigger if the hash algorithm - * is implemented correctly. */ - /* The size checks against the ipad and opad buffers cannot be written - * `block_size > sizeof( ipad ) || block_size > sizeof( hmac->opad )` - * because that triggers -Wlogical-op on GCC 7.3. */ - if (block_size > sizeof(ipad)) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (block_size > sizeof(hmac->opad)) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (block_size < hash_size) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (key_length > block_size) { - status = psa_hash_compute(hash_alg, key, key_length, - ipad, sizeof(ipad), &key_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - } - /* A 0-length key is not commonly used in HMAC when used as a MAC, - * but it is permitted. It is common when HMAC is used in HKDF, for - * example. Don't call `memcpy` in the 0-length because `key` could be - * an invalid pointer which would make the behavior undefined. */ - else if (key_length != 0) { - memcpy(ipad, key, key_length); - } - - /* ipad contains the key followed by garbage. Xor and fill with 0x36 - * to create the ipad value. */ - for (i = 0; i < key_length; i++) { - ipad[i] ^= 0x36; - } - memset(ipad + key_length, 0x36, block_size - key_length); - - /* Copy the key material from ipad to opad, flipping the requisite bits, - * and filling the rest of opad with the requisite constant. */ - for (i = 0; i < key_length; i++) { - hmac->opad[i] = ipad[i] ^ 0x36 ^ 0x5C; - } - memset(hmac->opad + key_length, 0x5C, block_size - key_length); - - status = psa_hash_setup(&hmac->hash_ctx, hash_alg); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - status = psa_hash_update(&hmac->hash_ctx, ipad, block_size); - -cleanup: - mbedtls_platform_zeroize(ipad, sizeof(ipad)); - - return status; -} - -static psa_status_t psa_hmac_update_internal( - mbedtls_psa_hmac_operation_t *hmac, - const uint8_t *data, - size_t data_length) -{ - return psa_hash_update(&hmac->hash_ctx, data, data_length); -} - -static psa_status_t psa_hmac_finish_internal( - mbedtls_psa_hmac_operation_t *hmac, - uint8_t *mac, - size_t mac_size) -{ - uint8_t tmp[PSA_HASH_MAX_SIZE]; - psa_algorithm_t hash_alg = hmac->alg; - size_t hash_size = 0; - size_t block_size = PSA_HASH_BLOCK_LENGTH(hash_alg); - psa_status_t status; - - status = psa_hash_finish(&hmac->hash_ctx, tmp, sizeof(tmp), &hash_size); - if (status != PSA_SUCCESS) { - return status; - } - /* From here on, tmp needs to be wiped. */ - - status = psa_hash_setup(&hmac->hash_ctx, hash_alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_hash_update(&hmac->hash_ctx, hmac->opad, block_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_hash_update(&hmac->hash_ctx, tmp, hash_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_hash_finish(&hmac->hash_ctx, tmp, sizeof(tmp), &hash_size); - if (status != PSA_SUCCESS) { - goto exit; - } - - memcpy(mac, tmp, mac_size); - -exit: - mbedtls_platform_zeroize(tmp, hash_size); - return status; -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) -static psa_status_t cmac_setup(mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - -#if defined(PSA_WANT_KEY_TYPE_DES) - /* Mbed TLS CMAC does not accept 3DES with only two keys, nor does it accept - * to do CMAC with pure DES, so return NOT_SUPPORTED here. */ - if (psa_get_key_type(attributes) == PSA_KEY_TYPE_DES && - (psa_get_key_bits(attributes) == 64 || - psa_get_key_bits(attributes) == 128)) { - return PSA_ERROR_NOT_SUPPORTED; - } -#endif - - const mbedtls_cipher_info_t *cipher_info = - mbedtls_cipher_info_from_psa( - PSA_ALG_CMAC, - psa_get_key_type(attributes), - psa_get_key_bits(attributes), - NULL); - - if (cipher_info == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - ret = mbedtls_cipher_setup(&operation->ctx.cmac, cipher_info); - if (ret != 0) { - goto exit; - } - - ret = mbedtls_cipher_cmac_starts(&operation->ctx.cmac, - key_buffer, - psa_get_key_bits(attributes)); -exit: - return mbedtls_to_psa_error(ret); -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - -/* Initialize this driver's MAC operation structure. Once this function has been - * called, mbedtls_psa_mac_abort can run and will do the right thing. */ -static psa_status_t mac_init( - mbedtls_psa_mac_operation_t *operation, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - operation->alg = alg; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { - mbedtls_cipher_init(&operation->ctx.cmac); - status = PSA_SUCCESS; - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->alg)) { - /* We'll set up the hash operation later in psa_hmac_setup_internal. */ - operation->ctx.hmac.alg = 0; - status = PSA_SUCCESS; - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - { - (void) operation; - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status != PSA_SUCCESS) { - memset(operation, 0, sizeof(*operation)); - } - return status; -} - -psa_status_t mbedtls_psa_mac_abort(mbedtls_psa_mac_operation_t *operation) -{ - if (operation->alg == 0) { - /* The object has (apparently) been initialized but it is not - * in use. It's ok to call abort on such an object, and there's - * nothing to do. */ - return PSA_SUCCESS; - } else -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { - mbedtls_cipher_free(&operation->ctx.cmac); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->alg)) { - psa_hmac_abort_internal(&operation->ctx.hmac); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - { - /* Sanity check (shouldn't happen: operation->alg should - * always have been initialized to a valid value). */ - goto bad_state; - } - - operation->alg = 0; - - return PSA_SUCCESS; - -bad_state: - /* If abort is called on an uninitialized object, we can't trust - * anything. Wipe the object in case it contains confidential data. - * This may result in a memory leak if a pointer gets overwritten, - * but it's too late to do anything about this. */ - memset(operation, 0, sizeof(*operation)); - return PSA_ERROR_BAD_STATE; -} - -static psa_status_t psa_mac_setup(mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - /* A context must be freshly initialized before it can be set up. */ - if (operation->alg != 0) { - return PSA_ERROR_BAD_STATE; - } - - status = mac_init(operation, alg); - if (status != PSA_SUCCESS) { - return status; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - if (PSA_ALG_FULL_LENGTH_MAC(alg) == PSA_ALG_CMAC) { - /* Key buffer size for CMAC is dictated by the key bits set on the - * attributes, and previously validated by the core on key import. */ - (void) key_buffer_size; - status = cmac_setup(operation, attributes, key_buffer); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) - if (PSA_ALG_IS_HMAC(alg)) { - status = psa_hmac_setup_internal(&operation->ctx.hmac, - key_buffer, - key_buffer_size, - PSA_ALG_HMAC_GET_HASH(alg)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - { - (void) attributes; - (void) key_buffer; - (void) key_buffer_size; - status = PSA_ERROR_NOT_SUPPORTED; - } - - if (status != PSA_SUCCESS) { - mbedtls_psa_mac_abort(operation); - } - - return status; -} - -psa_status_t mbedtls_psa_mac_sign_setup( - mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - return psa_mac_setup(operation, attributes, - key_buffer, key_buffer_size, alg); -} - -psa_status_t mbedtls_psa_mac_verify_setup( - mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg) -{ - return psa_mac_setup(operation, attributes, - key_buffer, key_buffer_size, alg); -} - -psa_status_t mbedtls_psa_mac_update( - mbedtls_psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length) -{ - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { - return mbedtls_to_psa_error( - mbedtls_cipher_cmac_update(&operation->ctx.cmac, - input, input_length)); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->alg)) { - return psa_hmac_update_internal(&operation->ctx.hmac, - input, input_length); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - { - /* This shouldn't happen if `operation` was initialized by - * a setup function. */ - (void) input; - (void) input_length; - return PSA_ERROR_BAD_STATE; - } -} - -static psa_status_t psa_mac_finish_internal( - mbedtls_psa_mac_operation_t *operation, - uint8_t *mac, size_t mac_size) -{ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) - if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { - uint8_t tmp[PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE]; - int ret = mbedtls_cipher_cmac_finish(&operation->ctx.cmac, tmp); - if (ret == 0) { - memcpy(mac, tmp, mac_size); - } - mbedtls_platform_zeroize(tmp, sizeof(tmp)); - return mbedtls_to_psa_error(ret); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) - if (PSA_ALG_IS_HMAC(operation->alg)) { - return psa_hmac_finish_internal(&operation->ctx.hmac, - mac, mac_size); - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ - { - /* This shouldn't happen if `operation` was initialized by - * a setup function. */ - (void) operation; - (void) mac; - (void) mac_size; - return PSA_ERROR_BAD_STATE; - } -} - -psa_status_t mbedtls_psa_mac_sign_finish( - mbedtls_psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - - status = psa_mac_finish_internal(operation, mac, mac_size); - if (status == PSA_SUCCESS) { - *mac_length = mac_size; - } - - return status; -} - -psa_status_t mbedtls_psa_mac_verify_finish( - mbedtls_psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length) -{ - uint8_t actual_mac[PSA_MAC_MAX_SIZE]; - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - if (operation->alg == 0) { - return PSA_ERROR_BAD_STATE; - } - - /* Consistency check: requested MAC length fits our local buffer */ - if (mac_length > sizeof(actual_mac)) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - status = psa_mac_finish_internal(operation, actual_mac, mac_length); - if (status != PSA_SUCCESS) { - goto cleanup; - } - - if (mbedtls_ct_memcmp(mac, actual_mac, mac_length) != 0) { - status = PSA_ERROR_INVALID_SIGNATURE; - } - -cleanup: - mbedtls_platform_zeroize(actual_mac, sizeof(actual_mac)); - - return status; -} - -psa_status_t mbedtls_psa_mac_compute( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_psa_mac_operation_t operation = MBEDTLS_PSA_MAC_OPERATION_INIT; - - status = psa_mac_setup(&operation, - attributes, key_buffer, key_buffer_size, - alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (input_length > 0) { - status = mbedtls_psa_mac_update(&operation, input, input_length); - if (status != PSA_SUCCESS) { - goto exit; - } - } - - status = psa_mac_finish_internal(&operation, mac, mac_size); - if (status == PSA_SUCCESS) { - *mac_length = mac_size; - } - -exit: - mbedtls_psa_mac_abort(&operation); - - return status; -} - -#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC || MBEDTLS_PSA_BUILTIN_ALG_CMAC */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA MAC layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa_crypto_core.h" +#include "psa_crypto_cipher.h" +#include "psa_crypto_mac.h" +#include + +#include +#include "mbedtls/constant_time.h" +#include + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) +static psa_status_t psa_hmac_abort_internal( + mbedtls_psa_hmac_operation_t *hmac) +{ + mbedtls_platform_zeroize(hmac->opad, sizeof(hmac->opad)); + return psa_hash_abort(&hmac->hash_ctx); +} + +static psa_status_t psa_hmac_setup_internal( + mbedtls_psa_hmac_operation_t *hmac, + const uint8_t *key, + size_t key_length, + psa_algorithm_t hash_alg) +{ + uint8_t ipad[PSA_HMAC_MAX_HASH_BLOCK_SIZE]; + size_t i; + size_t hash_size = PSA_HASH_LENGTH(hash_alg); + size_t block_size = PSA_HASH_BLOCK_LENGTH(hash_alg); + psa_status_t status; + + hmac->alg = hash_alg; + + /* Sanity checks on block_size, to guarantee that there won't be a buffer + * overflow below. This should never trigger if the hash algorithm + * is implemented correctly. */ + /* The size checks against the ipad and opad buffers cannot be written + * `block_size > sizeof( ipad ) || block_size > sizeof( hmac->opad )` + * because that triggers -Wlogical-op on GCC 7.3. */ + if (block_size > sizeof(ipad)) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (block_size > sizeof(hmac->opad)) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (block_size < hash_size) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (key_length > block_size) { + status = psa_hash_compute(hash_alg, key, key_length, + ipad, sizeof(ipad), &key_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + } + /* A 0-length key is not commonly used in HMAC when used as a MAC, + * but it is permitted. It is common when HMAC is used in HKDF, for + * example. Don't call `memcpy` in the 0-length because `key` could be + * an invalid pointer which would make the behavior undefined. */ + else if (key_length != 0) { + memcpy(ipad, key, key_length); + } + + /* ipad contains the key followed by garbage. Xor and fill with 0x36 + * to create the ipad value. */ + for (i = 0; i < key_length; i++) { + ipad[i] ^= 0x36; + } + memset(ipad + key_length, 0x36, block_size - key_length); + + /* Copy the key material from ipad to opad, flipping the requisite bits, + * and filling the rest of opad with the requisite constant. */ + for (i = 0; i < key_length; i++) { + hmac->opad[i] = ipad[i] ^ 0x36 ^ 0x5C; + } + memset(hmac->opad + key_length, 0x5C, block_size - key_length); + + status = psa_hash_setup(&hmac->hash_ctx, hash_alg); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + status = psa_hash_update(&hmac->hash_ctx, ipad, block_size); + +cleanup: + mbedtls_platform_zeroize(ipad, sizeof(ipad)); + + return status; +} + +static psa_status_t psa_hmac_update_internal( + mbedtls_psa_hmac_operation_t *hmac, + const uint8_t *data, + size_t data_length) +{ + return psa_hash_update(&hmac->hash_ctx, data, data_length); +} + +static psa_status_t psa_hmac_finish_internal( + mbedtls_psa_hmac_operation_t *hmac, + uint8_t *mac, + size_t mac_size) +{ + uint8_t tmp[PSA_HASH_MAX_SIZE]; + psa_algorithm_t hash_alg = hmac->alg; + size_t hash_size = 0; + size_t block_size = PSA_HASH_BLOCK_LENGTH(hash_alg); + psa_status_t status; + + status = psa_hash_finish(&hmac->hash_ctx, tmp, sizeof(tmp), &hash_size); + if (status != PSA_SUCCESS) { + return status; + } + /* From here on, tmp needs to be wiped. */ + + status = psa_hash_setup(&hmac->hash_ctx, hash_alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_hash_update(&hmac->hash_ctx, hmac->opad, block_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_hash_update(&hmac->hash_ctx, tmp, hash_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_hash_finish(&hmac->hash_ctx, tmp, sizeof(tmp), &hash_size); + if (status != PSA_SUCCESS) { + goto exit; + } + + memcpy(mac, tmp, mac_size); + +exit: + mbedtls_platform_zeroize(tmp, hash_size); + return status; +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) +static psa_status_t cmac_setup(mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + +#if defined(PSA_WANT_KEY_TYPE_DES) + /* Mbed TLS CMAC does not accept 3DES with only two keys, nor does it accept + * to do CMAC with pure DES, so return NOT_SUPPORTED here. */ + if (psa_get_key_type(attributes) == PSA_KEY_TYPE_DES && + (psa_get_key_bits(attributes) == 64 || + psa_get_key_bits(attributes) == 128)) { + return PSA_ERROR_NOT_SUPPORTED; + } +#endif + + const mbedtls_cipher_info_t *cipher_info = + mbedtls_cipher_info_from_psa( + PSA_ALG_CMAC, + psa_get_key_type(attributes), + psa_get_key_bits(attributes), + NULL); + + if (cipher_info == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + ret = mbedtls_cipher_setup(&operation->ctx.cmac, cipher_info); + if (ret != 0) { + goto exit; + } + + ret = mbedtls_cipher_cmac_starts(&operation->ctx.cmac, + key_buffer, + psa_get_key_bits(attributes)); +exit: + return mbedtls_to_psa_error(ret); +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + +/* Initialize this driver's MAC operation structure. Once this function has been + * called, mbedtls_psa_mac_abort can run and will do the right thing. */ +static psa_status_t mac_init( + mbedtls_psa_mac_operation_t *operation, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + operation->alg = alg; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { + mbedtls_cipher_init(&operation->ctx.cmac); + status = PSA_SUCCESS; + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->alg)) { + /* We'll set up the hash operation later in psa_hmac_setup_internal. */ + operation->ctx.hmac.alg = 0; + status = PSA_SUCCESS; + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + { + (void) operation; + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status != PSA_SUCCESS) { + memset(operation, 0, sizeof(*operation)); + } + return status; +} + +psa_status_t mbedtls_psa_mac_abort(mbedtls_psa_mac_operation_t *operation) +{ + if (operation->alg == 0) { + /* The object has (apparently) been initialized but it is not + * in use. It's ok to call abort on such an object, and there's + * nothing to do. */ + return PSA_SUCCESS; + } else +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { + mbedtls_cipher_free(&operation->ctx.cmac); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->alg)) { + psa_hmac_abort_internal(&operation->ctx.hmac); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + { + /* Sanity check (shouldn't happen: operation->alg should + * always have been initialized to a valid value). */ + goto bad_state; + } + + operation->alg = 0; + + return PSA_SUCCESS; + +bad_state: + /* If abort is called on an uninitialized object, we can't trust + * anything. Wipe the object in case it contains confidential data. + * This may result in a memory leak if a pointer gets overwritten, + * but it's too late to do anything about this. */ + memset(operation, 0, sizeof(*operation)); + return PSA_ERROR_BAD_STATE; +} + +static psa_status_t psa_mac_setup(mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + /* A context must be freshly initialized before it can be set up. */ + if (operation->alg != 0) { + return PSA_ERROR_BAD_STATE; + } + + status = mac_init(operation, alg); + if (status != PSA_SUCCESS) { + return status; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + if (PSA_ALG_FULL_LENGTH_MAC(alg) == PSA_ALG_CMAC) { + /* Key buffer size for CMAC is dictated by the key bits set on the + * attributes, and previously validated by the core on key import. */ + (void) key_buffer_size; + status = cmac_setup(operation, attributes, key_buffer); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) + if (PSA_ALG_IS_HMAC(alg)) { + status = psa_hmac_setup_internal(&operation->ctx.hmac, + key_buffer, + key_buffer_size, + PSA_ALG_HMAC_GET_HASH(alg)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + { + (void) attributes; + (void) key_buffer; + (void) key_buffer_size; + status = PSA_ERROR_NOT_SUPPORTED; + } + + if (status != PSA_SUCCESS) { + mbedtls_psa_mac_abort(operation); + } + + return status; +} + +psa_status_t mbedtls_psa_mac_sign_setup( + mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + return psa_mac_setup(operation, attributes, + key_buffer, key_buffer_size, alg); +} + +psa_status_t mbedtls_psa_mac_verify_setup( + mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg) +{ + return psa_mac_setup(operation, attributes, + key_buffer, key_buffer_size, alg); +} + +psa_status_t mbedtls_psa_mac_update( + mbedtls_psa_mac_operation_t *operation, + const uint8_t *input, + size_t input_length) +{ + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { + return mbedtls_to_psa_error( + mbedtls_cipher_cmac_update(&operation->ctx.cmac, + input, input_length)); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->alg)) { + return psa_hmac_update_internal(&operation->ctx.hmac, + input, input_length); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + { + /* This shouldn't happen if `operation` was initialized by + * a setup function. */ + (void) input; + (void) input_length; + return PSA_ERROR_BAD_STATE; + } +} + +static psa_status_t psa_mac_finish_internal( + mbedtls_psa_mac_operation_t *operation, + uint8_t *mac, size_t mac_size) +{ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_CMAC) + if (PSA_ALG_FULL_LENGTH_MAC(operation->alg) == PSA_ALG_CMAC) { + uint8_t tmp[PSA_BLOCK_CIPHER_BLOCK_MAX_SIZE]; + int ret = mbedtls_cipher_cmac_finish(&operation->ctx.cmac, tmp); + if (ret == 0) { + memcpy(mac, tmp, mac_size); + } + mbedtls_platform_zeroize(tmp, sizeof(tmp)); + return mbedtls_to_psa_error(ret); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_CMAC */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) + if (PSA_ALG_IS_HMAC(operation->alg)) { + return psa_hmac_finish_internal(&operation->ctx.hmac, + mac, mac_size); + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ + { + /* This shouldn't happen if `operation` was initialized by + * a setup function. */ + (void) operation; + (void) mac; + (void) mac_size; + return PSA_ERROR_BAD_STATE; + } +} + +psa_status_t mbedtls_psa_mac_sign_finish( + mbedtls_psa_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + status = psa_mac_finish_internal(operation, mac, mac_size); + if (status == PSA_SUCCESS) { + *mac_length = mac_size; + } + + return status; +} + +psa_status_t mbedtls_psa_mac_verify_finish( + mbedtls_psa_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length) +{ + uint8_t actual_mac[PSA_MAC_MAX_SIZE]; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + if (operation->alg == 0) { + return PSA_ERROR_BAD_STATE; + } + + /* Consistency check: requested MAC length fits our local buffer */ + if (mac_length > sizeof(actual_mac)) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + status = psa_mac_finish_internal(operation, actual_mac, mac_length); + if (status != PSA_SUCCESS) { + goto cleanup; + } + + if (mbedtls_ct_memcmp(mac, actual_mac, mac_length) != 0) { + status = PSA_ERROR_INVALID_SIGNATURE; + } + +cleanup: + mbedtls_platform_zeroize(actual_mac, sizeof(actual_mac)); + + return status; +} + +psa_status_t mbedtls_psa_mac_compute( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_psa_mac_operation_t operation = MBEDTLS_PSA_MAC_OPERATION_INIT; + + status = psa_mac_setup(&operation, + attributes, key_buffer, key_buffer_size, + alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (input_length > 0) { + status = mbedtls_psa_mac_update(&operation, input, input_length); + if (status != PSA_SUCCESS) { + goto exit; + } + } + + status = psa_mac_finish_internal(&operation, mac, mac_size); + if (status == PSA_SUCCESS) { + *mac_length = mac_size; + } + +exit: + mbedtls_psa_mac_abort(&operation); + + return status; +} + +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC || MBEDTLS_PSA_BUILTIN_ALG_CMAC */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.h index 4f8024a..4e1f199 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_mac.h @@ -1,276 +1,276 @@ -/* - * PSA MAC layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_MAC_H -#define PSA_CRYPTO_MAC_H - -#include - -/** Calculate the MAC (message authentication code) of a message using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver mac_compute - * entry point. This function behaves as a mac_compute entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key to use for - * computing the MAC. This buffer contains the key - * in export representation as defined by - * psa_export_key() (i.e. the raw key bytes). - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * \param[in] input Buffer containing the input message. - * \param input_length Size of the \p input buffer in bytes. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Size of the \p mac buffer in bytes. - * \param[out] mac_length On success, the number of bytes - * that make up the MAC value. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * \p mac_size is too small - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_mac_compute( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Set up a multipart MAC calculation operation using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver mac_sign_setup - * entry point. This function behaves as a mac_sign_setup entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized and not yet in use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key to use for - * computing the MAC. This buffer contains the key - * in export representation as defined by - * psa_export_key() (i.e. the raw key bytes). - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive). - */ -psa_status_t mbedtls_psa_mac_sign_setup( - mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -/** Set up a multipart MAC verification operation using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver mac_verify_setup - * entry point. This function behaves as a mac_verify_setup entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized and not yet in use. - * \param[in] attributes The attributes of the key to use for the - * operation. - * \param[in] key_buffer The buffer containing the key to use for - * computing the MAC. This buffer contains the key - * in export representation as defined by - * psa_export_key() (i.e. the raw key bytes). - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value - * such that #PSA_ALG_IS_MAC(\p alg) is true). - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * \p alg is not supported. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be inactive). - */ -psa_status_t mbedtls_psa_mac_verify_setup( - mbedtls_psa_mac_operation_t *operation, - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg); - -/** Add a message fragment to a multipart MAC operation using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver mac_update - * entry point. This function behaves as a mac_update entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * The PSA core calls mbedtls_psa_mac_sign_setup() or - * mbedtls_psa_mac_verify_setup() before calling this function. - * - * If this function returns an error status, the PSA core aborts the - * operation by calling mbedtls_psa_mac_abort(). - * - * \param[in,out] operation Active MAC operation. - * \param[in] input Buffer containing the message fragment to add to - * the MAC calculation. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be active). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_mac_update( - mbedtls_psa_mac_operation_t *operation, - const uint8_t *input, - size_t input_length); - -/** Finish the calculation of the MAC of a message using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver mac_sign_finish - * entry point. This function behaves as a mac_sign_finish entry point as - * defined in the PSA driver interface specification for transparent - * drivers. - * - * The PSA core calls mbedtls_psa_mac_sign_setup() before calling this function. - * This function calculates the MAC of the message formed by concatenating - * the inputs passed to preceding calls to mbedtls_psa_mac_update(). - * - * Whether this function returns successfully or not, the PSA core subsequently - * aborts the operation by calling mbedtls_psa_mac_abort(). - * - * \param[in,out] operation Active MAC operation. - * \param[out] mac Buffer where the MAC value is to be written. - * \param mac_size Output size requested for the MAC algorithm. The PSA - * core guarantees this is a valid MAC length for the - * algorithm and key combination passed to - * mbedtls_psa_mac_sign_setup(). It also guarantees the - * \p mac buffer is large enough to contain the - * requested output size. - * \param[out] mac_length On success, the number of bytes output to buffer - * \p mac, which will be equal to the requested length - * \p mac_size. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac sign - * operation). - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p mac buffer is too small. A sufficient buffer size - * can be determined by calling PSA_MAC_LENGTH(). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_mac_sign_finish( - mbedtls_psa_mac_operation_t *operation, - uint8_t *mac, - size_t mac_size, - size_t *mac_length); - -/** Finish the calculation of the MAC of a message and compare it with - * an expected value using Mbed TLS. - * - * \note The signature of this function is that of a PSA driver - * mac_verify_finish entry point. This function behaves as a - * mac_verify_finish entry point as defined in the PSA driver interface - * specification for transparent drivers. - * - * The PSA core calls mbedtls_psa_mac_verify_setup() before calling this - * function. This function calculates the MAC of the message formed by - * concatenating the inputs passed to preceding calls to - * mbedtls_psa_mac_update(). It then compares the calculated MAC with the - * expected MAC passed as a parameter to this function. - * - * Whether this function returns successfully or not, the PSA core subsequently - * aborts the operation by calling mbedtls_psa_mac_abort(). - * - * \param[in,out] operation Active MAC operation. - * \param[in] mac Buffer containing the expected MAC value. - * \param mac_length Length in bytes of the expected MAC value. The PSA - * core guarantees that this length is a valid MAC - * length for the algorithm and key combination passed - * to mbedtls_psa_mac_verify_setup(). - * - * \retval #PSA_SUCCESS - * The expected MAC is identical to the actual MAC of the message. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The MAC of the message was calculated successfully, but it - * differs from the expected MAC. - * \retval #PSA_ERROR_BAD_STATE - * The operation state is not valid (it must be an active mac verify - * operation). - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_mac_verify_finish( - mbedtls_psa_mac_operation_t *operation, - const uint8_t *mac, - size_t mac_length); - -/** Abort a MAC operation using Mbed TLS. - * - * Aborting an operation frees all associated resources except for the - * \p operation structure itself. Once aborted, the operation object - * can be reused for another operation by calling - * mbedtls_psa_mac_sign_setup() or mbedtls_psa_mac_verify_setup() again. - * - * The PSA core may call this function any time after the operation object has - * been initialized by one of the methods described in - * #mbedtls_psa_mac_operation_t. - * - * In particular, calling mbedtls_psa_mac_abort() after the operation has been - * terminated by a call to mbedtls_psa_mac_abort(), - * mbedtls_psa_mac_sign_finish() or mbedtls_psa_mac_verify_finish() is safe and - * has no effect. - * - * \param[in,out] operation Initialized MAC operation. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_mac_abort( - mbedtls_psa_mac_operation_t *operation); - -#endif /* PSA_CRYPTO_MAC_H */ +/* + * PSA MAC layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_MAC_H +#define PSA_CRYPTO_MAC_H + +#include + +/** Calculate the MAC (message authentication code) of a message using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver mac_compute + * entry point. This function behaves as a mac_compute entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key to use for + * computing the MAC. This buffer contains the key + * in export representation as defined by + * psa_export_key() (i.e. the raw key bytes). + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * \param[in] input Buffer containing the input message. + * \param input_length Size of the \p input buffer in bytes. + * \param[out] mac Buffer where the MAC value is to be written. + * \param mac_size Size of the \p mac buffer in bytes. + * \param[out] mac_length On success, the number of bytes + * that make up the MAC value. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * \p mac_size is too small + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_mac_compute( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +/** Set up a multipart MAC calculation operation using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver mac_sign_setup + * entry point. This function behaves as a mac_sign_setup entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized and not yet in use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key to use for + * computing the MAC. This buffer contains the key + * in export representation as defined by + * psa_export_key() (i.e. the raw key bytes). + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive). + */ +psa_status_t mbedtls_psa_mac_sign_setup( + mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +/** Set up a multipart MAC verification operation using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver mac_verify_setup + * entry point. This function behaves as a mac_verify_setup entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized and not yet in use. + * \param[in] attributes The attributes of the key to use for the + * operation. + * \param[in] key_buffer The buffer containing the key to use for + * computing the MAC. This buffer contains the key + * in export representation as defined by + * psa_export_key() (i.e. the raw key bytes). + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param alg The MAC algorithm to use (\c PSA_ALG_XXX value + * such that #PSA_ALG_IS_MAC(\p alg) is true). + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * \p alg is not supported. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be inactive). + */ +psa_status_t mbedtls_psa_mac_verify_setup( + mbedtls_psa_mac_operation_t *operation, + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg); + +/** Add a message fragment to a multipart MAC operation using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver mac_update + * entry point. This function behaves as a mac_update entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * The PSA core calls mbedtls_psa_mac_sign_setup() or + * mbedtls_psa_mac_verify_setup() before calling this function. + * + * If this function returns an error status, the PSA core aborts the + * operation by calling mbedtls_psa_mac_abort(). + * + * \param[in,out] operation Active MAC operation. + * \param[in] input Buffer containing the message fragment to add to + * the MAC calculation. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be active). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_mac_update( + mbedtls_psa_mac_operation_t *operation, + const uint8_t *input, + size_t input_length); + +/** Finish the calculation of the MAC of a message using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver mac_sign_finish + * entry point. This function behaves as a mac_sign_finish entry point as + * defined in the PSA driver interface specification for transparent + * drivers. + * + * The PSA core calls mbedtls_psa_mac_sign_setup() before calling this function. + * This function calculates the MAC of the message formed by concatenating + * the inputs passed to preceding calls to mbedtls_psa_mac_update(). + * + * Whether this function returns successfully or not, the PSA core subsequently + * aborts the operation by calling mbedtls_psa_mac_abort(). + * + * \param[in,out] operation Active MAC operation. + * \param[out] mac Buffer where the MAC value is to be written. + * \param mac_size Output size requested for the MAC algorithm. The PSA + * core guarantees this is a valid MAC length for the + * algorithm and key combination passed to + * mbedtls_psa_mac_sign_setup(). It also guarantees the + * \p mac buffer is large enough to contain the + * requested output size. + * \param[out] mac_length On success, the number of bytes output to buffer + * \p mac, which will be equal to the requested length + * \p mac_size. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active mac sign + * operation). + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p mac buffer is too small. A sufficient buffer size + * can be determined by calling PSA_MAC_LENGTH(). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_mac_sign_finish( + mbedtls_psa_mac_operation_t *operation, + uint8_t *mac, + size_t mac_size, + size_t *mac_length); + +/** Finish the calculation of the MAC of a message and compare it with + * an expected value using Mbed TLS. + * + * \note The signature of this function is that of a PSA driver + * mac_verify_finish entry point. This function behaves as a + * mac_verify_finish entry point as defined in the PSA driver interface + * specification for transparent drivers. + * + * The PSA core calls mbedtls_psa_mac_verify_setup() before calling this + * function. This function calculates the MAC of the message formed by + * concatenating the inputs passed to preceding calls to + * mbedtls_psa_mac_update(). It then compares the calculated MAC with the + * expected MAC passed as a parameter to this function. + * + * Whether this function returns successfully or not, the PSA core subsequently + * aborts the operation by calling mbedtls_psa_mac_abort(). + * + * \param[in,out] operation Active MAC operation. + * \param[in] mac Buffer containing the expected MAC value. + * \param mac_length Length in bytes of the expected MAC value. The PSA + * core guarantees that this length is a valid MAC + * length for the algorithm and key combination passed + * to mbedtls_psa_mac_verify_setup(). + * + * \retval #PSA_SUCCESS + * The expected MAC is identical to the actual MAC of the message. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The MAC of the message was calculated successfully, but it + * differs from the expected MAC. + * \retval #PSA_ERROR_BAD_STATE + * The operation state is not valid (it must be an active mac verify + * operation). + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_mac_verify_finish( + mbedtls_psa_mac_operation_t *operation, + const uint8_t *mac, + size_t mac_length); + +/** Abort a MAC operation using Mbed TLS. + * + * Aborting an operation frees all associated resources except for the + * \p operation structure itself. Once aborted, the operation object + * can be reused for another operation by calling + * mbedtls_psa_mac_sign_setup() or mbedtls_psa_mac_verify_setup() again. + * + * The PSA core may call this function any time after the operation object has + * been initialized by one of the methods described in + * #mbedtls_psa_mac_operation_t. + * + * In particular, calling mbedtls_psa_mac_abort() after the operation has been + * terminated by a call to mbedtls_psa_mac_abort(), + * mbedtls_psa_mac_sign_finish() or mbedtls_psa_mac_verify_finish() is safe and + * has no effect. + * + * \param[in,out] operation Initialized MAC operation. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_mac_abort( + mbedtls_psa_mac_operation_t *operation); + +#endif /* PSA_CRYPTO_MAC_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.c index 7a904d9..d907c34 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.c @@ -1,583 +1,583 @@ -/* - * PSA PAKE layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa_crypto_core.h" -#include "psa_crypto_pake.h" -#include "psa_crypto_slot_management.h" - -#include -#include "psa_util_internal.h" - -#include -#include -#include - -/* - * State sequence: - * - * psa_pake_setup() - * | - * |-- In any order: - * | | psa_pake_set_password_key() - * | | psa_pake_set_user() - * | | psa_pake_set_peer() - * | | psa_pake_set_role() - * | - * |--- In any order: (First round input before or after first round output) - * | | - * | |------ In Order - * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) - * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) - * | | - * | |------ In Order: - * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) - * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) - * | - * |--- In any order: (Second round input before or after second round output) - * | | - * | |------ In Order - * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) - * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) - * | | - * | |------ In Order: - * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) - * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) - * | - * psa_pake_get_implicit_key() - * psa_pake_abort() - */ - -/* - * Possible sequence of calls to implementation: - * - * |--- In any order: - * | | - * | |------ In Order - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_KEY_SHARE) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_ZK_PUBLIC) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_ZK_PROOF) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_KEY_SHARE) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_ZK_PUBLIC) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_ZK_PROOF) - * | | - * | |------ In Order: - * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_KEY_SHARE) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_ZK_PUBLIC) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_ZK_PROOF) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_KEY_SHARE) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_ZK_PUBLIC) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_ZK_PROOF) - * | - * |--- In any order: - * | | - * | |------ In Order - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_KEY_SHARE) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_ZK_PUBLIC) - * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_ZK_PROOF) - * | | - * | |------ In Order: - * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_KEY_SHARE) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_ZK_PUBLIC) - * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_ZK_PROOF) - */ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) -static psa_status_t mbedtls_ecjpake_to_psa_error(int ret) -{ - switch (ret) { - case MBEDTLS_ERR_MPI_BAD_INPUT_DATA: - case MBEDTLS_ERR_ECP_BAD_INPUT_DATA: - case MBEDTLS_ERR_ECP_INVALID_KEY: - case MBEDTLS_ERR_ECP_VERIFY_FAILED: - return PSA_ERROR_DATA_INVALID; - case MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL: - case MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL: - return PSA_ERROR_BUFFER_TOO_SMALL; - case MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE: - return PSA_ERROR_NOT_SUPPORTED; - case MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: - return PSA_ERROR_CORRUPTION_DETECTED; - default: - return PSA_ERROR_GENERIC_ERROR; - } -} -#endif - -#if defined(MBEDTLS_PSA_BUILTIN_PAKE) -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) -static psa_status_t psa_pake_ecjpake_setup(mbedtls_psa_pake_operation_t *operation) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - - mbedtls_ecjpake_init(&operation->ctx.jpake); - - ret = mbedtls_ecjpake_setup(&operation->ctx.jpake, - operation->role, - MBEDTLS_MD_SHA256, - MBEDTLS_ECP_DP_SECP256R1, - operation->password, - operation->password_len); - - mbedtls_platform_zeroize(operation->password, operation->password_len); - - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - - return PSA_SUCCESS; -} -#endif - -/* The only two JPAKE user/peer identifiers supported in built-in implementation. */ -static const uint8_t jpake_server_id[] = { 's', 'e', 'r', 'v', 'e', 'r' }; -static const uint8_t jpake_client_id[] = { 'c', 'l', 'i', 'e', 'n', 't' }; - -psa_status_t mbedtls_psa_pake_setup(mbedtls_psa_pake_operation_t *operation, - const psa_crypto_driver_pake_inputs_t *inputs) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t user_len = 0, peer_len = 0, password_len = 0; - uint8_t *peer = NULL, *user = NULL; - size_t actual_user_len = 0, actual_peer_len = 0, actual_password_len = 0; - psa_pake_cipher_suite_t cipher_suite = psa_pake_cipher_suite_init(); - - status = psa_crypto_driver_pake_get_password_len(inputs, &password_len); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_crypto_driver_pake_get_user_len(inputs, &user_len); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_crypto_driver_pake_get_peer_len(inputs, &peer_len); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_crypto_driver_pake_get_cipher_suite(inputs, &cipher_suite); - if (status != PSA_SUCCESS) { - return status; - } - - operation->password = mbedtls_calloc(1, password_len); - if (operation->password == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto error; - } - - user = mbedtls_calloc(1, user_len); - if (user == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto error; - } - - peer = mbedtls_calloc(1, peer_len); - if (peer == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto error; - } - - status = psa_crypto_driver_pake_get_password(inputs, operation->password, - password_len, &actual_password_len); - if (status != PSA_SUCCESS) { - goto error; - } - - status = psa_crypto_driver_pake_get_user(inputs, user, - user_len, &actual_user_len); - if (status != PSA_SUCCESS) { - goto error; - } - - status = psa_crypto_driver_pake_get_peer(inputs, peer, - peer_len, &actual_peer_len); - if (status != PSA_SUCCESS) { - goto error; - } - - operation->password_len = actual_password_len; - operation->alg = cipher_suite.algorithm; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - if (cipher_suite.algorithm == PSA_ALG_JPAKE) { - if (cipher_suite.type != PSA_PAKE_PRIMITIVE_TYPE_ECC || - cipher_suite.family != PSA_ECC_FAMILY_SECP_R1 || - cipher_suite.bits != 256 || - cipher_suite.hash != PSA_ALG_SHA_256) { - status = PSA_ERROR_NOT_SUPPORTED; - goto error; - } - - const size_t user_peer_len = sizeof(jpake_client_id); // client and server have the same length - if (actual_user_len != user_peer_len || - actual_peer_len != user_peer_len) { - status = PSA_ERROR_NOT_SUPPORTED; - goto error; - } - - if (memcmp(user, jpake_client_id, actual_user_len) == 0 && - memcmp(peer, jpake_server_id, actual_peer_len) == 0) { - operation->role = MBEDTLS_ECJPAKE_CLIENT; - } else - if (memcmp(user, jpake_server_id, actual_user_len) == 0 && - memcmp(peer, jpake_client_id, actual_peer_len) == 0) { - operation->role = MBEDTLS_ECJPAKE_SERVER; - } else { - status = PSA_ERROR_NOT_SUPPORTED; - goto error; - } - - operation->buffer_length = 0; - operation->buffer_offset = 0; - - status = psa_pake_ecjpake_setup(operation); - if (status != PSA_SUCCESS) { - goto error; - } - - /* Role has been set, release user/peer buffers. */ - mbedtls_free(user); mbedtls_free(peer); - - return PSA_SUCCESS; - } else -#else - (void) operation; - (void) inputs; -#endif - { status = PSA_ERROR_NOT_SUPPORTED; } - -error: - mbedtls_free(user); mbedtls_free(peer); - /* In case of failure of the setup of a multipart operation, the PSA driver interface - * specifies that the core does not call any other driver entry point thus does not - * call mbedtls_psa_pake_abort(). Therefore call it here to do the needed clean - * up like freeing the memory that may have been allocated to store the password. - */ - mbedtls_psa_pake_abort(operation); - return status; -} - -static psa_status_t mbedtls_psa_pake_output_internal( - mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - size_t length; - (void) step; // Unused parameter - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - /* - * The PSA CRYPTO PAKE and MbedTLS JPAKE API have a different - * handling of output sequencing. - * - * The MbedTLS JPAKE API outputs the whole X1+X2 and X2S steps data - * at once, on the other side the PSA CRYPTO PAKE api requires - * the KEY_SHARE/ZP_PUBLIC/ZK_PROOF parts of X1, X2 & X2S to be - * retrieved in sequence. - * - * In order to achieve API compatibility, the whole X1+X2 or X2S steps - * data is stored in an intermediate buffer at first step output call, - * and data is sliced down by parsing the ECPoint records in order - * to return the right parts on each step. - */ - if (operation->alg == PSA_ALG_JPAKE) { - /* Initialize & write round on KEY_SHARE sequences */ - if (step == PSA_JPAKE_X1_STEP_KEY_SHARE) { - ret = mbedtls_ecjpake_write_round_one(&operation->ctx.jpake, - operation->buffer, - sizeof(operation->buffer), - &operation->buffer_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - - operation->buffer_offset = 0; - } else if (step == PSA_JPAKE_X2S_STEP_KEY_SHARE) { - ret = mbedtls_ecjpake_write_round_two(&operation->ctx.jpake, - operation->buffer, - sizeof(operation->buffer), - &operation->buffer_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - - operation->buffer_offset = 0; - } - - /* - * mbedtls_ecjpake_write_round_xxx() outputs thing in the format - * defined by draft-cragie-tls-ecjpake-01 section 7. The summary is - * that the data for each step is prepended with a length byte, and - * then they're concatenated. Additionally, the server's second round - * output is prepended with a 3-bytes ECParameters structure. - * - * In PSA, we output each step separately, and don't prepend the - * output with a length byte, even less a curve identifier, as that - * information is already available. - */ - if (step == PSA_JPAKE_X2S_STEP_KEY_SHARE && - operation->role == MBEDTLS_ECJPAKE_SERVER) { - /* Skip ECParameters, with is 3 bytes (RFC 8422) */ - operation->buffer_offset += 3; - } - - /* Read the length byte then move past it to the data */ - length = operation->buffer[operation->buffer_offset]; - operation->buffer_offset += 1; - - if (operation->buffer_offset + length > operation->buffer_length) { - return PSA_ERROR_DATA_CORRUPT; - } - - if (output_size < length) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(output, - operation->buffer + operation->buffer_offset, - length); - *output_length = length; - - operation->buffer_offset += length; - - /* Reset buffer after ZK_PROOF sequence */ - if ((step == PSA_JPAKE_X2_STEP_ZK_PROOF) || - (step == PSA_JPAKE_X2S_STEP_ZK_PROOF)) { - mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); - operation->buffer_length = 0; - operation->buffer_offset = 0; - } - - return PSA_SUCCESS; - } else -#else - (void) step; - (void) output; - (void) output_size; - (void) output_length; -#endif - { return PSA_ERROR_NOT_SUPPORTED; } -} - -psa_status_t mbedtls_psa_pake_output(mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = mbedtls_psa_pake_output_internal( - operation, step, output, output_size, output_length); - - return status; -} - -static psa_status_t mbedtls_psa_pake_input_internal( - mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - const uint8_t *input, - size_t input_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - (void) step; // Unused parameter - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - /* - * The PSA CRYPTO PAKE and MbedTLS JPAKE API have a different - * handling of input sequencing. - * - * The MbedTLS JPAKE API takes the whole X1+X2 or X4S steps data - * at once as input, on the other side the PSA CRYPTO PAKE api requires - * the KEY_SHARE/ZP_PUBLIC/ZK_PROOF parts of X1, X2 & X4S to be - * given in sequence. - * - * In order to achieve API compatibility, each X1+X2 or X4S step data - * is stored sequentially in an intermediate buffer and given to the - * MbedTLS JPAKE API on the last step. - * - * This causes any input error to be only detected on the last step. - */ - if (operation->alg == PSA_ALG_JPAKE) { - /* - * Copy input to local buffer and format it as the Mbed TLS API - * expects, i.e. as defined by draft-cragie-tls-ecjpake-01 section 7. - * The summary is that the data for each step is prepended with a - * length byte, and then they're concatenated. Additionally, the - * server's second round output is prepended with a 3-bytes - * ECParameters structure - which means we have to prepend that when - * we're a client. - */ - if (step == PSA_JPAKE_X4S_STEP_KEY_SHARE && - operation->role == MBEDTLS_ECJPAKE_CLIENT) { - /* We only support secp256r1. */ - /* This is the ECParameters structure defined by RFC 8422. */ - unsigned char ecparameters[3] = { - 3, /* named_curve */ - 0, 23 /* secp256r1 */ - }; - - if (operation->buffer_length + sizeof(ecparameters) > - sizeof(operation->buffer)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - memcpy(operation->buffer + operation->buffer_length, - ecparameters, sizeof(ecparameters)); - operation->buffer_length += sizeof(ecparameters); - } - - /* - * The core checks that input_length is smaller than - * PSA_PAKE_INPUT_MAX_SIZE. - * Thus no risk of integer overflow here. - */ - if (operation->buffer_length + input_length + 1 > sizeof(operation->buffer)) { - return PSA_ERROR_BUFFER_TOO_SMALL; - } - - /* Write the length byte */ - operation->buffer[operation->buffer_length] = (uint8_t) input_length; - operation->buffer_length += 1; - - /* Finally copy the data */ - memcpy(operation->buffer + operation->buffer_length, - input, input_length); - operation->buffer_length += input_length; - - /* Load buffer at each last round ZK_PROOF */ - if (step == PSA_JPAKE_X2_STEP_ZK_PROOF) { - ret = mbedtls_ecjpake_read_round_one(&operation->ctx.jpake, - operation->buffer, - operation->buffer_length); - - mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); - operation->buffer_length = 0; - - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - } else if (step == PSA_JPAKE_X4S_STEP_ZK_PROOF) { - ret = mbedtls_ecjpake_read_round_two(&operation->ctx.jpake, - operation->buffer, - operation->buffer_length); - - mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); - operation->buffer_length = 0; - - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - } - - return PSA_SUCCESS; - } else -#else - (void) step; - (void) input; - (void) input_length; -#endif - { return PSA_ERROR_NOT_SUPPORTED; } -} - -psa_status_t mbedtls_psa_pake_input(mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - const uint8_t *input, - size_t input_length) -{ - psa_status_t status = mbedtls_psa_pake_input_internal( - operation, step, input, input_length); - - return status; -} - -psa_status_t mbedtls_psa_pake_get_implicit_key( - mbedtls_psa_pake_operation_t *operation, - uint8_t *output, size_t output_size, - size_t *output_length) -{ - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - if (operation->alg == PSA_ALG_JPAKE) { - ret = mbedtls_ecjpake_write_shared_key(&operation->ctx.jpake, - output, - output_size, - output_length, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE); - if (ret != 0) { - return mbedtls_ecjpake_to_psa_error(ret); - } - - return PSA_SUCCESS; - } else -#else - (void) output; -#endif - { return PSA_ERROR_NOT_SUPPORTED; } -} - -psa_status_t mbedtls_psa_pake_abort(mbedtls_psa_pake_operation_t *operation) -{ - mbedtls_zeroize_and_free(operation->password, operation->password_len); - operation->password = NULL; - operation->password_len = 0; - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) - if (operation->alg == PSA_ALG_JPAKE) { - operation->role = MBEDTLS_ECJPAKE_NONE; - mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); - operation->buffer_length = 0; - operation->buffer_offset = 0; - mbedtls_ecjpake_free(&operation->ctx.jpake); - } -#endif - - operation->alg = PSA_ALG_NONE; - - return PSA_SUCCESS; -} - -#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA PAKE layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa_crypto_core.h" +#include "psa_crypto_pake.h" +#include "psa_crypto_slot_management.h" + +#include +#include "psa_util_internal.h" + +#include +#include +#include + +/* + * State sequence: + * + * psa_pake_setup() + * | + * |-- In any order: + * | | psa_pake_set_password_key() + * | | psa_pake_set_user() + * | | psa_pake_set_peer() + * | | psa_pake_set_role() + * | + * |--- In any order: (First round input before or after first round output) + * | | + * | |------ In Order + * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) + * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) + * | | + * | |------ In Order: + * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) + * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) + * | + * |--- In any order: (Second round input before or after second round output) + * | | + * | |------ In Order + * | | | psa_pake_output(PSA_PAKE_STEP_KEY_SHARE) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PUBLIC) + * | | | psa_pake_output(PSA_PAKE_STEP_ZK_PROOF) + * | | + * | |------ In Order: + * | | psa_pake_input(PSA_PAKE_STEP_KEY_SHARE) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PUBLIC) + * | | psa_pake_input(PSA_PAKE_STEP_ZK_PROOF) + * | + * psa_pake_get_implicit_key() + * psa_pake_abort() + */ + +/* + * Possible sequence of calls to implementation: + * + * |--- In any order: + * | | + * | |------ In Order + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_KEY_SHARE) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_ZK_PUBLIC) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X1_STEP_ZK_PROOF) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_KEY_SHARE) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_ZK_PUBLIC) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2_STEP_ZK_PROOF) + * | | + * | |------ In Order: + * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_KEY_SHARE) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_ZK_PUBLIC) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X1_STEP_ZK_PROOF) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_KEY_SHARE) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_ZK_PUBLIC) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X2_STEP_ZK_PROOF) + * | + * |--- In any order: + * | | + * | |------ In Order + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_KEY_SHARE) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_ZK_PUBLIC) + * | | | mbedtls_psa_pake_output(PSA_JPAKE_X2S_STEP_ZK_PROOF) + * | | + * | |------ In Order: + * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_KEY_SHARE) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_ZK_PUBLIC) + * | | mbedtls_psa_pake_input(PSA_JPAKE_X4S_STEP_ZK_PROOF) + */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) +static psa_status_t mbedtls_ecjpake_to_psa_error(int ret) +{ + switch (ret) { + case MBEDTLS_ERR_MPI_BAD_INPUT_DATA: + case MBEDTLS_ERR_ECP_BAD_INPUT_DATA: + case MBEDTLS_ERR_ECP_INVALID_KEY: + case MBEDTLS_ERR_ECP_VERIFY_FAILED: + return PSA_ERROR_DATA_INVALID; + case MBEDTLS_ERR_MPI_BUFFER_TOO_SMALL: + case MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL: + return PSA_ERROR_BUFFER_TOO_SMALL; + case MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE: + return PSA_ERROR_NOT_SUPPORTED; + case MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: + return PSA_ERROR_CORRUPTION_DETECTED; + default: + return PSA_ERROR_GENERIC_ERROR; + } +} +#endif + +#if defined(MBEDTLS_PSA_BUILTIN_PAKE) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) +static psa_status_t psa_pake_ecjpake_setup(mbedtls_psa_pake_operation_t *operation) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + mbedtls_ecjpake_init(&operation->ctx.jpake); + + ret = mbedtls_ecjpake_setup(&operation->ctx.jpake, + operation->role, + MBEDTLS_MD_SHA256, + MBEDTLS_ECP_DP_SECP256R1, + operation->password, + operation->password_len); + + mbedtls_platform_zeroize(operation->password, operation->password_len); + + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + + return PSA_SUCCESS; +} +#endif + +/* The only two JPAKE user/peer identifiers supported in built-in implementation. */ +static const uint8_t jpake_server_id[] = { 's', 'e', 'r', 'v', 'e', 'r' }; +static const uint8_t jpake_client_id[] = { 'c', 'l', 'i', 'e', 'n', 't' }; + +psa_status_t mbedtls_psa_pake_setup(mbedtls_psa_pake_operation_t *operation, + const psa_crypto_driver_pake_inputs_t *inputs) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t user_len = 0, peer_len = 0, password_len = 0; + uint8_t *peer = NULL, *user = NULL; + size_t actual_user_len = 0, actual_peer_len = 0, actual_password_len = 0; + psa_pake_cipher_suite_t cipher_suite = psa_pake_cipher_suite_init(); + + status = psa_crypto_driver_pake_get_password_len(inputs, &password_len); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_crypto_driver_pake_get_user_len(inputs, &user_len); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_crypto_driver_pake_get_peer_len(inputs, &peer_len); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_crypto_driver_pake_get_cipher_suite(inputs, &cipher_suite); + if (status != PSA_SUCCESS) { + return status; + } + + operation->password = mbedtls_calloc(1, password_len); + if (operation->password == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto error; + } + + user = mbedtls_calloc(1, user_len); + if (user == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto error; + } + + peer = mbedtls_calloc(1, peer_len); + if (peer == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto error; + } + + status = psa_crypto_driver_pake_get_password(inputs, operation->password, + password_len, &actual_password_len); + if (status != PSA_SUCCESS) { + goto error; + } + + status = psa_crypto_driver_pake_get_user(inputs, user, + user_len, &actual_user_len); + if (status != PSA_SUCCESS) { + goto error; + } + + status = psa_crypto_driver_pake_get_peer(inputs, peer, + peer_len, &actual_peer_len); + if (status != PSA_SUCCESS) { + goto error; + } + + operation->password_len = actual_password_len; + operation->alg = cipher_suite.algorithm; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + if (cipher_suite.algorithm == PSA_ALG_JPAKE) { + if (cipher_suite.type != PSA_PAKE_PRIMITIVE_TYPE_ECC || + cipher_suite.family != PSA_ECC_FAMILY_SECP_R1 || + cipher_suite.bits != 256 || + cipher_suite.hash != PSA_ALG_SHA_256) { + status = PSA_ERROR_NOT_SUPPORTED; + goto error; + } + + const size_t user_peer_len = sizeof(jpake_client_id); // client and server have the same length + if (actual_user_len != user_peer_len || + actual_peer_len != user_peer_len) { + status = PSA_ERROR_NOT_SUPPORTED; + goto error; + } + + if (memcmp(user, jpake_client_id, actual_user_len) == 0 && + memcmp(peer, jpake_server_id, actual_peer_len) == 0) { + operation->role = MBEDTLS_ECJPAKE_CLIENT; + } else + if (memcmp(user, jpake_server_id, actual_user_len) == 0 && + memcmp(peer, jpake_client_id, actual_peer_len) == 0) { + operation->role = MBEDTLS_ECJPAKE_SERVER; + } else { + status = PSA_ERROR_NOT_SUPPORTED; + goto error; + } + + operation->buffer_length = 0; + operation->buffer_offset = 0; + + status = psa_pake_ecjpake_setup(operation); + if (status != PSA_SUCCESS) { + goto error; + } + + /* Role has been set, release user/peer buffers. */ + mbedtls_free(user); mbedtls_free(peer); + + return PSA_SUCCESS; + } else +#else + (void) operation; + (void) inputs; +#endif + { status = PSA_ERROR_NOT_SUPPORTED; } + +error: + mbedtls_free(user); mbedtls_free(peer); + /* In case of failure of the setup of a multipart operation, the PSA driver interface + * specifies that the core does not call any other driver entry point thus does not + * call mbedtls_psa_pake_abort(). Therefore call it here to do the needed clean + * up like freeing the memory that may have been allocated to store the password. + */ + mbedtls_psa_pake_abort(operation); + return status; +} + +static psa_status_t mbedtls_psa_pake_output_internal( + mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t length; + (void) step; // Unused parameter + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + /* + * The PSA CRYPTO PAKE and MbedTLS JPAKE API have a different + * handling of output sequencing. + * + * The MbedTLS JPAKE API outputs the whole X1+X2 and X2S steps data + * at once, on the other side the PSA CRYPTO PAKE api requires + * the KEY_SHARE/ZP_PUBLIC/ZK_PROOF parts of X1, X2 & X2S to be + * retrieved in sequence. + * + * In order to achieve API compatibility, the whole X1+X2 or X2S steps + * data is stored in an intermediate buffer at first step output call, + * and data is sliced down by parsing the ECPoint records in order + * to return the right parts on each step. + */ + if (operation->alg == PSA_ALG_JPAKE) { + /* Initialize & write round on KEY_SHARE sequences */ + if (step == PSA_JPAKE_X1_STEP_KEY_SHARE) { + ret = mbedtls_ecjpake_write_round_one(&operation->ctx.jpake, + operation->buffer, + sizeof(operation->buffer), + &operation->buffer_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + + operation->buffer_offset = 0; + } else if (step == PSA_JPAKE_X2S_STEP_KEY_SHARE) { + ret = mbedtls_ecjpake_write_round_two(&operation->ctx.jpake, + operation->buffer, + sizeof(operation->buffer), + &operation->buffer_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + + operation->buffer_offset = 0; + } + + /* + * mbedtls_ecjpake_write_round_xxx() outputs thing in the format + * defined by draft-cragie-tls-ecjpake-01 section 7. The summary is + * that the data for each step is prepended with a length byte, and + * then they're concatenated. Additionally, the server's second round + * output is prepended with a 3-bytes ECParameters structure. + * + * In PSA, we output each step separately, and don't prepend the + * output with a length byte, even less a curve identifier, as that + * information is already available. + */ + if (step == PSA_JPAKE_X2S_STEP_KEY_SHARE && + operation->role == MBEDTLS_ECJPAKE_SERVER) { + /* Skip ECParameters, with is 3 bytes (RFC 8422) */ + operation->buffer_offset += 3; + } + + /* Read the length byte then move past it to the data */ + length = operation->buffer[operation->buffer_offset]; + operation->buffer_offset += 1; + + if (operation->buffer_offset + length > operation->buffer_length) { + return PSA_ERROR_DATA_CORRUPT; + } + + if (output_size < length) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(output, + operation->buffer + operation->buffer_offset, + length); + *output_length = length; + + operation->buffer_offset += length; + + /* Reset buffer after ZK_PROOF sequence */ + if ((step == PSA_JPAKE_X2_STEP_ZK_PROOF) || + (step == PSA_JPAKE_X2S_STEP_ZK_PROOF)) { + mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); + operation->buffer_length = 0; + operation->buffer_offset = 0; + } + + return PSA_SUCCESS; + } else +#else + (void) step; + (void) output; + (void) output_size; + (void) output_length; +#endif + { return PSA_ERROR_NOT_SUPPORTED; } +} + +psa_status_t mbedtls_psa_pake_output(mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = mbedtls_psa_pake_output_internal( + operation, step, output, output_size, output_length); + + return status; +} + +static psa_status_t mbedtls_psa_pake_input_internal( + mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + const uint8_t *input, + size_t input_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + (void) step; // Unused parameter + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + /* + * The PSA CRYPTO PAKE and MbedTLS JPAKE API have a different + * handling of input sequencing. + * + * The MbedTLS JPAKE API takes the whole X1+X2 or X4S steps data + * at once as input, on the other side the PSA CRYPTO PAKE api requires + * the KEY_SHARE/ZP_PUBLIC/ZK_PROOF parts of X1, X2 & X4S to be + * given in sequence. + * + * In order to achieve API compatibility, each X1+X2 or X4S step data + * is stored sequentially in an intermediate buffer and given to the + * MbedTLS JPAKE API on the last step. + * + * This causes any input error to be only detected on the last step. + */ + if (operation->alg == PSA_ALG_JPAKE) { + /* + * Copy input to local buffer and format it as the Mbed TLS API + * expects, i.e. as defined by draft-cragie-tls-ecjpake-01 section 7. + * The summary is that the data for each step is prepended with a + * length byte, and then they're concatenated. Additionally, the + * server's second round output is prepended with a 3-bytes + * ECParameters structure - which means we have to prepend that when + * we're a client. + */ + if (step == PSA_JPAKE_X4S_STEP_KEY_SHARE && + operation->role == MBEDTLS_ECJPAKE_CLIENT) { + /* We only support secp256r1. */ + /* This is the ECParameters structure defined by RFC 8422. */ + unsigned char ecparameters[3] = { + 3, /* named_curve */ + 0, 23 /* secp256r1 */ + }; + + if (operation->buffer_length + sizeof(ecparameters) > + sizeof(operation->buffer)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + memcpy(operation->buffer + operation->buffer_length, + ecparameters, sizeof(ecparameters)); + operation->buffer_length += sizeof(ecparameters); + } + + /* + * The core checks that input_length is smaller than + * PSA_PAKE_INPUT_MAX_SIZE. + * Thus no risk of integer overflow here. + */ + if (operation->buffer_length + input_length + 1 > sizeof(operation->buffer)) { + return PSA_ERROR_BUFFER_TOO_SMALL; + } + + /* Write the length byte */ + operation->buffer[operation->buffer_length] = (uint8_t) input_length; + operation->buffer_length += 1; + + /* Finally copy the data */ + memcpy(operation->buffer + operation->buffer_length, + input, input_length); + operation->buffer_length += input_length; + + /* Load buffer at each last round ZK_PROOF */ + if (step == PSA_JPAKE_X2_STEP_ZK_PROOF) { + ret = mbedtls_ecjpake_read_round_one(&operation->ctx.jpake, + operation->buffer, + operation->buffer_length); + + mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); + operation->buffer_length = 0; + + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + } else if (step == PSA_JPAKE_X4S_STEP_ZK_PROOF) { + ret = mbedtls_ecjpake_read_round_two(&operation->ctx.jpake, + operation->buffer, + operation->buffer_length); + + mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); + operation->buffer_length = 0; + + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + } + + return PSA_SUCCESS; + } else +#else + (void) step; + (void) input; + (void) input_length; +#endif + { return PSA_ERROR_NOT_SUPPORTED; } +} + +psa_status_t mbedtls_psa_pake_input(mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + const uint8_t *input, + size_t input_length) +{ + psa_status_t status = mbedtls_psa_pake_input_internal( + operation, step, input, input_length); + + return status; +} + +psa_status_t mbedtls_psa_pake_get_implicit_key( + mbedtls_psa_pake_operation_t *operation, + uint8_t *output, size_t output_size, + size_t *output_length) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + if (operation->alg == PSA_ALG_JPAKE) { + ret = mbedtls_ecjpake_write_shared_key(&operation->ctx.jpake, + output, + output_size, + output_length, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE); + if (ret != 0) { + return mbedtls_ecjpake_to_psa_error(ret); + } + + return PSA_SUCCESS; + } else +#else + (void) output; +#endif + { return PSA_ERROR_NOT_SUPPORTED; } +} + +psa_status_t mbedtls_psa_pake_abort(mbedtls_psa_pake_operation_t *operation) +{ + mbedtls_zeroize_and_free(operation->password, operation->password_len); + operation->password = NULL; + operation->password_len = 0; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_JPAKE) + if (operation->alg == PSA_ALG_JPAKE) { + operation->role = MBEDTLS_ECJPAKE_NONE; + mbedtls_platform_zeroize(operation->buffer, sizeof(operation->buffer)); + operation->buffer_length = 0; + operation->buffer_offset = 0; + mbedtls_ecjpake_free(&operation->ctx.jpake); + } +#endif + + operation->alg = PSA_ALG_NONE; + + return PSA_SUCCESS; +} + +#endif /* MBEDTLS_PSA_BUILTIN_PAKE */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.h index f21b0e6..9cb9b87 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_pake.h @@ -1,171 +1,171 @@ -/* - * PSA PAKE layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_PAKE_H -#define PSA_CRYPTO_PAKE_H - -#include - -/** Set the session information for a password-authenticated key exchange. - * - * \note The signature of this function is that of a PSA driver - * pake_setup entry point. This function behaves as a pake_setup - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in,out] operation The operation object to set up. It must have - * been initialized but not set up yet. - * \param[in] inputs Inputs required for PAKE operation (role, password, - * key lifetime, cipher suite) - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * The algorithm in \p cipher_suite is not a supported PAKE algorithm, - * or the PAKE primitive in \p cipher_suite is not supported or not - * compatible with the PAKE algorithm, or the hash algorithm in - * \p cipher_suite is not supported or not compatible with the PAKE - * algorithm and primitive. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_pake_setup(mbedtls_psa_pake_operation_t *operation, - const psa_crypto_driver_pake_inputs_t *inputs); - - -/** Get output for a step of a password-authenticated key exchange. - * - * \note The signature of this function is that of a PSA driver - * pake_output entry point. This function behaves as a pake_output - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in,out] operation Active PAKE operation. - * \param step The step of the algorithm for which the output is - * requested. - * \param[out] output Buffer where the output is to be written in the - * format appropriate for this driver \p step. Refer to - * the documentation of psa_crypto_driver_pake_step_t for - * more information. - * \param output_size Size of the \p output buffer in bytes. This must - * be at least #PSA_PAKE_OUTPUT_SIZE(\p alg, \p - * primitive, \p step) where \p alg and - * \p primitive are the PAKE algorithm and primitive - * in the operation's cipher suite, and \p step is - * the output step. - * - * \param[out] output_length On success, the number of bytes of the returned - * output. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -psa_status_t mbedtls_psa_pake_output(mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** Provide input for a step of a password-authenticated key exchange. - * - * \note The signature of this function is that of a PSA driver - * pake_input entry point. This function behaves as a pake_input - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \note The core checks that input_length is smaller than PSA_PAKE_INPUT_MAX_SIZE. - * - * \param[in,out] operation Active PAKE operation. - * \param step The driver step for which the input is provided. - * \param[in] input Buffer containing the input in the format - * appropriate for this \p step. Refer to the - * documentation of psa_crypto_driver_pake_step_t - * for more information. - * \param input_length Size of the \p input buffer in bytes. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The verification fails for a zero-knowledge input step. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * the \p input is not valid for the \p operation's algorithm, cipher suite - * or \p step. - * \retval #PSA_ERROR_NOT_SUPPORTED - * the \p input is not supported for the \p operation's algorithm, cipher - * suite or \p step. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -psa_status_t mbedtls_psa_pake_input(mbedtls_psa_pake_operation_t *operation, - psa_crypto_driver_pake_step_t step, - const uint8_t *input, - size_t input_length); - -/** Get implicitly confirmed shared secret from a PAKE. - * - * \note The signature of this function is that of a PSA driver - * pake_get_implicit_key entry point. This function behaves as a - * pake_get_implicit_key entry point as defined in the PSA driver - * interface specification for transparent drivers. - * - * \param[in,out] operation Active PAKE operation. - * \param[out] output Output buffer for implicit key. - * \param output_size Size of the output buffer in bytes. - * \param[out] output_length On success, the number of bytes of the implicit key. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Input from a PAKE is not supported by the algorithm in the \p output - * key derivation operation. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -psa_status_t mbedtls_psa_pake_get_implicit_key( - mbedtls_psa_pake_operation_t *operation, - uint8_t *output, size_t output_size, - size_t *output_length); - -/** Abort a PAKE operation. - * - * \note The signature of this function is that of a PSA driver - * pake_abort entry point. This function behaves as a pake_abort - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in,out] operation The operation to abort. - * - * \retval #PSA_SUCCESS - * Success. - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_pake_abort(mbedtls_psa_pake_operation_t *operation); - -#endif /* PSA_CRYPTO_PAKE_H */ +/* + * PSA PAKE layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_PAKE_H +#define PSA_CRYPTO_PAKE_H + +#include + +/** Set the session information for a password-authenticated key exchange. + * + * \note The signature of this function is that of a PSA driver + * pake_setup entry point. This function behaves as a pake_setup + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in,out] operation The operation object to set up. It must have + * been initialized but not set up yet. + * \param[in] inputs Inputs required for PAKE operation (role, password, + * key lifetime, cipher suite) + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * The algorithm in \p cipher_suite is not a supported PAKE algorithm, + * or the PAKE primitive in \p cipher_suite is not supported or not + * compatible with the PAKE algorithm, or the hash algorithm in + * \p cipher_suite is not supported or not compatible with the PAKE + * algorithm and primitive. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_pake_setup(mbedtls_psa_pake_operation_t *operation, + const psa_crypto_driver_pake_inputs_t *inputs); + + +/** Get output for a step of a password-authenticated key exchange. + * + * \note The signature of this function is that of a PSA driver + * pake_output entry point. This function behaves as a pake_output + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in,out] operation Active PAKE operation. + * \param step The step of the algorithm for which the output is + * requested. + * \param[out] output Buffer where the output is to be written in the + * format appropriate for this driver \p step. Refer to + * the documentation of psa_crypto_driver_pake_step_t for + * more information. + * \param output_size Size of the \p output buffer in bytes. This must + * be at least #PSA_PAKE_OUTPUT_SIZE(\p alg, \p + * primitive, \p step) where \p alg and + * \p primitive are the PAKE algorithm and primitive + * in the operation's cipher suite, and \p step is + * the output step. + * + * \param[out] output_length On success, the number of bytes of the returned + * output. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +psa_status_t mbedtls_psa_pake_output(mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** Provide input for a step of a password-authenticated key exchange. + * + * \note The signature of this function is that of a PSA driver + * pake_input entry point. This function behaves as a pake_input + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \note The core checks that input_length is smaller than PSA_PAKE_INPUT_MAX_SIZE. + * + * \param[in,out] operation Active PAKE operation. + * \param step The driver step for which the input is provided. + * \param[in] input Buffer containing the input in the format + * appropriate for this \p step. Refer to the + * documentation of psa_crypto_driver_pake_step_t + * for more information. + * \param input_length Size of the \p input buffer in bytes. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The verification fails for a zero-knowledge input step. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * the \p input is not valid for the \p operation's algorithm, cipher suite + * or \p step. + * \retval #PSA_ERROR_NOT_SUPPORTED + * the \p input is not supported for the \p operation's algorithm, cipher + * suite or \p step. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +psa_status_t mbedtls_psa_pake_input(mbedtls_psa_pake_operation_t *operation, + psa_crypto_driver_pake_step_t step, + const uint8_t *input, + size_t input_length); + +/** Get implicitly confirmed shared secret from a PAKE. + * + * \note The signature of this function is that of a PSA driver + * pake_get_implicit_key entry point. This function behaves as a + * pake_get_implicit_key entry point as defined in the PSA driver + * interface specification for transparent drivers. + * + * \param[in,out] operation Active PAKE operation. + * \param[out] output Output buffer for implicit key. + * \param output_size Size of the output buffer in bytes. + * \param[out] output_length On success, the number of bytes of the implicit key. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Input from a PAKE is not supported by the algorithm in the \p output + * key derivation operation. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +psa_status_t mbedtls_psa_pake_get_implicit_key( + mbedtls_psa_pake_operation_t *operation, + uint8_t *output, size_t output_size, + size_t *output_length); + +/** Abort a PAKE operation. + * + * \note The signature of this function is that of a PSA driver + * pake_abort entry point. This function behaves as a pake_abort + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in,out] operation The operation to abort. + * + * \retval #PSA_SUCCESS + * Success. + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_pake_abort(mbedtls_psa_pake_operation_t *operation); + +#endif /* PSA_CRYPTO_PAKE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_random_impl.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_random_impl.h index 8719d9c..c7a8b49 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_random_impl.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_random_impl.h @@ -1,204 +1,204 @@ -/** \file psa_crypto_random_impl.h - * - * \brief PSA crypto random generator implementation abstraction. - * - * The definitions here need to be consistent with the declarations - * in include/psa_util_internal.h. This file contains some redundant - * declarations to increase the chance that a compiler will detect - * inconsistencies if one file is changed without updating the other, - * but not all potential inconsistencies can be enforced, so make sure - * to check the public declarations and contracts in - * include/psa_util_internal.h if you modify this file. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_RANDOM_IMPL_H -#define PSA_CRYPTO_RANDOM_IMPL_H - -#include "psa_util_internal.h" - -#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) - -#include -#include // only for error codes -#include - -typedef mbedtls_psa_external_random_context_t mbedtls_psa_random_context_t; - -/* Trivial wrapper around psa_generate_random(). */ -int mbedtls_psa_get_random(void *p_rng, - unsigned char *output, - size_t output_size); - -/* The PSA RNG API doesn't need any externally maintained state. */ -#define MBEDTLS_PSA_RANDOM_STATE NULL - -#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -/* Choose a DRBG based on configuration and availability */ -#if defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE) - -#include "mbedtls/hmac_drbg.h" - -#elif defined(MBEDTLS_CTR_DRBG_C) - -#include "mbedtls/ctr_drbg.h" - -#elif defined(MBEDTLS_HMAC_DRBG_C) - -#include "mbedtls/hmac_drbg.h" -#if defined(MBEDTLS_MD_CAN_SHA512) && defined(MBEDTLS_MD_CAN_SHA256) -#include -#if SIZE_MAX > 0xffffffff -/* Looks like a 64-bit system, so prefer SHA-512. */ -#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA512 -#else -/* Looks like a 32-bit system, so prefer SHA-256. */ -#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 -#endif -#elif defined(MBEDTLS_MD_CAN_SHA512) -#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA512 -#elif defined(MBEDTLS_MD_CAN_SHA256) -#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 -#else -#error "No hash algorithm available for HMAC_DBRG." -#endif - -#else -#error "No DRBG module available for the psa_crypto module." -#endif - -#include "mbedtls/entropy.h" - -/** Initialize the PSA DRBG. - * - * \param p_rng Pointer to the Mbed TLS DRBG state. - */ -static inline void mbedtls_psa_drbg_init(mbedtls_psa_drbg_context_t *p_rng) -{ -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_init(p_rng); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_init(p_rng); -#endif -} - -/** Deinitialize the PSA DRBG. - * - * \param p_rng Pointer to the Mbed TLS DRBG state. - */ -static inline void mbedtls_psa_drbg_free(mbedtls_psa_drbg_context_t *p_rng) -{ -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_free(p_rng); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_free(p_rng); -#endif -} - -/** The type of the PSA random generator context. - * - * The random generator context is composed of an entropy context and - * a DRBG context. - */ -typedef struct { - void (* entropy_init)(mbedtls_entropy_context *ctx); - void (* entropy_free)(mbedtls_entropy_context *ctx); - mbedtls_entropy_context entropy; - mbedtls_psa_drbg_context_t drbg; -} mbedtls_psa_random_context_t; - -/* Defined in include/psa_util_internal.h so that it's visible to - * application code. The declaration here is redundant, but included - * as a safety net to make it more likely that a future change that - * accidentally causes the implementation to diverge from the interface - * will be noticed. */ -/* Do not include the declaration under MSVC because it doesn't accept it - * ("error C2370: 'mbedtls_psa_get_random' : redefinition; different storage class"). - * Observed with Visual Studio 2013. A known bug apparently: - * https://stackoverflow.com/questions/8146541/duplicate-external-static-declarations-not-allowed-in-visual-studio - */ -#if !defined(_MSC_VER) -static mbedtls_f_rng_t *const mbedtls_psa_get_random; -#endif - -/** The maximum number of bytes that mbedtls_psa_get_random() is expected to - * return. - */ -#if defined(MBEDTLS_CTR_DRBG_C) -#define MBEDTLS_PSA_RANDOM_MAX_REQUEST MBEDTLS_CTR_DRBG_MAX_REQUEST -#elif defined(MBEDTLS_HMAC_DRBG_C) -#define MBEDTLS_PSA_RANDOM_MAX_REQUEST MBEDTLS_HMAC_DRBG_MAX_REQUEST -#endif - -/** A pointer to the PSA DRBG state. - * - * This variable is only intended to be used through the macro - * #MBEDTLS_PSA_RANDOM_STATE. - */ -/* psa_crypto.c sets this variable to a pointer to the DRBG state in the - * global PSA crypto state. */ -/* The type `mbedtls_psa_drbg_context_t` is defined in - * include/psa_util_internal.h so that `mbedtls_psa_random_state` can be - * declared there and be visible to application code. */ -extern mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state; - -/** A pointer to the PSA DRBG state. - * - * This macro expands to an expression that is suitable as the \c p_rng - * parameter to pass to mbedtls_psa_get_random(). - * - * This macro exists in all configurations where the psa_crypto module is - * enabled. Its expansion depends on the configuration. - */ -#define MBEDTLS_PSA_RANDOM_STATE mbedtls_psa_random_state - -/** Seed the PSA DRBG. - * - * \param entropy An entropy context to read the seed from. - * \param custom The personalization string. - * This can be \c NULL, in which case the personalization - * string is empty regardless of the value of \p len. - * \param len The length of the personalization string. - * - * \return \c 0 on success. - * \return An Mbed TLS error code (\c MBEDTLS_ERR_xxx) on failure. - */ -static inline int mbedtls_psa_drbg_seed( - mbedtls_entropy_context *entropy, - const unsigned char *custom, size_t len) -{ -#if defined(MBEDTLS_CTR_DRBG_C) - return mbedtls_ctr_drbg_seed(MBEDTLS_PSA_RANDOM_STATE, - mbedtls_entropy_func, - entropy, - custom, len); -#elif defined(MBEDTLS_HMAC_DRBG_C) - const mbedtls_md_info_t *md_info = - mbedtls_md_info_from_type(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE); - return mbedtls_hmac_drbg_seed(MBEDTLS_PSA_RANDOM_STATE, - md_info, - mbedtls_entropy_func, - entropy, - custom, len); -#endif -} - -#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ - -#endif /* PSA_CRYPTO_RANDOM_IMPL_H */ +/** \file psa_crypto_random_impl.h + * + * \brief PSA crypto random generator implementation abstraction. + * + * The definitions here need to be consistent with the declarations + * in include/psa_util_internal.h. This file contains some redundant + * declarations to increase the chance that a compiler will detect + * inconsistencies if one file is changed without updating the other, + * but not all potential inconsistencies can be enforced, so make sure + * to check the public declarations and contracts in + * include/psa_util_internal.h if you modify this file. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_RANDOM_IMPL_H +#define PSA_CRYPTO_RANDOM_IMPL_H + +#include "psa_util_internal.h" + +#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG) + +#include +#include // only for error codes +#include + +typedef mbedtls_psa_external_random_context_t mbedtls_psa_random_context_t; + +/* Trivial wrapper around psa_generate_random(). */ +int mbedtls_psa_get_random(void *p_rng, + unsigned char *output, + size_t output_size); + +/* The PSA RNG API doesn't need any externally maintained state. */ +#define MBEDTLS_PSA_RANDOM_STATE NULL + +#else /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + +/* Choose a DRBG based on configuration and availability */ +#if defined(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE) + +#include "mbedtls/hmac_drbg.h" + +#elif defined(MBEDTLS_CTR_DRBG_C) + +#include "mbedtls/ctr_drbg.h" + +#elif defined(MBEDTLS_HMAC_DRBG_C) + +#include "mbedtls/hmac_drbg.h" +#if defined(MBEDTLS_MD_CAN_SHA512) && defined(MBEDTLS_MD_CAN_SHA256) +#include +#if SIZE_MAX > 0xffffffff +/* Looks like a 64-bit system, so prefer SHA-512. */ +#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA512 +#else +/* Looks like a 32-bit system, so prefer SHA-256. */ +#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 +#endif +#elif defined(MBEDTLS_MD_CAN_SHA512) +#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA512 +#elif defined(MBEDTLS_MD_CAN_SHA256) +#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 +#else +#error "No hash algorithm available for HMAC_DBRG." +#endif + +#else +#error "No DRBG module available for the psa_crypto module." +#endif + +#include "mbedtls/entropy.h" + +/** Initialize the PSA DRBG. + * + * \param p_rng Pointer to the Mbed TLS DRBG state. + */ +static inline void mbedtls_psa_drbg_init(mbedtls_psa_drbg_context_t *p_rng) +{ +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_init(p_rng); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_init(p_rng); +#endif +} + +/** Deinitialize the PSA DRBG. + * + * \param p_rng Pointer to the Mbed TLS DRBG state. + */ +static inline void mbedtls_psa_drbg_free(mbedtls_psa_drbg_context_t *p_rng) +{ +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_free(p_rng); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_free(p_rng); +#endif +} + +/** The type of the PSA random generator context. + * + * The random generator context is composed of an entropy context and + * a DRBG context. + */ +typedef struct { + void (* entropy_init)(mbedtls_entropy_context *ctx); + void (* entropy_free)(mbedtls_entropy_context *ctx); + mbedtls_entropy_context entropy; + mbedtls_psa_drbg_context_t drbg; +} mbedtls_psa_random_context_t; + +/* Defined in include/psa_util_internal.h so that it's visible to + * application code. The declaration here is redundant, but included + * as a safety net to make it more likely that a future change that + * accidentally causes the implementation to diverge from the interface + * will be noticed. */ +/* Do not include the declaration under MSVC because it doesn't accept it + * ("error C2370: 'mbedtls_psa_get_random' : redefinition; different storage class"). + * Observed with Visual Studio 2013. A known bug apparently: + * https://stackoverflow.com/questions/8146541/duplicate-external-static-declarations-not-allowed-in-visual-studio + */ +#if !defined(_MSC_VER) +static mbedtls_f_rng_t *const mbedtls_psa_get_random; +#endif + +/** The maximum number of bytes that mbedtls_psa_get_random() is expected to + * return. + */ +#if defined(MBEDTLS_CTR_DRBG_C) +#define MBEDTLS_PSA_RANDOM_MAX_REQUEST MBEDTLS_CTR_DRBG_MAX_REQUEST +#elif defined(MBEDTLS_HMAC_DRBG_C) +#define MBEDTLS_PSA_RANDOM_MAX_REQUEST MBEDTLS_HMAC_DRBG_MAX_REQUEST +#endif + +/** A pointer to the PSA DRBG state. + * + * This variable is only intended to be used through the macro + * #MBEDTLS_PSA_RANDOM_STATE. + */ +/* psa_crypto.c sets this variable to a pointer to the DRBG state in the + * global PSA crypto state. */ +/* The type `mbedtls_psa_drbg_context_t` is defined in + * include/psa_util_internal.h so that `mbedtls_psa_random_state` can be + * declared there and be visible to application code. */ +extern mbedtls_psa_drbg_context_t *const mbedtls_psa_random_state; + +/** A pointer to the PSA DRBG state. + * + * This macro expands to an expression that is suitable as the \c p_rng + * parameter to pass to mbedtls_psa_get_random(). + * + * This macro exists in all configurations where the psa_crypto module is + * enabled. Its expansion depends on the configuration. + */ +#define MBEDTLS_PSA_RANDOM_STATE mbedtls_psa_random_state + +/** Seed the PSA DRBG. + * + * \param entropy An entropy context to read the seed from. + * \param custom The personalization string. + * This can be \c NULL, in which case the personalization + * string is empty regardless of the value of \p len. + * \param len The length of the personalization string. + * + * \return \c 0 on success. + * \return An Mbed TLS error code (\c MBEDTLS_ERR_xxx) on failure. + */ +static inline int mbedtls_psa_drbg_seed( + mbedtls_entropy_context *entropy, + const unsigned char *custom, size_t len) +{ +#if defined(MBEDTLS_CTR_DRBG_C) + return mbedtls_ctr_drbg_seed(MBEDTLS_PSA_RANDOM_STATE, + mbedtls_entropy_func, + entropy, + custom, len); +#elif defined(MBEDTLS_HMAC_DRBG_C) + const mbedtls_md_info_t *md_info = + mbedtls_md_info_from_type(MBEDTLS_PSA_HMAC_DRBG_MD_TYPE); + return mbedtls_hmac_drbg_seed(MBEDTLS_PSA_RANDOM_STATE, + md_info, + mbedtls_entropy_func, + entropy, + custom, len); +#endif +} + +#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */ + +#endif /* PSA_CRYPTO_RANDOM_IMPL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.c index 065e55a..7803fef 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.c @@ -1,739 +1,739 @@ -/* - * PSA RSA layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include -#include "psa/crypto_values.h" -#include "psa_crypto_core.h" -#include "psa_crypto_random_impl.h" -#include "psa_crypto_rsa.h" -#include "psa_crypto_hash.h" -#include "md_psa.h" - -#include -#include -#include "mbedtls/platform.h" - -#include -#include -#include -#include "pk_wrap.h" - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) - -/* Mbed TLS doesn't support non-byte-aligned key sizes (i.e. key sizes - * that are not a multiple of 8) well. For example, there is only - * mbedtls_rsa_get_len(), which returns a number of bytes, and no - * way to return the exact bit size of a key. - * To keep things simple, reject non-byte-aligned key sizes. */ -static psa_status_t psa_check_rsa_key_byte_aligned( - const mbedtls_rsa_context *rsa) -{ - mbedtls_mpi n; - psa_status_t status; - mbedtls_mpi_init(&n); - status = mbedtls_to_psa_error( - mbedtls_rsa_export(rsa, &n, NULL, NULL, NULL, NULL)); - if (status == PSA_SUCCESS) { - if (mbedtls_mpi_bitlen(&n) % 8 != 0) { - status = PSA_ERROR_NOT_SUPPORTED; - } - } - mbedtls_mpi_free(&n); - return status; -} - -psa_status_t mbedtls_psa_rsa_load_representation( - psa_key_type_t type, const uint8_t *data, size_t data_length, - mbedtls_rsa_context **p_rsa) -{ - psa_status_t status; - mbedtls_pk_context ctx; - size_t bits; - mbedtls_pk_init(&ctx); - - /* Parse the data. */ - if (PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - status = mbedtls_to_psa_error( - mbedtls_pk_parse_key(&ctx, data, data_length, NULL, 0, - mbedtls_psa_get_random, MBEDTLS_PSA_RANDOM_STATE)); - } else { - status = mbedtls_to_psa_error( - mbedtls_pk_parse_public_key(&ctx, data, data_length)); - } - if (status != PSA_SUCCESS) { - goto exit; - } - - /* We have something that the pkparse module recognizes. If it is a - * valid RSA key, store it. */ - if (mbedtls_pk_get_type(&ctx) != MBEDTLS_PK_RSA) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - /* The size of an RSA key doesn't have to be a multiple of 8. Mbed TLS - * supports non-byte-aligned key sizes, but not well. For example, - * mbedtls_rsa_get_len() returns the key size in bytes, not in bits. */ - bits = PSA_BYTES_TO_BITS(mbedtls_rsa_get_len(mbedtls_pk_rsa(ctx))); - if (bits > PSA_VENDOR_RSA_MAX_KEY_BITS) { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = psa_check_rsa_key_byte_aligned(mbedtls_pk_rsa(ctx)); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Copy out the pointer to the RSA context, and reset the PK context - * such that pk_free doesn't free the RSA context we just grabbed. */ - *p_rsa = mbedtls_pk_rsa(ctx); - ctx.pk_info = NULL; - -exit: - mbedtls_pk_free(&ctx); - return status; -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - -#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) -psa_status_t mbedtls_psa_rsa_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits) -{ - psa_status_t status; - mbedtls_rsa_context *rsa = NULL; - - /* Parse input */ - status = mbedtls_psa_rsa_load_representation(attributes->core.type, - data, - data_length, - &rsa); - if (status != PSA_SUCCESS) { - goto exit; - } - - *bits = (psa_key_bits_t) PSA_BYTES_TO_BITS(mbedtls_rsa_get_len(rsa)); - - /* Re-export the data to PSA export format, such that we can store export - * representation in the key slot. Export representation in case of RSA is - * the smallest representation that's allowed as input, so a straight-up - * allocation of the same size as the input buffer will be large enough. */ - status = mbedtls_psa_rsa_export_key(attributes->core.type, - rsa, - key_buffer, - key_buffer_size, - key_buffer_length); -exit: - /* Always free the RSA object */ - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - - return status; -} -#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ - defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) -psa_status_t mbedtls_psa_rsa_export_key(psa_key_type_t type, - mbedtls_rsa_context *rsa, - uint8_t *data, - size_t data_size, - size_t *data_length) -{ - int ret; - mbedtls_pk_context pk; - uint8_t *pos = data + data_size; - - mbedtls_pk_init(&pk); - pk.pk_info = &mbedtls_rsa_info; - pk.pk_ctx = rsa; - - /* PSA Crypto API defines the format of an RSA key as a DER-encoded - * representation of the non-encrypted PKCS#1 RSAPrivateKey for a - * private key and of the RFC3279 RSAPublicKey for a public key. */ - if (PSA_KEY_TYPE_IS_KEY_PAIR(type)) { - ret = mbedtls_pk_write_key_der(&pk, data, data_size); - } else { - ret = mbedtls_pk_write_pubkey(&pos, data, &pk); - } - - if (ret < 0) { - /* Clean up in case pk_write failed halfway through. */ - memset(data, 0, data_size); - return mbedtls_to_psa_error(ret); - } - - /* The mbedtls_pk_xxx functions write to the end of the buffer. - * Move the data to the beginning and erase remaining data - * at the original location. */ - if (2 * (size_t) ret <= data_size) { - memcpy(data, data + data_size - ret, ret); - memset(data + data_size - ret, 0, ret); - } else if ((size_t) ret < data_size) { - memmove(data, data + data_size - ret, ret); - memset(data + ret, 0, data_size - ret); - } - - *data_length = ret; - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_rsa_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_rsa_context *rsa = NULL; - - status = mbedtls_psa_rsa_load_representation( - attributes->core.type, key_buffer, key_buffer_size, &rsa); - if (status != PSA_SUCCESS) { - return status; - } - - status = mbedtls_psa_rsa_export_key(PSA_KEY_TYPE_RSA_PUBLIC_KEY, - rsa, - data, - data_size, - data_length); - - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - - return status; -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || - * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ - -#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) -static psa_status_t psa_rsa_read_exponent(const uint8_t *domain_parameters, - size_t domain_parameters_size, - int *exponent) -{ - size_t i; - uint32_t acc = 0; - - if (domain_parameters_size == 0) { - *exponent = 65537; - return PSA_SUCCESS; - } - - /* Mbed TLS encodes the public exponent as an int. For simplicity, only - * support values that fit in a 32-bit integer, which is larger than - * int on just about every platform anyway. */ - if (domain_parameters_size > sizeof(acc)) { - return PSA_ERROR_NOT_SUPPORTED; - } - for (i = 0; i < domain_parameters_size; i++) { - acc = (acc << 8) | domain_parameters[i]; - } - if (acc > INT_MAX) { - return PSA_ERROR_NOT_SUPPORTED; - } - *exponent = acc; - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_rsa_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) -{ - psa_status_t status; - mbedtls_rsa_context rsa; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - int exponent; - - status = psa_rsa_read_exponent(attributes->domain_parameters, - attributes->domain_parameters_size, - &exponent); - if (status != PSA_SUCCESS) { - return status; - } - - mbedtls_rsa_init(&rsa); - ret = mbedtls_rsa_gen_key(&rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - (unsigned int) attributes->core.bits, - exponent); - if (ret != 0) { - return mbedtls_to_psa_error(ret); - } - - status = mbedtls_psa_rsa_export_key(attributes->core.type, - &rsa, key_buffer, key_buffer_size, - key_buffer_length); - mbedtls_rsa_free(&rsa); - - return status; -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ - -/****************************************************************/ -/* Sign/verify hashes */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) - -/* Decode the hash algorithm from alg and store the mbedtls encoding in - * md_alg. Verify that the hash length is acceptable. */ -static psa_status_t psa_rsa_decode_md_type(psa_algorithm_t alg, - size_t hash_length, - mbedtls_md_type_t *md_alg) -{ - psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); - *md_alg = mbedtls_md_type_from_psa_alg(hash_alg); - - /* The Mbed TLS RSA module uses an unsigned int for hash length - * parameters. Validate that it fits so that we don't risk an - * overflow later. */ -#if SIZE_MAX > UINT_MAX - if (hash_length > UINT_MAX) { - return PSA_ERROR_INVALID_ARGUMENT; - } -#endif - - /* For signatures using a hash, the hash length must be correct. */ - if (alg != PSA_ALG_RSA_PKCS1V15_SIGN_RAW) { - if (*md_alg == MBEDTLS_MD_NONE) { - return PSA_ERROR_NOT_SUPPORTED; - } - if (mbedtls_md_get_size_from_type(*md_alg) != hash_length) { - return PSA_ERROR_INVALID_ARGUMENT; - } - } - - return PSA_SUCCESS; -} - -psa_status_t mbedtls_psa_rsa_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_rsa_context *rsa = NULL; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - mbedtls_md_type_t md_alg; - - status = mbedtls_psa_rsa_load_representation(attributes->core.type, - key_buffer, - key_buffer_size, - &rsa); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_rsa_decode_md_type(alg, hash_length, &md_alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (signature_size < mbedtls_rsa_get_len(rsa)) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto exit; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) - if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { - ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V15, - MBEDTLS_MD_NONE); - if (ret == 0) { - ret = mbedtls_rsa_pkcs1_sign(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - md_alg, - (unsigned int) hash_length, - hash, - signature); - } - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) - if (PSA_ALG_IS_RSA_PSS(alg)) { - ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); - - if (ret == 0) { - ret = mbedtls_rsa_rsassa_pss_sign(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - MBEDTLS_MD_NONE, - (unsigned int) hash_length, - hash, - signature); - } - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ - { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - if (ret == 0) { - *signature_length = mbedtls_rsa_get_len(rsa); - } - status = mbedtls_to_psa_error(ret); - -exit: - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - - return status; -} - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) -static int rsa_pss_expected_salt_len(psa_algorithm_t alg, - const mbedtls_rsa_context *rsa, - size_t hash_length) -{ - if (PSA_ALG_IS_RSA_PSS_ANY_SALT(alg)) { - return MBEDTLS_RSA_SALT_LEN_ANY; - } - /* Otherwise: standard salt length, i.e. largest possible salt length - * up to the hash length. */ - int klen = (int) mbedtls_rsa_get_len(rsa); // known to fit - int hlen = (int) hash_length; // known to fit - int room = klen - 2 - hlen; - if (room < 0) { - return 0; // there is no valid signature in this case anyway - } else if (room > hlen) { - return hlen; - } else { - return room; - } -} -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ - -psa_status_t mbedtls_psa_rsa_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - mbedtls_rsa_context *rsa = NULL; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - mbedtls_md_type_t md_alg; - - status = mbedtls_psa_rsa_load_representation(attributes->core.type, - key_buffer, - key_buffer_size, - &rsa); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_rsa_decode_md_type(alg, hash_length, &md_alg); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (signature_length != mbedtls_rsa_get_len(rsa)) { - status = PSA_ERROR_INVALID_SIGNATURE; - goto exit; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) - if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { - ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V15, - MBEDTLS_MD_NONE); - if (ret == 0) { - ret = mbedtls_rsa_pkcs1_verify(rsa, - md_alg, - (unsigned int) hash_length, - hash, - signature); - } - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) - if (PSA_ALG_IS_RSA_PSS(alg)) { - ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); - if (ret == 0) { - int slen = rsa_pss_expected_salt_len(alg, rsa, hash_length); - ret = mbedtls_rsa_rsassa_pss_verify_ext(rsa, - md_alg, - (unsigned) hash_length, - hash, - md_alg, - slen, - signature); - } - } else -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ - { - status = PSA_ERROR_INVALID_ARGUMENT; - goto exit; - } - - /* Mbed TLS distinguishes "invalid padding" from "valid padding but - * the rest of the signature is invalid". This has little use in - * practice and PSA doesn't report this distinction. */ - status = (ret == MBEDTLS_ERR_RSA_INVALID_PADDING) ? - PSA_ERROR_INVALID_SIGNATURE : - mbedtls_to_psa_error(ret); - -exit: - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); - - return status; -} - -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ - -/****************************************************************/ -/* Asymmetric cryptography */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) -static int psa_rsa_oaep_set_padding_mode(psa_algorithm_t alg, - mbedtls_rsa_context *rsa) -{ - psa_algorithm_t hash_alg = PSA_ALG_RSA_OAEP_GET_HASH(alg); - mbedtls_md_type_t md_alg = mbedtls_md_type_from_psa_alg(hash_alg); - - /* Just to get the error status right, as rsa_set_padding() doesn't - * distinguish between "bad RSA algorithm" and "unknown hash". */ - if (mbedtls_md_info_from_type(md_alg) == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - return mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); -} -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ - -psa_status_t mbedtls_psa_asymmetric_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - (void) key_buffer; - (void) key_buffer_size; - (void) input; - (void) input_length; - (void) salt; - (void) salt_length; - (void) output; - (void) output_size; - (void) output_length; - - if (PSA_KEY_TYPE_IS_RSA(attributes->core.type)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) - mbedtls_rsa_context *rsa = NULL; - status = mbedtls_psa_rsa_load_representation(attributes->core.type, - key_buffer, - key_buffer_size, - &rsa); - if (status != PSA_SUCCESS) { - goto rsa_exit; - } - - if (output_size < mbedtls_rsa_get_len(rsa)) { - status = PSA_ERROR_BUFFER_TOO_SMALL; - goto rsa_exit; - } -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ - if (alg == PSA_ALG_RSA_PKCS1V15_CRYPT) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) - status = mbedtls_to_psa_error( - mbedtls_rsa_pkcs1_encrypt(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - input_length, - input, - output)); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ - } else - if (PSA_ALG_IS_RSA_OAEP(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) - status = mbedtls_to_psa_error( - psa_rsa_oaep_set_padding_mode(alg, rsa)); - if (status != PSA_SUCCESS) { - goto rsa_exit; - } - - status = mbedtls_to_psa_error( - mbedtls_rsa_rsaes_oaep_encrypt(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - salt, salt_length, - input_length, - input, - output)); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ - } else { - status = PSA_ERROR_INVALID_ARGUMENT; - } -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) -rsa_exit: - if (status == PSA_SUCCESS) { - *output_length = mbedtls_rsa_get_len(rsa); - } - - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ - } else { - status = PSA_ERROR_NOT_SUPPORTED; - } - - return status; -} - -psa_status_t mbedtls_psa_asymmetric_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - (void) key_buffer; - (void) key_buffer_size; - (void) input; - (void) input_length; - (void) salt; - (void) salt_length; - (void) output; - (void) output_size; - (void) output_length; - - *output_length = 0; - - if (attributes->core.type == PSA_KEY_TYPE_RSA_KEY_PAIR) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) - mbedtls_rsa_context *rsa = NULL; - status = mbedtls_psa_rsa_load_representation(attributes->core.type, - key_buffer, - key_buffer_size, - &rsa); - if (status != PSA_SUCCESS) { - goto rsa_exit; - } - - if (input_length != mbedtls_rsa_get_len(rsa)) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto rsa_exit; - } -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ - - if (alg == PSA_ALG_RSA_PKCS1V15_CRYPT) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) - status = mbedtls_to_psa_error( - mbedtls_rsa_pkcs1_decrypt(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - output_length, - input, - output, - output_size)); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ - } else - if (PSA_ALG_IS_RSA_OAEP(alg)) { -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) - status = mbedtls_to_psa_error( - psa_rsa_oaep_set_padding_mode(alg, rsa)); - if (status != PSA_SUCCESS) { - goto rsa_exit; - } - - status = mbedtls_to_psa_error( - mbedtls_rsa_rsaes_oaep_decrypt(rsa, - mbedtls_psa_get_random, - MBEDTLS_PSA_RANDOM_STATE, - salt, salt_length, - output_length, - input, - output, - output_size)); -#else - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ - } else { - status = PSA_ERROR_INVALID_ARGUMENT; - } - -#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ - defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) -rsa_exit: - mbedtls_rsa_free(rsa); - mbedtls_free(rsa); -#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || - * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ - } else { - status = PSA_ERROR_NOT_SUPPORTED; - } - - return status; -} - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA RSA layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include +#include "psa/crypto_values.h" +#include "psa_crypto_core.h" +#include "psa_crypto_random_impl.h" +#include "psa_crypto_rsa.h" +#include "psa_crypto_hash.h" +#include "md_psa.h" + +#include +#include +#include "mbedtls/platform.h" + +#include +#include +#include +#include "pk_wrap.h" + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + +/* Mbed TLS doesn't support non-byte-aligned key sizes (i.e. key sizes + * that are not a multiple of 8) well. For example, there is only + * mbedtls_rsa_get_len(), which returns a number of bytes, and no + * way to return the exact bit size of a key. + * To keep things simple, reject non-byte-aligned key sizes. */ +static psa_status_t psa_check_rsa_key_byte_aligned( + const mbedtls_rsa_context *rsa) +{ + mbedtls_mpi n; + psa_status_t status; + mbedtls_mpi_init(&n); + status = mbedtls_to_psa_error( + mbedtls_rsa_export(rsa, &n, NULL, NULL, NULL, NULL)); + if (status == PSA_SUCCESS) { + if (mbedtls_mpi_bitlen(&n) % 8 != 0) { + status = PSA_ERROR_NOT_SUPPORTED; + } + } + mbedtls_mpi_free(&n); + return status; +} + +psa_status_t mbedtls_psa_rsa_load_representation( + psa_key_type_t type, const uint8_t *data, size_t data_length, + mbedtls_rsa_context **p_rsa) +{ + psa_status_t status; + mbedtls_pk_context ctx; + size_t bits; + mbedtls_pk_init(&ctx); + + /* Parse the data. */ + if (PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + status = mbedtls_to_psa_error( + mbedtls_pk_parse_key(&ctx, data, data_length, NULL, 0, + mbedtls_psa_get_random, MBEDTLS_PSA_RANDOM_STATE)); + } else { + status = mbedtls_to_psa_error( + mbedtls_pk_parse_public_key(&ctx, data, data_length)); + } + if (status != PSA_SUCCESS) { + goto exit; + } + + /* We have something that the pkparse module recognizes. If it is a + * valid RSA key, store it. */ + if (mbedtls_pk_get_type(&ctx) != MBEDTLS_PK_RSA) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + /* The size of an RSA key doesn't have to be a multiple of 8. Mbed TLS + * supports non-byte-aligned key sizes, but not well. For example, + * mbedtls_rsa_get_len() returns the key size in bytes, not in bits. */ + bits = PSA_BYTES_TO_BITS(mbedtls_rsa_get_len(mbedtls_pk_rsa(ctx))); + if (bits > PSA_VENDOR_RSA_MAX_KEY_BITS) { + status = PSA_ERROR_NOT_SUPPORTED; + goto exit; + } + status = psa_check_rsa_key_byte_aligned(mbedtls_pk_rsa(ctx)); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Copy out the pointer to the RSA context, and reset the PK context + * such that pk_free doesn't free the RSA context we just grabbed. */ + *p_rsa = mbedtls_pk_rsa(ctx); + ctx.pk_info = NULL; + +exit: + mbedtls_pk_free(&ctx); + return status; +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +#if (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) +psa_status_t mbedtls_psa_rsa_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits) +{ + psa_status_t status; + mbedtls_rsa_context *rsa = NULL; + + /* Parse input */ + status = mbedtls_psa_rsa_load_representation(attributes->core.type, + data, + data_length, + &rsa); + if (status != PSA_SUCCESS) { + goto exit; + } + + *bits = (psa_key_bits_t) PSA_BYTES_TO_BITS(mbedtls_rsa_get_len(rsa)); + + /* Re-export the data to PSA export format, such that we can store export + * representation in the key slot. Export representation in case of RSA is + * the smallest representation that's allowed as input, so a straight-up + * allocation of the same size as the input buffer will be large enough. */ + status = mbedtls_psa_rsa_export_key(attributes->core.type, + rsa, + key_buffer, + key_buffer_size, + key_buffer_length); +exit: + /* Always free the RSA object */ + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + + return status; +} +#endif /* (defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_IMPORT) && + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT)) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) +psa_status_t mbedtls_psa_rsa_export_key(psa_key_type_t type, + mbedtls_rsa_context *rsa, + uint8_t *data, + size_t data_size, + size_t *data_length) +{ + int ret; + mbedtls_pk_context pk; + uint8_t *pos = data + data_size; + + mbedtls_pk_init(&pk); + pk.pk_info = &mbedtls_rsa_info; + pk.pk_ctx = rsa; + + /* PSA Crypto API defines the format of an RSA key as a DER-encoded + * representation of the non-encrypted PKCS#1 RSAPrivateKey for a + * private key and of the RFC3279 RSAPublicKey for a public key. */ + if (PSA_KEY_TYPE_IS_KEY_PAIR(type)) { + ret = mbedtls_pk_write_key_der(&pk, data, data_size); + } else { + ret = mbedtls_pk_write_pubkey(&pos, data, &pk); + } + + if (ret < 0) { + /* Clean up in case pk_write failed halfway through. */ + memset(data, 0, data_size); + return mbedtls_to_psa_error(ret); + } + + /* The mbedtls_pk_xxx functions write to the end of the buffer. + * Move the data to the beginning and erase remaining data + * at the original location. */ + if (2 * (size_t) ret <= data_size) { + memcpy(data, data + data_size - ret, ret); + memset(data + data_size - ret, 0, ret); + } else if ((size_t) ret < data_size) { + memmove(data, data + data_size - ret, ret); + memset(data + ret, 0, data_size - ret); + } + + *data_length = ret; + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_rsa_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_rsa_context *rsa = NULL; + + status = mbedtls_psa_rsa_load_representation( + attributes->core.type, key_buffer, key_buffer_size, &rsa); + if (status != PSA_SUCCESS) { + return status; + } + + status = mbedtls_psa_rsa_export_key(PSA_KEY_TYPE_RSA_PUBLIC_KEY, + rsa, + data, + data_size, + data_length); + + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + + return status; +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_EXPORT) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) +static psa_status_t psa_rsa_read_exponent(const uint8_t *domain_parameters, + size_t domain_parameters_size, + int *exponent) +{ + size_t i; + uint32_t acc = 0; + + if (domain_parameters_size == 0) { + *exponent = 65537; + return PSA_SUCCESS; + } + + /* Mbed TLS encodes the public exponent as an int. For simplicity, only + * support values that fit in a 32-bit integer, which is larger than + * int on just about every platform anyway. */ + if (domain_parameters_size > sizeof(acc)) { + return PSA_ERROR_NOT_SUPPORTED; + } + for (i = 0; i < domain_parameters_size; i++) { + acc = (acc << 8) | domain_parameters[i]; + } + if (acc > INT_MAX) { + return PSA_ERROR_NOT_SUPPORTED; + } + *exponent = acc; + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_rsa_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length) +{ + psa_status_t status; + mbedtls_rsa_context rsa; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + int exponent; + + status = psa_rsa_read_exponent(attributes->domain_parameters, + attributes->domain_parameters_size, + &exponent); + if (status != PSA_SUCCESS) { + return status; + } + + mbedtls_rsa_init(&rsa); + ret = mbedtls_rsa_gen_key(&rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + (unsigned int) attributes->core.bits, + exponent); + if (ret != 0) { + return mbedtls_to_psa_error(ret); + } + + status = mbedtls_psa_rsa_export_key(attributes->core.type, + &rsa, key_buffer, key_buffer_size, + key_buffer_length); + mbedtls_rsa_free(&rsa); + + return status; +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR_GENERATE) */ + +/****************************************************************/ +/* Sign/verify hashes */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) + +/* Decode the hash algorithm from alg and store the mbedtls encoding in + * md_alg. Verify that the hash length is acceptable. */ +static psa_status_t psa_rsa_decode_md_type(psa_algorithm_t alg, + size_t hash_length, + mbedtls_md_type_t *md_alg) +{ + psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH(alg); + *md_alg = mbedtls_md_type_from_psa_alg(hash_alg); + + /* The Mbed TLS RSA module uses an unsigned int for hash length + * parameters. Validate that it fits so that we don't risk an + * overflow later. */ +#if SIZE_MAX > UINT_MAX + if (hash_length > UINT_MAX) { + return PSA_ERROR_INVALID_ARGUMENT; + } +#endif + + /* For signatures using a hash, the hash length must be correct. */ + if (alg != PSA_ALG_RSA_PKCS1V15_SIGN_RAW) { + if (*md_alg == MBEDTLS_MD_NONE) { + return PSA_ERROR_NOT_SUPPORTED; + } + if (mbedtls_md_get_size_from_type(*md_alg) != hash_length) { + return PSA_ERROR_INVALID_ARGUMENT; + } + } + + return PSA_SUCCESS; +} + +psa_status_t mbedtls_psa_rsa_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_rsa_context *rsa = NULL; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_md_type_t md_alg; + + status = mbedtls_psa_rsa_load_representation(attributes->core.type, + key_buffer, + key_buffer_size, + &rsa); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_rsa_decode_md_type(alg, hash_length, &md_alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (signature_size < mbedtls_rsa_get_len(rsa)) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto exit; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) + if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { + ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V15, + MBEDTLS_MD_NONE); + if (ret == 0) { + ret = mbedtls_rsa_pkcs1_sign(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + md_alg, + (unsigned int) hash_length, + hash, + signature); + } + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) + if (PSA_ALG_IS_RSA_PSS(alg)) { + ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); + + if (ret == 0) { + ret = mbedtls_rsa_rsassa_pss_sign(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + MBEDTLS_MD_NONE, + (unsigned int) hash_length, + hash, + signature); + } + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + if (ret == 0) { + *signature_length = mbedtls_rsa_get_len(rsa); + } + status = mbedtls_to_psa_error(ret); + +exit: + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + + return status; +} + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) +static int rsa_pss_expected_salt_len(psa_algorithm_t alg, + const mbedtls_rsa_context *rsa, + size_t hash_length) +{ + if (PSA_ALG_IS_RSA_PSS_ANY_SALT(alg)) { + return MBEDTLS_RSA_SALT_LEN_ANY; + } + /* Otherwise: standard salt length, i.e. largest possible salt length + * up to the hash length. */ + int klen = (int) mbedtls_rsa_get_len(rsa); // known to fit + int hlen = (int) hash_length; // known to fit + int room = klen - 2 - hlen; + if (room < 0) { + return 0; // there is no valid signature in this case anyway + } else if (room > hlen) { + return hlen; + } else { + return room; + } +} +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ + +psa_status_t mbedtls_psa_rsa_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + mbedtls_rsa_context *rsa = NULL; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_md_type_t md_alg; + + status = mbedtls_psa_rsa_load_representation(attributes->core.type, + key_buffer, + key_buffer_size, + &rsa); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_rsa_decode_md_type(alg, hash_length, &md_alg); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (signature_length != mbedtls_rsa_get_len(rsa)) { + status = PSA_ERROR_INVALID_SIGNATURE; + goto exit; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) + if (PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg)) { + ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V15, + MBEDTLS_MD_NONE); + if (ret == 0) { + ret = mbedtls_rsa_pkcs1_verify(rsa, + md_alg, + (unsigned int) hash_length, + hash, + signature); + } + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) + if (PSA_ALG_IS_RSA_PSS(alg)) { + ret = mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); + if (ret == 0) { + int slen = rsa_pss_expected_salt_len(alg, rsa, hash_length); + ret = mbedtls_rsa_rsassa_pss_verify_ext(rsa, + md_alg, + (unsigned) hash_length, + hash, + md_alg, + slen, + signature); + } + } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } + + /* Mbed TLS distinguishes "invalid padding" from "valid padding but + * the rest of the signature is invalid". This has little use in + * practice and PSA doesn't report this distinction. */ + status = (ret == MBEDTLS_ERR_RSA_INVALID_PADDING) ? + PSA_ERROR_INVALID_SIGNATURE : + mbedtls_to_psa_error(ret); + +exit: + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); + + return status; +} + +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ + +/****************************************************************/ +/* Asymmetric cryptography */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) +static int psa_rsa_oaep_set_padding_mode(psa_algorithm_t alg, + mbedtls_rsa_context *rsa) +{ + psa_algorithm_t hash_alg = PSA_ALG_RSA_OAEP_GET_HASH(alg); + mbedtls_md_type_t md_alg = mbedtls_md_type_from_psa_alg(hash_alg); + + /* Just to get the error status right, as rsa_set_padding() doesn't + * distinguish between "bad RSA algorithm" and "unknown hash". */ + if (mbedtls_md_info_from_type(md_alg) == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + return mbedtls_rsa_set_padding(rsa, MBEDTLS_RSA_PKCS_V21, md_alg); +} +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ + +psa_status_t mbedtls_psa_asymmetric_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + (void) key_buffer; + (void) key_buffer_size; + (void) input; + (void) input_length; + (void) salt; + (void) salt_length; + (void) output; + (void) output_size; + (void) output_length; + + if (PSA_KEY_TYPE_IS_RSA(attributes->core.type)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) + mbedtls_rsa_context *rsa = NULL; + status = mbedtls_psa_rsa_load_representation(attributes->core.type, + key_buffer, + key_buffer_size, + &rsa); + if (status != PSA_SUCCESS) { + goto rsa_exit; + } + + if (output_size < mbedtls_rsa_get_len(rsa)) { + status = PSA_ERROR_BUFFER_TOO_SMALL; + goto rsa_exit; + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ + if (alg == PSA_ALG_RSA_PKCS1V15_CRYPT) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) + status = mbedtls_to_psa_error( + mbedtls_rsa_pkcs1_encrypt(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + input_length, + input, + output)); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ + } else + if (PSA_ALG_IS_RSA_OAEP(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) + status = mbedtls_to_psa_error( + psa_rsa_oaep_set_padding_mode(alg, rsa)); + if (status != PSA_SUCCESS) { + goto rsa_exit; + } + + status = mbedtls_to_psa_error( + mbedtls_rsa_rsaes_oaep_encrypt(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + salt, salt_length, + input_length, + input, + output)); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ + } else { + status = PSA_ERROR_INVALID_ARGUMENT; + } +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) +rsa_exit: + if (status == PSA_SUCCESS) { + *output_length = mbedtls_rsa_get_len(rsa); + } + + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ + } else { + status = PSA_ERROR_NOT_SUPPORTED; + } + + return status; +} + +psa_status_t mbedtls_psa_asymmetric_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + (void) key_buffer; + (void) key_buffer_size; + (void) input; + (void) input_length; + (void) salt; + (void) salt_length; + (void) output; + (void) output_size; + (void) output_length; + + *output_length = 0; + + if (attributes->core.type == PSA_KEY_TYPE_RSA_KEY_PAIR) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) + mbedtls_rsa_context *rsa = NULL; + status = mbedtls_psa_rsa_load_representation(attributes->core.type, + key_buffer, + key_buffer_size, + &rsa); + if (status != PSA_SUCCESS) { + goto rsa_exit; + } + + if (input_length != mbedtls_rsa_get_len(rsa)) { + status = PSA_ERROR_INVALID_ARGUMENT; + goto rsa_exit; + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ + + if (alg == PSA_ALG_RSA_PKCS1V15_CRYPT) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) + status = mbedtls_to_psa_error( + mbedtls_rsa_pkcs1_decrypt(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + output_length, + input, + output, + output_size)); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ + } else + if (PSA_ALG_IS_RSA_OAEP(alg)) { +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) + status = mbedtls_to_psa_error( + psa_rsa_oaep_set_padding_mode(alg, rsa)); + if (status != PSA_SUCCESS) { + goto rsa_exit; + } + + status = mbedtls_to_psa_error( + mbedtls_rsa_rsaes_oaep_decrypt(rsa, + mbedtls_psa_get_random, + MBEDTLS_PSA_RANDOM_STATE, + salt, salt_length, + output_length, + input, + output, + output_size)); +#else + status = PSA_ERROR_NOT_SUPPORTED; +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ + } else { + status = PSA_ERROR_INVALID_ARGUMENT; + } + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) +rsa_exit: + mbedtls_rsa_free(rsa); + mbedtls_free(rsa); +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ + } else { + status = PSA_ERROR_NOT_SUPPORTED; + } + + return status; +} + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.h index bc24ef5..4fcebd1 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_rsa.h @@ -1,329 +1,329 @@ -/* - * PSA RSA layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_RSA_H -#define PSA_CRYPTO_RSA_H - -#include -#include - -/** Load the contents of a key buffer into an internal RSA representation - * - * \param[in] type The type of key contained in \p data. - * \param[in] data The buffer from which to load the representation. - * \param[in] data_length The size in bytes of \p data. - * \param[out] p_rsa Returns a pointer to an RSA context on success. - * The caller is responsible for freeing both the - * contents of the context and the context itself - * when done. - */ -psa_status_t mbedtls_psa_rsa_load_representation(psa_key_type_t type, - const uint8_t *data, - size_t data_length, - mbedtls_rsa_context **p_rsa); - -/** Import an RSA key in binary format. - * - * \note The signature of this function is that of a PSA driver - * import_key entry point. This function behaves as an import_key - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes for the key to import. - * \param[in] data The buffer containing the key data in import - * format. - * \param[in] data_length Size of the \p data buffer in bytes. - * \param[out] key_buffer The buffer containing the key data in output - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This - * size is greater or equal to \p data_length. - * \param[out] key_buffer_length The length of the data written in \p - * key_buffer in bytes. - * \param[out] bits The key size in number of bits. - * - * \retval #PSA_SUCCESS The RSA key was imported successfully. - * \retval #PSA_ERROR_INVALID_ARGUMENT - * The key data is not correctly formatted. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - */ -psa_status_t mbedtls_psa_rsa_import_key( - const psa_key_attributes_t *attributes, - const uint8_t *data, size_t data_length, - uint8_t *key_buffer, size_t key_buffer_size, - size_t *key_buffer_length, size_t *bits); - -/** Export an RSA key to export representation - * - * \param[in] type The type of key (public/private) to export - * \param[in] rsa The internal RSA representation from which to export - * \param[out] data The buffer to export to - * \param[in] data_size The length of the buffer to export to - * \param[out] data_length The amount of bytes written to \p data - */ -psa_status_t mbedtls_psa_rsa_export_key(psa_key_type_t type, - mbedtls_rsa_context *rsa, - uint8_t *data, - size_t data_size, - size_t *data_length); - -/** Export a public RSA key or the public part of an RSA key pair in binary - * format. - * - * \note The signature of this function is that of a PSA driver - * export_public_key entry point. This function behaves as an - * export_public_key entry point as defined in the PSA driver interface - * specification. - * - * \param[in] attributes The attributes for the key to export. - * \param[in] key_buffer Material or context of the key to export. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[out] data Buffer where the key data is to be written. - * \param[in] data_size Size of the \p data buffer in bytes. - * \param[out] data_length On success, the number of bytes written in - * \p data. - * - * \retval #PSA_SUCCESS The RSA public key was exported successfully. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_rsa_export_public_key( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - uint8_t *data, size_t data_size, size_t *data_length); - -/** - * \brief Generate an RSA key. - * - * \note The signature of the function is that of a PSA driver generate_key - * entry point. - * - * \param[in] attributes The attributes for the RSA key to generate. - * \param[out] key_buffer Buffer where the key data is to be written. - * \param[in] key_buffer_size Size of \p key_buffer in bytes. - * \param[out] key_buffer_length On success, the number of bytes written in - * \p key_buffer. - * - * \retval #PSA_SUCCESS - * The key was successfully generated. - * \retval #PSA_ERROR_NOT_SUPPORTED - * Key length or type not supported. - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of \p key_buffer is too small. - */ -psa_status_t mbedtls_psa_rsa_generate_key( - const psa_key_attributes_t *attributes, - uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); - -/** Sign an already-calculated hash with an RSA private key. - * - * \note The signature of this function is that of a PSA driver - * sign_hash entry point. This function behaves as a sign_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the RSA key to use for the - * operation. - * \param[in] key_buffer The buffer containing the RSA key context. - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * an RSA key. - * \param[in] hash The hash or message to sign. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[out] signature Buffer where the signature is to be written. - * \param[in] signature_size Size of the \p signature buffer in bytes. - * \param[out] signature_length On success, the number of bytes - * that make up the returned signature value. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p signature buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_SIGN_OUTPUT_SIZE(\c PSA_KEY_TYPE_RSA_KEY_PAIR, \c key_bits, - * \p alg) where \c key_bits is the bit-size of the RSA key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - */ -psa_status_t mbedtls_psa_rsa_sign_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - uint8_t *signature, size_t signature_size, size_t *signature_length); - -/** - * \brief Verify the signature a hash or short message using a public RSA key. - * - * \note The signature of this function is that of a PSA driver - * verify_hash entry point. This function behaves as a verify_hash - * entry point as defined in the PSA driver interface specification for - * transparent drivers. - * - * \param[in] attributes The attributes of the RSA key to use for the - * operation. - * \param[in] key_buffer The buffer containing the RSA key context. - * format. - * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] alg A signature algorithm that is compatible with - * an RSA key. - * \param[in] hash The hash or message whose signature is to be - * verified. - * \param[in] hash_length Size of the \p hash buffer in bytes. - * \param[in] signature Buffer containing the signature to verify. - * \param[in] signature_length Size of the \p signature buffer in bytes. - * - * \retval #PSA_SUCCESS - * The signature is valid. - * \retval #PSA_ERROR_INVALID_SIGNATURE - * The calculation was performed successfully, but the passed - * signature is not a valid signature. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - */ -psa_status_t mbedtls_psa_rsa_verify_hash( - const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, size_t key_buffer_size, - psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, - const uint8_t *signature, size_t signature_length); - -/** - * \brief Encrypt a short message with a public key. - * - * \param attributes The attributes for the key to import. - * \param key_buffer Buffer where the key data is to be written. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the encrypted message is to - * be written. - * \param output_size Size of the \p output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t mbedtls_psa_asymmetric_encrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -/** - * \brief Decrypt a short message with a private key. - * - * \param attributes The attributes for the key to import. - * \param key_buffer Buffer where the key data is to be written. - * \param key_buffer_size Size of the \p key_buffer buffer in bytes. - * \param[in] input The message to decrypt. - * \param input_length Size of the \p input buffer in bytes. - * \param[in] salt A salt or label, if supported by the - * encryption algorithm. - * If the algorithm does not support a - * salt, pass \c NULL. - * If the algorithm supports an optional - * salt and you do not want to pass a salt, - * pass \c NULL. - * - * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is - * supported. - * \param salt_length Size of the \p salt buffer in bytes. - * If \p salt is \c NULL, pass 0. - * \param[out] output Buffer where the decrypted message is to - * be written. - * \param output_size Size of the \c output buffer in bytes. - * \param[out] output_length On success, the number of bytes - * that make up the returned output. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_BUFFER_TOO_SMALL - * The size of the \p output buffer is too small. You can - * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) - * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p key. - * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription - * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription - * \retval #PSA_ERROR_INVALID_PADDING \emptydescription - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t mbedtls_psa_asymmetric_decrypt(const psa_key_attributes_t *attributes, - const uint8_t *key_buffer, - size_t key_buffer_size, - psa_algorithm_t alg, - const uint8_t *input, - size_t input_length, - const uint8_t *salt, - size_t salt_length, - uint8_t *output, - size_t output_size, - size_t *output_length); - -#endif /* PSA_CRYPTO_RSA_H */ +/* + * PSA RSA layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_RSA_H +#define PSA_CRYPTO_RSA_H + +#include +#include + +/** Load the contents of a key buffer into an internal RSA representation + * + * \param[in] type The type of key contained in \p data. + * \param[in] data The buffer from which to load the representation. + * \param[in] data_length The size in bytes of \p data. + * \param[out] p_rsa Returns a pointer to an RSA context on success. + * The caller is responsible for freeing both the + * contents of the context and the context itself + * when done. + */ +psa_status_t mbedtls_psa_rsa_load_representation(psa_key_type_t type, + const uint8_t *data, + size_t data_length, + mbedtls_rsa_context **p_rsa); + +/** Import an RSA key in binary format. + * + * \note The signature of this function is that of a PSA driver + * import_key entry point. This function behaves as an import_key + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes for the key to import. + * \param[in] data The buffer containing the key data in import + * format. + * \param[in] data_length Size of the \p data buffer in bytes. + * \param[out] key_buffer The buffer containing the key data in output + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. This + * size is greater or equal to \p data_length. + * \param[out] key_buffer_length The length of the data written in \p + * key_buffer in bytes. + * \param[out] bits The key size in number of bits. + * + * \retval #PSA_SUCCESS The RSA key was imported successfully. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * The key data is not correctly formatted. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + */ +psa_status_t mbedtls_psa_rsa_import_key( + const psa_key_attributes_t *attributes, + const uint8_t *data, size_t data_length, + uint8_t *key_buffer, size_t key_buffer_size, + size_t *key_buffer_length, size_t *bits); + +/** Export an RSA key to export representation + * + * \param[in] type The type of key (public/private) to export + * \param[in] rsa The internal RSA representation from which to export + * \param[out] data The buffer to export to + * \param[in] data_size The length of the buffer to export to + * \param[out] data_length The amount of bytes written to \p data + */ +psa_status_t mbedtls_psa_rsa_export_key(psa_key_type_t type, + mbedtls_rsa_context *rsa, + uint8_t *data, + size_t data_size, + size_t *data_length); + +/** Export a public RSA key or the public part of an RSA key pair in binary + * format. + * + * \note The signature of this function is that of a PSA driver + * export_public_key entry point. This function behaves as an + * export_public_key entry point as defined in the PSA driver interface + * specification. + * + * \param[in] attributes The attributes for the key to export. + * \param[in] key_buffer Material or context of the key to export. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[out] data Buffer where the key data is to be written. + * \param[in] data_size Size of the \p data buffer in bytes. + * \param[out] data_length On success, the number of bytes written in + * \p data. + * + * \retval #PSA_SUCCESS The RSA public key was exported successfully. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_rsa_export_public_key( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + uint8_t *data, size_t data_size, size_t *data_length); + +/** + * \brief Generate an RSA key. + * + * \note The signature of the function is that of a PSA driver generate_key + * entry point. + * + * \param[in] attributes The attributes for the RSA key to generate. + * \param[out] key_buffer Buffer where the key data is to be written. + * \param[in] key_buffer_size Size of \p key_buffer in bytes. + * \param[out] key_buffer_length On success, the number of bytes written in + * \p key_buffer. + * + * \retval #PSA_SUCCESS + * The key was successfully generated. + * \retval #PSA_ERROR_NOT_SUPPORTED + * Key length or type not supported. + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of \p key_buffer is too small. + */ +psa_status_t mbedtls_psa_rsa_generate_key( + const psa_key_attributes_t *attributes, + uint8_t *key_buffer, size_t key_buffer_size, size_t *key_buffer_length); + +/** Sign an already-calculated hash with an RSA private key. + * + * \note The signature of this function is that of a PSA driver + * sign_hash entry point. This function behaves as a sign_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the RSA key to use for the + * operation. + * \param[in] key_buffer The buffer containing the RSA key context. + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * an RSA key. + * \param[in] hash The hash or message to sign. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[out] signature Buffer where the signature is to be written. + * \param[in] signature_size Size of the \p signature buffer in bytes. + * \param[out] signature_length On success, the number of bytes + * that make up the returned signature value. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p signature buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_SIGN_OUTPUT_SIZE(\c PSA_KEY_TYPE_RSA_KEY_PAIR, \c key_bits, + * \p alg) where \c key_bits is the bit-size of the RSA key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + */ +psa_status_t mbedtls_psa_rsa_sign_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + uint8_t *signature, size_t signature_size, size_t *signature_length); + +/** + * \brief Verify the signature a hash or short message using a public RSA key. + * + * \note The signature of this function is that of a PSA driver + * verify_hash entry point. This function behaves as a verify_hash + * entry point as defined in the PSA driver interface specification for + * transparent drivers. + * + * \param[in] attributes The attributes of the RSA key to use for the + * operation. + * \param[in] key_buffer The buffer containing the RSA key context. + * format. + * \param[in] key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] alg A signature algorithm that is compatible with + * an RSA key. + * \param[in] hash The hash or message whose signature is to be + * verified. + * \param[in] hash_length Size of the \p hash buffer in bytes. + * \param[in] signature Buffer containing the signature to verify. + * \param[in] signature_length Size of the \p signature buffer in bytes. + * + * \retval #PSA_SUCCESS + * The signature is valid. + * \retval #PSA_ERROR_INVALID_SIGNATURE + * The calculation was performed successfully, but the passed + * signature is not a valid signature. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + */ +psa_status_t mbedtls_psa_rsa_verify_hash( + const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, size_t key_buffer_size, + psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, + const uint8_t *signature, size_t signature_length); + +/** + * \brief Encrypt a short message with a public key. + * + * \param attributes The attributes for the key to import. + * \param key_buffer Buffer where the key data is to be written. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param input_length Size of the \p input buffer in bytes. + * \param[in] salt A salt or label, if supported by the + * encryption algorithm. + * If the algorithm does not support a + * salt, pass \c NULL. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass \c NULL. + * + * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param salt_length Size of the \p salt buffer in bytes. + * If \p salt is \c NULL, pass 0. + * \param[out] output Buffer where the encrypted message is to + * be written. + * \param output_size Size of the \p output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t mbedtls_psa_asymmetric_encrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +/** + * \brief Decrypt a short message with a private key. + * + * \param attributes The attributes for the key to import. + * \param key_buffer Buffer where the key data is to be written. + * \param key_buffer_size Size of the \p key_buffer buffer in bytes. + * \param[in] input The message to decrypt. + * \param input_length Size of the \p input buffer in bytes. + * \param[in] salt A salt or label, if supported by the + * encryption algorithm. + * If the algorithm does not support a + * salt, pass \c NULL. + * If the algorithm supports an optional + * salt and you do not want to pass a salt, + * pass \c NULL. + * + * - For #PSA_ALG_RSA_PKCS1V15_CRYPT, no salt is + * supported. + * \param salt_length Size of the \p salt buffer in bytes. + * If \p salt is \c NULL, pass 0. + * \param[out] output Buffer where the decrypted message is to + * be written. + * \param output_size Size of the \c output buffer in bytes. + * \param[out] output_length On success, the number of bytes + * that make up the returned output. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_BUFFER_TOO_SMALL + * The size of the \p output buffer is too small. You can + * determine a sufficient buffer size by calling + * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * where \c key_type and \c key_bits are the type and bit-size + * respectively of \p key. + * \retval #PSA_ERROR_NOT_SUPPORTED \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_COMMUNICATION_FAILURE \emptydescription + * \retval #PSA_ERROR_HARDWARE_FAILURE \emptydescription + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_ENTROPY \emptydescription + * \retval #PSA_ERROR_INVALID_PADDING \emptydescription + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t mbedtls_psa_asymmetric_decrypt(const psa_key_attributes_t *attributes, + const uint8_t *key_buffer, + size_t key_buffer_size, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + const uint8_t *salt, + size_t salt_length, + uint8_t *output, + size_t output_size, + size_t *output_length); + +#endif /* PSA_CRYPTO_RSA_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.c index 9db3ded..a79f53c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.c @@ -1,385 +1,385 @@ -/* - * PSA crypto support for secure element drivers - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - -#include -#include - -#include "psa/crypto_se_driver.h" - -#include "psa_crypto_se.h" - -#if defined(MBEDTLS_PSA_ITS_FILE_C) -#include "psa_crypto_its.h" -#else /* Native ITS implementation */ -#include "psa/error.h" -#include "psa/internal_trusted_storage.h" -#endif - -#include "mbedtls/platform.h" - - - -/****************************************************************/ -/* Driver lookup */ -/****************************************************************/ - -/* This structure is identical to psa_drv_se_context_t declared in - * `crypto_se_driver.h`, except that some parts are writable here - * (non-const, or pointer to non-const). */ -typedef struct { - void *persistent_data; - size_t persistent_data_size; - uintptr_t transient_data; -} psa_drv_se_internal_context_t; - -struct psa_se_drv_table_entry_s { - psa_key_location_t location; - const psa_drv_se_t *methods; - union { - psa_drv_se_internal_context_t internal; - psa_drv_se_context_t context; - } u; -}; - -static psa_se_drv_table_entry_t driver_table[PSA_MAX_SE_DRIVERS]; - -psa_se_drv_table_entry_t *psa_get_se_driver_entry( - psa_key_lifetime_t lifetime) -{ - size_t i; - psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(lifetime); - /* In the driver table, location=0 means an entry that isn't used. - * No driver has a location of 0 because it's a reserved value - * (which designates transparent keys). Make sure we never return - * a driver entry for location 0. */ - if (location == 0) { - return NULL; - } - for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { - if (driver_table[i].location == location) { - return &driver_table[i]; - } - } - return NULL; -} - -const psa_drv_se_t *psa_get_se_driver_methods( - const psa_se_drv_table_entry_t *driver) -{ - return driver->methods; -} - -psa_drv_se_context_t *psa_get_se_driver_context( - psa_se_drv_table_entry_t *driver) -{ - return &driver->u.context; -} - -int psa_get_se_driver(psa_key_lifetime_t lifetime, - const psa_drv_se_t **p_methods, - psa_drv_se_context_t **p_drv_context) -{ - psa_se_drv_table_entry_t *driver = psa_get_se_driver_entry(lifetime); - if (p_methods != NULL) { - *p_methods = (driver ? driver->methods : NULL); - } - if (p_drv_context != NULL) { - *p_drv_context = (driver ? &driver->u.context : NULL); - } - return driver != NULL; -} - - - -/****************************************************************/ -/* Persistent data management */ -/****************************************************************/ - -static psa_status_t psa_get_se_driver_its_file_uid( - const psa_se_drv_table_entry_t *driver, - psa_storage_uid_t *uid) -{ - if (driver->location > PSA_MAX_SE_LOCATION) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* ITS file sizes are limited to 32 bits. */ - if (driver->u.internal.persistent_data_size > UINT32_MAX) { - return PSA_ERROR_NOT_SUPPORTED; - } - - /* See the documentation of PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE. */ - *uid = PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE + driver->location; - return PSA_SUCCESS; -} - -psa_status_t psa_load_se_persistent_data( - const psa_se_drv_table_entry_t *driver) -{ - psa_status_t status; - psa_storage_uid_t uid; - size_t length; - - status = psa_get_se_driver_its_file_uid(driver, &uid); - if (status != PSA_SUCCESS) { - return status; - } - - /* Read the amount of persistent data that the driver requests. - * If the data in storage is larger, it is truncated. If the data - * in storage is smaller, silently keep what is already at the end - * of the output buffer. */ - /* psa_get_se_driver_its_file_uid ensures that the size_t - * persistent_data_size is in range, but compilers don't know that, - * so cast to reassure them. */ - return psa_its_get(uid, 0, - (uint32_t) driver->u.internal.persistent_data_size, - driver->u.internal.persistent_data, - &length); -} - -psa_status_t psa_save_se_persistent_data( - const psa_se_drv_table_entry_t *driver) -{ - psa_status_t status; - psa_storage_uid_t uid; - - status = psa_get_se_driver_its_file_uid(driver, &uid); - if (status != PSA_SUCCESS) { - return status; - } - - /* psa_get_se_driver_its_file_uid ensures that the size_t - * persistent_data_size is in range, but compilers don't know that, - * so cast to reassure them. */ - return psa_its_set(uid, - (uint32_t) driver->u.internal.persistent_data_size, - driver->u.internal.persistent_data, - 0); -} - -psa_status_t psa_destroy_se_persistent_data(psa_key_location_t location) -{ - psa_storage_uid_t uid; - if (location > PSA_MAX_SE_LOCATION) { - return PSA_ERROR_NOT_SUPPORTED; - } - uid = PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE + location; - return psa_its_remove(uid); -} - -psa_status_t psa_find_se_slot_for_key( - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_se_drv_table_entry_t *driver, - psa_key_slot_number_t *slot_number) -{ - psa_status_t status; - psa_key_location_t key_location = - PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); - - /* If the location is wrong, it's a bug in the library. */ - if (driver->location != key_location) { - return PSA_ERROR_CORRUPTION_DETECTED; - } - - /* If the driver doesn't support key creation in any way, give up now. */ - if (driver->methods->key_management == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - - if (psa_get_key_slot_number(attributes, slot_number) == PSA_SUCCESS) { - /* The application wants to use a specific slot. Allow it if - * the driver supports it. On a system with isolation, - * the crypto service must check that the application is - * permitted to request this slot. */ - psa_drv_se_validate_slot_number_t p_validate_slot_number = - driver->methods->key_management->p_validate_slot_number; - if (p_validate_slot_number == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - status = p_validate_slot_number(&driver->u.context, - driver->u.internal.persistent_data, - attributes, method, - *slot_number); - } else if (method == PSA_KEY_CREATION_REGISTER) { - /* The application didn't specify a slot number. This doesn't - * make sense when registering a slot. */ - return PSA_ERROR_INVALID_ARGUMENT; - } else { - /* The application didn't tell us which slot to use. Let the driver - * choose. This is the normal case. */ - psa_drv_se_allocate_key_t p_allocate = - driver->methods->key_management->p_allocate; - if (p_allocate == NULL) { - return PSA_ERROR_NOT_SUPPORTED; - } - status = p_allocate(&driver->u.context, - driver->u.internal.persistent_data, - attributes, method, - slot_number); - } - return status; -} - -psa_status_t psa_destroy_se_key(psa_se_drv_table_entry_t *driver, - psa_key_slot_number_t slot_number) -{ - psa_status_t status; - psa_status_t storage_status; - /* Normally a missing method would mean that the action is not - * supported. But psa_destroy_key() is not supposed to return - * PSA_ERROR_NOT_SUPPORTED: if you can create a key, you should - * be able to destroy it. The only use case for a driver that - * does not have a way to destroy keys at all is if the keys are - * locked in a read-only state: we can use the keys but not - * destroy them. Hence, if the driver doesn't support destroying - * keys, it's really a lack of permission. */ - if (driver->methods->key_management == NULL || - driver->methods->key_management->p_destroy == NULL) { - return PSA_ERROR_NOT_PERMITTED; - } - status = driver->methods->key_management->p_destroy( - &driver->u.context, - driver->u.internal.persistent_data, - slot_number); - storage_status = psa_save_se_persistent_data(driver); - return status == PSA_SUCCESS ? storage_status : status; -} - -psa_status_t psa_init_all_se_drivers(void) -{ - size_t i; - for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { - psa_se_drv_table_entry_t *driver = &driver_table[i]; - if (driver->location == 0) { - continue; /* skipping unused entry */ - } - const psa_drv_se_t *methods = psa_get_se_driver_methods(driver); - if (methods->p_init != NULL) { - psa_status_t status = methods->p_init( - &driver->u.context, - driver->u.internal.persistent_data, - driver->location); - if (status != PSA_SUCCESS) { - return status; - } - status = psa_save_se_persistent_data(driver); - if (status != PSA_SUCCESS) { - return status; - } - } - } - return PSA_SUCCESS; -} - - - -/****************************************************************/ -/* Driver registration */ -/****************************************************************/ - -psa_status_t psa_register_se_driver( - psa_key_location_t location, - const psa_drv_se_t *methods) -{ - size_t i; - psa_status_t status; - - if (methods->hal_version != PSA_DRV_SE_HAL_VERSION) { - return PSA_ERROR_NOT_SUPPORTED; - } - /* Driver table entries are 0-initialized. 0 is not a valid driver - * location because it means a transparent key. */ - MBEDTLS_STATIC_ASSERT(PSA_KEY_LOCATION_LOCAL_STORAGE == 0, - "Secure element support requires 0 to mean a local key"); - - if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { - return PSA_ERROR_INVALID_ARGUMENT; - } - if (location > PSA_MAX_SE_LOCATION) { - return PSA_ERROR_NOT_SUPPORTED; - } - - for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { - if (driver_table[i].location == 0) { - break; - } - /* Check that location isn't already in use up to the first free - * entry. Since entries are created in order and never deleted, - * there can't be a used entry after the first free entry. */ - if (driver_table[i].location == location) { - return PSA_ERROR_ALREADY_EXISTS; - } - } - if (i == PSA_MAX_SE_DRIVERS) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - driver_table[i].location = location; - driver_table[i].methods = methods; - driver_table[i].u.internal.persistent_data_size = - methods->persistent_data_size; - - if (methods->persistent_data_size != 0) { - driver_table[i].u.internal.persistent_data = - mbedtls_calloc(1, methods->persistent_data_size); - if (driver_table[i].u.internal.persistent_data == NULL) { - status = PSA_ERROR_INSUFFICIENT_MEMORY; - goto error; - } - /* Load the driver's persistent data. On first use, the persistent - * data does not exist in storage, and is initialized to - * all-bits-zero by the calloc call just above. */ - status = psa_load_se_persistent_data(&driver_table[i]); - if (status != PSA_SUCCESS && status != PSA_ERROR_DOES_NOT_EXIST) { - goto error; - } - } - - return PSA_SUCCESS; - -error: - memset(&driver_table[i], 0, sizeof(driver_table[i])); - return status; -} - -void psa_unregister_all_se_drivers(void) -{ - size_t i; - for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { - if (driver_table[i].u.internal.persistent_data != NULL) { - mbedtls_free(driver_table[i].u.internal.persistent_data); - } - } - memset(driver_table, 0, sizeof(driver_table)); -} - - - -/****************************************************************/ -/* The end */ -/****************************************************************/ - -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ +/* + * PSA crypto support for secure element drivers + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + +#include +#include + +#include "psa/crypto_se_driver.h" + +#include "psa_crypto_se.h" + +#if defined(MBEDTLS_PSA_ITS_FILE_C) +#include "psa_crypto_its.h" +#else /* Native ITS implementation */ +#include "psa/error.h" +#include "psa/internal_trusted_storage.h" +#endif + +#include "mbedtls/platform.h" + + + +/****************************************************************/ +/* Driver lookup */ +/****************************************************************/ + +/* This structure is identical to psa_drv_se_context_t declared in + * `crypto_se_driver.h`, except that some parts are writable here + * (non-const, or pointer to non-const). */ +typedef struct { + void *persistent_data; + size_t persistent_data_size; + uintptr_t transient_data; +} psa_drv_se_internal_context_t; + +struct psa_se_drv_table_entry_s { + psa_key_location_t location; + const psa_drv_se_t *methods; + union { + psa_drv_se_internal_context_t internal; + psa_drv_se_context_t context; + } u; +}; + +static psa_se_drv_table_entry_t driver_table[PSA_MAX_SE_DRIVERS]; + +psa_se_drv_table_entry_t *psa_get_se_driver_entry( + psa_key_lifetime_t lifetime) +{ + size_t i; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(lifetime); + /* In the driver table, location=0 means an entry that isn't used. + * No driver has a location of 0 because it's a reserved value + * (which designates transparent keys). Make sure we never return + * a driver entry for location 0. */ + if (location == 0) { + return NULL; + } + for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { + if (driver_table[i].location == location) { + return &driver_table[i]; + } + } + return NULL; +} + +const psa_drv_se_t *psa_get_se_driver_methods( + const psa_se_drv_table_entry_t *driver) +{ + return driver->methods; +} + +psa_drv_se_context_t *psa_get_se_driver_context( + psa_se_drv_table_entry_t *driver) +{ + return &driver->u.context; +} + +int psa_get_se_driver(psa_key_lifetime_t lifetime, + const psa_drv_se_t **p_methods, + psa_drv_se_context_t **p_drv_context) +{ + psa_se_drv_table_entry_t *driver = psa_get_se_driver_entry(lifetime); + if (p_methods != NULL) { + *p_methods = (driver ? driver->methods : NULL); + } + if (p_drv_context != NULL) { + *p_drv_context = (driver ? &driver->u.context : NULL); + } + return driver != NULL; +} + + + +/****************************************************************/ +/* Persistent data management */ +/****************************************************************/ + +static psa_status_t psa_get_se_driver_its_file_uid( + const psa_se_drv_table_entry_t *driver, + psa_storage_uid_t *uid) +{ + if (driver->location > PSA_MAX_SE_LOCATION) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* ITS file sizes are limited to 32 bits. */ + if (driver->u.internal.persistent_data_size > UINT32_MAX) { + return PSA_ERROR_NOT_SUPPORTED; + } + + /* See the documentation of PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE. */ + *uid = PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE + driver->location; + return PSA_SUCCESS; +} + +psa_status_t psa_load_se_persistent_data( + const psa_se_drv_table_entry_t *driver) +{ + psa_status_t status; + psa_storage_uid_t uid; + size_t length; + + status = psa_get_se_driver_its_file_uid(driver, &uid); + if (status != PSA_SUCCESS) { + return status; + } + + /* Read the amount of persistent data that the driver requests. + * If the data in storage is larger, it is truncated. If the data + * in storage is smaller, silently keep what is already at the end + * of the output buffer. */ + /* psa_get_se_driver_its_file_uid ensures that the size_t + * persistent_data_size is in range, but compilers don't know that, + * so cast to reassure them. */ + return psa_its_get(uid, 0, + (uint32_t) driver->u.internal.persistent_data_size, + driver->u.internal.persistent_data, + &length); +} + +psa_status_t psa_save_se_persistent_data( + const psa_se_drv_table_entry_t *driver) +{ + psa_status_t status; + psa_storage_uid_t uid; + + status = psa_get_se_driver_its_file_uid(driver, &uid); + if (status != PSA_SUCCESS) { + return status; + } + + /* psa_get_se_driver_its_file_uid ensures that the size_t + * persistent_data_size is in range, but compilers don't know that, + * so cast to reassure them. */ + return psa_its_set(uid, + (uint32_t) driver->u.internal.persistent_data_size, + driver->u.internal.persistent_data, + 0); +} + +psa_status_t psa_destroy_se_persistent_data(psa_key_location_t location) +{ + psa_storage_uid_t uid; + if (location > PSA_MAX_SE_LOCATION) { + return PSA_ERROR_NOT_SUPPORTED; + } + uid = PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE + location; + return psa_its_remove(uid); +} + +psa_status_t psa_find_se_slot_for_key( + const psa_key_attributes_t *attributes, + psa_key_creation_method_t method, + psa_se_drv_table_entry_t *driver, + psa_key_slot_number_t *slot_number) +{ + psa_status_t status; + psa_key_location_t key_location = + PSA_KEY_LIFETIME_GET_LOCATION(psa_get_key_lifetime(attributes)); + + /* If the location is wrong, it's a bug in the library. */ + if (driver->location != key_location) { + return PSA_ERROR_CORRUPTION_DETECTED; + } + + /* If the driver doesn't support key creation in any way, give up now. */ + if (driver->methods->key_management == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + + if (psa_get_key_slot_number(attributes, slot_number) == PSA_SUCCESS) { + /* The application wants to use a specific slot. Allow it if + * the driver supports it. On a system with isolation, + * the crypto service must check that the application is + * permitted to request this slot. */ + psa_drv_se_validate_slot_number_t p_validate_slot_number = + driver->methods->key_management->p_validate_slot_number; + if (p_validate_slot_number == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + status = p_validate_slot_number(&driver->u.context, + driver->u.internal.persistent_data, + attributes, method, + *slot_number); + } else if (method == PSA_KEY_CREATION_REGISTER) { + /* The application didn't specify a slot number. This doesn't + * make sense when registering a slot. */ + return PSA_ERROR_INVALID_ARGUMENT; + } else { + /* The application didn't tell us which slot to use. Let the driver + * choose. This is the normal case. */ + psa_drv_se_allocate_key_t p_allocate = + driver->methods->key_management->p_allocate; + if (p_allocate == NULL) { + return PSA_ERROR_NOT_SUPPORTED; + } + status = p_allocate(&driver->u.context, + driver->u.internal.persistent_data, + attributes, method, + slot_number); + } + return status; +} + +psa_status_t psa_destroy_se_key(psa_se_drv_table_entry_t *driver, + psa_key_slot_number_t slot_number) +{ + psa_status_t status; + psa_status_t storage_status; + /* Normally a missing method would mean that the action is not + * supported. But psa_destroy_key() is not supposed to return + * PSA_ERROR_NOT_SUPPORTED: if you can create a key, you should + * be able to destroy it. The only use case for a driver that + * does not have a way to destroy keys at all is if the keys are + * locked in a read-only state: we can use the keys but not + * destroy them. Hence, if the driver doesn't support destroying + * keys, it's really a lack of permission. */ + if (driver->methods->key_management == NULL || + driver->methods->key_management->p_destroy == NULL) { + return PSA_ERROR_NOT_PERMITTED; + } + status = driver->methods->key_management->p_destroy( + &driver->u.context, + driver->u.internal.persistent_data, + slot_number); + storage_status = psa_save_se_persistent_data(driver); + return status == PSA_SUCCESS ? storage_status : status; +} + +psa_status_t psa_init_all_se_drivers(void) +{ + size_t i; + for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { + psa_se_drv_table_entry_t *driver = &driver_table[i]; + if (driver->location == 0) { + continue; /* skipping unused entry */ + } + const psa_drv_se_t *methods = psa_get_se_driver_methods(driver); + if (methods->p_init != NULL) { + psa_status_t status = methods->p_init( + &driver->u.context, + driver->u.internal.persistent_data, + driver->location); + if (status != PSA_SUCCESS) { + return status; + } + status = psa_save_se_persistent_data(driver); + if (status != PSA_SUCCESS) { + return status; + } + } + } + return PSA_SUCCESS; +} + + + +/****************************************************************/ +/* Driver registration */ +/****************************************************************/ + +psa_status_t psa_register_se_driver( + psa_key_location_t location, + const psa_drv_se_t *methods) +{ + size_t i; + psa_status_t status; + + if (methods->hal_version != PSA_DRV_SE_HAL_VERSION) { + return PSA_ERROR_NOT_SUPPORTED; + } + /* Driver table entries are 0-initialized. 0 is not a valid driver + * location because it means a transparent key. */ + MBEDTLS_STATIC_ASSERT(PSA_KEY_LOCATION_LOCAL_STORAGE == 0, + "Secure element support requires 0 to mean a local key"); + + if (location == PSA_KEY_LOCATION_LOCAL_STORAGE) { + return PSA_ERROR_INVALID_ARGUMENT; + } + if (location > PSA_MAX_SE_LOCATION) { + return PSA_ERROR_NOT_SUPPORTED; + } + + for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { + if (driver_table[i].location == 0) { + break; + } + /* Check that location isn't already in use up to the first free + * entry. Since entries are created in order and never deleted, + * there can't be a used entry after the first free entry. */ + if (driver_table[i].location == location) { + return PSA_ERROR_ALREADY_EXISTS; + } + } + if (i == PSA_MAX_SE_DRIVERS) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + driver_table[i].location = location; + driver_table[i].methods = methods; + driver_table[i].u.internal.persistent_data_size = + methods->persistent_data_size; + + if (methods->persistent_data_size != 0) { + driver_table[i].u.internal.persistent_data = + mbedtls_calloc(1, methods->persistent_data_size); + if (driver_table[i].u.internal.persistent_data == NULL) { + status = PSA_ERROR_INSUFFICIENT_MEMORY; + goto error; + } + /* Load the driver's persistent data. On first use, the persistent + * data does not exist in storage, and is initialized to + * all-bits-zero by the calloc call just above. */ + status = psa_load_se_persistent_data(&driver_table[i]); + if (status != PSA_SUCCESS && status != PSA_ERROR_DOES_NOT_EXIST) { + goto error; + } + } + + return PSA_SUCCESS; + +error: + memset(&driver_table[i], 0, sizeof(driver_table[i])); + return status; +} + +void psa_unregister_all_se_drivers(void) +{ + size_t i; + for (i = 0; i < PSA_MAX_SE_DRIVERS; i++) { + if (driver_table[i].u.internal.persistent_data != NULL) { + mbedtls_free(driver_table[i].u.internal.persistent_data); + } + } + memset(driver_table, 0, sizeof(driver_table)); +} + + + +/****************************************************************/ +/* The end */ +/****************************************************************/ + +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.h index a1e5e09..99a490c 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_se.h @@ -1,197 +1,197 @@ -/* - * PSA crypto support for secure element drivers - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_SE_H -#define PSA_CRYPTO_SE_H - -#include "mbedtls/build_info.h" - -#include "psa/crypto.h" -#include "psa/crypto_se_driver.h" - -/** The maximum location value that this implementation supports - * for a secure element. - * - * This is not a characteristic that each PSA implementation has, but a - * limitation of the current implementation due to the constraints imposed - * by storage. See #PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE. - * - * The minimum location value for a secure element is 1, like on any - * PSA implementation (0 means a transparent key). - */ -#define PSA_MAX_SE_LOCATION 255 - -/** The base of the range of ITS file identifiers for secure element - * driver persistent data. - * - * We use a slice of the implementation reserved range 0xffff0000..0xffffffff, - * specifically the range 0xfffffe00..0xfffffeff. The length of this range - * drives the value of #PSA_MAX_SE_LOCATION. The identifier 0xfffffe00 is - * actually not used since it corresponds to #PSA_KEY_LOCATION_LOCAL_STORAGE - * which doesn't have a driver. - */ -#define PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE ((psa_key_id_t) 0xfffffe00) - -/** The maximum number of registered secure element driver locations. */ -#define PSA_MAX_SE_DRIVERS 4 - -/** Unregister all secure element drivers. - * - * \warning Do not call this function while the library is in the initialized - * state. This function is only intended to be called at the end - * of mbedtls_psa_crypto_free(). - */ -void psa_unregister_all_se_drivers(void); - -/** Initialize all secure element drivers. - * - * Called from psa_crypto_init(). - */ -psa_status_t psa_init_all_se_drivers(void); - -/** A structure that describes a registered secure element driver. - * - * A secure element driver table entry contains a pointer to the - * driver's method table as well as the driver context structure. - */ -typedef struct psa_se_drv_table_entry_s psa_se_drv_table_entry_t; - -/** Return the secure element driver information for a lifetime value. - * - * \param lifetime The lifetime value to query. - * \param[out] p_methods On output, if there is a driver, - * \c *methods points to its method table. - * Otherwise \c *methods is \c NULL. - * \param[out] p_drv_context On output, if there is a driver, - * \c *drv_context points to its context - * structure. - * Otherwise \c *drv_context is \c NULL. - * - * \retval 1 - * \p lifetime corresponds to a registered driver. - * \retval 0 - * \p lifetime does not correspond to a registered driver. - */ -int psa_get_se_driver(psa_key_lifetime_t lifetime, - const psa_drv_se_t **p_methods, - psa_drv_se_context_t **p_drv_context); - -/** Return the secure element driver table entry for a lifetime value. - * - * \param lifetime The lifetime value to query. - * - * \return The driver table entry for \p lifetime, or - * \p NULL if \p lifetime does not correspond to a registered driver. - */ -psa_se_drv_table_entry_t *psa_get_se_driver_entry( - psa_key_lifetime_t lifetime); - -/** Return the method table for a secure element driver. - * - * \param[in] driver The driver table entry to access, or \c NULL. - * - * \return The driver's method table. - * \c NULL if \p driver is \c NULL. - */ -const psa_drv_se_t *psa_get_se_driver_methods( - const psa_se_drv_table_entry_t *driver); - -/** Return the context of a secure element driver. - * - * \param[in] driver The driver table entry to access, or \c NULL. - * - * \return A pointer to the driver context. - * \c NULL if \p driver is \c NULL. - */ -psa_drv_se_context_t *psa_get_se_driver_context( - psa_se_drv_table_entry_t *driver); - -/** Find a free slot for a key that is to be created. - * - * This function calls the relevant method in the driver to find a suitable - * slot for a key with the given attributes. - * - * \param[in] attributes Metadata about the key that is about to be created. - * \param[in] driver The driver table entry to query. - * \param[out] slot_number On success, a slot number that is free in this - * secure element. - */ -psa_status_t psa_find_se_slot_for_key( - const psa_key_attributes_t *attributes, - psa_key_creation_method_t method, - psa_se_drv_table_entry_t *driver, - psa_key_slot_number_t *slot_number); - -/** Destroy a key in a secure element. - * - * This function calls the relevant driver method to destroy a key - * and updates the driver's persistent data. - */ -psa_status_t psa_destroy_se_key(psa_se_drv_table_entry_t *driver, - psa_key_slot_number_t slot_number); - -/** Load the persistent data of a secure element driver. - * - * \param driver The driver table entry containing the persistent - * data to load from storage. - * - * \return #PSA_SUCCESS - * \return #PSA_ERROR_NOT_SUPPORTED - * \return #PSA_ERROR_DOES_NOT_EXIST - * \return #PSA_ERROR_STORAGE_FAILURE - * \return #PSA_ERROR_DATA_CORRUPT - * \return #PSA_ERROR_INVALID_ARGUMENT - */ -psa_status_t psa_load_se_persistent_data( - const psa_se_drv_table_entry_t *driver); - -/** Save the persistent data of a secure element driver. - * - * \param[in] driver The driver table entry containing the persistent - * data to save to storage. - * - * \return #PSA_SUCCESS - * \return #PSA_ERROR_NOT_SUPPORTED - * \return #PSA_ERROR_NOT_PERMITTED - * \return #PSA_ERROR_NOT_SUPPORTED - * \return #PSA_ERROR_INSUFFICIENT_STORAGE - * \return #PSA_ERROR_STORAGE_FAILURE - * \return #PSA_ERROR_INVALID_ARGUMENT - */ -psa_status_t psa_save_se_persistent_data( - const psa_se_drv_table_entry_t *driver); - -/** Destroy the persistent data of a secure element driver. - * - * This is currently only used for testing. - * - * \param[in] location The location identifier for the driver whose - * persistent data is to be erased. - */ -psa_status_t psa_destroy_se_persistent_data(psa_key_location_t location); - - -/** The storage representation of a key whose data is in a secure element. - */ -typedef struct { - uint8_t slot_number[sizeof(psa_key_slot_number_t)]; -} psa_se_key_data_storage_t; - -#endif /* PSA_CRYPTO_SE_H */ +/* + * PSA crypto support for secure element drivers + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_SE_H +#define PSA_CRYPTO_SE_H + +#include "mbedtls/build_info.h" + +#include "psa/crypto.h" +#include "psa/crypto_se_driver.h" + +/** The maximum location value that this implementation supports + * for a secure element. + * + * This is not a characteristic that each PSA implementation has, but a + * limitation of the current implementation due to the constraints imposed + * by storage. See #PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE. + * + * The minimum location value for a secure element is 1, like on any + * PSA implementation (0 means a transparent key). + */ +#define PSA_MAX_SE_LOCATION 255 + +/** The base of the range of ITS file identifiers for secure element + * driver persistent data. + * + * We use a slice of the implementation reserved range 0xffff0000..0xffffffff, + * specifically the range 0xfffffe00..0xfffffeff. The length of this range + * drives the value of #PSA_MAX_SE_LOCATION. The identifier 0xfffffe00 is + * actually not used since it corresponds to #PSA_KEY_LOCATION_LOCAL_STORAGE + * which doesn't have a driver. + */ +#define PSA_CRYPTO_SE_DRIVER_ITS_UID_BASE ((psa_key_id_t) 0xfffffe00) + +/** The maximum number of registered secure element driver locations. */ +#define PSA_MAX_SE_DRIVERS 4 + +/** Unregister all secure element drivers. + * + * \warning Do not call this function while the library is in the initialized + * state. This function is only intended to be called at the end + * of mbedtls_psa_crypto_free(). + */ +void psa_unregister_all_se_drivers(void); + +/** Initialize all secure element drivers. + * + * Called from psa_crypto_init(). + */ +psa_status_t psa_init_all_se_drivers(void); + +/** A structure that describes a registered secure element driver. + * + * A secure element driver table entry contains a pointer to the + * driver's method table as well as the driver context structure. + */ +typedef struct psa_se_drv_table_entry_s psa_se_drv_table_entry_t; + +/** Return the secure element driver information for a lifetime value. + * + * \param lifetime The lifetime value to query. + * \param[out] p_methods On output, if there is a driver, + * \c *methods points to its method table. + * Otherwise \c *methods is \c NULL. + * \param[out] p_drv_context On output, if there is a driver, + * \c *drv_context points to its context + * structure. + * Otherwise \c *drv_context is \c NULL. + * + * \retval 1 + * \p lifetime corresponds to a registered driver. + * \retval 0 + * \p lifetime does not correspond to a registered driver. + */ +int psa_get_se_driver(psa_key_lifetime_t lifetime, + const psa_drv_se_t **p_methods, + psa_drv_se_context_t **p_drv_context); + +/** Return the secure element driver table entry for a lifetime value. + * + * \param lifetime The lifetime value to query. + * + * \return The driver table entry for \p lifetime, or + * \p NULL if \p lifetime does not correspond to a registered driver. + */ +psa_se_drv_table_entry_t *psa_get_se_driver_entry( + psa_key_lifetime_t lifetime); + +/** Return the method table for a secure element driver. + * + * \param[in] driver The driver table entry to access, or \c NULL. + * + * \return The driver's method table. + * \c NULL if \p driver is \c NULL. + */ +const psa_drv_se_t *psa_get_se_driver_methods( + const psa_se_drv_table_entry_t *driver); + +/** Return the context of a secure element driver. + * + * \param[in] driver The driver table entry to access, or \c NULL. + * + * \return A pointer to the driver context. + * \c NULL if \p driver is \c NULL. + */ +psa_drv_se_context_t *psa_get_se_driver_context( + psa_se_drv_table_entry_t *driver); + +/** Find a free slot for a key that is to be created. + * + * This function calls the relevant method in the driver to find a suitable + * slot for a key with the given attributes. + * + * \param[in] attributes Metadata about the key that is about to be created. + * \param[in] driver The driver table entry to query. + * \param[out] slot_number On success, a slot number that is free in this + * secure element. + */ +psa_status_t psa_find_se_slot_for_key( + const psa_key_attributes_t *attributes, + psa_key_creation_method_t method, + psa_se_drv_table_entry_t *driver, + psa_key_slot_number_t *slot_number); + +/** Destroy a key in a secure element. + * + * This function calls the relevant driver method to destroy a key + * and updates the driver's persistent data. + */ +psa_status_t psa_destroy_se_key(psa_se_drv_table_entry_t *driver, + psa_key_slot_number_t slot_number); + +/** Load the persistent data of a secure element driver. + * + * \param driver The driver table entry containing the persistent + * data to load from storage. + * + * \return #PSA_SUCCESS + * \return #PSA_ERROR_NOT_SUPPORTED + * \return #PSA_ERROR_DOES_NOT_EXIST + * \return #PSA_ERROR_STORAGE_FAILURE + * \return #PSA_ERROR_DATA_CORRUPT + * \return #PSA_ERROR_INVALID_ARGUMENT + */ +psa_status_t psa_load_se_persistent_data( + const psa_se_drv_table_entry_t *driver); + +/** Save the persistent data of a secure element driver. + * + * \param[in] driver The driver table entry containing the persistent + * data to save to storage. + * + * \return #PSA_SUCCESS + * \return #PSA_ERROR_NOT_SUPPORTED + * \return #PSA_ERROR_NOT_PERMITTED + * \return #PSA_ERROR_NOT_SUPPORTED + * \return #PSA_ERROR_INSUFFICIENT_STORAGE + * \return #PSA_ERROR_STORAGE_FAILURE + * \return #PSA_ERROR_INVALID_ARGUMENT + */ +psa_status_t psa_save_se_persistent_data( + const psa_se_drv_table_entry_t *driver); + +/** Destroy the persistent data of a secure element driver. + * + * This is currently only used for testing. + * + * \param[in] location The location identifier for the driver whose + * persistent data is to be erased. + */ +psa_status_t psa_destroy_se_persistent_data(psa_key_location_t location); + + +/** The storage representation of a key whose data is in a secure element. + */ +typedef struct { + uint8_t slot_number[sizeof(psa_key_slot_number_t)]; +} psa_se_key_data_storage_t; + +#endif /* PSA_CRYPTO_SE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.c index fb6e4e4..6336c68 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.c @@ -1,743 +1,743 @@ -/* - * PSA crypto layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include "psa/crypto.h" - -#include "psa_crypto_core.h" -#include "psa_crypto_driver_wrappers_no_static.h" -#include "psa_crypto_slot_management.h" -#include "psa_crypto_storage.h" -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -#include "psa_crypto_se.h" -#endif - -#include -#include -#include "mbedtls/threading.h" -#include "mbedtls/platform.h" - -typedef struct { - psa_key_slot_t key_slots[MBEDTLS_PSA_KEY_SLOT_COUNT]; - uint8_t key_slots_initialized; -} psa_global_data_t; - -static psa_global_data_t global_data; - -int psa_is_valid_key_id(mbedtls_svc_key_id_t key, int vendor_ok) -{ - psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); - - if ((PSA_KEY_ID_USER_MIN <= key_id) && - (key_id <= PSA_KEY_ID_USER_MAX)) { - return 1; - } - - if (vendor_ok && - (PSA_KEY_ID_VENDOR_MIN <= key_id) && - (key_id <= PSA_KEY_ID_VENDOR_MAX)) { - return 1; - } - - return 0; -} - -psa_status_t psa_slot_change_state( psa_key_slot_t *slot, - psa_key_slot_state_t target_state ) -{ - switch( slot->state ) - { - case PSA_STATE_EMPTY: - if( target_state != PSA_STATE_CREATING && - target_state != PSA_STATE_UNUSED && - target_state != PSA_STATE_WIPING ) - return( PSA_ERROR_INVALID_HANDLE ); - break; - case PSA_STATE_CREATING: - if( target_state != PSA_STATE_UNUSED && - target_state != PSA_STATE_DESTROYING && - target_state != PSA_STATE_WIPING ) - return( PSA_ERROR_BAD_STATE ); - break; - case PSA_STATE_UNUSED: - if( target_state != PSA_STATE_READING && - target_state != PSA_STATE_DESTROYING && - target_state != PSA_STATE_WIPING ) - return( PSA_ERROR_BAD_STATE ); - break; - case PSA_STATE_READING: - if( target_state != PSA_STATE_UNUSED && - target_state != PSA_STATE_DESTROYING && - target_state != PSA_STATE_WIPING && - target_state != PSA_STATE_READING ) - return( PSA_ERROR_BAD_STATE ); - if( target_state == PSA_STATE_UNUSED && - slot->reader_count > 0 ) - return( PSA_ERROR_BAD_STATE ); - break; - case PSA_STATE_DESTROYING: - if( target_state != PSA_STATE_EMPTY ) - return( PSA_ERROR_BAD_STATE ); - break; - case PSA_STATE_WIPING : - if( target_state != PSA_STATE_DESTROYING && - target_state != PSA_STATE_EMPTY ) - return( PSA_ERROR_BAD_STATE ); - break; - } - slot->state = target_state; - return( PSA_SUCCESS ); -} - -int psa_slot_has_no_readers( psa_key_slot_t *slot ) -{ - if( slot->reader_count == 0 ) - return( 1 ); - - return( 0 ); -} - -static psa_status_t psa_slot_add_reader( psa_key_slot_t *slot ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - - status = psa_slot_change_state( slot, PSA_STATE_READING ); - if( status != PSA_SUCCESS ) - return( status ); - - if( slot->reader_count >= SIZE_MAX ) - return( PSA_ERROR_CORRUPTION_DETECTED ); - - slot->reader_count++; - - return( PSA_SUCCESS ); -} - -/** Get the description in memory of a key given its identifier. - * - * The descriptions of volatile keys and loaded persistent keys are - * stored in key slots. This function returns a pointer to the key slot - * containing the description of a key given its identifier. - * - * The function searches the key slots containing the description of the key - * with \p key identifier. The function does only read accesses to the key - * slots. The function does not load any persistent key thus does not access - * any storage. - * - * For volatile key identifiers, only one key slot is queried as a volatile - * key with identifier key_id can only be stored in slot of index - * ( key_id - #PSA_KEY_ID_VOLATILE_MIN ). - * - * Please note that, if MBEDTLS_THREADING_C is enabled, this function should - * be called with locked mbedtls_psa_slots_mutex. - * - * \param key Key identifier to query. - * \param[out] p_slot On success, `*p_slot` contains a pointer to the - * key slot containing the description of the key - * identified by \p key. - * - * \retval #PSA_SUCCESS - * The pointer to the key slot containing the description of the key - * identified by \p key was returned. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p key is not a valid key identifier. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no key with key identifier \p key in the key slots. - */ -static psa_status_t psa_get_key_slot( - mbedtls_svc_key_id_t key, psa_key_slot_t **p_slot ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); - size_t slot_idx; - psa_key_slot_t *slot = NULL; - - if (psa_key_id_is_volatile(key_id)) { - slot = &global_data.key_slots[key_id - PSA_KEY_ID_VOLATILE_MIN]; - - /* - * Check if both the PSA key identifier key_id and the owner - * identifier of key match those of the key slot. - * - * Note that, if the key slot is not occupied, its PSA key identifier - * is equal to zero. This is an invalid value for a PSA key identifier - * and thus cannot be equal to the valid PSA key identifier key_id. - */ - status = mbedtls_svc_key_id_equal(key, slot->attr.id) ? - PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; - } else { - if (!psa_is_valid_key_id(key, 1)) { - return PSA_ERROR_INVALID_HANDLE; - } - - for (slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++) { - slot = &global_data.key_slots[slot_idx]; - if (mbedtls_svc_key_id_equal(key, slot->attr.id)) { - break; - } - } - status = (slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT) ? - PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; - } - - if( status != PSA_SUCCESS ) - return( status ); - else - *p_slot = slot; - - return( status ); -} - -psa_status_t psa_initialize_key_slots(void) -{ - /* Nothing to do: program startup and psa_wipe_all_key_slots() both - * guarantee that the key slots are initialized to all-zero, which - * means that all the key slots are in a valid, empty state. */ - global_data.key_slots_initialized = 1; - return PSA_SUCCESS; -} - -void psa_wipe_all_key_slots(void) -{ - size_t slot_idx; - -#if defined(MBEDTLS_THREADING_C) - (void) mbedtls_mutex_lock( &mbedtls_psa_slots_mutex ); -#endif - - for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) - { - psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; - (void) psa_slot_change_state( slot, PSA_STATE_WIPING ); - (void) psa_wipe_key_slot( slot ); - } - global_data.key_slots_initialized = 0; -#if defined(MBEDTLS_THREADING_C) - (void) mbedtls_mutex_unlock( &mbedtls_psa_slots_mutex ); -#endif -} - -psa_status_t psa_get_empty_key_slot(psa_key_id_t *volatile_key_id, - psa_key_slot_t **p_slot) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - size_t slot_idx; - psa_key_slot_t *selected_slot, *unlocked_persistent_key_slot; - if( ! global_data.key_slots_initialized ) - { - status = PSA_ERROR_BAD_STATE; - goto error; - } - - selected_slot = unlocked_persistent_key_slot = NULL; - for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) - { - psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; - if( slot->state == PSA_STATE_EMPTY ) - { - selected_slot = slot; - break; - } - - if( ( unlocked_persistent_key_slot == NULL ) && - ( ! PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) && - ( slot->state == PSA_STATE_UNUSED ) ) - unlocked_persistent_key_slot = slot; - } - - /* - * If there is no unused key slot and there is at least one unlocked key - * slot containing the description of a persistent key, recycle the first - * such key slot we encountered. If we later need to operate on the - * persistent key we are evicting now, we will reload its description from - * storage. - */ - if( ( selected_slot == NULL ) && ( unlocked_persistent_key_slot != NULL ) ) - { - selected_slot = unlocked_persistent_key_slot; - status = psa_slot_change_state( selected_slot, PSA_STATE_WIPING ); - if( status != PSA_SUCCESS ) - return( status ); - - psa_wipe_key_slot( selected_slot ); - } - - if( selected_slot != NULL ) - { - *volatile_key_id = PSA_KEY_ID_VOLATILE_MIN + - ((psa_key_id_t) (selected_slot - global_data.key_slots)); - *p_slot = selected_slot; - - return PSA_SUCCESS; - } - status = PSA_ERROR_INSUFFICIENT_MEMORY; - -error: - *p_slot = NULL; - *volatile_key_id = 0; - - return status; -} - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) -static psa_status_t psa_load_persistent_key_into_slot(psa_key_slot_t *slot) -{ - psa_status_t status = PSA_SUCCESS; - uint8_t *key_data = NULL; - size_t key_data_length = 0; - - status = psa_load_persistent_key(&slot->attr, - &key_data, &key_data_length); - if (status != PSA_SUCCESS) { - goto exit; - } - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* Special handling is required for loading keys associated with a - * dynamically registered SE interface. */ - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; - if (psa_get_se_driver(slot->attr.lifetime, &drv, &drv_context)) { - psa_se_key_data_storage_t *data; - - if (key_data_length != sizeof(*data)) { - status = PSA_ERROR_DATA_INVALID; - goto exit; - } - data = (psa_se_key_data_storage_t *) key_data; - status = psa_copy_key_material_into_slot( - slot, data->slot_number, sizeof(data->slot_number)); - goto exit; - } -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - if( ( status = psa_copy_key_material_into_slot( slot, key_data, - key_data_length ) ) != PSA_SUCCESS ) - { - goto exit; - } - -exit: - psa_free_persistent_key_data( key_data, key_data_length ); - if( status == PSA_SUCCESS ) - status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); - return( status ); -} -#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ - -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) - -static psa_status_t psa_load_builtin_key_into_slot(psa_key_slot_t *slot) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_key_lifetime_t lifetime = PSA_KEY_LIFETIME_VOLATILE; - psa_drv_slot_number_t slot_number = 0; - size_t key_buffer_size = 0; - size_t key_buffer_length = 0; - - if (!psa_key_id_is_builtin( - MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id))) { - return PSA_ERROR_DOES_NOT_EXIST; - } - - /* Check the platform function to see whether this key actually exists */ - status = mbedtls_psa_platform_get_builtin_key( - slot->attr.id, &lifetime, &slot_number); - if (status != PSA_SUCCESS) { - return status; - } - - /* Set required key attributes to ensure get_builtin_key can retrieve the - * full attributes. */ - psa_set_key_id(&attributes, slot->attr.id); - psa_set_key_lifetime(&attributes, lifetime); - - /* Get the full key attributes from the driver in order to be able to - * calculate the required buffer size. */ - status = psa_driver_wrapper_get_builtin_key( - slot_number, &attributes, - NULL, 0, NULL); - if (status != PSA_ERROR_BUFFER_TOO_SMALL) { - /* Builtin keys cannot be defined by the attributes alone */ - if (status == PSA_SUCCESS) { - status = PSA_ERROR_CORRUPTION_DETECTED; - } - return status; - } - - /* If the key should exist according to the platform, then ask the driver - * what its expected size is. */ - status = psa_driver_wrapper_get_key_buffer_size(&attributes, - &key_buffer_size); - if (status != PSA_SUCCESS) { - return status; - } - - /* Allocate a buffer of the required size and load the builtin key directly - * into the (now properly sized) slot buffer. */ - status = psa_allocate_buffer_to_slot(slot, key_buffer_size); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_driver_wrapper_get_builtin_key( - slot_number, &attributes, - slot->key.data, slot->key.bytes, &key_buffer_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - /* Copy actual key length and core attributes into the slot on success */ - slot->key.bytes = key_buffer_length; - slot->attr = attributes.core; - - status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); -exit: - if (status != PSA_SUCCESS) { - psa_remove_key_data_from_memory(slot); - } - return status; -} -#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - -psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, - psa_key_slot_t **p_slot, - psa_slot_locking_intent_t intent ) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - - *p_slot = NULL; - if( !global_data.key_slots_initialized ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_ERROR_BAD_STATE ); - } - - /* - * On success, the pointer to the slot is passed directly to the caller - * thus no need to unlock the key slot here. - */ - if( ( status = psa_get_key_slot( key, p_slot ) ) == PSA_SUCCESS ) - { - if( intent == PSA_INTENT_READ ) - status = psa_slot_add_reader( *p_slot ); - else if( intent == PSA_INTENT_DESTROY ) - status = psa_slot_change_state( *p_slot, PSA_STATE_DESTROYING ); - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - } - if( status != PSA_ERROR_DOES_NOT_EXIST ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - /* Loading keys from storage requires support for such a mechanism */ -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || \ - defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) - psa_key_id_t volatile_key_id; - - status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - (*p_slot)->attr.id = key; - (*p_slot)->attr.lifetime = PSA_KEY_LIFETIME_PERSISTENT; - - status = PSA_ERROR_DOES_NOT_EXIST; -#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) - /* Load keys in the 'builtin' range through their own interface */ - status = psa_load_builtin_key_into_slot(*p_slot); -#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if (status == PSA_ERROR_DOES_NOT_EXIST) { - status = psa_load_persistent_key_into_slot(*p_slot); - } -#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ - - if( status != PSA_SUCCESS ) - { - (void) psa_slot_change_state( *p_slot, PSA_STATE_WIPING ); - (void) psa_wipe_key_slot( *p_slot ); - if( status == PSA_ERROR_DOES_NOT_EXIST ) - status = PSA_ERROR_INVALID_HANDLE; - } - else - { - /* Add implicit usage flags. */ - psa_extend_key_usage_flags( &(*p_slot)->attr.policy.usage ); - if( intent == PSA_INTENT_READ ) - status = psa_slot_add_reader( *p_slot ); - else if( intent == PSA_INTENT_DESTROY ) - status = psa_slot_change_state( *p_slot, PSA_STATE_DESTROYING ); - } - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); -#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_ERROR_INVALID_HANDLE ); -#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ -} - -psa_status_t psa_unlock_key_slot(psa_key_slot_t *slot) -{ - psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; - if( slot == NULL ) - return( PSA_SUCCESS ); - - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - - if( slot->state != PSA_STATE_READING && - slot->state != PSA_STATE_DESTROYING && - slot->state != PSA_STATE_WIPING ) - { - MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->state != PSA_STATE_READING && - slot->state != PSA_STATE_DESTROYING && - slot->state != PSA_STATE_WIPING ); - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_ERROR_BAD_STATE ); - } - - if( slot->reader_count == 0 ) - { - MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->reader_count != 0 ); - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( PSA_ERROR_CORRUPTION_DETECTED ); - } - slot->reader_count--; - status = PSA_SUCCESS; - - if( psa_slot_has_no_readers( slot ) ) - { - if( slot->state == PSA_STATE_DESTROYING ) - status = psa_finish_key_destruction( slot ); - else if ( slot->state == PSA_STATE_WIPING ) - status = psa_wipe_key_slot( slot ); - else - status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); - } - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); -} - -psa_status_t psa_validate_key_location(psa_key_lifetime_t lifetime, - psa_se_drv_table_entry_t **p_drv) -{ - if (psa_key_lifetime_is_external(lifetime)) { -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - /* Check whether a driver is registered against this lifetime */ - psa_se_drv_table_entry_t *driver = psa_get_se_driver_entry(lifetime); - if (driver != NULL) { - if (p_drv != NULL) { - *p_drv = driver; - } - return PSA_SUCCESS; - } -#else /* MBEDTLS_PSA_CRYPTO_SE_C */ - (void) p_drv; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - - /* Key location for external keys gets checked by the wrapper */ - return PSA_SUCCESS; - } else { - /* Local/internal keys are always valid */ - return PSA_SUCCESS; - } -} - -psa_status_t psa_validate_key_persistence(psa_key_lifetime_t lifetime) -{ - if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { - /* Volatile keys are always supported */ - return PSA_SUCCESS; - } else { - /* Persistent keys require storage support */ -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if (PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime)) { - return PSA_ERROR_INVALID_ARGUMENT; - } else { - return PSA_SUCCESS; - } -#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ - return PSA_ERROR_NOT_SUPPORTED; -#endif /* !MBEDTLS_PSA_CRYPTO_STORAGE_C */ - } -} - -psa_status_t psa_open_key(mbedtls_svc_key_id_t key, psa_key_handle_t *handle) -{ -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || \ - defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) - psa_status_t status; - psa_key_slot_t *slot; - - status = psa_get_and_lock_key_slot( key, &slot, PSA_INTENT_OPEN ); - if( status != PSA_SUCCESS ) - { - *handle = PSA_KEY_HANDLE_INIT; - if (status == PSA_ERROR_INVALID_HANDLE) { - status = PSA_ERROR_DOES_NOT_EXIST; - } - - return status; - } - - *handle = key; - - return( status ); - -#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ - (void) key; - *handle = PSA_KEY_HANDLE_INIT; - return PSA_ERROR_NOT_SUPPORTED; -#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ -} - -psa_status_t psa_close_key(psa_key_handle_t handle) -{ - psa_status_t status; - psa_key_slot_t *slot; - - if (psa_key_handle_is_null(handle)) { - return PSA_SUCCESS; - } - - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - status = psa_get_key_slot( handle, &slot ); - if( status != PSA_SUCCESS ) - { - if( status == PSA_ERROR_DOES_NOT_EXIST ) - status = PSA_ERROR_INVALID_HANDLE; - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - status = psa_slot_change_state( slot, PSA_STATE_WIPING ); - - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - if( psa_slot_has_no_readers(slot) ) - status = psa_wipe_key_slot( slot ); - else - status = PSA_ERROR_DELAYED; - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); -} - -psa_status_t psa_purge_key(mbedtls_svc_key_id_t key) -{ - psa_status_t status; - psa_key_slot_t *slot; - - if( psa_key_id_is_volatile( MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ) ) ) - return( PSA_SUCCESS ); - - MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); - status = psa_get_key_slot( key, &slot ); - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - status = psa_slot_change_state( slot, PSA_STATE_WIPING ); - - if( status != PSA_SUCCESS ) - { - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); - } - - if( psa_slot_has_no_readers(slot) ) - status = psa_wipe_key_slot( slot ); - else - status = PSA_ERROR_DELAYED; - - MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); - return( status ); -} - -void mbedtls_psa_get_stats(mbedtls_psa_stats_t *stats) -{ - size_t slot_idx; - - memset(stats, 0, sizeof(*stats)); - - for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) - { - const psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; - if( slot->state != PSA_STATE_EMPTY ) - { - ++stats->locked_slots; - } - if( slot->state == PSA_STATE_EMPTY ) - { - ++stats->empty_slots; - continue; - } - if (PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { - ++stats->volatile_slots; - } else { - psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id); - ++stats->persistent_slots; - if (id > stats->max_open_internal_key_id) { - stats->max_open_internal_key_id = id; - } - } - if (PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime) != - PSA_KEY_LOCATION_LOCAL_STORAGE) { - psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id); - ++stats->external_slots; - if (id > stats->max_open_external_key_id) { - stats->max_open_external_key_id = id; - } - } - } -} - -#if defined(MBEDTLS_TEST_HOOKS) -psa_key_slot_t* mbedtls_psa_get_key_slot( uint32_t num ) -{ - if( num >= MBEDTLS_PSA_KEY_SLOT_COUNT ) - return( NULL ); - return( &global_data.key_slots[num] ); -} -#endif /* MBEDTLS_TEST_HOOKS */ - -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA crypto layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include "psa/crypto.h" + +#include "psa_crypto_core.h" +#include "psa_crypto_driver_wrappers_no_static.h" +#include "psa_crypto_slot_management.h" +#include "psa_crypto_storage.h" +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +#include "psa_crypto_se.h" +#endif + +#include +#include +#include "mbedtls/threading.h" +#include "mbedtls/platform.h" + +typedef struct { + psa_key_slot_t key_slots[MBEDTLS_PSA_KEY_SLOT_COUNT]; + uint8_t key_slots_initialized; +} psa_global_data_t; + +static psa_global_data_t global_data; + +int psa_is_valid_key_id(mbedtls_svc_key_id_t key, int vendor_ok) +{ + psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); + + if ((PSA_KEY_ID_USER_MIN <= key_id) && + (key_id <= PSA_KEY_ID_USER_MAX)) { + return 1; + } + + if (vendor_ok && + (PSA_KEY_ID_VENDOR_MIN <= key_id) && + (key_id <= PSA_KEY_ID_VENDOR_MAX)) { + return 1; + } + + return 0; +} + +psa_status_t psa_slot_change_state( psa_key_slot_t *slot, + psa_key_slot_state_t target_state ) +{ + switch( slot->state ) + { + case PSA_STATE_EMPTY: + if( target_state != PSA_STATE_CREATING && + target_state != PSA_STATE_UNUSED && + target_state != PSA_STATE_WIPING ) + return( PSA_ERROR_INVALID_HANDLE ); + break; + case PSA_STATE_CREATING: + if( target_state != PSA_STATE_UNUSED && + target_state != PSA_STATE_DESTROYING && + target_state != PSA_STATE_WIPING ) + return( PSA_ERROR_BAD_STATE ); + break; + case PSA_STATE_UNUSED: + if( target_state != PSA_STATE_READING && + target_state != PSA_STATE_DESTROYING && + target_state != PSA_STATE_WIPING ) + return( PSA_ERROR_BAD_STATE ); + break; + case PSA_STATE_READING: + if( target_state != PSA_STATE_UNUSED && + target_state != PSA_STATE_DESTROYING && + target_state != PSA_STATE_WIPING && + target_state != PSA_STATE_READING ) + return( PSA_ERROR_BAD_STATE ); + if( target_state == PSA_STATE_UNUSED && + slot->reader_count > 0 ) + return( PSA_ERROR_BAD_STATE ); + break; + case PSA_STATE_DESTROYING: + if( target_state != PSA_STATE_EMPTY ) + return( PSA_ERROR_BAD_STATE ); + break; + case PSA_STATE_WIPING : + if( target_state != PSA_STATE_DESTROYING && + target_state != PSA_STATE_EMPTY ) + return( PSA_ERROR_BAD_STATE ); + break; + } + slot->state = target_state; + return( PSA_SUCCESS ); +} + +int psa_slot_has_no_readers( psa_key_slot_t *slot ) +{ + if( slot->reader_count == 0 ) + return( 1 ); + + return( 0 ); +} + +static psa_status_t psa_slot_add_reader( psa_key_slot_t *slot ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_slot_change_state( slot, PSA_STATE_READING ); + if( status != PSA_SUCCESS ) + return( status ); + + if( slot->reader_count >= SIZE_MAX ) + return( PSA_ERROR_CORRUPTION_DETECTED ); + + slot->reader_count++; + + return( PSA_SUCCESS ); +} + +/** Get the description in memory of a key given its identifier. + * + * The descriptions of volatile keys and loaded persistent keys are + * stored in key slots. This function returns a pointer to the key slot + * containing the description of a key given its identifier. + * + * The function searches the key slots containing the description of the key + * with \p key identifier. The function does only read accesses to the key + * slots. The function does not load any persistent key thus does not access + * any storage. + * + * For volatile key identifiers, only one key slot is queried as a volatile + * key with identifier key_id can only be stored in slot of index + * ( key_id - #PSA_KEY_ID_VOLATILE_MIN ). + * + * Please note that, if MBEDTLS_THREADING_C is enabled, this function should + * be called with locked mbedtls_psa_slots_mutex. + * + * \param key Key identifier to query. + * \param[out] p_slot On success, `*p_slot` contains a pointer to the + * key slot containing the description of the key + * identified by \p key. + * + * \retval #PSA_SUCCESS + * The pointer to the key slot containing the description of the key + * identified by \p key was returned. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p key is not a valid key identifier. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no key with key identifier \p key in the key slots. + */ +static psa_status_t psa_get_key_slot( + mbedtls_svc_key_id_t key, psa_key_slot_t **p_slot ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); + size_t slot_idx; + psa_key_slot_t *slot = NULL; + + if (psa_key_id_is_volatile(key_id)) { + slot = &global_data.key_slots[key_id - PSA_KEY_ID_VOLATILE_MIN]; + + /* + * Check if both the PSA key identifier key_id and the owner + * identifier of key match those of the key slot. + * + * Note that, if the key slot is not occupied, its PSA key identifier + * is equal to zero. This is an invalid value for a PSA key identifier + * and thus cannot be equal to the valid PSA key identifier key_id. + */ + status = mbedtls_svc_key_id_equal(key, slot->attr.id) ? + PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; + } else { + if (!psa_is_valid_key_id(key, 1)) { + return PSA_ERROR_INVALID_HANDLE; + } + + for (slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++) { + slot = &global_data.key_slots[slot_idx]; + if (mbedtls_svc_key_id_equal(key, slot->attr.id)) { + break; + } + } + status = (slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT) ? + PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; + } + + if( status != PSA_SUCCESS ) + return( status ); + else + *p_slot = slot; + + return( status ); +} + +psa_status_t psa_initialize_key_slots(void) +{ + /* Nothing to do: program startup and psa_wipe_all_key_slots() both + * guarantee that the key slots are initialized to all-zero, which + * means that all the key slots are in a valid, empty state. */ + global_data.key_slots_initialized = 1; + return PSA_SUCCESS; +} + +void psa_wipe_all_key_slots(void) +{ + size_t slot_idx; + +#if defined(MBEDTLS_THREADING_C) + (void) mbedtls_mutex_lock( &mbedtls_psa_slots_mutex ); +#endif + + for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) + { + psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + (void) psa_slot_change_state( slot, PSA_STATE_WIPING ); + (void) psa_wipe_key_slot( slot ); + } + global_data.key_slots_initialized = 0; +#if defined(MBEDTLS_THREADING_C) + (void) mbedtls_mutex_unlock( &mbedtls_psa_slots_mutex ); +#endif +} + +psa_status_t psa_get_empty_key_slot(psa_key_id_t *volatile_key_id, + psa_key_slot_t **p_slot) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t slot_idx; + psa_key_slot_t *selected_slot, *unlocked_persistent_key_slot; + if( ! global_data.key_slots_initialized ) + { + status = PSA_ERROR_BAD_STATE; + goto error; + } + + selected_slot = unlocked_persistent_key_slot = NULL; + for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) + { + psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + if( slot->state == PSA_STATE_EMPTY ) + { + selected_slot = slot; + break; + } + + if( ( unlocked_persistent_key_slot == NULL ) && + ( ! PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) && + ( slot->state == PSA_STATE_UNUSED ) ) + unlocked_persistent_key_slot = slot; + } + + /* + * If there is no unused key slot and there is at least one unlocked key + * slot containing the description of a persistent key, recycle the first + * such key slot we encountered. If we later need to operate on the + * persistent key we are evicting now, we will reload its description from + * storage. + */ + if( ( selected_slot == NULL ) && ( unlocked_persistent_key_slot != NULL ) ) + { + selected_slot = unlocked_persistent_key_slot; + status = psa_slot_change_state( selected_slot, PSA_STATE_WIPING ); + if( status != PSA_SUCCESS ) + return( status ); + + psa_wipe_key_slot( selected_slot ); + } + + if( selected_slot != NULL ) + { + *volatile_key_id = PSA_KEY_ID_VOLATILE_MIN + + ((psa_key_id_t) (selected_slot - global_data.key_slots)); + *p_slot = selected_slot; + + return PSA_SUCCESS; + } + status = PSA_ERROR_INSUFFICIENT_MEMORY; + +error: + *p_slot = NULL; + *volatile_key_id = 0; + + return status; +} + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) +static psa_status_t psa_load_persistent_key_into_slot(psa_key_slot_t *slot) +{ + psa_status_t status = PSA_SUCCESS; + uint8_t *key_data = NULL; + size_t key_data_length = 0; + + status = psa_load_persistent_key(&slot->attr, + &key_data, &key_data_length); + if (status != PSA_SUCCESS) { + goto exit; + } + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* Special handling is required for loading keys associated with a + * dynamically registered SE interface. */ + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + if (psa_get_se_driver(slot->attr.lifetime, &drv, &drv_context)) { + psa_se_key_data_storage_t *data; + + if (key_data_length != sizeof(*data)) { + status = PSA_ERROR_DATA_INVALID; + goto exit; + } + data = (psa_se_key_data_storage_t *) key_data; + status = psa_copy_key_material_into_slot( + slot, data->slot_number, sizeof(data->slot_number)); + goto exit; + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + if( ( status = psa_copy_key_material_into_slot( slot, key_data, + key_data_length ) ) != PSA_SUCCESS ) + { + goto exit; + } + +exit: + psa_free_persistent_key_data( key_data, key_data_length ); + if( status == PSA_SUCCESS ) + status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); + return( status ); +} +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ + +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + +static psa_status_t psa_load_builtin_key_into_slot(psa_key_slot_t *slot) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; + psa_key_lifetime_t lifetime = PSA_KEY_LIFETIME_VOLATILE; + psa_drv_slot_number_t slot_number = 0; + size_t key_buffer_size = 0; + size_t key_buffer_length = 0; + + if (!psa_key_id_is_builtin( + MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id))) { + return PSA_ERROR_DOES_NOT_EXIST; + } + + /* Check the platform function to see whether this key actually exists */ + status = mbedtls_psa_platform_get_builtin_key( + slot->attr.id, &lifetime, &slot_number); + if (status != PSA_SUCCESS) { + return status; + } + + /* Set required key attributes to ensure get_builtin_key can retrieve the + * full attributes. */ + psa_set_key_id(&attributes, slot->attr.id); + psa_set_key_lifetime(&attributes, lifetime); + + /* Get the full key attributes from the driver in order to be able to + * calculate the required buffer size. */ + status = psa_driver_wrapper_get_builtin_key( + slot_number, &attributes, + NULL, 0, NULL); + if (status != PSA_ERROR_BUFFER_TOO_SMALL) { + /* Builtin keys cannot be defined by the attributes alone */ + if (status == PSA_SUCCESS) { + status = PSA_ERROR_CORRUPTION_DETECTED; + } + return status; + } + + /* If the key should exist according to the platform, then ask the driver + * what its expected size is. */ + status = psa_driver_wrapper_get_key_buffer_size(&attributes, + &key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } + + /* Allocate a buffer of the required size and load the builtin key directly + * into the (now properly sized) slot buffer. */ + status = psa_allocate_buffer_to_slot(slot, key_buffer_size); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_driver_wrapper_get_builtin_key( + slot_number, &attributes, + slot->key.data, slot->key.bytes, &key_buffer_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + /* Copy actual key length and core attributes into the slot on success */ + slot->key.bytes = key_buffer_length; + slot->attr = attributes.core; + + status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); +exit: + if (status != PSA_SUCCESS) { + psa_remove_key_data_from_memory(slot); + } + return status; +} +#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + +psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_slot_locking_intent_t intent ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + + *p_slot = NULL; + if( !global_data.key_slots_initialized ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_ERROR_BAD_STATE ); + } + + /* + * On success, the pointer to the slot is passed directly to the caller + * thus no need to unlock the key slot here. + */ + if( ( status = psa_get_key_slot( key, p_slot ) ) == PSA_SUCCESS ) + { + if( intent == PSA_INTENT_READ ) + status = psa_slot_add_reader( *p_slot ); + else if( intent == PSA_INTENT_DESTROY ) + status = psa_slot_change_state( *p_slot, PSA_STATE_DESTROYING ); + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + } + if( status != PSA_ERROR_DOES_NOT_EXIST ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + /* Loading keys from storage requires support for such a mechanism */ +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || \ + defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + psa_key_id_t volatile_key_id; + + status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + (*p_slot)->attr.id = key; + (*p_slot)->attr.lifetime = PSA_KEY_LIFETIME_PERSISTENT; + + status = PSA_ERROR_DOES_NOT_EXIST; +#if defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + /* Load keys in the 'builtin' range through their own interface */ + status = psa_load_builtin_key_into_slot(*p_slot); +#endif /* MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + if (status == PSA_ERROR_DOES_NOT_EXIST) { + status = psa_load_persistent_key_into_slot(*p_slot); + } +#endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ + + if( status != PSA_SUCCESS ) + { + (void) psa_slot_change_state( *p_slot, PSA_STATE_WIPING ); + (void) psa_wipe_key_slot( *p_slot ); + if( status == PSA_ERROR_DOES_NOT_EXIST ) + status = PSA_ERROR_INVALID_HANDLE; + } + else + { + /* Add implicit usage flags. */ + psa_extend_key_usage_flags( &(*p_slot)->attr.policy.usage ); + if( intent == PSA_INTENT_READ ) + status = psa_slot_add_reader( *p_slot ); + else if( intent == PSA_INTENT_DESTROY ) + status = psa_slot_change_state( *p_slot, PSA_STATE_DESTROYING ); + } + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); +#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_ERROR_INVALID_HANDLE ); +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ +} + +psa_status_t psa_unlock_key_slot(psa_key_slot_t *slot) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + if( slot == NULL ) + return( PSA_SUCCESS ); + + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + + if( slot->state != PSA_STATE_READING && + slot->state != PSA_STATE_DESTROYING && + slot->state != PSA_STATE_WIPING ) + { + MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->state != PSA_STATE_READING && + slot->state != PSA_STATE_DESTROYING && + slot->state != PSA_STATE_WIPING ); + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_ERROR_BAD_STATE ); + } + + if( slot->reader_count == 0 ) + { + MBEDTLS_TEST_HOOK_TEST_ASSERT( slot->reader_count != 0 ); + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( PSA_ERROR_CORRUPTION_DETECTED ); + } + slot->reader_count--; + status = PSA_SUCCESS; + + if( psa_slot_has_no_readers( slot ) ) + { + if( slot->state == PSA_STATE_DESTROYING ) + status = psa_finish_key_destruction( slot ); + else if ( slot->state == PSA_STATE_WIPING ) + status = psa_wipe_key_slot( slot ); + else + status = psa_slot_change_state( slot, PSA_STATE_UNUSED ); + } + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); +} + +psa_status_t psa_validate_key_location(psa_key_lifetime_t lifetime, + psa_se_drv_table_entry_t **p_drv) +{ + if (psa_key_lifetime_is_external(lifetime)) { +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + /* Check whether a driver is registered against this lifetime */ + psa_se_drv_table_entry_t *driver = psa_get_se_driver_entry(lifetime); + if (driver != NULL) { + if (p_drv != NULL) { + *p_drv = driver; + } + return PSA_SUCCESS; + } +#else /* MBEDTLS_PSA_CRYPTO_SE_C */ + (void) p_drv; +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + /* Key location for external keys gets checked by the wrapper */ + return PSA_SUCCESS; + } else { + /* Local/internal keys are always valid */ + return PSA_SUCCESS; + } +} + +psa_status_t psa_validate_key_persistence(psa_key_lifetime_t lifetime) +{ + if (PSA_KEY_LIFETIME_IS_VOLATILE(lifetime)) { + /* Volatile keys are always supported */ + return PSA_SUCCESS; + } else { + /* Persistent keys require storage support */ +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + if (PSA_KEY_LIFETIME_IS_READ_ONLY(lifetime)) { + return PSA_ERROR_INVALID_ARGUMENT; + } else { + return PSA_SUCCESS; + } +#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ + return PSA_ERROR_NOT_SUPPORTED; +#endif /* !MBEDTLS_PSA_CRYPTO_STORAGE_C */ + } +} + +psa_status_t psa_open_key(mbedtls_svc_key_id_t key, psa_key_handle_t *handle) +{ +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) || \ + defined(MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS) + psa_status_t status; + psa_key_slot_t *slot; + + status = psa_get_and_lock_key_slot( key, &slot, PSA_INTENT_OPEN ); + if( status != PSA_SUCCESS ) + { + *handle = PSA_KEY_HANDLE_INIT; + if (status == PSA_ERROR_INVALID_HANDLE) { + status = PSA_ERROR_DOES_NOT_EXIST; + } + + return status; + } + + *handle = key; + + return( status ); + +#else /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ + (void) key; + *handle = PSA_KEY_HANDLE_INIT; + return PSA_ERROR_NOT_SUPPORTED; +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C || MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS */ +} + +psa_status_t psa_close_key(psa_key_handle_t handle) +{ + psa_status_t status; + psa_key_slot_t *slot; + + if (psa_key_handle_is_null(handle)) { + return PSA_SUCCESS; + } + + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + status = psa_get_key_slot( handle, &slot ); + if( status != PSA_SUCCESS ) + { + if( status == PSA_ERROR_DOES_NOT_EXIST ) + status = PSA_ERROR_INVALID_HANDLE; + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + status = psa_slot_change_state( slot, PSA_STATE_WIPING ); + + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + if( psa_slot_has_no_readers(slot) ) + status = psa_wipe_key_slot( slot ); + else + status = PSA_ERROR_DELAYED; + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); +} + +psa_status_t psa_purge_key(mbedtls_svc_key_id_t key) +{ + psa_status_t status; + psa_key_slot_t *slot; + + if( psa_key_id_is_volatile( MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ) ) ) + return( PSA_SUCCESS ); + + MBEDTLS_MUTEX_LOCK_CHECK( &mbedtls_psa_slots_mutex ); + status = psa_get_key_slot( key, &slot ); + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + status = psa_slot_change_state( slot, PSA_STATE_WIPING ); + + if( status != PSA_SUCCESS ) + { + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); + } + + if( psa_slot_has_no_readers(slot) ) + status = psa_wipe_key_slot( slot ); + else + status = PSA_ERROR_DELAYED; + + MBEDTLS_MUTEX_UNLOCK_CHECK( &mbedtls_psa_slots_mutex ); + return( status ); +} + +void mbedtls_psa_get_stats(mbedtls_psa_stats_t *stats) +{ + size_t slot_idx; + + memset(stats, 0, sizeof(*stats)); + + for( slot_idx = 0; slot_idx < MBEDTLS_PSA_KEY_SLOT_COUNT; slot_idx++ ) + { + const psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + if( slot->state != PSA_STATE_EMPTY ) + { + ++stats->locked_slots; + } + if( slot->state == PSA_STATE_EMPTY ) + { + ++stats->empty_slots; + continue; + } + if (PSA_KEY_LIFETIME_IS_VOLATILE(slot->attr.lifetime)) { + ++stats->volatile_slots; + } else { + psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id); + ++stats->persistent_slots; + if (id > stats->max_open_internal_key_id) { + stats->max_open_internal_key_id = id; + } + } + if (PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime) != + PSA_KEY_LOCATION_LOCAL_STORAGE) { + psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID(slot->attr.id); + ++stats->external_slots; + if (id > stats->max_open_external_key_id) { + stats->max_open_external_key_id = id; + } + } + } +} + +#if defined(MBEDTLS_TEST_HOOKS) +psa_key_slot_t* mbedtls_psa_get_key_slot( uint32_t num ) +{ + if( num >= MBEDTLS_PSA_KEY_SLOT_COUNT ) + return( NULL ); + return( &global_data.key_slots[num] ); +} +#endif /* MBEDTLS_TEST_HOOKS */ + +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.h index 6da0eb8..b8632d7 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_slot_management.h @@ -1,211 +1,211 @@ -/* - * PSA crypto layer on top of Mbed TLS crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_SLOT_MANAGEMENT_H -#define PSA_CRYPTO_SLOT_MANAGEMENT_H - -#include "psa/crypto.h" -#include "psa_crypto_core.h" -#include "psa_crypto_se.h" - -/** Range of volatile key identifiers. - * - * The last #MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of the implementation - * range of key identifiers are reserved for volatile key identifiers. - * A volatile key identifier is equal to #PSA_KEY_ID_VOLATILE_MIN plus the - * index of the key slot containing the volatile key definition. - */ - -/** The minimum value for a volatile key identifier. - */ -#define PSA_KEY_ID_VOLATILE_MIN (PSA_KEY_ID_VENDOR_MAX - \ - MBEDTLS_PSA_KEY_SLOT_COUNT + 1) - -/** The maximum value for a volatile key identifier. - */ -#define PSA_KEY_ID_VOLATILE_MAX PSA_KEY_ID_VENDOR_MAX - -/** Test whether a key identifier is a volatile key identifier. - * - * \param key_id Key identifier to test. - * - * \retval 1 - * The key identifier is a volatile key identifier. - * \retval 0 - * The key identifier is not a volatile key identifier. - */ -static inline int psa_key_id_is_volatile(psa_key_id_t key_id) -{ - return (key_id >= PSA_KEY_ID_VOLATILE_MIN) && - (key_id <= PSA_KEY_ID_VOLATILE_MAX); -} - -/** Get the description of a key given its identifier and lock it. - * - * The descriptions of volatile keys and loaded persistent keys are stored in - * key slots. This function returns a pointer to the key slot containing the - * description of a key given its identifier. - * - * In case of a persistent key, the function loads the description of the key - * into a key slot if not already done. - * - * On success, the returned key slot is locked. It is the responsibility of - * the caller to unlock the key slot when it does not access it anymore. - * - * \param key Key identifier to query. - * \param[out] p_slot On success, `*p_slot` contains a pointer to the - * key slot containing the description of the key - * identified by \p key. - * \param[in] intent Reason for locking the key. - * \retval #PSA_SUCCESS - * \p *p_slot contains a pointer to the key slot containing the - * description of the key identified by \p key. - * The key slot counter has been incremented. - * \retval #PSA_ERROR_BAD_STATE - * The library has not been initialized. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p key is not a valid key identifier. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * \p key is a persistent key identifier. The implementation does not - * have sufficient resources to load the persistent key. This can be - * due to a lack of empty key slot, or available memory. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no key with key identifier \p key. - * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, - psa_key_slot_t **p_slot, - psa_slot_locking_intent_t intent ); - -/** Initialize the key slot structures. - * - * \retval #PSA_SUCCESS - * Currently this function always succeeds. - */ -psa_status_t psa_initialize_key_slots(void); - -/** Delete all data from key slots in memory. - * - * This does not affect persistent storage. */ -void psa_wipe_all_key_slots(void); - -/** Find a free key slot. - * - * This function returns a key slot that is available for use and is in its - * ground state (all-bits-zero). On success, the key slot is locked. It is - * the responsibility of the caller to unlock the key slot when it does not - * access it anymore. - * - * Please note that, if MBEDTLS_THREADING_C is enabled, this function should - * be called with locked mbedtls_psa_slots_mutex. - * - * \param[out] volatile_key_id On success, volatile key identifier - * associated to the returned slot. - * \param[out] p_slot On success, a pointer to the slot. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_BAD_STATE \emptydescription - */ -psa_status_t psa_get_empty_key_slot(psa_key_id_t *volatile_key_id, - psa_key_slot_t **p_slot); - -/** Unlock a key slot and, if possible, perform any delayed destruction - * or purging. - * - * This function decrements the key slot lock counter by one. - * If there was a key destruction or purging requested while the key was - * still in use, and this caller is the last user of it, the delayed - * operation will be applied. - * - * \note To ease the handling of errors in retrieving a key slot - * a NULL input pointer is valid, and the function returns - * successfully without doing anything in that case. - * - * \param[in] slot The key slot. - * \retval #PSA_SUCCESS - * \p slot is NULL or the key slot lock counter has been - * decremented successfully. - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * The lock counter was equal to 0. - * \retval #PSA_ERROR_BAD_STATE - * This slot is not in a state that enables any active reader. - */ -psa_status_t psa_unlock_key_slot(psa_key_slot_t *slot); - -/** Test whether a lifetime designates a key in an external cryptoprocessor. - * - * \param lifetime The lifetime to test. - * - * \retval 1 - * The lifetime designates an external key. There should be a - * registered driver for this lifetime, otherwise the key cannot - * be created or manipulated. - * \retval 0 - * The lifetime designates a key that is volatile or in internal - * storage. - */ -static inline int psa_key_lifetime_is_external(psa_key_lifetime_t lifetime) -{ - return PSA_KEY_LIFETIME_GET_LOCATION(lifetime) - != PSA_KEY_LOCATION_LOCAL_STORAGE; -} - -/** Validate a key's location. - * - * This function checks whether the key's attributes point to a location that - * is known to the PSA Core, and returns the driver function table if the key - * is to be found in an external location. - * - * \param[in] lifetime The key lifetime attribute. - * \param[out] p_drv On success, when a key is located in external - * storage, returns a pointer to the driver table - * associated with the key's storage location. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - */ -psa_status_t psa_validate_key_location(psa_key_lifetime_t lifetime, - psa_se_drv_table_entry_t **p_drv); - -/** Validate the persistence of a key. - * - * \param[in] lifetime The key lifetime attribute. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_NOT_SUPPORTED The key is persistent but persistent keys - * are not supported. - */ -psa_status_t psa_validate_key_persistence(psa_key_lifetime_t lifetime); - -/** Validate a key identifier. - * - * \param[in] key The key identifier. - * \param[in] vendor_ok Non-zero to indicate that key identifiers in the - * vendor range are allowed, volatile key identifiers - * excepted \c 0 otherwise. - * - * \retval <> 0 if the key identifier is valid, 0 otherwise. - */ -int psa_is_valid_key_id(mbedtls_svc_key_id_t key, int vendor_ok); - -#endif /* PSA_CRYPTO_SLOT_MANAGEMENT_H */ +/* + * PSA crypto layer on top of Mbed TLS crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_SLOT_MANAGEMENT_H +#define PSA_CRYPTO_SLOT_MANAGEMENT_H + +#include "psa/crypto.h" +#include "psa_crypto_core.h" +#include "psa_crypto_se.h" + +/** Range of volatile key identifiers. + * + * The last #MBEDTLS_PSA_KEY_SLOT_COUNT identifiers of the implementation + * range of key identifiers are reserved for volatile key identifiers. + * A volatile key identifier is equal to #PSA_KEY_ID_VOLATILE_MIN plus the + * index of the key slot containing the volatile key definition. + */ + +/** The minimum value for a volatile key identifier. + */ +#define PSA_KEY_ID_VOLATILE_MIN (PSA_KEY_ID_VENDOR_MAX - \ + MBEDTLS_PSA_KEY_SLOT_COUNT + 1) + +/** The maximum value for a volatile key identifier. + */ +#define PSA_KEY_ID_VOLATILE_MAX PSA_KEY_ID_VENDOR_MAX + +/** Test whether a key identifier is a volatile key identifier. + * + * \param key_id Key identifier to test. + * + * \retval 1 + * The key identifier is a volatile key identifier. + * \retval 0 + * The key identifier is not a volatile key identifier. + */ +static inline int psa_key_id_is_volatile(psa_key_id_t key_id) +{ + return (key_id >= PSA_KEY_ID_VOLATILE_MIN) && + (key_id <= PSA_KEY_ID_VOLATILE_MAX); +} + +/** Get the description of a key given its identifier and lock it. + * + * The descriptions of volatile keys and loaded persistent keys are stored in + * key slots. This function returns a pointer to the key slot containing the + * description of a key given its identifier. + * + * In case of a persistent key, the function loads the description of the key + * into a key slot if not already done. + * + * On success, the returned key slot is locked. It is the responsibility of + * the caller to unlock the key slot when it does not access it anymore. + * + * \param key Key identifier to query. + * \param[out] p_slot On success, `*p_slot` contains a pointer to the + * key slot containing the description of the key + * identified by \p key. + * \param[in] intent Reason for locking the key. + * \retval #PSA_SUCCESS + * \p *p_slot contains a pointer to the key slot containing the + * description of the key identified by \p key. + * The key slot counter has been incremented. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been initialized. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p key is not a valid key identifier. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \p key is a persistent key identifier. The implementation does not + * have sufficient resources to load the persistent key. This can be + * due to a lack of empty key slot, or available memory. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no key with key identifier \p key. + * \retval #PSA_ERROR_CORRUPTION_DETECTED \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + */ +psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_slot_locking_intent_t intent ); + +/** Initialize the key slot structures. + * + * \retval #PSA_SUCCESS + * Currently this function always succeeds. + */ +psa_status_t psa_initialize_key_slots(void); + +/** Delete all data from key slots in memory. + * + * This does not affect persistent storage. */ +void psa_wipe_all_key_slots(void); + +/** Find a free key slot. + * + * This function returns a key slot that is available for use and is in its + * ground state (all-bits-zero). On success, the key slot is locked. It is + * the responsibility of the caller to unlock the key slot when it does not + * access it anymore. + * + * Please note that, if MBEDTLS_THREADING_C is enabled, this function should + * be called with locked mbedtls_psa_slots_mutex. + * + * \param[out] volatile_key_id On success, volatile key identifier + * associated to the returned slot. + * \param[out] p_slot On success, a pointer to the slot. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_BAD_STATE \emptydescription + */ +psa_status_t psa_get_empty_key_slot(psa_key_id_t *volatile_key_id, + psa_key_slot_t **p_slot); + +/** Unlock a key slot and, if possible, perform any delayed destruction + * or purging. + * + * This function decrements the key slot lock counter by one. + * If there was a key destruction or purging requested while the key was + * still in use, and this caller is the last user of it, the delayed + * operation will be applied. + * + * \note To ease the handling of errors in retrieving a key slot + * a NULL input pointer is valid, and the function returns + * successfully without doing anything in that case. + * + * \param[in] slot The key slot. + * \retval #PSA_SUCCESS + * \p slot is NULL or the key slot lock counter has been + * decremented successfully. + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * The lock counter was equal to 0. + * \retval #PSA_ERROR_BAD_STATE + * This slot is not in a state that enables any active reader. + */ +psa_status_t psa_unlock_key_slot(psa_key_slot_t *slot); + +/** Test whether a lifetime designates a key in an external cryptoprocessor. + * + * \param lifetime The lifetime to test. + * + * \retval 1 + * The lifetime designates an external key. There should be a + * registered driver for this lifetime, otherwise the key cannot + * be created or manipulated. + * \retval 0 + * The lifetime designates a key that is volatile or in internal + * storage. + */ +static inline int psa_key_lifetime_is_external(psa_key_lifetime_t lifetime) +{ + return PSA_KEY_LIFETIME_GET_LOCATION(lifetime) + != PSA_KEY_LOCATION_LOCAL_STORAGE; +} + +/** Validate a key's location. + * + * This function checks whether the key's attributes point to a location that + * is known to the PSA Core, and returns the driver function table if the key + * is to be found in an external location. + * + * \param[in] lifetime The key lifetime attribute. + * \param[out] p_drv On success, when a key is located in external + * storage, returns a pointer to the driver table + * associated with the key's storage location. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + */ +psa_status_t psa_validate_key_location(psa_key_lifetime_t lifetime, + psa_se_drv_table_entry_t **p_drv); + +/** Validate the persistence of a key. + * + * \param[in] lifetime The key lifetime attribute. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_NOT_SUPPORTED The key is persistent but persistent keys + * are not supported. + */ +psa_status_t psa_validate_key_persistence(psa_key_lifetime_t lifetime); + +/** Validate a key identifier. + * + * \param[in] key The key identifier. + * \param[in] vendor_ok Non-zero to indicate that key identifiers in the + * vendor range are allowed, volatile key identifiers + * excepted \c 0 otherwise. + * + * \retval <> 0 if the key identifier is valid, 0 otherwise. + */ +int psa_is_valid_key_id(mbedtls_svc_key_id_t key, int vendor_ok); + +#endif /* PSA_CRYPTO_SLOT_MANAGEMENT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.c index 574d4b0..fc947a6 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.c @@ -1,493 +1,493 @@ -/* - * PSA persistent key storage - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - -#include -#include - -#include "psa/crypto.h" -#include "psa_crypto_storage.h" -#include "mbedtls/platform_util.h" - -#if defined(MBEDTLS_PSA_ITS_FILE_C) -#include "psa_crypto_its.h" -#else /* Native ITS implementation */ -#include "psa/error.h" -#include "psa/internal_trusted_storage.h" -#endif - -#include "mbedtls/platform.h" - - - -/****************************************************************/ -/* Key storage */ -/****************************************************************/ - -/* Determine a file name (ITS file identifier) for the given key identifier. - * The file name must be distinct from any file that is used for a purpose - * other than storing a key. Currently, the only such file is the random seed - * file whose name is PSA_CRYPTO_ITS_RANDOM_SEED_UID and whose value is - * 0xFFFFFF52. */ -static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) -{ -#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) - /* Encode the owner in the upper 32 bits. This means that if - * owner values are nonzero (as they are on a PSA platform), - * no key file will ever have a value less than 0x100000000, so - * the whole range 0..0xffffffff is available for non-key files. */ - uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); - return ((uint64_t) unsigned_owner_id << 32) | - MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); -#else - /* Use the key id directly as a file name. - * psa_is_key_id_valid() in psa_crypto_slot_management.c - * is responsible for ensuring that key identifiers do not have a - * value that is reserved for non-key files. */ - return key; -#endif -} - -/** - * \brief Load persistent data for the given key slot number. - * - * This function reads data from a storage backend and returns the data in a - * buffer. - * - * \param key Persistent identifier of the key to be loaded. This - * should be an occupied storage location. - * \param[out] data Buffer where the data is to be written. - * \param data_size Size of the \c data buffer in bytes. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription - */ -static psa_status_t psa_crypto_storage_load( - const mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size) -{ - psa_status_t status; - psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); - struct psa_storage_info_t data_identifier_info; - size_t data_length = 0; - - status = psa_its_get_info(data_identifier, &data_identifier_info); - if (status != PSA_SUCCESS) { - return status; - } - - status = psa_its_get(data_identifier, 0, (uint32_t) data_size, data, &data_length); - if (data_size != data_length) { - return PSA_ERROR_DATA_INVALID; - } - - return status; -} - -int psa_is_key_present_in_storage(const mbedtls_svc_key_id_t key) -{ - psa_status_t ret; - psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); - struct psa_storage_info_t data_identifier_info; - - ret = psa_its_get_info(data_identifier, &data_identifier_info); - - if (ret == PSA_ERROR_DOES_NOT_EXIST) { - return 0; - } - return 1; -} - -/** - * \brief Store persistent data for the given key slot number. - * - * This function stores the given data buffer to a persistent storage. - * - * \param key Persistent identifier of the key to be stored. This - * should be an unoccupied storage location. - * \param[in] data Buffer containing the data to be stored. - * \param data_length The number of bytes - * that make up the data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -static psa_status_t psa_crypto_storage_store(const mbedtls_svc_key_id_t key, - const uint8_t *data, - size_t data_length) -{ - psa_status_t status; - psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); - struct psa_storage_info_t data_identifier_info; - - if (psa_is_key_present_in_storage(key) == 1) { - return PSA_ERROR_ALREADY_EXISTS; - } - - status = psa_its_set(data_identifier, (uint32_t) data_length, data, 0); - if (status != PSA_SUCCESS) { - return PSA_ERROR_DATA_INVALID; - } - - status = psa_its_get_info(data_identifier, &data_identifier_info); - if (status != PSA_SUCCESS) { - goto exit; - } - - if (data_identifier_info.size != data_length) { - status = PSA_ERROR_DATA_INVALID; - goto exit; - } - -exit: - if (status != PSA_SUCCESS) { - /* Remove the file in case we managed to create it but something - * went wrong. It's ok if the file doesn't exist. If the file exists - * but the removal fails, we're already reporting an error so there's - * nothing else we can do. */ - (void) psa_its_remove(data_identifier); - } - return status; -} - -psa_status_t psa_destroy_persistent_key(const mbedtls_svc_key_id_t key) -{ - psa_status_t ret; - psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); - struct psa_storage_info_t data_identifier_info; - - ret = psa_its_get_info(data_identifier, &data_identifier_info); - if (ret == PSA_ERROR_DOES_NOT_EXIST) { - return PSA_SUCCESS; - } - - if (psa_its_remove(data_identifier) != PSA_SUCCESS) { - return PSA_ERROR_DATA_INVALID; - } - - ret = psa_its_get_info(data_identifier, &data_identifier_info); - if (ret != PSA_ERROR_DOES_NOT_EXIST) { - return PSA_ERROR_DATA_INVALID; - } - - return PSA_SUCCESS; -} - -/** - * \brief Get data length for given key slot number. - * - * \param key Persistent identifier whose stored data length - * is to be obtained. - * \param[out] data_length The number of bytes that make up the data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -static psa_status_t psa_crypto_storage_get_data_length( - const mbedtls_svc_key_id_t key, - size_t *data_length) -{ - psa_status_t status; - psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); - struct psa_storage_info_t data_identifier_info; - - status = psa_its_get_info(data_identifier, &data_identifier_info); - if (status != PSA_SUCCESS) { - return status; - } - - *data_length = (size_t) data_identifier_info.size; - - return PSA_SUCCESS; -} - -/** - * Persistent key storage magic header. - */ -#define PSA_KEY_STORAGE_MAGIC_HEADER "PSA\0KEY" -#define PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH (sizeof(PSA_KEY_STORAGE_MAGIC_HEADER)) - -typedef struct { - uint8_t magic[PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH]; - uint8_t version[4]; - uint8_t lifetime[sizeof(psa_key_lifetime_t)]; - uint8_t type[2]; - uint8_t bits[2]; - uint8_t policy[sizeof(psa_key_policy_t)]; - uint8_t data_len[4]; - uint8_t key_data[]; -} psa_persistent_key_storage_format; - -void psa_format_key_data_for_storage(const uint8_t *data, - const size_t data_length, - const psa_core_key_attributes_t *attr, - uint8_t *storage_data) -{ - psa_persistent_key_storage_format *storage_format = - (psa_persistent_key_storage_format *) storage_data; - - memcpy(storage_format->magic, PSA_KEY_STORAGE_MAGIC_HEADER, - PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH); - MBEDTLS_PUT_UINT32_LE(0, storage_format->version, 0); - MBEDTLS_PUT_UINT32_LE(attr->lifetime, storage_format->lifetime, 0); - MBEDTLS_PUT_UINT16_LE((uint16_t) attr->type, storage_format->type, 0); - MBEDTLS_PUT_UINT16_LE((uint16_t) attr->bits, storage_format->bits, 0); - MBEDTLS_PUT_UINT32_LE(attr->policy.usage, storage_format->policy, 0); - MBEDTLS_PUT_UINT32_LE(attr->policy.alg, storage_format->policy, sizeof(uint32_t)); - MBEDTLS_PUT_UINT32_LE(attr->policy.alg2, storage_format->policy, 2 * sizeof(uint32_t)); - MBEDTLS_PUT_UINT32_LE(data_length, storage_format->data_len, 0); - memcpy(storage_format->key_data, data, data_length); -} - -static psa_status_t check_magic_header(const uint8_t *data) -{ - if (memcmp(data, PSA_KEY_STORAGE_MAGIC_HEADER, - PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH) != 0) { - return PSA_ERROR_DATA_INVALID; - } - return PSA_SUCCESS; -} - -psa_status_t psa_parse_key_data_from_storage(const uint8_t *storage_data, - size_t storage_data_length, - uint8_t **key_data, - size_t *key_data_length, - psa_core_key_attributes_t *attr) -{ - psa_status_t status; - const psa_persistent_key_storage_format *storage_format = - (const psa_persistent_key_storage_format *) storage_data; - uint32_t version; - - if (storage_data_length < sizeof(*storage_format)) { - return PSA_ERROR_DATA_INVALID; - } - - status = check_magic_header(storage_data); - if (status != PSA_SUCCESS) { - return status; - } - - version = MBEDTLS_GET_UINT32_LE(storage_format->version, 0); - if (version != 0) { - return PSA_ERROR_DATA_INVALID; - } - - *key_data_length = MBEDTLS_GET_UINT32_LE(storage_format->data_len, 0); - if (*key_data_length > (storage_data_length - sizeof(*storage_format)) || - *key_data_length > PSA_CRYPTO_MAX_STORAGE_SIZE) { - return PSA_ERROR_DATA_INVALID; - } - - if (*key_data_length == 0) { - *key_data = NULL; - } else { - *key_data = mbedtls_calloc(1, *key_data_length); - if (*key_data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - memcpy(*key_data, storage_format->key_data, *key_data_length); - } - - attr->lifetime = MBEDTLS_GET_UINT32_LE(storage_format->lifetime, 0); - attr->type = MBEDTLS_GET_UINT16_LE(storage_format->type, 0); - attr->bits = MBEDTLS_GET_UINT16_LE(storage_format->bits, 0); - attr->policy.usage = MBEDTLS_GET_UINT32_LE(storage_format->policy, 0); - attr->policy.alg = MBEDTLS_GET_UINT32_LE(storage_format->policy, sizeof(uint32_t)); - attr->policy.alg2 = MBEDTLS_GET_UINT32_LE(storage_format->policy, 2 * sizeof(uint32_t)); - - return PSA_SUCCESS; -} - -psa_status_t psa_save_persistent_key(const psa_core_key_attributes_t *attr, - const uint8_t *data, - const size_t data_length) -{ - size_t storage_data_length; - uint8_t *storage_data; - psa_status_t status; - - /* All keys saved to persistent storage always have a key context */ - if (data == NULL || data_length == 0) { - return PSA_ERROR_INVALID_ARGUMENT; - } - - if (data_length > PSA_CRYPTO_MAX_STORAGE_SIZE) { - return PSA_ERROR_INSUFFICIENT_STORAGE; - } - storage_data_length = data_length + sizeof(psa_persistent_key_storage_format); - - storage_data = mbedtls_calloc(1, storage_data_length); - if (storage_data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - psa_format_key_data_for_storage(data, data_length, attr, storage_data); - - status = psa_crypto_storage_store(attr->id, - storage_data, storage_data_length); - - mbedtls_zeroize_and_free(storage_data, storage_data_length); - - return status; -} - -void psa_free_persistent_key_data(uint8_t *key_data, size_t key_data_length) -{ - mbedtls_zeroize_and_free(key_data, key_data_length); -} - -psa_status_t psa_load_persistent_key(psa_core_key_attributes_t *attr, - uint8_t **data, - size_t *data_length) -{ - psa_status_t status = PSA_SUCCESS; - uint8_t *loaded_data; - size_t storage_data_length = 0; - mbedtls_svc_key_id_t key = attr->id; - - status = psa_crypto_storage_get_data_length(key, &storage_data_length); - if (status != PSA_SUCCESS) { - return status; - } - - loaded_data = mbedtls_calloc(1, storage_data_length); - - if (loaded_data == NULL) { - return PSA_ERROR_INSUFFICIENT_MEMORY; - } - - status = psa_crypto_storage_load(key, loaded_data, storage_data_length); - if (status != PSA_SUCCESS) { - goto exit; - } - - status = psa_parse_key_data_from_storage(loaded_data, storage_data_length, - data, data_length, attr); - - /* All keys saved to persistent storage always have a key context */ - if (status == PSA_SUCCESS && - (*data == NULL || *data_length == 0)) { - status = PSA_ERROR_STORAGE_FAILURE; - } - -exit: - mbedtls_zeroize_and_free(loaded_data, storage_data_length); - return status; -} - - - -/****************************************************************/ -/* Transactions */ -/****************************************************************/ - -#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) - -psa_crypto_transaction_t psa_crypto_transaction; - -psa_status_t psa_crypto_save_transaction(void) -{ - struct psa_storage_info_t p_info; - psa_status_t status; - status = psa_its_get_info(PSA_CRYPTO_ITS_TRANSACTION_UID, &p_info); - if (status == PSA_SUCCESS) { - /* This shouldn't happen: we're trying to start a transaction while - * there is still a transaction that hasn't been replayed. */ - return PSA_ERROR_CORRUPTION_DETECTED; - } else if (status != PSA_ERROR_DOES_NOT_EXIST) { - return status; - } - return psa_its_set(PSA_CRYPTO_ITS_TRANSACTION_UID, - sizeof(psa_crypto_transaction), - &psa_crypto_transaction, - 0); -} - -psa_status_t psa_crypto_load_transaction(void) -{ - psa_status_t status; - size_t length; - status = psa_its_get(PSA_CRYPTO_ITS_TRANSACTION_UID, 0, - sizeof(psa_crypto_transaction), - &psa_crypto_transaction, &length); - if (status != PSA_SUCCESS) { - return status; - } - if (length != sizeof(psa_crypto_transaction)) { - return PSA_ERROR_DATA_INVALID; - } - return PSA_SUCCESS; -} - -psa_status_t psa_crypto_stop_transaction(void) -{ - psa_status_t status = psa_its_remove(PSA_CRYPTO_ITS_TRANSACTION_UID); - /* Whether or not updating the storage succeeded, the transaction is - * finished now. It's too late to go back, so zero out the in-memory - * data. */ - memset(&psa_crypto_transaction, 0, sizeof(psa_crypto_transaction)); - return status; -} - -#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ - - - -/****************************************************************/ -/* Random generator state */ -/****************************************************************/ - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) -psa_status_t mbedtls_psa_storage_inject_entropy(const unsigned char *seed, - size_t seed_size) -{ - psa_status_t status; - struct psa_storage_info_t p_info; - - status = psa_its_get_info(PSA_CRYPTO_ITS_RANDOM_SEED_UID, &p_info); - - if (PSA_ERROR_DOES_NOT_EXIST == status) { /* No seed exists */ - status = psa_its_set(PSA_CRYPTO_ITS_RANDOM_SEED_UID, seed_size, seed, 0); - } else if (PSA_SUCCESS == status) { - /* You should not be here. Seed needs to be injected only once */ - status = PSA_ERROR_NOT_PERMITTED; - } - return status; -} -#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ - - - -/****************************************************************/ -/* The end */ -/****************************************************************/ - -#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ +/* + * PSA persistent key storage + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + +#include +#include + +#include "psa/crypto.h" +#include "psa_crypto_storage.h" +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_PSA_ITS_FILE_C) +#include "psa_crypto_its.h" +#else /* Native ITS implementation */ +#include "psa/error.h" +#include "psa/internal_trusted_storage.h" +#endif + +#include "mbedtls/platform.h" + + + +/****************************************************************/ +/* Key storage */ +/****************************************************************/ + +/* Determine a file name (ITS file identifier) for the given key identifier. + * The file name must be distinct from any file that is used for a purpose + * other than storing a key. Currently, the only such file is the random seed + * file whose name is PSA_CRYPTO_ITS_RANDOM_SEED_UID and whose value is + * 0xFFFFFF52. */ +static psa_storage_uid_t psa_its_identifier_of_slot(mbedtls_svc_key_id_t key) +{ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + /* Encode the owner in the upper 32 bits. This means that if + * owner values are nonzero (as they are on a PSA platform), + * no key file will ever have a value less than 0x100000000, so + * the whole range 0..0xffffffff is available for non-key files. */ + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID(key); + return ((uint64_t) unsigned_owner_id << 32) | + MBEDTLS_SVC_KEY_ID_GET_KEY_ID(key); +#else + /* Use the key id directly as a file name. + * psa_is_key_id_valid() in psa_crypto_slot_management.c + * is responsible for ensuring that key identifiers do not have a + * value that is reserved for non-key files. */ + return key; +#endif +} + +/** + * \brief Load persistent data for the given key slot number. + * + * This function reads data from a storage backend and returns the data in a + * buffer. + * + * \param key Persistent identifier of the key to be loaded. This + * should be an occupied storage location. + * \param[out] data Buffer where the data is to be written. + * \param data_size Size of the \c data buffer in bytes. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription + */ +static psa_status_t psa_crypto_storage_load( + const mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size) +{ + psa_status_t status; + psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); + struct psa_storage_info_t data_identifier_info; + size_t data_length = 0; + + status = psa_its_get_info(data_identifier, &data_identifier_info); + if (status != PSA_SUCCESS) { + return status; + } + + status = psa_its_get(data_identifier, 0, (uint32_t) data_size, data, &data_length); + if (data_size != data_length) { + return PSA_ERROR_DATA_INVALID; + } + + return status; +} + +int psa_is_key_present_in_storage(const mbedtls_svc_key_id_t key) +{ + psa_status_t ret; + psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); + struct psa_storage_info_t data_identifier_info; + + ret = psa_its_get_info(data_identifier, &data_identifier_info); + + if (ret == PSA_ERROR_DOES_NOT_EXIST) { + return 0; + } + return 1; +} + +/** + * \brief Store persistent data for the given key slot number. + * + * This function stores the given data buffer to a persistent storage. + * + * \param key Persistent identifier of the key to be stored. This + * should be an unoccupied storage location. + * \param[in] data Buffer containing the data to be stored. + * \param data_length The number of bytes + * that make up the data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +static psa_status_t psa_crypto_storage_store(const mbedtls_svc_key_id_t key, + const uint8_t *data, + size_t data_length) +{ + psa_status_t status; + psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); + struct psa_storage_info_t data_identifier_info; + + if (psa_is_key_present_in_storage(key) == 1) { + return PSA_ERROR_ALREADY_EXISTS; + } + + status = psa_its_set(data_identifier, (uint32_t) data_length, data, 0); + if (status != PSA_SUCCESS) { + return PSA_ERROR_DATA_INVALID; + } + + status = psa_its_get_info(data_identifier, &data_identifier_info); + if (status != PSA_SUCCESS) { + goto exit; + } + + if (data_identifier_info.size != data_length) { + status = PSA_ERROR_DATA_INVALID; + goto exit; + } + +exit: + if (status != PSA_SUCCESS) { + /* Remove the file in case we managed to create it but something + * went wrong. It's ok if the file doesn't exist. If the file exists + * but the removal fails, we're already reporting an error so there's + * nothing else we can do. */ + (void) psa_its_remove(data_identifier); + } + return status; +} + +psa_status_t psa_destroy_persistent_key(const mbedtls_svc_key_id_t key) +{ + psa_status_t ret; + psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); + struct psa_storage_info_t data_identifier_info; + + ret = psa_its_get_info(data_identifier, &data_identifier_info); + if (ret == PSA_ERROR_DOES_NOT_EXIST) { + return PSA_SUCCESS; + } + + if (psa_its_remove(data_identifier) != PSA_SUCCESS) { + return PSA_ERROR_DATA_INVALID; + } + + ret = psa_its_get_info(data_identifier, &data_identifier_info); + if (ret != PSA_ERROR_DOES_NOT_EXIST) { + return PSA_ERROR_DATA_INVALID; + } + + return PSA_SUCCESS; +} + +/** + * \brief Get data length for given key slot number. + * + * \param key Persistent identifier whose stored data length + * is to be obtained. + * \param[out] data_length The number of bytes that make up the data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + */ +static psa_status_t psa_crypto_storage_get_data_length( + const mbedtls_svc_key_id_t key, + size_t *data_length) +{ + psa_status_t status; + psa_storage_uid_t data_identifier = psa_its_identifier_of_slot(key); + struct psa_storage_info_t data_identifier_info; + + status = psa_its_get_info(data_identifier, &data_identifier_info); + if (status != PSA_SUCCESS) { + return status; + } + + *data_length = (size_t) data_identifier_info.size; + + return PSA_SUCCESS; +} + +/** + * Persistent key storage magic header. + */ +#define PSA_KEY_STORAGE_MAGIC_HEADER "PSA\0KEY" +#define PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH (sizeof(PSA_KEY_STORAGE_MAGIC_HEADER)) + +typedef struct { + uint8_t magic[PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH]; + uint8_t version[4]; + uint8_t lifetime[sizeof(psa_key_lifetime_t)]; + uint8_t type[2]; + uint8_t bits[2]; + uint8_t policy[sizeof(psa_key_policy_t)]; + uint8_t data_len[4]; + uint8_t key_data[]; +} psa_persistent_key_storage_format; + +void psa_format_key_data_for_storage(const uint8_t *data, + const size_t data_length, + const psa_core_key_attributes_t *attr, + uint8_t *storage_data) +{ + psa_persistent_key_storage_format *storage_format = + (psa_persistent_key_storage_format *) storage_data; + + memcpy(storage_format->magic, PSA_KEY_STORAGE_MAGIC_HEADER, + PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH); + MBEDTLS_PUT_UINT32_LE(0, storage_format->version, 0); + MBEDTLS_PUT_UINT32_LE(attr->lifetime, storage_format->lifetime, 0); + MBEDTLS_PUT_UINT16_LE((uint16_t) attr->type, storage_format->type, 0); + MBEDTLS_PUT_UINT16_LE((uint16_t) attr->bits, storage_format->bits, 0); + MBEDTLS_PUT_UINT32_LE(attr->policy.usage, storage_format->policy, 0); + MBEDTLS_PUT_UINT32_LE(attr->policy.alg, storage_format->policy, sizeof(uint32_t)); + MBEDTLS_PUT_UINT32_LE(attr->policy.alg2, storage_format->policy, 2 * sizeof(uint32_t)); + MBEDTLS_PUT_UINT32_LE(data_length, storage_format->data_len, 0); + memcpy(storage_format->key_data, data, data_length); +} + +static psa_status_t check_magic_header(const uint8_t *data) +{ + if (memcmp(data, PSA_KEY_STORAGE_MAGIC_HEADER, + PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH) != 0) { + return PSA_ERROR_DATA_INVALID; + } + return PSA_SUCCESS; +} + +psa_status_t psa_parse_key_data_from_storage(const uint8_t *storage_data, + size_t storage_data_length, + uint8_t **key_data, + size_t *key_data_length, + psa_core_key_attributes_t *attr) +{ + psa_status_t status; + const psa_persistent_key_storage_format *storage_format = + (const psa_persistent_key_storage_format *) storage_data; + uint32_t version; + + if (storage_data_length < sizeof(*storage_format)) { + return PSA_ERROR_DATA_INVALID; + } + + status = check_magic_header(storage_data); + if (status != PSA_SUCCESS) { + return status; + } + + version = MBEDTLS_GET_UINT32_LE(storage_format->version, 0); + if (version != 0) { + return PSA_ERROR_DATA_INVALID; + } + + *key_data_length = MBEDTLS_GET_UINT32_LE(storage_format->data_len, 0); + if (*key_data_length > (storage_data_length - sizeof(*storage_format)) || + *key_data_length > PSA_CRYPTO_MAX_STORAGE_SIZE) { + return PSA_ERROR_DATA_INVALID; + } + + if (*key_data_length == 0) { + *key_data = NULL; + } else { + *key_data = mbedtls_calloc(1, *key_data_length); + if (*key_data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + memcpy(*key_data, storage_format->key_data, *key_data_length); + } + + attr->lifetime = MBEDTLS_GET_UINT32_LE(storage_format->lifetime, 0); + attr->type = MBEDTLS_GET_UINT16_LE(storage_format->type, 0); + attr->bits = MBEDTLS_GET_UINT16_LE(storage_format->bits, 0); + attr->policy.usage = MBEDTLS_GET_UINT32_LE(storage_format->policy, 0); + attr->policy.alg = MBEDTLS_GET_UINT32_LE(storage_format->policy, sizeof(uint32_t)); + attr->policy.alg2 = MBEDTLS_GET_UINT32_LE(storage_format->policy, 2 * sizeof(uint32_t)); + + return PSA_SUCCESS; +} + +psa_status_t psa_save_persistent_key(const psa_core_key_attributes_t *attr, + const uint8_t *data, + const size_t data_length) +{ + size_t storage_data_length; + uint8_t *storage_data; + psa_status_t status; + + /* All keys saved to persistent storage always have a key context */ + if (data == NULL || data_length == 0) { + return PSA_ERROR_INVALID_ARGUMENT; + } + + if (data_length > PSA_CRYPTO_MAX_STORAGE_SIZE) { + return PSA_ERROR_INSUFFICIENT_STORAGE; + } + storage_data_length = data_length + sizeof(psa_persistent_key_storage_format); + + storage_data = mbedtls_calloc(1, storage_data_length); + if (storage_data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + psa_format_key_data_for_storage(data, data_length, attr, storage_data); + + status = psa_crypto_storage_store(attr->id, + storage_data, storage_data_length); + + mbedtls_zeroize_and_free(storage_data, storage_data_length); + + return status; +} + +void psa_free_persistent_key_data(uint8_t *key_data, size_t key_data_length) +{ + mbedtls_zeroize_and_free(key_data, key_data_length); +} + +psa_status_t psa_load_persistent_key(psa_core_key_attributes_t *attr, + uint8_t **data, + size_t *data_length) +{ + psa_status_t status = PSA_SUCCESS; + uint8_t *loaded_data; + size_t storage_data_length = 0; + mbedtls_svc_key_id_t key = attr->id; + + status = psa_crypto_storage_get_data_length(key, &storage_data_length); + if (status != PSA_SUCCESS) { + return status; + } + + loaded_data = mbedtls_calloc(1, storage_data_length); + + if (loaded_data == NULL) { + return PSA_ERROR_INSUFFICIENT_MEMORY; + } + + status = psa_crypto_storage_load(key, loaded_data, storage_data_length); + if (status != PSA_SUCCESS) { + goto exit; + } + + status = psa_parse_key_data_from_storage(loaded_data, storage_data_length, + data, data_length, attr); + + /* All keys saved to persistent storage always have a key context */ + if (status == PSA_SUCCESS && + (*data == NULL || *data_length == 0)) { + status = PSA_ERROR_STORAGE_FAILURE; + } + +exit: + mbedtls_zeroize_and_free(loaded_data, storage_data_length); + return status; +} + + + +/****************************************************************/ +/* Transactions */ +/****************************************************************/ + +#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) + +psa_crypto_transaction_t psa_crypto_transaction; + +psa_status_t psa_crypto_save_transaction(void) +{ + struct psa_storage_info_t p_info; + psa_status_t status; + status = psa_its_get_info(PSA_CRYPTO_ITS_TRANSACTION_UID, &p_info); + if (status == PSA_SUCCESS) { + /* This shouldn't happen: we're trying to start a transaction while + * there is still a transaction that hasn't been replayed. */ + return PSA_ERROR_CORRUPTION_DETECTED; + } else if (status != PSA_ERROR_DOES_NOT_EXIST) { + return status; + } + return psa_its_set(PSA_CRYPTO_ITS_TRANSACTION_UID, + sizeof(psa_crypto_transaction), + &psa_crypto_transaction, + 0); +} + +psa_status_t psa_crypto_load_transaction(void) +{ + psa_status_t status; + size_t length; + status = psa_its_get(PSA_CRYPTO_ITS_TRANSACTION_UID, 0, + sizeof(psa_crypto_transaction), + &psa_crypto_transaction, &length); + if (status != PSA_SUCCESS) { + return status; + } + if (length != sizeof(psa_crypto_transaction)) { + return PSA_ERROR_DATA_INVALID; + } + return PSA_SUCCESS; +} + +psa_status_t psa_crypto_stop_transaction(void) +{ + psa_status_t status = psa_its_remove(PSA_CRYPTO_ITS_TRANSACTION_UID); + /* Whether or not updating the storage succeeded, the transaction is + * finished now. It's too late to go back, so zero out the in-memory + * data. */ + memset(&psa_crypto_transaction, 0, sizeof(psa_crypto_transaction)); + return status; +} + +#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ + + + +/****************************************************************/ +/* Random generator state */ +/****************************************************************/ + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) +psa_status_t mbedtls_psa_storage_inject_entropy(const unsigned char *seed, + size_t seed_size) +{ + psa_status_t status; + struct psa_storage_info_t p_info; + + status = psa_its_get_info(PSA_CRYPTO_ITS_RANDOM_SEED_UID, &p_info); + + if (PSA_ERROR_DOES_NOT_EXIST == status) { /* No seed exists */ + status = psa_its_set(PSA_CRYPTO_ITS_RANDOM_SEED_UID, seed_size, seed, 0); + } else if (PSA_SUCCESS == status) { + /* You should not be here. Seed needs to be injected only once */ + status = PSA_ERROR_NOT_PERMITTED; + } + return status; +} +#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ + + + +/****************************************************************/ +/* The end */ +/****************************************************************/ + +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.h index 37ca46e..a90b9b8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_crypto_storage.h @@ -1,396 +1,396 @@ -/** - * \file psa_crypto_storage.h - * - * \brief PSA cryptography module: Mbed TLS key storage - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef PSA_CRYPTO_STORAGE_H -#define PSA_CRYPTO_STORAGE_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "psa/crypto.h" -#include "psa/crypto_se_driver.h" - -#include -#include - -/* Limit the maximum key size in storage. This should have no effect - * since the key size is limited in memory. */ -#define PSA_CRYPTO_MAX_STORAGE_SIZE (PSA_BITS_TO_BYTES(PSA_MAX_KEY_BITS)) -/* Sanity check: a file size must fit in 32 bits. Allow a generous - * 64kB of metadata. */ -#if PSA_CRYPTO_MAX_STORAGE_SIZE > 0xffff0000 -#error "PSA_CRYPTO_MAX_STORAGE_SIZE > 0xffff0000" -#endif - -/** The maximum permitted persistent slot number. - * - * In Mbed Crypto 0.1.0b: - * - Using the file backend, all key ids are ok except 0. - * - Using the ITS backend, all key ids are ok except 0xFFFFFF52 - * (#PSA_CRYPTO_ITS_RANDOM_SEED_UID) for which the file contains the - * device's random seed (if this feature is enabled). - * - Only key ids from 1 to #MBEDTLS_PSA_KEY_SLOT_COUNT are actually used. - * - * Since we need to preserve the random seed, avoid using that key slot. - * Reserve a whole range of key slots just in case something else comes up. - * - * This limitation will probably become moot when we implement client - * separation for key storage. - */ -#define PSA_MAX_PERSISTENT_KEY_IDENTIFIER PSA_KEY_ID_VENDOR_MAX - -/** - * \brief Checks if persistent data is stored for the given key slot number - * - * This function checks if any key data or metadata exists for the key slot in - * the persistent storage. - * - * \param key Persistent identifier to check. - * - * \retval 0 - * No persistent data present for slot number - * \retval 1 - * Persistent data present for slot number - */ -int psa_is_key_present_in_storage(const mbedtls_svc_key_id_t key); - -/** - * \brief Format key data and metadata and save to a location for given key - * slot. - * - * This function formats the key data and metadata and saves it to a - * persistent storage backend. The storage location corresponding to the - * key slot must be empty, otherwise this function will fail. This function - * should be called after loading the key into an internal slot to ensure the - * persistent key is not saved into a storage location corresponding to an - * already occupied non-persistent key, as well as ensuring the key data is - * validated. - * - * Note: This function will only succeed for key buffers which are not - * empty. If passed a NULL pointer or zero-length, the function will fail - * with #PSA_ERROR_INVALID_ARGUMENT. - * - * \param[in] attr The attributes of the key to save. - * The key identifier field in the attributes - * determines the key's location. - * \param[in] data Buffer containing the key data. - * \param data_length The number of bytes that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -psa_status_t psa_save_persistent_key(const psa_core_key_attributes_t *attr, - const uint8_t *data, - const size_t data_length); - -/** - * \brief Parses key data and metadata and load persistent key for given - * key slot number. - * - * This function reads from a storage backend, parses the key data and - * metadata and writes them to the appropriate output parameters. - * - * Note: This function allocates a buffer and returns a pointer to it through - * the data parameter. On successful return, the pointer is guaranteed to be - * valid and the buffer contains at least one byte of data. - * psa_free_persistent_key_data() must be called on the data buffer - * afterwards to zeroize and free this buffer. - * - * \param[in,out] attr On input, the key identifier field identifies - * the key to load. Other fields are ignored. - * On success, the attribute structure contains - * the key metadata that was loaded from storage. - * \param[out] data Pointer to an allocated key data buffer on return. - * \param[out] data_length The number of bytes that make up the key data. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription - */ -psa_status_t psa_load_persistent_key(psa_core_key_attributes_t *attr, - uint8_t **data, - size_t *data_length); - -/** - * \brief Remove persistent data for the given key slot number. - * - * \param key Persistent identifier of the key to remove - * from persistent storage. - * - * \retval #PSA_SUCCESS - * The key was successfully removed, - * or the key did not exist. - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -psa_status_t psa_destroy_persistent_key(const mbedtls_svc_key_id_t key); - -/** - * \brief Free the temporary buffer allocated by psa_load_persistent_key(). - * - * This function must be called at some point after psa_load_persistent_key() - * to zeroize and free the memory allocated to the buffer in that function. - * - * \param key_data Buffer for the key data. - * \param key_data_length Size of the key data buffer. - * - */ -void psa_free_persistent_key_data(uint8_t *key_data, size_t key_data_length); - -/** - * \brief Formats key data and metadata for persistent storage - * - * \param[in] data Buffer containing the key data. - * \param data_length Length of the key data buffer. - * \param[in] attr The core attributes of the key. - * \param[out] storage_data Output buffer for the formatted data. - * - */ -void psa_format_key_data_for_storage(const uint8_t *data, - const size_t data_length, - const psa_core_key_attributes_t *attr, - uint8_t *storage_data); - -/** - * \brief Parses persistent storage data into key data and metadata - * - * \param[in] storage_data Buffer for the storage data. - * \param storage_data_length Length of the storage data buffer - * \param[out] key_data On output, pointer to a newly allocated buffer - * containing the key data. This must be freed - * using psa_free_persistent_key_data() - * \param[out] key_data_length Length of the key data buffer - * \param[out] attr On success, the attribute structure is filled - * with the loaded key metadata. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - */ -psa_status_t psa_parse_key_data_from_storage(const uint8_t *storage_data, - size_t storage_data_length, - uint8_t **key_data, - size_t *key_data_length, - psa_core_key_attributes_t *attr); - -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) -/** This symbol is defined if transaction support is required. */ -#define PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS 1 -#endif - -#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) - -/** The type of transaction that is in progress. - */ -/* This is an integer type rather than an enum for two reasons: to support - * unknown values when loading a transaction file, and to ensure that the - * type has a known size. - */ -typedef uint16_t psa_crypto_transaction_type_t; - -/** No transaction is in progress. - * - * This has the value 0, so zero-initialization sets a transaction's type to - * this value. - */ -#define PSA_CRYPTO_TRANSACTION_NONE ((psa_crypto_transaction_type_t) 0x0000) - -/** A key creation transaction. - * - * This is only used for keys in an external cryptoprocessor (secure element). - * Keys in RAM or in internal storage are created atomically in storage - * (simple file creation), so they do not need a transaction mechanism. - */ -#define PSA_CRYPTO_TRANSACTION_CREATE_KEY ((psa_crypto_transaction_type_t) 0x0001) - -/** A key destruction transaction. - * - * This is only used for keys in an external cryptoprocessor (secure element). - * Keys in RAM or in internal storage are destroyed atomically in storage - * (simple file deletion), so they do not need a transaction mechanism. - */ -#define PSA_CRYPTO_TRANSACTION_DESTROY_KEY ((psa_crypto_transaction_type_t) 0x0002) - -/** Transaction data. - * - * This type is designed to be serialized by writing the memory representation - * and reading it back on the same device. - * - * \note The transaction mechanism is designed for a single active transaction - * at a time. The transaction object is #psa_crypto_transaction. - * - * \note If an API call starts a transaction, it must complete this transaction - * before returning to the application. - * - * The lifetime of a transaction is the following (note that only one - * transaction may be active at a time): - * - * -# Call psa_crypto_prepare_transaction() to initialize the transaction - * object in memory and declare the type of transaction that is starting. - * -# Fill in the type-specific fields of #psa_crypto_transaction. - * -# Call psa_crypto_save_transaction() to start the transaction. This - * saves the transaction data to internal storage. - * -# Perform the work of the transaction by modifying files, contacting - * external entities, or whatever needs doing. Note that the transaction - * may be interrupted by a power failure, so you need to have a way - * recover from interruptions either by undoing what has been done - * so far or by resuming where you left off. - * -# If there are intermediate stages in the transaction, update - * the fields of #psa_crypto_transaction and call - * psa_crypto_save_transaction() again when each stage is reached. - * -# When the transaction is over, call psa_crypto_stop_transaction() to - * remove the transaction data in storage and in memory. - * - * If the system crashes while a transaction is in progress, psa_crypto_init() - * calls psa_crypto_load_transaction() and takes care of completing or - * rewinding the transaction. This is done in psa_crypto_recover_transaction() - * in psa_crypto.c. If you add a new type of transaction, be - * sure to add code for it in psa_crypto_recover_transaction(). - */ -typedef union { - /* Each element of this union must have the following properties - * to facilitate serialization and deserialization: - * - * - The element is a struct. - * - The first field of the struct is `psa_crypto_transaction_type_t type`. - * - Elements of the struct are arranged such a way that there is - * no padding. - */ - struct psa_crypto_transaction_unknown_s { - psa_crypto_transaction_type_t type; - uint16_t unused1; - uint32_t unused2; - uint64_t unused3; - uint64_t unused4; - } unknown; - /* ::type is #PSA_CRYPTO_TRANSACTION_CREATE_KEY or - * #PSA_CRYPTO_TRANSACTION_DESTROY_KEY. */ - struct psa_crypto_transaction_key_s { - psa_crypto_transaction_type_t type; - uint16_t unused1; - psa_key_lifetime_t lifetime; - psa_key_slot_number_t slot; - mbedtls_svc_key_id_t id; - } key; -} psa_crypto_transaction_t; - -/** The single active transaction. - */ -extern psa_crypto_transaction_t psa_crypto_transaction; - -/** Prepare for a transaction. - * - * There must not be an ongoing transaction. - * - * \param type The type of transaction to start. - */ -static inline void psa_crypto_prepare_transaction( - psa_crypto_transaction_type_t type) -{ - psa_crypto_transaction.unknown.type = type; -} - -/** Save the transaction data to storage. - * - * You may call this function multiple times during a transaction to - * atomically update the transaction state. - * - * \retval #PSA_SUCCESS \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - */ -psa_status_t psa_crypto_save_transaction(void); - -/** Load the transaction data from storage, if any. - * - * This function is meant to be called from psa_crypto_init() to recover - * in case a transaction was interrupted by a system crash. - * - * \retval #PSA_SUCCESS - * The data about the ongoing transaction has been loaded to - * #psa_crypto_transaction. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no ongoing transaction. - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_DATA_INVALID \emptydescription - * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription - */ -psa_status_t psa_crypto_load_transaction(void); - -/** Indicate that the current transaction is finished. - * - * Call this function at the very end of transaction processing. - * This function does not "commit" or "abort" the transaction: the storage - * subsystem has no concept of "commit" and "abort", just saving and - * removing the transaction information in storage. - * - * This function erases the transaction data in storage (if any) and - * resets the transaction data in memory. - * - * \retval #PSA_SUCCESS - * There was transaction data in storage. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There was no transaction data in storage. - * \retval #PSA_ERROR_STORAGE_FAILURE - * It was impossible to determine whether there was transaction data - * in storage, or the transaction data could not be erased. - */ -psa_status_t psa_crypto_stop_transaction(void); - -/** The ITS file identifier for the transaction data. - * - * 0xffffffNN = special file; 0x74 = 't' for transaction. - */ -#define PSA_CRYPTO_ITS_TRANSACTION_UID ((psa_key_id_t) 0xffffff74) - -#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ - -#if defined(MBEDTLS_PSA_INJECT_ENTROPY) -/** Backend side of mbedtls_psa_inject_entropy(). - * - * This function stores the supplied data into the entropy seed file. - * - * \retval #PSA_SUCCESS - * Success - * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription - * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription - * \retval #PSA_ERROR_NOT_PERMITTED - * The entropy seed file already exists. - */ -psa_status_t mbedtls_psa_storage_inject_entropy(const unsigned char *seed, - size_t seed_size); -#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ - -#ifdef __cplusplus -} -#endif - -#endif /* PSA_CRYPTO_STORAGE_H */ +/** + * \file psa_crypto_storage.h + * + * \brief PSA cryptography module: Mbed TLS key storage + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_STORAGE_H +#define PSA_CRYPTO_STORAGE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "psa/crypto.h" +#include "psa/crypto_se_driver.h" + +#include +#include + +/* Limit the maximum key size in storage. This should have no effect + * since the key size is limited in memory. */ +#define PSA_CRYPTO_MAX_STORAGE_SIZE (PSA_BITS_TO_BYTES(PSA_MAX_KEY_BITS)) +/* Sanity check: a file size must fit in 32 bits. Allow a generous + * 64kB of metadata. */ +#if PSA_CRYPTO_MAX_STORAGE_SIZE > 0xffff0000 +#error "PSA_CRYPTO_MAX_STORAGE_SIZE > 0xffff0000" +#endif + +/** The maximum permitted persistent slot number. + * + * In Mbed Crypto 0.1.0b: + * - Using the file backend, all key ids are ok except 0. + * - Using the ITS backend, all key ids are ok except 0xFFFFFF52 + * (#PSA_CRYPTO_ITS_RANDOM_SEED_UID) for which the file contains the + * device's random seed (if this feature is enabled). + * - Only key ids from 1 to #MBEDTLS_PSA_KEY_SLOT_COUNT are actually used. + * + * Since we need to preserve the random seed, avoid using that key slot. + * Reserve a whole range of key slots just in case something else comes up. + * + * This limitation will probably become moot when we implement client + * separation for key storage. + */ +#define PSA_MAX_PERSISTENT_KEY_IDENTIFIER PSA_KEY_ID_VENDOR_MAX + +/** + * \brief Checks if persistent data is stored for the given key slot number + * + * This function checks if any key data or metadata exists for the key slot in + * the persistent storage. + * + * \param key Persistent identifier to check. + * + * \retval 0 + * No persistent data present for slot number + * \retval 1 + * Persistent data present for slot number + */ +int psa_is_key_present_in_storage(const mbedtls_svc_key_id_t key); + +/** + * \brief Format key data and metadata and save to a location for given key + * slot. + * + * This function formats the key data and metadata and saves it to a + * persistent storage backend. The storage location corresponding to the + * key slot must be empty, otherwise this function will fail. This function + * should be called after loading the key into an internal slot to ensure the + * persistent key is not saved into a storage location corresponding to an + * already occupied non-persistent key, as well as ensuring the key data is + * validated. + * + * Note: This function will only succeed for key buffers which are not + * empty. If passed a NULL pointer or zero-length, the function will fail + * with #PSA_ERROR_INVALID_ARGUMENT. + * + * \param[in] attr The attributes of the key to save. + * The key identifier field in the attributes + * determines the key's location. + * \param[in] data Buffer containing the key data. + * \param data_length The number of bytes that make up the key data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INVALID_ARGUMENT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_ALREADY_EXISTS \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + */ +psa_status_t psa_save_persistent_key(const psa_core_key_attributes_t *attr, + const uint8_t *data, + const size_t data_length); + +/** + * \brief Parses key data and metadata and load persistent key for given + * key slot number. + * + * This function reads from a storage backend, parses the key data and + * metadata and writes them to the appropriate output parameters. + * + * Note: This function allocates a buffer and returns a pointer to it through + * the data parameter. On successful return, the pointer is guaranteed to be + * valid and the buffer contains at least one byte of data. + * psa_free_persistent_key_data() must be called on the data buffer + * afterwards to zeroize and free this buffer. + * + * \param[in,out] attr On input, the key identifier field identifies + * the key to load. Other fields are ignored. + * On success, the attribute structure contains + * the key metadata that was loaded from storage. + * \param[out] data Pointer to an allocated key data buffer on return. + * \param[out] data_length The number of bytes that make up the key data. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_DOES_NOT_EXIST \emptydescription + */ +psa_status_t psa_load_persistent_key(psa_core_key_attributes_t *attr, + uint8_t **data, + size_t *data_length); + +/** + * \brief Remove persistent data for the given key slot number. + * + * \param key Persistent identifier of the key to remove + * from persistent storage. + * + * \retval #PSA_SUCCESS + * The key was successfully removed, + * or the key did not exist. + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +psa_status_t psa_destroy_persistent_key(const mbedtls_svc_key_id_t key); + +/** + * \brief Free the temporary buffer allocated by psa_load_persistent_key(). + * + * This function must be called at some point after psa_load_persistent_key() + * to zeroize and free the memory allocated to the buffer in that function. + * + * \param key_data Buffer for the key data. + * \param key_data_length Size of the key data buffer. + * + */ +void psa_free_persistent_key_data(uint8_t *key_data, size_t key_data_length); + +/** + * \brief Formats key data and metadata for persistent storage + * + * \param[in] data Buffer containing the key data. + * \param data_length Length of the key data buffer. + * \param[in] attr The core attributes of the key. + * \param[out] storage_data Output buffer for the formatted data. + * + */ +void psa_format_key_data_for_storage(const uint8_t *data, + const size_t data_length, + const psa_core_key_attributes_t *attr, + uint8_t *storage_data); + +/** + * \brief Parses persistent storage data into key data and metadata + * + * \param[in] storage_data Buffer for the storage data. + * \param storage_data_length Length of the storage data buffer + * \param[out] key_data On output, pointer to a newly allocated buffer + * containing the key data. This must be freed + * using psa_free_persistent_key_data() + * \param[out] key_data_length Length of the key data buffer + * \param[out] attr On success, the attribute structure is filled + * with the loaded key metadata. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + */ +psa_status_t psa_parse_key_data_from_storage(const uint8_t *storage_data, + size_t storage_data_length, + uint8_t **key_data, + size_t *key_data_length, + psa_core_key_attributes_t *attr); + +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/** This symbol is defined if transaction support is required. */ +#define PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS 1 +#endif + +#if defined(PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS) + +/** The type of transaction that is in progress. + */ +/* This is an integer type rather than an enum for two reasons: to support + * unknown values when loading a transaction file, and to ensure that the + * type has a known size. + */ +typedef uint16_t psa_crypto_transaction_type_t; + +/** No transaction is in progress. + * + * This has the value 0, so zero-initialization sets a transaction's type to + * this value. + */ +#define PSA_CRYPTO_TRANSACTION_NONE ((psa_crypto_transaction_type_t) 0x0000) + +/** A key creation transaction. + * + * This is only used for keys in an external cryptoprocessor (secure element). + * Keys in RAM or in internal storage are created atomically in storage + * (simple file creation), so they do not need a transaction mechanism. + */ +#define PSA_CRYPTO_TRANSACTION_CREATE_KEY ((psa_crypto_transaction_type_t) 0x0001) + +/** A key destruction transaction. + * + * This is only used for keys in an external cryptoprocessor (secure element). + * Keys in RAM or in internal storage are destroyed atomically in storage + * (simple file deletion), so they do not need a transaction mechanism. + */ +#define PSA_CRYPTO_TRANSACTION_DESTROY_KEY ((psa_crypto_transaction_type_t) 0x0002) + +/** Transaction data. + * + * This type is designed to be serialized by writing the memory representation + * and reading it back on the same device. + * + * \note The transaction mechanism is designed for a single active transaction + * at a time. The transaction object is #psa_crypto_transaction. + * + * \note If an API call starts a transaction, it must complete this transaction + * before returning to the application. + * + * The lifetime of a transaction is the following (note that only one + * transaction may be active at a time): + * + * -# Call psa_crypto_prepare_transaction() to initialize the transaction + * object in memory and declare the type of transaction that is starting. + * -# Fill in the type-specific fields of #psa_crypto_transaction. + * -# Call psa_crypto_save_transaction() to start the transaction. This + * saves the transaction data to internal storage. + * -# Perform the work of the transaction by modifying files, contacting + * external entities, or whatever needs doing. Note that the transaction + * may be interrupted by a power failure, so you need to have a way + * recover from interruptions either by undoing what has been done + * so far or by resuming where you left off. + * -# If there are intermediate stages in the transaction, update + * the fields of #psa_crypto_transaction and call + * psa_crypto_save_transaction() again when each stage is reached. + * -# When the transaction is over, call psa_crypto_stop_transaction() to + * remove the transaction data in storage and in memory. + * + * If the system crashes while a transaction is in progress, psa_crypto_init() + * calls psa_crypto_load_transaction() and takes care of completing or + * rewinding the transaction. This is done in psa_crypto_recover_transaction() + * in psa_crypto.c. If you add a new type of transaction, be + * sure to add code for it in psa_crypto_recover_transaction(). + */ +typedef union { + /* Each element of this union must have the following properties + * to facilitate serialization and deserialization: + * + * - The element is a struct. + * - The first field of the struct is `psa_crypto_transaction_type_t type`. + * - Elements of the struct are arranged such a way that there is + * no padding. + */ + struct psa_crypto_transaction_unknown_s { + psa_crypto_transaction_type_t type; + uint16_t unused1; + uint32_t unused2; + uint64_t unused3; + uint64_t unused4; + } unknown; + /* ::type is #PSA_CRYPTO_TRANSACTION_CREATE_KEY or + * #PSA_CRYPTO_TRANSACTION_DESTROY_KEY. */ + struct psa_crypto_transaction_key_s { + psa_crypto_transaction_type_t type; + uint16_t unused1; + psa_key_lifetime_t lifetime; + psa_key_slot_number_t slot; + mbedtls_svc_key_id_t id; + } key; +} psa_crypto_transaction_t; + +/** The single active transaction. + */ +extern psa_crypto_transaction_t psa_crypto_transaction; + +/** Prepare for a transaction. + * + * There must not be an ongoing transaction. + * + * \param type The type of transaction to start. + */ +static inline void psa_crypto_prepare_transaction( + psa_crypto_transaction_type_t type) +{ + psa_crypto_transaction.unknown.type = type; +} + +/** Save the transaction data to storage. + * + * You may call this function multiple times during a transaction to + * atomically update the transaction state. + * + * \retval #PSA_SUCCESS \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + */ +psa_status_t psa_crypto_save_transaction(void); + +/** Load the transaction data from storage, if any. + * + * This function is meant to be called from psa_crypto_init() to recover + * in case a transaction was interrupted by a system crash. + * + * \retval #PSA_SUCCESS + * The data about the ongoing transaction has been loaded to + * #psa_crypto_transaction. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no ongoing transaction. + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_DATA_INVALID \emptydescription + * \retval #PSA_ERROR_DATA_CORRUPT \emptydescription + */ +psa_status_t psa_crypto_load_transaction(void); + +/** Indicate that the current transaction is finished. + * + * Call this function at the very end of transaction processing. + * This function does not "commit" or "abort" the transaction: the storage + * subsystem has no concept of "commit" and "abort", just saving and + * removing the transaction information in storage. + * + * This function erases the transaction data in storage (if any) and + * resets the transaction data in memory. + * + * \retval #PSA_SUCCESS + * There was transaction data in storage. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There was no transaction data in storage. + * \retval #PSA_ERROR_STORAGE_FAILURE + * It was impossible to determine whether there was transaction data + * in storage, or the transaction data could not be erased. + */ +psa_status_t psa_crypto_stop_transaction(void); + +/** The ITS file identifier for the transaction data. + * + * 0xffffffNN = special file; 0x74 = 't' for transaction. + */ +#define PSA_CRYPTO_ITS_TRANSACTION_UID ((psa_key_id_t) 0xffffff74) + +#endif /* PSA_CRYPTO_STORAGE_HAS_TRANSACTIONS */ + +#if defined(MBEDTLS_PSA_INJECT_ENTROPY) +/** Backend side of mbedtls_psa_inject_entropy(). + * + * This function stores the supplied data into the entropy seed file. + * + * \retval #PSA_SUCCESS + * Success + * \retval #PSA_ERROR_STORAGE_FAILURE \emptydescription + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE \emptydescription + * \retval #PSA_ERROR_NOT_PERMITTED + * The entropy seed file already exists. + */ +psa_status_t mbedtls_psa_storage_inject_entropy(const unsigned char *seed, + size_t seed_size); +#endif /* MBEDTLS_PSA_INJECT_ENTROPY */ + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_STORAGE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util.c index 5a17c8d..2a6ecec 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util.c @@ -1,171 +1,171 @@ -/* - * PSA hashing layer on top of Mbed TLS software crypto - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "common.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -#include - -#include "psa_util_internal.h" - -/* The following includes are needed for MBEDTLS_ERR_XXX macros */ -#include -#if defined(MBEDTLS_MD_LIGHT) -#include -#endif -#if defined(MBEDTLS_LMS_C) -#include -#endif -#if defined(MBEDTLS_SSL_TLS_C) && \ - (defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3)) -#include -#endif -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -#include -#endif -#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ - defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -#include -#endif -#if defined(MBEDTLS_PK_C) -#include -#endif - -/* PSA_SUCCESS is kept at the top of each error table since - * it's the most common status when everything functions properly. */ -#if defined(MBEDTLS_MD_LIGHT) -const mbedtls_error_pair_t psa_to_md_errors[] = -{ - { PSA_SUCCESS, 0 }, - { PSA_ERROR_NOT_SUPPORTED, MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE }, - { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_MD_BAD_INPUT_DATA }, - { PSA_ERROR_INSUFFICIENT_MEMORY, MBEDTLS_ERR_MD_ALLOC_FAILED } -}; -#endif -#if defined(MBEDTLS_LMS_C) -const mbedtls_error_pair_t psa_to_lms_errors[] = -{ - { PSA_SUCCESS, 0 }, - { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_LMS_BUFFER_TOO_SMALL }, - { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_LMS_BAD_INPUT_DATA } -}; -#endif -#if defined(MBEDTLS_SSL_TLS_C) && \ - (defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3)) -const mbedtls_error_pair_t psa_to_ssl_errors[] = -{ - { PSA_SUCCESS, 0 }, - { PSA_ERROR_INSUFFICIENT_MEMORY, MBEDTLS_ERR_SSL_ALLOC_FAILED }, - { PSA_ERROR_NOT_SUPPORTED, MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE }, - { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_SSL_INVALID_MAC }, - { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_SSL_BAD_INPUT_DATA }, - { PSA_ERROR_BAD_STATE, MBEDTLS_ERR_SSL_INTERNAL_ERROR }, - { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL } -}; -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -const mbedtls_error_pair_t psa_to_pk_rsa_errors[] = -{ - { PSA_SUCCESS, 0 }, - { PSA_ERROR_NOT_PERMITTED, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, - { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, - { PSA_ERROR_INVALID_HANDLE, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, - { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE }, - { PSA_ERROR_INSUFFICIENT_ENTROPY, MBEDTLS_ERR_RSA_RNG_FAILED }, - { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_RSA_VERIFY_FAILED }, - { PSA_ERROR_INVALID_PADDING, MBEDTLS_ERR_RSA_INVALID_PADDING } -}; -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ - defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -const mbedtls_error_pair_t psa_to_pk_ecdsa_errors[] = -{ - { PSA_SUCCESS, 0 }, - { PSA_ERROR_NOT_PERMITTED, MBEDTLS_ERR_ECP_BAD_INPUT_DATA }, - { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_ECP_BAD_INPUT_DATA }, - { PSA_ERROR_INVALID_HANDLE, MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE }, - { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL }, - { PSA_ERROR_INSUFFICIENT_ENTROPY, MBEDTLS_ERR_ECP_RANDOM_FAILED }, - { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_ECP_VERIFY_FAILED } -}; -#endif - -int psa_generic_status_to_mbedtls(psa_status_t status) -{ - switch (status) { - case PSA_SUCCESS: - return 0; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - case PSA_ERROR_CORRUPTION_DETECTED: - return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - case PSA_ERROR_COMMUNICATION_FAILURE: - case PSA_ERROR_HARDWARE_FAILURE: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - case PSA_ERROR_NOT_PERMITTED: - default: - return MBEDTLS_ERR_ERROR_GENERIC_ERROR; - } -} - -int psa_status_to_mbedtls(psa_status_t status, - const mbedtls_error_pair_t *local_translations, - size_t local_errors_num, - int (*fallback_f)(psa_status_t)) -{ - for (size_t i = 0; i < local_errors_num; i++) { - if (status == local_translations[i].psa_status) { - return local_translations[i].mbedtls_error; - } - } - return fallback_f(status); -} - -#if defined(MBEDTLS_PK_C) -int psa_pk_status_to_mbedtls(psa_status_t status) -{ - switch (status) { - case PSA_ERROR_INVALID_HANDLE: - return MBEDTLS_ERR_PK_KEY_INVALID_FORMAT; - case PSA_ERROR_BUFFER_TOO_SMALL: - return MBEDTLS_ERR_PK_BUFFER_TOO_SMALL; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE; - case PSA_ERROR_INVALID_ARGUMENT: - return MBEDTLS_ERR_PK_INVALID_ALG; - case PSA_ERROR_INSUFFICIENT_MEMORY: - return MBEDTLS_ERR_PK_ALLOC_FAILED; - case PSA_ERROR_BAD_STATE: - return MBEDTLS_ERR_PK_BAD_INPUT_DATA; - case PSA_ERROR_DATA_CORRUPT: - case PSA_ERROR_DATA_INVALID: - case PSA_ERROR_STORAGE_FAILURE: - return MBEDTLS_ERR_PK_FILE_IO_ERROR; - default: - return psa_generic_status_to_mbedtls(status); - } -} -#endif /* MBEDTLS_PK_C */ -#endif /* MBEDTLS_PSA_CRYPTO_C */ +/* + * PSA hashing layer on top of Mbed TLS software crypto + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +#include + +#include "psa_util_internal.h" + +/* The following includes are needed for MBEDTLS_ERR_XXX macros */ +#include +#if defined(MBEDTLS_MD_LIGHT) +#include +#endif +#if defined(MBEDTLS_LMS_C) +#include +#endif +#if defined(MBEDTLS_SSL_TLS_C) && \ + (defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3)) +#include +#endif +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +#include +#endif +#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#include +#endif +#if defined(MBEDTLS_PK_C) +#include +#endif + +/* PSA_SUCCESS is kept at the top of each error table since + * it's the most common status when everything functions properly. */ +#if defined(MBEDTLS_MD_LIGHT) +const mbedtls_error_pair_t psa_to_md_errors[] = +{ + { PSA_SUCCESS, 0 }, + { PSA_ERROR_NOT_SUPPORTED, MBEDTLS_ERR_MD_FEATURE_UNAVAILABLE }, + { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_MD_BAD_INPUT_DATA }, + { PSA_ERROR_INSUFFICIENT_MEMORY, MBEDTLS_ERR_MD_ALLOC_FAILED } +}; +#endif +#if defined(MBEDTLS_LMS_C) +const mbedtls_error_pair_t psa_to_lms_errors[] = +{ + { PSA_SUCCESS, 0 }, + { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_LMS_BUFFER_TOO_SMALL }, + { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_LMS_BAD_INPUT_DATA } +}; +#endif +#if defined(MBEDTLS_SSL_TLS_C) && \ + (defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3)) +const mbedtls_error_pair_t psa_to_ssl_errors[] = +{ + { PSA_SUCCESS, 0 }, + { PSA_ERROR_INSUFFICIENT_MEMORY, MBEDTLS_ERR_SSL_ALLOC_FAILED }, + { PSA_ERROR_NOT_SUPPORTED, MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE }, + { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_SSL_INVALID_MAC }, + { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_SSL_BAD_INPUT_DATA }, + { PSA_ERROR_BAD_STATE, MBEDTLS_ERR_SSL_INTERNAL_ERROR }, + { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL } +}; +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +const mbedtls_error_pair_t psa_to_pk_rsa_errors[] = +{ + { PSA_SUCCESS, 0 }, + { PSA_ERROR_NOT_PERMITTED, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, + { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, + { PSA_ERROR_INVALID_HANDLE, MBEDTLS_ERR_RSA_BAD_INPUT_DATA }, + { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_RSA_OUTPUT_TOO_LARGE }, + { PSA_ERROR_INSUFFICIENT_ENTROPY, MBEDTLS_ERR_RSA_RNG_FAILED }, + { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_RSA_VERIFY_FAILED }, + { PSA_ERROR_INVALID_PADDING, MBEDTLS_ERR_RSA_INVALID_PADDING } +}; +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +const mbedtls_error_pair_t psa_to_pk_ecdsa_errors[] = +{ + { PSA_SUCCESS, 0 }, + { PSA_ERROR_NOT_PERMITTED, MBEDTLS_ERR_ECP_BAD_INPUT_DATA }, + { PSA_ERROR_INVALID_ARGUMENT, MBEDTLS_ERR_ECP_BAD_INPUT_DATA }, + { PSA_ERROR_INVALID_HANDLE, MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE }, + { PSA_ERROR_BUFFER_TOO_SMALL, MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL }, + { PSA_ERROR_INSUFFICIENT_ENTROPY, MBEDTLS_ERR_ECP_RANDOM_FAILED }, + { PSA_ERROR_INVALID_SIGNATURE, MBEDTLS_ERR_ECP_VERIFY_FAILED } +}; +#endif + +int psa_generic_status_to_mbedtls(psa_status_t status) +{ + switch (status) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + case PSA_ERROR_CORRUPTION_DETECTED: + return MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + case PSA_ERROR_COMMUNICATION_FAILURE: + case PSA_ERROR_HARDWARE_FAILURE: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + case PSA_ERROR_NOT_PERMITTED: + default: + return MBEDTLS_ERR_ERROR_GENERIC_ERROR; + } +} + +int psa_status_to_mbedtls(psa_status_t status, + const mbedtls_error_pair_t *local_translations, + size_t local_errors_num, + int (*fallback_f)(psa_status_t)) +{ + for (size_t i = 0; i < local_errors_num; i++) { + if (status == local_translations[i].psa_status) { + return local_translations[i].mbedtls_error; + } + } + return fallback_f(status); +} + +#if defined(MBEDTLS_PK_C) +int psa_pk_status_to_mbedtls(psa_status_t status) +{ + switch (status) { + case PSA_ERROR_INVALID_HANDLE: + return MBEDTLS_ERR_PK_KEY_INVALID_FORMAT; + case PSA_ERROR_BUFFER_TOO_SMALL: + return MBEDTLS_ERR_PK_BUFFER_TOO_SMALL; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE; + case PSA_ERROR_INVALID_ARGUMENT: + return MBEDTLS_ERR_PK_INVALID_ALG; + case PSA_ERROR_INSUFFICIENT_MEMORY: + return MBEDTLS_ERR_PK_ALLOC_FAILED; + case PSA_ERROR_BAD_STATE: + return MBEDTLS_ERR_PK_BAD_INPUT_DATA; + case PSA_ERROR_DATA_CORRUPT: + case PSA_ERROR_DATA_INVALID: + case PSA_ERROR_STORAGE_FAILURE: + return MBEDTLS_ERR_PK_FILE_IO_ERROR; + default: + return psa_generic_status_to_mbedtls(status); + } +} +#endif /* MBEDTLS_PK_C */ +#endif /* MBEDTLS_PSA_CRYPTO_C */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util_internal.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util_internal.h index 4a36dbf..625fb30 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util_internal.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/psa_util_internal.h @@ -1,108 +1,108 @@ -/** - * \file psa_util_internal.h - * - * \brief Internal utility functions for use of PSA Crypto. - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_PSA_UTIL_INTERNAL_H -#define MBEDTLS_PSA_UTIL_INTERNAL_H - -/* Include the public header so that users only need one include. */ -#include "mbedtls/psa_util.h" - -#include "psa/crypto.h" - -#if defined(MBEDTLS_PSA_CRYPTO_C) - -/************************************************************************* - * FFDH - ************************************************************************/ - -#define MBEDTLS_PSA_MAX_FFDH_PUBKEY_LENGTH \ - PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) - -/************************************************************************* - * ECC - ************************************************************************/ - -#define MBEDTLS_PSA_MAX_EC_PUBKEY_LENGTH \ - PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) - -#define MBEDTLS_PSA_MAX_EC_KEY_PAIR_LENGTH \ - PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) - -/************************************************************************* - * Error translation - ************************************************************************/ - -typedef struct { - /* Error codes used by PSA crypto are in -255..-128, fitting in 16 bits. */ - int16_t psa_status; - /* Error codes used by Mbed TLS are in one of the ranges - * -127..-1 (low-level) or -32767..-4096 (high-level with a low-level - * code optionally added), fitting in 16 bits. */ - int16_t mbedtls_error; -} mbedtls_error_pair_t; - -#if defined(MBEDTLS_MD_LIGHT) -extern const mbedtls_error_pair_t psa_to_md_errors[4]; -#endif - -#if defined(MBEDTLS_LMS_C) -extern const mbedtls_error_pair_t psa_to_lms_errors[3]; -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) -extern const mbedtls_error_pair_t psa_to_ssl_errors[7]; -#endif - -#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ - defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) -extern const mbedtls_error_pair_t psa_to_pk_rsa_errors[8]; -#endif - -#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ - defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) -extern const mbedtls_error_pair_t psa_to_pk_ecdsa_errors[7]; -#endif - -/* Generic fallback function for error translation, - * when the received state was not module-specific. */ -int psa_generic_status_to_mbedtls(psa_status_t status); - -/* This function iterates over provided local error translations, - * and if no match was found - calls the fallback error translation function. */ -int psa_status_to_mbedtls(psa_status_t status, - const mbedtls_error_pair_t *local_translations, - size_t local_errors_num, - int (*fallback_f)(psa_status_t)); - -/* The second out of three-stage error handling functions of the pk module, - * acts as a fallback after RSA / ECDSA error translation, and if no match - * is found, it itself calls psa_generic_status_to_mbedtls. */ -int psa_pk_status_to_mbedtls(psa_status_t status); - -/* Utility macro to shorten the defines of error translator in modules. */ -#define PSA_TO_MBEDTLS_ERR_LIST(status, error_list, fallback_f) \ - psa_status_to_mbedtls(status, error_list, \ - sizeof(error_list)/sizeof(error_list[0]), \ - fallback_f) - -#endif /* MBEDTLS_PSA_CRYPTO_C */ -#endif /* MBEDTLS_PSA_UTIL_INTERNAL_H */ +/** + * \file psa_util_internal.h + * + * \brief Internal utility functions for use of PSA Crypto. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_PSA_UTIL_INTERNAL_H +#define MBEDTLS_PSA_UTIL_INTERNAL_H + +/* Include the public header so that users only need one include. */ +#include "mbedtls/psa_util.h" + +#include "psa/crypto.h" + +#if defined(MBEDTLS_PSA_CRYPTO_C) + +/************************************************************************* + * FFDH + ************************************************************************/ + +#define MBEDTLS_PSA_MAX_FFDH_PUBKEY_LENGTH \ + PSA_KEY_EXPORT_FFDH_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_FFDH_MAX_KEY_BITS) + +/************************************************************************* + * ECC + ************************************************************************/ + +#define MBEDTLS_PSA_MAX_EC_PUBKEY_LENGTH \ + PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) + +#define MBEDTLS_PSA_MAX_EC_KEY_PAIR_LENGTH \ + PSA_KEY_EXPORT_ECC_KEY_PAIR_MAX_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) + +/************************************************************************* + * Error translation + ************************************************************************/ + +typedef struct { + /* Error codes used by PSA crypto are in -255..-128, fitting in 16 bits. */ + int16_t psa_status; + /* Error codes used by Mbed TLS are in one of the ranges + * -127..-1 (low-level) or -32767..-4096 (high-level with a low-level + * code optionally added), fitting in 16 bits. */ + int16_t mbedtls_error; +} mbedtls_error_pair_t; + +#if defined(MBEDTLS_MD_LIGHT) +extern const mbedtls_error_pair_t psa_to_md_errors[4]; +#endif + +#if defined(MBEDTLS_LMS_C) +extern const mbedtls_error_pair_t psa_to_lms_errors[3]; +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) +extern const mbedtls_error_pair_t psa_to_ssl_errors[7]; +#endif + +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) || \ + defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_BASIC) +extern const mbedtls_error_pair_t psa_to_pk_rsa_errors[8]; +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) && \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +extern const mbedtls_error_pair_t psa_to_pk_ecdsa_errors[7]; +#endif + +/* Generic fallback function for error translation, + * when the received state was not module-specific. */ +int psa_generic_status_to_mbedtls(psa_status_t status); + +/* This function iterates over provided local error translations, + * and if no match was found - calls the fallback error translation function. */ +int psa_status_to_mbedtls(psa_status_t status, + const mbedtls_error_pair_t *local_translations, + size_t local_errors_num, + int (*fallback_f)(psa_status_t)); + +/* The second out of three-stage error handling functions of the pk module, + * acts as a fallback after RSA / ECDSA error translation, and if no match + * is found, it itself calls psa_generic_status_to_mbedtls. */ +int psa_pk_status_to_mbedtls(psa_status_t status); + +/* Utility macro to shorten the defines of error translator in modules. */ +#define PSA_TO_MBEDTLS_ERR_LIST(status, error_list, fallback_f) \ + psa_status_to_mbedtls(status, error_list, \ + sizeof(error_list)/sizeof(error_list[0]), \ + fallback_f) + +#endif /* MBEDTLS_PSA_CRYPTO_C */ +#endif /* MBEDTLS_PSA_UTIL_INTERNAL_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/rsa_alt_helpers.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/rsa_alt_helpers.h index 3b22ba8..d7c7c12 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/rsa_alt_helpers.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/rsa_alt_helpers.h @@ -1,220 +1,220 @@ -/** - * \file rsa_alt_helpers.h - * - * \brief Context-independent RSA helper functions - * - * This module declares some RSA-related helper functions useful when - * implementing the RSA interface. These functions are provided in a separate - * compilation unit in order to make it easy for designers of alternative RSA - * implementations to use them in their own code, as it is conceived that the - * functionality they provide will be necessary for most complete - * implementations. - * - * End-users of Mbed TLS who are not providing their own alternative RSA - * implementations should not use these functions directly, and should instead - * use only the functions declared in rsa.h. - * - * The interface provided by this module will be maintained through LTS (Long - * Term Support) branches of Mbed TLS, but may otherwise be subject to change, - * and must be considered an internal interface of the library. - * - * There are two classes of helper functions: - * - * (1) Parameter-generating helpers. These are: - * - mbedtls_rsa_deduce_primes - * - mbedtls_rsa_deduce_private_exponent - * - mbedtls_rsa_deduce_crt - * Each of these functions takes a set of core RSA parameters and - * generates some other, or CRT related parameters. - * - * (2) Parameter-checking helpers. These are: - * - mbedtls_rsa_validate_params - * - mbedtls_rsa_validate_crt - * They take a set of core or CRT related RSA parameters and check their - * validity. - * - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#ifndef MBEDTLS_RSA_INTERNAL_H -#define MBEDTLS_RSA_INTERNAL_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/bignum.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * \brief Compute RSA prime moduli P, Q from public modulus N=PQ - * and a pair of private and public key. - * - * \note This is a 'static' helper function not operating on - * an RSA context. Alternative implementations need not - * overwrite it. - * - * \param N RSA modulus N = PQ, with P, Q to be found - * \param E RSA public exponent - * \param D RSA private exponent - * \param P Pointer to MPI holding first prime factor of N on success - * \param Q Pointer to MPI holding second prime factor of N on success - * - * \return - * - 0 if successful. In this case, P and Q constitute a - * factorization of N. - * - A non-zero error code otherwise. - * - * \note It is neither checked that P, Q are prime nor that - * D, E are modular inverses wrt. P-1 and Q-1. For that, - * use the helper function \c mbedtls_rsa_validate_params. - * - */ -int mbedtls_rsa_deduce_primes(mbedtls_mpi const *N, mbedtls_mpi const *E, - mbedtls_mpi const *D, - mbedtls_mpi *P, mbedtls_mpi *Q); - -/** - * \brief Compute RSA private exponent from - * prime moduli and public key. - * - * \note This is a 'static' helper function not operating on - * an RSA context. Alternative implementations need not - * overwrite it. - * - * \param P First prime factor of RSA modulus - * \param Q Second prime factor of RSA modulus - * \param E RSA public exponent - * \param D Pointer to MPI holding the private exponent on success. - * - * \return - * - 0 if successful. In this case, D is set to a simultaneous - * modular inverse of E modulo both P-1 and Q-1. - * - A non-zero error code otherwise. - * - * \note This function does not check whether P and Q are primes. - * - */ -int mbedtls_rsa_deduce_private_exponent(mbedtls_mpi const *P, - mbedtls_mpi const *Q, - mbedtls_mpi const *E, - mbedtls_mpi *D); - - -/** - * \brief Generate RSA-CRT parameters - * - * \note This is a 'static' helper function not operating on - * an RSA context. Alternative implementations need not - * overwrite it. - * - * \param P First prime factor of N - * \param Q Second prime factor of N - * \param D RSA private exponent - * \param DP Output variable for D modulo P-1 - * \param DQ Output variable for D modulo Q-1 - * \param QP Output variable for the modular inverse of Q modulo P. - * - * \return 0 on success, non-zero error code otherwise. - * - * \note This function does not check whether P, Q are - * prime and whether D is a valid private exponent. - * - */ -int mbedtls_rsa_deduce_crt(const mbedtls_mpi *P, const mbedtls_mpi *Q, - const mbedtls_mpi *D, mbedtls_mpi *DP, - mbedtls_mpi *DQ, mbedtls_mpi *QP); - - -/** - * \brief Check validity of core RSA parameters - * - * \note This is a 'static' helper function not operating on - * an RSA context. Alternative implementations need not - * overwrite it. - * - * \param N RSA modulus N = PQ - * \param P First prime factor of N - * \param Q Second prime factor of N - * \param D RSA private exponent - * \param E RSA public exponent - * \param f_rng PRNG to be used for primality check, or NULL - * \param p_rng PRNG context for f_rng, or NULL - * - * \return - * - 0 if the following conditions are satisfied - * if all relevant parameters are provided: - * - P prime if f_rng != NULL (%) - * - Q prime if f_rng != NULL (%) - * - 1 < N = P * Q - * - 1 < D, E < N - * - D and E are modular inverses modulo P-1 and Q-1 - * (%) This is only done if MBEDTLS_GENPRIME is defined. - * - A non-zero error code otherwise. - * - * \note The function can be used with a restricted set of arguments - * to perform specific checks only. E.g., calling it with - * (-,P,-,-,-) and a PRNG amounts to a primality check for P. - */ -int mbedtls_rsa_validate_params(const mbedtls_mpi *N, const mbedtls_mpi *P, - const mbedtls_mpi *Q, const mbedtls_mpi *D, - const mbedtls_mpi *E, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); - -/** - * \brief Check validity of RSA CRT parameters - * - * \note This is a 'static' helper function not operating on - * an RSA context. Alternative implementations need not - * overwrite it. - * - * \param P First prime factor of RSA modulus - * \param Q Second prime factor of RSA modulus - * \param D RSA private exponent - * \param DP MPI to check for D modulo P-1 - * \param DQ MPI to check for D modulo P-1 - * \param QP MPI to check for the modular inverse of Q modulo P. - * - * \return - * - 0 if the following conditions are satisfied: - * - D = DP mod P-1 if P, D, DP != NULL - * - Q = DQ mod P-1 if P, D, DQ != NULL - * - QP = Q^-1 mod P if P, Q, QP != NULL - * - \c MBEDTLS_ERR_RSA_KEY_CHECK_FAILED if check failed, - * potentially including \c MBEDTLS_ERR_MPI_XXX if some - * MPI calculations failed. - * - \c MBEDTLS_ERR_RSA_BAD_INPUT_DATA if insufficient - * data was provided to check DP, DQ or QP. - * - * \note The function can be used with a restricted set of arguments - * to perform specific checks only. E.g., calling it with the - * parameters (P, -, D, DP, -, -) will check DP = D mod P-1. - */ -int mbedtls_rsa_validate_crt(const mbedtls_mpi *P, const mbedtls_mpi *Q, - const mbedtls_mpi *D, const mbedtls_mpi *DP, - const mbedtls_mpi *DQ, const mbedtls_mpi *QP); - -#ifdef __cplusplus -} -#endif - -#endif /* rsa_alt_helpers.h */ +/** + * \file rsa_alt_helpers.h + * + * \brief Context-independent RSA helper functions + * + * This module declares some RSA-related helper functions useful when + * implementing the RSA interface. These functions are provided in a separate + * compilation unit in order to make it easy for designers of alternative RSA + * implementations to use them in their own code, as it is conceived that the + * functionality they provide will be necessary for most complete + * implementations. + * + * End-users of Mbed TLS who are not providing their own alternative RSA + * implementations should not use these functions directly, and should instead + * use only the functions declared in rsa.h. + * + * The interface provided by this module will be maintained through LTS (Long + * Term Support) branches of Mbed TLS, but may otherwise be subject to change, + * and must be considered an internal interface of the library. + * + * There are two classes of helper functions: + * + * (1) Parameter-generating helpers. These are: + * - mbedtls_rsa_deduce_primes + * - mbedtls_rsa_deduce_private_exponent + * - mbedtls_rsa_deduce_crt + * Each of these functions takes a set of core RSA parameters and + * generates some other, or CRT related parameters. + * + * (2) Parameter-checking helpers. These are: + * - mbedtls_rsa_validate_params + * - mbedtls_rsa_validate_crt + * They take a set of core or CRT related RSA parameters and check their + * validity. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef MBEDTLS_RSA_INTERNAL_H +#define MBEDTLS_RSA_INTERNAL_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/bignum.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * \brief Compute RSA prime moduli P, Q from public modulus N=PQ + * and a pair of private and public key. + * + * \note This is a 'static' helper function not operating on + * an RSA context. Alternative implementations need not + * overwrite it. + * + * \param N RSA modulus N = PQ, with P, Q to be found + * \param E RSA public exponent + * \param D RSA private exponent + * \param P Pointer to MPI holding first prime factor of N on success + * \param Q Pointer to MPI holding second prime factor of N on success + * + * \return + * - 0 if successful. In this case, P and Q constitute a + * factorization of N. + * - A non-zero error code otherwise. + * + * \note It is neither checked that P, Q are prime nor that + * D, E are modular inverses wrt. P-1 and Q-1. For that, + * use the helper function \c mbedtls_rsa_validate_params. + * + */ +int mbedtls_rsa_deduce_primes(mbedtls_mpi const *N, mbedtls_mpi const *E, + mbedtls_mpi const *D, + mbedtls_mpi *P, mbedtls_mpi *Q); + +/** + * \brief Compute RSA private exponent from + * prime moduli and public key. + * + * \note This is a 'static' helper function not operating on + * an RSA context. Alternative implementations need not + * overwrite it. + * + * \param P First prime factor of RSA modulus + * \param Q Second prime factor of RSA modulus + * \param E RSA public exponent + * \param D Pointer to MPI holding the private exponent on success. + * + * \return + * - 0 if successful. In this case, D is set to a simultaneous + * modular inverse of E modulo both P-1 and Q-1. + * - A non-zero error code otherwise. + * + * \note This function does not check whether P and Q are primes. + * + */ +int mbedtls_rsa_deduce_private_exponent(mbedtls_mpi const *P, + mbedtls_mpi const *Q, + mbedtls_mpi const *E, + mbedtls_mpi *D); + + +/** + * \brief Generate RSA-CRT parameters + * + * \note This is a 'static' helper function not operating on + * an RSA context. Alternative implementations need not + * overwrite it. + * + * \param P First prime factor of N + * \param Q Second prime factor of N + * \param D RSA private exponent + * \param DP Output variable for D modulo P-1 + * \param DQ Output variable for D modulo Q-1 + * \param QP Output variable for the modular inverse of Q modulo P. + * + * \return 0 on success, non-zero error code otherwise. + * + * \note This function does not check whether P, Q are + * prime and whether D is a valid private exponent. + * + */ +int mbedtls_rsa_deduce_crt(const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, mbedtls_mpi *DP, + mbedtls_mpi *DQ, mbedtls_mpi *QP); + + +/** + * \brief Check validity of core RSA parameters + * + * \note This is a 'static' helper function not operating on + * an RSA context. Alternative implementations need not + * overwrite it. + * + * \param N RSA modulus N = PQ + * \param P First prime factor of N + * \param Q Second prime factor of N + * \param D RSA private exponent + * \param E RSA public exponent + * \param f_rng PRNG to be used for primality check, or NULL + * \param p_rng PRNG context for f_rng, or NULL + * + * \return + * - 0 if the following conditions are satisfied + * if all relevant parameters are provided: + * - P prime if f_rng != NULL (%) + * - Q prime if f_rng != NULL (%) + * - 1 < N = P * Q + * - 1 < D, E < N + * - D and E are modular inverses modulo P-1 and Q-1 + * (%) This is only done if MBEDTLS_GENPRIME is defined. + * - A non-zero error code otherwise. + * + * \note The function can be used with a restricted set of arguments + * to perform specific checks only. E.g., calling it with + * (-,P,-,-,-) and a PRNG amounts to a primality check for P. + */ +int mbedtls_rsa_validate_params(const mbedtls_mpi *N, const mbedtls_mpi *P, + const mbedtls_mpi *Q, const mbedtls_mpi *D, + const mbedtls_mpi *E, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); + +/** + * \brief Check validity of RSA CRT parameters + * + * \note This is a 'static' helper function not operating on + * an RSA context. Alternative implementations need not + * overwrite it. + * + * \param P First prime factor of RSA modulus + * \param Q Second prime factor of RSA modulus + * \param D RSA private exponent + * \param DP MPI to check for D modulo P-1 + * \param DQ MPI to check for D modulo P-1 + * \param QP MPI to check for the modular inverse of Q modulo P. + * + * \return + * - 0 if the following conditions are satisfied: + * - D = DP mod P-1 if P, D, DP != NULL + * - Q = DQ mod P-1 if P, D, DQ != NULL + * - QP = Q^-1 mod P if P, Q, QP != NULL + * - \c MBEDTLS_ERR_RSA_KEY_CHECK_FAILED if check failed, + * potentially including \c MBEDTLS_ERR_MPI_XXX if some + * MPI calculations failed. + * - \c MBEDTLS_ERR_RSA_BAD_INPUT_DATA if insufficient + * data was provided to check DP, DQ or QP. + * + * \note The function can be used with a restricted set of arguments + * to perform specific checks only. E.g., calling it with the + * parameters (P, -, D, DP, -, -) will check DP = D mod P-1. + */ +int mbedtls_rsa_validate_crt(const mbedtls_mpi *P, const mbedtls_mpi *Q, + const mbedtls_mpi *D, const mbedtls_mpi *DP, + const mbedtls_mpi *DQ, const mbedtls_mpi *QP); + +#ifdef __cplusplus +} +#endif + +#endif /* rsa_alt_helpers.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_client.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_client.h index f57bea3..416efad 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_client.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_client.h @@ -1,34 +1,34 @@ -/** - * TLS 1.2 and 1.3 client-side functions - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_SSL_CLIENT_H -#define MBEDTLS_SSL_CLIENT_H - -#include "common.h" - -#if defined(MBEDTLS_SSL_TLS_C) -#include "ssl_misc.h" -#endif - -#include - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_client_hello(mbedtls_ssl_context *ssl); - -#endif /* MBEDTLS_SSL_CLIENT_H */ +/** + * TLS 1.2 and 1.3 client-side functions + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SSL_CLIENT_H +#define MBEDTLS_SSL_CLIENT_H + +#include "common.h" + +#if defined(MBEDTLS_SSL_TLS_C) +#include "ssl_misc.h" +#endif + +#include + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_client_hello(mbedtls_ssl_context *ssl); + +#endif /* MBEDTLS_SSL_CLIENT_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_debug_helpers.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_debug_helpers.h index 5c22ed2..f2ce9c8 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_debug_helpers.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_debug_helpers.h @@ -1,90 +1,90 @@ -/** - * \file ssl_debug_helpers.h - * - * \brief Automatically generated helper functions for debugging - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_SSL_DEBUG_HELPERS_H -#define MBEDTLS_SSL_DEBUG_HELPERS_H - -#include "common.h" - -#if defined(MBEDTLS_DEBUG_C) - -#include "mbedtls/ssl.h" -#include "ssl_misc.h" - - -const char *mbedtls_ssl_states_str(mbedtls_ssl_states in); - -const char *mbedtls_ssl_protocol_version_str(mbedtls_ssl_protocol_version in); - -const char *mbedtls_tls_prf_types_str(mbedtls_tls_prf_types in); - -const char *mbedtls_ssl_key_export_type_str(mbedtls_ssl_key_export_type in); - -const char *mbedtls_ssl_sig_alg_to_str(uint16_t in); - -const char *mbedtls_ssl_named_group_to_str(uint16_t in); - -const char *mbedtls_ssl_get_extension_name(unsigned int extension_type); - -void mbedtls_ssl_print_extensions(const mbedtls_ssl_context *ssl, - int level, const char *file, int line, - int hs_msg_type, uint32_t extensions_mask, - const char *extra); - -void mbedtls_ssl_print_extension(const mbedtls_ssl_context *ssl, - int level, const char *file, int line, - int hs_msg_type, unsigned int extension_type, - const char *extra_msg0, const char *extra_msg1); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -void mbedtls_ssl_print_ticket_flags(const mbedtls_ssl_context *ssl, - int level, const char *file, int line, - unsigned int flags); -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ - -#define MBEDTLS_SSL_PRINT_EXTS(level, hs_msg_type, extensions_mask) \ - mbedtls_ssl_print_extensions(ssl, level, __FILE__, __LINE__, \ - hs_msg_type, extensions_mask, NULL) - -#define MBEDTLS_SSL_PRINT_EXT(level, hs_msg_type, extension_type, extra) \ - mbedtls_ssl_print_extension(ssl, level, __FILE__, __LINE__, \ - hs_msg_type, extension_type, \ - extra, NULL) - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -#define MBEDTLS_SSL_PRINT_TICKET_FLAGS(level, flags) \ - mbedtls_ssl_print_ticket_flags(ssl, level, __FILE__, __LINE__, flags) -#endif - -#else - -#define MBEDTLS_SSL_PRINT_EXTS(level, hs_msg_type, extension_mask) - -#define MBEDTLS_SSL_PRINT_EXT(level, hs_msg_type, extension_type, extra) - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -#define MBEDTLS_SSL_PRINT_TICKET_FLAGS(level, flags) -#endif - -#endif /* MBEDTLS_DEBUG_C */ - -#endif /* MBEDTLS_SSL_DEBUG_HELPERS_H */ +/** + * \file ssl_debug_helpers.h + * + * \brief Automatically generated helper functions for debugging + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SSL_DEBUG_HELPERS_H +#define MBEDTLS_SSL_DEBUG_HELPERS_H + +#include "common.h" + +#if defined(MBEDTLS_DEBUG_C) + +#include "mbedtls/ssl.h" +#include "ssl_misc.h" + + +const char *mbedtls_ssl_states_str(mbedtls_ssl_states in); + +const char *mbedtls_ssl_protocol_version_str(mbedtls_ssl_protocol_version in); + +const char *mbedtls_tls_prf_types_str(mbedtls_tls_prf_types in); + +const char *mbedtls_ssl_key_export_type_str(mbedtls_ssl_key_export_type in); + +const char *mbedtls_ssl_sig_alg_to_str(uint16_t in); + +const char *mbedtls_ssl_named_group_to_str(uint16_t in); + +const char *mbedtls_ssl_get_extension_name(unsigned int extension_type); + +void mbedtls_ssl_print_extensions(const mbedtls_ssl_context *ssl, + int level, const char *file, int line, + int hs_msg_type, uint32_t extensions_mask, + const char *extra); + +void mbedtls_ssl_print_extension(const mbedtls_ssl_context *ssl, + int level, const char *file, int line, + int hs_msg_type, unsigned int extension_type, + const char *extra_msg0, const char *extra_msg1); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +void mbedtls_ssl_print_ticket_flags(const mbedtls_ssl_context *ssl, + int level, const char *file, int line, + unsigned int flags); +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ + +#define MBEDTLS_SSL_PRINT_EXTS(level, hs_msg_type, extensions_mask) \ + mbedtls_ssl_print_extensions(ssl, level, __FILE__, __LINE__, \ + hs_msg_type, extensions_mask, NULL) + +#define MBEDTLS_SSL_PRINT_EXT(level, hs_msg_type, extension_type, extra) \ + mbedtls_ssl_print_extension(ssl, level, __FILE__, __LINE__, \ + hs_msg_type, extension_type, \ + extra, NULL) + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +#define MBEDTLS_SSL_PRINT_TICKET_FLAGS(level, flags) \ + mbedtls_ssl_print_ticket_flags(ssl, level, __FILE__, __LINE__, flags) +#endif + +#else + +#define MBEDTLS_SSL_PRINT_EXTS(level, hs_msg_type, extension_mask) + +#define MBEDTLS_SSL_PRINT_EXT(level, hs_msg_type, extension_type, extra) + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +#define MBEDTLS_SSL_PRINT_TICKET_FLAGS(level, flags) +#endif + +#endif /* MBEDTLS_DEBUG_C */ + +#endif /* MBEDTLS_SSL_DEBUG_HELPERS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_misc.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_misc.h index a99bb33..7c764cb 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_misc.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_misc.h @@ -1,2859 +1,2859 @@ -/** - * \file ssl_misc.h - * - * \brief Internal functions shared by the SSL modules - */ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBEDTLS_SSL_MISC_H -#define MBEDTLS_SSL_MISC_H - -#include "mbedtls/build_info.h" - -#include "mbedtls/error.h" - -#include "mbedtls/ssl.h" -#include "mbedtls/cipher.h" - -#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) -#include "psa/crypto.h" -#include "psa_util_internal.h" -#endif - -#if defined(MBEDTLS_MD_CAN_MD5) -#include "mbedtls/md5.h" -#endif - -#if defined(MBEDTLS_MD_CAN_SHA1) -#include "mbedtls/sha1.h" -#endif - -#if defined(MBEDTLS_MD_CAN_SHA256) -#include "mbedtls/sha256.h" -#endif - -#if defined(MBEDTLS_MD_CAN_SHA512) -#include "mbedtls/sha512.h" -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ - !defined(MBEDTLS_USE_PSA_CRYPTO) -#include "mbedtls/ecjpake.h" -#endif - -#include "mbedtls/pk.h" -#include "pk_internal.h" -#include "common.h" - -/* Shorthand for restartable ECC */ -#if defined(MBEDTLS_ECP_RESTARTABLE) && \ - defined(MBEDTLS_SSL_CLI_C) && \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ - defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) -#define MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED -#endif - -#define MBEDTLS_SSL_INITIAL_HANDSHAKE 0 -#define MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS 1 /* In progress */ -#define MBEDTLS_SSL_RENEGOTIATION_DONE 2 /* Done or aborted */ -#define MBEDTLS_SSL_RENEGOTIATION_PENDING 3 /* Requested (server only) */ - -/* Faked handshake message identity for HelloRetryRequest. */ -#define MBEDTLS_SSL_TLS1_3_HS_HELLO_RETRY_REQUEST (-MBEDTLS_SSL_HS_SERVER_HELLO) - -/* - * Internal identity of handshake extensions - */ -#define MBEDTLS_SSL_EXT_ID_UNRECOGNIZED 0 -#define MBEDTLS_SSL_EXT_ID_SERVERNAME 1 -#define MBEDTLS_SSL_EXT_ID_SERVERNAME_HOSTNAME 1 -#define MBEDTLS_SSL_EXT_ID_MAX_FRAGMENT_LENGTH 2 -#define MBEDTLS_SSL_EXT_ID_STATUS_REQUEST 3 -#define MBEDTLS_SSL_EXT_ID_SUPPORTED_GROUPS 4 -#define MBEDTLS_SSL_EXT_ID_SUPPORTED_ELLIPTIC_CURVES 4 -#define MBEDTLS_SSL_EXT_ID_SIG_ALG 5 -#define MBEDTLS_SSL_EXT_ID_USE_SRTP 6 -#define MBEDTLS_SSL_EXT_ID_HEARTBEAT 7 -#define MBEDTLS_SSL_EXT_ID_ALPN 8 -#define MBEDTLS_SSL_EXT_ID_SCT 9 -#define MBEDTLS_SSL_EXT_ID_CLI_CERT_TYPE 10 -#define MBEDTLS_SSL_EXT_ID_SERV_CERT_TYPE 11 -#define MBEDTLS_SSL_EXT_ID_PADDING 12 -#define MBEDTLS_SSL_EXT_ID_PRE_SHARED_KEY 13 -#define MBEDTLS_SSL_EXT_ID_EARLY_DATA 14 -#define MBEDTLS_SSL_EXT_ID_SUPPORTED_VERSIONS 15 -#define MBEDTLS_SSL_EXT_ID_COOKIE 16 -#define MBEDTLS_SSL_EXT_ID_PSK_KEY_EXCHANGE_MODES 17 -#define MBEDTLS_SSL_EXT_ID_CERT_AUTH 18 -#define MBEDTLS_SSL_EXT_ID_OID_FILTERS 19 -#define MBEDTLS_SSL_EXT_ID_POST_HANDSHAKE_AUTH 20 -#define MBEDTLS_SSL_EXT_ID_SIG_ALG_CERT 21 -#define MBEDTLS_SSL_EXT_ID_KEY_SHARE 22 -#define MBEDTLS_SSL_EXT_ID_TRUNCATED_HMAC 23 -#define MBEDTLS_SSL_EXT_ID_SUPPORTED_POINT_FORMATS 24 -#define MBEDTLS_SSL_EXT_ID_ENCRYPT_THEN_MAC 25 -#define MBEDTLS_SSL_EXT_ID_EXTENDED_MASTER_SECRET 26 -#define MBEDTLS_SSL_EXT_ID_SESSION_TICKET 27 -#define MBEDTLS_SSL_EXT_ID_RECORD_SIZE_LIMIT 28 - -/* Utility for translating IANA extension type. */ -uint32_t mbedtls_ssl_get_extension_id(unsigned int extension_type); -uint32_t mbedtls_ssl_get_extension_mask(unsigned int extension_type); -/* Macros used to define mask constants */ -#define MBEDTLS_SSL_EXT_MASK(id) (1ULL << (MBEDTLS_SSL_EXT_ID_##id)) -/* Reset value of extension mask */ -#define MBEDTLS_SSL_EXT_MASK_NONE 0 - -/* In messages containing extension requests, we should ignore unrecognized - * extensions. In messages containing extension responses, unrecognized - * extensions should result in handshake abortion. Messages containing - * extension requests include ClientHello, CertificateRequest and - * NewSessionTicket. Messages containing extension responses include - * ServerHello, HelloRetryRequest, EncryptedExtensions and Certificate. - * - * RFC 8446 section 4.1.3 - * - * The ServerHello MUST only include extensions which are required to establish - * the cryptographic context and negotiate the protocol version. - * - * RFC 8446 section 4.2 - * - * If an implementation receives an extension which it recognizes and which is - * not specified for the message in which it appears, it MUST abort the handshake - * with an "illegal_parameter" alert. - */ - -/* Extensions that are not recognized by TLS 1.3 */ -#define MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED \ - (MBEDTLS_SSL_EXT_MASK(SUPPORTED_POINT_FORMATS) | \ - MBEDTLS_SSL_EXT_MASK(ENCRYPT_THEN_MAC) | \ - MBEDTLS_SSL_EXT_MASK(EXTENDED_MASTER_SECRET) | \ - MBEDTLS_SSL_EXT_MASK(SESSION_TICKET) | \ - MBEDTLS_SSL_EXT_MASK(TRUNCATED_HMAC) | \ - MBEDTLS_SSL_EXT_MASK(UNRECOGNIZED)) - -/* RFC 8446 section 4.2. Allowed extensions for ClientHello */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CH \ - (MBEDTLS_SSL_EXT_MASK(SERVERNAME) | \ - MBEDTLS_SSL_EXT_MASK(MAX_FRAGMENT_LENGTH) | \ - MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ - MBEDTLS_SSL_EXT_MASK(SUPPORTED_GROUPS) | \ - MBEDTLS_SSL_EXT_MASK(SIG_ALG) | \ - MBEDTLS_SSL_EXT_MASK(USE_SRTP) | \ - MBEDTLS_SSL_EXT_MASK(HEARTBEAT) | \ - MBEDTLS_SSL_EXT_MASK(ALPN) | \ - MBEDTLS_SSL_EXT_MASK(SCT) | \ - MBEDTLS_SSL_EXT_MASK(CLI_CERT_TYPE) | \ - MBEDTLS_SSL_EXT_MASK(SERV_CERT_TYPE) | \ - MBEDTLS_SSL_EXT_MASK(PADDING) | \ - MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ - MBEDTLS_SSL_EXT_MASK(PRE_SHARED_KEY) | \ - MBEDTLS_SSL_EXT_MASK(PSK_KEY_EXCHANGE_MODES) | \ - MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ - MBEDTLS_SSL_EXT_MASK(COOKIE) | \ - MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS) | \ - MBEDTLS_SSL_EXT_MASK(CERT_AUTH) | \ - MBEDTLS_SSL_EXT_MASK(POST_HANDSHAKE_AUTH) | \ - MBEDTLS_SSL_EXT_MASK(SIG_ALG_CERT) | \ - MBEDTLS_SSL_EXT_MASK(RECORD_SIZE_LIMIT) | \ - MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) - -/* RFC 8446 section 4.2. Allowed extensions for EncryptedExtensions */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_EE \ - (MBEDTLS_SSL_EXT_MASK(SERVERNAME) | \ - MBEDTLS_SSL_EXT_MASK(MAX_FRAGMENT_LENGTH) | \ - MBEDTLS_SSL_EXT_MASK(SUPPORTED_GROUPS) | \ - MBEDTLS_SSL_EXT_MASK(USE_SRTP) | \ - MBEDTLS_SSL_EXT_MASK(HEARTBEAT) | \ - MBEDTLS_SSL_EXT_MASK(ALPN) | \ - MBEDTLS_SSL_EXT_MASK(CLI_CERT_TYPE) | \ - MBEDTLS_SSL_EXT_MASK(SERV_CERT_TYPE) | \ - MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ - MBEDTLS_SSL_EXT_MASK(RECORD_SIZE_LIMIT)) - -/* RFC 8446 section 4.2. Allowed extensions for CertificateRequest */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CR \ - (MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ - MBEDTLS_SSL_EXT_MASK(SIG_ALG) | \ - MBEDTLS_SSL_EXT_MASK(SCT) | \ - MBEDTLS_SSL_EXT_MASK(CERT_AUTH) | \ - MBEDTLS_SSL_EXT_MASK(OID_FILTERS) | \ - MBEDTLS_SSL_EXT_MASK(SIG_ALG_CERT) | \ - MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) - -/* RFC 8446 section 4.2. Allowed extensions for Certificate */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CT \ - (MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ - MBEDTLS_SSL_EXT_MASK(SCT)) - -/* RFC 8446 section 4.2. Allowed extensions for ServerHello */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_SH \ - (MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ - MBEDTLS_SSL_EXT_MASK(PRE_SHARED_KEY) | \ - MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS)) - -/* RFC 8446 section 4.2. Allowed extensions for HelloRetryRequest */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_HRR \ - (MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ - MBEDTLS_SSL_EXT_MASK(COOKIE) | \ - MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS)) - -/* RFC 8446 section 4.2. Allowed extensions for NewSessionTicket */ -#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_NST \ - (MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ - MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) - -/* - * Helper macros for function call with return check. - */ -/* - * Exit when return non-zero value - */ -#define MBEDTLS_SSL_PROC_CHK(f) \ - do { \ - ret = (f); \ - if (ret != 0) \ - { \ - goto cleanup; \ - } \ - } while (0) -/* - * Exit when return negative value - */ -#define MBEDTLS_SSL_PROC_CHK_NEG(f) \ - do { \ - ret = (f); \ - if (ret < 0) \ - { \ - goto cleanup; \ - } \ - } while (0) - -/* - * DTLS retransmission states, see RFC 6347 4.2.4 - * - * The SENDING state is merged in PREPARING for initial sends, - * but is distinct for resends. - * - * Note: initial state is wrong for server, but is not used anyway. - */ -#define MBEDTLS_SSL_RETRANS_PREPARING 0 -#define MBEDTLS_SSL_RETRANS_SENDING 1 -#define MBEDTLS_SSL_RETRANS_WAITING 2 -#define MBEDTLS_SSL_RETRANS_FINISHED 3 - -/* - * Allow extra bytes for record, authentication and encryption overhead: - * counter (8) + header (5) + IV(16) + MAC (16-48) + padding (0-256). - */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - -/* This macro determines whether CBC is supported. */ -#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ - (defined(MBEDTLS_AES_C) || \ - defined(MBEDTLS_CAMELLIA_C) || \ - defined(MBEDTLS_ARIA_C) || \ - defined(MBEDTLS_DES_C)) -#define MBEDTLS_SSL_SOME_SUITES_USE_CBC -#endif - -/* This macro determines whether a ciphersuite using a - * stream cipher can be used. */ -#if defined(MBEDTLS_CIPHER_NULL_CIPHER) -#define MBEDTLS_SSL_SOME_SUITES_USE_STREAM -#endif - -/* This macro determines whether the CBC construct used in TLS 1.2 is supported. */ -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) && \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) -#define MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC -#endif - -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_STREAM) || \ - defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) -#define MBEDTLS_SSL_SOME_SUITES_USE_MAC -#endif - -/* This macro determines whether a ciphersuite uses Encrypt-then-MAC with CBC */ -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) && \ - defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) -#define MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM -#endif - -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) -/* Ciphersuites using HMAC */ -#if defined(MBEDTLS_MD_CAN_SHA384) -#define MBEDTLS_SSL_MAC_ADD 48 /* SHA-384 used for HMAC */ -#elif defined(MBEDTLS_MD_CAN_SHA256) -#define MBEDTLS_SSL_MAC_ADD 32 /* SHA-256 used for HMAC */ -#else -#define MBEDTLS_SSL_MAC_ADD 20 /* SHA-1 used for HMAC */ -#endif -#else /* MBEDTLS_SSL_SOME_SUITES_USE_MAC */ -/* AEAD ciphersuites: GCM and CCM use a 128 bits tag */ -#define MBEDTLS_SSL_MAC_ADD 16 -#endif - -#if defined(MBEDTLS_CIPHER_MODE_CBC) -#define MBEDTLS_SSL_PADDING_ADD 256 -#else -#define MBEDTLS_SSL_PADDING_ADD 0 -#endif - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -#define MBEDTLS_SSL_MAX_CID_EXPANSION MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY -#else -#define MBEDTLS_SSL_MAX_CID_EXPANSION 0 -#endif - -#define MBEDTLS_SSL_PAYLOAD_OVERHEAD (MBEDTLS_MAX_IV_LENGTH + \ - MBEDTLS_SSL_MAC_ADD + \ - MBEDTLS_SSL_PADDING_ADD + \ - MBEDTLS_SSL_MAX_CID_EXPANSION \ - ) - -#define MBEDTLS_SSL_IN_PAYLOAD_LEN (MBEDTLS_SSL_PAYLOAD_OVERHEAD + \ - (MBEDTLS_SSL_IN_CONTENT_LEN)) - -#define MBEDTLS_SSL_OUT_PAYLOAD_LEN (MBEDTLS_SSL_PAYLOAD_OVERHEAD + \ - (MBEDTLS_SSL_OUT_CONTENT_LEN)) - -/* The maximum number of buffered handshake messages. */ -#define MBEDTLS_SSL_MAX_BUFFERED_HS 4 - -/* Maximum length we can advertise as our max content length for - RFC 6066 max_fragment_length extension negotiation purposes - (the lesser of both sizes, if they are unequal.) - */ -#define MBEDTLS_TLS_EXT_ADV_CONTENT_LEN ( \ - (MBEDTLS_SSL_IN_CONTENT_LEN > MBEDTLS_SSL_OUT_CONTENT_LEN) \ - ? (MBEDTLS_SSL_OUT_CONTENT_LEN) \ - : (MBEDTLS_SSL_IN_CONTENT_LEN) \ - ) - -/* Maximum size in bytes of list in signature algorithms ext., RFC 5246/8446 */ -#define MBEDTLS_SSL_MAX_SIG_ALG_LIST_LEN 65534 - -/* Minimum size in bytes of list in signature algorithms ext., RFC 5246/8446 */ -#define MBEDTLS_SSL_MIN_SIG_ALG_LIST_LEN 2 - -/* Maximum size in bytes of list in supported elliptic curve ext., RFC 4492 */ -#define MBEDTLS_SSL_MAX_CURVE_LIST_LEN 65535 - -#define MBEDTLS_RECEIVED_SIG_ALGS_SIZE 20 - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) - -#define MBEDTLS_TLS_SIG_NONE MBEDTLS_TLS1_3_SIG_NONE - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -#define MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG(sig, hash) ((hash << 8) | sig) -#define MBEDTLS_SSL_TLS12_SIG_ALG_FROM_SIG_AND_HASH_ALG(alg) (alg & 0xFF) -#define MBEDTLS_SSL_TLS12_HASH_ALG_FROM_SIG_AND_HASH_ALG(alg) (alg >> 8) -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - -/* - * Check that we obey the standard's message size bounds - */ - -#if MBEDTLS_SSL_IN_CONTENT_LEN > 16384 -#error "Bad configuration - incoming record content too large." -#endif - -#if MBEDTLS_SSL_OUT_CONTENT_LEN > 16384 -#error "Bad configuration - outgoing record content too large." -#endif - -#if MBEDTLS_SSL_IN_PAYLOAD_LEN > MBEDTLS_SSL_IN_CONTENT_LEN + 2048 -#error "Bad configuration - incoming protected record payload too large." -#endif - -#if MBEDTLS_SSL_OUT_PAYLOAD_LEN > MBEDTLS_SSL_OUT_CONTENT_LEN + 2048 -#error "Bad configuration - outgoing protected record payload too large." -#endif - -/* Calculate buffer sizes */ - -/* Note: Even though the TLS record header is only 5 bytes - long, we're internally using 8 bytes to store the - implicit sequence number. */ -#define MBEDTLS_SSL_HEADER_LEN 13 - -#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -#define MBEDTLS_SSL_IN_BUFFER_LEN \ - ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_IN_PAYLOAD_LEN)) -#else -#define MBEDTLS_SSL_IN_BUFFER_LEN \ - ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_IN_PAYLOAD_LEN) \ - + (MBEDTLS_SSL_CID_IN_LEN_MAX)) -#endif - -#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -#define MBEDTLS_SSL_OUT_BUFFER_LEN \ - ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_OUT_PAYLOAD_LEN)) -#else -#define MBEDTLS_SSL_OUT_BUFFER_LEN \ - ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_OUT_PAYLOAD_LEN) \ - + (MBEDTLS_SSL_CID_OUT_LEN_MAX)) -#endif - -#define MBEDTLS_CLIENT_HELLO_RANDOM_LEN 32 -#define MBEDTLS_SERVER_HELLO_RANDOM_LEN 32 - -#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) -/** - * \brief Return the maximum fragment length (payload, in bytes) for - * the output buffer. For the client, this is the configured - * value. For the server, it is the minimum of two - the - * configured value and the negotiated one. - * - * \sa mbedtls_ssl_conf_max_frag_len() - * \sa mbedtls_ssl_get_max_out_record_payload() - * - * \param ssl SSL context - * - * \return Current maximum fragment length for the output buffer. - */ -size_t mbedtls_ssl_get_output_max_frag_len(const mbedtls_ssl_context *ssl); - -/** - * \brief Return the maximum fragment length (payload, in bytes) for - * the input buffer. This is the negotiated maximum fragment - * length, or, if there is none, MBEDTLS_SSL_IN_CONTENT_LEN. - * If it is not defined either, the value is 2^14. This function - * works as its predecessor, \c mbedtls_ssl_get_max_frag_len(). - * - * \sa mbedtls_ssl_conf_max_frag_len() - * \sa mbedtls_ssl_get_max_in_record_payload() - * - * \param ssl SSL context - * - * \return Current maximum fragment length for the output buffer. - */ -size_t mbedtls_ssl_get_input_max_frag_len(const mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ - -#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) -static inline size_t mbedtls_ssl_get_output_buflen(const mbedtls_ssl_context *ctx) -{ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - return mbedtls_ssl_get_output_max_frag_len(ctx) - + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD - + MBEDTLS_SSL_CID_OUT_LEN_MAX; -#else - return mbedtls_ssl_get_output_max_frag_len(ctx) - + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD; -#endif -} - -static inline size_t mbedtls_ssl_get_input_buflen(const mbedtls_ssl_context *ctx) -{ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - return mbedtls_ssl_get_input_max_frag_len(ctx) - + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD - + MBEDTLS_SSL_CID_IN_LEN_MAX; -#else - return mbedtls_ssl_get_input_max_frag_len(ctx) - + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD; -#endif -} -#endif - -/* - * TLS extension flags (for extensions with outgoing ServerHello content - * that need it (e.g. for RENEGOTIATION_INFO the server already knows because - * of state of the renegotiation flag, so no indicator is required) - */ -#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT (1 << 0) -#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP_OK (1 << 1) - -/** - * \brief This function checks if the remaining size in a buffer is - * greater or equal than a needed space. - * - * \param cur Pointer to the current position in the buffer. - * \param end Pointer to one past the end of the buffer. - * \param need Needed space in bytes. - * - * \return Zero if the needed space is available in the buffer, non-zero - * otherwise. - */ -#if !defined(MBEDTLS_TEST_HOOKS) -static inline int mbedtls_ssl_chk_buf_ptr(const uint8_t *cur, - const uint8_t *end, size_t need) -{ - return (cur > end) || (need > (size_t) (end - cur)); -} -#else -typedef struct { - const uint8_t *cur; - const uint8_t *end; - size_t need; -} mbedtls_ssl_chk_buf_ptr_args; - -void mbedtls_ssl_set_chk_buf_ptr_fail_args( - const uint8_t *cur, const uint8_t *end, size_t need); -void mbedtls_ssl_reset_chk_buf_ptr_fail_args(void); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_cmp_chk_buf_ptr_fail_args(mbedtls_ssl_chk_buf_ptr_args *args); - -static inline int mbedtls_ssl_chk_buf_ptr(const uint8_t *cur, - const uint8_t *end, size_t need) -{ - if ((cur > end) || (need > (size_t) (end - cur))) { - mbedtls_ssl_set_chk_buf_ptr_fail_args(cur, end, need); - return 1; - } - return 0; -} -#endif /* MBEDTLS_TEST_HOOKS */ - -/** - * \brief This macro checks if the remaining size in a buffer is - * greater or equal than a needed space. If it is not the case, - * it returns an SSL_BUFFER_TOO_SMALL error. - * - * \param cur Pointer to the current position in the buffer. - * \param end Pointer to one past the end of the buffer. - * \param need Needed space in bytes. - * - */ -#define MBEDTLS_SSL_CHK_BUF_PTR(cur, end, need) \ - do { \ - if (mbedtls_ssl_chk_buf_ptr((cur), (end), (need)) != 0) \ - { \ - return MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; \ - } \ - } while (0) - -/** - * \brief This macro checks if the remaining length in an input buffer is - * greater or equal than a needed length. If it is not the case, it - * returns #MBEDTLS_ERR_SSL_DECODE_ERROR error and pends a - * #MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR alert message. - * - * This is a function-like macro. It is guaranteed to evaluate each - * argument exactly once. - * - * \param cur Pointer to the current position in the buffer. - * \param end Pointer to one past the end of the buffer. - * \param need Needed length in bytes. - * - */ -#define MBEDTLS_SSL_CHK_BUF_READ_PTR(cur, end, need) \ - do { \ - if (mbedtls_ssl_chk_buf_ptr((cur), (end), (need)) != 0) \ - { \ - MBEDTLS_SSL_DEBUG_MSG(1, \ - ("missing input data in %s", __func__)); \ - MBEDTLS_SSL_PEND_FATAL_ALERT(MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR, \ - MBEDTLS_ERR_SSL_DECODE_ERROR); \ - return MBEDTLS_ERR_SSL_DECODE_ERROR; \ - } \ - } while (0) - -#ifdef __cplusplus -extern "C" { -#endif - -typedef int mbedtls_ssl_tls_prf_cb(const unsigned char *secret, size_t slen, - const char *label, - const unsigned char *random, size_t rlen, - unsigned char *dstbuf, size_t dlen); - -/* cipher.h exports the maximum IV, key and block length from - * all ciphers enabled in the config, regardless of whether those - * ciphers are actually usable in SSL/TLS. Notably, XTS is enabled - * in the default configuration and uses 64 Byte keys, but it is - * not used for record protection in SSL/TLS. - * - * In order to prevent unnecessary inflation of key structures, - * we introduce SSL-specific variants of the max-{key,block,IV} - * macros here which are meant to only take those ciphers into - * account which can be negotiated in SSL/TLS. - * - * Since the current definitions of MBEDTLS_MAX_{KEY|BLOCK|IV}_LENGTH - * in cipher.h are rough overapproximations of the real maxima, here - * we content ourselves with replicating those overapproximations - * for the maximum block and IV length, and excluding XTS from the - * computation of the maximum key length. */ -#define MBEDTLS_SSL_MAX_BLOCK_LENGTH 16 -#define MBEDTLS_SSL_MAX_IV_LENGTH 16 -#define MBEDTLS_SSL_MAX_KEY_LENGTH 32 - -/** - * \brief The data structure holding the cryptographic material (key and IV) - * used for record protection in TLS 1.3. - */ -struct mbedtls_ssl_key_set { - /*! The key for client->server records. */ - unsigned char client_write_key[MBEDTLS_SSL_MAX_KEY_LENGTH]; - /*! The key for server->client records. */ - unsigned char server_write_key[MBEDTLS_SSL_MAX_KEY_LENGTH]; - /*! The IV for client->server records. */ - unsigned char client_write_iv[MBEDTLS_SSL_MAX_IV_LENGTH]; - /*! The IV for server->client records. */ - unsigned char server_write_iv[MBEDTLS_SSL_MAX_IV_LENGTH]; - - size_t key_len; /*!< The length of client_write_key and - * server_write_key, in Bytes. */ - size_t iv_len; /*!< The length of client_write_iv and - * server_write_iv, in Bytes. */ -}; -typedef struct mbedtls_ssl_key_set mbedtls_ssl_key_set; - -typedef struct { - unsigned char binder_key[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char client_early_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char early_exporter_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; -} mbedtls_ssl_tls13_early_secrets; - -typedef struct { - unsigned char client_handshake_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char server_handshake_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; -} mbedtls_ssl_tls13_handshake_secrets; - -/* - * This structure contains the parameters only needed during handshake. - */ -struct mbedtls_ssl_handshake_params { - /* Frequently-used boolean or byte fields (placed early to take - * advantage of smaller code size for indirect access on Arm Thumb) */ - uint8_t resume; /*!< session resume indicator*/ - uint8_t cli_exts; /*!< client extension presence*/ - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) - uint8_t sni_authmode; /*!< authmode from SNI callback */ -#endif - -#if defined(MBEDTLS_SSL_SRV_C) - /* Flag indicating if a CertificateRequest message has been sent - * to the client or not. */ - uint8_t certificate_request_sent; -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_SESSION_TICKETS) - uint8_t new_session_ticket; /*!< use NewSessionTicket? */ -#endif /* MBEDTLS_SSL_SESSION_TICKETS */ - -#if defined(MBEDTLS_SSL_CLI_C) - /** Minimum TLS version to be negotiated. - * - * It is set up in the ClientHello writing preparation stage and used - * throughout the ClientHello writing. Not relevant anymore as soon as - * the protocol version has been negotiated thus as soon as the - * ServerHello is received. - * For a fresh handshake not linked to any previous handshake, it is - * equal to the configured minimum minor version to be negotiated. When - * renegotiating or resuming a session, it is equal to the previously - * negotiated minor version. - * - * There is no maximum TLS version field in this handshake context. - * From the start of the handshake, we need to define a current protocol - * version for the record layer which we define as the maximum TLS - * version to be negotiated. The `tls_version` field of the SSL context is - * used to store this maximum value until it contains the actual - * negotiated value. - */ - mbedtls_ssl_protocol_version min_tls_version; -#endif - -#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) - uint8_t extended_ms; /*!< use Extended Master Secret? */ -#endif - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) - uint8_t async_in_progress; /*!< an asynchronous operation is in progress */ -#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - unsigned char retransmit_state; /*!< Retransmission state */ -#endif - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) - unsigned char group_list_heap_allocated; - unsigned char sig_algs_heap_allocated; -#endif - -#if defined(MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED) - uint8_t ecrs_enabled; /*!< Handshake supports EC restart? */ - enum { /* this complements ssl->state with info on intra-state operations */ - ssl_ecrs_none = 0, /*!< nothing going on (yet) */ - ssl_ecrs_crt_verify, /*!< Certificate: crt_verify() */ - ssl_ecrs_ske_start_processing, /*!< ServerKeyExchange: pk_verify() */ - ssl_ecrs_cke_ecdh_calc_secret, /*!< ClientKeyExchange: ECDH step 2 */ - ssl_ecrs_crt_vrfy_sign, /*!< CertificateVerify: pk_sign() */ - } ecrs_state; /*!< current (or last) operation */ - mbedtls_x509_crt *ecrs_peer_cert; /*!< The peer's CRT chain. */ - size_t ecrs_n; /*!< place for saving a length */ -#endif - - mbedtls_ssl_ciphersuite_t const *ciphersuite_info; - - MBEDTLS_CHECK_RETURN_CRITICAL - int (*update_checksum)(mbedtls_ssl_context *, const unsigned char *, size_t); - MBEDTLS_CHECK_RETURN_CRITICAL - int (*calc_verify)(const mbedtls_ssl_context *, unsigned char *, size_t *); - MBEDTLS_CHECK_RETURN_CRITICAL - int (*calc_finished)(mbedtls_ssl_context *, unsigned char *, int); - mbedtls_ssl_tls_prf_cb *tls_prf; - - /* - * Handshake specific crypto variables - */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - uint8_t key_exchange_mode; /*!< Selected key exchange mode */ - - /** Number of HelloRetryRequest messages received/sent from/to the server. */ - int hello_retry_request_count; - -#if defined(MBEDTLS_SSL_SRV_C) - /** selected_group of key_share extension in HelloRetryRequest message. */ - uint16_t hrr_selected_group; -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) - uint8_t tls13_kex_modes; /*!< Key exchange modes supported by the client */ -#endif -#if defined(MBEDTLS_SSL_SESSION_TICKETS) - uint16_t new_session_tickets_count; /*!< number of session tickets */ -#endif -#endif /* MBEDTLS_SSL_SRV_C */ - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) - uint16_t received_sig_algs[MBEDTLS_RECEIVED_SIG_ALGS_SIZE]; -#endif - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) - const uint16_t *group_list; - const uint16_t *sig_algs; -#endif - -#if defined(MBEDTLS_DHM_C) - mbedtls_dhm_context dhm_ctx; /*!< DHM key exchange */ -#endif - -#if !defined(MBEDTLS_USE_PSA_CRYPTO) && \ - defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) - mbedtls_ecdh_context ecdh_ctx; /*!< ECDH key exchange */ -#endif /* !MBEDTLS_USE_PSA_CRYPTO && - MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED */ - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED) - psa_key_type_t xxdh_psa_type; - size_t xxdh_psa_bits; - mbedtls_svc_key_id_t xxdh_psa_privkey; - uint8_t xxdh_psa_privkey_is_external; - unsigned char xxdh_psa_peerkey[PSA_EXPORT_PUBLIC_KEY_MAX_SIZE]; - size_t xxdh_psa_peerkey_len; -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED */ - -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) -#if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_pake_operation_t psa_pake_ctx; /*!< EC J-PAKE key exchange */ - mbedtls_svc_key_id_t psa_pake_password; - uint8_t psa_pake_ctx_is_ok; -#else - mbedtls_ecjpake_context ecjpake_ctx; /*!< EC J-PAKE key exchange */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ -#if defined(MBEDTLS_SSL_CLI_C) - unsigned char *ecjpake_cache; /*!< Cache for ClientHello ext */ - size_t ecjpake_cache_len; /*!< Length of cached data */ -#endif -#endif /* MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ANY_ALLOWED_ENABLED) || \ - defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) - uint16_t *curves_tls_id; /*!< List of TLS IDs of supported elliptic curves */ -#endif - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) -#if defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_svc_key_id_t psk_opaque; /*!< Opaque PSK from the callback */ - uint8_t psk_opaque_is_internal; -#else - unsigned char *psk; /*!< PSK from the callback */ - size_t psk_len; /*!< Length of PSK from callback */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - uint16_t selected_identity; -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ - -#if defined(MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED) - mbedtls_x509_crt_restart_ctx ecrs_ctx; /*!< restart context */ -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) - mbedtls_ssl_key_cert *key_cert; /*!< chosen key/cert pair (server) */ -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) - mbedtls_ssl_key_cert *sni_key_cert; /*!< key/cert list from SNI */ - mbedtls_x509_crt *sni_ca_chain; /*!< trusted CAs from SNI callback */ - mbedtls_x509_crl *sni_ca_crl; /*!< trusted CAs CRLs from SNI */ -#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_X509_CRT_PARSE_C) && \ - !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) - mbedtls_pk_context peer_pubkey; /*!< The public key from the peer. */ -#endif /* MBEDTLS_X509_CRT_PARSE_C && !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ - - struct { - size_t total_bytes_buffered; /*!< Cumulative size of heap allocated - * buffers used for message buffering. */ - - uint8_t seen_ccs; /*!< Indicates if a CCS message has - * been seen in the current flight. */ - - struct mbedtls_ssl_hs_buffer { - unsigned is_valid : 1; - unsigned is_fragmented : 1; - unsigned is_complete : 1; - unsigned char *data; - size_t data_len; - } hs[MBEDTLS_SSL_MAX_BUFFERED_HS]; - - struct { - unsigned char *data; - size_t len; - unsigned epoch; - } future_record; - - } buffering; - -#if defined(MBEDTLS_SSL_CLI_C) && \ - (defined(MBEDTLS_SSL_PROTO_DTLS) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_3)) - unsigned char *cookie; /*!< HelloVerifyRequest cookie for DTLS - * HelloRetryRequest cookie for TLS 1.3 */ -#if !defined(MBEDTLS_SSL_PROTO_TLS1_3) - /* RFC 6347 page 15 - ... - opaque cookie<0..2^8-1>; - ... - */ - uint8_t cookie_len; -#else - /* RFC 8446 page 39 - ... - opaque cookie<0..2^16-1>; - ... - If TLS1_3 is enabled, the max length is 2^16 - 1 - */ - uint16_t cookie_len; /*!< DTLS: HelloVerifyRequest cookie length - * TLS1_3: HelloRetryRequest cookie length */ -#endif -#endif /* MBEDTLS_SSL_CLI_C && - ( MBEDTLS_SSL_PROTO_DTLS || - MBEDTLS_SSL_PROTO_TLS1_3 ) */ -#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_PROTO_DTLS) - unsigned char cookie_verify_result; /*!< Srv: flag for sending a cookie */ -#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_PROTO_DTLS */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - unsigned int out_msg_seq; /*!< Outgoing handshake sequence number */ - unsigned int in_msg_seq; /*!< Incoming handshake sequence number */ - - uint32_t retransmit_timeout; /*!< Current value of timeout */ - mbedtls_ssl_flight_item *flight; /*!< Current outgoing flight */ - mbedtls_ssl_flight_item *cur_msg; /*!< Current message in flight */ - unsigned char *cur_msg_p; /*!< Position in current message */ - unsigned int in_flight_start_seq; /*!< Minimum message sequence in the - flight being received */ - mbedtls_ssl_transform *alt_transform_out; /*!< Alternative transform for - resending messages */ - unsigned char alt_out_ctr[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /*!< Alternative record epoch/counter - for resending messages */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* The state of CID configuration in this handshake. */ - - uint8_t cid_in_use; /*!< This indicates whether the use of the CID extension - * has been negotiated. Possible values are - * #MBEDTLS_SSL_CID_ENABLED and - * #MBEDTLS_SSL_CID_DISABLED. */ - unsigned char peer_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX]; /*! The peer's CID */ - uint8_t peer_cid_len; /*!< The length of - * \c peer_cid. */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - uint16_t mtu; /*!< Handshake mtu, used to fragment outgoing messages */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* - * Checksum contexts - */ -#if defined(MBEDTLS_MD_CAN_SHA256) -#if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_hash_operation_t fin_sha256_psa; -#else - mbedtls_md_context_t fin_sha256; -#endif -#endif -#if defined(MBEDTLS_MD_CAN_SHA384) -#if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_hash_operation_t fin_sha384_psa; -#else - mbedtls_md_context_t fin_sha384; -#endif -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - uint16_t offered_group_id; /* The NamedGroup value for the group - * that is being used for ephemeral - * key exchange. - * - * On the client: Defaults to the first - * entry in the client's group list, - * but can be overwritten by the HRR. */ -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_CLI_C) - uint8_t client_auth; /*!< used to check if CertificateRequest has been - received from server side. If CertificateRequest - has been received, Certificate and CertificateVerify - should be sent to server */ -#endif /* MBEDTLS_SSL_CLI_C */ - /* - * State-local variables used during the processing - * of a specific handshake state. - */ - union { - /* Outgoing Finished message */ - struct { - uint8_t preparation_done; - - /* Buffer holding digest of the handshake up to - * but excluding the outgoing finished message. */ - unsigned char digest[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - size_t digest_len; - } finished_out; - - /* Incoming Finished message */ - struct { - uint8_t preparation_done; - - /* Buffer holding digest of the handshake up to but - * excluding the peer's incoming finished message. */ - unsigned char digest[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - size_t digest_len; - } finished_in; - - } state_local; - - /* End of state-local variables. */ - - unsigned char randbytes[MBEDTLS_CLIENT_HELLO_RANDOM_LEN + - MBEDTLS_SERVER_HELLO_RANDOM_LEN]; - /*!< random bytes */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - unsigned char premaster[MBEDTLS_PREMASTER_SIZE]; - /*!< premaster secret */ - size_t pmslen; /*!< premaster length */ -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - uint32_t sent_extensions; /*!< extensions sent by endpoint */ - uint32_t received_extensions; /*!< extensions received by endpoint */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) - unsigned char certificate_request_context_len; - unsigned char *certificate_request_context; -#endif - - /** TLS 1.3 transform for encrypted handshake messages. */ - mbedtls_ssl_transform *transform_handshake; - union { - unsigned char early[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char handshake[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - unsigned char app[MBEDTLS_TLS1_3_MD_MAX_SIZE]; - } tls13_master_secrets; - - mbedtls_ssl_tls13_handshake_secrets tls13_hs_secrets; -#if defined(MBEDTLS_SSL_EARLY_DATA) - /** TLS 1.3 transform for early data and handshake messages. */ - mbedtls_ssl_transform *transform_earlydata; -#endif -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) - /** Asynchronous operation context. This field is meant for use by the - * asynchronous operation callbacks (mbedtls_ssl_config::f_async_sign_start, - * mbedtls_ssl_config::f_async_decrypt_start, - * mbedtls_ssl_config::f_async_resume, mbedtls_ssl_config::f_async_cancel). - * The library does not use it internally. */ - void *user_async_ctx; -#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) - const unsigned char *sni_name; /*!< raw SNI */ - size_t sni_name_len; /*!< raw SNI len */ -#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) - const mbedtls_x509_crt *dn_hints; /*!< acceptable client cert issuers */ -#endif -#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ -}; - -typedef struct mbedtls_ssl_hs_buffer mbedtls_ssl_hs_buffer; - -/* - * Representation of decryption/encryption transformations on records - * - * There are the following general types of record transformations: - * - Stream transformations (TLS versions == 1.2 only) - * Transformation adding a MAC and applying a stream-cipher - * to the authenticated message. - * - CBC block cipher transformations ([D]TLS versions == 1.2 only) - * For TLS 1.2, no IV is generated at key extraction time, but every - * encrypted record is explicitly prefixed by the IV with which it was - * encrypted. - * - AEAD transformations ([D]TLS versions == 1.2 only) - * These come in two fundamentally different versions, the first one - * used in TLS 1.2, excluding ChaChaPoly ciphersuites, and the second - * one used for ChaChaPoly ciphersuites in TLS 1.2 as well as for TLS 1.3. - * In the first transformation, the IV to be used for a record is obtained - * as the concatenation of an explicit, static 4-byte IV and the 8-byte - * record sequence number, and explicitly prepending this sequence number - * to the encrypted record. In contrast, in the second transformation - * the IV is obtained by XOR'ing a static IV obtained at key extraction - * time with the 8-byte record sequence number, without prepending the - * latter to the encrypted record. - * - * Additionally, DTLS 1.2 + CID as well as TLS 1.3 use an inner plaintext - * which allows to add flexible length padding and to hide a record's true - * content type. - * - * In addition to type and version, the following parameters are relevant: - * - The symmetric cipher algorithm to be used. - * - The (static) encryption/decryption keys for the cipher. - * - For stream/CBC, the type of message digest to be used. - * - For stream/CBC, (static) encryption/decryption keys for the digest. - * - For AEAD transformations, the size (potentially 0) of an explicit, - * random initialization vector placed in encrypted records. - * - For some transformations (currently AEAD) an implicit IV. It is static - * and (if present) is combined with the explicit IV in a transformation- - * -dependent way (e.g. appending in TLS 1.2 and XOR'ing in TLS 1.3). - * - For stream/CBC, a flag determining the order of encryption and MAC. - * - The details of the transformation depend on the SSL/TLS version. - * - The length of the authentication tag. - * - * The struct below refines this abstract view as follows: - * - The cipher underlying the transformation is managed in - * cipher contexts cipher_ctx_{enc/dec}, which must have the - * same cipher type. The mode of these cipher contexts determines - * the type of the transformation in the sense above: e.g., if - * the type is MBEDTLS_CIPHER_AES_256_CBC resp. MBEDTLS_CIPHER_AES_192_GCM - * then the transformation has type CBC resp. AEAD. - * - The cipher keys are never stored explicitly but - * are maintained within cipher_ctx_{enc/dec}. - * - For stream/CBC transformations, the message digest contexts - * used for the MAC's are stored in md_ctx_{enc/dec}. These contexts - * are unused for AEAD transformations. - * - For stream/CBC transformations, the MAC keys are not stored explicitly - * but maintained within md_ctx_{enc/dec}. - * - The mac_enc and mac_dec fields are unused for EAD transformations. - * - For transformations using an implicit IV maintained within - * the transformation context, its contents are stored within - * iv_{enc/dec}. - * - The value of ivlen indicates the length of the IV. - * This is redundant in case of stream/CBC transformations - * which always use 0 resp. the cipher's block length as the - * IV length, but is needed for AEAD ciphers and may be - * different from the underlying cipher's block length - * in this case. - * - The field fixed_ivlen is nonzero for AEAD transformations only - * and indicates the length of the static part of the IV which is - * constant throughout the communication, and which is stored in - * the first fixed_ivlen bytes of the iv_{enc/dec} arrays. - * - tls_version denotes the 2-byte TLS version - * - For stream/CBC transformations, maclen denotes the length of the - * authentication tag, while taglen is unused and 0. - * - For AEAD transformations, taglen denotes the length of the - * authentication tag, while maclen is unused and 0. - * - For CBC transformations, encrypt_then_mac determines the - * order of encryption and authentication. This field is unused - * in other transformations. - * - */ -struct mbedtls_ssl_transform { - /* - * Session specific crypto layer - */ - size_t minlen; /*!< min. ciphertext length */ - size_t ivlen; /*!< IV length */ - size_t fixed_ivlen; /*!< Fixed part of IV (AEAD) */ - size_t maclen; /*!< MAC(CBC) len */ - size_t taglen; /*!< TAG(AEAD) len */ - - unsigned char iv_enc[16]; /*!< IV (encryption) */ - unsigned char iv_dec[16]; /*!< IV (decryption) */ - -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) - -#if defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_svc_key_id_t psa_mac_enc; /*!< MAC (encryption) */ - mbedtls_svc_key_id_t psa_mac_dec; /*!< MAC (decryption) */ - psa_algorithm_t psa_mac_alg; /*!< psa MAC algorithm */ -#else - mbedtls_md_context_t md_ctx_enc; /*!< MAC (encryption) */ - mbedtls_md_context_t md_ctx_dec; /*!< MAC (decryption) */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - int encrypt_then_mac; /*!< flag for EtM activation */ -#endif - -#endif /* MBEDTLS_SSL_SOME_SUITES_USE_MAC */ - - mbedtls_ssl_protocol_version tls_version; - -#if defined(MBEDTLS_USE_PSA_CRYPTO) - mbedtls_svc_key_id_t psa_key_enc; /*!< psa encryption key */ - mbedtls_svc_key_id_t psa_key_dec; /*!< psa decryption key */ - psa_algorithm_t psa_alg; /*!< psa algorithm */ -#else - mbedtls_cipher_context_t cipher_ctx_enc; /*!< encryption context */ - mbedtls_cipher_context_t cipher_ctx_dec; /*!< decryption context */ -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - uint8_t in_cid_len; - uint8_t out_cid_len; - unsigned char in_cid[MBEDTLS_SSL_CID_IN_LEN_MAX]; - unsigned char out_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX]; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) - /* We need the Hello random bytes in order to re-derive keys from the - * Master Secret and other session info, - * see ssl_tls12_populate_transform() */ - unsigned char randbytes[MBEDTLS_SERVER_HELLO_RANDOM_LEN + - MBEDTLS_CLIENT_HELLO_RANDOM_LEN]; - /*!< ServerHello.random+ClientHello.random */ -#endif /* MBEDTLS_SSL_CONTEXT_SERIALIZATION */ -}; - -/* - * Return 1 if the transform uses an AEAD cipher, 0 otherwise. - * Equivalently, return 0 if a separate MAC is used, 1 otherwise. - */ -static inline int mbedtls_ssl_transform_uses_aead( - const mbedtls_ssl_transform *transform) -{ -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) - return transform->maclen == 0 && transform->taglen != 0; -#else - (void) transform; - return 1; -#endif -} - -/* - * Internal representation of record frames - * - * Instances come in two flavors: - * (1) Encrypted - * These always have data_offset = 0 - * (2) Unencrypted - * These have data_offset set to the amount of - * pre-expansion during record protection. Concretely, - * this is the length of the fixed part of the explicit IV - * used for encryption, or 0 if no explicit IV is used - * (e.g. for stream ciphers). - * - * The reason for the data_offset in the unencrypted case - * is to allow for in-place conversion of an unencrypted to - * an encrypted record. If the offset wasn't included, the - * encrypted content would need to be shifted afterwards to - * make space for the fixed IV. - * - */ -#if MBEDTLS_SSL_CID_OUT_LEN_MAX > MBEDTLS_SSL_CID_IN_LEN_MAX -#define MBEDTLS_SSL_CID_LEN_MAX MBEDTLS_SSL_CID_OUT_LEN_MAX -#else -#define MBEDTLS_SSL_CID_LEN_MAX MBEDTLS_SSL_CID_IN_LEN_MAX -#endif - -typedef struct { - uint8_t ctr[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /* In TLS: The implicit record sequence number. - * In DTLS: The 2-byte epoch followed by - * the 6-byte sequence number. - * This is stored as a raw big endian byte array - * as opposed to a uint64_t because we rarely - * need to perform arithmetic on this, but do - * need it as a Byte array for the purpose of - * MAC computations. */ - uint8_t type; /* The record content type. */ - uint8_t ver[2]; /* SSL/TLS version as present on the wire. - * Convert to internal presentation of versions - * using mbedtls_ssl_read_version() and - * mbedtls_ssl_write_version(). - * Keep wire-format for MAC computations. */ - - unsigned char *buf; /* Memory buffer enclosing the record content */ - size_t buf_len; /* Buffer length */ - size_t data_offset; /* Offset of record content */ - size_t data_len; /* Length of record content */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - uint8_t cid_len; /* Length of the CID (0 if not present) */ - unsigned char cid[MBEDTLS_SSL_CID_LEN_MAX]; /* The CID */ -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ -} mbedtls_record; - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -/* - * List of certificate + private key pairs - */ -struct mbedtls_ssl_key_cert { - mbedtls_x509_crt *cert; /*!< cert */ - mbedtls_pk_context *key; /*!< private key */ - mbedtls_ssl_key_cert *next; /*!< next key/cert pair */ -}; -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) -/* - * List of handshake messages kept around for resending - */ -struct mbedtls_ssl_flight_item { - unsigned char *p; /*!< message, including handshake headers */ - size_t len; /*!< length of p */ - unsigned char type; /*!< type of the message: handshake or CCS */ - mbedtls_ssl_flight_item *next; /*!< next handshake message(s) */ -}; -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -/** - * \brief Given an SSL context and its associated configuration, write the TLS - * 1.2 specific extensions of the ClientHello message. - * - * \param[in] ssl SSL context - * \param[in] buf Base address of the buffer where to write the extensions - * \param[in] end End address of the buffer where to write the extensions - * \param uses_ec Whether one proposed ciphersuite uses an elliptic curve - * (<> 0) or not ( 0 ). - * \param[out] out_len Length of the data written into the buffer \p buf - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls12_write_client_hello_exts(mbedtls_ssl_context *ssl, - unsigned char *buf, - const unsigned char *end, - int uses_ec, - size_t *out_len); -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ - defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) - -/** - * \brief Find the preferred hash for a given signature algorithm. - * - * \param[in] ssl SSL context - * \param[in] sig_alg A signature algorithm identifier as defined in the - * TLS 1.2 SignatureAlgorithm enumeration. - * - * \return The preferred hash algorithm for \p sig_alg. It is a hash algorithm - * identifier as defined in the TLS 1.2 HashAlgorithm enumeration. - */ -unsigned int mbedtls_ssl_tls12_get_preferred_hash_for_sig_alg( - mbedtls_ssl_context *ssl, - unsigned int sig_alg); - -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 && - MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED */ - -/** - * \brief Free referenced items in an SSL transform context and clear - * memory - * - * \param transform SSL transform context - */ -void mbedtls_ssl_transform_free(mbedtls_ssl_transform *transform); - -/** - * \brief Free referenced items in an SSL handshake context and clear - * memory - * - * \param ssl SSL context - */ -void mbedtls_ssl_handshake_free(mbedtls_ssl_context *ssl); - -/* set inbound transform of ssl context */ -void mbedtls_ssl_set_inbound_transform(mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform); - -/* set outbound transform of ssl context */ -void mbedtls_ssl_set_outbound_transform(mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_handshake_client_step(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_handshake_server_step(mbedtls_ssl_context *ssl); -void mbedtls_ssl_handshake_wrapup(mbedtls_ssl_context *ssl); -static inline void mbedtls_ssl_handshake_set_state(mbedtls_ssl_context *ssl, - mbedtls_ssl_states state) -{ - ssl->state = (int) state; -} - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_send_fatal_handshake_failure(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_reset_checksum(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_derive_keys(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_handle_message_type(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_prepare_handshake_record(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_update_handshake_status(mbedtls_ssl_context *ssl); - -/** - * \brief Update record layer - * - * This function roughly separates the implementation - * of the logic of (D)TLS from the implementation - * of the secure transport. - * - * \param ssl The SSL context to use. - * \param update_hs_digest This indicates if the handshake digest - * should be automatically updated in case - * a handshake message is found. - * - * \return 0 or non-zero error code. - * - * \note A clarification on what is called 'record layer' here - * is in order, as many sensible definitions are possible: - * - * The record layer takes as input an untrusted underlying - * transport (stream or datagram) and transforms it into - * a serially multiplexed, secure transport, which - * conceptually provides the following: - * - * (1) Three datagram based, content-agnostic transports - * for handshake, alert and CCS messages. - * (2) One stream- or datagram-based transport - * for application data. - * (3) Functionality for changing the underlying transform - * securing the contents. - * - * The interface to this functionality is given as follows: - * - * a Updating - * [Currently implemented by mbedtls_ssl_read_record] - * - * Check if and on which of the four 'ports' data is pending: - * Nothing, a controlling datagram of type (1), or application - * data (2). In any case data is present, internal buffers - * provide access to the data for the user to process it. - * Consumption of type (1) datagrams is done automatically - * on the next update, invalidating that the internal buffers - * for previous datagrams, while consumption of application - * data (2) is user-controlled. - * - * b Reading of application data - * [Currently manual adaption of ssl->in_offt pointer] - * - * As mentioned in the last paragraph, consumption of data - * is different from the automatic consumption of control - * datagrams (1) because application data is treated as a stream. - * - * c Tracking availability of application data - * [Currently manually through decreasing ssl->in_msglen] - * - * For efficiency and to retain datagram semantics for - * application data in case of DTLS, the record layer - * provides functionality for checking how much application - * data is still available in the internal buffer. - * - * d Changing the transformation securing the communication. - * - * Given an opaque implementation of the record layer in the - * above sense, it should be possible to implement the logic - * of (D)TLS on top of it without the need to know anything - * about the record layer's internals. This is done e.g. - * in all the handshake handling functions, and in the - * application data reading function mbedtls_ssl_read. - * - * \note The above tries to give a conceptual picture of the - * record layer, but the current implementation deviates - * from it in some places. For example, our implementation of - * the update functionality through mbedtls_ssl_read_record - * discards datagrams depending on the current state, which - * wouldn't fall under the record layer's responsibility - * following the above definition. - * - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_read_record(mbedtls_ssl_context *ssl, - unsigned update_hs_digest); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_fetch_input(mbedtls_ssl_context *ssl, size_t nb_want); - -/* - * Write handshake message header - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_start_handshake_msg(mbedtls_ssl_context *ssl, unsigned hs_type, - unsigned char **buf, size_t *buf_len); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_handshake_msg_ext(mbedtls_ssl_context *ssl, - int update_checksum, - int force_flush); -static inline int mbedtls_ssl_write_handshake_msg(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_write_handshake_msg_ext(ssl, 1 /* update checksum */, 1 /* force flush */); -} - -/* - * Write handshake message tail - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_finish_handshake_msg(mbedtls_ssl_context *ssl, - size_t buf_len, size_t msg_len); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_record(mbedtls_ssl_context *ssl, int force_flush); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_flush_output(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_certificate(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_certificate(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_change_cipher_spec(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_change_cipher_spec(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_finished(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_finished(mbedtls_ssl_context *ssl); - -void mbedtls_ssl_optimize_checksum(mbedtls_ssl_context *ssl, - const mbedtls_ssl_ciphersuite_t *ciphersuite_info); - -/* - * Update checksum of handshake messages. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_add_hs_msg_to_checksum(mbedtls_ssl_context *ssl, - unsigned hs_type, - unsigned char const *msg, - size_t msg_len); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_add_hs_hdr_to_checksum(mbedtls_ssl_context *ssl, - unsigned hs_type, - size_t total_hs_len); - -#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) -#if !defined(MBEDTLS_USE_PSA_CRYPTO) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_psk_derive_premaster(mbedtls_ssl_context *ssl, - mbedtls_key_exchange_type_t key_ex); -#endif /* !MBEDTLS_USE_PSA_CRYPTO */ -#endif /* MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) -#if defined(MBEDTLS_SSL_CLI_C) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_conf_has_static_psk(mbedtls_ssl_config const *conf); -#endif -#if defined(MBEDTLS_USE_PSA_CRYPTO) -/** - * Get the first defined opaque PSK by order of precedence: - * 1. handshake PSK set by \c mbedtls_ssl_set_hs_psk_opaque() in the PSK - * callback - * 2. static PSK configured by \c mbedtls_ssl_conf_psk_opaque() - * Return an opaque PSK - */ -static inline mbedtls_svc_key_id_t mbedtls_ssl_get_opaque_psk( - const mbedtls_ssl_context *ssl) -{ - if (!mbedtls_svc_key_id_is_null(ssl->handshake->psk_opaque)) { - return ssl->handshake->psk_opaque; - } - - if (!mbedtls_svc_key_id_is_null(ssl->conf->psk_opaque)) { - return ssl->conf->psk_opaque; - } - - return MBEDTLS_SVC_KEY_ID_INIT; -} -#else -/** - * Get the first defined PSK by order of precedence: - * 1. handshake PSK set by \c mbedtls_ssl_set_hs_psk() in the PSK callback - * 2. static PSK configured by \c mbedtls_ssl_conf_psk() - * Return a code and update the pair (PSK, PSK length) passed to this function - */ -static inline int mbedtls_ssl_get_psk(const mbedtls_ssl_context *ssl, - const unsigned char **psk, size_t *psk_len) -{ - if (ssl->handshake->psk != NULL && ssl->handshake->psk_len > 0) { - *psk = ssl->handshake->psk; - *psk_len = ssl->handshake->psk_len; - } else if (ssl->conf->psk != NULL && ssl->conf->psk_len > 0) { - *psk = ssl->conf->psk; - *psk_len = ssl->conf->psk_len; - } else { - *psk = NULL; - *psk_len = 0; - return MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED; - } - - return 0; -} -#endif /* MBEDTLS_USE_PSA_CRYPTO */ - -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ - -#if defined(MBEDTLS_PK_C) -unsigned char mbedtls_ssl_sig_from_pk(mbedtls_pk_context *pk); -unsigned char mbedtls_ssl_sig_from_pk_alg(mbedtls_pk_type_t type); -mbedtls_pk_type_t mbedtls_ssl_pk_alg_from_sig(unsigned char sig); -#endif - -mbedtls_md_type_t mbedtls_ssl_md_alg_from_hash(unsigned char hash); -unsigned char mbedtls_ssl_hash_from_md_alg(int md); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_set_calc_verify_md(mbedtls_ssl_context *ssl, int md); -#endif - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_check_curve_tls_id(const mbedtls_ssl_context *ssl, uint16_t tls_id); -#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_check_curve(const mbedtls_ssl_context *ssl, mbedtls_ecp_group_id grp_id); -#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ - -/** - * \brief Return PSA EC info for the specified TLS ID. - * - * \param tls_id The TLS ID to look for - * \param type If the TLD ID is supported, then proper \c psa_key_type_t - * value is returned here. Can be NULL. - * \param bits If the TLD ID is supported, then proper bit size is returned - * here. Can be NULL. - * \return PSA_SUCCESS if the TLS ID is supported, - * PSA_ERROR_NOT_SUPPORTED otherwise - * - * \note If either \c family or \c bits parameters are NULL, then - * the corresponding value is not returned. - * The function can be called with both parameters as NULL - * simply to check if a specific TLS ID is supported. - */ -int mbedtls_ssl_get_psa_curve_info_from_tls_id(uint16_t tls_id, - psa_key_type_t *type, - size_t *bits); - -/** - * \brief Return \c mbedtls_ecp_group_id for the specified TLS ID. - * - * \param tls_id The TLS ID to look for - * \return Proper \c mbedtls_ecp_group_id if the TLS ID is supported, - * or MBEDTLS_ECP_DP_NONE otherwise - */ -mbedtls_ecp_group_id mbedtls_ssl_get_ecp_group_id_from_tls_id(uint16_t tls_id); - -/** - * \brief Return TLS ID for the specified \c mbedtls_ecp_group_id. - * - * \param grp_id The \c mbedtls_ecp_group_id ID to look for - * \return Proper TLS ID if the \c mbedtls_ecp_group_id is supported, - * or 0 otherwise - */ -uint16_t mbedtls_ssl_get_tls_id_from_ecp_group_id(mbedtls_ecp_group_id grp_id); - -#if defined(MBEDTLS_DEBUG_C) -/** - * \brief Return EC's name for the specified TLS ID. - * - * \param tls_id The TLS ID to look for - * \return A pointer to a const string with the proper name. If TLS - * ID is not supported, a NULL pointer is returned instead. - */ -const char *mbedtls_ssl_get_curve_name_from_tls_id(uint16_t tls_id); -#endif - -#if defined(MBEDTLS_SSL_DTLS_SRTP) -static inline mbedtls_ssl_srtp_profile mbedtls_ssl_check_srtp_profile_value - (const uint16_t srtp_profile_value) -{ - switch (srtp_profile_value) { - case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: - case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: - case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: - case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: - return srtp_profile_value; - default: break; - } - return MBEDTLS_TLS_SRTP_UNSET; -} -#endif - -#if defined(MBEDTLS_X509_CRT_PARSE_C) -static inline mbedtls_pk_context *mbedtls_ssl_own_key(mbedtls_ssl_context *ssl) -{ - mbedtls_ssl_key_cert *key_cert; - - if (ssl->handshake != NULL && ssl->handshake->key_cert != NULL) { - key_cert = ssl->handshake->key_cert; - } else { - key_cert = ssl->conf->key_cert; - } - - return key_cert == NULL ? NULL : key_cert->key; -} - -static inline mbedtls_x509_crt *mbedtls_ssl_own_cert(mbedtls_ssl_context *ssl) -{ - mbedtls_ssl_key_cert *key_cert; - - if (ssl->handshake != NULL && ssl->handshake->key_cert != NULL) { - key_cert = ssl->handshake->key_cert; - } else { - key_cert = ssl->conf->key_cert; - } - - return key_cert == NULL ? NULL : key_cert->cert; -} - -/* - * Check usage of a certificate wrt extensions: - * keyUsage, extendedKeyUsage (later), and nSCertType (later). - * - * Warning: cert_endpoint is the endpoint of the cert (ie, of our peer when we - * check a cert we received from them)! - * - * Return 0 if everything is OK, -1 if not. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_check_cert_usage(const mbedtls_x509_crt *cert, - const mbedtls_ssl_ciphersuite_t *ciphersuite, - int cert_endpoint, - uint32_t *flags); -#endif /* MBEDTLS_X509_CRT_PARSE_C */ - -void mbedtls_ssl_write_version(unsigned char version[2], int transport, - mbedtls_ssl_protocol_version tls_version); -uint16_t mbedtls_ssl_read_version(const unsigned char version[2], - int transport); - -static inline size_t mbedtls_ssl_in_hdr_len(const mbedtls_ssl_context *ssl) -{ -#if !defined(MBEDTLS_SSL_PROTO_DTLS) - ((void) ssl); -#endif - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { - return 13; - } else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - { - return 5; - } -} - -static inline size_t mbedtls_ssl_out_hdr_len(const mbedtls_ssl_context *ssl) -{ - return (size_t) (ssl->out_iv - ssl->out_hdr); -} - -static inline size_t mbedtls_ssl_hs_hdr_len(const mbedtls_ssl_context *ssl) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { - return 12; - } -#else - ((void) ssl); -#endif - return 4; -} - -#if defined(MBEDTLS_SSL_PROTO_DTLS) -void mbedtls_ssl_send_flight_completed(mbedtls_ssl_context *ssl); -void mbedtls_ssl_recv_flight_completed(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_resend(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_flight_transmit(mbedtls_ssl_context *ssl); -#endif - -/* Visible for testing purposes only */ -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_dtls_replay_check(mbedtls_ssl_context const *ssl); -void mbedtls_ssl_dtls_replay_update(mbedtls_ssl_context *ssl); -#endif - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_session_copy(mbedtls_ssl_session *dst, - const mbedtls_ssl_session *src); - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -/* The hash buffer must have at least MBEDTLS_MD_MAX_SIZE bytes of length. */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_get_key_exchange_md_tls1_2(mbedtls_ssl_context *ssl, - unsigned char *hash, size_t *hashlen, - unsigned char *data, size_t data_len, - mbedtls_md_type_t md_alg); -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -#ifdef __cplusplus -} -#endif - -void mbedtls_ssl_transform_init(mbedtls_ssl_transform *transform); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_encrypt_buf(mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform, - mbedtls_record *rec, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_decrypt_buf(mbedtls_ssl_context const *ssl, - mbedtls_ssl_transform *transform, - mbedtls_record *rec); - -/* Length of the "epoch" field in the record header */ -static inline size_t mbedtls_ssl_ep_len(const mbedtls_ssl_context *ssl) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { - return 2; - } -#else - ((void) ssl); -#endif - return 0; -} - -#if defined(MBEDTLS_SSL_PROTO_DTLS) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_resend_hello_request(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -void mbedtls_ssl_set_timer(mbedtls_ssl_context *ssl, uint32_t millisecs); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_check_timer(mbedtls_ssl_context *ssl); - -void mbedtls_ssl_reset_in_out_pointers(mbedtls_ssl_context *ssl); -void mbedtls_ssl_update_out_pointers(mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform); -void mbedtls_ssl_update_in_pointers(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_session_reset_int(mbedtls_ssl_context *ssl, int partial); -void mbedtls_ssl_session_reset_msg_layer(mbedtls_ssl_context *ssl, - int partial); - -/* - * Send pending alert - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_handle_pending_alert(mbedtls_ssl_context *ssl); - -/* - * Set pending fatal alert flag. - */ -void mbedtls_ssl_pend_fatal_alert(mbedtls_ssl_context *ssl, - unsigned char alert_type, - int alert_reason); - -/* Alias of mbedtls_ssl_pend_fatal_alert */ -#define MBEDTLS_SSL_PEND_FATAL_ALERT(type, user_return_value) \ - mbedtls_ssl_pend_fatal_alert(ssl, type, user_return_value) - -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) -void mbedtls_ssl_dtls_replay_reset(mbedtls_ssl_context *ssl); -#endif - -void mbedtls_ssl_handshake_wrapup_free_hs_transform(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_RENEGOTIATION) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_start_renegotiation(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) -size_t mbedtls_ssl_get_current_mtu(const mbedtls_ssl_context *ssl); -void mbedtls_ssl_buffering_free(mbedtls_ssl_context *ssl); -void mbedtls_ssl_flight_free(mbedtls_ssl_flight_item *flight); -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -/** - * ssl utils functions for checking configuration. - */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) -static inline int mbedtls_ssl_conf_is_tls13_only(const mbedtls_ssl_config *conf) -{ - return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_3 && - conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_3; -} - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -static inline int mbedtls_ssl_conf_is_tls12_only(const mbedtls_ssl_config *conf) -{ - return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_2 && - conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_2; -} - -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -static inline int mbedtls_ssl_conf_is_tls13_enabled(const mbedtls_ssl_config *conf) -{ -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - return conf->min_tls_version <= MBEDTLS_SSL_VERSION_TLS1_3 && - conf->max_tls_version >= MBEDTLS_SSL_VERSION_TLS1_3; -#else - ((void) conf); - return 0; -#endif -} - -static inline int mbedtls_ssl_conf_is_tls12_enabled(const mbedtls_ssl_config *conf) -{ -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - return conf->min_tls_version <= MBEDTLS_SSL_VERSION_TLS1_2 && - conf->max_tls_version >= MBEDTLS_SSL_VERSION_TLS1_2; -#else - ((void) conf); - return 0; -#endif -} - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && defined(MBEDTLS_SSL_PROTO_TLS1_3) -static inline int mbedtls_ssl_conf_is_hybrid_tls12_tls13(const mbedtls_ssl_config *conf) -{ - return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_2 && - conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_3; -} -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 && MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) -extern const uint8_t mbedtls_ssl_tls13_hello_retry_request_magic[ - MBEDTLS_SERVER_HELLO_RANDOM_LEN]; -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_process_finished_message(mbedtls_ssl_context *ssl); -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_finished_message(mbedtls_ssl_context *ssl); -void mbedtls_ssl_tls13_handshake_wrapup(mbedtls_ssl_context *ssl); - -/** - * \brief Given an SSL context and its associated configuration, write the TLS - * 1.3 specific extensions of the ClientHello message. - * - * \param[in] ssl SSL context - * \param[in] buf Base address of the buffer where to write the extensions - * \param[in] end End address of the buffer where to write the extensions - * \param[out] out_len Length of the data written into the buffer \p buf - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_client_hello_exts(mbedtls_ssl_context *ssl, - unsigned char *buf, - unsigned char *end, - size_t *out_len); - -/** - * \brief TLS 1.3 client side state machine entry - * - * \param ssl SSL context - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_handshake_client_step(mbedtls_ssl_context *ssl); - -/** - * \brief TLS 1.3 server side state machine entry - * - * \param ssl SSL context - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_handshake_server_step(mbedtls_ssl_context *ssl); - - -/* - * Helper functions around key exchange modes. - */ -static inline unsigned mbedtls_ssl_conf_tls13_check_kex_modes(mbedtls_ssl_context *ssl, - int kex_mode_mask) -{ - return (ssl->conf->tls13_kex_modes & kex_mode_mask) != 0; -} - -static inline int mbedtls_ssl_conf_tls13_psk_enabled(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK); -} - -static inline int mbedtls_ssl_conf_tls13_psk_ephemeral_enabled(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL); -} - -static inline int mbedtls_ssl_conf_tls13_ephemeral_enabled(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL); -} - -static inline int mbedtls_ssl_conf_tls13_some_ephemeral_enabled(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); -} - -static inline int mbedtls_ssl_conf_tls13_some_psk_enabled(mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); -} - -#if defined(MBEDTLS_SSL_SRV_C) && \ - defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) -/** - * Given a list of key exchange modes, check if at least one of them is - * supported. - * - * \param[in] ssl SSL context - * \param kex_modes_mask Mask of the key exchange modes to check - * - * \return 0 if at least one of the key exchange modes is supported, - * !=0 otherwise. - */ -static inline unsigned mbedtls_ssl_tls13_check_kex_modes(mbedtls_ssl_context *ssl, - int kex_modes_mask) -{ - return (ssl->handshake->tls13_kex_modes & kex_modes_mask) == 0; -} - -static inline int mbedtls_ssl_tls13_psk_enabled(mbedtls_ssl_context *ssl) -{ - return !mbedtls_ssl_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK); -} - -static inline int mbedtls_ssl_tls13_psk_ephemeral_enabled( - mbedtls_ssl_context *ssl) -{ - return !mbedtls_ssl_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL); -} - -static inline int mbedtls_ssl_tls13_ephemeral_enabled(mbedtls_ssl_context *ssl) -{ - return !mbedtls_ssl_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL); -} - -static inline int mbedtls_ssl_tls13_some_ephemeral_enabled(mbedtls_ssl_context *ssl) -{ - return !mbedtls_ssl_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); -} - -static inline int mbedtls_ssl_tls13_some_psk_enabled(mbedtls_ssl_context *ssl) -{ - return !mbedtls_ssl_tls13_check_kex_modes(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); -} -#endif /* MBEDTLS_SSL_SRV_C && - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED */ - -/* - * Helper functions for extensions checking. - */ - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_check_received_extension( - mbedtls_ssl_context *ssl, - int hs_msg_type, - unsigned int received_extension_type, - uint32_t hs_msg_allowed_extensions_mask); - -static inline void mbedtls_ssl_tls13_set_hs_sent_ext_mask( - mbedtls_ssl_context *ssl, unsigned int extension_type) -{ - ssl->handshake->sent_extensions |= - mbedtls_ssl_get_extension_mask(extension_type); -} - -/* - * Helper functions to check the selected key exchange mode. - */ -static inline int mbedtls_ssl_tls13_key_exchange_mode_check( - mbedtls_ssl_context *ssl, int kex_mask) -{ - return (ssl->handshake->key_exchange_mode & kex_mask) != 0; -} - -static inline int mbedtls_ssl_tls13_key_exchange_mode_with_psk( - mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_tls13_key_exchange_mode_check(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); -} - -static inline int mbedtls_ssl_tls13_key_exchange_mode_with_ephemeral( - mbedtls_ssl_context *ssl) -{ - return mbedtls_ssl_tls13_key_exchange_mode_check(ssl, - MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); -} - -/* - * Fetch TLS 1.3 handshake message header - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_fetch_handshake_msg(mbedtls_ssl_context *ssl, - unsigned hs_type, - unsigned char **buf, - size_t *buf_len); - -/** - * \brief Detect if a list of extensions contains a supported_versions - * extension or not. - * - * \param[in] ssl SSL context - * \param[in] buf Address of the first byte of the extensions vector. - * \param[in] end End of the buffer containing the list of extensions. - * \param[out] supported_versions_data If the extension is present, address of - * its first byte of data, NULL otherwise. - * \param[out] supported_versions_data_end If the extension is present, address - * of the first byte immediately - * following the extension data, NULL - * otherwise. - * \return 0 if the list of extensions does not contain a supported_versions - * extension. - * \return 1 if the list of extensions contains a supported_versions - * extension. - * \return A negative value if an error occurred while parsing the - * extensions. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_is_supported_versions_ext_present_in_exts( - mbedtls_ssl_context *ssl, - const unsigned char *buf, const unsigned char *end, - const unsigned char **supported_versions_data, - const unsigned char **supported_versions_data_end); - -/* - * Handler of TLS 1.3 server certificate message - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_process_certificate(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -/* - * Handler of TLS 1.3 write Certificate message - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_certificate(mbedtls_ssl_context *ssl); - -/* - * Handler of TLS 1.3 write Certificate Verify message - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_certificate_verify(mbedtls_ssl_context *ssl); - -#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED */ - -/* - * Generic handler of Certificate Verify - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_process_certificate_verify(mbedtls_ssl_context *ssl); - -/* - * Write of dummy-CCS's for middlebox compatibility - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_change_cipher_spec(mbedtls_ssl_context *ssl); - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_reset_transcript_for_hrr(mbedtls_ssl_context *ssl); - -#if defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_generate_and_write_xxdh_key_exchange( - mbedtls_ssl_context *ssl, - uint16_t named_group, - unsigned char *buf, - unsigned char *end, - size_t *out_len); -#endif /* PSA_WANT_ALG_ECDH || PSA_WANT_ALG_FFDH */ - -#if defined(MBEDTLS_SSL_EARLY_DATA) -int mbedtls_ssl_tls13_write_early_data_ext(mbedtls_ssl_context *ssl, - unsigned char *buf, - const unsigned char *end, - size_t *out_len); -#endif /* MBEDTLS_SSL_EARLY_DATA */ - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) -/* - * Write Signature Algorithm extension - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_sig_alg_ext(mbedtls_ssl_context *ssl, unsigned char *buf, - const unsigned char *end, size_t *out_len); -/* - * Parse TLS Signature Algorithm extension - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_sig_alg_ext(mbedtls_ssl_context *ssl, - const unsigned char *buf, - const unsigned char *end); -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - -/* Get handshake transcript */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_get_handshake_transcript(mbedtls_ssl_context *ssl, - const mbedtls_md_type_t md, - unsigned char *dst, - size_t dst_len, - size_t *olen); - -/* - * Return supported groups. - * - * In future, invocations can be changed to ssl->conf->group_list - * when mbedtls_ssl_conf_curves() is deleted. - * - * ssl->handshake->group_list is either a translation of curve_list to IANA TLS group - * identifiers when mbedtls_ssl_conf_curves() has been used, or a pointer to - * ssl->conf->group_list when mbedtls_ssl_conf_groups() has been more recently invoked. - * - */ -static inline const void *mbedtls_ssl_get_groups(const mbedtls_ssl_context *ssl) -{ - #if defined(MBEDTLS_DEPRECATED_REMOVED) || !defined(MBEDTLS_ECP_C) - return ssl->conf->group_list; - #else - if ((ssl->handshake != NULL) && (ssl->handshake->group_list != NULL)) { - return ssl->handshake->group_list; - } else { - return ssl->conf->group_list; - } - #endif -} - -/* - * Helper functions for NamedGroup. - */ -static inline int mbedtls_ssl_tls12_named_group_is_ecdhe(uint16_t named_group) -{ - /* - * RFC 8422 section 5.1.1 - */ - return named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X25519 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP256R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP384R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP512R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X448 || - /* Below deprecated curves should be removed with notice to users */ - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP192K1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP192R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP224K1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP224R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256K1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1; -} - -static inline int mbedtls_ssl_tls13_named_group_is_ecdhe(uint16_t named_group) -{ - return named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X25519 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1 || - named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X448; -} - -static inline int mbedtls_ssl_tls13_named_group_is_ffdh(uint16_t named_group) -{ - return named_group >= MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE2048 && - named_group <= MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE8192; -} - -static inline int mbedtls_ssl_named_group_is_offered( - const mbedtls_ssl_context *ssl, uint16_t named_group) -{ - const uint16_t *group_list = mbedtls_ssl_get_groups(ssl); - - if (group_list == NULL) { - return 0; - } - - for (; *group_list != 0; group_list++) { - if (*group_list == named_group) { - return 1; - } - } - - return 0; -} - -static inline int mbedtls_ssl_named_group_is_supported(uint16_t named_group) -{ -#if defined(PSA_WANT_ALG_ECDH) - if (mbedtls_ssl_tls13_named_group_is_ecdhe(named_group)) { - if (mbedtls_ssl_get_ecp_group_id_from_tls_id(named_group) != - MBEDTLS_ECP_DP_NONE) { - return 1; - } - } -#endif -#if defined(PSA_WANT_ALG_FFDH) - if (mbedtls_ssl_tls13_named_group_is_ffdh(named_group)) { - return 1; - } -#endif -#if !defined(PSA_WANT_ALG_ECDH) && !defined(PSA_WANT_ALG_FFDH) - (void) named_group; -#endif - return 0; -} - -/* - * Return supported signature algorithms. - * - * In future, invocations can be changed to ssl->conf->sig_algs when - * mbedtls_ssl_conf_sig_hashes() is deleted. - * - * ssl->handshake->sig_algs is either a translation of sig_hashes to IANA TLS - * signature algorithm identifiers when mbedtls_ssl_conf_sig_hashes() has been - * used, or a pointer to ssl->conf->sig_algs when mbedtls_ssl_conf_sig_algs() has - * been more recently invoked. - * - */ -static inline const void *mbedtls_ssl_get_sig_algs( - const mbedtls_ssl_context *ssl) -{ -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) - if (ssl->handshake != NULL && - ssl->handshake->sig_algs_heap_allocated == 1 && - ssl->handshake->sig_algs != NULL) { - return ssl->handshake->sig_algs; - } -#endif - return ssl->conf->sig_algs; - -#else /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - - ((void) ssl); - return NULL; -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ -} - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) -static inline int mbedtls_ssl_sig_alg_is_received(const mbedtls_ssl_context *ssl, - uint16_t own_sig_alg) -{ - const uint16_t *sig_alg = ssl->handshake->received_sig_algs; - if (sig_alg == NULL) { - return 0; - } - - for (; *sig_alg != MBEDTLS_TLS_SIG_NONE; sig_alg++) { - if (*sig_alg == own_sig_alg) { - return 1; - } - } - return 0; -} - -static inline int mbedtls_ssl_tls13_sig_alg_for_cert_verify_is_supported( - const uint16_t sig_alg) -{ - switch (sig_alg) { -#if defined(MBEDTLS_PK_CAN_ECDSA_SOME) -#if defined(PSA_WANT_ALG_SHA_256) && defined(PSA_WANT_ECC_SECP_R1_256) - case MBEDTLS_TLS1_3_SIG_ECDSA_SECP256R1_SHA256: - break; -#endif /* PSA_WANT_ALG_SHA_256 && MBEDTLS_ECP_DP_SECP256R1_ENABLED */ -#if defined(PSA_WANT_ALG_SHA_384) && defined(PSA_WANT_ECC_SECP_R1_384) - case MBEDTLS_TLS1_3_SIG_ECDSA_SECP384R1_SHA384: - break; -#endif /* PSA_WANT_ALG_SHA_384 && MBEDTLS_ECP_DP_SECP384R1_ENABLED */ -#if defined(PSA_WANT_ALG_SHA_512) && defined(PSA_WANT_ECC_SECP_R1_521) - case MBEDTLS_TLS1_3_SIG_ECDSA_SECP521R1_SHA512: - break; -#endif /* PSA_WANT_ALG_SHA_512 && MBEDTLS_ECP_DP_SECP521R1_ENABLED */ -#endif /* MBEDTLS_PK_CAN_ECDSA_SOME */ - -#if defined(MBEDTLS_PKCS1_V21) -#if defined(PSA_WANT_ALG_SHA_256) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256: - break; -#endif /* PSA_WANT_ALG_SHA_256 */ -#if defined(PSA_WANT_ALG_SHA_384) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384: - break; -#endif /* PSA_WANT_ALG_SHA_384 */ -#if defined(PSA_WANT_ALG_SHA_512) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512: - break; -#endif /* PSA_WANT_ALG_SHA_512 */ -#endif /* MBEDTLS_PKCS1_V21 */ - default: - return 0; - } - return 1; - -} - -static inline int mbedtls_ssl_tls13_sig_alg_is_supported( - const uint16_t sig_alg) -{ - switch (sig_alg) { -#if defined(MBEDTLS_PKCS1_V15) -#if defined(MBEDTLS_MD_CAN_SHA256) - case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA256: - break; -#endif /* MBEDTLS_MD_CAN_SHA256 */ -#if defined(MBEDTLS_MD_CAN_SHA384) - case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA384: - break; -#endif /* MBEDTLS_MD_CAN_SHA384 */ -#if defined(MBEDTLS_MD_CAN_SHA512) - case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA512: - break; -#endif /* MBEDTLS_MD_CAN_SHA512 */ -#endif /* MBEDTLS_PKCS1_V15 */ - default: - return mbedtls_ssl_tls13_sig_alg_for_cert_verify_is_supported( - sig_alg); - } - return 1; -} - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_check_sig_alg_cert_key_match(uint16_t sig_alg, - mbedtls_pk_context *key); -#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED */ - -#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) -static inline int mbedtls_ssl_sig_alg_is_offered(const mbedtls_ssl_context *ssl, - uint16_t proposed_sig_alg) -{ - const uint16_t *sig_alg = mbedtls_ssl_get_sig_algs(ssl); - if (sig_alg == NULL) { - return 0; - } - - for (; *sig_alg != MBEDTLS_TLS_SIG_NONE; sig_alg++) { - if (*sig_alg == proposed_sig_alg) { - return 1; - } - } - return 0; -} - -static inline int mbedtls_ssl_get_pk_type_and_md_alg_from_sig_alg( - uint16_t sig_alg, mbedtls_pk_type_t *pk_type, mbedtls_md_type_t *md_alg) -{ - *pk_type = mbedtls_ssl_pk_alg_from_sig(sig_alg & 0xff); - *md_alg = mbedtls_ssl_md_alg_from_hash((sig_alg >> 8) & 0xff); - - if (*pk_type != MBEDTLS_PK_NONE && *md_alg != MBEDTLS_MD_NONE) { - return 0; - } - - switch (sig_alg) { -#if defined(MBEDTLS_PKCS1_V21) -#if defined(MBEDTLS_MD_CAN_SHA256) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256: - *md_alg = MBEDTLS_MD_SHA256; - *pk_type = MBEDTLS_PK_RSASSA_PSS; - break; -#endif /* MBEDTLS_MD_CAN_SHA256 */ -#if defined(MBEDTLS_MD_CAN_SHA384) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384: - *md_alg = MBEDTLS_MD_SHA384; - *pk_type = MBEDTLS_PK_RSASSA_PSS; - break; -#endif /* MBEDTLS_MD_CAN_SHA384 */ -#if defined(MBEDTLS_MD_CAN_SHA512) - case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512: - *md_alg = MBEDTLS_MD_SHA512; - *pk_type = MBEDTLS_PK_RSASSA_PSS; - break; -#endif /* MBEDTLS_MD_CAN_SHA512 */ -#endif /* MBEDTLS_PKCS1_V21 */ - default: - return MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; - } - return 0; -} - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) -static inline int mbedtls_ssl_tls12_sig_alg_is_supported( - const uint16_t sig_alg) -{ - /* High byte is hash */ - unsigned char hash = MBEDTLS_BYTE_1(sig_alg); - unsigned char sig = MBEDTLS_BYTE_0(sig_alg); - - switch (hash) { -#if defined(MBEDTLS_MD_CAN_MD5) - case MBEDTLS_SSL_HASH_MD5: - break; -#endif - -#if defined(MBEDTLS_MD_CAN_SHA1) - case MBEDTLS_SSL_HASH_SHA1: - break; -#endif - -#if defined(MBEDTLS_MD_CAN_SHA224) - case MBEDTLS_SSL_HASH_SHA224: - break; -#endif - -#if defined(MBEDTLS_MD_CAN_SHA256) - case MBEDTLS_SSL_HASH_SHA256: - break; -#endif - -#if defined(MBEDTLS_MD_CAN_SHA384) - case MBEDTLS_SSL_HASH_SHA384: - break; -#endif - -#if defined(MBEDTLS_MD_CAN_SHA512) - case MBEDTLS_SSL_HASH_SHA512: - break; -#endif - - default: - return 0; - } - - switch (sig) { -#if defined(MBEDTLS_RSA_C) - case MBEDTLS_SSL_SIG_RSA: - break; -#endif - -#if defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED) - case MBEDTLS_SSL_SIG_ECDSA: - break; -#endif - - default: - return 0; - } - - return 1; -} -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -static inline int mbedtls_ssl_sig_alg_is_supported( - const mbedtls_ssl_context *ssl, - const uint16_t sig_alg) -{ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - if (ssl->tls_version == MBEDTLS_SSL_VERSION_TLS1_2) { - return mbedtls_ssl_tls12_sig_alg_is_supported(sig_alg); - } -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) - if (ssl->tls_version == MBEDTLS_SSL_VERSION_TLS1_3) { - return mbedtls_ssl_tls13_sig_alg_is_supported(sig_alg); - } -#endif - ((void) ssl); - ((void) sig_alg); - return 0; -} -#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ - -#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) -/* Corresponding PSA algorithm for MBEDTLS_CIPHER_NULL. - * Same value is used for PSA_ALG_CATEGORY_CIPHER, hence it is - * guaranteed to not be a valid PSA algorithm identifier. - */ -#define MBEDTLS_SSL_NULL_CIPHER 0x04000000 - -/** - * \brief Translate mbedtls cipher type/taglen pair to psa: - * algorithm, key type and key size. - * - * \param mbedtls_cipher_type [in] given mbedtls cipher type - * \param taglen [in] given tag length - * 0 - default tag length - * \param alg [out] corresponding PSA alg - * There is no corresponding PSA - * alg for MBEDTLS_CIPHER_NULL, so - * in this case MBEDTLS_SSL_NULL_CIPHER - * is returned via this parameter - * \param key_type [out] corresponding PSA key type - * \param key_size [out] corresponding PSA key size - * - * \return PSA_SUCCESS on success or PSA_ERROR_NOT_SUPPORTED if - * conversion is not supported. - */ -psa_status_t mbedtls_ssl_cipher_to_psa(mbedtls_cipher_type_t mbedtls_cipher_type, - size_t taglen, - psa_algorithm_t *alg, - psa_key_type_t *key_type, - size_t *key_size); - -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -/** - * \brief Convert given PSA status to mbedtls error code. - * - * \param status [in] given PSA status - * - * \return corresponding mbedtls error code - */ -static inline MBEDTLS_DEPRECATED int psa_ssl_status_to_mbedtls(psa_status_t status) -{ - switch (status) { - case PSA_SUCCESS: - return 0; - case PSA_ERROR_INSUFFICIENT_MEMORY: - return MBEDTLS_ERR_SSL_ALLOC_FAILED; - case PSA_ERROR_NOT_SUPPORTED: - return MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; - case PSA_ERROR_INVALID_SIGNATURE: - return MBEDTLS_ERR_SSL_INVALID_MAC; - case PSA_ERROR_INVALID_ARGUMENT: - return MBEDTLS_ERR_SSL_BAD_INPUT_DATA; - case PSA_ERROR_BAD_STATE: - return MBEDTLS_ERR_SSL_INTERNAL_ERROR; - case PSA_ERROR_BUFFER_TOO_SMALL: - return MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; - default: - return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; - } -} -#endif /* !MBEDTLS_DEPRECATED_REMOVED */ -#endif /* MBEDTLS_USE_PSA_CRYPTO || MBEDTLS_SSL_PROTO_TLS1_3 */ - -#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ - defined(MBEDTLS_USE_PSA_CRYPTO) - -typedef enum { - MBEDTLS_ECJPAKE_ROUND_ONE, - MBEDTLS_ECJPAKE_ROUND_TWO -} mbedtls_ecjpake_rounds_t; - -/** - * \brief Parse the provided input buffer for getting the first round - * of key exchange. This code is common between server and client - * - * \param pake_ctx [in] the PAKE's operation/context structure - * \param buf [in] input buffer to parse - * \param len [in] length of the input buffer - * \param round [in] either MBEDTLS_ECJPAKE_ROUND_ONE or - * MBEDTLS_ECJPAKE_ROUND_TWO - * - * \return 0 on success or a negative error code in case of failure - */ -int mbedtls_psa_ecjpake_read_round( - psa_pake_operation_t *pake_ctx, - const unsigned char *buf, - size_t len, mbedtls_ecjpake_rounds_t round); - -/** - * \brief Write the first round of key exchange into the provided output - * buffer. This code is common between server and client - * - * \param pake_ctx [in] the PAKE's operation/context structure - * \param buf [out] the output buffer in which data will be written to - * \param len [in] length of the output buffer - * \param olen [out] the length of the data really written on the buffer - * \param round [in] either MBEDTLS_ECJPAKE_ROUND_ONE or - * MBEDTLS_ECJPAKE_ROUND_TWO - * - * \return 0 on success or a negative error code in case of failure - */ -int mbedtls_psa_ecjpake_write_round( - psa_pake_operation_t *pake_ctx, - unsigned char *buf, - size_t len, size_t *olen, - mbedtls_ecjpake_rounds_t round); - -#endif //MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED && MBEDTLS_USE_PSA_CRYPTO - -/** - * \brief TLS record protection modes - */ -typedef enum { - MBEDTLS_SSL_MODE_STREAM = 0, - MBEDTLS_SSL_MODE_CBC, - MBEDTLS_SSL_MODE_CBC_ETM, - MBEDTLS_SSL_MODE_AEAD -} mbedtls_ssl_mode_t; - -mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_transform( - const mbedtls_ssl_transform *transform); - -#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM) -mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_ciphersuite( - int encrypt_then_mac, - const mbedtls_ssl_ciphersuite_t *suite); -#else -mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_ciphersuite( - const mbedtls_ssl_ciphersuite_t *suite); -#endif /* MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM */ - -#if defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_read_public_xxdhe_share(mbedtls_ssl_context *ssl, - const unsigned char *buf, - size_t buf_len); - -#endif /* PSA_WANT_ALG_ECDH || PSA_WANT_ALG_FFDH */ - -static inline int mbedtls_ssl_tls13_cipher_suite_is_offered( - mbedtls_ssl_context *ssl, int cipher_suite) -{ - const int *ciphersuite_list = ssl->conf->ciphersuite_list; - - /* Check whether we have offered this ciphersuite */ - for (size_t i = 0; ciphersuite_list[i] != 0; i++) { - if (ciphersuite_list[i] == cipher_suite) { - return 1; - } - } - return 0; -} - -/** - * \brief Validate cipher suite against config in SSL context. - * - * \param ssl SSL context - * \param suite_info Cipher suite to validate - * \param min_tls_version Minimal TLS version to accept a cipher suite - * \param max_tls_version Maximal TLS version to accept a cipher suite - * - * \return 0 if valid, negative value otherwise. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_validate_ciphersuite( - const mbedtls_ssl_context *ssl, - const mbedtls_ssl_ciphersuite_t *suite_info, - mbedtls_ssl_protocol_version min_tls_version, - mbedtls_ssl_protocol_version max_tls_version); - -#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_server_name_ext(mbedtls_ssl_context *ssl, - const unsigned char *buf, - const unsigned char *end); -#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ - -#if defined(MBEDTLS_SSL_RECORD_SIZE_LIMIT) -#define MBEDTLS_SSL_RECORD_SIZE_LIMIT_EXTENSION_DATA_LENGTH (2) -#define MBEDTLS_SSL_RECORD_SIZE_LIMIT_MIN (64) - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_parse_record_size_limit_ext(mbedtls_ssl_context *ssl, - const unsigned char *buf, - const unsigned char *end); -#endif /* MBEDTLS_SSL_RECORD_SIZE_LIMIT */ - -#if defined(MBEDTLS_SSL_ALPN) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_parse_alpn_ext(mbedtls_ssl_context *ssl, - const unsigned char *buf, - const unsigned char *end); - - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_write_alpn_ext(mbedtls_ssl_context *ssl, - unsigned char *buf, - unsigned char *end, - size_t *out_len); -#endif /* MBEDTLS_SSL_ALPN */ - -#if defined(MBEDTLS_TEST_HOOKS) -int mbedtls_ssl_check_dtls_clihlo_cookie( - mbedtls_ssl_context *ssl, - const unsigned char *cli_id, size_t cli_id_len, - const unsigned char *in, size_t in_len, - unsigned char *obuf, size_t buf_len, size_t *olen); -#endif - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) -/** - * \brief Given an SSL context and its associated configuration, write the TLS - * 1.3 specific Pre-Shared key extension. - * - * \param[in] ssl SSL context - * \param[in] buf Base address of the buffer where to write the extension - * \param[in] end End address of the buffer where to write the extension - * \param[out] out_len Length in bytes of the Pre-Shared key extension: data - * written into the buffer \p buf by this function plus - * the length of the binders to be written. - * \param[out] binders_len Length of the binders to be written at the end of - * the extension. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_identities_of_pre_shared_key_ext( - mbedtls_ssl_context *ssl, - unsigned char *buf, unsigned char *end, - size_t *out_len, size_t *binders_len); - -/** - * \brief Given an SSL context and its associated configuration, write the TLS - * 1.3 specific Pre-Shared key extension binders at the end of the - * ClientHello. - * - * \param[in] ssl SSL context - * \param[in] buf Base address of the buffer where to write the binders - * \param[in] end End address of the buffer where to write the binders - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_write_binders_of_pre_shared_key_ext( - mbedtls_ssl_context *ssl, - unsigned char *buf, unsigned char *end); -#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED */ - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ - defined(MBEDTLS_SSL_SESSION_TICKETS) && \ - defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \ - defined(MBEDTLS_SSL_CLI_C) -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_session_set_hostname(mbedtls_ssl_session *session, - const char *hostname); -#endif - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) -static inline unsigned int mbedtls_ssl_session_get_ticket_flags( - mbedtls_ssl_session *session, unsigned int flags) -{ - return session->ticket_flags & - (flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); -} - -static inline void mbedtls_ssl_session_set_ticket_flags( - mbedtls_ssl_session *session, unsigned int flags) -{ - session->ticket_flags |= (flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); -} - -static inline void mbedtls_ssl_session_clear_ticket_flags( - mbedtls_ssl_session *session, unsigned int flags) -{ - session->ticket_flags &= ~(flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); -} -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ - -#if defined(MBEDTLS_SSL_CLI_C) && defined(MBEDTLS_SSL_PROTO_TLS1_3) -int mbedtls_ssl_tls13_finalize_client_hello(mbedtls_ssl_context *ssl); -#endif - -#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) - -/** Compute the HMAC of variable-length data with constant flow. - * - * This function computes the HMAC of the concatenation of \p add_data and \p - * data, and does with a code flow and memory access pattern that does not - * depend on \p data_len_secret, but only on \p min_data_len and \p - * max_data_len. In particular, this function always reads exactly \p - * max_data_len bytes from \p data. - * - * \param ctx The HMAC context. It must have keys configured - * with mbedtls_md_hmac_starts() and use one of the - * following hashes: SHA-384, SHA-256, SHA-1 or MD-5. - * It is reset using mbedtls_md_hmac_reset() after - * the computation is complete to prepare for the - * next computation. - * \param add_data The first part of the message whose HMAC is being - * calculated. This must point to a readable buffer - * of \p add_data_len bytes. - * \param add_data_len The length of \p add_data in bytes. - * \param data The buffer containing the second part of the - * message. This must point to a readable buffer - * of \p max_data_len bytes. - * \param data_len_secret The length of the data to process in \p data. - * This must be no less than \p min_data_len and no - * greater than \p max_data_len. - * \param min_data_len The minimal length of the second part of the - * message, read from \p data. - * \param max_data_len The maximal length of the second part of the - * message, read from \p data. - * \param output The HMAC will be written here. This must point to - * a writable buffer of sufficient size to hold the - * HMAC value. - * - * \retval 0 on success. - * \retval #MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED - * The hardware accelerator failed. - */ -#if defined(MBEDTLS_USE_PSA_CRYPTO) -int mbedtls_ct_hmac(mbedtls_svc_key_id_t key, - psa_algorithm_t mac_alg, - const unsigned char *add_data, - size_t add_data_len, - const unsigned char *data, - size_t data_len_secret, - size_t min_data_len, - size_t max_data_len, - unsigned char *output); -#else -int mbedtls_ct_hmac(mbedtls_md_context_t *ctx, - const unsigned char *add_data, - size_t add_data_len, - const unsigned char *data, - size_t data_len_secret, - size_t min_data_len, - size_t max_data_len, - unsigned char *output); -#endif /* defined(MBEDTLS_USE_PSA_CRYPTO) */ -#endif /* MBEDTLS_TEST_HOOKS && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) */ - -#endif /* ssl_misc.h */ +/** + * \file ssl_misc.h + * + * \brief Internal functions shared by the SSL modules + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SSL_MISC_H +#define MBEDTLS_SSL_MISC_H + +#include "mbedtls/build_info.h" + +#include "mbedtls/error.h" + +#include "mbedtls/ssl.h" +#include "mbedtls/cipher.h" + +#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) +#include "psa/crypto.h" +#include "psa_util_internal.h" +#endif + +#if defined(MBEDTLS_MD_CAN_MD5) +#include "mbedtls/md5.h" +#endif + +#if defined(MBEDTLS_MD_CAN_SHA1) +#include "mbedtls/sha1.h" +#endif + +#if defined(MBEDTLS_MD_CAN_SHA256) +#include "mbedtls/sha256.h" +#endif + +#if defined(MBEDTLS_MD_CAN_SHA512) +#include "mbedtls/sha512.h" +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ + !defined(MBEDTLS_USE_PSA_CRYPTO) +#include "mbedtls/ecjpake.h" +#endif + +#include "mbedtls/pk.h" +#include "pk_internal.h" +#include "common.h" + +/* Shorthand for restartable ECC */ +#if defined(MBEDTLS_ECP_RESTARTABLE) && \ + defined(MBEDTLS_SSL_CLI_C) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ + defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) +#define MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED +#endif + +#define MBEDTLS_SSL_INITIAL_HANDSHAKE 0 +#define MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS 1 /* In progress */ +#define MBEDTLS_SSL_RENEGOTIATION_DONE 2 /* Done or aborted */ +#define MBEDTLS_SSL_RENEGOTIATION_PENDING 3 /* Requested (server only) */ + +/* Faked handshake message identity for HelloRetryRequest. */ +#define MBEDTLS_SSL_TLS1_3_HS_HELLO_RETRY_REQUEST (-MBEDTLS_SSL_HS_SERVER_HELLO) + +/* + * Internal identity of handshake extensions + */ +#define MBEDTLS_SSL_EXT_ID_UNRECOGNIZED 0 +#define MBEDTLS_SSL_EXT_ID_SERVERNAME 1 +#define MBEDTLS_SSL_EXT_ID_SERVERNAME_HOSTNAME 1 +#define MBEDTLS_SSL_EXT_ID_MAX_FRAGMENT_LENGTH 2 +#define MBEDTLS_SSL_EXT_ID_STATUS_REQUEST 3 +#define MBEDTLS_SSL_EXT_ID_SUPPORTED_GROUPS 4 +#define MBEDTLS_SSL_EXT_ID_SUPPORTED_ELLIPTIC_CURVES 4 +#define MBEDTLS_SSL_EXT_ID_SIG_ALG 5 +#define MBEDTLS_SSL_EXT_ID_USE_SRTP 6 +#define MBEDTLS_SSL_EXT_ID_HEARTBEAT 7 +#define MBEDTLS_SSL_EXT_ID_ALPN 8 +#define MBEDTLS_SSL_EXT_ID_SCT 9 +#define MBEDTLS_SSL_EXT_ID_CLI_CERT_TYPE 10 +#define MBEDTLS_SSL_EXT_ID_SERV_CERT_TYPE 11 +#define MBEDTLS_SSL_EXT_ID_PADDING 12 +#define MBEDTLS_SSL_EXT_ID_PRE_SHARED_KEY 13 +#define MBEDTLS_SSL_EXT_ID_EARLY_DATA 14 +#define MBEDTLS_SSL_EXT_ID_SUPPORTED_VERSIONS 15 +#define MBEDTLS_SSL_EXT_ID_COOKIE 16 +#define MBEDTLS_SSL_EXT_ID_PSK_KEY_EXCHANGE_MODES 17 +#define MBEDTLS_SSL_EXT_ID_CERT_AUTH 18 +#define MBEDTLS_SSL_EXT_ID_OID_FILTERS 19 +#define MBEDTLS_SSL_EXT_ID_POST_HANDSHAKE_AUTH 20 +#define MBEDTLS_SSL_EXT_ID_SIG_ALG_CERT 21 +#define MBEDTLS_SSL_EXT_ID_KEY_SHARE 22 +#define MBEDTLS_SSL_EXT_ID_TRUNCATED_HMAC 23 +#define MBEDTLS_SSL_EXT_ID_SUPPORTED_POINT_FORMATS 24 +#define MBEDTLS_SSL_EXT_ID_ENCRYPT_THEN_MAC 25 +#define MBEDTLS_SSL_EXT_ID_EXTENDED_MASTER_SECRET 26 +#define MBEDTLS_SSL_EXT_ID_SESSION_TICKET 27 +#define MBEDTLS_SSL_EXT_ID_RECORD_SIZE_LIMIT 28 + +/* Utility for translating IANA extension type. */ +uint32_t mbedtls_ssl_get_extension_id(unsigned int extension_type); +uint32_t mbedtls_ssl_get_extension_mask(unsigned int extension_type); +/* Macros used to define mask constants */ +#define MBEDTLS_SSL_EXT_MASK(id) (1ULL << (MBEDTLS_SSL_EXT_ID_##id)) +/* Reset value of extension mask */ +#define MBEDTLS_SSL_EXT_MASK_NONE 0 + +/* In messages containing extension requests, we should ignore unrecognized + * extensions. In messages containing extension responses, unrecognized + * extensions should result in handshake abortion. Messages containing + * extension requests include ClientHello, CertificateRequest and + * NewSessionTicket. Messages containing extension responses include + * ServerHello, HelloRetryRequest, EncryptedExtensions and Certificate. + * + * RFC 8446 section 4.1.3 + * + * The ServerHello MUST only include extensions which are required to establish + * the cryptographic context and negotiate the protocol version. + * + * RFC 8446 section 4.2 + * + * If an implementation receives an extension which it recognizes and which is + * not specified for the message in which it appears, it MUST abort the handshake + * with an "illegal_parameter" alert. + */ + +/* Extensions that are not recognized by TLS 1.3 */ +#define MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED \ + (MBEDTLS_SSL_EXT_MASK(SUPPORTED_POINT_FORMATS) | \ + MBEDTLS_SSL_EXT_MASK(ENCRYPT_THEN_MAC) | \ + MBEDTLS_SSL_EXT_MASK(EXTENDED_MASTER_SECRET) | \ + MBEDTLS_SSL_EXT_MASK(SESSION_TICKET) | \ + MBEDTLS_SSL_EXT_MASK(TRUNCATED_HMAC) | \ + MBEDTLS_SSL_EXT_MASK(UNRECOGNIZED)) + +/* RFC 8446 section 4.2. Allowed extensions for ClientHello */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CH \ + (MBEDTLS_SSL_EXT_MASK(SERVERNAME) | \ + MBEDTLS_SSL_EXT_MASK(MAX_FRAGMENT_LENGTH) | \ + MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ + MBEDTLS_SSL_EXT_MASK(SUPPORTED_GROUPS) | \ + MBEDTLS_SSL_EXT_MASK(SIG_ALG) | \ + MBEDTLS_SSL_EXT_MASK(USE_SRTP) | \ + MBEDTLS_SSL_EXT_MASK(HEARTBEAT) | \ + MBEDTLS_SSL_EXT_MASK(ALPN) | \ + MBEDTLS_SSL_EXT_MASK(SCT) | \ + MBEDTLS_SSL_EXT_MASK(CLI_CERT_TYPE) | \ + MBEDTLS_SSL_EXT_MASK(SERV_CERT_TYPE) | \ + MBEDTLS_SSL_EXT_MASK(PADDING) | \ + MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ + MBEDTLS_SSL_EXT_MASK(PRE_SHARED_KEY) | \ + MBEDTLS_SSL_EXT_MASK(PSK_KEY_EXCHANGE_MODES) | \ + MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ + MBEDTLS_SSL_EXT_MASK(COOKIE) | \ + MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS) | \ + MBEDTLS_SSL_EXT_MASK(CERT_AUTH) | \ + MBEDTLS_SSL_EXT_MASK(POST_HANDSHAKE_AUTH) | \ + MBEDTLS_SSL_EXT_MASK(SIG_ALG_CERT) | \ + MBEDTLS_SSL_EXT_MASK(RECORD_SIZE_LIMIT) | \ + MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) + +/* RFC 8446 section 4.2. Allowed extensions for EncryptedExtensions */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_EE \ + (MBEDTLS_SSL_EXT_MASK(SERVERNAME) | \ + MBEDTLS_SSL_EXT_MASK(MAX_FRAGMENT_LENGTH) | \ + MBEDTLS_SSL_EXT_MASK(SUPPORTED_GROUPS) | \ + MBEDTLS_SSL_EXT_MASK(USE_SRTP) | \ + MBEDTLS_SSL_EXT_MASK(HEARTBEAT) | \ + MBEDTLS_SSL_EXT_MASK(ALPN) | \ + MBEDTLS_SSL_EXT_MASK(CLI_CERT_TYPE) | \ + MBEDTLS_SSL_EXT_MASK(SERV_CERT_TYPE) | \ + MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ + MBEDTLS_SSL_EXT_MASK(RECORD_SIZE_LIMIT)) + +/* RFC 8446 section 4.2. Allowed extensions for CertificateRequest */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CR \ + (MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ + MBEDTLS_SSL_EXT_MASK(SIG_ALG) | \ + MBEDTLS_SSL_EXT_MASK(SCT) | \ + MBEDTLS_SSL_EXT_MASK(CERT_AUTH) | \ + MBEDTLS_SSL_EXT_MASK(OID_FILTERS) | \ + MBEDTLS_SSL_EXT_MASK(SIG_ALG_CERT) | \ + MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) + +/* RFC 8446 section 4.2. Allowed extensions for Certificate */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_CT \ + (MBEDTLS_SSL_EXT_MASK(STATUS_REQUEST) | \ + MBEDTLS_SSL_EXT_MASK(SCT)) + +/* RFC 8446 section 4.2. Allowed extensions for ServerHello */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_SH \ + (MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ + MBEDTLS_SSL_EXT_MASK(PRE_SHARED_KEY) | \ + MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS)) + +/* RFC 8446 section 4.2. Allowed extensions for HelloRetryRequest */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_HRR \ + (MBEDTLS_SSL_EXT_MASK(KEY_SHARE) | \ + MBEDTLS_SSL_EXT_MASK(COOKIE) | \ + MBEDTLS_SSL_EXT_MASK(SUPPORTED_VERSIONS)) + +/* RFC 8446 section 4.2. Allowed extensions for NewSessionTicket */ +#define MBEDTLS_SSL_TLS1_3_ALLOWED_EXTS_OF_NST \ + (MBEDTLS_SSL_EXT_MASK(EARLY_DATA) | \ + MBEDTLS_SSL_TLS1_3_EXT_MASK_UNRECOGNIZED) + +/* + * Helper macros for function call with return check. + */ +/* + * Exit when return non-zero value + */ +#define MBEDTLS_SSL_PROC_CHK(f) \ + do { \ + ret = (f); \ + if (ret != 0) \ + { \ + goto cleanup; \ + } \ + } while (0) +/* + * Exit when return negative value + */ +#define MBEDTLS_SSL_PROC_CHK_NEG(f) \ + do { \ + ret = (f); \ + if (ret < 0) \ + { \ + goto cleanup; \ + } \ + } while (0) + +/* + * DTLS retransmission states, see RFC 6347 4.2.4 + * + * The SENDING state is merged in PREPARING for initial sends, + * but is distinct for resends. + * + * Note: initial state is wrong for server, but is not used anyway. + */ +#define MBEDTLS_SSL_RETRANS_PREPARING 0 +#define MBEDTLS_SSL_RETRANS_SENDING 1 +#define MBEDTLS_SSL_RETRANS_WAITING 2 +#define MBEDTLS_SSL_RETRANS_FINISHED 3 + +/* + * Allow extra bytes for record, authentication and encryption overhead: + * counter (8) + header (5) + IV(16) + MAC (16-48) + padding (0-256). + */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + +/* This macro determines whether CBC is supported. */ +#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ + (defined(MBEDTLS_AES_C) || \ + defined(MBEDTLS_CAMELLIA_C) || \ + defined(MBEDTLS_ARIA_C) || \ + defined(MBEDTLS_DES_C)) +#define MBEDTLS_SSL_SOME_SUITES_USE_CBC +#endif + +/* This macro determines whether a ciphersuite using a + * stream cipher can be used. */ +#if defined(MBEDTLS_CIPHER_NULL_CIPHER) +#define MBEDTLS_SSL_SOME_SUITES_USE_STREAM +#endif + +/* This macro determines whether the CBC construct used in TLS 1.2 is supported. */ +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) && \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) +#define MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC +#endif + +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_STREAM) || \ + defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) +#define MBEDTLS_SSL_SOME_SUITES_USE_MAC +#endif + +/* This macro determines whether a ciphersuite uses Encrypt-then-MAC with CBC */ +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC) && \ + defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) +#define MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM +#endif + +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) +/* Ciphersuites using HMAC */ +#if defined(MBEDTLS_MD_CAN_SHA384) +#define MBEDTLS_SSL_MAC_ADD 48 /* SHA-384 used for HMAC */ +#elif defined(MBEDTLS_MD_CAN_SHA256) +#define MBEDTLS_SSL_MAC_ADD 32 /* SHA-256 used for HMAC */ +#else +#define MBEDTLS_SSL_MAC_ADD 20 /* SHA-1 used for HMAC */ +#endif +#else /* MBEDTLS_SSL_SOME_SUITES_USE_MAC */ +/* AEAD ciphersuites: GCM and CCM use a 128 bits tag */ +#define MBEDTLS_SSL_MAC_ADD 16 +#endif + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +#define MBEDTLS_SSL_PADDING_ADD 256 +#else +#define MBEDTLS_SSL_PADDING_ADD 0 +#endif + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +#define MBEDTLS_SSL_MAX_CID_EXPANSION MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY +#else +#define MBEDTLS_SSL_MAX_CID_EXPANSION 0 +#endif + +#define MBEDTLS_SSL_PAYLOAD_OVERHEAD (MBEDTLS_MAX_IV_LENGTH + \ + MBEDTLS_SSL_MAC_ADD + \ + MBEDTLS_SSL_PADDING_ADD + \ + MBEDTLS_SSL_MAX_CID_EXPANSION \ + ) + +#define MBEDTLS_SSL_IN_PAYLOAD_LEN (MBEDTLS_SSL_PAYLOAD_OVERHEAD + \ + (MBEDTLS_SSL_IN_CONTENT_LEN)) + +#define MBEDTLS_SSL_OUT_PAYLOAD_LEN (MBEDTLS_SSL_PAYLOAD_OVERHEAD + \ + (MBEDTLS_SSL_OUT_CONTENT_LEN)) + +/* The maximum number of buffered handshake messages. */ +#define MBEDTLS_SSL_MAX_BUFFERED_HS 4 + +/* Maximum length we can advertise as our max content length for + RFC 6066 max_fragment_length extension negotiation purposes + (the lesser of both sizes, if they are unequal.) + */ +#define MBEDTLS_TLS_EXT_ADV_CONTENT_LEN ( \ + (MBEDTLS_SSL_IN_CONTENT_LEN > MBEDTLS_SSL_OUT_CONTENT_LEN) \ + ? (MBEDTLS_SSL_OUT_CONTENT_LEN) \ + : (MBEDTLS_SSL_IN_CONTENT_LEN) \ + ) + +/* Maximum size in bytes of list in signature algorithms ext., RFC 5246/8446 */ +#define MBEDTLS_SSL_MAX_SIG_ALG_LIST_LEN 65534 + +/* Minimum size in bytes of list in signature algorithms ext., RFC 5246/8446 */ +#define MBEDTLS_SSL_MIN_SIG_ALG_LIST_LEN 2 + +/* Maximum size in bytes of list in supported elliptic curve ext., RFC 4492 */ +#define MBEDTLS_SSL_MAX_CURVE_LIST_LEN 65535 + +#define MBEDTLS_RECEIVED_SIG_ALGS_SIZE 20 + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) + +#define MBEDTLS_TLS_SIG_NONE MBEDTLS_TLS1_3_SIG_NONE + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +#define MBEDTLS_SSL_TLS12_SIG_AND_HASH_ALG(sig, hash) ((hash << 8) | sig) +#define MBEDTLS_SSL_TLS12_SIG_ALG_FROM_SIG_AND_HASH_ALG(alg) (alg & 0xFF) +#define MBEDTLS_SSL_TLS12_HASH_ALG_FROM_SIG_AND_HASH_ALG(alg) (alg >> 8) +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + +/* + * Check that we obey the standard's message size bounds + */ + +#if MBEDTLS_SSL_IN_CONTENT_LEN > 16384 +#error "Bad configuration - incoming record content too large." +#endif + +#if MBEDTLS_SSL_OUT_CONTENT_LEN > 16384 +#error "Bad configuration - outgoing record content too large." +#endif + +#if MBEDTLS_SSL_IN_PAYLOAD_LEN > MBEDTLS_SSL_IN_CONTENT_LEN + 2048 +#error "Bad configuration - incoming protected record payload too large." +#endif + +#if MBEDTLS_SSL_OUT_PAYLOAD_LEN > MBEDTLS_SSL_OUT_CONTENT_LEN + 2048 +#error "Bad configuration - outgoing protected record payload too large." +#endif + +/* Calculate buffer sizes */ + +/* Note: Even though the TLS record header is only 5 bytes + long, we're internally using 8 bytes to store the + implicit sequence number. */ +#define MBEDTLS_SSL_HEADER_LEN 13 + +#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +#define MBEDTLS_SSL_IN_BUFFER_LEN \ + ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_IN_PAYLOAD_LEN)) +#else +#define MBEDTLS_SSL_IN_BUFFER_LEN \ + ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_IN_PAYLOAD_LEN) \ + + (MBEDTLS_SSL_CID_IN_LEN_MAX)) +#endif + +#if !defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +#define MBEDTLS_SSL_OUT_BUFFER_LEN \ + ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_OUT_PAYLOAD_LEN)) +#else +#define MBEDTLS_SSL_OUT_BUFFER_LEN \ + ((MBEDTLS_SSL_HEADER_LEN) + (MBEDTLS_SSL_OUT_PAYLOAD_LEN) \ + + (MBEDTLS_SSL_CID_OUT_LEN_MAX)) +#endif + +#define MBEDTLS_CLIENT_HELLO_RANDOM_LEN 32 +#define MBEDTLS_SERVER_HELLO_RANDOM_LEN 32 + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) +/** + * \brief Return the maximum fragment length (payload, in bytes) for + * the output buffer. For the client, this is the configured + * value. For the server, it is the minimum of two - the + * configured value and the negotiated one. + * + * \sa mbedtls_ssl_conf_max_frag_len() + * \sa mbedtls_ssl_get_max_out_record_payload() + * + * \param ssl SSL context + * + * \return Current maximum fragment length for the output buffer. + */ +size_t mbedtls_ssl_get_output_max_frag_len(const mbedtls_ssl_context *ssl); + +/** + * \brief Return the maximum fragment length (payload, in bytes) for + * the input buffer. This is the negotiated maximum fragment + * length, or, if there is none, MBEDTLS_SSL_IN_CONTENT_LEN. + * If it is not defined either, the value is 2^14. This function + * works as its predecessor, \c mbedtls_ssl_get_max_frag_len(). + * + * \sa mbedtls_ssl_conf_max_frag_len() + * \sa mbedtls_ssl_get_max_in_record_payload() + * + * \param ssl SSL context + * + * \return Current maximum fragment length for the output buffer. + */ +size_t mbedtls_ssl_get_input_max_frag_len(const mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ + +#if defined(MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH) +static inline size_t mbedtls_ssl_get_output_buflen(const mbedtls_ssl_context *ctx) +{ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + return mbedtls_ssl_get_output_max_frag_len(ctx) + + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD + + MBEDTLS_SSL_CID_OUT_LEN_MAX; +#else + return mbedtls_ssl_get_output_max_frag_len(ctx) + + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD; +#endif +} + +static inline size_t mbedtls_ssl_get_input_buflen(const mbedtls_ssl_context *ctx) +{ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + return mbedtls_ssl_get_input_max_frag_len(ctx) + + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD + + MBEDTLS_SSL_CID_IN_LEN_MAX; +#else + return mbedtls_ssl_get_input_max_frag_len(ctx) + + MBEDTLS_SSL_HEADER_LEN + MBEDTLS_SSL_PAYLOAD_OVERHEAD; +#endif +} +#endif + +/* + * TLS extension flags (for extensions with outgoing ServerHello content + * that need it (e.g. for RENEGOTIATION_INFO the server already knows because + * of state of the renegotiation flag, so no indicator is required) + */ +#define MBEDTLS_TLS_EXT_SUPPORTED_POINT_FORMATS_PRESENT (1 << 0) +#define MBEDTLS_TLS_EXT_ECJPAKE_KKPP_OK (1 << 1) + +/** + * \brief This function checks if the remaining size in a buffer is + * greater or equal than a needed space. + * + * \param cur Pointer to the current position in the buffer. + * \param end Pointer to one past the end of the buffer. + * \param need Needed space in bytes. + * + * \return Zero if the needed space is available in the buffer, non-zero + * otherwise. + */ +#if !defined(MBEDTLS_TEST_HOOKS) +static inline int mbedtls_ssl_chk_buf_ptr(const uint8_t *cur, + const uint8_t *end, size_t need) +{ + return (cur > end) || (need > (size_t) (end - cur)); +} +#else +typedef struct { + const uint8_t *cur; + const uint8_t *end; + size_t need; +} mbedtls_ssl_chk_buf_ptr_args; + +void mbedtls_ssl_set_chk_buf_ptr_fail_args( + const uint8_t *cur, const uint8_t *end, size_t need); +void mbedtls_ssl_reset_chk_buf_ptr_fail_args(void); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_cmp_chk_buf_ptr_fail_args(mbedtls_ssl_chk_buf_ptr_args *args); + +static inline int mbedtls_ssl_chk_buf_ptr(const uint8_t *cur, + const uint8_t *end, size_t need) +{ + if ((cur > end) || (need > (size_t) (end - cur))) { + mbedtls_ssl_set_chk_buf_ptr_fail_args(cur, end, need); + return 1; + } + return 0; +} +#endif /* MBEDTLS_TEST_HOOKS */ + +/** + * \brief This macro checks if the remaining size in a buffer is + * greater or equal than a needed space. If it is not the case, + * it returns an SSL_BUFFER_TOO_SMALL error. + * + * \param cur Pointer to the current position in the buffer. + * \param end Pointer to one past the end of the buffer. + * \param need Needed space in bytes. + * + */ +#define MBEDTLS_SSL_CHK_BUF_PTR(cur, end, need) \ + do { \ + if (mbedtls_ssl_chk_buf_ptr((cur), (end), (need)) != 0) \ + { \ + return MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; \ + } \ + } while (0) + +/** + * \brief This macro checks if the remaining length in an input buffer is + * greater or equal than a needed length. If it is not the case, it + * returns #MBEDTLS_ERR_SSL_DECODE_ERROR error and pends a + * #MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR alert message. + * + * This is a function-like macro. It is guaranteed to evaluate each + * argument exactly once. + * + * \param cur Pointer to the current position in the buffer. + * \param end Pointer to one past the end of the buffer. + * \param need Needed length in bytes. + * + */ +#define MBEDTLS_SSL_CHK_BUF_READ_PTR(cur, end, need) \ + do { \ + if (mbedtls_ssl_chk_buf_ptr((cur), (end), (need)) != 0) \ + { \ + MBEDTLS_SSL_DEBUG_MSG(1, \ + ("missing input data in %s", __func__)); \ + MBEDTLS_SSL_PEND_FATAL_ALERT(MBEDTLS_SSL_ALERT_MSG_DECODE_ERROR, \ + MBEDTLS_ERR_SSL_DECODE_ERROR); \ + return MBEDTLS_ERR_SSL_DECODE_ERROR; \ + } \ + } while (0) + +#ifdef __cplusplus +extern "C" { +#endif + +typedef int mbedtls_ssl_tls_prf_cb(const unsigned char *secret, size_t slen, + const char *label, + const unsigned char *random, size_t rlen, + unsigned char *dstbuf, size_t dlen); + +/* cipher.h exports the maximum IV, key and block length from + * all ciphers enabled in the config, regardless of whether those + * ciphers are actually usable in SSL/TLS. Notably, XTS is enabled + * in the default configuration and uses 64 Byte keys, but it is + * not used for record protection in SSL/TLS. + * + * In order to prevent unnecessary inflation of key structures, + * we introduce SSL-specific variants of the max-{key,block,IV} + * macros here which are meant to only take those ciphers into + * account which can be negotiated in SSL/TLS. + * + * Since the current definitions of MBEDTLS_MAX_{KEY|BLOCK|IV}_LENGTH + * in cipher.h are rough overapproximations of the real maxima, here + * we content ourselves with replicating those overapproximations + * for the maximum block and IV length, and excluding XTS from the + * computation of the maximum key length. */ +#define MBEDTLS_SSL_MAX_BLOCK_LENGTH 16 +#define MBEDTLS_SSL_MAX_IV_LENGTH 16 +#define MBEDTLS_SSL_MAX_KEY_LENGTH 32 + +/** + * \brief The data structure holding the cryptographic material (key and IV) + * used for record protection in TLS 1.3. + */ +struct mbedtls_ssl_key_set { + /*! The key for client->server records. */ + unsigned char client_write_key[MBEDTLS_SSL_MAX_KEY_LENGTH]; + /*! The key for server->client records. */ + unsigned char server_write_key[MBEDTLS_SSL_MAX_KEY_LENGTH]; + /*! The IV for client->server records. */ + unsigned char client_write_iv[MBEDTLS_SSL_MAX_IV_LENGTH]; + /*! The IV for server->client records. */ + unsigned char server_write_iv[MBEDTLS_SSL_MAX_IV_LENGTH]; + + size_t key_len; /*!< The length of client_write_key and + * server_write_key, in Bytes. */ + size_t iv_len; /*!< The length of client_write_iv and + * server_write_iv, in Bytes. */ +}; +typedef struct mbedtls_ssl_key_set mbedtls_ssl_key_set; + +typedef struct { + unsigned char binder_key[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char client_early_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char early_exporter_master_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; +} mbedtls_ssl_tls13_early_secrets; + +typedef struct { + unsigned char client_handshake_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char server_handshake_traffic_secret[MBEDTLS_TLS1_3_MD_MAX_SIZE]; +} mbedtls_ssl_tls13_handshake_secrets; + +/* + * This structure contains the parameters only needed during handshake. + */ +struct mbedtls_ssl_handshake_params { + /* Frequently-used boolean or byte fields (placed early to take + * advantage of smaller code size for indirect access on Arm Thumb) */ + uint8_t resume; /*!< session resume indicator*/ + uint8_t cli_exts; /*!< client extension presence*/ + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) + uint8_t sni_authmode; /*!< authmode from SNI callback */ +#endif + +#if defined(MBEDTLS_SSL_SRV_C) + /* Flag indicating if a CertificateRequest message has been sent + * to the client or not. */ + uint8_t certificate_request_sent; +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_SESSION_TICKETS) + uint8_t new_session_ticket; /*!< use NewSessionTicket? */ +#endif /* MBEDTLS_SSL_SESSION_TICKETS */ + +#if defined(MBEDTLS_SSL_CLI_C) + /** Minimum TLS version to be negotiated. + * + * It is set up in the ClientHello writing preparation stage and used + * throughout the ClientHello writing. Not relevant anymore as soon as + * the protocol version has been negotiated thus as soon as the + * ServerHello is received. + * For a fresh handshake not linked to any previous handshake, it is + * equal to the configured minimum minor version to be negotiated. When + * renegotiating or resuming a session, it is equal to the previously + * negotiated minor version. + * + * There is no maximum TLS version field in this handshake context. + * From the start of the handshake, we need to define a current protocol + * version for the record layer which we define as the maximum TLS + * version to be negotiated. The `tls_version` field of the SSL context is + * used to store this maximum value until it contains the actual + * negotiated value. + */ + mbedtls_ssl_protocol_version min_tls_version; +#endif + +#if defined(MBEDTLS_SSL_EXTENDED_MASTER_SECRET) + uint8_t extended_ms; /*!< use Extended Master Secret? */ +#endif + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) + uint8_t async_in_progress; /*!< an asynchronous operation is in progress */ +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + unsigned char retransmit_state; /*!< Retransmission state */ +#endif + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + unsigned char group_list_heap_allocated; + unsigned char sig_algs_heap_allocated; +#endif + +#if defined(MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED) + uint8_t ecrs_enabled; /*!< Handshake supports EC restart? */ + enum { /* this complements ssl->state with info on intra-state operations */ + ssl_ecrs_none = 0, /*!< nothing going on (yet) */ + ssl_ecrs_crt_verify, /*!< Certificate: crt_verify() */ + ssl_ecrs_ske_start_processing, /*!< ServerKeyExchange: pk_verify() */ + ssl_ecrs_cke_ecdh_calc_secret, /*!< ClientKeyExchange: ECDH step 2 */ + ssl_ecrs_crt_vrfy_sign, /*!< CertificateVerify: pk_sign() */ + } ecrs_state; /*!< current (or last) operation */ + mbedtls_x509_crt *ecrs_peer_cert; /*!< The peer's CRT chain. */ + size_t ecrs_n; /*!< place for saving a length */ +#endif + + mbedtls_ssl_ciphersuite_t const *ciphersuite_info; + + MBEDTLS_CHECK_RETURN_CRITICAL + int (*update_checksum)(mbedtls_ssl_context *, const unsigned char *, size_t); + MBEDTLS_CHECK_RETURN_CRITICAL + int (*calc_verify)(const mbedtls_ssl_context *, unsigned char *, size_t *); + MBEDTLS_CHECK_RETURN_CRITICAL + int (*calc_finished)(mbedtls_ssl_context *, unsigned char *, int); + mbedtls_ssl_tls_prf_cb *tls_prf; + + /* + * Handshake specific crypto variables + */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + uint8_t key_exchange_mode; /*!< Selected key exchange mode */ + + /** Number of HelloRetryRequest messages received/sent from/to the server. */ + int hello_retry_request_count; + +#if defined(MBEDTLS_SSL_SRV_C) + /** selected_group of key_share extension in HelloRetryRequest message. */ + uint16_t hrr_selected_group; +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) + uint8_t tls13_kex_modes; /*!< Key exchange modes supported by the client */ +#endif +#if defined(MBEDTLS_SSL_SESSION_TICKETS) + uint16_t new_session_tickets_count; /*!< number of session tickets */ +#endif +#endif /* MBEDTLS_SSL_SRV_C */ + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) + uint16_t received_sig_algs[MBEDTLS_RECEIVED_SIG_ALGS_SIZE]; +#endif + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + const uint16_t *group_list; + const uint16_t *sig_algs; +#endif + +#if defined(MBEDTLS_DHM_C) + mbedtls_dhm_context dhm_ctx; /*!< DHM key exchange */ +#endif + +#if !defined(MBEDTLS_USE_PSA_CRYPTO) && \ + defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED) + mbedtls_ecdh_context ecdh_ctx; /*!< ECDH key exchange */ +#endif /* !MBEDTLS_USE_PSA_CRYPTO && + MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_1_2_ENABLED */ + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED) + psa_key_type_t xxdh_psa_type; + size_t xxdh_psa_bits; + mbedtls_svc_key_id_t xxdh_psa_privkey; + uint8_t xxdh_psa_privkey_is_external; + unsigned char xxdh_psa_peerkey[PSA_EXPORT_PUBLIC_KEY_MAX_SIZE]; + size_t xxdh_psa_peerkey_len; +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_XXDH_PSA_ANY_ENABLED */ + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) +#if defined(MBEDTLS_USE_PSA_CRYPTO) + psa_pake_operation_t psa_pake_ctx; /*!< EC J-PAKE key exchange */ + mbedtls_svc_key_id_t psa_pake_password; + uint8_t psa_pake_ctx_is_ok; +#else + mbedtls_ecjpake_context ecjpake_ctx; /*!< EC J-PAKE key exchange */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(MBEDTLS_SSL_CLI_C) + unsigned char *ecjpake_cache; /*!< Cache for ClientHello ext */ + size_t ecjpake_cache_len; /*!< Length of cached data */ +#endif +#endif /* MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED */ + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_ECDH_OR_ECDHE_ANY_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ANY_ALLOWED_ENABLED) || \ + defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) + uint16_t *curves_tls_id; /*!< List of TLS IDs of supported elliptic curves */ +#endif + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) +#if defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_svc_key_id_t psk_opaque; /*!< Opaque PSK from the callback */ + uint8_t psk_opaque_is_internal; +#else + unsigned char *psk; /*!< PSK from the callback */ + size_t psk_len; /*!< Length of PSK from callback */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + uint16_t selected_identity; +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ + +#if defined(MBEDTLS_SSL_ECP_RESTARTABLE_ENABLED) + mbedtls_x509_crt_restart_ctx ecrs_ctx; /*!< restart context */ +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) + mbedtls_ssl_key_cert *key_cert; /*!< chosen key/cert pair (server) */ +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) + mbedtls_ssl_key_cert *sni_key_cert; /*!< key/cert list from SNI */ + mbedtls_x509_crt *sni_ca_chain; /*!< trusted CAs from SNI callback */ + mbedtls_x509_crl *sni_ca_crl; /*!< trusted CAs CRLs from SNI */ +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_X509_CRT_PARSE_C) && \ + !defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) + mbedtls_pk_context peer_pubkey; /*!< The public key from the peer. */ +#endif /* MBEDTLS_X509_CRT_PARSE_C && !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ + + struct { + size_t total_bytes_buffered; /*!< Cumulative size of heap allocated + * buffers used for message buffering. */ + + uint8_t seen_ccs; /*!< Indicates if a CCS message has + * been seen in the current flight. */ + + struct mbedtls_ssl_hs_buffer { + unsigned is_valid : 1; + unsigned is_fragmented : 1; + unsigned is_complete : 1; + unsigned char *data; + size_t data_len; + } hs[MBEDTLS_SSL_MAX_BUFFERED_HS]; + + struct { + unsigned char *data; + size_t len; + unsigned epoch; + } future_record; + + } buffering; + +#if defined(MBEDTLS_SSL_CLI_C) && \ + (defined(MBEDTLS_SSL_PROTO_DTLS) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_3)) + unsigned char *cookie; /*!< HelloVerifyRequest cookie for DTLS + * HelloRetryRequest cookie for TLS 1.3 */ +#if !defined(MBEDTLS_SSL_PROTO_TLS1_3) + /* RFC 6347 page 15 + ... + opaque cookie<0..2^8-1>; + ... + */ + uint8_t cookie_len; +#else + /* RFC 8446 page 39 + ... + opaque cookie<0..2^16-1>; + ... + If TLS1_3 is enabled, the max length is 2^16 - 1 + */ + uint16_t cookie_len; /*!< DTLS: HelloVerifyRequest cookie length + * TLS1_3: HelloRetryRequest cookie length */ +#endif +#endif /* MBEDTLS_SSL_CLI_C && + ( MBEDTLS_SSL_PROTO_DTLS || + MBEDTLS_SSL_PROTO_TLS1_3 ) */ +#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_PROTO_DTLS) + unsigned char cookie_verify_result; /*!< Srv: flag for sending a cookie */ +#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + unsigned int out_msg_seq; /*!< Outgoing handshake sequence number */ + unsigned int in_msg_seq; /*!< Incoming handshake sequence number */ + + uint32_t retransmit_timeout; /*!< Current value of timeout */ + mbedtls_ssl_flight_item *flight; /*!< Current outgoing flight */ + mbedtls_ssl_flight_item *cur_msg; /*!< Current message in flight */ + unsigned char *cur_msg_p; /*!< Position in current message */ + unsigned int in_flight_start_seq; /*!< Minimum message sequence in the + flight being received */ + mbedtls_ssl_transform *alt_transform_out; /*!< Alternative transform for + resending messages */ + unsigned char alt_out_ctr[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /*!< Alternative record epoch/counter + for resending messages */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* The state of CID configuration in this handshake. */ + + uint8_t cid_in_use; /*!< This indicates whether the use of the CID extension + * has been negotiated. Possible values are + * #MBEDTLS_SSL_CID_ENABLED and + * #MBEDTLS_SSL_CID_DISABLED. */ + unsigned char peer_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX]; /*! The peer's CID */ + uint8_t peer_cid_len; /*!< The length of + * \c peer_cid. */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + uint16_t mtu; /*!< Handshake mtu, used to fragment outgoing messages */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* + * Checksum contexts + */ +#if defined(MBEDTLS_MD_CAN_SHA256) +#if defined(MBEDTLS_USE_PSA_CRYPTO) + psa_hash_operation_t fin_sha256_psa; +#else + mbedtls_md_context_t fin_sha256; +#endif +#endif +#if defined(MBEDTLS_MD_CAN_SHA384) +#if defined(MBEDTLS_USE_PSA_CRYPTO) + psa_hash_operation_t fin_sha384_psa; +#else + mbedtls_md_context_t fin_sha384; +#endif +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + uint16_t offered_group_id; /* The NamedGroup value for the group + * that is being used for ephemeral + * key exchange. + * + * On the client: Defaults to the first + * entry in the client's group list, + * but can be overwritten by the HRR. */ +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_CLI_C) + uint8_t client_auth; /*!< used to check if CertificateRequest has been + received from server side. If CertificateRequest + has been received, Certificate and CertificateVerify + should be sent to server */ +#endif /* MBEDTLS_SSL_CLI_C */ + /* + * State-local variables used during the processing + * of a specific handshake state. + */ + union { + /* Outgoing Finished message */ + struct { + uint8_t preparation_done; + + /* Buffer holding digest of the handshake up to + * but excluding the outgoing finished message. */ + unsigned char digest[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + size_t digest_len; + } finished_out; + + /* Incoming Finished message */ + struct { + uint8_t preparation_done; + + /* Buffer holding digest of the handshake up to but + * excluding the peer's incoming finished message. */ + unsigned char digest[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + size_t digest_len; + } finished_in; + + } state_local; + + /* End of state-local variables. */ + + unsigned char randbytes[MBEDTLS_CLIENT_HELLO_RANDOM_LEN + + MBEDTLS_SERVER_HELLO_RANDOM_LEN]; + /*!< random bytes */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + unsigned char premaster[MBEDTLS_PREMASTER_SIZE]; + /*!< premaster secret */ + size_t pmslen; /*!< premaster length */ +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + uint32_t sent_extensions; /*!< extensions sent by endpoint */ + uint32_t received_extensions; /*!< extensions received by endpoint */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) + unsigned char certificate_request_context_len; + unsigned char *certificate_request_context; +#endif + + /** TLS 1.3 transform for encrypted handshake messages. */ + mbedtls_ssl_transform *transform_handshake; + union { + unsigned char early[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char handshake[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + unsigned char app[MBEDTLS_TLS1_3_MD_MAX_SIZE]; + } tls13_master_secrets; + + mbedtls_ssl_tls13_handshake_secrets tls13_hs_secrets; +#if defined(MBEDTLS_SSL_EARLY_DATA) + /** TLS 1.3 transform for early data and handshake messages. */ + mbedtls_ssl_transform *transform_earlydata; +#endif +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_ASYNC_PRIVATE) + /** Asynchronous operation context. This field is meant for use by the + * asynchronous operation callbacks (mbedtls_ssl_config::f_async_sign_start, + * mbedtls_ssl_config::f_async_decrypt_start, + * mbedtls_ssl_config::f_async_resume, mbedtls_ssl_config::f_async_cancel). + * The library does not use it internally. */ + void *user_async_ctx; +#endif /* MBEDTLS_SSL_ASYNC_PRIVATE */ + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) + const unsigned char *sni_name; /*!< raw SNI */ + size_t sni_name_len; /*!< raw SNI len */ +#if defined(MBEDTLS_KEY_EXCHANGE_CERT_REQ_ALLOWED_ENABLED) + const mbedtls_x509_crt *dn_hints; /*!< acceptable client cert issuers */ +#endif +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ +}; + +typedef struct mbedtls_ssl_hs_buffer mbedtls_ssl_hs_buffer; + +/* + * Representation of decryption/encryption transformations on records + * + * There are the following general types of record transformations: + * - Stream transformations (TLS versions == 1.2 only) + * Transformation adding a MAC and applying a stream-cipher + * to the authenticated message. + * - CBC block cipher transformations ([D]TLS versions == 1.2 only) + * For TLS 1.2, no IV is generated at key extraction time, but every + * encrypted record is explicitly prefixed by the IV with which it was + * encrypted. + * - AEAD transformations ([D]TLS versions == 1.2 only) + * These come in two fundamentally different versions, the first one + * used in TLS 1.2, excluding ChaChaPoly ciphersuites, and the second + * one used for ChaChaPoly ciphersuites in TLS 1.2 as well as for TLS 1.3. + * In the first transformation, the IV to be used for a record is obtained + * as the concatenation of an explicit, static 4-byte IV and the 8-byte + * record sequence number, and explicitly prepending this sequence number + * to the encrypted record. In contrast, in the second transformation + * the IV is obtained by XOR'ing a static IV obtained at key extraction + * time with the 8-byte record sequence number, without prepending the + * latter to the encrypted record. + * + * Additionally, DTLS 1.2 + CID as well as TLS 1.3 use an inner plaintext + * which allows to add flexible length padding and to hide a record's true + * content type. + * + * In addition to type and version, the following parameters are relevant: + * - The symmetric cipher algorithm to be used. + * - The (static) encryption/decryption keys for the cipher. + * - For stream/CBC, the type of message digest to be used. + * - For stream/CBC, (static) encryption/decryption keys for the digest. + * - For AEAD transformations, the size (potentially 0) of an explicit, + * random initialization vector placed in encrypted records. + * - For some transformations (currently AEAD) an implicit IV. It is static + * and (if present) is combined with the explicit IV in a transformation- + * -dependent way (e.g. appending in TLS 1.2 and XOR'ing in TLS 1.3). + * - For stream/CBC, a flag determining the order of encryption and MAC. + * - The details of the transformation depend on the SSL/TLS version. + * - The length of the authentication tag. + * + * The struct below refines this abstract view as follows: + * - The cipher underlying the transformation is managed in + * cipher contexts cipher_ctx_{enc/dec}, which must have the + * same cipher type. The mode of these cipher contexts determines + * the type of the transformation in the sense above: e.g., if + * the type is MBEDTLS_CIPHER_AES_256_CBC resp. MBEDTLS_CIPHER_AES_192_GCM + * then the transformation has type CBC resp. AEAD. + * - The cipher keys are never stored explicitly but + * are maintained within cipher_ctx_{enc/dec}. + * - For stream/CBC transformations, the message digest contexts + * used for the MAC's are stored in md_ctx_{enc/dec}. These contexts + * are unused for AEAD transformations. + * - For stream/CBC transformations, the MAC keys are not stored explicitly + * but maintained within md_ctx_{enc/dec}. + * - The mac_enc and mac_dec fields are unused for EAD transformations. + * - For transformations using an implicit IV maintained within + * the transformation context, its contents are stored within + * iv_{enc/dec}. + * - The value of ivlen indicates the length of the IV. + * This is redundant in case of stream/CBC transformations + * which always use 0 resp. the cipher's block length as the + * IV length, but is needed for AEAD ciphers and may be + * different from the underlying cipher's block length + * in this case. + * - The field fixed_ivlen is nonzero for AEAD transformations only + * and indicates the length of the static part of the IV which is + * constant throughout the communication, and which is stored in + * the first fixed_ivlen bytes of the iv_{enc/dec} arrays. + * - tls_version denotes the 2-byte TLS version + * - For stream/CBC transformations, maclen denotes the length of the + * authentication tag, while taglen is unused and 0. + * - For AEAD transformations, taglen denotes the length of the + * authentication tag, while maclen is unused and 0. + * - For CBC transformations, encrypt_then_mac determines the + * order of encryption and authentication. This field is unused + * in other transformations. + * + */ +struct mbedtls_ssl_transform { + /* + * Session specific crypto layer + */ + size_t minlen; /*!< min. ciphertext length */ + size_t ivlen; /*!< IV length */ + size_t fixed_ivlen; /*!< Fixed part of IV (AEAD) */ + size_t maclen; /*!< MAC(CBC) len */ + size_t taglen; /*!< TAG(AEAD) len */ + + unsigned char iv_enc[16]; /*!< IV (encryption) */ + unsigned char iv_dec[16]; /*!< IV (decryption) */ + +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) + +#if defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_svc_key_id_t psa_mac_enc; /*!< MAC (encryption) */ + mbedtls_svc_key_id_t psa_mac_dec; /*!< MAC (decryption) */ + psa_algorithm_t psa_mac_alg; /*!< psa MAC algorithm */ +#else + mbedtls_md_context_t md_ctx_enc; /*!< MAC (encryption) */ + mbedtls_md_context_t md_ctx_dec; /*!< MAC (decryption) */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + int encrypt_then_mac; /*!< flag for EtM activation */ +#endif + +#endif /* MBEDTLS_SSL_SOME_SUITES_USE_MAC */ + + mbedtls_ssl_protocol_version tls_version; + +#if defined(MBEDTLS_USE_PSA_CRYPTO) + mbedtls_svc_key_id_t psa_key_enc; /*!< psa encryption key */ + mbedtls_svc_key_id_t psa_key_dec; /*!< psa decryption key */ + psa_algorithm_t psa_alg; /*!< psa algorithm */ +#else + mbedtls_cipher_context_t cipher_ctx_enc; /*!< encryption context */ + mbedtls_cipher_context_t cipher_ctx_dec; /*!< decryption context */ +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + uint8_t in_cid_len; + uint8_t out_cid_len; + unsigned char in_cid[MBEDTLS_SSL_CID_IN_LEN_MAX]; + unsigned char out_cid[MBEDTLS_SSL_CID_OUT_LEN_MAX]; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +#if defined(MBEDTLS_SSL_CONTEXT_SERIALIZATION) + /* We need the Hello random bytes in order to re-derive keys from the + * Master Secret and other session info, + * see ssl_tls12_populate_transform() */ + unsigned char randbytes[MBEDTLS_SERVER_HELLO_RANDOM_LEN + + MBEDTLS_CLIENT_HELLO_RANDOM_LEN]; + /*!< ServerHello.random+ClientHello.random */ +#endif /* MBEDTLS_SSL_CONTEXT_SERIALIZATION */ +}; + +/* + * Return 1 if the transform uses an AEAD cipher, 0 otherwise. + * Equivalently, return 0 if a separate MAC is used, 1 otherwise. + */ +static inline int mbedtls_ssl_transform_uses_aead( + const mbedtls_ssl_transform *transform) +{ +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) + return transform->maclen == 0 && transform->taglen != 0; +#else + (void) transform; + return 1; +#endif +} + +/* + * Internal representation of record frames + * + * Instances come in two flavors: + * (1) Encrypted + * These always have data_offset = 0 + * (2) Unencrypted + * These have data_offset set to the amount of + * pre-expansion during record protection. Concretely, + * this is the length of the fixed part of the explicit IV + * used for encryption, or 0 if no explicit IV is used + * (e.g. for stream ciphers). + * + * The reason for the data_offset in the unencrypted case + * is to allow for in-place conversion of an unencrypted to + * an encrypted record. If the offset wasn't included, the + * encrypted content would need to be shifted afterwards to + * make space for the fixed IV. + * + */ +#if MBEDTLS_SSL_CID_OUT_LEN_MAX > MBEDTLS_SSL_CID_IN_LEN_MAX +#define MBEDTLS_SSL_CID_LEN_MAX MBEDTLS_SSL_CID_OUT_LEN_MAX +#else +#define MBEDTLS_SSL_CID_LEN_MAX MBEDTLS_SSL_CID_IN_LEN_MAX +#endif + +typedef struct { + uint8_t ctr[MBEDTLS_SSL_SEQUENCE_NUMBER_LEN]; /* In TLS: The implicit record sequence number. + * In DTLS: The 2-byte epoch followed by + * the 6-byte sequence number. + * This is stored as a raw big endian byte array + * as opposed to a uint64_t because we rarely + * need to perform arithmetic on this, but do + * need it as a Byte array for the purpose of + * MAC computations. */ + uint8_t type; /* The record content type. */ + uint8_t ver[2]; /* SSL/TLS version as present on the wire. + * Convert to internal presentation of versions + * using mbedtls_ssl_read_version() and + * mbedtls_ssl_write_version(). + * Keep wire-format for MAC computations. */ + + unsigned char *buf; /* Memory buffer enclosing the record content */ + size_t buf_len; /* Buffer length */ + size_t data_offset; /* Offset of record content */ + size_t data_len; /* Length of record content */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + uint8_t cid_len; /* Length of the CID (0 if not present) */ + unsigned char cid[MBEDTLS_SSL_CID_LEN_MAX]; /* The CID */ +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ +} mbedtls_record; + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +/* + * List of certificate + private key pairs + */ +struct mbedtls_ssl_key_cert { + mbedtls_x509_crt *cert; /*!< cert */ + mbedtls_pk_context *key; /*!< private key */ + mbedtls_ssl_key_cert *next; /*!< next key/cert pair */ +}; +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +/* + * List of handshake messages kept around for resending + */ +struct mbedtls_ssl_flight_item { + unsigned char *p; /*!< message, including handshake headers */ + size_t len; /*!< length of p */ + unsigned char type; /*!< type of the message: handshake or CCS */ + mbedtls_ssl_flight_item *next; /*!< next handshake message(s) */ +}; +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +/** + * \brief Given an SSL context and its associated configuration, write the TLS + * 1.2 specific extensions of the ClientHello message. + * + * \param[in] ssl SSL context + * \param[in] buf Base address of the buffer where to write the extensions + * \param[in] end End address of the buffer where to write the extensions + * \param uses_ec Whether one proposed ciphersuite uses an elliptic curve + * (<> 0) or not ( 0 ). + * \param[out] out_len Length of the data written into the buffer \p buf + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls12_write_client_hello_exts(mbedtls_ssl_context *ssl, + unsigned char *buf, + const unsigned char *end, + int uses_ec, + size_t *out_len); +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && \ + defined(MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED) + +/** + * \brief Find the preferred hash for a given signature algorithm. + * + * \param[in] ssl SSL context + * \param[in] sig_alg A signature algorithm identifier as defined in the + * TLS 1.2 SignatureAlgorithm enumeration. + * + * \return The preferred hash algorithm for \p sig_alg. It is a hash algorithm + * identifier as defined in the TLS 1.2 HashAlgorithm enumeration. + */ +unsigned int mbedtls_ssl_tls12_get_preferred_hash_for_sig_alg( + mbedtls_ssl_context *ssl, + unsigned int sig_alg); + +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 && + MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED */ + +/** + * \brief Free referenced items in an SSL transform context and clear + * memory + * + * \param transform SSL transform context + */ +void mbedtls_ssl_transform_free(mbedtls_ssl_transform *transform); + +/** + * \brief Free referenced items in an SSL handshake context and clear + * memory + * + * \param ssl SSL context + */ +void mbedtls_ssl_handshake_free(mbedtls_ssl_context *ssl); + +/* set inbound transform of ssl context */ +void mbedtls_ssl_set_inbound_transform(mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform); + +/* set outbound transform of ssl context */ +void mbedtls_ssl_set_outbound_transform(mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_handshake_client_step(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_handshake_server_step(mbedtls_ssl_context *ssl); +void mbedtls_ssl_handshake_wrapup(mbedtls_ssl_context *ssl); +static inline void mbedtls_ssl_handshake_set_state(mbedtls_ssl_context *ssl, + mbedtls_ssl_states state) +{ + ssl->state = (int) state; +} + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_send_fatal_handshake_failure(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_reset_checksum(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_derive_keys(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_handle_message_type(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_prepare_handshake_record(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_update_handshake_status(mbedtls_ssl_context *ssl); + +/** + * \brief Update record layer + * + * This function roughly separates the implementation + * of the logic of (D)TLS from the implementation + * of the secure transport. + * + * \param ssl The SSL context to use. + * \param update_hs_digest This indicates if the handshake digest + * should be automatically updated in case + * a handshake message is found. + * + * \return 0 or non-zero error code. + * + * \note A clarification on what is called 'record layer' here + * is in order, as many sensible definitions are possible: + * + * The record layer takes as input an untrusted underlying + * transport (stream or datagram) and transforms it into + * a serially multiplexed, secure transport, which + * conceptually provides the following: + * + * (1) Three datagram based, content-agnostic transports + * for handshake, alert and CCS messages. + * (2) One stream- or datagram-based transport + * for application data. + * (3) Functionality for changing the underlying transform + * securing the contents. + * + * The interface to this functionality is given as follows: + * + * a Updating + * [Currently implemented by mbedtls_ssl_read_record] + * + * Check if and on which of the four 'ports' data is pending: + * Nothing, a controlling datagram of type (1), or application + * data (2). In any case data is present, internal buffers + * provide access to the data for the user to process it. + * Consumption of type (1) datagrams is done automatically + * on the next update, invalidating that the internal buffers + * for previous datagrams, while consumption of application + * data (2) is user-controlled. + * + * b Reading of application data + * [Currently manual adaption of ssl->in_offt pointer] + * + * As mentioned in the last paragraph, consumption of data + * is different from the automatic consumption of control + * datagrams (1) because application data is treated as a stream. + * + * c Tracking availability of application data + * [Currently manually through decreasing ssl->in_msglen] + * + * For efficiency and to retain datagram semantics for + * application data in case of DTLS, the record layer + * provides functionality for checking how much application + * data is still available in the internal buffer. + * + * d Changing the transformation securing the communication. + * + * Given an opaque implementation of the record layer in the + * above sense, it should be possible to implement the logic + * of (D)TLS on top of it without the need to know anything + * about the record layer's internals. This is done e.g. + * in all the handshake handling functions, and in the + * application data reading function mbedtls_ssl_read. + * + * \note The above tries to give a conceptual picture of the + * record layer, but the current implementation deviates + * from it in some places. For example, our implementation of + * the update functionality through mbedtls_ssl_read_record + * discards datagrams depending on the current state, which + * wouldn't fall under the record layer's responsibility + * following the above definition. + * + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_read_record(mbedtls_ssl_context *ssl, + unsigned update_hs_digest); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_fetch_input(mbedtls_ssl_context *ssl, size_t nb_want); + +/* + * Write handshake message header + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_start_handshake_msg(mbedtls_ssl_context *ssl, unsigned hs_type, + unsigned char **buf, size_t *buf_len); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_handshake_msg_ext(mbedtls_ssl_context *ssl, + int update_checksum, + int force_flush); +static inline int mbedtls_ssl_write_handshake_msg(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_write_handshake_msg_ext(ssl, 1 /* update checksum */, 1 /* force flush */); +} + +/* + * Write handshake message tail + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_finish_handshake_msg(mbedtls_ssl_context *ssl, + size_t buf_len, size_t msg_len); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_record(mbedtls_ssl_context *ssl, int force_flush); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_flush_output(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_certificate(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_certificate(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_change_cipher_spec(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_change_cipher_spec(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_finished(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_finished(mbedtls_ssl_context *ssl); + +void mbedtls_ssl_optimize_checksum(mbedtls_ssl_context *ssl, + const mbedtls_ssl_ciphersuite_t *ciphersuite_info); + +/* + * Update checksum of handshake messages. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_add_hs_msg_to_checksum(mbedtls_ssl_context *ssl, + unsigned hs_type, + unsigned char const *msg, + size_t msg_len); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_add_hs_hdr_to_checksum(mbedtls_ssl_context *ssl, + unsigned hs_type, + size_t total_hs_len); + +#if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) +#if !defined(MBEDTLS_USE_PSA_CRYPTO) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_psk_derive_premaster(mbedtls_ssl_context *ssl, + mbedtls_key_exchange_type_t key_ex); +#endif /* !MBEDTLS_USE_PSA_CRYPTO */ +#endif /* MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED) +#if defined(MBEDTLS_SSL_CLI_C) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_conf_has_static_psk(mbedtls_ssl_config const *conf); +#endif +#if defined(MBEDTLS_USE_PSA_CRYPTO) +/** + * Get the first defined opaque PSK by order of precedence: + * 1. handshake PSK set by \c mbedtls_ssl_set_hs_psk_opaque() in the PSK + * callback + * 2. static PSK configured by \c mbedtls_ssl_conf_psk_opaque() + * Return an opaque PSK + */ +static inline mbedtls_svc_key_id_t mbedtls_ssl_get_opaque_psk( + const mbedtls_ssl_context *ssl) +{ + if (!mbedtls_svc_key_id_is_null(ssl->handshake->psk_opaque)) { + return ssl->handshake->psk_opaque; + } + + if (!mbedtls_svc_key_id_is_null(ssl->conf->psk_opaque)) { + return ssl->conf->psk_opaque; + } + + return MBEDTLS_SVC_KEY_ID_INIT; +} +#else +/** + * Get the first defined PSK by order of precedence: + * 1. handshake PSK set by \c mbedtls_ssl_set_hs_psk() in the PSK callback + * 2. static PSK configured by \c mbedtls_ssl_conf_psk() + * Return a code and update the pair (PSK, PSK length) passed to this function + */ +static inline int mbedtls_ssl_get_psk(const mbedtls_ssl_context *ssl, + const unsigned char **psk, size_t *psk_len) +{ + if (ssl->handshake->psk != NULL && ssl->handshake->psk_len > 0) { + *psk = ssl->handshake->psk; + *psk_len = ssl->handshake->psk_len; + } else if (ssl->conf->psk != NULL && ssl->conf->psk_len > 0) { + *psk = ssl->conf->psk; + *psk_len = ssl->conf->psk_len; + } else { + *psk = NULL; + *psk_len = 0; + return MBEDTLS_ERR_SSL_PRIVATE_KEY_REQUIRED; + } + + return 0; +} +#endif /* MBEDTLS_USE_PSA_CRYPTO */ + +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_PSK_ENABLED */ + +#if defined(MBEDTLS_PK_C) +unsigned char mbedtls_ssl_sig_from_pk(mbedtls_pk_context *pk); +unsigned char mbedtls_ssl_sig_from_pk_alg(mbedtls_pk_type_t type); +mbedtls_pk_type_t mbedtls_ssl_pk_alg_from_sig(unsigned char sig); +#endif + +mbedtls_md_type_t mbedtls_ssl_md_alg_from_hash(unsigned char hash); +unsigned char mbedtls_ssl_hash_from_md_alg(int md); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_set_calc_verify_md(mbedtls_ssl_context *ssl, int md); +#endif + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_check_curve_tls_id(const mbedtls_ssl_context *ssl, uint16_t tls_id); +#if defined(MBEDTLS_PK_HAVE_ECC_KEYS) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_check_curve(const mbedtls_ssl_context *ssl, mbedtls_ecp_group_id grp_id); +#endif /* MBEDTLS_PK_HAVE_ECC_KEYS */ + +/** + * \brief Return PSA EC info for the specified TLS ID. + * + * \param tls_id The TLS ID to look for + * \param type If the TLD ID is supported, then proper \c psa_key_type_t + * value is returned here. Can be NULL. + * \param bits If the TLD ID is supported, then proper bit size is returned + * here. Can be NULL. + * \return PSA_SUCCESS if the TLS ID is supported, + * PSA_ERROR_NOT_SUPPORTED otherwise + * + * \note If either \c family or \c bits parameters are NULL, then + * the corresponding value is not returned. + * The function can be called with both parameters as NULL + * simply to check if a specific TLS ID is supported. + */ +int mbedtls_ssl_get_psa_curve_info_from_tls_id(uint16_t tls_id, + psa_key_type_t *type, + size_t *bits); + +/** + * \brief Return \c mbedtls_ecp_group_id for the specified TLS ID. + * + * \param tls_id The TLS ID to look for + * \return Proper \c mbedtls_ecp_group_id if the TLS ID is supported, + * or MBEDTLS_ECP_DP_NONE otherwise + */ +mbedtls_ecp_group_id mbedtls_ssl_get_ecp_group_id_from_tls_id(uint16_t tls_id); + +/** + * \brief Return TLS ID for the specified \c mbedtls_ecp_group_id. + * + * \param grp_id The \c mbedtls_ecp_group_id ID to look for + * \return Proper TLS ID if the \c mbedtls_ecp_group_id is supported, + * or 0 otherwise + */ +uint16_t mbedtls_ssl_get_tls_id_from_ecp_group_id(mbedtls_ecp_group_id grp_id); + +#if defined(MBEDTLS_DEBUG_C) +/** + * \brief Return EC's name for the specified TLS ID. + * + * \param tls_id The TLS ID to look for + * \return A pointer to a const string with the proper name. If TLS + * ID is not supported, a NULL pointer is returned instead. + */ +const char *mbedtls_ssl_get_curve_name_from_tls_id(uint16_t tls_id); +#endif + +#if defined(MBEDTLS_SSL_DTLS_SRTP) +static inline mbedtls_ssl_srtp_profile mbedtls_ssl_check_srtp_profile_value + (const uint16_t srtp_profile_value) +{ + switch (srtp_profile_value) { + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: + return srtp_profile_value; + default: break; + } + return MBEDTLS_TLS_SRTP_UNSET; +} +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +static inline mbedtls_pk_context *mbedtls_ssl_own_key(mbedtls_ssl_context *ssl) +{ + mbedtls_ssl_key_cert *key_cert; + + if (ssl->handshake != NULL && ssl->handshake->key_cert != NULL) { + key_cert = ssl->handshake->key_cert; + } else { + key_cert = ssl->conf->key_cert; + } + + return key_cert == NULL ? NULL : key_cert->key; +} + +static inline mbedtls_x509_crt *mbedtls_ssl_own_cert(mbedtls_ssl_context *ssl) +{ + mbedtls_ssl_key_cert *key_cert; + + if (ssl->handshake != NULL && ssl->handshake->key_cert != NULL) { + key_cert = ssl->handshake->key_cert; + } else { + key_cert = ssl->conf->key_cert; + } + + return key_cert == NULL ? NULL : key_cert->cert; +} + +/* + * Check usage of a certificate wrt extensions: + * keyUsage, extendedKeyUsage (later), and nSCertType (later). + * + * Warning: cert_endpoint is the endpoint of the cert (ie, of our peer when we + * check a cert we received from them)! + * + * Return 0 if everything is OK, -1 if not. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_check_cert_usage(const mbedtls_x509_crt *cert, + const mbedtls_ssl_ciphersuite_t *ciphersuite, + int cert_endpoint, + uint32_t *flags); +#endif /* MBEDTLS_X509_CRT_PARSE_C */ + +void mbedtls_ssl_write_version(unsigned char version[2], int transport, + mbedtls_ssl_protocol_version tls_version); +uint16_t mbedtls_ssl_read_version(const unsigned char version[2], + int transport); + +static inline size_t mbedtls_ssl_in_hdr_len(const mbedtls_ssl_context *ssl) +{ +#if !defined(MBEDTLS_SSL_PROTO_DTLS) + ((void) ssl); +#endif + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { + return 13; + } else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + { + return 5; + } +} + +static inline size_t mbedtls_ssl_out_hdr_len(const mbedtls_ssl_context *ssl) +{ + return (size_t) (ssl->out_iv - ssl->out_hdr); +} + +static inline size_t mbedtls_ssl_hs_hdr_len(const mbedtls_ssl_context *ssl) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { + return 12; + } +#else + ((void) ssl); +#endif + return 4; +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +void mbedtls_ssl_send_flight_completed(mbedtls_ssl_context *ssl); +void mbedtls_ssl_recv_flight_completed(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_resend(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_flight_transmit(mbedtls_ssl_context *ssl); +#endif + +/* Visible for testing purposes only */ +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_dtls_replay_check(mbedtls_ssl_context const *ssl); +void mbedtls_ssl_dtls_replay_update(mbedtls_ssl_context *ssl); +#endif + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_session_copy(mbedtls_ssl_session *dst, + const mbedtls_ssl_session *src); + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +/* The hash buffer must have at least MBEDTLS_MD_MAX_SIZE bytes of length. */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_get_key_exchange_md_tls1_2(mbedtls_ssl_context *ssl, + unsigned char *hash, size_t *hashlen, + unsigned char *data, size_t data_len, + mbedtls_md_type_t md_alg); +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +#ifdef __cplusplus +} +#endif + +void mbedtls_ssl_transform_init(mbedtls_ssl_transform *transform); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_encrypt_buf(mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform, + mbedtls_record *rec, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_decrypt_buf(mbedtls_ssl_context const *ssl, + mbedtls_ssl_transform *transform, + mbedtls_record *rec); + +/* Length of the "epoch" field in the record header */ +static inline size_t mbedtls_ssl_ep_len(const mbedtls_ssl_context *ssl) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if (ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM) { + return 2; + } +#else + ((void) ssl); +#endif + return 0; +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_resend_hello_request(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +void mbedtls_ssl_set_timer(mbedtls_ssl_context *ssl, uint32_t millisecs); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_check_timer(mbedtls_ssl_context *ssl); + +void mbedtls_ssl_reset_in_out_pointers(mbedtls_ssl_context *ssl); +void mbedtls_ssl_update_out_pointers(mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform); +void mbedtls_ssl_update_in_pointers(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_session_reset_int(mbedtls_ssl_context *ssl, int partial); +void mbedtls_ssl_session_reset_msg_layer(mbedtls_ssl_context *ssl, + int partial); + +/* + * Send pending alert + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_handle_pending_alert(mbedtls_ssl_context *ssl); + +/* + * Set pending fatal alert flag. + */ +void mbedtls_ssl_pend_fatal_alert(mbedtls_ssl_context *ssl, + unsigned char alert_type, + int alert_reason); + +/* Alias of mbedtls_ssl_pend_fatal_alert */ +#define MBEDTLS_SSL_PEND_FATAL_ALERT(type, user_return_value) \ + mbedtls_ssl_pend_fatal_alert(ssl, type, user_return_value) + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) +void mbedtls_ssl_dtls_replay_reset(mbedtls_ssl_context *ssl); +#endif + +void mbedtls_ssl_handshake_wrapup_free_hs_transform(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_start_renegotiation(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +size_t mbedtls_ssl_get_current_mtu(const mbedtls_ssl_context *ssl); +void mbedtls_ssl_buffering_free(mbedtls_ssl_context *ssl); +void mbedtls_ssl_flight_free(mbedtls_ssl_flight_item *flight); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +/** + * ssl utils functions for checking configuration. + */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) +static inline int mbedtls_ssl_conf_is_tls13_only(const mbedtls_ssl_config *conf) +{ + return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_3 && + conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_3; +} + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +static inline int mbedtls_ssl_conf_is_tls12_only(const mbedtls_ssl_config *conf) +{ + return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_2 && + conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_2; +} + +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +static inline int mbedtls_ssl_conf_is_tls13_enabled(const mbedtls_ssl_config *conf) +{ +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + return conf->min_tls_version <= MBEDTLS_SSL_VERSION_TLS1_3 && + conf->max_tls_version >= MBEDTLS_SSL_VERSION_TLS1_3; +#else + ((void) conf); + return 0; +#endif +} + +static inline int mbedtls_ssl_conf_is_tls12_enabled(const mbedtls_ssl_config *conf) +{ +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + return conf->min_tls_version <= MBEDTLS_SSL_VERSION_TLS1_2 && + conf->max_tls_version >= MBEDTLS_SSL_VERSION_TLS1_2; +#else + ((void) conf); + return 0; +#endif +} + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) && defined(MBEDTLS_SSL_PROTO_TLS1_3) +static inline int mbedtls_ssl_conf_is_hybrid_tls12_tls13(const mbedtls_ssl_config *conf) +{ + return conf->min_tls_version == MBEDTLS_SSL_VERSION_TLS1_2 && + conf->max_tls_version == MBEDTLS_SSL_VERSION_TLS1_3; +} +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 && MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) +extern const uint8_t mbedtls_ssl_tls13_hello_retry_request_magic[ + MBEDTLS_SERVER_HELLO_RANDOM_LEN]; +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_process_finished_message(mbedtls_ssl_context *ssl); +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_finished_message(mbedtls_ssl_context *ssl); +void mbedtls_ssl_tls13_handshake_wrapup(mbedtls_ssl_context *ssl); + +/** + * \brief Given an SSL context and its associated configuration, write the TLS + * 1.3 specific extensions of the ClientHello message. + * + * \param[in] ssl SSL context + * \param[in] buf Base address of the buffer where to write the extensions + * \param[in] end End address of the buffer where to write the extensions + * \param[out] out_len Length of the data written into the buffer \p buf + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_client_hello_exts(mbedtls_ssl_context *ssl, + unsigned char *buf, + unsigned char *end, + size_t *out_len); + +/** + * \brief TLS 1.3 client side state machine entry + * + * \param ssl SSL context + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_handshake_client_step(mbedtls_ssl_context *ssl); + +/** + * \brief TLS 1.3 server side state machine entry + * + * \param ssl SSL context + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_handshake_server_step(mbedtls_ssl_context *ssl); + + +/* + * Helper functions around key exchange modes. + */ +static inline unsigned mbedtls_ssl_conf_tls13_check_kex_modes(mbedtls_ssl_context *ssl, + int kex_mode_mask) +{ + return (ssl->conf->tls13_kex_modes & kex_mode_mask) != 0; +} + +static inline int mbedtls_ssl_conf_tls13_psk_enabled(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK); +} + +static inline int mbedtls_ssl_conf_tls13_psk_ephemeral_enabled(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL); +} + +static inline int mbedtls_ssl_conf_tls13_ephemeral_enabled(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL); +} + +static inline int mbedtls_ssl_conf_tls13_some_ephemeral_enabled(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); +} + +static inline int mbedtls_ssl_conf_tls13_some_psk_enabled(mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_conf_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); +} + +#if defined(MBEDTLS_SSL_SRV_C) && \ + defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) +/** + * Given a list of key exchange modes, check if at least one of them is + * supported. + * + * \param[in] ssl SSL context + * \param kex_modes_mask Mask of the key exchange modes to check + * + * \return 0 if at least one of the key exchange modes is supported, + * !=0 otherwise. + */ +static inline unsigned mbedtls_ssl_tls13_check_kex_modes(mbedtls_ssl_context *ssl, + int kex_modes_mask) +{ + return (ssl->handshake->tls13_kex_modes & kex_modes_mask) == 0; +} + +static inline int mbedtls_ssl_tls13_psk_enabled(mbedtls_ssl_context *ssl) +{ + return !mbedtls_ssl_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK); +} + +static inline int mbedtls_ssl_tls13_psk_ephemeral_enabled( + mbedtls_ssl_context *ssl) +{ + return !mbedtls_ssl_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL); +} + +static inline int mbedtls_ssl_tls13_ephemeral_enabled(mbedtls_ssl_context *ssl) +{ + return !mbedtls_ssl_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL); +} + +static inline int mbedtls_ssl_tls13_some_ephemeral_enabled(mbedtls_ssl_context *ssl) +{ + return !mbedtls_ssl_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); +} + +static inline int mbedtls_ssl_tls13_some_psk_enabled(mbedtls_ssl_context *ssl) +{ + return !mbedtls_ssl_tls13_check_kex_modes(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); +} +#endif /* MBEDTLS_SSL_SRV_C && + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED */ + +/* + * Helper functions for extensions checking. + */ + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_check_received_extension( + mbedtls_ssl_context *ssl, + int hs_msg_type, + unsigned int received_extension_type, + uint32_t hs_msg_allowed_extensions_mask); + +static inline void mbedtls_ssl_tls13_set_hs_sent_ext_mask( + mbedtls_ssl_context *ssl, unsigned int extension_type) +{ + ssl->handshake->sent_extensions |= + mbedtls_ssl_get_extension_mask(extension_type); +} + +/* + * Helper functions to check the selected key exchange mode. + */ +static inline int mbedtls_ssl_tls13_key_exchange_mode_check( + mbedtls_ssl_context *ssl, int kex_mask) +{ + return (ssl->handshake->key_exchange_mode & kex_mask) != 0; +} + +static inline int mbedtls_ssl_tls13_key_exchange_mode_with_psk( + mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_tls13_key_exchange_mode_check(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ALL); +} + +static inline int mbedtls_ssl_tls13_key_exchange_mode_with_ephemeral( + mbedtls_ssl_context *ssl) +{ + return mbedtls_ssl_tls13_key_exchange_mode_check(ssl, + MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ALL); +} + +/* + * Fetch TLS 1.3 handshake message header + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_fetch_handshake_msg(mbedtls_ssl_context *ssl, + unsigned hs_type, + unsigned char **buf, + size_t *buf_len); + +/** + * \brief Detect if a list of extensions contains a supported_versions + * extension or not. + * + * \param[in] ssl SSL context + * \param[in] buf Address of the first byte of the extensions vector. + * \param[in] end End of the buffer containing the list of extensions. + * \param[out] supported_versions_data If the extension is present, address of + * its first byte of data, NULL otherwise. + * \param[out] supported_versions_data_end If the extension is present, address + * of the first byte immediately + * following the extension data, NULL + * otherwise. + * \return 0 if the list of extensions does not contain a supported_versions + * extension. + * \return 1 if the list of extensions contains a supported_versions + * extension. + * \return A negative value if an error occurred while parsing the + * extensions. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_is_supported_versions_ext_present_in_exts( + mbedtls_ssl_context *ssl, + const unsigned char *buf, const unsigned char *end, + const unsigned char **supported_versions_data, + const unsigned char **supported_versions_data_end); + +/* + * Handler of TLS 1.3 server certificate message + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_process_certificate(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +/* + * Handler of TLS 1.3 write Certificate message + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_certificate(mbedtls_ssl_context *ssl); + +/* + * Handler of TLS 1.3 write Certificate Verify message + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_certificate_verify(mbedtls_ssl_context *ssl); + +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED */ + +/* + * Generic handler of Certificate Verify + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_process_certificate_verify(mbedtls_ssl_context *ssl); + +/* + * Write of dummy-CCS's for middlebox compatibility + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_change_cipher_spec(mbedtls_ssl_context *ssl); + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_reset_transcript_for_hrr(mbedtls_ssl_context *ssl); + +#if defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_generate_and_write_xxdh_key_exchange( + mbedtls_ssl_context *ssl, + uint16_t named_group, + unsigned char *buf, + unsigned char *end, + size_t *out_len); +#endif /* PSA_WANT_ALG_ECDH || PSA_WANT_ALG_FFDH */ + +#if defined(MBEDTLS_SSL_EARLY_DATA) +int mbedtls_ssl_tls13_write_early_data_ext(mbedtls_ssl_context *ssl, + unsigned char *buf, + const unsigned char *end, + size_t *out_len); +#endif /* MBEDTLS_SSL_EARLY_DATA */ + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) +/* + * Write Signature Algorithm extension + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_sig_alg_ext(mbedtls_ssl_context *ssl, unsigned char *buf, + const unsigned char *end, size_t *out_len); +/* + * Parse TLS Signature Algorithm extension + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_sig_alg_ext(mbedtls_ssl_context *ssl, + const unsigned char *buf, + const unsigned char *end); +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + +/* Get handshake transcript */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_get_handshake_transcript(mbedtls_ssl_context *ssl, + const mbedtls_md_type_t md, + unsigned char *dst, + size_t dst_len, + size_t *olen); + +/* + * Return supported groups. + * + * In future, invocations can be changed to ssl->conf->group_list + * when mbedtls_ssl_conf_curves() is deleted. + * + * ssl->handshake->group_list is either a translation of curve_list to IANA TLS group + * identifiers when mbedtls_ssl_conf_curves() has been used, or a pointer to + * ssl->conf->group_list when mbedtls_ssl_conf_groups() has been more recently invoked. + * + */ +static inline const void *mbedtls_ssl_get_groups(const mbedtls_ssl_context *ssl) +{ + #if defined(MBEDTLS_DEPRECATED_REMOVED) || !defined(MBEDTLS_ECP_C) + return ssl->conf->group_list; + #else + if ((ssl->handshake != NULL) && (ssl->handshake->group_list != NULL)) { + return ssl->handshake->group_list; + } else { + return ssl->conf->group_list; + } + #endif +} + +/* + * Helper functions for NamedGroup. + */ +static inline int mbedtls_ssl_tls12_named_group_is_ecdhe(uint16_t named_group) +{ + /* + * RFC 8422 section 5.1.1 + */ + return named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X25519 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP256R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP384R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_BP512R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X448 || + /* Below deprecated curves should be removed with notice to users */ + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP192K1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP192R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP224K1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP224R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256K1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1; +} + +static inline int mbedtls_ssl_tls13_named_group_is_ecdhe(uint16_t named_group) +{ + return named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X25519 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP256R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP384R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_SECP521R1 || + named_group == MBEDTLS_SSL_IANA_TLS_GROUP_X448; +} + +static inline int mbedtls_ssl_tls13_named_group_is_ffdh(uint16_t named_group) +{ + return named_group >= MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE2048 && + named_group <= MBEDTLS_SSL_IANA_TLS_GROUP_FFDHE8192; +} + +static inline int mbedtls_ssl_named_group_is_offered( + const mbedtls_ssl_context *ssl, uint16_t named_group) +{ + const uint16_t *group_list = mbedtls_ssl_get_groups(ssl); + + if (group_list == NULL) { + return 0; + } + + for (; *group_list != 0; group_list++) { + if (*group_list == named_group) { + return 1; + } + } + + return 0; +} + +static inline int mbedtls_ssl_named_group_is_supported(uint16_t named_group) +{ +#if defined(PSA_WANT_ALG_ECDH) + if (mbedtls_ssl_tls13_named_group_is_ecdhe(named_group)) { + if (mbedtls_ssl_get_ecp_group_id_from_tls_id(named_group) != + MBEDTLS_ECP_DP_NONE) { + return 1; + } + } +#endif +#if defined(PSA_WANT_ALG_FFDH) + if (mbedtls_ssl_tls13_named_group_is_ffdh(named_group)) { + return 1; + } +#endif +#if !defined(PSA_WANT_ALG_ECDH) && !defined(PSA_WANT_ALG_FFDH) + (void) named_group; +#endif + return 0; +} + +/* + * Return supported signature algorithms. + * + * In future, invocations can be changed to ssl->conf->sig_algs when + * mbedtls_ssl_conf_sig_hashes() is deleted. + * + * ssl->handshake->sig_algs is either a translation of sig_hashes to IANA TLS + * signature algorithm identifiers when mbedtls_ssl_conf_sig_hashes() has been + * used, or a pointer to ssl->conf->sig_algs when mbedtls_ssl_conf_sig_algs() has + * been more recently invoked. + * + */ +static inline const void *mbedtls_ssl_get_sig_algs( + const mbedtls_ssl_context *ssl) +{ +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + if (ssl->handshake != NULL && + ssl->handshake->sig_algs_heap_allocated == 1 && + ssl->handshake->sig_algs != NULL) { + return ssl->handshake->sig_algs; + } +#endif + return ssl->conf->sig_algs; + +#else /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + + ((void) ssl); + return NULL; +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ +} + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) +static inline int mbedtls_ssl_sig_alg_is_received(const mbedtls_ssl_context *ssl, + uint16_t own_sig_alg) +{ + const uint16_t *sig_alg = ssl->handshake->received_sig_algs; + if (sig_alg == NULL) { + return 0; + } + + for (; *sig_alg != MBEDTLS_TLS_SIG_NONE; sig_alg++) { + if (*sig_alg == own_sig_alg) { + return 1; + } + } + return 0; +} + +static inline int mbedtls_ssl_tls13_sig_alg_for_cert_verify_is_supported( + const uint16_t sig_alg) +{ + switch (sig_alg) { +#if defined(MBEDTLS_PK_CAN_ECDSA_SOME) +#if defined(PSA_WANT_ALG_SHA_256) && defined(PSA_WANT_ECC_SECP_R1_256) + case MBEDTLS_TLS1_3_SIG_ECDSA_SECP256R1_SHA256: + break; +#endif /* PSA_WANT_ALG_SHA_256 && MBEDTLS_ECP_DP_SECP256R1_ENABLED */ +#if defined(PSA_WANT_ALG_SHA_384) && defined(PSA_WANT_ECC_SECP_R1_384) + case MBEDTLS_TLS1_3_SIG_ECDSA_SECP384R1_SHA384: + break; +#endif /* PSA_WANT_ALG_SHA_384 && MBEDTLS_ECP_DP_SECP384R1_ENABLED */ +#if defined(PSA_WANT_ALG_SHA_512) && defined(PSA_WANT_ECC_SECP_R1_521) + case MBEDTLS_TLS1_3_SIG_ECDSA_SECP521R1_SHA512: + break; +#endif /* PSA_WANT_ALG_SHA_512 && MBEDTLS_ECP_DP_SECP521R1_ENABLED */ +#endif /* MBEDTLS_PK_CAN_ECDSA_SOME */ + +#if defined(MBEDTLS_PKCS1_V21) +#if defined(PSA_WANT_ALG_SHA_256) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256: + break; +#endif /* PSA_WANT_ALG_SHA_256 */ +#if defined(PSA_WANT_ALG_SHA_384) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384: + break; +#endif /* PSA_WANT_ALG_SHA_384 */ +#if defined(PSA_WANT_ALG_SHA_512) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512: + break; +#endif /* PSA_WANT_ALG_SHA_512 */ +#endif /* MBEDTLS_PKCS1_V21 */ + default: + return 0; + } + return 1; + +} + +static inline int mbedtls_ssl_tls13_sig_alg_is_supported( + const uint16_t sig_alg) +{ + switch (sig_alg) { +#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_MD_CAN_SHA256) + case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA256: + break; +#endif /* MBEDTLS_MD_CAN_SHA256 */ +#if defined(MBEDTLS_MD_CAN_SHA384) + case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA384: + break; +#endif /* MBEDTLS_MD_CAN_SHA384 */ +#if defined(MBEDTLS_MD_CAN_SHA512) + case MBEDTLS_TLS1_3_SIG_RSA_PKCS1_SHA512: + break; +#endif /* MBEDTLS_MD_CAN_SHA512 */ +#endif /* MBEDTLS_PKCS1_V15 */ + default: + return mbedtls_ssl_tls13_sig_alg_for_cert_verify_is_supported( + sig_alg); + } + return 1; +} + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_check_sig_alg_cert_key_match(uint16_t sig_alg, + mbedtls_pk_context *key); +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED */ + +#if defined(MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED) +static inline int mbedtls_ssl_sig_alg_is_offered(const mbedtls_ssl_context *ssl, + uint16_t proposed_sig_alg) +{ + const uint16_t *sig_alg = mbedtls_ssl_get_sig_algs(ssl); + if (sig_alg == NULL) { + return 0; + } + + for (; *sig_alg != MBEDTLS_TLS_SIG_NONE; sig_alg++) { + if (*sig_alg == proposed_sig_alg) { + return 1; + } + } + return 0; +} + +static inline int mbedtls_ssl_get_pk_type_and_md_alg_from_sig_alg( + uint16_t sig_alg, mbedtls_pk_type_t *pk_type, mbedtls_md_type_t *md_alg) +{ + *pk_type = mbedtls_ssl_pk_alg_from_sig(sig_alg & 0xff); + *md_alg = mbedtls_ssl_md_alg_from_hash((sig_alg >> 8) & 0xff); + + if (*pk_type != MBEDTLS_PK_NONE && *md_alg != MBEDTLS_MD_NONE) { + return 0; + } + + switch (sig_alg) { +#if defined(MBEDTLS_PKCS1_V21) +#if defined(MBEDTLS_MD_CAN_SHA256) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA256: + *md_alg = MBEDTLS_MD_SHA256; + *pk_type = MBEDTLS_PK_RSASSA_PSS; + break; +#endif /* MBEDTLS_MD_CAN_SHA256 */ +#if defined(MBEDTLS_MD_CAN_SHA384) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA384: + *md_alg = MBEDTLS_MD_SHA384; + *pk_type = MBEDTLS_PK_RSASSA_PSS; + break; +#endif /* MBEDTLS_MD_CAN_SHA384 */ +#if defined(MBEDTLS_MD_CAN_SHA512) + case MBEDTLS_TLS1_3_SIG_RSA_PSS_RSAE_SHA512: + *md_alg = MBEDTLS_MD_SHA512; + *pk_type = MBEDTLS_PK_RSASSA_PSS; + break; +#endif /* MBEDTLS_MD_CAN_SHA512 */ +#endif /* MBEDTLS_PKCS1_V21 */ + default: + return MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; + } + return 0; +} + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) +static inline int mbedtls_ssl_tls12_sig_alg_is_supported( + const uint16_t sig_alg) +{ + /* High byte is hash */ + unsigned char hash = MBEDTLS_BYTE_1(sig_alg); + unsigned char sig = MBEDTLS_BYTE_0(sig_alg); + + switch (hash) { +#if defined(MBEDTLS_MD_CAN_MD5) + case MBEDTLS_SSL_HASH_MD5: + break; +#endif + +#if defined(MBEDTLS_MD_CAN_SHA1) + case MBEDTLS_SSL_HASH_SHA1: + break; +#endif + +#if defined(MBEDTLS_MD_CAN_SHA224) + case MBEDTLS_SSL_HASH_SHA224: + break; +#endif + +#if defined(MBEDTLS_MD_CAN_SHA256) + case MBEDTLS_SSL_HASH_SHA256: + break; +#endif + +#if defined(MBEDTLS_MD_CAN_SHA384) + case MBEDTLS_SSL_HASH_SHA384: + break; +#endif + +#if defined(MBEDTLS_MD_CAN_SHA512) + case MBEDTLS_SSL_HASH_SHA512: + break; +#endif + + default: + return 0; + } + + switch (sig) { +#if defined(MBEDTLS_RSA_C) + case MBEDTLS_SSL_SIG_RSA: + break; +#endif + +#if defined(MBEDTLS_KEY_EXCHANGE_ECDSA_CERT_REQ_ALLOWED_ENABLED) + case MBEDTLS_SSL_SIG_ECDSA: + break; +#endif + + default: + return 0; + } + + return 1; +} +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +static inline int mbedtls_ssl_sig_alg_is_supported( + const mbedtls_ssl_context *ssl, + const uint16_t sig_alg) +{ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + if (ssl->tls_version == MBEDTLS_SSL_VERSION_TLS1_2) { + return mbedtls_ssl_tls12_sig_alg_is_supported(sig_alg); + } +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED) + if (ssl->tls_version == MBEDTLS_SSL_VERSION_TLS1_3) { + return mbedtls_ssl_tls13_sig_alg_is_supported(sig_alg); + } +#endif + ((void) ssl); + ((void) sig_alg); + return 0; +} +#endif /* MBEDTLS_SSL_HANDSHAKE_WITH_CERT_ENABLED */ + +#if defined(MBEDTLS_USE_PSA_CRYPTO) || defined(MBEDTLS_SSL_PROTO_TLS1_3) +/* Corresponding PSA algorithm for MBEDTLS_CIPHER_NULL. + * Same value is used for PSA_ALG_CATEGORY_CIPHER, hence it is + * guaranteed to not be a valid PSA algorithm identifier. + */ +#define MBEDTLS_SSL_NULL_CIPHER 0x04000000 + +/** + * \brief Translate mbedtls cipher type/taglen pair to psa: + * algorithm, key type and key size. + * + * \param mbedtls_cipher_type [in] given mbedtls cipher type + * \param taglen [in] given tag length + * 0 - default tag length + * \param alg [out] corresponding PSA alg + * There is no corresponding PSA + * alg for MBEDTLS_CIPHER_NULL, so + * in this case MBEDTLS_SSL_NULL_CIPHER + * is returned via this parameter + * \param key_type [out] corresponding PSA key type + * \param key_size [out] corresponding PSA key size + * + * \return PSA_SUCCESS on success or PSA_ERROR_NOT_SUPPORTED if + * conversion is not supported. + */ +psa_status_t mbedtls_ssl_cipher_to_psa(mbedtls_cipher_type_t mbedtls_cipher_type, + size_t taglen, + psa_algorithm_t *alg, + psa_key_type_t *key_type, + size_t *key_size); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/** + * \brief Convert given PSA status to mbedtls error code. + * + * \param status [in] given PSA status + * + * \return corresponding mbedtls error code + */ +static inline MBEDTLS_DEPRECATED int psa_ssl_status_to_mbedtls(psa_status_t status) +{ + switch (status) { + case PSA_SUCCESS: + return 0; + case PSA_ERROR_INSUFFICIENT_MEMORY: + return MBEDTLS_ERR_SSL_ALLOC_FAILED; + case PSA_ERROR_NOT_SUPPORTED: + return MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; + case PSA_ERROR_INVALID_SIGNATURE: + return MBEDTLS_ERR_SSL_INVALID_MAC; + case PSA_ERROR_INVALID_ARGUMENT: + return MBEDTLS_ERR_SSL_BAD_INPUT_DATA; + case PSA_ERROR_BAD_STATE: + return MBEDTLS_ERR_SSL_INTERNAL_ERROR; + case PSA_ERROR_BUFFER_TOO_SMALL: + return MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; + default: + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_USE_PSA_CRYPTO || MBEDTLS_SSL_PROTO_TLS1_3 */ + +#if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) && \ + defined(MBEDTLS_USE_PSA_CRYPTO) + +typedef enum { + MBEDTLS_ECJPAKE_ROUND_ONE, + MBEDTLS_ECJPAKE_ROUND_TWO +} mbedtls_ecjpake_rounds_t; + +/** + * \brief Parse the provided input buffer for getting the first round + * of key exchange. This code is common between server and client + * + * \param pake_ctx [in] the PAKE's operation/context structure + * \param buf [in] input buffer to parse + * \param len [in] length of the input buffer + * \param round [in] either MBEDTLS_ECJPAKE_ROUND_ONE or + * MBEDTLS_ECJPAKE_ROUND_TWO + * + * \return 0 on success or a negative error code in case of failure + */ +int mbedtls_psa_ecjpake_read_round( + psa_pake_operation_t *pake_ctx, + const unsigned char *buf, + size_t len, mbedtls_ecjpake_rounds_t round); + +/** + * \brief Write the first round of key exchange into the provided output + * buffer. This code is common between server and client + * + * \param pake_ctx [in] the PAKE's operation/context structure + * \param buf [out] the output buffer in which data will be written to + * \param len [in] length of the output buffer + * \param olen [out] the length of the data really written on the buffer + * \param round [in] either MBEDTLS_ECJPAKE_ROUND_ONE or + * MBEDTLS_ECJPAKE_ROUND_TWO + * + * \return 0 on success or a negative error code in case of failure + */ +int mbedtls_psa_ecjpake_write_round( + psa_pake_operation_t *pake_ctx, + unsigned char *buf, + size_t len, size_t *olen, + mbedtls_ecjpake_rounds_t round); + +#endif //MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED && MBEDTLS_USE_PSA_CRYPTO + +/** + * \brief TLS record protection modes + */ +typedef enum { + MBEDTLS_SSL_MODE_STREAM = 0, + MBEDTLS_SSL_MODE_CBC, + MBEDTLS_SSL_MODE_CBC_ETM, + MBEDTLS_SSL_MODE_AEAD +} mbedtls_ssl_mode_t; + +mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_transform( + const mbedtls_ssl_transform *transform); + +#if defined(MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM) +mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_ciphersuite( + int encrypt_then_mac, + const mbedtls_ssl_ciphersuite_t *suite); +#else +mbedtls_ssl_mode_t mbedtls_ssl_get_mode_from_ciphersuite( + const mbedtls_ssl_ciphersuite_t *suite); +#endif /* MBEDTLS_SSL_SOME_SUITES_USE_CBC_ETM */ + +#if defined(PSA_WANT_ALG_ECDH) || defined(PSA_WANT_ALG_FFDH) + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_read_public_xxdhe_share(mbedtls_ssl_context *ssl, + const unsigned char *buf, + size_t buf_len); + +#endif /* PSA_WANT_ALG_ECDH || PSA_WANT_ALG_FFDH */ + +static inline int mbedtls_ssl_tls13_cipher_suite_is_offered( + mbedtls_ssl_context *ssl, int cipher_suite) +{ + const int *ciphersuite_list = ssl->conf->ciphersuite_list; + + /* Check whether we have offered this ciphersuite */ + for (size_t i = 0; ciphersuite_list[i] != 0; i++) { + if (ciphersuite_list[i] == cipher_suite) { + return 1; + } + } + return 0; +} + +/** + * \brief Validate cipher suite against config in SSL context. + * + * \param ssl SSL context + * \param suite_info Cipher suite to validate + * \param min_tls_version Minimal TLS version to accept a cipher suite + * \param max_tls_version Maximal TLS version to accept a cipher suite + * + * \return 0 if valid, negative value otherwise. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_validate_ciphersuite( + const mbedtls_ssl_context *ssl, + const mbedtls_ssl_ciphersuite_t *suite_info, + mbedtls_ssl_protocol_version min_tls_version, + mbedtls_ssl_protocol_version max_tls_version); + +#if defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_server_name_ext(mbedtls_ssl_context *ssl, + const unsigned char *buf, + const unsigned char *end); +#endif /* MBEDTLS_SSL_SERVER_NAME_INDICATION */ + +#if defined(MBEDTLS_SSL_RECORD_SIZE_LIMIT) +#define MBEDTLS_SSL_RECORD_SIZE_LIMIT_EXTENSION_DATA_LENGTH (2) +#define MBEDTLS_SSL_RECORD_SIZE_LIMIT_MIN (64) + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_parse_record_size_limit_ext(mbedtls_ssl_context *ssl, + const unsigned char *buf, + const unsigned char *end); +#endif /* MBEDTLS_SSL_RECORD_SIZE_LIMIT */ + +#if defined(MBEDTLS_SSL_ALPN) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_parse_alpn_ext(mbedtls_ssl_context *ssl, + const unsigned char *buf, + const unsigned char *end); + + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_write_alpn_ext(mbedtls_ssl_context *ssl, + unsigned char *buf, + unsigned char *end, + size_t *out_len); +#endif /* MBEDTLS_SSL_ALPN */ + +#if defined(MBEDTLS_TEST_HOOKS) +int mbedtls_ssl_check_dtls_clihlo_cookie( + mbedtls_ssl_context *ssl, + const unsigned char *cli_id, size_t cli_id_len, + const unsigned char *in, size_t in_len, + unsigned char *obuf, size_t buf_len, size_t *olen); +#endif + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) +/** + * \brief Given an SSL context and its associated configuration, write the TLS + * 1.3 specific Pre-Shared key extension. + * + * \param[in] ssl SSL context + * \param[in] buf Base address of the buffer where to write the extension + * \param[in] end End address of the buffer where to write the extension + * \param[out] out_len Length in bytes of the Pre-Shared key extension: data + * written into the buffer \p buf by this function plus + * the length of the binders to be written. + * \param[out] binders_len Length of the binders to be written at the end of + * the extension. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_identities_of_pre_shared_key_ext( + mbedtls_ssl_context *ssl, + unsigned char *buf, unsigned char *end, + size_t *out_len, size_t *binders_len); + +/** + * \brief Given an SSL context and its associated configuration, write the TLS + * 1.3 specific Pre-Shared key extension binders at the end of the + * ClientHello. + * + * \param[in] ssl SSL context + * \param[in] buf Base address of the buffer where to write the binders + * \param[in] end End address of the buffer where to write the binders + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_write_binders_of_pre_shared_key_ext( + mbedtls_ssl_context *ssl, + unsigned char *buf, unsigned char *end); +#endif /* MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED */ + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && \ + defined(MBEDTLS_SSL_SESSION_TICKETS) && \ + defined(MBEDTLS_SSL_SERVER_NAME_INDICATION) && \ + defined(MBEDTLS_SSL_CLI_C) +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_session_set_hostname(mbedtls_ssl_session *session, + const char *hostname); +#endif + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) && defined(MBEDTLS_SSL_SESSION_TICKETS) +static inline unsigned int mbedtls_ssl_session_get_ticket_flags( + mbedtls_ssl_session *session, unsigned int flags) +{ + return session->ticket_flags & + (flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); +} + +static inline void mbedtls_ssl_session_set_ticket_flags( + mbedtls_ssl_session *session, unsigned int flags) +{ + session->ticket_flags |= (flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); +} + +static inline void mbedtls_ssl_session_clear_ticket_flags( + mbedtls_ssl_session *session, unsigned int flags) +{ + session->ticket_flags &= ~(flags & MBEDTLS_SSL_TLS1_3_TICKET_FLAGS_MASK); +} +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 && MBEDTLS_SSL_SESSION_TICKETS */ + +#if defined(MBEDTLS_SSL_CLI_C) && defined(MBEDTLS_SSL_PROTO_TLS1_3) +int mbedtls_ssl_tls13_finalize_client_hello(mbedtls_ssl_context *ssl); +#endif + +#if defined(MBEDTLS_TEST_HOOKS) && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) + +/** Compute the HMAC of variable-length data with constant flow. + * + * This function computes the HMAC of the concatenation of \p add_data and \p + * data, and does with a code flow and memory access pattern that does not + * depend on \p data_len_secret, but only on \p min_data_len and \p + * max_data_len. In particular, this function always reads exactly \p + * max_data_len bytes from \p data. + * + * \param ctx The HMAC context. It must have keys configured + * with mbedtls_md_hmac_starts() and use one of the + * following hashes: SHA-384, SHA-256, SHA-1 or MD-5. + * It is reset using mbedtls_md_hmac_reset() after + * the computation is complete to prepare for the + * next computation. + * \param add_data The first part of the message whose HMAC is being + * calculated. This must point to a readable buffer + * of \p add_data_len bytes. + * \param add_data_len The length of \p add_data in bytes. + * \param data The buffer containing the second part of the + * message. This must point to a readable buffer + * of \p max_data_len bytes. + * \param data_len_secret The length of the data to process in \p data. + * This must be no less than \p min_data_len and no + * greater than \p max_data_len. + * \param min_data_len The minimal length of the second part of the + * message, read from \p data. + * \param max_data_len The maximal length of the second part of the + * message, read from \p data. + * \param output The HMAC will be written here. This must point to + * a writable buffer of sufficient size to hold the + * HMAC value. + * + * \retval 0 on success. + * \retval #MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED + * The hardware accelerator failed. + */ +#if defined(MBEDTLS_USE_PSA_CRYPTO) +int mbedtls_ct_hmac(mbedtls_svc_key_id_t key, + psa_algorithm_t mac_alg, + const unsigned char *add_data, + size_t add_data_len, + const unsigned char *data, + size_t data_len_secret, + size_t min_data_len, + size_t max_data_len, + unsigned char *output); +#else +int mbedtls_ct_hmac(mbedtls_md_context_t *ctx, + const unsigned char *add_data, + size_t add_data_len, + const unsigned char *data, + size_t data_len_secret, + size_t min_data_len, + size_t max_data_len, + unsigned char *output); +#endif /* defined(MBEDTLS_USE_PSA_CRYPTO) */ +#endif /* MBEDTLS_TEST_HOOKS && defined(MBEDTLS_SSL_SOME_SUITES_USE_MAC) */ + +#endif /* ssl_misc.h */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_invasive.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_invasive.h index 3fb79a9..f107910 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_invasive.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_invasive.h @@ -1,35 +1,35 @@ -/* - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBEDTLS_SSL_TLS13_INVASIVE_H -#define MBEDTLS_SSL_TLS13_INVASIVE_H - -#include "common.h" - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - -#include "psa/crypto.h" - -#if defined(MBEDTLS_TEST_HOOKS) -int mbedtls_ssl_tls13_parse_certificate(mbedtls_ssl_context *ssl, - const unsigned char *buf, - const unsigned char *end); -#endif /* MBEDTLS_TEST_HOOKS */ - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#endif /* MBEDTLS_SSL_TLS13_INVASIVE_H */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SSL_TLS13_INVASIVE_H +#define MBEDTLS_SSL_TLS13_INVASIVE_H + +#include "common.h" + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + +#include "psa/crypto.h" + +#if defined(MBEDTLS_TEST_HOOKS) +int mbedtls_ssl_tls13_parse_certificate(mbedtls_ssl_context *ssl, + const unsigned char *buf, + const unsigned char *end); +#endif /* MBEDTLS_TEST_HOOKS */ + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#endif /* MBEDTLS_SSL_TLS13_INVASIVE_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_keys.h b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_keys.h index 21e9b4d..ce0e9cd 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_keys.h +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/ssl_tls13_keys.h @@ -1,663 +1,663 @@ -/* - * TLS 1.3 key schedule - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 ( the "License" ); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#if !defined(MBEDTLS_SSL_TLS1_3_KEYS_H) -#define MBEDTLS_SSL_TLS1_3_KEYS_H - -/* This requires MBEDTLS_SSL_TLS1_3_LABEL( idx, name, string ) to be defined at - * the point of use. See e.g. the definition of mbedtls_ssl_tls13_labels_union - * below. */ -#define MBEDTLS_SSL_TLS1_3_LABEL_LIST \ - MBEDTLS_SSL_TLS1_3_LABEL(finished, "finished") \ - MBEDTLS_SSL_TLS1_3_LABEL(resumption, "resumption") \ - MBEDTLS_SSL_TLS1_3_LABEL(traffic_upd, "traffic upd") \ - MBEDTLS_SSL_TLS1_3_LABEL(exporter, "exporter") \ - MBEDTLS_SSL_TLS1_3_LABEL(key, "key") \ - MBEDTLS_SSL_TLS1_3_LABEL(iv, "iv") \ - MBEDTLS_SSL_TLS1_3_LABEL(c_hs_traffic, "c hs traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(c_ap_traffic, "c ap traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(c_e_traffic, "c e traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(s_hs_traffic, "s hs traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(s_ap_traffic, "s ap traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(s_e_traffic, "s e traffic") \ - MBEDTLS_SSL_TLS1_3_LABEL(e_exp_master, "e exp master") \ - MBEDTLS_SSL_TLS1_3_LABEL(res_master, "res master") \ - MBEDTLS_SSL_TLS1_3_LABEL(exp_master, "exp master") \ - MBEDTLS_SSL_TLS1_3_LABEL(ext_binder, "ext binder") \ - MBEDTLS_SSL_TLS1_3_LABEL(res_binder, "res binder") \ - MBEDTLS_SSL_TLS1_3_LABEL(derived, "derived") \ - MBEDTLS_SSL_TLS1_3_LABEL(client_cv, "TLS 1.3, client CertificateVerify") \ - MBEDTLS_SSL_TLS1_3_LABEL(server_cv, "TLS 1.3, server CertificateVerify") - -#define MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED 0 -#define MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED 1 - -#define MBEDTLS_SSL_TLS1_3_PSK_EXTERNAL 0 -#define MBEDTLS_SSL_TLS1_3_PSK_RESUMPTION 1 - -#if defined(MBEDTLS_SSL_PROTO_TLS1_3) - -#define MBEDTLS_SSL_TLS1_3_LABEL(name, string) \ - const unsigned char name [sizeof(string) - 1]; - -union mbedtls_ssl_tls13_labels_union { - MBEDTLS_SSL_TLS1_3_LABEL_LIST -}; -struct mbedtls_ssl_tls13_labels_struct { - MBEDTLS_SSL_TLS1_3_LABEL_LIST -}; -#undef MBEDTLS_SSL_TLS1_3_LABEL - -extern const struct mbedtls_ssl_tls13_labels_struct mbedtls_ssl_tls13_labels; - -#define MBEDTLS_SSL_TLS1_3_LBL_LEN(LABEL) \ - sizeof(mbedtls_ssl_tls13_labels.LABEL) - -#define MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN(LABEL) \ - mbedtls_ssl_tls13_labels.LABEL, \ - MBEDTLS_SSL_TLS1_3_LBL_LEN(LABEL) - -#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN \ - sizeof(union mbedtls_ssl_tls13_labels_union) - -/* The maximum length of HKDF contexts used in the TLS 1.3 standard. - * Since contexts are always hashes of message transcripts, this can - * be approximated from above by the maximum hash size. */ -#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN \ - PSA_HASH_MAX_SIZE - -/* Maximum desired length for expanded key material generated - * by HKDF-Expand-Label. - * - * Warning: If this ever needs to be increased, the implementation - * ssl_tls13_hkdf_encode_label() in ssl_tls13_keys.c needs to be - * adjusted since it currently assumes that HKDF key expansion - * is never used with more than 255 Bytes of output. */ -#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN 255 - -/** - * \brief The \c HKDF-Expand-Label function from - * the TLS 1.3 standard RFC 8446. - * - * - * HKDF-Expand-Label( Secret, Label, Context, Length ) = - * HKDF-Expand( Secret, HkdfLabel, Length ) - * - * - * \param hash_alg The identifier for the hash algorithm to use. - * \param secret The \c Secret argument to \c HKDF-Expand-Label. - * This must be a readable buffer of length - * \p secret_len Bytes. - * \param secret_len The length of \p secret in Bytes. - * \param label The \c Label argument to \c HKDF-Expand-Label. - * This must be a readable buffer of length - * \p label_len Bytes. - * \param label_len The length of \p label in Bytes. - * \param ctx The \c Context argument to \c HKDF-Expand-Label. - * This must be a readable buffer of length \p ctx_len Bytes. - * \param ctx_len The length of \p context in Bytes. - * \param buf The destination buffer to hold the expanded secret. - * This must be a writable buffer of length \p buf_len Bytes. - * \param buf_len The desired size of the expanded secret in Bytes. - * - * \returns \c 0 on success. - * \return A negative error code on failure. - */ - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_hkdf_expand_label( - psa_algorithm_t hash_alg, - const unsigned char *secret, size_t secret_len, - const unsigned char *label, size_t label_len, - const unsigned char *ctx, size_t ctx_len, - unsigned char *buf, size_t buf_len); - -/** - * \brief This function is part of the TLS 1.3 key schedule. - * It extracts key and IV for the actual client/server traffic - * from the client/server traffic secrets. - * - * From RFC 8446: - * - * - * [sender]_write_key = HKDF-Expand-Label(Secret, "key", "", key_length) - * [sender]_write_iv = HKDF-Expand-Label(Secret, "iv", "", iv_length)* - * - * - * \param hash_alg The identifier for the hash algorithm to be used - * for the HKDF-based expansion of the secret. - * \param client_secret The client traffic secret. - * This must be a readable buffer of size - * \p secret_len Bytes - * \param server_secret The server traffic secret. - * This must be a readable buffer of size - * \p secret_len Bytes - * \param secret_len Length of the secrets \p client_secret and - * \p server_secret in Bytes. - * \param key_len The desired length of the key to be extracted in Bytes. - * \param iv_len The desired length of the IV to be extracted in Bytes. - * \param keys The address of the structure holding the generated - * keys and IVs. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_make_traffic_keys( - psa_algorithm_t hash_alg, - const unsigned char *client_secret, - const unsigned char *server_secret, size_t secret_len, - size_t key_len, size_t iv_len, - mbedtls_ssl_key_set *keys); - -/** - * \brief The \c Derive-Secret function from the TLS 1.3 standard RFC 8446. - * - * - * Derive-Secret( Secret, Label, Messages ) = - * HKDF-Expand-Label( Secret, Label, - * Hash( Messages ), - * Hash.Length ) ) - * - * - * \param hash_alg The identifier for the hash function used for the - * applications of HKDF. - * \param secret The \c Secret argument to the \c Derive-Secret function. - * This must be a readable buffer of length - * \p secret_len Bytes. - * \param secret_len The length of \p secret in Bytes. - * \param label The \c Label argument to the \c Derive-Secret function. - * This must be a readable buffer of length - * \p label_len Bytes. - * \param label_len The length of \p label in Bytes. - * \param ctx The hash of the \c Messages argument to the - * \c Derive-Secret function, or the \c Messages argument - * itself, depending on \p ctx_hashed. - * \param ctx_len The length of \p ctx in Bytes. - * \param ctx_hashed This indicates whether the \p ctx contains the hash of - * the \c Messages argument in the application of the - * \c Derive-Secret function - * (value MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED), or whether - * it is the content of \c Messages itself, in which case - * the function takes care of the hashing - * (value MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED). - * \param dstbuf The target buffer to write the output of - * \c Derive-Secret to. This must be a writable buffer of - * size \p dtsbuf_len Bytes. - * \param dstbuf_len The length of \p dstbuf in Bytes. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_derive_secret( - psa_algorithm_t hash_alg, - const unsigned char *secret, size_t secret_len, - const unsigned char *label, size_t label_len, - const unsigned char *ctx, size_t ctx_len, - int ctx_hashed, - unsigned char *dstbuf, size_t dstbuf_len); - -/** - * \brief Derive TLS 1.3 early data key material from early secret. - * - * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() - * with the appropriate labels. - * - * - * Early Secret - * | - * +-----> Derive-Secret(., "c e traffic", ClientHello) - * | = client_early_traffic_secret - * | - * +-----> Derive-Secret(., "e exp master", ClientHello) - * . = early_exporter_master_secret - * . - * . - * - * - * \note To obtain the actual key and IV for the early data traffic, - * the client secret derived by this function need to be - * further processed by mbedtls_ssl_tls13_make_traffic_keys(). - * - * \note The binder key, which is also generated from the early secret, - * is omitted here. Its calculation is part of the separate routine - * mbedtls_ssl_tls13_create_psk_binder(). - * - * \param hash_alg The hash algorithm associated with the PSK for which - * early data key material is being derived. - * \param early_secret The early secret from which the early data key material - * should be derived. This must be a readable buffer whose - * length is the digest size of the hash algorithm - * represented by \p md_size. - * \param transcript The transcript of the handshake so far, calculated with - * respect to \p hash_alg. This must be a readable buffer - * whose length is the digest size of the hash algorithm - * represented by \p md_size. - * \param derived The address of the structure in which to store - * the early data key material. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_derive_early_secrets( - psa_algorithm_t hash_alg, - unsigned char const *early_secret, - unsigned char const *transcript, size_t transcript_len, - mbedtls_ssl_tls13_early_secrets *derived); - -/** - * \brief Derive TLS 1.3 handshake key material from the handshake secret. - * - * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() - * with the appropriate labels from the standard. - * - * - * Handshake Secret - * | - * +-----> Derive-Secret( ., "c hs traffic", - * | ClientHello...ServerHello ) - * | = client_handshake_traffic_secret - * | - * +-----> Derive-Secret( ., "s hs traffic", - * . ClientHello...ServerHello ) - * . = server_handshake_traffic_secret - * . - * - * - * \note To obtain the actual key and IV for the encrypted handshake traffic, - * the client and server secret derived by this function need to be - * further processed by mbedtls_ssl_tls13_make_traffic_keys(). - * - * \param hash_alg The hash algorithm associated with the ciphersuite - * that's being used for the connection. - * \param handshake_secret The handshake secret from which the handshake key - * material should be derived. This must be a readable - * buffer whose length is the digest size of the hash - * algorithm represented by \p md_size. - * \param transcript The transcript of the handshake so far, calculated - * with respect to \p hash_alg. This must be a readable - * buffer whose length is the digest size of the hash - * algorithm represented by \p md_size. - * \param derived The address of the structure in which to - * store the handshake key material. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_derive_handshake_secrets( - psa_algorithm_t hash_alg, - unsigned char const *handshake_secret, - unsigned char const *transcript, size_t transcript_len, - mbedtls_ssl_tls13_handshake_secrets *derived); - -/** - * \brief Derive TLS 1.3 application key material from the master secret. - * - * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() - * with the appropriate labels from the standard. - * - * - * Master Secret - * | - * +-----> Derive-Secret( ., "c ap traffic", - * | ClientHello...server Finished ) - * | = client_application_traffic_secret_0 - * | - * +-----> Derive-Secret( ., "s ap traffic", - * | ClientHello...Server Finished ) - * | = server_application_traffic_secret_0 - * | - * +-----> Derive-Secret( ., "exp master", - * . ClientHello...server Finished) - * . = exporter_master_secret - * . - * - * - * \note To obtain the actual key and IV for the (0-th) application traffic, - * the client and server secret derived by this function need to be - * further processed by mbedtls_ssl_tls13_make_traffic_keys(). - * - * \param hash_alg The hash algorithm associated with the ciphersuite - * that's being used for the connection. - * \param master_secret The master secret from which the application key - * material should be derived. This must be a readable - * buffer whose length is the digest size of the hash - * algorithm represented by \p md_size. - * \param transcript The transcript of the handshake up to and including - * the ServerFinished message, calculated with respect - * to \p hash_alg. This must be a readable buffer whose - * length is the digest size of the hash algorithm - * represented by \p hash_alg. - * \param derived The address of the structure in which to - * store the application key material. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_derive_application_secrets( - psa_algorithm_t hash_alg, - unsigned char const *master_secret, - unsigned char const *transcript, size_t transcript_len, - mbedtls_ssl_tls13_application_secrets *derived); - -/** - * \brief Derive TLS 1.3 resumption master secret from the master secret. - * - * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() - * with the appropriate labels from the standard. - * - * \param hash_alg The hash algorithm used in the application for which - * key material is being derived. - * \param application_secret The application secret from which the resumption master - * secret should be derived. This must be a readable - * buffer whose length is the digest size of the hash - * algorithm represented by \p md_size. - * \param transcript The transcript of the handshake up to and including - * the ClientFinished message, calculated with respect - * to \p hash_alg. This must be a readable buffer whose - * length is the digest size of the hash algorithm - * represented by \p hash_alg. - * \param transcript_len The length of \p transcript in Bytes. - * \param derived The address of the structure in which to - * store the resumption master secret. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_derive_resumption_master_secret( - psa_algorithm_t hash_alg, - unsigned char const *application_secret, - unsigned char const *transcript, size_t transcript_len, - mbedtls_ssl_tls13_application_secrets *derived); - -/** - * \brief Compute the next secret in the TLS 1.3 key schedule - * - * The TLS 1.3 key schedule proceeds as follows to compute - * the three main secrets during the handshake: The early - * secret for early data, the handshake secret for all - * other encrypted handshake messages, and the master - * secret for all application traffic. - * - * - * 0 - * | - * v - * PSK -> HKDF-Extract = Early Secret - * | - * v - * Derive-Secret( ., "derived", "" ) - * | - * v - * (EC)DHE -> HKDF-Extract = Handshake Secret - * | - * v - * Derive-Secret( ., "derived", "" ) - * | - * v - * 0 -> HKDF-Extract = Master Secret - * - * - * Each of the three secrets in turn is the basis for further - * key derivations, such as the derivation of traffic keys and IVs; - * see e.g. mbedtls_ssl_tls13_make_traffic_keys(). - * - * This function implements one step in this evolution of secrets: - * - * - * old_secret - * | - * v - * Derive-Secret( ., "derived", "" ) - * | - * v - * input -> HKDF-Extract = new_secret - * - * - * \param hash_alg The identifier for the hash function used for the - * applications of HKDF. - * \param secret_old The address of the buffer holding the old secret - * on function entry. If not \c NULL, this must be a - * readable buffer whose size matches the output size - * of the hash function represented by \p hash_alg. - * If \c NULL, an all \c 0 array will be used instead. - * \param input The address of the buffer holding the additional - * input for the key derivation (e.g., the PSK or the - * ephemeral (EC)DH secret). If not \c NULL, this must be - * a readable buffer whose size \p input_len Bytes. - * If \c NULL, an all \c 0 array will be used instead. - * \param input_len The length of \p input in Bytes. - * \param secret_new The address of the buffer holding the new secret - * on function exit. This must be a writable buffer - * whose size matches the output size of the hash - * function represented by \p hash_alg. - * This may be the same as \p secret_old. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ - -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_evolve_secret( - psa_algorithm_t hash_alg, - const unsigned char *secret_old, - const unsigned char *input, size_t input_len, - unsigned char *secret_new); - -/** - * \brief Calculate a TLS 1.3 PSK binder. - * - * \param ssl The SSL context. This is used for debugging only and may - * be \c NULL if MBEDTLS_DEBUG_C is disabled. - * \param hash_alg The hash algorithm associated to the PSK \p psk. - * \param psk The buffer holding the PSK for which to create a binder. - * \param psk_len The size of \p psk in bytes. - * \param psk_type This indicates whether the PSK \p psk is externally - * provisioned (#MBEDTLS_SSL_TLS1_3_PSK_EXTERNAL) or a - * resumption PSK (#MBEDTLS_SSL_TLS1_3_PSK_RESUMPTION). - * \param transcript The handshake transcript up to the point where the - * PSK binder calculation happens. This must be readable, - * and its size must be equal to the digest size of - * the hash algorithm represented by \p hash_alg. - * \param result The address at which to store the PSK binder on success. - * This must be writable, and its size must be equal to the - * digest size of the hash algorithm represented by - * \p hash_alg. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_create_psk_binder(mbedtls_ssl_context *ssl, - const psa_algorithm_t hash_alg, - unsigned char const *psk, size_t psk_len, - int psk_type, - unsigned char const *transcript, - unsigned char *result); - -/** - * \bref Setup an SSL transform structure representing the - * record protection mechanism used by TLS 1.3 - * - * \param transform The SSL transform structure to be created. This must have - * been initialized through mbedtls_ssl_transform_init() and - * not used in any other way prior to calling this function. - * In particular, this function does not clean up the - * transform structure prior to installing the new keys. - * \param endpoint Indicates whether the transform is for the client - * (value #MBEDTLS_SSL_IS_CLIENT) or the server - * (value #MBEDTLS_SSL_IS_SERVER). - * \param ciphersuite The numerical identifier for the ciphersuite to use. - * This must be one of the identifiers listed in - * ssl_ciphersuites.h. - * \param traffic_keys The key material to use. No reference is stored in - * the SSL transform being generated, and the caller - * should destroy the key material afterwards. - * \param ssl (Debug-only) The SSL context to use for debug output - * in case of failure. This parameter is only needed if - * #MBEDTLS_DEBUG_C is set, and is ignored otherwise. - * - * \return \c 0 on success. In this case, \p transform is ready to - * be used with mbedtls_ssl_transform_decrypt() and - * mbedtls_ssl_transform_encrypt(). - * \return A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_populate_transform(mbedtls_ssl_transform *transform, - int endpoint, - int ciphersuite, - mbedtls_ssl_key_set const *traffic_keys, - mbedtls_ssl_context *ssl); - -/* - * TLS 1.3 key schedule evolutions - * - * Early -> Handshake -> Application - * - * Small wrappers around mbedtls_ssl_tls13_evolve_secret(). - */ - -/** - * \brief Begin TLS 1.3 key schedule by calculating early secret. - * - * The TLS 1.3 key schedule can be viewed as a simple state machine - * with states Initial -> Early -> Handshake -> Application, and - * this function represents the Initial -> Early transition. - * - * \param ssl The SSL context to operate on. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_key_schedule_stage_early(mbedtls_ssl_context *ssl); - -/** - * \brief Compute TLS 1.3 resumption master secret. - * - * \param ssl The SSL context to operate on. This must be in - * key schedule stage \c Application, see - * mbedtls_ssl_tls13_key_schedule_stage_application(). - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_compute_resumption_master_secret(mbedtls_ssl_context *ssl); - -/** - * \brief Calculate the verify_data value for the client or server TLS 1.3 - * Finished message. - * - * \param ssl The SSL context to operate on. This must be in - * key schedule stage \c Handshake, see - * mbedtls_ssl_tls13_key_schedule_stage_application(). - * \param dst The address at which to write the verify_data value. - * \param dst_len The size of \p dst in bytes. - * \param actual_len The address at which to store the amount of data - * actually written to \p dst upon success. - * \param which The message to calculate the `verify_data` for: - * - #MBEDTLS_SSL_IS_CLIENT for the Client's Finished message - * - #MBEDTLS_SSL_IS_SERVER for the Server's Finished message - * - * \note Both client and server call this function twice, once to - * generate their own Finished message, and once to verify the - * peer's Finished message. - - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_calculate_verify_data(mbedtls_ssl_context *ssl, - unsigned char *dst, - size_t dst_len, - size_t *actual_len, - int which); - -#if defined(MBEDTLS_SSL_EARLY_DATA) -/** - * \brief Compute TLS 1.3 early transform - * - * \param ssl The SSL context to operate on. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - * - * \warning The function does not compute the early master secret. Call - * mbedtls_ssl_tls13_key_schedule_stage_early() before to - * call this function to generate the early master secret. - * \note For a client/server endpoint, the function computes only the - * encryption/decryption part of the transform as the decryption/ - * encryption part is not defined by the specification (no early - * traffic from the server to the client). - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_compute_early_transform(mbedtls_ssl_context *ssl); -#endif /* MBEDTLS_SSL_EARLY_DATA */ - -/** - * \brief Compute TLS 1.3 handshake transform - * - * \param ssl The SSL context to operate on. The early secret must have been - * computed. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_compute_handshake_transform(mbedtls_ssl_context *ssl); - -/** - * \brief Compute TLS 1.3 application transform - * - * \param ssl The SSL context to operate on. The early secret must have been - * computed. - * - * \returns \c 0 on success. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_compute_application_transform(mbedtls_ssl_context *ssl); - -#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) -/** - * \brief Export TLS 1.3 PSK from handshake context - * - * \param[in] ssl The SSL context to operate on. - * \param[out] psk PSK output pointer. - * \param[out] psk_len Length of PSK. - * - * \returns \c 0 if there is a configured PSK and it was exported - * successfully. - * \returns A negative error code on failure. - */ -MBEDTLS_CHECK_RETURN_CRITICAL -int mbedtls_ssl_tls13_export_handshake_psk(mbedtls_ssl_context *ssl, - unsigned char **psk, - size_t *psk_len); -#endif - -#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ - -#endif /* MBEDTLS_SSL_TLS1_3_KEYS_H */ +/* + * TLS 1.3 key schedule + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 ( the "License" ); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if !defined(MBEDTLS_SSL_TLS1_3_KEYS_H) +#define MBEDTLS_SSL_TLS1_3_KEYS_H + +/* This requires MBEDTLS_SSL_TLS1_3_LABEL( idx, name, string ) to be defined at + * the point of use. See e.g. the definition of mbedtls_ssl_tls13_labels_union + * below. */ +#define MBEDTLS_SSL_TLS1_3_LABEL_LIST \ + MBEDTLS_SSL_TLS1_3_LABEL(finished, "finished") \ + MBEDTLS_SSL_TLS1_3_LABEL(resumption, "resumption") \ + MBEDTLS_SSL_TLS1_3_LABEL(traffic_upd, "traffic upd") \ + MBEDTLS_SSL_TLS1_3_LABEL(exporter, "exporter") \ + MBEDTLS_SSL_TLS1_3_LABEL(key, "key") \ + MBEDTLS_SSL_TLS1_3_LABEL(iv, "iv") \ + MBEDTLS_SSL_TLS1_3_LABEL(c_hs_traffic, "c hs traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(c_ap_traffic, "c ap traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(c_e_traffic, "c e traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(s_hs_traffic, "s hs traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(s_ap_traffic, "s ap traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(s_e_traffic, "s e traffic") \ + MBEDTLS_SSL_TLS1_3_LABEL(e_exp_master, "e exp master") \ + MBEDTLS_SSL_TLS1_3_LABEL(res_master, "res master") \ + MBEDTLS_SSL_TLS1_3_LABEL(exp_master, "exp master") \ + MBEDTLS_SSL_TLS1_3_LABEL(ext_binder, "ext binder") \ + MBEDTLS_SSL_TLS1_3_LABEL(res_binder, "res binder") \ + MBEDTLS_SSL_TLS1_3_LABEL(derived, "derived") \ + MBEDTLS_SSL_TLS1_3_LABEL(client_cv, "TLS 1.3, client CertificateVerify") \ + MBEDTLS_SSL_TLS1_3_LABEL(server_cv, "TLS 1.3, server CertificateVerify") + +#define MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED 0 +#define MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED 1 + +#define MBEDTLS_SSL_TLS1_3_PSK_EXTERNAL 0 +#define MBEDTLS_SSL_TLS1_3_PSK_RESUMPTION 1 + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3) + +#define MBEDTLS_SSL_TLS1_3_LABEL(name, string) \ + const unsigned char name [sizeof(string) - 1]; + +union mbedtls_ssl_tls13_labels_union { + MBEDTLS_SSL_TLS1_3_LABEL_LIST +}; +struct mbedtls_ssl_tls13_labels_struct { + MBEDTLS_SSL_TLS1_3_LABEL_LIST +}; +#undef MBEDTLS_SSL_TLS1_3_LABEL + +extern const struct mbedtls_ssl_tls13_labels_struct mbedtls_ssl_tls13_labels; + +#define MBEDTLS_SSL_TLS1_3_LBL_LEN(LABEL) \ + sizeof(mbedtls_ssl_tls13_labels.LABEL) + +#define MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN(LABEL) \ + mbedtls_ssl_tls13_labels.LABEL, \ + MBEDTLS_SSL_TLS1_3_LBL_LEN(LABEL) + +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN \ + sizeof(union mbedtls_ssl_tls13_labels_union) + +/* The maximum length of HKDF contexts used in the TLS 1.3 standard. + * Since contexts are always hashes of message transcripts, this can + * be approximated from above by the maximum hash size. */ +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN \ + PSA_HASH_MAX_SIZE + +/* Maximum desired length for expanded key material generated + * by HKDF-Expand-Label. + * + * Warning: If this ever needs to be increased, the implementation + * ssl_tls13_hkdf_encode_label() in ssl_tls13_keys.c needs to be + * adjusted since it currently assumes that HKDF key expansion + * is never used with more than 255 Bytes of output. */ +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN 255 + +/** + * \brief The \c HKDF-Expand-Label function from + * the TLS 1.3 standard RFC 8446. + * + * + * HKDF-Expand-Label( Secret, Label, Context, Length ) = + * HKDF-Expand( Secret, HkdfLabel, Length ) + * + * + * \param hash_alg The identifier for the hash algorithm to use. + * \param secret The \c Secret argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length + * \p secret_len Bytes. + * \param secret_len The length of \p secret in Bytes. + * \param label The \c Label argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length + * \p label_len Bytes. + * \param label_len The length of \p label in Bytes. + * \param ctx The \c Context argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length \p ctx_len Bytes. + * \param ctx_len The length of \p context in Bytes. + * \param buf The destination buffer to hold the expanded secret. + * This must be a writable buffer of length \p buf_len Bytes. + * \param buf_len The desired size of the expanded secret in Bytes. + * + * \returns \c 0 on success. + * \return A negative error code on failure. + */ + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_hkdf_expand_label( + psa_algorithm_t hash_alg, + const unsigned char *secret, size_t secret_len, + const unsigned char *label, size_t label_len, + const unsigned char *ctx, size_t ctx_len, + unsigned char *buf, size_t buf_len); + +/** + * \brief This function is part of the TLS 1.3 key schedule. + * It extracts key and IV for the actual client/server traffic + * from the client/server traffic secrets. + * + * From RFC 8446: + * + * + * [sender]_write_key = HKDF-Expand-Label(Secret, "key", "", key_length) + * [sender]_write_iv = HKDF-Expand-Label(Secret, "iv", "", iv_length)* + * + * + * \param hash_alg The identifier for the hash algorithm to be used + * for the HKDF-based expansion of the secret. + * \param client_secret The client traffic secret. + * This must be a readable buffer of size + * \p secret_len Bytes + * \param server_secret The server traffic secret. + * This must be a readable buffer of size + * \p secret_len Bytes + * \param secret_len Length of the secrets \p client_secret and + * \p server_secret in Bytes. + * \param key_len The desired length of the key to be extracted in Bytes. + * \param iv_len The desired length of the IV to be extracted in Bytes. + * \param keys The address of the structure holding the generated + * keys and IVs. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_make_traffic_keys( + psa_algorithm_t hash_alg, + const unsigned char *client_secret, + const unsigned char *server_secret, size_t secret_len, + size_t key_len, size_t iv_len, + mbedtls_ssl_key_set *keys); + +/** + * \brief The \c Derive-Secret function from the TLS 1.3 standard RFC 8446. + * + * + * Derive-Secret( Secret, Label, Messages ) = + * HKDF-Expand-Label( Secret, Label, + * Hash( Messages ), + * Hash.Length ) ) + * + * + * \param hash_alg The identifier for the hash function used for the + * applications of HKDF. + * \param secret The \c Secret argument to the \c Derive-Secret function. + * This must be a readable buffer of length + * \p secret_len Bytes. + * \param secret_len The length of \p secret in Bytes. + * \param label The \c Label argument to the \c Derive-Secret function. + * This must be a readable buffer of length + * \p label_len Bytes. + * \param label_len The length of \p label in Bytes. + * \param ctx The hash of the \c Messages argument to the + * \c Derive-Secret function, or the \c Messages argument + * itself, depending on \p ctx_hashed. + * \param ctx_len The length of \p ctx in Bytes. + * \param ctx_hashed This indicates whether the \p ctx contains the hash of + * the \c Messages argument in the application of the + * \c Derive-Secret function + * (value MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED), or whether + * it is the content of \c Messages itself, in which case + * the function takes care of the hashing + * (value MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED). + * \param dstbuf The target buffer to write the output of + * \c Derive-Secret to. This must be a writable buffer of + * size \p dtsbuf_len Bytes. + * \param dstbuf_len The length of \p dstbuf in Bytes. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_derive_secret( + psa_algorithm_t hash_alg, + const unsigned char *secret, size_t secret_len, + const unsigned char *label, size_t label_len, + const unsigned char *ctx, size_t ctx_len, + int ctx_hashed, + unsigned char *dstbuf, size_t dstbuf_len); + +/** + * \brief Derive TLS 1.3 early data key material from early secret. + * + * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() + * with the appropriate labels. + * + * + * Early Secret + * | + * +-----> Derive-Secret(., "c e traffic", ClientHello) + * | = client_early_traffic_secret + * | + * +-----> Derive-Secret(., "e exp master", ClientHello) + * . = early_exporter_master_secret + * . + * . + * + * + * \note To obtain the actual key and IV for the early data traffic, + * the client secret derived by this function need to be + * further processed by mbedtls_ssl_tls13_make_traffic_keys(). + * + * \note The binder key, which is also generated from the early secret, + * is omitted here. Its calculation is part of the separate routine + * mbedtls_ssl_tls13_create_psk_binder(). + * + * \param hash_alg The hash algorithm associated with the PSK for which + * early data key material is being derived. + * \param early_secret The early secret from which the early data key material + * should be derived. This must be a readable buffer whose + * length is the digest size of the hash algorithm + * represented by \p md_size. + * \param transcript The transcript of the handshake so far, calculated with + * respect to \p hash_alg. This must be a readable buffer + * whose length is the digest size of the hash algorithm + * represented by \p md_size. + * \param derived The address of the structure in which to store + * the early data key material. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_derive_early_secrets( + psa_algorithm_t hash_alg, + unsigned char const *early_secret, + unsigned char const *transcript, size_t transcript_len, + mbedtls_ssl_tls13_early_secrets *derived); + +/** + * \brief Derive TLS 1.3 handshake key material from the handshake secret. + * + * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() + * with the appropriate labels from the standard. + * + * + * Handshake Secret + * | + * +-----> Derive-Secret( ., "c hs traffic", + * | ClientHello...ServerHello ) + * | = client_handshake_traffic_secret + * | + * +-----> Derive-Secret( ., "s hs traffic", + * . ClientHello...ServerHello ) + * . = server_handshake_traffic_secret + * . + * + * + * \note To obtain the actual key and IV for the encrypted handshake traffic, + * the client and server secret derived by this function need to be + * further processed by mbedtls_ssl_tls13_make_traffic_keys(). + * + * \param hash_alg The hash algorithm associated with the ciphersuite + * that's being used for the connection. + * \param handshake_secret The handshake secret from which the handshake key + * material should be derived. This must be a readable + * buffer whose length is the digest size of the hash + * algorithm represented by \p md_size. + * \param transcript The transcript of the handshake so far, calculated + * with respect to \p hash_alg. This must be a readable + * buffer whose length is the digest size of the hash + * algorithm represented by \p md_size. + * \param derived The address of the structure in which to + * store the handshake key material. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_derive_handshake_secrets( + psa_algorithm_t hash_alg, + unsigned char const *handshake_secret, + unsigned char const *transcript, size_t transcript_len, + mbedtls_ssl_tls13_handshake_secrets *derived); + +/** + * \brief Derive TLS 1.3 application key material from the master secret. + * + * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() + * with the appropriate labels from the standard. + * + * + * Master Secret + * | + * +-----> Derive-Secret( ., "c ap traffic", + * | ClientHello...server Finished ) + * | = client_application_traffic_secret_0 + * | + * +-----> Derive-Secret( ., "s ap traffic", + * | ClientHello...Server Finished ) + * | = server_application_traffic_secret_0 + * | + * +-----> Derive-Secret( ., "exp master", + * . ClientHello...server Finished) + * . = exporter_master_secret + * . + * + * + * \note To obtain the actual key and IV for the (0-th) application traffic, + * the client and server secret derived by this function need to be + * further processed by mbedtls_ssl_tls13_make_traffic_keys(). + * + * \param hash_alg The hash algorithm associated with the ciphersuite + * that's being used for the connection. + * \param master_secret The master secret from which the application key + * material should be derived. This must be a readable + * buffer whose length is the digest size of the hash + * algorithm represented by \p md_size. + * \param transcript The transcript of the handshake up to and including + * the ServerFinished message, calculated with respect + * to \p hash_alg. This must be a readable buffer whose + * length is the digest size of the hash algorithm + * represented by \p hash_alg. + * \param derived The address of the structure in which to + * store the application key material. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_derive_application_secrets( + psa_algorithm_t hash_alg, + unsigned char const *master_secret, + unsigned char const *transcript, size_t transcript_len, + mbedtls_ssl_tls13_application_secrets *derived); + +/** + * \brief Derive TLS 1.3 resumption master secret from the master secret. + * + * This is a small wrapper invoking mbedtls_ssl_tls13_derive_secret() + * with the appropriate labels from the standard. + * + * \param hash_alg The hash algorithm used in the application for which + * key material is being derived. + * \param application_secret The application secret from which the resumption master + * secret should be derived. This must be a readable + * buffer whose length is the digest size of the hash + * algorithm represented by \p md_size. + * \param transcript The transcript of the handshake up to and including + * the ClientFinished message, calculated with respect + * to \p hash_alg. This must be a readable buffer whose + * length is the digest size of the hash algorithm + * represented by \p hash_alg. + * \param transcript_len The length of \p transcript in Bytes. + * \param derived The address of the structure in which to + * store the resumption master secret. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_derive_resumption_master_secret( + psa_algorithm_t hash_alg, + unsigned char const *application_secret, + unsigned char const *transcript, size_t transcript_len, + mbedtls_ssl_tls13_application_secrets *derived); + +/** + * \brief Compute the next secret in the TLS 1.3 key schedule + * + * The TLS 1.3 key schedule proceeds as follows to compute + * the three main secrets during the handshake: The early + * secret for early data, the handshake secret for all + * other encrypted handshake messages, and the master + * secret for all application traffic. + * + * + * 0 + * | + * v + * PSK -> HKDF-Extract = Early Secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * (EC)DHE -> HKDF-Extract = Handshake Secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * 0 -> HKDF-Extract = Master Secret + * + * + * Each of the three secrets in turn is the basis for further + * key derivations, such as the derivation of traffic keys and IVs; + * see e.g. mbedtls_ssl_tls13_make_traffic_keys(). + * + * This function implements one step in this evolution of secrets: + * + * + * old_secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * input -> HKDF-Extract = new_secret + * + * + * \param hash_alg The identifier for the hash function used for the + * applications of HKDF. + * \param secret_old The address of the buffer holding the old secret + * on function entry. If not \c NULL, this must be a + * readable buffer whose size matches the output size + * of the hash function represented by \p hash_alg. + * If \c NULL, an all \c 0 array will be used instead. + * \param input The address of the buffer holding the additional + * input for the key derivation (e.g., the PSK or the + * ephemeral (EC)DH secret). If not \c NULL, this must be + * a readable buffer whose size \p input_len Bytes. + * If \c NULL, an all \c 0 array will be used instead. + * \param input_len The length of \p input in Bytes. + * \param secret_new The address of the buffer holding the new secret + * on function exit. This must be a writable buffer + * whose size matches the output size of the hash + * function represented by \p hash_alg. + * This may be the same as \p secret_old. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ + +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_evolve_secret( + psa_algorithm_t hash_alg, + const unsigned char *secret_old, + const unsigned char *input, size_t input_len, + unsigned char *secret_new); + +/** + * \brief Calculate a TLS 1.3 PSK binder. + * + * \param ssl The SSL context. This is used for debugging only and may + * be \c NULL if MBEDTLS_DEBUG_C is disabled. + * \param hash_alg The hash algorithm associated to the PSK \p psk. + * \param psk The buffer holding the PSK for which to create a binder. + * \param psk_len The size of \p psk in bytes. + * \param psk_type This indicates whether the PSK \p psk is externally + * provisioned (#MBEDTLS_SSL_TLS1_3_PSK_EXTERNAL) or a + * resumption PSK (#MBEDTLS_SSL_TLS1_3_PSK_RESUMPTION). + * \param transcript The handshake transcript up to the point where the + * PSK binder calculation happens. This must be readable, + * and its size must be equal to the digest size of + * the hash algorithm represented by \p hash_alg. + * \param result The address at which to store the PSK binder on success. + * This must be writable, and its size must be equal to the + * digest size of the hash algorithm represented by + * \p hash_alg. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_create_psk_binder(mbedtls_ssl_context *ssl, + const psa_algorithm_t hash_alg, + unsigned char const *psk, size_t psk_len, + int psk_type, + unsigned char const *transcript, + unsigned char *result); + +/** + * \bref Setup an SSL transform structure representing the + * record protection mechanism used by TLS 1.3 + * + * \param transform The SSL transform structure to be created. This must have + * been initialized through mbedtls_ssl_transform_init() and + * not used in any other way prior to calling this function. + * In particular, this function does not clean up the + * transform structure prior to installing the new keys. + * \param endpoint Indicates whether the transform is for the client + * (value #MBEDTLS_SSL_IS_CLIENT) or the server + * (value #MBEDTLS_SSL_IS_SERVER). + * \param ciphersuite The numerical identifier for the ciphersuite to use. + * This must be one of the identifiers listed in + * ssl_ciphersuites.h. + * \param traffic_keys The key material to use. No reference is stored in + * the SSL transform being generated, and the caller + * should destroy the key material afterwards. + * \param ssl (Debug-only) The SSL context to use for debug output + * in case of failure. This parameter is only needed if + * #MBEDTLS_DEBUG_C is set, and is ignored otherwise. + * + * \return \c 0 on success. In this case, \p transform is ready to + * be used with mbedtls_ssl_transform_decrypt() and + * mbedtls_ssl_transform_encrypt(). + * \return A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_populate_transform(mbedtls_ssl_transform *transform, + int endpoint, + int ciphersuite, + mbedtls_ssl_key_set const *traffic_keys, + mbedtls_ssl_context *ssl); + +/* + * TLS 1.3 key schedule evolutions + * + * Early -> Handshake -> Application + * + * Small wrappers around mbedtls_ssl_tls13_evolve_secret(). + */ + +/** + * \brief Begin TLS 1.3 key schedule by calculating early secret. + * + * The TLS 1.3 key schedule can be viewed as a simple state machine + * with states Initial -> Early -> Handshake -> Application, and + * this function represents the Initial -> Early transition. + * + * \param ssl The SSL context to operate on. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_key_schedule_stage_early(mbedtls_ssl_context *ssl); + +/** + * \brief Compute TLS 1.3 resumption master secret. + * + * \param ssl The SSL context to operate on. This must be in + * key schedule stage \c Application, see + * mbedtls_ssl_tls13_key_schedule_stage_application(). + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_compute_resumption_master_secret(mbedtls_ssl_context *ssl); + +/** + * \brief Calculate the verify_data value for the client or server TLS 1.3 + * Finished message. + * + * \param ssl The SSL context to operate on. This must be in + * key schedule stage \c Handshake, see + * mbedtls_ssl_tls13_key_schedule_stage_application(). + * \param dst The address at which to write the verify_data value. + * \param dst_len The size of \p dst in bytes. + * \param actual_len The address at which to store the amount of data + * actually written to \p dst upon success. + * \param which The message to calculate the `verify_data` for: + * - #MBEDTLS_SSL_IS_CLIENT for the Client's Finished message + * - #MBEDTLS_SSL_IS_SERVER for the Server's Finished message + * + * \note Both client and server call this function twice, once to + * generate their own Finished message, and once to verify the + * peer's Finished message. + + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_calculate_verify_data(mbedtls_ssl_context *ssl, + unsigned char *dst, + size_t dst_len, + size_t *actual_len, + int which); + +#if defined(MBEDTLS_SSL_EARLY_DATA) +/** + * \brief Compute TLS 1.3 early transform + * + * \param ssl The SSL context to operate on. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + * + * \warning The function does not compute the early master secret. Call + * mbedtls_ssl_tls13_key_schedule_stage_early() before to + * call this function to generate the early master secret. + * \note For a client/server endpoint, the function computes only the + * encryption/decryption part of the transform as the decryption/ + * encryption part is not defined by the specification (no early + * traffic from the server to the client). + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_compute_early_transform(mbedtls_ssl_context *ssl); +#endif /* MBEDTLS_SSL_EARLY_DATA */ + +/** + * \brief Compute TLS 1.3 handshake transform + * + * \param ssl The SSL context to operate on. The early secret must have been + * computed. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_compute_handshake_transform(mbedtls_ssl_context *ssl); + +/** + * \brief Compute TLS 1.3 application transform + * + * \param ssl The SSL context to operate on. The early secret must have been + * computed. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_compute_application_transform(mbedtls_ssl_context *ssl); + +#if defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_SOME_PSK_ENABLED) +/** + * \brief Export TLS 1.3 PSK from handshake context + * + * \param[in] ssl The SSL context to operate on. + * \param[out] psk PSK output pointer. + * \param[out] psk_len Length of PSK. + * + * \returns \c 0 if there is a configured PSK and it was exported + * successfully. + * \returns A negative error code on failure. + */ +MBEDTLS_CHECK_RETURN_CRITICAL +int mbedtls_ssl_tls13_export_handshake_psk(mbedtls_ssl_context *ssl, + unsigned char **psk, + size_t *psk_len); +#endif + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3 */ + +#endif /* MBEDTLS_SSL_TLS1_3_KEYS_H */ diff --git a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/threading.c b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/threading.c index 0319de8..be258dc 100644 --- a/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/threading.c +++ b/locator_ncp/gecko_sdk_4.4.1/util/third_party/mbedtls/library/threading.c @@ -1,200 +1,200 @@ -/* - * Threading abstraction layer - * - * Copyright The Mbed TLS Contributors - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Ensure gmtime_r is available even with -std=c99; must be defined before - * mbedtls_config.h, which pulls in glibc's features.h. Harmless on other platforms. - */ -#if !defined(_POSIX_C_SOURCE) -#define _POSIX_C_SOURCE 200112L -#endif - -#include "common.h" - -#if defined(MBEDTLS_THREADING_C) - -#include "mbedtls/threading.h" - -#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) - -#if !defined(_WIN32) && (defined(unix) || \ - defined(__unix) || defined(__unix__) || (defined(__APPLE__) && \ - defined(__MACH__))) -#include -#endif /* !_WIN32 && (unix || __unix || __unix__ || - * (__APPLE__ && __MACH__)) */ - -#if !((defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L) || \ - (defined(_POSIX_THREAD_SAFE_FUNCTIONS) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L)) -/* - * This is a convenience shorthand macro to avoid checking the long - * preprocessor conditions above. Ideally, we could expose this macro in - * platform_util.h and simply use it in platform_util.c, threading.c and - * threading.h. However, this macro is not part of the Mbed TLS public API, so - * we keep it private by only defining it in this file - */ - -#if !(defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)) -#define THREADING_USE_GMTIME -#endif /* ! ( defined(_WIN32) && !defined(EFIX64) && !defined(EFI32) ) */ - -#endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ - ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ - -#endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */ - -#if defined(MBEDTLS_THREADING_PTHREAD) -static void threading_mutex_init_pthread(mbedtls_threading_mutex_t *mutex) -{ - if (mutex == NULL) { - return; - } - - /* A nonzero value of is_valid indicates a successfully initialized - * mutex. This is a workaround for not being able to return an error - * code for this function. The lock/unlock functions return an error - * if is_valid is nonzero. The Mbed TLS unit test code uses this field - * to distinguish more states of the mutex; see - * tests/src/threading_helpers for details. */ - mutex->is_valid = pthread_mutex_init(&mutex->mutex, NULL) == 0; -} - -static void threading_mutex_free_pthread(mbedtls_threading_mutex_t *mutex) -{ - if (mutex == NULL || !mutex->is_valid) { - return; - } - - (void) pthread_mutex_destroy(&mutex->mutex); - mutex->is_valid = 0; -} - -static int threading_mutex_lock_pthread(mbedtls_threading_mutex_t *mutex) -{ - if (mutex == NULL || !mutex->is_valid) { - return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; - } - - if (pthread_mutex_lock(&mutex->mutex) != 0) { - return MBEDTLS_ERR_THREADING_MUTEX_ERROR; - } - - return 0; -} - -static int threading_mutex_unlock_pthread(mbedtls_threading_mutex_t *mutex) -{ - if (mutex == NULL || !mutex->is_valid) { - return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; - } - - if (pthread_mutex_unlock(&mutex->mutex) != 0) { - return MBEDTLS_ERR_THREADING_MUTEX_ERROR; - } - - return 0; -} - -void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *) = threading_mutex_init_pthread; -void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *) = threading_mutex_free_pthread; -int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *) = threading_mutex_lock_pthread; -int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *) = threading_mutex_unlock_pthread; - -/* - * With pthreads we can statically initialize mutexes - */ -#define MUTEX_INIT = { PTHREAD_MUTEX_INITIALIZER, 1 } - -#endif /* MBEDTLS_THREADING_PTHREAD */ - -#if defined(MBEDTLS_THREADING_ALT) -static int threading_mutex_fail(mbedtls_threading_mutex_t *mutex) -{ - ((void) mutex); - return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; -} -static void threading_mutex_dummy(mbedtls_threading_mutex_t *mutex) -{ - ((void) mutex); - return; -} - -void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *) = threading_mutex_dummy; -void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *) = threading_mutex_dummy; -int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *) = threading_mutex_fail; -int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *) = threading_mutex_fail; - -/* - * Set functions pointers and initialize global mutexes - */ -void mbedtls_threading_set_alt(void (*mutex_init)(mbedtls_threading_mutex_t *), - void (*mutex_free)(mbedtls_threading_mutex_t *), - int (*mutex_lock)(mbedtls_threading_mutex_t *), - int (*mutex_unlock)(mbedtls_threading_mutex_t *)) -{ - mbedtls_mutex_init = mutex_init; - mbedtls_mutex_free = mutex_free; - mbedtls_mutex_lock = mutex_lock; - mbedtls_mutex_unlock = mutex_unlock; - -#if defined(MBEDTLS_FS_IO) - mbedtls_mutex_init(&mbedtls_threading_readdir_mutex); -#endif -#if defined(THREADING_USE_GMTIME) - mbedtls_mutex_init(&mbedtls_threading_gmtime_mutex); -#endif -} - -/* - * Free global mutexes - */ -void mbedtls_threading_free_alt(void) -{ -#if defined(MBEDTLS_FS_IO) - mbedtls_mutex_free(&mbedtls_threading_readdir_mutex); -#endif -#if defined(THREADING_USE_GMTIME) - mbedtls_mutex_free(&mbedtls_threading_gmtime_mutex); -#endif -} -#endif /* MBEDTLS_THREADING_ALT */ - -/* - * Define global mutexes - */ -#ifndef MUTEX_INIT -#define MUTEX_INIT -#endif -#if defined(MBEDTLS_FS_IO) -mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex MUTEX_INIT; -#endif -#if defined(MBEDTLS_PSA_CRYPTO_C) -/* - * psa_crypto_slot_management.c global data mutex. - */ -mbedtls_threading_mutex_t mbedtls_psa_slots_mutex MUTEX_INIT; -#endif - -#if defined(THREADING_USE_GMTIME) -mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex MUTEX_INIT; -#endif - -#endif /* MBEDTLS_THREADING_C */ +/* + * Threading abstraction layer + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Ensure gmtime_r is available even with -std=c99; must be defined before + * mbedtls_config.h, which pulls in glibc's features.h. Harmless on other platforms. + */ +#if !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 200112L +#endif + +#include "common.h" + +#if defined(MBEDTLS_THREADING_C) + +#include "mbedtls/threading.h" + +#if defined(MBEDTLS_HAVE_TIME_DATE) && !defined(MBEDTLS_PLATFORM_GMTIME_R_ALT) + +#if !defined(_WIN32) && (defined(unix) || \ + defined(__unix) || defined(__unix__) || (defined(__APPLE__) && \ + defined(__MACH__))) +#include +#endif /* !_WIN32 && (unix || __unix || __unix__ || + * (__APPLE__ && __MACH__)) */ + +#if !((defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L) || \ + (defined(_POSIX_THREAD_SAFE_FUNCTIONS) && \ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L)) +/* + * This is a convenience shorthand macro to avoid checking the long + * preprocessor conditions above. Ideally, we could expose this macro in + * platform_util.h and simply use it in platform_util.c, threading.c and + * threading.h. However, this macro is not part of the Mbed TLS public API, so + * we keep it private by only defining it in this file + */ + +#if !(defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)) +#define THREADING_USE_GMTIME +#endif /* ! ( defined(_WIN32) && !defined(EFIX64) && !defined(EFI32) ) */ + +#endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ + ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ + +#endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */ + +#if defined(MBEDTLS_THREADING_PTHREAD) +static void threading_mutex_init_pthread(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL) { + return; + } + + /* A nonzero value of is_valid indicates a successfully initialized + * mutex. This is a workaround for not being able to return an error + * code for this function. The lock/unlock functions return an error + * if is_valid is nonzero. The Mbed TLS unit test code uses this field + * to distinguish more states of the mutex; see + * tests/src/threading_helpers for details. */ + mutex->is_valid = pthread_mutex_init(&mutex->mutex, NULL) == 0; +} + +static void threading_mutex_free_pthread(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL || !mutex->is_valid) { + return; + } + + (void) pthread_mutex_destroy(&mutex->mutex); + mutex->is_valid = 0; +} + +static int threading_mutex_lock_pthread(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL || !mutex->is_valid) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + + if (pthread_mutex_lock(&mutex->mutex) != 0) { + return MBEDTLS_ERR_THREADING_MUTEX_ERROR; + } + + return 0; +} + +static int threading_mutex_unlock_pthread(mbedtls_threading_mutex_t *mutex) +{ + if (mutex == NULL || !mutex->is_valid) { + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; + } + + if (pthread_mutex_unlock(&mutex->mutex) != 0) { + return MBEDTLS_ERR_THREADING_MUTEX_ERROR; + } + + return 0; +} + +void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *) = threading_mutex_init_pthread; +void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *) = threading_mutex_free_pthread; +int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *) = threading_mutex_lock_pthread; +int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *) = threading_mutex_unlock_pthread; + +/* + * With pthreads we can statically initialize mutexes + */ +#define MUTEX_INIT = { PTHREAD_MUTEX_INITIALIZER, 1 } + +#endif /* MBEDTLS_THREADING_PTHREAD */ + +#if defined(MBEDTLS_THREADING_ALT) +static int threading_mutex_fail(mbedtls_threading_mutex_t *mutex) +{ + ((void) mutex); + return MBEDTLS_ERR_THREADING_BAD_INPUT_DATA; +} +static void threading_mutex_dummy(mbedtls_threading_mutex_t *mutex) +{ + ((void) mutex); + return; +} + +void (*mbedtls_mutex_init)(mbedtls_threading_mutex_t *) = threading_mutex_dummy; +void (*mbedtls_mutex_free)(mbedtls_threading_mutex_t *) = threading_mutex_dummy; +int (*mbedtls_mutex_lock)(mbedtls_threading_mutex_t *) = threading_mutex_fail; +int (*mbedtls_mutex_unlock)(mbedtls_threading_mutex_t *) = threading_mutex_fail; + +/* + * Set functions pointers and initialize global mutexes + */ +void mbedtls_threading_set_alt(void (*mutex_init)(mbedtls_threading_mutex_t *), + void (*mutex_free)(mbedtls_threading_mutex_t *), + int (*mutex_lock)(mbedtls_threading_mutex_t *), + int (*mutex_unlock)(mbedtls_threading_mutex_t *)) +{ + mbedtls_mutex_init = mutex_init; + mbedtls_mutex_free = mutex_free; + mbedtls_mutex_lock = mutex_lock; + mbedtls_mutex_unlock = mutex_unlock; + +#if defined(MBEDTLS_FS_IO) + mbedtls_mutex_init(&mbedtls_threading_readdir_mutex); +#endif +#if defined(THREADING_USE_GMTIME) + mbedtls_mutex_init(&mbedtls_threading_gmtime_mutex); +#endif +} + +/* + * Free global mutexes + */ +void mbedtls_threading_free_alt(void) +{ +#if defined(MBEDTLS_FS_IO) + mbedtls_mutex_free(&mbedtls_threading_readdir_mutex); +#endif +#if defined(THREADING_USE_GMTIME) + mbedtls_mutex_free(&mbedtls_threading_gmtime_mutex); +#endif +} +#endif /* MBEDTLS_THREADING_ALT */ + +/* + * Define global mutexes + */ +#ifndef MUTEX_INIT +#define MUTEX_INIT +#endif +#if defined(MBEDTLS_FS_IO) +mbedtls_threading_mutex_t mbedtls_threading_readdir_mutex MUTEX_INIT; +#endif +#if defined(MBEDTLS_PSA_CRYPTO_C) +/* + * psa_crypto_slot_management.c global data mutex. + */ +mbedtls_threading_mutex_t mbedtls_psa_slots_mutex MUTEX_INIT; +#endif + +#if defined(THREADING_USE_GMTIME) +mbedtls_threading_mutex_t mbedtls_threading_gmtime_mutex MUTEX_INIT; +#endif + +#endif /* MBEDTLS_THREADING_C */ diff --git a/locator_ncp/locator_ncp.pintool b/locator_ncp/locator_ncp.pintool index a18b348..215b711 100644 --- a/locator_ncp/locator_ncp.pintool +++ b/locator_ncp/locator_ncp.pintool @@ -1,31 +1,31 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/locator_ncp/locator_ncp.slcp b/locator_ncp/locator_ncp.slcp index 810ee97..9778630 100644 --- a/locator_ncp/locator_ncp.slcp +++ b/locator_ncp/locator_ncp.slcp @@ -1,71 +1,71 @@ -# Silicon Labs Project Configuration Tools: slcp, v0, Component selection file. -project_name: locator_ncp -label: locator_ncp -description: | - Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. -category: Bluetooth AoX Examples -filter: -- name: Device Type - value: [NCP] -- name: Project Difficulty - value: [Advanced] -- name: Wireless Technology - value: [Bluetooth] -package: Bluetooth -quality: production -readme: -- {path: readme.md} -source: -- {path: main.c} -- {path: app.c} -tag: [prebuilt_demo, 'hardware:rf:band:2400'] -include: -- path: '' - file_list: - - {path: app.h} -sdk: {id: gecko_sdk, version: 4.4.1} -toolchain_settings: [] -component: -- {id: bluetooth_feature_nvm} -- {id: bluetooth_feature_sync} -- {id: bluetooth_feature_gatt_server} -- {id: bluetooth_feature_sm} -- {id: bluetooth_feature_legacy_advertiser} -- {id: bluetooth_feature_gap} -- {id: mpu} -- {id: bluetooth_feature_extended_advertiser} -- {id: bluetooth_stack} -- {id: ncp} -- {id: device_init} -- {id: brd4002a} -- {id: bluetooth_feature_gatt} -- {id: bluetooth_feature_periodic_advertiser} -- {id: brd4185a} -- instance: [vcom] - id: uartdrv_usart -- {id: bt_post_build} -- {id: sl_system} -- {id: bluetooth_feature_connection} -- {id: bluetooth_feature_aoa_receiver} -- {id: bluetooth_feature_dynamic_gattdb} -- {id: bluetooth_feature_system} -- {id: bluetooth_feature_scanner} -- {id: bootloader_interface} -- {id: EFR32BG22C224F512IM40} -other_file: -- {path: image/readme_img0.png} -- {path: image/readme_img1.png} -- {path: image/readme_img2.png} -configuration: -- {name: SL_STACK_SIZE, value: '2752'} -- {name: SL_HEAP_SIZE, value: '12000'} -- {name: SL_BT_CONFIG_USER_ADVERTISERS, value: '4'} -- {name: SL_BOARD_ENABLE_VCOM, value: '1'} -- {name: SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, value: uartdrvFlowControlHw} -- {name: SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC, value: '8'} -- condition: [psa_crypto] - name: SL_PSA_KEY_USER_SLOT_COUNT - value: '0' -ui_hints: - highlight: - - {path: readme.md, focus: true} +# Silicon Labs Project Configuration Tools: slcp, v0, Component selection file. +project_name: locator_ncp +label: locator_ncp +description: | + Network Co-Processor (NCP) target application extended with CTE Receiver support. It enables Angle of Arrival (AoA) calculation. Use this application with Direction Finding host examples. +category: Bluetooth AoX Examples +filter: +- name: Device Type + value: [NCP] +- name: Project Difficulty + value: [Advanced] +- name: Wireless Technology + value: [Bluetooth] +package: Bluetooth +quality: production +readme: +- {path: readme.md} +source: +- {path: main.c} +- {path: app.c} +tag: [prebuilt_demo, 'hardware:rf:band:2400'] +include: +- path: '' + file_list: + - {path: app.h} +sdk: {id: gecko_sdk, version: 4.4.1} +toolchain_settings: [] +component: +- {id: bluetooth_feature_nvm} +- {id: bluetooth_feature_sync} +- {id: bluetooth_feature_gatt_server} +- {id: bluetooth_feature_sm} +- {id: bluetooth_feature_legacy_advertiser} +- {id: bluetooth_feature_gap} +- {id: mpu} +- {id: bluetooth_feature_extended_advertiser} +- {id: bluetooth_stack} +- {id: ncp} +- {id: device_init} +- {id: brd4002a} +- {id: bluetooth_feature_gatt} +- {id: bluetooth_feature_periodic_advertiser} +- {id: brd4185a} +- instance: [vcom] + id: uartdrv_usart +- {id: bt_post_build} +- {id: sl_system} +- {id: bluetooth_feature_connection} +- {id: bluetooth_feature_aoa_receiver} +- {id: bluetooth_feature_dynamic_gattdb} +- {id: bluetooth_feature_system} +- {id: bluetooth_feature_scanner} +- {id: bootloader_interface} +- {id: EFR32BG22C224F512IM40} +other_file: +- {path: image/readme_img0.png} +- {path: image/readme_img1.png} +- {path: image/readme_img2.png} +configuration: +- {name: SL_STACK_SIZE, value: '2752'} +- {name: SL_HEAP_SIZE, value: '12000'} +- {name: SL_BT_CONFIG_USER_ADVERTISERS, value: '4'} +- {name: SL_BOARD_ENABLE_VCOM, value: '1'} +- {name: SL_UARTDRV_USART_VCOM_FLOW_CONTROL_TYPE, value: uartdrvFlowControlHw} +- {name: SL_BT_CONFIG_MAX_PERIODIC_ADVERTISING_SYNC, value: '8'} +- condition: [psa_crypto] + name: SL_PSA_KEY_USER_SLOT_COUNT + value: '0' +ui_hints: + highlight: + - {path: readme.md, focus: true} diff --git a/locator_ncp/locator_ncp.slps b/locator_ncp/locator_ncp.slps index d5ac1a3..05863dd 100644 --- a/locator_ncp/locator_ncp.slps +++ b/locator_ncp/locator_ncp.slps @@ -1,16 +1,16 @@ - - - - - - - - - - - - - - - - \ No newline at end of file + + + + + + + + + + + + + + + + diff --git a/locator_ncp/locator_ncp_cmake/CMakeLists.txt b/locator_ncp/locator_ncp_cmake/CMakeLists.txt index 996ff60..e64b524 100644 --- a/locator_ncp/locator_ncp_cmake/CMakeLists.txt +++ b/locator_ncp/locator_ncp_cmake/CMakeLists.txt @@ -1,47 +1,47 @@ -# Define minimal required version of CMake. -cmake_minimum_required(VERSION "3.25") - -# Project definition -project( - locator_ncp - VERSION 1.0 - LANGUAGES C CXX ASM -) - -# Include the definition of the slc_locator_ncp target, -# which contains the content of the SLC project -include(locator_ncp.cmake) - -add_executable(locator_ncp - # Add additional sources here -) - -target_include_directories(locator_ncp PUBLIC - # Add additional include paths here -) - -target_compile_definitions(locator_ncp PUBLIC - # Add additional macros here -) - -target_compile_options(locator_ncp PUBLIC - # Set additional compiler flags here -) - -target_link_options(locator_ncp PUBLIC - # Set additional linker flags here -) - -# Link with the content defined in the SLC project -target_link_libraries(locator_ncp PRIVATE - slc_locator_ncp -) - -# Create .bin, .hex and .s37 artifacts after building the project -add_custom_command(TARGET locator_ncp - POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -O srec "$" "$/$.s37" - COMMAND ${CMAKE_OBJCOPY} -O ihex "$" "$/$.hex" - COMMAND ${CMAKE_OBJCOPY} -O binary "$" "$/$.bin" - COMMAND ${CMAKE_SIZE_UTIL} "$" -A -) +# Define minimal required version of CMake. +cmake_minimum_required(VERSION "3.25") + +# Project definition +project( + locator_ncp + VERSION 1.0 + LANGUAGES C CXX ASM +) + +# Include the definition of the slc_locator_ncp target, +# which contains the content of the SLC project +include(locator_ncp.cmake) + +add_executable(locator_ncp + # Add additional sources here +) + +target_include_directories(locator_ncp PUBLIC + # Add additional include paths here +) + +target_compile_definitions(locator_ncp PUBLIC + # Add additional macros here +) + +target_compile_options(locator_ncp PUBLIC + # Set additional compiler flags here +) + +target_link_options(locator_ncp PUBLIC + # Set additional linker flags here +) + +# Link with the content defined in the SLC project +target_link_libraries(locator_ncp PRIVATE + slc_locator_ncp +) + +# Create .bin, .hex and .s37 artifacts after building the project +add_custom_command(TARGET locator_ncp + POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O srec "$" "$/$.s37" + COMMAND ${CMAKE_OBJCOPY} -O ihex "$" "$/$.hex" + COMMAND ${CMAKE_OBJCOPY} -O binary "$" "$/$.bin" + COMMAND ${CMAKE_SIZE_UTIL} "$" -A +) diff --git a/locator_ncp/locator_ncp_cmake/CMakePresets.json b/locator_ncp/locator_ncp_cmake/CMakePresets.json index 3cb1c24..eda053a 100644 --- a/locator_ncp/locator_ncp_cmake/CMakePresets.json +++ b/locator_ncp/locator_ncp_cmake/CMakePresets.json @@ -1,38 +1,38 @@ -{ - "version": 6, - "cmakeMinimumRequired": { - "major": 3, - "minor": 25, - "patch": 0 - }, - "configurePresets": [ - { - "name": "project", - "displayName": "Configure locator_ncp", - "generator": "Ninja Multi-Config", - "binaryDir": "${sourceDir}/build", - "toolchainFile": "${sourceDir}/toolchain.cmake", - "cacheVariables": { - "CMAKE_CONFIGURATION_TYPES": "default_config" - } - } - ], - "buildPresets": [ - { - "name": "default_config", - "displayName": "Build locator_ncp", - "configurePreset": "project", - "configuration": "default_config", - "targets": ["locator_ncp"] - } - ], - "workflowPresets": [ - { - "name": "project", - "steps": [ - {"type": "configure", "name": "project"}, - {"type": "build", "name": "default_config"} - ] - } - ] - } +{ + "version": 6, + "cmakeMinimumRequired": { + "major": 3, + "minor": 25, + "patch": 0 + }, + "configurePresets": [ + { + "name": "project", + "displayName": "Configure locator_ncp", + "generator": "Ninja Multi-Config", + "binaryDir": "${sourceDir}/build", + "toolchainFile": "${sourceDir}/toolchain.cmake", + "cacheVariables": { + "CMAKE_CONFIGURATION_TYPES": "default_config" + } + } + ], + "buildPresets": [ + { + "name": "default_config", + "displayName": "Build locator_ncp", + "configurePreset": "project", + "configuration": "default_config", + "targets": ["locator_ncp"] + } + ], + "workflowPresets": [ + { + "name": "project", + "steps": [ + {"type": "configure", "name": "project"}, + {"type": "build", "name": "default_config"} + ] + } + ] + } diff --git a/locator_ncp/locator_ncp_cmake/locator_ncp.cmake b/locator_ncp/locator_ncp_cmake/locator_ncp.cmake index 009eaad..0c25a1a 100644 --- a/locator_ncp/locator_ncp_cmake/locator_ncp.cmake +++ b/locator_ncp/locator_ncp_cmake/locator_ncp.cmake @@ -1,313 +1,313 @@ -set(SDK_PATH "C:/Users/tilaczko/SimplicityStudio/SDKs/gecko_sdk_2") -set(COPIED_SDK_PATH "gecko_sdk_4.4.1") - -add_library(slc_locator_ncp OBJECT - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp/sl_ncp.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_robust.c" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_usart.c" - "../${COPIED_SDK_PATH}/app/common/util/app_timer/app_timer.c" - "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_control_gpio.c" - "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_init.c" - "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/src/sl_cos.c" - "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c" - "../${COPIED_SDK_PATH}/platform/bootloader/api/btl_interface.c" - "../${COPIED_SDK_PATH}/platform/bootloader/api/btl_interface_storage.c" - "../${COPIED_SDK_PATH}/platform/bootloader/app_properties/app_properties.c" - "../${COPIED_SDK_PATH}/platform/common/src/sl_assert.c" - "../${COPIED_SDK_PATH}/platform/common/src/sl_slist.c" - "../${COPIED_SDK_PATH}/platform/common/src/sl_syscalls.c" - "../${COPIED_SDK_PATH}/platform/common/toolchain/src/sl_memory.c" - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c" - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c" - "../${COPIED_SDK_PATH}/platform/driver/debug/src/sl_debug_swo.c" - "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/src/dmadrv.c" - "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c" - "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_default_common_linker.c" - "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_hal_flash.c" - "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_lock.c" - "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/src/uartdrv.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_burtc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_cmu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_core.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_dbg.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_emu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_eusart.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpcrc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpio.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_i2c.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_iadc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_ldma.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_letimer.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_msc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_prs.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_rmu.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_rtcc.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_se.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_system.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_timer.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_usart.c" - "../${COPIED_SDK_PATH}/platform/emlib/src/em_wdog.c" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_util.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dcdc_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_emu_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_hfxo_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfrco.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfxo_s2.c" - "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_nvic.c" - "../${COPIED_SDK_PATH}/platform/service/mpu/src/sl_mpu.c" - "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager.c" - "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager_debug.c" - "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager_hal_s2.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c" - "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_init.c" - "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_process_action.c" - "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay.c" - "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_stack_init.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_accept_list_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_advertiser_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_connection_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_l2cap_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_periodic_adv_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c" - "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_sync_config.c" - "../${COPIED_SDK_PATH}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/cipher.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/cipher_wrap.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/constant_time.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/platform.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/platform_util.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_aead.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_cipher.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_client.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_ecp.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_ffdh.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_hash.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_mac.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_pake.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_rsa.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_se.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_slot_management.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_storage.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_util.c" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/threading.c" - "../app.c" - "../autogen/sl_bluetooth.c" - "../autogen/sl_board_default_init.c" - "../autogen/sl_device_init_clocks.c" - "../autogen/sl_event_handler.c" - "../autogen/sl_power_manager_handler.c" - "../autogen/sl_simple_com_isr.c" - "../autogen/sl_uartdrv_init.c" - "../main.c" -) - -target_include_directories(slc_locator_ncp PUBLIC - "../config" - "../autogen" - "../." - "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Include" - "../${COPIED_SDK_PATH}/app/common/util/app_assert" - "../${COPIED_SDK_PATH}/app/common/util/app_timer" - "../${COPIED_SDK_PATH}/platform/common/inc" - "../${COPIED_SDK_PATH}/protocol/bluetooth/bgcommon/inc" - "../${COPIED_SDK_PATH}/protocol/bluetooth/inc" - "../${COPIED_SDK_PATH}/protocol/bluetooth/bgstack/ll/inc" - "../${COPIED_SDK_PATH}/hardware/board/inc" - "../${COPIED_SDK_PATH}/platform/bootloader" - "../${COPIED_SDK_PATH}/platform/bootloader/api" - "../${COPIED_SDK_PATH}/platform/CMSIS/Core/Include" - "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/inc" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/include" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src" - "../${COPIED_SDK_PATH}/platform/driver/debug/inc" - "../${COPIED_SDK_PATH}/platform/service/device_init/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/common/inc" - "../${COPIED_SDK_PATH}/platform/emlib/inc" - "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/inc" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/config" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/config/preset" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/inc" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/include" - "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library" - "../${COPIED_SDK_PATH}/platform/service/mpu/inc" - "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp" - "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_evt_filter" - "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/inc" - "../${COPIED_SDK_PATH}/platform/service/power_manager/inc" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/inc" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/common" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/ble" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/ieee802154" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/wmbus" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/zwave" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/chip/efr32/efr32xg2x" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/sidewalk" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_aox" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22" - "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_power_manager_init" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/inc" - "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src" - "../${COPIED_SDK_PATH}/util/silicon_labs/silabs_core/memory_manager" - "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com" - "../${COPIED_SDK_PATH}/platform/common/toolchain/inc" - "../${COPIED_SDK_PATH}/platform/service/system/inc" - "../${COPIED_SDK_PATH}/platform/service/sleeptimer/inc" - "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src" - "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/inc" - "../${COPIED_SDK_PATH}/platform/service/udelay/inc" -) - -target_compile_definitions(slc_locator_ncp PUBLIC - "EFR32BG22C224F512IM40=1" - "SL_APP_PROPERTIES=1" - "HARDWARE_BOARD_DEFAULT_RF_BAND_2400=1" - "HARDWARE_BOARD_SUPPORTS_1_RF_BAND=1" - "HARDWARE_BOARD_SUPPORTS_RF_BAND_2400=1" - "HFXO_FREQ=38400000" - "SL_BOARD_NAME=\"BRD4185A\"" - "SL_BOARD_REV=\"A01\"" - "SL_COMPONENT_CATALOG_PRESENT=1" - "MBEDTLS_CONFIG_FILE=" - "SL_BT_API_FULL=1" - "MBEDTLS_PSA_CRYPTO_CONFIG_FILE=" - "SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT=0" - "SL_RAIL_UTIL_PA_CONFIG_HEADER=" - "SLI_RADIOAES_REQUIRES_MASKING=1" -) - -target_link_libraries(slc_locator_ncp PUBLIC - "-Wl,--start-group" - "gcc" - "c" - "m" - "nosys" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_gcc_release.a" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a" - "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a" - "-Wl,--end-group" -) -target_compile_options(slc_locator_ncp PUBLIC - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - $<$:-Wall> - $<$:-Wextra> - $<$:-Os> - $<$:-fdata-sections> - $<$:-ffunction-sections> - $<$:-fomit-frame-pointer> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - $<$:-mcmse> - $<$:--specs=nano.specs> - $<$:-g> - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - $<$:-fno-rtti> - $<$:-fno-exceptions> - $<$:-Wall> - $<$:-Wextra> - $<$:-Os> - $<$:-fdata-sections> - $<$:-ffunction-sections> - $<$:-fomit-frame-pointer> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - $<$:-mcmse> - $<$:--specs=nano.specs> - $<$:-g> - $<$:-mcpu=cortex-m33> - $<$:-mthumb> - $<$:-mfpu=fpv5-sp-d16> - $<$:-mfloat-abi=hard> - "$<$:SHELL:-imacros sl_gcc_preinclude.h>" - "$<$:SHELL:-x assembler-with-cpp>" -) - -set(post_build_command ) -set_property(TARGET slc_locator_ncp PROPERTY C_STANDARD 99) -set_property(TARGET slc_locator_ncp PROPERTY CXX_STANDARD 11) -set_property(TARGET slc_locator_ncp PROPERTY CXX_EXTENSIONS OFF) - -target_link_options(slc_locator_ncp INTERFACE - -mcpu=cortex-m33 - -mthumb - -mfpu=fpv5-sp-d16 - -mfloat-abi=hard - -T${CMAKE_CURRENT_LIST_DIR}/../autogen/linkerfile.ld - --specs=nano.specs - -Xlinker -Map=$/locator_ncp.map - -Wl,--gc-sections - -Wl,--no-warn-rwx-segments -) - -# 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ocWlgJ69x1Ced3577xI4vNu+Mlcr5ksgxy0BJcXZgq0rTX99Lr8STzXmZkTOJGnNF9sgNMYc1OVSvOVblVY8tjYzk+m83qANLZTNULtuTpUEamKZKI1fTZmVGziRaNKe2owEHrNMIXoIQOzC9RSxrxGA6cZLFarONpmWI/oKbvOD5roEDGgF7vK2zHfx1HJWtTzHRRizsieXpUmQZQjbnpuav48BVVhtjL7QcqOFdLm/U8p5pzcp8iYMj47Pn2YDDD41RJ3JdBpSAhC0hZYe8OytbciRha07R3IzJiIRtmVUtKRNxDGfKr47aRFbNaIJR2rXlbcs0Zqe9Q4lDKM8mBa+CgHVmkYlt9ALTkcWyxqyesca0aub6+xuW+Fkd+c7jztEvpKf4PC12BUVlZUzSacTynBicVMJcv7qtBtgx/ceejQYOqj8jU/RjQWOUe2bVItbHik+uWlmBSVSMUFpK1tGykqsGa+/isDMAG0uw4ZqjuMniVIm5WapkmsES5eJZLjsw4kde76YbjgpRkjdevSipZdWjBqKslpQ1jVYsyiaz4OlVELBSQiO0AVQcKoaeb0TROKHn44SiWln6VNX3DBVYWLppKDnp9Au+YX+cTSNNaVlQz0M70synibRlntNCqZ/tkY7otLDmADzEdB/hVLCpbmWbhIqVNokcp9vW7WEcZ0DBZNqpdMOIla6J6EsA3KVrIthUt1zpsq1TX+kijzBFb96v12z+hUY1lKhfNCHAzfGRH8LMdBJJ45WERCErDAXlyoZxqY7RGtLUQNqWFpSrnBjXawRHQSjPfZzxvMqMl+V/UWstfSp4hjPKZqkSXKKzF80dJ+JRmc1tDmNUhTNPo+zMKbElOvvQ8ARZivmyFEcBqbrj02Vq+wAvnuGPX1szrf141iibcit0VvPBrgqcpY2fconOXjRkTsCWKO2Ds00HjQ6XKu2Fw6MtJZb5cOuCYRXRCcbP20RnH5rnj3Kmu4SW6OxD8yfoJXy+XmKsDRJltpZNEFW4YPwxScA1Ion384wPl6ntA5ymIeFuRqYZmnCPTJ5Md/wRZ6p00Ted4ppCNk+NRplBUpvYklBBa+/842p5o9OlSnnmbaOzNZ/7bUBjARvQSKsWZcKC6k5QulVkinQs6+1LSxQE2B8/HXO1fYCnaJQgAZUa3BgHoO4/GOtml3IZbL2vpTbOQQ69ZmF0woLePsTkEpPREQt6udxE42dyc1StJrhx1x0rkF2rjk0+rbEZE508Pq2x0VrCXLT4tEany9TyAU7VJde087ngxsbMtHK54Mans5ojDjW44MZmS3RyueBGZ0PN0XYaXXBjw6VKeV1wo/Ph9l3UDS64sfESnRxoUzV9ZdU8vsKxCROdPL7C0QepfL0vc9uNzpYo5fAVjo0WcA1LgwkyNODL0OAlMM7jj0NztZx+1gkAE7V8gJPNOurq+RzDY3Nyd27TjO+5h/fMRzs2Xaq01zHcv8+GhW3t3mfjI8vWm/an8Z1ZqKQZlTZGgjHDFil7ejAh1d6zmZC95pxHaWfaQVMCHtjYZ6izO5p1evJilOFMB3szEI8po10N1EHfdRtpDXjMS3I6mLvuwuHbeZjGdu4Ptn6yq+Fx2xKHPDlBuqSWLIj6RZGDOx51fU0NY3xYaqvthtPy/IUpEyCnWDRQySfHk3OKAs6UYM9OmQgMYFFmkTf9zyf0yFv82bNTms4AFmUWedMDy8RPyH7gtD59fMoESBkWNSLgSyvo4nF/y4nP/lprSb76g88X7bnx4abUpgB64GHDOo8z86h2RkT/gmEvMvhFM1nj1QetZXBIrqAodMlsqD9jiAWM1cc2RgFH/U5fSG3V6ImI9PUxDmdUkj+xdFExZNHLCVwPPDu6WBwJzqDoxYTE+uZCXo0IUHpjjO041TaFWbYoYSyauDhu9qi8NEEDyWXMoN7CQ3fEgGQ1uW2w0NjoNbeQXYnoId2I/MdJRuFJUpbNzdpAbdEOKtQOVsyngnJ1cfWerlJUjG+D660ZWfLM0KAKF5cttUSYS/Fsg+POoXiSPEOrmuCEy93cDOq0hbdBLrRCpWinjbfY9LS3NQFz6JDrVAsOarHuukHGDHpvCcsHT4F4PM71Lyrjc688aeJxKlcPDhP7+pzTRE3ikuxzUOdPKsxWoiT13VH6Ra50UdbfHyJsat4agpzvkcpojlbakD+qDzM0mRvHuStp78mc/NlxM6ZKylWMAsvxbDwhbwODuuPlJzvCoeuG1+6WhS8MF7GTI5wdeUpxic2MSlOYPphr7i8D9EG1Wd+FKN10kJd1/BjqBDjsbz9ibYUXJsiVgvZFIw9XXhXfGT/bum3ganPK76g/MiBlSteRAr7AQXGrRsTwRKDNHlZ+JK4xNXL9ixYa7q6EvuW7pyiYjxE5jogVY5fINnyhjrxg7kzwCzhgHXvf7KJxRVtuLHC68I0G+CI5pdLGXz3IV8bTfEtZ0hBP/WxwlxT0xfChB/ZOoY7MRzK7sALWHN/OltLDuPUUSqORt5H0nnU80TMYtxtm1zxMbUIjCY8J5gv5bBn6BYWheZrajFYaHlNszUDe1BZUIXjAPfTkz6g6tONwGYN9yzVJHhIJk1vSzCJqxlzypROJx6jg5WZMbUWFgQcbGQb2SNWygnBq+maUHiOY2SEyHpT71NvY6wQKAlDkXRFJFhqmVOm6bd3UNBhAnYGrkNUq1VTwjSRyw5EJ079OIj8cmcqMVhrh4chUFlQhBgxHpjKhHUd2ODKZJc0sA4cjc7BGLm+KQ4GprKgwSA5HJusqGlF4jEiaNNJDTgZfRuAeQ02X5E0MHNi2PTFzCaAX+II8axrSVDNHmk7GmKnmg0yOq1snAhYqvfiqB7kOIjZpmbS6tW1taUBWftKsi7b1iFkD6AiBoLpQW+NB8UwFTxeWL71uc45TZ82u9QbnemoDbcpC37VtMtyYhaOdJcXCtjNXuxDpgMNrjXcKNJU1I/Rtdk+IjV7UngvvTJ+s8NV5wPescZWz9jJ2dcmAagalq1akusHEazLpGfqcOiTD7p/Zc+PZTdQtiprFT8X3rSJekW8+IR93riK65KGBF1ZQK6gY1a6/1J4F05a5/Uqqe3sl9nTSaqkOjd8FXEVQ4qws61LYKlYsTZvBqna+3FE8GOtibR6FSe3VM33rsbatq7ZRj05ZIh8xN6JLnteDp2pcC64KWU9Lw1UZRj5LxNjMRbMlaZFPWOQ2IvFdu0tVjFBmus1NylLCArbdwHnWtvGNYnpwjULTferdztFWRsoP2XqD6HjPFNe4q+HtEctcg/a0wLWa1fJjy96qIedJ24qt+hwYrxo05UBSB4RzYBbHOmpnMiq/h1eL9BIeMaN6q3u1yp6wGdr1w6NNp7f9+g3xlYwmWUemGLeQ7TFXWMPY3vaCjYvEjEXCuaiB9GzsC68+RqZ1U7ma3QtdgugBTg8uTclbZODEZYel5sCcgfSBB2h65gJD35kY27rcHHxTOS7t5S1B9ACfbroTqRzx99LmBH2oZGa/2+jsWu2b0vuL+5nrKH3wJEsi5fHk+8HLGHzQjmvOgDmh4EbWffQ0D+yURAidFK5HFFhKoysJ2lBC6jHGsLwrmew8+Ujlmav+cUgZow9a9QkdjnFT22GcrpGeTg8hTIvdRCNmwgya9XaiHlOw4WWP68ietPdvYuHCn765qXL0YVN/ofdC9NqTFpsqRw+27bihSh9UL28G0APqEAGByqsLeklzgn7UqbuaAkIfrBeoPwzaz1ui4EBmsW6nJs4gOIDpbF7pGi8XcU7BgRz6yJi0CS5B9M3NkUl0qYx+2T81zxH6YB9mMcSoYPRDT92sFRB6YZ98K5y09BYQOP1K8ygUTTB9obnJO2R0p1+x7WGlt7v04jeg9J3jDmzdxKfoMgf8RhgOAwzbmtjRV6bgQHYspXcpcQGnDBy45NXVehYzk2YabhMe8MvkRbxMwtE8Gv6LF7ppAZvY/16D4fI/TboElhEIuMom580wuAvIPEqGELKOyJh8HtwZikCFnLxoN8LwGxBvCmAljXa3+s2le9tDy5iJTZ18/GYGthsmESmd+bSgDVQCJhEC8uJcTMlp+E3ASuPUieBjrrh1hRfOZ/M6E/YUhR/+ioK5wKco/PAOmkvblJDwo3voYS71NUXhhyczy5mwJyQCTeVcUj3gSXPjiulRzqRPV31Cs38s2owjOMCb2KNTQREe4M0DP4cRMGDiXS4NKGLwM1ieaSeSHmjPxJwGKoi5wyyNK/OJjVLnYRBuDl3cM0qdB3uKIjhKnQd8isIPPwdHaQuOgBHT7o2ok4jNEuaBnpAIzhLmwZ6iCMwS0M10nck3wbUTiU14ZmIC176b8jxjHuSBYPGpesRmYkWdStxPNxNTchrpk512ZDbdWcl5mqqWVkhpYJTWxEkMyT6jjmvySri+NUm7UONNOPqBg9tqFsAJBxfwZNtXmqg7NrI0nouZA3dO0g/NThbMAjoj6YeOLJue/T+7swAv0fTCG+Q/tj2PdqTI0g9uzKKcJBj9uFdE/qctZ8FcYOEE91xbZWw2QfSUhgMejxEPUQAfd8ZGrBswmdO3ht7h8a1CTzTlrSG3TnjrJ7w8FN5p9yqvpObHLtFwwLNI3sj8IwpC3cYXZLyk219mYU0nnpx5Z5/Moyc6hcJlYBFQ0EQ6RWKvx6LmZ2IDoISJQUQ94TictZkNkIKmBsEk3qdu0xIoQVOet8vj/GxJqXiNmVerIdBEFCKnzIO/DNRvQujrpn+axziswNILzk4BzIE6A+FAnoUjy+R0ZJnXWczlEoxeXGxMs5ZZ5U05eIDn0eplIBzIf0y1+lSH/qN99al+Zn4eyC3L881n5WeBnKP0Y0915rgG3X7uuIJ8mYe76sLprro+mCqvveDmTTn6gclcfzbDixJML7rtzKKzTjB6cZPnZ+RVqxP1GzHJPtAaeMsW0Brsdh60Wz5c7Lj+i36Kzmfs68gmymeB34zVa86NTP8D13jA02xBqppRwenHpzcfPUwS86yGnqP0YrvWLGpogtGL6+FZdO8JRj/uJOE5arQtETpqsEaw0uYBnJJwQc+i1c5AuJD3c0He8yGnsW7nQF1g4QafjT+vBsRvAguCOycTUqB+E1z7ZbVezqOeFlj6wX3rEYWY3W4YzGJYUifqNyINoDwH/AJLL7hvkX7WXO1msZmjBNOPPg8/YOs24mqslCuaxYbBlIMHWNvuZoKckPBAr2eCvOYF3s5jRJiT9EPPYyWYd+2XRZFCxnUWo5MSDB86264URFY4j6WwJiY+Q1z3wZpPJmQ0XPChRR0Vc4HPaXrh80s/ZsBegulHt5y5cGckvdDq73rlpm6997UBey5bYrg3wdAHdcOfRU9UZOEFn0VbUmThBA9msVxZZGk4NsZ5rS6ZK/UfpZp+AyrBXIjsM03icsS7ylBED7nf0MnGk/qhcyPayAQNS/adPeAXotHyld8GLmFhK6KcqcHLzb29TLvG2mpkEe4bOWhEbRE9ZBSbTt8KrRsNWuK5wdQj80KeNIOJmuX5ZLwTWo+zM6sMJmoWrYek9afuvYlHaA2m1eF4zYtPWczEnByGH3/q3RclfP4DTaWAONMFVGqwosYkbMwtxM9hML/2rRtQ1sxZNgz9kLLmzq557wbkNZO86k+6JlCwKGPhhZ/+7FCBXuSMUBLUZgbL1wUDhFaws7AqSTmciQ0lHm4jrD9nU6szFm740I+MuQxkchhe/DlNQIVnmo/IjmZDn8Nw+3akb0KvOYWC2F7dJgZ3321OniTPsPCVffebJ1s243hHft815/QWkXhbp+IQu0VbFwVzFmXeRQmoJ0xT/qziwiQO31CgpMtN5Yvqx9I2YmTdAHMyFbdo0oU8yPDvibRWTXA5nEhr1ETXjBx875hg2goSGzUa5IEQ6ydbp98G9ycUgululM1FEcAld5NoLgbvRRkDFZ0xxBPxyGeTnRTmF3xGkU2zglR2bJe+ObnIN98w74N1IkDhC/Uz+uZmudTQ6+U9/f8/Ldff0a9Wh23yFXmR9kbV9xwjukdk+IjP/lq7P100Lf6T/mVo2ua8XWmWs6Gvh65rG1dSJasyyNT0Pm6V7oPgnj52b5mYic3eub/convDDF+vlvfr+9W9ttRWy4O2IXJJY9cl0Xy4D0JkkH/pwf7XrFm81/drbbnfbFbLQg/zg4kDw7c8mpB/+WFR/JQ2XaXEZt/+sPB89w9shOzTq+9ffX73/uNv7968+/Jv+ucvv//y7oP+/sMvv//29vOr16/+/e+0jjruIyb16fUZ2QH+Pvbxhtbt7TPr3klX+vrf/yP/+rMb+Ub8bXqgnbYBOgoC7IcFP8z3pZ8JFTE3tHDQ+MgpTO6YOyMD68a572c9INlZfsZ0kOk/NkrHjm2d4mjV8X1qTQ/dHp01+ZkVy8YHSoGv6z+T3upERj+kiIRXHZmP1Nognhx3P8vzwI3kKMni/mdJIluuaRnUrW+0Pk6rHJu1+67d+lComy+k/hJZFxSG5qnjwUxrv91xBgRPrYlIGiHLoJdcWwTAMFuNKD6HnYjnsev5mUutffYNzgfbBdaPhDX+nIhreyoeEbX9+qxt9bONgqseXKPQdJ9uehSglmpIXiCtd9dP+DGkTXrYnnue+0R+TAZobQ/5yLLjayOR+9z/kIc4ninpZWnf8k5AY9uyqPStT9gYe3SPeasBEUlC2pbEafnYJit9LP+NtpOOa0Y2mVe8/vrqh6Qtfv3+Pfvyu2fHvgWvk29//Pr166trGHqvF4unp6e0hyDaFkGw+Bg/dI/ZLOUr7SjjBpi9Rua48ZeWyT5Hxn2s9z7AYeTdR8abGKrQb99fDIO945lOSchfvpK+gnUobEpHt54EpHcN6ZWf7MH7/0b/XSTPZV1MatZfWKIkeMRwKvcf3w/tW+gq8wXfFp++vNVph+re8C0+cPZ9/qNt3R5Ir0CGIfe2WfqFZCPpd8j4hvWNbF5debfYbtLBcttP9bdY85l2FbQw1l83UmKdACDbvdTFFBsSg+TTQ1AXgx+piCu6mXZ8mVnXzzUN5VrTKqVQZayg4fe0nDdbmv9Ko7EYuJpFgW1V2kI9+an/wdBHt4AdqGh/hXbL+eppj3zWh9cemlG1/YId6gPF33LFjeee32czze9b5mUN39OpRMPXQSyl6k0g8hdZPV3Eq2YLOkOJ+7OEQvQtMV2FTrPejQoSdMsC5CqsMPKKzBuJcpMBIUP33VMUhCKp1ScKgop1/x1QyfvMp5VPgQp/dlC0vBv3WuKvs+FM/pcAdPVNUZ15knW9fyU95hPy8YL1ndR1XJuHSLzJOiSu1wK/rlC/eJbbklJdrxe6wdbX4gWg8vxcd+laKZn5pEYYbtBH3y0nwaJy+HgaJgwpTOtcouVHTvImjQm2sMZmG9Mlw8Wb95/ffV68oY7kd8nShOEEVrzXwLJby2a/ANL/Sr9b2Mst+j67XctZryXedbxIR77zeJB4N/wzXdDve/kXNoItuRHf/vpprf38V03LxGX+Nx3htvIuK/FEqkRbDzRAZtib3YIyDSeClsgcUai/YArKpR4XaJHk8WSbJqRUB+mpS9Ttrdqiwj27rT+SFYnBiwCOxyewQs+kcYbOqotn+NCFivXd8CLJlBk8Sa9n+CSlnkxgkZYGnUcWAm9LrOwIJqBQm7QlCkQ+nxB0u5SKpc4n6wbendq4awwvLVVB+bfhy78TQBdWz4Qem3g+dJYTiWT+drkhG1oyGUVBJ2gA3ocGL0G+2AglVEUlilTUIhUDiCfTBU7P4ro9jGQn8b2DSCNFKCQSM9xBQmNH6iIIScZEXkFoz9yXS2gVtEfmyXVD20Umcw9Zi+JqSr6a32dtRQhdyGcRaw3X7E3+hnezTQCC8OV3B+ileyCD/trdKSK9dnCACcWrCwVl+JjeJsEzIyu9XNzCUfnYZ0jiOEwcTZ2+zbZ3QtexenuT8judLu6Wd3By4Rr/G4FttXqb214JURj1VpzUOe0XE40voZN3YjSxV0h3iGybN0ez7VCpaRfDIOUCJzuDOU2sSYk3PQx7mxTzC4fbrSYk9U3GCD3JkPg42ZaWVH22v6VPdenlRG3+co9m7Jj+Y7FcYZ4GNX4r3ijF3or/FHqNkiavcTHSWTVrtvzIC5nS0jd8ustCKEJZCBcJ3eDFAOgffHpLr6Qr/jKvXvAN+/0tWNOrV9Trimp5Lfafy7xMdyMIvGdbJ/p/7NU379dr5jBH3K/T/KzsvqPlWo83dwhkbiYoN17iZWY813vJ1geWbsnffKmWvkh1pi/2aqSpzKq6w9mHll7hcmtX3ujtpErPG1erbfG85YX+6Vz1+cIxZf7XuAYClVd8jsa08gJ/JS+8aJ56Z0ul5zncyOXnueZ4Da/IpDSXo7fyRr8bt/QCh5ey/DyHD7L0Ao8zsPwCn9Os9A6Hr6n6vEx+cLiLSs/7yDlHNzE0X7BA8riFSi8EYjWRw0dUfp7LA1R9JcS984SGV6RaCPHSJV7lORepS+/wOHryF+jmO5Emn/aMWa/F1TUmb1ANQs/Tpl7kBdpiizyPBYFw17aj5lfidlfsjdatL80v0HZX6Hna7oq8wNpdoRdw11an5ndouyvyPG1ARZ73BfOaNYYiLwRiZTVpqUReEU9U8fLKmo6eF3xkWu6CnQCgb+Ybvk/sOx/bGAU4+8y8ms9sGdcw0l/75iAVHXQAG7udF6m45/hX+oseeNiwzv2td1VqPEmnn+XfTI9XMd+pTuf6vT17h7AzRmHkDxLhnHs7wI63s1PuAu97dnSxbgsP3RnuLemwgiyjtPqZksh/BFISn1BJP8ZlTbD8CgiGIqb2xymtQDB0KhRlSnGWDh3VTiHJcfbIHMhZP9PUd+ZpqBUSGgVt9N3QNVx7cbJx/C35Q1aGhTE+LLXVdhP/mH+WlRhYJn5C9kP8U/pJVtqTc4qC+Hv2p6ycP5/QY5Ja7M8+OQEmtcUKX0rHjMi3WdyEdJ0h+wZeok4PmdCFDI5Zg4R040qElc/cgYpnUdBVCFZFzLnfR0Jy4dJTYMlXDuezhFjm9b8hm8ZVU5Eg9XBtChSws3hJZHJg8Ww3Dx3eKZDNNW6TkJveewMg1irK5R3oyshOy+Fg2enaa95c93Tz4hJLzTW89KQ9hRecNk7wkq8ci0MSYiuNhxoFWeMBLz5vPOBls0oOI7ZUEd0ArBLW5Oon5GMHh9Ia7Pykhs58Ff5LFjgtPZdEg06Sh+lcSIUW9gsNgEIGEUrlD+kdujQEzzxHh+QEn+yHpPniXCeUU2NedWTL9vZ9svsXrOQEY/I1nxdFXj5pzy74pi5xsGEGSKF46o9TlDwDxs99kp90jjUvOdkOChVRO9gxnN4dBvKypSdBPbLLQZHh5fvS04gewSGsZNrFntBmtapEO4KUvVYneoOz2ElygxhO4eDk65Uy7lw0LHX8LT3imc2yYNkbFKiwIB8VweJ7yDTlvQdtUpNxFixqaYylVDZ4YiSDNnDmwrhKiezCmEqB/HQ8BS56wJS8Qyobj8BLjcciSuRK+zs65BbGIOCyfWlPRIfQUIVUH1/kx2BpaLIg8ugh8UUWLjCPWkZvHifz+SGOYy49rnOzPHqO59a7QCejhgZJU2IK9aKSHoY0H3DcVKZhOPAyHWSAC70oAKUXg6sQqm13KsRuVxq82OxraLF5zF8VkvPrEgAlWyqg8yEtbVWHjBK7JZMKAio5iyepSi5pJZQIjsdZ5F/5wUuT+EJNARZbKHSwki0I0elmi0ROLrr8vXR94ZSvsz0gQ6pPm6JUcLJ64dChwRg6pBOM5GlyApL1tlkLAC+b3k/D/LSQArNdCKEfBSE2eQ9ki+igaa5aD9WRJ35yn9sgx1+nAhbQ10M+DVtMj5oMW/TiVjVsZapBTf7V0GWjbuEDNzA0ig9wet5DN7GHbya+GRyRHHhUlDtziKaoLDv5xgoDnR3iBRPbVgmUKCiWzEQZwsgcTdlAX5youkF+HVFlIBsw5NSqKO49aoeMPkV1Dd0a0qix3o6qEc6ze1pUNHQD0dYu96rwWeyfwnUCeSyK2g0DvY08lzCeKKGcojgONHNK4omJyCmKK9gWtywwrNtj/+mjJlFZdJHKzTpB7/kNTmn0/h0wYeyWHjBpcVZCyYIkY7nJKcrxoszT5XFXGPpWOuv3ek8mpm+VToFk7qril7z6+yXFEW+GyLMg0NKxZUmSVHI1SUqMhJNHw5vwF8MmgZVUo+tDj/TWEc7Uy69QyuNgpd9Iy7CGCcmiXmUyONOnSwZLaq5D6NzSPN+FFMdzhJhb2LB0syriuDORnVLOSlIcKoHn9FmnAJLOBg7oohzfGlZJVB4PLWPhTZUmARUWTlGRiW30kpoVf+K1I3k3wUjeFdNbepfdJrBzWGSnz81i8rN/6QUrNORgQC8IvH8mf/K+dbokR4XtOKxU+lnsjHeTXHbx5sK20yQ9hUbo2yzOFDGxvdXplJVSFq9rpNeLsI3dw4hTzAtJPX62zDhd/jU2WcmuMJURYts9W8O6XmaJO/j9riak6+1Ob2HXiz1hVNpetViiGwZpOnUas1HS8FhMywWcYlKSK9JMfBZOh/T9xhtLxaR0XT8qJimR0HEAovN1WzNQ3/7MTgEeevKBsqZ41SqUHACs+nWzHO/Xms6rS0r/wEYzvaup1Aq09Hxtb7fVSCkxtfSVkVKvUTJSmmuUjKRSlZAR0FIlpEQ1VImhcgCwilWi+X12lVoQx+zW6S2Si/gySZ0GpVokgWyziRuZxCPbdttG+5LCmisrExZeLd+kAa/Dl3RfQnY8IP3cfjCLX4RvtR1g4pcR3FYQMp58q3UWzC3oRNqrXVuQCn4p1qU9GjW/lMiyza5o39ySDORg2x6eVXQrzlARV0T+p7XdBiAox3PtthGugCTcN2Dll9W1nZ1fCl0bGiqDTQLutPu2WDcCkuI7d80/ItKb2viCjJfuPTfDRJ9916FrLLDC6aINkxxrgRceRKQPouH5VSgIgjaPjKTA5+3yCCQRJqvoBdQhc2INFhb6uum3xublltPl3hYQMriPNa+DG122F3G4jOEZjY0/PPQwOItx61XP/CI6Y+fwi+nYnMYt5DK8W70+mG3zY34ZdNs8RM2xncGFvnyZ/GBp5nAJ28Ei4mH8KTqf6a4hiBH8jXQ3gWs84HBwgt/oVPnhaagY1xqc1F5rfGZ+EW2B4QQkGMGqLZyhkJTB5YYK2Q8WkiwUQMkB6akzYR0xpPiFkanAar0cntzxcipzIQWDqxUdGUJY51ukWpir3eB5kz+8E6enlgBkaNsdgJS222BEZGyH13SAAXpA95l1XJEqJohNRIPICocPQJk8132wQMhCi/ZXQyWFVx+jjnP0/IIsB0BK9+oRtxiIWRmVQabng4tjImdwTsVyAulBMj1NMdwTRqUM81nkEtI5NI1rruMbOtlYetBTl5rMqumuZA9Z3XEb5cUHLzf39iI/Ti8IppkTWrd4j2wwpMFpEMoV0VNGcG9kHxGhRtf9LmKChkx3CoJ4DrhIybuF+DkMYDO7Khw806sKQDOfSPSlx1QFOcP8hgVBQ8f6BVEBTtIOQpb1J0h6B6EfGRCVDapl7TwK3iooDW+BbOty6zgz2SsgXrLqC4bUL4atWekd16fxinBc4e6wLkH3kbAzolkKSZlHFFitwdn7xd10J5JO12R5aUj7nonqOvzF+bb+5KO24DdCImRtkOqR8reLCwWyVhSF6JbjyedtWdLAGogNLz8z3B5ng1POsDKfuMd1z7Wl7bEdV9wvmb7smDILS4W3hxRSxwskh05FCVJrA0UBdIor3vUWJZCRSeud6b0CPGR2XCbb//rD4BpBRAzJRu9Bak9I9no6jpJsZ8ruTVkhfQE0BCR0HVUWFiObqLmYYd1ZXRAAkW21HwEWEjRgFFURM7AhKkhLZkG0RtGtCvAS9RsdnZNJW+c+t8Gyh3PT9ePhhBKr0A1SzufWOEHCYobTdBz4FxYznGboKKYoSn4oUpDSfmhfVMpwFraRYjiMzH6MBjE+upmuM2g0XZQWtF0oKiplOEvrvZ2CQgBIbDfsD1UxRCIAYxLjCICtM1oSl6ShAy/60OBBrM+C7ob6FdtDul22ChePTwZIYJvaIFAcq/UedK73yefVenADn0vquFGsV0q+mBiXFcsh5W5Bv2P+gcvy3rtdGn9Ztf6iZb84yEqPjcY/3zvm11f/QX9xzcjGX1+9/vrqB893/8BG+Pr9e/bld8+OfQteJ9/++PXr11fXMPReLxZPT0/38emAezIyJCmw+Bg/dI/pcJE++V2yyMFeC/0o/tIy2efIuI/13gc4jLz7LLTJZ/aRzPgQqXj6jQxuLobB3vRMpyTqL1+/+l+/3r777gfmDWU3gX7n0Xuq/Fjn/X+j/y6S535YVIz7C0uMBJKYT+X+4/u/0/Rx3EdMUuf1GdkBzh96+8y8rgH55d//I//6sxv5Rv7tLNLzDRuuJzI+ukH4M128/M90HZquJj6jyKallLxxCf4zQYcm6P9viujXV+kN4/eGnx/b8o0ZtbKRkb4/WSr/x6vvX31+9/7jb+/evPvyb/rnL7//8u6D/vGX959fvX71wz+TpPj69btkI8uPX1+t7pdfX5Fv8M1wad9Ivvr9y693h6+v/pmopXqJ4kQveeyGHPxjk91v4uyomk1Fk7fJMCR8+WyQ/5KXU2mvMgXkIfK/H86ubWI/1xJnce259GmLZHf2LB2rxDtv88UX8ispLjREOibZFSc7/ZJGE2DfsDIYJzCPgtLd0gr1OM/aVj/bZHKtB9coNN2nmx4FZEyjSieN1KgnLa8qHSV/l6qUq4WVGkkXi9WlThWpTTp+DHXyQ1g6BA6tqBQiQ4WOiJRi039UaYKLyAwgifChUE9qSVwxH0n3MVa+1OM2wBdtOn0MnlRWn67oEaC6kOfpKAiwuuazHKVJnZJyQLAxSlt23r4SPEJtu/2sstzRtlSRdNNBitu2vqAg4BUnGbtZOBilvKk3qiEs5hgDxnLVjcO9qmuMqHuerSiOlIpXtVW2kIxIlZpTmLiAz4hYldy9qlaDHmiGBq4GO/RKQ7akHHfjCucpsYN1BA1JYRuu6IdFPMmsfp3s9/yIwiv5GPkW1R9GpuW+Tmfdi3Q6msvMZuTZN9+pm2F/wQ7daoJh59iJT4V7kp211fex4sw7kudBPWOEO4Iki2GFs4lBOstNY05BayGdpm0ZbEc723kMbsmnL2/1N6kzP1CRUNlSgU7sQLZ7UaGkIfC5gtzAj9SMK7qZdrxzSK0CeAusSiOrJ/VVgS01VeyGAbazTZ3SWthkdQnJHFDqE5Gqyc9KKVZXHOpZAXy6se7Up9/d2yY8fepDUdUY5/Lp/m0DD2ouhwwdsl52krFDz9rvoPEDWxDnGz3UVtq/1sdrWQrSV18v3rxefI7j5f1Gw+VdrJCG7A/0P/HJRzpykZ4a47nGomDYomVxn6vk1Bb+xwRdSYFq44NqzaBt1aRacCrbN1qLUOW1dLd1y/Mtb/3CRhud77S8WUgsjtdbhLz99dNa+/mvmsYtoo2GLYcKSmluHeOw5yyS6+miaUnz21p60haNZFgejjxO1lKBykxdxKyLJkXNhVuMPyRte+SNYUCTJjELWuqEYOa/izsaiNzPbDE0bXPerjTL2SyTzhEwBRPiRas6gIKQydZR1r+rNCFVA4p+inzkjAGfKYLGD42R8GNFoPhGfMGVavhEDSx6eh/cKAYUlYGakd5WptqCVA8sPGFIYpYo589VwZrgICI7MHyLZLA/iiU1jbAGefGBVuVmJHpA4fE47RFW0B5hth1iFPpME6gB5yC5V1A1f6YIFP/iGf4oLWmmCBjfGiXxUz3g8GTWPE7xLykDNeN6HqkGZIqA8Z9Hon+Gh7e0USpvogYWHY0zhEv1wMJnERmV42eaQA2wyXhqDPxUDzj88wmNMu4s6lJiBF1htm7juCKadMIahbO7PpXbkquCNWGs7sxW0p3ZI3VntoruzAlG6RISNaDonjmKPy5RA4vuj9L4JGqg0fXAutwI7kgmFNWBmsJu/R3BhlQPKHwwjgciUOCBCF6CfPemWvpME6gBo/W4avrbaLQON1LT447mwVLjwHoy3VFKf6oHAt5JtgMq5C6qgFh+rq5qKyNv0qR09Zn7cY4HeR6pn/qlkRVk9mpYN0Ngj0Zt527oOpZcl53chm7F10zngnjzqWFfaXKx5ECUVIw8SHxyDiJVMkHyMHmMvIEwuSB5mIBeOwzAkskZgBKiMJIbMVdYMkH9MPztRLWeBv6gehoXJJntPomxyf3TuaABKU/GgMi2AwCcoqihpRKAJpWjsiCErmsbV2TxtPYAZaktzeLAEUMSLTMkTb5cJHdWCvbSQzq/7oTQfXyxhjWzeXokDUtNsuAQpi3P4Bkh4C6GoXs+TnaGg0LWRYMXMEXjupPrhrZLQ13LjO3Kh5Flu4+yFKkan5uxKEtb1IWrbDuRZ8mmQukk6vBEsBY1gZL9V/mIbCHGJChgUbAkaPGUXyHLZSp6hbRd8oA0ZSHqDVeyKWpIy5JAiMyGAisJBCmFHvIDSX9cZyHM5YJWFnDOguABoD6md6ZLb5NsICxLBGlpZXq1N+8/v/ss06G9ofHlpIe9cmcBKhljOIEV3/Fl2ZJFnJm/oLZkDqu61EHDqVhc4eZFOMaC0EGI4Z/pnWNQfGWJAOl3kVyMak27i8yqUxWN3XvgrNdgaEWBg9AcL9KR7zweoNBKAr+VIXuADWJl+CLTvhUDCQyY3tv5qQM9CeQ89BCduMugsYic0Ga1wVkwKZlRapq+i2JiLZpsZn6FukaAlQwidL0a14iSPgATYkX0REEWxH0EQ5q1gplDo/jEVxeOZktJJcQi2TM7LDcCf64JBvtkPxTuLRqBvqwQxgjzqiN7lDpdUgYDj4kKwvA4WvkpK4Qz4gG/XPBtxJyoK4UyxmRXXIxnR0EfjAnptUcj0KeqYMAdFI4FnqoCAseO4XhjoWfK4OA9uXUhOXhPaMWoG75w+fU4BpQVwhjh38ZqbRJNMNjheNwhHDidXqwqQRaVz2dKCoGMWI9swxrehMI0byQjyhqhJ5bjGFHSp2ZiOYIhzVoBzPGQya6/GsGGgirwGdkI+DWFIEb4+CK3RihMn2qaIkyRBRemKF1E0PFzSCym9+OoTj8rcyU3qgZ175j4PJo5VaUK/FSjm5KphfNVjWRDrg26dRyyR1bOkEbdoB6s8WzJFQIZIHkqW5Ie7Gx22R82ngVlpUqccOMaU1YM7Ygb05aCTiAz6B6iUQtXphDQmzgefqoOCP5Jlz0mKYmfKQR0iY6Hn6oDdYuOiJ8pBHWNjmuAJ7E5u82AgrdyPCPKSuFcpONZ4EPO6cNx2UMpeFWnJ9NEqW94Sa9hCCKPBvgaut2l8xZVsSwr3BFB0hjbNGK+7K681jysmJ9cu7PoUg5RHAviXedmeXR/6U1uQ98Q0yq6gSyjl1JMkmNNiqdwSgHt+cqNhV3eqaZgeoos1wXmr6GNI/iunCb+mjoAE7IbagxHvQEVZZD4DjJG5E+0ARoQTwfJv8C7ErrMKOsErQ+XMYpTTR1I267n92qP0iSV1QF2T+PZUNU30SIJcH+ktEdPT8jmugBynnQLOrIVD7EoeUERRLNhOONgFxRBYJNeYCTugiaIBuKKVuOAFzXBgGvb3WjoBV0w8NuVNhp8QRcA/GWsKnoBraLl7nWMBr2sDr43H8GGqj64fHhEdgTtHuzIh1zd3B1UlNb0rUeuSA7dwqCm5XEpgN93mZtaGjwC7rpMRcZaildhqjWhog/ekmQzwIi25BqBrAlwekZYN7GHbya+GbJxQ0Rs6tALOu+Nr911qK9RpUltCoFyKReflINRmoFWreBWsXuYPeTTm6YTXfAHWTot7CAYw1oVJ/FE7YU9nNenDWFkTmtvSjCGteDeUFFj4Rykvaoe8Atp08nf8XLIpGbXWcZKgZE6HgmWMVKAhZwPI18utBWY8SUMuGmTFQb67dFZKzaupuvbcuNWr7UOkJSgxoxIj42QTI+CEJuDgkPx5AidxZKPiy7FMgWstXpNZmGfcjAr2WZF5eZkWqSqv0wVas3S+jxOpfGtGuHnwWfMGllgR1K3PUWdiufCqq3q0KtqLqzSpDaFSufCqvOoVavS0dQ5uhkKzoR12teqX6mlCs5XcVspechqbK80TurTfFzSes4EORTOhGaR2ktqYMbxuUw9Ci3QcFod/JkucCPgPUhdZgD7ioqiiW7fhY1J0mVJQR24KdA+zC47QL2VRcHq3Dld5ihy3FRVXNHNtC1YX3qfWUWd4EYpcbx0WaTAxVKQjsIQ0xtbRix5FZVwc4tUgRvABtmoGtOoTI0Z+omMoBwcjmxQWe235RXrGEIpScL02qOSGvB6OuRGaHETgC+DLssGn4l0GQIa36E+0BzJilQXfCOjwrNUtaRVIXieZG5VMgwYrYjVlMLnkorQUZ25BBw1qjK3uWLjQUFUr65MquqEN2pccxQaAh4hq9MQ0PBYjRPPkSwpqFMzzx3JDsgYEV0zzpHMqWtVO88d0ayiToXz3JEsKilUOs8dyaCKynn7vm16U1joGm4aAGE2PnCrSqb7iOQP+PnjipZ8c3CHdqCRXipS3Z6mFttaFEMtYJe1Ai8+8WUX4Hi8KbFGMalF8TwaFEXXBnGfDam/iU8Rf6gSJZcBMwQ9eJI7ipwsqTIhqfu0JBH86qeWpIC4DjgHl6kqpaRIetiSxG/nFiz/0TJ4Ato2lGf6JjtkI1+qYbIyA9EN2zUeZD0sLCkWBXF51jZpGHQJW0WqaZhyl9hxUqfyIZmxE6lETsRDEl/Pz7K9PRdyKh+S2T77hlLoTAEstdqUthWk9I38qZI5lT9WNwkzYii3IXqgSc4A6kmUDSEaVQC3VIrBcw3Q7ZVi8IIK+FZLIXemALrVUpzetpr0Zm2LQuxU/hTj2pbmzfGiaWdTBGBQkpP3s2B4sahvaQJFkYd0ltT6NPSSJzTSG6Fsee4TOzoptutWSSkroQwqbyVJ2UmzqvihrVJJYDwpVkydK4FlvyJ7aGfAAZ9rGUhvVQR7bG1Jdpmknb9Dz7fUfpULPlwipVFvquJV1Cu11LkS2JIJjt0gf0Z9SfAShNiZthOJGYYE4IlTP5aT7Z0tSx1awhNxnu8aOKCBsAds/u3Arcv/lpqtYpoPqUdJ0qSrw2WpanISHLcuf07V3sbYCy1n6vFjzjGsKmVisupUEjy4yGTS2IjID41h89ku3pIGYHBSJolktei5DmD4U6ScPVMBjK62hJdVDB4OlQUPaxir1E3Sv6kOLm9WgNIl7TRKggHzEJazKnlGXVpkYhu9TNudxQyDKnosIq3kucChLVIsSUe+87hz9AvpXj4DU1Zkf0vVOknmIVUlSZGkOucCv5W9Ftgx/UepnRYO4ntTVb2LAaQqHTN6EQtghTmX9c0U3wRZpuyWzKclN5c1o4Y9DhE04S4ebLimnKcyTuDYAJbAmagZpe/Fs1x2csmPvAGbpQbX4xLHgOpcksNqdU3yN1O5y+TyRbCcJiyAflXyjEokDSw4YX2n6ulZXhRJ3mQQpzkVw5K6Km/QUI4FXQSCAoHRL/iGfcnNSU0pVZA3HE52BtsEJjhf7YTSz7bs6bQWtFzicEC6ixSMLRX2zewsK9bXJEChzpJBzoVTSBPaGXVLhyxcULAliUCFC4otFTZW4bKt07DCRQQw8Dfv12s2VUbDUoLIWzTJnFF3HiE/nHaKmBAMKHWJBFbwCtK+mYFkyizfqKcpQNv1grRvx7/BV3UHFb7qxNEZsGjBgFl5K4rhTu4aieHIbQgscSRCBlC4kjHAyhiuWGCvOod5ktv4VcJIhMhTYIg8wUPzBEcBqc8AIJkceZaLZ/gA9SUTM4TEktsjXgGxxE4f1jgsDSA9EiEDKJAJgZFIkeewTQcN50ilDODA8mu6ZRQsvHJbp3ECgMxJhMhTeL5ccIESRSJEnsKHaFP9oW2q9BaRMobgNpA6RwDQ2wYD+9p4QxQARyZHngWo1gLUWaBOF6DPfTJdgMFQKqWfQ34mKTINahuLy82AqKFsAacgZsAo+Gp5w0FSKcPmBMMxxI5CN1KwkB5I1ttehinIkmSi+1xAUqcsSD6FUBBgHyB1cjnyLKdILoJBpQ4JBSlomkdK31RTLi/C98809PXIoTdSDIcpCJKnSe5sGU5TEDRwvg+QS2IBzpo5Bq5UVXhk1qma/RCDcRIhw/wQgykEQ2K0+iGGg2RyhrKAdUs1cUM9JIOJMjEDPSQAIJZYUKJGD8lgjETIQA/JcAwkFgqnxUMymCOVMtxDMhwFi283bvSQDCZJhAyiAGtSyrKGeW0GwyRChnltho+fhvZAzN8yHCORMshrM5giGDhiCiByJBiaI8FLYJwBhki5nMF+LAiWRM5QFrgRbV3eUB/bYCSAVh9oQAkwnmTescEgqRQQH5vMKjoLqiqziu4jy9ZFNs8M3QbemBGUQioXmN2L1Ih0R3cqbtCeKCbUOcu1K+1cqcjhbLHTSGc3Fut0/7rceKEDtVnDcHL5O3M6YGWv5WzgG3SNTAeizG0xQ3copWGYh0ZAP9k88V750pfIgkja1LQFkbcoClYaS7olfSyM8WGprbYbsGTKRYKmVi520aBmirR7ck5RAJZsTBpoijGJi7LwKdLpzyf0CFcLmTTQdGISF2XhU6RTYJn4CdkPYEmVCgRNrVTooqZiHrHwWxKXrm4O7Uzw2V9rkrnTJOr5oj1LiWvPcmqmHnjYsM6S87jqQIAIXDDaRca8aFYldcWDVM0Zt+igKHTJTHZo6SGpydLNxzZGAUiDmIpMc0aj2/VTBVJHASq5n5i+qLAvehXPui3w7OhiDc5PlgD0UkgduXLVuB45oCRTahNNtdlmpi5KchdNikDuZ6mIheh2uPgn6rA9dGe4t2RhW3Yk2NIxyPUz/fniId2I/EeYWWKSO+V0yPoJbdGuebS+ojFFKEoOHLdigLWtkh5t2gCqXJamY9hQUQSEX0sZZeWyTRtgPsTunDEMadKmoEApt0EaH6YJLzRPpXCwQjf9dKRnuQWsqVDSxdfVLDgwoAcADVpUjAckjJ3NVHXoqkr3j7VpjNc9AZZfIqkf0SUpL780Q0ATH/6w5ZlcjkjJI2+l3m9qxiKXsigLHBpCDRyvJnMsZz3VKhb9tTW/hA9UNKVHHGKwJG5QZuWSBmZUFQygFAWW49kYEq9B6LdyKvtkRzh03fAq02gNDQx2M8QdjNXcJDJEC39mc5qdRMYiFzW0fFExgsWqi2jEVomo0/FjqBOTwqFNU0xfEAeRSwVxi0YFAHlXlAiQjd3IAM1ZWaLEuQwpcplzG0PDCsVNLFE8PIpwJkr8FGBjcuUCFy3igXotKtN3T1GgkDmXDwc9uEC20QKOCAq2q6ItyJ/dCEFsbsS13QR2uHG6DB1wQASPSikAlpDybS1p8UmFp1Gl+pXNKMzUgEA99JzmKdSR+UgmYlbA+pfb2RI7FV1PzjTmfZvoAcdTT/Qw0e2G2eUi4LSNoofRmi/ks2XoFxSG5gmcuFX8MGpbM5AHDluVOozRQ0++yqLbLn8gN/Yt1yR5RmTDQzcLhyNWltqdOobxBy83Axy4InQYITIM7JEKYgUhfBPcKFual9keIuNBfF2gDbMucqbBNPJugqQiDWYqtjhdtz8NllAXOrA81SoRGGejaOgeHTJV66JV9OhgxK3iAXt0MNiqVCU9Ohhtu3z4Hh0Oulm4sh5dCTh0ihc7XzDgilDwHh2uCW6UPYw3aW5I9wPHWZYJMOIATMgmoYMIbRsaryRxANsFeRYQVCpqUErB4WSyhvIkEQWsk2VbodiFWD10dclQI2/YWiC64aSRTvzgYReY8InDRiaZuFBdVELhoeRnKacLy5cBTtfBRxLF3baN2UD9qWk60gYt9F3bJmMBNY5clmoL285cuUKqJznZKBzjvr20G6Fvs1s1bPQiGIugMzGz4l9X8M3sUAMo5V0l++qS0ZiKMl0ryN2aVDZKpD+Td52Q0nP/zCQMSAzy/qIoSn1ECLH1uSvyzSfkdx+aqjf2Lnlt5EsaaCpStcJuvNTEBXs9c+GVZA3osZmcpK0WDkbfxVaVOVsfY5lXpBGvmJ+22lVxQ3NHdPjZhcU/7lS0Fc/0rUeuXVcN+/Do5CzyEXMvukSKHjzxRIkBqMxtGWS4QrHos5yJU2HRbFJajxLhY+08grjhmCLLlNTu9EhKcCJ8RnsBnGdtG99ZpgfXKDTdpwHbNmTKY1WErTcgxduzgAa9DfKH1IAGcWnxb7Wk5UeJrVzjHi+WqWDzyOABVbopg5P6LJzB39L0B3CQ23tqpvZGeLVIX++RpHyR6WmdEzZDm//gcnNIA59Hd0dZJJ0BmRDfQnbcQKSNYecWCkmwSOxZJFiLmuRBWyvDq4+Rad2E9hD0MpakDuJLj8yB4hWFgtCxU3lKEDPJwzgDpACxIHTYSSTbutwcfBOaJ/TilaQO4jvddCcSmlv1wuUih5GhAO82Oruj/CZ2i3M/Yl32MFaSHZH4ZQf9nGW5EIyOa6pATMQCEeo+elJEmYoGJCXl6BEFlliQM0Hkko5B7IblXcn07clHQufE+vvustxhjMKniDiGFqIHhlrICiMUnR6sAKZsEg9JrKI5bVcxiBwbXiZMRzZsF9okHIBWQUNQFTyMkjo/vRfdc23YMlAVPIjSdtxQyF/Vi5dJHMTlEPGB0O0avWC5yKFk4C16QeYwNi+QOBfaj1cSO5iQRZ8GB8ykDuajs06xpWwuwFzsYMLQRwZs01eSOmyWiEzbNYQCq/ZPEnOZw9ge1HTLFblDGcHbl4LMgWxPvhXClryCTBDvhKIcbpI+LC49kUhGQ/oV2x4Wuxmol7ZB9rCj04Gtm/gUXZTQNkofzGvYFrQzqCx2MKFjiV2VxcWXCh1MRwSv1mrG2c3igYgf8At88SyLHtxOGf6LF7ppWYJ2p9akA3gxYBcfMpFg/hV4vEwuUG4rymZAQh2REaqq0pjKBqs78MWyUToUb7wWzAoV7eL0m0u3wYeWocqEToVQVgW2GyYRJB2FTVmDGjALQtcnYpWR5+KhiLFYIDQRWgwQGK0g7nw2r6pQU9lQrFcUKGNNZUOxOkhZq5GIhiL10IOyqpXKhmIlkyZVqIlosDZLXXM1PEWNK6ZHHJN+VPh8Yv/orFk+6BgI2nNQkQ08BlJEm0sH44VetW+QDcmqwpferkLRSFMVfYMa9WPlcWwpK4Qctynix2LhY/tI2dhKEWoqG3Tcpog1lQ3FqsSZ1iIfjBl4ebguGnJUrIg0EQ06KlaEmsoGGxWjm+k68Ptv2lVAjudVEQPsIyiPuhWBBqBloeqGUQVdVwPt7VFFnosf8ciaHZndp385xIied+hIbiQWkKM1fRPLss9owPVoFULfgmkaaoiJYAjG4LZSw5gIBmKE2xDQBCq5NaCRNt6KrgQ1Fw3BybYjq+HMRENwRpZNT1OfXTWsJfEAvAb5j20rqvlF4RCshpoCkMiFILwi8j9tqQazIByM1XNtoThbgrSpeBBeLBV6ToAYS4Wh62KG80XWaCUdkc2cUNPEGqXUJLGZkQVwu9Puhe4J5ictiQfhZYGEkflHFIS6jS/IeEm3J6gxoFOfKovOPpmlQu1K57KpqBHcKjpvYQpiZSNY1aBRiVVBRL24OBzXsgat4NYFAYwXptuaRAs4/fN2eRwBP1UDx6+40oPW8MKxfkXIZQ0Q1KGvm/5J0VinIByAlW1UVgKaSQahVOODMcF8MOZVzQwnkQtAiA2gVbAqYioYhlFR05RJBqH8A2zJo875h9ySRwspzBptnVJigbaZMD79qYYylw1BCnbMr8Ypd9SvkfKiyNNyAfO0XB9MoQj53IipYAhGMvlV14WXpAPQ2o6a3jGRC0CYSFTpA6qrgOCG2TtXY5XYNtfCt1UEuIUixI7rv+in6HzGvo5s21XjrmrRA2DBjUyBA9d4wEA7R6rkFfkQxPRakweYODg12lw2AKlrqalgiVwAQg+r6U8TuRCEMGfTa4ASx9Nb+IxgpSliTEUDcappTTPJQJR7ZZR7KMo0lqAS0IJwQFZ1PqaaBkhqFmxQKXWqAYLatV9W66WialYQDsHqW48oxOyusEBN119XAcGdRqBUQlwQDsDqW6QfNFc7NcvuJekQtIp8U1LbLxsJgytSs8sqFQzDqG13qigT0TCca1WUazjGraKxVS4aglPROh/cyh6LhYKMq5oRQEk6FC3bRhJEVqhocaRJCRS76z5YCpM6Ew/EG1p0fq6MNxcPwJuHGVeBW5IOQWs5ylAz0QCcEpcgcoMKXYjYS6psVwLgPgQqSjd8NZ1CUTgcq5raXxQOxhqoWaYqChc8wAJyzSOZe0Cc51CwkY+QLWD36yUH7OMNQCiiZ2Jv6GRjWHdpzt2mCtyWZIvQA34hTJYvfuGthFGtOlVZF7zc3NsL8Kpcq11FbfM9B0Hx4c9AxOlB5YbWjd0U7QbgA+JCyjdrgrfE88ngJbQe1VtS1gRvCa11pBmnji7o8VODNXVtcBbF+8xVWZBLhyQGX24vEUOetyhFrgAMVNIAXlOigP8W4ucwGKFF6taozrJx6nW/VnUWqm+DuzXCWUaE+7Cu64IRmXA4XgXnHArAsOcZkjAVKhY8C8zAa55ZOIWkCKrCLikA5Lb+VFcpM+GAvKEfGcpGDrl0OGKl0zIF869HZEfqgHPpSv0eo11WmqZk9Spay7ZIX6Tb6MQTOaPpffImiwMnf9FospEvjpfCc6t4R+Gg8ePjrYCi8SWLSbEo2LUo4y1KGgZFdckliRZicVaBgjz1BbptX1d2mSKr985q+sbrxZvXi89xev1Gk+tihQsTPwb6n/jkIx25SCcJhELX1z3XWKR/3wxvkeqoplw1iIjXG854KEmiggOkpyhBgDSUpeq2CYxMB987plqYgpoeIIM8GmL9ZOv0++D+hELGccE37JNfKB3pU3Ejr6Ds4KpMtPcyQHTSy31E4RUsBzjVpA2Y57t/YCNcXLDxQEYx5oO+ud/cr7KNZ4tf8KNl4BLN218/rbWf/6ppi3dpoCgQnaQkJxc9xm0q+ayjIMD0DnZlCuh2QB860RIl7GZ6GMm+G7qGay9OZBAUum54XZwuY2hRbEIQIuNhYduAeq7IN58Q6XlPLvkL0oA0d08E3nbpxWvqJJOyaUFLf/P+87vPizd0VAJbcbMkj+eZyRH0yGf+Id2l7pXgyVWRFQE2yBtk4sA2nDiee8O3kH1gkwZkGHoaUs8CNVmGIPDB7U8SnB3zVpO+Pmv+TdYL6NaNdEQK1GDH9B8XpoPof5TJh28vc/kkj9WBXzzLZXfE+ZGnJP1bC3F6oC+IPM/1w6RmT6yeCMQBhhoUiFPAZUCf/0O1mqRlUtVqOF6komNPGj3nWdvqZxsFVz24RqHpPrG6zXKs/pMeBQh0IJkPY5J2hYy+FYvX8WNI5x0h/Mgjbmhuj85aZTfiuU9kLJD6QsZsyOiZiaTcKFDrI/Ic+deyaWef5JhiJYXxNPigpk2VhTE+LLXVdjOWxifnFAVjKfvzCT2qTkvjankLfPbXWvzv80V7Hsu+wDLxE7IfVOuzo4t1iz/TrkdHrnITY5UeuiNDhGQrr/Ji06Qzy1Rt7EQuta1spD5S44onaNBznXCTKhE/vsqOPqCXFrBLfBS5pYg227giS8lUKO3qg5cgxI5SDTbGHnPfjTuSSFrTZIKvYlYfD8YiMl5VNB9Ok5AIsNFLiwYHGb77Cz7TpoQ0bV8zH3jm/32jaZtftyvt3fvNUkTA59/0nz5+1D9++vDx7acv795+Fnn5f/706Zd//enTW/3nD+Qv/Ze3v/70+29f9E+/6j//9LdfdG2zFGKpiPv8+8ePHz59+ayvUokQwqThfv0/H/RfP73932w9ga2Ak2/XByJmKSaJJHnM9Lef3r8tSft//m/khv/j50+/bFaH7U/xJynJn97+S4Pgn5YrKZlvPrz/+OFvb//2RX/z05effvvwV1Jc3n4mn0XkvP/57S9ffvtMhP3t13d/1X9991vFdjv8H4UJfrqZ8i+i9n8h5fmd/uvvv/0mQ/fx80/6m0//9vHLh07Q0i1vcqCffnr3m/7bu5/196TKvCP178uHNx9+S8tpSaNo6WKif/9C/vn4U2rG/3z70y9vPzWleGHYgmSteUd0/vLuw09vSf16+79/f0eKh/7+p8//77u//bVBUOLq+DVezYNZaxNZpaFjNvJ/6Wc9GyfqF8PQfWxjFOB7NCfybHEmZU9/Y5slfde2yUBz9nbU4K9uEM4Nu8ENk3DTv/U379drCjo9YGUWQo8qXfAtdiSS75KEzD7LJnMWSLFpYNL4KPeDTaPqxgdvLhnDNjxMh88fvKQ1oh/esVX/7Nv7yLjPhtis8XPZ912P3RteVGonyZwjxM93zno9FsG5QnD2Hrd3QZNLU41620Whjk5WCYL6fCUJ6KCd5KffDZA+de/5OHO6N++Noi/+ZgVhpjiFJP0ZLd25hMb9OItcsYw5dCOEc+q1J3ts9gax3TE91sTPJP/5bPiWF5aKxz+lM528HaJP0tbv3h6p4Jyjm8HWucmMMYzdTgXCeDPQGBwmChE4g0Am3dCNDExprzBVCriOFepnn7TepD9j66UTgdzogQwDe1MWB8Lgh6E1QUFI98K9Rx7rUKex36C3Ld9M1n8U+9XjcST9z88tBP/9v69W4zA8If9m3S7BPbLtibIhQ2AnlKaG8LCJbqFllAc6LbszlWaIj3UWcTyYCoU+4Vh/si1aJQZ69IYbwUEPmPW2yHfu6QQlRP4Fh1WGlsdqo947h3zzo8TYdyBHeI2cU4Uk+W4cgOrg+84h3/yYDMHvzNVuNJDGYTjBod/fke9/FBqS19Tk7WMvUf5oW2N+F4TmjyIteocOzxMAonv/29r3GEqokQfGaur678439y7+djKoljERQyv+Nm7ZSttkvdpJ3v0r+2b85FJPJJU+9R787l+T7yZMI6VUIunU2qHefQAp06IppJpHJG3a56Z3Z/rbXf7b+Ak1KpxIqnV7Fu7O6e+Tpt4kkEL1stsrcHemD9yxB+6yByaortNgiqTk/DyKgOn/DRjX6gJuf/JbMKvZtdTyWLsveJgLeCAVc37WXJ93ZPKGjeBH+us9+3MsntQHp8efdQd5ZbL/k8j7+t3de+T9+E//5cPvXz7+/kX/5d2n/7r4p//y8dOH//X2zRe6WeS/3rOXObnjLUj3FiktiW++ipwcJXK98qiErRSeLppmaNrmvF1pltO4qUiwIaglmBUYwjXhzjGcJr9M73sc+d8ro+m0jXClI8lxH+9mZFkTWGstTiYzvI+3NJosLiBbkLu/3KL7QvN4QskZ8UI6FgRWno4fuqcJfe+GV+zbxKxvK8lbw0h0vHN2cBCQdLyz8e0SXn9sKrtjZBudbotkXPH5/8w6uKyzkH+PnzzWILU1Ru/e0onqh9TvIZxezeksx0o56RfJdoS0SDxu6f6PKnjHC0kZQqbJNmwh+/cA+9ObyNufSnUP/2p/f3d3MTqmOHwibu4d9Wvc+U/PRNbFwbewacQgbzzd+qSge+QZ5qgc/kpBP5MPmci7Jyu83rFJwzSdbTJu62mxRcUZlm9ENvJN7OGbiW/Gi/wK3HysupFSbNYG22JrZ3I9a3OjMUTWN5JF+bNpA2+bZxtdJJp0pS3doKzgHC4VU2GiNPghPeKRffPdD//87NhUR3wQjWhZ3S+ZNaRMufSyEPLV719+vTt8ffXPuaB0kpbteoyMe8c1I9LuBjiMvPs3bLvyx/ixj6Tm/czSr7BZ9J7t0iQSiCwP++HLZ4P890d6eVsyAaya5BExLBs+h9j7CzGm9HkCI018RpEdfsZhyJbnhaxbqOcblvwjAEZGgjisYFTjECY+nbYKVg7NdW/4RnqWwPBjzUlI8qwh/doUqqte5Srh7uol8dX3rz6/e//xt3dv3n35N/3zl99/efehcJ7p1etXf//66pe4VH199for+fj166sAPWJSxl3j4V+Qb9H7HQL69Wv6D32A/j/S4ngWecp8+I2mJGs44h9ep39UNmenX3+f/kFjPHzw6u81u1iSH/8R/0OkvCpk4bfF/g+SLTEC3XgWkFz4979TlUmGE3E0w7/PCiA7PEctTOKK0KNA8THPPKw6edr1rYtFZjLZ4+zbpAqRL1bfMwkhacDJp7v1fqdpW229+8f3otpLR6YHQRyPh9V+udWO4hCtwTMGAa02+/Vud9wcRInYAYikgR5GsFvvN4fNarUXJGg4eCWhXzseV9rusBfVTnKkEH1Jt8++MYiDpsJ+t9xIlIwih2mYxhCM1X5/0LTj9ihRTcqhUAYVCqJ/u9OWGwmK0nEo+VK53+625P82ouUiOR48SLm20rbb9eGwkzGfhtdLT4INotivljtts9xuxCHSRIjbp0cyWh9Csl4fd6vDeidRNUqF4Rb7gYYmynq/PspUDxYNjkbcG5YWux3tx5YSaUFahxcyKLMM/YLC0DwNajaXu+2B/P/NVhAkjx46qJnabtak0zhq4smQxycY2HGSUrnd7NYSCOWYIAM7TzKYWBOYIXWDzAIsMssw6HVZw3oPbX/cLw/7tUTxLPemz4NqyUpbHzfHNRnuyfViQ7JkQ+rncr1di+ZIHGZxWGlY7g/b5XKpyZSGMC8GyCQqQisYVjhJ+h/Xm93+INFCJFNTCweDigEZRKxXq6NMMchrB0xq3JHGaqMdlhJZU6wZ2ImGUGy0zXpHxvyirXY5NkAtpNHQNoy0pQepIXgelGfYoPdApkFbMkMcljnXgc3W3Wq91Ehx3a6H5Q8aVmn22/1utRcefJ5CW2cb4M6IJIhxlkyD3fFwpKMs0S6kpl4PNEOTrKukB9sejivRoS8LOMsCUyWjvWFDHDIPI/2YRLWoRk6RUb9eLzfLzVqmqUjVJ3VjWOOwoqMbgRFFuuGs2IbTDZUSgwhSFTbL/X6YajmzSU+xXO2P/O6Aom42BUx9M7RlkrJ/re1W2oa0RhIIpA+3rdjXyK40kkqFw2Gj7Zfanrv3TgE+fXmrv0mDgwVSuknSb4+rnVT6Z3HJdJICyHZlx7Dagdi+0WSKX7FXMmzXeAikisDmeNgtyRxPJhXwI02BK7qZdnzHmURPdFwfyOCAvxluVS9V/5fHPRlNkzogrt6qNMF68pNkOiwPZM6/X3L3yB0goY9uAY0ZMwyJjGbXy9WW3w9RyJry+HFIFt1tl5pGXZbcfWQxZZgDeXj23K0PJGu05VGqnFCI/Obk4TCrtUYGLsc9v2OmkDOF4bQVSNaazWp12G1X4i1nZYe4sOadtl9vNluZ6po5LKU7y9V+daApv+We7TZqp0dXDSzXZa2Ohy0ZuZNuSxShtkQrMVrcHrb7/XFdz3W2AahBudzVRp/dyM/CmOrZ8qNcnh3pXOuwOtQTTA10SPI58gZS362Om+VB22129YIOi53cRrNoXOSV7DZIHVnvlpt6LVGMriPZWrXXjis6Bqm3p6qRT5GPHLnRKykcO7qqOgVzaEg2X9v9Vjse9nUPmWpow4kkF+rI8OO4PC439SmKcub0HiPZYcL2uDtu9sf6AE41OV2ill5z2pDx+G78qkjnU7ezK7tUtCMz6e2hYWSinNtBhD1gx/JcuVnY3UpbbncH7XAYv5Cbnm1LQW/XZCR2OCzH72ewZFtCPT5H0mwvVQ9GGpDZMr2kl3B3oKORCRrtc+AbkhXySMap68N6NX47cvHI+FpySwyNLq4dG/yx6qEtuYTekAK9Xe8maK8psk5vBZPs18m0YHc4NmwvUA1+PUuXatLFrLa77bLBX62e+lkOesX2GJGOffz2w9Jkh067I+nPj7ul6rluAzOSHDqRSeN+vV0tSbEeH9pAxlVuBWBNxqi7zRT10CYjJ7lB6mq7XG21CcZ6FPn5hORGebvDdr067A/jN9UpNl2wsm6ys/T1brPZrXcTjJ5szDaTyXWQ68N2s1o2LPEop5buZ1ab5Ya015sJfDi2dDezJKm8o9VydGYnkGyx10dtv9H2+/EbEs+U8zrd7Y/b42q93Y9fCT1frt24W203ezIVaNoyNwKzHlgXwirJftC05frQsPalmtwPJd1OK2233JM57viuaz2Q9fGxfoUUkfGTOXgJpHdRbTZ70q0sG/bMq6aW7w2p02a3PU7QsUTy3SGZ3ZJGeoIefIDTZr86Lo+kzRud+cmU3AyzPWyPx9WmYYOmImQn2UIjWfvISENbrkbru2vLoXL9yY5u/NRWAN13crtWcu83Cl3Hkp24EqD9ardZAbRkZSp8iyRX13b7A2laG7bjDE0ndi5GdoK/IkSHFYR/sEwVf5LdkrBaH5YrCA9gGSqgMbAkp4pL7XA8LrcAI74KU4jCSHL+qq21HfXfwSVU4BfLlNxOAzKfXpIcbDgCOJCKDm2QbcvtSiSDSNq4NhwsGUrFCpVUUmnLPfXObzS4xjOL4pXixYfgpfjoTJJuDoJLspwuKf3JEX0fXyzZ1mJDJgeHA8T4rxtS9gDParfT9hCbKtrw6oFdxSvHck/q60prCDEgjHly3dB2kYn9yqGsykfJ1uWwXx2042ELMLMqkVrlsyCSe8NIbT6u90eAwtgFRzoN10cXOci7PZmZ7lZrCOdFBbK4gb+Q0ZLTjdWSbksEmCM1JCW7r8dwJavL3UrbbDa0j1NDl5dCqaQ7bLWDtltD9CqdpdBDfiC7S3+7I5PJDXh701ZRpKaPu+X6uFuvAEbsDYw+DjA9ZyO5P2i1oicsjgDp9+b953efF29cH2czQ8MJrEDPwoDKOc9pDd6tIFKvlTBRLjv32ZEWZrmG8MI0EIZ/snga+Fl2akYavz2NswPgcGlNwIukS/a422532voIMPFoYqNHIQ1nvZb1zu/pJkUNwsfdQOd4kY585/EgS3dcbw97MnMbThdgI/Kt8KV0fox9SPd56sltyGw2cEKb1QZngQrkxl/bIz3dNAn8ejUEfb0+7nfLXcO5MNXo8bd0VyXrmAixXNofN8udtjs0BCYYxwJ6TJmey5Qcuh93NPTJoSE8k2r84Jnt5Jcr8Npqt9xsIfbtiFOf7AfdsLyr7GHEzWa7Xh23EJ2wOLx51ZEt2czs96SR2e6PAHMUcXBMviLvPMoWmc1+S5ceIPYRy8E/4BeiVTr1ydxwpR2XK4j9dTIGmAGSLznHDT38v4JYLBZnv6JAMmzAfqPRfdwNMTxGwHaQbLSD3eagLfeknZkEGzuG48kVkx3dtrZriMg2Ercn6ZJdrw9kdAtxqkKc2/Mtxwot6XbxSEbm2nIJsSlCHN6/yY54j7u9tiGFHMCdIo4dynNrZHar7ciod5KJxmpQCJfVkS4qbxoCX43Bvh4WM3i302irOP6IsTLBk/Q77Ena0zBs007x5Jxie3o2e70bv8g3zPGkkn+rHfabKfolj97yc5MM2rfbrvdrbZqZXWGOJMVOsNfL3SQ9qo8vkrs4t/vVerPUIPZtCFBbmYMu9gzTC5vJw4RQcpFnu1rRzQIHABesjBmZV8PEZ7mjJhttf9xsRh4a1Pljr4xce7/ZHch4cj3yhCm1IXHNSC1a01Dfh7FnegXwvOUZtN2Jhl7d7PfbcVvPgh2Jo0auBq+1tXY4QBwflISXPHJF16bIGO24nqz4FNxMcuNMbXfcH5YNwYNGNKDgapLKhc2WhrfdLCcrP7m7SYZ/f9xpK209YSGiGxmkg9SsjuQfiON7cvDMXSa5AWO1In0vyHkySfanAdFqDzTQ+AriyJMcPHP4Sa6aa9vN8rCD2AgryR57/eRam/VhsydjhukSPnb9yZUaun652m8ngy/4/yTLznK736y30/VYvuQEd7XWlkcy5xrZp1MgD2XR78j8dnXcHSGOQrSip+FCg8ij8TMWRhrVOY8kSuzCNlUtu2GH5MBuvV6uGyJmjmqI69wsj+7eusnu7DnsNse9tlbqcugwhAYPHZwbd+vdYant90oXrKpGpFva46/l3OJrOlqj6T8yd167ZbcikMJPt6+sVbb/TeRZLGDDkTt5Qcb3BH25mQzcQYbc8ubquKaONoidtFLk8eSE/Cu3PHu32m53h8N6rXTA013aL5Kl5o5uESYz3APEDnDRFia/JVD2YI+22222E6BbQ9k3ZEK7PoDEROFGT8/ZJO26lCd2ud/ul7uGMMZqsUljriNb+vgldfxttkqHlU3UpCmXpibzVnrLoNJ9lI3MpBUfkNTbzW5HT+aM2e+zcn1FK2lsbXlggXPGZ9a2O/nEZjttNZCd9aLc25UmzX3c0pAuB6ULCk3YlwG18W61PBxJ4wcSk1e0wS50NVKzau2w2azWR6W7PJvRraHspItfki6HzK1V7jXoSPdHZEeyjpjNlgxNyAhFJTplNH2LMJRGJtL7mda7Fb08BOL8tihz/NWAax40TSPTCG1C9mR9UnID3Hp5XG83EAf6RfADnB7w0k3s4ZuJb4bsuWEymdB2azLQGrHI53Og+NYah3qM5HwWW7rOCnLGXSQDcgOSUiS/GXG/0XakFijdUd5pAbvByEM+eTa1Rnqz9p22We2pI1vlsF3UmgHHRPa73XKjNV1cOJ05CCNTsrna7A5btS4bUWNk/U93B21z2JHOWuWkRdSYB/xC2mPyd+w8lrFrt9GWmlJ3oIxRQ1vp1XG53hxpMzcjw1isyDDyJQNaUG85GSoq3aBXM4l9Y4WBfnt01pK38O32h/V+u1Y5cy5w03E5+bhI9/6SnIgCom9Q/IE7TVtvd2pXWBpsoEUK1I7Var3ZrVdHiIAjIoawrTGyk7s1aXfpzp7xkJtH7HLzu8OelB2lm4O74c+YtTnS+5JoTG61J+Qb+NvmG1I2HElPsNkrPURRMaFxuiG5uWqz2dL6OiJ9+3xDyoTtar9ZLVcQwTPkLCh2xefoZshvkr9bHQ5k6goT/3i4MfJbzdcrjZiyb7iaHMoMnN4Pm8Xmy76RHNLREM6kLClcVupg1qPQkgsVsSIjHxo9S2H/1cU9YC56t9ov2cF/hYeJutDJA74reTj3jjoolweQe2kk0OX9GSvSuGy3mqZwU2cXOMCM8k7bxM54dQ1+nwXsSmpL0kFG5lir3Xa9Vjhh6eIfOEs8Lmm7vlZ4CKQLHoUhplF0pcsOHetsNprCbalVfKvI7waSh0U1MrPaamRcMF6PWgPXT2RY4OBQ0oTt8XjQaCyGESxIAy7nYwLJueHxuD9uVgoXXDuYB114RMYzR3rcZqtw0bKLXX7suNrv1kd6wniSghIPxKRS/Lhfr4/LjcLwUVXuUhUdNhHfkNq5prevTJLomROK9K5yBuxXdB6+hbhRQSbxh0UC2NHLaLcgt0RLJL5xJcKGBZKgu/HW64PC4GOdBgxB36wPh8NqOcocpAFdPpoB3QlEVyanAU8nT5Llfb9c7jWISOkS6AOOIi53JM0PO4W+pi7wyuRJyoTDjsYw0FZjTP+aLcgmT5IO491+vRqzk22ePMmVn+N6t6Rha6aps8XZk+zqjrba7tWuUftu6BpuekYu3+FU/l73kWm50qE+D9vtnt4kpnTdocWSlHzoKrS2Wq7pZFZTuvjDlx2S0evXxITdUempdJFckFxCoRfjaiA+hcQtb+JTdEndH+yDHjzJnfGgJzxo8AuIzfAluqR5yemkxjDHPRn2HiCubQuwzy5Ci69lYzs4c8bsK92wXeNBdkpN7zva7IGO5XHhmobshd7r1f6wX65hNlxzsWLZGzRJsi4PRzJ9A3GzcLHKX0i/X5Ju47iFOTTFxTrgKubjcrVc0jo2Iqxkwm72B21L2ioQrw8X6u1R+s7B/Wa53W6BQpLUYbOWv9wQ6IEmtwdP2x9p2oJ0s1y0pCmQhT3stmRYBrR7mwuWtgWytNpKoxdqAR1G5MKNmwPJrdnrw470Coq620ZY+bSlZ1N3h+MSJrg6Fy5rEuQW9VZrerE5zNQoZnW8KAuD4EVyJ2m2NID0FmZ7WE6VHuL1ZDt80oDuyIgZJhRYzOW5T2z7dWnpsPSl5IGe/eFAJil7wHFUP2o8rJasNdvDZruC8Wdy816RLVvNt2Quvt0td4qBrQqxx/xokttcl/vlZr3eQQ5Wyszp6b9S+ZVb2Nmv6AW7kE1AP2pSfuXGrNvlfk+G2MrahmwT6+DEJZPr1ZEMWA6AvX98VXfhHlx6cbf0eUTS1JI59n4FdByrA5FIMXBAgz9J784gc5XVbrdewexNKrGmztBCcsrVpgPJ8s0O4hrmTsJKakpNqA6kZK6AIg8mqDbGXmg5hb052TdyEUjWB229B7lqm4eRdVN+aMiN8dhQig7yRoQlEgmvZESj5Zrt9RszcU+RNO6Rrksd14AD6F5a+YJ7R3CXy/1G00DWMFt4rQqw5C4mMjVZ7dbLDWSjlaOmDVfeEsjNCUi7uicDQTW1K9uyMYzy/yvuSpYbV5Lkv8xdXbkv5znPac5jNJCESmiBiwGkVGqz/veJAEAVqYUiPTPRbytCtCc6c4k9PKLkKZ0mT5/WCPK4rtvq7XRAxydMlgYZfCZ64u+hDfMw3WYYJ/q/iMkUyTdRKmfEf4I5ncNpBaEzaMmoV1bmkEH1Zt29/FpvKv6DV3B8CVatCu+iVTlKPS5w8ZJNuLA7G7zypBBzJBlGYNPgewZWwzO7paAzJnhqbS5Yv/fNbijx6o77MXB08RPQURdD46rIdtouUQ50QxcoobW0Olqb47qOGLnPd4DGL7jCtTqCdEhSShsj3Ysy2DD9QLc0R2n8V2s1/EIwY8EzB1WMOcodvoIGmybOKcndkxmqeb7BtXhsE5jnydOL0uWgIf4KHqeisVJ6ZUwMIsfU6zNcLNbOb+XUl7xom+0zaiabqKLzOkfR/1dI/24wFB1XXLFNQrgMuGF7MeeCNIOJMQtb2hmytlnyvwO4//4frQcjrsISoF5pq4LKtq/HqjucTKXpNaZVA9kjQpgctdSXyPjanpBBusHTphqfR5jwVvJS1ZsEl/vBOsFaNI9aOIO02mDpKpK4tEpahxxDZi8R7eCGt2DpSLk8J/0M0XqJDvt0wloSqjmCzheIanTXrLDMMJijDvES0LGn+wYa1y56m2fk0wWm3/tVh902LsYSJJuyyPQLRA1WDiANTy+VWQoXLxA1CpRHypEsUj5HWc0loGoNIjIyGBt9Dn6SC0QtzzID+cYNaRGR/2S3NR4OJSM+kNhWOZoNL0BtemzjtIqK/OsclZoXePYdWHAulQpGcZdaZkQdKrUNyUgTssyMvgSE5leYDyL4GE2OqeEXkHpQ94sYyA43IrdiG5N84ISNiV4z9xol5EI4YsrjUXNfNlz9P0hL20brlKPC6ALT63qH2W1OcOo4S8/bCGiIkZ7MfygopEyUzmTpmb2AtHpqsKFtD9IYG0yWKrpLRGhpevTORt64/ICGNpUKjH3SaQrKxnym2ylBlrBYQ55Rm5DH9T5brKrv6w7szvEuKEVqLvcGLo9gE4nn3ETU2eVAylhiS26A1i6flTth6qoNE6KhzZLBOeOMyeYwTaimT0SndCieiJmDJfXD9sFNpT6aoYE9qyyYIKVlHSwdK2FlPhNzQsaxEygER1BIHNjcAgrvfPJKks0bctAvXiIabScw7eFU4KGFZUCl6L0H6ZSwLoh8wa8J2xjXwfKQVmiRo6H+A6AGHFciJS0Q6RiRW8VwXAfTecw4n9EWP+Gp0OZIyWqF1F6OYXkXkFp4Rr03ngxym1tUnqI62DIFJlYlzy63JOCwDnaSAikUHtSYH1CSXApRCi9Ddgtqjw58V9xOS7o3t1HQgaqONk2TTJLZQiknPBxtQgB5R56Ky1TrdQaoR804I6wh2zIHh9IlIHDHpLPe0wLlGH1yCeitXz2idE1W6+iE07kFwBSSA7dORV6oHA22X4BKssEflDZ063S+GOaELUmtGK+4ija3QYAbvTEqbUli5haXQ7gQun2GJ1hmoRkYmE7ov03L0+ZPJZb8jDrmrFpiFmX3PbbF5hG7jpJZBKJQOdyXK/DGoNRimDyx4FJVlFQkahWDjzmi51fg4nychDB6OosiR9X7FYSJgyTIePbS+wz28weMJwKhX8u2Hn9KL3A/SHmhM0iZ70A2dV0HoaQ145t/n9HNZ0kdstQIfYf5dbM89uPPh5cg4Y0znmzwHMUD3wH912v1Mp2B4SUENOjALYQ5si7f4eybdf1atc/jW6cn7GJp4wOPhcpgcH28/E/N/lf92Gk1/vfPb/VnfJffWfT7etU8omaPCTYaqwqchup42NHv40rK4Wdd3dZVX78/n76L4vLK07tQmSVphRCZGCn/SWmPhGN8ZsLjRbX7w80zFz/AcuYueGVczDEOBwKNnBZt6UbSWcmv4CbM++qBPm36+P79uKtL+PtqsTp2L7Ce5qnnnu5qsaX/8DUY79/H8eBjh8Zb45muvID2/hb5sNIJoJU3kaR4DmIFfLUxA1kKDjaU0JRXV3s0QpOQW0mwQw7vHzonkGvphRoKrcoLxEsOjpHk6ELAfHofK64T2nBuL0PorMA3AnMmWmtrvcIlULXfn/wZhsbPk5N49hLmSyJk5DvgPuIVdLSgyQCFiToIEfFD/hXAsXf7/RVYMOsN84glcEzcAg1aNhddCD4hHf09Mu7Ibzb7tk4K1BkptCYlh1ugjHDZHuvDbnd4OmHdrvYMkP6AtjRy85s3CfLnJ1TgLQ0qsM+RH9eifjksHpv2MO7s5U/AvhYu/Dde4zFYDCwW3XGCk35pwvlurEk1VZ4HXwuRG/N0qenp7IrTU1KxrPDSiRSX7T6o3W557FGszlkvrVKZz+13YLEQj4rChwROUGg9Ic/XcU2USymP/BsePeFd/p4QTw2np+eMoRGpeGqw0SkFHJ+Bn1h3lodFtaaPPjT93/EyoPER2TZKScNfhUkfta0HjrAUmEEK8lJCKZDrt221aVaL39XhsF6mAFUjA3vK/JWrSFu1qvZJAIWOUYWkkserCPfVa5frcJI/QbsuTEp3/nWwddfs1rTzBDjtGlnvuBg4wYe+GWiea2+CkiGlkekq3v5tu0oBKFnly5iSiLouPVerek/XqekPSTB50g/XyBZYx2EZD9XqGY+DeEWbzHMLcqI7NWIsTyvHdBxor0EU2gWd0nN4FeDn24Jl7mgJNcf2yq3jByWJZcIkyUqyPLMexjOYX6tJzBUNllVlEtnEVawXihKBaHk4CavyQgC/0ZNgYsWQklQ+pWfnOtgv9CR0RLlyX3NxzgxAM6ys5BY2F1wxvOd6EksjW2uFyWu+nwvQz3oSE/SBbjxPdi+EcxJJpIngHiXJA04LXKC/ejztigcjY1LxyDWAbZt0TaRRgVt1E9Je36P7Xe0bsETRWe2kSqFZvLZoKC6tHXmJoYRZNsGaWgWaZdM2B5BrVAlyuiWTVJS8E3hGTImomLithPHI+PCCRC2l856kchlgKe2htGpaMy1lyviNrwJqw27+atv3kNrpPZYrh27XtjyTN194TRiV1lF69Uu8L/bq0LUDv2BbvaG5gaiFoBOR1yz/tMxPO1LRGRdYBzV0XWfV2CSaxnX9xx96CelBbYTmQfb41j9V3fq16upfyx29eve2+SFhjoWOOnLEF9/la7imS4RzadHCOabyTehL/YDvdEfO8YG9acZwmVJCeucaNFjDaMujlWJCe9E7rGkw6WhiHbthwvFi98IDm19PE19pDVHqJkFKWpmE8PiNQKd1ZaCg1x+tdDyQJhvSzR9lR4bVRf90PKx3r9v3mWSf3xqTkN+8Cd57JQTH/It+o9M8s3u/EbJLxljDuwR/oaHQ4/DU0N3bE7a3X5tlvT60/ViA3L3x6SJNuz0MlR/o0DOlyB1KGBT4I8rDU1dXa54Djw22Cz4aldBB9iPAU40aNtRMClIHIUG934xvKIRDWfs8WSE24um0n1H2FQ7wgRAaLVyKkvgRYdU2v7cJ478l2fw8w64cwuV2sTliyj8wDWI0CXV5P6MjG9iZxTBmYIsSwXMuSgdrEuzOn4HSPh9TmHYIoI3kaJTHuNmtMZuKlKW0KXSldyBcdNUrVhHNXKEyoTzmTpB0Nl+qvgH7tZiUzgWODRYEvGr2T2QFvnYVWnyoPcfRZUKf1g2GBVwOF8jk8cIkuG/3mT0Lro6Ch9oYF5keZjasKaJTCuulYve4HNx6tX8HuahaUFMyC18IpMxLA0257MZrJ0wK6cXPINmX378t9rsW23LjtC1qtLWb3QH0QY3VZHCUdBw29EaPkSyRKLfkHTudkHa+BR8uxqNjNrGYUOD2M759n1TYzPNchHUJg/pugjgQK4A8pEoJK1TCyO6bELL/CgatnfRMVlDQe2WAh65awaSSZEhqYxO6Zn52Das1PAGJFIkn3zVlsNDP+J7TNLMKZPO4FIL1WyDCsoYsRqZ4IqerJL7XrgGHrD9oKbSLCcHMm4MTiRYYk1IxQ0LBu9IRUjK8Fk91u69BTrgHHkHgrSi54X3fjrPfk5CGGEOQoqSWZqCrtsHDPjaGaMjjKryYmwakSpROxkhquiw8epY6zeSWOpKg1K5krPQv1Of6DWQYssqTNIoJNd03yaNV97Y/7E5nE6uaZnYZZRO4RG+MV4BRZ7o0XumEnM5d4RSostsYoUzRONrfvYab9oySMmUA+T3nsSJjF53qYkg7aptQTXLXxcFPJo9W8yGGBEqPe5COCcnhkLKmXGx3XLR1aLDpOdIoHYRNqUC4B3zf7g4T78IGFVRekKKPNmGM6V2ID7uO0IInIwYVtU0Z33QP1hrsjJcmauO9S2Ayugfm4+ManLxK5rLSKYzg98B8QgfEkmniIhn3CZy89+DcVOjgrGikV7PdpH31jF4jZnnSXs8kYclrwro46WyS6ZzAjXCXYAKLNLQOZDSbBMrLn+2op5oL6yfNmlJfbxyX18uiwYYP1goUs+GqVxeKptE+GytYlJPWVHif0DtzF1I0a26NCCLKklmfDzBTott0UGlFrSmaTvveBgT7HZTl6tPCVTw/Wq2QV+2tdYaMq3lEbY1y+1hLgjZoNc8aD3YVgjNGE6KUM6nXwa7CIpGaZKzV8/jXqeUf2gm+XwlU7HeBRTOv5KJE56VIGE12r7EKppZ4zo0KCRMJ7jZWsRQTh9FEKJmLPbdVq+16t8HrVqR1ZP9bMxdcNAWveFZ8CpXXnaY1tvXWGx6O+p+JpYCGCw8ik0rO5LRM0RTIdNU+OqZ8yI+02a7a47p+f65gMmVhuLPVJYxluB1k14BDw5TTTE1QopDgE8h+K+F5gt5oZxN6Iu9CmZBylo6wqpAyB+ZmqGPdNFiDEz3nHwuI+k8oh0paVCNFzWU4BRT9J5jHpuVetEd0ZqISzomQwjB1M9ZVtanbFrzy1jtpY5Hc3iecK3QelnS07UbPceFXTxX9owTmLgmjRSwRNf0a5n7XomwBgf7SrkRU4jPUOpVMwxjporJzXPyECJpke5lcpjnE6Ap2l5yxZNm7hO7d20EOrBYP6h/YFI2HQL4Sc3LOcZ9GarRq/c9jf1i09e9q9XZKp2NngdwSG2WJINpN2B87cv7wumamh9fSlOipuQ6fXYIB+/g9wBYGYU1Qdg518Ql8f+QwZn1I+QLkLTgXFA9dnfsr9D0YLtAyWqVjLJDouI74jxUR09akV5SRJZLG3yDG72Ow7JrJEnn4L7CetXtDZ4EnB8UoSoSOPqE9dIt1t4T57SSPDZ3jCAxVrDDtJtfOqxmcSHTspAxOy0AgZ1AY6yfQf5TO20AQZ7hE9QrMuEijVJRSmnlAwgIpRlpJkTKF6A6Y/8SD7px59daWiGJ+xon22vJcQetShpnfDnJsFsS5CXx0rkQXzyegcL+W9sooreewXX+DIY2B092YOdbx6XkNkmxy6NIqkTCp9XaQ5M7iatySs+WlnsPXajegflSB25V1iQzQR4zTn0khl2jYoBcl+m4/wcUqq0j/RO2tngWhRVvptWZm/Bm8uE292XVvi+Xx8bHuFlXb7rD4kHLChahLFCd8hLwlJ7nfrZ5ruEJBC/bytZpBb26ZUvkZ4yd5CJJQWj+HcbxrsOvkteA8eom6qY8Q9zVov5MMdVyjOIPNucfaiB+UcNpzvHqOdXxe9RKbIfrALgZdnHmWctWD8jM4G40np20elB4dN0FaSAU/g/nxziEHHk4vyM+QJYgMvkOKR5GiIUNeF+k/+hbswCyH5qi8EiKKGXQ9p/1I94GXKgo78DHOAbRrXuh3D2MJergMUXqhmORyBrwnckFIgypJ5qieowqpa0iHrqXDstRkNwUR6GaFGSQWWtdHijQo5WcJevZPFViKxE0TivY9YRDFPSjJ2AUjyDpybHaO9AHB1KBgUoJUk0+Ys3APSAuaTk7zZG8X5ziXaC7Ocre5KsF9+QXExapaPYH1cUpq78lYLtEe9SXUobqjPzYHtI5TCaaDcmGOuMOAeLd7blAijKBNMLMt7qFhXx6FGpSLRbqkPkL9SxQNHlkTyBMt0X/2CWmzQWFKSWfUaD1HJe+EAVTz3CBpE0av3wwTrhPgLmNLLp4pQX7zFcrFqgO9EDJGnCFzeablJKDofXfWBi9LsFx/DbTHcklGyBiVTRgG8yNOcjp+JVWaeeODDwmjxu6AeCq6qY7c/bitlm2NxRsfOB7K8cZZVvYEe6rDea7f6H9puoShUeR8cRefLGmtfou/f9vutm9gKupBCvrbsetSFnpiDb3VzC9XUpSdrS9jPTTbYRDbrsfNQxk4KRV9CXKiK7D3HZkKh+YFPcwqBhGULsE4eAU1X8N1PcSIUPuB7HGSfjHKglGXM+RjRTNo6WhrVLAlDccLpPgoXWW8tiWz6Wc4p/b/BIoF550lT6fE6JZreOnj/xz6DAKDa3055/ofgZ/hCobIdBymZPHSlS+QKvki00/bkgWgZ+AJcQd2ZlpjVSyZrjuDmVK5HrzWSsYSPMpfIE3Lh0lPos6Qyp5n9/t6Or1g4w6JCnaa5lnZvvkXLNJ0IImsTWn78r1zvDuu4CZ3r4eRUPOYD7i78cAkLII0RcEQxBnQl6o9wo6RNIGsh9T8Yt+0Df3WRVste36gPwY2plOl08hv0A2j9MZyJ2iumnPBkshKVF73g8WEa6BbpZW/fWlXXc0J2GW7eGxa2tH9G+YxWilC9HdQw3384GV1gCpAvOZy+DtaKj9+cA/mooJUjg7yv//vv/79/xI0fRw==END_SIMPLICITY_STUDIO_METADATA +set(SDK_PATH "C:/Users/tilaczko/SimplicityStudio/SDKs/gecko_sdk_2") +set(COPIED_SDK_PATH "gecko_sdk_4.4.1") + +add_library(slc_locator_ncp OBJECT + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp/sl_ncp.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_evt_filter/sl_ncp_evt_filter.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_robust.c" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com/sl_simple_com_usart.c" + "../${COPIED_SDK_PATH}/app/common/util/app_timer/app_timer.c" + "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_control_gpio.c" + "../${COPIED_SDK_PATH}/hardware/board/src/sl_board_init.c" + "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/src/sl_cos.c" + "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/src/sl_mx25_flash_shutdown_usart/sl_mx25_flash_shutdown.c" + "../${COPIED_SDK_PATH}/platform/bootloader/api/btl_interface.c" + "../${COPIED_SDK_PATH}/platform/bootloader/api/btl_interface_storage.c" + "../${COPIED_SDK_PATH}/platform/bootloader/app_properties/app_properties.c" + "../${COPIED_SDK_PATH}/platform/common/src/sl_assert.c" + "../${COPIED_SDK_PATH}/platform/common/src/sl_slist.c" + "../${COPIED_SDK_PATH}/platform/common/src/sl_syscalls.c" + "../${COPIED_SDK_PATH}/platform/common/toolchain/src/sl_memory.c" + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Source/startup_efr32bg22.c" + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Source/system_efr32bg22.c" + "../${COPIED_SDK_PATH}/platform/driver/debug/src/sl_debug_swo.c" + "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/src/dmadrv.c" + "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/src/gpiointerrupt.c" + "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_default_common_linker.c" + "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_hal_flash.c" + "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/src/nvm3_lock.c" + "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/src/uartdrv.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_burtc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_cmu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_core.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_dbg.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_emu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_eusart.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpcrc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_gpio.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_i2c.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_iadc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_ldma.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_letimer.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_msc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_prs.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_rmu.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_rtcc.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_se.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_system.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_timer.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_usart.c" + "../${COPIED_SDK_PATH}/platform/emlib/src/em_wdog.c" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/pa_conversions_efr32.c" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/pa_curves_efr32.c" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_aox/sl_rail_util_aox.c" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_power_manager_init/sl_rail_util_power_manager_init.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_attestation.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_cipher.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_entropy.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_hash.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_key_derivation.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_key_handling.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_signature.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src/sl_se_manager_util.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/ba414ep_config.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/ba431_config.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/cryptodma_internal.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/cryptolib_types.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_aes.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_blk_cipher.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_dh_alg.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_curves.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecc_keygen_alg.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_ecdsa_alg.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_hash.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_math.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcmp.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_memcpy.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_primitives.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_rng.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src/sx_trng.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_aes.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/cryptoacc_gcm.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ccm.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_cmac.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/mbedtls_ecdsa_ecdh.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sl_mbedtls.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sl_psa_crypto.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/src/sli_psa_crypto.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/cryptoacc_management.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sl_psa_its_nvm3.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_driver_trng.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_aead.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_cipher.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_hash.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_derivation.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_key_management.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_mac.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_cryptoacc_transparent_driver_signature.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_common.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_driver_init.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_psa_trng.c" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/src/sli_se_version_dependencies.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_dcdc_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_emu_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_hfxo_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfrco.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_lfxo_s2.c" + "../${COPIED_SDK_PATH}/platform/service/device_init/src/sl_device_init_nvic.c" + "../${COPIED_SDK_PATH}/platform/service/mpu/src/sl_mpu.c" + "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager.c" + "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager_debug.c" + "../${COPIED_SDK_PATH}/platform/service/power_manager/src/sl_power_manager_hal_s2.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_burtc.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_prortc.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_rtcc.c" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/src/sl_sleeptimer_hal_timer.c" + "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_init.c" + "../${COPIED_SDK_PATH}/platform/service/system/src/sl_system_process_action.c" + "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay.c" + "../${COPIED_SDK_PATH}/platform/service/udelay/src/sl_udelay_armv6m_gcc.S" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sl_bt_stack_init.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_accept_list_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_advertiser_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_connection_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_dynamic_gattdb_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_l2cap_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_pawr_advertiser_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_periodic_adv_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_periodic_advertiser_config.c" + "../${COPIED_SDK_PATH}/protocol/bluetooth/src/sli_bt_sync_config.c" + "../${COPIED_SDK_PATH}/util/silicon_labs/silabs_core/memory_manager/sl_malloc.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/cipher.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/cipher_wrap.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/constant_time.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/platform.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/platform_util.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_aead.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_cipher.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_client.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_driver_wrappers_no_static.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_ecp.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_ffdh.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_hash.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_mac.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_pake.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_rsa.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_se.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_slot_management.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_crypto_storage.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/psa_util.c" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library/threading.c" + "../app.c" + "../autogen/sl_bluetooth.c" + "../autogen/sl_board_default_init.c" + "../autogen/sl_device_init_clocks.c" + "../autogen/sl_event_handler.c" + "../autogen/sl_power_manager_handler.c" + "../autogen/sl_simple_com_isr.c" + "../autogen/sl_uartdrv_init.c" + "../main.c" +) + +target_include_directories(slc_locator_ncp PUBLIC + "../config" + "../autogen" + "../." + "../${COPIED_SDK_PATH}/platform/Device/SiliconLabs/EFR32BG22/Include" + "../${COPIED_SDK_PATH}/app/common/util/app_assert" + "../${COPIED_SDK_PATH}/app/common/util/app_timer" + "../${COPIED_SDK_PATH}/platform/common/inc" + "../${COPIED_SDK_PATH}/protocol/bluetooth/bgcommon/inc" + "../${COPIED_SDK_PATH}/protocol/bluetooth/inc" + "../${COPIED_SDK_PATH}/protocol/bluetooth/bgstack/ll/inc" + "../${COPIED_SDK_PATH}/hardware/board/inc" + "../${COPIED_SDK_PATH}/platform/bootloader" + "../${COPIED_SDK_PATH}/platform/bootloader/api" + "../${COPIED_SDK_PATH}/platform/CMSIS/Core/Include" + "../${COPIED_SDK_PATH}/hardware/driver/configuration_over_swo/inc" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/include" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_cryptoacc_library/src" + "../${COPIED_SDK_PATH}/platform/driver/debug/inc" + "../${COPIED_SDK_PATH}/platform/service/device_init/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/dmadrv/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/common/inc" + "../${COPIED_SDK_PATH}/platform/emlib/inc" + "../${COPIED_SDK_PATH}/platform/emdrv/gpiointerrupt/inc" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/config" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/config/preset" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_mbedtls_support/inc" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/include" + "../${COPIED_SDK_PATH}/util/third_party/mbedtls/library" + "../${COPIED_SDK_PATH}/platform/service/mpu/inc" + "../${COPIED_SDK_PATH}/hardware/driver/mx25_flash_shutdown/inc/sl_mx25_flash_shutdown_usart" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp" + "../${COPIED_SDK_PATH}/app/bluetooth/common/ncp_evt_filter" + "../${COPIED_SDK_PATH}/platform/emdrv/nvm3/inc" + "../${COPIED_SDK_PATH}/platform/service/power_manager/inc" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_psa_driver/inc" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/common" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/ble" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/ieee802154" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/wmbus" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/zwave" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/chip/efr32/efr32xg2x" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/protocol/sidewalk" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_aox" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/pa-conversions/efr32xg22" + "../${COPIED_SDK_PATH}/platform/radio/rail_lib/plugin/rail_util_power_manager_init" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/inc" + "../${COPIED_SDK_PATH}/platform/security/sl_component/se_manager/src" + "../${COPIED_SDK_PATH}/util/silicon_labs/silabs_core/memory_manager" + "../${COPIED_SDK_PATH}/app/bluetooth/common/simple_com" + "../${COPIED_SDK_PATH}/platform/common/toolchain/inc" + "../${COPIED_SDK_PATH}/platform/service/system/inc" + "../${COPIED_SDK_PATH}/platform/service/sleeptimer/inc" + "../${COPIED_SDK_PATH}/platform/security/sl_component/sl_protocol_crypto/src" + "../${COPIED_SDK_PATH}/platform/emdrv/uartdrv/inc" + "../${COPIED_SDK_PATH}/platform/service/udelay/inc" +) + +target_compile_definitions(slc_locator_ncp PUBLIC + "EFR32BG22C224F512IM40=1" + "SL_APP_PROPERTIES=1" + "HARDWARE_BOARD_DEFAULT_RF_BAND_2400=1" + "HARDWARE_BOARD_SUPPORTS_1_RF_BAND=1" + "HARDWARE_BOARD_SUPPORTS_RF_BAND_2400=1" + "HFXO_FREQ=38400000" + "SL_BOARD_NAME=\"BRD4185A\"" + "SL_BOARD_REV=\"A01\"" + "SL_COMPONENT_CATALOG_PRESENT=1" + "MBEDTLS_CONFIG_FILE=" + "SL_BT_API_FULL=1" + "MBEDTLS_PSA_CRYPTO_CONFIG_FILE=" + "SL_RAIL_LIB_MULTIPROTOCOL_SUPPORT=0" + "SL_RAIL_UTIL_PA_CONFIG_HEADER=" + "SLI_RADIOAES_REQUIRES_MASKING=1" +) + +target_link_libraries(slc_locator_ncp PUBLIC + "-Wl,--start-group" + "gcc" + "c" + "m" + "nosys" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/bgcommon/lib/libbgcommon_efr32xg22_gcc_release.a" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg22_gcc_release.a" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/protocol/bluetooth/lib/libbluetooth_host_efr32xg22_gcc_release.a" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/platform/emdrv/nvm3/lib/libnvm3_CM33_gcc.a" + "${CMAKE_CURRENT_LIST_DIR}/../${COPIED_SDK_PATH}/platform/radio/rail_lib/autogen/librail_release/librail_efr32xg22_gcc_release.a" + "-Wl,--end-group" +) +target_compile_options(slc_locator_ncp PUBLIC + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + $<$:-Wall> + $<$:-Wextra> + $<$:-Os> + $<$:-fdata-sections> + $<$:-ffunction-sections> + $<$:-fomit-frame-pointer> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + $<$:-mcmse> + $<$:--specs=nano.specs> + $<$:-g> + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + $<$:-fno-rtti> + $<$:-fno-exceptions> + $<$:-Wall> + $<$:-Wextra> + $<$:-Os> + $<$:-fdata-sections> + $<$:-ffunction-sections> + $<$:-fomit-frame-pointer> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + $<$:-mcmse> + $<$:--specs=nano.specs> + $<$:-g> + $<$:-mcpu=cortex-m33> + $<$:-mthumb> + $<$:-mfpu=fpv5-sp-d16> + $<$:-mfloat-abi=hard> + "$<$:SHELL:-imacros sl_gcc_preinclude.h>" + "$<$:SHELL:-x assembler-with-cpp>" +) + +set(post_build_command ) +set_property(TARGET slc_locator_ncp PROPERTY C_STANDARD 99) +set_property(TARGET slc_locator_ncp PROPERTY CXX_STANDARD 11) +set_property(TARGET slc_locator_ncp PROPERTY CXX_EXTENSIONS OFF) + +target_link_options(slc_locator_ncp INTERFACE + -mcpu=cortex-m33 + -mthumb + -mfpu=fpv5-sp-d16 + -mfloat-abi=hard + -T${CMAKE_CURRENT_LIST_DIR}/../autogen/linkerfile.ld + --specs=nano.specs + -Xlinker -Map=$/locator_ncp.map + -Wl,--gc-sections + -Wl,--no-warn-rwx-segments +) + +# BEGIN_SIMPLICITY_STUDIO_METADATA=eJzsvQmz3DaWoPtXHIqOF7P43sxk7hq7OmxZrtE8q6SR5O7paHUwkCQyk75kksPlLq6o//4AcN8B8ICkXvRMtXwzkzznO9hxABz8/dXHTx/+19s3X/RPHz58efX61d+/vvr09refvrz7l7d68aevr15/fXV///XVP159n73z+cPvn968/Uxe++Gfnx37u0fsB5Z7+/Hrq9X98uur7/DNcE3rdiFf/P7l17vD11f//Jev/tfbD57v/oGN8DvyXw/74ctng/yXPJV8//UVe+y77344u7aJ/e9uyKE/G+7tbF2yX+nvlo3TXwNbd7Dj+i96/Nz9lSBEvkV+oo+9Xrx5vfhs2Rb59Td0ChYXK1yY+DHQ/8QnH+nIRbrtGih0fd1zjUX6983wFrHARZOGRSuMjyxbj0LyD3KfVTK1KWpHc561rX62UXDVg2sUmu7TTY8C5IdKk45DaQvy7dFZ6yY+o8hWh9iipAXJC5Bu+C9e6CoDalTRnqlEuGVg3bpZoW6ffUMdWI8yPkTTMI2xCCu62gGJCB0/hjr5OsS+SrxWTe1wJzvCoeuGV5VcTUpakCJSd03/URlNXX5H2rjIN+mToe/aStOnRVE7WmpG3NY9Gq6jkq9TG2fZupE+mPTjoxWzur6uJuQUXfTgSXHrVlfSkXakgXkhHy1Dv6AwNE9KE65DWQsi8jwdBQFW2L03qmhPscDG2AstR20T26ilHcpzn8iTDrqhi1quNkU8tZMMly0ypjb04OWmtPvsV8k7EnkecSDyzFdjaeeruG/vxTAdpLLzrInvbL+yPEYmmcSFVqC2BvRq7GjJkjmjhQOlrVmjGp4aOlIKduvjq5vYicaqmmVVPJPmcivJhIwyh+7U29GlWY5nY13x6K5RC19mX0dsiK+8DXEh2dFI2Yv6wU6hTewg07IzIhYZZwVMjSp4cfRAM7QRmDI9LWDYsS06/vRxMmJWlYMdijqcXCdshra6XqJRRT9OUk9GoKppSuF+WMR+1WYvK4pC94JvHW7WrPO5N8DwE62LqniOLhcwERspOBwPqduQtn6KEqVRTzsXGcMQlYjNq8MXD6tJpCYtLUyfvrzV37iO597wLQwU4NQVtKeOkT6nEznIdiErYiF5GtXwddcGEfkQqClLzXraufAjNeGKbqaNfTUpVVPBS6MkgWoqWmmsSh+gJ1KUpFKXMn7C0Ee34Oz6zrisjWp5vTFKc7tVVUeasrWZMXK8WVEP2Smy7NC6jUfYrpBrxmQFirK2rqOFx7ZuD2TgS765t01wkor0/rUCdeOIqgYeliBENwOr6LPb1LRQ3Rt+5oEkf4Lj1OTzjZgth7QcbeNlHyPTIZ2tc1nee7cLGDNTuqhJb0m5/LmVUooVJ4WmlEIrU3Tn3gUbD64emA/65n5zvyrlY+lBz0Yh7cAKT9Se+YUNrUpP1J4pGFl5sPbo218/rbWf/6pptQfrUt3Ir2lOnyzW7JcgxI6Oz/5aO100DbCZqaTkIk2wRZwqJbGZZYsYfNHEteg1JiStR+TN0JomsLo5lZLZmrnvboYdmRy5m+kzNG1z3q40y9ksARtuuURJ8BetdL0Znb2pI9COCMielErAjlPkI2eGlmRcYraExjxtibkEbDGcaIaWJFQidrCdY8iYY76U2ARsovu4ZmhOiiViCdFwO7tzNCYnE7HHQeTNwPAtkrGQPiIws2qAItZ5tj1HmxIsAUvwLFs3LNy6Yba/bY6mZGAC1pwD35hjW5BxCdhy8cjMeYa2ZFxCtlhzzJYUS9ASwjPLKlNiE7Dpep5nrcm4hGx5nqcpz6KWWNoca39CJWIHmuVYM8USscRAxhVyARjMlgxMwBqbjORmaEuKJWjJ8wnNcbRcRJOwiO5TsG6zdNQ0IYpYiNmG8jkalpOJ2DPTPtSW6EPtefahtngf6gRz7HoSKgE7PHOOHs6ESsQOf45NWUIlZoceWJcbsmdqT5FOwC4/nKWbM8USsCSYpX8mEPbPBC8B7L5pMFMyMAFr5trny/T40Vy7/Eimz5+rG1DGC/hkgu5DhTIlxeq3xEl2ls7HiCJR/2aC6g6EuZjRBMa9l6Dx64Yvm76qhl9xHPfWvbfFuhkNe1oqW9ND17FG6a9j4gWBWpT0VhOvtsX4Fo0ycC3zpVr76OKD1hOkX6a3jzB+b3zCXG8fYWBbwQRJmKnt5QtRGI0ySK8AZnoXfQ1Gre4HPkfdj8vQCLu0ErsI1KKktzflyQAR2Tbk0QtOxqJmvvI7PmKqVrx0hK5rG1dkVTsQrmLUcJyOBeIaMQUy/jQtcoJaZrX0xP1dZZuduo8v1qgtam5u0jLUQBpGIM15NDk0H+3FMHTPx1Y86JqSuk7CVcKkBnUn1w1tF5Fvugd25ZgI3e18+dkx6mhuRSV4w6LOIt50Ic/qNrh0cnp0e61FTX9n91E+5x0QZegyOXWRo5O+eOS0kLEjVNcKfjtIb+pj33d9wx2nlWlI9ZJ+/rIyEW1Jv0DJ9pAfjOO26yzYOYZErZwavsDRS+/jANOj6eNsa23ALgP0tvP9neOb95/ffe7uF9+4fv1YBvfpjVIaGk5gBezMuAV7zro1DZl9C2pC5muqQ/SMnOIXktC/k0IXGHqYwz9ZBEf8PIoLoAG4DMCVwpdxlrhaU/fStpZVZqUxWgxnvZ6Ktai/h9XxIh35zuNhItaSfnUj/AAbxLbwpbsdK0ar6J2h2/kJDt22SJr4VelNbzXO66v9CNqsNjgLnzfCoDRNnlK8jkWTiWziXwfsXVcgr6xXs7aohNdrTyyGHqhg44QbsmdoVTMkp2002hQNZzPK3FXKsBJh/8rWMzugOD9jcjAeG072g25Y3hU0EAigKWU+HovMq47sOTYKJTYeSzARQDQ8zrWYlfl4LXrALxd8m28e1Rn5LDMDNGejCng89lxRABmKDtCUlIzHCgeBBtQDtCIl47ICO4bjzdSOjI3XEm+UFSY5S7zGtacmSzzfcqzQmm3bXObjsci/zbTtSsB4bAhna0TIawWdDK0UxDKFnKytmiKgdlq0nrdBa1F7CtPVeVpUBhSbT8/SohKezHx6flY1Q/ba5iGT3gA3Q4MKZIJzz/nZUuPjsMjHl1FWTYVNScHko2VZvNGy0mUOHT+HhMpyb3NLEivzazeSCvizTHyeq21VRmEv3dztyih5PXXzNCiHE2sxR9wPLGdVI6qA/262huV8XNaMc7Je0hTO8/VlX99szSkzSvgjZ21ZmVPMJzljwwqIXDbRbVZzLoMZH7eXdba2pHRcljwBX+oDbctT/UagdmuYd3a2tqR0Ar7j+dqS8Qn4j2dtjdeyN77Thzxbi8qMvH7k2Zrj83snwlkbErZaInJmtWkbUnrHSBB5NIBc/yak2C3HESW9cIEJsQqTqTfb6T1pIlesza/8amftLzyFl13nZnl0E+1tlH2RQ+ysoHKZSS8q+RbysolT3hnGte0uB5p0RaqaKOlJuxyN0zVEG6Kpdzw1GVOj67Unu0XJcGZnTYWN3xYHGfM1JoHjtiaeFpJ/p9290WVTGVGgDl1mWOpqdByNf3yNFntxdvbU6Lg7s9kaVMUbtJQj1HvNqUtPzyDnaL05S3oFHdnzGn1RMwpc/a2H4czShgJXvw2kE5inEQWw/nbiilaztKIIxmOFtt3N1Y4CGo8l25U2V0sKaL2WXGZaxy8Cdbzc787Nkhqd6KhgfgZV8Xhz6BHZ0cRux44cyung3VtUvulbj7XgHE2P883z40yYfO9pbllpyMi98zR9IZYBfV8qmD0VPFGzks0I8zUsB+QyLcDpIW3dxB6+mfhmjBQhRsTADkyBuXN8obRDPZQzsq+Njyv/8peT/J9jO9IKKWgiu7DcQz69Cj6RNPlBo05zO4CHmz6Dc5eixoscxeyThTAyvynjU+Dhpk/trBW1nNd/2yvoAb+Q9p/8Ha/CfEtpUEeHSY559mkS6MOTg91UEEb+KJHTwFKiRM07AbPCQL89Out5WVpDU+FlLl8AH6DGxyqplh6QIekfBSE2xwzmxZN8dPJKPi66OJuKRkMN+VZM7WPlMJdtlpybXRlUY1VuK/1ck84ZWdoKKDqfPmPW9k3rS+o2rog4aE49MxM7MOXm1DOyr41vwJx6RtZ1Qg4YR52jmzH9kbtOY1txB5g9/Yk1bpM7jq0N82zjpKLAubX1XOaEo9SMIYuXX6LiGW/nb+hRaE0ZWa3DmAxN0KLJnUhdNgm5i4ovEsm+O2mkmC6zCnSCdk3s7ewySsCvWXxtNh6dLtukfDdVAVd0M21rUud8n41FREEL5+B76TJP2MtSeBeFIaa38My3gFYIeWcp6etuMGmAk6pljWwyNuknMmpycDhv68qU6jdmFkZAc0iV9JqrEpVgDR3xcnNxe4TuNS+/OfXMpMsqgQga9YHqPE1K0UTbmhk4sapmtfIJ5lbmoiXjgznZ18komn8zCPLVmX9C8b0qU6grAZk+MltX9lURRS2ctW3SVk0d2KzTKoGoZo0z33maVaCTmZfP0yj+KBxdU9552laHHDIvn6+NRUTpefk8zSvxDZiXz9O6CqGC7ei+G7qGm0Z7gNyTXpas+8i03KkPcFeg8v3PHbBcg8H0hdlsp2oxtIWTb9W9LHPaBS++jOQezDelyxzta+Ec1jBI3UHVeIil+gw+RfXILFKXQzNRevA0ytnoZCmV6Uy9pSUArqu9OB1s7ZaOUABLlib9TwlA5SVm/qNlVEP61koQfYadtukrR7ypmwnUDZJEDyM5JZiti4L2PLWbgHruuau8ZxrmKDcJcpqR4ogZgZ1oRjYkNGImXM/PI3WLXDakOGJG2GffmJMVGY+oGbPKC1sqL27kzxkZkeLIdX+8HX25IdEDbZyRdD0Fsp6/kUi4dZuXJTmQeBs3L0sKRDIt3XwMyXjEW7p55YgtmyOsgZmPHSmO7CC41gQ6XgQzHSKCxkwnoi6L3BdrVjkDoipG7PSocWlgJ69x1Ced3577xI4vNu+Mlcr5ksgxy0BJcXZgq0rTX99Lr8STzXmZkTOJGnNF9sgNMYc1OVSvOVblVY8tjYzk+m83qANLZTNULtuTpUEamKZKI1fTZmVGziRaNKe2owEHrNMIXoIQOzC9RSxrxGA6cZLFarONpmWI/oKbvOD5roEDGgF7vK2zHfx1HJWtTzHRRizsieXpUmQZQjbnpuav48BVVhtjL7QcqOFdLm/U8p5pzcp8iYMj47Pn2YDDD41RJ3JdBpSAhC0hZYe8OytbciRha07R3IzJiIRtmVUtKRNxDGfKr47aRFbNaIJR2rXlbcs0Zqe9Q4lDKM8mBa+CgHVmkYlt9ALTkcWyxqyesca0aub6+xuW+Fkd+c7jztEvpKf4PC12BUVlZUzSacTynBicVMJcv7qtBtgx/ceejQYOqj8jU/RjQWOUe2bVItbHik+uWlmBSVSMUFpK1tGykqsGa+/isDMAG0uw4ZqjuMniVIm5WapkmsES5eJZLjsw4kde76YbjgpRkjdevSipZdWjBqKslpQ1jVYsyiaz4OlVELBSQiO0AVQcKoaeb0TROKHn44SiWln6VNX3DBVYWLppKDnp9Au+YX+cTSNNaVlQz0M70synibRlntNCqZ/tkY7otLDmADzEdB/hVLCpbmWbhIqVNokcp9vW7WEcZ0DBZNqpdMOIla6J6EsA3KVrIthUt1zpsq1TX+kijzBFb96v12z+hUY1lKhfNCHAzfGRH8LMdBJJ45WERCErDAXlyoZxqY7RGtLUQNqWFpSrnBjXawRHQSjPfZzxvMqMl+V/UWstfSp4hjPKZqkSXKKzF80dJ+JRmc1tDmNUhTNPo+zMKbElOvvQ8ARZivmyFEcBqbrj02Vq+wAvnuGPX1szrf141iibcit0VvPBrgqcpY2fconOXjRkTsCWKO2Ds00HjQ6XKu2Fw6MtJZb5cOuCYRXRCcbP20RnH5rnj3Kmu4SW6OxD8yfoJXy+XmKsDRJltpZNEFW4YPwxScA1Ion384wPl6ntA5ymIeFuRqYZmnCPTJ5Md/wRZ6p00Ted4ppCNk+NRplBUpvYklBBa+/842p5o9OlSnnmbaOzNZ/7bUBjARvQSKsWZcKC6k5QulVkinQs6+1LSxQE2B8/HXO1fYCnaJQgAZUa3BgHoO4/GOtml3IZbL2vpTbOQQ69ZmF0woLePsTkEpPREQt6udxE42dyc1StJrhx1x0rkF2rjk0+rbEZE508Pq2x0VrCXLT4tEany9TyAU7VJde087ngxsbMtHK54Mans5ojDjW44MZmS3RyueBGZ0PN0XYaXXBjw6VKeV1wo/Ph9l3UDS64sfESnRxoUzV9ZdU8vsKxCROdPL7C0QepfL0vc9uNzpYo5fAVjo0WcA1LgwkyNODL0OAlMM7jj0NztZx+1gkAE7V8gJPNOurq+RzDY3Nyd27TjO+5h/fMRzs2Xaq01zHcv8+GhW3t3mfjI8vWm/an8Z1ZqKQZlTZGgjHDFil7ejAh1d6zmZC95pxHaWfaQVMCHtjYZ6izO5p1evJilOFMB3szEI8po10N1EHfdRtpDXjMS3I6mLvuwuHbeZjGdu4Ptn6yq+Fx2xKHPDlBuqSWLIj6RZGDOx51fU0NY3xYaqvthtPy/IUpEyCnWDRQySfHk3OKAs6UYM9OmQgMYFFmkTf9zyf0yFv82bNTms4AFmUWedMDy8RPyH7gtD59fMoESBkWNSLgSyvo4nF/y4nP/lprSb76g88X7bnx4abUpgB64GHDOo8z86h2RkT/gmEvMvhFM1nj1QetZXBIrqAodMlsqD9jiAWM1cc2RgFH/U5fSG3V6ImI9PUxDmdUkj+xdFExZNHLCVwPPDu6WBwJzqDoxYTE+uZCXo0IUHpjjO041TaFWbYoYSyauDhu9qi8NEEDyWXMoN7CQ3fEgGQ1uW2w0NjoNbeQXYnoId2I/MdJRuFJUpbNzdpAbdEOKtQOVsyngnJ1cfWerlJUjG+D660ZWfLM0KAKF5cttUSYS/Fsg+POoXiSPEOrmuCEy93cDOq0hbdBLrRCpWinjbfY9LS3NQFz6JDrVAsOarHuukHGDHpvCcsHT4F4PM71Lyrjc688aeJxKlcPDhP7+pzTRE3ikuxzUOdPKsxWoiT13VH6Ra50UdbfHyJsat4agpzvkcpojlbakD+qDzM0mRvHuStp78mc/NlxM6ZKylWMAsvxbDwhbwODuuPlJzvCoeuG1+6WhS8MF7GTI5wdeUpxic2MSlOYPphr7i8D9EG1Wd+FKN10kJd1/BjqBDjsbz9ibYUXJsiVgvZFIw9XXhXfGT/bum3ganPK76g/MiBlSteRAr7AQXGrRsTwRKDNHlZ+JK4xNXL9ixYa7q6EvuW7pyiYjxE5jogVY5fINnyhjrxg7kzwCzhgHXvf7KJxRVtuLHC68I0G+CI5pdLGXz3IV8bTfEtZ0hBP/WxwlxT0xfChB/ZOoY7MRzK7sALWHN/OltLDuPUUSqORt5H0nnU80TMYtxtm1zxMbUIjCY8J5gv5bBn6BYWheZrajFYaHlNszUDe1BZUIXjAPfTkz6g6tONwGYN9yzVJHhIJk1vSzCJqxlzypROJx6jg5WZMbUWFgQcbGQb2SNWygnBq+maUHiOY2SEyHpT71NvY6wQKAlDkXRFJFhqmVOm6bd3UNBhAnYGrkNUq1VTwjSRyw5EJ079OIj8cmcqMVhrh4chUFlQhBgxHpjKhHUd2ODKZJc0sA4cjc7BGLm+KQ4GprKgwSA5HJusqGlF4jEiaNNJDTgZfRuAeQ02X5E0MHNi2PTFzCaAX+II8axrSVDNHmk7GmKnmg0yOq1snAhYqvfiqB7kOIjZpmbS6tW1taUBWftKsi7b1iFkD6AiBoLpQW+NB8UwFTxeWL71uc45TZ82u9QbnemoDbcpC37VtMtyYhaOdJcXCtjNXuxDpgMNrjXcKNJU1I/Rtdk+IjV7UngvvTJ+s8NV5wPescZWz9jJ2dcmAagalq1akusHEazLpGfqcOiTD7p/Zc+PZTdQtiprFT8X3rSJekW8+IR93riK65KGBF1ZQK6gY1a6/1J4F05a5/Uqqe3sl9nTSaqkOjd8FXEVQ4qws61LYKlYsTZvBqna+3FE8GOtibR6FSe3VM33rsbatq7ZRj05ZIh8xN6JLnteDp2pcC64KWU9Lw1UZRj5LxNjMRbMlaZFPWOQ2IvFdu0tVjFBmus1NylLCArbdwHnWtvGNYnpwjULTferdztFWRsoP2XqD6HjPFNe4q+HtEctcg/a0wLWa1fJjy96qIedJ24qt+hwYrxo05UBSB4RzYBbHOmpnMiq/h1eL9BIeMaN6q3u1yp6wGdr1w6NNp7f9+g3xlYwmWUemGLeQ7TFXWMPY3vaCjYvEjEXCuaiB9GzsC68+RqZ1U7ma3QtdgugBTg8uTclbZODEZYel5sCcgfSBB2h65gJD35kY27rcHHxTOS7t5S1B9ACfbroTqRzx99LmBH2oZGa/2+jsWu2b0vuL+5nrKH3wJEsi5fHk+8HLGHzQjmvOgDmh4EbWffQ0D+yURAidFK5HFFhKoysJ2lBC6jHGsLwrmew8+Ujlmav+cUgZow9a9QkdjnFT22GcrpGeTg8hTIvdRCNmwgya9XaiHlOw4WWP68ietPdvYuHCn765qXL0YVN/ofdC9NqTFpsqRw+27bihSh9UL28G0APqEAGByqsLeklzgn7UqbuaAkIfrBeoPwzaz1ui4EBmsW6nJs4gOIDpbF7pGi8XcU7BgRz6yJi0CS5B9M3NkUl0qYx+2T81zxH6YB9mMcSoYPRDT92sFRB6YZ98K5y09BYQOP1K8ygUTTB9obnJO2R0p1+x7WGlt7v04jeg9J3jDmzdxKfoMgf8RhgOAwzbmtjRV6bgQHYspXcpcQGnDBy45NXVehYzk2YabhMe8MvkRbxMwtE8Gv6LF7ppAZvY/16D4fI/TboElhEIuMom580wuAvIPEqGELKOyJh8HtwZikCFnLxoN8LwGxBvCmAljXa3+s2le9tDy5iJTZ18/GYGthsmESmd+bSgDVQCJhEC8uJcTMlp+E3ASuPUieBjrrh1hRfOZ/M6E/YUhR/+ioK5wKco/PAOmkvblJDwo3voYS71NUXhhyczy5mwJyQCTeVcUj3gSXPjiulRzqRPV31Cs38s2owjOMCb2KNTQREe4M0DP4cRMGDiXS4NKGLwM1ieaSeSHmjPxJwGKoi5wyyNK/OJjVLnYRBuDl3cM0qdB3uKIjhKnQd8isIPPwdHaQuOgBHT7o2ok4jNEuaBnpAIzhLmwZ6iCMwS0M10nck3wbUTiU14ZmIC176b8jxjHuSBYPGpesRmYkWdStxPNxNTchrpk512ZDbdWcl5mqqWVkhpYJTWxEkMyT6jjmvySri+NUm7UONNOPqBg9tqFsAJBxfwZNtXmqg7NrI0nouZA3dO0g/NThbMAjoj6YeOLJue/T+7swAv0fTCG+Q/tj2PdqTI0g9uzKKcJBj9uFdE/qctZ8FcYOEE91xbZWw2QfSUhgMejxEPUQAfd8ZGrBswmdO3ht7h8a1CTzTlrSG3TnjrJ7w8FN5p9yqvpObHLtFwwLNI3sj8IwpC3cYXZLyk219mYU0nnpx5Z5/Moyc6hcJlYBFQ0EQ6RWKvx6LmZ2IDoISJQUQ94TictZkNkIKmBsEk3qdu0xIoQVOet8vj/GxJqXiNmVerIdBEFCKnzIO/DNRvQujrpn+axziswNILzk4BzIE6A+FAnoUjy+R0ZJnXWczlEoxeXGxMs5ZZ5U05eIDn0eplIBzIf0y1+lSH/qN99al+Zn4eyC3L881n5WeBnKP0Y0915rgG3X7uuIJ8mYe76sLprro+mCqvveDmTTn6gclcfzbDixJML7rtzKKzTjB6cZPnZ+RVqxP1GzHJPtAaeMsW0Brsdh60Wz5c7Lj+i36Kzmfs68gmymeB34zVa86NTP8D13jA02xBqppRwenHpzcfPUwS86yGnqP0YrvWLGpogtGL6+FZdO8JRj/uJOE5arQtETpqsEaw0uYBnJJwQc+i1c5AuJD3c0He8yGnsW7nQF1g4QafjT+vBsRvAguCOycTUqB+E1z7ZbVezqOeFlj6wX3rEYWY3W4YzGJYUifqNyINoDwH/AJLL7hvkX7WXO1msZmjBNOPPg8/YOs24mqslCuaxYbBlIMHWNvuZoKckPBAr2eCvOYF3s5jRJiT9EPPYyWYd+2XRZFCxnUWo5MSDB86264URFY4j6WwJiY+Q1z3wZpPJmQ0XPChRR0Vc4HPaXrh80s/ZsBegulHt5y5cGckvdDq73rlpm6997UBey5bYrg3wdAHdcOfRU9UZOEFn0VbUmThBA9msVxZZGk4NsZ5rS6ZK/UfpZp+AyrBXIjsM03icsS7ylBED7nf0MnGk/qhcyPayAQNS/adPeAXotHyld8GLmFhK6KcqcHLzb29TLvG2mpkEe4bOWhEbRE9ZBSbTt8KrRsNWuK5wdQj80KeNIOJmuX5ZLwTWo+zM6sMJmoWrYek9afuvYlHaA2m1eF4zYtPWczEnByGH3/q3RclfP4DTaWAONMFVGqwosYkbMwtxM9hML/2rRtQ1sxZNgz9kLLmzq557wbkNZO86k+6JlCwKGPhhZ/+7FCBXuSMUBLUZgbL1wUDhFaws7AqSTmciQ0lHm4jrD9nU6szFm740I+MuQxkchhe/DlNQIVnmo/IjmZDn8Nw+3akb0KvOYWC2F7dJgZ3321OniTPsPCVffebJ1s243hHft815/QWkXhbp+IQu0VbFwVzFmXeRQmoJ0xT/qziwiQO31CgpMtN5Yvqx9I2YmTdAHMyFbdo0oU8yPDvibRWTXA5nEhr1ETXjBx875hg2goSGzUa5IEQ6ydbp98G9ycUgululM1FEcAld5NoLgbvRRkDFZ0xxBPxyGeTnRTmF3xGkU2zglR2bJe+ObnIN98w74N1IkDhC/Uz+uZmudTQ6+U9/f8/Ldff0a9Wh23yFXmR9kbV9xwjukdk+IjP/lq7P100Lf6T/mVo2ua8XWmWs6Gvh65rG1dSJasyyNT0Pm6V7oPgnj52b5mYic3eub/convDDF+vlvfr+9W9ttRWy4O2IXJJY9cl0Xy4D0JkkH/pwf7XrFm81/drbbnfbFbLQg/zg4kDw7c8mpB/+WFR/JQ2XaXEZt/+sPB89w9shOzTq+9ffX73/uNv7968+/Jv+ucvv//y7oP+/sMvv//29vOr16/+/e+0jjruIyb16fUZ2QH+Pvbxhtbt7TPr3klX+vrf/yP/+rMb+Ub8bXqgnbYBOgoC7IcFP8z3pZ8JFTE3tHDQ+MgpTO6YOyMD68a572c9INlZfsZ0kOk/NkrHjm2d4mjV8X1qTQ/dHp01+ZkVy8YHSoGv6z+T3upERj+kiIRXHZmP1Nognhx3P8vzwI3kKMni/mdJIluuaRnUrW+0Pk6rHJu1+67d+lComy+k/hJZFxSG5qnjwUxrv91xBgRPrYlIGiHLoJdcWwTAMFuNKD6HnYjnsev5mUutffYNzgfbBdaPhDX+nIhreyoeEbX9+qxt9bONgqseXKPQdJ9uehSglmpIXiCtd9dP+DGkTXrYnnue+0R+TAZobQ/5yLLjayOR+9z/kIc4ninpZWnf8k5AY9uyqPStT9gYe3SPeasBEUlC2pbEafnYJit9LP+NtpOOa0Y2mVe8/vrqh6Qtfv3+Pfvyu2fHvgWvk29//Pr166trGHqvF4unp6e0hyDaFkGw+Bg/dI/ZLOUr7SjjBpi9Rua48ZeWyT5Hxn2s9z7AYeTdR8abGKrQb99fDIO945lOSchfvpK+gnUobEpHt54EpHcN6ZWf7MH7/0b/XSTPZV1MatZfWKIkeMRwKvcf3w/tW+gq8wXfFp++vNVph+re8C0+cPZ9/qNt3R5Ir0CGIfe2WfqFZCPpd8j4hvWNbF5debfYbtLBcttP9bdY85l2FbQw1l83UmKdACDbvdTFFBsSg+TTQ1AXgx+piCu6mXZ8mVnXzzUN5VrTKqVQZayg4fe0nDdbmv9Ko7EYuJpFgW1V2kI9+an/wdBHt4AdqGh/hXbL+eppj3zWh9cemlG1/YId6gPF33LFjeee32czze9b5mUN39OpRMPXQSyl6k0g8hdZPV3Eq2YLOkOJ+7OEQvQtMV2FTrPejQoSdMsC5CqsMPKKzBuJcpMBIUP33VMUhCKp1ScKgop1/x1QyfvMp5VPgQp/dlC0vBv3WuKvs+FM/pcAdPVNUZ15knW9fyU95hPy8YL1ndR1XJuHSLzJOiSu1wK/rlC/eJbbklJdrxe6wdbX4gWg8vxcd+laKZn5pEYYbtBH3y0nwaJy+HgaJgwpTOtcouVHTvImjQm2sMZmG9Mlw8Wb95/ffV68oY7kd8nShOEEVrzXwLJby2a/ANL/Sr9b2Mst+j67XctZryXedbxIR77zeJB4N/wzXdDve/kXNoItuRHf/vpprf38V03LxGX+Nx3htvIuK/FEqkRbDzRAZtib3YIyDSeClsgcUai/YArKpR4XaJHk8WSbJqRUB+mpS9Ttrdqiwj27rT+SFYnBiwCOxyewQs+kcYbOqotn+NCFivXd8CLJlBk8Sa9n+CSlnkxgkZYGnUcWAm9LrOwIJqBQm7QlCkQ+nxB0u5SKpc4n6wbendq4awwvLVVB+bfhy78TQBdWz4Qem3g+dJYTiWT+drkhG1oyGUVBJ2gA3ocGL0G+2AglVEUlilTUIhUDiCfTBU7P4ro9jGQn8b2DSCNFKCQSM9xBQmNH6iIIScZEXkFoz9yXS2gVtEfmyXVD20Umcw9Zi+JqSr6a32dtRQhdyGcRaw3X7E3+hnezTQCC8OV3B+ileyCD/trdKSK9dnCACcWrCwVl+JjeJsEzIyu9XNzCUfnYZ0jiOEwcTZ2+zbZ3QtexenuT8judLu6Wd3By4Rr/G4FttXqb214JURj1VpzUOe0XE40voZN3YjSxV0h3iGybN0ez7VCpaRfDIOUCJzuDOU2sSYk3PQx7mxTzC4fbrSYk9U3GCD3JkPg42ZaWVH22v6VPdenlRG3+co9m7Jj+Y7FcYZ4GNX4r3ijF3or/FHqNkiavcTHSWTVrtvzIC5nS0jd8ustCKEJZCBcJ3eDFAOgffHpLr6Qr/jKvXvAN+/0tWNOrV9Trimp5Lfafy7xMdyMIvGdbJ/p/7NU379dr5jBH3K/T/KzsvqPlWo83dwhkbiYoN17iZWY813vJ1geWbsnffKmWvkh1pi/2aqSpzKq6w9mHll7hcmtX3ujtpErPG1erbfG85YX+6Vz1+cIxZf7XuAYClVd8jsa08gJ/JS+8aJ56Z0ul5zncyOXnueZ4Da/IpDSXo7fyRr8bt/QCh5ey/DyHD7L0Ao8zsPwCn9Os9A6Hr6n6vEx+cLiLSs/7yDlHNzE0X7BA8riFSi8EYjWRw0dUfp7LA1R9JcS984SGV6RaCPHSJV7lORepS+/wOHryF+jmO5Emn/aMWa/F1TUmb1ANQs/Tpl7kBdpiizyPBYFw17aj5lfidlfsjdatL80v0HZX6Hna7oq8wNpdoRdw11an5ndouyvyPG1ARZ73BfOaNYYiLwRiZTVpqUReEU9U8fLKmo6eF3xkWu6CnQCgb+Ybvk/sOx/bGAU4+8y8ms9sGdcw0l/75iAVHXQAG7udF6m45/hX+oseeNiwzv2td1VqPEmnn+XfTI9XMd+pTuf6vT17h7AzRmHkDxLhnHs7wI63s1PuAu97dnSxbgsP3RnuLemwgiyjtPqZksh/BFISn1BJP8ZlTbD8CgiGIqb2xymtQDB0KhRlSnGWDh3VTiHJcfbIHMhZP9PUd+ZpqBUSGgVt9N3QNVx7cbJx/C35Q1aGhTE+LLXVdhP/mH+WlRhYJn5C9kP8U/pJVtqTc4qC+Hv2p6ycP5/QY5Ja7M8+OQEmtcUKX0rHjMi3WdyEdJ0h+wZeok4PmdCFDI5Zg4R040qElc/cgYpnUdBVCFZFzLnfR0Jy4dJTYMlXDuezhFjm9b8hm8ZVU5Eg9XBtChSws3hJZHJg8Ww3Dx3eKZDNNW6TkJveewMg1irK5R3oyshOy+Fg2enaa95c93Tz4hJLzTW89KQ9hRecNk7wkq8ci0MSYiuNhxoFWeMBLz5vPOBls0oOI7ZUEd0ArBLW5Oon5GMHh9Ia7Pykhs58Ff5LFjgtPZdEg06Sh+lcSIUW9gsNgEIGEUrlD+kdujQEzzxHh+QEn+yHpPniXCeUU2NedWTL9vZ9svsXrOQEY/I1nxdFXj5pzy74pi5xsGEGSKF46o9TlDwDxs99kp90jjUvOdkOChVRO9gxnN4dBvKypSdBPbLLQZHh5fvS04gewSGsZNrFntBmtapEO4KUvVYneoOz2ElygxhO4eDk65Uy7lw0LHX8LT3imc2yYNkbFKiwIB8VweJ7yDTlvQdtUpNxFixqaYylVDZ4YiSDNnDmwrhKiezCmEqB/HQ8BS56wJS8Qyobj8BLjcciSuRK+zs65BbGIOCyfWlPRIfQUIVUH1/kx2BpaLIg8ugh8UUWLjCPWkZvHifz+SGOYy49rnOzPHqO59a7QCejhgZJU2IK9aKSHoY0H3DcVKZhOPAyHWSAC70oAKUXg6sQqm13KsRuVxq82OxraLF5zF8VkvPrEgAlWyqg8yEtbVWHjBK7JZMKAio5iyepSi5pJZQIjsdZ5F/5wUuT+EJNARZbKHSwki0I0elmi0ROLrr8vXR94ZSvsz0gQ6pPm6JUcLJ64dChwRg6pBOM5GlyApL1tlkLAC+b3k/D/LSQArNdCKEfBSE2eQ9ki+igaa5aD9WRJ35yn9sgx1+nAhbQ10M+DVtMj5oMW/TiVjVsZapBTf7V0GWjbuEDNzA0ig9wet5DN7GHbya+GRyRHHhUlDtziKaoLDv5xgoDnR3iBRPbVgmUKCiWzEQZwsgcTdlAX5youkF+HVFlIBsw5NSqKO49aoeMPkV1Dd0a0qix3o6qEc6ze1pUNHQD0dYu96rwWeyfwnUCeSyK2g0DvY08lzCeKKGcojgONHNK4omJyCmKK9gWtywwrNtj/+mjJlFZdJHKzTpB7/kNTmn0/h0wYeyWHjBpcVZCyYIkY7nJKcrxoszT5XFXGPpWOuv3ek8mpm+VToFk7qril7z6+yXFEW+GyLMg0NKxZUmSVHI1SUqMhJNHw5vwF8MmgZVUo+tDj/TWEc7Uy69QyuNgpd9Iy7CGCcmiXmUyONOnSwZLaq5D6NzSPN+FFMdzhJhb2LB0syriuDORnVLOSlIcKoHn9FmnAJLOBg7oohzfGlZJVB4PLWPhTZUmARUWTlGRiW30kpoVf+K1I3k3wUjeFdNbepfdJrBzWGSnz81i8rN/6QUrNORgQC8IvH8mf/K+dbokR4XtOKxU+lnsjHeTXHbx5sK20yQ9hUbo2yzOFDGxvdXplJVSFq9rpNeLsI3dw4hTzAtJPX62zDhd/jU2WcmuMJURYts9W8O6XmaJO/j9riak6+1Ob2HXiz1hVNpetViiGwZpOnUas1HS8FhMywWcYlKSK9JMfBZOh/T9xhtLxaR0XT8qJimR0HEAovN1WzNQ3/7MTgEeevKBsqZ41SqUHACs+nWzHO/Xms6rS0r/wEYzvaup1Aq09Hxtb7fVSCkxtfSVkVKvUTJSmmuUjKRSlZAR0FIlpEQ1VImhcgCwilWi+X12lVoQx+zW6S2Si/gySZ0GpVokgWyziRuZxCPbdttG+5LCmisrExZeLd+kAa/Dl3RfQnY8IP3cfjCLX4RvtR1g4pcR3FYQMp58q3UWzC3oRNqrXVuQCn4p1qU9GjW/lMiyza5o39ySDORg2x6eVXQrzlARV0T+p7XdBiAox3PtthGugCTcN2Dll9W1nZ1fCl0bGiqDTQLutPu2WDcCkuI7d80/ItKb2viCjJfuPTfDRJ9916FrLLDC6aINkxxrgRceRKQPouH5VSgIgjaPjKTA5+3yCCQRJqvoBdQhc2INFhb6uum3xublltPl3hYQMriPNa+DG122F3G4jOEZjY0/PPQwOItx61XP/CI6Y+fwi+nYnMYt5DK8W70+mG3zY34ZdNs8RM2xncGFvnyZ/GBp5nAJ28Ei4mH8KTqf6a4hiBH8jXQ3gWs84HBwgt/oVPnhaagY1xqc1F5rfGZ+EW2B4QQkGMGqLZyhkJTB5YYK2Q8WkiwUQMkB6akzYR0xpPiFkanAar0cntzxcipzIQWDqxUdGUJY51ukWpir3eB5kz+8E6enlgBkaNsdgJS222BEZGyH13SAAXpA95l1XJEqJohNRIPICocPQJk8132wQMhCi/ZXQyWFVx+jjnP0/IIsB0BK9+oRtxiIWRmVQabng4tjImdwTsVyAulBMj1NMdwTRqUM81nkEtI5NI1rruMbOtlYetBTl5rMqumuZA9Z3XEb5cUHLzf39iI/Ti8IppkTWrd4j2wwpMFpEMoV0VNGcG9kHxGhRtf9LmKChkx3CoJ4DrhIybuF+DkMYDO7Khw806sKQDOfSPSlx1QFOcP8hgVBQ8f6BVEBTtIOQpb1J0h6B6EfGRCVDapl7TwK3iooDW+BbOty6zgz2SsgXrLqC4bUL4atWekd16fxinBc4e6wLkH3kbAzolkKSZlHFFitwdn7xd10J5JO12R5aUj7nonqOvzF+bb+5KO24DdCImRtkOqR8reLCwWyVhSF6JbjyedtWdLAGogNLz8z3B5ng1POsDKfuMd1z7Wl7bEdV9wvmb7smDILS4W3hxRSxwskh05FCVJrA0UBdIor3vUWJZCRSeud6b0CPGR2XCbb//rD4BpBRAzJRu9Bak9I9no6jpJsZ8ruTVkhfQE0BCR0HVUWFiObqLmYYd1ZXRAAkW21HwEWEjRgFFURM7AhKkhLZkG0RtGtCvAS9RsdnZNJW+c+t8Gyh3PT9ePhhBKr0A1SzufWOEHCYobTdBz4FxYznGboKKYoSn4oUpDSfmhfVMpwFraRYjiMzH6MBjE+upmuM2g0XZQWtF0oKiplOEvrvZ2CQgBIbDfsD1UxRCIAYxLjCICtM1oSl6ShAy/60OBBrM+C7ob6FdtDul22ChePTwZIYJvaIFAcq/UedK73yefVenADn0vquFGsV0q+mBiXFcsh5W5Bv2P+gcvy3rtdGn9Ztf6iZb84yEqPjcY/3zvm11f/QX9xzcjGX1+9/vrqB893/8BG+Pr9e/bld8+OfQteJ9/++PXr11fXMPReLxZPT0/38emAezIyJCmw+Bg/dI/pcJE++V2yyMFeC/0o/tIy2efIuI/13gc4jLz7LLTJZ/aRzPgQqXj6jQxuLobB3vRMpyTqL1+/+l+/3r777gfmDWU3gX7n0Xuq/Fjn/X+j/y6S535YVIz7C0uMBJKYT+X+4/u/0/Rx3EdMUuf1GdkBzh96+8y8rgH55d//I//6sxv5Rv7tLNLzDRuuJzI+ukH4M128/M90HZquJj6jyKallLxxCf4zQYcm6P9viujXV+kN4/eGnx/b8o0ZtbKRkb4/WSr/x6vvX31+9/7jb+/evPvyb/rnL7//8u6D/vGX959fvX71wz+TpPj69btkI8uPX1+t7pdfX5Fv8M1wad9Ivvr9y693h6+v/pmopXqJ4kQveeyGHPxjk91v4uyomk1Fk7fJMCR8+WyQ/5KXU2mvMgXkIfK/H86ubWI/1xJnce259GmLZHf2LB2rxDtv88UX8ispLjREOibZFSc7/ZJGE2DfsDIYJzCPgtLd0gr1OM/aVj/bZHKtB9coNN2nmx4FZEyjSieN1KgnLa8qHSV/l6qUq4WVGkkXi9WlThWpTTp+DHXyQ1g6BA6tqBQiQ4WOiJRi039UaYKLyAwgifChUE9qSVwxH0n3MVa+1OM2wBdtOn0MnlRWn67oEaC6kOfpKAiwuuazHKVJnZJyQLAxSlt23r4SPEJtu/2sstzRtlSRdNNBitu2vqAg4BUnGbtZOBilvKk3qiEs5hgDxnLVjcO9qmuMqHuerSiOlIpXtVW2kIxIlZpTmLiAz4hYldy9qlaDHmiGBq4GO/RKQ7akHHfjCucpsYN1BA1JYRuu6IdFPMmsfp3s9/yIwiv5GPkW1R9GpuW+Tmfdi3Q6msvMZuTZN9+pm2F/wQ7daoJh59iJT4V7kp211fex4sw7kudBPWOEO4Iki2GFs4lBOstNY05BayGdpm0ZbEc723kMbsmnL2/1N6kzP1CRUNlSgU7sQLZ7UaGkIfC5gtzAj9SMK7qZdrxzSK0CeAusSiOrJ/VVgS01VeyGAbazTZ3SWthkdQnJHFDqE5Gqyc9KKVZXHOpZAXy6se7Up9/d2yY8fepDUdUY5/Lp/m0DD2ouhwwdsl52krFDz9rvoPEDWxDnGz3UVtq/1sdrWQrSV18v3rxefI7j5f1Gw+VdrJCG7A/0P/HJRzpykZ4a47nGomDYomVxn6vk1Bb+xwRdSYFq44NqzaBt1aRacCrbN1qLUOW1dLd1y/Mtb/3CRhud77S8WUgsjtdbhLz99dNa+/mvmsYtoo2GLYcKSmluHeOw5yyS6+miaUnz21p60haNZFgejjxO1lKBykxdxKyLJkXNhVuMPyRte+SNYUCTJjELWuqEYOa/izsaiNzPbDE0bXPerjTL2SyTzhEwBRPiRas6gIKQydZR1r+rNCFVA4p+inzkjAGfKYLGD42R8GNFoPhGfMGVavhEDSx6eh/cKAYUlYGakd5WptqCVA8sPGFIYpYo589VwZrgICI7MHyLZLA/iiU1jbAGefGBVuVmJHpA4fE47RFW0B5hth1iFPpME6gB5yC5V1A1f6YIFP/iGf4oLWmmCBjfGiXxUz3g8GTWPE7xLykDNeN6HqkGZIqA8Z9Hon+Gh7e0USpvogYWHY0zhEv1wMJnERmV42eaQA2wyXhqDPxUDzj88wmNMu4s6lJiBF1htm7juCKadMIahbO7PpXbkquCNWGs7sxW0p3ZI3VntoruzAlG6RISNaDonjmKPy5RA4vuj9L4JGqg0fXAutwI7kgmFNWBmsJu/R3BhlQPKHwwjgciUOCBCF6CfPemWvpME6gBo/W4avrbaLQON1LT447mwVLjwHoy3VFKf6oHAt5JtgMq5C6qgFh+rq5qKyNv0qR09Zn7cY4HeR6pn/qlkRVk9mpYN0Ngj0Zt527oOpZcl53chm7F10zngnjzqWFfaXKx5ECUVIw8SHxyDiJVMkHyMHmMvIEwuSB5mIBeOwzAkskZgBKiMJIbMVdYMkH9MPztRLWeBv6gehoXJJntPomxyf3TuaABKU/GgMi2AwCcoqihpRKAJpWjsiCErmsbV2TxtPYAZaktzeLAEUMSLTMkTb5cJHdWCvbSQzq/7oTQfXyxhjWzeXokDUtNsuAQpi3P4Bkh4C6GoXs+TnaGg0LWRYMXMEXjupPrhrZLQ13LjO3Kh5Flu4+yFKkan5uxKEtb1IWrbDuRZ8mmQukk6vBEsBY1gZL9V/mIbCHGJChgUbAkaPGUXyHLZSp6hbRd8oA0ZSHqDVeyKWpIy5JAiMyGAisJBCmFHvIDSX9cZyHM5YJWFnDOguABoD6md6ZLb5NsICxLBGlpZXq1N+8/v/ss06G9ofHlpIe9cmcBKhljOIEV3/Fl2ZJFnJm/oLZkDqu61EHDqVhc4eZFOMaC0EGI4Z/pnWNQfGWJAOl3kVyMak27i8yqUxWN3XvgrNdgaEWBg9AcL9KR7zweoNBKAr+VIXuADWJl+CLTvhUDCQyY3tv5qQM9CeQ89BCduMugsYic0Ga1wVkwKZlRapq+i2JiLZpsZn6FukaAlQwidL0a14iSPgATYkX0REEWxH0EQ5q1gplDo/jEVxeOZktJJcQi2TM7LDcCf64JBvtkPxTuLRqBvqwQxgjzqiN7lDpdUgYDj4kKwvA4WvkpK4Qz4gG/XPBtxJyoK4UyxmRXXIxnR0EfjAnptUcj0KeqYMAdFI4FnqoCAseO4XhjoWfK4OA9uXUhOXhPaMWoG75w+fU4BpQVwhjh38ZqbRJNMNjheNwhHDidXqwqQRaVz2dKCoGMWI9swxrehMI0byQjyhqhJ5bjGFHSp2ZiOYIhzVoBzPGQya6/GsGGgirwGdkI+DWFIEb4+CK3RihMn2qaIkyRBRemKF1E0PFzSCym9+OoTj8rcyU3qgZ175j4PJo5VaUK/FSjm5KphfNVjWRDrg26dRyyR1bOkEbdoB6s8WzJFQIZIHkqW5Ie7Gx22R82ngVlpUqccOMaU1YM7Ygb05aCTiAz6B6iUQtXphDQmzgefqoOCP5Jlz0mKYmfKQR0iY6Hn6oDdYuOiJ8pBHWNjmuAJ7E5u82AgrdyPCPKSuFcpONZ4EPO6cNx2UMpeFWnJ9NEqW94Sa9hCCKPBvgaut2l8xZVsSwr3BFB0hjbNGK+7K681jysmJ9cu7PoUg5RHAviXedmeXR/6U1uQ98Q0yq6gSyjl1JMkmNNiqdwSgHt+cqNhV3eqaZgeoos1wXmr6GNI/iunCb+mjoAE7IbagxHvQEVZZD4DjJG5E+0ARoQTwfJv8C7ErrMKOsErQ+XMYpTTR1I267n92qP0iSV1QF2T+PZUNU30SIJcH+ktEdPT8jmugBynnQLOrIVD7EoeUERRLNhOONgFxRBYJNeYCTugiaIBuKKVuOAFzXBgGvb3WjoBV0w8NuVNhp8QRcA/GWsKnoBraLl7nWMBr2sDr43H8GGqj64fHhEdgTtHuzIh1zd3B1UlNb0rUeuSA7dwqCm5XEpgN93mZtaGjwC7rpMRcZaildhqjWhog/ekmQzwIi25BqBrAlwekZYN7GHbya+GbJxQ0Rs6tALOu+Nr911qK9RpUltCoFyKReflINRmoFWreBWsXuYPeTTm6YTXfAHWTot7CAYw1oVJ/FE7YU9nNenDWFkTmtvSjCGteDeUFFj4Rykvaoe8Atp08nf8XLIpGbXWcZKgZE6HgmWMVKAhZwPI18utBWY8SUMuGmTFQb67dFZKzaupuvbcuNWr7UOkJSgxoxIj42QTI+CEJuDgkPx5AidxZKPiy7FMgWstXpNZmGfcjAr2WZF5eZkWqSqv0wVas3S+jxOpfGtGuHnwWfMGllgR1K3PUWdiufCqq3q0KtqLqzSpDaFSufCqvOoVavS0dQ5uhkKzoR12teqX6mlCs5XcVspechqbK80TurTfFzSes4EORTOhGaR2ktqYMbxuUw9Ci3QcFod/JkucCPgPUhdZgD7ioqiiW7fhY1J0mVJQR24KdA+zC47QL2VRcHq3Dld5ihy3FRVXNHNtC1YX3qfWUWd4EYpcbx0WaTAxVKQjsIQ0xtbRix5FZVwc4tUgRvABtmoGtOoTI0Z+omMoBwcjmxQWe235RXrGEIpScL02qOSGvB6OuRGaHETgC+DLssGn4l0GQIa36E+0BzJilQXfCOjwrNUtaRVIXieZG5VMgwYrYjVlMLnkorQUZ25BBw1qjK3uWLjQUFUr65MquqEN2pccxQaAh4hq9MQ0PBYjRPPkSwpqFMzzx3JDsgYEV0zzpHMqWtVO88d0ayiToXz3JEsKilUOs8dyaCKynn7vm16U1joGm4aAGE2PnCrSqb7iOQP+PnjipZ8c3CHdqCRXipS3Z6mFttaFEMtYJe1Ai8+8WUX4Hi8KbFGMalF8TwaFEXXBnGfDam/iU8Rf6gSJZcBMwQ9eJI7ipwsqTIhqfu0JBH86qeWpIC4DjgHl6kqpaRIetiSxG/nFiz/0TJ4Ato2lGf6JjtkI1+qYbIyA9EN2zUeZD0sLCkWBXF51jZpGHQJW0WqaZhyl9hxUqfyIZmxE6lETsRDEl/Pz7K9PRdyKh+S2T77hlLoTAEstdqUthWk9I38qZI5lT9WNwkzYii3IXqgSc4A6kmUDSEaVQC3VIrBcw3Q7ZVi8IIK+FZLIXemALrVUpzetpr0Zm2LQuxU/hTj2pbmzfGiaWdTBGBQkpP3s2B4sahvaQJFkYd0ltT6NPSSJzTSG6Fsee4TOzoptutWSSkroQwqbyVJ2UmzqvihrVJJYDwpVkydK4FlvyJ7aGfAAZ9rGUhvVQR7bG1Jdpmknb9Dz7fUfpULPlwipVFvquJV1Cu11LkS2JIJjt0gf0Z9SfAShNiZthOJGYYE4IlTP5aT7Z0tSx1awhNxnu8aOKCBsAds/u3Arcv/lpqtYpoPqUdJ0qSrw2WpanISHLcuf07V3sbYCy1n6vFjzjGsKmVisupUEjy4yGTS2IjID41h89ku3pIGYHBSJolktei5DmD4U6ScPVMBjK62hJdVDB4OlQUPaxir1E3Sv6kOLm9WgNIl7TRKggHzEJazKnlGXVpkYhu9TNudxQyDKnosIq3kucChLVIsSUe+87hz9AvpXj4DU1Zkf0vVOknmIVUlSZGkOucCv5W9Ftgx/UepnRYO4ntTVb2LAaQqHTN6EQtghTmX9c0U3wRZpuyWzKclN5c1o4Y9DhE04S4ebLimnKcyTuDYAJbAmagZpe/Fs1x2csmPvAGbpQbX4xLHgOpcksNqdU3yN1O5y+TyRbCcJiyAflXyjEokDSw4YX2n6ulZXhRJ3mQQpzkVw5K6Km/QUI4FXQSCAoHRL/iGfcnNSU0pVZA3HE52BtsEJjhf7YTSz7bs6bQWtFzicEC6ixSMLRX2zewsK9bXJEChzpJBzoVTSBPaGXVLhyxcULAliUCFC4otFTZW4bKt07DCRQQw8Dfv12s2VUbDUoLIWzTJnFF3HiE/nHaKmBAMKHWJBFbwCtK+mYFkyizfqKcpQNv1grRvx7/BV3UHFb7qxNEZsGjBgFl5K4rhTu4aieHIbQgscSRCBlC4kjHAyhiuWGCvOod5ktv4VcJIhMhTYIg8wUPzBEcBqc8AIJkceZaLZ/gA9SUTM4TEktsjXgGxxE4f1jgsDSA9EiEDKJAJgZFIkeewTQcN50ilDODA8mu6ZRQsvHJbp3ECgMxJhMhTeL5ccIESRSJEnsKHaFP9oW2q9BaRMobgNpA6RwDQ2wYD+9p4QxQARyZHngWo1gLUWaBOF6DPfTJdgMFQKqWfQ34mKTINahuLy82AqKFsAacgZsAo+Gp5w0FSKcPmBMMxxI5CN1KwkB5I1ttehinIkmSi+1xAUqcsSD6FUBBgHyB1cjnyLKdILoJBpQ4JBSlomkdK31RTLi/C98809PXIoTdSDIcpCJKnSe5sGU5TEDRwvg+QS2IBzpo5Bq5UVXhk1qma/RCDcRIhw/wQgykEQ2K0+iGGg2RyhrKAdUs1cUM9JIOJMjEDPSQAIJZYUKJGD8lgjETIQA/JcAwkFgqnxUMymCOVMtxDMhwFi283bvSQDCZJhAyiAGtSyrKGeW0GwyRChnltho+fhvZAzN8yHCORMshrM5giGDhiCiByJBiaI8FLYJwBhki5nMF+LAiWRM5QFrgRbV3eUB/bYCSAVh9oQAkwnmTescEgqRQQH5vMKjoLqiqziu4jy9ZFNs8M3QbemBGUQioXmN2L1Ih0R3cqbtCeKCbUOcu1K+1cqcjhbLHTSGc3Fut0/7rceKEDtVnDcHL5O3M6YGWv5WzgG3SNTAeizG0xQ3copWGYh0ZAP9k88V750pfIgkja1LQFkbcoClYaS7olfSyM8WGprbYbsGTKRYKmVi520aBmirR7ck5RAJZsTBpoijGJi7LwKdLpzyf0CFcLmTTQdGISF2XhU6RTYJn4CdkPYEmVCgRNrVTooqZiHrHwWxKXrm4O7Uzw2V9rkrnTJOr5oj1LiWvPcmqmHnjYsM6S87jqQIAIXDDaRca8aFYldcWDVM0Zt+igKHTJTHZo6SGpydLNxzZGAUiDmIpMc0aj2/VTBVJHASq5n5i+qLAvehXPui3w7OhiDc5PlgD0UkgduXLVuB45oCRTahNNtdlmpi5KchdNikDuZ6mIheh2uPgn6rA9dGe4t2RhW3Yk2NIxyPUz/fniId2I/EeYWWKSO+V0yPoJbdGuebS+ojFFKEoOHLdigLWtkh5t2gCqXJamY9hQUQSEX0sZZeWyTRtgPsTunDEMadKmoEApt0EaH6YJLzRPpXCwQjf9dKRnuQWsqVDSxdfVLDgwoAcADVpUjAckjJ3NVHXoqkr3j7VpjNc9AZZfIqkf0SUpL780Q0ATH/6w5ZlcjkjJI2+l3m9qxiKXsigLHBpCDRyvJnMsZz3VKhb9tTW/hA9UNKVHHGKwJG5QZuWSBmZUFQygFAWW49kYEq9B6LdyKvtkRzh03fAq02gNDQx2M8QdjNXcJDJEC39mc5qdRMYiFzW0fFExgsWqi2jEVomo0/FjqBOTwqFNU0xfEAeRSwVxi0YFAHlXlAiQjd3IAM1ZWaLEuQwpcplzG0PDCsVNLFE8PIpwJkr8FGBjcuUCFy3igXotKtN3T1GgkDmXDwc9uEC20QKOCAq2q6ItyJ/dCEFsbsS13QR2uHG6DB1wQASPSikAlpDybS1p8UmFp1Gl+pXNKMzUgEA99JzmKdSR+UgmYlbA+pfb2RI7FV1PzjTmfZvoAcdTT/Qw0e2G2eUi4LSNoofRmi/ks2XoFxSG5gmcuFX8MGpbM5AHDluVOozRQ0++yqLbLn8gN/Yt1yR5RmTDQzcLhyNWltqdOobxBy83Axy4InQYITIM7JEKYgUhfBPcKFual9keIuNBfF2gDbMucqbBNPJugqQiDWYqtjhdtz8NllAXOrA81SoRGGejaOgeHTJV66JV9OhgxK3iAXt0MNiqVCU9Ohhtu3z4Hh0Oulm4sh5dCTh0ihc7XzDgilDwHh2uCW6UPYw3aW5I9wPHWZYJMOIATMgmoYMIbRsaryRxANsFeRYQVCpqUErB4WSyhvIkEQWsk2VbodiFWD10dclQI2/YWiC64aSRTvzgYReY8InDRiaZuFBdVELhoeRnKacLy5cBTtfBRxLF3baN2UD9qWk60gYt9F3bJmMBNY5clmoL285cuUKqJznZKBzjvr20G6Fvs1s1bPQiGIugMzGz4l9X8M3sUAMo5V0l++qS0ZiKMl0ryN2aVDZKpD+Td52Q0nP/zCQMSAzy/qIoSn1ECLH1uSvyzSfkdx+aqjf2Lnlt5EsaaCpStcJuvNTEBXs9c+GVZA3osZmcpK0WDkbfxVaVOVsfY5lXpBGvmJ+22lVxQ3NHdPjZhcU/7lS0Fc/0rUeuXVcN+/Do5CzyEXMvukSKHjzxRIkBqMxtGWS4QrHos5yJU2HRbFJajxLhY+08grjhmCLLlNTu9EhKcCJ8RnsBnGdtG99ZpgfXKDTdpwHbNmTKY1WErTcgxduzgAa9DfKH1IAGcWnxb7Wk5UeJrVzjHi+WqWDzyOABVbopg5P6LJzB39L0B3CQ23tqpvZGeLVIX++RpHyR6WmdEzZDm//gcnNIA59Hd0dZJJ0BmRDfQnbcQKSNYecWCkmwSOxZJFiLmuRBWyvDq4+Rad2E9hD0MpakDuJLj8yB4hWFgtCxU3lKEDPJwzgDpACxIHTYSSTbutwcfBOaJ/TilaQO4jvddCcSmlv1wuUih5GhAO82Oruj/CZ2i3M/Yl32MFaSHZH4ZQf9nGW5EIyOa6pATMQCEeo+elJEmYoGJCXl6BEFlliQM0Hkko5B7IblXcn07clHQufE+vvustxhjMKniDiGFqIHhlrICiMUnR6sAKZsEg9JrKI5bVcxiBwbXiZMRzZsF9okHIBWQUNQFTyMkjo/vRfdc23YMlAVPIjSdtxQyF/Vi5dJHMTlEPGB0O0avWC5yKFk4C16QeYwNi+QOBfaj1cSO5iQRZ8GB8ykDuajs06xpWwuwFzsYMLQRwZs01eSOmyWiEzbNYQCq/ZPEnOZw9ge1HTLFblDGcHbl4LMgWxPvhXClryCTBDvhKIcbpI+LC49kUhGQ/oV2x4Wuxmol7ZB9rCj04Gtm/gUXZTQNkofzGvYFrQzqCx2MKFjiV2VxcWXCh1MRwSv1mrG2c3igYgf8At88SyLHtxOGf6LF7ppWYJ2p9akA3gxYBcfMpFg/hV4vEwuUG4rymZAQh2REaqq0pjKBqs78MWyUToUb7wWzAoV7eL0m0u3wYeWocqEToVQVgW2GyYRJB2FTVmDGjALQtcnYpWR5+KhiLFYIDQRWgwQGK0g7nw2r6pQU9lQrFcUKGNNZUOxOkhZq5GIhiL10IOyqpXKhmIlkyZVqIlosDZLXXM1PEWNK6ZHHJN+VPh8Yv/orFk+6BgI2nNQkQ08BlJEm0sH44VetW+QDcmqwpferkLRSFMVfYMa9WPlcWwpK4Qctynix2LhY/tI2dhKEWoqG3Tcpog1lQ3FqsSZ1iIfjBl4ebguGnJUrIg0EQ06KlaEmsoGGxWjm+k68Ptv2lVAjudVEQPsIyiPuhWBBqBloeqGUQVdVwPt7VFFnosf8ciaHZndp385xIied+hIbiQWkKM1fRPLss9owPVoFULfgmkaaoiJYAjG4LZSw5gIBmKE2xDQBCq5NaCRNt6KrgQ1Fw3BybYjq+HMRENwRpZNT1OfXTWsJfEAvAb5j20rqvlF4RCshpoCkMiFILwi8j9tqQazIByM1XNtoThbgrSpeBBeLBV6ToAYS4Wh62KG80XWaCUdkc2cUNPEGqXUJLGZkQVwu9Puhe4J5ictiQfhZYGEkflHFIS6jS/IeEm3J6gxoFOfKovOPpmlQu1K57KpqBHcKjpvYQpiZSNY1aBRiVVBRL24OBzXsgat4NYFAYwXptuaRAs4/fN2eRwBP1UDx6+40oPW8MKxfkXIZQ0Q1KGvm/5J0VinIByAlW1UVgKaSQahVOODMcF8MOZVzQwnkQtAiA2gVbAqYioYhlFR05RJBqH8A2zJo875h9ySRwspzBptnVJigbaZMD79qYYylw1BCnbMr8Ypd9SvkfKiyNNyAfO0XB9MoQj53IipYAhGMvlV14WXpAPQ2o6a3jGRC0CYSFTpA6qrgOCG2TtXY5XYNtfCt1UEuIUixI7rv+in6HzGvo5s21XjrmrRA2DBjUyBA9d4wEA7R6rkFfkQxPRakweYODg12lw2AKlrqalgiVwAQg+r6U8TuRCEMGfTa4ASx9Nb+IxgpSliTEUDcappTTPJQJR7ZZR7KMo0lqAS0IJwQFZ1PqaaBkhqFmxQKXWqAYLatV9W66WialYQDsHqW48oxOyusEBN119XAcGdRqBUQlwQDsDqW6QfNFc7NcvuJekQtIp8U1LbLxsJgytSs8sqFQzDqG13qigT0TCca1WUazjGraKxVS4aglPROh/cyh6LhYKMq5oRQEk6FC3bRhJEVqhocaRJCRS76z5YCpM6Ew/EG1p0fq6MNxcPwJuHGVeBW5IOQWs5ylAz0QCcEpcgcoMKXYjYS6psVwLgPgQqSjd8NZ1CUTgcq5raXxQOxhqoWaYqChc8wAJyzSOZe0Cc51CwkY+QLWD36yUH7OMNQCiiZ2Jv6GRjWHdpzt2mCtyWZIvQA34hTJYvfuGthFGtOlVZF7zc3NsL8Kpcq11FbfM9B0Hx4c9AxOlB5YbWjd0U7QbgA+JCyjdrgrfE88ngJbQe1VtS1gRvCa11pBmnji7o8VODNXVtcBbF+8xVWZBLhyQGX24vEUOetyhFrgAMVNIAXlOigP8W4ucwGKFF6taozrJx6nW/VnUWqm+DuzXCWUaE+7Cu64IRmXA4XgXnHArAsOcZkjAVKhY8C8zAa55ZOIWkCKrCLikA5Lb+VFcpM+GAvKEfGcpGDrl0OGKl0zIF869HZEfqgHPpSv0eo11WmqZk9Spay7ZIX6Tb6MQTOaPpffImiwMnf9FospEvjpfCc6t4R+Gg8ePjrYCi8SWLSbEo2LUo4y1KGgZFdckliRZicVaBgjz1BbptX1d2mSKr985q+sbrxZvXi89xev1Gk+tihQsTPwb6n/jkIx25SCcJhELX1z3XWKR/3wxvkeqoplw1iIjXG854KEmiggOkpyhBgDSUpeq2CYxMB987plqYgpoeIIM8GmL9ZOv0++D+hELGccE37JNfKB3pU3Ejr6Ds4KpMtPcyQHTSy31E4RUsBzjVpA2Y57t/YCNcXLDxQEYx5oO+ud/cr7KNZ4tf8KNl4BLN218/rbWf/6ppi3dpoCgQnaQkJxc9xm0q+ayjIMD0DnZlCuh2QB860RIl7GZ6GMm+G7qGay9OZBAUum54XZwuY2hRbEIQIuNhYduAeq7IN58Q6XlPLvkL0oA0d08E3nbpxWvqJJOyaUFLf/P+87vPizd0VAJbcbMkj+eZyRH0yGf+Id2l7pXgyVWRFQE2yBtk4sA2nDiee8O3kH1gkwZkGHoaUs8CNVmGIPDB7U8SnB3zVpO+Pmv+TdYL6NaNdEQK1GDH9B8XpoPof5TJh28vc/kkj9WBXzzLZXfE+ZGnJP1bC3F6oC+IPM/1w6RmT6yeCMQBhhoUiFPAZUCf/0O1mqRlUtVqOF6komNPGj3nWdvqZxsFVz24RqHpPrG6zXKs/pMeBQh0IJkPY5J2hYy+FYvX8WNI5x0h/Mgjbmhuj85aZTfiuU9kLJD6QsZsyOiZiaTcKFDrI/Ic+deyaWef5JhiJYXxNPigpk2VhTE+LLXVdjOWxifnFAVjKfvzCT2qTkvjankLfPbXWvzv80V7Hsu+wDLxE7IfVOuzo4t1iz/TrkdHrnITY5UeuiNDhGQrr/Ji06Qzy1Rt7EQuta1spD5S44onaNBznXCTKhE/vsqOPqCXFrBLfBS5pYg227giS8lUKO3qg5cgxI5SDTbGHnPfjTuSSFrTZIKvYlYfD8YiMl5VNB9Ok5AIsNFLiwYHGb77Cz7TpoQ0bV8zH3jm/32jaZtftyvt3fvNUkTA59/0nz5+1D9++vDx7acv795+Fnn5f/706Zd//enTW/3rd+Qv/Ze3v/70+29f9E+/6j//9LdfdG2zFGKpiPv8+8ePHz59+ayvUokQwqThfv0/H/RfP73932w9ga2Ak2/XByJmKSaJJHnM9Lef3r8tSft//m/khv/j50+/bFaH7U/xJynJn97+S4Pgn5YrKZlvPrz/+OFvb//2RX/z05effvvwV1Jc3n4mn0XkvP/57S9ffvtMhP3t13d/1X9991vFdjv8H4UJfrqZ8i+i9n8h5fmd/uvvv/0mQ/fx80/6m0//9vHLh07Q0i1vcqCffnr3m/7bu5/196TKvCP178uHNx9+S8tpSaNo6WKif/9C/vn4U2rG/3z70y9vPzWleGHYgmSteUd0/vLuw09vSf16+79/f0eKh/7+p8//77u//bVBUOLq+DVezYNZaxNZpaFjNvJ/6Wc9GyfqF8PQfWxjFOB7NCfybHEmZU9/Y5slfde2yUBz9nbU4K9uEM4Nu8ENk3DTv/U379drCjo9YGUWQo8qXfAtdiSS75KEzD7LJnMWSLFpYNL4KPeDTaPqxgdvLhnDNjxMh88fvKQ1oh/esVX/7Nv7yLjPhtis8XPZ912P3RteVGonyZwjxM93zno9FsG5QnD2Hrd3QZNLU41620Whjk5WCYL6fCUJ6KCd5KffDZA+de/5OHO6N++Noi/+ZgVhpjiFJP0ZLd25hMb9OItcsYw5dCOEc+q1J3ts9gax3TE91sTPJP/5bPiWF5aKxz+lM528HaJP0tbv3h6p4Jyjm8HWucmMMYzdTgXCeDPQGBwmChE4g0Am3dCNDExprzBVCriOFepnn7TepD9j66UTgdzogQwDe1MWB8Lgh6E1QUFI98K9Rx7rUKex36C3Ld9M1n8U+9XjcST9z88tBP/9v69W4zA8If9m3S7BPbLtibIhQ2AnlKaG8LCJbqFllAc6LbszlWaIj3UWcTyYCoU+4Vh/si1aJQZ69IYbwUEPmPW2yHfu6QQlRP4Fh1WGlsdqo947h3zzo8TYdyBHeI2cU4Uk+W4cgOrg+84h3/yYDMHvzNVuNJDGYTjBod/fke9/FBqS19Tk7WMvUf5oW2N+F4TmjyIteocOzxMAonv/29r3GEqokQfGaur678439y7+djKoljERQyv+Nm7ZSttkvdpJ3v0r+2b85FJPJJU+9R787l+T7yZMI6VUIunU2qHefQAp06IppJpHJG3a56Z3Z/rbXf7b+Ak1KpxIqnV7Fu7O6e+Tpt4kkEL1stsrcHemD9yxB+6yByaortNgiqTk/DyKgOn/DRjX6gJuf/JbMKvZtdTyWLsveJgLeCAVc37WXJ93ZPKGjeBH+us9+3MsntQHp8efdQd5ZbL/k8j7+t3de+T9+E//5cPvXz7+/kX/5d2n/7r4p//y8dOH//X2zRe6WeS/3rOXObnjLUj3FiktiW++ipwcJXK98qiErRSeLppmaNrmvF1pltO4qUiwIaglmBUYwjXhzjGcJr9M73sc+d8ro+m0jXClI8lxH+9mZFkTWGstTiYzvI+3NJosLiBbkLu/3KL7QvN4QskZ8UI6FgRWno4fuqcJfe+GV+zbxKxvK8lbw0h0vHN2cBCQdLyz8e0SXn9sKrtjZBudbotkXPH5/8w6uKyzkH+PnzzWILU1Ru/e0onqh9TvIZxezeksx0o56RfJdoS0SDxu6f6PKnjHC0kZQqbJNmwh+/cA+9ObyNufSnUP/2p/f3d3MTqmOHwibu4d9Wvc+U/PRNbFwbewacQgbzzd+qSge+QZ5qgc/kpBP5MPmci7Jyu83rFJwzSdbTJu62mxRcUZlm9ENvJN7OGbiW/Gi/wK3HysupFSbNYG22JrZ3I9a3OjMUTWN5JF+bNpA2+bZxtdJJp0pS3doKzgHC4VU2GiNPghPeKRffPdD//87NhUR3wQjWhZ3S+ZNaRMufSyEPLV719+vTt8ffXPuaB0kpbteoyMe8c1I9LuBjiMvPs3bLvyx/ixj6Tm/czSr7BZ9J7t0iQSiCwP++HLZ4P890d6eVsyAaya5BExLBs+h9j7CzGm9HkCI018RpEdfsZhyJbnhaxbqOcblvwjAEZGgjisYFTjECY+nbYKVg7NdW/4RnqWwPBjzUlI8qwh/doUqqte5Srh7uol8dX3rz6/e//xt3dv3n35N/3zl99/efehcJ7p1etXf//66pe4VH199for+fj166sAPWJSxl3j4V+Qb9H7HQL69Wv6D32A/j/S4ngWecp8+I2mJGs44h9ep39UNmenX3+f/kFjPHzw6u81u1iSH/8R/0OkvCpk4bfF/g+SLTEC3XgWkFz4979TlUmGE3E0w7/PCiA7PEctTOKK0KNA8THPPKw6edr1rYtFZjLZ4+zbpAqRL1bfMwkhacDJp7v1fqdpW229+8f3otpLR6YHQRyPh9V+udWO4hCtwTMGAa02+/Vud9wcRInYAYikgR5GsFvvN4fNarUXJGg4eCWhXzseV9rusBfVTnKkEH1Jt8++MYiDpsJ+t9xIlIwih2mYxhCM1X5/0LTj9ihRTcqhUAYVCqJ/u9OWGwmK0nEo+VK53+625P82ouUiOR48SLm20rbb9eGwkzGfhtdLT4INotivljtts9xuxCHSRIjbp0cyWh9Csl4fd6vDeidRNUqF4Rb7gYYmynq/PspUDxYNjkbcG5YWux3tx5YSaUFahxcyKLMM/YLC0DwNajaXu+2B/P/NVhAkjx46qJnabtak0zhq4smQxycY2HGSUrnd7NYSCOWYIAM7TzKYWBOYIXWDzAIsMssw6HVZw3oPbX/cLw/7tUTxLPemz4NqyUpbHzfHNRnuyfViQ7JkQ+rncr1di+ZIHGZxWGlY7g/b5XKpyZSGMC8GyCQqQisYVjhJ+h/Xm93+INFCJFNTCweDigEZRKxXq6NMMchrB0xq3JHGaqMdlhJZU6wZ2ImGUGy0zXpHxvyirXY5NkAtpNHQNoy0pQepIXgelGfYoPdApkFbMkMcljnXgc3W3Wq91Ehx3a6H5Q8aVmn22/1utRcefJ5CW2cb4M6IJIhxlkyD3fFwpKMs0S6kpl4PNEOTrKukB9sejivRoS8LOMsCUyWjvWFDHDIPI/2YRLWoRk6RUb9eLzfLzVqmqUjVJ3VjWOOwoqMbgRFFuuGs2IbTDZUSgwhSFTbL/X6YajmzSU+xXO2P/O6Aom42BUx9M7RlkrJ/re1W2oa0RhIIpA+3rdjXyK40kkqFw2Gj7Zfanrv3TgE+fXmrv0mDgwVSuknSb4+rnVT6Z3HJdJICyHZlx7Dagdi+0WSKX7FXMmzXeAikisDmeNgtyRxPJhXwI02BK7qZdnzHmURPdFwfyOCAvxluVS9V/5fHPRlNkzogrt6qNMF68pNkOiwPZM6/X3L3yB0goY9uAY0ZMwyJjGbXy9WW3w9RyJry+HFIFt1tl5pGXZbcfWQxZZgDeXj23K0PJGu05VGqnFCI/Obk4TCrtUYGLsc9v2OmkDOF4bQVSNaazWp12G1X4i1nZYe4sOadtl9vNluZ6po5LKU7y9V+daApv+We7TZqp0dXDSzXZa2Ohy0ZuZNuSxShtkQrMVrcHrb7/XFdz3W2AahBudzVRp/dyM/CmOrZ8qNcnh3pXOuwOtQTTA10SPI58gZS362Om+VB22129YIOi53cRrNoXOSV7DZIHVnvlpt6LVGMriPZWrXXjis6Bqm3p6qRT5GPHLnRKykcO7qqOgVzaEg2X9v9Vjse9nUPmWpow4kkF+rI8OO4PC439SmKcub0HiPZYcL2uDtu9sf6AE41OV2ill5z2pDx+G78qkjnU7ezK7tUtCMz6e2hYWSinNtBhD1gx/JcuVnY3UpbbncH7XAYv5Cbnm1LQW/XZCR2OCzH72ewZFtCPT5H0mwvVQ9GGpDZMr2kl3B3oKORCRrtc+AbkhXySMap68N6NX47cvHI+FpySwyNLq4dG/yx6qEtuYTekAK9Xe8maK8psk5vBZPs18m0YHc4NmwvUA1+PUuXatLFrLa77bLBX62e+lkOesX2GJGOffz2w9Jkh067I+nPj7ul6rluAzOSHDqRSeN+vV0tSbEeH9pAxlVuBWBNxqi7zRT10CYjJ7lB6mq7XG21CcZ6FPn5hORGebvDdr067A/jN9UpNl2wsm6ys/T1brPZrXcTjJ5szDaTyXWQ68N2s1o2LPEop5buZ1ab5Ya015sJfDi2dDezJKm8o9VydGYnkGyx10dtv9H2+/EbEs+U8zrd7Y/b42q93Y9fCT1frt24W203ezIVaNoyNwKzHlgXwirJftC05frQsPalmtwPJd1OK2233JM57viuaz2Q9fGxfoUUkfGTOXgJpHdRbTZ70q0sG/bMq6aW7w2p02a3PU7QsUTy3SGZ3ZJGeoIefIDTZr86Lo+kzRud+cmU3AyzPWyPx9WmYYOmImQn2UIjWfvISENbrkbru2vLoXL9yY5u/NRWAN13crtWcu83Cl3Hkp24EqD9ardZAbRkZSp8iyRX13b7A2laG7bjDE0ndi5GdoK/IkSHFYR/sEwVf5LdkrBaH5YrCA9gGSqgMbAkp4pL7XA8LrcAI74KU4jCSHL+qq21HfXfwSVU4BfLlNxOAzKfXpIcbDgCOJCKDm2QbcvtSiSDSNq4NhwsGUrFCpVUUmnLPfXObzS4xjOL4pXixYfgpfjoTJJuDoJLspwuKf3JEX0fXyzZ1mJDJgeHA8T4rxtS9gDParfT9hCbKtrw6oFdxSvHck/q60prCDEgjHly3dB2kYn9yqGsykfJ1uWwXx2042ELMLMqkVrlsyCSe8NIbT6u90eAwtgFRzoN10cXOci7PZmZ7lZrCOdFBbK4gb+Q0ZLTjdWSbksEmCM1JCW7r8dwJavL3UrbbDa0j1NDl5dCqaQ7bLWDtltD9CqdpdBDfiC7S3+7I5PJDXh701ZRpKaPu+X6uFuvAEbsDYw+DjA9ZyO5P2i1oicsjgDp9+b953efF29cH2czQ8MJrEDPwoDKOc9pDd6tIFKvlTBRLjv32ZEWZrmG8MI0EIZ/snga+Fl2akYavz2NswPgcGlNwIukS/a422532voIMPFoYqNHIQ1nvZb1zu/pJkUNwsfdQOd4kY585/EgS3dcbw97MnMbThdgI/Kt8KV0fox9SPd56sltyGw2cEKb1QZngQrkxl/bIz3dNAn8ejUEfb0+7nfLXcO5MNXo8bd0VyXrmAixXNofN8udtjs0BCYYxwJ6TJmey5Qcuh93NPTJoSE8k2r84Jnt5Jcr8Npqt9xsIfbtiFOf7AfdsLyr7GHEzWa7Xh23EJ2wOLx51ZEt2czs96SR2e6PAHMUcXBMviLvPMoWmc1+S5ceIPYRy8E/4BeiVTr1ydxwpR2XK4j9dTIGmAGSLznHDT38v4JYLBZnv6JAMmzAfqPRfdwNMTxGwHaQbLSD3eagLfeknZkEGzuG48kVkx3dtrZriMg2Ercn6ZJdrw9kdAtxqkKc2/Mtxwot6XbxSEbm2nIJsSlCHN6/yY54j7u9tiGFHMCdIo4dynNrZHar7ciod5KJxmpQCJfVkS4qbxoCX43Bvh4WM3i302irOP6IsTLBk/Q77Ena0zBs007x5Jxie3o2e70bv8g3zPGkkn+rHfabKfolj97yc5MM2rfbrvdrbZqZXWGOJMVOsNfL3SQ9qo8vkrs4t/vVerPUIPZtCFBbmYMu9gzTC5vJw4RQcpFnu1rRzQIHABesjBmZV8PEZ7mjJhttf9xsRh4a1Pljr4xce7/ZHch4cj3yhCm1IXHNSC1a01Dfh7FnegXwvOUZtN2Jhl7d7PfbcVvPgh2Jo0auBq+1tXY4QBwflISXPHJF16bIGO24nqz4FNxMcuNMbXfcH5YNwYNGNKDgapLKhc2WhrfdLCcrP7m7SYZ/f9xpK209YSGiGxmkg9SsjuQfiON7cvDMXSa5AWO1In0vyHkySfanAdFqDzTQ+AriyJMcPHP4Sa6aa9vN8rCD2AgryR57/eRam/VhsydjhukSPnb9yZUaun652m8ngy/4/yTLznK736y30/VYvuQEd7XWlkcy5xrZp1MgD2XR78j8dnXcHSGOQrSip+FCg8ij8TMWRhrVOY8kSuzCNlUtu2GH5MBuvV6uGyJmjmqI69wsj+7eusnu7DnsNse9tlbqcugwhAYPHZwbd+vdYant90oXrKpGpFva46/l3OJrOlqj6T8yd167ZbcikMJPt6+sVbb/TeRZLGDDkTt5Qcb3BH25mQzcQYbc8ubquKaONoidtFLk8eSE/Cu3PHu32m53h8N6rXTA013aL5Kl5o5uESYz3APEDnDRFia/JVD2YI+22222E6BbQ9k3ZEK7PoDEROFGT8/ZJO26lCd2ud/ul7uGMMZqsUljriNb+vgldfxttkqHlU3UpCmXpibzVnrLoNJ9lI3MpBUfkNTbzW5HT+aM2e+zcn1FK2lsbXlggXPGZ9a2O/nEZjttNZCd9aLc25UmzX3c0pAuB6ULCk3YlwG18W61PBxJ4wcSk1e0wS50NVKzau2w2azWR6W7PJvRraHspItfki6HzK1V7jXoSPdHZEeyjpjNlgxNyAhFJTplNH2LMJRGJtL7mda7Fb08BOL8tihz/NWAax40TSPTCG1C9mR9UnID3Hp5XG83EAf6RfADnB7w0k3s4ZuJb4bsuWEymdB2azLQGrHI53Og+NYah3qM5HwWW7rOCnLGXSQDcgOSUiS/GXG/0XakFijdUd5pAbvByEM+eTa1Rnqz9p22We2pI1vlsF3UmgHHRPa73XKjNV1cOJ05CCNTsrna7A5btS4bUWNk/U93B21z2JHOWuWkRdSYB/xC2mPyd+w8lrFrt9GWmlJ3oIxRQ1vp1XG53hxpMzcjw1isyDDyJQNaUG85GSoq3aBXM4l9Y4WBfnt01pK38O32h/V+u1Y5cy5w03E5+bhI9/6SnIgCom9Q/IE7TVtvd2pXWBpsoEUK1I7Var3ZrVdHiIAjIoawrTGyk7s1aXfpzp7xkJtH7HLzu8OelB2lm4O74c+YtTnS+5JoTG61J+Qb+NvmG1I2HElPsNkrPURRMaFxuiG5uWqz2dL6OiJ9+3xDyoTtar9ZLVcQwTPkLCh2xefoZshvkr9bHQ5k6goT/3i4MfJbzdcrjZiyb7iaHMoMnN4Pm8Xmy76RHNLREM6kLClcVupg1qPQkgsVsSIjHxo9S2H/1cU9YC56t9ov2cF/hYeJutDJA74reTj3jjoolweQe2kk0OX9GSvSuGy3mqZwU2cXOMCM8k7bxM54dQ1+nwXsSmpL0kFG5lir3Xa9Vjhh6eIfOEs8Lmm7vlZ4CKQLHoUhplF0pcsOHetsNprCbalVfKvI7waSh0U1MrPaamRcMF6PWgPXT2RY4OBQ0oTt8XjQaCyGESxIAy7nYwLJueHxuD9uVgoXXDuYB114RMYzR3rcZqtw0bKLXX7suNrv1kd6wniSghIPxKRS/Lhfr4/LjcLwUVXuUhUdNhHfkNq5prevTJLomROK9K5yBuxXdB6+hbhRQSbxh0UC2NHLaLcgt0RLJL5xJcKGBZKgu/HW64PC4GOdBgxB36wPh8NqOcocpAFdPpoB3QlEVyanAU8nT5Llfb9c7jWISOkS6AOOIi53JM0PO4W+pi7wyuRJyoTDjsYw0FZjTP+aLcgmT5IO491+vRqzk22ePMmVn+N6t6Rha6aps8XZk+zqjrba7tWuUftu6BpuekYu3+FU/l73kWm50qE+D9vtnt4kpnTdocWSlHzoKrS2Wq7pZFZTuvjDlx2S0evXxITdUempdJFckFxCoRfjaiA+hcQtb+JTdEndH+yDHjzJnfGgJzxo8AuIzfAluqR5yemkxjDHPRn2HiCubQuwzy5Ci69lYzs4c8bsK92wXeNBdkpN7zva7IGO5XHhmobshd7r1f6wX65hNlxzsWLZGzRJsi4PRzJ9A3GzcLHKX0i/X5Ju47iFOTTFxTrgKubjcrVc0jo2Iqxkwm72B21L2ioQrw8X6u1R+s7B/Wa53W6BQpLUYbOWv9wQ6IEmtwdP2x9p2oJ0s1y0pCmQhT3stmRYBrR7mwuWtgWytNpKoxdqAR1G5MKNmwPJrdnrw470Coq620ZY+bSlZ1N3h+MSJrg6Fy5rEuQW9VZrerE5zNQoZnW8KAuD4EVyJ2m2NID0FmZ7WE6VHuL1ZDt80oDuyIgZJhRYzOW5T2z7dWnpsPSl5IGe/eFAJil7wHFUP2o8rJasNdvDZruC8Wdy816RLVvNt2Quvt0td4qBrQqxx/xokttcl/vlZr3eQQ5Wyszp6b9S+ZVb2Nmv6AW7kE1AP2pSfuXGrNvlfk+G2MrahmwT6+DEJZPr1ZEMWA6AvX98VXfhHlx6cbf0eUTS1JI59n4FdByrA5FIMXBAgz9J784gc5XVbrdewexNKrGmztBCcsrVpgPJ8s0O4hrmTsJKakpNqA6kZK6AIg8mqDbGXmg5hb052TdyEUjWB229B7lqm4eRdVN+aMiN8dhQig7yRoQlEgmvZESj5Zrt9RszcU+RNO6Rrksd14AD6F5a+YJ7R3CXy/1G00DWMFt4rQqw5C4mMjVZ7dbLDWSjlaOmDVfeEsjNCUi7uicDQTW1K9uyMYzy/yvuSpYbV5Lkv8xdXbkv5znPac5jNJCESmiBiwGkVGqz/veJAEAVqYUiPTPRbytCtCc6c4k9PKLkKZ0mT5/WCPK4rtvq7XRAxydMlgYZfCZ64u+hDfMw3WYYJ/q/iMkUyTdRKmfEf4I5ncNpBaEzaMmoV1bmkEH1Zt29/FpvKv6DV3B8CVatCu+iVTlKPS5w8ZJNuLA7G7zypBBzJBlGYNPgewZWwzO7paAzJnhqbS5Yv/fNbijx6o77MXB08RPQURdD46rIdtouUQ50QxcoobW0Olqb47qOGLnPd4DGL7jCtTqCdEhSShsj3Ysy2DD9QLc0R2n8V2s1/EIwY8EzB1WMOcodvoIGmybOKcndkxmqeb7BtXhsE5jnydOL0uWgIf4KHqeisVJ6ZUwMIsfU6zNcLNbOb+XUl7xom+0zaiabqKLzOkfR/1dI/24wFB1XXLFNQrgMuGF7MeeCNIOJMQtb2hmytlnyvwO4//4frQcjrsISoF5pq4LKtq/HqjucTKXpNaZVA9kjQpgctdSXyPjanpBBusHTphqfR5jwVvJS1ZsEl/vBOsFaNI9aOIO02mDpKpK4tEpahxxDZi8R7eCGt2DpSLk8J/0M0XqJDvt0wloSqjmCzheIanTXrLDMMJijDvES0LGn+wYa1y56m2fk0wWm3/tVh902LsYSJJuyyPQLRA1WDiANTy+VWQoXLxA1CpRHypEsUj5HWc0loGoNIjIyGBt9Dn6SC0QtzzID+cYNaRGR/2S3NR4OJSM+kNhWOZoNL0BtemzjtIqK/OsclZoXePYdWHAulQpGcZdaZkQdKrUNyUgTssyMvgSE5leYDyL4GE2OqeEXkHpQ94sYyA43IrdiG5N84ISNiV4z9xol5EI4YsrjUXNfNlz9P0hL20brlKPC6ALT63qH2W1OcOo4S8/bCGiIkZ7MfygopEyUzmTpmb2AtHpqsKFtD9IYG0yWKrpLRGhpevTORt64/ICGNpUKjH3SaQrKxnym2ylBlrBYQ55Rm5DH9T5brKrv6w7szvEuKEVqLvcGLo9gE4nn3ETU2eVAylhiS26A1i6flTth6qoNE6KhzZLBOeOMyeYwTaimT0SndCieiJmDJfXD9sFNpT6aoYE9qyyYIKVlHSwdK2FlPhNzQsaxEygER1BIHNjcAgrvfPJKks0bctAvXiIabScw7eFU4KGFZUCl6L0H6ZSwLoh8wa8J2xjXwfKQVmiRo6H+A6AGHFciJS0Q6RiRW8VwXAfTecw4n9EWP+Gp0OZIyWqF1F6OYXkXkFp4Rr03ngxym1tUnqI62DIFJlYlzy63JOCwDnaSAikUHtSYH1CSXApRCi9Ddgtqjw58V9xOS7o3t1HQgaqONk2TTJLZQiknPBxtQgB5R56Ky1TrdQaoR804I6wh2zIHh9IlIHDHpLPe0wLlGH1yCeitXz2idE1W6+iE07kFwBSSA7dORV6oHA22X4BKssEflDZ063S+GOaELUmtGK+4ija3QYAbvTEqbUli5haXQ7gQun2GJ1hmoRkYmE7ov03L0+ZPJZb8jDrmrFpiFmX3PbbF5hG7jpJZBKJQOdyXK/DGoNRimDyx4FJVlFQkahWDjzmi51fg4nychDB6OosiR9X7FYSJgyTIePbS+wz28weMJwKhX8u2Hn9KL3A/SHmhM0iZ70A2dV0HoaQ145t/n9HNZ0kdstQIfYf5dbM89uPPh5cg4Y0znmzwHMUD3wH912v1Mp2B4SUENOjALYQ5si7f4eybdf1atc/jW6cn7GJp4wOPhcpgcH28/E/N/lf92Gk1/vfPb/VnfJffWfT7etU8omaPCTYaqwqchup42NHv40rK4Wdd3dZVX78/n76L4vLK07tQmSVphRCZGCn/SWmPhGN8ZsLjRbX7w80zFz/AcuYueGVczDEOBwKNnBZt6UbSWcmv4CbM++qBPm36+P79uKtL+PtqsTp2L7Ce5qnnnu5qsaX/8DUY79/H8eBjh8Zb45muvID2/hb5sNIJoJU3kaR4DmIFfLUxA1kKDjaU0JRXV3s0QpOQW0mwQw7vHzonkGvphRoKrcoLxEsOjpHk6ELAfHofK64T2nBuL0PorMA3AnMmWmtrvcIlULXfn/wZhsbPk5N49hLmSyJk5DvgPuIVdLSgyQCFiToIEfFD/hXAsXf7/RVYMOsN84glcEzcAg1aNhddCD4hHf09Mu7Ibzb7tk4K1BkptCYlh1ugjHDZHuvDbnd4OmHdrvYMkP6AtjRy85s3CfLnJ1TgLQ0qsM+RH9eifjksHpv2MO7s5U/AvhYu/Dde4zFYDCwW3XGCk35pwvlurEk1VZ4HXwuRG/N0qenp7IrTU1KxrPDSiRSX7T6o3W557FGszlkvrVKZz+13YLEQj4rChwROUGg9Ic/XcU2USymP/BsePeFd/p4QTw2np+eMoRGpeGqw0SkFHJ+Bn1h3lodFtaaPPjT93/EyoPER2TZKScNfhUkfta0HjrAUmEEK8lJCKZDrt221aVaL39XhsF6mAFUjA3vK/JWrSFu1qvZJAIWOUYWkkserCPfVa5frcJI/QbsuTEp3/nWwddfs1rTzBDjtGlnvuBg4wYe+GWiea2+CkiGlkekq3v5tu0oBKFnly5iSiLouPVerek/XqekPSTB50g/XyBZYx2EZD9XqGY+DeEWbzHMLcqI7NWIsTyvHdBxor0EU2gWd0nN4FeDn24Jl7mgJNcf2yq3jByWJZcIkyUqyPLMexjOYX6tJzBUNllVlEtnEVawXihKBaHk4CavyQgC/0ZNgYsWQklQ+pWfnOtgv9CR0RLlyX3NxzgxAM6ys5BY2F1wxvOd6EksjW2uFyWu+nwvQz3oSE/SBbjxPdi+EcxJJpIngHiXJA04LXKC/ejztigcjY1LxyDWAbZt0TaRRgVt1E9Je36P7Xe0bsETRWe2kSqFZvLZoKC6tHXmJoYRZNsGaWgWaZdM2B5BrVAlyuiWTVJS8E3hGTImomLithPHI+PCCRC2l856kchlgKe2htGpaMy1lyviNrwJqw27+atv3kNrpPZYrh27XtjyTN194TRiV1lF69Uu8L/bq0LUDv2BbvaG5gaiFoBOR1yz/tMxPO1LRGRdYBzV0XWfV2CSaxnX9xx96CelBbYTmQfb41j9V3fq16upfyx29eve2+SFhjoWOOnLEF9/la7imS4RzadHCOabyTehL/YDvdEfO8YG9acZwmVJCeucaNFjDaMujlWJCe9E7rGkw6WhiHbthwvFi98IDm19PE19pDVHqJkFKWpmE8PiNQKd1ZaCg1x+tdDyQJhvSzR9lR4bVRf90PKx3r9v3mWSf3xqTkN+8Cd57JQTH/It+o9M8s3u/EbJLxljDuwR/oaHQ4/DU0N3bE7a3X5tlvT60/ViA3L3x6SJNuz0MlR/o0DOlyB1KGBT4I8rDU1dXa54Djw22Cz4aldBB9iPAU40aNtRMClIHIUG934xvKIRDWfs8WSE24um0n1H2FQ7wgRAaLVyKkvgRYdU2v7cJ478l2fw8w64cwuV2sTliyj8wDWI0CXV5P6MjG9iZxTBmYIsSwXMuSgdrEuzOn4HSPh9TmHYIoI3kaJTHuNmtMZuKlKW0KXSldyBcdNUrVhHNXKEyoTzmTpB0Nl+qvgH7tZiUzgWODRYEvGr2T2QFvnYVWnyoPcfRZUKf1g2GBVwOF8jk8cIkuG/3mT0Lro6Ch9oYF5keZjasKaJTCuulYve4HNx6tX8HuahaUFMyC18IpMxLA0257MZrJ0wK6cXPINmX378t9rsW23LjtC1qtLWb3QH0QY3VZHCUdBw29EaPkSyRKLfkHTudkHa+BR8uxqNjNrGYUOD2M759n1TYzPNchHUJg/pugjgQK4A8pEoJK1TCyO6bELL/CgatnfRMVlDQe2WAh65awaSSZEhqYxO6Zn52Das1PAGJFIkn3zVlsNDP+J7TNLMKZPO4FIL1WyDCsoYsRqZ4IqerJL7XrgGHrD9oKbSLCcHMm4MTiRYYk1IxQ0LBu9IRUjK8Fk91u69BTrgHHkHgrSi54X3fjrPfk5CGGEOQoqSWZqCrtsHDPjaGaMjjKryYmwakSpROxkhquiw8epY6zeSWOpKg1K5krPQv1Of6DWQYssqTNIoJNd03yaNV97Y/7E5nE6uaZnYZZRO4RG+MV4BRZ7o0XumEnM5d4RSostsYoUzRONrfvYab9oySMmUA+T3nsSJjF53qYkg7aptQTXLXxcFPJo9W8yGGBEqPe5COCcnhkLKmXGx3XLR1aLDpOdIoHYRNqUC4B3zf7g4T78IGFVRekKKPNmGM6V2ID7uO0IInIwYVtU0Z33QP1hrsjJcmauO9S2Ayugfm4+ManLxK5rLSKYzg98B8QgfEkmniIhn3CZy89+DcVOjgrGikV7PdpH31jF4jZnnSXs8kYclrwro46WyS6ZzAjXCXYAKLNLQOZDSbBMrLn+2op5oL6yfNmlJfbxyX18uiwYYP1goUs+GqVxeKptE+GytYlJPWVHif0DtzF1I0a26NCCLKklmfDzBTott0UGlFrSmaTvveBgT7HZTl6tPCVTw/Wq2QV+2tdYaMq3lEbY1y+1hLgjZoNc8aD3YVgjNGE6KUM6nXwa7CIpGaZKzV8/jXqeUf2gm+XwlU7HeBRTOv5KJE56VIGE12r7EKppZ4zo0KCRMJ7jZWsRQTh9FEKJmLPbdVq+16t8HrVqR1ZP9bMxdcNAWveFZ8CpXXnaY1tvXWGx6O+p+JpYCGCw8ik0rO5LRM0RTIdNU+OqZ8yI+02a7a47p+f65gMmVhuLPVJYxluB1k14BDw5TTTE1QopDgE8h+K+F5gt5oZxN6Iu9CmZBylo6wqpAyB+ZmqGPdNFiDEz3nHwuI+k8oh0paVCNFzWU4BRT9J5jHpuVetEd0ZqISzomQwjB1M9ZVtanbFrzy1jtpY5Hc3iecK3QelnS07UbPceFXTxX9owTmLgmjRSwRNf0a5n7XomwBgf7SrkRU4jPUOpVMwxjporJzXPyECJpke5lcpjnE6Ap2l5yxZNm7hO7d20EOrBYP6h/YFI2HQL4Sc3LOcZ9GarRq/c9jf1i09e9q9XZKp2NngdwSG2WJINpN2B87cv7wumamh9fSlOipuQ6fXYIB+/g9wBYGYU1Qdg518Ql8f+QwZn1I+QLkLTgXFA9dnfsr9D0YLtAyWqVjLJDouI74jxUR09akV5SRJZLG3yDG72Ow7JrJEnn4L7CetXtDZ4EnB8UoSoSOPqE9dIt1t4T57SSPDZ3jCAxVrDDtJtfOqxmcSHTspAxOy0AgZ1AY6yfQf5TO20AQZ7hE9QrMuEijVJRSmnlAwgIpRlpJkTKF6A6Y/8SD7px59daWiGJ+xon22vJcQetShpnfDnJsFsS5CXx0rkQXzyegcL+W9sooreewXX+DIY2B092YOdbx6XkNkmxy6NIqkTCp9XaQ5M7iatySs+WlnsPXajegflSB25V1iQzQR4zTn0khl2jYoBcl+m4/wcUqq0j/RO2tngWhRVvptWZm/Bm8uE292XVvi+Xx8bHuFlXb7rD4kHLChahLFCd8hLwlJ7nfrZ5ruEJBC/bytZpBb26ZUvkZ4yd5CJJQWj+HcbxrsOvkteA8eom6qY8Q9zVov5MMdVyjOIPNucfaiB+UcNpzvHqOdXxe9RKbIfrALgZdnHmWctWD8jM4G40np20elB4dN0FaSAU/g/nxziEHHk4vyM+QJYgMvkOKR5GiIUNeF+k/+hbswCyH5qi8EiKKGXQ9p/1I94GXKgo78DHOAbRrXuh3D2MJergMUXqhmORyBrwnckFIgypJ5qieowqpa0iHrqXDstRkNwUR6GaFGSQWWtdHijQo5WcJevZPFViKxE0TivY9YRDFPSjJ2AUjyDpybHaO9AHB1KBgUoJUk0+Ys3APSAuaTk7zZG8X5ziXaC7Ocre5KsF9+QXExapaPYH1cUpq78lYLtEe9SXUobqjPzYHtI5TCaaDcmGOuMOAeLd7blAijKBNMLMt7qFhXx6FGpSLRbqkPkL9SxQNHlkTyBMt0X/2CWmzQWFKSWfUaD1HJe+EAVTz3CBpE0av3wwTrhPgLmNLLp4pQX7zFcrFqgO9EDJGnCFzeablJKDofXfWBi9LsFx/DbTHcklGyBiVTRgG8yNOcjp+JVWaeeODDwmjxu6AeCq6qY7c/bitlm2NxRsfOB7K8cZZVvYEe6rDea7f6H9puoShUeR8cRefLGmtfou/f9vutm9gKupBCvrbsetSFnpiDb3VzC9XUpSdrS9jPTTbYRDbrsfNQxk4KRV9CXKiK7D3HZkKh+YFPcwqBhGULsE4eAU1X8N1PcSIUPuB7HGSfjHKglGXM+RjRTNo6WhrVLAlDccLpPgoXWW8tiWz6Wc4p/b/BIoF550lT6fE6JZreOnj/xz6DAKDa3055/ofgZ/hCobIdBymZPHSlS+QKvki00/bkgWgZ+AJcQd2ZlpjVSyZrjuDmVK5HrzWSsYSPMpfIE3Lh0lPos6Qyp5n9/t6Or1g4w6JCnaa5lnZvvkXLNJ0IImsTWn78r1zvDuu4CZ3r4eRUPOYD7i78cAkLII0RcEQxBnQl6o9wo6RNIGsh9T8Yt+0Df3WRVste36gPwY2plOl08hv0A2j9MZyJ2iumnPBkshKVF73g8WEa6BbpZW/fWlXXc0J2GW7eGxa2tH9G+YxWilC9HdQw3384GV1gCpAvOZy+DtaKj9+cA/mooJUjg7yv//vv/79/xI0fRw==END_SIMPLICITY_STUDIO_METADATA diff --git a/locator_ncp/locator_ncp_cmake/toolchain.cmake b/locator_ncp/locator_ncp_cmake/toolchain.cmake index a5e4fd4..dd6a0b8 100644 --- a/locator_ncp/locator_ncp_cmake/toolchain.cmake +++ b/locator_ncp/locator_ncp_cmake/toolchain.cmake @@ -1,72 +1,72 @@ -set(CMAKE_SYSTEM_NAME Generic) -set(CMAKE_SYSTEM_PROCESSOR arm) -set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) - -if(WIN32) - set(EXE_SUFFIX ".exe") -else() - set(EXE_SUFFIX "") -endif() - -if(DEFINED ENV{ARM_GCC_DIR}) - set(TOOLCHAIN_DIR "$ENV{ARM_GCC_DIR}/bin/") -elseif(WIN32) - set(TOOLCHAIN_DIR "C:/SiliconLabs/SimplicityStudio/v5/developer/toolchains/gnu_arm/12.2.rel1_2023.7/bin/") -elseif(APPLE) - set(TOOLCHAIN_DIR "/bin/") -else() - set(TOOLCHAIN_DIR "/bin/") -endif() - -if(DEFINED ENV{POST_BUILD_EXE}) - set(POST_BUILD_EXE "$ENV{POST_BUILD_EXE}") -elseif(WIN32) - set(POST_BUILD_EXE "C:/SiliconLabs/SimplicityStudio/v5/developer/adapter_packs/commander/commander.exe") -elseif(APPLE) - set(POST_BUILD_EXE "") -else() - set(POST_BUILD_EXE "") -endif() - -if(DEFINED ENV{NINJA_EXE_PATH}) - set(CMAKE_MAKE_PROGRAM "$ENV{NINJA_EXE_PATH}" CACHE FILEPATH "" FORCE) -elseif(WIN32) - set(NINJA_RUNTIME_PATH "C:/SiliconLabs/SimplicityStudio/v5/developer/adapter_packs/ninja/ninja.exe") -elseif(APPLE) - set(NINJA_RUNTIME_PATH "") -else() - set(NINJA_RUNTIME_PATH "") -endif() -# Use default lookup mechanisms if the OS specific values are not set above -if (NINJA_RUNTIME_PATH) - set(CMAKE_MAKE_PROGRAM ${NINJA_RUNTIME_PATH} CACHE FILEPATH "" FORCE) -endif() - -set(TARGET_TRIPLET "arm-none-eabi-") -set(CMAKE_C_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}g++${EXE_SUFFIX}) -set(CMAKE_ASM_COMPILER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_LINKER ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc${EXE_SUFFIX}) -set(CMAKE_AR ${TOOLCHAIN_DIR}${TARGET_TRIPLET}ar${EXE_SUFFIX}) -set(CMAKE_SIZE_UTIL ${TOOLCHAIN_DIR}${TARGET_TRIPLET}size${EXE_SUFFIX}) -set(CMAKE_STRIP ${TOOLCHAIN_DIR}${TARGET_TRIPLET}strip${EXE_SUFFIX}) -set(CMAKE_OBJCOPY ${TOOLCHAIN_DIR}${TARGET_TRIPLET}objcopy${EXE_SUFFIX}) -set(CMAKE_OBJDUMP ${TOOLCHAIN_DIR}${TARGET_TRIPLET}objdump${EXE_SUFFIX}) -set(CMAKE_NM_UTIL ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc-nm${EXE_SUFFIX}) -set(CMAKE_RANLIB ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc-ranlib${EXE_SUFFIX}) -set(CMAKE_GCOV ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcov${EXE_SUFFIX}) - -set(CMAKE_C_STANDARD_REQUIRED OFF) -set(CMAKE_CXX_STANDARD_REQUIRED OFF) -set(CMAKE_C_EXTENSIONS OFF) - -set(CMAKE_C_FLAGS_RELEASE "" CACHE STRING "") -set(CMAKE_CXX_FLAGS_RELEASE "" CACHE STRING "") - -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -set(CMAKE_EXECUTABLE_SUFFIX .out) -set(CMAKE_EXECUTABLE_SUFFIX_C .out) -set(CMAKE_EXECUTABLE_SUFFIX_CXX .out) +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR arm) +set(CMAKE_TRY_COMPILE_TARGET_TYPE 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${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcc-ranlib${EXE_SUFFIX}) +set(CMAKE_GCOV ${TOOLCHAIN_DIR}${TARGET_TRIPLET}gcov${EXE_SUFFIX}) + +set(CMAKE_C_STANDARD_REQUIRED OFF) +set(CMAKE_CXX_STANDARD_REQUIRED OFF) +set(CMAKE_C_EXTENSIONS OFF) + +set(CMAKE_C_FLAGS_RELEASE "" CACHE STRING "") +set(CMAKE_CXX_FLAGS_RELEASE "" CACHE STRING "") + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +set(CMAKE_EXECUTABLE_SUFFIX .out) +set(CMAKE_EXECUTABLE_SUFFIX_C .out) +set(CMAKE_EXECUTABLE_SUFFIX_CXX .out) diff --git a/locator_ncp/main.c b/locator_ncp/main.c index 939ed36..c956e18 100644 --- a/locator_ncp/main.c +++ b/locator_ncp/main.c @@ -1,71 +1,71 @@ -/***************************************************************************//** - * @file - * @brief main() function. - ******************************************************************************* - * # License - * Copyright 2020 Silicon Laboratories Inc. www.silabs.com - ******************************************************************************* - * - * SPDX-License-Identifier: Zlib - * - * The licensor of this software is Silicon Laboratories Inc. - * - * This software is provided 'as-is', without any express or implied - * warranty. In no event will the authors be held liable for any damages - * arising from the use of this software. - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software - * in a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * 3. This notice may not be removed or altered from any source distribution. - * - ******************************************************************************/ -#include "sl_component_catalog.h" -#include "sl_system_init.h" -#include "app.h" -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) -#include "sl_power_manager.h" -#endif // SL_CATALOG_POWER_MANAGER_PRESENT -#if defined(SL_CATALOG_KERNEL_PRESENT) -#include "sl_system_kernel.h" -#else // SL_CATALOG_KERNEL_PRESENT -#include "sl_system_process_action.h" -#endif // SL_CATALOG_KERNEL_PRESENT - -int main(void) -{ - // Initialize Silicon Labs device, system, service(s) and protocol stack(s). - // Note that if the kernel is present, processing task(s) will be created by - // this call. - sl_system_init(); - - // Initialize the application. For example, create periodic timer(s) or - // task(s) if the kernel is present. - app_init(); - -#if defined(SL_CATALOG_KERNEL_PRESENT) - // Start the kernel. Task(s) created in app_init() will start running. - sl_system_kernel_start(); -#else // SL_CATALOG_KERNEL_PRESENT - while (1) { - // Do not remove this call: Silicon Labs components process action routine - // must be called from the super loop. - sl_system_process_action(); - - // Application process. - app_process_action(); - -#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) - // Let the CPU go to sleep if the system allows it. - sl_power_manager_sleep(); -#endif - } -#endif // SL_CATALOG_KERNEL_PRESENT -} +/***************************************************************************//** + * @file + * @brief main() function. + ******************************************************************************* + * # License + * Copyright 2020 Silicon Laboratories Inc. www.silabs.com + ******************************************************************************* + * + * SPDX-License-Identifier: Zlib + * + * The licensor of this software is Silicon Laboratories Inc. + * + * This software is provided 'as-is', without any express or implied + * warranty. In no event will the authors be held liable for any damages + * arising from the use of this software. + * + * Permission is granted to anyone to use this software for any purpose, + * including commercial applications, and to alter it and redistribute it + * freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software + * in a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * 3. This notice may not be removed or altered from any source distribution. + * + ******************************************************************************/ +#include "sl_component_catalog.h" +#include "sl_system_init.h" +#include "app.h" +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) +#include "sl_power_manager.h" +#endif // SL_CATALOG_POWER_MANAGER_PRESENT +#if defined(SL_CATALOG_KERNEL_PRESENT) +#include "sl_system_kernel.h" +#else // SL_CATALOG_KERNEL_PRESENT +#include "sl_system_process_action.h" +#endif // SL_CATALOG_KERNEL_PRESENT + +int main(void) +{ + // Initialize Silicon Labs device, system, service(s) and protocol stack(s). + // Note that if the kernel is present, processing task(s) will be created by + // this call. + sl_system_init(); + + // Initialize the application. For example, create periodic timer(s) or + // task(s) if the kernel is present. + app_init(); + +#if defined(SL_CATALOG_KERNEL_PRESENT) + // Start the kernel. Task(s) created in app_init() will start running. + sl_system_kernel_start(); +#else // SL_CATALOG_KERNEL_PRESENT + while (1) { + // Do not remove this call: Silicon Labs components process action routine + // must be called from the super loop. + sl_system_process_action(); + + // Application process. + app_process_action(); + +#if defined(SL_CATALOG_POWER_MANAGER_PRESENT) + // Let the CPU go to sleep if the system allows it. + sl_power_manager_sleep(); +#endif + } +#endif // SL_CATALOG_KERNEL_PRESENT +} diff --git a/locator_ncp/readme.md b/locator_ncp/readme.md index bbb185f..c50bd2d 100644 --- a/locator_ncp/readme.md +++ b/locator_ncp/readme.md @@ -1,105 +1,105 @@ -# NCP - AoA Locator - -This is an NCP (Network Co-Processor) target example to be used together with the **aoa_locator** NCP host example. The **NCP - AoA Locator** NCP target and the **aoa_locator** NCP host examples together demonstrate a locator that can receive CTEs (Constant Tone Extensions) from asset tags and estimate their directions (AoA - Angle of Arrival). - -Use this example together with **SoC - AoA Asset Tag**, which can transmit CTE signals. - -> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. - -## Getting Started - -To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). - -To learn how an NCP (Network Co-Processor) setup works, see [AN1259: Using the v3.x Silicon Labs Bluetooth Stack in Network Co-Processor Mode](https://www.silabs.com/documents/public/application-notes/an1259-bt-ncp-mode-sdk-v3x.pdf). You should also test the **NCP - Empty** example first. - -To learn the basics of Bluetooth direction finding technology, see [UG103.18: Bluetooth Direction Finding Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-18-bluetooth-direction-finding-fundamentals.pdf). - -To get started with Silicon Labs' Direction Finding Solution, see [QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf). - -In an AoA direction finding use case, the tag acts as a transmitter and the locator acts as a receiver. The locator determines the direction of the tag by sampling the signal of the tag on different antennas of an antenna array and measuring phase differences. - -![Locators determine the direction of the tag by sampling different antennas](image/readme_img1.png) - -To estimate the direction of the incoming signal, the AoA Locator needs to receive a special Bluetooth packet, which has a Constant Tone Extension (CTE). CTEs can be transmitted in the following ways: - -* Via a Bluetooth connections (connection oriented mode) -* In periodic advertisements (connectionless mode) -* Attached to extended advertisements, which is not part of the Bluetooth standard, but is a Silicon Labs proprietary solution (Silicon Labs mode). - -This example provides support for the following: - -* Requesting and receiving CTEs on connections -* Receiving CTEs from periodic advertisements and Silicon Labs proprietary extended advertisements -* Taking IQ samples on the received CTEs. - -This way, the NCP host example can locate the asset tag by estimating the Angle of Arrival from the received IQ samples. - -**NCP - AoA Locator** target can be run on antenna array boards only. **aoa_locator** host is typically run on PC or Raspberry Pi. - -The whole setup looks like this: - -![AoA measurement setup](image/readme_img2.png) - -## Testing the NCP - AoA Locator Application - -After programming your antenna array board with the **NCP - AoA Locator** target example, program another board with an **SoC - AoA Asset Tag** example, and then start the **AoA Analyzer** tool as described in [QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf). - -## Troubleshooting - -Note that, when using **NCP - AoA Locator**, you may need to change the mainboard flow control settings. Follow the instructions of [AN1296: Application Development with Silicon Labs’ RTL Library](https://www.silabs.com/documents/public/application-notes/an1296-application-development-with-rtl-library.pdf). - -### Bootloader Issues - -Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either -- flash the proper bootloader or -- remove the DFU functionality from the project. - -**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. - -**If you want to add a bootloader**, then either -- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: - - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader - - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader - - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader - -- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. - - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. - - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. - -**Important Notes:** -- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. - -- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. - -- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. - -For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). - - -### Programming the Radio Board - -Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. - -![Radio board power supply switch](image/readme_img0.png) - - - -## Resources - -[Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) - -[UG103.14: Bluetooth LE Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-14-fundamentals-ble.pdf) - -[UG103.18: Bluetooth Direction Finding Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-18-bluetooth-direction-finding-fundamentals.pdf) - -[QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf) - -[QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf) - -[AN1296: Application Development with Silicon Labs’ RTL Library](https://www.silabs.com/documents/public/application-notes/an1296-application-development-with-rtl-library.pdf) - -[Bluetooth Training](https://www.silabs.com/support/training/bluetooth) - -## Report Bugs & Get Support - -You are always encouraged and welcome to report any issues you found to us via [Silicon Labs Community](https://www.silabs.com/community). +# NCP - AoA Locator + +This is an NCP (Network Co-Processor) target example to be used together with the **aoa_locator** NCP host example. The **NCP - AoA Locator** NCP target and the **aoa_locator** NCP host examples together demonstrate a locator that can receive CTEs (Constant Tone Extensions) from asset tags and estimate their directions (AoA - Angle of Arrival). + +Use this example together with **SoC - AoA Asset Tag**, which can transmit CTE signals. + +> Note: this example expects a specific Gecko Bootloader to be present on your device. For details see the Troubleshooting section. + +## Getting Started + +To get started with Silicon Labs Bluetooth software and Simplicity Studio, see [QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf). + +To learn how an NCP (Network Co-Processor) setup works, see [AN1259: Using the v3.x Silicon Labs Bluetooth Stack in Network Co-Processor Mode](https://www.silabs.com/documents/public/application-notes/an1259-bt-ncp-mode-sdk-v3x.pdf). You should also test the **NCP - Empty** example first. + +To learn the basics of Bluetooth direction finding technology, see [UG103.18: Bluetooth Direction Finding Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-18-bluetooth-direction-finding-fundamentals.pdf). + +To get started with Silicon Labs' Direction Finding Solution, see [QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf). + +In an AoA direction finding use case, the tag acts as a transmitter and the locator acts as a receiver. The locator determines the direction of the tag by sampling the signal of the tag on different antennas of an antenna array and measuring phase differences. + +![Locators determine the direction of the tag by sampling different antennas](image/readme_img1.png) + +To estimate the direction of the incoming signal, the AoA Locator needs to receive a special Bluetooth packet, which has a Constant Tone Extension (CTE). CTEs can be transmitted in the following ways: + +* Via a Bluetooth connections (connection oriented mode) +* In periodic advertisements (connectionless mode) +* Attached to extended advertisements, which is not part of the Bluetooth standard, but is a Silicon Labs proprietary solution (Silicon Labs mode). + +This example provides support for the following: + +* Requesting and receiving CTEs on connections +* Receiving CTEs from periodic advertisements and Silicon Labs proprietary extended advertisements +* Taking IQ samples on the received CTEs. + +This way, the NCP host example can locate the asset tag by estimating the Angle of Arrival from the received IQ samples. + +**NCP - AoA Locator** target can be run on antenna array boards only. **aoa_locator** host is typically run on PC or Raspberry Pi. + +The whole setup looks like this: + +![AoA measurement setup](image/readme_img2.png) + +## Testing the NCP - AoA Locator Application + +After programming your antenna array board with the **NCP - AoA Locator** target example, program another board with an **SoC - AoA Asset Tag** example, and then start the **AoA Analyzer** tool as described in [QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf). + +## Troubleshooting + +Note that, when using **NCP - AoA Locator**, you may need to change the mainboard flow control settings. Follow the instructions of [AN1296: Application Development with Silicon Labs’ RTL Library](https://www.silabs.com/documents/public/application-notes/an1296-application-development-with-rtl-library.pdf). + +### Bootloader Issues + +Note that Example Projects do not include a bootloader. However, Bluetooth-based Example Projects expect a bootloader to be present on the device in order to support device firmware upgrade (DFU). To get your application to work, you should either +- flash the proper bootloader or +- remove the DFU functionality from the project. + +**If you do not wish to add a bootloader**, then remove the DFU functionality by uninstalling the *Bootloader Application Interface* software component -- and all of its dependants. This will automatically put your application code to the start address of the flash, which means that a bootloader is no longer needed, but also that you will not be able to upgrade your firmware. + +**If you want to add a bootloader**, then either +- Create a bootloader project, build it and flash it to your device. Note that different projects expect different bootloaders: + - for NCP and RCP projects create a *BGAPI UART DFU* type bootloader + - for SoC projects on Series 1 devices create a *Bluetooth in-place OTA DFU* type bootloader or any *Internal Storage* type bootloader + - for SoC projects on Series 2 devices create a *Bluetooth Apploader OTA DFU* type bootloader + +- or run a precompiled Demo on your device from the Launcher view before flashing your application. Precompiled demos flash both bootloader and application images to the device. Flashing your own application image after the demo will overwrite the demo application but leave the bootloader in place. + - For NCP and RCP projects, flash the *Bluetooth - NCP* demo. + - For SoC projects, flash the *Bluetooth - SoC Thermometer* demo. + +**Important Notes:** +- when you flash your application image to the device, use the *.hex* or *.s37* output file. Flashing *.bin* files may overwrite (erase) the bootloader. + +- On Series 1 devices (EFR32xG1x), both first stage and second stage bootloaders have to be flashed. This can be done at once by flashing the *-combined.s37* file found in the bootloader project after building the project. + +- On Series 2 devices SoC example projects require a *Bluetooth Apploader OTA DFU* type bootloader by default. This bootloader needs a lot of flash space and does not fit into the regular bootloader area, hence the application start address must be shifted. This shift is automatically done by the *Apploader Support for Applications* software component, which is installed by default. If you want to use any other bootloader type, you should remove this software component in order to shift the application start address back to the end of the regular bootloader area. Note, that in this case you cannot do OTA DFU with Apploader, but you can still implement application-level OTA DFU by installing the *Application OTA DFU* software component instead of *In-place OTA DFU*. + +For more information on bootloaders, see [UG103.6: Bootloader Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-06-fundamentals-bootloading.pdf) and [UG489: Silicon Labs Gecko Bootloader User's Guide for GSDK 4.0 and Higher](https://cn.silabs.com/documents/public/user-guides/ug489-gecko-bootloader-user-guide-gsdk-4.pdf). + + +### Programming the Radio Board + +Before programming the radio board mounted on the mainboard, make sure the power supply switch is in the AEM position (right side) as shown below. + +![Radio board power supply switch](image/readme_img0.png) + + + +## Resources + +[Bluetooth Documentation](https://docs.silabs.com/bluetooth/latest/) + +[UG103.14: Bluetooth LE Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-14-fundamentals-ble.pdf) + +[UG103.18: Bluetooth Direction Finding Fundamentals](https://www.silabs.com/documents/public/user-guides/ug103-18-bluetooth-direction-finding-fundamentals.pdf) + +[QSG169: Bluetooth SDK v3.x Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg169-bluetooth-sdk-v3x-quick-start-guide.pdf) + +[QSG175: Silicon Labs Direction Finding Solution Quick-Start Guide](https://www.silabs.com/documents/public/quick-start-guides/qsg175-direction-finding-solution-quick-start-guide.pdf) + +[AN1296: Application Development with Silicon Labs’ RTL Library](https://www.silabs.com/documents/public/application-notes/an1296-application-development-with-rtl-library.pdf) + +[Bluetooth Training](https://www.silabs.com/support/training/bluetooth) + +## Report Bugs & Get Support + +You are always encouraged and welcome to report any issues you found to us via [Silicon Labs Community](https://www.silabs.com/community). diff --git a/sonar-project.properties b/sonar-project.properties index 12cbd4b..9bbc7e0 100644 --- a/sonar-project.properties +++ b/sonar-project.properties @@ -1,26 +1,26 @@ - -sonar.host.url= http://sonarqube.silabs.net/ -# must be unique in a given SonarQube instance -sonar.projectKey=devs_identec_xg24_aoa_poc -sonar.cfamily.variants.names=locator_host,locator_ncp -sonar.cfamily.variants.dir = sonar-bw - -# we don't care which version, SQ is just too dumb to ignore python language when it sees (even if we try excluding it in sonar.exclusions) -sonar.python.version=3.9 - -# Path is relative to the sonar-project.properties file. Defaults to . -sonar.sources= \ - locator_host/, \ - locator_ncp/, - -sonar.inclusions= \ - locator_host/*.c, \ - locator_host/*.h, \ - locator_ncp/*.c, \ - locator_ncp/*.h, \ - locator_host/tools/mqtt_forwarder/*.py - -sonar.exclusions= \ - docs/**/*, \ - cicd/**/*, \ - **/gecko_sdk_4.4.1/**/* + +sonar.host.url= http://sonarqube.silabs.net/ +# must be unique in a given SonarQube instance +sonar.projectKey=devs_identec_xg24_aoa_poc +sonar.cfamily.variants.names=locator_host,locator_ncp +sonar.cfamily.variants.dir = sonar-bw + +# we don't care which version, SQ is just too dumb to ignore python language when it sees (even if we try excluding it in sonar.exclusions) +sonar.python.version=3.9 + +# Path is relative to the sonar-project.properties file. Defaults to . +sonar.sources= \ + locator_host/, \ + locator_ncp/, + +sonar.inclusions= \ + locator_host/*.c, \ + locator_host/*.h, \ + locator_ncp/*.c, \ + locator_ncp/*.h, \ + locator_host/tools/mqtt_forwarder/*.py + +sonar.exclusions= \ + docs/**/*, \ + cicd/**/*, \ + **/gecko_sdk_4.4.1/**/* diff --git a/tools/.clang-tidy b/tools/.clang-tidy index a764bc0..33711ca 100644 --- a/tools/.clang-tidy +++ b/tools/.clang-tidy @@ -1,50 +1,50 @@ -Checks: > - -*, - readability-identifier-naming, - readability-magic-numbers, - readability-braces-around-statements - -WarningsAsErrors: > - readability-identifier-naming, - readability-magic-numbers, - readability-braces-around-statements - -HeaderFilterRegex: '' -FormatStyle: none -InheritParentConfig: true -User: user -CheckOptions: - - key: readability-identifier-naming.VariableCase - value: lower_case - - key: readability-identifier-naming.GlobalConstantCase - value: UPPER_CASE - - key: readability-identifier-naming.GlobalConstantPrefix - value: SL_ - - key: readability-identifier-naming.ConstantCase - value: UPPER_CASE - - key: readability-identifier-naming.ConstantPrefix - value: SL_ - - key: readability-identifier-naming.EnumConstantCase - value: UPPER_CASE - - key: readability-identifier-naming.EnumConstantPrefix - value: SL_ - - key: readability-identifier-naming.EnumCase - value: lower_case - - key: readability-identifier-naming.EnumPrefix - value: sl_ - - key: readability-identifier-naming.FunctionIgnoredRegexp - value: 'sli_.*' - - key: readability-identifier-naming.FunctionCase - value: lower_case - - key: readability-identifier-naming.FunctionPrefix - value: 'sl_' - - key: readability-identifier-naming.StructCase - value: lower_case - - key: readability-identifier-naming.StructPrefix - value: 'sl_' - - key: readability-identifier-naming.StructMemberCase - value: lower_case - - key: readability-identifier-naming.TypedefCase - value: lower_case - - key: readability-identifier-naming.TypedefPrefix - value: 'sl_' +Checks: > + -*, + readability-identifier-naming, + readability-magic-numbers, + readability-braces-around-statements + +WarningsAsErrors: > + readability-identifier-naming, + readability-magic-numbers, + readability-braces-around-statements + +HeaderFilterRegex: '' +FormatStyle: none +InheritParentConfig: true +User: user +CheckOptions: + - key: readability-identifier-naming.VariableCase + value: lower_case + - key: readability-identifier-naming.GlobalConstantCase + value: UPPER_CASE + - key: readability-identifier-naming.GlobalConstantPrefix + value: SL_ + - key: readability-identifier-naming.ConstantCase + value: UPPER_CASE + - key: readability-identifier-naming.ConstantPrefix + value: SL_ + - key: readability-identifier-naming.EnumConstantCase + value: UPPER_CASE + - key: readability-identifier-naming.EnumConstantPrefix + value: SL_ + - key: readability-identifier-naming.EnumCase + value: lower_case + - key: readability-identifier-naming.EnumPrefix + value: sl_ + - key: readability-identifier-naming.FunctionIgnoredRegexp + value: 'sli_.*' + - key: readability-identifier-naming.FunctionCase + value: lower_case + - key: readability-identifier-naming.FunctionPrefix + value: 'sl_' + - key: readability-identifier-naming.StructCase + value: lower_case + - key: readability-identifier-naming.StructPrefix + value: 'sl_' + - key: readability-identifier-naming.StructMemberCase + value: lower_case + - key: readability-identifier-naming.TypedefCase + value: lower_case + - key: readability-identifier-naming.TypedefPrefix + value: 'sl_' diff --git a/tools/.codespell/.codespellrc b/tools/.codespell/.codespellrc index 5540960..1cd614f 100644 --- a/tools/.codespell/.codespellrc +++ b/tools/.codespell/.codespellrc @@ -1,10 +1,10 @@ -# See: https://github.com/codespell-project/codespell#using-a-config-file -[codespell] -# In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line). -# Or copy & paste the whole problematic line to 'exclude-file.txt' -ignore-words = ./tools/.codespell/ignore-words.txt -exclude-file = ./tools/.codespell/exclude-file.txt -check-filenames = -check-hidden = -count = -skip = .git,*.a, +# See: https://github.com/codespell-project/codespell#using-a-config-file +[codespell] +# In the event of a false positive, add the problematic word, in all lowercase, to 'ignore-words.txt' (one word per line). +# Or copy & paste the whole problematic line to 'exclude-file.txt' +ignore-words = ./tools/.codespell/ignore-words.txt +exclude-file = ./tools/.codespell/exclude-file.txt +check-filenames = +check-hidden = +count = +skip = .git,*.a, diff --git a/tools/.codespell/ignore-words.txt b/tools/.codespell/ignore-words.txt index 62fde74..68d03c7 100644 --- a/tools/.codespell/ignore-words.txt +++ b/tools/.codespell/ignore-words.txt @@ -1,2 +1,2 @@ -teh -foobar +teh +foobar diff --git a/tools/README.md b/tools/README.md index 149f295..28318a4 100644 --- a/tools/README.md +++ b/tools/README.md @@ -1,169 +1,169 @@ -![Silabs](https://img.shields.io/badge/CodingConventionTool-1.1-green) -![Silabs](https://img.shields.io/badge/precommit-2.17.0-green) -![Silabs](https://img.shields.io/badge/codespell-2.2.4-green) -![Silabs](https://img.shields.io/badge/uncrustify-0.72.0-green) -![Silabs](https://img.shields.io/badge/clang_tidy-14.0.0-green) -![Silabs](https://img.shields.io/badge/cppcheck-2.7-green) - -# Coding Convention Tool -This is a code formatter tool that helps ensure consistent coding style and detects common issues in source code files. It integrates with [pre-commit](https://pre-commit.com/), allowing you to automate code formatting and checks as part of your development workflow. - -## Features - -- Automatically fixes end-of-file issues. -- Removes trailing whitespace from lines. -- Identifies and suggests fixes for common spelling errors using [codespell](https://github.com/codespell-project/codespell). -- Formats code according to specified [Uncrustify](https://github.com/uncrustify/uncrustify) rules base on [Silabs's coding standard](https://stash.silabs.com/projects/WMN_DOCS/repos/docs_misc/browse/software/standards/coding-standard.md) -- Checks for identifiers naming style mismatch of function, definition, struct, variable using [clang-tidy](https://releases.llvm.org/14.0.0/tools/clang/tools/extra/docs/clang-tidy/index.htmlextensible) -- Checks code for potential errors and style issues using [cppcheck](https://cppcheck.sourceforge.io/). - -## Project Structure - -The following outlines the structure of the code formatter project, detailing the purpose of each file and directory. - -* **tools**: Contains all config file of codespell, clang-format, clang-tidy. - * **.codespell** - * **exclude-file.txt**: Contains lines to be excluded from Codespell checks. - * **ignore-words.txt**: Contains words to be ignored by Codespell to avoid false positives. - * **uncrustify.cfg**: Configuration file for Uncrustify, specifying the coding style and formatting rules. Base on [Uncrustify Project](https://confluence.silabs.com/display/DEVOPS/Uncrustify+Project) - * **.clang-tidy**: Configuration file for clang-tidy, specifying checks and options for static analysis. - -* **.pre-commit-config.yaml**: Configuration file for pre-commit, defining the hooks and their settings to be run before commits. -* **data_format_sample.c**: Sample C source file used for demonstrating the code formatter and static analysis tools. -* **README.md**: Documentation file providing an overview of the project, setup instructions, and usage guidelines. - -## Installation -### Ubuntu -Recommended operating system: WSL, Ubuntu 22.04. - -Ensure Python3 is installed on your system. Then, install pre-commit clang-format clang-tidy cppcheck by running: -``` -$ pip install pre-commit -$ sudo apt install uncrustify clang-tidy cppcheck -``` - -Recommended version: -- Codespell 2.2.4 -- Uncrustify 0.72.0 -- Clang tidy 14.0.0 -- Cppcheck 2.7 - -### Windows - -TBD - - -## Quick start - -Copy the folder ```tools``` and file ```.pre-commit-config.yaml``` to your repo. - -Run pre-commit install to install pre-commit into your git hooks. pre-commit will now run on every commit: - -```$ pre-commit install``` - -Staging files need formatting. For example: - -```$ git add file.c``` - -Run pre-commit hooks on a repository to check coding convention. - -```pre-commit run --all-files``` - -Or run pre-commit for a file: - -```pre-commit run --file ./file.c``` - -### Exclude Folder - -When using this tool, you may want to skip some folders. You can specify folders to exclude from formatting and checks by replacing the exclude regex pattern with the folders you want to skip. - -Here's how you can exclude folders ```build``` and ```gecko_sdk_xxx```using regex patterns in [.pre-commit-config.yaml](./.pre-commit-config.yaml) file: - -```yaml -exclude: .*/build/.*|.*/gecko_sdk.*/.* -``` - -### Exclude File, Ignore Words for Codespell - -When using Codespell, you may encounter false positives or want to exclude specific files or directories from being checked. Codespell provides configuration options to handle these scenarios. - -Here's an example of a codespell configuration file [.codespellrc](tools/.codespell/.codespellrc) - -``` -ignore-words = ./tools/.codespell/ignore-words.txt -exclude-file = ./tools/.codespell/exclude-file.txt -check-filenames = -check-hidden = -count = -skip = .git,*.a, -``` - -Explanation of Configuration Options - -* **[ignore-words](tools/.codespell/ignore-words.txt)** : This option points to a file containing words that should be ignored by Codespell. If you encounter a false positive, add the problematic word to ignore-words.txt. Ensure each word is in lowercase and on a new line. - -Example ignore-words.txt: - -``` -teh -foobar -``` -* **[exclude-file](tools/.codespell/exclude-file.txt)** : This option points to a file containing lines that should be excluded from spell-checking. If a specific line in your code is causing a false positive, copy and paste the entire line into exclude-file.txt. - -Example exclude-file.txt: -``` -This is a sample line that should be excluded. -``` -* **check-filenames**: Set this option to true if you want Codespell to check filenames for spelling errors. By default, this is empty (disabled). - -* **check-hidden**: Set this option to true if you want Codespell to check hidden files for spelling errors. By default, this is empty (disabled). - -* **count**: Set this option to true if you want Codespell to display the number of occurrences of each misspelled word. By default, this is empty (disabled). - -* **skip**: This option allows you to specify files or directories that Codespell should skip. You can list multiple entries separated by commas. For example, .git,*.a, will skip the .git directory and all files with the .a extension. - -### Uncrustify - -Automatic source code formatting follows [Silabs's coding standard](https://stash.silabs.com/projects/WMN_DOCS/repos/docs_misc/browse/software/standards/coding-standard.md) -The Uncrustify configuration file is located at [/tools/uncrustify.cfg](./tools/uncrustify.cfg). - -Base on the repo [/projects/WMN_TOOLS/repos/scripts/browse/uncrustify](https://stash.silabs.com/projects/WMN_TOOLS/repos/scripts/browse/uncrustify) - - -### Clang-Tidy - -**Checks for identifiers naming style mismatch** - -Clang-Tidy supports checking casing types (UPPER_CASE/lower_case) and prefixes of Function, Struct, Enum, Global Constant. -You can modify the prefix in the file [.clang-tidy](./tools/.clang-tidy). - -For example, config function with lower_case and prefix 'sl_' -``` - - key: readability-identifier-naming.FunctionCase - value: lower_case - - key: readability-identifier-naming.FunctionPrefix - value: 'sl_' -``` - -**Adding Extra Arguments** - -You may need to provide additional paths to header files or define macros for Clang-Tidy to ensure it correctly analyzes your code. This can be done using the ```--extra-arg``` option in the hook configuration. - -To add extra arguments to the clang-tidy hook, modify the args section of the hook configuration in your .pre-commit-config.yaml file. Here's an example of how to add extra arguments: - -```yaml -- repo: https://github.com/pocc/pre-commit-hooks - rev: v1.3.5 - hooks: - - id: clang-tidy - args: - - --config-file=./tools/.clang-tidy - - --use-color - - --extra-arg=-I/inc/ - - --extra-arg=-DMY_MACRO=1 -``` -In this example, we've added two extra arguments to Clang-Tidy: - -```-I/inc/```: Specifies an include directory where Clang-Tidy will look for header files. - -```-DMY_MACRO=1```: Defines a macro named MY_MACRO with the value 1 for use in the code analysis. +![Silabs](https://img.shields.io/badge/CodingConventionTool-1.1-green) +![Silabs](https://img.shields.io/badge/precommit-2.17.0-green) +![Silabs](https://img.shields.io/badge/codespell-2.2.4-green) +![Silabs](https://img.shields.io/badge/uncrustify-0.72.0-green) +![Silabs](https://img.shields.io/badge/clang_tidy-14.0.0-green) +![Silabs](https://img.shields.io/badge/cppcheck-2.7-green) + +# Coding Convention Tool +This is a code formatter tool that helps ensure consistent coding style and detects common issues in source code files. It integrates with [pre-commit](https://pre-commit.com/), allowing you to automate code formatting and checks as part of your development workflow. + +## Features + +- Automatically fixes end-of-file issues. +- Removes trailing whitespace from lines. +- Identifies and suggests fixes for common spelling errors using [codespell](https://github.com/codespell-project/codespell). +- Formats code according to specified [Uncrustify](https://github.com/uncrustify/uncrustify) rules base on [Silabs's coding standard](https://stash.silabs.com/projects/WMN_DOCS/repos/docs_misc/browse/software/standards/coding-standard.md) +- Checks for identifiers naming style mismatch of function, definition, struct, variable using [clang-tidy](https://releases.llvm.org/14.0.0/tools/clang/tools/extra/docs/clang-tidy/index.htmlextensible) +- Checks code for potential errors and style issues using [cppcheck](https://cppcheck.sourceforge.io/). + +## Project Structure + +The following outlines the structure of the code formatter project, detailing the purpose of each file and directory. + +* **tools**: Contains all config file of codespell, clang-format, clang-tidy. + * **.codespell** + * **exclude-file.txt**: Contains lines to be excluded from Codespell checks. + * **ignore-words.txt**: Contains words to be ignored by Codespell to avoid false positives. + * **uncrustify.cfg**: Configuration file for Uncrustify, specifying the coding style and formatting rules. Base on [Uncrustify Project](https://confluence.silabs.com/display/DEVOPS/Uncrustify+Project) + * **.clang-tidy**: Configuration file for clang-tidy, specifying checks and options for static analysis. + +* **.pre-commit-config.yaml**: Configuration file for pre-commit, defining the hooks and their settings to be run before commits. +* **data_format_sample.c**: Sample C source file used for demonstrating the code formatter and static analysis tools. +* **README.md**: Documentation file providing an overview of the project, setup instructions, and usage guidelines. + +## Installation +### Ubuntu +Recommended operating system: WSL, Ubuntu 22.04. + +Ensure Python3 is installed on your system. Then, install pre-commit clang-format clang-tidy cppcheck by running: +``` +$ pip install pre-commit +$ sudo apt install uncrustify clang-tidy cppcheck +``` + +Recommended version: +- Codespell 2.2.4 +- Uncrustify 0.72.0 +- Clang tidy 14.0.0 +- Cppcheck 2.7 + +### Windows + +TBD + + +## Quick start + +Copy the folder ```tools``` and file ```.pre-commit-config.yaml``` to your repo. + +Run pre-commit install to install pre-commit into your git hooks. pre-commit will now run on every commit: + +```$ pre-commit install``` + +Staging files need formatting. For example: + +```$ git add file.c``` + +Run pre-commit hooks on a repository to check coding convention. + +```pre-commit run --all-files``` + +Or run pre-commit for a file: + +```pre-commit run --file ./file.c``` + +### Exclude Folder + +When using this tool, you may want to skip some folders. You can specify folders to exclude from formatting and checks by replacing the exclude regex pattern with the folders you want to skip. + +Here's how you can exclude folders ```build``` and ```gecko_sdk_xxx```using regex patterns in [.pre-commit-config.yaml](./.pre-commit-config.yaml) file: + +```yaml +exclude: .*/build/.*|.*/gecko_sdk.*/.* +``` + +### Exclude File, Ignore Words for Codespell + +When using Codespell, you may encounter false positives or want to exclude specific files or directories from being checked. Codespell provides configuration options to handle these scenarios. + +Here's an example of a codespell configuration file [.codespellrc](tools/.codespell/.codespellrc) + +``` +ignore-words = ./tools/.codespell/ignore-words.txt +exclude-file = ./tools/.codespell/exclude-file.txt +check-filenames = +check-hidden = +count = +skip = .git,*.a, +``` + +Explanation of Configuration Options + +* **[ignore-words](tools/.codespell/ignore-words.txt)** : This option points to a file containing words that should be ignored by Codespell. If you encounter a false positive, add the problematic word to ignore-words.txt. Ensure each word is in lowercase and on a new line. + +Example ignore-words.txt: + +``` +teh +foobar +``` +* **[exclude-file](tools/.codespell/exclude-file.txt)** : This option points to a file containing lines that should be excluded from spell-checking. If a specific line in your code is causing a false positive, copy and paste the entire line into exclude-file.txt. + +Example exclude-file.txt: +``` +This is a sample line that should be excluded. +``` +* **check-filenames**: Set this option to true if you want Codespell to check filenames for spelling errors. By default, this is empty (disabled). + +* **check-hidden**: Set this option to true if you want Codespell to check hidden files for spelling errors. By default, this is empty (disabled). + +* **count**: Set this option to true if you want Codespell to display the number of occurrences of each misspelled word. By default, this is empty (disabled). + +* **skip**: This option allows you to specify files or directories that Codespell should skip. You can list multiple entries separated by commas. For example, .git,*.a, will skip the .git directory and all files with the .a extension. + +### Uncrustify + +Automatic source code formatting follows [Silabs's coding standard](https://stash.silabs.com/projects/WMN_DOCS/repos/docs_misc/browse/software/standards/coding-standard.md) +The Uncrustify configuration file is located at [/tools/uncrustify.cfg](./tools/uncrustify.cfg). + +Base on the repo [/projects/WMN_TOOLS/repos/scripts/browse/uncrustify](https://stash.silabs.com/projects/WMN_TOOLS/repos/scripts/browse/uncrustify) + + +### Clang-Tidy + +**Checks for identifiers naming style mismatch** + +Clang-Tidy supports checking casing types (UPPER_CASE/lower_case) and prefixes of Function, Struct, Enum, Global Constant. +You can modify the prefix in the file [.clang-tidy](./tools/.clang-tidy). + +For example, config function with lower_case and prefix 'sl_' +``` + - key: readability-identifier-naming.FunctionCase + value: lower_case + - key: readability-identifier-naming.FunctionPrefix + value: 'sl_' +``` + +**Adding Extra Arguments** + +You may need to provide additional paths to header files or define macros for Clang-Tidy to ensure it correctly analyzes your code. This can be done using the ```--extra-arg``` option in the hook configuration. + +To add extra arguments to the clang-tidy hook, modify the args section of the hook configuration in your .pre-commit-config.yaml file. Here's an example of how to add extra arguments: + +```yaml +- repo: https://github.com/pocc/pre-commit-hooks + rev: v1.3.5 + hooks: + - id: clang-tidy + args: + - --config-file=./tools/.clang-tidy + - --use-color + - --extra-arg=-I/inc/ + - --extra-arg=-DMY_MACRO=1 +``` +In this example, we've added two extra arguments to Clang-Tidy: + +```-I/inc/```: Specifies an include directory where Clang-Tidy will look for header files. + +```-DMY_MACRO=1```: Defines a macro named MY_MACRO with the value 1 for use in the code analysis. diff --git a/tools/uncrustify.cfg b/tools/uncrustify.cfg index 87bb119..b49726d 100644 --- a/tools/uncrustify.cfg +++ b/tools/uncrustify.cfg @@ -1,184 +1,184 @@ -# uncrustify.cfg version 1.0.0 -# SPDX-FileCopyrightText: Silicon Laboratories Inc. https://www.silabs.com -# SPDX-License-Identifier: Zlib - -tok_split_gte=false -utf8_byte=false -utf8_force=true -indent_cmt_with_tabs=false -indent_align_string=true -indent_braces=false -indent_braces_no_func=false -indent_braces_no_class=false -indent_braces_no_struct=false -indent_brace_parent=false -indent_namespace=false -indent_extern=false -indent_class=true -indent_class_colon=false -indent_else_if=false -indent_var_def_cont=false -indent_func_call_param=false -indent_func_def_param=false -indent_func_proto_param=false -indent_func_class_param=false -indent_func_ctor_var_param=false -indent_template_param=false -indent_func_param_double=false -indent_relative_single_line_comments=false -indent_col1_comment=false -indent_access_spec_body=false -indent_paren_nl=false -indent_comma_paren=false -indent_bool_paren=false -indent_first_bool_expr=false -indent_square_nl=false -indent_preserve_sql=false -indent_align_assign=true -sp_balance_nested_parens=false -align_keep_tabs=false -align_with_tabs=false -align_on_tabstop=false -align_number_left=false -align_func_params=false -align_same_func_call_params=false -align_var_def_colon=false -align_var_def_attribute=false -align_var_def_inline=false -align_right_cmt_mix=false -align_on_operator=false -align_mix_var_proto=false -align_single_line_func=false -align_single_line_brace=false -align_nl_cont=true -align_left_shift=true -align_oc_decl_colon=false -nl_collapse_empty_body=false -nl_assign_leave_one_liners=false -nl_class_leave_one_liners=false -nl_enum_leave_one_liners=false -nl_getset_leave_one_liners=false -nl_func_leave_one_liners=false -nl_if_leave_one_liners=false -nl_multi_line_cond=false -nl_multi_line_define=false -nl_before_case=false -nl_after_case=false -nl_after_return=false -nl_after_semicolon=false -nl_after_brace_open=false -nl_after_brace_open_cmt=false -nl_after_vbrace_open=false -nl_after_vbrace_open_empty=false -nl_after_brace_close=false -nl_after_vbrace_close=false -nl_define_macro=false -nl_squeeze_ifdef=false -nl_ds_struct_enum_cmt=false -nl_ds_struct_enum_close_brace=false -nl_create_if_one_liner=false -nl_create_for_one_liner=false -nl_create_while_one_liner=false -ls_for_split_full=false -ls_func_split_full=true -nl_after_multiline_comment=false -eat_blanks_after_open_brace=true -eat_blanks_before_close_brace=true -mod_full_brace_if_chain=false -mod_pawn_semicolon=false -mod_full_paren_if_bool=false -mod_remove_extra_semicolon=false -mod_sort_import=false -mod_sort_using=false -mod_sort_include=false -mod_move_case_break=false -mod_remove_empty_return=false -cmt_indent_multi=true -cmt_c_group=false -cmt_c_nl_start=false -cmt_c_nl_end=false -cmt_cpp_group=false -cmt_cpp_nl_start=false -cmt_cpp_nl_end=false -cmt_cpp_to_c=false -cmt_star_cont=false -cmt_multi_check_last=true -cmt_insert_before_preproc=false -pp_indent=ignore -pp_if_indent_code=false -input_tab_size=2 -indent_columns=2 -indent_label=0 -align_pp_define_span=0 -nl_start_of_file=remove -nl_end_of_file_min=1 -code_width=0 -nl_max=2 -nl_comment_func_def=1 -cmt_width=0 -utf8_bom=remove -indent_with_tabs=0 -sp_before_assign=add -sp_after_assign=add -sp_bool=add -sp_compare=add -sp_inside_paren=remove -sp_before_sparen=force -sp_paren_paren=ignore -sp_inside_sparen=ignore -sp_after_sparen=force -sp_before_square=remove -sp_before_squares=remove -sp_inside_square=remove -sp_after_comma=force -sp_before_comma=remove -sp_paren_comma=remove -sp_inside_braces=add -sp_inside_braces_empty=remove -sp_func_def_paren=remove -sp_inside_fparen=remove -sp_func_call_paren=remove -sp_func_call_paren_empty=remove -sp_else_brace=force -sp_brace_else=force -sp_sign=remove -sp_incdec=remove -sp_cmt_cpp_start=ignore -sp_endif_cmt=force -nl_end_of_file=add -nl_enum_brace=remove -nl_struct_brace=remove -nl_union_brace=remove -nl_for_brace=remove -nl_brace_finally=remove -nl_while_brace=remove -nl_do_brace=remove -nl_brace_while=remove -nl_switch_brace=remove -nl_if_brace=remove -nl_brace_else=remove -nl_elseif_brace=remove -nl_else_brace=remove -nl_fdef_brace=add -mod_full_brace_do=force -mod_full_brace_if=force -mod_full_brace_while=ignore -mod_full_brace_for=force -mod_full_brace_function=force -sp_cmt_cpp_doxygen=true -cmt_sp_after_star_cont=3 -align_keep_extra_space=True -align_var_def_star_style=1 -align_var_def_amp_style=1 -sp_after_type=ignore -pos_arith=lead -pos_bool=lead -pos_compare=lead -pos_conditional=lead -pos_comma=trail -sp_arith=add -sp_assign=add -sp_pp_concat=ignore -# Indent the 'case' label from the 'switch' header (coding standard §4.4.3) -# Note: Must come *after* the declaration of 'indent_columns'! -indent_switch_case=indent_columns +# uncrustify.cfg version 1.0.0 +# SPDX-FileCopyrightText: Silicon Laboratories Inc. https://www.silabs.com +# SPDX-License-Identifier: Zlib + +tok_split_gte=false +utf8_byte=false +utf8_force=true +indent_cmt_with_tabs=false +indent_align_string=true +indent_braces=false +indent_braces_no_func=false +indent_braces_no_class=false +indent_braces_no_struct=false +indent_brace_parent=false +indent_namespace=false +indent_extern=false +indent_class=true +indent_class_colon=false +indent_else_if=false +indent_var_def_cont=false +indent_func_call_param=false +indent_func_def_param=false +indent_func_proto_param=false +indent_func_class_param=false +indent_func_ctor_var_param=false +indent_template_param=false +indent_func_param_double=false +indent_relative_single_line_comments=false +indent_col1_comment=false +indent_access_spec_body=false +indent_paren_nl=false +indent_comma_paren=false +indent_bool_paren=false +indent_first_bool_expr=false +indent_square_nl=false +indent_preserve_sql=false +indent_align_assign=true +sp_balance_nested_parens=false +align_keep_tabs=false +align_with_tabs=false +align_on_tabstop=false +align_number_left=false +align_func_params=false +align_same_func_call_params=false +align_var_def_colon=false +align_var_def_attribute=false +align_var_def_inline=false +align_right_cmt_mix=false +align_on_operator=false +align_mix_var_proto=false +align_single_line_func=false +align_single_line_brace=false +align_nl_cont=true +align_left_shift=true +align_oc_decl_colon=false +nl_collapse_empty_body=false +nl_assign_leave_one_liners=false +nl_class_leave_one_liners=false +nl_enum_leave_one_liners=false +nl_getset_leave_one_liners=false +nl_func_leave_one_liners=false +nl_if_leave_one_liners=false +nl_multi_line_cond=false +nl_multi_line_define=false +nl_before_case=false +nl_after_case=false +nl_after_return=false +nl_after_semicolon=false +nl_after_brace_open=false +nl_after_brace_open_cmt=false +nl_after_vbrace_open=false +nl_after_vbrace_open_empty=false +nl_after_brace_close=false +nl_after_vbrace_close=false +nl_define_macro=false +nl_squeeze_ifdef=false +nl_ds_struct_enum_cmt=false +nl_ds_struct_enum_close_brace=false +nl_create_if_one_liner=false +nl_create_for_one_liner=false +nl_create_while_one_liner=false +ls_for_split_full=false +ls_func_split_full=true +nl_after_multiline_comment=false +eat_blanks_after_open_brace=true +eat_blanks_before_close_brace=true +mod_full_brace_if_chain=false +mod_pawn_semicolon=false +mod_full_paren_if_bool=false +mod_remove_extra_semicolon=false +mod_sort_import=false +mod_sort_using=false +mod_sort_include=false +mod_move_case_break=false +mod_remove_empty_return=false +cmt_indent_multi=true +cmt_c_group=false +cmt_c_nl_start=false +cmt_c_nl_end=false +cmt_cpp_group=false +cmt_cpp_nl_start=false +cmt_cpp_nl_end=false +cmt_cpp_to_c=false +cmt_star_cont=false +cmt_multi_check_last=true +cmt_insert_before_preproc=false +pp_indent=ignore +pp_if_indent_code=false +input_tab_size=2 +indent_columns=2 +indent_label=0 +align_pp_define_span=0 +nl_start_of_file=remove +nl_end_of_file_min=1 +code_width=0 +nl_max=2 +nl_comment_func_def=1 +cmt_width=0 +utf8_bom=remove +indent_with_tabs=0 +sp_before_assign=add +sp_after_assign=add +sp_bool=add +sp_compare=add +sp_inside_paren=remove +sp_before_sparen=force +sp_paren_paren=ignore +sp_inside_sparen=ignore +sp_after_sparen=force +sp_before_square=remove +sp_before_squares=remove +sp_inside_square=remove +sp_after_comma=force +sp_before_comma=remove +sp_paren_comma=remove +sp_inside_braces=add +sp_inside_braces_empty=remove +sp_func_def_paren=remove +sp_inside_fparen=remove +sp_func_call_paren=remove +sp_func_call_paren_empty=remove +sp_else_brace=force +sp_brace_else=force +sp_sign=remove +sp_incdec=remove +sp_cmt_cpp_start=ignore +sp_endif_cmt=force +nl_end_of_file=add +nl_enum_brace=remove +nl_struct_brace=remove +nl_union_brace=remove +nl_for_brace=remove +nl_brace_finally=remove +nl_while_brace=remove +nl_do_brace=remove +nl_brace_while=remove +nl_switch_brace=remove +nl_if_brace=remove +nl_brace_else=remove +nl_elseif_brace=remove +nl_else_brace=remove +nl_fdef_brace=add +mod_full_brace_do=force +mod_full_brace_if=force +mod_full_brace_while=ignore +mod_full_brace_for=force +mod_full_brace_function=force +sp_cmt_cpp_doxygen=true +cmt_sp_after_star_cont=3 +align_keep_extra_space=True +align_var_def_star_style=1 +align_var_def_amp_style=1 +sp_after_type=ignore +pos_arith=lead +pos_bool=lead +pos_compare=lead +pos_conditional=lead +pos_comma=trail +sp_arith=add +sp_assign=add +sp_pp_concat=ignore +# Indent the 'case' label from the 'switch' header (coding standard §4.4.3) +# Note: Must come *after* the declaration of 'indent_columns'! +indent_switch_case=indent_columns